diff --git a/stand/arm/Makefile b/stand/arm/Makefile deleted file mode 100644 index 7ff21abcc9b..00000000000 --- a/stand/arm/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# $FreeBSD$ - -NO_OBJ=t - -SUBDIR= uboot - -.include diff --git a/stand/arm/Makefile.inc b/stand/arm/Makefile.inc deleted file mode 100644 index 265f86d1ed5..00000000000 --- a/stand/arm/Makefile.inc +++ /dev/null @@ -1,3 +0,0 @@ -# $FreeBSD$ - -.include "../Makefile.inc" diff --git a/stand/arm/uboot/Makefile b/stand/arm/uboot/Makefile deleted file mode 100644 index 0c906c99ee6..00000000000 --- a/stand/arm/uboot/Makefile +++ /dev/null @@ -1,68 +0,0 @@ -# $FreeBSD$ - -LOADER_UFS_SUPPORT?= yes -LOADER_CD9660_SUPPORT?= no -LOADER_MSDOS_SUPPORT?= no -LOADER_EXT2FS_SUPPORT?= no -LOADER_NET_SUPPORT?= yes -LOADER_NFS_SUPPORT?= yes -LOADER_TFTP_SUPPORT?= no -LOADER_GZIP_SUPPORT?= no -LOADER_BZIP2_SUPPORT?= no - -.include - -FILES+= ubldr ubldr.bin - -NEWVERSWHAT= "U-Boot loader" ${MACHINE_ARCH} -INSTALLFLAGS= -b -WARNS?= 1 -# Address at which ubldr will be loaded. -# This varies for different boards and SOCs. -UBLDR_LOADADDR?= 0x1000000 - -# Architecture-specific loader code -SRCS= start.S conf.c self_reloc.c vers.c - -.if ${COMPILER_TYPE} == "gcc" && ${COMPILER_VERSION} > 40201 -CWARNFLAGS.self_reloc.c+= -Wno-error=maybe-uninitialized -.endif - -HELP_FILES= ${.CURDIR}/help.uboot ${BOOTSRC}/fdt/help.fdt - -# Always add MI sources -.include "${BOOTSRC}/loader.mk" - -LDFLAGS= -nostdlib -static -T ${.CURDIR}/ldscript.${MACHINE_CPUARCH} -LDFLAGS+= -Wl,-znotext - -# Pull in common loader code -.include "${BOOTSRC}/uboot.mk" - -CFLAGS+= -fPIC - -DPADD= ${LDR_INTERP} ${LIBUBOOT} ${LIBFDT} ${LIBUBOOT_FDT} ${LIBSA} -LDADD= ${LDR_INTERP} ${LIBUBOOT} ${LIBFDT} ${LIBUBOOT_FDT} ${LIBSA} - -OBJS+= ${SRCS:N*.h:R:S/$/.o/g} - -ldscript.abs: - echo "UBLDR_LOADADDR = ${UBLDR_LOADADDR};" >${.TARGET} - -ldscript.pie: - echo "UBLDR_LOADADDR = 0;" >${.TARGET} - -ubldr: ${OBJS} ldscript.abs ${.CURDIR}/ldscript.${MACHINE_CPUARCH} ${DPADD} - ${CC} ${CFLAGS} -T ldscript.abs ${LDFLAGS} \ - -o ${.TARGET} ${OBJS} ${LDADD} - -ubldr.pie: ${OBJS} ldscript.pie ${.CURDIR}/ldscript.${MACHINE_CPUARCH} ${DPADD} - ${CC} ${CFLAGS} -T ldscript.pie ${LDFLAGS} -pie -Wl,-Bsymbolic \ - -o ${.TARGET} ${OBJS} ${LDADD} - -ubldr.bin: ubldr.pie - ${OBJCOPY} -S -O binary ubldr.pie ${.TARGET} - -CLEANFILES+= ldscript.abs ldscript.pie ubldr ubldr.pie ubldr.bin - -.include diff --git a/stand/arm/uboot/conf.c b/stand/arm/uboot/conf.c deleted file mode 100644 index 777a7b20340..00000000000 --- a/stand/arm/uboot/conf.c +++ /dev/null @@ -1,97 +0,0 @@ -/*- - * Copyright (c) 2008 Semihalf, Rafal Jaworowski - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - */ - -#include -__FBSDID("$FreeBSD$"); - -#include -#include "bootstrap.h" -#include "libuboot.h" - -#if defined(LOADER_NET_SUPPORT) -#include "dev_net.h" -#endif - -/* Make sure we have an explicit reference to exit so libsa's panic pulls in the MD exit */ -void (*exitfn)(int) = exit; - -struct devsw *devsw[] = { -#if defined(LOADER_DISK_SUPPORT) || defined(LOADER_CD9660_SUPPORT) - &uboot_storage, -#endif -#if defined(LOADER_NET_SUPPORT) - &netdev, -#endif - NULL -}; - -struct fs_ops *file_system[] = { -#if defined(LOADER_UFS_SUPPORT) - &ufs_fsops, -#endif -#if defined(LOADER_CD9660_SUPPORT) - &cd9660_fsops, -#endif -#if defined(LOADER_EXT2FS_SUPPORT) - &ext2fs_fsops, -#endif -#if defined(LOADER_NANDFS_SUPPORT) - &nandfs_fsops, -#endif -#if defined(LOADER_NFS_SUPPORT) - &nfs_fsops, -#endif -#if defined(LOADER_TFTP_SUPPORT) - &tftp_fsops, -#endif -#if defined(LOADER_GZIP_SUPPORT) - &gzipfs_fsops, -#endif -#if defined(LOADER_BZIP2_SUPPORT) - &bzipfs_fsops, -#endif - NULL -}; - -struct netif_driver *netif_drivers[] = { -#if defined(LOADER_NET_SUPPORT) - &uboot_net, -#endif - NULL, -}; - -struct file_format *file_formats[] = { - &uboot_elf, - NULL -}; - -extern struct console uboot_console; - -struct console *consoles[] = { - &uboot_console, - NULL -}; diff --git a/stand/arm/uboot/help.uboot b/stand/arm/uboot/help.uboot deleted file mode 100644 index c1574af9271..00000000000 --- a/stand/arm/uboot/help.uboot +++ /dev/null @@ -1,27 +0,0 @@ -$FreeBSD$ - -############################################################################### -# Tubenv DShow or import U-Boot environment variables - - ubenv [varname ...] - - Display U-Boot environment variables, or import them into the - loader environment (which makes them available in the kernel). - -############################################################################### -# Tubenv Simport DImport U-Boot env vars - - ubenv import [varname ...] - - If no variable names are specified, all U-Boot environment - variables are imported. Each variable is prefixed with "uboot." - to avoid any possible conflicts with loader or kernel variables. - -############################################################################### -# Tubenv Sshow DShow U-Boot env vars - - ubenv show [varname ...] - - If no variable names are specified, all U-Boot environment - variables are shown. - diff --git a/stand/arm/uboot/ldscript.arm b/stand/arm/uboot/ldscript.arm deleted file mode 100644 index b768e00f39a..00000000000 --- a/stand/arm/uboot/ldscript.arm +++ /dev/null @@ -1,134 +0,0 @@ -/* $FreeBSD$ */ - -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = UBLDR_LOADADDR + SIZEOF_HEADERS; - . = ALIGN(8); - .text : - { - *(.text) - /* .gnu.warning sections are handled specially by elf32.em. */ - *(.gnu.warning) - *(.gnu.linkonce.t*) - } =0 - _etext = .; - PROVIDE (etext = .); - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .gnu.version : { *(.gnu.version) } - .gnu.version_d : { *(.gnu.version_d) } - .gnu.version_r : { *(.gnu.version_r) } - .rela.text : - { *(.rela.text) *(.rela.gnu.linkonce.t*) } - .rela.data : - { *(.rela.data) *(.rela.gnu.linkonce.d*) } - .rela.rodata : - { *(.rela.rodata) *(.rela.gnu.linkonce.r*) } - .rela.got : { *(.rela.got) } - .rela.got1 : { *(.rela.got1) } - .rela.got2 : { *(.rela.got2) } - .dynamic : { *(.dynamic) } - PROVIDE (_GOT_START_ = .); - .got : { *(.got) } - .got.plt : { *(.got.plt) } - PROVIDE (_GOT_END_ = .); - .rela.ctors : { *(.rela.ctors) } - .rela.dtors : { *(.rela.dtors) } - .rela.init : { *(.rela.init) } - .rela.fini : { *(.rela.fini) } - .rela.bss : { *(.rela.bss) } - .rela.plt : { *(.rela.plt) } - .rela.sdata : { *(.rela.sdata) } - .rela.sbss : { *(.rela.sbss) } - .rela.sdata2 : { *(.rela.sdata2) } - .rela.sbss2 : { *(.rela.sbss2) } - .init : { *(.init) } =0 - .fini : { *(.fini) } =0 - .rodata : { *(.rodata) *(.gnu.linkonce.r*) } - .rodata1 : { *(.rodata1) } - .sdata2 : { *(.sdata2) } - .sbss2 : { *(.sbss2) } - /* Adjust the address for the data segment to the doubleword boundary. */ - . = ALIGN(8); - .data : - { - *(.data) - *(.gnu.linkonce.d*) - CONSTRUCTORS - } - .data1 : { *(.data1) } - .got1 : { *(.got1) } - /* Put .ctors and .dtors next to the .got2 section, so that the pointers - get relocated with -mrelocatable. Also put in the .fixup pointers. - The current compiler no longer needs this, but keep it around for 2.7.2 */ - PROVIDE (_GOT2_START_ = .); - .got2 : { *(.got2) } - PROVIDE (__CTOR_LIST__ = .); - .ctors : { *(.ctors) } - PROVIDE (__CTOR_END__ = .); - PROVIDE (__DTOR_LIST__ = .); - .dtors : { *(.dtors) } - PROVIDE (__DTOR_END__ = .); - PROVIDE (_FIXUP_START_ = .); - .fixup : { *(.fixup) } - PROVIDE (_FIXUP_END_ = .); - PROVIDE (_GOT2_END_ = .); - /* We want the small data sections together, so single-instruction offsets - can access them all, and initialized data all before uninitialized, so - we can shorten the on-disk segment size. */ - .sdata : { *(.sdata) } - _edata = .; - PROVIDE (edata = .); - .sbss : - { - PROVIDE (__sbss_start = .); - *(.sbss) - *(.scommon) - *(.dynsbss) - PROVIDE (__sbss_end = .); - } - .plt : { *(.plt) } - .bss : - { - PROVIDE (__bss_start = .); - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); - /* Stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - /* DWARF debug sections. - Symbols in the DWARF debugging sections are relative to the beginning - of the section so we begin them at 0. */ - /* DWARF 1 */ - .debug 0 : { *(.debug) } - .line 0 : { *(.line) } - /* GNU DWARF 1 extensions */ - .debug_srcinfo 0 : { *(.debug_srcinfo) } - .debug_sfnames 0 : { *(.debug_sfnames) } - /* DWARF 1.1 and DWARF 2 */ - .debug_aranges 0 : { *(.debug_aranges) } - .debug_pubnames 0 : { *(.debug_pubnames) } - /* DWARF 2 */ - .debug_info 0 : { *(.debug_info) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_line 0 : { *(.debug_line) } - .debug_frame 0 : { *(.debug_frame) } - .debug_str 0 : { *(.debug_str) } - .debug_loc 0 : { *(.debug_loc) } - .debug_macinfo 0 : { *(.debug_macinfo) } - /* SGI/MIPS DWARF 2 extensions */ - .debug_weaknames 0 : { *(.debug_weaknames) } - .debug_funcnames 0 : { *(.debug_funcnames) } - .debug_typenames 0 : { *(.debug_typenames) } - .debug_varnames 0 : { *(.debug_varnames) } - /* These must appear regardless of . */ -} diff --git a/stand/arm/uboot/start.S b/stand/arm/uboot/start.S deleted file mode 100644 index ede6a620e08..00000000000 --- a/stand/arm/uboot/start.S +++ /dev/null @@ -1,145 +0,0 @@ -/*- - * Copyright (c) 2008 Semihalf, Rafal Czubak - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * $FreeBSD$ - */ - -#include -#include - - .text - .extern _C_LABEL(self_reloc), _C_LABEL(main) - .weak _DYNAMIC - -/* - * Entry point to the loader that U-Boot passes control to. - */ - .globl _start -_start: - -#ifdef _ARM_ARCH_6 - mrc p15, 0, ip, c1, c0, 0 - orr ip, ip, #(CPU_CONTROL_UNAL_ENABLE) - orr ip, ip, #(CPU_CONTROL_AFLT_ENABLE) - mcr p15, 0, ip, c1, c0, 0 -#endif - - /* Save the arguments and return register before calling self_reloc */ - push {r0, r1, r9, lr} - - /* - * Do self-relocation when the weak external symbol _DYNAMIC is non-NULL. - * When linked as a dynamic relocatable file, the linker automatically - * defines _DYNAMIC with a value that is the offset of the dynamic - * relocation info section. - * Note that we're still on u-boot's stack here, but the self_reloc - * code uses only a couple dozen bytes of stack space. - */ - adr ip, .here_off /* .here_off is a symbol whose value */ - ldr r0, [ip] /* is its own offset in the text seg. */ - sub r0, ip, r0 /* Get its pc-relative address and */ - ldr r1, .dynamic_off /* subtract its value and we get */ - teq r1, #0 /* r0 = physaddr we were loaded at. */ - addne r1, r1, r0 /* r1 = dynamic section physaddr. */ - blne _C_LABEL(self_reloc) /* Do reloc if _DYNAMIC is non-NULL. */ - - /* Restore saved arguments */ - pop {r0, r1, r9, lr} - - /* Hint where to look for the API signature */ - ldr ip, =uboot_address - str sp, [ip] - - /* Save U-Boot's r8 and r9 for syscall trampoline */ - ldr ip, =saved_regs - str r8, [ip, #0] /* old gd pointer (use to hold lr) */ - str r9, [ip, #4] /* new gd pointer */ - - /* - * Start loader. Save return address first (r8 is available from - * trampoline save). - */ - mov r8, lr - bl main - mov lr, r8 - - /* Restore U-Boot environment */ - ldr ip, =saved_regs - ldr r8, [ip, #0] - ldr r9, [ip, #4] - mov pc, lr - - /* - * Data for self-relocation, in the text segment for pc-rel access. - */ -.here_off: - .word . -.dynamic_off: - .word _DYNAMIC - -/* - * syscall() - */ -ENTRY(syscall) - /* Save caller's lr, r8 and r9 */ - ldr ip, =saved_regs - str r8, [ip, #8] - str r9, [ip, #12] - str lr, [ip, #16] - /* Restore U-Boot's r8 and r9 */ - ldr r8, [ip, #0] - ldr r9, [ip, #4] - /* Call into U-Boot */ - ldr lr, =return_from_syscall - ldr ip, =syscall_ptr - ldr pc, [ip] -return_from_syscall: - /* Restore loader's r8, r9 and lr */ - ldr ip, =saved_regs - ldr lr, [ip, #16] - ldr r9, [ip, #12] - ldr r8, [ip, #8] - /* Return to caller */ - mov pc, lr - -/* - * Data section - */ - .data - .align 4 - .globl syscall_ptr -syscall_ptr: - .long 0 - - .globl uboot_address -uboot_address: - .long 0 - -saved_regs: - .long 0 /* U-Boot's r8 */ - .long 0 /* U-Boot's r9 */ - .long 0 /* Loader's r8 */ - .long 0 /* Loader's r9 */ - .long 0 /* Loader's lr */ diff --git a/stand/arm/uboot/version b/stand/arm/uboot/version deleted file mode 100644 index 486c4125cc0..00000000000 --- a/stand/arm/uboot/version +++ /dev/null @@ -1,9 +0,0 @@ -$FreeBSD$ - -NOTE ANY CHANGES YOU MAKE TO THE BOOTBLOCKS HERE. The format of this -file is important. Make sure the current version number is on line 6. - -1.2: Extended with NAND FS support. -1.1: Flattened Device Tree blob support. -1.0: Added storage support. Booting from HDD, USB, etc. is now possible. -0.5: Initial U-Boot/arm version (netbooting only). diff --git a/stand/efi/boot1/Makefile.fat b/stand/efi/boot1/Makefile.fat deleted file mode 100644 index 1d40fa8ab54..00000000000 --- a/stand/efi/boot1/Makefile.fat +++ /dev/null @@ -1,4 +0,0 @@ -# This file autogenerated by generate-fat.sh - DO NOT EDIT -# $FreeBSD$ -BOOT1_OFFSET=0x2d -BOOT1_MAXSIZE=393216 diff --git a/stand/efi/boot1/fat-amd64.tmpl.xz b/stand/efi/boot1/fat-amd64.tmpl.xz deleted file mode 100644 index fe68cd8c255..00000000000 Binary files a/stand/efi/boot1/fat-amd64.tmpl.xz and /dev/null differ diff --git a/stand/efi/boot1/fat-arm.tmpl.xz b/stand/efi/boot1/fat-arm.tmpl.xz deleted file mode 100644 index d8fea415067..00000000000 Binary files a/stand/efi/boot1/fat-arm.tmpl.xz and /dev/null differ diff --git a/stand/efi/boot1/fat-arm64.tmpl.xz b/stand/efi/boot1/fat-arm64.tmpl.xz deleted file mode 100644 index 9e9fea278e4..00000000000 Binary files a/stand/efi/boot1/fat-arm64.tmpl.xz and /dev/null differ diff --git a/stand/efi/boot1/fat-i386.tmpl.xz b/stand/efi/boot1/fat-i386.tmpl.xz deleted file mode 100644 index d576a7bcb96..00000000000 Binary files a/stand/efi/boot1/fat-i386.tmpl.xz and /dev/null differ diff --git a/stand/efi/boot1/generate-fat.sh b/stand/efi/boot1/generate-fat.sh deleted file mode 100755 index a4389f98074..00000000000 --- a/stand/efi/boot1/generate-fat.sh +++ /dev/null @@ -1,79 +0,0 @@ -#!/bin/sh - -# This script generates the dummy FAT filesystem used for the EFI boot -# blocks. It uses newfs_msdos to generate a template filesystem with the -# relevant interesting files. These are then found by grep, and the offsets -# written to a Makefile snippet. -# -# Because it requires root, and because it is overkill, we do not -# do this as part of the normal build. If makefs(8) grows workable FAT -# support, this should be revisited. - -# $FreeBSD$ - -FAT_SIZE=1600 #Size in 512-byte blocks of the produced image - -BOOT1_OFFSET=2d -BOOT1_SIZE=384k - -if [ $(id -u) != 0 ]; then - echo "${0##*/}: must run as root" >&2 - exit 1 -fi - -# Record maximum boot1 size in bytes -case $BOOT1_SIZE in -*k) - BOOT1_MAXSIZE=$(expr ${BOOT1_SIZE%k} '*' 1024) - ;; -*) - BOOT1_MAXSIZE=$BOOT1_SIZE - ;; -esac - -echo '# This file autogenerated by generate-fat.sh - DO NOT EDIT' > Makefile.fat -echo "# \$FreeBSD\$" >> Makefile.fat -echo "BOOT1_OFFSET=0x$BOOT1_OFFSET" >> Makefile.fat -echo "BOOT1_MAXSIZE=$BOOT1_MAXSIZE" >> Makefile.fat - -while read ARCH FILENAME; do - # Generate 800K FAT image - OUTPUT_FILE=fat-${ARCH}.tmpl - - dd if=/dev/zero of=$OUTPUT_FILE bs=512 count=$FAT_SIZE - DEVICE=`mdconfig -a -f $OUTPUT_FILE` - newfs_msdos -F 12 -L EFISYS $DEVICE - mkdir stub - mount -t msdosfs /dev/$DEVICE stub - - # Create and bless a directory for the boot loader - mkdir -p stub/efi/boot - - # Make a dummy file for boot1 - echo 'Boot1 START' | dd of=stub/efi/boot/$FILENAME cbs=$BOOT1_SIZE count=1 conv=block - # Provide a fallback startup.nsh - echo $FILENAME > stub/efi/boot/startup.nsh - - umount stub - mdconfig -d -u $DEVICE - rmdir stub - - # Locate the offset of the fake file - OFFSET=$(hd $OUTPUT_FILE | grep 'Boot1 START' | cut -f 1 -d ' ') - - # Convert to number of blocks - OFFSET=$(echo 0x$OFFSET | awk '{printf("%x\n",$1/512);}') - - # Validate the offset - if [ $OFFSET != $BOOT1_OFFSET ]; then - echo "Incorrect offset $OFFSET != $BOOT1_OFFSET" >&2 - exit 1 - fi - - xz -f $OUTPUT_FILE -done < -__FBSDID("$FreeBSD: stable/11/stand/efi/loader/arch/i386/efimd.c 339210 2018-10-05 21:10:03Z jhb $"); - -#include - -#include -#include - -#include -#include - -#define EFI_INTEL_FPSWA \ - {0xc41b6531,0x97b9,0x11d3,{0x9a,0x29,0x00,0x90,0x27,0x3f,0xc1,0x4d}} - -static EFI_GUID fpswa_guid = EFI_INTEL_FPSWA; - -/* DIG64 Headless Console & Debug Port Table. */ -#define HCDP_TABLE_GUID \ - {0xf951938d,0x620b,0x42ef,{0x82,0x79,0xa8,0x4b,0x79,0x61,0x78,0x98}} - -static EFI_GUID hcdp_guid = HCDP_TABLE_GUID; - -static UINTN mapkey; - -int ldr_bootinfo(struct bootinfo *, uint64_t *); -int ldr_enter(const char *); - -static uint64_t -ldr_alloc(vm_offset_t va) -{ - - return (0); -} - -int -ldr_bootinfo(struct bootinfo *bi, uint64_t *bi_addr) -{ - VOID *fpswa; - EFI_MEMORY_DESCRIPTOR *mm; - EFI_PHYSICAL_ADDRESS addr; - EFI_HANDLE handle; - EFI_STATUS status; - size_t bisz; - UINTN mmsz, pages, sz; - UINT32 mmver; - - bi->bi_systab = (uintptr_t)ST; - bi->bi_hcdp = (uintptr_t)efi_get_table(&hcdp_guid); - - sz = sizeof(EFI_HANDLE); - status = BS->LocateHandle(ByProtocol, &fpswa_guid, 0, &sz, &handle); - if (status == 0) - status = BS->HandleProtocol(handle, &fpswa_guid, &fpswa); - bi->bi_fpswa = (status == 0) ? (uintptr_t)fpswa : 0; - - bisz = (sizeof(struct bootinfo) + 0x0f) & ~0x0f; - - /* - * Allocate enough pages to hold the bootinfo block and the memory - * map EFI will return to us. The memory map has an unknown size, - * so we have to determine that first. Note that the AllocatePages - * call can itself modify the memory map, so we have to take that - * into account as well. The changes to the memory map are caused - * by splitting a range of free memory into two (AFAICT), so that - * one is marked as being loader data. - */ - sz = 0; - BS->GetMemoryMap(&sz, NULL, &mapkey, &mmsz, &mmver); - sz += mmsz; - sz = (sz + 15) & ~15; - pages = EFI_SIZE_TO_PAGES(sz + bisz); - status = BS->AllocatePages(AllocateAnyPages, EfiLoaderData, pages, - &addr); - if (EFI_ERROR(status)) { - printf("%s: AllocatePages() returned 0x%lx\n", __func__, - (long)status); - return (ENOMEM); - } - - /* - * Read the memory map and stash it after bootinfo. Align the - * memory map on a 16-byte boundary (the bootinfo block is page - * aligned). - */ - *bi_addr = addr; - mm = (void *)(uintptr_t)(addr + bisz); - sz = (EFI_PAGE_SIZE * pages) - bisz; - status = BS->GetMemoryMap(&sz, mm, &mapkey, &mmsz, &mmver); - if (EFI_ERROR(status)) { - printf("%s: GetMemoryMap() returned 0x%lx\n", __func__, - (long)status); - return (EINVAL); - } - bi->bi_memmap = (uintptr_t)mm; - bi->bi_memmap_size = sz; - bi->bi_memdesc_size = mmsz; - bi->bi_memdesc_version = mmver; - - bcopy(bi, (void *)(uintptr_t)(*bi_addr), sizeof(*bi)); - return (0); -} - -int -ldr_enter(const char *kernel) -{ - EFI_STATUS status; - - status = BS->ExitBootServices(IH, mapkey); - if (EFI_ERROR(status)) { - printf("%s: ExitBootServices() returned 0x%lx\n", __func__, - (long)status); - return (EINVAL); - } - - return (0); -} diff --git a/stand/i386/btx/lib/btxsys.s b/stand/i386/btx/lib/btxsys.s deleted file mode 100644 index 9c77b4295e7..00000000000 --- a/stand/i386/btx/lib/btxsys.s +++ /dev/null @@ -1,40 +0,0 @@ -# -# Copyright (c) 1998 Robert Nordier -# All rights reserved. -# -# Redistribution and use in source and binary forms are freely -# permitted provided that the above copyright notice and this -# paragraph and the following disclaimer are duplicated in all -# such forms. -# -# This software is provided "AS IS" and without any express or -# implied warranties, including, without limitation, the implied -# warranties of merchantability and fitness for a particular -# purpose. -# - -# $FreeBSD$ - -# -# BTX system calls. -# - -# -# Globals. -# - .global __exit - .global __exec -# -# Constants. -# - .set INT_SYS,0x30 # Interrupt number -# -# System call: exit -# -__exit: xorl %eax,%eax # BTX system - int $INT_SYS # call 0x0 -# -# System call: exec -# -__exec: movl $0x1,%eax # BTX system - int $INT_SYS # call 0x1 diff --git a/stand/i386/btx/lib/btxv86.s b/stand/i386/btx/lib/btxv86.s deleted file mode 100644 index f4d4dd0a3b2..00000000000 --- a/stand/i386/btx/lib/btxv86.s +++ /dev/null @@ -1,85 +0,0 @@ -# -# Copyright (c) 1998 Robert Nordier -# All rights reserved. -# -# Redistribution and use in source and binary forms are freely -# permitted provided that the above copyright notice and this -# paragraph and the following disclaimer are duplicated in all -# such forms. -# -# This software is provided "AS IS" and without any express or -# implied warranties, including, without limitation, the implied -# warranties of merchantability and fitness for a particular -# purpose. -# - -# $FreeBSD: stable/11/stand/i386/btx/lib/btxv86.s 50477 1999-08-28 01:08:13Z peter $ - -# -# BTX V86 interface. -# - -# -# Globals. -# - .global __v86int -# -# Fields in V86 interface structure. -# - .set V86_CTL,0x0 # Control flags - .set V86_ADDR,0x4 # Int number/address - .set V86_ES,0x8 # V86 ES - .set V86_DS,0xc # V86 DS - .set V86_FS,0x10 # V86 FS - .set V86_GS,0x14 # V86 GS - .set V86_EAX,0x18 # V86 EAX - .set V86_ECX,0x1c # V86 ECX - .set V86_EDX,0x20 # V86 EDX - .set V86_EBX,0x24 # V86 EBX - .set V86_EFL,0x28 # V86 eflags - .set V86_EBP,0x2c # V86 EBP - .set V86_ESI,0x30 # V86 ESI - .set V86_EDI,0x34 # V86 EDI -# -# Other constants. -# - .set INT_V86,0x31 # Interrupt number - .set SIZ_V86,0x38 # Size of V86 structure -# -# V86 interface function. -# -__v86int: popl __v86ret # Save return address - pushl $__v86 # Push pointer - call __v86_swap # Load V86 registers - int $INT_V86 # To BTX - call __v86_swap # Load user registers - addl $0x4,%esp # Discard pointer - pushl __v86ret # Restore return address - ret # To user -# -# Swap V86 and user registers. -# -__v86_swap: xchgl %ebp,0x4(%esp,1) # Swap pointer, EBP - xchgl %eax,V86_EAX(%ebp) # Swap EAX - xchgl %ecx,V86_ECX(%ebp) # Swap ECX - xchgl %edx,V86_EDX(%ebp) # Swap EDX - xchgl %ebx,V86_EBX(%ebp) # Swap EBX - pushl %eax # Save - pushf # Put eflags - popl %eax # in EAX - xchgl %eax,V86_EFL(%ebp) # Swap - pushl %eax # Put EAX - popf # in eflags - movl 0x8(%esp,1),%eax # Load EBP - xchgl %eax,V86_EBP(%ebp) # Swap - movl %eax,0x8(%esp,1) # Save EBP - popl %eax # Restore - xchgl %esi,V86_ESI(%ebp) # Swap ESI - xchgl %edi,V86_EDI(%ebp) # Swap EDI - xchgl %ebp,0x4(%esp,1) # Swap pointer, EBP - ret # To caller -# -# V86 interface structure. -# - .comm __v86,SIZ_V86 - .comm __v86ret,4 diff --git a/stand/i386/libi386/pxetramp.s b/stand/i386/libi386/pxetramp.s deleted file mode 100644 index 6b9b0b38c00..00000000000 --- a/stand/i386/libi386/pxetramp.s +++ /dev/null @@ -1,38 +0,0 @@ -# -# Copyright (c) 2000 Peter Wemm -# All rights reserved. -# -# Redistribution and use in source and binary forms are freely -# permitted provided that the above copyright notice and this -# paragraph and the following disclaimer are duplicated in all -# such forms. -# -# This software is provided "AS IS" and without any express or -# implied warranties, including, without limitation, the implied -# warranties of merchantability and fitness for a particular -# purpose. -# -# $FreeBSD: stable/11/stand/i386/libi386/pxetramp.s 84461 2001-10-04 10:18:00Z jhb $ - -# ph33r this - - .globl __bangpxeentry, __bangpxeseg, __bangpxeoff - .globl __pxenventry, __pxenvseg, __pxenvoff - - .code16 - .p2align 4,0x90 -__bangpxeentry: - push %dx # seg:data - push %ax # off:data - push %bx # int16 func - .byte 0x9a # far call -__bangpxeoff: .word 0x0000 # offset -__bangpxeseg: .word 0x0000 # segment - add $6, %sp # restore stack - .byte 0xcb # to vm86int -# -__pxenventry: - .byte 0x9a # far call -__pxenvoff: .word 0x0000 # offset -__pxenvseg: .word 0x0000 # segment - .byte 0xcb # to vm86int diff --git a/stand/i386/mbr/mbr.s b/stand/i386/mbr/mbr.s deleted file mode 100644 index 3cfc20dd58e..00000000000 --- a/stand/i386/mbr/mbr.s +++ /dev/null @@ -1,157 +0,0 @@ -# -# Copyright (c) 1999 Robert Nordier -# All rights reserved. -# -# Redistribution and use in source and binary forms are freely -# permitted provided that the above copyright notice and this -# paragraph and the following disclaimer are duplicated in all -# such forms. -# -# This software is provided "AS IS" and without any express or -# implied warranties, including, without limitation, the implied -# warranties of merchantability and fitness for a particular -# purpose. -# - -# $FreeBSD$ - -# A 512 byte MBR boot manager that simply boots the active partition. - - .set LOAD,0x7c00 # Load address - .set EXEC,0x600 # Execution address - .set PT_OFF,0x1be # Partition table - .set MAGIC,0xaa55 # Magic: bootable - .set FL_PACKET,0x80 # Flag: try EDD - - .set NHRDRV,0x475 # Number of hard drives - - .globl start # Entry point - .code16 - -# -# Setup the segment registers for flat addressing and setup the stack. -# -start: cld # String ops inc - xorw %ax,%ax # Zero - movw %ax,%es # Address - movw %ax,%ds # data - movw %ax,%ss # Set up - movw $LOAD,%sp # stack -# -# Relocate ourself to a lower address so that we are out of the way when -# we load in the bootstrap from the partition to boot. -# - movw $main-EXEC+LOAD,%si # Source - movw $main,%di # Destination - movw $0x200-(main-start),%cx # Byte count - rep # Relocate - movsb # code -# -# Jump to the relocated code. -# - jmp main-LOAD+EXEC # To relocated code -# -# Scan the partition table looking for an active entry. Note that %ch is -# zero from the repeated string instruction above. We save the offset of -# the active partition in %si and scan the entire table to ensure that only -# one partition is marked active. -# -main: xorw %si,%si # No active partition - movw $partbl,%bx # Partition table - movb $0x4,%cl # Number of entries -main.1: cmpb %ch,(%bx) # Null entry? - je main.2 # Yes - jg err_pt # If 0x1..0x7f - testw %si,%si # Active already found? - jnz err_pt # Yes - movw %bx,%si # Point to active -main.2: addb $0x10,%bl # Till - loop main.1 # done - testw %si,%si # Active found? - jnz main.3 # Yes - int $0x18 # BIOS: Diskless boot -# -# Ok, we've found a possible active partition. Check to see that the drive -# is a valid hard drive number. -# -main.3: cmpb $0x80,%dl # Drive valid? - jb main.4 # No - movb NHRDRV,%dh # Calculate the highest - addb $0x80,%dh # drive number available - cmpb %dh,%dl # Within range? - jb main.5 # Yes -main.4: movb (%si),%dl # Load drive -# -# Ok, now that we have a valid drive and partition entry, load the CHS from -# the partition entry and read the sector from the disk. -# -main.5: movw %sp,%di # Save stack pointer - movb 0x1(%si),%dh # Load head - movw 0x2(%si),%cx # Load cylinder:sector - movw $LOAD,%bx # Transfer buffer - testb $FL_PACKET,flags # Try EDD? - jz main.7 # No. - pushw %cx # Save %cx - pushw %bx # Save %bx - movw $0x55aa,%bx # Magic - movb $0x41,%ah # BIOS: EDD extensions - int $0x13 # present? - jc main.6 # No. - cmpw $0xaa55,%bx # Magic ok? - jne main.6 # No. - testb $0x1,%cl # Packet mode present? - jz main.6 # No. - popw %bx # Restore %bx - pushl $0x0 # Set the LBA - pushl 0x8(%si) # address - pushw %es # Set the address of - pushw %bx # the transfer buffer - pushw $0x1 # Read 1 sector - pushw $0x10 # Packet length - movw %sp,%si # Packer pointer - movw $0x4200,%ax # BIOS: LBA Read from disk - jmp main.8 # Skip the CHS setup -main.6: popw %bx # Restore %bx - popw %cx # Restore %cx -main.7: movw $0x201,%ax # BIOS: Read from disk -main.8: int $0x13 # Call the BIOS - movw %di,%sp # Restore stack - jc err_rd # If error -# -# Now that we've loaded the bootstrap, check for the 0xaa55 signature. If it -# is present, execute the bootstrap we just loaded. -# - cmpw $MAGIC,0x1fe(%bx) # Bootable? - jne err_os # No - jmp *%bx # Invoke bootstrap -# -# Various error message entry points. -# -err_pt: movw $msg_pt,%si # "Invalid partition - jmp putstr # table" - -err_rd: movw $msg_rd,%si # "Error loading - jmp putstr # operating system" - -err_os: movw $msg_os,%si # "Missing operating - jmp putstr # system" -# -# Output an ASCIZ string to the console via the BIOS. -# -putstr.0: movw $0x7,%bx # Page:attribute - movb $0xe,%ah # BIOS: Display - int $0x10 # character -putstr: lodsb # Get character - testb %al,%al # End of string? - jnz putstr.0 # No -putstr.1: jmp putstr.1 # Await reset - -msg_pt: .asciz "Invalid partition table" -msg_rd: .asciz "Error loading operating system" -msg_os: .asciz "Missing operating system" - - .org PT_OFF-1,0x90 -flags: .byte FLAGS # Flags - -partbl: .fill 0x10,0x4,0x0 # Partition table - .word MAGIC # Magic number diff --git a/stand/i386/pmbr/pmbr.S b/stand/i386/pmbr/pmbr.S index c61acbe261b..643f3257b46 100644 --- a/stand/i386/pmbr/pmbr.S +++ b/stand/i386/pmbr/pmbr.S @@ -1,4 +1,5 @@ #- +# Copyright (c) 2011 Lucas Holt # Copyright (c) 2007 Yahoo!, Inc. # All rights reserved. # Written by: John Baldwin @@ -27,10 +28,12 @@ # OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF # SUCH DAMAGE. # +# $MidnightBSD$ +# $FreeBSD: src/sys/boot/i386/pmbr/pmbr.s,v 1.2.2.1.2.1 2008/11/25 02:59:29 kensmith Exp $ # # Partly from: src/sys/boot/i386/mbr/mbr.s 1.7 -# A 512 byte PMBR boot manager that looks for a FreeBSD boot GPT partition +# A 512 byte PMBR boot manager that looks for a MidnightBSD boot GPT partition # and boots it. .set LOAD,0x7c00 # Load address @@ -120,14 +123,14 @@ main.3a: subl $1, (%si) # 0x0(%si) = last sec (0-31) movsw # $lastsec--, copy it to $lba jmp main.2a # Read the next sector # -# Load a partition table sector from disk and look for a FreeBSD boot +# Load a partition table sector from disk and look for a MidnightBSD boot # partition. # load_part: movw $GPT_ADDR+GPT_PART_LBA,%si movw $PART_ADDR,%bx call read scan: movw %bx,%si # Compare partition UUID - movw $boot_uuid,%di # with FreeBSD boot UUID + movw $boot_uuid,%di # with MidnightBSD boot UUID movw $0x10,%cx repe cmpsb jnz next_part # Didn't match, next partition @@ -232,17 +235,17 @@ msg_noboot: .asciz "Missing boot loader" lba: .quad 1 # LBA of GPT header -boot_uuid: .long 0x83bd6b9d - .word 0x7f41 - .word 0x11dc - .byte 0xbe - .byte 0x0b - .byte 0x00 - .byte 0x15 - .byte 0x60 - .byte 0xb8 - .byte 0x4f - .byte 0x0f +boot_uuid: .long 0x85d5e45e + .word 0x237c + .word 0x11e1 + .byte 0xb4 + .byte 0xb3 + .byte 0xe8 + .byte 0x9a + .byte 0x8f + .byte 0x7f + .byte 0xc3 + .byte 0xa7 .org DISKSIG,0x90 sig: .long 0 # OS Disk Signature diff --git a/stand/i386/pmbr/pmbr.s b/stand/i386/pmbr/pmbr.s deleted file mode 100644 index 643f3257b46..00000000000 --- a/stand/i386/pmbr/pmbr.s +++ /dev/null @@ -1,255 +0,0 @@ -#- -# Copyright (c) 2011 Lucas Holt -# Copyright (c) 2007 Yahoo!, Inc. -# All rights reserved. -# Written by: John Baldwin -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# 3. Neither the name of the author nor the names of any co-contributors -# may be used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND -# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -# ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE -# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -# OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -# HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -# OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -# SUCH DAMAGE. -# -# $MidnightBSD$ -# $FreeBSD: src/sys/boot/i386/pmbr/pmbr.s,v 1.2.2.1.2.1 2008/11/25 02:59:29 kensmith Exp $ -# -# Partly from: src/sys/boot/i386/mbr/mbr.s 1.7 - -# A 512 byte PMBR boot manager that looks for a MidnightBSD boot GPT partition -# and boots it. - - .set LOAD,0x7c00 # Load address - .set EXEC,0x600 # Execution address - .set MAGIC,0xaa55 # Magic: bootable - .set SECSIZE,0x200 # Size of a single disk sector - .set DISKSIG,440 # Disk signature offset - .set STACK,EXEC+SECSIZE*4 # Stack address - .set GPT_ADDR,STACK # GPT header address - .set GPT_SIG,0 - .set GPT_SIG_0,0x20494645 # "EFI " - .set GPT_SIG_1,0x54524150 # "PART" - .set GPT_MYLBA,24 - .set GPT_PART_LBA,72 - .set GPT_NPART,80 - .set GPT_PART_SIZE,84 - .set PART_ADDR,GPT_ADDR+SECSIZE # GPT partition array address - .set PART_TYPE,0 - .set PART_START_LBA,32 - .set PART_END_LBA,40 - .set DPBUF,PART_ADDR+SECSIZE - .set DPBUF_SEC,0x10 # Number of sectors - - .set NHRDRV,0x475 # Number of hard drives - - .globl start # Entry point - .code16 - -# -# Setup the segment registers for flat addressing and setup the stack. -# -start: cld # String ops inc - xorw %ax,%ax # Zero - movw %ax,%es # Address - movw %ax,%ds # data - movw %ax,%ss # Set up - movw $STACK,%sp # stack -# -# Relocate ourself to a lower address so that we have more room to load -# other sectors. -# - movw $main-EXEC+LOAD,%si # Source - movw $main,%di # Destination - movw $SECSIZE-(main-start),%cx # Byte count - rep # Relocate - movsb # code -# -# Jump to the relocated code. -# - jmp main-LOAD+EXEC # To relocated code -# -# Validate drive number in %dl. -# -main: cmpb $0x80,%dl # Drive valid? - jb main.1 # No - movb NHRDRV,%dh # Calculate the highest - addb $0x80,%dh # drive number available - cmpb %dh,%dl # Within range? - jb main.2 # Yes -main.1: movb $0x80,%dl # Assume drive 0x80 -# -# Load the GPT header and verify signature. Try LBA 1 for the primary one and -# the last LBA for the backup if it is broken. -# -main.2: call getdrvparams # Read drive parameters - movb $1,%dh # %dh := 1 (reading primary) -main.2a: movw $GPT_ADDR,%bx - movw $lba,%si - call read # Read header and check GPT sig - cmpl $GPT_SIG_0,GPT_ADDR+GPT_SIG - jnz main.2b - cmpl $GPT_SIG_1,GPT_ADDR+GPT_SIG+4 - jnz main.2b - jmp load_part -main.2b: cmpb $1,%dh # Reading primary? - jne err_pt # If no - invalid table found -# -# Try alternative LBAs from the last sector for the GPT header. -# -main.3: movb $0,%dh # %dh := 0 (reading backup) - movw $DPBUF+DPBUF_SEC,%si # %si = last sector + 1 - movw $lba,%di # %di = $lba -main.3a: subl $1, (%si) # 0x0(%si) = last sec (0-31) - sbbl $0, 4(%si) - movw $4,%cx - rep - movsw # $lastsec--, copy it to $lba - jmp main.2a # Read the next sector -# -# Load a partition table sector from disk and look for a MidnightBSD boot -# partition. -# -load_part: movw $GPT_ADDR+GPT_PART_LBA,%si - movw $PART_ADDR,%bx - call read -scan: movw %bx,%si # Compare partition UUID - movw $boot_uuid,%di # with MidnightBSD boot UUID - movw $0x10,%cx - repe cmpsb - jnz next_part # Didn't match, next partition -# -# We found a boot partition. Load it into RAM starting at 0x7c00. -# - movw %bx,%di # Save partition pointer in %di - leaw PART_START_LBA(%di),%si - movw $LOAD/16,%bx - movw %bx,%es - xorw %bx,%bx -load_boot: push %si # Save %si - call read - pop %si # Restore - movl PART_END_LBA(%di),%eax # See if this was the last LBA - cmpl (%si),%eax - jnz next_boot - movl PART_END_LBA+4(%di),%eax - cmpl 4(%si),%eax - jnz next_boot - mov %bx,%es # Reset %es to zero - jmp LOAD # Jump to boot code -next_boot: addl $1,(%si) # Next LBA - adcl $0,4(%si) - mov %es,%ax # Adjust segment for next - addw $SECSIZE/16,%ax # sector - cmp $0x9000,%ax # Don't load past 0x90000, - jae err_big # 545k should be enough for - mov %ax,%es # any boot code. :) - jmp load_boot -# -# Move to the next partition. If we walk off the end of the sector, load -# the next sector. We assume that partition entries are smaller than 64k -# and that they won't span a sector boundary. -# -# XXX: Should we int 0x18 instead of err_noboot if we hit the end of the table? -# -next_part: decl GPT_ADDR+GPT_NPART # Was this the last partition? - jz err_noboot - movw GPT_ADDR+GPT_PART_SIZE,%ax - addw %ax,%bx # Next partition - cmpw $PART_ADDR+0x200,%bx # Still in sector? - jb scan - addl $1, GPT_ADDR+GPT_PART_LBA # Next sector - adcl $0,GPT_ADDR+GPT_PART_LBA+4 - jmp load_part -# -# Load a sector (64-bit LBA at %si) from disk %dl into %es:%bx by creating -# a EDD packet on the stack and passing it to the BIOS. Trashes %ax and %si. -# -read: pushl 0x4(%si) # Set the LBA - pushl 0x0(%si) # address - pushw %es # Set the address of - pushw %bx # the transfer buffer - pushw $0x1 # Read 1 sector - pushw $0x10 # Packet length - movw %sp,%si # Packer pointer - movw $0x4200,%ax # BIOS: LBA Read from disk - int $0x13 # Call the BIOS - add $0x10,%sp # Restore stack - jc err_rd # If error - ret -# -# Check the number of LBAs on the drive index %dx. Trashes %ax and %si. -# -getdrvparams: - movw $DPBUF,%si # Set the address of result buf - movw $0x001e,(%si) # len - movw $0x4800,%ax # BIOS: Read Drive Parameters - int $0x13 # Call the BIOS - jc err_rd # "I/O error" if error - ret -# -# Various error message entry points. -# -err_big: movw $msg_big,%si # "Boot loader too - jmp putstr # large" - -err_pt: movw $msg_pt,%si # "Invalid partition - jmp putstr # table" - -err_rd: movw $msg_rd,%si # "I/O error loading - jmp putstr # boot loader" - -err_noboot: movw $msg_noboot,%si # "Missing boot - jmp putstr # loader" -# -# Output an ASCIZ string to the console via the BIOS. -# -putstr.0: movw $0x7,%bx # Page:attribute - movb $0xe,%ah # BIOS: Display - int $0x10 # character -putstr: lodsb # Get character - testb %al,%al # End of string? - jnz putstr.0 # No -putstr.1: jmp putstr.1 # Await reset - -msg_big: .asciz "Boot loader too large" -msg_pt: .asciz "Invalid partition table" -msg_rd: .asciz "I/O error loading boot loader" -msg_noboot: .asciz "Missing boot loader" - -lba: .quad 1 # LBA of GPT header - -boot_uuid: .long 0x85d5e45e - .word 0x237c - .word 0x11e1 - .byte 0xb4 - .byte 0xb3 - .byte 0xe8 - .byte 0x9a - .byte 0x8f - .byte 0x7f - .byte 0xc3 - .byte 0xa7 - - .org DISKSIG,0x90 -sig: .long 0 # OS Disk Signature - .word 0 # "Unknown" in PMBR - -partbl: .fill 0x10,0x4,0x0 # Partition table - .word MAGIC # Magic number diff --git a/stand/libsa/nandfs.c b/stand/libsa/nandfs.c deleted file mode 100644 index b3e72243e99..00000000000 --- a/stand/libsa/nandfs.c +++ /dev/null @@ -1,1061 +0,0 @@ -/*- - * Copyright (c) 2010-2012 Semihalf. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include -__FBSDID("$FreeBSD$"); - -#include -#include -#include -#include -#include -#include "stand.h" -#include "string.h" -#include "zlib.h" - -#define DEBUG -#undef DEBUG -#ifdef DEBUG -#define NANDFS_DEBUG(fmt, args...) do { \ - printf("NANDFS_DEBUG:" fmt "\n", ##args); } while (0) -#else -#define NANDFS_DEBUG(fmt, args...) -#endif - -struct nandfs_mdt { - uint32_t entries_per_block; - uint32_t entries_per_group; - uint32_t blocks_per_group; - uint32_t groups_per_desc_block; /* desc is super group */ - uint32_t blocks_per_desc_block; /* desc is super group */ -}; - -struct bmap_buf { - LIST_ENTRY(bmap_buf) list; - nandfs_daddr_t blknr; - uint64_t *map; -}; - -struct nandfs_node { - struct nandfs_inode *inode; - LIST_HEAD(, bmap_buf) bmap_bufs; -}; -struct nandfs { - int nf_blocksize; - int nf_sectorsize; - int nf_cpno; - - struct open_file *nf_file; - struct nandfs_node *nf_opened_node; - u_int nf_offset; - uint8_t *nf_buf; - int64_t nf_buf_blknr; - - struct nandfs_fsdata *nf_fsdata; - struct nandfs_super_block *nf_sb; - struct nandfs_segment_summary nf_segsum; - struct nandfs_checkpoint nf_checkpoint; - struct nandfs_super_root nf_sroot; - struct nandfs_node nf_ifile; - struct nandfs_node nf_datfile; - struct nandfs_node nf_cpfile; - struct nandfs_mdt nf_datfile_mdt; - struct nandfs_mdt nf_ifile_mdt; - - int nf_nindir[NANDFS_NIADDR]; -}; - -static int nandfs_open(const char *, struct open_file *); -static int nandfs_close(struct open_file *); -static int nandfs_read(struct open_file *, void *, size_t, size_t *); -static off_t nandfs_seek(struct open_file *, off_t, int); -static int nandfs_stat(struct open_file *, struct stat *); -static int nandfs_readdir(struct open_file *, struct dirent *); - -static int nandfs_buf_read(struct nandfs *, void **, size_t *); -static struct nandfs_node *nandfs_lookup_path(struct nandfs *, const char *); -static int nandfs_read_inode(struct nandfs *, struct nandfs_node *, - nandfs_lbn_t, u_int, void *, int); -static int nandfs_read_blk(struct nandfs *, nandfs_daddr_t, void *, int); -static int nandfs_bmap_lookup(struct nandfs *, struct nandfs_node *, - nandfs_lbn_t, nandfs_daddr_t *, int); -static int nandfs_get_checkpoint(struct nandfs *, uint64_t, - struct nandfs_checkpoint *); -static nandfs_daddr_t nandfs_vtop(struct nandfs *, nandfs_daddr_t); -static void nandfs_calc_mdt_consts(int, struct nandfs_mdt *, int); -static void nandfs_mdt_trans(struct nandfs_mdt *, uint64_t, - nandfs_daddr_t *, uint32_t *); -static int ioread(struct open_file *, off_t, void *, u_int); -static int nandfs_probe_sectorsize(struct open_file *); - -struct fs_ops nandfs_fsops = { - "nandfs", - nandfs_open, - nandfs_close, - nandfs_read, - null_write, - nandfs_seek, - nandfs_stat, - nandfs_readdir -}; - -#define NINDIR(fs) ((fs)->nf_blocksize / sizeof(nandfs_daddr_t)) - -/* from NetBSD's src/sys/net/if_ethersubr.c */ -static uint32_t -nandfs_crc32(uint32_t crc, const uint8_t *buf, size_t len) -{ - static const uint32_t crctab[] = { - 0x00000000, 0x1db71064, 0x3b6e20c8, 0x26d930ac, - 0x76dc4190, 0x6b6b51f4, 0x4db26158, 0x5005713c, - 0xedb88320, 0xf00f9344, 0xd6d6a3e8, 0xcb61b38c, - 0x9b64c2b0, 0x86d3d2d4, 0xa00ae278, 0xbdbdf21c - }; - size_t i; - - crc = crc ^ ~0U; - for (i = 0; i < len; i++) { - crc ^= buf[i]; - crc = (crc >> 4) ^ crctab[crc & 0xf]; - crc = (crc >> 4) ^ crctab[crc & 0xf]; - } - return (crc ^ ~0U); -} - -static int -nandfs_check_fsdata_crc(struct nandfs_fsdata *fsdata) -{ - uint32_t fsdata_crc, comp_crc; - - if (fsdata->f_magic != NANDFS_FSDATA_MAGIC) - return (0); - - /* Preserve crc */ - fsdata_crc = fsdata->f_sum; - - /* Calculate */ - fsdata->f_sum = (0); - comp_crc = nandfs_crc32(0, (uint8_t *)fsdata, fsdata->f_bytes); - - /* Restore */ - fsdata->f_sum = fsdata_crc; - - /* Check CRC */ - return (fsdata_crc == comp_crc); -} - -static int -nandfs_check_superblock_crc(struct nandfs_fsdata *fsdata, - struct nandfs_super_block *super) -{ - uint32_t super_crc, comp_crc; - - /* Check super block magic */ - if (super->s_magic != NANDFS_SUPER_MAGIC) - return (0); - - /* Preserve CRC */ - super_crc = super->s_sum; - - /* Calculate */ - super->s_sum = (0); - comp_crc = nandfs_crc32(0, (uint8_t *)super, fsdata->f_sbbytes); - - /* Restore */ - super->s_sum = super_crc; - - /* Check CRC */ - return (super_crc == comp_crc); -} - -static int -nandfs_find_super_block(struct nandfs *fs, struct open_file *f) -{ - struct nandfs_super_block *sb; - int i, j, n, s; - int sectors_to_read, error; - - sb = malloc(fs->nf_sectorsize); - if (sb == NULL) - return (ENOMEM); - - memset(fs->nf_sb, 0, sizeof(*fs->nf_sb)); - - sectors_to_read = (NANDFS_NFSAREAS * fs->nf_fsdata->f_erasesize) / - fs->nf_sectorsize; - for (i = 0; i < sectors_to_read; i++) { - NANDFS_DEBUG("reading i %d offset %d\n", i, - i * fs->nf_sectorsize); - error = ioread(f, i * fs->nf_sectorsize, (char *)sb, - fs->nf_sectorsize); - if (error) { - NANDFS_DEBUG("error %d\n", error); - continue; - } - n = fs->nf_sectorsize / sizeof(struct nandfs_super_block); - s = 0; - if ((i * fs->nf_sectorsize) % fs->nf_fsdata->f_erasesize == 0) { - if (fs->nf_sectorsize == sizeof(struct nandfs_fsdata)) - continue; - else { - s += (sizeof(struct nandfs_fsdata) / - sizeof(struct nandfs_super_block)); - } - } - - for (j = s; j < n; j++) { - if (!nandfs_check_superblock_crc(fs->nf_fsdata, &sb[j])) - continue; - NANDFS_DEBUG("magic %x wtime %jd, lastcp 0x%jx\n", - sb[j].s_magic, sb[j].s_wtime, sb[j].s_last_cno); - if (sb[j].s_last_cno > fs->nf_sb->s_last_cno) - memcpy(fs->nf_sb, &sb[j], sizeof(*fs->nf_sb)); - } - } - - free(sb); - - return (fs->nf_sb->s_magic != 0 ? 0 : EINVAL); -} - -static int -nandfs_find_fsdata(struct nandfs *fs, struct open_file *f) -{ - int offset, error, i; - - NANDFS_DEBUG("starting\n"); - - offset = 0; - for (i = 0; i < 64 * NANDFS_NFSAREAS; i++) { - error = ioread(f, offset, (char *)fs->nf_fsdata, - sizeof(struct nandfs_fsdata)); - if (error) - return (error); - if (fs->nf_fsdata->f_magic == NANDFS_FSDATA_MAGIC) { - NANDFS_DEBUG("found at %x, volume %s\n", offset, - fs->nf_fsdata->f_volume_name); - if (nandfs_check_fsdata_crc(fs->nf_fsdata)) - break; - } - offset += fs->nf_sectorsize; - } - - return (error); -} - -static int -nandfs_read_structures(struct nandfs *fs, struct open_file *f) -{ - int error; - - error = nandfs_find_fsdata(fs, f); - if (error) - return (error); - - error = nandfs_find_super_block(fs, f); - - if (error == 0) - NANDFS_DEBUG("selected sb with w_time %jd last_pseg %jx\n", - fs->nf_sb->s_wtime, fs->nf_sb->s_last_pseg); - - return (error); -} - -static int -nandfs_mount(struct nandfs *fs, struct open_file *f) -{ - int err = 0, level; - uint64_t last_pseg; - - fs->nf_fsdata = malloc(sizeof(struct nandfs_fsdata)); - fs->nf_sb = malloc(sizeof(struct nandfs_super_block)); - - err = nandfs_read_structures(fs, f); - if (err) { - free(fs->nf_fsdata); - free(fs->nf_sb); - return (err); - } - - fs->nf_blocksize = 1 << (fs->nf_fsdata->f_log_block_size + 10); - - NANDFS_DEBUG("using superblock with wtime %jd\n", fs->nf_sb->s_wtime); - - fs->nf_cpno = fs->nf_sb->s_last_cno; - last_pseg = fs->nf_sb->s_last_pseg; - - /* - * Calculate indirect block levels. - */ - nandfs_daddr_t mult; - - mult = 1; - for (level = 0; level < NANDFS_NIADDR; level++) { - mult *= NINDIR(fs); - fs->nf_nindir[level] = mult; - } - - nandfs_calc_mdt_consts(fs->nf_blocksize, &fs->nf_datfile_mdt, - fs->nf_fsdata->f_dat_entry_size); - - nandfs_calc_mdt_consts(fs->nf_blocksize, &fs->nf_ifile_mdt, - fs->nf_fsdata->f_inode_size); - - err = ioread(f, last_pseg * fs->nf_blocksize, &fs->nf_segsum, - sizeof(struct nandfs_segment_summary)); - if (err) { - free(fs->nf_sb); - free(fs->nf_fsdata); - return (err); - } - - err = ioread(f, (last_pseg + fs->nf_segsum.ss_nblocks - 1) * - fs->nf_blocksize, &fs->nf_sroot, sizeof(struct nandfs_super_root)); - if (err) { - free(fs->nf_sb); - free(fs->nf_fsdata); - return (err); - } - - fs->nf_datfile.inode = &fs->nf_sroot.sr_dat; - LIST_INIT(&fs->nf_datfile.bmap_bufs); - fs->nf_cpfile.inode = &fs->nf_sroot.sr_cpfile; - LIST_INIT(&fs->nf_cpfile.bmap_bufs); - - err = nandfs_get_checkpoint(fs, fs->nf_cpno, &fs->nf_checkpoint); - if (err) { - free(fs->nf_sb); - free(fs->nf_fsdata); - return (err); - } - - NANDFS_DEBUG("checkpoint cp_cno=%lld\n", fs->nf_checkpoint.cp_cno); - NANDFS_DEBUG("checkpoint cp_inodes_count=%lld\n", - fs->nf_checkpoint.cp_inodes_count); - NANDFS_DEBUG("checkpoint cp_ifile_inode.i_blocks=%lld\n", - fs->nf_checkpoint.cp_ifile_inode.i_blocks); - - fs->nf_ifile.inode = &fs->nf_checkpoint.cp_ifile_inode; - LIST_INIT(&fs->nf_ifile.bmap_bufs); - return (0); -} - -#define NINDIR(fs) ((fs)->nf_blocksize / sizeof(nandfs_daddr_t)) - -static int -nandfs_open(const char *path, struct open_file *f) -{ - struct nandfs *fs; - struct nandfs_node *node; - int err, bsize, level; - - NANDFS_DEBUG("nandfs_open('%s', %p)\n", path, f); - - fs = malloc(sizeof(struct nandfs)); - f->f_fsdata = fs; - fs->nf_file = f; - - bsize = nandfs_probe_sectorsize(f); - if (bsize < 0) { - printf("Cannot probe medium sector size\n"); - return (EINVAL); - } - - fs->nf_sectorsize = bsize; - - /* - * Calculate indirect block levels. - */ - nandfs_daddr_t mult; - - mult = 1; - for (level = 0; level < NANDFS_NIADDR; level++) { - mult *= NINDIR(fs); - fs->nf_nindir[level] = mult; - } - - NANDFS_DEBUG("fs %p nf_sectorsize=%x\n", fs, fs->nf_sectorsize); - - err = nandfs_mount(fs, f); - if (err) { - NANDFS_DEBUG("Cannot mount nandfs: %s\n", strerror(err)); - return (err); - } - - node = nandfs_lookup_path(fs, path); - if (node == NULL) - return (EINVAL); - - fs->nf_offset = 0; - fs->nf_buf = NULL; - fs->nf_buf_blknr = -1; - fs->nf_opened_node = node; - LIST_INIT(&fs->nf_opened_node->bmap_bufs); - return (0); -} - -static void -nandfs_free_node(struct nandfs_node *node) -{ - struct bmap_buf *bmap, *tmp; - - free(node->inode); - LIST_FOREACH_SAFE(bmap, &node->bmap_bufs, list, tmp) { - LIST_REMOVE(bmap, list); - free(bmap->map); - free(bmap); - } - free(node); -} - -static int -nandfs_close(struct open_file *f) -{ - struct nandfs *fs = f->f_fsdata; - - NANDFS_DEBUG("nandfs_close(%p)\n", f); - - if (fs->nf_buf != NULL) - free(fs->nf_buf); - - nandfs_free_node(fs->nf_opened_node); - free(fs->nf_sb); - free(fs); - return (0); -} - -static int -nandfs_read(struct open_file *f, void *addr, size_t size, size_t *resid) -{ - struct nandfs *fs = (struct nandfs *)f->f_fsdata; - size_t csize, buf_size; - void *buf; - int error = 0; - - NANDFS_DEBUG("nandfs_read(file=%p, addr=%p, size=%d)\n", f, addr, size); - - while (size != 0) { - if (fs->nf_offset >= fs->nf_opened_node->inode->i_size) - break; - - error = nandfs_buf_read(fs, &buf, &buf_size); - if (error) - break; - - csize = size; - if (csize > buf_size) - csize = buf_size; - - bcopy(buf, addr, csize); - - fs->nf_offset += csize; - addr = (char *)addr + csize; - size -= csize; - } - - if (resid) - *resid = size; - return (error); -} - -static off_t -nandfs_seek(struct open_file *f, off_t offset, int where) -{ - struct nandfs *fs = f->f_fsdata; - off_t off; - u_int size; - - NANDFS_DEBUG("nandfs_seek(file=%p, offset=%lld, where=%d)\n", f, - offset, where); - - size = fs->nf_opened_node->inode->i_size; - - switch (where) { - case SEEK_SET: - off = 0; - break; - case SEEK_CUR: - off = fs->nf_offset; - break; - case SEEK_END: - off = size; - break; - default: - errno = EINVAL; - return (-1); - } - - off += offset; - if (off < 0 || off > size) { - errno = EINVAL; - return(-1); - } - - fs->nf_offset = (u_int)off; - - return (off); -} - -static int -nandfs_stat(struct open_file *f, struct stat *sb) -{ - struct nandfs *fs = f->f_fsdata; - - NANDFS_DEBUG("nandfs_stat(file=%p, stat=%p)\n", f, sb); - - sb->st_size = fs->nf_opened_node->inode->i_size; - sb->st_mode = fs->nf_opened_node->inode->i_mode; - sb->st_uid = fs->nf_opened_node->inode->i_uid; - sb->st_gid = fs->nf_opened_node->inode->i_gid; - return (0); -} - -static int -nandfs_readdir(struct open_file *f, struct dirent *d) -{ - struct nandfs *fs = f->f_fsdata; - struct nandfs_dir_entry *dirent; - void *buf; - size_t buf_size; - - NANDFS_DEBUG("nandfs_readdir(file=%p, dirent=%p)\n", f, d); - - if (fs->nf_offset >= fs->nf_opened_node->inode->i_size) { - NANDFS_DEBUG("nandfs_readdir(file=%p, dirent=%p) ENOENT\n", - f, d); - return (ENOENT); - } - - if (nandfs_buf_read(fs, &buf, &buf_size)) { - NANDFS_DEBUG("nandfs_readdir(file=%p, dirent=%p)" - "buf_read failed\n", f, d); - return (EIO); - } - - NANDFS_DEBUG("nandfs_readdir(file=%p, dirent=%p) moving forward\n", - f, d); - - dirent = (struct nandfs_dir_entry *)buf; - fs->nf_offset += dirent->rec_len; - strncpy(d->d_name, dirent->name, dirent->name_len); - d->d_name[dirent->name_len] = '\0'; - d->d_type = dirent->file_type; - return (0); -} - -static int -nandfs_buf_read(struct nandfs *fs, void **buf_p, size_t *size_p) -{ - nandfs_daddr_t blknr, blkoff; - - blknr = fs->nf_offset / fs->nf_blocksize; - blkoff = fs->nf_offset % fs->nf_blocksize; - - if (blknr != fs->nf_buf_blknr) { - if (fs->nf_buf == NULL) - fs->nf_buf = malloc(fs->nf_blocksize); - - if (nandfs_read_inode(fs, fs->nf_opened_node, blknr, 1, - fs->nf_buf, 0)) - return (EIO); - - fs->nf_buf_blknr = blknr; - } - - *buf_p = fs->nf_buf + blkoff; - *size_p = fs->nf_blocksize - blkoff; - - NANDFS_DEBUG("nandfs_buf_read buf_p=%p size_p=%d\n", *buf_p, *size_p); - - if (*size_p > fs->nf_opened_node->inode->i_size - fs->nf_offset) - *size_p = fs->nf_opened_node->inode->i_size - fs->nf_offset; - - return (0); -} - -static struct nandfs_node * -nandfs_lookup_node(struct nandfs *fs, uint64_t ino) -{ - uint64_t blocknr; - int entrynr; - struct nandfs_inode *buffer; - struct nandfs_node *node; - struct nandfs_inode *inode; - - NANDFS_DEBUG("nandfs_lookup_node ino=%lld\n", ino); - - if (ino == 0) { - printf("nandfs_lookup_node: invalid inode requested\n"); - return (NULL); - } - - buffer = malloc(fs->nf_blocksize); - inode = malloc(sizeof(struct nandfs_inode)); - node = malloc(sizeof(struct nandfs_node)); - - nandfs_mdt_trans(&fs->nf_ifile_mdt, ino, &blocknr, &entrynr); - - if (nandfs_read_inode(fs, &fs->nf_ifile, blocknr, 1, buffer, 0)) - return (NULL); - - memcpy(inode, &buffer[entrynr], sizeof(struct nandfs_inode)); - node->inode = inode; - free(buffer); - return (node); -} - -static struct nandfs_node * -nandfs_lookup_path(struct nandfs *fs, const char *path) -{ - struct nandfs_node *node; - struct nandfs_dir_entry *dirent; - char *namebuf; - uint64_t i, done, pinode, inode; - int nlinks = 0, counter, len, link_len, nameidx; - uint8_t *buffer, *orig; - char *strp, *lpath; - - buffer = malloc(fs->nf_blocksize); - orig = buffer; - - namebuf = malloc(2 * MAXPATHLEN + 2); - strncpy(namebuf, path, MAXPATHLEN); - namebuf[MAXPATHLEN] = '\0'; - done = nameidx = 0; - lpath = namebuf; - - /* Get the root inode */ - node = nandfs_lookup_node(fs, NANDFS_ROOT_INO); - inode = NANDFS_ROOT_INO; - - while ((strp = strsep(&lpath, "/")) != NULL) { - if (*strp == '\0') - continue; - if ((node->inode->i_mode & IFMT) != IFDIR) { - nandfs_free_node(node); - node = NULL; - goto out; - } - - len = strlen(strp); - NANDFS_DEBUG("%s: looking for %s\n", __func__, strp); - for (i = 0; i < node->inode->i_blocks; i++) { - if (nandfs_read_inode(fs, node, i, 1, orig, 0)) { - node = NULL; - goto out; - } - - buffer = orig; - done = counter = 0; - while (1) { - dirent = - (struct nandfs_dir_entry *)(void *)buffer; - NANDFS_DEBUG("%s: dirent.name = %s\n", - __func__, dirent->name); - NANDFS_DEBUG("%s: dirent.rec_len = %d\n", - __func__, dirent->rec_len); - NANDFS_DEBUG("%s: dirent.inode = %lld\n", - __func__, dirent->inode); - if (len == dirent->name_len && - (strncmp(strp, dirent->name, len) == 0) && - dirent->inode != 0) { - nandfs_free_node(node); - node = nandfs_lookup_node(fs, - dirent->inode); - pinode = inode; - inode = dirent->inode; - done = 1; - break; - } - - counter += dirent->rec_len; - buffer += dirent->rec_len; - - if (counter == fs->nf_blocksize) - break; - } - - if (done) - break; - } - - if (!done) { - node = NULL; - goto out; - } - - NANDFS_DEBUG("%s: %.*s has mode %o\n", __func__, - dirent->name_len, dirent->name, node->inode->i_mode); - - if ((node->inode->i_mode & IFMT) == IFLNK) { - NANDFS_DEBUG("%s: %.*s is symlink\n", - __func__, dirent->name_len, dirent->name); - link_len = node->inode->i_size; - - if (++nlinks > MAXSYMLINKS) { - nandfs_free_node(node); - node = NULL; - goto out; - } - - if (nandfs_read_inode(fs, node, 0, 1, orig, 0)) { - nandfs_free_node(node); - node = NULL; - goto out; - } - - NANDFS_DEBUG("%s: symlink is %.*s\n", - __func__, link_len, (char *)orig); - - nameidx = (nameidx == 0) ? MAXPATHLEN + 1 : 0; - bcopy((char *)orig, namebuf + nameidx, - (unsigned)link_len); - if (lpath != NULL) { - namebuf[nameidx + link_len++] = '/'; - strncpy(namebuf + nameidx + link_len, lpath, - MAXPATHLEN - link_len); - namebuf[nameidx + MAXPATHLEN] = '\0'; - } else - namebuf[nameidx + link_len] = '\0'; - - NANDFS_DEBUG("%s: strp=%s, lpath=%s, namebuf0=%s, " - "namebuf1=%s, idx=%d\n", __func__, strp, lpath, - namebuf + 0, namebuf + MAXPATHLEN + 1, nameidx); - - lpath = namebuf + nameidx; - - nandfs_free_node(node); - - /* - * If absolute pathname, restart at root. Otherwise - * continue with out parent inode. - */ - inode = (orig[0] == '/') ? NANDFS_ROOT_INO : pinode; - node = nandfs_lookup_node(fs, inode); - } - } - -out: - free(namebuf); - free(orig); - return (node); -} - -static int -nandfs_read_inode(struct nandfs *fs, struct nandfs_node *node, - nandfs_daddr_t blknr, u_int nblks, void *buf, int raw) -{ - uint64_t *pblks; - uint64_t *vblks; - u_int i; - int error; - - pblks = malloc(nblks * sizeof(uint64_t)); - vblks = malloc(nblks * sizeof(uint64_t)); - - NANDFS_DEBUG("nandfs_read_inode fs=%p node=%p blknr=%lld nblks=%d\n", - fs, node, blknr, nblks); - for (i = 0; i < nblks; i++) { - error = nandfs_bmap_lookup(fs, node, blknr + i, &vblks[i], raw); - if (error) { - free(pblks); - free(vblks); - return (error); - } - if (raw == 0) - pblks[i] = nandfs_vtop(fs, vblks[i]); - else - pblks[i] = vblks[i]; - } - - for (i = 0; i < nblks; i++) { - if (ioread(fs->nf_file, pblks[i] * fs->nf_blocksize, buf, - fs->nf_blocksize)) { - free(pblks); - free(vblks); - return (EIO); - } - - buf = (void *)((uintptr_t)buf + fs->nf_blocksize); - } - - free(pblks); - free(vblks); - return (0); -} - -static int -nandfs_read_blk(struct nandfs *fs, nandfs_daddr_t blknr, void *buf, int phys) -{ - uint64_t pblknr; - - pblknr = (phys ? blknr : nandfs_vtop(fs, blknr)); - - return (ioread(fs->nf_file, pblknr * fs->nf_blocksize, buf, - fs->nf_blocksize)); -} - -static int -nandfs_get_checkpoint(struct nandfs *fs, uint64_t cpno, - struct nandfs_checkpoint *cp) -{ - uint64_t blocknr; - int blockoff, cp_per_block, dlen; - uint8_t *buf; - - NANDFS_DEBUG("nandfs_get_checkpoint(fs=%p cpno=%lld)\n", fs, cpno); - - buf = malloc(fs->nf_blocksize); - - cpno += NANDFS_CPFILE_FIRST_CHECKPOINT_OFFSET - 1; - dlen = fs->nf_fsdata->f_checkpoint_size; - cp_per_block = fs->nf_blocksize / dlen; - blocknr = cpno / cp_per_block; - blockoff = (cpno % cp_per_block) * dlen; - - if (nandfs_read_inode(fs, &fs->nf_cpfile, blocknr, 1, buf, 0)) { - free(buf); - return (EINVAL); - } - - memcpy(cp, buf + blockoff, sizeof(struct nandfs_checkpoint)); - free(buf); - - return (0); -} - -static uint64_t * -nandfs_get_map(struct nandfs *fs, struct nandfs_node *node, nandfs_daddr_t blknr, - int phys) -{ - struct bmap_buf *bmap; - uint64_t *map; - - LIST_FOREACH(bmap, &node->bmap_bufs, list) { - if (bmap->blknr == blknr) - return (bmap->map); - } - - map = malloc(fs->nf_blocksize); - if (nandfs_read_blk(fs, blknr, map, phys)) { - free(map); - return (NULL); - } - - bmap = malloc(sizeof(struct bmap_buf)); - bmap->blknr = blknr; - bmap->map = map; - - LIST_INSERT_HEAD(&node->bmap_bufs, bmap, list); - - NANDFS_DEBUG("%s:(node=%p, map=%p)\n", __func__, node, map); - return (map); -} - -static int -nandfs_bmap_lookup(struct nandfs *fs, struct nandfs_node *node, - nandfs_lbn_t lblknr, nandfs_daddr_t *vblknr, int phys) -{ - struct nandfs_inode *ino; - nandfs_daddr_t ind_block_num; - uint64_t *map; - int idx; - int level; - - ino = node->inode; - - if (lblknr < NANDFS_NDADDR) { - *vblknr = ino->i_db[lblknr]; - return (0); - } - - lblknr -= NANDFS_NDADDR; - - /* - * nindir[0] = NINDIR - * nindir[1] = NINDIR**2 - * nindir[2] = NINDIR**3 - * etc - */ - for (level = 0; level < NANDFS_NIADDR; level++) { - NANDFS_DEBUG("lblknr=%jx fs->nf_nindir[%d]=%d\n", lblknr, level, fs->nf_nindir[level]); - if (lblknr < fs->nf_nindir[level]) - break; - lblknr -= fs->nf_nindir[level]; - } - - if (level == NANDFS_NIADDR) { - /* Block number too high */ - NANDFS_DEBUG("lblknr %jx too high\n", lblknr); - return (EFBIG); - } - - ind_block_num = ino->i_ib[level]; - - for (; level >= 0; level--) { - if (ind_block_num == 0) { - *vblknr = 0; /* missing */ - return (0); - } - - twiddle(1); - NANDFS_DEBUG("calling get_map with %jx\n", ind_block_num); - map = nandfs_get_map(fs, node, ind_block_num, phys); - if (map == NULL) - return (EIO); - - if (level > 0) { - idx = lblknr / fs->nf_nindir[level - 1]; - lblknr %= fs->nf_nindir[level - 1]; - } else - idx = lblknr; - - ind_block_num = ((nandfs_daddr_t *)map)[idx]; - } - - *vblknr = ind_block_num; - - return (0); -} - -static nandfs_daddr_t -nandfs_vtop(struct nandfs *fs, nandfs_daddr_t vblocknr) -{ - nandfs_lbn_t blocknr; - nandfs_daddr_t pblocknr; - int entrynr; - struct nandfs_dat_entry *dat; - - dat = malloc(fs->nf_blocksize); - nandfs_mdt_trans(&fs->nf_datfile_mdt, vblocknr, &blocknr, &entrynr); - - if (nandfs_read_inode(fs, &fs->nf_datfile, blocknr, 1, dat, 1)) { - free(dat); - return (0); - } - - NANDFS_DEBUG("nandfs_vtop entrynr=%d vblocknr=%lld pblocknr=%lld\n", - entrynr, vblocknr, dat[entrynr].de_blocknr); - - pblocknr = dat[entrynr].de_blocknr; - free(dat); - return (pblocknr); -} - -static void -nandfs_calc_mdt_consts(int blocksize, struct nandfs_mdt *mdt, int entry_size) -{ - - mdt->entries_per_group = blocksize * 8; /* bits in sector */ - mdt->entries_per_block = blocksize / entry_size; - mdt->blocks_per_group = - (mdt->entries_per_group -1) / mdt->entries_per_block + 1 + 1; - mdt->groups_per_desc_block = - blocksize / sizeof(struct nandfs_block_group_desc); - mdt->blocks_per_desc_block = - mdt->groups_per_desc_block * mdt->blocks_per_group + 1; -} - -static void -nandfs_mdt_trans(struct nandfs_mdt *mdt, uint64_t index, - nandfs_daddr_t *blocknr, uint32_t *entry_in_block) -{ - nandfs_daddr_t blknr; - uint64_t group, group_offset, blocknr_in_group; - uint64_t desc_block, desc_offset; - - /* Calculate our offset in the file */ - group = index / mdt->entries_per_group; - group_offset = index % mdt->entries_per_group; - desc_block = group / mdt->groups_per_desc_block; - desc_offset = group % mdt->groups_per_desc_block; - blocknr_in_group = group_offset / mdt->entries_per_block; - - /* To descgroup offset */ - blknr = 1 + desc_block * mdt->blocks_per_desc_block; - - /* To group offset */ - blknr += desc_offset * mdt->blocks_per_group; - - /* To actual file block */ - blknr += 1 + blocknr_in_group; - - *blocknr = blknr; - *entry_in_block = group_offset % mdt->entries_per_block; -} - -static int -ioread(struct open_file *f, off_t pos, void *buf, u_int length) -{ - void *buffer; - int err; - int bsize = ((struct nandfs *)f->f_fsdata)->nf_sectorsize; - u_int off, nsec; - - off = pos % bsize; - pos /= bsize; - nsec = howmany(length, bsize); - - NANDFS_DEBUG("pos=%lld length=%d off=%d nsec=%d\n", pos, length, - off, nsec); - - buffer = malloc(nsec * bsize); - - err = (f->f_dev->dv_strategy)(f->f_devdata, F_READ, pos, - nsec * bsize, buffer, NULL); - - memcpy(buf, (void *)((uintptr_t)buffer + off), length); - free(buffer); - - return (err); -} - -static int -nandfs_probe_sectorsize(struct open_file *f) -{ - void *buffer; - int i, err; - - buffer = malloc(16 * 1024); - - NANDFS_DEBUG("probing for sector size: "); - - for (i = 512; i < (16 * 1024); i <<= 1) { - NANDFS_DEBUG("%d ", i); - err = (f->f_dev->dv_strategy)(f->f_devdata, F_READ, 0, i, - buffer, NULL); - - if (err == 0) { - NANDFS_DEBUG("found"); - free(buffer); - return (i); - } - } - - free(buffer); - NANDFS_DEBUG("not found\n"); - return (-1); -} diff --git a/stand/libsa/zfs/devicename_stubs.c b/stand/libsa/zfs/devicename_stubs.c deleted file mode 100644 index 41bf907e0cf..00000000000 --- a/stand/libsa/zfs/devicename_stubs.c +++ /dev/null @@ -1,47 +0,0 @@ -/*- - * Copyright (c) 2012 Andriy Gapon - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include -__FBSDID("$FreeBSD$"); - -#include -#include "libzfs.h" - -__attribute__((weak)) -int -zfs_parsedev(struct zfs_devdesc *dev, const char *devspec, const char **path) -{ - return (EINVAL); -} - -__attribute__((weak)) -char * -zfs_fmtdev(void *vdev) -{ - static char buf[128]; - - return (buf); -} diff --git a/stand/powerpc/uboot/Makefile b/stand/powerpc/uboot/Makefile deleted file mode 100644 index 4787b5a48c6..00000000000 --- a/stand/powerpc/uboot/Makefile +++ /dev/null @@ -1,35 +0,0 @@ -# $FreeBSD$ - -LOADER_UFS_SUPPORT?= yes -LOADER_CD9660_SUPPORT?= no -LOADER_EXT2FS_SUPPORT?= no -LOADER_NET_SUPPORT?= yes -LOADER_NFS_SUPPORT?= yes -LOADER_TFTP_SUPPORT?= no -LOADER_GZIP_SUPPORT?= no -LOADER_BZIP2_SUPPORT?= no - -.include - -PROG= ubldr -NEWVERSWHAT= "U-Boot loader" ${MACHINE_ARCH} -INSTALLFLAGS= -b - -# Architecture-specific loader code -SRCS= start.S conf.c vers.c ppc64_elf_freebsd.c -SRCS+= ucmpdi2.c - -# Always add MI sources -.include "${BOOTSRC}/loader.mk" -.PATH: ${SYSDIR}/libkern - -LDFLAGS= -nostdlib -static -T ${.CURDIR}/ldscript.powerpc - -.include "${BOOTSRC}/uboot.mk" - -DPADD= ${LDR_INTERP} ${LIBUBOOT} ${LIBFDT} ${LIBUBOOT_FDT} ${LIBSA} -LDADD= ${LDR_INTERP} ${LIBUBOOT} ${LIBFDT} ${LIBUBOOT_FDT} ${LIBSA} - -MK_PIE= no - -.include diff --git a/stand/powerpc/uboot/conf.c b/stand/powerpc/uboot/conf.c deleted file mode 100644 index 49658a47cbd..00000000000 --- a/stand/powerpc/uboot/conf.c +++ /dev/null @@ -1,114 +0,0 @@ -/*- - * Copyright (c) 1999 Michael Smith - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include -__FBSDID("$FreeBSD$"); - -#include -#include "bootstrap.h" -#include "libuboot.h" - -#if defined(LOADER_NET_SUPPORT) -#include "dev_net.h" -#endif - -/* Make sure we have an explicit reference to exit so libsa's panic pulls in the MD exit */ -void (*exitfn)(int) = exit; - -/* - * We could use linker sets for some or all of these, but - * then we would have to control what ended up linked into - * the bootstrap. So it's easier to conditionalise things - * here. - * - * XXX rename these arrays to be consistent and less namespace-hostile - */ - -/* Exported for libstand */ -struct devsw *devsw[] = { -#if defined(LOADER_DISK_SUPPORT) || defined(LOADER_CD9660_SUPPORT) - &uboot_storage, -#endif -#if defined(LOADER_NET_SUPPORT) - &netdev, -#endif - NULL -}; - -struct fs_ops *file_system[] = { -#if defined(LOADER_UFS_SUPPORT) - &ufs_fsops, -#endif -#if defined(LOADER_CD9660_SUPPORT) - &cd9660_fsops, -#endif -#if defined(LOADER_EXT2FS_SUPPORT) - &ext2fs_fsops, -#endif -#if defined(LOADER_NFS_SUPPORT) - &nfs_fsops, -#endif -#if defined(LOADER_TFTP_SUPPORT) - &tftp_fsops, -#endif -#if defined(LOADER_GZIP_SUPPORT) - &gzipfs_fsops, -#endif -#if defined(LOADER_BZIP2_SUPPORT) - &bzipfs_fsops, -#endif - NULL -}; - -struct netif_driver *netif_drivers[] = { -#if defined(LOADER_NET_SUPPORT) - &uboot_net, -#endif - NULL, -}; - -/* Exported for PowerPC only */ -/* - * Sort formats so that those that can detect based on arguments - * rather than reading the file go first. - */ -extern struct file_format uboot_elf64; - -struct file_format *file_formats[] = { - &uboot_elf, - &uboot_elf64, - NULL -}; - -/* - * Consoles - */ -extern struct console uboot_console; - -struct console *consoles[] = { - &uboot_console, - NULL -}; diff --git a/stand/powerpc/uboot/ldscript.powerpc b/stand/powerpc/uboot/ldscript.powerpc deleted file mode 100644 index 92383836579..00000000000 --- a/stand/powerpc/uboot/ldscript.powerpc +++ /dev/null @@ -1,138 +0,0 @@ -/* $FreeBSD$ */ - -OUTPUT_FORMAT("elf32-powerpc-freebsd", "elf32-powerpc-freebsd", - "elf32-powerpc-freebsd") -OUTPUT_ARCH(powerpc:common) -ENTRY(_start) -SEARCH_DIR(/usr/lib); -PROVIDE (__stack = 0); -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = 0x00010000 + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .gnu.version : { *(.gnu.version) } - .gnu.version_d : { *(.gnu.version_d) } - .gnu.version_r : { *(.gnu.version_r) } - .rela.text : - { *(.rela.text) *(.rela.gnu.linkonce.t*) } - .rela.data : - { *(.rela.data) *(.rela.gnu.linkonce.d*) } - .rela.rodata : - { *(.rela.rodata) *(.rela.gnu.linkonce.r*) } - .rela.got : { *(.rela.got) } - .rela.got1 : { *(.rela.got1) } - .rela.got2 : { *(.rela.got2) } - .rela.ctors : { *(.rela.ctors) } - .rela.dtors : { *(.rela.dtors) } - .rela.init : { *(.rela.init) } - .rela.fini : { *(.rela.fini) } - .rela.bss : { *(.rela.bss) } - .rela.plt : { *(.rela.plt) } - .rela.sdata : { *(.rela.sdata) } - .rela.sbss : { *(.rela.sbss) } - .rela.sdata2 : { *(.rela.sdata2) } - .rela.sbss2 : { *(.rela.sbss2) } - .text : - { - *(.text) - /* .gnu.warning sections are handled specially by elf32.em. */ - *(.gnu.warning) - *(.gnu.linkonce.t*) - } =0 - _etext = .; - PROVIDE (etext = .); - .init : { *(.init) } =0 - .fini : { *(.fini) } =0 - .rodata : { *(.rodata) *(.gnu.linkonce.r*) } - .rodata1 : { *(.rodata1) } - .sdata2 : { *(.sdata2) } - .sbss2 : { *(.sbss2) } - /* Adjust the address for the data segment to the next page up. */ - . = ((. + 0x1000) & ~(0x1000 - 1)); - .data : - { - *(.data) - *(.gnu.linkonce.d*) - CONSTRUCTORS - } - .data1 : { *(.data1) } - .got1 : { *(.got1) } - .dynamic : { *(.dynamic) } - /* Put .ctors and .dtors next to the .got2 section, so that the pointers - get relocated with -mrelocatable. Also put in the .fixup pointers. - The current compiler no longer needs this, but keep it around for 2.7.2 */ - PROVIDE (_GOT2_START_ = .); - .got2 : { *(.got2) } - PROVIDE (__CTOR_LIST__ = .); - .ctors : { *(.ctors) } - PROVIDE (__CTOR_END__ = .); - PROVIDE (__DTOR_LIST__ = .); - .dtors : { *(.dtors) } - PROVIDE (__DTOR_END__ = .); - PROVIDE (_FIXUP_START_ = .); - .fixup : { *(.fixup) } - PROVIDE (_FIXUP_END_ = .); - PROVIDE (_GOT2_END_ = .); - PROVIDE (_GOT_START_ = .); - .got : { *(.got) } - .got.plt : { *(.got.plt) } - PROVIDE (_GOT_END_ = .); - /* We want the small data sections together, so single-instruction offsets - can access them all, and initialized data all before uninitialized, so - we can shorten the on-disk segment size. */ - .sdata : { *(.sdata) } - _edata = .; - PROVIDE (edata = .); - .sbss : - { - PROVIDE (__sbss_start = .); - *(.sbss) - *(.scommon) - *(.dynsbss) - PROVIDE (__sbss_end = .); - } - .plt : { *(.plt) } - .bss : - { - PROVIDE (__bss_start = .); - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); - /* Stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - /* DWARF debug sections. - Symbols in the DWARF debugging sections are relative to the beginning - of the section so we begin them at 0. */ - /* DWARF 1 */ - .debug 0 : { *(.debug) } - .line 0 : { *(.line) } - /* GNU DWARF 1 extensions */ - .debug_srcinfo 0 : { *(.debug_srcinfo) } - .debug_sfnames 0 : { *(.debug_sfnames) } - /* DWARF 1.1 and DWARF 2 */ - .debug_aranges 0 : { *(.debug_aranges) } - .debug_pubnames 0 : { *(.debug_pubnames) } - /* DWARF 2 */ - .debug_info 0 : { *(.debug_info) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_line 0 : { *(.debug_line) } - .debug_frame 0 : { *(.debug_frame) } - .debug_str 0 : { *(.debug_str) } - .debug_loc 0 : { *(.debug_loc) } - .debug_macinfo 0 : { *(.debug_macinfo) } - /* SGI/MIPS DWARF 2 extensions */ - .debug_weaknames 0 : { *(.debug_weaknames) } - .debug_funcnames 0 : { *(.debug_funcnames) } - .debug_typenames 0 : { *(.debug_typenames) } - .debug_varnames 0 : { *(.debug_varnames) } - /* These must appear regardless of . */ -} - diff --git a/stand/powerpc/uboot/ppc64_elf_freebsd.c b/stand/powerpc/uboot/ppc64_elf_freebsd.c deleted file mode 100644 index 57b2e791fbb..00000000000 --- a/stand/powerpc/uboot/ppc64_elf_freebsd.c +++ /dev/null @@ -1,101 +0,0 @@ -/*- - * Copyright (c) 2001 Benno Rice - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include -__FBSDID("$FreeBSD$"); - -#define __ELF_WORD_SIZE 64 - -#include -#include - -#include -#include -#include - -#include - -#include "bootstrap.h" -#include "libuboot.h" - -vm_offset_t md_load64(char *args, vm_offset_t *modulep, vm_offset_t *dtb); -extern char end[]; -extern vm_offset_t reloc; /* From /conf.c */ - -int -ppc64_uboot_elf_loadfile(char *filename, uint64_t dest, - struct preloaded_file **result) -{ - int r; - - r = __elfN(loadfile)(filename, dest, result); - if (r != 0) - return (r); - - /* - * No need to sync the icache for modules: this will - * be done by the kernel after relocation. - */ - if (!strcmp((*result)->f_type, "elf kernel")) - __syncicache((void *) (*result)->f_addr, (*result)->f_size); - return (0); -} - -int -ppc64_uboot_elf_exec(struct preloaded_file *fp) -{ - struct file_metadata *fmp; - vm_offset_t mdp, dtbp; - Elf_Ehdr *e; - int error; - void (*entry)(void *); - - if ((fmp = file_findmetadata(fp, MODINFOMD_ELFHDR)) == NULL) { - return(EFTYPE); - } - e = (Elf_Ehdr *)&fmp->md_data; - - /* Handle function descriptor for ELFv1 kernels */ - if ((e->e_flags & 3) == 2) - entry = (void (*)(void*))(intptr_t)e->e_entry; - else - entry = *(void (*)(void*))(uint64_t *)(intptr_t)e->e_entry; - - if ((error = md_load64(fp->f_args, &mdp, &dtbp)) != 0) - return (error); - - dev_cleanup(); - printf("Kernel args: %s\n", fp->f_args); - - (*entry)((void *)mdp); - panic("exec returned"); -} - -struct file_format uboot_elf64 = -{ - ppc64_uboot_elf_loadfile, - ppc64_uboot_elf_exec -}; diff --git a/stand/powerpc/uboot/start.S b/stand/powerpc/uboot/start.S deleted file mode 100644 index 3e80576907a..00000000000 --- a/stand/powerpc/uboot/start.S +++ /dev/null @@ -1,94 +0,0 @@ -/*- - * Copyright (c) 2007 Semihalf, Rafal Jaworowski - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * $FreeBSD$ - */ - -#include - -/* - * Entry point to the loader that U-Boot passes control to. - */ - .text - .globl _start -_start: - /* Hint where to look for the API signature */ - lis %r11, uboot_address@ha - addi %r11, %r11, uboot_address@l - stw %r1, 0(%r11) - /* Save U-Boot's r14 */ - lis %r11, saved_regs@ha - addi %r11, %r11, saved_regs@l - stw %r14, 0(%r11) - /* Disable interrupts */ - mfmsr %r11 - andi. %r11, %r11, ~0x8000@l - mtmsr %r11 - b main - -/* - * syscall() - */ -ENTRY(syscall) - stwu %r1, -16(%r1) - mflr %r0 - stw %r14, 8(%r1) - stw %r0, 20(%r1) - /* Restore U-Boot's r14 */ - lis %r11, saved_regs@ha - addi %r11, %r11, saved_regs@l - lwz %r14, 0(%r11) - /* Enable interrupts */ - mfmsr %r11 - ori %r11, %r11, 0x8000@l - mtmsr %r11 - /* Call into U-Boot */ - lis %r11, syscall_ptr@ha - addi %r11, %r11, syscall_ptr@l - lwz %r11, 0(%r11) - mtctr %r11 - bctrl - /* Disable interrupts */ - mfmsr %r11 - andi. %r11, %r11, ~0x8000@l - mtmsr %r11 - /* Epilogue */ - lwz %r11, 0(%r1) - lwz %r0, 4(%r11) - mtlr %r0 - lwz %r14, 8(%r1) - mr %r1, %r11 - blr - -/* - * Data section - */ - .data -GLOBAL(syscall_ptr) - .long 0 -GLOBAL(saved_regs) - .long 0 /* R14 */ -GLOBAL(uboot_address) - .long 0 diff --git a/stand/powerpc/uboot/version b/stand/powerpc/uboot/version deleted file mode 100644 index 21556cff70e..00000000000 --- a/stand/powerpc/uboot/version +++ /dev/null @@ -1,11 +0,0 @@ -$FreeBSD$ - -NOTE ANY CHANGES YOU MAKE TO THE BOOTBLOCKS HERE. The format of this -file is important. Make sure the current version number is on line 6. - -1.1: Flattened Device Tree blob support. -1.0: Added storage support. -0.6: Integrated with the new U-Boot API -0.5: Full network functionality. -0.2: Initial U-Boot/PowerPC version derived from the existing - OpenFirmware-based. diff --git a/sys/arm/ti/omap4/omap4var.h b/sys/arm/ti/omap4/omap4var.h deleted file mode 100644 index 95e5e47a3d7..00000000000 --- a/sys/arm/ti/omap4/omap4var.h +++ /dev/null @@ -1,91 +0,0 @@ -/*- - * Copyright (c) 2010 - * Ben Gray . - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the company nor the name of the author may be used to - * endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY BEN GRAY ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL BEN GRAY BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF - * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * $FreeBSD: stable/10/sys/arm/ti/omap4/omap4var.h 239281 2012-08-15 06:31:32Z gonzo $ - */ - -#ifndef _OMAP4VAR_H_ -#define _OMAP4VAR_H_ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - - -void omap4_mask_all_intr(void); -void omap4_post_filter_intr(void *arg); - -struct omap4_softc { - device_t sc_dev; - bus_space_tag_t sc_iotag; - - /* Handles for the two generic interrupt controller (GIC) register mappings */ - bus_space_handle_t sc_gic_cpu_ioh; - bus_space_handle_t sc_gic_dist_ioh; - - /* Handle for the PL310 L2 cache controller */ - bus_space_handle_t sc_pl310_ioh; - - /* Handle for the global and provate timer register set in the Cortex core */ - bus_space_handle_t sc_prv_timer_ioh; - bus_space_handle_t sc_gbl_timer_ioh; - - /* SCM access */ - struct resource *sc_scm_mem; - int sc_scm_rid; -}; - -struct omap4_intr_conf { - int num; - unsigned int priority; - unsigned int target_cpu; -}; - -int omap4_setup_intr_controller(device_t dev, - const struct omap4_intr_conf *irqs); -int omap4_setup_gic_cpu(unsigned int prio_mask); - -void omap4_init_timer(device_t dev); - -int omap4_setup_l2cache_controller(struct omap4_softc *sc); -void omap4_smc_call(uint32_t fn, uint32_t arg); - -#endif /* _OMAP4VAR_H_ */ diff --git a/sys/arm/ti/omap4/pandaboard/files.pandaboard b/sys/arm/ti/omap4/pandaboard/files.pandaboard deleted file mode 100644 index 379a1ede0b0..00000000000 --- a/sys/arm/ti/omap4/pandaboard/files.pandaboard +++ /dev/null @@ -1,3 +0,0 @@ -# $FreeBSD: stable/11/sys/arm/ti/omap4/pandaboard/files.pandaboard 239281 2012-08-15 06:31:32Z gonzo $ - -arm/ti/omap4/pandaboard/pandaboard.c standard diff --git a/sys/arm/ti/omap4/pandaboard/std.pandaboard b/sys/arm/ti/omap4/pandaboard/std.pandaboard deleted file mode 100644 index 65bac38cd07..00000000000 --- a/sys/arm/ti/omap4/pandaboard/std.pandaboard +++ /dev/null @@ -1,4 +0,0 @@ -# $FreeBSD: stable/11/sys/arm/ti/omap4/pandaboard/std.pandaboard 239281 2012-08-15 06:31:32Z gonzo $ - -include "../ti/omap4/std.omap4" -files "../ti/omap4/pandaboard/files.pandaboard" diff --git a/sys/arm64/linux/linux_ptrace.c b/sys/arm64/linux/linux_ptrace.c deleted file mode 100644 index 7acf234aa52..00000000000 --- a/sys/arm64/linux/linux_ptrace.c +++ /dev/null @@ -1,54 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (C) 2018 Turing Robotic Industries Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - */ - -#include - -#include -#include -#include -#include -#include - -#include -#include -#include - -/* DTrace init */ -LIN_SDT_PROVIDER_DECLARE(LINUX_DTRACE); - -/* DTrace probes */ -LIN_SDT_PROBE_DEFINE0(ptrace, linux_ptrace, todo); - -int -linux_ptrace(struct thread *td, struct linux_ptrace_args *uap) -{ - - /* LINUXTODO: implement arm64 linux_ptrace */ - LIN_SDT_PROBE0(ptrace, linux_ptrace, todo); - return (EDOOFUS); -} diff --git a/sys/compat/freebsd32/capabilities.conf b/sys/compat/freebsd32/capabilities.conf deleted file mode 100644 index c171035327f..00000000000 --- a/sys/compat/freebsd32/capabilities.conf +++ /dev/null @@ -1,286 +0,0 @@ -## -## Copyright (c) 2008-2010 Robert N. M. Watson -## Copyright (c) 2016 The FreeBSD Foundation -## All rights reserved. -## -## This software was developed at the University of Cambridge Computer -## Laboratory with support from a grant from Google, Inc. -## -## Portions of this software were developed by Konstantin Belousov -## under sponsorship from the FreeBSD Foundation. -## -## Redistribution and use in source and binary forms, with or without -## modification, are permitted provided that the following conditions -## are met: -## 1. Redistributions of source code must retain the above copyright -## notice, this list of conditions and the following disclaimer. -## 2. Redistributions in binary form must reproduce the above copyright -## notice, this list of conditions and the following disclaimer in the -## documentation and/or other materials provided with the distribution. -## -## THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND -## ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -## ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE -## FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -## DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -## OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -## HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -## LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -## OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -## SUCH DAMAGE. -## -## List of system calls enabled in freebsd32 capability mode, one name -## per line. See the original list in the sys/kern/capabilities.conf. -## Position of the compat syscall in this file must be identical to -## the master, to facilitate comparision and diagnostic. -## -## $FreeBSD: stable/11/sys/compat/freebsd32/capabilities.conf 338728 2018-09-17 18:46:30Z emaste $ -## - -__acl_aclcheck_fd -__acl_delete_fd -__acl_get_fd -__acl_set_fd -__mac_get_fd -#__mac_get_pid -__mac_get_proc -__mac_set_fd -__mac_set_proc -freebsd32_sysctl -freebsd32_umtx_op -abort2 -accept -accept4 -aio_cancel -freebsd32_aio_error -aio_fsync -freebsd32_aio_read -freebsd32_aio_return -freebsd32_aio_suspend -freebsd32_aio_waitcomplete -freebsd32_aio_write -#audit -bindat -cap_enter -cap_fcntls_get -cap_fcntls_limit -cap_getmode -freebsd32_cap_ioctls_get -freebsd32_cap_ioctls_limit -__cap_rights_get -cap_rights_limit -freebsd32_clock_getres -freebsd32_clock_gettime -close -closefrom -connectat -#cpuset -freebsd32_cpuset_getaffinity -#freebsd32_cpuset_getid -freebsd32_cpuset_setaffinity -#freebsd32_cpuset_setid -dup -dup2 -extattr_delete_fd -extattr_get_fd -extattr_list_fd -extattr_set_fd -fchflags -fchmod -fchown -freebsd32_fcntl -freebsd32_fexecve -flock -fork -fpathconf -freebsd6_freebsd32_ftruncate -freebsd6_freebsd32_lseek -freebsd6_freebsd32_mmap -freebsd6_freebsd32_pread -freebsd6_freebsd32_pwrite -freebsd32_fstat -fstatfs -fsync -ftruncate -freebsd32_ftruncate -freebsd32_futimens -freebsd32_futimes -getaudit -getaudit_addr -getauid -freebsd32_getcontext -getdents -freebsd32_getdirentries -getdomainname -getdtablesize -getegid -geteuid -gethostid -gethostname -freebsd32_getitimer -getgid -getgroups -getlogin -freebsd32_getpagesize -getpeername -getpgid -getpgrp -getpid -getppid -getpriority -getresgid -getresuid -getrlimit -freebsd32_getrusage -getsid -getsockname -getsockopt -freebsd32_gettimeofday -getuid -freebsd32_ioctl -issetugid -freebsd32_kevent -kill -freebsd32_kmq_notify -freebsd32_kmq_setattr -freebsd32_kmq_timedreceive -freebsd32_kmq_timedsend -kqueue -freebsd32_ktimer_create -ktimer_delete -ktimer_getoverrun -freebsd32_ktimer_gettime -freebsd32_ktimer_settime -#ktrace -freebsd32_lio_listio -listen -freebsd32_lseek -madvise -mincore -minherit -mlock -mlockall -freebsd32_mmap -freebsd32_mprotect -msync -munlock -munlockall -munmap -freebsd32_nanosleep -ntp_gettime -freebsd6_freebsd32_aio_read -freebsd6_freebsd32_aio_write -obreak -freebsd6_freebsd32_lio_listio -chflagsat -faccessat -fchmodat -fchownat -freebsd32_fstatat -freebsd32_futimesat -linkat -mkdirat -mkfifoat -mknodat -openat -readlinkat -renameat -symlinkat -unlinkat -freebsd32_utimensat -open -pdfork -pdgetpid -pdkill -#pdwait4 # not yet implemented -freebsd32_pipe -pipe2 -poll -freebsd32_posix_fallocate -freebsd32_pread -freebsd32_preadv -profil -#ptrace -freebsd32_pwrite -freebsd32_pwritev -read -freebsd32_readv -freebsd6_freebsd32_recv -freebsd32_recvfrom -freebsd32_recvmsg -rtprio -rtprio_thread -sbrk -sched_get_priority_max -sched_get_priority_min -sched_getparam -sched_getscheduler -sched_rr_get_interval -sched_setparam -sched_setscheduler -sched_yield -sctp_generic_recvmsg -sctp_generic_sendmsg -sctp_generic_sendmsg_iov -sctp_peeloff -freebsd32_pselect -freebsd32_select -freebsd6_freebsd32_send -freebsd32_sendfile -freebsd32_sendmsg -sendto -setaudit -setaudit_addr -setauid -freebsd32_setcontext -setegid -seteuid -setgid -freebsd32_setitimer -setpriority -setregid -setresgid -setresuid -setreuid -setrlimit -setsid -setsockopt -setuid -shm_open -shutdown -freebsd32_sigaction -freebsd32_sigaltstack -freebsd32_sigblock -freebsd32_sigpending -sigprocmask -sigqueue -freebsd32_sigreturn -freebsd32_sigsetmask -ofreebsd32_sigstack -sigsuspend -freebsd32_sigtimedwait -freebsd32_sigvec -freebsd32_sigwaitinfo -sigwait -socket -socketpair -sstk -sync -sys_exit -freebsd32_sysarch -thr_create -thr_exit -thr_kill -#thr_kill2 -freebsd32_thr_new -thr_self -thr_set_name -freebsd32_thr_suspend -thr_wake -umask -utrace -uuidgen -write -freebsd32_writev -yield diff --git a/sys/compat/ia32/ia32_reg.h b/sys/compat/ia32/ia32_reg.h deleted file mode 100644 index ad959bcd76f..00000000000 --- a/sys/compat/ia32/ia32_reg.h +++ /dev/null @@ -1,117 +0,0 @@ -/*- - * Copyright (c) 1990 The Regents of the University of California. - * All rights reserved. - * - * This code is derived from software contributed to Berkeley by - * William Jolitz. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 4. Neither the name of the University nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * from: @(#)reg.h 5.5 (Berkeley) 1/18/91 - */ - -#ifndef _COMPAT_IA32_IA32_REG_H_ -#define _COMPAT_IA32_IA32_REG_H_ - -/* - * Register set accessible via /proc/$pid/regs and PT_{SET,GET}REGS. - */ -struct reg32 { - unsigned int r_fs; - unsigned int r_es; - unsigned int r_ds; - unsigned int r_edi; - unsigned int r_esi; - unsigned int r_ebp; - unsigned int r_isp; - unsigned int r_ebx; - unsigned int r_edx; - unsigned int r_ecx; - unsigned int r_eax; - unsigned int r_trapno; - unsigned int r_err; - unsigned int r_eip; - unsigned int r_cs; - unsigned int r_eflags; - unsigned int r_esp; - unsigned int r_ss; - unsigned int r_gs; -}; - -/* - * Register set accessible via /proc/$pid/fpregs. - */ -struct fpreg32 { - unsigned int fpr_env[7]; - unsigned char fpr_acc[8][10]; - unsigned int fpr_ex_sw; - unsigned char fpr_pad[64]; -}; - -/* - * Register set accessible via /proc/$pid/dbregs. - */ -struct dbreg32 { - unsigned int dr[8]; /* debug registers */ -}; - -/* Environment information of floating point unit */ -struct env87 { - int en_cw; /* control word (16bits) */ - int en_sw; /* status word (16bits) */ - int en_tw; /* tag word (16bits) */ - int en_fip; /* floating point instruction pointer */ - u_short en_fcs; /* floating code segment selector */ - u_short en_opcode; /* opcode last executed (11 bits ) */ - int en_foo; /* floating operand offset */ - int en_fos; /* floating operand segment selector */ -}; - -#ifdef __ia64__ -/* Layout of an x87 fpu register (amd64 gets this elsewhere) */ -struct fpacc87 { - u_char fp_bytes[10]; -}; -#endif - -/* Floating point context */ -struct save87 { - struct env87 sv_env; /* floating point control/status */ - struct fpacc87 sv_ac[8]; /* accumulator contents, 0-7 */ - u_char sv_pad0[4]; /* padding for (now unused) saved status word */ - u_char sv_pad[64]; /* padding; used by emulators */ -}; - -/* - * Wrappers and converters. - */ -int fill_regs32(struct thread *, struct reg32 *); -int set_regs32(struct thread *, struct reg32 *); -int fill_fpregs32(struct thread *, struct fpreg32 *); -int set_fpregs32(struct thread *, struct fpreg32 *); -int fill_dbregs32(struct thread *, struct dbreg32 *); -int set_dbregs32(struct thread *, struct dbreg32 *); - -#endif /* !_COMPAT_IA32_IA32_REG_H_ */ diff --git a/sys/compat/netbsd/dvcfg.h b/sys/compat/netbsd/dvcfg.h deleted file mode 100644 index 5e569c6c0ca..00000000000 --- a/sys/compat/netbsd/dvcfg.h +++ /dev/null @@ -1,66 +0,0 @@ -/* $NetBSD$ */ -/*- - * SPDX-License-Identifier: BSD-3-Clause - * - * [NetBSD for NEC PC98 series] - * Copyright (c) 1996 NetBSD/pc98 porting staff. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ -/* - * Copyright (c) 1996 Naofumi HONDA. All rights reserved. - */ - -#ifndef _COMPAT_NETBSD_DVCFG_H_ -#define _COMPAT_NETBSD_DVCFG_H_ - -typedef void *dvcfg_hw_t; - -struct dvcfg_hwsel { - int cfg_max; - - dvcfg_hw_t *cfg_sel; -}; - -#define DVCFG_MAJOR(dvcfg) (((u_int)(dvcfg)) >> 16) -#define DVCFG_MINOR(dvcfg) (((u_int)(dvcfg)) & 0xffff) - -#define DVCFG_MKCFG(major, minor) ((((u_int)(major)) << 16) | ((minor) & 0xffff)) - -#define DVCFG_HWSEL_SZ(array) (sizeof(array) / sizeof(dvcfg_hw_t)) - -static __inline dvcfg_hw_t dvcfg_hw(struct dvcfg_hwsel *, u_int); - -static __inline dvcfg_hw_t -dvcfg_hw(selp, num) - struct dvcfg_hwsel *selp; - u_int num; -{ - - return ((num >= selp->cfg_max) ? 0 : selp->cfg_sel[num]); -} - -#define DVCFG_HW(SELP, NUM) dvcfg_hw((SELP), (NUM)) -#endif /* _COMPAT_NETBSD_DVCFG_H_ */ diff --git a/sys/compat/netbsd/physio_proc.h b/sys/compat/netbsd/physio_proc.h deleted file mode 100644 index ef14efd5a06..00000000000 --- a/sys/compat/netbsd/physio_proc.h +++ /dev/null @@ -1,57 +0,0 @@ -/* $FreeBSD: src/sys/compat/netbsd/physio_proc.h,v 1.7 2005/01/05 22:34:36 imp Exp $ */ -/* $NecBSD: physio_proc.h,v 3.4 1999/07/23 20:47:03 honda Exp $ */ -/* $NetBSD$ */ - -/*- - * [NetBSD for NEC PC-98 series] - * Copyright (c) 1998 - * NetBSD/pc98 porting staff. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _COMPAT_NETBSD_PHYSIO_PROC_H_ -#define _COMPAT_NETBSD_PHYSIO_PROC_H_ -#include - -struct buf; - -struct physio_proc { -}; - -static __inline struct physio_proc *physio_proc_enter(struct buf *); -static __inline void physio_proc_leave(struct physio_proc *); - -static __inline struct physio_proc * -physio_proc_enter(bp) - struct buf *bp; -{ - return NULL; -} - -static __inline void -physio_proc_leave(pp) - struct physio_proc *pp; -{ -} -#endif /* _COMPAT_NETBSD_PHYSIO_PROC_H_ */ diff --git a/sys/compat/svr4/Makefile b/sys/compat/svr4/Makefile deleted file mode 100644 index 2311b9c9ccf..00000000000 --- a/sys/compat/svr4/Makefile +++ /dev/null @@ -1,22 +0,0 @@ -# Makefile for syscall tables -# -# $FreeBSD: stable/11/sys/compat/svr4/Makefile 357108 2020-01-25 05:47:56Z kevans $ - -# Don't use an OBJDIR -.OBJDIR: ${.CURDIR} - -MAKESYSCALLS= ../../kern/makesyscalls.sh -GENERATED= svr4_sysent.c \ - svr4_syscall.h \ - svr4_syscallnames.c \ - svr4_proto.h - -all: - @echo "make sysent only" - -.ORDER: ${GENERATED} -sysent: ${GENERATED} - -${GENERATED}: ${MAKESYSCALLS} syscalls.master syscalls.conf - sh ${MAKESYSCALLS} syscalls.master syscalls.conf - diff --git a/sys/compat/svr4/README b/sys/compat/svr4/README deleted file mode 100644 index 44c03f1ba52..00000000000 --- a/sys/compat/svr4/README +++ /dev/null @@ -1,38 +0,0 @@ -This is a SysVR4 emulator derived from work done as part of the NetBSD -Project by Christos Zoulas. It has been ported to FreeBSD by Mark Newton. - -To use it: - -1. Choose one of: - a. Add "device streams" to your kernel config file and rebuild, - reboot; or - b. Build and install the streams module in /sys/modules/streams - -2. Build and install the svr4 module in /sys/modules/svr4 - -3. Type "kldload svr4" to start it up. - -4. Grab compat_sol26.tar.gz or compat_svr4.tar.gz from - http://www.freebsd.org/~newton/freebsd-svr4 and install them in - /compat/svr4 - -5. Run "sh SVR4_MAKEDEV all" in /compat/svr4/dev - -6. Mount a Solaris/x86 v2.6 or v7 CD-ROM on /cdrom (also works with - v2.4 and v2.5.1, but you need different symlinks in /compat/svr4) - -7. Brand any executables you want to run, and/or set the - kern.fallback_elf_brand sysctl to 'SVR4' to establish this as the - default emulator for unbranded executables. - -8. See if your SysVR4 programs work. - -It's early days yet, folks -- You'll probably have trouble getting 100% -functionality out of most things (specifically, poll() on a socket doesn't -look like it works at the moment, so Netscape doesn't work (among other -things)). Patches will be appreciated. - - - Mark Newton - newton@atdot.dotat.org - -$FreeBSD: stable/11/sys/compat/svr4/README 274185 2014-11-06 16:52:51Z imp $ diff --git a/sys/compat/svr4/TO-DO b/sys/compat/svr4/TO-DO deleted file mode 100644 index 9a971942384..00000000000 --- a/sys/compat/svr4/TO-DO +++ /dev/null @@ -1,15 +0,0 @@ -TO-DO list ----------- - - * svr4_getdents64() doesn't work properly in 'large' directories. - - * signals are still suspect - - * networking is notworking - - * VM86 and USER_LDT are currently disabled (low-priority) - - * Make SysV emulator use SysV shared memory support (duh) - - -$FreeBSD: stable/11/sys/compat/svr4/TO-DO 274185 2014-11-06 16:52:51Z imp $ diff --git a/sys/compat/svr4/imgact_svr4.c b/sys/compat/svr4/imgact_svr4.c deleted file mode 100644 index 1a7640f5741..00000000000 --- a/sys/compat/svr4/imgact_svr4.c +++ /dev/null @@ -1,237 +0,0 @@ -/*- - * Copyright (c) 1998 Mark Newton - * Copyright (c) 1994-1996 Søren Schmidt - * All rights reserved. - * - * Based heavily on /sys/kern/imgact_aout.c which is: - * Copyright (c) 1993, David Greenman - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer - * in this position and unchanged. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#include - -static int exec_svr4_imgact(struct image_params *iparams); - -static int -exec_svr4_imgact(imgp) - struct image_params *imgp; -{ - const struct exec *a_out = (const struct exec *) imgp->image_header; - struct vmspace *vmspace; - vm_offset_t vmaddr; - unsigned long virtual_offset, file_offset; - unsigned long bss_size; - ssize_t aresid; - int error; - - if (((a_out->a_magic >> 16) & 0xff) != 0x64) - return -1; - - /* - * Set file/virtual offset based on a.out variant. - */ - switch ((int)(a_out->a_magic & 0xffff)) { - case 0413: - virtual_offset = 0; - file_offset = 1024; - break; - case 0314: - virtual_offset = 4096; - file_offset = 0; - break; - default: - return (-1); - } - bss_size = round_page(a_out->a_bss); -#ifdef DEBUG - printf("imgact: text: %08lx, data: %08lx, bss: %08lx\n", (u_long)a_out->a_text, (u_long)a_out->a_data, bss_size); -#endif - - /* - * Check various fields in header for validity/bounds. - */ - if (a_out->a_entry < virtual_offset || - a_out->a_entry >= virtual_offset + a_out->a_text || - a_out->a_text & PAGE_MASK || a_out->a_data & PAGE_MASK) - return (-1); - - /* text + data can't exceed file size */ - if (a_out->a_data + a_out->a_text > imgp->attr->va_size) - return (EFAULT); - /* - * text/data/bss must not exceed limits - */ - PROC_LOCK(imgp->proc); - if (a_out->a_text > maxtsiz || - a_out->a_data + bss_size > lim_cur_proc(imgp->proc, RLIMIT_DATA) || - racct_set(imgp->proc, RACCT_DATA, a_out->a_data + bss_size) != 0) { - PROC_UNLOCK(imgp->proc); - return (ENOMEM); - } - PROC_UNLOCK(imgp->proc); - - VOP_UNLOCK(imgp->vp, 0); - - /* - * Destroy old process VM and create a new one (with a new stack) - */ - error = exec_new_vmspace(imgp, &svr4_sysvec); - if (error) - goto fail; - vmspace = imgp->proc->p_vmspace; - - /* - * Check if file_offset page aligned,. - * Currently we cannot handle misalinged file offsets, - * and so we read in the entire image (what a waste). - */ - if (file_offset & PAGE_MASK) { -#ifdef DEBUG - printf("imgact: Non page aligned binary %lu\n", file_offset); -#endif - /* - * Map text+data+bss read/write/execute - */ - vmaddr = virtual_offset; - error = vm_map_find(&vmspace->vm_map, NULL, 0, &vmaddr, - a_out->a_text + a_out->a_data + bss_size, 0, VMFS_NO_SPACE, - VM_PROT_ALL, VM_PROT_ALL, 0); - if (error) - goto fail; - - error = vn_rdwr(UIO_READ, imgp->vp, (void *)vmaddr, file_offset, - a_out->a_text + a_out->a_data, UIO_USERSPACE, 0, - curthread->td_ucred, NOCRED, &aresid, curthread); - if (error != 0) - goto fail; - if (aresid != 0) { - error = ENOEXEC; - goto fail; - } - - /* - * remove write enable on the 'text' part - */ - error = vm_map_protect(&vmspace->vm_map, - vmaddr, - vmaddr + a_out->a_text, - VM_PROT_EXECUTE|VM_PROT_READ, - TRUE); - if (error) - goto fail; - } - else { -#ifdef DEBUG - printf("imgact: Page aligned binary %lu\n", file_offset); -#endif - /* - * Map text+data read/execute - */ - vmaddr = virtual_offset; - error = vm_mmap(&vmspace->vm_map, &vmaddr, - a_out->a_text + a_out->a_data, - VM_PROT_READ | VM_PROT_EXECUTE, - VM_PROT_ALL, - MAP_PRIVATE | MAP_FIXED, - OBJT_VNODE, imgp->vp, file_offset); - if (error) - goto fail; - -#ifdef DEBUG - printf("imgact: startaddr=%08lx, length=%08lx\n", (u_long)vmaddr, - (u_long)a_out->a_text + a_out->a_data); -#endif - /* - * allow read/write of data - */ - error = vm_map_protect(&vmspace->vm_map, - vmaddr + a_out->a_text, - vmaddr + a_out->a_text + a_out->a_data, - VM_PROT_ALL, - FALSE); - if (error) - goto fail; - - /* - * Allocate anon demand-zeroed area for uninitialized data - */ - if (bss_size != 0) { - vmaddr = virtual_offset + a_out->a_text + a_out->a_data; - error = vm_map_find(&vmspace->vm_map, NULL, 0, &vmaddr, - bss_size, 0, VMFS_NO_SPACE, VM_PROT_ALL, VM_PROT_ALL, 0); - if (error) - goto fail; -#ifdef DEBUG - printf("imgact: bssaddr=%08lx, length=%08lx\n", - (u_long)vmaddr, bss_size); -#endif - - } - } - /* Fill in process VM information */ - vmspace->vm_tsize = round_page(a_out->a_text) >> PAGE_SHIFT; - vmspace->vm_dsize = round_page(a_out->a_data + bss_size) >> PAGE_SHIFT; - vmspace->vm_taddr = (caddr_t)virtual_offset; - vmspace->vm_daddr = (caddr_t)virtual_offset + a_out->a_text; - - /* Fill in image_params */ - imgp->interpreted = 0; - imgp->entry_addr = a_out->a_entry; - - imgp->proc->p_sysent = &svr4_sysvec; -fail: - vn_lock(imgp->vp, LK_EXCLUSIVE | LK_RETRY); - return (error); -} - -/* - * Tell kern_execve.c about it, with a little help from the linker. - */ -struct execsw svr4_execsw = { exec_svr4_imgact, "svr4 ELF" }; -EXEC_SET(execsw_set, svr4_execsw); - diff --git a/sys/compat/svr4/svr4.h b/sys/compat/svr4/svr4.h deleted file mode 100644 index 75bb0cfa5c6..00000000000 --- a/sys/compat/svr4/svr4.h +++ /dev/null @@ -1,39 +0,0 @@ -/*- - * Copyright (c) 1998 Mark Newton - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * $FreeBSD: stable/11/sys/compat/svr4/svr4.h 147965 2005-07-13 15:14:33Z jhb $ - */ - -#include "opt_svr4.h" - -#if !defined(_SVR4_H) -#define _SVR4_H - -extern struct sysentvec svr4_sysvec; - -#define COMPAT_SVR4_SOLARIS2 - -#endif diff --git a/sys/compat/svr4/svr4_acl.h b/sys/compat/svr4/svr4_acl.h deleted file mode 100644 index 9bf92a17d94..00000000000 --- a/sys/compat/svr4/svr4_acl.h +++ /dev/null @@ -1,46 +0,0 @@ -/*- - * Copyright (c) 1998 Mark Newton - * Copyright (c) 1996 Christos Zoulas. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by Christos Zoulas. - * 4. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * $FreeBSD: stable/11/sys/compat/svr4/svr4_acl.h 139743 2005-01-05 22:34:37Z imp $ - */ -#ifndef _SVR4_ACL_H_ -#define _SVR4_ACL_H_ - -typedef struct svr4_aclent { - int a_type; - svr4_uid_t a_id; - svr4_o_mode_t a_perm; -} svr4_aclent_t; - -#define SVR4_SYS_GETACL 1 -#define SVR4_SYS_SETACL 2 -#define SVR4_SYS_GETACLCNT 3 - -#endif /* !_SVR4_ACL_H_ */ diff --git a/sys/compat/svr4/svr4_dirent.h b/sys/compat/svr4/svr4_dirent.h deleted file mode 100644 index cc6cca716fd..00000000000 --- a/sys/compat/svr4/svr4_dirent.h +++ /dev/null @@ -1,53 +0,0 @@ -/*- - * Copyright (c) 1998 Mark Newton - * Copyright (c) 1994 Christos Zoulas - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * $FreeBSD: stable/11/sys/compat/svr4/svr4_dirent.h 139743 2005-01-05 22:34:37Z imp $ - */ - -#ifndef _SVR4_DIRENT_H_ -#define _SVR4_DIRENT_H_ - -#define SVR4_MAXNAMLEN 512 - -struct svr4_dirent { - svr4_ino_t d_ino; - svr4_off_t d_off; - u_short d_reclen; - char d_name[SVR4_MAXNAMLEN + 1]; -}; - -struct svr4_dirent64 { - svr4_ino64_t d_ino; - svr4_off64_t d_off; - u_short d_reclen; - char d_name[SVR4_MAXNAMLEN + 1]; -}; - -#define SVR4_NAMEOFF(dp) ((char *)&(dp)->d_name - (char *)dp) -#define SVR4_RECLEN(de,namlen) ALIGN((SVR4_NAMEOFF(de) + (namlen) + 1)) - -#endif /* !_SVR4_DIRENT_H_ */ diff --git a/sys/compat/svr4/svr4_errno.h b/sys/compat/svr4/svr4_errno.h deleted file mode 100644 index 9c5c4a6d0a5..00000000000 --- a/sys/compat/svr4/svr4_errno.h +++ /dev/null @@ -1,172 +0,0 @@ -/*- - * Copyright (c) 1998 Mark Newton - * Copyright (c) 1994 Christos Zoulas - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * $FreeBSD: stable/11/sys/compat/svr4/svr4_errno.h 139743 2005-01-05 22:34:37Z imp $ - */ - -#ifndef _SVR4_ERRNO_H_ -#define _SVR4_ERRNO_H_ - -#define SVR4_EPERM 1 -#define SVR4_ENOENT 2 -#define SVR4_ESRCH 3 -#define SVR4_EINTR 4 -#define SVR4_EIO 5 -#define SVR4_ENXIO 6 -#define SVR4_E2BIG 7 -#define SVR4_ENOEXEC 8 -#define SVR4_EBADF 9 -#define SVR4_ECHILD 10 -#define SVR4_EAGAIN 11 -#define SVR4_ENOMEM 12 -#define SVR4_EACCES 13 -#define SVR4_EFAULT 14 -#define SVR4_ENOTBLK 15 -#define SVR4_EBUSY 16 -#define SVR4_EEXIST 17 -#define SVR4_EXDEV 18 -#define SVR4_ENODEV 19 -#define SVR4_ENOTDIR 20 -#define SVR4_EISDIR 21 -#define SVR4_EINVAL 22 -#define SVR4_ENFILE 23 -#define SVR4_EMFILE 24 -#define SVR4_ENOTTY 25 -#define SVR4_ETXTBSY 26 -#define SVR4_EFBIG 27 -#define SVR4_ENOSPC 28 -#define SVR4_ESPIPE 29 -#define SVR4_EROFS 30 -#define SVR4_EMLINK 31 -#define SVR4_EPIPE 32 -#define SVR4_EDOM 33 -#define SVR4_ERANGE 34 -#define SVR4_ENOMSG 35 -#define SVR4_EIDRM 36 -#define SVR4_ECHRNG 37 -#define SVR4_EL2NSYNC 38 -#define SVR4_EL3HLT 39 -#define SVR4_EL3RST 40 -#define SVR4_ELNRNG 41 -#define SVR4_EUNATCH 42 -#define SVR4_ENOCSI 43 -#define SVR4_EL2HLT 44 -#define SVR4_EDEADLK 45 -#define SVR4_ENOLCK 46 -#define SVR4_EBADE 50 -#define SVR4_EBADR 51 -#define SVR4_EXFULL 52 -#define SVR4_ENOANO 53 -#define SVR4_EBADRQC 54 -#define SVR4_EBADSLT 55 -#define SVR4_EDEADLOCK 56 -#define SVR4_EBFONT 57 -#define SVR4_ENOSTR 60 -#define SVR4_ENODATA 61 -#define SVR4_ETIME 62 -#define SVR4_ENOSR 63 -#define SVR4_ENONET 64 -#define SVR4_ENOPKG 65 -#define SVR4_EREMOTE 66 -#define SVR4_ENOLINK 67 -#define SVR4_EADV 68 -#define SVR4_ESRMNT 69 -#define SVR4_ECOMM 70 -#define SVR4_EPROTO 71 -#define SVR4_EMULTIHOP 74 -#define SVR4_EBADMSG 77 -#define SVR4_ENAMETOOLONG 78 -#define SVR4_EOVERFLOW 79 -#define SVR4_ENOTUNIQ 80 -#define SVR4_EBADFD 81 -#define SVR4_EREMCHG 82 -#define SVR4_ELIBACC 83 -#define SVR4_ELIBBAD 84 -#define SVR4_ELIBSCN 85 -#define SVR4_ELIBMAX 86 -#define SVR4_ELIBEXEC 87 -#define SVR4_EILSEQ 88 -#define SVR4_ENOSYS 89 -#define SVR4_ELOOP 90 -#define SVR4_ERESTART 91 -#define SVR4_ESTRPIPE 92 -#define SVR4_ENOTEMPTY 93 -#define SVR4_EUSERS 94 -#define SVR4_ENOTSOCK 95 -#define SVR4_EDESTADDRREQ 96 -#define SVR4_EMSGSIZE 97 -#define SVR4_EPROTOTYPE 98 -#define SVR4_ENOPROTOOPT 99 -#define SVR4_EPROTONOSUPPORT 120 -#define SVR4_ESOCKTNOSUPPORT 121 -#define SVR4_EOPNOTSUPP 122 -#define SVR4_EPFNOSUPPORT 123 -#define SVR4_EAFNOSUPPORT 124 -#define SVR4_EADDRINUSE 125 -#define SVR4_EADDRNOTAVAIL 126 -#define SVR4_ENETDOWN 127 -#define SVR4_ENETUNREACH 128 -#define SVR4_ENETRESET 129 -#define SVR4_ECONNABORTED 130 -#define SVR4_ECONNRESET 131 -#define SVR4_ENOBUFS 132 -#define SVR4_EISCONN 133 -#define SVR4_ENOTCONN 134 -#define SVR4_EUCLEAN 135 -#define SVR4_ENOTNAM 137 -#define SVR4_ENAVAIL 138 -#define SVR4_EISNAM 139 -#define SVR4_EREMOTEIO 140 -#define SVR4_EINIT 141 -#define SVR4_EREMDEV 142 -#define SVR4_ESHUTDOWN 143 -#define SVR4_ETOOMANYREFS 144 -#define SVR4_ETIMEDOUT 145 -#define SVR4_ECONNREFUSED 146 -#define SVR4_EHOSTDOWN 147 -#define SVR4_EHOSTUNREACH 148 -#define SVR4_EWOULDBLOCK SVR4_EAGAIN -#define SVR4_EALREADY 149 -#define SVR4_EINPROGRESS 150 -#define SVR4_ESTALE 151 -#define SVR4_EIORESID 500 - -/* - * These ones are not translated... - */ -#define SVR4_EPROCLIM SVR4_ENOSYS -#define SVR4_EDQUOT SVR4_ENOSYS -#define SVR4_EBADRPC SVR4_ENOSYS -#define SVR4_ERPCMISMATCH SVR4_ENOSYS -#define SVR4_EPROGUNAVAIL SVR4_ENOSYS -#define SVR4_EPROGMISMATCH SVR4_ENOSYS -#define SVR4_EPROCUNAVAIL SVR4_ENOSYS -#define SVR4_EFTYPE SVR4_ENOSYS -#define SVR4_EAUTH SVR4_ENOSYS -#define SVR4_ENEEDAUTH SVR4_ENOSYS - -#endif /* !_SVR4_ERRNO_H_ */ diff --git a/sys/compat/svr4/svr4_exec.h b/sys/compat/svr4/svr4_exec.h deleted file mode 100644 index a3aecc3fc90..00000000000 --- a/sys/compat/svr4/svr4_exec.h +++ /dev/null @@ -1,70 +0,0 @@ -/*- - * Copyright (c) 1998 Mark Newton - * Copyright (c) 1994 Christos Zoulas - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * $FreeBSD: stable/11/sys/compat/svr4/svr4_exec.h 139743 2005-01-05 22:34:37Z imp $ - */ - -#ifndef _SVR4_EXEC_H_ -#define _SVR4_EXEC_H_ - -#ifdef SVR4_COMPAT_SOLARIS2 -# define SVR4_AUX_ARGSIZ (sizeof(AuxInfo) * 12 / sizeof(char *)) -#else -# define SVR4_AUX_ARGSIZ (sizeof(AuxInfo) * 8 / sizeof(char *)) -#endif - -#if 0 -/* Don't think we need all this NetBSD stuff */ -/* - * The following is horrible; there must be a better way. I need to - * play with brk(2) a bit more. - */ -#ifdef __i386__ -/* - * I cannot load the interpreter after the data segment because brk(2) - * breaks. I have to load it somewhere before. Programs start at - * 0x08000000 so I load the interpreter far before. - */ -#define SVR4_INTERP_ADDR 0x01000000 -#endif - -#ifdef sparc -/* - * Here programs load at 0x00010000, so I load the interpreter far after - * the end of the data segment. - */ -#define SVR4_INTERP_ADDR 0x10000000 -#endif - -#ifndef SVR4_INTERP_ADDR -# define SVR4_INTERP_ADDR 0 -#endif -#endif - -/*void svr4_setregs(struct thread *, struct exec_package *, u_long);*/ - -#endif /* !_SVR4_EXEC_H_ */ diff --git a/sys/compat/svr4/svr4_fcntl.c b/sys/compat/svr4/svr4_fcntl.c deleted file mode 100644 index 9d8256208f2..00000000000 --- a/sys/compat/svr4/svr4_fcntl.c +++ /dev/null @@ -1,731 +0,0 @@ -/*- - * Copyright (c) 1998 Mark Newton - * Copyright (c) 1994, 1997 Christos Zoulas. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by Christos Zoulas. - * 4. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include - -#include -#include -#include -#include -#include -/*#include */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include -#include -#include -#include -#include -#include - -#include - -static int svr4_to_bsd_flags(int); -static u_long svr4_to_bsd_cmd(u_long); -static int fd_revoke(struct thread *, int); -static int fd_truncate(struct thread *, int, struct flock *); -static int bsd_to_svr4_flags(int); -static void bsd_to_svr4_flock(struct flock *, struct svr4_flock *); -static void svr4_to_bsd_flock(struct svr4_flock *, struct flock *); -static void bsd_to_svr4_flock64(struct flock *, struct svr4_flock64 *); -static void svr4_to_bsd_flock64(struct svr4_flock64 *, struct flock *); - -static u_long -svr4_to_bsd_cmd(cmd) - u_long cmd; -{ - switch (cmd) { - case SVR4_F_DUPFD: - return F_DUPFD; - case SVR4_F_DUP2FD: - return F_DUP2FD; - case SVR4_F_GETFD: - return F_GETFD; - case SVR4_F_SETFD: - return F_SETFD; - case SVR4_F_GETFL: - return F_GETFL; - case SVR4_F_SETFL: - return F_SETFL; - case SVR4_F_GETLK: - return F_GETLK; - case SVR4_F_SETLK: - return F_SETLK; - case SVR4_F_SETLKW: - return F_SETLKW; - default: - return -1; - } -} - -static int -svr4_to_bsd_flags(l) - int l; -{ - int r = 0; - r |= (l & SVR4_O_RDONLY) ? O_RDONLY : 0; - r |= (l & SVR4_O_WRONLY) ? O_WRONLY : 0; - r |= (l & SVR4_O_RDWR) ? O_RDWR : 0; - r |= (l & SVR4_O_NDELAY) ? O_NONBLOCK : 0; - r |= (l & SVR4_O_APPEND) ? O_APPEND : 0; - r |= (l & SVR4_O_SYNC) ? O_FSYNC : 0; - r |= (l & SVR4_O_NONBLOCK) ? O_NONBLOCK : 0; - r |= (l & SVR4_O_PRIV) ? O_EXLOCK : 0; - r |= (l & SVR4_O_CREAT) ? O_CREAT : 0; - r |= (l & SVR4_O_TRUNC) ? O_TRUNC : 0; - r |= (l & SVR4_O_EXCL) ? O_EXCL : 0; - r |= (l & SVR4_O_NOCTTY) ? O_NOCTTY : 0; - return r; -} - -static int -bsd_to_svr4_flags(l) - int l; -{ - int r = 0; - r |= (l & O_RDONLY) ? SVR4_O_RDONLY : 0; - r |= (l & O_WRONLY) ? SVR4_O_WRONLY : 0; - r |= (l & O_RDWR) ? SVR4_O_RDWR : 0; - r |= (l & O_NDELAY) ? SVR4_O_NONBLOCK : 0; - r |= (l & O_APPEND) ? SVR4_O_APPEND : 0; - r |= (l & O_FSYNC) ? SVR4_O_SYNC : 0; - r |= (l & O_NONBLOCK) ? SVR4_O_NONBLOCK : 0; - r |= (l & O_EXLOCK) ? SVR4_O_PRIV : 0; - r |= (l & O_CREAT) ? SVR4_O_CREAT : 0; - r |= (l & O_TRUNC) ? SVR4_O_TRUNC : 0; - r |= (l & O_EXCL) ? SVR4_O_EXCL : 0; - r |= (l & O_NOCTTY) ? SVR4_O_NOCTTY : 0; - return r; -} - - -static void -bsd_to_svr4_flock(iflp, oflp) - struct flock *iflp; - struct svr4_flock *oflp; -{ - switch (iflp->l_type) { - case F_RDLCK: - oflp->l_type = SVR4_F_RDLCK; - break; - case F_WRLCK: - oflp->l_type = SVR4_F_WRLCK; - break; - case F_UNLCK: - oflp->l_type = SVR4_F_UNLCK; - break; - default: - oflp->l_type = -1; - break; - } - - oflp->l_whence = (short) iflp->l_whence; - oflp->l_start = (svr4_off_t) iflp->l_start; - oflp->l_len = (svr4_off_t) iflp->l_len; - oflp->l_sysid = 0; - oflp->l_pid = (svr4_pid_t) iflp->l_pid; -} - - -static void -svr4_to_bsd_flock(iflp, oflp) - struct svr4_flock *iflp; - struct flock *oflp; -{ - switch (iflp->l_type) { - case SVR4_F_RDLCK: - oflp->l_type = F_RDLCK; - break; - case SVR4_F_WRLCK: - oflp->l_type = F_WRLCK; - break; - case SVR4_F_UNLCK: - oflp->l_type = F_UNLCK; - break; - default: - oflp->l_type = -1; - break; - } - - oflp->l_whence = iflp->l_whence; - oflp->l_start = (off_t) iflp->l_start; - oflp->l_len = (off_t) iflp->l_len; - oflp->l_pid = (pid_t) iflp->l_pid; - oflp->l_sysid = iflp->l_sysid; -} - -static void -bsd_to_svr4_flock64(iflp, oflp) - struct flock *iflp; - struct svr4_flock64 *oflp; -{ - switch (iflp->l_type) { - case F_RDLCK: - oflp->l_type = SVR4_F_RDLCK; - break; - case F_WRLCK: - oflp->l_type = SVR4_F_WRLCK; - break; - case F_UNLCK: - oflp->l_type = SVR4_F_UNLCK; - break; - default: - oflp->l_type = -1; - break; - } - - oflp->l_whence = (short) iflp->l_whence; - oflp->l_start = (svr4_off64_t) iflp->l_start; - oflp->l_len = (svr4_off64_t) iflp->l_len; - oflp->l_sysid = iflp->l_sysid; - oflp->l_pid = (svr4_pid_t) iflp->l_pid; -} - - -static void -svr4_to_bsd_flock64(iflp, oflp) - struct svr4_flock64 *iflp; - struct flock *oflp; -{ - switch (iflp->l_type) { - case SVR4_F_RDLCK: - oflp->l_type = F_RDLCK; - break; - case SVR4_F_WRLCK: - oflp->l_type = F_WRLCK; - break; - case SVR4_F_UNLCK: - oflp->l_type = F_UNLCK; - break; - default: - oflp->l_type = -1; - break; - } - - oflp->l_whence = iflp->l_whence; - oflp->l_start = (off_t) iflp->l_start; - oflp->l_len = (off_t) iflp->l_len; - oflp->l_pid = (pid_t) iflp->l_pid; - -} - - -static int -fd_revoke(td, fd) - struct thread *td; - int fd; -{ - struct vnode *vp; - struct mount *mp; - struct vattr vattr; - cap_rights_t rights; - int error, *retval; - - retval = td->td_retval; - /* - * If we ever want to support Capsicum on SVR4 processes (unlikely) - * or FreeBSD grows a native frevoke() (more likely), we will need a - * CAP_FREVOKE here. - * - * In the meantime, use CAP_ALL(): if a SVR4 process wants to - * do an frevoke(), it needs to do it on either a regular file - * descriptor or a fully-privileged capability (which is effectively - * the same as a non-capability-restricted file descriptor). - */ - CAP_ALL(&rights); - if ((error = fgetvp(td, fd, &rights, &vp)) != 0) - return (error); - - if (vp->v_type != VCHR && vp->v_type != VBLK) { - error = EINVAL; - goto out; - } - -#ifdef MAC - vn_lock(vp, LK_EXCLUSIVE | LK_RETRY); - error = mac_vnode_check_revoke(td->td_ucred, vp); - VOP_UNLOCK(vp, 0); - if (error) - goto out; -#endif - - if ((error = VOP_GETATTR(vp, &vattr, td->td_ucred)) != 0) - goto out; - - if (td->td_ucred->cr_uid != vattr.va_uid && - (error = priv_check(td, PRIV_VFS_ADMIN)) != 0) - goto out; - - if ((error = vn_start_write(vp, &mp, V_WAIT | PCATCH)) != 0) - goto out; - if (vcount(vp) > 1) - VOP_REVOKE(vp, REVOKEALL); - vn_finished_write(mp); -out: - vrele(vp); - return error; -} - - -static int -fd_truncate(td, fd, flp) - struct thread *td; - int fd; - struct flock *flp; -{ - off_t start, length; - struct file *fp; - struct vnode *vp; - struct vattr vattr; - int error, *retval; - struct ftruncate_args ft; - cap_rights_t rights; - - retval = td->td_retval; - - /* - * We only support truncating the file. - */ - error = fget(td, fd, cap_rights_init(&rights, CAP_FTRUNCATE), &fp); - if (error != 0) - return (error); - - vp = fp->f_vnode; - - if (fp->f_type != DTYPE_VNODE || vp->v_type == VFIFO) { - fdrop(fp, td); - return ESPIPE; - } - - if ((error = VOP_GETATTR(vp, &vattr, td->td_ucred)) != 0) { - fdrop(fp, td); - return error; - } - - length = vattr.va_size; - - switch (flp->l_whence) { - case SEEK_CUR: - start = fp->f_offset + flp->l_start; - break; - - case SEEK_END: - start = flp->l_start + length; - break; - - case SEEK_SET: - start = flp->l_start; - break; - - default: - fdrop(fp, td); - return EINVAL; - } - - if (start + flp->l_len < length) { - /* We don't support free'ing in the middle of the file */ - fdrop(fp, td); - return EINVAL; - } - - ft.fd = fd; - ft.length = start; - - error = sys_ftruncate(td, &ft); - - fdrop(fp, td); - return (error); -} - -int -svr4_sys_open(td, uap) - struct thread *td; - struct svr4_sys_open_args *uap; -{ - struct proc *p = td->td_proc; - char *newpath; - int bsd_flags, error, retval; - - CHECKALTEXIST(td, uap->path, &newpath); - - bsd_flags = svr4_to_bsd_flags(uap->flags); - error = kern_openat(td, AT_FDCWD, newpath, UIO_SYSSPACE, bsd_flags, - uap->mode); - free(newpath, M_TEMP); - - if (error) { - /* uprintf("svr4_open(%s, 0x%0x, 0%o): %d\n", uap->path, - uap->flags, uap->mode, error);*/ - return error; - } - - retval = td->td_retval[0]; - - PROC_LOCK(p); - if (!(bsd_flags & O_NOCTTY) && SESS_LEADER(p) && - !(p->p_flag & P_CONTROLT)) { -#if defined(NOTYET) - cap_rights_t rights; - struct file *fp; - - error = fget(td, retval, - cap_rights_init(&rights, CAP_IOCTL), &fp); - PROC_UNLOCK(p); - /* - * we may have lost a race the above open() and - * another thread issuing a close() - */ - if (error) - return (EBADF); /* XXX: correct errno? */ - /* ignore any error, just give it a try */ - if (fp->f_type == DTYPE_VNODE) - fo_ioctl(fp, TIOCSCTTY, (caddr_t) 0, td->td_ucred, - td); - fdrop(fp, td); - } else { - PROC_UNLOCK(p); - } -#else - } - PROC_UNLOCK(p); -#endif - return error; -} - -int -svr4_sys_open64(td, uap) - struct thread *td; - struct svr4_sys_open64_args *uap; -{ - return svr4_sys_open(td, (struct svr4_sys_open_args *)uap); -} - -int -svr4_sys_creat(td, uap) - struct thread *td; - struct svr4_sys_creat_args *uap; -{ - char *newpath; - int error; - - CHECKALTEXIST(td, uap->path, &newpath); - - error = kern_openat(td, AT_FDCWD, newpath, UIO_SYSSPACE, - O_WRONLY | O_CREAT | O_TRUNC, uap->mode); - free(newpath, M_TEMP); - return (error); -} - -int -svr4_sys_creat64(td, uap) - struct thread *td; - struct svr4_sys_creat64_args *uap; -{ - return svr4_sys_creat(td, (struct svr4_sys_creat_args *)uap); -} - -int -svr4_sys_llseek(td, uap) - struct thread *td; - struct svr4_sys_llseek_args *uap; -{ - struct lseek_args ap; - - ap.fd = uap->fd; - -#if BYTE_ORDER == BIG_ENDIAN - ap.offset = (((u_int64_t) uap->offset1) << 32) | - uap->offset2; -#else - ap.offset = (((u_int64_t) uap->offset2) << 32) | - uap->offset1; -#endif - ap.whence = uap->whence; - - return sys_lseek(td, &ap); -} - -int -svr4_sys_access(td, uap) - struct thread *td; - struct svr4_sys_access_args *uap; -{ - char *newpath; - int error; - - CHECKALTEXIST(td, uap->path, &newpath); - error = kern_accessat(td, AT_FDCWD, newpath, UIO_SYSSPACE, - 0, uap->amode); - free(newpath, M_TEMP); - return (error); -} - -#if defined(NOTYET) -int -svr4_sys_pread(td, uap) - struct thread *td; - struct svr4_sys_pread_args *uap; -{ - struct pread_args pra; - - /* - * Just translate the args structure and call the NetBSD - * pread(2) system call (offset type is 64-bit in NetBSD). - */ - pra.fd = uap->fd; - pra.buf = uap->buf; - pra.nbyte = uap->nbyte; - pra.offset = uap->off; - - return pread(td, &pra); -} -#endif - -#if defined(NOTYET) -int -svr4_sys_pread64(td, v, retval) - struct thread *td; - void *v; - register_t *retval; -{ - - struct svr4_sys_pread64_args *uap = v; - struct sys_pread_args pra; - - /* - * Just translate the args structure and call the NetBSD - * pread(2) system call (offset type is 64-bit in NetBSD). - */ - pra.fd = uap->fd; - pra.buf = uap->buf; - pra.nbyte = uap->nbyte; - pra.offset = uap->off; - - return (sys_pread(td, &pra, retval)); -} -#endif /* NOTYET */ - -#if defined(NOTYET) -int -svr4_sys_pwrite(td, uap) - struct thread *td; - struct svr4_sys_pwrite_args *uap; -{ - struct pwrite_args pwa; - - /* - * Just translate the args structure and call the NetBSD - * pwrite(2) system call (offset type is 64-bit in NetBSD). - */ - pwa.fd = uap->fd; - pwa.buf = uap->buf; - pwa.nbyte = uap->nbyte; - pwa.offset = uap->off; - - return pwrite(td, &pwa); -} -#endif - -#if defined(NOTYET) -int -svr4_sys_pwrite64(td, v, retval) - struct thread *td; - void *v; - register_t *retval; -{ - struct svr4_sys_pwrite64_args *uap = v; - struct sys_pwrite_args pwa; - - /* - * Just translate the args structure and call the NetBSD - * pwrite(2) system call (offset type is 64-bit in NetBSD). - */ - pwa.fd = uap->fd; - pwa.buf = uap->buf; - pwa.nbyte = uap->nbyte; - pwa.offset = uap->off; - - return (sys_pwrite(td, &pwa, retval)); -} -#endif /* NOTYET */ - -int -svr4_sys_fcntl(td, uap) - struct thread *td; - struct svr4_sys_fcntl_args *uap; -{ - int cmd, error, *retval; - - retval = td->td_retval; - - cmd = svr4_to_bsd_cmd(uap->cmd); - - switch (cmd) { - case F_DUPFD: - case F_DUP2FD: - case F_GETFD: - case F_SETFD: - return (kern_fcntl(td, uap->fd, cmd, (intptr_t)uap->arg)); - - case F_GETFL: - error = kern_fcntl(td, uap->fd, cmd, (intptr_t)uap->arg); - if (error) - return (error); - *retval = bsd_to_svr4_flags(*retval); - return (error); - - case F_SETFL: - { - /* - * we must save the O_ASYNC flag, as that is - * handled by ioctl(_, I_SETSIG, _) emulation. - */ - int flags; - - DPRINTF(("Setting flags %p\n", uap->arg)); - - error = kern_fcntl(td, uap->fd, F_GETFL, 0); - if (error) - return (error); - flags = *retval; - flags &= O_ASYNC; - flags |= svr4_to_bsd_flags((u_long) uap->arg); - return (kern_fcntl(td, uap->fd, F_SETFL, flags)); - } - - case F_GETLK: - case F_SETLK: - case F_SETLKW: - { - struct svr4_flock ifl; - struct flock fl; - - error = copyin(uap->arg, &ifl, sizeof (ifl)); - if (error) - return (error); - - svr4_to_bsd_flock(&ifl, &fl); - - error = kern_fcntl(td, uap->fd, cmd, (intptr_t)&fl); - if (error || cmd != F_GETLK) - return (error); - - bsd_to_svr4_flock(&fl, &ifl); - - return (copyout(&ifl, uap->arg, sizeof (ifl))); - } - case -1: - switch (uap->cmd) { - case SVR4_F_FREESP: - { - struct svr4_flock ifl; - struct flock fl; - - error = copyin(uap->arg, &ifl, - sizeof ifl); - if (error) - return error; - svr4_to_bsd_flock(&ifl, &fl); - return fd_truncate(td, uap->fd, &fl); - } - - case SVR4_F_GETLK64: - case SVR4_F_SETLK64: - case SVR4_F_SETLKW64: - { - struct svr4_flock64 ifl; - struct flock fl; - - switch (uap->cmd) { - case SVR4_F_GETLK64: - cmd = F_GETLK; - break; - case SVR4_F_SETLK64: - cmd = F_SETLK; - break; - case SVR4_F_SETLKW64: - cmd = F_SETLKW; - break; - } - error = copyin(uap->arg, &ifl, - sizeof (ifl)); - if (error) - return (error); - - svr4_to_bsd_flock64(&ifl, &fl); - - error = kern_fcntl(td, uap->fd, cmd, - (intptr_t)&fl); - if (error || cmd != F_GETLK) - return (error); - - bsd_to_svr4_flock64(&fl, &ifl); - - return (copyout(&ifl, uap->arg, - sizeof (ifl))); - } - - case SVR4_F_FREESP64: - { - struct svr4_flock64 ifl; - struct flock fl; - - error = copyin(uap->arg, &ifl, - sizeof ifl); - if (error) - return error; - svr4_to_bsd_flock64(&ifl, &fl); - return fd_truncate(td, uap->fd, &fl); - } - - case SVR4_F_REVOKE: - return fd_revoke(td, uap->fd); - - default: - return ENOSYS; - } - - default: - return ENOSYS; - } -} diff --git a/sys/compat/svr4/svr4_fcntl.h b/sys/compat/svr4/svr4_fcntl.h deleted file mode 100644 index 2c3812075fc..00000000000 --- a/sys/compat/svr4/svr4_fcntl.h +++ /dev/null @@ -1,134 +0,0 @@ -/*- - * Copyright (c) 1998 Mark Newton - * Copyright (c) 1994 Christos Zoulas - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * $FreeBSD: stable/11/sys/compat/svr4/svr4_fcntl.h 139743 2005-01-05 22:34:37Z imp $ - */ - -#ifndef _SVR4_FCNTL_H_ -#define _SVR4_FCNTL_H_ - -#include -#include - -#define SVR4_O_RDONLY 0x0000 -#define SVR4_O_WRONLY 0x0001 -#define SVR4_O_RDWR 0x0002 -#define SVR4_O_ACCMODE 0x0003 -#define SVR4_O_NDELAY 0x0004 -#define SVR4_O_APPEND 0x0008 -#define SVR4_O_SYNC 0x0010 -#define SVR4_O_NONBLOCK 0x0080 -#define SVR4_O_CREAT 0x0100 -#define SVR4_O_TRUNC 0x0200 -#define SVR4_O_EXCL 0x0400 -#define SVR4_O_NOCTTY 0x0800 -#define SVR4_O_PRIV 0x1000 - - -#define SVR4_FD_CLOEXEC 1 - -#define SVR4_F_DUPFD 0 -#define SVR4_F_GETFD 1 -#define SVR4_F_SETFD 2 -#define SVR4_F_GETFL 3 -#define SVR4_F_SETFL 4 -#define SVR4_F_GETLK_SVR3 5 -#define SVR4_F_SETLK 6 -#define SVR4_F_SETLKW 7 -#define SVR4_F_CHKFL 8 -#define SVR4_F_DUP2FD 9 -#define SVR4_F_ALLOCSP 10 -#define SVR4_F_FREESP 11 - -#define SVR4_F_ISSTREAM 13 -#define SVR4_F_GETLK 14 -#define SVR4_F_PRIV 15 -#define SVR4_F_NPRIV 16 -#define SVR4_F_QUOTACTL 17 -#define SVR4_F_BLOCKS 18 -#define SVR4_F_BLKSIZE 19 -#define SVR4_F_RSETLK 20 -#define SVR4_F_RGETLK 21 -#define SVR4_F_RSETLKW 22 -#define SVR4_F_GETOWN 23 -#define SVR4_F_SETOWN 24 -#define SVR4_F_REVOKE 25 -#define SVR4_F_HASREMOTELOCKS 26 -#define SVR4_F_FREESP64 27 - -#define SVR4_F_GETLK64 33 -#define SVR4_F_SETLK64 34 -#define SVR4_F_SETLKW64 35 - -#define SVR4_F_SHARE 40 -#define SVR4_F_UNSHARE 41 - -#define SVR4_F_CHSIZE_XENIX 0x6000 -#define SVR4_F_RDCHK_XENIX 0x6001 -#define SVR4_F_LK_UNLCK_XENIX 0x6300 -#define SVR4_F_LK_LOCK_XENIX 0x7200 -#define SVR4_F_LK_NBLCK_XENIX 0x6200 -#define SVR4_F_LK_RLCK_XENIX 0x7100 -#define SVR4_F_LK_NBRLCK_XENIX 0x6100 - -#define SVR4_LK_CMDTYPE(x) (((x) >> 12) & 0x7) -#define SVR4_LK_LCKTYPE(x) (((x) >> 8) & 0x7) - -#define SVR4_F_RDLCK 1 -#define SVR4_F_WRLCK 2 -#define SVR4_F_UNLCK 3 - -struct svr4_flock_svr3 { - short l_type; - short l_whence; - svr4_off_t l_start; - svr4_off_t l_len; - short l_sysid; - svr4_o_pid_t l_pid; -}; - - -struct svr4_flock { - short l_type; - short l_whence; - svr4_off_t l_start; - svr4_off_t l_len; - long l_sysid; - svr4_pid_t l_pid; - long pad[4]; -}; - -struct svr4_flock64 { - short l_type; - short l_whence; - svr4_off64_t l_start; - svr4_off64_t l_len; - long l_sysid; - svr4_pid_t l_pid; - long pad[4]; -}; -#endif /* !_SVR4_FCNTL_H_ */ diff --git a/sys/compat/svr4/svr4_filio.c b/sys/compat/svr4/svr4_filio.c deleted file mode 100644 index 86c9ea59fba..00000000000 --- a/sys/compat/svr4/svr4_filio.c +++ /dev/null @@ -1,268 +0,0 @@ -/*- - * Copyright (c) 1998 Mark Newton - * Copyright (c) 1994 Christos Zoulas - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include -#include -#include -#include -#include -#include -#include - -/*#define GROTTY_READ_HACK*/ - -int -svr4_sys_poll(td, uap) - struct thread *td; - struct svr4_sys_poll_args *uap; -{ - int error; - struct poll_args pa; - struct pollfd *pfd; - int idx = 0, cerr; - u_long siz; - - if (uap->nfds > maxfilesperproc && uap->nfds > FD_SETSIZE) - return (EINVAL); - - pa.fds = uap->fds; - pa.nfds = uap->nfds; - pa.timeout = uap->timeout; - - siz = uap->nfds * sizeof(struct pollfd); - pfd = (struct pollfd *)malloc(siz, M_TEMP, M_WAITOK); - - error = sys_poll(td, (struct poll_args *)uap); - - if ((cerr = copyin(uap->fds, pfd, siz)) != 0) { - error = cerr; - goto done; - } - - for (idx = 0; idx < uap->nfds; idx++) { - /* POLLWRNORM already equals POLLOUT, so we don't worry about that */ - if (pfd[idx].revents & (POLLOUT | POLLWRNORM | POLLWRBAND)) - pfd[idx].revents |= (POLLOUT | POLLWRNORM | POLLWRBAND); - } - if ((cerr = copyout(pfd, uap->fds, siz)) != 0) { - error = cerr; - goto done; /* yeah, I know it's the next line, but this way I won't - forget to update it if I add more code */ - } -done: - free(pfd, M_TEMP); - return error; -} - -#if defined(READ_TEST) -int -svr4_sys_read(td, uap) - struct thread *td; - struct svr4_sys_read_args *uap; -{ - struct read_args ra; - cap_rights_t rights; - struct file *fp; - struct socket *so = NULL; - int so_state; - sigset_t sigmask; - int rv; - - ra.fd = uap->fd; - ra.buf = uap->buf; - ra.nbyte = uap->nbyte; - - if (fget(td, uap->fd, cap_rights_init(&rights, CAP_READ), &fp) != 0) { - DPRINTF(("Something fishy with the user-supplied file descriptor...\n")); - return EBADF; - } - - if (fp->f_type == DTYPE_SOCKET) { - so = fp->f_data; - DPRINTF(("fd %d is a socket\n", uap->fd)); - if (so->so_state & SS_ASYNC) { - DPRINTF(("fd %d is an ASYNC socket!\n", uap->fd)); - } - DPRINTF(("Here are its flags: 0x%x\n", so->so_state)); -#if defined(GROTTY_READ_HACK) - so_state = so->so_state; - so->so_state &= ~SS_NBIO; -#endif - } - - rv = read(td, &ra); - - DPRINTF(("svr4_read(%d, 0x%0x, %d) = %d\n", - uap->fd, uap->buf, uap->nbyte, rv)); - if (rv == EAGAIN) { -#ifdef DEBUG_SVR4 - struct sigacts *ps; - - PROC_LOCK(td->td_proc); - ps = td->td_proc->p_sigacts; - mtx_lock(&ps->ps_mtx); -#endif - DPRINTF(("sigmask = 0x%x\n", td->td_sigmask)); - DPRINTF(("sigignore = 0x%x\n", ps->ps_sigignore)); - DPRINTF(("sigcaught = 0x%x\n", ps->ps_sigcatch)); - DPRINTF(("siglist = 0x%x\n", td->td_siglist)); -#ifdef DEBUG_SVR4 - mtx_unlock(&ps->ps_mtx); - PROC_UNLOCK(td->td_proc); -#endif - } - -#if defined(GROTTY_READ_HACK) - if (so) { /* We've already checked to see if this is a socket */ - so->so_state = so_state; - } -#endif - fdrop(fp, td); - - return(rv); -} -#endif /* READ_TEST */ - -#if defined(BOGUS) -int -svr4_sys_write(td, uap) - struct thread *td; - struct svr4_sys_write_args *uap; -{ - struct write_args wa; - struct file *fp; - int rv; - - wa.fd = uap->fd; - wa.buf = uap->buf; - wa.nbyte = uap->nbyte; - - rv = write(td, &wa); - - DPRINTF(("svr4_write(%d, 0x%0x, %d) = %d\n", - uap->fd, uap->buf, uap->nbyte, rv)); - - return(rv); -} -#endif /* BOGUS */ - -int -svr4_fil_ioctl(fp, td, retval, fd, cmd, data) - struct file *fp; - struct thread *td; - register_t *retval; - int fd; - u_long cmd; - caddr_t data; -{ - struct filedesc *fdp = td->td_proc->p_fd; - struct filedescent *fde; - int error, num; - - *retval = 0; - - switch (cmd) { - case SVR4_FIOCLEX: - FILEDESC_XLOCK(fdp); - fde = &fdp->fd_ofiles[fd]; - fde->fde_flags |= UF_EXCLOSE; - FILEDESC_XUNLOCK(fdp); - return 0; - - case SVR4_FIONCLEX: - FILEDESC_XLOCK(fdp); - fde = &fdp->fd_ofiles[fd]; - fde->fde_flags &= ~UF_EXCLOSE; - FILEDESC_XUNLOCK(fdp); - return 0; - - case SVR4_FIOGETOWN: - case SVR4_FIOSETOWN: - case SVR4_FIOASYNC: - case SVR4_FIONBIO: - case SVR4_FIONREAD: - if ((error = copyin(data, &num, sizeof(num))) != 0) - return error; - - switch (cmd) { - case SVR4_FIOGETOWN: cmd = FIOGETOWN; break; - case SVR4_FIOSETOWN: cmd = FIOSETOWN; break; - case SVR4_FIOASYNC: cmd = FIOASYNC; break; - case SVR4_FIONBIO: cmd = FIONBIO; break; - case SVR4_FIONREAD: cmd = FIONREAD; break; - } - -#ifdef SVR4_DEBUG - if (cmd == FIOASYNC) DPRINTF(("FIOASYNC\n")); -#endif - error = fo_ioctl(fp, cmd, (caddr_t) &num, td->td_ucred, td); - - if (error) - return error; - - return copyout(&num, data, sizeof(num)); - - default: - DPRINTF(("Unknown svr4 filio %lx\n", cmd)); - return 0; /* ENOSYS really */ - } -} - -int -svr4_pipe(struct thread *td, struct svr4_pipe_args *uap) { - int error; - int fildes[2]; - - error = kern_pipe(td, fildes, 0, NULL, NULL); - if (error) - return (error); - - td->td_retval[0] = fildes[0]; - td->td_retval[1] = fildes[1]; - - return (0); -} - diff --git a/sys/compat/svr4/svr4_filio.h b/sys/compat/svr4/svr4_filio.h deleted file mode 100644 index 7209a842c57..00000000000 --- a/sys/compat/svr4/svr4_filio.h +++ /dev/null @@ -1,45 +0,0 @@ -/*- - * Copyright (c) 1998 Mark Newton - * Copyright (c) 1994 Christos Zoulas - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * $FreeBSD: stable/11/sys/compat/svr4/svr4_filio.h 139743 2005-01-05 22:34:37Z imp $ - */ - -#ifndef _SVR4_FILIO_H_ -#define _SVR4_FILIO_H_ - -#define SVR4_FIOC ('f' << 8) - -#define SVR4_FIOCLEX SVR4_IO('f', 1) -#define SVR4_FIONCLEX SVR4_IO('f', 2) - -#define SVR4_FIOGETOWN SVR4_IOR('f', 123, int) -#define SVR4_FIOSETOWN SVR4_IOW('f', 124, int) -#define SVR4_FIOASYNC SVR4_IOW('f', 125, int) -#define SVR4_FIONBIO SVR4_IOW('f', 126, int) -#define SVR4_FIONREAD SVR4_IOR('f', 127, int) - -#endif /* !_SVR4_FILIO_H_ */ diff --git a/sys/compat/svr4/svr4_fuser.h b/sys/compat/svr4/svr4_fuser.h deleted file mode 100644 index 82dc7f02aeb..00000000000 --- a/sys/compat/svr4/svr4_fuser.h +++ /dev/null @@ -1,90 +0,0 @@ -/* - * $FreeBSD: stable/11/sys/compat/svr4/svr4_fuser.h 263289 2014-03-18 01:40:25Z emaste $ - * Derived from: - * $NetBSD: svr4_fuser.h,v 1.4 1998/09/04 19:54:38 christos Exp $ */ - -/*- - * Original Copyright: - * - * Copyright (c) 1994 The NetBSD Foundation, Inc. - * All rights reserved. - * - * This code is derived from software contributed to The NetBSD Foundation - * by Christos Zoulas. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS - * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -/*- - * Portions of this code have been derived from code contributed to the - * FreeBSD Project by Mark Newton. - * - * Copyright (c) 1999 Mark Newton - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _SVR4_FUSER_H_ -#define _SVR4_FUSER_H_ - -#include - -struct svr4_f_user { - svr4_pid_t fu_pid; - int fu_flags; - uid_t fu_uid; -}; - - -#define SVR4_F_FILE_ONLY 1 -#define SVR4_F_CONTAINED 2 - -#define SVR4_F_CDIR 0x01 -#define SVR4_F_RDIR 0x02 -#define SVR4_F_TEXT 0x04 -#define SVR4_F_MAP 0x08 -#define SVR4_F_OPEN 0x10 -#define SVR4_F_TRACE 0x20 -#define SVR4_F_TTY 0x40 - -#endif /* !_SVR4_FUSER_H_ */ diff --git a/sys/compat/svr4/svr4_hrt.h b/sys/compat/svr4/svr4_hrt.h deleted file mode 100644 index cfec0b2dd86..00000000000 --- a/sys/compat/svr4/svr4_hrt.h +++ /dev/null @@ -1,87 +0,0 @@ -/*- - * Copyright (c) 1998 Mark Newton - * Copyright (c) 1994 Christos Zoulas - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * $FreeBSD: stable/11/sys/compat/svr4/svr4_hrt.h 139743 2005-01-05 22:34:37Z imp $ - */ - -#ifndef _SVR4_HRT_H_ -#define _SVR4_HRT_H_ - -#define SVR4_HRT_CNTL 0 -#define SVR4_HRT_CNTL_RES 0 -#define SVR4_HRT_CNTL_TOFD 1 -#define SVR4_HRT_CNTL_START 2 -#define SVR4_HRT_CNTL_GET 3 - -#define SVR4_HRT_ALRM 1 -#define SVR4_HRT_ALRM_DO 4 -#define SVR4_HRT_ALRM_REP 5 -#define SVR4_HRT_ALRM_TOD 6 -#define SVR4_HRT_ALRM_FUTREP 7 -#define SVR4_HRT_ALRM_TODREP 8 -#define SVR4_HRT_ALRM_PEND 9 - -#define SVR4_HRT_SLP 2 -#define SVR4_HRT_SLP_INT 10 -#define SVR4_HRT_SLP_TOD 11 - -#define SVR4_HRT_BSD 12 -#define SVR4_HRT_BSD_PEND 13 -#define SVR4_HRT_BSD_REP1 14 -#define SVR4_HRT_BSD_REP2 15 -#define SVR4_HRT_BSD_CANCEL 16 - -#define SVR4_HRT_CAN 3 - -#define SVR4_HRT_SEC 1 -#define SVR4_HRT_MSEC 1000 -#define SVR4_HRT_USEC 1000000 -#define SVR4_HRT_NSEC 1000000000 - -#define SVR4_HRT_TRUNC 0 -#define SVR4_HRT_RND 1 - -typedef struct { - u_long i_word1; - u_long i_word2; - int i_clock; -} svr4_hrt_interval_t; - -typedef struct { - u_long h_sec; - long h_rem; - u_long h_res; -} svr4_hrt_time_t; - -#define SVR4_HRT_DONE 1 -#define SVR4_HRT_ERROR 2 - -#define SVR4_HRT_CLK_STD 1 -#define SVR4_HRT_CLK_USERVIRT 2 -#define SVR4_HRT_CLK_PROCVIRT 4 - -#endif /* !_SVR4_HRT_H_ */ diff --git a/sys/compat/svr4/svr4_ioctl.c b/sys/compat/svr4/svr4_ioctl.c deleted file mode 100644 index f9c04e1138e..00000000000 --- a/sys/compat/svr4/svr4_ioctl.c +++ /dev/null @@ -1,164 +0,0 @@ -/*- - * Copyright (c) 1998 Mark Newton - * Copyright (c) 1994 Christos Zoulas - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#ifdef DEBUG_SVR4 -static void svr4_decode_cmd(u_long, char *, char *, int *, int *); -/* - * Decode an ioctl command symbolically - */ -static void -svr4_decode_cmd(cmd, dir, c, num, argsiz) - u_long cmd; - char *dir, *c; - int *num, *argsiz; -{ - if (cmd & SVR4_IOC_VOID) - *dir++ = 'V'; - if (cmd & SVR4_IOC_IN) - *dir++ = 'R'; - if (cmd & SVR4_IOC_OUT) - *dir++ = 'W'; - *dir = '\0'; - if (cmd & SVR4_IOC_INOUT) - *argsiz = (cmd >> 16) & 0xff; - else - *argsiz = -1; - - *c = (cmd >> 8) & 0xff; - *num = cmd & 0xff; -} -#endif - -int -svr4_sys_ioctl(td, uap) - struct thread *td; - struct svr4_sys_ioctl_args *uap; -{ - int *retval; - cap_rights_t rights; - struct file *fp; - u_long cmd; - int (*fun)(struct file *, struct thread *, register_t *, - int, u_long, caddr_t); - int error; -#ifdef DEBUG_SVR4 - char dir[4]; - char c; - int num; - int argsiz; - - svr4_decode_cmd(uap->com, dir, &c, &num, &argsiz); - - DPRINTF(("svr4_ioctl[%lx](%d, _IO%s(%c, %d, %d), %p);\n", uap->com, uap->fd, - dir, c, num, argsiz, uap->data)); -#endif - retval = td->td_retval; - cmd = uap->com; - - error = fget(td, uap->fd, cap_rights_init(&rights, CAP_IOCTL), &fp); - if (error != 0) - return (error); - - if ((fp->f_flag & (FREAD | FWRITE)) == 0) { - fdrop(fp, td); - return EBADF; - } - -#if defined(DEBUG_SVR4) - if (fp->f_type == DTYPE_SOCKET) { - struct socket *so = fp->f_data; - DPRINTF(("<<< IN: so_state = 0x%x\n", so->so_state)); - } -#endif - - switch (cmd & 0xff00) { - case SVR4_TIOC: - DPRINTF(("term\n")); - fun = svr4_term_ioctl; - break; - - case SVR4_STR: - DPRINTF(("stream\n")); - fun = svr4_stream_ioctl; - break; - - case SVR4_FIOC: - DPRINTF(("file\n")); - fun = svr4_fil_ioctl; - break; - - case SVR4_SIOC: - DPRINTF(("socket\n")); - fun = svr4_sock_ioctl; - break; - - case SVR4_XIOC: - /* We do not support those */ - fdrop(fp, td); - return EINVAL; - - default: - fdrop(fp, td); - DPRINTF(("Unimplemented ioctl %lx\n", cmd)); - return 0; /* XXX: really ENOSYS */ - } -#if defined(DEBUG_SVR4) - if (fp->f_type == DTYPE_SOCKET) { - struct socket *so; - - so = fp->f_data; - DPRINTF((">>> OUT: so_state = 0x%x\n", so->so_state)); - } -#endif - error = (*fun)(fp, td, retval, uap->fd, cmd, uap->data); - fdrop(fp, td); - return (error); -} diff --git a/sys/compat/svr4/svr4_ioctl.h b/sys/compat/svr4/svr4_ioctl.h deleted file mode 100644 index e8206a95e79..00000000000 --- a/sys/compat/svr4/svr4_ioctl.h +++ /dev/null @@ -1,60 +0,0 @@ -/*- - * Copyright (c) 1998 Mark Newton - * Copyright (c) 1994 Christos Zoulas - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * $FreeBSD: stable/11/sys/compat/svr4/svr4_ioctl.h 191919 2009-05-08 20:06:37Z ed $ - */ - -#ifndef _SVR4_IOCTL_H_ -#define _SVR4_IOCTL_H_ - -#define SVR4_IOC_VOID 0x20000000 -#define SVR4_IOC_OUT 0x40000000 -#define SVR4_IOC_IN 0x80000000 -#define SVR4_IOC_INOUT (SVR4_IOC_IN|SVR4_IOC_OUT) - -#define SVR4_IOC(inout,group,num,len) \ - (inout | ((len & 0xff) << 16) | ((group) << 8) | (num)) - -#define SVR4_XIOC ('X' << 8) - -#define SVR4_IO(g,n) SVR4_IOC(SVR4_IOC_VOID, (g), (n), 0) -#define SVR4_IOR(g,n,t) SVR4_IOC(SVR4_IOC_OUT, (g), (n), sizeof(t)) -#define SVR4_IOW(g,n,t) SVR4_IOC(SVR4_IOC_IN, (g), (n), sizeof(t)) -#define SVR4_IOWR(g,n,t) SVR4_IOC(SVR4_IOC_INOUT,(g), (n), sizeof(t)) - -int svr4_stream_ti_ioctl(struct file *, struct thread *, register_t *, - int, u_long, caddr_t); -int svr4_stream_ioctl(struct file *, struct thread *, register_t *, - int, u_long, caddr_t); -int svr4_term_ioctl(struct file *, struct thread *, register_t *, - int, u_long, caddr_t); -int svr4_fil_ioctl (struct file *, struct thread *, register_t *, - int, u_long, caddr_t); -int svr4_sock_ioctl (struct file *, struct thread *, register_t *, - int, u_long, caddr_t); - -#endif /* !_SVR4_IOCTL_H_ */ diff --git a/sys/compat/svr4/svr4_ipc.c b/sys/compat/svr4/svr4_ipc.c deleted file mode 100644 index ad4d608327b..00000000000 --- a/sys/compat/svr4/svr4_ipc.c +++ /dev/null @@ -1,678 +0,0 @@ -/*- - * Copyright (c) 1995 The NetBSD Foundation, Inc. - * All rights reserved. - * - * This code is derived from software contributed to The NetBSD Foundation - * by Christos Zoulas. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS - * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ -/*- - * Portions of this code have been derived from software contributed - * to the FreeBSD Project by Mark Newton. - * - * Copyright (c) 1999 Mark Newton - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * XXX- This code is presently a no-op on FreeBSD (and isn't compiled due - * to preprocessor conditionals). A nice project for a kernel hacking - * novice might be to MakeItGo, but I have more important fish to fry - * at present. - * - * Derived from: $NetBSD: svr4_ipc.c,v 1.7 1998/10/19 22:43:00 tron Exp $ - */ - -#include - -#include "opt_sysvipc.h" - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -static void svr4_to_bsd_ipc_perm(const struct svr4_ipc_perm *, - struct ipc_perm *); -static void bsd_to_svr4_ipc_perm(const struct ipc_perm *, - struct svr4_ipc_perm *); -static void bsd_to_svr4_semid_ds(const struct semid_ds *, - struct svr4_semid_ds *); -static void svr4_to_bsd_semid_ds(const struct svr4_semid_ds *, - struct semid_ds *); -static int svr4_semop(struct thread *, void *); -static int svr4_semget(struct thread *, void *); -static int svr4_semctl(struct thread *, void *); -static void bsd_to_svr4_msqid_ds(const struct msqid_ds *, - struct svr4_msqid_ds *); -static void svr4_to_bsd_msqid_ds(const struct svr4_msqid_ds *, - struct msqid_ds *); -static int svr4_msgsnd(struct thread *, void *); -static int svr4_msgrcv(struct thread *, void *); -static int svr4_msgget(struct thread *, void *); -static int svr4_msgctl(struct thread *, void *); -static void bsd_to_svr4_shmid_ds(const struct shmid_ds *, - struct svr4_shmid_ds *); -static void svr4_to_bsd_shmid_ds(const struct svr4_shmid_ds *, - struct shmid_ds *); -static int svr4_shmat(struct thread *, void *); -static int svr4_shmdt(struct thread *, void *); -static int svr4_shmget(struct thread *, void *); -static int svr4_shmctl(struct thread *, void *); - -static void -svr4_to_bsd_ipc_perm(spp, bpp) - const struct svr4_ipc_perm *spp; - struct ipc_perm *bpp; -{ - bpp->key = spp->key; - bpp->uid = spp->uid; - bpp->gid = spp->gid; - bpp->cuid = spp->cuid; - bpp->cgid = spp->cgid; - bpp->mode = spp->mode; - bpp->seq = spp->seq; -} - -static void -bsd_to_svr4_ipc_perm(bpp, spp) - const struct ipc_perm *bpp; - struct svr4_ipc_perm *spp; -{ - spp->key = bpp->key; - spp->uid = bpp->uid; - spp->gid = bpp->gid; - spp->cuid = bpp->cuid; - spp->cgid = bpp->cgid; - spp->mode = bpp->mode; - spp->seq = bpp->seq; -} - -static void -bsd_to_svr4_semid_ds(bds, sds) - const struct semid_ds *bds; - struct svr4_semid_ds *sds; -{ - bzero(sds, sizeof(*sds)); - bsd_to_svr4_ipc_perm(&bds->sem_perm, &sds->sem_perm); - sds->sem_base = (struct svr4_sem *) bds->sem_base; - sds->sem_nsems = bds->sem_nsems; - sds->sem_otime = bds->sem_otime; - sds->sem_ctime = bds->sem_ctime; -} - -static void -svr4_to_bsd_semid_ds(sds, bds) - const struct svr4_semid_ds *sds; - struct semid_ds *bds; -{ - svr4_to_bsd_ipc_perm(&sds->sem_perm, &bds->sem_perm); - bds->sem_base = (struct sem *) bds->sem_base; - bds->sem_nsems = sds->sem_nsems; - bds->sem_otime = sds->sem_otime; - bds->sem_ctime = sds->sem_ctime; -} - -struct svr4_sys_semctl_args { - int what; - int semid; - int semnum; - int cmd; - union semun arg; -}; - -static int -svr4_semctl(td, v) - struct thread *td; - void *v; -{ - struct svr4_sys_semctl_args *uap = v; - struct svr4_semid_ds ss; - struct semid_ds bs; - union semun semun; - register_t rval; - int cmd, error; - - switch (uap->cmd) { - case SVR4_SEM_GETZCNT: - cmd = GETZCNT; - break; - - case SVR4_SEM_GETNCNT: - cmd = GETNCNT; - break; - - case SVR4_SEM_GETPID: - cmd = GETPID; - break; - - case SVR4_SEM_GETVAL: - cmd = GETVAL; - break; - - case SVR4_SEM_SETVAL: - cmd = SETVAL; - break; - - case SVR4_SEM_GETALL: - cmd = GETVAL; - break; - - case SVR4_SEM_SETALL: - cmd = SETVAL; - break; - - case SVR4_IPC_STAT: - cmd = IPC_STAT; - semun.buf = &bs; - error = kern_semctl(td, uap->semid, uap->semnum, cmd, &semun, - &rval); - if (error) - return (error); - bsd_to_svr4_semid_ds(&bs, &ss); - error = copyout(&ss, uap->arg.buf, sizeof(ss)); - if (error == 0) - td->td_retval[0] = rval; - return (error); - - case SVR4_IPC_SET: - cmd = IPC_SET; - error = copyin(uap->arg.buf, (caddr_t) &ss, sizeof ss); - if (error) - return (error); - svr4_to_bsd_semid_ds(&ss, &bs); - semun.buf = &bs; - return (kern_semctl(td, uap->semid, uap->semnum, cmd, &semun, - td->td_retval)); - - case SVR4_IPC_RMID: - cmd = IPC_RMID; - break; - - default: - return EINVAL; - } - - return (kern_semctl(td, uap->semid, uap->semnum, cmd, &uap->arg, - td->td_retval)); -} - -struct svr4_sys_semget_args { - int what; - svr4_key_t key; - int nsems; - int semflg; -}; - -static int -svr4_semget(td, v) - struct thread *td; - void *v; -{ - struct svr4_sys_semget_args *uap = v; - struct semget_args ap; - - ap.key = uap->key; - ap.nsems = uap->nsems; - ap.semflg = uap->semflg; - - return sys_semget(td, &ap); -} - -struct svr4_sys_semop_args { - int what; - int semid; - struct svr4_sembuf * sops; - u_int nsops; -}; - -static int -svr4_semop(td, v) - struct thread *td; - void *v; -{ - struct svr4_sys_semop_args *uap = v; - struct semop_args ap; - - ap.semid = uap->semid; - /* These are the same */ - ap.sops = (struct sembuf *) uap->sops; - ap.nsops = uap->nsops; - - return sys_semop(td, &ap); -} - -int -svr4_sys_semsys(td, uap) - struct thread *td; - struct svr4_sys_semsys_args *uap; -{ - - DPRINTF(("svr4_semsys(%d)\n", uap->what)); - - switch (uap->what) { - case SVR4_semctl: - return svr4_semctl(td, uap); - case SVR4_semget: - return svr4_semget(td, uap); - case SVR4_semop: - return svr4_semop(td, uap); - default: - return EINVAL; - } -} - - -static void -bsd_to_svr4_msqid_ds(bds, sds) - const struct msqid_ds *bds; - struct svr4_msqid_ds *sds; -{ - bzero(sds, sizeof(*sds)); - bsd_to_svr4_ipc_perm(&bds->msg_perm, &sds->msg_perm); - sds->msg_first = (struct svr4_msg *) bds->msg_first; - sds->msg_last = (struct svr4_msg *) bds->msg_last; - sds->msg_cbytes = bds->msg_cbytes; - sds->msg_qnum = bds->msg_qnum; - sds->msg_qbytes = bds->msg_qbytes; - sds->msg_lspid = bds->msg_lspid; - sds->msg_lrpid = bds->msg_lrpid; - sds->msg_stime = bds->msg_stime; - sds->msg_rtime = bds->msg_rtime; - sds->msg_ctime = bds->msg_ctime; -} - -static void -svr4_to_bsd_msqid_ds(sds, bds) - const struct svr4_msqid_ds *sds; - struct msqid_ds *bds; -{ - svr4_to_bsd_ipc_perm(&sds->msg_perm, &bds->msg_perm); - bds->msg_first = (struct msg *) sds->msg_first; - bds->msg_last = (struct msg *) sds->msg_last; - bds->msg_cbytes = sds->msg_cbytes; - bds->msg_qnum = sds->msg_qnum; - bds->msg_qbytes = sds->msg_qbytes; - bds->msg_lspid = sds->msg_lspid; - bds->msg_lrpid = sds->msg_lrpid; - bds->msg_stime = sds->msg_stime; - bds->msg_rtime = sds->msg_rtime; - bds->msg_ctime = sds->msg_ctime; -} - -struct svr4_sys_msgsnd_args { - int what; - int msqid; - void * msgp; - size_t msgsz; - int msgflg; -}; - -static int -svr4_msgsnd(td, v) - struct thread *td; - void *v; -{ - struct svr4_sys_msgsnd_args *uap = v; - struct msgsnd_args ap; - - ap.msqid = uap->msqid; - ap.msgp = uap->msgp; - ap.msgsz = uap->msgsz; - ap.msgflg = uap->msgflg; - - return sys_msgsnd(td, &ap); -} - -struct svr4_sys_msgrcv_args { - int what; - int msqid; - void * msgp; - size_t msgsz; - long msgtyp; - int msgflg; -}; - -static int -svr4_msgrcv(td, v) - struct thread *td; - void *v; -{ - struct svr4_sys_msgrcv_args *uap = v; - struct msgrcv_args ap; - - ap.msqid = uap->msqid; - ap.msgp = uap->msgp; - ap.msgsz = uap->msgsz; - ap.msgtyp = uap->msgtyp; - ap.msgflg = uap->msgflg; - - return sys_msgrcv(td, &ap); -} - -struct svr4_sys_msgget_args { - int what; - svr4_key_t key; - int msgflg; -}; - -static int -svr4_msgget(td, v) - struct thread *td; - void *v; -{ - struct svr4_sys_msgget_args *uap = v; - struct msgget_args ap; - - ap.key = uap->key; - ap.msgflg = uap->msgflg; - - return sys_msgget(td, &ap); -} - -struct svr4_sys_msgctl_args { - int what; - int msqid; - int cmd; - struct svr4_msqid_ds * buf; -}; - -static int -svr4_msgctl(td, v) - struct thread *td; - void *v; -{ - struct svr4_sys_msgctl_args *uap = v; - struct svr4_msqid_ds ss; - struct msqid_ds bs; - int error; - - switch (uap->cmd) { - case SVR4_IPC_STAT: - error = kern_msgctl(td, uap->msqid, IPC_STAT, &bs); - if (error) - return error; - bsd_to_svr4_msqid_ds(&bs, &ss); - return copyout(&ss, uap->buf, sizeof ss); - - case SVR4_IPC_SET: - error = copyin(uap->buf, &ss, sizeof ss); - if (error) - return error; - svr4_to_bsd_msqid_ds(&ss, &bs); - return (kern_msgctl(td, uap->msqid, IPC_SET, &bs)); - - case SVR4_IPC_RMID: - return (kern_msgctl(td, uap->msqid, IPC_RMID, NULL)); - - default: - return EINVAL; - } -} - -int -svr4_sys_msgsys(td, uap) - struct thread *td; - struct svr4_sys_msgsys_args *uap; -{ - - DPRINTF(("svr4_msgsys(%d)\n", uap->what)); - - switch (uap->what) { - case SVR4_msgsnd: - return svr4_msgsnd(td, uap); - case SVR4_msgrcv: - return svr4_msgrcv(td, uap); - case SVR4_msgget: - return svr4_msgget(td, uap); - case SVR4_msgctl: - return svr4_msgctl(td, uap); - default: - return EINVAL; - } -} - - -static void -bsd_to_svr4_shmid_ds(bds, sds) - const struct shmid_ds *bds; - struct svr4_shmid_ds *sds; -{ - bzero(sds, sizeof(*sds)); - bsd_to_svr4_ipc_perm(&bds->shm_perm, &sds->shm_perm); - sds->shm_segsz = bds->shm_segsz; - sds->shm_lkcnt = 0; - sds->shm_lpid = bds->shm_lpid; - sds->shm_cpid = bds->shm_cpid; - sds->shm_amp = 0; - sds->shm_nattch = bds->shm_nattch; - sds->shm_cnattch = 0; - sds->shm_atime = bds->shm_atime; - sds->shm_dtime = bds->shm_dtime; - sds->shm_ctime = bds->shm_ctime; -} - -static void -svr4_to_bsd_shmid_ds(sds, bds) - const struct svr4_shmid_ds *sds; - struct shmid_ds *bds; -{ - svr4_to_bsd_ipc_perm(&sds->shm_perm, &bds->shm_perm); - bds->shm_segsz = sds->shm_segsz; - bds->shm_lpid = sds->shm_lpid; - bds->shm_cpid = sds->shm_cpid; - bds->shm_nattch = sds->shm_nattch; - bds->shm_atime = sds->shm_atime; - bds->shm_dtime = sds->shm_dtime; - bds->shm_ctime = sds->shm_ctime; -} - -struct svr4_sys_shmat_args { - int what; - int shmid; - void * shmaddr; - int shmflg; -}; - -static int -svr4_shmat(td, v) - struct thread *td; - void *v; -{ - struct svr4_sys_shmat_args *uap = v; - struct shmat_args ap; - - ap.shmid = uap->shmid; - ap.shmaddr = uap->shmaddr; - ap.shmflg = uap->shmflg; - - return sys_shmat(td, &ap); -} - -struct svr4_sys_shmdt_args { - int what; - void * shmaddr; -}; - -static int -svr4_shmdt(td, v) - struct thread *td; - void *v; -{ - struct svr4_sys_shmdt_args *uap = v; - struct shmdt_args ap; - - ap.shmaddr = uap->shmaddr; - - return sys_shmdt(td, &ap); -} - -struct svr4_sys_shmget_args { - int what; - key_t key; - int size; - int shmflg; -}; - -static int -svr4_shmget(td, v) - struct thread *td; - void *v; -{ - struct svr4_sys_shmget_args *uap = v; - struct shmget_args ap; - - ap.key = uap->key; - ap.size = uap->size; - ap.shmflg = uap->shmflg; - - return sys_shmget(td, &ap); -} - -struct svr4_sys_shmctl_args { - int what; - int shmid; - int cmd; - struct svr4_shmid_ds * buf; -}; - -int -svr4_shmctl(td, v) - struct thread *td; - void *v; -{ - struct svr4_sys_shmctl_args *uap = v; - struct shmid_ds bs; - struct svr4_shmid_ds ss; - size_t bufsize; - int cmd, error; - - if (uap->buf != NULL) { - switch (uap->cmd) { - case SVR4_IPC_SET: - case SVR4_SHM_LOCK: - case SVR4_SHM_UNLOCK: - error = copyin(uap->buf, &ss, sizeof(ss)); - if (error) - return (error); - svr4_to_bsd_shmid_ds(&ss, &bs); - break; - default: - return (EINVAL); - } - } - - switch (uap->cmd) { - case SVR4_IPC_STAT: - cmd = IPC_STAT; - break; - case SVR4_IPC_SET: - cmd = IPC_SET; - break; - case SVR4_IPC_RMID: - cmd = IPC_RMID; - break; - case SVR4_SHM_LOCK: - cmd = SHM_LOCK; - break; - case SVR4_SHM_UNLOCK: - cmd = SHM_UNLOCK; - break; - default: - return (EINVAL); - } - - error = kern_shmctl(td, uap->shmid, cmd, &bs, &bufsize); - if (error) - return (error); - - switch (uap->cmd) { - case SVR4_IPC_STAT: - if (uap->buf != NULL) { - bsd_to_svr4_shmid_ds(&bs, &ss); - error = copyout(&ss, uap->buf, sizeof(ss)); - } - break; - } - - return (error); -} - -int -svr4_sys_shmsys(td, uap) - struct thread *td; - struct svr4_sys_shmsys_args *uap; -{ - - DPRINTF(("svr4_shmsys(%d)\n", uap->what)); - - switch (uap->what) { - case SVR4_shmat: - return svr4_shmat(td, uap); - case SVR4_shmdt: - return svr4_shmdt(td, uap); - case SVR4_shmget: - return svr4_shmget(td, uap); - case SVR4_shmctl: - return svr4_shmctl(td, uap); - default: - return ENOSYS; - } -} - -MODULE_DEPEND(svr4elf, sysvshm, 1, 1, 1); -MODULE_DEPEND(svr4elf, sysvmsg, 1, 1, 1); -MODULE_DEPEND(svr4elf, sysvsem, 1, 1, 1); diff --git a/sys/compat/svr4/svr4_ipc.h b/sys/compat/svr4/svr4_ipc.h deleted file mode 100644 index 83043acb3be..00000000000 --- a/sys/compat/svr4/svr4_ipc.h +++ /dev/null @@ -1,176 +0,0 @@ -/*- - * Copyright (c) 1998 Mark Newton - * Copyright (c) 1995 Christos Zoulas. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by Christos Zoulas. - * 4. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * $FreeBSD: stable/11/sys/compat/svr4/svr4_ipc.h 139743 2005-01-05 22:34:37Z imp $ - */ - -#ifndef _SVR4_IPC_H_ -#define _SVR4_IPC_H_ - -/* - * General IPC - */ -#define SVR4_IPC_RMID 10 -#define SVR4_IPC_SET 11 -#define SVR4_IPC_STAT 12 - -struct svr4_ipc_perm { - svr4_uid_t uid; - svr4_gid_t gid; - svr4_uid_t cuid; - svr4_gid_t cgid; - svr4_mode_t mode; - u_long seq; - svr4_key_t key; - long pad[4]; -}; - -/* - * Message queues - */ -#define SVR4_msgget 0 -#define SVR4_msgctl 1 -#define SVR4_msgrcv 2 -#define SVR4_msgsnd 3 - -struct svr4_msg { - struct svr4_msg *msg_next; - long msg_type; - u_short msg_ts; - short msg_spot; -}; - -struct svr4_msqid_ds { - struct svr4_ipc_perm msg_perm; - struct svr4_msg *msg_first; - struct svr4_msg *msg_last; - u_long msg_cbytes; - u_long msg_qnum; - u_long msg_qbytes; - svr4_pid_t msg_lspid; - svr4_pid_t msg_lrpid; - svr4_time_t msg_stime; - long msg_pad1; - svr4_time_t msg_rtime; - long msg_pad2; - svr4_time_t msg_ctime; - long msg_pad3; - short msg_cv; - short msg_qnum_cv; - long msg_pad4[3]; -}; - -struct svr4_msgbuf { - long mtype; /* message type */ - char mtext[1]; /* message text */ -}; - -struct svr4_msginfo { - int msgmap; - int msgmax; - int msgmnb; - int msgmni; - int msgssz; - int msgtql; - u_short msgseg; -}; - -/* - * Shared memory - */ -#define SVR4_shmat 0 -#define SVR4_shmctl 1 -#define SVR4_shmdt 2 -#define SVR4_shmget 3 - -/* shmctl() operations */ -#define SVR4_SHM_LOCK 3 -#define SVR4_SHM_UNLOCK 4 - -struct svr4_shmid_ds { - struct svr4_ipc_perm shm_perm; - int shm_segsz; - void *shm_amp; - u_short shm_lkcnt; - svr4_pid_t shm_lpid; - svr4_pid_t shm_cpid; - u_long shm_nattch; - u_long shm_cnattch; - svr4_time_t shm_atime; - long shm_pad1; - svr4_time_t shm_dtime; - long shm_pad2; - svr4_time_t shm_ctime; - long shm_pad3; - long shm_pad4[4]; -}; - -/* - * Semaphores - */ -#define SVR4_semctl 0 -#define SVR4_semget 1 -#define SVR4_semop 2 - -/* semctl() operations */ -#define SVR4_SEM_GETNCNT 3 -#define SVR4_SEM_GETPID 4 -#define SVR4_SEM_GETVAL 5 -#define SVR4_SEM_GETALL 6 -#define SVR4_SEM_GETZCNT 7 -#define SVR4_SEM_SETVAL 8 -#define SVR4_SEM_SETALL 9 - -struct svr4_sem { - u_short semval; - svr4_pid_t sempid; - u_short semncnt; - u_short semzcnt; - u_short semncnt_cv; - u_short semzcnt_cv; -}; - -struct svr4_semid_ds { - struct svr4_ipc_perm sem_perm; - struct svr4_sem *sem_base; - u_short sem_nsems; - svr4_time_t sem_otime; - long sem_pad1; - svr4_time_t sem_ctime; - long sem_pad2; - long sem_pad3[4]; -}; - -struct svr4_sembuf { - u_short sem_num; - short sem_op; - short sem_flg; -}; - -#endif /* _SVR4_IPC_H */ diff --git a/sys/compat/svr4/svr4_misc.c b/sys/compat/svr4/svr4_misc.c deleted file mode 100644 index 6e2f0f3539d..00000000000 --- a/sys/compat/svr4/svr4_misc.c +++ /dev/null @@ -1,1680 +0,0 @@ -/*- - * Copyright (c) 1998 Mark Newton - * Copyright (c) 1994 Christos Zoulas - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/* - * SVR4 compatibility module. - * - * SVR4 system calls that are implemented differently in BSD are - * handled here. - */ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include /* Must come after sys/malloc.h */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include -#include -#include -#if defined(__MidnightBSD__) -#include -#include -#endif - -#if defined(NetBSD) -# if defined(UVM) -# include -# endif -#endif - -#define BSD_DIRENT(cp) ((struct dirent *)(cp)) - -static int svr4_mknod(struct thread *, register_t *, char *, - svr4_mode_t, svr4_dev_t); - -static __inline clock_t timeval_to_clock_t(struct timeval *); -static int svr4_setinfo (pid_t , struct rusage *, int, svr4_siginfo_t *); - -struct svr4_hrtcntl_args; -static int svr4_hrtcntl (struct thread *, struct svr4_hrtcntl_args *, - register_t *); -static void bsd_statfs_to_svr4_statvfs(const struct statfs *, - struct svr4_statvfs *); -static void bsd_statfs_to_svr4_statvfs64(const struct statfs *, - struct svr4_statvfs64 *); -static struct proc *svr4_pfind(pid_t pid); - -/* BOGUS noop */ -#if defined(BOGUS) -int -svr4_sys_setitimer(td, uap) - struct thread *td; - struct svr4_sys_setitimer_args *uap; -{ - td->td_retval[0] = 0; - return 0; -} -#endif - -int -svr4_sys_wait(td, uap) - struct thread *td; - struct svr4_sys_wait_args *uap; -{ - int error, st, sig; - - error = kern_wait(td, WAIT_ANY, &st, 0, NULL); - if (error) - return (error); - - if (WIFSIGNALED(st)) { - sig = WTERMSIG(st); - if (sig >= 0 && sig < NSIG) - st = (st & ~0177) | SVR4_BSD2SVR4_SIG(sig); - } else if (WIFSTOPPED(st)) { - sig = WSTOPSIG(st); - if (sig >= 0 && sig < NSIG) - st = (st & ~0xff00) | (SVR4_BSD2SVR4_SIG(sig) << 8); - } - - /* - * It looks like wait(2) on svr4/solaris/2.4 returns - * the status in retval[1], and the pid on retval[0]. - */ - td->td_retval[1] = st; - - if (uap->status) - error = copyout(&st, uap->status, sizeof(st)); - - return (error); -} - -int -svr4_sys_execv(td, uap) - struct thread *td; - struct svr4_sys_execv_args *uap; -{ - struct image_args eargs; - struct vmspace *oldvmspace; - char *path; - int error; - - CHECKALTEXIST(td, uap->path, &path); - - error = pre_execve(td, &oldvmspace); - if (error != 0) { - free(path, M_TEMP); - return (error); - } - error = exec_copyin_args(&eargs, path, UIO_SYSSPACE, uap->argp, NULL); - free(path, M_TEMP); - if (error == 0) - error = kern_execve(td, &eargs, NULL); - post_execve(td, error, oldvmspace); - return (error); -} - -int -svr4_sys_execve(td, uap) - struct thread *td; - struct svr4_sys_execve_args *uap; -{ - struct image_args eargs; - struct vmspace *oldvmspace; - char *path; - int error; - - CHECKALTEXIST(td, uap->path, &path); - - error = pre_execve(td, &oldvmspace); - if (error != 0) { - free(path, M_TEMP); - return (error); - } - error = exec_copyin_args(&eargs, path, UIO_SYSSPACE, uap->argp, - uap->envp); - free(path, M_TEMP); - if (error == 0) - error = kern_execve(td, &eargs, NULL); - post_execve(td, error, oldvmspace); - return (error); -} - -int -svr4_sys_time(td, v) - struct thread *td; - struct svr4_sys_time_args *v; -{ - struct svr4_sys_time_args *uap = v; - int error = 0; - struct timeval tv; - - microtime(&tv); - if (uap->t) - error = copyout(&tv.tv_sec, uap->t, - sizeof(*(uap->t))); - td->td_retval[0] = (int) tv.tv_sec; - - return error; -} - - -/* - * Read SVR4-style directory entries. We suck them into kernel space so - * that they can be massaged before being copied out to user code. - * - * This code is ported from the Linux emulator: Changes to the VFS interface - * between FreeBSD and NetBSD have made it simpler to port it from there than - * to adapt the NetBSD version. - */ -int -svr4_sys_getdents64(td, uap) - struct thread *td; - struct svr4_sys_getdents64_args *uap; -{ - struct dirent *bdp; - struct vnode *vp; - caddr_t inp, buf; /* BSD-format */ - int len, reclen; /* BSD-format */ - caddr_t outp; /* SVR4-format */ - int resid, svr4reclen=0; /* SVR4-format */ - cap_rights_t rights; - struct file *fp; - struct uio auio; - struct iovec aiov; - off_t off; - struct svr4_dirent64 svr4_dirent; - int buflen, error, eofflag, nbytes, justone; - u_long *cookies = NULL, *cookiep; - int ncookies; - - memset(&svr4_dirent, 0, sizeof(svr4_dirent)); - DPRINTF(("svr4_sys_getdents64(%d, *, %d)\n", - uap->fd, uap->nbytes)); - error = getvnode(td, uap->fd, cap_rights_init(&rights, CAP_READ), &fp); - if (error != 0) - return (error); - - if ((fp->f_flag & FREAD) == 0) { - fdrop(fp, td); - return (EBADF); - } - - vp = fp->f_vnode; - if (vp->v_type != VDIR) { - fdrop(fp, td); - return (EINVAL); - } - - nbytes = uap->nbytes; - if (nbytes == 1) { - nbytes = sizeof (struct svr4_dirent64); - justone = 1; - } - else - justone = 0; - - off = fp->f_offset; -#define DIRBLKSIZ 512 /* XXX we used to use ufs's DIRBLKSIZ */ - buflen = max(DIRBLKSIZ, nbytes); - buflen = min(buflen, MAXBSIZE); - buf = malloc(buflen, M_TEMP, M_WAITOK); - vn_lock(vp, LK_SHARED | LK_RETRY); -again: - aiov.iov_base = buf; - aiov.iov_len = buflen; - auio.uio_iov = &aiov; - auio.uio_iovcnt = 1; - auio.uio_rw = UIO_READ; - auio.uio_segflg = UIO_SYSSPACE; - auio.uio_td = td; - auio.uio_resid = buflen; - auio.uio_offset = off; - - if (cookies) { - free(cookies, M_TEMP); - cookies = NULL; - } - -#ifdef MAC - error = mac_vnode_check_readdir(td->td_ucred, vp); - if (error) - goto out; -#endif - - error = VOP_READDIR(vp, &auio, fp->f_cred, &eofflag, - &ncookies, &cookies); - if (error) { - goto out; - } - - inp = buf; - outp = (caddr_t) uap->dp; - resid = nbytes; - if ((len = buflen - auio.uio_resid) <= 0) { - goto eof; - } - - cookiep = cookies; - - if (cookies) { - /* - * When using cookies, the vfs has the option of reading from - * a different offset than that supplied (UFS truncates the - * offset to a block boundary to make sure that it never reads - * partway through a directory entry, even if the directory - * has been compacted). - */ - while (len > 0 && ncookies > 0 && *cookiep <= off) { - bdp = (struct dirent *) inp; - len -= bdp->d_reclen; - inp += bdp->d_reclen; - cookiep++; - ncookies--; - } - } - - while (len > 0) { - if (cookiep && ncookies == 0) - break; - bdp = (struct dirent *) inp; - reclen = bdp->d_reclen; - if (reclen & 3) { - DPRINTF(("svr4_readdir: reclen=%d\n", reclen)); - error = EFAULT; - goto out; - } - - if (bdp->d_fileno == 0) { - inp += reclen; - if (cookiep) { - off = *cookiep++; - ncookies--; - } else - off += reclen; - len -= reclen; - continue; - } - svr4reclen = SVR4_RECLEN(&svr4_dirent, bdp->d_namlen); - if (reclen > len || resid < svr4reclen) { - outp++; - break; - } - svr4_dirent.d_ino = (long) bdp->d_fileno; - if (justone) { - /* - * old svr4-style readdir usage. - */ - svr4_dirent.d_off = (svr4_off_t) svr4reclen; - svr4_dirent.d_reclen = (u_short) bdp->d_namlen; - } else { - svr4_dirent.d_off = (svr4_off_t)(off + reclen); - svr4_dirent.d_reclen = (u_short) svr4reclen; - } - strlcpy(svr4_dirent.d_name, bdp->d_name, sizeof(svr4_dirent.d_name)); - if ((error = copyout((caddr_t)&svr4_dirent, outp, svr4reclen))) - goto out; - inp += reclen; - if (cookiep) { - off = *cookiep++; - ncookies--; - } else - off += reclen; - outp += svr4reclen; - resid -= svr4reclen; - len -= reclen; - if (justone) - break; - } - - if (outp == (caddr_t) uap->dp) - goto again; - fp->f_offset = off; - - if (justone) - nbytes = resid + svr4reclen; - -eof: - td->td_retval[0] = nbytes - resid; -out: - VOP_UNLOCK(vp, 0); - fdrop(fp, td); - if (cookies) - free(cookies, M_TEMP); - free(buf, M_TEMP); - return error; -} - - -int -svr4_sys_getdents(td, uap) - struct thread *td; - struct svr4_sys_getdents_args *uap; -{ - struct dirent *bdp; - struct vnode *vp; - caddr_t inp, buf; /* BSD-format */ - int len, reclen; /* BSD-format */ - caddr_t outp; /* SVR4-format */ - int resid, svr4_reclen; /* SVR4-format */ - cap_rights_t rights; - struct file *fp; - struct uio auio; - struct iovec aiov; - struct svr4_dirent idb; - off_t off; /* true file offset */ - int buflen, error, eofflag; - u_long *cookiebuf = NULL, *cookie; - int ncookies = 0, *retval = td->td_retval; - - if (uap->nbytes < 0) - return (EINVAL); - - error = getvnode(td, uap->fd, cap_rights_init(&rights, CAP_READ), &fp); - if (error != 0) - return (error); - - if ((fp->f_flag & FREAD) == 0) { - fdrop(fp, td); - return (EBADF); - } - - vp = fp->f_vnode; - if (vp->v_type != VDIR) { - fdrop(fp, td); - return (EINVAL); - } - - buflen = min(MAXBSIZE, uap->nbytes); - buf = malloc(buflen, M_TEMP, M_WAITOK); - vn_lock(vp, LK_SHARED | LK_RETRY); - off = fp->f_offset; -again: - aiov.iov_base = buf; - aiov.iov_len = buflen; - auio.uio_iov = &aiov; - auio.uio_iovcnt = 1; - auio.uio_rw = UIO_READ; - auio.uio_segflg = UIO_SYSSPACE; - auio.uio_td = td; - auio.uio_resid = buflen; - auio.uio_offset = off; - -#ifdef MAC - error = mac_vnode_check_readdir(td->td_ucred, vp); - if (error) - goto out; -#endif - - /* - * First we read into the malloc'ed buffer, then - * we massage it into user space, one record at a time. - */ - error = VOP_READDIR(vp, &auio, fp->f_cred, &eofflag, &ncookies, - &cookiebuf); - if (error) { - goto out; - } - - inp = buf; - outp = uap->buf; - resid = uap->nbytes; - if ((len = buflen - auio.uio_resid) == 0) - goto eof; - - for (cookie = cookiebuf; len > 0; len -= reclen) { - bdp = (struct dirent *)inp; - reclen = bdp->d_reclen; - if (reclen & 3) - panic("svr4_sys_getdents64: bad reclen"); - if (cookie) - off = *cookie++; /* each entry points to the next */ - else - off += reclen; - if ((off >> 32) != 0) { - uprintf("svr4_sys_getdents64: dir offset too large for emulated program"); - error = EINVAL; - goto out; - } - if (bdp->d_fileno == 0) { - inp += reclen; /* it is a hole; squish it out */ - continue; - } - svr4_reclen = SVR4_RECLEN(&idb, bdp->d_namlen); - if (reclen > len || resid < svr4_reclen) { - /* entry too big for buffer, so just stop */ - outp++; - break; - } - /* - * Massage in place to make a SVR4-shaped dirent (otherwise - * we have to worry about touching user memory outside of - * the copyout() call). - */ - idb.d_ino = (svr4_ino_t)bdp->d_fileno; - idb.d_off = (svr4_off_t)off; - idb.d_reclen = (u_short)svr4_reclen; - strlcpy(idb.d_name, bdp->d_name, sizeof(idb.d_name)); - if ((error = copyout((caddr_t)&idb, outp, svr4_reclen))) - goto out; - /* advance past this real entry */ - inp += reclen; - /* advance output past SVR4-shaped entry */ - outp += svr4_reclen; - resid -= svr4_reclen; - } - - /* if we squished out the whole block, try again */ - if (outp == uap->buf) - goto again; - fp->f_offset = off; /* update the vnode offset */ - -eof: - *retval = uap->nbytes - resid; -out: - VOP_UNLOCK(vp, 0); - fdrop(fp, td); - if (cookiebuf) - free(cookiebuf, M_TEMP); - free(buf, M_TEMP); - return error; -} - - -int -svr4_sys_mmap(td, uap) - struct thread *td; - struct svr4_sys_mmap_args *uap; -{ - struct mmap_args mm; - int *retval; - - retval = td->td_retval; -#define _MAP_NEW 0x80000000 - /* - * Verify the arguments. - */ - if (uap->prot & ~(PROT_READ | PROT_WRITE | PROT_EXEC)) - return EINVAL; /* XXX still needed? */ - - if (uap->len == 0) - return EINVAL; - - mm.prot = uap->prot; - mm.len = uap->len; - mm.flags = uap->flags & ~_MAP_NEW; - mm.fd = uap->fd; - mm.addr = uap->addr; - mm.pos = uap->pos; - - return sys_mmap(td, &mm); -} - -int -svr4_sys_mmap64(td, uap) - struct thread *td; - struct svr4_sys_mmap64_args *uap; -{ - struct mmap_args mm; - void *rp; - -#define _MAP_NEW 0x80000000 - /* - * Verify the arguments. - */ - if (uap->prot & ~(PROT_READ | PROT_WRITE | PROT_EXEC)) - return EINVAL; /* XXX still needed? */ - - if (uap->len == 0) - return EINVAL; - - mm.prot = uap->prot; - mm.len = uap->len; - mm.flags = uap->flags & ~_MAP_NEW; - mm.fd = uap->fd; - mm.addr = uap->addr; - mm.pos = uap->pos; - - rp = (void *) round_page((vm_offset_t)(td->td_proc->p_vmspace->vm_daddr + maxdsiz)); - if ((mm.flags & MAP_FIXED) == 0 && - mm.addr != 0 && (void *)mm.addr < rp) - mm.addr = rp; - - return sys_mmap(td, &mm); -} - - -int -svr4_sys_fchroot(td, uap) - struct thread *td; - struct svr4_sys_fchroot_args *uap; -{ - cap_rights_t rights; - struct vnode *vp; - struct file *fp; - int error; - - if ((error = priv_check(td, PRIV_VFS_FCHROOT)) != 0) - return error; - /* XXX: we have the chroot priv... what cap might we need? all? */ - if ((error = getvnode(td, uap->fd, cap_rights_init(&rights), &fp)) != 0) - return error; - vp = fp->f_vnode; - VREF(vp); - fdrop(fp, td); - vn_lock(vp, LK_EXCLUSIVE | LK_RETRY); - error = change_dir(vp, td); - if (error) - goto fail; -#ifdef MAC - error = mac_vnode_check_chroot(td->td_ucred, vp); - if (error) - goto fail; -#endif - VOP_UNLOCK(vp, 0); - error = pwd_chroot(td, vp); - vrele(vp); - return (error); -fail: - vput(vp); - return (error); -} - - -static int -svr4_mknod(td, retval, path, mode, dev) - struct thread *td; - register_t *retval; - char *path; - svr4_mode_t mode; - svr4_dev_t dev; -{ - char *newpath; - int error; - - CHECKALTEXIST(td, path, &newpath); - - if (S_ISFIFO(mode)) { - error = kern_mkfifoat(td, AT_FDCWD, newpath, UIO_SYSSPACE, - mode); - } else { - error = kern_mknodat(td, AT_FDCWD, newpath, UIO_SYSSPACE, - mode, dev); - } - free(newpath, M_TEMP); - return (error); -} - - -int -svr4_sys_mknod(td, uap) - struct thread *td; - struct svr4_sys_mknod_args *uap; -{ - int *retval = td->td_retval; - return svr4_mknod(td, retval, - uap->path, uap->mode, - (svr4_dev_t)svr4_to_bsd_odev_t(uap->dev)); -} - - -int -svr4_sys_xmknod(td, uap) - struct thread *td; - struct svr4_sys_xmknod_args *uap; -{ - int *retval = td->td_retval; - return svr4_mknod(td, retval, - uap->path, uap->mode, - (svr4_dev_t)svr4_to_bsd_dev_t(uap->dev)); -} - - -int -svr4_sys_vhangup(td, uap) - struct thread *td; - struct svr4_sys_vhangup_args *uap; -{ - return 0; -} - - -int -svr4_sys_sysconfig(td, uap) - struct thread *td; - struct svr4_sys_sysconfig_args *uap; -{ - int *retval; - - retval = &(td->td_retval[0]); - - switch (uap->name) { - case SVR4_CONFIG_NGROUPS: - *retval = ngroups_max; - break; - case SVR4_CONFIG_CHILD_MAX: - *retval = maxproc; - break; - case SVR4_CONFIG_OPEN_FILES: - *retval = maxfiles; - break; - case SVR4_CONFIG_POSIX_VER: - *retval = 198808; - break; - case SVR4_CONFIG_PAGESIZE: - *retval = PAGE_SIZE; - break; - case SVR4_CONFIG_CLK_TCK: - *retval = 60; /* should this be `hz', ie. 100? */ - break; - case SVR4_CONFIG_XOPEN_VER: - *retval = 2; /* XXX: What should that be? */ - break; - case SVR4_CONFIG_PROF_TCK: - *retval = 60; /* XXX: What should that be? */ - break; - case SVR4_CONFIG_NPROC_CONF: - *retval = 1; /* Only one processor for now */ - break; - case SVR4_CONFIG_NPROC_ONLN: - *retval = 1; /* And it better be online */ - break; - case SVR4_CONFIG_AIO_LISTIO_MAX: - case SVR4_CONFIG_AIO_MAX: - case SVR4_CONFIG_AIO_PRIO_DELTA_MAX: - *retval = 0; /* No aio support */ - break; - case SVR4_CONFIG_DELAYTIMER_MAX: - *retval = 0; /* No delaytimer support */ - break; - case SVR4_CONFIG_MQ_OPEN_MAX: - *retval = msginfo.msgmni; - break; - case SVR4_CONFIG_MQ_PRIO_MAX: - *retval = 0; /* XXX: Don't know */ - break; - case SVR4_CONFIG_RTSIG_MAX: - *retval = 0; - break; - case SVR4_CONFIG_SEM_NSEMS_MAX: - *retval = seminfo.semmni; - break; - case SVR4_CONFIG_SEM_VALUE_MAX: - *retval = seminfo.semvmx; - break; - case SVR4_CONFIG_SIGQUEUE_MAX: - *retval = 0; /* XXX: Don't know */ - break; - case SVR4_CONFIG_SIGRT_MIN: - case SVR4_CONFIG_SIGRT_MAX: - *retval = 0; /* No real time signals */ - break; - case SVR4_CONFIG_TIMER_MAX: - *retval = 3; /* XXX: real, virtual, profiling */ - break; -#if defined(NOTYET) - case SVR4_CONFIG_PHYS_PAGES: -#if defined(UVM) - *retval = uvmexp.free; /* XXX: free instead of total */ -#else - *retval = vm_cnt.v_free_count; /* XXX: free instead of total */ -#endif - break; - case SVR4_CONFIG_AVPHYS_PAGES: -#if defined(UVM) - *retval = uvmexp.active; /* XXX: active instead of avg */ -#else - *retval = vm_cnt.v_active_count;/* XXX: active instead of avg */ -#endif - break; -#endif /* NOTYET */ - case SVR4_CONFIG_COHERENCY: - *retval = 0; /* XXX */ - break; - case SVR4_CONFIG_SPLIT_CACHE: - *retval = 0; /* XXX */ - break; - case SVR4_CONFIG_ICACHESZ: - *retval = 256; /* XXX */ - break; - case SVR4_CONFIG_DCACHESZ: - *retval = 256; /* XXX */ - break; - case SVR4_CONFIG_ICACHELINESZ: - *retval = 64; /* XXX */ - break; - case SVR4_CONFIG_DCACHELINESZ: - *retval = 64; /* XXX */ - break; - case SVR4_CONFIG_ICACHEBLKSZ: - *retval = 64; /* XXX */ - break; - case SVR4_CONFIG_DCACHEBLKSZ: - *retval = 64; /* XXX */ - break; - case SVR4_CONFIG_DCACHETBLKSZ: - *retval = 64; /* XXX */ - break; - case SVR4_CONFIG_ICACHE_ASSOC: - *retval = 1; /* XXX */ - break; - case SVR4_CONFIG_DCACHE_ASSOC: - *retval = 1; /* XXX */ - break; - case SVR4_CONFIG_MAXPID: - *retval = PID_MAX; - break; - case SVR4_CONFIG_STACK_PROT: - *retval = PROT_READ|PROT_WRITE|PROT_EXEC; - break; - default: - return EINVAL; - } - return 0; -} - -/* ARGSUSED */ -int -svr4_sys_break(td, uap) - struct thread *td; - struct svr4_sys_break_args *uap; -{ - struct obreak_args ap; - - ap.nsize = uap->nsize; - return (sys_obreak(td, &ap)); -} - -static __inline clock_t -timeval_to_clock_t(tv) - struct timeval *tv; -{ - return tv->tv_sec * hz + tv->tv_usec / (1000000 / hz); -} - - -int -svr4_sys_times(td, uap) - struct thread *td; - struct svr4_sys_times_args *uap; -{ - struct timeval tv, utime, stime, cutime, cstime; - struct tms tms; - struct proc *p; - int error; - - p = td->td_proc; - PROC_LOCK(p); - PROC_STATLOCK(p); - calcru(p, &utime, &stime); - PROC_STATUNLOCK(p); - calccru(p, &cutime, &cstime); - PROC_UNLOCK(p); - - tms.tms_utime = timeval_to_clock_t(&utime); - tms.tms_stime = timeval_to_clock_t(&stime); - - tms.tms_cutime = timeval_to_clock_t(&cutime); - tms.tms_cstime = timeval_to_clock_t(&cstime); - - error = copyout(&tms, uap->tp, sizeof(tms)); - if (error) - return (error); - - microtime(&tv); - td->td_retval[0] = (int)timeval_to_clock_t(&tv); - return (0); -} - - -int -svr4_sys_ulimit(td, uap) - struct thread *td; - struct svr4_sys_ulimit_args *uap; -{ - int *retval = td->td_retval; - int error; - - switch (uap->cmd) { - case SVR4_GFILLIM: - *retval = lim_cur(td, RLIMIT_FSIZE) / 512; - if (*retval == -1) - *retval = 0x7fffffff; - return 0; - - case SVR4_SFILLIM: - { - struct rlimit krl; - - krl.rlim_cur = uap->newlimit * 512; - krl.rlim_max = lim_max(td, RLIMIT_FSIZE); - - error = kern_setrlimit(td, RLIMIT_FSIZE, &krl); - if (error) - return error; - - *retval = lim_cur(td, RLIMIT_FSIZE); - if (*retval == -1) - *retval = 0x7fffffff; - return 0; - } - - case SVR4_GMEMLIM: - { - struct vmspace *vm = td->td_proc->p_vmspace; - register_t r; - - r = lim_cur(td, RLIMIT_DATA); - - if (r == -1) - r = 0x7fffffff; - r += (long) vm->vm_daddr; - if (r < 0) - r = 0x7fffffff; - *retval = r; - return 0; - } - - case SVR4_GDESLIM: - *retval = lim_cur(td, RLIMIT_NOFILE); - if (*retval == -1) - *retval = 0x7fffffff; - return 0; - - default: - return EINVAL; - } -} - -static struct proc * -svr4_pfind(pid) - pid_t pid; -{ - struct proc *p; - - /* look in the live processes */ - if ((p = pfind(pid)) == NULL) - /* look in the zombies */ - p = zpfind(pid); - - return p; -} - - -int -svr4_sys_pgrpsys(td, uap) - struct thread *td; - struct svr4_sys_pgrpsys_args *uap; -{ - int *retval = td->td_retval; - struct proc *p = td->td_proc; - - switch (uap->cmd) { - case 1: /* setpgrp() */ - /* - * SVR4 setpgrp() (which takes no arguments) has the - * semantics that the session ID is also created anew, so - * in almost every sense, setpgrp() is identical to - * setsid() for SVR4. (Under BSD, the difference is that - * a setpgid(0,0) will not create a new session.) - */ - sys_setsid(td, NULL); - /*FALLTHROUGH*/ - - case 0: /* getpgrp() */ - PROC_LOCK(p); - *retval = p->p_pgrp->pg_id; - PROC_UNLOCK(p); - return 0; - - case 2: /* getsid(pid) */ - if (uap->pid == 0) - PROC_LOCK(p); - else if ((p = svr4_pfind(uap->pid)) == NULL) - return ESRCH; - /* - * This has already been initialized to the pid of - * the session leader. - */ - *retval = (register_t) p->p_session->s_sid; - PROC_UNLOCK(p); - return 0; - - case 3: /* setsid() */ - return sys_setsid(td, NULL); - - case 4: /* getpgid(pid) */ - - if (uap->pid == 0) - PROC_LOCK(p); - else if ((p = svr4_pfind(uap->pid)) == NULL) - return ESRCH; - - *retval = (int) p->p_pgrp->pg_id; - PROC_UNLOCK(p); - return 0; - - case 5: /* setpgid(pid, pgid); */ - { - struct setpgid_args sa; - - sa.pid = uap->pid; - sa.pgid = uap->pgid; - return sys_setpgid(td, &sa); - } - - default: - return EINVAL; - } -} - -struct svr4_hrtcntl_args { - int cmd; - int fun; - int clk; - svr4_hrt_interval_t * iv; - svr4_hrt_time_t * ti; -}; - - -static int -svr4_hrtcntl(td, uap, retval) - struct thread *td; - struct svr4_hrtcntl_args *uap; - register_t *retval; -{ - switch (uap->fun) { - case SVR4_HRT_CNTL_RES: - DPRINTF(("htrcntl(RES)\n")); - *retval = SVR4_HRT_USEC; - return 0; - - case SVR4_HRT_CNTL_TOFD: - DPRINTF(("htrcntl(TOFD)\n")); - { - struct timeval tv; - svr4_hrt_time_t t; - if (uap->clk != SVR4_HRT_CLK_STD) { - DPRINTF(("clk == %d\n", uap->clk)); - return EINVAL; - } - if (uap->ti == NULL) { - DPRINTF(("ti NULL\n")); - return EINVAL; - } - microtime(&tv); - t.h_sec = tv.tv_sec; - t.h_rem = tv.tv_usec; - t.h_res = SVR4_HRT_USEC; - return copyout(&t, uap->ti, sizeof(t)); - } - - case SVR4_HRT_CNTL_START: - DPRINTF(("htrcntl(START)\n")); - return ENOSYS; - - case SVR4_HRT_CNTL_GET: - DPRINTF(("htrcntl(GET)\n")); - return ENOSYS; - default: - DPRINTF(("Bad htrcntl command %d\n", uap->fun)); - return ENOSYS; - } -} - - -int -svr4_sys_hrtsys(td, uap) - struct thread *td; - struct svr4_sys_hrtsys_args *uap; -{ - int *retval = td->td_retval; - - switch (uap->cmd) { - case SVR4_HRT_CNTL: - return svr4_hrtcntl(td, (struct svr4_hrtcntl_args *) uap, - retval); - - case SVR4_HRT_ALRM: - DPRINTF(("hrtalarm\n")); - return ENOSYS; - - case SVR4_HRT_SLP: - DPRINTF(("hrtsleep\n")); - return ENOSYS; - - case SVR4_HRT_CAN: - DPRINTF(("hrtcancel\n")); - return ENOSYS; - - default: - DPRINTF(("Bad hrtsys command %d\n", uap->cmd)); - return EINVAL; - } -} - - -static int -svr4_setinfo(pid, ru, st, s) - pid_t pid; - struct rusage *ru; - int st; - svr4_siginfo_t *s; -{ - svr4_siginfo_t i; - int sig; - - memset(&i, 0, sizeof(i)); - - i.svr4_si_signo = SVR4_SIGCHLD; - i.svr4_si_errno = 0; /* XXX? */ - - i.svr4_si_pid = pid; - if (ru) { - i.svr4_si_stime = ru->ru_stime.tv_sec; - i.svr4_si_utime = ru->ru_utime.tv_sec; - } - - if (WIFEXITED(st)) { - i.svr4_si_status = WEXITSTATUS(st); - i.svr4_si_code = SVR4_CLD_EXITED; - } else if (WIFSTOPPED(st)) { - sig = WSTOPSIG(st); - if (sig >= 0 && sig < NSIG) - i.svr4_si_status = SVR4_BSD2SVR4_SIG(sig); - - if (i.svr4_si_status == SVR4_SIGCONT) - i.svr4_si_code = SVR4_CLD_CONTINUED; - else - i.svr4_si_code = SVR4_CLD_STOPPED; - } else { - sig = WTERMSIG(st); - if (sig >= 0 && sig < NSIG) - i.svr4_si_status = SVR4_BSD2SVR4_SIG(sig); - - if (WCOREDUMP(st)) - i.svr4_si_code = SVR4_CLD_DUMPED; - else - i.svr4_si_code = SVR4_CLD_KILLED; - } - - DPRINTF(("siginfo [pid %ld signo %d code %d errno %d status %d]\n", - i.svr4_si_pid, i.svr4_si_signo, i.svr4_si_code, i.svr4_si_errno, - i.svr4_si_status)); - - return copyout(&i, s, sizeof(i)); -} - - -int -svr4_sys_waitsys(td, uap) - struct thread *td; - struct svr4_sys_waitsys_args *uap; -{ - struct rusage ru; - pid_t pid; - int nfound, status; - int error, *retval = td->td_retval; - struct proc *p, *q; - - DPRINTF(("waitsys(%d, %d, %p, %x)\n", - uap->grp, uap->id, - uap->info, uap->options)); - - q = td->td_proc; - switch (uap->grp) { - case SVR4_P_PID: - pid = uap->id; - break; - - case SVR4_P_PGID: - PROC_LOCK(q); - pid = -q->p_pgid; - PROC_UNLOCK(q); - break; - - case SVR4_P_ALL: - pid = WAIT_ANY; - break; - - default: - return EINVAL; - } - - /* Hand off the easy cases to kern_wait(). */ - if (!(uap->options & (SVR4_WNOWAIT)) && - (uap->options & (SVR4_WEXITED | SVR4_WTRAPPED))) { - int options; - - options = 0; - if (uap->options & SVR4_WSTOPPED) - options |= WUNTRACED; - if (uap->options & SVR4_WCONTINUED) - options |= WCONTINUED; - if (uap->options & SVR4_WNOHANG) - options |= WNOHANG; - - error = kern_wait(td, pid, &status, options, &ru); - if (error) - return (error); - if (uap->options & SVR4_WNOHANG && *retval == 0) - error = svr4_setinfo(*retval, NULL, 0, uap->info); - else - error = svr4_setinfo(*retval, &ru, status, uap->info); - *retval = 0; - return (error); - } - - /* - * Ok, handle the weird cases. Either WNOWAIT is set (meaning we - * just want to see if there is a process to harvest, we don't - * want to actually harvest it), or WEXIT and WTRAPPED are clear - * meaning we want to ignore zombies. Either way, we don't have - * to handle harvesting zombies here. We do have to duplicate the - * other portions of kern_wait() though, especially for WCONTINUED - * and WSTOPPED. - */ -loop: - nfound = 0; - sx_slock(&proctree_lock); - LIST_FOREACH(p, &q->p_children, p_sibling) { - PROC_LOCK(p); - if (pid != WAIT_ANY && - p->p_pid != pid && p->p_pgid != -pid) { - PROC_UNLOCK(p); - DPRINTF(("pid %d pgid %d != %d\n", p->p_pid, - p->p_pgid, pid)); - continue; - } - if (p_canwait(td, p)) { - PROC_UNLOCK(p); - continue; - } - - nfound++; - - PROC_SLOCK(p); - /* - * See if we have a zombie. If so, WNOWAIT should be set, - * as otherwise we should have called kern_wait() up above. - */ - if ((p->p_state == PRS_ZOMBIE) && - ((uap->options & (SVR4_WEXITED|SVR4_WTRAPPED)))) { - PROC_SUNLOCK(p); - KASSERT(uap->options & SVR4_WNOWAIT, - ("WNOWAIT is clear")); - - /* Found a zombie, so cache info in local variables. */ - pid = p->p_pid; - status = KW_EXITCODE(p->p_xexit, p->p_xsig); - ru = p->p_ru; - PROC_STATLOCK(p); - calcru(p, &ru.ru_utime, &ru.ru_stime); - PROC_STATUNLOCK(p); - PROC_UNLOCK(p); - sx_sunlock(&proctree_lock); - - /* Copy the info out to userland. */ - *retval = 0; - DPRINTF(("found %d\n", pid)); - return (svr4_setinfo(pid, &ru, status, uap->info)); - } - - /* - * See if we have a stopped or continued process. - * XXX: This duplicates the same code in kern_wait(). - */ - if ((p->p_flag & P_STOPPED_SIG) && - (p->p_suspcount == p->p_numthreads) && - (p->p_flag & P_WAITED) == 0 && - (p->p_flag & P_TRACED || uap->options & SVR4_WSTOPPED)) { - PROC_SUNLOCK(p); - if (((uap->options & SVR4_WNOWAIT)) == 0) - p->p_flag |= P_WAITED; - sx_sunlock(&proctree_lock); - pid = p->p_pid; - status = W_STOPCODE(p->p_xsig); - ru = p->p_ru; - PROC_STATLOCK(p); - calcru(p, &ru.ru_utime, &ru.ru_stime); - PROC_STATUNLOCK(p); - PROC_UNLOCK(p); - - if (((uap->options & SVR4_WNOWAIT)) == 0) { - PROC_LOCK(q); - sigqueue_take(p->p_ksi); - PROC_UNLOCK(q); - } - - *retval = 0; - DPRINTF(("jobcontrol %d\n", pid)); - return (svr4_setinfo(pid, &ru, status, uap->info)); - } - PROC_SUNLOCK(p); - if (uap->options & SVR4_WCONTINUED && - (p->p_flag & P_CONTINUED)) { - sx_sunlock(&proctree_lock); - if (((uap->options & SVR4_WNOWAIT)) == 0) - p->p_flag &= ~P_CONTINUED; - pid = p->p_pid; - ru = p->p_ru; - status = SIGCONT; - PROC_STATLOCK(p); - calcru(p, &ru.ru_utime, &ru.ru_stime); - PROC_STATUNLOCK(p); - PROC_UNLOCK(p); - - if (((uap->options & SVR4_WNOWAIT)) == 0) { - PROC_LOCK(q); - sigqueue_take(p->p_ksi); - PROC_UNLOCK(q); - } - - *retval = 0; - DPRINTF(("jobcontrol %d\n", pid)); - return (svr4_setinfo(pid, &ru, status, uap->info)); - } - PROC_UNLOCK(p); - } - - if (nfound == 0) { - sx_sunlock(&proctree_lock); - return (ECHILD); - } - - if (uap->options & SVR4_WNOHANG) { - sx_sunlock(&proctree_lock); - *retval = 0; - return (svr4_setinfo(0, NULL, 0, uap->info)); - } - - PROC_LOCK(q); - sx_sunlock(&proctree_lock); - if (q->p_flag & P_STATCHILD) { - q->p_flag &= ~P_STATCHILD; - error = 0; - } else - error = msleep(q, &q->p_mtx, PWAIT | PCATCH, "svr4_wait", 0); - PROC_UNLOCK(q); - if (error) - return error; - goto loop; -} - - -static void -bsd_statfs_to_svr4_statvfs(bfs, sfs) - const struct statfs *bfs; - struct svr4_statvfs *sfs; -{ - sfs->f_bsize = bfs->f_iosize; /* XXX */ - sfs->f_frsize = bfs->f_bsize; - sfs->f_blocks = bfs->f_blocks; - sfs->f_bfree = bfs->f_bfree; - sfs->f_bavail = bfs->f_bavail; - sfs->f_files = bfs->f_files; - sfs->f_ffree = bfs->f_ffree; - sfs->f_favail = bfs->f_ffree; - sfs->f_fsid = bfs->f_fsid.val[0]; - memcpy(sfs->f_basetype, bfs->f_fstypename, sizeof(sfs->f_basetype)); - sfs->f_flag = 0; - if (bfs->f_flags & MNT_RDONLY) - sfs->f_flag |= SVR4_ST_RDONLY; - if (bfs->f_flags & MNT_NOSUID) - sfs->f_flag |= SVR4_ST_NOSUID; - sfs->f_namemax = MAXNAMLEN; - memcpy(sfs->f_fstr, bfs->f_fstypename, sizeof(sfs->f_fstr)); /* XXX */ - memset(sfs->f_filler, 0, sizeof(sfs->f_filler)); -} - - -static void -bsd_statfs_to_svr4_statvfs64(bfs, sfs) - const struct statfs *bfs; - struct svr4_statvfs64 *sfs; -{ - sfs->f_bsize = bfs->f_iosize; /* XXX */ - sfs->f_frsize = bfs->f_bsize; - sfs->f_blocks = bfs->f_blocks; - sfs->f_bfree = bfs->f_bfree; - sfs->f_bavail = bfs->f_bavail; - sfs->f_files = bfs->f_files; - sfs->f_ffree = bfs->f_ffree; - sfs->f_favail = bfs->f_ffree; - sfs->f_fsid = bfs->f_fsid.val[0]; - memcpy(sfs->f_basetype, bfs->f_fstypename, sizeof(sfs->f_basetype)); - sfs->f_flag = 0; - if (bfs->f_flags & MNT_RDONLY) - sfs->f_flag |= SVR4_ST_RDONLY; - if (bfs->f_flags & MNT_NOSUID) - sfs->f_flag |= SVR4_ST_NOSUID; - sfs->f_namemax = MAXNAMLEN; - memcpy(sfs->f_fstr, bfs->f_fstypename, sizeof(sfs->f_fstr)); /* XXX */ - memset(sfs->f_filler, 0, sizeof(sfs->f_filler)); -} - - -int -svr4_sys_statvfs(td, uap) - struct thread *td; - struct svr4_sys_statvfs_args *uap; -{ - struct svr4_statvfs sfs; - struct statfs *bfs; - char *path; - int error; - - CHECKALTEXIST(td, uap->path, &path); - - bfs = malloc(sizeof(struct statfs), M_STATFS, M_WAITOK); - error = kern_statfs(td, path, UIO_SYSSPACE, bfs); - free(path, M_TEMP); - if (error == 0) - bsd_statfs_to_svr4_statvfs(bfs, &sfs); - free(bfs, M_STATFS); - if (error != 0) - return (error); - return copyout(&sfs, uap->fs, sizeof(sfs)); -} - - -int -svr4_sys_fstatvfs(td, uap) - struct thread *td; - struct svr4_sys_fstatvfs_args *uap; -{ - struct svr4_statvfs sfs; - struct statfs *bfs; - int error; - - bfs = malloc(sizeof(struct statfs), M_STATFS, M_WAITOK); - error = kern_fstatfs(td, uap->fd, bfs); - if (error == 0) - bsd_statfs_to_svr4_statvfs(bfs, &sfs); - free(bfs, M_STATFS); - if (error != 0) - return (error); - return copyout(&sfs, uap->fs, sizeof(sfs)); -} - - -int -svr4_sys_statvfs64(td, uap) - struct thread *td; - struct svr4_sys_statvfs64_args *uap; -{ - struct svr4_statvfs64 sfs; - struct statfs *bfs; - char *path; - int error; - - CHECKALTEXIST(td, uap->path, &path); - - bfs = malloc(sizeof(struct statfs), M_STATFS, M_WAITOK); - error = kern_statfs(td, path, UIO_SYSSPACE, bfs); - free(path, M_TEMP); - if (error == 0) - bsd_statfs_to_svr4_statvfs64(bfs, &sfs); - free(bfs, M_STATFS); - if (error != 0) - return (error); - return copyout(&sfs, uap->fs, sizeof(sfs)); -} - - -int -svr4_sys_fstatvfs64(td, uap) - struct thread *td; - struct svr4_sys_fstatvfs64_args *uap; -{ - struct svr4_statvfs64 sfs; - struct statfs *bfs; - int error; - - bfs = malloc(sizeof(struct statfs), M_STATFS, M_WAITOK); - error = kern_fstatfs(td, uap->fd, bfs); - if (error == 0) - bsd_statfs_to_svr4_statvfs64(bfs, &sfs); - free(bfs, M_STATFS); - if (error != 0) - return (error); - return copyout(&sfs, uap->fs, sizeof(sfs)); -} - -int -svr4_sys_alarm(td, uap) - struct thread *td; - struct svr4_sys_alarm_args *uap; -{ - struct itimerval itv, oitv; - int error; - - timevalclear(&itv.it_interval); - itv.it_value.tv_sec = uap->sec; - itv.it_value.tv_usec = 0; - error = kern_setitimer(td, ITIMER_REAL, &itv, &oitv); - if (error) - return (error); - if (oitv.it_value.tv_usec != 0) - oitv.it_value.tv_sec++; - td->td_retval[0] = oitv.it_value.tv_sec; - return (0); -} - -int -svr4_sys_gettimeofday(td, uap) - struct thread *td; - struct svr4_sys_gettimeofday_args *uap; -{ - if (uap->tp) { - struct timeval atv; - - microtime(&atv); - return copyout(&atv, uap->tp, sizeof (atv)); - } - - return 0; -} - -int -svr4_sys_facl(td, uap) - struct thread *td; - struct svr4_sys_facl_args *uap; -{ - int *retval; - - retval = td->td_retval; - *retval = 0; - - switch (uap->cmd) { - case SVR4_SYS_SETACL: - /* We don't support acls on any filesystem */ - return ENOSYS; - - case SVR4_SYS_GETACL: - return copyout(retval, &uap->num, - sizeof(uap->num)); - - case SVR4_SYS_GETACLCNT: - return 0; - - default: - return EINVAL; - } -} - - -int -svr4_sys_acl(td, uap) - struct thread *td; - struct svr4_sys_acl_args *uap; -{ - /* XXX: for now the same */ - return svr4_sys_facl(td, (struct svr4_sys_facl_args *)uap); -} - -int -svr4_sys_auditsys(td, uap) - struct thread *td; - struct svr4_sys_auditsys_args *uap; -{ - /* - * XXX: Big brother is *not* watching. - */ - return 0; -} - -int -svr4_sys_memcntl(td, uap) - struct thread *td; - struct svr4_sys_memcntl_args *uap; -{ - switch (uap->cmd) { - case SVR4_MC_SYNC: - { - struct msync_args msa; - - msa.addr = uap->addr; - msa.len = uap->len; - msa.flags = (int)uap->arg; - - return sys_msync(td, &msa); - } - case SVR4_MC_ADVISE: - { - struct madvise_args maa; - - maa.addr = uap->addr; - maa.len = uap->len; - maa.behav = (int)uap->arg; - - return sys_madvise(td, &maa); - } - case SVR4_MC_LOCK: - case SVR4_MC_UNLOCK: - case SVR4_MC_LOCKAS: - case SVR4_MC_UNLOCKAS: - return EOPNOTSUPP; - default: - return ENOSYS; - } -} - - -int -svr4_sys_nice(td, uap) - struct thread *td; - struct svr4_sys_nice_args *uap; -{ - struct setpriority_args ap; - int error; - - ap.which = PRIO_PROCESS; - ap.who = 0; - ap.prio = uap->prio; - - if ((error = sys_setpriority(td, &ap)) != 0) - return error; - - /* the cast is stupid, but the structures are the same */ - if ((error = sys_getpriority(td, (struct getpriority_args *)&ap)) != 0) - return error; - - return 0; -} - -int -svr4_sys_resolvepath(td, uap) - struct thread *td; - struct svr4_sys_resolvepath_args *uap; -{ - struct nameidata nd; - int error, *retval = td->td_retval; - unsigned int ncopy; - - NDINIT(&nd, LOOKUP, NOFOLLOW | SAVENAME, UIO_USERSPACE, - uap->path, td); - - if ((error = namei(&nd)) != 0) - return (error); - NDFREE(&nd, NDF_NO_FREE_PNBUF); - - ncopy = min(uap->bufsiz, strlen(nd.ni_cnd.cn_pnbuf) + 1); - if ((error = copyout(nd.ni_cnd.cn_pnbuf, uap->buf, ncopy)) != 0) - goto bad; - - *retval = ncopy; -bad: - NDFREE(&nd, NDF_ONLY_PNBUF); - return error; -} diff --git a/sys/compat/svr4/svr4_mman.h b/sys/compat/svr4/svr4_mman.h deleted file mode 100644 index 6dd471a87f0..00000000000 --- a/sys/compat/svr4/svr4_mman.h +++ /dev/null @@ -1,47 +0,0 @@ -/*- - * Copyright (c) 1998 Mark Newton - * Copyright (c) 1997 Todd Vierling - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * $FreeBSD: stable/11/sys/compat/svr4/svr4_mman.h 139743 2005-01-05 22:34:37Z imp $ - */ - -#ifndef _SVR4_MMAN_H_ -#define _SVR4_MMAN_H_ - -/* - * Commands and flags passed to memcntl(). - * Most of them are the same as , but we need the MC_ - * memcntl command definitions. - */ - -#define SVR4_MC_SYNC 1 -#define SVR4_MC_LOCK 2 -#define SVR4_MC_UNLOCK 3 -#define SVR4_MC_ADVISE 4 -#define SVR4_MC_LOCKAS 5 -#define SVR4_MC_UNLOCKAS 6 - -#endif /* !_SVR4_MMAN_H */ diff --git a/sys/compat/svr4/svr4_proto.h b/sys/compat/svr4/svr4_proto.h deleted file mode 100644 index 5b0017579ee..00000000000 --- a/sys/compat/svr4/svr4_proto.h +++ /dev/null @@ -1,608 +0,0 @@ -/* - * System call prototypes. - * - * DO NOT EDIT-- this file is automatically generated. - * $FreeBSD: stable/11/sys/compat/svr4/svr4_proto.h 318164 2017-05-10 23:09:17Z jhb $ - */ - -#ifndef _SVR4_SYSPROTO_H_ -#define _SVR4_SYSPROTO_H_ - -#include -#include -#include -#include -#include -#include -#include - -#include - -struct proc; - -struct thread; - -#define PAD_(t) (sizeof(register_t) <= sizeof(t) ? \ - 0 : sizeof(register_t) - sizeof(t)) - -#if BYTE_ORDER == LITTLE_ENDIAN -#define PADL_(t) 0 -#define PADR_(t) PAD_(t) -#else -#define PADL_(t) PAD_(t) -#define PADR_(t) 0 -#endif - -struct svr4_sys_open_args { - char path_l_[PADL_(char *)]; char * path; char path_r_[PADR_(char *)]; - char flags_l_[PADL_(int)]; int flags; char flags_r_[PADR_(int)]; - char mode_l_[PADL_(int)]; int mode; char mode_r_[PADR_(int)]; -}; -struct svr4_sys_wait_args { - char status_l_[PADL_(int *)]; int * status; char status_r_[PADR_(int *)]; -}; -struct svr4_sys_creat_args { - char path_l_[PADL_(char *)]; char * path; char path_r_[PADR_(char *)]; - char mode_l_[PADL_(int)]; int mode; char mode_r_[PADR_(int)]; -}; -struct svr4_sys_execv_args { - char path_l_[PADL_(char *)]; char * path; char path_r_[PADR_(char *)]; - char argp_l_[PADL_(char **)]; char ** argp; char argp_r_[PADR_(char **)]; -}; -struct svr4_sys_time_args { - char t_l_[PADL_(time_t *)]; time_t * t; char t_r_[PADR_(time_t *)]; -}; -struct svr4_sys_mknod_args { - char path_l_[PADL_(char *)]; char * path; char path_r_[PADR_(char *)]; - char mode_l_[PADL_(int)]; int mode; char mode_r_[PADR_(int)]; - char dev_l_[PADL_(int)]; int dev; char dev_r_[PADR_(int)]; -}; -struct svr4_sys_break_args { - char nsize_l_[PADL_(caddr_t)]; caddr_t nsize; char nsize_r_[PADR_(caddr_t)]; -}; -struct svr4_sys_stat_args { - char path_l_[PADL_(char *)]; char * path; char path_r_[PADR_(char *)]; - char ub_l_[PADL_(struct svr4_stat *)]; struct svr4_stat * ub; char ub_r_[PADR_(struct svr4_stat *)]; -}; -struct svr4_sys_alarm_args { - char sec_l_[PADL_(unsigned)]; unsigned sec; char sec_r_[PADR_(unsigned)]; -}; -struct svr4_sys_fstat_args { - char fd_l_[PADL_(int)]; int fd; char fd_r_[PADR_(int)]; - char sb_l_[PADL_(struct svr4_stat *)]; struct svr4_stat * sb; char sb_r_[PADR_(struct svr4_stat *)]; -}; -struct svr4_sys_pause_args { - register_t dummy; -}; -struct svr4_sys_utime_args { - char path_l_[PADL_(char *)]; char * path; char path_r_[PADR_(char *)]; - char ubuf_l_[PADL_(struct svr4_utimbuf *)]; struct svr4_utimbuf * ubuf; char ubuf_r_[PADR_(struct svr4_utimbuf *)]; -}; -struct svr4_sys_access_args { - char path_l_[PADL_(char *)]; char * path; char path_r_[PADR_(char *)]; - char amode_l_[PADL_(int)]; int amode; char amode_r_[PADR_(int)]; -}; -struct svr4_sys_nice_args { - char prio_l_[PADL_(int)]; int prio; char prio_r_[PADR_(int)]; -}; -struct svr4_sys_kill_args { - char pid_l_[PADL_(int)]; int pid; char pid_r_[PADR_(int)]; - char signum_l_[PADL_(int)]; int signum; char signum_r_[PADR_(int)]; -}; -struct svr4_sys_pgrpsys_args { - char cmd_l_[PADL_(int)]; int cmd; char cmd_r_[PADR_(int)]; - char pid_l_[PADL_(int)]; int pid; char pid_r_[PADR_(int)]; - char pgid_l_[PADL_(int)]; int pgid; char pgid_r_[PADR_(int)]; -}; -struct svr4_pipe_args { - register_t dummy; -}; -struct svr4_sys_times_args { - char tp_l_[PADL_(struct tms *)]; struct tms * tp; char tp_r_[PADR_(struct tms *)]; -}; -struct svr4_sys_signal_args { - char signum_l_[PADL_(int)]; int signum; char signum_r_[PADR_(int)]; - char handler_l_[PADL_(svr4_sig_t)]; svr4_sig_t handler; char handler_r_[PADR_(svr4_sig_t)]; -}; -struct svr4_sys_msgsys_args { - char what_l_[PADL_(int)]; int what; char what_r_[PADR_(int)]; - char a2_l_[PADL_(int)]; int a2; char a2_r_[PADR_(int)]; - char a3_l_[PADL_(int)]; int a3; char a3_r_[PADR_(int)]; - char a4_l_[PADL_(int)]; int a4; char a4_r_[PADR_(int)]; - char a5_l_[PADL_(int)]; int a5; char a5_r_[PADR_(int)]; -}; -struct svr4_sys_sysarch_args { - char op_l_[PADL_(int)]; int op; char op_r_[PADR_(int)]; - char a1_l_[PADL_(void *)]; void * a1; char a1_r_[PADR_(void *)]; -}; -struct svr4_sys_shmsys_args { - char what_l_[PADL_(int)]; int what; char what_r_[PADR_(int)]; - char a2_l_[PADL_(int)]; int a2; char a2_r_[PADR_(int)]; - char a3_l_[PADL_(int)]; int a3; char a3_r_[PADR_(int)]; - char a4_l_[PADL_(int)]; int a4; char a4_r_[PADR_(int)]; - char a5_l_[PADL_(int)]; int a5; char a5_r_[PADR_(int)]; -}; -struct svr4_sys_semsys_args { - char what_l_[PADL_(int)]; int what; char what_r_[PADR_(int)]; - char a2_l_[PADL_(int)]; int a2; char a2_r_[PADR_(int)]; - char a3_l_[PADL_(int)]; int a3; char a3_r_[PADR_(int)]; - char a4_l_[PADL_(int)]; int a4; char a4_r_[PADR_(int)]; - char a5_l_[PADL_(int)]; int a5; char a5_r_[PADR_(int)]; -}; -struct svr4_sys_ioctl_args { - char fd_l_[PADL_(int)]; int fd; char fd_r_[PADR_(int)]; - char com_l_[PADL_(u_long)]; u_long com; char com_r_[PADR_(u_long)]; - char data_l_[PADL_(caddr_t)]; caddr_t data; char data_r_[PADR_(caddr_t)]; -}; -struct svr4_sys_utssys_args { - char a1_l_[PADL_(void *)]; void * a1; char a1_r_[PADR_(void *)]; - char a2_l_[PADL_(void *)]; void * a2; char a2_r_[PADR_(void *)]; - char sel_l_[PADL_(int)]; int sel; char sel_r_[PADR_(int)]; - char a3_l_[PADL_(void *)]; void * a3; char a3_r_[PADR_(void *)]; -}; -struct svr4_sys_execve_args { - char path_l_[PADL_(char *)]; char * path; char path_r_[PADR_(char *)]; - char argp_l_[PADL_(char **)]; char ** argp; char argp_r_[PADR_(char **)]; - char envp_l_[PADL_(char **)]; char ** envp; char envp_r_[PADR_(char **)]; -}; -struct svr4_sys_fcntl_args { - char fd_l_[PADL_(int)]; int fd; char fd_r_[PADR_(int)]; - char cmd_l_[PADL_(int)]; int cmd; char cmd_r_[PADR_(int)]; - char arg_l_[PADL_(char *)]; char * arg; char arg_r_[PADR_(char *)]; -}; -struct svr4_sys_ulimit_args { - char cmd_l_[PADL_(int)]; int cmd; char cmd_r_[PADR_(int)]; - char newlimit_l_[PADL_(long)]; long newlimit; char newlimit_r_[PADR_(long)]; -}; -struct svr4_sys_getdents_args { - char fd_l_[PADL_(int)]; int fd; char fd_r_[PADR_(int)]; - char buf_l_[PADL_(char *)]; char * buf; char buf_r_[PADR_(char *)]; - char nbytes_l_[PADL_(int)]; int nbytes; char nbytes_r_[PADR_(int)]; -}; -struct svr4_sys_getmsg_args { - char fd_l_[PADL_(int)]; int fd; char fd_r_[PADR_(int)]; - char ctl_l_[PADL_(struct svr4_strbuf *)]; struct svr4_strbuf * ctl; char ctl_r_[PADR_(struct svr4_strbuf *)]; - char dat_l_[PADL_(struct svr4_strbuf *)]; struct svr4_strbuf * dat; char dat_r_[PADR_(struct svr4_strbuf *)]; - char flags_l_[PADL_(int *)]; int * flags; char flags_r_[PADR_(int *)]; -}; -struct svr4_sys_putmsg_args { - char fd_l_[PADL_(int)]; int fd; char fd_r_[PADR_(int)]; - char ctl_l_[PADL_(struct svr4_strbuf *)]; struct svr4_strbuf * ctl; char ctl_r_[PADR_(struct svr4_strbuf *)]; - char dat_l_[PADL_(struct svr4_strbuf *)]; struct svr4_strbuf * dat; char dat_r_[PADR_(struct svr4_strbuf *)]; - char flags_l_[PADL_(int)]; int flags; char flags_r_[PADR_(int)]; -}; -struct svr4_sys_poll_args { - char fds_l_[PADL_(struct pollfd *)]; struct pollfd * fds; char fds_r_[PADR_(struct pollfd *)]; - char nfds_l_[PADL_(unsigned int)]; unsigned int nfds; char nfds_r_[PADR_(unsigned int)]; - char timeout_l_[PADL_(int)]; int timeout; char timeout_r_[PADR_(int)]; -}; -struct svr4_sys_lstat_args { - char path_l_[PADL_(char *)]; char * path; char path_r_[PADR_(char *)]; - char ub_l_[PADL_(struct svr4_stat *)]; struct svr4_stat * ub; char ub_r_[PADR_(struct svr4_stat *)]; -}; -struct svr4_sys_sigprocmask_args { - char how_l_[PADL_(int)]; int how; char how_r_[PADR_(int)]; - char set_l_[PADL_(svr4_sigset_t *)]; svr4_sigset_t * set; char set_r_[PADR_(svr4_sigset_t *)]; - char oset_l_[PADL_(svr4_sigset_t *)]; svr4_sigset_t * oset; char oset_r_[PADR_(svr4_sigset_t *)]; -}; -struct svr4_sys_sigsuspend_args { - char ss_l_[PADL_(svr4_sigset_t *)]; svr4_sigset_t * ss; char ss_r_[PADR_(svr4_sigset_t *)]; -}; -struct svr4_sys_sigaltstack_args { - char nss_l_[PADL_(struct svr4_sigaltstack *)]; struct svr4_sigaltstack * nss; char nss_r_[PADR_(struct svr4_sigaltstack *)]; - char oss_l_[PADL_(struct svr4_sigaltstack *)]; struct svr4_sigaltstack * oss; char oss_r_[PADR_(struct svr4_sigaltstack *)]; -}; -struct svr4_sys_sigaction_args { - char signum_l_[PADL_(int)]; int signum; char signum_r_[PADR_(int)]; - char nsa_l_[PADL_(struct svr4_sigaction *)]; struct svr4_sigaction * nsa; char nsa_r_[PADR_(struct svr4_sigaction *)]; - char osa_l_[PADL_(struct svr4_sigaction *)]; struct svr4_sigaction * osa; char osa_r_[PADR_(struct svr4_sigaction *)]; -}; -struct svr4_sys_sigpending_args { - char what_l_[PADL_(int)]; int what; char what_r_[PADR_(int)]; - char mask_l_[PADL_(svr4_sigset_t *)]; svr4_sigset_t * mask; char mask_r_[PADR_(svr4_sigset_t *)]; -}; -struct svr4_sys_context_args { - char func_l_[PADL_(int)]; int func; char func_r_[PADR_(int)]; - char uc_l_[PADL_(struct svr4_ucontext *)]; struct svr4_ucontext * uc; char uc_r_[PADR_(struct svr4_ucontext *)]; -}; -struct svr4_sys_statvfs_args { - char path_l_[PADL_(char *)]; char * path; char path_r_[PADR_(char *)]; - char fs_l_[PADL_(struct svr4_statvfs *)]; struct svr4_statvfs * fs; char fs_r_[PADR_(struct svr4_statvfs *)]; -}; -struct svr4_sys_fstatvfs_args { - char fd_l_[PADL_(int)]; int fd; char fd_r_[PADR_(int)]; - char fs_l_[PADL_(struct svr4_statvfs *)]; struct svr4_statvfs * fs; char fs_r_[PADR_(struct svr4_statvfs *)]; -}; -struct svr4_sys_waitsys_args { - char grp_l_[PADL_(int)]; int grp; char grp_r_[PADR_(int)]; - char id_l_[PADL_(int)]; int id; char id_r_[PADR_(int)]; - char info_l_[PADL_(union svr4_siginfo *)]; union svr4_siginfo * info; char info_r_[PADR_(union svr4_siginfo *)]; - char options_l_[PADL_(int)]; int options; char options_r_[PADR_(int)]; -}; -struct svr4_sys_hrtsys_args { - char cmd_l_[PADL_(int)]; int cmd; char cmd_r_[PADR_(int)]; - char fun_l_[PADL_(int)]; int fun; char fun_r_[PADR_(int)]; - char sub_l_[PADL_(int)]; int sub; char sub_r_[PADR_(int)]; - char rv1_l_[PADL_(void *)]; void * rv1; char rv1_r_[PADR_(void *)]; - char rv2_l_[PADL_(void *)]; void * rv2; char rv2_r_[PADR_(void *)]; -}; -struct svr4_sys_pathconf_args { - char path_l_[PADL_(char *)]; char * path; char path_r_[PADR_(char *)]; - char name_l_[PADL_(int)]; int name; char name_r_[PADR_(int)]; -}; -struct svr4_sys_mmap_args { - char addr_l_[PADL_(caddr_t)]; caddr_t addr; char addr_r_[PADR_(caddr_t)]; - char len_l_[PADL_(svr4_size_t)]; svr4_size_t len; char len_r_[PADR_(svr4_size_t)]; - char prot_l_[PADL_(int)]; int prot; char prot_r_[PADR_(int)]; - char flags_l_[PADL_(int)]; int flags; char flags_r_[PADR_(int)]; - char fd_l_[PADL_(int)]; int fd; char fd_r_[PADR_(int)]; - char pos_l_[PADL_(svr4_off_t)]; svr4_off_t pos; char pos_r_[PADR_(svr4_off_t)]; -}; -struct svr4_sys_fpathconf_args { - char fd_l_[PADL_(int)]; int fd; char fd_r_[PADR_(int)]; - char name_l_[PADL_(int)]; int name; char name_r_[PADR_(int)]; -}; -struct svr4_sys_xstat_args { - char two_l_[PADL_(int)]; int two; char two_r_[PADR_(int)]; - char path_l_[PADL_(char *)]; char * path; char path_r_[PADR_(char *)]; - char ub_l_[PADL_(struct svr4_xstat *)]; struct svr4_xstat * ub; char ub_r_[PADR_(struct svr4_xstat *)]; -}; -struct svr4_sys_lxstat_args { - char two_l_[PADL_(int)]; int two; char two_r_[PADR_(int)]; - char path_l_[PADL_(char *)]; char * path; char path_r_[PADR_(char *)]; - char ub_l_[PADL_(struct svr4_xstat *)]; struct svr4_xstat * ub; char ub_r_[PADR_(struct svr4_xstat *)]; -}; -struct svr4_sys_fxstat_args { - char two_l_[PADL_(int)]; int two; char two_r_[PADR_(int)]; - char fd_l_[PADL_(int)]; int fd; char fd_r_[PADR_(int)]; - char sb_l_[PADL_(struct svr4_xstat *)]; struct svr4_xstat * sb; char sb_r_[PADR_(struct svr4_xstat *)]; -}; -struct svr4_sys_xmknod_args { - char two_l_[PADL_(int)]; int two; char two_r_[PADR_(int)]; - char path_l_[PADL_(char *)]; char * path; char path_r_[PADR_(char *)]; - char mode_l_[PADL_(svr4_mode_t)]; svr4_mode_t mode; char mode_r_[PADR_(svr4_mode_t)]; - char dev_l_[PADL_(svr4_dev_t)]; svr4_dev_t dev; char dev_r_[PADR_(svr4_dev_t)]; -}; -struct svr4_sys_setrlimit_args { - char which_l_[PADL_(int)]; int which; char which_r_[PADR_(int)]; - char rlp_l_[PADL_(const struct svr4_rlimit *)]; const struct svr4_rlimit * rlp; char rlp_r_[PADR_(const struct svr4_rlimit *)]; -}; -struct svr4_sys_getrlimit_args { - char which_l_[PADL_(int)]; int which; char which_r_[PADR_(int)]; - char rlp_l_[PADL_(struct svr4_rlimit *)]; struct svr4_rlimit * rlp; char rlp_r_[PADR_(struct svr4_rlimit *)]; -}; -struct svr4_sys_memcntl_args { - char addr_l_[PADL_(void *)]; void * addr; char addr_r_[PADR_(void *)]; - char len_l_[PADL_(svr4_size_t)]; svr4_size_t len; char len_r_[PADR_(svr4_size_t)]; - char cmd_l_[PADL_(int)]; int cmd; char cmd_r_[PADR_(int)]; - char arg_l_[PADL_(void *)]; void * arg; char arg_r_[PADR_(void *)]; - char attr_l_[PADL_(int)]; int attr; char attr_r_[PADR_(int)]; - char mask_l_[PADL_(int)]; int mask; char mask_r_[PADR_(int)]; -}; -struct svr4_sys_uname_args { - char name_l_[PADL_(struct svr4_utsname *)]; struct svr4_utsname * name; char name_r_[PADR_(struct svr4_utsname *)]; - char dummy_l_[PADL_(int)]; int dummy; char dummy_r_[PADR_(int)]; -}; -struct svr4_sys_sysconfig_args { - char name_l_[PADL_(int)]; int name; char name_r_[PADR_(int)]; -}; -struct svr4_sys_systeminfo_args { - char what_l_[PADL_(int)]; int what; char what_r_[PADR_(int)]; - char buf_l_[PADL_(char *)]; char * buf; char buf_r_[PADR_(char *)]; - char len_l_[PADL_(long)]; long len; char len_r_[PADR_(long)]; -}; -struct svr4_sys_fchroot_args { - char fd_l_[PADL_(int)]; int fd; char fd_r_[PADR_(int)]; -}; -struct svr4_sys_utimes_args { - char path_l_[PADL_(char *)]; char * path; char path_r_[PADR_(char *)]; - char tptr_l_[PADL_(struct timeval *)]; struct timeval * tptr; char tptr_r_[PADR_(struct timeval *)]; -}; -struct svr4_sys_vhangup_args { - register_t dummy; -}; -struct svr4_sys_gettimeofday_args { - char tp_l_[PADL_(struct timeval *)]; struct timeval * tp; char tp_r_[PADR_(struct timeval *)]; -}; -struct svr4_sys_llseek_args { - char fd_l_[PADL_(int)]; int fd; char fd_r_[PADR_(int)]; - char offset1_l_[PADL_(long)]; long offset1; char offset1_r_[PADR_(long)]; - char offset2_l_[PADL_(long)]; long offset2; char offset2_r_[PADR_(long)]; - char whence_l_[PADL_(int)]; int whence; char whence_r_[PADR_(int)]; -}; -struct svr4_sys_acl_args { - char path_l_[PADL_(char *)]; char * path; char path_r_[PADR_(char *)]; - char cmd_l_[PADL_(int)]; int cmd; char cmd_r_[PADR_(int)]; - char num_l_[PADL_(int)]; int num; char num_r_[PADR_(int)]; - char buf_l_[PADL_(struct svr4_aclent *)]; struct svr4_aclent * buf; char buf_r_[PADR_(struct svr4_aclent *)]; -}; -struct svr4_sys_auditsys_args { - char code_l_[PADL_(int)]; int code; char code_r_[PADR_(int)]; - char a1_l_[PADL_(int)]; int a1; char a1_r_[PADR_(int)]; - char a2_l_[PADL_(int)]; int a2; char a2_r_[PADR_(int)]; - char a3_l_[PADL_(int)]; int a3; char a3_r_[PADR_(int)]; - char a4_l_[PADL_(int)]; int a4; char a4_r_[PADR_(int)]; - char a5_l_[PADL_(int)]; int a5; char a5_r_[PADR_(int)]; -}; -struct svr4_sys_facl_args { - char fd_l_[PADL_(int)]; int fd; char fd_r_[PADR_(int)]; - char cmd_l_[PADL_(int)]; int cmd; char cmd_r_[PADR_(int)]; - char num_l_[PADL_(int)]; int num; char num_r_[PADR_(int)]; - char buf_l_[PADL_(struct svr4_aclent *)]; struct svr4_aclent * buf; char buf_r_[PADR_(struct svr4_aclent *)]; -}; -struct svr4_sys_resolvepath_args { - char path_l_[PADL_(const char *)]; const char * path; char path_r_[PADR_(const char *)]; - char buf_l_[PADL_(char *)]; char * buf; char buf_r_[PADR_(char *)]; - char bufsiz_l_[PADL_(size_t)]; size_t bufsiz; char bufsiz_r_[PADR_(size_t)]; -}; -struct svr4_sys_getdents64_args { - char fd_l_[PADL_(int)]; int fd; char fd_r_[PADR_(int)]; - char dp_l_[PADL_(struct svr4_dirent64 *)]; struct svr4_dirent64 * dp; char dp_r_[PADR_(struct svr4_dirent64 *)]; - char nbytes_l_[PADL_(int)]; int nbytes; char nbytes_r_[PADR_(int)]; -}; -struct svr4_sys_mmap64_args { - char addr_l_[PADL_(void *)]; void * addr; char addr_r_[PADR_(void *)]; - char len_l_[PADL_(svr4_size_t)]; svr4_size_t len; char len_r_[PADR_(svr4_size_t)]; - char prot_l_[PADL_(int)]; int prot; char prot_r_[PADR_(int)]; - char flags_l_[PADL_(int)]; int flags; char flags_r_[PADR_(int)]; - char fd_l_[PADL_(int)]; int fd; char fd_r_[PADR_(int)]; - char pos_l_[PADL_(svr4_off64_t)]; svr4_off64_t pos; char pos_r_[PADR_(svr4_off64_t)]; -}; -struct svr4_sys_stat64_args { - char path_l_[PADL_(char *)]; char * path; char path_r_[PADR_(char *)]; - char sb_l_[PADL_(struct svr4_stat64 *)]; struct svr4_stat64 * sb; char sb_r_[PADR_(struct svr4_stat64 *)]; -}; -struct svr4_sys_lstat64_args { - char path_l_[PADL_(char *)]; char * path; char path_r_[PADR_(char *)]; - char sb_l_[PADL_(struct svr4_stat64 *)]; struct svr4_stat64 * sb; char sb_r_[PADR_(struct svr4_stat64 *)]; -}; -struct svr4_sys_fstat64_args { - char fd_l_[PADL_(int)]; int fd; char fd_r_[PADR_(int)]; - char sb_l_[PADL_(struct svr4_stat64 *)]; struct svr4_stat64 * sb; char sb_r_[PADR_(struct svr4_stat64 *)]; -}; -struct svr4_sys_statvfs64_args { - char path_l_[PADL_(char *)]; char * path; char path_r_[PADR_(char *)]; - char fs_l_[PADL_(struct svr4_statvfs64 *)]; struct svr4_statvfs64 * fs; char fs_r_[PADR_(struct svr4_statvfs64 *)]; -}; -struct svr4_sys_fstatvfs64_args { - char fd_l_[PADL_(int)]; int fd; char fd_r_[PADR_(int)]; - char fs_l_[PADL_(struct svr4_statvfs64 *)]; struct svr4_statvfs64 * fs; char fs_r_[PADR_(struct svr4_statvfs64 *)]; -}; -struct svr4_sys_setrlimit64_args { - char which_l_[PADL_(int)]; int which; char which_r_[PADR_(int)]; - char rlp_l_[PADL_(const struct svr4_rlimit64 *)]; const struct svr4_rlimit64 * rlp; char rlp_r_[PADR_(const struct svr4_rlimit64 *)]; -}; -struct svr4_sys_getrlimit64_args { - char which_l_[PADL_(int)]; int which; char which_r_[PADR_(int)]; - char rlp_l_[PADL_(struct svr4_rlimit64 *)]; struct svr4_rlimit64 * rlp; char rlp_r_[PADR_(struct svr4_rlimit64 *)]; -}; -struct svr4_sys_creat64_args { - char path_l_[PADL_(char *)]; char * path; char path_r_[PADR_(char *)]; - char mode_l_[PADL_(int)]; int mode; char mode_r_[PADR_(int)]; -}; -struct svr4_sys_open64_args { - char path_l_[PADL_(char *)]; char * path; char path_r_[PADR_(char *)]; - char flags_l_[PADL_(int)]; int flags; char flags_r_[PADR_(int)]; - char mode_l_[PADL_(int)]; int mode; char mode_r_[PADR_(int)]; -}; -struct svr4_sys_socket_args { - char domain_l_[PADL_(int)]; int domain; char domain_r_[PADR_(int)]; - char type_l_[PADL_(int)]; int type; char type_r_[PADR_(int)]; - char protocol_l_[PADL_(int)]; int protocol; char protocol_r_[PADR_(int)]; -}; -struct svr4_sys_recv_args { - char s_l_[PADL_(int)]; int s; char s_r_[PADR_(int)]; - char buf_l_[PADL_(caddr_t)]; caddr_t buf; char buf_r_[PADR_(caddr_t)]; - char len_l_[PADL_(int)]; int len; char len_r_[PADR_(int)]; - char flags_l_[PADL_(int)]; int flags; char flags_r_[PADR_(int)]; -}; -struct svr4_sys_send_args { - char s_l_[PADL_(int)]; int s; char s_r_[PADR_(int)]; - char buf_l_[PADL_(caddr_t)]; caddr_t buf; char buf_r_[PADR_(caddr_t)]; - char len_l_[PADL_(int)]; int len; char len_r_[PADR_(int)]; - char flags_l_[PADL_(int)]; int flags; char flags_r_[PADR_(int)]; -}; -struct svr4_sys_sendto_args { - char s_l_[PADL_(int)]; int s; char s_r_[PADR_(int)]; - char buf_l_[PADL_(void *)]; void * buf; char buf_r_[PADR_(void *)]; - char len_l_[PADL_(size_t)]; size_t len; char len_r_[PADR_(size_t)]; - char flags_l_[PADL_(int)]; int flags; char flags_r_[PADR_(int)]; - char to_l_[PADL_(struct sockaddr *)]; struct sockaddr * to; char to_r_[PADR_(struct sockaddr *)]; - char tolen_l_[PADL_(int)]; int tolen; char tolen_r_[PADR_(int)]; -}; -int svr4_sys_open(struct thread *, struct svr4_sys_open_args *); -int svr4_sys_wait(struct thread *, struct svr4_sys_wait_args *); -int svr4_sys_creat(struct thread *, struct svr4_sys_creat_args *); -int svr4_sys_execv(struct thread *, struct svr4_sys_execv_args *); -int svr4_sys_time(struct thread *, struct svr4_sys_time_args *); -int svr4_sys_mknod(struct thread *, struct svr4_sys_mknod_args *); -int svr4_sys_break(struct thread *, struct svr4_sys_break_args *); -int svr4_sys_stat(struct thread *, struct svr4_sys_stat_args *); -int svr4_sys_alarm(struct thread *, struct svr4_sys_alarm_args *); -int svr4_sys_fstat(struct thread *, struct svr4_sys_fstat_args *); -int svr4_sys_pause(struct thread *, struct svr4_sys_pause_args *); -int svr4_sys_utime(struct thread *, struct svr4_sys_utime_args *); -int svr4_sys_access(struct thread *, struct svr4_sys_access_args *); -int svr4_sys_nice(struct thread *, struct svr4_sys_nice_args *); -int svr4_sys_kill(struct thread *, struct svr4_sys_kill_args *); -int svr4_sys_pgrpsys(struct thread *, struct svr4_sys_pgrpsys_args *); -int svr4_pipe(struct thread *, struct svr4_pipe_args *); -int svr4_sys_times(struct thread *, struct svr4_sys_times_args *); -int svr4_sys_signal(struct thread *, struct svr4_sys_signal_args *); -int svr4_sys_msgsys(struct thread *, struct svr4_sys_msgsys_args *); -int svr4_sys_sysarch(struct thread *, struct svr4_sys_sysarch_args *); -int svr4_sys_shmsys(struct thread *, struct svr4_sys_shmsys_args *); -int svr4_sys_semsys(struct thread *, struct svr4_sys_semsys_args *); -int svr4_sys_ioctl(struct thread *, struct svr4_sys_ioctl_args *); -int svr4_sys_utssys(struct thread *, struct svr4_sys_utssys_args *); -int svr4_sys_execve(struct thread *, struct svr4_sys_execve_args *); -int svr4_sys_fcntl(struct thread *, struct svr4_sys_fcntl_args *); -int svr4_sys_ulimit(struct thread *, struct svr4_sys_ulimit_args *); -int svr4_sys_getdents(struct thread *, struct svr4_sys_getdents_args *); -int svr4_sys_getmsg(struct thread *, struct svr4_sys_getmsg_args *); -int svr4_sys_putmsg(struct thread *, struct svr4_sys_putmsg_args *); -int svr4_sys_poll(struct thread *, struct svr4_sys_poll_args *); -int svr4_sys_lstat(struct thread *, struct svr4_sys_lstat_args *); -int svr4_sys_sigprocmask(struct thread *, struct svr4_sys_sigprocmask_args *); -int svr4_sys_sigsuspend(struct thread *, struct svr4_sys_sigsuspend_args *); -int svr4_sys_sigaltstack(struct thread *, struct svr4_sys_sigaltstack_args *); -int svr4_sys_sigaction(struct thread *, struct svr4_sys_sigaction_args *); -int svr4_sys_sigpending(struct thread *, struct svr4_sys_sigpending_args *); -int svr4_sys_context(struct thread *, struct svr4_sys_context_args *); -int svr4_sys_statvfs(struct thread *, struct svr4_sys_statvfs_args *); -int svr4_sys_fstatvfs(struct thread *, struct svr4_sys_fstatvfs_args *); -int svr4_sys_waitsys(struct thread *, struct svr4_sys_waitsys_args *); -int svr4_sys_hrtsys(struct thread *, struct svr4_sys_hrtsys_args *); -int svr4_sys_pathconf(struct thread *, struct svr4_sys_pathconf_args *); -int svr4_sys_mmap(struct thread *, struct svr4_sys_mmap_args *); -int svr4_sys_fpathconf(struct thread *, struct svr4_sys_fpathconf_args *); -int svr4_sys_xstat(struct thread *, struct svr4_sys_xstat_args *); -int svr4_sys_lxstat(struct thread *, struct svr4_sys_lxstat_args *); -int svr4_sys_fxstat(struct thread *, struct svr4_sys_fxstat_args *); -int svr4_sys_xmknod(struct thread *, struct svr4_sys_xmknod_args *); -int svr4_sys_setrlimit(struct thread *, struct svr4_sys_setrlimit_args *); -int svr4_sys_getrlimit(struct thread *, struct svr4_sys_getrlimit_args *); -int svr4_sys_memcntl(struct thread *, struct svr4_sys_memcntl_args *); -int svr4_sys_uname(struct thread *, struct svr4_sys_uname_args *); -int svr4_sys_sysconfig(struct thread *, struct svr4_sys_sysconfig_args *); -int svr4_sys_systeminfo(struct thread *, struct svr4_sys_systeminfo_args *); -int svr4_sys_fchroot(struct thread *, struct svr4_sys_fchroot_args *); -int svr4_sys_utimes(struct thread *, struct svr4_sys_utimes_args *); -int svr4_sys_vhangup(struct thread *, struct svr4_sys_vhangup_args *); -int svr4_sys_gettimeofday(struct thread *, struct svr4_sys_gettimeofday_args *); -int svr4_sys_llseek(struct thread *, struct svr4_sys_llseek_args *); -int svr4_sys_acl(struct thread *, struct svr4_sys_acl_args *); -int svr4_sys_auditsys(struct thread *, struct svr4_sys_auditsys_args *); -int svr4_sys_facl(struct thread *, struct svr4_sys_facl_args *); -int svr4_sys_resolvepath(struct thread *, struct svr4_sys_resolvepath_args *); -int svr4_sys_getdents64(struct thread *, struct svr4_sys_getdents64_args *); -int svr4_sys_mmap64(struct thread *, struct svr4_sys_mmap64_args *); -int svr4_sys_stat64(struct thread *, struct svr4_sys_stat64_args *); -int svr4_sys_lstat64(struct thread *, struct svr4_sys_lstat64_args *); -int svr4_sys_fstat64(struct thread *, struct svr4_sys_fstat64_args *); -int svr4_sys_statvfs64(struct thread *, struct svr4_sys_statvfs64_args *); -int svr4_sys_fstatvfs64(struct thread *, struct svr4_sys_fstatvfs64_args *); -int svr4_sys_setrlimit64(struct thread *, struct svr4_sys_setrlimit64_args *); -int svr4_sys_getrlimit64(struct thread *, struct svr4_sys_getrlimit64_args *); -int svr4_sys_creat64(struct thread *, struct svr4_sys_creat64_args *); -int svr4_sys_open64(struct thread *, struct svr4_sys_open64_args *); -int svr4_sys_socket(struct thread *, struct svr4_sys_socket_args *); -int svr4_sys_recv(struct thread *, struct svr4_sys_recv_args *); -int svr4_sys_send(struct thread *, struct svr4_sys_send_args *); -int svr4_sys_sendto(struct thread *, struct svr4_sys_sendto_args *); - -#ifdef COMPAT_43 - - -#endif /* COMPAT_43 */ - - -#ifdef COMPAT_FREEBSD4 - - -#endif /* COMPAT_FREEBSD4 */ - - -#ifdef COMPAT_FREEBSD6 - - -#endif /* COMPAT_FREEBSD6 */ - - -#ifdef COMPAT_FREEBSD7 - - -#endif /* COMPAT_FREEBSD7 */ - - -#ifdef COMPAT_FREEBSD10 - - -#endif /* COMPAT_FREEBSD10 */ - -#define SVR4_SYS_AUE_svr4_sys_open AUE_NULL -#define SVR4_SYS_AUE_svr4_sys_wait AUE_NULL -#define SVR4_SYS_AUE_svr4_sys_creat AUE_NULL -#define SVR4_SYS_AUE_svr4_sys_execv AUE_NULL -#define SVR4_SYS_AUE_svr4_sys_time AUE_NULL -#define SVR4_SYS_AUE_svr4_sys_mknod AUE_NULL -#define SVR4_SYS_AUE_svr4_sys_break AUE_NULL -#define SVR4_SYS_AUE_svr4_sys_stat AUE_NULL -#define SVR4_SYS_AUE_svr4_sys_alarm AUE_NULL -#define SVR4_SYS_AUE_svr4_sys_fstat AUE_NULL -#define SVR4_SYS_AUE_svr4_sys_pause AUE_NULL -#define SVR4_SYS_AUE_svr4_sys_utime AUE_NULL -#define SVR4_SYS_AUE_svr4_sys_access AUE_NULL -#define SVR4_SYS_AUE_svr4_sys_nice AUE_NULL -#define SVR4_SYS_AUE_svr4_sys_kill AUE_NULL -#define SVR4_SYS_AUE_svr4_sys_pgrpsys AUE_NULL -#define SVR4_SYS_AUE_svr4_pipe AUE_NULL -#define SVR4_SYS_AUE_svr4_sys_times AUE_NULL -#define SVR4_SYS_AUE_svr4_sys_signal AUE_NULL -#define SVR4_SYS_AUE_svr4_sys_msgsys AUE_NULL -#define SVR4_SYS_AUE_svr4_sys_sysarch AUE_NULL -#define SVR4_SYS_AUE_svr4_sys_shmsys AUE_NULL -#define SVR4_SYS_AUE_svr4_sys_semsys AUE_NULL -#define SVR4_SYS_AUE_svr4_sys_ioctl AUE_NULL -#define SVR4_SYS_AUE_svr4_sys_utssys AUE_NULL -#define SVR4_SYS_AUE_svr4_sys_execve AUE_NULL -#define SVR4_SYS_AUE_svr4_sys_fcntl AUE_NULL -#define SVR4_SYS_AUE_svr4_sys_ulimit AUE_NULL -#define SVR4_SYS_AUE_svr4_sys_getdents AUE_NULL -#define SVR4_SYS_AUE_svr4_sys_getmsg AUE_NULL -#define SVR4_SYS_AUE_svr4_sys_putmsg AUE_NULL -#define SVR4_SYS_AUE_svr4_sys_poll AUE_NULL -#define SVR4_SYS_AUE_svr4_sys_lstat AUE_NULL -#define SVR4_SYS_AUE_svr4_sys_sigprocmask AUE_NULL -#define SVR4_SYS_AUE_svr4_sys_sigsuspend AUE_NULL -#define SVR4_SYS_AUE_svr4_sys_sigaltstack AUE_NULL -#define SVR4_SYS_AUE_svr4_sys_sigaction AUE_NULL -#define SVR4_SYS_AUE_svr4_sys_sigpending AUE_NULL -#define SVR4_SYS_AUE_svr4_sys_context AUE_NULL -#define SVR4_SYS_AUE_svr4_sys_statvfs AUE_NULL -#define SVR4_SYS_AUE_svr4_sys_fstatvfs AUE_NULL -#define SVR4_SYS_AUE_svr4_sys_waitsys AUE_NULL -#define SVR4_SYS_AUE_svr4_sys_hrtsys AUE_NULL -#define SVR4_SYS_AUE_svr4_sys_pathconf AUE_NULL -#define SVR4_SYS_AUE_svr4_sys_mmap AUE_NULL -#define SVR4_SYS_AUE_svr4_sys_fpathconf AUE_NULL -#define SVR4_SYS_AUE_svr4_sys_xstat AUE_NULL -#define SVR4_SYS_AUE_svr4_sys_lxstat AUE_NULL -#define SVR4_SYS_AUE_svr4_sys_fxstat AUE_NULL -#define SVR4_SYS_AUE_svr4_sys_xmknod AUE_NULL -#define SVR4_SYS_AUE_svr4_sys_setrlimit AUE_NULL -#define SVR4_SYS_AUE_svr4_sys_getrlimit AUE_NULL -#define SVR4_SYS_AUE_svr4_sys_memcntl AUE_NULL -#define SVR4_SYS_AUE_svr4_sys_uname AUE_NULL -#define SVR4_SYS_AUE_svr4_sys_sysconfig AUE_NULL -#define SVR4_SYS_AUE_svr4_sys_systeminfo AUE_NULL -#define SVR4_SYS_AUE_svr4_sys_fchroot AUE_NULL -#define SVR4_SYS_AUE_svr4_sys_utimes AUE_NULL -#define SVR4_SYS_AUE_svr4_sys_vhangup AUE_NULL -#define SVR4_SYS_AUE_svr4_sys_gettimeofday AUE_NULL -#define SVR4_SYS_AUE_svr4_sys_llseek AUE_NULL -#define SVR4_SYS_AUE_svr4_sys_acl AUE_NULL -#define SVR4_SYS_AUE_svr4_sys_auditsys AUE_NULL -#define SVR4_SYS_AUE_svr4_sys_facl AUE_NULL -#define SVR4_SYS_AUE_svr4_sys_resolvepath AUE_NULL -#define SVR4_SYS_AUE_svr4_sys_getdents64 AUE_NULL -#define SVR4_SYS_AUE_svr4_sys_mmap64 AUE_NULL -#define SVR4_SYS_AUE_svr4_sys_stat64 AUE_NULL -#define SVR4_SYS_AUE_svr4_sys_lstat64 AUE_NULL -#define SVR4_SYS_AUE_svr4_sys_fstat64 AUE_NULL -#define SVR4_SYS_AUE_svr4_sys_statvfs64 AUE_NULL -#define SVR4_SYS_AUE_svr4_sys_fstatvfs64 AUE_NULL -#define SVR4_SYS_AUE_svr4_sys_setrlimit64 AUE_NULL -#define SVR4_SYS_AUE_svr4_sys_getrlimit64 AUE_NULL -#define SVR4_SYS_AUE_svr4_sys_creat64 AUE_NULL -#define SVR4_SYS_AUE_svr4_sys_open64 AUE_NULL -#define SVR4_SYS_AUE_svr4_sys_socket AUE_NULL -#define SVR4_SYS_AUE_svr4_sys_recv AUE_NULL -#define SVR4_SYS_AUE_svr4_sys_send AUE_NULL -#define SVR4_SYS_AUE_svr4_sys_sendto AUE_NULL - -#undef PAD_ -#undef PADL_ -#undef PADR_ - -#endif /* !_SVR4_SYSPROTO_H_ */ diff --git a/sys/compat/svr4/svr4_resource.c b/sys/compat/svr4/svr4_resource.c deleted file mode 100644 index e32b7c21366..00000000000 --- a/sys/compat/svr4/svr4_resource.c +++ /dev/null @@ -1,305 +0,0 @@ -/*- - * Copyright (c) 1998 The NetBSD Foundation, Inc. - * All rights reserved. - * - * This code is derived from software contributed to The NetBSD Foundation - * by Christos Zoulas. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS - * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ -/*- - * Portions of this software have been derived from software contributed - * to the FreeBSD Project by Mark Newton. - * - * Copyright (c) 1999 Mark Newton - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Derived from: $NetBSD: svr4_resource.c,v 1.3 1998/12/13 18:00:52 christos Exp $ - */ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -static __inline int svr4_to_native_rl(int); - -static __inline int -svr4_to_native_rl(rl) - int rl; -{ - switch (rl) { - case SVR4_RLIMIT_CPU: - return RLIMIT_CPU; - case SVR4_RLIMIT_FSIZE: - return RLIMIT_FSIZE; - case SVR4_RLIMIT_DATA: - return RLIMIT_DATA; - case SVR4_RLIMIT_STACK: - return RLIMIT_STACK; - case SVR4_RLIMIT_CORE: - return RLIMIT_CORE; - case SVR4_RLIMIT_NOFILE: - return RLIMIT_NOFILE; - case SVR4_RLIMIT_VMEM: - return RLIMIT_VMEM; - default: - return -1; - } -} - -/* - * Check if the resource limit fits within the BSD range and it is not - * one of the magic SVR4 limit values - */ -#define OKLIMIT(l) (((int32_t)(l)) >= 0 && ((int32_t)(l)) < 0x7fffffff && \ - ((svr4_rlim_t)(l)) != SVR4_RLIM_INFINITY && \ - ((svr4_rlim_t)(l)) != SVR4_RLIM_SAVED_CUR && \ - ((svr4_rlim_t)(l)) != SVR4_RLIM_SAVED_MAX) - -#define OKLIMIT64(l) (((rlim_t)(l)) >= 0 && ((rlim_t)(l)) < RLIM_INFINITY && \ - ((svr4_rlim64_t)(l)) != SVR4_RLIM64_INFINITY && \ - ((svr4_rlim64_t)(l)) != SVR4_RLIM64_SAVED_CUR && \ - ((svr4_rlim64_t)(l)) != SVR4_RLIM64_SAVED_MAX) - -int -svr4_sys_getrlimit(td, uap) - struct thread *td; - struct svr4_sys_getrlimit_args *uap; -{ - int rl = svr4_to_native_rl(uap->which); - struct rlimit blim; - struct svr4_rlimit slim; - - if (rl == -1) - return EINVAL; - - lim_rlimit(td, rl, &blim); - - /* - * Our infinity, is their maxfiles. - */ - if (rl == RLIMIT_NOFILE && blim.rlim_max == RLIM_INFINITY) - blim.rlim_max = maxfiles; - - /* - * If the limit can be be represented, it is returned. - * Otherwise, if rlim_cur == rlim_max, return RLIM_SAVED_MAX - * else return RLIM_SAVED_CUR - */ - if (blim.rlim_max == RLIM_INFINITY) - slim.rlim_max = SVR4_RLIM_INFINITY; - else if (OKLIMIT(blim.rlim_max)) - slim.rlim_max = (svr4_rlim_t) blim.rlim_max; - else - slim.rlim_max = SVR4_RLIM_SAVED_MAX; - - if (blim.rlim_cur == RLIM_INFINITY) - slim.rlim_cur = SVR4_RLIM_INFINITY; - else if (OKLIMIT(blim.rlim_cur)) - slim.rlim_cur = (svr4_rlim_t) blim.rlim_cur; - else if (blim.rlim_max == blim.rlim_cur) - slim.rlim_cur = SVR4_RLIM_SAVED_MAX; - else - slim.rlim_cur = SVR4_RLIM_SAVED_CUR; - - return copyout(&slim, uap->rlp, sizeof(*uap->rlp)); -} - - -int -svr4_sys_setrlimit(td, uap) - struct thread *td; - struct svr4_sys_setrlimit_args *uap; -{ - int rl = svr4_to_native_rl(uap->which); - struct rlimit blim, curlim; - struct svr4_rlimit slim; - int error; - - if (rl == -1) - return EINVAL; - - if ((error = copyin(uap->rlp, &slim, sizeof(slim))) != 0) - return error; - - lim_rlimit(td, rl, &curlim); - - /* - * if the limit is SVR4_RLIM_INFINITY, then we set it to our - * unlimited. - * We should also: If it is SVR4_RLIM_SAVED_MAX, we should set the - * new limit to the corresponding saved hard limit, and if - * it is equal to SVR4_RLIM_SAVED_CUR, we should set it to the - * corresponding saved soft limit. - * - */ - if (slim.rlim_max == SVR4_RLIM_INFINITY) - blim.rlim_max = RLIM_INFINITY; - else if (OKLIMIT(slim.rlim_max)) - blim.rlim_max = (rlim_t) slim.rlim_max; - else if (slim.rlim_max == SVR4_RLIM_SAVED_MAX) - blim.rlim_max = curlim.rlim_max; - else if (slim.rlim_max == SVR4_RLIM_SAVED_CUR) - blim.rlim_max = curlim.rlim_cur; - - if (slim.rlim_cur == SVR4_RLIM_INFINITY) - blim.rlim_cur = RLIM_INFINITY; - else if (OKLIMIT(slim.rlim_cur)) - blim.rlim_cur = (rlim_t) slim.rlim_cur; - else if (slim.rlim_cur == SVR4_RLIM_SAVED_MAX) - blim.rlim_cur = curlim.rlim_max; - else if (slim.rlim_cur == SVR4_RLIM_SAVED_CUR) - blim.rlim_cur = curlim.rlim_cur; - - return (kern_setrlimit(td, rl, &blim)); -} - - -int -svr4_sys_getrlimit64(td, uap) - struct thread *td; - struct svr4_sys_getrlimit64_args *uap; -{ - int rl = svr4_to_native_rl(uap->which); - struct rlimit blim; - struct svr4_rlimit64 slim; - - if (rl == -1) - return EINVAL; - - lim_rlimit(td, rl, &blim); - - /* - * Our infinity, is their maxfiles. - */ - if (rl == RLIMIT_NOFILE && blim.rlim_max == RLIM_INFINITY) - blim.rlim_max = maxfiles; - - /* - * If the limit can be be represented, it is returned. - * Otherwise, if rlim_cur == rlim_max, return SVR4_RLIM_SAVED_MAX - * else return SVR4_RLIM_SAVED_CUR - */ - if (blim.rlim_max == RLIM_INFINITY) - slim.rlim_max = SVR4_RLIM64_INFINITY; - else if (OKLIMIT64(blim.rlim_max)) - slim.rlim_max = (svr4_rlim64_t) blim.rlim_max; - else - slim.rlim_max = SVR4_RLIM64_SAVED_MAX; - - if (blim.rlim_cur == RLIM_INFINITY) - slim.rlim_cur = SVR4_RLIM64_INFINITY; - else if (OKLIMIT64(blim.rlim_cur)) - slim.rlim_cur = (svr4_rlim64_t) blim.rlim_cur; - else if (blim.rlim_max == blim.rlim_cur) - slim.rlim_cur = SVR4_RLIM64_SAVED_MAX; - else - slim.rlim_cur = SVR4_RLIM64_SAVED_CUR; - - return copyout(&slim, uap->rlp, sizeof(*uap->rlp)); -} - - -int -svr4_sys_setrlimit64(td, uap) - struct thread *td; - struct svr4_sys_setrlimit64_args *uap; -{ - int rl = svr4_to_native_rl(uap->which); - struct rlimit blim, curlim; - struct svr4_rlimit64 slim; - int error; - - if (rl == -1) - return EINVAL; - - if ((error = copyin(uap->rlp, &slim, sizeof(slim))) != 0) - return error; - - lim_rlimit(td, rl, &curlim); - - /* - * if the limit is SVR4_RLIM64_INFINITY, then we set it to our - * unlimited. - * We should also: If it is SVR4_RLIM64_SAVED_MAX, we should set the - * new limit to the corresponding saved hard limit, and if - * it is equal to SVR4_RLIM64_SAVED_CUR, we should set it to the - * corresponding saved soft limit. - * - */ - if (slim.rlim_max == SVR4_RLIM64_INFINITY) - blim.rlim_max = RLIM_INFINITY; - else if (OKLIMIT64(slim.rlim_max)) - blim.rlim_max = (rlim_t) slim.rlim_max; - else if (slim.rlim_max == SVR4_RLIM64_SAVED_MAX) - blim.rlim_max = curlim.rlim_max; - else if (slim.rlim_max == SVR4_RLIM64_SAVED_CUR) - blim.rlim_max = curlim.rlim_cur; - - if (slim.rlim_cur == SVR4_RLIM64_INFINITY) - blim.rlim_cur = RLIM_INFINITY; - else if (OKLIMIT64(slim.rlim_cur)) - blim.rlim_cur = (rlim_t) slim.rlim_cur; - else if (slim.rlim_cur == SVR4_RLIM64_SAVED_MAX) - blim.rlim_cur = curlim.rlim_max; - else if (slim.rlim_cur == SVR4_RLIM64_SAVED_CUR) - blim.rlim_cur = curlim.rlim_cur; - - return (kern_setrlimit(td, rl, &blim)); -} diff --git a/sys/compat/svr4/svr4_resource.h b/sys/compat/svr4/svr4_resource.h deleted file mode 100644 index c544b3adb77..00000000000 --- a/sys/compat/svr4/svr4_resource.h +++ /dev/null @@ -1,102 +0,0 @@ -/* Derived from: - * $NetBSD: svr4_resource.h,v 1.1 1998/11/28 21:53:02 christos Exp $ */ - -/*- - * Original copyright: - * - * Copyright (c) 1998 The NetBSD Foundation, Inc. - * All rights reserved. - * - * This code is derived from software contributed to The NetBSD Foundation - * by Christos Zoulas. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS - * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * $FreeBSD: stable/11/sys/compat/svr4/svr4_resource.h 263289 2014-03-18 01:40:25Z emaste $ - */ - -/*- - * Portions of this code derived from software contributed to the - * FreeBSD Project by Mark Newton. - * - * Copyright (c) 1999 Mark Newton - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _SVR4_RESOURCE_H_ -#define _SVR4_RESOURCE_H_ - -#define SVR4_RLIMIT_CPU 0 -#define SVR4_RLIMIT_FSIZE 1 -#define SVR4_RLIMIT_DATA 2 -#define SVR4_RLIMIT_STACK 3 -#define SVR4_RLIMIT_CORE 4 -#define SVR4_RLIMIT_NOFILE 5 -#define SVR4_RLIMIT_VMEM 6 -#define SVR4_RLIMIT_AS SVR4_RLIMIT_VMEM -#define SVR4_RLIM_NLIMITS 7 - -typedef u_int32_t svr4_rlim_t; - -#define SVR4_RLIM_SAVED_CUR 0x7ffffffd -#define SVR4_RLIM_SAVED_MAX 0x7ffffffe -#define SVR4_RLIM_INFINITY 0x7fffffff - -struct svr4_rlimit { - svr4_rlim_t rlim_cur; - svr4_rlim_t rlim_max; -}; - -typedef u_int64_t svr4_rlim64_t; - -#define SVR4_RLIM64_SAVED_CUR ((svr4_rlim64_t) -1) -#define SVR4_RLIM64_SAVED_MAX ((svr4_rlim64_t) -2) -#define SVR4_RLIM64_INFINITY ((svr4_rlim64_t) -3) - -struct svr4_rlimit64 { - svr4_rlim64_t rlim_cur; - svr4_rlim64_t rlim_max; -}; - -#endif /* !_SVR4_RESOURCE_H_ */ diff --git a/sys/compat/svr4/svr4_siginfo.h b/sys/compat/svr4/svr4_siginfo.h deleted file mode 100644 index 3ad8c25c08b..00000000000 --- a/sys/compat/svr4/svr4_siginfo.h +++ /dev/null @@ -1,111 +0,0 @@ -/*- - * Copyright (c) 1998 Mark Newton - * Copyright (c) 1994 Christos Zoulas - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * $FreeBSD: stable/11/sys/compat/svr4/svr4_siginfo.h 151463 2005-10-19 09:33:15Z davidxu $ - */ - -#ifndef _SVR4_SIGINFO_H_ -#define _SVR4_SIGINFO_H_ - -#define SVR4_ILL_ILLOPC 1 -#define SVR4_ILL_ILLOPN 2 -#define SVR4_ILL_ILLADR 3 -#define SVR4_ILL_ILLTRP 4 -#define SVR4_ILL_PRVOPC 5 -#define SVR4_ILL_PRVREG 6 -#define SVR4_ILL_COPROC 7 -#define SVR4_ILL_BADSTK 8 - -#define SVR4_FPE_INTDIV 1 -#define SVR4_FPE_INTOVF 2 -#define SVR4_FPE_FLTDIV 3 -#define SVR4_FPE_FLTOVF 4 -#define SVR4_FPE_FLTUND 5 -#define SVR4_FPE_FLTRES 6 -#define SVR4_FPE_FLTINV 7 -#define SVR4_FPE_FLTSUB 8 - -#define SVR4_SEGV_MAPERR 1 -#define SVR4_SEGV_ACCERR 2 - -#define SVR4_BUS_ADRALN 1 -#define SVR4_BUS_ADRERR 2 -#define SVR4_BUS_OBJERR 3 - -#define SVR4_TRAP_BRKPT 1 -#define SVR4_TRAP_TRACE 2 - -#define SVR4_POLL_IN 1 -#define SVR4_POLL_OUT 2 -#define SVR4_POLL_MSG 3 -#define SVR4_POLL_ERR 4 -#define SVR4_POLL_PRI 5 - -#define SVR4_CLD_EXITED 1 -#define SVR4_CLD_KILLED 2 -#define SVR4_CLD_DUMPED 3 -#define SVR4_CLD_TRAPPED 4 -#define SVR4_CLD_STOPPED 5 -#define SVR4_CLD_CONTINUED 6 - -#define SVR4_EMT_TAGOVF 1 - -typedef union svr4_siginfo { - char si_pad[128]; /* Total size; for future expansion */ - struct { - int _signo; - int _code; - int _errno; - union { - struct { - svr4_pid_t _pid; - svr4_clock_t _utime; - int _status; - svr4_clock_t _stime; - } _child; - - struct { - caddr_t _addr; - int _trap; - } _fault; - } _reason; - } _info; -} svr4_siginfo_t; - -#define svr4_si_signo _info._signo -#define svr4_si_code _info._code -#define svr4_si_errno _info._errno - -#define svr4_si_pid _info._reason._child._pid -#define svr4_si_stime _info._reason._child._stime -#define svr4_si_status _info._reason._child._status -#define svr4_si_utime _info._reason._child._utime - -#define svr4_si_addr _info._reason._fault._addr -#define svr4_si_trap _info._reason._fault._trap - -#endif /* !_SVR4_SIGINFO_H_ */ diff --git a/sys/compat/svr4/svr4_signal.c b/sys/compat/svr4/svr4_signal.c deleted file mode 100644 index c122e0dd83d..00000000000 --- a/sys/compat/svr4/svr4_signal.c +++ /dev/null @@ -1,576 +0,0 @@ -/*- - * Copyright (c) 1998 Mark Newton - * Copyright (c) 1994 Christos Zoulas - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include -#include -#include -#include -#include -#include - -#define svr4_sigmask(n) (1 << (((n) - 1) & 31)) -#define svr4_sigword(n) (((n) - 1) >> 5) -#define svr4_sigemptyset(s) memset((s), 0, sizeof(*(s))) -#define svr4_sigismember(s, n) ((s)->bits[svr4_sigword(n)] & svr4_sigmask(n)) -#define svr4_sigaddset(s, n) ((s)->bits[svr4_sigword(n)] |= svr4_sigmask(n)) - -void svr4_to_bsd_sigaction(const struct svr4_sigaction *, struct sigaction *); -void bsd_to_svr4_sigaction(const struct sigaction *, struct svr4_sigaction *); -void svr4_sigfillset(svr4_sigset_t *); - -int bsd_to_svr4_sig[SVR4_NSIG] = { - 0, - SVR4_SIGHUP, - SVR4_SIGINT, - SVR4_SIGQUIT, - SVR4_SIGILL, - SVR4_SIGTRAP, - SVR4_SIGABRT, - SVR4_SIGEMT, - SVR4_SIGFPE, - SVR4_SIGKILL, - SVR4_SIGBUS, - SVR4_SIGSEGV, - SVR4_SIGSYS, - SVR4_SIGPIPE, - SVR4_SIGALRM, - SVR4_SIGTERM, - SVR4_SIGURG, - SVR4_SIGSTOP, - SVR4_SIGTSTP, - SVR4_SIGCONT, - SVR4_SIGCHLD, - SVR4_SIGTTIN, - SVR4_SIGTTOU, - SVR4_SIGIO, - SVR4_SIGXCPU, - SVR4_SIGXFSZ, - SVR4_SIGVTALRM, - SVR4_SIGPROF, - SVR4_SIGWINCH, - 0, /* SIGINFO */ - SVR4_SIGUSR1, - SVR4_SIGUSR2, -}; - -int svr4_to_bsd_sig[SVR4_NSIG] = { - 0, - SIGHUP, - SIGINT, - SIGQUIT, - SIGILL, - SIGTRAP, - SIGABRT, - SIGEMT, - SIGFPE, - SIGKILL, - SIGBUS, - SIGSEGV, - SIGSYS, - SIGPIPE, - SIGALRM, - SIGTERM, - SIGUSR1, - SIGUSR2, - SIGCHLD, - 0, /* XXX NetBSD uses SIGPWR here, but we don't seem to have one */ - SIGWINCH, - SIGURG, - SIGIO, - SIGSTOP, - SIGTSTP, - SIGCONT, - SIGTTIN, - SIGTTOU, - SIGVTALRM, - SIGPROF, - SIGXCPU, - SIGXFSZ, -}; - -void -svr4_sigfillset(s) - svr4_sigset_t *s; -{ - int i; - - svr4_sigemptyset(s); - for (i = 1; i < SVR4_NSIG; i++) - if (svr4_to_bsd_sig[i] != 0) - svr4_sigaddset(s, i); -} - -void -svr4_to_bsd_sigset(sss, bss) - const svr4_sigset_t *sss; - sigset_t *bss; -{ - int i, newsig; - - SIGEMPTYSET(*bss); - for (i = 1; i < SVR4_NSIG; i++) - if (svr4_sigismember(sss, i)) { - newsig = svr4_to_bsd_sig[i]; - if (newsig) - SIGADDSET(*bss, newsig); - } -} - -void -bsd_to_svr4_sigset(bss, sss) - const sigset_t *bss; - svr4_sigset_t *sss; -{ - int i, newsig; - - svr4_sigemptyset(sss); - for (i = 1; i < SVR4_NSIG; i++) { - if (SIGISMEMBER(*bss, i)) { - newsig = bsd_to_svr4_sig[i]; - if (newsig) - svr4_sigaddset(sss, newsig); - } - } -} - -/* - * XXX: Only a subset of the flags is currently implemented. - */ -void -svr4_to_bsd_sigaction(ssa, bsa) - const struct svr4_sigaction *ssa; - struct sigaction *bsa; -{ - - bsa->sa_handler = (sig_t) ssa->ssa_handler; - svr4_to_bsd_sigset(&ssa->ssa_mask, &bsa->sa_mask); - bsa->sa_flags = 0; - if ((ssa->ssa_flags & SVR4_SA_ONSTACK) != 0) - bsa->sa_flags |= SA_ONSTACK; - if ((ssa->ssa_flags & SVR4_SA_RESETHAND) != 0) - bsa->sa_flags |= SA_RESETHAND; - if ((ssa->ssa_flags & SVR4_SA_RESTART) != 0) - bsa->sa_flags |= SA_RESTART; - if ((ssa->ssa_flags & SVR4_SA_SIGINFO) != 0) - DPRINTF(("svr4_to_bsd_sigaction: SA_SIGINFO ignored\n")); - if ((ssa->ssa_flags & SVR4_SA_NOCLDSTOP) != 0) - bsa->sa_flags |= SA_NOCLDSTOP; - if ((ssa->ssa_flags & SVR4_SA_NODEFER) != 0) - bsa->sa_flags |= SA_NODEFER; - if ((ssa->ssa_flags & SVR4_SA_NOCLDWAIT) != 0) - bsa->sa_flags |= SA_NOCLDWAIT; - if ((ssa->ssa_flags & ~SVR4_SA_ALLBITS) != 0) - DPRINTF(("svr4_to_bsd_sigaction: extra bits ignored\n")); -} - -void -bsd_to_svr4_sigaction(bsa, ssa) - const struct sigaction *bsa; - struct svr4_sigaction *ssa; -{ - - ssa->ssa_handler = (svr4_sig_t) bsa->sa_handler; - bsd_to_svr4_sigset(&bsa->sa_mask, &ssa->ssa_mask); - ssa->ssa_flags = 0; - if ((bsa->sa_flags & SA_ONSTACK) != 0) - ssa->ssa_flags |= SVR4_SA_ONSTACK; - if ((bsa->sa_flags & SA_RESETHAND) != 0) - ssa->ssa_flags |= SVR4_SA_RESETHAND; - if ((bsa->sa_flags & SA_RESTART) != 0) - ssa->ssa_flags |= SVR4_SA_RESTART; - if ((bsa->sa_flags & SA_NODEFER) != 0) - ssa->ssa_flags |= SVR4_SA_NODEFER; - if ((bsa->sa_flags & SA_NOCLDSTOP) != 0) - ssa->ssa_flags |= SVR4_SA_NOCLDSTOP; -} - -void -svr4_to_bsd_sigaltstack(sss, bss) - const struct svr4_sigaltstack *sss; - struct sigaltstack *bss; -{ - - bss->ss_sp = sss->ss_sp; - bss->ss_size = sss->ss_size; - bss->ss_flags = 0; - if ((sss->ss_flags & SVR4_SS_DISABLE) != 0) - bss->ss_flags |= SS_DISABLE; - if ((sss->ss_flags & SVR4_SS_ONSTACK) != 0) - bss->ss_flags |= SS_ONSTACK; - if ((sss->ss_flags & ~SVR4_SS_ALLBITS) != 0) - /*XXX*/ uprintf("svr4_to_bsd_sigaltstack: extra bits ignored\n"); -} - -void -bsd_to_svr4_sigaltstack(bss, sss) - const struct sigaltstack *bss; - struct svr4_sigaltstack *sss; -{ - - sss->ss_sp = bss->ss_sp; - sss->ss_size = bss->ss_size; - sss->ss_flags = 0; - if ((bss->ss_flags & SS_DISABLE) != 0) - sss->ss_flags |= SVR4_SS_DISABLE; - if ((bss->ss_flags & SS_ONSTACK) != 0) - sss->ss_flags |= SVR4_SS_ONSTACK; -} - -int -svr4_sys_sigaction(td, uap) - struct thread *td; - struct svr4_sys_sigaction_args *uap; -{ - struct svr4_sigaction isa; - struct sigaction nbsa, obsa; - struct sigaction *nbsap; - int error; - - if (uap->signum < 0 || uap->signum >= SVR4_NSIG) - return (EINVAL); - - DPRINTF(("@@@ svr4_sys_sigaction(%d, %d, %d)\n", td->td_proc->p_pid, - uap->signum, - SVR4_SVR42BSD_SIG(uap->signum))); - - if (uap->nsa != NULL) { - if ((error = copyin(uap->nsa, &isa, sizeof(isa))) != 0) - return (error); - svr4_to_bsd_sigaction(&isa, &nbsa); - nbsap = &nbsa; - } else - nbsap = NULL; -#if defined(DEBUG_SVR4) - { - int i; - for (i = 0; i < 4; i++) - DPRINTF(("\tssa_mask[%d] = %lx\n", i, - isa.ssa_mask.bits[i])); - DPRINTF(("\tssa_handler = %p\n", isa.ssa_handler)); - } -#endif - error = kern_sigaction(td, SVR4_SVR42BSD_SIG(uap->signum), nbsap, &obsa, - 0); - if (error == 0 && uap->osa != NULL) { - bsd_to_svr4_sigaction(&obsa, &isa); - error = copyout(&isa, uap->osa, sizeof(isa)); - } - return (error); -} - -int -svr4_sys_sigaltstack(td, uap) - struct thread *td; - struct svr4_sys_sigaltstack_args *uap; -{ - struct svr4_sigaltstack sss; - struct sigaltstack nbss, obss, *nbssp; - int error; - - if (uap->nss != NULL) { - if ((error = copyin(uap->nss, &sss, sizeof(sss))) != 0) - return (error); - svr4_to_bsd_sigaltstack(&sss, &nbss); - nbssp = &nbss; - } else - nbssp = NULL; - error = kern_sigaltstack(td, nbssp, &obss); - if (error == 0 && uap->oss != NULL) { - bsd_to_svr4_sigaltstack(&obss, &sss); - error = copyout(&sss, uap->oss, sizeof(sss)); - } - return (error); -} - -/* - * Stolen from the ibcs2 one - */ -int -svr4_sys_signal(td, uap) - struct thread *td; - struct svr4_sys_signal_args *uap; -{ - struct proc *p; - int signum; - int error; - - p = td->td_proc; - DPRINTF(("@@@ svr4_sys_signal(%d)\n", p->p_pid)); - - signum = SVR4_SIGNO(uap->signum); - if (signum < 0 || signum >= SVR4_NSIG) { - if (SVR4_SIGCALL(uap->signum) == SVR4_SIGNAL_MASK || - SVR4_SIGCALL(uap->signum) == SVR4_SIGDEFER_MASK) - td->td_retval[0] = (int)SVR4_SIG_ERR; - return (EINVAL); - } - signum = SVR4_SVR42BSD_SIG(signum); - - switch (SVR4_SIGCALL(uap->signum)) { - case SVR4_SIGDEFER_MASK: - if (uap->handler == SVR4_SIG_HOLD) - goto sighold; - /* FALLTHROUGH */ - - case SVR4_SIGNAL_MASK: - { - struct sigaction nbsa, obsa; - - nbsa.sa_handler = (sig_t) uap->handler; - SIGEMPTYSET(nbsa.sa_mask); - nbsa.sa_flags = 0; - if (signum != SIGALRM) - nbsa.sa_flags = SA_RESTART; - error = kern_sigaction(td, signum, &nbsa, &obsa, 0); - if (error != 0) { - DPRINTF(("signal: sigaction failed: %d\n", - error)); - td->td_retval[0] = (int)SVR4_SIG_ERR; - return (error); - } - td->td_retval[0] = (int)obsa.sa_handler; - return (0); - } - - case SVR4_SIGHOLD_MASK: -sighold: - { - sigset_t set; - - SIGEMPTYSET(set); - SIGADDSET(set, signum); - return (kern_sigprocmask(td, SIG_BLOCK, &set, NULL, 0)); - } - - case SVR4_SIGRELSE_MASK: - { - sigset_t set; - - SIGEMPTYSET(set); - SIGADDSET(set, signum); - return (kern_sigprocmask(td, SIG_UNBLOCK, &set, NULL, - 0)); - } - - case SVR4_SIGIGNORE_MASK: - { - struct sigaction sa; - - sa.sa_handler = SIG_IGN; - SIGEMPTYSET(sa.sa_mask); - sa.sa_flags = 0; - error = kern_sigaction(td, signum, &sa, NULL, 0); - if (error != 0) - DPRINTF(("sigignore: sigaction failed\n")); - return (error); - } - - case SVR4_SIGPAUSE_MASK: - { - sigset_t mask; - - PROC_LOCK(p); - mask = td->td_sigmask; - PROC_UNLOCK(p); - SIGDELSET(mask, signum); - return kern_sigsuspend(td, mask); - } - - default: - return (ENOSYS); - } -} - - -int -svr4_sys_sigprocmask(td, uap) - struct thread *td; - struct svr4_sys_sigprocmask_args *uap; -{ - svr4_sigset_t sss; - sigset_t oss, nss; - sigset_t *nssp; - int error; - - if (uap->set != NULL) { - if ((error = copyin(uap->set, &sss, sizeof(sss))) != 0) - return error; - svr4_to_bsd_sigset(&sss, &nss); - nssp = &nss; - } else - nssp = NULL; - - /* SVR/4 sigprocmask flag values are the same as the FreeBSD values. */ - error = kern_sigprocmask(td, uap->how, nssp, &oss, 0); - if (error == 0 && uap->oset != NULL) { - bsd_to_svr4_sigset(&oss, &sss); - error = copyout(&sss, uap->oset, sizeof(sss)); - } - return (error); -} - -int -svr4_sys_sigpending(td, uap) - struct thread *td; - struct svr4_sys_sigpending_args *uap; -{ - struct proc *p; - sigset_t bss; - svr4_sigset_t sss; - - p = td->td_proc; - DPRINTF(("@@@ svr4_sys_sigpending(%d)\n", p->p_pid)); - switch (uap->what) { - case 1: /* sigpending */ - if (uap->mask == NULL) - return 0; - PROC_LOCK(p); - bss = p->p_siglist; - SIGSETOR(bss, td->td_siglist); - SIGSETAND(bss, td->td_sigmask); - PROC_UNLOCK(p); - bsd_to_svr4_sigset(&bss, &sss); - break; - - case 2: /* sigfillset */ - svr4_sigfillset(&sss); -#if defined(DEBUG_SVR4) - { - int i; - for (i = 0; i < 4; i++) - DPRINTF(("new sigset[%d] = %lx\n", i, (long)sss.bits[i])); - } -#endif - break; - - default: - return EINVAL; - } - - return copyout(&sss, uap->mask, sizeof(sss)); -} - -int -svr4_sys_sigsuspend(td, uap) - struct thread *td; - struct svr4_sys_sigsuspend_args *uap; -{ - svr4_sigset_t sss; - sigset_t bss; - int error; - - if ((error = copyin(uap->ss, &sss, sizeof(sss))) != 0) - return error; - - svr4_to_bsd_sigset(&sss, &bss); - return kern_sigsuspend(td, bss); -} - - -int -svr4_sys_kill(td, uap) - struct thread *td; - struct svr4_sys_kill_args *uap; -{ - struct kill_args ka; - - if (uap->signum < 0 || uap->signum >= SVR4_NSIG) - return (EINVAL); - ka.pid = uap->pid; - ka.signum = SVR4_SVR42BSD_SIG(uap->signum); - return sys_kill(td, &ka); -} - - -int -svr4_sys_context(td, uap) - struct thread *td; - struct svr4_sys_context_args *uap; -{ - struct svr4_ucontext uc; - int error, onstack; - - switch (uap->func) { - case 0: - DPRINTF(("getcontext(%p)\n", uap->uc)); - PROC_LOCK(td->td_proc); - onstack = sigonstack(cpu_getstack(td)); - PROC_UNLOCK(td->td_proc); - svr4_getcontext(td, &uc, &td->td_sigmask, onstack); - return copyout(&uc, uap->uc, sizeof(uc)); - - case 1: - DPRINTF(("setcontext(%p)\n", uap->uc)); - if ((error = copyin(uap->uc, &uc, sizeof(uc))) != 0) - return error; - DPRINTF(("uc_flags = %lx\n", uc.uc_flags)); -#if defined(DEBUG_SVR4) - { - int i; - for (i = 0; i < 4; i++) - DPRINTF(("uc_sigmask[%d] = %lx\n", i, - uc.uc_sigmask.bits[i])); - } -#endif - return svr4_setcontext(td, &uc); - - default: - DPRINTF(("context(%d, %p)\n", uap->func, - uap->uc)); - return ENOSYS; - } - return 0; -} - -int -svr4_sys_pause(td, uap) - struct thread *td; - struct svr4_sys_pause_args *uap; -{ - sigset_t mask; - - PROC_LOCK(td->td_proc); - mask = td->td_sigmask; - PROC_UNLOCK(td->td_proc); - return kern_sigsuspend(td, mask); -} diff --git a/sys/compat/svr4/svr4_signal.h b/sys/compat/svr4/svr4_signal.h deleted file mode 100644 index 9a01376aa6a..00000000000 --- a/sys/compat/svr4/svr4_signal.h +++ /dev/null @@ -1,144 +0,0 @@ -/*- - * Copyright (c) 1998 Mark Newton - * Copyright (c) 1994 Christos Zoulas - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * $FreeBSD: stable/11/sys/compat/svr4/svr4_signal.h 151316 2005-10-14 12:43:47Z davidxu $ - */ - -#ifndef _SVR4_SIGNAL_H_ -#define _SVR4_SIGNAL_H_ - -#include -#include - -#define SVR4_SIGHUP 1 -#define SVR4_SIGINT 2 -#define SVR4_SIGQUIT 3 -#define SVR4_SIGILL 4 -#define SVR4_SIGTRAP 5 -#define SVR4_SIGIOT 6 -#define SVR4_SIGABRT 6 -#define SVR4_SIGEMT 7 -#define SVR4_SIGFPE 8 -#define SVR4_SIGKILL 9 -#define SVR4_SIGBUS 10 -#define SVR4_SIGSEGV 11 -#define SVR4_SIGSYS 12 -#define SVR4_SIGPIPE 13 -#define SVR4_SIGALRM 14 -#define SVR4_SIGTERM 15 -#define SVR4_SIGUSR1 16 -#define SVR4_SIGUSR2 17 -#define SVR4_SIGCLD 18 -#define SVR4_SIGCHLD 18 -#define SVR4_SIGPWR 19 -#define SVR4_SIGWINCH 20 -#define SVR4_SIGURG 21 -#define SVR4_SIGPOLL 22 -#define SVR4_SIGIO 22 -#define SVR4_SIGSTOP 23 -#define SVR4_SIGTSTP 24 -#define SVR4_SIGCONT 25 -#define SVR4_SIGTTIN 26 -#define SVR4_SIGTTOU 27 -#define SVR4_SIGVTALRM 28 -#define SVR4_SIGPROF 29 -#define SVR4_SIGXCPU 30 -#define SVR4_SIGXFSZ 31 -#define SVR4_NSIG 32 - -#define SVR4_SIGNO_MASK 0x00FF -#define SVR4_SIGNAL_MASK 0x0000 -#define SVR4_SIGDEFER_MASK 0x0100 -#define SVR4_SIGHOLD_MASK 0x0200 -#define SVR4_SIGRELSE_MASK 0x0400 -#define SVR4_SIGIGNORE_MASK 0x0800 -#define SVR4_SIGPAUSE_MASK 0x1000 - -typedef void (*svr4_sig_t)(int, svr4_siginfo_t *, void *); -#define SVR4_SIG_DFL (svr4_sig_t) 0 -#define SVR4_SIG_ERR (svr4_sig_t) -1 -#define SVR4_SIG_IGN (svr4_sig_t) 1 -#define SVR4_SIG_HOLD (svr4_sig_t) 2 - -#define SVR4_SIGNO(a) ((a) & SVR4_SIGNO_MASK) -#define SVR4_SIGCALL(a) ((a) & ~SVR4_SIGNO_MASK) - -#define SVR4_SIG_BLOCK 1 -#define SVR4_SIG_UNBLOCK 2 -#define SVR4_SIG_SETMASK 3 - -extern int bsd_to_svr4_sig[SVR4_NSIG]; -extern int svr4_to_bsd_sig[SVR4_NSIG]; - -#define SVR4_BSD2SVR4_SIG(sig) \ - (((sig) < SVR4_NSIG) ? bsd_to_svr4_sig[sig] : sig) -#define SVR4_SVR42BSD_SIG(sig) \ - (((sig) < SVR4_NSIG) ? svr4_to_bsd_sig[sig] : sig) - -typedef struct { - u_long bits[4]; -} svr4_sigset_t; - -struct svr4_sigaction { - int ssa_flags; - svr4_sig_t ssa_handler; - svr4_sigset_t ssa_mask; - int ssa_reserved[2]; -}; - -struct svr4_sigaltstack { - char *ss_sp; - int ss_size; - int ss_flags; -}; - -/* sa_flags */ -#define SVR4_SA_ONSTACK 0x00000001 -#define SVR4_SA_RESETHAND 0x00000002 -#define SVR4_SA_RESTART 0x00000004 -#define SVR4_SA_SIGINFO 0x00000008 -#define SVR4_SA_NODEFER 0x00000010 -#define SVR4_SA_NOCLDWAIT 0x00010000 /* No zombies */ -#define SVR4_SA_NOCLDSTOP 0x00020000 /* No jcl */ -#define SVR4_SA_ALLBITS 0x0003001f - -/* ss_flags */ -#define SVR4_SS_ONSTACK 0x00000001 -#define SVR4_SS_DISABLE 0x00000002 -#define SVR4_SS_ALLBITS 0x00000003 - -#define SVR4_MINSIGSTKSZ 8192 - -struct ksiginfo; - -void bsd_to_svr4_sigaltstack(const struct sigaltstack *, struct svr4_sigaltstack *); -void bsd_to_svr4_sigset(const sigset_t *, svr4_sigset_t *); -void svr4_to_bsd_sigaltstack(const struct svr4_sigaltstack *, struct sigaltstack *); -void svr4_to_bsd_sigset(const svr4_sigset_t *, sigset_t *); -void svr4_sendsig(sig_t, struct ksiginfo *, sigset_t *); - -#endif /* !_SVR4_SIGNAL_H_ */ diff --git a/sys/compat/svr4/svr4_socket.c b/sys/compat/svr4/svr4_socket.c deleted file mode 100644 index 6b57d3c1e36..00000000000 --- a/sys/compat/svr4/svr4_socket.c +++ /dev/null @@ -1,258 +0,0 @@ -/*- - * Copyright (c) 1998 Mark Newton - * Copyright (c) 1996 Christos Zoulas. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by Christos Zoulas. - * 4. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/* - * In SVR4 unix domain sockets are referenced sometimes - * (in putmsg(2) for example) as a [device, inode] pair instead of a pathname. - * Since there is no iname() routine in the kernel, and we need access to - * a mapping from inode to pathname, we keep our own table. This is a simple - * linked list that contains the pathname, the [device, inode] pair, the - * file corresponding to that socket and the process. When the - * socket gets closed we remove the item from the list. The list gets loaded - * every time a stat(2) call finds a socket. - */ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include - -struct svr4_sockcache_entry { - struct proc *p; /* Process for the socket */ - void *cookie; /* Internal cookie used for matching */ - struct sockaddr_un sock;/* Pathname for the socket */ - dev_t dev; /* Device where the socket lives on */ - ino_t ino; /* Inode where the socket lives on */ - TAILQ_ENTRY(svr4_sockcache_entry) entries; -}; - -static TAILQ_HEAD(, svr4_sockcache_entry) svr4_head; -static struct mtx svr4_sockcache_lock; -static eventhandler_tag svr4_sockcache_exit_tag, svr4_sockcache_exec_tag; - -static void svr4_purge_sockcache(void *arg, struct proc *p); - -int -svr4_find_socket(td, fp, dev, ino, saun) - struct thread *td; - struct file *fp; - dev_t dev; - ino_t ino; - struct sockaddr_un *saun; -{ - struct svr4_sockcache_entry *e; - void *cookie = ((struct socket *)fp->f_data)->so_emuldata; - - DPRINTF(("svr4_find_socket: [%p,%ju,%ju]: ", td, (uintmax_t)dev, - (uintmax_t)ino)); - mtx_lock(&svr4_sockcache_lock); - TAILQ_FOREACH(e, &svr4_head, entries) - if (e->p == td->td_proc && e->dev == dev && e->ino == ino) { -#ifdef DIAGNOSTIC - if (e->cookie != NULL && e->cookie != cookie) - panic("svr4 socket cookie mismatch"); -#endif - e->cookie = cookie; - DPRINTF(("%s\n", e->sock.sun_path)); - *saun = e->sock; - mtx_unlock(&svr4_sockcache_lock); - return (0); - } - - mtx_unlock(&svr4_sockcache_lock); - DPRINTF(("not found\n")); - return (ENOENT); -} - -int -svr4_add_socket(td, path, st) - struct thread *td; - const char *path; - struct stat *st; -{ - struct svr4_sockcache_entry *e; - size_t len; - int error; - - e = malloc(sizeof(*e), M_TEMP, M_WAITOK); - e->cookie = NULL; - e->dev = st->st_dev; - e->ino = st->st_ino; - e->p = td->td_proc; - - if ((error = copyinstr(path, e->sock.sun_path, - sizeof(e->sock.sun_path), &len)) != 0) { - DPRINTF(("svr4_add_socket: copyinstr failed %d\n", error)); - free(e, M_TEMP); - return error; - } - - e->sock.sun_family = AF_LOCAL; - e->sock.sun_len = len; - - mtx_lock(&svr4_sockcache_lock); - TAILQ_INSERT_HEAD(&svr4_head, e, entries); - mtx_unlock(&svr4_sockcache_lock); - DPRINTF(("svr4_add_socket: %s [%p,%ju,%ju]\n", e->sock.sun_path, - td->td_proc, (uintmax_t)e->dev, (uintmax_t)e->ino)); - return 0; -} - -void -svr4_delete_socket(p, fp) - struct proc *p; - struct file *fp; -{ - struct svr4_sockcache_entry *e; - void *cookie = ((struct socket *)fp->f_data)->so_emuldata; - - mtx_lock(&svr4_sockcache_lock); - TAILQ_FOREACH(e, &svr4_head, entries) - if (e->p == p && e->cookie == cookie) { - TAILQ_REMOVE(&svr4_head, e, entries); - mtx_unlock(&svr4_sockcache_lock); - DPRINTF(("svr4_delete_socket: %s [%p,%ju,%ju]\n", - e->sock.sun_path, p, (uintmax_t)e->dev, - (uintmax_t)e->ino)); - free(e, M_TEMP); - return; - } - mtx_unlock(&svr4_sockcache_lock); -} - -struct svr4_strm * -svr4_stream_get(fp) - struct file *fp; -{ - struct socket *so; - - if (fp == NULL || fp->f_type != DTYPE_SOCKET) - return NULL; - - so = fp->f_data; - return so->so_emuldata; -} - -void -svr4_purge_sockcache(arg, p) - void *arg; - struct proc *p; -{ - struct svr4_sockcache_entry *e, *ne; - - mtx_lock(&svr4_sockcache_lock); - TAILQ_FOREACH_SAFE(e, &svr4_head, entries, ne) { - if (e->p == p) { - TAILQ_REMOVE(&svr4_head, e, entries); - DPRINTF(("svr4_purge_sockcache: %s [%p,%ju,%ju]\n", - e->sock.sun_path, p, (uintmax_t)e->dev, - (uintmax_t)e->ino)); - free(e, M_TEMP); - } - } - mtx_unlock(&svr4_sockcache_lock); -} - -void -svr4_sockcache_init(void) -{ - - TAILQ_INIT(&svr4_head); - mtx_init(&svr4_sockcache_lock, "svr4 socket cache", NULL, MTX_DEF); - svr4_sockcache_exit_tag = EVENTHANDLER_REGISTER(process_exit, - svr4_purge_sockcache, NULL, EVENTHANDLER_PRI_ANY); - svr4_sockcache_exec_tag = EVENTHANDLER_REGISTER(process_exec, - svr4_purge_sockcache, NULL, EVENTHANDLER_PRI_ANY); -} - -void -svr4_sockcache_destroy(void) -{ - - KASSERT(TAILQ_EMPTY(&svr4_head), - ("%s: sockcache entries still around", __func__)); - EVENTHANDLER_DEREGISTER(process_exec, svr4_sockcache_exec_tag); - EVENTHANDLER_DEREGISTER(process_exit, svr4_sockcache_exit_tag); - mtx_destroy(&svr4_sockcache_lock); -} - -int -svr4_sys_socket(td, uap) - struct thread *td; - struct svr4_sys_socket_args *uap; -{ - switch (uap->type) { - case SVR4_SOCK_DGRAM: - uap->type = SOCK_DGRAM; - break; - - case SVR4_SOCK_STREAM: - uap->type = SOCK_STREAM; - break; - - case SVR4_SOCK_RAW: - uap->type = SOCK_RAW; - break; - - case SVR4_SOCK_RDM: - uap->type = SOCK_RDM; - break; - - case SVR4_SOCK_SEQPACKET: - uap->type = SOCK_SEQPACKET; - break; - default: - return EINVAL; - } - return sys_socket(td, (struct socket_args *)uap); -} diff --git a/sys/compat/svr4/svr4_socket.h b/sys/compat/svr4/svr4_socket.h deleted file mode 100644 index 731e7f53993..00000000000 --- a/sys/compat/svr4/svr4_socket.h +++ /dev/null @@ -1,58 +0,0 @@ -/*- - * Copyright (c) 1998 Mark Newton - * Copyright (c) 1996 Christos Zoulas. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by Christos Zoulas. - * 4. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * $FreeBSD: stable/11/sys/compat/svr4/svr4_socket.h 160558 2006-07-21 20:40:13Z jhb $ - */ - -#ifndef _SVR4_SOCKET_H_ -#define _SVR4_SOCKET_H_ - -#include - -struct sockaddr_un; -struct proc; -struct thread; -struct file; - -struct svr4_sockaddr_in { - u_char sin_family; - u_short sin_port; - struct in_addr sin_addr; - u_char sin_zero[8]; -}; - -int svr4_add_socket(struct thread *, const char *, struct stat *); -void svr4_delete_socket(struct proc *, struct file *); -int svr4_find_socket(struct thread *, struct file *, dev_t, ino_t, - struct sockaddr_un *); -void svr4_sockcache_init(void); -void svr4_sockcache_destroy(void); - -#endif /* _SVR4_SOCKET_H_ */ diff --git a/sys/compat/svr4/svr4_sockio.c b/sys/compat/svr4/svr4_sockio.c deleted file mode 100644 index 53f1093581a..00000000000 --- a/sys/compat/svr4/svr4_sockio.c +++ /dev/null @@ -1,170 +0,0 @@ -/*- - * Copyright (c) 1998 Mark Newton - * Copyright (c) 1995 Christos Zoulas - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include -#include -#include -#include - -static int bsd_to_svr4_flags(int); - -#define bsd_to_svr4_flag(a) \ - if (bf & __CONCAT(I,a)) sf |= __CONCAT(SVR4_I,a) - -static int -bsd_to_svr4_flags(bf) - int bf; -{ - int sf = 0; - bsd_to_svr4_flag(FF_UP); - bsd_to_svr4_flag(FF_BROADCAST); - bsd_to_svr4_flag(FF_DEBUG); - bsd_to_svr4_flag(FF_LOOPBACK); - bsd_to_svr4_flag(FF_POINTOPOINT); -#if defined(IFF_NOTRAILERS) - bsd_to_svr4_flag(FF_NOTRAILERS); -#endif - if (bf & IFF_DRV_RUNNING) - sf |= SVR4_IFF_RUNNING; - bsd_to_svr4_flag(FF_NOARP); - bsd_to_svr4_flag(FF_PROMISC); - bsd_to_svr4_flag(FF_ALLMULTI); - bsd_to_svr4_flag(FF_MULTICAST); - return sf; -} - -#define OSIOCGIFCONF _IOWR('i', 20, struct ifconf) - -int -svr4_sock_ioctl(fp, td, retval, fd, cmd, data) - struct file *fp; - struct thread *td; - register_t *retval; - int fd; - u_long cmd; - caddr_t data; -{ - int error; - - *retval = 0; - - switch (cmd) { - case SVR4_SIOCGIFNUM: - { - struct ifnet *ifp; - struct ifaddr *ifa; - int ifnum = 0; - - /* - * This does not return the number of physical - * interfaces (if_index), but the number of interfaces - * + addresses like ifconf() does, because this number - * is used by code that will call SVR4_SIOCGIFCONF to - * find the space needed for SVR4_SIOCGIFCONF. So we - * count the number of ifreq entries that the next - * SVR4_SIOCGIFCONF will return. Maybe a more correct - * fix is to make SVR4_SIOCGIFCONF return only one - * entry per physical interface? - */ - IFNET_RLOCK(); - TAILQ_FOREACH(ifp, &V_ifnet, if_link) - if (TAILQ_EMPTY(&ifp->if_addrhead)) - ifnum++; - else - TAILQ_FOREACH(ifa, &ifp->if_addrhead, - ifa_link) - ifnum++; - IFNET_RUNLOCK(); - DPRINTF(("SIOCGIFNUM %d\n", ifnum)); - return copyout(&ifnum, data, sizeof(ifnum)); - } - - case SVR4_SIOCGIFFLAGS: - { - struct ifreq br; - struct svr4_ifreq sr; - - if ((error = copyin(data, &sr, sizeof(sr))) != 0) - return error; - - (void) strlcpy(br.ifr_name, sr.svr4_ifr_name, - sizeof(br.ifr_name)); - if ((error = fo_ioctl(fp, SIOCGIFFLAGS, - (caddr_t) &br, td->td_ucred, - td)) != 0) { - DPRINTF(("SIOCGIFFLAGS (%s) %s: error %d\n", - br.ifr_name, sr.svr4_ifr_name, error)); - return error; - } - - sr.svr4_ifr_flags = bsd_to_svr4_flags(br.ifr_flags); - DPRINTF(("SIOCGIFFLAGS %s = %x\n", - sr.svr4_ifr_name, sr.svr4_ifr_flags)); - return copyout(&sr, data, sizeof(sr)); - } - - case SVR4_SIOCGIFCONF: - { - struct svr4_ifconf sc; - - if ((error = copyin(data, &sc, sizeof(sc))) != 0) - return error; - - DPRINTF(("ifreq %d svr4_ifreq %d ifc_len %d\n", - sizeof(struct ifreq), sizeof(struct svr4_ifreq), - sc.svr4_ifc_len)); - - if ((error = fo_ioctl(fp, OSIOCGIFCONF, - (caddr_t) &sc, td->td_ucred, - td)) != 0) - return error; - - DPRINTF(("SIOCGIFCONF\n")); - return 0; - } - - - default: - DPRINTF(("Unknown svr4 sockio %lx\n", cmd)); - return 0; /* ENOSYS really */ - } -} diff --git a/sys/compat/svr4/svr4_sockio.h b/sys/compat/svr4/svr4_sockio.h deleted file mode 100644 index 22359a0004e..00000000000 --- a/sys/compat/svr4/svr4_sockio.h +++ /dev/null @@ -1,93 +0,0 @@ -/*- - * Copyright (c) 1998 Mark Newton - * Copyright (c) 1995 Christos Zoulas - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * $FreeBSD: stable/11/sys/compat/svr4/svr4_sockio.h 139743 2005-01-05 22:34:37Z imp $ - */ - -#ifndef _SVR4_SOCKIO_H_ -#define _SVR4_SOCKIO_H_ - -#define SVR4_IFF_UP 0x0001 -#define SVR4_IFF_BROADCAST 0x0002 -#define SVR4_IFF_DEBUG 0x0004 -#define SVR4_IFF_LOOPBACK 0x0008 -#define SVR4_IFF_POINTOPOINT 0x0010 -#define SVR4_IFF_NOTRAILERS 0x0020 -#define SVR4_IFF_RUNNING 0x0040 -#define SVR4_IFF_NOARP 0x0080 -#define SVR4_IFF_PROMISC 0x0100 -#define SVR4_IFF_ALLMULTI 0x0200 -#define SVR4_IFF_INTELLIGENT 0x0400 -#define SVR4_IFF_MULTICAST 0x0800 -#define SVR4_IFF_MULTI_BCAST 0x1000 -#define SVR4_IFF_UNNUMBERED 0x2000 -#define SVR4_IFF_PRIVATE 0x8000 - -struct svr4_ifreq { -#define SVR4_IFNAMSIZ 16 - char svr4_ifr_name[SVR4_IFNAMSIZ]; - union { - struct osockaddr ifru_addr; - struct osockaddr ifru_dstaddr; - struct osockaddr ifru_broadaddr; - short ifru_flags; - int ifru_metric; - char ifru_data; - char ifru_enaddr[6]; - int if_muxid[2]; - - } ifr_ifru; - -#define svr4_ifr_addr ifr_ifru.ifru_addr -#define svr4_ifr_dstaddr ifr_ifru.ifru_dstaddr -#define svr4_ifr_broadaddr ifr_ifru.ifru_broadaddr -#define svr4_ifr_flags ifr_ifru.ifru_flags -#define svr4_ifr_metric ifr_ifru.ifru_metric -#define svr4_ifr_data ifr_ifru.ifru_data -#define svr4_ifr_enaddr ifr_ifru.ifru_enaddr -#define svr4_ifr_muxid ifr_ifru.ifru_muxid - -}; - -struct svr4_ifconf { - int svr4_ifc_len; - union { - caddr_t ifcu_buf; - struct svr4_ifreq *ifcu_req; - } ifc_ifcu; - -#define svr4_ifc_buf ifc_ifcu.ifcu_buf -#define svr4_ifc_req ifc_ifcu.ifcu_req -}; - -#define SVR4_SIOC ('i' << 8) - -#define SVR4_SIOCGIFFLAGS SVR4_IOWR('i', 17, struct svr4_ifreq) -#define SVR4_SIOCGIFCONF SVR4_IOWR('i', 20, struct svr4_ifconf) -#define SVR4_SIOCGIFNUM SVR4_IOR('i', 87, int) - -#endif /* !_SVR4_SOCKIO_H_ */ diff --git a/sys/compat/svr4/svr4_sockmod.h b/sys/compat/svr4/svr4_sockmod.h deleted file mode 100644 index 726cef998c9..00000000000 --- a/sys/compat/svr4/svr4_sockmod.h +++ /dev/null @@ -1,83 +0,0 @@ -/*- - * Copyright (c) 1998 Mark Newton - * Copyright (c) 1994 Christos Zoulas - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * $FreeBSD: stable/11/sys/compat/svr4/svr4_sockmod.h 139743 2005-01-05 22:34:37Z imp $ - */ - -#ifndef _SVR4_SOCKMOD_H_ -#define _SVR4_SOCKMOD_H_ - -#define SVR4_SIMOD ('I' << 8) - -#define SVR4_SI_OGETUDATA (SVR4_SIMOD|101) -#define SVR4_SI_SHUTDOWN (SVR4_SIMOD|102) -#define SVR4_SI_LISTEN (SVR4_SIMOD|103) -#define SVR4_SI_SETMYNAME (SVR4_SIMOD|104) -#define SVR4_SI_SETPEERNAME (SVR4_SIMOD|105) -#define SVR4_SI_GETINTRANSIT (SVR4_SIMOD|106) -#define SVR4_SI_TCL_LINK (SVR4_SIMOD|107) -#define SVR4_SI_TCL_UNLINK (SVR4_SIMOD|108) -#define SVR4_SI_SOCKPARAMS (SVR4_SIMOD|109) -#define SVR4_SI_GETUDATA (SVR4_SIMOD|110) - - -#define SVR4_SOCK_DGRAM 1 -#define SVR4_SOCK_STREAM 2 -#define SVR4_SOCK_STREAM_ORD 3 -#define SVR4_SOCK_RAW 4 -#define SVR4_SOCK_RDM 5 -#define SVR4_SOCK_SEQPACKET 6 - -struct svr4_si_sockparms { - int family; - int type; - int protocol; -}; - -struct svr4_si_oudata { - int tidusize; - int addrsize; - int optsize; - int etsdusize; - int servtype; - int so_state; - int so_options; - int tsdusize; -}; - -struct svr4_si_udata { - int tidusize; - int addrsize; - int optsize; - int etsdusize; - int servtype; - int so_state; - int so_options; - int tsdusize; - struct svr4_si_sockparms sockparms; -}; -#endif /* !_SVR4_SOCKMOD_H_ */ diff --git a/sys/compat/svr4/svr4_stat.c b/sys/compat/svr4/svr4_stat.c deleted file mode 100644 index b167b20b10c..00000000000 --- a/sys/compat/svr4/svr4_stat.c +++ /dev/null @@ -1,704 +0,0 @@ -/*- - * Copyright (c) 1998 Mark Newton - * Copyright (c) 1994 Christos Zoulas - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#if defined(NOTYET) -#include "svr4_fuser.h" -#endif - -#ifdef sparc -/* - * Solaris-2.4 on the sparc has the old stat call using the new - * stat data structure... - */ -# define SVR4_NO_OSTAT -#endif - -struct svr4_ustat_args { - svr4_dev_t dev; - struct svr4_ustat * name; -}; - -static void bsd_to_svr4_xstat(struct stat *, struct svr4_xstat *); -static void bsd_to_svr4_stat64(struct stat *, struct svr4_stat64 *); -int svr4_ustat(struct thread *, struct svr4_ustat_args *); -static int svr4_to_bsd_pathconf(int); - -/* - * SVR4 uses named pipes as named sockets, so we tell programs - * that sockets are named pipes with mode 0 - */ -#define BSD_TO_SVR4_MODE(mode) (S_ISSOCK(mode) ? S_IFIFO : (mode)) - - -#ifndef SVR4_NO_OSTAT -static void bsd_to_svr4_stat(struct stat *, struct svr4_stat *); - -static void -bsd_to_svr4_stat(st, st4) - struct stat *st; - struct svr4_stat *st4; -{ - memset(st4, 0, sizeof(*st4)); - st4->st_dev = bsd_to_svr4_odev_t(st->st_dev); - st4->st_ino = st->st_ino; - st4->st_mode = BSD_TO_SVR4_MODE(st->st_mode); - st4->st_nlink = st->st_nlink; - st4->st_uid = st->st_uid; - st4->st_gid = st->st_gid; - st4->st_rdev = bsd_to_svr4_odev_t(st->st_rdev); - st4->st_size = st->st_size; - st4->st_atim = st->st_atim.tv_sec; - st4->st_mtim = st->st_mtim.tv_sec; - st4->st_ctim = st->st_ctim.tv_sec; -} -#endif - - -static void -bsd_to_svr4_xstat(st, st4) - struct stat *st; - struct svr4_xstat *st4; -{ - memset(st4, 0, sizeof(*st4)); - st4->st_dev = bsd_to_svr4_dev_t(st->st_dev); - st4->st_ino = st->st_ino; - st4->st_mode = BSD_TO_SVR4_MODE(st->st_mode); - st4->st_nlink = st->st_nlink; - st4->st_uid = st->st_uid; - st4->st_gid = st->st_gid; - st4->st_rdev = bsd_to_svr4_dev_t(st->st_rdev); - st4->st_size = st->st_size; - st4->st_atim = st->st_atim; - st4->st_mtim = st->st_mtim; - st4->st_ctim = st->st_ctim; - st4->st_blksize = st->st_blksize; - st4->st_blocks = st->st_blocks; - strcpy(st4->st_fstype, "unknown"); -} - - -static void -bsd_to_svr4_stat64(st, st4) - struct stat *st; - struct svr4_stat64 *st4; -{ - memset(st4, 0, sizeof(*st4)); - st4->st_dev = bsd_to_svr4_dev_t(st->st_dev); - st4->st_ino = st->st_ino; - st4->st_mode = BSD_TO_SVR4_MODE(st->st_mode); - st4->st_nlink = st->st_nlink; - st4->st_uid = st->st_uid; - st4->st_gid = st->st_gid; - st4->st_rdev = bsd_to_svr4_dev_t(st->st_rdev); - st4->st_size = st->st_size; - st4->st_atim = st->st_atim; - st4->st_mtim = st->st_mtim; - st4->st_ctim = st->st_ctim; - st4->st_blksize = st->st_blksize; - st4->st_blocks = st->st_blocks; - strcpy(st4->st_fstype, "unknown"); -} - -int -svr4_sys_stat(td, uap) - struct thread *td; - struct svr4_sys_stat_args *uap; -{ - struct svr4_stat svr4_st; - struct stat st; - char *path; - int error; - - CHECKALTEXIST(td, uap->path, &path); - - error = kern_statat(td, 0, AT_FDCWD, path, UIO_SYSSPACE, &st, NULL); - free(path, M_TEMP); - if (error) - return (error); - bsd_to_svr4_stat(&st, &svr4_st); - - if (S_ISSOCK(st.st_mode)) - (void) svr4_add_socket(td, uap->path, &st); - - return (copyout(&svr4_st, uap->ub, sizeof svr4_st)); -} - - -int -svr4_sys_lstat(td, uap) - struct thread *td; - struct svr4_sys_lstat_args *uap; -{ - struct svr4_stat svr4_st; - struct stat st; - char *path; - int error; - - CHECKALTEXIST(td, uap->path, &path); - - error = kern_statat(td, AT_SYMLINK_NOFOLLOW, AT_FDCWD, path, - UIO_SYSSPACE, &st, NULL); - free(path, M_TEMP); - if (error) - return (error); - bsd_to_svr4_stat(&st, &svr4_st); - - if (S_ISSOCK(st.st_mode)) - (void) svr4_add_socket(td, uap->path, &st); - - return (copyout(&svr4_st, uap->ub, sizeof svr4_st)); -} - - -int -svr4_sys_fstat(td, uap) - struct thread *td; - struct svr4_sys_fstat_args *uap; -{ - struct svr4_stat svr4_st; - struct stat st; - int error; - - - error = kern_fstat(td, uap->fd, &st); - if (error) - return (error); - bsd_to_svr4_stat(&st, &svr4_st); - return (copyout(&svr4_st, uap->sb, sizeof svr4_st)); -} - - -int -svr4_sys_xstat(td, uap) - struct thread *td; - struct svr4_sys_xstat_args *uap; -{ - struct svr4_xstat svr4_st; - struct stat st; - char *path; - int error; - - CHECKALTEXIST(td, uap->path, &path); - - error = kern_statat(td, 0, AT_FDCWD, path, UIO_SYSSPACE, &st, NULL); - free(path, M_TEMP); - if (error) - return (error); - - bsd_to_svr4_xstat(&st, &svr4_st); - -#if defined(SOCKET_NOTYET) - if (S_ISSOCK(st.st_mode)) - (void) svr4_add_socket(td, uap->path, &st); -#endif - - return (copyout(&svr4_st, uap->ub, sizeof svr4_st)); -} - -int -svr4_sys_lxstat(td, uap) - struct thread *td; - struct svr4_sys_lxstat_args *uap; -{ - struct svr4_xstat svr4_st; - struct stat st; - char *path; - int error; - - CHECKALTEXIST(td, uap->path, &path); - - error = kern_statat(td, AT_SYMLINK_NOFOLLOW, AT_FDCWD, path, - UIO_SYSSPACE, &st, NULL); - free(path, M_TEMP); - if (error) - return (error); - - bsd_to_svr4_xstat(&st, &svr4_st); - -#if defined(SOCKET_NOTYET) - if (S_ISSOCK(st.st_mode)) - (void) svr4_add_socket(td, uap->path, &st); -#endif - return (copyout(&svr4_st, uap->ub, sizeof svr4_st)); -} - - -int -svr4_sys_fxstat(td, uap) - struct thread *td; - struct svr4_sys_fxstat_args *uap; -{ - struct svr4_xstat svr4_st; - struct stat st; - int error; - - - error = kern_fstat(td, uap->fd, &st); - if (error) - return (error); - bsd_to_svr4_xstat(&st, &svr4_st); - return (copyout(&svr4_st, uap->sb, sizeof svr4_st)); -} - -int -svr4_sys_stat64(td, uap) - struct thread *td; - struct svr4_sys_stat64_args *uap; -{ - struct svr4_stat64 svr4_st; - struct stat st; - char *path; - int error; - - CHECKALTEXIST(td, uap->path, &path); - - error = kern_statat(td, 0, AT_FDCWD, path, UIO_SYSSPACE, &st, NULL); - free(path, M_TEMP); - if (error) - return (error); - - bsd_to_svr4_stat64(&st, &svr4_st); - - if (S_ISSOCK(st.st_mode)) - (void) svr4_add_socket(td, uap->path, &st); - - return (copyout(&svr4_st, uap->sb, sizeof svr4_st)); -} - - -int -svr4_sys_lstat64(td, uap) - struct thread *td; - struct svr4_sys_lstat64_args *uap; -{ - struct svr4_stat64 svr4_st; - struct stat st; - char *path; - int error; - - CHECKALTEXIST(td, uap->path, &path); - - error = kern_statat(td, AT_SYMLINK_NOFOLLOW, AT_FDCWD, path, - UIO_SYSSPACE, &st, NULL); - free(path, M_TEMP); - if (error) - return (error); - - bsd_to_svr4_stat64(&st, &svr4_st); - - if (S_ISSOCK(st.st_mode)) - (void) svr4_add_socket(td, uap->path, &st); - - return (copyout(&svr4_st, uap->sb, sizeof svr4_st)); -} - - -int -svr4_sys_fstat64(td, uap) - struct thread *td; - struct svr4_sys_fstat64_args *uap; -{ - struct svr4_stat64 svr4_st; - struct stat st; - int error; - - error = kern_fstat(td, uap->fd, &st); - if (error) - return (error); - bsd_to_svr4_stat64(&st, &svr4_st); - return (copyout(&svr4_st, uap->sb, sizeof svr4_st)); -} - - -int -svr4_ustat(td, uap) - struct thread *td; - struct svr4_ustat_args *uap; -{ - struct svr4_ustat us; - int error; - - memset(&us, 0, sizeof us); - - /* - * XXX: should set f_tfree and f_tinode at least - * How do we translate dev -> fstat? (and then to svr4_ustat) - */ - if ((error = copyout(&us, uap->name, sizeof us)) != 0) - return (error); - - return 0; -} - -/*extern char ostype[], osrelease[], version[], machine[];*/ - -int -svr4_sys_uname(td, uap) - struct thread *td; - struct svr4_sys_uname_args *uap; -{ - struct svr4_utsname sut; - - memset(&sut, 0, sizeof(sut)); - - strlcpy(sut.sysname, ostype, sizeof(sut.sysname)); - getcredhostname(td->td_ucred, sut.nodename, sizeof(sut.nodename)); - strlcpy(sut.release, osrelease, sizeof(sut.release)); - strlcpy(sut.version, version, sizeof(sut.version)); - strlcpy(sut.machine, machine, sizeof(sut.machine)); - - return copyout((caddr_t) &sut, (caddr_t) uap->name, - sizeof(struct svr4_utsname)); -} - -int -svr4_sys_systeminfo(td, uap) - struct thread *td; - struct svr4_sys_systeminfo_args *uap; -{ - char *str = NULL; - int error = 0; - register_t *retval = td->td_retval; - u_long hostid; - size_t len = 0; - char buf[MAXHOSTNAMELEN]; - u_int rlen = uap->len; - - switch (uap->what) { - case SVR4_SI_SYSNAME: - str = ostype; - break; - - case SVR4_SI_HOSTNAME: - getcredhostname(td->td_ucred, buf, sizeof(buf)); - str = buf; - break; - - case SVR4_SI_RELEASE: - str = osrelease; - break; - - case SVR4_SI_VERSION: - str = version; - break; - - case SVR4_SI_MACHINE: - str = machine; - break; - - case SVR4_SI_ARCHITECTURE: - str = machine; - break; - - case SVR4_SI_ISALIST: -#if defined(__sparc__) - str = "sparcv9 sparcv9-fsmuld sparcv8 sparcv8-fsmuld sparcv7 sparc"; -#elif defined(__i386__) - str = "i386"; -#elif defined(__amd64__) - str = "amd64"; -#else - str = "unknown"; -#endif - break; - - case SVR4_SI_HW_SERIAL: - getcredhostid(td->td_ucred, &hostid); - snprintf(buf, sizeof(buf), "%lu", hostid); - str = buf; - break; - - case SVR4_SI_HW_PROVIDER: - str = ostype; - break; - - case SVR4_SI_SRPC_DOMAIN: - getcreddomainname(td->td_ucred, buf, sizeof(buf)); - str = buf; - break; - - case SVR4_SI_PLATFORM: -#if defined(__i386__) - str = "i86pc"; -#else - str = "unknown"; -#endif - break; - - case SVR4_SI_KERB_REALM: - str = "unsupported"; - break; -#if defined(WHY_DOES_AN_EMULATOR_WANT_TO_SET_HOSTNAMES) - case SVR4_SI_SET_HOSTNAME: - name = KERN_HOSTNAME; - return kern_sysctl(&name, 1, 0, 0, uap->buf, rlen, td); - - case SVR4_SI_SET_SRPC_DOMAIN: - name = KERN_NISDOMAINNAME; - return kern_sysctl(&name, 1, 0, 0, uap->buf, rlen, td); -#else - case SVR4_SI_SET_HOSTNAME: - case SVR4_SI_SET_SRPC_DOMAIN: - /* FALLTHROUGH */ -#endif - case SVR4_SI_SET_KERB_REALM: - return 0; - - default: - DPRINTF(("Bad systeminfo command %d\n", uap->what)); - return ENOSYS; - } - - if (str) { - len = strlen(str) + 1; - if (len > rlen) - len = rlen; - - if (uap->buf) { - error = copyout(str, uap->buf, len); - if (error) - return error; - /* make sure we are NULL terminated */ - buf[0] = '\0'; - error = copyout(buf, &(uap->buf[len - 1]), 1); - } - else - error = 0; - } - /* XXX NetBSD has hostname setting stuff here. Why would an emulator - want to do that? */ - - *retval = len; - return error; -} - -int -svr4_sys_utssys(td, uap) - struct thread *td; - struct svr4_sys_utssys_args *uap; -{ - switch (uap->sel) { - case 0: /* uname(2) */ - { - struct svr4_sys_uname_args ua; - ua.name = uap->a1; - return svr4_sys_uname(td, &ua); - } - - case 2: /* ustat(2) */ - { - struct svr4_ustat_args ua; - ua.dev = (svr4_dev_t) uap->a2; - ua.name = uap->a1; - return svr4_ustat(td, &ua); - } - - case 3: /* fusers(2) */ - return ENOSYS; - - default: - return ENOSYS; - } - return ENOSYS; -} - - -int -svr4_sys_utime(td, uap) - struct thread *td; - struct svr4_sys_utime_args *uap; -{ - struct svr4_utimbuf ub; - struct timeval tbuf[2], *tp; - char *path; - int error; - - if (uap->ubuf != NULL) { - error = copyin(uap->ubuf, &ub, sizeof(ub)); - if (error) - return (error); - tbuf[0].tv_sec = ub.actime; - tbuf[0].tv_usec = 0; - tbuf[1].tv_sec = ub.modtime; - tbuf[1].tv_usec = 0; - tp = tbuf; - } else - tp = NULL; - - CHECKALTEXIST(td, uap->path, &path); - error = kern_utimesat(td, AT_FDCWD, path, UIO_SYSSPACE, - tp, UIO_SYSSPACE); - free(path, M_TEMP); - return (error); -} - - -int -svr4_sys_utimes(td, uap) - struct thread *td; - struct svr4_sys_utimes_args *uap; -{ - char *path; - int error; - - CHECKALTEXIST(td, uap->path, &path); - error = kern_utimesat(td, AT_FDCWD, path, UIO_SYSSPACE, - uap->tptr, UIO_USERSPACE); - free(path, M_TEMP); - return (error); -} - -static int -svr4_to_bsd_pathconf(name) - int name; -{ - switch (name) { - case SVR4_PC_LINK_MAX: - return _PC_LINK_MAX; - - case SVR4_PC_MAX_CANON: - return _PC_MAX_CANON; - - case SVR4_PC_MAX_INPUT: - return _PC_MAX_INPUT; - - case SVR4_PC_NAME_MAX: - return _PC_NAME_MAX; - - case SVR4_PC_PATH_MAX: - return _PC_PATH_MAX; - - case SVR4_PC_PIPE_BUF: - return _PC_PIPE_BUF; - - case SVR4_PC_NO_TRUNC: - return _PC_NO_TRUNC; - - case SVR4_PC_VDISABLE: - return _PC_VDISABLE; - - case SVR4_PC_CHOWN_RESTRICTED: - return _PC_CHOWN_RESTRICTED; - case SVR4_PC_SYNC_IO: -#if defined(_PC_SYNC_IO) - return _PC_SYNC_IO; -#else - return 0; -#endif - case SVR4_PC_ASYNC_IO: - case SVR4_PC_PRIO_IO: - /* Not supported */ - return 0; - - default: - /* Invalid */ - return -1; - } -} - - -int -svr4_sys_pathconf(td, uap) - struct thread *td; - struct svr4_sys_pathconf_args *uap; -{ - char *path; - int error, name; - - name = svr4_to_bsd_pathconf(uap->name); - - switch (name) { - case -1: - td->td_retval[0] = -1; - return (EINVAL); - case 0: - td->td_retval[0] = 0; - return (0); - default: - CHECKALTEXIST(td, uap->path, &path); - error = kern_pathconf(td, path, UIO_SYSSPACE, name, FOLLOW); - free(path, M_TEMP); - return (error); - } -} - - -int -svr4_sys_fpathconf(td, uap) - struct thread *td; - struct svr4_sys_fpathconf_args *uap; -{ - register_t *retval = td->td_retval; - - uap->name = svr4_to_bsd_pathconf(uap->name); - - switch (uap->name) { - case -1: - *retval = -1; - return EINVAL; - case 0: - *retval = 0; - return 0; - default: - return sys_fpathconf(td, (struct fpathconf_args *)uap); - } -} diff --git a/sys/compat/svr4/svr4_stat.h b/sys/compat/svr4/svr4_stat.h deleted file mode 100644 index b7ae117a3c0..00000000000 --- a/sys/compat/svr4/svr4_stat.h +++ /dev/null @@ -1,105 +0,0 @@ -/*- - * Copyright (c) 1998 Mark Newton - * Copyright (c) 1994 Christos Zoulas - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * $FreeBSD: stable/11/sys/compat/svr4/svr4_stat.h 139743 2005-01-05 22:34:37Z imp $ - */ - -#ifndef _SVR4_STAT_H_ -#define _SVR4_STAT_H_ - -#include -#include - -struct svr4_stat { - svr4_o_dev_t st_dev; - svr4_o_ino_t st_ino; - svr4_o_mode_t st_mode; - svr4_o_nlink_t st_nlink; - svr4_o_uid_t st_uid; - svr4_o_gid_t st_gid; - svr4_o_dev_t st_rdev; - svr4_off_t st_size; - svr4_time_t st_atim; - svr4_time_t st_mtim; - svr4_time_t st_ctim; -}; - -struct svr4_xstat { - svr4_dev_t st_dev; - long st_pad1[3]; - svr4_ino_t st_ino; - svr4_mode_t st_mode; - svr4_nlink_t st_nlink; - svr4_uid_t st_uid; - svr4_gid_t st_gid; - svr4_dev_t st_rdev; - long st_pad2[2]; - svr4_off_t st_size; - long st_pad3; - svr4_timestruc_t st_atim; - svr4_timestruc_t st_mtim; - svr4_timestruc_t st_ctim; - long st_blksize; - svr4_blkcnt_t st_blocks; - char st_fstype[16]; - long st_pad4[8]; -}; - -struct svr4_stat64 { - svr4_dev_t st_dev; - long st_pad1[3]; - svr4_ino64_t st_ino; - svr4_mode_t st_mode; - svr4_nlink_t st_nlink; - svr4_uid_t st_uid; - svr4_gid_t st_gid; - svr4_dev_t st_rdev; - long st_pad2[2]; - svr4_off64_t st_size; - svr4_timestruc_t st_atim; - svr4_timestruc_t st_mtim; - svr4_timestruc_t st_ctim; - long st_blksize; - svr4_blkcnt64_t st_blocks; - char st_fstype[16]; - long st_pad4[8]; -}; - -#define SVR4_PC_LINK_MAX 1 -#define SVR4_PC_MAX_CANON 2 -#define SVR4_PC_MAX_INPUT 3 -#define SVR4_PC_NAME_MAX 4 -#define SVR4_PC_PATH_MAX 5 -#define SVR4_PC_PIPE_BUF 6 -#define SVR4_PC_NO_TRUNC 7 -#define SVR4_PC_VDISABLE 8 -#define SVR4_PC_CHOWN_RESTRICTED 9 -#define SVR4_PC_ASYNC_IO 10 -#define SVR4_PC_PRIO_IO 11 -#define SVR4_PC_SYNC_IO 12 - -#endif /* !_SVR4_STAT_H_ */ diff --git a/sys/compat/svr4/svr4_statvfs.h b/sys/compat/svr4/svr4_statvfs.h deleted file mode 100644 index 542fecaa2ae..00000000000 --- a/sys/compat/svr4/svr4_statvfs.h +++ /dev/null @@ -1,72 +0,0 @@ -/*- - * Copyright (c) 1998 Mark Newton - * Copyright (c) 1994 Christos Zoulas - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * $FreeBSD: stable/11/sys/compat/svr4/svr4_statvfs.h 139743 2005-01-05 22:34:37Z imp $ - */ - -#ifndef _SVR4_STATVFS_H_ -#define _SVR4_STATVFS_H_ - -typedef struct svr4_statvfs { - u_long f_bsize; - u_long f_frsize; - svr4_fsblkcnt_t f_blocks; - svr4_fsblkcnt_t f_bfree; - svr4_fsblkcnt_t f_bavail; - svr4_fsblkcnt_t f_files; - svr4_fsblkcnt_t f_ffree; - svr4_fsblkcnt_t f_favail; - u_long f_fsid; - char f_basetype[16]; - u_long f_flag; - u_long f_namemax; - char f_fstr[32]; - u_long f_filler[16]; -} svr4_statvfs_t; - -typedef struct svr4_statvfs64 { - u_long f_bsize; - u_long f_frsize; - svr4_fsblkcnt64_t f_blocks; - svr4_fsblkcnt64_t f_bfree; - svr4_fsblkcnt64_t f_bavail; - svr4_fsblkcnt64_t f_files; - svr4_fsblkcnt64_t f_ffree; - svr4_fsblkcnt64_t f_favail; - u_long f_fsid; - char f_basetype[16]; - u_long f_flag; - u_long f_namemax; - char f_fstr[32]; - u_long f_filler[16]; -} svr4_statvfs64_t; - -#define SVR4_ST_RDONLY 0x01 -#define SVR4_ST_NOSUID 0x02 -#define SVR4_ST_NOTRUNC 0x04 - -#endif /* !_SVR4_STATVFS_H_ */ diff --git a/sys/compat/svr4/svr4_stream.c b/sys/compat/svr4/svr4_stream.c deleted file mode 100644 index cc91eeca118..00000000000 --- a/sys/compat/svr4/svr4_stream.c +++ /dev/null @@ -1,2042 +0,0 @@ -/*- - * Copyright (c) 1998 Mark Newton. All rights reserved. - * Copyright (c) 1994, 1996 Christos Zoulas. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by Christos Zoulas. - * 4. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/* - * Pretend that we have streams... - * Yes, this is gross. - * - * ToDo: The state machine for getmsg needs re-thinking - */ - -#include - -#include "opt_compat.h" -#include "opt_ktrace.h" - -#include -#include -#include -#include -#include -#include -#include -#include -#include /* Must come after sys/malloc.h */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include /* Must come after sys/uio.h */ -#include - -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* Utils */ -static int clean_pipe(struct thread *, char *); -static void getparm(struct file *, struct svr4_si_sockparms *); -static int svr4_do_putmsg(struct thread *, struct svr4_sys_putmsg_args *, - struct file *); -static int svr4_do_getmsg(struct thread *, struct svr4_sys_getmsg_args *, - struct file *); - -/* Address Conversions */ -static void sockaddr_to_netaddr_in(struct svr4_strmcmd *, - const struct sockaddr_in *); -static void sockaddr_to_netaddr_un(struct svr4_strmcmd *, - const struct sockaddr_un *); -static void netaddr_to_sockaddr_in(struct sockaddr_in *, - const struct svr4_strmcmd *); -static void netaddr_to_sockaddr_un(struct sockaddr_un *, - const struct svr4_strmcmd *); - -/* stream ioctls */ -static int i_nread(struct file *, struct thread *, register_t *, int, - u_long, caddr_t); -static int i_fdinsert(struct file *, struct thread *, register_t *, int, - u_long, caddr_t); -static int i_str(struct file *, struct thread *, register_t *, int, - u_long, caddr_t); -static int i_setsig(struct file *, struct thread *, register_t *, int, - u_long, caddr_t); -static int i_getsig(struct file *, struct thread *, register_t *, int, - u_long, caddr_t); -static int _i_bind_rsvd(struct file *, struct thread *, register_t *, int, - u_long, caddr_t); -static int _i_rele_rsvd(struct file *, struct thread *, register_t *, int, - u_long, caddr_t); - -/* i_str sockmod calls */ -static int sockmod(struct file *, int, struct svr4_strioctl *, - struct thread *); -static int si_listen(struct file *, int, struct svr4_strioctl *, - struct thread *); -static int si_ogetudata(struct file *, int, struct svr4_strioctl *, - struct thread *); -static int si_sockparams(struct file *, int, struct svr4_strioctl *, - struct thread *); -static int si_shutdown (struct file *, int, struct svr4_strioctl *, - struct thread *); -static int si_getudata(struct file *, int, struct svr4_strioctl *, - struct thread *); - -/* i_str timod calls */ -static int timod(struct file *, int, struct svr4_strioctl *, struct thread *); -static int ti_getinfo(struct file *, int, struct svr4_strioctl *, - struct thread *); -static int ti_bind(struct file *, int, struct svr4_strioctl *, struct thread *); - -#ifdef DEBUG_SVR4 -static void bufprint(u_char *, size_t); -static int show_ioc(const char *, struct svr4_strioctl *); -static int show_strbuf(struct svr4_strbuf *); -static void show_msg(const char *, int, struct svr4_strbuf *, - struct svr4_strbuf *, int); - -static void -bufprint(buf, len) - u_char *buf; - size_t len; -{ - size_t i; - - uprintf("\n\t"); - for (i = 0; i < len; i++) { - uprintf("%x ", buf[i]); - if (i && (i % 16) == 0) - uprintf("\n\t"); - } -} - -static int -show_ioc(str, ioc) - const char *str; - struct svr4_strioctl *ioc; -{ - u_char *ptr = NULL; - int len; - int error; - - len = ioc->len; - if (len > 1024) - len = 1024; - - if (len > 0) { - ptr = (u_char *) malloc(len, M_TEMP, M_WAITOK); - if ((error = copyin(ioc->buf, ptr, len)) != 0) { - free((char *) ptr, M_TEMP); - return error; - } - } - - uprintf("%s cmd = %ld, timeout = %d, len = %d, buf = %p { ", - str, ioc->cmd, ioc->timeout, ioc->len, ioc->buf); - - if (ptr != NULL) - bufprint(ptr, len); - - uprintf("}\n"); - - if (ptr != NULL) - free((char *) ptr, M_TEMP); - return 0; -} - - -static int -show_strbuf(str) - struct svr4_strbuf *str; -{ - int error; - u_char *ptr = NULL; - int maxlen = str->maxlen; - int len = str->len; - - if (maxlen > 8192) - maxlen = 8192; - - if (maxlen < 0) - maxlen = 0; - - if (len >= maxlen) - len = maxlen; - - if (len > 0) { - ptr = (u_char *) malloc(len, M_TEMP, M_WAITOK); - - if ((error = copyin(str->buf, ptr, len)) != 0) { - free((char *) ptr, M_TEMP); - return error; - } - } - - uprintf(", { %d, %d, %p=[ ", str->maxlen, str->len, str->buf); - - if (ptr) - bufprint(ptr, len); - - uprintf("]}"); - - if (ptr) - free((char *) ptr, M_TEMP); - - return 0; -} - - -static void -show_msg(str, fd, ctl, dat, flags) - const char *str; - int fd; - struct svr4_strbuf *ctl; - struct svr4_strbuf *dat; - int flags; -{ - struct svr4_strbuf buf; - int error; - - uprintf("%s(%d", str, fd); - if (ctl != NULL) { - if ((error = copyin(ctl, &buf, sizeof(buf))) != 0) - return; - show_strbuf(&buf); - } - else - uprintf(", NULL"); - - if (dat != NULL) { - if ((error = copyin(dat, &buf, sizeof(buf))) != 0) - return; - show_strbuf(&buf); - } - else - uprintf(", NULL"); - - uprintf(", %x);\n", flags); -} - -#endif /* DEBUG_SVR4 */ - -/* - * We are faced with an interesting situation. On svr4 unix sockets - * are really pipes. But we really have sockets, and we might as - * well use them. At the point where svr4 calls TI_BIND, it has - * already created a named pipe for the socket using mknod(2). - * We need to create a socket with the same name when we bind, - * so we need to remove the pipe before, otherwise we'll get address - * already in use. So we *carefully* remove the pipe, to avoid - * using this as a random file removal tool. We use system calls - * to avoid code duplication. - */ -static int -clean_pipe(td, path) - struct thread *td; - char *path; -{ - struct stat st; - int error; - - error = kern_statat(td, AT_SYMLINK_NOFOLLOW, AT_FDCWD, path, - UIO_SYSSPACE, &st, NULL); - - /* - * Make sure we are dealing with a mode 0 named pipe. - */ - if ((st.st_mode & S_IFMT) != S_IFIFO) - return (0); - - if ((st.st_mode & ALLPERMS) != 0) - return (0); - - error = kern_unlinkat(td, AT_FDCWD, path, UIO_SYSSPACE, 0); - if (error) - DPRINTF(("clean_pipe: unlink failed %d\n", error)); - return (error); -} - - -static void -sockaddr_to_netaddr_in(sc, sain) - struct svr4_strmcmd *sc; - const struct sockaddr_in *sain; -{ - struct svr4_netaddr_in *na; - na = SVR4_ADDROF(sc); - - na->family = sain->sin_family; - na->port = sain->sin_port; - na->addr = sain->sin_addr.s_addr; - DPRINTF(("sockaddr_in -> netaddr %d %d %lx\n", na->family, na->port, - na->addr)); -} - - -static void -sockaddr_to_netaddr_un(sc, saun) - struct svr4_strmcmd *sc; - const struct sockaddr_un *saun; -{ - struct svr4_netaddr_un *na; - char *dst, *edst = ((char *) sc) + sc->offs + sizeof(na->family) + 1 - - sizeof(*sc); - const char *src; - - na = SVR4_ADDROF(sc); - na->family = saun->sun_family; - for (src = saun->sun_path, dst = na->path; (*dst++ = *src++) != '\0'; ) - if (dst == edst) - break; - DPRINTF(("sockaddr_un -> netaddr %d %s\n", na->family, na->path)); -} - - -static void -netaddr_to_sockaddr_in(sain, sc) - struct sockaddr_in *sain; - const struct svr4_strmcmd *sc; -{ - const struct svr4_netaddr_in *na; - - - na = SVR4_C_ADDROF(sc); - memset(sain, 0, sizeof(*sain)); - sain->sin_len = sizeof(*sain); - sain->sin_family = na->family; - sain->sin_port = na->port; - sain->sin_addr.s_addr = na->addr; - DPRINTF(("netaddr -> sockaddr_in %d %d %x\n", sain->sin_family, - sain->sin_port, sain->sin_addr.s_addr)); -} - - -static void -netaddr_to_sockaddr_un(saun, sc) - struct sockaddr_un *saun; - const struct svr4_strmcmd *sc; -{ - const struct svr4_netaddr_un *na; - char *dst, *edst = &saun->sun_path[sizeof(saun->sun_path) - 1]; - const char *src; - - na = SVR4_C_ADDROF(sc); - memset(saun, 0, sizeof(*saun)); - saun->sun_family = na->family; - for (src = na->path, dst = saun->sun_path; (*dst++ = *src++) != '\0'; ) - if (dst == edst) - break; - saun->sun_len = dst - saun->sun_path; - DPRINTF(("netaddr -> sockaddr_un %d %s\n", saun->sun_family, - saun->sun_path)); -} - - -static void -getparm(fp, pa) - struct file *fp; - struct svr4_si_sockparms *pa; -{ - struct svr4_strm *st; - struct socket *so; - - st = svr4_stream_get(fp); - if (st == NULL) - return; - - so = fp->f_data; - - pa->family = st->s_family; - - switch (so->so_type) { - case SOCK_DGRAM: - pa->type = SVR4_T_CLTS; - pa->protocol = IPPROTO_UDP; - DPRINTF(("getparm(dgram)\n")); - return; - - case SOCK_STREAM: - pa->type = SVR4_T_COTS; /* What about T_COTS_ORD? XXX */ - pa->protocol = IPPROTO_IP; - DPRINTF(("getparm(stream)\n")); - return; - - case SOCK_RAW: - pa->type = SVR4_T_CLTS; - pa->protocol = IPPROTO_RAW; - DPRINTF(("getparm(raw)\n")); - return; - - default: - pa->type = 0; - pa->protocol = 0; - DPRINTF(("getparm(type %d?)\n", so->so_type)); - return; - } -} - - -static int -si_ogetudata(fp, fd, ioc, td) - struct file *fp; - int fd; - struct svr4_strioctl *ioc; - struct thread *td; -{ - int error; - struct svr4_si_oudata ud; - struct svr4_si_sockparms pa; - - if (ioc->len != sizeof(ud) && ioc->len != sizeof(ud) - sizeof(int)) { - DPRINTF(("SI_OGETUDATA: Wrong size %d != %d\n", - sizeof(ud), ioc->len)); - return EINVAL; - } - - if ((error = copyin(ioc->buf, &ud, sizeof(ud))) != 0) - return error; - - getparm(fp, &pa); - - switch (pa.family) { - case AF_INET: - ud.tidusize = 16384; - ud.addrsize = sizeof(struct svr4_sockaddr_in); - if (pa.type == SVR4_SOCK_STREAM) - ud.etsdusize = 1; - else - ud.etsdusize = 0; - break; - - case AF_LOCAL: - ud.tidusize = 65536; - ud.addrsize = 128; - ud.etsdusize = 128; - break; - - default: - DPRINTF(("SI_OGETUDATA: Unsupported address family %d\n", - pa.family)); - return ENOSYS; - } - - /* I have no idea what these should be! */ - ud.optsize = 128; - ud.tsdusize = 128; - - ud.servtype = pa.type; - - /* XXX: Fixme */ - ud.so_state = 0; - ud.so_options = 0; - return copyout(&ud, ioc->buf, ioc->len); -} - - -static int -si_sockparams(fp, fd, ioc, td) - struct file *fp; - int fd; - struct svr4_strioctl *ioc; - struct thread *td; -{ - struct svr4_si_sockparms pa; - - getparm(fp, &pa); - return copyout(&pa, ioc->buf, sizeof(pa)); -} - - -static int -si_listen(fp, fd, ioc, td) - struct file *fp; - int fd; - struct svr4_strioctl *ioc; - struct thread *td; -{ - int error; - struct svr4_strm *st = svr4_stream_get(fp); - struct svr4_strmcmd lst; - struct listen_args la; - - if (st == NULL) - return EINVAL; - - if (ioc->len < 0 || ioc->len > sizeof(lst)) - return EINVAL; - - if ((error = copyin(ioc->buf, &lst, ioc->len)) != 0) - return error; - - if (lst.cmd != SVR4_TI_OLD_BIND_REQUEST) { - DPRINTF(("si_listen: bad request %ld\n", lst.cmd)); - return EINVAL; - } - - /* - * We are making assumptions again... - */ - la.s = fd; - DPRINTF(("SI_LISTEN: fileno %d backlog = %d\n", fd, 5)); - la.backlog = 5; - - if ((error = sys_listen(td, &la)) != 0) { - DPRINTF(("SI_LISTEN: listen failed %d\n", error)); - return error; - } - - st->s_cmd = SVR4_TI__ACCEPT_WAIT; - lst.cmd = SVR4_TI_BIND_REPLY; - - switch (st->s_family) { - case AF_INET: - /* XXX: Fill the length here */ - break; - - case AF_LOCAL: - lst.len = 140; - lst.pad[28] = 0x00000000; /* magic again */ - lst.pad[29] = 0x00000800; /* magic again */ - lst.pad[30] = 0x80001400; /* magic again */ - break; - - default: - DPRINTF(("SI_LISTEN: Unsupported address family %d\n", - st->s_family)); - return ENOSYS; - } - - - if ((error = copyout(&lst, ioc->buf, ioc->len)) != 0) - return error; - - return 0; -} - - -static int -si_getudata(fp, fd, ioc, td) - struct file *fp; - int fd; - struct svr4_strioctl *ioc; - struct thread *td; -{ - int error; - struct svr4_si_udata ud; - - if (sizeof(ud) != ioc->len) { - DPRINTF(("SI_GETUDATA: Wrong size %d != %d\n", - sizeof(ud), ioc->len)); - return EINVAL; - } - - if ((error = copyin(ioc->buf, &ud, sizeof(ud))) != 0) - return error; - - getparm(fp, &ud.sockparms); - - switch (ud.sockparms.family) { - case AF_INET: - DPRINTF(("getudata_inet\n")); - ud.tidusize = 16384; - ud.tsdusize = 16384; - ud.addrsize = sizeof(struct svr4_sockaddr_in); - if (ud.sockparms.type == SVR4_SOCK_STREAM) - ud.etsdusize = 1; - else - ud.etsdusize = 0; - ud.optsize = 0; - break; - - case AF_LOCAL: - DPRINTF(("getudata_local\n")); - ud.tidusize = 65536; - ud.tsdusize = 128; - ud.addrsize = 128; - ud.etsdusize = 128; - ud.optsize = 128; - break; - - default: - DPRINTF(("SI_GETUDATA: Unsupported address family %d\n", - ud.sockparms.family)); - return ENOSYS; - } - - - ud.servtype = ud.sockparms.type; - DPRINTF(("ud.servtype = %d\n", ud.servtype)); - /* XXX: Fixme */ - ud.so_state = 0; - ud.so_options = 0; - return copyout(&ud, ioc->buf, sizeof(ud)); -} - - -static int -si_shutdown(fp, fd, ioc, td) - struct file *fp; - int fd; - struct svr4_strioctl *ioc; - struct thread *td; -{ - int error; - struct shutdown_args ap; - - if (ioc->len != sizeof(ap.how)) { - DPRINTF(("SI_SHUTDOWN: Wrong size %d != %d\n", - sizeof(ap.how), ioc->len)); - return EINVAL; - } - - if ((error = copyin(ioc->buf, &ap.how, ioc->len)) != 0) - return error; - - ap.s = fd; - - return sys_shutdown(td, &ap); -} - - -static int -sockmod(fp, fd, ioc, td) - struct file *fp; - int fd; - struct svr4_strioctl *ioc; - struct thread *td; -{ - switch (ioc->cmd) { - case SVR4_SI_OGETUDATA: - DPRINTF(("SI_OGETUDATA\n")); - return si_ogetudata(fp, fd, ioc, td); - - case SVR4_SI_SHUTDOWN: - DPRINTF(("SI_SHUTDOWN\n")); - return si_shutdown(fp, fd, ioc, td); - - case SVR4_SI_LISTEN: - DPRINTF(("SI_LISTEN\n")); - return si_listen(fp, fd, ioc, td); - - case SVR4_SI_SETMYNAME: - DPRINTF(("SI_SETMYNAME\n")); - return 0; - - case SVR4_SI_SETPEERNAME: - DPRINTF(("SI_SETPEERNAME\n")); - return 0; - - case SVR4_SI_GETINTRANSIT: - DPRINTF(("SI_GETINTRANSIT\n")); - return 0; - - case SVR4_SI_TCL_LINK: - DPRINTF(("SI_TCL_LINK\n")); - return 0; - - case SVR4_SI_TCL_UNLINK: - DPRINTF(("SI_TCL_UNLINK\n")); - return 0; - - case SVR4_SI_SOCKPARAMS: - DPRINTF(("SI_SOCKPARAMS\n")); - return si_sockparams(fp, fd, ioc, td); - - case SVR4_SI_GETUDATA: - DPRINTF(("SI_GETUDATA\n")); - return si_getudata(fp, fd, ioc, td); - - default: - DPRINTF(("Unknown sockmod ioctl %lx\n", ioc->cmd)); - return 0; - - } -} - - -static int -ti_getinfo(fp, fd, ioc, td) - struct file *fp; - int fd; - struct svr4_strioctl *ioc; - struct thread *td; -{ - int error; - struct svr4_infocmd info; - - memset(&info, 0, sizeof(info)); - - if (ioc->len < 0 || ioc->len > sizeof(info)) - return EINVAL; - - if ((error = copyin(ioc->buf, &info, ioc->len)) != 0) - return error; - - if (info.cmd != SVR4_TI_INFO_REQUEST) - return EINVAL; - - info.cmd = SVR4_TI_INFO_REPLY; - info.tsdu = 0; - info.etsdu = 1; - info.cdata = -2; - info.ddata = -2; - info.addr = 16; - info.opt = -1; - info.tidu = 16384; - info.serv = 2; - info.current = 0; - info.provider = 2; - - ioc->len = sizeof(info); - if ((error = copyout(&info, ioc->buf, ioc->len)) != 0) - return error; - - return 0; -} - - -static int -ti_bind(fp, fd, ioc, td) - struct file *fp; - int fd; - struct svr4_strioctl *ioc; - struct thread *td; -{ - int error; - struct svr4_strm *st = svr4_stream_get(fp); - struct sockaddr_in sain; - struct sockaddr_un saun; - struct sockaddr *skp; - int sasize; - struct svr4_strmcmd bnd; - - if (st == NULL) { - DPRINTF(("ti_bind: bad file descriptor\n")); - return EINVAL; - } - - if (ioc->len < 0 || ioc->len > sizeof(bnd)) - return EINVAL; - - if ((error = copyin(ioc->buf, &bnd, ioc->len)) != 0) - return error; - - if (bnd.cmd != SVR4_TI_OLD_BIND_REQUEST) { - DPRINTF(("ti_bind: bad request %ld\n", bnd.cmd)); - return EINVAL; - } - - switch (st->s_family) { - case AF_INET: - skp = (struct sockaddr *)&sain; - sasize = sizeof(sain); - - if (bnd.offs == 0) - goto error; - - netaddr_to_sockaddr_in(&sain, &bnd); - - DPRINTF(("TI_BIND: fam %d, port %d, addr %x\n", - sain.sin_family, sain.sin_port, - sain.sin_addr.s_addr)); - break; - - case AF_LOCAL: - skp = (struct sockaddr *)&saun; - sasize = sizeof(saun); - if (bnd.offs == 0) - goto error; - - netaddr_to_sockaddr_un(&saun, &bnd); - - if (saun.sun_path[0] == '\0') - goto error; - - DPRINTF(("TI_BIND: fam %d, path %s\n", - saun.sun_family, saun.sun_path)); - - if ((error = clean_pipe(td, saun.sun_path)) != 0) - return error; - - bnd.pad[28] = 0x00001000; /* magic again */ - break; - - default: - DPRINTF(("TI_BIND: Unsupported address family %d\n", - st->s_family)); - return ENOSYS; - } - - DPRINTF(("TI_BIND: fileno %d\n", fd)); - - if ((error = kern_bindat(td, AT_FDCWD, fd, skp)) != 0) { - DPRINTF(("TI_BIND: bind failed %d\n", error)); - return error; - } - goto reply; - -error: - memset(&bnd, 0, sizeof(bnd)); - bnd.len = sasize + 4; - bnd.offs = 0x10; /* XXX */ - -reply: - bnd.cmd = SVR4_TI_BIND_REPLY; - - if ((error = copyout(&bnd, ioc->buf, ioc->len)) != 0) - return error; - - return 0; -} - - -static int -timod(fp, fd, ioc, td) - struct file *fp; - int fd; - struct svr4_strioctl *ioc; - struct thread *td; -{ - switch (ioc->cmd) { - case SVR4_TI_GETINFO: - DPRINTF(("TI_GETINFO\n")); - return ti_getinfo(fp, fd, ioc, td); - - case SVR4_TI_OPTMGMT: - DPRINTF(("TI_OPTMGMT\n")); - return 0; - - case SVR4_TI_BIND: - DPRINTF(("TI_BIND\n")); - return ti_bind(fp, fd, ioc, td); - - case SVR4_TI_UNBIND: - DPRINTF(("TI_UNBIND\n")); - return 0; - - default: - DPRINTF(("Unknown timod ioctl %lx\n", ioc->cmd)); - return 0; - } -} - - -int -svr4_stream_ti_ioctl(fp, td, retval, fd, cmd, dat) - struct file *fp; - struct thread *td; - register_t *retval; - int fd; - u_long cmd; - caddr_t dat; -{ - struct svr4_strbuf skb, *sub = (struct svr4_strbuf *) dat; - struct svr4_strm *st = svr4_stream_get(fp); - int error; - struct sockaddr *sa; - socklen_t sasize, oldsasize; - struct svr4_strmcmd sc; - - DPRINTF(("svr4_stream_ti_ioctl\n")); - - if (st == NULL) - return EINVAL; - - sc.offs = 0x10; - - if ((error = copyin(sub, &skb, sizeof(skb))) != 0) { - DPRINTF(("ti_ioctl: error copying in strbuf\n")); - return error; - } - - switch (st->s_family) { - case AF_INET: - sasize = sizeof(struct sockaddr_in); - break; - - case AF_LOCAL: - sasize = sizeof(struct sockaddr_un); - break; - - default: - DPRINTF(("ti_ioctl: Unsupported address family %d\n", - st->s_family)); - return ENOSYS; - } - oldsasize = sasize; - - switch (cmd) { - case SVR4_TI_GETMYNAME: - DPRINTF(("TI_GETMYNAME\n")); - { - error = kern_getsockname(td, fd, &sa, &sasize); - if (error) { - DPRINTF(("ti_ioctl: getsockname error\n")); - return error; - } - } - break; - - case SVR4_TI_GETPEERNAME: - DPRINTF(("TI_GETPEERNAME\n")); - { - error = kern_getpeername(td, fd, &sa, &sasize); - if (error) { - DPRINTF(("ti_ioctl: getpeername error\n")); - return error; - } - } - break; - - case SVR4_TI_SETMYNAME: - DPRINTF(("TI_SETMYNAME\n")); - return 0; - - case SVR4_TI_SETPEERNAME: - DPRINTF(("TI_SETPEERNAME\n")); - return 0; - default: - DPRINTF(("ti_ioctl: Unknown ioctl %lx\n", cmd)); - return ENOSYS; - } - - if (sasize < 0 || sasize > oldsasize) { - free(sa, M_SONAME); - return EINVAL; - } - - switch (st->s_family) { - case AF_INET: - sockaddr_to_netaddr_in(&sc, (struct sockaddr_in *)sa); - skb.len = sasize; - break; - - case AF_LOCAL: - sockaddr_to_netaddr_un(&sc, (struct sockaddr_un *)sa); - skb.len = sasize + 4; - break; - - default: - free(sa, M_SONAME); - return ENOSYS; - } - free(sa, M_SONAME); - - if ((error = copyout(SVR4_ADDROF(&sc), skb.buf, sasize)) != 0) { - DPRINTF(("ti_ioctl: error copying out socket data\n")); - return error; - } - - - if ((error = copyout(&skb, sub, sizeof(skb))) != 0) { - DPRINTF(("ti_ioctl: error copying out strbuf\n")); - return error; - } - - return error; -} - - - - -static int -i_nread(fp, td, retval, fd, cmd, dat) - struct file *fp; - struct thread *td; - register_t *retval; - int fd; - u_long cmd; - caddr_t dat; -{ - int error; - int nread = 0; - - /* - * We are supposed to return the message length in nread, and the - * number of messages in retval. We don't have the notion of number - * of stream messages, so we just find out if we have any bytes waiting - * for us, and if we do, then we assume that we have at least one - * message waiting for us. - */ - if ((error = fo_ioctl(fp, FIONREAD, (caddr_t) &nread, td->td_ucred, - td)) != 0) - return error; - - if (nread != 0) - *retval = 1; - else - *retval = 0; - - return copyout(&nread, dat, sizeof(nread)); -} - -static int -i_fdinsert(fp, td, retval, fd, cmd, dat) - struct file *fp; - struct thread *td; - register_t *retval; - int fd; - u_long cmd; - caddr_t dat; -{ - /* - * Major hack again here. We assume that we are using this to - * implement accept(2). If that is the case, we have already - * called accept, and we have stored the file descriptor in - * afd. We find the file descriptor that the code wants to use - * in fd insert, and then we dup2() our accepted file descriptor - * to it. - */ - int error; - struct svr4_strm *st = svr4_stream_get(fp); - struct svr4_strfdinsert fdi; - struct dup2_args d2p; - - if (st == NULL) { - DPRINTF(("fdinsert: bad file type\n")); - return EINVAL; - } - - mtx_lock(&Giant); - if (st->s_afd == -1) { - DPRINTF(("fdinsert: accept fd not found\n")); - mtx_unlock(&Giant); - return ENOENT; - } - - if ((error = copyin(dat, &fdi, sizeof(fdi))) != 0) { - DPRINTF(("fdinsert: copyin failed %d\n", error)); - mtx_unlock(&Giant); - return error; - } - - d2p.from = st->s_afd; - d2p.to = fdi.fd; - - if ((error = sys_dup2(td, &d2p)) != 0) { - DPRINTF(("fdinsert: dup2(%d, %d) failed %d\n", - st->s_afd, fdi.fd, error)); - mtx_unlock(&Giant); - return error; - } - - if ((error = kern_close(td, st->s_afd)) != 0) { - DPRINTF(("fdinsert: close(%d) failed %d\n", - st->s_afd, error)); - mtx_unlock(&Giant); - return error; - } - - st->s_afd = -1; - mtx_unlock(&Giant); - - *retval = 0; - return 0; -} - - -static int -_i_bind_rsvd(fp, td, retval, fd, cmd, dat) - struct file *fp; - struct thread *td; - register_t *retval; - int fd; - u_long cmd; - caddr_t dat; -{ - struct mkfifo_args ap; - - /* - * This is a supposed to be a kernel and library only ioctl. - * It gets called before ti_bind, when we have a unix - * socket, to physically create the socket transport and - * ``reserve'' it. I don't know how this get reserved inside - * the kernel, but we are going to create it nevertheless. - */ - ap.path = dat; - ap.mode = S_IFIFO; - - return sys_mkfifo(td, &ap); -} - -static int -_i_rele_rsvd(fp, td, retval, fd, cmd, dat) - struct file *fp; - struct thread *td; - register_t *retval; - int fd; - u_long cmd; - caddr_t dat; -{ - struct unlink_args ap; - - /* - * This is a supposed to be a kernel and library only ioctl. - * I guess it is supposed to release the socket. - */ - ap.path = dat; - - return sys_unlink(td, &ap); -} - -static int -i_str(fp, td, retval, fd, cmd, dat) - struct file *fp; - struct thread *td; - register_t *retval; - int fd; - u_long cmd; - caddr_t dat; -{ - int error; - struct svr4_strioctl ioc; - - if ((error = copyin(dat, &ioc, sizeof(ioc))) != 0) - return error; - -#ifdef DEBUG_SVR4 - if ((error = show_ioc(">", &ioc)) != 0) - return error; -#endif /* DEBUG_SVR4 */ - - switch (ioc.cmd & 0xff00) { - case SVR4_SIMOD: - if ((error = sockmod(fp, fd, &ioc, td)) != 0) - return error; - break; - - case SVR4_TIMOD: - if ((error = timod(fp, fd, &ioc, td)) != 0) - return error; - break; - - default: - DPRINTF(("Unimplemented module %c %ld\n", - (char) (cmd >> 8), cmd & 0xff)); - return 0; - } - -#ifdef DEBUG_SVR4 - if ((error = show_ioc("<", &ioc)) != 0) - return error; -#endif /* DEBUG_SVR4 */ - return copyout(&ioc, dat, sizeof(ioc)); -} - -static int -i_setsig(fp, td, retval, fd, cmd, dat) - struct file *fp; - struct thread *td; - register_t *retval; - int fd; - u_long cmd; - caddr_t dat; -{ - /* - * This is the best we can do for now; we cannot generate - * signals only for specific events so the signal mask gets - * ignored; we save it just to pass it to a possible I_GETSIG... - * - * We alse have to fix the O_ASYNC fcntl bit, so the - * process will get SIGPOLLs. - */ - int error; - register_t oflags, flags; - struct svr4_strm *st = svr4_stream_get(fp); - - if (st == NULL) { - DPRINTF(("i_setsig: bad file descriptor\n")); - return EINVAL; - } - /* get old status flags */ - error = kern_fcntl(td, fd, F_GETFL, 0); - if (error) - return (error); - - oflags = td->td_retval[0]; - - /* update the flags */ - mtx_lock(&Giant); - if (dat != NULL) { - int mask; - - flags = oflags | O_ASYNC; - if ((error = copyin(dat, &mask, sizeof(mask))) != 0) { - DPRINTF(("i_setsig: bad eventmask pointer\n")); - return error; - } - if (mask & SVR4_S_ALLMASK) { - DPRINTF(("i_setsig: bad eventmask data %x\n", mask)); - return EINVAL; - } - st->s_eventmask = mask; - } - else { - flags = oflags & ~O_ASYNC; - st->s_eventmask = 0; - } - mtx_unlock(&Giant); - - /* set the new flags, if changed */ - if (flags != oflags) { - error = kern_fcntl(td, fd, F_SETFL, flags); - if (error) - return (error); - flags = td->td_retval[0]; - } - - /* set up SIGIO receiver if needed */ - if (dat != NULL) - return (kern_fcntl(td, fd, F_SETOWN, td->td_proc->p_pid)); - return 0; -} - -static int -i_getsig(fp, td, retval, fd, cmd, dat) - struct file *fp; - struct thread *td; - register_t *retval; - int fd; - u_long cmd; - caddr_t dat; -{ - int error, eventmask; - - if (dat != NULL) { - struct svr4_strm *st = svr4_stream_get(fp); - - if (st == NULL) { - DPRINTF(("i_getsig: bad file descriptor\n")); - return EINVAL; - } - mtx_lock(&Giant); - eventmask = st->s_eventmask; - mtx_unlock(&Giant); - if ((error = copyout(&eventmask, dat, - sizeof(eventmask))) != 0) { - DPRINTF(("i_getsig: bad eventmask pointer\n")); - return error; - } - } - return 0; -} - -int -svr4_stream_ioctl(fp, td, retval, fd, cmd, dat) - struct file *fp; - struct thread *td; - register_t *retval; - int fd; - u_long cmd; - caddr_t dat; -{ - *retval = 0; - - /* - * All the following stuff assumes "sockmod" is pushed... - */ - switch (cmd) { - case SVR4_I_NREAD: - DPRINTF(("I_NREAD\n")); - return i_nread(fp, td, retval, fd, cmd, dat); - - case SVR4_I_PUSH: - DPRINTF(("I_PUSH %p\n", dat)); -#if defined(DEBUG_SVR4) - show_strbuf((struct svr4_strbuf *)dat); -#endif - return 0; - - case SVR4_I_POP: - DPRINTF(("I_POP\n")); - return 0; - - case SVR4_I_LOOK: - DPRINTF(("I_LOOK\n")); - return 0; - - case SVR4_I_FLUSH: - DPRINTF(("I_FLUSH\n")); - return 0; - - case SVR4_I_SRDOPT: - DPRINTF(("I_SRDOPT\n")); - return 0; - - case SVR4_I_GRDOPT: - DPRINTF(("I_GRDOPT\n")); - return 0; - - case SVR4_I_STR: - DPRINTF(("I_STR\n")); - return i_str(fp, td, retval, fd, cmd, dat); - - case SVR4_I_SETSIG: - DPRINTF(("I_SETSIG\n")); - return i_setsig(fp, td, retval, fd, cmd, dat); - - case SVR4_I_GETSIG: - DPRINTF(("I_GETSIG\n")); - return i_getsig(fp, td, retval, fd, cmd, dat); - - case SVR4_I_FIND: - DPRINTF(("I_FIND\n")); - /* - * Here we are not pushing modules really, we just - * pretend all are present - */ - *retval = 0; - return 0; - - case SVR4_I_LINK: - DPRINTF(("I_LINK\n")); - return 0; - - case SVR4_I_UNLINK: - DPRINTF(("I_UNLINK\n")); - return 0; - - case SVR4_I_ERECVFD: - DPRINTF(("I_ERECVFD\n")); - return 0; - - case SVR4_I_PEEK: - DPRINTF(("I_PEEK\n")); - return 0; - - case SVR4_I_FDINSERT: - DPRINTF(("I_FDINSERT\n")); - return i_fdinsert(fp, td, retval, fd, cmd, dat); - - case SVR4_I_SENDFD: - DPRINTF(("I_SENDFD\n")); - return 0; - - case SVR4_I_RECVFD: - DPRINTF(("I_RECVFD\n")); - return 0; - - case SVR4_I_SWROPT: - DPRINTF(("I_SWROPT\n")); - return 0; - - case SVR4_I_GWROPT: - DPRINTF(("I_GWROPT\n")); - return 0; - - case SVR4_I_LIST: - DPRINTF(("I_LIST\n")); - return 0; - - case SVR4_I_PLINK: - DPRINTF(("I_PLINK\n")); - return 0; - - case SVR4_I_PUNLINK: - DPRINTF(("I_PUNLINK\n")); - return 0; - - case SVR4_I_SETEV: - DPRINTF(("I_SETEV\n")); - return 0; - - case SVR4_I_GETEV: - DPRINTF(("I_GETEV\n")); - return 0; - - case SVR4_I_STREV: - DPRINTF(("I_STREV\n")); - return 0; - - case SVR4_I_UNSTREV: - DPRINTF(("I_UNSTREV\n")); - return 0; - - case SVR4_I_FLUSHBAND: - DPRINTF(("I_FLUSHBAND\n")); - return 0; - - case SVR4_I_CKBAND: - DPRINTF(("I_CKBAND\n")); - return 0; - - case SVR4_I_GETBAND: - DPRINTF(("I_GETBANK\n")); - return 0; - - case SVR4_I_ATMARK: - DPRINTF(("I_ATMARK\n")); - return 0; - - case SVR4_I_SETCLTIME: - DPRINTF(("I_SETCLTIME\n")); - return 0; - - case SVR4_I_GETCLTIME: - DPRINTF(("I_GETCLTIME\n")); - return 0; - - case SVR4_I_CANPUT: - DPRINTF(("I_CANPUT\n")); - return 0; - - case SVR4__I_BIND_RSVD: - DPRINTF(("_I_BIND_RSVD\n")); - return _i_bind_rsvd(fp, td, retval, fd, cmd, dat); - - case SVR4__I_RELE_RSVD: - DPRINTF(("_I_RELE_RSVD\n")); - return _i_rele_rsvd(fp, td, retval, fd, cmd, dat); - - default: - DPRINTF(("unimpl cmd = %lx\n", cmd)); - break; - } - - return 0; -} - - - -int -svr4_sys_putmsg(td, uap) - struct thread *td; - struct svr4_sys_putmsg_args *uap; -{ - cap_rights_t rights; - struct file *fp; - int error; - - error = fget(td, uap->fd, cap_rights_init(&rights, CAP_SEND), &fp); - if (error != 0) { -#ifdef DEBUG_SVR4 - uprintf("putmsg: bad fp\n"); -#endif - return EBADF; - } - error = svr4_do_putmsg(td, uap, fp); - fdrop(fp, td); - return (error); -} - -static int -svr4_do_putmsg(td, uap, fp) - struct thread *td; - struct svr4_sys_putmsg_args *uap; - struct file *fp; -{ - struct svr4_strbuf dat, ctl; - struct svr4_strmcmd sc; - struct sockaddr_in sain; - struct sockaddr_un saun; - struct sockaddr *sa; - int sasize, *retval; - struct svr4_strm *st; - int error; - - retval = td->td_retval; - -#ifdef DEBUG_SVR4 - show_msg(">putmsg", uap->fd, uap->ctl, - uap->dat, uap->flags); -#endif /* DEBUG_SVR4 */ - - if (uap->ctl != NULL) { - if ((error = copyin(uap->ctl, &ctl, sizeof(ctl))) != 0) { -#ifdef DEBUG_SVR4 - uprintf("putmsg: copyin(): %d\n", error); -#endif - return error; - } - } - else - ctl.len = -1; - - if (uap->dat != NULL) { - if ((error = copyin(uap->dat, &dat, sizeof(dat))) != 0) { -#ifdef DEBUG_SVR4 - uprintf("putmsg: copyin(): %d (2)\n", error); -#endif - return error; - } - } - else - dat.len = -1; - - /* - * Only for sockets for now. - */ - if ((st = svr4_stream_get(fp)) == NULL) { - DPRINTF(("putmsg: bad file type\n")); - return EINVAL; - } - - if (ctl.len < 0 || ctl.len > sizeof(sc)) { - DPRINTF(("putmsg: Bad control size %d != %d\n", ctl.len, - sizeof(struct svr4_strmcmd))); - return EINVAL; - } - - if ((error = copyin(ctl.buf, &sc, ctl.len)) != 0) - return error; - - switch (st->s_family) { - case AF_INET: - if (sc.len != sizeof(sain)) { - if (sc.cmd == SVR4_TI_DATA_REQUEST) { - struct write_args wa; - - /* Solaris seems to use sc.cmd = 3 to - * send "expedited" data. telnet uses - * this for options processing, sending EOF, - * etc. I'm sure other things use it too. - * I don't have any documentation - * on it, so I'm making a guess that this - * is how it works. newton@atdot.dotat.org XXX - */ - DPRINTF(("sending expedited data ??\n")); - wa.fd = uap->fd; - wa.buf = dat.buf; - wa.nbyte = dat.len; - return sys_write(td, &wa); - } - DPRINTF(("putmsg: Invalid inet length %ld\n", sc.len)); - return EINVAL; - } - netaddr_to_sockaddr_in(&sain, &sc); - sa = (struct sockaddr *)&sain; - sasize = sizeof(sain); - if (sain.sin_family != st->s_family) - error = EINVAL; - break; - - case AF_LOCAL: - if (ctl.len == 8) { - /* We are doing an accept; succeed */ - DPRINTF(("putmsg: Do nothing\n")); - *retval = 0; - return 0; - } - else { - /* Maybe we've been given a device/inode pair */ - dev_t *dev = SVR4_ADDROF(&sc); - ino_t *ino = (ino_t *) &dev[1]; - if (svr4_find_socket(td, fp, *dev, *ino, &saun) != 0) { - /* I guess we have it by name */ - netaddr_to_sockaddr_un(&saun, &sc); - } - sa = (struct sockaddr *)&saun; - sasize = sizeof(saun); - } - break; - - default: - DPRINTF(("putmsg: Unsupported address family %d\n", - st->s_family)); - return ENOSYS; - } - - mtx_lock(&Giant); - st->s_cmd = sc.cmd; - mtx_unlock(&Giant); - switch (sc.cmd) { - case SVR4_TI_CONNECT_REQUEST: /* connect */ - { - - return (kern_connectat(td, AT_FDCWD, uap->fd, sa)); - } - - case SVR4_TI_SENDTO_REQUEST: /* sendto */ - { - struct msghdr msg; - struct iovec aiov; - - msg.msg_name = sa; - msg.msg_namelen = sasize; - msg.msg_iov = &aiov; - msg.msg_iovlen = 1; - msg.msg_control = 0; - msg.msg_flags = 0; - aiov.iov_base = dat.buf; - aiov.iov_len = dat.len; - error = kern_sendit(td, uap->fd, &msg, uap->flags, - NULL, UIO_USERSPACE); - DPRINTF(("sendto_request error: %d\n", error)); - *retval = 0; - return error; - } - - default: - DPRINTF(("putmsg: Unimplemented command %lx\n", sc.cmd)); - return ENOSYS; - } -} - -int -svr4_sys_getmsg(td, uap) - struct thread *td; - struct svr4_sys_getmsg_args *uap; -{ - cap_rights_t rights; - struct file *fp; - int error; - - error = fget(td, uap->fd, cap_rights_init(&rights, CAP_RECV), &fp); - if (error != 0) { -#ifdef DEBUG_SVR4 - uprintf("getmsg: bad fp\n"); -#endif - return EBADF; - } - error = svr4_do_getmsg(td, uap, fp); - fdrop(fp, td); - return (error); -} - -int -svr4_do_getmsg(td, uap, fp) - struct thread *td; - struct svr4_sys_getmsg_args *uap; - struct file *fp; -{ - struct svr4_strbuf dat, ctl; - struct svr4_strmcmd sc; - int error, *retval; - struct msghdr msg; - struct iovec aiov; - struct sockaddr_in sain; - struct sockaddr_un saun; - struct sockaddr *sa; - socklen_t sasize; - struct svr4_strm *st; - struct file *afp; - int fl; - - retval = td->td_retval; - error = 0; - afp = NULL; - - memset(&sc, 0, sizeof(sc)); - -#ifdef DEBUG_SVR4 - show_msg(">getmsg", uap->fd, uap->ctl, - uap->dat, 0); -#endif /* DEBUG_SVR4 */ - - if (uap->ctl != NULL) { - if ((error = copyin(uap->ctl, &ctl, sizeof(ctl))) != 0) - return error; - if (ctl.len < 0) - return EINVAL; - } - else { - ctl.len = -1; - ctl.maxlen = 0; - } - - if (uap->dat != NULL) { - if ((error = copyin(uap->dat, &dat, sizeof(dat))) != 0) - return error; - } - else { - dat.len = -1; - dat.maxlen = 0; - } - - /* - * Only for sockets for now. - */ - if ((st = svr4_stream_get(fp)) == NULL) { - DPRINTF(("getmsg: bad file type\n")); - return EINVAL; - } - - if (ctl.maxlen == -1 || dat.maxlen == -1) { - DPRINTF(("getmsg: Cannot handle -1 maxlen (yet)\n")); - return ENOSYS; - } - - switch (st->s_family) { - case AF_INET: - sasize = sizeof(sain); - break; - - case AF_LOCAL: - sasize = sizeof(saun); - break; - - default: - DPRINTF(("getmsg: Unsupported address family %d\n", - st->s_family)); - return ENOSYS; - } - - mtx_lock(&Giant); - switch (st->s_cmd) { - case SVR4_TI_CONNECT_REQUEST: - DPRINTF(("getmsg: TI_CONNECT_REQUEST\n")); - /* - * We do the connect in one step, so the putmsg should - * have gotten the error. - */ - sc.cmd = SVR4_TI_OK_REPLY; - sc.len = 0; - - ctl.len = 8; - dat.len = -1; - fl = 1; - st->s_cmd = sc.cmd; - break; - - case SVR4_TI_OK_REPLY: - DPRINTF(("getmsg: TI_OK_REPLY\n")); - /* - * We are immediately after a connect reply, so we send - * a connect verification. - */ - - error = kern_getpeername(td, uap->fd, &sa, &sasize); - if (error) { - mtx_unlock(&Giant); - DPRINTF(("getmsg: getpeername failed %d\n", error)); - return error; - } - - sc.cmd = SVR4_TI_CONNECT_REPLY; - sc.pad[0] = 0x4; - sc.offs = 0x18; - sc.pad[1] = 0x14; - sc.pad[2] = 0x04000402; - - switch (st->s_family) { - case AF_INET: - sc.len = sasize; - sockaddr_to_netaddr_in(&sc, (struct sockaddr_in *)sa); - break; - - case AF_LOCAL: - sc.len = sasize + 4; - sockaddr_to_netaddr_un(&sc, (struct sockaddr_un *)sa); - break; - - default: - mtx_unlock(&Giant); - free(sa, M_SONAME); - return ENOSYS; - } - free(sa, M_SONAME); - - ctl.len = 40; - dat.len = -1; - fl = 0; - st->s_cmd = sc.cmd; - break; - - case SVR4_TI__ACCEPT_OK: - DPRINTF(("getmsg: TI__ACCEPT_OK\n")); - /* - * We do the connect in one step, so the putmsg should - * have gotten the error. - */ - sc.cmd = SVR4_TI_OK_REPLY; - sc.len = 1; - - ctl.len = 8; - dat.len = -1; - fl = 1; - st->s_cmd = SVR4_TI__ACCEPT_WAIT; - break; - - case SVR4_TI__ACCEPT_WAIT: - DPRINTF(("getmsg: TI__ACCEPT_WAIT\n")); - /* - * We are after a listen, so we try to accept... - */ - - error = kern_accept(td, uap->fd, &sa, &sasize, &afp); - if (error) { - mtx_unlock(&Giant); - DPRINTF(("getmsg: accept failed %d\n", error)); - return error; - } - - st->s_afd = *retval; - - DPRINTF(("getmsg: Accept fd = %d\n", st->s_afd)); - - sc.cmd = SVR4_TI_ACCEPT_REPLY; - sc.offs = 0x18; - sc.pad[0] = 0x0; - - switch (st->s_family) { - case AF_INET: - sc.pad[1] = 0x28; - sockaddr_to_netaddr_in(&sc, (struct sockaddr_in *)&sa); - ctl.len = 40; - sc.len = sasize; - break; - - case AF_LOCAL: - sc.pad[1] = 0x00010000; - sc.pad[2] = 0xf6bcdaa0; /* I don't know what that is */ - sc.pad[3] = 0x00010000; - ctl.len = 134; - sc.len = sasize + 4; - break; - - default: - fdclose(td, afp, st->s_afd); - fdrop(afp, td); - st->s_afd = -1; - mtx_unlock(&Giant); - free(sa, M_SONAME); - return ENOSYS; - } - free(sa, M_SONAME); - - dat.len = -1; - fl = 0; - st->s_cmd = SVR4_TI__ACCEPT_OK; - break; - - case SVR4_TI_SENDTO_REQUEST: - DPRINTF(("getmsg: TI_SENDTO_REQUEST\n")); - if (ctl.maxlen > 36 && ctl.len < 36) - ctl.len = 36; - - if (ctl.len > sizeof(sc)) - ctl.len = sizeof(sc); - - if ((error = copyin(ctl.buf, &sc, ctl.len)) != 0) { - mtx_unlock(&Giant); - return error; - } - - switch (st->s_family) { - case AF_INET: - sa = (struct sockaddr *)&sain; - sockaddr_to_netaddr_in(&sc, &sain); - break; - - case AF_LOCAL: - sa = (struct sockaddr *)&saun; - sockaddr_to_netaddr_un(&sc, &saun); - break; - - default: - mtx_unlock(&Giant); - return ENOSYS; - } - - msg.msg_name = sa; - msg.msg_namelen = sasize; - msg.msg_iov = &aiov; - msg.msg_iovlen = 1; - msg.msg_control = 0; - aiov.iov_base = dat.buf; - aiov.iov_len = dat.maxlen; - msg.msg_flags = 0; - - error = kern_recvit(td, uap->fd, &msg, UIO_SYSSPACE, NULL); - - if (error) { - mtx_unlock(&Giant); - DPRINTF(("getmsg: recvit failed %d\n", error)); - return error; - } - - sc.cmd = SVR4_TI_RECVFROM_IND; - - switch (st->s_family) { - case AF_INET: - sc.len = sasize; - sockaddr_to_netaddr_in(&sc, &sain); - break; - - case AF_LOCAL: - sc.len = sasize + 4; - sockaddr_to_netaddr_un(&sc, &saun); - break; - - default: - mtx_unlock(&Giant); - return ENOSYS; - } - - dat.len = *retval; - fl = 0; - st->s_cmd = sc.cmd; - break; - - default: - st->s_cmd = sc.cmd; - if (st->s_cmd == SVR4_TI_CONNECT_REQUEST) { - struct read_args ra; - - /* More weirdness: Again, I can't find documentation - * to back this up, but when a process does a generic - * "getmsg()" call it seems that the command field is - * zero and the length of the data area is zero. I - * think processes expect getmsg() to fill in dat.len - * after reading at most dat.maxlen octets from the - * stream. Since we're using sockets I can let - * read() look after it and frob return values - * appropriately (or inappropriately :-) - * -- newton@atdot.dotat.org XXX - */ - ra.fd = uap->fd; - ra.buf = dat.buf; - ra.nbyte = dat.maxlen; - if ((error = sys_read(td, &ra)) != 0) { - mtx_unlock(&Giant); - return error; - } - dat.len = *retval; - *retval = 0; - st->s_cmd = SVR4_TI_SENDTO_REQUEST; - break; - } - mtx_unlock(&Giant); - DPRINTF(("getmsg: Unknown state %x\n", st->s_cmd)); - return EINVAL; - } - - if (uap->ctl) { - if (ctl.len > sizeof(sc)) - ctl.len = sizeof(sc); - if (ctl.len != -1) - error = copyout(&sc, ctl.buf, ctl.len); - - if (error == 0) - error = copyout(&ctl, uap->ctl, sizeof(ctl)); - } - - if (uap->dat) { - if (error == 0) - error = copyout(&dat, uap->dat, sizeof(dat)); - } - - if (uap->flags) { /* XXX: Need translation */ - if (error == 0) - error = copyout(&fl, uap->flags, sizeof(fl)); - } - - if (error) { - if (afp) { - fdclose(td, afp, st->s_afd); - fdrop(afp, td); - st->s_afd = -1; - } - mtx_unlock(&Giant); - return (error); - } - mtx_unlock(&Giant); - if (afp) - fdrop(afp, td); - - *retval = 0; - -#ifdef DEBUG_SVR4 - show_msg("fd, uap->ctl, - uap->dat, fl); -#endif /* DEBUG_SVR4 */ - return error; -} - -int svr4_sys_send(td, uap) - struct thread *td; - struct svr4_sys_send_args *uap; -{ - struct sendto_args sta; - - sta.s = uap->s; - sta.buf = uap->buf; - sta.len = uap->len; - sta.flags = uap->flags; - sta.to = NULL; - sta.tolen = 0; - - return (sys_sendto(td, &sta)); -} - -int svr4_sys_recv(td, uap) - struct thread *td; - struct svr4_sys_recv_args *uap; -{ - struct recvfrom_args rfa; - - rfa.s = uap->s; - rfa.buf = uap->buf; - rfa.len = uap->len; - rfa.flags = uap->flags; - rfa.from = NULL; - rfa.fromlenaddr = NULL; - - return (sys_recvfrom(td, &rfa)); -} - -/* - * XXX This isn't necessary, but it's handy for inserting debug code into - * sendto(). Let's leave it here for now... - */ -int -svr4_sys_sendto(td, uap) - struct thread *td; - struct svr4_sys_sendto_args *uap; -{ - struct sendto_args sa; - - sa.s = uap->s; - sa.buf = uap->buf; - sa.len = uap->len; - sa.flags = uap->flags; - sa.to = (caddr_t)uap->to; - sa.tolen = uap->tolen; - - DPRINTF(("calling sendto()\n")); - return sys_sendto(td, &sa); -} - diff --git a/sys/compat/svr4/svr4_stropts.h b/sys/compat/svr4/svr4_stropts.h deleted file mode 100644 index d5729b59fcd..00000000000 --- a/sys/compat/svr4/svr4_stropts.h +++ /dev/null @@ -1,179 +0,0 @@ -/*- - * Copyright (c) 1998 Mark Newton - * Copyright (c) 1994 Christos Zoulas - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * $FreeBSD: stable/11/sys/compat/svr4/svr4_stropts.h 160794 2006-07-28 16:56:17Z jhb $ - */ - -#ifndef _SVR4_STROPTS_H_ -#define _SVR4_STROPTS_H_ - - -struct svr4_strbuf { - int maxlen; - int len; - char *buf; -}; - -#define SVR4_STR ('S' << 8) -#define SVR4_I_NREAD (SVR4_STR| 1) -#define SVR4_I_PUSH (SVR4_STR| 2) -#define SVR4_I_POP (SVR4_STR| 3) -#define SVR4_I_LOOK (SVR4_STR| 4) -#define SVR4_I_FLUSH (SVR4_STR| 5) -#define SVR4_I_SRDOPT (SVR4_STR| 6) -#define SVR4_I_GRDOPT (SVR4_STR| 7) -#define SVR4_I_STR (SVR4_STR| 8) -#define SVR4_I_SETSIG (SVR4_STR| 9) -#define SVR4_I_GETSIG (SVR4_STR|10) -#define SVR4_I_FIND (SVR4_STR|11) -#define SVR4_I_LINK (SVR4_STR|12) -#define SVR4_I_UNLINK (SVR4_STR|13) -#define SVR4_I_ERECVFD (SVR4_STR|14) -#define SVR4_I_PEEK (SVR4_STR|15) -#define SVR4_I_FDINSERT (SVR4_STR|16) -#define SVR4_I_SENDFD (SVR4_STR|17) -#define SVR4_I_RECVFD (SVR4_STR|18) -#define SVR4_I_SWROPT (SVR4_STR|19) -#define SVR4_I_GWROPT (SVR4_STR|20) -#define SVR4_I_LIST (SVR4_STR|21) -#define SVR4_I_PLINK (SVR4_STR|22) -#define SVR4_I_PUNLINK (SVR4_STR|23) -#define SVR4_I_SETEV (SVR4_STR|24) -#define SVR4_I_GETEV (SVR4_STR|25) -#define SVR4_I_STREV (SVR4_STR|26) -#define SVR4_I_UNSTREV (SVR4_STR|27) -#define SVR4_I_FLUSHBAND (SVR4_STR|28) -#define SVR4_I_CKBAND (SVR4_STR|29) -#define SVR4_I_GETBAND (SVR4_STR|30) -#define SVR4_I_ATMARK (SVR4_STR|31) -#define SVR4_I_SETCLTIME (SVR4_STR|32) -#define SVR4_I_GETCLTIME (SVR4_STR|33) -#define SVR4_I_CANPUT (SVR4_STR|34) - -/* - * The following two ioctls are OS specific and - * undocumented. - */ -#define SVR4__I_BIND_RSVD (SVR4_STR|242) -#define SVR4__I_RELE_RSVD (SVR4_STR|243) - -/* - * Service type definitions - */ -#define SVR4_T_COTS 1 /* Connection-orieted */ -#define SVR4_T_COTS_ORD 2 /* Local connection-oriented */ -#define SVR4_T_CLTS 3 /* Connectionless */ - -/* Struct passed for SVR4_I_STR */ -struct svr4_strioctl { - u_long cmd; - int timeout; - int len; - char *buf; -}; - -/* - * Bits for I_{G,S}ETSIG - */ -#define SVR4_S_INPUT 0x0001 /* any message on read queue no HIPRI */ -#define SVR4_S_HIPRI 0x0002 /* high prio message on read queue */ -#define SVR4_S_OUTPUT 0x0004 /* write queue has free space */ -#define SVR4_S_MSG 0x0008 /* signal message in read queue head */ -#define SVR4_S_ERROR 0x0010 /* error message in read queue head */ -#define SVR4_S_HANGUP 0x0020 /* hangup message in read queue head */ -#define SVR4_S_RDNORM 0x0040 /* normal message on read queue */ -#define SVR4_S_WRNORM S_OUTPUT /* write queue has free space */ -#define SVR4_S_RDBAND 0x0080 /* out of band message on read queue */ -#define SVR4_S_WRBAND 0x0100 /* write queue has free space for oob */ -#define SVR4_S_BANDURG 0x0200 /* generate SIGURG instead of SIGPOLL */ -#define SVR4_S_ALLMASK 0x03ff /* all events mask */ - -/* - * Our internal state for the stream - * For now we keep almost nothing... In the future we can keep more - * streams state. - * - * Locking key: - * r - Read only field only set during creation - * G - Giant - */ -struct svr4_strm { - int s_family; /* (r) socket family */ - int s_cmd; /* (G) last getmsg reply or putmsg request */ - int s_afd; /* (G) last accepted fd; [for fd_insert] */ - int s_eventmask; /* (G) state info from I_SETSIG et al */ -}; - -/* - * The following structures are determined empirically. - */ -struct svr4_strmcmd { - long cmd; /* command ? */ - long len; /* Address len */ - long offs; /* Address offset */ - long pad[61]; -}; - -struct svr4_infocmd { - long cmd; - long tsdu; - long etsdu; - long cdata; - long ddata; - long addr; - long opt; - long tidu; - long serv; - long current; - long provider; -}; - -struct svr4_strfdinsert { - struct svr4_strbuf ctl; - struct svr4_strbuf data; - long flags; - int fd; - int offset; -}; - -struct svr4_netaddr_in { - u_short family; - u_short port; - u_long addr; -}; - -struct svr4_netaddr_un { - u_short family; - char path[1]; -}; - -#define SVR4_ADDROF(sc) (void *) (((char *) (sc)) + (sc)->offs) -#define SVR4_C_ADDROF(sc) (const void *) (((const char *) (sc)) + (sc)->offs) - -struct svr4_strm *svr4_stream_get(struct file *fp); - -#endif /* !_SVR4_STROPTS */ diff --git a/sys/compat/svr4/svr4_syscall.h b/sys/compat/svr4/svr4_syscall.h deleted file mode 100644 index 0c7ba4ad93b..00000000000 --- a/sys/compat/svr4/svr4_syscall.h +++ /dev/null @@ -1,146 +0,0 @@ -/* - * System call numbers. - * - * DO NOT EDIT-- this file is automatically generated. - * $FreeBSD: stable/11/sys/compat/svr4/svr4_syscall.h 318164 2017-05-10 23:09:17Z jhb $ - */ - -#define SVR4_SYS_exit 1 -#define SVR4_SYS_fork 2 -#define SVR4_SYS_read 3 -#define SVR4_SYS_write 4 -#define SVR4_SYS_svr4_sys_open 5 -#define SVR4_SYS_close 6 -#define SVR4_SYS_svr4_sys_wait 7 -#define SVR4_SYS_svr4_sys_creat 8 -#define SVR4_SYS_link 9 -#define SVR4_SYS_unlink 10 -#define SVR4_SYS_svr4_sys_execv 11 -#define SVR4_SYS_chdir 12 -#define SVR4_SYS_svr4_sys_time 13 -#define SVR4_SYS_svr4_sys_mknod 14 -#define SVR4_SYS_chmod 15 -#define SVR4_SYS_chown 16 -#define SVR4_SYS_svr4_sys_break 17 -#define SVR4_SYS_svr4_sys_stat 18 -#define SVR4_SYS_lseek 19 -#define SVR4_SYS_getpid 20 -#define SVR4_SYS_setuid 23 -#define SVR4_SYS_getuid 24 -#define SVR4_SYS_svr4_sys_alarm 27 -#define SVR4_SYS_svr4_sys_fstat 28 -#define SVR4_SYS_svr4_sys_pause 29 -#define SVR4_SYS_svr4_sys_utime 30 -#define SVR4_SYS_svr4_sys_access 33 -#define SVR4_SYS_svr4_sys_nice 34 -#define SVR4_SYS_sync 36 -#define SVR4_SYS_svr4_sys_kill 37 -#define SVR4_SYS_svr4_sys_pgrpsys 39 -#define SVR4_SYS_dup 41 -#define SVR4_SYS_svr4_pipe 42 -#define SVR4_SYS_svr4_sys_times 43 -#define SVR4_SYS_setgid 46 -#define SVR4_SYS_getgid 47 -#define SVR4_SYS_svr4_sys_signal 48 -#define SVR4_SYS_svr4_sys_msgsys 49 -#define SVR4_SYS_svr4_sys_sysarch 50 -#define SVR4_SYS_svr4_sys_shmsys 52 -#define SVR4_SYS_svr4_sys_semsys 53 -#define SVR4_SYS_svr4_sys_ioctl 54 -#define SVR4_SYS_svr4_sys_utssys 57 -#define SVR4_SYS_fsync 58 -#define SVR4_SYS_svr4_sys_execve 59 -#define SVR4_SYS_umask 60 -#define SVR4_SYS_chroot 61 -#define SVR4_SYS_svr4_sys_fcntl 62 -#define SVR4_SYS_svr4_sys_ulimit 63 -#define SVR4_SYS_rmdir 79 -#define SVR4_SYS_mkdir 80 -#define SVR4_SYS_svr4_sys_getdents 81 -#define SVR4_SYS_svr4_sys_getmsg 85 -#define SVR4_SYS_svr4_sys_putmsg 86 -#define SVR4_SYS_svr4_sys_poll 87 -#define SVR4_SYS_svr4_sys_lstat 88 -#define SVR4_SYS_symlink 89 -#define SVR4_SYS_readlink 90 -#define SVR4_SYS_getgroups 91 -#define SVR4_SYS_setgroups 92 -#define SVR4_SYS_fchmod 93 -#define SVR4_SYS_fchown 94 -#define SVR4_SYS_svr4_sys_sigprocmask 95 -#define SVR4_SYS_svr4_sys_sigsuspend 96 -#define SVR4_SYS_svr4_sys_sigaltstack 97 -#define SVR4_SYS_svr4_sys_sigaction 98 -#define SVR4_SYS_svr4_sys_sigpending 99 -#define SVR4_SYS_svr4_sys_context 100 -#define SVR4_SYS_svr4_sys_statvfs 103 -#define SVR4_SYS_svr4_sys_fstatvfs 104 -#define SVR4_SYS_svr4_sys_waitsys 107 -#define SVR4_SYS_svr4_sys_hrtsys 109 -#define SVR4_SYS_svr4_sys_pathconf 113 -#define SVR4_SYS_svr4_sys_mmap 115 -#define SVR4_SYS_mprotect 116 -#define SVR4_SYS_munmap 117 -#define SVR4_SYS_svr4_sys_fpathconf 118 -#define SVR4_SYS_vfork 119 -#define SVR4_SYS_fchdir 120 -#define SVR4_SYS_readv 121 -#define SVR4_SYS_writev 122 -#define SVR4_SYS_svr4_sys_xstat 123 -#define SVR4_SYS_svr4_sys_lxstat 124 -#define SVR4_SYS_svr4_sys_fxstat 125 -#define SVR4_SYS_svr4_sys_xmknod 126 -#define SVR4_SYS_svr4_sys_setrlimit 128 -#define SVR4_SYS_svr4_sys_getrlimit 129 -#define SVR4_SYS_lchown 130 -#define SVR4_SYS_svr4_sys_memcntl 131 -#define SVR4_SYS_rename 134 -#define SVR4_SYS_svr4_sys_uname 135 -#define SVR4_SYS_setegid 136 -#define SVR4_SYS_svr4_sys_sysconfig 137 -#define SVR4_SYS_adjtime 138 -#define SVR4_SYS_svr4_sys_systeminfo 139 -#define SVR4_SYS_seteuid 141 -#define SVR4_SYS_svr4_sys_fchroot 153 -#define SVR4_SYS_svr4_sys_utimes 154 -#define SVR4_SYS_svr4_sys_vhangup 155 -#define SVR4_SYS_svr4_sys_gettimeofday 156 -#define SVR4_SYS_getitimer 157 -#define SVR4_SYS_setitimer 158 -#define SVR4_SYS_svr4_sys_llseek 175 -#define SVR4_SYS_svr4_sys_acl 185 -#define SVR4_SYS_svr4_sys_auditsys 186 -#define SVR4_SYS_nanosleep 199 -#define SVR4_SYS_svr4_sys_facl 200 -#define SVR4_SYS_setreuid 202 -#define SVR4_SYS_setregid 203 -#define SVR4_SYS_svr4_sys_resolvepath 209 -#define SVR4_SYS_svr4_sys_getdents64 213 -#define SVR4_SYS_svr4_sys_mmap64 214 -#define SVR4_SYS_svr4_sys_stat64 215 -#define SVR4_SYS_svr4_sys_lstat64 216 -#define SVR4_SYS_svr4_sys_fstat64 217 -#define SVR4_SYS_svr4_sys_statvfs64 218 -#define SVR4_SYS_svr4_sys_fstatvfs64 219 -#define SVR4_SYS_svr4_sys_setrlimit64 220 -#define SVR4_SYS_svr4_sys_getrlimit64 221 -#define SVR4_SYS_svr4_sys_creat64 224 -#define SVR4_SYS_svr4_sys_open64 225 -#define SVR4_SYS_svr4_sys_socket 230 -#define SVR4_SYS_socketpair 231 -#define SVR4_SYS_bind 232 -#define SVR4_SYS_listen 233 -#define SVR4_SYS_accept 234 -#define SVR4_SYS_connect 235 -#define SVR4_SYS_shutdown 236 -#define SVR4_SYS_svr4_sys_recv 237 -#define SVR4_SYS_recvfrom 238 -#define SVR4_SYS_recvmsg 239 -#define SVR4_SYS_svr4_sys_send 240 -#define SVR4_SYS_sendmsg 241 -#define SVR4_SYS_svr4_sys_sendto 242 -#define SVR4_SYS_getpeername 243 -#define SVR4_SYS_getsockname 244 -#define SVR4_SYS_getsockopt 245 -#define SVR4_SYS_setsockopt 246 -#define SVR4_SYS_MAXSYSCALL 250 diff --git a/sys/compat/svr4/svr4_syscallnames.c b/sys/compat/svr4/svr4_syscallnames.c deleted file mode 100644 index 2dbae9ec827..00000000000 --- a/sys/compat/svr4/svr4_syscallnames.c +++ /dev/null @@ -1,259 +0,0 @@ -/* - * System call names. - * - * DO NOT EDIT-- this file is automatically generated. - * $FreeBSD: stable/11/sys/compat/svr4/svr4_syscallnames.c 318164 2017-05-10 23:09:17Z jhb $ - */ - -const char *svr4_syscallnames[] = { - "#0", /* 0 = unused */ - "exit", /* 1 = exit */ - "fork", /* 2 = fork */ - "read", /* 3 = read */ - "write", /* 4 = write */ - "svr4_sys_open", /* 5 = svr4_sys_open */ - "close", /* 6 = close */ - "svr4_sys_wait", /* 7 = svr4_sys_wait */ - "svr4_sys_creat", /* 8 = svr4_sys_creat */ - "link", /* 9 = link */ - "unlink", /* 10 = unlink */ - "svr4_sys_execv", /* 11 = svr4_sys_execv */ - "chdir", /* 12 = chdir */ - "svr4_sys_time", /* 13 = svr4_sys_time */ - "svr4_sys_mknod", /* 14 = svr4_sys_mknod */ - "chmod", /* 15 = chmod */ - "chown", /* 16 = chown */ - "svr4_sys_break", /* 17 = svr4_sys_break */ - "svr4_sys_stat", /* 18 = svr4_sys_stat */ - "lseek", /* 19 = lseek */ - "getpid", /* 20 = getpid */ - "#21", /* 21 = old_mount */ - "#22", /* 22 = sysv_umount */ - "setuid", /* 23 = setuid */ - "getuid", /* 24 = getuid */ - "#25", /* 25 = stime */ - "#26", /* 26 = ptrace */ - "svr4_sys_alarm", /* 27 = svr4_sys_alarm */ - "svr4_sys_fstat", /* 28 = svr4_sys_fstat */ - "svr4_sys_pause", /* 29 = svr4_sys_pause */ - "svr4_sys_utime", /* 30 = svr4_sys_utime */ - "#31", /* 31 = stty */ - "#32", /* 32 = gtty */ - "svr4_sys_access", /* 33 = svr4_sys_access */ - "svr4_sys_nice", /* 34 = svr4_sys_nice */ - "#35", /* 35 = statfs */ - "sync", /* 36 = sync */ - "svr4_sys_kill", /* 37 = svr4_sys_kill */ - "#38", /* 38 = fstatfs */ - "svr4_sys_pgrpsys", /* 39 = svr4_sys_pgrpsys */ - "#40", /* 40 = xenix */ - "dup", /* 41 = dup */ - "svr4_pipe", /* 42 = svr4_pipe */ - "svr4_sys_times", /* 43 = svr4_sys_times */ - "#44", /* 44 = profil */ - "#45", /* 45 = plock */ - "setgid", /* 46 = setgid */ - "getgid", /* 47 = getgid */ - "svr4_sys_signal", /* 48 = svr4_sys_signal */ - "svr4_sys_msgsys", /* 49 = svr4_sys_msgsys */ - "svr4_sys_sysarch", /* 50 = svr4_sys_sysarch */ - "#51", /* 51 = acct */ - "svr4_sys_shmsys", /* 52 = svr4_sys_shmsys */ - "svr4_sys_semsys", /* 53 = svr4_sys_semsys */ - "svr4_sys_ioctl", /* 54 = svr4_sys_ioctl */ - "#55", /* 55 = uadmin */ - "#56", /* 56 = exch */ - "svr4_sys_utssys", /* 57 = svr4_sys_utssys */ - "fsync", /* 58 = fsync */ - "svr4_sys_execve", /* 59 = svr4_sys_execve */ - "umask", /* 60 = umask */ - "chroot", /* 61 = chroot */ - "svr4_sys_fcntl", /* 62 = svr4_sys_fcntl */ - "svr4_sys_ulimit", /* 63 = svr4_sys_ulimit */ - "#64", /* 64 = reserved */ - "#65", /* 65 = reserved */ - "#66", /* 66 = reserved */ - "#67", /* 67 = reserved */ - "#68", /* 68 = reserved */ - "#69", /* 69 = reserved */ - "#70", /* 70 = advfs */ - "#71", /* 71 = unadvfs */ - "#72", /* 72 = rmount */ - "#73", /* 73 = rumount */ - "#74", /* 74 = rfstart */ - "#75", /* 75 = sigret */ - "#76", /* 76 = rdebug */ - "#77", /* 77 = rfstop */ - "#78", /* 78 = rfsys */ - "rmdir", /* 79 = rmdir */ - "mkdir", /* 80 = mkdir */ - "svr4_sys_getdents", /* 81 = svr4_sys_getdents */ - "#82", /* 82 = libattach */ - "#83", /* 83 = libdetach */ - "#84", /* 84 = sysfs */ - "svr4_sys_getmsg", /* 85 = svr4_sys_getmsg */ - "svr4_sys_putmsg", /* 86 = svr4_sys_putmsg */ - "svr4_sys_poll", /* 87 = svr4_sys_poll */ - "svr4_sys_lstat", /* 88 = svr4_sys_lstat */ - "symlink", /* 89 = symlink */ - "readlink", /* 90 = readlink */ - "getgroups", /* 91 = getgroups */ - "setgroups", /* 92 = setgroups */ - "fchmod", /* 93 = fchmod */ - "fchown", /* 94 = fchown */ - "svr4_sys_sigprocmask", /* 95 = svr4_sys_sigprocmask */ - "svr4_sys_sigsuspend", /* 96 = svr4_sys_sigsuspend */ - "svr4_sys_sigaltstack", /* 97 = svr4_sys_sigaltstack */ - "svr4_sys_sigaction", /* 98 = svr4_sys_sigaction */ - "svr4_sys_sigpending", /* 99 = svr4_sys_sigpending */ - "svr4_sys_context", /* 100 = svr4_sys_context */ - "#101", /* 101 = evsys */ - "#102", /* 102 = evtrapret */ - "svr4_sys_statvfs", /* 103 = svr4_sys_statvfs */ - "svr4_sys_fstatvfs", /* 104 = svr4_sys_fstatvfs */ - "#105", /* 105 = whoknows */ - "#106", /* 106 = nfssvc */ - "svr4_sys_waitsys", /* 107 = svr4_sys_waitsys */ - "#108", /* 108 = sigsendsys */ - "svr4_sys_hrtsys", /* 109 = svr4_sys_hrtsys */ - "#110", /* 110 = acancel */ - "#111", /* 111 = async */ - "#112", /* 112 = priocntlsys */ - "svr4_sys_pathconf", /* 113 = svr4_sys_pathconf */ - "#114", /* 114 = mincore */ - "svr4_sys_mmap", /* 115 = svr4_sys_mmap */ - "mprotect", /* 116 = mprotect */ - "munmap", /* 117 = munmap */ - "svr4_sys_fpathconf", /* 118 = svr4_sys_fpathconf */ - "vfork", /* 119 = vfork */ - "fchdir", /* 120 = fchdir */ - "readv", /* 121 = readv */ - "writev", /* 122 = writev */ - "svr4_sys_xstat", /* 123 = svr4_sys_xstat */ - "svr4_sys_lxstat", /* 124 = svr4_sys_lxstat */ - "svr4_sys_fxstat", /* 125 = svr4_sys_fxstat */ - "svr4_sys_xmknod", /* 126 = svr4_sys_xmknod */ - "#127", /* 127 = clocal */ - "svr4_sys_setrlimit", /* 128 = svr4_sys_setrlimit */ - "svr4_sys_getrlimit", /* 129 = svr4_sys_getrlimit */ - "lchown", /* 130 = lchown */ - "svr4_sys_memcntl", /* 131 = svr4_sys_memcntl */ - "#132", /* 132 = getpmsg */ - "#133", /* 133 = putpmsg */ - "rename", /* 134 = rename */ - "svr4_sys_uname", /* 135 = svr4_sys_uname */ - "setegid", /* 136 = setegid */ - "svr4_sys_sysconfig", /* 137 = svr4_sys_sysconfig */ - "adjtime", /* 138 = adjtime */ - "svr4_sys_systeminfo", /* 139 = svr4_sys_systeminfo */ - "#140", /* 140 = notused */ - "seteuid", /* 141 = seteuid */ - "#142", /* 142 = vtrace */ - "#143", /* 143 = { */ - "#144", /* 144 = sigtimedwait */ - "#145", /* 145 = lwp_info */ - "#146", /* 146 = yield */ - "#147", /* 147 = lwp_sema_wait */ - "#148", /* 148 = lwp_sema_post */ - "#149", /* 149 = lwp_sema_trywait */ - "#150", /* 150 = notused */ - "#151", /* 151 = notused */ - "#152", /* 152 = modctl */ - "svr4_sys_fchroot", /* 153 = svr4_sys_fchroot */ - "svr4_sys_utimes", /* 154 = svr4_sys_utimes */ - "svr4_sys_vhangup", /* 155 = svr4_sys_vhangup */ - "svr4_sys_gettimeofday", /* 156 = svr4_sys_gettimeofday */ - "getitimer", /* 157 = getitimer */ - "setitimer", /* 158 = setitimer */ - "#159", /* 159 = lwp_create */ - "#160", /* 160 = lwp_exit */ - "#161", /* 161 = lwp_suspend */ - "#162", /* 162 = lwp_continue */ - "#163", /* 163 = lwp_kill */ - "#164", /* 164 = lwp_self */ - "#165", /* 165 = lwp_getprivate */ - "#166", /* 166 = lwp_setprivate */ - "#167", /* 167 = lwp_wait */ - "#168", /* 168 = lwp_mutex_unlock */ - "#169", /* 169 = lwp_mutex_lock */ - "#170", /* 170 = lwp_cond_wait */ - "#171", /* 171 = lwp_cond_signal */ - "#172", /* 172 = lwp_cond_broadcast */ - "#173", /* 173 = { */ - "#174", /* 174 = { */ - "svr4_sys_llseek", /* 175 = svr4_sys_llseek */ - "#176", /* 176 = inst_sync */ - "#177", /* 177 = whoknows */ - "#178", /* 178 = kaio */ - "#179", /* 179 = whoknows */ - "#180", /* 180 = whoknows */ - "#181", /* 181 = whoknows */ - "#182", /* 182 = whoknows */ - "#183", /* 183 = whoknows */ - "#184", /* 184 = tsolsys */ - "svr4_sys_acl", /* 185 = svr4_sys_acl */ - "svr4_sys_auditsys", /* 186 = svr4_sys_auditsys */ - "#187", /* 187 = processor_bind */ - "#188", /* 188 = processor_info */ - "#189", /* 189 = p_online */ - "#190", /* 190 = sigqueue */ - "#191", /* 191 = clock_gettime */ - "#192", /* 192 = clock_settime */ - "#193", /* 193 = clock_getres */ - "#194", /* 194 = timer_create */ - "#195", /* 195 = timer_delete */ - "#196", /* 196 = timer_settime */ - "#197", /* 197 = timer_gettime */ - "#198", /* 198 = timer_overrun */ - "nanosleep", /* 199 = nanosleep */ - "svr4_sys_facl", /* 200 = svr4_sys_facl */ - "#201", /* 201 = door */ - "setreuid", /* 202 = setreuid */ - "setregid", /* 203 = setregid */ - "#204", /* 204 = install_utrap */ - "#205", /* 205 = signotify */ - "#206", /* 206 = schedctl */ - "#207", /* 207 = pset */ - "#208", /* 208 = whoknows */ - "svr4_sys_resolvepath", /* 209 = svr4_sys_resolvepath */ - "#210", /* 210 = signotifywait */ - "#211", /* 211 = lwp_sigredirect */ - "#212", /* 212 = lwp_alarm */ - "svr4_sys_getdents64", /* 213 = svr4_sys_getdents64 */ - "svr4_sys_mmap64", /* 214 = svr4_sys_mmap64 */ - "svr4_sys_stat64", /* 215 = svr4_sys_stat64 */ - "svr4_sys_lstat64", /* 216 = svr4_sys_lstat64 */ - "svr4_sys_fstat64", /* 217 = svr4_sys_fstat64 */ - "svr4_sys_statvfs64", /* 218 = svr4_sys_statvfs64 */ - "svr4_sys_fstatvfs64", /* 219 = svr4_sys_fstatvfs64 */ - "svr4_sys_setrlimit64", /* 220 = svr4_sys_setrlimit64 */ - "svr4_sys_getrlimit64", /* 221 = svr4_sys_getrlimit64 */ - "#222", /* 222 = pread64 */ - "#223", /* 223 = pwrite64 */ - "svr4_sys_creat64", /* 224 = svr4_sys_creat64 */ - "svr4_sys_open64", /* 225 = svr4_sys_open64 */ - "#226", /* 226 = rpcsys */ - "#227", /* 227 = whoknows */ - "#228", /* 228 = whoknows */ - "#229", /* 229 = whoknows */ - "svr4_sys_socket", /* 230 = svr4_sys_socket */ - "socketpair", /* 231 = socketpair */ - "bind", /* 232 = bind */ - "listen", /* 233 = listen */ - "accept", /* 234 = accept */ - "connect", /* 235 = connect */ - "shutdown", /* 236 = shutdown */ - "svr4_sys_recv", /* 237 = svr4_sys_recv */ - "recvfrom", /* 238 = recvfrom */ - "recvmsg", /* 239 = recvmsg */ - "svr4_sys_send", /* 240 = svr4_sys_send */ - "sendmsg", /* 241 = sendmsg */ - "svr4_sys_sendto", /* 242 = svr4_sys_sendto */ - "getpeername", /* 243 = getpeername */ - "getsockname", /* 244 = getsockname */ - "getsockopt", /* 245 = getsockopt */ - "setsockopt", /* 246 = setsockopt */ - "#247", /* 247 = sockconfig */ - "#248", /* 248 = { */ - "#249", /* 249 = { */ -}; diff --git a/sys/compat/svr4/svr4_sysconfig.h b/sys/compat/svr4/svr4_sysconfig.h deleted file mode 100644 index a565c8e7893..00000000000 --- a/sys/compat/svr4/svr4_sysconfig.h +++ /dev/null @@ -1,78 +0,0 @@ -/*- - * Copyright (c) 1998 Mark Newton - * Copyright (c) 1995 Christos Zoulas - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * $FreeBSD: stable/11/sys/compat/svr4/svr4_sysconfig.h 193012 2009-05-29 05:37:27Z delphij $ - */ - -#ifndef _SVR4_SYSCONFIG_H_ -#define _SVR4_SYSCONFIG_H_ - -#define SVR4_CONFIG_UNUSED_1 0x01 -#define SVR4_CONFIG_NGROUPS 0x02 -#define SVR4_CONFIG_CHILD_MAX 0x03 -#define SVR4_CONFIG_OPEN_FILES 0x04 -#define SVR4_CONFIG_POSIX_VER 0x05 -#define SVR4_CONFIG_PAGESIZE 0x06 -#define SVR4_CONFIG_CLK_TCK 0x07 -#define SVR4_CONFIG_XOPEN_VER 0x08 -#define SVR4_CONFIG_UNUSED_9 0x09 -#define SVR4_CONFIG_PROF_TCK 0x0a -#define SVR4_CONFIG_NPROC_CONF 0x0b -#define SVR4_CONFIG_NPROC_ONLN 0x0c -#define SVR4_CONFIG_AIO_LISTIO_MAX 0x0d -#define SVR4_CONFIG_AIO_MAX 0x0e -#define SVR4_CONFIG_AIO_PRIO_DELTA_MAX 0x0f -#define SVR4_CONFIG_DELAYTIMER_MAX 0x10 -#define SVR4_CONFIG_MQ_OPEN_MAX 0x11 -#define SVR4_CONFIG_MQ_PRIO_MAX 0x12 -#define SVR4_CONFIG_RTSIG_MAX 0x13 -#define SVR4_CONFIG_SEM_NSEMS_MAX 0x14 -#define SVR4_CONFIG_SEM_VALUE_MAX 0x15 -#define SVR4_CONFIG_SIGQUEUE_MAX 0x16 -#define SVR4_CONFIG_SIGRT_MIN 0x17 -#define SVR4_CONFIG_SIGRT_MAX 0x18 -#define SVR4_CONFIG_TIMER_MAX 0x19 -#define SVR4_CONFIG_PHYS_PAGES 0x1a -#define SVR4_CONFIG_AVPHYS_PAGES 0x1b -#define SVR4_CONFIG_COHERENCY 0x1c -#define SVR4_CONFIG_SPLIT_CACHE 0x1d -#define SVR4_CONFIG_ICACHESZ 0x1e -#define SVR4_CONFIG_DCACHESZ 0x1f -#define SVR4_CONFIG_ICACHELINESZ 0x20 -#define SVR4_CONFIG_DCACHELINESZ 0x21 -#define SVR4_CONFIG_ICACHEBLKSZ 0x22 -#define SVR4_CONFIG_DCACHEBLKSZ 0x23 -#define SVR4_CONFIG_DCACHETBLKSZ 0x24 -#define SVR4_CONFIG_ICACHE_ASSOC 0x25 -#define SVR4_CONFIG_DCACHE_ASSOC 0x26 -#define SVR4_CONFIG_UNUSED_2 0x27 -#define SVR4_CONFIG_UNUSED_3 0x28 -#define SVR4_CONFIG_UNUSED_4 0x29 -#define SVR4_CONFIG_MAXPID 0x2a -#define SVR4_CONFIG_STACK_PROT 0x2b - -#endif /* !_SVR4_SYSCONFIG_H_ */ diff --git a/sys/compat/svr4/svr4_sysent.c b/sys/compat/svr4/svr4_sysent.c deleted file mode 100644 index 2d49ff9b082..00000000000 --- a/sys/compat/svr4/svr4_sysent.c +++ /dev/null @@ -1,271 +0,0 @@ -/* - * System call switch table. - * - * DO NOT EDIT-- this file is automatically generated. - * $FreeBSD: stable/11/sys/compat/svr4/svr4_sysent.c 318164 2017-05-10 23:09:17Z jhb $ - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#define AS(name) (sizeof(struct name) / sizeof(register_t)) - -/* The casts are bogus but will do for now. */ -struct sysent svr4_sysent[] = { - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 0 = unused */ - { AS(sys_exit_args), (sy_call_t *)sys_sys_exit, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 1 = exit */ - { 0, (sy_call_t *)sys_fork, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 2 = fork */ - { AS(read_args), (sy_call_t *)sys_read, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 3 = read */ - { AS(write_args), (sy_call_t *)sys_write, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 4 = write */ - { AS(svr4_sys_open_args), (sy_call_t *)svr4_sys_open, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 5 = svr4_sys_open */ - { AS(close_args), (sy_call_t *)sys_close, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 6 = close */ - { AS(svr4_sys_wait_args), (sy_call_t *)svr4_sys_wait, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 7 = svr4_sys_wait */ - { AS(svr4_sys_creat_args), (sy_call_t *)svr4_sys_creat, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 8 = svr4_sys_creat */ - { AS(link_args), (sy_call_t *)sys_link, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 9 = link */ - { AS(unlink_args), (sy_call_t *)sys_unlink, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 10 = unlink */ - { AS(svr4_sys_execv_args), (sy_call_t *)svr4_sys_execv, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 11 = svr4_sys_execv */ - { AS(chdir_args), (sy_call_t *)sys_chdir, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 12 = chdir */ - { AS(svr4_sys_time_args), (sy_call_t *)svr4_sys_time, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 13 = svr4_sys_time */ - { AS(svr4_sys_mknod_args), (sy_call_t *)svr4_sys_mknod, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 14 = svr4_sys_mknod */ - { AS(chmod_args), (sy_call_t *)sys_chmod, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 15 = chmod */ - { AS(chown_args), (sy_call_t *)sys_chown, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 16 = chown */ - { AS(svr4_sys_break_args), (sy_call_t *)svr4_sys_break, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 17 = svr4_sys_break */ - { AS(svr4_sys_stat_args), (sy_call_t *)svr4_sys_stat, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 18 = svr4_sys_stat */ - { AS(lseek_args), (sy_call_t *)sys_lseek, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 19 = lseek */ - { 0, (sy_call_t *)sys_getpid, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 20 = getpid */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 21 = old_mount */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 22 = sysv_umount */ - { AS(setuid_args), (sy_call_t *)sys_setuid, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 23 = setuid */ - { 0, (sy_call_t *)sys_getuid, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 24 = getuid */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 25 = stime */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 26 = ptrace */ - { AS(svr4_sys_alarm_args), (sy_call_t *)svr4_sys_alarm, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 27 = svr4_sys_alarm */ - { AS(svr4_sys_fstat_args), (sy_call_t *)svr4_sys_fstat, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 28 = svr4_sys_fstat */ - { 0, (sy_call_t *)svr4_sys_pause, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 29 = svr4_sys_pause */ - { AS(svr4_sys_utime_args), (sy_call_t *)svr4_sys_utime, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 30 = svr4_sys_utime */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 31 = stty */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 32 = gtty */ - { AS(svr4_sys_access_args), (sy_call_t *)svr4_sys_access, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 33 = svr4_sys_access */ - { AS(svr4_sys_nice_args), (sy_call_t *)svr4_sys_nice, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 34 = svr4_sys_nice */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 35 = statfs */ - { 0, (sy_call_t *)sys_sync, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 36 = sync */ - { AS(svr4_sys_kill_args), (sy_call_t *)svr4_sys_kill, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 37 = svr4_sys_kill */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 38 = fstatfs */ - { AS(svr4_sys_pgrpsys_args), (sy_call_t *)svr4_sys_pgrpsys, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 39 = svr4_sys_pgrpsys */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 40 = xenix */ - { AS(dup_args), (sy_call_t *)sys_dup, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 41 = dup */ - { 0, (sy_call_t *)svr4_pipe, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 42 = svr4_pipe */ - { AS(svr4_sys_times_args), (sy_call_t *)svr4_sys_times, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 43 = svr4_sys_times */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 44 = profil */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 45 = plock */ - { AS(setgid_args), (sy_call_t *)sys_setgid, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 46 = setgid */ - { 0, (sy_call_t *)sys_getgid, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 47 = getgid */ - { AS(svr4_sys_signal_args), (sy_call_t *)svr4_sys_signal, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 48 = svr4_sys_signal */ - { AS(svr4_sys_msgsys_args), (sy_call_t *)svr4_sys_msgsys, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 49 = svr4_sys_msgsys */ - { AS(svr4_sys_sysarch_args), (sy_call_t *)svr4_sys_sysarch, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 50 = svr4_sys_sysarch */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 51 = acct */ - { AS(svr4_sys_shmsys_args), (sy_call_t *)svr4_sys_shmsys, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 52 = svr4_sys_shmsys */ - { AS(svr4_sys_semsys_args), (sy_call_t *)svr4_sys_semsys, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 53 = svr4_sys_semsys */ - { AS(svr4_sys_ioctl_args), (sy_call_t *)svr4_sys_ioctl, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 54 = svr4_sys_ioctl */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 55 = uadmin */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 56 = exch */ - { AS(svr4_sys_utssys_args), (sy_call_t *)svr4_sys_utssys, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 57 = svr4_sys_utssys */ - { AS(fsync_args), (sy_call_t *)sys_fsync, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 58 = fsync */ - { AS(svr4_sys_execve_args), (sy_call_t *)svr4_sys_execve, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 59 = svr4_sys_execve */ - { AS(umask_args), (sy_call_t *)sys_umask, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 60 = umask */ - { AS(chroot_args), (sy_call_t *)sys_chroot, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 61 = chroot */ - { AS(svr4_sys_fcntl_args), (sy_call_t *)svr4_sys_fcntl, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 62 = svr4_sys_fcntl */ - { AS(svr4_sys_ulimit_args), (sy_call_t *)svr4_sys_ulimit, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 63 = svr4_sys_ulimit */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 64 = reserved */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 65 = reserved */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 66 = reserved */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 67 = reserved */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 68 = reserved */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 69 = reserved */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 70 = advfs */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 71 = unadvfs */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 72 = rmount */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 73 = rumount */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 74 = rfstart */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 75 = sigret */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 76 = rdebug */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 77 = rfstop */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 78 = rfsys */ - { AS(rmdir_args), (sy_call_t *)sys_rmdir, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 79 = rmdir */ - { AS(mkdir_args), (sy_call_t *)sys_mkdir, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 80 = mkdir */ - { AS(svr4_sys_getdents_args), (sy_call_t *)svr4_sys_getdents, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 81 = svr4_sys_getdents */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 82 = libattach */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 83 = libdetach */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 84 = sysfs */ - { AS(svr4_sys_getmsg_args), (sy_call_t *)svr4_sys_getmsg, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 85 = svr4_sys_getmsg */ - { AS(svr4_sys_putmsg_args), (sy_call_t *)svr4_sys_putmsg, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 86 = svr4_sys_putmsg */ - { AS(svr4_sys_poll_args), (sy_call_t *)svr4_sys_poll, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 87 = svr4_sys_poll */ - { AS(svr4_sys_lstat_args), (sy_call_t *)svr4_sys_lstat, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 88 = svr4_sys_lstat */ - { AS(symlink_args), (sy_call_t *)sys_symlink, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 89 = symlink */ - { AS(readlink_args), (sy_call_t *)sys_readlink, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 90 = readlink */ - { AS(getgroups_args), (sy_call_t *)sys_getgroups, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 91 = getgroups */ - { AS(setgroups_args), (sy_call_t *)sys_setgroups, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 92 = setgroups */ - { AS(fchmod_args), (sy_call_t *)sys_fchmod, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 93 = fchmod */ - { AS(fchown_args), (sy_call_t *)sys_fchown, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 94 = fchown */ - { AS(svr4_sys_sigprocmask_args), (sy_call_t *)svr4_sys_sigprocmask, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 95 = svr4_sys_sigprocmask */ - { AS(svr4_sys_sigsuspend_args), (sy_call_t *)svr4_sys_sigsuspend, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 96 = svr4_sys_sigsuspend */ - { AS(svr4_sys_sigaltstack_args), (sy_call_t *)svr4_sys_sigaltstack, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 97 = svr4_sys_sigaltstack */ - { AS(svr4_sys_sigaction_args), (sy_call_t *)svr4_sys_sigaction, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 98 = svr4_sys_sigaction */ - { AS(svr4_sys_sigpending_args), (sy_call_t *)svr4_sys_sigpending, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 99 = svr4_sys_sigpending */ - { AS(svr4_sys_context_args), (sy_call_t *)svr4_sys_context, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 100 = svr4_sys_context */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 101 = evsys */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 102 = evtrapret */ - { AS(svr4_sys_statvfs_args), (sy_call_t *)svr4_sys_statvfs, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 103 = svr4_sys_statvfs */ - { AS(svr4_sys_fstatvfs_args), (sy_call_t *)svr4_sys_fstatvfs, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 104 = svr4_sys_fstatvfs */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 105 = whoknows */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 106 = nfssvc */ - { AS(svr4_sys_waitsys_args), (sy_call_t *)svr4_sys_waitsys, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 107 = svr4_sys_waitsys */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 108 = sigsendsys */ - { AS(svr4_sys_hrtsys_args), (sy_call_t *)svr4_sys_hrtsys, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 109 = svr4_sys_hrtsys */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 110 = acancel */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 111 = async */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 112 = priocntlsys */ - { AS(svr4_sys_pathconf_args), (sy_call_t *)svr4_sys_pathconf, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 113 = svr4_sys_pathconf */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 114 = mincore */ - { AS(svr4_sys_mmap_args), (sy_call_t *)svr4_sys_mmap, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 115 = svr4_sys_mmap */ - { AS(mprotect_args), (sy_call_t *)sys_mprotect, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 116 = mprotect */ - { AS(munmap_args), (sy_call_t *)sys_munmap, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 117 = munmap */ - { AS(svr4_sys_fpathconf_args), (sy_call_t *)svr4_sys_fpathconf, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 118 = svr4_sys_fpathconf */ - { 0, (sy_call_t *)sys_vfork, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 119 = vfork */ - { AS(fchdir_args), (sy_call_t *)sys_fchdir, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 120 = fchdir */ - { AS(readv_args), (sy_call_t *)sys_readv, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 121 = readv */ - { AS(writev_args), (sy_call_t *)sys_writev, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 122 = writev */ - { AS(svr4_sys_xstat_args), (sy_call_t *)svr4_sys_xstat, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 123 = svr4_sys_xstat */ - { AS(svr4_sys_lxstat_args), (sy_call_t *)svr4_sys_lxstat, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 124 = svr4_sys_lxstat */ - { AS(svr4_sys_fxstat_args), (sy_call_t *)svr4_sys_fxstat, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 125 = svr4_sys_fxstat */ - { AS(svr4_sys_xmknod_args), (sy_call_t *)svr4_sys_xmknod, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 126 = svr4_sys_xmknod */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 127 = clocal */ - { AS(svr4_sys_setrlimit_args), (sy_call_t *)svr4_sys_setrlimit, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 128 = svr4_sys_setrlimit */ - { AS(svr4_sys_getrlimit_args), (sy_call_t *)svr4_sys_getrlimit, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 129 = svr4_sys_getrlimit */ - { AS(lchown_args), (sy_call_t *)sys_lchown, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 130 = lchown */ - { AS(svr4_sys_memcntl_args), (sy_call_t *)svr4_sys_memcntl, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 131 = svr4_sys_memcntl */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 132 = getpmsg */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 133 = putpmsg */ - { AS(rename_args), (sy_call_t *)sys_rename, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 134 = rename */ - { AS(svr4_sys_uname_args), (sy_call_t *)svr4_sys_uname, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 135 = svr4_sys_uname */ - { AS(setegid_args), (sy_call_t *)sys_setegid, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 136 = setegid */ - { AS(svr4_sys_sysconfig_args), (sy_call_t *)svr4_sys_sysconfig, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 137 = svr4_sys_sysconfig */ - { AS(adjtime_args), (sy_call_t *)sys_adjtime, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 138 = adjtime */ - { AS(svr4_sys_systeminfo_args), (sy_call_t *)svr4_sys_systeminfo, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 139 = svr4_sys_systeminfo */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 140 = notused */ - { AS(seteuid_args), (sy_call_t *)sys_seteuid, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 141 = seteuid */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 142 = vtrace */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 143 = { */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 144 = sigtimedwait */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 145 = lwp_info */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 146 = yield */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 147 = lwp_sema_wait */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 148 = lwp_sema_post */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 149 = lwp_sema_trywait */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 150 = notused */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 151 = notused */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 152 = modctl */ - { AS(svr4_sys_fchroot_args), (sy_call_t *)svr4_sys_fchroot, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 153 = svr4_sys_fchroot */ - { AS(svr4_sys_utimes_args), (sy_call_t *)svr4_sys_utimes, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 154 = svr4_sys_utimes */ - { 0, (sy_call_t *)svr4_sys_vhangup, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 155 = svr4_sys_vhangup */ - { AS(svr4_sys_gettimeofday_args), (sy_call_t *)svr4_sys_gettimeofday, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 156 = svr4_sys_gettimeofday */ - { AS(getitimer_args), (sy_call_t *)sys_getitimer, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 157 = getitimer */ - { AS(setitimer_args), (sy_call_t *)sys_setitimer, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 158 = setitimer */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 159 = lwp_create */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 160 = lwp_exit */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 161 = lwp_suspend */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 162 = lwp_continue */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 163 = lwp_kill */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 164 = lwp_self */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 165 = lwp_getprivate */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 166 = lwp_setprivate */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 167 = lwp_wait */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 168 = lwp_mutex_unlock */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 169 = lwp_mutex_lock */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 170 = lwp_cond_wait */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 171 = lwp_cond_signal */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 172 = lwp_cond_broadcast */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 173 = { */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 174 = { */ - { AS(svr4_sys_llseek_args), (sy_call_t *)svr4_sys_llseek, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 175 = svr4_sys_llseek */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 176 = inst_sync */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 177 = whoknows */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 178 = kaio */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 179 = whoknows */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 180 = whoknows */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 181 = whoknows */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 182 = whoknows */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 183 = whoknows */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 184 = tsolsys */ - { AS(svr4_sys_acl_args), (sy_call_t *)svr4_sys_acl, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 185 = svr4_sys_acl */ - { AS(svr4_sys_auditsys_args), (sy_call_t *)svr4_sys_auditsys, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 186 = svr4_sys_auditsys */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 187 = processor_bind */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 188 = processor_info */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 189 = p_online */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 190 = sigqueue */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 191 = clock_gettime */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 192 = clock_settime */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 193 = clock_getres */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 194 = timer_create */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 195 = timer_delete */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 196 = timer_settime */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 197 = timer_gettime */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 198 = timer_overrun */ - { AS(nanosleep_args), (sy_call_t *)sys_nanosleep, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 199 = nanosleep */ - { AS(svr4_sys_facl_args), (sy_call_t *)svr4_sys_facl, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 200 = svr4_sys_facl */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 201 = door */ - { AS(setreuid_args), (sy_call_t *)sys_setreuid, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 202 = setreuid */ - { AS(setregid_args), (sy_call_t *)sys_setregid, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 203 = setregid */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 204 = install_utrap */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 205 = signotify */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 206 = schedctl */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 207 = pset */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 208 = whoknows */ - { AS(svr4_sys_resolvepath_args), (sy_call_t *)svr4_sys_resolvepath, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 209 = svr4_sys_resolvepath */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 210 = signotifywait */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 211 = lwp_sigredirect */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 212 = lwp_alarm */ - { AS(svr4_sys_getdents64_args), (sy_call_t *)svr4_sys_getdents64, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 213 = svr4_sys_getdents64 */ - { AS(svr4_sys_mmap64_args), (sy_call_t *)svr4_sys_mmap64, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 214 = svr4_sys_mmap64 */ - { AS(svr4_sys_stat64_args), (sy_call_t *)svr4_sys_stat64, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 215 = svr4_sys_stat64 */ - { AS(svr4_sys_lstat64_args), (sy_call_t *)svr4_sys_lstat64, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 216 = svr4_sys_lstat64 */ - { AS(svr4_sys_fstat64_args), (sy_call_t *)svr4_sys_fstat64, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 217 = svr4_sys_fstat64 */ - { AS(svr4_sys_statvfs64_args), (sy_call_t *)svr4_sys_statvfs64, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 218 = svr4_sys_statvfs64 */ - { AS(svr4_sys_fstatvfs64_args), (sy_call_t *)svr4_sys_fstatvfs64, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 219 = svr4_sys_fstatvfs64 */ - { AS(svr4_sys_setrlimit64_args), (sy_call_t *)svr4_sys_setrlimit64, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 220 = svr4_sys_setrlimit64 */ - { AS(svr4_sys_getrlimit64_args), (sy_call_t *)svr4_sys_getrlimit64, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 221 = svr4_sys_getrlimit64 */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 222 = pread64 */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 223 = pwrite64 */ - { AS(svr4_sys_creat64_args), (sy_call_t *)svr4_sys_creat64, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 224 = svr4_sys_creat64 */ - { AS(svr4_sys_open64_args), (sy_call_t *)svr4_sys_open64, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 225 = svr4_sys_open64 */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 226 = rpcsys */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 227 = whoknows */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 228 = whoknows */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 229 = whoknows */ - { AS(svr4_sys_socket_args), (sy_call_t *)svr4_sys_socket, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 230 = svr4_sys_socket */ - { AS(socketpair_args), (sy_call_t *)sys_socketpair, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 231 = socketpair */ - { AS(bind_args), (sy_call_t *)sys_bind, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 232 = bind */ - { AS(listen_args), (sy_call_t *)sys_listen, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 233 = listen */ - { AS(accept_args), (sy_call_t *)sys_accept, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 234 = accept */ - { AS(connect_args), (sy_call_t *)sys_connect, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 235 = connect */ - { AS(shutdown_args), (sy_call_t *)sys_shutdown, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 236 = shutdown */ - { AS(svr4_sys_recv_args), (sy_call_t *)svr4_sys_recv, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 237 = svr4_sys_recv */ - { AS(recvfrom_args), (sy_call_t *)sys_recvfrom, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 238 = recvfrom */ - { AS(recvmsg_args), (sy_call_t *)sys_recvmsg, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 239 = recvmsg */ - { AS(svr4_sys_send_args), (sy_call_t *)svr4_sys_send, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 240 = svr4_sys_send */ - { AS(sendmsg_args), (sy_call_t *)sys_sendmsg, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 241 = sendmsg */ - { AS(svr4_sys_sendto_args), (sy_call_t *)svr4_sys_sendto, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 242 = svr4_sys_sendto */ - { AS(getpeername_args), (sy_call_t *)sys_getpeername, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 243 = getpeername */ - { AS(getsockname_args), (sy_call_t *)sys_getsockname, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 244 = getsockname */ - { AS(getsockopt_args), (sy_call_t *)sys_getsockopt, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 245 = getsockopt */ - { AS(setsockopt_args), (sy_call_t *)sys_setsockopt, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 246 = setsockopt */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 247 = sockconfig */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 248 = { */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 249 = { */ -}; diff --git a/sys/compat/svr4/svr4_systeminfo.h b/sys/compat/svr4/svr4_systeminfo.h deleted file mode 100644 index 2a0c2027434..00000000000 --- a/sys/compat/svr4/svr4_systeminfo.h +++ /dev/null @@ -1,50 +0,0 @@ -/*- - * Copyright (c) 1998 Mark Newton - * Copyright (c) 1994 Christos Zoulas - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * $FreeBSD: stable/11/sys/compat/svr4/svr4_systeminfo.h 139743 2005-01-05 22:34:37Z imp $ - */ - -#ifndef _SVR4_SYSTEMINFO_H_ -#define _SVR4_SYSTEMINFO_H_ - -#define SVR4_SI_SYSNAME 1 -#define SVR4_SI_HOSTNAME 2 -#define SVR4_SI_RELEASE 3 -#define SVR4_SI_VERSION 4 -#define SVR4_SI_MACHINE 5 -#define SVR4_SI_ARCHITECTURE 6 -#define SVR4_SI_HW_SERIAL 7 -#define SVR4_SI_HW_PROVIDER 8 -#define SVR4_SI_SRPC_DOMAIN 9 -#define SVR4_SI_SET_HOSTNAME 258 -#define SVR4_SI_SET_SRPC_DOMAIN 265 -#define SVR4_SI_SET_KERB_REALM 266 -#define SVR4_SI_KERB_REALM 267 -#define SVR4_SI_PLATFORM 513 -#define SVR4_SI_ISALIST 514 - -#endif /* !_SVR4_SYSTEMINFO_H_ */ diff --git a/sys/compat/svr4/svr4_sysvec.c b/sys/compat/svr4/svr4_sysvec.c deleted file mode 100644 index 2750011909d..00000000000 --- a/sys/compat/svr4/svr4_sysvec.c +++ /dev/null @@ -1,312 +0,0 @@ -/*- - * Copyright (c) 1998 Mark Newton - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by Christos Zoulas. - * 4. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include - -/* XXX we use functions that might not exist. */ -#include "opt_compat.h" - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -int bsd_to_svr4_errno[ELAST+1] = { - 0, - SVR4_EPERM, - SVR4_ENOENT, - SVR4_ESRCH, - SVR4_EINTR, - SVR4_EIO, - SVR4_ENXIO, - SVR4_E2BIG, - SVR4_ENOEXEC, - SVR4_EBADF, - SVR4_ECHILD, - SVR4_EDEADLK, - SVR4_ENOMEM, - SVR4_EACCES, - SVR4_EFAULT, - SVR4_ENOTBLK, - SVR4_EBUSY, - SVR4_EEXIST, - SVR4_EXDEV, - SVR4_ENODEV, - SVR4_ENOTDIR, - SVR4_EISDIR, - SVR4_EINVAL, - SVR4_ENFILE, - SVR4_EMFILE, - SVR4_ENOTTY, - SVR4_ETXTBSY, - SVR4_EFBIG, - SVR4_ENOSPC, - SVR4_ESPIPE, - SVR4_EROFS, - SVR4_EMLINK, - SVR4_EPIPE, - SVR4_EDOM, - SVR4_ERANGE, - SVR4_EAGAIN, - SVR4_EINPROGRESS, - SVR4_EALREADY, - SVR4_ENOTSOCK, - SVR4_EDESTADDRREQ, - SVR4_EMSGSIZE, - SVR4_EPROTOTYPE, - SVR4_ENOPROTOOPT, - SVR4_EPROTONOSUPPORT, - SVR4_ESOCKTNOSUPPORT, - SVR4_EOPNOTSUPP, - SVR4_EPFNOSUPPORT, - SVR4_EAFNOSUPPORT, - SVR4_EADDRINUSE, - SVR4_EADDRNOTAVAIL, - SVR4_ENETDOWN, - SVR4_ENETUNREACH, - SVR4_ENETRESET, - SVR4_ECONNABORTED, - SVR4_ECONNRESET, - SVR4_ENOBUFS, - SVR4_EISCONN, - SVR4_ENOTCONN, - SVR4_ESHUTDOWN, - SVR4_ETOOMANYREFS, - SVR4_ETIMEDOUT, - SVR4_ECONNREFUSED, - SVR4_ELOOP, - SVR4_ENAMETOOLONG, - SVR4_EHOSTDOWN, - SVR4_EHOSTUNREACH, - SVR4_ENOTEMPTY, - SVR4_EPROCLIM, - SVR4_EUSERS, - SVR4_EDQUOT, - SVR4_ESTALE, - SVR4_EREMOTE, - SVR4_EBADRPC, - SVR4_ERPCMISMATCH, - SVR4_EPROGUNAVAIL, - SVR4_EPROGMISMATCH, - SVR4_EPROCUNAVAIL, - SVR4_ENOLCK, - SVR4_ENOSYS, - SVR4_EFTYPE, - SVR4_EAUTH, - SVR4_ENEEDAUTH, - SVR4_EIDRM, - SVR4_ENOMSG, -}; - - -static int svr4_fixup(register_t **stack_base, struct image_params *imgp); - -extern struct sysent svr4_sysent[]; -#undef szsigcode -#undef sigcode - -extern int svr4_szsigcode; -extern char svr4_sigcode[]; - -struct sysentvec svr4_sysvec = { - .sv_size = SVR4_SYS_MAXSYSCALL, - .sv_table = svr4_sysent, - .sv_mask = 0xff, - .sv_errsize = ELAST, /* ELAST */ - .sv_errtbl = bsd_to_svr4_errno, - .sv_transtrap = NULL, - .sv_fixup = svr4_fixup, - .sv_sendsig = svr4_sendsig, - .sv_sigcode = svr4_sigcode, - .sv_szsigcode = &svr4_szsigcode, - .sv_name = "SVR4", - .sv_coredump = elf32_coredump, - .sv_imgact_try = NULL, - .sv_minsigstksz = SVR4_MINSIGSTKSZ, - .sv_pagesize = PAGE_SIZE, - .sv_minuser = VM_MIN_ADDRESS, - .sv_maxuser = VM_MAXUSER_ADDRESS, - .sv_usrstack = USRSTACK, - .sv_psstrings = PS_STRINGS, - .sv_stackprot = VM_PROT_ALL, - .sv_copyout_strings = exec_copyout_strings, - .sv_setregs = exec_setregs, - .sv_fixlimit = NULL, - .sv_maxssiz = NULL, - .sv_flags = SV_ABI_UNDEF | SV_IA32 | SV_ILP32, - .sv_set_syscall_retval = cpu_set_syscall_retval, - .sv_fetch_syscall_args = cpu_fetch_syscall_args, - .sv_syscallnames = NULL, - .sv_schedtail = NULL, - .sv_thread_detach = NULL, - .sv_trap = NULL, -}; - -const char svr4_emul_path[] = "/compat/svr4"; - -Elf32_Brandinfo svr4_brand = { - .brand = ELFOSABI_SYSV, - .machine = EM_386, /* XXX only implemented for x86 so far. */ - .compat_3_brand = "SVR4", - .emul_path = svr4_emul_path, - .interp_path = "/lib/libc.so.1", - .sysvec = &svr4_sysvec, - .interp_newpath = NULL, - .brand_note = NULL, - .flags = 0 -}; - -static int -svr4_fixup(register_t **stack_base, struct image_params *imgp) -{ - Elf32_Auxargs *args; - register_t *pos; - - KASSERT(curthread->td_proc == imgp->proc, - ("unsafe svr4_fixup(), should be curproc")); - args = (Elf32_Auxargs *)imgp->auxargs; - pos = *stack_base + (imgp->args->argc + imgp->args->envc + 2); - - if (args->execfd != -1) - AUXARGS_ENTRY(pos, AT_EXECFD, args->execfd); - AUXARGS_ENTRY(pos, AT_PHDR, args->phdr); - AUXARGS_ENTRY(pos, AT_PHENT, args->phent); - AUXARGS_ENTRY(pos, AT_PHNUM, args->phnum); - AUXARGS_ENTRY(pos, AT_PAGESZ, args->pagesz); - AUXARGS_ENTRY(pos, AT_FLAGS, args->flags); - AUXARGS_ENTRY(pos, AT_ENTRY, args->entry); - AUXARGS_ENTRY(pos, AT_BASE, args->base); - AUXARGS_ENTRY(pos, AT_UID, imgp->proc->p_ucred->cr_ruid); - AUXARGS_ENTRY(pos, AT_EUID, imgp->proc->p_ucred->cr_svuid); - AUXARGS_ENTRY(pos, AT_GID, imgp->proc->p_ucred->cr_rgid); - AUXARGS_ENTRY(pos, AT_EGID, imgp->proc->p_ucred->cr_svgid); - AUXARGS_ENTRY(pos, AT_NULL, 0); - - free(imgp->auxargs, M_TEMP); - imgp->auxargs = NULL; - - (*stack_base)--; - **stack_base = (register_t)imgp->args->argc; - return 0; -} - -/* - * Search an alternate path before passing pathname arguments on - * to system calls. Useful for keeping a separate 'emulation tree'. - * - * If cflag is set, we check if an attempt can be made to create - * the named file, i.e. we check if the directory it should - * be in exists. - */ -int -svr4_emul_find(struct thread *td, char *path, enum uio_seg pathseg, - char **pbuf, int create) -{ - - return (kern_alternate_path(td, svr4_emul_path, path, pathseg, pbuf, - create, AT_FDCWD)); -} - -static int -svr4_elf_modevent(module_t mod, int type, void *data) -{ - int error; - - error = 0; - - switch(type) { - case MOD_LOAD: - if (elf32_insert_brand_entry(&svr4_brand) < 0) { - printf("cannot insert svr4 elf brand handler\n"); - error = EINVAL; - break; - } - if (bootverbose) - printf("svr4 ELF exec handler installed\n"); - svr4_sockcache_init(); - break; - case MOD_UNLOAD: - /* Only allow the emulator to be removed if it isn't in use. */ - if (elf32_brand_inuse(&svr4_brand) != 0) { - error = EBUSY; - } else if (elf32_remove_brand_entry(&svr4_brand) < 0) { - error = EINVAL; - } - - if (error) { - printf("Could not deinstall ELF interpreter entry (error %d)\n", - error); - break; - } - if (bootverbose) - printf("svr4 ELF exec handler removed\n"); - svr4_sockcache_destroy(); - break; - default: - return (EOPNOTSUPP); - break; - } - return error; -} - -static moduledata_t svr4_elf_mod = { - "svr4elf", - svr4_elf_modevent, - 0 -}; -DECLARE_MODULE_TIED(svr4elf, svr4_elf_mod, SI_SUB_EXEC, SI_ORDER_ANY); -MODULE_VERSION(svr4elf, 1); diff --git a/sys/compat/svr4/svr4_termios.c b/sys/compat/svr4/svr4_termios.c deleted file mode 100644 index 79d1f767f12..00000000000 --- a/sys/compat/svr4/svr4_termios.c +++ /dev/null @@ -1,611 +0,0 @@ -/*- - * Copyright (c) 1998 Mark Newton - * Copyright (c) 1994 Christos Zoulas - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include - -#include -#include -#include -#include -#include -#include - -#include - -#include -#include -#include -#include - -#ifndef __CONCAT3 -# if __STDC__ -# define __CONCAT3(a,b,c) a ## b ## c -# else -# define __CONCAT3(a,b,c) a/**/b/**/c -# endif -#endif - -static u_long bsd_to_svr4_speed(u_long, u_long); -static u_long svr4_to_bsd_speed(u_long, u_long); -static void svr4_to_bsd_termios(const struct svr4_termios *, - struct termios *, int); -static void bsd_to_svr4_termios(const struct termios *, - struct svr4_termios *); -static void svr4_termio_to_termios(const struct svr4_termio *, - struct svr4_termios *); -static void svr4_termios_to_termio(const struct svr4_termios *, - struct svr4_termio *); -#ifdef DEBUG_SVR4 -static void print_svr4_termios(const struct svr4_termios *); -static void print_bsd_termios(const struct termios *); -#endif /* DEBUG_SVR4 */ - -#define undefined_char(a,b) /**/ -#define undefined_flag1(f,a,b) /**/ -#define undefined_flag2(f,a,b,c1,t1,c2,t2) /**/ -#define undefined_flag4(f,a,b,c1,t1,c2,t2,c3,t3,c4,t4) /**/ - -#define svr4_to_bsd_char(a,b) \ - if (new || __CONCAT3(SVR4_,a,b) < SVR4_NCC) { \ - if (st->c_cc[__CONCAT3(SVR4_,a,b)] == SVR4_POSIX_VDISABLE) \ - bt->c_cc[__CONCAT(a,b)] = _POSIX_VDISABLE; \ - else \ - bt->c_cc[__CONCAT(a,b)] = st->c_cc[__CONCAT3(SVR4_,a,b)]; \ - } - -#define svr4_to_bsd_flag1(f,a,b) \ - if (new || __CONCAT3(SVR4_,a,b) < 0200000) { \ - if (st->f & __CONCAT3(SVR4_,a,b)) \ - bt->f |= __CONCAT(a,b); \ - else \ - bt->f &= ~__CONCAT(a,b); \ - } - -#define svr4_to_bsd_flag2(f,a,b,c1,t1,c2,t2) \ - if (new || __CONCAT3(SVR4_,a,b) < 0200000) { \ - bt->f &= ~__CONCAT(a,b); \ - switch (st->f & __CONCAT3(SVR4_,a,b)) { \ - case __CONCAT3(SVR4_,c1,t1): bt->f |= __CONCAT(c1,t1); break; \ - case __CONCAT3(SVR4_,c2,t2): bt->f |= __CONCAT(c2,t2); break; \ - } \ - } - -#define svr4_to_bsd_flag4(f,a,b,c1,t1,c2,t2,c3,t3,c4,t4) \ - if (new || __CONCAT3(SVR4_,a,b) < 0200000) { \ - bt->f &= ~__CONCAT(a,b); \ - switch (st->f & __CONCAT3(SVR4_,a,b)) { \ - case __CONCAT3(SVR4_,c1,t1): bt->f |= __CONCAT(c1,t1); break; \ - case __CONCAT3(SVR4_,c2,t2): bt->f |= __CONCAT(c2,t2); break; \ - case __CONCAT3(SVR4_,c3,t3): bt->f |= __CONCAT(c3,t3); break; \ - case __CONCAT3(SVR4_,c4,t4): bt->f |= __CONCAT(c4,t4); break; \ - } \ - } - - -#define bsd_to_svr4_char(a,b) \ - if (bt->c_cc[__CONCAT(a,b)] == _POSIX_VDISABLE) \ - st->c_cc[__CONCAT3(SVR4_,a,b)] = SVR4_POSIX_VDISABLE; \ - else \ - st->c_cc[__CONCAT3(SVR4_,a,b)] = bt->c_cc[__CONCAT(a,b)] - -#define bsd_to_svr4_flag1(f,a,b) \ - if (bt->f & __CONCAT(a,b)) \ - st->f |= __CONCAT3(SVR4_,a,b); \ - else \ - st->f &= ~__CONCAT3(SVR4_,a,b) - -#define bsd_to_svr4_flag2(f,a,b,c1,t1,c2,t2) \ - st->f &= ~__CONCAT(a,b); \ - switch (bt->f & __CONCAT(a,b)) { \ - case __CONCAT(c1,t1): st->f |= __CONCAT3(SVR4_,c1,t1); break; \ - case __CONCAT(c2,t2): st->f |= __CONCAT3(SVR4_,c2,t2); break; \ - } - -#define bsd_to_svr4_flag4(f,a,b,c1,t1,c2,t2,c3,t3,c4,t4) \ - st->f &= ~__CONCAT(a,b); \ - switch (bt->f & __CONCAT(a,b)) { \ - case __CONCAT(c1,t1): st->f |= __CONCAT3(SVR4_,c1,t1); break; \ - case __CONCAT(c2,t2): st->f |= __CONCAT3(SVR4_,c2,t2); break; \ - case __CONCAT(c3,t3): st->f |= __CONCAT3(SVR4_,c3,t3); break; \ - case __CONCAT(c4,t4): st->f |= __CONCAT3(SVR4_,c4,t4); break; \ - } - -#ifdef DEBUG_SVR4 -static void -print_svr4_termios(st) - const struct svr4_termios *st; -{ - int i; - DPRINTF(("SVR4\niflag=%lo oflag=%lo cflag=%lo lflag=%lo\n", - st->c_iflag, st->c_oflag, st->c_cflag, st->c_lflag)); - DPRINTF(("cc: ")); - for (i = 0; i < SVR4_NCCS; i++) - DPRINTF(("%o ", st->c_cc[i])); - DPRINTF(("\n")); -} - - -static void -print_bsd_termios(bt) - const struct termios *bt; -{ - int i; - uprintf("BSD\niflag=%o oflag=%o cflag=%o lflag=%o\n", - bt->c_iflag, bt->c_oflag, bt->c_cflag, bt->c_lflag); - uprintf("cc: "); - for (i = 0; i < NCCS; i++) - uprintf("%o ", bt->c_cc[i]); - uprintf("\n"); -} -#endif /* DEBUG_SVR4 */ - -static u_long -bsd_to_svr4_speed(sp, mask) - u_long sp; - u_long mask; -{ - switch (sp) { -#undef getval -#define getval(a,b) case __CONCAT(a,b): sp = __CONCAT3(SVR4_,a,b) - getval(B,0); - getval(B,50); - getval(B,75); - getval(B,110); - getval(B,134); - getval(B,150); - getval(B,200); - getval(B,300); - getval(B,600); - getval(B,1200); - getval(B,1800); - getval(B,2400); - getval(B,4800); - getval(B,9600); - getval(B,19200); - getval(B,38400); - getval(B,57600); - getval(B,115200); - default: sp = SVR4_B9600; /* XXX */ - } - - while ((mask & 1) == 0) { - mask >>= 1; - sp <<= 1; - } - - return sp; -} - - -static u_long -svr4_to_bsd_speed(sp, mask) - u_long sp; - u_long mask; -{ - while ((mask & 1) == 0) { - mask >>= 1; - sp >>= 1; - } - - switch (sp & mask) { -#undef getval -#define getval(a,b) case __CONCAT3(SVR4_,a,b): return __CONCAT(a,b) - getval(B,0); - getval(B,50); - getval(B,75); - getval(B,110); - getval(B,134); - getval(B,150); - getval(B,200); - getval(B,300); - getval(B,600); - getval(B,1200); - getval(B,1800); - getval(B,2400); - getval(B,4800); - getval(B,9600); - getval(B,19200); - getval(B,38400); - getval(B,57600); - getval(B,115200); - default: return B9600; /* XXX */ - } -} - - -static void -svr4_to_bsd_termios(st, bt, new) - const struct svr4_termios *st; - struct termios *bt; - int new; -{ - /* control characters */ - /* - * We process VMIN and VTIME first, - * because they are shared with VEOF and VEOL - */ - svr4_to_bsd_char(V,MIN); - svr4_to_bsd_char(V,TIME); - - svr4_to_bsd_char(V,INTR); - svr4_to_bsd_char(V,QUIT); - svr4_to_bsd_char(V,ERASE); - svr4_to_bsd_char(V,KILL); - svr4_to_bsd_char(V,EOF); - svr4_to_bsd_char(V,EOL); - svr4_to_bsd_char(V,EOL2); - undefined_char(V,SWTCH); - svr4_to_bsd_char(V,START); - svr4_to_bsd_char(V,STOP); - svr4_to_bsd_char(V,SUSP); - svr4_to_bsd_char(V,DSUSP); - svr4_to_bsd_char(V,REPRINT); - svr4_to_bsd_char(V,DISCARD); - svr4_to_bsd_char(V,WERASE); - svr4_to_bsd_char(V,LNEXT); - - /* Input modes */ - svr4_to_bsd_flag1(c_iflag,I,GNBRK); - svr4_to_bsd_flag1(c_iflag,B,RKINT); - svr4_to_bsd_flag1(c_iflag,I,GNPAR); - svr4_to_bsd_flag1(c_iflag,P,ARMRK); - svr4_to_bsd_flag1(c_iflag,I,NPCK); - svr4_to_bsd_flag1(c_iflag,I,STRIP); - svr4_to_bsd_flag1(c_iflag,I,NLCR); - svr4_to_bsd_flag1(c_iflag,I,GNCR); - svr4_to_bsd_flag1(c_iflag,I,CRNL); - undefined_flag1(c_iflag,I,UCLC); - svr4_to_bsd_flag1(c_iflag,I,XON); - svr4_to_bsd_flag1(c_iflag,I,XANY); - svr4_to_bsd_flag1(c_iflag,I,XOFF); - svr4_to_bsd_flag1(c_iflag,I,MAXBEL); - undefined_flag1(c_iflag,D,OSMODE); - - /* Output modes */ - svr4_to_bsd_flag1(c_oflag,O,POST); - undefined_flag1(c_oflag,O,LCUC); - svr4_to_bsd_flag1(c_oflag,O,NLCR); - undefined_flag1(c_oflag,O,CRNL); - undefined_flag1(c_oflag,O,NOCR); - undefined_flag1(c_oflag,O,NLRET); - undefined_flag1(c_oflag,O,FILL); - undefined_flag1(c_oflag,O,FDEL); - undefined_flag2(c_oflag,N,LDLY,N,L0,N,L1); - undefined_flag4(c_oflag,C,RDLY,C,R0,C,R1,C,R2,C,R3); - undefined_flag4(c_oflag,T,ABDLY,T,AB0,T,AB1,T,AB2,T,AB3); - undefined_flag2(c_oflag,B,SDLY,B,S0,B,S1); - undefined_flag2(c_oflag,V,TDLY,V,T0,V,T1); - undefined_flag2(c_oflag,F,FDLY,F,F0,F,F1); - undefined_flag1(c_oflag,P,AGEOUT); - undefined_flag1(c_oflag,W,RAP); - - /* Control modes */ - bt->c_ospeed = svr4_to_bsd_speed(st->c_cflag, SVR4_CBAUD); - svr4_to_bsd_flag4(c_cflag,C,SIZE,C,S5,C,S6,C,S7,C,S8) - svr4_to_bsd_flag1(c_cflag,C,STOPB); - svr4_to_bsd_flag1(c_cflag,C,READ); - svr4_to_bsd_flag1(c_cflag,P,ARENB); - svr4_to_bsd_flag1(c_cflag,P,ARODD); - svr4_to_bsd_flag1(c_cflag,H,UPCL); - svr4_to_bsd_flag1(c_cflag,C,LOCAL); - undefined_flag1(c_cflag,R,CV1EN); - undefined_flag1(c_cflag,X,MT1EN); - undefined_flag1(c_cflag,L,OBLK); - undefined_flag1(c_cflag,X,CLUDE); - bt->c_ispeed = svr4_to_bsd_speed(st->c_cflag, SVR4_CIBAUD); - undefined_flag1(c_cflag,P,AREXT); - - /* line discipline modes */ - svr4_to_bsd_flag1(c_lflag,I,SIG); - svr4_to_bsd_flag1(c_lflag,I,CANON); - undefined_flag1(c_lflag,X,CASE); - svr4_to_bsd_flag1(c_lflag,E,CHO); - svr4_to_bsd_flag1(c_lflag,E,CHOE); - svr4_to_bsd_flag1(c_lflag,E,CHOK); - svr4_to_bsd_flag1(c_lflag,E,CHONL); - svr4_to_bsd_flag1(c_lflag,N,OFLSH); - svr4_to_bsd_flag1(c_lflag,T,OSTOP); - svr4_to_bsd_flag1(c_lflag,E,CHOCTL); - svr4_to_bsd_flag1(c_lflag,E,CHOPRT); - svr4_to_bsd_flag1(c_lflag,E,CHOKE); - undefined_flag1(c_lflag,D,EFECHO); - svr4_to_bsd_flag1(c_lflag,F,LUSHO); - svr4_to_bsd_flag1(c_lflag,P,ENDIN); - svr4_to_bsd_flag1(c_lflag,I,EXTEN); -} - - -static void -bsd_to_svr4_termios(bt, st) - const struct termios *bt; - struct svr4_termios *st; -{ - /* control characters */ - /* - * We process VMIN and VTIME first, - * because they are shared with VEOF and VEOL - */ - bsd_to_svr4_char(V,MIN); - bsd_to_svr4_char(V,TIME); - bsd_to_svr4_char(V,INTR); - bsd_to_svr4_char(V,QUIT); - bsd_to_svr4_char(V,ERASE); - bsd_to_svr4_char(V,KILL); - bsd_to_svr4_char(V,EOF); - bsd_to_svr4_char(V,EOL); - bsd_to_svr4_char(V,EOL2); - undefined_char(V,SWTCH); - bsd_to_svr4_char(V,START); - bsd_to_svr4_char(V,STOP); - bsd_to_svr4_char(V,SUSP); - bsd_to_svr4_char(V,DSUSP); - bsd_to_svr4_char(V,REPRINT); - bsd_to_svr4_char(V,DISCARD); - bsd_to_svr4_char(V,WERASE); - bsd_to_svr4_char(V,LNEXT); - - /* Input modes */ - bsd_to_svr4_flag1(c_iflag,I,GNBRK); - bsd_to_svr4_flag1(c_iflag,B,RKINT); - bsd_to_svr4_flag1(c_iflag,I,GNPAR); - bsd_to_svr4_flag1(c_iflag,P,ARMRK); - bsd_to_svr4_flag1(c_iflag,I,NPCK); - bsd_to_svr4_flag1(c_iflag,I,STRIP); - bsd_to_svr4_flag1(c_iflag,I,NLCR); - bsd_to_svr4_flag1(c_iflag,I,GNCR); - bsd_to_svr4_flag1(c_iflag,I,CRNL); - undefined_flag1(c_iflag,I,UCLC); - bsd_to_svr4_flag1(c_iflag,I,XON); - bsd_to_svr4_flag1(c_iflag,I,XANY); - bsd_to_svr4_flag1(c_iflag,I,XOFF); - bsd_to_svr4_flag1(c_iflag,I,MAXBEL); - undefined_flag1(c_iflag,D,OSMODE); - - /* Output modes */ - bsd_to_svr4_flag1(c_oflag,O,POST); - undefined_flag1(c_oflag,O,LCUC); - bsd_to_svr4_flag1(c_oflag,O,NLCR); - undefined_flag1(c_oflag,O,CRNL); - undefined_flag1(c_oflag,O,NOCR); - undefined_flag1(c_oflag,O,NLRET); - undefined_flag1(c_oflag,O,FILL); - undefined_flag1(c_oflag,O,FDEL); - undefined_flag2(c_oflag,N,LDLY,N,L0,N,L1); - undefined_flag4(c_oflag,C,RDLY,C,R0,C,R1,C,R2,C,R3); - undefined_flag4(c_oflag,T,ABDLY,T,AB0,T,AB1,T,AB2,T,AB3); - undefined_flag2(c_oflag,B,SDLY,B,S0,B,S1); - undefined_flag2(c_oflag,V,TDLY,V,T0,V,T1); - undefined_flag2(c_oflag,F,FDLY,F,F0,F,F1); - undefined_flag1(c_oflag,P,AGEOUT); - undefined_flag1(c_oflag,W,RAP); - - /* Control modes */ - st->c_cflag &= ~SVR4_CBAUD; - st->c_cflag |= bsd_to_svr4_speed(bt->c_ospeed, SVR4_CBAUD); - bsd_to_svr4_flag4(c_cflag,C,SIZE,C,S5,C,S6,C,S7,C,S8) - bsd_to_svr4_flag1(c_cflag,C,STOPB); - bsd_to_svr4_flag1(c_cflag,C,READ); - bsd_to_svr4_flag1(c_cflag,P,ARENB); - bsd_to_svr4_flag1(c_cflag,P,ARODD); - bsd_to_svr4_flag1(c_cflag,H,UPCL); - bsd_to_svr4_flag1(c_cflag,C,LOCAL); - undefined_flag1(c_cflag,R,CV1EN); - undefined_flag1(c_cflag,X,MT1EN); - undefined_flag1(c_cflag,L,OBLK); - undefined_flag1(c_cflag,X,CLUDE); - st->c_cflag &= ~SVR4_CIBAUD; - st->c_cflag |= bsd_to_svr4_speed(bt->c_ispeed, SVR4_CIBAUD); - - undefined_flag1(c_oflag,P,AREXT); - - /* line discipline modes */ - bsd_to_svr4_flag1(c_lflag,I,SIG); - bsd_to_svr4_flag1(c_lflag,I,CANON); - undefined_flag1(c_lflag,X,CASE); - bsd_to_svr4_flag1(c_lflag,E,CHO); - bsd_to_svr4_flag1(c_lflag,E,CHOE); - bsd_to_svr4_flag1(c_lflag,E,CHOK); - bsd_to_svr4_flag1(c_lflag,E,CHONL); - bsd_to_svr4_flag1(c_lflag,N,OFLSH); - bsd_to_svr4_flag1(c_lflag,T,OSTOP); - bsd_to_svr4_flag1(c_lflag,E,CHOCTL); - bsd_to_svr4_flag1(c_lflag,E,CHOPRT); - bsd_to_svr4_flag1(c_lflag,E,CHOKE); - undefined_flag1(c_lflag,D,EFECHO); - bsd_to_svr4_flag1(c_lflag,F,LUSHO); - bsd_to_svr4_flag1(c_lflag,P,ENDIN); - bsd_to_svr4_flag1(c_lflag,I,EXTEN); -} - - -static void -svr4_termio_to_termios(t, ts) - const struct svr4_termio *t; - struct svr4_termios *ts; -{ - int i; - - ts->c_iflag = (svr4_tcflag_t) t->c_iflag; - ts->c_oflag = (svr4_tcflag_t) t->c_oflag; - ts->c_cflag = (svr4_tcflag_t) t->c_cflag; - ts->c_lflag = (svr4_tcflag_t) t->c_lflag; - - for (i = 0; i < SVR4_NCC; i++) - ts->c_cc[i] = (svr4_cc_t) t->c_cc[i]; -} - - -static void -svr4_termios_to_termio(ts, t) - const struct svr4_termios *ts; - struct svr4_termio *t; -{ - int i; - - t->c_iflag = (u_short) ts->c_iflag; - t->c_oflag = (u_short) ts->c_oflag; - t->c_cflag = (u_short) ts->c_cflag; - t->c_lflag = (u_short) ts->c_lflag; - t->c_line = 0; /* XXX */ - - for (i = 0; i < SVR4_NCC; i++) - t->c_cc[i] = (u_char) ts->c_cc[i]; -} - -int -svr4_term_ioctl(fp, td, retval, fd, cmd, data) - struct file *fp; - struct thread *td; - register_t *retval; - int fd; - u_long cmd; - caddr_t data; -{ - struct termios bt; - struct svr4_termios st; - struct svr4_termio t; - int error, new; - - *retval = 0; - - DPRINTF(("TERM ioctl %lx\n", cmd)); - - switch (cmd) { - case SVR4_TCGETA: - case SVR4_TCGETS: - DPRINTF(("ioctl(TCGET%c);\n", cmd == SVR4_TCGETA ? 'A' : 'S')); - if ((error = fo_ioctl(fp, TIOCGETA, (caddr_t) &bt, - td->td_ucred, td)) != 0) - return error; - - memset(&st, 0, sizeof(st)); - bsd_to_svr4_termios(&bt, &st); - -#ifdef DEBUG_SVR4 - print_bsd_termios(&bt); - print_svr4_termios(&st); -#endif /* DEBUG_SVR4 */ - - if (cmd == SVR4_TCGETA) { - svr4_termios_to_termio(&st, &t); - return copyout(&t, data, sizeof(t)); - } - else { - return copyout(&st, data, sizeof(st)); - } - - case SVR4_TCSETA: - case SVR4_TCSETS: - case SVR4_TCSETAW: - case SVR4_TCSETSW: - case SVR4_TCSETAF: - case SVR4_TCSETSF: - DPRINTF(("TCSET{A,S,AW,SW,AF,SF}\n")); - /* get full BSD termios so we don't lose information */ - if ((error = fo_ioctl(fp, TIOCGETA, (caddr_t) &bt, - td->td_ucred, td)) != 0) - return error; - - switch (cmd) { - case SVR4_TCSETS: - case SVR4_TCSETSW: - case SVR4_TCSETSF: - if ((error = copyin(data, &st, sizeof(st))) != 0) - return error; - new = 1; - break; - - case SVR4_TCSETA: - case SVR4_TCSETAW: - case SVR4_TCSETAF: - if ((error = copyin(data, &t, sizeof(t))) != 0) - return error; - - svr4_termio_to_termios(&t, &st); - new = 0; - break; - - default: - return EINVAL; - } - - svr4_to_bsd_termios(&st, &bt, new); - - switch (cmd) { - case SVR4_TCSETA: - case SVR4_TCSETS: - DPRINTF(("ioctl(TCSET[A|S]);\n")); - cmd = TIOCSETA; - break; - case SVR4_TCSETAW: - case SVR4_TCSETSW: - DPRINTF(("ioctl(TCSET[A|S]W);\n")); - cmd = TIOCSETAW; - break; - case SVR4_TCSETAF: - case SVR4_TCSETSF: - DPRINTF(("ioctl(TCSET[A|S]F);\n")); - cmd = TIOCSETAF; - break; - } - -#ifdef DEBUG_SVR4 - print_bsd_termios(&bt); - print_svr4_termios(&st); -#endif /* DEBUG_SVR4 */ - - return fo_ioctl(fp, cmd, (caddr_t) &bt, td->td_ucred, td); - - case SVR4_TIOCGWINSZ: - DPRINTF(("TIOCGWINSZ\n")); - { - struct svr4_winsize ws; - - error = fo_ioctl(fp, TIOCGWINSZ, (caddr_t) &ws, - td->td_ucred, td); - if (error) - return error; - return copyout(&ws, data, sizeof(ws)); - } - - case SVR4_TIOCSWINSZ: - DPRINTF(("TIOCSWINSZ\n")); - { - struct svr4_winsize ws; - - if ((error = copyin(data, &ws, sizeof(ws))) != 0) - return error; - return fo_ioctl(fp, TIOCSWINSZ, (caddr_t) &ws, - td->td_ucred, td); - } - - default: - DPRINTF(("teleport to STREAMS ioctls...\n")); - return svr4_stream_ti_ioctl(fp, td, retval, fd, cmd, data); - } -} diff --git a/sys/compat/svr4/svr4_termios.h b/sys/compat/svr4/svr4_termios.h deleted file mode 100644 index 06caa915054..00000000000 --- a/sys/compat/svr4/svr4_termios.h +++ /dev/null @@ -1,224 +0,0 @@ -/*- - * Copyright (c) 1998 Mark Newton - * Copyright (c) 1994 Christos Zoulas - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * $FreeBSD: stable/11/sys/compat/svr4/svr4_termios.h 139743 2005-01-05 22:34:37Z imp $ - */ - -#ifndef _SVR4_TERMIOS_H_ -#define _SVR4_TERMIOS_H_ - -#define SVR4_POSIX_VDISABLE 0 -#define SVR4_NCC 8 -#define SVR4_NCCS 19 - -typedef u_long svr4_tcflag_t; -typedef u_char svr4_cc_t; -typedef u_long svr4_speed_t; - -struct svr4_termios { - svr4_tcflag_t c_iflag; - svr4_tcflag_t c_oflag; - svr4_tcflag_t c_cflag; - svr4_tcflag_t c_lflag; - svr4_cc_t c_cc[SVR4_NCCS]; -}; - -struct svr4_termio { - u_short c_iflag; - u_short c_oflag; - u_short c_cflag; - u_short c_lflag; - char c_line; - u_char c_cc[SVR4_NCC]; -}; - -/* control characters */ -#define SVR4_VINTR 0 -#define SVR4_VQUIT 1 -#define SVR4_VERASE 2 -#define SVR4_VKILL 3 -#define SVR4_VEOF 4 -#define SVR4_VEOL 5 -#define SVR4_VEOL2 6 -#define SVR4_VMIN 4 -#define SVR4_VTIME 5 -#define SVR4_VSWTCH 7 -#define SVR4_VSTART 8 -#define SVR4_VSTOP 9 -#define SVR4_VSUSP 10 -#define SVR4_VDSUSP 11 -#define SVR4_VREPRINT 12 -#define SVR4_VDISCARD 13 -#define SVR4_VWERASE 14 -#define SVR4_VLNEXT 15 - -/* Input modes */ -#define SVR4_IGNBRK 00000001 -#define SVR4_BRKINT 00000002 -#define SVR4_IGNPAR 00000004 -#define SVR4_PARMRK 00000010 -#define SVR4_INPCK 00000020 -#define SVR4_ISTRIP 00000040 -#define SVR4_INLCR 00000100 -#define SVR4_IGNCR 00000200 -#define SVR4_ICRNL 00000400 -#define SVR4_IUCLC 00001000 -#define SVR4_IXON 00002000 -#define SVR4_IXANY 00004000 -#define SVR4_IXOFF 00010000 -#define SVR4_IMAXBEL 00020000 -#define SVR4_DOSMODE 00100000 - -/* Output modes */ -#define SVR4_OPOST 00000001 -#define SVR4_OLCUC 00000002 -#define SVR4_ONLCR 00000004 -#define SVR4_OCRNL 00000010 -#define SVR4_ONOCR 00000020 -#define SVR4_ONLRET 00000040 -#define SVR4_OFILL 00000100 -#define SVR4_OFDEL 00000200 -#define SVR4_NLDLY 00000400 -#define SVR4_NL0 00000000 -#define SVR4_NL1 00000400 -#define SVR4_CRDLY 00003000 -#define SVR4_CR0 00000000 -#define SVR4_CR1 00001000 -#define SVR4_CR2 00002000 -#define SVR4_CR3 00003000 -#define SVR4_TABDLY 00014000 -#define SVR4_TAB0 00000000 -#define SVR4_TAB1 00004000 -#define SVR4_TAB2 00010000 -#define SVR4_TAB3 00014000 -#define SVR4_XTABS 00014000 -#define SVR4_BSDLY 00020000 -#define SVR4_BS0 00000000 -#define SVR4_BS1 00020000 -#define SVR4_VTDLY 00040000 -#define SVR4_VT0 00000000 -#define SVR4_VT1 00040000 -#define SVR4_FFDLY 00100000 -#define SVR4_FF0 00000000 -#define SVR4_FF1 00100000 -#define SVR4_PAGEOUT 00200000 -#define SVR4_WRAP 00400000 - -/* Control modes */ -#define SVR4_CBAUD 00000017 -#define SVR4_CSIZE 00000060 -#define SVR4_CS5 00000000 -#define SVR4_CS6 00000200 -#define SVR4_CS7 00000040 -#define SVR4_CS8 00000006 -#define SVR4_CSTOPB 00000100 -#define SVR4_CREAD 00000200 -#define SVR4_PARENB 00000400 -#define SVR4_PARODD 00001000 -#define SVR4_HUPCL 00002000 -#define SVR4_CLOCAL 00004000 -#define SVR4_RCV1EN 00010000 -#define SVR4_XMT1EN 00020000 -#define SVR4_LOBLK 00040000 -#define SVR4_XCLUDE 00100000 -#define SVR4_CIBAUD 03600000 -#define SVR4_PAREXT 04000000 - -/* line discipline modes */ -#define SVR4_ISIG 00000001 -#define SVR4_ICANON 00000002 -#define SVR4_XCASE 00000004 -#define SVR4_ECHO 00000010 -#define SVR4_ECHOE 00000020 -#define SVR4_ECHOK 00000040 -#define SVR4_ECHONL 00000100 -#define SVR4_NOFLSH 00000200 -#define SVR4_TOSTOP 00000400 -#define SVR4_ECHOCTL 00001000 -#define SVR4_ECHOPRT 00002000 -#define SVR4_ECHOKE 00004000 -#define SVR4_DEFECHO 00010000 -#define SVR4_FLUSHO 00020000 -#define SVR4_PENDIN 00040000 -#define SVR4_IEXTEN 00100000 - -#define SVR4_TIOC ('T' << 8) - -#define SVR4_TCGETA (SVR4_TIOC| 1) -#define SVR4_TCSETA (SVR4_TIOC| 2) -#define SVR4_TCSETAW (SVR4_TIOC| 3) -#define SVR4_TCSETAF (SVR4_TIOC| 4) -#define SVR4_TCSBRK (SVR4_TIOC| 5) -#define SVR4_TCXONC (SVR4_TIOC| 6) -#define SVR4_TCFLSH (SVR4_TIOC| 7) -#define SVR4_TIOCKBON (SVR4_TIOC| 8) -#define SVR4_TIOCKBOF (SVR4_TIOC| 9) -#define SVR4_KBENABLED (SVR4_TIOC|10) -#define SVR4_TCGETS (SVR4_TIOC|13) -#define SVR4_TCSETS (SVR4_TIOC|14) -#define SVR4_TCSETSW (SVR4_TIOC|15) -#define SVR4_TCSETSF (SVR4_TIOC|16) -#define SVR4_TCDSET (SVR4_TIOC|32) -#define SVR4_RTS_TOG (SVR4_TIOC|33) -#define SVR4_TCGETSC (SVR4_TIOC|34) -#define SVR4_TCSETSC (SVR4_TIOC|35) -#define SVR4_TCMOUSE (SVR4_TIOC|36) -#define SVR4_TIOCGWINSZ (SVR4_TIOC|104) -#define SVR4_TIOCSWINSZ (SVR4_TIOC|103) - -struct svr4_winsize { - u_short ws_row; - u_short ws_col; - u_short ws_xpixel; - u_short ws_ypixel; -}; - -#define SVR4_B0 0 -#define SVR4_B50 1 -#define SVR4_B75 2 -#define SVR4_B110 3 -#define SVR4_B134 4 -#define SVR4_B150 5 -#define SVR4_B200 6 -#define SVR4_B300 7 -#define SVR4_B600 8 -#define SVR4_B1200 9 -#define SVR4_B1800 10 -#define SVR4_B2400 11 -#define SVR4_B4800 12 -#define SVR4_B9600 13 -#define SVR4_B19200 14 -#define SVR4_B38400 15 -#define SVR4_B57600 16 -#define SVR4_B76800 17 -#define SVR4_B115200 18 -#define SVR4_B153600 19 -#define SVR4_B230400 20 -#define SVR4_B307200 21 -#define SVR4_B460800 22 - -#endif /* !_SVR4_TERMIOS_H_ */ diff --git a/sys/compat/svr4/svr4_time.h b/sys/compat/svr4/svr4_time.h deleted file mode 100644 index 2b02be63012..00000000000 --- a/sys/compat/svr4/svr4_time.h +++ /dev/null @@ -1,41 +0,0 @@ -/*- - * Copyright (c) 1998 Mark Newton - * Copyright (c) 1994 Christos Zoulas - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * $FreeBSD: stable/11/sys/compat/svr4/svr4_time.h 139743 2005-01-05 22:34:37Z imp $ - */ - -#ifndef _SVR4_TIME_H_ -#define _SVR4_TIME_H_ - -#include - -struct svr4_utimbuf { - time_t actime; - time_t modtime; -}; - -#endif /* !_SVR4_TIME_H_ */ diff --git a/sys/compat/svr4/svr4_timod.h b/sys/compat/svr4/svr4_timod.h deleted file mode 100644 index f51ca7bd7ef..00000000000 --- a/sys/compat/svr4/svr4_timod.h +++ /dev/null @@ -1,87 +0,0 @@ -/*- - * Copyright (c) 1998 Mark Newton - * Copyright (c) 1994 Christos Zoulas - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * $FreeBSD: stable/11/sys/compat/svr4/svr4_timod.h 139743 2005-01-05 22:34:37Z imp $ - */ - -#ifndef _SVR4_TIMOD_H_ -#define _SVR4_TIMOD_H_ - -#define SVR4_TIMOD ('T' << 8) -#define SVR4_TI_GETINFO (SVR4_TIMOD|140) -#define SVR4_TI_OPTMGMT (SVR4_TIMOD|141) -#define SVR4_TI_BIND (SVR4_TIMOD|142) -#define SVR4_TI_UNBIND (SVR4_TIMOD|143) -#define SVR4_TI_GETMYNAME (SVR4_TIMOD|144) -#define SVR4_TI_GETPEERNAME (SVR4_TIMOD|145) -#define SVR4_TI_SETMYNAME (SVR4_TIMOD|146) -#define SVR4_TI_SETPEERNAME (SVR4_TIMOD|147) -#define SVR4_TI_SYNC (SVR4_TIMOD|148) -#define SVR4_TI_GETADDRS (SVR4_TIMOD|149) - -#define SVR4_TI_CONNECT_REQUEST 0x00 -#define SVR4_TI_CONNECT_RESPONSE 0x01 -#define SVR4_TI_DISCONNECT_REQUEST 0x02 -#define SVR4_TI_DATA_REQUEST 0x03 -#define SVR4_TI_EXPDATA_REQUEST 0x04 -#define SVR4_TI_INFO_REQUEST 0x05 -#define SVR4_TI_OLD_BIND_REQUEST 0x06 -#define SVR4_TI_UNBIND_REQUEST 0x07 -#define SVR4_TI_SENDTO_REQUEST 0x08 -#define SVR4_TI_OLD_OPTMGMT_REQUEST 0x09 -#define SVR4_TI_ORDREL_REQUEST 0x0a - -#define SVR4_TI_ACCEPT_REPLY 0x0b -#define SVR4_TI_CONNECT_REPLY 0x0c -#define SVR4_TI_DISCONNECT_IND 0x0d -#define SVR4_TI_DATA_IND 0x0e -#define SVR4_TI_EXPDATA_IND 0x0f -#define SVR4_TI_INFO_REPLY 0x10 -#define SVR4_TI_BIND_REPLY 0x11 -#define SVR4_TI_ERROR_REPLY 0x12 -#define SVR4_TI_OK_REPLY 0x13 -#define SVR4_TI_RECVFROM_IND 0x14 -#define SVR4_TI_RECVFROM_ERROR_IND 0x15 -#define SVR4_TI_OPTMGMT_REPLY 0x16 -#define SVR4_TI_ORDREL_IND 0x17 - -#define SVR4_TI_ADDRESS_REQUEST 0x18 -#define SVR4_TI_ADDRESS_REPLY 0x19 - -#define SVR4_TI_BIND_REQUEST 0x20 -#define SVR4_TI_OPTMGMT_REQUEST 0x21 - -#define SVR4_TI__ACCEPT_WAIT 0x10000001 -#define SVR4_TI__ACCEPT_OK 0x10000002 - -struct svr4_netbuf { - u_int maxlen; - u_int len; - char *buf; -}; - -#endif /* !_SVR4_TIMOD_H_ */ diff --git a/sys/compat/svr4/svr4_types.h b/sys/compat/svr4/svr4_types.h deleted file mode 100644 index 3b93326a47e..00000000000 --- a/sys/compat/svr4/svr4_types.h +++ /dev/null @@ -1,81 +0,0 @@ -/*- - * Copyright (c) 1998 Mark Newton - * Copyright (c) 1994 Christos Zoulas - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * $FreeBSD: stable/11/sys/compat/svr4/svr4_types.h 187830 2009-01-28 17:57:16Z ed $ - */ - -#ifndef _SVR4_TYPES_H_ -#define _SVR4_TYPES_H_ - -typedef u_quad_t svr4_ino64_t; -typedef quad_t svr4_off64_t; -typedef quad_t svr4_blkcnt64_t; -typedef u_quad_t svr4_fsblkcnt64_t; - -typedef long svr4_off_t; -typedef u_long svr4_dev_t; -typedef u_long svr4_ino_t; -typedef u_long svr4_mode_t; -typedef u_long svr4_nlink_t; -typedef long svr4_uid_t; -typedef long svr4_gid_t; -typedef long svr4_daddr_t; -typedef long svr4_pid_t; -typedef long svr4_time_t; -typedef long svr4_blkcnt_t; -typedef u_long svr4_fsblkcnt_t; -typedef char *svr4_caddr_t; -typedef u_int svr4_size_t; - -typedef short svr4_o_dev_t; -typedef short svr4_o_pid_t; -typedef u_short svr4_o_ino_t; -typedef u_short svr4_o_mode_t; -typedef short svr4_o_nlink_t; -typedef u_short svr4_o_uid_t; -typedef u_short svr4_o_gid_t; -typedef long svr4_clock_t; -typedef int svr4_key_t; - -typedef struct timespec svr4_timestruc_t; - -#define svr4_omajor(x) ((int32_t)((((x) & 0x7f00) >> 8))) -#define svr4_ominor(x) ((int32_t)((((x) & 0x00ff) >> 0))) -#define svr4_omakedev(x,y) ((svr4_o_dev_t)((((x) << 8) & 0x7f00) | \ - (((y) << 0) & 0x00ff))) - -#define svr4_to_bsd_odev_t(d) makedev(svr4_omajor(d), svr4_ominor(d)) -#define bsd_to_svr4_odev_t(d) svr4_omakedev(major(d), minor(d)) - -#define svr4_major(x) ((int32_t)((((x) & 0xfffc0000) >> 18))) -#define svr4_minor(x) ((int32_t)((((x) & 0x0003ffff) >> 0))) -#define svr4_makedev(x,y) ((svr4_dev_t)((((x) << 18) & 0xfffc0000) | \ - (((y) << 0) & 0x0003ffff))) -#define svr4_to_bsd_dev_t(d) makedev(svr4_major(d), svr4_minor(d)) -#define bsd_to_svr4_dev_t(d) svr4_makedev(major(d), minor(d)) - -#endif /* !_SVR4_TYPES_H_ */ diff --git a/sys/compat/svr4/svr4_ucontext.h b/sys/compat/svr4/svr4_ucontext.h deleted file mode 100644 index 39a338bef85..00000000000 --- a/sys/compat/svr4/svr4_ucontext.h +++ /dev/null @@ -1,74 +0,0 @@ -/*- - * Copyright (c) 1998 Mark Newton - * Copyright (c) 1994 Christos Zoulas - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * $FreeBSD: stable/11/sys/compat/svr4/svr4_ucontext.h 139743 2005-01-05 22:34:37Z imp $ - */ - -#ifndef _SVR4_UCONTEXT_H_ -#define _SVR4_UCONTEXT_H_ - -/* - * Machine context - */ - -#define SVR4_UC_SIGMASK 0x01 -#define SVR4_UC_STACK 0x02 - -#define SVR4_UC_CPU 0x04 -#define SVR4_UC_FPU 0x08 -#define SVR4_UC_WEITEK 0x10 - -#define SVR4_UC_MCONTEXT (SVR4_UC_CPU|SVR4_UC_FPU|SVR4_UC_WEITEK) - -#define SVR4_UC_ALL (SVR4_UC_SIGMASK|SVR4_UC_STACK|SVR4_UC_MCONTEXT) - -typedef struct svr4_ucontext { - u_long uc_flags; - /* struct svr4_ucontext *uc_link;*/ - void *uc_link; - svr4_sigset_t uc_sigmask; - struct svr4_sigaltstack uc_stack; - svr4_mcontext_t uc_mcontext; - long uc_pad[5]; -} svr4_ucontext_t; - -#define SVR4_UC_GETREGSET 0 -#define SVR4_UC_SETREGSET 1 - -/* - * Signal frame - */ -struct svr4_sigframe { - int sf_signum; - union svr4_siginfo *sf_sip; - struct svr4_ucontext *sf_ucp; - sig_t sf_handler; - struct svr4_ucontext sf_uc; - union svr4_siginfo sf_si; -}; - -#endif /* !_SVR4_UCONTEXT_H_ */ diff --git a/sys/compat/svr4/svr4_ulimit.h b/sys/compat/svr4/svr4_ulimit.h deleted file mode 100644 index d28e0e650cb..00000000000 --- a/sys/compat/svr4/svr4_ulimit.h +++ /dev/null @@ -1,41 +0,0 @@ -/*- - * Copyright (c) 1998 Mark Newton - * Copyright (c) 1994 Christos Zoulas - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * $FreeBSD: stable/11/sys/compat/svr4/svr4_ulimit.h 139743 2005-01-05 22:34:37Z imp $ - */ - -#ifndef _SVR4_ULIMIT_H_ -#define _SVR4_ULIMIT_H_ - -#define SVR4_GFILLIM 1 -#define SVR4_SFILLIM 2 -#define SVR4_GMEMLIM 3 -#define SVR4_GDESLIM 4 -#define SVR4_GTXTOFF 64 - - -#endif /* !_SVR4_ULIMIT_H_ */ diff --git a/sys/compat/svr4/svr4_ustat.h b/sys/compat/svr4/svr4_ustat.h deleted file mode 100644 index ac61a0bb00d..00000000000 --- a/sys/compat/svr4/svr4_ustat.h +++ /dev/null @@ -1,43 +0,0 @@ -/*- - * Copyright (c) 1998 Mark Newton - * Copyright (c) 1994 Christos Zoulas - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * $FreeBSD: stable/11/sys/compat/svr4/svr4_ustat.h 139743 2005-01-05 22:34:37Z imp $ - */ - -#ifndef _SVR4_USTAT_H_ -#define _SVR4_USTAT_H_ - -#include - -struct svr4_ustat { - svr4_daddr_t f_tfree; - svr4_ino_t f_tinode; - char f_fname[6]; - char f_fpack[6]; -}; - -#endif /* !_SVR4_USTAT_H_ */ diff --git a/sys/compat/svr4/svr4_util.h b/sys/compat/svr4/svr4_util.h deleted file mode 100644 index bc7f7b38637..00000000000 --- a/sys/compat/svr4/svr4_util.h +++ /dev/null @@ -1,63 +0,0 @@ -/*- - * Copyright (c) 1998 Mark Newton - * Copyright (c) 1994 Christos Zoulas - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * $FreeBSD: stable/11/sys/compat/svr4/svr4_util.h 295882 2016-02-22 09:08:04Z skra $ - */ - -#ifndef _SVR4_UTIL_H_ -#define _SVR4_UTIL_H_ - -/*#include */ -#include -#include -#include -#include -#include -#include -#include - -#ifdef DEBUG_SVR4 -#define DPRINTF(a) uprintf a; -#else -#define DPRINTF(a) -#endif - -int svr4_emul_find(struct thread *, char *, enum uio_seg, char **, int); - -#define CHECKALT(td, upath, pathp, i) \ - do { \ - int _error; \ - \ - _error = svr4_emul_find(td, upath, UIO_USERSPACE, pathp, i); \ - if (*(pathp) == NULL) \ - return (_error); \ - } while (0) - -#define CHECKALTEXIST(td, upath, pathp) CHECKALT(td, upath, pathp, 0) -#define CHECKALTCREAT(td, upath, pathp) CHECKALT(td, upath, pathp, 1) - -#endif /* !_SVR4_UTIL_H_ */ diff --git a/sys/compat/svr4/svr4_utsname.h b/sys/compat/svr4/svr4_utsname.h deleted file mode 100644 index 699b0b95592..00000000000 --- a/sys/compat/svr4/svr4_utsname.h +++ /dev/null @@ -1,44 +0,0 @@ -/*- - * Copyright (c) 1998 Mark Newton - * Copyright (c) 1994 Christos Zoulas - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * $FreeBSD: stable/11/sys/compat/svr4/svr4_utsname.h 139743 2005-01-05 22:34:37Z imp $ - */ - -#ifndef _SVR4_UTSNAME_H_ -#define _SVR4_UTSNAME_H_ - -#include - -struct svr4_utsname { - char sysname[257]; - char nodename[257]; - char release[257]; - char version[257]; - char machine[257]; -}; - -#endif /* !_SVR4_UTSNAME_H_ */ diff --git a/sys/compat/svr4/svr4_wait.h b/sys/compat/svr4/svr4_wait.h deleted file mode 100644 index 8833735f90a..00000000000 --- a/sys/compat/svr4/svr4_wait.h +++ /dev/null @@ -1,56 +0,0 @@ -/*- - * Copyright (c) 1998 Mark Newton - * Copyright (c) 1994 Christos Zoulas - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * $FreeBSD: stable/11/sys/compat/svr4/svr4_wait.h 139743 2005-01-05 22:34:37Z imp $ - */ - -#ifndef _SVR4_WAIT_H_ -#define _SVR4_WAIT_H_ - - -#define SVR4_P_PID 0 -#define SVR4_P_PPID 1 -#define SVR4_P_PGID 2 -#define SVR4_P_SID 3 -#define SVR4_P_CID 4 -#define SVR4_P_UID 5 -#define SVR4_P_GID 6 -#define SVR4_P_ALL 7 - -#define SVR4_WEXITED 0x01 -#define SVR4_WTRAPPED 0x02 -#define SVR4_WSTOPPED 0x04 -#define SVR4_WCONTINUED 0x08 -#define SVR4_WUNDEF1 0x10 -#define SVR4_WUNDEF2 0x20 -#define SVR4_WNOHANG 0x40 -#define SVR4_WNOWAIT 0x80 - -#define SVR4_WOPTMASK (SVR4_WEXITED|SVR4_WTRAPPED|SVR4_WSTOPPED|\ - SVR4_WCONTINUED|SVR4_WNOHANG|SVR4_WNOWAIT) - -#endif /* !_SVR4_WAIT_H_ */ diff --git a/sys/compat/svr4/syscalls.conf b/sys/compat/svr4/syscalls.conf deleted file mode 100644 index f3459cbc637..00000000000 --- a/sys/compat/svr4/syscalls.conf +++ /dev/null @@ -1,11 +0,0 @@ -# $FreeBSD: stable/11/sys/compat/svr4/syscalls.conf 161328 2006-08-15 17:25:55Z jhb $ -sysnames="svr4_syscallnames.c" -sysproto="svr4_proto.h" -sysproto_h=_SVR4_SYSPROTO_H_ -syshdr="svr4_syscall.h" -syssw="svr4_sysent.c" -sysmk="/dev/null" -syscallprefix="SVR4_SYS_" -switchname="svr4_sysent" -namesname="svr4_syscallnames" -systrace="/dev/null" diff --git a/sys/compat/svr4/syscalls.master b/sys/compat/svr4/syscalls.master deleted file mode 100644 index e15c2878518..00000000000 --- a/sys/compat/svr4/syscalls.master +++ /dev/null @@ -1,396 +0,0 @@ - $FreeBSD: stable/11/sys/compat/svr4/syscalls.master 302096 2016-06-23 00:29:03Z brooks $ -; from: @(#)syscalls.master 8.1 (Berkeley) 7/19/93 -; -; System call name/number master file (or rather, slave, from SVR4). -; Processed to create svr4_sysent.c, svr4_syscalls.c and svr4_syscall.h. - -; Columns: number type nargs name alt{name,tag,rtyp}/comments -; number system call number, must be in order -; audit the audit event associated with the system call -; A value of AUE_NULL means no auditing, but it also means that -; there is no audit event for the call at this time. For the -; case where the event exists, but we don't want auditing, the -; event should be #defined to AUE_NULL in audit_kevents.h. -; type one of STD, OBSOL, UNIMPL, COMPAT -; name psuedo-prototype of syscall routine -; If one of the following alts is different, then all appear: -; altname name of system call if different -; alttag name of args struct tag if different from [o]`name'"_args" -; altrtyp return type if not int (bogus - syscalls always return int) -; for UNIMPL/OBSOL, name continues with comments - -; types: -; STD always included -; COMPAT included on COMPAT #ifdef -; OBSOL obsolete, not included in system, only specifies name -; UNIMPL not implemented, placeholder only - -; #ifdef's, etc. may be included, and are copied to the output files. - -#include -#include -#include -#include - -#include -#include -#include -#include - -0 AUE_NULL UNIMPL unused -1 AUE_NULL NOPROTO { void sys_exit(int rval); } exit \ - sys_exit_args void -2 AUE_NULL NOPROTO { int fork(void); } -3 AUE_NULL NOPROTO { int read(int fd, char *buf, u_int nbyte); } -4 AUE_NULL NOPROTO { int write(int fd, char *buf, u_int nbyte); } -5 AUE_NULL STD { int svr4_sys_open(char *path, int flags, \ - int mode); } -6 AUE_NULL NOPROTO { int close(int fd); } -7 AUE_NULL STD { int svr4_sys_wait(int *status); } -8 AUE_NULL STD { int svr4_sys_creat(char *path, int mode); } -9 AUE_NULL NOPROTO { int link(char *path, char *link); } -10 AUE_NULL NOPROTO { int unlink(char *path); } -11 AUE_NULL STD { int svr4_sys_execv(char *path, char **argp); } -12 AUE_NULL NOPROTO { int chdir(char *path); } -13 AUE_NULL STD { int svr4_sys_time(time_t *t); } -14 AUE_NULL STD { int svr4_sys_mknod(char* path, int mode, int dev); } -15 AUE_NULL NOPROTO { int chmod(char *path, int mode); } -16 AUE_NULL NOPROTO { int chown(char *path, uid_t uid, gid_t gid); } -17 AUE_NULL STD { int svr4_sys_break(caddr_t nsize); } -18 AUE_NULL STD { int svr4_sys_stat(char* path, \ - struct svr4_stat* ub); } -19 AUE_NULL NOPROTO { int lseek(int filedes, off_t *offset, \ - int whence); } -20 AUE_NULL NOPROTO { pid_t getpid(void); } -21 AUE_NULL UNIMPL old_mount -22 AUE_NULL UNIMPL sysv_umount -23 AUE_NULL NOPROTO { int setuid(uid_t uid); } -24 AUE_NULL NOPROTO { uid_t getuid(void); } -25 AUE_NULL UNIMPL stime -26 AUE_NULL UNIMPL ptrace -27 AUE_NULL STD { int svr4_sys_alarm(unsigned sec); } -28 AUE_NULL STD { int svr4_sys_fstat(int fd, \ - struct svr4_stat *sb); } -29 AUE_NULL STD { int svr4_sys_pause(void); } -30 AUE_NULL STD { int svr4_sys_utime(char *path, \ - struct svr4_utimbuf *ubuf); } -31 AUE_NULL UNIMPL stty -32 AUE_NULL UNIMPL gtty -33 AUE_NULL STD { int svr4_sys_access(char *path, \ - int amode); } -34 AUE_NULL STD { int svr4_sys_nice(int prio); } -35 AUE_NULL UNIMPL statfs -36 AUE_NULL NOPROTO { int sync(void); } -37 AUE_NULL STD { int svr4_sys_kill(int pid, int signum); } -38 AUE_NULL UNIMPL fstatfs -39 AUE_NULL STD { int svr4_sys_pgrpsys(int cmd, int pid, \ - int pgid); } -40 AUE_NULL UNIMPL xenix -41 AUE_NULL NOPROTO { int dup(u_int fd); } -42 AUE_NULL STD { int svr4_pipe(void); } -43 AUE_NULL STD { int svr4_sys_times(struct tms *tp); } -44 AUE_NULL UNIMPL profil -45 AUE_NULL UNIMPL plock -46 AUE_NULL NOPROTO { int setgid(gid_t gid); } -47 AUE_NULL NOPROTO { gid_t getgid(void); } -48 AUE_NULL STD { int svr4_sys_signal(int signum, \ - svr4_sig_t handler); } -49 AUE_NULL STD { int svr4_sys_msgsys(int what, int a2, \ - int a3, int a4, int a5); } -50 AUE_NULL STD { int svr4_sys_sysarch(int op, void *a1); } -51 AUE_NULL UNIMPL acct -52 AUE_NULL STD { int svr4_sys_shmsys(int what, int a2, \ - int a3, int a4, int a5); } -53 AUE_NULL STD { int svr4_sys_semsys(int what, int a2, \ - int a3, int a4, int a5); } -54 AUE_NULL STD { int svr4_sys_ioctl(int fd, u_long com, \ - caddr_t data); } -55 AUE_NULL UNIMPL uadmin -56 AUE_NULL UNIMPL exch -57 AUE_NULL STD { int svr4_sys_utssys(void *a1, void *a2, \ - int sel, void *a3); } -58 AUE_NULL NOPROTO { int fsync(int fd); } -59 AUE_NULL STD { int svr4_sys_execve(char *path, \ - char **argp, char **envp); } -60 AUE_NULL NOPROTO { int umask(int newmask); } -61 AUE_NULL NOPROTO { int chroot(char *path); } -62 AUE_NULL STD { int svr4_sys_fcntl(int fd, int cmd, \ - char *arg); } -63 AUE_NULL STD { int svr4_sys_ulimit(int cmd, \ - long newlimit); } -64 AUE_NULL UNIMPL reserved -65 AUE_NULL UNIMPL reserved -66 AUE_NULL UNIMPL reserved -67 AUE_NULL UNIMPL reserved -68 AUE_NULL UNIMPL reserved -69 AUE_NULL UNIMPL reserved -70 AUE_NULL UNIMPL advfs -71 AUE_NULL UNIMPL unadvfs -72 AUE_NULL UNIMPL rmount -73 AUE_NULL UNIMPL rumount -74 AUE_NULL UNIMPL rfstart -75 AUE_NULL UNIMPL sigret -76 AUE_NULL UNIMPL rdebug -77 AUE_NULL UNIMPL rfstop -78 AUE_NULL UNIMPL rfsys -79 AUE_NULL NOPROTO { int rmdir(char *path); } -80 AUE_NULL NOPROTO { int mkdir(char *path, int mode); } -81 AUE_NULL STD { int svr4_sys_getdents(int fd, char *buf, \ - int nbytes); } -82 AUE_NULL UNIMPL libattach -83 AUE_NULL UNIMPL libdetach -84 AUE_NULL UNIMPL sysfs -85 AUE_NULL STD { int svr4_sys_getmsg(int fd, \ - struct svr4_strbuf *ctl, \ - struct svr4_strbuf *dat, int *flags); } -86 AUE_NULL STD { int svr4_sys_putmsg(int fd, \ - struct svr4_strbuf *ctl, \ - struct svr4_strbuf *dat, int flags); } -87 AUE_NULL STD { int svr4_sys_poll(struct pollfd *fds, \ - unsigned int nfds, int timeout); } -88 AUE_NULL STD { int svr4_sys_lstat(char *path, \ - struct svr4_stat *ub); } -89 AUE_NULL NOPROTO { int symlink(char *path, char *link); } -90 AUE_NULL NOPROTO { int readlink(char *path, char *buf, \ - int count); } -91 AUE_NULL NOPROTO { int getgroups(u_int gidsetsize, \ - gid_t *gidset); } -92 AUE_NULL NOPROTO { int setgroups(u_int gidsetsize, \ - gid_t *gidset); } -93 AUE_NULL NOPROTO { int fchmod(int fd, int mode); } -94 AUE_NULL NOPROTO { int fchown(int fd, int uid, int gid); } -95 AUE_NULL STD { int svr4_sys_sigprocmask(int how, \ - svr4_sigset_t *set, \ - svr4_sigset_t *oset); } -96 AUE_NULL STD { int svr4_sys_sigsuspend( \ - svr4_sigset_t *ss); } -97 AUE_NULL STD { int svr4_sys_sigaltstack( \ - struct svr4_sigaltstack *nss, \ - struct svr4_sigaltstack *oss); } -98 AUE_NULL STD { int svr4_sys_sigaction(int signum, \ - struct svr4_sigaction *nsa, \ - struct svr4_sigaction *osa); } -99 AUE_NULL STD { int svr4_sys_sigpending(int what, \ - svr4_sigset_t *mask); } -100 AUE_NULL STD { int svr4_sys_context(int func, \ - struct svr4_ucontext *uc); } -101 AUE_NULL UNIMPL evsys -102 AUE_NULL UNIMPL evtrapret -103 AUE_NULL STD { int svr4_sys_statvfs(char *path, \ - struct svr4_statvfs *fs); } -104 AUE_NULL STD { int svr4_sys_fstatvfs(int fd, \ - struct svr4_statvfs *fs); } -105 AUE_NULL UNIMPL whoknows -106 AUE_NULL UNIMPL nfssvc -107 AUE_NULL STD { int svr4_sys_waitsys(int grp, int id, \ - union svr4_siginfo *info, int options); } -108 AUE_NULL UNIMPL sigsendsys -109 AUE_NULL STD { int svr4_sys_hrtsys(int cmd, int fun, \ - int sub, void *rv1, void *rv2); } -110 AUE_NULL UNIMPL acancel -111 AUE_NULL UNIMPL async -112 AUE_NULL UNIMPL priocntlsys -113 AUE_NULL STD { int svr4_sys_pathconf(char *path, \ - int name); } -114 AUE_NULL UNIMPL mincore -115 AUE_NULL STD { caddr_t svr4_sys_mmap(caddr_t addr, \ - svr4_size_t len, int prot, int flags, \ - int fd, svr4_off_t pos); } -116 AUE_NULL NOPROTO { int mprotect(void *addr, int len, \ - int prot); } -117 AUE_NULL NOPROTO { int munmap(void *addr, int len); } -118 AUE_NULL STD { int svr4_sys_fpathconf(int fd, int name); } -119 AUE_NULL NOPROTO { int vfork(void); } -120 AUE_NULL NOPROTO { int fchdir(int fd); } -121 AUE_NULL NOPROTO { int readv(int fd, struct iovec *iovp, \ - u_int iovcnt); } -122 AUE_NULL NOPROTO { int writev(int fd, struct iovec *iovp, \ - u_int iovcnt); } -123 AUE_NULL STD { int svr4_sys_xstat(int two, char *path, \ - struct svr4_xstat *ub); } -124 AUE_NULL STD { int svr4_sys_lxstat(int two, char *path, \ - struct svr4_xstat *ub); } -125 AUE_NULL STD { int svr4_sys_fxstat(int two, int fd, \ - struct svr4_xstat *sb); } -126 AUE_NULL STD { int svr4_sys_xmknod(int two, char *path, \ - svr4_mode_t mode, svr4_dev_t dev); } -127 AUE_NULL UNIMPL clocal -128 AUE_NULL STD { int svr4_sys_setrlimit(int which, \ - const struct svr4_rlimit *rlp); } -129 AUE_NULL STD { int svr4_sys_getrlimit(int which, \ - struct svr4_rlimit *rlp); } -130 AUE_NULL NOPROTO { int lchown(char *path, uid_t uid, \ - gid_t gid); } -131 AUE_NULL STD { int svr4_sys_memcntl(void * addr, \ - svr4_size_t len, int cmd, void * arg, \ - int attr, int mask); } -132 AUE_NULL UNIMPL getpmsg -133 AUE_NULL UNIMPL putpmsg -134 AUE_NULL NOPROTO { int rename(char *from, char *to); } -135 AUE_NULL STD { int svr4_sys_uname( \ - struct svr4_utsname* name, int dummy); } -136 AUE_NULL NOPROTO { int setegid(gid_t egid); } -137 AUE_NULL STD { int svr4_sys_sysconfig(int name); } -138 AUE_NULL NOPROTO { int adjtime(struct timeval *delta, \ - struct timeval *olddelta); } -139 AUE_NULL STD { long svr4_sys_systeminfo(int what, \ - char *buf, long len); } -140 AUE_NULL UNIMPL notused -141 AUE_NULL NOPROTO { int seteuid(uid_t euid); } -142 AUE_NULL UNIMPL vtrace -; fork1 -143 AUE_NULL UNIMPL { int fork(void); } -144 AUE_NULL UNIMPL sigtimedwait -145 AUE_NULL UNIMPL lwp_info -146 AUE_NULL UNIMPL yield -147 AUE_NULL UNIMPL lwp_sema_wait -148 AUE_NULL UNIMPL lwp_sema_post -149 AUE_NULL UNIMPL lwp_sema_trywait -150 AUE_NULL UNIMPL notused -151 AUE_NULL UNIMPL notused -152 AUE_NULL UNIMPL modctl -153 AUE_NULL STD { int svr4_sys_fchroot(int fd); } -154 AUE_NULL STD { int svr4_sys_utimes(char *path, \ - struct timeval *tptr); } -155 AUE_NULL STD { int svr4_sys_vhangup(void); } -156 AUE_NULL STD { int svr4_sys_gettimeofday( \ - struct timeval *tp); } -157 AUE_NULL NOPROTO { int getitimer(u_int which, \ - struct itimerval *itv); } -158 AUE_NULL NOPROTO { int setitimer(u_int which, \ - struct itimerval *itv, \ - struct itimerval *oitv); } -159 AUE_NULL UNIMPL lwp_create -160 AUE_NULL UNIMPL lwp_exit -161 AUE_NULL UNIMPL lwp_suspend -162 AUE_NULL UNIMPL lwp_continue -163 AUE_NULL UNIMPL lwp_kill -164 AUE_NULL UNIMPL lwp_self -165 AUE_NULL UNIMPL lwp_getprivate -166 AUE_NULL UNIMPL lwp_setprivate -167 AUE_NULL UNIMPL lwp_wait -168 AUE_NULL UNIMPL lwp_mutex_unlock -169 AUE_NULL UNIMPL lwp_mutex_lock -170 AUE_NULL UNIMPL lwp_cond_wait -171 AUE_NULL UNIMPL lwp_cond_signal -172 AUE_NULL UNIMPL lwp_cond_broadcast -173 AUE_NULL UNIMPL { ssize_t svr4_sys_pread(int fd, void *buf, \ - size_t nbyte, svr4_off_t off); } -174 AUE_NULL UNIMPL { ssize_t svr4_sys_pwrite(int fd, \ - const void *buf, size_t nbyte, \ - svr4_off_t off); } -175 AUE_NULL STD { svr4_off64_t svr4_sys_llseek(int fd, \ - long offset1, long offset2, int whence); } -176 AUE_NULL UNIMPL inst_sync -177 AUE_NULL UNIMPL whoknows -178 AUE_NULL UNIMPL kaio -179 AUE_NULL UNIMPL whoknows -180 AUE_NULL UNIMPL whoknows -181 AUE_NULL UNIMPL whoknows -182 AUE_NULL UNIMPL whoknows -183 AUE_NULL UNIMPL whoknows -184 AUE_NULL UNIMPL tsolsys -185 AUE_NULL STD { int svr4_sys_acl(char *path, int cmd, \ - int num, struct svr4_aclent *buf); } -186 AUE_NULL STD { int svr4_sys_auditsys(int code, int a1, \ - int a2, int a3, int a4, int a5); } -187 AUE_NULL UNIMPL processor_bind -188 AUE_NULL UNIMPL processor_info -189 AUE_NULL UNIMPL p_online -190 AUE_NULL UNIMPL sigqueue -191 AUE_NULL UNIMPL clock_gettime -192 AUE_NULL UNIMPL clock_settime -193 AUE_NULL UNIMPL clock_getres -194 AUE_NULL UNIMPL timer_create -195 AUE_NULL UNIMPL timer_delete -196 AUE_NULL UNIMPL timer_settime -197 AUE_NULL UNIMPL timer_gettime -198 AUE_NULL UNIMPL timer_overrun -199 AUE_NULL NOPROTO { int nanosleep( \ - const struct timespec *rqtp, \ - struct timespec *rmtp); } -200 AUE_NULL STD { int svr4_sys_facl(int fd, int cmd, \ - int num, struct svr4_aclent *buf); } -201 AUE_NULL UNIMPL door -202 AUE_NULL NOPROTO { int setreuid(int ruid, int euid); } -203 AUE_NULL NOPROTO { int setregid(int rgid, int egid); } -204 AUE_NULL UNIMPL install_utrap -205 AUE_NULL UNIMPL signotify -206 AUE_NULL UNIMPL schedctl -207 AUE_NULL UNIMPL pset -208 AUE_NULL UNIMPL whoknows -209 AUE_NULL STD { int svr4_sys_resolvepath(const char *path, \ - char *buf, size_t bufsiz); } -210 AUE_NULL UNIMPL signotifywait -211 AUE_NULL UNIMPL lwp_sigredirect -212 AUE_NULL UNIMPL lwp_alarm -213 AUE_NULL STD { int svr4_sys_getdents64(int fd, \ - struct svr4_dirent64 *dp, int nbytes); } -;213 AUE_NULL UNIMPL getdents64 -214 AUE_NULL STD { caddr_t svr4_sys_mmap64(void *addr, \ - svr4_size_t len, int prot, int flags, \ - int fd, svr4_off64_t pos); } -215 AUE_NULL STD { int svr4_sys_stat64(char *path, \ - struct svr4_stat64 *sb); } -216 AUE_NULL STD { int svr4_sys_lstat64(char *path, \ - struct svr4_stat64 *sb); } -217 AUE_NULL STD { int svr4_sys_fstat64(int fd, \ - struct svr4_stat64 *sb); } -218 AUE_NULL STD { int svr4_sys_statvfs64(char *path, \ - struct svr4_statvfs64 *fs); } -219 AUE_NULL STD { int svr4_sys_fstatvfs64(int fd, \ - struct svr4_statvfs64 *fs); } -220 AUE_NULL STD { int svr4_sys_setrlimit64(int which, \ - const struct svr4_rlimit64 *rlp); } -221 AUE_NULL STD { int svr4_sys_getrlimit64(int which, \ - struct svr4_rlimit64 *rlp); } -222 AUE_NULL UNIMPL pread64 -223 AUE_NULL UNIMPL pwrite64 -224 AUE_NULL STD { int svr4_sys_creat64(char *path, \ - int mode); } -225 AUE_NULL STD { int svr4_sys_open64(char *path, int flags, \ - int mode); } -226 AUE_NULL UNIMPL rpcsys -227 AUE_NULL UNIMPL whoknows -228 AUE_NULL UNIMPL whoknows -229 AUE_NULL UNIMPL whoknows -230 AUE_NULL STD { int svr4_sys_socket(int domain, int type, \ - int protocol); } -231 AUE_NULL NOPROTO { int socketpair(int domain, int type, \ - int protocol, int *rsv); } -232 AUE_NULL NOPROTO { int bind(int s, \ - const struct sockaddr *name, \ - int namelen); } -233 AUE_NULL NOPROTO { int listen(int s, int backlog); } -234 AUE_NULL NOPROTO { int accept(int s, struct sockaddr *name, \ - int *anamelen); } -235 AUE_NULL NOPROTO { int connect(int s, \ - const struct sockaddr *name, \ - int namelen); } -236 AUE_NULL NOPROTO { int shutdown(int s, int how); } -237 AUE_NULL STD { int svr4_sys_recv(int s, caddr_t buf, \ - int len, int flags); } -238 AUE_NULL NOPROTO { ssize_t recvfrom(int s, void *buf, \ - size_t len, int flags, \ - struct sockaddr *from, \ - int *fromlenaddr); } -239 AUE_NULL NOPROTO { ssize_t recvmsg(int s, struct msghdr *msg, \ - int flags); } -240 AUE_NULL STD { int svr4_sys_send(int s, caddr_t buf, \ - int len, int flags); } -241 AUE_NULL NOPROTO { ssize_t sendmsg(int s, \ - const struct msghdr *msg, int flags); } -242 AUE_NULL STD { ssize_t svr4_sys_sendto(int s, void *buf, \ - size_t len, int flags, \ - struct sockaddr *to, int tolen); } -243 AUE_NULL NOPROTO { int getpeername(int fdes, \ - struct sockaddr *asa, int *alen); } -244 AUE_NULL NOPROTO { int getsockname(int fdes, \ - struct sockaddr *asa, int *alen); } -245 AUE_NULL NOPROTO { int getsockopt(int s, int level, int name, \ - void *val, int *avalsize); } -246 AUE_NULL NOPROTO { int setsockopt(int s, int level, int name, \ - const void *val, int valsize); } -247 AUE_NULL UNIMPL sockconfig -248 AUE_NULL UNIMPL { int ntp_gettime(struct ntptimeval *ntvp); } -249 AUE_NULL UNIMPL { int ntp_adjtime(struct timex *tp); } diff --git a/sys/contrib/ck/include/gcc/arm/ck_pr_armv4.h b/sys/contrib/ck/include/gcc/arm/ck_pr_armv4.h deleted file mode 100644 index 892fe2c83ae..00000000000 --- a/sys/contrib/ck/include/gcc/arm/ck_pr_armv4.h +++ /dev/null @@ -1,349 +0,0 @@ -/* - * Copyright 2009-2016 Samy Al Bahra. - * Copyright 2016 Olivier Houchard. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - */ - -#ifndef CK_PR_ARM_H -#define CK_PR_ARM_H - -#ifndef CK_PR_H -#error Do not include this file directly, use ck_pr.h -#endif - -#include -#include - -#include - -/* - * armv4/v5 CPUs lack any instruction that would let us implement an atomic CAS - * so we have to give atomicity by disabling interrupts. This only works in - * the kernel, obviously. - */ -#define __with_interrupts_disabled(expr) \ - do { \ - u_int cpsr_save, tmp; \ - \ - __asm __volatile( \ - "mrs %0, cpsr;" \ - "orr %1, %0, %2;" \ - "msr cpsr_fsxc, %1;" \ - : "=r" (cpsr_save), "=r" (tmp) \ - : "I" (PSR_I | PSR_F) \ - : "cc" ); \ - (expr); \ - __asm __volatile( \ - "msr cpsr_fsxc, %0" \ - : /* no output */ \ - : "r" (cpsr_save) \ - : "cc" ); \ - } while(0) -/* - * The following represent supported atomic operations. - * These operations may be emulated. - */ -#include "ck_f_pr.h" - -/* - * Minimum interface requirement met. - */ -#define CK_F_PR - -CK_CC_INLINE static void -ck_pr_stall(void) -{ - - __asm__ __volatile__("" ::: "memory"); - return; -} - -#define CK_PR_FENCE(T, I) \ - CK_CC_INLINE static void \ - ck_pr_fence_strict_##T(void) \ - { \ - I; \ - } - -/* - * ARM CPUs prior to armv6 didn't reorder instructions, and we don't - * support any SMP system, so a compiler barrier should be enough for fences - */ -CK_PR_FENCE(atomic, ck_pr_stall()) -CK_PR_FENCE(atomic_store, ck_pr_stall()) -CK_PR_FENCE(atomic_load, ck_pr_stall()) -CK_PR_FENCE(store_atomic, ck_pr_stall()) -CK_PR_FENCE(load_atomic, ck_pr_stall()) -CK_PR_FENCE(store, ck_pr_stall()) -CK_PR_FENCE(store_load, ck_pr_stall()) -CK_PR_FENCE(load, ck_pr_stall()) -CK_PR_FENCE(load_store, ck_pr_stall()) -CK_PR_FENCE(memory, ck_pr_stall()) -CK_PR_FENCE(acquire, ck_pr_stall()) -CK_PR_FENCE(release, ck_pr_stall()) -CK_PR_FENCE(acqrel, ck_pr_stall()) -CK_PR_FENCE(lock, ck_pr_stall()) -CK_PR_FENCE(unlock, ck_pr_stall()) - -#undef CK_PR_FENCE - -#define CK_PR_LOAD(S, M, T, C, I) \ - CK_CC_INLINE static T \ - ck_pr_md_load_##S(const M *target) \ - { \ - long r = 0; \ - __asm__ __volatile__(I " %0, [%1];" \ - : "=r" (r) \ - : "r" (target) \ - : "memory"); \ - return ((T)r); \ - } - -CK_PR_LOAD(ptr, void, void *, uint32_t, "ldr") - -#define CK_PR_LOAD_S(S, T, I) CK_PR_LOAD(S, T, T, T, I) - -CK_PR_LOAD_S(32, uint32_t, "ldr") -CK_PR_LOAD_S(16, uint16_t, "ldrh") -CK_PR_LOAD_S(8, uint8_t, "ldrb") -CK_PR_LOAD_S(uint, unsigned int, "ldr") -CK_PR_LOAD_S(int, int, "ldr") -CK_PR_LOAD_S(short, short, "ldrh") -CK_PR_LOAD_S(char, char, "ldrb") - -#undef CK_PR_LOAD_S -#undef CK_PR_LOAD - -#define CK_PR_STORE(S, M, T, C, I) \ - CK_CC_INLINE static void \ - ck_pr_md_store_##S(M *target, T v) \ - { \ - __asm__ __volatile__(I " %1, [%0]" \ - : \ - : "r" (target), \ - "r" (v) \ - : "memory"); \ - return; \ - } - -CK_PR_STORE(ptr, void, const void *, uint32_t, "str") - -#define CK_PR_STORE_S(S, T, I) CK_PR_STORE(S, T, T, T, I) - -CK_PR_STORE_S(32, uint32_t, "str") -CK_PR_STORE_S(16, uint16_t, "strh") -CK_PR_STORE_S(8, uint8_t, "strb") -CK_PR_STORE_S(uint, unsigned int, "str") -CK_PR_STORE_S(int, int, "str") -CK_PR_STORE_S(short, short, "strh") -CK_PR_STORE_S(char, char, "strb") - -#undef CK_PR_STORE_S -#undef CK_PR_STORE - -#define CK_PR_CAS(N, M, T) \ -CK_CC_INLINE static bool \ -ck_pr_cas_##N##_value(M *target, T compare, T set, M *value) \ -{ \ - bool ret; \ - __with_interrupts_disabled( \ - { \ - *(T *)value = *(T *)target; \ - if (*(T *)target == compare) { \ - *(T *)target = set; \ - ret = true; \ - } else \ - ret = false; \ - } \ - ); \ - return ret; \ -} \ -CK_CC_INLINE static bool \ -ck_pr_cas_##N(M *target, T compare, T set) \ -{ \ - bool ret; \ - __with_interrupts_disabled( \ - { \ - if (*(T *)target == compare) { \ - *(T *)target = set; \ - ret = true; \ - } else \ - ret = false; \ - } \ - ); \ - return ret; \ -} - -CK_PR_CAS(ptr, void, void *) - -#define CK_PR_CAS_S(N, T) CK_PR_CAS(N, T, T) -CK_PR_CAS_S(32, uint32_t) -CK_PR_CAS_S(uint, unsigned int) -CK_PR_CAS_S(int, int) -CK_PR_CAS_S(16, uint16_t) -CK_PR_CAS_S(8, uint8_t) -CK_PR_CAS_S(short, short) -CK_PR_CAS_S(char, char) - -#undef CK_PR_CAS_S -#undef CK_PR_CAS - -#define CK_PR_FAS(N, M, T, W) \ - CK_CC_INLINE static T \ - ck_pr_fas_##N(M *target, T v) \ - { \ - T previous = 0; \ - __with_interrupts_disabled( \ - { \ - previous = *(T *)target; \ - *(T *)target = v; \ - } \ - ); \ - return (previous); \ - } - -CK_PR_FAS(32, uint32_t, uint32_t, "") -CK_PR_FAS(ptr, void, void *, "") -CK_PR_FAS(int, int, int, "") -CK_PR_FAS(uint, unsigned int, unsigned int, "") -CK_PR_FAS(16, uint16_t, uint16_t, "h") -CK_PR_FAS(8, uint8_t, uint8_t, "b") -CK_PR_FAS(short, short, short, "h") -CK_PR_FAS(char, char, char, "b") - - -#undef CK_PR_FAS - -#define CK_PR_UNARY(O, N, M, T, I, W) \ - CK_CC_INLINE static void \ - ck_pr_##O##_##N(M *target) \ - { \ - __with_interrupts_disabled( \ - { \ - I; \ - } \ - ); \ - return; \ - } - -CK_PR_UNARY(inc, ptr, void, void *, (*(int *)target)++, "") -CK_PR_UNARY(dec, ptr, void, void *, (*(int *)target)--, "") -CK_PR_UNARY(not, ptr, void, void *, *(int *)target = !(*(int*)target), "") -CK_PR_UNARY(neg, ptr, void, void *, *(int *)target = -(*(int *)target), "") - -#define CK_PR_UNARY_S(S, T, W) \ - CK_PR_UNARY(inc, S, T, T, *target++, W) \ - CK_PR_UNARY(dec, S, T, T, *target--, W) \ - CK_PR_UNARY(not, S, T, T, *target = !*target, W) \ - CK_PR_UNARY(neg, S, T, T, *target = -*target, W) \ - -CK_PR_UNARY_S(32, uint32_t, "") -CK_PR_UNARY_S(uint, unsigned int, "") -CK_PR_UNARY_S(int, int, "") -CK_PR_UNARY_S(16, uint16_t, "h") -CK_PR_UNARY_S(8, uint8_t, "b") -CK_PR_UNARY_S(short, short, "h") -CK_PR_UNARY_S(char, char, "b") - -#undef CK_PR_UNARY_S -#undef CK_PR_UNARY - -#define CK_PR_BINARY(O, N, M, T, I, W) \ - CK_CC_INLINE static void \ - ck_pr_##O##_##N(M *target, T delta) \ - { \ - __with_interrupts_disabled( \ - { \ - I; \ - } \ - ); \ - return; \ - } - -CK_PR_BINARY(and, ptr, void, uintptr_t, *((uintptr_t *)target) &= delta, "") -CK_PR_BINARY(add, ptr, void, uintptr_t, *((uintptr_t *)target) += delta, "") -CK_PR_BINARY(or, ptr, void, uintptr_t, *((uintptr_t *)target) |= delta, "") -CK_PR_BINARY(sub, ptr, void, uintptr_t, *((uintptr_t *)target) -= delta, "") -CK_PR_BINARY(xor, ptr, void, uintptr_t, *((uintptr_t *)target) ^= delta, "") - -#define CK_PR_BINARY_S(S, T, W) \ - CK_PR_BINARY(and, S, T, T, *target &= delta, W) \ - CK_PR_BINARY(add, S, T, T, *target += delta, W) \ - CK_PR_BINARY(or, S, T, T, *target |= delta, W) \ - CK_PR_BINARY(sub, S, T, T, *target -= delta, W) \ - CK_PR_BINARY(xor, S, T, T, *target ^= delta, W) - -CK_PR_BINARY_S(32, uint32_t, "") -CK_PR_BINARY_S(uint, unsigned int, "") -CK_PR_BINARY_S(int, int, "") -CK_PR_BINARY_S(16, uint16_t, "h") -CK_PR_BINARY_S(8, uint8_t, "b") -CK_PR_BINARY_S(short, short, "h") -CK_PR_BINARY_S(char, char, "b") - -#undef CK_PR_BINARY_S -#undef CK_PR_BINARY - -CK_CC_INLINE static void * -ck_pr_faa_ptr(void *target, uintptr_t delta) -{ - uintptr_t previous; - __with_interrupts_disabled( - { - previous = *(uintptr_t *)target; - *(uintptr_t *)target += delta; - } - ); - return (void *)(previous); -} - -#define CK_PR_FAA(S, T, W) \ - CK_CC_INLINE static T \ - ck_pr_faa_##S(T *target, T delta) \ - { \ - T previous = 0; \ - __with_interrupts_disabled( \ - { \ - previous = *target; \ - *target += delta; \ - } \ - ); \ - return (previous); \ - } - -CK_PR_FAA(32, uint32_t, "") -CK_PR_FAA(uint, unsigned int, "") -CK_PR_FAA(int, int, "") -CK_PR_FAA(16, uint16_t, "h") -CK_PR_FAA(8, uint8_t, "b") -CK_PR_FAA(short, short, "h") -CK_PR_FAA(char, char, "b") - -#undef CK_PR_FAA - -#undef __with_interrupts_disabled - -#endif /* CK_PR_ARM_H */ - diff --git a/sys/dev/fb/boot_font.c b/sys/dev/fb/boot_font.c deleted file mode 100644 index afe62c481a3..00000000000 --- a/sys/dev/fb/boot_font.c +++ /dev/null @@ -1,4636 +0,0 @@ -/*- - * Copyright (c) 1999 The NetBSD Foundation, Inc. - * All rights reserved. - * - * This code is derived from software contributed to The NetBSD Foundation - * by Andrew Doran. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS - * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ -/*- - * This font lives in the public domain. It is a PC font, IBM encoding - * (CP437), which was designed for use with syscons. - * - * Copyright (c) 2000 Andrew Miklic - */ - -#include - -#include - -#include - -const struct gfb_font bold8x16 = { - 8, - 16, - { - /* \00 */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - - /* \01 */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x3c, /* ..****.. */ - 0x42, /* .*....*. */ - 0x81, /* *......* */ - 0xe7, /* ***..*** */ - 0xa5, /* *.*..*.* */ - 0x99, /* *..**..* */ - 0x81, /* *......* */ - 0x99, /* *..**..* */ - 0x42, /* .*....*. */ - 0x3c, /* ..****.. */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - - /* \02 */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x3c, /* ..****.. */ - 0x7e, /* .******. */ - 0xff, /* ******** */ - 0x99, /* *..**..* */ - 0xdb, /* **.**.** */ - 0xe7, /* ***..*** */ - 0xff, /* ******** */ - 0xe7, /* ***..*** */ - 0x7e, /* .******. */ - 0x3c, /* ..****.. */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - - /* \03 */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x6c, /* .**.**.. */ - 0xfe, /* *******. */ - 0xfe, /* *******. */ - 0xfe, /* *******. */ - 0xfe, /* *******. */ - 0xfe, /* *******. */ - 0x7c, /* .*****.. */ - 0x38, /* ..***... */ - 0x10, /* ...*.... */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - - /* \04 */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x10, /* ...*.... */ - 0x38, /* ..***... */ - 0x7c, /* .*****.. */ - 0xfe, /* *******. */ - 0x7c, /* .*****.. */ - 0x38, /* ..***... */ - 0x10, /* ...*.... */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - - /* \05 */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x38, /* ..***... */ - 0x38, /* ..***... */ - 0x10, /* ...*.... */ - 0xd6, /* **.*.**. */ - 0xfe, /* *******. */ - 0xd6, /* **.*.**. */ - 0x10, /* ...*.... */ - 0x38, /* ..***... */ - 0x7c, /* .*****.. */ - 0x7c, /* .*****.. */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - - /* \06 */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x10, /* ...*.... */ - 0x38, /* ..***... */ - 0x7c, /* .*****.. */ - 0xfe, /* *******. */ - 0xfe, /* *******. */ - 0x54, /* .*.*.*.. */ - 0x10, /* ...*.... */ - 0x38, /* ..***... */ - 0x7c, /* .*****.. */ - 0x7c, /* .*****.. */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - - /* \07 */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x18, /* ...**... */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x18, /* ...**... */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - - /* \010 */ - 0xff, /* ******** */ - 0xff, /* ******** */ - 0xff, /* ******** */ - 0xff, /* ******** */ - 0xff, /* ******** */ - 0xff, /* ******** */ - 0xe7, /* ***..*** */ - 0xc3, /* **....** */ - 0xc3, /* **....** */ - 0xe7, /* ***..*** */ - 0xff, /* ******** */ - 0xff, /* ******** */ - 0xff, /* ******** */ - 0xff, /* ******** */ - 0xff, /* ******** */ - 0xff, /* ******** */ - - /* \011 */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x3c, /* ..****.. */ - 0x66, /* .**..**. */ - 0x42, /* .*....*. */ - 0x42, /* .*....*. */ - 0x66, /* .**..**. */ - 0x3c, /* ..****.. */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - - /* \012 */ - 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0xfc, /* ******.. */ - 0xfc, /* ******.. */ - 0xfc, /* ******.. */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - - /* ╝ */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0xfc, /* ******.. */ - 0xfc, /* ******.. */ - 0xfc, /* ******.. */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - - /* ╜ */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0xfc, /* ******.. */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - - /* ╛ */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0xf8, /* *****... */ - 0xf8, /* *****... */ - 0xf8, /* *****... */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - - /* ┐ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0xf8, /* *****... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - - /* └ */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x1f, /* ...***** */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - - /* ┴ */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0xff, /* ******** */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - - /* ┬ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0xff, /* ******** */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - - /* ├ */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x1f, /* ...***** */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - - /* ─ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0xff, /* ******** */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - - /* ┼ */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0xff, /* ******** */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - - /* ╞ */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x1f, /* ...***** */ - 0x1f, /* ...***** */ - 0x1f, /* ...***** */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - - /* ╟ */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3f, /* ..****** */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - - /* ╚ */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3f, /* ..****** */ - 0x3f, /* ..****** */ - 0x3f, /* ..****** */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - - /* ╔ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x3f, /* ..****** */ - 0x3f, /* ..****** */ - 0x3f, /* ..****** */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - - /* ╩ */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0xff, /* ******** */ - 0xff, /* ******** */ - 0xff, /* ******** */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - - /* ╦ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0xff, /* ******** */ - 0xff, /* ******** */ - 0xff, /* ******** */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - - /* ╠ */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3f, /* ..****** */ - 0x3f, /* ..****** */ - 0x3f, /* ..****** */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - - /* ═ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0xff, /* ******** */ - 0xff, /* ******** */ - 0xff, /* ******** */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - - /* ╬ */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0xff, /* ******** */ - 0xff, /* ******** */ - 0xff, /* ******** */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - - /* ╧ */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0xff, /* ******** */ - 0xff, /* ******** */ - 0xff, /* ******** */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - - /* ╨ */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0xff, /* ******** */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - - /* ╤ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0xff, /* ******** */ - 0xff, /* ******** */ - 0xff, /* ******** */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - - /* ╥ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0xff, /* ******** */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - - /* ╙ */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3f, /* ..****** */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - - /* ╘ */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x1f, /* ...***** */ - 0x1f, /* ...***** */ - 0x1f, /* ...***** */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - - /* ╒ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x1f, /* ...***** */ - 0x1f, /* ...***** */ - 0x1f, /* ...***** */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - - /* ╓ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x3f, /* ..****** */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - - /* ╫ */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0xff, /* ******** */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - 0x3c, /* ..****.. */ - - /* ╪ */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0xff, /* ******** */ - 0xff, /* ******** */ - 0xff, /* ******** */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - - /* ┘ */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0xf8, /* *****... */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - - /* ┌ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x1f, /* ...***** */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - - /* █ */ - 0xff, /* ******** */ - 0xff, /* ******** */ - 0xff, /* ******** */ - 0xff, /* ******** */ - 0xff, /* ******** */ - 0xff, /* ******** */ - 0xff, /* ******** */ - 0xff, /* ******** */ - 0xff, /* ******** */ - 0xff, /* ******** */ - 0xff, /* ******** */ - 0xff, /* ******** */ - 0xff, /* ******** */ - 0xff, /* ******** */ - 0xff, /* ******** */ - 0xff, /* ******** */ - - /* ▄ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0xff, /* ******** */ - 0xff, /* ******** */ - 0xff, /* ******** */ - 0xff, /* ******** */ - 0xff, /* ******** */ - 0xff, /* ******** */ - 0xff, /* ******** */ - 0xff, /* ******** */ - - /* ▌ */ - 0xf0, /* ****.... */ - 0xf0, /* ****.... */ - 0xf0, /* ****.... */ - 0xf0, /* ****.... */ - 0xf0, /* ****.... */ - 0xf0, /* ****.... */ - 0xf0, /* ****.... */ - 0xf0, /* ****.... */ - 0xf0, /* ****.... */ - 0xf0, /* ****.... */ - 0xf0, /* ****.... */ - 0xf0, /* ****.... */ - 0xf0, /* ****.... */ - 0xf0, /* ****.... */ - 0xf0, /* ****.... */ - 0xf0, /* ****.... */ - - /* ▐ */ - 0x0f, /* ....**** */ - 0x0f, /* ....**** */ - 0x0f, /* ....**** */ - 0x0f, /* ....**** */ - 0x0f, /* ....**** */ - 0x0f, /* ....**** */ - 0x0f, /* ....**** */ - 0x0f, /* ....**** */ - 0x0f, /* ....**** */ - 0x0f, /* ....**** */ - 0x0f, /* ....**** */ - 0x0f, /* ....**** */ - 0x0f, /* ....**** */ - 0x0f, /* ....**** */ - 0x0f, /* ....**** */ - 0x0f, /* ....**** */ - - /* ▀ */ - 0xff, /* ******** */ - 0xff, /* ******** */ - 0xff, /* ******** */ - 0xff, /* ******** */ - 0xff, /* ******** */ - 0xff, /* ******** */ - 0xff, /* ******** */ - 0xff, /* ******** */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - - /* α */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x77, /* .***.*** */ - 0xcc, /* **..**.. */ - 0xcc, /* **..**.. */ - 0xcc, /* **..**.. */ - 0xde, /* **.****. */ - 0x73, /* .***..** */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - - /* ß */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x7c, /* .*****.. */ - 0xc6, /* **...**. */ - 0xc6, /* **...**. */ - 0xc4, /* **...*.. */ - 0xc8, /* **..*... */ - 0xc4, /* **...*.. */ - 0xc6, /* **...**. */ - 0xc6, /* **...**. */ - 0xc6, /* **...**. */ - 0xdc, /* **.***.. */ - 0xc0, /* **...... */ - 0xc0, /* **...... */ - 0x00, /* ........ */ - 0x00, /* ........ */ - - /* Γ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0xfe, /* *******. */ - 0xc6, /* **...**. */ - 0xc6, /* **...**. */ - 0xc0, /* **...... */ - 0xc0, /* **...... */ - 0xc0, /* **...... */ - 0xc0, /* **...... */ - 0xc0, /* **...... */ - 0xc0, /* **...... */ - 0xc0, /* **...... */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - - /* π */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x03, /* ......** */ - 0x7e, /* .******. */ - 0xec, /* ***.**.. */ - 0x6c, /* .**.**.. */ - 0x6c, /* .**.**.. */ - 0x6c, /* .**.**.. */ - 0x6c, /* .**.**.. */ - 0x68, /* .**.*... */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - - /* Σ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0xfe, /* *******. */ - 0xc6, /* **...**. */ - 0x60, /* .**..... */ - 0x30, /* ..**.... */ - 0x18, /* ...**... */ - 0x30, /* ..**.... */ - 0x60, /* .**..... */ - 0xc0, /* **...... */ - 0xc6, /* **...**. */ - 0xfe, /* *******. */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - - /* σ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x7f, /* .******* */ - 0xf0, /* ****.... */ - 0xd8, /* **.**... */ - 0xd8, /* **.**... */ - 0xd8, /* **.**... */ - 0xd8, /* **.**... */ - 0x70, /* .***.... */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - - /* µ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x66, /* .**..**. */ - 0x66, /* .**..**. */ - 0x66, /* .**..**. */ - 0x66, /* .**..**. */ - 0x66, /* .**..**. */ - 0x66, /* .**..**. */ - 0x7c, /* .*****.. */ - 0x60, /* .**..... */ - 0x60, /* .**..... */ - 0xc0, /* **...... */ - 0x00, /* ........ */ - - /* τ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x76, /* .***.**. */ - 0xdc, /* **.***.. */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - - /* Φ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x7e, /* .******. */ - 0xdb, /* **.**.** */ - 0xdb, /* **.**.** */ - 0xdb, /* **.**.** */ - 0xdb, /* **.**.** */ - 0x7e, /* .******. */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - - /* Θ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x38, /* ..***... */ - 0x6c, /* .**.**.. */ - 0xc6, /* **...**. */ - 0xc6, /* **...**. */ - 0xfe, /* *******. */ - 0xc6, /* **...**. */ - 0xc6, /* **...**. */ - 0xc6, /* **...**. */ - 0x6c, /* .**.**.. */ - 0x38, /* ..***... */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - - /* Ω */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x3c, /* ..****.. */ - 0x66, /* .**..**. */ - 0xc3, /* **....** */ - 0xc3, /* **....** */ - 0xc3, /* **....** */ - 0xc3, /* **....** */ - 0x66, /* .**..**. */ - 0x24, /* ..*..*.. */ - 0xa5, /* *.*..*.* */ - 0xe7, /* ***..*** */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - - /* δ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x1e, /* ...****. */ - 0x30, /* ..**.... */ - 0x18, /* ...**... */ - 0x0c, /* ....**.. */ - 0x3e, /* ..*****. */ - 0x66, /* .**..**. */ - 0x66, /* .**..**. */ - 0x66, /* .**..**. */ - 0x66, /* .**..**. */ - 0x3c, /* ..****.. */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - - /* ∞ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x7e, /* .******. */ - 0xdb, /* **.**.** */ - 0xdb, /* **.**.** */ - 0xdb, /* **.**.** */ - 0x7e, /* .******. */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - - /* φ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x03, /* ......** */ - 0x06, /* .....**. */ - 0x7e, /* .******. */ - 0xcf, /* **..**** */ - 0xdb, /* **.**.** */ - 0xf3, /* ****..** */ - 0x7e, /* .******. */ - 0x60, /* .**..... */ - 0xc0, /* **...... */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - - /* ε */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x1c, /* ...***.. */ - 0x30, /* ..**.... */ - 0x60, /* .**..... */ - 0x60, /* .**..... */ - 0x7c, /* .*****.. */ - 0x60, /* .**..... */ - 0x60, /* .**..... */ - 0x60, /* .**..... */ - 0x30, /* ..**.... */ - 0x1c, /* ...***.. */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - - /* ∩ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x7c, /* .*****.. */ - 0xc6, /* **...**. */ - 0xc6, /* **...**. */ - 0xc6, /* **...**. */ - 0xc6, /* **...**. */ - 0xc6, /* **...**. */ - 0xc6, /* **...**. */ - 0xc6, /* **...**. */ - 0xc6, /* **...**. */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - - /* ≡ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0xfe, /* *******. */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x7c, /* .*****.. */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0xfe, /* *******. */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - - /* ± */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x7e, /* .******. */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x7e, /* .******. */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - - /* ≥ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x30, /* ..**.... */ - 0x18, /* ...**... */ - 0x0c, /* ....**.. */ - 0x06, /* .....**. */ - 0x0c, /* ....**.. */ - 0x18, /* ...**... */ - 0x30, /* ..**.... */ - 0x00, /* ........ */ - 0x7e, /* .******. */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - - /* ≤ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x0c, /* ....**.. */ - 0x18, /* ...**... */ - 0x30, /* ..**.... */ - 0x60, /* .**..... */ - 0x30, /* ..**.... */ - 0x18, /* ...**... */ - 0x0c, /* ....**.. */ - 0x00, /* ........ */ - 0x7e, /* .******. */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - - /* ⌠ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x0e, /* ....***. */ - 0x1b, /* ...**.** */ - 0x1b, /* ...**.** */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - - /* ⌡ */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0xd8, /* **.**... */ - 0xd8, /* **.**... */ - 0x70, /* .***.... */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - - /* ÷ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x00, /* ........ */ - 0x7e, /* .******. */ - 0x00, /* ........ */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - - /* ≈ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x76, /* .***.**. */ - 0xdc, /* **.***.. */ - 0x00, /* ........ */ - 0x76, /* .***.**. */ - 0xdc, /* **.***.. */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - - /* ° */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x38, /* ..***... */ - 0x6c, /* .**.**.. */ - 0x6c, /* .**.**.. */ - 0x38, /* ..***... */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - - /* ∙ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x18, /* ...**... */ - 0x18, /* ...**... */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - - /* · */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x18, /* ...**... */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - - /* √ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x03, /* ......** */ - 0x02, /* ......*. */ - 0x06, /* .....**. */ - 0x04, /* .....*.. */ - 0x0c, /* ....**.. */ - 0x08, /* ....*... */ - 0xd8, /* **.**... */ - 0x50, /* .*.*.... */ - 0x70, /* .***.... */ - 0x20, /* ..*..... */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - - /* ⁿ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0xd8, /* **.**... */ - 0x6c, /* .**.**.. */ - 0x6c, /* .**.**.. */ - 0x6c, /* .**.**.. */ - 0x6c, /* .**.**.. */ - 0x6c, /* .**.**.. */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - - /* ² */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x78, /* .****... */ - 0xcc, /* **..**.. */ - 0x18, /* ...**... */ - 0x30, /* ..**.... */ - 0x60, /* .**..... */ - 0xfc, /* ******.. */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - - /* ■ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x7c, /* .*****.. */ - 0x7c, /* .*****.. */ - 0x7c, /* .*****.. */ - 0x7c, /* .*****.. */ - 0x7c, /* .*****.. */ - 0x7c, /* .*****.. */ - 0x7c, /* .*****.. */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - 0x00, /* ........ */ - } -}; diff --git a/sys/dev/fb/creator.c b/sys/dev/fb/creator.c deleted file mode 100644 index fcedaa0a858..00000000000 --- a/sys/dev/fb/creator.c +++ /dev/null @@ -1,1128 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2003 Jake Burkholder. - * Copyright (c) 2005 - 2006 Marius Strobl - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include -#include -#include -#include -#include - -#include - -#include -#include -#include -#include - -#define CREATOR_DRIVER_NAME "creator" - -struct creator_softc { - video_adapter_t sc_va; /* XXX must be first */ - - phandle_t sc_node; - - struct cdev *sc_si; - - struct resource *sc_reg[FFB_NREG]; - bus_space_tag_t sc_bt[FFB_NREG]; - bus_space_handle_t sc_bh[FFB_NREG]; - u_long sc_reg_size; - - u_int sc_height; - u_int sc_width; - - u_int sc_xmargin; - u_int sc_ymargin; - - const u_char *sc_font; - - int sc_bg_cache; - int sc_fg_cache; - int sc_fifo_cache; - int sc_fontinc_cache; - int sc_fontw_cache; - int sc_pmask_cache; - - u_int sc_flags; -#define CREATOR_AFB (1 << 0) -#define CREATOR_CONSOLE (1 << 1) -#define CREATOR_CUREN (1 << 2) -#define CREATOR_CURINV (1 << 3) -#define CREATOR_PAC1 (1 << 4) -}; - -#define FFB_READ(sc, reg, off) \ - bus_space_read_4((sc)->sc_bt[(reg)], (sc)->sc_bh[(reg)], (off)) -#define FFB_WRITE(sc, reg, off, val) \ - bus_space_write_4((sc)->sc_bt[(reg)], (sc)->sc_bh[(reg)], (off), (val)) - -#define C(r, g, b) ((b << 16) | (g << 8) | (r)) -static const uint32_t creator_cmap[] = { - C(0x00, 0x00, 0x00), /* black */ - C(0x00, 0x00, 0xff), /* blue */ - C(0x00, 0xff, 0x00), /* green */ - C(0x00, 0xc0, 0xc0), /* cyan */ - C(0xff, 0x00, 0x00), /* red */ - C(0xc0, 0x00, 0xc0), /* magenta */ - C(0xc0, 0xc0, 0x00), /* brown */ - C(0xc0, 0xc0, 0xc0), /* light grey */ - C(0x80, 0x80, 0x80), /* dark grey */ - C(0x80, 0x80, 0xff), /* light blue */ - C(0x80, 0xff, 0x80), /* light green */ - C(0x80, 0xff, 0xff), /* light cyan */ - C(0xff, 0x80, 0x80), /* light red */ - C(0xff, 0x80, 0xff), /* light magenta */ - C(0xff, 0xff, 0x80), /* yellow */ - C(0xff, 0xff, 0xff), /* white */ -}; -#undef C - -static const struct { - vm_offset_t virt; - vm_paddr_t phys; - vm_size_t size; -} creator_fb_map[] = { - { FFB_VIRT_SFB8R, FFB_PHYS_SFB8R, FFB_SIZE_SFB8R }, - { FFB_VIRT_SFB8G, FFB_PHYS_SFB8G, FFB_SIZE_SFB8G }, - { FFB_VIRT_SFB8B, FFB_PHYS_SFB8B, FFB_SIZE_SFB8B }, - { FFB_VIRT_SFB8X, FFB_PHYS_SFB8X, FFB_SIZE_SFB8X }, - { FFB_VIRT_SFB32, FFB_PHYS_SFB32, FFB_SIZE_SFB32 }, - { FFB_VIRT_SFB64, FFB_PHYS_SFB64, FFB_SIZE_SFB64 }, - { FFB_VIRT_FBC, FFB_PHYS_FBC, FFB_SIZE_FBC }, - { FFB_VIRT_FBC_BM, FFB_PHYS_FBC_BM, FFB_SIZE_FBC_BM }, - { FFB_VIRT_DFB8R, FFB_PHYS_DFB8R, FFB_SIZE_DFB8R }, - { FFB_VIRT_DFB8G, FFB_PHYS_DFB8G, FFB_SIZE_DFB8G }, - { FFB_VIRT_DFB8B, FFB_PHYS_DFB8B, FFB_SIZE_DFB8B }, - { FFB_VIRT_DFB8X, FFB_PHYS_DFB8X, FFB_SIZE_DFB8X }, - { FFB_VIRT_DFB24, FFB_PHYS_DFB24, FFB_SIZE_DFB24 }, - { FFB_VIRT_DFB32, FFB_PHYS_DFB32, FFB_SIZE_DFB32 }, - { FFB_VIRT_DFB422A, FFB_PHYS_DFB422A, FFB_SIZE_DFB422A }, - { FFB_VIRT_DFB422AD, FFB_PHYS_DFB422AD, FFB_SIZE_DFB422AD }, - { FFB_VIRT_DFB24B, FFB_PHYS_DFB24B, FFB_SIZE_DFB24B }, - { FFB_VIRT_DFB422B, FFB_PHYS_DFB422B, FFB_SIZE_DFB422B }, - { FFB_VIRT_DFB422BD, FFB_PHYS_DFB422BD, FFB_SIZE_DFB422BD }, - { FFB_VIRT_SFB16Z, FFB_PHYS_SFB16Z, FFB_SIZE_SFB16Z }, - { FFB_VIRT_SFB8Z, FFB_PHYS_SFB8Z, FFB_SIZE_SFB8Z }, - { FFB_VIRT_SFB422, FFB_PHYS_SFB422, FFB_SIZE_SFB422 }, - { FFB_VIRT_SFB422D, FFB_PHYS_SFB422D, FFB_SIZE_SFB422D }, - { FFB_VIRT_FBC_KREG, FFB_PHYS_FBC_KREG, FFB_SIZE_FBC_KREG }, - { FFB_VIRT_DAC, FFB_PHYS_DAC, FFB_SIZE_DAC }, - { FFB_VIRT_PROM, FFB_PHYS_PROM, FFB_SIZE_PROM }, - { FFB_VIRT_EXP, FFB_PHYS_EXP, FFB_SIZE_EXP }, -}; - -#define CREATOR_FB_MAP_SIZE nitems(creator_fb_map) - -extern const struct gfb_font gallant12x22; - -static struct creator_softc creator_softc; -static struct bus_space_tag creator_bst_store[FFB_FBC]; - -static device_probe_t creator_bus_probe; -static device_attach_t creator_bus_attach; - -static device_method_t creator_bus_methods[] = { - DEVMETHOD(device_probe, creator_bus_probe), - DEVMETHOD(device_attach, creator_bus_attach), - - { 0, 0 } -}; - -static devclass_t creator_devclass; - -DEFINE_CLASS_0(creator, creator_bus_driver, creator_bus_methods, - sizeof(struct creator_softc)); -DRIVER_MODULE(creator, nexus, creator_bus_driver, creator_devclass, 0, 0); -DRIVER_MODULE(creator, upa, creator_bus_driver, creator_devclass, 0, 0); - -static d_open_t creator_fb_open; -static d_close_t creator_fb_close; -static d_ioctl_t creator_fb_ioctl; -static d_mmap_t creator_fb_mmap; - -static struct cdevsw creator_fb_devsw = { - .d_version = D_VERSION, - .d_flags = D_NEEDGIANT, - .d_open = creator_fb_open, - .d_close = creator_fb_close, - .d_ioctl = creator_fb_ioctl, - .d_mmap = creator_fb_mmap, - .d_name = "fb", -}; - -static void creator_cursor_enable(struct creator_softc *sc, int onoff); -static void creator_cursor_install(struct creator_softc *sc); -static void creator_shutdown(void *xsc); - -static int creator_configure(int flags); - -static vi_probe_t creator_probe; -static vi_init_t creator_init; -static vi_get_info_t creator_get_info; -static vi_query_mode_t creator_query_mode; -static vi_set_mode_t creator_set_mode; -static vi_save_font_t creator_save_font; -static vi_load_font_t creator_load_font; -static vi_show_font_t creator_show_font; -static vi_save_palette_t creator_save_palette; -static vi_load_palette_t creator_load_palette; -static vi_set_border_t creator_set_border; -static vi_save_state_t creator_save_state; -static vi_load_state_t creator_load_state; -static vi_set_win_org_t creator_set_win_org; -static vi_read_hw_cursor_t creator_read_hw_cursor; -static vi_set_hw_cursor_t creator_set_hw_cursor; -static vi_set_hw_cursor_shape_t creator_set_hw_cursor_shape; -static vi_blank_display_t creator_blank_display; -static vi_mmap_t creator_mmap; -static vi_ioctl_t creator_ioctl; -static vi_clear_t creator_clear; -static vi_fill_rect_t creator_fill_rect; -static vi_bitblt_t creator_bitblt; -static vi_diag_t creator_diag; -static vi_save_cursor_palette_t creator_save_cursor_palette; -static vi_load_cursor_palette_t creator_load_cursor_palette; -static vi_copy_t creator_copy; -static vi_putp_t creator_putp; -static vi_putc_t creator_putc; -static vi_puts_t creator_puts; -static vi_putm_t creator_putm; - -static video_switch_t creatorvidsw = { - .probe = creator_probe, - .init = creator_init, - .get_info = creator_get_info, - .query_mode = creator_query_mode, - .set_mode = creator_set_mode, - .save_font = creator_save_font, - .load_font = creator_load_font, - .show_font = creator_show_font, - .save_palette = creator_save_palette, - .load_palette = creator_load_palette, - .set_border = creator_set_border, - .save_state = creator_save_state, - .load_state = creator_load_state, - .set_win_org = creator_set_win_org, - .read_hw_cursor = creator_read_hw_cursor, - .set_hw_cursor = creator_set_hw_cursor, - .set_hw_cursor_shape = creator_set_hw_cursor_shape, - .blank_display = creator_blank_display, - .mmap = creator_mmap, - .ioctl = creator_ioctl, - .clear = creator_clear, - .fill_rect = creator_fill_rect, - .bitblt = creator_bitblt, - .diag = creator_diag, - .save_cursor_palette = creator_save_cursor_palette, - .load_cursor_palette = creator_load_cursor_palette, - .copy = creator_copy, - .putp = creator_putp, - .putc = creator_putc, - .puts = creator_puts, - .putm = creator_putm -}; - -VIDEO_DRIVER(creator, creatorvidsw, creator_configure); - -extern sc_rndr_sw_t txtrndrsw; -RENDERER(creator, 0, txtrndrsw, gfb_set); - -RENDERER_MODULE(creator, gfb_set); - -static const u_char creator_mouse_pointer[64][8] __aligned(8) = { - { 0x00, 0x00, }, /* ............ */ - { 0x80, 0x00, }, /* *........... */ - { 0xc0, 0x00, }, /* **.......... */ - { 0xe0, 0x00, }, /* ***......... */ - { 0xf0, 0x00, }, /* ****........ */ - { 0xf8, 0x00, }, /* *****....... */ - { 0xfc, 0x00, }, /* ******...... */ - { 0xfe, 0x00, }, /* *******..... */ - { 0xff, 0x00, }, /* ********.... */ - { 0xff, 0x80, }, /* *********... */ - { 0xfc, 0xc0, }, /* ******..**.. */ - { 0xdc, 0x00, }, /* **.***...... */ - { 0x8e, 0x00, }, /* *...***..... */ - { 0x0e, 0x00, }, /* ....***..... */ - { 0x07, 0x00, }, /* .....***.... */ - { 0x04, 0x00, }, /* .....*...... */ - { 0x00, 0x00, }, /* ............ */ - { 0x00, 0x00, }, /* ............ */ - { 0x00, 0x00, }, /* ............ */ - { 0x00, 0x00, }, /* ............ */ - { 0x00, 0x00, }, /* ............ */ - { 0x00, 0x00, }, /* ............ */ -}; - -static inline void creator_ras_fifo_wait(struct creator_softc *sc, int n); -static inline void creator_ras_setfontinc(struct creator_softc *sc, int fontinc); -static inline void creator_ras_setfontw(struct creator_softc *sc, int fontw); -static inline void creator_ras_setbg(struct creator_softc *sc, int bg); -static inline void creator_ras_setfg(struct creator_softc *sc, int fg); -static inline void creator_ras_setpmask(struct creator_softc *sc, int pmask); -static inline void creator_ras_wait(struct creator_softc *sc); - -static inline void -creator_ras_wait(struct creator_softc *sc) -{ - int ucsr; - int r; - - for (;;) { - ucsr = FFB_READ(sc, FFB_FBC, FFB_FBC_UCSR); - if ((ucsr & (FBC_UCSR_FB_BUSY | FBC_UCSR_RP_BUSY)) == 0) - break; - r = ucsr & (FBC_UCSR_READ_ERR | FBC_UCSR_FIFO_OVFL); - if (r != 0) - FFB_WRITE(sc, FFB_FBC, FFB_FBC_UCSR, r); - } -} - -static inline void -creator_ras_fifo_wait(struct creator_softc *sc, int n) -{ - int cache; - - cache = sc->sc_fifo_cache; - while (cache < n) - cache = (FFB_READ(sc, FFB_FBC, FFB_FBC_UCSR) & - FBC_UCSR_FIFO_MASK) - 8; - sc->sc_fifo_cache = cache - n; -} - -static inline void -creator_ras_setfontinc(struct creator_softc *sc, int fontinc) -{ - - if (fontinc == sc->sc_fontinc_cache) - return; - sc->sc_fontinc_cache = fontinc; - creator_ras_fifo_wait(sc, 1); - FFB_WRITE(sc, FFB_FBC, FFB_FBC_FONTINC, fontinc); - creator_ras_wait(sc); -} - -static inline void -creator_ras_setfontw(struct creator_softc *sc, int fontw) -{ - - if (fontw == sc->sc_fontw_cache) - return; - sc->sc_fontw_cache = fontw; - creator_ras_fifo_wait(sc, 1); - FFB_WRITE(sc, FFB_FBC, FFB_FBC_FONTW, fontw); - creator_ras_wait(sc); -} - -static inline void -creator_ras_setbg(struct creator_softc *sc, int bg) -{ - - if (bg == sc->sc_bg_cache) - return; - sc->sc_bg_cache = bg; - creator_ras_fifo_wait(sc, 1); - FFB_WRITE(sc, FFB_FBC, FFB_FBC_BG, bg); - creator_ras_wait(sc); -} - -static inline void -creator_ras_setfg(struct creator_softc *sc, int fg) -{ - - if (fg == sc->sc_fg_cache) - return; - sc->sc_fg_cache = fg; - creator_ras_fifo_wait(sc, 1); - FFB_WRITE(sc, FFB_FBC, FFB_FBC_FG, fg); - creator_ras_wait(sc); -} - -static inline void -creator_ras_setpmask(struct creator_softc *sc, int pmask) -{ - - if (pmask == sc->sc_pmask_cache) - return; - sc->sc_pmask_cache = pmask; - creator_ras_fifo_wait(sc, 1); - FFB_WRITE(sc, FFB_FBC, FFB_FBC_PMASK, pmask); - creator_ras_wait(sc); -} - -/* - * video driver interface - */ -static int -creator_configure(int flags) -{ - struct creator_softc *sc; - phandle_t chosen; - phandle_t output; - ihandle_t stdout; - bus_addr_t addr; - char buf[sizeof("SUNW,ffb")]; - int i; - int space; - - /* - * For the high-level console probing return the number of - * registered adapters. - */ - if (!(flags & VIO_PROBE_ONLY)) { - for (i = 0; vid_find_adapter(CREATOR_DRIVER_NAME, i) >= 0; i++) - ; - return (i); - } - - /* Low-level console probing and initialization. */ - - sc = &creator_softc; - if (sc->sc_va.va_flags & V_ADP_REGISTERED) - goto found; - - if ((chosen = OF_finddevice("/chosen")) == -1) - return (0); - if (OF_getprop(chosen, "stdout", &stdout, sizeof(stdout)) == -1) - return (0); - if ((output = OF_instance_to_package(stdout)) == -1) - return (0); - if (OF_getprop(output, "name", buf, sizeof(buf)) == -1) - return (0); - if (strcmp(buf, "SUNW,ffb") == 0 || strcmp(buf, "SUNW,afb") == 0) { - sc->sc_flags = CREATOR_CONSOLE; - if (strcmp(buf, "SUNW,afb") == 0) - sc->sc_flags |= CREATOR_AFB; - sc->sc_node = output; - } else - return (0); - - for (i = FFB_DAC; i <= FFB_FBC; i++) { - if (OF_decode_addr(output, i, &space, &addr) != 0) - return (0); - sc->sc_bt[i] = &creator_bst_store[i - FFB_DAC]; - sc->sc_bh[i] = sparc64_fake_bustag(space, addr, sc->sc_bt[i]); - } - - if (creator_init(0, &sc->sc_va, 0) < 0) - return (0); - - found: - /* Return number of found adapters. */ - return (1); -} - -static int -creator_probe(int unit, video_adapter_t **adpp, void *arg, int flags) -{ - - return (0); -} - -static int -creator_init(int unit, video_adapter_t *adp, int flags) -{ - struct creator_softc *sc; - phandle_t options; - video_info_t *vi; - char buf[sizeof("screen-#columns")]; - - sc = (struct creator_softc *)adp; - vi = &adp->va_info; - - vid_init_struct(adp, CREATOR_DRIVER_NAME, -1, unit); - - if (OF_getprop(sc->sc_node, "height", &sc->sc_height, - sizeof(sc->sc_height)) == -1) - return (ENXIO); - if (OF_getprop(sc->sc_node, "width", &sc->sc_width, - sizeof(sc->sc_width)) == -1) - return (ENXIO); - if ((options = OF_finddevice("/options")) == -1) - return (ENXIO); - if (OF_getprop(options, "screen-#rows", buf, sizeof(buf)) == -1) - return (ENXIO); - vi->vi_height = strtol(buf, NULL, 10); - if (OF_getprop(options, "screen-#columns", buf, sizeof(buf)) == -1) - return (ENXIO); - vi->vi_width = strtol(buf, NULL, 10); - vi->vi_cwidth = gallant12x22.width; - vi->vi_cheight = gallant12x22.height; - vi->vi_flags = V_INFO_COLOR; - vi->vi_mem_model = V_INFO_MM_OTHER; - - sc->sc_font = gallant12x22.data; - sc->sc_xmargin = (sc->sc_width - (vi->vi_width * vi->vi_cwidth)) / 2; - sc->sc_ymargin = (sc->sc_height - (vi->vi_height * vi->vi_cheight)) / 2; - - creator_set_mode(adp, 0); - - if (!(sc->sc_flags & CREATOR_AFB)) { - FFB_WRITE(sc, FFB_DAC, FFB_DAC_TYPE, FFB_DAC_CFG_DID); - if (((FFB_READ(sc, FFB_DAC, FFB_DAC_VALUE) & - FFB_DAC_CFG_DID_PNUM) >> 12) != 0x236e) { - sc->sc_flags |= CREATOR_PAC1; - FFB_WRITE(sc, FFB_DAC, FFB_DAC_TYPE, FFB_DAC_CFG_UCTRL); - if (((FFB_READ(sc, FFB_DAC, FFB_DAC_VALUE) & - FFB_DAC_UCTRL_MANREV) >> 8) <= 2) - sc->sc_flags |= CREATOR_CURINV; - } - } - - creator_blank_display(adp, V_DISPLAY_ON); - creator_clear(adp); - - /* - * Setting V_ADP_MODECHANGE serves as hack so creator_set_mode() - * (which will invalidate our caches and restore our settings) is - * called when the X server shuts down. Otherwise screen corruption - * happens most of the time. - */ - adp->va_flags |= V_ADP_COLOR | V_ADP_MODECHANGE | V_ADP_BORDER | - V_ADP_INITIALIZED; - if (vid_register(adp) < 0) - return (ENXIO); - adp->va_flags |= V_ADP_REGISTERED; - - return (0); -} - -static int -creator_get_info(video_adapter_t *adp, int mode, video_info_t *info) -{ - - bcopy(&adp->va_info, info, sizeof(*info)); - return (0); -} - -static int -creator_query_mode(video_adapter_t *adp, video_info_t *info) -{ - - return (ENODEV); -} - -static int -creator_set_mode(video_adapter_t *adp, int mode) -{ - struct creator_softc *sc; - - sc = (struct creator_softc *)adp; - sc->sc_bg_cache = -1; - sc->sc_fg_cache = -1; - sc->sc_fontinc_cache = -1; - sc->sc_fontw_cache = -1; - sc->sc_pmask_cache = -1; - - creator_ras_wait(sc); - sc->sc_fifo_cache = 0; - creator_ras_fifo_wait(sc, 2); - FFB_WRITE(sc, FFB_FBC, FFB_FBC_PPC, FBC_PPC_VCE_DIS | - FBC_PPC_TBE_OPAQUE | FBC_PPC_APE_DIS | FBC_PPC_CS_CONST); - FFB_WRITE(sc, FFB_FBC, FFB_FBC_FBC, FFB_FBC_WB_A | FFB_FBC_RB_A | - FFB_FBC_SB_BOTH | FFB_FBC_XE_OFF | FFB_FBC_RGBE_MASK); - return (0); -} - -static int -creator_save_font(video_adapter_t *adp, int page, int size, int width, - u_char *data, int c, int count) -{ - - return (ENODEV); -} - -static int -creator_load_font(video_adapter_t *adp, int page, int size, int width, - u_char *data, int c, int count) -{ - - return (ENODEV); -} - -static int -creator_show_font(video_adapter_t *adp, int page) -{ - - return (ENODEV); -} - -static int -creator_save_palette(video_adapter_t *adp, u_char *palette) -{ - - return (ENODEV); -} - -static int -creator_load_palette(video_adapter_t *adp, u_char *palette) -{ - - return (ENODEV); -} - -static int -creator_set_border(video_adapter_t *adp, int border) -{ - struct creator_softc *sc; - - sc = (struct creator_softc *)adp; - creator_fill_rect(adp, border, 0, 0, sc->sc_width, sc->sc_ymargin); - creator_fill_rect(adp, border, 0, sc->sc_height - sc->sc_ymargin, - sc->sc_width, sc->sc_ymargin); - creator_fill_rect(adp, border, 0, 0, sc->sc_xmargin, sc->sc_height); - creator_fill_rect(adp, border, sc->sc_width - sc->sc_xmargin, 0, - sc->sc_xmargin, sc->sc_height); - return (0); -} - -static int -creator_save_state(video_adapter_t *adp, void *p, size_t size) -{ - - return (ENODEV); -} - -static int -creator_load_state(video_adapter_t *adp, void *p) -{ - - return (ENODEV); -} - -static int -creator_set_win_org(video_adapter_t *adp, off_t offset) -{ - - return (ENODEV); -} - -static int -creator_read_hw_cursor(video_adapter_t *adp, int *col, int *row) -{ - - *col = 0; - *row = 0; - return (0); -} - -static int -creator_set_hw_cursor(video_adapter_t *adp, int col, int row) -{ - - return (ENODEV); -} - -static int -creator_set_hw_cursor_shape(video_adapter_t *adp, int base, int height, - int celsize, int blink) -{ - - return (ENODEV); -} - -static int -creator_blank_display(video_adapter_t *adp, int mode) -{ - struct creator_softc *sc; - uint32_t v; - int i; - - sc = (struct creator_softc *)adp; - FFB_WRITE(sc, FFB_DAC, FFB_DAC_TYPE, FFB_DAC_CFG_TGEN); - v = FFB_READ(sc, FFB_DAC, FFB_DAC_VALUE); - switch (mode) { - case V_DISPLAY_ON: - v |= FFB_DAC_CFG_TGEN_VIDE; - break; - case V_DISPLAY_BLANK: - case V_DISPLAY_STAND_BY: - case V_DISPLAY_SUSPEND: - v &= ~FFB_DAC_CFG_TGEN_VIDE; - break; - } - FFB_WRITE(sc, FFB_DAC, FFB_DAC_TYPE, FFB_DAC_CFG_TGEN); - FFB_WRITE(sc, FFB_DAC, FFB_DAC_VALUE, v); - for (i = 0; i < 10; i++) { - FFB_WRITE(sc, FFB_DAC, FFB_DAC_TYPE, FFB_DAC_CFG_TGEN); - (void)FFB_READ(sc, FFB_DAC, FFB_DAC_VALUE); - } - return (0); -} - -static int -creator_mmap(video_adapter_t *adp, vm_ooffset_t offset, vm_paddr_t *paddr, - int prot, vm_memattr_t *memattr) -{ - - return (EINVAL); -} - -static int -creator_ioctl(video_adapter_t *adp, u_long cmd, caddr_t data) -{ - struct creator_softc *sc; - struct fbcursor *fbc; - struct fbtype *fb; - - sc = (struct creator_softc *)adp; - switch (cmd) { - case FBIOGTYPE: - fb = (struct fbtype *)data; - fb->fb_type = FBTYPE_CREATOR; - fb->fb_height = sc->sc_height; - fb->fb_width = sc->sc_width; - fb->fb_depth = fb->fb_cmsize = fb->fb_size = 0; - break; - case FBIOSCURSOR: - fbc = (struct fbcursor *)data; - if (fbc->set & FB_CUR_SETCUR && fbc->enable == 0) { - creator_cursor_enable(sc, 0); - sc->sc_flags &= ~CREATOR_CUREN; - } else - return (ENODEV); - break; - break; - default: - return (fb_commonioctl(adp, cmd, data)); - } - return (0); -} - -static int -creator_clear(video_adapter_t *adp) -{ - struct creator_softc *sc; - - sc = (struct creator_softc *)adp; - creator_fill_rect(adp, (SC_NORM_ATTR >> 4) & 0xf, 0, 0, sc->sc_width, - sc->sc_height); - return (0); -} - -static int -creator_fill_rect(video_adapter_t *adp, int val, int x, int y, int cx, int cy) -{ - struct creator_softc *sc; - - sc = (struct creator_softc *)adp; - creator_ras_setpmask(sc, 0xffffffff); - creator_ras_fifo_wait(sc, 2); - FFB_WRITE(sc, FFB_FBC, FFB_FBC_ROP, FBC_ROP_NEW); - FFB_WRITE(sc, FFB_FBC, FFB_FBC_DRAWOP, FBC_DRAWOP_RECTANGLE); - creator_ras_setfg(sc, creator_cmap[val & 0xf]); - /* - * Note that at least the Elite3D cards are sensitive to the order - * of operations here. - */ - creator_ras_fifo_wait(sc, 4); - FFB_WRITE(sc, FFB_FBC, FFB_FBC_BY, y); - FFB_WRITE(sc, FFB_FBC, FFB_FBC_BX, x); - FFB_WRITE(sc, FFB_FBC, FFB_FBC_BH, cy); - FFB_WRITE(sc, FFB_FBC, FFB_FBC_BW, cx); - creator_ras_wait(sc); - return (0); -} - -static int -creator_bitblt(video_adapter_t *adp, ...) -{ - - return (ENODEV); -} - -static int -creator_diag(video_adapter_t *adp, int level) -{ - video_info_t info; - - fb_dump_adp_info(adp->va_name, adp, level); - creator_get_info(adp, 0, &info); - fb_dump_mode_info(adp->va_name, adp, &info, level); - return (0); -} - -static int -creator_save_cursor_palette(video_adapter_t *adp, u_char *palette) -{ - - return (ENODEV); -} - -static int -creator_load_cursor_palette(video_adapter_t *adp, u_char *palette) -{ - - return (ENODEV); -} - -static int -creator_copy(video_adapter_t *adp, vm_offset_t src, vm_offset_t dst, int n) -{ - - return (ENODEV); -} - -static int -creator_putp(video_adapter_t *adp, vm_offset_t off, u_int32_t p, u_int32_t a, - int size, int bpp, int bit_ltor, int byte_ltor) -{ - - return (ENODEV); -} - -static int -creator_putc(video_adapter_t *adp, vm_offset_t off, u_int8_t c, u_int8_t a) -{ - struct creator_softc *sc; - const uint16_t *p; - int row; - int col; - int i; - - sc = (struct creator_softc *)adp; - row = (off / adp->va_info.vi_width) * adp->va_info.vi_cheight; - col = (off % adp->va_info.vi_width) * adp->va_info.vi_cwidth; - p = (const uint16_t *)sc->sc_font + (c * adp->va_info.vi_cheight); - creator_ras_setfg(sc, creator_cmap[a & 0xf]); - creator_ras_setbg(sc, creator_cmap[(a >> 4) & 0xf]); - creator_ras_fifo_wait(sc, 1 + adp->va_info.vi_cheight); - FFB_WRITE(sc, FFB_FBC, FFB_FBC_FONTXY, - ((row + sc->sc_ymargin) << 16) | (col + sc->sc_xmargin)); - creator_ras_setfontw(sc, adp->va_info.vi_cwidth); - creator_ras_setfontinc(sc, 0x10000); - for (i = 0; i < adp->va_info.vi_cheight; i++) { - FFB_WRITE(sc, FFB_FBC, FFB_FBC_FONT, *p++ << 16); - } - return (0); -} - -static int -creator_puts(video_adapter_t *adp, vm_offset_t off, u_int16_t *s, int len) -{ - int i; - - for (i = 0; i < len; i++) { - vidd_putc(adp, off + i, s[i] & 0xff, (s[i] & 0xff00) >> 8); - } - - return (0); -} - -static int -creator_putm(video_adapter_t *adp, int x, int y, u_int8_t *pixel_image, - u_int32_t pixel_mask, int size, int width) -{ - struct creator_softc *sc; - - sc = (struct creator_softc *)adp; - if (!(sc->sc_flags & CREATOR_CUREN)) { - creator_cursor_install(sc); - creator_cursor_enable(sc, 1); - sc->sc_flags |= CREATOR_CUREN; - } - FFB_WRITE(sc, FFB_DAC, FFB_DAC_TYPE2, FFB_DAC_CUR_POS); - FFB_WRITE(sc, FFB_DAC, FFB_DAC_VALUE2, - ((y + sc->sc_ymargin) << 16) | (x + sc->sc_xmargin)); - return (0); -} - -/* - * bus interface - */ -static int -creator_bus_probe(device_t dev) -{ - const char *name; - phandle_t node; - int type; - - name = ofw_bus_get_name(dev); - node = ofw_bus_get_node(dev); - if (strcmp(name, "SUNW,ffb") == 0) { - if (OF_getprop(node, "board_type", &type, sizeof(type)) == -1) - return (ENXIO); - switch (type & 7) { - case 0x0: - device_set_desc(dev, "Creator"); - break; - case 0x3: - device_set_desc(dev, "Creator3D"); - break; - default: - return (ENXIO); - } - } else if (strcmp(name, "SUNW,afb") == 0) - device_set_desc(dev, "Elite3D"); - else - return (ENXIO); - return (BUS_PROBE_DEFAULT); -} - -static int -creator_bus_attach(device_t dev) -{ - struct creator_softc *sc; - video_adapter_t *adp; - video_switch_t *sw; - phandle_t node; - int error; - int rid; - int unit; - int i; - - node = ofw_bus_get_node(dev); - if ((sc = (struct creator_softc *)vid_get_adapter(vid_find_adapter( - CREATOR_DRIVER_NAME, 0))) != NULL && sc->sc_node == node) { - device_printf(dev, "console\n"); - device_set_softc(dev, sc); - } else { - sc = device_get_softc(dev); - sc->sc_node = node; - } - adp = &sc->sc_va; - - /* - * Allocate resources regardless of whether we are the console - * and already obtained the bus tags and handles for the FFB_DAC - * and FFB_FBC register banks in creator_configure() or not so - * the resources are marked as taken in the respective RMAN. - * The supported cards use either 15 (Creator, Elite3D?) or 24 - * (Creator3D?) register banks. We make sure that we can also - * allocate the resources for at least the FFB_DAC and FFB_FBC - * banks here. We try but don't actually care whether we can - * allocate more than these two resources and just limit the - * range accessible via creator_fb_mmap() accordingly. - */ - for (i = 0; i < FFB_NREG; i++) { - rid = i; - sc->sc_reg[i] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, - &rid, RF_ACTIVE); - if (sc->sc_reg[i] == NULL) { - if (i <= FFB_FBC) { - device_printf(dev, - "cannot allocate resources\n"); - error = ENXIO; - goto fail; - } - break; - } - sc->sc_bt[i] = rman_get_bustag(sc->sc_reg[i]); - sc->sc_bh[i] = rman_get_bushandle(sc->sc_reg[i]); - } - /* - * The XFree86/X.Org sunffb(4) expects to be able to access the - * memory spanned by the first and the last resource as one chunk - * via creator_fb_mmap(), using offsets from the first resource, - * even though the backing resources are actually non-continuous. - * So make sure that the memory we provide is at least backed by - * increasing resources. - */ - for (i = 1; i < FFB_NREG && sc->sc_reg[i] != NULL && - rman_get_start(sc->sc_reg[i]) > rman_get_start(sc->sc_reg[i - 1]); - i++) - ; - sc->sc_reg_size = rman_get_end(sc->sc_reg[i - 1]) - - rman_get_start(sc->sc_reg[0]) + 1; - - if (!(sc->sc_flags & CREATOR_CONSOLE)) { - if ((sw = vid_get_switch(CREATOR_DRIVER_NAME)) == NULL) { - device_printf(dev, "cannot get video switch\n"); - error = ENODEV; - goto fail; - } - /* - * During device configuration we don't necessarily probe - * the adapter which is the console first so we can't use - * the device unit number for the video adapter unit. The - * worst case would be that we use the video adapter unit - * 0 twice. As it doesn't really matter which unit number - * the corresponding video adapter has just use the next - * unused one. - */ - for (i = 0; i < devclass_get_maxunit(creator_devclass); i++) - if (vid_find_adapter(CREATOR_DRIVER_NAME, i) < 0) - break; - if (strcmp(ofw_bus_get_name(dev), "SUNW,afb") == 0) - sc->sc_flags |= CREATOR_AFB; - if ((error = sw->init(i, adp, 0)) != 0) { - device_printf(dev, "cannot initialize adapter\n"); - goto fail; - } - } - - if (bootverbose) { - if (sc->sc_flags & CREATOR_PAC1) - device_printf(dev, - "BT9068/PAC1 RAMDAC (%s cursor control)\n", - sc->sc_flags & CREATOR_CURINV ? "inverted" : - "normal"); - else - device_printf(dev, "BT498/PAC2 RAMDAC\n"); - } - device_printf(dev, "resolution %dx%d\n", sc->sc_width, sc->sc_height); - - unit = device_get_unit(dev); - sc->sc_si = make_dev(&creator_fb_devsw, unit, UID_ROOT, GID_WHEEL, - 0600, "fb%d", unit); - sc->sc_si->si_drv1 = sc; - - EVENTHANDLER_REGISTER(shutdown_final, creator_shutdown, sc, - SHUTDOWN_PRI_DEFAULT); - - return (0); - - fail: - for (i = 0; i < FFB_NREG && sc->sc_reg[i] != NULL; i++) - bus_release_resource(dev, SYS_RES_MEMORY, - rman_get_rid(sc->sc_reg[i]), sc->sc_reg[i]); - return (error); -} - -/* - * /dev/fb interface - */ -static int -creator_fb_open(struct cdev *dev, int flags, int mode, struct thread *td) -{ - - return (0); -} - -static int -creator_fb_close(struct cdev *dev, int flags, int mode, struct thread *td) -{ - - return (0); -} - -static int -creator_fb_ioctl(struct cdev *dev, u_long cmd, caddr_t data, int flags, - struct thread *td) -{ - struct creator_softc *sc; - - sc = dev->si_drv1; - return (creator_ioctl(&sc->sc_va, cmd, data)); -} - -static int -creator_fb_mmap(struct cdev *dev, vm_ooffset_t offset, vm_paddr_t *paddr, - int prot, vm_memattr_t *memattr) -{ - struct creator_softc *sc; - int i; - - /* - * NB: This is a special implementation based on the /dev/fb - * requirements of the XFree86/X.Org sunffb(4). - */ - sc = dev->si_drv1; - for (i = 0; i < CREATOR_FB_MAP_SIZE; i++) { - if (offset >= creator_fb_map[i].virt && - offset < creator_fb_map[i].virt + creator_fb_map[i].size) { - offset += creator_fb_map[i].phys - - creator_fb_map[i].virt; - if (offset >= sc->sc_reg_size) - return (EINVAL); - *paddr = sc->sc_bh[0] + offset; - return (0); - } - } - return (EINVAL); -} - -/* - * internal functions - */ -static void -creator_cursor_enable(struct creator_softc *sc, int onoff) -{ - int v; - - FFB_WRITE(sc, FFB_DAC, FFB_DAC_TYPE2, FFB_DAC_CUR_CTRL); - if (sc->sc_flags & CREATOR_CURINV) - v = onoff ? FFB_DAC_CUR_CTRL_P0 | FFB_DAC_CUR_CTRL_P1 : 0; - else - v = onoff ? 0 : FFB_DAC_CUR_CTRL_P0 | FFB_DAC_CUR_CTRL_P1; - FFB_WRITE(sc, FFB_DAC, FFB_DAC_VALUE2, v); -} - -static void -creator_cursor_install(struct creator_softc *sc) -{ - int i, j; - - creator_cursor_enable(sc, 0); - FFB_WRITE(sc, FFB_DAC, FFB_DAC_TYPE2, FFB_DAC_CUR_COLOR1); - FFB_WRITE(sc, FFB_DAC, FFB_DAC_VALUE2, 0xffffff); - FFB_WRITE(sc, FFB_DAC, FFB_DAC_VALUE2, 0x0); - for (i = 0; i < 2; i++) { - FFB_WRITE(sc, FFB_DAC, FFB_DAC_TYPE2, - i ? FFB_DAC_CUR_BITMAP_P0 : FFB_DAC_CUR_BITMAP_P1); - for (j = 0; j < 64; j++) { - FFB_WRITE(sc, FFB_DAC, FFB_DAC_VALUE2, - *(const uint32_t *)(&creator_mouse_pointer[j][0])); - FFB_WRITE(sc, FFB_DAC, FFB_DAC_VALUE2, - *(const uint32_t *)(&creator_mouse_pointer[j][4])); - } - } -} - -static void -creator_shutdown(void *xsc) -{ - struct creator_softc *sc = xsc; - - creator_cursor_enable(sc, 0); - /* - * In case this is the console set the cursor of the stdout - * instance to the start of the last line so OFW output ends - * up beneath what FreeBSD left on the screen. - */ - if (sc->sc_flags & CREATOR_CONSOLE) { - OF_interpret("stdout @ is my-self 0 to column#", 0); - OF_interpret("stdout @ is my-self #lines 1 - to line#", 0); - } -} diff --git a/sys/dev/fb/creator_vt.c b/sys/dev/fb/creator_vt.c deleted file mode 100644 index e6a97c1d58b..00000000000 --- a/sys/dev/fb/creator_vt.c +++ /dev/null @@ -1,273 +0,0 @@ -/*- - * Copyright (c) 2014 Nathan Whitehorn - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include - -#include -#include -#include -#include - -#include -#include -#include - -#include -#include - -#include -#include "creatorreg.h" - -static vd_probe_t creatorfb_probe; -static vd_init_t creatorfb_init; -static vd_blank_t creatorfb_blank; -static vd_bitblt_text_t creatorfb_bitblt_text; -static vd_bitblt_bmp_t creatorfb_bitblt_bitmap; - -static const struct vt_driver vt_creatorfb_driver = { - .vd_name = "creatorfb", - .vd_probe = creatorfb_probe, - .vd_init = creatorfb_init, - .vd_blank = creatorfb_blank, - .vd_bitblt_text = creatorfb_bitblt_text, - .vd_bitblt_bmp = creatorfb_bitblt_bitmap, - .vd_fb_ioctl = vt_fb_ioctl, - .vd_fb_mmap = vt_fb_mmap, - .vd_priority = VD_PRIORITY_SPECIFIC -}; - -struct creatorfb_softc { - struct fb_info fb; - struct bus_space_tag memt[1]; - bus_space_handle_t memh; -}; - -static struct creatorfb_softc creatorfb_conssoftc; -VT_DRIVER_DECLARE(vt_creatorfb, vt_creatorfb_driver); - -static int -creatorfb_probe(struct vt_device *vd) -{ - phandle_t chosen, node; - ihandle_t stdout; - char type[64], name[64]; - - chosen = OF_finddevice("/chosen"); - OF_getprop(chosen, "stdout", &stdout, sizeof(stdout)); - node = OF_instance_to_package(stdout); - if (node == -1) { - /* - * The "/chosen/stdout" does not exist try - * using "screen" directly. - */ - node = OF_finddevice("screen"); - } - OF_getprop(node, "device_type", type, sizeof(type)); - if (strcmp(type, "display") != 0) - return (CN_DEAD); - - OF_getprop(node, "name", name, sizeof(name)); - if (strcmp(name, "SUNW,ffb") != 0 && strcmp(name, "SUNW,afb") != 0) - return (CN_DEAD); - - /* Looks OK... */ - return (CN_INTERNAL); -} - -static int -creatorfb_init(struct vt_device *vd) -{ - struct creatorfb_softc *sc; - phandle_t chosen; - phandle_t node; - ihandle_t handle; - uint32_t height, width; - char type[64], name[64]; - bus_addr_t phys; - int space; - - /* Initialize softc */ - vd->vd_softc = sc = &creatorfb_conssoftc; - - chosen = OF_finddevice("/chosen"); - OF_getprop(chosen, "stdout", &handle, sizeof(ihandle_t)); - node = OF_instance_to_package(handle); - if (node == -1) { - /* - * The "/chosen/stdout" does not exist try - * using "screen" directly. - */ - node = OF_finddevice("screen"); - handle = OF_open("screen"); - } - OF_getprop(node, "device_type", type, sizeof(type)); - if (strcmp(type, "display") != 0) - return (CN_DEAD); - - OF_getprop(node, "name", name, sizeof(name)); - if (strcmp(name, "SUNW,ffb") != 0 && strcmp(name, "SUNW,afb") != 0) - return (CN_DEAD); - - /* Make sure we have needed properties */ - if (OF_getproplen(node, "height") != sizeof(height) || - OF_getproplen(node, "width") != sizeof(width)) - return (CN_DEAD); - - OF_getprop(node, "height", &height, sizeof(height)); - OF_getprop(node, "width", &width, sizeof(width)); - - sc->fb.fb_height = height; - sc->fb.fb_width = width; - sc->fb.fb_bpp = sc->fb.fb_depth = 32; - sc->fb.fb_stride = 8192; /* Fixed */ - sc->fb.fb_size = sc->fb.fb_height * sc->fb.fb_stride; - - /* Map linear framebuffer */ - if (OF_decode_addr(node, FFB_DFB24, &space, &phys) != 0) - return (CN_DEAD); - sc->fb.fb_pbase = phys; - sc->memh = sparc64_fake_bustag(space, phys, &sc->memt[0]); - - /* 32-bit VGA palette */ - vt_generate_cons_palette(sc->fb.fb_cmap, COLOR_FORMAT_RGB, - 255, 0, 255, 8, 255, 16); - sc->fb.fb_cmsize = 16; - - vt_fb_init(vd); - - return (CN_INTERNAL); -} - -static void -creatorfb_blank(struct vt_device *vd, term_color_t color) -{ - struct creatorfb_softc *sc; - uint32_t c; - int i; - - sc = vd->vd_softc; - c = sc->fb.fb_cmap[color]; - - for (i = 0; i < sc->fb.fb_height; i++) - bus_space_set_region_4(sc->memt, sc->memh, i*sc->fb.fb_stride, - c, sc->fb.fb_width); -} - -static void -creatorfb_bitblt_bitmap(struct vt_device *vd, const struct vt_window *vw, - const uint8_t *pattern, const uint8_t *mask, - unsigned int width, unsigned int height, - unsigned int x, unsigned int y, term_color_t fg, term_color_t bg) -{ - struct creatorfb_softc *sc = vd->vd_softc; - u_long line; - uint32_t fgc, bgc; - int c, l; - uint8_t b, m; - - fgc = sc->fb.fb_cmap[fg]; - bgc = sc->fb.fb_cmap[bg]; - b = m = 0; - - line = (sc->fb.fb_stride * y) + 4*x; - for (l = 0; - l < height && y + l < vw->vw_draw_area.tr_end.tp_row; - l++) { - for (c = 0; - c < width && x + c < vw->vw_draw_area.tr_end.tp_col; - c++) { - if (c % 8 == 0) - b = *pattern++; - else - b <<= 1; - if (mask != NULL) { - if (c % 8 == 0) - m = *mask++; - else - m <<= 1; - /* Skip pixel write if mask not set. */ - if ((m & 0x80) == 0) - continue; - } - bus_space_write_4(sc->memt, sc->memh, line + 4*c, - (b & 0x80) ? fgc : bgc); - } - line += sc->fb.fb_stride; - } -} - -void -creatorfb_bitblt_text(struct vt_device *vd, const struct vt_window *vw, - const term_rect_t *area) -{ - unsigned int col, row, x, y; - struct vt_font *vf; - term_char_t c; - term_color_t fg, bg; - const uint8_t *pattern; - - vf = vw->vw_font; - - for (row = area->tr_begin.tp_row; row < area->tr_end.tp_row; ++row) { - for (col = area->tr_begin.tp_col; col < area->tr_end.tp_col; - ++col) { - x = col * vf->vf_width + - vw->vw_draw_area.tr_begin.tp_col; - y = row * vf->vf_height + - vw->vw_draw_area.tr_begin.tp_row; - - c = VTBUF_GET_FIELD(&vw->vw_buf, row, col); - pattern = vtfont_lookup(vf, c); - vt_determine_colors(c, - VTBUF_ISCURSOR(&vw->vw_buf, row, col), &fg, &bg); - - creatorfb_bitblt_bitmap(vd, vw, - pattern, NULL, vf->vf_width, vf->vf_height, - x, y, fg, bg); - } - } - -#ifndef SC_NO_CUTPASTE - if (!vd->vd_mshown) - return; - - term_rect_t drawn_area; - - drawn_area.tr_begin.tp_col = area->tr_begin.tp_col * vf->vf_width; - drawn_area.tr_begin.tp_row = area->tr_begin.tp_row * vf->vf_height; - drawn_area.tr_end.tp_col = area->tr_end.tp_col * vf->vf_width; - drawn_area.tr_end.tp_row = area->tr_end.tp_row * vf->vf_height; - - if (vt_is_cursor_in_area(vd, &drawn_area)) { - creatorfb_bitblt_bitmap(vd, vw, - vd->vd_mcursor->map, vd->vd_mcursor->mask, - vd->vd_mcursor->width, vd->vd_mcursor->height, - vd->vd_mx_drawn + vw->vw_draw_area.tr_begin.tp_col, - vd->vd_my_drawn + vw->vw_draw_area.tr_begin.tp_row, - vd->vd_mcursor_fg, vd->vd_mcursor_bg); - } -#endif -} diff --git a/sys/dev/fb/creatorreg.h b/sys/dev/fb/creatorreg.h deleted file mode 100644 index 0c26f70c938..00000000000 --- a/sys/dev/fb/creatorreg.h +++ /dev/null @@ -1,248 +0,0 @@ -/*- - * Copyright (C) 2000 David S. Miller (davem@redhat.com) - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * DAVID MILLER BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * from: XFree86: ffb_dac.h,v 1.1 2000/05/23 04:47:44 dawes Exp - */ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2003 Jake Burkholder. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - */ - -#ifndef _DEV_FB_CREATORREG_H_ -#define _DEV_FB_CREATORREG_H_ - -#define FFB_NREG 24 - -#define FFB_PROM 0 -#define FFB_DAC 1 -#define FFB_FBC 2 -#define FFB_DFB8R 3 -#define FFB_DFB8G 4 -#define FFB_DFB8B 5 -#define FFB_DFB8X 6 -#define FFB_DFB24 7 -#define FFB_DFB32 8 -#define FFB_SFB8R 9 -#define FFB_SFB8G 10 -#define FFB_SFB8B 11 -#define FFB_SFB8X 12 -#define FFB_SFB32 13 -#define FFB_SFB64 14 -#define FFB_DFB422A 15 - -#define FFB_DAC_TYPE 0x0 -#define FFB_DAC_VALUE 0x4 -#define FFB_DAC_TYPE2 0x8 -#define FFB_DAC_VALUE2 0xc - -/* FFB_DAC_TYPE configuration and palette register addresses */ -#define FFB_DAC_CFG_UCTRL 0x1001 /* User Control */ -#define FFB_DAC_CFG_TGEN 0x6000 /* Timing Generator Control */ -#define FFB_DAC_CFG_DID 0x8000 /* Device Identification */ - -/* FFB_DAC_CFG_UCTRL register */ -#define FFB_DAC_UCTRL_IPDISAB 0x0001 /* Input Pullup Resistor Dis. */ -#define FFB_DAC_UCTRL_ABLANK 0x0002 /* Asynchronous Blank */ -#define FFB_DAC_UCTRL_DBENAB 0x0004 /* Double-Buffer Enable */ -#define FFB_DAC_UCTRL_OVENAB 0x0008 /* Overlay Enable */ -#define FFB_DAC_UCTRL_WMODE 0x0030 /* Window Mode */ -#define FFB_DAC_UCTRL_WM_COMB 0x0000 /* Window Mode Combined */ -#define FFB_DAC_UCTRL_WM_S4 0x0010 /* Window Mode Separate 4 */ -#define FFB_DAC_UCTRL_WM_S8 0x0020 /* Window Mode Separate 8 */ -#define FFB_DAC_UCTRL_WM_RESV 0x0030 /* Window Mode Reserved */ -#define FFB_DAC_UCTRL_MANREV 0x0f00 /* Manufacturing Revision */ - -/* FFB_DAC_CFG_TGEN register */ -#define FFB_DAC_CFG_TGEN_VIDE 0x01 /* Video Enable */ -#define FFB_DAC_CFG_TGEN_TGE 0x02 /* Timing Generator Enable */ -#define FFB_DAC_CFG_TGEN_HSD 0x04 /* HSYNC* Disable */ -#define FFB_DAC_CFG_TGEN_VSD 0x08 /* VSYNC* Disable */ -#define FFB_DAC_CFG_TGEN_EQD 0x10 /* Equalization Disable */ -#define FFB_DAC_CFG_TGEN_MM 0x20 /* 0 = Slave, 1 = Master */ -#define FFB_DAC_CFG_TGEN_IM 0x40 /* 1 = Interlaced Mode */ - -/* FFB_DAC_CFG_DID register */ -#define FFB_DAC_CFG_DID_ONE 0x00000001 /* Always Set */ -#define FFB_DAC_CFG_DID_MANUF 0x00000ffe /* DAC Manufacturer ID */ -#define FFB_DAC_CFG_DID_PNUM 0x0ffff000 /* DAC Part Number */ -#define FFB_DAC_CFG_DID_REV 0xf0000000 /* DAC Revision */ - -/* FFB_DAC_TYPE2 cursor register addresses */ -#define FFB_DAC_CUR_BITMAP_P0 0x0 /* Plane 0 Cursor Bitmap */ -#define FFB_DAC_CUR_BITMAP_P1 0x80 /* Plane 1 Cursor Bitmap */ -#define FFB_DAC_CUR_CTRL 0x100 /* Cursor Control */ -#define FFB_DAC_CUR_COLOR0 0x101 /* Cursor Color 0 */ -#define FFB_DAC_CUR_COLOR1 0x102 /* Cursor Color 1 (bg) */ -#define FFB_DAC_CUR_COLOR2 0x103 /* Cursor Color 2 (fg) */ -#define FFB_DAC_CUR_POS 0x104 /* Active Cursor Position */ - -/* FFB_DAC_CUR_CTRL register (might be inverted on PAC1 DACs) */ -#define FFB_DAC_CUR_CTRL_P0 0x1 /* Plane0 Display Disable */ -#define FFB_DAC_CUR_CTRL_P1 0x2 /* Plane1 Display Disable */ - -#define FFB_FBC_BY 0x60 -#define FFB_FBC_BX 0x64 -#define FFB_FBC_DY 0x68 -#define FFB_FBC_DX 0x6c -#define FFB_FBC_BH 0x70 -#define FFB_FBC_BW 0x74 -#define FFB_FBC_PPC 0x200 /* Pixel Processor Control */ -#define FFB_FBC_FG 0x208 /* Foreground */ -#define FFB_FBC_BG 0x20c /* Background */ -#define FFB_FBC_FBC 0x254 /* Frame Buffer Control */ -#define FFB_FBC_ROP 0x258 /* Raster Operation */ -#define FFB_FBC_PMASK 0x290 /* Pixel Mask */ -#define FFB_FBC_DRAWOP 0x300 /* Draw Operation */ -#define FFB_FBC_FONTXY 0x314 /* Font X/Y */ -#define FFB_FBC_FONTW 0x318 /* Font Width */ -#define FFB_FBC_FONTINC 0x31c /* Font Increment */ -#define FFB_FBC_FONT 0x320 /* Font Data */ -#define FFB_FBC_UCSR 0x900 /* User Control & Status */ - -#define FBC_PPC_VCE_DIS 0x00001000 -#define FBC_PPC_APE_DIS 0x00000800 -#define FBC_PPC_TBE_OPAQUE 0x00000200 -#define FBC_PPC_CS_CONST 0x00000003 - -#define FFB_FBC_WB_A 0x20000000 -#define FFB_FBC_RB_A 0x00004000 -#define FFB_FBC_SB_BOTH 0x00003000 -#define FFB_FBC_XE_OFF 0x00000040 -#define FFB_FBC_RGBE_MASK 0x0000003f - -#define FBC_ROP_NEW 0x83 - -#define FBC_DRAWOP_RECTANGLE 0x08 - -#define FBC_UCSR_FIFO_OVFL 0x80000000 -#define FBC_UCSR_READ_ERR 0x40000000 -#define FBC_UCSR_RP_BUSY 0x02000000 -#define FBC_UCSR_FB_BUSY 0x01000000 -#define FBC_UCSR_FIFO_MASK 0x00000fff - -#define FFB_VIRT_SFB8R 0x00000000 -#define FFB_VIRT_SFB8G 0x00400000 -#define FFB_VIRT_SFB8B 0x00800000 -#define FFB_VIRT_SFB8X 0x00c00000 -#define FFB_VIRT_SFB32 0x01000000 -#define FFB_VIRT_SFB64 0x02000000 -#define FFB_VIRT_FBC 0x04000000 -#define FFB_VIRT_FBC_BM 0x04002000 -#define FFB_VIRT_DFB8R 0x04004000 -#define FFB_VIRT_DFB8G 0x04404000 -#define FFB_VIRT_DFB8B 0x04804000 -#define FFB_VIRT_DFB8X 0x04c04000 -#define FFB_VIRT_DFB24 0x05004000 -#define FFB_VIRT_DFB32 0x06004000 -#define FFB_VIRT_DFB422A 0x07004000 -#define FFB_VIRT_DFB422AD 0x07804000 -#define FFB_VIRT_DFB24B 0x08004000 -#define FFB_VIRT_DFB422B 0x09004000 -#define FFB_VIRT_DFB422BD 0x09804000 -#define FFB_VIRT_SFB16Z 0x0a004000 -#define FFB_VIRT_SFB8Z 0x0a404000 -#define FFB_VIRT_SFB422 0x0ac04000 -#define FFB_VIRT_SFB422D 0x0b404000 -#define FFB_VIRT_FBC_KREG 0x0bc04000 -#define FFB_VIRT_DAC 0x0bc06000 -#define FFB_VIRT_PROM 0x0bc08000 -#define FFB_VIRT_EXP 0x0bc18000 - -#define FFB_PHYS_SFB8R 0x04000000 -#define FFB_PHYS_SFB8G 0x04400000 -#define FFB_PHYS_SFB8B 0x04800000 -#define FFB_PHYS_SFB8X 0x04c00000 -#define FFB_PHYS_SFB32 0x05000000 -#define FFB_PHYS_SFB64 0x06000000 -#define FFB_PHYS_FBC 0x00600000 -#define FFB_PHYS_FBC_BM 0x00600000 -#define FFB_PHYS_DFB8R 0x01000000 -#define FFB_PHYS_DFB8G 0x01400000 -#define FFB_PHYS_DFB8B 0x01800000 -#define FFB_PHYS_DFB8X 0x01c00000 -#define FFB_PHYS_DFB24 0x02000000 -#define FFB_PHYS_DFB32 0x03000000 -#define FFB_PHYS_DFB422A 0x09000000 -#define FFB_PHYS_DFB422AD 0x09800000 -#define FFB_PHYS_DFB24B 0x0a000000 -#define FFB_PHYS_DFB422B 0x0b000000 -#define FFB_PHYS_DFB422BD 0x0b800000 -#define FFB_PHYS_SFB16Z 0x0c800000 -#define FFB_PHYS_SFB8Z 0x0c000000 -#define FFB_PHYS_SFB422 0x0d000000 -#define FFB_PHYS_SFB422D 0x0d800000 -#define FFB_PHYS_FBC_KREG 0x00610000 -#define FFB_PHYS_DAC 0x00400000 -#define FFB_PHYS_PROM 0x00000000 -#define FFB_PHYS_EXP 0x00200000 - -#define FFB_SIZE_SFB8R 0x00400000 -#define FFB_SIZE_SFB8G 0x00400000 -#define FFB_SIZE_SFB8B 0x00400000 -#define FFB_SIZE_SFB8X 0x00400000 -#define FFB_SIZE_SFB32 0x01000000 -#define FFB_SIZE_SFB64 0x02000000 -#define FFB_SIZE_FBC 0x00002000 -#define FFB_SIZE_FBC_BM 0x00002000 -#define FFB_SIZE_DFB8R 0x00400000 -#define FFB_SIZE_DFB8G 0x00400000 -#define FFB_SIZE_DFB8B 0x00400000 -#define FFB_SIZE_DFB8X 0x00400000 -#define FFB_SIZE_DFB24 0x01000000 -#define FFB_SIZE_DFB32 0x01000000 -#define FFB_SIZE_DFB422A 0x00800000 -#define FFB_SIZE_DFB422AD 0x00800000 -#define FFB_SIZE_DFB24B 0x01000000 -#define FFB_SIZE_DFB422B 0x00800000 -#define FFB_SIZE_DFB422BD 0x00800000 -#define FFB_SIZE_SFB16Z 0x00800000 -#define FFB_SIZE_SFB8Z 0x00800000 -#define FFB_SIZE_SFB422 0x00800000 -#define FFB_SIZE_SFB422D 0x00800000 -#define FFB_SIZE_FBC_KREG 0x00002000 -#define FFB_SIZE_DAC 0x00002000 -#define FFB_SIZE_PROM 0x00010000 -#define FFB_SIZE_EXP 0x00002000 - -#endif /* !_DEV_FB_CREATORREG_H_ */ diff --git a/sys/dev/fb/gallant12x22.c b/sys/dev/fb/gallant12x22.c deleted file mode 100644 index 5fffdc1e1b3..00000000000 --- a/sys/dev/fb/gallant12x22.c +++ /dev/null @@ -1,6195 +0,0 @@ -/* $OpenBSD: gallant12x22.h,v 1.2 2002/05/09 08:59:03 maja Exp $ */ -/* $NetBSD: gallant12x22.h,v 1.2 1999/05/18 21:51:58 ad Exp $ */ - -/*- - * SPDX-License-Identifier: BSD-3-Clause - * - * Copyright (c) 1992, 1993 - * The Regents of the University of California. All rights reserved. - * - * This code is derived from software contributed to the Computer Systems - * Engineering Group at Lawrence Berkeley Laboratory and to the University - * of California at Berkeley by Jef Poskanzer. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the University nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * Derived from: @(#)gallant19.h 8.1 (Berkeley) 6/11/93 - */ - -#include - -#include - -#include - -const struct gfb_font gallant12x22 = { - 12, - 22, - { - /* 0 0x00 '^@' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 1 0x01 '^A' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 2 0x02 '^B' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 3 0x03 '^C' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 4 0x04 '^D' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 5 0x05 '^E' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 6 0x06 '^F' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 7 0x07 '^G' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 8 0x08 '^H' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 9 0x09 '^I' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 10 0x0a '^J' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 11 0x0b '^K' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 12 0x0c '^L' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 13 0x0d '^M' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 14 0x0e '^N' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 15 0x0f '^O' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 16 0x10 '^P' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 17 0x11 '^Q' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 18 0x12 '^R' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 19 0x13 '^S' */ - 0x00, 0x00, /* ............ */ - 0x31, 0x80, /* ..**...**... */ - 0x31, 0x80, /* ..**...**... */ - 0x31, 0x80, /* ..**...**... */ - 0x31, 0x80, /* ..**...**... */ - 0x31, 0x80, /* ..**...**... */ - 0x31, 0x80, /* ..**...**... */ - 0x31, 0x80, /* ..**...**... */ - 0x31, 0x80, /* ..**...**... */ - 0x31, 0x80, /* ..**...**... */ - 0x31, 0x80, /* ..**...**... */ - 0x31, 0x80, /* ..**...**... */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x31, 0x80, /* ..**...**... */ - 0x31, 0x80, /* ..**...**... */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 20 0x14 '^T' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x1f, 0xf0, /* ...********* */ - 0x3c, 0xc0, /* ..****..**.. */ - 0x7c, 0xc0, /* .*****..**.. */ - 0x7c, 0xc0, /* .*****..**.. */ - 0x7c, 0xc0, /* .*****..**.. */ - 0x3c, 0xc0, /* ..****..**.. */ - 0x1c, 0xc0, /* ...***..**.. */ - 0x0c, 0xc0, /* ....**..**.. */ - 0x0c, 0xc0, /* ....**..**.. */ - 0x0c, 0xc0, /* ....**..**.. */ - 0x0c, 0xc0, /* ....**..**.. */ - 0x0c, 0xc0, /* ....**..**.. */ - 0x0c, 0xc0, /* ....**..**.. */ - 0x1c, 0xe0, /* ...***..***. */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 21 0x15 '^U' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x1f, 0x00, /* ...*****.... */ - 0x31, 0x80, /* ..**...**... */ - 0x31, 0x80, /* ..**...**... */ - 0x30, 0x00, /* ..**........ */ - 0x30, 0x00, /* ..**........ */ - 0x1f, 0x00, /* ...*****.... */ - 0x31, 0x80, /* ..**...**... */ - 0x31, 0x80, /* ..**...**... */ - 0x1f, 0x00, /* ...*****.... */ - 0x01, 0x80, /* .......**... */ - 0x01, 0x80, /* .......**... */ - 0x31, 0x80, /* ..**...**... */ - 0x31, 0x80, /* ..**...**... */ - 0x1f, 0x00, /* ...*****.... */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 22 0x16 '^V' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 23 0x17 '^W' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 24 0x18 '^X' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 25 0x19 '^Y' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 26 0x1a '^Z' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 27 0x1b '^[' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 28 0x1c '^\' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 29 0x1d '^]' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 30 0x1e '^^' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 31 0x1f '^_' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 32 0x20 ' ' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 33 0x21 '!' */ - 0x00, 0x00, /* ............ */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 34 0x22 '"' */ - 0x00, 0x00, /* ............ */ - 0x19, 0x80, /* ...**..**... */ - 0x19, 0x80, /* ...**..**... */ - 0x19, 0x80, /* ...**..**... */ - 0x19, 0x80, /* ...**..**... */ - 0x19, 0x80, /* ...**..**... */ - 0x19, 0x80, /* ...**..**... */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 35 0x23 '#' */ - 0x00, 0x00, /* ............ */ - 0x03, 0x30, /* ......**..** */ - 0x03, 0x30, /* ......**..** */ - 0x03, 0x30, /* ......**..** */ - 0x06, 0x60, /* .....**..**. */ - 0x1f, 0xf0, /* ...********* */ - 0x1f, 0xf0, /* ...********* */ - 0x0c, 0xc0, /* ....**..**.. */ - 0x0c, 0xc0, /* ....**..**.. */ - 0x19, 0x80, /* ...**..**... */ - 0x19, 0x80, /* ...**..**... */ - 0x7f, 0xc0, /* .*********.. */ - 0x7f, 0xc0, /* .*********.. */ - 0x33, 0x00, /* ..**..**.... */ - 0x66, 0x00, /* .**..**..... */ - 0x66, 0x00, /* .**..**..... */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 36 0x24 '$' */ - 0x00, 0x00, /* ............ */ - 0x06, 0x00, /* .....**..... */ - 0x1f, 0x80, /* ...******... */ - 0x3f, 0xc0, /* ..********.. */ - 0x66, 0xe0, /* .**..**.***. */ - 0x66, 0x60, /* .**..**..**. */ - 0x66, 0x00, /* .**..**..... */ - 0x3e, 0x00, /* ..*****..... */ - 0x1f, 0x80, /* ...******... */ - 0x07, 0xc0, /* .....*****.. */ - 0x06, 0x60, /* .....**..**. */ - 0x06, 0x60, /* .....**..**. */ - 0x66, 0x60, /* .**..**..**. */ - 0x7f, 0xc0, /* .*********.. */ - 0x3f, 0x80, /* ..*******... */ - 0x06, 0x00, /* .....**..... */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 37 0x25 '%' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x38, 0xc0, /* ..***...**.. */ - 0x4c, 0xc0, /* .*..**..**.. */ - 0x45, 0x80, /* .*...*.**... */ - 0x65, 0x80, /* .**..*.**... */ - 0x3b, 0x00, /* ..***.**.... */ - 0x03, 0x00, /* ......**.... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x0c, 0x00, /* ....**...... */ - 0x0d, 0xc0, /* ....**.***.. */ - 0x1a, 0x60, /* ...**.*..**. */ - 0x1a, 0x20, /* ...**.*...*. */ - 0x33, 0x20, /* ..**..**..*. */ - 0x31, 0xc0, /* ..**...***.. */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 38 0x26 '&' */ - 0x00, 0x00, /* ............ */ - 0x07, 0x00, /* .....***.... */ - 0x0f, 0x80, /* ....*****... */ - 0x18, 0xc0, /* ...**...**.. */ - 0x18, 0xc0, /* ...**...**.. */ - 0x18, 0xc0, /* ...**...**.. */ - 0x0f, 0x80, /* ....*****... */ - 0x1e, 0x00, /* ...****..... */ - 0x3e, 0x00, /* ..*****..... */ - 0x77, 0x00, /* .***.***.... */ - 0x63, 0x60, /* .**...**.**. */ - 0x61, 0xe0, /* .**....****. */ - 0x61, 0xc0, /* .**....***.. */ - 0x61, 0x80, /* .**....**... */ - 0x3f, 0xe0, /* ..*********. */ - 0x1e, 0x60, /* ...****..**. */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 39 0x27 ''' */ - 0x00, 0x00, /* ............ */ - 0x0c, 0x00, /* ....**...... */ - 0x1e, 0x00, /* ...****..... */ - 0x1e, 0x00, /* ...****..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x0c, 0x00, /* ....**...... */ - 0x18, 0x00, /* ...**....... */ - 0x10, 0x00, /* ...*........ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 40 0x28 '(' */ - 0x00, 0x00, /* ............ */ - 0x01, 0x80, /* .......**... */ - 0x03, 0x00, /* ......**.... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x0c, 0x00, /* ....**...... */ - 0x0c, 0x00, /* ....**...... */ - 0x0c, 0x00, /* ....**...... */ - 0x0c, 0x00, /* ....**...... */ - 0x0c, 0x00, /* ....**...... */ - 0x0c, 0x00, /* ....**...... */ - 0x0c, 0x00, /* ....**...... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x03, 0x00, /* ......**.... */ - 0x01, 0x80, /* .......**... */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 41 0x29 ')' */ - 0x00, 0x00, /* ............ */ - 0x18, 0x00, /* ...**....... */ - 0x0c, 0x00, /* ....**...... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x03, 0x00, /* ......**.... */ - 0x03, 0x00, /* ......**.... */ - 0x03, 0x00, /* ......**.... */ - 0x03, 0x00, /* ......**.... */ - 0x03, 0x00, /* ......**.... */ - 0x03, 0x00, /* ......**.... */ - 0x03, 0x00, /* ......**.... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x0c, 0x00, /* ....**...... */ - 0x18, 0x00, /* ...**....... */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 42 0x2a '*' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x0f, 0x00, /* ....****.... */ - 0x06, 0x00, /* .....**..... */ - 0x66, 0x60, /* .**..**..**. */ - 0x76, 0xe0, /* .***.**.***. */ - 0x19, 0x80, /* ...**..**... */ - 0x00, 0x00, /* ............ */ - 0x19, 0x80, /* ...**..**... */ - 0x76, 0xe0, /* .***.**.***. */ - 0x66, 0x60, /* .**..**..**. */ - 0x06, 0x00, /* .....**..... */ - 0x0f, 0x00, /* ....****.... */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 43 0x2b '+' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x7f, 0xe0, /* .**********. */ - 0x7f, 0xe0, /* .**********. */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 44 0x2c ',' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x0c, 0x00, /* ....**...... */ - 0x1e, 0x00, /* ...****..... */ - 0x1e, 0x00, /* ...****..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x0c, 0x00, /* ....**...... */ - 0x18, 0x00, /* ...**....... */ - 0x10, 0x00, /* ...*........ */ - 0x00, 0x00, /* ............ */ - - /* 45 0x2d '-' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x7f, 0xe0, /* .**********. */ - 0x7f, 0xe0, /* .**********. */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 46 0x2e '.' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x0c, 0x00, /* ....**...... */ - 0x1e, 0x00, /* ...****..... */ - 0x1e, 0x00, /* ...****..... */ - 0x0c, 0x00, /* ....**...... */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 47 0x2f '/' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x60, /* .........**. */ - 0x00, 0xc0, /* ........**.. */ - 0x00, 0xc0, /* ........**.. */ - 0x01, 0x80, /* .......**... */ - 0x01, 0x80, /* .......**... */ - 0x03, 0x00, /* ......**.... */ - 0x03, 0x00, /* ......**.... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x0c, 0x00, /* ....**...... */ - 0x0c, 0x00, /* ....**...... */ - 0x18, 0x00, /* ...**....... */ - 0x18, 0x00, /* ...**....... */ - 0x30, 0x00, /* ..**........ */ - 0x30, 0x00, /* ..**........ */ - 0x60, 0x00, /* .**......... */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 48 0x30 '0' */ - 0x00, 0x00, /* ............ */ - 0x07, 0x00, /* .....***.... */ - 0x0f, 0x80, /* ....*****... */ - 0x11, 0x80, /* ...*...**... */ - 0x10, 0xc0, /* ...*....**.. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x30, 0x80, /* ..**....*... */ - 0x18, 0x80, /* ...**...*... */ - 0x1f, 0x00, /* ...*****.... */ - 0x0e, 0x00, /* ....***..... */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 49 0x31 '1' */ - 0x00, 0x00, /* ............ */ - 0x02, 0x00, /* ......*..... */ - 0x06, 0x00, /* .....**..... */ - 0x0e, 0x00, /* ....***..... */ - 0x1e, 0x00, /* ...****..... */ - 0x36, 0x00, /* ..**.**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x3f, 0xc0, /* ..********.. */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 50 0x32 '2' */ - 0x00, 0x00, /* ............ */ - 0x1f, 0x00, /* ...*****.... */ - 0x3f, 0x80, /* ..*******... */ - 0x61, 0xc0, /* .**....***.. */ - 0x40, 0xc0, /* .*......**.. */ - 0x00, 0xc0, /* ........**.. */ - 0x00, 0xc0, /* ........**.. */ - 0x00, 0xc0, /* ........**.. */ - 0x01, 0x80, /* .......**... */ - 0x03, 0x00, /* ......**.... */ - 0x06, 0x00, /* .....**..... */ - 0x0c, 0x00, /* ....**...... */ - 0x18, 0x00, /* ...**....... */ - 0x30, 0x20, /* ..**......*. */ - 0x7f, 0xe0, /* .**********. */ - 0x7f, 0xe0, /* .**********. */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 51 0x33 '3' */ - 0x00, 0x00, /* ............ */ - 0x0f, 0x80, /* ....*****... */ - 0x1f, 0xc0, /* ...*******.. */ - 0x20, 0xe0, /* ..*.....***. */ - 0x40, 0x60, /* .*.......**. */ - 0x00, 0x60, /* .........**. */ - 0x00, 0xe0, /* ........***. */ - 0x07, 0xc0, /* .....*****.. */ - 0x0f, 0xc0, /* ....******.. */ - 0x00, 0xe0, /* ........***. */ - 0x00, 0x60, /* .........**. */ - 0x00, 0x60, /* .........**. */ - 0x40, 0x60, /* .*.......**. */ - 0x60, 0x40, /* .**......*.. */ - 0x3f, 0x80, /* ..*******... */ - 0x1f, 0x00, /* ...*****.... */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 52 0x34 '4' */ - 0x00, 0x00, /* ............ */ - 0x01, 0x80, /* .......**... */ - 0x03, 0x80, /* ......***... */ - 0x03, 0x80, /* ......***... */ - 0x05, 0x80, /* .....*.**... */ - 0x05, 0x80, /* .....*.**... */ - 0x09, 0x80, /* ....*..**... */ - 0x09, 0x80, /* ....*..**... */ - 0x11, 0x80, /* ...*...**... */ - 0x11, 0x80, /* ...*...**... */ - 0x21, 0x80, /* ..*....**... */ - 0x3f, 0xe0, /* ..*********. */ - 0x7f, 0xe0, /* .**********. */ - 0x01, 0x80, /* .......**... */ - 0x01, 0x80, /* .......**... */ - 0x01, 0x80, /* .......**... */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 53 0x35 '5' */ - 0x00, 0x00, /* ............ */ - 0x0f, 0xc0, /* ....******.. */ - 0x0f, 0xc0, /* ....******.. */ - 0x10, 0x00, /* ...*........ */ - 0x10, 0x00, /* ...*........ */ - 0x20, 0x00, /* ..*......... */ - 0x3f, 0x80, /* ..*******... */ - 0x31, 0xc0, /* ..**...***.. */ - 0x00, 0xe0, /* ........***. */ - 0x00, 0x60, /* .........**. */ - 0x00, 0x60, /* .........**. */ - 0x00, 0x60, /* .........**. */ - 0x40, 0x60, /* .*.......**. */ - 0x60, 0x60, /* .**......**. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x1f, 0x80, /* ...******... */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 54 0x36 '6' */ - 0x00, 0x00, /* ............ */ - 0x07, 0x00, /* .....***.... */ - 0x0c, 0x00, /* ....**...... */ - 0x18, 0x00, /* ...**....... */ - 0x30, 0x00, /* ..**........ */ - 0x30, 0x00, /* ..**........ */ - 0x60, 0x00, /* .**......... */ - 0x67, 0x80, /* .**..****... */ - 0x6f, 0xc0, /* .**.******.. */ - 0x70, 0xe0, /* .***....***. */ - 0x60, 0x60, /* .**......**. */ - 0x60, 0x60, /* .**......**. */ - 0x60, 0x60, /* .**......**. */ - 0x70, 0x40, /* .***.....*.. */ - 0x3f, 0x80, /* ..*******... */ - 0x1f, 0x00, /* ...*****.... */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 55 0x37 '7' */ - 0x00, 0x00, /* ............ */ - 0x1f, 0xe0, /* ...********. */ - 0x3f, 0xe0, /* ..*********. */ - 0x60, 0x40, /* .**......*.. */ - 0x00, 0x40, /* .........*.. */ - 0x00, 0xc0, /* ........**.. */ - 0x00, 0x80, /* ........*... */ - 0x00, 0x80, /* ........*... */ - 0x01, 0x80, /* .......**... */ - 0x01, 0x00, /* .......*.... */ - 0x01, 0x00, /* .......*.... */ - 0x03, 0x00, /* ......**.... */ - 0x02, 0x00, /* ......*..... */ - 0x02, 0x00, /* ......*..... */ - 0x06, 0x00, /* .....**..... */ - 0x04, 0x00, /* .....*...... */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 56 0x38 '8' */ - 0x00, 0x00, /* ............ */ - 0x0f, 0x00, /* ....****.... */ - 0x11, 0x80, /* ...*...**... */ - 0x30, 0xc0, /* ..**....**.. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x18, 0x80, /* ...**...*... */ - 0x0d, 0x00, /* ....**.*.... */ - 0x06, 0x00, /* .....**..... */ - 0x0b, 0x00, /* ....*.**.... */ - 0x11, 0x80, /* ...*...**... */ - 0x30, 0xc0, /* ..**....**.. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x18, 0x80, /* ...**...*... */ - 0x0f, 0x00, /* ....****.... */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 57 0x39 '9' */ - 0x00, 0x00, /* ............ */ - 0x0f, 0x80, /* ....*****... */ - 0x11, 0xc0, /* ...*...***.. */ - 0x20, 0xe0, /* ..*.....***. */ - 0x60, 0x60, /* .**......**. */ - 0x60, 0x60, /* .**......**. */ - 0x60, 0x60, /* .**......**. */ - 0x70, 0xe0, /* .***....***. */ - 0x3f, 0x60, /* ..******.**. */ - 0x1e, 0x60, /* ...****..**. */ - 0x00, 0x60, /* .........**. */ - 0x00, 0xc0, /* ........**.. */ - 0x00, 0xc0, /* ........**.. */ - 0x01, 0x80, /* .......**... */ - 0x07, 0x00, /* .....***.... */ - 0x3c, 0x00, /* ..****...... */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 58 0x3a ':' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x0c, 0x00, /* ....**...... */ - 0x1e, 0x00, /* ...****..... */ - 0x1e, 0x00, /* ...****..... */ - 0x0c, 0x00, /* ....**...... */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x0c, 0x00, /* ....**...... */ - 0x1e, 0x00, /* ...****..... */ - 0x1e, 0x00, /* ...****..... */ - 0x0c, 0x00, /* ....**...... */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 59 0x3b ';' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x0c, 0x00, /* ....**...... */ - 0x1e, 0x00, /* ...****..... */ - 0x1e, 0x00, /* ...****..... */ - 0x0c, 0x00, /* ....**...... */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x0c, 0x00, /* ....**...... */ - 0x1e, 0x00, /* ...****..... */ - 0x1e, 0x00, /* ...****..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x0c, 0x00, /* ....**...... */ - 0x18, 0x00, /* ...**....... */ - 0x10, 0x00, /* ...*........ */ - 0x00, 0x00, /* ............ */ - - /* 60 0x3c '<' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x60, /* .........**. */ - 0x01, 0xc0, /* .......***.. */ - 0x07, 0x00, /* .....***.... */ - 0x1c, 0x00, /* ...***...... */ - 0x70, 0x00, /* .***........ */ - 0x70, 0x00, /* .***........ */ - 0x1c, 0x00, /* ...***...... */ - 0x07, 0x00, /* .....***.... */ - 0x01, 0xc0, /* .......***.. */ - 0x00, 0x60, /* .........**. */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 61 0x3d '=' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x7f, 0xe0, /* .**********. */ - 0x7f, 0xe0, /* .**********. */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x7f, 0xe0, /* .**********. */ - 0x7f, 0xe0, /* .**********. */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 62 0x3e '>' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x60, 0x00, /* .**......... */ - 0x38, 0x00, /* ..***....... */ - 0x0e, 0x00, /* ....***..... */ - 0x03, 0x80, /* ......***... */ - 0x00, 0xe0, /* ........***. */ - 0x00, 0xe0, /* ........***. */ - 0x03, 0x80, /* ......***... */ - 0x0e, 0x00, /* ....***..... */ - 0x38, 0x00, /* ..***....... */ - 0x60, 0x00, /* .**......... */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 63 0x3f '?' */ - 0x00, 0x00, /* ............ */ - 0x0f, 0x00, /* ....****.... */ - 0x1f, 0x80, /* ...******... */ - 0x39, 0xc0, /* ..***..***.. */ - 0x20, 0xc0, /* ..*.....**.. */ - 0x00, 0xc0, /* ........**.. */ - 0x00, 0xc0, /* ........**.. */ - 0x01, 0x80, /* .......**... */ - 0x03, 0x00, /* ......**.... */ - 0x06, 0x00, /* .....**..... */ - 0x0c, 0x00, /* ....**...... */ - 0x0c, 0x00, /* ....**...... */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x0c, 0x00, /* ....**...... */ - 0x0c, 0x00, /* ....**...... */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 64 0x40 '@' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x0f, 0x80, /* ....*****... */ - 0x3f, 0xc0, /* ..********.. */ - 0x30, 0x60, /* ..**.....**. */ - 0x60, 0x60, /* .**......**. */ - 0x67, 0x20, /* .**..***..*. */ - 0x6f, 0xa0, /* .**.*****.*. */ - 0x6c, 0xa0, /* .**.**..*.*. */ - 0x6c, 0xa0, /* .**.**..*.*. */ - 0x67, 0xe0, /* .**..******. */ - 0x60, 0x00, /* .**......... */ - 0x30, 0x00, /* ..**........ */ - 0x3f, 0xe0, /* ..*********. */ - 0x0f, 0xe0, /* ....*******. */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 65 0x41 'A' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x0b, 0x00, /* ....*.**.... */ - 0x0b, 0x00, /* ....*.**.... */ - 0x09, 0x00, /* ....*..*.... */ - 0x11, 0x80, /* ...*...**... */ - 0x11, 0x80, /* ...*...**... */ - 0x10, 0x80, /* ...*....*... */ - 0x3f, 0xc0, /* ..********.. */ - 0x20, 0xc0, /* ..*.....**.. */ - 0x20, 0x40, /* ..*......*.. */ - 0x40, 0x60, /* .*.......**. */ - 0x40, 0x60, /* .*.......**. */ - 0xe0, 0xf0, /* ***.....**** */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 66 0x42 'B' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0xff, 0x00, /* ********.... */ - 0x60, 0x80, /* .**.....*... */ - 0x60, 0xc0, /* .**.....**.. */ - 0x60, 0xc0, /* .**.....**.. */ - 0x60, 0xc0, /* .**.....**.. */ - 0x61, 0x80, /* .**....**... */ - 0x7f, 0x80, /* .********... */ - 0x60, 0xc0, /* .**.....**.. */ - 0x60, 0x60, /* .**......**. */ - 0x60, 0x60, /* .**......**. */ - 0x60, 0x60, /* .**......**. */ - 0x60, 0x60, /* .**......**. */ - 0x60, 0xc0, /* .**.....**.. */ - 0xff, 0x80, /* *********... */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 67 0x43 'C' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x0f, 0xc0, /* ....******.. */ - 0x10, 0x60, /* ...*.....**. */ - 0x20, 0x20, /* ..*.......*. */ - 0x20, 0x00, /* ..*......... */ - 0x60, 0x00, /* .**......... */ - 0x60, 0x00, /* .**......... */ - 0x60, 0x00, /* .**......... */ - 0x60, 0x00, /* .**......... */ - 0x60, 0x00, /* .**......... */ - 0x60, 0x00, /* .**......... */ - 0x20, 0x00, /* ..*......... */ - 0x30, 0x20, /* ..**......*. */ - 0x18, 0x40, /* ...**....*.. */ - 0x0f, 0x80, /* ....*****... */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 68 0x44 'D' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0xff, 0x00, /* ********.... */ - 0x61, 0xc0, /* .**....***.. */ - 0x60, 0xc0, /* .**.....**.. */ - 0x60, 0x60, /* .**......**. */ - 0x60, 0x60, /* .**......**. */ - 0x60, 0x60, /* .**......**. */ - 0x60, 0x60, /* .**......**. */ - 0x60, 0x60, /* .**......**. */ - 0x60, 0x60, /* .**......**. */ - 0x60, 0x60, /* .**......**. */ - 0x60, 0x60, /* .**......**. */ - 0x60, 0x40, /* .**......*.. */ - 0x61, 0x80, /* .**....**... */ - 0xfe, 0x00, /* *******..... */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 69 0x45 'E' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x7f, 0xc0, /* .*********.. */ - 0x30, 0x40, /* ..**.....*.. */ - 0x30, 0x40, /* ..**.....*.. */ - 0x30, 0x00, /* ..**........ */ - 0x30, 0x00, /* ..**........ */ - 0x30, 0x80, /* ..**....*... */ - 0x3f, 0x80, /* ..*******... */ - 0x30, 0x80, /* ..**....*... */ - 0x30, 0x00, /* ..**........ */ - 0x30, 0x00, /* ..**........ */ - 0x30, 0x00, /* ..**........ */ - 0x30, 0x20, /* ..**......*. */ - 0x30, 0x20, /* ..**......*. */ - 0x7f, 0xe0, /* .**********. */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 70 0x46 'F' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x7f, 0xc0, /* .*********.. */ - 0x30, 0x40, /* ..**.....*.. */ - 0x30, 0x40, /* ..**.....*.. */ - 0x30, 0x00, /* ..**........ */ - 0x30, 0x00, /* ..**........ */ - 0x30, 0x80, /* ..**....*... */ - 0x3f, 0x80, /* ..*******... */ - 0x30, 0x80, /* ..**....*... */ - 0x30, 0x00, /* ..**........ */ - 0x30, 0x00, /* ..**........ */ - 0x30, 0x00, /* ..**........ */ - 0x30, 0x00, /* ..**........ */ - 0x30, 0x00, /* ..**........ */ - 0x78, 0x00, /* .****....... */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 71 0x47 'G' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x0f, 0xc0, /* ....******.. */ - 0x10, 0x60, /* ...*.....**. */ - 0x20, 0x20, /* ..*.......*. */ - 0x20, 0x00, /* ..*......... */ - 0x60, 0x00, /* .**......... */ - 0x60, 0x00, /* .**......... */ - 0x60, 0x00, /* .**......... */ - 0x60, 0x00, /* .**......... */ - 0x61, 0xf0, /* .**....***** */ - 0x60, 0x60, /* .**......**. */ - 0x20, 0x60, /* ..*......**. */ - 0x30, 0x60, /* ..**.....**. */ - 0x18, 0x60, /* ...**....**. */ - 0x0f, 0x80, /* ....*****... */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 72 0x48 'H' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0xf0, 0xf0, /* ****....**** */ - 0x60, 0x60, /* .**......**. */ - 0x60, 0x60, /* .**......**. */ - 0x60, 0x60, /* .**......**. */ - 0x60, 0x60, /* .**......**. */ - 0x60, 0x60, /* .**......**. */ - 0x7f, 0xe0, /* .**********. */ - 0x60, 0x60, /* .**......**. */ - 0x60, 0x60, /* .**......**. */ - 0x60, 0x60, /* .**......**. */ - 0x60, 0x60, /* .**......**. */ - 0x60, 0x60, /* .**......**. */ - 0x60, 0x60, /* .**......**. */ - 0xf0, 0xf0, /* ****....**** */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 73 0x49 'I' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x1f, 0x80, /* ...******... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x1f, 0x80, /* ...******... */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 74 0x4a 'J' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x1f, 0x80, /* ...******... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x04, 0x00, /* .....*...... */ - 0x38, 0x00, /* ..***....... */ - 0x30, 0x00, /* ..**........ */ - 0x00, 0x00, /* ............ */ - - /* 75 0x4b 'K' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0xf0, 0xe0, /* ****....***. */ - 0x61, 0x80, /* .**....**... */ - 0x63, 0x00, /* .**...**.... */ - 0x66, 0x00, /* .**..**..... */ - 0x6c, 0x00, /* .**.**...... */ - 0x78, 0x00, /* .****....... */ - 0x78, 0x00, /* .****....... */ - 0x7c, 0x00, /* .*****...... */ - 0x6e, 0x00, /* .**.***..... */ - 0x67, 0x00, /* .**..***.... */ - 0x63, 0x80, /* .**...***... */ - 0x61, 0xc0, /* .**....***.. */ - 0x60, 0xe0, /* .**.....***. */ - 0xf0, 0x70, /* ****.....*** */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 76 0x4c 'L' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x78, 0x00, /* .****....... */ - 0x30, 0x00, /* ..**........ */ - 0x30, 0x00, /* ..**........ */ - 0x30, 0x00, /* ..**........ */ - 0x30, 0x00, /* ..**........ */ - 0x30, 0x00, /* ..**........ */ - 0x30, 0x00, /* ..**........ */ - 0x30, 0x00, /* ..**........ */ - 0x30, 0x00, /* ..**........ */ - 0x30, 0x00, /* ..**........ */ - 0x30, 0x00, /* ..**........ */ - 0x30, 0x20, /* ..**......*. */ - 0x30, 0x20, /* ..**......*. */ - 0x7f, 0xe0, /* .**********. */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 77 0x4d 'M' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0xe0, 0x70, /* ***......*** */ - 0x60, 0xe0, /* .**.....***. */ - 0x70, 0xe0, /* .***....***. */ - 0x70, 0xe0, /* .***....***. */ - 0x70, 0xe0, /* .***....***. */ - 0x59, 0x60, /* .*.**..*.**. */ - 0x59, 0x60, /* .*.**..*.**. */ - 0x59, 0x60, /* .*.**..*.**. */ - 0x4d, 0x60, /* .*..**.*.**. */ - 0x4e, 0x60, /* .*..***..**. */ - 0x4e, 0x60, /* .*..***..**. */ - 0x44, 0x60, /* .*...*...**. */ - 0x44, 0x60, /* .*...*...**. */ - 0xe4, 0xf0, /* ***..*..**** */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 78 0x4e 'N' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0xc0, 0x70, /* **.......*** */ - 0x60, 0x20, /* .**.......*. */ - 0x70, 0x20, /* .***......*. */ - 0x78, 0x20, /* .****.....*. */ - 0x58, 0x20, /* .*.**.....*. */ - 0x4c, 0x20, /* .*..**....*. */ - 0x46, 0x20, /* .*...**...*. */ - 0x47, 0x20, /* .*...***..*. */ - 0x43, 0x20, /* .*....**..*. */ - 0x41, 0xa0, /* .*.....**.*. */ - 0x40, 0xe0, /* .*......***. */ - 0x40, 0xe0, /* .*......***. */ - 0x40, 0x60, /* .*.......**. */ - 0xe0, 0x30, /* ***.......** */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 79 0x4f 'O' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x0f, 0x00, /* ....****.... */ - 0x11, 0xc0, /* ...*...***.. */ - 0x20, 0xc0, /* ..*.....**.. */ - 0x20, 0x60, /* ..*......**. */ - 0x60, 0x60, /* .**......**. */ - 0x60, 0x60, /* .**......**. */ - 0x60, 0x60, /* .**......**. */ - 0x60, 0x60, /* .**......**. */ - 0x60, 0x60, /* .**......**. */ - 0x60, 0x60, /* .**......**. */ - 0x20, 0x40, /* ..*......*.. */ - 0x30, 0x40, /* ..**.....*.. */ - 0x18, 0x80, /* ...**...*... */ - 0x0f, 0x00, /* ....****.... */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 80 0x50 'P' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x7f, 0x80, /* .********... */ - 0x30, 0xc0, /* ..**....**.. */ - 0x30, 0x60, /* ..**.....**. */ - 0x30, 0x60, /* ..**.....**. */ - 0x30, 0x60, /* ..**.....**. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x37, 0x80, /* ..**.****... */ - 0x30, 0x00, /* ..**........ */ - 0x30, 0x00, /* ..**........ */ - 0x30, 0x00, /* ..**........ */ - 0x30, 0x00, /* ..**........ */ - 0x30, 0x00, /* ..**........ */ - 0x30, 0x00, /* ..**........ */ - 0x78, 0x00, /* .****....... */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 81 0x51 'Q' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x0f, 0x00, /* ....****.... */ - 0x11, 0xc0, /* ...*...***.. */ - 0x20, 0xc0, /* ..*.....**.. */ - 0x20, 0x60, /* ..*......**. */ - 0x60, 0x60, /* .**......**. */ - 0x60, 0x60, /* .**......**. */ - 0x60, 0x60, /* .**......**. */ - 0x60, 0x60, /* .**......**. */ - 0x60, 0x60, /* .**......**. */ - 0x60, 0x60, /* .**......**. */ - 0x30, 0x40, /* ..**.....*.. */ - 0x38, 0x40, /* ..***....*.. */ - 0x1f, 0x80, /* ...******... */ - 0x0e, 0x00, /* ....***..... */ - 0x1f, 0x00, /* ...*****.... */ - 0x23, 0x90, /* ..*...***..* */ - 0x01, 0xe0, /* .......****. */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 82 0x52 'R' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0xff, 0x00, /* ********.... */ - 0x61, 0x80, /* .**....**... */ - 0x60, 0xc0, /* .**.....**.. */ - 0x60, 0xc0, /* .**.....**.. */ - 0x60, 0xc0, /* .**.....**.. */ - 0x60, 0x80, /* .**.....*... */ - 0x7f, 0x00, /* .*******.... */ - 0x7c, 0x00, /* .*****...... */ - 0x6e, 0x00, /* .**.***..... */ - 0x67, 0x00, /* .**..***.... */ - 0x63, 0x80, /* .**...***... */ - 0x61, 0xc0, /* .**....***.. */ - 0x60, 0xe0, /* .**.....***. */ - 0xf0, 0x70, /* ****.....*** */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 83 0x53 'S' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x1f, 0xe0, /* ...********. */ - 0x30, 0x60, /* ..**.....**. */ - 0x60, 0x20, /* .**.......*. */ - 0x60, 0x20, /* .**.......*. */ - 0x70, 0x00, /* .***........ */ - 0x3c, 0x00, /* ..****...... */ - 0x1e, 0x00, /* ...****..... */ - 0x07, 0x80, /* .....****... */ - 0x01, 0xc0, /* .......***.. */ - 0x00, 0xe0, /* ........***. */ - 0x40, 0x60, /* .*.......**. */ - 0x40, 0x60, /* .*.......**. */ - 0x60, 0xc0, /* .**.....**.. */ - 0x7f, 0x80, /* .********... */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 84 0x54 'T' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x7f, 0xe0, /* .**********. */ - 0x46, 0x20, /* .*...**...*. */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x1f, 0x80, /* ...******... */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 85 0x55 'U' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0xf0, 0x70, /* ****.....*** */ - 0x60, 0x20, /* .**.......*. */ - 0x60, 0x20, /* .**.......*. */ - 0x60, 0x20, /* .**.......*. */ - 0x60, 0x20, /* .**.......*. */ - 0x60, 0x20, /* .**.......*. */ - 0x60, 0x20, /* .**.......*. */ - 0x60, 0x20, /* .**.......*. */ - 0x60, 0x20, /* .**.......*. */ - 0x60, 0x20, /* .**.......*. */ - 0x60, 0x20, /* .**.......*. */ - 0x70, 0x40, /* .***.....*.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x1f, 0x80, /* ...******... */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 86 0x56 'V' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0xe0, 0xe0, /* ***.....***. */ - 0x60, 0x40, /* .**......*.. */ - 0x30, 0x80, /* ..**....*... */ - 0x30, 0x80, /* ..**....*... */ - 0x30, 0x80, /* ..**....*... */ - 0x19, 0x00, /* ...**..*.... */ - 0x19, 0x00, /* ...**..*.... */ - 0x19, 0x00, /* ...**..*.... */ - 0x0a, 0x00, /* ....*.*..... */ - 0x0e, 0x00, /* ....***..... */ - 0x0e, 0x00, /* ....***..... */ - 0x04, 0x00, /* .....*...... */ - 0x04, 0x00, /* .....*...... */ - 0x04, 0x00, /* .....*...... */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 87 0x57 'W' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0xfe, 0xf0, /* *******.**** */ - 0x66, 0x20, /* .**..**...*. */ - 0x66, 0x20, /* .**..**...*. */ - 0x66, 0x20, /* .**..**...*. */ - 0x76, 0x20, /* .***.**...*. */ - 0x77, 0x40, /* .***.***.*.. */ - 0x33, 0x40, /* ..**..**.*.. */ - 0x37, 0x40, /* ..**.***.*.. */ - 0x3b, 0xc0, /* ..***.****.. */ - 0x3b, 0x80, /* ..***.***... */ - 0x19, 0x80, /* ...**..**... */ - 0x19, 0x80, /* ...**..**... */ - 0x19, 0x80, /* ...**..**... */ - 0x19, 0x80, /* ...**..**... */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 88 0x58 'X' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0xf0, 0x70, /* ****.....*** */ - 0x60, 0x20, /* .**.......*. */ - 0x30, 0x40, /* ..**.....*.. */ - 0x38, 0x80, /* ..***...*... */ - 0x18, 0x80, /* ...**...*... */ - 0x0d, 0x00, /* ....**.*.... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x0b, 0x00, /* ....*.**.... */ - 0x11, 0x80, /* ...*...**... */ - 0x11, 0xc0, /* ...*...***.. */ - 0x20, 0xc0, /* ..*.....**.. */ - 0x40, 0x60, /* .*.......**. */ - 0xe0, 0xf0, /* ***.....**** */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 89 0x59 'Y' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0xf0, 0x70, /* ****.....*** */ - 0x60, 0x20, /* .**.......*. */ - 0x30, 0x40, /* ..**.....*.. */ - 0x18, 0x80, /* ...**...*... */ - 0x18, 0x80, /* ...**...*... */ - 0x0d, 0x00, /* ....**.*.... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x0f, 0x00, /* ....****.... */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 90 0x5a 'Z' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x3f, 0xe0, /* ..*********. */ - 0x20, 0xc0, /* ..*.....**.. */ - 0x00, 0xc0, /* ........**.. */ - 0x01, 0x80, /* .......**... */ - 0x01, 0x80, /* .......**... */ - 0x03, 0x00, /* ......**.... */ - 0x03, 0x00, /* ......**.... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x0c, 0x00, /* ....**...... */ - 0x0c, 0x00, /* ....**...... */ - 0x18, 0x00, /* ...**....... */ - 0x18, 0x20, /* ...**.....*. */ - 0x3f, 0xe0, /* ..*********. */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 91 0x5b '[' */ - 0x00, 0x00, /* ............ */ - 0x0f, 0x80, /* ....*****... */ - 0x0f, 0x80, /* ....*****... */ - 0x0c, 0x00, /* ....**...... */ - 0x0c, 0x00, /* ....**...... */ - 0x0c, 0x00, /* ....**...... */ - 0x0c, 0x00, /* ....**...... */ - 0x0c, 0x00, /* ....**...... */ - 0x0c, 0x00, /* ....**...... */ - 0x0c, 0x00, /* ....**...... */ - 0x0c, 0x00, /* ....**...... */ - 0x0c, 0x00, /* ....**...... */ - 0x0c, 0x00, /* ....**...... */ - 0x0c, 0x00, /* ....**...... */ - 0x0f, 0x80, /* ....*****... */ - 0x0f, 0x80, /* ....*****... */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 92 0x5c '\' */ - 0x00, 0x00, /* ............ */ - 0x60, 0x00, /* .**......... */ - 0x30, 0x00, /* ..**........ */ - 0x30, 0x00, /* ..**........ */ - 0x18, 0x00, /* ...**....... */ - 0x18, 0x00, /* ...**....... */ - 0x0c, 0x00, /* ....**...... */ - 0x0c, 0x00, /* ....**...... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x03, 0x00, /* ......**.... */ - 0x03, 0x00, /* ......**.... */ - 0x01, 0x80, /* .......**... */ - 0x01, 0x80, /* .......**... */ - 0x00, 0xc0, /* ........**.. */ - 0x00, 0xc0, /* ........**.. */ - 0x00, 0x60, /* .........**. */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 93 0x5d ']' */ - 0x00, 0x00, /* ............ */ - 0x1f, 0x00, /* ...*****.... */ - 0x1f, 0x00, /* ...*****.... */ - 0x03, 0x00, /* ......**.... */ - 0x03, 0x00, /* ......**.... */ - 0x03, 0x00, /* ......**.... */ - 0x03, 0x00, /* ......**.... */ - 0x03, 0x00, /* ......**.... */ - 0x03, 0x00, /* ......**.... */ - 0x03, 0x00, /* ......**.... */ - 0x03, 0x00, /* ......**.... */ - 0x03, 0x00, /* ......**.... */ - 0x03, 0x00, /* ......**.... */ - 0x03, 0x00, /* ......**.... */ - 0x1f, 0x00, /* ...*****.... */ - 0x1f, 0x00, /* ...*****.... */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 94 0x5e '^' */ - 0x00, 0x00, /* ............ */ - 0x04, 0x00, /* .....*...... */ - 0x0e, 0x00, /* ....***..... */ - 0x1b, 0x00, /* ...**.**.... */ - 0x31, 0x80, /* ..**...**... */ - 0x60, 0xc0, /* .**.....**.. */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 95 0x5f '_' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0xff, 0xf0, /* ************ */ - 0xff, 0xf0, /* ************ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 96 0x60 '`' */ - 0x00, 0x00, /* ............ */ - 0x01, 0x00, /* .......*.... */ - 0x03, 0x00, /* ......**.... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x07, 0x80, /* .....****... */ - 0x07, 0x80, /* .....****... */ - 0x03, 0x00, /* ......**.... */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 97 0x61 'a' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x0f, 0x80, /* ....*****... */ - 0x18, 0xc0, /* ...**...**.. */ - 0x10, 0xc0, /* ...*....**.. */ - 0x03, 0xc0, /* ......****.. */ - 0x1c, 0xc0, /* ...***..**.. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x39, 0xc0, /* ..***..***.. */ - 0x1e, 0xe0, /* ...****.***. */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 98 0x62 'b' */ - 0x00, 0x00, /* ............ */ - 0x20, 0x00, /* ..*......... */ - 0x60, 0x00, /* .**......... */ - 0xe0, 0x00, /* ***......... */ - 0x60, 0x00, /* .**......... */ - 0x60, 0x00, /* .**......... */ - 0x67, 0x80, /* .**..****... */ - 0x6f, 0xc0, /* .**.******.. */ - 0x70, 0xe0, /* .***....***. */ - 0x60, 0x60, /* .**......**. */ - 0x60, 0x60, /* .**......**. */ - 0x60, 0x60, /* .**......**. */ - 0x60, 0x60, /* .**......**. */ - 0x70, 0x60, /* .***.....**. */ - 0x78, 0xc0, /* .****...**.. */ - 0x4f, 0x80, /* .*..*****... */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 99 0x63 'c' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x1f, 0x80, /* ...******... */ - 0x31, 0xc0, /* ..**...***.. */ - 0x20, 0xc0, /* ..*.....**.. */ - 0x60, 0x00, /* .**......... */ - 0x60, 0x00, /* .**......... */ - 0x60, 0x00, /* .**......... */ - 0x60, 0x00, /* .**......... */ - 0x70, 0x40, /* .***.....*.. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x1f, 0x80, /* ...******... */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 100 0x64 'd' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x60, /* .........**. */ - 0x00, 0xe0, /* ........***. */ - 0x00, 0x60, /* .........**. */ - 0x00, 0x60, /* .........**. */ - 0x00, 0x60, /* .........**. */ - 0x0f, 0x60, /* ....****.**. */ - 0x31, 0xe0, /* ..**...****. */ - 0x20, 0xe0, /* ..*.....***. */ - 0x60, 0x60, /* .**......**. */ - 0x60, 0x60, /* .**......**. */ - 0x60, 0x60, /* .**......**. */ - 0x60, 0x60, /* .**......**. */ - 0x70, 0xe0, /* .***....***. */ - 0x39, 0x60, /* ..***..*.**. */ - 0x1e, 0x70, /* ...****..*** */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 101 0x65 'e' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x0f, 0x00, /* ....****.... */ - 0x30, 0xc0, /* ..**....**.. */ - 0x60, 0x60, /* .**......**. */ - 0x60, 0x60, /* .**......**. */ - 0x7f, 0xe0, /* .**********. */ - 0x60, 0x00, /* .**......... */ - 0x60, 0x00, /* .**......... */ - 0x30, 0x00, /* ..**........ */ - 0x18, 0x60, /* ...**....**. */ - 0x0f, 0x80, /* ....*****... */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 102 0x66 'f' */ - 0x00, 0x00, /* ............ */ - 0x03, 0x80, /* ......***... */ - 0x04, 0xc0, /* .....*..**.. */ - 0x04, 0xc0, /* .....*..**.. */ - 0x0c, 0x00, /* ....**...... */ - 0x0c, 0x00, /* ....**...... */ - 0x0c, 0x00, /* ....**...... */ - 0x0c, 0x00, /* ....**...... */ - 0x3f, 0x80, /* ..*******... */ - 0x0c, 0x00, /* ....**...... */ - 0x0c, 0x00, /* ....**...... */ - 0x0c, 0x00, /* ....**...... */ - 0x0c, 0x00, /* ....**...... */ - 0x0c, 0x00, /* ....**...... */ - 0x0c, 0x00, /* ....**...... */ - 0x1e, 0x00, /* ...****..... */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 103 0x67 'g' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x1f, 0x20, /* ...*****..*. */ - 0x31, 0xe0, /* ..**...****. */ - 0x60, 0xc0, /* .**.....**.. */ - 0x60, 0xc0, /* .**.....**.. */ - 0x60, 0xc0, /* .**.....**.. */ - 0x31, 0x80, /* ..**...**... */ - 0x3f, 0x00, /* ..******.... */ - 0x60, 0x00, /* .**......... */ - 0x7f, 0xc0, /* .*********.. */ - 0x3f, 0xe0, /* ..*********. */ - 0x20, 0x60, /* ..*......**. */ - 0x40, 0x20, /* .*........*. */ - 0x40, 0x20, /* .*........*. */ - 0x7f, 0xc0, /* .*********.. */ - 0x3f, 0x80, /* ..*******... */ - 0x00, 0x00, /* ............ */ - - /* 104 0x68 'h' */ - 0x00, 0x00, /* ............ */ - 0x10, 0x00, /* ...*........ */ - 0x30, 0x00, /* ..**........ */ - 0x70, 0x00, /* .***........ */ - 0x30, 0x00, /* ..**........ */ - 0x30, 0x00, /* ..**........ */ - 0x37, 0x80, /* ..**.****... */ - 0x39, 0xc0, /* ..***..***.. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x79, 0xe0, /* .****..****. */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 105 0x69 'i' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x1e, 0x00, /* ...****..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x1f, 0x80, /* ...******... */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 106 0x6a 'j' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0xc0, /* ........**.. */ - 0x00, 0xc0, /* ........**.. */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x03, 0xc0, /* ......****.. */ - 0x00, 0xc0, /* ........**.. */ - 0x00, 0xc0, /* ........**.. */ - 0x00, 0xc0, /* ........**.. */ - 0x00, 0xc0, /* ........**.. */ - 0x00, 0xc0, /* ........**.. */ - 0x00, 0xc0, /* ........**.. */ - 0x00, 0xc0, /* ........**.. */ - 0x00, 0xc0, /* ........**.. */ - 0x00, 0xc0, /* ........**.. */ - 0x20, 0xc0, /* ..*.....**.. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x38, 0x80, /* ..***...*... */ - 0x1f, 0x00, /* ...*****.... */ - 0x0e, 0x00, /* ....***..... */ - 0x00, 0x00, /* ............ */ - - /* 107 0x6b 'k' */ - 0x00, 0x00, /* ............ */ - 0x60, 0x00, /* .**......... */ - 0xe0, 0x00, /* ***......... */ - 0x60, 0x00, /* .**......... */ - 0x60, 0x00, /* .**......... */ - 0x60, 0x00, /* .**......... */ - 0x61, 0xc0, /* .**....***.. */ - 0x63, 0x00, /* .**...**.... */ - 0x66, 0x00, /* .**..**..... */ - 0x7c, 0x00, /* .*****...... */ - 0x78, 0x00, /* .****....... */ - 0x7c, 0x00, /* .*****...... */ - 0x6e, 0x00, /* .**.***..... */ - 0x67, 0x00, /* .**..***.... */ - 0x63, 0x80, /* .**...***... */ - 0xf1, 0xe0, /* ****...****. */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 108 0x6c 'l' */ - 0x00, 0x00, /* ............ */ - 0x1e, 0x00, /* ...****..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x1f, 0x80, /* ...******... */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 109 0x6d 'm' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0xdd, 0xc0, /* **.***.***.. */ - 0x6e, 0xe0, /* .**.***.***. */ - 0x66, 0x60, /* .**..**..**. */ - 0x66, 0x60, /* .**..**..**. */ - 0x66, 0x60, /* .**..**..**. */ - 0x66, 0x60, /* .**..**..**. */ - 0x66, 0x60, /* .**..**..**. */ - 0x66, 0x60, /* .**..**..**. */ - 0x66, 0x60, /* .**..**..**. */ - 0xef, 0x70, /* ***.****.*** */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 110 0x6e 'n' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x27, 0x80, /* ..*..****... */ - 0x79, 0xc0, /* .****..***.. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x79, 0xe0, /* .****..****. */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 111 0x6f 'o' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x0f, 0x80, /* ....*****... */ - 0x11, 0xc0, /* ...*...***.. */ - 0x20, 0xe0, /* ..*.....***. */ - 0x60, 0x60, /* .**......**. */ - 0x60, 0x60, /* .**......**. */ - 0x60, 0x60, /* .**......**. */ - 0x60, 0x60, /* .**......**. */ - 0x70, 0x40, /* .***.....*.. */ - 0x38, 0x80, /* ..***...*... */ - 0x1f, 0x00, /* ...*****.... */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 112 0x70 'p' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0xef, 0x80, /* ***.*****... */ - 0x71, 0xc0, /* .***...***.. */ - 0x60, 0xe0, /* .**.....***. */ - 0x60, 0x60, /* .**......**. */ - 0x60, 0x60, /* .**......**. */ - 0x60, 0x60, /* .**......**. */ - 0x60, 0x60, /* .**......**. */ - 0x60, 0x40, /* .**......*.. */ - 0x70, 0x80, /* .***....*... */ - 0x7f, 0x00, /* .*******.... */ - 0x60, 0x00, /* .**......... */ - 0x60, 0x00, /* .**......... */ - 0x60, 0x00, /* .**......... */ - 0x60, 0x00, /* .**......... */ - 0xf0, 0x00, /* ****........ */ - 0x00, 0x00, /* ............ */ - - /* 113 0x71 'q' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x0f, 0x20, /* ....****..*. */ - 0x11, 0xe0, /* ...*...****. */ - 0x20, 0xe0, /* ..*.....***. */ - 0x60, 0x60, /* .**......**. */ - 0x60, 0x60, /* .**......**. */ - 0x60, 0x60, /* .**......**. */ - 0x60, 0x60, /* .**......**. */ - 0x70, 0x60, /* .***.....**. */ - 0x38, 0xe0, /* ..***...***. */ - 0x1f, 0xe0, /* ...********. */ - 0x00, 0x60, /* .........**. */ - 0x00, 0x60, /* .........**. */ - 0x00, 0x60, /* .........**. */ - 0x00, 0x60, /* .........**. */ - 0x00, 0xf0, /* ........**** */ - 0x00, 0x00, /* ............ */ - - /* 114 0x72 'r' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x73, 0x80, /* .***..***... */ - 0x34, 0xc0, /* ..**.*..**.. */ - 0x38, 0xc0, /* ..***...**.. */ - 0x30, 0x00, /* ..**........ */ - 0x30, 0x00, /* ..**........ */ - 0x30, 0x00, /* ..**........ */ - 0x30, 0x00, /* ..**........ */ - 0x30, 0x00, /* ..**........ */ - 0x30, 0x00, /* ..**........ */ - 0x78, 0x00, /* .****....... */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 115 0x73 's' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x1f, 0xc0, /* ...*******.. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x30, 0x40, /* ..**.....*.. */ - 0x38, 0x00, /* ..***....... */ - 0x1e, 0x00, /* ...****..... */ - 0x07, 0x80, /* .....****... */ - 0x01, 0xc0, /* .......***.. */ - 0x20, 0xc0, /* ..*.....**.. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x3f, 0x80, /* ..*******... */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 116 0x74 't' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x04, 0x00, /* .....*...... */ - 0x04, 0x00, /* .....*...... */ - 0x0c, 0x00, /* ....**...... */ - 0x7f, 0xc0, /* .*********.. */ - 0x0c, 0x00, /* ....**...... */ - 0x0c, 0x00, /* ....**...... */ - 0x0c, 0x00, /* ....**...... */ - 0x0c, 0x00, /* ....**...... */ - 0x0c, 0x00, /* ....**...... */ - 0x0c, 0x00, /* ....**...... */ - 0x0c, 0x20, /* ....**....*. */ - 0x0e, 0x40, /* ....***..*.. */ - 0x07, 0x80, /* .....****... */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 117 0x75 'u' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x79, 0xe0, /* .****..****. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x39, 0xc0, /* ..***..***.. */ - 0x1e, 0x60, /* ...****..**. */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 118 0x76 'v' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0xf0, 0x70, /* ****.....*** */ - 0x60, 0x20, /* .**.......*. */ - 0x30, 0x40, /* ..**.....*.. */ - 0x30, 0x40, /* ..**.....*.. */ - 0x18, 0x80, /* ...**...*... */ - 0x18, 0x80, /* ...**...*... */ - 0x0d, 0x00, /* ....**.*.... */ - 0x0d, 0x00, /* ....**.*.... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 119 0x77 'w' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0xff, 0x70, /* ********.*** */ - 0x66, 0x20, /* .**..**...*. */ - 0x66, 0x20, /* .**..**...*. */ - 0x66, 0x20, /* .**..**...*. */ - 0x37, 0x40, /* ..**.***.*.. */ - 0x3b, 0x40, /* ..***.**.*.. */ - 0x3b, 0x40, /* ..***.**.*.. */ - 0x19, 0x80, /* ...**..**... */ - 0x19, 0x80, /* ...**..**... */ - 0x19, 0x80, /* ...**..**... */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 120 0x78 'x' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0xf8, 0xf0, /* *****...**** */ - 0x70, 0x40, /* .***.....*.. */ - 0x38, 0x80, /* ..***...*... */ - 0x1d, 0x00, /* ...***.*.... */ - 0x0e, 0x00, /* ....***..... */ - 0x07, 0x00, /* .....***.... */ - 0x0b, 0x80, /* ....*.***... */ - 0x11, 0xc0, /* ...*...***.. */ - 0x20, 0xe0, /* ..*.....***. */ - 0xf1, 0xf0, /* ****...***** */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 121 0x79 'y' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0xf0, 0xf0, /* ****....**** */ - 0x60, 0x20, /* .**.......*. */ - 0x30, 0x40, /* ..**.....*.. */ - 0x30, 0x40, /* ..**.....*.. */ - 0x18, 0x80, /* ...**...*... */ - 0x18, 0x80, /* ...**...*... */ - 0x0d, 0x00, /* ....**.*.... */ - 0x0d, 0x00, /* ....**.*.... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x04, 0x00, /* .....*...... */ - 0x0c, 0x00, /* ....**...... */ - 0x08, 0x00, /* ....*....... */ - 0x78, 0x00, /* .****....... */ - 0x70, 0x00, /* .***........ */ - 0x00, 0x00, /* ............ */ - - /* 122 0x7a 'z' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x7f, 0xe0, /* .**********. */ - 0x60, 0xe0, /* .**.....***. */ - 0x41, 0xc0, /* .*.....***.. */ - 0x03, 0x80, /* ......***... */ - 0x07, 0x00, /* .....***.... */ - 0x0e, 0x00, /* ....***..... */ - 0x1c, 0x00, /* ...***...... */ - 0x38, 0x20, /* ..***.....*. */ - 0x70, 0x60, /* .***.....**. */ - 0x7f, 0xe0, /* .**********. */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 123 0x7b '{' */ - 0x00, 0x00, /* ............ */ - 0x03, 0x80, /* ......***... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x0c, 0x00, /* ....**...... */ - 0x38, 0x00, /* ..***....... */ - 0x0c, 0x00, /* ....**...... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x03, 0x80, /* ......***... */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 124 0x7c '|' */ - 0x00, 0x00, /* ............ */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x00, 0x00, /* ............ */ - - /* 125 0x7d '}' */ - 0x00, 0x00, /* ............ */ - 0x1c, 0x00, /* ...***...... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x03, 0x00, /* ......**.... */ - 0x01, 0xc0, /* .......***.. */ - 0x03, 0x00, /* ......**.... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x1c, 0x00, /* ...***...... */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 126 0x7e '~' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x1c, 0x20, /* ...***....*. */ - 0x3e, 0x60, /* ..*****..**. */ - 0x67, 0xc0, /* .**..*****.. */ - 0x43, 0x80, /* .*....***... */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 127 0x7f '.' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 128 0x80 '.' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x0f, 0xc0, /* ....******.. */ - 0x10, 0x60, /* ...*.....**. */ - 0x20, 0x20, /* ..*.......*. */ - 0x20, 0x00, /* ..*......... */ - 0x60, 0x00, /* .**......... */ - 0x60, 0x00, /* .**......... */ - 0x60, 0x00, /* .**......... */ - 0x60, 0x00, /* .**......... */ - 0x60, 0x00, /* .**......... */ - 0x60, 0x00, /* .**......... */ - 0x20, 0x00, /* ..*......... */ - 0x30, 0x20, /* ..**......*. */ - 0x18, 0x40, /* ...**....*.. */ - 0x0f, 0x80, /* ....*****... */ - 0x06, 0x00, /* .....**..... */ - 0x03, 0x00, /* ......**.... */ - 0x01, 0x80, /* .......**... */ - 0x0f, 0x00, /* ....****.... */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 129 0x81 '.' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x19, 0x80, /* ...**..**... */ - 0x19, 0x80, /* ...**..**... */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x79, 0xe0, /* .****..****. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x39, 0xc0, /* ..***..***.. */ - 0x1e, 0x60, /* ...****..**. */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 130 0x82 '.' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x01, 0x80, /* .......**... */ - 0x03, 0x00, /* ......**.... */ - 0x06, 0x00, /* .....**..... */ - 0x00, 0x00, /* ............ */ - 0x0f, 0x00, /* ....****.... */ - 0x30, 0xc0, /* ..**....**.. */ - 0x60, 0x60, /* .**......**. */ - 0x60, 0x60, /* .**......**. */ - 0x7f, 0xe0, /* .**********. */ - 0x60, 0x00, /* .**......... */ - 0x60, 0x00, /* .**......... */ - 0x30, 0x00, /* ..**........ */ - 0x18, 0x60, /* ...**....**. */ - 0x0f, 0x80, /* ....*****... */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 131 0x83 '.' */ - 0x00, 0x00, /* ............ */ - 0x02, 0x00, /* ......*..... */ - 0x07, 0x00, /* .....***.... */ - 0x0d, 0x80, /* ....**.**... */ - 0x18, 0xc0, /* ...**...**.. */ - 0x00, 0x00, /* ............ */ - 0x0f, 0x80, /* ....*****... */ - 0x18, 0xc0, /* ...**...**.. */ - 0x10, 0xc0, /* ...*....**.. */ - 0x03, 0xc0, /* ......****.. */ - 0x1c, 0xc0, /* ...***..**.. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x39, 0xc0, /* ..***..***.. */ - 0x1e, 0xe0, /* ...****.***. */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 132 0x84 '.' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x19, 0x80, /* ...**..**... */ - 0x19, 0x80, /* ...**..**... */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x0f, 0x80, /* ....*****... */ - 0x18, 0xc0, /* ...**...**.. */ - 0x10, 0xc0, /* ...*....**.. */ - 0x03, 0xc0, /* ......****.. */ - 0x1c, 0xc0, /* ...***..**.. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x39, 0xc0, /* ..***..***.. */ - 0x1e, 0xe0, /* ...****.***. */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 133 0x85 '.' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x0c, 0x00, /* ....**...... */ - 0x06, 0x00, /* .....**..... */ - 0x03, 0x00, /* ......**.... */ - 0x00, 0x00, /* ............ */ - 0x0f, 0x80, /* ....*****... */ - 0x18, 0xc0, /* ...**...**.. */ - 0x10, 0xc0, /* ...*....**.. */ - 0x03, 0xc0, /* ......****.. */ - 0x1c, 0xc0, /* ...***..**.. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x39, 0xc0, /* ..***..***.. */ - 0x1e, 0xe0, /* ...****.***. */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 134 0x86 '.' */ - 0x00, 0x00, /* ............ */ - 0x07, 0x00, /* .....***.... */ - 0x0d, 0x80, /* ....**.**... */ - 0x0d, 0x80, /* ....**.**... */ - 0x07, 0x00, /* .....***.... */ - 0x00, 0x00, /* ............ */ - 0x0f, 0x80, /* ....*****... */ - 0x18, 0xc0, /* ...**...**.. */ - 0x10, 0xc0, /* ...*....**.. */ - 0x03, 0xc0, /* ......****.. */ - 0x1c, 0xc0, /* ...***..**.. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x39, 0xc0, /* ..***..***.. */ - 0x1e, 0xe0, /* ...****.***. */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 135 0x87 '.' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x1f, 0x80, /* ...******... */ - 0x31, 0xc0, /* ..**...***.. */ - 0x20, 0xc0, /* ..*.....**.. */ - 0x60, 0x00, /* .**......... */ - 0x60, 0x00, /* .**......... */ - 0x60, 0x00, /* .**......... */ - 0x60, 0x00, /* .**......... */ - 0x70, 0x40, /* .***.....*.. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x1f, 0x80, /* ...******... */ - 0x06, 0x00, /* .....**..... */ - 0x03, 0x00, /* ......**.... */ - 0x01, 0x80, /* .......**... */ - 0x0f, 0x00, /* ....****.... */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 136 0x88 '.' */ - 0x00, 0x00, /* ............ */ - 0x02, 0x00, /* ......*..... */ - 0x07, 0x00, /* .....***.... */ - 0x0d, 0x80, /* ....**.**... */ - 0x18, 0xc0, /* ...**...**.. */ - 0x00, 0x00, /* ............ */ - 0x0f, 0x00, /* ....****.... */ - 0x30, 0xc0, /* ..**....**.. */ - 0x60, 0x60, /* .**......**. */ - 0x60, 0x60, /* .**......**. */ - 0x7f, 0xe0, /* .**********. */ - 0x60, 0x00, /* .**......... */ - 0x60, 0x00, /* .**......... */ - 0x30, 0x00, /* ..**........ */ - 0x18, 0x60, /* ...**....**. */ - 0x0f, 0x80, /* ....*****... */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 137 0x89 '.' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x19, 0x80, /* ...**..**... */ - 0x19, 0x80, /* ...**..**... */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x0f, 0x00, /* ....****.... */ - 0x30, 0xc0, /* ..**....**.. */ - 0x60, 0x60, /* .**......**. */ - 0x60, 0x60, /* .**......**. */ - 0x7f, 0xe0, /* .**********. */ - 0x60, 0x00, /* .**......... */ - 0x60, 0x00, /* .**......... */ - 0x30, 0x00, /* ..**........ */ - 0x18, 0x60, /* ...**....**. */ - 0x0f, 0x80, /* ....*****... */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 138 0x8a '.' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x0c, 0x00, /* ....**...... */ - 0x06, 0x00, /* .....**..... */ - 0x03, 0x00, /* ......**.... */ - 0x00, 0x00, /* ............ */ - 0x0f, 0x00, /* ....****.... */ - 0x30, 0xc0, /* ..**....**.. */ - 0x60, 0x60, /* .**......**. */ - 0x60, 0x60, /* .**......**. */ - 0x7f, 0xe0, /* .**********. */ - 0x60, 0x00, /* .**......... */ - 0x60, 0x00, /* .**......... */ - 0x30, 0x00, /* ..**........ */ - 0x18, 0x60, /* ...**....**. */ - 0x0f, 0x80, /* ....*****... */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 139 0x8b '.' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x19, 0x80, /* ...**..**... */ - 0x19, 0x80, /* ...**..**... */ - 0x00, 0x00, /* ............ */ - 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0x30, 0xc0, /* ..**....**.. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x39, 0xc0, /* ..***..***.. */ - 0x1e, 0x60, /* ...****..**. */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 152 0x98 '.' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x19, 0x80, /* ...**..**... */ - 0x19, 0x80, /* ...**..**... */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0xf0, 0xf0, /* ****....**** */ - 0x60, 0x20, /* .**.......*. */ - 0x30, 0x40, /* ..**.....*.. */ - 0x30, 0x40, /* ..**.....*.. */ - 0x18, 0x80, /* ...**...*... */ - 0x18, 0x80, /* ...**...*... */ - 0x0d, 0x00, /* ....**.*.... */ - 0x0d, 0x00, /* ....**.*.... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x04, 0x00, /* .....*...... */ - 0x0c, 0x00, /* ....**...... */ - 0x08, 0x00, /* ....*....... */ - 0x78, 0x00, /* .****....... */ - 0x70, 0x00, /* .***........ */ - 0x00, 0x00, /* ............ */ - - /* 153 0x99 '.' */ - 0x00, 0x00, /* ............ */ - 0x19, 0x80, /* ...**..**... */ - 0x19, 0x80, /* ...**..**... */ - 0x00, 0x00, /* ............ */ - 0x0f, 0x80, /* ....*****... */ - 0x11, 0xc0, /* ...*...***.. */ - 0x20, 0xc0, /* ..*.....**.. */ - 0x20, 0x60, /* ..*......**. */ - 0x60, 0x60, /* .**......**. */ - 0x60, 0x60, /* .**......**. */ - 0x60, 0x60, /* .**......**. */ - 0x60, 0x60, /* .**......**. */ - 0x20, 0x40, /* ..*......*.. */ - 0x30, 0x40, /* ..**.....*.. */ - 0x18, 0x80, /* ...**...*... */ - 0x0f, 0x00, /* ....****.... */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 154 0x9a '.' */ - 0x00, 0x00, /* ............ */ - 0x19, 0x80, /* ...**..**... */ - 0x19, 0x80, /* ...**..**... */ - 0xe0, 0x30, /* ***.......** */ - 0x60, 0x20, /* .**.......*. */ - 0x60, 0x20, /* .**.......*. */ - 0x60, 0x20, /* .**.......*. */ - 0x60, 0x20, /* .**.......*. */ - 0x60, 0x20, /* .**.......*. */ - 0x60, 0x20, /* .**.......*. */ - 0x60, 0x20, /* .**.......*. */ - 0x60, 0x20, /* .**.......*. */ - 0x60, 0x20, /* .**.......*. */ - 0x70, 0x40, /* .***.....*.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x1f, 0x80, /* ...******... */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 155 0x9b '.' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x1f, 0x80, /* ...******... */ - 0x36, 0xc0, /* ..**.**.**.. */ - 0x26, 0xc0, /* ..*..**.**.. */ - 0x66, 0x00, /* .**..**..... */ - 0x66, 0x00, /* .**..**..... */ - 0x66, 0x00, /* .**..**..... */ - 0x66, 0x00, /* .**..**..... */ - 0x76, 0x40, /* .***.**..*.. */ - 0x36, 0xc0, /* ..**.**.**.. */ - 0x1f, 0x80, /* ...******... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 156 0x9c '.' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x0f, 0x80, /* ....*****... */ - 0x1c, 0xc0, /* ...***..**.. */ - 0x18, 0xc0, /* ...**...**.. */ - 0x18, 0x00, /* ...**....... */ - 0x18, 0x00, /* ...**....... */ - 0x18, 0x00, /* ...**....... */ - 0x7e, 0x00, /* .******..... */ - 0x7e, 0x00, /* .******..... */ - 0x18, 0x00, /* ...**....... */ - 0x18, 0x00, /* ...**....... */ - 0x18, 0x00, /* ...**....... */ - 0x18, 0x00, /* ...**....... */ - 0x3e, 0x20, /* ..*****...*. */ - 0x7f, 0xe0, /* .**********. */ - 0x61, 0xc0, /* .**....***.. */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 157 0x9d '.' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x60, 0x60, /* .**......**. */ - 0x60, 0x60, /* .**......**. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x19, 0x80, /* ...**..**... */ - 0x19, 0x80, /* ...**..**... */ - 0x0f, 0x00, /* ....****.... */ - 0x06, 0x00, /* .....**..... */ - 0x1f, 0x80, /* ...******... */ - 0x06, 0x00, /* .....**..... */ - 0x1f, 0x80, /* ...******... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 158 0x9e '.' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 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0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 160 0xa0 '.' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x01, 0x80, /* .......**... */ - 0x03, 0x00, /* ......**.... */ - 0x06, 0x00, /* .....**..... */ - 0x00, 0x00, /* ............ */ - 0x0f, 0x80, /* ....*****... */ - 0x18, 0xc0, /* ...**...**.. */ - 0x10, 0xc0, /* ...*....**.. */ - 0x03, 0xc0, /* ......****.. */ - 0x1c, 0xc0, /* ...***..**.. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x39, 0xc0, /* ..***..***.. */ - 0x1e, 0xe0, /* ...****.***. */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 161 0xa1 '.' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x01, 0x80, /* .......**... */ - 0x03, 0x00, /* ......**.... */ - 0x06, 0x00, /* .....**..... */ - 0x00, 0x00, /* ............ */ - 0x1e, 0x00, /* ...****..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x1f, 0x80, /* ...******... */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 162 0xa2 '.' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x01, 0x80, /* .......**... */ - 0x03, 0x00, /* ......**.... */ - 0x06, 0x00, /* .....**..... */ - 0x00, 0x00, /* ............ */ - 0x0f, 0x80, /* ....*****... */ - 0x11, 0xc0, /* ...*...***.. */ - 0x20, 0xe0, /* ..*.....***. */ - 0x60, 0x60, /* .**......**. */ - 0x60, 0x60, /* .**......**. */ - 0x60, 0x60, /* .**......**. */ - 0x60, 0x60, /* .**......**. */ - 0x70, 0x40, /* .***.....*.. */ - 0x38, 0x80, /* ..***...*... */ - 0x1f, 0x00, /* ...*****.... */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 163 0xa3 '.' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x01, 0x80, /* .......**... */ - 0x03, 0x00, /* ......**.... */ - 0x06, 0x00, /* .....**..... */ - 0x00, 0x00, /* ............ */ - 0x79, 0xe0, /* .****..****. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x39, 0xc0, /* ..***..***.. */ - 0x1e, 0x60, /* ...****..**. */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 164 0xa4 '.' */ - 0x00, 0x00, /* ............ */ - 0x1c, 0x40, /* ...***...*.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x23, 0x80, /* ..*...***... */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x27, 0x80, /* ..*..****... */ - 0x79, 0xc0, /* .****..***.. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x79, 0xe0, /* .****..****. */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 165 0xa5 '.' */ - 0x00, 0x00, /* ............ */ - 0x1c, 0x40, /* ...***...*.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x23, 0x80, /* ..*...***... */ - 0xc0, 0x70, /* **.......*** */ - 0x60, 0x20, /* .**.......*. */ - 0x70, 0x20, /* .***......*. */ - 0x78, 0x20, /* .****.....*. */ - 0x5c, 0x20, /* .*.***....*. */ - 0x4e, 0x20, /* .*..***...*. */ - 0x47, 0x20, /* .*...***..*. */ - 0x43, 0xa0, /* .*....***.*. */ - 0x41, 0xe0, /* .*.....****. */ - 0x40, 0xe0, /* .*......***. */ - 0x40, 0x60, /* .*.......**. */ - 0xe0, 0x30, /* ***.......** */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 166 0xa6 '.' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x1f, 0x00, /* ...*****.... */ - 0x31, 0x80, /* ..**...**... */ - 0x01, 0x80, /* .......**... */ - 0x07, 0x80, /* .....****... */ - 0x19, 0x80, /* ...**..**... */ - 0x31, 0x80, /* ..**...**... */ - 0x31, 0x80, /* ..**...**... */ - 0x33, 0x80, /* ..**..***... */ - 0x1d, 0xc0, /* ...***.***.. */ - 0x00, 0x00, /* ............ */ - 0x3f, 0xc0, /* ..********.. */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 167 0xa7 '.' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x07, 0x00, /* .....***.... */ - 0x19, 0x80, /* ...**..**... */ - 0x10, 0xc0, /* ...*....**.. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x30, 0x80, /* ..**....*... */ - 0x19, 0x80, /* ...**..**... */ - 0x0e, 0x00, /* ....***..... */ - 0x00, 0x00, /* ............ */ - 0x3f, 0xc0, /* ..********.. */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 168 0xa8 '.' */ - 0x00, 0x00, /* ............ */ - 0x03, 0x00, /* ......**.... */ - 0x03, 0x00, /* ......**.... */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x03, 0x00, /* ......**.... */ - 0x03, 0x00, /* ......**.... */ - 0x06, 0x00, /* .....**..... */ - 0x0c, 0x00, /* ....**...... */ - 0x18, 0x00, /* ...**....... */ - 0x30, 0x00, /* ..**........ */ - 0x30, 0x00, /* ..**........ */ - 0x30, 0x40, /* ..**.....*.. */ - 0x39, 0xc0, /* ..***..***.. */ - 0x1f, 0x80, /* ...******... */ - 0x0f, 0x00, /* ....****.... */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 169 0xa9 '.' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 170 0xaa '.' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x00, 0xc0, /* ........**.. */ - 0x00, 0xc0, /* ........**.. */ - 0x00, 0xc0, /* ........**.. */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 171 0xab '.' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x10, 0x00, /* ...*........ */ - 0x30, 0x00, /* ..**........ */ - 0x10, 0x00, /* ...*........ */ - 0x10, 0x40, /* ...*.....*.. */ - 0x10, 0x80, /* ...*....*... */ - 0x11, 0x00, /* ...*...*.... */ - 0x3a, 0x00, /* ..***.*..... */ - 0x05, 0xc0, /* .....*.***.. */ - 0x0a, 0x20, /* ....*.*...*. */ - 0x10, 0x20, /* ...*......*. */ - 0x20, 0xc0, /* ..*.....**.. */ - 0x41, 0x00, /* .*.....*.... */ - 0x02, 0x00, /* ......*..... */ - 0x03, 0xe0, /* ......*****. */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 172 0xac '.' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x10, 0x00, /* ...*........ */ - 0x30, 0x00, /* ..**........ */ - 0x10, 0x00, /* ...*........ */ - 0x10, 0x40, /* ...*.....*.. */ - 0x10, 0x80, /* ...*....*... */ - 0x11, 0x00, /* ...*...*.... */ - 0x3a, 0x40, /* ..***.*..*.. */ - 0x04, 0xc0, /* .....*..**.. */ - 0x09, 0x40, /* ....*..*.*.. */ - 0x12, 0x40, /* ...*..*..*.. */ - 0x24, 0x40, /* ..*..*...*.. */ - 0x47, 0xe0, /* .*...******. */ - 0x00, 0x40, /* .........*.. */ - 0x00, 0x40, /* .........*.. */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 173 0xad '.' */ - 0x00, 0x00, /* ............ */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 174 0xae '.' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x06, 0x60, /* .....**..**. */ - 0x0c, 0xc0, /* ....**..**.. */ - 0x19, 0x80, /* ...**..**... */ - 0x33, 0x00, /* ..**..**.... */ - 0x66, 0x00, /* .**..**..... */ - 0x33, 0x00, /* ..**..**.... */ - 0x19, 0x80, /* ...**..**... */ - 0x0c, 0xc0, /* ....**..**.. */ - 0x06, 0x60, /* .....**..**. */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 175 0xaf '.' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x66, 0x00, /* .**..**..... */ - 0x33, 0x00, /* ..**..**.... */ - 0x19, 0x80, /* ...**..**... */ - 0x0c, 0xc0, /* ....**..**.. */ - 0x06, 0x60, /* .....**..**. */ - 0x0c, 0xc0, /* ....**..**.. */ - 0x19, 0x80, /* ...**..**... */ - 0x33, 0x00, /* ..**..**.... */ - 0x66, 0x00, /* .**..**..... */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 176 0xb0 '.' */ - 0x0c, 0x30, /* ....**....** */ - 0x08, 0x20, /* ....*.....*. */ - 0x61, 0x80, /* .**....**... */ - 0x20, 0x80, /* ..*.....*... */ - 0x0c, 0x30, /* ....**....** */ - 0x08, 0x20, /* ....*.....*. */ - 0x61, 0x80, /* .**....**... */ - 0x20, 0x80, /* ..*.....*... */ - 0x0c, 0x30, /* ....**....** */ - 0x08, 0x20, /* ....*.....*. */ - 0x61, 0x80, /* .**....**... */ - 0x20, 0x80, /* ..*.....*... */ - 0x0c, 0x30, /* ....**....** */ - 0x08, 0x20, /* ....*.....*. */ - 0x61, 0x80, /* .**....**... */ - 0x20, 0x80, /* ..*.....*... */ - 0x0c, 0x30, /* ....**....** */ - 0x08, 0x20, /* ....*.....*. */ - 0x61, 0x80, /* .**....**... */ - 0x20, 0x80, /* ..*.....*... */ - 0x0c, 0x30, /* ....**....** */ - 0x08, 0x20, /* ....*.....*. */ - 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- /* 208 0xd0 '.' */ - 0x0d, 0x80, /* ....**.**... */ - 0x0d, 0x80, /* ....**.**... */ - 0x0d, 0x80, /* ....**.**... */ - 0x0d, 0x80, /* ....**.**... */ - 0x0d, 0x80, /* ....**.**... */ - 0x0d, 0x80, /* ....**.**... */ - 0x0d, 0x80, /* ....**.**... */ - 0x0d, 0x80, /* ....**.**... */ - 0x0d, 0x80, /* ....**.**... */ - 0x0d, 0x80, /* ....**.**... */ - 0xff, 0xf0, /* ************ */ - 0xff, 0xf0, /* ************ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 209 0xd1 '.' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0xff, 0xf0, /* ************ */ - 0xff, 0xf0, /* ************ */ - 0x00, 0x00, /* ............ */ - 0xff, 0xf0, /* ************ */ - 0xff, 0xf0, /* ************ */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - - /* 210 0xd2 '.' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0xff, 0xf0, /* ************ */ - 0xff, 0xf0, /* ************ */ - 0x0d, 0x80, /* ....**.**... */ - 0x0d, 0x80, /* ....**.**... */ - 0x0d, 0x80, /* ....**.**... */ - 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0x07, 0xf0, /* .....******* */ - 0x06, 0x00, /* .....**..... */ - 0x07, 0xf0, /* .....******* */ - 0x07, 0xf0, /* .....******* */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - - /* 214 0xd6 '.' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x0f, 0xf0, /* ....******** */ - 0x0f, 0xf0, /* ....******** */ - 0x0d, 0x80, /* ....**.**... */ - 0x0d, 0x80, /* ....**.**... */ - 0x0d, 0x80, /* ....**.**... */ - 0x0d, 0x80, /* ....**.**... */ - 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0xfc, 0x00, /* ******...... */ - 0xfc, 0x00, /* ******...... */ - 0xfc, 0x00, /* ******...... */ - 0xfc, 0x00, /* ******...... */ - 0xfc, 0x00, /* ******...... */ - 0xfc, 0x00, /* ******...... */ - 0xfc, 0x00, /* ******...... */ - 0xfc, 0x00, /* ******...... */ - 0xfc, 0x00, /* ******...... */ - 0xfc, 0x00, /* ******...... */ - 0xfc, 0x00, /* ******...... */ - 0xfc, 0x00, /* ******...... */ - - /* 222 0xde '.' */ - 0x03, 0xf0, /* ......****** */ - 0x03, 0xf0, /* ......****** */ - 0x03, 0xf0, /* ......****** */ - 0x03, 0xf0, /* ......****** */ - 0x03, 0xf0, /* ......****** */ - 0x03, 0xf0, /* ......****** */ - 0x03, 0xf0, /* ......****** */ - 0x03, 0xf0, /* ......****** */ - 0x03, 0xf0, /* ......****** */ - 0x03, 0xf0, /* ......****** */ - 0x03, 0xf0, /* ......****** */ - 0x03, 0xf0, /* ......****** */ - 0x03, 0xf0, /* ......****** */ - 0x03, 0xf0, /* ......****** */ - 0x03, 0xf0, /* ......****** */ - 0x03, 0xf0, /* ......****** */ - 0x03, 0xf0, /* ......****** */ - 0x03, 0xf0, /* ......****** */ - 0x03, 0xf0, /* ......****** */ - 0x03, 0xf0, /* ......****** */ - 0x03, 0xf0, /* ......****** */ - 0x03, 0xf0, /* ......****** */ - - /* 223 0xdf '.' */ - 0xff, 0xf0, /* ************ */ - 0xff, 0xf0, /* ************ */ - 0xff, 0xf0, /* ************ */ - 0xff, 0xf0, /* ************ */ - 0xff, 0xf0, /* ************ */ - 0xff, 0xf0, /* ************ */ - 0xff, 0xf0, /* ************ */ - 0xff, 0xf0, /* ************ */ - 0xff, 0xf0, /* ************ */ - 0xff, 0xf0, /* ************ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 224 0xe0 '.' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 225 0xe1 '.' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x0f, 0x00, /* ....****.... */ - 0x19, 0x80, /* ...**..**... */ - 0x30, 0xc0, /* ..**....**.. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x31, 0x80, /* ..**...**... */ - 0x37, 0x80, /* ..**.****... */ - 0x31, 0x80, /* ..**...**... */ - 0x30, 0xc0, /* ..**....**.. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x31, 0x80, /* ..**...**... */ - 0x77, 0x00, /* .***.***.... */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 226 0xe2 '.' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 227 0xe3 '.' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 228 0xe4 '.' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 229 0xe5 '.' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 230 0xe6 '.' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x30, 0xc0, /* ..**....**.. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x30, 0xc0, /* ..**....**.. */ - 0x39, 0xc0, /* ..***..***.. */ - 0x36, 0xe0, /* ..**.**.***. */ - 0x30, 0x00, /* ..**........ */ - 0x30, 0x00, /* ..**........ */ - 0x60, 0x00, /* .**......... */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 231 0xe7 '.' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 232 0xe8 '.' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 233 0xe9 '.' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 234 0xea '.' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 235 0xeb '.' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 236 0xec '.' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 237 0xed '.' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 238 0xee '.' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 239 0xef '.' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 240 0xf0 '.' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 241 0xf1 '.' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x7f, 0xe0, /* .**********. */ - 0x7f, 0xe0, /* .**********. */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x00, 0x00, /* ............ */ - 0x7f, 0xe0, /* .**********. */ - 0x7f, 0xe0, /* .**********. */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 242 0xf2 '.' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 243 0xf3 '.' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 244 0xf4 '.' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 245 0xf5 '.' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 246 0xf6 '.' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x7f, 0xe0, /* .**********. */ - 0x7f, 0xe0, /* .**********. */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x06, 0x00, /* .....**..... */ - 0x06, 0x00, /* .....**..... */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 247 0xf7 '.' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 248 0xf8 '.' */ - 0x00, 0x00, /* ............ */ - 0x0f, 0x00, /* ....****.... */ - 0x19, 0x80, /* ...**..**... */ - 0x19, 0x80, /* ...**..**... */ - 0x19, 0x80, /* ...**..**... */ - 0x0f, 0x00, /* ....****.... */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 249 0xf9 '.' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 250 0xfa '.' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x06, 0x00, /* .....**..... */ - 0x0f, 0x00, /* ....****.... */ - 0x0f, 0x00, /* ....****.... */ - 0x06, 0x00, /* .....**..... */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 251 0xfb '.' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 252 0xfc '.' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 253 0xfd '.' */ - 0x00, 0x00, /* ............ */ - 0x0f, 0x00, /* ....****.... */ - 0x1f, 0x80, /* ...******... */ - 0x31, 0x80, /* ..**...**... */ - 0x21, 0x80, /* ..*....**... */ - 0x03, 0x00, /* ......**.... */ - 0x06, 0x00, /* .....**..... */ - 0x0c, 0x00, /* ....**...... */ - 0x18, 0x40, /* ...**....*.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 254 0xfe '.' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x3f, 0xc0, /* ..********.. */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - - /* 255 0xff '.' */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - 0x00, 0x00, /* ............ */ - } -}; diff --git a/sys/dev/fb/gfb.h b/sys/dev/fb/gfb.h deleted file mode 100644 index 18e6f3b241c..00000000000 --- a/sys/dev/fb/gfb.h +++ /dev/null @@ -1,42 +0,0 @@ -/*- - * SPDX-License-Identifier: MIT-CMU - * - * Copyright (c) 1995, 1996 Carnegie-Mellon University. - * All rights reserved. - * - * Author: Chris G. Demetriou - * - * Permission to use, copy, modify and distribute this software and - * its documentation is hereby granted, provided that both the copyright - * notice and this permission notice appear in all copies of the - * software, derivative works or modified versions, and any portions - * thereof, and that both notices appear in supporting documentation. - * - * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" - * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND - * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. - * - * Carnegie Mellon requests users of this software to return to - * - * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU - * School of Computer Science - * Carnegie Mellon University - * Pittsburgh PA 15213-3890 - * - * any improvements or extensions that they make and grant Carnegie the - * rights to redistribute these changes. - * - * Copyright (c) 2000 Andrew Miklic - * - */ - -#ifndef _FB_GFB_H_ -#define _FB_GFB_H_ - -struct gfb_font { - int width; - int height; - const u_char data[]; -}; - -#endif /* _FB_GFB_H_ */ diff --git a/sys/dev/fb/machfb.c b/sys/dev/fb/machfb.c deleted file mode 100644 index 805b42a1acd..00000000000 --- a/sys/dev/fb/machfb.c +++ /dev/null @@ -1,1580 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-3-Clause - * - * Copyright (c) 2002 Bang Jun-Young - * Copyright (c) 2005 Marius Strobl - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * from: NetBSD: machfb.c,v 1.23 2005/03/07 21:45:24 martin Exp - */ - -#include - -/* - * Driver for ATI Mach64 graphics chips. Some code is derived from the - * ATI Rage Pro and Derivatives Programmer's Guide. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include -#include - -#include -#include -#include -#include -#include - -#include - -#include -#include -#include -#include -#include -#include - -/* #define MACHFB_DEBUG */ - -#define MACHFB_DRIVER_NAME "machfb" - -#define MACH64_REG_OFF 0x7ffc00 -#define MACH64_REG_SIZE 1024 - -struct machfb_softc { - video_adapter_t sc_va; /* must be first */ - - phandle_t sc_node; - uint16_t sc_chip_id; - uint8_t sc_chip_rev; - - struct resource *sc_memres; - struct resource *sc_vmemres; - bus_space_tag_t sc_memt; - bus_space_tag_t sc_regt; - bus_space_tag_t sc_vmemt; - bus_space_handle_t sc_memh; - bus_space_handle_t sc_vmemh; - bus_space_handle_t sc_regh; - u_long sc_mem; - u_long sc_vmem; - - u_int sc_height; - u_int sc_width; - u_int sc_depth; - u_int sc_xmargin; - u_int sc_ymargin; - - size_t sc_memsize; - u_int sc_memtype; - u_int sc_mem_freq; - u_int sc_ramdac_freq; - u_int sc_ref_freq; - - u_int sc_ref_div; - u_int sc_mclk_post_div; - u_int sc_mclk_fb_div; - - const u_char *sc_font; - u_int sc_cbwidth; - vm_offset_t sc_curoff; - - int sc_bg_cache; - int sc_fg_cache; - u_int sc_draw_cache; -#define MACHFB_DRAW_CHAR (1 << 0) -#define MACHFB_DRAW_FILLRECT (1 << 1) - - u_int sc_flags; -#define MACHFB_CONSOLE (1 << 0) -#define MACHFB_CUREN (1 << 1) -#define MACHFB_DSP (1 << 2) -#define MACHFB_SWAP (1 << 3) -}; - -static const struct { - uint16_t chip_id; - const char *name; - uint32_t ramdac_freq; -} machfb_info[] = { - { ATI_MACH64_CT, "ATI Mach64 CT", 135000 }, - { ATI_RAGE_PRO_AGP, "ATI 3D Rage Pro (AGP)", 230000 }, - { ATI_RAGE_PRO_AGP1X, "ATI 3D Rage Pro (AGP 1x)", 230000 }, - { ATI_RAGE_PRO_PCI_B, "ATI 3D Rage Pro Turbo", 230000 }, - { ATI_RAGE_XC_PCI66, "ATI Rage XL (PCI66)", 230000 }, - { ATI_RAGE_XL_AGP, "ATI Rage XL (AGP)", 230000 }, - { ATI_RAGE_XC_AGP, "ATI Rage XC (AGP)", 230000 }, - { ATI_RAGE_XL_PCI66, "ATI Rage XL (PCI66)", 230000 }, - { ATI_RAGE_PRO_PCI_P, "ATI 3D Rage Pro", 230000 }, - { ATI_RAGE_PRO_PCI_L, "ATI 3D Rage Pro (limited 3D)", 230000 }, - { ATI_RAGE_XL_PCI, "ATI Rage XL", 230000 }, - { ATI_RAGE_XC_PCI, "ATI Rage XC", 230000 }, - { ATI_RAGE_II, "ATI 3D Rage I/II", 135000 }, - { ATI_RAGE_IIP, "ATI 3D Rage II+", 200000 }, - { ATI_RAGE_IIC_PCI, "ATI 3D Rage IIC", 230000 }, - { ATI_RAGE_IIC_AGP_B, "ATI 3D Rage IIC (AGP)", 230000 }, - { ATI_RAGE_IIC_AGP_P, "ATI 3D Rage IIC (AGP)", 230000 }, - { ATI_RAGE_LT_PRO_AGP, "ATI 3D Rage LT Pro (AGP 133MHz)", 230000 }, - { ATI_RAGE_MOB_M3_PCI, "ATI Rage Mobility M3", 230000 }, - { ATI_RAGE_MOB_M3_AGP, "ATI Rage Mobility M3 (AGP)", 230000 }, - { ATI_RAGE_LT, "ATI 3D Rage LT", 230000 }, - { ATI_RAGE_LT_PRO_PCI, "ATI 3D Rage LT Pro", 230000 }, - { ATI_RAGE_MOBILITY, "ATI Rage Mobility", 230000 }, - { ATI_RAGE_L_MOBILITY, "ATI Rage L Mobility", 230000 }, - { ATI_RAGE_LT_PRO, "ATI 3D Rage LT Pro", 230000 }, - { ATI_RAGE_LT_PRO2, "ATI 3D Rage LT Pro", 230000 }, - { ATI_RAGE_MOB_M1_PCI, "ATI Rage Mobility M1 (PCI)", 230000 }, - { ATI_RAGE_L_MOB_M1_PCI, "ATI Rage L Mobility (PCI)", 230000 }, - { ATI_MACH64_VT, "ATI Mach64 VT", 170000 }, - { ATI_MACH64_VTB, "ATI Mach64 VTB", 200000 }, - { ATI_MACH64_VT4, "ATI Mach64 VT4", 230000 } -}; - -static const struct machfb_cmap { - uint8_t red; - uint8_t green; - uint8_t blue; -} machfb_default_cmap[16] = { - {0x00, 0x00, 0x00}, /* black */ - {0x00, 0x00, 0xff}, /* blue */ - {0x00, 0xff, 0x00}, /* green */ - {0x00, 0xc0, 0xc0}, /* cyan */ - {0xff, 0x00, 0x00}, /* red */ - {0xc0, 0x00, 0xc0}, /* magenta */ - {0xc0, 0xc0, 0x00}, /* brown */ - {0xc0, 0xc0, 0xc0}, /* light grey */ - {0x80, 0x80, 0x80}, /* dark grey */ - {0x80, 0x80, 0xff}, /* light blue */ - {0x80, 0xff, 0x80}, /* light green */ - {0x80, 0xff, 0xff}, /* light cyan */ - {0xff, 0x80, 0x80}, /* light red */ - {0xff, 0x80, 0xff}, /* light magenta */ - {0xff, 0xff, 0x80}, /* yellow */ - {0xff, 0xff, 0xff} /* white */ -}; - -#define MACHFB_CMAP_OFF 16 - -static const u_char machfb_mouse_pointer_bits[64][8] = { - { 0x00, 0x00, }, /* ............ */ - { 0x80, 0x00, }, /* *........... */ - { 0xc0, 0x00, }, /* **.......... */ - { 0xe0, 0x00, }, /* ***......... */ - { 0xf0, 0x00, }, /* ****........ */ - { 0xf8, 0x00, }, /* *****....... */ - { 0xfc, 0x00, }, /* ******...... */ - { 0xfe, 0x00, }, /* *******..... */ - { 0xff, 0x00, }, /* ********.... */ - { 0xff, 0x80, }, /* *********... */ - { 0xfc, 0xc0, }, /* ******..**.. */ - { 0xdc, 0x00, }, /* **.***...... */ - { 0x8e, 0x00, }, /* *...***..... */ - { 0x0e, 0x00, }, /* ....***..... */ - { 0x07, 0x00, }, /* .....***.... */ - { 0x04, 0x00, }, /* .....*...... */ - { 0x00, 0x00, }, /* ............ */ - { 0x00, 0x00, }, /* ............ */ - { 0x00, 0x00, }, /* ............ */ - { 0x00, 0x00, }, /* ............ */ - { 0x00, 0x00, }, /* ............ */ - { 0x00, 0x00, }, /* ............ */ -}; - -/* - * Lookup table to perform a bit-swap of the mouse pointer bits, - * map set bits to CUR_CLR0 and unset bits to transparent. - */ -static const u_char machfb_mouse_pointer_lut[] = { - 0xaa, 0x2a, 0x8a, 0x0a, 0xa2, 0x22, 0x82, 0x02, - 0xa8, 0x28, 0x88, 0x08, 0xa0, 0x20, 0x80, 0x00 -}; - -static const char *const machfb_memtype_names[] = { - "(N/A)", "DRAM", "EDO DRAM", "EDO DRAM", "SDRAM", "SGRAM", "WRAM", - "(unknown type)" -}; - -extern const struct gfb_font gallant12x22; - -static struct machfb_softc machfb_softc; -static struct bus_space_tag machfb_bst_store[1]; - -static device_probe_t machfb_pci_probe; -static device_attach_t machfb_pci_attach; -static device_detach_t machfb_pci_detach; - -static device_method_t machfb_methods[] = { - /* Device interface */ - DEVMETHOD(device_probe, machfb_pci_probe), - DEVMETHOD(device_attach, machfb_pci_attach), - DEVMETHOD(device_detach, machfb_pci_detach), - - { 0, 0 } -}; - -static driver_t machfb_pci_driver = { - MACHFB_DRIVER_NAME, - machfb_methods, - sizeof(struct machfb_softc), -}; - -static devclass_t machfb_devclass; - -DRIVER_MODULE(machfb, pci, machfb_pci_driver, machfb_devclass, 0, 0); -MODULE_DEPEND(machfb, pci, 1, 1, 1); - -static void machfb_cursor_enable(struct machfb_softc *, int); -static int machfb_cursor_install(struct machfb_softc *); -static int machfb_get_memsize(struct machfb_softc *); -static void machfb_reset_engine(struct machfb_softc *); -static void machfb_init_engine(struct machfb_softc *); -#if 0 -static void machfb_adjust_frame(struct machfb_softc *, int, int); -#endif -static void machfb_shutdown_final(void *); -static void machfb_shutdown_reset(void *); - -static int machfb_configure(int); - -static vi_probe_t machfb_probe; -static vi_init_t machfb_init; -static vi_get_info_t machfb_get_info; -static vi_query_mode_t machfb_query_mode; -static vi_set_mode_t machfb_set_mode; -static vi_save_font_t machfb_save_font; -static vi_load_font_t machfb_load_font; -static vi_show_font_t machfb_show_font; -static vi_save_palette_t machfb_save_palette; -static vi_load_palette_t machfb_load_palette; -static vi_set_border_t machfb_set_border; -static vi_save_state_t machfb_save_state; -static vi_load_state_t machfb_load_state; -static vi_set_win_org_t machfb_set_win_org; -static vi_read_hw_cursor_t machfb_read_hw_cursor; -static vi_set_hw_cursor_t machfb_set_hw_cursor; -static vi_set_hw_cursor_shape_t machfb_set_hw_cursor_shape; -static vi_blank_display_t machfb_blank_display; -static vi_mmap_t machfb_mmap; -static vi_ioctl_t machfb_ioctl; -static vi_clear_t machfb_clear; -static vi_fill_rect_t machfb_fill_rect; -static vi_bitblt_t machfb_bitblt; -static vi_diag_t machfb_diag; -static vi_save_cursor_palette_t machfb_save_cursor_palette; -static vi_load_cursor_palette_t machfb_load_cursor_palette; -static vi_copy_t machfb_copy; -static vi_putp_t machfb_putp; -static vi_putc_t machfb_putc; -static vi_puts_t machfb_puts; -static vi_putm_t machfb_putm; - -static video_switch_t machfbvidsw = { - .probe = machfb_probe, - .init = machfb_init, - .get_info = machfb_get_info, - .query_mode = machfb_query_mode, - .set_mode = machfb_set_mode, - .save_font = machfb_save_font, - .load_font = machfb_load_font, - .show_font = machfb_show_font, - .save_palette = machfb_save_palette, - .load_palette = machfb_load_palette, - .set_border = machfb_set_border, - .save_state = machfb_save_state, - .load_state = machfb_load_state, - .set_win_org = machfb_set_win_org, - .read_hw_cursor = machfb_read_hw_cursor, - .set_hw_cursor = machfb_set_hw_cursor, - .set_hw_cursor_shape = machfb_set_hw_cursor_shape, - .blank_display = machfb_blank_display, - .mmap = machfb_mmap, - .ioctl = machfb_ioctl, - .clear = machfb_clear, - .fill_rect = machfb_fill_rect, - .bitblt = machfb_bitblt, - .diag = machfb_diag, - .save_cursor_palette = machfb_save_cursor_palette, - .load_cursor_palette = machfb_load_cursor_palette, - .copy = machfb_copy, - .putp = machfb_putp, - .putc = machfb_putc, - .puts = machfb_puts, - .putm = machfb_putm -}; - -VIDEO_DRIVER(machfb, machfbvidsw, machfb_configure); - -extern sc_rndr_sw_t txtrndrsw; -RENDERER(machfb, 0, txtrndrsw, gfb_set); - -RENDERER_MODULE(machfb, gfb_set); - -/* - * Inline functions for getting access to register aperture. - */ -static inline uint32_t regr(struct machfb_softc *, uint32_t); -static inline uint8_t regrb(struct machfb_softc *, uint32_t); -static inline void regw(struct machfb_softc *, uint32_t, uint32_t); -static inline void regwb(struct machfb_softc *, uint32_t, uint8_t); -static inline void regwb_pll(struct machfb_softc *, uint32_t, uint8_t); - -static inline uint32_t -regr(struct machfb_softc *sc, uint32_t index) -{ - - return bus_space_read_4(sc->sc_regt, sc->sc_regh, index); -} - -static inline uint8_t -regrb(struct machfb_softc *sc, uint32_t index) -{ - - return bus_space_read_1(sc->sc_regt, sc->sc_regh, index); -} - -static inline void -regw(struct machfb_softc *sc, uint32_t index, uint32_t data) -{ - - bus_space_write_4(sc->sc_regt, sc->sc_regh, index, data); - bus_space_barrier(sc->sc_regt, sc->sc_regh, index, 4, - BUS_SPACE_BARRIER_WRITE); -} - -static inline void -regwb(struct machfb_softc *sc, uint32_t index, uint8_t data) -{ - - bus_space_write_1(sc->sc_regt, sc->sc_regh, index, data); - bus_space_barrier(sc->sc_regt, sc->sc_regh, index, 1, - BUS_SPACE_BARRIER_WRITE); -} - -static inline void -regwb_pll(struct machfb_softc *sc, uint32_t index, uint8_t data) -{ - - regwb(sc, CLOCK_CNTL + 1, (index << 2) | PLL_WR_EN); - regwb(sc, CLOCK_CNTL + 2, data); - regwb(sc, CLOCK_CNTL + 1, (index << 2) & ~PLL_WR_EN); -} - -static inline void -wait_for_fifo(struct machfb_softc *sc, uint8_t v) -{ - - while ((regr(sc, FIFO_STAT) & 0xffff) > (0x8000 >> v)) - ; -} - -static inline void -wait_for_idle(struct machfb_softc *sc) -{ - - wait_for_fifo(sc, 16); - while ((regr(sc, GUI_STAT) & 1) != 0) - ; -} - -/* - * Inline functions for setting the background and foreground colors. - */ -static inline void machfb_setbg(struct machfb_softc *sc, int bg); -static inline void machfb_setfg(struct machfb_softc *sc, int fg); - -static inline void -machfb_setbg(struct machfb_softc *sc, int bg) -{ - - if (bg == sc->sc_bg_cache) - return; - sc->sc_bg_cache = bg; - wait_for_fifo(sc, 1); - regw(sc, DP_BKGD_CLR, bg + MACHFB_CMAP_OFF); -} - -static inline void -machfb_setfg(struct machfb_softc *sc, int fg) -{ - - if (fg == sc->sc_fg_cache) - return; - sc->sc_fg_cache = fg; - wait_for_fifo(sc, 1); - regw(sc, DP_FRGD_CLR, fg + MACHFB_CMAP_OFF); -} - -/* - * video driver interface - */ -static int -machfb_configure(int flags) -{ - struct machfb_softc *sc; - phandle_t chosen, output; - ihandle_t stdout; - bus_addr_t addr; - uint32_t id; - int i, space; - - /* - * For the high-level console probing return the number of - * registered adapters. - */ - if (!(flags & VIO_PROBE_ONLY)) { - for (i = 0; vid_find_adapter(MACHFB_DRIVER_NAME, i) >= 0; i++) - ; - return (i); - } - - /* Low-level console probing and initialization. */ - - sc = &machfb_softc; - if (sc->sc_va.va_flags & V_ADP_REGISTERED) - goto found; - - if ((chosen = OF_finddevice("/chosen")) == -1) /* Quis contra nos? */ - return (0); - if (OF_getprop(chosen, "stdout", &stdout, sizeof(stdout)) == -1) - return (0); - if ((output = OF_instance_to_package(stdout)) == -1) - return (0); - if ((OF_getprop(output, "vendor-id", &id, sizeof(id)) == -1) || - id != ATI_VENDOR) - return (0); - if (OF_getprop(output, "device-id", &id, sizeof(id)) == -1) - return (0); - for (i = 0; i < nitems(machfb_info); i++) { - if (id == machfb_info[i].chip_id) { - sc->sc_flags = MACHFB_CONSOLE; - sc->sc_node = output; - sc->sc_chip_id = id; - break; - } - } - if (!(sc->sc_flags & MACHFB_CONSOLE)) - return (0); - - if (OF_getprop(output, "revision-id", &sc->sc_chip_rev, - sizeof(sc->sc_chip_rev)) == -1) - return (0); - if (OF_decode_addr(output, 0, &space, &addr) != 0) - return (0); - sc->sc_memt = &machfb_bst_store[0]; - sc->sc_memh = sparc64_fake_bustag(space, addr, sc->sc_memt); - sc->sc_regt = sc->sc_memt; - bus_space_subregion(sc->sc_regt, sc->sc_memh, MACH64_REG_OFF, - MACH64_REG_SIZE, &sc->sc_regh); - - if (machfb_init(0, &sc->sc_va, 0) < 0) - return (0); - - found: - /* Return number of found adapters. */ - return (1); -} - -static int -machfb_probe(int unit, video_adapter_t **adpp, void *arg, int flags) -{ - - return (0); -} - -static int -machfb_init(int unit, video_adapter_t *adp, int flags) -{ - struct machfb_softc *sc; - phandle_t options; - video_info_t *vi; - char buf[32]; - int i; - uint8_t dac_mask, dac_rindex, dac_windex; - - sc = (struct machfb_softc *)adp; - vi = &adp->va_info; - - if ((regr(sc, CONFIG_CHIP_ID) & 0xffff) != sc->sc_chip_id) - return (ENXIO); - - sc->sc_ramdac_freq = 0; - for (i = 0; i < nitems(machfb_info); i++) { - if (sc->sc_chip_id == machfb_info[i].chip_id) { - sc->sc_ramdac_freq = machfb_info[i].ramdac_freq; - break; - } - } - if (sc->sc_ramdac_freq == 0) - return (ENXIO); - if (sc->sc_chip_id == ATI_RAGE_II && sc->sc_chip_rev & 0x07) - sc->sc_ramdac_freq = 170000; - - vid_init_struct(adp, MACHFB_DRIVER_NAME, -1, unit); - - if (OF_getprop(sc->sc_node, "height", &sc->sc_height, - sizeof(sc->sc_height)) == -1) - return (ENXIO); - if (OF_getprop(sc->sc_node, "width", &sc->sc_width, - sizeof(sc->sc_width)) == -1) - return (ENXIO); - if (OF_getprop(sc->sc_node, "depth", &sc->sc_depth, - sizeof(sc->sc_depth)) == -1) - return (ENXIO); - if ((options = OF_finddevice("/options")) == -1) - return (ENXIO); - if (OF_getprop(options, "screen-#rows", buf, sizeof(buf)) == -1) - return (ENXIO); - vi->vi_height = strtol(buf, NULL, 10); - if (OF_getprop(options, "screen-#columns", buf, sizeof(buf)) == -1) - return (ENXIO); - vi->vi_width = strtol(buf, NULL, 10); - vi->vi_cwidth = gallant12x22.width; - vi->vi_cheight = gallant12x22.height; - vi->vi_flags = V_INFO_COLOR; - vi->vi_mem_model = V_INFO_MM_OTHER; - - sc->sc_font = gallant12x22.data; - sc->sc_cbwidth = howmany(vi->vi_cwidth, NBBY); /* width in bytes */ - sc->sc_xmargin = (sc->sc_width - (vi->vi_width * vi->vi_cwidth)) / 2; - sc->sc_ymargin = (sc->sc_height - (vi->vi_height * vi->vi_cheight)) / 2; - - if (sc->sc_chip_id != ATI_MACH64_CT && - !((sc->sc_chip_id == ATI_MACH64_VT || - sc->sc_chip_id == ATI_RAGE_II) && - (sc->sc_chip_rev & 0x07) == 0)) - sc->sc_flags |= MACHFB_DSP; - - sc->sc_memsize = machfb_get_memsize(sc); - if (sc->sc_memsize == 8192) - /* The last page is used as register aperture. */ - sc->sc_memsize -= 4; - sc->sc_memtype = regr(sc, CONFIG_STAT0) & 0x07; - - if ((sc->sc_chip_id >= ATI_RAGE_XC_PCI66 && - sc->sc_chip_id <= ATI_RAGE_XL_PCI66) || - (sc->sc_chip_id >= ATI_RAGE_XL_PCI && - sc->sc_chip_id <= ATI_RAGE_XC_PCI)) - sc->sc_ref_freq = 29498; - else - sc->sc_ref_freq = 14318; - - regwb(sc, CLOCK_CNTL + 1, PLL_REF_DIV << 2); - sc->sc_ref_div = regrb(sc, CLOCK_CNTL + 2); - regwb(sc, CLOCK_CNTL + 1, MCLK_FB_DIV << 2); - sc->sc_mclk_fb_div = regrb(sc, CLOCK_CNTL + 2); - sc->sc_mem_freq = (2 * sc->sc_ref_freq * sc->sc_mclk_fb_div) / - (sc->sc_ref_div * 2); - sc->sc_mclk_post_div = (sc->sc_mclk_fb_div * 2 * sc->sc_ref_freq) / - (sc->sc_mem_freq * sc->sc_ref_div); - - machfb_init_engine(sc); -#if 0 - machfb_adjust_frame(0, 0); -#endif - machfb_set_mode(adp, 0); - - /* - * Install our 16-color color map. This is done only once and with - * an offset of 16 on sparc64 as there the OBP driver expects white - * to be at index 0 and black at 255 (some versions also use 1 - 8 - * for color text support or the full palette for the boot banner - * logo but no versions seems to use the ISO 6429-1983 color map). - * Otherwise the colors are inverted when back in the OFW. - */ - dac_rindex = regrb(sc, DAC_RINDEX); - dac_windex = regrb(sc, DAC_WINDEX); - dac_mask = regrb(sc, DAC_MASK); - regwb(sc, DAC_MASK, 0xff); - regwb(sc, DAC_WINDEX, MACHFB_CMAP_OFF); - for (i = 0; i < 16; i++) { - regwb(sc, DAC_DATA, machfb_default_cmap[i].red); - regwb(sc, DAC_DATA, machfb_default_cmap[i].green); - regwb(sc, DAC_DATA, machfb_default_cmap[i].blue); - } - regwb(sc, DAC_MASK, dac_mask); - regwb(sc, DAC_RINDEX, dac_rindex); - regwb(sc, DAC_WINDEX, dac_windex); - - machfb_blank_display(adp, V_DISPLAY_ON); - machfb_clear(adp); - - /* - * Setting V_ADP_MODECHANGE serves as hack so machfb_set_mode() - * (which will invalidate our caches) is called as a precaution - * when the X server shuts down. - */ - adp->va_flags |= V_ADP_COLOR | V_ADP_MODECHANGE | V_ADP_PALETTE | - V_ADP_BORDER | V_ADP_INITIALIZED; - if (vid_register(adp) < 0) - return (ENXIO); - adp->va_flags |= V_ADP_REGISTERED; - - return (0); -} - -static int -machfb_get_info(video_adapter_t *adp, int mode, video_info_t *info) -{ - - bcopy(&adp->va_info, info, sizeof(*info)); - - return (0); -} - -static int -machfb_query_mode(video_adapter_t *adp, video_info_t *info) -{ - - return (ENODEV); -} - -static int -machfb_set_mode(video_adapter_t *adp, int mode) -{ - struct machfb_softc *sc; - - sc = (struct machfb_softc *)adp; - - sc->sc_bg_cache = -1; - sc->sc_fg_cache = -1; - sc->sc_draw_cache = 0; - - return (0); -} - -static int -machfb_save_font(video_adapter_t *adp, int page, int size, int width, - u_char *data, int c, int count) -{ - - return (ENODEV); -} - -static int -machfb_load_font(video_adapter_t *adp, int page, int size, int width, - u_char *data, int c, int count) -{ - - return (ENODEV); -} - -static int -machfb_show_font(video_adapter_t *adp, int page) -{ - - return (ENODEV); -} - -static int -machfb_save_palette(video_adapter_t *adp, u_char *palette) -{ - struct machfb_softc *sc; - int i; - uint8_t dac_mask, dac_rindex, dac_windex; - - sc = (struct machfb_softc *)adp; - - dac_rindex = regrb(sc, DAC_RINDEX); - dac_windex = regrb(sc, DAC_WINDEX); - dac_mask = regrb(sc, DAC_MASK); - regwb(sc, DAC_MASK, 0xff); - regwb(sc, DAC_RINDEX, 0x0); - for (i = 0; i < 256 * 3; i++) - palette[i] = regrb(sc, DAC_DATA); - regwb(sc, DAC_MASK, dac_mask); - regwb(sc, DAC_RINDEX, dac_rindex); - regwb(sc, DAC_WINDEX, dac_windex); - - return (0); -} - -static int -machfb_load_palette(video_adapter_t *adp, u_char *palette) -{ - struct machfb_softc *sc; - int i; - uint8_t dac_mask, dac_rindex, dac_windex; - - sc = (struct machfb_softc *)adp; - - dac_rindex = regrb(sc, DAC_RINDEX); - dac_windex = regrb(sc, DAC_WINDEX); - dac_mask = regrb(sc, DAC_MASK); - regwb(sc, DAC_MASK, 0xff); - regwb(sc, DAC_WINDEX, 0x0); - for (i = 0; i < 256 * 3; i++) - regwb(sc, DAC_DATA, palette[i]); - regwb(sc, DAC_MASK, dac_mask); - regwb(sc, DAC_RINDEX, dac_rindex); - regwb(sc, DAC_WINDEX, dac_windex); - - return (0); -} - -static int -machfb_set_border(video_adapter_t *adp, int border) -{ - struct machfb_softc *sc; - - sc = (struct machfb_softc *)adp; - - machfb_fill_rect(adp, border, 0, 0, sc->sc_width, sc->sc_ymargin); - machfb_fill_rect(adp, border, 0, sc->sc_height - sc->sc_ymargin, - sc->sc_width, sc->sc_ymargin); - machfb_fill_rect(adp, border, 0, 0, sc->sc_xmargin, sc->sc_height); - machfb_fill_rect(adp, border, sc->sc_width - sc->sc_xmargin, 0, - sc->sc_xmargin, sc->sc_height); - - return (0); -} - -static int -machfb_save_state(video_adapter_t *adp, void *p, size_t size) -{ - - return (ENODEV); -} - -static int -machfb_load_state(video_adapter_t *adp, void *p) -{ - - return (ENODEV); -} - -static int -machfb_set_win_org(video_adapter_t *adp, off_t offset) -{ - - return (ENODEV); -} - -static int -machfb_read_hw_cursor(video_adapter_t *adp, int *col, int *row) -{ - - *col = 0; - *row = 0; - - return (0); -} - -static int -machfb_set_hw_cursor(video_adapter_t *adp, int col, int row) -{ - - return (ENODEV); -} - -static int -machfb_set_hw_cursor_shape(video_adapter_t *adp, int base, int height, - int celsize, int blink) -{ - - return (ENODEV); -} - -static int -machfb_blank_display(video_adapter_t *adp, int mode) -{ - struct machfb_softc *sc; - uint32_t crtc_gen_cntl; - - sc = (struct machfb_softc *)adp; - - crtc_gen_cntl = (regr(sc, CRTC_GEN_CNTL) | CRTC_EXT_DISP_EN | CRTC_EN) & - ~(CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS); - switch (mode) { - case V_DISPLAY_ON: - break; - case V_DISPLAY_BLANK: - crtc_gen_cntl |= CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | - CRTC_DISPLAY_DIS; - break; - case V_DISPLAY_STAND_BY: - crtc_gen_cntl |= CRTC_HSYNC_DIS | CRTC_DISPLAY_DIS; - break; - case V_DISPLAY_SUSPEND: - crtc_gen_cntl |= CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS; - break; - } - regw(sc, CRTC_GEN_CNTL, crtc_gen_cntl); - - return (0); -} - -static int -machfb_mmap(video_adapter_t *adp, vm_ooffset_t offset, vm_paddr_t *paddr, - int prot, vm_memattr_t *memattr) -{ - struct machfb_softc *sc; - video_info_t *vi; - - sc = (struct machfb_softc *)adp; - vi = &adp->va_info; - - /* BAR 2 - VGA memory */ - if (sc->sc_vmem != 0 && offset >= sc->sc_vmem && - offset < sc->sc_vmem + vi->vi_registers_size) { - *paddr = vi->vi_registers + offset - sc->sc_vmem; - return (0); - } - - /* BAR 0 - framebuffer */ - if (offset >= sc->sc_mem && - offset < sc->sc_mem + vi->vi_buffer_size) { - *paddr = vi->vi_buffer + offset - sc->sc_mem; - return (0); - } - - /* 'regular' framebuffer mmap()ing */ - if (offset < adp->va_window_size) { - *paddr = vi->vi_window + offset; - return (0); - } - - return (EINVAL); -} - -static int -machfb_ioctl(video_adapter_t *adp, u_long cmd, caddr_t data) -{ - struct machfb_softc *sc; - struct fbcursor *fbc; - struct fbtype *fb; - - sc = (struct machfb_softc *)adp; - - switch (cmd) { - case FBIOGTYPE: - fb = (struct fbtype *)data; - fb->fb_type = FBTYPE_PCIMISC; - fb->fb_height = sc->sc_height; - fb->fb_width = sc->sc_width; - fb->fb_depth = sc->sc_depth; - if (sc->sc_depth <= 1 || sc->sc_depth > 8) - fb->fb_cmsize = 0; - else - fb->fb_cmsize = 1 << sc->sc_depth; - fb->fb_size = adp->va_buffer_size; - break; - case FBIOSCURSOR: - fbc = (struct fbcursor *)data; - if (fbc->set & FB_CUR_SETCUR && fbc->enable == 0) { - machfb_cursor_enable(sc, 0); - sc->sc_flags &= ~MACHFB_CUREN; - } else - return (ENODEV); - break; - default: - return (fb_commonioctl(adp, cmd, data)); - } - - return (0); -} - -static int -machfb_clear(video_adapter_t *adp) -{ - struct machfb_softc *sc; - - sc = (struct machfb_softc *)adp; - - machfb_fill_rect(adp, (SC_NORM_ATTR >> 4) & 0xf, 0, 0, sc->sc_width, - sc->sc_height); - - return (0); -} - -static int -machfb_fill_rect(video_adapter_t *adp, int val, int x, int y, int cx, int cy) -{ - struct machfb_softc *sc; - - sc = (struct machfb_softc *)adp; - - if (sc->sc_draw_cache != MACHFB_DRAW_FILLRECT) { - wait_for_fifo(sc, 7); - regw(sc, DP_WRITE_MASK, 0xff); - regw(sc, DP_PIX_WIDTH, DST_8BPP | SRC_8BPP | HOST_8BPP); - regw(sc, DP_SRC, FRGD_SRC_FRGD_CLR); - regw(sc, DP_MIX, MIX_SRC << 16); - regw(sc, CLR_CMP_CNTL, 0); /* no transparency */ - regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); - regw(sc, DST_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM); - sc->sc_draw_cache = MACHFB_DRAW_FILLRECT; - } - machfb_setfg(sc, val); - wait_for_fifo(sc, 4); - regw(sc, SRC_Y_X, (x << 16) | y); - regw(sc, SRC_WIDTH1, cx); - regw(sc, DST_Y_X, (x << 16) | y); - regw(sc, DST_HEIGHT_WIDTH, (cx << 16) | cy); - - return (0); -} - -static int -machfb_bitblt(video_adapter_t *adp, ...) -{ - - return (ENODEV); -} - -static int -machfb_diag(video_adapter_t *adp, int level) -{ - video_info_t info; - - fb_dump_adp_info(adp->va_name, adp, level); - machfb_get_info(adp, 0, &info); - fb_dump_mode_info(adp->va_name, adp, &info, level); - - return (0); -} - -static int -machfb_save_cursor_palette(video_adapter_t *adp, u_char *palette) -{ - - return (ENODEV); -} - -static int -machfb_load_cursor_palette(video_adapter_t *adp, u_char *palette) -{ - - return (ENODEV); -} - -static int -machfb_copy(video_adapter_t *adp, vm_offset_t src, vm_offset_t dst, int n) -{ - - return (ENODEV); -} - -static int -machfb_putp(video_adapter_t *adp, vm_offset_t off, uint32_t p, uint32_t a, - int size, int bpp, int bit_ltor, int byte_ltor) -{ - - return (ENODEV); -} - -static int -machfb_putc(video_adapter_t *adp, vm_offset_t off, uint8_t c, uint8_t a) -{ - struct machfb_softc *sc; - const uint8_t *p; - int i; - - sc = (struct machfb_softc *)adp; - - if (sc->sc_draw_cache != MACHFB_DRAW_CHAR) { - wait_for_fifo(sc, 8); - regw(sc, DP_WRITE_MASK, 0xff); /* XXX only good for 8 bit */ - regw(sc, DP_PIX_WIDTH, DST_8BPP | SRC_1BPP | HOST_1BPP); - regw(sc, DP_SRC, MONO_SRC_HOST | BKGD_SRC_BKGD_CLR | - FRGD_SRC_FRGD_CLR); - regw(sc, DP_MIX ,((MIX_SRC & 0xffff) << 16) | MIX_SRC); - regw(sc, CLR_CMP_CNTL, 0); /* no transparency */ - regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); - regw(sc, DST_CNTL, DST_Y_TOP_TO_BOTTOM | DST_X_LEFT_TO_RIGHT); - regw(sc, HOST_CNTL, HOST_BYTE_ALIGN); - sc->sc_draw_cache = MACHFB_DRAW_CHAR; - } - machfb_setbg(sc, (a >> 4) & 0xf); - machfb_setfg(sc, a & 0xf); - wait_for_fifo(sc, 4 + (adp->va_info.vi_cheight / sc->sc_cbwidth)); - regw(sc, SRC_Y_X, 0); - regw(sc, SRC_WIDTH1, adp->va_info.vi_cwidth); - regw(sc, DST_Y_X, ((((off % adp->va_info.vi_width) * - adp->va_info.vi_cwidth) + sc->sc_xmargin) << 16) | - (((off / adp->va_info.vi_width) * adp->va_info.vi_cheight) + - sc->sc_ymargin)); - regw(sc, DST_HEIGHT_WIDTH, (adp->va_info.vi_cwidth << 16) | - adp->va_info.vi_cheight); - p = sc->sc_font + (c * adp->va_info.vi_cheight * sc->sc_cbwidth); - for (i = 0; i < adp->va_info.vi_cheight * sc->sc_cbwidth; i += 4) - regw(sc, HOST_DATA0 + i, (p[i + 3] << 24 | p[i + 2] << 16 | - p[i + 1] << 8 | p[i])); - - return (0); -} - -static int -machfb_puts(video_adapter_t *adp, vm_offset_t off, uint16_t *s, int len) -{ - struct machfb_softc *sc; - int blanks, i, x1, x2, y1, y2; - uint8_t a, c, color1, color2; - - sc = (struct machfb_softc *)adp; - -#define MACHFB_BLANK machfb_fill_rect(adp, color1, x1, y1, \ - blanks * adp->va_info.vi_cwidth, \ - adp->va_info.vi_cheight) - - blanks = color1 = x1 = y1 = 0; - for (i = 0; i < len; i++) { - /* - * Accelerate continuous blanks by drawing a respective - * rectangle instead. Drawing a rectangle of any size - * takes about the same number of operations as drawing - * a single character. - */ - c = s[i] & 0xff; - a = (s[i] & 0xff00) >> 8; - if (c == 0x00 || c == 0x20 || c == 0xdb || c == 0xff) { - color2 = (a >> (c == 0xdb ? 0 : 4) & 0xf); - x2 = (((off + i) % adp->va_info.vi_width) * - adp->va_info.vi_cwidth) + sc->sc_xmargin; - y2 = (((off + i) / adp->va_info.vi_width) * - adp->va_info.vi_cheight) + sc->sc_ymargin; - if (blanks == 0) { - color1 = color2; - x1 = x2; - y1 = y2; - blanks++; - } else if (color1 != color2 || y1 != y2) { - MACHFB_BLANK; - color1 = color2; - x1 = x2; - y1 = y2; - blanks = 1; - } else - blanks++; - } else { - if (blanks != 0) { - MACHFB_BLANK; - blanks = 0; - } - vidd_putc(adp, off + i, c, a); - } - } - if (blanks != 0) - MACHFB_BLANK; - -#undef MACHFB_BLANK - - return (0); -} - -static int -machfb_putm(video_adapter_t *adp, int x, int y, uint8_t *pixel_image, - uint32_t pixel_mask, int size, int width) -{ - struct machfb_softc *sc; - int error; - - sc = (struct machfb_softc *)adp; - - if ((!(sc->sc_flags & MACHFB_CUREN)) && - (error = machfb_cursor_install(sc)) < 0) - return (error); - else { - /* - * The hardware cursor always must be disabled when - * fiddling with its bits otherwise some artifacts - * may appear on the screen. - */ - machfb_cursor_enable(sc, 0); - } - - regw(sc, CUR_HORZ_VERT_OFF, 0); - if ((regr(sc, GEN_TEST_CNTL) & CRTC_DBL_SCAN_EN) != 0) - y <<= 1; - regw(sc, CUR_HORZ_VERT_POSN, ((y + sc->sc_ymargin) << 16) | - (x + sc->sc_xmargin)); - machfb_cursor_enable(sc, 1); - sc->sc_flags |= MACHFB_CUREN; - - return (0); -} - -/* - * PCI bus interface - */ -static int -machfb_pci_probe(device_t dev) -{ - int i; - - if (pci_get_class(dev) != PCIC_DISPLAY || - pci_get_subclass(dev) != PCIS_DISPLAY_VGA) - return (ENXIO); - - for (i = 0; i < nitems(machfb_info); i++) { - if (pci_get_device(dev) == machfb_info[i].chip_id) { - device_set_desc(dev, machfb_info[i].name); - return (BUS_PROBE_DEFAULT); - } - } - - return (ENXIO); -} - -static int -machfb_pci_attach(device_t dev) -{ - struct machfb_softc *sc; - video_adapter_t *adp; - video_switch_t *sw; - video_info_t *vi; - phandle_t node; - int error, i, rid; - uint32_t *p32, u32; - uint8_t *p; - - node = ofw_bus_get_node(dev); - if ((sc = (struct machfb_softc *)vid_get_adapter(vid_find_adapter( - MACHFB_DRIVER_NAME, 0))) != NULL && sc->sc_node == node) { - device_printf(dev, "console\n"); - device_set_softc(dev, sc); - } else { - sc = device_get_softc(dev); - - sc->sc_node = node; - sc->sc_chip_id = pci_get_device(dev); - sc->sc_chip_rev = pci_get_revid(dev); - } - adp = &sc->sc_va; - vi = &adp->va_info; - - rid = PCIR_BAR(0); - if ((sc->sc_memres = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, - RF_ACTIVE)) == NULL) { - device_printf(dev, "cannot allocate memory resources\n"); - return (ENXIO); - } - sc->sc_memt = rman_get_bustag(sc->sc_memres); - sc->sc_memh = rman_get_bushandle(sc->sc_memres); - sc->sc_mem = rman_get_start(sc->sc_memres); - vi->vi_buffer = sc->sc_memh; - vi->vi_buffer_size = rman_get_size(sc->sc_memres); - if (OF_getprop(sc->sc_node, "address", &u32, sizeof(u32)) > 0 && - vtophys(u32) == sc->sc_memh) - adp->va_mem_base = u32; - else { - if (bus_space_map(sc->sc_memt, vi->vi_buffer, - vi->vi_buffer_size, BUS_SPACE_MAP_LINEAR, - &sc->sc_memh) != 0) { - device_printf(dev, "cannot map memory resources\n"); - error = ENXIO; - goto fail_memres; - } - adp->va_mem_base = - (vm_offset_t)rman_get_virtual(sc->sc_memres); - } - adp->va_mem_size = vi->vi_buffer_size; - adp->va_buffer = adp->va_mem_base; - adp->va_buffer_size = adp->va_mem_size; - sc->sc_regt = sc->sc_memt; - if (bus_space_subregion(sc->sc_regt, sc->sc_memh, MACH64_REG_OFF, - MACH64_REG_SIZE, &sc->sc_regh) != 0) { - device_printf(dev, "cannot allocate register resources\n"); - error = ENXIO; - goto fail_memmap; - } - - /* - * Depending on the firmware version the VGA I/O and/or memory - * resources of the Mach64 chips come up disabled. These will be - * enabled by pci(4) when activating the resource in question but - * this doesn't necessarily mean that the resource is valid. - * Invalid resources seem to have in common that they start at - * address 0. We don't allocate the VGA memory in this case in - * order to avoid warnings in apb(4) and crashes when using this - * invalid resources. X.Org is aware of this and doesn't use the - * VGA memory resource in this case (but demands it if it's valid). - */ - rid = PCIR_BAR(2); - if (bus_get_resource_start(dev, SYS_RES_MEMORY, rid) != 0) { - if ((sc->sc_vmemres = bus_alloc_resource_any(dev, - SYS_RES_MEMORY, &rid, RF_ACTIVE)) == NULL) { - device_printf(dev, - "cannot allocate VGA memory resources\n"); - error = ENXIO; - goto fail_memmap; - } - sc->sc_vmemt = rman_get_bustag(sc->sc_vmemres); - sc->sc_vmemh = rman_get_bushandle(sc->sc_vmemres); - sc->sc_vmem = rman_get_start(sc->sc_vmemres); - vi->vi_registers = sc->sc_vmemh; - vi->vi_registers_size = rman_get_size(sc->sc_vmemres); - if (bus_space_map(sc->sc_vmemt, vi->vi_registers, - vi->vi_registers_size, BUS_SPACE_MAP_LINEAR, - &sc->sc_vmemh) != 0) { - device_printf(dev, - "cannot map VGA memory resources\n"); - error = ENXIO; - goto fail_vmemres; - } - adp->va_registers = - (vm_offset_t)rman_get_virtual(sc->sc_vmemres); - adp->va_registers_size = vi->vi_registers_size; - } - - if (!(sc->sc_flags & MACHFB_CONSOLE)) { - if ((sw = vid_get_switch(MACHFB_DRIVER_NAME)) == NULL) { - device_printf(dev, "cannot get video switch\n"); - error = ENODEV; - goto fail_vmemmap; - } - /* - * During device configuration we don't necessarily probe - * the adapter which is the console first so we can't use - * the device unit number for the video adapter unit. The - * worst case would be that we use the video adapter unit - * 0 twice. As it doesn't really matter which unit number - * the corresponding video adapter has just use the next - * unused one. - */ - for (i = 0; i < devclass_get_maxunit(machfb_devclass); i++) - if (vid_find_adapter(MACHFB_DRIVER_NAME, i) < 0) - break; - if ((error = sw->init(i, adp, 0)) != 0) { - device_printf(dev, "cannot initialize adapter\n"); - goto fail_vmemmap; - } - } - - /* - * Test whether the aperture is byte swapped or not, set - * va_window and va_window_size as appropriate. Note that - * the aperture could be mapped either big or little endian - * independently of the endianness of the host so this has - * to be a runtime test. - */ - p32 = (uint32_t *)adp->va_buffer; - u32 = *p32; - p = (uint8_t *)adp->va_buffer; - *p32 = 0x12345678; - if (!(p[0] == 0x12 && p[1] == 0x34 && p[2] == 0x56 && p[3] == 0x78)) { - adp->va_window = adp->va_buffer + 0x800000; - adp->va_window_size = adp->va_buffer_size - 0x800000; - vi->vi_window = vi->vi_buffer + 0x800000; - vi->vi_window_size = vi->vi_buffer_size - 0x800000; - sc->sc_flags |= MACHFB_SWAP; - } else { - adp->va_window = adp->va_buffer; - adp->va_window_size = adp->va_buffer_size; - vi->vi_window = vi->vi_buffer; - vi->vi_window_size = vi->vi_buffer_size; - } - *p32 = u32; - adp->va_window_gran = adp->va_window_size; - - device_printf(dev, - "%d MB aperture at %p %sswapped\n", - (u_int)(adp->va_window_size / (1024 * 1024)), - (void *)adp->va_window, (sc->sc_flags & MACHFB_SWAP) ? - "" : "not "); - device_printf(dev, - "%ld KB %s %d.%d MHz, maximum RAMDAC clock %d MHz, %sDSP\n", - (u_long)sc->sc_memsize, machfb_memtype_names[sc->sc_memtype], - sc->sc_mem_freq / 1000, sc->sc_mem_freq % 1000, - sc->sc_ramdac_freq / 1000, - (sc->sc_flags & MACHFB_DSP) ? "" : "no "); - device_printf(dev, "resolution %dx%d at %d bpp\n", - sc->sc_width, sc->sc_height, sc->sc_depth); - - /* - * Allocate one page for the mouse pointer image at the end of - * the little endian aperture, right before the memory mapped - * registers that might also reside there. Must be done after - * sc_memsize was set and possibly adjusted to account for the - * memory mapped registers. - */ - sc->sc_curoff = (sc->sc_memsize * 1024) - PAGE_SIZE; - sc->sc_memsize -= PAGE_SIZE / 1024; - machfb_cursor_enable(sc, 0); - /* Initialize with an all transparent image. */ - memset((void *)(adp->va_buffer + sc->sc_curoff), 0xaa, PAGE_SIZE); - - /* - * Register a handler that performs some cosmetic surgery like - * turning off the mouse pointer on halt in preparation for - * handing the screen over to the OFW. Register another handler - * that turns off the CRTC when resetting, otherwise the OFW - * boot command issued by cpu_reset() just doesn't work. - */ - EVENTHANDLER_REGISTER(shutdown_final, machfb_shutdown_final, sc, - SHUTDOWN_PRI_DEFAULT); - EVENTHANDLER_REGISTER(shutdown_reset, machfb_shutdown_reset, sc, - SHUTDOWN_PRI_DEFAULT); - - return (0); - - fail_vmemmap: - if (adp->va_registers != 0) - bus_space_unmap(sc->sc_vmemt, sc->sc_vmemh, - vi->vi_registers_size); - fail_vmemres: - if (sc->sc_vmemres != NULL) - bus_release_resource(dev, SYS_RES_MEMORY, - rman_get_rid(sc->sc_vmemres), sc->sc_vmemres); - fail_memmap: - bus_space_unmap(sc->sc_memt, sc->sc_memh, vi->vi_buffer_size); - fail_memres: - bus_release_resource(dev, SYS_RES_MEMORY, - rman_get_rid(sc->sc_memres), sc->sc_memres); - - return (error); -} - -static int -machfb_pci_detach(device_t dev) -{ - - return (EINVAL); -} - -/* - * internal functions - */ -static void -machfb_cursor_enable(struct machfb_softc *sc, int onoff) -{ - - if (onoff) - regw(sc, GEN_TEST_CNTL, - regr(sc, GEN_TEST_CNTL) | HWCURSOR_ENABLE); - else - regw(sc, GEN_TEST_CNTL, - regr(sc, GEN_TEST_CNTL) &~ HWCURSOR_ENABLE); -} - -static int -machfb_cursor_install(struct machfb_softc *sc) -{ - uint16_t *p, v; - uint8_t fg; - int i, j; - - if (sc->sc_curoff == 0) - return (ENODEV); - - machfb_cursor_enable(sc, 0); - regw(sc, CUR_OFFSET, sc->sc_curoff >> 3); - fg = SC_NORM_ATTR & 0xf; - regw(sc, CUR_CLR0, machfb_default_cmap[fg].red << 24 | - machfb_default_cmap[fg].green << 16 | - machfb_default_cmap[fg].blue << 8); - p = (uint16_t *)(sc->sc_va.va_buffer + sc->sc_curoff); - for (i = 0; i < 64; i++) { - for (j = 0; j < 8; j++) { - v = machfb_mouse_pointer_lut[ - machfb_mouse_pointer_bits[i][j] >> 4] << 8 | - machfb_mouse_pointer_lut[ - machfb_mouse_pointer_bits[i][j] & 0x0f]; - if (sc->sc_flags & MACHFB_SWAP) - *(p++) = bswap16(v); - else - *(p++) = v; - } - } - - return (0); -} - -static int -machfb_get_memsize(struct machfb_softc *sc) -{ - int tmp, memsize; - const int mem_tab[] = { - 512, 1024, 2048, 4096, 6144, 8192, 12288, 16384 - }; - - tmp = regr(sc, MEM_CNTL); -#ifdef MACHFB_DEBUG - printf("memcntl=0x%08x\n", tmp); -#endif - if (sc->sc_flags & MACHFB_DSP) { - tmp &= 0x0000000f; - if (tmp < 8) - memsize = (tmp + 1) * 512; - else if (tmp < 12) - memsize = (tmp - 3) * 1024; - else - memsize = (tmp - 7) * 2048; - } else - memsize = mem_tab[tmp & 0x07]; - - return (memsize); -} - -static void -machfb_reset_engine(struct machfb_softc *sc) -{ - - /* Reset engine.*/ - regw(sc, GEN_TEST_CNTL, regr(sc, GEN_TEST_CNTL) & ~GUI_ENGINE_ENABLE); - - /* Enable engine. */ - regw(sc, GEN_TEST_CNTL, regr(sc, GEN_TEST_CNTL) | GUI_ENGINE_ENABLE); - - /* - * Ensure engine is not locked up by clearing any FIFO or - * host errors. - */ - regw(sc, BUS_CNTL, regr(sc, BUS_CNTL) | BUS_HOST_ERR_ACK | - BUS_FIFO_ERR_ACK); -} - -static void -machfb_init_engine(struct machfb_softc *sc) -{ - uint32_t pitch_value; - - pitch_value = sc->sc_width; - - if (sc->sc_depth == 24) - pitch_value *= 3; - - machfb_reset_engine(sc); - - wait_for_fifo(sc, 14); - - regw(sc, CONTEXT_MASK, 0xffffffff); - - regw(sc, DST_OFF_PITCH, (pitch_value / 8) << 22); - - regw(sc, DST_Y_X, 0); - regw(sc, DST_HEIGHT, 0); - regw(sc, DST_BRES_ERR, 0); - regw(sc, DST_BRES_INC, 0); - regw(sc, DST_BRES_DEC, 0); - - regw(sc, DST_CNTL, DST_LAST_PEL | DST_X_LEFT_TO_RIGHT | - DST_Y_TOP_TO_BOTTOM); - - regw(sc, SRC_OFF_PITCH, (pitch_value / 8) << 22); - - regw(sc, SRC_Y_X, 0); - regw(sc, SRC_HEIGHT1_WIDTH1, 1); - regw(sc, SRC_Y_X_START, 0); - regw(sc, SRC_HEIGHT2_WIDTH2, 1); - - regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); - - wait_for_fifo(sc, 13); - regw(sc, HOST_CNTL, 0); - - regw(sc, PAT_REG0, 0); - regw(sc, PAT_REG1, 0); - regw(sc, PAT_CNTL, 0); - - regw(sc, SC_LEFT, 0); - regw(sc, SC_TOP, 0); - regw(sc, SC_BOTTOM, sc->sc_height - 1); - regw(sc, SC_RIGHT, pitch_value - 1); - - regw(sc, DP_BKGD_CLR, 0); - regw(sc, DP_FRGD_CLR, 0xffffffff); - regw(sc, DP_WRITE_MASK, 0xffffffff); - regw(sc, DP_MIX, (MIX_SRC << 16) | MIX_DST); - - regw(sc, DP_SRC, FRGD_SRC_FRGD_CLR); - - wait_for_fifo(sc, 3); - regw(sc, CLR_CMP_CLR, 0); - regw(sc, CLR_CMP_MASK, 0xffffffff); - regw(sc, CLR_CMP_CNTL, 0); - - wait_for_fifo(sc, 2); - switch (sc->sc_depth) { - case 8: - regw(sc, DP_PIX_WIDTH, HOST_8BPP | SRC_8BPP | DST_8BPP); - regw(sc, DP_CHAIN_MASK, DP_CHAIN_8BPP); - regw(sc, DAC_CNTL, regr(sc, DAC_CNTL) | DAC_8BIT_EN); - break; -#if 0 - case 32: - regw(sc, DP_PIX_WIDTH, HOST_32BPP | SRC_32BPP | DST_32BPP); - regw(sc, DP_CHAIN_MASK, DP_CHAIN_32BPP); - regw(sc, DAC_CNTL, regr(sc, DAC_CNTL) | DAC_8BIT_EN); - break; -#endif - } - - wait_for_fifo(sc, 2); - regw(sc, CRTC_INT_CNTL, regr(sc, CRTC_INT_CNTL) & ~0x20); - regw(sc, GUI_TRAJ_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM); - - wait_for_idle(sc); -} - -#if 0 -static void -machfb_adjust_frame(struct machfb_softc *sc, int x, int y) -{ - int offset; - - offset = ((x + y * sc->sc_width) * (sc->sc_depth >> 3)) >> 3; - - regw(sc, CRTC_OFF_PITCH, (regr(sc, CRTC_OFF_PITCH) & 0xfff00000) | - offset); -} -#endif - -static void -machfb_shutdown_final(void *v) -{ - struct machfb_softc *sc = v; - - machfb_cursor_enable(sc, 0); - /* - * In case this is the console set the cursor of the stdout - * instance to the start of the last line so OFW output ends - * up beneath what FreeBSD left on the screen. - */ - if (sc->sc_flags & MACHFB_CONSOLE) { - OF_interpret("stdout @ is my-self 0 to column#", 0); - OF_interpret("stdout @ is my-self #lines 1 - to line#", 0); - } -} - -static void -machfb_shutdown_reset(void *v) -{ - struct machfb_softc *sc = v; - - machfb_blank_display(&sc->sc_va, V_DISPLAY_STAND_BY); -} diff --git a/sys/dev/fb/machfbreg.h b/sys/dev/fb/machfbreg.h deleted file mode 100644 index 8f3174656bb..00000000000 --- a/sys/dev/fb/machfbreg.h +++ /dev/null @@ -1,457 +0,0 @@ -/*- - * Copyright 1992,1993,1994,1995,1996,1997 by Kevin E. Martin, Chapel Hill, North Carolina. - * - * Permission to use, copy, modify, distribute, and sell this software and - * its documentation for any purpose is hereby granted without fee, - * provided that the above copyright notice appear in all copies and that - * both that copyright notice and this permission notice appear in - * supporting documentation, and that the name of Kevin E. Martin not be - * used in advertising or publicity pertaining to distribution of the - * software without specific, written prior permission. Kevin E. Martin - * makes no representations about the suitability of this software for any - * purpose. It is provided "as is" without express or implied warranty. - * - * KEVIN E. MARTIN, RICKARD E. FAITH, AND TIAGO GONS DISCLAIM ALL - * WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING ALL IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL THE - * AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR - * ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, - * WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, - * ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS - * SOFTWARE. - * - * Modified for the Mach-8 by Rickard E. Faith (faith@cs.unc.edu) - * Modified for the Mach32 by Kevin E. Martin (martin@cs.unc.edu) - * Modified for the Mach64 by Kevin E. Martin (martin@cs.unc.edu) - * - * from: NetBSD: machfbreg.h,v 1.1 2002/10/24 18:15:57 junyoung Exp - * - */ - -#ifndef _DEV_FB_MACHFB_H_ -#define _DEV_FB_MACHFB_H_ - -/* NON-GUI MEMORY MAPPED Registers - expressed in BYTE offsets */ - -#define CRTC_H_TOTAL_DISP 0x0000 /* Dword offset 00 */ -#define CRTC_H_SYNC_STRT_WID 0x0004 /* Dword offset 01 */ -#define CRTC_V_TOTAL_DISP 0x0008 /* Dword offset 02 */ -#define CRTC_V_SYNC_STRT_WID 0x000C /* Dword offset 03 */ -#define CRTC_VLINE_CRNT_VLINE 0x0010 /* Dword offset 04 */ -#define CRTC_OFF_PITCH 0x0014 /* Dword offset 05 */ -#define CRTC_INT_CNTL 0x0018 /* Dword offset 06 */ -#define CRTC_GEN_CNTL 0x001C /* Dword offset 07 */ - -#define DSP_CONFIG 0x0020 /* Dword offset 08 */ -#define DSP_ON_OFF 0x0024 /* Dword offset 09 */ - -#define SHARED_CNTL 0x0038 /* Dword offset 0E */ - -#define OVR_CLR 0x0040 /* Dword offset 10 */ -#define OVR_WID_LEFT_RIGHT 0x0044 /* Dword offset 11 */ -#define OVR_WID_TOP_BOTTOM 0x0048 /* Dword offset 12 */ - -#define CUR_CLR0 0x0060 /* Dword offset 18 */ -#define CUR_CLR1 0x0064 /* Dword offset 19 */ -#define CUR_OFFSET 0x0068 /* Dword offset 1A */ -#define CUR_HORZ_VERT_POSN 0x006C /* Dword offset 1B */ -#define CUR_HORZ_VERT_OFF 0x0070 /* Dword offset 1C */ - -#define HW_DEBUG 0x007C /* Dword offset 1F */ - -#define SCRATCH_REG0 0x0080 /* Dword offset 20 */ -#define SCRATCH_REG1 0x0084 /* Dword offset 21 */ - -#define CLOCK_CNTL 0x0090 /* Dword offset 24 */ - -#define BUS_CNTL 0x00A0 /* Dword offset 28 */ - -#define LCD_INDEX 0x00A4 /* Dword offset 29 (LTPro) */ -#define LCD_DATA 0x00A8 /* Dword offset 2A (LTPro) */ - -#define MEM_CNTL 0x00B0 /* Dword offset 2C */ - -#define MEM_VGA_WP_SEL 0x00B4 /* Dword offset 2D */ -#define MEM_VGA_RP_SEL 0x00B8 /* Dword offset 2E */ - -#define DAC_REGS 0x00C0 /* Dword offset 30 */ -#define DAC_WINDEX 0x00C0 /* Dword offset 30 */ -#define DAC_DATA 0x00C1 /* Dword offset 30 */ -#define DAC_MASK 0x00C2 /* Dword offset 30 */ -#define DAC_RINDEX 0x00C3 /* Dword offset 30 */ -#define DAC_CNTL 0x00C4 /* Dword offset 31 */ - -#define HORZ_STRETCHING 0x00C8 /* Dword offset 32 (LT) */ -#define VERT_STRETCHING 0x00CC /* Dword offset 33 (LT) */ - -#define GEN_TEST_CNTL 0x00D0 /* Dword offset 34 */ - -#define LCD_GEN_CNTL 0x00D4 /* Dword offset 35 (LT) */ -#define POWER_MANAGEMENT 0x00D8 /* Dword offset 36 (LT) */ - -#define CONFIG_CNTL 0x00DC /* Dword offset 37 (CT, ET, VT) */ -#define CONFIG_CHIP_ID 0x00E0 /* Dword offset 38 */ -#define CONFIG_STAT0 0x00E4 /* Dword offset 39 */ -#define CONFIG_STAT1 0x00E8 /* Dword offset 3A */ - - -/* GUI MEMORY MAPPED Registers */ - -#define DST_OFF_PITCH 0x0100 /* Dword offset 40 */ -#define DST_X 0x0104 /* Dword offset 41 */ -#define DST_Y 0x0108 /* Dword offset 42 */ -#define DST_Y_X 0x010C /* Dword offset 43 */ -#define DST_WIDTH 0x0110 /* Dword offset 44 */ -#define DST_HEIGHT 0x0114 /* Dword offset 45 */ -#define DST_HEIGHT_WIDTH 0x0118 /* Dword offset 46 */ -#define DST_X_WIDTH 0x011C /* Dword offset 47 */ -#define DST_BRES_LNTH 0x0120 /* Dword offset 48 */ -#define DST_BRES_ERR 0x0124 /* Dword offset 49 */ -#define DST_BRES_INC 0x0128 /* Dword offset 4A */ -#define DST_BRES_DEC 0x012C /* Dword offset 4B */ -#define DST_CNTL 0x0130 /* Dword offset 4C */ - -#define SRC_OFF_PITCH 0x0180 /* Dword offset 60 */ -#define SRC_X 0x0184 /* Dword offset 61 */ -#define SRC_Y 0x0188 /* Dword offset 62 */ -#define SRC_Y_X 0x018C /* Dword offset 63 */ -#define SRC_WIDTH1 0x0190 /* Dword offset 64 */ -#define SRC_HEIGHT1 0x0194 /* Dword offset 65 */ -#define SRC_HEIGHT1_WIDTH1 0x0198 /* Dword offset 66 */ -#define SRC_X_START 0x019C /* Dword offset 67 */ -#define SRC_Y_START 0x01A0 /* Dword offset 68 */ -#define SRC_Y_X_START 0x01A4 /* Dword offset 69 */ -#define SRC_WIDTH2 0x01A8 /* Dword offset 6A */ -#define SRC_HEIGHT2 0x01AC /* Dword offset 6B */ -#define SRC_HEIGHT2_WIDTH2 0x01B0 /* Dword offset 6C */ -#define SRC_CNTL 0x01B4 /* Dword offset 6D */ - -#define HOST_DATA0 0x0200 /* Dword offset 80 */ -#define HOST_DATA1 0x0204 /* Dword offset 81 */ -#define HOST_DATA2 0x0208 /* Dword offset 82 */ -#define HOST_DATA3 0x020C /* Dword offset 83 */ -#define HOST_DATA4 0x0210 /* Dword offset 84 */ -#define HOST_DATA5 0x0214 /* Dword offset 85 */ -#define HOST_DATA6 0x0218 /* Dword offset 86 */ -#define HOST_DATA7 0x021C /* Dword offset 87 */ -#define HOST_DATA8 0x0220 /* Dword offset 88 */ -#define HOST_DATA9 0x0224 /* Dword offset 89 */ -#define HOST_DATAA 0x0228 /* Dword offset 8A */ -#define HOST_DATAB 0x022C /* Dword offset 8B */ -#define HOST_DATAC 0x0230 /* Dword offset 8C */ -#define HOST_DATAD 0x0234 /* Dword offset 8D */ -#define HOST_DATAE 0x0238 /* Dword offset 8E */ -#define HOST_DATAF 0x023C /* Dword offset 8F */ -#define HOST_CNTL 0x0240 /* Dword offset 90 */ - -#define PAT_REG0 0x0280 /* Dword offset A0 */ -#define PAT_REG1 0x0284 /* Dword offset A1 */ -#define PAT_CNTL 0x0288 /* Dword offset A2 */ - -#define SC_LEFT 0x02A0 /* Dword offset A8 */ -#define SC_RIGHT 0x02A4 /* Dword offset A9 */ -#define SC_LEFT_RIGHT 0x02A8 /* Dword offset AA */ -#define SC_TOP 0x02AC /* Dword offset AB */ -#define SC_BOTTOM 0x02B0 /* Dword offset AC */ -#define SC_TOP_BOTTOM 0x02B4 /* Dword offset AD */ - -#define DP_BKGD_CLR 0x02C0 /* Dword offset B0 */ -#define DP_FRGD_CLR 0x02C4 /* Dword offset B1 */ -#define DP_WRITE_MASK 0x02C8 /* Dword offset B2 */ -#define DP_CHAIN_MASK 0x02CC /* Dword offset B3 */ -#define DP_PIX_WIDTH 0x02D0 /* Dword offset B4 */ -#define DP_MIX 0x02D4 /* Dword offset B5 */ -#define DP_SRC 0x02D8 /* Dword offset B6 */ - -#define CLR_CMP_CLR 0x0300 /* Dword offset C0 */ -#define CLR_CMP_MASK 0x0304 /* Dword offset C1 */ -#define CLR_CMP_CNTL 0x0308 /* Dword offset C2 */ - -#define FIFO_STAT 0x0310 /* Dword offset C4 */ - -#define CONTEXT_MASK 0x0320 /* Dword offset C8 */ -#define CONTEXT_LOAD_CNTL 0x032C /* Dword offset CB */ - -#define GUI_TRAJ_CNTL 0x0330 /* Dword offset CC */ -#define GUI_STAT 0x0338 /* Dword offset CE */ - - -/* CRTC control values */ - -#define CRTC_HSYNC_NEG 0x00200000 -#define CRTC_VSYNC_NEG 0x00200000 - -#define CRTC_DBL_SCAN_EN 0x00000001 -#define CRTC_INTERLACE_EN 0x00000002 -#define CRTC_HSYNC_DIS 0x00000004 -#define CRTC_VSYNC_DIS 0x00000008 -#define CRTC_CSYNC_EN 0x00000010 -#define CRTC_PIX_BY_2_EN 0x00000020 -#define CRTC_DISPLAY_DIS 0x00000040 -#define CRTC_VGA_XOVERSCAN 0x00000080 - -#define CRTC_PIX_WIDTH 0x00000700 -#define CRTC_PIX_WIDTH_4BPP 0x00000100 -#define CRTC_PIX_WIDTH_8BPP 0x00000200 -#define CRTC_PIX_WIDTH_15BPP 0x00000300 -#define CRTC_PIX_WIDTH_16BPP 0x00000400 -#define CRTC_PIX_WIDTH_24BPP 0x00000500 -#define CRTC_PIX_WIDTH_32BPP 0x00000600 - -#define CRTC_BYTE_PIX_ORDER 0x00000800 -#define CRTC_PIX_ORDER_MSN_LSN 0x00000000 -#define CRTC_PIX_ORDER_LSN_MSN 0x00000800 - -#define CRTC_FIFO_LWM 0x000f0000 -#define CRTC_LOCK_REGS 0x00400000 -#define CRTC_EXT_DISP_EN 0x01000000 -#define CRTC_EN 0x02000000 -#define CRTC_DISP_REQ_EN 0x04000000 -#define CRTC_VGA_LINEAR 0x08000000 -#define CRTC_VSYNC_FALL_EDGE 0x10000000 -#define CRTC_VGA_TEXT_132 0x20000000 -#define CRTC_CNT_EN 0x40000000 -#define CRTC_CUR_B_TEST 0x80000000 - -#define CRTC_CRNT_VLINE 0x07f00000 -#define CRTC_VBLANK 0x00000001 - -/* DAC control values */ - -#define DAC_EXT_SEL_RS2 0x01 -#define DAC_EXT_SEL_RS3 0x02 -#define DAC_8BIT_EN 0x00000100 -#define DAC_PIX_DLY_MASK 0x00000600 -#define DAC_PIX_DLY_0NS 0x00000000 -#define DAC_PIX_DLY_2NS 0x00000200 -#define DAC_PIX_DLY_4NS 0x00000400 -#define DAC_BLANK_ADJ_MASK 0x00001800 -#define DAC_BLANK_ADJ_0 0x00000000 -#define DAC_BLANK_ADJ_1 0x00000800 -#define DAC_BLANK_ADJ_2 0x00001000 - - -/* Mix control values */ - -#define MIX_NOT_DST 0x0000 -#define MIX_0 0x0001 -#define MIX_1 0x0002 -#define MIX_DST 0x0003 -#define MIX_NOT_SRC 0x0004 -#define MIX_XOR 0x0005 -#define MIX_XNOR 0x0006 -#define MIX_SRC 0x0007 -#define MIX_NAND 0x0008 -#define MIX_NOT_SRC_OR_DST 0x0009 -#define MIX_SRC_OR_NOT_DST 0x000a -#define MIX_OR 0x000b -#define MIX_AND 0x000c -#define MIX_SRC_AND_NOT_DST 0x000d -#define MIX_NOT_SRC_AND_DST 0x000e -#define MIX_NOR 0x000f - -/* Maximum engine dimensions */ -#define ENGINE_MIN_X 0 -#define ENGINE_MIN_Y 0 -#define ENGINE_MAX_X 4095 -#define ENGINE_MAX_Y 16383 - -/* Mach64 engine bit constants - these are typically ORed together */ - -/* HW_DEBUG register constants */ -/* For RagePro only... */ -#define AUTO_FF_DIS 0x000001000 -#define AUTO_BLKWRT_DIS 0x000002000 - -/* BUS_CNTL register constants */ -#define BUS_FIFO_ERR_ACK 0x00200000 -#define BUS_HOST_ERR_ACK 0x00800000 -#define BUS_APER_REG_DIS 0x00000010 - -/* GEN_TEST_CNTL register constants */ -#define GEN_OVR_OUTPUT_EN 0x20 -#define HWCURSOR_ENABLE 0x80 -#define GUI_ENGINE_ENABLE 0x100 -#define BLOCK_WRITE_ENABLE 0x200 - -/* DSP_CONFIG register constants */ -#define DSP_XCLKS_PER_QW 0x00003fff -#define DSP_LOOP_LATENCY 0x000f0000 -#define DSP_PRECISION 0x00700000 - -/* DSP_ON_OFF register constants */ -#define DSP_OFF 0x000007ff -#define DSP_ON 0x07ff0000 - -/* SHARED_CNTL register constants */ -#define CTD_FIFO5 0x01000000 - -/* CLOCK_CNTL register constants */ -#define CLOCK_SEL 0x0f -#define CLOCK_DIV 0x30 -#define CLOCK_DIV1 0x00 -#define CLOCK_DIV2 0x10 -#define CLOCK_DIV4 0x20 -#define CLOCK_STROBE 0x40 -#define PLL_WR_EN 0x02 - -/* PLL registers */ -#define PLL_MACRO_CNTL 0x01 -#define PLL_REF_DIV 0x02 -#define PLL_GEN_CNTL 0x03 -#define MCLK_FB_DIV 0x04 -#define PLL_VCLK_CNTL 0x05 -#define VCLK_POST_DIV 0x06 -#define VCLK0_FB_DIV 0x07 -#define VCLK1_FB_DIV 0x08 -#define VCLK2_FB_DIV 0x09 -#define VCLK3_FB_DIV 0x0A -#define PLL_XCLK_CNTL 0x0B -#define PLL_TEST_CTRL 0x0E -#define PLL_TEST_COUNT 0x0F - -/* Memory types for CT, ET, VT, GT */ -#define DRAM 1 -#define EDO_DRAM 2 -#define PSEUDO_EDO 3 -#define SDRAM 4 -#define SGRAM 5 -#define SGRAM32 6 - -#define DAC_INTERNAL 0x00 -#define DAC_IBMRGB514 0x01 -#define DAC_ATI68875 0x02 -#define DAC_TVP3026_A 0x72 -#define DAC_BT476 0x03 -#define DAC_BT481 0x04 -#define DAC_ATT20C491 0x14 -#define DAC_SC15026 0x24 -#define DAC_MU9C1880 0x34 -#define DAC_IMSG174 0x44 -#define DAC_ATI68860_B 0x05 -#define DAC_ATI68860_C 0x15 -#define DAC_TVP3026_B 0x75 -#define DAC_STG1700 0x06 -#define DAC_ATT498 0x16 -#define DAC_STG1702 0x07 -#define DAC_SC15021 0x17 -#define DAC_ATT21C498 0x27 -#define DAC_STG1703 0x37 -#define DAC_CH8398 0x47 -#define DAC_ATT20C408 0x57 - -#define CLK_ATI18818_0 0 -#define CLK_ATI18818_1 1 -#define CLK_STG1703 2 -#define CLK_CH8398 3 -#define CLK_INTERNAL 4 -#define CLK_ATT20C408 5 -#define CLK_IBMRGB514 6 - -/* DST_CNTL register constants */ -#define DST_X_RIGHT_TO_LEFT 0 -#define DST_X_LEFT_TO_RIGHT 1 -#define DST_Y_BOTTOM_TO_TOP 0 -#define DST_Y_TOP_TO_BOTTOM 2 -#define DST_X_MAJOR 0 -#define DST_Y_MAJOR 4 -#define DST_X_TILE 8 -#define DST_Y_TILE 0x10 -#define DST_LAST_PEL 0x20 -#define DST_POLYGON_ENABLE 0x40 -#define DST_24_ROTATION_ENABLE 0x80 - -/* SRC_CNTL register constants */ -#define SRC_PATTERN_ENABLE 1 -#define SRC_ROTATION_ENABLE 2 -#define SRC_LINEAR_ENABLE 4 -#define SRC_BYTE_ALIGN 8 -#define SRC_LINE_X_RIGHT_TO_LEFT 0 -#define SRC_LINE_X_LEFT_TO_RIGHT 0x10 - -/* HOST_CNTL register constants */ -#define HOST_BYTE_ALIGN 1 - -/* DP_CHAIN_MASK register constants */ -#define DP_CHAIN_4BPP 0x8888 -#define DP_CHAIN_7BPP 0xD2D2 -#define DP_CHAIN_8BPP 0x8080 -#define DP_CHAIN_8BPP_RGB 0x9292 -#define DP_CHAIN_15BPP 0x4210 -#define DP_CHAIN_16BPP 0x8410 -#define DP_CHAIN_24BPP 0x8080 -#define DP_CHAIN_32BPP 0x8080 - -/* DP_PIX_WIDTH register constants */ -#define DST_1BPP 0 -#define DST_4BPP 1 -#define DST_8BPP 2 -#define DST_15BPP 3 -#define DST_16BPP 4 -#define DST_32BPP 6 -#define SRC_1BPP 0 -#define SRC_4BPP 0x100 -#define SRC_8BPP 0x200 -#define SRC_15BPP 0x300 -#define SRC_16BPP 0x400 -#define SRC_32BPP 0x600 -#define HOST_1BPP 0 -#define HOST_4BPP 0x10000 -#define HOST_8BPP 0x20000 -#define HOST_15BPP 0x30000 -#define HOST_16BPP 0x40000 -#define HOST_32BPP 0x60000 -#define BYTE_ORDER_MSB_TO_LSB 0 -#define BYTE_ORDER_LSB_TO_MSB 0x1000000 - -/* DP_SRC register constants */ -#define BKGD_SRC_BKGD_CLR 0 -#define BKGD_SRC_FRGD_CLR 1 -#define BKGD_SRC_HOST 2 -#define BKGD_SRC_BLIT 3 -#define BKGD_SRC_PATTERN 4 -#define FRGD_SRC_BKGD_CLR 0 -#define FRGD_SRC_FRGD_CLR 0x100 -#define FRGD_SRC_HOST 0x200 -#define FRGD_SRC_BLIT 0x300 -#define FRGD_SRC_PATTERN 0x400 -#define MONO_SRC_ONE 0 -#define MONO_SRC_PATTERN 0x10000 -#define MONO_SRC_HOST 0x20000 -#define MONO_SRC_BLIT 0x30000 - -/* PCI IDs */ -#define ATI_VENDOR 0x1002 -#define ATI_MACH64_CT 0x4354 /* Mach64 CT */ -#define ATI_RAGE_PRO_AGP 0x4742 /* 3D Rage Pro (AGP) */ -#define ATI_RAGE_PRO_AGP1X 0x4744 /* 3D Rage Pro (AGP 1x) */ -#define ATI_RAGE_PRO_PCI_B 0x4749 /* 3D Rage Pro Turbo */ -#define ATI_RAGE_XC_PCI66 0x474c /* Rage XC (PCI66) */ -#define ATI_RAGE_XL_AGP 0x474d /* Rage XL (AGP) */ -#define ATI_RAGE_XC_AGP 0x474e /* Rage XC (AGP) */ -#define ATI_RAGE_XL_PCI66 0x474f /* Rage XL (PCI66) */ -#define ATI_RAGE_PRO_PCI_P 0x4750 /* 3D Rage Pro */ -#define ATI_RAGE_PRO_PCI_L 0x4751 /* 3D Rage Pro (limited 3D) */ -#define ATI_RAGE_XL_PCI 0x4752 /* Rage XL */ -#define ATI_RAGE_XC_PCI 0x4753 /* Rage XC */ -#define ATI_RAGE_II 0x4754 /* 3D Rage I/II */ -#define ATI_RAGE_IIP 0x4755 /* 3D Rage II+ */ -#define ATI_RAGE_IIC_PCI 0x4756 /* 3D Rage IIC */ -#define ATI_RAGE_IIC_AGP_B 0x4757 /* 3D Rage IIC (AGP) */ -#define ATI_RAGE_IIC_AGP_P 0x475a /* 3D Rage IIC (AGP) */ -#define ATI_RAGE_LT_PRO_AGP 0x4c42 /* 3D Rage LT Pro (AGP 133MHz) */ -#define ATI_RAGE_MOB_M3_PCI 0x4c45 /* Rage Mobility M3 */ -#define ATI_RAGE_MOB_M3_AGP 0x4c46 /* Rage Mobility M3 (AGP) */ -#define ATI_RAGE_LT 0x4c47 /* 3D Rage LT */ -#define ATI_RAGE_LT_PRO_PCI 0x4c49 /* 3D Rage LT Pro */ -#define ATI_RAGE_MOBILITY 0x4c4d /* Rage Mobility */ -#define ATI_RAGE_L_MOBILITY 0x4c4e /* Rage L Mobility */ -#define ATI_RAGE_LT_PRO 0x4c50 /* 3D Rage LT Pro */ -#define ATI_RAGE_LT_PRO2 0x4c51 /* 3D Rage LT Pro */ -#define ATI_RAGE_MOB_M1_PCI 0x4c52 /* Rage Mobility M1 (PCI) */ -#define ATI_RAGE_L_MOB_M1_PCI 0x4c53 /* Rage L Mobility (PCI) */ -#define ATI_MACH64_VT 0x5654 /* Mach64 VT */ -#define ATI_MACH64_VTB 0x5655 /* Mach64 VTB */ -#define ATI_MACH64_VT4 0x5656 /* Mach64 VT4 */ - -#endif /* !_DEV_FB_MACHFB_H_ */ diff --git a/sys/dev/fdc/fdc_pccard.c b/sys/dev/fdc/fdc_pccard.c deleted file mode 100644 index 103474f4826..00000000000 --- a/sys/dev/fdc/fdc_pccard.c +++ /dev/null @@ -1,146 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2004-2005 M. Warner Losh. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include "pccarddevs.h" - -static int fdc_pccard_probe(device_t); -static int fdc_pccard_attach(device_t); - -static const struct pccard_product fdc_pccard_products[] = { - PCMCIA_CARD(YEDATA, EXTERNAL_FDD), - { NULL } -}; - -static int -fdc_pccard_alloc_resources(device_t dev, struct fdc_data *fdc) -{ - struct resource *res; - int rid, i; - - rid = 0; - res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, RF_ACTIVE); - if (res == NULL) { - device_printf(dev, "cannot alloc I/O port range\n"); - return (ENXIO); - } - for (i = 0; i < FDC_MAXREG; i++) { - fdc->resio[i] = res; - fdc->ridio[i] = rid; - fdc->ioff[i] = i; - fdc->ioh[i] = rman_get_bushandle(res); - } - fdc->iot = rman_get_bustag(res); - - fdc->rid_irq = 0; - fdc->res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &fdc->rid_irq, - RF_ACTIVE | RF_SHAREABLE); - if (fdc->res_irq == NULL) { - device_printf(dev, "cannot reserve interrupt line\n"); - return (ENXIO); - } - return (0); -} - -static int -fdc_pccard_probe(device_t dev) -{ - if (pccard_product_lookup(dev, fdc_pccard_products, - sizeof(fdc_pccard_products[0]), NULL) != NULL) { - device_set_desc(dev, "PC Card Floppy"); - return (0); - } - return (ENXIO); -} - -static int -fdc_pccard_attach(device_t dev) -{ - int error; - struct fdc_data *fdc; - device_t child; - - fdc = device_get_softc(dev); - fdc->flags = FDC_NODMA | FDC_NOFAST; - fdc->fdct = FDC_NE765; - error = fdc_pccard_alloc_resources(dev, fdc); - if (error == 0) - error = fdc_attach(dev); - if (error == 0) { - child = fdc_add_child(dev, "fd", -1); - device_set_flags(child, 0x24); - error = bus_generic_attach(dev); - } - if (error == 0) { - gone_in_dev(dev, 13, "pccard removed"); - fdc_start_worker(dev); - } else - fdc_release_resources(fdc); - return (error); -} - -static device_method_t fdc_pccard_methods[] = { - /* Device interface */ - DEVMETHOD(device_probe, fdc_pccard_probe), - DEVMETHOD(device_attach, fdc_pccard_attach), - DEVMETHOD(device_detach, fdc_detach), - DEVMETHOD(device_shutdown, bus_generic_shutdown), - DEVMETHOD(device_suspend, bus_generic_suspend), - DEVMETHOD(device_resume, bus_generic_resume), - - /* Bus interface */ - DEVMETHOD(bus_print_child, fdc_print_child), - DEVMETHOD(bus_read_ivar, fdc_read_ivar), - DEVMETHOD(bus_write_ivar, fdc_write_ivar), - /* Our children never use any other bus interface methods. */ - - { 0, 0 } -}; - -static driver_t fdc_pccard_driver = { - "fdc", - fdc_pccard_methods, - sizeof(struct fdc_data) -}; - -DRIVER_MODULE(fdc, pccard, fdc_pccard_driver, fdc_devclass, 0, 0); -PCCARD_PNP_INFO(fdc_pccard_products); diff --git a/sys/dev/gem/if_gem_sbus.c b/sys/dev/gem/if_gem_sbus.c deleted file mode 100644 index 7adbeb8fba6..00000000000 --- a/sys/dev/gem/if_gem_sbus.c +++ /dev/null @@ -1,209 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-NetBSD - * - * Copyright (C) 2001 Eduardo Horvath. - * Copyright (c) 2007 Marius Strobl - * All rights reserved. - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * from: NetBSD: if_gem_pci.c,v 1.7 2001/10/18 15:09:15 thorpej Exp - */ - -#include - -/* - * SBus bindings for Sun GEM Ethernet controllers - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include - -#include -#include -#include - -#include - -#include -#include - -#include "miibus_if.h" - -static device_probe_t gem_sbus_probe; -static device_attach_t gem_sbus_attach; -static device_detach_t gem_sbus_detach; -static device_suspend_t gem_sbus_suspend; -static device_resume_t gem_sbus_resume; - -static device_method_t gem_sbus_methods[] = { - /* Device interface */ - DEVMETHOD(device_probe, gem_sbus_probe), - DEVMETHOD(device_attach, gem_sbus_attach), - DEVMETHOD(device_detach, gem_sbus_detach), - DEVMETHOD(device_suspend, gem_sbus_suspend), - DEVMETHOD(device_resume, gem_sbus_resume), - /* Use the suspend handler here, it is all that is required. */ - DEVMETHOD(device_shutdown, gem_sbus_suspend), - - /* MII interface */ - DEVMETHOD(miibus_readreg, gem_mii_readreg), - DEVMETHOD(miibus_writereg, gem_mii_writereg), - DEVMETHOD(miibus_statchg, gem_mii_statchg), - - DEVMETHOD_END -}; - -static driver_t gem_sbus_driver = { - "gem", - gem_sbus_methods, - sizeof(struct gem_softc) -}; - -DRIVER_MODULE(gem, sbus, gem_sbus_driver, gem_devclass, 0, 0); -MODULE_DEPEND(gem, sbus, 1, 1, 1); -MODULE_DEPEND(gem, ether, 1, 1, 1); - -static int -gem_sbus_probe(device_t dev) -{ - - if (strcmp(ofw_bus_get_name(dev), "network") == 0 && - ofw_bus_get_compat(dev) != NULL && - strcmp(ofw_bus_get_compat(dev), "SUNW,sbus-gem") == 0) { - device_set_desc(dev, "Sun GEM Gigabit Ethernet"); - return (0); - } - - return (ENXIO); -} - -static struct resource_spec gem_sbus_res_spec[] = { - { SYS_RES_IRQ, 0, RF_SHAREABLE | RF_ACTIVE }, /* GEM_RES_INTR */ - { SYS_RES_MEMORY, 1, RF_ACTIVE }, /* GEM_RES_BANK1 */ - { SYS_RES_MEMORY, 0, RF_ACTIVE }, /* GEM_RES_BANK2 */ - { -1, 0 } -}; - -static int -gem_sbus_attach(device_t dev) -{ - struct gem_softc *sc; - int burst; - uint32_t val; - - sc = device_get_softc(dev); - sc->sc_variant = GEM_SUN_GEM; - sc->sc_dev = dev; - /* All known SBus models use a SERDES. */ - sc->sc_flags = GEM_SERDES; - - if (bus_alloc_resources(dev, gem_sbus_res_spec, sc->sc_res)) { - device_printf(dev, "failed to allocate resources\n"); - bus_release_resources(dev, gem_sbus_res_spec, sc->sc_res); - return (ENXIO); - } - - GEM_LOCK_INIT(sc, device_get_nameunit(dev)); - - OF_getetheraddr(dev, sc->sc_enaddr); - - burst = sbus_get_burstsz(dev); - val = GEM_SBUS_CFG_PARITY; - if ((burst & SBUS_BURST64_MASK) != 0) { - val |= GEM_SBUS_CFG_64BIT; - burst >>= SBUS_BURST64_SHIFT; - } - if ((burst & SBUS_BURST_64) != 0) - val |= GEM_SBUS_CFG_BURST_64; - else if ((burst & SBUS_BURST_32) != 0) - val |= GEM_SBUS_CFG_BURST_32; - else { - device_printf(dev, "unsupported burst size\n"); - goto fail; - } - /* Reset the SBus interface only. */ - (void)GEM_BANK2_READ_4(sc, GEM_SBUS_BIF_RESET); - DELAY(100); - GEM_BANK2_WRITE_4(sc, GEM_SBUS_CONFIG, val); - - if (gem_attach(sc) != 0) { - device_printf(dev, "could not be attached\n"); - goto fail; - } - - if (bus_setup_intr(dev, sc->sc_res[GEM_RES_INTR], INTR_TYPE_NET | - INTR_MPSAFE, NULL, gem_intr, sc, &sc->sc_ih) != 0) { - device_printf(dev, "failed to set up interrupt\n"); - gem_detach(sc); - goto fail; - } - return (0); - - fail: - GEM_LOCK_DESTROY(sc); - bus_release_resources(dev, gem_sbus_res_spec, sc->sc_res); - return (ENXIO); -} - -static int -gem_sbus_detach(device_t dev) -{ - struct gem_softc *sc; - - sc = device_get_softc(dev); - bus_teardown_intr(dev, sc->sc_res[GEM_RES_INTR], sc->sc_ih); - gem_detach(sc); - GEM_LOCK_DESTROY(sc); - bus_release_resources(dev, gem_sbus_res_spec, sc->sc_res); - return (0); -} - -static int -gem_sbus_suspend(device_t dev) -{ - - gem_suspend(device_get_softc(dev)); - return (0); -} - -static int -gem_sbus_resume(device_t dev) -{ - - gem_resume(device_get_softc(dev)); - return (0); -} diff --git a/sys/dev/hwpmc/hwpmc_sparc64.c b/sys/dev/hwpmc/hwpmc_sparc64.c deleted file mode 100644 index 0f2ef8b42f9..00000000000 --- a/sys/dev/hwpmc/hwpmc_sparc64.c +++ /dev/null @@ -1,67 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2005, Joseph Koshy - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - */ - -#include - -#include -#include - -#include - -struct pmc_mdep * -pmc_md_initialize() -{ - return NULL; -} - -void -pmc_md_finalize(struct pmc_mdep *md) -{ - (void) md; -} - -int -pmc_save_kernel_callchain(uintptr_t *cc, int maxsamples, - struct trapframe *tf) -{ - (void) cc; - (void) maxsamples; - (void) tf; - return (0); -} - -int -pmc_save_user_callchain(uintptr_t *cc, int maxsamples, - struct trapframe *tf) -{ - (void) cc; - (void) maxsamples; - (void) tf; - return (0); -} diff --git a/sys/dev/hwpmc/hwpmc_xscale.h b/sys/dev/hwpmc/hwpmc_xscale.h deleted file mode 100644 index f2b5c19db82..00000000000 --- a/sys/dev/hwpmc/hwpmc_xscale.h +++ /dev/null @@ -1,71 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2009 Rui Paulo - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - */ - -#ifndef _DEV_HWPMC_XSCALE_H_ -#define _DEV_HWPMC_XSCALE_H_ - -#define XSCALE_PMC_CAPS (PMC_CAP_INTERRUPT | PMC_CAP_USER | \ - PMC_CAP_SYSTEM | PMC_CAP_EDGE | \ - PMC_CAP_THRESHOLD | PMC_CAP_READ | \ - PMC_CAP_WRITE | PMC_CAP_INVERT | \ - PMC_CAP_QUALIFIER) - - -#define XSCALE_PMNC_ENABLE 0x01 /* Enable all Counters */ -#define XSCALE_PMNC_PMNRESET 0x02 /* Performance Counter Reset */ -#define XSCALE_PMNC_CCNTRESET 0x04 /* Clock Counter Reset */ -#define XSCALE_PMNC_CCNTDIV 0x08 /* Clock Counter Divider */ - -#define XSCALE_INTEN_CCNT 0x01 /* Enable Clock Counter Int. */ -#define XSCALE_INTEN_PMN0 0x02 /* Enable PMN0 Interrupts */ -#define XSCALE_INTEN_PMN1 0x04 /* Enable PMN1 Interrupts */ -#define XSCALE_INTEN_PMN2 0x08 /* Enable PMN2 Interrupts */ -#define XSCALE_INTEN_PMN3 0x10 /* Enable PMN3 Interrupts */ - -#define XSCALE_EVTSEL_EVT0_MASK 0x000000ff -#define XSCALE_EVTSEL_EVT1_MASK 0x0000ff00 -#define XSCALE_EVTSEL_EVT2_MASK 0x00ff0000 -#define XSCALE_EVTSEL_EVT3_MASK 0xff000000 - -#define XSCALE_FLAG_CCNT_OVERFLOW 0x01 -#define XSCALE_FLAG_PMN0_OVERFLOW 0x02 -#define XSCALE_FLAG_PMN1_OVERFLOW 0x04 -#define XSCALE_FLAG_PMN2_OVERFLOW 0x08 -#define XSCALE_FLAG_PMN3_OVERFLOW 0x10 - -#define XSCALE_RELOAD_COUNT_TO_PERFCTR_VALUE(R) (-(R)) -#define XSCALE_PERFCTR_VALUE_TO_RELOAD_COUNT(P) (-(P)) - -#ifdef _KERNEL -/* MD extension for 'struct pmc' */ -struct pmc_md_xscale_pmc { - uint32_t pm_xscale_evsel; -}; -#endif /* _KERNEL */ -#endif /* _DEV_HWPMC_XSCALE_H_ */ diff --git a/sys/dev/if_ndis/if_ndis_pccard.c b/sys/dev/if_ndis/if_ndis_pccard.c deleted file mode 100644 index 586d3f70bb6..00000000000 --- a/sys/dev/if_ndis/if_ndis_pccard.c +++ /dev/null @@ -1,336 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-4-Clause - * - * Copyright (c) 2003 - * Bill Paul . All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by Bill Paul. - * 4. Neither the name of the author nor the names of any co-contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - * THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include -#include - -#include - -#include -#include -#include -#include -#include -#include - -#include -#include "card_if.h" - -MODULE_DEPEND(ndis, pccard, 1, 1, 1); - -static int ndis_probe_pccard (device_t); -static int ndis_attach_pccard (device_t); -static int ndis_detach_pccard (device_t); -static struct resource_list *ndis_get_resource_list - (device_t, device_t); -static int ndis_devcompare (interface_type, - struct ndis_pccard_type *, device_t); -extern int ndisdrv_modevent (module_t, int, void *); -extern int ndis_attach (device_t); -extern int ndis_shutdown (device_t); -extern int ndis_detach (device_t); -extern int ndis_suspend (device_t); -extern int ndis_resume (device_t); - -extern unsigned char drv_data[]; - -static device_method_t ndis_methods[] = { - /* Device interface */ - DEVMETHOD(device_probe, ndis_probe_pccard), - DEVMETHOD(device_attach, ndis_attach_pccard), - DEVMETHOD(device_detach, ndis_detach_pccard), - DEVMETHOD(device_shutdown, ndis_shutdown), - DEVMETHOD(device_suspend, ndis_suspend), - DEVMETHOD(device_resume, ndis_resume), - - /* Bus interface. */ - - /* - * This is an awful kludge, but we need it becase pccard - * does not implement a bus_get_resource_list() method. - */ - - DEVMETHOD(bus_get_resource_list, ndis_get_resource_list), - - { 0, 0 } -}; - -static driver_t ndis_driver = { - "ndis", - ndis_methods, - sizeof(struct ndis_softc) -}; - -static devclass_t ndis_devclass; - -DRIVER_MODULE(ndis, pccard, ndis_driver, ndis_devclass, ndisdrv_modevent, 0); - -static int -ndis_devcompare(bustype, t, dev) - interface_type bustype; - struct ndis_pccard_type *t; - device_t dev; -{ - const char *prodstr, *vendstr; - int error; - - if (bustype != PCMCIABus) - return(FALSE); - - error = pccard_get_product_str(dev, &prodstr); - if (error) - return(FALSE); - error = pccard_get_vendor_str(dev, &vendstr); - if (error) - return(FALSE); - - while(t->ndis_name != NULL) { - if (strcasecmp(vendstr, t->ndis_vid) == 0 && - strcasecmp(prodstr, t->ndis_did) == 0) { - device_set_desc(dev, t->ndis_name); - return(TRUE); - } - t++; - } - - return(FALSE); -} - -/* - * Probe for an NDIS device. Check the PCI vendor and device - * IDs against our list and return a device name if we find a match. - */ -static int -ndis_probe_pccard(dev) - device_t dev; -{ - driver_object *drv; - struct drvdb_ent *db; - - drv = windrv_lookup(0, "PCCARD Bus"); - if (drv == NULL) - return(ENXIO); - - db = windrv_match((matchfuncptr)ndis_devcompare, dev); - - if (db != NULL) { - /* Create PDO for this device instance */ - windrv_create_pdo(drv, dev); - return(0); - } - - return(ENXIO); -} - -#define NDIS_AM_RID 3 - -static int -ndis_alloc_amem(struct ndis_softc *sc) -{ - int error, rid; - - rid = NDIS_AM_RID; - sc->ndis_res_am = bus_alloc_resource_anywhere(sc->ndis_dev, - SYS_RES_MEMORY, &rid, 0x1000, RF_ACTIVE); - - if (sc->ndis_res_am == NULL) { - device_printf(sc->ndis_dev, - "failed to allocate attribute memory\n"); - return(ENXIO); - } - sc->ndis_rescnt++; - resource_list_add(&sc->ndis_rl, SYS_RES_MEMORY, rid, - rman_get_start(sc->ndis_res_am), rman_get_end(sc->ndis_res_am), - rman_get_size(sc->ndis_res_am)); - - error = CARD_SET_MEMORY_OFFSET(device_get_parent(sc->ndis_dev), - sc->ndis_dev, rid, 0, NULL); - - if (error) { - device_printf(sc->ndis_dev, - "CARD_SET_MEMORY_OFFSET() returned 0x%x\n", error); - return(error); - } - - error = CARD_SET_RES_FLAGS(device_get_parent(sc->ndis_dev), - sc->ndis_dev, SYS_RES_MEMORY, rid, PCCARD_A_MEM_ATTR); - - if (error) { - device_printf(sc->ndis_dev, - "CARD_SET_RES_FLAGS() returned 0x%x\n", error); - return(error); - } - - sc->ndis_am_rid = rid; - - return(0); -} - -/* - * Attach the interface. Allocate softc structures, do ifmedia - * setup and ethernet/BPF attach. - */ -static int -ndis_attach_pccard(dev) - device_t dev; -{ - struct ndis_softc *sc; - int unit, error = 0, rid; - struct ndis_pccard_type *t; - int devidx = 0; - const char *prodstr, *vendstr; - struct drvdb_ent *db; - - sc = device_get_softc(dev); - unit = device_get_unit(dev); - sc->ndis_dev = dev; - - db = windrv_match((matchfuncptr)ndis_devcompare, dev); - if (db == NULL) - return (ENXIO); - sc->ndis_dobj = db->windrv_object; - sc->ndis_regvals = db->windrv_regvals; - resource_list_init(&sc->ndis_rl); - - sc->ndis_io_rid = 0; - sc->ndis_res_io = bus_alloc_resource_any(dev, SYS_RES_IOPORT, - &sc->ndis_io_rid, RF_ACTIVE); - if (sc->ndis_res_io == NULL) { - device_printf(dev, - "couldn't map iospace\n"); - error = ENXIO; - goto fail; - } - sc->ndis_rescnt++; - resource_list_add(&sc->ndis_rl, SYS_RES_IOPORT, sc->ndis_io_rid, - rman_get_start(sc->ndis_res_io), rman_get_end(sc->ndis_res_io), - rman_get_size(sc->ndis_res_io)); - - rid = 0; - sc->ndis_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, - RF_SHAREABLE | RF_ACTIVE); - if (sc->ndis_irq == NULL) { - device_printf(dev, - "couldn't map interrupt\n"); - error = ENXIO; - goto fail; - } - sc->ndis_rescnt++; - resource_list_add(&sc->ndis_rl, SYS_RES_IRQ, rid, - rman_get_start(sc->ndis_irq), rman_get_start(sc->ndis_irq), 1); - - sc->ndis_iftype = PCMCIABus; - - /* Figure out exactly which device we matched. */ - - t = db->windrv_devlist; - - error = pccard_get_product_str(dev, &prodstr); - if (error) - return(error); - error = pccard_get_vendor_str(dev, &vendstr); - if (error) - return(error); - - while(t->ndis_name != NULL) { - if (strcasecmp(vendstr, t->ndis_vid) == 0 && - strcasecmp(prodstr, t->ndis_did) == 0) - break; - t++; - devidx++; - } - - sc->ndis_devidx = devidx; - - error = ndis_alloc_amem(sc); - if (error) { - device_printf(dev, "failed to allocate attribute memory\n"); - goto fail; - } - - error = ndis_attach(dev); - if (error == 0) - gone_in_dev(dev, 13, "ndis removed"); - -fail: - return(error); -} - -static int -ndis_detach_pccard(device_t dev) -{ - struct ndis_softc *sc = device_get_softc(dev); - - (void) ndis_detach(dev); - - if (sc->ndis_res_am != NULL) - bus_release_resource(sc->ndis_dev, SYS_RES_MEMORY, - sc->ndis_am_rid, sc->ndis_res_am); - resource_list_free(&sc->ndis_rl); - - return (0); -} - -static struct resource_list * -ndis_get_resource_list(dev, child) - device_t dev; - device_t child; -{ - struct ndis_softc *sc; - - sc = device_get_softc(dev); - return (&sc->ndis_rl); -} diff --git a/sys/dev/isp/isp_sbus.c b/sys/dev/isp/isp_sbus.c deleted file mode 100644 index bdd13fd9081..00000000000 --- a/sys/dev/isp/isp_sbus.c +++ /dev/null @@ -1,700 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 1997-2006 by Matthew Jacob - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice immediately at the beginning of the file, without modification, - * this list of conditions, and the following disclaimer. - * 2. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ -/* - * SBus specific probe and attach routines for Qlogic ISP SCSI adapters. - * FreeBSD Version. - */ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include -#include -#include -#include -#include - -#include - -static uint32_t isp_sbus_rd_reg(ispsoftc_t *, int); -static void isp_sbus_wr_reg(ispsoftc_t *, int, uint32_t); -static void isp_sbus_run_isr(ispsoftc_t *); -static int isp_sbus_mbxdma(ispsoftc_t *); -static void isp_sbus_mbxdmafree(ispsoftc_t *); -static int isp_sbus_dmasetup(ispsoftc_t *, XS_T *, void *); -static void isp_sbus_dumpregs(ispsoftc_t *, const char *); - -static struct ispmdvec mdvec = { - isp_sbus_run_isr, - isp_sbus_rd_reg, - isp_sbus_wr_reg, - isp_sbus_mbxdma, - isp_sbus_dmasetup, - isp_common_dmateardown, - NULL, - isp_sbus_dumpregs, - NULL, - BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 -}; - -static int isp_sbus_probe (device_t); -static int isp_sbus_attach (device_t); -static int isp_sbus_detach (device_t); - - -#define ISP_SBD(isp) ((struct isp_sbussoftc *)isp)->sbus_dev -struct isp_sbussoftc { - ispsoftc_t sbus_isp; - device_t sbus_dev; - struct resource * regs; - void * irq; - int iqd; - int rgd; - void * ih; - int16_t sbus_poff[_NREG_BLKS]; - sdparam sbus_param; - struct isp_spi sbus_spi; - struct ispmdvec sbus_mdvec; -}; - - -static device_method_t isp_sbus_methods[] = { - /* Device interface */ - DEVMETHOD(device_probe, isp_sbus_probe), - DEVMETHOD(device_attach, isp_sbus_attach), - DEVMETHOD(device_detach, isp_sbus_detach), - { 0, 0 } -}; - -static driver_t isp_sbus_driver = { - "isp", isp_sbus_methods, sizeof (struct isp_sbussoftc) -}; -static devclass_t isp_devclass; -DRIVER_MODULE(isp, sbus, isp_sbus_driver, isp_devclass, 0, 0); -MODULE_DEPEND(isp, cam, 1, 1, 1); -MODULE_DEPEND(isp, firmware, 1, 1, 1); - -static int -isp_sbus_probe(device_t dev) -{ - int found = 0; - const char *name = ofw_bus_get_name(dev); - if (strcmp(name, "SUNW,isp") == 0 || - strcmp(name, "QLGC,isp") == 0 || - strcmp(name, "ptisp") == 0 || - strcmp(name, "PTI,ptisp") == 0) { - found++; - } - if (!found) - return (ENXIO); - - if (isp_announced == 0 && bootverbose) { - printf("Qlogic ISP Driver, FreeBSD Version %d.%d, " - "Core Version %d.%d\n", - ISP_PLATFORM_VERSION_MAJOR, ISP_PLATFORM_VERSION_MINOR, - ISP_CORE_VERSION_MAJOR, ISP_CORE_VERSION_MINOR); - isp_announced++; - } - return (0); -} - -static int -isp_sbus_attach(device_t dev) -{ - struct isp_sbussoftc *sbs = device_get_softc(dev); - ispsoftc_t *isp = &sbs->sbus_isp; - int tval, isp_debug, role, ispburst, default_id; - - sbs->sbus_dev = dev; - sbs->sbus_mdvec = mdvec; - isp->isp_dev = dev; - mtx_init(&isp->isp_lock, "isp", NULL, MTX_DEF); - - role = 0; - if (resource_int_value(device_get_name(dev), device_get_unit(dev), - "role", &role) == 0 && - ((role & ~(ISP_ROLE_INITIATOR|ISP_ROLE_TARGET)) == 0)) { - device_printf(dev, "setting role to 0x%x\n", role); - } else { - role = ISP_DEFAULT_ROLES; - } - - sbs->irq = sbs->regs = NULL; - sbs->rgd = sbs->iqd = 0; - - sbs->regs = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sbs->rgd, - RF_ACTIVE); - if (sbs->regs == NULL) { - device_printf(dev, "unable to map registers\n"); - goto bad; - } - - sbs->sbus_poff[BIU_BLOCK >> _BLK_REG_SHFT] = BIU_REGS_OFF; - sbs->sbus_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = SBUS_MBOX_REGS_OFF; - sbs->sbus_poff[SXP_BLOCK >> _BLK_REG_SHFT] = SBUS_SXP_REGS_OFF; - sbs->sbus_poff[RISC_BLOCK >> _BLK_REG_SHFT] = SBUS_RISC_REGS_OFF; - sbs->sbus_poff[DMA_BLOCK >> _BLK_REG_SHFT] = DMA_REGS_OFF; - isp->isp_regs = sbs->regs; - isp->isp_mdvec = &sbs->sbus_mdvec; - isp->isp_bustype = ISP_BT_SBUS; - isp->isp_type = ISP_HA_SCSI_UNKNOWN; - isp->isp_param = &sbs->sbus_param; - isp->isp_osinfo.pc.ptr = &sbs->sbus_spi; - isp->isp_revision = 0; /* XXX */ - isp->isp_nchan = 1; - if (IS_FC(isp)) - ISP_FC_PC(isp, 0)->def_role = role; - - /* - * Get the clock frequency and convert it from HZ to MHz, - * rounding up. This defaults to 25MHz if there isn't a - * device specific one in the OFW device tree. - */ - sbs->sbus_mdvec.dv_clock = (sbus_get_clockfreq(dev) + 500000)/1000000; - - /* - * Now figure out what the proper burst sizes, etc., to use. - * Unfortunately, there is no ddi_dma_burstsizes here which - * walks up the tree finding the limiting burst size node (if - * any). We just use what's here for isp. - */ - ispburst = sbus_get_burstsz(dev); - if (ispburst == 0) { - ispburst = SBUS_BURST_32 - 1; - } - sbs->sbus_mdvec.dv_conf1 = 0; - if (ispburst & (1 << 5)) { - sbs->sbus_mdvec.dv_conf1 = BIU_SBUS_CONF1_FIFO_32; - } else if (ispburst & (1 << 4)) { - sbs->sbus_mdvec.dv_conf1 = BIU_SBUS_CONF1_FIFO_16; - } else if (ispburst & (1 << 3)) { - sbs->sbus_mdvec.dv_conf1 = - BIU_SBUS_CONF1_BURST8 | BIU_SBUS_CONF1_FIFO_8; - } - if (sbs->sbus_mdvec.dv_conf1) { - sbs->sbus_mdvec.dv_conf1 |= BIU_BURST_ENABLE; - } - - /* - * We don't trust NVRAM on SBus cards - */ - isp->isp_confopts |= ISP_CFG_NONVRAM; - - /* - * Mark things if we're a PTI SBus adapter. - */ - if (strcmp("PTI,ptisp", ofw_bus_get_name(dev)) == 0 || - strcmp("ptisp", ofw_bus_get_name(dev)) == 0) { - SDPARAM(isp, 0)->isp_ptisp = 1; - } - - isp->isp_osinfo.fw = firmware_get("isp_1000"); - if (isp->isp_osinfo.fw) { - union { - const void *cp; - uint16_t *sp; - } stupid; - stupid.cp = isp->isp_osinfo.fw->data; - isp->isp_mdvec->dv_ispfw = stupid.sp; - } - - tval = 0; - if (resource_int_value(device_get_name(dev), device_get_unit(dev), - "fwload_disable", &tval) == 0 && tval != 0) { - isp->isp_confopts |= ISP_CFG_NORELOAD; - } - - default_id = -1; - if (resource_int_value(device_get_name(dev), device_get_unit(dev), - "iid", &tval) == 0) { - default_id = tval; - isp->isp_confopts |= ISP_CFG_OWNLOOPID; - } - if (default_id == -1) { - default_id = OF_getscsinitid(dev); - } - ISP_SPI_PC(isp, 0)->iid = default_id; - - isp_debug = 0; - (void) resource_int_value(device_get_name(dev), device_get_unit(dev), - "debug", &isp_debug); - - sbs->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sbs->iqd, - RF_ACTIVE | RF_SHAREABLE); - if (sbs->irq == NULL) { - device_printf(dev, "could not allocate interrupt\n"); - goto bad; - } - - if (bus_setup_intr(dev, sbs->irq, ISP_IFLAGS, NULL, isp_platform_intr, - isp, &sbs->ih)) { - device_printf(dev, "could not setup interrupt\n"); - (void) bus_release_resource(dev, SYS_RES_IRQ, - sbs->iqd, sbs->irq); - goto bad; - } - isp->isp_nirq = 1; - - /* - * Set up logging levels. - */ - if (isp_debug) { - isp->isp_dblev = isp_debug; - } else { - isp->isp_dblev = ISP_LOGWARN|ISP_LOGERR; - } - if (bootverbose) { - isp->isp_dblev |= ISP_LOGCONFIG|ISP_LOGINFO; - } - - /* - * Make sure we're in reset state. - */ - ISP_LOCK(isp); - if (isp_reinit(isp, 1) != 0) { - ISP_UNLOCK(isp); - goto bad; - } - ISP_UNLOCK(isp); - if (isp_attach(isp)) { - ISP_LOCK(isp); - isp_shutdown(isp); - ISP_UNLOCK(isp); - goto bad; - } - return (0); - -bad: - if (isp->isp_nirq > 0) { - (void) bus_teardown_intr(dev, sbs->irq, sbs->ih); - (void) bus_release_resource(dev, SYS_RES_IRQ, sbs->iqd, - sbs->irq); - } - - if (sbs->regs) { - (void) bus_release_resource(dev, SYS_RES_MEMORY, sbs->rgd, - sbs->regs); - } - mtx_destroy(&isp->isp_lock); - return (ENXIO); -} - -static int -isp_sbus_detach(device_t dev) -{ - struct isp_sbussoftc *sbs = device_get_softc(dev); - ispsoftc_t *isp = &sbs->sbus_isp; - int status; - - status = isp_detach(isp); - if (status) - return (status); - ISP_LOCK(isp); - isp_shutdown(isp); - ISP_UNLOCK(isp); - if (isp->isp_nirq > 0) { - (void) bus_teardown_intr(dev, sbs->irq, sbs->ih); - (void) bus_release_resource(dev, SYS_RES_IRQ, sbs->iqd, - sbs->irq); - } - (void) bus_release_resource(dev, SYS_RES_MEMORY, sbs->rgd, sbs->regs); - isp_sbus_mbxdmafree(isp); - mtx_destroy(&isp->isp_lock); - return (0); -} - -#define IspVirt2Off(a, x) \ - (((struct isp_sbussoftc *)a)->sbus_poff[((x) & _BLK_REG_MASK) >> \ - _BLK_REG_SHFT] + ((x) & 0xff)) - -#define BXR2(isp, off) bus_read_2((isp)->isp_regs, (off)) - -static void -isp_sbus_run_isr(ispsoftc_t *isp) -{ - uint16_t isr, sema, info; - - isr = BXR2(isp, IspVirt2Off(isp, BIU_ISR)); - sema = BXR2(isp, IspVirt2Off(isp, BIU_SEMA)); - isp_prt(isp, ISP_LOGDEBUG3, "ISR 0x%x SEMA 0x%x", isr, sema); - isr &= INT_PENDING_MASK(isp); - sema &= BIU_SEMA_LOCK; - if (isr == 0 && sema == 0) - return; - if (sema != 0) { - info = BXR2(isp, IspVirt2Off(isp, OUTMAILBOX0)); - if (info & MBOX_COMMAND_COMPLETE) - isp_intr_mbox(isp, info); - else - isp_intr_async(isp, info); - if (isp->isp_state == ISP_RUNSTATE) - isp_intr_respq(isp); - } else - isp_intr_respq(isp); - ISP_WRITE(isp, HCCR, HCCR_CMD_CLEAR_RISC_INT); - if (sema) - ISP_WRITE(isp, BIU_SEMA, 0); -} - -static uint32_t -isp_sbus_rd_reg(ispsoftc_t *isp, int regoff) -{ - uint16_t rval; - struct isp_sbussoftc *sbs = (struct isp_sbussoftc *) isp; - int offset = sbs->sbus_poff[(regoff & _BLK_REG_MASK) >> _BLK_REG_SHFT]; - offset += (regoff & 0xff); - rval = BXR2(isp, offset); - isp_prt(isp, ISP_LOGDEBUG3, - "isp_sbus_rd_reg(off %x) = %x", regoff, rval); - return (rval); -} - -static void -isp_sbus_wr_reg(ispsoftc_t *isp, int regoff, uint32_t val) -{ - struct isp_sbussoftc *sbs = (struct isp_sbussoftc *) isp; - int offset = sbs->sbus_poff[(regoff & _BLK_REG_MASK) >> _BLK_REG_SHFT]; - offset += (regoff & 0xff); - isp_prt(isp, ISP_LOGDEBUG3, - "isp_sbus_wr_reg(off %x) = %x", regoff, val); - bus_write_2(isp->isp_regs, offset, val); - MEMORYBARRIER(isp, SYNC_REG, offset, 2, -1); -} - -struct imush { - bus_addr_t maddr; - int error; -}; - -static void imc(void *, bus_dma_segment_t *, int, int); - -static void -imc(void *arg, bus_dma_segment_t *segs, int nseg, int error) -{ - struct imush *imushp = (struct imush *) arg; - - if (!(imushp->error = error)) - imushp->maddr = segs[0].ds_addr; -} - -static int -isp_sbus_mbxdma(ispsoftc_t *isp) -{ - caddr_t base; - uint32_t len; - int i, error; - struct imush im; - - /* Already been here? If so, leave... */ - if (isp->isp_xflist != NULL) - return (0); - if (isp->isp_rquest != NULL && isp->isp_maxcmds == 0) - return (0); - ISP_UNLOCK(isp); - if (isp->isp_rquest != NULL) - goto gotmaxcmds; - - if (bus_dma_tag_create(bus_get_dma_tag(ISP_SBD(isp)), 1, - BUS_SPACE_MAXADDR_24BIT+1, BUS_SPACE_MAXADDR_32BIT, - BUS_SPACE_MAXADDR_32BIT, NULL, NULL, BUS_SPACE_MAXSIZE_32BIT, - ISP_NSEG_MAX, BUS_SPACE_MAXADDR_24BIT, 0, - busdma_lock_mutex, &isp->isp_lock, &isp->isp_osinfo.dmat)) { - isp_prt(isp, ISP_LOGERR, "could not create master dma tag"); - goto bad; - } - - /* - * Allocate and map the request queue. - */ - len = ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp)); - if (bus_dma_tag_create(isp->isp_osinfo.dmat, QENTRY_LEN, BUS_SPACE_MAXADDR_24BIT+1, - BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, - len, 1, len, 0, busdma_lock_mutex, &isp->isp_lock, - &isp->isp_osinfo.reqdmat)) { - isp_prt(isp, ISP_LOGERR, "cannot create request DMA tag"); - goto bad; - } - if (bus_dmamem_alloc(isp->isp_osinfo.reqdmat, (void **)&base, - BUS_DMA_COHERENT, &isp->isp_osinfo.reqmap) != 0) { - isp_prt(isp, ISP_LOGERR, "cannot allocate request DMA memory"); - bus_dma_tag_destroy(isp->isp_osinfo.reqdmat); - goto bad; - } - isp->isp_rquest = base; - im.error = 0; - if (bus_dmamap_load(isp->isp_osinfo.reqdmat, isp->isp_osinfo.reqmap, - base, len, imc, &im, 0) || im.error) { - isp_prt(isp, ISP_LOGERR, "error loading request DMA map %d", im.error); - goto bad; - } - isp_prt(isp, ISP_LOGDEBUG0, "request area @ 0x%jx/0x%jx", - (uintmax_t)im.maddr, (uintmax_t)len); - isp->isp_rquest_dma = im.maddr; - - /* - * Allocate and map the result queue. - */ - len = ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp)); - if (bus_dma_tag_create(isp->isp_osinfo.dmat, QENTRY_LEN, BUS_SPACE_MAXADDR_24BIT+1, - BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, - len, 1, len, 0, busdma_lock_mutex, &isp->isp_lock, - &isp->isp_osinfo.respdmat)) { - isp_prt(isp, ISP_LOGERR, "cannot create response DMA tag"); - goto bad; - } - if (bus_dmamem_alloc(isp->isp_osinfo.respdmat, (void **)&base, - BUS_DMA_COHERENT, &isp->isp_osinfo.respmap) != 0) { - isp_prt(isp, ISP_LOGERR, "cannot allocate response DMA memory"); - bus_dma_tag_destroy(isp->isp_osinfo.respdmat); - goto bad; - } - isp->isp_result = base; - im.error = 0; - if (bus_dmamap_load(isp->isp_osinfo.respdmat, isp->isp_osinfo.respmap, - base, len, imc, &im, 0) || im.error) { - isp_prt(isp, ISP_LOGERR, "error loading response DMA map %d", im.error); - goto bad; - } - isp_prt(isp, ISP_LOGDEBUG0, "response area @ 0x%jx/0x%jx", - (uintmax_t)im.maddr, (uintmax_t)len); - isp->isp_result_dma = im.maddr; - - if (isp->isp_maxcmds == 0) { - ISP_LOCK(isp); - return (0); - } - -gotmaxcmds: - len = sizeof (struct isp_pcmd) * isp->isp_maxcmds; - isp->isp_osinfo.pcmd_pool = (struct isp_pcmd *) - malloc(len, M_DEVBUF, M_WAITOK | M_ZERO); - for (i = 0; i < isp->isp_maxcmds; i++) { - struct isp_pcmd *pcmd = &isp->isp_osinfo.pcmd_pool[i]; - error = bus_dmamap_create(isp->isp_osinfo.dmat, 0, &pcmd->dmap); - if (error) { - isp_prt(isp, ISP_LOGERR, - "error %d creating per-cmd DMA maps", error); - while (--i >= 0) { - bus_dmamap_destroy(isp->isp_osinfo.dmat, - isp->isp_osinfo.pcmd_pool[i].dmap); - } - goto bad; - } - callout_init_mtx(&pcmd->wdog, &isp->isp_lock, 0); - if (i == isp->isp_maxcmds-1) { - pcmd->next = NULL; - } else { - pcmd->next = &isp->isp_osinfo.pcmd_pool[i+1]; - } - } - isp->isp_osinfo.pcmd_free = &isp->isp_osinfo.pcmd_pool[0]; - - len = sizeof (isp_hdl_t *) * isp->isp_maxcmds; - isp->isp_xflist = (isp_hdl_t *) malloc(len, M_DEVBUF, M_WAITOK | M_ZERO); - for (len = 0; len < isp->isp_maxcmds - 1; len++) - isp->isp_xflist[len].cmd = &isp->isp_xflist[len+1]; - isp->isp_xffree = isp->isp_xflist; - - ISP_LOCK(isp); - return (0); - -bad: - isp_sbus_mbxdmafree(isp); - ISP_LOCK(isp); - return (1); -} - -static void -isp_sbus_mbxdmafree(ispsoftc_t *isp) -{ - int i; - - if (isp->isp_xflist != NULL) { - free(isp->isp_xflist, M_DEVBUF); - isp->isp_xflist = NULL; - } - if (isp->isp_osinfo.pcmd_pool != NULL) { - for (i = 0; i < isp->isp_maxcmds; i++) { - bus_dmamap_destroy(isp->isp_osinfo.dmat, - isp->isp_osinfo.pcmd_pool[i].dmap); - } - free(isp->isp_osinfo.pcmd_pool, M_DEVBUF); - isp->isp_osinfo.pcmd_pool = NULL; - } - if (isp->isp_result_dma != 0) { - bus_dmamap_unload(isp->isp_osinfo.respdmat, - isp->isp_osinfo.respmap); - isp->isp_result_dma = 0; - } - if (isp->isp_result != NULL) { - bus_dmamem_free(isp->isp_osinfo.respdmat, isp->isp_result, - isp->isp_osinfo.respmap); - bus_dma_tag_destroy(isp->isp_osinfo.respdmat); - isp->isp_result = NULL; - } - if (isp->isp_rquest_dma != 0) { - bus_dmamap_unload(isp->isp_osinfo.reqdmat, - isp->isp_osinfo.reqmap); - isp->isp_rquest_dma = 0; - } - if (isp->isp_rquest != NULL) { - bus_dmamem_free(isp->isp_osinfo.reqdmat, isp->isp_rquest, - isp->isp_osinfo.reqmap); - bus_dma_tag_destroy(isp->isp_osinfo.reqdmat); - isp->isp_rquest = NULL; - } -} - -typedef struct { - ispsoftc_t *isp; - void *cmd_token; - void *rq; /* original request */ - int error; -} mush_t; - -#define MUSHERR_NOQENTRIES -2 - -static void -dma2(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) -{ - mush_t *mp = (mush_t *) arg; - ispsoftc_t *isp = mp->isp; - struct ccb_scsiio *csio = mp->cmd_token; - isp_ddir_t ddir; - int sdir; - - if (error) { - mp->error = error; - return; - } - if (nseg == 0) { - ddir = ISP_NOXFR; - } else { - if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { - ddir = ISP_FROM_DEVICE; - } else { - ddir = ISP_TO_DEVICE; - } - if ((csio->ccb_h.func_code == XPT_CONT_TARGET_IO) ^ - ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN)) { - sdir = BUS_DMASYNC_PREREAD; - } else { - sdir = BUS_DMASYNC_PREWRITE; - } - bus_dmamap_sync(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, - sdir); - } - - if (isp_send_cmd(isp, mp->rq, dm_segs, nseg, XS_XFRLEN(csio), - ddir, NULL) != CMD_QUEUED) { - mp->error = MUSHERR_NOQENTRIES; - } -} - -static int -isp_sbus_dmasetup(ispsoftc_t *isp, struct ccb_scsiio *csio, void *ff) -{ - mush_t mush, *mp; - int error; - - mp = &mush; - mp->isp = isp; - mp->cmd_token = csio; - mp->rq = ff; - mp->error = 0; - - error = bus_dmamap_load_ccb(isp->isp_osinfo.dmat, - PISP_PCMD(csio)->dmap, (union ccb *)csio, dma2, mp, 0); - if (error == EINPROGRESS) { - bus_dmamap_unload(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap); - mp->error = EINVAL; - isp_prt(isp, ISP_LOGERR, - "deferred dma allocation not supported"); - } else if (error && mp->error == 0) { -#ifdef DIAGNOSTIC - isp_prt(isp, ISP_LOGERR, "error %d in dma mapping code", error); -#endif - mp->error = error; - } - if (mp->error) { - int retval = CMD_COMPLETE; - if (mp->error == MUSHERR_NOQENTRIES) { - retval = CMD_EAGAIN; - } else if (mp->error == EFBIG) { - XS_SETERR(csio, CAM_REQ_TOO_BIG); - } else if (mp->error == EINVAL) { - XS_SETERR(csio, CAM_REQ_INVALID); - } else { - XS_SETERR(csio, CAM_UNREC_HBA_ERROR); - } - return (retval); - } - return (CMD_QUEUED); -} - -static void -isp_sbus_dumpregs(ispsoftc_t *isp, const char *msg) -{ - if (msg) - printf("%s: %s\n", device_get_nameunit(isp->isp_dev), msg); - else - printf("%s:\n", device_get_nameunit(isp->isp_dev)); - printf(" biu_conf1=%x", ISP_READ(isp, BIU_CONF1)); - printf(" biu_icr=%x biu_isr=%x biu_sema=%x ", ISP_READ(isp, BIU_ICR), - ISP_READ(isp, BIU_ISR), ISP_READ(isp, BIU_SEMA)); - printf("risc_hccr=%x\n", ISP_READ(isp, HCCR)); - - - ISP_WRITE(isp, HCCR, HCCR_CMD_PAUSE); - printf(" cdma_conf=%x cdma_sts=%x cdma_fifostat=%x\n", - ISP_READ(isp, CDMA_CONF), ISP_READ(isp, CDMA_STATUS), - ISP_READ(isp, CDMA_FIFO_STS)); - printf(" ddma_conf=%x ddma_sts=%x ddma_fifostat=%x\n", - ISP_READ(isp, DDMA_CONF), ISP_READ(isp, DDMA_STATUS), - ISP_READ(isp, DDMA_FIFO_STS)); - printf(" sxp_int=%x sxp_gross=%x sxp(scsi_ctrl)=%x\n", - ISP_READ(isp, SXP_INTERRUPT), - ISP_READ(isp, SXP_GROSS_ERR), - ISP_READ(isp, SXP_PINS_CTRL)); - ISP_WRITE(isp, HCCR, HCCR_CMD_RELEASE); - printf(" mbox regs: %x %x %x %x %x\n", - ISP_READ(isp, OUTMAILBOX0), ISP_READ(isp, OUTMAILBOX1), - ISP_READ(isp, OUTMAILBOX2), ISP_READ(isp, OUTMAILBOX3), - ISP_READ(isp, OUTMAILBOX4)); -} diff --git a/sys/dev/ispfw/asm_1000.h b/sys/dev/ispfw/asm_1000.h deleted file mode 100644 index 491dda3bd03..00000000000 --- a/sys/dev/ispfw/asm_1000.h +++ /dev/null @@ -1,1292 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-3-Clause - * - * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2000 Qlogic, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms are permitted provided - * that the following conditions are met: - * 1. Redistribution of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistribution in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/* - * Firmware Version 1.37.00 (11:28 Aug 28, 2000) - */ -static const u_int16_t isp_1000_risc_code[] = { - 0x0078, 0x1041, 0x0000, 0x2757, 0x0000, 0x12ff, 0x2043, 0x4f50, - 0x5952, 0x4947, 0x4854, 0x2031, 0x3939, 0x312c, 0x3139, 0x3932, - 0x2c31, 0x3939, 0x332c, 0x3139, 0x3934, 0x2051, 0x4c4f, 0x4749, - 0x4320, 0x434f, 0x5250, 0x4f52, 0x4154, 0x494f, 0x4e00, 0x2049, - 0x5350, 0x3130, 0x3030, 0x2046, 0x6972, 0x6d77, 0x6172, 0x6520, - 0x2056, 0x6572, 0x7369, 0x6f6e, 0x2030, 0x312e, 0x3337, 0x2020, - 0x2043, 0x7573, 0x746f, 0x6d65, 0x7220, 0x4e6f, 0x2e20, 0x3135, - 0x2050, 0x726f, 0x6475, 0x6374, 0x204e, 0x6f2e, 0x2000, 0x3030, - 0x2024, 0x20b9, 0x1212, 0x20c1, 0x0008, 0x2071, 0x0010, 0x70c3, - 0x0004, 0x20c9, 0x5cff, 0x2089, 0x10ee, 0x70c7, 0x4953, 0x70cb, - 0x5020, 0x70cf, 0x2020, 0x70d3, 0x0001, 0x3f00, 0x70d6, 0x2031, - 0x0030, 0x2079, 0x3800, 0x7863, 0x0000, 0x2fa0, 0x2009, 0x031b, - 0x2011, 0x0000, 0x20a9, 0x0040, 0x42a4, 0x8109, 0x00c0, 0x1062, - 0x789b, 0x0101, 0x780b, 0x0002, 0x780f, 0x0002, 0x784f, 0x0bb8, - 0x2009, 0x3835, 0x200b, 0x0003, 0x78bb, 0x0000, 0x78bf, 0x0000, - 0x78c3, 0x0000, 0x2069, 0x3840, 0x00a8, 0x1085, 0x681b, 0x003c, - 0x2009, 0x1313, 0x21b8, 0x0078, 0x1087, 0x681b, 0x0028, 0x6807, - 0x0007, 0x680b, 0x00fa, 0x680f, 0x0008, 0x6813, 0x0005, 0x681f, - 0x0000, 0x6823, 0x0006, 0x6817, 0x0008, 0x6827, 0x0000, 0x2069, - 0x3a80, 0x2011, 0x0020, 0x2009, 0x0010, 0x680b, 0x0c19, 0x680f, - 0x0019, 0x6803, 0xdd00, 0x6807, 0x001a, 0x6a1a, 0x2d00, 0xa0e8, - 0x0008, 0xa290, 0x0004, 0x8109, 0x00c0, 0x109d, 0x2069, 0x3b00, - 0x2009, 0x0002, 0x20a9, 0x0100, 0x683f, 0x0000, 0x2001, 0x0008, - 0x8007, 0x6832, 0x6837, 0x000a, 0x680b, 0x0040, 0x6817, 0x0100, - 0x681f, 0x0064, 0xade8, 0x0010, 0x0070, 0x10c8, 0x0078, 0x10b4, - 0x8109, 0x00c0, 0x10b2, 0x1078, 0x1b64, 0x1078, 0x31c0, 0x1078, - 0x1747, 0x1078, 0x368b, 0x3200, 0xa085, 0x000d, 0x2090, 0x70c3, - 0x0000, 0x0090, 0x10e2, 0x70c0, 0xa086, 0x0002, 0x00c0, 0x10e2, - 0x1078, 0x11e0, 0x1078, 0x1112, 0x1078, 0x18f2, 0x1078, 0x1aaf, - 0x1078, 0x34fd, 0x1078, 0x184d, 0x0078, 0x10e2, 0x10f6, 0x10f8, - 0x1d05, 0x1d05, 0x321e, 0x321e, 0x1d05, 0x1d05, 0x0078, 0x10f6, - 0x0078, 0x10f8, 0x0078, 0x10fa, 0x0078, 0x10fc, 0x7008, 0x800c, - 0x00c8, 0x110d, 0x7007, 0x0002, 0xa08c, 0x000c, 0x00c0, 0x110e, - 0x8004, 0x8004, 0x00c8, 0x110d, 0x087a, 0x097a, 0x70c3, 0x4002, - 0x0078, 0x11e3, 0x7814, 0xa005, 0x00c0, 0x111a, 0x0010, 0x1156, - 0x0078, 0x1155, 0x2009, 0x3868, 0x2104, 0xa005, 0x00c0, 0x1155, - 0x7814, 0xa086, 0x0001, 0x00c0, 0x1127, 0x1078, 0x15ae, 0x7817, - 0x0000, 0x2009, 0x386f, 0x2104, 0xa065, 0x0040, 0x1143, 0x2009, - 0x386a, 0x211c, 0x8108, 0x2114, 0x8108, 0x2104, 0xa210, 0xa399, - 0x0000, 0x2009, 0x0018, 0x6083, 0x0103, 0x1078, 0x16d7, 0x00c0, - 0x114f, 0x1078, 0x173e, 0x2009, 0x386f, 0x200b, 0x0000, 0x2009, - 0x3869, 0x2104, 0x200b, 0x0000, 0xa005, 0x0040, 0x1153, 0x2001, - 0x4005, 0x0078, 0x11e2, 0x0078, 0x11e0, 0x007c, 0x2061, 0x0000, - 0x6018, 0xa084, 0x0001, 0x0040, 0x115e, 0x007c, 0x70c3, 0x0000, - 0x70c7, 0x0000, 0x70cb, 0x0000, 0x70cf, 0x0000, 0x70c0, 0xa0bc, - 0xffc0, 0x00c0, 0x11ae, 0x2038, 0x0079, 0x116e, 0x11e0, 0x122e, - 0x11fc, 0x122e, 0x127f, 0x127f, 0x11f3, 0x1608, 0x128a, 0x11ef, - 0x1200, 0x1202, 0x1204, 0x1206, 0x160d, 0x11ef, 0x1292, 0x12ba, - 0x15bc, 0x1602, 0x1208, 0x14e3, 0x1505, 0x151f, 0x1548, 0x149c, - 0x14aa, 0x14be, 0x14d2, 0x1357, 0x1332, 0x12e2, 0x12e9, 0x12ee, - 0x12f3, 0x12f9, 0x12fe, 0x1303, 0x1308, 0x130d, 0x1311, 0x1326, - 0x11ef, 0x11ef, 0x11ef, 0x11ef, 0x11ef, 0x1363, 0x136c, 0x137b, - 0x13a1, 0x13ab, 0x13b2, 0x13d8, 0x13e7, 0x13f6, 0x1408, 0x147a, - 0x11ef, 0x148a, 0x11ef, 0x11ef, 0x11ef, 0x1491, 0xa0bc, 0xffa0, - 0x00c0, 0x11ef, 0x2038, 0xa084, 0x001f, 0x0079, 0x11b7, 0x11ef, - 0x11ef, 0x11ef, 0x11ef, 0x11ef, 0x11ef, 0x11ef, 0x11ef, 0x11ef, - 0x11ef, 0x11ef, 0x11ef, 0x11ef, 0x11ef, 0x1665, 0x1674, 0x11ef, - 0x11ef, 0x11ef, 0x11ef, 0x11ef, 0x11ef, 0x11ef, 0x11ef, 0x11ef, - 0x11ef, 0x16b3, 0x16bd, 0x16c1, 0x16cf, 0x167f, 0x169c, 0x72ca, - 0x71c6, 0x2001, 0x4006, 0x0078, 0x11e2, 0x73ce, 0x72ca, 0x71c6, - 0x2001, 0x4000, 0x70c2, 0x2061, 0x0000, 0x601b, 0x0001, 0x2091, - 0x5000, 0x2091, 0x4080, 0x007c, 0x71c6, 0x0078, 0x11e2, 0x70c3, - 0x4001, 0x0078, 0x11e3, 0x2099, 0x0041, 0x20a1, 0x0041, 0x20a9, - 0x0005, 0x53a3, 0x0078, 0x11e0, 0x70c4, 0x70c3, 0x0004, 0x007a, - 0x0078, 0x11e0, 0x0078, 0x11e0, 0x0078, 0x11e0, 0x0078, 0x11e0, - 0x2091, 0x8000, 0x70c3, 0x0000, 0x70c7, 0x4953, 0x70cb, 0x5020, - 0x70cf, 0x2020, 0x70d3, 0x0001, 0x3f00, 0x70d6, 0x2079, 0x0000, - 0x781b, 0x0001, 0x2031, 0x0030, 0x2059, 0x1000, 0x2029, 0x0457, - 0x2051, 0x0470, 0x2061, 0x0472, 0x20b9, 0xffff, 0x20c1, 0x0000, - 0x2091, 0x5000, 0x2091, 0x4080, 0x0078, 0x0455, 0x71d0, 0x72c8, - 0x73cc, 0x70c4, 0x20a0, 0x2098, 0x2031, 0x0030, 0x81ff, 0x0040, - 0x11e0, 0x7007, 0x0004, 0x731a, 0x721e, 0x2051, 0x0012, 0x2049, - 0x125d, 0x2041, 0x11e0, 0x7003, 0x0002, 0xa786, 0x0001, 0x00c0, - 0x124f, 0x2049, 0x126b, 0x2041, 0x1277, 0x7003, 0x0003, 0x7017, - 0x0000, 0x810b, 0x7112, 0x00c8, 0x1257, 0x7017, 0x0001, 0x7007, - 0x0001, 0xa786, 0x0001, 0x0040, 0x126b, 0x700c, 0xa084, 0x007f, - 0x8004, 0x2009, 0x0020, 0xa102, 0x0942, 0x094a, 0x20a8, 0x26a0, - 0x53a6, 0x0078, 0x10fe, 0x700c, 0xa084, 0x007f, 0x0040, 0x126b, - 0x80ac, 0x0048, 0x126b, 0x2698, 0x53a5, 0x0078, 0x10fe, 0x700c, - 0xa084, 0x007f, 0x80ac, 0x2698, 0x53a5, 0x0078, 0x11e0, 0x71c4, - 0x70c8, 0x2114, 0xa79e, 0x0004, 0x00c0, 0x1287, 0x200a, 0x72ca, - 0x0078, 0x11df, 0x70c7, 0x0125, 0x70cb, 0x0000, 0x70cf, 0x0f00, - 0x0078, 0x11e0, 0x70c4, 0x72c8, 0x73cc, 0x74d0, 0x70c6, 0x72ca, - 0x73ce, 0x74d2, 0xa005, 0x0040, 0x12b4, 0x8001, 0x7872, 0xa084, - 0xfc00, 0x0040, 0x12ab, 0x7898, 0xa085, 0x0001, 0x789a, 0x2001, - 0x4005, 0x0078, 0x11e2, 0x7a7a, 0x7b7e, 0x7c76, 0x7898, 0xa084, - 0xfffc, 0x789a, 0x0078, 0x12b8, 0x7898, 0xa085, 0x0001, 0x789a, - 0x0078, 0x11e0, 0x70c4, 0x72c8, 0x73cc, 0x74d4, 0x70c6, 0x72ca, - 0x73ce, 0x74d6, 0xa005, 0x0040, 0x12dc, 0x8001, 0x7886, 0xa084, - 0xfc00, 0x0040, 0x12d3, 0x7898, 0xa085, 0x0100, 0x789a, 0x2001, - 0x4005, 0x0078, 0x11e2, 0x7a8e, 0x7b92, 0x7c8a, 0x7898, 0xa084, - 0xfcff, 0x789a, 0x0078, 0x12e0, 0x7898, 0xa085, 0x0100, 0x789a, - 0x0078, 0x11e0, 0x2009, 0x3859, 0x210c, 0x2011, 0x0372, 0x0078, - 0x11de, 0x2009, 0x3841, 0x210c, 0x0078, 0x11df, 0x2009, 0x3842, - 0x210c, 0x0078, 0x11df, 0x2061, 0x3840, 0x610c, 0x6210, 0x0078, - 0x11de, 0x2009, 0x3845, 0x210c, 0x0078, 0x11df, 0x2009, 0x3846, - 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0x6818, 0xa005, 0x0040, 0x3606, 0x8001, 0x681a, 0x6808, 0xa084, - 0xffef, 0x680a, 0x6810, 0x8001, 0x00d0, 0x3610, 0x1078, 0x1ce7, - 0x6812, 0x602f, 0x0000, 0x602b, 0x0000, 0x2c68, 0x1078, 0x18b6, - 0x2069, 0x3840, 0x6710, 0xa784, 0x0f00, 0x68b6, 0x2001, 0x0002, - 0x1078, 0x1b44, 0x2041, 0x0021, 0x2049, 0x0005, 0x2051, 0x0030, - 0x1078, 0x1765, 0x2011, 0x3835, 0x2214, 0x6a3e, 0x8738, 0xa784, - 0x001f, 0x00c0, 0x3622, 0x2009, 0x382b, 0x200b, 0x0008, 0x2009, - 0x382c, 0x2069, 0x3840, 0x68b4, 0x200a, 0x2091, 0x8001, 0x007c, - 0x2009, 0x384f, 0x2164, 0x2069, 0x0100, 0x1078, 0x1c97, 0x6017, - 0x0006, 0x6858, 0xa084, 0x3f00, 0x601a, 0x601c, 0xa084, 0x00ff, - 0xa085, 0x0048, 0x601e, 0x602f, 0x0000, 0x602b, 0x0000, 0x6830, - 0xa084, 0x0040, 0x0040, 0x367c, 0x684b, 0x0004, 0x20a9, 0x0014, - 0x6848, 0xa084, 0x0004, 0x0040, 0x3669, 0x0070, 0x3669, 0x0078, - 0x3660, 0x684b, 0x0009, 0x20a9, 0x0014, 0x6848, 0xa084, 0x0001, - 0x0040, 0x3676, 0x0070, 0x3676, 0x0078, 0x366d, 0x20a9, 0x00fa, - 0x0070, 0x367c, 0x0078, 0x3678, 0x6808, 0xa084, 0xfffd, 0x680a, - 0x681b, 0x0046, 0x2009, 0x3868, 0x200b, 0x0007, 0x784c, 0x784a, - 0x2091, 0x8001, 0x007c, 0x2079, 0x3800, 0x1078, 0x36de, 0x1078, - 0x36a6, 0x1078, 0x36b4, 0x1078, 0x36c9, 0x1078, 0x36f3, 0x2009, - 0x3833, 0x200b, 0x0000, 0x2009, 0x3834, 0x200b, 0x0000, 0x7833, - 0x0000, 0x7847, 0x0000, 0x784b, 0x0000, 0x007c, 0x2019, 0x0003, - 0x2011, 0x3846, 0x2204, 0xa086, 0x003c, 0x0040, 0x36b1, 0x2019, - 0x0002, 0x7b2a, 0x7b2e, 0x007c, 0x2019, 0x0030, 0x2011, 0x3846, - 0x2204, 0xa086, 0x0032, 0x0040, 0x36c6, 0x2019, 0x0039, 0x2204, - 0xa086, 0x003c, 0x0040, 0x36c6, 0x2019, 0x0027, 0x7b36, 0x7b3a, - 0x007c, 0x2019, 0x000f, 0x2011, 0x3846, 0x2204, 0xa086, 0x003c, - 0x0040, 0x36db, 0x2019, 0x000d, 0x2204, 0xa086, 0x0032, 0x0040, - 0x36db, 0x2019, 0x000a, 0x7b3e, 0x7b42, 0x007c, 0x2019, 0x2faf, - 0x2011, 0x3846, 0x2204, 0xa086, 0x0032, 0x0040, 0x36f0, 0x2019, - 0x3971, 0x2204, 0xa086, 0x003c, 0x0040, 0x36f0, 0x2019, 0x2626, - 0x7b22, 0x7b26, 0x007c, 0x2019, 0x0001, 0x2011, 0x3846, 0x2204, - 0xa086, 0x003c, 0x0040, 0x36fe, 0x2019, 0x0001, 0x017e, 0x2009, - 0x3831, 0x230a, 0x2009, 0x3832, 0x230a, 0x017f, 0x007c, 0x2009, - 0x3831, 0x2104, 0x8001, 0x200a, 0xa005, 0x00c0, 0x3755, 0x2009, - 0x3832, 0x2104, 0x2009, 0x3831, 0x200a, 0x2009, 0x3833, 0x2104, - 0xa005, 0x00c0, 0x371d, 0x2001, 0x0200, 0x8001, 0x200a, 0x8003, - 0x8003, 0x8003, 0x8003, 0xa090, 0x3b00, 0x2208, 0xa298, 0x0002, - 0x2304, 0xa084, 0x0200, 0x0040, 0x3755, 0xa290, 0x000e, 0x2204, - 0xa005, 0x0040, 0x3740, 0x8001, 0x0040, 0x3740, 0x8001, 0x0040, - 0x3740, 0x8001, 0x0040, 0x3740, 0x8001, 0x2012, 0x00c0, 0x3755, - 0x2012, 0x2304, 0xa084, 0xfdff, 0xa085, 0x0400, 0x201a, 0xa188, - 0x000c, 0x2104, 0x007e, 0xa084, 0x00ff, 0x8001, 0x027f, 0xa294, - 0xff00, 0xa205, 0x200a, 0x1078, 0x1b49, 0x007c, 0x6ed0 -}; diff --git a/sys/dev/ispfw/asm_1040.h b/sys/dev/ispfw/asm_1040.h deleted file mode 100644 index 677911a8b65..00000000000 --- a/sys/dev/ispfw/asm_1040.h +++ /dev/null @@ -1,1475 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-3-Clause - * - * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2000 Qlogic, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms are permitted provided - * that the following conditions are met: - * 1. Redistribution of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistribution in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/************************************************************************ - * * - * --- ISP1040 Initiator Firmware --- * - * 32 LUN Support * - * * - ************************************************************************/ -/* - * Firmware Version 4.66.00 (14:49 Sep 05, 2000) - */ -#ifdef ISP_1040 -static const u_int16_t isp_1040_risc_code[] = { - 0x0078, 0x1041, 0x0000, 0x2cd0, 0x0000, 0x2043, 0x4f50, 0x5952, - 0x4947, 0x4854, 0x2031, 0x3939, 0x312c, 0x3139, 0x3932, 0x2c31, - 0x3939, 0x332c, 0x3139, 0x3934, 0x2051, 0x4c4f, 0x4749, 0x4320, - 0x434f, 0x5250, 0x4f52, 0x4154, 0x494f, 0x4e00, 0x2049, 0x5350, - 0x3130, 0x3230, 0x2046, 0x6972, 0x6d77, 0x6172, 0x6520, 0x2056, - 0x6572, 0x7369, 0x6f6e, 0x2030, 0x342e, 0x3636, 0x2020, 0x2043, - 0x7573, 0x746f, 0x6d65, 0x7220, 0x4e6f, 0x2e20, 0x3030, 0x2050, - 0x726f, 0x6475, 0x6374, 0x204e, 0x6f2e, 0x2020, 0x3030, 0x2020, - 0x2400, 0x2001, 0x04fd, 0x2004, 0xa082, 0x0005, 0x0048, 0x104c, - 0x0038, 0x1052, 0x0078, 0x104e, 0x0028, 0x1052, 0x20b9, 0x1212, - 0x0078, 0x1054, 0x20b9, 0x1313, 0x2071, 0x0010, 0x70c3, 0x0004, - 0x20c9, 0x62ff, 0x2089, 0x1185, 0x70c7, 0x4953, 0x70cb, 0x5020, - 0x70cf, 0x2020, 0x70d3, 0x0004, 0x3f00, 0x70d6, 0x20c1, 0x0008, - 0x2019, 0x0000, 0x2009, 0xfeff, 0x2100, 0x200b, 0xa5a5, 0xa1ec, - 0x7fff, 0x2d64, 0x206b, 0x0a0a, 0xaddc, 0x3fff, 0x2b54, 0x205b, - 0x5050, 0x2114, 0xa286, 0xa5a5, 0x0040, 0x10c4, 0xa386, 0x000f, - 0x0040, 0x108a, 0x2c6a, 0x2a5a, 0x20c1, 0x0000, 0x2019, 0x000f, - 0x0078, 0x106a, 0x2c6a, 0x2a5a, 0x20c1, 0x0008, 0x2009, 0x7fff, - 0x2148, 0x2944, 0x204b, 0x0a0a, 0xa9bc, 0x3fff, 0x2734, 0x203b, - 0x5050, 0x2114, 0xa286, 0x0a0a, 0x0040, 0x10ae, 0x284a, 0x263a, - 0x20c1, 0x0004, 0x2009, 0x3fff, 0x2134, 0x200b, 0x5050, 0x2114, - 0xa286, 0x5050, 0x0040, 0x10af, 0x0078, 0x118d, 0x284a, 0x263a, - 0x98c0, 0xa188, 0x1000, 0x212c, 0x200b, 0xa5a5, 0x2114, 0xa286, - 0xa5a5, 0x0040, 0x10c1, 0x250a, 0xa18a, 0x1000, 0x98c1, 0x0078, - 0x10c6, 0x250a, 0x0078, 0x10c6, 0x2c6a, 0x2a5a, 0x2130, 0xa18a, - 0x0040, 0x2128, 0xa1a2, 0x3d00, 0x8424, 0x8424, 0x8424, 0x8424, - 0x8424, 0x8424, 0xa192, 0x6300, 0x2009, 0x0000, 0x2001, 0x002f, - 0x1078, 0x1bc9, 0x2218, 0x2079, 0x3d00, 0x2fa0, 0x2408, 0x2011, - 0x0000, 0x20a9, 0x0040, 0x42a4, 0x8109, 0x00c0, 0x10e1, 0x7ee6, - 0x8528, 0x7dda, 0x7cde, 0x7be2, 0x787b, 0x0000, 0x2031, 0x0030, - 0x78c3, 0x0101, 0x780b, 0x0002, 0x780f, 0x0002, 0x784f, 0x0003, - 0x7803, 0x0002, 0x2069, 0x3d40, 0x2001, 0x04fd, 0x2004, 0xa082, - 0x0005, 0x0048, 0x1107, 0x0038, 0x1109, 0x0078, 0x110d, 0x00a8, - 0x110d, 0x681b, 0x003c, 0x0078, 0x110f, 0x681b, 0x0028, 0x6807, - 0x0007, 0x680b, 0x00fa, 0x680f, 0x0008, 0x6813, 0x0005, 0x681f, - 0x0000, 0x6823, 0x0006, 0x6817, 0x0008, 0x6827, 0x0000, 0x2069, - 0x3f80, 0x2011, 0x0020, 0x2009, 0x0010, 0x680b, 0x0c19, 0x680f, - 0x0019, 0x6803, 0xfd00, 0x6807, 0x0018, 0x6a1a, 0x2d00, 0xa0e8, - 0x0008, 0xa290, 0x0004, 0x8109, 0x00c0, 0x1125, 0x2069, 0x4000, - 0x2009, 0x0002, 0x20a9, 0x0100, 0x6837, 0x0000, 0x680b, 0x0040, - 0x7be4, 0xa386, 0xfeff, 0x00c0, 0x114b, 0x6817, 0x0100, 0x681f, - 0x0064, 0x0078, 0x114f, 0x6817, 0x0064, 0x681f, 0x0002, 0xade8, - 0x0010, 0x0070, 0x1155, 0x0078, 0x113c, 0x8109, 0x00c0, 0x113a, - 0x1078, 0x1f20, 0x1078, 0x3792, 0x1078, 0x19e0, 0x1078, 0x3c4a, - 0x3200, 0xa085, 0x000d, 0x2090, 0x70c3, 0x0000, 0x0090, 0x116f, - 0x70c0, 0xa086, 0x0002, 0x00c0, 0x116f, 0x1078, 0x12a4, 0x1078, - 0x11b6, 0x78c0, 0xa005, 0x00c0, 0x117b, 0x1078, 0x1bf2, 0x0068, - 0x117f, 0x1078, 0x1e44, 0x0068, 0x117f, 0x1078, 0x1adf, 0x00e0, - 0x116f, 0x1078, 0x3ac1, 0x0078, 0x116f, 0x118d, 0x1192, 0x20e8, - 0x20e8, 0x380c, 0x380c, 0x20e8, 0x20e8, 0x0088, 0x118d, 0x2091, - 0x8001, 0x007c, 0x0088, 0x1192, 0x2091, 0x8001, 0x007c, 0x0078, - 0x1197, 0x0078, 0x1199, 0x2009, 0x0022, 0x2104, 0xa086, 0x4000, - 0x0040, 0x11b1, 0x7008, 0x800b, 0x00c8, 0x11b1, 0x7007, 0x0002, - 0xa08c, 0x01e0, 0x00c0, 0x11b2, 0xa084, 0x0008, 0x0040, 0x11b1, - 0x087a, 0x097a, 0x70c3, 0x4002, 0x0078, 0x12a7, 0x0068, 0x1221, - 0x2061, 0x0000, 0x6018, 0xa084, 0x0001, 0x00c0, 0x1221, 0x7814, - 0xa005, 0x00c0, 0x11c7, 0x0010, 0x1222, 0x0078, 0x1221, 0x2009, - 0x3d68, 0x2104, 0xa005, 0x00c0, 0x1221, 0x2009, 0x3d71, 0x200b, - 0x0000, 0x7914, 0xa186, 0x0042, 0x00c0, 0x11ec, 0x7816, 0x2009, - 0x3d6f, 0x2164, 0x200b, 0x0000, 0x6018, 0x70c6, 0x6014, 0x70ca, - 0x611c, 0xa18c, 0xff00, 0x6020, 0xa084, 0x00ff, 0xa105, 0x70ce, - 0x1078, 0x19d2, 0x0078, 0x121f, 0x7814, 0xa086, 0x0018, 0x00c0, - 0x11f3, 0x1078, 0x16cd, 0x7817, 0x0000, 0x2009, 0x3d6f, 0x2104, - 0xa065, 0x0040, 0x120f, 0x0c7e, 0x609c, 0x2060, 0x1078, 0x1a30, - 0x0c7f, 0x609f, 0x0000, 0x1078, 0x17b3, 0x2009, 0x0018, 0x6087, - 0x0103, 0x1078, 0x1959, 0x00c0, 0x121b, 0x1078, 0x19d2, 0x2009, - 0x3d6f, 0x200b, 0x0000, 0x2009, 0x3d69, 0x2104, 0x200b, 0x0000, - 0xa005, 0x0040, 0x121f, 0x2001, 0x4005, 0x0078, 0x12a6, 0x0078, - 0x12a4, 0x007c, 0x70c3, 0x0000, 0x70c7, 0x0000, 0x70cb, 0x0000, - 0x70cf, 0x0000, 0x70c0, 0xa0bc, 0xffc0, 0x00c0, 0x1272, 0x2038, - 0x0079, 0x1232, 0x12a4, 0x12ff, 0x12c3, 0x12ff, 0x1368, 0x1368, - 0x12ba, 0x17cb, 0x1373, 0x12b2, 0x12c7, 0x12c9, 0x12cb, 0x12cd, - 0x17d0, 0x12b2, 0x1385, 0x13c1, 0x16e5, 0x17c5, 0x12cf, 0x15fa, - 0x161c, 0x163a, 0x1667, 0x15b3, 0x15c1, 0x15d5, 0x15e9, 0x1445, - 0x12b2, 0x13f3, 0x13f9, 0x13fe, 0x1403, 0x1409, 0x140e, 0x1413, - 0x1418, 0x141d, 0x1421, 0x1436, 0x1442, 0x12b2, 0x12b2, 0x12b2, - 0x12b2, 0x1451, 0x145a, 0x1469, 0x148f, 0x1499, 0x14a0, 0x14e0, - 0x14ef, 0x14fe, 0x1510, 0x1593, 0x15a3, 0x12b2, 0x12b2, 0x12b2, - 0x12b2, 0x15a8, 0xa0bc, 0xffa0, 0x00c0, 0x12b2, 0x2038, 0xa084, - 0x001f, 0x0079, 0x127b, 0x17e7, 0x17ea, 0x17fa, 0x189f, 0x18d8, - 0x1914, 0x1931, 0x1886, 0x12b2, 0x12b2, 0x1935, 0x193d, 0x12b2, - 0x12b2, 0x12b2, 0x12b2, 0x12f5, 0x135e, 0x137b, 0x13b7, 0x16db, - 0x12b2, 0x12b2, 0x12b2, 0x12b2, 0x1943, 0x18f0, 0x18fa, 0x18fe, - 0x190c, 0x12b2, 0x12b2, 0x72ca, 0x71c6, 0x2001, 0x4006, 0x0078, - 0x12a6, 0x73ce, 0x72ca, 0x71c6, 0x2001, 0x4000, 0x70c2, 0x0068, - 0x12a7, 0x2061, 0x0000, 0x601b, 0x0001, 0x2091, 0x5000, 0x2091, - 0x4080, 0x007c, 0x70c3, 0x4001, 0x0078, 0x12a7, 0x70c3, 0x4006, - 0x0078, 0x12a7, 0x2099, 0x0041, 0x20a1, 0x0041, 0x20a9, 0x0005, - 0x53a3, 0x0078, 0x12a4, 0x70c4, 0x70c3, 0x0004, 0x007a, 0x0078, - 0x12a4, 0x0078, 0x12a4, 0x0078, 0x12a4, 0x0078, 0x12a4, 0x2091, - 0x8000, 0x70c3, 0x0000, 0x70c7, 0x4953, 0x70cb, 0x5020, 0x70cf, - 0x2020, 0x70d3, 0x0004, 0x3f00, 0x70d6, 0x2079, 0x0000, 0x781b, - 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0x3b89, 0x2091, 0x8001, 0x007c, 0x7834, 0x8001, 0x7836, 0x00c0, - 0x3b88, 0x7838, 0x7836, 0x2091, 0x8000, 0x7844, 0xa005, 0x00c0, - 0x3b73, 0x2001, 0x0101, 0x8001, 0x7846, 0xa080, 0x6000, 0x2040, - 0x2004, 0xa065, 0x0040, 0x3b88, 0x6024, 0xa005, 0x0040, 0x3b84, - 0x8001, 0x6026, 0x0040, 0x3bb8, 0x6000, 0x2c40, 0x0078, 0x3b79, - 0x007c, 0x7828, 0x8001, 0x782a, 0x00c0, 0x3bb7, 0x782c, 0x782a, - 0x7830, 0xa005, 0x00c0, 0x3b96, 0x2001, 0x0200, 0x8001, 0x7832, - 0x8003, 0x8003, 0x8003, 0x8003, 0xa090, 0x4000, 0xa298, 0x0002, - 0x2304, 0xa084, 0x0008, 0x0040, 0x3bb7, 0xa290, 0x0009, 0x2204, - 0xa005, 0x0040, 0x3baf, 0x8001, 0x2012, 0x00c0, 0x3bb7, 0x2304, - 0xa084, 0xfff7, 0xa085, 0x0080, 0x201a, 0x1078, 0x1f05, 0x007c, - 0x2069, 0x3d40, 0x6800, 0xa005, 0x0040, 0x3bc2, 0x683c, 0xac06, - 0x0040, 0x3bff, 0x601b, 0x0006, 0x60b4, 0xa084, 0x3f00, 0x601e, - 0x6020, 0xa084, 0x00ff, 0xa085, 0x0060, 0x6022, 0x6000, 0x2042, - 0x6714, 0x6fb6, 0x1078, 0x19f0, 0x6818, 0xa005, 0x0040, 0x3bda, - 0x8001, 0x681a, 0x6808, 0xa084, 0xffef, 0x680a, 0x6810, 0x8001, - 0x00d0, 0x3be4, 0x1078, 0x20c8, 0x6812, 0x602f, 0x0000, 0x6033, - 0x0000, 0x2c68, 0x1078, 0x1b7f, 0x2069, 0x3d40, 0x7944, 0xa184, - 0x0100, 0x2001, 0x0006, 0x68a2, 0x00c0, 0x3bfa, 0x69ba, 0x2001, - 0x0004, 0x68a2, 0x1078, 0x1f00, 0x2091, 0x8001, 0x007c, 0x2009, - 0x3d4f, 0x2164, 0x2069, 0x0100, 0x1078, 0x2073, 0x601b, 0x0006, - 0x6858, 0xa084, 0x3f00, 0x601e, 0x6020, 0xa084, 0x00ff, 0xa085, - 0x0048, 0x6022, 0x602f, 0x0000, 0x6033, 0x0000, 0x6830, 0xa084, - 0x0040, 0x0040, 0x3c3b, 0x684b, 0x0004, 0x20a9, 0x0014, 0x6848, - 0xa084, 0x0004, 0x0040, 0x3c28, 0x0070, 0x3c28, 0x0078, 0x3c1f, - 0x684b, 0x0009, 0x20a9, 0x0014, 0x6848, 0xa084, 0x0001, 0x0040, - 0x3c35, 0x0070, 0x3c35, 0x0078, 0x3c2c, 0x20a9, 0x00fa, 0x0070, - 0x3c3b, 0x0078, 0x3c37, 0x6808, 0xa084, 0xfffd, 0x680a, 0x681b, - 0x0047, 0x2009, 0x3d68, 0x200b, 0x0007, 0x784c, 0x784a, 0x2091, - 0x8001, 0x007c, 0x2079, 0x3d00, 0x1078, 0x3c75, 0x1078, 0x3c59, - 0x1078, 0x3c67, 0x7833, 0x0000, 0x7847, 0x0000, 0x784b, 0x0000, - 0x007c, 0x2019, 0x0003, 0x2011, 0x3d46, 0x2204, 0xa086, 0x003c, - 0x0040, 0x3c64, 0x2019, 0x0002, 0x7b2a, 0x7b2e, 0x007c, 0x2019, - 0x0039, 0x2011, 0x3d46, 0x2204, 0xa086, 0x003c, 0x0040, 0x3c72, - 0x2019, 0x0027, 0x7b36, 0x7b3a, 0x007c, 0x2019, 0x3971, 0x2011, - 0x3d46, 0x2204, 0xa086, 0x003c, 0x0040, 0x3c80, 0x2019, 0x2626, - 0x7b22, 0x7b26, 0x783f, 0x0000, 0x7843, 0x000a, 0x007c, 0x2069, - 0x3d40, 0x6a40, 0xa285, 0x0000, 0x0040, 0x3cce, 0x6944, 0xa080, - 0x3d80, 0x2164, 0x6304, 0x83ff, 0x00c0, 0x3ca1, 0x8211, 0x0040, - 0x3ca4, 0x8108, 0xa11a, 0x0048, 0x3c91, 0x2009, 0x3d80, 0x0078, - 0x3c91, 0x7940, 0x793e, 0x007c, 0x2011, 0x0002, 0x2039, 0x0000, - 0x20a9, 0x0100, 0x1078, 0x19f0, 0x2d00, 0xa088, 0x0002, 0x2168, - 0x682b, 0x0000, 0x682f, 0x0000, 0x2104, 0xa085, 0x0040, 0x200a, - 0x2100, 0xa088, 0x0010, 0x0070, 0x3cbf, 0x0078, 0x3caf, 0x8211, - 0x0040, 0x3cc6, 0x20a9, 0x0100, 0x0078, 0x3caf, 0x2009, 0x3d51, - 0x200b, 0x3d7f, 0x2009, 0x3d50, 0x200b, 0x0000, 0x007c, 0x4de2 -}; -#endif diff --git a/sys/dev/ispfw/asm_1080.h b/sys/dev/ispfw/asm_1080.h deleted file mode 100644 index 3bb1753abbe..00000000000 --- a/sys/dev/ispfw/asm_1080.h +++ /dev/null @@ -1,2001 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-3-Clause - * - * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2000 Qlogic, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms are permitted provided - * that the following conditions are met: - * 1. Redistribution of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistribution in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/************************************************************************ - * * - * --- ISP1240/ISP1080/ISP1280 Initiator Firmware --- * - * 32 LUN Support * - * * - ************************************************************************/ -/* - * Firmware Version 8.15.00 (14:35 Aug 22, 2000) - */ -#ifdef ISP_1080 -static const u_int16_t isp_1080_risc_code[] = { - 0x0078, 0x1041, 0x0000, 0x3d3b, 0x0000, 0x2043, 0x4f50, 0x5952, - 0x4947, 0x4854, 0x2031, 0x3939, 0x312c, 0x3139, 0x3932, 0x2c31, - 0x3939, 0x332c, 0x3139, 0x3934, 0x2051, 0x4c4f, 0x4749, 0x4320, - 0x434f, 0x5250, 0x4f52, 0x4154, 0x494f, 0x4e00, 0x2049, 0x5350, - 0x3132, 0x3430, 0x2046, 0x6972, 0x6d77, 0x6172, 0x6520, 0x2056, - 0x6572, 0x7369, 0x6f6e, 0x2030, 0x382e, 0x3135, 0x2020, 0x2043, - 0x7573, 0x746f, 0x6d65, 0x7220, 0x4e6f, 0x2e20, 0x3030, 0x2050, - 0x726f, 0x6475, 0x6374, 0x204e, 0x6f2e, 0x2020, 0x3030, 0x2020, - 0x2400, 0x20c9, 0x97ff, 0x2001, 0x04fc, 0x2004, 0xa086, 0x1080, - 0x00c0, 0x1054, 0x2071, 0x0100, 0x70a0, 0x70a2, 0x20c1, 0x0010, - 0x2089, 0x1374, 0x0078, 0x106d, 0x2001, 0x04fc, 0x2004, 0xa086, - 0x1280, 0x00c0, 0x1069, 0x2071, 0x0200, 0x70a0, 0x70a2, 0x2071, - 0x0100, 0x70a0, 0x70a2, 0x20c1, 0x0010, 0x2089, 0x13f8, 0x0078, - 0x106d, 0x20c1, 0x0020, 0x2089, 0x131c, 0x2071, 0x0010, 0x70c3, - 0x0004, 0x70c7, 0x4953, 0x70cb, 0x5020, 0x70cf, 0x2020, 0x70d3, - 0x0008, 0x2001, 0x04fe, 0x70d6, 0x20c1, 0x0021, 0x2019, 0x0000, - 0x2009, 0xfeff, 0x2100, 0x200b, 0xa5a5, 0xa1ec, 0x7fff, 0x2d64, - 0x206b, 0x0a0a, 0xaddc, 0x3fff, 0x2b54, 0x205b, 0x5050, 0x2114, - 0xa286, 0xa5a5, 0x0040, 0x10a4, 0xa386, 0x000f, 0x0040, 0x10a0, - 0x2c6a, 0x2a5a, 0x20c1, 0x0020, 0x2019, 0x000f, 0x0078, 0x1080, - 0x2c6a, 0x2a5a, 0x0078, 0x10a2, 0x2c6a, 0x2a5a, 0x2130, 0x2128, - 0xa1a2, 0x4e00, 0x8424, 0x8424, 0x8424, 0x8424, 0x8424, 0x8424, - 0xa192, 0x9800, 0x2009, 0x0000, 0x2001, 0x0032, 0x1078, 0x207a, - 0x2218, 0x2079, 0x4e00, 0x2fa0, 0x2408, 0x2011, 0x0000, 0x20a9, - 0x0040, 0x42a4, 0x8109, 0x00c0, 0x10bf, 0x2009, 0xff00, 0x3400, - 0xa102, 0x0048, 0x10cf, 0x0040, 0x10cf, 0x20a8, 0x42a4, 0x2001, - 0x04fc, 0x2004, 0xa086, 0x1080, 0x00c0, 0x10e5, 0x2071, 0x0100, - 0x0d7e, 0x2069, 0x4e40, 0x1078, 0x4cdd, 0x0d7f, 0x7810, 0xc0ed, - 0x7812, 0x781b, 0x0064, 0x0078, 0x110a, 0x2001, 0x04fc, 0x2004, - 0xa086, 0x1280, 0x00c0, 0x1105, 0x7814, 0xc0ed, 0xc0d5, 0x7816, - 0x781b, 0x0064, 0x2071, 0x0200, 0x0d7e, 0x2069, 0x4e40, 0x1078, - 0x4cdd, 0x2069, 0x4e80, 0x2071, 0x0100, 0x1078, 0x4cdd, 0x7814, - 0xc0d4, 0x7816, 0x0d7f, 0x0078, 0x110a, 0x7814, 0xc0e5, 0x7816, - 0x781b, 0x003c, 0x7eca, 0x7cc2, 0x7bc6, 0x7867, 0x0000, 0x7800, - 0xc08d, 0x7802, 0x2031, 0x0030, 0x78af, 0x0101, 0x7823, 0x0002, - 0x7827, 0x0002, 0x2009, 0x0002, 0x2069, 0x4e40, 0x681b, 0x0003, - 0x6823, 0x0007, 0x6827, 0x00fa, 0x682b, 0x0008, 0x682f, 0x0028, - 0x6837, 0x0000, 0x683b, 0x0006, 0x6833, 0x0008, 0x683f, 0x0000, - 0x8109, 0x0040, 0x115e, 0x68d3, 0x000a, 0x68c3, 0x4ec0, 0x2079, - 0x4e00, 0x7814, 0xd0e4, 0x00c0, 0x1144, 0xd0ec, 0x00c0, 0x1148, - 0x68d7, 0x7329, 0x0078, 0x114a, 0x68d7, 0x730d, 0x0078, 0x114a, - 0x68d7, 0x732d, 0x68c7, 0x53c0, 0x68cb, 0x52c0, 0x68cf, 0x93c0, - 0x68ab, 0x9644, 0x68af, 0x9649, 0x68b3, 0x9644, 0x68b7, 0x9644, - 0x68a7, 0x0001, 0x2069, 0x4e80, 0x0078, 0x111e, 0x68d3, 0x000a, - 0x68c3, 0x50c0, 0x7814, 0xd0e4, 0x00c0, 0x116a, 0x68d7, 0x7439, - 0x0078, 0x116c, 0x68d7, 0x7419, 0x68c7, 0x73c0, 0x68cb, 0x5340, - 0x68cf, 0x94d0, 0x68ab, 0x9649, 0x68af, 0x964e, 0x68b3, 0x9649, - 0x68b7, 0x9649, 0x68a7, 0x0001, 0x7810, 0xd0ec, 0x00c0, 0x11c2, - 0x7814, 0xd0e4, 0x00c0, 0x11b4, 0x0e7e, 0x2069, 0x52c0, 0x2071, - 0x0200, 0x70ec, 0xd0e4, 0x00c0, 0x1195, 0x2019, 0x0c0c, 0x2021, - 0x000c, 0x1078, 0x2009, 0x0078, 0x119b, 0x2019, 0x0c0a, 0x2021, - 0x000a, 0x1078, 0x2009, 0x2069, 0x5340, 0x2071, 0x0100, 0x70ec, - 0xd0e4, 0x00c0, 0x11ab, 0x2019, 0x0c0c, 0x2021, 0x000c, 0x1078, - 0x2009, 0x0078, 0x11b1, 0x2019, 0x0c0a, 0x2021, 0x000a, 0x1078, - 0x2009, 0x0e7f, 0x0078, 0x11db, 0x2019, 0x0c0c, 0x2021, 0x000c, - 0x2069, 0x52c0, 0x1078, 0x2009, 0x2069, 0x5340, 0x1078, 0x2009, - 0x0078, 0x11db, 0x2069, 0x52c0, 0x0e7e, 0x2071, 0x0100, 0x70ec, - 0xd0e4, 0x00c0, 0x11d4, 0x2019, 0x0c0c, 0x2021, 0x000c, 0x1078, - 0x2009, 0x0e7f, 0x0078, 0x11db, 0x2019, 0x0c0a, 0x2021, 0x000a, - 0x1078, 0x2009, 0x0e7f, 0x2011, 0x0002, 0x2069, 0x53c0, 0x2009, - 0x0002, 0x20a9, 0x0100, 0x6837, 0x0000, 0x680b, 0x0040, 0x7bc8, - 0xa386, 0xfeff, 0x00c0, 0x11f2, 0x6817, 0x0100, 0x681f, 0x0064, - 0x0078, 0x11f6, 0x6817, 0x0064, 0x681f, 0x0002, 0xade8, 0x0010, - 0x00f0, 0x11e3, 0x8109, 0x00c0, 0x11e1, 0x8211, 0x0040, 0x1204, - 0x2069, 0x73c0, 0x0078, 0x11df, 0x1078, 0x265b, 0x1078, 0x468e, - 0x1078, 0x1dd4, 0x1078, 0x4c6f, 0x2091, 0x2100, 0x2079, 0x4e00, - 0x7810, 0xd0ec, 0x0040, 0x1218, 0x2071, 0x0020, 0x0078, 0x121a, - 0x2071, 0x0050, 0x2091, 0x2200, 0x2079, 0x4e00, 0x2071, 0x0020, - 0x2091, 0x2300, 0x2079, 0x4e00, 0x7810, 0xd0ec, 0x0040, 0x122c, - 0x2079, 0x0100, 0x0078, 0x122e, 0x2079, 0x0200, 0x2071, 0x4e40, - 0x2091, 0x2400, 0x2079, 0x0100, 0x2071, 0x4e80, 0x2091, 0x2000, - 0x2079, 0x4e00, 0x2071, 0x0010, 0x3200, 0xa085, 0x303d, 0x2090, - 0x2071, 0x0010, 0x70c3, 0x0000, 0x0090, 0x124d, 0x70c0, 0xa086, - 0x0002, 0x00c0, 0x124d, 0x1078, 0x15ba, 0x2039, 0x0000, 0x7810, - 0xd0ec, 0x00c0, 0x12cf, 0x1078, 0x148e, 0x78ac, 0xa005, 0x00c0, - 0x126b, 0x0068, 0x1261, 0x786c, 0xa065, 0x0040, 0x1261, 0x1078, - 0x2395, 0x1078, 0x20a1, 0x0068, 0x1278, 0x786c, 0xa065, 0x0040, - 0x126b, 0x1078, 0x2395, 0x0068, 0x1278, 0x2009, 0x4e47, 0x2011, - 0x4e87, 0x2104, 0x220c, 0xa105, 0x0040, 0x1278, 0x1078, 0x1f0a, - 0x2071, 0x4e40, 0x70a4, 0xa005, 0x0040, 0x129d, 0x7450, 0xa485, - 0x0000, 0x0040, 0x129d, 0x2079, 0x0200, 0x2091, 0x8000, 0x72d4, - 0xa28c, 0x303d, 0x2190, 0x1078, 0x2b6a, 0x2091, 0x8000, 0x2091, - 0x303d, 0x0068, 0x129d, 0x2079, 0x4e00, 0x786c, 0xa065, 0x0040, - 0x129d, 0x2071, 0x0010, 0x1078, 0x2395, 0x00e0, 0x12a5, 0x2079, - 0x4e00, 0x2071, 0x0010, 0x1078, 0x4a43, 0x2071, 0x4e80, 0x70a4, - 0xa005, 0x0040, 0x12bd, 0x7050, 0xa025, 0x0040, 0x12bd, 0x2079, - 0x0100, 0x2091, 0x8000, 0x72d4, 0xa28c, 0x303d, 0x2190, 0x1078, - 0x2b6a, 0x2091, 0x8000, 0x2091, 0x303d, 0x2079, 0x4e00, 0x2071, - 0x0010, 0x0068, 0x12c9, 0x786c, 0xa065, 0x0040, 0x12c9, 0x1078, - 0x2395, 0x00e0, 0x1253, 0x1078, 0x4a43, 0x0078, 0x1253, 0x1078, - 0x148e, 0x78ac, 0xa005, 0x00c0, 0x12e7, 0x0068, 0x12dd, 0x786c, - 0xa065, 0x0040, 0x12dd, 0x1078, 0x2395, 0x1078, 0x20a1, 0x0068, - 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0x7007, 0x0010, 0x7108, 0xd1fc, 0x0040, 0x49e2, 0x1078, 0x4769, - 0x7008, 0xa086, 0x0008, 0x00c0, 0x49cd, 0x7000, 0xa005, 0x00c0, - 0x49cd, 0x7003, 0x0000, 0x2049, 0x0000, 0x127f, 0x2000, 0x007c, - 0x127e, 0x147e, 0x137e, 0x157e, 0x0c7e, 0x0d7e, 0x70d4, 0xa084, - 0x4600, 0x8004, 0x2090, 0x0d7f, 0x2049, 0x49f8, 0xad80, 0x0011, - 0x20a0, 0xb284, 0x0100, 0x0040, 0x4a1b, 0x2001, 0x4e04, 0x2004, - 0xd0ec, 0x0040, 0x4a17, 0x2099, 0x0031, 0x0078, 0x4a1d, 0x2099, - 0x0032, 0x0078, 0x4a1d, 0x2099, 0x0031, 0x700c, 0xa084, 0x03ff, - 0x682a, 0x7007, 0x0008, 0x7007, 0x0002, 0x7003, 0x0001, 0x0040, - 0x4a2c, 0x8000, 0x80ac, 0x53a5, 0x700c, 0xa084, 0x03ff, 0x0040, - 0x4a38, 0x7007, 0x0004, 0x7004, 0xa084, 0x0004, 0x00c0, 0x4a33, - 0x0c7f, 0x2049, 0x0000, 0x7003, 0x0000, 0x157f, 0x137f, 0x147f, - 0x127f, 0x2000, 0x007c, 0x2091, 0x8000, 0x2091, 0x6000, 0x78ac, - 0xa005, 0x00c0, 0x4a5a, 0x7974, 0x70d0, 0xa106, 0x00c0, 0x4a5a, - 0x781c, 0xa005, 0x0040, 0x4a5a, 0x781f, 0x0000, 0x0068, 0x4a5a, - 0x2091, 0x4080, 0x7830, 0x8001, 0x7832, 0x00c0, 0x4ae2, 0x7834, - 0x7832, 0x7810, 0xd0ec, 0x00c0, 0x4adb, 0x2061, 0x73c0, 0x2069, - 0x4e80, 0xc7fd, 0x68d0, 0xa005, 0x0040, 0x4a74, 0x8001, 0x68d2, - 0x00c0, 0x4a74, 0x1078, 0x4cb0, 0x6800, 0xa084, 0x000f, 0x0040, - 0x4a89, 0xa086, 0x0001, 0x0040, 0x4a89, 0x6844, 0xa00d, 0x0040, - 0x4a89, 0x2104, 0xa005, 0x0040, 0x4a89, 0x8001, 0x200a, 0x0040, - 0x4c23, 0x6814, 0xa005, 0x0040, 0x4aae, 0x8001, 0x6816, 0x00c0, - 0x4aae, 0x68a7, 0x0001, 0x0f7e, 0xd7fc, 0x00c0, 0x4aa3, 0x7810, - 0xd0ec, 0x0040, 0x4a9f, 0x2079, 0x0100, 0x0078, 0x4aa5, 0x2079, - 0x0200, 0x0078, 0x4aa5, 0x2079, 0x0100, 0x1078, 0x4383, 0x0f7f, - 0x6864, 0xa005, 0x0040, 0x4aae, 0x1078, 0x2628, 0x6880, 0xa005, - 0x0040, 0x4abb, 0x8001, 0x6882, 0x00c0, 0x4abb, 0x6867, 0x0000, - 0x68d4, 0xc0dd, 0x68d6, 0x68d4, 0xd0fc, 0x0040, 0x4ad8, 0xc0fc, - 0x68d6, 0x20a9, 0x0200, 0x6034, 0xa005, 0x0040, 0x4ad4, 0x8001, - 0x6036, 0x68d4, 0xc0fd, 0x68d6, 0x00c0, 0x4ad4, 0x6010, 0xa005, - 0x0040, 0x4ad4, 0x1078, 0x2628, 0xace0, 0x0010, 0x00f0, 0x4ac3, - 0xd7fc, 0x0040, 0x4ae2, 0x2061, 0x53c0, 0x2069, 0x4e40, 0xc7fc, - 0x0078, 0x4a6a, 0x1078, 0x4b1e, 0x7838, 0x8001, 0x783a, 0x00c0, - 0x4b04, 0x783c, 0x783a, 0x2061, 0x53c0, 0x2069, 0x4e40, 0xc7fc, - 0x680c, 0xa005, 0x0040, 0x4af6, 0x1078, 0x4b88, 0xd7fc, 0x00c0, - 0x4b04, 0x7810, 0xd0ec, 0x00c0, 0x4b04, 0x2061, 0x73c0, 0x2069, - 0x4e80, 0xc7fd, 0x0078, 0x4af0, 0x7814, 0xd0e4, 0x00c0, 0x4b08, - 0x7810, 0xd0cc, 0x0040, 0x4b1b, 0xd0ac, 0x00c0, 0x4b14, 0xd0a4, - 0x0040, 0x4b1b, 0xc0ad, 0x7812, 0x2091, 0x8001, 0x0068, 0x4b1a, - 0x1078, 0x2395, 0x007c, 0x2091, 0x8001, 0x007c, 0x7840, 0x8001, - 0x7842, 0x00c0, 0x4b87, 0x7844, 0x7842, 0x2069, 0x4e40, 0xc7fc, - 0x7810, 0x2079, 0x0200, 0xd0ec, 0x0040, 0x4b30, 0x2079, 0x0100, - 0x68d8, 0xa005, 0x0040, 0x4b3c, 0x7de0, 0xa504, 0x00c0, 0x4b3c, - 0x68da, 0x68d4, 0xc0bc, 0x68d6, 0x2079, 0x4e00, 0x6810, 0xa005, - 0x00c0, 0x4b44, 0x2001, 0x0101, 0x8001, 0x6812, 0xd7fc, 0x0040, - 0x4b4d, 0xa080, 0x94d0, 0x0078, 0x4b4f, 0xa080, 0x93c0, 0x2040, - 0x2004, 0xa065, 0x0040, 0x4b79, 0x6024, 0xa005, 0x0040, 0x4b75, - 0x8001, 0x6026, 0x00c0, 0x4b75, 0x6800, 0xa005, 0x0040, 0x4b68, - 0x684c, 0xac06, 0x00c0, 0x4b68, 0x1078, 0x4c23, 0x0078, 0x4b79, - 0x6864, 0xa005, 0x0040, 0x4b70, 0x6027, 0x0001, 0x0078, 0x4b75, - 0x1078, 0x4bd6, 0x2804, 0x0078, 0x4b51, 0x6000, 0x2c40, 0x0078, - 0x4b51, 0xd7fc, 0x00c0, 0x4b87, 0x7810, 0xd0ec, 0x00c0, 0x4b87, - 0x2069, 0x4e80, 0xc7fd, 0x2079, 0x0100, 0x0078, 0x4b30, 0x007c, - 0x2009, 0x0000, 0x20a9, 0x0200, 0x6008, 0xd09c, 0x0040, 0x4bc2, - 0x6024, 0xa005, 0x0040, 0x4b98, 0x8001, 0x6026, 0x0078, 0x4bc0, - 0x6008, 0xc09c, 0xd084, 0x00c0, 0x4ba0, 0xd0ac, 0x0040, 0x4bba, - 0x600a, 0x6004, 0xa005, 0x0040, 0x4bc2, 0x0d7e, 0x0c7e, 0x017e, - 0x2068, 0x6010, 0x8001, 0x6012, 0x1078, 0x3dd0, 0x2d00, 0x2c68, - 0x2060, 0x1078, 0x1e5b, 0x1078, 0x201d, 0x017f, 0x0c7f, 0x0d7f, - 0x0078, 0x4bc2, 0xc0bd, 0x600a, 0xa18d, 0x0001, 0x0078, 0x4bc2, - 0xa18d, 0x0100, 0xace0, 0x0010, 0x00f0, 0x4b8c, 0xa184, 0x0001, - 0x0040, 0x4bd1, 0xa18c, 0xfffe, 0x690e, 0x1078, 0x2628, 0x0078, - 0x4bd2, 0x690e, 0x007c, 0x00c0, 0x4bd2, 0x786c, 0x2c00, 0x687e, - 0x6714, 0x6f76, 0x6017, 0x0000, 0x602b, 0x0000, 0x601b, 0x0006, - 0x60b4, 0xa084, 0x3f00, 0x601e, 0x6020, 0xa084, 0x00ff, 0xa085, - 0x0060, 0x6022, 0x6000, 0x2042, 0x1078, 0x1de4, 0x6818, 0xa005, - 0x0040, 0x4bf4, 0x8001, 0x681a, 0x6808, 0xc0a4, 0x680a, 0x6810, - 0x7908, 0x8109, 0x790a, 0x8001, 0x00d0, 0x4c00, 0x1078, 0x296b, - 0x6812, 0x00c0, 0x4c06, 0x7910, 0xc1a5, 0x7912, 0x602f, 0x0000, - 0x6033, 0x0000, 0x2c68, 0x1078, 0x202c, 0xd7fc, 0x00c0, 0x4c14, - 0x2069, 0x4e40, 0x0078, 0x4c16, 0x2069, 0x4e80, 0x6910, 0xa184, - 0x0100, 0x2001, 0x0006, 0x00c0, 0x4c20, 0x697a, 0x2001, 0x0004, - 0x1078, 0x261c, 0x007c, 0x0d7e, 0x694c, 0x2160, 0xd7fc, 0x00c0, - 0x4c35, 0x7810, 0xd0ec, 0x0040, 0x4c31, 0x2069, 0x0100, 0x0078, - 0x4c37, 0x2069, 0x0200, 0x0078, 0x4c37, 0x2069, 0x0100, 0x1078, - 0x28df, 0x601b, 0x0006, 0x6858, 0xa084, 0x3f00, 0x601e, 0x6020, - 0xa084, 0x00ff, 0xa085, 0x0048, 0x6022, 0x602f, 0x0000, 0x6033, - 0x0000, 0x6808, 0xa084, 0xfffd, 0x680a, 0x6830, 0xd0b4, 0x0040, - 0x4c69, 0x684b, 0x0004, 0x20a9, 0x0014, 0x6848, 0xd094, 0x0040, - 0x4c5b, 0x00f0, 0x4c55, 0x684b, 0x0009, 0x20a9, 0x0014, 0x6848, - 0xd084, 0x0040, 0x4c65, 0x00f0, 0x4c5f, 0x20a9, 0x00fa, 0x00f0, - 0x4c67, 0x681b, 0x0047, 0x0d7f, 0x6867, 0x0007, 0x007c, 0x2079, - 0x4e00, 0x1078, 0x4ca3, 0x1078, 0x4c89, 0x1078, 0x4c96, 0x2009, - 0x0002, 0x2069, 0x4e80, 0x680f, 0x0000, 0x6813, 0x0000, 0x6817, - 0x0000, 0x8109, 0x0040, 0x4c88, 0x2069, 0x4e40, 0x0078, 0x4c7b, - 0x007c, 0x7810, 0xd0ec, 0x0040, 0x4c91, 0x2019, 0x00cc, 0x0078, - 0x4c93, 0x2019, 0x007b, 0x7b3a, 0x7b3e, 0x007c, 0x7814, 0xd0e4, - 0x00c0, 0x4c9e, 0x2019, 0x0040, 0x0078, 0x4ca0, 0x2019, 0x0026, - 0x7b42, 0x7b46, 0x007c, 0x7814, 0xd0e4, 0x00c0, 0x4cab, 0x2019, - 0x3f94, 0x0078, 0x4cad, 0x2019, 0x2624, 0x7b32, 0x7b36, 0x007c, - 0x6a50, 0xa285, 0x0000, 0x0040, 0x4cdc, 0x6954, 0x6bc0, 0xa300, - 0x0c7e, 0x2164, 0x6304, 0x83ff, 0x00c0, 0x4cc8, 0x8211, 0x0040, - 0x4ccc, 0x8108, 0xa11a, 0x0048, 0x4cb9, 0x69c0, 0x0078, 0x4cb9, - 0x68d3, 0x000a, 0x0c7f, 0x007c, 0x6950, 0x6ac0, 0x2264, 0x602b, - 0x0000, 0x602f, 0x0000, 0x6008, 0xc0b5, 0x600a, 0x8210, 0x8109, - 0x00c0, 0x4cce, 0x6952, 0x0c7f, 0x007c, 0x00e0, 0x4cdd, 0x2091, - 0x6000, 0x00e0, 0x4ce1, 0x2091, 0x6000, 0x70ec, 0xd0dc, 0x00c0, - 0x4cee, 0xd0d4, 0x0040, 0x4d17, 0x0078, 0x4d1a, 0x2008, 0x7810, - 0xd0ec, 0x0040, 0x4d01, 0xd1c4, 0x00c0, 0x4d39, 0x7814, 0xc0c5, - 0x7816, 0x7810, 0xc0f5, 0x7812, 0xd0ec, 0x0040, 0x4d35, 0x0078, - 0x4d31, 0xae8e, 0x0100, 0x0040, 0x4d0e, 0x7814, 0xc0f5, 0xc0c5, - 0x7816, 0xd0d4, 0x00c0, 0x4d35, 0x0078, 0x4d31, 0x7814, 0xc0fd, - 0xc0c5, 0x7816, 0xd0d4, 0x00c0, 0x4d35, 0x0078, 0x4d31, 0xd0e4, - 0x0040, 0x4d37, 0x00e0, 0x4d1a, 0x2091, 0x6000, 0x2009, 0x000c, - 0x00e0, 0x4d20, 0x2091, 0x6000, 0x8109, 0x00c0, 0x4d20, 0x70e4, - 0xa084, 0x01ff, 0xa086, 0x01ff, 0x00c0, 0x4d31, 0x70ec, 0x0078, - 0x4cee, 0x7804, 0xd08c, 0x0040, 0x4d37, 0x681f, 0x000c, 0x70a0, - 0x70a2, 0x007c, 0x205b -}; -#endif diff --git a/sys/dev/ispfw/asm_12160.h b/sys/dev/ispfw/asm_12160.h deleted file mode 100644 index 7581712aaf5..00000000000 --- a/sys/dev/ispfw/asm_12160.h +++ /dev/null @@ -1,1795 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-3-Clause - * - * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2000 Qlogic, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms are permitted provided - * that the following conditions are met: - * 1. Redistribution of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistribution in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/************************************************************************ - * * - * --- ISP12160A Initiator/Target RISC Firmware --- * - * 32 LUN Support * - * * - ************************************************************************/ -/* - * Firmware Version 10.04.41 (10:30 Mar 21, 2003) - */ -#ifdef ISP_12160 -static const u_int16_t isp_12160_risc_code[] = { - 0x0804, 0x1041, 0x0000, 0x36c9, 0x0000, 0x2043, 0x4f50, 0x5952, - 0x4947, 0x4854, 0x2031, 0x3939, 0x312c, 0x3139, 0x3932, 0x2c31, - 0x3939, 0x332c, 0x3139, 0x3934, 0x2051, 0x4c4f, 0x4749, 0x4320, - 0x434f, 0x5250, 0x4f52, 0x4154, 0x494f, 0x4e00, 0x2049, 0x5350, - 0x3132, 0x3136, 0x2046, 0x6972, 0x6d77, 0x6172, 0x6520, 0x2056, - 0x6572, 0x7369, 0x6f6e, 0x2031, 0x302e, 0x3034, 0x2020, 0x2043, - 0x7573, 0x746f, 0x6d65, 0x7220, 0x4e6f, 0x2e20, 0x3030, 0x2050, - 0x726f, 0x6475, 0x6374, 0x204e, 0x6f2e, 0x2020, 0x3030, 0x2020, - 0x2400, 0x20c9, 0x90ff, 0x2071, 0x0200, 0x70a0, 0x70a2, 0x2001, - 0x01ff, 0x2004, 0xd0fc, 0x1120, 0x2071, 0x0100, 0x70a0, 0x70a2, - 0x20c1, 0x0020, 0x2089, 0x1221, 0x2071, 0x0010, 0x70c3, 0x0004, - 0x70c7, 0x4953, 0x70cb, 0x5020, 0x70cf, 0x2020, 0x70d3, 0x000a, - 0x2001, 0x04fd, 0x2004, 0x70d6, 0x2009, 0xfeff, 0x2130, 0x2128, - 0xa1a2, 0x4700, 0x8424, 0x8424, 0x8424, 0x8424, 0x8424, 0x8424, - 0xa192, 0x9100, 0x2009, 0x0000, 0x2001, 0x0032, 0x080c, 0x1e05, - 0x2218, 0x2079, 0x4700, 0x2fa0, 0x2408, 0x2011, 0x0000, 0x20a9, - 0x0040, 0x42a4, 0x8109, 0x1dd8, 0x2009, 0xff00, 0x3400, 0xa102, - 0x0218, 0x0110, 0x20a8, 0x42a4, 0x781b, 0x0064, 0x7814, 0xc0cd, - 0xc0d5, 0x7816, 0x2071, 0x0200, 0x00d6, 0x2069, 0x4740, 0x080c, - 0x465c, 0x2001, 0x01ff, 0x2004, 0xd0fc, 0x1130, 0x2069, 0x4780, - 0x2071, 0x0100, 0x080c, 0x465c, 0x7814, 0xc0d4, 0x7816, 0x00de, - 0x7eca, 0x7cc2, 0x7bc6, 0x7867, 0x0000, 0x7800, 0xc08d, 0x7802, - 0x2031, 0x0030, 0x78af, 0x0101, 0x7823, 0x0002, 0x7827, 0x0002, - 0x2009, 0x0002, 0x2069, 0x4740, 0x681b, 0x0003, 0x6823, 0x0007, - 0x6827, 0x00fa, 0x682b, 0x0008, 0x682f, 0x0028, 0x6837, 0x0006, - 0x6833, 0x0008, 0x683b, 0x0000, 0x8109, 0x0500, 0x68cf, 0x000a, - 0x68bf, 0x47c0, 0x2079, 0x4700, 0x68d3, 0x762d, 0x68c3, 0x4cc0, - 0x68c7, 0x4bc0, 0x68cb, 0x8cc0, 0x68a7, 0x8f44, 0x68ab, 0x8f49, - 0x68af, 0x8f44, 0x68b3, 0x8f44, 0x68a3, 0x0001, 0x2001, 0x01ff, - 0x2004, 0xd0fc, 0x11c8, 0x2069, 0x4780, 0x0870, 0x68cf, 0x000a, - 0x68bf, 0x49c0, 0x68d3, 0x7839, 0x68c3, 0x6cc0, 0x68c7, 0x4c40, - 0x68cb, 0x8dd0, 0x68a7, 0x8f49, 0x68ab, 0x8f4e, 0x68af, 0x8f49, - 0x68b3, 0x8f49, 0x68a3, 0x0001, 0x00e6, 0x2069, 0x4bc0, 0x2071, - 0x0200, 0x70ec, 0xd0e4, 0x2019, 0x1809, 0x2021, 0x0009, 0x1120, - 0x2019, 0x180c, 0x2021, 0x000c, 0x080c, 0x1d75, 0x2001, 0x01ff, - 0x2004, 0xd0fc, 0x1188, 0x2069, 0x4c40, 0x2071, 0x0100, 0x70ec, - 0xd0e4, 0x2019, 0x1809, 0x2021, 0x0009, 0x1120, 0x2019, 0x180c, - 0x2021, 0x000c, 0x080c, 0x1d75, 0x00ee, 0x2011, 0x0002, 0x2069, - 0x4cc0, 0x2009, 0x0002, 0x20a9, 0x0100, 0x6837, 0x0000, 0x680b, - 0x0040, 0x7bc8, 0xa386, 0xfeff, 0x1128, 0x6817, 0x0100, 0x681f, - 0x0064, 0x0020, 0x6817, 0x0064, 0x681f, 0x0002, 0xade8, 0x0010, - 0x1f04, 0x1135, 0x8109, 0x1d38, 0x2001, 0x01ff, 0x2004, 0xd0fc, - 0x1128, 0x8211, 0x0118, 0x2069, 0x6cc0, 0x08d8, 0x080c, 0x22f6, - 0x080c, 0x403d, 0x080c, 0x1b8c, 0x080c, 0x4615, 0x2091, 0x2200, - 0x2079, 0x4700, 0x2071, 0x0050, 0x2091, 0x2400, 0x2079, 0x4700, - 0x2071, 0x0020, 0x2091, 0x2600, 0x2079, 0x0200, 0x2071, 0x4740, - 0x2091, 0x2800, 0x2079, 0x0100, 0x2071, 0x4780, 0x2091, 0x2000, - 0x2079, 0x4700, 0x2071, 0x0010, 0x3200, 0xa085, 0x303d, 0x2090, - 0x2071, 0x0010, 0x70c3, 0x0000, 0x1004, 0x118c, 0x70c0, 0xa086, - 0x0002, 0x1110, 0x080c, 0x13ba, 0x2039, 0x0000, 0x080c, 0x12ab, - 0x78ac, 0xa005, 0x1180, 0x0e04, 0x119a, 0x786c, 0xa065, 0x0110, - 0x080c, 0x20a1, 0x080c, 0x1e26, 0x0e04, 0x11af, 0x786c, 0xa065, - 0x0110, 0x080c, 0x20a1, 0x0e04, 0x11af, 0x2009, 0x4747, 0x2011, - 0x4787, 0x2104, 0x220c, 0xa105, 0x0110, 0x080c, 0x1c9b, 0x2071, - 0x4740, 0x70a0, 0xa005, 0x01e8, 0x744c, 0xa485, 0x0000, 0x01c8, - 0x2079, 0x0200, 0x2091, 0x8000, 0x72d0, 0xa28c, 0x303d, 0x2190, - 0x080c, 0x274c, 0x2091, 0x8000, 0x2091, 0x303d, 0x0e04, 0x11d1, - 0x2079, 0x4700, 0x786c, 0xa065, 0x0120, 0x2071, 0x0010, 0x080c, - 0x20a1, 0x1d04, 0x11d9, 0x2079, 0x4700, 0x2071, 0x0010, 0x080c, - 0x4429, 0x2071, 0x4780, 0x70a0, 0xa005, 0x0188, 0x704c, 0xa025, - 0x0170, 0x2079, 0x0100, 0x2091, 0x8000, 0x72d0, 0xa28c, 0x303d, - 0x2190, 0x080c, 0x274c, 0x2091, 0x8000, 0x2091, 0x303d, 0x2079, - 0x4700, 0x2071, 0x0010, 0x0e04, 0x11fa, 0x786c, 0xa065, 0x0110, - 0x080c, 0x20a1, 0x1d04, 0x118e, 0x080c, 0x4429, 0x0804, 0x118e, - 0x3c00, 0xa084, 0x0007, 0x0002, 0x120c, 0x120c, 0x120e, 0x120e, - 0x1213, 0x1213, 0x1218, 0x1218, 0x080c, 0x2575, 0x2091, 0x2400, - 0x080c, 0x40d5, 0x0005, 0x2091, 0x2200, 0x080c, 0x40d5, 0x0005, - 0x2091, 0x2200, 0x080c, 0x40d5, 0x2091, 0x2400, 0x080c, 0x40d5, - 0x0005, 0x1241, 0x1241, 0x1242, 0x1242, 0x124d, 0x124d, 0x124d, - 0x124d, 0x1256, 0x1256, 0x1261, 0x1261, 0x124d, 0x124d, 0x124d, - 0x124d, 0x1270, 0x1270, 0x1270, 0x1270, 0x1270, 0x1270, 0x1270, - 0x1270, 0x1270, 0x1270, 0x1270, 0x1270, 0x1270, 0x1270, 0x1270, - 0x1270, 0x0cf8, 0x0006, 0x0106, 0x0126, 0x2091, 0x2800, 0x080c, - 0x2592, 0x012e, 0x010e, 0x000e, 0x000d, 0x0006, 0x0106, 0x0126, - 0x080c, 0x1200, 0x012e, 0x010e, 0x000e, 0x000d, 0x0006, 0x0106, - 0x0126, 0x2091, 0x2600, 0x080c, 0x2592, 0x012e, 0x010e, 0x000e, - 0x000d, 0x0006, 0x0106, 0x0126, 0x2091, 0x2600, 0x080c, 0x2592, - 0x2091, 0x2800, 0x080c, 0x2592, 0x012e, 0x010e, 0x000e, 0x000d, - 0x0006, 0x0106, 0x0126, 0x00d6, 0x00e6, 0x00f6, 0x2079, 0x4700, - 0x2071, 0x0200, 0x2069, 0x4740, 0x3d00, 0xd08c, 0x0130, 0x70ec, - 0xa084, 0x1c00, 0x78e2, 0x080c, 0x465c, 0x3d00, 0xd084, 0x0150, - 0x2069, 0x4780, 0x2071, 0x0100, 0x70ec, 0xa084, 0x1c00, 0x78e6, - 0x080c, 0x465c, 0x080c, 0x2526, 0x00fe, 0x00ee, 0x00de, 0x012e, - 0x010e, 0x000e, 0x000d, 0x7008, 0x800b, 0x1240, 0x7007, 0x0002, - 0xa08c, 0x01e0, 0x1120, 0xd09c, 0x0108, 0x0887, 0x0897, 0x70c3, - 0x4002, 0x0804, 0x13bd, 0x0e04, 0x131e, 0x2061, 0x0000, 0x6018, - 0xd084, 0x1904, 0x131e, 0x7828, 0xa005, 0x1120, 0x0004, 0x131f, - 0x0804, 0x131e, 0xd0fc, 0x0130, 0x0006, 0x080c, 0x1b29, 0x000e, - 0x0150, 0x0028, 0x0006, 0x080c, 0x1b1e, 0x000e, 0x0120, 0x2001, - 0x4007, 0x0804, 0x13bc, 0x7910, 0xd0fc, 0x1128, 0x2061, 0x4740, - 0xc19c, 0xc7fc, 0x0020, 0x2061, 0x4780, 0xc19d, 0xc7fd, 0x6060, - 0xa005, 0x1904, 0x131e, 0x7912, 0x607e, 0x7828, 0xc0fc, 0xa086, - 0x0018, 0x1120, 0x00c6, 0x080c, 0x1926, 0x00ce, 0x782b, 0x0000, - 0x6078, 0xa065, 0x01e0, 0x00c6, 0x609c, 0x080c, 0x1bf3, 0x00ce, - 0x609f, 0x0000, 0x080c, 0x1a60, 0x2009, 0x0018, 0x6087, 0x0103, - 0x7810, 0x0006, 0x84ff, 0x1110, 0x85ff, 0x0110, 0xc0c5, 0x7812, - 0x080c, 0x1b34, 0x000e, 0x7812, 0x1198, 0x080c, 0x1b7f, 0x7810, - 0xd09c, 0x1118, 0x2061, 0x4740, 0x0020, 0x2061, 0x4780, 0xc09c, - 0x7812, 0x607b, 0x0000, 0x60d0, 0xd0c4, 0x0130, 0xc0c4, 0x60d2, - 0x2001, 0x4005, 0x0804, 0x13bc, 0x0804, 0x13ba, 0x0005, 0xa006, - 0x70c2, 0x70c6, 0x70ca, 0x70ce, 0x70da, 0x70c0, 0xa03d, 0xa08a, - 0x0040, 0x1a04, 0x136c, 0x0002, 0x13ba, 0x1408, 0x13d6, 0x143c, - 0x1470, 0x1470, 0x13ce, 0x1a78, 0x147a, 0x13c8, 0x13da, 0x13db, - 0x13dc, 0x13dd, 0x1a7c, 0x13c8, 0x1487, 0x14db, 0x1941, 0x1a72, - 0x13de, 0x17c8, 0x17fe, 0x1830, 0x1876, 0x1785, 0x1792, 0x17a5, - 0x17b7, 0x15bf, 0x13c8, 0x150d, 0x1518, 0x1526, 0x1534, 0x154b, - 0x1559, 0x155c, 0x156e, 0x157c, 0x1586, 0x15a5, 0x15b1, 0x13c8, - 0x13c8, 0x13c8, 0x13c8, 0x15cc, 0x15dd, 0x15f7, 0x162b, 0x1654, - 0x1666, 0x1669, 0x1693, 0x16cc, 0x16de, 0x1753, 0x1763, 0x13c8, - 0x13c8, 0x13c8, 0x13c8, 0x1775, 0x2100, 0xa08a, 0x0040, 0x1a04, - 0x13c8, 0x0002, 0x13c8, 0x13c8, 0x13c8, 0x13c8, 0x13c8, 0x1a9e, - 0x1aa4, 0x13c8, 0x13c8, 0x13c8, 0x1aa8, 0x1ae8, 0x13c8, 0x13c8, - 0x13c8, 0x13c8, 0x1403, 0x146b, 0x1482, 0x14d6, 0x193c, 0x13c8, - 0x13c8, 0x190b, 0x13c8, 0x1aec, 0x1a90, 0x1a9a, 0x13c8, 0x13c8, - 0x13c8, 0x13c8, 0x13c8, 0x13c8, 0x13c8, 0x13c8, 0x13c8, 0x13c8, - 0x13c8, 0x13c8, 0x13c8, 0x13c8, 0x13c8, 0x13c8, 0x13c8, 0x13c8, - 0x13c8, 0x13c8, 0x13c8, 0x13c8, 0x13c8, 0x13c8, 0x13c8, 0x13c8, - 0x13c8, 0x13c8, 0x13c8, 0x13c8, 0x13c8, 0x13c8, 0x13c8, 0x13c8, - 0x13c8, 0x13c8, 0x72ca, 0x71c6, 0x2001, 0x4006, 0x0028, 0x73ce, - 0x72ca, 0x71c6, 0x2001, 0x4000, 0x70c2, 0x0e04, 0x13bd, 0x2061, - 0x0000, 0x601b, 0x0001, 0x2091, 0x5000, 0x2091, 0x4080, 0x0005, - 0x70c3, 0x4001, 0x0c90, 0x70c3, 0x4006, 0x0c78, 0x2099, 0x0041, - 0x20a1, 0x0041, 0x20a9, 0x0005, 0x53a3, 0x0c20, 0x70c4, 0x70c3, - 0x0004, 0x0807, 0x08f8, 0x08f0, 0x08e8, 0x08e0, 0x2091, 0x8000, - 0x70c3, 0x0004, 0x70c7, 0x4953, 0x70cb, 0x5020, 0x70cf, 0x2020, - 0x70d3, 0x000a, 0x2001, 0x0004, 0x70d6, 0x2079, 0x0000, 0x781b, - 0x0001, 0x2031, 0x0030, 0x2059, 0x1000, 0x2029, 0x041a, 0x2051, - 0x0445, 0x2061, 0x0447, 0x20c1, 0x0020, 0x2091, 0x5000, 0x2091, - 0x4080, 0x0804, 0x0418, 0x75d8, 0x74dc, 0x75da, 0x74de, 0x0018, - 0x2029, 0x0000, 0x2520, 0x71d0, 0x72c8, 0x73cc, 0x70c4, 0x20a0, - 0x2099, 0x0030, 0x7003, 0x0001, 0x7007, 0x0006, 0x731a, 0x721e, - 0x7422, 0x7526, 0x2021, 0x0040, 0x81ff, 0x0904, 0x13ba, 0xa182, - 0x0040, 0x1210, 0x2120, 0xa006, 0x2008, 0x8403, 0x7012, 0x7007, - 0x0004, 0x7007, 0x0001, 0x7008, 0xd0fc, 0x0de8, 0x7007, 0x0002, - 0xa084, 0x01e0, 0x0120, 0x70c3, 0x4002, 0x0804, 0x13bd, 0x24a8, - 0x53a5, 0x0c10, 0x0804, 0x13ba, 0x2029, 0x0000, 0x2520, 0x71d0, - 0x72c8, 0x73cc, 0x70c4, 0x2098, 0x20a1, 0x0030, 0x7003, 0x0000, - 0x7007, 0x0006, 0x731a, 0x721e, 0x7422, 0x7526, 0x2021, 0x0040, - 0x7007, 0x0006, 0x81ff, 0x0904, 0x13ba, 0xa182, 0x0040, 0x1210, - 0x2120, 0xa006, 0x2008, 0x8403, 0x7012, 0x24a8, 0x53a6, 0x7007, - 0x0001, 0x7008, 0xd0fc, 0x0de8, 0xa084, 0x01e0, 0x0d48, 0x70c3, - 0x4002, 0x0804, 0x13bd, 0x75d8, 0x74dc, 0x75da, 0x74de, 0x0878, - 0x71c4, 0x70c8, 0x2114, 0xa79e, 0x0004, 0x1108, 0x200a, 0x72ca, - 0x0804, 0x13b9, 0x70c7, 0x000a, 0x70cb, 0x0004, 0x70cf, 0x0029, - 0x0804, 0x13ba, 0x75d8, 0x76dc, 0x75da, 0x76de, 0x0018, 0x2029, - 0x0000, 0x2530, 0x70c4, 0x72c8, 0x73cc, 0x74d0, 0x70c6, 0x72ca, - 0x73ce, 0x74d2, 0xa005, 0x05e8, 0xa40a, 0x0108, 0x1240, 0x8001, - 0x7872, 0xa084, 0xfc00, 0x0138, 0x78ac, 0xc085, 0x78ae, 0x2001, - 0x4005, 0x0804, 0x13bc, 0x7b7e, 0x7a7a, 0x7e86, 0x7d82, 0x7c76, - 0xa48c, 0xff00, 0x0170, 0x8407, 0x8004, 0x8004, 0x810c, 0x810c, - 0x810f, 0xa118, 0xa291, 0x0000, 0xa6b1, 0x0000, 0xa581, 0x0000, - 0x0050, 0x8407, 0x8004, 0x8004, 0xa318, 0xa291, 0x0000, 0xa6b1, - 0x0000, 0xa581, 0x0000, 0x731a, 0x721e, 0x7622, 0x7026, 0xa605, - 0x0118, 0x7a10, 0xc2c5, 0x7a12, 0x78ac, 0xa084, 0xfffc, 0x78ae, - 0x0018, 0x78ac, 0xc085, 0x78ae, 0x0804, 0x13ba, 0x75d8, 0x76dc, - 0x75da, 0x76de, 0x0018, 0x2029, 0x0000, 0x2530, 0x70c4, 0x72c8, - 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0x7026, 0x6208, 0x2400, 0xa202, 0x7012, 0x620c, 0x2300, 0xa203, - 0x7016, 0x7602, 0x7007, 0x0001, 0x2b60, 0x080c, 0x42c5, 0x0010, - 0x080c, 0x429a, 0x1de8, 0x012e, 0x2000, 0x0005, 0x0126, 0x00d6, - 0x70d0, 0xa084, 0x4c00, 0x8004, 0x2090, 0x00de, 0x7007, 0x0004, - 0x7004, 0xd094, 0x1de8, 0x7003, 0x0008, 0x012e, 0x2000, 0x0005, - 0x0126, 0x00d6, 0x70d0, 0xa084, 0x4c00, 0x8004, 0x2090, 0x00de, - 0x7e20, 0xb284, 0x0200, 0x1108, 0x7e24, 0xa6b5, 0x000c, 0x681c, - 0xd0ac, 0x1118, 0xc685, 0x7003, 0x0000, 0x6828, 0x2050, 0x2d60, - 0x6004, 0xa0bc, 0x000f, 0xa7b8, 0x401d, 0x273c, 0x87fb, 0x1138, - 0x0210, 0x080c, 0x2575, 0x689c, 0xa065, 0x0120, 0x0c88, 0x080c, - 0x429a, 0x1de8, 0x012e, 0x2000, 0x0005, 0x0126, 0x0006, 0x0016, - 0x00d6, 0x70d0, 0xa084, 0x4c00, 0x8004, 0x2090, 0x7e20, 0xb284, - 0x0200, 0x1108, 0x7e24, 0x00de, 0x003e, 0x004e, 0xa6b5, 0x000c, - 0x681c, 0xd0b4, 0x0128, 0xc685, 0x7003, 0x0000, 0x7007, 0x0004, - 0x2049, 0x4235, 0x6828, 0xa055, 0x00d6, 0x0904, 0x4296, 0x2d70, - 0x2e60, 0x7004, 0xa0bc, 0x000f, 0xa7b8, 0x401d, 0x273c, 0x87fb, - 0x1140, 0x0210, 0x080c, 0x2575, 0x709c, 0xa075, 0x2060, 0x0570, - 0x0c80, 0x2704, 0xae68, 0x6808, 0xa422, 0x680c, 0xa31b, 0x0268, - 0x8a51, 0x1110, 0x080c, 0x2575, 0x8738, 0x2704, 0xa005, 0x1d90, - 0x709c, 0xa075, 0x2060, 0x01d0, 0x08e0, 0x8422, 0x8420, 0x831a, - 0xa399, 0x0000, 0x6908, 0x2400, 0xa122, 0x690c, 0x2300, 0xa11b, - 0x1210, 0x080c, 0x2575, 0xb284, 0x0200, 0x0118, 0x2071, 0x0050, - 0x0010, 0x2071, 0x0020, 0x00de, 0x0804, 0x41c3, 0x00de, 0x012e, - 0x2000, 0x0005, 0x7008, 0x0006, 0xa084, 0x01e0, 0x000e, 0x0110, - 0xa006, 0x0005, 0xa084, 0x0003, 0xa086, 0x0003, 0x1108, 0x0005, - 0x2704, 0xac78, 0x7800, 0x2f08, 0xd094, 0x1904, 0x43a6, 0x701a, - 0x7804, 0x701e, 0x7808, 0x7012, 0x780c, 0x7016, 0x6004, 0xd09c, - 0x0120, 0x7810, 0x7022, 0x7814, 0x7026, 0x7602, 0x7004, 0xa084, - 0x0010, 0xc085, 0x7006, 0x2079, 0x4700, 0x8a51, 0x01e8, 0x8738, - 0x2704, 0xa005, 0x1168, 0x609c, 0xa005, 0x01b8, 0x2060, 0x6004, - 0xa084, 0x000f, 0xa080, 0x401d, 0x203c, 0x87fb, 0x090c, 0x2575, - 0x7008, 0x0006, 0xa084, 0x01e0, 0x000e, 0x0110, 0xa006, 0x0028, - 0xa084, 0x0003, 0xa086, 0x0003, 0x0005, 0x2051, 0x0000, 0x0005, - 0x0126, 0x0006, 0x00d6, 0x70d0, 0xa084, 0x4c00, 0x8004, 0x2090, - 0x00de, 0x008e, 0x7108, 0xa184, 0x0003, 0x1128, 0x6828, 0xa005, - 0x0178, 0x0804, 0x3f6d, 0x7108, 0xd1fc, 0x0118, 0x080c, 0x40d6, - 0x0c88, 0x7007, 0x0010, 0x7108, 0xd1fc, 0x0de8, 0x080c, 0x40d6, - 0x7008, 0xa086, 0x0008, 0x1d30, 0x7000, 0xa005, 0x1d18, 0x7003, - 0x0000, 0x2049, 0x0000, 0x0006, 0x2001, 0x4701, 0x2004, 0xd0cc, - 0x0110, 0x080c, 0x435b, 0x000e, 0x012e, 0x2000, 0x0005, 0x0126, - 0x0146, 0x0136, 0x0156, 0x00c6, 0x00d6, 0x70d0, 0xa084, 0x4c00, - 0x8004, 0x2090, 0x00de, 0x2049, 0x431f, 0xad80, 0x0011, 0x20a0, - 0xb284, 0x0200, 0x0118, 0x2099, 0x0032, 0x0010, 0x2099, 0x0031, - 0x700c, 0xa084, 0x07ff, 0x682a, 0x7007, 0x0008, 0x7007, 0x0002, - 0x7003, 0x0001, 0x0118, 0x8000, 0x80ac, 0x53a5, 0x700c, 0xa084, - 0x07ff, 0x0130, 0x7007, 0x0004, 0x7004, 0xa084, 0x0004, 0x1de0, - 0x00ce, 0x2049, 0x0000, 0x7003, 0x0000, 0x015e, 0x013e, 0x014e, - 0x012e, 0x2000, 0x0005, 0x6814, 0xd0fc, 0x0904, 0x439e, 0x7000, - 0xd084, 0x05e0, 0x7e24, 0xa6b5, 0x0004, 0x7007, 0x0004, 0x7004, - 0xa084, 0x0004, 0x1de0, 0x7118, 0x0016, 0x711c, 0x0016, 0x7120, - 0x0016, 0x7124, 0x0016, 0x701b, 0x0000, 0x701f, 0x3fff, 0x7023, - 0x0000, 0x7027, 0x0000, 0x7013, 0x0004, 0x7017, 0x0000, 0x7602, - 0x7007, 0x0001, 0x2001, 0xffff, 0x2009, 0x0031, 0x200a, 0x200a, - 0x7108, 0x7008, 0xa106, 0x1de0, 0xd1fc, 0x0dd0, 0x002e, 0x7226, - 0x002e, 0x7222, 0x002e, 0x721e, 0x002e, 0x721a, 0x7007, 0x0002, - 0x7008, 0xa086, 0x0008, 0x0110, 0x0804, 0x410e, 0x7007, 0x0004, - 0x7003, 0x0000, 0x0005, 0x2049, 0x41c3, 0x0068, 0x7008, 0xa084, - 0x0003, 0x0110, 0xa006, 0x0005, 0xa006, 0x2020, 0x2018, 0x2c58, - 0x2160, 0x2049, 0x0000, 0x8b58, 0x6100, 0x2100, 0xa408, 0x711a, - 0x6004, 0xa301, 0x701e, 0x0006, 0x2b04, 0xa084, 0x0008, 0x0150, - 0x6010, 0xa081, 0x0000, 0x7022, 0x0006, 0x6014, 0xa081, 0x0000, - 0x7026, 0x0006, 0xa184, 0x0007, 0x2011, 0x0008, 0xa22a, 0x6208, - 0x2400, 0xa212, 0x0026, 0x620c, 0x2240, 0x2300, 0xa843, 0x002e, - 0x88ff, 0x1170, 0x2500, 0xa202, 0x0108, 0x1250, 0x2220, 0x2041, - 0x0000, 0x2b04, 0xd09c, 0x0110, 0x000e, 0x000e, 0x000e, 0x0450, - 0x7512, 0x7017, 0x0000, 0x7602, 0xa986, 0x41c3, 0x1118, 0x7007, - 0x0001, 0x0028, 0x7004, 0xa084, 0x0010, 0xc085, 0x7006, 0x2500, - 0xa100, 0x701a, 0x2b04, 0xa084, 0x0008, 0x0110, 0x000e, 0x004e, - 0x001e, 0xa189, 0x0000, 0x711e, 0x2b0c, 0xa18c, 0x0008, 0x0130, - 0xa4a1, 0x0000, 0x7422, 0xa081, 0x0000, 0x7026, 0x2500, 0xa222, - 0xa8c3, 0x0000, 0x7412, 0x2820, 0x7416, 0x7602, 0xa986, 0x41c3, - 0x1118, 0x7007, 0x0001, 0x0028, 0x7004, 0xa084, 0x0010, 0xc085, - 0x7006, 0x8b59, 0x2b60, 0x2079, 0x4700, 0x080c, 0x42c5, 0xa006, - 0x0005, 0x2091, 0x8000, 0x2091, 0x6000, 0x78ac, 0xa005, 0x1168, - 0x7974, 0x70d0, 0xa106, 0x1148, 0x781c, 0xa005, 0x0130, 0x781f, - 0x0000, 0x0e04, 0x443d, 0x2091, 0x4080, 0x2069, 0x4780, 0xc7fd, - 0x6800, 0xa084, 0x000f, 0x1198, 0x68d0, 0xd0b4, 0x0180, 0xd0bc, - 0x1170, 0x00f6, 0x2079, 0x0100, 0xd7fc, 0x1110, 0x2079, 0x0200, - 0x7830, 0xa084, 0x00c0, 0x1110, 0x080c, 0x22d5, 0x00fe, 0xd7fc, - 0x0120, 0x2069, 0x4740, 0xc7fc, 0x0c18, 0x7830, 0x8001, 0x7832, - 0x1904, 0x44c7, 0x7834, 0x7832, 0x2061, 0x6cc0, 0x2069, 0x4780, - 0xc7fd, 0x68cc, 0xa005, 0x0128, 0x8001, 0x68ce, 0x1110, 0x080c, - 0x4639, 0x6800, 0xa084, 0x000f, 0x0168, 0xa086, 0x0001, 0x0150, - 0x6840, 0xa00d, 0x0138, 0x2104, 0xa005, 0x0120, 0x8001, 0x200a, - 0x0904, 0x45d6, 0x6814, 0xa005, 0x01a8, 0x8001, 0x6816, 0x1190, - 0x68a3, 0x0001, 0x00f6, 0xd7fc, 0x1118, 0x2079, 0x0200, 0x0010, - 0x2079, 0x0100, 0x080c, 0x3c6e, 0x00fe, 0x6860, 0xa005, 0x0110, - 0x080c, 0x22d5, 0x687c, 0xa005, 0x0140, 0x8001, 0x687e, 0x1128, - 0x6863, 0x0000, 0x68d0, 0xc0c5, 0x68d2, 0x68d0, 0xd0fc, 0x01b0, - 0xc0fc, 0x68d2, 0x20a9, 0x0200, 0x6034, 0xa005, 0x0158, 0x8001, - 0x6036, 0x68d0, 0xc0fd, 0x68d2, 0x1128, 0x6010, 0xa005, 0x0110, - 0x080c, 0x22d5, 0xace0, 0x0010, 0x1f04, 0x44ac, 0xd7fc, 0x0138, - 0x2061, 0x4cc0, 0x2069, 0x4740, 0xc7fc, 0x0804, 0x4469, 0x0459, - 0x7838, 0x8001, 0x783a, 0x11a0, 0x783c, 0x783a, 0x2061, 0x4cc0, - 0x2069, 0x4740, 0xc7fc, 0x680c, 0xa005, 0x0110, 0x080c, 0x4543, - 0xd7fc, 0x1130, 0x2061, 0x6cc0, 0x2069, 0x4780, 0xc7fd, 0x0c98, - 0x7810, 0xd0cc, 0x0168, 0xd0ac, 0x1120, 0xd0a4, 0x0148, 0xc0ad, - 0x7812, 0x2091, 0x8001, 0x0e04, 0x44ef, 0x080c, 0x20a1, 0x0005, - 0x2091, 0x8001, 0x0005, 0x7840, 0x8001, 0x7842, 0x1904, 0x4542, - 0x7844, 0x7842, 0x2069, 0x4740, 0xc7fc, 0x2079, 0x0200, 0x68d4, - 0xa005, 0x0138, 0x7de0, 0xa504, 0x1120, 0x68d6, 0x68d0, 0xc0bc, - 0x68d2, 0x2079, 0x4700, 0x6810, 0xa005, 0x1110, 0x2001, 0x0101, - 0x8001, 0x6812, 0xd7fc, 0x0118, 0xa080, 0x8dd0, 0x0010, 0xa080, - 0x8cc0, 0x2040, 0x2004, 0xa065, 0x01e0, 0x6024, 0xa005, 0x01b0, - 0x8001, 0x6026, 0x1198, 0x6800, 0xa005, 0x0130, 0x6848, 0xac06, - 0x1118, 0x080c, 0x45d6, 0x0068, 0x6860, 0xa005, 0x0118, 0x6027, - 0x0001, 0x0020, 0x080c, 0x4584, 0x2804, 0x0c28, 0x6000, 0x2c40, - 0x0c10, 0xd7fc, 0x1138, 0x2069, 0x4780, 0xc7fd, 0x2079, 0x0100, - 0x0804, 0x44ff, 0x0005, 0x2009, 0x0000, 0x20a9, 0x0200, 0x6008, - 0xd09c, 0x0558, 0x6024, 0xa005, 0x0118, 0x8001, 0x6026, 0x0418, - 0x6008, 0xc09c, 0xd084, 0x1110, 0xd0ac, 0x01c0, 0x600a, 0x6004, - 0xa005, 0x01d8, 0x00d6, 0x00c6, 0x0016, 0x2068, 0x6010, 0x8001, - 0x6012, 0x080c, 0x37c7, 0x2d00, 0x2c68, 0x2060, 0x080c, 0x1c02, - 0x080c, 0x1db2, 0x001e, 0x00ce, 0x00de, 0x0038, 0xc0bd, 0x600a, - 0xa18d, 0x0001, 0x0010, 0xa18d, 0x0100, 0xace0, 0x0010, 0x1f04, - 0x4547, 0xa184, 0x0001, 0x0130, 0xa18c, 0xfffe, 0x690e, 0x080c, - 0x22d5, 0x0008, 0x690e, 0x0005, 0x2c00, 0x687a, 0x6714, 0x6f72, - 0x6017, 0x0000, 0x602b, 0x0000, 0x601b, 0x0006, 0x60b4, 0xa084, - 0x5f00, 0x601e, 0x6020, 0xa084, 0x00ff, 0xa085, 0x0060, 0x6022, - 0x6000, 0x2042, 0x2069, 0x4780, 0xd7fc, 0x1110, 0x2069, 0x4740, - 0x6858, 0xac06, 0x1110, 0x2800, 0x685a, 0x080c, 0x1b9a, 0x6818, - 0xa005, 0x0110, 0x8001, 0x681a, 0x6808, 0xc0a4, 0x680a, 0x6810, - 0x7908, 0x8109, 0x790a, 0x8001, 0x1310, 0x080c, 0x2575, 0x6812, - 0x1118, 0x7910, 0xc1a5, 0x7912, 0x602f, 0x0000, 0x6033, 0x0000, - 0x2c68, 0x080c, 0x1dbf, 0xd7fc, 0x1118, 0x2069, 0x4740, 0x0010, - 0x2069, 0x4780, 0x6910, 0xa184, 0x0100, 0x2001, 0x0006, 0x1118, - 0x6976, 0x2001, 0x0004, 0x080c, 0x22cb, 0x0005, 0x00d6, 0x6948, - 0x2160, 0xd7fc, 0x1118, 0x2069, 0x0200, 0x0010, 0x2069, 0x0100, - 0x080c, 0x2490, 0x601b, 0x0006, 0x6858, 0xa084, 0x5f00, 0x601e, - 0x6020, 0xa084, 0x00ff, 0xa085, 0x0048, 0x6022, 0x602f, 0x0000, - 0x6033, 0x0000, 0x6808, 0xa084, 0xfffd, 0x680a, 0x6830, 0xd0b4, - 0x01b0, 0x684b, 0x0004, 0x20a9, 0x0014, 0x6848, 0xd094, 0x0110, - 0x1f04, 0x45fd, 0x684b, 0x0009, 0x20a9, 0x0014, 0x6848, 0xd084, - 0x0110, 0x1f04, 0x4606, 0x20a9, 0x00fa, 0x1f04, 0x460d, 0x681b, - 0x0054, 0x00de, 0x6863, 0x0007, 0x0005, 0x2079, 0x4700, 0x00e1, - 0x0089, 0x00a9, 0x2009, 0x0002, 0x2069, 0x4780, 0x680f, 0x0000, - 0x6813, 0x0000, 0x6817, 0x0000, 0x8109, 0x0118, 0x2069, 0x4740, - 0x0ca8, 0x0005, 0x2019, 0x00a3, 0x7b3a, 0x7b3e, 0x0005, 0x2019, - 0x0033, 0x7b42, 0x7b46, 0x0005, 0x2019, 0x32dd, 0x7b32, 0x7b36, - 0x0005, 0x6a4c, 0xa285, 0x0000, 0x01f0, 0x6950, 0x6bbc, 0xa300, - 0x00c6, 0x2164, 0x6304, 0x83ff, 0x1138, 0x8211, 0x0148, 0x8108, - 0xa11a, 0x0eb8, 0x69bc, 0x0ca8, 0x68cf, 0x000a, 0x00ce, 0x0005, - 0x694c, 0x6abc, 0x2264, 0x6008, 0xc0b5, 0x600a, 0x8210, 0x8109, - 0x1dc8, 0x694e, 0x00ce, 0x0005, 0x0016, 0x1d04, 0x465d, 0x2091, - 0x6000, 0x1d04, 0x4661, 0x2091, 0x6000, 0x70ec, 0xd0dc, 0x1118, - 0xd0d4, 0x0190, 0x00a0, 0xae8e, 0x0100, 0x0138, 0x7814, 0xc0f5, - 0xc0c5, 0x7816, 0xd0d4, 0x1580, 0x0460, 0x7814, 0xc0fd, 0xc0c5, - 0x7816, 0xd0d4, 0x1548, 0x0428, 0xd0e4, 0x0904, 0x46c4, 0x1d04, - 0x467f, 0x2091, 0x6000, 0x2009, 0x000c, 0x1d04, 0x4685, 0x2091, - 0x6000, 0x8109, 0x1dd0, 0x70e4, 0xa084, 0x01ff, 0xa086, 0x01ff, - 0x1110, 0x70ec, 0x08c0, 0xae8e, 0x0100, 0x0128, 0x7814, 0xc0f4, - 0xd0fc, 0x1130, 0x0020, 0x7814, 0xc0fc, 0xd0f4, 0x1108, 0xc0c4, - 0x7816, 0x7804, 0xd08c, 0x0500, 0x00c6, 0x2061, 0x0000, 0x6018, - 0xd084, 0x11b8, 0xae86, 0x0200, 0x00e6, 0x2071, 0x0010, 0x0120, - 0x70db, 0x0001, 0x78e4, 0x0018, 0x70db, 0x0000, 0x78e0, 0x70c6, - 0x70c3, 0x800e, 0x601b, 0x0001, 0x2091, 0x4080, 0x00ee, 0x00ce, - 0x0018, 0x00ce, 0x681f, 0x000c, 0x001e, 0x70a0, 0x70a2, 0x0005, - 0x0c28 -}; -#endif diff --git a/sys/dev/ispfw/asm_2100.h b/sys/dev/ispfw/asm_2100.h deleted file mode 100644 index 94c0f695860..00000000000 --- a/sys/dev/ispfw/asm_2100.h +++ /dev/null @@ -1,8148 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-3-Clause - * - * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2000 Qlogic, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms are permitted provided - * that the following conditions are met: - * 1. Redistribution of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistribution in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/* - * Some very early boards have problems loading firmware that is larger than - * 0x8000 words. In order to be able to provide at least *some* support - * for such ancient cards, an alternate firmware set is provided. This firmware - * isn't all that great, but, hey, it's better than nothing. - * - * Define USE_SMALLER_2100_FIRMWARE to select this. - */ -#ifndef USE_SMALLER_2100_FIRMWARE -/************************************************************************ - * * - * --- ISP2100 Fabric Initiator/Target Firmware --- * - * with expanded LUN addressing * - * and FcTape (FCP-2) support * - * * - ************************************************************************/ -/* - * Firmware Version 1.19.24 (14:02 Jul 16, 2002) - */ -static const u_int16_t isp_2100_risc_code[] = { - 0x0078, 0x102d, 0x0000, 0x95f1, 0x0000, 0x0001, 0x0013, 0x0018, - 0x0017, 0x2043, 0x4f50, 0x5952, 0x4947, 0x4854, 0x2032, 0x3030, - 0x3120, 0x514c, 0x4f47, 0x4943, 0x2043, 0x4f52, 0x504f, 0x5241, - 0x5449, 0x4f4e, 0x2049, 0x5350, 0x3231, 0x3030, 0x2046, 0x6972, - 0x6d77, 0x6172, 0x6520, 0x2056, 0x6572, 0x7369, 0x6f6e, 0x2030, - 0x312e, 0x3139, 0x2020, 0x2020, 0x2400, 0x2091, 0x2000, 0x20c1, - 0x0021, 0x2039, 0xffff, 0x2019, 0xaaaa, 0x2760, 0x2069, 0x7fff, - 0x20c1, 0x0020, 0x2c2c, 0x2d34, 0x2762, 0x236a, 0x2c24, 0x2d04, - 0x266a, 0x2562, 0xa406, 0x00c0, 0x1052, 0x20c1, 0x0021, 0x2c2c, - 0x2362, 0x2c04, 0x2562, 0xa306, 0x0040, 0x1052, 0x20c1, 0x0020, - 0x2039, 0x8fff, 0x20a1, 0xad00, 0x2708, 0x810d, 0x810d, 0x810d, - 0x810d, 0xa18c, 0x000f, 0x2001, 0x000a, 0xa112, 0xa00e, 0x21a8, - 0x41a4, 0x3400, 0x8211, 0x00c0, 0x105f, 0x2708, 0x3400, 0xa102, - 0x0040, 0x106f, 0x0048, 0x106f, 0x20a8, 0xa00e, 0x41a4, 0x20a1, - 0xa5f1, 0x2009, 0x0000, 0x20a9, 0x070f, 0x41a4, 0x3400, 0x20c9, - 0xaaff, 0x2059, 0x0000, 0x2b78, 0x7823, 0x0004, 0x2089, 0x25c7, - 0x2051, 0xa600, 0x2a70, 0x7762, 0xa786, 0x8fff, 0x0040, 0x1092, - 0x705f, 0xcd00, 0x705b, 0xccf1, 0x7067, 0x0200, 0x706b, 0x0200, - 0x0078, 0x109a, 0x705b, 0xbd01, 0x7067, 0x0100, 0x706b, 0x0100, - 0x705f, 0xbd00, 0x1078, 0x12df, 0x1078, 0x13ca, 0x1078, 0x1577, - 0x1078, 0x1ce9, 0x1078, 0x42ec, 0x1078, 0x76bf, 0x1078, 0x1355, - 0x1078, 0x2ac0, 0x1078, 0x4e93, 0x1078, 0x49a3, 0x1078, 0x594a, - 0x1078, 0x2263, 0x1078, 0x5c43, 0x1078, 0x5485, 0x1078, 0x2162, - 0x1078, 0x2240, 0x2091, 0x3009, 0x7823, 0x0000, 0x0090, 0x10cf, - 0x7820, 0xa086, 0x0002, 0x00c0, 0x10cf, 0x7823, 0x4000, 0x0068, - 0x10c7, 0x781b, 0x0001, 0x2091, 0x5000, 0x2091, 0x4080, 0x2a70, - 0x7003, 0x0000, 0x2001, 0x017f, 0x2003, 0x0000, 0x2a70, 0x7000, - 0xa08e, 0x0003, 0x00c0, 0x10ef, 0x1078, 0x365e, 0x1078, 0x2ae8, - 0x1078, 0x4ee3, 0x1078, 0x4b66, 0x2009, 0x0100, 0x2104, 0xa082, - 0x0002, 0x0048, 0x10f3, 0x1078, 0x5966, 0x0078, 0x10d6, 0x1079, - 0x10f7, 0x0078, 0x10dc, 0x1078, 0x7197, 0x0078, 0x10eb, 0x1101, - 0x1102, 0x11be, 0x10ff, 0x1246, 0x12dc, 0x12dd, 0x12de, 0x1078, - 0x1332, 0x007c, 0x127e, 0x0f7e, 0x2091, 0x8000, 0x7000, 0xa086, - 0x0001, 0x00c0, 0x1198, 0x1078, 0x3aec, 0x2079, 0x0100, 0x7844, - 0xa005, 0x00c0, 0x1198, 0x2011, 0x41dc, 0x1078, 0x5a45, 0x1078, - 0x1adf, 0x780f, 0x00ff, 0x7840, 0xa084, 0xfffb, 0x7842, 0x2011, - 0x8010, 0x73c4, 0x1078, 0x361b, 0x2001, 0xffff, 0x1078, 0x5ae6, - 0x723c, 0xc284, 0x723e, 0x2001, 0xa60c, 0x2014, 0xc2ac, 0x2202, - 0x1078, 0x6f9f, 0x2011, 0x0004, 0x1078, 0x8d1b, 0x1078, 0x489e, - 0x1078, 0x42d4, 0x0040, 0x1144, 0x7087, 0x0001, 0x70bf, 0x0000, - 0x1078, 0x3c9e, 0x0078, 0x1198, 0x1078, 0x4967, 0x0040, 0x114d, - 0x7a0c, 0xc2b4, 0x7a0e, 0x0078, 0x1159, 0x1078, 0x90a6, 0x70cc, - 0xd09c, 0x00c0, 0x1159, 0x7098, 0xa005, 0x0040, 0x1159, 0x1078, - 0x42b8, 0x70d7, 0x0000, 0x70d3, 0x0000, 0x72cc, 0x2079, 0xa652, - 0x7804, 0xd0ac, 0x0040, 0x1165, 0xc295, 0x72ce, 0xa296, 0x0004, - 0x0040, 0x1186, 0x2011, 0x0001, 0x1078, 0x8d1b, 0x7093, 0x0000, - 0x7097, 0xffff, 0x7003, 0x0002, 0x0f7f, 0x1078, 0x2677, 0x2011, - 0x0005, 0x1078, 0x70e0, 0x1078, 0x62d1, 0x0c7e, 0x2061, 0x0100, - 0x60e3, 0x0008, 0x0c7f, 0x127f, 0x0078, 0x119a, 0x7093, 0x0000, - 0x7097, 0xffff, 0x7003, 0x0002, 0x2011, 0x0005, 0x1078, 0x70e0, - 0x1078, 0x62d1, 0x0c7e, 0x2061, 0x0100, 0x60e3, 0x0008, 0x0c7f, - 0x0f7f, 0x127f, 0x007c, 0x0c7e, 0x20a9, 0x0082, 0x2009, 0x007e, - 0x017e, 0x027e, 0x037e, 0x2110, 0x027e, 0x2019, 0x0029, 0x1078, - 0x73d0, 0x027f, 0x1078, 0xa4f1, 0x037f, 0x027f, 0x017f, 0x1078, - 0x298e, 0x8108, 0x00f0, 0x11a0, 0x0c7f, 0x706f, 0x0000, 0x7070, - 0xa084, 0x00ff, 0x7072, 0x709b, 0x0000, 0x007c, 0x127e, 0x2091, - 0x8000, 0x7000, 0xa086, 0x0002, 0x00c0, 0x1244, 0x7094, 0xa086, - 0xffff, 0x0040, 0x11d1, 0x1078, 0x2677, 0x1078, 0x62d1, 0x0078, - 0x1244, 0x70cc, 0xd09c, 0x0040, 0x11fd, 0xd084, 0x0040, 0x11fd, - 0x0f7e, 0x2079, 0x0100, 0x790c, 0xc1b5, 0x790e, 0x0f7f, 0xd08c, - 0x0040, 0x11fd, 0x70d0, 0xa086, 0xffff, 0x0040, 0x11f9, 0x1078, - 0x27f7, 0x1078, 0x62d1, 0x70cc, 0xd094, 0x00c0, 0x1244, 0x2011, - 0x0001, 0x2019, 0x0000, 0x1078, 0x282f, 0x1078, 0x62d1, 0x0078, - 0x1244, 0x70d4, 0xa005, 0x00c0, 0x1244, 0x7090, 0xa005, 0x00c0, - 0x1244, 0x1078, 0x4967, 0x00c0, 0x1244, 0x2001, 0xa653, 0x2004, - 0xd0ac, 0x0040, 0x1227, 0x157e, 0x0c7e, 0x20a9, 0x007f, 0x2009, - 0x0000, 0x017e, 0x1078, 0x45c4, 0x00c0, 0x121a, 0x6000, 0xd0ec, - 0x00c0, 0x1222, 0x017f, 0x8108, 0x00f0, 0x1211, 0x0c7f, 0x157f, - 0x0078, 0x1227, 0x017f, 0x0c7f, 0x157f, 0x0078, 0x1244, 0x7003, - 0x0003, 0x7097, 0xffff, 0x2001, 0x0000, 0x1078, 0x24e8, 0x1078, - 0x3699, 0x2001, 0xa8b2, 0x2004, 0xa086, 0x0005, 0x00c0, 0x123c, - 0x2011, 0x0000, 0x1078, 0x70e0, 0x2011, 0x0000, 0x1078, 0x70ea, - 0x1078, 0x62d1, 0x1078, 0x639b, 0x127f, 0x007c, 0x017e, 0x0f7e, - 0x127e, 0x2091, 0x8000, 0x2079, 0x0100, 0x2009, 0x00f7, 0x1078, - 0x42a1, 0x7940, 0xa18c, 0x0010, 0x7942, 0x7924, 0xd1b4, 0x0040, - 0x125b, 0x7827, 0x0040, 0xd19c, 0x0040, 0x1260, 0x7827, 0x0008, - 0x007e, 0x037e, 0x157e, 0xa006, 0x1078, 0x5ae6, 0x7900, 0xa18a, - 0x0003, 0x0050, 0x1289, 0x7954, 0xd1ac, 0x00c0, 0x1289, 0x2009, - 0x00f8, 0x1078, 0x42a1, 0x7843, 0x0090, 0x7843, 0x0010, 0x20a9, - 0x09c4, 0x7820, 0xd09c, 0x00c0, 0x1281, 0x7824, 0xd0ac, 0x00c0, - 0x12ca, 0x00f0, 0x1279, 0x2001, 0x0001, 0x1078, 0x24e8, 0x0078, - 0x12d5, 0x7853, 0x0000, 0x782f, 0x0020, 0x20a9, 0x0050, 0x00e0, - 0x128f, 0x2091, 0x6000, 0x00f0, 0x128f, 0x7853, 0x0400, 0x782f, - 0x0000, 0x2009, 0x00f8, 0x1078, 0x42a1, 0x20a9, 0x000e, 0x0005, - 0x00f0, 0x129f, 0x7853, 0x1400, 0x7843, 0x0090, 0x7843, 0x0010, - 0x2019, 0x61a8, 0x7854, 0x0005, 0x0005, 0xd08c, 0x0040, 0x12b4, - 0x7824, 0xd0ac, 0x00c0, 0x12ca, 0x8319, 0x00c0, 0x12aa, 0x2009, - 0xa632, 0x2104, 0x8000, 0x200a, 0xa084, 0xfff0, 0x0040, 0x12c4, - 0x200b, 0x0000, 0x1078, 0x2588, 0x2001, 0x0001, 0x1078, 0x24e8, - 0x0078, 0x12d3, 0x2001, 0xa632, 0x2003, 0x0000, 0x7828, 0xc09d, - 0x782a, 0x7827, 0x0048, 0x7853, 0x0400, 0x157f, 0x037f, 0x007f, - 0x127f, 0x0f7f, 0x017f, 0x007c, 0x007c, 0x007c, 0x007c, 0x2a70, - 0x2061, 0xa8ad, 0x2063, 0x0001, 0x6007, 0x0013, 0x600b, 0x0018, - 0x600f, 0x0017, 0x2009, 0x0100, 0x2104, 0xa082, 0x0002, 0x0048, - 0x12f5, 0x7053, 0xffff, 0x0078, 0x12f7, 0x7053, 0x0000, 0x7057, - 0xffff, 0x706f, 0x0000, 0x7073, 0x0000, 0x1078, 0x90a6, 0x2061, - 0xa88d, 0x6003, 0x0909, 0x6007, 0x0000, 0x600b, 0x8800, 0x600f, - 0x0200, 0x6013, 0x00ff, 0x6017, 0x0003, 0x601b, 0x0000, 0x601f, - 0x07d0, 0x2061, 0xa895, 0x6003, 0x8000, 0x6007, 0x0000, 0x600b, - 0x0000, 0x600f, 0x0200, 0x6013, 0x00ff, 0x6017, 0x0000, 0x601b, - 0x0001, 0x601f, 0x0000, 0x2061, 0xa8a5, 0x6003, 0x514c, 0x6007, - 0x4f47, 0x600b, 0x4943, 0x600f, 0x2020, 0x2001, 0xa626, 0x2003, - 0x0000, 0x007c, 0x2091, 0x8000, 0x0068, 0x1334, 0x007e, 0x017e, - 0x2079, 0x0000, 0x7818, 0xd084, 0x00c0, 0x133a, 0x017f, 0x792e, - 0x007f, 0x782a, 0x007f, 0x7826, 0x3900, 0x783a, 0x7823, 0x8002, - 0x781b, 0x0001, 0x2091, 0x5000, 0x2091, 0x4080, 0x2079, 0xa600, - 0x7803, 0x0005, 0x0078, 0x1352, 0x007c, 0x2071, 0xa600, 0x715c, - 0x712e, 0x2021, 0x0001, 0xa190, 0x002d, 0xa298, 0x002d, 0x0048, - 0x136b, 0x7060, 0xa302, 0x00c8, 0x136b, 0x220a, 0x2208, 0x2310, - 0x8420, 0x0078, 0x135d, 0x200b, 0x0000, 0x74aa, 0x74ae, 0x007c, - 0x0e7e, 0x127e, 0x2091, 0x8000, 0x2071, 0xa600, 0x70ac, 0xa0ea, - 0x0010, 0x00c8, 0x137e, 0xa06e, 0x0078, 0x1388, 0x8001, 0x70ae, - 0x702c, 0x2068, 0x2d04, 0x702e, 0x206b, 0x0000, 0x6807, 0x0000, - 0x127f, 0x0e7f, 0x007c, 0x0e7e, 0x2071, 0xa600, 0x127e, 0x2091, - 0x8000, 0x70ac, 0x8001, 0x00c8, 0x1398, 0xa06e, 0x0078, 0x13a1, - 0x70ae, 0x702c, 0x2068, 0x2d04, 0x702e, 0x206b, 0x0000, 0x6807, - 0x0000, 0x127f, 0x0e7f, 0x007c, 0x0e7e, 0x127e, 0x2091, 0x8000, - 0x2071, 0xa600, 0x702c, 0x206a, 0x2d00, 0x702e, 0x70ac, 0x8000, - 0x70ae, 0x127f, 0x0e7f, 0x007c, 0x8dff, 0x0040, 0x13c0, 0x6804, - 0x6807, 0x0000, 0x007e, 0x1078, 0x13a4, 0x0d7f, 0x0078, 0x13b4, - 0x007c, 0x0e7e, 0x2071, 0xa600, 0x70ac, 0xa08a, 0x0010, 0xa00d, - 0x0e7f, 0x007c, 0x0e7e, 0x2071, 0xa8d6, 0x7007, 0x0000, 0x701b, - 0x0000, 0x701f, 0x0000, 0x2071, 0x0000, 0x7010, 0xa085, 0x8004, - 0x7012, 0x0e7f, 0x007c, 0x127e, 0x2091, 0x8000, 0x0e7e, 0x2270, - 0x700b, 0x0000, 0x2071, 0xa8d6, 0x7018, 0xa088, 0xa8df, 0x220a, - 0x8000, 0xa084, 0x0007, 0x701a, 0x7004, 0xa005, 0x00c0, 0x13f6, - 0x0f7e, 0x2079, 0x0010, 0x1078, 0x1408, 0x0f7f, 0x0e7f, 0x127f, - 0x007c, 0x0e7e, 0x2071, 0xa8d6, 0x7004, 0xa005, 0x00c0, 0x1406, - 0x0f7e, 0x2079, 0x0010, 0x1078, 0x1408, 0x0f7f, 0x0e7f, 0x007c, - 0x7000, 0x0079, 0x140b, 0x140f, 0x1479, 0x1496, 0x1496, 0x7018, - 0x711c, 0xa106, 0x00c0, 0x1417, 0x7007, 0x0000, 0x007c, 0x0d7e, - 0xa180, 0xa8df, 0x2004, 0x700a, 0x2068, 0x8108, 0xa18c, 0x0007, - 0x711e, 0x7803, 0x0026, 0x6824, 0x7832, 0x6828, 0x7836, 0x682c, - 0x783a, 0x6830, 0x783e, 0x6810, 0x700e, 0x680c, 0x7016, 0x6804, - 0x0d7f, 0xd084, 0x0040, 0x1439, 0x7007, 0x0001, 0x1078, 0x143e, - 0x007c, 0x7007, 0x0002, 0x1078, 0x1454, 0x007c, 0x017e, 0x027e, - 0x710c, 0x2011, 0x0040, 0xa182, 0x0040, 0x00c8, 0x1449, 0x2110, - 0xa006, 0x700e, 0x7212, 0x8203, 0x7822, 0x7803, 0x0020, 0x7803, - 0x0041, 0x027f, 0x017f, 0x007c, 0x017e, 0x027e, 0x137e, 0x147e, - 0x157e, 0x7014, 0x2098, 0x20a1, 0x0014, 0x7803, 0x0026, 0x710c, - 0x2011, 0x0040, 0xa182, 0x0040, 0x00c8, 0x1468, 0x2110, 0xa006, - 0x700e, 0x22a8, 0x53a6, 0x8203, 0x7822, 0x7803, 0x0020, 0x3300, - 0x7016, 0x7803, 0x0001, 0x157f, 0x147f, 0x137f, 0x027f, 0x017f, - 0x007c, 0x137e, 0x147e, 0x157e, 0x2099, 0xa6fa, 0x20a1, 0x0018, - 0x20a9, 0x0008, 0x53a3, 0x7803, 0x0020, 0x127e, 0x2091, 0x8000, - 0x7803, 0x0041, 0x7007, 0x0003, 0x7000, 0xc084, 0x7002, 0x700b, - 0xa6f5, 0x127f, 0x157f, 0x147f, 0x137f, 0x007c, 0x137e, 0x147e, - 0x157e, 0x2001, 0xa729, 0x209c, 0x20a1, 0x0014, 0x7803, 0x0026, - 0x2001, 0xa72a, 0x20ac, 0x53a6, 0x2099, 0xa72b, 0x20a1, 0x0018, - 0x20a9, 0x0008, 0x53a3, 0x7803, 0x0020, 0x127e, 0x2091, 0x8000, - 0x7803, 0x0001, 0x7007, 0x0004, 0x7000, 0xc08c, 0x7002, 0x700b, - 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0x7c83, 0x1078, 0x8ec6, 0xace0, 0x0010, 0x2001, 0xa616, 0x2004, - 0xac02, 0x00c8, 0xa545, 0x0078, 0xa504, 0x127f, 0x017f, 0x027f, - 0x047f, 0x057f, 0x067f, 0x077f, 0x0c7f, 0x0e7f, 0x007c, 0x127e, - 0x007e, 0x0e7e, 0x017e, 0x2091, 0x8000, 0x2071, 0xa640, 0xd5a4, - 0x0040, 0xa55d, 0x7034, 0x8000, 0x7036, 0xd5b4, 0x0040, 0xa563, - 0x7030, 0x8000, 0x7032, 0xd5ac, 0x0040, 0xa579, 0x2500, 0xa084, - 0x0007, 0xa08e, 0x0003, 0x0040, 0xa579, 0xa08e, 0x0004, 0x0040, - 0xa579, 0xa08e, 0x0005, 0x0040, 0xa579, 0x2071, 0xa64a, 0x1078, - 0xa5ba, 0x017f, 0x0e7f, 0x007f, 0x127f, 0x007c, 0x127e, 0x007e, - 0x0e7e, 0x017e, 0x2091, 0x8000, 0x2071, 0xa640, 0xd5a4, 0x0040, - 0xa58c, 0x7034, 0x8000, 0x7036, 0xd5b4, 0x0040, 0xa592, 0x7030, - 0x8000, 0x7032, 0xd5ac, 0x0040, 0xa5a8, 0x2500, 0xa084, 0x0007, - 0xa08e, 0x0003, 0x0040, 0xa5a8, 0xa08e, 0x0004, 0x0040, 0xa5a8, - 0xa08e, 0x0005, 0x0040, 0xa5a8, 0x2071, 0xa64a, 0x1078, 0xa5ba, - 0x017f, 0x0e7f, 0x007f, 0x127f, 0x007c, 0x127e, 0x007e, 0x0e7e, - 0x2091, 0x8000, 0x2071, 0xa642, 0x1078, 0xa5ba, 0x0e7f, 0x007f, - 0x127f, 0x007c, 0x2e04, 0x8000, 0x2072, 0x00c8, 0xa5c3, 0x8e70, - 0x2e04, 0x8000, 0x2072, 0x007c, 0x0e7e, 0x2071, 0xa640, 0x1078, - 0xa5ba, 0x0e7f, 0x007c, 0x0e7e, 0x2071, 0xa644, 0x1078, 0xa5ba, - 0x0e7f, 0x007c, 0x127e, 0x007e, 0x0e7e, 0x2091, 0x8000, 0x2071, - 0xa640, 0x7044, 0x8000, 0x7046, 0x0e7f, 0x007f, 0x127f, 0x007c, - 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080, - 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000, - 0xa50c -}; -#else -/* - * Firmware Version 1.15.37 (15:36 May 03, 1999) - */ -static const u_int16_t isp_2100_risc_code[] = { - 0x0078, 0x1029, 0x0000, 0x66e6, 0x0000, 0x2043, 0x4f50, 0x5952, - 0x4947, 0x4854, 0x2031, 0x3939, 0x3620, 0x514c, 0x4f47, 0x4943, - 0x2043, 0x4f52, 0x504f, 0x5241, 0x5449, 0x4f4e, 0x2049, 0x5350, - 0x3231, 0x3030, 0x2046, 0x6972, 0x6d77, 0x6172, 0x6520, 0x2056, - 0x6572, 0x7369, 0x6f6e, 0x2030, 0x312e, 0x3135, 0x2020, 0x2020, - 0x2400, 0x20c1, 0x0021, 0x20a1, 0x76e6, 0x2009, 0x0000, 0x20a9, - 0x071a, 0x41a4, 0x3400, 0x20c9, 0x7bff, 0x2091, 0x2000, 0x2059, - 0x0000, 0x2b78, 0x7823, 0x0004, 0x2089, 0x209a, 0x2051, 0x7700, - 0x2a70, 0x705b, 0x9600, 0x705f, 0xffff, 0x7057, 0x95f9, 0x7063, - 0x0300, 0x1078, 0x127a, 0x20a1, 0x7e00, 0x715c, 0x810d, 0x810d, - 0x810d, 0x810d, 0xa18c, 0x000f, 0x2001, 0x0007, 0xa112, 0xa00e, - 0x21a8, 0x41a4, 0x3400, 0x8211, 0x00c0, 0x1058, 0x715c, 0x3400, - 0xa102, 0x0040, 0x1068, 0x0048, 0x1068, 0x20a8, 0xa00e, 0x41a4, - 0x1078, 0x1241, 0x1078, 0x1366, 0x1078, 0x14eb, 0x1078, 0x19c0, - 0x1078, 0x362b, 0x1078, 0x5cac, 0x1078, 0x12f1, 0x1078, 0x2429, - 0x1078, 0x3d6e, 0x1078, 0x3b46, 0x1078, 0x45af, 0x1078, 0x1e55, - 0x1078, 0x47ef, 0x1078, 0x428f, 0x1078, 0x1d74, 0x1078, 0x1e34, - 0x2091, 0x3009, 0x7823, 0x0000, 0x0090, 0x109d, 0x7820, 0xa086, - 0x0002, 0x00c0, 0x109d, 0x7823, 0x4000, 0x0068, 0x1095, 0x781b, - 0x0001, 0x2091, 0x5000, 0x2091, 0x4080, 0x2a70, 0x7003, 0x0000, - 0x2001, 0x017f, 0x2003, 0x0000, 0x2a70, 0x7000, 0xa08e, 0x0003, - 0x00c0, 0x10bd, 0x1078, 0x2d9c, 0x1078, 0x2451, 0x1078, 0x3dbe, - 0x1078, 0x3c31, 0x2009, 0x0100, 0x2104, 0xa082, 0x0002, 0x0048, - 0x10c1, 0x1078, 0x45c7, 0x0078, 0x10a4, 0x1079, 0x10c5, 0x0078, - 0x10aa, 0x1078, 0x597e, 0x0078, 0x10b9, 0x10cf, 0x10d0, 0x1143, - 0x10cd, 0x11be, 0x123e, 0x123f, 0x1240, 0x1078, 0x12cd, 0x007c, - 0x127e, 0x0f7e, 0x2091, 0x8000, 0x1078, 0x2ec1, 0x2079, 0x0100, - 0x7844, 0xa005, 0x00c0, 0x1134, 0x2011, 0x3558, 0x1078, 0x4689, - 0x780f, 0x00ff, 0x7840, 0xa084, 0xfffb, 0x7842, 0x2011, 0x8010, - 0x73b8, 0x1078, 0x2d59, 0x1078, 0x57c9, 0x2011, 0x0004, 0x1078, - 0x6a6d, 0x1078, 0x3ae0, 0x70c7, 0x0000, 0x70c3, 0x0000, 0x1078, - 0x1137, 0x72bc, 0x2079, 0x7751, 0x7804, 0xd0ac, 0x0040, 0x1101, - 0xc295, 0x72be, 0xa296, 0x0004, 0x0040, 0x1122, 0x2011, 0x0001, - 0x1078, 0x6a6d, 0x708b, 0x0000, 0x708f, 0xffff, 0x7003, 0x0002, - 0x0f7f, 0x1078, 0x214a, 0x2011, 0x0005, 0x1078, 0x58d8, 0x1078, - 0x4d96, 0x0c7e, 0x2061, 0x0100, 0x60e3, 0x0008, 0x0c7f, 0x127f, - 0x0078, 0x1136, 0x708b, 0x0000, 0x708f, 0xffff, 0x7003, 0x0002, - 0x2011, 0x0005, 0x1078, 0x58d8, 0x1078, 0x4d96, 0x0c7e, 0x2061, - 0x0100, 0x60e3, 0x0008, 0x0c7f, 0x0f7f, 0x127f, 0x007c, 0x0c7e, - 0x20a9, 0x0082, 0x2009, 0x007e, 0x1078, 0x3834, 0x8108, 0x00f0, - 0x113c, 0x0c7f, 0x007c, 0x127e, 0x2091, 0x8000, 0x708c, 0xa086, - 0xffff, 0x0040, 0x1151, 0x1078, 0x214a, 0x1078, 0x4d96, 0x0078, - 0x11bc, 0x70bc, 0xd09c, 0x0040, 0x1179, 0xd084, 0x0040, 0x1179, - 0x0f7e, 0x2079, 0x0100, 0x790c, 0xc1b5, 0x790e, 0x0f7f, 0xd08c, - 0x0040, 0x1179, 0x70c0, 0xa086, 0xffff, 0x0040, 0x1175, 0x1078, - 0x223f, 0x1078, 0x4d96, 0x2011, 0x0001, 0x2019, 0x0000, 0x1078, - 0x2277, 0x1078, 0x4d96, 0x0078, 0x11bc, 0x70c4, 0xa005, 0x00c0, - 0x11bc, 0x7088, 0xa005, 0x00c0, 0x11bc, 0x2001, 0x7752, 0x2004, - 0xd0ac, 0x0040, 0x119f, 0x157e, 0x0c7e, 0x20a9, 0x007f, 0x2009, - 0x0000, 0x017e, 0x1078, 0x384c, 0x00c0, 0x1192, 0x6000, 0xd0ec, - 0x00c0, 0x119a, 0x017f, 0x8108, 0x00f0, 0x1189, 0x0c7f, 0x157f, - 0x0078, 0x119f, 0x017f, 0x0c7f, 0x157f, 0x0078, 0x11bc, 0x7003, - 0x0003, 0x708f, 0xffff, 0x2001, 0x0000, 0x1078, 0x2025, 0x1078, - 0x2dd7, 0x2001, 0x7937, 0x2004, 0xa086, 0x0005, 0x00c0, 0x11b4, - 0x2011, 0x0000, 0x1078, 0x58d8, 0x2011, 0x0000, 0x1078, 0x58e2, - 0x1078, 0x4d96, 0x1078, 0x4e56, 0x127f, 0x007c, 0x017e, 0x0f7e, - 0x127e, 0x2091, 0x8000, 0x2079, 0x0100, 0x7940, 0xa18c, 0x0010, - 0x7942, 0x7924, 0xd1b4, 0x0040, 0x11cf, 0x7827, 0x0040, 0xd19c, - 0x0040, 0x11d4, 0x7827, 0x0008, 0x007e, 0x037e, 0x157e, 0x7900, - 0xa18a, 0x0003, 0x0050, 0x11fa, 0x7954, 0xd1ac, 0x00c0, 0x11fa, - 0x2009, 0x00f8, 0x1078, 0x35fa, 0x7843, 0x0090, 0x7843, 0x0010, - 0x20a9, 0x09c4, 0x7820, 0xd09c, 0x00c0, 0x11f2, 0x7824, 0xd0ac, - 0x00c0, 0x122e, 0x00f0, 0x11ea, 0x2001, 0x0001, 0x1078, 0x2025, - 0x0078, 0x1237, 0x7853, 0x0000, 0x782f, 0x0020, 0x20a9, 0x0008, - 0x00e0, 0x1200, 0x2091, 0x6000, 0x00f0, 0x1200, 0x7853, 0x0400, - 0x782f, 0x0000, 0x2009, 0x00f8, 0x1078, 0x35fa, 0x20a9, 0x000e, - 0x0005, 0x00f0, 0x1210, 0x7853, 0x1400, 0x7843, 0x0090, 0x7843, - 0x0010, 0x2019, 0x61a8, 0x7854, 0x0005, 0x0005, 0xd08c, 0x0040, - 0x1225, 0x7824, 0xd0ac, 0x00c0, 0x122e, 0x8319, 0x00c0, 0x121b, - 0x2001, 0x0001, 0x1078, 0x2025, 0x0078, 0x1235, 0x7828, 0xc09d, - 0x782a, 0x7827, 0x0008, 0x7827, 0x0040, 0x7853, 0x0400, 0x157f, - 0x037f, 0x007f, 0x127f, 0x0f7f, 0x017f, 0x007c, 0x007c, 0x007c, - 0x007c, 0x2a70, 0x2009, 0x0100, 0x2104, 0xa082, 0x0002, 0x0048, - 0x124d, 0x704f, 0xffff, 0x0078, 0x124f, 0x704f, 0x0000, 0x7053, - 0xffff, 0x7067, 0x0000, 0x706b, 0x0000, 0x2061, 0x7920, 0x6003, - 0x0909, 0x6007, 0x0000, 0x600b, 0x8800, 0x600f, 0x0200, 0x6013, - 0x00ff, 0x6017, 0x0003, 0x601b, 0x0000, 0x601f, 0x07d0, 0x2061, - 0x7928, 0x6003, 0x8000, 0x6007, 0x0000, 0x600b, 0x0000, 0x600f, - 0x0200, 0x6013, 0x00ff, 0x6017, 0x0000, 0x601b, 0x0001, 0x601f, - 0x0000, 0x007c, 0x1078, 0x12a0, 0x2011, 0x0000, 0x81ff, 0x0040, - 0x129f, 0xa186, 0x0001, 0x00c0, 0x128f, 0x705f, 0x8fff, 0x7057, - 0x8601, 0x7063, 0x0100, 0x705b, 0x8600, 0x0078, 0x129d, 0xa186, - 0x0002, 0x00c0, 0x1297, 0x2011, 0x0000, 0x0078, 0x129d, 0xa186, - 0x0005, 0x00c0, 0x129d, 0x2011, 0x0001, 0x1078, 0x12c7, 0x007c, - 0x2009, 0x0000, 0x2011, 0x0000, 0x1078, 0x12c7, 0x2019, 0xaaaa, - 0x2061, 0xffff, 0x2362, 0x2c24, 0x2061, 0x7fff, 0x2c04, 0xa406, - 0x0040, 0x12b5, 0xc18d, 0x0078, 0x12c2, 0xc185, 0x2011, 0x0001, - 0x1078, 0x12c7, 0x2061, 0xffff, 0x2362, 0x2c04, 0xa306, 0x00c0, - 0x12c2, 0xc195, 0x2011, 0x0001, 0x1078, 0x12c7, 0x007c, 0x3800, - 0xa084, 0xfffc, 0xa205, 0x20c0, 0x007c, 0x2091, 0x8000, 0x0068, - 0x12cf, 0x007e, 0x017e, 0x2079, 0x0000, 0x7818, 0xa084, 0x0000, - 0x00c0, 0x12d5, 0x017f, 0x792e, 0x007f, 0x782a, 0x007f, 0x7826, - 0x3900, 0x783a, 0x7823, 0x8002, 0x781b, 0x0001, 0x2091, 0x5000, - 0x2091, 0x4080, 0x2079, 0x7700, 0x7803, 0x0005, 0x0078, 0x12ee, - 0x007c, 0x2071, 0x7700, 0x7158, 0x712e, 0x2021, 0x0001, 0xa190, - 0x002d, 0xa298, 0x002d, 0x0048, 0x1307, 0x705c, 0xa302, 0x00c8, - 0x1307, 0x220a, 0x2208, 0x2310, 0x8420, 0x0078, 0x12f9, 0x200b, - 0x0000, 0x749e, 0x74a2, 0x007c, 0x0e7e, 0x127e, 0x2091, 0x8000, - 0x2071, 0x7700, 0x70a0, 0xa0ea, 0x0010, 0x00c8, 0x131a, 0xa06e, - 0x0078, 0x1324, 0x8001, 0x70a2, 0x702c, 0x2068, 0x2d04, 0x702e, - 0x206b, 0x0000, 0x6807, 0x0000, 0x127f, 0x0e7f, 0x007c, 0x0e7e, - 0x2071, 0x7700, 0x127e, 0x2091, 0x8000, 0x70a0, 0x8001, 0x00c8, - 0x1334, 0xa06e, 0x0078, 0x133d, 0x70a2, 0x702c, 0x2068, 0x2d04, - 0x702e, 0x206b, 0x0000, 0x6807, 0x0000, 0x127f, 0x0e7f, 0x007c, - 0x0e7e, 0x127e, 0x2091, 0x8000, 0x2071, 0x7700, 0x702c, 0x206a, - 0x2d00, 0x702e, 0x70a0, 0x8000, 0x70a2, 0x127f, 0x0e7f, 0x007c, - 0x8dff, 0x0040, 0x135c, 0x6804, 0x6807, 0x0000, 0x007e, 0x1078, - 0x1340, 0x0d7f, 0x0078, 0x1350, 0x007c, 0x0e7e, 0x2071, 0x7700, - 0x70a0, 0xa08a, 0x0010, 0xa00d, 0x0e7f, 0x007c, 0x0e7e, 0x2071, - 0x7959, 0x7007, 0x0000, 0x701b, 0x0000, 0x701f, 0x0000, 0x2071, - 0x0000, 0x7010, 0xa085, 0x8004, 0x7012, 0x0e7f, 0x007c, 0x0e7e, - 0x2270, 0x700b, 0x0000, 0x2071, 0x7959, 0x7018, 0xa088, 0x7962, - 0x220a, 0x8000, 0xa084, 0x0007, 0x701a, 0x7004, 0xa005, 0x00c0, - 0x138f, 0x0f7e, 0x2079, 0x0010, 0x1078, 0x13a0, 0x0f7f, 0x0e7f, - 0x007c, 0x0e7e, 0x2071, 0x7959, 0x7004, 0xa005, 0x00c0, 0x139e, - 0x0f7e, 0x2079, 0x0010, 0x1078, 0x13a0, 0x0f7f, 0x0e7f, 0x007c, - 0x7000, 0x0079, 0x13a3, 0x13a7, 0x1411, 0x142e, 0x142e, 0x7018, - 0x711c, 0xa106, 0x00c0, 0x13af, 0x7007, 0x0000, 0x007c, 0x0d7e, - 0xa180, 0x7962, 0x2004, 0x700a, 0x2068, 0x8108, 0xa18c, 0x0007, - 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0x2001, 0x7815, 0x20ac, 0x53a6, 0x2099, 0x7816, 0x20a1, 0x0018, - 0x20a9, 0x0008, 0x53a3, 0x7803, 0x0020, 0x127e, 0x2091, 0x8000, - 0x7803, 0x0001, 0x7007, 0x0004, 0x7000, 0xc08c, 0x7002, 0x700b, - 0x7811, 0x127f, 0x157f, 0x147f, 0x137f, 0x007c, 0x017e, 0x0e7e, - 0x2071, 0x7959, 0x0f7e, 0x2079, 0x0010, 0x7904, 0x7803, 0x0002, - 0xd1fc, 0x0040, 0x1471, 0xa18c, 0x0700, 0x0040, 0x146e, 0x7008, - 0xa080, 0x0002, 0x2003, 0x0200, 0x0078, 0x1471, 0x7004, 0x1079, - 0x1475, 0x0f7f, 0x0e7f, 0x017f, 0x007c, 0x13a0, 0x147d, 0x149f, - 0x14b9, 0x14e2, 0x147b, 0x0078, 0x147b, 0x137e, 0x147e, 0x157e, - 0x7014, 0x20a0, 0x2099, 0x0014, 0x7803, 0x0040, 0x7010, 0x20a8, - 0x53a5, 0x3400, 0x7016, 0x157f, 0x147f, 0x137f, 0x700c, 0xa005, - 0x0040, 0x14a6, 0x1078, 0x13d6, 0x007c, 0x7008, 0xa080, 0x0002, - 0x2003, 0x0100, 0x7007, 0x0000, 0x1078, 0x13a0, 0x007c, 0x700c, - 0xa005, 0x0040, 0x14a6, 0x1078, 0x13ec, 0x007c, 0x0d7e, 0x7008, - 0x2068, 0x7830, 0x6826, 0x7834, 0x682a, 0x7838, 0x682e, 0x783c, - 0x6832, 0x680b, 0x0100, 0x0d7f, 0x7007, 0x0000, 0x1078, 0x13a0, - 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0xac02, 0x00c8, 0x75bd, 0x0078, 0x756f, 0xa006, 0x127f, 0x027f, - 0x067f, 0x077f, 0x0c7f, 0x0e7f, 0x0f7f, 0x007c, 0xa8c5, 0x0001, - 0x0078, 0x75be, 0x087e, 0x2041, 0x0000, 0x2c20, 0x2019, 0x0002, - 0x6218, 0x1078, 0x5a2d, 0x1078, 0x5ace, 0x1078, 0x7562, 0x087f, - 0x007c, 0x027e, 0x047e, 0x087e, 0x0c7e, 0x157e, 0x2c20, 0x20a9, - 0x007f, 0x2009, 0x0000, 0x017e, 0x037e, 0x1078, 0x384c, 0x00c0, - 0x75f2, 0x2c10, 0x2041, 0x0000, 0x1078, 0x5a2d, 0x1078, 0x5ace, - 0x1078, 0x7562, 0x037f, 0x017f, 0x8108, 0x00f0, 0x75e3, 0x157f, - 0x0c7f, 0x087f, 0x047f, 0x027f, 0x007c, 0x017e, 0x0f7e, 0x8dff, - 0x0040, 0x7611, 0x6800, 0xa07d, 0x0040, 0x760e, 0x6803, 0x0000, - 0x6b52, 0x1078, 0x3b92, 0x2f68, 0x0078, 0x7602, 0x6b52, 0x1078, - 0x3b92, 0x0f7f, 0x017f, 0x007c, 0x0e7e, 0x047e, 0x037e, 0x2061, - 0x7e00, 0x2071, 0x7700, 0x7444, 0x7060, 0x8001, 0xa402, 0x00c8, - 0x763c, 0x2100, 0xac06, 0x0040, 0x762e, 0x6000, 0xa086, 0x0000, - 0x0040, 0x762e, 0x6008, 0xa206, 0x0040, 0x7638, 0xace0, 0x0008, - 0x2001, 0x7715, 0x2004, 0xac02, 0x00c8, 0x763c, 0x0078, 0x7619, - 0xa085, 0x0001, 0x0078, 0x763d, 0xa006, 0x037f, 0x047f, 0x0e7f, - 0x007c, 0x0d7e, 0x007e, 0x1078, 0x1327, 0x007f, 0x1040, 0x12cd, - 0x6837, 0x010d, 0x6803, 0x0000, 0x683b, 0x0000, 0x685b, 0x0000, - 0x685e, 0x6956, 0x6c46, 0x684f, 0x0000, 0x1078, 0x3b92, 0x0d7f, - 0x007c, 0x6700, 0xa786, 0x0000, 0x0040, 0x766c, 0xa786, 0x0001, - 0x0040, 0x766c, 0xa786, 0x000a, 0x0040, 0x766c, 0xa786, 0x0009, - 0x0040, 0x766c, 0xa085, 0x0001, 0x007c, 0x0e7e, 0x6018, 0x2070, - 0x70a0, 0xa206, 0x0e7f, 0x007c, 0x127e, 0x007e, 0x0e7e, 0x2091, - 0x8000, 0x2071, 0x7740, 0xd5a4, 0x0040, 0x7681, 0x7034, 0x8000, - 0x7036, 0xd5b4, 0x0040, 0x7687, 0x7030, 0x8000, 0x7032, 0xd5ac, - 0x0040, 0x768e, 0x2071, 0x774a, 0x1078, 0x76bd, 0x0e7f, 0x007f, - 0x127f, 0x007c, 0x127e, 0x007e, 0x0e7e, 0x2091, 0x8000, 0x2071, - 0x7740, 0xd5a4, 0x0040, 0x769f, 0x7034, 0x8000, 0x7036, 0xd5b4, - 0x0040, 0x76a5, 0x7030, 0x8000, 0x7032, 0xd5ac, 0x0040, 0x76ac, - 0x2071, 0x774a, 0x1078, 0x76bd, 0x0e7f, 0x007f, 0x127f, 0x007c, - 0x127e, 0x007e, 0x0e7e, 0x2091, 0x8000, 0x2071, 0x7742, 0x1078, - 0x76bd, 0x0e7f, 0x007f, 0x127f, 0x007c, 0x2e04, 0x8000, 0x2072, - 0x00c8, 0x76c6, 0x8e70, 0x2e04, 0x8000, 0x2072, 0x007c, 0x0e7e, - 0x2071, 0x7740, 0x1078, 0x76bd, 0x0e7f, 0x007c, 0x0e7e, 0x2071, - 0x7744, 0x1078, 0x76bd, 0x0e7f, 0x007c, 0x0001, 0x0002, 0x0004, - 0x0008, 0x0010, 0x0020, 0x0040, 0x0080, 0x0100, 0x0200, 0x0400, - 0x0800, 0x1000, 0x2000, 0x4000, 0x8000, 0x687d -}; -#endif diff --git a/sys/dev/ispfw/asm_2200.h b/sys/dev/ispfw/asm_2200.h deleted file mode 100644 index a9d80a2d3b5..00000000000 --- a/sys/dev/ispfw/asm_2200.h +++ /dev/null @@ -1,5326 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-3-Clause - * - * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2000 Qlogic, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms are permitted provided - * that the following conditions are met: - * 1. Redistribution of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistribution in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/************************************************************************ - * * - * --- ISP2200 Initiator/Target Firmware --- * - * with Fabric support (Public Loop) and * - * with expanded LUN addressing for FCTAPE. * - * * - ************************************************************************/ -/* - * Firmware Version 2.02.08 - */ -static const uint16_t isp_2200_risc_code[] = { - 0x0470, 0x0000, 0x0000, 0xa52b, 0x0000, 0x0002, 0x0002, 0x0008, - 0x0017, 0x2043, 0x4f50, 0x5952, 0x4947, 0x4854, 0x2032, 0x3030, - 0x3120, 0x514c, 0x4f47, 0x4943, 0x2043, 0x4f52, 0x504f, 0x5241, - 0x5449, 0x4f4e, 0x2049, 0x5350, 0x3232, 0x3030, 0x2046, 0x6972, - 0x6d77, 0x6172, 0x6520, 0x2056, 0x6572, 0x7369, 0x6f6e, 0x2030, - 0x322e, 0x3032, 0x2e30, 0x3820, 0x2020, 0x2020, 0x2400, 0x20c1, - 0x0005, 0x2001, 0x017f, 0x2003, 0x0000, 0x20c9, 0xbbff, 0x2091, - 0x2000, 0x2059, 0x0000, 0x2b78, 0x7823, 0x0004, 0x2089, 0x299f, - 0x2051, 0xb600, 0x2a70, 0x2029, 0xee00, 0x2031, 0xffff, 0x2039, - 0xede9, 0x2021, 0x0200, 0x0804, 0x146d, 0x20a1, 0xb52b, 0xa00e, - 0x20a9, 0x08d5, 0x41a4, 0x3400, 0x7562, 0x7666, 0x775e, 0x746a, - 0x746e, 0x20a1, 0xbe00, 0x7164, 0x810d, 0x810d, 0x810d, 0x810d, - 0xa18c, 0x000f, 0x2001, 0x000b, 0xa112, 0xa00e, 0x21a8, 0x41a4, - 0x3400, 0x8211, 0x1dd8, 0x7164, 0x3400, 0xa102, 0x0120, 0x0218, - 0x20a8, 0xa00e, 0x41a4, 0x3800, 0xd08c, 0x01d8, 0x2009, 0xb600, - 0x810d, 0x810d, 0x810d, 0x810d, 0xa18c, 0x000f, 0x2001, 0x0001, - 0xa112, 0x20a1, 0x1000, 0xa00e, 0x21a8, 0x41a4, 0x8211, 0x1de0, - 0x2009, 0xb600, 0x3400, 0xa102, 0x0120, 0x0218, 0x20a8, 0xa00e, - 0x41a4, 0x080c, 0x1416, 0x080c, 0x1637, 0x080c, 0x17d4, 0x080c, - 0x1fbe, 0x080c, 0x4c72, 0x080c, 0x8646, 0x080c, 0x15c0, 0x080c, - 0x2ef9, 0x080c, 0x5dfc, 0x080c, 0x53b3, 0x080c, 0x6940, 0x080c, - 0x2545, 0x080c, 0x6bd3, 0x080c, 0x642d, 0x080c, 0x23ff, 0x080c, - 0x2513, 0x2091, 0x3009, 0x7823, 0x0000, 0x1004, 0x10c5, 0x7820, - 0xa086, 0x0002, 0x1150, 0x7823, 0x4000, 0x0e04, 0x10bd, 0x781b, - 0x0001, 0x2091, 0x5000, 0x2091, 0x4080, 0x2a70, 0x7003, 0x0000, - 0x2a70, 0x7000, 0xa08e, 0x0003, 0x1158, 0x080c, 0x3f4f, 0x080c, - 0x2f20, 0x080c, 0x5e4a, 0x080c, 0x5562, 0x080c, 0x696b, 0x0c80, - 0x000b, 0x0c98, 0x10e4, 0x10e5, 0x1215, 0x10e2, 0x12e2, 0x1413, - 0x1414, 0x1415, 0x080c, 0x151a, 0x0005, 0x0126, 0x00f6, 0x2091, - 0x8000, 0x7000, 0xa086, 0x0001, 0x1904, 0x11f2, 0x080c, 0x158d, - 0x080c, 0x5b41, 0x0150, 0x080c, 0x5b67, 0x15c0, 0x2079, 0x0100, - 0x7828, 0xa085, 0x1800, 0x782a, 0x0488, 0x080c, 0x5a79, 0x7000, - 0xa086, 0x0001, 0x1904, 0x11f2, 0x708c, 0xa086, 0x0028, 0x1904, - 0x11f2, 0x2001, 0x0161, 0x2003, 0x0001, 0x2079, 0x0100, 0x7827, - 0xffff, 0x7a28, 0xa295, 0x1e2f, 0x7a2a, 0x2011, 0x5a14, 0x080c, - 0x6a0e, 0x2011, 0x5a07, 0x080c, 0x6ace, 0x2011, 0x5a56, 0x080c, - 0x6a0e, 0x2011, 0x4b23, 0x080c, 0x6a0e, 0x2011, 0x8030, 0x2019, - 0x0000, 0x708b, 0x0000, 0x080c, 0x1e05, 0x00e8, 0x080c, 0x44d6, - 0x2079, 0x0100, 0x7844, 0xa005, 0x1904, 0x11f2, 0x2011, 0x4b23, - 0x080c, 0x6a0e, 0x2011, 0x5a56, 0x080c, 0x6a0e, 0x080c, 0x1e05, - 0x2001, 0xb88d, 0x2004, 0x780e, 0x7840, 0xa084, 0xfffb, 0x7842, - 0x2011, 0x8010, 0x73cc, 0x080c, 0x3f13, 0x723c, 0xc284, 0x723e, - 0x2001, 0xb60c, 0x200c, 0xc1ac, 0x2102, 0x080c, 0x7fbc, 0x2011, - 0x0004, 0x080c, 0x9d1c, 0x080c, 0x52bf, 0x080c, 0x5b41, 0x0158, - 0x080c, 0x4c4a, 0x0140, 0x708b, 0x0001, 0x70c7, 0x0000, 0x080c, - 0x4673, 0x0804, 0x11f2, 0x080c, 0x537b, 0x0120, 0x7a0c, 0xc2b4, - 0x7a0e, 0x0060, 0x7073, 0x0000, 0x080c, 0xa0c4, 0x70d4, 0xd09c, - 0x1128, 0x70a0, 0xa005, 0x0110, 0x080c, 0x4c28, 0x70df, 0x0000, - 0x70db, 0x0000, 0x72d4, 0x080c, 0x5b41, 0x1180, 0x2011, 0x0000, - 0x0016, 0x080c, 0x2920, 0x2019, 0xb88f, 0x211a, 0x001e, 0x7053, - 0xffff, 0x7057, 0x00ef, 0x7077, 0x0000, 0x0020, 0x2019, 0xb88f, - 0x201b, 0x0000, 0x2079, 0xb652, 0x7804, 0xd0ac, 0x0108, 0xc295, - 0x72d6, 0x080c, 0x5b41, 0x0118, 0xa296, 0x0004, 0x0548, 0x2011, - 0x0001, 0x080c, 0x9d1c, 0x709b, 0x0000, 0x709f, 0xffff, 0x7003, - 0x0002, 0x2079, 0x0100, 0x7827, 0x0003, 0x7828, 0xa085, 0x0003, - 0x782a, 0x00fe, 0x080c, 0x2aed, 0x2011, 0x0005, 0x080c, 0x80fc, - 0x080c, 0x71e5, 0x080c, 0x5b41, 0x0148, 0x00c6, 0x2061, 0x0100, - 0x0016, 0x080c, 0x2920, 0x61e2, 0x001e, 0x00ce, 0x012e, 0x0420, - 0x709b, 0x0000, 0x709f, 0xffff, 0x7003, 0x0002, 0x00f6, 0x2079, - 0x0100, 0x7827, 0x0003, 0x7828, 0xa085, 0x0003, 0x782a, 0x00fe, - 0x2011, 0x0005, 0x080c, 0x80fc, 0x080c, 0x71e5, 0x080c, 0x5b41, - 0x0148, 0x00c6, 0x2061, 0x0100, 0x0016, 0x080c, 0x2920, 0x61e2, - 0x001e, 0x00ce, 0x00fe, 0x012e, 0x0005, 0x00c6, 0x080c, 0x5b41, - 0x1118, 0x20a9, 0x0100, 0x0010, 0x20a9, 0x0082, 0x080c, 0x5b41, - 0x1118, 0x2009, 0x0000, 0x0010, 0x2009, 0x007e, 0x080c, 0x2dcc, - 0x8108, 0x1f04, 0x1206, 0x00ce, 0x7073, 0x0000, 0x7074, 0xa084, - 0x00ff, 0x7076, 0x70a3, 0x0000, 0x0005, 0x0126, 0x2091, 0x8000, - 0x7000, 0xa086, 0x0002, 0x1904, 0x12e0, 0x709c, 0xa086, 0xffff, - 0x0130, 0x080c, 0x2aed, 0x080c, 0x71e5, 0x0804, 0x12e0, 0x70d4, - 0xd0ac, 0x1110, 0xd09c, 0x0540, 0xd084, 0x0530, 0x0006, 0x0016, - 0x2001, 0x0103, 0x2009, 0xb88d, 0x210c, 0x2102, 0x001e, 0x000e, - 0xd08c, 0x01d0, 0x70d8, 0xa086, 0xffff, 0x0190, 0x080c, 0x2c4c, - 0x080c, 0x71e5, 0x70d4, 0xd094, 0x1904, 0x12e0, 0x2011, 0x0001, - 0x2019, 0x0000, 0x080c, 0x2c84, 0x080c, 0x71e5, 0x0804, 0x12e0, - 0x70dc, 0xa005, 0x1904, 0x12e0, 0x7098, 0xa005, 0x1904, 0x12e0, - 0x70d4, 0xd0a4, 0x0118, 0xd0b4, 0x0904, 0x12e0, 0x080c, 0x537b, - 0x1904, 0x12e0, 0x2001, 0xb653, 0x2004, 0xd0ac, 0x01c8, 0x0156, - 0x00c6, 0x20a9, 0x007f, 0x2009, 0x0000, 0x0016, 0x080c, 0x501b, - 0x1118, 0x6000, 0xd0ec, 0x1138, 0x001e, 0x8108, 0x1f04, 0x126d, - 0x00ce, 0x015e, 0x0028, 0x001e, 0x00ce, 0x015e, 0x0804, 0x12e0, - 0x0006, 0x0016, 0x2001, 0x0103, 0x2009, 0xb88d, 0x210c, 0x2102, - 0x001e, 0x000e, 0x71a8, 0x81ff, 0x11b0, 0xa006, 0x2009, 0x0200, - 0x20a9, 0x0002, 0x20a1, 0xb8df, 0x40a1, 0x2009, 0x0700, 0x20a9, - 0x0002, 0x20a1, 0xb8cf, 0x40a1, 0x7070, 0x8007, 0x7174, 0x810f, - 0x20a9, 0x0002, 0x40a1, 0x20a1, 0xb8d3, 0x2009, 0x0000, 0x080c, - 0x1500, 0x2001, 0x0000, 0x810f, 0x20a9, 0x0002, 0x40a1, 0x7030, - 0xc08c, 0x7032, 0x7003, 0x0003, 0x709f, 0xffff, 0x080c, 0x1586, - 0xa006, 0x080c, 0x27f8, 0x080c, 0x3f85, 0x00f6, 0x2079, 0x0100, - 0x080c, 0x5b67, 0x0150, 0x080c, 0x5b41, 0x7828, 0x0118, 0xa084, - 0xe1ff, 0x0010, 0xa084, 0xffdf, 0x782a, 0x00fe, 0x2001, 0xb8e2, - 0x2004, 0xa086, 0x0005, 0x1120, 0x2011, 0x0000, 0x080c, 0x80fc, - 0x2011, 0x0000, 0x080c, 0x8106, 0x080c, 0x71e5, 0x080c, 0x72a2, - 0x012e, 0x0005, 0x0016, 0x0046, 0x00f6, 0x0126, 0x2091, 0x8000, - 0x2079, 0x0100, 0x2009, 0xb634, 0x2104, 0xa005, 0x1110, 0x080c, - 0x294c, 0x2009, 0x00f7, 0x080c, 0x4c11, 0x7940, 0xa18c, 0x0010, - 0x7942, 0x7924, 0xd1b4, 0x0110, 0x7827, 0x0040, 0xd19c, 0x0110, - 0x7827, 0x0008, 0x0006, 0x0036, 0x0156, 0x7954, 0xd1ac, 0x1904, - 0x1350, 0x080c, 0x5b53, 0x0158, 0x080c, 0x5b67, 0x1128, 0x2001, - 0xb89e, 0x2003, 0x0000, 0x0070, 0x080c, 0x5b49, 0x0dc0, 0x2001, - 0xb89e, 0x2003, 0xaaaa, 0x2001, 0xb89f, 0x2003, 0x0001, 0x080c, - 0x5a79, 0x0058, 0x080c, 0x5b41, 0x0140, 0x2009, 0x00f8, 0x080c, - 0x4c11, 0x7843, 0x0090, 0x7843, 0x0010, 0x20a9, 0x09c4, 0x7820, - 0xd09c, 0x1138, 0x080c, 0x5b41, 0x0138, 0x7824, 0xd0ac, 0x1904, - 0x13fa, 0x1f04, 0x132f, 0x0070, 0x7824, 0x080c, 0x5b5d, 0x0118, - 0xd0ac, 0x1904, 0x13fa, 0xa084, 0x1800, 0x0d98, 0x7003, 0x0001, - 0x0804, 0x13fa, 0x2001, 0x0001, 0x080c, 0x27f8, 0x0804, 0x1409, - 0x7850, 0xa084, 0x0180, 0x7852, 0x782f, 0x0020, 0x20a9, 0x0046, - 0x1d04, 0x1358, 0x080c, 0x6ab6, 0x1f04, 0x1358, 0x7850, 0xa084, - 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0x864e, 0x01e8, 0x2d00, 0x601a, 0x080c, 0xa0e3, 0x601f, 0x0001, - 0x2001, 0x0000, 0x080c, 0x4f5d, 0x2001, 0x0002, 0x080c, 0x4f6f, - 0x0126, 0x2091, 0x8000, 0x080c, 0x2cd1, 0x70dc, 0x8000, 0x70de, - 0x012e, 0x2009, 0x0002, 0x080c, 0x86d3, 0xa085, 0x0001, 0x00ce, - 0x00de, 0x007e, 0x001e, 0x0005, 0x00c6, 0x00d6, 0x0126, 0x2091, - 0x8000, 0x2009, 0x007f, 0x080c, 0x4fbf, 0x1190, 0x2c68, 0x080c, - 0x864e, 0x0170, 0x2d00, 0x601a, 0x6312, 0x601f, 0x0001, 0x620a, - 0x080c, 0xa0e3, 0x2009, 0x0022, 0x080c, 0x86d3, 0xa085, 0x0001, - 0x012e, 0x00de, 0x00ce, 0x0005, 0x00e6, 0x00c6, 0x0066, 0x0036, - 0x0026, 0x080c, 0x6e73, 0x080c, 0x6e16, 0x080c, 0x90fb, 0x2130, - 0x81ff, 0x0128, 0x20a9, 0x007e, 0x2009, 0x0000, 0x0020, 0x20a9, - 0x007f, 0x2009, 0x0000, 0x0016, 0x080c, 0x501b, 0x1120, 0x080c, - 0x521c, 0x080c, 0x4c7e, 0x001e, 0x8108, 0x1f04, 0x2cbb, 0x86ff, - 0x1110, 0x080c, 0x11f5, 0x002e, 0x003e, 0x006e, 0x00ce, 0x00ee, - 0x0005, 0x00e6, 0x00c6, 0x0036, 0x0026, 0x0016, 0x6218, 0x2270, - 0x72a0, 0x0026, 0x2019, 0x0029, 0x080c, 0x6e67, 0x0076, 0x2039, - 0x0000, 0x080c, 0x6d74, 0x2c08, 0x080c, 0xaf3e, 0x007e, 0x001e, - 0x2e60, 0x080c, 0x521c, 0x6210, 0x6314, 0x080c, 0x4c7e, 0x6212, - 0x6316, 0x001e, 0x002e, 0x003e, 0x00ce, 0x00ee, 0x0005, 0x00e6, - 0x0006, 0x6018, 0xa080, 0x0028, 0x2004, 0xa086, 0x0080, 0x0150, - 0x2071, 0xb600, 0x7098, 0xa005, 0x0110, 0x8001, 0x709a, 0x000e, - 0x00ee, 0x0005, 0x2071, 0xb600, 0x70dc, 0xa005, 0x0dc0, 0x8001, - 0x70de, 0x0ca8, 0x6000, 0xc08c, 0x6002, 0x0005, 0x00f6, 0x00e6, - 0x00c6, 0x0036, 0x0026, 0x0016, 0x0156, 0x2178, 0x81ff, 0x1118, - 0x20a9, 0x0001, 0x0098, 0x2001, 0xb653, 0x2004, 0xd0c4, 0x0150, - 0xd0a4, 0x0140, 0xa006, 0x0046, 0x2020, 0x2009, 0x002d, 0x080c, - 0xb1a4, 0x004e, 0x20a9, 0x00ff, 0x2011, 0x0000, 0x0026, 0xa28e, - 0x007e, 0x0904, 0x2d7e, 0xa28e, 0x007f, 0x0904, 0x2d7e, 0xa28e, - 0x0080, 0x05e0, 0xa288, 0xb735, 0x210c, 0x81ff, 0x05b8, 0x8fff, - 0x1148, 0x2001, 0xb8be, 0x0006, 0x2003, 0x0001, 0x04d9, 0x000e, - 0x2003, 0x0000, 0x00c6, 0x2160, 0x2001, 0x0001, 0x080c, 0x5385, - 0x00ce, 0x2019, 0x0029, 0x080c, 0x6e67, 0x0076, 0x2039, 0x0000, - 0x080c, 0x6d74, 0x00c6, 0x0026, 0x2160, 0x6204, 0xa294, 0x00ff, - 0xa286, 0x0006, 0x1118, 0x6007, 0x0404, 0x0028, 0x2001, 0x0004, - 0x8007, 0xa215, 0x6206, 0x002e, 0x00ce, 0x0016, 0x2c08, 0x080c, - 0xaf3e, 0x001e, 0x007e, 0x2160, 0x080c, 0x521c, 0x002e, 0x8210, - 0x1f04, 0x2d36, 0x015e, 0x001e, 0x002e, 0x003e, 0x00ce, 0x00ee, - 0x00fe, 0x0005, 0x0046, 0x0026, 0x0016, 0x2001, 0xb653, 0x2004, - 0xd0c4, 0x0148, 0xd0a4, 0x0138, 0xa006, 0x2220, 0x8427, 0x2009, - 0x0029, 0x080c, 0xb1a4, 0x001e, 0x002e, 0x004e, 0x0005, 0x0016, - 0x0026, 0x0036, 0x00c6, 0x7288, 0x82ff, 0x01f8, 0x2011, 0xb653, - 0x2214, 0xd2ac, 0x11d0, 0x2100, 0x080c, 0x2866, 0x81ff, 0x01b8, - 0x2019, 0x0001, 0x8314, 0xa2e0, 0xbdc0, 0x2c04, 0xd384, 0x0120, - 0xa084, 0xff00, 0x8007, 0x0010, 0xa084, 0x00ff, 0xa116, 0x0138, - 0xa096, 0x00ff, 0x0110, 0x8318, 0x0c68, 0xa085, 0x0001, 0x00ce, - 0x003e, 0x002e, 0x001e, 0x0005, 0x0016, 0x00c6, 0x0126, 0x2091, - 0x8000, 0x0016, 0x0026, 0x0036, 0x2110, 0x0026, 0x2019, 0x0029, - 0x080c, 0x8320, 0x002e, 0x080c, 0xb449, 0x003e, 0x002e, 0x001e, - 0xa180, 0xb735, 0x2004, 0xa065, 0x0158, 0x0016, 0x00c6, 0x2061, - 0xb9f5, 0x001e, 0x611a, 0x080c, 0x2cd1, 0x001e, 0x080c, 0x4fde, - 0x012e, 0x00ce, 0x001e, 0x0005, 0x2001, 0xb635, 0x2004, 0xd0cc, - 0x0005, 0x7eef, 0x7de8, 0x7ce4, 0x80e2, 0x7be1, 0x80e0, 0x80dc, - 0x80da, 0x7ad9, 0x80d6, 0x80d5, 0x80d4, 0x80d3, 0x80d2, 0x80d1, - 0x79ce, 0x78cd, 0x80cc, 0x80cb, 0x80ca, 0x80c9, 0x80c7, 0x80c6, - 0x77c5, 0x76c3, 0x80bc, 0x80ba, 0x75b9, 0x80b6, 0x74b5, 0x73b4, - 0x72b3, 0x80b2, 0x80b1, 0x80ae, 0x71ad, 0x80ac, 0x70ab, 0x6faa, - 0x6ea9, 0x80a7, 0x6da6, 0x6ca5, 0x6ba3, 0x6a9f, 0x699e, 0x689d, - 0x809b, 0x8098, 0x6797, 0x6690, 0x658f, 0x6488, 0x6384, 0x6282, - 0x8081, 0x8080, 0x617c, 0x607a, 0x8079, 0x5f76, 0x8075, 0x8074, - 0x8073, 0x8072, 0x8071, 0x806e, 0x5e6d, 0x806c, 0x5d6b, 0x5c6a, - 0x5b69, 0x8067, 0x5a66, 0x5965, 0x5863, 0x575c, 0x565a, 0x5559, - 0x8056, 0x8055, 0x5454, 0x5353, 0x5252, 0x5151, 0x504e, 0x4f4d, - 0x804c, 0x804b, 0x4e4a, 0x4d49, 0x8047, 0x4c46, 0x8045, 0x8043, - 0x803c, 0x803a, 0x8039, 0x8036, 0x4b35, 0x8034, 0x4a33, 0x4932, - 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0x0010, 0xa285, 0x0080, 0x6042, 0x6242, 0x0030, 0x6242, 0x708f, - 0x0000, 0x7083, 0x0000, 0x0000, 0x015e, 0x0005, 0x7080, 0xa08a, - 0x0003, 0x1210, 0x0023, 0x0010, 0x080c, 0x151a, 0x0005, 0x457a, - 0x45ca, 0x464c, 0x00f6, 0x7083, 0x0001, 0x20e1, 0xa000, 0xe000, - 0x20e1, 0x8700, 0x080c, 0x24a5, 0x20e1, 0x9080, 0x20e1, 0x4000, - 0x2079, 0xbc00, 0x207b, 0x2200, 0x7807, 0x00ef, 0x780b, 0x0000, - 0x780f, 0x00ef, 0x7813, 0x0138, 0x7817, 0x0000, 0x781b, 0x0000, - 0x781f, 0x0000, 0x7823, 0xffff, 0x7827, 0xffff, 0x782b, 0x0000, - 0x782f, 0x0000, 0x2079, 0xbc0c, 0x207b, 0x1101, 0x7807, 0x0000, - 0x2099, 0xb605, 0x20a1, 0xbc0e, 0x20a9, 0x0004, 0x53a3, 0x2079, - 0xbc12, 0x207b, 0x0000, 0x7807, 0x0000, 0x2099, 0xbc00, 0x20a1, - 0x020b, 0x20a9, 0x0014, 0x53a6, 0x60c3, 0x000c, 0x600f, 0x0000, - 0x080c, 0x4b55, 0x00fe, 0x7087, 0x0000, 0x6043, 0x0008, 0x6043, - 0x0000, 0x0005, 0x00d6, 0x7084, 0x7087, 0x0000, 0xa025, 0x0904, - 0x4634, 0x6020, 0xd0b4, 0x1904, 0x4632, 0x7194, 0x81ff, 0x0904, - 0x4622, 0xa486, 0x000c, 0x1904, 0x462d, 0xa480, 0x0018, 0x8004, - 0x20a8, 0x2011, 0xbc80, 0x2019, 0xbc00, 0x220c, 0x2304, 0xa106, - 0x11b8, 0x8210, 0x8318, 0x1f04, 0x45e5, 0x6043, 0x0004, 0x608b, - 0xbc94, 0x608f, 0xf0f0, 0x6043, 0x0006, 0x7083, 0x0002, 0x708f, - 0x0002, 0x2009, 0x07d0, 0x2011, 0x4b23, 0x080c, 0x6a94, 0x0490, - 0x2069, 0xbc80, 0x6930, 0xa18e, 0x1101, 0x1538, 0x6834, 0xa005, - 0x1520, 0x6900, 0xa18c, 0x00ff, 0x1118, 0x6804, 0xa005, 0x0190, - 0x2011, 0xbc8e, 0x2019, 0xb605, 0x20a9, 0x0004, 0x220c, 0x2304, - 0xa102, 0x0230, 0x1190, 0x8210, 0x8318, 0x1f04, 0x4616, 0x0068, - 0x7097, 0x0000, 0x20e1, 0x9080, 0x20e1, 0x4000, 0x2099, 0xbc80, - 0x20a1, 0x020b, 0x20a9, 0x0014, 0x53a6, 0x6043, 0x0008, 0x6043, - 0x0000, 0x0010, 0x00de, 0x0005, 0x6040, 0xa085, 0x0100, 0x6042, - 0x6020, 0xd0b4, 0x1db8, 0x60c3, 0x000c, 0x2011, 0xb8eb, 0x2013, - 0x0000, 0x7087, 0x0000, 0x20e1, 0x9080, 0x60a3, 0x0056, 0x60a7, - 0x9575, 0x080c, 0x7dea, 0x0c30, 0x0005, 0x708c, 0xa08a, 0x001d, - 0x1210, 0x0023, 0x0010, 0x080c, 0x151a, 0x0005, 0x4680, 0x468f, - 0x46b7, 0x46d0, 0x46f4, 0x471c, 0x4740, 0x4771, 0x4795, 0x47bd, - 0x47f4, 0x481c, 0x4838, 0x484e, 0x486e, 0x4881, 0x4889, 0x48b9, - 0x48dd, 0x4905, 0x4929, 0x495a, 0x4997, 0x49c6, 0x49e2, 0x4a21, - 0x4a41, 0x4a5a, 0x4a5b, 0x00c6, 0x2061, 0xb600, 0x6003, 0x0007, - 0x2061, 0x0100, 0x6004, 0xa084, 0xfff9, 0x6006, 0x00ce, 0x0005, - 0x608b, 0xbc94, 0x608f, 0xf0f0, 0x6043, 0x0002, 0x708f, 0x0001, - 0x2009, 0x07d0, 0x2011, 0x4b23, 0x080c, 0x6a94, 0x0005, 0x00f6, - 0x7084, 0xa086, 0x0014, 0x1508, 0x6043, 0x0000, 0x6020, 0xd0b4, - 0x11e0, 0x2079, 0xbc80, 0x7a30, 0xa296, 0x1102, 0x11a0, 0x7834, - 0xa005, 0x1188, 0x7a38, 0xd2fc, 0x0128, 0x70b8, 0xa005, 0x1110, - 0x70bb, 0x0001, 0x2011, 0x4b23, 0x080c, 0x6a0e, 0x708f, 0x0010, - 0x080c, 0x4889, 0x0010, 0x080c, 0x4b7b, 0x00fe, 0x0005, 0x708f, - 0x0003, 0x6043, 0x0004, 0x2011, 0x4b23, 0x080c, 0x6a0e, 0x080c, - 0x4bf9, 0x20a3, 0x1102, 0x20a3, 0x0000, 0x20a9, 0x000a, 0x20a3, - 0x0000, 0x1f04, 0x46c7, 0x60c3, 0x0014, 0x080c, 0x4b55, 0x0005, - 0x00f6, 0x7084, 0xa005, 0x01f0, 0x2011, 0x4b23, 0x080c, 0x6a0e, - 0xa086, 0x0014, 0x11a8, 0x2079, 0xbc80, 0x7a30, 0xa296, 0x1102, - 0x1178, 0x7834, 0xa005, 0x1160, 0x7a38, 0xd2fc, 0x0128, 0x70b8, - 0xa005, 0x1110, 0x70bb, 0x0001, 0x708f, 0x0004, 0x0029, 0x0010, - 0x080c, 0x4b7b, 0x00fe, 0x0005, 0x708f, 0x0005, 0x080c, 0x4bf9, - 0x20a3, 0x1103, 0x20a3, 0x0000, 0x3430, 0x2011, 0xbc8e, 0x080c, - 0x4c4a, 0x1160, 0x7078, 0xa005, 0x1148, 0x7150, 0xa186, 0xffff, - 0x0128, 0x080c, 0x4ae7, 0x0110, 0x080c, 0x4c28, 0x20a9, 0x0008, - 0x2298, 0x26a0, 0x53a6, 0x20a3, 0x0000, 0x20a3, 0x0000, 0x60c3, - 0x0014, 0x080c, 0x4b55, 0x0005, 0x00f6, 0x7084, 0xa005, 0x01f0, - 0x2011, 0x4b23, 0x080c, 0x6a0e, 0xa086, 0x0014, 0x11a8, 0x2079, - 0xbc80, 0x7a30, 0xa296, 0x1103, 0x1178, 0x7834, 0xa005, 0x1160, - 0x7a38, 0xd2fc, 0x0128, 0x70b8, 0xa005, 0x1110, 0x70bb, 0x0001, - 0x708f, 0x0006, 0x0029, 0x0010, 0x080c, 0x4b7b, 0x00fe, 0x0005, - 0x708f, 0x0007, 0x080c, 0x4bf9, 0x20a3, 0x1104, 0x20a3, 0x0000, - 0x3430, 0x2011, 0xbc8e, 0x080c, 0x4c4a, 0x11a8, 0x7078, 0xa005, - 0x1190, 0x7158, 0xa186, 0xffff, 0x0170, 0xa180, 0x2df9, 0x200d, - 0xa18c, 0xff00, 0x810f, 0x080c, 0x4ae7, 0x0128, 0x080c, 0x411d, - 0x0110, 0x080c, 0x289c, 0x20a9, 0x0008, 0x2298, 0x26a0, 0x53a6, - 0x20a3, 0x0000, 0x20a3, 0x0000, 0x60c3, 0x0014, 0x080c, 0x4b55, - 0x0005, 0x00f6, 0x7084, 0xa005, 0x01f0, 0x2011, 0x4b23, 0x080c, - 0x6a0e, 0xa086, 0x0014, 0x11a8, 0x2079, 0xbc80, 0x7a30, 0xa296, - 0x1104, 0x1178, 0x7834, 0xa005, 0x1160, 0x7a38, 0xd2fc, 0x0128, - 0x70b8, 0xa005, 0x1110, 0x70bb, 0x0001, 0x708f, 0x0008, 0x0029, - 0x0010, 0x080c, 0x4b7b, 0x00fe, 0x0005, 0x708f, 0x0009, 0x080c, - 0x4bf9, 0x20a3, 0x1105, 0x20a3, 0x0100, 0x3430, 0x080c, 0x4c4a, - 0x1150, 0x7078, 0xa005, 0x1138, 0x080c, 0x4a5c, 0x1170, 0xa085, - 0x0001, 0x080c, 0x289c, 0x20a9, 0x0008, 0x2099, 0xbc8e, 0x26a0, - 0x53a6, 0x20a3, 0x0000, 0x20a3, 0x0000, 0x60c3, 0x0014, 0x080c, - 0x4b55, 0x0010, 0x080c, 0x4673, 0x0005, 0x00f6, 0x7084, 0xa005, - 0x0588, 0x2011, 0x4b23, 0x080c, 0x6a0e, 0xa086, 0x0014, 0x1540, - 0x2079, 0xbc80, 0x7a30, 0xa296, 0x1105, 0x1510, 0x7834, 0x2011, - 0x0100, 0xa21e, 0x1160, 0x7a38, 0xd2fc, 0x0128, 0x70b8, 0xa005, - 0x1110, 0x70bb, 0x0001, 0x708f, 0x000a, 0x00b1, 0x0098, 0xa005, - 0x1178, 0x7a38, 0xd2fc, 0x0128, 0x70b8, 0xa005, 0x1110, 0x70bb, - 0x0001, 0x708b, 0x0000, 0x708f, 0x000e, 0x080c, 0x486e, 0x0010, - 0x080c, 0x4b7b, 0x00fe, 0x0005, 0x708f, 0x000b, 0x2011, 0xbc0e, - 0x22a0, 0x20a9, 0x0040, 0x2019, 0xffff, 0x43a4, 0x20a9, 0x0002, - 0x2009, 0x0000, 0x41a4, 0x080c, 0x4bf9, 0x20a3, 0x1106, 0x20a3, - 0x0000, 0x080c, 0x4c4a, 0x0118, 0x2013, 0x0000, 0x0020, 0x7054, - 0xa085, 0x0100, 0x2012, 0x2298, 0x20a9, 0x0042, 0x53a6, 0x60c3, - 0x0084, 0x080c, 0x4b55, 0x0005, 0x00f6, 0x7084, 0xa005, 0x01b0, - 0x2011, 0x4b23, 0x080c, 0x6a0e, 0xa086, 0x0084, 0x1168, 0x2079, - 0xbc80, 0x7a30, 0xa296, 0x1106, 0x1138, 0x7834, 0xa005, 0x1120, - 0x708f, 0x000c, 0x0029, 0x0010, 0x080c, 0x4b7b, 0x00fe, 0x0005, - 0x708f, 0x000d, 0x080c, 0x4bf9, 0x20a3, 0x1107, 0x20a3, 0x0000, - 0x2099, 0xbc8e, 0x20a9, 0x0040, 0x53a6, 0x20a3, 0x0000, 0x20a3, - 0x0000, 0x60c3, 0x0084, 0x080c, 0x4b55, 0x0005, 0x00f6, 0x7084, - 0xa005, 0x01d0, 0x2011, 0x4b23, 0x080c, 0x6a0e, 0xa086, 0x0084, - 0x1188, 0x2079, 0xbc80, 0x7a30, 0xa296, 0x1107, 0x1158, 0x7834, - 0xa005, 0x1140, 0x708b, 0x0001, 0x080c, 0x4beb, 0x708f, 0x000e, - 0x0029, 0x0010, 0x080c, 0x4b7b, 0x00fe, 0x0005, 0x708f, 0x000f, - 0x7087, 0x0000, 0x608b, 0xbc85, 0x608f, 0xb5b5, 0x6043, 0x0005, - 0x6043, 0x0004, 0x2009, 0x07d0, 0x2011, 0x4b23, 0x080c, 0x6a02, - 0x0005, 0x7084, 0xa005, 0x0120, 0x2011, 0x4b23, 0x080c, 0x6a0e, - 0x0005, 0x708f, 0x0011, 0x080c, 0x4c4a, 0x11a0, 0x7170, 0x81ff, - 0x0188, 0x2009, 0x0000, 0x7074, 0xa084, 0x00ff, 0x080c, 0x2852, - 0xa186, 0x007e, 0x0138, 0xa186, 0x0080, 0x0120, 0x2011, 0xbc8e, - 0x080c, 0x4ae7, 0x20e1, 0x9080, 0x20e1, 0x4000, 0x2099, 0xbc80, - 0x20a1, 0x020b, 0x7484, 0xa480, 0x0018, 0xa080, 0x0007, 0xa084, - 0x03f8, 0x8004, 0x20a8, 0x53a6, 0x60c3, 0x0014, 0x080c, 0x4b55, - 0x0005, 0x00f6, 0x7084, 0xa005, 0x01f0, 0x2011, 0x4b23, 0x080c, - 0x6a0e, 0xa086, 0x0014, 0x11a8, 0x2079, 0xbc80, 0x7a30, 0xa296, - 0x1103, 0x1178, 0x7834, 0xa005, 0x1160, 0x7a38, 0xd2fc, 0x0128, - 0x70b8, 0xa005, 0x1110, 0x70bb, 0x0001, 0x708f, 0x0012, 0x0029, - 0x0010, 0x080c, 0x4b7b, 0x00fe, 0x0005, 0x708f, 0x0013, 0x080c, - 0x4c05, 0x20a3, 0x1103, 0x20a3, 0x0000, 0x3430, 0x2011, 0xbc8e, - 0x080c, 0x4c4a, 0x1160, 0x7078, 0xa005, 0x1148, 0x7150, 0xa186, - 0xffff, 0x0128, 0x080c, 0x4ae7, 0x0110, 0x080c, 0x4c28, 0x20a9, - 0x0008, 0x2298, 0x26a0, 0x53a6, 0x20a3, 0x0000, 0x20a3, 0x0000, - 0x60c3, 0x0014, 0x080c, 0x4b55, 0x0005, 0x00f6, 0x7084, 0xa005, - 0x01f0, 0x2011, 0x4b23, 0x080c, 0x6a0e, 0xa086, 0x0014, 0x11a8, - 0x2079, 0xbc80, 0x7a30, 0xa296, 0x1104, 0x1178, 0x7834, 0xa005, - 0x1160, 0x7a38, 0xd2fc, 0x0128, 0x70b8, 0xa005, 0x1110, 0x70bb, - 0x0001, 0x708f, 0x0014, 0x0029, 0x0010, 0x080c, 0x4b7b, 0x00fe, - 0x0005, 0x708f, 0x0015, 0x080c, 0x4c05, 0x20a3, 0x1104, 0x20a3, - 0x0000, 0x3430, 0x2011, 0xbc8e, 0x080c, 0x4c4a, 0x11a8, 0x7078, - 0xa005, 0x1190, 0x7158, 0xa186, 0xffff, 0x0170, 0xa180, 0x2df9, - 0x200d, 0xa18c, 0xff00, 0x810f, 0x080c, 0x4ae7, 0x0128, 0x080c, - 0x411d, 0x0110, 0x080c, 0x289c, 0x20a9, 0x0008, 0x2298, 0x26a0, - 0x53a6, 0x20a3, 0x0000, 0x20a3, 0x0000, 0x60c3, 0x0014, 0x080c, - 0x4b55, 0x0005, 0x00f6, 0x7084, 0xa005, 0x05b8, 0x2011, 0x4b23, - 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0x2091, 0x8000, 0x6218, 0x2260, 0x6200, 0xa005, 0x0110, 0xc285, - 0x0008, 0xc284, 0x6202, 0x002e, 0x00ce, 0x012e, 0x0005, 0x0126, - 0x00c6, 0x2091, 0x8000, 0x6218, 0x2260, 0x6204, 0x0006, 0xa086, - 0x0006, 0x1180, 0x609c, 0xd0ac, 0x0168, 0x2001, 0xb653, 0x2004, - 0xd0a4, 0x0140, 0xa284, 0xff00, 0x8007, 0xa086, 0x0007, 0x1110, - 0x2011, 0x0600, 0x000e, 0xa294, 0xff00, 0xa215, 0x6206, 0x0006, - 0xa086, 0x0006, 0x1128, 0x6290, 0x82ff, 0x1110, 0x080c, 0x151a, - 0x000e, 0x00ce, 0x012e, 0x0005, 0x0126, 0x00c6, 0x2091, 0x8000, - 0x6218, 0x2260, 0x6204, 0x0006, 0xa086, 0x0006, 0x1178, 0x609c, - 0xd0a4, 0x0160, 0x2001, 0xb653, 0x2004, 0xd0ac, 0x1138, 0xa284, - 0x00ff, 0xa086, 0x0007, 0x1110, 0x2011, 0x0006, 0x000e, 0xa294, - 0x00ff, 0x8007, 0xa215, 0x6206, 0x00ce, 0x012e, 0x0005, 0x0026, - 0xa182, 0x00ff, 0x0218, 0xa085, 0x0001, 0x00b0, 0xa190, 0xb735, - 0x2204, 0xa065, 0x1180, 0x0016, 0x00d6, 0x080c, 0x15e4, 0x2d60, - 0x00de, 0x001e, 0x0d80, 0x2c00, 0x2012, 0x60a7, 0x0000, 0x60ab, - 0x0000, 0x080c, 0x4c7e, 0xa006, 0x002e, 0x0005, 0x0126, 0x2091, - 0x8000, 0x0026, 0xa182, 0x00ff, 0x0218, 0xa085, 0x0001, 0x0480, - 0x00d6, 0xa190, 0xb735, 0x2204, 0xa06d, 0x0540, 0x2013, 0x0000, - 0x00d6, 0x00c6, 0x2d60, 0x60a4, 0xa06d, 0x0110, 0x080c, 0x1614, - 0x60a8, 0xa06d, 0x0110, 0x080c, 0x1614, 0x00ce, 0x00de, 0x00d6, - 0x00c6, 0x68ac, 0x2060, 0x8cff, 0x0168, 0x600c, 0x0006, 0x6010, - 0x2068, 0x080c, 0x9d16, 0x0110, 0x080c, 0x1624, 0x080c, 0x86a4, - 0x00ce, 0x0c88, 0x00ce, 0x00de, 0x080c, 0x1614, 0x00de, 0xa006, - 0x002e, 0x012e, 0x0005, 0x0016, 0xa182, 0x00ff, 0x0218, 0xa085, - 0x0001, 0x0030, 0xa188, 0xb735, 0x2104, 0xa065, 0x0dc0, 0xa006, - 0x001e, 0x0005, 0x00d6, 0x0156, 0x0136, 0x0146, 0x600b, 0x0000, - 0x600f, 0x0000, 0x6000, 0xc08c, 0x6002, 0x080c, 0x5b41, 0x1558, - 0x60a0, 0xa086, 0x007e, 0x2069, 0xbc90, 0x0130, 0x2001, 0xb635, - 0x2004, 0xd0ac, 0x1500, 0x0098, 0x2d04, 0xd0e4, 0x01e0, 0x00d6, - 0x2069, 0xbc8e, 0x00c6, 0x2061, 0xb8b2, 0x6810, 0x2062, 0x6814, - 0x6006, 0x6818, 0x600a, 0x681c, 0x600e, 0x00ce, 0x00de, 0x8d69, - 0x2d04, 0x2069, 0x0140, 0xa005, 0x1110, 0x2001, 0x0001, 0x6886, - 0x2069, 0xb600, 0x68a6, 0x2069, 0xbc8e, 0x6808, 0x605e, 0x6810, - 0x6062, 0x6138, 0xa10a, 0x0208, 0x603a, 0x6814, 0x6066, 0x2099, - 0xbc96, 0xac88, 0x000a, 0x21a0, 0x20a9, 0x0004, 0x53a3, 0x2099, - 0xbc9a, 0xac88, 0x0006, 0x21a0, 0x20a9, 0x0004, 0x53a3, 0x2069, - 0xbcae, 0x6808, 0x606a, 0x690c, 0x616e, 0x6810, 0x6072, 0x6818, - 0x6076, 0x60a0, 0xa086, 0x007e, 0x1120, 0x2069, 0xbc8e, 0x690c, - 0x616e, 0xa182, 0x0211, 0x1218, 0x2009, 0x0008, 0x0400, 0xa182, - 0x0259, 0x1218, 0x2009, 0x0007, 0x00d0, 0xa182, 0x02c1, 0x1218, - 0x2009, 0x0006, 0x00a0, 0xa182, 0x0349, 0x1218, 0x2009, 0x0005, - 0x0070, 0xa182, 0x0421, 0x1218, 0x2009, 0x0004, 0x0040, 0xa182, - 0x0581, 0x1218, 0x2009, 0x0003, 0x0010, 0x2009, 0x0002, 0x6192, - 0x014e, 0x013e, 0x015e, 0x00de, 0x0005, 0x0016, 0x0026, 0x00e6, - 0x2071, 0xbc8d, 0x2e04, 0x6896, 0x2071, 0xbc8e, 0x7004, 0x689a, - 0x701c, 0x689e, 0x6a00, 0x2009, 0xb672, 0x210c, 0xd0bc, 0x0120, - 0xd1ec, 0x0110, 0xc2ad, 0x0008, 0xc2ac, 0xd0c4, 0x0120, 0xd1e4, - 0x0110, 0xc2bd, 0x0008, 0xc2bc, 0x6a02, 0x00ee, 0x002e, 0x001e, - 0x0005, 0x00d6, 0x0126, 0x2091, 0x8000, 0x60a4, 0xa06d, 0x01c0, - 0x6900, 0x81ff, 0x1540, 0x6a04, 0xa282, 0x0010, 0x1648, 0xad88, - 0x0004, 0x20a9, 0x0010, 0x2104, 0xa086, 0xffff, 0x0128, 0x8108, - 0x1f04, 0x50f3, 0x080c, 0x151a, 0x260a, 0x8210, 0x6a06, 0x0098, - 0x080c, 0x15fd, 0x01a8, 0x2d00, 0x60a6, 0x6803, 0x0000, 0xad88, - 0x0004, 0x20a9, 0x0010, 0x200b, 0xffff, 0x8108, 0x1f04, 0x510b, - 0x6807, 0x0001, 0x6e12, 0xa085, 0x0001, 0x012e, 0x00de, 0x0005, - 0xa006, 0x0cd8, 0x0126, 0x2091, 0x8000, 0x00d6, 0x60a4, 0xa00d, - 0x01a0, 0x2168, 0x6800, 0xa005, 0x1160, 0x080c, 0x5246, 0x1168, - 0x200b, 0xffff, 0x6804, 0xa08a, 0x0002, 0x0218, 0x8001, 0x6806, - 0x0020, 0x080c, 0x1614, 0x60a7, 0x0000, 0x00de, 0x012e, 0x0005, - 0x0126, 0x2091, 0x8000, 0x080c, 0x52a4, 0x0010, 0x080c, 0x4eff, - 0x080c, 0x51be, 0x1dd8, 0x080c, 0x5185, 0x012e, 0x0005, 0x00d6, - 0x0126, 0x2091, 0x8000, 0x60a8, 0xa06d, 0x01c0, 0x6950, 0x81ff, - 0x1540, 0x6a54, 0xa282, 0x0010, 0x1670, 0xad88, 0x0018, 0x20a9, - 0x0010, 0x2104, 0xa086, 0xffff, 0x0128, 0x8108, 0x1f04, 0x5159, - 0x080c, 0x151a, 0x260a, 0x8210, 0x6a56, 0x0098, 0x080c, 0x15fd, - 0x01d0, 0x2d00, 0x60aa, 0x6853, 0x0000, 0xad88, 0x0018, 0x20a9, - 0x0010, 0x200b, 0xffff, 0x8108, 0x1f04, 0x5171, 0x6857, 0x0001, - 0x6e62, 0x0010, 0x080c, 0x4f50, 0x0089, 0x1de0, 0xa085, 0x0001, - 0x012e, 0x00de, 0x0005, 0xa006, 0x0cd8, 0x0126, 0x2091, 0x8000, - 0x080c, 0x6d1c, 0x012e, 0x0005, 0xa01e, 0x0010, 0x2019, 0x0001, - 0xa00e, 0x0126, 0x2091, 0x8000, 0x604c, 0x2068, 0x6000, 0xd0dc, - 0x1170, 0x8dff, 0x01f8, 0x83ff, 0x0120, 0x6848, 0xa606, 0x0158, - 0x0030, 0x683c, 0xa406, 0x1118, 0x6840, 0xa506, 0x0120, 0x2d08, - 0x6800, 0x2068, 0x0c70, 0x080c, 0x81a5, 0x6a00, 0x604c, 0xad06, - 0x1110, 0x624e, 0x0018, 0xa180, 0x0000, 0x2202, 0x82ff, 0x1110, - 0x6152, 0x8dff, 0x012e, 0x0005, 0xa01e, 0x0010, 0x2019, 0x0001, - 0xa00e, 0x6080, 0x2068, 0x8dff, 0x01e8, 0x83ff, 0x0120, 0x6848, - 0xa606, 0x0158, 0x0030, 0x683c, 0xa406, 0x1118, 0x6840, 0xa506, - 0x0120, 0x2d08, 0x6800, 0x2068, 0x0c70, 0x6a00, 0x6080, 0xad06, - 0x1110, 0x6282, 0x0018, 0xa180, 0x0000, 0x2202, 0x82ff, 0x1110, - 0x6186, 0x8dff, 0x0005, 0xa016, 0x080c, 0x5240, 0x1110, 0x2011, - 0x0001, 0x080c, 0x528b, 0x1110, 0xa295, 0x0002, 0x0005, 0x080c, - 0x52bc, 0x0118, 0x080c, 0x9dcb, 0x0010, 0xa085, 0x0001, 0x0005, - 0x080c, 0x52bc, 0x0118, 0x080c, 0x9d5b, 0x0010, 0xa085, 0x0001, - 0x0005, 0x080c, 0x52bc, 0x0118, 0x080c, 0x9dae, 0x0010, 0xa085, - 0x0001, 0x0005, 0x080c, 0x52bc, 0x0118, 0x080c, 0x9d77, 0x0010, - 0xa085, 0x0001, 0x0005, 0x080c, 0x52bc, 0x0118, 0x080c, 0x9de7, - 0x0010, 0xa085, 0x0001, 0x0005, 0x0126, 0x0006, 0x00d6, 0x2091, - 0x8000, 0x6080, 0xa06d, 0x01a0, 0x6800, 0x0006, 0x6837, 0x0103, - 0x6b4a, 0x6847, 0x0000, 0x080c, 0x9f88, 0x0006, 0x6000, 0xd0fc, - 0x0110, 0x080c, 0xb445, 0x000e, 0x080c, 0x547a, 0x000e, 0x0c50, - 0x6083, 0x0000, 0x6087, 0x0000, 0x00de, 0x000e, 0x012e, 0x0005, - 0x60a4, 0xa00d, 0x1118, 0xa085, 0x0001, 0x0005, 0x00e6, 0x2170, - 0x7000, 0xa005, 0x1168, 0x20a9, 0x0010, 0xae88, 0x0004, 0x2104, - 0xa606, 0x0130, 0x8108, 0x1f04, 0x524f, 0xa085, 0x0001, 0x0008, - 0xa006, 0x00ee, 0x0005, 0x00d6, 0x0126, 0x2091, 0x8000, 0x60a4, - 0xa06d, 0x1128, 0x080c, 0x15fd, 0x01a0, 0x2d00, 0x60a6, 0x6803, - 0x0001, 0x6807, 0x0000, 0xad88, 0x0004, 0x20a9, 0x0010, 0x200b, - 0xffff, 0x8108, 0x1f04, 0x526f, 0xa085, 0x0001, 0x012e, 0x00de, - 0x0005, 0xa006, 0x0cd8, 0x00d6, 0x0126, 0x2091, 0x8000, 0x60a4, - 0xa06d, 0x0130, 0x60a7, 0x0000, 0x080c, 0x1614, 0xa085, 0x0001, - 0x012e, 0x00de, 0x0005, 0x60a8, 0xa00d, 0x1118, 0xa085, 0x0001, - 0x0005, 0x00e6, 0x2170, 0x7050, 0xa005, 0x1160, 0x20a9, 0x0010, - 0xae88, 0x0018, 0x2104, 0xa606, 0x0128, 0x8108, 0x1f04, 0x529a, - 0xa085, 0x0001, 0x00ee, 0x0005, 0x0126, 0x2091, 0x8000, 0x0c19, - 0x1188, 0x200b, 0xffff, 0x00d6, 0x60a8, 0x2068, 0x6854, 0xa08a, - 0x0002, 0x0218, 0x8001, 0x6856, 0x0020, 0x080c, 0x1614, 0x60ab, - 0x0000, 0x00de, 0x012e, 0x0005, 0x609c, 0xd0a4, 0x0005, 0x00f6, - 0x080c, 0x5b41, 0x01b0, 0x71b8, 0x81ff, 0x1198, 0x71d4, 0xd19c, - 0x0180, 0x2001, 0x007e, 0xa080, 0xb735, 0x2004, 0xa07d, 0x0148, - 0x7804, 0xa084, 0x00ff, 0xa086, 0x0006, 0x1118, 0x7800, 0xc0ed, - 0x7802, 0x2079, 0xb652, 0x7804, 0xd0a4, 0x01e8, 0x0156, 0x00c6, - 0x20a9, 0x007f, 0x2009, 0x0000, 0x0016, 0x080c, 0x501b, 0x1168, - 0x6004, 0xa084, 0xff00, 0x8007, 0xa096, 0x0004, 0x0118, 0xa086, - 0x0006, 0x1118, 0x6000, 0xc0ed, 0x6002, 0x001e, 0x8108, 0x1f04, - 0x52e4, 0x00ce, 0x015e, 0x080c, 0x537b, 0x0120, 0x2001, 0xb8b5, - 0x200c, 0x0038, 0x2079, 0xb652, 0x7804, 0xd0a4, 0x0130, 0x2009, - 0x07d0, 0x2011, 0x530f, 0x080c, 0x6a94, 0x00fe, 0x0005, 0x2011, - 0x530f, 0x080c, 0x6a0e, 0x080c, 0x537b, 0x01f0, 0x2001, 0xb7b3, - 0x2004, 0xa080, 0x0000, 0x200c, 0xc1ec, 0x2102, 0x2001, 0xb653, - 0x2004, 0xd0a4, 0x0130, 0x2009, 0x07d0, 0x2011, 0x530f, 0x080c, - 0x6a94, 0x00e6, 0x2071, 0xb600, 0x7073, 0x0000, 0x7077, 0x0000, - 0x080c, 0x2aed, 0x00ee, 0x04b0, 0x0156, 0x00c6, 0x20a9, 0x007f, - 0x2009, 0x0000, 0x0016, 0x080c, 0x501b, 0x1530, 0x6000, 0xd0ec, - 0x0518, 0x0046, 0x62a0, 0xa294, 0x00ff, 0x8227, 0xa006, 0x2009, - 0x0029, 0x080c, 0xb1a4, 0x6000, 0xc0e5, 0xc0ec, 0x6002, 0x6004, - 0xa084, 0x00ff, 0xa085, 0x0700, 0x6006, 0x2019, 0x0029, 0x080c, - 0x6e67, 0x0076, 0x2039, 0x0000, 0x080c, 0x6d74, 0x2009, 0x0000, - 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0x5b41, 0x1108, 0xc2ad, 0x2202, 0x0016, 0x0026, 0x0036, 0x2110, - 0x0026, 0x2019, 0x0028, 0x080c, 0x8320, 0x002e, 0x080c, 0xb449, - 0x003e, 0x002e, 0x001e, 0x0016, 0x0026, 0x0036, 0x2110, 0x2019, - 0x0028, 0x080c, 0x6e67, 0x0076, 0x2039, 0x0000, 0x080c, 0x6d74, - 0x00c6, 0x6018, 0xa065, 0x0110, 0x080c, 0x521c, 0x00ce, 0x2c08, - 0x080c, 0xaf3e, 0x007e, 0x003e, 0x002e, 0x001e, 0x080c, 0x4fde, - 0x080c, 0xa0db, 0x080c, 0x86a4, 0x080c, 0x71e5, 0x0005, 0x080c, - 0x8ca5, 0x0cb0, 0x080c, 0x8cd3, 0x0c98, 0xa186, 0x0014, 0x1db0, - 0x080c, 0x7102, 0x080c, 0x2cd1, 0x080c, 0x9f03, 0x1188, 0x080c, - 0x2cf7, 0x6018, 0xa080, 0x0028, 0x200c, 0x080c, 0x8ca5, 0xa186, - 0x007e, 0x1128, 0x2001, 0xb635, 0x200c, 0xc185, 0x2102, 0x08c0, - 0x080c, 0x9f14, 0x1118, 0x080c, 0x8ca5, 0x0890, 0x6004, 0xa08e, - 0x0032, 0x1158, 0x00e6, 0x00f6, 0x2071, 0xb682, 0x2079, 0x0000, - 0x080c, 0x3004, 0x00fe, 0x00ee, 0x0818, 0x6004, 0xa08e, 0x0021, - 0x0d50, 0xa08e, 0x0022, 0x090c, 0x8ca5, 0x0804, 0x8b90, 0xa0b2, - 0x0040, 0x1a04, 0x8c9a, 0x2008, 0x0002, 0x8c1f, 0x8c20, 0x8c23, - 0x8c26, 0x8c29, 0x8c2c, 0x8c1d, 0x8c1d, 0x8c1d, 0x8c1d, 0x8c1d, - 0x8c1d, 0x8c1d, 0x8c1d, 0x8c1d, 0x8c1d, 0x8c1d, 0x8c1d, 0x8c1d, - 0x8c1d, 0x8c1d, 0x8c1d, 0x8c1d, 0x8c1d, 0x8c1d, 0x8c1d, 0x8c1d, - 0x8c1d, 0x8c1d, 0x8c1d, 0x8c2f, 0x8c3e, 0x8c1d, 0x8c40, 0x8c3e, - 0x8c1d, 0x8c1d, 0x8c1d, 0x8c1d, 0x8c1d, 0x8c3e, 0x8c3e, 0x8c1d, - 0x8c1d, 0x8c1d, 0x8c1d, 0x8c1d, 0x8c1d, 0x8c1d, 0x8c1d, 0x8c7a, - 0x8c3e, 0x8c1d, 0x8c3a, 0x8c1d, 0x8c1d, 0x8c1d, 0x8c3b, 0x8c1d, - 0x8c1d, 0x8c1d, 0x8c3e, 0x8c71, 0x8c1d, 0x080c, 0x151a, 0x00f0, - 0x2001, 0x000b, 0x0460, 0x2001, 0x0003, 0x0448, 0x2001, 0x0005, - 0x0430, 0x2001, 0x0001, 0x0418, 0x2001, 0x0009, 0x0400, 0x080c, - 0x7102, 0x6003, 0x0005, 0x2001, 0xb8b8, 0x2004, 0x603e, 0x080c, - 0x71e5, 0x00a0, 0x0018, 0x0010, 0x080c, 0x4f6f, 0x0804, 0x8c8b, - 0x080c, 0x7102, 0x2001, 0xb8b6, 0x2004, 0x6016, 0x2001, 0xb8b8, - 0x2004, 0x603e, 0x6003, 0x0004, 0x080c, 0x71e5, 0x0005, 0x080c, - 0x4f6f, 0x080c, 0x7102, 0x6003, 0x0002, 0x2001, 0xb8b8, 0x2004, - 0x603e, 0x0036, 0x2019, 0xb65d, 0x2304, 0xa084, 0xff00, 0x1120, - 0x2001, 0xb8b6, 0x201c, 0x0040, 0x8007, 0xa09a, 0x0004, 0x0ec0, - 0x8003, 0x801b, 0x831b, 0xa318, 0x6316, 0x003e, 0x080c, 0x71e5, - 0x08e8, 0x080c, 0x7102, 0x080c, 0xa0db, 0x080c, 0x86a4, 0x080c, - 0x71e5, 0x08a0, 0x00e6, 0x00f6, 0x2071, 0xb682, 0x2079, 0x0000, - 0x080c, 0x3004, 0x00fe, 0x00ee, 0x080c, 0x7102, 0x080c, 0x86a4, - 0x080c, 0x71e5, 0x0818, 0x080c, 0x7102, 0x2001, 0xb8b8, 0x2004, - 0x603e, 0x6003, 0x0002, 0x2001, 0xb8b6, 0x2004, 0x6016, 0x080c, - 0x71e5, 0x0005, 0x2600, 0x2008, 0x0002, 0x8ca3, 0x8ca3, 0x8ca3, - 0x8c8b, 0x8c8b, 0x8ca3, 0x080c, 0x151a, 0x00e6, 0x0026, 0x0016, - 0x080c, 0x9d16, 0x0508, 0x6010, 0x2070, 0x7034, 0xa086, 0x0139, - 0x1148, 0x2001, 0x0030, 0x2009, 0x0000, 0x2011, 0x4005, 0x080c, - 0xa192, 0x0090, 0x7038, 0xd0fc, 0x0178, 0x7007, 0x0000, 0x0016, - 0x6004, 0xa08e, 0x0021, 0x0160, 0xa08e, 0x003d, 0x0148, 0x001e, - 0x7037, 0x0103, 0x7033, 0x0100, 0x001e, 0x002e, 0x00ee, 0x0005, - 0x001e, 0x0009, 0x0cc8, 0x00e6, 0xacf0, 0x0004, 0x2e74, 0x7000, - 0x2070, 0x7037, 0x0103, 0x7023, 0x8001, 0x00ee, 0x0005, 0x00d6, - 0x6618, 0x2668, 0x6804, 0xa084, 0x00ff, 0x00de, 0xa0b2, 0x000c, - 0x1a0c, 0x151a, 0x6604, 0xa6b6, 0x0043, 0x1120, 0x080c, 0xa14e, - 0x0804, 0x8d44, 0x6604, 0xa6b6, 0x0033, 0x1120, 0x080c, 0xa0fe, - 0x0804, 0x8d44, 0x6604, 0xa6b6, 0x0028, 0x1120, 0x080c, 0x9f44, - 0x0804, 0x8d44, 0x6604, 0xa6b6, 0x0029, 0x1118, 0x080c, 0x9f5b, - 0x04d8, 0x6604, 0xa6b6, 0x001f, 0x1118, 0x080c, 0x8812, 0x04a0, - 0x6604, 0xa6b6, 0x0000, 0x1118, 0x080c, 0x8a66, 0x0468, 0x6604, - 0xa6b6, 0x0022, 0x1118, 0x080c, 0x883a, 0x0430, 0x6604, 0xa6b6, - 0x0035, 0x1118, 0x080c, 0x88a1, 0x00f8, 0x6604, 0xa6b6, 0x0039, - 0x1118, 0x080c, 0x8a02, 0x00c0, 0x6604, 0xa6b6, 0x003d, 0x1118, - 0x080c, 0x8854, 0x0088, 0x6604, 0xa6b6, 0x0044, 0x1118, 0x080c, - 0x8874, 0x0050, 0xa1b6, 0x0015, 0x1110, 0x0053, 0x0028, 0xa1b6, - 0x0016, 0x1118, 0x0804, 0x8f08, 0x0005, 0x080c, 0x86ef, 0x0ce0, - 0x8d6b, 0x8d6e, 0x8d6b, 0x8db0, 0x8d6b, 0x8e95, 0x8f16, 0x8d6b, - 0x8d6b, 0x8ee4, 0x8d6b, 0x8ef8, 0xa1b6, 0x0048, 0x0140, 0x20e1, - 0x0005, 0x3d18, 0x3e20, 0x2c10, 0x080c, 0x1863, 0x0005, 0x00e6, - 0xacf0, 0x0004, 0x2e74, 0x7000, 0x2070, 0x7037, 0x0103, 0x00ee, - 0x080c, 0x86a4, 0x0005, 0xe000, 0xe000, 0x0005, 0x00e6, 0x2071, - 0xb600, 0x7084, 0xa086, 0x0074, 0x1530, 0x080c, 0xaf15, 0x11b0, - 0x00d6, 0x6018, 0x2068, 0x7030, 0xd08c, 0x0128, 0x6800, 0xd0bc, - 0x0110, 0xc0c5, 0x6802, 0x00d9, 0x00de, 0x2001, 0x0006, 0x080c, - 0x4f6f, 0x080c, 0x2cf7, 0x080c, 0x86a4, 0x0078, 0x2001, 0x000a, - 0x080c, 0x4f6f, 0x080c, 0x2cf7, 0x6003, 0x0001, 0x6007, 0x0001, - 0x080c, 0x6d45, 0x0010, 0x080c, 0x8e82, 0x00ee, 0x0005, 0x6800, - 0xd084, 0x0168, 0x2001, 0x0000, 0x080c, 0x4f5d, 0x2069, 0xb652, - 0x6804, 0xd0a4, 0x0120, 0x2001, 0x0006, 0x080c, 0x4f9c, 0x0005, - 0x00d6, 0x2011, 0xb621, 0x2204, 0xa086, 0x0074, 0x1904, 0x8e7f, - 0x6018, 0x2068, 0x6aa0, 0xa286, 0x007e, 0x1120, 0x080c, 0x902e, - 0x0804, 0x8e1e, 0x080c, 0x9024, 0x6018, 0x2068, 0xa080, 0x0028, - 0x2014, 0xa286, 0x0080, 0x11c0, 0x6813, 0x00ff, 0x6817, 0xfffc, - 0x6010, 0xa005, 0x0138, 0x2068, 0x6807, 0x0000, 0x6837, 0x0103, - 0x6833, 0x0200, 0x2001, 0x0006, 0x080c, 0x4f6f, 0x080c, 0x2cf7, - 0x080c, 0x86a4, 0x0804, 0x8e80, 0x00e6, 0x2071, 0xb635, 0x2e04, - 0xd09c, 0x0188, 0x2071, 0xbc80, 0x7108, 0x720c, 0xa18c, 0x00ff, - 0x1118, 0xa284, 0xff00, 0x0138, 0x6018, 0x2070, 0x70a0, 0xd0bc, - 0x1110, 0x7112, 0x7216, 0x00ee, 0x6010, 0xa005, 0x0198, 0x2068, - 0x6838, 0xd0f4, 0x0178, 0x6834, 0xa084, 0x00ff, 0xa086, 0x0039, - 0x1958, 0x2001, 0x0000, 0x2009, 0x0000, 0x2011, 0x4000, 0x080c, - 0xa192, 0x0840, 0x2001, 0x0004, 0x080c, 0x4f6f, 0x6003, 0x0001, - 0x6007, 0x0003, 0x080c, 0x6d45, 0x0804, 0x8e80, 0x685c, 0xd0e4, - 0x01d8, 0x080c, 0xa08e, 0x080c, 0x5b41, 0x0118, 0xd0dc, 0x1904, - 0x8dda, 0x2011, 0xb635, 0x2204, 0xc0ad, 0x2012, 0x2001, 0xb88f, - 0x2004, 0x00f6, 0x2079, 0x0100, 0x78e3, 0x0000, 0x080c, 0x28a7, - 0x78e2, 0x00fe, 0x0804, 0x8dda, 0x080c, 0xa0c4, 0x2011, 0xb635, - 0x2204, 0xc0a5, 0x2012, 0x0006, 0x080c, 0xb037, 0x000e, 0x1904, - 0x8dda, 0xc0b5, 0x2012, 0x2001, 0x0006, 0x080c, 0x4f6f, 0x2001, - 0x0000, 0x080c, 0x4f5d, 0x00c6, 0x2009, 0x00ef, 0x00f6, 0x2079, - 0x0100, 0x79ea, 0x7932, 0x7936, 0x00fe, 0x080c, 0x287c, 0x00f6, - 0x2079, 0xb600, 0x7976, 0x2100, 0x2009, 0x0000, 0x080c, 0x2852, - 0x7952, 0x00fe, 0x8108, 0x080c, 0x4fbf, 0x2c00, 0x00ce, 0x1904, - 0x8dda, 0x601a, 0x2001, 0x0002, 0x080c, 0x4f6f, 0x601f, 0x0001, - 0x6003, 0x0001, 0x6007, 0x0002, 0x080c, 0x6d45, 0x0008, 0x0011, - 0x00de, 0x0005, 0x2001, 0x0007, 0x080c, 0x4f6f, 0x2001, 0xb600, - 0x2004, 0xa086, 0x0003, 0x1120, 0x2001, 0x0007, 0x080c, 0x4f9c, - 0x080c, 0x2cf7, 0x080c, 0x86a4, 0x0005, 0x00e6, 0x0026, 0x0016, - 0x2071, 0xb600, 0x7084, 0xa086, 0x0014, 0x15f0, 0x7000, 0xa086, - 0x0003, 0x1128, 0x6010, 0xa005, 0x1110, 0x080c, 0x3f85, 0x00d6, - 0x6018, 0x2068, 0x080c, 0x50bd, 0x080c, 0x8d9f, 0x00de, 0x080c, - 0x90dd, 0x1550, 0x00d6, 0x6018, 0x2068, 0x6890, 0x00de, 0xa005, - 0x0518, 0x2001, 0x0006, 0x080c, 0x4f6f, 0x00e6, 0x6010, 0xa075, - 0x01a8, 0x7034, 0xa084, 0x00ff, 0xa086, 0x0039, 0x1148, 0x2001, - 0x0000, 0x2009, 0x0000, 0x2011, 0x4000, 0x080c, 0xa192, 0x0030, - 0x7007, 0x0000, 0x7037, 0x0103, 0x7033, 0x0200, 0x00ee, 0x080c, - 0x2cf7, 0x080c, 0x86a4, 0x0020, 0x080c, 0x8ca5, 0x080c, 0x8e82, - 0x001e, 0x002e, 0x00ee, 0x0005, 0x2011, 0xb621, 0x2204, 0xa086, - 0x0014, 0x1158, 0x2001, 0x0002, 0x080c, 0x4f6f, 0x6003, 0x0001, - 0x6007, 0x0001, 0x080c, 0x6d45, 0x0010, 0x080c, 0x8e82, 0x0005, - 0x2011, 0xb621, 0x2204, 0xa086, 0x0004, 0x1138, 0x2001, 0x0007, - 0x080c, 0x4f6f, 0x080c, 0x86a4, 0x0010, 0x080c, 0x8e82, 0x0005, - 0x000b, 0x0005, 0x8d6b, 0x8f21, 0x8d6b, 0x8f55, 0x8d6b, 0x8fe0, - 0x8f16, 0x8d6b, 0x8d6b, 0x8ff3, 0x8d6b, 0x9003, 0x6604, 0xa686, - 0x0003, 0x0904, 0x8e95, 0xa6b6, 0x001e, 0x1110, 0x080c, 0x86a4, - 0x0005, 0x00d6, 0x00c6, 0x080c, 0x9013, 0x1178, 0x2001, 0x0000, - 0x080c, 0x4f5d, 0x2001, 0x0002, 0x080c, 0x4f6f, 0x6003, 0x0001, - 0x6007, 0x0002, 0x080c, 0x6d45, 0x00e8, 0x2009, 0xbc8e, 0x2104, - 0xa086, 0x0009, 0x1160, 0x6018, 0x2068, 0x6840, 0xa084, 0x00ff, - 0xa005, 0x0170, 0x8001, 0x6842, 0x6017, 0x000a, 0x0058, 0x2009, - 0xbc8f, 0x2104, 0xa084, 0xff00, 0xa086, 0x1900, 0x1108, 0x08d0, - 0x080c, 0x8e82, 0x00ce, 0x00de, 0x0005, 0x0026, 0x2011, 0x0000, - 0x080c, 0x9021, 0x00d6, 0x2069, 0xb89e, 0x2d04, 0xa005, 0x0168, - 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0x9563, 0x9563, 0x9563, 0x080c, 0x151a, 0x0076, 0x00f6, 0x00e6, - 0x00d6, 0x2071, 0xbc8c, 0x6110, 0x2178, 0x7614, 0xa6b4, 0x0fff, - 0x00f6, 0x2c78, 0x080c, 0x5377, 0x00fe, 0x0150, 0xa684, 0x00ff, - 0x1138, 0x6020, 0xd0f4, 0x0120, 0x080c, 0x9ff1, 0x0804, 0x961b, - 0x7e46, 0x7f4c, 0xc7e5, 0x7f4e, 0x6218, 0x2268, 0x6a3c, 0x82ff, - 0x0110, 0x8211, 0x6a3e, 0x86ff, 0x0904, 0x9611, 0xa694, 0xff00, - 0xa284, 0x0c00, 0x0120, 0x7018, 0x7862, 0x701c, 0x785e, 0xa284, - 0x0300, 0x0904, 0x960f, 0xa686, 0x0100, 0x1140, 0x2001, 0xbc99, - 0x2004, 0xa005, 0x1118, 0xc6c4, 0x7e46, 0x0c28, 0x080c, 0x15fd, - 0x090c, 0x151a, 0x2d00, 0x784a, 0x7f4c, 0xa7bd, 0x0200, 0x7f4e, - 0x6837, 0x0103, 0x7838, 0x683a, 0x783c, 0x683e, 0x7840, 0x6842, - 0x6e46, 0xa68c, 0x0c00, 0x0120, 0x7318, 0x6b62, 0x731c, 0x6b5e, - 0xa68c, 0x00ff, 0xa186, 0x0002, 0x0180, 0xa186, 0x0028, 0x1118, - 0x684b, 0x001c, 0x0060, 0xd6dc, 0x0118, 0x684b, 0x0015, 0x0038, - 0xd6d4, 0x0118, 0x684b, 0x0007, 0x0010, 0x684b, 0x0000, 0x6f4e, - 0x7850, 0x6852, 0x7854, 0x6856, 0xa01e, 0xd6c4, 0x0198, 0x7328, - 0x732c, 0x6b56, 0x83ff, 0x0170, 0xa38a, 0x0009, 0x0210, 0x2019, - 0x0008, 0x0036, 0x2308, 0x2019, 0xbc98, 0xad90, 0x0019, 0x080c, - 0x99c9, 0x003e, 0xd6cc, 0x01d8, 0x7124, 0x695a, 0x81ff, 0x01b8, - 0xa192, 0x0021, 0x1250, 0x2071, 0xbc98, 0x831c, 0x2300, 0xae18, - 0xad90, 0x001d, 0x080c, 0x99c9, 0x0050, 0x7838, 0xd0fc, 0x0120, - 0x2009, 0x0020, 0x695a, 0x0c78, 0x2d78, 0x080c, 0x996e, 0xd6dc, - 0x1110, 0xa006, 0x0030, 0x2001, 0x0001, 0x2071, 0xbc8c, 0x7218, - 0x731c, 0x080c, 0x18b6, 0x00de, 0x00ee, 0x00fe, 0x007e, 0x0005, - 0x2001, 0xb8b8, 0x2004, 0x603e, 0x20e1, 0x0005, 0x3d18, 0x3e20, - 0x2c10, 0x080c, 0x1863, 0x0005, 0x2001, 0xb8b8, 0x2004, 0x603e, - 0x00d6, 0x6003, 0x0002, 0x6110, 0x2168, 0x694c, 0xd1e4, 0x0904, - 0x9737, 0x603f, 0x0000, 0x00f6, 0x2c78, 0x080c, 0x5377, 0x00fe, - 0x0560, 0x6814, 0x6910, 0xa115, 0x0540, 0x6a60, 0xa206, 0x1118, - 0x685c, 0xa106, 0x0510, 0x684c, 0xc0e4, 0x684e, 0x6847, 0x0000, - 0x6863, 0x0000, 0x685f, 0x0000, 0x6020, 0xd0f4, 0x1158, 0x697c, - 0x6810, 0xa102, 0x603a, 0x6980, 0x6814, 0xa103, 0x6036, 0x6020, - 0xc0f5, 0x6022, 0x00d6, 0x6018, 0x2068, 0x683c, 0x8000, 0x683e, - 0x00de, 0x080c, 0x9ff1, 0x0804, 0x9737, 0x694c, 0xd1cc, 0x0904, - 0x9707, 0x6948, 0x6838, 0xd0fc, 0x0904, 0x96ca, 0x0016, 0x684c, - 0x0006, 0x6850, 0x0006, 0x00f6, 0x2178, 0x7944, 0xa184, 0x00ff, - 0xa0b6, 0x0002, 0x01e0, 0xa086, 0x0028, 0x1128, 0x684b, 0x001c, - 0x784b, 0x001c, 0x00e8, 0xd1dc, 0x0158, 0x684b, 0x0015, 0x784b, - 0x0015, 0x080c, 0xa17b, 0x0118, 0x7944, 0xc1dc, 0x7946, 0x0080, - 0xd1d4, 0x0128, 0x684b, 0x0007, 0x784b, 0x0007, 0x0048, 0x684c, - 0xd0ac, 0x0130, 0x6810, 0x6914, 0xa115, 0x0110, 0x080c, 0x953f, - 0x6848, 0x784a, 0x6860, 0x7862, 0x685c, 0x785e, 0xad90, 0x000d, - 0xaf98, 0x000d, 0x2009, 0x0020, 0x0156, 0x21a8, 0x2304, 0x2012, - 0x8318, 0x8210, 0x1f04, 0x96b6, 0x015e, 0x00fe, 0x000e, 0x6852, - 0x000e, 0x684e, 0x080c, 0xa1f3, 0x001e, 0x2168, 0x080c, 0x1624, - 0x0804, 0x9732, 0x0016, 0x00f6, 0x2178, 0x7944, 0xa184, 0x00ff, - 0xa0b6, 0x0002, 0x01e0, 0xa086, 0x0028, 0x1128, 0x684b, 0x001c, - 0x784b, 0x001c, 0x00e8, 0xd1dc, 0x0158, 0x684b, 0x0015, 0x784b, - 0x0015, 0x080c, 0xa17b, 0x0118, 0x7944, 0xc1dc, 0x7946, 0x0080, - 0xd1d4, 0x0128, 0x684b, 0x0007, 0x784b, 0x0007, 0x0048, 0x684c, - 0xd0ac, 0x0130, 0x6810, 0x6914, 0xa115, 0x0110, 0x080c, 0x953f, - 0x6860, 0x7862, 0x685c, 0x785e, 0x684c, 0x784e, 0x00fe, 0x080c, - 0x1624, 0x00de, 0x080c, 0xa1f3, 0x080c, 0x99b9, 0x0458, 0x6837, - 0x0103, 0x6944, 0xa184, 0x00ff, 0xa0b6, 0x0002, 0x01b0, 0xa086, - 0x0028, 0x1118, 0x684b, 0x001c, 0x00d8, 0xd1dc, 0x0148, 0x684b, - 0x0015, 0x080c, 0xa17b, 0x0118, 0x6944, 0xc1dc, 0x6946, 0x0080, - 0xd1d4, 0x0118, 0x684b, 0x0007, 0x0058, 0x684b, 0x0000, 0x684c, - 0xd0ac, 0x0130, 0x6810, 0x6914, 0xa115, 0x0110, 0x080c, 0x953f, - 0x080c, 0x547a, 0x080c, 0x9fbf, 0x1110, 0x080c, 0x86a4, 0x00de, - 0x0005, 0x080c, 0x7102, 0x0010, 0x080c, 0x7198, 0x080c, 0x9d16, - 0x01c0, 0x00d6, 0x6110, 0x2168, 0x6837, 0x0103, 0x2009, 0xb60c, - 0x210c, 0xd18c, 0x11c0, 0xd184, 0x1198, 0x6108, 0x694a, 0xa18e, - 0x0029, 0x1110, 0x080c, 0xb43c, 0x6847, 0x0000, 0x080c, 0x547a, - 0x00de, 0x080c, 0x86a4, 0x080c, 0x71e5, 0x080c, 0x72a2, 0x0005, - 0x684b, 0x0004, 0x0c88, 0x684b, 0x0004, 0x0c70, 0xa182, 0x0040, - 0x0002, 0x977c, 0x977c, 0x977c, 0x977c, 0x977c, 0x977e, 0x977c, - 0x9781, 0x977c, 0x977c, 0x977c, 0x977c, 0x977c, 0x977c, 0x977c, - 0x977c, 0x977c, 0x977c, 0x977c, 0x080c, 0x151a, 0x080c, 0x86a4, - 0x0005, 0x0006, 0x0026, 0xa016, 0x080c, 0x1863, 0x002e, 0x000e, - 0x0005, 0xa182, 0x0085, 0x0002, 0x9795, 0x9793, 0x9793, 0x97a1, - 0x9793, 0x9793, 0x9793, 0x080c, 0x151a, 0x6003, 0x0001, 0x6106, - 0x080c, 0x6cff, 0x0126, 0x2091, 0x8000, 0x080c, 0x71e5, 0x012e, - 0x0005, 0x0026, 0x0056, 0x00d6, 0x00e6, 0x2071, 0xbc80, 0x7224, - 0x6212, 0x7220, 0x080c, 0x9d06, 0x01a0, 0x2268, 0x6800, 0xa086, - 0x0000, 0x0178, 0x6018, 0x6d18, 0xa52e, 0x1158, 0x00c6, 0x2d60, - 0x080c, 0x99d9, 0x00ce, 0x0128, 0x6803, 0x0002, 0x6007, 0x0086, - 0x0010, 0x6007, 0x0087, 0x6003, 0x0001, 0x080c, 0x6cff, 0x080c, - 0x71e5, 0x00f6, 0x2278, 0x080c, 0x5377, 0x00fe, 0x0150, 0x6820, - 0xd0ec, 0x0138, 0x00c6, 0x2260, 0x603f, 0x0000, 0x080c, 0x9ff1, - 0x00ce, 0x00ee, 0x00de, 0x005e, 0x002e, 0x0005, 0xa186, 0x0013, - 0x1160, 0x6004, 0xa08a, 0x0085, 0x0a0c, 0x151a, 0xa08a, 0x008c, - 0x1a0c, 0x151a, 0xa082, 0x0085, 0x0072, 0xa186, 0x0027, 0x0120, - 0xa186, 0x0014, 0x190c, 0x151a, 0x080c, 0x7102, 0x080c, 0x9ed9, - 0x080c, 0x71e5, 0x0005, 0x9802, 0x9804, 0x9804, 0x9802, 0x9802, - 0x9802, 0x9802, 0x080c, 0x151a, 0x080c, 0x7102, 0x080c, 0x9ed9, - 0x080c, 0x71e5, 0x0005, 0xa186, 0x0013, 0x1128, 0x6004, 0xa082, - 0x0085, 0x2008, 0x04a8, 0xa186, 0x0027, 0x11e8, 0x080c, 0x7102, - 0x080c, 0x2cd1, 0x00d6, 0x6010, 0x2068, 0x080c, 0x9d16, 0x0150, - 0x6837, 0x0103, 0x6847, 0x0000, 0x684b, 0x0029, 0x080c, 0x547a, - 0x080c, 0x9ecd, 0x00de, 0x080c, 0x86a4, 0x080c, 0x71e5, 0x0005, - 0x080c, 0x86ef, 0x0ce0, 0xa186, 0x0014, 0x1dd0, 0x080c, 0x7102, - 0x00d6, 0x6010, 0x2068, 0x080c, 0x9d16, 0x0d60, 0x6837, 0x0103, - 0x6847, 0x0000, 0x684b, 0x0006, 0x6850, 0xc0ec, 0x6852, 0x08f0, - 0x0002, 0x9852, 0x9850, 0x9850, 0x9850, 0x9850, 0x9850, 0x986a, - 0x080c, 0x151a, 0x080c, 0x7102, 0x6030, 0xa08c, 0xff00, 0x810f, - 0xa186, 0x0039, 0x0118, 0xa186, 0x0035, 0x1118, 0x2001, 0xb8b6, - 0x0010, 0x2001, 0xb8b7, 0x2004, 0x6016, 0x6003, 0x000c, 0x080c, - 0x71e5, 0x0005, 0x080c, 0x7102, 0x6030, 0xa08c, 0xff00, 0x810f, - 0xa186, 0x0039, 0x0118, 0xa186, 0x0035, 0x1118, 0x2001, 0xb8b6, - 0x0010, 0x2001, 0xb8b7, 0x2004, 0x6016, 0x6003, 0x000e, 0x080c, - 0x71e5, 0x0005, 0xa182, 0x008c, 0x1220, 0xa182, 0x0085, 0x0208, - 0x001a, 0x080c, 0x86ef, 0x0005, 0x9893, 0x9893, 0x9893, 0x9893, - 0x9895, 0x98ee, 0x9893, 0x080c, 0x151a, 0x00d6, 0x00f6, 0x2c78, - 0x080c, 0x5377, 0x00fe, 0x0168, 0x6030, 0xa08c, 0xff00, 0x810f, - 0xa186, 0x0039, 0x0118, 0xa186, 0x0035, 0x1118, 0x00de, 0x0804, - 0x9901, 0x080c, 0x9d16, 0x1118, 0x080c, 0x9ecd, 0x00f0, 0x6010, - 0x2068, 0x684c, 0xd0e4, 0x1110, 0x080c, 0x9ecd, 0x6837, 0x0103, - 0x6850, 0xd0b4, 0x0128, 0x684b, 0x0006, 0xc0ec, 0x6852, 0x0048, - 0xd0bc, 0x0118, 0x684b, 0x0002, 0x0020, 0x684b, 0x0005, 0x080c, - 0x9f8e, 0x6847, 0x0000, 0x080c, 0x547a, 0x2c68, 0x080c, 0x864e, - 0x01c0, 0x6003, 0x0001, 0x6007, 0x001e, 0x600b, 0xffff, 0x2009, - 0xbc8e, 0x210c, 0x6136, 0x2009, 0xbc8f, 0x210c, 0x613a, 0x6918, - 0x611a, 0x080c, 0xa0e3, 0x6950, 0x6152, 0x601f, 0x0001, 0x080c, - 0x6cff, 0x2d60, 0x080c, 0x86a4, 0x00de, 0x0005, 0x00f6, 0x2c78, - 0x080c, 0x5377, 0x00fe, 0x0598, 0x6030, 0xa08c, 0xff00, 0x810f, - 0xa186, 0x0035, 0x0130, 0xa186, 0x001e, 0x0118, 0xa186, 0x0039, - 0x1530, 0x00d6, 0x2c68, 0x080c, 0xa1c6, 0x1904, 0x9946, 0x080c, - 0x864e, 0x01d8, 0x6106, 0x6003, 0x0001, 0x601f, 0x0001, 0x6918, - 0x611a, 0x6928, 0x612a, 0x692c, 0x612e, 0x6930, 0xa18c, 0x00ff, - 0x6132, 0x6934, 0x6136, 0x6938, 0x613a, 0x6950, 0x6152, 0x080c, - 0xa0e3, 0x080c, 0x6cff, 0x080c, 0x71e5, 0x2d60, 0x00f8, 0x00d6, - 0x6010, 0x2068, 0x080c, 0x9d16, 0x01c8, 0x6837, 0x0103, 0x6850, - 0xd0b4, 0x0128, 0xc0ec, 0x6852, 0x684b, 0x0006, 0x0048, 0xd0bc, - 0x0118, 0x684b, 0x0002, 0x0020, 0x684b, 0x0005, 0x080c, 0x9f8e, - 0x6847, 0x0000, 0x080c, 0x547a, 0x080c, 0x9ecd, 0x00de, 0x080c, - 0x86a4, 0x0005, 0x0016, 0x00d6, 0x6010, 0x2068, 0x080c, 0x9d16, - 0x0140, 0x6837, 0x0103, 0x684b, 0x0028, 0x6847, 0x0000, 0x080c, - 0x547a, 0x00de, 0x001e, 0xa186, 0x0013, 0x0148, 0xa186, 0x0014, - 0x0130, 0xa186, 0x0027, 0x0118, 0x080c, 0x86ef, 0x0030, 0x080c, - 0x7102, 0x080c, 0x9ed9, 0x080c, 0x71e5, 0x0005, 0x0056, 0x0066, - 0x00d6, 0x00f6, 0x2029, 0x0001, 0xa182, 0x0101, 0x1208, 0x0010, - 0x2009, 0x0100, 0x2130, 0x2069, 0xbc98, 0x831c, 0x2300, 0xad18, - 0x2009, 0x0020, 0xaf90, 0x001d, 0x080c, 0x99c9, 0xa6b2, 0x0020, - 0x7804, 0xa06d, 0x0110, 0x080c, 0x1624, 0x080c, 0x15fd, 0x0500, - 0x8528, 0x6837, 0x0110, 0x683b, 0x0000, 0x2d20, 0x7c06, 0xa68a, - 0x003d, 0x1228, 0x2608, 0xad90, 0x000f, 0x0459, 0x0088, 0xa6b2, - 0x003c, 0x2009, 0x003c, 0x2d78, 0xad90, 0x000f, 0x0411, 0x0c28, - 0x00fe, 0x852f, 0xa5ad, 0x0003, 0x7d36, 0xa5ac, 0x0000, 0x0028, - 0x00fe, 0x852f, 0xa5ad, 0x0003, 0x7d36, 0x00de, 0x006e, 0x005e, - 0x0005, 0x00f6, 0x8dff, 0x0158, 0x6804, 0xa07d, 0x0130, 0x6807, - 0x0000, 0x080c, 0x547a, 0x2f68, 0x0cb8, 0x080c, 0x547a, 0x00fe, - 0x0005, 0x0156, 0xa184, 0x0001, 0x0108, 0x8108, 0x810c, 0x21a8, - 0x2304, 0x8007, 0x2012, 0x8318, 0x8210, 0x1f04, 0x99d0, 0x015e, - 0x0005, 0x0066, 0x0126, 0x2091, 0x8000, 0x2031, 0x0001, 0x601c, - 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0x080c, 0x6cff, 0x080c, 0x71e5, 0xa085, 0x0001, 0x0005, 0x080c, - 0x1952, 0x0c08, 0x00e6, 0x2071, 0xb8e1, 0x7024, 0xac06, 0x1110, - 0x080c, 0x7fe0, 0x601c, 0xa084, 0x000f, 0xa086, 0x0006, 0x1150, - 0x0086, 0x0096, 0x2049, 0x0001, 0x2c40, 0x080c, 0x81b7, 0x009e, - 0x008e, 0x0010, 0x080c, 0x7ed1, 0x00ee, 0x1928, 0x080c, 0x9a0b, - 0x0005, 0x0036, 0x00e6, 0x2071, 0xb8e1, 0x703c, 0xac06, 0x1140, - 0x2019, 0x0000, 0x080c, 0x806b, 0x00ee, 0x003e, 0x0804, 0x9a4b, - 0x080c, 0x82e4, 0x00ee, 0x003e, 0x1904, 0x9a4b, 0x080c, 0x9a0b, - 0x0005, 0x00c6, 0x601c, 0xa084, 0x000f, 0x0013, 0x00ce, 0x0005, - 0x9aba, 0x9b27, 0x9c75, 0x9ac5, 0x9ed9, 0x9aba, 0xad8e, 0xa20a, - 0x9b27, 0x9ab3, 0x9ce0, 0x080c, 0x151a, 0x080c, 0x9f14, 0x1110, - 0x080c, 0x8ca5, 0x0005, 0x080c, 0x7102, 0x080c, 0x71e5, 0x080c, - 0x86a4, 0x0005, 0x6017, 0x0001, 0x0005, 0x080c, 0x9d16, 0x0120, - 0x6010, 0xa080, 0x0019, 0x2c02, 0x6000, 0xa08a, 0x0010, 0x1a0c, - 0x151a, 0x000b, 0x0005, 0x9ae3, 0x9ae5, 0x9b05, 0x9b17, 0x9b24, - 0x9ae3, 0x9aba, 0x9aba, 0x9aba, 0x9b17, 0x9b17, 0x9ae3, 0x9ae3, - 0x9ae3, 0x9ae3, 0x9b21, 0x080c, 0x151a, 0x00e6, 0x6010, 0x2070, - 0x7050, 0xc0b5, 0x7052, 0x2071, 0xb8e1, 0x7024, 0xac06, 0x0190, - 0x080c, 0x7ed1, 0x6007, 0x0085, 0x6003, 0x000b, 0x601f, 0x0002, - 0x2001, 0xb8b7, 0x2004, 0x6016, 0x080c, 0x6cff, 0x080c, 0x71e5, - 0x00ee, 0x0005, 0x6017, 0x0001, 0x0cd8, 0x00d6, 0x6010, 0x2068, - 0x6850, 0xc0b5, 0x6852, 0x00de, 0x6007, 0x0085, 0x6003, 0x000b, - 0x601f, 0x0002, 0x080c, 0x6cff, 0x080c, 0x71e5, 0x0005, 0x00d6, - 0x6017, 0x0001, 0x6010, 0x2068, 0x6850, 0xc0b5, 0x6852, 0x00de, - 0x0005, 0x080c, 0x86a4, 0x0005, 0x080c, 0x1952, 0x08f0, 0x6000, - 0xa08a, 0x0010, 0x1a0c, 0x151a, 0x000b, 0x0005, 0x9b3e, 0x9ac2, - 0x9b40, 0x9b3e, 0x9b40, 0x9b40, 0x9abb, 0x9b3e, 0x9ab5, 0x9ab5, - 0x9b3e, 0x9b3e, 0x9b3e, 0x9b3e, 0x9b3e, 0x9b3e, 0x080c, 0x151a, - 0x00d6, 0x6018, 0x2068, 0x6804, 0xa084, 0x00ff, 0x00de, 0xa08a, - 0x000c, 0x1a0c, 0x151a, 0x000b, 0x0005, 0x9b59, 0x9c1b, 0x9b5b, - 0x9b99, 0x9b5b, 0x9b99, 0x9b5b, 0x9b69, 0x9b59, 0x9b99, 0x9b59, - 0x9b85, 0x080c, 0x151a, 0x6004, 0xa08e, 0x0016, 0x05a8, 0xa08e, - 0x0004, 0x0590, 0xa08e, 0x0002, 0x0578, 0xa08e, 0x004b, 0x0904, - 0x9c17, 0x6004, 0x080c, 0x9f14, 0x0904, 0x9c34, 0xa08e, 0x0021, - 0x0904, 0x9c38, 0xa08e, 0x0022, 0x0904, 0x9c34, 0xa08e, 0x003d, - 0x0904, 0x9c38, 0xa08e, 0x0039, 0x0904, 0x9c3c, 0xa08e, 0x0035, - 0x0904, 0x9c3c, 0xa08e, 0x001e, 0x0188, 0xa08e, 0x0001, 0x1150, - 0x00d6, 0x6018, 0x2068, 0x6804, 0xa084, 0x00ff, 0x00de, 0xa086, - 0x0006, 0x0110, 0x080c, 0x2cd1, 0x080c, 0x8ca5, 0x080c, 0x9ed9, - 0x0005, 0x00c6, 0x00d6, 0x6104, 0xa186, 0x0016, 0x0904, 0x9c08, - 0xa186, 0x0002, 0x15d8, 0x2001, 0xb635, 0x2004, 0xd08c, 0x1198, - 0x080c, 0x5b41, 0x1180, 0x2001, 0xb89f, 0x2003, 0x0001, 0x2001, - 0xb600, 0x2003, 0x0001, 0xa085, 0x0001, 0x080c, 0x5b85, 0x080c, - 0x5a79, 0x0804, 0x9c5e, 0x6018, 0x2068, 0x2001, 0xb635, 0x2004, - 0xd0ac, 0x1904, 0x9c5e, 0x68a0, 0xd0bc, 0x1904, 0x9c5e, 0x6840, - 0xa084, 0x00ff, 0xa005, 0x0190, 0x8001, 0x6842, 0x6013, 0x0000, - 0x601f, 0x0007, 0x6017, 0x0398, 0x603f, 0x0000, 0x080c, 0x864e, - 0x0128, 0x2d00, 0x601a, 0x601f, 0x0001, 0x0450, 0x00de, 0x00ce, - 0x6004, 0xa08e, 0x0002, 0x11a8, 0x6018, 0xa080, 0x0028, 0x2004, - 0xa086, 0x007e, 0x1170, 0x2009, 0xb635, 0x2104, 0xc085, 0x200a, - 0x00e6, 0x2071, 0xb600, 0x080c, 0x4c28, 0x00ee, 0x080c, 0x8ca5, - 0x0020, 0x080c, 0x8ca5, 0x080c, 0x2cd1, 0x00e6, 0x0126, 0x2091, - 0x8000, 0x080c, 0x2cf7, 0x012e, 0x00ee, 0x080c, 0x9ed9, 0x0005, - 0x2001, 0x0002, 0x080c, 0x4f6f, 0x6003, 0x0001, 0x6007, 0x0002, - 0x080c, 0x6d45, 0x080c, 0x71e5, 0x00de, 0x00ce, 0x0c80, 0x080c, - 0x2cf7, 0x0804, 0x9b94, 0x00c6, 0x00d6, 0x6104, 0xa186, 0x0016, - 0x0d38, 0x6018, 0x2068, 0x6840, 0xa084, 0x00ff, 0xa005, 0x0904, - 0x9bde, 0x8001, 0x6842, 0x6003, 0x0001, 0x080c, 0x6d45, 0x080c, - 0x71e5, 0x00de, 0x00ce, 0x0898, 0x080c, 0x8ca5, 0x0804, 0x9b96, - 0x080c, 0x8cd3, 0x0804, 0x9b96, 0x00d6, 0x2c68, 0x6104, 0x080c, - 0xa1c6, 0x00de, 0x0118, 0x080c, 0x86a4, 0x00b8, 0x6004, 0x8007, - 0x6130, 0xa18c, 0x00ff, 0xa105, 0x6032, 0x6007, 0x0085, 0x6003, - 0x000b, 0x601f, 0x0002, 0x6038, 0x600a, 0x2001, 0xb8b7, 0x2004, - 0x6016, 0x080c, 0x6cff, 0x080c, 0x71e5, 0x0005, 0x00de, 0x00ce, - 0x080c, 0x8ca5, 0x080c, 0x2cd1, 0x00e6, 0x0126, 0x2091, 0x8000, - 0x080c, 0x2cf7, 0x6013, 0x0000, 0x601f, 0x0007, 0x6017, 0x0398, - 0x603f, 0x0000, 0x012e, 0x00ee, 0x0005, 0x6000, 0xa08a, 0x0010, - 0x1a0c, 0x151a, 0x000b, 0x0005, 0x9c8c, 0x9c8c, 0x9c8c, 0x9c8c, - 0x9c8c, 0x9c8c, 0x9c8c, 0x9c8c, 0x9c8c, 0x9aba, 0x9c8c, 0x9ac2, - 0x9c8e, 0x9ac2, 0x9c9b, 0x9c8c, 0x080c, 0x151a, 0x6004, 0xa086, - 0x008b, 0x0148, 0x6007, 0x008b, 0x6003, 0x000d, 0x080c, 0x6cff, - 0x080c, 0x71e5, 0x0005, 0x080c, 0x9ecd, 0x080c, 0x9d16, 0x0580, - 0x080c, 0x2cd1, 0x00d6, 0x080c, 0x9d16, 0x0168, 0x6010, 0x2068, - 0x6837, 0x0103, 0x684b, 0x0006, 0x6847, 0x0000, 0x6850, 0xc0ed, - 0x6852, 0x080c, 0x547a, 0x2c68, 0x080c, 0x864e, 0x0150, 0x6818, - 0x601a, 0x080c, 0xa0e3, 0x00c6, 0x2d60, 0x080c, 0x9ed9, 0x00ce, - 0x0008, 0x2d60, 0x00de, 0x6013, 0x0000, 0x601f, 0x0001, 0x6007, - 0x0001, 0x6003, 0x0001, 0x080c, 0x6d45, 0x080c, 0x71e5, 0x0078, - 0x6030, 0xa08c, 0xff00, 0x810f, 0xa186, 0x0039, 0x0118, 0xa186, - 0x0035, 0x1118, 0x080c, 0x2cd1, 0x08b0, 0x080c, 0x9ed9, 0x0005, - 0x6000, 0xa08a, 0x0010, 0x1a0c, 0x151a, 0x000b, 0x0005, 0x9cf7, - 0x9cf7, 0x9cf7, 0x9cf9, 0x9cf9, 0x9cf7, 0x9cf7, 0x9cf7, 0x9cf7, - 0x9cf7, 0x9cf7, 0x9cf7, 0x9cf7, 0x9cf7, 0x9cf7, 0x9cf7, 0x080c, - 0x151a, 0x080c, 0x82e4, 0x190c, 0x151a, 0x6110, 0x2168, 0x684b, - 0x0006, 0x080c, 0x547a, 0x080c, 0x86a4, 0x0005, 0xa284, 0x0007, - 0x1158, 0xa282, 0xbe00, 0x0240, 0x2001, 0xb617, 0x2004, 0xa202, - 0x1218, 0xa085, 0x0001, 0x0005, 0xa006, 0x0ce8, 0x0026, 0x6210, - 0xa294, 0xf000, 0x002e, 0x0005, 0x00e6, 0x00c6, 0x0036, 0x0006, - 0x0126, 0x2091, 0x8000, 0x2061, 0xbe00, 0x2071, 0xb600, 0x7348, - 0x7068, 0xa302, 0x12a8, 0x601c, 0xa206, 0x1160, 0x080c, 0xa06e, - 0x0148, 0x080c, 0x9f14, 0x1110, 0x080c, 0x8ca5, 0x00c6, 0x080c, - 0x86a4, 0x00ce, 0xace0, 0x0018, 0x705c, 0xac02, 0x1208, 0x0c38, - 0x012e, 0x000e, 0x003e, 0x00ce, 0x00ee, 0x0005, 0x00e6, 0x00c6, - 0x0016, 0xa188, 0xb735, 0x210c, 0x81ff, 0x0128, 0x2061, 0xb9f5, - 0x611a, 0x080c, 0x2cd1, 0xa006, 0x0010, 0xa085, 0x0001, 0x001e, - 0x00ce, 0x00ee, 0x0005, 0x00c6, 0x0056, 0x0126, 0x2091, 0x8000, - 0x00c6, 0x080c, 0x864e, 0x005e, 0x0180, 0x6612, 0x651a, 0x080c, - 0xa0e3, 0x601f, 0x0003, 0x2009, 0x004b, 0x080c, 0x86d3, 0xa085, - 0x0001, 0x012e, 0x005e, 0x00ce, 0x0005, 0xa006, 0x0cd0, 0x00c6, - 0x0056, 0x0126, 0x2091, 0x8000, 0x62a0, 0x00c6, 0x080c, 0x9f92, - 0x005e, 0x0550, 0x6013, 0x0000, 0x651a, 0x080c, 0xa0e3, 0x601f, - 0x0003, 0x0016, 0x00c6, 0x2560, 0x080c, 0x521c, 0x00ce, 0x080c, - 0x6e67, 0x0076, 0x2039, 0x0000, 0x080c, 0x6d74, 0x2c08, 0x080c, - 0xaf3e, 0x007e, 0x001e, 0xd184, 0x0128, 0x080c, 0x86a4, 0xa085, - 0x0001, 0x0030, 0x2009, 0x004c, 0x080c, 0x86d3, 0xa085, 0x0001, - 0x012e, 0x005e, 0x00ce, 0x0005, 0xa006, 0x0cd0, 0x00f6, 0x00c6, - 0x0046, 0x00c6, 0x080c, 0x864e, 0x2c78, 0x00ce, 0x0180, 0x7e12, - 0x2c00, 0x781a, 0x781f, 0x0003, 0x2021, 0x0005, 0x080c, 0x9e0c, - 0x2f60, 0x2009, 0x004d, 0x080c, 0x86d3, 0xa085, 0x0001, 0x004e, - 0x00ce, 0x00fe, 0x0005, 0x00f6, 0x00c6, 0x0046, 0x00c6, 0x080c, - 0x864e, 0x2c78, 0x00ce, 0x0178, 0x7e12, 0x2c00, 0x781a, 0x781f, - 0x0003, 0x2021, 0x0005, 0x0481, 0x2f60, 0x2009, 0x004e, 0x080c, - 0x86d3, 0xa085, 0x0001, 0x004e, 0x00ce, 0x00fe, 0x0005, 0x00f6, - 0x00c6, 0x0046, 0x00c6, 0x080c, 0x864e, 0x2c78, 0x00ce, 0x01c0, - 0x7e12, 0x2c00, 0x781a, 0x781f, 0x0003, 0x2021, 0x0004, 0x00a1, - 0x2001, 0xb8a0, 0x2004, 0xd0fc, 0x0120, 0x2f60, 0x080c, 0x86a4, - 0x0028, 0x2f60, 0x2009, 0x0052, 0x080c, 0x86d3, 0xa085, 0x0001, - 0x004e, 0x00ce, 0x00fe, 0x0005, 0x0096, 0x0076, 0x0126, 0x2091, - 0x8000, 0x080c, 0x51be, 0x0118, 0x2001, 0x9e11, 0x0028, 0x080c, - 0x518e, 0x0158, 0x2001, 0x9e17, 0x0006, 0xa00e, 0x2400, 0x080c, - 0x554d, 0x080c, 0x547a, 0x000e, 0x0807, 0x2418, 0x080c, 0x70a1, - 0x62a0, 0x0086, 0x2041, 0x0001, 0x2039, 0x0001, 0x2608, 0x080c, - 0x6e80, 0x008e, 0x080c, 0x6d74, 0x2f08, 0x2648, 0x080c, 0xaf3e, - 0x613c, 0x81ff, 0x090c, 0x6f35, 0x080c, 0x71e5, 0x012e, 0x007e, - 0x009e, 0x0005, 0x00c6, 0x0126, 0x2091, 0x8000, 0x00c6, 0x080c, - 0x864e, 0x001e, 0x0188, 0x660a, 0x611a, 0x080c, 0xa0e3, 0x601f, - 0x0001, 0x2d00, 0x6012, 0x2009, 0x001f, 0x080c, 0x86d3, 0xa085, - 0x0001, 0x012e, 0x00ce, 0x0005, 0xa006, 0x0cd8, 0x00c6, 0x0126, - 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0x080c, 0x15fd, 0x003e, 0x090c, 0x151a, 0x6837, 0x010d, 0x6803, - 0x0000, 0x683b, 0x0000, 0x685b, 0x0000, 0x6b5e, 0x6857, 0x0045, - 0x2c00, 0x6862, 0x6034, 0x6872, 0x2360, 0x6020, 0xc0dd, 0x6022, - 0x6018, 0xa080, 0x0028, 0x2004, 0xa084, 0x00ff, 0x8007, 0x6350, - 0x6b4a, 0x6846, 0x684f, 0x0000, 0x6853, 0x0000, 0x6d6a, 0x6e66, - 0x686f, 0x0001, 0x080c, 0x547a, 0x2019, 0x0045, 0x6008, 0x2068, - 0x080c, 0xad9c, 0x2d00, 0x600a, 0x601f, 0x0006, 0x6003, 0x0007, - 0x6017, 0x0000, 0x603f, 0x0000, 0x00de, 0x003e, 0x0038, 0x603f, - 0x0000, 0x6003, 0x0007, 0x080c, 0xac12, 0x00ce, 0x00de, 0x0005, - 0xa186, 0x0013, 0x1128, 0x6004, 0xa082, 0x0085, 0x2008, 0x00c2, - 0xa186, 0x0027, 0x1178, 0x080c, 0x7102, 0x0036, 0x00d6, 0x6010, - 0x2068, 0x2019, 0x0004, 0x080c, 0xb155, 0x00de, 0x003e, 0x080c, - 0x71e5, 0x0005, 0xa186, 0x0014, 0x0d70, 0x080c, 0x86ef, 0x0005, - 0xb351, 0xb34f, 0xb34f, 0xb34f, 0xb34f, 0xb34f, 0xb351, 0x080c, - 0x151a, 0x080c, 0x7102, 0x6003, 0x000c, 0x080c, 0x71e5, 0x0005, - 0xa182, 0x008c, 0x1220, 0xa182, 0x0085, 0x0208, 0x001a, 0x080c, - 0x86ef, 0x0005, 0xb369, 0xb369, 0xb369, 0xb369, 0xb36b, 0xb389, - 0xb369, 0x080c, 0x151a, 0x00d6, 0x2c68, 0x080c, 0x864e, 0x01a0, - 0x6003, 0x0001, 0x6007, 0x001e, 0x2009, 0xbc8e, 0x210c, 0x6136, - 0x2009, 0xbc8f, 0x210c, 0x613a, 0x600b, 0xffff, 0x6918, 0x611a, - 0x601f, 0x0004, 0x080c, 0x6cff, 0x2d60, 0x080c, 0x86a4, 0x00de, - 0x0005, 0x080c, 0x86a4, 0x0005, 0x00e6, 0x6018, 0x2070, 0x7000, - 0xd0ec, 0x00ee, 0x0005, 0x6010, 0xa08c, 0xf000, 0x0904, 0xb3d7, - 0xa080, 0x0013, 0x200c, 0xd1ec, 0x05d0, 0x2001, 0xb672, 0x2004, - 0xd0ec, 0x05a8, 0x6003, 0x0002, 0x6020, 0xc0e5, 0x6022, 0xd1ac, - 0x0180, 0x00f6, 0x2c78, 0x080c, 0x5373, 0x00fe, 0x0150, 0x2001, - 0xb8b8, 0x2004, 0x603e, 0x2009, 0xb672, 0x210c, 0xd1f4, 0x11e8, - 0x0080, 0x2009, 0xb672, 0x210c, 0xd1f4, 0x0128, 0x6020, 0xc0e4, - 0x6022, 0xa006, 0x00a0, 0x2001, 0xb8b8, 0x200c, 0x8103, 0xa100, - 0x603e, 0x6018, 0xa088, 0x002b, 0x2104, 0xa005, 0x0118, 0xa088, - 0x0003, 0x0cd0, 0x2c0a, 0x600f, 0x0000, 0xa085, 0x0001, 0x0005, - 0x0016, 0x00c6, 0x00e6, 0x6150, 0xa2f0, 0x002b, 0x2e04, 0x2060, - 0x8cff, 0x0180, 0x84ff, 0x1118, 0x6050, 0xa106, 0x1138, 0x600c, - 0x2072, 0x080c, 0x6b61, 0x080c, 0x86a4, 0x0010, 0xacf0, 0x0003, - 0x2e64, 0x0c70, 0x00ee, 0x00ce, 0x001e, 0x0005, 0x00d6, 0x6018, - 0xa0e8, 0x002b, 0x2d04, 0xa005, 0x0140, 0xac06, 0x0120, 0x2d04, - 0xa0e8, 0x0003, 0x0cb8, 0x600c, 0x206a, 0x00de, 0x0005, 0x0026, - 0x0036, 0x0156, 0x2011, 0xb628, 0x2204, 0xa084, 0x00ff, 0x2019, - 0xbc8e, 0x2334, 0xa636, 0x11d8, 0x8318, 0x2334, 0x2204, 0xa084, - 0xff00, 0xa636, 0x11a0, 0x2011, 0xbc90, 0x6018, 0xa098, 0x000a, - 0x20a9, 0x0004, 0x080c, 0x9166, 0x1150, 0x2011, 0xbc94, 0x6018, - 0xa098, 0x0006, 0x20a9, 0x0004, 0x080c, 0x9166, 0x1100, 0x015e, - 0x003e, 0x002e, 0x0005, 0x00e6, 0x2071, 0xb600, 0x080c, 0x4c28, - 0x080c, 0x2aed, 0x00ee, 0x0005, 0x00e6, 0x6018, 0x2070, 0x7000, - 0xd0fc, 0x0108, 0x0011, 0x00ee, 0x0005, 0x6850, 0xc0e5, 0x6852, - 0x0005, 0x00e6, 0x00c6, 0x0076, 0x0066, 0x0056, 0x0046, 0x0026, - 0x0016, 0x0126, 0x2091, 0x8000, 0x2029, 0xb8ea, 0x252c, 0x2021, - 0xb8f0, 0x2424, 0x2061, 0xbe00, 0x2071, 0xb600, 0x7648, 0x7068, - 0xa606, 0x0578, 0x671c, 0xa786, 0x0001, 0x0118, 0xa786, 0x0008, - 0x1500, 0x2500, 0xac06, 0x01e8, 0x2400, 0xac06, 0x01d0, 0x080c, - 0xb1cc, 0x01b8, 0x080c, 0xb1dc, 0x11a0, 0x6000, 0xa086, 0x0004, - 0x1120, 0x0016, 0x080c, 0x1952, 0x001e, 0x080c, 0x9f03, 0x1110, - 0x080c, 0x2cf7, 0x080c, 0x9f14, 0x1110, 0x080c, 0x8ca5, 0x080c, - 0x9ed9, 0xace0, 0x0018, 0x2001, 0xb617, 0x2004, 0xac02, 0x1208, - 0x0858, 0x012e, 0x001e, 0x002e, 0x004e, 0x005e, 0x006e, 0x007e, - 0x00ce, 0x00ee, 0x0005, 0x0126, 0x0006, 0x00e6, 0x0016, 0x2091, - 0x8000, 0x2071, 0xb640, 0xd5a4, 0x0118, 0x7034, 0x8000, 0x7036, - 0xd5b4, 0x0118, 0x7030, 0x8000, 0x7032, 0xd5ac, 0x0178, 0x2500, - 0xa084, 0x0007, 0xa08e, 0x0003, 0x0148, 0xa08e, 0x0004, 0x0130, - 0xa08e, 0x0005, 0x0118, 0x2071, 0xb64a, 0x04c9, 0x001e, 0x00ee, - 0x000e, 0x012e, 0x0005, 0x0126, 0x0006, 0x00e6, 0x0016, 0x2091, - 0x8000, 0x2071, 0xb640, 0xd5a4, 0x0118, 0x7034, 0x8000, 0x7036, - 0xd5b4, 0x0118, 0x7030, 0x8000, 0x7032, 0xd5ac, 0x0178, 0x2500, - 0xa084, 0x0007, 0xa08e, 0x0003, 0x0148, 0xa08e, 0x0004, 0x0130, - 0xa08e, 0x0005, 0x0118, 0x2071, 0xb64a, 0x0089, 0x001e, 0x00ee, - 0x000e, 0x012e, 0x0005, 0x0126, 0x0006, 0x00e6, 0x2091, 0x8000, - 0x2071, 0xb642, 0x0021, 0x00ee, 0x000e, 0x012e, 0x0005, 0x2e04, - 0x8000, 0x2072, 0x1220, 0x8e70, 0x2e04, 0x8000, 0x2072, 0x0005, - 0x00e6, 0x2071, 0xb640, 0x0c99, 0x00ee, 0x0005, 0x00e6, 0x2071, - 0xb644, 0x0c69, 0x00ee, 0x0005, 0x0126, 0x0006, 0x00e6, 0x2091, - 0x8000, 0x2071, 0xb640, 0x7044, 0x8000, 0x7046, 0x00ee, 0x000e, - 0x012e, 0x0005, 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, - 0x0040, 0x0080, 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, - 0x4000, 0x8000, 0xdb06 -}; diff --git a/sys/dev/ispfw/asm_2300.h b/sys/dev/ispfw/asm_2300.h deleted file mode 100644 index 1dc2061ebd8..00000000000 --- a/sys/dev/ispfw/asm_2300.h +++ /dev/null @@ -1,7869 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-3-Clause - * - * Copyright (C) 2001, 2002, 2003, 2004, 2005 by Qlogic, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms are permitted provided - * that the following conditions are met: - * 1. Redistribution of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistribution in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/************************************************************************ - * * - * --- ISP2300 Initiator/Target Firmware --- * - * with Fabric (Public Loop), Point-point, * - * expanded LUN addressing for FCTAPE, and 2K port logins * - * * - ************************************************************************/ -/* - * Firmware Version 3.03.28 - */ -static const uint16_t isp_2300_risc_code[] = { - 0x0470, 0x0000, 0x0000, 0xf4a2, 0x0000, 0x0003, 0x0003, 0x001c, - 0x0137, 0x2043, 0x4f50, 0x5952, 0x4947, 0x4854, 0x2032, 0x3030, - 0x3120, 0x514c, 0x4f47, 0x4943, 0x2043, 0x4f52, 0x504f, 0x5241, - 0x5449, 0x4f4e, 0x2049, 0x5350, 0x3233, 0x3030, 0x2046, 0x6972, - 0x6d77, 0x6172, 0x6520, 0x2056, 0x6572, 0x7369, 0x6f6e, 0x2030, - 0x332e, 0x3033, 0x2e32, 0x3820, 0x2020, 0x2020, 0x2400, 0x20a9, - 0x000f, 0x2001, 0x0000, 0x400f, 0x2091, 0x2200, 0x20a9, 0x000f, - 0x2001, 0x0000, 0x400f, 0x2091, 0x2400, 0x20a9, 0x000f, 0x2001, - 0x0000, 0x400f, 0x2091, 0x2600, 0x20a9, 0x000f, 0x2001, 0x0000, - 0x400f, 0x2091, 0x2800, 0x20a9, 0x000f, 0x2001, 0x0000, 0x400f, - 0x2091, 0x2a00, 0x20a9, 0x000f, 0x2001, 0x0000, 0x400f, 0x2091, - 0x2c00, 0x20a9, 0x000f, 0x2001, 0x0000, 0x400f, 0x2091, 0x2e00, - 0x20a9, 0x000f, 0x2001, 0x0000, 0x400f, 0x2091, 0x2000, 0x2001, - 0x0000, 0x20c1, 0x0004, 0x20c9, 0x1bff, 0x2059, 0x0000, 0x2b78, - 0x7883, 0x0004, 0x2089, 0x2e49, 0x2051, 0x1800, 0x2a70, 0x20e1, - 0x0001, 0x20e9, 0x0001, 0x2009, 0x0000, 0x080c, 0x0e5a, 0x2029, - 0x4d00, 0x2031, 0xffff, 0x2039, 0x4cd0, 0x2021, 0x0200, 0x20e9, - 0x0001, 0x20a1, 0x0000, 0x20a9, 0x0800, 0x900e, 0x4104, 0x20e9, - 0x0001, 0x20a1, 0x1000, 0x900e, 0x2001, 0x0cc0, 0x9084, 0x0fff, - 0x20a8, 0x4104, 0x2001, 0x0000, 0x9086, 0x0000, 0x0120, 0x21a8, - 0x4104, 0x8001, 0x1de0, 0x756e, 0x7672, 0x776a, 0x7476, 0x747a, - 0x00e6, 0x2071, 0x1ad4, 0x2472, 0x00ee, 0x20a1, 0x1cd0, 0x7170, - 0x810d, 0x810d, 0x810d, 0x810d, 0x918c, 0x000f, 0x2001, 0x0001, - 0x9112, 0x900e, 0x21a8, 0x4104, 0x8211, 0x1de0, 0x7170, 0x3400, - 0x8001, 0x9102, 0x0120, 0x0218, 0x20a8, 0x900e, 0x4104, 0x2009, - 0x1800, 0x810d, 0x810d, 0x810d, 0x810d, 0x810d, 0x918c, 0x001f, - 0x2001, 0x0001, 0x9112, 0x20e9, 0x0001, 0x20a1, 0x0800, 0x900e, - 0x20a9, 0x0800, 0x4104, 0x8211, 0x1dd8, 0x080c, 0x0f2e, 0x080c, - 0x62c2, 0x080c, 0xb4d2, 0x080c, 0x10f9, 0x080c, 0x131b, 0x080c, - 0x1c33, 0x080c, 0x0d5e, 0x080c, 0x106a, 0x080c, 0x3571, 0x080c, - 0x7b0e, 0x080c, 0x6d4b, 0x080c, 0x8cdb, 0x080c, 0x8972, 0x080c, - 0x2515, 0x080c, 0x95d8, 0x080c, 0x822e, 0x080c, 0x2346, 0x080c, - 0x247a, 0x080c, 0x250a, 0x2091, 0x3009, 0x7883, 0x0000, 0x1004, - 0x091f, 0x7880, 0x9086, 0x0002, 0x1190, 0x7883, 0x4000, 0x7837, - 0x4000, 0x7833, 0x0010, 0x0e04, 0x0913, 0x2091, 0x5000, 0x2091, - 0x4080, 0x2001, 0x0089, 0x2004, 0xd084, 0x190c, 0x11c6, 0x2071, - 0x1800, 0x7003, 0x0000, 0x2071, 0x1800, 0x7000, 0x908e, 0x0003, - 0x1178, 0x080c, 0x4e84, 0x080c, 0x3598, 0x080c, 0x7b7f, 0x080c, - 0x72ed, 0x080c, 0x8dc2, 0x080c, 0x899e, 0x080c, 0x2d52, 0x0c58, - 0x000b, 0x0c78, 0x0944, 0x0945, 0x0ae2, 0x0942, 0x0ba7, 0x0d5d, - 0x0d5d, 0x0d5d, 0x080c, 0x0dcc, 0x0005, 0x0126, 0x00f6, 0x2091, - 0x8000, 0x7000, 0x9086, 0x0001, 0x1904, 0x0ab3, 0x080c, 0x0e9c, - 0x080c, 0x77ff, 0x0150, 0x080c, 0x7822, 0x15b0, 0x2079, 0x0100, - 0x7828, 0x9085, 0x1800, 0x782a, 0x0478, 0x080c, 0x772c, 0x7000, - 0x9086, 0x0001, 0x1904, 0x0ab3, 0x7098, 0x9086, 0x0029, 0x1904, - 0x0ab3, 0x080c, 0x8952, 0x080c, 0x8944, 0x2079, 0x0100, 0x782f, - 0x0008, 0x2001, 0x0161, 0x2003, 0x0001, 0x7827, 0xffff, 0x7a28, - 0x9295, 0x5e2f, 0x7a2a, 0x2011, 0x767b, 0x080c, 0x8a65, 0x2011, - 0x766e, 0x080c, 0x8b89, 0x2011, 0x611b, 0x080c, 0x8a65, 0x2011, - 0x8030, 0x901e, 0x7396, 0x04c0, 0x080c, 0x59bf, 0x2079, 0x0100, - 0x7844, 0x9005, 0x1904, 0x0ab3, 0x2011, 0x611b, 0x080c, 0x8a65, - 0x2011, 0x767b, 0x080c, 0x8a65, 0x2011, 0x766e, 0x080c, 0x8b89, - 0x2001, 0x0205, 0x2003, 0x0000, 0x7840, 0x9084, 0xfffb, 0x7842, - 0x2001, 0x19aa, 0x2004, 0x9005, 0x1140, 0x00c6, 0x2061, 0x0100, - 0x080c, 0x626a, 0x00ce, 0x0804, 0x0ab3, 0x780f, 0x006b, 0x7a28, - 0x080c, 0x7807, 0x0118, 0x9295, 0x5e2f, 0x0010, 0x9295, 0x402f, - 0x7a2a, 0x2011, 0x8010, 0x73d8, 0x2001, 0x19ab, 0x2003, 0x0001, - 0x080c, 0x2bf7, 0x080c, 0x4dbf, 0x7248, 0xc284, 0x724a, 0x2001, - 0x180c, 0x200c, 0xc1ac, 0xc1cc, 0x2102, 0x080c, 0xabfd, 0x2011, - 0x0004, 0x080c, 0xd404, 0x080c, 0x6aef, 0x080c, 0x77ff, 0x1120, - 0x080c, 0x2c3b, 0x02e0, 0x0400, 0x080c, 0x6271, 0x0140, 0x7097, - 0x0001, 0x70d3, 0x0000, 0x080c, 0x5b91, 0x0804, 0x0ab3, 0x080c, - 0x595f, 0xd094, 0x0188, 0x2011, 0x180c, 0x2204, 0xc0cd, 0x2012, - 0x080c, 0x5963, 0xd0d4, 0x1118, 0x080c, 0x2c3b, 0x1270, 0x2011, - 0x180c, 0x2204, 0xc0bc, 0x00a8, 0x080c, 0x5963, 0xd0d4, 0x1db8, - 0x2011, 0x180c, 0x2204, 0xc0bd, 0x0060, 0x2011, 0x180c, 0x2204, - 0xc0bd, 0x2012, 0x080c, 0x6c53, 0x1128, 0xd0a4, 0x0118, 0x2204, - 0xc0fd, 0x2012, 0x080c, 0x6c19, 0x0120, 0x7a0c, 0xc2b4, 0x7a0e, - 0x00a8, 0x707f, 0x0000, 0x080c, 0x77ff, 0x1130, 0x70b0, 0x9005, - 0x1168, 0x080c, 0xd855, 0x0050, 0x080c, 0xd855, 0x70dc, 0xd09c, - 0x1128, 0x70b0, 0x9005, 0x0110, 0x080c, 0x6247, 0x70e7, 0x0000, - 0x70e3, 0x0000, 0x70a7, 0x0000, 0x080c, 0x2c43, 0x0228, 0x2011, - 0x0101, 0x2204, 0xc0c4, 0x2012, 0x72dc, 0x080c, 0x77ff, 0x1178, - 0x9016, 0x0016, 0x080c, 0x2a00, 0x2019, 0x1970, 0x211a, 0x001e, - 0x705f, 0xffff, 0x7063, 0x00ef, 0x7083, 0x0000, 0x0020, 0x2019, - 0x1970, 0x201b, 0x0000, 0x2079, 0x184a, 0x7804, 0xd0ac, 0x0108, - 0xc295, 0x72de, 0x080c, 0x77ff, 0x0118, 0x9296, 0x0004, 0x0548, - 0x2011, 0x0001, 0x080c, 0xd404, 0x70ab, 0x0000, 0x70af, 0xffff, - 0x7003, 0x0002, 0x2079, 0x0100, 0x7827, 0x0003, 0x7828, 0x9085, - 0x0003, 0x782a, 0x00fe, 0x080c, 0x30b6, 0x2011, 0x0005, 0x080c, - 0xad0c, 0x080c, 0x9ce8, 0x080c, 0x77ff, 0x0148, 0x00c6, 0x2061, - 0x0100, 0x0016, 0x080c, 0x2a00, 0x61e2, 0x001e, 0x00ce, 0x012e, - 0x0420, 0x70ab, 0x0000, 0x70af, 0xffff, 0x7003, 0x0002, 0x00f6, - 0x2079, 0x0100, 0x7827, 0x0003, 0x7828, 0x9085, 0x0003, 0x782a, - 0x00fe, 0x2011, 0x0005, 0x080c, 0xad0c, 0x080c, 0x9ce8, 0x080c, - 0x77ff, 0x0148, 0x00c6, 0x2061, 0x0100, 0x0016, 0x080c, 0x2a00, - 0x61e2, 0x001e, 0x00ce, 0x00fe, 0x012e, 0x0005, 0x00c6, 0x00f6, - 0x00b6, 0x080c, 0x77ff, 0x1118, 0x20a9, 0x0800, 0x0010, 0x20a9, - 0x0782, 0x080c, 0x77ff, 0x1110, 0x900e, 0x0010, 0x2009, 0x007e, - 0x86ff, 0x0138, 0x9180, 0x1000, 0x2004, 0x905d, 0x0110, 0xb800, - 0xd0bc, 0x090c, 0x3407, 0x8108, 0x1f04, 0x0ac8, 0x707f, 0x0000, - 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0x0006, 0x0126, 0x01c6, 0x01d6, 0x0136, 0x0146, 0x0156, 0x080c, - 0x29eb, 0x080c, 0x251e, 0x080c, 0x13b5, 0x080c, 0x2365, 0x0804, - 0x30ad, 0x0106, 0x0006, 0x0126, 0x01c6, 0x01d6, 0x0136, 0x0146, - 0x0156, 0x080c, 0x29eb, 0x080c, 0x232a, 0x080c, 0x251e, 0x080c, - 0x13b5, 0x0498, 0x0106, 0x0006, 0x0126, 0x01c6, 0x01d6, 0x0136, - 0x0146, 0x0156, 0x080c, 0x29eb, 0x080c, 0x232a, 0x080c, 0x13b5, - 0x080c, 0x2365, 0x0410, 0x0106, 0x0006, 0x0126, 0x01c6, 0x01d6, - 0x0136, 0x0146, 0x0156, 0x080c, 0x29eb, 0x080c, 0x13b5, 0x080c, - 0x2365, 0x0098, 0x0106, 0x0006, 0x0126, 0x01c6, 0x01d6, 0x0136, - 0x0146, 0x0156, 0x080c, 0x29eb, 0x080c, 0x232a, 0x080c, 0x251e, - 0x080c, 0x13b5, 0x080c, 0x2365, 0x0000, 0x015e, 0x014e, 0x013e, - 0x01de, 0x01ce, 0x012e, 0x000e, 0x010e, 0x000d, 0x00b6, 0x00c6, - 0x0026, 0x0046, 0x9026, 0x080c, 0x6c19, 0x1904, 0x31ed, 0x72dc, - 0x2001, 0x197f, 0x2004, 0x9005, 0x1110, 0xd29c, 0x0148, 0xd284, - 0x1138, 0xd2bc, 0x1904, 0x31ed, 0x080c, 0x31f2, 0x0804, 0x31ed, - 0xd2cc, 0x1904, 0x31ed, 0x080c, 0x77ff, 0x1120, 0x70af, 0xffff, - 0x0804, 0x31ed, 0xd294, 0x0120, 0x70af, 0xffff, 0x0804, 0x31ed, - 0x080c, 0x3460, 0x0160, 0x080c, 0xdb0c, 0x0128, 0x2001, 0x1818, - 0x203c, 0x0804, 0x3166, 0x70af, 0xffff, 0x0804, 0x31ed, 0x2001, - 0x1818, 0x203c, 0x7294, 0xd284, 0x0904, 0x3166, 0xd28c, 0x1904, - 0x3166, 0x0036, 0x73ac, 0x938e, 0xffff, 0x1110, 0x2019, 0x0001, - 0x8314, 0x92e0, 0x1c80, 0x2c04, 0x938c, 0x0001, 0x0120, 0x9084, - 0xff00, 0x8007, 0x0010, 0x9084, 0x00ff, 0x970e, 0x0904, 0x315c, - 0x908e, 0x0000, 0x0904, 0x315c, 0x908e, 0x00ff, 0x1160, 0x7230, - 0xd284, 0x1904, 0x3161, 0x7294, 0xc28d, 0x7296, 0x70af, 0xffff, - 0x003e, 0x0804, 0x3166, 0x2009, 0x180d, 0x210c, 0xd18c, 0x0150, - 0x0026, 0x2011, 0x0010, 0x080c, 0x6c96, 0x002e, 0x0118, 0x70af, - 0xffff, 0x0488, 0x900e, 0x080c, 0x28e8, 0x080c, 0x681e, 0x1538, - 0x9006, 0xb8bb, 0x0520, 0xb8ac, 0x9005, 0x0148, 0x00c6, 0x2060, - 0x080c, 0x8f6e, 0x00ce, 0x090c, 0x92ee, 0xb8af, 0x0000, 0x080c, - 0x6c5b, 0x1168, 0x7030, 0xd08c, 0x0130, 0xb800, 0xd0bc, 0x0138, - 0x080c, 0x6adf, 0x0120, 0x080c, 0x320b, 0x0148, 0x0028, 0x080c, - 0x3350, 0x080c, 0x3237, 0x0118, 0x8318, 0x0804, 0x3100, 0x73ae, - 0x0010, 0x70af, 0xffff, 0x003e, 0x0804, 0x31ed, 0x9780, 0x3471, - 0x203d, 0x97bc, 0xff00, 0x873f, 0x2041, 0x007e, 0x70ac, 0x9096, - 0xffff, 0x1118, 0x900e, 0x28a8, 0x0050, 0x9812, 0x0220, 0x2008, - 0x9802, 0x20a8, 0x0020, 0x70af, 0xffff, 0x0804, 0x31ed, 0x2700, - 0x0156, 0x0016, 0x9106, 0x0904, 0x31e2, 0x2001, 0x180d, 0x2004, - 0xd08c, 0x0158, 0x0026, 0x2011, 0x0010, 0x080c, 0x6c96, 0x002e, - 0x0120, 0x2009, 0xffff, 0x0804, 0x31ea, 0xc484, 0x080c, 0x6890, - 0x0168, 0x080c, 0xdb0c, 0x1904, 0x31e2, 0x080c, 0x3460, 0x1904, - 0x31e2, 0x080c, 0x681e, 0x1904, 0x31ea, 0x0008, 0xc485, 0xb8bb, - 0x0520, 0xb8ac, 0x9005, 0x0148, 0x00c6, 0x2060, 0x080c, 0x8f6e, - 0x00ce, 0x090c, 0x92ee, 0xb8af, 0x0000, 0x080c, 0x6c5b, 0x1130, - 0x7030, 0xd08c, 0x01f8, 0xb800, 0xd0bc, 0x11e0, 0x7294, 0xd28c, - 0x0180, 0x080c, 0x6c5b, 0x9082, 0x0006, 0x02e0, 0xd484, 0x1118, - 0x080c, 0x684b, 0x0028, 0x080c, 0x33dc, 0x01a0, 0x080c, 0x3407, - 0x0088, 0x080c, 0x3350, 0x080c, 0xdb0c, 0x1160, 0x080c, 0x3237, - 0x0188, 0x0040, 0x080c, 0xdb0c, 0x1118, 0x080c, 0x33dc, 0x0110, - 0x0451, 0x0140, 0x001e, 0x8108, 0x015e, 0x1f04, 0x317f, 0x70af, - 0xffff, 0x0018, 0x001e, 0x015e, 0x71ae, 0x004e, 0x002e, 0x00ce, - 0x00be, 0x0005, 0x00c6, 0x0016, 0x70af, 0x0001, 0x2009, 0x007e, - 0x080c, 0x681e, 0x1168, 0xb813, 0x00ff, 0xb817, 0xfffe, 0x080c, - 0x3350, 0x04a9, 0x0128, 0x70dc, 0xc0bd, 0x70de, 0x080c, 0xd855, - 0x001e, 0x00ce, 0x0005, 0x0016, 0x0076, 0x00d6, 0x00c6, 0x2001, - 0x184f, 0x2004, 0x9084, 0x00ff, 0xb842, 0x080c, 0xb58c, 0x01d0, - 0x2b00, 0x6012, 0x080c, 0xd87e, 0x6023, 0x0001, 0x9006, 0x080c, - 0x67bb, 0x2001, 0x0000, 0x080c, 0x67cf, 0x0126, 0x2091, 0x8000, - 0x70a8, 0x8000, 0x70aa, 0x012e, 0x2009, 0x0004, 0x080c, 0xb5b9, - 0x9085, 0x0001, 0x00ce, 0x00de, 0x007e, 0x001e, 0x0005, 0x0016, - 0x0076, 0x00d6, 0x00c6, 0x2001, 0x184f, 0x2004, 0x9084, 0x00ff, - 0xb842, 0x080c, 0xb58c, 0x0548, 0x2b00, 0x6012, 0xb800, 0xc0c4, - 0xb802, 0xb8a0, 0x9086, 0x007e, 0x0140, 0xb804, 0x9084, 0x00ff, - 0x9086, 0x0006, 0x1110, 0x080c, 0x330b, 0x080c, 0xd87e, 0x6023, - 0x0001, 0x9006, 0x080c, 0x67bb, 0x2001, 0x0002, 0x080c, 0x67cf, - 0x0126, 0x2091, 0x8000, 0x70a8, 0x8000, 0x70aa, 0x012e, 0x2009, - 0x0002, 0x080c, 0xb5b9, 0x9085, 0x0001, 0x00ce, 0x00de, 0x007e, - 0x001e, 0x0005, 0x00b6, 0x00c6, 0x0026, 0x2009, 0x0080, 0x080c, - 0x681e, 0x1140, 0xb813, 0x00ff, 0xb817, 0xfffc, 0x0039, 0x0110, - 0x70e3, 0xffff, 0x002e, 0x00ce, 0x00be, 0x0005, 0x0016, 0x0076, - 0x00d6, 0x00c6, 0x080c, 0xb58c, 0x01d0, 0x2b00, 0x6012, 0x080c, - 0xd87e, 0x6023, 0x0001, 0x9006, 0x080c, 0x67bb, 0x2001, 0x0002, - 0x080c, 0x67cf, 0x0126, 0x2091, 0x8000, 0x70e4, 0x8000, 0x70e6, - 0x012e, 0x2009, 0x0002, 0x080c, 0xb5b9, 0x9085, 0x0001, 0x00ce, - 0x00de, 0x007e, 0x001e, 0x0005, 0x00c6, 0x00d6, 0x0126, 0x2091, - 0x8000, 0x2009, 0x007f, 0x080c, 0x681e, 0x11e0, 0xb813, 0x00ff, - 0xb817, 0xfffd, 0xb8cf, 0x0004, 0x080c, 0xb58c, 0x0198, 0x83ff, - 0x1118, 0x70dc, 0xc0f5, 0x70de, 0x2b00, 0x6012, 0x6316, 0x6023, - 0x0001, 0x620a, 0x080c, 0xd87e, 0x2009, 0x0022, 0x080c, 0xb5b9, - 0x9085, 0x0001, 0x012e, 0x00de, 0x00ce, 0x0005, 0x00e6, 0x00c6, - 0x0066, 0x0036, 0x0026, 0x00b6, 0x21f0, 0x080c, 0x98e4, 0x080c, - 0x9864, 0x080c, 0xb37a, 0x080c, 0xc5a2, 0x3e08, 0x2130, 0x81ff, - 0x0120, 0x20a9, 0x007e, 0x900e, 0x0018, 0x20a9, 0x007f, 0x900e, - 0x0016, 0x080c, 0x6890, 0x1140, 0x9686, 0x0002, 0x1118, 0xb800, - 0xd0bc, 0x1110, 0x080c, 0x62ce, 0x001e, 0x8108, 0x1f04, 0x32f0, - 0x9686, 0x0001, 0x190c, 0x3434, 0x00be, 0x002e, 0x003e, 0x006e, - 0x00ce, 0x00ee, 0x0005, 0x00e6, 0x00c6, 0x0046, 0x0036, 0x0026, - 0x0016, 0x00b6, 0x6210, 0x2258, 0xbaa0, 0x0026, 0x2019, 0x0029, - 0x080c, 0x98d9, 0x0076, 0x2039, 0x0000, 0x080c, 0x97ac, 0x2c08, - 0x080c, 0xece8, 0x007e, 0x001e, 0xba10, 0xbb14, 0xbcc0, 0x080c, - 0x62ce, 0xba12, 0xbb16, 0xbcc2, 0x00be, 0x001e, 0x002e, 0x003e, - 0x004e, 0x00ce, 0x00ee, 0x0005, 0x00e6, 0x0006, 0x00b6, 0x6010, - 0x2058, 0xb8a0, 0x00be, 0x9086, 0x0080, 0x0150, 0x2071, 0x1800, - 0x70a8, 0x9005, 0x0110, 0x8001, 0x70aa, 0x000e, 0x00ee, 0x0005, - 0x2071, 0x1800, 0x70e4, 0x9005, 0x0dc0, 0x8001, 0x70e6, 0x0ca8, - 0xb800, 0xc08c, 0xb802, 0x0005, 0x00f6, 0x00e6, 0x00c6, 0x00b6, - 0x0046, 0x0036, 0x0026, 0x0016, 0x0156, 0x2178, 0x81ff, 0x1118, - 0x20a9, 0x0001, 0x0078, 0x080c, 0x595f, 0xd0c4, 0x0140, 0xd0a4, - 0x0130, 0x9006, 0x2020, 0x2009, 0x002d, 0x080c, 0xf00a, 0x20a9, - 0x0800, 0x9016, 0x0026, 0x928e, 0x007e, 0x0904, 0x33bb, 0x928e, - 0x007f, 0x0904, 0x33bb, 0x928e, 0x0080, 0x05e8, 0x9288, 0x1000, - 0x210c, 0x81ff, 0x05c0, 0x8fff, 0x1148, 0x2001, 0x1991, 0x0006, - 0x2003, 0x0001, 0x04f1, 0x000e, 0x2003, 0x0000, 0x00b6, 0x00c6, - 0x2158, 0x2001, 0x0001, 0x080c, 0x6c25, 0x00ce, 0x00be, 0x2019, - 0x0029, 0x080c, 0x98d9, 0x0076, 0x2039, 0x0000, 0x080c, 0x97ac, - 0x00b6, 0x00c6, 0x0026, 0x2158, 0xba04, 0x9294, 0x00ff, 0x9286, - 0x0006, 0x1118, 0xb807, 0x0404, 0x0028, 0x2001, 0x0004, 0x8007, - 0x9215, 0xba06, 0x002e, 0x00ce, 0x00be, 0x0016, 0x2c08, 0x080c, - 0xece8, 0x001e, 0x007e, 0x002e, 0x8210, 0x1f04, 0x3372, 0x015e, - 0x001e, 0x002e, 0x003e, 0x004e, 0x00be, 0x00ce, 0x00ee, 0x00fe, - 0x0005, 0x0046, 0x0026, 0x0016, 0x080c, 0x595f, 0xd0c4, 0x0140, - 0xd0a4, 0x0130, 0x9006, 0x2220, 0x2009, 0x0029, 0x080c, 0xf00a, - 0x001e, 0x002e, 0x004e, 0x0005, 0x0016, 0x0026, 0x0036, 0x00c6, - 0x7294, 0x82ff, 0x01e8, 0x080c, 0x6c53, 0x11d0, 0x2100, 0x080c, - 0x291b, 0x81ff, 0x01b8, 0x2019, 0x0001, 0x8314, 0x92e0, 0x1c80, - 0x2c04, 0xd384, 0x0120, 0x9084, 0xff00, 0x8007, 0x0010, 0x9084, - 0x00ff, 0x9116, 0x0138, 0x9096, 0x00ff, 0x0110, 0x8318, 0x0c68, - 0x9085, 0x0001, 0x00ce, 0x003e, 0x002e, 0x001e, 0x0005, 0x0016, - 0x00c6, 0x0126, 0x2091, 0x8000, 0x0036, 0x2019, 0x0029, 0x00a9, - 0x003e, 0x9180, 0x1000, 0x2004, 0x9065, 0x0158, 0x0016, 0x00c6, - 0x2061, 0x1aba, 0x001e, 0x6112, 0x080c, 0x330b, 0x001e, 0x080c, - 0x684b, 0x012e, 0x00ce, 0x001e, 0x0005, 0x0016, 0x0026, 0x2110, - 0x080c, 0xaeb9, 0x080c, 0xf381, 0x002e, 0x001e, 0x0005, 0x2001, - 0x1837, 0x2004, 0xd0cc, 0x0005, 0x00c6, 0x00b6, 0x080c, 0x77ff, - 0x1118, 0x20a9, 0x0800, 0x0010, 0x20a9, 0x0782, 0x080c, 0x77ff, - 0x1110, 0x900e, 0x0010, 0x2009, 0x007e, 0x9180, 0x1000, 0x2004, - 0x905d, 0x0130, 0x86ff, 0x0110, 0xb800, 0xd0bc, 0x090c, 0x684b, - 0x8108, 0x1f04, 0x3445, 0x2061, 0x1800, 0x607f, 0x0000, 0x6080, - 0x9084, 0x00ff, 0x6082, 0x60b3, 0x0000, 0x00be, 0x00ce, 0x0005, - 0x2001, 0x186c, 0x2004, 0xd0bc, 0x0005, 0x2011, 0x184b, 0x2214, - 0xd2ec, 0x0005, 0x0026, 0x2011, 0x186a, 0x2214, 0xd2dc, 0x002e, - 0x0005, 0x7eef, 0x7de8, 0x7ce4, 0x80e2, 0x7be1, 0x80e0, 0x80dc, - 0x80da, 0x7ad9, 0x80d6, 0x80d5, 0x80d4, 0x80d3, 0x80d2, 0x80d1, - 0x79ce, 0x78cd, 0x80cc, 0x80cb, 0x80ca, 0x80c9, 0x80c7, 0x80c6, - 0x77c5, 0x76c3, 0x80bc, 0x80ba, 0x75b9, 0x80b6, 0x74b5, 0x73b4, - 0x72b3, 0x80b2, 0x80b1, 0x80ae, 0x71ad, 0x80ac, 0x70ab, 0x6faa, - 0x6ea9, 0x80a7, 0x6da6, 0x6ca5, 0x6ba3, 0x6a9f, 0x699e, 0x689d, - 0x809b, 0x8098, 0x6797, 0x6690, 0x658f, 0x6488, 0x6384, 0x6282, - 0x8081, 0x8080, 0x617c, 0x607a, 0x8079, 0x5f76, 0x8075, 0x8074, - 0x8073, 0x8072, 0x8071, 0x806e, 0x5e6d, 0x806c, 0x5d6b, 0x5c6a, - 0x5b69, 0x8067, 0x5a66, 0x5965, 0x5863, 0x575c, 0x565a, 0x5559, - 0x8056, 0x8055, 0x5454, 0x5353, 0x5252, 0x5151, 0x504e, 0x4f4d, - 0x804c, 0x804b, 0x4e4a, 0x4d49, 0x8047, 0x4c46, 0x8045, 0x8043, - 0x803c, 0x803a, 0x8039, 0x8036, 0x4b35, 0x8034, 0x4a33, 0x4932, - 0x4831, 0x802e, 0x472d, 0x462c, 0x452b, 0x442a, 0x4329, 0x4227, - 0x8026, 0x8025, 0x4123, 0x401f, 0x3f1e, 0x3e1d, 0x3d1b, 0x3c18, - 0x8017, 0x8010, 0x3b0f, 0x3a08, 0x8004, 0x3902, 0x8001, 0x8000, - 0x8000, 0x3800, 0x3700, 0x3600, 0x8000, 0x3500, 0x8000, 0x8000, - 0x8000, 0x3400, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, - 0x3300, 0x3200, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, - 0x3100, 0x3000, 0x8000, 0x8000, 0x2f00, 0x8000, 0x2e00, 0x2d00, - 0x2c00, 0x8000, 0x8000, 0x8000, 0x2b00, 0x8000, 0x2a00, 0x2900, - 0x2800, 0x8000, 0x2700, 0x2600, 0x2500, 0x2400, 0x2300, 0x2200, - 0x8000, 0x8000, 0x2100, 0x2000, 0x1f00, 0x1e00, 0x1d00, 0x1c00, - 0x8000, 0x8000, 0x1b00, 0x1a00, 0x8000, 0x1900, 0x8000, 0x8000, - 0x8000, 0x8000, 0x8000, 0x8000, 0x1800, 0x8000, 0x1700, 0x1600, - 0x1500, 0x8000, 0x1400, 0x1300, 0x1200, 0x1100, 0x1000, 0x0f00, - 0x8000, 0x8000, 0x0e00, 0x0d00, 0x0c00, 0x0b00, 0x0a00, 0x0900, - 0x8000, 0x8000, 0x0800, 0x0700, 0x8000, 0x0600, 0x8000, 0x8000, - 0x8000, 0x0500, 0x0400, 0x0300, 0x8000, 0x0200, 0x8000, 0x8000, - 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0x2069, 0x1800, 0x6a7c, 0x720a, 0x6a80, 0x720e, 0x7013, 0x0829, - 0x2f10, 0x7222, 0x7027, 0xffff, 0x0005, 0x00d6, 0x0096, 0x0081, - 0x7814, 0x2048, 0xa894, 0x7002, 0xa890, 0x7006, 0xa8b4, 0x700a, - 0xa8b0, 0x700e, 0x60c3, 0x000c, 0x009e, 0x00de, 0x0804, 0xa8ef, - 0x6813, 0x0008, 0xb810, 0x9085, 0x0500, 0x7002, 0xb814, 0x7006, - 0x2069, 0x1800, 0x687c, 0x700a, 0x6880, 0x700e, 0x7013, 0x0889, - 0x080c, 0xa8dd, 0x721a, 0x7a08, 0x7222, 0x2f10, 0x7226, 0x2071, - 0x024c, 0x0005, 0x00d6, 0x0096, 0x080c, 0xa612, 0x7814, 0x2048, - 0x080c, 0xd3f3, 0x1130, 0x7814, 0x9084, 0x0700, 0x8007, 0x0033, - 0x0010, 0x9006, 0x001b, 0x009e, 0x00de, 0x0005, 0xa530, 0xa599, - 0xa5a9, 0xa5cf, 0xa5db, 0xa5ec, 0xa5f4, 0xa52e, 0x080c, 0x0dcc, - 0x0016, 0x0036, 0xa980, 0x918c, 0x0003, 0x0118, 0x9186, 0x0003, - 0x1198, 0xabac, 0x7824, 0xd0cc, 0x1168, 0x7316, 0xa89c, 0x701a, - 0xa898, 0x701e, 0x003e, 0x001e, 0x2001, 0x19b5, 0x2004, 0x60c2, - 0x0804, 0xa8ef, 0xc3e5, 0x0c88, 0x9186, 0x0001, 0x190c, 0x0dcc, - 0xabac, 0x7824, 0xd0cc, 0x1904, 0xa596, 0x7316, 0xa89c, 0x701a, - 0xa898, 0x701e, 0xa8a8, 0x7026, 0xa8b0, 0x702e, 0x2009, 0x0018, - 0x9384, 0x0300, 0x0570, 0xd3c4, 0x0110, 0xa8b0, 0x9108, 0xd3cc, - 0x0110, 0xa8a8, 0x9108, 0x6810, 0x9085, 0x0010, 0x6812, 0x2011, - 0x0258, 0x20e9, 0x0000, 0x22a0, 0x0156, 0x20a9, 0x0008, 0xa860, - 0x20e0, 0xa85c, 0x9080, 0x002d, 0x2098, 0x4003, 0x6810, 0x8000, - 0x6812, 0x2011, 0x0240, 0x22a0, 0x20a9, 0x0005, 0x4003, 0x6810, - 0xc0a4, 0x6812, 0x015e, 0x9184, 0x0003, 0x0118, 0x2019, 0x0245, - 0x201a, 0x61c2, 0x003e, 0x001e, 0x0804, 0xa8ef, 0xc3e5, 0x0804, - 0xa555, 0x2011, 0x0008, 0x2001, 0x180f, 0x2004, 0xd0a4, 0x0110, - 0x2011, 0x0028, 0x7824, 0xd0cc, 0x1110, 0x7216, 0x0470, 0x0ce8, - 0xc2e5, 0x2011, 0x0302, 0x0016, 0x782c, 0x701a, 0x7930, 0x711e, - 0x9105, 0x0108, 0xc2dd, 0x001e, 0x7824, 0xd0cc, 0x0108, 0xc2e5, - 0x7216, 0x7027, 0x0012, 0x702f, 0x0008, 0x7043, 0x7000, 0x7047, - 0x0500, 0x704f, 0x000a, 0x2069, 0x0200, 0x6813, 0x0009, 0x2071, - 0x0240, 0x700b, 0x2500, 0x60c3, 0x0032, 0x0804, 0xa8ef, 0x2011, - 0x0028, 0x7824, 0xd0cc, 0x1128, 0x7216, 0x60c3, 0x0018, 0x0804, - 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0x7032, 0x0010, 0x7033, 0x3f00, 0x60c3, 0x0001, 0x0804, 0xa8ef, - 0x2009, 0x0003, 0x0019, 0x7033, 0x7f00, 0x0cb0, 0x0016, 0x080c, - 0xb1f7, 0x001e, 0xb810, 0x9085, 0x0100, 0x7002, 0xb814, 0x7006, - 0x2069, 0x1800, 0x6a7c, 0x720a, 0x6a80, 0x720e, 0x7013, 0x0888, - 0x918d, 0x0008, 0x7116, 0x080c, 0xa8dd, 0x721a, 0x7a08, 0x7222, - 0x2f10, 0x7226, 0x0005, 0x00b6, 0x00e6, 0x00d6, 0x00c6, 0x0066, - 0x0056, 0x0046, 0x0036, 0x2061, 0x0100, 0x2071, 0x1800, 0x7160, - 0x7810, 0x2058, 0x76dc, 0x96b4, 0x0028, 0x0110, 0x737c, 0x7480, - 0x2500, 0x76dc, 0x96b4, 0x0028, 0x0140, 0x2001, 0x04ff, 0x6062, - 0x6067, 0xffff, 0x636a, 0x646e, 0x0050, 0x2001, 0x00ff, 0x9085, - 0x0400, 0x6062, 0x6067, 0xffff, 0x606b, 0x0000, 0x616e, 0xb8b8, - 0x6073, 0x0530, 0x6077, 0x0008, 0xb88c, 0x8000, 0x9084, 0x00ff, - 0xb88e, 0x8007, 0x9085, 0x0020, 0x607a, 0x607f, 0x0000, 0x2b00, - 0x6082, 0x6087, 0xffff, 0x7814, 0x0096, 0x2048, 0xa838, 0x608a, - 0xa834, 0x608e, 0xa848, 0x60c6, 0xa844, 0x60ca, 0x009e, 0xb86c, - 0x60ce, 0x60ab, 0x0036, 0x60af, 0x95d5, 0x60d7, 0x0000, 0x2001, - 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0x20e1, 0x0000, 0x4003, 0x83ff, 0x0180, 0x3300, 0x9086, 0x0280, - 0x1130, 0x7814, 0x8000, 0x9085, 0x0080, 0x7816, 0x2e98, 0x2310, - 0x84ff, 0x0904, 0xb8a5, 0x0804, 0xb8a7, 0x9085, 0x0001, 0x7817, - 0x0000, 0x009e, 0x00fe, 0x00de, 0x001e, 0x0005, 0x00d6, 0x0036, - 0x0096, 0x6314, 0x2348, 0xa87e, 0xa986, 0x080c, 0x7061, 0x009e, - 0x003e, 0x00de, 0x0005, 0x91b6, 0x0015, 0x1118, 0x080c, 0xb53c, - 0x0030, 0x91b6, 0x0016, 0x190c, 0x0dcc, 0x080c, 0xb53c, 0x0005, - 0x20a9, 0x000e, 0x20e1, 0x0000, 0x2e98, 0x6014, 0x0096, 0x2048, - 0xa804, 0x9005, 0x15c0, 0x2900, 0x009e, 0x0096, 0x2048, 0xa860, - 0x20e8, 0xa85c, 0x20a0, 0x009e, 0x4003, 0x9196, 0x0016, 0x01f0, - 0x0136, 0x9080, 0x001c, 0x20a0, 0x2011, 0x0006, 0x20a9, 0x0001, - 0x3418, 0x8318, 0x23a0, 0x4003, 0x3318, 0x8318, 0x2398, 0x8211, - 0x1db8, 0x2011, 0x0006, 0x013e, 0x20a0, 0x3318, 0x8318, 0x2398, - 0x4003, 0x3418, 0x8318, 0x23a0, 0x8211, 0x1db8, 0x0096, 0x080c, - 0xd3f5, 0x0130, 0x6014, 0x2048, 0xa807, 0x0000, 0xa86b, 0x0103, - 0x009e, 0x0804, 0xb53c, 0x009e, 0x7130, 0x918e, 0x0100, 0x1120, - 0x080c, 0xbf7f, 0x0804, 0xb53c, 0x20e1, 0x0000, 0x9e88, 0x000e, - 0x2198, 0x0096, 0x2048, 0xa860, 0x20e8, 0xa85c, 0x009e, 0x0136, - 0x9080, 0x000e, 0x20a0, 0x2011, 0x0006, 0x20a9, 0x0001, 0x3418, - 0x83a0, 0x4003, 0x3318, 0x8398, 0x8211, 0x1dc8, 0x2011, 0x0006, - 0x013e, 0x20a0, 0x3318, 0x8398, 0x4003, 0x3418, 0x83a0, 0x8211, - 0x1dc8, 0x6014, 0x0096, 0x2048, 0xa804, 0x0086, 0x2040, 0x2009, - 0x000c, 0x8806, 0x8006, 0x8007, 0x90bc, 0x003f, 0x9084, 0xffc0, - 0x9080, 0x000e, 0xaaa4, 0xaba0, 0xacac, 0xada8, 0x2031, 0x0000, - 0x2041, 0x1270, 0x080c, 0xbab4, 0x0120, 0x008e, 0x009e, 0x0804, - 0xb53c, 0x080c, 0xbf7f, 0x0cc8, 0x0096, 0x00d6, 0x0036, 0x7330, - 0x9386, 0x0200, 0x11a8, 0x6010, 0x00b6, 0x2058, 0xb8cf, 0x0000, - 0x00be, 0x6014, 0x9005, 0x0130, 0x2048, 0xa807, 0x0000, 0xa86b, - 0x0103, 0xab32, 0x080c, 0xb53c, 0x003e, 0x00de, 0x009e, 0x0005, - 0x0011, 0x1d48, 0x0cc8, 0x0006, 0x0016, 0x080c, 0xdb0c, 0x0188, - 0x6014, 0x9005, 0x1170, 0x600b, 0x0003, 0x601b, 0x0000, 0x6043, - 0x0000, 0x2009, 0x0022, 0x080c, 0xbda4, 0x9006, 0x001e, 0x000e, - 0x0005, 0x9085, 0x0001, 0x0cd0, 0x0096, 0x0016, 0x20a9, 0x0014, - 0x9e80, 0x000c, 0x20e1, 0x0000, 0x2098, 0x6014, 0x2048, 0xa860, - 0x20e8, 0xa85c, 0x9080, 0x0002, 0x20a0, 0x4003, 0x2001, 0x0205, - 0x2003, 0x0001, 0x2099, 0x0260, 0x20a9, 0x0016, 0x4003, 0x20a9, - 0x000a, 0xa804, 0x2048, 0xa860, 0x20e8, 0xa85c, 0x9080, 0x0002, - 0x20a0, 0x4003, 0x2001, 0x0205, 0x2003, 0x0002, 0x2099, 0x0260, - 0x20a9, 0x0020, 0x4003, 0x2003, 0x0000, 0x6014, 0x2048, 0xa800, - 0x2048, 0xa86b, 0x0103, 0x080c, 0xb53c, 0x001e, 0x009e, 0x0005, - 0x0096, 0x0016, 0x900e, 0x7030, 0x9086, 0x0100, 0x0140, 0x7038, - 0x9084, 0x00ff, 0x800c, 0x703c, 0x9084, 0x00ff, 0x8004, 0x9080, - 0x0004, 0x9108, 0x810b, 0x2011, 0x0002, 0x2019, 0x000c, 0x6014, - 0x2048, 0x080c, 0xcf79, 0x2011, 0x0205, 0x2013, 0x0000, 0x080c, - 0xd3f5, 0x0140, 0x6014, 0x2048, 0xa807, 0x0000, 0xa868, 0xa8e6, - 0xa86b, 0x0103, 0x080c, 0xb53c, 0x001e, 0x009e, 0x0005, 0x0016, - 0x2009, 0x0000, 0x7030, 0x9086, 0x0200, 0x0110, 0x2009, 0x0001, - 0x0096, 0x6014, 0x904d, 0x090c, 0x0dcc, 0xa97e, 0x080c, 0x706e, - 0x009e, 0x080c, 0xb53c, 0x001e, 0x0005, 0x0016, 0x0096, 0x7030, - 0x9086, 0x0100, 0x1118, 0x2009, 0x0004, 0x0010, 0x7034, 0x800c, - 0x810b, 0x2011, 0x000c, 0x2019, 0x000c, 0x6014, 0x2048, 0xa804, - 0x0096, 0x9005, 0x0108, 0x2048, 0x080c, 0xcf79, 0x2011, 0x0205, - 0x2013, 0x0000, 0x009e, 0x080c, 0xd3f5, 0x0148, 0xa804, 0x9005, - 0x1158, 0xa807, 0x0000, 0xa868, 0xa8e6, 0xa86b, 0x0103, 0x080c, - 0xb53c, 0x009e, 0x001e, 0x0005, 0x0086, 0x2040, 0xa030, 0x8007, - 0x9086, 0x0100, 0x1118, 0x080c, 0xbf7f, 0x00e0, 0xa034, 0x8007, - 0x800c, 0x8806, 0x8006, 0x8007, 0x90bc, 0x003f, 0x9084, 0xffc0, - 0x9080, 0x000c, 0xa87f, 0x0000, 0xa887, 0x0000, 0xa89b, 0x4000, - 0xaaa4, 0xaba0, 0xacac, 0xada8, 0x2031, 0x0000, 0x2041, 0x1270, - 0x0019, 0x0d08, 0x008e, 0x0898, 0x0096, 0x0006, 0x080c, 0x1016, - 0x000e, 0x01b0, 0xa8af, 0x0dcb, 0xa87a, 0x000e, 0xa8a6, 0x0006, - 0xae6e, 0x2800, 0xa8a2, 0xa97e, 0xaf76, 0xaa92, 0xab96, 0xac9a, - 0xad9e, 0x0086, 0x2940, 0x080c, 0x1114, 0x008e, 0x9085, 0x0001, - 0x009e, 0x0005, 0x00e6, 0x00d6, 0x0026, 0x7008, 0x9084, 0x00ff, - 0x6210, 0x00b6, 0x2258, 0xba10, 0x00be, 0x9206, 0x1540, 0x700c, - 0x6210, 0x00b6, 0x2258, 0xba14, 0x00be, 0x9206, 0x1500, 0x6043, - 0x0000, 0x2c68, 0x0016, 0x2009, 0x0035, 0x080c, 0xda7d, 0x001e, - 0x1178, 0x622c, 0x2268, 0x6054, 0x6b54, 0x9306, 0x1148, 0x2071, - 0x026c, 0x6b20, 0x9386, 0x0003, 0x0130, 0x9386, 0x0006, 0x0128, - 0x080c, 0xb56f, 0x0020, 0x0039, 0x0010, 0x080c, 0xbbdb, 0x002e, - 0x00de, 0x00ee, 0x0005, 0x0096, 0x6814, 0x2048, 0x9186, 0x0015, - 0x0904, 0xbbc1, 0x918e, 0x0016, 0x1904, 0xbbd9, 0x700c, 0x908c, - 0xff00, 0x9186, 0x1700, 0x0120, 0x9186, 0x0300, 0x1904, 0xbb9b, - 0x89ff, 0x1138, 0x6800, 0x9086, 0x000f, 0x0904, 0xbb7c, 0x0804, - 0xbbd7, 0x6808, 0x9086, 0xffff, 0x1904, 0xbbc3, 0xa880, 0x9084, - 0x0060, 0x9086, 0x0020, 0x1128, 0xa83c, 0xa940, 0x9105, 0x1904, - 0xbbc3, 0x6824, 0xd084, 0x1904, 0xbbc3, 0xd0b4, 0x0158, 0x0016, - 0x2001, 0x1989, 0x200c, 0x6018, 0x9102, 0x9082, 0x0005, 0x001e, - 0x1a04, 0xbbc3, 0x080c, 0xd5f2, 0x685c, 0xa886, 0xa880, 0xc0dc, - 0xc0f4, 0xc0d4, 0xa882, 0x0026, 0x900e, 0x6a18, 0x2001, 0x000a, - 0x080c, 0x95a7, 0xa888, 0x920a, 0x0208, 0x8011, 0xaa8a, 0x82ff, - 0x002e, 0x1138, 0x00c6, 0x2d60, 0x080c, 0xd0f9, 0x00ce, 0x0804, - 0xbbd7, 0x00c6, 0xa86c, 0xd0fc, 0x1118, 0x080c, 0x6347, 0x0010, - 0x080c, 0x6765, 0x00ce, 0x1904, 0xbbc3, 0x00c6, 0x2d60, 0x080c, - 0xb56f, 0x00ce, 0x0804, 0xbbd7, 0x00c6, 0x080c, 0xb58c, 0x01a8, - 0x6818, 0x601a, 0x6017, 0x0000, 0x6810, 0x6012, 0x080c, 0xd87e, - 0x6023, 0x0003, 0x6904, 0x00c6, 0x2d60, 0x080c, 0xb56f, 0x00ce, - 0x080c, 0xb5b9, 0x00ce, 0x0804, 0xbbd7, 0x2001, 0x198b, 0x2004, - 0x6842, 0x00ce, 0x04e0, 0x7008, 0x9086, 0x000b, 0x11c8, 0x6010, - 0x00b6, 0x2058, 0xb900, 0xc1bc, 0xb902, 0x00be, 0x00c6, 0x2d60, - 0xa87f, 0x0003, 0x080c, 0xdac1, 0x6007, 0x0085, 0x6003, 0x000b, - 0x6023, 0x0002, 0x080c, 0x9734, 0x080c, 0x9ce8, 0x00ce, 0x00f8, - 0x700c, 0x9086, 0x2a00, 0x1138, 0x2001, 0x198b, 0x2004, 0x6842, - 0x00b0, 0x0489, 0x00b0, 0x89ff, 0x090c, 0x0dcc, 0x00c6, 0x00d6, - 0x2d60, 0xa86b, 0x0103, 0xa87f, 0x0003, 0xa87b, 0x0000, 0x080c, - 0x6e88, 0x080c, 0xd5f2, 0x080c, 0xb56f, 0x00de, 0x00ce, 0x080c, - 0xb53c, 0x009e, 0x0005, 0x9186, 0x0015, 0x1128, 0x2001, 0x198b, - 0x2004, 0x6842, 0x0068, 0x918e, 0x0016, 0x1160, 0x00c6, 0x2d00, - 0x2060, 0x080c, 0xf26e, 0x080c, 0x8c97, 0x080c, 0xb53c, 0x00ce, - 0x080c, 0xb53c, 0x0005, 0x0026, 0x0036, 0x0046, 0x7228, 0xacb4, - 0xabb0, 0xd2f4, 0x0130, 0x2001, 0x198b, 0x2004, 0x6842, 0x0804, - 0xbc55, 0x00c6, 0x2d60, 0x080c, 0xcffe, 0x00ce, 0x6804, 0x9086, - 0x0050, 0x1168, 0x00c6, 0x2d00, 0x2060, 0x6003, 0x0001, 0x6007, - 0x0050, 0x080c, 0x9734, 0x080c, 0x9ce8, 0x00ce, 0x04f0, 0x6800, - 0x9086, 0x000f, 0x01a8, 0x89ff, 0x090c, 0x0dcc, 0x6800, 0x9086, - 0x0004, 0x1190, 0xa880, 0xd0ac, 0x0178, 0xa843, 0x0fff, 0xa83f, - 0x0fff, 0xa884, 0xc0fc, 0xa886, 0x2001, 0x0001, 0x6832, 0x0400, - 0x2001, 0x0007, 0x6832, 0x00e0, 0xa880, 0xd0b4, 0x1150, 0xd0ac, - 0x0db8, 0x6824, 0xd0f4, 0x1d48, 0xa838, 0xa934, 0x9105, 0x0d80, - 0x0c20, 0xd2ec, 0x1d68, 0x7024, 0x9306, 0x1118, 0x7020, 0x9406, - 0x0d38, 0x7020, 0x683e, 0x7024, 0x683a, 0x2001, 0x0005, 0x6832, - 0x080c, 0xd775, 0x080c, 0x9ce8, 0x0010, 0x080c, 0xb53c, 0x004e, - 0x003e, 0x002e, 0x0005, 0x00e6, 0x00d6, 0x0026, 0x7008, 0x9084, - 0x00ff, 0x6210, 0x00b6, 0x2258, 0xba10, 0x00be, 0x9206, 0x1904, - 0xbcbc, 0x700c, 0x6210, 0x00b6, 0x2258, 0xba14, 0x00be, 0x9206, - 0x1904, 0xbcbc, 0x6038, 0x2068, 0x6824, 0xc0dc, 0x6826, 0x6a20, - 0x9286, 0x0007, 0x0904, 0xbcbc, 0x9286, 0x0002, 0x05e8, 0x9286, - 0x0000, 0x05d0, 0x6808, 0x633c, 0x9306, 0x15b0, 0x2071, 0x026c, - 0x9186, 0x0015, 0x0558, 0x00c6, 0x6038, 0x2060, 0x6104, 0x9186, - 0x004b, 0x01c0, 0x9186, 0x004c, 0x01a8, 0x9186, 0x004d, 0x0190, - 0x9186, 0x004e, 0x0178, 0x9186, 0x0052, 0x0160, 0x6014, 0x0096, - 0x2048, 0x080c, 0xd3f5, 0x090c, 0x0dcc, 0xa87f, 0x0003, 0x009e, - 0x080c, 0xdac1, 0x6007, 0x0085, 0x6003, 0x000b, 0x6023, 0x0002, - 0x080c, 0x9734, 0x080c, 0x9ce8, 0x00ce, 0x0030, 0x6038, 0x2070, - 0x2001, 0x198b, 0x2004, 0x7042, 0x080c, 0xb53c, 0x002e, 0x00de, - 0x00ee, 0x0005, 0x00b6, 0x0096, 0x00f6, 0x6014, 0x2048, 0x6010, - 0x2058, 0x91b6, 0x0015, 0x0130, 0xba08, 0xbb0c, 0xbc00, 0xc48c, - 0xbc02, 0x0470, 0x0096, 0x0156, 0x0036, 0x0026, 0x2b48, 0x9e90, - 0x0010, 0x2019, 0x000a, 0x20a9, 0x0004, 0x080c, 0xc661, 0x002e, - 0x003e, 0x015e, 0x009e, 0x1904, 0xbd2d, 0x0096, 0x0156, 0x0036, - 0x0026, 0x2b48, 0x9e90, 0x0014, 0x2019, 0x0006, 0x20a9, 0x0004, - 0x080c, 0xc661, 0x002e, 0x003e, 0x015e, 0x009e, 0x15b0, 0x7238, - 0xba0a, 0x733c, 0xbb0e, 0x83ff, 0x0118, 0xbc00, 0xc48d, 0xbc02, - 0xa804, 0x9005, 0x1128, 0x00fe, 0x009e, 0x00be, 0x0804, 0xb946, - 0x0096, 0x2048, 0xaa12, 0xab16, 0xac0a, 0x009e, 0x8006, 0x8006, - 0x8007, 0x90bc, 0x003f, 0x9084, 0xffc0, 0x9080, 0x0002, 0x2009, - 0x002b, 0xaaa4, 0xaba0, 0xacac, 0xada8, 0x2031, 0x0000, 0x2041, - 0x1270, 0x080c, 0xbab4, 0x0130, 0x00fe, 0x009e, 0x080c, 0xb53c, - 0x00be, 0x0005, 0x080c, 0xbf7f, 0x0cb8, 0x2b78, 0x00f6, 0x080c, - 0x330b, 0x080c, 0xdb21, 0x00fe, 0x00c6, 0x080c, 0xb4e6, 0x2f00, - 0x6012, 0x6017, 0x0000, 0x6023, 0x0001, 0x6007, 0x0001, 0x6003, - 0x0001, 0x2001, 0x0007, 0x080c, 0x67cf, 0x080c, 0x67fb, 0x080c, - 0x977c, 0x080c, 0x9ce8, 0x00ce, 0x0804, 0xbd00, 0x2100, 0x91b2, - 0x0054, 0x1a0c, 0x0dcc, 0x91b2, 0x0040, 0x1a04, 0xbdb6, 0x0002, - 0xbda4, 0xbda4, 0xbd9a, 0xbda4, 0xbda4, 0xbda4, 0xbd98, 0xbd98, - 0xbd98, 0xbd98, 0xbd98, 0xbd98, 0xbd98, 0xbd98, 0xbd98, 0xbd98, - 0xbd98, 0xbd98, 0xbd98, 0xbd98, 0xbd98, 0xbd98, 0xbd98, 0xbd98, - 0xbd98, 0xbd98, 0xbd98, 0xbd98, 0xbd98, 0xbd98, 0xbd98, 0xbda4, - 0xbd98, 0xbda4, 0xbda4, 0xbd98, 0xbd98, 0xbd98, 0xbd98, 0xbd98, - 0xbd9a, 0xbd98, 0xbd98, 0xbd98, 0xbd98, 0xbd98, 0xbd98, 0xbd98, - 0xbd98, 0xbd98, 0xbda4, 0xbda4, 0xbd98, 0xbd98, 0xbd98, 0xbd98, - 0xbd98, 0xbd98, 0xbd98, 0xbd98, 0xbd98, 0xbda4, 0xbd98, 0xbd98, - 0x080c, 0x0dcc, 0x0066, 0x00b6, 0x6610, 0x2658, 0xb8cc, 0xc08c, - 0xb8ce, 0x00be, 0x006e, 0x0000, 0x6003, 0x0001, 0x6106, 0x9186, - 0x0032, 0x0118, 0x080c, 0x977c, 0x0010, 0x080c, 0x9734, 0x0126, - 0x2091, 0x8000, 0x080c, 0x9ce8, 0x012e, 0x0005, 0x2600, 0x0002, - 0xbda4, 0xbda4, 0xbdcc, 0xbda4, 0xbda4, 0xbdcc, 0xbdcc, 0xbdcc, - 0xbdcc, 0xbda4, 0xbdcc, 0xbda4, 0xbdcc, 0xbda4, 0xbdcc, 0xbdcc, - 0xbdcc, 0xbdcc, 0xbdcc, 0xbdcc, 0x080c, 0x0dcc, 0x6004, 0x90b2, - 0x0054, 0x1a0c, 0x0dcc, 0x91b6, 0x0013, 0x0904, 0xbea1, 0x91b6, - 0x0027, 0x1904, 0xbe4b, 0x080c, 0x9bda, 0x6004, 0x080c, 0xd5fe, - 0x01b0, 0x080c, 0xd60f, 0x01a8, 0x908e, 0x0021, 0x0904, 0xbe48, - 0x908e, 0x0022, 0x1130, 0x080c, 0xb9c3, 0x0904, 0xbe44, 0x0804, - 0xbe45, 0x908e, 0x003d, 0x0904, 0xbe48, 0x0804, 0xbe3e, 0x080c, - 0x3334, 0x2001, 0x0007, 0x080c, 0x67cf, 0x6010, 0x00b6, 0x2058, - 0xb9a0, 0x00be, 0x080c, 0xbf7f, 0x9186, 0x007e, 0x1148, 0x2001, - 0x1837, 0x2014, 0xc285, 0x080c, 0x77ff, 0x1108, 0xc2ad, 0x2202, - 0x0036, 0x0026, 0x2019, 0x0028, 0x2110, 0x080c, 0xf381, 0x002e, - 0x003e, 0x0016, 0x0026, 0x0036, 0x2110, 0x2019, 0x0028, 0x080c, - 0x98d9, 0x0076, 0x903e, 0x080c, 0x97ac, 0x6010, 0x00b6, 0x905d, - 0x0100, 0x00be, 0x2c08, 0x080c, 0xece8, 0x007e, 0x003e, 0x002e, - 0x001e, 0x080c, 0xdb21, 0x0016, 0x080c, 0xd876, 0x080c, 0xb53c, - 0x001e, 0x080c, 0x3407, 0x080c, 0x9ce8, 0x0030, 0x080c, 0xd876, - 0x080c, 0xb53c, 0x080c, 0x9ce8, 0x0005, 0x080c, 0xbf7f, 0x0cb0, - 0x080c, 0xbfbb, 0x0c98, 0x9186, 0x0015, 0x0118, 0x9186, 0x0016, - 0x1148, 0x080c, 0xdb50, 0x0d80, 0x6000, 0x9086, 0x0002, 0x0904, - 0xbfc6, 0x0c50, 0x9186, 0x0014, 0x1d38, 0x080c, 0x9bda, 0x6004, - 0x908e, 0x0022, 0x1118, 0x080c, 0xb9c3, 0x09f0, 0x080c, 0x330b, - 0x080c, 0xdb21, 0x080c, 0xd5fe, 0x1198, 0x080c, 0x3334, 0x6010, - 0x00b6, 0x2058, 0xb9a0, 0x00be, 0x080c, 0xbf7f, 0x9186, 0x007e, - 0x1128, 0x2001, 0x1837, 0x200c, 0xc185, 0x2102, 0x0804, 0xbe3e, - 0x080c, 0xd60f, 0x1120, 0x080c, 0xbf7f, 0x0804, 0xbe3e, 0x6004, - 0x908e, 0x0032, 0x1160, 0x00e6, 0x00f6, 0x2071, 0x18a1, 0x2079, - 0x0000, 0x080c, 0x36a2, 0x00fe, 0x00ee, 0x0804, 0xbe3e, 0x6004, - 0x908e, 0x0021, 0x0d40, 0x908e, 0x0022, 0x090c, 0xbf7f, 0x0804, - 0xbe3e, 0x90b2, 0x0040, 0x1a04, 0xbf59, 0x2008, 0x0002, 0xbee9, - 0xbeea, 0xbeed, 0xbef0, 0xbef3, 0xbf00, 0xbee7, 0xbee7, 0xbee7, - 0xbee7, 0xbee7, 0xbee7, 0xbee7, 0xbee7, 0xbee7, 0xbee7, 0xbee7, - 0xbee7, 0xbee7, 0xbee7, 0xbee7, 0xbee7, 0xbee7, 0xbee7, 0xbee7, - 0xbee7, 0xbee7, 0xbee7, 0xbee7, 0xbee7, 0xbf03, 0xbf0e, 0xbee7, - 0xbf10, 0xbf0e, 0xbee7, 0xbee7, 0xbee7, 0xbee7, 0xbee7, 0xbf0e, - 0xbf0e, 0xbee7, 0xbee7, 0xbee7, 0xbee7, 0xbee7, 0xbee7, 0xbee7, - 0xbee7, 0xbf40, 0xbf0e, 0xbee7, 0xbf0c, 0xbee7, 0xbee7, 0xbee7, - 0xbf0d, 0xbee7, 0xbee7, 0xbee7, 0xbf0e, 0xbf37, 0xbee7, 0x080c, - 0x0dcc, 0x0420, 0x2001, 0x000b, 0x0460, 0x2001, 0x0003, 0x0448, - 0x2001, 0x0005, 0x0430, 0x6010, 0x00b6, 0x2058, 0xb804, 0x00be, - 0x9084, 0x00ff, 0x9086, 0x0000, 0x11f0, 0x2001, 0x0001, 0x00c8, - 0x2001, 0x0009, 0x00b0, 0x080c, 0x9bda, 0x6003, 0x0005, 0x080c, - 0xdb24, 0x080c, 0x9ce8, 0x0060, 0x0008, 0x0000, 0x0804, 0xbf51, - 0x080c, 0x9bda, 0x080c, 0xdb24, 0x6003, 0x0004, 0x080c, 0x9ce8, - 0x0005, 0x080c, 0x67cf, 0x080c, 0x9bda, 0x6003, 0x0002, 0x0036, - 0x2019, 0x1855, 0x2304, 0x9084, 0xff00, 0x1120, 0x2001, 0x1989, - 0x201c, 0x0040, 0x8007, 0x909a, 0x0004, 0x0ec0, 0x8003, 0x801b, - 0x831b, 0x9318, 0x631a, 0x003e, 0x080c, 0x9ce8, 0x0c08, 0x080c, - 0x9bda, 0x080c, 0xd876, 0x080c, 0xb53c, 0x080c, 0x9ce8, 0x08c0, - 0x00e6, 0x00f6, 0x2071, 0x18a1, 0x2079, 0x0000, 0x080c, 0x36a2, - 0x00fe, 0x00ee, 0x080c, 0x9bda, 0x080c, 0xb53c, 0x080c, 0x9ce8, - 0x0838, 0x080c, 0x9bda, 0x6003, 0x0002, 0x080c, 0xdb24, 0x0804, - 0x9ce8, 0x2600, 0x2008, 0x0002, 0xbf72, 0xbf51, 0xbf70, 0xbf51, - 0xbf51, 0xbf70, 0xbf70, 0xbf70, 0xbf70, 0xbf51, 0xbf70, 0xbf51, - 0xbf70, 0xbf51, 0xbf70, 0xbf70, 0xbf70, 0xbf70, 0xbf70, 0xbf70, - 0x080c, 0x0dcc, 0x080c, 0x9bda, 0x0096, 0x6014, 0x2048, 0x080c, - 0x706e, 0x009e, 0x080c, 0xb53c, 0x080c, 0x9ce8, 0x0005, 0x00e6, - 0x0096, 0x0026, 0x0016, 0x080c, 0xd3f5, 0x0568, 0x6014, 0x2048, - 0xa868, 0x9086, 0x0139, 0x11a8, 0xa898, 0x9086, 0x0056, 0x1148, - 0x080c, 0x56f4, 0x0130, 0x2001, 0x0000, 0x900e, 0x2011, 0x4000, - 0x0028, 0x2001, 0x0030, 0x900e, 0x2011, 0x4005, 0x080c, 0xd9e7, - 0x0090, 0xa86c, 0xd0fc, 0x0178, 0xa807, 0x0000, 0x0016, 0x6004, - 0x908e, 0x0021, 0x0168, 0x908e, 0x003d, 0x0150, 0x001e, 0xa86b, - 0x0103, 0xa833, 0x0100, 0x001e, 0x002e, 0x009e, 0x00ee, 0x0005, - 0x001e, 0x0009, 0x0cc0, 0x0096, 0x6014, 0x2048, 0xa800, 0x2048, - 0xa86b, 0x0103, 0xa823, 0x8001, 0x009e, 0x0005, 0x00b6, 0x6610, - 0x2658, 0xb804, 0x9084, 0x00ff, 0x90b2, 0x000c, 0x1a0c, 0x0dcc, - 0x6604, 0x96b6, 0x004d, 0x1120, 0x080c, 0xd906, 0x0804, 0xc04b, - 0x6604, 0x96b6, 0x0043, 0x1120, 0x080c, 0xd94f, 0x0804, 0xc04b, - 0x6604, 0x96b6, 0x004b, 0x1120, 0x080c, 0xd97b, 0x0804, 0xc04b, - 0x6604, 0x96b6, 0x0033, 0x1120, 0x080c, 0xd898, 0x0804, 0xc04b, - 0x6604, 0x96b6, 0x0028, 0x1120, 0x080c, 0xd64d, 0x0804, 0xc04b, - 0x6604, 0x96b6, 0x0029, 0x1120, 0x080c, 0xd68e, 0x0804, 0xc04b, - 0x6604, 0x96b6, 0x001f, 0x1120, 0x080c, 0xb910, 0x0804, 0xc04b, - 0x6604, 0x96b6, 0x0000, 0x1118, 0x080c, 0xbcc2, 0x04e0, 0x6604, - 0x96b6, 0x0022, 0x1118, 0x080c, 0xb9a4, 0x04a8, 0x6604, 0x96b6, - 0x0035, 0x1118, 0x080c, 0xbad2, 0x0470, 0x6604, 0x96b6, 0x0039, - 0x1118, 0x080c, 0xbc5b, 0x0438, 0x6604, 0x96b6, 0x003d, 0x1118, - 0x080c, 0xb9dc, 0x0400, 0x6604, 0x96b6, 0x0044, 0x1118, 0x080c, - 0xba18, 0x00c8, 0x6604, 0x96b6, 0x0049, 0x1118, 0x080c, 0xba5d, - 0x0090, 0x6604, 0x96b6, 0x0041, 0x1118, 0x080c, 0xba47, 0x0058, - 0x91b6, 0x0015, 0x1110, 0x0063, 0x0030, 0x91b6, 0x0016, 0x1128, - 0x00be, 0x0804, 0xc358, 0x00be, 0x0005, 0x080c, 0xb5d4, 0x0cd8, - 0xc069, 0xc077, 0xc069, 0xc0be, 0xc069, 0xc275, 0xc365, 0xc069, - 0xc069, 0xc069, 0xc32e, 0xc069, 0xc344, 0x0096, 0x601f, 0x0000, - 0x6014, 0x2048, 0xa800, 0x2048, 0xa86b, 0x0103, 0x009e, 0x0804, - 0xb53c, 0xa001, 0xa001, 0x0005, 0x6604, 0x96b6, 0x0004, 0x1130, - 0x2001, 0x0001, 0x080c, 0x67bb, 0x0804, 0xb53c, 0x0005, 0x00e6, - 0x2071, 0x1800, 0x7090, 0x9086, 0x0074, 0x1540, 0x080c, 0xecb9, - 0x11b0, 0x6010, 0x00b6, 0x2058, 0x7030, 0xd08c, 0x0128, 0xb800, - 0xd0bc, 0x0110, 0xc0c5, 0xb802, 0x00f9, 0x00be, 0x2001, 0x0006, - 0x080c, 0x67cf, 0x080c, 0x3334, 0x080c, 0xb53c, 0x0098, 0x2001, - 0x000a, 0x080c, 0x67cf, 0x080c, 0x3334, 0x6003, 0x0001, 0x6007, - 0x0001, 0x080c, 0x977c, 0x080c, 0x9ce8, 0x0020, 0x2001, 0x0001, - 0x080c, 0xc245, 0x00ee, 0x0005, 0x00d6, 0xb800, 0xd084, 0x0160, - 0x9006, 0x080c, 0x67bb, 0x2069, 0x184a, 0x6804, 0xd0a4, 0x0120, - 0x2001, 0x0006, 0x080c, 0x67fb, 0x00de, 0x0005, 0x00b6, 0x0096, - 0x00d6, 0x2011, 0x1824, 0x2204, 0x9086, 0x0074, 0x1904, 0xc21a, - 0x6010, 0x2058, 0xbaa0, 0x9286, 0x007e, 0x1120, 0x080c, 0xc4b4, - 0x0804, 0xc187, 0x2001, 0x180d, 0x2004, 0xd08c, 0x0904, 0xc129, - 0x00d6, 0x080c, 0x77ff, 0x01a0, 0x0026, 0x2011, 0x0010, 0x080c, - 0x6c96, 0x002e, 0x0904, 0xc128, 0x080c, 0x5973, 0x1598, 0x6014, - 0x2048, 0xa807, 0x0000, 0xa86b, 0x0103, 0xa833, 0xdead, 0x0450, - 0x6010, 0x00b6, 0x2058, 0xb910, 0x00be, 0x9186, 0x00ff, 0x0580, - 0x0026, 0x2011, 0x8008, 0x080c, 0x6c96, 0x002e, 0x0548, 0x6014, - 0x9005, 0x090c, 0x0dcc, 0x2048, 0xa868, 0x9084, 0x00ff, 0x9086, - 0x0039, 0x1140, 0x2001, 0x0030, 0x900e, 0x2011, 0x4009, 0x080c, - 0xd9e7, 0x0040, 0x6014, 0x2048, 0xa807, 0x0000, 0xa86b, 0x0103, - 0xa833, 0xdead, 0x6010, 0x2058, 0xb9a0, 0x0016, 0x080c, 0x3334, - 0x080c, 0xb53c, 0x001e, 0x080c, 0x3407, 0x00de, 0x0804, 0xc21f, - 0x00de, 0x080c, 0xc4a9, 0x6010, 0x2058, 0xbaa0, 0x9286, 0x0080, - 0x1510, 0x6014, 0x9005, 0x01a8, 0x2048, 0xa868, 0x9084, 0x00ff, - 0x9086, 0x0039, 0x1140, 0x2001, 0x0000, 0x900e, 0x2011, 0x4000, - 0x080c, 0xd9e7, 0x0030, 0xa807, 0x0000, 0xa86b, 0x0103, 0xa833, - 0x0200, 0x2001, 0x0006, 0x080c, 0x67cf, 0x080c, 0x3334, 0x080c, - 0xb53c, 0x0804, 0xc21f, 0x080c, 0xc22d, 0x6014, 0x9005, 0x0190, - 0x2048, 0xa86c, 0xd0f4, 0x01e8, 0xa868, 0x9084, 0x00ff, 0x9086, - 0x0039, 0x1d08, 0x2001, 0x0000, 0x900e, 0x2011, 0x4000, 0x080c, - 0xd9e7, 0x08f8, 0x080c, 0xc223, 0x0160, 0x9006, 0x080c, 0x67bb, - 0x2001, 0x0004, 0x080c, 0x67fb, 0x2001, 0x0007, 0x080c, 0x67cf, - 0x08a0, 0x2001, 0x0004, 0x080c, 0x67cf, 0x6003, 0x0001, 0x6007, - 0x0003, 0x080c, 0x977c, 0x080c, 0x9ce8, 0x0804, 0xc21f, 0xb85c, - 0xd0e4, 0x0178, 0x080c, 0xd818, 0x080c, 0x77ff, 0x0118, 0xd0dc, - 0x1904, 0xc149, 0x2011, 0x1837, 0x2204, 0xc0ad, 0x2012, 0x0804, - 0xc149, 0x080c, 0xd855, 0x2011, 0x1837, 0x2204, 0xc0a5, 0x2012, - 0x0006, 0x080c, 0xee95, 0x000e, 0x1904, 0xc149, 0xc0b5, 0x2012, - 0x2001, 0x0006, 0x080c, 0x67cf, 0x9006, 0x080c, 0x67bb, 0x00c6, - 0x2001, 0x180f, 0x2004, 0xd09c, 0x0520, 0x00f6, 0x2079, 0x0100, - 0x00e6, 0x2071, 0x1800, 0x700c, 0x9084, 0x00ff, 0x78e6, 0x707e, - 0x7010, 0x78ea, 0x7082, 0x908c, 0x00ff, 0x00ee, 0x780c, 0xc0b5, - 0x780e, 0x00fe, 0x080c, 0x2931, 0x00f6, 0x2100, 0x900e, 0x080c, - 0x28e8, 0x795e, 0x00fe, 0x9186, 0x0081, 0x01f0, 0x2009, 0x0081, - 0x00e0, 0x2009, 0x00ef, 0x00f6, 0x2079, 0x0100, 0x79ea, 0x78e7, - 0x0000, 0x7932, 0x7936, 0x780c, 0xc0b5, 0x780e, 0x00fe, 0x080c, - 0x2931, 0x00f6, 0x2079, 0x1800, 0x7982, 0x2100, 0x900e, 0x797e, - 0x080c, 0x28e8, 0x795e, 0x00fe, 0x8108, 0x080c, 0x681e, 0x2b00, - 0x00ce, 0x1904, 0xc149, 0x6012, 0x2009, 0x180f, 0x210c, 0xd19c, - 0x0150, 0x2009, 0x027c, 0x210c, 0x918c, 0x00ff, 0xb912, 0x2009, - 0x027d, 0x210c, 0xb916, 0x2001, 0x0002, 0x080c, 0x67cf, 0x6023, - 0x0001, 0x6003, 0x0001, 0x6007, 0x0002, 0x080c, 0x977c, 0x080c, - 0x9ce8, 0x0028, 0x080c, 0xbf7f, 0x2001, 0x0001, 0x0431, 0x00de, - 0x009e, 0x00be, 0x0005, 0x2001, 0x1810, 0x2004, 0xd0a4, 0x0120, - 0x2001, 0x184b, 0x2004, 0xd0ac, 0x0005, 0x00e6, 0x080c, 0xf3da, - 0x0190, 0x2071, 0x0260, 0x7108, 0x720c, 0x918c, 0x00ff, 0x1118, - 0x9284, 0xff00, 0x0140, 0x6010, 0x2058, 0xb8a0, 0x9084, 0xff80, - 0x1110, 0xb912, 0xba16, 0x00ee, 0x0005, 0x2030, 0x9005, 0x0158, - 0x2001, 0x0007, 0x080c, 0x67cf, 0x080c, 0x5973, 0x1120, 0x2001, - 0x0007, 0x080c, 0x67fb, 0x2600, 0x9005, 0x11b0, 0x6014, 0x0096, - 0x2048, 0xa86c, 0x009e, 0xd0fc, 0x1178, 0x0036, 0x0046, 0x6010, - 0x00b6, 0x2058, 0xbba0, 0x00be, 0x2021, 0x0004, 0x2011, 0x8014, - 0x080c, 0x4dbf, 0x004e, 0x003e, 0x080c, 0x3334, 0x6020, 0x9086, - 0x000a, 0x1108, 0x0005, 0x0804, 0xb53c, 0x00b6, 0x00e6, 0x0026, - 0x0016, 0x2071, 0x1800, 0x7090, 0x9086, 0x0014, 0x1904, 0xc324, - 0x2001, 0x180d, 0x2004, 0xd08c, 0x0904, 0xc2d7, 0x00d6, 0x080c, - 0x77ff, 0x01a0, 0x0026, 0x2011, 0x0010, 0x080c, 0x6c96, 0x002e, - 0x0904, 0xc2d6, 0x080c, 0x5973, 0x1598, 0x6014, 0x2048, 0xa807, - 0x0000, 0xa86b, 0x0103, 0xa833, 0xdead, 0x0450, 0x6010, 0x00b6, - 0x2058, 0xb910, 0x00be, 0x9186, 0x00ff, 0x0580, 0x0026, 0x2011, - 0x8008, 0x080c, 0x6c96, 0x002e, 0x0548, 0x6014, 0x9005, 0x090c, - 0x0dcc, 0x2048, 0xa868, 0x9084, 0x00ff, 0x9086, 0x0039, 0x1140, - 0x2001, 0x0030, 0x900e, 0x2011, 0x4009, 0x080c, 0xd9e7, 0x0040, - 0x6014, 0x2048, 0xa807, 0x0000, 0xa86b, 0x0103, 0xa833, 0xdead, - 0x6010, 0x2058, 0xb9a0, 0x0016, 0x080c, 0x3334, 0x080c, 0xb53c, - 0x001e, 0x080c, 0x3407, 0x00de, 0x0804, 0xc329, 0x00de, 0x080c, - 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0x1220, 0x9182, 0x0040, 0x0208, 0x000a, 0x0005, 0xccf2, 0xccf2, - 0xccf2, 0xccf2, 0xccf2, 0xccf4, 0xccf2, 0xccf2, 0xccf2, 0xccf2, - 0xccf2, 0xccf2, 0xccf2, 0xccf2, 0xccf2, 0xccf2, 0xccf2, 0xccf2, - 0xccf2, 0xccf2, 0x080c, 0x0dcc, 0x080c, 0x5967, 0x0528, 0x7144, - 0x918c, 0x0fff, 0x0066, 0x2130, 0x080c, 0xdb72, 0x006e, 0x11f0, - 0x6014, 0x9016, 0xd1c4, 0x0118, 0x7264, 0x9294, 0x00ff, 0x0096, - 0x904d, 0x0188, 0xa87f, 0x0000, 0xa868, 0x9086, 0x0139, 0x0128, - 0xa86b, 0x0103, 0xa97a, 0xaa9a, 0x0030, 0xa89b, 0x4000, 0xa99e, - 0xaaa2, 0x080c, 0x706e, 0x009e, 0x0804, 0xb53c, 0x0005, 0x9182, - 0x0085, 0x0002, 0xcd31, 0xcd2f, 0xcd2f, 0xcd3d, 0xcd2f, 0xcd2f, - 0xcd2f, 0xcd2f, 0xcd2f, 0xcd2f, 0xcd2f, 0xcd2f, 0xcd2f, 0x080c, - 0x0dcc, 0x6003, 0x0001, 0x6106, 0x080c, 0x9734, 0x0126, 0x2091, - 0x8000, 0x080c, 0x9ce8, 0x012e, 0x0005, 0x0026, 0x0056, 0x00d6, - 0x00e6, 0x2071, 0x0260, 0x7224, 0x6216, 0x7220, 0x080c, 0xd3e3, - 0x01f8, 0x2268, 0x6800, 0x9086, 0x0000, 0x01d0, 0x6010, 0x6d10, - 0x952e, 0x11b0, 0x00c6, 0x2d60, 0x00d6, 0x080c, 0xcffe, 0x00de, - 0x00ce, 0x0158, 0x702c, 0xd084, 0x1118, 0x080c, 0xcfa6, 0x0010, - 0x6803, 0x0002, 0x6007, 0x0086, 0x0028, 0x080c, 0xcfea, 0x0d90, - 0x6007, 0x0087, 0x6003, 0x0001, 0x080c, 0x9734, 0x080c, 0x9ce8, - 0x7220, 0x080c, 0xd3e3, 0x0178, 0x6810, 0x00b6, 0x2058, 0xb800, - 0x00be, 0xd0bc, 0x0140, 0x6824, 0xd0ec, 0x0128, 0x00c6, 0x2d60, - 0x080c, 0xd73c, 0x00ce, 0x00ee, 0x00de, 0x005e, 0x002e, 0x0005, - 0x9186, 0x0013, 0x1160, 0x6004, 0x908a, 0x0085, 0x0a0c, 0x0dcc, - 0x908a, 0x0092, 0x1a0c, 0x0dcc, 0x9082, 0x0085, 0x00e2, 0x9186, - 0x0027, 0x0120, 0x9186, 0x0014, 0x0108, 0x0005, 0x080c, 0x9bda, - 0x0096, 0x6014, 0x2048, 0x080c, 0xd3f5, 0x0140, 0xa86b, 0x0103, - 0xa87b, 0x0000, 0xa87f, 0x0029, 0x080c, 0x706e, 0x009e, 0x080c, - 0xb56f, 0x0804, 0x9ce8, 0xcdc0, 0xcdc2, 0xcdc2, 0xcdc0, 0xcdc0, - 0xcdc0, 0xcdc0, 0xcdc0, 0xcdc0, 0xcdc0, 0xcdc0, 0xcdc0, 0xcdc0, - 0x080c, 0x0dcc, 0x080c, 0x9bda, 0x080c, 0xb56f, 0x080c, 0x9ce8, - 0x0005, 0x9186, 0x0013, 0x1128, 0x6004, 0x9082, 0x0085, 0x2008, - 0x04b8, 0x9186, 0x0027, 0x11f8, 0x080c, 0x9bda, 0x080c, 0x330b, - 0x080c, 0xdb21, 0x0096, 0x6014, 0x2048, 0x080c, 0xd3f5, 0x0150, - 0xa86b, 0x0103, 0xa87b, 0x0000, 0xa87f, 0x0029, 0x080c, 0x706e, - 0x080c, 0xd5f2, 0x009e, 0x080c, 0xb53c, 0x080c, 0x9ce8, 0x0005, - 0x080c, 0xb5d4, 0x0ce0, 0x9186, 0x0014, 0x1dd0, 0x080c, 0x9bda, - 0x0096, 0x6014, 0x2048, 0x080c, 0xd3f5, 0x0d60, 0xa86b, 0x0103, - 0xa87b, 0x0000, 0xa87f, 0x0006, 0xa884, 0xc0ec, 0xa886, 0x08f0, - 0x0002, 0xce18, 0xce16, 0xce16, 0xce16, 0xce16, 0xce16, 0xce30, - 0xce16, 0xce16, 0xce16, 0xce16, 0xce16, 0xce16, 0x080c, 0x0dcc, - 0x080c, 0x9bda, 0x6034, 0x908c, 0xff00, 0x810f, 0x9186, 0x0039, - 0x0118, 0x9186, 0x0035, 0x1118, 0x2001, 0x1989, 0x0010, 0x2001, - 0x198a, 0x2004, 0x601a, 0x6003, 0x000c, 0x080c, 0x9ce8, 0x0005, - 0x080c, 0x9bda, 0x6034, 0x908c, 0xff00, 0x810f, 0x9186, 0x0039, - 0x0118, 0x9186, 0x0035, 0x1118, 0x2001, 0x1989, 0x0010, 0x2001, - 0x198a, 0x2004, 0x601a, 0x6003, 0x000e, 0x080c, 0x9ce8, 0x0005, - 0x9182, 0x0092, 0x1220, 0x9182, 0x0085, 0x0208, 0x0012, 0x0804, - 0xb5d4, 0xce5e, 0xce5e, 0xce5e, 0xce5e, 0xce60, 0xce97, 0xce5e, - 0xce5e, 0xce5e, 0xce5e, 0xce5e, 0xce5e, 0xce5e, 0x080c, 0x0dcc, - 0x0096, 0x6010, 0x00b6, 0x2058, 0xb800, 0x00be, 0xd0bc, 0x0160, - 0x6034, 0x908c, 0xff00, 0x810f, 0x9186, 0x0039, 0x0118, 0x9186, - 0x0035, 0x1110, 0x009e, 0x04b8, 0x080c, 0xd3f5, 0x1118, 0x080c, - 0xd5f2, 0x0068, 0x6014, 0x2048, 0xa880, 0xd0e4, 0x1110, 0x080c, - 0xd5f2, 0xa86b, 0x0103, 0x080c, 0xdae7, 0x080c, 0x706e, 0x2009, - 0x026e, 0x210c, 0x613a, 0x2009, 0x026f, 0x210c, 0x613e, 0x6000, - 0x6036, 0x6003, 0x0013, 0x080c, 0xb56f, 0x009e, 0x0005, 0x6010, - 0x00b6, 0x2058, 0xb800, 0x00be, 0xd0bc, 0x05a0, 0x6034, 0x908c, - 0xff00, 0x810f, 0x9186, 0x0035, 0x0130, 0x9186, 0x001e, 0x0118, - 0x9186, 0x0039, 0x1538, 0x00d6, 0x2c68, 0x080c, 0xda7d, 0x11f0, - 0x080c, 0xb4e6, 0x01d8, 0x6106, 0x6003, 0x0001, 0x6023, 0x0001, - 0x6910, 0x6112, 0x692c, 0x612e, 0x6930, 0x6132, 0x6934, 0x918c, - 0x00ff, 0x6136, 0x6938, 0x613a, 0x693c, 0x613e, 0x6954, 0x6156, - 0x080c, 0xd87e, 0x080c, 0x9734, 0x080c, 0x9ce8, 0x2d60, 0x00de, - 0x0804, 0xb53c, 0x0096, 0x6014, 0x2048, 0x080c, 0xd3f5, 0x01c8, - 0xa86b, 0x0103, 0xa884, 0xd0b4, 0x0128, 0xc0ec, 0xa886, 0xa87f, - 0x0006, 0x0048, 0xd0bc, 0x0118, 0xa87f, 0x0002, 0x0020, 0xa87f, - 0x0005, 0x080c, 0xd6fe, 0xa87b, 0x0000, 0x080c, 0x706e, 0x080c, - 0xd5f2, 0x009e, 0x0804, 0xb53c, 0x0016, 0x0096, 0x6014, 0x2048, - 0x080c, 0xd3f5, 0x0140, 0xa86b, 0x0103, 0xa87f, 0x0028, 0xa87b, - 0x0000, 0x080c, 0x706e, 0x009e, 0x001e, 0x9186, 0x0013, 0x0148, - 0x9186, 0x0014, 0x0130, 0x9186, 0x0027, 0x0118, 0x080c, 0xb5d4, - 0x0030, 0x080c, 0x9bda, 0x080c, 0xb56f, 0x080c, 0x9ce8, 0x0005, - 0x0056, 0x0066, 0x0096, 0x00a6, 0x2029, 0x0001, 0x9182, 0x0101, - 0x1208, 0x0010, 0x2009, 0x0100, 0x2130, 0x8304, 0x9098, 0x0018, - 0x2009, 0x0020, 0x2011, 0x002a, 0x080c, 0xcf79, 0x96b2, 0x0020, - 0xb004, 0x904d, 0x0110, 0x080c, 0x0fc8, 0x080c, 0x1016, 0x0520, - 0x8528, 0xa86b, 0x0110, 0xa86f, 0x0000, 0x2920, 0xb406, 0x968a, - 0x003d, 0x1228, 0x2608, 0x2011, 0x001c, 0x0499, 0x00a8, 0x96b2, - 0x003c, 0x2009, 0x003c, 0x2950, 0x2011, 0x001c, 0x0451, 0x0c28, - 0x2001, 0x0205, 0x2003, 0x0000, 0x00ae, 0x852f, 0x95ad, 0x0003, - 0xb56a, 0x95ac, 0x0000, 0x0048, 0x2001, 0x0205, 0x2003, 0x0000, - 0x00ae, 0x852f, 0x95ad, 0x0003, 0xb56a, 0x009e, 0x006e, 0x005e, - 0x0005, 0x00a6, 0x89ff, 0x0158, 0xa804, 0x9055, 0x0130, 0xa807, - 0x0000, 0x080c, 0x706e, 0x2a48, 0x0cb8, 0x080c, 0x706e, 0x00ae, - 0x0005, 0x00f6, 0x2079, 0x0200, 0x7814, 0x9085, 0x0080, 0x7816, - 0xd184, 0x0108, 0x8108, 0x810c, 0x20a9, 0x0001, 0xa860, 0x20e8, - 0xa85c, 0x9200, 0x20a0, 0x20e1, 0x0000, 0x2300, 0x9e00, 0x2098, - 0x4003, 0x8318, 0x9386, 0x0020, 0x1148, 0x2018, 0x2300, 0x9e00, - 0x2098, 0x7814, 0x8000, 0x9085, 0x0080, 0x7816, 0x8109, 0x1d80, - 0x7814, 0x9084, 0xff7f, 0x7816, 0x00fe, 0x0005, 0x6920, 0x9186, - 0x0003, 0x0148, 0x9186, 0x0002, 0x0130, 0x9186, 0x0008, 0x0118, - 0x9186, 0x000a, 0x1510, 0x00c6, 0x00d6, 0x00e6, 0x2d60, 0x0096, - 0x6014, 0x2048, 0x080c, 0xd3f5, 0x0190, 0x6120, 0x9186, 0x000a, - 0x01a8, 0x9186, 0x0008, 0x01b8, 0x00c9, 0x2001, 0x0006, 0xa984, - 0xc1d5, 0x080c, 0x72d6, 0x080c, 0x7061, 0x080c, 0xd5f2, 0x009e, - 0x080c, 0xb56f, 0x00ee, 0x00de, 0x00ce, 0x0005, 0xa87f, 0x0013, - 0x080c, 0x706e, 0x0ca0, 0x080c, 0xbf7f, 0x0c88, 0xa880, 0xd0cc, - 0x0140, 0x0096, 0xa87c, 0x2048, 0x080c, 0x0fc8, 0x009e, 0xa87f, - 0x0000, 0x0005, 0x00c6, 0x702c, 0xd084, 0x1170, 0x6008, 0x2060, - 0x6020, 0x9086, 0x0002, 0x1140, 0x6104, 0x9186, 0x0085, 0x0118, - 0x9186, 0x008b, 0x1108, 0x9006, 0x00ce, 0x0005, 0x0066, 0x0126, - 0x2091, 0x8000, 0x2031, 0x0001, 0x6020, 0x9084, 0x000f, 0x0083, - 0x012e, 0x006e, 0x0005, 0x0126, 0x2091, 0x8000, 0x0066, 0x2031, - 0x0000, 0x6020, 0x9084, 0x000f, 0x001b, 0x006e, 0x012e, 0x0005, - 0xd035, 0xd035, 0xd030, 0xd057, 0xd027, 0xd030, 0xd057, 0xd030, - 0xdb9b, 0x94bf, 0xee4f, 0xd030, 0xd030, 0xd027, 0xd027, 0x080c, - 0x0dcc, 0x0036, 0x2019, 0x0010, 0x080c, 0xeb0e, 0x003e, 0x0005, - 0x9006, 0x0005, 0x9085, 0x0001, 0x0005, 0x0096, 0x86ff, 0x11d8, - 0x6014, 0x2048, 0x080c, 0xd3f5, 0x01c0, 0xa868, 0x9086, 0x0139, - 0x1128, 0xa87f, 0x0005, 0xa887, 0x0000, 0x0028, 0x900e, 0x2001, - 0x0005, 0x080c, 0x72d6, 0x080c, 0xd6fe, 0x080c, 0x7061, 0x080c, - 0xb56f, 0x9085, 0x0001, 0x009e, 0x0005, 0x9006, 0x0ce0, 0x6000, - 0x908a, 0x0014, 0x1a0c, 0x0dcc, 0x0002, 0xd06d, 0xd09d, 0xd06f, - 0xd0be, 0xd098, 0xd06d, 0xd030, 0xd035, 0xd035, 0xd030, 0xd030, - 0xd030, 0xd030, 0xd030, 0xd030, 0xd030, 0x080c, 0x0dcc, 0x86ff, - 0x1520, 0x6020, 0x9086, 0x0006, 0x0500, 0x0096, 0x6014, 0x2048, - 0x080c, 0xd3f5, 0x0168, 0xa880, 0xd0cc, 0x0140, 0x0096, 0xc0cc, - 0xa882, 0xa87c, 0x2048, 0x080c, 0x0fc8, 0x009e, 0x080c, 0xd6fe, - 0x009e, 0x080c, 0xdac1, 0x6007, 0x0085, 0x6003, 0x000b, 0x6023, - 0x0002, 0x080c, 0x9734, 0x080c, 0x9ce8, 0x9085, 0x0001, 0x0005, - 0x0066, 0x080c, 0x1aea, 0x006e, 0x0890, 0x00e6, 0x2071, 0x19eb, - 0x7024, 0x9c06, 0x1120, 0x080c, 0xac20, 0x00ee, 0x0840, 0x6020, - 0x9084, 0x000f, 0x9086, 0x0006, 0x1150, 0x0086, 0x0096, 0x2049, - 0x0001, 0x2c40, 0x080c, 0xad48, 0x009e, 0x008e, 0x0010, 0x080c, - 0xab1d, 0x00ee, 0x1904, 0xd06f, 0x0804, 0xd030, 0x0036, 0x00e6, - 0x2071, 0x19eb, 0x703c, 0x9c06, 0x1138, 0x901e, 0x080c, 0xac96, - 0x00ee, 0x003e, 0x0804, 0xd06f, 0x080c, 0xae78, 0x00ee, 0x003e, - 0x1904, 0xd06f, 0x0804, 0xd030, 0x00c6, 0x6020, 0x9084, 0x000f, - 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0xdbd9, 0x080c, 0x0dcc, 0x0066, 0x6000, 0x90b2, 0x0014, 0x1a0c, - 0x0dcc, 0x0013, 0x006e, 0x0005, 0xdbf4, 0xea9d, 0xdbf4, 0xdbf4, - 0xdbf4, 0xdbf4, 0xdbf4, 0xdbf4, 0xea4a, 0xeaf1, 0xdbf4, 0xf18c, - 0xf1c2, 0xf18c, 0xf1c2, 0xdbf4, 0x080c, 0x0dcc, 0x6000, 0x9082, - 0x0014, 0x1a0c, 0x0dcc, 0x6000, 0x000a, 0x0005, 0xdc0e, 0xe72c, - 0xe7fb, 0xe81e, 0xe8de, 0xdc0e, 0xe9bd, 0xe966, 0xe55b, 0xea20, - 0xea35, 0xdc0e, 0xdc0e, 0xdc0e, 0xdc0e, 0xdc0e, 0x080c, 0x0dcc, - 0x91b2, 0x0054, 0x1a0c, 0x0dcc, 0x2100, 0x91b2, 0x0040, 0x1a04, - 0xe0ae, 0x0002, 0xdc5a, 0xde6e, 0xdc5a, 0xdc5a, 0xdc5a, 0xde77, - 0xdc5a, 0xdc5a, 0xdc5a, 0xdc5a, 0xdc5a, 0xdc5a, 0xdc5a, 0xdc5a, - 0xdc5a, 0xdc5a, 0xdc5a, 0xdc5a, 0xdc5a, 0xdc5a, 0xdc5a, 0xdc5a, - 0xdc5a, 0xdc5c, 0xdcbf, 0xdcce, 0xdd37, 0xdd6d, 0xdde6, 0xde59, - 0xdc5a, 0xdc5a, 0xde7a, 0xdc5a, 0xdc5a, 0xde8f, 0xde9c, 0xdc5a, - 0xdc5a, 0xdc5a, 0xdc5a, 0xdc5a, 0xdf42, 0xdc5a, 0xdc5a, 0xdf56, - 0xdc5a, 0xdc5a, 0xdf11, 0xdc5a, 0xdc5a, 0xdc5a, 0xdf6e, 0xdc5a, - 0xdc5a, 0xdc5a, 0xdfeb, 0xdc5a, 0xdc5a, 0xdc5a, 0xdc5a, 0xdc5a, - 0xdc5a, 0xe076, 0x080c, 0x0dcc, 0x080c, 0x6c19, 0x1150, 0x2001, - 0x1837, 0x2004, 0xd0cc, 0x1128, 0x9084, 0x0009, 0x9086, 0x0008, - 0x1140, 0x6007, 0x0009, 0x602f, 0x0009, 0x6017, 0x0000, 0x0804, - 0xde67, 0x080c, 0x6bb5, 0x00e6, 0x00c6, 0x0036, 0x0026, 0x0016, - 0x6210, 0x2258, 0xbaa0, 0x0026, 0x2019, 0x0029, 0x080c, 0x98d9, - 0x0076, 0x903e, 0x080c, 0x97ac, 0x2c08, 0x080c, 0xece8, 0x007e, - 0x001e, 0x001e, 0x002e, 0x003e, 0x00ce, 0x00ee, 0x6610, 0x2658, - 0x080c, 0x689f, 0xbe04, 0x9684, 0x00ff, 0x9082, 0x0006, 0x1268, - 0x0016, 0x0026, 0x6210, 0x00b6, 0x2258, 0xbaa0, 0x00be, 0x2c08, - 0x080c, 0xf402, 0x002e, 0x001e, 0x1178, 0x080c, 0xec1a, 0x1904, - 0xdd2f, 0x080c, 0xebb2, 0x1120, 0x6007, 0x0008, 0x0804, 0xde67, - 0x6007, 0x0009, 0x0804, 0xde67, 0x080c, 0xee95, 0x0128, 0x080c, - 0xec1a, 0x0d78, 0x0804, 0xdd2f, 0x6017, 0x1900, 0x0c88, 0x080c, - 0x342f, 0x1904, 0xe0ab, 0x6106, 0x080c, 0xeb56, 0x6007, 0x0006, - 0x0804, 0xde67, 0x6007, 0x0007, 0x0804, 0xde67, 0x080c, 0xf1fe, - 0x1904, 0xe0ab, 0x080c, 0x342f, 0x1904, 0xe0ab, 0x00d6, 0x6610, - 0x2658, 0xbe04, 0x9684, 0x00ff, 0x9082, 0x0006, 0x1220, 0x2001, - 0x0001, 0x080c, 0x67bb, 0x96b4, 0xff00, 0x8637, 0x9686, 0x0006, - 0x0188, 0x9686, 0x0004, 0x0170, 0xbe04, 0x96b4, 0x00ff, 0x9686, - 0x0006, 0x0140, 0x9686, 0x0004, 0x0128, 0x9686, 0x0005, 0x0110, - 0x00de, 0x04a8, 0x00e6, 0x2071, 0x0260, 0x7034, 0x9084, 0x0003, - 0x1168, 0x7034, 0x908a, 0x0014, 0x0248, 0x2009, 0x1824, 0x210c, - 0x9102, 0x0220, 0x7030, 0x9084, 0x0003, 0x0130, 0x00ee, 0x6017, - 0x0000, 0x602f, 0x0007, 0x00b0, 0x00ee, 0x080c, 0xec7e, 0x1190, - 0x9686, 0x0006, 0x1140, 0x0026, 0x6210, 0x2258, 0xbaa0, 0x900e, - 0x080c, 0x3354, 0x002e, 0x080c, 0x692b, 0x6007, 0x000a, 0x00de, - 0x0804, 0xde67, 0x6007, 0x000b, 0x00de, 0x0804, 0xde67, 0x080c, - 0x330b, 0x080c, 0xdb21, 0x6007, 0x0001, 0x0804, 0xde67, 0x080c, - 0xf1fe, 0x1904, 0xe0ab, 0x080c, 0x342f, 0x1904, 0xe0ab, 0x00d6, - 0x00e6, 0x2071, 0x0260, 0x7034, 0x90b4, 0x0003, 0x1938, 0x2031, - 0x1824, 0x2634, 0x9632, 0x0a10, 0x90b2, 0x0014, 0x0a04, 0xdd0e, - 0x7030, 0x9084, 0x0003, 0x1904, 0xdd0e, 0x00ee, 0x00de, 0x6610, - 0x2658, 0xbe04, 0x9686, 0x0707, 0x0990, 0x0026, 0x6210, 0x2258, - 0xbaa0, 0x900e, 0x080c, 0x3354, 0x002e, 0x6007, 0x000c, 0x2001, - 0x0001, 0x080c, 0xf3e1, 0x0804, 0xde67, 0x080c, 0x6c19, 0x1140, - 0x2001, 0x1837, 0x2004, 0x9084, 0x0009, 0x9086, 0x0008, 0x1110, - 0x0804, 0xdc69, 0x080c, 0x6bb5, 0x6610, 0x2658, 0xbe04, 0x9684, - 0x00ff, 0x9082, 0x0006, 0x06c8, 0x1138, 0x0026, 0x2001, 0x0006, - 0x080c, 0x67fb, 0x002e, 0x0050, 0x96b4, 0xff00, 0x8637, 0x9686, - 0x0004, 0x0120, 0x9686, 0x0006, 0x1904, 0xdd2f, 0x080c, 0xec8b, - 0x1120, 0x6007, 0x000e, 0x0804, 0xde67, 0x0046, 0x6410, 0x2458, - 0xbca0, 0x0046, 0x080c, 0x330b, 0x080c, 0xdb21, 0x004e, 0x0016, - 0x9006, 0x2009, 0x184b, 0x210c, 0xd1a4, 0x0148, 0x2009, 0x0029, - 0x080c, 0xf00a, 0x6010, 0x2058, 0xb800, 0xc0e5, 0xb802, 0x001e, - 0x004e, 0x6007, 0x0001, 0x0804, 0xde67, 0x2001, 0x0001, 0x080c, - 0x67bb, 0x0156, 0x0016, 0x0026, 0x0036, 0x20a9, 0x0004, 0x2019, - 0x1805, 0x2011, 0x0270, 0x080c, 0xc64d, 0x003e, 0x002e, 0x001e, - 0x015e, 0x9005, 0x0168, 0x96b4, 0xff00, 0x8637, 0x9682, 0x0004, - 0x0a04, 0xdd2f, 0x9682, 0x0007, 0x0a04, 0xdd96, 0x0804, 0xdd2f, - 0x6017, 0x1900, 0x6007, 0x0009, 0x0804, 0xde67, 0x080c, 0x6c19, - 0x1140, 0x2001, 0x1837, 0x2004, 0x9084, 0x0009, 0x9086, 0x0008, - 0x1110, 0x0804, 0xdc69, 0x080c, 0x6bb5, 0x6610, 0x2658, 0xbe04, - 0x9684, 0x00ff, 0x0006, 0x0016, 0x908e, 0x0001, 0x0118, 0x908e, - 0x0000, 0x1118, 0x001e, 0x000e, 0x0080, 0x001e, 0x000e, 0x9082, - 0x0006, 0x06a0, 0x0150, 0x96b4, 0xff00, 0x8637, 0x9686, 0x0004, - 0x0120, 0x9686, 0x0006, 0x1904, 0xdd2f, 0x080c, 0xecb9, 0x1138, - 0x080c, 0xebb2, 0x1120, 0x6007, 0x0010, 0x0804, 0xde67, 0x0046, - 0x6410, 0x2458, 0xbca0, 0x0046, 0x080c, 0x330b, 0x080c, 0xdb21, - 0x004e, 0x0016, 0x9006, 0x2009, 0x184b, 0x210c, 0xd1a4, 0x0148, - 0x2009, 0x0029, 0x080c, 0xf00a, 0x6010, 0x2058, 0xb800, 0xc0e5, - 0xb802, 0x001e, 0x004e, 0x6007, 0x0001, 0x0448, 0x080c, 0xee95, - 0x0198, 0x0016, 0x968c, 0x00ff, 0x9186, 0x0002, 0x0160, 0x9186, - 0x0003, 0x0148, 0x001e, 0x96b4, 0xff00, 0x8637, 0x9686, 0x0006, - 0x0920, 0x0804, 0xdd2f, 0x001e, 0x6017, 0x1900, 0x6007, 0x0009, - 0x0070, 0x080c, 0x342f, 0x1904, 0xe0ab, 0x080c, 0xf1fe, 0x1904, - 0xe0ab, 0x080c, 0xe28c, 0x1904, 0xdd2f, 0x6007, 0x0012, 0x6003, - 0x0001, 0x080c, 0x977c, 0x080c, 0x9ce8, 0x0005, 0x6007, 0x0001, - 0x6003, 0x0001, 0x080c, 0x977c, 0x080c, 0x9ce8, 0x0cb0, 0x6007, - 0x0005, 0x0c68, 0x080c, 0xf1fe, 0x1904, 0xe0ab, 0x080c, 0x342f, - 0x1904, 0xe0ab, 0x080c, 0xe28c, 0x1904, 0xdd2f, 0x6007, 0x0020, - 0x6003, 0x0001, 0x080c, 0x977c, 0x080c, 0x9ce8, 0x0005, 0x080c, - 0x342f, 0x1904, 0xe0ab, 0x6007, 0x0023, 0x6003, 0x0001, 0x080c, - 0x977c, 0x080c, 0x9ce8, 0x0005, 0x080c, 0xf1fe, 0x1904, 0xe0ab, - 0x080c, 0x342f, 0x1904, 0xe0ab, 0x080c, 0xe28c, 0x1904, 0xdd2f, - 0x0016, 0x0026, 0x00e6, 0x2071, 0x0260, 0x2c08, 0x2011, 0x1820, - 0x2214, 0x703c, 0x9206, 0x11e0, 0x2011, 0x181f, 0x2214, 0x7038, - 0x9084, 0x00ff, 0x9206, 0x11a0, 0x7240, 0x080c, 0xd3e3, 0x0570, - 0x2260, 0x6008, 0x9086, 0xffff, 0x0120, 0x7244, 0x6008, 0x9206, - 0x1528, 0x6020, 0x9086, 0x0007, 0x1508, 0x080c, 0xb53c, 0x04a0, - 0x7244, 0x9286, 0xffff, 0x0180, 0x2c08, 0x080c, 0xd3e3, 0x01b0, - 0x2260, 0x7240, 0x6008, 0x9206, 0x1188, 0x6010, 0x9190, 0x0004, - 0x2214, 0x9206, 0x01b8, 0x0050, 0x7240, 0x2c08, 0x9006, 0x080c, - 0xefd4, 0x1180, 0x7244, 0x9286, 0xffff, 0x01b0, 0x2160, 0x6007, - 0x0026, 0x6017, 0x1700, 0x7214, 0x9296, 0xffff, 0x1180, 0x6007, - 0x0025, 0x0068, 0x6020, 0x9086, 0x0007, 0x1d80, 0x6004, 0x9086, - 0x0024, 0x1110, 0x080c, 0xb53c, 0x2160, 0x6007, 0x0025, 0x6003, - 0x0001, 0x080c, 0x977c, 0x080c, 0x9ce8, 0x00ee, 0x002e, 0x001e, - 0x0005, 0x2001, 0x0001, 0x080c, 0x67bb, 0x0156, 0x0016, 0x0026, - 0x0036, 0x20a9, 0x0004, 0x2019, 0x1805, 0x2011, 0x0276, 0x080c, - 0xc64d, 0x003e, 0x002e, 0x001e, 0x015e, 0x0120, 0x6007, 0x0031, - 0x0804, 0xde67, 0x080c, 0xc245, 0x080c, 0x77ff, 0x1190, 0x0006, - 0x0026, 0x0036, 0x080c, 0x7819, 0x1138, 0x080c, 0x7afa, 0x080c, - 0x62b4, 0x080c, 0x772c, 0x0010, 0x080c, 0x77d7, 0x003e, 0x002e, - 0x000e, 0x0005, 0x080c, 0x342f, 0x1904, 0xe0ab, 0x080c, 0xe28c, - 0x1904, 0xdd2f, 0x6106, 0x080c, 0xe2a8, 0x1120, 0x6007, 0x002b, - 0x0804, 0xde67, 0x6007, 0x002c, 0x0804, 0xde67, 0x080c, 0xf1fe, - 0x1904, 0xe0ab, 0x080c, 0x342f, 0x1904, 0xe0ab, 0x080c, 0xe28c, - 0x1904, 0xdd2f, 0x6106, 0x080c, 0xe2ad, 0x1120, 0x6007, 0x002e, - 0x0804, 0xde67, 0x6007, 0x002f, 0x0804, 0xde67, 0x080c, 0x342f, - 0x1904, 0xe0ab, 0x00e6, 0x00d6, 0x00c6, 0x6010, 0x2058, 0xb904, - 0x9184, 0x00ff, 0x9086, 0x0006, 0x0158, 0x9184, 0xff00, 0x8007, - 0x9086, 0x0006, 0x0128, 0x00ce, 0x00de, 0x00ee, 0x0804, 0xde6e, - 0x080c, 0x5963, 0xd0e4, 0x0904, 0xdfe8, 0x2071, 0x026c, 0x7010, - 0x603a, 0x7014, 0x603e, 0x7108, 0x720c, 0x080c, 0x6c57, 0x0140, - 0x6010, 0x2058, 0xb810, 0x9106, 0x1118, 0xb814, 0x9206, 0x0510, - 0x080c, 0x6c53, 0x15b8, 0x2069, 0x1800, 0x6880, 0x9206, 0x1590, - 0x687c, 0x9106, 0x1578, 0x7210, 0x080c, 0xd3e3, 0x0590, 0x080c, - 0xe179, 0x0578, 0x080c, 0xf086, 0x0560, 0x622e, 0x6007, 0x0036, - 0x6003, 0x0001, 0x080c, 0x9734, 0x080c, 0x9ce8, 0x00ce, 0x00de, - 0x00ee, 0x0005, 0x7214, 0x9286, 0xffff, 0x0150, 0x080c, 0xd3e3, - 0x01c0, 0x9280, 0x0002, 0x2004, 0x7110, 0x9106, 0x1190, 0x08e0, - 0x7210, 0x2c08, 0x9085, 0x0001, 0x080c, 0xefd4, 0x2c10, 0x2160, - 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0x0009, 0x00ff, 0x0008, 0x7f00, 0x0000, 0x80e0, 0x0001, 0x0004, - 0x0000, 0x0ae8, 0x000b, 0x80e0, 0x0001, 0x0005, 0x0008, 0x0ae8, - 0x000b, 0x80e0, 0x0001, 0x0006, 0x0008, 0x0ae8, 0x000b, 0x82c0, - 0x0001, 0xff00, 0x0008, 0x7f04, 0x0008, 0x82e0, 0x0009, 0x0600, - 0x0008, 0x0ae8, 0x000b, 0x82e0, 0x0009, 0x0500, 0x0008, 0x0ae8, - 0x000b, 0x82e0, 0x0009, 0x0400, 0x0000, 0x0f9d, 0x0003, 0xc4c0, - 0x0009, 0x7000, 0x0000, 0xffe0, 0x0009, 0x1000, 0x0000, 0x0b27, - 0x0003, 0x3941, 0x0002, 0x0ef4, 0x000b, 0x8072, 0x0000, 0x0404, - 0x0008, 0x0000, 0x0007, 0x3941, 0x0002, 0x0af7, 0x0003, 0x8072, - 0x0000, 0x0400, 0x0000, 0x000a, 0x000b, 0x0460, 0x0000, 0x80fe, - 0x0008, 0x002b, 0x0008, 0x7f62, 0x0008, 0x8066, 0x0000, 0x2209, - 0x0008, 0x46fd, 0x000b, 0x11fe, 0x0000, 0x3322, 0x000b, 0x808c, - 0x0008, 0x0002, 0x0000, 0x9180, 0x0001, 0x000a, 0x0008, 0x8060, - 0x0000, 0x0400, 0x0000, 0x7f62, 0x0008, 0x8066, 0x0000, 0x0209, - 0x0000, 0x4709, 0x000b, 0x40fe, 0x0008, 0x01e0, 0x0001, 0x0f1f, - 0x0003, 0x808c, 0x0008, 0x0001, 0x0000, 0x9180, 0x0001, 0x0002, - 0x0000, 0x8060, 0x0000, 0x0400, 0x0000, 0x7f62, 0x0008, 0x8066, - 0x0000, 0x0609, 0x0008, 0x4716, 0x0003, 0x42fe, 0x0000, 0xffc0, - 0x0001, 0xff00, 0x0008, 0x03e0, 0x0009, 0x0f1f, 0x0003, 0x8072, - 0x0000, 0x0400, 0x0000, 0x0046, 0x0003, 0x9180, 0x0001, 0x0003, - 0x0008, 0x02fa, 0x0003, 0x8072, 0x0000, 0x0400, 0x0000, 0x8010, - 0x0008, 0x0010, 0x0000, 0x038e, 0x000b, 0x3941, 0x0002, 0x0f2e, - 0x000b, 0x8072, 0x0000, 0x0404, 0x0008, 0x0000, 0x0007, 0x3941, - 0x0002, 0x0b31, 0x000b, 0x8072, 0x0000, 0x0400, 0x0000, 0x000a, - 0x000b, 0x1042, 0x000a, 0x0b36, 0x0003, 0x0373, 0x000c, 0x11fe, - 0x0000, 0x373b, 0x000b, 0x8072, 0x0000, 0x0400, 0x0000, 0x8010, - 0x0008, 0x000e, 0x0000, 0x038e, 0x000b, 0x808c, 0x0008, 0x0001, - 0x0000, 0x8060, 0x0000, 0x0400, 0x0000, 0x04fe, 0x0008, 0x3752, - 0x000b, 0x808c, 0x0008, 0x0000, 0x0008, 0x9180, 0x0001, 0x0005, - 0x0008, 0x7f62, 0x0008, 0x8066, 0x0000, 0x0009, 0x0008, 0x4748, - 0x000b, 0x0060, 0x0008, 0x8062, 0x0008, 0x001c, 0x0000, 0x4304, - 0x0008, 0x4206, 0x0008, 0x8066, 0x0000, 0x0412, 0x0000, 0x4750, - 0x000b, 0x0370, 0x0003, 0x4006, 0x0000, 0x9180, 0x0001, 0x000a, - 0x0008, 0x7f62, 0x0008, 0x8066, 0x0000, 0x060a, 0x0008, 0x4758, - 0x0003, 0x808c, 0x0008, 0x0001, 0x0000, 0x0460, 0x0000, 0x8062, - 0x0008, 0x002b, 0x0008, 0x8066, 0x0000, 0x0609, 0x0008, 0x4760, - 0x000b, 0x8066, 0x0000, 0x220a, 0x0008, 0x4763, 0x000b, 0x42fe, - 0x0000, 0xffc0, 0x0001, 0xff00, 0x0008, 0x7f04, 0x0008, 0x8060, - 0x0000, 0x0400, 0x0000, 0x9180, 0x0001, 0x0002, 0x0000, 0x7f62, - 0x0008, 0x8066, 0x0000, 0x041a, 0x0008, 0x476f, 0x000b, 0x8072, - 0x0000, 0x0400, 0x0000, 0x0046, 0x0003, 0x8060, 0x0000, 0x0400, - 0x0000, 0x1362, 0x0008, 0x8066, 0x0000, 0x0411, 0x0000, 0x4778, - 0x000b, 0x02fe, 0x0008, 0x03e0, 0x0009, 0x0f7e, 0x000b, 0x0d22, - 0x0000, 0x4000, 0x000f, 0x8280, 0x0009, 0x0002, 0x0000, 0x1380, - 0x0001, 0x7f62, 0x0008, 0x8066, 0x0000, 0x2209, 0x0008, 0x4784, - 0x000b, 0x0200, 0x000a, 0xffc0, 0x0001, 0x0007, 0x0000, 0x7f06, - 0x0000, 0x1362, 0x0008, 0x8066, 0x0000, 0x060a, 0x0008, 0x478c, - 0x0003, 0x4000, 0x000f, 0x3a44, 0x0002, 0x0c0a, 0x000b, 0x2f44, - 0x000a, 0x2f44, 0x000a, 0x0e76, 0x000b, 0x808a, 0x0008, 0x0003, - 0x0008, 0x8074, 0x0000, 0xf080, 0x0000, 0x8072, 0x0000, 0x3000, - 0x0008, 0x5b99, 0x0003, 0x8054, 0x0008, 0x0019, 0x0000, 0x000a, - 0x000b, 0x3a44, 0x0002, 0x0c0a, 0x000b, 0x808c, 0x0008, 0x0000, - 0x0008, 0x8010, 0x0008, 0x0011, 0x0008, 0x022c, 0x0004, 0x42fe, - 0x0000, 0xffc0, 0x0001, 0x00ff, 0x0008, 0x7f10, 0x0008, 0x022c, - 0x0004, 0x4310, 0x0008, 0x0285, 0x000b, 0xc2c0, 0x0009, 0x00ff, - 0x0008, 0x7f00, 0x0000, 0xc3c0, 0x0001, 0xff00, 0x0008, 0x00d0, - 0x0009, 0x0bd0, 0x000b, 0x0d0a, 0x0000, 0x8580, 0x0001, 0x1000, - 0x0000, 0x7f62, 0x0008, 0x8060, 0x0000, 0x0400, 0x0000, 0x8066, - 0x0000, 0x0809, 0x0000, 0x47ba, 0x0003, 0x04fe, 0x0008, 0x33c9, - 0x000b, 0x0460, 0x0000, 0x8062, 0x0008, 0x0004, 0x0000, 0x8066, - 0x0000, 0x0211, 0x0000, 0x47c2, 0x0003, 0x01fe, 0x0008, 0x00e0, - 0x0009, 0x0fc9, 0x000b, 0x02fe, 0x0008, 0x43e0, 0x0001, 0x0bcf, - 0x0003, 0x0500, 0x0002, 0x7f0a, 0x0000, 0xffe0, 0x0009, 0x0800, - 0x0000, 0x0fb3, 0x0003, 0x0d08, 0x0008, 0x4000, 0x000f, 0x43fe, - 0x0008, 0x3e80, 0x0001, 0xffc0, 0x0001, 0x7fff, 0x0000, 0x0d60, - 0x0000, 0x7f62, 0x0008, 0x8066, 0x0000, 0x0809, 0x0000, 0x47d8, - 0x000b, 0x8060, 0x0000, 0x0400, 0x0000, 0x84c0, 0x0001, 0xff00, - 0x0008, 0x7f60, 0x000a, 0x7f60, 0x000a, 0x7f60, 0x000a, 0x7f60, - 0x000a, 0x7f60, 0x000a, 0x7f60, 0x000a, 0x7f60, 0x000a, 0x7f60, - 0x000a, 0xff80, 0x0009, 0x1000, 0x0000, 0x7f62, 0x0008, 0x8066, - 0x0000, 0x0809, 0x0000, 0x47ea, 0x0003, 0x4000, 0x000f, 0xa8ad, - 0xeb6a, 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, - 0x0080, 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, - 0x8000, 0xc174 -}; diff --git a/sys/dev/ispfw/asm_2322.h b/sys/dev/ispfw/asm_2322.h deleted file mode 100644 index a080a5d1aef..00000000000 --- a/sys/dev/ispfw/asm_2322.h +++ /dev/null @@ -1,8543 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-3-Clause - * - * Copyright (C) 2004-2005 by Qlogic, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms are permitted provided - * that the following conditions are met: - * 1. Redistribution of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistribution in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/************************************************************************ - * * - * --- ISP2300 Initiator/Target Firmware --- * - * with Fabric (Public Loop), Point-point, * - * expanded LUN addressing for FCTAPE, and 2K port logins * - * * - ************************************************************************/ -/* - * Firmware Version 3.03.28 - */ -static const uint16_t isp_2322_risc_code[] = { - 0x0470, 0x0000, 0x0000, 0xebf7, 0x0000, 0x0003, 0x0003, 0x001c, - 0x0137, 0x2043, 0x4f50, 0x5952, 0x4947, 0x4854, 0x2032, 0x3030, - 0x3120, 0x514c, 0x4f47, 0x4943, 0x2043, 0x4f52, 0x504f, 0x5241, - 0x5449, 0x4f4e, 0x2049, 0x5350, 0x3233, 0x3030, 0x2046, 0x6972, - 0x6d77, 0x6172, 0x6520, 0x2056, 0x6572, 0x7369, 0x6f6e, 0x2030, - 0x332e, 0x3033, 0x2e32, 0x3820, 0x2020, 0x2020, 0x2400, 0x20a9, - 0x000f, 0x2001, 0x0000, 0x400f, 0x2091, 0x2200, 0x20a9, 0x000f, - 0x2001, 0x0000, 0x400f, 0x2091, 0x2400, 0x20a9, 0x000f, 0x2001, - 0x0000, 0x400f, 0x2091, 0x2600, 0x20a9, 0x000f, 0x2001, 0x0000, - 0x400f, 0x2091, 0x2800, 0x20a9, 0x000f, 0x2001, 0x0000, 0x400f, - 0x2091, 0x2a00, 0x20a9, 0x000f, 0x2001, 0x0000, 0x400f, 0x2091, - 0x2c00, 0x20a9, 0x000f, 0x2001, 0x0000, 0x400f, 0x2091, 0x2e00, - 0x20a9, 0x000f, 0x2001, 0x0000, 0x400f, 0x2091, 0x2000, 0x2001, - 0x0000, 0x20c1, 0x0004, 0x20c9, 0x1cff, 0x2059, 0x0000, 0x2b78, - 0x7883, 0x0004, 0x2089, 0x2ccc, 0x2051, 0x1800, 0x2a70, 0x20e1, - 0x0001, 0x20e9, 0x0001, 0x2009, 0x0000, 0x080c, 0x0e7c, 0x00f6, - 0x7888, 0x9005, 0x11f8, 0x2061, 0xc000, 0x080c, 0x2161, 0x1170, - 0x2079, 0x0300, 0x080c, 0x2177, 0x2061, 0xe000, 0x080c, 0x2161, - 0x1128, 0x2079, 0x0380, 0x080c, 0x2177, 0x0060, 0x00fe, 0x7883, - 0x4010, 0x7837, 0x4010, 0x7833, 0x0011, 0x2091, 0x5000, 0x2091, - 0x4080, 0x0cf8, 0x00fe, 0x2029, 0x5600, 0x2031, 0xffff, 0x2039, - 0x55dc, 0x2021, 0x0200, 0x20e9, 0x0001, 0x20a1, 0x0000, 0x20a9, - 0x0800, 0x900e, 0x4104, 0x20e9, 0x0001, 0x20a1, 0x1000, 0x900e, - 0x2001, 0x0dc1, 0x9084, 0x0fff, 0x20a8, 0x4104, 0x2001, 0x0000, - 0x9086, 0x0000, 0x0120, 0x21a8, 0x4104, 0x8001, 0x1de0, 0x756e, - 0x7672, 0x776a, 0x7476, 0x747a, 0x00e6, 0x2071, 0x1b86, 0x2472, - 0x00ee, 0x20a1, 0x1ddc, 0x7170, 0x810d, 0x810d, 0x810d, 0x810d, - 0x918c, 0x000f, 0x2001, 0x0001, 0x9112, 0x900e, 0x21a8, 0x4104, - 0x8211, 0x1de0, 0x7170, 0x3400, 0x8001, 0x9102, 0x0120, 0x0218, - 0x20a8, 0x900e, 0x4104, 0x2009, 0x1800, 0x810d, 0x810d, 0x810d, - 0x810d, 0x810d, 0x918c, 0x001f, 0x2001, 0x0001, 0x9112, 0x20e9, - 0x0001, 0x20a1, 0x0800, 0x900e, 0x20a9, 0x0800, 0x4104, 0x8211, - 0x1dd8, 0x080c, 0x0f79, 0x080c, 0x635d, 0x080c, 0xb403, 0x080c, - 0x1144, 0x080c, 0x1371, 0x080c, 0x1cb7, 0x080c, 0x9827, 0x080c, - 0x0d1e, 0x080c, 0x10b5, 0x080c, 0x369d, 0x080c, 0x7cf7, 0x080c, - 0x6f1b, 0x080c, 0x8f31, 0x080c, 0x8b46, 0x080c, 0x235e, 0x080c, - 0x8422, 0x080c, 0x2190, 0x080c, 0x22d2, 0x080c, 0x2353, 0x2091, - 0x3009, 0x7883, 0x0000, 0x1004, 0x0943, 0x7880, 0x9086, 0x0002, - 0x1190, 0x7883, 0x4000, 0x7837, 0x4000, 0x7833, 0x0010, 0x0e04, - 0x0937, 0x2091, 0x5000, 0x2091, 0x4080, 0x2001, 0x0089, 0x2004, - 0xd084, 0x190c, 0x121c, 0x2071, 0x1800, 0x7003, 0x0000, 0x780c, - 0x9084, 0x0030, 0x9086, 0x0020, 0x1168, 0x7034, 0xc08d, 0x7036, - 0x2001, 0x0050, 0x7076, 0x707a, 0x7056, 0x606b, 0x269c, 0x2071, - 0x1b86, 0x2072, 0x2071, 0x1800, 0x7000, 0x908e, 0x0003, 0x1168, - 0x080c, 0x4f0d, 0x080c, 0x36c4, 0x080c, 0x7d5f, 0x080c, 0x74a4, - 0x080c, 0x9018, 0x080c, 0x8b6f, 0x0c68, 0x000b, 0x0c88, 0x0979, - 0x097a, 0x0b17, 0x0977, 0x0bd6, 0x0d1d, 0x0d1d, 0x0d1d, 0x080c, - 0x0d8c, 0x0005, 0x0126, 0x00f6, 0x2091, 0x8000, 0x7000, 0x9086, - 0x0001, 0x1904, 0x0ae8, 0x080c, 0x0ecc, 0x080c, 0x79cb, 0x0150, - 0x080c, 0x79ee, 0x15c0, 0x2079, 0x0100, 0x7828, 0x9085, 0x1800, - 0x782a, 0x0488, 0x080c, 0x78fa, 0x7000, 0x9086, 0x0001, 0x1904, - 0x0ae8, 0x7098, 0x9086, 0x0029, 0x1904, 0x0ae8, 0x080c, 0x8b26, - 0x080c, 0x8b18, 0x2079, 0x0100, 0x782f, 0x0008, 0x2001, 0x0161, - 0x2003, 0x0001, 0x2011, 0xffff, 0x080c, 0x2b94, 0x7a28, 0x9295, - 0x5e2c, 0x7a2a, 0x2011, 0x783f, 0x080c, 0x8c1b, 0x2011, 0x7832, - 0x080c, 0x8d73, 0x2011, 0x61b2, 0x080c, 0x8c1b, 0x2011, 0x8030, - 0x901e, 0x7396, 0x04c0, 0x080c, 0x5a56, 0x2079, 0x0100, 0x7844, - 0x9005, 0x1904, 0x0ae8, 0x2011, 0x61b2, 0x080c, 0x8c1b, 0x2011, - 0x783f, 0x080c, 0x8c1b, 0x2011, 0x7832, 0x080c, 0x8d73, 0x2001, - 0x0205, 0x2003, 0x0000, 0x7840, 0x9084, 0xfffb, 0x7842, 0x2001, - 0x19aa, 0x2004, 0x9005, 0x1140, 0x00c6, 0x2061, 0x0100, 0x080c, - 0x6305, 0x00ce, 0x0804, 0x0ae8, 0x780f, 0x006b, 0x7a28, 0x080c, - 0x79d3, 0x0118, 0x9295, 0x5e2c, 0x0010, 0x9295, 0x402c, 0x7a2a, - 0x2011, 0x8010, 0x73d8, 0x2001, 0x19ab, 0x2003, 0x0001, 0x080c, - 0x2a53, 0x080c, 0x4e48, 0x7248, 0xc284, 0x724a, 0x2001, 0x180c, - 0x200c, 0xc1ac, 0xc1cc, 0x2102, 0x2001, 0x0390, 0x2003, 0x0400, - 0x080c, 0xafdc, 0x080c, 0xa7b5, 0x2011, 0x0004, 0x080c, 0xd321, - 0x080c, 0xaff8, 0x080c, 0x6cbb, 0x080c, 0x79cb, 0x1120, 0x080c, - 0x2ab4, 0x0600, 0x0420, 0x080c, 0x630c, 0x0140, 0x7097, 0x0001, - 0x70d3, 0x0000, 0x080c, 0x5c28, 0x0804, 0x0ae8, 0x2001, 0x0390, - 0x2003, 0x0404, 0x080c, 0x59f6, 0xd094, 0x0188, 0x2011, 0x180c, - 0x2204, 0xc0cd, 0x2012, 0x080c, 0x59fa, 0xd0d4, 0x1118, 0x080c, - 0x2ab4, 0x1270, 0x2011, 0x180c, 0x2204, 0xc0bc, 0x00a8, 0x080c, - 0x59fa, 0xd0d4, 0x1db8, 0x2011, 0x180c, 0x2204, 0xc0bd, 0x0060, - 0x2011, 0x180c, 0x2204, 0xc0bd, 0x2012, 0x080c, 0x6e23, 0x1128, - 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0xd29c, 0x0148, 0xd284, 0x1138, 0xd2bc, 0x1904, 0x3300, 0x080c, - 0x3305, 0x0804, 0x3300, 0xd2cc, 0x1904, 0x3300, 0x080c, 0x79cb, - 0x1120, 0x70af, 0xffff, 0x0804, 0x3300, 0xd294, 0x0120, 0x70af, - 0xffff, 0x0804, 0x3300, 0x080c, 0x358c, 0x0160, 0x080c, 0xda4e, - 0x0128, 0x2001, 0x1818, 0x203c, 0x0804, 0x3279, 0x70af, 0xffff, - 0x0804, 0x3300, 0x2001, 0x1818, 0x203c, 0x7294, 0xd284, 0x0904, - 0x3279, 0xd28c, 0x1904, 0x3279, 0x0036, 0x73ac, 0x938e, 0xffff, - 0x1110, 0x2019, 0x0001, 0x8314, 0x92e0, 0x1d80, 0x2c04, 0x938c, - 0x0001, 0x0120, 0x9084, 0xff00, 0x8007, 0x0010, 0x9084, 0x00ff, - 0x970e, 0x0904, 0x326f, 0x908e, 0x0000, 0x0904, 0x326f, 0x908e, - 0x00ff, 0x1160, 0x7230, 0xd284, 0x1904, 0x3274, 0x7294, 0xc28d, - 0x7296, 0x70af, 0xffff, 0x003e, 0x0804, 0x3279, 0x2009, 0x180d, - 0x210c, 0xd18c, 0x0150, 0x0026, 0x2011, 0x0010, 0x080c, 0x6e66, - 0x002e, 0x0118, 0x70af, 0xffff, 0x0488, 0x900e, 0x080c, 0x2744, - 0x080c, 0x6905, 0x1538, 0x9006, 0xb8bb, 0x0520, 0xb8ac, 0x9005, - 0x0148, 0x00c6, 0x2060, 0x080c, 0x91c7, 0x00ce, 0x090c, 0x9547, - 0xb8af, 0x0000, 0x080c, 0x6e2b, 0x1168, 0x7030, 0xd08c, 0x0130, - 0xb800, 0xd0bc, 0x0138, 0x080c, 0x6cab, 0x0120, 0x080c, 0x331e, - 0x0148, 0x0028, 0x080c, 0x346f, 0x080c, 0x334a, 0x0118, 0x8318, - 0x0804, 0x3213, 0x73ae, 0x0010, 0x70af, 0xffff, 0x003e, 0x0804, - 0x3300, 0x9780, 0x359d, 0x203d, 0x97bc, 0xff00, 0x873f, 0x2041, - 0x007e, 0x70ac, 0x9096, 0xffff, 0x1118, 0x900e, 0x28a8, 0x0050, - 0x9812, 0x0220, 0x2008, 0x9802, 0x20a8, 0x0020, 0x70af, 0xffff, - 0x0804, 0x3300, 0x2700, 0x0156, 0x0016, 0x9106, 0x0904, 0x32f5, - 0x2001, 0x180d, 0x2004, 0xd08c, 0x0158, 0x0026, 0x2011, 0x0010, - 0x080c, 0x6e66, 0x002e, 0x0120, 0x2009, 0xffff, 0x0804, 0x32fd, - 0xc484, 0x080c, 0x6977, 0x0168, 0x080c, 0xda4e, 0x1904, 0x32f5, - 0x080c, 0x358c, 0x1904, 0x32f5, 0x080c, 0x6905, 0x1904, 0x32fd, - 0x0008, 0xc485, 0xb8bb, 0x0520, 0xb8ac, 0x9005, 0x0148, 0x00c6, - 0x2060, 0x080c, 0x91c7, 0x00ce, 0x090c, 0x9547, 0xb8af, 0x0000, - 0x080c, 0x6e2b, 0x1130, 0x7030, 0xd08c, 0x01f8, 0xb800, 0xd0bc, - 0x11e0, 0x7294, 0xd28c, 0x0180, 0x080c, 0x6e2b, 0x9082, 0x0006, - 0x02e0, 0xd484, 0x1118, 0x080c, 0x6932, 0x0028, 0x080c, 0x3502, - 0x01a0, 0x080c, 0x352d, 0x0088, 0x080c, 0x346f, 0x080c, 0xda4e, - 0x1160, 0x080c, 0x334a, 0x0188, 0x0040, 0x080c, 0xda4e, 0x1118, - 0x080c, 0x3502, 0x0110, 0x0451, 0x0140, 0x001e, 0x8108, 0x015e, - 0x1f04, 0x3292, 0x70af, 0xffff, 0x0018, 0x001e, 0x015e, 0x71ae, - 0x004e, 0x002e, 0x00ce, 0x00be, 0x0005, 0x00c6, 0x0016, 0x70af, - 0x0001, 0x2009, 0x007e, 0x080c, 0x6905, 0x1168, 0xb813, 0x00ff, - 0xb817, 0xfffe, 0x080c, 0x346f, 0x04a9, 0x0128, 0x70dc, 0xc0bd, - 0x70de, 0x080c, 0xd793, 0x001e, 0x00ce, 0x0005, 0x0016, 0x0076, - 0x00d6, 0x00c6, 0x2001, 0x184f, 0x2004, 0x9084, 0x00ff, 0xb842, - 0x080c, 0xb4dd, 0x01d0, 0x2b00, 0x6012, 0x080c, 0xd7c0, 0x6023, - 0x0001, 0x9006, 0x080c, 0x68a2, 0x2001, 0x0000, 0x080c, 0x68b6, - 0x0126, 0x2091, 0x8000, 0x70a8, 0x8000, 0x70aa, 0x012e, 0x2009, - 0x0004, 0x080c, 0xb50a, 0x9085, 0x0001, 0x00ce, 0x00de, 0x007e, - 0x001e, 0x0005, 0x0016, 0x0076, 0x00d6, 0x00c6, 0x2001, 0x184f, - 0x2004, 0x9084, 0x00ff, 0xb842, 0x080c, 0xb4dd, 0x0548, 0x2b00, - 0x6012, 0xb800, 0xc0c4, 0xb802, 0xb8a0, 0x9086, 0x007e, 0x0140, - 0xb804, 0x9084, 0x00ff, 0x9086, 0x0006, 0x1110, 0x080c, 0x3424, - 0x080c, 0xd7c0, 0x6023, 0x0001, 0x9006, 0x080c, 0x68a2, 0x2001, - 0x0002, 0x080c, 0x68b6, 0x0126, 0x2091, 0x8000, 0x70a8, 0x8000, - 0x70aa, 0x012e, 0x2009, 0x0002, 0x080c, 0xb50a, 0x9085, 0x0001, - 0x00ce, 0x00de, 0x007e, 0x001e, 0x0005, 0x00b6, 0x00c6, 0x0026, - 0x2009, 0x0080, 0x080c, 0x6905, 0x1140, 0xb813, 0x00ff, 0xb817, - 0xfffc, 0x0039, 0x0110, 0x70e3, 0xffff, 0x002e, 0x00ce, 0x00be, - 0x0005, 0x0016, 0x0076, 0x00d6, 0x00c6, 0x080c, 0xb4dd, 0x01d0, - 0x2b00, 0x6012, 0x080c, 0xd7c0, 0x6023, 0x0001, 0x9006, 0x080c, - 0x68a2, 0x2001, 0x0002, 0x080c, 0x68b6, 0x0126, 0x2091, 0x8000, - 0x70e4, 0x8000, 0x70e6, 0x012e, 0x2009, 0x0002, 0x080c, 0xb50a, - 0x9085, 0x0001, 0x00ce, 0x00de, 0x007e, 0x001e, 0x0005, 0x00c6, - 0x00d6, 0x0126, 0x2091, 0x8000, 0x2009, 0x007f, 0x080c, 0x6905, - 0x11e0, 0xb813, 0x00ff, 0xb817, 0xfffd, 0xb8d7, 0x0004, 0x080c, - 0xb4dd, 0x0198, 0x83ff, 0x1118, 0x70dc, 0xc0f5, 0x70de, 0x2b00, - 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0xb8a0, 0x00be, 0x9086, 0x0080, 0x0150, 0x2071, 0x1800, 0x70a8, - 0x9005, 0x0110, 0x8001, 0x70aa, 0x000e, 0x00ee, 0x0005, 0x2071, - 0x1800, 0x70e4, 0x9005, 0x0dc0, 0x8001, 0x70e6, 0x0ca8, 0xb800, - 0xc08c, 0xb802, 0x0005, 0x00f6, 0x00e6, 0x00c6, 0x00b6, 0x0046, - 0x0036, 0x0026, 0x0016, 0x0156, 0x2178, 0x080c, 0xafdc, 0x0106, - 0x81ff, 0x1118, 0x20a9, 0x0001, 0x0078, 0x080c, 0x59f6, 0xd0c4, - 0x0140, 0xd0a4, 0x0130, 0x9006, 0x2020, 0x2009, 0x002d, 0x080c, - 0xef3b, 0x20a9, 0x0800, 0x9016, 0x0026, 0x928e, 0x007e, 0x0904, - 0x34de, 0x928e, 0x007f, 0x0904, 0x34de, 0x928e, 0x0080, 0x05f0, - 0x9288, 0x1000, 0x210c, 0x81ff, 0x05c8, 0x8fff, 0x1150, 0x2001, - 0x1991, 0x0006, 0x2003, 0x0001, 0x080c, 0x34ef, 0x000e, 0x2003, - 0x0000, 0x00b6, 0x00c6, 0x2158, 0x2001, 0x0001, 0x080c, 0x6df5, - 0x00ce, 0x00be, 0x2019, 0x0029, 0x080c, 0x9a55, 0x0076, 0x2039, - 0x0000, 0x080c, 0x9912, 0x00b6, 0x00c6, 0x0026, 0x2158, 0xba04, - 0x9294, 0x00ff, 0x9286, 0x0006, 0x1118, 0xb807, 0x0404, 0x0028, - 0x2001, 0x0004, 0x8007, 0x9215, 0xba06, 0x002e, 0x00ce, 0x00be, - 0x0016, 0x2c08, 0x080c, 0xec04, 0x001e, 0x007e, 0x002e, 0x8210, - 0x1f04, 0x3494, 0x010e, 0x090c, 0xaff8, 0x015e, 0x001e, 0x002e, - 0x003e, 0x004e, 0x00be, 0x00ce, 0x00ee, 0x00fe, 0x0005, 0x0046, - 0x0026, 0x0016, 0x080c, 0x59f6, 0xd0c4, 0x0140, 0xd0a4, 0x0130, - 0x9006, 0x2220, 0x2009, 0x0029, 0x080c, 0xef3b, 0x001e, 0x002e, - 0x004e, 0x0005, 0x0016, 0x0026, 0x0036, 0x00c6, 0x7294, 0x82ff, - 0x01e8, 0x080c, 0x6e23, 0x11d0, 0x2100, 0x080c, 0x2777, 0x81ff, - 0x01b8, 0x2019, 0x0001, 0x8314, 0x92e0, 0x1d80, 0x2c04, 0xd384, - 0x0120, 0x9084, 0xff00, 0x8007, 0x0010, 0x9084, 0x00ff, 0x9116, - 0x0138, 0x9096, 0x00ff, 0x0110, 0x8318, 0x0c68, 0x9085, 0x0001, - 0x00ce, 0x003e, 0x002e, 0x001e, 0x0005, 0x0016, 0x00c6, 0x0126, - 0x2091, 0x8000, 0x080c, 0xafdc, 0x0106, 0x0036, 0x2019, 0x0029, - 0x00c1, 0x003e, 0x010e, 0x090c, 0xaff8, 0x9180, 0x1000, 0x2004, - 0x9065, 0x0158, 0x0016, 0x00c6, 0x2061, 0x1b4c, 0x001e, 0x6112, - 0x080c, 0x3424, 0x001e, 0x080c, 0x6932, 0x012e, 0x00ce, 0x001e, - 0x0005, 0x0016, 0x0026, 0x2110, 0x080c, 0xaaa6, 0x080c, 0xf2b0, - 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0x0904, 0x6403, 0x0804, 0x63fe, 0x00e6, 0x2071, 0x19eb, 0x7004, - 0x9086, 0x0002, 0x1128, 0x7030, 0x9080, 0x0004, 0x2004, 0x9b06, - 0x00ee, 0x0005, 0x00b6, 0x00e6, 0x0126, 0x2091, 0x8000, 0xa878, - 0x908e, 0x00ff, 0x1120, 0x2001, 0x196e, 0x205c, 0x0060, 0xa978, - 0x9182, 0x0800, 0x1690, 0x9188, 0x1000, 0x2104, 0x905d, 0x01d0, - 0x080c, 0x6dcb, 0x11d0, 0x080c, 0xb417, 0x0570, 0x2b00, 0x6012, - 0x2900, 0x6016, 0x6023, 0x0009, 0x602b, 0x0000, 0xa878, 0x908e, - 0x00ff, 0x1110, 0x602b, 0x8000, 0x2009, 0x0043, 0x080c, 0xb50a, - 0x9006, 0x00b0, 0x2001, 0x0028, 0x0090, 0x2009, 0x180c, 0x210c, - 0xd18c, 0x0118, 0x2001, 0x0004, 0x0038, 0xd184, 0x0118, 0x2001, - 0x0004, 0x0010, 0x2001, 0x0029, 0x0010, 0x2001, 0x0029, 0x9005, - 0x012e, 0x00ee, 0x00be, 0x0005, 0x2001, 0x002c, 0x0cc0, 0x00b6, - 0x00e6, 0x0126, 0x2091, 0x8000, 0xa978, 0x9182, 0x0800, 0x1a04, - 0x6535, 0x9188, 0x1000, 0x2104, 0x905d, 0x0904, 0x650d, 0xb8a0, - 0x9086, 0x007f, 0x0190, 0xa880, 0xd0fc, 0x1178, 0x080c, 0x6e33, - 0x0160, 0xa998, 0x81ff, 0x0130, 0x908e, 0x0004, 0x0130, 0x908e, - 0x0005, 0x0118, 0x080c, 0x6e2b, 0x1598, 0xa880, 0xd0fc, 0x01e0, - 0xa898, 0x9005, 0x01c8, 0x2060, 0x0026, 0x2010, 0x080c, 0xd300, - 0x002e, 0x1120, 0x2001, 0x0008, 0x0804, 0x6537, 0x6020, 0x9086, - 0x000a, 0x0120, 0x2001, 0x0008, 0x0804, 0x6537, 0x601a, 0x6003, - 0x0008, 0x2900, 0x6016, 0x0058, 0x080c, 0xb417, 0x05e8, 0x2b00, - 0x6012, 0x2900, 0x6016, 0x600b, 0xffff, 0x6023, 0x000a, 0x2009, - 0x0003, 0x080c, 0xb50a, 0x9006, 0x0458, 0x2001, 0x0028, 0x0438, - 0x9082, 0x0006, 0x1290, 0x080c, 0xb395, 0x1160, 0xb8a0, 0x9084, - 0xff80, 0x1140, 0xb900, 0xd1fc, 0x0900, 0x2001, 0x0029, 0x2009, - 0x1000, 0x00a8, 0x2001, 0x0028, 0x0090, 0x2009, 0x180c, 0x210c, - 0xd18c, 0x0118, 0x2001, 0x0004, 0x0050, 0xd184, 0x0118, 0x2001, - 0x0004, 0x0028, 0x2001, 0x0029, 0x0010, 0x2001, 0x0029, 0x9005, - 0x012e, 0x00ee, 0x00be, 0x0005, 0x2001, 0x002c, 0x0cc0, 0x00f6, - 0x00b6, 0x0126, 0x2091, 0x8000, 0xa8e4, 0x9005, 0x1550, 0xa8e0, - 0x9082, 0x0101, 0x1630, 0xa8cc, 0x9005, 0x1518, 0xa8c8, 0x9082, - 0x0101, 0x12f8, 0xa978, 0x2079, 0x1800, 0x9182, 0x0800, 0x12e8, - 0x7830, 0x9084, 0x0003, 0x1130, 0xaa9c, 0xab98, 0xa87c, 0x9084, - 0x0007, 0x00ea, 0x7930, 0xd18c, 0x0118, 0x2001, 0x0004, 0x0038, - 0xd184, 0x0118, 0x2001, 0x0004, 0x0010, 0x2001, 0x0029, 0x900e, - 0x0038, 0x2001, 0x002c, 0x900e, 0x0018, 0x2001, 0x0029, 0x900e, - 0x9006, 0x0008, 0x9005, 0x012e, 0x00be, 0x00fe, 0x0005, 0x65cc, - 0x6587, 0x659e, 0x65cc, 0x65cc, 0x65cc, 0x65cc, 0x65cc, 0x2100, - 0x9082, 0x007e, 0x1278, 0x080c, 0x6905, 0x0148, 0x9046, 0xb810, - 0x9306, 0x1904, 0x65d4, 0xb814, 0x9206, 0x15f0, 0x0028, 0xbb12, - 0xba16, 0x0010, 0x080c, 0x4cff, 0x0150, 0x04b0, 0x080c, 0x6977, - 0x1598, 0xb810, 0x9306, 0x1580, 0xb814, 0x9206, 0x1568, 0x080c, - 0xb417, 0x0530, 0x2b00, 0x6012, 0x080c, 0xd7c0, 0x2900, 0x6016, - 0x600b, 0xffff, 0x6023, 0x000a, 0xa87c, 0x9086, 0x0001, 0x1170, - 0x080c, 0x3424, 0x9006, 0x080c, 0x68a2, 0x2001, 0x0002, 0x080c, - 0x68b6, 0x2001, 0x0200, 0xb86e, 0xb893, 0x0002, 0x2009, 0x0003, - 0x080c, 0xb50a, 0x9006, 0x0068, 0x2001, 0x0001, 0x900e, 0x0038, - 0x2001, 0x002c, 0x900e, 0x0018, 0x2001, 0x0028, 0x900e, 0x9005, - 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0xbec0, 0x0804, 0xbd94, 0x6004, 0x908e, 0x0032, 0x1160, 0x00e6, - 0x00f6, 0x2071, 0x18a1, 0x2079, 0x0000, 0x080c, 0x37ce, 0x00fe, - 0x00ee, 0x0804, 0xbd94, 0x6004, 0x908e, 0x0021, 0x0d40, 0x908e, - 0x0022, 0x090c, 0xbec0, 0x0804, 0xbd94, 0x90b2, 0x0040, 0x1a04, - 0xbe9e, 0x2008, 0x0002, 0xbe3d, 0xbe3e, 0xbe41, 0xbe44, 0xbe47, - 0xbe54, 0xbe3b, 0xbe3b, 0xbe3b, 0xbe3b, 0xbe3b, 0xbe3b, 0xbe3b, - 0xbe3b, 0xbe3b, 0xbe3b, 0xbe3b, 0xbe3b, 0xbe3b, 0xbe3b, 0xbe3b, - 0xbe3b, 0xbe3b, 0xbe3b, 0xbe3b, 0xbe3b, 0xbe3b, 0xbe3b, 0xbe3b, - 0xbe3b, 0xbe57, 0xbe60, 0xbe3b, 0xbe61, 0xbe60, 0xbe3b, 0xbe3b, - 0xbe3b, 0xbe3b, 0xbe3b, 0xbe60, 0xbe60, 0xbe3b, 0xbe3b, 0xbe3b, - 0xbe3b, 0xbe3b, 0xbe3b, 0xbe3b, 0xbe3b, 0xbe89, 0xbe60, 0xbe3b, - 0xbe5e, 0xbe3b, 0xbe3b, 0xbe3b, 0xbe5f, 0xbe3b, 0xbe3b, 0xbe3b, - 0xbe60, 0xbe84, 0xbe3b, 0x080c, 0x0d8c, 0x0410, 0x2001, 0x000b, - 0x0438, 0x2001, 0x0003, 0x0420, 0x2001, 0x0005, 0x0408, 0x6010, - 0x00b6, 0x2058, 0xb804, 0x00be, 0x9084, 0x00ff, 0x9086, 0x0000, - 0x11c8, 0x2001, 0x0001, 0x00a0, 0x2001, 0x0009, 0x0088, 0x6003, - 0x0005, 0x080c, 0xda66, 0x080c, 0x9d5e, 0x0048, 0x0008, 0x0000, - 0x04b8, 0x080c, 0xda66, 0x6003, 0x0004, 0x080c, 0x9d5e, 0x0005, - 0x080c, 0x68b6, 0x6003, 0x0002, 0x0036, 0x2019, 0x1855, 0x2304, - 0x9084, 0xff00, 0x1120, 0x2001, 0x1989, 0x201c, 0x0040, 0x8007, - 0x909a, 0x0004, 0x0ec0, 0x8003, 0x801b, 0x831b, 0x9318, 0x631a, - 0x003e, 0x080c, 0x9d5e, 0x0c18, 0x080c, 0xd7b8, 0x080c, 0xb46d, - 0x08f0, 0x00e6, 0x00f6, 0x2071, 0x18a1, 0x2079, 0x0000, 0x080c, - 0x37ce, 0x00fe, 0x00ee, 0x080c, 0x9c98, 0x080c, 0xb46d, 0x0878, - 0x6003, 0x0002, 0x080c, 0xda66, 0x0804, 0x9d5e, 0x2600, 0x2008, - 0x0002, 0xbeb7, 0xbe98, 0xbeb5, 0xbe98, 0xbe98, 0xbeb5, 0xbeb5, - 0xbeb5, 0xbeb5, 0xbe98, 0xbeb5, 0xbe98, 0xbeb5, 0xbe98, 0xbeb5, - 0xbeb5, 0xbeb5, 0xbeb5, 0xbeb5, 0xbeb5, 0x080c, 0x0d8c, 0x0096, - 0x6014, 0x2048, 0x080c, 0x7243, 0x009e, 0x080c, 0xb46d, 0x0005, - 0x00e6, 0x0096, 0x0026, 0x0016, 0x080c, 0xd312, 0x0568, 0x6014, - 0x2048, 0xa868, 0x9086, 0x0139, 0x11a8, 0xa898, 0x9086, 0x0056, - 0x1148, 0x080c, 0x577d, 0x0130, 0x2001, 0x0000, 0x900e, 0x2011, - 0x4000, 0x0028, 0x2001, 0x0030, 0x900e, 0x2011, 0x4005, 0x080c, - 0xd929, 0x0090, 0xa86c, 0xd0fc, 0x0178, 0xa807, 0x0000, 0x0016, - 0x6004, 0x908e, 0x0021, 0x0168, 0x908e, 0x003d, 0x0150, 0x001e, - 0xa86b, 0x0103, 0xa833, 0x0100, 0x001e, 0x002e, 0x009e, 0x00ee, - 0x0005, 0x001e, 0x0009, 0x0cc0, 0x0096, 0x6014, 0x2048, 0xa800, - 0x2048, 0xa86b, 0x0103, 0xa823, 0x8001, 0x009e, 0x0005, 0x00b6, - 0x6610, 0x2658, 0xb804, 0x9084, 0x00ff, 0x90b2, 0x000c, 0x1a0c, - 0x0d8c, 0x6604, 0x96b6, 0x004d, 0x1120, 0x080c, 0xd848, 0x0804, - 0xbf8c, 0x6604, 0x96b6, 0x0043, 0x1120, 0x080c, 0xd891, 0x0804, - 0xbf8c, 0x6604, 0x96b6, 0x004b, 0x1120, 0x080c, 0xd8bd, 0x0804, - 0xbf8c, 0x6604, 0x96b6, 0x0033, 0x1120, 0x080c, 0xd7da, 0x0804, - 0xbf8c, 0x6604, 0x96b6, 0x0028, 0x1120, 0x080c, 0xd57f, 0x0804, - 0xbf8c, 0x6604, 0x96b6, 0x0029, 0x1120, 0x080c, 0xd5c0, 0x0804, - 0xbf8c, 0x6604, 0x96b6, 0x001f, 0x1120, 0x080c, 0xb849, 0x0804, - 0xbf8c, 0x6604, 0x96b6, 0x0000, 0x1118, 0x080c, 0xbc12, 0x04e0, - 0x6604, 0x96b6, 0x0022, 0x1118, 0x080c, 0xb8dd, 0x04a8, 0x6604, - 0x96b6, 0x0035, 0x1118, 0x080c, 0xba0b, 0x0470, 0x6604, 0x96b6, - 0x0039, 0x1118, 0x080c, 0xbbab, 0x0438, 0x6604, 0x96b6, 0x003d, - 0x1118, 0x080c, 0xb915, 0x0400, 0x6604, 0x96b6, 0x0044, 0x1118, - 0x080c, 0xb951, 0x00c8, 0x6604, 0x96b6, 0x0049, 0x1118, 0x080c, - 0xb996, 0x0090, 0x6604, 0x96b6, 0x0041, 0x1118, 0x080c, 0xb980, - 0x0058, 0x91b6, 0x0015, 0x1110, 0x0063, 0x0030, 0x91b6, 0x0016, - 0x1128, 0x00be, 0x0804, 0xc299, 0x00be, 0x0005, 0x080c, 0xb527, - 0x0cd8, 0xbfaa, 0xbfb8, 0xbfaa, 0xbfff, 0xbfaa, 0xc1b6, 0xc2a6, - 0xbfaa, 0xbfaa, 0xbfaa, 0xc26f, 0xbfaa, 0xc285, 0x0096, 0x601f, - 0x0000, 0x6014, 0x2048, 0xa800, 0x2048, 0xa86b, 0x0103, 0x009e, - 0x0804, 0xb46d, 0xa001, 0xa001, 0x0005, 0x6604, 0x96b6, 0x0004, - 0x1130, 0x2001, 0x0001, 0x080c, 0x68a2, 0x0804, 0xb46d, 0x0005, - 0x00e6, 0x2071, 0x1800, 0x7090, 0x9086, 0x0074, 0x1540, 0x080c, - 0xebd5, 0x11b0, 0x6010, 0x00b6, 0x2058, 0x7030, 0xd08c, 0x0128, - 0xb800, 0xd0bc, 0x0110, 0xc0c5, 0xb802, 0x00f9, 0x00be, 0x2001, - 0x0006, 0x080c, 0x68b6, 0x080c, 0x3453, 0x080c, 0xb46d, 0x0098, - 0x2001, 0x000a, 0x080c, 0x68b6, 0x080c, 0x3453, 0x6003, 0x0001, - 0x6007, 0x0001, 0x080c, 0x98c3, 0x080c, 0x9d5e, 0x0020, 0x2001, - 0x0001, 0x080c, 0xc186, 0x00ee, 0x0005, 0x00d6, 0xb800, 0xd084, - 0x0160, 0x9006, 0x080c, 0x68a2, 0x2069, 0x184a, 0x6804, 0xd0a4, - 0x0120, 0x2001, 0x0006, 0x080c, 0x68e2, 0x00de, 0x0005, 0x00b6, - 0x0096, 0x00d6, 0x2011, 0x1824, 0x2204, 0x9086, 0x0074, 0x1904, - 0xc15b, 0x6010, 0x2058, 0xbaa0, 0x9286, 0x007e, 0x1120, 0x080c, - 0xc3f5, 0x0804, 0xc0c8, 0x2001, 0x180d, 0x2004, 0xd08c, 0x0904, - 0xc06a, 0x00d6, 0x080c, 0x79cb, 0x01a0, 0x0026, 0x2011, 0x0010, - 0x080c, 0x6e66, 0x002e, 0x0904, 0xc069, 0x080c, 0x5a0a, 0x1598, - 0x6014, 0x2048, 0xa807, 0x0000, 0xa86b, 0x0103, 0xa833, 0xdead, - 0x0450, 0x6010, 0x00b6, 0x2058, 0xb910, 0x00be, 0x9186, 0x00ff, - 0x0580, 0x0026, 0x2011, 0x8008, 0x080c, 0x6e66, 0x002e, 0x0548, - 0x6014, 0x9005, 0x090c, 0x0d8c, 0x2048, 0xa868, 0x9084, 0x00ff, - 0x9086, 0x0039, 0x1140, 0x2001, 0x0030, 0x900e, 0x2011, 0x4009, - 0x080c, 0xd929, 0x0040, 0x6014, 0x2048, 0xa807, 0x0000, 0xa86b, - 0x0103, 0xa833, 0xdead, 0x6010, 0x2058, 0xb9a0, 0x0016, 0x080c, - 0x3453, 0x080c, 0xb46d, 0x001e, 0x080c, 0x352d, 0x00de, 0x0804, - 0xc160, 0x00de, 0x080c, 0xc3ea, 0x6010, 0x2058, 0xbaa0, 0x9286, - 0x0080, 0x1510, 0x6014, 0x9005, 0x01a8, 0x2048, 0xa868, 0x9084, - 0x00ff, 0x9086, 0x0039, 0x1140, 0x2001, 0x0000, 0x900e, 0x2011, - 0x4000, 0x080c, 0xd929, 0x0030, 0xa807, 0x0000, 0xa86b, 0x0103, - 0xa833, 0x0200, 0x2001, 0x0006, 0x080c, 0x68b6, 0x080c, 0x3453, - 0x080c, 0xb46d, 0x0804, 0xc160, 0x080c, 0xc16e, 0x6014, 0x9005, - 0x0190, 0x2048, 0xa86c, 0xd0f4, 0x01e8, 0xa868, 0x9084, 0x00ff, - 0x9086, 0x0039, 0x1d08, 0x2001, 0x0000, 0x900e, 0x2011, 0x4000, - 0x080c, 0xd929, 0x08f8, 0x080c, 0xc164, 0x0160, 0x9006, 0x080c, - 0x68a2, 0x2001, 0x0004, 0x080c, 0x68e2, 0x2001, 0x0007, 0x080c, - 0x68b6, 0x08a0, 0x2001, 0x0004, 0x080c, 0x68b6, 0x6003, 0x0001, - 0x6007, 0x0003, 0x080c, 0x98c3, 0x080c, 0x9d5e, 0x0804, 0xc160, - 0xb85c, 0xd0e4, 0x0178, 0x080c, 0xd752, 0x080c, 0x79cb, 0x0118, - 0xd0dc, 0x1904, 0xc08a, 0x2011, 0x1837, 0x2204, 0xc0ad, 0x2012, - 0x0804, 0xc08a, 0x080c, 0xd793, 0x2011, 0x1837, 0x2204, 0xc0a5, - 0x2012, 0x0006, 0x080c, 0xedb6, 0x000e, 0x1904, 0xc08a, 0xc0b5, - 0x2012, 0x2001, 0x0006, 0x080c, 0x68b6, 0x9006, 0x080c, 0x68a2, - 0x00c6, 0x2001, 0x180f, 0x2004, 0xd09c, 0x0520, 0x00f6, 0x2079, - 0x0100, 0x00e6, 0x2071, 0x1800, 0x700c, 0x9084, 0x00ff, 0x78e6, - 0x707e, 0x7010, 0x78ea, 0x7082, 0x908c, 0x00ff, 0x00ee, 0x780c, - 0xc0b5, 0x780e, 0x00fe, 0x080c, 0x278d, 0x00f6, 0x2100, 0x900e, - 0x080c, 0x2744, 0x795e, 0x00fe, 0x9186, 0x0081, 0x01f0, 0x2009, - 0x0081, 0x00e0, 0x2009, 0x00ef, 0x00f6, 0x2079, 0x0100, 0x79ea, - 0x78e7, 0x0000, 0x7932, 0x7936, 0x780c, 0xc0b5, 0x780e, 0x00fe, - 0x080c, 0x278d, 0x00f6, 0x2079, 0x1800, 0x7982, 0x2100, 0x900e, - 0x797e, 0x080c, 0x2744, 0x795e, 0x00fe, 0x8108, 0x080c, 0x6905, - 0x2b00, 0x00ce, 0x1904, 0xc08a, 0x6012, 0x2009, 0x180f, 0x210c, - 0xd19c, 0x0150, 0x2009, 0x027c, 0x210c, 0x918c, 0x00ff, 0xb912, - 0x2009, 0x027d, 0x210c, 0xb916, 0x2001, 0x0002, 0x080c, 0x68b6, - 0x6023, 0x0001, 0x6003, 0x0001, 0x6007, 0x0002, 0x080c, 0x98c3, - 0x080c, 0x9d5e, 0x0028, 0x080c, 0xbec0, 0x2001, 0x0001, 0x0431, - 0x00de, 0x009e, 0x00be, 0x0005, 0x2001, 0x1810, 0x2004, 0xd0a4, - 0x0120, 0x2001, 0x184b, 0x2004, 0xd0ac, 0x0005, 0x00e6, 0x080c, - 0xf309, 0x0190, 0x2071, 0x0260, 0x7108, 0x720c, 0x918c, 0x00ff, - 0x1118, 0x9284, 0xff00, 0x0140, 0x6010, 0x2058, 0xb8a0, 0x9084, - 0xff80, 0x1110, 0xb912, 0xba16, 0x00ee, 0x0005, 0x2030, 0x9005, - 0x0158, 0x2001, 0x0007, 0x080c, 0x68b6, 0x080c, 0x5a0a, 0x1120, - 0x2001, 0x0007, 0x080c, 0x68e2, 0x2600, 0x9005, 0x11b0, 0x6014, - 0x0096, 0x2048, 0xa86c, 0x009e, 0xd0fc, 0x1178, 0x0036, 0x0046, - 0x6010, 0x00b6, 0x2058, 0xbba0, 0x00be, 0x2021, 0x0004, 0x2011, - 0x8014, 0x080c, 0x4e48, 0x004e, 0x003e, 0x080c, 0x3453, 0x6020, - 0x9086, 0x000a, 0x1108, 0x0005, 0x0804, 0xb46d, 0x00b6, 0x00e6, - 0x0026, 0x0016, 0x2071, 0x1800, 0x7090, 0x9086, 0x0014, 0x1904, - 0xc265, 0x2001, 0x180d, 0x2004, 0xd08c, 0x0904, 0xc218, 0x00d6, - 0x080c, 0x79cb, 0x01a0, 0x0026, 0x2011, 0x0010, 0x080c, 0x6e66, - 0x002e, 0x0904, 0xc217, 0x080c, 0x5a0a, 0x1598, 0x6014, 0x2048, - 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0x2004, 0x601a, 0x6003, 0x000c, 0x0005, 0x6034, 0x908c, 0xff00, - 0x810f, 0x9186, 0x0039, 0x0118, 0x9186, 0x0035, 0x1118, 0x2001, - 0x1989, 0x0010, 0x2001, 0x198a, 0x2004, 0x601a, 0x6003, 0x000e, - 0x0005, 0x9182, 0x0092, 0x1220, 0x9182, 0x0085, 0x0208, 0x0012, - 0x0804, 0xb527, 0xcd07, 0xcd07, 0xcd07, 0xcd07, 0xcd09, 0xcd47, - 0xcd07, 0xcd07, 0xcd07, 0xcd07, 0xcd07, 0xcd07, 0xcd07, 0x080c, - 0x0d8c, 0x0096, 0x6010, 0x00b6, 0x2058, 0xb800, 0x00be, 0xd0bc, - 0x0160, 0x6034, 0x908c, 0xff00, 0x810f, 0x9186, 0x0039, 0x0118, - 0x9186, 0x0035, 0x1110, 0x009e, 0x04f0, 0x080c, 0xd312, 0x1118, - 0x080c, 0xd51b, 0x00a0, 0x6014, 0x2048, 0x080c, 0xda98, 0x1110, - 0x080c, 0xd51b, 0xa86b, 0x0103, 0x080c, 0xda29, 0x080c, 0x7243, - 0x00b6, 0x6010, 0x2058, 0xba3c, 0x080c, 0x6ac4, 0x00be, 0x2009, - 0x026e, 0x210c, 0x613a, 0x2009, 0x026f, 0x210c, 0x613e, 0x6000, - 0x6036, 0x6003, 0x0013, 0x080c, 0xb4a8, 0x009e, 0x0005, 0x6010, - 0x00b6, 0x2058, 0xb800, 0x00be, 0xd0bc, 0x05a0, 0x6034, 0x908c, - 0xff00, 0x810f, 0x9186, 0x0035, 0x0130, 0x9186, 0x001e, 0x0118, - 0x9186, 0x0039, 0x1538, 0x00d6, 0x2c68, 0x080c, 0xd9bf, 0x11f0, - 0x080c, 0xb417, 0x01d8, 0x6106, 0x6003, 0x0001, 0x6023, 0x0001, - 0x6910, 0x6112, 0x692c, 0x612e, 0x6930, 0x6132, 0x6934, 0x918c, - 0x00ff, 0x6136, 0x6938, 0x613a, 0x693c, 0x613e, 0x695c, 0x615e, - 0x080c, 0xd7c0, 0x2009, 0x8020, 0x080c, 0x98bc, 0x2d60, 0x00de, - 0x0804, 0xb46d, 0x0096, 0x6014, 0x2048, 0x080c, 0xd312, 0x0500, - 0xa86b, 0x0103, 0xa884, 0xd0b4, 0x0128, 0xc0ec, 0xa886, 0xa87f, - 0x0006, 0x0048, 0xd0bc, 0x0118, 0xa87f, 0x0002, 0x0020, 0xa87f, - 0x0005, 0x080c, 0xd630, 0xa87b, 0x0000, 0x080c, 0x7243, 0x080c, - 0xd51b, 0x00b6, 0x6010, 0x2058, 0xba3c, 0x080c, 0x6ac4, 0x00be, - 0x009e, 0x0804, 0xb46d, 0x0016, 0x0096, 0x6014, 0x2048, 0x080c, - 0xd312, 0x0140, 0xa86b, 0x0103, 0xa87f, 0x0028, 0xa87b, 0x0000, - 0x080c, 0x7243, 0x009e, 0x001e, 0x9186, 0x0013, 0x0148, 0x9186, - 0x0014, 0x0130, 0x9186, 0x0027, 0x0118, 0x080c, 0xb527, 0x0068, - 0x080c, 0x9c98, 0x080c, 0xd51b, 0x00b6, 0x6010, 0x2058, 0xba3c, - 0x080c, 0x6ac4, 0x00be, 0x080c, 0xb4a8, 0x0005, 0x0056, 0x0066, - 0x0096, 0x00a6, 0x2029, 0x0001, 0x9182, 0x0101, 0x1208, 0x0010, - 0x2009, 0x0100, 0x2130, 0x8304, 0x9098, 0x0018, 0x2009, 0x0020, - 0x2011, 0x002a, 0x080c, 0xce37, 0x96b2, 0x0020, 0xb004, 0x904d, - 0x0110, 0x080c, 0x1013, 0x080c, 0x1061, 0x0520, 0x8528, 0xa86b, - 0x0110, 0xa86f, 0x0000, 0x2920, 0xb406, 0x968a, 0x003d, 0x1228, - 0x2608, 0x2011, 0x001c, 0x0499, 0x00a8, 0x96b2, 0x003c, 0x2009, - 0x003c, 0x2950, 0x2011, 0x001c, 0x0451, 0x0c28, 0x2001, 0x0205, - 0x2003, 0x0000, 0x00ae, 0x852f, 0x95ad, 0x0003, 0xb56a, 0x95ac, - 0x0000, 0x0048, 0x2001, 0x0205, 0x2003, 0x0000, 0x00ae, 0x852f, - 0x95ad, 0x0003, 0xb56a, 0x009e, 0x006e, 0x005e, 0x0005, 0x00a6, - 0x89ff, 0x0158, 0xa804, 0x9055, 0x0130, 0xa807, 0x0000, 0x080c, - 0x7243, 0x2a48, 0x0cb8, 0x080c, 0x7243, 0x00ae, 0x0005, 0x00f6, - 0x2079, 0x0200, 0x7814, 0x9085, 0x0080, 0x7816, 0xd184, 0x0108, - 0x8108, 0x810c, 0x20a9, 0x0001, 0xa860, 0x20e8, 0xa85c, 0x9200, - 0x20a0, 0x20e1, 0x0000, 0x2300, 0x9e00, 0x2098, 0x4003, 0x8318, - 0x9386, 0x0020, 0x1148, 0x2018, 0x2300, 0x9e00, 0x2098, 0x7814, - 0x8000, 0x9085, 0x0080, 0x7816, 0x8109, 0x1d80, 0x7814, 0x9084, - 0xff7f, 0x7816, 0x00fe, 0x0005, 0x6920, 0x9186, 0x0003, 0x0148, - 0x9186, 0x0002, 0x0130, 0x9186, 0x0008, 0x0118, 0x9186, 0x000a, - 0x1510, 0x00c6, 0x00d6, 0x00e6, 0x2d60, 0x0096, 0x6014, 0x2048, - 0x080c, 0xd312, 0x0190, 0x6120, 0x9186, 0x000a, 0x01a8, 0x9186, - 0x0008, 0x01b8, 0x00c9, 0x2001, 0x0006, 0xa984, 0xc1d5, 0x080c, - 0x748d, 0x080c, 0x7237, 0x080c, 0xd51b, 0x009e, 0x080c, 0xb4a8, - 0x00ee, 0x00de, 0x00ce, 0x0005, 0xa87f, 0x0013, 0x080c, 0x7243, - 0x0ca0, 0x080c, 0xbec0, 0x0c88, 0xa880, 0xd0cc, 0x0140, 0x0096, - 0xa87c, 0x2048, 0x080c, 0x1013, 0x009e, 0xa87f, 0x0000, 0x0005, - 0x00c6, 0x702c, 0xd084, 0x1170, 0x6008, 0x2060, 0x6020, 0x9086, - 0x0002, 0x1140, 0x6104, 0x9186, 0x0085, 0x0118, 0x9186, 0x008b, - 0x1108, 0x9006, 0x00ce, 0x0005, 0x0066, 0x0126, 0x2091, 0x8000, - 0x2031, 0x0001, 0x6020, 0x9084, 0x000f, 0x0083, 0x012e, 0x006e, - 0x0005, 0x0126, 0x2091, 0x8000, 0x0066, 0x2031, 0x0000, 0x6020, - 0x9084, 0x000f, 0x001b, 0x006e, 0x012e, 0x0005, 0xcf0e, 0xcf0e, - 0xcf09, 0xcf32, 0xcee6, 0xcf09, 0xcee8, 0xcf09, 0xdaee, 0x9714, - 0xed76, 0xcf09, 0xcf09, 0xcee6, 0xcee6, 0xcee6, 0x080c, 0x0d8c, - 0x86ff, 0x0120, 0x080c, 0x6dc3, 0x190c, 0xcf32, 0x0036, 0x6014, - 0x0096, 0x2048, 0xa884, 0x009e, 0xd0cc, 0x0118, 0x2019, 0x000c, - 0x0060, 0xd094, 0x0118, 0x2019, 0x000d, 0x0038, 0xd0dc, 0x0118, - 0x2019, 0x0004, 0x0010, 0x2019, 0x0010, 0x080c, 0xea1b, 0x003e, - 0x0005, 0x9006, 0x0005, 0x9085, 0x0001, 0x0005, 0x0096, 0x86ff, - 0x11e8, 0x6014, 0x2048, 0x080c, 0xd312, 0x01d0, 0x6043, 0xffff, - 0xa868, 0x9086, 0x0139, 0x1128, 0xa87f, 0x0005, 0xa887, 0x0000, - 0x0028, 0x900e, 0x2001, 0x0005, 0x080c, 0x748d, 0x080c, 0xd630, - 0x080c, 0x7237, 0x080c, 0xb4a8, 0x9085, 0x0001, 0x009e, 0x0005, - 0x9006, 0x0ce0, 0x080c, 0xafdc, 0x080c, 0xdaa6, 0x6043, 0xffff, - 0x908a, 0x0014, 0x1a0c, 0x0d8c, 0x002b, 0x0106, 0x080c, 0xaff8, - 0x010e, 0x0005, 0xcf52, 0xcf8d, 0xcf54, 0xcfb5, 0xcf88, 0xcf52, - 0xcf09, 0xcf0e, 0xcf0e, 0xcf09, 0xcf09, 0xcf09, 0xcf09, 0xcf09, - 0xcf09, 0xcf09, 0x080c, 0x0d8c, 0x86ff, 0x1578, 0x6020, 0x9086, - 0x0006, 0x0558, 0x0096, 0x6014, 0x2048, 0x080c, 0xd312, 0x0168, - 0xa880, 0xd0cc, 0x0140, 0x0096, 0xc0cc, 0xa882, 0xa87c, 0x2048, - 0x080c, 0x1013, 0x009e, 0x080c, 0xd630, 0x009e, 0x080c, 0xda03, - 0x2009, 0x2000, 0x2001, 0x0338, 0x2004, 0xd0a4, 0x0120, 0x8109, - 0x090c, 0x0d8c, 0x0cb8, 0x6023, 0x0002, 0x6007, 0x0085, 0x6003, - 0x000b, 0x2009, 0x8020, 0x080c, 0x989e, 0x9085, 0x0001, 0x0005, - 0x0066, 0x080c, 0x1b6e, 0x006e, 0x0838, 0x00e6, 0x2071, 0x19eb, - 0x7030, 0x9c06, 0x1128, 0x080c, 0xa7da, 0x00ee, 0x0804, 0xcf54, - 0x6020, 0x9084, 0x000f, 0x9086, 0x0006, 0x1150, 0x0086, 0x0096, - 0x2049, 0x0001, 0x2c40, 0x080c, 0xa92b, 0x009e, 0x008e, 0x0040, - 0x0066, 0x080c, 0xa6d2, 0x190c, 0x0d8c, 0x080c, 0xa6e2, 0x006e, - 0x00ee, 0x1904, 0xcf54, 0x0804, 0xcf09, 0x0036, 0x00e6, 0x2071, - 0x19eb, 0x704c, 0x9c06, 0x1138, 0x901e, 0x080c, 0xa85a, 0x00ee, - 0x003e, 0x0804, 0xcf54, 0x080c, 0xaa65, 0x00ee, 0x003e, 0x1904, - 0xcf54, 0x0804, 0xcf09, 0x00c6, 0x0066, 0x6020, 0x9084, 0x000f, - 0x001b, 0x006e, 0x00ce, 0x0005, 0xcfeb, 0xd0d5, 0xd247, 0xcff1, - 0xb4a8, 0xcfeb, 0xea11, 0xda70, 0xd0d5, 0x96db, 0xd2d3, 0xcfe4, - 0xcfe4, 0xcfe4, 0xcfe4, 0xcfe4, 0x080c, 0x0d8c, 0x080c, 0xd541, - 0x1110, 0x080c, 0xbec0, 0x0005, 0x0804, 0xb46d, 0x601b, 0x0001, - 0x0005, 0x080c, 0xd312, 0x0130, 0x6014, 0x0096, 0x2048, 0x2c00, - 0xa89a, 0x009e, 0x080c, 0xafdc, 0x080c, 0xdaa6, 0x908a, 0x0014, - 0x1a0c, 0x0d8c, 0x0013, 0x0804, 0xaff8, 0xd015, 0xd017, 0xd041, - 0xd055, 0xd082, 0xd015, 0xcfeb, 0xcfeb, 0xcfeb, 0xd05c, 0xd05c, - 0xd015, 0xd015, 0xd015, 0xd015, 0xd066, 0x080c, 0x0d8c, 0x00e6, - 0x6014, 0x0096, 0x2048, 0xa884, 0xc0b5, 0xa886, 0x009e, 0x2071, - 0x19eb, 0x7030, 0x9c06, 0x01d0, 0x0066, 0x080c, 0xa6d2, 0x190c, - 0x0d8c, 0x080c, 0xa6e2, 0x006e, 0x080c, 0xda03, 0x6007, 0x0085, - 0x6003, 0x000b, 0x6023, 0x0002, 0x2001, 0x198a, 0x2004, 0x601a, - 0x2009, 0x8020, 0x080c, 0x989e, 0x00ee, 0x0005, 0x601b, 0x0001, - 0x0cd8, 0x0096, 0x6014, 0x2048, 0xa884, 0xc0b5, 0xa886, 0x009e, - 0x080c, 0xda03, 0x6007, 0x0085, 0x6003, 0x000b, 0x6023, 0x0002, - 0x2009, 0x8020, 0x080c, 0x989e, 0x0005, 0x080c, 0xafdc, 0x080c, - 0xb1e4, 0x080c, 0xaff8, 0x0c28, 0x0096, 0x601b, 0x0001, 0x6014, - 0x2048, 0xa884, 0xc0b5, 0xa886, 0x009e, 0x0005, 0x080c, 0x59fe, - 0x01b8, 0x6014, 0x0096, 0x904d, 0x0190, 0xa868, 0xa86b, 0x0103, - 0xa87f, 0x0006, 0x9086, 0x0139, 0x1150, 0xa86b, 0x0139, 0xa87f, - 0x0030, 0xa89b, 0x4005, 0xa89f, 0x0004, 0x080c, 0x7243, 0x009e, - 0x0804, 0xb46d, 0x6014, 0x0096, 0x904d, 0x0904, 0xd0d0, 0xa980, - 0xd1e4, 0x1160, 0x611c, 0xd1fc, 0x0904, 0xd0d0, 0x6110, 0x00b6, - 0x2158, 0xb93c, 0x8109, 0x0208, 0xb93e, 0x00be, 0x080c, 0xaff8, - 0x2001, 0x180f, 0x2004, 0xd0c4, 0x0110, 0x009e, 0x0005, 0xa888, - 0x009e, 0x8003, 0x800b, 0x810b, 0x9108, 0x611a, 0x2001, 0x0030, - 0x2c08, 0x0026, 0x621c, 0x080c, 0x1742, 0x2001, 0x030c, 0x2004, - 0x002e, 0x9086, 0x0041, 0x1198, 0x6014, 0x0096, 0x904d, 0x090c, - 0x0d8c, 0xa884, 0xd0f4, 0x1130, 0xc0f5, 0xa886, 0x009e, 0x601b, - 0x0002, 0x0068, 0x009e, 0x00c6, 0x080c, 0x2220, 0x00ce, 0x6000, - 0x9086, 0x0004, 0x1120, 0x2009, 0x0048, 0x080c, 0xb50a, 0x0005, - 0x009e, 0x080c, 0x1b6e, 0x0804, 0xd041, 0x6000, 0x908a, 0x0014, - 0x1a0c, 0x0d8c, 0x000b, 0x0005, 0xd0ec, 0xcfee, 0xd0ee, 0xd0ec, - 0xd0ee, 0xd0ee, 0xcfec, 0xd0ec, 0xcfe6, 0xcfe6, 0xd0ec, 0xd0ec, - 0xd0ec, 0xd0ec, 0xd0ec, 0xd0ec, 0x080c, 0x0d8c, 0x6010, 0x00b6, - 0x2058, 0xb804, 0x9084, 0x00ff, 0x00be, 0x908a, 0x000c, 0x1a0c, - 0x0d8c, 0x00b6, 0x0013, 0x00be, 0x0005, 0xd109, 0xd1de, 0xd10b, - 0xd14b, 0xd10b, 0xd14b, 0xd10b, 0xd119, 0xd109, 0xd14b, 0xd109, - 0xd13a, 0x080c, 0x0d8c, 0x6004, 0x908e, 0x0016, 0x05c0, 0x908e, - 0x0004, 0x05a8, 0x908e, 0x0002, 0x0590, 0x908e, 0x0052, 0x0904, - 0xd1da, 0x6004, 0x080c, 0xd541, 0x0904, 0xd1f7, 0x908e, 0x0004, - 0x1110, 0x080c, 0x3453, 0x908e, 0x0021, 0x0904, 0xd1fb, 0x908e, - 0x0022, 0x0904, 0xd242, 0x908e, 0x003d, 0x0904, 0xd1fb, 0x908e, - 0x0039, 0x0904, 0xd1ff, 0x908e, 0x0035, 0x0904, 0xd1ff, 0x908e, - 0x001e, 0x0178, 0x908e, 0x0001, 0x1140, 0x6010, 0x2058, 0xb804, - 0x9084, 0x00ff, 0x9086, 0x0006, 0x0110, 0x080c, 0x3424, 0x080c, - 0xbec0, 0x0804, 0xb4a8, 0x00c6, 0x00d6, 0x6104, 0x9186, 0x0016, - 0x0904, 0xd1cb, 0x9186, 0x0002, 0x1904, 0xd1a0, 0x2001, 0x1837, - 0x2004, 0xd08c, 0x11c8, 0x080c, 0x79cb, 0x11b0, 0x080c, 0xda4e, - 0x0138, 0x080c, 0x79ee, 0x1120, 0x080c, 0x78d4, 0x0804, 0xd22b, - 0x2001, 0x1980, 0x2003, 0x0001, 0x2001, 0x1800, 0x2003, 0x0001, - 0x080c, 0x78fa, 0x0804, 0xd22b, 0x6010, 0x2058, 0xb8a0, 0x9086, - 0x0080, 0x0130, 0x2001, 0x1837, 0x2004, 0xd0ac, 0x1904, 0xd22b, - 0x6014, 0x9005, 0x1904, 0xd22b, 0xb8a0, 0x9082, 0x0081, 0x1a04, - 0xd22b, 0xb840, 0x9084, 0x00ff, 0x9005, 0x0190, 0x8001, 0xb842, - 0x6017, 0x0000, 0x6023, 0x0007, 0x601b, 0x0398, 0x604b, 0x0000, - 0x080c, 0xb417, 0x0128, 0x2b00, 0x6012, 0x6023, 0x0001, 0x0458, - 0x00de, 0x00ce, 0x6004, 0x908e, 0x0002, 0x11a0, 0x6010, 0x2058, - 0xb8a0, 0x9086, 0x007e, 0x1170, 0x2009, 0x1837, 0x2104, 0xc085, - 0x200a, 0x00e6, 0x2071, 0x1800, 0x080c, 0x62e2, 0x00ee, 0x080c, - 0xbec0, 0x0030, 0x080c, 0xbec0, 0x080c, 0x3424, 0x080c, 0xda63, - 0x00e6, 0x0126, 0x2091, 0x8000, 0x080c, 0x3453, 0x012e, 0x00ee, - 0x080c, 0xb4a8, 0x0005, 0x2001, 0x0002, 0x080c, 0x68b6, 0x6003, - 0x0001, 0x6007, 0x0002, 0x080c, 0x98c3, 0x080c, 0x9d5e, 0x00de, - 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0x210c, 0x9102, 0x0220, 0x7030, 0x9084, 0x0003, 0x0130, 0x00ee, - 0x6017, 0x0000, 0x602f, 0x0007, 0x00b0, 0x00ee, 0x080c, 0xeb9a, - 0x1190, 0x9686, 0x0006, 0x1140, 0x0026, 0x6210, 0x2258, 0xbaa0, - 0x900e, 0x080c, 0x3473, 0x002e, 0x080c, 0x6a12, 0x6007, 0x000a, - 0x00de, 0x0804, 0xddb8, 0x6007, 0x000b, 0x00de, 0x0804, 0xddb8, - 0x080c, 0x3424, 0x080c, 0xda63, 0x6007, 0x0001, 0x0804, 0xddb8, - 0x080c, 0xf12d, 0x1904, 0xdffc, 0x080c, 0x355b, 0x1904, 0xdffc, - 0x00d6, 0x00e6, 0x2071, 0x0260, 0x7034, 0x90b4, 0x0003, 0x1938, - 0x2031, 0x1824, 0x2634, 0x9632, 0x0a10, 0x90b2, 0x0014, 0x0a04, - 0xdc5f, 0x7030, 0x9084, 0x0003, 0x1904, 0xdc5f, 0x00ee, 0x00de, - 0x6610, 0x2658, 0xbe04, 0x9686, 0x0707, 0x0990, 0x0026, 0x6210, - 0x2258, 0xbaa0, 0x900e, 0x080c, 0x3473, 0x002e, 0x6007, 0x000c, - 0x2001, 0x0001, 0x080c, 0xf310, 0x0804, 0xddb8, 0x080c, 0x6de9, - 0x1140, 0x2001, 0x1837, 0x2004, 0x9084, 0x0009, 0x9086, 0x0008, - 0x1110, 0x0804, 0xdbb6, 0x080c, 0x6d85, 0x6610, 0x2658, 0xbe04, - 0x9684, 0x00ff, 0x9082, 0x0006, 0x06c8, 0x1138, 0x0026, 0x2001, - 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0x9082, 0x0006, 0x06a0, 0x0150, 0x96b4, 0xff00, 0x8637, 0x9686, - 0x0004, 0x0120, 0x9686, 0x0006, 0x1904, 0xdc80, 0x080c, 0xebd5, - 0x1138, 0x080c, 0xeaca, 0x1120, 0x6007, 0x0010, 0x0804, 0xddb8, - 0x0046, 0x6410, 0x2458, 0xbca0, 0x0046, 0x080c, 0x3424, 0x080c, - 0xda63, 0x004e, 0x0016, 0x9006, 0x2009, 0x184b, 0x210c, 0xd1a4, - 0x0148, 0x2009, 0x0029, 0x080c, 0xef3b, 0x6010, 0x2058, 0xb800, - 0xc0e5, 0xb802, 0x001e, 0x004e, 0x6007, 0x0001, 0x0448, 0x080c, - 0xedb6, 0x0198, 0x0016, 0x968c, 0x00ff, 0x9186, 0x0002, 0x0160, - 0x9186, 0x0003, 0x0148, 0x001e, 0x96b4, 0xff00, 0x8637, 0x9686, - 0x0006, 0x0920, 0x0804, 0xdc80, 0x001e, 0x6017, 0x1900, 0x6007, - 0x0009, 0x0070, 0x080c, 0x355b, 0x1904, 0xdffc, 0x080c, 0xf12d, - 0x1904, 0xdffc, 0x080c, 0xe1dd, 0x1904, 0xdc80, 0x6007, 0x0012, - 0x6003, 0x0001, 0x080c, 0x98c3, 0x080c, 0x9d5e, 0x0005, 0x6007, - 0x0001, 0x6003, 0x0001, 0x080c, 0x98c3, 0x080c, 0x9d5e, 0x0cb0, - 0x6007, 0x0005, 0x0c68, 0x080c, 0xf12d, 0x1904, 0xdffc, 0x080c, - 0x355b, 0x1904, 0xdffc, 0x080c, 0xe1dd, 0x1904, 0xdc80, 0x6007, - 0x0020, 0x6003, 0x0001, 0x080c, 0x98c3, 0x080c, 0x9d5e, 0x0005, - 0x080c, 0x355b, 0x1904, 0xdffc, 0x6007, 0x0023, 0x6003, 0x0001, - 0x080c, 0x98c3, 0x080c, 0x9d5e, 0x0005, 0x080c, 0xf12d, 0x1904, - 0xdffc, 0x080c, 0x355b, 0x1904, 0xdffc, 0x080c, 0xe1dd, 0x1904, - 0xdc80, 0x0016, 0x0026, 0x00e6, 0x2071, 0x0260, 0x2c08, 0x2011, - 0x1820, 0x2214, 0x703c, 0x9206, 0x11e0, 0x2011, 0x181f, 0x2214, - 0x7038, 0x9084, 0x00ff, 0x9206, 0x11a0, 0x7240, 0x080c, 0xd300, - 0x0570, 0x2260, 0x6008, 0x9086, 0xffff, 0x0120, 0x7244, 0x6008, - 0x9206, 0x1528, 0x6020, 0x9086, 0x0007, 0x1508, 0x080c, 0xb46d, - 0x04a0, 0x7244, 0x9286, 0xffff, 0x0180, 0x2c08, 0x080c, 0xd300, - 0x01b0, 0x2260, 0x7240, 0x6008, 0x9206, 0x1188, 0x6010, 0x9190, - 0x0004, 0x2214, 0x9206, 0x01b8, 0x0050, 0x7240, 0x2c08, 0x9006, - 0x080c, 0xef05, 0x1180, 0x7244, 0x9286, 0xffff, 0x01b0, 0x2160, - 0x6007, 0x0026, 0x6017, 0x1700, 0x7214, 0x9296, 0xffff, 0x1180, - 0x6007, 0x0025, 0x0068, 0x6020, 0x9086, 0x0007, 0x1d80, 0x6004, - 0x9086, 0x0024, 0x1110, 0x080c, 0xb46d, 0x2160, 0x6007, 0x0025, - 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0xddbf, 0x080c, 0x59fa, 0xd0e4, 0x0904, 0xdf39, 0x2071, 0x026c, - 0x7010, 0x603a, 0x7014, 0x603e, 0x7108, 0x720c, 0x080c, 0x6e27, - 0x0140, 0x6010, 0x2058, 0xb810, 0x9106, 0x1118, 0xb814, 0x9206, - 0x0510, 0x080c, 0x6e23, 0x15b8, 0x2069, 0x1800, 0x6880, 0x9206, - 0x1590, 0x687c, 0x9106, 0x1578, 0x7210, 0x080c, 0xd300, 0x0590, - 0x080c, 0xe0ca, 0x0578, 0x080c, 0xefb7, 0x0560, 0x622e, 0x6007, - 0x0036, 0x6003, 0x0001, 0x2009, 0x8020, 0x080c, 0x98bc, 0x00ce, - 0x00de, 0x00ee, 0x0005, 0x7214, 0x9286, 0xffff, 0x0150, 0x080c, - 0xd300, 0x01c0, 0x9280, 0x0002, 0x2004, 0x7110, 0x9106, 0x1190, - 0x08e0, 0x7210, 0x2c08, 0x9085, 0x0001, 0x080c, 0xef05, 0x2c10, - 0x2160, 0x0140, 0x0890, 0x6007, 0x0037, 0x602f, 0x0009, 0x6017, - 0x1500, 0x08b8, 0x6007, 0x0037, 0x602f, 0x0003, 0x6017, 0x1700, - 0x0880, 0x6007, 0x0012, 0x0868, 0x080c, 0x355b, 0x1904, 0xdffc, - 0x6010, 0x2058, 0xb804, 0x9084, 0xff00, 0x8007, 0x9086, 0x0006, - 0x1904, 0xddbf, 0x00e6, 0x00d6, 0x00c6, 0x080c, 0x59fa, 0xd0e4, - 0x0904, 0xdfbf, 0x2069, 0x1800, 0x2071, 0x026c, 0x7008, 0x603a, - 0x720c, 0x623e, 0x9286, 0xffff, 0x1158, 0x7208, 0x00c6, 0x2c08, - 0x9085, 0x0001, 0x080c, 0xef05, 0x2c10, 0x00ce, 0x0904, 0xdfb2, - 0x080c, 0xd300, 0x0904, 0xdfb2, 0x7108, 0x9280, 0x0002, 0x2004, - 0x9106, 0x1904, 0xdfb2, 0x00c6, 0x0026, 0x2260, 0x0066, 0x2031, - 0x0001, 0x6020, 0x9084, 0x000f, 0x9086, 0x0006, 0x190c, 0x0d8c, - 0x080c, 0xcf32, 0x006e, 0x002e, 0x00ce, 0x7118, 0x918c, 0xff00, - 0x810f, 0x9186, 0x0001, 0x0178, 0x9186, 0x0005, 0x0118, 0x9186, - 0x0007, 0x1198, 0x9280, 0x0005, 0x2004, 0x9005, 0x0170, 0x080c, - 0xe0ca, 0x0904, 0xdf32, 0x0056, 0x7510, 0x7614, 0x080c, 0xefd0, - 0x005e, 0x00ce, 0x00de, 0x00ee, 0x0005, 0x6007, 0x003b, 0x602f, - 0x0009, 0x6017, 0x2a00, 0x6003, 0x0001, 0x2009, 0x8020, 0x080c, - 0x98bc, 0x0c78, 0x6007, 0x003b, 0x602f, 0x0003, 0x6017, 0x0300, - 0x6003, 0x0001, 0x2009, 0x8020, 0x080c, 0x98bc, 0x0c10, 0x6007, - 0x003b, 0x602f, 0x000b, 0x6017, 0x0000, 0x0804, 0xdf09, 0x00e6, - 0x0026, 0x080c, 0x6de9, 0x0550, 0x080c, 0x6d85, 0x080c, 0xf1b3, - 0x1518, 0x2071, 0x1800, 0x70dc, 0x9085, 0x0003, 0x70de, 0x00f6, - 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0x3c0a, 0x001b, 0x80a0, 0x0000, 0x3c04, 0x0002, 0x0c00, 0x0010, - 0xff0c, 0x0003, 0x00da, 0x0011, 0x3be8, 0x0010, 0x001b, 0x000b, - 0x10ae, 0x0010, 0xc014, 0x0000, 0xc013, 0x0000, 0xc010, 0x0015, - 0x000f, 0x0010, 0x0000, 0x0003, 0x00da, 0x0011, 0x3be8, 0x0000, - 0x0015, 0x000b, 0x10ba, 0x0014, 0x012e, 0x0004, 0x0140, 0x0015, - 0x0039, 0x0000, 0x8000, 0x0017, 0x8000, 0x0004, 0x0125, 0x0004, - 0x0137, 0x0004, 0x0110, 0x0003, 0x002f, 0x0011, 0x3be8, 0x0000, - 0x0016, 0x001b, 0x10cc, 0x0001, 0x0fe8, 0x0010, 0x0000, 0x0003, - 0x10c6, 0x0001, 0x0fe8, 0x0000, 0x0002, 0x0003, 0x10c6, 0x0015, - 0x0039, 0x0010, 0x1010, 0x0003, 0x00da, 0x0015, 0x0039, 0x0000, - 0x5040, 0x0015, 0x00b8, 0x0000, 0x0008, 0x0004, 0x0948, 0x0003, - 0x00da, 0x0011, 0x3be8, 0x0010, 0x0017, 0x001b, 0x10d1, 0x0010, - 0x3cc3, 0x0003, 0x00da, 0x0011, 0x3be8, 0x0010, 0x0018, 0x000b, - 0x10d6, 0x0000, 0x3cc2, 0x0003, 0x00da, 0x0005, 0x00ce, 0x0000, - 0x0001, 0x0000, 0x3bcf, 0x0004, 0x0900, 0x0015, 0x0039, 0x0000, - 0x8000, 0x0003, 0x002f, 0x0001, 0xb288, 0x0000, 0x0002, 0x0001, - 0xc180, 0x0000, 0xff31, 0x0015, 0x0033, 0x0000, 0xb009, 0x000b, - 0x80e3, 0x0002, 0xb200, 0x0011, 0xffc8, 0x0000, 0x0007, 0x0010, - 0xffb2, 0x0010, 0xc131, 0x0015, 0x0033, 0x0010, 0xb20a, 0x001b, - 0x80eb, 0x0011, 0xb088, 0x0000, 0x0008, 0x0000, 0xff31, 0x0015, - 0x0033, 0x0010, 0xb109, 0x000b, 0x80f1, 0x0001, 0xb1e8, 0x0010, - 0x0003, 0x0003, 0x1102, 0x0017, 0x4000, 0x0015, 0x0030, 0x0000, - 0x0400, 0x0011, 0xb088, 0x0000, 0x0010, 0x0000, 0xff31, 0x0015, - 0x0033, 0x0010, 0xb109, 0x000b, 0x80fd, 0x0001, 0xb1e8, 0x0010, - 0xffff, 0x001b, 0x1102, 0x0017, 0x4000, 0x0000, 0x11fe, 0x001b, - 0x6106, 0x0000, 0xb012, 0x0013, 0x010e, 0x0015, 0x0030, 0x0000, - 0x0400, 0x0001, 0x1188, 0x0010, 0x0003, 0x0000, 0xff31, 0x0015, - 0x0033, 0x0000, 0xb00a, 0x001b, 0x810d, 0x0000, 0xb011, 0x0017, - 0x4000, 0x0015, 0x0030, 0x0000, 0x0400, 0x0011, 0xbc88, 0x0000, - 0x001f, 0x0000, 0xff31, 0x0015, 0x0033, 0x0000, 0xc411, 0x000b, - 0x8117, 0x0011, 0xbc88, 0x0010, 0x0018, 0x0000, 0xff31, 0x0015, - 0x0033, 0x0010, 0xc609, 0x000b, 0x811d, 0x0011, 0xbc88, 0x0000, - 0x0037, 0x0000, 0xff31, 0x0015, 0x0033, 0x0000, 0xc709, 0x001b, - 0x8123, 0x0017, 0x4000, 0x0015, 0x0030, 0x0000, 0x0400, 0x0001, - 0xbb88, 0x0000, 0x0001, 0x0000, 0xff31, 0x0015, 0x0033, 0x0000, - 0x0269, 0x001b, 0x812c, 0x0017, 0x4000, 0x0015, 0x0030, 0x0000, - 0x0400, 0x0001, 0xbb88, 0x0000, 0x0001, 0x0000, 0xff31, 0x0015, - 0x0033, 0x0000, 0x026a, 0x000b, 0x8135, 0x0017, 0x4000, 0x0015, - 0x0030, 0x0000, 0x0400, 0x0001, 0xbb88, 0x0010, 0x000f, 0x0000, - 0xff31, 0x0015, 0x0033, 0x0010, 0x0f59, 0x001b, 0x813e, 0x0017, - 0x4000, 0x0015, 0x0030, 0x0000, 0x0400, 0x0001, 0xbb88, 0x0010, - 0x000f, 0x0000, 0xff31, 0x0015, 0x0033, 0x0010, 0x0f5a, 0x000b, - 0x8147, 0x0017, 0x4000, 0x0000, 0xd0ff, 0x0012, 0xff40, 0x001b, - 0x1036, 0x0015, 0x00d1, 0x0010, 0x0101, 0x0003, 0x914e, 0x0005, - 0x0079, 0x0000, 0x0001, 0x0013, 0x9151, 0x0015, 0x00d1, 0x0000, - 0x0100, 0x0011, 0x02e8, 0x0000, 0x0002, 0x0003, 0x117a, 0x0011, - 0x02e8, 0x0000, 0x0001, 0x0003, 0x1192, 0x0011, 0x02e8, 0x0000, - 0x0004, 0x0003, 0x11b0, 0x0011, 0x02e8, 0x0010, 0x0003, 0x0013, - 0x11e1, 0x0005, 0x0002, 0x0010, 0x0000, 0x0000, 0xc00e, 0x0000, - 0xc00d, 0x0010, 0xc003, 0x0015, 0x0030, 0x0000, 0x0400, 0x0001, - 0xbd88, 0x0010, 0x0009, 0x0000, 0xff31, 0x0015, 0x0033, 0x0010, - 0xc00a, 0x000b, 0x816c, 0x0000, 0xff31, 0x0015, 0x0033, 0x0010, - 0xc00a, 0x001b, 0x8170, 0x0012, 0x3a45, 0x0013, 0x1178, 0x0015, - 0x003a, 0x0000, 0x2000, 0x0015, 0x003a, 0x0010, 0x1010, 0x0014, - 0x0932, 0x000b, 0x4057, 0x0013, 0x005c, 0x0012, 0x7849, 0x0003, - 0x11ef, 0x0010, 0x0dfe, 0x0013, 0x6162, 0x0012, 0x0c10, 0x0010, - 0xff0c, 0x0015, 0x0030, 0x0000, 0x0400, 0x0011, 0x0d88, 0x0010, - 0x0003, 0x0000, 0xff31, 0x0015, 0x0033, 0x0000, 0xb309, 0x000b, - 0x8187, 0x0010, 0xb3fe, 0x0013, 0x618f, 0x0010, 0xb30b, 0x0015, - 0x0033, 0x0010, 0xc00a, 0x000b, 0x818d, 0x0003, 0x01e4, 0x0000, - 0xc00b, 0x0010, 0xc00a, 0x0003, 0x01e4, 0x0000, 0x78b0, 0x0012, - 0xb044, 0x0003, 0x11ef, 0x0002, 0xb049, 0x0003, 0x11ef, 0x0010, - 0x71ff, 0x0012, 0xff38, 0x0010, 0xff71, 0x0010, 0x0dfe, 0x0003, - 0x6160, 0x0012, 0x0c10, 0x0010, 0xff0c, 0x0015, 0x0030, 0x0000, - 0x0400, 0x0011, 0x0d88, 0x0010, 0x0003, 0x0000, 0xff31, 0x0015, - 0x0033, 0x0000, 0xb309, 0x000b, 0x81a5, 0x0010, 0xb3fe, 0x0013, - 0x61ad, 0x0000, 0xb309, 0x0015, 0x0033, 0x0010, 0xc00a, 0x001b, - 0x81ab, 0x0003, 0x01e4, 0x0010, 0xc009, 0x0000, 0xc008, 0x0003, - 0x01e4, 0x0000, 0x78b0, 0x0012, 0xb044, 0x0003, 0x11ef, 0x0002, - 0xb049, 0x0003, 0x11ef, 0x0010, 0x71ff, 0x0012, 0xff38, 0x0010, - 0xff71, 0x0010, 0x0dfe, 0x0003, 0x6160, 0x0012, 0x0c10, 0x0010, - 0xff0c, 0x0015, 0x0030, 0x0000, 0x0400, 0x0011, 0x0d88, 0x0010, - 0x0003, 0x0000, 0xff31, 0x0015, 0x0033, 0x0000, 0xb309, 0x000b, - 0x81c3, 0x0010, 0xb3fe, 0x0013, 0x61cb, 0x0000, 0xb305, 0x0015, - 0x0033, 0x0010, 0xc00a, 0x000b, 0x81c9, 0x0013, 0x01cd, 0x0010, - 0xc005, 0x0000, 0xc004, 0x0002, 0x033f, 0x0002, 0xff27, 0x0000, - 0x0db8, 0x0014, 0x03d5, 0x0000, 0x0db8, 0x0004, 0x0948, 0x0015, - 0x0030, 0x0000, 0x0400, 0x0011, 0xbc88, 0x0010, 0x0000, 0x0000, - 0xff31, 0x0015, 0x0033, 0x0000, 0xb309, 0x001b, 0x81da, 0x0011, - 0xb3e8, 0x0000, 0x0002, 0x000b, 0x1160, 0x0005, 0x0002, 0x0010, - 0x0005, 0x0013, 0x0162, 0x0012, 0x7849, 0x0003, 0x11ef, 0x0013, - 0x0162, 0x0000, 0x0db8, 0x0012, 0x0345, 0x001b, 0x11ea, 0x0002, - 0x033f, 0x0014, 0x03d5, 0x0003, 0x0160, 0x0002, 0x033f, 0x0002, - 0xff27, 0x0014, 0x03d5, 0x0004, 0x0948, 0x0003, 0x0160, 0x0015, - 0x00b8, 0x0000, 0x0001, 0x0015, 0x003a, 0x0010, 0x0101, 0x0004, - 0x0948, 0x0003, 0x0171, 0x0001, 0x2bd8, 0x0010, 0x0000, 0x0000, - 0xffba, 0x0003, 0xb1f8, 0x0005, 0x002a, 0x0000, 0x0002, 0x0001, - 0xbac8, 0x0000, 0x0700, 0x001b, 0x12e6, 0x0011, 0x15e8, 0x0000, - 0x0002, 0x0013, 0x125c, 0x0011, 0x15e8, 0x0000, 0x0001, 0x0003, - 0x1207, 0x0005, 0x0015, 0x0010, 0x0000, 0x0013, 0x023e, 0x0005, - 0x0015, 0x0010, 0x0000, 0x0002, 0xba43, 0x0003, 0x1240, 0x0003, - 0xb20b, 0x0005, 0x002a, 0x0000, 0x0004, 0x0012, 0xba42, 0x0003, - 0x1246, 0x0012, 0x104b, 0x001b, 0x123e, 0x0000, 0x1a30, 0x0005, - 0x0031, 0x0000, 0x0002, 0x0015, 0x0033, 0x0000, 0x1b2a, 0x000b, - 0x8217, 0x0011, 0x20d8, 0x0010, 0x0000, 0x0000, 0xffb0, 0x0001, - 0x21d8, 0x0010, 0x0000, 0x0010, 0xffb1, 0x0001, 0x22d8, 0x0010, - 0x0000, 0x0010, 0xffb2, 0x0011, 0x23d8, 0x0010, 0x0000, 0x0000, - 0xffb3, 0x0001, 0x24d8, 0x0010, 0x0000, 0x0010, 0xffb4, 0x0011, - 0x25d8, 0x0010, 0x0000, 0x0000, 0xffb5, 0x0001, 0x28d8, 0x0010, - 0x0000, 0x0010, 0xffb8, 0x0011, 0x29d8, 0x0010, 0x0000, 0x0000, - 0xffb9, 0x0000, 0x1a30, 0x0005, 0x0031, 0x0000, 0x0007, 0x0015, - 0x0033, 0x0010, 0xb032, 0x000b, 0x8235, 0x0000, 0x1a30, 0x0005, - 0x0031, 0x0010, 0x000f, 0x0015, 0x0033, 0x0010, 0xb812, 0x001b, - 0x823b, 0x0005, 0x0015, 0x0010, 0x0000, 0x001b, 0x403a, 0x0013, - 0x005c, 0x0000, 0x1efe, 0x0013, 0x6254, 0x0014, 0x028b, 0x0000, - 0x1efe, 0x000c, 0x628b, 0x0013, 0x023e, 0x0000, 0x1a30, 0x0005, - 0x0031, 0x0010, 0x0021, 0x0015, 0x0033, 0x0000, 0xb009, 0x000b, - 0x824b, 0x0002, 0xb02f, 0x0000, 0xffb0, 0x0005, 0x0031, 0x0010, - 0x0021, 0x0015, 0x0033, 0x0000, 0xb00a, 0x001b, 0x8252, 0x0003, - 0x0212, 0x0015, 0x00b8, 0x0010, 0x0005, 0x0004, 0x0948, 0x0000, - 0x13b8, 0x0015, 0x003a, 0x0010, 0x0404, 0x0004, 0x0948, 0x0013, - 0x023e, 0x0005, 0x0015, 0x0000, 0x0001, 0x0012, 0xba42, 0x0013, - 0x126a, 0x0013, 0xb260, 0x0001, 0x2bd8, 0x0010, 0x0000, 0x0012, - 0xff4f, 0x000b, 0x11f5, 0x0002, 0xba43, 0x001b, 0x1246, 0x0000, - 0x1efe, 0x000c, 0x628b, 0x0013, 0x023e, 0x0001, 0x28d8, 0x0010, - 0x0000, 0x0010, 0xffb8, 0x0011, 0x29d8, 0x0010, 0x0000, 0x0000, - 0xffb9, 0x0014, 0x02fc, 0x0002, 0x3a42, 0x001b, 0x123e, 0x0000, - 0x1c30, 0x0015, 0x00ff, 0x0000, 0x0002, 0x0002, 0x1f43, 0x000b, - 0x127b, 0x0001, 0xff88, 0x0000, 0x0002, 0x0003, 0x027d, 0x0001, - 0xff88, 0x0000, 0x0004, 0x0000, 0xff31, 0x0015, 0x0033, 0x0000, - 0xb011, 0x001b, 0x8280, 0x0000, 0xb0ff, 0x0011, 0x16a0, 0x0000, - 0xff16, 0x000b, 0x2287, 0x0002, 0xb100, 0x0003, 0x0288, 0x0010, - 0xb1ff, 0x0001, 0x17a0, 0x0010, 0xff17, 0x0013, 0x0246, 0x0000, - 0x16ff, 0x0001, 0x18a0, 0x0010, 0xff00, 0x001b, 0x2292, 0x0002, - 0x1700, 0x0003, 0x12e5, 0x0003, 0x0293, 0x0010, 0x17ff, 0x0011, - 0x19a0, 0x0003, 0x22e5, 0x0011, 0x00d0, 0x0003, 0x12e5, 0x0000, - 0x1c30, 0x0000, 0x1b31, 0x0015, 0x0033, 0x0000, 0xb131, 0x001b, - 0x829b, 0x0013, 0xb29c, 0x0000, 0xb120, 0x0010, 0xb221, 0x0002, - 0x1f43, 0x001b, 0x12a8, 0x0010, 0xc022, 0x0000, 0xc023, 0x0000, - 0xb324, 0x0000, 0xb425, 0x0010, 0xb3b5, 0x0000, 0xb4b6, 0x0003, - 0x02ac, 0x0000, 0xb322, 0x0000, 0xb423, 0x0000, 0xb524, 0x0010, - 0xb625, 0x0013, 0xb2ac, 0x0005, 0x002a, 0x0000, 0x0001, 0x0012, - 0x1500, 0x0000, 0xff15, 0x0000, 0x16ff, 0x0001, 0xb580, 0x0000, - 0xff16, 0x000b, 0x22b7, 0x0002, 0x1700, 0x0003, 0x02b8, 0x0010, - 0x17ff, 0x0001, 0xb680, 0x0010, 0xff17, 0x0012, 0x1e10, 0x0010, - 0xff1e, 0x0013, 0x62e5, 0x0002, 0x1d00, 0x0010, 0xff1d, 0x0010, - 0xc030, 0x0000, 0xff31, 0x0015, 0x0033, 0x0000, 0xb009, 0x000b, - 0x82c3, 0x0010, 0xb0fe, 0x001b, 0x62e4, 0x0000, 0x1c30, 0x0005, - 0x0031, 0x0000, 0x0001, 0x0015, 0x0033, 0x0000, 0xb009, 0x001b, - 0x82cb, 0x0010, 0xb0fe, 0x001b, 0x62d1, 0x0005, 0x00ce, 0x0010, - 0x0005, 0x0013, 0x0900, 0x0010, 0xb01c, 0x0000, 0x1c30, 0x0005, - 0x0031, 0x0000, 0x001a, 0x0015, 0x0033, 0x0000, 0xb009, 0x000b, - 0x82d7, 0x0001, 0xb0c8, 0x0010, 0x00ff, 0x0000, 0xff1f, 0x0010, - 0xc030, 0x0011, 0xbe80, 0x0000, 0xff31, 0x0015, 0x0033, 0x0000, - 0xb009, 0x001b, 0x82e0, 0x0000, 0xb01d, 0x0010, 0x1dff, 0x0013, - 0x02bf, 0x0000, 0xb01b, 0x0017, 0x4000, 0x0002, 0x3a41, 0x0013, - 0x12ee, 0x0013, 0xb2e8, 0x0005, 0x002a, 0x0000, 0x0004, 0x0005, - 0x0015, 0x0010, 0x0000, 0x0013, 0x023e, 0x0000, 0x1a30, 0x0005, - 0x0031, 0x0000, 0x0002, 0x0015, 0x0033, 0x0000, 0x1b2a, 0x000b, - 0x82f3, 0x0015, 0x00b8, 0x0000, 0x0004, 0x0004, 0x0948, 0x0000, - 0x13b8, 0x0015, 0x003a, 0x0010, 0x0404, 0x0004, 0x0948, 0x0003, - 0x003e, 0x0002, 0x1e00, 0x0010, 0xff1e, 0x0012, 0x1d10, 0x0010, - 0xff1d, 0x0010, 0xc030, 0x0000, 0xff31, 0x0015, 0x0033, 0x0000, - 0xb009, 0x000b, 0x8304, 0x0010, 0xb0fe, 0x001b, 0x6329, 0x0000, - 0x1cff, 0x0001, 0x1ae0, 0x0013, 0x1313, 0x0000, 0x1c30, 0x0005, - 0x0031, 0x0010, 0x0000, 0x0015, 0x0033, 0x0000, 0xb009, 0x001b, - 0x830f, 0x0010, 0xb0fe, 0x001b, 0x6313, 0x0000, 0x1aff, 0x0000, - 0xff1c, 0x0000, 0x1c30, 0x0005, 0x0031, 0x0000, 0x001a, 0x0015, - 0x0033, 0x0000, 0xb009, 0x000b, 0x8319, 0x0001, 0xb0c8, 0x0010, - 0x000f, 0x0000, 0xff1f, 0x0001, 0xbf80, 0x0010, 0xff1d, 0x0010, - 0xc030, 0x0000, 0xff31, 0x0015, 0x0033, 0x0000, 0xb009, 0x000b, - 0x8323, 0x0010, 0xb0fe, 0x001b, 0x6329, 0x0005, 0x00ce, 0x0010, - 0x0006, 0x0013, 0x0900, 0x0000, 0xb01b, 0x0017, 0x4000, 0x0010, - 0x79b0, 0x0000, 0xd0ff, 0x0012, 0xff40, 0x000b, 0x103e, 0x0015, - 0x00d1, 0x0010, 0x0101, 0x0003, 0x9331, 0x0005, 0x0079, 0x0000, - 0x0002, 0x0003, 0x9334, 0x0015, 0x00d1, 0x0000, 0x0100, 0x0010, - 0x13fe, 0x0003, 0x6385, 0x0012, 0xb04e, 0x001b, 0x13af, 0x0000, - 0x78b0, 0x0002, 0xb045, 0x0003, 0x13b2, 0x0012, 0x784a, 0x0003, - 0x13b2, 0x0000, 0x75ff, 0x0011, 0xffc8, 0x0010, 0x1800, 0x001b, - 0x13b2, 0x0001, 0x0fe8, 0x0000, 0x0001, 0x001b, 0x1350, 0x0015, - 0x0030, 0x0000, 0x0400, 0x0011, 0x1388, 0x0000, 0x000e, 0x0000, - 0xff31, 0x0015, 0x0033, 0x0000, 0x8f0a, 0x001b, 0x834e, 0x0013, - 0x03b8, 0x0001, 0x0fe8, 0x0000, 0x0002, 0x000b, 0x135b, 0x0015, - 0x0030, 0x0000, 0x0400, 0x0005, 0x0031, 0x0000, 0x001a, 0x0015, - 0x0033, 0x0010, 0xc00a, 0x001b, 0x8359, 0x0013, 0x03b8, 0x0001, - 0x0fe8, 0x0010, 0x0000, 0x0013, 0x1362, 0x0005, 0x00ce, 0x0000, - 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0x1288, 0x0010, 0x0003, 0x0000, 0xff31, 0x0015, 0x0033, 0x0010, - 0xc00a, 0x001b, 0x84a4, 0x0005, 0x00b0, 0x0000, 0x8000, 0x0001, - 0x1288, 0x0010, 0x0011, 0x0000, 0xff31, 0x0015, 0x0033, 0x0000, - 0xb00a, 0x000b, 0x84ac, 0x0003, 0x0057, 0x0015, 0x0030, 0x0000, - 0x0400, 0x0011, 0x0d88, 0x0010, 0x0011, 0x0000, 0xff31, 0x0015, - 0x0033, 0x0010, 0x0309, 0x001b, 0x84b5, 0x0011, 0x0d88, 0x0010, - 0x0005, 0x0000, 0xff31, 0x0015, 0x0033, 0x0000, 0xb909, 0x000b, - 0x84bb, 0x0017, 0x4000, 0x0005, 0x00b6, 0x0010, 0x0600, 0x0014, - 0x0697, 0x0014, 0x052f, 0x0000, 0xb05a, 0x0000, 0xb15b, 0x0005, - 0x0054, 0x0010, 0x0829, 0x0010, 0x0d58, 0x0015, 0x0059, 0x0010, - 0xffff, 0x0000, 0xb930, 0x0005, 0x0031, 0x0000, 0x001f, 0x0015, - 0x0033, 0x0000, 0xb009, 0x001b, 0x84cd, 0x0000, 0xb05c, 0x0005, - 0x0031, 0x0000, 0x0020, 0x0015, 0x0033, 0x0000, 0xb009, 0x001b, - 0x84d3, 0x0001, 0xb0c8, 0x0010, 0x000f, 0x001b, 0x14da, 0x0015, - 0x00ff, 0x0010, 0x0005, 0x0003, 0x04e2, 0x0002, 0xb040, 0x0003, - 0x14df, 0x0015, 0x00ff, 0x0000, 0x0004, 0x0003, 0x04e2, 0x0001, - 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0x855f, 0x0010, 0xb058, 0x0000, 0x0d59, 0x0000, 0xb930, 0x0005, - 0x0031, 0x0010, 0x0024, 0x0015, 0x0033, 0x0000, 0xb011, 0x000b, - 0x8567, 0x0010, 0xb15c, 0x0010, 0xb05d, 0x0005, 0x0031, 0x0000, - 0x002c, 0x0015, 0x0033, 0x0000, 0xb011, 0x000b, 0x856e, 0x0000, - 0xb15e, 0x0000, 0xb05f, 0x0013, 0x9571, 0x0015, 0x00a0, 0x0010, - 0x000c, 0x0003, 0x067c, 0x0005, 0x00b6, 0x0000, 0x0700, 0x0014, - 0x0697, 0x0015, 0x0030, 0x0000, 0x0400, 0x0011, 0x0d88, 0x0010, - 0x0009, 0x0000, 0xff31, 0x0015, 0x0033, 0x0010, 0xb709, 0x000b, - 0x857f, 0x0012, 0xb749, 0x0013, 0x1585, 0x0005, 0x0054, 0x0010, - 0x0889, 0x0013, 0x0587, 0x0005, 0x0054, 0x0010, 0x0898, 0x0015, - 0x0030, 0x0000, 0x0400, 0x0011, 0x0d88, 0x0000, 0x0002, 0x0000, - 0xff31, 0x0015, 0x0033, 0x0000, 0xb009, 0x001b, 0x858e, 0x0010, - 0xb058, 0x0000, 0x0d59, 0x0001, 0xb9c8, 0x0010, 0xf000, 0x0001, - 0xffe8, 0x0010, 0xf000, 0x001b, 0x15b7, 0x0015, 0x0030, 0x0000, - 0x0400, 0x0011, 0x0d88, 0x0010, 0x0005, 0x0000, 0xff31, 0x0015, - 0x0033, 0x0000, 0xb009, 0x000b, 0x859d, 0x0001, 0xb0c8, 0x0000, - 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0x0009, 0x0001, 0xbd88, 0x0000, 0x000b, 0x0000, 0xff31, 0x0015, - 0x0033, 0x0000, 0xb012, 0x000b, 0x88a5, 0x0003, 0x0717, 0x0015, - 0x00d1, 0x0000, 0x0400, 0x0001, 0x1288, 0x0010, 0x0003, 0x0000, - 0xff31, 0x0015, 0x0033, 0x0000, 0xb009, 0x001b, 0x88ae, 0x0001, - 0x1288, 0x0010, 0x0003, 0x0000, 0xff31, 0x0015, 0x0033, 0x0010, - 0xc00a, 0x000b, 0x88b4, 0x0010, 0xb0fe, 0x0013, 0x68b9, 0x0000, - 0xb012, 0x0003, 0x0717, 0x0010, 0xc012, 0x0010, 0xc011, 0x0003, - 0x0717, 0x0000, 0xba30, 0x0005, 0x0031, 0x0010, 0x0021, 0x0015, - 0x0033, 0x0010, 0xb019, 0x001b, 0x88c1, 0x0002, 0xb200, 0x0011, - 0xffc8, 0x0010, 0x00ff, 0x0010, 0xffb2, 0x0010, 0xb2b7, 0x0005, - 0x0031, 0x0000, 0x0023, 0x0015, 0x0033, 0x0010, 0xb20a, 0x001b, - 0x88cb, 0x0017, 0x4000, 0x0000, 0xba30, 0x0005, 0x0031, 0x0000, - 0x0023, 0x0015, 0x0033, 0x0010, 0xb409, 0x000b, 0x88d2, 0x0002, - 0xb400, 0x0011, 0xffc8, 0x0010, 0x00ff, 0x0010, 0xffb4, 0x0010, - 0xb4b7, 0x0005, 0x0031, 0x0000, 0x0023, 0x0015, 0x0033, 0x0010, - 0xb40a, 0x001b, 0x88dc, 0x0017, 0x4000, 0x0000, 0xba30, 0x0001, - 0xc7c8, 0x0000, 0x0020, 0x001b, 0x18ea, 0x0005, 0x0031, 0x0010, - 0x0028, 0x0015, 0x0033, 0x0010, 0xb209, 0x001b, 0x88e6, 0x0011, - 0xb2c8, 0x0000, 0xff80, 0x0013, 0x18ed, 0x0010, 0xc4b0, 0x0010, - 0xc5b1, 0x0013, 0x08ef, 0x0010, 0xc6b1, 0x0000, 0xc0b0, 0x0005, - 0x0031, 0x0000, 0x0004, 0x0015, 0x0033, 0x0010, 0xb211, 0x000b, - 0x88f3, 0x0017, 0x4000, 0x0011, 0x3ac8, 0x0000, 0x0007, 0x0001, - 0xffe8, 0x0000, 0x0007, 0x0013, 0x102f, 0x0015, 0x00b8, 0x0010, - 0x0009, 0x0015, 0x003a, 0x0010, 0x0707, 0x0004, 0x0948, 0x0003, - 0x002f, 0x0011, 0x3ac8, 0x0000, 0x0007, 0x0001, 0xffe8, 0x0000, - 0x0007, 0x001b, 0x1906, 0x0017, 0x4000, 0x0015, 0x00b8, 0x0010, - 0x0009, 0x0015, 0x003a, 0x0010, 0x0707, 0x0013, 0x0948, 0x0014, - 0x012e, 0x0015, 0x0030, 0x0000, 0x0400, 0x0011, 0x0d88, 0x0000, - 0x0004, 0x0000, 0xff31, 0x0015, 0x0033, 0x0000, 0xba09, 0x000b, - 0x8913, 0x0004, 0x08bc, 0x0015, 0x0030, 0x0000, 0x0400, 0x0011, - 0x0d88, 0x0000, 0x0010, 0x0000, 0xff31, 0x0015, 0x0033, 0x0010, - 0xb20a, 0x000b, 0x891c, 0x0015, 0x0030, 0x0000, 0x0400, 0x0011, - 0x0d88, 0x0010, 0x0011, 0x0000, 0xff31, 0x0015, 0x0033, 0x0010, - 0x0309, 0x001b, 0x8924, 0x0002, 0x0327, 0x0010, 0xffb2, 0x0011, - 0x0d88, 0x0010, 0x0011, 0x0000, 0xff31, 0x0015, 0x0033, 0x0010, - 0xb20a, 0x000b, 0x892c, 0x0015, 0x00b8, 0x0010, 0x0006, 0x0004, - 0x0948, 0x0000, 0x0db8, 0x0013, 0x0948, 0x0004, 0x0140, 0x0004, - 0x08bc, 0x0015, 0x0030, 0x0000, 0x0400, 0x0011, 0x1388, 0x0000, - 0x0010, 0x0000, 0xff31, 0x0015, 0x0033, 0x0010, 0xb20a, 0x000b, - 0x893b, 0x0012, 0x1027, 0x0010, 0xffb2, 0x0011, 0x1388, 0x0010, - 0x0011, 0x0000, 0xff31, 0x0015, 0x0033, 0x0010, 0xb20a, 0x000b, - 0x8943, 0x0015, 0x00b8, 0x0000, 0x0007, 0x0004, 0x0948, 0x0000, - 0x13b8, 0x0012, 0xd143, 0x000b, 0x194f, 0x0015, 0x00ff, 0x0000, - 0x0100, 0x000b, 0x496d, 0x0012, 0xff10, 0x000b, 0x194c, 0x0000, - 0xcdff, 0x0001, 0xcca0, 0x0013, 0x195b, 0x0013, 0x2958, 0x0005, - 0x00b0, 0x0010, 0x000f, 0x0011, 0xb0a0, 0x000b, 0x195b, 0x0013, - 0x096f, 0x0001, 0xffe8, 0x0010, 0xffff, 0x0003, 0x196f, 0x0015, - 0x0030, 0x0000, 0x0400, 0x0000, 0xcc31, 0x0015, 0x0033, 0x0010, - 0xb80a, 0x001b, 0x8960, 0x0002, 0xcc00, 0x0010, 0xffcc, 0x0001, - 0xbb88, 0x0000, 0x002c, 0x0001, 0xcca0, 0x0003, 0x296a, 0x0001, - 0xbb88, 0x0000, 0x001c, 0x0010, 0xffcc, 0x0015, 0x00d1, 0x0010, - 0x0808, 0x0017, 0x4000, 0x0000, 0xb838, 0x0017, 0x4000, 0x0003, - 0x496f, 0x0015, 0x00d1, 0x0010, 0x1010, 0x0015, 0x0030, 0x0000, - 0x0400, 0x0010, 0xcd31, 0x0015, 0x0033, 0x0000, 0xb009, 0x001b, - 0x8977, 0x0010, 0xb038, 0x0012, 0xcd00, 0x0000, 0xffcd, 0x0001, - 0xbb88, 0x0000, 0x002c, 0x0011, 0xcda0, 0x0003, 0x2982, 0x0001, - 0xbb88, 0x0000, 0x001c, 0x0000, 0xffcd, 0x0000, 0xcdff, 0x0011, - 0xcce0, 0x001b, 0x1987, 0x0015, 0x00d1, 0x0000, 0x0800, 0x0002, - 0xd144, 0x0013, 0x102f, 0x0015, 0x00d1, 0x0000, 0x1000, 0x0013, - 0x0948, 0x96b3, 0x24c6 -}; diff --git a/sys/dev/le/if_le_lebuffer.c b/sys/dev/le/if_le_lebuffer.c deleted file mode 100644 index b7532b40e0b..00000000000 --- a/sys/dev/le/if_le_lebuffer.c +++ /dev/null @@ -1,392 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-NetBSD - * - * Copyright (c) 2006 Marius Strobl - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include -#include -#include - -#include -#include -#include - -#include -#include -#include -#include - -/* - * LANCE registers - */ -#define LEREG1_RDP 0 /* Register Data port */ -#define LEREG1_RAP 2 /* Register Address port */ - -struct le_lebuffer_softc { - struct am7990_softc sc_am7990; /* glue to MI code */ - - struct resource *sc_bres; - - struct resource *sc_rres; - - struct resource *sc_ires; - void *sc_ih; -}; - -static devclass_t le_lebuffer_devclass; - -static device_probe_t le_lebuffer_probe; -static device_attach_t le_lebuffer_attach; -static device_detach_t le_lebuffer_detach; -static device_resume_t le_buffer_resume; -static device_suspend_t le_buffer_suspend; - -static device_method_t le_lebuffer_methods[] = { - /* Device interface */ - DEVMETHOD(device_probe, le_lebuffer_probe), - DEVMETHOD(device_attach, le_lebuffer_attach), - DEVMETHOD(device_detach, le_lebuffer_detach), - /* We can just use the suspend method here. */ - DEVMETHOD(device_shutdown, le_buffer_suspend), - DEVMETHOD(device_suspend, le_buffer_suspend), - DEVMETHOD(device_resume, le_buffer_resume), - - { 0, 0 } -}; - -DEFINE_CLASS_0(le, le_lebuffer_driver, le_lebuffer_methods, - sizeof(struct le_lebuffer_softc)); -DRIVER_MODULE(le, lebuffer, le_lebuffer_driver, le_lebuffer_devclass, 0, 0); -MODULE_DEPEND(le, ether, 1, 1, 1); -MODULE_DEPEND(le, lebuffer, 1, 1, 1); - -/* - * Media types supported - */ -static const int le_lebuffer_media[] = { - IFM_MAKEWORD(IFM_ETHER, IFM_10_T, 0, 0) -}; -#define NLEMEDIA nitems(le_lebuffer_media) - -static void le_lebuffer_wrcsr(struct lance_softc *, uint16_t, uint16_t); -static uint16_t le_lebuffer_rdcsr(struct lance_softc *, uint16_t); -static void le_lebuffer_copytodesc(struct lance_softc *, void *, int, int); -static void le_lebuffer_copyfromdesc(struct lance_softc *, void *, int, int); -static void le_lebuffer_copytobuf(struct lance_softc *, void *, int, int); -static void le_lebuffer_copyfrombuf(struct lance_softc *, void *, int, int); -static void le_lebuffer_zerobuf(struct lance_softc *, int, int); - -static void -le_lebuffer_wrcsr(struct lance_softc *sc, uint16_t port, uint16_t val) -{ - struct le_lebuffer_softc *lesc = (struct le_lebuffer_softc *)sc; - - bus_write_2(lesc->sc_rres, LEREG1_RAP, port); - bus_barrier(lesc->sc_rres, LEREG1_RAP, 2, BUS_SPACE_BARRIER_WRITE); - bus_write_2(lesc->sc_rres, LEREG1_RDP, val); -} - -static uint16_t -le_lebuffer_rdcsr(struct lance_softc *sc, uint16_t port) -{ - struct le_lebuffer_softc *lesc = (struct le_lebuffer_softc *)sc; - - bus_write_2(lesc->sc_rres, LEREG1_RAP, port); - bus_barrier(lesc->sc_rres, LEREG1_RAP, 2, BUS_SPACE_BARRIER_WRITE); - return (bus_read_2(lesc->sc_rres, LEREG1_RDP)); -} - -/* - * It turns out that using bus_space(9) to access the buffers and the - * descriptors yields way more throughput than accessing them via the - * KVA returned by rman_get_virtual(9). The descriptor rings can be - * accessed using 8-bit up to 64-bit operations while the buffers can - * be only accessed using 8-bit and 16-bit operations. - * NB: For whatever reason setting LE_C3_BSWP has no effect with at - * least the 501-2981 (although their 'busmaster-regval' property - * indicates to set LE_C3_BSWP also for these cards), so we need - * to manually byte swap access to the buffers, i.e. the accesses - * going through the RX/TX FIFOs. - */ - -static void -le_lebuffer_copytodesc(struct lance_softc *sc, void *fromv, int off, int len) -{ - struct le_lebuffer_softc *lesc = (struct le_lebuffer_softc *)sc; - caddr_t from = fromv; - - for (; len >= 8; len -= 8, off += 8, from += 8) - bus_write_8(lesc->sc_bres, off, be64dec(from)); - for (; len >= 4; len -= 4, off += 4, from += 4) - bus_write_4(lesc->sc_bres, off, be32dec(from)); - for (; len >= 2; len -= 2, off += 2, from += 2) - bus_write_2(lesc->sc_bres, off, be16dec(from)); - if (len == 1) - bus_write_1(lesc->sc_bres, off, *from); -} - -static void -le_lebuffer_copyfromdesc(struct lance_softc *sc, void *tov, int off, int len) -{ - struct le_lebuffer_softc *lesc = (struct le_lebuffer_softc *)sc; - caddr_t to = tov; - - for (; len >= 8; len -= 8, off += 8, to += 8) - be64enc(to, - bus_read_8(lesc->sc_bres, off)); - for (; len >= 4; len -= 4, off += 4, to += 4) - be32enc(to, - bus_read_4(lesc->sc_bres, off)); - for (; len >= 2; len -= 2, off += 2, to += 2) - be16enc(to, - bus_read_2(lesc->sc_bres, off)); - if (len == 1) - *to = bus_read_1(lesc->sc_bres, off); -} - -static void -le_lebuffer_copytobuf(struct lance_softc *sc, void *fromv, int off, int len) -{ - struct le_lebuffer_softc *lesc = (struct le_lebuffer_softc *)sc; - caddr_t from = fromv; - - for (; len >= 2; len -= 2, off += 2, from += 2) - bus_write_2(lesc->sc_bres, off, le16dec(from)); - if (len == 1) - bus_write_1(lesc->sc_bres, off + 1, *from); -} - -static void -le_lebuffer_copyfrombuf(struct lance_softc *sc, void *tov, int off, int len) -{ - struct le_lebuffer_softc *lesc = (struct le_lebuffer_softc *)sc; - caddr_t to = tov; - - for (; len >= 2; len -= 2, off += 2, to += 2) - le16enc(to, - bus_read_2(lesc->sc_bres, off)); - if (len == 1) - *to = bus_read_1(lesc->sc_bres, off + 1); -} - -static void -le_lebuffer_zerobuf(struct lance_softc *sc, int off, int len) -{ - struct le_lebuffer_softc *lesc = (struct le_lebuffer_softc *)sc; - - for (; len >= 2; len -= 2, off += 2) - bus_write_2(lesc->sc_bres, off, 0); - if (len == 1) - bus_write_1(lesc->sc_bres, off + 1, 0); -} - -static int -le_lebuffer_probe(device_t dev) -{ - - if (strcmp(ofw_bus_get_name(dev), "le") == 0) { - device_set_desc(dev, "LANCE Ethernet"); - return (BUS_PROBE_DEFAULT); - } - return (ENXIO); -} - -static int -le_lebuffer_attach(device_t dev) -{ - struct le_lebuffer_softc *lesc; - struct lance_softc *sc; - int error, i; - - lesc = device_get_softc(dev); - sc = &lesc->sc_am7990.lsc; - - LE_LOCK_INIT(sc, device_get_nameunit(dev)); - - /* - * The "register space" of the parent is just a buffer where the - * the LANCE descriptor rings and the RX/TX buffers can be stored. - */ - i = 0; - lesc->sc_bres = bus_alloc_resource_any(device_get_parent(dev), - SYS_RES_MEMORY, &i, RF_ACTIVE); - if (lesc->sc_bres == NULL) { - device_printf(dev, "cannot allocate LANCE buffer\n"); - error = ENXIO; - goto fail_mtx; - } - - /* Allocate LANCE registers. */ - i = 0; - lesc->sc_rres = bus_alloc_resource_any(dev, SYS_RES_MEMORY, - &i, RF_ACTIVE); - if (lesc->sc_rres == NULL) { - device_printf(dev, "cannot allocate LANCE registers\n"); - error = ENXIO; - goto fail_bres; - } - - /* Allocate LANCE interrupt. */ - i = 0; - if ((lesc->sc_ires = bus_alloc_resource_any(dev, SYS_RES_IRQ, - &i, RF_SHAREABLE | RF_ACTIVE)) == NULL) { - device_printf(dev, "cannot allocate interrupt\n"); - error = ENXIO; - goto fail_rres; - } - - /* - * LANCE view is offset by buffer location. - * Note that we don't use sc->sc_mem. - */ - sc->sc_addr = 0; - sc->sc_memsize = rman_get_size(lesc->sc_bres); - sc->sc_flags = 0; - - /* That old black magic... */ - if (OF_getprop(ofw_bus_get_node(dev), "busmaster-regval", - &sc->sc_conf3, sizeof(sc->sc_conf3)) == -1) - sc->sc_conf3 = LE_C3_ACON | LE_C3_BCON; - /* - * Make sure LE_C3_BSWP is cleared so that for cards where - * that flag actually works le_lebuffer_copy{from,to}buf() - * don't fail... - */ - sc->sc_conf3 &= ~LE_C3_BSWP; - - OF_getetheraddr(dev, sc->sc_enaddr); - - sc->sc_copytodesc = le_lebuffer_copytodesc; - sc->sc_copyfromdesc = le_lebuffer_copyfromdesc; - sc->sc_copytobuf = le_lebuffer_copytobuf; - sc->sc_copyfrombuf = le_lebuffer_copyfrombuf; - sc->sc_zerobuf = le_lebuffer_zerobuf; - - sc->sc_rdcsr = le_lebuffer_rdcsr; - sc->sc_wrcsr = le_lebuffer_wrcsr; - sc->sc_hwreset = NULL; - sc->sc_hwinit = NULL; - sc->sc_hwintr = NULL; - sc->sc_nocarrier = NULL; - sc->sc_mediachange = NULL; - sc->sc_mediastatus = NULL; - sc->sc_supmedia = le_lebuffer_media; - sc->sc_nsupmedia = NLEMEDIA; - sc->sc_defaultmedia = le_lebuffer_media[0]; - - error = am7990_config(&lesc->sc_am7990, device_get_name(dev), - device_get_unit(dev)); - if (error != 0) { - device_printf(dev, "cannot attach Am7990\n"); - goto fail_ires; - } - - error = bus_setup_intr(dev, lesc->sc_ires, INTR_TYPE_NET | INTR_MPSAFE, - NULL, am7990_intr, sc, &lesc->sc_ih); - if (error != 0) { - device_printf(dev, "cannot set up interrupt\n"); - goto fail_am7990; - } - - return (0); - - fail_am7990: - am7990_detach(&lesc->sc_am7990); - fail_ires: - bus_release_resource(dev, SYS_RES_IRQ, - rman_get_rid(lesc->sc_ires), lesc->sc_ires); - fail_rres: - bus_release_resource(dev, SYS_RES_MEMORY, - rman_get_rid(lesc->sc_rres), lesc->sc_rres); - fail_bres: - bus_release_resource(device_get_parent(dev), SYS_RES_MEMORY, - rman_get_rid(lesc->sc_bres), lesc->sc_bres); - fail_mtx: - LE_LOCK_DESTROY(sc); - return (error); -} - -static int -le_lebuffer_detach(device_t dev) -{ - struct le_lebuffer_softc *lesc; - struct lance_softc *sc; - - lesc = device_get_softc(dev); - sc = &lesc->sc_am7990.lsc; - - bus_teardown_intr(dev, lesc->sc_ires, lesc->sc_ih); - am7990_detach(&lesc->sc_am7990); - bus_release_resource(dev, SYS_RES_IRQ, - rman_get_rid(lesc->sc_ires), lesc->sc_ires); - bus_release_resource(dev, SYS_RES_MEMORY, - rman_get_rid(lesc->sc_rres), lesc->sc_rres); - bus_release_resource(device_get_parent(dev), SYS_RES_MEMORY, - rman_get_rid(lesc->sc_bres), lesc->sc_bres); - LE_LOCK_DESTROY(sc); - - return (0); -} - -static int -le_buffer_suspend(device_t dev) -{ - struct le_lebuffer_softc *lesc; - - lesc = device_get_softc(dev); - - lance_suspend(&lesc->sc_am7990.lsc); - - return (0); -} - -static int -le_buffer_resume(device_t dev) -{ - struct le_lebuffer_softc *lesc; - - lesc = device_get_softc(dev); - - lance_resume(&lesc->sc_am7990.lsc); - - return (0); -} diff --git a/sys/dev/le/if_le_ledma.c b/sys/dev/le/if_le_ledma.c deleted file mode 100644 index c7adb722933..00000000000 --- a/sys/dev/le/if_le_ledma.c +++ /dev/null @@ -1,495 +0,0 @@ -/* $NetBSD: if_le_ledma.c,v 1.26 2005/12/11 12:23:44 christos Exp $ */ - -/*- - * SPDX-License-Identifier: BSD-2-Clause-NetBSD - * - * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. - * All rights reserved. - * - * This code is derived from software contributed to The NetBSD Foundation - * by Charles M. Hannum; Jason R. Thorpe of the Numerical Aerospace - * Simulation Facility, NASA Ames Research Center; Paul Kranenburg. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS - * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include -#include -#include - -#include -#include -#include -#include - -#include -#include - -#include -#include -#include - -#define LEDMA_ALIGNMENT 8 /* ring desc. alignmet for NCR92C990 */ -#define LEDMA_BOUNDARY (16*1024*1024) /* must not cross 16MB boundary */ -#define LEDMA_MEMSIZE (16*1024) /* LANCE memory size */ -#define LEREG1_RDP 0 /* Register Data Port */ -#define LEREG1_RAP 2 /* Register Address Port */ - -struct le_dma_softc { - struct am7990_softc sc_am7990; /* glue to MI code */ - - struct resource *sc_rres; - - struct resource *sc_ires; - void *sc_ih; - - bus_dma_tag_t sc_dmat; - bus_dmamap_t sc_dmam; - bus_addr_t sc_laddr; /* LANCE DMA address */ - - struct lsi64854_softc *sc_dma; /* pointer to DMA engine */ -}; - -static device_probe_t le_dma_probe; -static device_attach_t le_dma_attach; -static device_detach_t le_dma_detach; -static device_resume_t le_dma_resume; -static device_suspend_t le_dma_suspend; - -static device_method_t le_dma_methods[] = { - /* Device interface */ - DEVMETHOD(device_probe, le_dma_probe), - DEVMETHOD(device_attach, le_dma_attach), - DEVMETHOD(device_detach, le_dma_detach), - /* We can just use the suspend method here. */ - DEVMETHOD(device_shutdown, le_dma_suspend), - DEVMETHOD(device_suspend, le_dma_suspend), - DEVMETHOD(device_resume, le_dma_resume), - - { 0, 0 } -}; - -DEFINE_CLASS_0(le, le_dma_driver, le_dma_methods, sizeof(struct le_dma_softc)); -DRIVER_MODULE(le, dma, le_dma_driver, le_devclass, 0, 0); -MODULE_DEPEND(le, dma, 1, 1, 1); -MODULE_DEPEND(le, ether, 1, 1, 1); - -/* - * Media types supported - */ -static const int le_dma_supmedia[] = { - IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, 0), - IFM_MAKEWORD(IFM_ETHER, IFM_10_T, 0, 0), - IFM_MAKEWORD(IFM_ETHER, IFM_10_5, 0, 0) -}; - -static void le_dma_wrcsr(struct lance_softc *, uint16_t, uint16_t); -static uint16_t le_dma_rdcsr(struct lance_softc *, uint16_t); -static void le_dma_setutp(struct lance_softc *); -static void le_dma_setaui(struct lance_softc *); -static int le_dma_supmediachange(struct lance_softc *); -static void le_dma_supmediastatus(struct lance_softc *, struct ifmediareq *); -static void le_dma_hwreset(struct lance_softc *); -static int le_dma_hwintr(struct lance_softc *); -static void le_dma_nocarrier(struct lance_softc *); -static bus_dmamap_callback_t le_dma_dma_callback; - -static void -le_dma_wrcsr(struct lance_softc *sc, uint16_t port, uint16_t val) -{ - struct le_dma_softc *lesc = (struct le_dma_softc *)sc; - - bus_write_2(lesc->sc_rres, LEREG1_RAP, port); - bus_barrier(lesc->sc_rres, LEREG1_RAP, 2, BUS_SPACE_BARRIER_WRITE); - bus_write_2(lesc->sc_rres, LEREG1_RDP, val); -} - -static uint16_t -le_dma_rdcsr(struct lance_softc *sc, uint16_t port) -{ - struct le_dma_softc *lesc = (struct le_dma_softc *)sc; - - bus_write_2(lesc->sc_rres, LEREG1_RAP, port); - bus_barrier(lesc->sc_rres, LEREG1_RAP, 2, BUS_SPACE_BARRIER_WRITE); - return (bus_read_2(lesc->sc_rres, LEREG1_RDP)); -} - -static void -le_dma_setutp(struct lance_softc *sc) -{ - struct lsi64854_softc *dma = ((struct le_dma_softc *)sc)->sc_dma; - - L64854_SCSR(dma, L64854_GCSR(dma) | E_TP_AUI); - DELAY(20000); /* We must not touch the LANCE chip for 20ms. */ -} - -static void -le_dma_setaui(struct lance_softc *sc) -{ - struct lsi64854_softc *dma = ((struct le_dma_softc *)sc)->sc_dma; - - L64854_SCSR(dma, L64854_GCSR(dma) & ~E_TP_AUI); - DELAY(20000); /* We must not touch the LANCE chip for 20ms. */ -} - -static int -le_dma_supmediachange(struct lance_softc *sc) -{ - struct ifmedia *ifm = &sc->sc_media; - - if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) - return (EINVAL); - - /* - * Switch to the selected media. If autoselect is set, we don't - * really have to do anything. We'll switch to the other media - * when we detect loss of carrier. - */ - switch (IFM_SUBTYPE(ifm->ifm_media)) { - case IFM_10_T: - le_dma_setutp(sc); - break; - - case IFM_10_5: - le_dma_setaui(sc); - break; - - case IFM_AUTO: - break; - - default: - return (EINVAL); - } - - return (0); -} - -static void -le_dma_supmediastatus(struct lance_softc *sc, struct ifmediareq *ifmr) -{ - struct lsi64854_softc *dma = ((struct le_dma_softc *)sc)->sc_dma; - - /* - * Notify the world which media we're currently using. - */ - if (L64854_GCSR(dma) & E_TP_AUI) - ifmr->ifm_active = IFM_MAKEWORD(IFM_ETHER, IFM_10_T, 0, 0); - else - ifmr->ifm_active = IFM_MAKEWORD(IFM_ETHER, IFM_10_5, 0, 0); -} - -static void -le_dma_hwreset(struct lance_softc *sc) -{ - struct le_dma_softc *lesc = (struct le_dma_softc *)sc; - struct lsi64854_softc *dma = lesc->sc_dma; - uint32_t aui_bit, csr; - - /* - * Reset DMA channel. - */ - csr = L64854_GCSR(dma); - aui_bit = csr & E_TP_AUI; - DMA_RESET(dma); - - /* Write bits 24-31 of Lance address. */ - bus_write_4(dma->sc_res, L64854_REG_ENBAR, - lesc->sc_laddr & 0xff000000); - - DMA_ENINTR(dma); - - /* - * Disable E-cache invalidates on chip writes. - * Retain previous cable selection bit. - */ - csr = L64854_GCSR(dma); - csr |= (E_DSBL_WR_INVAL | aui_bit); - L64854_SCSR(dma, csr); - DELAY(20000); /* We must not touch the LANCE chip for 20ms. */ -} - -static int -le_dma_hwintr(struct lance_softc *sc) -{ - struct le_dma_softc *lesc = (struct le_dma_softc *)sc; - struct lsi64854_softc *dma = lesc->sc_dma; - - return (DMA_INTR(dma)); -} - -static void -le_dma_nocarrier(struct lance_softc *sc) -{ - struct le_dma_softc *lesc = (struct le_dma_softc *)sc; - - /* - * Check if the user has requested a certain cable type, and - * if so, honor that request. - */ - - if (L64854_GCSR(lesc->sc_dma) & E_TP_AUI) { - switch (IFM_SUBTYPE(sc->sc_media.ifm_media)) { - case IFM_10_5: - case IFM_AUTO: - if_printf(sc->sc_ifp, "lost carrier on UTP port, " - "switching to AUI port\n"); - le_dma_setaui(sc); - } - } else { - switch (IFM_SUBTYPE(sc->sc_media.ifm_media)) { - case IFM_10_T: - case IFM_AUTO: - if_printf(sc->sc_ifp, "lost carrier on AUI port, " - "switching to UTP port\n"); - le_dma_setutp(sc); - } - } -} - -static void -le_dma_dma_callback(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) -{ - struct le_dma_softc *lesc = (struct le_dma_softc *)xsc; - - if (error != 0) - return; - KASSERT(nsegs == 1, ("%s: bad DMA segment count", __func__)); - lesc->sc_laddr = segs[0].ds_addr; -} - -static int -le_dma_probe(device_t dev) -{ - - if (strcmp(ofw_bus_get_name(dev), "le") == 0) { - device_set_desc(dev, "LANCE Ethernet"); - return (BUS_PROBE_DEFAULT); - } - return (ENXIO); -} - -static int -le_dma_attach(device_t dev) -{ - struct le_dma_softc *lesc; - struct lsi64854_softc *dma; - struct lance_softc *sc; - int error, i; - - lesc = device_get_softc(dev); - sc = &lesc->sc_am7990.lsc; - - LE_LOCK_INIT(sc, device_get_nameunit(dev)); - - /* - * Establish link to `ledma' device. - * XXX hackery. - */ - dma = (struct lsi64854_softc *)device_get_softc(device_get_parent(dev)); - lesc->sc_dma = dma; - lesc->sc_dma->sc_client = lesc; - - i = 0; - lesc->sc_rres = bus_alloc_resource_any(dev, SYS_RES_MEMORY, - &i, RF_ACTIVE); - if (lesc->sc_rres == NULL) { - device_printf(dev, "cannot allocate registers\n"); - error = ENXIO; - goto fail_mtx; - } - - i = 0; - if ((lesc->sc_ires = bus_alloc_resource_any(dev, SYS_RES_IRQ, - &i, RF_SHAREABLE | RF_ACTIVE)) == NULL) { - device_printf(dev, "cannot allocate interrupt\n"); - error = ENXIO; - goto fail_rres; - } - - /* Attach the DMA engine. */ - error = lsi64854_attach(dma); - if (error != 0) { - device_printf(dev, "lsi64854_attach failed\n"); - goto fail_ires; - } - - sc->sc_memsize = LEDMA_MEMSIZE; - error = bus_dma_tag_create( - dma->sc_parent_dmat, /* parent */ - LEDMA_ALIGNMENT, /* alignment */ - LEDMA_BOUNDARY, /* boundary */ - BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ - BUS_SPACE_MAXADDR, /* highaddr */ - NULL, NULL, /* filter, filterarg */ - sc->sc_memsize, /* maxsize */ - 1, /* nsegments */ - sc->sc_memsize, /* maxsegsize */ - 0, /* flags */ - NULL, NULL, /* lockfunc, lockarg */ - &lesc->sc_dmat); - if (error != 0) { - device_printf(dev, "cannot allocate buffer DMA tag\n"); - goto fail_lsi; - } - - error = bus_dmamem_alloc(lesc->sc_dmat, (void **)&sc->sc_mem, - BUS_DMA_WAITOK | BUS_DMA_COHERENT, &lesc->sc_dmam); - if (error != 0) { - device_printf(dev, "cannot allocate DMA buffer memory\n"); - goto fail_dtag; - } - - lesc->sc_laddr = 0; - error = bus_dmamap_load(lesc->sc_dmat, lesc->sc_dmam, sc->sc_mem, - sc->sc_memsize, le_dma_dma_callback, lesc, 0); - if (error != 0 || lesc->sc_laddr == 0) { - device_printf(dev, "cannot load DMA buffer map\n"); - goto fail_dmem; - } - - sc->sc_addr = lesc->sc_laddr & 0xffffff; - sc->sc_flags = 0; - sc->sc_conf3 = LE_C3_BSWP | LE_C3_ACON | LE_C3_BCON; - - sc->sc_mediachange = le_dma_supmediachange; - sc->sc_mediastatus = le_dma_supmediastatus; - sc->sc_supmedia = le_dma_supmedia; - sc->sc_nsupmedia = nitems(le_dma_supmedia); - sc->sc_defaultmedia = le_dma_supmedia[0]; - - OF_getetheraddr(dev, sc->sc_enaddr); - - sc->sc_copytodesc = lance_copytobuf_contig; - sc->sc_copyfromdesc = lance_copyfrombuf_contig; - sc->sc_copytobuf = lance_copytobuf_contig; - sc->sc_copyfrombuf = lance_copyfrombuf_contig; - sc->sc_zerobuf = lance_zerobuf_contig; - - sc->sc_rdcsr = le_dma_rdcsr; - sc->sc_wrcsr = le_dma_wrcsr; - sc->sc_hwreset = le_dma_hwreset; - sc->sc_hwintr = le_dma_hwintr; - sc->sc_nocarrier = le_dma_nocarrier; - - error = am7990_config(&lesc->sc_am7990, device_get_name(dev), - device_get_unit(dev)); - if (error != 0) { - device_printf(dev, "cannot attach Am7990\n"); - goto fail_dmap; - } - - error = bus_setup_intr(dev, lesc->sc_ires, INTR_TYPE_NET | INTR_MPSAFE, - NULL, am7990_intr, sc, &lesc->sc_ih); - if (error != 0) { - device_printf(dev, "cannot set up interrupt\n"); - goto fail_am7990; - } - - return (0); - - fail_am7990: - am7990_detach(&lesc->sc_am7990); - fail_dmap: - bus_dmamap_unload(lesc->sc_dmat, lesc->sc_dmam); - fail_dmem: - bus_dmamem_free(lesc->sc_dmat, sc->sc_mem, lesc->sc_dmam); - fail_dtag: - bus_dma_tag_destroy(lesc->sc_dmat); - fail_lsi: - lsi64854_detach(dma); - fail_ires: - bus_release_resource(dev, SYS_RES_IRQ, rman_get_rid(lesc->sc_ires), - lesc->sc_ires); - fail_rres: - bus_release_resource(dev, SYS_RES_MEMORY, rman_get_rid(lesc->sc_rres), - lesc->sc_rres); - fail_mtx: - LE_LOCK_DESTROY(sc); - return (error); -} - -static int -le_dma_detach(device_t dev) -{ - struct le_dma_softc *lesc; - struct lance_softc *sc; - int error; - - lesc = device_get_softc(dev); - sc = &lesc->sc_am7990.lsc; - - bus_teardown_intr(dev, lesc->sc_ires, lesc->sc_ih); - am7990_detach(&lesc->sc_am7990); - bus_dmamap_unload(lesc->sc_dmat, lesc->sc_dmam); - bus_dmamem_free(lesc->sc_dmat, sc->sc_mem, lesc->sc_dmam); - bus_dma_tag_destroy(lesc->sc_dmat); - error = lsi64854_detach(lesc->sc_dma); - if (error != 0) - return (error); - bus_release_resource(dev, SYS_RES_IRQ, rman_get_rid(lesc->sc_ires), - lesc->sc_ires); - bus_release_resource(dev, SYS_RES_MEMORY, rman_get_rid(lesc->sc_rres), - lesc->sc_rres); - LE_LOCK_DESTROY(sc); - - return (0); -} - -static int -le_dma_suspend(device_t dev) -{ - struct le_dma_softc *lesc; - - lesc = device_get_softc(dev); - - lance_suspend(&lesc->sc_am7990.lsc); - - return (0); -} - -static int -le_dma_resume(device_t dev) -{ - struct le_dma_softc *lesc; - - lesc = device_get_softc(dev); - - lance_resume(&lesc->sc_am7990.lsc); - - return (0); -} diff --git a/sys/dev/le/lebuffer_sbus.c b/sys/dev/le/lebuffer_sbus.c deleted file mode 100644 index e0cea141467..00000000000 --- a/sys/dev/le/lebuffer_sbus.c +++ /dev/null @@ -1,304 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2006 Marius Strobl - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include -#include -#include - -#include -#include -#include - -struct lebuffer_devinfo { - struct ofw_bus_devinfo ldi_obdinfo; - struct resource_list ldi_rl; -}; - -static devclass_t lebuffer_devclass; - -static device_probe_t lebuffer_probe; -static device_attach_t lebuffer_attach; -static device_detach_t lebuffer_detach; -static bus_print_child_t lebuffer_print_child; -static bus_probe_nomatch_t lebuffer_probe_nomatch; -static bus_get_resource_list_t lebuffer_get_resource_list; -static ofw_bus_get_devinfo_t lebuffer_get_devinfo; - -static struct lebuffer_devinfo *lebuffer_setup_dinfo(device_t, phandle_t); -static void lebuffer_destroy_dinfo(struct lebuffer_devinfo *); -static int lebuffer_print_res(struct lebuffer_devinfo *); - -static device_method_t lebuffer_methods[] = { - /* Device interface */ - DEVMETHOD(device_probe, lebuffer_probe), - DEVMETHOD(device_attach, lebuffer_attach), - DEVMETHOD(device_detach, lebuffer_detach), - DEVMETHOD(device_shutdown, bus_generic_shutdown), - DEVMETHOD(device_suspend, bus_generic_suspend), - DEVMETHOD(device_resume, bus_generic_resume), - - /* Bus interface */ - DEVMETHOD(bus_print_child, lebuffer_print_child), - DEVMETHOD(bus_probe_nomatch, lebuffer_probe_nomatch), - DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), - DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), - DEVMETHOD(bus_alloc_resource, bus_generic_rl_alloc_resource), - DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource), - DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource), - DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), - DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), - DEVMETHOD(bus_get_resource_list, lebuffer_get_resource_list), - DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), - - /* ofw_bus interface */ - DEVMETHOD(ofw_bus_get_devinfo, lebuffer_get_devinfo), - DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat), - DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model), - DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name), - DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node), - DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type), - - { 0, 0 } -}; - -DEFINE_CLASS_0(lebuffer, lebuffer_driver, lebuffer_methods, 1); -DRIVER_MODULE(lebuffer, sbus, lebuffer_driver, lebuffer_devclass, 0, 0); -MODULE_DEPEND(lebuffer, sbus, 1, 1, 1); -MODULE_VERSION(lebuffer, 1); - -static int -lebuffer_probe(device_t dev) -{ - const char *name; - - name = ofw_bus_get_name(dev); - if (strcmp(name, "lebuffer") == 0) { - device_set_desc_copy(dev, name); - return (0); - } - return (ENXIO); -} - -static int -lebuffer_attach(device_t dev) -{ - struct lebuffer_devinfo *ldi; - device_t cdev; - phandle_t child; - int children; - - children = 0; - for (child = OF_child(ofw_bus_get_node(dev)); child != 0; - child = OF_peer(child)) { - if ((ldi = lebuffer_setup_dinfo(dev, child)) == NULL) - continue; - if (children != 0) { - device_printf(dev, - "<%s>: only one child per buffer supported\n", - ldi->ldi_obdinfo.obd_name); - lebuffer_destroy_dinfo(ldi); - continue; - } - if ((cdev = device_add_child(dev, NULL, -1)) == NULL) { - device_printf(dev, "<%s>: device_add_child failed\n", - ldi->ldi_obdinfo.obd_name); - lebuffer_destroy_dinfo(ldi); - continue; - } - device_set_ivars(cdev, ldi); - children++; - } - return (bus_generic_attach(dev)); -} - -static int -lebuffer_detach(device_t dev) -{ - device_t *children; - int i, nchildren; - - bus_generic_detach(dev); - if (device_get_children(dev, &children, &nchildren) == 0) { - for (i = 0; i < nchildren; i++) { - lebuffer_destroy_dinfo(device_get_ivars(children[i])); - device_delete_child(dev, children[i]); - } - free(children, M_TEMP); - } - return (0); -} - -static struct lebuffer_devinfo * -lebuffer_setup_dinfo(device_t dev, phandle_t node) -{ - struct lebuffer_devinfo *ldi; - struct sbus_regs *reg; - uint32_t base, iv, *intr; - int i, nreg, nintr, slot, rslot; - - ldi = malloc(sizeof(*ldi), M_DEVBUF, M_WAITOK | M_ZERO); - if (ofw_bus_gen_setup_devinfo(&ldi->ldi_obdinfo, node) != 0) { - free(ldi, M_DEVBUF); - return (NULL); - } - resource_list_init(&ldi->ldi_rl); - slot = -1; - nreg = OF_getprop_alloc_multi(node, "reg", sizeof(*reg), (void **)®); - if (nreg == -1) { - device_printf(dev, "<%s>: incomplete\n", - ldi->ldi_obdinfo.obd_name); - goto fail; - } - for (i = 0; i < nreg; i++) { - base = reg[i].sbr_offset; - if (SBUS_ABS(base)) { - rslot = SBUS_ABS_TO_SLOT(base); - base = SBUS_ABS_TO_OFFSET(base); - } else - rslot = reg[i].sbr_slot; - if (slot != -1 && slot != rslot) { - device_printf(dev, "<%s>: multiple slots\n", - ldi->ldi_obdinfo.obd_name); - OF_prop_free(reg); - goto fail; - } - slot = rslot; - - resource_list_add(&ldi->ldi_rl, SYS_RES_MEMORY, i, base, - base + reg[i].sbr_size, reg[i].sbr_size); - } - OF_prop_free(reg); - if (slot != sbus_get_slot(dev)) { - device_printf(dev, "<%s>: parent and child slot do not match\n", - ldi->ldi_obdinfo.obd_name); - goto fail; - } - - /* - * The `interrupts' property contains the SBus interrupt level. - */ - nintr = OF_getprop_alloc_multi(node, "interrupts", sizeof(*intr), - (void **)&intr); - if (nintr != -1) { - for (i = 0; i < nintr; i++) { - iv = intr[i]; - /* - * SBus card devices need the slot number encoded into - * the vector as this is generally not done. - */ - if ((iv & INTMAP_OBIO_MASK) == 0) - iv |= slot << 3; - /* Set the IGN as appropriate. */ - iv |= sbus_get_ign(dev) << INTMAP_IGN_SHIFT; - resource_list_add(&ldi->ldi_rl, SYS_RES_IRQ, i, - iv, iv, 1); - } - OF_prop_free(intr); - } - return (ldi); - - fail: - lebuffer_destroy_dinfo(ldi); - return (NULL); -} - -static void -lebuffer_destroy_dinfo(struct lebuffer_devinfo *dinfo) -{ - - resource_list_free(&dinfo->ldi_rl); - ofw_bus_gen_destroy_devinfo(&dinfo->ldi_obdinfo); - free(dinfo, M_DEVBUF); -} - -static int -lebuffer_print_child(device_t dev, device_t child) -{ - int rv; - - rv = bus_print_child_header(dev, child); - rv += lebuffer_print_res(device_get_ivars(child)); - rv += bus_print_child_footer(dev, child); - return (rv); -} - -static void -lebuffer_probe_nomatch(device_t dev, device_t child) -{ - const char *type; - - device_printf(dev, "<%s>", ofw_bus_get_name(child)); - lebuffer_print_res(device_get_ivars(child)); - type = ofw_bus_get_type(child); - printf(" type %s (no driver attached)\n", - type != NULL ? type : "unknown"); -} - -static struct resource_list * -lebuffer_get_resource_list(device_t dev, device_t child) -{ - struct lebuffer_devinfo *ldi; - - ldi = device_get_ivars(child); - return (&ldi->ldi_rl); -} - -static const struct ofw_bus_devinfo * -lebuffer_get_devinfo(device_t bus, device_t child) -{ - struct lebuffer_devinfo *ldi; - - ldi = device_get_ivars(child); - return (&ldi->ldi_obdinfo); -} - -static int -lebuffer_print_res(struct lebuffer_devinfo *ldi) -{ - int rv; - - rv = 0; - rv += resource_list_print_type(&ldi->ldi_rl, "mem", SYS_RES_MEMORY, - "%#jx"); - rv += resource_list_print_type(&ldi->ldi_rl, "irq", SYS_RES_IRQ, "%jd"); - return (rv); -} diff --git a/sys/dev/ofw/openpromio.c b/sys/dev/ofw/openpromio.c deleted file mode 100644 index 03f6bc0a82c..00000000000 --- a/sys/dev/ofw/openpromio.c +++ /dev/null @@ -1,236 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2003 Jake Burkholder. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - */ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -/* - * This provides a Solaris compatible character device interface to - * Open Firmware. It exists entirely for compatibility with software - * like X11, and only the features that are actually needed for that - * are implemented. The interface sucks too much to actually use, - * new code should use the /dev/openfirm device. - */ - -static d_open_t openprom_open; -static d_close_t openprom_close; -static d_ioctl_t openprom_ioctl; - -static int openprom_modevent(module_t mode, int type, void *data); -static int openprom_node_valid(phandle_t node); -static int openprom_node_search(phandle_t root, phandle_t node); - -static struct cdevsw openprom_cdevsw = { - .d_version = D_VERSION, - .d_flags = D_NEEDGIANT, - .d_open = openprom_open, - .d_close = openprom_close, - .d_ioctl = openprom_ioctl, - .d_name = "openprom", -}; - -static int openprom_is_open; -static struct cdev *openprom_dev; -static phandle_t openprom_node; - -static int -openprom_open(struct cdev *dev, int oflags, int devtype, struct thread *td) -{ - - if (openprom_is_open != 0) - return (EBUSY); - openprom_is_open = 1; - return (0); -} - -static int -openprom_close(struct cdev *dev, int fflag, int devtype, struct thread *td) -{ - - openprom_is_open = 0; - return (0); -} - -static int -openprom_ioctl(struct cdev *dev, u_long cmd, caddr_t data, int flags, - struct thread *td) -{ - struct openpromio *oprom; - phandle_t node; - uint32_t len; - size_t done; - int proplen; - char *prop; - char *buf; - int error; - - if ((flags & FREAD) == 0) - return (EPERM); - - prop = buf = NULL; - error = 0; - switch (cmd) { - case OPROMCHILD: - case OPROMNEXT: - if (data == NULL || *(void **)data == NULL) - return (EINVAL); - oprom = *(void **)data; - error = copyin(&oprom->oprom_size, &len, sizeof(len)); - if (error != 0) - break; - if (len != sizeof(node)) { - error = EINVAL; - break; - } - error = copyin(&oprom->oprom_array, &node, sizeof(node)); - if (error != 0) - break; - error = openprom_node_valid(node); - if (error != 0) - break; - switch (cmd) { - case OPROMCHILD: - node = OF_child(node); - break; - case OPROMNEXT: - node = OF_peer(node); - break; - } - error = copyout(&node, &oprom->oprom_array, sizeof(node)); - if (error != 0) - break; - openprom_node = node; - break; - case OPROMGETPROP: - case OPROMNXTPROP: - if (data == NULL || *(void **)data == NULL) - return (EINVAL); - oprom = *(void **)data; - error = copyin(&oprom->oprom_size, &len, sizeof(len)); - if (error != 0) - break; - if (len > OPROMMAXPARAM) { - error = EINVAL; - break; - } - prop = malloc(len, M_TEMP, M_WAITOK | M_ZERO); - error = copyinstr(&oprom->oprom_array, prop, len, &done); - if (error != 0) - break; - buf = malloc(OPROMMAXPARAM, M_TEMP, M_WAITOK | M_ZERO); - node = openprom_node; - switch (cmd) { - case OPROMGETPROP: - proplen = OF_getproplen(node, prop); - if (proplen > OPROMMAXPARAM) { - error = EINVAL; - break; - } - error = OF_getprop(node, prop, buf, proplen); - break; - case OPROMNXTPROP: - error = OF_nextprop(node, prop, buf, OPROMMAXPARAM); - proplen = strlen(buf); - break; - } - if (error != -1) { - error = copyout(&proplen, &oprom->oprom_size, - sizeof(proplen)); - if (error == 0) - error = copyout(buf, &oprom->oprom_array, - proplen + 1); - } else - error = EINVAL; - break; - default: - error = ENOIOCTL; - break; - } - - if (prop != NULL) - free(prop, M_TEMP); - if (buf != NULL) - free(buf, M_TEMP); - - return (error); -} - -static int -openprom_node_valid(phandle_t node) -{ - - if (node == 0) - return (0); - return (openprom_node_search(OF_peer(0), node)); -} - -static int -openprom_node_search(phandle_t root, phandle_t node) -{ - phandle_t child; - - if (root == node) - return (0); - for (child = OF_child(root); child != 0 && child != -1; - child = OF_peer(child)) - if (openprom_node_search(child, node) == 0) - return (0); - return (EINVAL); -} - -static int -openprom_modevent(module_t mode, int type, void *data) -{ - - switch (type) { - case MOD_LOAD: - openprom_dev = make_dev(&openprom_cdevsw, 0, UID_ROOT, - GID_WHEEL, 0600, "openprom"); - return (0); - case MOD_UNLOAD: - destroy_dev(openprom_dev); - return (0); - default: - return (EOPNOTSUPP); - } -} - -DEV_MODULE(openprom, openprom_modevent, NULL); diff --git a/sys/dev/ofw/openpromio.h b/sys/dev/ofw/openpromio.h deleted file mode 100644 index 67d8fda499f..00000000000 --- a/sys/dev/ofw/openpromio.h +++ /dev/null @@ -1,47 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2003 Jake Burkholder. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - */ - -#ifndef _DEV_OFW_OPENPROMIO_H_ -#define _DEV_OFW_OPENPROMIO_H_ - -#include - -struct openpromio { - uint32_t oprom_size; - char oprom_array[]; -}; - -#define OPROMNEXT _IO('O', 1) -#define OPROMCHILD _IO('O', 2) -#define OPROMGETPROP _IO('O', 3) -#define OPROMNXTPROP _IO('O', 4) - -#define OPROMMAXPARAM 4096 - -#endif diff --git a/sys/dev/pccard/power_if.m b/sys/dev/pccard/power_if.m deleted file mode 100644 index f6279479eef..00000000000 --- a/sys/dev/pccard/power_if.m +++ /dev/null @@ -1,45 +0,0 @@ -#- -# Copyright (c) 1999 M. Warner Losh. -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# -# THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND -# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -# ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE -# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -# OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -# HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -# OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -# SUCH DAMAGE. -# -# - -#include - -INTERFACE power; - -# -# Interface for powering cards on/off. It is hoped that this will be -# generic enough to be used for other systems in addition to the pccard -# <-> pcic interface that it was originally written for. -# -METHOD int enable_socket { - device_t dev; - device_t child; -}; - -METHOD int disable_socket { - device_t dev; - device_t child; -}; diff --git a/sys/dev/pccbb/pccbb_isa.c b/sys/dev/pccbb/pccbb_isa.c deleted file mode 100644 index 83b4aafbd1b..00000000000 --- a/sys/dev/pccbb/pccbb_isa.c +++ /dev/null @@ -1,256 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2002-2004 M. Warner Losh. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -/* - * Driver for ISA to PCMCIA bridges compliant with the Intel ExCA - * specification. - */ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include -#include - -#include -#include - -#include -#include - -#include -#include - -#include "power_if.h" -#include "card_if.h" - -/***************************************************************************** - * Configurable parameters. - *****************************************************************************/ - -/* sysctl vars */ -static SYSCTL_NODE(_hw, OID_AUTO, pcic, CTLFLAG_RD, 0, "PCIC parameters"); - -static int isa_intr_mask = EXCA_INT_MASK_ALLOWED; -SYSCTL_INT(_hw_pcic, OID_AUTO, intr_mask, CTLFLAG_RDTUN, &isa_intr_mask, 0, - "Mask of allowable interrupts for this laptop. The default is generally" - " correct, but some laptops do not route all the IRQ pins to the bridge to" - " save wires. Sometimes you need a more restrictive mask because some of" - " the hardware in your laptop may not have a driver so its IRQ might not be" - " allocated."); - -/* - * CL-PD6722's VSENSE method - * 0: NO VSENSE (assume a 5.0V card always) - * 1: 6710's method (default) - * 2: 6729's method - */ -int pcic_pd6722_vsense = 1; -SYSCTL_INT(_hw_pcic, OID_AUTO, pd6722_vsense, CTLFLAG_RDTUN, - &pcic_pd6722_vsense, 1, - "Select CL-PD6722's VSENSE method. VSENSE is used to determine the" - " voltage of inserted cards. The CL-PD6722 has two methods to determine" - " the voltage of the card. 0 means assume a 5.0V card and do not check. 1" - " means use the same method that the CL-PD6710 uses (default). 2 means use" - " the same method as the CL-PD6729. 2 is documented in the datasheet as" - " being the correct way, but 1 seems to give better results on more" - " laptops."); -/***************************************************************************** - * End of configurable parameters. - *****************************************************************************/ - -#define DPRINTF(x) do { if (cbb_debug) printf x; } while (0) -#define DEVPRINTF(x) do { if (cbb_debug) device_printf x; } while (0) - -static struct isa_pnp_id pcic_ids[] = { - {EXCA_PNP_ACTIONTEC, NULL}, /* AEI0218 */ - {EXCA_PNP_IBM3765, NULL}, /* IBM3765 */ - {EXCA_PNP_82365, NULL}, /* PNP0E00 */ - {EXCA_PNP_CL_PD6720, NULL}, /* PNP0E01 */ - {EXCA_PNP_VLSI_82C146, NULL}, /* PNP0E02 */ - {EXCA_PNP_82365_CARDBUS, NULL}, /* PNP0E03 */ - {EXCA_PNP_SCM_SWAPBOX, NULL}, /* SCM0469 */ - {0} -}; - -/************************************************************************/ -/* Probe/Attach */ -/************************************************************************/ - -static int -cbb_isa_activate(device_t dev) -{ - struct cbb_softc *sc = device_get_softc(dev); - struct resource *res; - int rid; - int i; - - /* A little bogus, but go ahead and get the irq for CSC events */ - rid = 0; - res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE); - if (res == NULL) { - /* - * No IRQ specified, find one. This can be due to the PnP - * data not specifying any IRQ, or the default kernel not - * assinging an IRQ. - */ - for (i = 0; i < 16 && res == NULL; i++) { - if (((1 << i) & isa_intr_mask) == 0) - continue; - res = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, i, i, - 1, RF_ACTIVE); - } - } - if (res == NULL) - return (ENXIO); - sc->irq_res = res; - rid = 0; - res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, RF_ACTIVE); - if (res == NULL) { - bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq_res); - sc->irq_res = NULL; - device_printf(dev, "Cannot allocate I/O\n"); - return (ENOMEM); - } - sc->bst = rman_get_bustag(res); - sc->bsh = rman_get_bushandle(res); - sc->base_res = res; - return (0); -} - -static void -cbb_isa_deactivate(device_t dev) -{ - struct cbb_softc *sc = device_get_softc(dev); - - if (sc->irq_res) - bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq_res); - sc->irq_res = NULL; - if (sc->base_res) - bus_release_resource(dev, SYS_RES_IOPORT, 0, sc->base_res); - sc->base_res = NULL; -} - -static int -cbb_isa_probe(device_t dev) -{ - int error; - struct cbb_softc *sc = device_get_softc(dev); - - /* Check isapnp ids */ - error = ISA_PNP_PROBE(device_get_parent(dev), dev, pcic_ids); - if (error != 0 && error != ENOENT) - return (error); - - error = cbb_isa_activate(dev); - if (error != 0) - return (error); - - /* Check to make sure that we have actual hardware */ - error = exca_probe_slots(dev, &sc->exca[0], sc->bst, sc->bsh); - cbb_isa_deactivate(dev); - return (error); -} - -static int -cbb_isa_attach(device_t dev) -{ - return (ENOMEM); -} - -static int -cbb_isa_suspend(device_t dev) -{ - return (0); -} - -static int -cbb_isa_resume(device_t dev) -{ - return (0); -} - -static device_method_t cbb_methods[] = { - /* Device interface */ - DEVMETHOD(device_probe, cbb_isa_probe), - DEVMETHOD(device_attach, cbb_isa_attach), - DEVMETHOD(device_detach, cbb_detach), - DEVMETHOD(device_suspend, cbb_isa_suspend), - DEVMETHOD(device_resume, cbb_isa_resume), - - /* bus methods */ - DEVMETHOD(bus_read_ivar, cbb_read_ivar), - DEVMETHOD(bus_write_ivar, cbb_write_ivar), - DEVMETHOD(bus_alloc_resource, cbb_alloc_resource), - DEVMETHOD(bus_release_resource, cbb_release_resource), - DEVMETHOD(bus_activate_resource, cbb_activate_resource), - DEVMETHOD(bus_deactivate_resource, cbb_deactivate_resource), - DEVMETHOD(bus_driver_added, cbb_driver_added), - DEVMETHOD(bus_child_detached, cbb_child_detached), - DEVMETHOD(bus_setup_intr, cbb_setup_intr), - DEVMETHOD(bus_teardown_intr, cbb_teardown_intr), - DEVMETHOD(bus_child_present, cbb_child_present), - - /* 16-bit card interface */ - DEVMETHOD(card_set_res_flags, cbb_pcic_set_res_flags), - DEVMETHOD(card_set_memory_offset, cbb_pcic_set_memory_offset), - - /* power interface */ - DEVMETHOD(power_enable_socket, cbb_power_enable_socket), - DEVMETHOD(power_disable_socket, cbb_power_disable_socket), - - DEVMETHOD_END -}; - -static driver_t cbb_isa_driver = { - "cbb", - cbb_methods, - sizeof(struct cbb_softc) -}; - -DRIVER_MODULE(cbb, isa, cbb_isa_driver, cbb_devclass, 0, 0); -MODULE_DEPEND(cbb, exca, 1, 1, 1); -ISA_PNP_INFO(pcic_ids); diff --git a/sys/dev/pcf/envctrl.c b/sys/dev/pcf/envctrl.c deleted file mode 100644 index af57d4416f5..00000000000 --- a/sys/dev/pcf/envctrl.c +++ /dev/null @@ -1,193 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2004 Joerg Wunsch - * - * derived from sys/i386/isa/pcf.c which is: - * - * Copyright (c) 1998 Nicolas Souchu, Marc Bouget - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ -#include - -/* - * Device specific driver for the SUNW,envctrl device found on some - * UltraSPARC Sun systems. This device is a Philips PCF8584 sitting - * on the Ebus2. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include -#include - -#include - -#include -#include -#include -#include "iicbus_if.h" - -#undef PCF_DEFAULT_ADDR -#define PCF_DEFAULT_ADDR 0x55 /* SUNW,pcf default */ - -static int envctrl_probe(device_t); -static int envctrl_attach(device_t); -static int envctrl_detach(device_t); - -static device_method_t envctrl_methods[] = { - /* device interface */ - DEVMETHOD(device_probe, envctrl_probe), - DEVMETHOD(device_attach, envctrl_attach), - DEVMETHOD(device_detach, envctrl_detach), - - /* iicbus interface */ - DEVMETHOD(iicbus_callback, iicbus_null_callback), - DEVMETHOD(iicbus_repeated_start, pcf_repeated_start), - DEVMETHOD(iicbus_start, pcf_start), - DEVMETHOD(iicbus_stop, pcf_stop), - DEVMETHOD(iicbus_write, pcf_write), - DEVMETHOD(iicbus_read, pcf_read), - DEVMETHOD(iicbus_reset, pcf_rst_card), - { 0, 0 } -}; - -static devclass_t envctrl_devclass; - -static driver_t envctrl_driver = { - "envctrl", - envctrl_methods, - sizeof(struct pcf_softc), -}; - -static int -envctrl_probe(device_t dev) -{ - - if (strcmp("SUNW,envctrl", ofw_bus_get_name(dev)) == 0) { - device_set_desc(dev, "EBus SUNW,envctrl"); - return (0); - } - return (ENXIO); -} - -static int -envctrl_attach(device_t dev) -{ - struct pcf_softc *sc; - int rv = ENXIO; - - sc = DEVTOSOFTC(dev); - mtx_init(&sc->pcf_lock, device_get_nameunit(dev), "pcf", MTX_DEF); - - /* IO port is mandatory */ - sc->res_ioport = bus_alloc_resource_any(dev, SYS_RES_MEMORY, - &sc->rid_ioport, RF_ACTIVE); - if (sc->res_ioport == 0) { - device_printf(dev, "cannot reserve I/O port range\n"); - goto error; - } - - sc->pcf_flags = device_get_flags(dev); - - if (!(sc->pcf_flags & IIC_POLLED)) { - sc->res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->rid_irq, - RF_ACTIVE); - if (sc->res_irq == 0) { - device_printf(dev, "can't reserve irq, polled mode.\n"); - sc->pcf_flags |= IIC_POLLED; - } - } - - /* reset the chip */ - pcf_rst_card(dev, IIC_FASTEST, PCF_DEFAULT_ADDR, NULL); - - rv = bus_setup_intr(dev, sc->res_irq, - INTR_TYPE_NET | INTR_MPSAFE /* | INTR_ENTROPY */, - NULL, pcf_intr, sc, &sc->intr_cookie); - if (rv) { - device_printf(dev, "could not setup IRQ\n"); - goto error; - } - - if ((sc->iicbus = device_add_child(dev, "iicbus", -1)) == NULL) - device_printf(dev, "could not allocate iicbus instance\n"); - - /* probe and attach the iicbus */ - bus_generic_attach(dev); - - return (0); - -error: - if (sc->res_irq != 0) { - bus_release_resource(dev, SYS_RES_IRQ, sc->rid_irq, - sc->res_irq); - } - if (sc->res_ioport != 0) { - bus_release_resource(dev, SYS_RES_MEMORY, sc->rid_ioport, - sc->res_ioport); - } - mtx_destroy(&sc->pcf_lock); - return (rv); -} - -static int -envctrl_detach(device_t dev) -{ - struct pcf_softc *sc; - int rv; - - sc = DEVTOSOFTC(dev); - - if ((rv = bus_generic_detach(dev)) != 0) - return (rv); - - if ((rv = device_delete_child(dev, sc->iicbus)) != 0) - return (rv); - - if (sc->res_irq != 0) { - bus_teardown_intr(dev, sc->res_irq, sc->intr_cookie); - bus_release_resource(dev, SYS_RES_IRQ, sc->rid_irq, sc->res_irq); - } - - bus_release_resource(dev, SYS_RES_MEMORY, sc->rid_ioport, sc->res_ioport); - mtx_destroy(&sc->pcf_lock); - - return (0); -} - -DRIVER_MODULE(envctrl, ebus, envctrl_driver, envctrl_devclass, 0, 0); -DRIVER_MODULE(iicbus, envctrl, iicbus_driver, iicbus_devclass, 0, 0); diff --git a/sys/dev/pcf/pcf_ebus.c b/sys/dev/pcf/pcf_ebus.c deleted file mode 100644 index 5b26527435f..00000000000 --- a/sys/dev/pcf/pcf_ebus.c +++ /dev/null @@ -1,255 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2004 Marius Strobl, Joerg Wunsch - * - * derived from sys/i386/isa/pcf.c which is: - * - * Copyright (c) 1998 Nicolas Souchu, Marc Bouget - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ -#include - -/* - * Device specific driver for the EBus i2c devices found on some sun4u - * systems. On systems not having a boot-bus controller the i2c devices - * are PCF8584. - * - * Known onboard slave devices on the primary bus are: - * - * AXe: - * 0x40 PCF8574 I/O fan status (CPU fans 1+2) - * 0x9e PCF8591 A/D temperature (CPU + hotspot) - * - * AXmp: - * 0x70 PCF8574 I/O fan status (fans 1-4) - * 0x78 PCF8574 I/O fan fail interrupt - * 0x9a PCF8591 A/D voltage (CPU core) - * 0x9c PCF8591 A/D temperature (hotspots 1+2, aux. analog 1+2) - * 0x9e PCF8591 A/D temperature (CPUs 1-4) - * - * CP1400: - * 0x70 PCF8574 I/O reserved for factory use - * 0x9e PCF8591 A/D temperature (CPU) - * - * CP1500: - * 0x70 PCF8574 I/O reserved for factory use - * 0x72 PCF8574 I/O geographic address + power supply status lines - * 0x9e PCF8591 A/D temperature (CPU) - * 0xa0 AT24C01A hostid - * - * For AXmp, CP1400 and CP1500 these are described in more detail in: - * http://www.sun.com/oem/products/manuals/805-7581-04.pdf - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include -#include - -#include - -#include -#include -#include "iicbus_if.h" - -#define PCF_NAME "pcf" - -static int pcf_ebus_probe(device_t); -static int pcf_ebus_attach(device_t); -static int pcf_ebus_detach(device_t); - -static device_method_t pcf_ebus_methods[] = { - /* device interface */ - DEVMETHOD(device_probe, pcf_ebus_probe), - DEVMETHOD(device_attach, pcf_ebus_attach), - DEVMETHOD(device_detach, pcf_ebus_detach), - - /* iicbus interface */ - DEVMETHOD(iicbus_callback, iicbus_null_callback), - DEVMETHOD(iicbus_repeated_start, pcf_repeated_start), - DEVMETHOD(iicbus_start, pcf_start), - DEVMETHOD(iicbus_stop, pcf_stop), - DEVMETHOD(iicbus_write, pcf_write), - DEVMETHOD(iicbus_read, pcf_read), - DEVMETHOD(iicbus_reset, pcf_rst_card), - { 0, 0 } -}; - -static devclass_t pcf_ebus_devclass; - -static driver_t pcf_ebus_driver = { - PCF_NAME, - pcf_ebus_methods, - sizeof(struct pcf_softc), -}; - -static int -pcf_ebus_probe(device_t dev) -{ - const char *compat; - - /* - * We must not attach to this i2c device if this is a system with - * a boot-bus controller. Additionally testing the compatibility - * property will hopefully take care of this. - */ - if (strcmp("i2c", ofw_bus_get_name(dev)) == 0) { - compat = ofw_bus_get_compat(dev); - if (compat != NULL && strcmp("i2cpcf,8584", compat) == 0) { - device_set_desc(dev, "PCF8584 I2C bus controller"); - return (0); - } - } - return (ENXIO); -} - -static int -pcf_ebus_attach(device_t dev) -{ - struct pcf_softc *sc; - int rv = ENXIO; - phandle_t node; - uint64_t own_addr; - - sc = DEVTOSOFTC(dev); - mtx_init(&sc->pcf_lock, device_get_nameunit(dev), "pcf", MTX_DEF); - - /* get OFW node of the pcf */ - if ((node = ofw_bus_get_node(dev)) == -1) { - device_printf(dev, "cannot get OFW node\n"); - goto error; - } - - /* IO port is mandatory */ - sc->res_ioport = bus_alloc_resource_any(dev, SYS_RES_MEMORY, - &sc->rid_ioport, RF_ACTIVE); - if (sc->res_ioport == 0) { - device_printf(dev, "cannot reserve I/O port range\n"); - goto error; - } - - sc->pcf_flags = device_get_flags(dev); - - /* - * XXX use poll-mode property? - */ - if (!(sc->pcf_flags & IIC_POLLED)) { - sc->res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, - &sc->rid_irq, RF_ACTIVE); - if (sc->res_irq == 0) { - device_printf(dev, "can't reserve irq, polled mode.\n"); - sc->pcf_flags |= IIC_POLLED; - } - } - - /* - * XXX on AXmp there's probably a second IRQ which is the fan fail - * interrupt genererated by the PCF8574 at 0x78. - */ - - /* get address of the pcf */ - if (OF_getprop(node, "own-address", &own_addr, sizeof(own_addr)) == - -1) { - device_printf(dev, "cannot get own address\n"); - goto error; - } - if (bootverbose) - device_printf(dev, "PCF8584 address: 0x%08llx\n", (unsigned - long long)own_addr); - - /* reset the chip */ - pcf_rst_card(dev, IIC_FASTEST, own_addr, NULL); - - if (sc->res_irq) { - rv = bus_setup_intr(dev, sc->res_irq, - INTR_TYPE_NET /* | INTR_ENTROPY */, NULL, pcf_intr, sc, - &sc->intr_cookie); - if (rv) { - device_printf(dev, "could not setup IRQ\n"); - goto error; - } - } - - if ((sc->iicbus = device_add_child(dev, "iicbus", -1)) == NULL) - device_printf(dev, "could not allocate iicbus instance\n"); - - /* probe and attach the iicbus */ - bus_generic_attach(dev); - - return (0); - -error: - if (sc->res_irq != 0) { - bus_release_resource(dev, SYS_RES_IRQ, sc->rid_irq, - sc->res_irq); - } - if (sc->res_ioport != 0) { - bus_release_resource(dev, SYS_RES_MEMORY, sc->rid_ioport, - sc->res_ioport); - } - mtx_destroy(&sc->pcf_lock); - return (rv); -} - -static int -pcf_ebus_detach(device_t dev) -{ - struct pcf_softc *sc; - int rv; - - sc = DEVTOSOFTC(dev); - - if ((rv = bus_generic_detach(dev)) != 0) - return (rv); - - if ((rv = device_delete_child(dev, sc->iicbus)) != 0) - return (rv); - - if (sc->res_irq != 0) { - bus_teardown_intr(dev, sc->res_irq, - sc->intr_cookie); - bus_release_resource(dev, SYS_RES_IRQ, sc->rid_irq, - sc->res_irq); - } - - bus_release_resource(dev, SYS_RES_MEMORY, sc->rid_ioport, - sc->res_ioport); - mtx_destroy(&sc->pcf_lock); - - return (0); -} - -DRIVER_MODULE(pcf_ebus, ebus, pcf_ebus_driver, pcf_ebus_devclass, 0, 0); diff --git a/sys/dev/ppbus/immio.c b/sys/dev/ppbus/immio.c deleted file mode 100644 index 487a222811b..00000000000 --- a/sys/dev/ppbus/immio.c +++ /dev/null @@ -1,817 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 1998, 1999 Nicolas Souchu - * Copyright (c) 2001 Alcove - Nicolas Souchu - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * - */ - -#include - -/* - * Iomega ZIP+ Matchmaker Parallel Port Interface driver - * - * Thanks to David Campbell work on the Linux driver and the Iomega specs - * Thanks to Thiebault Moeglin for the drive - */ -#ifdef _KERNEL -#include -#include -#include -#include -#include - -#endif /* _KERNEL */ - -#include "opt_vpo.h" - -#include -#include -#include -#include -#include - -#include "ppbus_if.h" - -#define VP0_SELTMO 5000 /* select timeout */ -#define VP0_FAST_SPINTMO 500000 /* wait status timeout */ -#define VP0_LOW_SPINTMO 5000000 /* wait status timeout */ - -#define VP0_SECTOR_SIZE 512 - -/* - * Microcode to execute very fast I/O sequences at the lowest bus level. - */ - -#define WAIT_RET MS_PARAM(7, 2, MS_TYP_PTR) -#define WAIT_TMO MS_PARAM(1, 0, MS_TYP_INT) - -#define DECLARE_WAIT_MICROSEQUENCE \ -struct ppb_microseq wait_microseq[] = { \ - MS_CASS(0x0c), \ - MS_SET(MS_UNKNOWN), \ - /* loop */ \ - MS_BRSET(nBUSY, 4 /* ready */), \ - MS_DBRA(-2 /* loop */), \ - MS_CASS(0x04), \ - MS_RET(1), /* timed out */ \ - /* ready */ \ - MS_CASS(0x04), \ - MS_RFETCH(MS_REG_STR, 0xb8, MS_UNKNOWN ), \ - MS_RET(0) /* no error */ \ -} - -#define SELECT_TARGET MS_PARAM(6, 1, MS_TYP_CHA) - -#define DECLARE_SELECT_MICROSEQUENCE \ -struct ppb_microseq select_microseq[] = { \ - MS_CASS(0xc), \ - /* first, check there is nothing holding onto the bus */ \ - MS_SET(VP0_SELTMO), \ -/* _loop: */ \ - MS_BRCLEAR(0x8, 2 /* _ready */), \ - MS_DBRA(-2 /* _loop */), \ - MS_RET(2), /* bus busy */ \ -/* _ready: */ \ - MS_CASS(0x4), \ - MS_DASS(MS_UNKNOWN /* 0x80 | 1 << target */), \ - MS_DELAY(1), \ - MS_CASS(0xc), \ - MS_CASS(0xd), \ - /* now, wait until the drive is ready */ \ - MS_SET(VP0_SELTMO), \ -/* loop: */ \ - MS_BRSET(0x8, 3 /* ready */), \ - MS_DBRA(-2 /* loop */), \ -/* error: */ \ - MS_CASS(0xc), \ - MS_RET(VP0_ESELECT_TIMEOUT), \ -/* ready: */ \ - MS_CASS(0xc), \ - MS_RET(0) \ -} - -static struct ppb_microseq transfer_epilog[] = { - MS_CASS(0x4), - MS_CASS(0xc), - MS_CASS(0xe), - MS_CASS(0x4), - MS_RET(0) -}; - -#define CPP_S1 MS_PARAM(10, 2, MS_TYP_PTR) -#define CPP_S2 MS_PARAM(13, 2, MS_TYP_PTR) -#define CPP_S3 MS_PARAM(16, 2, MS_TYP_PTR) -#define CPP_PARAM MS_PARAM(17, 1, MS_TYP_CHA) - -#define DECLARE_CPP_MICROSEQ \ -struct ppb_microseq cpp_microseq[] = { \ - MS_CASS(0x0c), MS_DELAY(2), \ - MS_DASS(0xaa), MS_DELAY(10), \ - MS_DASS(0x55), MS_DELAY(10), \ - MS_DASS(0x00), MS_DELAY(10), \ - MS_DASS(0xff), MS_DELAY(10), \ - MS_RFETCH(MS_REG_STR, 0xb8, MS_UNKNOWN /* &s1 */), \ - MS_DASS(0x87), MS_DELAY(10), \ - MS_RFETCH(MS_REG_STR, 0xb8, MS_UNKNOWN /* &s2 */), \ - MS_DASS(0x78), MS_DELAY(10), \ - MS_RFETCH(MS_REG_STR, 0x38, MS_UNKNOWN /* &s3 */), \ - MS_DASS(MS_UNKNOWN /* param */), \ - MS_DELAY(2), \ - MS_CASS(0x0c), MS_DELAY(10), \ - MS_CASS(0x0d), MS_DELAY(2), \ - MS_CASS(0x0c), MS_DELAY(10), \ - MS_DASS(0xff), MS_DELAY(10), \ - MS_RET(0) \ -} - -#define NEGOCIATED_MODE MS_PARAM(2, 1, MS_TYP_CHA) - -#define DECLARE_NEGOCIATE_MICROSEQ \ -struct ppb_microseq negociate_microseq[] = { \ - MS_CASS(0x4), \ - MS_DELAY(5), \ - MS_DASS(MS_UNKNOWN /* mode */), \ - MS_DELAY(100), \ - MS_CASS(0x6), \ - MS_DELAY(5), \ - MS_BRSET(0x20, 5 /* continue */), \ - MS_DELAY(5), \ - MS_CASS(0x7), \ - MS_DELAY(5), \ - MS_CASS(0x6), \ - MS_RET(VP0_ENEGOCIATE), \ -/* continue: */ \ - MS_DELAY(5), \ - MS_CASS(0x7), \ - MS_DELAY(5), \ - MS_CASS(0x6), \ - MS_RET(0) \ -} - -#define INB_NIBBLE_L MS_PARAM(3, 2, MS_TYP_PTR) -#define INB_NIBBLE_H MS_PARAM(6, 2, MS_TYP_PTR) -#define INB_NIBBLE_F MS_PARAM(9, 0, MS_TYP_FUN) -#define INB_NIBBLE_P MS_PARAM(9, 1, MS_TYP_PTR) - -/* - * This is the sub-microseqence for MS_GET in NIBBLE mode - * Retrieve the two nibbles and call the C function to generate the character - * and store it in the buffer (see nibble_inbyte_hook()) - */ - -#define DECLARE_NIBBLE_INBYTE_SUBMICROSEQ \ -struct ppb_microseq nibble_inbyte_submicroseq[] = { \ - MS_CASS(0x4), \ -/* loop: */ \ - MS_CASS(0x6), \ - MS_DELAY(1), \ - MS_RFETCH(MS_REG_STR, MS_FETCH_ALL, MS_UNKNOWN /* low nibble */),\ - MS_CASS(0x5), \ - MS_DELAY(1), \ - MS_RFETCH(MS_REG_STR, MS_FETCH_ALL, MS_UNKNOWN /* high nibble */),\ - MS_CASS(0x4), \ - MS_DELAY(1), \ - /* do a C call to format the received nibbles */ \ - MS_C_CALL(MS_UNKNOWN /* C hook */, MS_UNKNOWN /* param */), \ - MS_DBRA(-7 /* loop */), \ - MS_RET(0) \ -} - -static struct ppb_microseq reset_microseq[] = { - MS_CASS(0x04), - MS_DASS(0x40), - MS_DELAY(1), - MS_CASS(0x0c), - MS_CASS(0x0d), - MS_DELAY(50), - MS_CASS(0x0c), - MS_CASS(0x04), - MS_RET(0) -}; - -/* - * nibble_inbyte_hook() - * - * Formats high and low nibble into a character - */ -static int -nibble_inbyte_hook (void *p, char *ptr) -{ - struct vpo_nibble *s = (struct vpo_nibble *)p; - - /* increment the buffer pointer */ - *ptr = ((s->l >> 4) & 0x0f) + (s->h & 0xf0); - - return (0); -} - -/* - * This is the sub-microseqence for MS_GET in PS2 mode - */ -static struct ppb_microseq ps2_inbyte_submicroseq[] = { - MS_CASS(0x4), - -/* loop: */ - MS_CASS(PCD | 0x6), - MS_RFETCH_P(1, MS_REG_DTR, MS_FETCH_ALL), - MS_CASS(PCD | 0x5), - MS_DBRA(-4 /* loop */), - - MS_RET(0) -}; - -/* - * This is the sub-microsequence for MS_PUT in both NIBBLE and PS2 modes - */ -static struct ppb_microseq spp_outbyte_submicroseq[] = { - MS_CASS(0x4), - -/* loop: */ - MS_RASSERT_P(1, MS_REG_DTR), - MS_CASS(0x5), - MS_DBRA(0), /* decrement counter */ - MS_RASSERT_P(1, MS_REG_DTR), - MS_CASS(0x0), - MS_DBRA(-6 /* loop */), - - /* return from the put call */ - MS_CASS(0x4), - MS_RET(0) -}; - -/* EPP 1.7 microsequences, ptr and len set at runtime */ -static struct ppb_microseq epp17_outstr[] = { - MS_CASS(0x4), - MS_RASSERT_P(MS_ACCUM, MS_REG_EPP_D), - MS_CASS(0xc), - MS_RET(0), -}; - -static struct ppb_microseq epp17_instr[] = { - MS_CASS(PCD | 0x4), - MS_RFETCH_P(MS_ACCUM, MS_REG_EPP_D, MS_FETCH_ALL), - MS_CASS(PCD | 0xc), - MS_RET(0), -}; - -static int -imm_disconnect(struct vpoio_data *vpo, int *connected, int release_bus) -{ - DECLARE_CPP_MICROSEQ; - - device_t ppbus = device_get_parent(vpo->vpo_dev); - char s1, s2, s3; - int ret; - - /* all should be ok */ - if (connected) - *connected = 0; - - ppb_MS_init_msq(cpp_microseq, 4, CPP_S1, (void *)&s1, - CPP_S2, (void *)&s2, CPP_S3, (void *)&s3, - CPP_PARAM, 0x30); - - ppb_MS_microseq(ppbus, vpo->vpo_dev, cpp_microseq, &ret); - - if ((s1 != (char)0xb8 || s2 != (char)0x18 || s3 != (char)0x38)) { - if (bootverbose) - device_printf(vpo->vpo_dev, - "(disconnect) s1=0x%x s2=0x%x, s3=0x%x\n", - s1 & 0xff, s2 & 0xff, s3 & 0xff); - if (connected) - *connected = VP0_ECONNECT; - } - - if (release_bus) - return (ppb_release_bus(ppbus, vpo->vpo_dev)); - else - return (0); -} - -/* - * how : PPB_WAIT or PPB_DONTWAIT - */ -static int -imm_connect(struct vpoio_data *vpo, int how, int *disconnected, int request_bus) -{ - DECLARE_CPP_MICROSEQ; - - device_t ppbus = device_get_parent(vpo->vpo_dev); - char s1, s2, s3; - int error; - int ret; - - /* all should be ok */ - if (disconnected) - *disconnected = 0; - - if (request_bus) - if ((error = ppb_request_bus(ppbus, vpo->vpo_dev, how))) - return (error); - - ppb_MS_init_msq(cpp_microseq, 3, CPP_S1, (void *)&s1, - CPP_S2, (void *)&s2, CPP_S3, (void *)&s3); - - /* select device 0 in compatible mode */ - ppb_MS_init_msq(cpp_microseq, 1, CPP_PARAM, 0xe0); - ppb_MS_microseq(ppbus, vpo->vpo_dev, cpp_microseq, &ret); - - /* disconnect all devices */ - ppb_MS_init_msq(cpp_microseq, 1, CPP_PARAM, 0x30); - ppb_MS_microseq(ppbus, vpo->vpo_dev, cpp_microseq, &ret); - - if (PPB_IN_EPP_MODE(ppbus)) - ppb_MS_init_msq(cpp_microseq, 1, CPP_PARAM, 0x28); - else - ppb_MS_init_msq(cpp_microseq, 1, CPP_PARAM, 0xe0); - - ppb_MS_microseq(ppbus, vpo->vpo_dev, cpp_microseq, &ret); - - if ((s1 != (char)0xb8 || s2 != (char)0x18 || s3 != (char)0x30)) { - if (bootverbose) - device_printf(vpo->vpo_dev, - "(connect) s1=0x%x s2=0x%x, s3=0x%x\n", - s1 & 0xff, s2 & 0xff, s3 & 0xff); - if (disconnected) - *disconnected = VP0_ECONNECT; - } - - return (0); -} - -/* - * imm_detect() - * - * Detect and initialise the VP0 adapter. - */ -static int -imm_detect(struct vpoio_data *vpo) -{ - device_t ppbus = device_get_parent(vpo->vpo_dev); - int error; - - if ((error = ppb_request_bus(ppbus, vpo->vpo_dev, PPB_DONTWAIT))) - return (error); - - /* disconnect the drive, keep the bus */ - imm_disconnect(vpo, NULL, 0); - - vpo->vpo_mode_found = VP0_MODE_UNDEFINED; - error = 1; - - /* try to enter EPP mode since vpoio failure put the bus in NIBBLE */ - if (ppb_set_mode(ppbus, PPB_EPP) != -1) { - imm_connect(vpo, PPB_DONTWAIT, &error, 0); - } - - /* if connection failed try PS/2 then NIBBLE modes */ - if (error) { - if (ppb_set_mode(ppbus, PPB_PS2) != -1) { - imm_connect(vpo, PPB_DONTWAIT, &error, 0); - } - if (error) { - if (ppb_set_mode(ppbus, PPB_NIBBLE) != -1) { - imm_connect(vpo, PPB_DONTWAIT, &error, 0); - if (error) - goto error; - vpo->vpo_mode_found = VP0_MODE_NIBBLE; - } else { - device_printf(vpo->vpo_dev, - "NIBBLE mode unavailable!\n"); - goto error; - } - } else { - vpo->vpo_mode_found = VP0_MODE_PS2; - } - } else { - vpo->vpo_mode_found = VP0_MODE_EPP; - } - - /* send SCSI reset signal */ - ppb_MS_microseq(ppbus, vpo->vpo_dev, reset_microseq, NULL); - - /* release the bus now */ - imm_disconnect(vpo, &error, 1); - - /* ensure we are disconnected or daisy chained peripheral - * may cause serious problem to the disk */ - - if (error) { - if (bootverbose) - device_printf(vpo->vpo_dev, - "can't disconnect from the drive\n"); - goto error; - } - - return (0); - -error: - ppb_release_bus(ppbus, vpo->vpo_dev); - return (VP0_EINITFAILED); -} - -/* - * imm_outstr() - */ -static int -imm_outstr(struct vpoio_data *vpo, char *buffer, int size) -{ - device_t ppbus = device_get_parent(vpo->vpo_dev); - int error = 0; - - if (PPB_IN_EPP_MODE(ppbus)) - ppb_reset_epp_timeout(ppbus); - - ppb_MS_exec(ppbus, vpo->vpo_dev, MS_OP_PUT, (union ppb_insarg)buffer, - (union ppb_insarg)size, (union ppb_insarg)MS_UNKNOWN, &error); - - return (error); -} - -/* - * imm_instr() - */ -static int -imm_instr(struct vpoio_data *vpo, char *buffer, int size) -{ - device_t ppbus = device_get_parent(vpo->vpo_dev); - int error = 0; - - if (PPB_IN_EPP_MODE(ppbus)) - ppb_reset_epp_timeout(ppbus); - - ppb_MS_exec(ppbus, vpo->vpo_dev, MS_OP_GET, (union ppb_insarg)buffer, - (union ppb_insarg)size, (union ppb_insarg)MS_UNKNOWN, &error); - - return (error); -} - -static char -imm_select(struct vpoio_data *vpo, int initiator, int target) -{ - DECLARE_SELECT_MICROSEQUENCE; - device_t ppbus = device_get_parent(vpo->vpo_dev); - int ret; - - /* initialize the select microsequence */ - ppb_MS_init_msq(select_microseq, 1, - SELECT_TARGET, 1 << initiator | 1 << target); - - ppb_MS_microseq(ppbus, vpo->vpo_dev, select_microseq, &ret); - - return (ret); -} - -/* - * imm_wait() - * - * H_SELIN must be low. - * - */ -static char -imm_wait(struct vpoio_data *vpo, int tmo) -{ - DECLARE_WAIT_MICROSEQUENCE; - - device_t ppbus = device_get_parent(vpo->vpo_dev); - int ret, err; - - /* - * Return some status information. - * Semantics : 0x88 = ZIP+ wants more data - * 0x98 = ZIP+ wants to send more data - * 0xa8 = ZIP+ wants command - * 0xb8 = end of transfer, ZIP+ is sending status - */ - - ppb_MS_init_msq(wait_microseq, 2, - WAIT_RET, (void *)&ret, - WAIT_TMO, tmo); - - ppb_MS_microseq(ppbus, vpo->vpo_dev, wait_microseq, &err); - - if (err) - return (0); /* command timed out */ - - return(ret); -} - -static int -imm_negociate(struct vpoio_data *vpo) -{ - DECLARE_NEGOCIATE_MICROSEQ; - device_t ppbus = device_get_parent(vpo->vpo_dev); - int negociate_mode; - int ret; - - if (PPB_IN_NIBBLE_MODE(ppbus)) - negociate_mode = 0; - else if (PPB_IN_PS2_MODE(ppbus)) - negociate_mode = 1; - else - return (0); - -#if 0 /* XXX use standalone code not to depend on ppb_1284 code yet */ - ret = ppb_1284_negociate(ppbus, negociate_mode); - - if (ret) - return (VP0_ENEGOCIATE); -#endif - - ppb_MS_init_msq(negociate_microseq, 1, - NEGOCIATED_MODE, negociate_mode); - - ppb_MS_microseq(ppbus, vpo->vpo_dev, negociate_microseq, &ret); - - return (ret); -} - -/* - * imm_probe() - * - * Low level probe of vpo device - * - */ -int -imm_probe(device_t dev, struct vpoio_data *vpo) -{ - int error; - - /* ppbus dependent initialisation */ - vpo->vpo_dev = dev; - - /* now, try to initialise the drive */ - if ((error = imm_detect(vpo))) { - return (error); - } - - return (0); -} - -/* - * imm_attach() - * - * Low level attachment of vpo device - * - */ -int -imm_attach(struct vpoio_data *vpo) -{ - DECLARE_NIBBLE_INBYTE_SUBMICROSEQ; - device_t ppbus = device_get_parent(vpo->vpo_dev); - int error = 0; - - /* - * Initialize microsequence code - */ - vpo->vpo_nibble_inbyte_msq = (struct ppb_microseq *)malloc( - sizeof(nibble_inbyte_submicroseq), M_DEVBUF, M_NOWAIT); - - if (!vpo->vpo_nibble_inbyte_msq) - return (ENXIO); - - bcopy((void *)nibble_inbyte_submicroseq, - (void *)vpo->vpo_nibble_inbyte_msq, - sizeof(nibble_inbyte_submicroseq)); - - ppb_MS_init_msq(vpo->vpo_nibble_inbyte_msq, 4, - INB_NIBBLE_H, (void *)&(vpo)->vpo_nibble.h, - INB_NIBBLE_L, (void *)&(vpo)->vpo_nibble.l, - INB_NIBBLE_F, nibble_inbyte_hook, - INB_NIBBLE_P, (void *)&(vpo)->vpo_nibble); - - /* - * Initialize mode dependent in/out microsequences - */ - ppb_lock(ppbus); - if ((error = ppb_request_bus(ppbus, vpo->vpo_dev, PPB_WAIT))) - goto error; - - /* ppbus automatically restore the last mode entered during detection */ - switch (vpo->vpo_mode_found) { - case VP0_MODE_EPP: - ppb_MS_GET_init(ppbus, vpo->vpo_dev, epp17_instr); - ppb_MS_PUT_init(ppbus, vpo->vpo_dev, epp17_outstr); - device_printf(vpo->vpo_dev, "EPP mode\n"); - break; - case VP0_MODE_PS2: - ppb_MS_GET_init(ppbus, vpo->vpo_dev, ps2_inbyte_submicroseq); - ppb_MS_PUT_init(ppbus, vpo->vpo_dev, spp_outbyte_submicroseq); - device_printf(vpo->vpo_dev, "PS2 mode\n"); - break; - case VP0_MODE_NIBBLE: - ppb_MS_GET_init(ppbus, vpo->vpo_dev, vpo->vpo_nibble_inbyte_msq); - ppb_MS_PUT_init(ppbus, vpo->vpo_dev, spp_outbyte_submicroseq); - device_printf(vpo->vpo_dev, "NIBBLE mode\n"); - break; - default: - panic("imm: unknown mode %d", vpo->vpo_mode_found); - } - - ppb_release_bus(ppbus, vpo->vpo_dev); - error: - ppb_unlock(ppbus); - return (error); -} - -/* - * imm_reset_bus() - * - */ -int -imm_reset_bus(struct vpoio_data *vpo) -{ - device_t ppbus = device_get_parent(vpo->vpo_dev); - int disconnected; - - /* first, connect to the drive and request the bus */ - imm_connect(vpo, PPB_WAIT|PPB_INTR, &disconnected, 1); - - if (!disconnected) { - - /* reset the SCSI bus */ - ppb_MS_microseq(ppbus, vpo->vpo_dev, reset_microseq, NULL); - - /* then disconnect */ - imm_disconnect(vpo, NULL, 1); - } - - return (0); -} - -/* - * imm_do_scsi() - * - * Send an SCSI command - * - */ -int -imm_do_scsi(struct vpoio_data *vpo, int host, int target, char *command, - int clen, char *buffer, int blen, int *result, int *count, - int *ret) -{ - device_t ppbus = device_get_parent(vpo->vpo_dev); - char r; - char l, h = 0; - int len, error = 0, not_connected = 0; - int k; - int negociated = 0; - - /* - * enter disk state, allocate the ppbus - * - * XXX - * Should we allow this call to be interruptible? - * The only way to report the interruption is to return - * EIO to upper SCSI code :^( - */ - if ((error = imm_connect(vpo, PPB_WAIT|PPB_INTR, ¬_connected, 1))) - return (error); - - if (not_connected) { - *ret = VP0_ECONNECT; - goto error; - } - - /* - * Select the drive ... - */ - if ((*ret = imm_select(vpo,host,target))) - goto error; - - /* - * Send the command ... - */ - for (k = 0; k < clen; k+=2) { - if (imm_wait(vpo, VP0_FAST_SPINTMO) != (char)0xa8) { - *ret = VP0_ECMD_TIMEOUT; - goto error; - } - if (imm_outstr(vpo, &command[k], 2)) { - *ret = VP0_EPPDATA_TIMEOUT; - goto error; - } - } - - if (!(r = imm_wait(vpo, VP0_LOW_SPINTMO))) { - *ret = VP0_ESTATUS_TIMEOUT; - goto error; - } - - if ((r & 0x30) == 0x10) { - if (imm_negociate(vpo)) { - *ret = VP0_ENEGOCIATE; - goto error; - } else - negociated = 1; - } - - /* - * Complete transfer ... - */ - *count = 0; - for (;;) { - - if (!(r = imm_wait(vpo, VP0_LOW_SPINTMO))) { - *ret = VP0_ESTATUS_TIMEOUT; - goto error; - } - - /* stop when the ZIP+ wants to send status */ - if (r == (char)0xb8) - break; - - if (*count >= blen) { - *ret = VP0_EDATA_OVERFLOW; - goto error; - } - - /* ZIP+ wants to send data? */ - if (r == (char)0x88) { - len = (((blen - *count) >= VP0_SECTOR_SIZE)) ? - VP0_SECTOR_SIZE : 2; - - error = imm_outstr(vpo, &buffer[*count], len); - } else { - if (!PPB_IN_EPP_MODE(ppbus)) - len = 1; - else - len = (((blen - *count) >= VP0_SECTOR_SIZE)) ? - VP0_SECTOR_SIZE : 1; - - error = imm_instr(vpo, &buffer[*count], len); - } - - if (error) { - *ret = error; - goto error; - } - - *count += len; - } - - if ((PPB_IN_NIBBLE_MODE(ppbus) || - PPB_IN_PS2_MODE(ppbus)) && negociated) - ppb_MS_microseq(ppbus, vpo->vpo_dev, transfer_epilog, NULL); - - /* - * Retrieve status ... - */ - if (imm_negociate(vpo)) { - *ret = VP0_ENEGOCIATE; - goto error; - } else - negociated = 1; - - if (imm_instr(vpo, &l, 1)) { - *ret = VP0_EOTHER; - goto error; - } - - /* check if the ZIP+ wants to send more status */ - if (imm_wait(vpo, VP0_FAST_SPINTMO) == (char)0xb8) - if (imm_instr(vpo, &h, 1)) { - *ret = VP0_EOTHER + 2; - goto error; - } - - /* Experience showed that we should discard this */ - if (h == (char) -1) - h = 0; - - *result = ((int) h << 8) | ((int) l & 0xff); - -error: - if ((PPB_IN_NIBBLE_MODE(ppbus) || - PPB_IN_PS2_MODE(ppbus)) && negociated) - ppb_MS_microseq(ppbus, vpo->vpo_dev, transfer_epilog, NULL); - - /* return to printer state, release the ppbus */ - imm_disconnect(vpo, NULL, 1); - - return (0); -} diff --git a/sys/dev/ppbus/vpo.c b/sys/dev/ppbus/vpo.c deleted file mode 100644 index ac909d9ef60..00000000000 --- a/sys/dev/ppbus/vpo.c +++ /dev/null @@ -1,440 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 1997, 1998, 1999 Nicolas Souchu - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - */ - -#include - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include - -#include "opt_vpo.h" - -#include -#include - -#include "ppbus_if.h" - -struct vpo_sense { - struct scsi_sense cmd; - unsigned int stat; - unsigned int count; -}; - -struct vpo_data { - device_t vpo_dev; - int vpo_stat; - int vpo_count; - int vpo_error; - - int vpo_isplus; - - struct cam_sim *sim; - - struct vpo_sense vpo_sense; - - struct vpoio_data vpo_io; /* interface to low level functions */ -}; - -#define DEVTOSOFTC(dev) \ - ((struct vpo_data *)device_get_softc(dev)) - -/* cam related functions */ -static void vpo_action(struct cam_sim *sim, union ccb *ccb); -static void vpo_poll(struct cam_sim *sim); - -static void -vpo_identify(driver_t *driver, device_t parent) -{ - - device_t dev; - - dev = device_find_child(parent, "vpo", -1); - if (!dev) - BUS_ADD_CHILD(parent, 0, "vpo", -1); -} - -/* - * vpo_probe() - */ -static int -vpo_probe(device_t dev) -{ - device_t ppbus = device_get_parent(dev); - struct vpo_data *vpo; - int error; - - vpo = DEVTOSOFTC(dev); - vpo->vpo_dev = dev; - - /* check ZIP before ZIP+ or imm_probe() will send controls to - * the printer or whatelse connected to the port */ - ppb_lock(ppbus); - if ((error = vpoio_probe(dev, &vpo->vpo_io)) == 0) { - vpo->vpo_isplus = 0; - device_set_desc(dev, - "Iomega VPI0 Parallel to SCSI interface"); - } else if ((error = imm_probe(dev, &vpo->vpo_io)) == 0) { - vpo->vpo_isplus = 1; - device_set_desc(dev, - "Iomega Matchmaker Parallel to SCSI interface"); - } else { - ppb_unlock(ppbus); - return (error); - } - ppb_unlock(ppbus); - gone_in_dev(dev, 13, "Hardware no longer relevant"); - - return (0); -} - -/* - * vpo_attach() - */ -static int -vpo_attach(device_t dev) -{ - struct vpo_data *vpo = DEVTOSOFTC(dev); - device_t ppbus = device_get_parent(dev); - struct ppb_data *ppb = device_get_softc(ppbus); /* XXX: layering */ - struct cam_devq *devq; - int error; - - /* low level attachment */ - if (vpo->vpo_isplus) { - if ((error = imm_attach(&vpo->vpo_io))) - return (error); - } else { - if ((error = vpoio_attach(&vpo->vpo_io))) - return (error); - } - - /* - ** Now tell the generic SCSI layer - ** about our bus. - */ - devq = cam_simq_alloc(/*maxopenings*/1); - /* XXX What about low-level detach on error? */ - if (devq == NULL) - return (ENXIO); - - vpo->sim = cam_sim_alloc(vpo_action, vpo_poll, "vpo", vpo, - device_get_unit(dev), ppb->ppc_lock, - /*untagged*/1, /*tagged*/0, devq); - if (vpo->sim == NULL) { - cam_simq_free(devq); - return (ENXIO); - } - - ppb_lock(ppbus); - if (xpt_bus_register(vpo->sim, dev, /*bus*/0) != CAM_SUCCESS) { - cam_sim_free(vpo->sim, /*free_devq*/TRUE); - ppb_unlock(ppbus); - return (ENXIO); - } - ppb_unlock(ppbus); - - return (0); -} - -/* - * vpo_intr() - */ -static void -vpo_intr(struct vpo_data *vpo, struct ccb_scsiio *csio) -{ - int errno; /* error in errno.h */ -#ifdef VP0_DEBUG - int i; -#endif - uint8_t *ptr; - - ptr = scsiio_cdb_ptr(csio); - if (vpo->vpo_isplus) { - errno = imm_do_scsi(&vpo->vpo_io, VP0_INITIATOR, - csio->ccb_h.target_id, - ptr, csio->cdb_len, - (char *)csio->data_ptr, csio->dxfer_len, - &vpo->vpo_stat, &vpo->vpo_count, &vpo->vpo_error); - } else { - errno = vpoio_do_scsi(&vpo->vpo_io, VP0_INITIATOR, - csio->ccb_h.target_id, - ptr, csio->cdb_len, - (char *)csio->data_ptr, csio->dxfer_len, - &vpo->vpo_stat, &vpo->vpo_count, &vpo->vpo_error); - } - -#ifdef VP0_DEBUG - printf("vpo_do_scsi = %d, status = 0x%x, count = %d, vpo_error = %d\n", - errno, vpo->vpo_stat, vpo->vpo_count, vpo->vpo_error); - - /* dump of command */ - for (i=0; icdb_len; i++) - printf("%x ", ((char *)ptr)[i]); - - printf("\n"); -#endif - - if (errno) { - /* connection to ppbus interrupted */ - csio->ccb_h.status = CAM_CMD_TIMEOUT; - return; - } - - /* if a timeout occurred, no sense */ - if (vpo->vpo_error) { - if (vpo->vpo_error != VP0_ESELECT_TIMEOUT) - device_printf(vpo->vpo_dev, "VP0 error/timeout (%d)\n", - vpo->vpo_error); - - csio->ccb_h.status = CAM_CMD_TIMEOUT; - return; - } - - /* check scsi status */ - if (vpo->vpo_stat != SCSI_STATUS_OK) { - csio->scsi_status = vpo->vpo_stat; - - /* check if we have to sense the drive */ - if ((vpo->vpo_stat & SCSI_STATUS_CHECK_COND) != 0) { - - vpo->vpo_sense.cmd.opcode = REQUEST_SENSE; - vpo->vpo_sense.cmd.length = csio->sense_len; - vpo->vpo_sense.cmd.control = 0; - - if (vpo->vpo_isplus) { - errno = imm_do_scsi(&vpo->vpo_io, VP0_INITIATOR, - csio->ccb_h.target_id, - (char *)&vpo->vpo_sense.cmd, - sizeof(vpo->vpo_sense.cmd), - (char *)&csio->sense_data, csio->sense_len, - &vpo->vpo_sense.stat, &vpo->vpo_sense.count, - &vpo->vpo_error); - } else { - errno = vpoio_do_scsi(&vpo->vpo_io, VP0_INITIATOR, - csio->ccb_h.target_id, - (char *)&vpo->vpo_sense.cmd, - sizeof(vpo->vpo_sense.cmd), - (char *)&csio->sense_data, csio->sense_len, - &vpo->vpo_sense.stat, &vpo->vpo_sense.count, - &vpo->vpo_error); - } - - -#ifdef VP0_DEBUG - printf("(sense) vpo_do_scsi = %d, status = 0x%x, count = %d, vpo_error = %d\n", - errno, vpo->vpo_sense.stat, vpo->vpo_sense.count, vpo->vpo_error); -#endif - - /* check sense return status */ - if (errno == 0 && vpo->vpo_sense.stat == SCSI_STATUS_OK) { - /* sense ok */ - csio->ccb_h.status = CAM_AUTOSNS_VALID | CAM_SCSI_STATUS_ERROR; - csio->sense_resid = csio->sense_len - vpo->vpo_sense.count; - -#ifdef VP0_DEBUG - /* dump of sense info */ - printf("(sense) "); - for (i=0; ivpo_sense.count; i++) - printf("%x ", ((char *)&csio->sense_data)[i]); - printf("\n"); -#endif - - } else { - /* sense failed */ - csio->ccb_h.status = CAM_AUTOSENSE_FAIL; - } - } else { - /* no sense */ - csio->ccb_h.status = CAM_SCSI_STATUS_ERROR; - } - - return; - } - - csio->resid = csio->dxfer_len - vpo->vpo_count; - csio->ccb_h.status = CAM_REQ_CMP; -} - -static void -vpo_action(struct cam_sim *sim, union ccb *ccb) -{ - struct vpo_data *vpo = (struct vpo_data *)sim->softc; - - ppb_assert_locked(device_get_parent(vpo->vpo_dev)); - switch (ccb->ccb_h.func_code) { - case XPT_SCSI_IO: - { - struct ccb_scsiio *csio; - - csio = &ccb->csio; - - if (ccb->ccb_h.flags & CAM_CDB_PHYS) { - ccb->ccb_h.status = CAM_REQ_INVALID; - xpt_done(ccb); - break; - } -#ifdef VP0_DEBUG - device_printf(vpo->vpo_dev, "XPT_SCSI_IO (0x%x) request\n", - *scsiio_cdb_ptr(csio)); -#endif - vpo_intr(vpo, csio); - - xpt_done(ccb); - - break; - } - case XPT_CALC_GEOMETRY: - { - struct ccb_calc_geometry *ccg; - - ccg = &ccb->ccg; - -#ifdef VP0_DEBUG - device_printf(vpo->vpo_dev, "XPT_CALC_GEOMETRY (bs=%d,vs=%jd,c=%d,h=%d,spt=%d) request\n", - ccg->block_size, - (intmax_t)ccg->volume_size, - ccg->cylinders, - ccg->heads, - ccg->secs_per_track); -#endif - - ccg->heads = 64; - ccg->secs_per_track = 32; - ccg->cylinders = ccg->volume_size / - (ccg->heads * ccg->secs_per_track); - - ccb->ccb_h.status = CAM_REQ_CMP; - xpt_done(ccb); - break; - } - case XPT_RESET_BUS: /* Reset the specified SCSI bus */ - { - -#ifdef VP0_DEBUG - device_printf(vpo->vpo_dev, "XPT_RESET_BUS request\n"); -#endif - - if (vpo->vpo_isplus) { - if (imm_reset_bus(&vpo->vpo_io)) { - ccb->ccb_h.status = CAM_REQ_CMP_ERR; - xpt_done(ccb); - return; - } - } else { - if (vpoio_reset_bus(&vpo->vpo_io)) { - ccb->ccb_h.status = CAM_REQ_CMP_ERR; - xpt_done(ccb); - return; - } - } - - ccb->ccb_h.status = CAM_REQ_CMP; - xpt_done(ccb); - break; - } - case XPT_PATH_INQ: /* Path routing inquiry */ - { - struct ccb_pathinq *cpi = &ccb->cpi; - -#ifdef VP0_DEBUG - device_printf(vpo->vpo_dev, "XPT_PATH_INQ request\n"); -#endif - cpi->version_num = 1; /* XXX??? */ - cpi->hba_inquiry = 0; - cpi->target_sprt = 0; - cpi->hba_misc = 0; - cpi->hba_eng_cnt = 0; - cpi->max_target = 7; - cpi->max_lun = 0; - cpi->initiator_id = VP0_INITIATOR; - cpi->bus_id = sim->bus_id; - cpi->base_transfer_speed = 93; - strlcpy(cpi->sim_vid, "MidnightBSD", SIM_IDLEN); - strlcpy(cpi->hba_vid, "Iomega", HBA_IDLEN); - strlcpy(cpi->dev_name, sim->sim_name, DEV_IDLEN); - cpi->unit_number = sim->unit_number; - cpi->transport = XPORT_PPB; - cpi->transport_version = 0; - - cpi->ccb_h.status = CAM_REQ_CMP; - xpt_done(ccb); - break; - } - default: - ccb->ccb_h.status = CAM_REQ_INVALID; - xpt_done(ccb); - break; - } - - return; -} - -static void -vpo_poll(struct cam_sim *sim) -{ - - /* The ZIP is actually always polled throw vpo_action(). */ -} - -static devclass_t vpo_devclass; - -static device_method_t vpo_methods[] = { - /* device interface */ - DEVMETHOD(device_identify, vpo_identify), - DEVMETHOD(device_probe, vpo_probe), - DEVMETHOD(device_attach, vpo_attach), - - { 0, 0 } -}; - -static driver_t vpo_driver = { - "vpo", - vpo_methods, - sizeof(struct vpo_data), -}; -DRIVER_MODULE(vpo, ppbus, vpo_driver, vpo_devclass, 0, 0); -MODULE_DEPEND(vpo, ppbus, 1, 1, 1); -MODULE_DEPEND(vpo, cam, 1, 1, 1); diff --git a/sys/dev/ppbus/vpoio.c b/sys/dev/ppbus/vpoio.c deleted file mode 100644 index 19fa6d212a3..00000000000 --- a/sys/dev/ppbus/vpoio.c +++ /dev/null @@ -1,788 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 1998, 1999 Nicolas Souchu - * Copyright (c) 2000 Alcove - Nicolas Souchu - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * - */ - -#include - -#ifdef _KERNEL -#include -#include -#include -#include -#include - - -#endif - -#include "opt_vpo.h" - -#include -#include -#include -#include - -#include "ppbus_if.h" - -/* - * The driver pools the drive. We may add a timeout queue to avoid - * active polling on nACK. I've tried this but it leads to unreliable - * transfers - */ -#define VP0_SELTMO 5000 /* select timeout */ -#define VP0_FAST_SPINTMO 500000 /* wait status timeout */ -#define VP0_LOW_SPINTMO 5000000 /* wait status timeout */ - -/* - * Actually, VP0 timings are more accurate (about few 16MHZ cycles), - * but succeeding in respecting such timings leads to architecture - * dependent considerations. - */ -#define VP0_PULSE 1 - -#define VP0_SECTOR_SIZE 512 -#define VP0_BUFFER_SIZE 0x12000 - -#define n(flags) (~(flags) & (flags)) - -/* - * VP0 connections. - */ -#define H_AUTO n(AUTOFEED) -#define H_nAUTO AUTOFEED -#define H_STROBE n(STROBE) -#define H_nSTROBE STROBE -#define H_BSY n(nBUSY) -#define H_nBSY nBUSY -#define H_SEL SELECT -#define H_nSEL n(SELECT) -#define H_ERR PERROR -#define H_nERR n(PERROR) -#define H_ACK nACK -#define H_nACK n(nACK) -#define H_FLT nFAULT -#define H_nFLT n(nFAULT) -#define H_SELIN n(SELECTIN) -#define H_nSELIN SELECTIN -#define H_INIT nINIT -#define H_nINIT n(nINIT) - -/* - * Microcode to execute very fast I/O sequences at the lowest bus level. - */ - -#define WAIT_RET MS_PARAM(4, 2, MS_TYP_PTR) -#define WAIT_TMO MS_PARAM(0, 0, MS_TYP_INT) - -#define DECLARE_WAIT_MICROSEQUENCE \ -struct ppb_microseq wait_microseq[] = { \ - MS_SET(MS_UNKNOWN), \ - /* loop */ \ - MS_BRSET(nBUSY, 2 /* ready */), \ - MS_DBRA(-2 /* loop */), \ - MS_RET(1), /* timed out */ \ - /* ready */ \ - MS_RFETCH(MS_REG_STR, 0xf0, MS_UNKNOWN), \ - MS_RET(0) /* no error */ \ -} - -/* call this macro to initialize connect/disconnect microsequences */ -#define INIT_TRIG_MICROSEQ { \ - int i; \ - for (i=1; i <= 7; i+=2) { \ - disconnect_microseq[i].arg[2] = (union ppb_insarg)d_pulse; \ - connect_epp_microseq[i].arg[2] = \ - connect_spp_microseq[i].arg[2] = (union ppb_insarg)c_pulse; \ - } \ -} - -#define trig_d_pulse MS_TRIG(MS_REG_CTR,5,MS_UNKNOWN /* d_pulse */) -static char d_pulse[] = { - H_AUTO | H_nSELIN | H_INIT | H_STROBE, 0, - H_nAUTO | H_nSELIN | H_INIT | H_STROBE, VP0_PULSE, - H_AUTO | H_nSELIN | H_INIT | H_STROBE, 0, - H_AUTO | H_SELIN | H_INIT | H_STROBE, VP0_PULSE, - H_AUTO | H_nSELIN | H_INIT | H_STROBE, VP0_PULSE -}; - -#define trig_c_pulse MS_TRIG(MS_REG_CTR,5,MS_UNKNOWN /* c_pulse */) -static char c_pulse[] = { - H_AUTO | H_nSELIN | H_INIT | H_STROBE, 0, - H_AUTO | H_SELIN | H_INIT | H_STROBE, 0, - H_nAUTO | H_SELIN | H_INIT | H_STROBE, VP0_PULSE, - H_AUTO | H_SELIN | H_INIT | H_STROBE, 0, - H_AUTO | H_nSELIN | H_INIT | H_STROBE, VP0_PULSE -}; - -static struct ppb_microseq disconnect_microseq[] = { - MS_DASS(0x0), trig_d_pulse, MS_DASS(0x3c), trig_d_pulse, - MS_DASS(0x20), trig_d_pulse, MS_DASS(0xf), trig_d_pulse, MS_RET(0) -}; - -static struct ppb_microseq connect_epp_microseq[] = { - MS_DASS(0x0), trig_c_pulse, MS_DASS(0x3c), trig_c_pulse, - MS_DASS(0x20), trig_c_pulse, MS_DASS(0xcf), trig_c_pulse, MS_RET(0) -}; - -static struct ppb_microseq connect_spp_microseq[] = { - MS_DASS(0x0), trig_c_pulse, MS_DASS(0x3c), trig_c_pulse, - MS_DASS(0x20), trig_c_pulse, MS_DASS(0x8f), trig_c_pulse, MS_RET(0) -}; - -/* - * nibble_inbyte_hook() - * - * Formats high and low nibble into a character - */ -static int -nibble_inbyte_hook (void *p, char *ptr) -{ - struct vpo_nibble *s = (struct vpo_nibble *)p; - - /* increment the buffer pointer */ - *ptr++ = ((s->l >> 4) & 0x0f) + (s->h & 0xf0); - - return (0); -} - -#define INB_NIBBLE_H MS_PARAM(2, 2, MS_TYP_PTR) -#define INB_NIBBLE_L MS_PARAM(4, 2, MS_TYP_PTR) -#define INB_NIBBLE_F MS_PARAM(5, 0, MS_TYP_FUN) -#define INB_NIBBLE_P MS_PARAM(5, 1, MS_TYP_PTR) - -/* - * This is the sub-microseqence for MS_GET in NIBBLE mode - * Retrieve the two nibbles and call the C function to generate the character - * and store it in the buffer (see nibble_inbyte_hook()) - */ - -#define DECLARE_NIBBLE_INBYTE_SUBMICROSEQ \ -struct ppb_microseq nibble_inbyte_submicroseq[] = { \ -/* loop: */ \ - MS_CASS( H_AUTO | H_SELIN | H_INIT | H_STROBE), \ - MS_DELAY(VP0_PULSE), \ - MS_RFETCH(MS_REG_STR, MS_FETCH_ALL, MS_UNKNOWN /* high nibble */),\ - MS_CASS(H_nAUTO | H_SELIN | H_INIT | H_STROBE), \ - MS_RFETCH(MS_REG_STR, MS_FETCH_ALL, MS_UNKNOWN /* low nibble */),\ - /* do a C call to format the received nibbles */ \ - MS_C_CALL(MS_UNKNOWN /* C hook */, MS_UNKNOWN /* param */),\ - MS_DBRA(-7 /* loop */), \ - MS_CASS(H_AUTO | H_nSELIN | H_INIT | H_STROBE), \ - MS_RET(0) \ -} - -/* - * This is the sub-microseqence for MS_GET in PS2 mode - */ -static struct ppb_microseq ps2_inbyte_submicroseq[] = { - MS_CASS(PCD | H_AUTO | H_SELIN | H_INIT | H_nSTROBE), - -/* loop: */ - MS_RFETCH_P(1, MS_REG_DTR, MS_FETCH_ALL), - MS_CASS(PCD | H_nAUTO | H_SELIN | H_INIT | H_nSTROBE), - MS_CASS(PCD | H_AUTO | H_SELIN | H_INIT | H_nSTROBE), - MS_DBRA(-4 /* loop */), - - MS_CASS(H_AUTO | H_nSELIN | H_INIT | H_STROBE), - MS_RET(0) -}; - -/* - * This is the sub-microsequence for MS_PUT in both NIBBLE and PS2 modes - */ -static struct ppb_microseq spp_outbyte_submicroseq[] = { - -/* loop: */ - MS_RASSERT_P(1, MS_REG_DTR), - MS_CASS(H_nAUTO | H_nSELIN | H_INIT | H_STROBE), - MS_CASS( H_AUTO | H_nSELIN | H_INIT | H_STROBE), - MS_DELAY(VP0_PULSE), - MS_DBRA(-5 /* loop */), - - /* return from the put call */ - MS_RET(0) -}; - -/* EPP 1.7 microsequences, ptr and len set at runtime */ -static struct ppb_microseq epp17_outstr_body[] = { - MS_CASS(H_AUTO | H_SELIN | H_INIT | H_STROBE), - -/* loop: */ - MS_RASSERT_P(1, MS_REG_EPP_D), - MS_BRSET(TIMEOUT, 3 /* error */), /* EPP timeout? */ - MS_DBRA(-3 /* loop */), - - MS_CASS(H_AUTO | H_nSELIN | H_INIT | H_STROBE), - MS_RET(0), -/* error: */ - MS_CASS(H_AUTO | H_nSELIN | H_INIT | H_STROBE), - MS_RET(1) -}; - -static struct ppb_microseq epp17_instr_body[] = { - MS_CASS(PCD | H_AUTO | H_SELIN | H_INIT | H_STROBE), - -/* loop: */ - MS_RFETCH_P(1, MS_REG_EPP_D, MS_FETCH_ALL), - MS_BRSET(TIMEOUT, 3 /* error */), /* EPP timeout? */ - MS_DBRA(-3 /* loop */), - - MS_CASS(PCD | H_AUTO | H_nSELIN | H_INIT | H_STROBE), - MS_RET(0), -/* error: */ - MS_CASS(PCD | H_AUTO | H_nSELIN | H_INIT | H_STROBE), - MS_RET(1) -}; - -static struct ppb_microseq in_disk_mode[] = { - MS_CASS( H_AUTO | H_nSELIN | H_INIT | H_STROBE), - MS_CASS(H_nAUTO | H_nSELIN | H_INIT | H_STROBE), - - MS_BRCLEAR(H_FLT, 3 /* error */), - MS_CASS( H_AUTO | H_nSELIN | H_INIT | H_STROBE), - MS_BRSET(H_FLT, 1 /* error */), - - MS_RET(1), -/* error: */ - MS_RET(0) -}; - -static int -vpoio_disconnect(struct vpoio_data *vpo) -{ - device_t ppbus = device_get_parent(vpo->vpo_dev); - int ret; - - ppb_MS_microseq(ppbus, vpo->vpo_dev, disconnect_microseq, &ret); - return (ppb_release_bus(ppbus, vpo->vpo_dev)); -} - -/* - * how : PPB_WAIT or PPB_DONTWAIT - */ -static int -vpoio_connect(struct vpoio_data *vpo, int how) -{ - device_t ppbus = device_get_parent(vpo->vpo_dev); - int error; - int ret; - - if ((error = ppb_request_bus(ppbus, vpo->vpo_dev, how))) { - -#ifdef VP0_DEBUG - printf("%s: can't request bus!\n", __func__); -#endif - return (error); - } - - if (PPB_IN_EPP_MODE(ppbus)) - ppb_MS_microseq(ppbus, vpo->vpo_dev, connect_epp_microseq, &ret); - else - ppb_MS_microseq(ppbus, vpo->vpo_dev, connect_spp_microseq, &ret); - - return (0); -} - -/* - * vpoio_reset() - * - * SCSI reset signal, the drive must be in disk mode - */ -static void -vpoio_reset(struct vpoio_data *vpo) -{ - device_t ppbus = device_get_parent(vpo->vpo_dev); - int ret; - - struct ppb_microseq reset_microseq[] = { - - #define INITIATOR MS_PARAM(0, 1, MS_TYP_INT) - - MS_DASS(MS_UNKNOWN), - MS_CASS(H_AUTO | H_nSELIN | H_nINIT | H_STROBE), - MS_DELAY(25), - MS_CASS(H_AUTO | H_nSELIN | H_INIT | H_STROBE), - MS_RET(0) - }; - - ppb_MS_init_msq(reset_microseq, 1, INITIATOR, 1 << VP0_INITIATOR); - ppb_MS_microseq(ppbus, vpo->vpo_dev, reset_microseq, &ret); - - return; -} - -/* - * vpoio_in_disk_mode() - */ -static int -vpoio_in_disk_mode(struct vpoio_data *vpo) -{ - device_t ppbus = device_get_parent(vpo->vpo_dev); - int ret; - - ppb_MS_microseq(ppbus, vpo->vpo_dev, in_disk_mode, &ret); - - return (ret); -} - -/* - * vpoio_detect() - * - * Detect and initialise the VP0 adapter. - */ -static int -vpoio_detect(struct vpoio_data *vpo) -{ - device_t ppbus = device_get_parent(vpo->vpo_dev); - int error, ret; - - /* allocate the bus, then apply microsequences */ - if ((error = ppb_request_bus(ppbus, vpo->vpo_dev, PPB_DONTWAIT))) - return (error); - - /* Force disconnection */ - ppb_MS_microseq(ppbus, vpo->vpo_dev, disconnect_microseq, &ret); - - /* Try to enter EPP mode, then connect to the drive in EPP mode */ - if (ppb_set_mode(ppbus, PPB_EPP) != -1) { - /* call manually the microseq instead of using the appropriate function - * since we already requested the ppbus */ - ppb_MS_microseq(ppbus, vpo->vpo_dev, connect_epp_microseq, &ret); - } - - /* If EPP mode switch failed or ZIP connection in EPP mode failed, - * try to connect in NIBBLE mode */ - if (!vpoio_in_disk_mode(vpo)) { - - /* The interface must be at least PS/2 or NIBBLE capable. - * There is no way to know if the ZIP will work with - * PS/2 mode since PS/2 and SPP both use the same connect - * sequence. One must suppress PS/2 with boot flags if - * PS/2 mode fails (see ppc(4)). - */ - if (ppb_set_mode(ppbus, PPB_PS2) != -1) { - vpo->vpo_mode_found = VP0_MODE_PS2; - } else { - if (ppb_set_mode(ppbus, PPB_NIBBLE) == -1) - goto error; - - vpo->vpo_mode_found = VP0_MODE_NIBBLE; - } - - /* Can't know if the interface is capable of PS/2 yet */ - ppb_MS_microseq(ppbus, vpo->vpo_dev, connect_spp_microseq, &ret); - if (!vpoio_in_disk_mode(vpo)) { - vpo->vpo_mode_found = VP0_MODE_UNDEFINED; - if (bootverbose) - device_printf(vpo->vpo_dev, - "can't connect to the drive\n"); - - /* disconnect and release the bus */ - ppb_MS_microseq(ppbus, vpo->vpo_dev, disconnect_microseq, - &ret); - goto error; - } - } else { - vpo->vpo_mode_found = VP0_MODE_EPP; - } - - /* send SCSI reset signal */ - vpoio_reset(vpo); - - ppb_MS_microseq(ppbus, vpo->vpo_dev, disconnect_microseq, &ret); - - /* ensure we are disconnected or daisy chained peripheral - * may cause serious problem to the disk */ - if (vpoio_in_disk_mode(vpo)) { - if (bootverbose) - device_printf(vpo->vpo_dev, - "can't disconnect from the drive\n"); - goto error; - } - - ppb_release_bus(ppbus, vpo->vpo_dev); - return (0); - -error: - ppb_release_bus(ppbus, vpo->vpo_dev); - return (VP0_EINITFAILED); -} - -/* - * vpoio_outstr() - */ -static int -vpoio_outstr(struct vpoio_data *vpo, char *buffer, int size) -{ - device_t ppbus = device_get_parent(vpo->vpo_dev); - int error = 0; - - ppb_MS_exec(ppbus, vpo->vpo_dev, MS_OP_PUT, (union ppb_insarg)buffer, - (union ppb_insarg)size, (union ppb_insarg)MS_UNKNOWN, &error); - - ppb_ecp_sync(ppbus); - - return (error); -} - -/* - * vpoio_instr() - */ -static int -vpoio_instr(struct vpoio_data *vpo, char *buffer, int size) -{ - device_t ppbus = device_get_parent(vpo->vpo_dev); - int error = 0; - - ppb_MS_exec(ppbus, vpo->vpo_dev, MS_OP_GET, (union ppb_insarg)buffer, - (union ppb_insarg)size, (union ppb_insarg)MS_UNKNOWN, &error); - - ppb_ecp_sync(ppbus); - - return (error); -} - -static char -vpoio_select(struct vpoio_data *vpo, int initiator, int target) -{ - device_t ppbus = device_get_parent(vpo->vpo_dev); - int ret; - - struct ppb_microseq select_microseq[] = { - - /* parameter list - */ - #define SELECT_TARGET MS_PARAM(0, 1, MS_TYP_INT) - #define SELECT_INITIATOR MS_PARAM(3, 1, MS_TYP_INT) - - /* send the select command to the drive */ - MS_DASS(MS_UNKNOWN), - MS_CASS(H_nAUTO | H_nSELIN | H_INIT | H_STROBE), - MS_CASS( H_AUTO | H_nSELIN | H_INIT | H_STROBE), - MS_DASS(MS_UNKNOWN), - MS_CASS( H_AUTO | H_nSELIN | H_nINIT | H_STROBE), - - /* now, wait until the drive is ready */ - MS_SET(VP0_SELTMO), -/* loop: */ MS_BRSET(H_ACK, 2 /* ready */), - MS_DBRA(-2 /* loop */), -/* error: */ MS_RET(1), -/* ready: */ MS_RET(0) - }; - - /* initialize the select microsequence */ - ppb_MS_init_msq(select_microseq, 2, - SELECT_TARGET, 1 << target, - SELECT_INITIATOR, 1 << initiator); - - ppb_MS_microseq(ppbus, vpo->vpo_dev, select_microseq, &ret); - - if (ret) - return (VP0_ESELECT_TIMEOUT); - - return (0); -} - -/* - * vpoio_wait() - * - * H_SELIN must be low. - * - * XXX should be ported to microseq - */ -static char -vpoio_wait(struct vpoio_data *vpo, int tmo) -{ - DECLARE_WAIT_MICROSEQUENCE; - - device_t ppbus = device_get_parent(vpo->vpo_dev); - int ret, err; - -#if 0 /* broken */ - if (ppb_poll_device(ppbus, 150, nBUSY, nBUSY, PPB_INTR)) - return (0); - - return (ppb_rstr(ppbus) & 0xf0); -#endif - - /* - * Return some status information. - * Semantics : 0xc0 = ZIP wants more data - * 0xd0 = ZIP wants to send more data - * 0xe0 = ZIP wants command - * 0xf0 = end of transfer, ZIP is sending status - */ - - ppb_MS_init_msq(wait_microseq, 2, - WAIT_RET, (void *)&ret, - WAIT_TMO, tmo); - - ppb_MS_microseq(ppbus, vpo->vpo_dev, wait_microseq, &err); - - if (err) - return (0); /* command timed out */ - - return(ret); -} - -/* - * vpoio_probe() - * - * Low level probe of vpo device - * - */ -int -vpoio_probe(device_t dev, struct vpoio_data *vpo) -{ - int error; - - /* ppbus dependent initialisation */ - vpo->vpo_dev = dev; - - /* - * Initialize microsequence code - */ - INIT_TRIG_MICROSEQ; - - /* now, try to initialise the drive */ - if ((error = vpoio_detect(vpo))) { - return (error); - } - - return (0); -} - -/* - * vpoio_attach() - * - * Low level attachment of vpo device - * - */ -int -vpoio_attach(struct vpoio_data *vpo) -{ - DECLARE_NIBBLE_INBYTE_SUBMICROSEQ; - device_t ppbus = device_get_parent(vpo->vpo_dev); - int error = 0; - - vpo->vpo_nibble_inbyte_msq = (struct ppb_microseq *)malloc( - sizeof(nibble_inbyte_submicroseq), M_DEVBUF, M_NOWAIT); - - if (!vpo->vpo_nibble_inbyte_msq) - return (ENXIO); - - bcopy((void *)nibble_inbyte_submicroseq, - (void *)vpo->vpo_nibble_inbyte_msq, - sizeof(nibble_inbyte_submicroseq)); - - ppb_MS_init_msq(vpo->vpo_nibble_inbyte_msq, 4, - INB_NIBBLE_H, (void *)&(vpo)->vpo_nibble.h, - INB_NIBBLE_L, (void *)&(vpo)->vpo_nibble.l, - INB_NIBBLE_F, nibble_inbyte_hook, - INB_NIBBLE_P, (void *)&(vpo)->vpo_nibble); - - /* - * Initialize mode dependent in/out microsequences - */ - ppb_lock(ppbus); - if ((error = ppb_request_bus(ppbus, vpo->vpo_dev, PPB_WAIT))) - goto error; - - /* ppbus sets automatically the last mode entered during detection */ - switch (vpo->vpo_mode_found) { - case VP0_MODE_EPP: - ppb_MS_GET_init(ppbus, vpo->vpo_dev, epp17_instr_body); - ppb_MS_PUT_init(ppbus, vpo->vpo_dev, epp17_outstr_body); - device_printf(vpo->vpo_dev, "EPP mode\n"); - break; - case VP0_MODE_PS2: - ppb_MS_GET_init(ppbus, vpo->vpo_dev, ps2_inbyte_submicroseq); - ppb_MS_PUT_init(ppbus, vpo->vpo_dev, spp_outbyte_submicroseq); - device_printf(vpo->vpo_dev, "PS2 mode\n"); - break; - case VP0_MODE_NIBBLE: - ppb_MS_GET_init(ppbus, vpo->vpo_dev, vpo->vpo_nibble_inbyte_msq); - ppb_MS_PUT_init(ppbus, vpo->vpo_dev, spp_outbyte_submicroseq); - device_printf(vpo->vpo_dev, "NIBBLE mode\n"); - break; - default: - panic("vpo: unknown mode %d", vpo->vpo_mode_found); - } - - ppb_release_bus(ppbus, vpo->vpo_dev); - -error: - ppb_unlock(ppbus); - return (error); -} - -/* - * vpoio_reset_bus() - * - */ -int -vpoio_reset_bus(struct vpoio_data *vpo) -{ - /* first, connect to the drive */ - if (vpoio_connect(vpo, PPB_WAIT|PPB_INTR) || !vpoio_in_disk_mode(vpo)) { - -#ifdef VP0_DEBUG - printf("%s: not in disk mode!\n", __func__); -#endif - /* release ppbus */ - vpoio_disconnect(vpo); - return (1); - } - - /* reset the SCSI bus */ - vpoio_reset(vpo); - - /* then disconnect */ - vpoio_disconnect(vpo); - - return (0); -} - -/* - * vpoio_do_scsi() - * - * Send an SCSI command - * - */ -int -vpoio_do_scsi(struct vpoio_data *vpo, int host, int target, char *command, - int clen, char *buffer, int blen, int *result, int *count, - int *ret) -{ - device_t ppbus = device_get_parent(vpo->vpo_dev); - char r; - char l, h = 0; - int len, error = 0; - int k; - - /* - * enter disk state, allocate the ppbus - * - * XXX - * Should we allow this call to be interruptible? - * The only way to report the interruption is to return - * EIO do upper SCSI code :^( - */ - if ((error = vpoio_connect(vpo, PPB_WAIT|PPB_INTR))) - return (error); - - if (!vpoio_in_disk_mode(vpo)) { - *ret = VP0_ECONNECT; - goto error; - } - - if ((*ret = vpoio_select(vpo,host,target))) - goto error; - - /* - * Send the command ... - * - * set H_SELIN low for vpoio_wait(). - */ - ppb_wctr(ppbus, H_AUTO | H_nSELIN | H_INIT | H_STROBE); - - for (k = 0; k < clen; k++) { - if (vpoio_wait(vpo, VP0_FAST_SPINTMO) != (char)0xe0) { - *ret = VP0_ECMD_TIMEOUT; - goto error; - } - if (vpoio_outstr(vpo, &command[k], 1)) { - *ret = VP0_EPPDATA_TIMEOUT; - goto error; - } - } - - /* - * Completion ... - */ - - *count = 0; - for (;;) { - - if (!(r = vpoio_wait(vpo, VP0_LOW_SPINTMO))) { - *ret = VP0_ESTATUS_TIMEOUT; - goto error; - } - - /* stop when the ZIP wants to send status */ - if (r == (char)0xf0) - break; - - if (*count >= blen) { - *ret = VP0_EDATA_OVERFLOW; - goto error; - } - - /* if in EPP mode or writing bytes, try to transfer a sector - * otherwise, just send one byte - */ - if (PPB_IN_EPP_MODE(ppbus) || r == (char)0xc0) - len = (((blen - *count) >= VP0_SECTOR_SIZE)) ? - VP0_SECTOR_SIZE : 1; - else - len = 1; - - /* ZIP wants to send data? */ - if (r == (char)0xc0) - error = vpoio_outstr(vpo, &buffer[*count], len); - else - error = vpoio_instr(vpo, &buffer[*count], len); - - if (error) { - *ret = error; - goto error; - } - - *count += len; - } - - if (vpoio_instr(vpo, &l, 1)) { - *ret = VP0_EOTHER; - goto error; - } - - /* check if the ZIP wants to send more status */ - if (vpoio_wait(vpo, VP0_FAST_SPINTMO) == (char)0xf0) - if (vpoio_instr(vpo, &h, 1)) { - *ret = VP0_EOTHER + 2; - goto error; - } - - *result = ((int) h << 8) | ((int) l & 0xff); - -error: - /* return to printer state, release the ppbus */ - vpoio_disconnect(vpo); - return (0); -} diff --git a/sys/dev/ppbus/vpoio.h b/sys/dev/ppbus/vpoio.h deleted file mode 100644 index da265c89d72..00000000000 --- a/sys/dev/ppbus/vpoio.h +++ /dev/null @@ -1,98 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 1998 Nicolas Souchu - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * - */ -#ifndef __VP0IO_H -#define __VP0IO_H - -/* - * The ZIP drive cannot act as an initiator. - */ -#define VP0_INITIATOR 0x7 - -#define VP0_ESELECT_TIMEOUT 1 -#define VP0_ECMD_TIMEOUT 2 -#define VP0_ECONNECT 3 -#define VP0_ESTATUS_TIMEOUT 4 -#define VP0_EDATA_OVERFLOW 5 -#define VP0_EDISCONNECT 6 -#define VP0_EPPDATA_TIMEOUT 7 -#define VP0_ENEGOCIATE 8 -#define VP0_ENOPORT 9 -#define VP0_EINITFAILED 10 -#define VP0_EINTR 12 - -#define VP0_EOTHER 13 - -#define VP0_OPENNINGS 1 - -/* - * Data structure used during microsequence execution - * when characters are received in nibble mode - */ -struct vpo_nibble { - char h; /* most significant nibble */ - char l; /* less significant nibble */ -}; - -/* Mode found during initialisation */ -#define VP0_MODE_UNDEFINED 0x0 -#define VP0_MODE_NIBBLE 0x1 -#define VP0_MODE_PS2 0x2 -#define VP0_MODE_EPP 0x3 - -struct vpoio_data { - int vpo_mode_found; /* Mode found during init */ - - struct vpo_nibble vpo_nibble; - - /* each device must have its own nibble inbyte microsequence */ - struct ppb_microseq *vpo_nibble_inbyte_msq; - - device_t vpo_dev; -}; - -int vpoio_probe(device_t dev, struct vpoio_data *vpo); - -int vpoio_attach(struct vpoio_data *vpo); -int vpoio_reset_bus(struct vpoio_data *vpo); - -int vpoio_do_scsi(struct vpoio_data *vpo, int host, int target, char *command, - int clen, char *buffer, int blen, int *result, int *count, - int *ret); - -int imm_probe(device_t dev, struct vpoio_data *vpo); - -int imm_attach(struct vpoio_data *vpo); -int imm_reset_bus(struct vpoio_data *vpo); - -int imm_do_scsi(struct vpoio_data *vpo, int host, int target, char *command, - int clen, char *buffer, int blen, int *result, int *count, - int *ret); - -#endif diff --git a/sys/dev/psci/psci_arm.S b/sys/dev/psci/psci_arm.S deleted file mode 100644 index 7a7666db85f..00000000000 --- a/sys/dev/psci/psci_arm.S +++ /dev/null @@ -1,47 +0,0 @@ -/*- - * Copyright (c) 2015 Andrew Turner - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - */ - -#include - -.arch_extension sec /* For smc */ -.arch_extension virt /* For hvc */ - -/* - * int psci_hvc_despatch(register_t psci_fnid, register_t...) - */ -ENTRY(psci_hvc_despatch) - hvc #0 - RET -END(psci_hvc_despatch) - -/* - * int psci_smc_despatch(register_t psci_fnid, register_t...) - */ -ENTRY(psci_smc_despatch) - smc #0 - RET -END(psci_smc_despatch) diff --git a/sys/dev/psci/psci_arm64.S b/sys/dev/psci/psci_arm64.S deleted file mode 100644 index 005c047019b..00000000000 --- a/sys/dev/psci/psci_arm64.S +++ /dev/null @@ -1,48 +0,0 @@ -/*- - * Copyright (c) 2013, 2014 Robin Randhawa - * Copyright (c) 2015 The FreeBSD Foundation - * All rights reserved. - * - * This software was developed by Andrew Turner under - * sponsorship from the FreeBSD Foundation. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - */ - -#include - -/* - * uint64_t psci_hvc_despatch(uint64_t psci_fnid, uint64_t, uint64_t, uint64_t) - */ -ENTRY(psci_hvc_despatch) - hvc #0 - ret -END(psci_hvc_despatch) - -/* - * uint64_t psci_smc_despatch(uint64_t psci_fnid, uint64_t, uint64_t, uint64_t) - */ -ENTRY(psci_smc_despatch) - smc #0 - ret -END(psci_smc_despatch) diff --git a/sys/dev/puc/puc_pccard.c b/sys/dev/puc/puc_pccard.c deleted file mode 100644 index a1c45df999a..00000000000 --- a/sys/dev/puc/puc_pccard.c +++ /dev/null @@ -1,111 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2002 Poul-Henning Kamp. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice unmodified, this list of conditions, and the following - * disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include - -#include -#include - -/* http://www.argosy.com.tw/product/sp320.htm */ -const struct puc_cfg puc_pccard_rscom = { - 0, 0, 0, 0, - "ARGOSY SP320 Dual port serial PCMCIA", - DEFAULT_RCLK, - PUC_PORT_2S, 0, 1, 0, -}; - -static int -puc_pccard_probe(device_t dev) -{ - const char *vendor, *product; - int error; - - error = pccard_get_vendor_str(dev, &vendor); - if (error) - return(error); - error = pccard_get_product_str(dev, &product); - if (error) - return(error); - if (!strcmp(vendor, "PCMCIA") && !strcmp(product, "RS-COM 2P")) - return (puc_bfe_probe(dev, &puc_pccard_rscom)); - - return (ENXIO); -} - -static int -puc_pccard_attach(device_t dev) -{ - int error; - - error = puc_bfe_attach(dev); - if (error == 0) - gone_in_dev(dev, 13, "pccard removed"); - return (error); -} - -static device_method_t puc_pccard_methods[] = { - /* Device interface */ - DEVMETHOD(device_probe, puc_pccard_probe), - DEVMETHOD(device_attach, puc_pccard_attach), - DEVMETHOD(device_detach, puc_bfe_detach), - - DEVMETHOD(bus_alloc_resource, puc_bus_alloc_resource), - DEVMETHOD(bus_release_resource, puc_bus_release_resource), - DEVMETHOD(bus_get_resource, puc_bus_get_resource), - DEVMETHOD(bus_read_ivar, puc_bus_read_ivar), - DEVMETHOD(bus_setup_intr, puc_bus_setup_intr), - DEVMETHOD(bus_teardown_intr, puc_bus_teardown_intr), - DEVMETHOD(bus_print_child, puc_bus_print_child), - DEVMETHOD(bus_child_pnpinfo_str, puc_bus_child_pnpinfo_str), - DEVMETHOD(bus_child_location_str, puc_bus_child_location_str), - - DEVMETHOD_END -}; - -static driver_t puc_pccard_driver = { - puc_driver_name, - puc_pccard_methods, - sizeof(struct puc_softc), -}; - -DRIVER_MODULE(puc, pccard, puc_pccard_driver, puc_devclass, 0, 0); diff --git a/sys/dev/scc/scc_bfe_ebus.c b/sys/dev/scc/scc_bfe_ebus.c deleted file mode 100644 index 13ed52aa707..00000000000 --- a/sys/dev/scc/scc_bfe_ebus.c +++ /dev/null @@ -1,98 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2004-2006 Marcel Moolenaar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include - -#include -#include -#include -#include -#include -#include - -#include - -#include -#include -#include - -#include - -#define EBUS_REGSHFT 0 -#define EBUS_RCLK 29491200 - -static int -scc_ebus_probe(device_t dev) -{ - struct scc_softc *sc; - const char *cmpt, *nm; - - sc = device_get_softc(dev); - nm = ofw_bus_get_name(dev); - cmpt = ofw_bus_get_compat(dev); - if (cmpt == NULL) - cmpt = ""; - if (!strcmp(nm, "se") || !strcmp(nm, "FJSV,se") || - !strcmp(cmpt, "sab82532")) { - device_set_desc(dev, "Siemens SAB 82532 dual channel SCC"); - sc->sc_class = &scc_sab82532_class; - return (scc_bfe_probe(dev, EBUS_REGSHFT, EBUS_RCLK, 0)); - } - return (ENXIO); -} - -static int -scc_ebus_attach(device_t dev) -{ - - return (scc_bfe_attach(dev, 0)); -} - -static device_method_t scc_ebus_methods[] = { - /* Device interface */ - DEVMETHOD(device_probe, scc_ebus_probe), - DEVMETHOD(device_attach, scc_ebus_attach), - DEVMETHOD(device_detach, scc_bfe_detach), - - DEVMETHOD(bus_alloc_resource, scc_bus_alloc_resource), - DEVMETHOD(bus_release_resource, scc_bus_release_resource), - DEVMETHOD(bus_get_resource, scc_bus_get_resource), - DEVMETHOD(bus_read_ivar, scc_bus_read_ivar), - DEVMETHOD(bus_setup_intr, scc_bus_setup_intr), - DEVMETHOD(bus_teardown_intr, scc_bus_teardown_intr), - - DEVMETHOD_END -}; - -static driver_t scc_ebus_driver = { - scc_driver_name, - scc_ebus_methods, - sizeof(struct scc_softc), -}; - -DRIVER_MODULE(scc, ebus, scc_ebus_driver, scc_devclass, NULL, NULL); diff --git a/sys/dev/scc/scc_bfe_sbus.c b/sys/dev/scc/scc_bfe_sbus.c deleted file mode 100644 index be767af0943..00000000000 --- a/sys/dev/scc/scc_bfe_sbus.c +++ /dev/null @@ -1,95 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2004-2006 Marcel Moolenaar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include - -#include -#include -#include -#include -#include -#include - -#include - -#include -#include -#include - -#include - -#define SBUS_REGSHFT 1 -#define SBUS_RCLK 307200 - -static int -scc_sbus_probe(device_t dev) -{ - struct scc_softc *sc; - const char *nm; - - sc = device_get_softc(dev); - nm = ofw_bus_get_name(dev); - if (!strcmp(nm, "zs")) { - device_set_desc(dev, "Zilog Z8530 dual channel SCC"); - sc->sc_class = &scc_z8530_class; - return (scc_bfe_probe(dev, SBUS_REGSHFT, SBUS_RCLK, 0)); - } - return (ENXIO); -} - -static int -scc_sbus_attach(device_t dev) -{ - - return (scc_bfe_attach(dev, 0)); -} - -static device_method_t scc_sbus_methods[] = { - /* Device interface */ - DEVMETHOD(device_probe, scc_sbus_probe), - DEVMETHOD(device_attach, scc_sbus_attach), - DEVMETHOD(device_detach, scc_bfe_detach), - - DEVMETHOD(bus_alloc_resource, scc_bus_alloc_resource), - DEVMETHOD(bus_release_resource, scc_bus_release_resource), - DEVMETHOD(bus_get_resource, scc_bus_get_resource), - DEVMETHOD(bus_read_ivar, scc_bus_read_ivar), - DEVMETHOD(bus_setup_intr, scc_bus_setup_intr), - DEVMETHOD(bus_teardown_intr, scc_bus_teardown_intr), - - DEVMETHOD_END -}; - -static driver_t scc_sbus_driver = { - scc_driver_name, - scc_sbus_methods, - sizeof(struct scc_softc), -}; - -DRIVER_MODULE(scc, fhc, scc_sbus_driver, scc_devclass, NULL, NULL); -DRIVER_MODULE(scc, sbus, scc_sbus_driver, scc_devclass, NULL, NULL); diff --git a/sys/dev/scc/scc_dev_sab82532.c b/sys/dev/scc/scc_dev_sab82532.c deleted file mode 100644 index 4e2781ede27..00000000000 --- a/sys/dev/scc/scc_dev_sab82532.c +++ /dev/null @@ -1,151 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2004-2006 Marcel Moolenaar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include - -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include - -#include "scc_if.h" - -static int sab82532_bfe_attach(struct scc_softc *, int); -static int sab82532_bfe_iclear(struct scc_softc *, struct scc_chan *); -static int sab82532_bfe_ipend(struct scc_softc *); -static int sab82532_bfe_probe(struct scc_softc *); - -static kobj_method_t sab82532_methods[] = { - KOBJMETHOD(scc_attach, sab82532_bfe_attach), - KOBJMETHOD(scc_iclear, sab82532_bfe_iclear), - KOBJMETHOD(scc_ipend, sab82532_bfe_ipend), - KOBJMETHOD(scc_probe, sab82532_bfe_probe), - KOBJMETHOD_END -}; - -struct scc_class scc_sab82532_class = { - "sab82532 class", - sab82532_methods, - sizeof(struct scc_softc), - .cl_channels = SAB_NCHAN, - .cl_class = SCC_CLASS_SAB82532, - .cl_modes = SCC_MODE_ASYNC | SCC_MODE_BISYNC | SCC_MODE_HDLC, - .cl_range = SAB_CHANLEN, -}; - -static int -sab82532_bfe_attach(struct scc_softc *sc __unused, int reset __unused) -{ - - return (0); -} - -static int -sab82532_bfe_iclear(struct scc_softc *sc, struct scc_chan *ch) -{ - struct scc_bas *bas; - int i, ofs, rbcl; - - bas = &sc->sc_bas; - ofs = (ch->ch_nr - 1) * SAB_CHANLEN; - mtx_lock_spin(&sc->sc_hwmtx); - if (ch->ch_ipend & SER_INT_RXREADY) { - if (scc_getreg(bas, ofs + SAB_STAR) & SAB_STAR_RFNE) { - rbcl = scc_getreg(bas, ofs + SAB_RBCL) & 31; - if (rbcl == 0) - rbcl = 32; - for (i = 0; i < rbcl; i += 2) { - (void)scc_getreg(bas, ofs + SAB_RFIFO); - (void)scc_getreg(bas, ofs + SAB_RFIFO + 1); - } - } - while (scc_getreg(bas, ofs + SAB_STAR) & SAB_STAR_CEC) - ; - scc_setreg(bas, ofs + SAB_CMDR, SAB_CMDR_RMC); - scc_barrier(bas); - } - mtx_unlock_spin(&sc->sc_hwmtx); - return (0); -} - -static int -sab82532_bfe_ipend(struct scc_softc *sc) -{ - struct scc_bas *bas; - struct scc_chan *ch; - int ipend; - int c, ofs; - uint8_t isr0, isr1; - - bas = &sc->sc_bas; - ipend = 0; - for (c = 0; c < SAB_NCHAN; c++) { - ch = &sc->sc_chan[c]; - ofs = c * SAB_CHANLEN; - mtx_lock_spin(&sc->sc_hwmtx); - isr0 = scc_getreg(bas, ofs + SAB_ISR0); - isr1 = scc_getreg(bas, ofs + SAB_ISR1); - scc_barrier(bas); - if (isr0 & SAB_ISR0_TIME) { - while (scc_getreg(bas, ofs + SAB_STAR) & SAB_STAR_CEC) - ; - scc_setreg(bas, ofs + SAB_CMDR, SAB_CMDR_RFRD); - scc_barrier(bas); - } - mtx_unlock_spin(&sc->sc_hwmtx); - - ch->ch_ipend = 0; - if (isr1 & SAB_ISR1_BRKT) - ch->ch_ipend |= SER_INT_BREAK; - if (isr0 & SAB_ISR0_RFO) - ch->ch_ipend |= SER_INT_OVERRUN; - if (isr0 & (SAB_ISR0_TCD|SAB_ISR0_RPF)) - ch->ch_ipend |= SER_INT_RXREADY; - if ((isr0 & SAB_ISR0_CDSC) || (isr1 & SAB_ISR1_CSC)) - ch->ch_ipend |= SER_INT_SIGCHG; - if (isr1 & SAB_ISR1_ALLS) - ch->ch_ipend |= SER_INT_TXIDLE; - ipend |= ch->ch_ipend; - } - return (ipend); -} - -static int -sab82532_bfe_probe(struct scc_softc *sc __unused) -{ - - return (0); -} diff --git a/sys/dev/sound/sbus/apcdmareg.h b/sys/dev/sound/sbus/apcdmareg.h deleted file mode 100644 index 54287c836f4..00000000000 --- a/sys/dev/sound/sbus/apcdmareg.h +++ /dev/null @@ -1,115 +0,0 @@ -/* $OpenBSD: apcdmareg.h,v 1.2 2003/06/02 18:53:18 jason Exp $ */ - -/*- - * SPDX-License-Identifier: BSD-2-Clause - * - * Copyright (c) 2001 Jason L. Wright (jason@thought.net) - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -/* - * Definitions for Sun APC DMA controller. - */ - -/* APC DMA registers */ -#define APC_CSR 0x0010 /* control/status */ -#define APC_CVA 0x0020 /* capture virtual address */ -#define APC_CC 0x0024 /* capture count */ -#define APC_CNVA 0x0028 /* capture next virtual address */ -#define APC_CNC 0x002c /* capture next count */ -#define APC_PVA 0x0030 /* playback virtual address */ -#define APC_PC 0x0034 /* playback count */ -#define APC_PNVA 0x0038 /* playback next virtual address */ -#define APC_PNC 0x003c /* playback next count */ - -/* - * APC DMA Register definitions - */ -#define APC_CSR_RESET 0x00000001 /* reset */ -#define APC_CSR_CDMA_GO 0x00000004 /* capture dma go */ -#define APC_CSR_PDMA_GO 0x00000008 /* playback dma go */ -#define APC_CSR_CODEC_RESET 0x00000020 /* codec reset */ -#define APC_CSR_CPAUSE 0x00000040 /* capture dma pause */ -#define APC_CSR_PPAUSE 0x00000080 /* playback dma pause */ -#define APC_CSR_CMIE 0x00000100 /* capture pipe empty enb */ -#define APC_CSR_CMI 0x00000200 /* capture pipe empty intr */ -#define APC_CSR_CD 0x00000400 /* capture nva dirty */ -#define APC_CSR_CM 0x00000800 /* capture data lost */ -#define APC_CSR_PMIE 0x00001000 /* pb pipe empty intr enable */ -#define APC_CSR_PD 0x00002000 /* pb nva dirty */ -#define APC_CSR_PM 0x00004000 /* pb pipe empty */ -#define APC_CSR_PMI 0x00008000 /* pb pipe empty interrupt */ -#define APC_CSR_EIE 0x00010000 /* error interrupt enable */ -#define APC_CSR_CIE 0x00020000 /* capture intr enable */ -#define APC_CSR_PIE 0x00040000 /* playback intr enable */ -#define APC_CSR_GIE 0x00080000 /* general intr enable */ -#define APC_CSR_EI 0x00100000 /* error interrupt */ -#define APC_CSR_CI 0x00200000 /* capture interrupt */ -#define APC_CSR_PI 0x00400000 /* playback interrupt */ -#define APC_CSR_GI 0x00800000 /* general interrupt */ - -#define APC_CSR_PLAY ( \ - APC_CSR_EI | \ - APC_CSR_GIE | \ - APC_CSR_PIE | \ - APC_CSR_EIE | \ - APC_CSR_PDMA_GO | \ - APC_CSR_PMIE ) - -#define APC_CSR_CAPTURE ( \ - APC_CSR_EI | \ - APC_CSR_GIE | \ - APC_CSR_CIE | \ - APC_CSR_EIE | \ - APC_CSR_CDMA_GO ) - -#define APC_CSR_PLAY_PAUSE (~( \ - APC_CSR_PPAUSE | \ - APC_CSR_GI | \ - APC_CSR_PI | \ - APC_CSR_CI | \ - APC_CSR_EI | \ - APC_CSR_PMI | \ - APC_CSR_PMIE | \ - APC_CSR_CMI | \ - APC_CSR_CMIE ) ) - -#define APC_CSR_CAPTURE_PAUSE (~( \ - APC_CSR_PPAUSE | \ - APC_CSR_GI | \ - APC_CSR_PI | \ - APC_CSR_CI | \ - APC_CSR_EI | \ - APC_CSR_PMI | \ - APC_CSR_PMIE | \ - APC_CSR_CMI | \ - APC_CSR_CMIE ) ) - -#define APC_CSR_INTR_MASK ( \ - APC_CSR_GI | \ - APC_CSR_PI | \ - APC_CSR_CI | \ - APC_CSR_EI | \ - APC_CSR_PMI | \ - APC_CSR_CMI ) diff --git a/sys/dev/sound/sbus/cs4231.c b/sys/dev/sound/sbus/cs4231.c deleted file mode 100644 index d4df189773d..00000000000 --- a/sys/dev/sound/sbus/cs4231.c +++ /dev/null @@ -1,1565 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 1999 Jason L. Wright (jason@thought.net) - * Copyright (c) 2004 Pyun YongHyeon - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * Effort sponsored in part by the Defense Advanced Research Projects - * Agency (DARPA) and Air Force Research Laboratory, Air Force - * Materiel Command, USAF, under agreement number F30602-01-2-0537. - * - * from: OpenBSD: cs4231.c,v 1.21 2003/07/03 20:36:07 jason Exp - */ - -/* - * Driver for CS4231 based audio found in some sun4m systems (cs4231) - * based on ideas from the S/Linux project and the NetBSD project. - */ - -#include - -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#ifdef HAVE_KERNEL_OPTION_HEADERS -#include "opt_snd.h" -#endif - -#include -#include -#include - -#include -#include - -#include "mixer_if.h" - -/* - * The driver supports CS4231A audio chips found on Sbus/Ebus based - * UltraSPARCs. Though, CS4231A says it supports full-duplex mode, I - * doubt it due to the lack of independent sampling frequency register - * for playback/capture. - * Since I couldn't find any documentation for APCDMA programming - * information, I guessed the usage of APCDMA from that of OpenBSD's - * driver. The EBDMA information of PCIO can be obtained from - * http://solutions.sun.com/embedded/databook/web/microprocessors/pcio.html - * And CS4231A datasheet can also be obtained from - * ftp://ftp.alsa-project.org/pub/manuals/cirrus/4231a.pdf - * - * Audio capture(recording) was not tested at all and may have bugs. - * Sorry, I don't have microphone. Don't try to use full-duplex mode. - * It wouldn't work. - */ -#define CS_TIMEOUT 90000 - -#define CS4231_MIN_BUF_SZ (16*1024) -#define CS4231_DEFAULT_BUF_SZ (32*1024) -#define CS4231_MAX_BUF_SZ (64*1024) -#define CS4231_MAX_BLK_SZ (8*1024) -#define CS4231_MAX_APC_DMA_SZ (8*1024) - - -#undef CS4231_DEBUG -#ifdef CS4231_DEBUG -#define DPRINTF(x) printf x -#else -#define DPRINTF(x) -#endif -#define CS4231_AUTO_CALIBRATION - -struct cs4231_softc; - -struct cs4231_channel { - struct cs4231_softc *parent; - struct pcm_channel *channel; - struct snd_dbuf *buffer; - u_int32_t format; - u_int32_t speed; - u_int32_t nextaddr; - u_int32_t togo; - int dir; - int locked; -}; - -#define CS4231_RES_MEM_MAX 4 -#define CS4231_RES_IRQ_MAX 2 -struct cs4231_softc { - device_t sc_dev; - int sc_rid[CS4231_RES_MEM_MAX]; - struct resource *sc_res[CS4231_RES_MEM_MAX]; - bus_space_handle_t sc_regh[CS4231_RES_MEM_MAX]; - bus_space_tag_t sc_regt[CS4231_RES_MEM_MAX]; - - int sc_irqrid[CS4231_RES_IRQ_MAX]; - struct resource *sc_irqres[CS4231_RES_IRQ_MAX]; - void *sc_ih[CS4231_RES_IRQ_MAX]; - bus_dma_tag_t sc_dmat[CS4231_RES_IRQ_MAX]; - int sc_burst; - - u_int32_t sc_bufsz; - struct cs4231_channel sc_pch; - struct cs4231_channel sc_rch; - int sc_enabled; - int sc_nmres; - int sc_nires; - int sc_codecv; - int sc_chipvid; - int sc_flags; -#define CS4231_SBUS 0x01 -#define CS4231_EBUS 0x02 - - struct mtx *sc_lock; -}; - -struct mix_table { - u_int32_t reg:8; - u_int32_t bits:8; - u_int32_t mute:8; - u_int32_t shift:4; - u_int32_t neg:1; - u_int32_t avail:1; - u_int32_t recdev:1; -}; - -static int cs4231_bus_probe(device_t); -static int cs4231_sbus_attach(device_t); -static int cs4231_ebus_attach(device_t); -static int cs4231_attach_common(struct cs4231_softc *); -static int cs4231_bus_detach(device_t); -static int cs4231_bus_suspend(device_t); -static int cs4231_bus_resume(device_t); -static void cs4231_getversion(struct cs4231_softc *); -static void cs4231_free_resource(struct cs4231_softc *); -static void cs4231_ebdma_reset(struct cs4231_softc *); -static void cs4231_power_reset(struct cs4231_softc *, int); -static int cs4231_enable(struct cs4231_softc *, int); -static void cs4231_disable(struct cs4231_softc *); -static void cs4231_write(struct cs4231_softc *, u_int8_t, u_int8_t); -static u_int8_t cs4231_read(struct cs4231_softc *, u_int8_t); -static void cs4231_sbus_intr(void *); -static void cs4231_ebus_pintr(void *arg); -static void cs4231_ebus_cintr(void *arg); -static int cs4231_mixer_init(struct snd_mixer *); -static void cs4231_mixer_set_value(struct cs4231_softc *, - const struct mix_table *, u_int8_t); -static int cs4231_mixer_set(struct snd_mixer *, u_int32_t, u_int32_t, - u_int32_t); -static u_int32_t cs4231_mixer_setrecsrc(struct snd_mixer *, u_int32_t); -static void *cs4231_chan_init(kobj_t, void *, struct snd_dbuf *, - struct pcm_channel *, int); -static int cs4231_chan_setformat(kobj_t, void *, u_int32_t); -static u_int32_t cs4231_chan_setspeed(kobj_t, void *, u_int32_t); -static void cs4231_chan_fs(struct cs4231_softc *, int, u_int8_t); -static u_int32_t cs4231_chan_setblocksize(kobj_t, void *, u_int32_t); -static int cs4231_chan_trigger(kobj_t, void *, int); -static u_int32_t cs4231_chan_getptr(kobj_t, void *); -static struct pcmchan_caps * - cs4231_chan_getcaps(kobj_t, void *); -static void cs4231_trigger(struct cs4231_channel *); -static void cs4231_apcdma_trigger(struct cs4231_softc *, - struct cs4231_channel *); -static void cs4231_ebdma_trigger(struct cs4231_softc *, - struct cs4231_channel *); -static void cs4231_halt(struct cs4231_channel *); - -#define CS4231_LOCK(sc) snd_mtxlock(sc->sc_lock) -#define CS4231_UNLOCK(sc) snd_mtxunlock(sc->sc_lock) -#define CS4231_LOCK_ASSERT(sc) snd_mtxassert(sc->sc_lock) - -#define CS_WRITE(sc,r,v) \ - bus_space_write_1((sc)->sc_regt[0], (sc)->sc_regh[0], (r) << 2, (v)) -#define CS_READ(sc,r) \ - bus_space_read_1((sc)->sc_regt[0], (sc)->sc_regh[0], (r) << 2) - -#define APC_WRITE(sc,r,v) \ - bus_space_write_4(sc->sc_regt[0], sc->sc_regh[0], r, v) -#define APC_READ(sc,r) \ - bus_space_read_4(sc->sc_regt[0], sc->sc_regh[0], r) - -#define EBDMA_P_WRITE(sc,r,v) \ - bus_space_write_4((sc)->sc_regt[1], (sc)->sc_regh[1], (r), (v)) -#define EBDMA_P_READ(sc,r) \ - bus_space_read_4((sc)->sc_regt[1], (sc)->sc_regh[1], (r)) - -#define EBDMA_C_WRITE(sc,r,v) \ - bus_space_write_4((sc)->sc_regt[2], (sc)->sc_regh[2], (r), (v)) -#define EBDMA_C_READ(sc,r) \ - bus_space_read_4((sc)->sc_regt[2], (sc)->sc_regh[2], (r)) - -#define AUXIO_CODEC 0x00 -#define AUXIO_WRITE(sc,r,v) \ - bus_space_write_4((sc)->sc_regt[3], (sc)->sc_regh[3], (r), (v)) -#define AUXIO_READ(sc,r) \ - bus_space_read_4((sc)->sc_regt[3], (sc)->sc_regh[3], (r)) - -#define CODEC_WARM_RESET 0 -#define CODEC_COLD_RESET 1 - -/* SBus */ -static device_method_t cs4231_sbus_methods[] = { - DEVMETHOD(device_probe, cs4231_bus_probe), - DEVMETHOD(device_attach, cs4231_sbus_attach), - DEVMETHOD(device_detach, cs4231_bus_detach), - DEVMETHOD(device_suspend, cs4231_bus_suspend), - DEVMETHOD(device_resume, cs4231_bus_resume), - - DEVMETHOD_END -}; - -static driver_t cs4231_sbus_driver = { - "pcm", - cs4231_sbus_methods, - PCM_SOFTC_SIZE -}; - -DRIVER_MODULE(snd_audiocs, sbus, cs4231_sbus_driver, pcm_devclass, 0, 0); - -/* EBus */ -static device_method_t cs4231_ebus_methods[] = { - DEVMETHOD(device_probe, cs4231_bus_probe), - DEVMETHOD(device_attach, cs4231_ebus_attach), - DEVMETHOD(device_detach, cs4231_bus_detach), - DEVMETHOD(device_suspend, cs4231_bus_suspend), - DEVMETHOD(device_resume, cs4231_bus_resume), - - DEVMETHOD_END -}; - -static driver_t cs4231_ebus_driver = { - "pcm", - cs4231_ebus_methods, - PCM_SOFTC_SIZE -}; - -DRIVER_MODULE(snd_audiocs, ebus, cs4231_ebus_driver, pcm_devclass, 0, 0); -MODULE_DEPEND(snd_audiocs, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); -MODULE_VERSION(snd_audiocs, 1); - - -static u_int32_t cs4231_fmt[] = { - SND_FORMAT(AFMT_U8, 1, 0), - SND_FORMAT(AFMT_U8, 2, 0), - SND_FORMAT(AFMT_MU_LAW, 1, 0), - SND_FORMAT(AFMT_MU_LAW, 2, 0), - SND_FORMAT(AFMT_A_LAW, 1, 0), - SND_FORMAT(AFMT_A_LAW, 2, 0), - SND_FORMAT(AFMT_IMA_ADPCM, 1, 0), - SND_FORMAT(AFMT_IMA_ADPCM, 2, 0), - SND_FORMAT(AFMT_S16_LE, 1, 0), - SND_FORMAT(AFMT_S16_LE, 2, 0), - SND_FORMAT(AFMT_S16_BE, 1, 0), - SND_FORMAT(AFMT_S16_BE, 2, 0), - 0 -}; - -static struct pcmchan_caps cs4231_caps = {5510, 48000, cs4231_fmt, 0}; - -/* - * sound(4) channel interface - */ -static kobj_method_t cs4231_chan_methods[] = { - KOBJMETHOD(channel_init, cs4231_chan_init), - KOBJMETHOD(channel_setformat, cs4231_chan_setformat), - KOBJMETHOD(channel_setspeed, cs4231_chan_setspeed), - KOBJMETHOD(channel_setblocksize, cs4231_chan_setblocksize), - KOBJMETHOD(channel_trigger, cs4231_chan_trigger), - KOBJMETHOD(channel_getptr, cs4231_chan_getptr), - KOBJMETHOD(channel_getcaps, cs4231_chan_getcaps), - KOBJMETHOD_END -}; -CHANNEL_DECLARE(cs4231_chan); - -/* - * sound(4) mixer interface - */ -static kobj_method_t cs4231_mixer_methods[] = { - KOBJMETHOD(mixer_init, cs4231_mixer_init), - KOBJMETHOD(mixer_set, cs4231_mixer_set), - KOBJMETHOD(mixer_setrecsrc, cs4231_mixer_setrecsrc), - KOBJMETHOD_END -}; -MIXER_DECLARE(cs4231_mixer); - -static int -cs4231_bus_probe(device_t dev) -{ - const char *compat, *name; - - compat = ofw_bus_get_compat(dev); - name = ofw_bus_get_name(dev); - if (strcmp("SUNW,CS4231", name) == 0 || - (compat != NULL && strcmp("SUNW,CS4231", compat) == 0)) { - device_set_desc(dev, "Sun Audiocs"); - return (BUS_PROBE_DEFAULT); - } - return (ENXIO); -} - -static int -cs4231_sbus_attach(device_t dev) -{ - struct cs4231_softc *sc; - int burst; - - sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO); - sc->sc_dev = dev; - /* - * XXX - * No public documentation exists on programming burst size of APCDMA. - */ - burst = sbus_get_burstsz(sc->sc_dev); - if ((burst & SBUS_BURST_64)) - sc->sc_burst = 64; - else if ((burst & SBUS_BURST_32)) - sc->sc_burst = 32; - else if ((burst & SBUS_BURST_16)) - sc->sc_burst = 16; - else - sc->sc_burst = 0; - sc->sc_flags = CS4231_SBUS; - sc->sc_nmres = 1; - sc->sc_nires = 1; - return cs4231_attach_common(sc); -} - -static int -cs4231_ebus_attach(device_t dev) -{ - struct cs4231_softc *sc; - - sc = malloc(sizeof(struct cs4231_softc), M_DEVBUF, M_NOWAIT | M_ZERO); - if (sc == NULL) { - device_printf(dev, "cannot allocate softc\n"); - return (ENOMEM); - } - sc->sc_dev = dev; - sc->sc_burst = EBDCSR_BURST_1; - sc->sc_nmres = CS4231_RES_MEM_MAX; - sc->sc_nires = CS4231_RES_IRQ_MAX; - sc->sc_flags = CS4231_EBUS; - return cs4231_attach_common(sc); -} - -static int -cs4231_attach_common(struct cs4231_softc *sc) -{ - char status[SND_STATUSLEN]; - driver_intr_t *ihandler; - int i; - - sc->sc_lock = snd_mtxcreate(device_get_nameunit(sc->sc_dev), - "snd_cs4231 softc"); - - for (i = 0; i < sc->sc_nmres; i++) { - sc->sc_rid[i] = i; - if ((sc->sc_res[i] = bus_alloc_resource_any(sc->sc_dev, - SYS_RES_MEMORY, &sc->sc_rid[i], RF_ACTIVE)) == NULL) { - device_printf(sc->sc_dev, - "cannot map register %d\n", i); - goto fail; - } - sc->sc_regt[i] = rman_get_bustag(sc->sc_res[i]); - sc->sc_regh[i] = rman_get_bushandle(sc->sc_res[i]); - } - for (i = 0; i < sc->sc_nires; i++) { - sc->sc_irqrid[i] = i; - if ((sc->sc_irqres[i] = bus_alloc_resource_any(sc->sc_dev, - SYS_RES_IRQ, &sc->sc_irqrid[i], RF_SHAREABLE | RF_ACTIVE)) - == NULL) { - if ((sc->sc_flags & CS4231_SBUS) != 0) - device_printf(sc->sc_dev, - "cannot allocate interrupt\n"); - else - device_printf(sc->sc_dev, "cannot allocate %s " - "interrupt\n", i == 0 ? "capture" : - "playback"); - goto fail; - } - } - - ihandler = cs4231_sbus_intr; - for (i = 0; i < sc->sc_nires; i++) { - if ((sc->sc_flags & CS4231_EBUS) != 0) { - if (i == 0) - ihandler = cs4231_ebus_cintr; - else - ihandler = cs4231_ebus_pintr; - } - if (snd_setup_intr(sc->sc_dev, sc->sc_irqres[i], INTR_MPSAFE, - ihandler, sc, &sc->sc_ih[i])) { - if ((sc->sc_flags & CS4231_SBUS) != 0) - device_printf(sc->sc_dev, - "cannot set up interrupt\n"); - else - device_printf(sc->sc_dev, "cannot set up %s " - " interrupt\n", i == 0 ? "capture" : - "playback"); - goto fail; - } - } - - sc->sc_bufsz = pcm_getbuffersize(sc->sc_dev, CS4231_MIN_BUF_SZ, - CS4231_DEFAULT_BUF_SZ, CS4231_MAX_BUF_SZ); - for (i = 0; i < sc->sc_nires; i++) { - if (bus_dma_tag_create( - bus_get_dma_tag(sc->sc_dev),/* parent */ - 64, 0, /* alignment, boundary */ - BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ - BUS_SPACE_MAXADDR, /* highaddr */ - NULL, NULL, /* filtfunc, filtfuncarg */ - sc->sc_bufsz, /* maxsize */ - 1, /* nsegments */ - sc->sc_bufsz, /* maxsegsz */ - BUS_DMA_ALLOCNOW, /* flags */ - NULL, /* lockfunc */ - NULL, /* lockfuncarg */ - &sc->sc_dmat[i])) { - if ((sc->sc_flags & CS4231_SBUS) != 0) - device_printf(sc->sc_dev, - "cannot allocate DMA tag\n"); - else - device_printf(sc->sc_dev, "cannot allocate %s " - "DMA tag\n", i == 0 ? "capture" : - "playback"); - goto fail; - } - } - cs4231_enable(sc, CODEC_WARM_RESET); - cs4231_getversion(sc); - if (mixer_init(sc->sc_dev, &cs4231_mixer_class, sc) != 0) - goto fail; - if (pcm_register(sc->sc_dev, sc, 1, 1)) { - device_printf(sc->sc_dev, "cannot register to pcm\n"); - goto fail; - } - if (pcm_addchan(sc->sc_dev, PCMDIR_REC, &cs4231_chan_class, sc) != 0) - goto chan_fail; - if (pcm_addchan(sc->sc_dev, PCMDIR_PLAY, &cs4231_chan_class, sc) != 0) - goto chan_fail; - if ((sc->sc_flags & CS4231_SBUS) != 0) - snprintf(status, SND_STATUSLEN, "at mem 0x%lx irq %ld bufsz %u", - rman_get_start(sc->sc_res[0]), - rman_get_start(sc->sc_irqres[0]), sc->sc_bufsz); - else - snprintf(status, SND_STATUSLEN, "at io 0x%lx 0x%lx 0x%lx 0x%lx " - "irq %ld %ld bufsz %u", rman_get_start(sc->sc_res[0]), - rman_get_start(sc->sc_res[1]), - rman_get_start(sc->sc_res[2]), - rman_get_start(sc->sc_res[3]), - rman_get_start(sc->sc_irqres[0]), - rman_get_start(sc->sc_irqres[1]), sc->sc_bufsz); - pcm_setstatus(sc->sc_dev, status); - return (0); - -chan_fail: - pcm_unregister(sc->sc_dev); -fail: - cs4231_free_resource(sc); - return (ENXIO); -} - -static int -cs4231_bus_detach(device_t dev) -{ - struct cs4231_softc *sc; - struct cs4231_channel *pch, *rch; - int error; - - sc = pcm_getdevinfo(dev); - CS4231_LOCK(sc); - pch = &sc->sc_pch; - rch = &sc->sc_pch; - if (pch->locked || rch->locked) { - CS4231_UNLOCK(sc); - return (EBUSY); - } - /* - * Since EBDMA requires valid DMA buffer to drain its FIFO, we need - * real DMA buffer for draining. - */ - if ((sc->sc_flags & CS4231_EBUS) != 0) - cs4231_ebdma_reset(sc); - CS4231_UNLOCK(sc); - error = pcm_unregister(dev); - if (error) - return (error); - cs4231_free_resource(sc); - return (0); -} - -static int -cs4231_bus_suspend(device_t dev) -{ - - return (ENXIO); -} - -static int -cs4231_bus_resume(device_t dev) -{ - - return (ENXIO); -} - -static void -cs4231_getversion(struct cs4231_softc *sc) -{ - u_int8_t v; - - v = cs4231_read(sc, CS_MISC_INFO); - sc->sc_codecv = v & CS_CODEC_ID_MASK; - v = cs4231_read(sc, CS_VERSION_ID); - v &= (CS_VERSION_NUMBER | CS_VERSION_CHIPID); - sc->sc_chipvid = v; - switch(v) { - case 0x80: - device_printf(sc->sc_dev, "\n", - sc->sc_codecv); - break; - case 0xa0: - device_printf(sc->sc_dev, "\n", - sc->sc_codecv); - break; - case 0x82: - device_printf(sc->sc_dev, "\n", - sc->sc_codecv); - break; - default: - device_printf(sc->sc_dev, - "sc_codecv); - break; - } -} - -static void -cs4231_ebdma_reset(struct cs4231_softc *sc) -{ - int i; - - /* playback */ - EBDMA_P_WRITE(sc, EBDMA_DCSR, - EBDMA_P_READ(sc, EBDMA_DCSR) & ~(EBDCSR_INTEN | EBDCSR_NEXTEN)); - EBDMA_P_WRITE(sc, EBDMA_DCSR, EBDCSR_RESET); - for (i = CS_TIMEOUT; - i && EBDMA_P_READ(sc, EBDMA_DCSR) & EBDCSR_DRAIN; i--) - DELAY(1); - if (i == 0) - device_printf(sc->sc_dev, - "timeout waiting for playback DMA reset\n"); - EBDMA_P_WRITE(sc, EBDMA_DCSR, sc->sc_burst); - /* capture */ - EBDMA_C_WRITE(sc, EBDMA_DCSR, - EBDMA_C_READ(sc, EBDMA_DCSR) & ~(EBDCSR_INTEN | EBDCSR_NEXTEN)); - EBDMA_C_WRITE(sc, EBDMA_DCSR, EBDCSR_RESET); - for (i = CS_TIMEOUT; - i && EBDMA_C_READ(sc, EBDMA_DCSR) & EBDCSR_DRAIN; i--) - DELAY(1); - if (i == 0) - device_printf(sc->sc_dev, - "timeout waiting for capture DMA reset\n"); - EBDMA_C_WRITE(sc, EBDMA_DCSR, sc->sc_burst); -} - -static void -cs4231_power_reset(struct cs4231_softc *sc, int how) -{ - u_int32_t v; - int i; - - if ((sc->sc_flags & CS4231_SBUS) != 0) { - APC_WRITE(sc, APC_CSR, APC_CSR_RESET); - DELAY(10); - APC_WRITE(sc, APC_CSR, 0); - DELAY(10); - APC_WRITE(sc, - APC_CSR, APC_READ(sc, APC_CSR) | APC_CSR_CODEC_RESET); - DELAY(20); - APC_WRITE(sc, - APC_CSR, APC_READ(sc, APC_CSR) & (~APC_CSR_CODEC_RESET)); - } else { - v = AUXIO_READ(sc, AUXIO_CODEC); - if (how == CODEC_WARM_RESET && v != 0) { - AUXIO_WRITE(sc, AUXIO_CODEC, 0); - DELAY(20); - } else if (how == CODEC_COLD_RESET){ - AUXIO_WRITE(sc, AUXIO_CODEC, 1); - DELAY(20); - AUXIO_WRITE(sc, AUXIO_CODEC, 0); - DELAY(20); - } - cs4231_ebdma_reset(sc); - } - - for (i = CS_TIMEOUT; - i && CS_READ(sc, CS4231_IADDR) == CS_IN_INIT; i--) - DELAY(10); - if (i == 0) - device_printf(sc->sc_dev, "timeout waiting for reset\n"); - - /* turn on cs4231 mode */ - cs4231_write(sc, CS_MISC_INFO, - cs4231_read(sc, CS_MISC_INFO) | CS_MODE2); - /* enable interrupts & clear CSR */ - cs4231_write(sc, CS_PIN_CONTROL, - cs4231_read(sc, CS_PIN_CONTROL) | INTERRUPT_ENABLE); - CS_WRITE(sc, CS4231_STATUS, 0); - /* enable DAC output */ - cs4231_write(sc, CS_LEFT_OUTPUT_CONTROL, - cs4231_read(sc, CS_LEFT_OUTPUT_CONTROL) & ~OUTPUT_MUTE); - cs4231_write(sc, CS_RIGHT_OUTPUT_CONTROL, - cs4231_read(sc, CS_RIGHT_OUTPUT_CONTROL) & ~OUTPUT_MUTE); - /* mute AUX1 since it generates noises */ - cs4231_write(sc, CS_LEFT_AUX1_CONTROL, - cs4231_read(sc, CS_LEFT_AUX1_CONTROL) | AUX_INPUT_MUTE); - cs4231_write(sc, CS_RIGHT_AUX1_CONTROL, - cs4231_read(sc, CS_RIGHT_AUX1_CONTROL) | AUX_INPUT_MUTE); - /* protect buffer underrun and set output level to 0dB */ - cs4231_write(sc, CS_ALT_FEATURE1, - cs4231_read(sc, CS_ALT_FEATURE1) | CS_DAC_ZERO | CS_OUTPUT_LVL); - /* enable high pass filter, dual xtal was disabled due to noises */ - cs4231_write(sc, CS_ALT_FEATURE2, - cs4231_read(sc, CS_ALT_FEATURE2) | CS_HPF_ENABLE); -} - -static int -cs4231_enable(struct cs4231_softc *sc, int how) -{ - cs4231_power_reset(sc, how); - sc->sc_enabled = 1; - return (0); -} - -static void -cs4231_disable(struct cs4231_softc *sc) -{ - u_int8_t v; - - CS4231_LOCK_ASSERT(sc); - - if (sc->sc_enabled == 0) - return; - sc->sc_enabled = 0; - CS4231_UNLOCK(sc); - cs4231_halt(&sc->sc_pch); - cs4231_halt(&sc->sc_rch); - CS4231_LOCK(sc); - v = cs4231_read(sc, CS_PIN_CONTROL) & ~INTERRUPT_ENABLE; - cs4231_write(sc, CS_PIN_CONTROL, v); - - if ((sc->sc_flags & CS4231_SBUS) != 0) { - APC_WRITE(sc, APC_CSR, APC_CSR_RESET); - DELAY(10); - APC_WRITE(sc, APC_CSR, 0); - DELAY(10); - } else - cs4231_ebdma_reset(sc); -} - -static void -cs4231_free_resource(struct cs4231_softc *sc) -{ - int i; - - CS4231_LOCK(sc); - cs4231_disable(sc); - CS4231_UNLOCK(sc); - for (i = 0; i < sc->sc_nires; i++) { - if (sc->sc_irqres[i]) { - if (sc->sc_ih[i]) { - bus_teardown_intr(sc->sc_dev, sc->sc_irqres[i], - sc->sc_ih[i]); - sc->sc_ih[i] = NULL; - } - bus_release_resource(sc->sc_dev, SYS_RES_IRQ, - sc->sc_irqrid[i], sc->sc_irqres[i]); - sc->sc_irqres[i] = NULL; - } - } - for (i = 0; i < sc->sc_nires; i++) { - if (sc->sc_dmat[i]) - bus_dma_tag_destroy(sc->sc_dmat[i]); - } - for (i = 0; i < sc->sc_nmres; i++) { - if (sc->sc_res[i]) - bus_release_resource(sc->sc_dev, SYS_RES_MEMORY, - sc->sc_rid[i], sc->sc_res[i]); - } - snd_mtxfree(sc->sc_lock); - free(sc, M_DEVBUF); -} - -static void -cs4231_write(struct cs4231_softc *sc, u_int8_t r, u_int8_t v) -{ - CS_WRITE(sc, CS4231_IADDR, r); - CS_WRITE(sc, CS4231_IDATA, v); -} - -static u_int8_t -cs4231_read(struct cs4231_softc *sc, u_int8_t r) -{ - CS_WRITE(sc, CS4231_IADDR, r); - return (CS_READ(sc, CS4231_IDATA)); -} - -static void -cs4231_sbus_intr(void *arg) -{ - struct cs4231_softc *sc; - struct cs4231_channel *pch, *rch; - u_int32_t csr; - u_int8_t status; - - sc = arg; - CS4231_LOCK(sc); - - csr = APC_READ(sc, APC_CSR); - if ((csr & APC_CSR_GI) == 0) { - CS4231_UNLOCK(sc); - return; - } - APC_WRITE(sc, APC_CSR, csr); - - if ((csr & APC_CSR_EIE) && (csr & APC_CSR_EI)) { - status = cs4231_read(sc, CS_TEST_AND_INIT); - device_printf(sc->sc_dev, - "apc error interrupt : stat = 0x%x\n", status); - } - - pch = rch = NULL; - if ((csr & APC_CSR_PMIE) && (csr & APC_CSR_PMI)) { - u_long nextaddr, saddr; - u_int32_t togo; - - pch = &sc->sc_pch; - togo = pch->togo; - saddr = sndbuf_getbufaddr(pch->buffer); - nextaddr = pch->nextaddr + togo; - if (nextaddr >= saddr + sndbuf_getsize(pch->buffer)) - nextaddr = saddr; - APC_WRITE(sc, APC_PNVA, nextaddr); - APC_WRITE(sc, APC_PNC, togo); - pch->nextaddr = nextaddr; - } - - if ((csr & APC_CSR_CIE) && (csr & APC_CSR_CI) && (csr & APC_CSR_CD)) { - u_long nextaddr, saddr; - u_int32_t togo; - - rch = &sc->sc_rch; - togo = rch->togo; - saddr = sndbuf_getbufaddr(rch->buffer); - nextaddr = rch->nextaddr + togo; - if (nextaddr >= saddr + sndbuf_getsize(rch->buffer)) - nextaddr = saddr; - APC_WRITE(sc, APC_CNVA, nextaddr); - APC_WRITE(sc, APC_CNC, togo); - rch->nextaddr = nextaddr; - } - CS4231_UNLOCK(sc); - if (pch) - chn_intr(pch->channel); - if (rch) - chn_intr(rch->channel); -} - -/* playback interrupt handler */ -static void -cs4231_ebus_pintr(void *arg) -{ - struct cs4231_softc *sc; - struct cs4231_channel *ch; - u_int32_t csr; - u_int8_t status; - - sc = arg; - CS4231_LOCK(sc); - - csr = EBDMA_P_READ(sc, EBDMA_DCSR); - if ((csr & EBDCSR_INT) == 0) { - CS4231_UNLOCK(sc); - return; - } - - if ((csr & EBDCSR_ERR)) { - status = cs4231_read(sc, CS_TEST_AND_INIT); - device_printf(sc->sc_dev, - "ebdma error interrupt : stat = 0x%x\n", status); - } - EBDMA_P_WRITE(sc, EBDMA_DCSR, csr | EBDCSR_TC); - - ch = NULL; - if (csr & EBDCSR_TC) { - u_long nextaddr, saddr; - u_int32_t togo; - - ch = &sc->sc_pch; - togo = ch->togo; - saddr = sndbuf_getbufaddr(ch->buffer); - nextaddr = ch->nextaddr + togo; - if (nextaddr >= saddr + sndbuf_getsize(ch->buffer)) - nextaddr = saddr; - /* - * EBDMA_DCNT is loaded automatically - * EBDMA_P_WRITE(sc, EBDMA_DCNT, togo); - */ - EBDMA_P_WRITE(sc, EBDMA_DADDR, nextaddr); - ch->nextaddr = nextaddr; - } - CS4231_UNLOCK(sc); - if (ch) - chn_intr(ch->channel); -} - -/* capture interrupt handler */ -static void -cs4231_ebus_cintr(void *arg) -{ - struct cs4231_softc *sc; - struct cs4231_channel *ch; - u_int32_t csr; - u_int8_t status; - - sc = arg; - CS4231_LOCK(sc); - - csr = EBDMA_C_READ(sc, EBDMA_DCSR); - if ((csr & EBDCSR_INT) == 0) { - CS4231_UNLOCK(sc); - return; - } - if ((csr & EBDCSR_ERR)) { - status = cs4231_read(sc, CS_TEST_AND_INIT); - device_printf(sc->sc_dev, - "dma error interrupt : stat = 0x%x\n", status); - } - EBDMA_C_WRITE(sc, EBDMA_DCSR, csr | EBDCSR_TC); - - ch = NULL; - if (csr & EBDCSR_TC) { - u_long nextaddr, saddr; - u_int32_t togo; - - ch = &sc->sc_rch; - togo = ch->togo; - saddr = sndbuf_getbufaddr(ch->buffer); - nextaddr = ch->nextaddr + togo; - if (nextaddr >= saddr + sndbuf_getblksz(ch->buffer)) - nextaddr = saddr; - /* - * EBDMA_DCNT is loaded automatically - * EBDMA_C_WRITE(sc, EBDMA_DCNT, togo); - */ - EBDMA_C_WRITE(sc, EBDMA_DADDR, nextaddr); - ch->nextaddr = nextaddr; - } - CS4231_UNLOCK(sc); - if (ch) - chn_intr(ch->channel); -} - -static const struct mix_table cs4231_mix_table[SOUND_MIXER_NRDEVICES][2] = { - [SOUND_MIXER_PCM] = { - { CS_LEFT_OUTPUT_CONTROL, 6, OUTPUT_MUTE, 0, 1, 1, 0 }, - { CS_RIGHT_OUTPUT_CONTROL, 6, OUTPUT_MUTE, 0, 1, 1, 0 } - }, - [SOUND_MIXER_SPEAKER] = { - { CS_MONO_IO_CONTROL, 4, MONO_OUTPUT_MUTE, 0, 1, 1, 0 }, - { CS_REG_NONE, 0, 0, 0, 0, 1, 0 } - }, - [SOUND_MIXER_LINE] = { - { CS_LEFT_LINE_CONTROL, 5, LINE_INPUT_MUTE, 0, 1, 1, 1 }, - { CS_RIGHT_LINE_CONTROL, 5, LINE_INPUT_MUTE, 0, 1, 1, 1 } - }, - /* - * AUX1 : removed intentionally since it generates noises - * AUX2 : Ultra1/Ultra2 has no internal CD-ROM audio in - */ - [SOUND_MIXER_CD] = { - { CS_LEFT_AUX2_CONTROL, 5, LINE_INPUT_MUTE, 0, 1, 1, 1 }, - { CS_RIGHT_AUX2_CONTROL, 5, LINE_INPUT_MUTE, 0, 1, 1, 1 } - }, - [SOUND_MIXER_MIC] = { - { CS_LEFT_INPUT_CONTROL, 4, 0, 0, 0, 1, 1 }, - { CS_RIGHT_INPUT_CONTROL, 4, 0, 0, 0, 1, 1 } - }, - [SOUND_MIXER_IGAIN] = { - { CS_LEFT_INPUT_CONTROL, 4, 0, 0, 1, 0 }, - { CS_RIGHT_INPUT_CONTROL, 4, 0, 0, 1, 0 } - } -}; - -static int -cs4231_mixer_init(struct snd_mixer *m) -{ - u_int32_t v; - int i; - - v = 0; - for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) - if (cs4231_mix_table[i][0].avail != 0) - v |= (1 << i); - mix_setdevs(m, v); - v = 0; - for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) - if (cs4231_mix_table[i][0].recdev != 0) - v |= (1 << i); - mix_setrecdevs(m, v); - return (0); -} - -static void -cs4231_mixer_set_value(struct cs4231_softc *sc, const struct mix_table *mt, - u_int8_t v) -{ - u_int8_t mask, reg; - u_int8_t old, shift, val; - - if (mt->avail == 0 || mt->reg == CS_REG_NONE) - return; - reg = mt->reg; - if (mt->neg != 0) - val = 100 - v; - else - val = v; - mask = (1 << mt->bits) - 1; - val = ((val * mask) + 50) / 100; - shift = mt->shift; - val <<= shift; - if (v == 0) - val |= mt->mute; - old = cs4231_read(sc, reg); - old &= ~(mt->mute | (mask << shift)); - val |= old; - if (reg == CS_LEFT_INPUT_CONTROL || reg == CS_RIGHT_INPUT_CONTROL) { - if ((val & (mask << shift)) != 0) - val |= ADC_INPUT_GAIN_ENABLE; - else - val &= ~ADC_INPUT_GAIN_ENABLE; - } - cs4231_write(sc, reg, val); -} - -static int -cs4231_mixer_set(struct snd_mixer *m, u_int32_t dev, u_int32_t left, - u_int32_t right) -{ - struct cs4231_softc *sc; - - sc = mix_getdevinfo(m); - CS4231_LOCK(sc); - cs4231_mixer_set_value(sc, &cs4231_mix_table[dev][0], left); - cs4231_mixer_set_value(sc, &cs4231_mix_table[dev][1], right); - CS4231_UNLOCK(sc); - - return (left | (right << 8)); -} - -static u_int32_t -cs4231_mixer_setrecsrc(struct snd_mixer *m, u_int32_t src) -{ - struct cs4231_softc *sc; - u_int8_t v; - - sc = mix_getdevinfo(m); - switch (src) { - case SOUND_MASK_LINE: - v = CS_IN_LINE; - break; - - case SOUND_MASK_CD: - v = CS_IN_DAC; - break; - - case SOUND_MASK_MIC: - default: - v = CS_IN_MIC; - src = SOUND_MASK_MIC; - break; - } - CS4231_LOCK(sc); - cs4231_write(sc, CS_LEFT_INPUT_CONTROL, - (cs4231_read(sc, CS_LEFT_INPUT_CONTROL) & CS_IN_MASK) | v); - cs4231_write(sc, CS_RIGHT_INPUT_CONTROL, - (cs4231_read(sc, CS_RIGHT_INPUT_CONTROL) & CS_IN_MASK) | v); - CS4231_UNLOCK(sc); - - return (src); -} - -static void * -cs4231_chan_init(kobj_t obj, void *dev, struct snd_dbuf *b, - struct pcm_channel *c, int dir) -{ - struct cs4231_softc *sc; - struct cs4231_channel *ch; - bus_dma_tag_t dmat; - - sc = dev; - ch = (dir == PCMDIR_PLAY) ? &sc->sc_pch : &sc->sc_rch; - ch->parent = sc; - ch->channel = c; - ch->dir = dir; - ch->buffer = b; - if ((sc->sc_flags & CS4231_SBUS) != 0) - dmat = sc->sc_dmat[0]; - else { - if (dir == PCMDIR_PLAY) - dmat = sc->sc_dmat[1]; - else - dmat = sc->sc_dmat[0]; - } - if (sndbuf_alloc(ch->buffer, dmat, 0, sc->sc_bufsz) != 0) - return (NULL); - DPRINTF(("%s channel addr: 0x%lx\n", dir == PCMDIR_PLAY ? "playback" : - "capture", sndbuf_getbufaddr(ch->buffer))); - - return (ch); -} - -static int -cs4231_chan_setformat(kobj_t obj, void *data, u_int32_t format) -{ - struct cs4231_softc *sc; - struct cs4231_channel *ch; - u_int32_t encoding; - u_int8_t fs, v; - - ch = data; - sc = ch->parent; - - CS4231_LOCK(sc); - if (ch->format == format) { - CS4231_UNLOCK(sc); - return (0); - } - - encoding = AFMT_ENCODING(format); - fs = 0; - switch (encoding) { - case AFMT_U8: - fs = CS_AFMT_U8; - break; - case AFMT_MU_LAW: - fs = CS_AFMT_MU_LAW; - break; - case AFMT_S16_LE: - fs = CS_AFMT_S16_LE; - break; - case AFMT_A_LAW: - fs = CS_AFMT_A_LAW; - break; - case AFMT_IMA_ADPCM: - fs = CS_AFMT_IMA_ADPCM; - break; - case AFMT_S16_BE: - fs = CS_AFMT_S16_BE; - break; - default: - fs = CS_AFMT_U8; - format = AFMT_U8; - break; - } - - if (AFMT_CHANNEL(format) > 1) - fs |= CS_AFMT_STEREO; - - DPRINTF(("FORMAT: %s : 0x%x\n", ch->dir == PCMDIR_PLAY ? "playback" : - "capture", format)); - v = cs4231_read(sc, CS_CLOCK_DATA_FORMAT); - v &= CS_CLOCK_DATA_FORMAT_MASK; - fs |= v; - cs4231_chan_fs(sc, ch->dir, fs); - ch->format = format; - CS4231_UNLOCK(sc); - - return (0); -} - -static u_int32_t -cs4231_chan_setspeed(kobj_t obj, void *data, u_int32_t speed) -{ - typedef struct { - u_int32_t speed; - u_int8_t bits; - } speed_struct; - - const static speed_struct speed_table[] = { - {5510, (0 << 1) | CLOCK_XTAL2}, - {5510, (0 << 1) | CLOCK_XTAL2}, - {6620, (7 << 1) | CLOCK_XTAL2}, - {8000, (0 << 1) | CLOCK_XTAL1}, - {9600, (7 << 1) | CLOCK_XTAL1}, - {11025, (1 << 1) | CLOCK_XTAL2}, - {16000, (1 << 1) | CLOCK_XTAL1}, - {18900, (2 << 1) | CLOCK_XTAL2}, - {22050, (3 << 1) | CLOCK_XTAL2}, - {27420, (2 << 1) | CLOCK_XTAL1}, - {32000, (3 << 1) | CLOCK_XTAL1}, - {33075, (6 << 1) | CLOCK_XTAL2}, - {33075, (4 << 1) | CLOCK_XTAL2}, - {44100, (5 << 1) | CLOCK_XTAL2}, - {48000, (6 << 1) | CLOCK_XTAL1}, - }; - - struct cs4231_softc *sc; - struct cs4231_channel *ch; - int i, n, sel; - u_int8_t fs; - - ch = data; - sc = ch->parent; - CS4231_LOCK(sc); - if (ch->speed == speed) { - CS4231_UNLOCK(sc); - return (speed); - } - n = sizeof(speed_table) / sizeof(speed_struct); - - for (i = 1, sel =0; i < n - 1; i++) - if (abs(speed - speed_table[i].speed) < - abs(speed - speed_table[sel].speed)) - sel = i; - DPRINTF(("SPEED: %s : %dHz -> %dHz\n", ch->dir == PCMDIR_PLAY ? - "playback" : "capture", speed, speed_table[sel].speed)); - speed = speed_table[sel].speed; - - fs = cs4231_read(sc, CS_CLOCK_DATA_FORMAT); - fs &= ~CS_CLOCK_DATA_FORMAT_MASK; - fs |= speed_table[sel].bits; - cs4231_chan_fs(sc, ch->dir, fs); - ch->speed = speed; - CS4231_UNLOCK(sc); - - return (speed); -} - -static void -cs4231_chan_fs(struct cs4231_softc *sc, int dir, u_int8_t fs) -{ - int i, doreset; -#ifdef CS4231_AUTO_CALIBRATION - u_int8_t v; -#endif - - CS4231_LOCK_ASSERT(sc); - - /* set autocalibration */ - doreset = 0; -#ifdef CS4231_AUTO_CALIBRATION - v = cs4231_read(sc, CS_INTERFACE_CONFIG) | AUTO_CAL_ENABLE; - CS_WRITE(sc, CS4231_IADDR, MODE_CHANGE_ENABLE); - CS_WRITE(sc, CS4231_IADDR, MODE_CHANGE_ENABLE | CS_INTERFACE_CONFIG); - CS_WRITE(sc, CS4231_IDATA, v); -#endif - - /* - * We always need to write CS_CLOCK_DATA_FORMAT register since - * the clock frequency is shared with playback/capture. - */ - CS_WRITE(sc, CS4231_IADDR, MODE_CHANGE_ENABLE | CS_CLOCK_DATA_FORMAT); - CS_WRITE(sc, CS4231_IDATA, fs); - CS_READ(sc, CS4231_IDATA); - CS_READ(sc, CS4231_IDATA); - for (i = CS_TIMEOUT; - i && CS_READ(sc, CS4231_IADDR) == CS_IN_INIT; i--) - DELAY(10); - if (i == 0) { - device_printf(sc->sc_dev, "timeout setting playback speed\n"); - doreset++; - } - - /* - * capture channel - * cs4231 doesn't allow separate fs setup for playback/capture. - * I believe this will break full-duplex operation. - */ - if (dir == PCMDIR_REC) { - CS_WRITE(sc, CS4231_IADDR, MODE_CHANGE_ENABLE | CS_REC_FORMAT); - CS_WRITE(sc, CS4231_IDATA, fs); - CS_READ(sc, CS4231_IDATA); - CS_READ(sc, CS4231_IDATA); - for (i = CS_TIMEOUT; - i && CS_READ(sc, CS4231_IADDR) == CS_IN_INIT; i--) - DELAY(10); - if (i == 0) { - device_printf(sc->sc_dev, - "timeout setting capture format\n"); - doreset++; - } - } - - CS_WRITE(sc, CS4231_IADDR, 0); - for (i = CS_TIMEOUT; - i && CS_READ(sc, CS4231_IADDR) == CS_IN_INIT; i--) - DELAY(10); - if (i == 0) { - device_printf(sc->sc_dev, "timeout waiting for !MCE\n"); - doreset++; - } - -#ifdef CS4231_AUTO_CALIBRATION - CS_WRITE(sc, CS4231_IADDR, CS_TEST_AND_INIT); - for (i = CS_TIMEOUT; - i && CS_READ(sc, CS4231_IDATA) & AUTO_CAL_IN_PROG; i--) - DELAY(10); - if (i == 0) { - device_printf(sc->sc_dev, - "timeout waiting for autocalibration\n"); - doreset++; - } -#endif - if (doreset) { - /* - * Maybe the last resort to avoid a dreadful message like - * "pcm0:play:0: play interrupt timeout, channel dead" would - * be hardware reset. - */ - device_printf(sc->sc_dev, "trying to hardware reset\n"); - cs4231_disable(sc); - cs4231_enable(sc, CODEC_COLD_RESET); - CS4231_UNLOCK(sc); /* XXX */ - if (mixer_reinit(sc->sc_dev) != 0) - device_printf(sc->sc_dev, - "unable to reinitialize the mixer\n"); - CS4231_LOCK(sc); - } -} - -static u_int32_t -cs4231_chan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize) -{ - struct cs4231_softc *sc; - struct cs4231_channel *ch; - int nblks, error; - - ch = data; - sc = ch->parent; - - if (blocksize > CS4231_MAX_BLK_SZ) - blocksize = CS4231_MAX_BLK_SZ; - nblks = sc->sc_bufsz / blocksize; - error = sndbuf_resize(ch->buffer, nblks, blocksize); - if (error != 0) - device_printf(sc->sc_dev, - "unable to block size, blksz = %d, error = %d\n", - blocksize, error); - - return (blocksize); -} - -static int -cs4231_chan_trigger(kobj_t obj, void *data, int go) -{ - struct cs4231_channel *ch; - - ch = data; - switch (go) { - case PCMTRIG_EMLDMAWR: - case PCMTRIG_EMLDMARD: - break; - case PCMTRIG_START: - cs4231_trigger(ch); - break; - case PCMTRIG_ABORT: - case PCMTRIG_STOP: - cs4231_halt(ch); - break; - default: - break; - } - - return (0); -} - -static u_int32_t -cs4231_chan_getptr(kobj_t obj, void *data) -{ - struct cs4231_softc *sc; - struct cs4231_channel *ch; - u_int32_t cur, ptr, sz; - - ch = data; - sc = ch->parent; - - CS4231_LOCK(sc); - if ((sc->sc_flags & CS4231_SBUS) != 0) - cur = (ch->dir == PCMDIR_PLAY) ? APC_READ(sc, APC_PVA) : - APC_READ(sc, APC_CVA); - else - cur = (ch->dir == PCMDIR_PLAY) ? EBDMA_P_READ(sc, EBDMA_DADDR) : - EBDMA_C_READ(sc, EBDMA_DADDR); - sz = sndbuf_getsize(ch->buffer); - ptr = cur - sndbuf_getbufaddr(ch->buffer) + sz; - CS4231_UNLOCK(sc); - - ptr %= sz; - return (ptr); -} - -static struct pcmchan_caps * -cs4231_chan_getcaps(kobj_t obj, void *data) -{ - - return (&cs4231_caps); -} - -static void -cs4231_trigger(struct cs4231_channel *ch) -{ - struct cs4231_softc *sc; - - sc = ch->parent; - if ((sc->sc_flags & CS4231_SBUS) != 0) - cs4231_apcdma_trigger(sc, ch); - else - cs4231_ebdma_trigger(sc, ch); -} - -static void -cs4231_apcdma_trigger(struct cs4231_softc *sc, struct cs4231_channel *ch) -{ - u_int32_t csr, togo; - u_int32_t nextaddr; - - CS4231_LOCK(sc); - if (ch->locked) { - device_printf(sc->sc_dev, "%s channel already triggered\n", - ch->dir == PCMDIR_PLAY ? "playback" : "capture"); - CS4231_UNLOCK(sc); - return; - } - - nextaddr = sndbuf_getbufaddr(ch->buffer); - togo = sndbuf_getsize(ch->buffer) / 2; - if (togo > CS4231_MAX_APC_DMA_SZ) - togo = CS4231_MAX_APC_DMA_SZ; - ch->togo = togo; - if (ch->dir == PCMDIR_PLAY) { - DPRINTF(("TRG: PNVA = 0x%x, togo = 0x%x\n", nextaddr, togo)); - - cs4231_read(sc, CS_TEST_AND_INIT); /* clear pending error */ - csr = APC_READ(sc, APC_CSR); - APC_WRITE(sc, APC_PNVA, nextaddr); - APC_WRITE(sc, APC_PNC, togo); - - if ((csr & APC_CSR_PDMA_GO) == 0 || - (csr & APC_CSR_PPAUSE) != 0) { - APC_WRITE(sc, APC_CSR, APC_READ(sc, APC_CSR) & - ~(APC_CSR_PIE | APC_CSR_PPAUSE)); - APC_WRITE(sc, APC_CSR, APC_READ(sc, APC_CSR) | - APC_CSR_GIE | APC_CSR_PIE | APC_CSR_EIE | - APC_CSR_EI | APC_CSR_PMIE | APC_CSR_PDMA_GO); - cs4231_write(sc, CS_INTERFACE_CONFIG, - cs4231_read(sc, CS_INTERFACE_CONFIG) | - PLAYBACK_ENABLE); - } - /* load next address */ - if (APC_READ(sc, APC_CSR) & APC_CSR_PD) { - nextaddr += togo; - APC_WRITE(sc, APC_PNVA, nextaddr); - APC_WRITE(sc, APC_PNC, togo); - } - } else { - DPRINTF(("TRG: CNVA = 0x%x, togo = 0x%x\n", nextaddr, togo)); - - cs4231_read(sc, CS_TEST_AND_INIT); /* clear pending error */ - APC_WRITE(sc, APC_CNVA, nextaddr); - APC_WRITE(sc, APC_CNC, togo); - csr = APC_READ(sc, APC_CSR); - if ((csr & APC_CSR_CDMA_GO) == 0 || - (csr & APC_CSR_CPAUSE) != 0) { - csr &= APC_CSR_CPAUSE; - csr |= APC_CSR_GIE | APC_CSR_CMIE | APC_CSR_CIE | - APC_CSR_EI | APC_CSR_CDMA_GO; - APC_WRITE(sc, APC_CSR, csr); - cs4231_write(sc, CS_INTERFACE_CONFIG, - cs4231_read(sc, CS_INTERFACE_CONFIG) | - CAPTURE_ENABLE); - } - /* load next address */ - if (APC_READ(sc, APC_CSR) & APC_CSR_CD) { - nextaddr += togo; - APC_WRITE(sc, APC_CNVA, nextaddr); - APC_WRITE(sc, APC_CNC, togo); - } - } - ch->nextaddr = nextaddr; - ch->locked = 1; - CS4231_UNLOCK(sc); -} - -static void -cs4231_ebdma_trigger(struct cs4231_softc *sc, struct cs4231_channel *ch) -{ - u_int32_t csr, togo; - u_int32_t nextaddr; - - CS4231_LOCK(sc); - if (ch->locked) { - device_printf(sc->sc_dev, "%s channel already triggered\n", - ch->dir == PCMDIR_PLAY ? "playback" : "capture"); - CS4231_UNLOCK(sc); - return; - } - - nextaddr = sndbuf_getbufaddr(ch->buffer); - togo = sndbuf_getsize(ch->buffer) / 2; - if (togo % 64 == 0) - sc->sc_burst = EBDCSR_BURST_16; - else if (togo % 32 == 0) - sc->sc_burst = EBDCSR_BURST_8; - else if (togo % 16 == 0) - sc->sc_burst = EBDCSR_BURST_4; - else - sc->sc_burst = EBDCSR_BURST_1; - ch->togo = togo; - DPRINTF(("TRG: DNAR = 0x%x, togo = 0x%x\n", nextaddr, togo)); - if (ch->dir == PCMDIR_PLAY) { - cs4231_read(sc, CS_TEST_AND_INIT); /* clear pending error */ - csr = EBDMA_P_READ(sc, EBDMA_DCSR); - - if (csr & EBDCSR_DMAEN) { - EBDMA_P_WRITE(sc, EBDMA_DCNT, togo); - EBDMA_P_WRITE(sc, EBDMA_DADDR, nextaddr); - } else { - EBDMA_P_WRITE(sc, EBDMA_DCSR, EBDCSR_RESET); - EBDMA_P_WRITE(sc, EBDMA_DCSR, sc->sc_burst); - EBDMA_P_WRITE(sc, EBDMA_DCNT, togo); - EBDMA_P_WRITE(sc, EBDMA_DADDR, nextaddr); - - EBDMA_P_WRITE(sc, EBDMA_DCSR, sc->sc_burst | - EBDCSR_DMAEN | EBDCSR_INTEN | EBDCSR_CNTEN | - EBDCSR_NEXTEN); - cs4231_write(sc, CS_INTERFACE_CONFIG, - cs4231_read(sc, CS_INTERFACE_CONFIG) | - PLAYBACK_ENABLE); - } - /* load next address */ - if (EBDMA_P_READ(sc, EBDMA_DCSR) & EBDCSR_A_LOADED) { - nextaddr += togo; - EBDMA_P_WRITE(sc, EBDMA_DCNT, togo); - EBDMA_P_WRITE(sc, EBDMA_DADDR, nextaddr); - } - } else { - cs4231_read(sc, CS_TEST_AND_INIT); /* clear pending error */ - csr = EBDMA_C_READ(sc, EBDMA_DCSR); - - if (csr & EBDCSR_DMAEN) { - EBDMA_C_WRITE(sc, EBDMA_DCNT, togo); - EBDMA_C_WRITE(sc, EBDMA_DADDR, nextaddr); - } else { - EBDMA_C_WRITE(sc, EBDMA_DCSR, EBDCSR_RESET); - EBDMA_C_WRITE(sc, EBDMA_DCSR, sc->sc_burst); - EBDMA_C_WRITE(sc, EBDMA_DCNT, togo); - EBDMA_C_WRITE(sc, EBDMA_DADDR, nextaddr); - - EBDMA_C_WRITE(sc, EBDMA_DCSR, sc->sc_burst | - EBDCSR_WRITE | EBDCSR_DMAEN | EBDCSR_INTEN | - EBDCSR_CNTEN | EBDCSR_NEXTEN); - cs4231_write(sc, CS_INTERFACE_CONFIG, - cs4231_read(sc, CS_INTERFACE_CONFIG) | - CAPTURE_ENABLE); - } - /* load next address */ - if (EBDMA_C_READ(sc, EBDMA_DCSR) & EBDCSR_A_LOADED) { - nextaddr += togo; - EBDMA_C_WRITE(sc, EBDMA_DCNT, togo); - EBDMA_C_WRITE(sc, EBDMA_DADDR, nextaddr); - } - } - ch->nextaddr = nextaddr; - ch->locked = 1; - CS4231_UNLOCK(sc); -} - -static void -cs4231_halt(struct cs4231_channel *ch) -{ - struct cs4231_softc *sc; - u_int8_t status; - int i; - - sc = ch->parent; - CS4231_LOCK(sc); - if (ch->locked == 0) { - CS4231_UNLOCK(sc); - return; - } - - if (ch->dir == PCMDIR_PLAY ) { - if ((sc->sc_flags & CS4231_SBUS) != 0) { - /* XXX Kills some capture bits */ - APC_WRITE(sc, APC_CSR, APC_READ(sc, APC_CSR) & - ~(APC_CSR_EI | APC_CSR_GIE | APC_CSR_PIE | - APC_CSR_EIE | APC_CSR_PDMA_GO | APC_CSR_PMIE)); - } else { - EBDMA_P_WRITE(sc, EBDMA_DCSR, - EBDMA_P_READ(sc, EBDMA_DCSR) & ~EBDCSR_DMAEN); - } - /* Waiting for playback FIFO to empty */ - status = cs4231_read(sc, CS_TEST_AND_INIT); - for (i = CS_TIMEOUT; - i && (status & PLAYBACK_UNDERRUN) == 0; i--) { - DELAY(5); - status = cs4231_read(sc, CS_TEST_AND_INIT); - } - if (i == 0) - device_printf(sc->sc_dev, "timeout waiting for " - "playback FIFO drain\n"); - cs4231_write(sc, CS_INTERFACE_CONFIG, - cs4231_read(sc, CS_INTERFACE_CONFIG) & (~PLAYBACK_ENABLE)); - } else { - if ((sc->sc_flags & CS4231_SBUS) != 0) { - /* XXX Kills some playback bits */ - APC_WRITE(sc, APC_CSR, APC_CSR_CAPTURE_PAUSE); - } else { - EBDMA_C_WRITE(sc, EBDMA_DCSR, - EBDMA_C_READ(sc, EBDMA_DCSR) & ~EBDCSR_DMAEN); - } - /* Waiting for capture FIFO to empty */ - status = cs4231_read(sc, CS_TEST_AND_INIT); - for (i = CS_TIMEOUT; - i && (status & CAPTURE_OVERRUN) == 0; i--) { - DELAY(5); - status = cs4231_read(sc, CS_TEST_AND_INIT); - } - if (i == 0) - device_printf(sc->sc_dev, "timeout waiting for " - "capture FIFO drain\n"); - cs4231_write(sc, CS_INTERFACE_CONFIG, - cs4231_read(sc, CS_INTERFACE_CONFIG) & (~CAPTURE_ENABLE)); - } - ch->locked = 0; - CS4231_UNLOCK(sc); -} diff --git a/sys/dev/sound/sbus/cs4231.h b/sys/dev/sound/sbus/cs4231.h deleted file mode 100644 index 36e9932fd0b..00000000000 --- a/sys/dev/sound/sbus/cs4231.h +++ /dev/null @@ -1,242 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-NetBSD - * - * Copyright (c) 1996 The NetBSD Foundation, Inc. - * All rights reserved. - * - * This code is derived from software contributed to The NetBSD Foundation - * by Ken Hornstein and John Kohl. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS - * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -/** - * Register defs for Crystal Semiconductor CS4231 Audio Codec/mixer - * chip, used on Gravis UltraSound MAX cards. - * - * Block diagram: - * +----------------------------------------------------+ - * | | - * | +----------------------------------------------+ | - * | |mixed in +-+ | | - * | +------------>--| | | | - * | mic in | | | | - * Mic --+-->| --------- GAIN ->-| | | | - * | | AUX 1 in |M| | | - * GF1 --)-->| -------------+-->-|U| | | - * | | Line in | |X|---- GAIN ----------+ | | - * Line --)-->| ---------+---)-->-| | | | | - * | | | | | | | | | - * | | | | +-+ ADC | | - * | | | | | | | - * | | | | | | | - * | | | +--- L/M --\ | | | AMP--> - * | | | \ | | | | - * | | | \ | | | | - * | | +---- L/M -------O-->--+--------)-------+-|--+-> line - * | | mono in /| | | | - * +---|-->------------ L/M -----/ | | | | - * | AUX 2 in | | | | - * CD --------|-->------------ L/M -------+ L/M | | - * | | v | - * | | | | - * | DAC | | - * | | | | - * +----------------------------------------------------+ - * | | - * | | - * v v - * Pc BUS (DISK) ??? - * - * Documentation for this chip can be found at: - * http://www.cirrus.com/products/overviews/cs4231.html - */ - -/* - * This file was merged from two header files.(ad1848reg.h and cs4231reg.h) - * And the suffix AD1848 and SP was changed to CS4231 and CS respectively. - */ -/* CS4231 direct registers */ -#define CS4231_IADDR 0x00 -#define CS4231_IDATA 0x01 -#define CS4231_STATUS 0x02 -#define CS4231_PIO 0x03 - -/* Index address register */ -#define CS_IN_INIT 0x80 -#define MODE_CHANGE_ENABLE 0x40 -#define TRANSFER_DISABLE 0x20 -#define ADDRESS_MASK 0xe0 - -/* Status bits */ -#define INTERRUPT_STATUS 0x01 -#define PLAYBACK_READY 0x02 -#define PLAYBACK_LEFT 0x04 -/* pbright is not left */ -#define PLAYBACK_UPPER 0x08 -/* bplower is not upper */ -#define SAMPLE_ERROR 0x10 -#define CAPTURE_READY 0x20 -#define CAPTURE_LEFT 0x40 -/* cpright is not left */ -#define CAPTURE_UPPER 0x80 -/* cplower is not upper */ - -/* CS4231 indirect mapped registers */ -#define CS_LEFT_INPUT_CONTROL 0x00 -#define CS_RIGHT_INPUT_CONTROL 0x01 -#define CS_LEFT_AUX1_CONTROL 0x02 -#define CS_RIGHT_AUX1_CONTROL 0x03 -#define CS_LEFT_AUX2_CONTROL 0x04 -#define CS_RIGHT_AUX2_CONTROL 0x05 -#define CS_LEFT_OUTPUT_CONTROL 0x06 -#define CS_RIGHT_OUTPUT_CONTROL 0x07 -#define CS_CLOCK_DATA_FORMAT 0x08 -#define CS_INTERFACE_CONFIG 0x09 -#define CS_PIN_CONTROL 0x0a -#define CS_TEST_AND_INIT 0x0b -#define CS_MISC_INFO 0x0c -#define CS_DIGITAL_MIX 0x0d -#define CS_UPPER_BASE_COUNT 0x0e -#define CS_LOWER_BASE_COUNT 0x0f -/* CS4231/AD1845 mode2 registers; added to AD1848 registers */ -#define CS_ALT_FEATURE1 0x10 -#define CS_ALT_FEATURE2 0x11 -#define CS_LEFT_LINE_CONTROL 0x12 -#define CS_RIGHT_LINE_CONTROL 0x13 -#define CS_TIMER_LOW 0x14 -#define CS_TIMER_HIGH 0x15 -#define CS_UPPER_FREQUENCY_SEL 0x16 -#define CS_LOWER_FREQUENCY_SEL 0x17 -#define CS_IRQ_STATUS 0x18 -#define CS_VERSION_ID 0x19 -#define CS_MONO_IO_CONTROL 0x1a -#define CS_POWERDOWN_CONTROL 0x1b -#define CS_REC_FORMAT 0x1c -#define CS_XTAL_SELECT 0x1d -#define CS_UPPER_REC_CNT 0x1e -#define CS_LOWER_REC_CNT 0x1f -#define CS_REG_NONE 0xff - -#define CS_IN_MASK 0x2f -#define CS_IN_LINE 0x00 -#define CS_IN_AUX1 0x40 -#define CS_IN_MIC 0x80 -#define CS_IN_DAC 0xc0 -#define CS_MIC_GAIN_ENABLE 0x20 -#define CS_IN_GAIN_MASK 0xf0 - -/* ADC input control - registers I0 (channel 1,left); I1 (channel 1,right) */ -#define ADC_INPUT_ATTEN_BITS 0x0f -#define ADC_INPUT_GAIN_ENABLE 0x20 - -/* Aux input control - registers I2 (channel 1,left); I3 (channel 1,right) - I4 (channel 2,left); I5 (channel 2,right) */ -#define AUX_INPUT_ATTEN_BITS 0x1f -#define AUX_INPUT_ATTEN_MASK 0xe0 -#define AUX_INPUT_MUTE 0x80 - -/* Output bits - registers I6,I7*/ -#define OUTPUT_MUTE 0x80 -#define OUTPUT_ATTEN_BITS 0x3f -#define OUTPUT_ATTEN_MASK (~OUTPUT_ATTEN_BITS & 0xff) - -/* Clock and Data format reg bits (some also Capture Data format) - reg I8 */ -#define CS_CLOCK_DATA_FORMAT_MASK 0x0f -#define CLOCK_XTAL1 0x00 -#define CLOCK_XTAL2 0x01 -#define CLOCK_FREQ_MASK 0xf1 -#define CS_AFMT_STEREO 0x10 -#define CS_AFMT_U8 0x00 -#define CS_AFMT_MU_LAW 0x20 -#define CS_AFMT_S16_LE 0x40 -#define CS_AFMT_A_LAW 0x60 -#define CS_AFMT_IMA_ADPCM 0xa0 -#define CS_AFMT_S16_BE 0xc0 - -/* Interface Configuration reg bits - register I9 */ -#define PLAYBACK_ENABLE 0x01 -#define CAPTURE_ENABLE 0x02 -#define DUAL_DMA 0x00 -#define SINGLE_DMA 0x04 -#define AUTO_CAL_ENABLE 0x08 -#define PLAYBACK_PIO_ENABLE 0x40 -#define CAPTURE_PIO_ENABLE 0x80 - -/* Pin control bits - register I10 */ -#define INTERRUPT_ENABLE 0x02 -#define XCTL0_ENABLE 0x40 -#define XCTL1_ENABLE 0x80 - -/* Test and init reg bits - register I11 (read-only) */ -#define OVERRANGE_LEFT_MASK 0xfc -#define OVERRANGE_RIGHT_MASK 0xf3 -#define DATA_REQUEST_STATUS 0x10 -#define AUTO_CAL_IN_PROG 0x20 -#define PLAYBACK_UNDERRUN 0x40 -#define CAPTURE_OVERRUN 0x80 - -/* Miscellaneous Control reg bits - register I12 */ -#define CS_ID_MASK 0x70 -#define CS_MODE2 0x40 -#define CS_CODEC_ID_MASK 0x0f - -/* Digital Mix Control reg bits - register I13 */ -#define DIGITAL_MIX1_ENABLE 0x01 -#define MIX_ATTEN_MASK 0x03 - -/* Alternate Feature Enable I - register I16 */ -#define CS_DAC_ZERO 0x01 -#define CS_PMC_ENABLE 0x10 -#define CS_CMC_ENABLE 0x20 -#define CS_OUTPUT_LVL 0x80 - -/* Alternate Feature Enable II - register I17 */ -#define CS_HPF_ENABLE 0x01 -#define DUAL_XTAL_ENABLE 0x02 - -/* alternate feature status(I24) */ -#define CS_AFS_TI 0x40 /* timer interrupt */ -#define CS_AFS_CI 0x20 /* capture interrupt */ -#define CS_AFS_PI 0x10 /* playback interrupt */ -#define CS_AFS_CU 0x08 /* capture underrun */ -#define CS_AFS_CO 0x04 /* capture overrun */ -#define CS_AFS_PO 0x02 /* playback overrun */ -#define CS_AFS_PU 0x01 /* playback underrun */ - -/* Version - register I25 */ -#define CS_VERSION_NUMBER 0xe0 -#define CS_VERSION_CHIPID 0x07 - -/* Miscellaneous Control reg bits */ -#define CS_MODE2 0x40 - -#define MONO_INPUT_ATTEN_BITS 0x0f -#define MONO_INPUT_ATTEN_MASK 0xf0 -#define MONO_OUTPUT_MUTE 0x40 -#define MONO_INPUT_MUTE 0x80 -#define MONO_INPUT_MUTE_MASK 0x7f - -#define LINE_INPUT_ATTEN_BITS 0x1f -#define LINE_INPUT_ATTEN_MASK 0xe0 -#define LINE_INPUT_MUTE 0x80 -#define LINE_INPUT_MUTE_MASK 0x7f diff --git a/sys/dev/syscons/apm/apm_saver.c b/sys/dev/syscons/apm/apm_saver.c deleted file mode 100644 index d0c4ee435ec..00000000000 --- a/sys/dev/syscons/apm/apm_saver.c +++ /dev/null @@ -1,94 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-3-Clause - * - * Copyright (c) 1999 Nick Sayer (who stole shamelessly from blank_saver) - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer, - * without modification, immediately at the beginning of the file. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include -#include -#include -#include -#include - -extern int apm_display(int newstate); - -extern struct apm_softc apm_softc; - -static int blanked=0; - -static int -apm_saver(video_adapter_t *adp, int blank) -{ - if (!apm_softc.initialized || !apm_softc.active) - return 0; - - if (blank==blanked) - return 0; - - blanked=blank; - - apm_display(!blanked); - - return 0; -} - -static int -apm_init(video_adapter_t *adp) -{ - if (!apm_softc.initialized || !apm_softc.active) - printf("WARNING: apm_saver module requires apm enabled\n"); - return 0; -} - -static int -apm_term(video_adapter_t *adp) -{ - return 0; -} - -static scrn_saver_t apm_module = { - "apm_saver", apm_init, apm_term, apm_saver, NULL, -}; - -SAVER_MODULE(apm_saver, apm_module); -MODULE_DEPEND(apm_saver, apm, 1, 1, 1); diff --git a/sys/dev/uart/uart_bus_ebus.c b/sys/dev/uart/uart_bus_ebus.c deleted file mode 100644 index eabbe252249..00000000000 --- a/sys/dev/uart/uart_bus_ebus.c +++ /dev/null @@ -1,107 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2001 by Thomas Moestl . - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include - -#include -#include -#include -#include -#include - -#include - -#include -#include -#include -#include - -#include -#include -#include - -static int uart_ebus_probe(device_t dev); - -static device_method_t uart_ebus_methods[] = { - /* Device interface */ - DEVMETHOD(device_probe, uart_ebus_probe), - DEVMETHOD(device_attach, uart_bus_attach), - DEVMETHOD(device_detach, uart_bus_detach), - { 0, 0 } -}; - -static driver_t uart_ebus_driver = { - uart_driver_name, - uart_ebus_methods, - sizeof(struct uart_softc), -}; - -static int -uart_ebus_probe(device_t dev) -{ - const char *nm, *cmpt; - struct uart_softc *sc; - struct uart_devinfo dummy; - - sc = device_get_softc(dev); - sc->sc_class = NULL; - - nm = ofw_bus_get_name(dev); - cmpt = ofw_bus_get_compat(dev); - if (cmpt == NULL) - cmpt = ""; - if (!strcmp(nm, "lom-console") || !strcmp(nm, "su") || - !strcmp(nm, "su_pnp") || !strcmp(cmpt, "rsc-console") || - !strcmp(cmpt, "rsc-control") || !strcmp(cmpt, "su") || - !strcmp(cmpt, "su16550") || !strcmp(cmpt, "su16552")) { - /* - * On AXi and AXmp boards the NS16550 (used to connect - * keyboard/mouse) share their IRQ lines with the i8042. - * Any IRQ activity (typically during attach) of the - * NS16550 used to connect the keyboard when actually the - * PS/2 keyboard is selected in OFW causes interaction - * with the OBP i8042 driver resulting in a hang and vice - * versa. As RS232 keyboards and mice obviously aren't - * meant to be used in parallel with PS/2 ones on these - * boards don't attach to the NS16550 in case the RS232 - * keyboard isn't selected in order to prevent such hangs. - */ - if ((!strcmp(sparc64_model, "SUNW,UltraAX-MP") || - !strcmp(sparc64_model, "SUNW,UltraSPARC-IIi-Engine")) && - uart_cpu_getdev(UART_DEV_KEYBOARD, &dummy)) { - device_disable(dev); - return (ENXIO); - } - sc->sc_class = &uart_ns8250_class; - return (uart_bus_probe(dev, 0, 0, 0, 0, 0, 0)); - } - - return (ENXIO); -} - -DRIVER_MODULE(uart, ebus, uart_ebus_driver, uart_devclass, 0, 0); diff --git a/sys/dev/uart/uart_bus_pccard.c b/sys/dev/uart/uart_bus_pccard.c deleted file mode 100644 index 02cf8db72a4..00000000000 --- a/sys/dev/uart/uart_bus_pccard.c +++ /dev/null @@ -1,106 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2001 M. Warner Losh. All rights reserved. - * Copyright (c) 2003 Norikatsu Shigemura, Takenori Watanabe All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include -#include - -#include "pccarddevs.h" - -static int uart_pccard_probe(device_t dev); -static int uart_pccard_attach(device_t dev); - -static device_method_t uart_pccard_methods[] = { - /* Device interface */ - DEVMETHOD(device_probe, uart_pccard_probe), - DEVMETHOD(device_attach, uart_pccard_attach), - DEVMETHOD(device_detach, uart_bus_detach), - - { 0, 0 } -}; - -static uint32_t uart_pccard_function = PCCARD_FUNCTION_SERIAL; - -static driver_t uart_pccard_driver = { - uart_driver_name, - uart_pccard_methods, - sizeof(struct uart_softc), -}; - -static int -uart_pccard_probe(device_t dev) -{ - int error; - uint32_t fcn; - - fcn = PCCARD_FUNCTION_UNSPEC; - error = pccard_get_function(dev, &fcn); - if (error != 0) - return (error); - /* - * If a serial card, we are likely the right driver. However, - * some serial cards are better serviced by other drivers, so - * allow other drivers to claim it, if they want. - */ - if (fcn == uart_pccard_function) - return (BUS_PROBE_GENERIC); - - return (ENXIO); -} - -static int -uart_pccard_attach(device_t dev) -{ - struct uart_softc *sc; - int error; - - sc = device_get_softc(dev); - sc->sc_class = &uart_ns8250_class; - - error = uart_bus_probe(dev, 0, 0, 0, 0, 0, 0); - if (error > 0) - return (error); - gone_in_dev(dev, 13, "pccard removed"); - return (uart_bus_attach(dev)); -} - -DRIVER_MODULE(uart, pccard, uart_pccard_driver, uart_devclass, 0, 0); -MODULE_PNP_INFO("U32:function_type;", pccard, uart, &uart_pccard_function, - 1); diff --git a/sys/dev/uart/uart_cpu_sparc64.c b/sys/dev/uart/uart_cpu_sparc64.c deleted file mode 100644 index d0caf141b8b..00000000000 --- a/sys/dev/uart/uart_cpu_sparc64.c +++ /dev/null @@ -1,306 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2003, 2004 Marcel Moolenaar - * Copyright (c) 2004 - 2006 Marius Strobl - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include - -#include -#include - -#include -#include - -#include -#include - -#include -#include - -bus_space_tag_t uart_bus_space_io; -bus_space_tag_t uart_bus_space_mem; - -static struct bus_space_tag bst_store[3]; - -/* - * Determine which channel of a SCC a device referenced by a full device - * path or as an alias is (in the latter case we try to look up the device - * path via the /aliases node). - * Only the device paths of devices which are used for TTYs really allow - * to do this as they look like these (taken from /aliases nodes): - * ttya: '/central/fhc/zs@0,902000:a' - * ttyc: '/pci@1f,0/pci@1,1/ebus@1/se@14,400000:a' - * Additionally, for device paths of SCCs which are connected to a RSC - * (Remote System Control) device we can hardcode the appropriate channel. - * Such device paths look like these: - * rsc: '/pci@1f,4000/ebus@1/se@14,200000:ssp' - * ttyc: '/pci@1f,4000/ebus@1/se@14,200000:ssp' - */ -static int -uart_cpu_channel(char *dev) -{ - char alias[64]; - phandle_t aliases; - int len; - const char *p; - - strcpy(alias, dev); - if ((aliases = OF_finddevice("/aliases")) != -1) - (void)OF_getprop(aliases, dev, alias, sizeof(alias)); - len = strlen(alias); - if ((p = strrchr(alias, ':')) == NULL) - return (0); - p++; - if (p - alias == len - 1 && (*p == 'a' || *p == 'b')) - return (*p - 'a' + 1); - if (strcmp(p, "ssp") == 0) - return (1); - return (0); -} - -int -uart_cpu_eqres(struct uart_bas *b1, struct uart_bas *b2) -{ - - return ((b1->bsh == b2->bsh) ? 1 : 0); -} - -/* - * Get the package handle of the UART that is selected as the console, if - * the console is an UART of course. Note that we enforce that both input - * and output are selected. - * Note that the currently active console (i.e. /chosen/stdout and - * /chosen/stdin) may not be the same as the device selected in the - * environment (ie /options/output-device and /options/input-device) because - * keyboard and screen were selected but the keyboard was unplugged or the - * user has changed the environment. In the latter case I would assume that - * the user expects that FreeBSD uses the new console setting. - * For weirder configurations, use ofw_console(4). - */ -static phandle_t -uart_cpu_getdev_console(phandle_t options, char *dev, size_t devsz) -{ - char buf[sizeof("serial")]; - ihandle_t inst; - phandle_t chosen, input, output; - - if (OF_getprop(options, "input-device", dev, devsz) == -1) - return (-1); - input = OF_finddevice(dev); - if (OF_getprop(options, "output-device", dev, devsz) == -1) - return (-1); - output = OF_finddevice(dev); - if (input == -1 || output == -1 || - OF_getproplen(input, "keyboard") >= 0) { - if ((chosen = OF_finddevice("/chosen")) == -1) - return (-1); - if (OF_getprop(chosen, "stdin", &inst, sizeof(inst)) == -1) - return (-1); - if ((input = OF_instance_to_package(inst)) == -1) - return (-1); - if (OF_getprop(chosen, "stdout", &inst, sizeof(inst)) == -1) - return (-1); - if ((output = OF_instance_to_package(inst)) == -1) - return (-1); - snprintf(dev, devsz, "ttya"); - } - if (input != output) - return (-1); - if (OF_getprop(input, "device_type", buf, sizeof(buf)) == -1) - return (-1); - if (strcmp(buf, "serial") != 0) - return (-1); - /* For a Serengeti console device point to the bootbus controller. */ - if (OF_getprop(input, "name", buf, sizeof(buf)) > 0 && - !strcmp(buf, "sgcn")) { - if ((chosen = OF_finddevice("/chosen")) == -1) - return (-1); - if (OF_getprop(chosen, "iosram", &input, sizeof(input)) == -1) - return (-1); - } - return (input); -} - -/* - * Get the package handle of the UART that's selected as the debug port. - * Since there's no place for this in the OF, we use the kernel environment - * variable "hw.uart.dbgport". Note however that the variable is not a - * list of attributes. It's single device name or alias, as known by - * the OF. - */ -static phandle_t -uart_cpu_getdev_dbgport(char *dev, size_t devsz) -{ - char buf[sizeof("serial")]; - phandle_t input; - - if (!getenv_string("hw.uart.dbgport", dev, devsz)) - return (-1); - if ((input = OF_finddevice(dev)) == -1) - return (-1); - if (OF_getprop(input, "device_type", buf, sizeof(buf)) == -1) - return (-1); - if (strcmp(buf, "serial") != 0) - return (-1); - return (input); -} - -/* - * Get the package handle of the UART that is selected as the keyboard port, - * if it's actually used to connect the keyboard according to the OF. I.e. - * this will return the UART used to connect the keyboard regardless whether - * it's stdin or not, however not in case the user or the OF gave preference - * to e.g. a PS/2 keyboard by setting /aliases/keyboard accordingly. - */ -static phandle_t -uart_cpu_getdev_keyboard(char *dev, size_t devsz) -{ - char buf[sizeof("serial")]; - phandle_t input; - - if ((input = OF_finddevice("keyboard")) == -1) - return (-1); - if (OF_getprop(input, "device_type", buf, sizeof(buf)) == -1) - return (-1); - if (strcmp(buf, "serial") != 0) - return (-1); - if (OF_getprop(input, "name", dev, devsz) == -1) - return (-1); - /* - * So far this also matched PS/2 keyboard nodes so make sure it's - * one of the SCCs/UARTs known to be used to connect keyboards. - */ - if (strcmp(dev, "su") && strcmp(dev, "su_pnp") && strcmp(dev, "zs")) - return (-1); - return (input); -} - -int -uart_cpu_getdev(int devtype, struct uart_devinfo *di) -{ - char buf[32], compat[32], dev[64]; - struct uart_class *class; - phandle_t input, options; - bus_addr_t addr; - int baud, bits, error, range, space, stop; - char flag, par; - - if ((options = OF_finddevice("/options")) == -1) - return (ENXIO); - switch (devtype) { - case UART_DEV_CONSOLE: - input = uart_cpu_getdev_console(options, dev, sizeof(dev)); - break; - case UART_DEV_DBGPORT: - input = uart_cpu_getdev_dbgport(dev, sizeof(dev)); - break; - case UART_DEV_KEYBOARD: - input = uart_cpu_getdev_keyboard(dev, sizeof(dev)); - break; - default: - input = -1; - break; - } - if (input == -1) - return (ENXIO); - error = OF_decode_addr(input, 0, &space, &addr); - if (error) - return (error); - - /* Get the device class. */ - if (OF_getprop(input, "name", buf, sizeof(buf)) == -1) - return (ENXIO); - if (OF_getprop(input, "compatible", compat, sizeof(compat)) == -1) - compat[0] = '\0'; - di->bas.regshft = 0; - di->bas.rclk = 0; - class = NULL; - if (!strcmp(buf, "se") || !strcmp(buf, "FJSV,se") || - !strcmp(compat, "sab82532")) { - class = &uart_sab82532_class; - /* SAB82532 are only known to be used for TTYs. */ - if ((di->bas.chan = uart_cpu_channel(dev)) == 0) - return (ENXIO); - addr += uart_getrange(class) * (di->bas.chan - 1); - } else if (!strcmp(buf, "zs")) { - class = &uart_z8530_class; - if ((di->bas.chan = uart_cpu_channel(dev)) == 0) { - /* - * There's no way to determine from OF which - * channel has the keyboard. Should always be - * on channel 1 however. - */ - if (devtype == UART_DEV_KEYBOARD) - di->bas.chan = 1; - else - return (ENXIO); - } - di->bas.regshft = 1; - range = uart_getrange(class) << di->bas.regshft; - addr += range - range * (di->bas.chan - 1); - } else if (!strcmp(buf, "lom-console") || !strcmp(buf, "su") || - !strcmp(buf, "su_pnp") || !strcmp(compat, "rsc-console") || - !strcmp(compat, "su") || !strcmp(compat, "su16550") || - !strcmp(compat, "su16552")) { - class = &uart_ns8250_class; - di->bas.chan = 0; - } else if (!strcmp(compat, "sgsbbc")) { - class = &uart_sbbc_class; - di->bas.chan = 0; - } - if (class == NULL) - return (ENXIO); - - /* Fill in the device info. */ - di->ops = uart_getops(class); - di->bas.bst = &bst_store[devtype]; - di->bas.bsh = sparc64_fake_bustag(space, addr, di->bas.bst); - - /* Get the line settings. */ - if (devtype == UART_DEV_KEYBOARD) - di->baudrate = 1200; - else if (!strcmp(compat, "rsc-console")) - di->baudrate = 115200; - else - di->baudrate = 9600; - di->databits = 8; - di->stopbits = 1; - di->parity = UART_PARITY_NONE; - snprintf(buf, sizeof(buf), "%s-mode", dev); - if (OF_getprop(options, buf, buf, sizeof(buf)) == -1 && - OF_getprop(input, "ssp-console-modes", buf, sizeof(buf)) == -1) - return (0); - if (sscanf(buf, "%d,%d,%c,%d,%c", &baud, &bits, &par, &stop, &flag) - != 5) - return (0); - di->baudrate = baud; - di->databits = bits; - di->stopbits = stop; - di->parity = (par == 'n') ? UART_PARITY_NONE : - (par == 'o') ? UART_PARITY_ODD : UART_PARITY_EVEN; - return (0); -} diff --git a/sys/dev/uart/uart_dev_sab82532.c b/sys/dev/uart/uart_dev_sab82532.c deleted file mode 100644 index 820234d1f69..00000000000 --- a/sys/dev/uart/uart_dev_sab82532.c +++ /dev/null @@ -1,761 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2003 Marcel Moolenaar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include - -#include -#include -#include -#include -#include - -#include -#include -#include - -#include - -#include "uart_if.h" - -#define DEFAULT_RCLK 29491200 - -/* - * NOTE: To allow us to read the baudrate divisor from the chip, we - * copy the value written to the write-only BGR register to an unused - * read-write register. We use TCR for that. - */ - -static int -sab82532_delay(struct uart_bas *bas) -{ - int divisor, m, n; - uint8_t bgr, ccr2; - - bgr = uart_getreg(bas, SAB_TCR); - ccr2 = uart_getreg(bas, SAB_CCR2); - n = (bgr & 0x3f) + 1; - m = (bgr >> 6) | ((ccr2 >> 4) & 0xC); - divisor = n * (1<rclk); -} - -static int -sab82532_divisor(int rclk, int baudrate) -{ - int act_baud, act_div, divisor; - int error, m, n; - - if (baudrate == 0) - return (0); - - divisor = (rclk / (baudrate << 3) + 1) >> 1; - if (divisor < 2 || divisor >= 1048576) - return (0); - - /* Find the best (N+1,M) pair. */ - for (m = 1; m < 15; m++) { - n = divisor / (1< 63) - continue; - act_div = n * (1<> 1; - - /* 3.0% maximum error tolerance: */ - if (error < -30 || error > 30) - continue; - - /* Got it. */ - return ((n - 1) | (m << 6)); - } - - return (0); -} - -static void -sab82532_flush(struct uart_bas *bas, int what) -{ - - if (what & UART_FLUSH_TRANSMITTER) { - while (uart_getreg(bas, SAB_STAR) & SAB_STAR_CEC) - ; - uart_setreg(bas, SAB_CMDR, SAB_CMDR_XRES); - uart_barrier(bas); - } - if (what & UART_FLUSH_RECEIVER) { - while (uart_getreg(bas, SAB_STAR) & SAB_STAR_CEC) - ; - uart_setreg(bas, SAB_CMDR, SAB_CMDR_RRES); - uart_barrier(bas); - } -} - -static int -sab82532_param(struct uart_bas *bas, int baudrate, int databits, int stopbits, - int parity) -{ - int divisor; - uint8_t ccr2, dafo; - - if (databits >= 8) - dafo = SAB_DAFO_CHL_CS8; - else if (databits == 7) - dafo = SAB_DAFO_CHL_CS7; - else if (databits == 6) - dafo = SAB_DAFO_CHL_CS6; - else - dafo = SAB_DAFO_CHL_CS5; - if (stopbits > 1) - dafo |= SAB_DAFO_STOP; - switch (parity) { - case UART_PARITY_EVEN: dafo |= SAB_DAFO_PAR_EVEN; break; - case UART_PARITY_MARK: dafo |= SAB_DAFO_PAR_MARK; break; - case UART_PARITY_NONE: dafo |= SAB_DAFO_PAR_NONE; break; - case UART_PARITY_ODD: dafo |= SAB_DAFO_PAR_ODD; break; - case UART_PARITY_SPACE: dafo |= SAB_DAFO_PAR_SPACE; break; - default: return (EINVAL); - } - - /* Set baudrate. */ - if (baudrate > 0) { - divisor = sab82532_divisor(bas->rclk, baudrate); - if (divisor == 0) - return (EINVAL); - uart_setreg(bas, SAB_BGR, divisor & 0xff); - uart_barrier(bas); - /* Allow reading the (n-1,m) tuple from the chip. */ - uart_setreg(bas, SAB_TCR, divisor & 0xff); - uart_barrier(bas); - ccr2 = uart_getreg(bas, SAB_CCR2); - ccr2 &= ~(SAB_CCR2_BR9 | SAB_CCR2_BR8); - ccr2 |= (divisor >> 2) & (SAB_CCR2_BR9 | SAB_CCR2_BR8); - uart_setreg(bas, SAB_CCR2, ccr2); - uart_barrier(bas); - } - - uart_setreg(bas, SAB_DAFO, dafo); - uart_barrier(bas); - return (0); -} - -/* - * Low-level UART interface. - */ -static int sab82532_probe(struct uart_bas *bas); -static void sab82532_init(struct uart_bas *bas, int, int, int, int); -static void sab82532_term(struct uart_bas *bas); -static void sab82532_putc(struct uart_bas *bas, int); -static int sab82532_rxready(struct uart_bas *bas); -static int sab82532_getc(struct uart_bas *bas, struct mtx *); - -static struct uart_ops uart_sab82532_ops = { - .probe = sab82532_probe, - .init = sab82532_init, - .term = sab82532_term, - .putc = sab82532_putc, - .rxready = sab82532_rxready, - .getc = sab82532_getc, -}; - -static int -sab82532_probe(struct uart_bas *bas) -{ - - return (0); -} - -static void -sab82532_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, - int parity) -{ - uint8_t ccr0, pvr; - - if (bas->rclk == 0) - bas->rclk = DEFAULT_RCLK; - - /* - * Set all pins, except the DTR pins (pin 1 and 2) to be inputs. - * Pin 4 is magical, meaning that I don't know what it does, but - * it too has to be set to output. - */ - uart_setreg(bas, SAB_PCR, - ~(SAB_PVR_DTR_A|SAB_PVR_DTR_B|SAB_PVR_MAGIC)); - uart_barrier(bas); - /* Disable port interrupts. */ - uart_setreg(bas, SAB_PIM, 0xff); - uart_barrier(bas); - /* Interrupts are active low. */ - uart_setreg(bas, SAB_IPC, SAB_IPC_ICPL); - uart_barrier(bas); - /* Set DTR. */ - pvr = uart_getreg(bas, SAB_PVR); - switch (bas->chan) { - case 1: - pvr &= ~SAB_PVR_DTR_A; - break; - case 2: - pvr &= ~SAB_PVR_DTR_B; - break; - } - uart_setreg(bas, SAB_PVR, pvr | SAB_PVR_MAGIC); - uart_barrier(bas); - - /* power down */ - uart_setreg(bas, SAB_CCR0, 0); - uart_barrier(bas); - - /* set basic configuration */ - ccr0 = SAB_CCR0_MCE|SAB_CCR0_SC_NRZ|SAB_CCR0_SM_ASYNC; - uart_setreg(bas, SAB_CCR0, ccr0); - uart_barrier(bas); - uart_setreg(bas, SAB_CCR1, SAB_CCR1_ODS|SAB_CCR1_BCR|SAB_CCR1_CM_7); - uart_barrier(bas); - uart_setreg(bas, SAB_CCR2, SAB_CCR2_BDF|SAB_CCR2_SSEL|SAB_CCR2_TOE); - uart_barrier(bas); - uart_setreg(bas, SAB_CCR3, 0); - uart_barrier(bas); - uart_setreg(bas, SAB_CCR4, SAB_CCR4_MCK4|SAB_CCR4_EBRG|SAB_CCR4_ICD); - uart_barrier(bas); - uart_setreg(bas, SAB_MODE, SAB_MODE_FCTS|SAB_MODE_RTS|SAB_MODE_RAC); - uart_barrier(bas); - uart_setreg(bas, SAB_RFC, SAB_RFC_DPS|SAB_RFC_RFDF| - SAB_RFC_RFTH_32CHAR); - uart_barrier(bas); - - sab82532_param(bas, baudrate, databits, stopbits, parity); - - /* Clear interrupts. */ - uart_setreg(bas, SAB_IMR0, (unsigned char)~SAB_IMR0_TCD); - uart_setreg(bas, SAB_IMR1, 0xff); - uart_barrier(bas); - uart_getreg(bas, SAB_ISR0); - uart_getreg(bas, SAB_ISR1); - uart_barrier(bas); - - sab82532_flush(bas, UART_FLUSH_TRANSMITTER|UART_FLUSH_RECEIVER); - - /* Power up. */ - uart_setreg(bas, SAB_CCR0, ccr0|SAB_CCR0_PU); - uart_barrier(bas); -} - -static void -sab82532_term(struct uart_bas *bas) -{ - uint8_t pvr; - - pvr = uart_getreg(bas, SAB_PVR); - switch (bas->chan) { - case 1: - pvr |= SAB_PVR_DTR_A; - break; - case 2: - pvr |= SAB_PVR_DTR_B; - break; - } - uart_setreg(bas, SAB_PVR, pvr); - uart_barrier(bas); -} - -static void -sab82532_putc(struct uart_bas *bas, int c) -{ - int delay, limit; - - /* 1/10th the time to transmit 1 character (estimate). */ - delay = sab82532_delay(bas); - - limit = 20; - while ((uart_getreg(bas, SAB_STAR) & SAB_STAR_TEC) && --limit) - DELAY(delay); - uart_setreg(bas, SAB_TIC, c); - limit = 20; - while ((uart_getreg(bas, SAB_STAR) & SAB_STAR_TEC) && --limit) - DELAY(delay); -} - -static int -sab82532_rxready(struct uart_bas *bas) -{ - - return ((uart_getreg(bas, SAB_STAR) & SAB_STAR_RFNE) != 0 ? 1 : 0); -} - -static int -sab82532_getc(struct uart_bas *bas, struct mtx *hwmtx) -{ - int c, delay; - - uart_lock(hwmtx); - - /* 1/10th the time to transmit 1 character (estimate). */ - delay = sab82532_delay(bas); - - while (!(uart_getreg(bas, SAB_STAR) & SAB_STAR_RFNE)) { - uart_unlock(hwmtx); - DELAY(delay); - uart_lock(hwmtx); - } - - while (uart_getreg(bas, SAB_STAR) & SAB_STAR_CEC) - ; - uart_setreg(bas, SAB_CMDR, SAB_CMDR_RFRD); - uart_barrier(bas); - - while (!(uart_getreg(bas, SAB_ISR0) & SAB_ISR0_TCD)) - DELAY(delay); - - c = uart_getreg(bas, SAB_RFIFO); - uart_barrier(bas); - - /* Blow away everything left in the FIFO... */ - while (uart_getreg(bas, SAB_STAR) & SAB_STAR_CEC) - ; - uart_setreg(bas, SAB_CMDR, SAB_CMDR_RMC); - uart_barrier(bas); - - uart_unlock(hwmtx); - - return (c); -} - -/* - * High-level UART interface. - */ -struct sab82532_softc { - struct uart_softc base; -}; - -static int sab82532_bus_attach(struct uart_softc *); -static int sab82532_bus_detach(struct uart_softc *); -static int sab82532_bus_flush(struct uart_softc *, int); -static int sab82532_bus_getsig(struct uart_softc *); -static int sab82532_bus_ioctl(struct uart_softc *, int, intptr_t); -static int sab82532_bus_ipend(struct uart_softc *); -static int sab82532_bus_param(struct uart_softc *, int, int, int, int); -static int sab82532_bus_probe(struct uart_softc *); -static int sab82532_bus_receive(struct uart_softc *); -static int sab82532_bus_setsig(struct uart_softc *, int); -static int sab82532_bus_transmit(struct uart_softc *); -static void sab82532_bus_grab(struct uart_softc *); -static void sab82532_bus_ungrab(struct uart_softc *); - -static kobj_method_t sab82532_methods[] = { - KOBJMETHOD(uart_attach, sab82532_bus_attach), - KOBJMETHOD(uart_detach, sab82532_bus_detach), - KOBJMETHOD(uart_flush, sab82532_bus_flush), - KOBJMETHOD(uart_getsig, sab82532_bus_getsig), - KOBJMETHOD(uart_ioctl, sab82532_bus_ioctl), - KOBJMETHOD(uart_ipend, sab82532_bus_ipend), - KOBJMETHOD(uart_param, sab82532_bus_param), - KOBJMETHOD(uart_probe, sab82532_bus_probe), - KOBJMETHOD(uart_receive, sab82532_bus_receive), - KOBJMETHOD(uart_setsig, sab82532_bus_setsig), - KOBJMETHOD(uart_transmit, sab82532_bus_transmit), - KOBJMETHOD(uart_grab, sab82532_bus_grab), - KOBJMETHOD(uart_ungrab, sab82532_bus_ungrab), - { 0, 0 } -}; - -struct uart_class uart_sab82532_class = { - "sab82532", - sab82532_methods, - sizeof(struct sab82532_softc), - .uc_ops = &uart_sab82532_ops, - .uc_range = 64, - .uc_rclk = DEFAULT_RCLK, - .uc_rshift = 0 -}; - -#define SIGCHG(c, i, s, d) \ - if (c) { \ - i |= (i & s) ? s : s | d; \ - } else { \ - i = (i & s) ? (i & ~s) | d : i; \ - } - -static int -sab82532_bus_attach(struct uart_softc *sc) -{ - struct uart_bas *bas; - uint8_t imr0, imr1; - - bas = &sc->sc_bas; - if (sc->sc_sysdev == NULL) - sab82532_init(bas, 9600, 8, 1, UART_PARITY_NONE); - - imr0 = SAB_IMR0_TCD|SAB_IMR0_TIME|SAB_IMR0_CDSC|SAB_IMR0_RFO| - SAB_IMR0_RPF; - uart_setreg(bas, SAB_IMR0, 0xff & ~imr0); - imr1 = SAB_IMR1_BRKT|SAB_IMR1_ALLS|SAB_IMR1_CSC; - uart_setreg(bas, SAB_IMR1, 0xff & ~imr1); - uart_barrier(bas); - - if (sc->sc_sysdev == NULL) - sab82532_bus_setsig(sc, SER_DDTR|SER_DRTS); - (void)sab82532_bus_getsig(sc); - return (0); -} - -static int -sab82532_bus_detach(struct uart_softc *sc) -{ - struct uart_bas *bas; - - bas = &sc->sc_bas; - uart_setreg(bas, SAB_IMR0, 0xff); - uart_setreg(bas, SAB_IMR1, 0xff); - uart_barrier(bas); - uart_getreg(bas, SAB_ISR0); - uart_getreg(bas, SAB_ISR1); - uart_barrier(bas); - uart_setreg(bas, SAB_CCR0, 0); - uart_barrier(bas); - return (0); -} - -static int -sab82532_bus_flush(struct uart_softc *sc, int what) -{ - - uart_lock(sc->sc_hwmtx); - sab82532_flush(&sc->sc_bas, what); - uart_unlock(sc->sc_hwmtx); - return (0); -} - -static int -sab82532_bus_getsig(struct uart_softc *sc) -{ - struct uart_bas *bas; - uint32_t new, old, sig; - uint8_t pvr, star, vstr; - - bas = &sc->sc_bas; - do { - old = sc->sc_hwsig; - sig = old; - uart_lock(sc->sc_hwmtx); - star = uart_getreg(bas, SAB_STAR); - SIGCHG(star & SAB_STAR_CTS, sig, SER_CTS, SER_DCTS); - vstr = uart_getreg(bas, SAB_VSTR); - SIGCHG(vstr & SAB_VSTR_CD, sig, SER_DCD, SER_DDCD); - pvr = ~uart_getreg(bas, SAB_PVR); - switch (bas->chan) { - case 1: - pvr &= SAB_PVR_DSR_A; - break; - case 2: - pvr &= SAB_PVR_DSR_B; - break; - } - SIGCHG(pvr, sig, SER_DSR, SER_DDSR); - uart_unlock(sc->sc_hwmtx); - new = sig & ~SER_MASK_DELTA; - } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); - return (sig); -} - -static int -sab82532_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) -{ - struct uart_bas *bas; - uint8_t dafo, mode; - int error; - - bas = &sc->sc_bas; - error = 0; - uart_lock(sc->sc_hwmtx); - switch (request) { - case UART_IOCTL_BREAK: - dafo = uart_getreg(bas, SAB_DAFO); - if (data) - dafo |= SAB_DAFO_XBRK; - else - dafo &= ~SAB_DAFO_XBRK; - uart_setreg(bas, SAB_DAFO, dafo); - uart_barrier(bas); - break; - case UART_IOCTL_IFLOW: - mode = uart_getreg(bas, SAB_MODE); - if (data) { - mode &= ~SAB_MODE_RTS; - mode |= SAB_MODE_FRTS; - } else { - mode |= SAB_MODE_RTS; - mode &= ~SAB_MODE_FRTS; - } - uart_setreg(bas, SAB_MODE, mode); - uart_barrier(bas); - break; - case UART_IOCTL_OFLOW: - mode = uart_getreg(bas, SAB_MODE); - if (data) - mode &= ~SAB_MODE_FCTS; - else - mode |= SAB_MODE_FCTS; - uart_setreg(bas, SAB_MODE, mode); - uart_barrier(bas); - break; - default: - error = EINVAL; - break; - } - uart_unlock(sc->sc_hwmtx); - return (error); -} - -static int -sab82532_bus_ipend(struct uart_softc *sc) -{ - struct uart_bas *bas; - int ipend; - uint8_t isr0, isr1; - - bas = &sc->sc_bas; - uart_lock(sc->sc_hwmtx); - isr0 = uart_getreg(bas, SAB_ISR0); - isr1 = uart_getreg(bas, SAB_ISR1); - uart_barrier(bas); - if (isr0 & SAB_ISR0_TIME) { - while (uart_getreg(bas, SAB_STAR) & SAB_STAR_CEC) - ; - uart_setreg(bas, SAB_CMDR, SAB_CMDR_RFRD); - uart_barrier(bas); - } - uart_unlock(sc->sc_hwmtx); - - ipend = 0; - if (isr1 & SAB_ISR1_BRKT) - ipend |= SER_INT_BREAK; - if (isr0 & SAB_ISR0_RFO) - ipend |= SER_INT_OVERRUN; - if (isr0 & (SAB_ISR0_TCD|SAB_ISR0_RPF)) - ipend |= SER_INT_RXREADY; - if ((isr0 & SAB_ISR0_CDSC) || (isr1 & SAB_ISR1_CSC)) - ipend |= SER_INT_SIGCHG; - if (isr1 & SAB_ISR1_ALLS) - ipend |= SER_INT_TXIDLE; - - return (ipend); -} - -static int -sab82532_bus_param(struct uart_softc *sc, int baudrate, int databits, - int stopbits, int parity) -{ - struct uart_bas *bas; - int error; - - bas = &sc->sc_bas; - uart_lock(sc->sc_hwmtx); - error = sab82532_param(bas, baudrate, databits, stopbits, parity); - uart_unlock(sc->sc_hwmtx); - return (error); -} - -static int -sab82532_bus_probe(struct uart_softc *sc) -{ - char buf[80]; - const char *vstr; - int error; - char ch; - - error = sab82532_probe(&sc->sc_bas); - if (error) - return (error); - - sc->sc_rxfifosz = 32; - sc->sc_txfifosz = 32; - - ch = sc->sc_bas.chan - 1 + 'A'; - - switch (uart_getreg(&sc->sc_bas, SAB_VSTR) & SAB_VSTR_VMASK) { - case SAB_VSTR_V_1: - vstr = "v1"; - break; - case SAB_VSTR_V_2: - vstr = "v2"; - break; - case SAB_VSTR_V_32: - vstr = "v3.2"; - sc->sc_hwiflow = 0; /* CTS doesn't work with RFC:RFDF. */ - sc->sc_hwoflow = 1; - break; - default: - vstr = "v4?"; - break; - } - - snprintf(buf, sizeof(buf), "SAB 82532 %s, channel %c", vstr, ch); - device_set_desc_copy(sc->sc_dev, buf); - return (0); -} - -static int -sab82532_bus_receive(struct uart_softc *sc) -{ - struct uart_bas *bas; - int i, rbcl, xc; - uint8_t s; - - bas = &sc->sc_bas; - uart_lock(sc->sc_hwmtx); - if (uart_getreg(bas, SAB_STAR) & SAB_STAR_RFNE) { - rbcl = uart_getreg(bas, SAB_RBCL) & 31; - if (rbcl == 0) - rbcl = 32; - for (i = 0; i < rbcl; i += 2) { - if (uart_rx_full(sc)) { - sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; - break; - } - xc = uart_getreg(bas, SAB_RFIFO); - s = uart_getreg(bas, SAB_RFIFO + 1); - if (s & SAB_RSTAT_FE) - xc |= UART_STAT_FRAMERR; - if (s & SAB_RSTAT_PE) - xc |= UART_STAT_PARERR; - uart_rx_put(sc, xc); - } - } - - while (uart_getreg(bas, SAB_STAR) & SAB_STAR_CEC) - ; - uart_setreg(bas, SAB_CMDR, SAB_CMDR_RMC); - uart_barrier(bas); - uart_unlock(sc->sc_hwmtx); - return (0); -} - -static int -sab82532_bus_setsig(struct uart_softc *sc, int sig) -{ - struct uart_bas *bas; - uint32_t new, old; - uint8_t mode, pvr; - - bas = &sc->sc_bas; - do { - old = sc->sc_hwsig; - new = old; - if (sig & SER_DDTR) { - SIGCHG(sig & SER_DTR, new, SER_DTR, - SER_DDTR); - } - if (sig & SER_DRTS) { - SIGCHG(sig & SER_RTS, new, SER_RTS, - SER_DRTS); - } - } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); - - uart_lock(sc->sc_hwmtx); - /* Set DTR pin. */ - pvr = uart_getreg(bas, SAB_PVR); - switch (bas->chan) { - case 1: - if (new & SER_DTR) - pvr &= ~SAB_PVR_DTR_A; - else - pvr |= SAB_PVR_DTR_A; - break; - case 2: - if (new & SER_DTR) - pvr &= ~SAB_PVR_DTR_B; - else - pvr |= SAB_PVR_DTR_B; - break; - } - uart_setreg(bas, SAB_PVR, pvr); - - /* Set RTS pin. */ - mode = uart_getreg(bas, SAB_MODE); - if (new & SER_RTS) - mode &= ~SAB_MODE_FRTS; - else - mode |= SAB_MODE_FRTS; - uart_setreg(bas, SAB_MODE, mode); - uart_barrier(bas); - uart_unlock(sc->sc_hwmtx); - return (0); -} - -static int -sab82532_bus_transmit(struct uart_softc *sc) -{ - struct uart_bas *bas; - int i; - - bas = &sc->sc_bas; - uart_lock(sc->sc_hwmtx); - while (!(uart_getreg(bas, SAB_STAR) & SAB_STAR_XFW)) - ; - for (i = 0; i < sc->sc_txdatasz; i++) - uart_setreg(bas, SAB_XFIFO + i, sc->sc_txbuf[i]); - uart_barrier(bas); - while (uart_getreg(bas, SAB_STAR) & SAB_STAR_CEC) - ; - uart_setreg(bas, SAB_CMDR, SAB_CMDR_XF); - sc->sc_txbusy = 1; - uart_unlock(sc->sc_hwmtx); - return (0); -} - -static void -sab82532_bus_grab(struct uart_softc *sc) -{ - struct uart_bas *bas; - uint8_t imr0; - - bas = &sc->sc_bas; - imr0 = SAB_IMR0_TIME|SAB_IMR0_CDSC|SAB_IMR0_RFO; /* No TCD or RPF */ - uart_lock(sc->sc_hwmtx); - uart_setreg(bas, SAB_IMR0, 0xff & ~imr0); - uart_barrier(bas); - uart_unlock(sc->sc_hwmtx); -} - -static void -sab82532_bus_ungrab(struct uart_softc *sc) -{ - struct uart_bas *bas; - uint8_t imr0; - - bas = &sc->sc_bas; - imr0 = SAB_IMR0_TCD|SAB_IMR0_TIME|SAB_IMR0_CDSC|SAB_IMR0_RFO| - SAB_IMR0_RPF; - uart_lock(sc->sc_hwmtx); - uart_setreg(bas, SAB_IMR0, 0xff & ~imr0); - uart_barrier(bas); - uart_unlock(sc->sc_hwmtx); -} diff --git a/sys/dev/uart/uart_kbd_sun.c b/sys/dev/uart/uart_kbd_sun.c deleted file mode 100644 index 8850afa52c4..00000000000 --- a/sys/dev/uart/uart_kbd_sun.c +++ /dev/null @@ -1,868 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2003 Jake Burkholder. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include - -#include "opt_kbd.h" -#include "opt_sunkbd.h" - -#if (defined(SUNKBD_EMULATE_ATKBD) && defined(SUNKBD_DFLT_KEYMAP)) || \ - !defined(SUNKBD_EMULATE_ATKBD) -#define KBD_DFLT_KEYMAP -#endif - -#include -#include -#include -#include -#include -#include -#include - -#include - -#include -#include - -#include -#include -#include - -#include -#if !defined(SUNKBD_EMULATE_ATKBD) -#include -#endif - -#if defined(SUNKBD_EMULATE_ATKBD) && defined(SUNKBD_DFLT_KEYMAP) -#include "sunkbdmap.h" -#endif -#include "uart_if.h" - -#define SUNKBD_DRIVER_NAME "sunkbd" - -#define TODO printf("%s: unimplemented", __func__) - -struct sunkbd_softc { - keyboard_t sc_kbd; - struct uart_softc *sc_uart; - struct uart_devinfo *sc_sysdev; - - struct callout sc_repeat_callout; - int sc_repeat_key; - - int sc_accents; - int sc_composed_char; - int sc_flags; -#define KPCOMPOSE (1 << 0) - int sc_mode; - int sc_polling; - int sc_repeating; - int sc_state; - -#if defined(SUNKBD_EMULATE_ATKBD) - int sc_buffered_char[2]; -#endif -}; - -static int sunkbd_configure(int flags); -static int sunkbd_probe_keyboard(struct uart_devinfo *di); - -static int sunkbd_probe(int unit, void *arg, int flags); -static int sunkbd_init(int unit, keyboard_t **kbdp, void *arg, int flags); -static int sunkbd_term(keyboard_t *kbd); -static int sunkbd_intr(keyboard_t *kbd, void *arg); -static int sunkbd_test_if(keyboard_t *kbd); -static int sunkbd_enable(keyboard_t *kbd); -static int sunkbd_disable(keyboard_t *kbd); -static int sunkbd_read(keyboard_t *kbd, int wait); -static int sunkbd_check(keyboard_t *kbd); -static u_int sunkbd_read_char(keyboard_t *kbd, int wait); -static int sunkbd_check_char(keyboard_t *kbd); -static int sunkbd_ioctl(keyboard_t *kbd, u_long cmd, caddr_t data); -static int sunkbd_lock(keyboard_t *kbd, int lock); -static void sunkbd_clear_state(keyboard_t *kbd); -static int sunkbd_get_state(keyboard_t *kbd, void *buf, size_t len); -static int sunkbd_set_state(keyboard_t *kbd, void *buf, size_t len); -static int sunkbd_poll_mode(keyboard_t *kbd, int on); -static void sunkbd_diag(keyboard_t *kbd, int level); - -static void sunkbd_repeat(void *v); -#if defined(SUNKBD_EMULATE_ATKBD) -static int keycode2scancode(int keycode, int shift, int up); -#endif - -static keyboard_switch_t sunkbdsw = { - .probe = sunkbd_probe, - .init = sunkbd_init, - .term = sunkbd_term, - .intr = sunkbd_intr, - .test_if = sunkbd_test_if, - .enable = sunkbd_enable, - .disable = sunkbd_disable, - .read = sunkbd_read, - .check = sunkbd_check, - .read_char = sunkbd_read_char, - .check_char = sunkbd_check_char, - .ioctl = sunkbd_ioctl, - .lock = sunkbd_lock, - .clear_state = sunkbd_clear_state, - .get_state = sunkbd_get_state, - .set_state = sunkbd_set_state, - .poll = sunkbd_poll_mode, - .diag = sunkbd_diag -}; - -KEYBOARD_DRIVER(sunkbd, sunkbdsw, sunkbd_configure); - -static struct sunkbd_softc sunkbd_softc; -static struct uart_devinfo uart_keyboard; - -#if defined(SUNKBD_EMULATE_ATKBD) - -#define SCAN_PRESS 0x000 -#define SCAN_RELEASE 0x080 -#define SCAN_PREFIX_E0 0x100 -#define SCAN_PREFIX_E1 0x200 -#define SCAN_PREFIX_CTL 0x400 -#define SCAN_PREFIX_SHIFT 0x800 -#define SCAN_PREFIX (SCAN_PREFIX_E0 | SCAN_PREFIX_E1 | \ - SCAN_PREFIX_CTL | SCAN_PREFIX_SHIFT) - -#define NOTR 0x0 /* no translation */ - -static const uint8_t sunkbd_trtab[] = { - NOTR, 0x6d, 0x78, 0x6e, 0x79, 0x3b, 0x3c, 0x44, /* 0x00 - 0x07 */ - 0x3d, 0x57, 0x3e, 0x58, 0x3f, 0x5d, 0x40, NOTR, /* 0x08 - 0x0f */ - 0x41, 0x42, 0x43, 0x38, 0x5f, 0x68, 0x5c, 0x46, /* 0x10 - 0x17 */ - 0x61, 0x6f, 0x70, 0x64, 0x62, 0x01, 0x02, 0x03, /* 0x18 - 0x1f */ - 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, /* 0x20 - 0x27 */ - 0x0c, 0x0d, 0x29, 0x0e, 0x66, 0x77, 0x5b, 0x37, /* 0x28 - 0x2f */ - 0x7a, 0x71, 0x53, 0x74, 0x5e, 0x0f, 0x10, 0x11, /* 0x30 - 0x37 */ - 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, /* 0x38 - 0x3f */ - 0x1a, 0x1b, 0x67, 0x6b, 0x47, 0x48, 0x49, 0x4a, /* 0x40 - 0x47 */ - 0x73, 0x72, 0x63, NOTR, 0x1d, 0x1e, 0x1f, 0x20, /* 0x48 - 0x4f */ - 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, /* 0x50 - 0x57 */ - 0x2b, 0x1c, 0x59, 0x4b, 0x4c, 0x4d, 0x52, 0x75, /* 0x58 - 0x5f */ - 0x60, 0x76, 0x45, 0x2a, 0x2c, 0x2d, 0x2e, 0x2f, /* 0x60 - 0x67 */ - 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, NOTR, /* 0x68 - 0x6f */ - 0x4f, 0x50, 0x51, NOTR, NOTR, NOTR, 0x6c, 0x3a, /* 0x70 - 0x77 */ - 0x69, 0x39, 0x6a, 0x65, 0x56, 0x4e, NOTR, NOTR /* 0x78 - 0x7f */ -}; - -#endif - -static int -sunkbd_probe_keyboard(struct uart_devinfo *di) -{ - int c, id, ltries, tries; - - for (tries = 5; tries != 0; tries--) { - uart_putc(di, SKBD_CMD_RESET); - for (ltries = 1000; ltries != 0; ltries--) { - if (uart_poll(di) == SKBD_RSP_RESET) - break; - DELAY(1000); - } - if (ltries == 0) - continue; - id = -1; - for (ltries = 1000; ltries != 0; ltries--) { - switch (c = uart_poll(di)) { - case -1: - break; - case SKBD_RSP_IDLE: - return (id); - default: - id = c; - } - DELAY(1000); - } - } - return (-1); -} - -static int sunkbd_attach(struct uart_softc *sc); -static void sunkbd_uart_intr(void *arg); - -static int -sunkbd_configure(int flags) -{ - struct sunkbd_softc *sc; - - /* - * We are only prepared to be used for the high-level console - * when the keyboard is both configured and attached. - */ - if (!(flags & KB_CONF_PROBE_ONLY)) { - if (KBD_IS_INITIALIZED(&sunkbd_softc.sc_kbd)) - goto found; - else - return (0); - } - - if (uart_cpu_getdev(UART_DEV_KEYBOARD, &uart_keyboard)) - return (0); - if (uart_probe(&uart_keyboard)) - return (0); - uart_init(&uart_keyboard); - - uart_keyboard.type = UART_DEV_KEYBOARD; - uart_keyboard.attach = sunkbd_attach; - uart_add_sysdev(&uart_keyboard); - - if (sunkbd_probe_keyboard(&uart_keyboard) != KB_SUN4) - return (0); - - sc = &sunkbd_softc; - callout_init(&sc->sc_repeat_callout, 0); - sunkbd_clear_state(&sc->sc_kbd); - -#if defined(SUNKBD_EMULATE_ATKBD) - kbd_init_struct(&sc->sc_kbd, SUNKBD_DRIVER_NAME, KB_101, 0, 0, 0, 0); - kbd_set_maps(&sc->sc_kbd, &key_map, &accent_map, fkey_tab, - sizeof(fkey_tab) / sizeof(fkey_tab[0])); -#else - kbd_init_struct(&sc->sc_kbd, SUNKBD_DRIVER_NAME, KB_OTHER, 0, 0, 0, 0); - kbd_set_maps(&sc->sc_kbd, &keymap_sun_us_unix_kbd, - &accentmap_sun_us_unix_kbd, fkey_tab, - sizeof(fkey_tab) / sizeof(fkey_tab[0])); -#endif - sc->sc_mode = K_XLATE; - kbd_register(&sc->sc_kbd); - - sc->sc_sysdev = &uart_keyboard; - - found: - /* Return number of found keyboards. */ - return (1); -} - -static int -sunkbd_attach(struct uart_softc *sc) -{ - - /* - * Don't attach if we didn't probe the keyboard. Note that - * the UART is still marked as a system device in that case. - */ - if (sunkbd_softc.sc_sysdev == NULL) { - device_printf(sc->sc_dev, "keyboard not present\n"); - return (0); - } - - if (sc->sc_sysdev != NULL) { - sunkbd_softc.sc_uart = sc; - -#ifdef KBD_INSTALL_CDEV - kbd_attach(&sunkbd_softc.sc_kbd); -#endif - sunkbd_enable(&sunkbd_softc.sc_kbd); - - swi_add(&tty_intr_event, uart_driver_name, sunkbd_uart_intr, - &sunkbd_softc, SWI_TTY, INTR_TYPE_TTY, &sc->sc_softih); - - sc->sc_opened = 1; - KBD_INIT_DONE(&sunkbd_softc.sc_kbd); - } - - return (0); -} - -static void -sunkbd_uart_intr(void *arg) -{ - struct sunkbd_softc *sc = arg; - int pend; - - if (sc->sc_uart->sc_leaving) - return; - - pend = atomic_readandclear_32(&sc->sc_uart->sc_ttypend); - if (!(pend & SER_INT_MASK)) - return; - - if (pend & SER_INT_RXREADY) { - if (KBD_IS_ACTIVE(&sc->sc_kbd) && KBD_IS_BUSY(&sc->sc_kbd)) { - sc->sc_kbd.kb_callback.kc_func(&sc->sc_kbd, - KBDIO_KEYINPUT, sc->sc_kbd.kb_callback.kc_arg); - } - } -} - -static int -sunkbd_probe(int unit, void *arg, int flags) -{ - - TODO; - return (0); -} - -static int -sunkbd_init(int unit, keyboard_t **kbdp, void *arg, int flags) -{ - - TODO; - return (0); -} - -static int -sunkbd_term(keyboard_t *kbd) -{ - - TODO; - return (0); -} - -static int -sunkbd_intr(keyboard_t *kbd, void *arg) -{ - - TODO; - return (0); -} - -static int -sunkbd_test_if(keyboard_t *kbd) -{ - - TODO; - return (0); -} - -static int -sunkbd_enable(keyboard_t *kbd) -{ - - KBD_ACTIVATE(kbd); - return (0); -} - -static int -sunkbd_disable(keyboard_t *kbd) -{ - - KBD_DEACTIVATE(kbd); - return (0); -} - -static int -sunkbd_read(keyboard_t *kbd, int wait) -{ - - TODO; - return (0); -} - -static int -sunkbd_check(keyboard_t *kbd) -{ - struct sunkbd_softc *sc; - - if (!KBD_IS_ACTIVE(kbd)) - return (FALSE); - - sc = (struct sunkbd_softc *)kbd; - -#if defined(SUNKBD_EMULATE_ATKBD) - if (sc->sc_buffered_char[0]) - return (TRUE); -#endif - - if (sc->sc_repeating) - return (TRUE); - - if (sc->sc_uart != NULL && !uart_rx_empty(sc->sc_uart)) - return (TRUE); - - if (sc->sc_polling != 0 && sc->sc_sysdev != NULL && - uart_rxready(sc->sc_sysdev)) - return (TRUE); - - return (FALSE); -} - -static u_int -sunkbd_read_char(keyboard_t *kbd, int wait) -{ - struct sunkbd_softc *sc; - int key, release, repeated, suncode; - - sc = (struct sunkbd_softc *)kbd; - -#if defined(SUNKBD_EMULATE_ATKBD) - if (sc->sc_mode == K_RAW && sc->sc_buffered_char[0]) { - key = sc->sc_buffered_char[0]; - if (key & SCAN_PREFIX) { - sc->sc_buffered_char[0] = key & ~SCAN_PREFIX; - return ((key & SCAN_PREFIX_E0) ? 0xe0 : 0xe1); - } else { - sc->sc_buffered_char[0] = sc->sc_buffered_char[1]; - sc->sc_buffered_char[1] = 0; - return (key); - } - } -#endif - - repeated = 0; - if (sc->sc_repeating) { - repeated = 1; - sc->sc_repeating = 0; - callout_reset(&sc->sc_repeat_callout, hz / 10, - sunkbd_repeat, sc); - suncode = sc->sc_repeat_key; - goto process_code; - } - - for (;;) { - next_code: - if (!(sc->sc_flags & KPCOMPOSE) && (sc->sc_composed_char > 0)) { - key = sc->sc_composed_char; - sc->sc_composed_char = 0; - if (key > UCHAR_MAX) - return (ERRKEY); - return (key); - } - - if (sc->sc_uart != NULL && !uart_rx_empty(sc->sc_uart)) { - suncode = uart_rx_get(sc->sc_uart); - } else if (sc->sc_polling != 0 && sc->sc_sysdev != NULL) { - if (wait) - suncode = uart_getc(sc->sc_sysdev); - else if ((suncode = uart_poll(sc->sc_sysdev)) == -1) - return (NOKEY); - } else { - return (NOKEY); - } - - switch (suncode) { - case SKBD_RSP_IDLE: - break; - default: - process_code: - ++kbd->kb_count; - key = SKBD_KEY_CHAR(suncode); - release = suncode & SKBD_KEY_RELEASE; - if (!repeated) { - if (release == 0) { - callout_reset(&sc->sc_repeat_callout, - hz / 2, sunkbd_repeat, sc); - sc->sc_repeat_key = suncode; - } else if (sc->sc_repeat_key == key) { - callout_stop(&sc->sc_repeat_callout); - sc->sc_repeat_key = -1; - } - } - -#if defined(SUNKBD_EMULATE_ATKBD) - key = sunkbd_trtab[key]; - if (key == NOTR) - return (NOKEY); - - if (!repeated) { - switch (key) { - case 0x1d: /* ctrl */ - if (release != 0) - sc->sc_flags &= ~CTLS; - else - sc->sc_flags |= CTLS; - break; - case 0x2a: /* left shift */ - case 0x36: /* right shift */ - if (release != 0) - sc->sc_flags &= ~SHIFTS; - else - sc->sc_flags |= SHIFTS; - break; - case 0x38: /* alt */ - case 0x5d: /* altgr */ - if (release != 0) - sc->sc_flags &= ~ALTS; - else - sc->sc_flags |= ALTS; - break; - } - } - if (sc->sc_mode == K_RAW) { - key = keycode2scancode(key, sc->sc_flags, - release); - if (key & SCAN_PREFIX) { - if (key & SCAN_PREFIX_CTL) { - sc->sc_buffered_char[0] = - 0x1d | (key & SCAN_RELEASE); - sc->sc_buffered_char[1] = - key & ~SCAN_PREFIX; - } else if (key & SCAN_PREFIX_SHIFT) { - sc->sc_buffered_char[0] = - 0x2a | (key & SCAN_RELEASE); - sc->sc_buffered_char[1] = - key & ~SCAN_PREFIX_SHIFT; - } else { - sc->sc_buffered_char[0] = - key & ~SCAN_PREFIX; - sc->sc_buffered_char[1] = 0; - } - return ((key & SCAN_PREFIX_E0) ? - 0xe0 : 0xe1); - } - return (key); - } - switch (key) { - case 0x5c: /* print screen */ - if (sc->sc_flags & ALTS) - key = 0x54; /* sysrq */ - break; - case 0x68: /* pause/break */ - if (sc->sc_flags & CTLS) - key = 0x6c; /* break */ - break; - } - - if (sc->sc_mode == K_CODE) - return (key | release); -#else - if (sc->sc_mode == K_RAW || sc->sc_mode == K_CODE) - return (suncode); -#endif - -#if defined(SUNKBD_EMULATE_ATKBD) - if (key == 0x38) { /* left alt (KP compose key) */ -#else - if (key == 0x13) { /* left alt (KP compose key) */ -#endif - if (release != 0) { - if (sc->sc_flags & KPCOMPOSE) { - sc->sc_flags &= ~KPCOMPOSE; - if (sc->sc_composed_char > - UCHAR_MAX) - sc->sc_composed_char = - 0; - } - } else { - if (!(sc->sc_flags & KPCOMPOSE)) { - sc->sc_flags |= KPCOMPOSE; - sc->sc_composed_char = 0; - } - } - } - if (sc->sc_flags & KPCOMPOSE) { - switch (suncode) { - case 0x44: /* KP 7 */ - case 0x45: /* KP 8 */ - case 0x46: /* KP 9 */ - sc->sc_composed_char *= 10; - sc->sc_composed_char += suncode - 0x3d; - if (sc->sc_composed_char > UCHAR_MAX) - return (ERRKEY); - goto next_code; - case 0x5b: /* KP 4 */ - case 0x5c: /* KP 5 */ - case 0x5d: /* KP 6 */ - sc->sc_composed_char *= 10; - sc->sc_composed_char += suncode - 0x58; - if (sc->sc_composed_char > UCHAR_MAX) - return (ERRKEY); - goto next_code; - case 0x70: /* KP 1 */ - case 0x71: /* KP 2 */ - case 0x72: /* KP 3 */ - sc->sc_composed_char *= 10; - sc->sc_composed_char += suncode - 0x6f; - if (sc->sc_composed_char > UCHAR_MAX) - return (ERRKEY); - goto next_code; - case 0x5e: /* KP 0 */ - sc->sc_composed_char *= 10; - if (sc->sc_composed_char > UCHAR_MAX) - return (ERRKEY); - goto next_code; - - case 0x44 | SKBD_KEY_RELEASE: /* KP 7 */ - case 0x45 | SKBD_KEY_RELEASE: /* KP 8 */ - case 0x46 | SKBD_KEY_RELEASE: /* KP 9 */ - case 0x5b | SKBD_KEY_RELEASE: /* KP 4 */ - case 0x5c | SKBD_KEY_RELEASE: /* KP 5 */ - case 0x5d | SKBD_KEY_RELEASE: /* KP 6 */ - case 0x70 | SKBD_KEY_RELEASE: /* KP 1 */ - case 0x71 | SKBD_KEY_RELEASE: /* KP 2 */ - case 0x72 | SKBD_KEY_RELEASE: /* KP 3 */ - case 0x5e | SKBD_KEY_RELEASE: /* KP 0 */ - goto next_code; - default: - if (sc->sc_composed_char > 0) { - sc->sc_flags &= ~KPCOMPOSE; - sc->sc_composed_char = 0; - return (ERRKEY); - } - } - } - - key = genkbd_keyaction(kbd, key, release, - &sc->sc_state, &sc->sc_accents); - if (key != NOKEY || repeated) - return (key); - } - } - return (0); -} - -static int -sunkbd_check_char(keyboard_t *kbd) -{ - struct sunkbd_softc *sc; - - if (!KBD_IS_ACTIVE(kbd)) - return (FALSE); - - sc = (struct sunkbd_softc *)kbd; - if (!(sc->sc_flags & KPCOMPOSE) && (sc->sc_composed_char > 0)) - return (TRUE); - - return (sunkbd_check(kbd)); -} - -static int -sunkbd_ioctl(keyboard_t *kbd, u_long cmd, caddr_t data) -{ - struct sunkbd_softc *sc; - int c, error; -#if defined(COMPAT_FREEBSD6) || defined(COMPAT_FREEBSD5) - int ival; -#endif - - sc = (struct sunkbd_softc *)kbd; - error = 0; - switch (cmd) { - case KDGKBMODE: - *(int *)data = sc->sc_mode; - break; -#if defined(COMPAT_FREEBSD6) || defined(COMPAT_FREEBSD5) - case _IO('K', 7): - ival = IOCPARM_IVAL(data); - data = (caddr_t)&ival; - /* FALLTHROUGH */ -#endif - case KDSKBMODE: - switch (*(int *)data) { - case K_XLATE: - if (sc->sc_mode != K_XLATE) { - /* make lock key state and LED state match */ - sc->sc_state &= ~LOCK_MASK; - sc->sc_state |= KBD_LED_VAL(kbd); - } - /* FALLTHROUGH */ - case K_RAW: - case K_CODE: - if (sc->sc_mode != *(int *)data) { - sunkbd_clear_state(kbd); - sc->sc_mode = *(int *)data; - } - break; - default: - error = EINVAL; - break; - } - break; - case KDGETLED: - *(int *)data = KBD_LED_VAL(kbd); - break; -#if defined(COMPAT_FREEBSD6) || defined(COMPAT_FREEBSD5) - case _IO('K', 66): - ival = IOCPARM_IVAL(data); - data = (caddr_t)&ival; - /* FALLTHROUGH */ -#endif - case KDSETLED: - if (*(int *)data & ~LOCK_MASK) { - error = EINVAL; - break; - } - if (sc->sc_sysdev == NULL) - break; - c = 0; - if (*(int *)data & CLKED) - c |= SKBD_LED_CAPSLOCK; - if (*(int *)data & NLKED) - c |= SKBD_LED_NUMLOCK; - if (*(int *)data & SLKED) - c |= SKBD_LED_SCROLLLOCK; - uart_lock(sc->sc_sysdev->hwmtx); - sc->sc_sysdev->ops->putc(&sc->sc_sysdev->bas, SKBD_CMD_SETLED); - sc->sc_sysdev->ops->putc(&sc->sc_sysdev->bas, c); - uart_unlock(sc->sc_sysdev->hwmtx); - KBD_LED_VAL(kbd) = *(int *)data; - break; - case KDGKBSTATE: - *(int *)data = sc->sc_state & LOCK_MASK; - break; -#if defined(COMPAT_FREEBSD6) || defined(COMPAT_FREEBSD5) - case _IO('K', 20): - ival = IOCPARM_IVAL(data); - data = (caddr_t)&ival; - /* FALLTHROUGH */ -#endif - case KDSKBSTATE: - if (*(int *)data & ~LOCK_MASK) { - error = EINVAL; - break; - } - sc->sc_state &= ~LOCK_MASK; - sc->sc_state |= *(int *)data; - /* set LEDs and quit */ - return (sunkbd_ioctl(kbd, KDSETLED, data)); - case KDSETREPEAT: - case KDSETRAD: - break; - case PIO_KEYMAP: - case OPIO_KEYMAP: - case PIO_KEYMAPENT: - case PIO_DEADKEYMAP: - default: - return (genkbd_commonioctl(kbd, cmd, data)); - } - return (error); -} - -static int -sunkbd_lock(keyboard_t *kbd, int lock) -{ - - TODO; - return (0); -} - -static void -sunkbd_clear_state(keyboard_t *kbd) -{ - struct sunkbd_softc *sc; - - sc = (struct sunkbd_softc *)kbd; - sc->sc_repeat_key = -1; - sc->sc_accents = 0; - sc->sc_composed_char = 0; - sc->sc_flags = 0; - sc->sc_polling = 0; - sc->sc_repeating = 0; - sc->sc_state &= LOCK_MASK; /* Preserve locking key state. */ - -#if defined(SUNKBD_EMULATE_ATKBD) - sc->sc_buffered_char[0] = 0; - sc->sc_buffered_char[1] = 0; -#endif -} - -static int -sunkbd_get_state(keyboard_t *kbd, void *buf, size_t len) -{ - - TODO; - return (0); -} - -static int -sunkbd_set_state(keyboard_t *kbd, void *buf, size_t len) -{ - - TODO; - return (0); -} - -static int -sunkbd_poll_mode(keyboard_t *kbd, int on) -{ - struct sunkbd_softc *sc; - - sc = (struct sunkbd_softc *)kbd; - if (on) - sc->sc_polling++; - else - sc->sc_polling--; - return (0); -} - -static void -sunkbd_diag(keyboard_t *kbd, int level) -{ - - TODO; -} - -static void -sunkbd_repeat(void *v) -{ - struct sunkbd_softc *sc = v; - - if (KBD_IS_ACTIVE(&sc->sc_kbd) && KBD_IS_BUSY(&sc->sc_kbd)) { - if (sc->sc_repeat_key != -1) { - sc->sc_repeating = 1; - sc->sc_kbd.kb_callback.kc_func(&sc->sc_kbd, - KBDIO_KEYINPUT, sc->sc_kbd.kb_callback.kc_arg); - } - } -} - -#if defined(SUNKBD_EMULATE_ATKBD) -static int -keycode2scancode(int keycode, int shift, int up) -{ - static const int scan[] = { - /* KP enter, right ctrl, KP divide */ - 0x1c , 0x1d , 0x35 , - /* print screen */ - 0x37 | SCAN_PREFIX_SHIFT, - /* right alt, home, up, page up, left, right, end */ - 0x38, 0x47, 0x48, 0x49, 0x4b, 0x4d, 0x4f, - /* down, page down, insert, delete */ - 0x50, 0x51, 0x52, 0x53, - /* pause/break (see also below) */ - 0x46, - /* - * MS: left window, right window, menu - * also Sun: left meta, right meta, compose - */ - 0x5b, 0x5c, 0x5d, - /* Sun type 6 USB */ - /* help, stop, again, props, undo, front, copy */ - 0x68, 0x5e, 0x5f, 0x60, 0x61, 0x62, 0x63, - /* open, paste, find, cut, audiomute, audiolower, audioraise */ - 0x64, 0x65, 0x66, 0x67, 0x25, 0x1f, 0x1e, - /* power */ - 0x20 - }; - int scancode; - - scancode = keycode; - if ((keycode >= 89) && (keycode < 89 + nitems(scan))) - scancode = scan[keycode - 89] | SCAN_PREFIX_E0; - /* pause/break */ - if ((keycode == 104) && !(shift & CTLS)) - scancode = 0x45 | SCAN_PREFIX_E1 | SCAN_PREFIX_CTL; - if (shift & SHIFTS) - scancode &= ~SCAN_PREFIX_SHIFT; - return (scancode | (up ? SCAN_RELEASE : SCAN_PRESS)); -} -#endif diff --git a/sys/dev/uart/uart_kbd_sun.h b/sys/dev/uart/uart_kbd_sun.h deleted file mode 100644 index 68924817479..00000000000 --- a/sys/dev/uart/uart_kbd_sun.h +++ /dev/null @@ -1,69 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-4-Clause - * - * Copyright (c) 2002 Jason L. Wright (jason@thought.net) - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by Jason L. Wright - * 4. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * Effort sponsored in part by the Defense Advanced Research Projects - * Agency (DARPA) and Air Force Research Laboratory, Air Force - * Materiel Command, USAF, under agreement number F30602-01-2-0537. - * - */ - -/* keyboard commands (host->kbd) */ -#define SKBD_CMD_RESET 0x01 -#define SKBD_CMD_BELLON 0x02 -#define SKBD_CMD_BELLOFF 0x03 -#define SKBD_CMD_CLICKON 0x0a -#define SKBD_CMD_CLICKOFF 0x0b -#define SKBD_CMD_SETLED 0x0e -#define SKBD_CMD_LAYOUT 0x0f - -/* keyboard responses (kbd->host) */ -#define SKBD_RSP_RESET_OK 0x04 /* normal reset status for type 4/5/6 */ -#define SKBD_RSP_IDLE 0x7f /* no keys down */ -#define SKBD_RSP_LAYOUT 0xfe /* layout follows */ -#define SKBD_RSP_RESET 0xff /* reset status follows */ - -#define SKBD_LED_NUMLOCK 0x01 -#define SKBD_LED_COMPOSE 0x02 -#define SKBD_LED_SCROLLLOCK 0x04 -#define SKBD_LED_CAPSLOCK 0x08 - -#define SKBD_STATE_RESET 0 -#define SKBD_STATE_LAYOUT 1 -#define SKBD_STATE_GETKEY 2 - -/* keyboard types */ -#define KB_SUN2 2 /* type 2 keyboard */ -#define KB_SUN3 3 /* type 3 keyboard */ -#define KB_SUN4 4 /* type 4/5/6 keyboard */ - -#define SKBD_KEY_RELEASE 0x80 -#define SKBD_KEY_CHAR(c) ((c) & 0x7f) diff --git a/sys/dev/uart/uart_kbd_sun_tables.h b/sys/dev/uart/uart_kbd_sun_tables.h deleted file mode 100644 index bc4e81d75d9..00000000000 --- a/sys/dev/uart/uart_kbd_sun_tables.h +++ /dev/null @@ -1,143 +0,0 @@ -/* - * Automatically generated from sun.us.unix.kbd. - * DO NOT EDIT! - * - */ -static keymap_t keymap_sun_us_unix_kbd = { 0x80, { -/* alt - * scan cntrl alt alt cntrl - * code base shift cntrl shift alt shift cntrl shift spcl flgs - * --------------------------------------------------------------------------- - */ -/*00*/{{ NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, }, 0xFF,0x00 }, -/*01*/{{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, 0x00,0x00 }, -/*02*/{{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, 0x00,0x00 }, -/*03*/{{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, 0x00,0x00 }, -/*04*/{{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, 0x00,0x00 }, -/*05*/{{ F( 1), F(13), F(25), F(37), S( 1), S(11), S( 1), S(11),}, 0xFF,0x00 }, -/*06*/{{ F( 2), F(14), F(26), F(38), S( 2), S(12), S( 2), S(12),}, 0xFF,0x00 }, -/*07*/{{ F(10), F(22), F(34), F(46), S(10), S(10), S(10), S(10),}, 0xFF,0x00 }, -/*08*/{{ F( 3), F(15), F(27), F(39), S( 3), S(13), S( 3), S(13),}, 0xFF,0x00 }, -/*09*/{{ F(11), F(23), F(35), F(47), S(11), S(11), S(11), S(11),}, 0xFF,0x00 }, -/*0a*/{{ F( 4), F(16), F(28), F(40), S( 4), S(14), S( 4), S(14),}, 0xFF,0x00 }, -/*0b*/{{ F(12), F(24), F(36), F(48), S(12), S(12), S(12), S(12),}, 0xFF,0x00 }, -/*0c*/{{ F( 5), F(17), F(29), F(41), S( 5), S(15), S( 5), S(15),}, 0xFF,0x00 }, -/*0d*/{{ RALT, RALT, RALT, RALT, RALT, RALT, RALT, RALT, }, 0xFF,0x00 }, -/*0e*/{{ F( 6), F(18), F(30), F(42), S( 6), S(16), S( 6), S(16),}, 0xFF,0x00 }, -/*0f*/{{ NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, }, 0xFF,0x00 }, -/*10*/{{ F( 7), F(19), F(31), F(43), S( 7), S( 7), S( 7), S( 7),}, 0xFF,0x00 }, -/*11*/{{ F( 8), F(20), F(32), F(44), S( 8), S( 8), S( 8), S( 8),}, 0xFF,0x00 }, -/*12*/{{ F( 9), F(21), F(33), F(45), S( 9), S( 9), S( 9), S( 9),}, 0xFF,0x00 }, -/*13*/{{ LALT, LALT, LALT, LALT, LALT, LALT, LALT, LALT, }, 0xFF,0x00 }, -/*14*/{{ F(50), F(50), F(50), F(50), F(50), F(50), F(50), F(50),}, 0xFF,0x00 }, -/*15*/{{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, 0x00,0x00 }, -/*16*/{{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, 0x00,0x00 }, -/*17*/{{ SLK, SPSC, SLK, SPSC, SUSP, NOP, SUSP, NOP, }, 0xFF,0x00 }, -/*18*/{{ F(53), F(53), F(53), F(53), F(53), F(53), F(53), F(53),}, 0xFF,0x00 }, -/*19*/{{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, 0x00,0x00 }, -/*1a*/{{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, 0x00,0x00 }, -/*1b*/{{ F(58), F(58), F(58), F(58), F(58), F(58), F(58), F(58),}, 0xFF,0x00 }, -/*1c*/{{ F(55), F(55), F(55), F(55), F(55), F(55), F(55), F(55),}, 0xFF,0x00 }, -/*1d*/{{ 0x1B, 0x1B, 0x1B, 0x1B, 0x1B, 0x1B, DBG, 0x1B, }, 0x02,0x00 }, -/*1e*/{{ '1', '!', NOP, NOP, '1', '!', NOP, NOP, }, 0x33,0x00 }, -/*1f*/{{ '2', '@', 0x00, 0x00, '2', '@', 0x00, 0x00, }, 0x00,0x00 }, -/*20*/{{ '3', '#', NOP, NOP, '3', '#', NOP, NOP, }, 0x33,0x00 }, -/*21*/{{ '4', '$', NOP, NOP, '4', '$', NOP, NOP, }, 0x33,0x00 }, -/*22*/{{ '5', '%', NOP, NOP, '5', '%', NOP, NOP, }, 0x33,0x00 }, -/*23*/{{ '6', '^', 0x1E, 0x1E, '6', '^', 0x1E, 0x1E, }, 0x00,0x00 }, -/*24*/{{ '7', '&', NOP, NOP, '7', '&', NOP, NOP, }, 0x33,0x00 }, -/*25*/{{ '8', '*', NOP, NOP, '8', '*', NOP, NOP, }, 0x33,0x00 }, -/*26*/{{ '9', '(', NOP, NOP, '9', '(', NOP, NOP, }, 0x33,0x00 }, -/*27*/{{ '0', ')', NOP, NOP, '0', ')', NOP, NOP, }, 0x33,0x00 }, -/*28*/{{ '-', '_', 0x1F, 0x1F, '-', '_', 0x1F, 0x1F, }, 0x00,0x00 }, -/*29*/{{ '=', '+', NOP, NOP, '=', '+', NOP, NOP, }, 0x33,0x00 }, -/*2a*/{{ '`', '~', NOP, NOP, '`', '~', DBG, NOP, }, 0x33,0x00 }, -/*2b*/{{ 0x7F, 0x7F, 0x08, 0x08, 0x7F, 0x7F, 0x08, 0x08, }, 0x00,0x00 }, -/*2c*/{{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, 0x00,0x00 }, -/*2d*/{{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, 0x00,0x00 }, -/*2e*/{{ '/', '/', '/', '/', '/', '/', '/', '/', }, 0x00,0x02 }, -/*2f*/{{ '*', '*', '*', '*', '*', '*', '*', '*', }, 0x00,0x00 }, -/*30*/{{ NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, }, 0xFF,0x00 }, -/*31*/{{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, 0x00,0x00 }, -/*32*/{{ 0x08, '.', '.', '.', '.', '.', RBT, RBT, }, 0x03,0x02 }, -/*33*/{{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, 0x00,0x00 }, -/*34*/{{ F(49), F(49), F(49), F(49), F(49), F(49), F(49), F(49),}, 0xFF,0x00 }, -/*35*/{{ 0x09, BTAB, NOP, NOP, 0x09, BTAB, NOP, NOP, }, 0x77,0x00 }, -/*36*/{{ 'q', 'Q', 0x11, 0x11, 'q', 'Q', 0x11, 0x11, }, 0x00,0x01 }, -/*37*/{{ 'w', 'W', 0x17, 0x17, 'w', 'W', 0x17, 0x17, }, 0x00,0x01 }, -/*38*/{{ 'e', 'E', 0x05, 0x05, 'e', 'E', 0x05, 0x05, }, 0x00,0x01 }, -/*39*/{{ 'r', 'R', 0x12, 0x12, 'r', 'R', 0x12, 0x12, }, 0x00,0x01 }, -/*3a*/{{ 't', 'T', 0x14, 0x14, 't', 'T', 0x14, 0x14, }, 0x00,0x01 }, -/*3b*/{{ 'y', 'Y', 0x19, 0x19, 'y', 'Y', 0x19, 0x19, }, 0x00,0x01 }, -/*3c*/{{ 'u', 'U', 0x15, 0x15, 'u', 'U', 0x15, 0x15, }, 0x00,0x01 }, -/*3d*/{{ 'i', 'I', 0x09, 0x09, 'i', 'I', 0x09, 0x09, }, 0x00,0x01 }, -/*3e*/{{ 'o', 'O', 0x0F, 0x0F, 'o', 'O', 0x0F, 0x0F, }, 0x00,0x01 }, -/*3f*/{{ 'p', 'P', 0x10, 0x10, 'p', 'P', 0x10, 0x10, }, 0x00,0x01 }, -/*40*/{{ '[', '{', 0x1B, 0x1B, '[', '{', 0x1B, 0x1B, }, 0x00,0x00 }, -/*41*/{{ ']', '}', 0x1D, 0x1D, ']', '}', 0x1D, 0x1D, }, 0x00,0x00 }, -/*42*/{{ 0x7F, 0x7F, 0x08, 0x08, 0x7F, 0x7F, 0x08, 0x08, }, 0x00,0x00 }, -/*43*/{{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, 0x00,0x00 }, -/*44*/{{ F(49), '7', '7', '7', '7', '7', '7', '7', }, 0x80,0x02 }, -/*45*/{{ F(50), '8', '8', '8', '8', '8', '8', '8', }, 0x80,0x02 }, -/*46*/{{ F(51), '9', '9', '9', '9', '9', '9', '9', }, 0x80,0x02 }, -/*47*/{{ F(52), '-', '-', '-', '-', '-', '-', '-', }, 0x80,0x02 }, -/*48*/{{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, 0x00,0x00 }, -/*49*/{{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, 0x00,0x00 }, -/*4a*/{{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, 0x00,0x00 }, -/*4b*/{{ NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, }, 0xFF,0x00 }, -/*4c*/{{ LCTR, LCTR, LCTR, LCTR, LCTR, LCTR, LCTR, LCTR, }, 0xFF,0x00 }, -/*4d*/{{ 'a', 'A', 0x01, 0x01, 'a', 'A', 0x01, 0x01, }, 0x00,0x01 }, -/*4e*/{{ 's', 'S', 0x13, 0x13, 's', 'S', 0x13, 0x13, }, 0x00,0x01 }, -/*4f*/{{ 'd', 'D', 0x04, 0x04, 'd', 'D', 0x04, 0x04, }, 0x00,0x01 }, -/*50*/{{ 'f', 'F', 0x06, 0x06, 'f', 'F', 0x06, 0x06, }, 0x00,0x01 }, -/*51*/{{ 'g', 'G', 0x07, 0x07, 'g', 'G', 0x07, 0x07, }, 0x00,0x01 }, -/*52*/{{ 'h', 'H', 0x08, 0x08, 'h', 'H', 0x08, 0x08, }, 0x00,0x01 }, -/*53*/{{ 'j', 'J', 0x0A, 0x0A, 'j', 'J', 0x0A, 0x0A, }, 0x00,0x01 }, -/*54*/{{ 'k', 'K', 0x0B, 0x0B, 'k', 'K', 0x0B, 0x0B, }, 0x00,0x01 }, -/*55*/{{ 'l', 'L', 0x0C, 0x0C, 'l', 'L', 0x0C, 0x0C, }, 0x00,0x01 }, -/*56*/{{ ';', ':', NOP, NOP, ';', ':', NOP, NOP, }, 0x33,0x00 }, -/*57*/{{ '\'', '"', NOP, NOP, '\'', '"', NOP, NOP, }, 0x33,0x00 }, -/*58*/{{ '\\', '|', 0x1C, 0x1C, '\\', '|', 0x1C, 0x1C, }, 0x00,0x00 }, -/*59*/{{ 0x0D, 0x0D, 0x0A, 0x0A, 0x0D, 0x0D, 0x0A, 0x0A, }, 0x00,0x00 }, -/*5a*/{{ 0x0D, 0x0D, 0x0A, 0x0A, 0x0D, 0x0D, 0x0A, 0x0A, }, 0x00,0x00 }, -/*5b*/{{ F(53), '4', '4', '4', '4', '4', '4', '4', }, 0x80,0x02 }, -/*5c*/{{ F(54), '5', '5', '5', '5', '5', '5', '5', }, 0x80,0x02 }, -/*5d*/{{ F(55), '6', '6', '6', '6', '6', '6', '6', }, 0x80,0x02 }, -/*5e*/{{ F(60), '0', '0', '0', '0', '0', '0', '0', }, 0x80,0x02 }, -/*5f*/{{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, 0x00,0x00 }, -/*60*/{{ F(51), F(51), F(51), F(51), F(51), F(51), F(51), F(51),}, 0xFF,0x00 }, -/*61*/{{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, 0x00,0x00 }, -/*62*/{{ NLK, NLK, NLK, NLK, NLK, NLK, NLK, NLK, }, 0xFF,0x00 }, -/*63*/{{ LSH, LSH, LSH, LSH, LSH, LSH, LSH, LSH, }, 0xFF,0x00 }, -/*64*/{{ 'z', 'Z', 0x1A, 0x1A, 'z', 'Z', 0x1A, 0x1A, }, 0x00,0x01 }, -/*65*/{{ 'x', 'X', 0x18, 0x18, 'x', 'X', 0x18, 0x18, }, 0x00,0x01 }, -/*66*/{{ 'c', 'C', 0x03, 0x03, 'c', 'C', 0x03, 0x03, }, 0x00,0x01 }, -/*67*/{{ 'v', 'V', 0x16, 0x16, 'v', 'V', 0x16, 0x16, }, 0x00,0x01 }, -/*68*/{{ 'b', 'B', 0x02, 0x02, 'b', 'B', 0x02, 0x02, }, 0x00,0x01 }, -/*69*/{{ 'n', 'N', 0x0E, 0x0E, 'n', 'N', 0x0E, 0x0E, }, 0x00,0x01 }, -/*6a*/{{ 'm', 'M', 0x0D, 0x0D, 'm', 'M', 0x0D, 0x0D, }, 0x00,0x01 }, -/*6b*/{{ ',', '<', NOP, NOP, ',', '<', NOP, NOP, }, 0x33,0x00 }, -/*6c*/{{ '.', '>', NOP, NOP, '.', '>', NOP, NOP, }, 0x33,0x00 }, -/*6d*/{{ '/', '?', NOP, NOP, '/', '?', NOP, NOP, }, 0x33,0x00 }, -/*6e*/{{ RSH, RSH, RSH, RSH, RSH, RSH, RSH, RSH, }, 0xFF,0x00 }, -/*6f*/{{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, 0x00,0x00 }, -/*70*/{{ F(57), '1', '1', '1', '1', '1', '1', '1', }, 0x80,0x02 }, -/*71*/{{ F(58), '2', '2', '2', '2', '2', '2', '2', }, 0x80,0x02 }, -/*72*/{{ F(59), '3', '3', '3', '3', '3', '3', '3', }, 0x80,0x02 }, -/*73*/{{ NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, }, 0xFF,0x00 }, -/*74*/{{ NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, }, 0xFF,0x00 }, -/*75*/{{ NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, }, 0xFF,0x00 }, -/*76*/{{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, 0x00,0x00 }, -/*77*/{{ CLK, CLK, CLK, CLK, CLK, CLK, CLK, CLK, }, 0xFF,0x00 }, -/*78*/{{ META, META, META, META, META, META, META, META, }, 0xFF,0x00 }, -/*79*/{{ ' ', ' ', 0x00, ' ', ' ', ' ', SUSP, ' ', }, 0x02,0x00 }, -/*7a*/{{ META, META, META, META, META, META, META, META, }, 0xFF,0x00 }, -/*7b*/{{ F(59), F(59), F(59), F(59), F(59), F(59), F(59), F(59),}, 0xFF,0x00 }, -/*7c*/{{ NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, }, 0xFF,0x00 }, -/*7d*/{{ F(56), '+', '+', '+', '+', '+', '+', '+', }, 0x80,0x02 }, -/*7e*/{{ NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, }, 0xFF,0x00 }, -/*7f*/{{ NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, }, 0xFF,0x00 }, -} }; - -static accentmap_t accentmap_sun_us_unix_kbd = { 0 }; - diff --git a/sys/dev/usb/controller/ohci_s3c24x0.c b/sys/dev/usb/controller/ohci_s3c24x0.c deleted file mode 100644 index b2c30fd99f4..00000000000 --- a/sys/dev/usb/controller/ohci_s3c24x0.c +++ /dev/null @@ -1,213 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2006 M. Warner Losh. All rights reserved. - * Copyright (c) 2009 Andrew Turner. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include -#include -#include -#include - -#include -#include -#include -#include - -#include - -#include - -static device_probe_t ohci_s3c24x0_probe; -static device_attach_t ohci_s3c24x0_attach; -static device_detach_t ohci_s3c24x0_detach; - -static int -ohci_s3c24x0_probe(device_t dev) -{ - device_set_desc(dev, "S3C24x0 integrated OHCI controller"); - return (BUS_PROBE_DEFAULT); -} - -static int -ohci_s3c24x0_attach(device_t dev) -{ - struct ohci_softc *sc = device_get_softc(dev); - int err; - int rid; - - /* initialise some bus fields */ - sc->sc_bus.parent = dev; - sc->sc_bus.devices = sc->sc_devices; - sc->sc_bus.devices_max = OHCI_MAX_DEVICES; - sc->sc_bus.dma_bits = 32; - - /* get all DMA memory */ - if (usb_bus_mem_alloc_all(&sc->sc_bus, USB_GET_DMA_TAG(dev), - &ohci_iterate_hw_softc)) { - return (ENOMEM); - } - - sc->sc_dev = dev; - - rid = 0; - sc->sc_io_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, - &rid, RF_ACTIVE); - - if (!(sc->sc_io_res)) { - err = ENOMEM; - goto error; - } - sc->sc_io_tag = rman_get_bustag(sc->sc_io_res); - sc->sc_io_hdl = rman_get_bushandle(sc->sc_io_res); - sc->sc_io_size = rman_get_size(sc->sc_io_res); - - rid = 0; - sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, - RF_ACTIVE); - if (!(sc->sc_irq_res)) { - goto error; - } - sc->sc_bus.bdev = device_add_child(dev, "usbus", -1); - if (!(sc->sc_bus.bdev)) { - goto error; - } - device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus); - - strlcpy(sc->sc_vendor, "Samsung", sizeof(sc->sc_vendor)); - - err = bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE, - NULL, (void *)ohci_interrupt, sc, &sc->sc_intr_hdl); - if (err) { - sc->sc_intr_hdl = NULL; - goto error; - } - - bus_space_write_4(sc->sc_io_tag, sc->sc_io_hdl, - OHCI_CONTROL, 0); - - err = ohci_init(sc); - if (!err) { - err = device_probe_and_attach(sc->sc_bus.bdev); - } - if (err) { - goto error; - } - return (0); - -error: - ohci_s3c24x0_detach(dev); - return (ENXIO); -} - -static int -ohci_s3c24x0_detach(device_t dev) -{ - struct ohci_softc *sc = device_get_softc(dev); - int err; - - /* during module unload there are lots of children leftover */ - device_delete_children(dev); - - /* - * Put the controller into reset, then disable clocks and do - * the MI tear down. We have to disable the clocks/hardware - * after we do the rest of the teardown. We also disable the - * clocks in the opposite order we acquire them, but that - * doesn't seem to be absolutely necessary. We free up the - * clocks after we disable them, so the system could, in - * theory, reuse them. - */ - bus_space_write_4(sc->sc_io_tag, sc->sc_io_hdl, - OHCI_CONTROL, 0); - - if (sc->sc_irq_res && sc->sc_intr_hdl) { - /* - * only call ohci_detach() after ohci_init() - */ - ohci_detach(sc); - - err = bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intr_hdl); - sc->sc_intr_hdl = NULL; - } - if (sc->sc_irq_res) { - bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); - sc->sc_irq_res = NULL; - } - if (sc->sc_io_res) { - bus_release_resource(dev, SYS_RES_MEMORY, 0, - sc->sc_io_res); - sc->sc_io_res = NULL; - } - usb_bus_mem_free_all(&sc->sc_bus, &ohci_iterate_hw_softc); - - return (0); -} - -static device_method_t ohci_methods[] = { - /* Device interface */ - DEVMETHOD(device_probe, ohci_s3c24x0_probe), - DEVMETHOD(device_attach, ohci_s3c24x0_attach), - DEVMETHOD(device_detach, ohci_s3c24x0_detach), - DEVMETHOD(device_suspend, bus_generic_suspend), - DEVMETHOD(device_resume, bus_generic_resume), - DEVMETHOD(device_shutdown, bus_generic_shutdown), - - DEVMETHOD_END -}; - -static driver_t ohci_driver = { - .name = "ohci", - .methods = ohci_methods, - .size = sizeof(struct ohci_softc), -}; - -static devclass_t ohci_devclass; - -DRIVER_MODULE(ohci, s3c24x0, ohci_driver, ohci_devclass, 0, 0); -MODULE_DEPEND(ohci, usb, 1, 1, 1); diff --git a/sys/dev/usb/misc/ufm.c b/sys/dev/usb/misc/ufm.c deleted file mode 100644 index 39bd3af2cb2..00000000000 --- a/sys/dev/usb/misc/ufm.c +++ /dev/null @@ -1,340 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2001 M. Warner Losh - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions, and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * This code is based on ugen.c and ulpt.c developed by Lennart Augustsson. - * This code includes software developed by the NetBSD Foundation, Inc. and - * its contributors. - */ - -#include - - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include "usbdevs.h" - -#define USB_DEBUG_VAR usb_debug -#include - -#include - -#define UFM_CMD0 0x00 -#define UFM_CMD_SET_FREQ 0x01 -#define UFM_CMD2 0x02 - -struct ufm_softc { - struct usb_fifo_sc sc_fifo; - struct mtx sc_mtx; - - struct usb_device *sc_udev; - - uint32_t sc_unit; - uint32_t sc_freq; - - uint8_t sc_name[16]; -}; - -/* prototypes */ - -static device_probe_t ufm_probe; -static device_attach_t ufm_attach; -static device_detach_t ufm_detach; - -static usb_fifo_ioctl_t ufm_ioctl; - -static struct usb_fifo_methods ufm_fifo_methods = { - .f_ioctl = &ufm_ioctl, - .basename[0] = "ufm", -}; - -static int ufm_do_req(struct ufm_softc *, uint8_t, uint16_t, uint16_t, - uint8_t *); -static int ufm_set_freq(struct ufm_softc *, void *); -static int ufm_get_freq(struct ufm_softc *, void *); -static int ufm_start(struct ufm_softc *, void *); -static int ufm_stop(struct ufm_softc *, void *); -static int ufm_get_stat(struct ufm_softc *, void *); - -static devclass_t ufm_devclass; - -static device_method_t ufm_methods[] = { - DEVMETHOD(device_probe, ufm_probe), - DEVMETHOD(device_attach, ufm_attach), - DEVMETHOD(device_detach, ufm_detach), - - DEVMETHOD_END -}; - -static driver_t ufm_driver = { - .name = "ufm", - .methods = ufm_methods, - .size = sizeof(struct ufm_softc), -}; - -static const STRUCT_USB_HOST_ID ufm_devs[] = { - {USB_VPI(USB_VENDOR_CYPRESS, USB_PRODUCT_CYPRESS_FMRADIO, 0)}, -}; - -DRIVER_MODULE(ufm, uhub, ufm_driver, ufm_devclass, NULL, 0); -MODULE_DEPEND(ufm, usb, 1, 1, 1); -MODULE_VERSION(ufm, 1); -USB_PNP_HOST_INFO(ufm_devs); - -static int -ufm_probe(device_t dev) -{ - struct usb_attach_arg *uaa = device_get_ivars(dev); - - if (uaa->usb_mode != USB_MODE_HOST) - return (ENXIO); - if (uaa->info.bConfigIndex != 0) - return (ENXIO); - if (uaa->info.bIfaceIndex != 0) - return (ENXIO); - - return (usbd_lookup_id_by_uaa(ufm_devs, sizeof(ufm_devs), uaa)); -} - -static int -ufm_attach(device_t dev) -{ - struct usb_attach_arg *uaa = device_get_ivars(dev); - struct ufm_softc *sc = device_get_softc(dev); - int error; - - sc->sc_udev = uaa->device; - sc->sc_unit = device_get_unit(dev); - - snprintf(sc->sc_name, sizeof(sc->sc_name), "%s", - device_get_nameunit(dev)); - - mtx_init(&sc->sc_mtx, "ufm lock", NULL, MTX_DEF | MTX_RECURSE); - - device_set_usb_desc(dev); - - error = usb_fifo_attach(uaa->device, sc, &sc->sc_mtx, - &ufm_fifo_methods, &sc->sc_fifo, - device_get_unit(dev), -1, uaa->info.bIfaceIndex, - UID_ROOT, GID_OPERATOR, 0644); - if (error) { - goto detach; - } - gone_in_dev(dev, 13, "Driver no longer relevant"); - return (0); /* success */ - -detach: - ufm_detach(dev); - return (ENXIO); -} - -static int -ufm_detach(device_t dev) -{ - struct ufm_softc *sc = device_get_softc(dev); - - usb_fifo_detach(&sc->sc_fifo); - - mtx_destroy(&sc->sc_mtx); - - return (0); -} - -static int -ufm_do_req(struct ufm_softc *sc, uint8_t request, - uint16_t value, uint16_t index, uint8_t *retbuf) -{ - int error; - - struct usb_device_request req; - uint8_t buf[1]; - - req.bmRequestType = UT_READ_VENDOR_DEVICE; - req.bRequest = request; - USETW(req.wValue, value); - USETW(req.wIndex, index); - USETW(req.wLength, 1); - - error = usbd_do_request(sc->sc_udev, NULL, &req, buf); - - if (retbuf) { - *retbuf = buf[0]; - } - if (error) { - return (ENXIO); - } - return (0); -} - -static int -ufm_set_freq(struct ufm_softc *sc, void *addr) -{ - int freq = *(int *)addr; - - /* - * Freq now is in Hz. We need to convert it to the frequency - * that the radio wants. This frequency is 10.7MHz above - * the actual frequency. We then need to convert to - * units of 12.5kHz. We add one to the IFM to make rounding - * easier. - */ - mtx_lock(&sc->sc_mtx); - sc->sc_freq = freq; - mtx_unlock(&sc->sc_mtx); - - freq = (freq + 10700001) / 12500; - - /* This appears to set the frequency */ - if (ufm_do_req(sc, UFM_CMD_SET_FREQ, - freq >> 8, freq, NULL) != 0) { - return (EIO); - } - /* Not sure what this does */ - if (ufm_do_req(sc, UFM_CMD0, - 0x96, 0xb7, NULL) != 0) { - return (EIO); - } - return (0); -} - -static int -ufm_get_freq(struct ufm_softc *sc, void *addr) -{ - int *valp = (int *)addr; - - mtx_lock(&sc->sc_mtx); - *valp = sc->sc_freq; - mtx_unlock(&sc->sc_mtx); - return (0); -} - -static int -ufm_start(struct ufm_softc *sc, void *addr) -{ - uint8_t ret; - - if (ufm_do_req(sc, UFM_CMD0, - 0x00, 0xc7, &ret)) { - return (EIO); - } - if (ufm_do_req(sc, UFM_CMD2, - 0x01, 0x00, &ret)) { - return (EIO); - } - if (ret & 0x1) { - return (EIO); - } - return (0); -} - -static int -ufm_stop(struct ufm_softc *sc, void *addr) -{ - if (ufm_do_req(sc, UFM_CMD0, - 0x16, 0x1C, NULL)) { - return (EIO); - } - if (ufm_do_req(sc, UFM_CMD2, - 0x00, 0x00, NULL)) { - return (EIO); - } - return (0); -} - -static int -ufm_get_stat(struct ufm_softc *sc, void *addr) -{ - uint8_t ret; - - /* - * Note, there's a 240ms settle time before the status - * will be valid, so sleep that amount. - */ - usb_pause_mtx(NULL, hz / 4); - - if (ufm_do_req(sc, UFM_CMD0, - 0x00, 0x24, &ret)) { - return (EIO); - } - *(int *)addr = ret; - - return (0); -} - -static int -ufm_ioctl(struct usb_fifo *fifo, u_long cmd, void *addr, - int fflags) -{ - struct ufm_softc *sc = usb_fifo_softc(fifo); - int error = 0; - - if ((fflags & (FWRITE | FREAD)) != (FWRITE | FREAD)) { - return (EACCES); - } - - switch (cmd) { - case FM_SET_FREQ: - error = ufm_set_freq(sc, addr); - break; - case FM_GET_FREQ: - error = ufm_get_freq(sc, addr); - break; - case FM_START: - error = ufm_start(sc, addr); - break; - case FM_STOP: - error = ufm_stop(sc, addr); - break; - case FM_GET_STAT: - error = ufm_get_stat(sc, addr); - break; - default: - error = ENOTTY; - break; - } - return (error); -} diff --git a/sys/dts/arm/bcm2835.dtsi b/sys/dts/arm/bcm2835.dtsi deleted file mode 100644 index 00416b621a7..00000000000 --- a/sys/dts/arm/bcm2835.dtsi +++ /dev/null @@ -1,504 +0,0 @@ -/* - * Copyright (c) 2012 Oleksandr Tymoshenko - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - */ - -/ { - #address-cells = <1>; - #size-cells = <1>; - - cpus { - cpu@0 { - compatible = "arm,1176jzf-s"; - }; - }; - - - SOC: axi { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x20000000 0x01000000>; - ranges = <0 0x20000000 0x01000000>; - - intc: interrupt-controller { - compatible = "broadcom,bcm2835-armctrl-ic", - "broadcom,bcm2708-armctrl-ic"; - reg = <0xB200 0x200>; - - interrupt-controller; - #interrupt-cells = <1>; - - /* Bank 0 - * 0: ARM_TIMER - * 1: ARM_MAILBOX - * 2: ARM_DOORBELL_0 - * 3: ARM_DOORBELL_1 - * 4: VPU0_HALTED - * 5: VPU1_HALTED - * 6: ILLEGAL_TYPE0 - * 7: ILLEGAL_TYPE1 - */ - - /* Bank 1 - * 0: TIMER0 16: DMA0 - * 1: TIMER1 17: DMA1 - * 2: TIMER2 18: VC_DMA2 - * 3: TIMER3 19: VC_DMA3 - * 4: CODEC0 20: DMA4 - * 5: CODEC1 21: DMA5 - * 6: CODEC2 22: DMA6 - * 7: VC_JPEG 23: DMA7 - * 8: ISP 24: DMA8 - * 9: VC_USB 25: DMA9 - * 10: VC_3D 26: DMA10 - * 11: TRANSPOSER 27: DMA11 - * 12: MULTICORESYNC0 28: DMA12 - * 13: MULTICORESYNC1 29: AUX - * 14: MULTICORESYNC2 30: ARM - * 15: MULTICORESYNC3 31: VPUDMA - */ - - /* Bank 2 - * 0: HOSTPORT 16: SMI - * 1: VIDEOSCALER 17: GPIO0 - * 2: CCP2TX 18: GPIO1 - * 3: SDC 19: GPIO2 - * 4: DSI0 20: GPIO3 - * 5: AVE 21: VC_I2C - * 6: CAM0 22: VC_SPI - * 7: CAM1 23: VC_I2SPCM - * 8: HDMI0 24: VC_SDIO - * 9: HDMI1 25: VC_UART - * 10: PIXELVALVE1 26: SLIMBUS - * 11: I2CSPISLV 27: VEC - * 12: DSI1 28: CPG - * 13: PWA0 29: RNG - * 14: PWA1 30: VC_ARASANSDIO - * 15: CPR 31: AVSPMON - */ - }; - - timer { - compatible = "broadcom,bcm2835-system-timer", - "broadcom,bcm2708-system-timer"; - reg = <0x3000 0x1000>; - interrupts = <8 9 10 11>; - interrupt-parent = <&intc>; - - clock-frequency = <1000000>; - }; - - armtimer { - /* Not AMBA compatible */ - compatible = "broadcom,bcm2835-sp804", "arm,sp804"; - reg = <0xB400 0x24>; - interrupts = <0>; - interrupt-parent = <&intc>; - }; - - watchdog0 { - compatible = "broadcom,bcm2835-wdt", - "broadcom,bcm2708-wdt"; - reg = <0x10001c 0x0c>; /* 0x1c, 0x20, 0x24 */ - }; - - gpio: gpio { - compatible = "broadcom,bcm2835-gpio", - "broadcom,bcm2708-gpio"; - reg = <0x200000 0xb0>; - - /* Unusual arrangement of interrupts - * (determined by testing) - * 17: Bank 0 (GPIOs 0-31) - * 19: Bank 1 (GPIOs 32-53) - * 18: Bank 2 - * 20: All banks (GPIOs 0-53) - */ - interrupts = <57 59 58 60>; - interrupt-parent = <&intc>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - - pinctrl-names = "default"; - pinctrl-0 = <&pins_reserved>; - - /* Pins that can short 3.3V to GND in output mode: 46-47 - * Pins used by VideoCore: 48-53 - */ - broadcom,read-only = <46>, <47>, <48>, <49>, <50>, - <51>, <52>, <53>; - - /* BSC0 */ - pins_bsc0_a: bsc0_a { - broadcom,pins = <0>, <1>; - }; - - pins_bsc0_b: bsc0_b { - broadcom,pins = <28>, <29>; - }; - - pins_bsc0_c: bsc0_c { - broadcom,pins = <44>, <45>; - }; - - /* BSC1 */ - pins_bsc1_a: bsc1_a { - broadcom,pins = <2>, <3>; - }; - - pins_bsc1_b: bsc1_b { - broadcom,pins = <44>, <45>; - }; - - /* GPCLK0 */ - pins_gpclk0_a: gpclk0_a { - broadcom,pins = <4>; - }; - - pins_gpclk0_b: gpclk0_b { - broadcom,pins = <20>; - }; - - pins_gpclk0_c: gpclk0_c { - broadcom,pins = <32>; - }; - - pins_gpclk0_d: gpclk0_d { - broadcom,pins = <34>; - }; - - /* GPCLK1 */ - pins_gpclk1_a: gpclk1_a { - broadcom,pins = <5>; - }; - - pins_gpclk1_b: gpclk1_b { - broadcom,pins = <21>; - }; - - pins_gpclk1_c: gpclk1_c { - broadcom,pins = <42>; - }; - - pins_gpclk1_d: gpclk1_d { - broadcom,pins = <44>; - }; - - /* GPCLK2 */ - pins_gpclk2_a: gpclk2_a { - broadcom,pins = <6>; - }; - - pins_gpclk2_b: gpclk2_b { - broadcom,pins = <43>; - }; - - /* SPI0 */ - pins_spi0_a: spi0_a { - broadcom,pins = <7>, <8>, <9>, <10>, <11>; - }; - - pins_spi0_b: spi0_b { - broadcom,pins = <35>, <36>, <37>, <38>, <39>; - }; - - /* PWM */ - pins_pwm0_a: pwm0_a { - broadcom,pins = <12>; - }; - - pins_pwm0_b: pwm0_b { - broadcom,pins = <18>; - }; - - pins_pwm0_c: pwm0_c { - broadcom,pins = <40>; - }; - - pins_pwm1_a: pwm1_a { - broadcom,pins = <13>; - }; - - pins_pwm1_b: pwm1_b { - broadcom,pins = <19>; - }; - - pins_pwm1_c: pwm1_c { - broadcom,pins = <41>; - }; - - pins_pwm1_d: pwm1_d { - broadcom,pins = <45>; - }; - - /* UART0 */ - pins_uart0_a: uart0_a { - broadcom,pins = <14>, <15>; - }; - - pins_uart0_b: uart0_b { - broadcom,pins = <32>, <33>; - }; - - pins_uart0_c: uart0_c { - broadcom,pins = <36>, <37>; - }; - - pins_uart0_fc_a: uart0_fc_a { - broadcom,pins = <16>, <17>; - }; - - pins_uart0_fc_b: uart0_fc_b { - broadcom,pins = <30>, <31>; - }; - - pins_uart0_fc_c: uart0_fc_c { - broadcom,pins = <39>, <38>; - }; - - /* PCM */ - pins_pcm_a: pcm_a { - broadcom,pins = <18>, <19>, <20>, <21>; - }; - - pins_pcm_b: pcm_b { - broadcom,pins = <28>, <29>, <30>, <31>; - }; - - /* Secondary Address Bus */ - pins_sm_addr_a: sm_addr_a { - broadcom,pins = <5>, <4>, <3>, <2>, <1>, <0>; - }; - - pins_sm_addr_b: sm_addr_b { - broadcom,pins = <33>, <32>, <31>, <30>, <29>, - <28>; - }; - - pins_sm_ctl_a: sm_ctl_a { - broadcom,pins = <6>, <7>; - }; - - pins_sm_ctl_b: sm_ctl_b { - broadcom,pins = <34>, <35>; - }; - - pins_sm_data_8bit_a: sm_data_8bit_a { - broadcom,pins = <8>, <9>, <10>, <11>, <12>, - <13>, <14>, <15>; - }; - - pins_sm_data_8bit_b: sm_data_8bit_b { - broadcom,pins = <36>, <37>, <38>, <39>, <40>, - <41>, <42>, <43>; - }; - - pins_sm_data_16bit: sm_data_16bit { - broadcom,pins = <16>, <17>, <18>, <19>, <20>, - <21>, <22>, <23>; - }; - - pins_sm_data_18bit: sm_data_18bit { - broadcom,pins = <24>, <25>; - }; - - /* BSCSL */ - pins_bscsl: bscsl { - broadcom,pins = <18>, <19>; - }; - - /* SPISL */ - pins_spisl: spisl { - broadcom,pins = <18>, <19>, <20>, <21>; - }; - - /* SPI1 */ - pins_spi1: spi1 { - broadcom,pins = <16>, <17>, <18>, <19>, <20>, - <21>; - }; - - /* UART1 */ - pins_uart1_a: uart1_a { - broadcom,pins = <14>, <15>; - }; - - pins_uart1_b: uart1_b { - broadcom,pins = <32>, <33>; - }; - - pins_uart1_c: uart1_c { - broadcom,pins = <40>, <41>; - }; - - pins_uart1_fc_a: uart1_fc_a { - broadcom,pins = <16>, <17>; - }; - - pins_uart1_fc_b: uart1_fc_b { - broadcom,pins = <30>, <31>; - }; - - pins_uart1_fc_c: uart1_fc_c { - broadcom,pins = <43>, <42>; - }; - - /* SPI2 */ - pins_spi2: spi2 { - broadcom,pins = <40>, <41>, <42>, <43>, <44>, - <45>; - }; - - /* ARM JTAG */ - pins_arm_jtag_trst: arm_jtag_trst { - broadcom,pins = <22>; - }; - - pins_arm_jtag_a: arm_jtag_a { - broadcom,pins = <4>, <5>, <6>, <12>, <13>; - }; - - pins_arm_jtag_b: arm_jtag_b { - broadcom,pins = <23>, <24>, <25>, <26>, <27>; - }; - - /* Reserved */ - pins_reserved: reserved { - broadcom,pins = <48>, <49>, <50>, <51>, <52>, - <53>; - }; - }; - - rng { - compatible = "broadcom,bcm2835-rng", - "broadcom,bcm2708-rng"; - reg = <0x104000 0x20>; - interrupts = <69>; - interrupt-parent = <&intc>; - }; - - bsc0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "broadcom,bcm2835-bsc", - "broadcom,bcm2708-bsc"; - reg = <0x205000 0x20>; - interrupts = <61>; - interrupt-parent = <&intc>; - }; - - bsc1 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "broadcom,bcm2835-bsc", - "broadcom,bcm2708-bsc"; - reg = <0x804000 0x20>; - interrupts = <61>; - interrupt-parent = <&intc>; - }; - - spi0 { - compatible = "broadcom,bcm2835-spi", - "broadcom,bcm2708-spi"; - reg = <0x204000 0x20>; - interrupts = <62>; - interrupt-parent = <&intc>; - }; - - dma: dma { - compatible = "broadcom,bcm2835-dma", - "broadcom,bcm2708-dma"; - reg = <0x7000 0x1000>, <0xE05000 0x1000>; - interrupts = <24 25 26 27 28 29 30 31 32 33 34 35 36>; - interrupt-parent = <&intc>; - - broadcom,channels = <0x7f35>; - }; - - vc_mbox: mbox { - compatible = "broadcom,bcm2835-mbox", - "broadcom,bcm2708-mbox"; - reg = <0xB880 0x40>; - interrupts = <1>; - interrupt-parent = <&intc>; - - /* Channels - * 0: Power - * 1: Frame buffer - * 2: Virtual UART - * 3: VCHIQ - * 4: LEDs - * 5: Buttons - * 6: Touch screen - */ - }; - - sdhci { - compatible = "broadcom,bcm2835-sdhci", - "broadcom,bcm2708-sdhci"; - reg = <0x300000 0x100>; - interrupts = <70>; - interrupt-parent = <&intc>; - - clock-frequency = <50000000>; /* Set by VideoCore */ - }; - - uart0: uart0 { - compatible = "broadcom,bcm2835-uart", - "broadcom,bcm2708-uart", "arm,pl011", - "arm,primecell"; - reg = <0x201000 0x1000>; - interrupts = <65>; - interrupt-parent = <&intc>; - - clock-frequency = <3000000>; /* Set by VideoCore */ - reg-shift = <2>; - }; - - vchiq: vchiq { - compatible = "broadcom,bcm2835-vchiq"; - reg = <0xB800 0x50>; - interrupts = <2>; - interrupt-parent = <&intc>; - cache-line-size = <32>; - }; - - usb { - compatible = "broadcom,bcm2835-usb", - "broadcom,bcm2708-usb", - "synopsys,designware-hs-otg2"; - reg = <0x980000 0x20000>; - interrupts = <17>; - interrupt-parent = <&intc>; - #address-cells = <1>; - #size-cells = <0>; - }; - - }; -}; diff --git a/sys/dts/arm/bcm2836.dtsi b/sys/dts/arm/bcm2836.dtsi deleted file mode 100644 index 4060af09e24..00000000000 --- a/sys/dts/arm/bcm2836.dtsi +++ /dev/null @@ -1,507 +0,0 @@ -/* - * Copyright (c) 2012 Oleksandr Tymoshenko - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - */ - -/ { - #address-cells = <1>; - #size-cells = <1>; - - timer { - compatible = "arm,armv7-timer"; - clock-frequency = <19200000>; - interrupts = <0 1 3 2>; - interrupt-parent = <&local_intc>; - }; - - SOC: axi { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x3f000000 0x01000000>; - ranges = <0 0x3f000000 0x01000000>, - <0x40000000 0x40000000 0x00001000>; - - local_intc: local_intc { - compatible = "brcm,bcm2836-l1-intc"; - reg = <0x40000000 0x100>; - interrupt-controller; - #interrupt-cells = <1>; - interrupt-parent = <&local_intc>; - }; - - intc: interrupt-controller { - compatible = "broadcom,bcm2835-armctrl-ic", - "broadcom,bcm2708-armctrl-ic"; - reg = <0xB200 0x200>; - interrupt-parent = <&local_intc>; - interrupts = <8>; - - interrupt-controller; - #interrupt-cells = <1>; - - /* Bank 0 - * 0: ARM_TIMER - * 1: ARM_MAILBOX - * 2: ARM_DOORBELL_0 - * 3: ARM_DOORBELL_1 - * 4: VPU0_HALTED - * 5: VPU1_HALTED - * 6: ILLEGAL_TYPE0 - * 7: ILLEGAL_TYPE1 - */ - - /* Bank 1 - * 0: TIMER0 16: DMA0 - * 1: TIMER1 17: DMA1 - * 2: TIMER2 18: VC_DMA2 - * 3: TIMER3 19: VC_DMA3 - * 4: CODEC0 20: DMA4 - * 5: CODEC1 21: DMA5 - * 6: CODEC2 22: DMA6 - * 7: VC_JPEG 23: DMA7 - * 8: ISP 24: DMA8 - * 9: VC_USB 25: DMA9 - * 10: VC_3D 26: DMA10 - * 11: TRANSPOSER 27: DMA11 - * 12: MULTICORESYNC0 28: DMA12 - * 13: MULTICORESYNC1 29: AUX - * 14: MULTICORESYNC2 30: ARM - * 15: MULTICORESYNC3 31: VPUDMA - */ - - /* Bank 2 - * 0: HOSTPORT 16: SMI - * 1: VIDEOSCALER 17: GPIO0 - * 2: CCP2TX 18: GPIO1 - * 3: SDC 19: GPIO2 - * 4: DSI0 20: GPIO3 - * 5: AVE 21: VC_I2C - * 6: CAM0 22: VC_SPI - * 7: CAM1 23: VC_I2SPCM - * 8: HDMI0 24: VC_SDIO - * 9: HDMI1 25: VC_UART - * 10: PIXELVALVE1 26: SLIMBUS - * 11: I2CSPISLV 27: VEC - * 12: DSI1 28: CPG - * 13: PWA0 29: RNG - * 14: PWA1 30: VC_ARASANSDIO - * 15: CPR 31: AVSPMON - */ - }; - - watchdog0 { - compatible = "broadcom,bcm2835-wdt", - "broadcom,bcm2708-wdt"; - reg = <0x10001c 0x0c>; /* 0x1c, 0x20, 0x24 */ - }; - - gpio: gpio { - compatible = "broadcom,bcm2835-gpio", - "broadcom,bcm2708-gpio"; - reg = <0x200000 0xb0>; - - /* Unusual arrangement of interrupts - * (determined by testing) - * 17: Bank 0 (GPIOs 0-31) - * 19: Bank 1 (GPIOs 32-53) - * 18: Bank 2 - * 20: All banks (GPIOs 0-53) - */ - interrupts = <57 59 58 60>; - interrupt-parent = <&intc>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - - pinctrl-names = "default"; - pinctrl-0 = <&pins_reserved>; - - /* Pins that can short 3.3V to GND in output mode: 46 - * Pins used by VideoCore: 48-53 - */ - broadcom,read-only = <46>, <48>, <49>, <50>, - <51>, <52>, <53>; - - /* BSC0 */ - pins_bsc0_a: bsc0_a { - broadcom,pins = <0>, <1>; - }; - - pins_bsc0_b: bsc0_b { - broadcom,pins = <28>, <29>; - }; - - pins_bsc0_c: bsc0_c { - broadcom,pins = <44>, <45>; - }; - - /* BSC1 */ - pins_bsc1_a: bsc1_a { - broadcom,pins = <2>, <3>; - }; - - pins_bsc1_b: bsc1_b { - broadcom,pins = <44>, <45>; - }; - - /* GPCLK0 */ - pins_gpclk0_a: gpclk0_a { - broadcom,pins = <4>; - }; - - pins_gpclk0_b: gpclk0_b { - broadcom,pins = <20>; - }; - - pins_gpclk0_c: gpclk0_c { - broadcom,pins = <32>; - }; - - pins_gpclk0_d: gpclk0_d { - broadcom,pins = <34>; - }; - - /* GPCLK1 */ - pins_gpclk1_a: gpclk1_a { - broadcom,pins = <5>; - }; - - pins_gpclk1_b: gpclk1_b { - broadcom,pins = <21>; - }; - - pins_gpclk1_c: gpclk1_c { - broadcom,pins = <42>; - }; - - pins_gpclk1_d: gpclk1_d { - broadcom,pins = <44>; - }; - - /* GPCLK2 */ - pins_gpclk2_a: gpclk2_a { - broadcom,pins = <6>; - }; - - pins_gpclk2_b: gpclk2_b { - broadcom,pins = <43>; - }; - - /* SPI0 */ - pins_spi0_a: spi0_a { - broadcom,pins = <7>, <8>, <9>, <10>, <11>; - }; - - pins_spi0_b: spi0_b { - broadcom,pins = <35>, <36>, <37>, <38>, <39>; - }; - - /* PWM */ - pins_pwm0_a: pwm0_a { - broadcom,pins = <12>; - }; - - pins_pwm0_b: pwm0_b { - broadcom,pins = <18>; - }; - - pins_pwm0_c: pwm0_c { - broadcom,pins = <40>; - }; - - pins_pwm1_a: pwm1_a { - broadcom,pins = <13>; - }; - - pins_pwm1_b: pwm1_b { - broadcom,pins = <19>; - }; - - pins_pwm1_c: pwm1_c { - broadcom,pins = <41>; - }; - - pins_pwm1_d: pwm1_d { - broadcom,pins = <45>; - }; - - /* UART0 */ - pins_uart0_a: uart0_a { - broadcom,pins = <14>, <15>; - }; - - pins_uart0_b: uart0_b { - broadcom,pins = <32>, <33>; - }; - - pins_uart0_c: uart0_c { - broadcom,pins = <36>, <37>; - }; - - pins_uart0_fc_a: uart0_fc_a { - broadcom,pins = <16>, <17>; - }; - - pins_uart0_fc_b: uart0_fc_b { - broadcom,pins = <30>, <31>; - }; - - pins_uart0_fc_c: uart0_fc_c { - broadcom,pins = <39>, <38>; - }; - - /* PCM */ - pins_pcm_a: pcm_a { - broadcom,pins = <18>, <19>, <20>, <21>; - }; - - pins_pcm_b: pcm_b { - broadcom,pins = <28>, <29>, <30>, <31>; - }; - - /* Secondary Address Bus */ - pins_sm_addr_a: sm_addr_a { - broadcom,pins = <5>, <4>, <3>, <2>, <1>, <0>; - }; - - pins_sm_addr_b: sm_addr_b { - broadcom,pins = <33>, <32>, <31>, <30>, <29>, - <28>; - }; - - pins_sm_ctl_a: sm_ctl_a { - broadcom,pins = <6>, <7>; - }; - - pins_sm_ctl_b: sm_ctl_b { - broadcom,pins = <34>, <35>; - }; - - pins_sm_data_8bit_a: sm_data_8bit_a { - broadcom,pins = <8>, <9>, <10>, <11>, <12>, - <13>, <14>, <15>; - }; - - pins_sm_data_8bit_b: sm_data_8bit_b { - broadcom,pins = <36>, <37>, <38>, <39>, <40>, - <41>, <42>, <43>; - }; - - pins_sm_data_16bit: sm_data_16bit { - broadcom,pins = <16>, <17>, <18>, <19>, <20>, - <21>, <22>, <23>; - }; - - pins_sm_data_18bit: sm_data_18bit { - broadcom,pins = <24>, <25>; - }; - - /* BSCSL */ - pins_bscsl: bscsl { - broadcom,pins = <18>, <19>; - }; - - /* SPISL */ - pins_spisl: spisl { - broadcom,pins = <18>, <19>, <20>, <21>; - }; - - /* SPI1 */ - pins_spi1: spi1 { - broadcom,pins = <16>, <17>, <18>, <19>, <20>, - <21>; - }; - - /* UART1 */ - pins_uart1_a: uart1_a { - broadcom,pins = <14>, <15>; - }; - - pins_uart1_b: uart1_b { - broadcom,pins = <32>, <33>; - }; - - pins_uart1_c: uart1_c { - broadcom,pins = <40>, <41>; - }; - - pins_uart1_fc_a: uart1_fc_a { - broadcom,pins = <16>, <17>; - }; - - pins_uart1_fc_b: uart1_fc_b { - broadcom,pins = <30>, <31>; - }; - - pins_uart1_fc_c: uart1_fc_c { - broadcom,pins = <43>, <42>; - }; - - /* SPI2 */ - pins_spi2: spi2 { - broadcom,pins = <40>, <41>, <42>, <43>, <44>, - <45>; - }; - - /* ARM JTAG */ - pins_arm_jtag_trst: arm_jtag_trst { - broadcom,pins = <22>; - }; - - pins_arm_jtag_a: arm_jtag_a { - broadcom,pins = <4>, <5>, <6>, <12>, <13>; - }; - - pins_arm_jtag_b: arm_jtag_b { - broadcom,pins = <23>, <24>, <25>, <26>, <27>; - }; - - /* Reserved */ - pins_reserved: reserved { - broadcom,pins = <48>, <49>, <50>, <51>, <52>, - <53>; - }; - }; - - cprman { - compatible = "broadcom,bcm2835-cprman"; - reg = <0x101000 0x2000>; - }; - - rng { - compatible = "broadcom,bcm2835-rng", - "broadcom,bcm2708-rng"; - reg = <0x104000 0x20>; - interrupts = <69>; - interrupt-parent = <&intc>; - }; - - bsc0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "broadcom,bcm2835-bsc", - "broadcom,bcm2708-bsc"; - reg = <0x205000 0x20>; - interrupts = <61>; - interrupt-parent = <&intc>; - }; - - bsc1 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "broadcom,bcm2835-bsc", - "broadcom,bcm2708-bsc"; - reg = <0x804000 0x20>; - interrupts = <61>; - interrupt-parent = <&intc>; - }; - - spi0 { - compatible = "broadcom,bcm2835-spi", - "broadcom,bcm2708-spi"; - reg = <0x204000 0x20>; - interrupts = <62>; - interrupt-parent = <&intc>; - }; - - pwm0 { - compatible = "broadcom,bcm2835-pwm"; - reg = <0x20c000 0x28>; - }; - - dma: dma { - compatible = "broadcom,bcm2835-dma", - "broadcom,bcm2708-dma"; - reg = <0x7000 0x1000>, <0xE05000 0x1000>; - interrupts = <24 25 26 27 28 29 30 31 32 33 34 35 36>; - interrupt-parent = <&intc>; - - broadcom,channels = <0x7f35>; - }; - - vc_mbox: mbox { - compatible = "broadcom,bcm2835-mbox", - "broadcom,bcm2708-mbox"; - reg = <0xB880 0x40>; - interrupts = <1>; - interrupt-parent = <&intc>; - - /* Channels - * 0: Power - * 1: Frame buffer - * 2: Virtual UART - * 3: VCHIQ - * 4: LEDs - * 5: Buttons - * 6: Touch screen - */ - }; - - sdhci { - compatible = "broadcom,bcm2835-sdhci", - "broadcom,bcm2708-sdhci"; - reg = <0x300000 0x100>; - interrupts = <70>; - interrupt-parent = <&intc>; - - clock-frequency = <250000000>; /* Set by VideoCore */ - }; - - uart0: uart0 { - compatible = "broadcom,bcm2835-uart", - "broadcom,bcm2708-uart", "arm,pl011", - "arm,primecell"; - reg = <0x201000 0x1000>; - interrupts = <65>; - interrupt-parent = <&intc>; - - clock-frequency = <3000000>; /* Set by VideoCore */ - reg-shift = <2>; - }; - - vchiq: vchiq { - compatible = "broadcom,bcm2835-vchiq"; - reg = <0xB800 0x50>; - interrupts = <2>; - interrupt-parent = <&intc>; - cache-line-size = <32>; - }; - - usb { - compatible = "broadcom,bcm2835-usb", - "broadcom,bcm2708-usb", - "synopsys,designware-hs-otg2"; - reg = <0x980000 0x20000>; - interrupts = <17>; - interrupt-parent = <&intc>; - #address-cells = <1>; - #size-cells = <0>; - }; - - }; -}; diff --git a/sys/dts/arm/exynos5.dtsi b/sys/dts/arm/exynos5.dtsi deleted file mode 100644 index 9f70057f12f..00000000000 --- a/sys/dts/arm/exynos5.dtsi +++ /dev/null @@ -1,336 +0,0 @@ -/*- - * Copyright (c) 2013-2014 Ruslan Bukin - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - */ - -/ { - compatible = "samsung,exynos5"; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&GIC>; - - aliases { - soc = &SOC; - serial0 = &serial0; - serial1 = &serial1; - serial2 = &serial2; - serial3 = &serial3; - clk0 = &clk0; - dp0 = &dp0; - fimd0 = &fimd0; - }; - - SOC: Exynos5@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges; - bus-frequency = <0>; - - pmu_system_controller: system-controller@10040000 { - reg = <0x10040000 0x5000>; - status = "disabled"; - }; - - GIC: interrupt-controller@10481000 { - compatible = "arm,gic"; - reg = < 0x10481000 0x1000 >, /* Distributor Registers */ - < 0x10482000 0x2000 >; /* CPU Interface Registers */ - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - }; - - combiner: interrupt-controller@10440000 { - compatible = "exynos,combiner"; - reg = <0x10440000 0x1000>; - interrupts = < 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 - 48 49 50 51 52 53 54 55 - 56 57 58 59 60 61 62 63 >; - interrupt-parent = <&GIC>; - }; - - clk0: clk@10010000 { - compatible = "exynos,clk"; - reg = < 0x10020000 0x20000 >; - }; - - mct { - compatible = "exynos,mct"; - reg = < 0x101C0000 0x1000 >; - clock-frequency = <24000000>; - }; - - generic_timer { - compatible = "arm,armv7-timer"; - clock-frequency = <24000000>; - interrupts = < 29 30 27 26 >; - interrupt-parent = <&GIC>; - }; - - pwm { - compatible = "samsung,s3c24x0-timer"; - reg = <0x12DD0000 0x1000>; - interrupts = < 71 >; - interrupt-parent = <&GIC>; - clock-frequency = <24000000>; - }; - - pad0: pad@11400000 { - status = "disabled"; - }; - - usbdrd_phy0: phy@12100000 { - compatible = "samsung,exynos5420-usbdrd-phy"; - status = "disabled"; - reg = <0x12100000 0x100>; - samsung,pmu-syscon = <&pmu_system_controller>; - }; - - usbdrd_phy1: phy@12500000 { - compatible = "samsung,exynos5420-usbdrd-phy"; - status = "disabled"; - reg = <0x12500000 0x100>; - samsung,pmu-syscon = <&pmu_system_controller>; - }; - - xhci@12000000 { - compatible = "samsung,exynos5250-dwusb3"; - status = "disabled"; - reg = <0x12000000 0x1000>, - <0x1200c100 0x1000>; - interrupts = < 104 >; - interrupt-parent = <&GIC>; - }; - - xhci@12400000 { - compatible = "samsung,exynos5250-dwusb3"; - status = "disabled"; - reg = <0x12400000 0x1000>, - <0x1240c100 0x1000>; - interrupts = < 105 >; - interrupt-parent = <&GIC>; - }; - - usb@12110000 { - compatible = "exynos,usb-ehci", "usb-ehci"; - status = "disabled"; - reg = <0x12110000 0x1000>, /* EHCI */ - <0x12130000 0x1000>, /* EHCI host ctrl */ - <0x10050230 0x10>; /* Sysreg */ - interrupts = < 103 >; - interrupt-parent = <&GIC>; - }; - - usb@12120000 { - compatible = "exynos,usb-ohci", "usb-ohci"; - status = "disabled"; - reg = <0x12120000 0x10000>; - interrupts = < 103 >; - interrupt-parent = <&GIC>; - }; - - sdhci@12200000 { - compatible = "sdhci_generic"; - status = "disabled"; - reg = <0x12200000 0x1000>; - interrupts = <107>; - interrupt-parent = <&GIC>; - max-frequency = <24000000>; /* TODO: verify freq */ - }; - - sdhci@12210000 { - compatible = "sdhci_generic"; - status = "disabled"; - reg = <0x12210000 0x1000>; - interrupts = <108>; - interrupt-parent = <&GIC>; - max-frequency = <24000000>; - }; - - sdhci@12220000 { - compatible = "sdhci_generic"; - status = "disabled"; - reg = <0x12220000 0x1000>; - interrupts = <109>; - interrupt-parent = <&GIC>; - max-frequency = <24000000>; - }; - - sdhci@12230000 { - compatible = "sdhci_generic"; - status = "disabled"; - reg = <0x12230000 0x1000>; - interrupts = <110>; - interrupt-parent = <&GIC>; - max-frequency = <24000000>; - }; - - serial0: serial@12C00000 { - compatible = "exynos"; - status = "disabled"; - reg = <0x12C00000 0x100>; - interrupts = < 83 >; - interrupt-parent = <&GIC>; - clock-frequency = < 100000000 >; - current-speed = <115200>; - }; - - serial1: serial@12C10000 { - compatible = "exynos"; - status = "disabled"; - reg = <0x12C10000 0x100>; - interrupts = < 84 >; - interrupt-parent = <&GIC>; - clock-frequency = < 100000000 >; - current-speed = <115200>; - }; - - serial2: serial@12C20000 { - compatible = "exynos"; - status = "disabled"; - reg = <0x12C20000 0x100>; - interrupts = < 85 >; - interrupt-parent = <&GIC>; - clock-frequency = < 100000000 >; - current-speed = <115200>; - }; - - serial3: serial@12C30000 { - compatible = "exynos"; - status = "disabled"; - reg = <0x12C30000 0x100>; - interrupts = < 86 >; - interrupt-parent = <&GIC>; - clock-frequency = < 100000000 >; - current-speed = <115200>; - }; - - spi0: spi@12d20000 { - compatible = "samsung,exynos5-spi"; - status = "disabled"; - reg = <0x12d20000 0x100>; - interrupts = < 100 >; - interrupt-parent = <&GIC>; - }; - - spi1: spi@12d30000 { - compatible = "samsung,exynos5-spi"; - status = "disabled"; - reg = <0x12d30000 0x100>; - interrupts = < 101 >; - interrupt-parent = <&GIC>; - }; - - spi2: spi@12d40000 { - compatible = "samsung,exynos5-spi"; - status = "disabled"; - reg = <0x12d40000 0x100>; - interrupts = < 102 >; - interrupt-parent = <&GIC>; - }; - - i2c0: i2c@12C60000 { - compatible = "exynos,i2c"; - status = "disabled"; - reg = <0x12C60000 0x10000>; - interrupts = < 88 >; - interrupt-parent = <&GIC>; - }; - - i2c1: i2c@12C70000 { - compatible = "exynos,i2c"; - status = "disabled"; - reg = <0x12C70000 0x10000>; - interrupts = < 89 >; - interrupt-parent = <&GIC>; - }; - - i2c2: i2c@12C80000 { - compatible = "exynos,i2c"; - status = "disabled"; - reg = <0x12C80000 0x10000>; - interrupts = < 90 >; - interrupt-parent = <&GIC>; - }; - - i2c3: i2c@12C90000 { - compatible = "exynos,i2c"; - status = "disabled"; - reg = <0x12C90000 0x10000>; - interrupts = < 91 >; - interrupt-parent = <&GIC>; - }; - - i2c4: i2c@12CA0000 { - compatible = "exynos,i2c"; - status = "disabled"; - reg = <0x12CA0000 0x10000>; - interrupts = < 92 >; - interrupt-parent = <&GIC>; - }; - - i2c5: i2c@12CB0000 { - compatible = "exynos,i2c"; - status = "disabled"; - reg = <0x12CB0000 0x10000>; - interrupts = < 93 >; - interrupt-parent = <&GIC>; - }; - - i2c6: i2c@12CC0000 { - compatible = "exynos,i2c"; - status = "disabled"; - reg = <0x12CC0000 0x10000>; - interrupts = < 94 >; - interrupt-parent = <&GIC>; - }; - - i2c7: i2c@12CD0000 { - compatible = "exynos,i2c"; - status = "disabled"; - reg = <0x12CD0000 0x10000>; - interrupts = < 95 >; - interrupt-parent = <&GIC>; - }; - - fimd0: fimd@14400000 { - compatible = "exynos,fimd"; - status = "disabled"; - reg = < 0x14400000 0x10000 >, /* fimd */ - < 0x14420000 0x10000 >, /* disp */ - < 0x10050000 0x220 >; /* sysreg */ - interrupt-parent = <&GIC>; - }; - - dp0: dp@145B0000 { - compatible = "exynos,dp"; - status = "disabled"; - reg = < 0x145B0000 0x10000 >; - interrupt-parent = <&GIC>; - }; - }; -}; diff --git a/sys/dts/arm/exynos5250-arndale.dts b/sys/dts/arm/exynos5250-arndale.dts deleted file mode 100644 index bfe0c9483a9..00000000000 --- a/sys/dts/arm/exynos5250-arndale.dts +++ /dev/null @@ -1,56 +0,0 @@ -/*- - * Copyright (c) 2013 Ruslan Bukin - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - */ - -/dts-v1/; - -/include/ "exynos5250.dtsi" - -/ { - model = "Arndale Board"; - - memory { - device_type = "memory"; - reg = < 0x40000000 0x80000000 >; /* 2G */ - }; - - SOC: Exynos5@0 { - - pad0: pad@11400000 { - status = "okay"; - }; - - serial2: serial@12C20000 { - status = "okay"; - }; - - }; - - chosen { - stdin = &serial2; - stdout = &serial2; - }; -}; diff --git a/sys/dts/arm/exynos5250-snow.dts b/sys/dts/arm/exynos5250-snow.dts deleted file mode 100644 index 581b3a7226d..00000000000 --- a/sys/dts/arm/exynos5250-snow.dts +++ /dev/null @@ -1,81 +0,0 @@ -/*- - * Copyright (c) 2014 Ruslan Bukin - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - */ - -/dts-v1/; - -/include/ "exynos5250.dtsi" - -/ { - model = "Samsung Chromebook"; - - memory { - device_type = "memory"; - reg = < 0x40000000 0x80000000 >; /* 2G */ - }; - - SOC: Exynos5@0 { - - pad0: pad@11400000 { - status = "okay"; - }; - - fimd0: fimd@14400000 { - status = "okay"; - - panel-size = < 1366 768 >; - panel-hsync = < 80 32 48 >; - panel-vsync = < 14 5 3 >; - panel-clk-div = < 17 >; - panel-backlight-pin = < 25 >; - }; - - i2c4: i2c@12CA0000 { - status = "okay"; - }; - - keyboard-controller { - compatible = "google,mkbp-keyb"; - google,key-rows = <8>; - google,key-columns = <13>; - freebsd,intr-gpio = <146>; - }; - - usbdrd_phy0: phy@12100000 { - vbus-supply = < 155 >; - }; - }; - - i2c-arbitrator { - freebsd,our-gpio = <177>; - freebsd,ec-gpio = <168>; - }; - - chosen { - stdin = &serial2; - stdout = &serial2; - }; -}; diff --git a/sys/dts/arm/exynos5250-spring.dts b/sys/dts/arm/exynos5250-spring.dts deleted file mode 100644 index ffa0931c3ec..00000000000 --- a/sys/dts/arm/exynos5250-spring.dts +++ /dev/null @@ -1,77 +0,0 @@ -/*- - * Copyright (c) 2014 Ruslan Bukin - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - */ - -/dts-v1/; - -/include/ "exynos5250.dtsi" - -/ { - model = "HP Chromebook 11"; - - memory { - device_type = "memory"; - reg = < 0x40000000 0x80000000 >; /* 2G */ - }; - - SOC: Exynos5@0 { - - pad0: pad@11400000 { - status = "okay"; - }; - - fimd0: fimd@14400000 { - status = "okay"; - - panel-size = < 1366 768 >; - panel-hsync = < 80 32 48 >; - panel-vsync = < 14 5 3 >; - panel-clk-div = < 17 >; - panel-backlight-pin = < 25 >; - }; - - i2c4: i2c@12CA0000 { - status = "okay"; - }; - - keyboard-controller { - compatible = "google,mkbp-keyb"; - google,key-rows = <8>; - google,key-columns = <13>; - freebsd,intr-gpio = <146>; - }; - }; - - chosen { - stdin = &serial2; - stdout = &serial2; - }; - - hsichub@13400000 { - compatible = "smsc,usb3503"; - freebsd,reset-gpio = <172>; - }; -}; diff --git a/sys/dts/arm/exynos5250.dtsi b/sys/dts/arm/exynos5250.dtsi deleted file mode 100644 index c602b2e558b..00000000000 --- a/sys/dts/arm/exynos5250.dtsi +++ /dev/null @@ -1,78 +0,0 @@ -/*- - * Copyright (c) 2013-2014 Ruslan Bukin - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - */ - -/include/ "exynos5.dtsi" - -/ { - compatible = "samsung,exynos5250", "samsung,exynos5"; - - SOC: Exynos5@0 { - - pmu_system_controller: system-controller@10040000 { - compatible = "samsung,exynos5250-pmu"; - status = "okay"; - }; - - pad0: pad@11400000 { - compatible = "samsung,exynos5250-padctrl"; - reg = <0x11400000 0x1000>, - <0x13400000 0x1000>, - <0x10D10000 0x1000>, - <0x03860000 0x1000>; - interrupts = < 78 77 82 79 >; - interrupt-parent = <&GIC>; - }; - - serial0: serial@12C00000 { - clock-frequency = < 100000000 >; - }; - - serial1: serial@12C10000 { - clock-frequency = < 100000000 >; - }; - - serial2: serial@12C20000 { - clock-frequency = < 100000000 >; - }; - - serial3: serial@12C30000 { - clock-frequency = < 100000000 >; - }; - - usb@12110000 { - status = "okay"; - }; - - usbdrd_phy0: phy@12100000 { - status = "okay"; - }; - - xhci@12000000 { - status = "okay"; - }; - }; -}; diff --git a/sys/dts/arm/exynos5420-arndale-octa.dts b/sys/dts/arm/exynos5420-arndale-octa.dts deleted file mode 100644 index c43d4a479f3..00000000000 --- a/sys/dts/arm/exynos5420-arndale-octa.dts +++ /dev/null @@ -1,69 +0,0 @@ -/*- - * Copyright (c) 2014 Ruslan Bukin - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - */ - -/dts-v1/; - -/include/ "exynos5420.dtsi" - -/ { - model = "Arndale Octa Board"; - - memory { - device_type = "memory"; - reg = < 0x20000000 0x7f200000 >; /* 2G */ - }; - - SOC: Exynos5@0 { - serial3: serial@12C30000 { - status = "okay"; - }; - - usb@12110000 { - status = "okay"; - }; - - mmc2: dwmmc@12220000 { - status = "okay"; - num-slots = <1>; - supports-highspeed; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; - bus-frequency = <50000000>; - - slot@0 { - reg = <0>; - bus-width = <4>; - }; - }; - }; - - chosen { - stdin = &serial3; - stdout = &serial3; - }; -}; diff --git a/sys/dts/arm/exynos5420-peach-pit.dts b/sys/dts/arm/exynos5420-peach-pit.dts deleted file mode 100644 index 62b6d6e1a76..00000000000 --- a/sys/dts/arm/exynos5420-peach-pit.dts +++ /dev/null @@ -1,86 +0,0 @@ -/*- - * Copyright (c) 2014 Ruslan Bukin - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - */ - -/dts-v1/; - -/include/ "exynos5420.dtsi" - -/ { - model = "Chromebook Peach Pit"; - - memory { - device_type = "memory"; - reg = < 0x20000000 0xdf000000 >; /* 3.5G */ - }; - - SOC: Exynos5@0 { - - fimd0: fimd@14400000 { - status = "okay"; - - panel-size = < 1366 768 >; - panel-hsync = < 80 32 48 >; - panel-vsync = < 14 5 3 >; - panel-clk-div = < 17 >; - panel-backlight-pin = < 25 >; - }; - - spi2: spi@12d40000 { - status = "okay"; - }; - - keyboard-controller { - compatible = "google,mkbp-keyb"; - google,key-rows = <8>; - google,key-columns = <13>; - freebsd,intr-gpio = < 21 >; - }; - - usbdrd_phy0: phy@12100000 { - vbus-supply = < 217 >; - }; - - usbdrd_phy1: phy@12500000 { - vbus-supply = < 218 >; - }; - - mmc2: dwmmc@12220000 { - status = "okay"; - num-slots = <1>; - supports-highspeed; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; - bus-frequency = <50000000>; - - slot@0 { - reg = <0>; - bus-width = <4>; - }; - }; - }; -}; diff --git a/sys/dts/arm/exynos5420.dtsi b/sys/dts/arm/exynos5420.dtsi deleted file mode 100644 index 7ee2406446c..00000000000 --- a/sys/dts/arm/exynos5420.dtsi +++ /dev/null @@ -1,111 +0,0 @@ -/*- - * Copyright (c) 2014 Ruslan Bukin - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - */ - -/include/ "exynos5.dtsi" - -/ { - compatible = "samsung,exynos5420", "samsung,exynos5"; - - SOC: Exynos5@0 { - - pmu_system_controller: system-controller@10040000 { - compatible = "samsung,exynos5420-pmu"; - status = "okay"; - }; - - pad0: pad@11400000 { - compatible = "samsung,exynos5420-padctrl"; - status = "okay"; - reg = <0x13400000 0x1000>, - <0x13410000 0x1000>, - <0x14000000 0x1000>, - <0x14010000 0x1000>, - <0x03860000 0x1000>; - interrupts = < 77 110 78 82 79 >; - interrupt-parent = <&GIC>; - }; - - serial0: serial@12C00000 { - clock-frequency = < 50000000 >; - }; - - serial1: serial@12C10000 { - clock-frequency = < 50000000 >; - }; - - serial2: serial@12C20000 { - clock-frequency = < 50000000 >; - }; - - serial3: serial@12C30000 { - clock-frequency = < 50000000 >; - }; - - usbdrd_phy0: phy@12100000 { - status = "okay"; - }; - - usbdrd_phy1: phy@12500000 { - status = "okay"; - }; - - xhci@12000000 { - status = "okay"; - }; - - xhci@12400000 { - status = "okay"; - }; - - mmc0: dwmmc@12200000 { - compatible = "samsung,exynos5420-dw-mshc-smu"; - reg = <0x12200000 0x10000>; - interrupts = <107>; - interrupt-parent = <&GIC>; - fifo-depth = <0x40>; - status = "disabled"; - }; - - mmc1: dwmmc@12210000 { - compatible = "samsung,exynos5420-dw-mshc-smu"; - reg = <0x12210000 0x10000>; - interrupts = <108>; - interrupt-parent = <&GIC>; - fifo-depth = <0x40>; - status = "disabled"; - }; - - mmc2: dwmmc@12220000 { - compatible = "samsung,exynos5420-dw-mshc"; - reg = <0x12220000 0x10000>; - interrupts = <109>; - interrupt-parent = <&GIC>; - fifo-depth = <0x40>; - status = "disabled"; - }; - }; -}; diff --git a/sys/dts/arm/meson3.dtsi b/sys/dts/arm/meson3.dtsi deleted file mode 100644 index 83c0cb343c0..00000000000 --- a/sys/dts/arm/meson3.dtsi +++ /dev/null @@ -1,76 +0,0 @@ -/*- - * Copyright (c) 2015 John Wehle - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - */ - -/* - * The basic single core aml8726 (aka meson) uses an Amlogic interrupt - * controller, however meson.dtsi specifies GIC (which is present on - * the multicore aml8726) so we need to override things here. - */ - -/include/ "meson.dtsi" - -/ { - model = "Amlogic Meson3 SoC"; - compatible = "amlogic,meson3"; - - interrupt-parent = <&pic>; - - pic: pic@c1109a40 { - device_type = "interrupt-controller"; - compatible = "amlogic,aml8726-pic"; - reg = <0xc1109a40 128>; /* cbus 0x2690 */ - - interrupt-controller; - #interrupt-cells = <3>; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@200 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - next-level-cache = <&L2>; - reg = <0x200>; - }; - }; - - clk81: clk@0 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; -}; - -&gic { - status = "disabled"; -}; - -&L2 { - interrupts = <0 61 1>; -}; diff --git a/sys/dts/arm/meson8b.dtsi b/sys/dts/arm/meson8b.dtsi deleted file mode 100644 index a94f6182f93..00000000000 --- a/sys/dts/arm/meson8b.dtsi +++ /dev/null @@ -1,78 +0,0 @@ -/*- - * Copyright (c) 2015 John Wehle - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - */ - -/include/ "meson.dtsi" - -/ { - model = "Amlogic Meson8b SoC"; - compatible = "amlogic,meson8b"; - - interrupt-parent = <&gic>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@200 { - device_type = "cpu"; - compatible = "arm,cortex-a5"; - next-level-cache = <&L2>; - reg = <0x200>; - }; - - cpu@201 { - device_type = "cpu"; - compatible = "arm,cortex-a5"; - next-level-cache = <&L2>; - reg = <0x201>; - }; - - cpu@202 { - device_type = "cpu"; - compatible = "arm,cortex-a5"; - next-level-cache = <&L2>; - reg = <0x202>; - }; - - cpu@203 { - device_type = "cpu"; - compatible = "arm,cortex-a5"; - next-level-cache = <&L2>; - reg = <0x203>; - }; - }; - - clk81: clk@0 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; -}; - -&L2 { - interrupts = <0 143 1>; -}; diff --git a/sys/dts/arm/odroidc1.dts b/sys/dts/arm/odroidc1.dts deleted file mode 100644 index b9c05edf946..00000000000 --- a/sys/dts/arm/odroidc1.dts +++ /dev/null @@ -1,395 +0,0 @@ -/*- - * Copyright (c) 2015 John Wehle - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - */ - -/* - * The ordering of certain devices is significant (e.g. usb depends on - * usb-phy which depends on gpio, also the timer should appear early on - * to provide a reasonably accurate DELAY implementation). - * - * Both usb-phys devices must be configured to prevent the usb controller - * from hanging during initialization. - */ - -/dts-v1/; - -/memreserve/ 0x7900000 0x00600000; /* 6MB frame buffer */ - -#include "meson8b.dtsi" - -/ { - model = "hardkernel,odroid-c1"; - compatible = "hardkernel,odroid-c1", "amlogic,s805"; - - #address-cells = <1>; - #size-cells = <1>; - - aliases { - soc = &soc; - screen = &screen; - uart0 = &uart_AO; - }; - - memory { - device_type = "memory"; - reg = <0x0 0x40000000>; /* 1GB RAM */ - }; - - soc: soc { - device_type = "soc"; - bus-frequency = <0>; - - scu: scu@c4300000 { - compatible = "arm,cortex-a5-scu"; - reg = <0xc4300000 0x1000>; - }; - - cpuconfig: cpuconfig@d901ff80 { - compatible = "amlogic,aml8726-cpuconfig"; - reg = <0xd901ff80 16>; - }; - - ccm@c1104140 { - compatible = "amlogic,aml8726-ccm"; - reg = <0xc1104140 20>; /* cbus 0x1050 */ - - functions = "ethernet", "i2c", "rng", "sdio", "sdxc", - "uart-a", "uart-b", "uart-c", - "usb-a", "usb-b"; - }; - - pinctrl@c11080b0 { - compatible = "amlogic,aml8726-pinctrl"; - reg = <0xc11080b0 40>, /* mux */ - <0xc11080e8 24>, /* pu/pd */ - <0xc1108120 24>, /* pull enable */ - <0xc8100014 4>, /* ao mux */ - <0xc810002c 4>, /* ao pu/pd */ - <0xc810002c 4>; /* ao pull enable */ - - /* - * Currently only pin muxing that deviates - * from the power on default of gpio is - * specified here. - */ - - pinctrl-names = "default"; - pinctrl-0 = <&pins_uartao &pins_ethernet &pins_hdmi>; - - pins_ethernet: ethernet { - amlogic,pins = "ref_clk", - "tx_clk", "tx_en", - "tx_d0", "tx_d1", - "tx_d2", "tx_d3", - "rx_clk", "rx_dv", - "rx_d0", "rx_d1", - "rx_d2", "rx_d3", - "mdc", "mdio"; - amlogic,function = "ethernet"; - }; - - pins_hdmi: hdmi { - amlogic,pins = "cec", "hpd", - "scl", "sda"; - amlogic,function = "hdmi"; - }; - - pins_sdio_b: sdio_b { - amlogic,pins = "clk", "cmd", - "d0", "d1", - "d2", "d3"; - amlogic,function = "sdio-b"; - amlogic,pull = "up"; - }; - - pins_sdxc_b: sdxc_b { - amlogic,pins = "clk", "cmd", - "d0", "d1", - "d2", "d3"; - amlogic,function = "sdxc-b"; - amlogic,pull = "up"; - }; - - pins_sdio_c: sdio_c { - amlogic,pins = "clk", "cmd", - "d0", "d1", - "d2", "d3"; - amlogic,function = "sdio-c"; - amlogic,pull = "up"; - }; - - pins_sdxc_c: sdxc_c { - amlogic,pins = "clk", "cmd", - "d0", "d1", - "d2", "d3", - "d4", "d5", - "d6", "d7"; - amlogic,function = "sdxc-c"; - amlogic,pull = "up"; - }; - - pins_i2c_a: i2c_a { - amlogic,pins = "scl", "sda"; - amlogic,function = "i2c-a"; - }; - - pins_i2c_b: i2c_b { - amlogic,pins = "scl", "sda"; - amlogic,function = "i2c-b"; - }; - - pins_uarta: uarta { - amlogic,pins = "tx", "rx", "cts", "rts"; - amlogic,function = "uart-a"; - }; - - pins_uartb: uartb { - - /* - * gpiox18 appears to have special - * meaning to the bootloader making - * hardware handshaking unavailable. - */ - - amlogic,pins = "tx", "rx"; - amlogic,function = "uart-b"; - }; - - pins_uartc: uartc { - amlogic,pins = "tx", "rx", "cts", "rts"; - amlogic,function = "uart-c"; - }; - - pins_uartao: uartao { - amlogic,pins = "tx", "rx"; - amlogic,function = "uart-ao"; - }; - }; - - rtc@c8100740 { - compatible = "amlogic,aml8726-rtc"; - reg = <0xc8100740 20>; /* aobus 0x1d0 */ - interrupts = <0 72 1>; - }; - - clkmsr: clkmsr@c1108758 { - compatible = "amlogic,aml8726-clkmsr"; - reg = <0xc1108758 16>; /* cbus 0x21d6 */ - - clocks = <&clk81>; - }; - - gpioao: gpio@c8100024 { - /* gpio unit 7 */ - compatible = "amlogic,aml8726-gpio"; - reg = <0xc8100024 4>, /* oen aobus 0x9 */ - <0xc8100024 4>, /* out */ - <0xc8100028 4>; /* in */ - - gpio-controller; - #gpio-cells = <1>; - pin-count = <14>; - }; - - gpio3: gpio@c1108054 { - compatible = "amlogic,aml8726-gpio"; - reg = <0xc1108054 4>, /* oen cbus 0x2015 */ - <0xc1108058 4>, /* out */ - <0xc110805c 4>; /* in */ - - gpio-controller; - #gpio-cells = <1>; - pin-count = <32>; - }; - - gpio5: gpio@c110806c { - compatible = "amlogic,aml8726-gpio"; - reg = <0xc110806c 4>, /* oen cbus 0x201b */ - <0xc1108070 4>, /* out */ - <0xc1108074 4>; /* in */ - - gpio-controller; - #gpio-cells = <1>; - pin-count = <32>; - }; - - mmc@c1108c20 { - compatible = "amlogic,aml8726-mmc"; - reg = <0xc1108c20 32>; /* cbus 0x2308 */ - interrupts = <0 28 1>; - - clocks = <&clk81>; - - pinctrl-names = "default"; - pinctrl-0 = <&pins_sdio_b>; - - /* - * Ordering is significant. - * - * mmc-vselect low sets first voltage - * mmc-vselect high sets second voltage - * - * If mmc-vselect is not present, then - * only one voltage should be specified. - */ - mmc-voltages = "3.3", "1.8"; - mmc-vselect = <&gpioao 3>; /* gpioao_3 */ - - mmc-pwr-en = <&gpio5 31 0>; /* card_8 */ - ins-detect = <&gpio5 29 0>; /* card_6 */ - }; - - sdxc@c1108e00 { - compatible = "amlogic,aml8726-sdxc-m8"; - clock-frequency = <1275000000>; - reg = <0xc1108e00 60>; /* cbus 0x2380 */ - interrupts = <0 78 1>; - - pinctrl-names = "default"; - pinctrl-0 = <&pins_sdxc_c>; - - mmc-voltages = "1.8"; - - mmc-rst = <&gpio3 9 0>; /* boot_9 emmc-rst */ - }; - - rng@c1108100 { - compatible = "amlogic,aml8726-rng"; - reg = <0xc1108100 8>; /* cbus 0x2040 */ - }; - - usb-phy@c1108800 { - /* usb-a phy */ - compatible = "amlogic,aml8726-m8-usb-phy"; - reg = <0xc1108800 32>; /* cbus 0x2200 */ - - usb-pwr-en = <&gpioao 5 1>; /* gpioao_5 vbus */ - }; - - usb-phy@c1108820 { - /* usb-b phy */ - compatible = "amlogic,aml8726-m8-usb-phy"; - reg = <0xc1108820 32>; /* cbus 0x2208 */ - - force-aca = "true"; - usb-hub-rst = <&gpioao 4 0>; /* gpioao_4 hub-rst */ - }; - - usb@c9040000 { - /* usb-a */ - compatible = "synopsys,designware-hs-otg2"; - reg = <0xc9040000 0x40000>; /* ahbbus 0x40000*/ - interrupts = <0 30 4>; - #address-cells = <1>; - #size-cells = <0>; - - dr_mode = "host"; - }; - - usb@c90c0000 { - /* usb-b */ - compatible = "synopsys,designware-hs-otg2"; - reg = <0xc90c0000 0x40000>; /* ahbbus 0xc0000 */ - interrupts = <0 31 4>; - #address-cells = <1>; - #size-cells = <0>; - - dr_mode = "host"; - }; - - eth@c9410000 { - /* ethernet */ - compatible = "amlogic,meson6-dwmac"; - reg = <0xc9410000 0x2000>; /* ahbbus 0x410000 */ - interrupts = <0 8 1>; - #address-cells = <1>; - #size-cells = <0>; - - eth-phy-rst = <&gpio3 23 0>; /* gpioh_4 phy-rst */ - }; - - screen: fb@c8006020 { - device_type = "display"; - compatible = "amlogic,aml8726-fb"; - reg = <0xc8006048 12>, /* CANVAS */ - <0xc1106800 1024>, /* VIU */ - <0xc1107400 1024>; /* VPP */ - interrupts = <0 2 1>, - <0 3 1>, - <0 12 1>, - <0 13 1>; - - address = <0x7900000>; /* match memreserve */ - width = <720>; - height = <480>; - depth = <24>; - linebytes = <2160>; - }; - }; - - leds { - compatible = "gpio-leds"; - - sys_led { - gpios = <&gpioao 13>; /* gpioao_13 sys_led */ - label = "sys_led"; - }; - }; - - chosen { - stdin = "uart0"; - stdout = "uart0"; - }; -}; - -&clk81 { - clock-frequency = <0>; -}; - -&uart_AO { - status = "okay"; - current-speed = <115200>; -}; - -&uart_A { - status = "okay"; -}; - -&uart_B { - status = "okay"; -}; - -&uart_C { - status = "okay"; -}; - -&i2c_A { - status = "okay"; -}; - -&i2c_B { - status = "okay"; -}; diff --git a/sys/dts/arm/pandaboard-common.dtsi b/sys/dts/arm/pandaboard-common.dtsi deleted file mode 100644 index fed8a19a86e..00000000000 --- a/sys/dts/arm/pandaboard-common.dtsi +++ /dev/null @@ -1,52 +0,0 @@ -/*- - * Copyright (c) 2015 Oleksandr Tymoshenko - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - */ - -&mmc1 { - non-removable; /* XXX need real solution */ -}; - -&mmc5 { - status = "disabled"; -}; - -/ { - ocp { - global-timer@48240600 { - compatible = "arm,cortex-a9-global-timer"; - reg = <0x48240200 0x20>; - interrupts = ; - }; - - elm: elm@48078000 { - interrupts = ; - }; - }; - chosen { - stdin = "serial2"; - stdout = "serial2"; - }; -}; diff --git a/sys/dts/arm/pandaboard-es.dts b/sys/dts/arm/pandaboard-es.dts deleted file mode 100644 index 36c9eb312c1..00000000000 --- a/sys/dts/arm/pandaboard-es.dts +++ /dev/null @@ -1,30 +0,0 @@ -/*- - * Copyright (c) 2015 Oleksandr Tymoshenko - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - */ - - -#include "omap4-panda-es.dts" -#include "pandaboard-common.dtsi" diff --git a/sys/dts/arm/pandaboard.dts b/sys/dts/arm/pandaboard.dts deleted file mode 100644 index c43fd330bee..00000000000 --- a/sys/dts/arm/pandaboard.dts +++ /dev/null @@ -1,30 +0,0 @@ -/*- - * Copyright (c) 2015 Oleksandr Tymoshenko - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - */ - - -#include "omap4-panda.dts" -#include "pandaboard-common.dtsi" diff --git a/sys/dts/arm/rk3188-radxa-lite.dts b/sys/dts/arm/rk3188-radxa-lite.dts deleted file mode 100644 index 8cec1ed568a..00000000000 --- a/sys/dts/arm/rk3188-radxa-lite.dts +++ /dev/null @@ -1,62 +0,0 @@ -/*- - * Copyright (c) 2014 Ganbold Tsagaankhuu - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - */ - -/dts-v1/; - -/include/ "rk3188.dtsi" - -/ { - model = "Radxa RadxaRock Lite"; - - memory { - device_type = "memory"; - reg = < 0x60000000 0x40000000 >; /* 1GB RAM */ - }; - - aliases { - soc = &SOC; - }; - - SOC: rk3188 { - - uart2: serial@20064000 { - status = "okay"; - }; - - mmc@10214000 { - status = "okay"; - }; - - }; - - chosen { - bootargs = "-v"; - stdin = &uart2; - stdout = &uart2; - }; -}; - diff --git a/sys/dts/arm/rk3188-radxa.dts b/sys/dts/arm/rk3188-radxa.dts deleted file mode 100644 index 1b20a3d2d11..00000000000 --- a/sys/dts/arm/rk3188-radxa.dts +++ /dev/null @@ -1,62 +0,0 @@ -/*- - * Copyright (c) 2013 Ganbold Tsagaankhuu - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - */ - -/dts-v1/; - -/include/ "rk3188.dtsi" - -/ { - model = "Radxa RadxaRock"; - - memory { - device_type = "memory"; - reg = < 0x60000000 0x80000000 >; /* 2GB RAM */ - }; - - aliases { - soc = &SOC; - }; - - SOC: rk3188 { - - uart2: serial@20064000 { - status = "okay"; - }; - - mmc@10214000 { - status = "okay"; - }; - - }; - - chosen { - bootargs = "-v"; - stdin = &uart2; - stdout = &uart2; - }; -}; - diff --git a/sys/dts/arm/rk3188.dtsi b/sys/dts/arm/rk3188.dtsi deleted file mode 100644 index dc9ee14ee32..00000000000 --- a/sys/dts/arm/rk3188.dtsi +++ /dev/null @@ -1,253 +0,0 @@ -/*- - * Copyright (c) 2013 Ganbold Tsagaankhuu - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - */ - -/ { - compatible = "rockchip,rk3188"; - #address-cells = <1>; - #size-cells = <1>; - - interrupt-parent = <&GIC>; - - aliases { - soc = &SOC; - }; - - SOC: rk3188 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges; - bus-frequency = <0>; - - GIC: interrupt-controller@1013d000 { - compatible = "arm,gic"; - reg = <0x1013d000 0x1000>, /* Distributor Registers */ - <0x1013c100 0x0100>; /* CPU Interface Registers */ - interrupt-controller; - #interrupt-cells = <1>; - }; - - pmu@20004000 { - compatible = "rockchip,rk30xx-pmu"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x20004000 0x100>; - }; - - grf@20008000 { - compatible = "rockchip,rk30xx-grf"; - #address-cells = <1>; - #size-cells = <1>; - reg = < 0x20008000 0x2000 >; - }; - - mp_tmr@1013c600 { - compatible = "arm,mpcore-timers"; - #address-cells = <1>; - #size-cells = <0>; - clock-frequency = < 148500000 >; - reg = <0x1013c200 0x100>, /* Global Timer Regs */ - <0x1013c600 0x20>; /* Private Timer Regs */ - interrupts = < 27 29 >; - interrupt-parent = <&GIC>; - }; - - timer@20038000 { - compatible = "rockchip,rk30xx-timer"; - reg = <0x20038000 0x20>; - interrupts = <76>; - clock-frequency = <24000000>; - status = "disabled"; - }; - - timer@20038020 { - compatible = "rockchip,rk30xx-timer"; - reg = <0x20038020 0x20>; - interrupts = <77>; - clock-frequency = <24000000>; - status = "disabled"; - }; - - timer@20038060 { - compatible = "rockchip,rk30xx-timer"; - reg = <0x20038060 0x20>; - interrupts = <91>; - clock-frequency = <24000000>; - status = "disabled"; - }; - - timer@20038080 { - compatible = "rockchip,rk30xx-timer"; - reg = <0x20038080 0x20>; - interrupts = <92>; - clock-frequency = <24000000>; - status = "disabled"; - }; - - timer@200380a0 { - compatible = "rockchip,rk30xx-timer"; - reg = <0x200380a0 0x20>; - interrupts = <96>; - clock-frequency = <24000000>; - status = "disabled"; - }; - - watchdog@2004c000 { - compatible = "rockchip,rk30xx-wdt"; - reg = <0x2004c000 0x100>; - clock-frequency = < 66000000 >; - }; - - gpio0: gpio@2000a000 { - compatible = "rockchip,rk30xx-gpio"; - gpio-controller; - #gpio-cells = <2>; - reg = <0x2000a000 0x100>; - interrupts = <86>; - interrupt-parent = <&GIC>; - }; - - gpio1: gpio@2003c000 { - compatible = "rockchip,rk30xx-gpio"; - gpio-controller; - #gpio-cells = <2>; - reg = <0x2003c000 0x100>; - interrupts = <87>; - interrupt-parent = <&GIC>; - }; - - gpio2: gpio@2003e000 { - compatible = "rockchip,rk30xx-gpio"; - gpio-controller; - #gpio-cells = <2>; - reg = <0x2003e000 0x100>; - interrupts = <88>; - interrupt-parent = <&GIC>; - }; - - gpio3: gpio@20080000 { - compatible = "rockchip,rk30xx-gpio"; - gpio-controller; - #gpio-cells = <2>; - reg = <0x20080000 0x100>; - interrupts = <89>; - interrupt-parent = <&GIC>; - }; - - usb0: usb@10180000 { - compatible = "synopsys,designware-hs-otg2"; - reg = <0x10180000 0x40000>; - interrupts = <48>; - interrupt-parent = <&GIC>; - #address-cells = <1>; - #size-cells = <0>; - }; - - usb1: usb@101c0000 { - compatible = "synopsys,designware-hs-otg2"; - reg = <0x101c0000 0x40000>; - interrupts = < 49 >; - interrupt-parent = <&GIC>; - #address-cells = <1>; - #size-cells = <0>; - gpios = <&gpio0 3 2 2>; - }; - - uart0: serial@10124000 { - compatible = "snps,dw-apb-uart"; - reg = <0x10124000 0x400>; - reg-shift = <2>; - interrupts = <66>; - interrupt-parent = <&GIC>; - current-speed = <115200>; - clock-frequency = < 24000000 >; - broken-txfifo = <1>; - status = "disabled"; - }; - - uart1: serial@10126000 { - compatible = "snps,dw-apb-uart"; - reg = <0x10126000 0x400>; - reg-shift = <2>; - interrupts = <67>; - interrupt-parent = <&GIC>; - current-speed = <115200>; - clock-frequency = < 24000000 >; - broken-txfifo = <1>; - status = "disabled"; - }; - - uart2: serial@20064000 { - compatible = "snps,dw-apb-uart"; - reg = <0x20064000 0x400>; - reg-shift = <2>; - interrupts = <68>; - interrupt-parent = <&GIC>; - current-speed = <115200>; - clock-frequency = < 24000000 >; - broken-txfifo = <1>; - status = "disabled"; - }; - - uart3: serial@20068000 { - compatible = "snps,dw-apb-uart"; - reg = <0x20068000 0x400>; - reg-shift = <2>; - interrupts = <69>; - interrupt-parent = <&GIC>; - current-speed = <115200>; - clock-frequency = < 24000000 >; - broken-txfifo = <1>; - status = "disabled"; - }; - - mmc@10214000 { - compatible = "rockchip,rk2928-dw-mshc"; - reg = <0x10214000 0x1000>; - interrupts = <55>; - #address-cells = <1>; - #size-cells = <0>; - bus-frequency = <48000000>; /* TODO: verify freq */ - fifo-depth = <0x40>; - num-slots = <1>; - status = "disabled"; - }; - - mmc@10218000 { - compatible = "rockchip,rk2928-dw-mshc"; - reg = <0x10218000 0x1000>; - interrupts = <56>; - #address-cells = <1>; - #size-cells = <0>; - bus-frequency = <48000000>; /* TODO: verify freq */ - fifo-depth = <0x40>; - num-slots = <1>; - status = "disabled"; - }; - }; -}; - diff --git a/sys/dts/arm/rpi.dts b/sys/dts/arm/rpi.dts deleted file mode 100644 index 2bebb8c786c..00000000000 --- a/sys/dts/arm/rpi.dts +++ /dev/null @@ -1,104 +0,0 @@ -/* - * Copyright (c) 2012 Oleksandr Tymoshenko - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - */ - -#include "bcm2835-rpi-b.dts" - -/ { - /* This is only necessary for FDT_DTB_STATIC */ - memory { - device_type = "memory"; - reg = <0 0x8000000>; /* 128MB, Set by VideoCore */ - - }; - - rpi_ft5406 { - compatible = "rpi,rpi-ft5406"; - status = "okay"; - }; - - - /* Temporary patches */ - soc { - sdhost: mmc@7e202000 { - status = "disabled"; - } - - sdhci@7e300000 { - status = "okay"; - }; - - spi@7e204000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins &spi0_cs_pins>; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins &spi0_cs_pins>; - }; - - gpio@7e200000 { - /* Pins that can short 3.3V to GND in output mode: 46-47 - * Pins used by VideoCore: 48-53 - */ - broadcom,read-only = <46>, <47>, <48>, <49>, <50>, - <51>, <52>, <53>; - - /* Reserved */ - pins_reserved: reserved { - broadcom,pins = <48>, <49>, <50>, <51>, <52>, - <53>; - }; - - spi0_pins: spi0_pins { - brcm,pins = <9 10 11>; - brcm,function = <4>; /* alt0 */ - }; - - spi0_cs_pins: spi0_cs_pins { - brcm,pins = <8 7>; - brcm,function = <1>; /* output */ - }; - } - - vchiq { - compatible = "brcm,bcm2835-vchiq"; - reg = <0x7e00b840 0xf>; - interrupts = <0 2>; - cache-line-size = <32>; - }; - - display { - compatible = "broadcom,bcm2835-fb", "broadcom,bcm2708-fb"; - - broadcom,vc-mailbox = <&mailbox>; - broadcom,vc-channel = <1>; - - broadcom,width = <0>; /* Set by VideoCore */ - broadcom,height = <0>; /* Set by VideoCore */ - broadcom,depth = <0>; /* Set by VideoCore */ - }; - - }; -}; diff --git a/sys/dts/arm/rpi2.dts b/sys/dts/arm/rpi2.dts deleted file mode 100644 index 3680bcc9d14..00000000000 --- a/sys/dts/arm/rpi2.dts +++ /dev/null @@ -1,102 +0,0 @@ -/* - * Copyright (c) 2012 Oleksandr Tymoshenko - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - */ - -#include "bcm2836-rpi-2-b.dts" - -/ { - /* This is only necessary for FDT_DTB_STATIC */ - memory { - device_type = "memory"; - reg = <0 0x8000000>; /* 128MB, Set by VideoCore */ - - }; - - rpi_ft5406 { - compatible = "rpi,rpi-ft5406"; - status = "okay"; - }; - - - /* Temporary patches */ - soc { - sdhost: mmc@7e202000 { - status = "disabled"; - } - - sdhci@7e300000 { - status = "okay"; - }; - - spi@7e204000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins &spi0_cs_pins>; - }; - - gpio@7e200000 { - /* Pins that can short 3.3V to GND in output mode: 46-47 - * Pins used by VideoCore: 48-53 - */ - broadcom,read-only = <46>, <47>, <48>, <49>, <50>, - <51>, <52>, <53>; - - /* Reserved */ - pins_reserved: reserved { - broadcom,pins = <48>, <49>, <50>, <51>, <52>, - <53>; - }; - - spi0_pins: spi0_pins { - brcm,pins = <9 10 11>; - brcm,function = <4>; /* alt0 */ - }; - - spi0_cs_pins: spi0_cs_pins { - brcm,pins = <8 7>; - brcm,function = <1>; /* output */ - }; - } - - vchiq { - compatible = "brcm,bcm2835-vchiq"; - reg = <0x7e00b840 0xf>; - interrupts = <0 2>; - cache-line-size = <32>; - }; - - display { - compatible = "broadcom,bcm2835-fb", "broadcom,bcm2708-fb"; - - broadcom,vc-mailbox = <&mailbox>; - broadcom,vc-channel = <1>; - - broadcom,width = <0>; /* Set by VideoCore */ - broadcom,height = <0>; /* Set by VideoCore */ - broadcom,depth = <0>; /* Set by VideoCore */ - }; - - }; -}; diff --git a/sys/fs/fifofs/fifo.h b/sys/fs/fifofs/fifo.h deleted file mode 100644 index 1b9bdeac186..00000000000 --- a/sys/fs/fifofs/fifo.h +++ /dev/null @@ -1,37 +0,0 @@ -/*- - * Copyright (c) 1991, 1993 - * The Regents of the University of California. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 4. Neither the name of the University nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @(#)fifo.h 8.6 (Berkeley) 5/21/95 - */ - -/* - * Prototypes for fifo operations on vnodes. - */ -int fifo_vnoperate(struct vop_generic_args *); -int fifo_printinfo(struct vnode *); - diff --git a/sys/fs/hpfs/hpfs.h b/sys/fs/hpfs/hpfs.h deleted file mode 100644 index 3dd0cd6e05b..00000000000 --- a/sys/fs/hpfs/hpfs.h +++ /dev/null @@ -1,386 +0,0 @@ -/*- - * Copyright (c) 1998, 1999 Semen Ustimenko (semenu@FreeBSD.org) - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - */ - -/*#define HPFS_DEBUG 10*/ -typedef u_int32_t lsn_t; /* Logical Sector Number */ -typedef struct { - lsn_t lsn1; - lsn_t lsn2; -} rsp_t; /* Redundant Sector Pointer */ -typedef struct { - u_int32_t cnt; - lsn_t lsn; -} sptr_t; /* Storage Pointer */ - -#define SUBLOCK 0x10 -#define SUSIZE DEV_BSIZE -#define SPBLOCK 0x11 -#define SPSIZE DEV_BSIZE -#define BMSIZE (4 * DEV_BSIZE) -#define HPFS_MAXFILENAME 255 - -#define SU_MAGIC ((u_int64_t)0xFA53E9C5F995E849) -struct sublock { - u_int64_t su_magic; - u_int8_t su_hpfsver; - u_int8_t su_fnctver; - u_int16_t unused; - lsn_t su_rootfno; /* Root Fnode */ - u_int32_t su_btotal; /* Total blocks */ - u_int32_t su_badbtotal; /* Bad Sectors total */ - rsp_t su_bitmap; - rsp_t su_badbl; - u_long su_chkdskdate; - u_long su_dskoptdate; - u_int32_t su_dbbsz; /* Sectors in DirBlock Band */ - lsn_t su_dbbstart; - lsn_t su_dbbend; - lsn_t su_dbbbitmap; - char su_volname[0x20]; - lsn_t su_uidt; /* Ptr to User ID Table (8 sect) */ -}; - -#define SP_MAGIC ((u_int64_t)0xFA5229C5F9911849) -#define SP_DIRTY 0x0001 -#define SP_SPDBINUSE 0x0002 -#define SP_HFINUSE 0x0004 -#define SP_BADSECT 0x0008 -#define SP_BADBMBL 0x0010 -#define SP_FASTFRMT 0x0020 -#define SP_OLDHPFS 0x0080 -#define SP_IDASD 0x0100 -#define SP_RDASD 0x0200 -#define SP_DASD 0x0400 -#define SP_MMACTIVE 0x0800 -#define SP_DCEACLS 0x1000 -#define SP_DSADDIRTY 0x2000 -struct spblock { - u_int64_t sp_magic; - u_int16_t sp_flag; - u_int8_t sp_mmcontf; - u_int8_t unused; - lsn_t sp_hf; /* HotFix list */ - u_int32_t sp_hfinuse; /* HotFixes in use */ - u_int32_t sp_hfavail; /* HotFixes available */ - u_int32_t sp_spdbavail; /* Spare DirBlocks available */ - u_int32_t sp_spdbmax; /* Spare DirBlocks maximum */ - lsn_t sp_cpi; - u_int32_t sp_cpinum; - u_int32_t sp_suchecksum; - u_int32_t sp_spchecksum; - u_int8_t reserved[0x3C]; - lsn_t sp_spdb[0x65]; -}; - -#define DE_SPECIAL 0x0001 -#define DE_ACL 0x0002 -#define DE_DOWN 0x0004 -#define DE_END 0x0008 -#define DE_EALIST 0x0010 -#define DE_EPERM 0x0020 -#define DE_EXPLACL 0x0040 -#define DE_NEEDEA 0x0080 -#define DE_RONLY 0x0100 -#define DE_HIDDEN 0x0200 -#define DE_SYSTEM 0x0400 -#define DE_VOLLABEL 0x0800 -#define DE_DIR 0x1000 -#define DE_ARCHIV 0x2000 -#define DE_DOWNLSN(dep) (*(lsn_t *)((caddr_t)(dep) + (dep)->de_reclen - sizeof(lsn_t))) -#define DE_NEXTDE(dep) ((struct hpfsdirent *)((caddr_t)(dep) + (dep)->de_reclen)) -typedef struct hpfsdirent { - u_int16_t de_reclen; - u_int16_t de_flag; - lsn_t de_fnode; - u_long de_mtime; - u_int32_t de_size; - u_long de_atime; - u_long de_ctime; - u_int32_t de_ealen; - u_int8_t de_flexflag; - u_int8_t de_cpid; - u_int8_t de_namelen; - char de_name[1]; -/* ... de_flex; */ -/* lsn_t de_down; */ -} hpfsdirent_t; - -#define D_BSIZE (DEV_BSIZE*4) -#define D_MAGIC 0x77E40AAE -#define D_DIRENT(dbp) ((hpfsdirent_t *)((caddr_t)dbp + sizeof(dirblk_t))) -#define D_DE(dbp, deoff) ((hpfsdirent_t *)((caddr_t)dbp + sizeof(dirblk_t) + (deoff))) -typedef struct dirblk { - u_int32_t d_magic; - u_int32_t d_freeoff; /* Offset of first free byte */ - u_int32_t d_chcnt; /* Change count */ - lsn_t d_parent; - lsn_t d_self; -} dirblk_t; - -/* - * Allocation Block (ALBLK) - */ -#define AB_HBOFFEO 0x01 -#define AB_FNPARENT 0x20 -#define AB_SUGGBSCH 0x40 -#define AB_NODES 0x80 -#define AB_ALLEAF(abp) ((alleaf_t *)((caddr_t)(abp) + sizeof(alblk_t))) -#define AB_ALNODE(abp) ((alnode_t *)((caddr_t)(abp) + sizeof(alblk_t))) -#define AB_FREEALP(abp) ((alleaf_t *)((caddr_t)(abp) + (abp)->ab_freeoff)) -#define AB_FREEANP(abp) ((alnode_t *)((caddr_t)(abp) + (abp)->ab_freeoff)) -#define AB_LASTALP(abp) (AB_ALLEAF(abp) + (abp)->ab_busycnt - 1) -#define AB_LASTANP(abp) (AB_ALNODE(abp) + (abp)->ab_busycnt - 1) -#define AB_ADDNREC(abp, sz, n) { \ - (abp)->ab_busycnt += (n); \ - (abp)->ab_freecnt -= (n); \ - (abp)->ab_freeoff += (n) * (sz); \ -} -#define AB_RMNREC(abp, sz, n) { \ - (abp)->ab_busycnt -= (n); \ - (abp)->ab_freecnt += (n); \ - (abp)->ab_freeoff -= (n) * (sz);\ -} -#define AB_ADDAL(abp) AB_ADDNREC(abp,sizeof(alleaf_t), 1) -#define AB_ADDAN(abp) AB_ADDNREC(abp,sizeof(alnode_t), 1) -#define AB_RMAL(abp) AB_RMNREC(abp,sizeof(alleaf_t), 1) -#define AB_RMAN(abp) AB_RMNREC(abp,sizeof(alnode_t), 1) -typedef struct alblk { - u_int8_t ab_flag; - u_int8_t ab_res[3]; - u_int8_t ab_freecnt; - u_int8_t ab_busycnt; - u_int16_t ab_freeoff; -} alblk_t; - -/* - * FNode - */ -#define FNODESIZE DEV_BSIZE -#define FN_MAGIC 0xF7E40AAE -struct fnode { - u_int32_t fn_magic; - u_int64_t fn_readhist; - u_int8_t fn_namelen; - char fn_name[0xF]; /* First 15 symbols or less */ - lsn_t fn_parent; - sptr_t fn_extacl; - u_int16_t fn_acllen; - u_int8_t fn_extaclflag; - u_int8_t fn_histbitcount; - sptr_t fn_extea; - u_int16_t fn_ealen; /* Len of EAs in Fnode */ - u_int8_t fn_exteaflag; /* EAs in exteas */ - u_int8_t fn_flag; - alblk_t fn_ab; - u_int8_t fn_abd[0x60]; - u_int32_t fn_size; - u_int32_t fn_reqea; - u_int8_t fn_uid[0x10]; - u_int16_t fn_intoff; - u_int8_t fn_1dasdthr; - u_int8_t fn_dasdthr; - u_int32_t fn_dasdlim; - u_int32_t fn_dasdusage; - u_int8_t fn_int[0x13c]; -}; - -#define EA_NAME(eap) ((char *)(((caddr_t)(eap)) + sizeof(struct ea))) -struct ea { - u_int8_t ea_type; /* 0 - plain val */ - /* 1 - sptr to val */ - /* 3 - lsn point to AlSec, cont. val */ - u_int8_t ea_namelen; - u_int16_t ea_vallen; - /*u_int8_t ea_name[]; */ - /*u_int8_t ea_val[]; */ -}; - -/* - * Allocation Block Data (ALNODE) - * - * NOTE: AlNodes are used when there are too many fragments - * to represent the data in the AlBlk - */ -#define AN_SET(anp,nextoff,lsn) { \ - (anp)->an_nextoff = (nextoff); \ - (anp)->an_lsn = (lsn); \ -} -typedef struct alnode { - u_int32_t an_nextoff; /* next node offset in blocks */ - lsn_t an_lsn; /* position of AlSec structure */ -} alnode_t; - -/* - * Allocaion Block Data (ALLEAF) - * - * NOTE: Leaves are used to point at contiguous block of data - * (a fragment or an "extent"); - */ -#define AL_SET(alp,off,len,lsn) { \ - (alp)->al_off = (off); \ - (alp)->al_len = (len); \ - (alp)->al_lsn = (lsn); \ -} -typedef struct alleaf { - u_int32_t al_off; /* offset in blocks */ - u_int32_t al_len; /* len in blocks */ - lsn_t al_lsn; /* phys position */ -} alleaf_t; - -/* - * Allocation Sector - * - * NOTE: AlSecs are not initialized before use, so they ussually - * look full of junk. Use the AlBlk tto validate the data. - */ -#define AS_MAGIC 0x37E40AAE -typedef struct alsec { - u_int32_t as_magic; - lsn_t as_self; - lsn_t as_parent; - alblk_t as_ab; - u_int8_t as_abd[0x1E0]; -} alsec_t; - -/* - * Code Page structures - */ -struct cpdblk { - u_int16_t b_country; /* Country code */ - u_int16_t b_cpid; /* CP ID */ - u_int16_t b_dbcscnt; /* Count of DBCS ranges in CP */ - char b_upcase[0x80]; /* Case conversion table */ - u_int16_t b_dbcsrange; /* Start/End DBCS range pairs */ - -}; - -#define CPD_MAGIC ((u_int32_t)0x894521F7) -struct cpdsec { - u_int32_t d_magic; - u_int16_t d_cpcnt; /* CP Data count */ - u_int16_t d_cpfirst; /* Index of first CP Data */ - u_int32_t d_checksum[3]; /* CP Data checksumms */ - u_int16_t d_offset[3]; /* Offsets of CP Data blocks */ - struct cpdblk d_cpdblk[3]; /* Array of CP Data Blocks */ -}; - -struct cpiblk { - u_int16_t b_country; /* Country code */ - u_int16_t b_cpid; /* CP ID */ - u_int32_t b_checksum; - lsn_t b_cpdsec; /* Pointer to CP Data Sector */ - u_int16_t b_vcpid; /* Volume spec. CP ID */ - u_int16_t b_dbcscnt; /* Count of DBCS ranges in CP */ -}; - -#define CPI_MAGIC ((u_int32_t)0x494521F7) -struct cpisec { - u_int32_t s_magic; - u_int32_t s_cpicnt; /* Count of CPI's in this sector */ - u_int32_t s_cpifirst; /* Index of first CPI in this sector */ - lsn_t s_next; /* Pointer to next CPI Sector */ - struct cpiblk s_cpi[0x1F]; /* Array of CPI blocks */ -}; - -struct hpfsmount { - struct sublock hpm_su; - struct spblock hpm_sp; - struct mount * hpm_mp; - struct vnode * hpm_devvp; /* XXX: lose this, it's in hpfsmount */ - struct g_consumer *hpm_cp; - struct bufobj *hpm_bo; - struct cdev *hpm_dev; - uid_t hpm_uid; - gid_t hpm_gid; - mode_t hpm_mode; - - lsn_t * hpm_bmind; - struct cpdblk * hpm_cpdblk; /* Array of CP Data Blocks */ - u_char hpm_u2d[0x80]; /* Unix to DOS Table*/ - u_char hpm_d2u[0x80]; /* DOS to Unix Table*/ - - u_long hpm_bavail; /* Blocks available */ - u_long hpm_dbnum; /* Data Band number */ - u_int8_t * hpm_bitmap; -}; - -#define H_PARVALID 0x0002 /* parent info is valid */ -#define H_CHANGE 0x0004 /* node date was changed */ -#define H_PARCHANGE 0x0008 /* parent node date was changed */ -#define H_INVAL 0x0010 /* Invalid node */ -struct hpfsnode { - struct mtx h_interlock; - - struct hpfsmount *h_hpmp; - struct fnode h_fn; - struct vnode * h_vp; - struct vnode * h_devvp; /* XXX: remove, hpfsmount has it */ - struct cdev *h_dev; - lsn_t h_no; - uid_t h_uid; - gid_t h_gid; - mode_t h_mode; - u_int32_t h_flag; - - /* parent dir information */ - u_long h_mtime; - u_long h_atime; - u_long h_ctime; - char h_name[HPFS_MAXFILENAME+1]; /* Used to speedup dirent */ - int h_namelen; /* lookup */ -}; - -/* This overlays the fid structure (see ) */ -struct hpfid { - u_int16_t hpfid_len; /* Length of structure. */ - u_int16_t hpfid_pad; /* Force 32-bit alignment. */ - lsn_t hpfid_ino; /* File number (ino). */ - int32_t hpfid_gen; /* Generation number. */ -}; - -#if defined(HPFS_DEBUG) -#define dprintf(a) printf a -#if HPFS_DEBUG > 1 -#define ddprintf(a) printf a -#else -#define ddprintf(a) -#endif -#else -#define dprintf(a) -#define ddprintf(a) -#endif - -#if __FreeBSD_version >= 300000 -MALLOC_DECLARE(M_HPFSMNT); -MALLOC_DECLARE(M_HPFSNO); -#endif -#define VFSTOHPFS(mp) ((struct hpfsmount *)((mp)->mnt_data)) -#define VTOHP(v) ((struct hpfsnode *)((v)->v_data)) -#define HPTOV(h) ((struct vnode *)((h)->h_vp)) -#define FID(f) (*((lsn_t *)(f)->fid_data)) - -extern struct vop_vector hpfs_vnodeops; diff --git a/sys/fs/hpfs/hpfs_alsubr.c b/sys/fs/hpfs/hpfs_alsubr.c deleted file mode 100644 index 187e086a0f1..00000000000 --- a/sys/fs/hpfs/hpfs_alsubr.c +++ /dev/null @@ -1,906 +0,0 @@ -/*- - * Copyright (c) 1998, 1999 Semen Ustimenko (semenu@FreeBSD.org) - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#define AE_DONE 0 /* Nothing to change */ -#define AE_SPLIT 2 /* Split was done, ranp is valid */ - -int hpfs_addextentr (struct hpfsmount *, lsn_t, alleaf_t *, - alnode_t *, u_long *); -int hpfs_allocalsec (struct hpfsmount *, lsn_t, struct buf **); -int hpfs_alblk2alsec (struct hpfsmount *, alblk_t *, alsec_t **, - struct buf **); -int hpfs_splitalsec (struct hpfsmount *, alsec_t *, alsec_t **, - struct buf **); -int hpfs_concatalsec (struct hpfsmount *, alsec_t *, alsec_t *, - alnode_t *); - -/* - * Map file offset to disk offset. hpfsnode have to be locked. - */ -int -hpfs_hpbmap(hp, bn, bnp, runp) - struct hpfsnode *hp; - daddr_t bn; - daddr_t *bnp; - int *runp; -{ - struct buf *bp; - alblk_t * abp; - alleaf_t *alp; - alnode_t *anp; - int error, i; - - dprintf(("hpfs_hpbmap(0x%x, 0x%x): ",hp->h_no, bn)); - - bp = NULL; - abp = &hp->h_fn.fn_ab; - alp = (alleaf_t *)&hp->h_fn.fn_abd; - anp = (alnode_t *)&hp->h_fn.fn_abd; - -dive: - if (abp->ab_flag & AB_NODES) { - for (i=0; iab_busycnt; i++, anp++) { - dprintf(("[0x%x,0x%x] ",anp->an_nextoff,anp->an_lsn)); - if (bn < anp->an_nextoff) { - alsec_t *asp; - - dprintf(("< found | ")); - - if (bp) - brelse(bp); - error = bread(hp->h_devvp, anp->an_lsn, - DEV_BSIZE, NOCRED, &bp); - if (error) { - printf("hpfs_hpbmap: bread error\n"); - brelse(bp); - return (error); - } - - asp = (alsec_t *) bp->b_data; - if (asp->as_magic != AS_MAGIC) { - brelse(bp); - printf("hpfs_hpbmap: " - "MAGIC DOESN'T MATCH"); - return (EINVAL); - } - - abp = &asp->as_ab; - alp = (alleaf_t *)&asp->as_abd; - anp = (alnode_t *)&asp->as_abd; - - goto dive; - } - } - } else { - for (i=0; iab_busycnt; i++, alp++) { - dprintf(("[0x%x,0x%x,0x%x] ", - alp->al_off,alp->al_len,alp->al_lsn)); - - if ((bn >= alp->al_off) && - (!alp->al_len || (bn < alp->al_off + alp->al_len))) { - dprintf(("found, ")); - - *bnp = bn - alp->al_off + alp->al_lsn; - - dprintf((" 0x%x ", *bnp)); - - if (runp != NULL) { - if (alp->al_len) - *runp = alp->al_off - 1 + - alp->al_len - bn; - else - *runp = 3; /* XXX */ - - dprintf((" 0x%x cont", *runp)); - } - - if (bp) - brelse(bp); - - dprintf(("\n")); - return (0); - } - } - } - - dprintf(("END, notfound\n")); - if (bp) - brelse(bp); - - dprintf(("hpfs_hpbmap: offset too big\n")); - - return (EFBIG); -} - -/* - * Find place and preinitialize AlSec structure - * AlBlk is initialized to contain AlLeafs. - */ -int -hpfs_allocalsec ( - struct hpfsmount *hpmp, - lsn_t parlsn, - struct buf **bpp) -{ - alsec_t * asp; - struct buf * bp; - lsn_t lsn; - int error; - - *bpp = NULL; - - error = hpfs_bmfblookup(hpmp, &lsn); - if (error) { - printf("hpfs_allocalsec: CAN'T ALLOC SPACE FOR AlSec\n"); - return (error); - } - - error = hpfs_bmmarkbusy(hpmp, lsn, 1); - if (error) - return (error); - - bp = getblk(hpmp->hpm_devvp, lsn, DEV_BSIZE, 0, 0, 0); - clrbuf(bp); - - /* Fill AlSec info */ - asp = (alsec_t *) bp->b_data; - asp->as_magic = AS_MAGIC; - asp->as_self = lsn; - asp->as_parent = parlsn; - - /* Fill AlBlk */ - asp->as_ab.ab_flag = 0; - asp->as_ab.ab_busycnt = 0; - asp->as_ab.ab_freecnt = 0x28; - asp->as_ab.ab_freeoff = sizeof(alblk_t); - - *bpp = bp; - - return (0); -} - -/* - * Split AlSec structure into new allocated: - * allocate new AlSec; then move second half of asp's entries in - * into it; set proper flags. - * - * IF AlSec CONTAINS AlNodes, THEN YOU ALMOST EVERYTIME HAVE TO - * FIX LAST AlNode in OLD AlSec (NEXTOFF TO BE 0xFFFFFFFF). - * TOGETHER WITH FIXING ALL CHILDREN'S AlSecs (THEY HAVE GOT NEW PARENT). - */ -int -hpfs_splitalsec ( - struct hpfsmount *hpmp, - alsec_t *asp, - alsec_t **naspp, - struct buf **nbpp) -{ - alsec_t *nasp; - struct buf *nbp; - alblk_t *abp; - alblk_t *nabp; - int error, n1, n2, sz; - - error = hpfs_allocalsec(hpmp, asp->as_parent, &nbp); - if (error) - return (error); - - nasp = (alsec_t *)nbp->b_data; - nabp = &nasp->as_ab; - abp = &asp->as_ab; - - n1 = (abp->ab_busycnt + 1) / 2; - n2 = (abp->ab_busycnt - n1); - sz = (abp->ab_flag & AB_NODES) ? sizeof(alnode_t) : sizeof(alleaf_t); - - bcopy((caddr_t)abp + sizeof(alblk_t) + n1 * sz, - (caddr_t)nabp + sizeof(alblk_t), n2 * sz); - - nabp->ab_flag = abp->ab_flag; - nabp->ab_busycnt = n2; - nabp->ab_freecnt = (0x1e0 / sz - n2); - nabp->ab_freeoff += n2 * sz; - - abp->ab_busycnt -= n1; - abp->ab_freecnt += n1; - abp->ab_freeoff -= n1 * sz; - - *naspp = nasp; - *nbpp = nbp; - - return (0); -} - -/* - * Try to concatenate two AlSec's - * - * Moves all entries from AlSec corresponding (as1p, aanp[1]) into - * corresponding aanp[0] one. If not enought space, then return ENOSPC. - * - * WARNING! YOU HAVE TO FIX aanp VALUES YOURSELF LATER: - * aanp[0].an_nextoff = aanp[1].an_nextoff; - */ -int -hpfs_concatalsec ( - struct hpfsmount *hpmp, - alsec_t *as0p, - alsec_t *as1p, - alnode_t *aanp) -{ - alblk_t *ab0p; - alblk_t *ab1p; - int sz; - - dprintf(("hpfs_concatalsec: AlSecs at 0x%x and 0x%x \n", - as0p->as_self,as1p->as_self)); - - ab0p = &as0p->as_ab; - ab1p = &as1p->as_ab; - sz = (ab0p->ab_flag & AB_NODES) ? sizeof(alnode_t) : sizeof(alleaf_t); - - if (ab0p->ab_freecnt > ab1p->ab_busycnt) { - /* - * Concatenate AlSecs - */ - if (ab0p->ab_flag & AB_NODES) - AB_LASTANP(ab0p)->an_nextoff = aanp[0].an_nextoff; - - bcopy (AB_ALNODE(ab1p), AB_FREEANP(ab0p), - ab1p->ab_busycnt * sz); - - AB_ADDNREC(ab0p, sz, ab1p->ab_busycnt); - - return (0); - } else { - /* Not enought space to concatenate */ - return (ENOSPC); - } -} - -/* - * Transform AlBlk structure into new allocated - * AlSec. - * - * DOESN'T SET AlSec'S PARENT LSN. - */ -int -hpfs_alblk2alsec ( - struct hpfsmount *hpmp, - alblk_t *abp, - alsec_t **naspp, - struct buf **nbpp) -{ - alsec_t *nasp; - alblk_t *nabp; - struct buf *nbp; - int error, sz; - - error = hpfs_allocalsec(hpmp, 0, &nbp); - if (error) - return (error); - - nasp = (alsec_t *)nbp->b_data; - nabp = &nasp->as_ab; - - sz = (abp->ab_flag & AB_NODES) ? sizeof(alnode_t) : sizeof(alleaf_t); - - bcopy (abp, nabp, sizeof(alblk_t) + sz * abp->ab_busycnt); - - nabp->ab_freecnt = 0x1e0 / sz - nabp->ab_busycnt; - - *naspp = nasp; - *nbpp = nbp; - - return (0); -} - -/* - * Allocate len blocks and concatenate them to file. - * If we hadn't found contignous run of len blocks, concatenate - * as much as we can, and return. - * - */ -int -hpfs_addextent ( - struct hpfsmount *hpmp, - struct hpfsnode *hp, - u_long len) -{ - alblk_t *rabp; - alnode_t ranp[2]; - alleaf_t al; - int error; - u_long pf; - - /* - * We don't know for now start lsn of block - */ - al.al_lsn = ~0; - al.al_len = len; - al.al_off = (hp->h_fn.fn_size + DEV_BSIZE - 1) >> DEV_BSHIFT; - - rabp = &hp->h_fn.fn_ab; - - /* Init AlBlk if this is first extent */ - if (al.al_off == 0) { - lsn_t nlsn; - u_long nlen; - - dprintf(("hpfs_addextent: init AlBlk in root\n")); - - rabp->ab_busycnt = 0; - rabp->ab_freecnt = 0x8; - rabp->ab_freeoff = sizeof(alblk_t); - rabp->ab_flag = 0; - - error = hpfs_bmlookup (hpmp, 0, hp->h_no + 1, al.al_len, &nlsn, &nlen); - if (error) - return (error); - - error = hpfs_bmmarkbusy(hpmp, nlsn, nlen); - if (error) - return (error); - - dprintf(("hpfs_addextent: new: 0x%x 0x%lx, ", nlsn, nlen)); - - AL_SET(AB_FREEALP(rabp), al.al_off, nlen, nlsn); - AB_ADDAL(rabp); - - al.al_off += nlen; - al.al_len -= nlen; - } - -retry: - dprintf(("hpfs_addextent: AlBlk: [0x%x, 0x%x, 0x%x] need: 0x%x\n", - rabp->ab_freecnt, rabp->ab_busycnt, rabp->ab_flag, al.al_len)); - - while ((al.al_len) && (rabp->ab_freecnt > 0)) { - if (rabp->ab_flag & AB_NODES) { - alnode_t *anp; - /* - * This is level containing AlNodes, so try to - * insert recursively into last entry. - */ - anp = AB_LASTANP(rabp); - dprintf(("hpfs_addextent: AlNode: [0x%x,0x%x] \n", - anp->an_nextoff,anp->an_lsn)); - - /* - * Try to insert... - */ - error = hpfs_addextentr (hpmp, anp->an_lsn, &al, ranp, &pf); - if (error) { - printf("hpfs_addextent: FAILED %d\n",error); - return (error); - } - - switch (pf) { - case AE_SPLIT: - dprintf(("hpfs_addextent: successful (split)\n")); - /* - * Then hpfs_addextentr has split tree below, now - * we need to fix this level. Particulary: - * fix last AlNode and add another one. - */ - - bcopy(ranp, AB_LASTANP(rabp), sizeof(alnode_t) * 2); - AB_ADDAN(rabp); - break; - - default: - case AE_DONE: - dprintf(("hpfs_addextent: successful\n")); - break; - } - } else { - alleaf_t *alp; - - alp = AB_LASTALP(rabp); - dprintf(("hpfs_addextent: AlLeaf: [0x%x,0x%x,0x%x] \n", - alp->al_off,alp->al_len,alp->al_lsn)); - - /* Check if we trying to add in right place */ - if (alp->al_off + alp->al_len == al.al_off) { - lsn_t nlsn; - u_long nlen; - - /* - * Search bitmap for block begining from - * alp->al_lsn + alp->al_len and long of ralp->al_len - */ - error = hpfs_bmlookup (hpmp, 0, - alp->al_lsn + alp->al_len, al.al_len, &nlsn, &nlen); - if (error) - return (error); - - error = hpfs_bmmarkbusy(hpmp, nlsn, nlen); - if (error) - return (error); - - dprintf(("hpfs_addextent: new: 0x%x 0x%lx, ", nlsn, nlen)); - - if (alp->al_lsn + alp->al_len == nlsn) { - dprintf(("extended existed leaf\n")); - - alp->al_len += nlen; - } else { - dprintf(("created new leaf\n")); - AL_SET(AB_FREEALP(rabp), al.al_off, nlen, nlsn); - AB_ADDAL(rabp); - } - al.al_off += nlen; - al.al_len -= nlen; - } else { - printf("hpfs_addextent: INTERNAL INCONSISTENCE\n"); - return (EINVAL); - } - } - } - - /* - * Move AlBlk contain to new AlSec (it will fit more - * entries) if overflowed (no more free entries). - */ - if (rabp->ab_freecnt <= 0) { - struct buf *nbp; - alsec_t * nrasp; - - dprintf(("hpfs_addextent: overflow, convt\n")); - - /* - * Convert AlBlk to new AlSec, it will set - * AB_FNPARENT also. - */ - rabp->ab_flag |= AB_FNPARENT; - error = hpfs_alblk2alsec (hpmp, rabp, &nrasp, &nbp); - if (error) { - printf("hpfs_addextent: CAN'T CONVT\n"); - return (error); - } - nrasp->as_parent = hp->h_no; - - /* - * Scan all childrens (if exist), set new parent and - * clean their AB_FNPARENT flag. - */ - if (rabp->ab_flag & AB_NODES) { - int i; - alsec_t * asp; - alnode_t * anp; - struct buf * bp; - - anp = AB_ALNODE(rabp); - for (i=0; iab_busycnt; i++) { - error = hpfs_breadalsec(hpmp, anp->an_lsn, &bp); - if (error) - return (error); - - asp = (alsec_t *)bp->b_data; - asp->as_ab.ab_flag &= ~AB_FNPARENT; - asp->as_parent = nrasp->as_self; - - bdwrite(bp); - anp ++; - } - } - - /* Convert AlBlk to contain AlNodes */ - rabp->ab_flag = AB_NODES; - rabp->ab_busycnt = 0; - rabp->ab_freecnt = 0xC; - rabp->ab_freeoff = sizeof(alblk_t); - - /* Add AlNode for new allocated AlSec */ - AN_SET(AB_FREEANP(rabp), ~0, nrasp->as_self); - AB_ADDAN(rabp); - - bdwrite(nbp); - } - - if (al.al_len) { - dprintf(("hpfs_addextent: root retry\n")); - goto retry; - } - - return (0); -} - -/* - * Descent down to the end of tree, then search for - * ralp->len contignous run begining from last run's end and - * concatenate new block! If we can't find one, then... - */ -int -hpfs_addextentr ( - struct hpfsmount *hpmp, /* Mix info */ - lsn_t rlsn, /* LSN containing AlSec */ - alleaf_t *ralp, /* AlLeaf to insert */ - alnode_t *ranp, /* New AlNodes' values */ - u_long *resp) /* Mix returning info */ -{ - struct buf *rbp; - alsec_t *rasp; - alblk_t *rabp; - alleaf_t *alp; - alnode_t *anp; - int error; - u_long pf; - u_long wb; - - *resp = 0; - - dprintf(("hpfs_addextentr: AlSec at 0x%x\n", rlsn)); - - error = hpfs_breadalsec(hpmp, rlsn, &rbp); - if (error) - return (error); - - rasp = (alsec_t *)rbp->b_data; - rabp = &rasp->as_ab; - wb = 0; - - dprintf(("hpfs_addextentr: AlBlk: [0x%x, 0x%x, 0x%x]\n", - rabp->ab_freecnt, rabp->ab_busycnt, rabp->ab_flag)); - - while ((ralp->al_len) && (rabp->ab_freecnt > 0)) { - if (rabp->ab_flag & AB_NODES) { - /* - * This is level containing AlNodes, so try to - * insert recursively into last entry. - */ - anp = AB_LASTANP(rabp); - dprintf(("hpfs_addextentr: AlNode: [0x%x,0x%x] \n", - anp->an_nextoff,anp->an_lsn)); - - /* - * Try to insert... - */ - error = hpfs_addextentr (hpmp, anp->an_lsn, ralp, ranp, &pf); - if (error) { - printf("hpfs_addextentr: FAILED %d\n",error); - goto fail; - } - - switch (pf) { - case AE_SPLIT: - dprintf(("hpfs_addextentr: successful (split)\n")); - /* - * Then hpfs_addextentr has split tree below, now - * we need to fix this level. Particulary: - * fix last AlNode and add another one. - */ - bcopy(ranp, AB_LASTANP(rabp), sizeof(alnode_t) * 2); - AB_ADDAN(rabp); - wb = 1; - break; - - default: - case AE_DONE: - dprintf(("hpfs_addextentr: successful\n")); - break; - } - } else { - alp = AB_LASTALP(rabp); - dprintf(("hpfs_addextentr: AlLeaf: [0x%x,0x%x,0x%x] \n", - alp->al_off,alp->al_len,alp->al_lsn)); - - /* Check if we trying to add in right place */ - if (alp->al_off + alp->al_len == ralp->al_off) { - lsn_t nlsn; - u_long nlen; - /* - * Search bitmap for block begining from - * alp->al_lsn + alp->al_len and long of ralp->al_len - */ - error = hpfs_bmlookup (hpmp, 0, - alp->al_lsn + alp->al_len, ralp->al_len, &nlsn, &nlen); - if (error) - goto fail; - - error = hpfs_bmmarkbusy(hpmp, nlsn, nlen); - if (error) - goto fail; - - dprintf(("hpfs_addextentr: new: 0x%x 0x%lx, ", nlsn, nlen)); - - /* - * If ending of existed entry fits the - * begining of the extent being added, - * then we add concatenate two extents. - */ - if (alp->al_lsn + alp->al_len == nlsn) { - dprintf(("concat\n")); - alp->al_len += nlen; - } else { - dprintf(("created new leaf\n")); - AL_SET(AB_FREEALP(rabp), ralp->al_off, nlen, nlsn); - AB_ADDAL(rabp); - } - - ralp->al_len -= nlen; - ralp->al_off += nlen; - } else { - printf("hpfs_addextentr: INTERNAL INCONSISTENCE\n"); - error = (EINVAL); - goto fail; - } - } - } - - /* - * Split AlBlk if overflowed. - */ - if (rabp->ab_freecnt <= 0) { - struct buf *nbp; - alsec_t * nrasp; - - dprintf(("hpfs_addextentr: overflow, split\n")); - - error = hpfs_splitalsec (hpmp, rasp, &nrasp, &nbp); - if (error) { - printf("hpfs_addextent: CAN'T SPLIT\n"); - goto fail; - } - - if (rabp->ab_flag & AB_NODES) { - int i; - alsec_t * asp; - alnode_t * anp; - struct buf * bp; - - ranp[0].an_nextoff = - AB_LASTANP(&rasp->as_ab)->an_nextoff; - - /* We need to set left subtree's last entry - * offset to 0xFFFFFFFF for OS/2 to be able - * to read our files. It treats absence of - * 0xFFFFFFFF as error. - */ - AB_LASTANP(&rasp->as_ab)->an_nextoff = ~0; - - /* We need to fix new allocated AlSec's - * children, becouse their parent has changed. - */ - anp = AB_ALNODE(&nrasp->as_ab); - for (i=0; ias_ab.ab_busycnt; i++) { - error = hpfs_breadalsec(hpmp, anp->an_lsn, &bp); - if (error) { - brelse(nbp); - goto fail; - } - - asp = (alsec_t *)bp->b_data; - asp->as_parent = nrasp->as_self; - - bdwrite(bp); - anp ++; - } - } else { - ranp[0].an_nextoff = - AB_ALLEAF(&nrasp->as_ab)->al_off; - } - - ranp[0].an_lsn = rasp->as_self; - ranp[1].an_nextoff = ~0; - ranp[1].an_lsn = nrasp->as_self; - - bdwrite(nbp); - - *resp = AE_SPLIT; - wb = 1; - } - - if (wb) - bdwrite (rbp); - else - brelse(rbp); - - return (0); - -fail: - brelse(rbp); - - return (error); -} - -/* - * Recursive routine walking down the b-tree and deallocating all - * extents above bn. Returns *resp != 0 if alblk was totally - * deallocated and may be freed. Tries to keep b-tree. - * - * (XXXX) NOTE! THIS ROUTINE WILL NEVER DECREMENT DEPTH OF - * THE TREE. - */ -int -hpfs_truncatealblk ( - struct hpfsmount *hpmp, - alblk_t *abp, - lsn_t bn, - int *resp) -{ - int error; - alleaf_t *alp; - alnode_t *anp; - alsec_t *asp; - struct buf *bp; - - dprintf(("hpfs_truncatealblk: AlBlk: [0x%x,0x%x, 0x%x]\n", - abp->ab_freecnt, abp->ab_busycnt, abp->ab_flag)); - - if (abp->ab_flag & AB_NODES) { - /* - * Scan array of AlNodes backward, - * diving in recursion if needed - */ - anp = AB_LASTANP(abp); - - while (abp->ab_busycnt && (bn <= anp->an_nextoff)) { - dprintf(("hpfs_truncatealblk: AlNode: [0x%x,0x%x] \n", - anp->an_nextoff,anp->an_lsn)); - - error = hpfs_breadalsec(hpmp, anp->an_lsn, &bp); - if (error) - return (error); - - asp = (alsec_t *)bp->b_data; - - error = hpfs_truncatealblk (hpmp, - &asp->as_ab, bn, resp); - if (error) { - brelse(bp); - return (error); - } - - if (*resp) { - brelse (bp); - - error = hpfs_bmmarkfree(hpmp, - anp->an_lsn, 1); - if (error) - return (error); - - AB_RMAN(abp); - anp --; - } else { - /* - * We have deallocated some entries, some space - * migth been freed, then try to concat two - * last AlSec. - */ - anp->an_nextoff = ~0; - if (abp->ab_busycnt >= 2) { - alsec_t *as0p; - struct buf *b0p; - - error = hpfs_breadalsec(hpmp, - (anp-1)->an_lsn, &b0p); - if (error) - return (error); - - as0p = (alsec_t *)b0p->b_data; - error = hpfs_concatalsec(hpmp, - as0p, asp, anp - 1); - if (error == ENOSPC) { - /* Not enought space */ - brelse (b0p); - bdwrite (bp); - } else if (error == 0) { - /* All OK */ - (anp-1)->an_nextoff = anp->an_nextoff; - - bdwrite (b0p); - brelse (bp); - - error = hpfs_bmmarkfree(hpmp, - anp->an_lsn, 1); - if (error) - return (error); - - AB_RMAN(abp); - } else { - /* True error */ - brelse (b0p); - brelse (bp); - return (error); - } - } else { - /* Nowhere to concatenate */ - bdwrite (bp); - } - - /* There can not be any more entries - * over greater bn, becouse last AlSec - * wasn't freed totally. So go out. - */ - break; - } - } - - if (abp->ab_busycnt == 0) - *resp = 1; - else - *resp = 0; - } else { - /* - * Scan array of AlLeafs backward, - * free all above bn. - */ - alp = AB_LASTALP(abp); - - while (abp->ab_busycnt && (bn < alp->al_off + alp->al_len)){ - dprintf(("hpfs_truncatealblk: AlLeaf: [0x%x,0x%x,0x%x] \n", - alp->al_off,alp->al_len,alp->al_lsn)); - - if (bn <= alp->al_off) { - error = hpfs_bmmarkfree(hpmp, alp->al_lsn, - alp->al_len); - if (error) - return (error); - - AB_RMAL(abp); - alp --; - } else if ((bn > alp->al_off) && - (bn < alp->al_off + alp->al_len)){ - error = hpfs_bmmarkfree(hpmp, - alp->al_lsn + bn - alp->al_off, - alp->al_len - bn + alp->al_off); - if (error) - return (error); - - alp->al_len = bn - alp->al_off; - - break; - } else - break; - } - } - - /* Signal parent deallocation, if need */ - if (abp->ab_busycnt == 0) - *resp = 1; - else - *resp = 0; - - return (0); -} diff --git a/sys/fs/hpfs/hpfs_ioctl.h b/sys/fs/hpfs/hpfs_ioctl.h deleted file mode 100644 index 53623c60324..00000000000 --- a/sys/fs/hpfs/hpfs_ioctl.h +++ /dev/null @@ -1,42 +0,0 @@ -/*- - * Copyright (c) 1998, 1999 Semen Ustimenko (semenu@FreeBSD.org) - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - */ - -#ifndef _HPFS_IOCTL_H_ -#define _HPFS_IOCTL_H_ -#include - -struct hpfs_rdea { - u_long ea_no; - u_long ea_sz; - void * ea_data; -}; - -#define HPFSIOCGEANUM _IOR('H', 0, u_long) /* Get EA number */ -#define HPFSIOCGEASZ _IOWR('H', 1, u_long) /* Get EA size */ -#define HPFSIOCRDEA _IOWR('H', 2, struct hpfs_rdea) /* Read EA */ - -#endif diff --git a/sys/fs/hpfs/hpfs_lookup.c b/sys/fs/hpfs/hpfs_lookup.c deleted file mode 100644 index 167c37d1298..00000000000 --- a/sys/fs/hpfs/hpfs_lookup.c +++ /dev/null @@ -1,212 +0,0 @@ -/*- - * Copyright (c) 1998, 1999 Semen Ustimenko (semenu@FreeBSD.org) - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -int hpfs_removedirent (struct hpfsmount *, lsn_t, char *, int, int *); - -/* - * This routine traverse the b+ tree representing directory - * looking for file named 'name'. Returns buf struct and hpfsdirent - * pointer. Calling routine is supposed to brelse buffer. - * name is supposed in Unix encodeing. - */ -int -hpfs_genlookupbyname ( - struct hpfsnode *dhp, - char *name, - int namelen, - struct buf **bpp, - struct hpfsdirent **depp) -{ - struct hpfsmount *hpmp = dhp->h_hpmp; - struct buf *bp; - struct dirblk *dp; - struct hpfsdirent *dep; - lsn_t lsn; - int error, res; - - dprintf(("hpfs_genlookupbyname(0x%x, %s (%d)): \n", - dhp->h_no, name, namelen)); - - lsn = ((alleaf_t *)dhp->h_fn.fn_abd)->al_lsn; -dive: - error = hpfs_breaddirblk (hpmp, lsn, &bp); - if (error) - return (error); - - dp = (struct dirblk *) bp->b_data; - dep = D_DIRENT(dp); - - while(!(dep->de_flag & DE_END)) { - dprintf(("no: 0x%x, size: %d, name: %2d:%.*s, flag: 0x%x\n", - dep->de_fnode, dep->de_size, dep->de_namelen, - dep->de_namelen, dep->de_name, dep->de_flag)); - - res = hpfs_cmpfname(hpmp, name, namelen, - dep->de_name, dep->de_namelen, dep->de_cpid); - if (res == 0) { - *bpp = bp; - *depp = dep; - return (0); - } else if (res < 0) - break; - - dep = (hpfsdirent_t *)(((caddr_t)dep) + dep->de_reclen); - } - - if (dep->de_flag & DE_DOWN) { - lsn = DE_DOWNLSN(dep); - brelse(bp); - goto dive; - } - - brelse(bp); - - return (ENOENT); -} - -int -hpfs_makefnode ( - struct vnode * dvp, - struct vnode ** vpp, - struct componentname *cnp, - struct vattr *vap) -{ -#ifdef HPFS_DEBUG - register struct hpfsnode *dhp = VTOHP(dvp); - dprintf(("hpfs_makefnode(0x%x, %s, %ld): \n", - dhp->h_no, cnp->cn_nameptr, cnp->cn_namelen)); -#endif - - return (EOPNOTSUPP); -} - -int -hpfs_removedirent ( - struct hpfsmount *hpmp, - lsn_t lsn, - char *name, - int namelen, - int *retp) -{ -#if 0 - struct buf *bp; - dirblk_t *dbp; - struct hpfsdirent *dep; - int deoff; - int error, ret; - - dprintf(("hpfs_removedirent(0x%x, %.*s, %d): \n", - lsn, namelen, name, namelen)); - - error = hpfs_breaddirblk (hpmp, lsn, &bp); - if (error) - return (error); - - dbp = (dirblk_t *) bp->b_data; - deoff = sizeof(dirblk_t); - dep = DB_DIRENT(dbp); - - while(!(dep->de_flag & DE_END)) { - dprintf(("no: 0x%x, size: %d, name: %2d:%.*s, flag: 0x%x\n", - dep->de_fnode, dep->de_size, dep->de_namelen, - dep->de_namelen, dep->de_name, dep->de_flag)); - - res = hpfs_cmpfname(hpmp, name, namelen, - dep->de_name, dep->de_namelen, dep->de_cpid); - if (res == 0) { - if (dep->de_flag & DE_DOWN) { - /*XXXXXX*/ - } else { - /* XXX we can copy less */ - bcopy (DE_NEXTDE(dep), dep, DB_BSIZE - deoff - dep->de_reclen); - dbp->d_freeoff -= dep->de_reclen; - *retp = 0; - } - bdwrite (bp); - return (0); - } else if (res < 0) - break; - - deoff += dep->de_reclen; - dep = DB_NEXTDE(dep); - } - - if (dep->de_flag & DE_DOWN) { - error = hpfs_removede (hpmp, DE_DOWNLSN(dep), name, namelen, &ret); - if (error) { - brelse (bp); - return (error); - } - if (ret == 0) { - if (deoff > sizeof (dirblk_t)) { - } else if (deoff + dep->de_reclen < dbp->db_freeoff) { - } - } - } else { - error = ENOENT; - } - - brelse (bp); - return (error); -#endif - return (EOPNOTSUPP); -} - -int -hpfs_removefnode ( - struct vnode * dvp, - struct vnode * vp, - struct componentname *cnp) -{ -#ifdef HPFS_DEBUG - register struct hpfsnode *dhp = VTOHP(dvp); - register struct hpfsnode *hp = VTOHP(vp); - dprintf(("hpfs_removefnode(0x%x, 0x%x, %s, %ld): \n", - dhp->h_no, hp->h_no, cnp->cn_nameptr, cnp->cn_namelen)); -#endif - - - return (EOPNOTSUPP); -} diff --git a/sys/fs/hpfs/hpfs_subr.c b/sys/fs/hpfs/hpfs_subr.c deleted file mode 100644 index e76aba3b16f..00000000000 --- a/sys/fs/hpfs/hpfs_subr.c +++ /dev/null @@ -1,868 +0,0 @@ -/*- - * Copyright (c) 1998, 1999 Semen Ustimenko (semenu@FreeBSD.org) - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -u_long -hpfs_checksum( - u_int8_t *object, - int size) -{ - register int i; - u_long csum=0L; - for (i=0; i < size; i++) { - csum += (u_long) *object++; - csum = (csum << 7) + (csum >> (25)); - } - return (csum); -} - -void -hpfs_bmdeinit( - struct hpfsmount *hpmp) -{ - struct buf *bp; - int i; - - dprintf(("hpmp_bmdeinit: ")); - - if (!(hpmp->hpm_mp->mnt_flag & MNT_RDONLY)) { - /* - * Write down BitMap. - */ - for (i=0; ihpm_dbnum; i++) { - dprintf(("[%d: 0x%x] ", i, hpmp->hpm_bmind[i])); - - bp = getblk(hpmp->hpm_devvp, hpmp->hpm_bmind[i], - BMSIZE, 0, 0, 0); - clrbuf(bp); - - bcopy(hpmp->hpm_bitmap + BMSIZE * i, bp->b_data, - BMSIZE); - - bwrite(bp); - } - } - - free(hpmp->hpm_bitmap,M_HPFSMNT); - free(hpmp->hpm_bmind,M_HPFSMNT); - - dprintf(("\n")); -} - -/* - * Initialize BitMap management, includes calculation of - * available blocks number. - */ -int -hpfs_bminit( - struct hpfsmount *hpmp) -{ - struct buf *bp; - int error, i, k; - u_long dbavail; - - dprintf(("hpfs_bminit: ")); - - hpmp->hpm_dbnum = (hpmp->hpm_su.su_btotal + 0x3FFF) / 0x4000; - - dprintf(("0x%lx data bands, ", hpmp->hpm_dbnum)); - - hpmp->hpm_bmind = malloc(hpmp->hpm_dbnum * sizeof(lsn_t), - M_HPFSMNT, M_WAITOK); - - hpmp->hpm_bitmap = malloc(hpmp->hpm_dbnum * BMSIZE, - M_HPFSMNT, M_WAITOK); - - error = bread(hpmp->hpm_devvp, hpmp->hpm_su.su_bitmap.lsn1, - ((hpmp->hpm_dbnum + 0x7F) & ~(0x7F)) << 2, NOCRED, &bp); - if (error) { - brelse(bp); - free(hpmp->hpm_bitmap, M_HPFSMNT); - free(hpmp->hpm_bmind, M_HPFSMNT); - dprintf((" error %d\n", error)); - return (error); - } - bcopy(bp->b_data, hpmp->hpm_bmind, hpmp->hpm_dbnum * sizeof(lsn_t)); - - brelse(bp); - - /* - * Read in all BitMap - */ - for (i=0; ihpm_dbnum; i++) { - dprintf(("[%d: 0x%x] ", i, hpmp->hpm_bmind[i])); - - error = bread(hpmp->hpm_devvp, hpmp->hpm_bmind[i], - BMSIZE, NOCRED, &bp); - if (error) { - brelse(bp); - free(hpmp->hpm_bitmap, M_HPFSMNT); - free(hpmp->hpm_bmind, M_HPFSMNT); - dprintf((" error %d\n", error)); - return (error); - } - bcopy(bp->b_data, hpmp->hpm_bitmap + BMSIZE * i, BMSIZE); - - brelse(bp); - } - - /* - * Look througth BitMap and count free bits - */ - dbavail = 0; - for (i=0; i < hpmp->hpm_su.su_btotal >> 5; i++) { - register u_int32_t mask; - for (k=0, mask=1; k < 32; k++, mask<<=1) - if(((u_int32_t *)hpmp->hpm_bitmap)[i] & mask) - dbavail ++; - - } - hpmp->hpm_bavail = dbavail; - - return (0); -} - -int -hpfs_cmpfname ( - struct hpfsmount *hpmp, - char * uname, - int ulen, - char * dname, - int dlen, - u_int16_t cp) -{ - register int i, res; - - for (i = 0; i < ulen && i < dlen; i++) { - res = hpfs_toupper(hpmp, hpfs_u2d(hpmp, uname[i]), cp) - - hpfs_toupper(hpmp, dname[i], cp); - if (res) - return res; - } - return (ulen - dlen); -} - -int -hpfs_cpstrnnicmp ( - struct hpfsmount *hpmp, - char * str1, - int str1len, - u_int16_t str1cp, - char * str2, - int str2len, - u_int16_t str2cp) -{ - int i, res; - - for (i = 0; i < str1len && i < str2len; i++) { - res = (int)hpfs_toupper(hpmp, ((u_char *)str1)[i], str1cp) - - (int)hpfs_toupper(hpmp, ((u_char *)str2)[i], str2cp); - if (res) - return res; - } - return (str1len - str2len); -} - - -int -hpfs_cpload ( - struct hpfsmount *hpmp, - struct cpiblk *cpibp, - struct cpdblk *cpdbp) -{ - struct buf *bp; - struct cpdsec * cpdsp; - int error, i; - - error = bread(hpmp->hpm_devvp, cpibp->b_cpdsec, DEV_BSIZE, NOCRED, &bp); - if (error) { - brelse(bp); - return (error); - } - - cpdsp = (struct cpdsec *)bp->b_data; - - for (i=cpdsp->d_cpfirst; id_cpcnt; i++) { - if (cpdsp->d_cpdblk[i].b_cpid == cpibp->b_cpid) { - bcopy(cpdsp->d_cpdblk + i, cpdbp, - sizeof(struct cpdblk)); - - brelse(bp); - - return (0); - } - } - - brelse(bp); - - return (ENOENT); -} - - -/* - * Initialize Code Page information management. - * Load all copdepages in memory. - */ -int -hpfs_cpinit ( - struct mount *mp, - struct hpfsmount *hpmp) -{ - struct buf *bp; - int error, i; - lsn_t lsn; - int cpicnt; - struct cpisec * cpisp; - struct cpiblk * cpibp; - struct cpdblk * cpdbp; - - dprintf(("hpfs_cpinit: \n")); - - error = vfs_copyopt(mp->mnt_optnew, "d2u", hpmp->hpm_d2u, - sizeof hpmp->hpm_d2u); - if (error == ENOENT) - for (i=0x0; i<0x80;i++) - hpmp->hpm_d2u[i] = i + 0x80; - else if (error) - return (error); - - error = vfs_copyopt(mp->mnt_optnew, "u2d", hpmp->hpm_u2d, - sizeof hpmp->hpm_u2d); - if (error == ENOENT) - for (i=0x0; i<0x80;i++) - hpmp->hpm_u2d[i] = i + 0x80; - else if (error) - return (error); - - cpicnt = hpmp->hpm_sp.sp_cpinum; - - hpmp->hpm_cpdblk = malloc(cpicnt * sizeof(struct cpdblk), - M_HPFSMNT, M_WAITOK); - - cpdbp = hpmp->hpm_cpdblk; - lsn = hpmp->hpm_sp.sp_cpi; - - while (cpicnt > 0) { - error = bread(hpmp->hpm_devvp, lsn, DEV_BSIZE, NOCRED, &bp); - if (error) { - brelse(bp); - return (error); - } - - cpisp = (struct cpisec *)bp->b_data; - - cpibp = cpisp->s_cpi; - for (i=0; is_cpicnt; i++, cpicnt --, cpdbp++, cpibp++) { - dprintf(("hpfs_cpinit: Country: %d, CP: %d (%d)\n", - cpibp->b_country, cpibp->b_cpid, - cpibp->b_vcpid)); - - error = hpfs_cpload(hpmp, cpibp, cpdbp); - if (error) { - brelse(bp); - return (error); - } - } - lsn = cpisp->s_next; - brelse(bp); - } - - return (0); -} - -int -hpfs_cpdeinit ( - struct hpfsmount *hpmp) -{ - dprintf(("hpmp_cpdeinit: ")); - free(hpmp->hpm_cpdblk,M_HPFSMNT); - return (0); -} - -/* - * Lookup for a run of blocks. - */ -int -hpfs_bmlookup ( - struct hpfsmount *hpmp, - u_long flags, /* 1 means we want right len blocks in run, not less */ - lsn_t lsn, /* We want near this one */ - u_long len, /* We want such long */ - lsn_t *lsnp, /* We got here */ - u_long *lenp) /* We got this long */ -{ - u_int32_t * bitmap; - register u_int32_t mask; - int i,k; - int cband, vcband; - u_int bandsz; - int count; - - dprintf(("hpfs_bmlookup: lsn: 0x%x, len 0x%lx | Step1\n", lsn, len)); - - if (lsn > hpmp->hpm_su.su_btotal) { - printf("hpfs_bmlookup: OUT OF VOLUME\n"); - return ENOSPC; - } - if (len > hpmp->hpm_bavail) { - printf("hpfs_bmlookup: OUT OF SPACE\n"); - return ENOSPC; - } - i = lsn >> 5; - k = lsn & 0x1F; - mask = 1 << k; - bitmap = (u_int32_t *)hpmp->hpm_bitmap + i; - - if (*bitmap & mask) { - *lsnp = lsn; - *lenp = 0; - for (; k < 32; k++, mask<<=1) { - if (*bitmap & mask) - (*lenp) ++; - else { - if (flags & 1) - goto step2; - else - return (0); - } - - if (*lenp == len) - return (0); - } - - bitmap++; - i++; - for (; i < hpmp->hpm_su.su_btotal >> 5; i++, bitmap++) { - for (k=0, mask=1; k < 32; k++, mask<<=1) { - if (*bitmap & mask) - (*lenp) ++; - else { - if (flags & 1) - goto step2; - else - return (0); - } - - if (*lenp == len) - return (0); - } - } - return (0); - } - -step2: - /* - * Lookup all bands begining from cband, lookup for first block - */ - cband = (lsn >> 14); - dprintf(("hpfs_bmlookup: Step2: band 0x%x (0x%lx)\n", - cband, hpmp->hpm_dbnum)); - for (vcband = 0; vcband < hpmp->hpm_dbnum; vcband ++, cband++) { - cband = cband % hpmp->hpm_dbnum; - bandsz = min (hpmp->hpm_su.su_btotal - (cband << 14), 0x4000); - dprintf(("hpfs_bmlookup: band: %d, sz: 0x%x\n", cband, bandsz)); - - bitmap = (u_int32_t *)hpmp->hpm_bitmap + (cband << 9); - *lsnp = cband << 14; - *lenp = 0; - count = 0; - for (i=0; i < bandsz >> 5; i++, bitmap++) { - for (k=0, mask=1; k < 32; k++, mask<<=1) { - if (*bitmap & mask) { - if (count) { - (*lenp) ++; - } else { - count = 1; - *lsnp = (cband << 14) + (i << 5) + k; - *lenp = 1; - } - } else { - if ((*lenp) && !(flags & 1)) { - return (0); - } else { - count = 0; - } - } - - if (*lenp == len) - return (0); - } - } - if (cband == hpmp->hpm_dbnum - 1) { - if ((*lenp) && !(flags & 1)) { - return (0); - } else { - count = 0; - } - } - } - - return (ENOSPC); -} - -/* - * Lookup a single free block. XXX Need locking on BitMap operations - * VERY STUPID ROUTINE!!! - */ -int -hpfs_bmfblookup ( - struct hpfsmount *hpmp, - lsn_t *lp) -{ - u_int32_t * bitmap; - int i,k; - - dprintf(("hpfs_bmfblookup: ")); - - bitmap = (u_int32_t *)hpmp->hpm_bitmap; - for (i=0; i < hpmp->hpm_su.su_btotal >> 5; i++, bitmap++) { - k = ffs(*bitmap); - if (k) { - *lp = (i << 5) + k - 1; - dprintf((" found: 0x%x\n",*lp)); - return (0); - } - } - - return (ENOSPC); -} - -/* - * Mark contignous block of blocks. - */ -int -hpfs_bmmark ( - struct hpfsmount *hpmp, - lsn_t bn, - u_long bl, - int state) -{ - u_int32_t * bitmap; - int i, didprint = 0; - - dprintf(("hpfs_bmmark(0x%x, 0x%lx, %d): \n",bn,bl, state)); - - if ((bn > hpmp->hpm_su.su_btotal) || (bn+bl > hpmp->hpm_su.su_btotal)) { - printf("hpfs_bmmark: MARKING OUT OF VOLUME\n"); - return 0; - } - bitmap = (u_int32_t *)hpmp->hpm_bitmap; - bitmap += bn >> 5; - - while (bl > 0) { - for (i = bn & 0x1F; (i < 0x20) && (bl > 0) ; i++, bl--) { - if (state) { - if ( *bitmap & (1 << i)) { - if (!didprint) { - printf("hpfs_bmmark: ALREADY FREE\n"); - didprint = 1; - } - } else - hpmp->hpm_bavail++; - - *bitmap |= (1 << i); - } else { - if ((~(*bitmap)) & (1 << i)) { - if (!didprint) { - printf("hpfs_bmmark: ALREADY BUSY\n"); - didprint = 1; - } - } else - hpmp->hpm_bavail--; - - *bitmap &= ~(1 << i); - } - } - bn = 0; - bitmap++; - } - - return (0); -} - - -int -hpfs_validateparent ( - struct hpfsnode *hp) -{ - struct hpfsnode *dhp; - struct vnode *dvp; - struct hpfsmount *hpmp = hp->h_hpmp; - struct buf *bp; - struct dirblk *dp; - struct hpfsdirent *dep; - lsn_t lsn, olsn; - int level, error; - - dprintf(("hpfs_validatetimes(0x%x): [parent: 0x%x] ", - hp->h_no, hp->h_fn.fn_parent)); - - if (hp->h_no == hp->h_fn.fn_parent) { - dhp = hp; - } else { - error = VFS_VGET(hpmp->hpm_mp, hp->h_fn.fn_parent, - LK_EXCLUSIVE, &dvp); - if (error) - return (error); - dhp = VTOHP(dvp); - } - - lsn = ((alleaf_t *)dhp->h_fn.fn_abd)->al_lsn; - - olsn = 0; - level = 1; - bp = NULL; - -dive: - dprintf(("[dive 0x%x] ", lsn)); - if (bp != NULL) - brelse(bp); - error = bread(dhp->h_devvp, lsn, D_BSIZE, NOCRED, &bp); - if (error) - goto failed; - - dp = (struct dirblk *) bp->b_data; - if (dp->d_magic != D_MAGIC) { - printf("hpfs_validatetimes: magic doesn't match\n"); - error = EINVAL; - goto failed; - } - - dep = D_DIRENT(dp); - - if (olsn) { - dprintf(("[restore 0x%x] ", olsn)); - - while(!(dep->de_flag & DE_END) ) { - if((dep->de_flag & DE_DOWN) && - (olsn == DE_DOWNLSN(dep))) - break; - dep = (hpfsdirent_t *)((caddr_t)dep + dep->de_reclen); - } - - if((dep->de_flag & DE_DOWN) && (olsn == DE_DOWNLSN(dep))) { - if (dep->de_flag & DE_END) - goto blockdone; - - if (hp->h_no == dep->de_fnode) { - dprintf(("[found] ")); - goto readdone; - } - - dep = (hpfsdirent_t *)((caddr_t)dep + dep->de_reclen); - } else { - printf("hpfs_validatetimes: ERROR! oLSN not found\n"); - error = EINVAL; - goto failed; - } - } - - olsn = 0; - - while(!(dep->de_flag & DE_END)) { - if(dep->de_flag & DE_DOWN) { - lsn = DE_DOWNLSN(dep); - level++; - goto dive; - } - - if (hp->h_no == dep->de_fnode) { - dprintf(("[found] ")); - goto readdone; - } - - dep = (hpfsdirent_t *)((caddr_t)dep + dep->de_reclen); - } - - if(dep->de_flag & DE_DOWN) { - dprintf(("[enddive] ")); - lsn = DE_DOWNLSN(dep); - level++; - goto dive; - } - -blockdone: - dprintf(("[EOB] ")); - olsn = lsn; - lsn = dp->d_parent; - level--; - dprintf(("[level %d] ", level)); - if (level > 0) - goto dive; /* undive really */ - - goto failed; - -readdone: - bcopy(dep->de_name,hp->h_name,dep->de_namelen); - hp->h_name[dep->de_namelen] = '\0'; - hp->h_namelen = dep->de_namelen; - hp->h_ctime = dep->de_ctime; - hp->h_atime = dep->de_atime; - hp->h_mtime = dep->de_mtime; - hp->h_flag |= H_PARVALID; - - dprintf(("[readdone]")); - -failed: - dprintf(("\n")); - if (bp != NULL) - brelse(bp); - if (hp != dhp) - vput(dvp); - - return (error); -} - -struct timespec -hpfstimetounix ( - u_long hptime) -{ - struct timespec t; - - t.tv_nsec = 0; - t.tv_sec = hptime; - - return t; -} - -/* - * Write down changes done to parent dir, these are only times for now. - * hpfsnode have to be locked. - */ -int -hpfs_updateparent ( - struct hpfsnode *hp) -{ - struct hpfsnode *dhp; - struct vnode *dvp; - struct hpfsdirent *dep; - struct buf * bp; - int error; - - dprintf(("hpfs_updateparent(0x%x): \n", hp->h_no)); - - if (!(hp->h_flag & H_PARCHANGE)) - return (0); - - if (!(hp->h_flag & H_PARVALID)) { - error = hpfs_validateparent (hp); - if (error) - return (error); - } - - if (hp->h_no == hp->h_fn.fn_parent) { - dhp = hp; - } else { - error = VFS_VGET(hp->h_hpmp->hpm_mp, hp->h_fn.fn_parent, - LK_EXCLUSIVE, &dvp); - if (error) - return (error); - dhp = VTOHP(dvp); - } - - error = hpfs_genlookupbyname (dhp, hp->h_name, hp->h_namelen, - &bp, &dep); - if (error) { - goto failed; - } - - dep->de_atime = hp->h_atime; - dep->de_mtime = hp->h_mtime; - dep->de_size = hp->h_fn.fn_size; - - bdwrite (bp); - - hp->h_flag &= ~H_PARCHANGE; - - error = 0; -failed: - if (hp != dhp) - vput(dvp); - - return (0); -} - -/* - * Write down on disk changes done to fnode. hpfsnode have to be locked. - */ -int -hpfs_update ( - struct hpfsnode *hp) -{ - struct buf * bp; - - dprintf(("hpfs_update(0x%x): \n", hp->h_no)); - - if (!(hp->h_flag & H_CHANGE)) - return (0); - - bp = getblk(hp->h_devvp, hp->h_no, FNODESIZE, 0, 0, 0); - clrbuf(bp); - - bcopy (&hp->h_fn, bp->b_data, sizeof(struct fnode)); - bdwrite (bp); - - hp->h_flag &= ~H_CHANGE; - - if (hp->h_flag & H_PARCHANGE) - return (hpfs_updateparent(hp)); - - return (0); -} - -/* - * Truncate file to specifed size. hpfsnode have to be locked. - */ -int -hpfs_truncate ( - struct hpfsnode *hp, - u_long size) -{ - struct hpfsmount *hpmp = hp->h_hpmp; - lsn_t newblen, oldblen; - int error, pf; - - dprintf(("hpfs_truncate(0x%x, 0x%x -> 0x%lx): ", - hp->h_no, hp->h_fn.fn_size, size)); - - newblen = (size + DEV_BSIZE - 1) >> DEV_BSHIFT; - oldblen = (hp->h_fn.fn_size + DEV_BSIZE - 1) >> DEV_BSHIFT; - - dprintf(("blen: 0x%x -> 0x%x\n", oldblen, newblen)); - - error = hpfs_truncatealblk (hpmp, &hp->h_fn.fn_ab, newblen, &pf); - if (error) - return (error); - if (pf) { - hp->h_fn.fn_ab.ab_flag = 0; - hp->h_fn.fn_ab.ab_freecnt = 0x8; - hp->h_fn.fn_ab.ab_busycnt = 0x0; - hp->h_fn.fn_ab.ab_freeoff = sizeof(alblk_t); - } - - hp->h_fn.fn_size = size; - - hp->h_flag |= (H_CHANGE | H_PARCHANGE); - - dprintf(("hpfs_truncate: successful\n")); - - return (0); -} - -/* - * Enlarge file to specifed size. hpfsnode have to be locked. - */ -int -hpfs_extend ( - struct hpfsnode *hp, - u_long size) -{ - struct hpfsmount *hpmp = hp->h_hpmp; - lsn_t newblen, oldblen; - int error; - - dprintf(("hpfs_extend(0x%x, 0x%x -> 0x%lx): ", - hp->h_no, hp->h_fn.fn_size, size)); - - if (hpmp->hpm_bavail < 0x10) - return (ENOSPC); - - newblen = (size + DEV_BSIZE - 1) >> DEV_BSHIFT; - oldblen = (hp->h_fn.fn_size + DEV_BSIZE - 1) >> DEV_BSHIFT; - - dprintf(("blen: 0x%x -> 0x%x\n", oldblen, newblen)); - - error = hpfs_addextent(hpmp, hp, newblen - oldblen); - if (error) { - printf("hpfs_extend: FAILED TO ADD EXTENT %d\n", error); - return (error); - } - - hp->h_fn.fn_size = size; - - hp->h_flag |= (H_CHANGE | H_PARCHANGE); - - dprintf(("hpfs_extend: successful\n")); - - return (0); -} - -/* - * Read AlSec structure, and check if magic is valid. - * You don't need to brelse buf on error. - */ -int -hpfs_breadstruct ( - struct hpfsmount *hpmp, - lsn_t lsn, - u_int len, - u_int32_t magic, - struct buf **bpp) -{ - struct buf *bp; - u_int32_t *mp; - int error; - - dprintf(("hpfs_breadstruct: reading at 0x%x\n", lsn)); - - *bpp = NULL; - - error = bread(hpmp->hpm_devvp, lsn, len, NOCRED, &bp); - if (error) { - brelse(bp); - return (error); - } - mp = (u_int32_t *) bp->b_data; - if (*mp != magic) { - brelse(bp); - printf("hpfs_breadstruct: MAGIC DOESN'T MATCH (0x%08x != 0x%08x)\n", - *mp, magic); - return (EINVAL); - } - - *bpp = bp; - - return (0); -} - diff --git a/sys/fs/hpfs/hpfs_subr.h b/sys/fs/hpfs/hpfs_subr.h deleted file mode 100644 index 2fa6ab3019e..00000000000 --- a/sys/fs/hpfs/hpfs_subr.h +++ /dev/null @@ -1,88 +0,0 @@ -/*- - * Copyright (c) 1998, 1999 Semen Ustimenko (semenu@FreeBSD.org) - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - */ - -#define hpfs_bmmarkfree(hpmp, bn,bl) hpfs_bmmark(hpmp, bn, bl, 1) -#define hpfs_bmmarkbusy(hpmp, bn,bl) hpfs_bmmark(hpmp, bn, bl, 0) - -u_long hpfs_checksum (u_int8_t *, int); - -int hpfs_bminit (struct hpfsmount *); -void hpfs_bmdeinit (struct hpfsmount *); -int hpfs_bmfblookup (struct hpfsmount *, lsn_t *); -int hpfs_bmmark (struct hpfsmount *, lsn_t, u_long, int); -int hpfs_bmlookup (struct hpfsmount *, u_long, lsn_t, u_long, - lsn_t *, u_long *); - -struct hpfs_args; -int hpfs_cpinit (struct mount *, struct hpfsmount *); -int hpfs_cpdeinit (struct hpfsmount *); -int hpfs_cpload (struct hpfsmount *, struct cpiblk *, - struct cpdblk *); -int hpfs_cpstrnnicmp (struct hpfsmount *, char *, int, u_int16_t, - char *, int, u_int16_t); -int hpfs_cmpfname (struct hpfsmount *, char *, int, - char *, int, u_int16_t); - -/* XXX Need unsigned conversion? */ -#define hpfs_u2d(hpmp, c) ((((u_char)(c))&0x80)?(hpmp->hpm_u2d[((u_char)(c))&0x7F]):((u_char)(c))) -#define hpfs_d2u(hpmp, c) ((((u_char)(c))&0x80)?(hpmp->hpm_d2u[((u_char)(c))&0x7F]):((u_char)(c))) -#define hpfs_toupper(hpmp, c, cp) ((((u_char)(c))&0x80) ? ((u_char)((hpmp)->hpm_cpdblk[(cp)].b_upcase[((u_char)(c))&0x7F])) : ((((u_char)(c)) >= 'a' && ((u_char)(c)) <='z')?(((u_char)(c))-'a'+'A'):((u_char)(c)))) - - -int hpfs_truncate (struct hpfsnode *, u_long); -int hpfs_extend (struct hpfsnode *, u_long); - -int hpfs_updateparent (struct hpfsnode *); -int hpfs_update (struct hpfsnode *); - -int hpfs_validateparent (struct hpfsnode *); -struct timespec hpfstimetounix (u_long); -int hpfs_genlookupbyname (struct hpfsnode *, char *, int, - struct buf **, struct hpfsdirent **); - -int hpfs_makefnode (struct vnode *, struct vnode **, - struct componentname *, struct vattr *); -int hpfs_removefnode (struct vnode *, struct vnode *, - struct componentname *); - -int hpfs_breadstruct (struct hpfsmount *, lsn_t, u_int, u_int32_t, - struct buf **); -#define hpfs_breadalsec(hpmp, lsn, bpp) \ - hpfs_breadstruct(hpmp, lsn, DEV_BSIZE, AS_MAGIC, bpp) -#define hpfs_breaddirblk(hpmp, lsn, bpp) \ - hpfs_breadstruct(hpmp, lsn, D_BSIZE, D_MAGIC, bpp) - -#if 0 -#define hpfs_hplock(hp, p) \ - lockmgr(&(hp)->h_intlock, LK_EXCLUSIVE, (p)) -#define hpfs_hpunlock(hp, p) \ - lockmgr(&(hp)->h_intlock, LK_RELEASE, (p)) -#endif - -int hpfs_hpbmap (struct hpfsnode *, daddr_t, daddr_t *, int *); -int hpfs_truncatealblk (struct hpfsmount *, alblk_t *, lsn_t,int *); -int hpfs_addextent (struct hpfsmount *, struct hpfsnode *, u_long); diff --git a/sys/fs/hpfs/hpfs_vfsops.c b/sys/fs/hpfs/hpfs_vfsops.c deleted file mode 100644 index d83c28f50fb..00000000000 --- a/sys/fs/hpfs/hpfs_vfsops.c +++ /dev/null @@ -1,544 +0,0 @@ -/*- - * Copyright (c) 1998, 1999 Semen Ustimenko (semenu@FreeBSD.org) - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - */ - - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include -#include -#include -#include -#include - -#include -#include -#include - -MALLOC_DEFINE(M_HPFSMNT, "hpfs_mount", "HPFS mount structure"); -MALLOC_DEFINE(M_HPFSNO, "hpfs_node", "HPFS node structure"); - -struct sockaddr; - -static int hpfs_mountfs(register struct vnode *, struct mount *, - struct thread *); - -static vfs_fhtovp_t hpfs_fhtovp; -static vfs_vget_t hpfs_vget; -static vfs_cmount_t hpfs_cmount; -static vfs_mount_t hpfs_mount; -static vfs_root_t hpfs_root; -static vfs_statfs_t hpfs_statfs; -static vfs_unmount_t hpfs_unmount; - -static int -hpfs_cmount ( - struct mntarg *ma, - void *data, - uint64_t flags) -{ - struct hpfs_args args; - struct export_args exp; - int error; - - error = copyin(data, (caddr_t)&args, sizeof (struct hpfs_args)); - if (error) - return (error); - vfs_oexport_conv(&args.export, &exp); - - ma = mount_argsu(ma, "from", args.fspec, MAXPATHLEN); - ma = mount_arg(ma, "export", &exp, sizeof(exp)); - ma = mount_argf(ma, "uid", "%d", args.uid); - ma = mount_argf(ma, "gid", "%d", args.gid); - ma = mount_argf(ma, "mode", "%d", args.mode); - if (args.flags & HPFSMNT_TABLES) { - ma = mount_arg(ma, "d2u", args.d2u, sizeof args.d2u); - ma = mount_arg(ma, "u2d", args.u2d, sizeof args.u2d); - } - - error = kernel_mount(ma, flags); - - return (error); -} - -static const char *hpfs_opts[] = { - "from", "export", "uid", "gid", "mode", "d2u", "u2d", NULL -}; - -static int -hpfs_mount (struct mount *mp) -{ - int err = 0, error; - struct vnode *devvp; - struct thread *td; - struct nameidata ndp; - struct export_args export; - char *from; - - td = curthread; - dprintf(("hpfs_omount():\n")); - /* - *** - * Mounting non-root filesystem or updating a filesystem - *** - */ - if (vfs_filteropt(mp->mnt_optnew, hpfs_opts)) - return (EINVAL); - - from = vfs_getopts(mp->mnt_optnew, "from", &error); - if (error) - return (error); - - /* - * If updating, check whether changing from read-only to - * read/write; if there is no device name, that's all we do. - */ - if (mp->mnt_flag & MNT_UPDATE) { - dprintf(("hpfs_omount: MNT_UPDATE: ")); - - if (from == NULL) { - error = vfs_copyopt(mp->mnt_optnew, "export", - &export, sizeof export); - if (error) - return (error); - dprintf(("export 0x%x\n",args.export.ex_flags)); - err = vfs_export(mp, &export); - if (err) { - printf("hpfs_omount: vfs_export failed %d\n", - err); - } - goto success; - } else { - dprintf(("name [FAILED]\n")); - err = EINVAL; - goto success; - } - dprintf(("\n")); - } - - /* - * Not an update, or updating the name: look up the name - * and verify that it refers to a sensible block device. - */ - NDINIT(&ndp, LOOKUP, FOLLOW | LOCKLEAF, UIO_SYSSPACE, from, td); - err = namei(&ndp); - if (err) { - /* can't get devvp!*/ - goto error_1; - } - - devvp = ndp.ni_vp; - - if (!vn_isdisk(devvp, &err)) { - vput(devvp); - return (err); - } - - /* - ******************** - * NEW MOUNT - ******************** - */ - - /* - * Since this is a new mount, we want the names for - * the device and the mount point copied in. If an - * error occurs, the mountpoint is discarded by the - * upper level code. Note that vfs_omount() handles - * copying the mountpoint f_mntonname for us, so we - * don't have to do it here unless we want to set it - * to something other than "path" for some rason. - */ - /* Save "mounted from" info for mount point (NULL pad)*/ - vfs_mountedfrom(mp, from); - - err = hpfs_mountfs(devvp, mp, td); - if (err) { - vrele(devvp); - goto error_1; - } - - goto success; - -error_1: /* no state to back out*/ - /* XXX: Missing NDFREE(&ndp, ...) */ - -success: - return( err); -} - -/* - * Common code for mount and mountroot - */ -int -hpfs_mountfs(devvp, mp, td) - register struct vnode *devvp; - struct mount *mp; - struct thread *td; -{ - int error, ronly, v; - struct sublock *sup; - struct spblock *spp; - struct hpfsmount *hpmp; - struct buf *bp = NULL; - struct vnode *vp; - struct cdev *dev = devvp->v_rdev; - struct g_consumer *cp; - struct bufobj *bo; - - if (mp->mnt_flag & MNT_ROOTFS) - return (EOPNOTSUPP); - dprintf(("hpfs_mountfs():\n")); - ronly = (mp->mnt_flag & MNT_RDONLY) != 0; - /* XXX: use VOP_ACCESS to check FS perms */ - DROP_GIANT(); - g_topology_lock(); - error = g_vfs_open(devvp, &cp, "hpfs", ronly ? 0 : 1); - g_topology_unlock(); - PICKUP_GIANT(); - VOP_UNLOCK(devvp, 0); - if (error) - return (error); - - bo = &devvp->v_bufobj; - bo->bo_private = cp; - bo->bo_ops = g_vfs_bufops; - - /* - * Do actual mount - */ - hpmp = malloc(sizeof(struct hpfsmount), M_HPFSMNT, M_WAITOK | M_ZERO); - - hpmp->hpm_cp = cp; - hpmp->hpm_bo = bo; - - /* Read in SuperBlock */ - error = bread(devvp, SUBLOCK, SUSIZE, NOCRED, &bp); - if (error) - goto failed; - bcopy(bp->b_data, &hpmp->hpm_su, sizeof(struct sublock)); - brelse(bp); bp = NULL; - - /* Read in SpareBlock */ - error = bread(devvp, SPBLOCK, SPSIZE, NOCRED, &bp); - if (error) - goto failed; - bcopy(bp->b_data, &hpmp->hpm_sp, sizeof(struct spblock)); - brelse(bp); bp = NULL; - - sup = &hpmp->hpm_su; - spp = &hpmp->hpm_sp; - - /* Check magic */ - if (sup->su_magic != SU_MAGIC) { - printf("hpfs_mountfs: SuperBlock MAGIC DOESN'T MATCH\n"); - error = EINVAL; - goto failed; - } - if (spp->sp_magic != SP_MAGIC) { - printf("hpfs_mountfs: SpareBlock MAGIC DOESN'T MATCH\n"); - error = EINVAL; - goto failed; - } - - mp->mnt_data = hpmp; - hpmp->hpm_devvp = devvp; - hpmp->hpm_dev = devvp->v_rdev; - hpmp->hpm_mp = mp; - if (vfs_scanopt(mp->mnt_optnew, "uid", "%d", &v) == 1) - hpmp->hpm_uid = v; - if (vfs_scanopt(mp->mnt_optnew, "gid", "%d", &v) == 1) - hpmp->hpm_gid = v; - if (vfs_scanopt(mp->mnt_optnew, "mode", "%d", &v) == 1) - hpmp->hpm_mode = v; - - error = hpfs_bminit(hpmp); - if (error) - goto failed; - - error = hpfs_cpinit(mp, hpmp); - if (error) { - hpfs_bmdeinit(hpmp); - goto failed; - } - - error = hpfs_root(mp, LK_EXCLUSIVE, &vp); - if (error) { - hpfs_cpdeinit(hpmp); - hpfs_bmdeinit(hpmp); - goto failed; - } - - vput(vp); - - mp->mnt_stat.f_fsid.val[0] = (long)dev2udev(dev); - mp->mnt_stat.f_fsid.val[1] = mp->mnt_vfc->vfc_typenum; - mp->mnt_maxsymlinklen = 0; - MNT_ILOCK(mp); - mp->mnt_flag |= MNT_LOCAL; - MNT_IUNLOCK(mp); - return (0); - -failed: - if (bp) - brelse (bp); - mp->mnt_data = NULL; - DROP_GIANT(); - g_topology_lock(); - g_vfs_close(cp); - g_topology_unlock(); - PICKUP_GIANT(); - return (error); -} - -static int -hpfs_unmount( - struct mount *mp, - int mntflags) -{ - int error, flags; - register struct hpfsmount *hpmp = VFSTOHPFS(mp); - - dprintf(("hpfs_unmount():\n")); - - flags = 0; - if(mntflags & MNT_FORCE) - flags |= FORCECLOSE; - - dprintf(("hpfs_unmount: vflushing...\n")); - - error = vflush(mp, 0, flags, curthread); - if (error) { - printf("hpfs_unmount: vflush failed: %d\n",error); - return (error); - } - - vinvalbuf(hpmp->hpm_devvp, V_SAVE, 0, 0); - DROP_GIANT(); - g_topology_lock(); - g_vfs_close(hpmp->hpm_cp); - g_topology_unlock(); - PICKUP_GIANT(); - vrele(hpmp->hpm_devvp); - - dprintf(("hpfs_umount: freeing memory...\n")); - hpfs_cpdeinit(hpmp); - hpfs_bmdeinit(hpmp); - mp->mnt_data = NULL; - MNT_ILOCK(mp); - mp->mnt_flag &= ~MNT_LOCAL; - MNT_IUNLOCK(mp); - free(hpmp, M_HPFSMNT); - - return (0); -} - -static int -hpfs_root( - struct mount *mp, - int flags, - struct vnode **vpp) -{ - int error = 0; - struct hpfsmount *hpmp = VFSTOHPFS(mp); - - dprintf(("hpfs_root():\n")); - error = VFS_VGET(mp, (ino_t)hpmp->hpm_su.su_rootfno, LK_EXCLUSIVE, vpp); - if(error) { - printf("hpfs_root: VFS_VGET failed: %d\n",error); - return (error); - } - - return (error); -} - -static int -hpfs_statfs( - struct mount *mp, - struct statfs *sbp) -{ - struct hpfsmount *hpmp = VFSTOHPFS(mp); - - dprintf(("hpfs_statfs(): HPFS%d.%d\n", - hpmp->hpm_su.su_hpfsver, hpmp->hpm_su.su_fnctver)); - - sbp->f_type = mp->mnt_vfc->vfc_typenum; - sbp->f_bsize = DEV_BSIZE; - sbp->f_iosize = DEV_BSIZE; - sbp->f_blocks = hpmp->hpm_su.su_btotal; - sbp->f_bfree = sbp->f_bavail = hpmp->hpm_bavail; - sbp->f_ffree = 0; - sbp->f_files = 0; - sbp->f_flags = mp->mnt_flag; - - return (0); -} - -/*ARGSUSED*/ -static int -hpfs_fhtovp( - struct mount *mp, - struct fid *fhp, - int flags, - struct vnode **vpp) -{ - struct vnode *nvp; - struct hpfid *hpfhp = (struct hpfid *)fhp; - int error; - - if ((error = VFS_VGET(mp, hpfhp->hpfid_ino, LK_EXCLUSIVE, &nvp)) != 0) { - *vpp = NULLVP; - return (error); - } - /* XXX as unlink/rmdir/mkdir/creat are not currently possible - * with HPFS, we don't need to check anything else for now */ - *vpp = nvp; - - return (0); -} - -static int -hpfs_vget( - struct mount *mp, - ino_t ino, - int flags, - struct vnode **vpp) -{ - struct hpfsmount *hpmp = VFSTOHPFS(mp); - struct vnode *vp; - struct hpfsnode *hp; - struct buf *bp; - int error; - - dprintf(("hpfs_vget(0x%x): ",ino)); - - error = vfs_hash_get(mp, ino, flags, curthread, vpp, NULL, NULL); - if (error || *vpp != NULL) - return (error); - - *vpp = NULL; - hp = NULL; - vp = NULL; - - /* - * We have to lock node creation for a while, - * but then we have to call getnewvnode(), - * this may cause hpfs_reclaim() to be called, - * this may need to VOP_VGET() parent dir for - * update reasons, and if parent is not in - * hash, we have to lock node creation... - * To solve this, we MALLOC, getnewvnode and init while - * not locked (probability of node appearence - * at that time is little, and anyway - we'll - * check for it). - */ - hp = malloc(sizeof(struct hpfsnode), - M_HPFSNO, M_WAITOK); - - error = getnewvnode("hpfs", mp, &hpfs_vnodeops, &vp); - if (error) { - printf("hpfs_vget: can't get new vnode\n"); - free(hp, M_HPFSNO); - return (error); - } - - dprintf(("prenew ")); - - vp->v_data = hp; - - if (ino == (ino_t)hpmp->hpm_su.su_rootfno) - vp->v_vflag |= VV_ROOT; - - - mtx_init(&hp->h_interlock, "hpfsnode interlock", NULL, MTX_DEF); - - hp->h_flag = H_INVAL; - hp->h_vp = vp; - hp->h_hpmp = hpmp; - hp->h_no = ino; - hp->h_dev = hpmp->hpm_dev; - hp->h_uid = hpmp->hpm_uid; - hp->h_gid = hpmp->hpm_uid; - hp->h_mode = hpmp->hpm_mode; - hp->h_devvp = hpmp->hpm_devvp; - - lockmgr(vp->v_vnlock, LK_EXCLUSIVE, NULL); - error = insmntque(vp, mp); - if (error != 0) { - free(hp, M_HPFSNO); - return (error); - } - error = vfs_hash_insert(vp, ino, flags, curthread, vpp, NULL, NULL); - if (error || *vpp != NULL) - return (error); - - error = bread(hpmp->hpm_devvp, ino, FNODESIZE, NOCRED, &bp); - if (error) { - printf("hpfs_vget: can't read ino %d\n",ino); - vput(vp); - return (error); - } - bcopy(bp->b_data, &hp->h_fn, sizeof(struct fnode)); - brelse(bp); - - if (hp->h_fn.fn_magic != FN_MAGIC) { - printf("hpfs_vget: MAGIC DOESN'T MATCH\n"); - vput(vp); - return (EINVAL); - } - - vp->v_type = hp->h_fn.fn_flag ? VDIR:VREG; - hp->h_flag &= ~H_INVAL; - - *vpp = vp; - - return (0); -} - -static struct vfsops hpfs_vfsops = { - .vfs_fhtovp = hpfs_fhtovp, - .vfs_cmount = hpfs_cmount, - .vfs_mount = hpfs_mount, - .vfs_root = hpfs_root, - .vfs_statfs = hpfs_statfs, - .vfs_unmount = hpfs_unmount, - .vfs_vget = hpfs_vget, -}; -VFS_SET(hpfs_vfsops, hpfs, 0); diff --git a/sys/fs/hpfs/hpfs_vnops.c b/sys/fs/hpfs/hpfs_vnops.c deleted file mode 100644 index 6fda6b97e5c..00000000000 --- a/sys/fs/hpfs/hpfs_vnops.c +++ /dev/null @@ -1,1252 +0,0 @@ -/*- - * Copyright (c) 1998, 1999 Semen Ustimenko (semenu@FreeBSD.org) - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include - -#include /* for pathconf(2) constants */ - -#include -#include -#include -#include - -static int hpfs_de_uiomove(struct hpfsmount *, struct hpfsdirent *, - struct uio *); -static vop_ioctl_t hpfs_ioctl; -static vop_read_t hpfs_read; -static vop_write_t hpfs_write; -static vop_getattr_t hpfs_getattr; -static vop_setattr_t hpfs_setattr; -static vop_inactive_t hpfs_inactive; -static vop_print_t hpfs_print; -static vop_reclaim_t hpfs_reclaim; -static vop_strategy_t hpfs_strategy; -static vop_access_t hpfs_access; -static vop_open_t hpfs_open; -static vop_close_t hpfs_close; -static vop_readdir_t hpfs_readdir; -static vop_cachedlookup_t hpfs_lookup; -static vop_create_t hpfs_create; -static vop_remove_t hpfs_remove; -static vop_bmap_t hpfs_bmap; -static vop_fsync_t hpfs_fsync; -static vop_pathconf_t hpfs_pathconf; -static vop_vptofh_t hpfs_vptofh; - -static int -hpfs_fsync(ap) - struct vop_fsync_args /* { - struct vnode *a_vp; - struct ucred *a_cred; - int a_waitfor; - struct thread *a_td; - } */ *ap; -{ - /* - * Flush our dirty buffers. - */ - vop_stdfsync(ap); - - /* - * Write out the on-disc version of the vnode. - */ - return hpfs_update(VTOHP(ap->a_vp)); -} - -static int -hpfs_ioctl ( - struct vop_ioctl_args /* { - struct vnode *a_vp; - u_long a_command; - caddr_t a_data; - int a_fflag; - struct ucred *a_cred; - struct thread *a_td; - } */ *ap) -{ - register struct vnode *vp = ap->a_vp; - register struct hpfsnode *hp = VTOHP(vp); - int error; - - printf("hpfs_ioctl(0x%x, 0x%lx, 0x%p, 0x%x): ", - hp->h_no, ap->a_command, ap->a_data, ap->a_fflag); - - switch (ap->a_command) { - case HPFSIOCGEANUM: { - u_long eanum; - u_long passed; - struct ea *eap; - - eanum = 0; - - if (hp->h_fn.fn_ealen > 0) { - eap = (struct ea *)&(hp->h_fn.fn_int); - passed = 0; - - while (passed < hp->h_fn.fn_ealen) { - - printf("EAname: %s\n", EA_NAME(eap)); - - eanum++; - passed += sizeof(struct ea) + - eap->ea_namelen + 1 + eap->ea_vallen; - eap = (struct ea *)((caddr_t)hp->h_fn.fn_int + - passed); - } - error = 0; - } else { - error = ENOENT; - } - - printf("%lu eas\n", eanum); - - *(u_long *)ap->a_data = eanum; - - break; - } - case HPFSIOCGEASZ: { - u_long eanum; - u_long passed; - struct ea *eap; - - printf("EA%ld\n", *(u_long *)ap->a_data); - - eanum = 0; - if (hp->h_fn.fn_ealen > 0) { - eap = (struct ea *)&(hp->h_fn.fn_int); - passed = 0; - - error = ENOENT; - while (passed < hp->h_fn.fn_ealen) { - printf("EAname: %s\n", EA_NAME(eap)); - - if (eanum == *(u_long *)ap->a_data) { - *(u_long *)ap->a_data = - eap->ea_namelen + 1 + - eap->ea_vallen; - - error = 0; - break; - } - - eanum++; - passed += sizeof(struct ea) + - eap->ea_namelen + 1 + eap->ea_vallen; - eap = (struct ea *)((caddr_t)hp->h_fn.fn_int + - passed); - } - } else { - error = ENOENT; - } - - break; - } - case HPFSIOCRDEA: { - u_long eanum; - u_long passed; - struct hpfs_rdea *rdeap; - struct ea *eap; - - rdeap = (struct hpfs_rdea *)ap->a_data; - printf("EA%ld\n", rdeap->ea_no); - - eanum = 0; - if (hp->h_fn.fn_ealen > 0) { - eap = (struct ea *)&(hp->h_fn.fn_int); - passed = 0; - - error = ENOENT; - while (passed < hp->h_fn.fn_ealen) { - printf("EAname: %s\n", EA_NAME(eap)); - - if (eanum == rdeap->ea_no) { - rdeap->ea_sz = eap->ea_namelen + 1 + - eap->ea_vallen; - copyout(EA_NAME(eap),rdeap->ea_data, - rdeap->ea_sz); - error = 0; - break; - } - - eanum++; - passed += sizeof(struct ea) + - eap->ea_namelen + 1 + eap->ea_vallen; - eap = (struct ea *)((caddr_t)hp->h_fn.fn_int + - passed); - } - } else { - error = ENOENT; - } - - break; - } - default: - error = ENOTTY; - break; - } - return (error); -} - -/* - * Map file offset to disk offset. - */ -int -hpfs_bmap(ap) - struct vop_bmap_args /* { - struct vnode *a_vp; - daddr_t a_bn; - struct bufobj **a_bop; - daddr_t *a_bnp; - int *a_runp; - int *a_runb; - } */ *ap; -{ - register struct hpfsnode *hp = VTOHP(ap->a_vp); - daddr_t blkno; - int error; - - if (ap->a_bop != NULL) - *ap->a_bop = &hp->h_devvp->v_bufobj; - if (ap->a_runb != NULL) - *ap->a_runb = 0; - if (ap->a_bnp == NULL) - return (0); - - dprintf(("hpfs_bmap(0x%x, 0x%x): ",hp->h_no, ap->a_bn)); - - error = hpfs_hpbmap (hp, ap->a_bn, &blkno, ap->a_runp); - *ap->a_bnp = blkno; - - return (error); -} - -static int -hpfs_read(ap) - struct vop_read_args /* { - struct vnode *a_vp; - struct uio *a_uio; - int a_ioflag; - struct ucred *a_cred; - } */ *ap; -{ - register struct vnode *vp = ap->a_vp; - register struct hpfsnode *hp = VTOHP(vp); - struct uio *uio = ap->a_uio; - struct buf *bp; - u_int xfersz, toread; - u_int off; - daddr_t lbn, bn; - int resid; - int runl; - int error = 0; - - resid = min (uio->uio_resid, hp->h_fn.fn_size - uio->uio_offset); - - dprintf(("hpfs_read(0x%x, off: %d resid: %d, segflg: %d): [resid: 0x%x]\n",hp->h_no,(u_int32_t)uio->uio_offset,uio->uio_resid,uio->uio_segflg, resid)); - - while (resid) { - lbn = uio->uio_offset >> DEV_BSHIFT; - off = uio->uio_offset & (DEV_BSIZE - 1); - dprintf(("hpfs_read: resid: 0x%x lbn: 0x%x off: 0x%x\n", - uio->uio_resid, lbn, off)); - error = hpfs_hpbmap(hp, lbn, &bn, &runl); - if (error) - return (error); - - toread = min(off + resid, min(DFLTPHYS, (runl+1)*DEV_BSIZE)); - xfersz = (toread + DEV_BSIZE - 1) & ~(DEV_BSIZE - 1); - dprintf(("hpfs_read: bn: 0x%x (0x%x) toread: 0x%x (0x%x)\n", - bn, runl, toread, xfersz)); - - if (toread == 0) - break; - - error = bread(hp->h_devvp, bn, xfersz, NOCRED, &bp); - if (error) { - brelse(bp); - break; - } - - error = uiomove(bp->b_data + off, toread - off, uio); - if(error) { - brelse(bp); - break; - } - brelse(bp); - resid -= toread; - } - dprintf(("hpfs_read: successful\n")); - return (error); -} - -static int -hpfs_write(ap) - struct vop_write_args /* { - struct vnode *a_vp; - struct uio *a_uio; - int a_ioflag; - struct ucred *a_cred; - } */ *ap; -{ - register struct vnode *vp = ap->a_vp; - register struct hpfsnode *hp = VTOHP(vp); - struct uio *uio = ap->a_uio; - struct buf *bp; - u_int xfersz, towrite; - u_int off; - daddr_t lbn, bn; - int runl; - int error = 0; - - dprintf(("hpfs_write(0x%x, off: %d resid: %d, segflg: %d):\n",hp->h_no,(u_int32_t)uio->uio_offset,uio->uio_resid,uio->uio_segflg)); - - if (ap->a_ioflag & IO_APPEND) { - dprintf(("hpfs_write: APPEND mode\n")); - uio->uio_offset = hp->h_fn.fn_size; - } - if (uio->uio_offset + uio->uio_resid > hp->h_fn.fn_size) { - error = hpfs_extend (hp, uio->uio_offset + uio->uio_resid); - if (error) { - printf("hpfs_write: hpfs_extend FAILED %d\n", error); - return (error); - } - } - - while (uio->uio_resid) { - lbn = uio->uio_offset >> DEV_BSHIFT; - off = uio->uio_offset & (DEV_BSIZE - 1); - dprintf(("hpfs_write: resid: 0x%x lbn: 0x%x off: 0x%x\n", - uio->uio_resid, lbn, off)); - error = hpfs_hpbmap(hp, lbn, &bn, &runl); - if (error) - return (error); - - towrite = min(off + uio->uio_resid, min(DFLTPHYS, (runl+1)*DEV_BSIZE)); - xfersz = (towrite + DEV_BSIZE - 1) & ~(DEV_BSIZE - 1); - dprintf(("hpfs_write: bn: 0x%x (0x%x) towrite: 0x%x (0x%x)\n", - bn, runl, towrite, xfersz)); - - if ((off == 0) && (towrite == xfersz)) { - bp = getblk(hp->h_devvp, bn, xfersz, 0, 0, 0); - clrbuf(bp); - } else { - error = bread(hp->h_devvp, bn, xfersz, NOCRED, &bp); - if (error) { - brelse(bp); - return (error); - } - } - - error = uiomove(bp->b_data + off, towrite - off, uio); - if(error) { - brelse(bp); - return (error); - } - - if (ap->a_ioflag & IO_SYNC) - bwrite(bp); - else - bawrite(bp); - } - - dprintf(("hpfs_write: successful\n")); - return (0); -} - -/* - * XXXXX do we need hpfsnode locking inside? - */ -static int -hpfs_getattr(ap) - struct vop_getattr_args /* { - struct vnode *a_vp; - struct vattr *a_vap; - struct ucred *a_cred; - } */ *ap; -{ - register struct vnode *vp = ap->a_vp; - register struct hpfsnode *hp = VTOHP(vp); - register struct vattr *vap = ap->a_vap; - int error; - - dprintf(("hpfs_getattr(0x%x):\n", hp->h_no)); - - vap->va_fsid = dev2udev(hp->h_dev); - vap->va_fileid = hp->h_no; - vap->va_mode = hp->h_mode; - vap->va_nlink = 1; - vap->va_uid = hp->h_uid; - vap->va_gid = hp->h_gid; - vap->va_rdev = NODEV; - vap->va_size = hp->h_fn.fn_size; - vap->va_bytes = ((hp->h_fn.fn_size + DEV_BSIZE-1) & ~(DEV_BSIZE-1)) + - DEV_BSIZE; - - if (!(hp->h_flag & H_PARVALID)) { - error = hpfs_validateparent(hp); - if (error) - return (error); - } - vap->va_atime = hpfstimetounix(hp->h_atime); - vap->va_mtime = hpfstimetounix(hp->h_mtime); - vap->va_ctime = hpfstimetounix(hp->h_ctime); - - vap->va_flags = 0; - vap->va_gen = 0; - vap->va_blocksize = DEV_BSIZE; - vap->va_type = vp->v_type; - vap->va_filerev = 0; - - return (0); -} - -/* - * XXXXX do we need hpfsnode locking inside? - */ -static int -hpfs_setattr(ap) - struct vop_setattr_args /* { - struct vnode *a_vp; - struct vattr *a_vap; - struct ucred *a_cred; - } */ *ap; -{ - struct vnode *vp = ap->a_vp; - struct hpfsnode *hp = VTOHP(vp); - struct vattr *vap = ap->a_vap; - struct ucred *cred = ap->a_cred; - struct thread *td = curthread; - int error; - - dprintf(("hpfs_setattr(0x%x):\n", hp->h_no)); - - /* - * Check for unsettable attributes. - */ - if ((vap->va_type != VNON) || (vap->va_nlink != VNOVAL) || - (vap->va_fsid != VNOVAL) || (vap->va_fileid != VNOVAL) || - (vap->va_blocksize != VNOVAL) || (vap->va_rdev != VNOVAL) || - (vap->va_bytes != VNOVAL) || (vap->va_gen != VNOVAL)) { - dprintf(("hpfs_setattr: changing nonsettable attr\n")); - return (EINVAL); - } - - /* Can't change flags XXX Could be implemented */ - if (vap->va_flags != VNOVAL) { - printf("hpfs_setattr: FLAGS CANNOT BE SET\n"); - return (EINVAL); - } - - /* Can't change uid/gid XXX Could be implemented */ - if (vap->va_uid != (uid_t)VNOVAL || vap->va_gid != (gid_t)VNOVAL) { - printf("hpfs_setattr: UID/GID CANNOT BE SET\n"); - return (EINVAL); - } - - /* Can't change mode XXX Could be implemented */ - if (vap->va_mode != (mode_t)VNOVAL) { - printf("hpfs_setattr: MODE CANNOT BE SET\n"); - return (EINVAL); - } - - /* Update times */ - if (vap->va_atime.tv_sec != VNOVAL || vap->va_mtime.tv_sec != VNOVAL) { - if (vp->v_mount->mnt_flag & MNT_RDONLY) - return (EROFS); - if (vap->va_vaflags & VA_UTIMES_NULL) { - error = VOP_ACCESS(vp, VADMIN, cred, td); - if (error) - error = VOP_ACCESS(vp, VWRITE, cred, td); - } else - error = VOP_ACCESS(vp, VADMIN, cred, td); - if (vap->va_atime.tv_sec != VNOVAL) - hp->h_atime = vap->va_atime.tv_sec; - if (vap->va_mtime.tv_sec != VNOVAL) - hp->h_mtime = vap->va_mtime.tv_sec; - - hp->h_flag |= H_PARCHANGE; - } - - if (vap->va_size != VNOVAL) { - switch (vp->v_type) { - case VDIR: - return (EISDIR); - case VREG: - if (vp->v_mount->mnt_flag & MNT_RDONLY) - return (EROFS); - break; - default: - printf("hpfs_setattr: WRONG v_type\n"); - return (EINVAL); - } - - if (vap->va_size < hp->h_fn.fn_size) { - error = vtruncbuf(vp, cred, td, vap->va_size, DEV_BSIZE); - if (error) - return (error); - error = hpfs_truncate(hp, vap->va_size); - if (error) - return (error); - - } else if (vap->va_size > hp->h_fn.fn_size) { - vnode_pager_setsize(vp, vap->va_size); - error = hpfs_extend(hp, vap->va_size); - if (error) - return (error); - } - } - - return (0); -} - -/* - * Last reference to a node. If necessary, write or delete it. - */ -int -hpfs_inactive(ap) - struct vop_inactive_args /* { - struct vnode *a_vp; - } */ *ap; -{ - register struct vnode *vp = ap->a_vp; - register struct hpfsnode *hp = VTOHP(vp); - int error; - - dprintf(("hpfs_inactive(0x%x): \n", hp->h_no)); - - if (hp->h_flag & H_CHANGE) { - dprintf(("hpfs_inactive: node changed, update\n")); - error = hpfs_update (hp); - if (error) - return (error); - } - - if (hp->h_flag & H_PARCHANGE) { - dprintf(("hpfs_inactive: parent node changed, update\n")); - error = hpfs_updateparent (hp); - if (error) - return (error); - } - - if (hp->h_flag & H_INVAL) { - vrecycle(vp, ap->a_td); - return (0); - } - - return (0); -} - -/* - * Reclaim an inode so that it can be used for other purposes. - */ -int -hpfs_reclaim(ap) - struct vop_reclaim_args /* { - struct vnode *a_vp; - } */ *ap; -{ - register struct vnode *vp = ap->a_vp; - register struct hpfsnode *hp = VTOHP(vp); - - dprintf(("hpfs_reclaim(0x%x0): \n", hp->h_no)); - - /* - * Destroy the vm object and flush associated pages. - */ - vnode_destroy_vobject(vp); - - vfs_hash_remove(vp); - - mtx_destroy(&hp->h_interlock); - - vp->v_data = NULL; - - free(hp, M_HPFSNO); - - return (0); -} - -static int -hpfs_print(ap) - struct vop_print_args /* { - struct vnode *a_vp; - } */ *ap; -{ - register struct vnode *vp = ap->a_vp; - register struct hpfsnode *hp = VTOHP(vp); - - printf("\tino 0x%x\n", hp->h_no); - return (0); -} - -/* - * Calculate the logical to physical mapping if not done already, - * then call the device strategy routine. - * - * In order to be able to swap to a file, the hpfs_hpbmap operation may not - * deadlock on memory. See hpfs_bmap() for details. XXXXXXX (not impl) - */ -int -hpfs_strategy(ap) - struct vop_strategy_args /* { - struct buf *a_bp; - } */ *ap; -{ - register struct buf *bp = ap->a_bp; - register struct vnode *vp = ap->a_vp; - register struct hpfsnode *hp = VTOHP(ap->a_vp); - daddr_t blkno; - struct bufobj *bo; - int error; - - dprintf(("hpfs_strategy(): \n")); - - if (vp->v_type == VBLK || vp->v_type == VCHR) - panic("hpfs_strategy: spec"); - if (bp->b_blkno == bp->b_lblkno) { - error = hpfs_hpbmap (hp, bp->b_lblkno, &blkno, NULL); - bp->b_blkno = blkno; - if (error) { - printf("hpfs_strategy: hpfs_bpbmap FAILED %d\n", error); - bp->b_error = error; - bp->b_ioflags |= BIO_ERROR; - bufdone(bp); - return (0); - } - if ((long)bp->b_blkno == -1) - vfs_bio_clrbuf(bp); - } - if ((long)bp->b_blkno == -1) { - bufdone(bp); - return (0); - } - bp->b_iooffset = dbtob(bp->b_blkno); - bo = hp->h_hpmp->hpm_bo; - BO_STRATEGY(bo, bp); - return (0); -} - -/* - * XXXXX do we need hpfsnode locking inside? - */ -int -hpfs_access(ap) - struct vop_access_args /* { - struct vnode *a_vp; - accmode_t a_accmode; - struct ucred *a_cred; - struct thread *a_td; - } */ *ap; -{ - struct vnode *vp = ap->a_vp; - struct hpfsnode *hp = VTOHP(vp); - accmode_t accmode = ap->a_accmode; - - dprintf(("hpfs_access(0x%x):\n", hp->h_no)); - - /* - * Disallow write attempts on read-only filesystems; - * unless the file is a socket, fifo, or a block or - * character device resident on the filesystem. - */ - if (accmode & VWRITE) { - switch ((int)vp->v_type) { - case VDIR: - case VLNK: - case VREG: - if (vp->v_mount->mnt_flag & MNT_RDONLY) - return (EROFS); - break; - } - } - - return (vaccess(vp->v_type, hp->h_mode, hp->h_uid, hp->h_gid, - ap->a_accmode, ap->a_cred, NULL)); -} - -/* - * Open called. - * - * Nothing to do. - */ -/* ARGSUSED */ -static int -hpfs_open(ap) - struct vop_open_args /* { - struct vnode *a_vp; - int a_mode; - struct ucred *a_cred; - struct thread *a_td; - } */ *ap; -{ -#ifdef HPFS_DEBUG - register struct vnode *vp = ap->a_vp; - register struct hpfsnode *hp = VTOHP(vp); - - printf("hpfs_open(0x%x):\n",hp->h_no); -#endif - - /* - * Files marked append-only must be opened for appending. - */ - - return (0); -} - -/* - * Close called. - * - * Update the times on the inode. - */ -/* ARGSUSED */ -static int -hpfs_close(ap) - struct vop_close_args /* { - struct vnode *a_vp; - int a_fflag; - struct ucred *a_cred; - struct thread *a_td; - } */ *ap; -{ -#ifdef HPFS_DEBUG - register struct vnode *vp = ap->a_vp; - register struct hpfsnode *hp = VTOHP(vp); - - printf("hpfs_close: %d\n",hp->h_no); -#endif - - return (0); -} - -static int -hpfs_de_uiomove ( - struct hpfsmount *hpmp, - struct hpfsdirent *dep, - struct uio *uio) -{ - struct dirent cde; - int i, error; - - dprintf(("[no: 0x%x, size: %d, name: %2d:%.*s, flag: 0x%x] ", - dep->de_fnode, dep->de_size, dep->de_namelen, - dep->de_namelen, dep->de_name, dep->de_flag)); - - /*strncpy(cde.d_name, dep->de_name, dep->de_namelen);*/ - for (i=0; ide_namelen; i++) - cde.d_name[i] = hpfs_d2u(hpmp, dep->de_name[i]); - - cde.d_name[dep->de_namelen] = '\0'; - cde.d_namlen = dep->de_namelen; - cde.d_fileno = dep->de_fnode; - cde.d_type = (dep->de_flag & DE_DIR) ? DT_DIR : DT_REG; - cde.d_reclen = sizeof(struct dirent); - - error = uiomove((char *)&cde, sizeof(struct dirent), uio); - if (error) - return (error); - - dprintf(("[0x%x] ", uio->uio_resid)); - return (error); -} - - -static struct dirent hpfs_de_dot = - { 0, sizeof(struct dirent), DT_DIR, 1, "." }; -static struct dirent hpfs_de_dotdot = - { 0, sizeof(struct dirent), DT_DIR, 2, ".." }; -int -hpfs_readdir(ap) - struct vop_readdir_args /* { - struct vnode *a_vp; - struct uio *a_uio; - struct ucred *a_cred; - int *a_ncookies; - u_int **cookies; - } */ *ap; -{ - register struct vnode *vp = ap->a_vp; - register struct hpfsnode *hp = VTOHP(vp); - struct hpfsmount *hpmp = hp->h_hpmp; - struct uio *uio = ap->a_uio; - int ncookies = 0, i, num, cnum; - int error = 0; - off_t off; - struct buf *bp; - struct dirblk *dp; - struct hpfsdirent *dep; - lsn_t olsn; - lsn_t lsn; - int level; - - dprintf(("hpfs_readdir(0x%x, 0x%x, 0x%x): ",hp->h_no,(u_int32_t)uio->uio_offset,uio->uio_resid)); - - off = uio->uio_offset; - - if( uio->uio_offset < sizeof(struct dirent) ) { - dprintf((". faked, ")); - hpfs_de_dot.d_fileno = hp->h_no; - error = uiomove((char *)&hpfs_de_dot,sizeof(struct dirent),uio); - if(error) { - return (error); - } - - ncookies ++; - } - - if( uio->uio_offset < 2 * sizeof(struct dirent) ) { - dprintf((".. faked, ")); - hpfs_de_dotdot.d_fileno = hp->h_fn.fn_parent; - - error = uiomove((char *)&hpfs_de_dotdot, sizeof(struct dirent), - uio); - if(error) { - return (error); - } - - ncookies ++; - } - - num = uio->uio_offset / sizeof(struct dirent) - 2; - cnum = 0; - - lsn = ((alleaf_t *)hp->h_fn.fn_abd)->al_lsn; - - olsn = 0; - level = 1; - -dive: - dprintf(("[dive 0x%x] ", lsn)); - error = bread(hp->h_devvp, lsn, D_BSIZE, NOCRED, &bp); - if (error) { - brelse(bp); - return (error); - } - - dp = (struct dirblk *) bp->b_data; - if (dp->d_magic != D_MAGIC) { - printf("hpfs_readdir: MAGIC DOESN'T MATCH\n"); - brelse(bp); - return (EINVAL); - } - - dep = D_DIRENT(dp); - - if (olsn) { - dprintf(("[restore 0x%x] ", olsn)); - - while(!(dep->de_flag & DE_END) ) { - if((dep->de_flag & DE_DOWN) && - (olsn == DE_DOWNLSN(dep))) - break; - dep = (hpfsdirent_t *)((caddr_t)dep + dep->de_reclen); - } - - if((dep->de_flag & DE_DOWN) && (olsn == DE_DOWNLSN(dep))) { - if (dep->de_flag & DE_END) - goto blockdone; - - if (!(dep->de_flag & DE_SPECIAL)) { - if (num <= cnum) { - if (uio->uio_resid < sizeof(struct dirent)) { - brelse(bp); - dprintf(("[resid] ")); - goto readdone; - } - - error = hpfs_de_uiomove(hpmp, dep, uio); - if (error) { - brelse (bp); - return (error); - } - ncookies++; - - if (uio->uio_resid < sizeof(struct dirent)) { - brelse(bp); - dprintf(("[resid] ")); - goto readdone; - } - } - cnum++; - } - - dep = (hpfsdirent_t *)((caddr_t)dep + dep->de_reclen); - } else { - printf("hpfs_readdir: ERROR! oLSN not found\n"); - brelse(bp); - return (EINVAL); - } - } - - olsn = 0; - - while(!(dep->de_flag & DE_END)) { - if(dep->de_flag & DE_DOWN) { - lsn = DE_DOWNLSN(dep); - brelse(bp); - level++; - goto dive; - } - - if (!(dep->de_flag & DE_SPECIAL)) { - if (num <= cnum) { - if (uio->uio_resid < sizeof(struct dirent)) { - brelse(bp); - dprintf(("[resid] ")); - goto readdone; - } - - error = hpfs_de_uiomove(hpmp, dep, uio); - if (error) { - brelse (bp); - return (error); - } - ncookies++; - - if (uio->uio_resid < sizeof(struct dirent)) { - brelse(bp); - dprintf(("[resid] ")); - goto readdone; - } - } - cnum++; - } - - dep = (hpfsdirent_t *)((caddr_t)dep + dep->de_reclen); - } - - if(dep->de_flag & DE_DOWN) { - dprintf(("[enddive] ")); - lsn = DE_DOWNLSN(dep); - brelse(bp); - level++; - goto dive; - } - -blockdone: - dprintf(("[EOB] ")); - olsn = lsn; - lsn = dp->d_parent; - brelse(bp); - level--; - - dprintf(("[level %d] ", level)); - - if (level > 0) - goto dive; /* undive really */ - - if (ap->a_eofflag) { - dprintf(("[EOF] ")); - *ap->a_eofflag = 1; - } - -readdone: - dprintf(("[readdone]\n")); - if (!error && ap->a_ncookies != NULL) { - struct dirent* dpStart; - struct dirent* dp; - u_long *cookies; - u_long *cookiep; - - dprintf(("%d cookies, ",ncookies)); - if (uio->uio_segflg != UIO_SYSSPACE || uio->uio_iovcnt != 1) - panic("hpfs_readdir: unexpected uio from NFS server"); - dpStart = (struct dirent *) - ((caddr_t)uio->uio_iov->iov_base - - (uio->uio_offset - off)); - cookies = malloc(ncookies * sizeof(u_long), - M_TEMP, M_WAITOK); - for (dp = dpStart, cookiep = cookies, i=0; - i < ncookies; - dp = (struct dirent *)((caddr_t) dp + dp->d_reclen), i++) { - off += dp->d_reclen; - *cookiep++ = (u_int) off; - } - *ap->a_ncookies = ncookies; - *ap->a_cookies = cookies; - } - - return (0); -} - -int -hpfs_lookup(ap) - struct vop_cachedlookup_args /* { - struct vnode *a_dvp; - struct vnode **a_vpp; - struct componentname *a_cnp; - } */ *ap; -{ - register struct vnode *dvp = ap->a_dvp; - register struct hpfsnode *dhp = VTOHP(dvp); - struct hpfsmount *hpmp = dhp->h_hpmp; - struct componentname *cnp = ap->a_cnp; - struct ucred *cred = cnp->cn_cred; - int error; - int nameiop = cnp->cn_nameiop; - int flags = cnp->cn_flags; - dprintf(("hpfs_lookup(0x%x, %s, %ld):\n", - dhp->h_no, cnp->cn_nameptr, cnp->cn_namelen)); - - if (nameiop != CREATE && nameiop != DELETE && nameiop != LOOKUP) { - printf("hpfs_lookup: LOOKUP, DELETE and CREATE are only supported\n"); - return (EOPNOTSUPP); - } - - error = VOP_ACCESS(dvp, VEXEC, cred, cnp->cn_thread); - if(error) - return (error); - - if( (cnp->cn_namelen == 1) && - !strncmp(cnp->cn_nameptr,".",1) ) { - dprintf(("hpfs_lookup(0x%x,...): . faked\n",dhp->h_no)); - - VREF(dvp); - *ap->a_vpp = dvp; - - return (0); - } else if( (cnp->cn_namelen == 2) && - !strncmp(cnp->cn_nameptr,"..",2) && (flags & ISDOTDOT) ) { - dprintf(("hpfs_lookup(0x%x,...): .. faked (0x%x)\n", - dhp->h_no, dhp->h_fn.fn_parent)); - - if (VFS_VGET(hpmp->hpm_mp, dhp->h_fn.fn_parent, - LK_NOWAIT | LK_EXCLUSIVE, ap->a_vpp)) { - VOP_UNLOCK(dvp,0); - error = VFS_VGET(hpmp->hpm_mp, - dhp->h_fn.fn_parent, LK_EXCLUSIVE, ap->a_vpp); - vn_lock(dvp, LK_EXCLUSIVE|LK_RETRY); - if (error) - return(error); - } - return (0); - } else { - struct buf *bp; - struct hpfsdirent *dep; - struct hpfsnode *hp; - - error = hpfs_genlookupbyname(dhp, - cnp->cn_nameptr, cnp->cn_namelen, &bp, &dep); - if (error) { - if ((error == ENOENT) && (flags & ISLASTCN) && - (nameiop == CREATE || nameiop == RENAME)) { - cnp->cn_flags |= SAVENAME; - return (EJUSTRETURN); - } - - return (error); - } - - dprintf(("hpfs_lookup: fnode: 0x%x, CPID: 0x%x\n", - dep->de_fnode, dep->de_cpid)); - - if (nameiop == DELETE && (flags & ISLASTCN)) { - error = VOP_ACCESS(dvp, VWRITE, cred, cnp->cn_thread); - if (error) { - brelse(bp); - return (error); - } - } - - if (dhp->h_no == dep->de_fnode) { - brelse(bp); - VREF(dvp); - *ap->a_vpp = dvp; - return (0); - } - - error = VFS_VGET(hpmp->hpm_mp, dep->de_fnode, LK_EXCLUSIVE, - ap->a_vpp); - if (error) { - printf("hpfs_lookup: VFS_VGET FAILED %d\n", error); - brelse(bp); - return(error); - } - - hp = VTOHP(*ap->a_vpp); - - hp->h_mtime = dep->de_mtime; - hp->h_ctime = dep->de_ctime; - hp->h_atime = dep->de_atime; - bcopy(dep->de_name, hp->h_name, dep->de_namelen); - hp->h_name[dep->de_namelen] = '\0'; - hp->h_namelen = dep->de_namelen; - hp->h_flag |= H_PARVALID; - - brelse(bp); - - if ((flags & MAKEENTRY) && - (!(flags & ISLASTCN) || - (nameiop != DELETE && nameiop != CREATE))) - cache_enter(dvp, *ap->a_vpp, cnp); - } - return (error); -} - -int -hpfs_remove(ap) - struct vop_remove_args /* { - struct vnode *a_dvp; - struct vnode *a_vp; - struct componentname *a_cnp; - } */ *ap; -{ - int error; - - dprintf(("hpfs_remove(0x%x, %s, %ld): \n", VTOHP(ap->a_vp)->h_no, - ap->a_cnp->cn_nameptr, ap->a_cnp->cn_namelen)); - - if (ap->a_vp->v_type == VDIR) - return (EPERM); - - error = hpfs_removefnode (ap->a_dvp, ap->a_vp, ap->a_cnp); - return (error); -} - -int -hpfs_create(ap) - struct vop_create_args /* { - struct vnode *a_dvp; - struct vnode **a_vpp; - struct componentname *a_cnp; - struct vattr *a_vap; - } */ *ap; -{ - int error; - - dprintf(("hpfs_create(0x%x, %s, %ld): \n", VTOHP(ap->a_dvp)->h_no, - ap->a_cnp->cn_nameptr, ap->a_cnp->cn_namelen)); - - if (!(ap->a_cnp->cn_flags & HASBUF)) - panic ("hpfs_create: no name\n"); - - error = hpfs_makefnode (ap->a_dvp, ap->a_vpp, ap->a_cnp, ap->a_vap); - - return (error); -} - -/* - * Return POSIX pathconf information applicable to NTFS filesystem - */ -int -hpfs_pathconf(ap) - struct vop_pathconf_args /* { - struct vnode *a_vp; - int a_name; - register_t *a_retval; - } */ *ap; -{ - switch (ap->a_name) { - case _PC_LINK_MAX: - *ap->a_retval = 1; - return (0); - case _PC_NAME_MAX: - *ap->a_retval = HPFS_MAXFILENAME; - return (0); - case _PC_PATH_MAX: - *ap->a_retval = PATH_MAX; - return (0); - case _PC_CHOWN_RESTRICTED: - *ap->a_retval = 1; - return (0); - case _PC_NO_TRUNC: - *ap->a_retval = 0; - return (0); - default: - return (EINVAL); - } - /* NOTREACHED */ -} - -int -hpfs_vptofh(ap) - struct vop_vptofh_args /* { - struct vnode *a_vp; - struct fid *a_fhp; - } */ *ap; -{ - register struct hpfsnode *hpp; - register struct hpfid *hpfhp; - - hpp = VTOHP(ap->a_vp); - hpfhp = (struct hpfid *)ap->a_fhp; - hpfhp->hpfid_len = sizeof(struct hpfid); - hpfhp->hpfid_ino = hpp->h_no; - /* hpfhp->hpfid_gen = hpp->h_gen; */ - return (0); -} - - -/* - * Global vfs data structures - */ -struct vop_vector hpfs_vnodeops = { - .vop_default = &default_vnodeops, - - .vop_access = hpfs_access, - .vop_bmap = hpfs_bmap, - .vop_cachedlookup = hpfs_lookup, - .vop_close = hpfs_close, - .vop_create = hpfs_create, - .vop_fsync = hpfs_fsync, - .vop_getattr = hpfs_getattr, - .vop_inactive = hpfs_inactive, - .vop_ioctl = hpfs_ioctl, - .vop_lookup = vfs_cache_lookup, - .vop_open = hpfs_open, - .vop_pathconf = hpfs_pathconf, - .vop_print = hpfs_print, - .vop_read = hpfs_read, - .vop_readdir = hpfs_readdir, - .vop_reclaim = hpfs_reclaim, - .vop_remove = hpfs_remove, - .vop_setattr = hpfs_setattr, - .vop_strategy = hpfs_strategy, - .vop_write = hpfs_write, - .vop_vptofh = hpfs_vptofh, -}; diff --git a/sys/fs/hpfs/hpfsmount.h b/sys/fs/hpfs/hpfsmount.h deleted file mode 100644 index 7f5cd1e9848..00000000000 --- a/sys/fs/hpfs/hpfsmount.h +++ /dev/null @@ -1,38 +0,0 @@ -/*- - * Copyright (c) 1998, 1999 Semen Ustimenko (semenu@FreeBSD.org) - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - */ - -#define HPFSMNT_TABLES 0x0001 -struct hpfs_args { - char *fspec; /* block special device to mount */ - struct oexport_args export; /* network export information */ - uid_t uid; /* uid that owns hpfs files */ - gid_t gid; /* gid that owns hpfs files */ - mode_t mode; /* mask to be applied for hpfs perms */ - u_long flags; /* additional flags */ - u_char d2u[0x80]; - u_char u2d[0x80]; -}; diff --git a/sys/fs/msdosfs/msdosfs_fileno.c b/sys/fs/msdosfs/msdosfs_fileno.c deleted file mode 100644 index bddffcba9ac..00000000000 --- a/sys/fs/msdosfs/msdosfs_fileno.c +++ /dev/null @@ -1,151 +0,0 @@ -/*- - * Copyright (c) 2003-2004 Tim J. Robbins. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ -/* - * Compress 64-bit file numbers into temporary, unique 32-bit file numbers. - * This is needed because the algorithm we use to calculate these numbers - * generates 64-bit quantities, but struct dirent's d_fileno member and - * struct vnodeattr's va_fileid member only have space for 32 bits. - * - * 32-bit file numbers are generated sequentially, and stored in a - * red-black tree, indexed on 64-bit file number. The mappings do not - * persist across reboots (or unmounts); anything that relies on this - * (e.g. NFS) will not work correctly. This scheme consumes 32 bytes - * of kernel memory per file (on i386), and it may be possible for a user - * to cause a panic by creating millions of tiny files. - * - * As an optimization, we split the file number space between statically - * allocated and dynamically allocated. File numbers less than - * FILENO_FIRST_DYN are left unchanged and do not have any tree nodes - * allocated to them. - */ - -#include - -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -static MALLOC_DEFINE(M_MSDOSFSFILENO, "msdosfs_fileno", "MSDOSFS fileno mapping node"); - -RB_PROTOTYPE(msdosfs_filenotree, msdosfs_fileno, mf_tree, - msdosfs_fileno_compare) - -static int msdosfs_fileno_compare(struct msdosfs_fileno *, - struct msdosfs_fileno *); - -#define FILENO_FIRST_DYN 0xf0000000 - -/* Initialize file number mapping structures. */ -void -msdosfs_fileno_init(struct mount *mp) -{ - struct msdosfsmount *pmp = VFSTOMSDOSFS(mp); - - RB_INIT(&pmp->pm_filenos); - pmp->pm_nfileno = FILENO_FIRST_DYN; - if (pmp->pm_HugeSectors > 0xffffffff / - (pmp->pm_BytesPerSec / sizeof(struct direntry)) + 1) - pmp->pm_flags |= MSDOSFS_LARGEFS; -} - -/* Free 32-bit file number generation structures. */ -void -msdosfs_fileno_free(struct mount *mp) -{ - struct msdosfsmount *pmp = VFSTOMSDOSFS(mp); - struct msdosfs_fileno *mf, *next; - - for (mf = RB_MIN(msdosfs_filenotree, &pmp->pm_filenos); mf != NULL; - mf = next) { - next = RB_NEXT(msdosfs_filenotree, &pmp->pm_filenos, mf); - RB_REMOVE(msdosfs_filenotree, &pmp->pm_filenos, mf); - free(mf, M_MSDOSFSFILENO); - } -} - -/* Map a 64-bit file number into a 32-bit one. */ -uint32_t -msdosfs_fileno_map(struct mount *mp, uint64_t fileno) -{ - struct msdosfsmount *pmp = VFSTOMSDOSFS(mp); - struct msdosfs_fileno key, *mf, *tmf; - uint32_t mapped; - - if ((pmp->pm_flags & MSDOSFS_LARGEFS) == 0) { - KASSERT((uint32_t)fileno == fileno, - ("fileno >32 bits but not a large fs?")); - return ((uint32_t)fileno); - } - if (fileno < FILENO_FIRST_DYN) - return ((uint32_t)fileno); - MSDOSFS_LOCK_MP(pmp); - key.mf_fileno64 = fileno; - mf = RB_FIND(msdosfs_filenotree, &pmp->pm_filenos, &key); - if (mf != NULL) { - mapped = mf->mf_fileno32; - MSDOSFS_UNLOCK_MP(pmp); - return (mapped); - } - if (pmp->pm_nfileno < FILENO_FIRST_DYN) - panic("msdosfs_fileno_map: wraparound"); - MSDOSFS_UNLOCK_MP(pmp); - mf = malloc(sizeof(*mf), M_MSDOSFSFILENO, M_WAITOK); - MSDOSFS_LOCK_MP(pmp); - tmf = RB_FIND(msdosfs_filenotree, &pmp->pm_filenos, &key); - if (tmf != NULL) { - mapped = tmf->mf_fileno32; - MSDOSFS_UNLOCK_MP(pmp); - free(mf, M_MSDOSFSFILENO); - return (mapped); - } - mf->mf_fileno64 = fileno; - mapped = mf->mf_fileno32 = pmp->pm_nfileno++; - RB_INSERT(msdosfs_filenotree, &pmp->pm_filenos, mf); - MSDOSFS_UNLOCK_MP(pmp); - return (mapped); -} - -/* Compare by 64-bit file number. */ -static int -msdosfs_fileno_compare(struct msdosfs_fileno *fa, struct msdosfs_fileno *fb) -{ - - if (fa->mf_fileno64 > fb->mf_fileno64) - return (1); - else if (fa->mf_fileno64 < fb->mf_fileno64) - return (-1); - return (0); -} - -RB_GENERATE(msdosfs_filenotree, msdosfs_fileno, mf_tree, - msdosfs_fileno_compare) diff --git a/sys/fs/nandfs/bmap.c b/sys/fs/nandfs/bmap.c deleted file mode 100644 index 44c777a962d..00000000000 --- a/sys/fs/nandfs/bmap.c +++ /dev/null @@ -1,624 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2012 Semihalf - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include - -#include -#include -#include -#include - -#include "nandfs_mount.h" -#include "nandfs.h" -#include "nandfs_subr.h" -#include "bmap.h" - -static int bmap_getlbns(struct nandfs_node *, nandfs_lbn_t, - struct nandfs_indir *, int *); - -int -bmap_lookup(struct nandfs_node *node, nandfs_lbn_t lblk, nandfs_daddr_t *vblk) -{ - struct nandfs_inode *ip; - struct nandfs_indir a[NANDFS_NIADDR + 1], *ap; - nandfs_daddr_t daddr; - struct buf *bp; - int error; - int num, *nump; - - DPRINTF(BMAP, ("%s: node %p lblk %jx enter\n", __func__, node, lblk)); - ip = &node->nn_inode; - - ap = a; - nump = # - - error = bmap_getlbns(node, lblk, ap, nump); - if (error) - return (error); - - if (num == 0) { - *vblk = ip->i_db[lblk]; - return (0); - } - - DPRINTF(BMAP, ("%s: node %p lblk=%jx trying ip->i_ib[%x]\n", __func__, - node, lblk, ap->in_off)); - daddr = ip->i_ib[ap->in_off]; - for (bp = NULL, ++ap; --num; ap++) { - if (daddr == 0) { - DPRINTF(BMAP, ("%s: node %p lblk=%jx returning with " - "vblk 0\n", __func__, node, lblk)); - *vblk = 0; - return (0); - } - if (ap->in_lbn == lblk) { - DPRINTF(BMAP, ("%s: node %p lblk=%jx ap->in_lbn=%jx " - "returning address of indirect block (%jx)\n", - __func__, node, lblk, ap->in_lbn, daddr)); - *vblk = daddr; - return (0); - } - - DPRINTF(BMAP, ("%s: node %p lblk=%jx reading block " - "ap->in_lbn=%jx\n", __func__, node, lblk, ap->in_lbn)); - - error = nandfs_bread_meta(node, ap->in_lbn, NOCRED, 0, &bp); - if (error) { - brelse(bp); - return (error); - } - - daddr = ((nandfs_daddr_t *)bp->b_data)[ap->in_off]; - brelse(bp); - } - - DPRINTF(BMAP, ("%s: node %p lblk=%jx returning with %jx\n", __func__, - node, lblk, daddr)); - *vblk = daddr; - - return (0); -} - -int -bmap_dirty_meta(struct nandfs_node *node, nandfs_lbn_t lblk, int force) -{ - struct nandfs_indir a[NANDFS_NIADDR+1], *ap; -#ifdef DEBUG - nandfs_daddr_t daddr; -#endif - struct buf *bp; - int error; - int num, *nump; - - DPRINTF(BMAP, ("%s: node %p lblk=%jx\n", __func__, node, lblk)); - - ap = a; - nump = # - - error = bmap_getlbns(node, lblk, ap, nump); - if (error) - return (error); - - /* - * Direct block, nothing to do - */ - if (num == 0) - return (0); - - DPRINTF(BMAP, ("%s: node %p reading blocks\n", __func__, node)); - - for (bp = NULL, ++ap; --num; ap++) { - error = nandfs_bread_meta(node, ap->in_lbn, NOCRED, 0, &bp); - if (error) { - brelse(bp); - return (error); - } - -#ifdef DEBUG - daddr = ((nandfs_daddr_t *)bp->b_data)[ap->in_off]; - MPASS(daddr != 0 || node->nn_ino == 3); -#endif - - error = nandfs_dirty_buf_meta(bp, force); - if (error) - return (error); - } - - return (0); -} - -int -bmap_insert_block(struct nandfs_node *node, nandfs_lbn_t lblk, - nandfs_daddr_t vblk) -{ - struct nandfs_inode *ip; - struct nandfs_indir a[NANDFS_NIADDR+1], *ap; - struct buf *bp; - nandfs_daddr_t daddr; - int error; - int num, *nump, i; - - DPRINTF(BMAP, ("%s: node %p lblk=%jx vblk=%jx\n", __func__, node, lblk, - vblk)); - - ip = &node->nn_inode; - - ap = a; - nump = # - - error = bmap_getlbns(node, lblk, ap, nump); - if (error) - return (error); - - DPRINTF(BMAP, ("%s: node %p lblk=%jx vblk=%jx got num=%d\n", __func__, - node, lblk, vblk, num)); - - if (num == 0) { - DPRINTF(BMAP, ("%s: node %p lblk=%jx direct block\n", __func__, - node, lblk)); - ip->i_db[lblk] = vblk; - return (0); - } - - DPRINTF(BMAP, ("%s: node %p lblk=%jx indirect block level %d\n", - __func__, node, lblk, ap->in_off)); - - if (num == 1) { - DPRINTF(BMAP, ("%s: node %p lblk=%jx indirect block: inserting " - "%jx as vblk for indirect block %d\n", __func__, node, - lblk, vblk, ap->in_off)); - ip->i_ib[ap->in_off] = vblk; - return (0); - } - - bp = NULL; - daddr = ip->i_ib[a[0].in_off]; - for (i = 1; i < num; i++) { - if (bp) - brelse(bp); - if (daddr == 0) { - DPRINTF(BMAP, ("%s: node %p lblk=%jx vblk=%jx create " - "block %jx %d\n", __func__, node, lblk, vblk, - a[i].in_lbn, a[i].in_off)); - error = nandfs_bcreate_meta(node, a[i].in_lbn, NOCRED, - 0, &bp); - if (error) - return (error); - } else { - DPRINTF(BMAP, ("%s: node %p lblk=%jx vblk=%jx read " - "block %jx %d\n", __func__, node, daddr, vblk, - a[i].in_lbn, a[i].in_off)); - error = nandfs_bread_meta(node, a[i].in_lbn, NOCRED, 0, &bp); - if (error) { - brelse(bp); - return (error); - } - } - daddr = ((nandfs_daddr_t *)bp->b_data)[a[i].in_off]; - } - i--; - - DPRINTF(BMAP, - ("%s: bmap node %p lblk=%jx vblk=%jx inserting vblk level %d at " - "offset %d at %jx\n", __func__, node, lblk, vblk, i, a[i].in_off, - daddr)); - - if (!bp) { - nandfs_error("%s: cannot find indirect block\n", __func__); - return (-1); - } - ((nandfs_daddr_t *)bp->b_data)[a[i].in_off] = vblk; - - error = nandfs_dirty_buf_meta(bp, 0); - if (error) { - nandfs_warning("%s: dirty failed buf: %p\n", __func__, bp); - return (error); - } - DPRINTF(BMAP, ("%s: exiting node %p lblk=%jx vblk=%jx\n", __func__, - node, lblk, vblk)); - - return (error); -} - -CTASSERT(NANDFS_NIADDR <= 3); -#define SINGLE 0 /* index of single indirect block */ -#define DOUBLE 1 /* index of double indirect block */ -#define TRIPLE 2 /* index of triple indirect block */ - -static __inline nandfs_lbn_t -lbn_offset(struct nandfs_device *fsdev, int level) -{ - nandfs_lbn_t res; - - for (res = 1; level > 0; level--) - res *= MNINDIR(fsdev); - return (res); -} - -static nandfs_lbn_t -blocks_inside(struct nandfs_device *fsdev, int level, struct nandfs_indir *nip) -{ - nandfs_lbn_t blocks; - - for (blocks = 1; level >= SINGLE; level--, nip++) { - MPASS(nip->in_off >= 0 && nip->in_off < MNINDIR(fsdev)); - blocks += nip->in_off * lbn_offset(fsdev, level); - } - - return (blocks); -} - -static int -bmap_truncate_indirect(struct nandfs_node *node, int level, nandfs_lbn_t *left, - int *cleaned, struct nandfs_indir *ap, struct nandfs_indir *fp, - nandfs_daddr_t *copy) -{ - struct buf *bp; - nandfs_lbn_t i, lbn, nlbn, factor, tosub; - struct nandfs_device *fsdev; - int error, lcleaned, modified; - - DPRINTF(BMAP, ("%s: node %p level %d left %jx\n", __func__, - node, level, *left)); - - fsdev = node->nn_nandfsdev; - - MPASS(ap->in_off >= 0 && ap->in_off < MNINDIR(fsdev)); - - factor = lbn_offset(fsdev, level); - lbn = ap->in_lbn; - - error = nandfs_bread_meta(node, lbn, NOCRED, 0, &bp); - if (error) { - if (bp != NULL) - brelse(bp); - return (error); - } - - bcopy(bp->b_data, copy, fsdev->nd_blocksize); - bqrelse(bp); - - modified = 0; - - i = ap->in_off; - - if (ap != fp) - ap++; - for (nlbn = lbn + 1 - i * factor; i >= 0 && *left > 0; i--, - nlbn += factor) { - lcleaned = 0; - - DPRINTF(BMAP, - ("%s: node %p i=%jx nlbn=%jx left=%jx ap=%p vblk %jx\n", - __func__, node, i, nlbn, *left, ap, copy[i])); - - if (copy[i] == 0) { - tosub = blocks_inside(fsdev, level - 1, ap); - if (tosub > *left) - tosub = 0; - - *left -= tosub; - } else { - if (level > SINGLE) { - if (ap == fp) - ap->in_lbn = nlbn; - - error = bmap_truncate_indirect(node, level - 1, - left, &lcleaned, ap, fp, - copy + MNINDIR(fsdev)); - if (error) - return (error); - } else { - error = nandfs_bdestroy(node, copy[i]); - if (error) - return (error); - lcleaned = 1; - *left -= 1; - } - } - - if (lcleaned) { - if (level > SINGLE) { - error = nandfs_vblock_end(fsdev, copy[i]); - if (error) - return (error); - } - copy[i] = 0; - modified++; - } - - ap = fp; - } - - if (i == -1) - *cleaned = 1; - - error = nandfs_bread_meta(node, lbn, NOCRED, 0, &bp); - if (error) { - brelse(bp); - return (error); - } - if (modified) - bcopy(copy, bp->b_data, fsdev->nd_blocksize); - - /* Force success even if we can't dirty the buffer metadata when freeing space */ - nandfs_dirty_buf_meta(bp, 1); - - return (0); -} - -int -bmap_truncate_mapping(struct nandfs_node *node, nandfs_lbn_t lastblk, - nandfs_lbn_t todo) -{ - struct nandfs_inode *ip; - struct nandfs_indir a[NANDFS_NIADDR + 1], f[NANDFS_NIADDR], *ap; - nandfs_daddr_t indir_lbn[NANDFS_NIADDR]; - nandfs_daddr_t *copy; - int error, level; - nandfs_lbn_t left, tosub; - struct nandfs_device *fsdev; - int cleaned, i; - int num, *nump; - - DPRINTF(BMAP, ("%s: node %p lastblk %jx truncating by %jx\n", __func__, - node, lastblk, todo)); - - ip = &node->nn_inode; - fsdev = node->nn_nandfsdev; - - ap = a; - nump = # - - error = bmap_getlbns(node, lastblk, ap, nump); - if (error) - return (error); - - indir_lbn[SINGLE] = -NANDFS_NDADDR; - indir_lbn[DOUBLE] = indir_lbn[SINGLE] - MNINDIR(fsdev) - 1; - indir_lbn[TRIPLE] = indir_lbn[DOUBLE] - MNINDIR(fsdev) - * MNINDIR(fsdev) - 1; - - for (i = 0; i < NANDFS_NIADDR; i++) { - f[i].in_off = MNINDIR(fsdev) - 1; - f[i].in_lbn = 0xdeadbeef; - } - - left = todo; - -#ifdef DEBUG - a[num].in_off = -1; -#endif - - ap++; - num -= 2; - - if (num < 0) - goto direct; - - copy = malloc(MNINDIR(fsdev) * sizeof(nandfs_daddr_t) * (num + 1), - M_NANDFSTEMP, M_WAITOK); - - for (level = num; level >= SINGLE && left > 0; level--) { - cleaned = 0; - - if (ip->i_ib[level] == 0) { - tosub = blocks_inside(fsdev, level, ap); - if (tosub > left) - left = 0; - else - left -= tosub; - } else { - if (ap == f) - ap->in_lbn = indir_lbn[level]; - error = bmap_truncate_indirect(node, level, &left, - &cleaned, ap, f, copy); - if (error) { - free(copy, M_NANDFSTEMP); - nandfs_error("%s: error %d when truncate " - "at level %d\n", __func__, error, level); - return (error); - } - } - - if (cleaned) { - nandfs_vblock_end(fsdev, ip->i_ib[level]); - ip->i_ib[level] = 0; - } - - ap = f; - } - - free(copy, M_NANDFSTEMP); - -direct: - if (num < 0) - i = lastblk; - else - i = NANDFS_NDADDR - 1; - - for (; i >= 0 && left > 0; i--) { - if (ip->i_db[i] != 0) { - error = nandfs_bdestroy(node, ip->i_db[i]); - if (error) { - nandfs_error("%s: cannot destroy " - "block %jx, error %d\n", __func__, - (uintmax_t)ip->i_db[i], error); - return (error); - } - ip->i_db[i] = 0; - } - - left--; - } - - KASSERT(left == 0, - ("truncated wrong number of blocks (%jd should be 0)", left)); - - return (error); -} - -nandfs_lbn_t -get_maxfilesize(struct nandfs_device *fsdev) -{ - struct nandfs_indir f[NANDFS_NIADDR]; - nandfs_lbn_t max; - int i; - - max = NANDFS_NDADDR; - - for (i = 0; i < NANDFS_NIADDR; i++) { - f[i].in_off = MNINDIR(fsdev) - 1; - max += blocks_inside(fsdev, i, f); - } - - max *= fsdev->nd_blocksize; - - return (max); -} - -/* - * This is ufs_getlbns with minor modifications. - */ -/* - * Create an array of logical block number/offset pairs which represent the - * path of indirect blocks required to access a data block. The first "pair" - * contains the logical block number of the appropriate single, double or - * triple indirect block and the offset into the inode indirect block array. - * Note, the logical block number of the inode single/double/triple indirect - * block appears twice in the array, once with the offset into the i_ib and - * once with the offset into the page itself. - */ -static int -bmap_getlbns(struct nandfs_node *node, nandfs_lbn_t bn, struct nandfs_indir *ap, int *nump) -{ - nandfs_daddr_t blockcnt; - nandfs_lbn_t metalbn, realbn; - struct nandfs_device *fsdev; - int i, numlevels, off; - - fsdev = node->nn_nandfsdev; - - DPRINTF(BMAP, ("%s: node %p bn=%jx mnindir=%zd enter\n", __func__, - node, bn, MNINDIR(fsdev))); - - if (nump) - *nump = 0; - numlevels = 0; - realbn = bn; - - if (bn < 0) - bn = -bn; - - /* The first NANDFS_NDADDR blocks are direct blocks. */ - if (bn < NANDFS_NDADDR) - return (0); - - /* - * Determine the number of levels of indirection. After this loop - * is done, blockcnt indicates the number of data blocks possible - * at the previous level of indirection, and NANDFS_NIADDR - i is the - * number of levels of indirection needed to locate the requested block. - */ - for (blockcnt = 1, i = NANDFS_NIADDR, bn -= NANDFS_NDADDR;; i--, bn -= blockcnt) { - DPRINTF(BMAP, ("%s: blockcnt=%jd i=%d bn=%jd\n", __func__, - blockcnt, i, bn)); - if (i == 0) - return (EFBIG); - blockcnt *= MNINDIR(fsdev); - if (bn < blockcnt) - break; - } - - /* Calculate the address of the first meta-block. */ - if (realbn >= 0) - metalbn = -(realbn - bn + NANDFS_NIADDR - i); - else - metalbn = -(-realbn - bn + NANDFS_NIADDR - i); - - /* - * At each iteration, off is the offset into the bap array which is - * an array of disk addresses at the current level of indirection. - * The logical block number and the offset in that block are stored - * into the argument array. - */ - ap->in_lbn = metalbn; - ap->in_off = off = NANDFS_NIADDR - i; - - DPRINTF(BMAP, ("%s: initial: ap->in_lbn=%jx ap->in_off=%d\n", __func__, - metalbn, off)); - - ap++; - for (++numlevels; i <= NANDFS_NIADDR; i++) { - /* If searching for a meta-data block, quit when found. */ - if (metalbn == realbn) - break; - - blockcnt /= MNINDIR(fsdev); - off = (bn / blockcnt) % MNINDIR(fsdev); - - ++numlevels; - ap->in_lbn = metalbn; - ap->in_off = off; - - DPRINTF(BMAP, ("%s: in_lbn=%jx in_off=%d\n", __func__, - ap->in_lbn, ap->in_off)); - ++ap; - - metalbn -= -1 + off * blockcnt; - } - if (nump) - *nump = numlevels; - - DPRINTF(BMAP, ("%s: numlevels=%d\n", __func__, numlevels)); - - return (0); -} diff --git a/sys/fs/nandfs/bmap.h b/sys/fs/nandfs/bmap.h deleted file mode 100644 index 2ab59ac86ce..00000000000 --- a/sys/fs/nandfs/bmap.h +++ /dev/null @@ -1,41 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2012 Semihalf - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef _BMAP_H -#define _BMAP_H - -#include "nandfs_fs.h" - -int bmap_lookup(struct nandfs_node *, nandfs_lbn_t, nandfs_daddr_t *); -int bmap_insert_block(struct nandfs_node *, nandfs_lbn_t, nandfs_daddr_t); -int bmap_truncate_mapping(struct nandfs_node *, nandfs_lbn_t, nandfs_lbn_t); -int bmap_dirty_meta(struct nandfs_node *, nandfs_lbn_t, int); - -nandfs_lbn_t get_maxfilesize(struct nandfs_device *); - -#endif /* _BMAP_H */ diff --git a/sys/fs/nandfs/nandfs.h b/sys/fs/nandfs/nandfs.h deleted file mode 100644 index e2acdf93c0a..00000000000 --- a/sys/fs/nandfs/nandfs.h +++ /dev/null @@ -1,311 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2010-2012 Semihalf - * Copyright (c) 2008, 2009 Reinoud Zandijk - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * From: NetBSD: nilfs.h,v 1.1 2009/07/18 16:31:42 reinoud - * - */ - -#ifndef _FS_NANDFS_NANDFS_H_ -#define _FS_NANDFS_NANDFS_H_ - -#include -#include -#include -#include -#include - -#include -#include -#include - -#include -#include -#include "nandfs_fs.h" - -MALLOC_DECLARE(M_NANDFSTEMP); - -/* Debug categories */ -#define NANDFS_DEBUG_VOLUMES 0x000001 -#define NANDFS_DEBUG_BLOCK 0x000004 -#define NANDFS_DEBUG_LOCKING 0x000008 -#define NANDFS_DEBUG_NODE 0x000010 -#define NANDFS_DEBUG_LOOKUP 0x000020 -#define NANDFS_DEBUG_READDIR 0x000040 -#define NANDFS_DEBUG_TRANSLATE 0x000080 -#define NANDFS_DEBUG_STRATEGY 0x000100 -#define NANDFS_DEBUG_READ 0x000200 -#define NANDFS_DEBUG_WRITE 0x000400 -#define NANDFS_DEBUG_IFILE 0x000800 -#define NANDFS_DEBUG_ATTR 0x001000 -#define NANDFS_DEBUG_EXTATTR 0x002000 -#define NANDFS_DEBUG_ALLOC 0x004000 -#define NANDFS_DEBUG_CPFILE 0x008000 -#define NANDFS_DEBUG_DIRHASH 0x010000 -#define NANDFS_DEBUG_NOTIMPL 0x020000 -#define NANDFS_DEBUG_SHEDULE 0x040000 -#define NANDFS_DEBUG_SEG 0x080000 -#define NANDFS_DEBUG_SYNC 0x100000 -#define NANDFS_DEBUG_PARANOIA 0x200000 -#define NANDFS_DEBUG_VNCALL 0x400000 -#define NANDFS_DEBUG_BUF 0x1000000 -#define NANDFS_DEBUG_BMAP 0x2000000 -#define NANDFS_DEBUG_DAT 0x4000000 -#define NANDFS_DEBUG_GENERIC 0x8000000 -#define NANDFS_DEBUG_CLEAN 0x10000000 - -extern int nandfs_verbose; - -#define DPRINTF(name, arg) { \ - if (nandfs_verbose & NANDFS_DEBUG_##name) {\ - printf arg;\ - };\ - } -#define DPRINTFIF(name, cond, arg) { \ - if (nandfs_verbose & NANDFS_DEBUG_##name) { \ - if (cond) printf arg;\ - };\ - } - -#define VFSTONANDFS(mp) ((struct nandfsmount *)((mp)->mnt_data)) -#define VTON(vp) ((struct nandfs_node *)(vp)->v_data) -#define NTOV(xp) ((xp)->nn_vnode) - -int nandfs_init(struct vfsconf *); -int nandfs_uninit(struct vfsconf *); - -extern struct vop_vector nandfs_vnodeops; -extern struct vop_vector nandfs_system_vnodeops; - -struct nandfs_node; - -/* Structure and derivatives */ -struct nandfs_mdt { - uint32_t entries_per_block; - uint32_t entries_per_group; - uint32_t blocks_per_group; - uint32_t groups_per_desc_block; /* desc is super group */ - uint32_t blocks_per_desc_block; /* desc is super group */ -}; - -struct nandfs_segment { - LIST_ENTRY(nandfs_segment) seg_link; - - struct nandfs_device *fsdev; - - TAILQ_HEAD(, buf) segsum; - TAILQ_HEAD(, buf) data; - - uint64_t seg_num; - uint64_t seg_next; - uint64_t start_block; - uint32_t num_blocks; - - uint32_t nblocks; - uint32_t nbinfos; - uint32_t segsum_blocks; - uint32_t segsum_bytes; - uint32_t bytes_left; - char *current_off; -}; - -struct nandfs_seginfo { - LIST_HEAD( ,nandfs_segment) seg_list; - struct nandfs_segment *curseg; - struct nandfs_device *fsdev; - uint32_t blocks; - uint8_t reiterate; -}; - -#define NANDFS_FSSTOR_FAILED 1 -struct nandfs_fsarea { - int offset; - int flags; - int last_used; -}; - -extern int nandfs_cleaner_enable; -extern int nandfs_cleaner_interval; -extern int nandfs_cleaner_segments; - -struct nandfs_device { - struct vnode *nd_devvp; - struct g_consumer *nd_gconsumer; - - struct thread *nd_syncer; - struct thread *nd_cleaner; - int nd_syncer_exit; - int nd_cleaner_exit; - - struct nandfs_fsarea nd_fsarea[NANDFS_NFSAREAS]; - int nd_last_fsarea; - - STAILQ_HEAD(nandfs_mnts, nandfsmount) nd_mounts; - SLIST_ENTRY(nandfs_device) nd_next_device; - - /* FS structures */ - struct nandfs_fsdata nd_fsdata; - struct nandfs_super_block nd_super; - struct nandfs_segment_summary nd_last_segsum; - struct nandfs_super_root nd_super_root; - struct nandfs_node *nd_dat_node; - struct nandfs_node *nd_cp_node; - struct nandfs_node *nd_su_node; - struct nandfs_node *nd_gc_node; - - struct nandfs_mdt nd_dat_mdt; - struct nandfs_mdt nd_ifile_mdt; - - struct timespec nd_ts; - - /* Synchronization */ - struct mtx nd_mutex; - struct mtx nd_sync_mtx; - struct cv nd_sync_cv; - struct mtx nd_clean_mtx; - struct cv nd_clean_cv; - struct lock nd_seg_const; - - struct nandfs_seginfo *nd_seginfo; - - /* FS geometry */ - uint64_t nd_devsize; - uint64_t nd_maxfilesize; - uint32_t nd_blocksize; - uint32_t nd_erasesize; - - uint32_t nd_devblocksize; - - uint32_t nd_segs_reserved; - - /* Segment usage */ - uint64_t nd_clean_segs; - uint64_t *nd_free_base; - uint64_t nd_free_count; - uint64_t nd_dirty_bufs; - - /* Running values */ - uint64_t nd_seg_sequence; - uint64_t nd_seg_num; - uint64_t nd_next_seg_num; - uint64_t nd_last_pseg; - uint64_t nd_last_cno; - uint64_t nd_last_ino; - uint64_t nd_fakevblk; - - int nd_mount_state; - int nd_refcnt; - int nd_syncing; - int nd_cleaning; -}; - -extern SLIST_HEAD(_nandfs_devices, nandfs_device) nandfs_devices; - -#define NANDFS_FORCE_SYNCER 0x1 -#define NANDFS_UMOUNT 0x2 - -#define SYNCER_UMOUNT 0x0 -#define SYNCER_VFS_SYNC 0x1 -#define SYNCER_BDFLUSH 0x2 -#define SYNCER_FFORCE 0x3 -#define SYNCER_FSYNC 0x4 -#define SYNCER_ROUPD 0x5 - -static __inline int -nandfs_writelockflags(struct nandfs_device *fsdev, int flags) -{ - int error = 0; - - if (lockstatus(&fsdev->nd_seg_const) != LK_EXCLUSIVE) - error = lockmgr(&fsdev->nd_seg_const, flags | LK_SHARED, NULL); - - return (error); -} - -static __inline void -nandfs_writeunlock(struct nandfs_device *fsdev) -{ - - if (lockstatus(&fsdev->nd_seg_const) != LK_EXCLUSIVE) - lockmgr(&(fsdev)->nd_seg_const, LK_RELEASE, NULL); -} - -#define NANDFS_WRITELOCKFLAGS(fsdev, flags) nandfs_writelockflags(fsdev, flags) - -#define NANDFS_WRITELOCK(fsdev) NANDFS_WRITELOCKFLAGS(fsdev, 0) - -#define NANDFS_WRITEUNLOCK(fsdev) nandfs_writeunlock(fsdev) - -#define NANDFS_WRITEASSERT(fsdev) lockmgr_assert(&(fsdev)->nd_seg_const, KA_LOCKED) - -/* Specific mountpoint; head or a checkpoint/snapshot */ -struct nandfsmount { - STAILQ_ENTRY(nandfsmount) nm_next_mount; - - struct mount *nm_vfs_mountp; - struct nandfs_device *nm_nandfsdev; - struct nandfs_args nm_mount_args; - struct nandfs_node *nm_ifile_node; - - uint8_t nm_flags; - int8_t nm_ronly; -}; - -struct nandfs_node { - struct vnode *nn_vnode; - struct nandfsmount *nn_nmp; - struct nandfs_device *nn_nandfsdev; - struct lockf *nn_lockf; - - uint64_t nn_ino; - struct nandfs_inode nn_inode; - - uint64_t nn_diroff; - uint32_t nn_flags; -}; - -#define IN_ACCESS 0x0001 /* Inode access time update request */ -#define IN_CHANGE 0x0002 /* Inode change time update request */ -#define IN_UPDATE 0x0004 /* Inode was written to; update mtime*/ -#define IN_MODIFIED 0x0008 /* node has been modified */ -#define IN_RENAME 0x0010 /* node is being renamed. */ - -/* File permissions. */ -#define IEXEC 0000100 /* Executable. */ -#define IWRITE 0000200 /* Writeable. */ -#define IREAD 0000400 /* Readable. */ -#define ISVTX 0001000 /* Sticky bit. */ -#define ISGID 0002000 /* Set-gid. */ -#define ISUID 0004000 /* Set-uid. */ - -#define PRINT_NODE_FLAGS \ - "\10\1IN_ACCESS\2IN_CHANGE\3IN_UPDATE\4IN_MODIFIED\5IN_RENAME" - -#define NANDFS_GATHER(x) ((x)->b_flags |= B_FS_FLAG1) -#define NANDFS_UNGATHER(x) ((x)->b_flags &= ~B_FS_FLAG1) -#define NANDFS_ISGATHERED(x) ((x)->b_flags & B_FS_FLAG1) - -#endif /* !_FS_NANDFS_NANDFS_H_ */ diff --git a/sys/fs/nandfs/nandfs_alloc.c b/sys/fs/nandfs/nandfs_alloc.c deleted file mode 100644 index 01072741d90..00000000000 --- a/sys/fs/nandfs/nandfs_alloc.c +++ /dev/null @@ -1,365 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2010-2012 Semihalf. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include -#include -#include - -static void -nandfs_get_desc_block_nr(struct nandfs_mdt *mdt, uint64_t desc, - uint64_t *desc_block) -{ - - *desc_block = desc * mdt->blocks_per_desc_block; -} - -static void -nandfs_get_group_block_nr(struct nandfs_mdt *mdt, uint64_t group, - uint64_t *group_block) -{ - uint64_t desc, group_off; - - desc = group / mdt->groups_per_desc_block; - group_off = group % mdt->groups_per_desc_block; - *group_block = desc * mdt->blocks_per_desc_block + - 1 + group_off * mdt->blocks_per_group; -} - -static void -init_desc_block(struct nandfs_mdt *mdt, uint8_t *block_data) -{ - struct nandfs_block_group_desc *desc; - uint32_t i; - - desc = (struct nandfs_block_group_desc *) block_data; - for (i = 0; i < mdt->groups_per_desc_block; i++) - desc[i].bg_nfrees = mdt->entries_per_group; -} - -int -nandfs_find_free_entry(struct nandfs_mdt *mdt, struct nandfs_node *node, - struct nandfs_alloc_request *req) -{ - nandfs_daddr_t desc, group, maxgroup, maxdesc, pos = 0; - nandfs_daddr_t start_group, start_desc; - nandfs_daddr_t desc_block, group_block; - nandfs_daddr_t file_blocks; - struct nandfs_block_group_desc *descriptors; - struct buf *bp, *bp2; - uint32_t *mask, i, mcount, msize; - int error; - - file_blocks = node->nn_inode.i_blocks; - maxgroup = 0x100000000ull / mdt->entries_per_group; - maxdesc = maxgroup / mdt->groups_per_desc_block; - start_group = req->entrynum / mdt->entries_per_group; - start_desc = start_group / mdt->groups_per_desc_block; - - bp = bp2 = NULL; -restart: - for (desc = start_desc; desc < maxdesc; desc++) { - nandfs_get_desc_block_nr(mdt, desc, &desc_block); - - if (bp) - brelse(bp); - if (desc_block < file_blocks) { - error = nandfs_bread(node, desc_block, NOCRED, 0, &bp); - if (error) { - brelse(bp); - return (error); - } - } else { - error = nandfs_bcreate(node, desc_block, NOCRED, 0, - &bp); - if (error) - return (error); - file_blocks++; - init_desc_block(mdt, bp->b_data); - } - - descriptors = (struct nandfs_block_group_desc *) bp->b_data; - for (group = start_group; group < mdt->groups_per_desc_block; - group++) { - if (descriptors[group].bg_nfrees > 0) { - nandfs_get_group_block_nr(mdt, group, - &group_block); - - if (bp2) - brelse(bp2); - if (group_block < file_blocks) { - error = nandfs_bread(node, group_block, - NOCRED, 0, &bp2); - if (error) { - brelse(bp); - return (error); - } - } else { - error = nandfs_bcreate(node, - group_block, NOCRED, 0, &bp2); - if (error) - return (error); - file_blocks++; - } - mask = (uint32_t *)bp2->b_data; - msize = (sizeof(uint32_t) * __CHAR_BIT); - mcount = mdt->entries_per_group / msize; - for (i = 0; i < mcount; i++) { - if (mask[i] == UINT32_MAX) - continue; - - pos = ffs(~mask[i]) - 1; - pos += (msize * i); - pos += (group * mdt->entries_per_group); - pos += desc * group * - mdt->groups_per_desc_block * - mdt->entries_per_group; - goto found; - } - } - } - start_group = 0; - } - - if (start_desc != 0) { - maxdesc = start_desc; - start_desc = 0; - req->entrynum = 0; - goto restart; - } - - return (ENOENT); - -found: - req->entrynum = pos; - req->bp_desc = bp; - req->bp_bitmap = bp2; - DPRINTF(ALLOC, ("%s: desc: %p bitmap: %p entry: %#jx\n", - __func__, req->bp_desc, req->bp_bitmap, (uintmax_t)pos)); - - return (0); -} - -int -nandfs_find_entry(struct nandfs_mdt* mdt, struct nandfs_node *nnode, - struct nandfs_alloc_request *req) -{ - uint64_t dblock, bblock, eblock; - uint32_t offset; - int error; - - nandfs_mdt_trans_blk(mdt, req->entrynum, &dblock, &bblock, &eblock, - &offset); - - error = nandfs_bread(nnode, dblock, NOCRED, 0, &req->bp_desc); - if (error) { - brelse(req->bp_desc); - return (error); - } - - error = nandfs_bread(nnode, bblock, NOCRED, 0, &req->bp_bitmap); - if (error) { - brelse(req->bp_desc); - brelse(req->bp_bitmap); - return (error); - } - - error = nandfs_bread(nnode, eblock, NOCRED, 0, &req->bp_entry); - if (error) { - brelse(req->bp_desc); - brelse(req->bp_bitmap); - brelse(req->bp_entry); - return (error); - } - - DPRINTF(ALLOC, - ("%s: desc_buf: %p bitmap_buf %p entry_buf %p offset %x\n", - __func__, req->bp_desc, req->bp_bitmap, req->bp_entry, offset)); - - return (0); -} - -static __inline void -nandfs_calc_idx_entry(struct nandfs_mdt* mdt, uint32_t entrynum, - uint64_t *group, uint64_t *bitmap_idx, uint64_t *bitmap_off) -{ - - /* Find group_desc index */ - entrynum = entrynum % - (mdt->entries_per_group * mdt->groups_per_desc_block); - *group = entrynum / mdt->entries_per_group; - /* Find bitmap index and bit offset */ - entrynum = entrynum % mdt->entries_per_group; - *bitmap_idx = entrynum / (sizeof(uint32_t) * __CHAR_BIT); - *bitmap_off = entrynum % (sizeof(uint32_t) * __CHAR_BIT); -} - -int -nandfs_free_entry(struct nandfs_mdt* mdt, struct nandfs_alloc_request *req) -{ - struct nandfs_block_group_desc *descriptors; - uint64_t bitmap_idx, bitmap_off; - uint64_t group; - uint32_t *mask, maskrw; - - nandfs_calc_idx_entry(mdt, req->entrynum, &group, &bitmap_idx, - &bitmap_off); - - DPRINTF(ALLOC, ("nandfs_free_entry: req->entrynum=%jx bitmap_idx=%jx" - " bitmap_off=%jx group=%jx\n", (uintmax_t)req->entrynum, - (uintmax_t)bitmap_idx, (uintmax_t)bitmap_off, (uintmax_t)group)); - - /* Update counter of free entries for group */ - descriptors = (struct nandfs_block_group_desc *) req->bp_desc->b_data; - descriptors[group].bg_nfrees++; - - /* Set bit to indicate that entry is taken */ - mask = (uint32_t *)req->bp_bitmap->b_data; - maskrw = mask[bitmap_idx]; - KASSERT(maskrw & (1 << bitmap_off), ("freeing unallocated vblock")); - maskrw &= ~(1 << bitmap_off); - mask[bitmap_idx] = maskrw; - - /* Make descriptor, bitmap and entry buffer dirty */ - if (nandfs_dirty_buf(req->bp_desc, 0) == 0) { - nandfs_dirty_buf(req->bp_bitmap, 1); - nandfs_dirty_buf(req->bp_entry, 1); - } else { - brelse(req->bp_bitmap); - brelse(req->bp_entry); - return (-1); - } - - return (0); -} - -int -nandfs_alloc_entry(struct nandfs_mdt* mdt, struct nandfs_alloc_request *req) -{ - struct nandfs_block_group_desc *descriptors; - uint64_t bitmap_idx, bitmap_off; - uint64_t group; - uint32_t *mask, maskrw; - - nandfs_calc_idx_entry(mdt, req->entrynum, &group, &bitmap_idx, - &bitmap_off); - - DPRINTF(ALLOC, ("nandfs_alloc_entry: req->entrynum=%jx bitmap_idx=%jx" - " bitmap_off=%jx group=%jx\n", (uintmax_t)req->entrynum, - (uintmax_t)bitmap_idx, (uintmax_t)bitmap_off, (uintmax_t)group)); - - /* Update counter of free entries for group */ - descriptors = (struct nandfs_block_group_desc *) req->bp_desc->b_data; - descriptors[group].bg_nfrees--; - - /* Clear bit to indicate that entry is free */ - mask = (uint32_t *)req->bp_bitmap->b_data; - maskrw = mask[bitmap_idx]; - maskrw |= 1 << bitmap_off; - mask[bitmap_idx] = maskrw; - - /* Make descriptor, bitmap and entry buffer dirty */ - if (nandfs_dirty_buf(req->bp_desc, 0) == 0) { - nandfs_dirty_buf(req->bp_bitmap, 1); - nandfs_dirty_buf(req->bp_entry, 1); - } else { - brelse(req->bp_bitmap); - brelse(req->bp_entry); - return (-1); - } - - return (0); -} - -void -nandfs_abort_entry(struct nandfs_alloc_request *req) -{ - - brelse(req->bp_desc); - brelse(req->bp_bitmap); - brelse(req->bp_entry); -} - -int -nandfs_get_entry_block(struct nandfs_mdt *mdt, struct nandfs_node *node, - struct nandfs_alloc_request *req, uint32_t *entry, int create) -{ - struct buf *bp; - nandfs_lbn_t blocknr; - int error; - - /* Find buffer number for given entry */ - nandfs_mdt_trans(mdt, req->entrynum, &blocknr, entry); - DPRINTF(ALLOC, ("%s: ino %#jx entrynum:%#jx block:%#jx entry:%x\n", - __func__, (uintmax_t)node->nn_ino, (uintmax_t)req->entrynum, - (uintmax_t)blocknr, *entry)); - - /* Read entry block or create if 'create' parameter is not zero */ - bp = NULL; - - if (blocknr < node->nn_inode.i_blocks) - error = nandfs_bread(node, blocknr, NOCRED, 0, &bp); - else if (create) - error = nandfs_bcreate(node, blocknr, NOCRED, 0, &bp); - else - error = E2BIG; - - if (error) { - DPRINTF(ALLOC, ("%s: ino %#jx block %#jx entry %x error %d\n", - __func__, (uintmax_t)node->nn_ino, (uintmax_t)blocknr, - *entry, error)); - if (bp) - brelse(bp); - return (error); - } - - MPASS(nandfs_vblk_get(bp) != 0 || node->nn_ino == NANDFS_DAT_INO); - - req->bp_entry = bp; - return (0); -} diff --git a/sys/fs/nandfs/nandfs_bmap.c b/sys/fs/nandfs/nandfs_bmap.c deleted file mode 100644 index d19d6ec63ba..00000000000 --- a/sys/fs/nandfs/nandfs_bmap.c +++ /dev/null @@ -1,231 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2010-2012 Semihalf - * Copyright (c) 2008, 2009 Reinoud Zandijk - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * From: NetBSD: nilfs_subr.c,v 1.4 2009/07/29 17:06:57 reinoud - */ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include - -#include -#include -#include -#include - -#include "nandfs_mount.h" -#include "nandfs.h" -#include "nandfs_subr.h" -#include "bmap.h" - -nandfs_lbn_t -nandfs_get_maxfilesize(struct nandfs_device *fsdev) -{ - - return (get_maxfilesize(fsdev)); -} - -int -nandfs_bmap_lookup(struct nandfs_node *node, nandfs_lbn_t lblk, - nandfs_daddr_t *vblk) -{ - int error = 0; - - if (node->nn_ino == NANDFS_GC_INO && lblk >= 0) - *vblk = lblk; - else - error = bmap_lookup(node, lblk, vblk); - - DPRINTF(TRANSLATE, ("%s: error %d ino %#jx lblocknr %#jx -> %#jx\n", - __func__, error, (uintmax_t)node->nn_ino, (uintmax_t)lblk, - (uintmax_t)*vblk)); - - if (error) - nandfs_error("%s: returned %d", __func__, error); - - return (error); -} - -int -nandfs_bmap_insert_block(struct nandfs_node *node, nandfs_lbn_t lblk, - struct buf *bp) -{ - struct nandfs_device *fsdev; - nandfs_daddr_t vblk; - int error; - - fsdev = node->nn_nandfsdev; - - vblk = 0; - if (node->nn_ino != NANDFS_DAT_INO) { - error = nandfs_vblock_alloc(fsdev, &vblk); - if (error) - return (error); - } - - nandfs_buf_set(bp, NANDFS_VBLK_ASSIGNED); - nandfs_vblk_set(bp, vblk); - - error = bmap_insert_block(node, lblk, vblk); - if (error) { - nandfs_vblock_free(fsdev, vblk); - return (error); - } - - return (0); -} - -int -nandfs_bmap_dirty_blocks(struct nandfs_node *node, struct buf *bp, int force) -{ - int error; - - error = bmap_dirty_meta(node, bp->b_lblkno, force); - if (error) - nandfs_error("%s: cannot dirty buffer %p\n", - __func__, bp); - - return (error); -} - -static int -nandfs_bmap_update_mapping(struct nandfs_node *node, nandfs_lbn_t lblk, - nandfs_daddr_t blknr) -{ - int error; - - DPRINTF(BMAP, - ("%s: node: %p ino: %#jx lblk: %#jx vblk: %#jx\n", - __func__, node, (uintmax_t)node->nn_ino, (uintmax_t)lblk, - (uintmax_t)blknr)); - - error = bmap_insert_block(node, lblk, blknr); - - return (error); -} - -int -nandfs_bmap_update_block(struct nandfs_node *node, struct buf *bp, - nandfs_lbn_t blknr) -{ - nandfs_lbn_t lblk; - int error; - - lblk = bp->b_lblkno; - nandfs_vblk_set(bp, blknr); - - DPRINTF(BMAP, ("%s: node: %p ino: %#jx bp: %p lblk: %#jx blk: %#jx\n", - __func__, node, (uintmax_t)node->nn_ino, bp, - (uintmax_t)lblk, (uintmax_t)blknr)); - - error = nandfs_bmap_update_mapping(node, lblk, blknr); - if (error) { - nandfs_error("%s: cannot update lblk:%jx to blk:%jx for " - "node:%p, error:%d\n", __func__, (uintmax_t)lblk, - (uintmax_t)blknr, node, error); - return (error); - } - - return (error); -} - -int -nandfs_bmap_update_dat(struct nandfs_node *node, nandfs_daddr_t oldblk, - struct buf *bp) -{ - struct nandfs_device *fsdev; - nandfs_daddr_t vblk = 0; - int error; - - if (node->nn_ino == NANDFS_DAT_INO) - return (0); - - if (nandfs_buf_check(bp, NANDFS_VBLK_ASSIGNED)) { - nandfs_buf_clear(bp, NANDFS_VBLK_ASSIGNED); - return (0); - } - - fsdev = node->nn_nandfsdev; - - /* First alloc new virtual block.... */ - error = nandfs_vblock_alloc(fsdev, &vblk); - if (error) - return (error); - - error = nandfs_bmap_update_block(node, bp, vblk); - if (error) - return (error); - - /* Then we can end up with old one */ - nandfs_vblock_end(fsdev, oldblk); - - DPRINTF(BMAP, - ("%s: ino %#jx block %#jx: update vblk %#jx to %#jx\n", - __func__, (uintmax_t)node->nn_ino, (uintmax_t)bp->b_lblkno, - (uintmax_t)oldblk, (uintmax_t)vblk)); - return (error); -} - -int -nandfs_bmap_truncate_mapping(struct nandfs_node *node, nandfs_lbn_t oblk, - nandfs_lbn_t nblk) -{ - nandfs_lbn_t todo; - int error; - - todo = oblk - nblk; - - DPRINTF(BMAP, ("%s: node %p oblk %jx nblk %jx truncate by %jx\n", - __func__, node, oblk, nblk, todo)); - - error = bmap_truncate_mapping(node, oblk, todo); - if (error) - return (error); - - return (error); -} diff --git a/sys/fs/nandfs/nandfs_buffer.c b/sys/fs/nandfs/nandfs_buffer.c deleted file mode 100644 index b5bbde433d7..00000000000 --- a/sys/fs/nandfs/nandfs_buffer.c +++ /dev/null @@ -1,84 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2010-2012 Semihalf. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -struct buf * -nandfs_geteblk(int size, int flags) -{ - struct buf *bp; - - /* - * XXX - * Right now we can call geteblk with GB_NOWAIT_BD flag, which means - * it can return NULL. But we cannot afford to get NULL, hence this panic. - */ - bp = geteblk(size, flags); - if (bp == NULL) - panic("geteblk returned NULL"); - - return (bp); -} - -void -nandfs_dirty_bufs_increment(struct nandfs_device *fsdev) -{ - - mtx_lock(&fsdev->nd_mutex); - KASSERT(fsdev->nd_dirty_bufs >= 0, ("negative nd_dirty_bufs")); - fsdev->nd_dirty_bufs++; - mtx_unlock(&fsdev->nd_mutex); -} - -void -nandfs_dirty_bufs_decrement(struct nandfs_device *fsdev) -{ - - mtx_lock(&fsdev->nd_mutex); - KASSERT(fsdev->nd_dirty_bufs > 0, - ("decrementing not-positive nd_dirty_bufs")); - fsdev->nd_dirty_bufs--; - mtx_unlock(&fsdev->nd_mutex); -} diff --git a/sys/fs/nandfs/nandfs_cleaner.c b/sys/fs/nandfs/nandfs_cleaner.c deleted file mode 100644 index b5783091444..00000000000 --- a/sys/fs/nandfs/nandfs_cleaner.c +++ /dev/null @@ -1,621 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2010-2012 Semihalf. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#define NANDFS_CLEANER_KILL 1 - -static void nandfs_cleaner(struct nandfs_device *); -static int nandfs_cleaner_clean_segments(struct nandfs_device *, - struct nandfs_vinfo *, uint32_t, struct nandfs_period *, uint32_t, - struct nandfs_bdesc *, uint32_t, uint64_t *, uint32_t); - -static int -nandfs_process_bdesc(struct nandfs_device *nffsdev, struct nandfs_bdesc *bd, - uint64_t nmembs); - -static void -nandfs_wakeup_wait_cleaner(struct nandfs_device *fsdev, int reason) -{ - - mtx_lock(&fsdev->nd_clean_mtx); - if (reason == NANDFS_CLEANER_KILL) - fsdev->nd_cleaner_exit = 1; - if (fsdev->nd_cleaning == 0) { - fsdev->nd_cleaning = 1; - wakeup(&fsdev->nd_cleaning); - } - cv_wait(&fsdev->nd_clean_cv, &fsdev->nd_clean_mtx); - mtx_unlock(&fsdev->nd_clean_mtx); -} - -int -nandfs_start_cleaner(struct nandfs_device *fsdev) -{ - int error; - - MPASS(fsdev->nd_cleaner == NULL); - - fsdev->nd_cleaner_exit = 0; - - error = kthread_add((void(*)(void *))nandfs_cleaner, fsdev, NULL, - &fsdev->nd_cleaner, 0, 0, "nandfs_cleaner"); - if (error) - printf("nandfs: could not start cleaner: %d\n", error); - - return (error); -} - -int -nandfs_stop_cleaner(struct nandfs_device *fsdev) -{ - - MPASS(fsdev->nd_cleaner != NULL); - nandfs_wakeup_wait_cleaner(fsdev, NANDFS_CLEANER_KILL); - fsdev->nd_cleaner = NULL; - - DPRINTF(CLEAN, ("cleaner stopped\n")); - return (0); -} - -static int -nandfs_cleaner_finished(struct nandfs_device *fsdev) -{ - int exit; - - mtx_lock(&fsdev->nd_clean_mtx); - fsdev->nd_cleaning = 0; - if (!fsdev->nd_cleaner_exit) { - DPRINTF(CLEAN, ("%s: sleep\n", __func__)); - msleep(&fsdev->nd_cleaning, &fsdev->nd_clean_mtx, PRIBIO, "-", - hz * nandfs_cleaner_interval); - } - exit = fsdev->nd_cleaner_exit; - cv_broadcast(&fsdev->nd_clean_cv); - mtx_unlock(&fsdev->nd_clean_mtx); - if (exit) { - DPRINTF(CLEAN, ("%s: no longer active\n", __func__)); - return (1); - } - - return (0); -} - -static void -print_suinfo(struct nandfs_suinfo *suinfo, int nsegs) -{ - int i; - - for (i = 0; i < nsegs; i++) { - DPRINTF(CLEAN, ("%jx %jd %c%c%c %10u\n", - suinfo[i].nsi_num, suinfo[i].nsi_lastmod, - (suinfo[i].nsi_flags & - (NANDFS_SEGMENT_USAGE_ACTIVE) ? 'a' : '-'), - (suinfo[i].nsi_flags & - (NANDFS_SEGMENT_USAGE_DIRTY) ? 'd' : '-'), - (suinfo[i].nsi_flags & - (NANDFS_SEGMENT_USAGE_ERROR) ? 'e' : '-'), - suinfo[i].nsi_blocks)); - } -} - -static int -nandfs_cleaner_vblock_is_alive(struct nandfs_device *fsdev, - struct nandfs_vinfo *vinfo, struct nandfs_cpinfo *cp, uint32_t ncps) -{ - int64_t idx, min, max; - - if (vinfo->nvi_end >= fsdev->nd_last_cno) - return (1); - - if (ncps == 0) - return (0); - - if (vinfo->nvi_end < cp[0].nci_cno || - vinfo->nvi_start > cp[ncps - 1].nci_cno) - return (0); - - idx = min = 0; - max = ncps - 1; - while (min <= max) { - idx = (min + max) / 2; - if (vinfo->nvi_start == cp[idx].nci_cno) - return (1); - if (vinfo->nvi_start < cp[idx].nci_cno) - max = idx - 1; - else - min = idx + 1; - } - - return (vinfo->nvi_end >= cp[idx].nci_cno); -} - -static void -nandfs_cleaner_vinfo_mark_alive(struct nandfs_device *fsdev, - struct nandfs_vinfo *vinfo, uint32_t nmembs, struct nandfs_cpinfo *cp, - uint32_t ncps) -{ - uint32_t i; - - for (i = 0; i < nmembs; i++) - vinfo[i].nvi_alive = - nandfs_cleaner_vblock_is_alive(fsdev, &vinfo[i], cp, ncps); -} - -static int -nandfs_cleaner_bdesc_is_alive(struct nandfs_device *fsdev, - struct nandfs_bdesc *bdesc) -{ - int alive; - - alive = bdesc->bd_oblocknr == bdesc->bd_blocknr; - if (!alive) - MPASS(abs(bdesc->bd_oblocknr - bdesc->bd_blocknr) > 2); - - return (alive); -} - -static void -nandfs_cleaner_bdesc_mark_alive(struct nandfs_device *fsdev, - struct nandfs_bdesc *bdesc, uint32_t nmembs) -{ - uint32_t i; - - for (i = 0; i < nmembs; i++) - bdesc[i].bd_alive = nandfs_cleaner_bdesc_is_alive(fsdev, - &bdesc[i]); -} - -static void -nandfs_cleaner_iterate_psegment(struct nandfs_device *fsdev, - struct nandfs_segment_summary *segsum, union nandfs_binfo *binfo, - nandfs_daddr_t blk, struct nandfs_vinfo **vipp, struct nandfs_bdesc **bdpp) -{ - int i; - - DPRINTF(CLEAN, ("%s nbinfos %x\n", __func__, segsum->ss_nbinfos)); - for (i = 0; i < segsum->ss_nbinfos; i++) { - if (binfo[i].bi_v.bi_ino == NANDFS_DAT_INO) { - (*bdpp)->bd_oblocknr = blk + segsum->ss_nblocks - - segsum->ss_nbinfos + i; - /* - * XXX Hack - */ - if (segsum->ss_flags & NANDFS_SS_SR) - (*bdpp)->bd_oblocknr--; - (*bdpp)->bd_level = binfo[i].bi_dat.bi_level; - (*bdpp)->bd_offset = binfo[i].bi_dat.bi_blkoff; - (*bdpp)++; - } else { - (*vipp)->nvi_ino = binfo[i].bi_v.bi_ino; - (*vipp)->nvi_vblocknr = binfo[i].bi_v.bi_vblocknr; - (*vipp)++; - } - } -} - -static int -nandfs_cleaner_iterate_segment(struct nandfs_device *fsdev, uint64_t segno, - struct nandfs_vinfo **vipp, struct nandfs_bdesc **bdpp, int *select) -{ - struct nandfs_segment_summary *segsum; - union nandfs_binfo *binfo; - struct buf *bp; - uint32_t nblocks; - nandfs_daddr_t curr, start, end; - int error = 0; - - nandfs_get_segment_range(fsdev, segno, &start, &end); - - DPRINTF(CLEAN, ("%s: segno %jx start %jx end %jx\n", __func__, segno, - start, end)); - - *select = 0; - - for (curr = start; curr < end; curr += nblocks) { - error = nandfs_dev_bread(fsdev, curr, NOCRED, 0, &bp); - if (error) { - brelse(bp); - nandfs_error("%s: couldn't load segment summary of %jx: %d\n", - __func__, segno, error); - return (error); - } - - segsum = (struct nandfs_segment_summary *)bp->b_data; - binfo = (union nandfs_binfo *)(bp->b_data + segsum->ss_bytes); - - if (!nandfs_segsum_valid(segsum)) { - brelse(bp); - nandfs_error("nandfs: invalid summary of segment %jx\n", segno); - return (error); - } - - DPRINTF(CLEAN, ("%s: %jx magic %x bytes %x nblocks %x nbinfos " - "%x\n", __func__, segno, segsum->ss_magic, segsum->ss_bytes, - segsum->ss_nblocks, segsum->ss_nbinfos)); - - nandfs_cleaner_iterate_psegment(fsdev, segsum, binfo, curr, - vipp, bdpp); - nblocks = segsum->ss_nblocks; - brelse(bp); - } - - if (error == 0) - *select = 1; - - return (error); -} - -static int -nandfs_cleaner_choose_segment(struct nandfs_device *fsdev, uint64_t **segpp, - uint64_t nsegs, uint64_t *rseg) -{ - struct nandfs_suinfo *suinfo; - uint64_t i, ssegs; - int error; - - suinfo = malloc(sizeof(*suinfo) * nsegs, M_NANDFSTEMP, - M_ZERO | M_WAITOK); - - if (*rseg >= fsdev->nd_fsdata.f_nsegments) - *rseg = 0; - -retry: - error = nandfs_get_segment_info_filter(fsdev, suinfo, nsegs, *rseg, - &ssegs, NANDFS_SEGMENT_USAGE_DIRTY, - NANDFS_SEGMENT_USAGE_ACTIVE | NANDFS_SEGMENT_USAGE_ERROR | - NANDFS_SEGMENT_USAGE_GC); - if (error) { - nandfs_error("%s:%d", __FILE__, __LINE__); - goto out; - } - if (ssegs == 0 && *rseg != 0) { - *rseg = 0; - goto retry; - } - if (ssegs > 0) { - print_suinfo(suinfo, ssegs); - - for (i = 0; i < ssegs; i++) { - (**segpp) = suinfo[i].nsi_num; - (*segpp)++; - } - *rseg = suinfo[i - 1].nsi_num + 1; - } - -out: - free(suinfo, M_NANDFSTEMP); - return (error); -} - -static int -nandfs_cleaner_body(struct nandfs_device *fsdev, uint64_t *rseg) -{ - struct nandfs_vinfo *vinfo, *vip, *vipi; - struct nandfs_bdesc *bdesc, *bdp, *bdpi; - struct nandfs_cpstat cpstat; - struct nandfs_cpinfo *cpinfo = NULL; - uint64_t *segnums, *segp; - int select, selected; - int error = 0; - int nsegs; - int i; - - nsegs = nandfs_cleaner_segments; - - vip = vinfo = malloc(sizeof(*vinfo) * - fsdev->nd_fsdata.f_blocks_per_segment * nsegs, M_NANDFSTEMP, - M_ZERO | M_WAITOK); - bdp = bdesc = malloc(sizeof(*bdesc) * - fsdev->nd_fsdata.f_blocks_per_segment * nsegs, M_NANDFSTEMP, - M_ZERO | M_WAITOK); - segp = segnums = malloc(sizeof(*segnums) * nsegs, M_NANDFSTEMP, - M_WAITOK); - - error = nandfs_cleaner_choose_segment(fsdev, &segp, nsegs, rseg); - if (error) { - nandfs_error("%s:%d", __FILE__, __LINE__); - goto out; - } - - if (segnums == segp) - goto out; - - selected = 0; - for (i = 0; i < segp - segnums; i++) { - error = nandfs_cleaner_iterate_segment(fsdev, segnums[i], &vip, - &bdp, &select); - if (error) { - /* - * XXX deselect (see below)? - */ - goto out; - } - if (!select) - segnums[i] = NANDFS_NOSEGMENT; - else { - error = nandfs_markgc_segment(fsdev, segnums[i]); - if (error) { - nandfs_error("%s:%d\n", __FILE__, __LINE__); - goto out; - } - selected++; - } - } - - if (selected == 0) { - MPASS(vinfo == vip); - MPASS(bdesc == bdp); - goto out; - } - - error = nandfs_get_cpstat(fsdev->nd_cp_node, &cpstat); - if (error) { - nandfs_error("%s:%d\n", __FILE__, __LINE__); - goto out; - } - - if (cpstat.ncp_nss != 0) { - cpinfo = malloc(sizeof(struct nandfs_cpinfo) * cpstat.ncp_nss, - M_NANDFSTEMP, M_WAITOK); - error = nandfs_get_cpinfo(fsdev->nd_cp_node, 1, NANDFS_SNAPSHOT, - cpinfo, cpstat.ncp_nss, NULL); - if (error) { - nandfs_error("%s:%d\n", __FILE__, __LINE__); - goto out_locked; - } - } - - NANDFS_WRITELOCK(fsdev); - DPRINTF(CLEAN, ("%s: got lock\n", __func__)); - - error = nandfs_get_dat_vinfo(fsdev, vinfo, vip - vinfo); - if (error) { - nandfs_error("%s:%d\n", __FILE__, __LINE__); - goto out_locked; - } - - nandfs_cleaner_vinfo_mark_alive(fsdev, vinfo, vip - vinfo, cpinfo, - cpstat.ncp_nss); - - error = nandfs_get_dat_bdescs(fsdev, bdesc, bdp - bdesc); - if (error) { - nandfs_error("%s:%d\n", __FILE__, __LINE__); - goto out_locked; - } - - nandfs_cleaner_bdesc_mark_alive(fsdev, bdesc, bdp - bdesc); - - DPRINTF(CLEAN, ("got:\n")); - for (vipi = vinfo; vipi < vip; vipi++) { - DPRINTF(CLEAN, ("v ino %jx vblocknr %jx start %jx end %jx " - "alive %d\n", vipi->nvi_ino, vipi->nvi_vblocknr, - vipi->nvi_start, vipi->nvi_end, vipi->nvi_alive)); - } - for (bdpi = bdesc; bdpi < bdp; bdpi++) { - DPRINTF(CLEAN, ("b oblocknr %jx blocknr %jx offset %jx " - "alive %d\n", bdpi->bd_oblocknr, bdpi->bd_blocknr, - bdpi->bd_offset, bdpi->bd_alive)); - } - DPRINTF(CLEAN, ("end list\n")); - - error = nandfs_cleaner_clean_segments(fsdev, vinfo, vip - vinfo, NULL, - 0, bdesc, bdp - bdesc, segnums, segp - segnums); - if (error) - nandfs_error("%s:%d\n", __FILE__, __LINE__); - -out_locked: - NANDFS_WRITEUNLOCK(fsdev); -out: - free(cpinfo, M_NANDFSTEMP); - free(segnums, M_NANDFSTEMP); - free(bdesc, M_NANDFSTEMP); - free(vinfo, M_NANDFSTEMP); - - return (error); -} - -static void -nandfs_cleaner(struct nandfs_device *fsdev) -{ - uint64_t checked_seg = 0; - int error; - - while (!nandfs_cleaner_finished(fsdev)) { - if (!nandfs_cleaner_enable || rebooting) - continue; - - DPRINTF(CLEAN, ("%s: run started\n", __func__)); - - fsdev->nd_cleaning = 1; - - error = nandfs_cleaner_body(fsdev, &checked_seg); - - DPRINTF(CLEAN, ("%s: run finished error %d\n", __func__, - error)); - } - - DPRINTF(CLEAN, ("%s: exiting\n", __func__)); - kthread_exit(); -} - -static int -nandfs_cleaner_clean_segments(struct nandfs_device *nffsdev, - struct nandfs_vinfo *vinfo, uint32_t nvinfo, - struct nandfs_period *pd, uint32_t npd, - struct nandfs_bdesc *bdesc, uint32_t nbdesc, - uint64_t *segments, uint32_t nsegs) -{ - struct nandfs_node *gc; - struct buf *bp; - uint32_t i; - int error = 0; - - gc = nffsdev->nd_gc_node; - - DPRINTF(CLEAN, ("%s: enter\n", __func__)); - - VOP_LOCK(NTOV(gc), LK_EXCLUSIVE); - for (i = 0; i < nvinfo; i++) { - if (!vinfo[i].nvi_alive) - continue; - DPRINTF(CLEAN, ("%s: read vblknr:%#jx blk:%#jx\n", - __func__, (uintmax_t)vinfo[i].nvi_vblocknr, - (uintmax_t)vinfo[i].nvi_blocknr)); - error = nandfs_bread(nffsdev->nd_gc_node, vinfo[i].nvi_blocknr, - NULL, 0, &bp); - if (error) { - nandfs_error("%s:%d", __FILE__, __LINE__); - VOP_UNLOCK(NTOV(gc), 0); - goto out; - } - nandfs_vblk_set(bp, vinfo[i].nvi_vblocknr); - nandfs_buf_set(bp, NANDFS_VBLK_ASSIGNED); - nandfs_dirty_buf(bp, 1); - } - VOP_UNLOCK(NTOV(gc), 0); - - /* Delete checkpoints */ - for (i = 0; i < npd; i++) { - DPRINTF(CLEAN, ("delete checkpoint: %jx\n", - (uintmax_t)pd[i].p_start)); - error = nandfs_delete_cp(nffsdev->nd_cp_node, pd[i].p_start, - pd[i].p_end); - if (error) { - nandfs_error("%s:%d", __FILE__, __LINE__); - goto out; - } - } - - /* Update vblocks */ - for (i = 0; i < nvinfo; i++) { - if (vinfo[i].nvi_alive) - continue; - DPRINTF(CLEAN, ("freeing vblknr: %jx\n", vinfo[i].nvi_vblocknr)); - error = nandfs_vblock_free(nffsdev, vinfo[i].nvi_vblocknr); - if (error) { - nandfs_error("%s:%d", __FILE__, __LINE__); - goto out; - } - } - - error = nandfs_process_bdesc(nffsdev, bdesc, nbdesc); - if (error) { - nandfs_error("%s:%d", __FILE__, __LINE__); - goto out; - } - - /* Add segments to clean */ - if (nffsdev->nd_free_count) { - nffsdev->nd_free_base = realloc(nffsdev->nd_free_base, - (nffsdev->nd_free_count + nsegs) * sizeof(uint64_t), - M_NANDFSTEMP, M_WAITOK | M_ZERO); - memcpy(&nffsdev->nd_free_base[nffsdev->nd_free_count], segments, - nsegs * sizeof(uint64_t)); - nffsdev->nd_free_count += nsegs; - } else { - nffsdev->nd_free_base = malloc(nsegs * sizeof(uint64_t), - M_NANDFSTEMP, M_WAITOK|M_ZERO); - memcpy(nffsdev->nd_free_base, segments, - nsegs * sizeof(uint64_t)); - nffsdev->nd_free_count = nsegs; - } - -out: - - DPRINTF(CLEAN, ("%s: exit error %d\n", __func__, error)); - - return (error); -} - -static int -nandfs_process_bdesc(struct nandfs_device *nffsdev, struct nandfs_bdesc *bd, - uint64_t nmembs) -{ - struct nandfs_node *dat_node; - struct buf *bp; - uint64_t i; - int error; - - dat_node = nffsdev->nd_dat_node; - - VOP_LOCK(NTOV(dat_node), LK_EXCLUSIVE); - - for (i = 0; i < nmembs; i++) { - if (!bd[i].bd_alive) - continue; - DPRINTF(CLEAN, ("%s: idx %jx offset %jx\n", - __func__, i, bd[i].bd_offset)); - if (bd[i].bd_level) { - error = nandfs_bread_meta(dat_node, bd[i].bd_offset, - NULL, 0, &bp); - if (error) { - nandfs_error("%s: cannot read dat node " - "level:%d\n", __func__, bd[i].bd_level); - brelse(bp); - VOP_UNLOCK(NTOV(dat_node), 0); - return (error); - } - nandfs_dirty_buf_meta(bp, 1); - nandfs_bmap_dirty_blocks(VTON(bp->b_vp), bp, 1); - } else { - error = nandfs_bread(dat_node, bd[i].bd_offset, NULL, - 0, &bp); - if (error) { - nandfs_error("%s: cannot read dat node\n", - __func__); - brelse(bp); - VOP_UNLOCK(NTOV(dat_node), 0); - return (error); - } - nandfs_dirty_buf(bp, 1); - } - DPRINTF(CLEAN, ("%s: bp: %p\n", __func__, bp)); - } - - VOP_UNLOCK(NTOV(dat_node), 0); - - return (0); -} diff --git a/sys/fs/nandfs/nandfs_cpfile.c b/sys/fs/nandfs/nandfs_cpfile.c deleted file mode 100644 index 6cfdb687605..00000000000 --- a/sys/fs/nandfs/nandfs_cpfile.c +++ /dev/null @@ -1,777 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2010-2012 Semihalf. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include "nandfs_mount.h" -#include "nandfs.h" -#include "nandfs_subr.h" - - -static int -nandfs_checkpoint_size(struct nandfs_device *fsdev) -{ - - return (fsdev->nd_fsdata.f_checkpoint_size); -} - -static int -nandfs_checkpoint_blk_offset(struct nandfs_device *fsdev, uint64_t cn, - uint64_t *blk, uint64_t *offset) -{ - uint64_t off; - uint16_t cp_size, cp_per_blk; - - KASSERT((cn), ("checkpoing cannot be zero")); - - cp_size = fsdev->nd_fsdata.f_checkpoint_size; - cp_per_blk = fsdev->nd_blocksize / cp_size; - off = roundup(sizeof(struct nandfs_cpfile_header), cp_size) / cp_size; - off += (cn - 1); - - *blk = off / cp_per_blk; - *offset = (off % cp_per_blk) * cp_size; - - return (0); -} - -static int -nandfs_checkpoint_blk_remaining(struct nandfs_device *fsdev, uint64_t cn, - uint64_t blk, uint64_t offset) -{ - uint16_t cp_size, cp_remaining; - - cp_size = fsdev->nd_fsdata.f_checkpoint_size; - cp_remaining = (fsdev->nd_blocksize - offset) / cp_size; - - return (cp_remaining); -} - -int -nandfs_get_checkpoint(struct nandfs_device *fsdev, struct nandfs_node *cp_node, - uint64_t cn) -{ - struct buf *bp; - uint64_t blk, offset; - int error; - - if (cn != fsdev->nd_last_cno && cn != (fsdev->nd_last_cno + 1)) { - return (-1); - } - - error = nandfs_bread(cp_node, 0, NOCRED, 0, &bp); - if (error) { - brelse(bp); - return (-1); - } - - error = nandfs_dirty_buf(bp, 0); - if (error) - return (-1); - - - nandfs_checkpoint_blk_offset(fsdev, cn, &blk, &offset); - - if (blk != 0) { - if (blk < cp_node->nn_inode.i_blocks) - error = nandfs_bread(cp_node, blk, NOCRED, 0, &bp); - else - error = nandfs_bcreate(cp_node, blk, NOCRED, 0, &bp); - if (error) { - if (bp) - brelse(bp); - return (-1); - } - - nandfs_dirty_buf(bp, 1); - } - - DPRINTF(CPFILE, ("%s: cn:%#jx entry block:%#jx offset:%#jx\n", - __func__, (uintmax_t)cn, (uintmax_t)blk, (uintmax_t)offset)); - - return (0); -} - -int -nandfs_set_checkpoint(struct nandfs_device *fsdev, struct nandfs_node *cp_node, - uint64_t cn, struct nandfs_inode *ifile_inode, uint64_t nblocks) -{ - struct nandfs_cpfile_header *cnh; - struct nandfs_checkpoint *cnp; - struct buf *bp; - uint64_t blk, offset; - int error; - - if (cn != fsdev->nd_last_cno && cn != (fsdev->nd_last_cno + 1)) { - nandfs_error("%s: trying to set invalid chekpoint %jx - %jx\n", - __func__, cn, fsdev->nd_last_cno); - return (-1); - } - - error = nandfs_bread(cp_node, 0, NOCRED, 0, &bp); - if (error) { - brelse(bp); - return error; - } - - cnh = (struct nandfs_cpfile_header *) bp->b_data; - cnh->ch_ncheckpoints++; - - nandfs_checkpoint_blk_offset(fsdev, cn, &blk, &offset); - - if(blk != 0) { - brelse(bp); - error = nandfs_bread(cp_node, blk, NOCRED, 0, &bp); - if (error) { - brelse(bp); - return error; - } - } - - cnp = (struct nandfs_checkpoint *)((uint8_t *)bp->b_data + offset); - cnp->cp_flags = 0; - cnp->cp_checkpoints_count = 1; - memset(&cnp->cp_snapshot_list, 0, sizeof(struct nandfs_snapshot_list)); - cnp->cp_cno = cn; - cnp->cp_create = fsdev->nd_ts.tv_sec; - cnp->cp_nblk_inc = nblocks; - cnp->cp_blocks_count = 0; - memcpy (&cnp->cp_ifile_inode, ifile_inode, sizeof(cnp->cp_ifile_inode)); - - DPRINTF(CPFILE, ("%s: cn:%#jx ctime:%#jx nblk:%#jx\n", - __func__, (uintmax_t)cn, (uintmax_t)cnp->cp_create, - (uintmax_t)nblocks)); - - brelse(bp); - return (0); -} - -static int -nandfs_cp_mounted(struct nandfs_device *nandfsdev, uint64_t cno) -{ - struct nandfsmount *nmp; - int mounted = 0; - - mtx_lock(&nandfsdev->nd_mutex); - /* No double-mounting of the same checkpoint */ - STAILQ_FOREACH(nmp, &nandfsdev->nd_mounts, nm_next_mount) { - if (nmp->nm_mount_args.cpno == cno) { - mounted = 1; - break; - } - } - mtx_unlock(&nandfsdev->nd_mutex); - - return (mounted); -} - -static int -nandfs_cp_set_snapshot(struct nandfs_node *cp_node, uint64_t cno) -{ - struct nandfs_device *fsdev; - struct nandfs_cpfile_header *cnh; - struct nandfs_checkpoint *cnp; - struct nandfs_snapshot_list *list; - struct buf *bp; - uint64_t blk, prev_blk, offset; - uint64_t curr, prev; - int error; - - fsdev = cp_node->nn_nandfsdev; - - /* Get snapshot data */ - nandfs_checkpoint_blk_offset(fsdev, cno, &blk, &offset); - error = nandfs_bread(cp_node, blk, NOCRED, 0, &bp); - if (error) { - brelse(bp); - return (error); - } - cnp = (struct nandfs_checkpoint *)(bp->b_data + offset); - if (cnp->cp_flags & NANDFS_CHECKPOINT_INVALID) { - brelse(bp); - return (ENOENT); - } - if ((cnp->cp_flags & NANDFS_CHECKPOINT_SNAPSHOT)) { - brelse(bp); - return (EINVAL); - } - - brelse(bp); - /* Get list from header */ - error = nandfs_bread(cp_node, 0, NOCRED, 0, &bp); - if (error) { - brelse(bp); - return (error); - } - - cnh = (struct nandfs_cpfile_header *) bp->b_data; - list = &cnh->ch_snapshot_list; - prev = list->ssl_prev; - brelse(bp); - prev_blk = ~(0); - curr = 0; - while (prev > cno) { - curr = prev; - nandfs_checkpoint_blk_offset(fsdev, prev, &prev_blk, &offset); - error = nandfs_bread(cp_node, prev_blk, NOCRED, 0, &bp); - if (error) { - brelse(bp); - return (error); - } - cnp = (struct nandfs_checkpoint *)(bp->b_data + offset); - list = &cnp->cp_snapshot_list; - prev = list->ssl_prev; - brelse(bp); - } - - if (curr == 0) { - nandfs_bread(cp_node, 0, NOCRED, 0, &bp); - cnh = (struct nandfs_cpfile_header *) bp->b_data; - list = &cnh->ch_snapshot_list; - } else { - nandfs_checkpoint_blk_offset(fsdev, curr, &blk, &offset); - error = nandfs_bread(cp_node, blk, NOCRED, 0, &bp); - if (error) { - brelse(bp); - return (error); - } - cnp = (struct nandfs_checkpoint *)(bp->b_data + offset); - list = &cnp->cp_snapshot_list; - } - - list->ssl_prev = cno; - error = nandfs_dirty_buf(bp, 0); - if (error) - return (error); - - - /* Update snapshot for cno */ - nandfs_checkpoint_blk_offset(fsdev, cno, &blk, &offset); - error = nandfs_bread(cp_node, blk, NOCRED, 0, &bp); - if (error) { - brelse(bp); - return (error); - } - cnp = (struct nandfs_checkpoint *)(bp->b_data + offset); - list = &cnp->cp_snapshot_list; - list->ssl_prev = prev; - list->ssl_next = curr; - cnp->cp_flags |= NANDFS_CHECKPOINT_SNAPSHOT; - nandfs_dirty_buf(bp, 1); - - if (prev == 0) { - nandfs_bread(cp_node, 0, NOCRED, 0, &bp); - cnh = (struct nandfs_cpfile_header *) bp->b_data; - list = &cnh->ch_snapshot_list; - } else { - /* Update snapshot list for prev */ - nandfs_checkpoint_blk_offset(fsdev, prev, &blk, &offset); - error = nandfs_bread(cp_node, blk, NOCRED, 0, &bp); - if (error) { - brelse(bp); - return (error); - } - cnp = (struct nandfs_checkpoint *)(bp->b_data + offset); - list = &cnp->cp_snapshot_list; - } - list->ssl_next = cno; - nandfs_dirty_buf(bp, 1); - - /* Update header */ - error = nandfs_bread(cp_node, 0, NOCRED, 0, &bp); - if (error) { - brelse(bp); - return (error); - } - cnh = (struct nandfs_cpfile_header *) bp->b_data; - cnh->ch_nsnapshots++; - nandfs_dirty_buf(bp, 1); - - return (0); -} - -static int -nandfs_cp_clr_snapshot(struct nandfs_node *cp_node, uint64_t cno) -{ - struct nandfs_device *fsdev; - struct nandfs_cpfile_header *cnh; - struct nandfs_checkpoint *cnp; - struct nandfs_snapshot_list *list; - struct buf *bp; - uint64_t blk, offset, snapshot_cnt; - uint64_t next, prev; - int error; - - fsdev = cp_node->nn_nandfsdev; - - /* Get snapshot data */ - nandfs_checkpoint_blk_offset(fsdev, cno, &blk, &offset); - error = nandfs_bread(cp_node, blk, NOCRED, 0, &bp); - if (error) { - brelse(bp); - return (error); - } - cnp = (struct nandfs_checkpoint *)(bp->b_data + offset); - if (cnp->cp_flags & NANDFS_CHECKPOINT_INVALID) { - brelse(bp); - return (ENOENT); - } - if (!(cnp->cp_flags & NANDFS_CHECKPOINT_SNAPSHOT)) { - brelse(bp); - return (EINVAL); - } - - list = &cnp->cp_snapshot_list; - next = list->ssl_next; - prev = list->ssl_prev; - brelse(bp); - - /* Get previous snapshot */ - if (prev != 0) { - nandfs_checkpoint_blk_offset(fsdev, prev, &blk, &offset); - error = nandfs_bread(cp_node, blk, NOCRED, 0, &bp); - if (error) { - brelse(bp); - return (error); - } - cnp = (struct nandfs_checkpoint *)(bp->b_data + offset); - list = &cnp->cp_snapshot_list; - } else { - nandfs_bread(cp_node, 0, NOCRED, 0, &bp); - cnh = (struct nandfs_cpfile_header *) bp->b_data; - list = &cnh->ch_snapshot_list; - } - - list->ssl_next = next; - error = nandfs_dirty_buf(bp, 0); - if (error) - return (error); - - /* Get next snapshot */ - if (next != 0) { - nandfs_checkpoint_blk_offset(fsdev, next, &blk, &offset); - error = nandfs_bread(cp_node, blk, NOCRED, 0, &bp); - if (error) { - brelse(bp); - return (error); - } - cnp = (struct nandfs_checkpoint *)(bp->b_data + offset); - list = &cnp->cp_snapshot_list; - } else { - nandfs_bread(cp_node, 0, NOCRED, 0, &bp); - cnh = (struct nandfs_cpfile_header *) bp->b_data; - list = &cnh->ch_snapshot_list; - } - list->ssl_prev = prev; - nandfs_dirty_buf(bp, 1); - - /* Update snapshot list for cno */ - nandfs_checkpoint_blk_offset(fsdev, cno, &blk, &offset); - error = nandfs_bread(cp_node, blk, NOCRED, 0, &bp); - if (error) { - brelse(bp); - return (error); - } - cnp = (struct nandfs_checkpoint *)(bp->b_data + offset); - list = &cnp->cp_snapshot_list; - list->ssl_prev = 0; - list->ssl_next = 0; - cnp->cp_flags &= !NANDFS_CHECKPOINT_SNAPSHOT; - nandfs_dirty_buf(bp, 1); - - /* Update header */ - error = nandfs_bread(cp_node, 0, NOCRED, 0, &bp); - if (error) { - brelse(bp); - return (error); - } - cnh = (struct nandfs_cpfile_header *) bp->b_data; - snapshot_cnt = cnh->ch_nsnapshots; - snapshot_cnt--; - cnh->ch_nsnapshots = snapshot_cnt; - nandfs_dirty_buf(bp, 1); - - return (0); -} - -int -nandfs_chng_cpmode(struct nandfs_node *node, struct nandfs_cpmode *ncpm) -{ - struct nandfs_device *fsdev; - uint64_t cno = ncpm->ncpm_cno; - int mode = ncpm->ncpm_mode; - int ret; - - fsdev = node->nn_nandfsdev; - VOP_LOCK(NTOV(node), LK_EXCLUSIVE); - switch (mode) { - case NANDFS_CHECKPOINT: - if (nandfs_cp_mounted(fsdev, cno)) { - ret = EBUSY; - } else - ret = nandfs_cp_clr_snapshot(node, cno); - break; - case NANDFS_SNAPSHOT: - ret = nandfs_cp_set_snapshot(node, cno); - break; - default: - ret = EINVAL; - break; - } - VOP_UNLOCK(NTOV(node), 0); - - return (ret); -} - -static void -nandfs_cpinfo_fill(struct nandfs_checkpoint *cnp, struct nandfs_cpinfo *nci) -{ - - nci->nci_flags = cnp->cp_flags; - nci->nci_pad = 0; - nci->nci_cno = cnp->cp_cno; - nci->nci_create = cnp->cp_create; - nci->nci_nblk_inc = cnp->cp_nblk_inc; - nci->nci_blocks_count = cnp->cp_blocks_count; - nci->nci_next = cnp->cp_snapshot_list.ssl_next; - DPRINTF(CPFILE, ("%s: cn:%#jx ctime:%#jx\n", - __func__, (uintmax_t)cnp->cp_cno, - (uintmax_t)cnp->cp_create)); -} - -static int -nandfs_get_cpinfo_cp(struct nandfs_node *node, uint64_t cno, - struct nandfs_cpinfo *nci, uint32_t mnmembs, uint32_t *nmembs) -{ - struct nandfs_device *fsdev; - struct buf *bp; - uint64_t blk, offset, last_cno, i; - uint16_t remaining; - int error; -#ifdef INVARIANTS - uint64_t testblk, testoffset; -#endif - - if (cno == 0) { - return (ENOENT); - } - - if (mnmembs < 1) { - return (EINVAL); - } - - fsdev = node->nn_nandfsdev; - last_cno = fsdev->nd_last_cno; - DPRINTF(CPFILE, ("%s: cno:%#jx mnmembs: %#jx last:%#jx\n", __func__, - (uintmax_t)cno, (uintmax_t)mnmembs, - (uintmax_t)fsdev->nd_last_cno)); - - /* - * do { - * get block - * read checkpoints until we hit last checkpoint, end of block or - * requested number - * } while (last read checkpoint <= last checkpoint on fs && - * read checkpoints < request number); - */ - *nmembs = i = 0; - do { - nandfs_checkpoint_blk_offset(fsdev, cno, &blk, &offset); - remaining = nandfs_checkpoint_blk_remaining(fsdev, cno, - blk, offset); - error = nandfs_bread(node, blk, NOCRED, 0, &bp); - if (error) { - brelse(bp); - return (error); - } - - while (cno <= last_cno && i < mnmembs && remaining) { -#ifdef INVARIANTS - nandfs_checkpoint_blk_offset(fsdev, cno, &testblk, - &testoffset); - KASSERT(testblk == blk, ("testblk != blk")); - KASSERT(testoffset == offset, ("testoffset != offset")); -#endif - DPRINTF(CPFILE, ("%s: cno %#jx\n", __func__, - (uintmax_t)cno)); - - nandfs_cpinfo_fill((struct nandfs_checkpoint *) - (bp->b_data + offset), nci); - offset += nandfs_checkpoint_size(fsdev); - i++; - nci++; - cno++; - (*nmembs)++; - remaining--; - } - brelse(bp); - } while (cno <= last_cno && i < mnmembs); - - return (0); -} - -static int -nandfs_get_cpinfo_sp(struct nandfs_node *node, uint64_t cno, - struct nandfs_cpinfo *nci, uint32_t mnmembs, uint32_t *nmembs) -{ - struct nandfs_checkpoint *cnp; - struct nandfs_cpfile_header *cnh; - struct nandfs_device *fsdev; - struct buf *bp = NULL; - uint64_t curr = 0; - uint64_t blk, offset, curr_cno; - uint32_t flag; - int i, error; - - if (cno == 0 || cno == ~(0)) - return (ENOENT); - - fsdev = node->nn_nandfsdev; - curr_cno = cno; - - if (nmembs) - *nmembs = 0; - if (curr_cno == 1) { - /* Get list from header */ - error = nandfs_bread(node, 0, NOCRED, 0, &bp); - if (error) { - brelse(bp); - return (error); - } - cnh = (struct nandfs_cpfile_header *) bp->b_data; - curr_cno = cnh->ch_snapshot_list.ssl_next; - brelse(bp); - bp = NULL; - - /* No snapshots */ - if (curr_cno == 0) - return (0); - } - - for (i = 0; i < mnmembs; i++, nci++) { - nandfs_checkpoint_blk_offset(fsdev, curr_cno, &blk, &offset); - if (i == 0 || curr != blk) { - if (bp) - brelse(bp); - error = nandfs_bread(node, blk, NOCRED, 0, &bp); - if (error) { - brelse(bp); - return (ENOENT); - } - curr = blk; - } - cnp = (struct nandfs_checkpoint *)(bp->b_data + offset); - flag = cnp->cp_flags; - if (!(flag & NANDFS_CHECKPOINT_SNAPSHOT) || - (flag & NANDFS_CHECKPOINT_INVALID)) - break; - - nci->nci_flags = flag; - nci->nci_pad = 0; - nci->nci_cno = cnp->cp_cno; - nci->nci_create = cnp->cp_create; - nci->nci_nblk_inc = cnp->cp_nblk_inc; - nci->nci_blocks_count = cnp->cp_blocks_count; - nci->nci_next = cnp->cp_snapshot_list.ssl_next; - if (nmembs) - (*nmembs)++; - - curr_cno = nci->nci_next; - if (!curr_cno) - break; - } - - brelse(bp); - - return (0); -} - -int -nandfs_get_cpinfo(struct nandfs_node *node, uint64_t cno, uint16_t flags, - struct nandfs_cpinfo *nci, uint32_t nmembs, uint32_t *nnmembs) -{ - int error; - - VOP_LOCK(NTOV(node), LK_EXCLUSIVE); - switch (flags) { - case NANDFS_CHECKPOINT: - error = nandfs_get_cpinfo_cp(node, cno, nci, nmembs, nnmembs); - break; - case NANDFS_SNAPSHOT: - error = nandfs_get_cpinfo_sp(node, cno, nci, nmembs, nnmembs); - break; - default: - error = EINVAL; - break; - } - VOP_UNLOCK(NTOV(node), 0); - - return (error); -} - -int -nandfs_get_cpinfo_ioctl(struct nandfs_node *node, struct nandfs_argv *nargv) -{ - struct nandfs_cpinfo *nci; - uint64_t cno = nargv->nv_index; - void *buf = (void *)((uintptr_t)nargv->nv_base); - uint16_t flags = nargv->nv_flags; - uint32_t nmembs = 0; - int error; - - if (nargv->nv_nmembs > NANDFS_CPINFO_MAX) - return (EINVAL); - - nci = malloc(sizeof(struct nandfs_cpinfo) * nargv->nv_nmembs, - M_NANDFSTEMP, M_WAITOK | M_ZERO); - - error = nandfs_get_cpinfo(node, cno, flags, nci, nargv->nv_nmembs, &nmembs); - - if (error == 0) { - nargv->nv_nmembs = nmembs; - error = copyout(nci, buf, - sizeof(struct nandfs_cpinfo) * nmembs); - } - - free(nci, M_NANDFSTEMP); - return (error); -} - -int -nandfs_delete_cp(struct nandfs_node *node, uint64_t start, uint64_t end) -{ - struct nandfs_checkpoint *cnp; - struct nandfs_device *fsdev; - struct buf *bp; - uint64_t cno = start, blk, offset; - int error; - - DPRINTF(CPFILE, ("%s: delete cno %jx-%jx\n", __func__, start, end)); - VOP_LOCK(NTOV(node), LK_EXCLUSIVE); - fsdev = node->nn_nandfsdev; - for (cno = start; cno <= end; cno++) { - if (!cno) - continue; - - nandfs_checkpoint_blk_offset(fsdev, cno, &blk, &offset); - error = nandfs_bread(node, blk, NOCRED, 0, &bp); - if (error) { - VOP_UNLOCK(NTOV(node), 0); - brelse(bp); - return (error); - } - - cnp = (struct nandfs_checkpoint *)(bp->b_data + offset); - if (cnp->cp_flags & NANDFS_CHECKPOINT_SNAPSHOT) { - brelse(bp); - VOP_UNLOCK(NTOV(node), 0); - return (0); - } - - cnp->cp_flags |= NANDFS_CHECKPOINT_INVALID; - - error = nandfs_dirty_buf(bp, 0); - if (error) - return (error); - } - VOP_UNLOCK(NTOV(node), 0); - - return (0); -} - -int -nandfs_make_snap(struct nandfs_device *fsdev, uint64_t *cno) -{ - struct nandfs_cpmode cpm; - int error; - - *cno = cpm.ncpm_cno = fsdev->nd_last_cno; - cpm.ncpm_mode = NANDFS_SNAPSHOT; - error = nandfs_chng_cpmode(fsdev->nd_cp_node, &cpm); - return (error); -} - -int -nandfs_delete_snap(struct nandfs_device *fsdev, uint64_t cno) -{ - struct nandfs_cpmode cpm; - int error; - - cpm.ncpm_cno = cno; - cpm.ncpm_mode = NANDFS_CHECKPOINT; - error = nandfs_chng_cpmode(fsdev->nd_cp_node, &cpm); - return (error); -} - -int nandfs_get_cpstat(struct nandfs_node *cp_node, struct nandfs_cpstat *ncp) -{ - struct nandfs_device *fsdev; - struct nandfs_cpfile_header *cnh; - struct buf *bp; - int error; - - VOP_LOCK(NTOV(cp_node), LK_EXCLUSIVE); - fsdev = cp_node->nn_nandfsdev; - - /* Get header */ - error = nandfs_bread(cp_node, 0, NOCRED, 0, &bp); - if (error) { - brelse(bp); - VOP_UNLOCK(NTOV(cp_node), 0); - return (error); - } - cnh = (struct nandfs_cpfile_header *) bp->b_data; - ncp->ncp_cno = fsdev->nd_last_cno; - ncp->ncp_ncps = cnh->ch_ncheckpoints; - ncp->ncp_nss = cnh->ch_nsnapshots; - DPRINTF(CPFILE, ("%s: cno:%#jx ncps:%#jx nss:%#jx\n", - __func__, ncp->ncp_cno, ncp->ncp_ncps, ncp->ncp_nss)); - brelse(bp); - VOP_UNLOCK(NTOV(cp_node), 0); - - return (0); -} diff --git a/sys/fs/nandfs/nandfs_dat.c b/sys/fs/nandfs/nandfs_dat.c deleted file mode 100644 index b120d130648..00000000000 --- a/sys/fs/nandfs/nandfs_dat.c +++ /dev/null @@ -1,349 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2010-2012 Semihalf. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include -#include -#include - -int -nandfs_vblock_alloc(struct nandfs_device *nandfsdev, nandfs_daddr_t *vblock) -{ - struct nandfs_node *dat; - struct nandfs_mdt *mdt; - struct nandfs_alloc_request req; - struct nandfs_dat_entry *dat_entry; - uint64_t start; - uint32_t entry; - int locked, error; - - dat = nandfsdev->nd_dat_node; - mdt = &nandfsdev->nd_dat_mdt; - start = nandfsdev->nd_last_cno + 1; - - locked = NANDFS_VOP_ISLOCKED(NTOV(dat)); - if (!locked) - VOP_LOCK(NTOV(dat), LK_EXCLUSIVE); - req.entrynum = 0; - - /* Alloc vblock number */ - error = nandfs_find_free_entry(mdt, dat, &req); - if (error) { - nandfs_error("%s: cannot find free vblk entry\n", - __func__); - if (!locked) - VOP_UNLOCK(NTOV(dat), 0); - return (error); - } - - /* Read/create buffer */ - error = nandfs_get_entry_block(mdt, dat, &req, &entry, 1); - if (error) { - nandfs_error("%s: cannot get free vblk entry\n", - __func__); - nandfs_abort_entry(&req); - if (!locked) - VOP_UNLOCK(NTOV(dat), 0); - return (error); - } - - /* Fill out vblock data */ - dat_entry = (struct nandfs_dat_entry *) req.bp_entry->b_data; - dat_entry[entry].de_start = start; - dat_entry[entry].de_end = UINTMAX_MAX; - dat_entry[entry].de_blocknr = 0; - - /* Commit allocation */ - error = nandfs_alloc_entry(mdt, &req); - if (error) { - nandfs_error("%s: cannot get free vblk entry\n", - __func__); - if (!locked) - VOP_UNLOCK(NTOV(dat), 0); - return (error); - } - - /* Return allocated vblock */ - *vblock = req.entrynum; - DPRINTF(DAT, ("%s: allocated vblock %#jx\n", - __func__, (uintmax_t)*vblock)); - - if (!locked) - VOP_UNLOCK(NTOV(dat), 0); - return (error); -} - -int -nandfs_vblock_assign(struct nandfs_device *nandfsdev, nandfs_daddr_t vblock, - nandfs_lbn_t block) -{ - struct nandfs_node *dat; - struct nandfs_mdt *mdt; - struct nandfs_alloc_request req; - struct nandfs_dat_entry *dat_entry; - uint32_t entry; - int locked, error; - - dat = nandfsdev->nd_dat_node; - mdt = &nandfsdev->nd_dat_mdt; - - locked = NANDFS_VOP_ISLOCKED(NTOV(dat)); - if (!locked) - VOP_LOCK(NTOV(dat), LK_EXCLUSIVE); - req.entrynum = vblock; - - error = nandfs_get_entry_block(mdt, dat, &req, &entry, 0); - if (!error) { - dat_entry = (struct nandfs_dat_entry *) req.bp_entry->b_data; - dat_entry[entry].de_blocknr = block; - - DPRINTF(DAT, ("%s: assing vblock %jx->%jx\n", - __func__, (uintmax_t)vblock, (uintmax_t)block)); - - /* - * It is mostly called from syncer() so - * we want to force making buf dirty - */ - error = nandfs_dirty_buf(req.bp_entry, 1); - } - - if (!locked) - VOP_UNLOCK(NTOV(dat), 0); - - return (error); -} - -int -nandfs_vblock_end(struct nandfs_device *nandfsdev, nandfs_daddr_t vblock) -{ - struct nandfs_node *dat; - struct nandfs_mdt *mdt; - struct nandfs_alloc_request req; - struct nandfs_dat_entry *dat_entry; - uint64_t end; - uint32_t entry; - int locked, error; - - dat = nandfsdev->nd_dat_node; - mdt = &nandfsdev->nd_dat_mdt; - end = nandfsdev->nd_last_cno; - - locked = NANDFS_VOP_ISLOCKED(NTOV(dat)); - if (!locked) - VOP_LOCK(NTOV(dat), LK_EXCLUSIVE); - req.entrynum = vblock; - - error = nandfs_get_entry_block(mdt, dat, &req, &entry, 0); - if (!error) { - dat_entry = (struct nandfs_dat_entry *) req.bp_entry->b_data; - dat_entry[entry].de_end = end; - DPRINTF(DAT, ("%s: end vblock %#jx at checkpoint %#jx\n", - __func__, (uintmax_t)vblock, (uintmax_t)end)); - - /* - * It is mostly called from syncer() so - * we want to force making buf dirty - */ - error = nandfs_dirty_buf(req.bp_entry, 1); - } - - if (!locked) - VOP_UNLOCK(NTOV(dat), 0); - - return (error); -} - -int -nandfs_vblock_free(struct nandfs_device *nandfsdev, nandfs_daddr_t vblock) -{ - struct nandfs_node *dat; - struct nandfs_mdt *mdt; - struct nandfs_alloc_request req; - int error; - - dat = nandfsdev->nd_dat_node; - mdt = &nandfsdev->nd_dat_mdt; - - VOP_LOCK(NTOV(dat), LK_EXCLUSIVE); - req.entrynum = vblock; - - error = nandfs_find_entry(mdt, dat, &req); - if (!error) { - DPRINTF(DAT, ("%s: vblk %#jx\n", __func__, (uintmax_t)vblock)); - nandfs_free_entry(mdt, &req); - } - - VOP_UNLOCK(NTOV(dat), 0); - return (error); -} - -int -nandfs_get_dat_vinfo_ioctl(struct nandfs_device *nandfsdev, struct nandfs_argv *nargv) -{ - struct nandfs_vinfo *vinfo; - size_t size; - int error; - - if (nargv->nv_nmembs > NANDFS_VINFO_MAX) - return (EINVAL); - - size = sizeof(struct nandfs_vinfo) * nargv->nv_nmembs; - vinfo = malloc(size, M_NANDFSTEMP, M_WAITOK|M_ZERO); - - error = copyin((void *)(uintptr_t)nargv->nv_base, vinfo, size); - if (error) { - free(vinfo, M_NANDFSTEMP); - return (error); - } - - error = nandfs_get_dat_vinfo(nandfsdev, vinfo, nargv->nv_nmembs); - if (error == 0) - error = copyout(vinfo, (void *)(uintptr_t)nargv->nv_base, size); - free(vinfo, M_NANDFSTEMP); - return (error); -} - -int -nandfs_get_dat_vinfo(struct nandfs_device *nandfsdev, struct nandfs_vinfo *vinfo, - uint32_t nmembs) -{ - struct nandfs_node *dat; - struct nandfs_mdt *mdt; - struct nandfs_alloc_request req; - struct nandfs_dat_entry *dat_entry; - uint32_t i, idx; - int error = 0; - - dat = nandfsdev->nd_dat_node; - mdt = &nandfsdev->nd_dat_mdt; - - DPRINTF(DAT, ("%s: nmembs %#x\n", __func__, nmembs)); - - VOP_LOCK(NTOV(dat), LK_EXCLUSIVE); - - for (i = 0; i < nmembs; i++) { - req.entrynum = vinfo[i].nvi_vblocknr; - - error = nandfs_get_entry_block(mdt, dat,&req, &idx, 0); - if (error) - break; - - dat_entry = ((struct nandfs_dat_entry *) req.bp_entry->b_data); - vinfo[i].nvi_start = dat_entry[idx].de_start; - vinfo[i].nvi_end = dat_entry[idx].de_end; - vinfo[i].nvi_blocknr = dat_entry[idx].de_blocknr; - - DPRINTF(DAT, ("%s: vinfo: %jx[%jx-%jx]->%jx\n", - __func__, vinfo[i].nvi_vblocknr, vinfo[i].nvi_start, - vinfo[i].nvi_end, vinfo[i].nvi_blocknr)); - - brelse(req.bp_entry); - } - - VOP_UNLOCK(NTOV(dat), 0); - return (error); -} - -int -nandfs_get_dat_bdescs_ioctl(struct nandfs_device *nffsdev, - struct nandfs_argv *nargv) -{ - struct nandfs_bdesc *bd; - size_t size, sizecheck; - int error; - - sizecheck = nargv->nv_nmembs; - if (sizecheck >= SIZE_MAX / sizeof(struct nandfs_bdesc)) - return (EINVAL); - - size = nargv->nv_nmembs * sizeof(struct nandfs_bdesc); - bd = malloc(size, M_NANDFSTEMP, M_WAITOK); - error = copyin((void *)(uintptr_t)nargv->nv_base, bd, size); - if (error) { - free(bd, M_NANDFSTEMP); - return (error); - } - - error = nandfs_get_dat_bdescs(nffsdev, bd, nargv->nv_nmembs); - - if (error == 0) - error = copyout(bd, (void *)(uintptr_t)nargv->nv_base, size); - - free(bd, M_NANDFSTEMP); - return (error); -} - -int -nandfs_get_dat_bdescs(struct nandfs_device *nffsdev, struct nandfs_bdesc *bd, - uint32_t nmembs) -{ - struct nandfs_node *dat_node; - uint64_t map; - uint32_t i; - int error = 0; - - dat_node = nffsdev->nd_dat_node; - - VOP_LOCK(NTOV(dat_node), LK_EXCLUSIVE); - - for (i = 0; i < nmembs; i++) { - DPRINTF(CLEAN, - ("%s: bd ino:%#jx oblk:%#jx blocknr:%#jx off:%#jx\n", - __func__, (uintmax_t)bd[i].bd_ino, - (uintmax_t)bd[i].bd_oblocknr, (uintmax_t)bd[i].bd_blocknr, - (uintmax_t)bd[i].bd_offset)); - - error = nandfs_bmap_lookup(dat_node, bd[i].bd_offset, &map); - if (error) - break; - bd[i].bd_blocknr = map; - } - - VOP_UNLOCK(NTOV(dat_node), 0); - return (error); -} diff --git a/sys/fs/nandfs/nandfs_dir.c b/sys/fs/nandfs/nandfs_dir.c deleted file mode 100644 index e1d9f29fde7..00000000000 --- a/sys/fs/nandfs/nandfs_dir.c +++ /dev/null @@ -1,315 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2010-2012 Semihalf - * Copyright (c) 2008, 2009 Reinoud Zandijk - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * From: NetBSD: nilfs_subr.c,v 1.4 2009/07/29 17:06:57 reinoud - */ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include "nandfs_mount.h" -#include "nandfs.h" -#include "nandfs_subr.h" - -int -nandfs_add_dirent(struct vnode *dvp, uint64_t ino, char *nameptr, long namelen, - uint8_t type) -{ - struct nandfs_node *dir_node = VTON(dvp); - struct nandfs_dir_entry *dirent, *pdirent; - uint32_t blocksize = dir_node->nn_nandfsdev->nd_blocksize; - uint64_t filesize = dir_node->nn_inode.i_size; - uint64_t inode_blks = dir_node->nn_inode.i_blocks; - uint32_t off, rest; - uint8_t *pos; - struct buf *bp; - int error; - - pdirent = NULL; - bp = NULL; - if (inode_blks) { - error = nandfs_bread(dir_node, inode_blks - 1, NOCRED, 0, &bp); - if (error) { - brelse(bp); - return (error); - } - - pos = bp->b_data; - off = 0; - while (off < blocksize) { - pdirent = (struct nandfs_dir_entry *) (pos + off); - if (!pdirent->rec_len) { - pdirent = NULL; - break; - } - off += pdirent->rec_len; - } - - if (pdirent) - rest = pdirent->rec_len - - NANDFS_DIR_REC_LEN(pdirent->name_len); - else - rest = blocksize; - - if (rest < NANDFS_DIR_REC_LEN(namelen)) { - /* Do not update pdirent as new block is created */ - pdirent = NULL; - brelse(bp); - /* Set to NULL to create new */ - bp = NULL; - filesize += rest; - } - } - - /* If no bp found create new */ - if (!bp) { - error = nandfs_bcreate(dir_node, inode_blks, NOCRED, 0, &bp); - if (error) - return (error); - off = 0; - pos = bp->b_data; - } - - /* Modify pdirent if exists */ - if (pdirent) { - DPRINTF(LOOKUP, ("modify pdirent %p\n", pdirent)); - /* modify last de */ - off -= pdirent->rec_len; - pdirent->rec_len = - NANDFS_DIR_REC_LEN(pdirent->name_len); - off += pdirent->rec_len; - } - - /* Create new dirent */ - dirent = (struct nandfs_dir_entry *) (pos + off); - dirent->rec_len = blocksize - off; - dirent->inode = ino; - dirent->name_len = namelen; - memset(dirent->name, 0, NANDFS_DIR_NAME_LEN(namelen)); - memcpy(dirent->name, nameptr, namelen); - dirent->file_type = type; - - filesize += NANDFS_DIR_REC_LEN(dirent->name_len); - - DPRINTF(LOOKUP, ("create dir_entry '%.*s' at %p with size %x " - "new filesize: %jx\n", - (int)namelen, dirent->name, dirent, dirent->rec_len, - (uintmax_t)filesize)); - - error = nandfs_dirty_buf(bp, 0); - if (error) - return (error); - - dir_node->nn_inode.i_size = filesize; - dir_node->nn_flags |= IN_CHANGE | IN_UPDATE; - vnode_pager_setsize(dvp, filesize); - - return (0); -} - -int -nandfs_remove_dirent(struct vnode *dvp, struct nandfs_node *node, - struct componentname *cnp) -{ - struct nandfs_node *dir_node; - struct nandfs_dir_entry *dirent, *pdirent; - struct buf *bp; - uint64_t filesize, blocknr, ino, offset; - uint32_t blocksize, limit, off; - uint16_t newsize; - uint8_t *pos; - int error, found; - - dir_node = VTON(dvp); - filesize = dir_node->nn_inode.i_size; - if (!filesize) - return (0); - - if (node) { - offset = node->nn_diroff; - ino = node->nn_ino; - } else { - offset = dir_node->nn_diroff; - ino = NANDFS_WHT_INO; - } - - dirent = pdirent = NULL; - blocksize = dir_node->nn_nandfsdev->nd_blocksize; - blocknr = offset / blocksize; - - DPRINTF(LOOKUP, ("rm direntry dvp %p node %p ino %#jx at off %#jx\n", - dvp, node, (uintmax_t)ino, (uintmax_t)offset)); - - error = nandfs_bread(dir_node, blocknr, NOCRED, 0, &bp); - if (error) { - brelse(bp); - return (error); - } - - pos = bp->b_data; - off = 0; - found = 0; - limit = offset % blocksize; - pdirent = (struct nandfs_dir_entry *) bp->b_data; - while (off <= limit) { - dirent = (struct nandfs_dir_entry *) (pos + off); - - if ((off == limit) && - (dirent->inode == ino)) { - found = 1; - break; - } - if (dirent->inode != 0) - pdirent = dirent; - off += dirent->rec_len; - } - - if (!found) { - nandfs_error("cannot find entry to remove"); - brelse(bp); - return (error); - } - DPRINTF(LOOKUP, - ("rm dirent ino %#jx at %#x with size %#x\n", - (uintmax_t)dirent->inode, off, dirent->rec_len)); - - newsize = (uintptr_t)dirent - (uintptr_t)pdirent; - newsize += dirent->rec_len; - pdirent->rec_len = newsize; - dirent->inode = 0; - error = nandfs_dirty_buf(bp, 0); - if (error) - return (error); - - dir_node->nn_flags |= IN_CHANGE | IN_UPDATE; - /* If last one modify filesize */ - if ((offset + NANDFS_DIR_REC_LEN(dirent->name_len)) == filesize) { - filesize = blocknr * blocksize + - ((uintptr_t)pdirent - (uintptr_t)pos) + - NANDFS_DIR_REC_LEN(pdirent->name_len); - dir_node->nn_inode.i_size = filesize; - } - - return (0); -} - -int -nandfs_update_parent_dir(struct vnode *dvp, uint64_t newparent) -{ - struct nandfs_dir_entry *dirent; - struct nandfs_node *dir_node; - struct buf *bp; - int error; - - dir_node = VTON(dvp); - error = nandfs_bread(dir_node, 0, NOCRED, 0, &bp); - if (error) { - brelse(bp); - return (error); - } - dirent = (struct nandfs_dir_entry *)bp->b_data; - dirent->inode = newparent; - error = nandfs_dirty_buf(bp, 0); - if (error) - return (error); - - return (0); -} - -int -nandfs_update_dirent(struct vnode *dvp, struct nandfs_node *fnode, - struct nandfs_node *tnode) -{ - struct nandfs_node *dir_node; - struct nandfs_dir_entry *dirent; - struct buf *bp; - uint64_t file_size, blocknr; - uint32_t blocksize, off; - uint8_t *pos; - int error; - - dir_node = VTON(dvp); - file_size = dir_node->nn_inode.i_size; - if (!file_size) - return (0); - - DPRINTF(LOOKUP, - ("chg direntry dvp %p ino %#jx to in %#jx at off %#jx\n", - dvp, (uintmax_t)tnode->nn_ino, (uintmax_t)fnode->nn_ino, - (uintmax_t)tnode->nn_diroff)); - - blocksize = dir_node->nn_nandfsdev->nd_blocksize; - blocknr = tnode->nn_diroff / blocksize; - off = tnode->nn_diroff % blocksize; - error = nandfs_bread(dir_node, blocknr, NOCRED, 0, &bp); - if (error) { - brelse(bp); - return (error); - } - - pos = bp->b_data; - dirent = (struct nandfs_dir_entry *) (pos + off); - KASSERT((dirent->inode == tnode->nn_ino), - ("direntry mismatch")); - - dirent->inode = fnode->nn_ino; - error = nandfs_dirty_buf(bp, 0); - if (error) - return (error); - - return (0); -} - -int -nandfs_init_dir(struct vnode *dvp, uint64_t ino, uint64_t parent_ino) -{ - - if (nandfs_add_dirent(dvp, parent_ino, "..", 2, DT_DIR) || - nandfs_add_dirent(dvp, ino, ".", 1, DT_DIR)) { - nandfs_error("%s: cannot initialize dir ino:%jd(pino:%jd)\n", - __func__, ino, parent_ino); - return (-1); - } - return (0); -} diff --git a/sys/fs/nandfs/nandfs_fs.h b/sys/fs/nandfs/nandfs_fs.h deleted file mode 100644 index 4db332d61bf..00000000000 --- a/sys/fs/nandfs/nandfs_fs.h +++ /dev/null @@ -1,566 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2010-2012 Semihalf - * Copyright (c) 2008, 2009 Reinoud Zandijk - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Original definitions written by Koji Sato - * and Ryusuke Konishi - * From: NetBSD: nandfs_fs.h,v 1.1 2009/07/18 16:31:42 reinoud - * - */ - -#ifndef _NANDFS_FS_H -#define _NANDFS_FS_H - -#include - -#define MNINDIR(fsdev) ((fsdev)->nd_blocksize / sizeof(nandfs_daddr_t)) - -/* - * Inode structure. There are a few dedicated inode numbers that are - * defined here first. - */ -#define NANDFS_WHT_INO 1 /* Whiteout ino */ -#define NANDFS_ROOT_INO 2 /* Root file inode */ -#define NANDFS_DAT_INO 3 /* DAT file */ -#define NANDFS_CPFILE_INO 4 /* checkpoint file */ -#define NANDFS_SUFILE_INO 5 /* segment usage file */ -#define NANDFS_IFILE_INO 6 /* ifile */ -#define NANDFS_GC_INO 7 /* Cleanerd node */ -#define NANDFS_ATIME_INO 8 /* Atime file (reserved) */ -#define NANDFS_XATTR_INO 9 /* Xattribute file (reserved) */ -#define NANDFS_SKETCH_INO 10 /* Sketch file (obsolete) */ -#define NANDFS_USER_INO 11 /* First user's file inode number */ - -#define NANDFS_SYS_NODE(ino) \ - (((ino) >= NANDFS_DAT_INO) && ((ino) <= NANDFS_GC_INO)) - -#define NANDFS_NDADDR 12 /* Direct addresses in inode. */ -#define NANDFS_NIADDR 3 /* Indirect addresses in inode. */ - -typedef int64_t nandfs_daddr_t; -typedef int64_t nandfs_lbn_t; - -struct nandfs_inode { - uint64_t i_blocks; /* 0: size in device blocks */ - uint64_t i_size; /* 8: size in bytes */ - uint64_t i_ctime; /* 16: creation time in seconds */ - uint64_t i_mtime; /* 24: modification time in seconds part*/ - uint32_t i_ctime_nsec; /* 32: creation time nanoseconds part */ - uint32_t i_mtime_nsec; /* 36: modification time in nanoseconds */ - uint32_t i_uid; /* 40: user id */ - uint32_t i_gid; /* 44: group id */ - uint16_t i_mode; /* 48: file mode */ - uint16_t i_links_count; /* 50: number of references to the inode*/ - uint32_t i_flags; /* 52: NANDFS_*_FL flags */ - nandfs_daddr_t i_special; /* 56: special */ - nandfs_daddr_t i_db[NANDFS_NDADDR]; /* 64: Direct disk blocks. */ - nandfs_daddr_t i_ib[NANDFS_NIADDR]; /* 160: Indirect disk blocks. */ - uint64_t i_xattr; /* 184: reserved for extended attributes*/ - uint32_t i_generation; /* 192: file generation for NFS */ - uint32_t i_pad[15]; /* 196: make it 64 bits aligned */ -}; - -#ifdef _KERNEL -CTASSERT(sizeof(struct nandfs_inode) == 256); -#endif - -/* - * Each checkpoint/snapshot has a super root. - * - * The super root holds the inodes of the three system files: `dat', `cp' and - * 'su' files. All other FS state is defined by those. - * - * It is CRC checksum'ed and time stamped. - */ - -struct nandfs_super_root { - uint32_t sr_sum; /* check-sum */ - uint16_t sr_bytes; /* byte count of this structure */ - uint16_t sr_flags; /* reserved for flags */ - uint64_t sr_nongc_ctime; /* timestamp, not for cleaner(?) */ - struct nandfs_inode sr_dat; /* DAT, virt->phys translation inode */ - struct nandfs_inode sr_cpfile; /* CP, checkpoints inode */ - struct nandfs_inode sr_sufile; /* SU, segment usage inode */ -}; - -#define NANDFS_SR_MDT_OFFSET(inode_size, i) \ - ((uint32_t)&((struct nandfs_super_root *)0)->sr_dat + \ - (inode_size) * (i)) - -#define NANDFS_SR_DAT_OFFSET(inode_size) NANDFS_SR_MDT_OFFSET(inode_size, 0) -#define NANDFS_SR_CPFILE_OFFSET(inode_size) NANDFS_SR_MDT_OFFSET(inode_size, 1) -#define NANDFS_SR_SUFILE_OFFSET(inode_size) NANDFS_SR_MDT_OFFSET(inode_size, 2) -#define NANDFS_SR_BYTES (sizeof(struct nandfs_super_root)) - -/* - * The superblock describes the basic structure and mount history. It also - * records some sizes of structures found on the disc for sanity checks. - * - * The superblock is stored at two places: NANDFS_SB_OFFSET_BYTES and - * NANDFS_SB2_OFFSET_BYTES. - */ - -/* File system states stored on media in superblock's sbp->s_state */ -#define NANDFS_VALID_FS 0x0001 /* cleanly unmounted and all is ok */ -#define NANDFS_ERROR_FS 0x0002 /* there were errors detected, fsck */ -#define NANDFS_RESIZE_FS 0x0004 /* resize required, XXX unknown flag*/ -#define NANDFS_MOUNT_STATE_BITS "\20\1VALID_FS\2ERROR_FS\3RESIZE_FS" - -/* - * Brief description of control structures: - * - * NANDFS_NFSAREAS first blocks contain fsdata and some amount of super blocks. - * Simple round-robin policy is used in order to choose which block will - * contain new super block. - * - * Simple case with 2 blocks: - * 1: fsdata sblock1 [sblock3 [sblock5 ..]] - * 2: fsdata sblock2 [sblock4 [sblock6 ..]] - */ -struct nandfs_fsdata { - uint16_t f_magic; - uint16_t f_bytes; - - uint32_t f_sum; /* checksum of fsdata */ - uint32_t f_rev_level; /* major disk format revision */ - - uint64_t f_ctime; /* creation time (execution time - of newfs) */ - /* Block size represented as: blocksize = 1 << (f_log_block_size + 10) */ - uint32_t f_log_block_size; - - uint16_t f_inode_size; /* size of an inode */ - uint16_t f_dat_entry_size; /* size of a dat entry */ - uint16_t f_checkpoint_size; /* size of a checkpoint */ - uint16_t f_segment_usage_size; /* size of a segment usage */ - - uint16_t f_sbbytes; /* byte count of CRC calculation - for super blocks. s_reserved - is excluded! */ - - uint16_t f_errors; /* behaviour on detecting errors */ - - uint32_t f_erasesize; - uint64_t f_nsegments; /* number of segm. in filesystem */ - nandfs_daddr_t f_first_data_block; /* 1st seg disk block number */ - uint32_t f_blocks_per_segment; /* number of blocks per segment */ - uint32_t f_r_segments_percentage; /* reserved segments percentage */ - - struct uuid f_uuid; /* 128-bit uuid for volume */ - char f_volume_name[16]; /* volume name */ - uint32_t f_pad[104]; -} __packed; - -#ifdef _KERNEL -CTASSERT(sizeof(struct nandfs_fsdata) == 512); -#endif - -struct nandfs_super_block { - uint16_t s_magic; /* magic value for identification */ - - uint32_t s_sum; /* check sum of super block */ - - uint64_t s_last_cno; /* last checkpoint number */ - uint64_t s_last_pseg; /* addr part. segm. written last */ - uint64_t s_last_seq; /* seq.number of seg written last */ - uint64_t s_free_blocks_count; /* free blocks count */ - - uint64_t s_mtime; /* mount time */ - uint64_t s_wtime; /* write time */ - uint16_t s_state; /* file system state */ - - char s_last_mounted[64]; /* directory where last mounted */ - - uint32_t s_c_interval; /* commit interval of segment */ - uint32_t s_c_block_max; /* threshold of data amount for - the segment construction */ - uint32_t s_reserved[32]; /* padding to end of the block */ -} __packed; - -#ifdef _KERNEL -CTASSERT(sizeof(struct nandfs_super_block) == 256); -#endif - -#define NANDFS_FSDATA_MAGIC 0xf8da -#define NANDFS_SUPER_MAGIC 0x8008 - -#define NANDFS_NFSAREAS 4 -#define NANDFS_DATA_OFFSET_BYTES(esize) (NANDFS_NFSAREAS * (esize)) - -#define NANDFS_SBLOCK_OFFSET_BYTES (sizeof(struct nandfs_fsdata)) - -#define NANDFS_DEF_BLOCKSIZE 4096 -#define NANDFS_MIN_BLOCKSIZE 512 - -#define NANDFS_DEF_ERASESIZE (2 << 16) - -#define NANDFS_MIN_SEGSIZE NANDFS_DEF_ERASESIZE - -#define NANDFS_CURRENT_REV 9 /* current major revision */ - -#define NANDFS_FSDATA_CRC_BYTES offsetof(struct nandfs_fsdata, f_pad) -/* Bytes count of super_block for CRC-calculation */ -#define NANDFS_SB_BYTES offsetof(struct nandfs_super_block, s_reserved) - -/* Maximal count of links to a file */ -#define NANDFS_LINK_MAX 32000 - -/* - * Structure of a directory entry. - * - * Note that they can't span blocks; the rec_len fills out. - */ - -#define NANDFS_NAME_LEN 255 -struct nandfs_dir_entry { - uint64_t inode; /* inode number */ - uint16_t rec_len; /* directory entry length */ - uint8_t name_len; /* name length */ - uint8_t file_type; - char name[NANDFS_NAME_LEN]; /* file name */ - char pad; -}; - -/* - * NANDFS_DIR_PAD defines the directory entries boundaries - * - * NOTE: It must be a multiple of 8 - */ -#define NANDFS_DIR_PAD 8 -#define NANDFS_DIR_ROUND (NANDFS_DIR_PAD - 1) -#define NANDFS_DIR_NAME_OFFSET (offsetof(struct nandfs_dir_entry, name)) -#define NANDFS_DIR_REC_LEN(name_len) \ - (((name_len) + NANDFS_DIR_NAME_OFFSET + NANDFS_DIR_ROUND) \ - & ~NANDFS_DIR_ROUND) -#define NANDFS_DIR_NAME_LEN(name_len) \ - (NANDFS_DIR_REC_LEN(name_len) - NANDFS_DIR_NAME_OFFSET) - -/* - * NiLFS/NANDFS devides the disc into fixed length segments. Each segment is - * filled with one or more partial segments of variable lengths. - * - * Each partial segment has a segment summary header followed by updates of - * files and optionally a super root. - */ - -/* - * Virtual to physical block translation information. For data blocks it maps - * logical block number bi_blkoff to virtual block nr bi_vblocknr. For non - * datablocks it is the virtual block number assigned to an indirect block - * and has no bi_blkoff. The physical block number is the next - * available data block in the partial segment after all the binfo's. - */ -struct nandfs_binfo_v { - uint64_t bi_ino; /* file's inode */ - uint64_t bi_vblocknr; /* assigned virtual block number */ - uint64_t bi_blkoff; /* for file's logical block number */ -}; - -/* - * DAT allocation. For data blocks just the logical block number that maps on - * the next available data block in the partial segment after the binfo's. - */ -struct nandfs_binfo_dat { - uint64_t bi_ino; - uint64_t bi_blkoff; /* DAT file's logical block number */ - uint8_t bi_level; /* whether this is meta block */ - uint8_t bi_pad[7]; -}; - -#ifdef _KERNEL -CTASSERT(sizeof(struct nandfs_binfo_v) == sizeof(struct nandfs_binfo_dat)); -#endif - -/* Convenience union for both types of binfo's */ -union nandfs_binfo { - struct nandfs_binfo_v bi_v; - struct nandfs_binfo_dat bi_dat; -}; - -/* Indirect buffers path */ -struct nandfs_indir { - nandfs_daddr_t in_lbn; - int in_off; -}; - -/* The (partial) segment summary */ -struct nandfs_segment_summary { - uint32_t ss_datasum; /* CRC of complete data block */ - uint32_t ss_sumsum; /* CRC of segment summary only */ - uint32_t ss_magic; /* magic to identify segment summary */ - uint16_t ss_bytes; /* size of segment summary structure */ - uint16_t ss_flags; /* NANDFS_SS_* flags */ - uint64_t ss_seq; /* sequence number of this segm. sum */ - uint64_t ss_create; /* creation timestamp in seconds */ - uint64_t ss_next; /* blocknumber of next segment */ - uint32_t ss_nblocks; /* number of blocks used by summary */ - uint32_t ss_nbinfos; /* number of binfo structures */ - uint32_t ss_sumbytes; /* total size of segment summary */ - uint32_t ss_pad; - /* stream of binfo structures */ -}; - -#define NANDFS_SEGSUM_MAGIC 0x8e680011 /* segment summary magic number */ - -/* Segment summary flags */ -#define NANDFS_SS_LOGBGN 0x0001 /* begins a logical segment */ -#define NANDFS_SS_LOGEND 0x0002 /* ends a logical segment */ -#define NANDFS_SS_SR 0x0004 /* has super root */ -#define NANDFS_SS_SYNDT 0x0008 /* includes data only updates */ -#define NANDFS_SS_GC 0x0010 /* segment written for cleaner operation */ -#define NANDFS_SS_FLAG_BITS "\20\1LOGBGN\2LOGEND\3SR\4SYNDT\5GC" - -/* Segment summary constrains */ -#define NANDFS_SEG_MIN_BLOCKS 16 /* minimum number of blocks in a - full segment */ -#define NANDFS_PSEG_MIN_BLOCKS 2 /* minimum number of blocks in a - partial segment */ -#define NANDFS_MIN_NRSVSEGS 8 /* minimum number of reserved - segments */ - -/* - * Structure of DAT/inode file. - * - * A DAT file is divided into groups. The maximum number of groups is the - * number of block group descriptors that fit into one block; this descriptor - * only gives the number of free entries in the associated group. - * - * Each group has a block sized bitmap indicating if an entry is taken or - * empty. Each bit stands for a DAT entry. - * - * The inode file has exactly the same format only the entries are inode - * entries. - */ - -struct nandfs_block_group_desc { - uint32_t bg_nfrees; /* num. free entries in block group */ -}; - -/* DAT entry in a super root's DAT file */ -struct nandfs_dat_entry { - uint64_t de_blocknr; /* block number */ - uint64_t de_start; /* valid from checkpoint */ - uint64_t de_end; /* valid till checkpoint */ - uint64_t de_rsv; /* reserved for future use */ -}; - -/* - * Structure of CP file. - * - * A snapshot is just a checkpoint only it's protected against removal by the - * cleaner. The snapshots are kept on a double linked list of checkpoints. - */ -struct nandfs_snapshot_list { - uint64_t ssl_next; /* checkpoint nr. forward */ - uint64_t ssl_prev; /* checkpoint nr. back */ -}; - -/* Checkpoint entry structure */ -struct nandfs_checkpoint { - uint32_t cp_flags; /* NANDFS_CHECKPOINT_* flags */ - uint32_t cp_checkpoints_count; /* ZERO, not used anymore? */ - struct nandfs_snapshot_list cp_snapshot_list; /* list of snapshots */ - uint64_t cp_cno; /* checkpoint number */ - uint64_t cp_create; /* creation timestamp */ - uint64_t cp_nblk_inc; /* number of blocks incremented */ - uint64_t cp_blocks_count; /* reserved (might be deleted) */ - struct nandfs_inode cp_ifile_inode; /* inode file inode */ -}; - -/* Checkpoint flags */ -#define NANDFS_CHECKPOINT_SNAPSHOT 1 -#define NANDFS_CHECKPOINT_INVALID 2 -#define NANDFS_CHECKPOINT_SKETCH 4 -#define NANDFS_CHECKPOINT_MINOR 8 -#define NANDFS_CHECKPOINT_BITS "\20\1SNAPSHOT\2INVALID\3SKETCH\4MINOR" - -/* Header of the checkpoint file */ -struct nandfs_cpfile_header { - uint64_t ch_ncheckpoints; /* number of checkpoints */ - uint64_t ch_nsnapshots; /* number of snapshots */ - struct nandfs_snapshot_list ch_snapshot_list; /* snapshot list */ -}; - -#define NANDFS_CPFILE_FIRST_CHECKPOINT_OFFSET \ - ((sizeof(struct nandfs_cpfile_header) + \ - sizeof(struct nandfs_checkpoint) - 1) / \ - sizeof(struct nandfs_checkpoint)) - - -#define NANDFS_NOSEGMENT 0xffffffff - -/* - * Structure of SU file. - * - * The segment usage file sums up how each of the segments are used. They are - * indexed by their segment number. - */ - -/* Segment usage entry */ -struct nandfs_segment_usage { - uint64_t su_lastmod; /* last modified timestamp */ - uint32_t su_nblocks; /* number of blocks in segment */ - uint32_t su_flags; /* NANDFS_SEGMENT_USAGE_* flags */ -}; - -/* Segment usage flag */ -#define NANDFS_SEGMENT_USAGE_ACTIVE 1 -#define NANDFS_SEGMENT_USAGE_DIRTY 2 -#define NANDFS_SEGMENT_USAGE_ERROR 4 -#define NANDFS_SEGMENT_USAGE_GC 8 -#define NANDFS_SEGMENT_USAGE_BITS "\20\1ACTIVE\2DIRTY\3ERROR" - -/* Header of the segment usage file */ -struct nandfs_sufile_header { - uint64_t sh_ncleansegs; /* number of segments marked clean */ - uint64_t sh_ndirtysegs; /* number of segments marked dirty */ - uint64_t sh_last_alloc; /* last allocated segment number */ -}; - -#define NANDFS_SUFILE_FIRST_SEGMENT_USAGE_OFFSET \ - ((sizeof(struct nandfs_sufile_header) + \ - sizeof(struct nandfs_segment_usage) - 1) / \ - sizeof(struct nandfs_segment_usage)) - -struct nandfs_seg_stat { - uint64_t nss_nsegs; - uint64_t nss_ncleansegs; - uint64_t nss_ndirtysegs; - uint64_t nss_ctime; - uint64_t nss_nongc_ctime; - uint64_t nss_prot_seq; -}; - -enum { - NANDFS_CHECKPOINT, - NANDFS_SNAPSHOT -}; - -#define NANDFS_CPINFO_MAX 512 - -struct nandfs_cpinfo { - uint32_t nci_flags; - uint32_t nci_pad; - uint64_t nci_cno; - uint64_t nci_create; - uint64_t nci_nblk_inc; - uint64_t nci_blocks_count; - uint64_t nci_next; -}; - -#define NANDFS_SEGMENTS_MAX 512 - -struct nandfs_suinfo { - uint64_t nsi_num; - uint64_t nsi_lastmod; - uint32_t nsi_blocks; - uint32_t nsi_flags; -}; - -#define NANDFS_VINFO_MAX 512 - -struct nandfs_vinfo { - uint64_t nvi_ino; - uint64_t nvi_vblocknr; - uint64_t nvi_start; - uint64_t nvi_end; - uint64_t nvi_blocknr; - int nvi_alive; -}; - -struct nandfs_cpmode { - uint64_t ncpm_cno; - uint32_t ncpm_mode; - uint32_t ncpm_pad; -}; - -struct nandfs_argv { - uint64_t nv_base; - uint32_t nv_nmembs; - uint16_t nv_size; - uint16_t nv_flags; - uint64_t nv_index; -}; - -struct nandfs_cpstat { - uint64_t ncp_cno; - uint64_t ncp_ncps; - uint64_t ncp_nss; -}; - -struct nandfs_period { - uint64_t p_start; - uint64_t p_end; -}; - -struct nandfs_vdesc { - uint64_t vd_ino; - uint64_t vd_cno; - uint64_t vd_vblocknr; - struct nandfs_period vd_period; - uint64_t vd_blocknr; - uint64_t vd_offset; - uint32_t vd_flags; - uint32_t vd_pad; -}; - -struct nandfs_bdesc { - uint64_t bd_ino; - uint64_t bd_oblocknr; - uint64_t bd_blocknr; - uint64_t bd_offset; - uint32_t bd_level; - uint32_t bd_alive; -}; - -#ifndef _KERNEL -#ifndef MNAMELEN -#define MNAMELEN 1024 -#endif -#endif - -struct nandfs_fsinfo { - struct nandfs_fsdata fs_fsdata; - struct nandfs_super_block fs_super; - char fs_dev[MNAMELEN]; -}; - -#define NANDFS_MAX_MOUNTS 65535 - -#define NANDFS_IOCTL_GET_SUSTAT _IOR('N', 100, struct nandfs_seg_stat) -#define NANDFS_IOCTL_CHANGE_CPMODE _IOWR('N', 101, struct nandfs_cpmode) -#define NANDFS_IOCTL_GET_CPINFO _IOWR('N', 102, struct nandfs_argv) -#define NANDFS_IOCTL_DELETE_CP _IOWR('N', 103, uint64_t[2]) -#define NANDFS_IOCTL_GET_CPSTAT _IOR('N', 104, struct nandfs_cpstat) -#define NANDFS_IOCTL_GET_SUINFO _IOWR('N', 105, struct nandfs_argv) -#define NANDFS_IOCTL_GET_VINFO _IOWR('N', 106, struct nandfs_argv) -#define NANDFS_IOCTL_GET_BDESCS _IOWR('N', 107, struct nandfs_argv) -#define NANDFS_IOCTL_GET_FSINFO _IOR('N', 108, struct nandfs_fsinfo) -#define NANDFS_IOCTL_MAKE_SNAP _IOWR('N', 109, uint64_t) -#define NANDFS_IOCTL_DELETE_SNAP _IOWR('N', 110, uint64_t) -#define NANDFS_IOCTL_SYNC _IOWR('N', 111, uint64_t) - -#endif /* _NANDFS_FS_H */ diff --git a/sys/fs/nandfs/nandfs_ifile.c b/sys/fs/nandfs/nandfs_ifile.c deleted file mode 100644 index 2e079bfc449..00000000000 --- a/sys/fs/nandfs/nandfs_ifile.c +++ /dev/null @@ -1,214 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2010-2012 Semihalf. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include -#include -#include - -int -nandfs_node_create(struct nandfsmount *nmp, struct nandfs_node **node, - uint16_t mode) -{ - struct nandfs_alloc_request req; - struct nandfs_device *nandfsdev; - struct nandfs_mdt *mdt; - struct nandfs_node *ifile; - struct nandfs_inode *inode; - struct vnode *vp; - uint32_t entry; - int error = 0; - - nandfsdev = nmp->nm_nandfsdev; - mdt = &nandfsdev->nd_ifile_mdt; - ifile = nmp->nm_ifile_node; - vp = NTOV(ifile); - - VOP_LOCK(vp, LK_EXCLUSIVE); - /* Allocate new inode in ifile */ - req.entrynum = nandfsdev->nd_last_ino + 1; - error = nandfs_find_free_entry(mdt, ifile, &req); - if (error) { - VOP_UNLOCK(vp, 0); - return (error); - } - - error = nandfs_get_entry_block(mdt, ifile, &req, &entry, 1); - if (error) { - VOP_UNLOCK(vp, 0); - return (error); - } - - /* Inode initialization */ - inode = ((struct nandfs_inode *) req.bp_entry->b_data) + entry; - nandfs_inode_init(inode, mode); - - error = nandfs_alloc_entry(mdt, &req); - if (error) { - VOP_UNLOCK(vp, 0); - return (error); - } - - VOP_UNLOCK(vp, 0); - - nandfsdev->nd_last_ino = req.entrynum; - error = nandfs_get_node(nmp, req.entrynum, node); - DPRINTF(IFILE, ("%s: node: %p ino: %#jx\n", - __func__, node, (uintmax_t)((*node)->nn_ino))); - - return (error); -} - -int -nandfs_node_destroy(struct nandfs_node *node) -{ - struct nandfs_alloc_request req; - struct nandfsmount *nmp; - struct nandfs_mdt *mdt; - struct nandfs_node *ifile; - struct vnode *vp; - int error = 0; - - nmp = node->nn_nmp; - req.entrynum = node->nn_ino; - mdt = &nmp->nm_nandfsdev->nd_ifile_mdt; - ifile = nmp->nm_ifile_node; - vp = NTOV(ifile); - - DPRINTF(IFILE, ("%s: destroy node: %p ino: %#jx\n", - __func__, node, (uintmax_t)node->nn_ino)); - VOP_LOCK(vp, LK_EXCLUSIVE); - - error = nandfs_find_entry(mdt, ifile, &req); - if (error) { - nandfs_error("%s: finding entry error:%d node %p(%jx)", - __func__, error, node, node->nn_ino); - VOP_UNLOCK(vp, 0); - return (error); - } - - nandfs_inode_destroy(&node->nn_inode); - - error = nandfs_free_entry(mdt, &req); - if (error) { - nandfs_error("%s: freing entry error:%d node %p(%jx)", - __func__, error, node, node->nn_ino); - VOP_UNLOCK(vp, 0); - return (error); - } - - VOP_UNLOCK(vp, 0); - DPRINTF(IFILE, ("%s: freed node %p ino %#jx\n", - __func__, node, (uintmax_t)node->nn_ino)); - return (error); -} - -int -nandfs_node_update(struct nandfs_node *node) -{ - struct nandfs_alloc_request req; - struct nandfsmount *nmp; - struct nandfs_mdt *mdt; - struct nandfs_node *ifile; - struct nandfs_inode *inode; - uint32_t index; - int error = 0; - - nmp = node->nn_nmp; - ifile = nmp->nm_ifile_node; - ASSERT_VOP_LOCKED(NTOV(ifile), __func__); - - req.entrynum = node->nn_ino; - mdt = &nmp->nm_nandfsdev->nd_ifile_mdt; - - DPRINTF(IFILE, ("%s: node:%p ino:%#jx\n", - __func__, &node->nn_inode, (uintmax_t)node->nn_ino)); - - error = nandfs_get_entry_block(mdt, ifile, &req, &index, 0); - if (error) { - printf("nandfs_get_entry_block returned with ERROR=%d\n", - error); - return (error); - } - - inode = ((struct nandfs_inode *) req.bp_entry->b_data) + index; - memcpy(inode, &node->nn_inode, sizeof(*inode)); - error = nandfs_dirty_buf(req.bp_entry, 0); - - return (error); -} - -int -nandfs_get_node_entry(struct nandfsmount *nmp, struct nandfs_inode **inode, - uint64_t ino, struct buf **bp) -{ - struct nandfs_alloc_request req; - struct nandfs_mdt *mdt; - struct nandfs_node *ifile; - struct vnode *vp; - uint32_t index; - int error = 0; - - req.entrynum = ino; - mdt = &nmp->nm_nandfsdev->nd_ifile_mdt; - ifile = nmp->nm_ifile_node; - vp = NTOV(ifile); - - VOP_LOCK(vp, LK_EXCLUSIVE); - error = nandfs_get_entry_block(mdt, ifile, &req, &index, 0); - if (error) { - VOP_UNLOCK(vp, 0); - return (error); - } - - *inode = ((struct nandfs_inode *) req.bp_entry->b_data) + index; - *bp = req.bp_entry; - VOP_UNLOCK(vp, 0); - return (0); -} - diff --git a/sys/fs/nandfs/nandfs_mount.h b/sys/fs/nandfs/nandfs_mount.h deleted file mode 100644 index 72798db99e3..00000000000 --- a/sys/fs/nandfs/nandfs_mount.h +++ /dev/null @@ -1,51 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-4-Clause - * - * Copyright (c) 2008, 2009 Reinoud Zandijk - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed for the - * NetBSD Project. See http://www.NetBSD.org/ for - * information about NetBSD. - * 4. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * From: NetBSD: nilfs_mount.h,v 1.1 2009/07/18 16:31:42 reinoud - * - */ - -#ifndef _FS_NANDFS_NANDFS_MOUNT_H_ -#define _FS_NANDFS_NANDFS_MOUNT_H_ - -/* - * Arguments to mount NANDFS filingsystem. - */ - -struct nandfs_args { - char *fspec; /* mount specifier */ - int64_t cpno; /* checkpoint number */ -}; - -#endif /* !_FS_NANDFS_NANDFS_MOUNT_H_ */ - diff --git a/sys/fs/nandfs/nandfs_segment.c b/sys/fs/nandfs/nandfs_segment.c deleted file mode 100644 index 8ca44773661..00000000000 --- a/sys/fs/nandfs/nandfs_segment.c +++ /dev/null @@ -1,1313 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2010-2012 Semihalf. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include - -#include "opt_ddb.h" - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include -#include -#include -#include - -#include -#include - -#include -#include -#include - -static int -nandfs_new_segment(struct nandfs_device *fsdev) -{ - int error = 0; - uint64_t new; - - error = nandfs_alloc_segment(fsdev, &new); - if (!error) { - fsdev->nd_seg_num = fsdev->nd_next_seg_num; - fsdev->nd_next_seg_num = new; - } - DPRINTF(SYNC, ("%s: new segment %jx next %jx error %d\n", - __func__, (uintmax_t)fsdev->nd_seg_num, (uintmax_t)new, error)); - if (error) - nandfs_error("%s: cannot create segment error %d\n", - __func__, error); - - return (error); -} - -static int -create_segment(struct nandfs_seginfo *seginfo) -{ - struct nandfs_segment *seg; - struct nandfs_device *fsdev; - struct nandfs_segment *prev; - struct buf *bp; - uint64_t start_block, curr; - uint32_t blks_per_seg, nblocks; - int error; - - fsdev = seginfo->fsdev; - prev = seginfo->curseg; - blks_per_seg = fsdev->nd_fsdata.f_blocks_per_segment; - nblocks = fsdev->nd_last_segsum.ss_nblocks; - - if (!prev) { - vfs_timestamp(&fsdev->nd_ts); - /* Touch current segment */ - error = nandfs_touch_segment(fsdev, fsdev->nd_seg_num); - if (error) { - nandfs_error("%s: cannot preallocate segment %jx\n", - __func__, fsdev->nd_seg_num); - return (error); - } - error = nandfs_touch_segment(fsdev, 0); - if (error) { - nandfs_error("%s: cannot dirty block with segment 0\n", - __func__); - return (error); - } - start_block = fsdev->nd_last_pseg + (uint64_t)nblocks; - /* - * XXX Hack - */ - if (blks_per_seg - (start_block % blks_per_seg) - 1 == 0) - start_block++; - curr = nandfs_get_segnum_of_block(fsdev, start_block); - /* Allocate new segment if last one is full */ - if (fsdev->nd_seg_num != curr) { - error = nandfs_new_segment(fsdev); - if (error) { - nandfs_error("%s: cannot create new segment\n", - __func__); - return (error); - } - /* - * XXX Hack - */ - nandfs_get_segment_range(fsdev, fsdev->nd_seg_num, &start_block, NULL); - } - } else { - nandfs_get_segment_range(fsdev, fsdev->nd_next_seg_num, - &start_block, NULL); - - /* Touch current segment and allocate and touch new one */ - error = nandfs_new_segment(fsdev); - if (error) { - nandfs_error("%s: cannot create next segment\n", - __func__); - return (error); - } - - /* Reiterate in case new buf is dirty */ - seginfo->reiterate = 1; - } - - /* Allocate and initialize nandfs_segment structure */ - seg = malloc(sizeof(*seg), M_DEVBUF, M_WAITOK|M_ZERO); - TAILQ_INIT(&seg->segsum); - TAILQ_INIT(&seg->data); - seg->fsdev = fsdev; - seg->start_block = start_block; - seg->num_blocks = blks_per_seg - (start_block % blks_per_seg) - 1; - seg->seg_num = fsdev->nd_seg_num; - seg->seg_next = fsdev->nd_next_seg_num; - seg->segsum_blocks = 1; - seg->bytes_left = fsdev->nd_blocksize - - sizeof(struct nandfs_segment_summary); - seg->segsum_bytes = sizeof(struct nandfs_segment_summary); - - /* Allocate buffer for segment summary */ - bp = getblk(fsdev->nd_devvp, nandfs_block_to_dblock(fsdev, - seg->start_block), fsdev->nd_blocksize, 0, 0, 0); - bzero(bp->b_data, seginfo->fsdev->nd_blocksize); - bp->b_bufobj = &seginfo->fsdev->nd_devvp->v_bufobj; - bp->b_flags |= B_MANAGED; - - /* Add buffer to segment */ - TAILQ_INSERT_TAIL(&seg->segsum, bp, b_cluster.cluster_entry); - seg->current_off = bp->b_data + sizeof(struct nandfs_segment_summary); - - DPRINTF(SYNC, ("%s: seg %p : initial settings: start %#jx size :%#x\n", - __func__, seg, (uintmax_t)seg->start_block, seg->num_blocks)); - DPRINTF(SYNC, ("%s: seg->seg_num %#jx cno %#jx next %#jx\n", __func__, - (uintmax_t)seg->seg_num, (uintmax_t)(fsdev->nd_last_cno + 1), - (uintmax_t)seg->seg_next)); - - if (!prev) - LIST_INSERT_HEAD(&seginfo->seg_list, seg, seg_link); - else - LIST_INSERT_AFTER(prev, seg, seg_link); - - seginfo->curseg = seg; - - return (0); -} - -static int -delete_segment(struct nandfs_seginfo *seginfo) -{ - struct nandfs_segment *seg, *tseg; - struct buf *bp, *tbp; - - LIST_FOREACH_SAFE(seg, &seginfo->seg_list, seg_link, tseg) { - TAILQ_FOREACH_SAFE(bp, &seg->segsum, b_cluster.cluster_entry, - tbp) { - TAILQ_REMOVE(&seg->segsum, bp, b_cluster.cluster_entry); - bp->b_flags &= ~B_MANAGED; - brelse(bp); - } - - LIST_REMOVE(seg, seg_link); - free(seg, M_DEVBUF); - } - - return (0); -} - -static int -create_seginfo(struct nandfs_device *fsdev, struct nandfs_seginfo **seginfo) -{ - struct nandfs_seginfo *info; - - info = malloc(sizeof(*info), M_DEVBUF, M_WAITOK); - - LIST_INIT(&info->seg_list); - info->fsdev = fsdev; - info->curseg = NULL; - info->blocks = 0; - *seginfo = info; - fsdev->nd_seginfo = info; - return (0); -} - -static int -delete_seginfo(struct nandfs_seginfo *seginfo) -{ - struct nandfs_device *nffsdev; - - nffsdev = seginfo->fsdev; - delete_segment(seginfo); - nffsdev->nd_seginfo = NULL; - free(seginfo, M_DEVBUF); - - return (0); -} - -static int -nandfs_create_superroot_block(struct nandfs_seginfo *seginfo, - struct buf **newbp) -{ - struct buf *bp; - int error; - - bp = nandfs_geteblk(seginfo->fsdev->nd_blocksize, GB_NOWAIT_BD); - - bzero(bp->b_data, seginfo->fsdev->nd_blocksize); - bp->b_bufobj = &seginfo->fsdev->nd_devvp->v_bufobj; - bp->b_flags |= B_MANAGED; - - if (!(seginfo->curseg) || !seginfo->curseg->num_blocks) { - error = create_segment(seginfo); - if (error) { - brelse(bp); - nandfs_error("%s: no segment for superroot\n", - __func__); - return (error); - } - } - - TAILQ_INSERT_TAIL(&seginfo->curseg->data, bp, b_cluster.cluster_entry); - - seginfo->curseg->nblocks++; - seginfo->curseg->num_blocks--; - seginfo->blocks++; - - *newbp = bp; - return (0); -} - -static int -nandfs_add_superroot(struct nandfs_seginfo *seginfo) -{ - struct nandfs_device *fsdev; - struct nandfs_super_root *sr; - struct buf *bp = NULL; - uint64_t crc_skip; - uint32_t crc_calc; - int error; - - fsdev = seginfo->fsdev; - - error = nandfs_create_superroot_block(seginfo, &bp); - if (error) { - nandfs_error("%s: cannot add superroot\n", __func__); - return (error); - } - - sr = (struct nandfs_super_root *)bp->b_data; - /* Save superroot CRC */ - sr->sr_bytes = NANDFS_SR_BYTES; - sr->sr_flags = 0; - sr->sr_nongc_ctime = 0; - - memcpy(&sr->sr_dat, &fsdev->nd_dat_node->nn_inode, - sizeof(struct nandfs_inode)); - memcpy(&sr->sr_cpfile, &fsdev->nd_cp_node->nn_inode, - sizeof(struct nandfs_inode)); - memcpy(&sr->sr_sufile, &fsdev->nd_su_node->nn_inode, - sizeof(struct nandfs_inode)); - - crc_skip = sizeof(sr->sr_sum); - crc_calc = crc32((uint8_t *)sr + crc_skip, NANDFS_SR_BYTES - crc_skip); - - sr->sr_sum = crc_calc; - - bp->b_flags |= B_MANAGED; - bp->b_bufobj = &seginfo->fsdev->nd_devvp->v_bufobj; - - bp->b_flags &= ~B_INVAL; - nandfs_dirty_bufs_increment(fsdev); - DPRINTF(SYNC, ("%s: bp:%p\n", __func__, bp)); - - return (0); -} - -static int -nandfs_add_segsum_block(struct nandfs_seginfo *seginfo, struct buf **newbp) -{ - struct nandfs_device *fsdev; - nandfs_daddr_t blk; - struct buf *bp; - int error; - - if (!(seginfo->curseg) || seginfo->curseg->num_blocks <= 1) { - error = create_segment(seginfo); - if (error) { - nandfs_error("%s: error:%d when creating segment\n", - __func__, error); - return (error); - } - *newbp = TAILQ_FIRST(&seginfo->curseg->segsum); - return (0); - } - - fsdev = seginfo->fsdev; - blk = nandfs_block_to_dblock(fsdev, seginfo->curseg->start_block + - seginfo->curseg->segsum_blocks); - - bp = getblk(fsdev->nd_devvp, blk, fsdev->nd_blocksize, 0, 0, 0); - - bzero(bp->b_data, seginfo->fsdev->nd_blocksize); - bp->b_bufobj = &seginfo->fsdev->nd_devvp->v_bufobj; - bp->b_flags |= B_MANAGED; - - TAILQ_INSERT_TAIL(&seginfo->curseg->segsum, bp, - b_cluster.cluster_entry); - seginfo->curseg->num_blocks--; - - seginfo->curseg->segsum_blocks++; - seginfo->curseg->bytes_left = seginfo->fsdev->nd_blocksize; - seginfo->curseg->current_off = bp->b_data; - seginfo->blocks++; - - *newbp = bp; - - DPRINTF(SYNC, ("%s: bp %p\n", __func__, bp)); - - return (0); -} - -static int -nandfs_add_blocks(struct nandfs_seginfo *seginfo, struct nandfs_node *node, - struct buf *bp) -{ - union nandfs_binfo *binfo; - struct buf *seg_bp; - int error; - - if (!(seginfo->curseg) || !seginfo->curseg->num_blocks) { - error = create_segment(seginfo); - if (error) { - nandfs_error("%s: error:%d when creating segment\n", - __func__, error); - return (error); - } - } - - if (seginfo->curseg->bytes_left < sizeof(union nandfs_binfo)) { - error = nandfs_add_segsum_block(seginfo, &seg_bp); - if (error) { - nandfs_error("%s: error:%d when adding segsum\n", - __func__, error); - return (error); - } - } - binfo = (union nandfs_binfo *)seginfo->curseg->current_off; - - if (node->nn_ino != NANDFS_DAT_INO) { - binfo->bi_v.bi_blkoff = bp->b_lblkno; - binfo->bi_v.bi_ino = node->nn_ino; - } else { - binfo->bi_dat.bi_blkoff = bp->b_lblkno; - binfo->bi_dat.bi_ino = node->nn_ino; - if (NANDFS_IS_INDIRECT(bp)) - binfo->bi_dat.bi_level = 1; - else - binfo->bi_dat.bi_level = 0; - } - binfo++; - - seginfo->curseg->bytes_left -= sizeof(union nandfs_binfo); - seginfo->curseg->segsum_bytes += sizeof(union nandfs_binfo); - seginfo->curseg->current_off = (char *)binfo; - - TAILQ_INSERT_TAIL(&seginfo->curseg->data, bp, b_cluster.cluster_entry); - - seginfo->curseg->nbinfos++; - seginfo->curseg->nblocks++; - seginfo->curseg->num_blocks--; - seginfo->blocks++; - - DPRINTF(SYNC, ("%s: bp (%p) number %x (left %x)\n", - __func__, bp, seginfo->curseg->nblocks, - seginfo->curseg->num_blocks)); - return (0); -} - -static int -nandfs_iterate_dirty_buf(struct vnode *vp, struct nandfs_seginfo *seginfo, - uint8_t hold) -{ - struct buf *bp, *tbd; - struct bufobj *bo; - struct nandfs_node *node; - int error; - - node = VTON(vp); - bo = &vp->v_bufobj; - - ASSERT_VOP_ELOCKED(vp, __func__); - - /* Iterate dirty data bufs */ - TAILQ_FOREACH_SAFE(bp, &bo->bo_dirty.bv_hd, b_bobufs, tbd) { - DPRINTF(SYNC, ("%s: vp (%p): bp (%p) with lblkno %jx ino %jx " - "add buf\n", __func__, vp, bp, bp->b_lblkno, node->nn_ino)); - - if (!(NANDFS_ISGATHERED(bp))) { - error = nandfs_bmap_update_dat(node, - nandfs_vblk_get(bp), bp); - if (error) - return (error); - NANDFS_GATHER(bp); - nandfs_add_blocks(seginfo, node, bp); - } - } - - return (0); -} - -static int -nandfs_iterate_system_vnode(struct nandfs_node *node, - struct nandfs_seginfo *seginfo) -{ - struct vnode *vp; - int nblocks; - uint8_t hold = 0; - - if (node->nn_ino != NANDFS_IFILE_INO) - hold = 1; - - vp = NTOV(node); - - nblocks = vp->v_bufobj.bo_dirty.bv_cnt; - DPRINTF(SYNC, ("%s: vp (%p): nblocks %x ino %jx\n", - __func__, vp, nblocks, node->nn_ino)); - - if (nblocks) - nandfs_iterate_dirty_buf(vp, seginfo, hold); - - return (0); -} - -static int -nandfs_iterate_dirty_vnodes(struct mount *mp, struct nandfs_seginfo *seginfo) -{ - struct nandfs_node *nandfs_node; - struct vnode *vp, *mvp; - struct thread *td; - struct bufobj *bo; - int error, update; - - td = curthread; - - MNT_VNODE_FOREACH_ACTIVE(vp, mp, mvp) { - update = 0; - - if (mp->mnt_syncer == vp || VOP_ISLOCKED(vp)) { - VI_UNLOCK(vp); - continue; - } - if (vget(vp, LK_EXCLUSIVE | LK_INTERLOCK | LK_NOWAIT, td) != 0) - continue; - - nandfs_node = VTON(vp); - if (nandfs_node->nn_flags & IN_MODIFIED) { - nandfs_node->nn_flags &= ~(IN_MODIFIED); - update = 1; - } - - bo = &vp->v_bufobj; - BO_LOCK(bo); - if (vp->v_bufobj.bo_dirty.bv_cnt) { - error = nandfs_iterate_dirty_buf(vp, seginfo, 0); - if (error) { - nandfs_error("%s: cannot iterate vnode:%p " - "err:%d\n", __func__, vp, error); - vput(vp); - BO_UNLOCK(bo); - return (error); - } - update = 1; - } else - vput(vp); - BO_UNLOCK(bo); - - if (update) - nandfs_node_update(nandfs_node); - } - - return (0); -} - -static int -nandfs_update_phys_block(struct nandfs_device *fsdev, struct buf *bp, - uint64_t phys_blknr, union nandfs_binfo *binfo) -{ - struct nandfs_node *node, *dat; - struct vnode *vp; - uint64_t new_blknr; - int error; - - vp = bp->b_vp; - node = VTON(vp); - new_blknr = nandfs_vblk_get(bp); - dat = fsdev->nd_dat_node; - - DPRINTF(BMAP, ("%s: ino %#jx lblk %#jx: vblk %#jx -> %#jx\n", - __func__, (uintmax_t)node->nn_ino, (uintmax_t)bp->b_lblkno, - (uintmax_t)new_blknr, (uintmax_t)phys_blknr)); - - if (node->nn_ino != NANDFS_DAT_INO) { - KASSERT((new_blknr != 0), ("vblk for bp %p is 0", bp)); - - nandfs_vblock_assign(fsdev, new_blknr, phys_blknr); - binfo->bi_v.bi_vblocknr = new_blknr; - binfo->bi_v.bi_blkoff = bp->b_lblkno; - binfo->bi_v.bi_ino = node->nn_ino; - } else { - VOP_LOCK(NTOV(dat), LK_EXCLUSIVE); - error = nandfs_bmap_update_block(node, bp, phys_blknr); - if (error) { - nandfs_error("%s: error updating block:%jx for bp:%p\n", - __func__, (uintmax_t)phys_blknr, bp); - VOP_UNLOCK(NTOV(dat), 0); - return (error); - } - VOP_UNLOCK(NTOV(dat), 0); - binfo->bi_dat.bi_blkoff = bp->b_lblkno; - binfo->bi_dat.bi_ino = node->nn_ino; - if (NANDFS_IS_INDIRECT(bp)) - binfo->bi_dat.bi_level = 1; - else - binfo->bi_dat.bi_level = 0; - } - - return (0); -} - -#define NBINFO(off) ((off) + sizeof(union nandfs_binfo)) -static int -nandfs_segment_assign_pblk(struct nandfs_segment *nfsseg) -{ - struct nandfs_device *fsdev; - union nandfs_binfo *binfo; - struct buf *bp, *seg_bp; - uint64_t blocknr; - uint32_t curr_off, blocksize; - int error; - - fsdev = nfsseg->fsdev; - blocksize = fsdev->nd_blocksize; - - blocknr = nfsseg->start_block + nfsseg->segsum_blocks; - seg_bp = TAILQ_FIRST(&nfsseg->segsum); - DPRINTF(SYNC, ("%s: seg:%p segsum bp:%p data:%p\n", - __func__, nfsseg, seg_bp, seg_bp->b_data)); - - binfo = (union nandfs_binfo *)(seg_bp->b_data + - sizeof(struct nandfs_segment_summary)); - curr_off = sizeof(struct nandfs_segment_summary); - - TAILQ_FOREACH(bp, &nfsseg->data, b_cluster.cluster_entry) { - KASSERT((bp->b_vp), ("bp %p has not vp", bp)); - - DPRINTF(BMAP, ("\n\n%s: assign buf %p for ino %#jx next %p\n", - __func__, bp, (uintmax_t)VTON(bp->b_vp)->nn_ino, - TAILQ_NEXT(bp, b_cluster.cluster_entry))); - - if (NBINFO(curr_off) > blocksize) { - seg_bp = TAILQ_NEXT(seg_bp, b_cluster.cluster_entry); - binfo = (union nandfs_binfo *)seg_bp->b_data; - curr_off = 0; - DPRINTF(SYNC, ("%s: next segsum %p data %p\n", - __func__, seg_bp, seg_bp->b_data)); - } - - error = nandfs_update_phys_block(fsdev, bp, blocknr, binfo); - if (error) { - nandfs_error("%s: err:%d when updatinng phys block:%jx" - " for bp:%p and binfo:%p\n", __func__, error, - (uintmax_t)blocknr, bp, binfo); - return (error); - } - binfo++; - curr_off = NBINFO(curr_off); - - blocknr++; - } - - return (0); -} - -static int -nandfs_seginfo_assign_pblk(struct nandfs_seginfo *seginfo) -{ - struct nandfs_segment *nfsseg; - int error = 0; - - LIST_FOREACH(nfsseg, &seginfo->seg_list, seg_link) { - error = nandfs_segment_assign_pblk(nfsseg); - if (error) - break; - } - - return (error); -} - -static struct nandfs_segment_summary * -nandfs_fill_segsum(struct nandfs_segment *seg, int has_sr) -{ - struct nandfs_segment_summary *ss; - struct nandfs_device *fsdev; - struct buf *bp; - uint32_t rest, segsum_size, blocksize, crc_calc; - uint16_t flags; - uint8_t *crc_area, crc_skip; - - DPRINTF(SYNC, ("%s: seg %#jx nblocks %#x sumbytes %#x\n", - __func__, (uintmax_t) seg->seg_num, - seg->nblocks + seg->segsum_blocks, - seg->segsum_bytes)); - - fsdev = seg->fsdev; - - flags = NANDFS_SS_LOGBGN | NANDFS_SS_LOGEND; - if (has_sr) - flags |= NANDFS_SS_SR; - - bp = TAILQ_FIRST(&seg->segsum); - ss = (struct nandfs_segment_summary *) bp->b_data; - ss->ss_magic = NANDFS_SEGSUM_MAGIC; - ss->ss_bytes = sizeof(struct nandfs_segment_summary); - ss->ss_flags = flags; - ss->ss_seq = ++(fsdev->nd_seg_sequence); - ss->ss_create = fsdev->nd_ts.tv_sec; - nandfs_get_segment_range(fsdev, seg->seg_next, &ss->ss_next, NULL); - ss->ss_nblocks = seg->nblocks + seg->segsum_blocks; - ss->ss_nbinfos = seg->nbinfos; - ss->ss_sumbytes = seg->segsum_bytes; - - crc_skip = sizeof(ss->ss_datasum) + sizeof(ss->ss_sumsum); - blocksize = seg->fsdev->nd_blocksize; - - segsum_size = seg->segsum_bytes - crc_skip; - rest = min(seg->segsum_bytes, blocksize) - crc_skip; - crc_area = (uint8_t *)ss + crc_skip; - crc_calc = ~0U; - while (segsum_size > 0) { - crc_calc = crc32_raw(crc_area, rest, crc_calc); - segsum_size -= rest; - if (!segsum_size) - break; - bp = TAILQ_NEXT(bp, b_cluster.cluster_entry); - crc_area = (uint8_t *)bp->b_data; - rest = segsum_size <= blocksize ? segsum_size : blocksize; - } - ss->ss_sumsum = crc_calc ^ ~0U; - - return (ss); - -} - -static int -nandfs_save_buf(struct buf *bp, uint64_t blocknr, struct nandfs_device *fsdev) -{ - struct bufobj *bo; - int error; - - bo = &fsdev->nd_devvp->v_bufobj; - - bp->b_blkno = nandfs_block_to_dblock(fsdev, blocknr); - bp->b_iooffset = dbtob(bp->b_blkno); - - KASSERT(bp->b_bufobj != NULL, ("no bufobj for %p", bp)); - if (bp->b_bufobj != bo) { - BO_LOCK(bp->b_bufobj); - BUF_LOCK(bp, LK_EXCLUSIVE | LK_NOWAIT | LK_INTERLOCK, - BO_LOCKPTR(bp->b_bufobj)); - KASSERT(BUF_ISLOCKED(bp), ("Problem with locking buffer")); - } - - DPRINTF(SYNC, ("%s: buf: %p offset %#jx blk %#jx size %#x\n", - __func__, bp, (uintmax_t)bp->b_offset, (uintmax_t)blocknr, - fsdev->nd_blocksize)); - - NANDFS_UNGATHER(bp); - nandfs_buf_clear(bp, 0xffffffff); - bp->b_flags &= ~(B_ASYNC|B_INVAL|B_MANAGED); - error = bwrite(bp); - if (error) { - nandfs_error("%s: error:%d when writing buffer:%p\n", - __func__, error, bp); - return (error); - } - return (error); -} - -static void -nandfs_clean_buf(struct nandfs_device *fsdev, struct buf *bp) -{ - - DPRINTF(SYNC, ("%s: buf: %p\n", __func__, bp)); - - NANDFS_UNGATHER(bp); - nandfs_buf_clear(bp, 0xffffffff); - bp->b_flags &= ~(B_ASYNC|B_INVAL|B_MANAGED); - nandfs_undirty_buf_fsdev(fsdev, bp); -} - -static void -nandfs_clean_segblocks(struct nandfs_segment *seg, uint8_t unlock) -{ - struct nandfs_device *fsdev = seg->fsdev; - struct nandfs_segment *next_seg; - struct buf *bp, *tbp, *next_bp; - struct vnode *vp, *next_vp; - - VOP_LOCK(fsdev->nd_devvp, LK_EXCLUSIVE); - TAILQ_FOREACH_SAFE(bp, &seg->segsum, b_cluster.cluster_entry, tbp) { - TAILQ_REMOVE(&seg->segsum, bp, b_cluster.cluster_entry); - nandfs_clean_buf(fsdev, bp); - } - - TAILQ_FOREACH_SAFE(bp, &seg->data, b_cluster.cluster_entry, tbp) { - TAILQ_REMOVE(&seg->data, bp, b_cluster.cluster_entry); - - /* - * If bp is not super-root and vnode is not currently - * locked lock it. - */ - vp = bp->b_vp; - next_vp = NULL; - next_bp = TAILQ_NEXT(bp, b_cluster.cluster_entry); - if (!next_bp) { - next_seg = LIST_NEXT(seg, seg_link); - if (next_seg) - next_bp = TAILQ_FIRST(&next_seg->data); - } - - if (next_bp) - next_vp = next_bp->b_vp; - - nandfs_clean_buf(fsdev, bp); - - if (unlock && vp != NULL && next_vp != vp && - !NANDFS_SYS_NODE(VTON(vp)->nn_ino)) - vput(vp); - - nandfs_dirty_bufs_decrement(fsdev); - } - - VOP_UNLOCK(fsdev->nd_devvp, 0); -} - -static int -nandfs_save_segblocks(struct nandfs_segment *seg, uint8_t unlock) -{ - struct nandfs_device *fsdev = seg->fsdev; - struct nandfs_segment *next_seg; - struct buf *bp, *tbp, *next_bp; - struct vnode *vp, *next_vp; - uint64_t blocknr; - uint32_t i = 0; - int error = 0; - - VOP_LOCK(fsdev->nd_devvp, LK_EXCLUSIVE); - TAILQ_FOREACH_SAFE(bp, &seg->segsum, b_cluster.cluster_entry, tbp) { - TAILQ_REMOVE(&seg->segsum, bp, b_cluster.cluster_entry); - blocknr = seg->start_block + i; - error = nandfs_save_buf(bp, blocknr, fsdev); - if (error) { - nandfs_error("%s: error saving buf: %p blocknr:%jx\n", - __func__, bp, (uintmax_t)blocknr); - goto out; - } - i++; - } - - i = 0; - TAILQ_FOREACH_SAFE(bp, &seg->data, b_cluster.cluster_entry, tbp) { - TAILQ_REMOVE(&seg->data, bp, b_cluster.cluster_entry); - - blocknr = seg->start_block + seg->segsum_blocks + i; - /* - * If bp is not super-root and vnode is not currently - * locked lock it. - */ - vp = bp->b_vp; - next_vp = NULL; - next_bp = TAILQ_NEXT(bp, b_cluster.cluster_entry); - if (!next_bp) { - next_seg = LIST_NEXT(seg, seg_link); - if (next_seg) - next_bp = TAILQ_FIRST(&next_seg->data); - } - - if (next_bp) - next_vp = next_bp->b_vp; - - error = nandfs_save_buf(bp, blocknr, fsdev); - if (error) { - nandfs_error("%s: error saving buf: %p blknr: %jx\n", - __func__, bp, (uintmax_t)blocknr); - if (unlock && vp != NULL && next_vp != vp && - !NANDFS_SYS_NODE(VTON(vp)->nn_ino)) - vput(vp); - goto out; - } - - if (unlock && vp != NULL && next_vp != vp && - !NANDFS_SYS_NODE(VTON(vp)->nn_ino)) - vput(vp); - - i++; - nandfs_dirty_bufs_decrement(fsdev); - } -out: - if (error) { - nandfs_clean_segblocks(seg, unlock); - VOP_UNLOCK(fsdev->nd_devvp, 0); - return (error); - } - - VOP_UNLOCK(fsdev->nd_devvp, 0); - return (error); -} - - -static void -clean_seginfo(struct nandfs_seginfo *seginfo, uint8_t unlock) -{ - struct nandfs_segment *seg; - - DPRINTF(SYNC, ("%s: seginfo %p\n", __func__, seginfo)); - - LIST_FOREACH(seg, &seginfo->seg_list, seg_link) { - nandfs_clean_segblocks(seg, unlock); - } -} - -static int -save_seginfo(struct nandfs_seginfo *seginfo, uint8_t unlock) -{ - struct nandfs_segment *seg; - struct nandfs_device *fsdev; - struct nandfs_segment_summary *ss; - int error = 0; - - fsdev = seginfo->fsdev; - - DPRINTF(SYNC, ("%s: seginfo %p\n", __func__, seginfo)); - - LIST_FOREACH(seg, &seginfo->seg_list, seg_link) { - if (LIST_NEXT(seg, seg_link)) { - nandfs_fill_segsum(seg, 0); - error = nandfs_save_segblocks(seg, unlock); - if (error) { - nandfs_error("%s: error:%d saving seg:%p\n", - __func__, error, seg); - goto out; - } - } else { - ss = nandfs_fill_segsum(seg, 1); - fsdev->nd_last_segsum = *ss; - error = nandfs_save_segblocks(seg, unlock); - if (error) { - nandfs_error("%s: error:%d saving seg:%p\n", - __func__, error, seg); - goto out; - } - fsdev->nd_last_cno++; - fsdev->nd_last_pseg = seg->start_block; - } - } -out: - if (error) - clean_seginfo(seginfo, unlock); - return (error); -} - -static void -nandfs_invalidate_bufs(struct nandfs_device *fsdev, uint64_t segno) -{ - uint64_t start, end; - struct buf *bp, *tbd; - struct bufobj *bo; - - nandfs_get_segment_range(fsdev, segno, &start, &end); - - bo = &NTOV(fsdev->nd_gc_node)->v_bufobj; - - BO_LOCK(bo); -restart_locked_gc: - TAILQ_FOREACH_SAFE(bp, &bo->bo_clean.bv_hd, b_bobufs, tbd) { - if (!(bp->b_lblkno >= start && bp->b_lblkno <= end)) - continue; - - if (BUF_LOCK(bp, LK_EXCLUSIVE | LK_NOWAIT, NULL)) - goto restart_locked_gc; - - bremfree(bp); - bp->b_flags |= (B_INVAL | B_RELBUF); - bp->b_flags &= ~(B_ASYNC | B_MANAGED); - BO_UNLOCK(bo); - brelse(bp); - BO_LOCK(bo); - } - BO_UNLOCK(bo); -} - -/* Process segments marks to free by cleaner */ -static void -nandfs_process_segments(struct nandfs_device *fsdev) -{ - uint64_t saved_segment; - int i; - - if (fsdev->nd_free_base) { - saved_segment = nandfs_get_segnum_of_block(fsdev, - fsdev->nd_super.s_last_pseg); - for (i = 0; i < fsdev->nd_free_count; i++) { - if (fsdev->nd_free_base[i] == NANDFS_NOSEGMENT) - continue; - /* Update superblock if clearing segment point by it */ - if (fsdev->nd_free_base[i] == saved_segment) { - nandfs_write_superblock(fsdev); - saved_segment = nandfs_get_segnum_of_block( - fsdev, fsdev->nd_super.s_last_pseg); - } - nandfs_invalidate_bufs(fsdev, fsdev->nd_free_base[i]); - nandfs_clear_segment(fsdev, fsdev->nd_free_base[i]); - } - - free(fsdev->nd_free_base, M_NANDFSTEMP); - fsdev->nd_free_base = NULL; - fsdev->nd_free_count = 0; - } -} - -/* Collect and write dirty buffers */ -int -nandfs_sync_file(struct vnode *vp) -{ - struct nandfs_device *fsdev; - struct nandfs_node *nandfs_node; - struct nandfsmount *nmp; - struct nandfs_node *dat, *su, *ifile, *cp; - struct nandfs_seginfo *seginfo = NULL; - struct nandfs_segment *seg; - int update, error; - int cno_changed; - - ASSERT_VOP_LOCKED(vp, __func__); - DPRINTF(SYNC, ("%s: START\n", __func__)); - - error = 0; - nmp = VFSTONANDFS(vp->v_mount); - fsdev = nmp->nm_nandfsdev; - - dat = fsdev->nd_dat_node; - su = fsdev->nd_su_node; - cp = fsdev->nd_cp_node; - ifile = nmp->nm_ifile_node; - - NANDFS_WRITEASSERT(fsdev); - if (lockmgr(&fsdev->nd_seg_const, LK_UPGRADE, NULL) != 0) { - DPRINTF(SYNC, ("%s: lost shared lock\n", __func__)); - if (lockmgr(&fsdev->nd_seg_const, LK_EXCLUSIVE, NULL) != 0) - panic("couldn't lock exclusive"); - } - DPRINTF(SYNC, ("%s: got lock\n", __func__)); - - VOP_LOCK(NTOV(su), LK_EXCLUSIVE); - create_seginfo(fsdev, &seginfo); - - update = 0; - - nandfs_node = VTON(vp); - if (nandfs_node->nn_flags & IN_MODIFIED) { - nandfs_node->nn_flags &= ~(IN_MODIFIED); - update = 1; - } - - if (vp->v_bufobj.bo_dirty.bv_cnt) { - error = nandfs_iterate_dirty_buf(vp, seginfo, 0); - if (error) { - clean_seginfo(seginfo, 0); - delete_seginfo(seginfo); - VOP_UNLOCK(NTOV(su), 0); - lockmgr(&fsdev->nd_seg_const, LK_DOWNGRADE, NULL); - nandfs_error("%s: err:%d iterating dirty bufs vp:%p", - __func__, error, vp); - return (error); - } - update = 1; - } - - if (update) { - VOP_LOCK(NTOV(ifile), LK_EXCLUSIVE); - error = nandfs_node_update(nandfs_node); - if (error) { - clean_seginfo(seginfo, 0); - delete_seginfo(seginfo); - VOP_UNLOCK(NTOV(ifile), 0); - VOP_UNLOCK(NTOV(su), 0); - lockmgr(&fsdev->nd_seg_const, LK_DOWNGRADE, NULL); - nandfs_error("%s: err:%d updating vp:%p", - __func__, error, vp); - return (error); - } - VOP_UNLOCK(NTOV(ifile), 0); - } - - cno_changed = 0; - if (seginfo->blocks) { - VOP_LOCK(NTOV(cp), LK_EXCLUSIVE); - cno_changed = 1; - /* Create new checkpoint */ - error = nandfs_get_checkpoint(fsdev, cp, fsdev->nd_last_cno + 1); - if (error) { - clean_seginfo(seginfo, 0); - delete_seginfo(seginfo); - VOP_UNLOCK(NTOV(cp), 0); - VOP_UNLOCK(NTOV(su), 0); - lockmgr(&fsdev->nd_seg_const, LK_DOWNGRADE, NULL); - nandfs_error("%s: err:%d getting cp:%jx", - __func__, error, fsdev->nd_last_cno + 1); - return (error); - } - - /* Reiterate all blocks and assign physical block number */ - nandfs_seginfo_assign_pblk(seginfo); - - /* Fill checkpoint data */ - error = nandfs_set_checkpoint(fsdev, cp, fsdev->nd_last_cno + 1, - &ifile->nn_inode, seginfo->blocks); - if (error) { - clean_seginfo(seginfo, 0); - delete_seginfo(seginfo); - VOP_UNLOCK(NTOV(cp), 0); - VOP_UNLOCK(NTOV(su), 0); - lockmgr(&fsdev->nd_seg_const, LK_DOWNGRADE, NULL); - nandfs_error("%s: err:%d setting cp:%jx", - __func__, error, fsdev->nd_last_cno + 1); - return (error); - } - - VOP_UNLOCK(NTOV(cp), 0); - LIST_FOREACH(seg, &seginfo->seg_list, seg_link) - nandfs_update_segment(fsdev, seg->seg_num, - seg->nblocks + seg->segsum_blocks); - - VOP_LOCK(NTOV(dat), LK_EXCLUSIVE); - error = save_seginfo(seginfo, 0); - if (error) { - clean_seginfo(seginfo, 0); - delete_seginfo(seginfo); - VOP_UNLOCK(NTOV(dat), 0); - VOP_UNLOCK(NTOV(su), 0); - lockmgr(&fsdev->nd_seg_const, LK_DOWNGRADE, NULL); - nandfs_error("%s: err:%d updating seg", - __func__, error); - return (error); - } - VOP_UNLOCK(NTOV(dat), 0); - } - - VOP_UNLOCK(NTOV(su), 0); - - delete_seginfo(seginfo); - lockmgr(&fsdev->nd_seg_const, LK_DOWNGRADE, NULL); - - if (cno_changed && !error) { - if (nandfs_cps_between_sblocks != 0 && - fsdev->nd_last_cno % nandfs_cps_between_sblocks == 0) - nandfs_write_superblock(fsdev); - } - - ASSERT_VOP_LOCKED(vp, __func__); - DPRINTF(SYNC, ("%s: END error %d\n", __func__, error)); - return (error); -} - -int -nandfs_segment_constructor(struct nandfsmount *nmp, int flags) -{ - struct nandfs_device *fsdev; - struct nandfs_seginfo *seginfo = NULL; - struct nandfs_segment *seg; - struct nandfs_node *dat, *su, *ifile, *cp, *gc; - int cno_changed, error; - - DPRINTF(SYNC, ("%s: START\n", __func__)); - fsdev = nmp->nm_nandfsdev; - - lockmgr(&fsdev->nd_seg_const, LK_EXCLUSIVE, NULL); - DPRINTF(SYNC, ("%s: git lock\n", __func__)); -again: - create_seginfo(fsdev, &seginfo); - - dat = fsdev->nd_dat_node; - su = fsdev->nd_su_node; - cp = fsdev->nd_cp_node; - gc = fsdev->nd_gc_node; - ifile = nmp->nm_ifile_node; - - VOP_LOCK(NTOV(su), LK_EXCLUSIVE); - VOP_LOCK(NTOV(ifile), LK_EXCLUSIVE); - VOP_LOCK(NTOV(gc), LK_EXCLUSIVE); - VOP_LOCK(NTOV(cp), LK_EXCLUSIVE); - - nandfs_iterate_system_vnode(gc, seginfo); - nandfs_iterate_dirty_vnodes(nmp->nm_vfs_mountp, seginfo); - nandfs_iterate_system_vnode(ifile, seginfo); - nandfs_iterate_system_vnode(su, seginfo); - - cno_changed = 0; - if (seginfo->blocks || flags) { - cno_changed = 1; - /* Create new checkpoint */ - error = nandfs_get_checkpoint(fsdev, cp, fsdev->nd_last_cno + 1); - if (error) { - clean_seginfo(seginfo, 0); - delete_seginfo(seginfo); - goto error_locks; - } - - /* Collect blocks from system files */ - nandfs_iterate_system_vnode(cp, seginfo); - nandfs_iterate_system_vnode(su, seginfo); - VOP_LOCK(NTOV(dat), LK_EXCLUSIVE); - nandfs_iterate_system_vnode(dat, seginfo); - VOP_UNLOCK(NTOV(dat), 0); -reiterate: - seginfo->reiterate = 0; - nandfs_iterate_system_vnode(su, seginfo); - VOP_LOCK(NTOV(dat), LK_EXCLUSIVE); - nandfs_iterate_system_vnode(dat, seginfo); - VOP_UNLOCK(NTOV(dat), 0); - if (seginfo->reiterate) - goto reiterate; - if (!(seginfo->curseg) || !seginfo->curseg->num_blocks) { - error = create_segment(seginfo); - if (error) { - clean_seginfo(seginfo, 0); - delete_seginfo(seginfo); - goto error_locks; - } - goto reiterate; - } - - /* Reiterate all blocks and assign physical block number */ - nandfs_seginfo_assign_pblk(seginfo); - - /* Fill superroot */ - error = nandfs_add_superroot(seginfo); - if (error) { - clean_seginfo(seginfo, 0); - delete_seginfo(seginfo); - goto error_locks; - } - KASSERT(!(seginfo->reiterate), ("reiteration after superroot")); - - /* Fill checkpoint data */ - nandfs_set_checkpoint(fsdev, cp, fsdev->nd_last_cno + 1, - &ifile->nn_inode, seginfo->blocks); - - LIST_FOREACH(seg, &seginfo->seg_list, seg_link) - nandfs_update_segment(fsdev, seg->seg_num, - seg->nblocks + seg->segsum_blocks); - - VOP_LOCK(NTOV(dat), LK_EXCLUSIVE); - error = save_seginfo(seginfo, 1); - if (error) { - clean_seginfo(seginfo, 1); - delete_seginfo(seginfo); - goto error_dat; - } - VOP_UNLOCK(NTOV(dat), 0); - } - - VOP_UNLOCK(NTOV(cp), 0); - VOP_UNLOCK(NTOV(gc), 0); - VOP_UNLOCK(NTOV(ifile), 0); - - nandfs_process_segments(fsdev); - - VOP_UNLOCK(NTOV(su), 0); - - delete_seginfo(seginfo); - - /* - * XXX: a hack, will go away soon - */ - if ((NTOV(dat)->v_bufobj.bo_dirty.bv_cnt != 0 || - NTOV(cp)->v_bufobj.bo_dirty.bv_cnt != 0 || - NTOV(gc)->v_bufobj.bo_dirty.bv_cnt != 0 || - NTOV(ifile)->v_bufobj.bo_dirty.bv_cnt != 0 || - NTOV(su)->v_bufobj.bo_dirty.bv_cnt != 0) && - (flags & NANDFS_UMOUNT)) { - DPRINTF(SYNC, ("%s: RERUN\n", __func__)); - goto again; - } - - MPASS(fsdev->nd_free_base == NULL); - - lockmgr(&fsdev->nd_seg_const, LK_RELEASE, NULL); - - if (cno_changed) { - if ((nandfs_cps_between_sblocks != 0 && - fsdev->nd_last_cno % nandfs_cps_between_sblocks == 0) || - flags & NANDFS_UMOUNT) - nandfs_write_superblock(fsdev); - } - - DPRINTF(SYNC, ("%s: END\n", __func__)); - return (0); -error_dat: - VOP_UNLOCK(NTOV(dat), 0); -error_locks: - VOP_UNLOCK(NTOV(cp), 0); - VOP_UNLOCK(NTOV(gc), 0); - VOP_UNLOCK(NTOV(ifile), 0); - VOP_UNLOCK(NTOV(su), 0); - lockmgr(&fsdev->nd_seg_const, LK_RELEASE, NULL); - - return (error); -} - -#ifdef DDB -/* - * Show details about the given NANDFS mount point. - */ -DB_SHOW_COMMAND(nandfs, db_show_nandfs) -{ - struct mount *mp; - struct nandfs_device *nffsdev; - struct nandfs_segment *seg; - struct nandfsmount *nmp; - struct buf *bp; - struct vnode *vp; - - if (!have_addr) { - db_printf("\nUsage: show nandfs \n"); - return; - } - - mp = (struct mount *)addr; - db_printf("%p %s on %s (%s)\n", mp, mp->mnt_stat.f_mntfromname, - mp->mnt_stat.f_mntonname, mp->mnt_stat.f_fstypename); - - - nmp = (struct nandfsmount *)(mp->mnt_data); - nffsdev = nmp->nm_nandfsdev; - db_printf("dev vnode:%p\n", nffsdev->nd_devvp); - db_printf("blocksize:%jx last cno:%jx last pseg:%jx seg num:%jx\n", - (uintmax_t)nffsdev->nd_blocksize, (uintmax_t)nffsdev->nd_last_cno, - (uintmax_t)nffsdev->nd_last_pseg, (uintmax_t)nffsdev->nd_seg_num); - db_printf("system nodes: dat:%p cp:%p su:%p ifile:%p gc:%p\n", - nffsdev->nd_dat_node, nffsdev->nd_cp_node, nffsdev->nd_su_node, - nmp->nm_ifile_node, nffsdev->nd_gc_node); - - if (nffsdev->nd_seginfo != NULL) { - LIST_FOREACH(seg, &nffsdev->nd_seginfo->seg_list, seg_link) { - db_printf("seg: %p\n", seg); - TAILQ_FOREACH(bp, &seg->segsum, - b_cluster.cluster_entry) - db_printf("segbp %p\n", bp); - TAILQ_FOREACH(bp, &seg->data, - b_cluster.cluster_entry) { - vp = bp->b_vp; - db_printf("bp:%p bp->b_vp:%p ino:%jx\n", bp, vp, - (uintmax_t)(vp ? VTON(vp)->nn_ino : 0)); - } - } - } -} -#endif diff --git a/sys/fs/nandfs/nandfs_subr.c b/sys/fs/nandfs/nandfs_subr.c deleted file mode 100644 index cd25ac044de..00000000000 --- a/sys/fs/nandfs/nandfs_subr.c +++ /dev/null @@ -1,1090 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2010-2012 Semihalf - * Copyright (c) 2008, 2009 Reinoud Zandijk - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * From: NetBSD: nilfs_subr.c,v 1.4 2009/07/29 17:06:57 reinoud - */ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include -#include - -#include -#include "nandfs_mount.h" -#include "nandfs.h" -#include "nandfs_subr.h" - -MALLOC_DEFINE(M_NANDFSMNT, "nandfs_mount", "NANDFS mount"); -MALLOC_DEFINE(M_NANDFSTEMP, "nandfs_tmt", "NANDFS tmp"); - -uma_zone_t nandfs_node_zone; - -void nandfs_bdflush(struct bufobj *bo, struct buf *bp); -int nandfs_bufsync(struct bufobj *bo, int waitfor); - -struct buf_ops buf_ops_nandfs = { - .bop_name = "buf_ops_nandfs", - .bop_write = bufwrite, - .bop_strategy = bufstrategy, - .bop_sync = nandfs_bufsync, - .bop_bdflush = nandfs_bdflush, -}; - -int -nandfs_bufsync(struct bufobj *bo, int waitfor) -{ - struct vnode *vp; - int error = 0; - - vp = bo2vnode(bo); - - ASSERT_VOP_LOCKED(vp, __func__); - error = nandfs_sync_file(vp); - if (error) - nandfs_warning("%s: cannot flush buffers err:%d\n", - __func__, error); - - return (error); -} - -void -nandfs_bdflush(bo, bp) - struct bufobj *bo; - struct buf *bp; -{ - struct vnode *vp; - int error; - - if (bo->bo_dirty.bv_cnt <= ((dirtybufthresh * 8) / 10)) - return; - - vp = bp->b_vp; - if (NANDFS_SYS_NODE(VTON(vp)->nn_ino)) - return; - - if (NANDFS_IS_INDIRECT(bp)) - return; - - error = nandfs_sync_file(vp); - if (error) - nandfs_warning("%s: cannot flush buffers err:%d\n", - __func__, error); -} - -int -nandfs_init(struct vfsconf *vfsp) -{ - - nandfs_node_zone = uma_zcreate("nandfs node zone", - sizeof(struct nandfs_node), NULL, NULL, NULL, NULL, 0, 0); - - return (0); -} - -int -nandfs_uninit(struct vfsconf *vfsp) -{ - - uma_zdestroy(nandfs_node_zone); - return (0); -} - -/* Basic calculators */ -uint64_t -nandfs_get_segnum_of_block(struct nandfs_device *nandfsdev, - nandfs_daddr_t blocknr) -{ - uint64_t segnum, blks_per_seg; - - MPASS(blocknr >= nandfsdev->nd_fsdata.f_first_data_block); - - blks_per_seg = nandfsdev->nd_fsdata.f_blocks_per_segment; - - segnum = blocknr / blks_per_seg; - segnum -= nandfsdev->nd_fsdata.f_first_data_block / blks_per_seg; - - DPRINTF(SYNC, ("%s: returning blocknr %jx -> segnum %jx\n", __func__, - blocknr, segnum)); - - return (segnum); -} - -void -nandfs_get_segment_range(struct nandfs_device *nandfsdev, uint64_t segnum, - uint64_t *seg_start, uint64_t *seg_end) -{ - uint64_t blks_per_seg; - - blks_per_seg = nandfsdev->nd_fsdata.f_blocks_per_segment; - *seg_start = nandfsdev->nd_fsdata.f_first_data_block + - blks_per_seg * segnum; - if (seg_end != NULL) - *seg_end = *seg_start + blks_per_seg -1; -} - -void nandfs_calc_mdt_consts(struct nandfs_device *nandfsdev, - struct nandfs_mdt *mdt, int entry_size) -{ - uint32_t blocksize = nandfsdev->nd_blocksize; - - mdt->entries_per_group = blocksize * 8; - mdt->entries_per_block = blocksize / entry_size; - - mdt->blocks_per_group = - (mdt->entries_per_group -1) / mdt->entries_per_block + 1 + 1; - mdt->groups_per_desc_block = - blocksize / sizeof(struct nandfs_block_group_desc); - mdt->blocks_per_desc_block = - mdt->groups_per_desc_block * mdt->blocks_per_group + 1; -} - -int -nandfs_dev_bread(struct nandfs_device *nandfsdev, nandfs_lbn_t blocknr, - struct ucred *cred, int flags, struct buf **bpp) -{ - int blk2dev = nandfsdev->nd_blocksize / DEV_BSIZE; - int error; - - DPRINTF(BLOCK, ("%s: read from block %jx vp %p\n", __func__, - blocknr * blk2dev, nandfsdev->nd_devvp)); - error = bread(nandfsdev->nd_devvp, blocknr * blk2dev, - nandfsdev->nd_blocksize, NOCRED, bpp); - if (error) - nandfs_error("%s: cannot read from device - blk:%jx\n", - __func__, blocknr); - return (error); -} - -/* Read on a node */ -int -nandfs_bread(struct nandfs_node *node, nandfs_lbn_t blocknr, - struct ucred *cred, int flags, struct buf **bpp) -{ - nandfs_daddr_t vblk; - int error; - - DPRINTF(BLOCK, ("%s: vp:%p lbn:%#jx\n", __func__, NTOV(node), - blocknr)); - - error = bread(NTOV(node), blocknr, node->nn_nandfsdev->nd_blocksize, - cred, bpp); - - KASSERT(error == 0, ("%s: vp:%p lbn:%#jx err:%d\n", __func__, - NTOV(node), blocknr, error)); - - if (!nandfs_vblk_get(*bpp) && - ((*bpp)->b_flags & B_CACHE) && node->nn_ino != NANDFS_DAT_INO) { - nandfs_bmap_lookup(node, blocknr, &vblk); - nandfs_vblk_set(*bpp, vblk); - } - return (error); -} - -int -nandfs_bread_meta(struct nandfs_node *node, nandfs_lbn_t blocknr, - struct ucred *cred, int flags, struct buf **bpp) -{ - nandfs_daddr_t vblk; - int error; - - DPRINTF(BLOCK, ("%s: vp:%p lbn:%#jx\n", __func__, NTOV(node), - blocknr)); - - error = bread(NTOV(node), blocknr, node->nn_nandfsdev->nd_blocksize, - cred, bpp); - - KASSERT(error == 0, ("%s: vp:%p lbn:%#jx err:%d\n", __func__, - NTOV(node), blocknr, error)); - - if (!nandfs_vblk_get(*bpp) && - ((*bpp)->b_flags & B_CACHE) && node->nn_ino != NANDFS_DAT_INO) { - nandfs_bmap_lookup(node, blocknr, &vblk); - nandfs_vblk_set(*bpp, vblk); - } - - return (error); -} - -int -nandfs_bdestroy(struct nandfs_node *node, nandfs_daddr_t vblk) -{ - int error; - - if (!NANDFS_SYS_NODE(node->nn_ino)) - NANDFS_WRITEASSERT(node->nn_nandfsdev); - - error = nandfs_vblock_end(node->nn_nandfsdev, vblk); - if (error) { - nandfs_error("%s: ending vblk: %jx failed\n", - __func__, (uintmax_t)vblk); - return (error); - } - node->nn_inode.i_blocks--; - - return (0); -} - -int -nandfs_bcreate(struct nandfs_node *node, nandfs_lbn_t blocknr, - struct ucred *cred, int flags, struct buf **bpp) -{ - int error; - - ASSERT_VOP_LOCKED(NTOV(node), __func__); - if (!NANDFS_SYS_NODE(node->nn_ino)) - NANDFS_WRITEASSERT(node->nn_nandfsdev); - - DPRINTF(BLOCK, ("%s: vp:%p lbn:%#jx\n", __func__, NTOV(node), - blocknr)); - - *bpp = getblk(NTOV(node), blocknr, node->nn_nandfsdev->nd_blocksize, - 0, 0, 0); - - KASSERT((*bpp), ("%s: vp:%p lbn:%#jx\n", __func__, - NTOV(node), blocknr)); - - if (*bpp) { - vfs_bio_clrbuf(*bpp); - (*bpp)->b_blkno = ~(0); /* To avoid VOP_BMAP in bdwrite */ - error = nandfs_bmap_insert_block(node, blocknr, *bpp); - if (error) { - nandfs_warning("%s: failed bmap insert node:%p" - " blk:%jx\n", __func__, node, blocknr); - brelse(*bpp); - return (error); - } - node->nn_inode.i_blocks++; - - return (0); - } - - return (-1); -} - -int -nandfs_bcreate_meta(struct nandfs_node *node, nandfs_lbn_t blocknr, - struct ucred *cred, int flags, struct buf **bpp) -{ - struct nandfs_device *fsdev; - nandfs_daddr_t vblk; - int error; - - ASSERT_VOP_LOCKED(NTOV(node), __func__); - NANDFS_WRITEASSERT(node->nn_nandfsdev); - - DPRINTF(BLOCK, ("%s: vp:%p lbn:%#jx\n", __func__, NTOV(node), - blocknr)); - - fsdev = node->nn_nandfsdev; - - *bpp = getblk(NTOV(node), blocknr, node->nn_nandfsdev->nd_blocksize, - 0, 0, 0); - - KASSERT((*bpp), ("%s: vp:%p lbn:%#jx\n", __func__, - NTOV(node), blocknr)); - - memset((*bpp)->b_data, 0, fsdev->nd_blocksize); - - vfs_bio_clrbuf(*bpp); - (*bpp)->b_blkno = ~(0); /* To avoid VOP_BMAP in bdwrite */ - - nandfs_buf_set(*bpp, NANDFS_VBLK_ASSIGNED); - - if (node->nn_ino != NANDFS_DAT_INO) { - error = nandfs_vblock_alloc(fsdev, &vblk); - if (error) { - nandfs_buf_clear(*bpp, NANDFS_VBLK_ASSIGNED); - brelse(*bpp); - return (error); - } - } else - vblk = fsdev->nd_fakevblk++; - - nandfs_vblk_set(*bpp, vblk); - - nandfs_bmap_insert_block(node, blocknr, *bpp); - return (0); -} - -/* Translate index to a file block number and an entry */ -void -nandfs_mdt_trans(struct nandfs_mdt *mdt, uint64_t index, - nandfs_lbn_t *blocknr, uint32_t *entry_in_block) -{ - uint64_t blknr; - uint64_t group, group_offset, blocknr_in_group; - uint64_t desc_block, desc_offset; - - /* Calculate our offset in the file */ - group = index / mdt->entries_per_group; - group_offset = index % mdt->entries_per_group; - desc_block = group / mdt->groups_per_desc_block; - desc_offset = group % mdt->groups_per_desc_block; - blocknr_in_group = group_offset / mdt->entries_per_block; - - /* To descgroup offset */ - blknr = 1 + desc_block * mdt->blocks_per_desc_block; - - /* To group offset */ - blknr += desc_offset * mdt->blocks_per_group; - - /* To actual file block */ - blknr += 1 + blocknr_in_group; - - *blocknr = blknr; - *entry_in_block = group_offset % mdt->entries_per_block; -} - -void -nandfs_mdt_trans_blk(struct nandfs_mdt *mdt, uint64_t index, - uint64_t *desc, uint64_t *bitmap, nandfs_lbn_t *blocknr, - uint32_t *entry_in_block) -{ - uint64_t blknr; - uint64_t group, group_offset, blocknr_in_group; - uint64_t desc_block, desc_offset; - - /* Calculate our offset in the file */ - group = index / mdt->entries_per_group; - group_offset = index % mdt->entries_per_group; - desc_block = group / mdt->groups_per_desc_block; - desc_offset = group % mdt->groups_per_desc_block; - blocknr_in_group = group_offset / mdt->entries_per_block; - - /* To descgroup offset */ - *desc = desc_block * mdt->blocks_per_desc_block; - blknr = 1 + desc_block * mdt->blocks_per_desc_block; - - /* To group offset */ - blknr += desc_offset * mdt->blocks_per_group; - *bitmap = blknr; - - /* To actual file block */ - blknr += 1 + blocknr_in_group; - - *blocknr = blknr; - *entry_in_block = group_offset % mdt->entries_per_block; - - DPRINTF(ALLOC, - ("%s: desc_buf: %jx bitmap_buf: %jx entry_buf: %jx entry: %x\n", - __func__, (uintmax_t)*desc, (uintmax_t)*bitmap, - (uintmax_t)*blocknr, *entry_in_block)); -} - -int -nandfs_vtop(struct nandfs_node *node, nandfs_daddr_t vblocknr, - nandfs_daddr_t *pblocknr) -{ - struct nandfs_node *dat_node; - struct nandfs_dat_entry *entry; - struct buf *bp; - nandfs_lbn_t ldatblknr; - uint32_t entry_in_block; - int locked, error; - - if (node->nn_ino == NANDFS_DAT_INO || node->nn_ino == NANDFS_GC_INO) { - *pblocknr = vblocknr; - return (0); - } - - /* only translate valid vblocknrs */ - if (vblocknr == 0) - return (0); - - dat_node = node->nn_nandfsdev->nd_dat_node; - nandfs_mdt_trans(&node->nn_nandfsdev->nd_dat_mdt, vblocknr, &ldatblknr, - &entry_in_block); - - locked = NANDFS_VOP_ISLOCKED(NTOV(dat_node)); - if (!locked) - VOP_LOCK(NTOV(dat_node), LK_SHARED); - error = nandfs_bread(dat_node, ldatblknr, NOCRED, 0, &bp); - if (error) { - DPRINTF(TRANSLATE, ("vtop: can't read in DAT block %#jx!\n", - (uintmax_t)ldatblknr)); - brelse(bp); - VOP_UNLOCK(NTOV(dat_node), 0); - return (error); - } - - /* Get our translation */ - entry = ((struct nandfs_dat_entry *) bp->b_data) + entry_in_block; - DPRINTF(TRANSLATE, ("\tentry %p data %p entry_in_block %x\n", - entry, bp->b_data, entry_in_block)) - DPRINTF(TRANSLATE, ("\tvblk %#jx -> %#jx for cp [%#jx-%#jx]\n", - (uintmax_t)vblocknr, (uintmax_t)entry->de_blocknr, - (uintmax_t)entry->de_start, (uintmax_t)entry->de_end)); - - *pblocknr = entry->de_blocknr; - brelse(bp); - if (!locked) - VOP_UNLOCK(NTOV(dat_node), 0); - - MPASS(*pblocknr >= node->nn_nandfsdev->nd_fsdata.f_first_data_block || - *pblocknr == 0); - - return (0); -} - -int -nandfs_segsum_valid(struct nandfs_segment_summary *segsum) -{ - - return (segsum->ss_magic == NANDFS_SEGSUM_MAGIC); -} - -int -nandfs_load_segsum(struct nandfs_device *fsdev, nandfs_daddr_t blocknr, - struct nandfs_segment_summary *segsum) -{ - struct buf *bp; - int error; - - DPRINTF(VOLUMES, ("nandfs: try segsum at block %jx\n", - (uintmax_t)blocknr)); - - error = nandfs_dev_bread(fsdev, blocknr, NOCRED, 0, &bp); - if (error) - return (error); - - memcpy(segsum, bp->b_data, sizeof(struct nandfs_segment_summary)); - brelse(bp); - - if (!nandfs_segsum_valid(segsum)) { - DPRINTF(VOLUMES, ("%s: bad magic pseg:%jx\n", __func__, - blocknr)); - return (EINVAL); - } - - return (error); -} - -static int -nandfs_load_super_root(struct nandfs_device *nandfsdev, - struct nandfs_segment_summary *segsum, uint64_t pseg) -{ - struct nandfs_super_root super_root; - struct buf *bp; - uint64_t blocknr; - uint32_t super_root_crc, comp_crc; - int off, error; - - /* Check if there is a superroot */ - if ((segsum->ss_flags & NANDFS_SS_SR) == 0) { - DPRINTF(VOLUMES, ("%s: no super root in pseg:%jx\n", __func__, - pseg)); - return (ENOENT); - } - - /* Get our super root, located at the end of the pseg */ - blocknr = pseg + segsum->ss_nblocks - 1; - DPRINTF(VOLUMES, ("%s: try at %#jx\n", __func__, (uintmax_t)blocknr)); - - error = nandfs_dev_bread(nandfsdev, blocknr, NOCRED, 0, &bp); - if (error) - return (error); - - memcpy(&super_root, bp->b_data, sizeof(struct nandfs_super_root)); - brelse(bp); - - /* Check super root CRC */ - super_root_crc = super_root.sr_sum; - off = sizeof(super_root.sr_sum); - comp_crc = crc32((uint8_t *)&super_root + off, - NANDFS_SR_BYTES - off); - - if (super_root_crc != comp_crc) { - DPRINTF(VOLUMES, ("%s: invalid crc:%#x [expect:%#x]\n", - __func__, super_root_crc, comp_crc)); - return (EINVAL); - } - - nandfsdev->nd_super_root = super_root; - DPRINTF(VOLUMES, ("%s: got valid superroot\n", __func__)); - - return (0); -} - -/* - * Search for the last super root recorded. - */ -int -nandfs_search_super_root(struct nandfs_device *nandfsdev) -{ - struct nandfs_super_block *super; - struct nandfs_segment_summary segsum; - uint64_t seg_start, seg_end, cno, seq, create, pseg; - uint64_t segnum; - int error, found; - - error = found = 0; - - /* Search for last super root */ - pseg = nandfsdev->nd_super.s_last_pseg; - segnum = nandfs_get_segnum_of_block(nandfsdev, pseg); - - cno = nandfsdev->nd_super.s_last_cno; - create = seq = 0; - DPRINTF(VOLUMES, ("%s: start in pseg %#jx\n", __func__, - (uintmax_t)pseg)); - - for (;;) { - error = nandfs_load_segsum(nandfsdev, pseg, &segsum); - if (error) - break; - - if (segsum.ss_seq < seq || segsum.ss_create < create) - break; - - /* Try to load super root */ - if (segsum.ss_flags & NANDFS_SS_SR) { - error = nandfs_load_super_root(nandfsdev, &segsum, pseg); - if (error) - break; /* confused */ - found = 1; - - super = &nandfsdev->nd_super; - nandfsdev->nd_last_segsum = segsum; - super->s_last_pseg = pseg; - super->s_last_cno = cno++; - super->s_last_seq = segsum.ss_seq; - super->s_state = NANDFS_VALID_FS; - seq = segsum.ss_seq; - create = segsum.ss_create; - } else { - seq = segsum.ss_seq; - create = segsum.ss_create; - } - - /* Calculate next partial segment location */ - pseg += segsum.ss_nblocks; - DPRINTF(VOLUMES, ("%s: next partial seg is %jx\n", __func__, - (uintmax_t)pseg)); - - /* Did we reach the end of the segment? if so, go to the next */ - nandfs_get_segment_range(nandfsdev, segnum, &seg_start, - &seg_end); - if (pseg >= seg_end) { - pseg = segsum.ss_next; - DPRINTF(VOLUMES, - (" partial seg oor next is %jx[%jx - %jx]\n", - (uintmax_t)pseg, (uintmax_t)seg_start, - (uintmax_t)seg_end)); - } - segnum = nandfs_get_segnum_of_block(nandfsdev, pseg); - } - - if (error && !found) - return (error); - - return (0); -} - -int -nandfs_get_node_raw(struct nandfs_device *nandfsdev, struct nandfsmount *nmp, - uint64_t ino, struct nandfs_inode *inode, struct nandfs_node **nodep) -{ - struct nandfs_node *node; - struct vnode *nvp; - struct mount *mp; - int error; - - *nodep = NULL; - - /* Associate with mountpoint if present */ - if (nmp) { - mp = nmp->nm_vfs_mountp; - error = getnewvnode("nandfs", mp, &nandfs_vnodeops, &nvp); - if (error) - return (error); - } else { - mp = NULL; - error = getnewvnode("snandfs", mp, &nandfs_system_vnodeops, - &nvp); - if (error) - return (error); - } - - if (mp) - NANDFS_WRITELOCK(nandfsdev); - - DPRINTF(IFILE, ("%s: ino: %#jx -> vp: %p\n", - __func__, (uintmax_t)ino, nvp)); - /* Lock node */ - lockmgr(nvp->v_vnlock, LK_EXCLUSIVE, NULL); - - if (mp) { - error = insmntque(nvp, mp); - if (error != 0) { - *nodep = NULL; - return (error); - } - } - - node = uma_zalloc(nandfs_node_zone, M_WAITOK | M_ZERO); - - /* Crosslink */ - node->nn_vnode = nvp; - nvp->v_bufobj.bo_ops = &buf_ops_nandfs; - node->nn_nmp = nmp; - node->nn_nandfsdev = nandfsdev; - nvp->v_data = node; - - /* Initiase NANDFS node */ - node->nn_ino = ino; - if (inode != NULL) - node->nn_inode = *inode; - - nandfs_vinit(nvp, ino); - - /* Return node */ - *nodep = node; - DPRINTF(IFILE, ("%s: ino:%#jx vp:%p node:%p\n", - __func__, (uintmax_t)ino, nvp, *nodep)); - - return (0); -} - -int -nandfs_get_node(struct nandfsmount *nmp, uint64_t ino, - struct nandfs_node **nodep) -{ - struct nandfs_device *nandfsdev; - struct nandfs_inode inode, *entry; - struct vnode *nvp, *vpp; - struct thread *td; - struct buf *bp; - uint64_t ivblocknr; - uint32_t entry_in_block; - int error; - - /* Look up node in hash table */ - td = curthread; - *nodep = NULL; - - if ((ino < NANDFS_ATIME_INO) && (ino != NANDFS_ROOT_INO)) { - printf("nandfs_get_node: system ino %"PRIu64" not in mount " - "point!\n", ino); - return (ENOENT); - } - - error = vfs_hash_get(nmp->nm_vfs_mountp, ino, LK_EXCLUSIVE, td, &nvp, - NULL, NULL); - if (error) - return (error); - - if (nvp != NULL) { - *nodep = (struct nandfs_node *)nvp->v_data; - return (0); - } - - /* Look up inode structure in mountpoints ifile */ - nandfsdev = nmp->nm_nandfsdev; - nandfs_mdt_trans(&nandfsdev->nd_ifile_mdt, ino, &ivblocknr, - &entry_in_block); - - VOP_LOCK(NTOV(nmp->nm_ifile_node), LK_SHARED); - error = nandfs_bread(nmp->nm_ifile_node, ivblocknr, NOCRED, 0, &bp); - if (error) { - brelse(bp); - VOP_UNLOCK(NTOV(nmp->nm_ifile_node), 0); - return (ENOENT); - } - - /* Get inode entry */ - entry = (struct nandfs_inode *) bp->b_data + entry_in_block; - memcpy(&inode, entry, sizeof(struct nandfs_inode)); - brelse(bp); - VOP_UNLOCK(NTOV(nmp->nm_ifile_node), 0); - - /* Get node */ - error = nandfs_get_node_raw(nmp->nm_nandfsdev, nmp, ino, &inode, nodep); - if (error) { - *nodep = NULL; - return (error); - } - - nvp = (*nodep)->nn_vnode; - error = vfs_hash_insert(nvp, ino, 0, td, &vpp, NULL, NULL); - if (error) { - *nodep = NULL; - return (error); - } - - return (error); -} - -void -nandfs_dispose_node(struct nandfs_node **nodep) -{ - struct nandfs_node *node; - struct vnode *vp; - - /* Protect against rogue values */ - node = *nodep; - if (!node) { - return; - } - DPRINTF(NODE, ("nandfs_dispose_node: %p\n", *nodep)); - - vp = NTOV(node); - vp->v_data = NULL; - - /* Free our associated memory */ - uma_zfree(nandfs_node_zone, node); - - *nodep = NULL; -} - -int -nandfs_lookup_name_in_dir(struct vnode *dvp, const char *name, int namelen, - uint64_t *ino, int *found, uint64_t *off) -{ - struct nandfs_node *dir_node = VTON(dvp); - struct nandfs_dir_entry *ndirent; - struct buf *bp; - uint64_t file_size, diroffset, blkoff; - uint64_t blocknr; - uint32_t blocksize = dir_node->nn_nandfsdev->nd_blocksize; - uint8_t *pos, name_len; - int error; - - *found = 0; - - DPRINTF(VNCALL, ("%s: %s file\n", __func__, name)); - if (dvp->v_type != VDIR) { - return (ENOTDIR); - } - - /* Get directory filesize */ - file_size = dir_node->nn_inode.i_size; - - /* Walk the directory */ - diroffset = 0; - blocknr = 0; - blkoff = 0; - error = nandfs_bread(dir_node, blocknr, NOCRED, 0, &bp); - if (error) { - brelse(bp); - return (EIO); - } - - while (diroffset < file_size) { - if (blkoff >= blocksize) { - blkoff = 0; blocknr++; - brelse(bp); - error = nandfs_bread(dir_node, blocknr, NOCRED, 0, - &bp); - if (error) { - brelse(bp); - return (EIO); - } - } - - /* Read in one dirent */ - pos = (uint8_t *) bp->b_data + blkoff; - ndirent = (struct nandfs_dir_entry *) pos; - name_len = ndirent->name_len; - - if ((name_len == namelen) && - (strncmp(name, ndirent->name, name_len) == 0) && - (ndirent->inode != 0)) { - *ino = ndirent->inode; - *off = diroffset; - DPRINTF(LOOKUP, ("found `%.*s` with ino %"PRIx64"\n", - name_len, ndirent->name, *ino)); - *found = 1; - break; - } - - /* Advance */ - diroffset += ndirent->rec_len; - blkoff += ndirent->rec_len; - } - brelse(bp); - - return (error); -} - -int -nandfs_get_fsinfo(struct nandfsmount *nmp, struct nandfs_fsinfo *fsinfo) -{ - struct nandfs_device *fsdev; - - fsdev = nmp->nm_nandfsdev; - - memcpy(&fsinfo->fs_fsdata, &fsdev->nd_fsdata, sizeof(fsdev->nd_fsdata)); - memcpy(&fsinfo->fs_super, &fsdev->nd_super, sizeof(fsdev->nd_super)); - snprintf(fsinfo->fs_dev, sizeof(fsinfo->fs_dev), - "%s", nmp->nm_vfs_mountp->mnt_stat.f_mntfromname); - - return (0); -} - -void -nandfs_inode_init(struct nandfs_inode *inode, uint16_t mode) -{ - struct timespec ts; - - vfs_timestamp(&ts); - - inode->i_blocks = 0; - inode->i_size = 0; - inode->i_ctime = ts.tv_sec; - inode->i_ctime_nsec = ts.tv_nsec; - inode->i_mtime = ts.tv_sec; - inode->i_mtime_nsec = ts.tv_nsec; - inode->i_mode = mode; - inode->i_links_count = 1; - if (S_ISDIR(mode)) - inode->i_links_count = 2; - inode->i_flags = 0; - - inode->i_special = 0; - memset(inode->i_db, 0, sizeof(inode->i_db)); - memset(inode->i_ib, 0, sizeof(inode->i_ib)); -} - -void -nandfs_inode_destroy(struct nandfs_inode *inode) -{ - - MPASS(inode->i_blocks == 0); - bzero(inode, sizeof(*inode)); -} - -int -nandfs_fs_full(struct nandfs_device *nffsdev) -{ - uint64_t space, bps; - - bps = nffsdev->nd_fsdata.f_blocks_per_segment; - space = (nffsdev->nd_clean_segs - 1) * bps; - - DPRINTF(BUF, ("%s: bufs:%jx space:%jx\n", __func__, - (uintmax_t)nffsdev->nd_dirty_bufs, (uintmax_t)space)); - - if (nffsdev->nd_dirty_bufs + (nffsdev->nd_segs_reserved * bps) >= space) - return (1); - - return (0); -} - -static int -_nandfs_dirty_buf(struct buf *bp, int dirty_meta, int force) -{ - struct nandfs_device *nffsdev; - struct nandfs_node *node; - uint64_t ino, bps; - - if (NANDFS_ISGATHERED(bp)) { - bqrelse(bp); - return (0); - } - if ((bp->b_flags & (B_MANAGED | B_DELWRI)) == (B_MANAGED | B_DELWRI)) { - bqrelse(bp); - return (0); - } - - node = VTON(bp->b_vp); - nffsdev = node->nn_nandfsdev; - DPRINTF(BUF, ("%s: buf:%p\n", __func__, bp)); - ino = node->nn_ino; - - if (nandfs_fs_full(nffsdev) && !NANDFS_SYS_NODE(ino) && !force) { - brelse(bp); - return (ENOSPC); - } - - bp->b_flags |= B_MANAGED; - bdwrite(bp); - - nandfs_dirty_bufs_increment(nffsdev); - - KASSERT((bp->b_vp), ("vp missing for bp")); - KASSERT((nandfs_vblk_get(bp) || ino == NANDFS_DAT_INO), - ("bp vblk is 0")); - - /* - * To maintain consistency of FS we need to force making - * meta buffers dirty, even if free space is low. - */ - if (dirty_meta && ino != NANDFS_GC_INO) - nandfs_bmap_dirty_blocks(VTON(bp->b_vp), bp, 1); - - bps = nffsdev->nd_fsdata.f_blocks_per_segment; - - if (nffsdev->nd_dirty_bufs >= (bps * nandfs_max_dirty_segs)) { - mtx_lock(&nffsdev->nd_sync_mtx); - if (nffsdev->nd_syncing == 0) { - DPRINTF(SYNC, ("%s: wakeup gc\n", __func__)); - nffsdev->nd_syncing = 1; - wakeup(&nffsdev->nd_syncing); - } - mtx_unlock(&nffsdev->nd_sync_mtx); - } - - return (0); -} - -int -nandfs_dirty_buf(struct buf *bp, int force) -{ - - return (_nandfs_dirty_buf(bp, 1, force)); -} - -int -nandfs_dirty_buf_meta(struct buf *bp, int force) -{ - - return (_nandfs_dirty_buf(bp, 0, force)); -} - -void -nandfs_undirty_buf_fsdev(struct nandfs_device *nffsdev, struct buf *bp) -{ - - BUF_ASSERT_HELD(bp); - - if (bp->b_flags & B_DELWRI) { - bp->b_flags &= ~(B_DELWRI|B_MANAGED); - nandfs_dirty_bufs_decrement(nffsdev); - } - /* - * Since it is now being written, we can clear its deferred write flag. - */ - bp->b_flags &= ~B_DEFERRED; - - brelse(bp); -} - -void -nandfs_undirty_buf(struct buf *bp) -{ - struct nandfs_node *node; - - node = VTON(bp->b_vp); - - nandfs_undirty_buf_fsdev(node->nn_nandfsdev, bp); -} - -void -nandfs_vblk_set(struct buf *bp, nandfs_daddr_t blocknr) -{ - - nandfs_daddr_t *vblk = (nandfs_daddr_t *)(&bp->b_fsprivate1); - *vblk = blocknr; -} - -nandfs_daddr_t -nandfs_vblk_get(struct buf *bp) -{ - - nandfs_daddr_t *vblk = (nandfs_daddr_t *)(&bp->b_fsprivate1); - return (*vblk); -} - -void -nandfs_buf_set(struct buf *bp, uint32_t bits) -{ - uintptr_t flags; - - flags = (uintptr_t)bp->b_fsprivate3; - flags |= (uintptr_t)bits; - bp->b_fsprivate3 = (void *)flags; -} - -void -nandfs_buf_clear(struct buf *bp, uint32_t bits) -{ - uintptr_t flags; - - flags = (uintptr_t)bp->b_fsprivate3; - flags &= ~(uintptr_t)bits; - bp->b_fsprivate3 = (void *)flags; -} - -int -nandfs_buf_check(struct buf *bp, uint32_t bits) -{ - uintptr_t flags; - - flags = (uintptr_t)bp->b_fsprivate3; - if (flags & bits) - return (1); - return (0); -} - -int -nandfs_erase(struct nandfs_device *fsdev, off_t offset, size_t size) -{ - DPRINTF(BLOCK, ("%s: performing erase at offset %jx size %zx\n", - __func__, offset, size)); - - MPASS(size % fsdev->nd_erasesize == 0); - - return (g_delete_data(fsdev->nd_gconsumer, offset, size)); -} - -int -nandfs_vop_islocked(struct vnode *vp) -{ - int islocked; - - islocked = VOP_ISLOCKED(vp); - return (islocked == LK_EXCLUSIVE || islocked == LK_SHARED); -} - -nandfs_daddr_t -nandfs_block_to_dblock(struct nandfs_device *fsdev, nandfs_lbn_t block) -{ - - return (btodb(block * fsdev->nd_blocksize)); -} diff --git a/sys/fs/nandfs/nandfs_subr.h b/sys/fs/nandfs/nandfs_subr.h deleted file mode 100644 index f3eb534eb68..00000000000 --- a/sys/fs/nandfs/nandfs_subr.h +++ /dev/null @@ -1,239 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2010-2012 Semihalf - * Copyright (c) 2008, 2009 Reinoud Zandijk - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * From: NetBSD: nilfs_subr.h,v 1.1 2009/07/18 16:31:42 reinoud - * - */ - -#ifndef _FS_NANDFS_NANDFS_SUBR_H_ -#define _FS_NANDFS_NANDFS_SUBR_H_ - -struct nandfs_mdt; - -struct nandfs_alloc_request -{ - uint64_t entrynum; - struct buf *bp_desc; - struct buf *bp_bitmap; - struct buf *bp_entry; -}; - -/* Segment creation */ -void nandfs_wakeup_wait_sync(struct nandfs_device *, int); -int nandfs_segment_constructor(struct nandfsmount *, int); -int nandfs_sync_file(struct vnode *); - -/* Basic calculators */ -uint64_t nandfs_get_segnum_of_block(struct nandfs_device *, nandfs_daddr_t); -void nandfs_get_segment_range(struct nandfs_device *, uint64_t, uint64_t *, - uint64_t *); -void nandfs_calc_mdt_consts(struct nandfs_device *, struct nandfs_mdt *, int); - -/* Log reading / volume helpers */ -int nandfs_search_super_root(struct nandfs_device *); - -/* Reading */ -int nandfs_dev_bread(struct nandfs_device *, nandfs_daddr_t, struct ucred *, - int, struct buf **); -int nandfs_bread(struct nandfs_node *, nandfs_lbn_t, struct ucred *, int, - struct buf **); -int nandfs_bread_meta(struct nandfs_node *, nandfs_lbn_t, struct ucred *, int, - struct buf **); -int nandfs_bdestroy(struct nandfs_node *, nandfs_daddr_t); -int nandfs_bcreate(struct nandfs_node *, nandfs_lbn_t, struct ucred *, int, - struct buf **); -int nandfs_bcreate_meta(struct nandfs_node *, nandfs_lbn_t, struct ucred *, - int, struct buf **); -int nandfs_bread_create(struct nandfs_node *, nandfs_lbn_t, struct ucred *, - int, struct buf **); - -/* vtop operations */ -int nandfs_vtop(struct nandfs_node *, nandfs_daddr_t, nandfs_daddr_t *); - -/* Node action implementators */ -int nandfs_vinit(struct vnode *, uint64_t); -int nandfs_get_node(struct nandfsmount *, uint64_t, struct nandfs_node **); -int nandfs_get_node_raw(struct nandfs_device *, struct nandfsmount *, uint64_t, - struct nandfs_inode *, struct nandfs_node **); -void nandfs_dispose_node(struct nandfs_node **); - -void nandfs_itimes(struct vnode *); -int nandfs_lookup_name_in_dir(struct vnode *, const char *, int, uint64_t *, - int *, uint64_t *); -int nandfs_create_node(struct vnode *, struct vnode **, struct vattr *, - struct componentname *); -void nandfs_delete_node(struct nandfs_node *); - -int nandfs_chsize(struct vnode *, u_quad_t, struct ucred *); -int nandfs_dir_detach(struct nandfsmount *, struct nandfs_node *, - struct nandfs_node *, struct componentname *); -int nandfs_dir_attach(struct nandfsmount *, struct nandfs_node *, - struct nandfs_node *, struct vattr *, struct componentname *); - -int nandfs_dirty_buf(struct buf *, int); -int nandfs_dirty_buf_meta(struct buf *, int); -int nandfs_fs_full(struct nandfs_device *); -void nandfs_undirty_buf_fsdev(struct nandfs_device *, struct buf *); -void nandfs_undirty_buf(struct buf *); - -void nandfs_clear_buf(struct buf *); -void nandfs_buf_set(struct buf *, uint32_t); -void nandfs_buf_clear(struct buf *, uint32_t); -int nandfs_buf_check(struct buf *, uint32_t); - -int nandfs_find_free_entry(struct nandfs_mdt *, struct nandfs_node *, - struct nandfs_alloc_request *); -int nandfs_find_entry(struct nandfs_mdt *, struct nandfs_node *, - struct nandfs_alloc_request *); -int nandfs_alloc_entry(struct nandfs_mdt *, struct nandfs_alloc_request *); -void nandfs_abort_entry(struct nandfs_alloc_request *); -int nandfs_free_entry(struct nandfs_mdt *, struct nandfs_alloc_request *); -int nandfs_get_entry_block(struct nandfs_mdt *, struct nandfs_node *, - struct nandfs_alloc_request *, uint32_t *, int); - -/* Inode management. */ -int nandfs_node_create(struct nandfsmount *, struct nandfs_node **, uint16_t); -int nandfs_node_destroy(struct nandfs_node *); -int nandfs_node_update(struct nandfs_node *); -int nandfs_get_node_entry(struct nandfsmount *, struct nandfs_inode **, - uint64_t, struct buf **); -void nandfs_mdt_trans_blk(struct nandfs_mdt *, uint64_t, uint64_t *, - uint64_t *, nandfs_lbn_t *, uint32_t *); - -/* vblock management */ -void nandfs_mdt_trans(struct nandfs_mdt *, uint64_t, nandfs_lbn_t *, uint32_t *); -int nandfs_vblock_alloc(struct nandfs_device *, nandfs_daddr_t *); -int nandfs_vblock_end(struct nandfs_device *, nandfs_daddr_t); -int nandfs_vblock_assign(struct nandfs_device *, nandfs_daddr_t, - nandfs_lbn_t); -int nandfs_vblock_free(struct nandfs_device *, nandfs_daddr_t); - -/* Checkpoint management */ -int nandfs_get_checkpoint(struct nandfs_device *, struct nandfs_node *, - uint64_t); -int nandfs_set_checkpoint(struct nandfs_device *, struct nandfs_node *, - uint64_t, struct nandfs_inode *, uint64_t); - -/* Segment management */ -int nandfs_alloc_segment(struct nandfs_device *, uint64_t *); -int nandfs_update_segment(struct nandfs_device *, uint64_t, uint32_t); -int nandfs_free_segment(struct nandfs_device *, uint64_t); -int nandfs_clear_segment(struct nandfs_device *, uint64_t); -int nandfs_touch_segment(struct nandfs_device *, uint64_t); -int nandfs_markgc_segment(struct nandfs_device *, uint64_t); - -int nandfs_bmap_insert_block(struct nandfs_node *, nandfs_lbn_t, struct buf *); -int nandfs_bmap_update_block(struct nandfs_node *, struct buf *, nandfs_lbn_t); -int nandfs_bmap_update_dat(struct nandfs_node *, nandfs_daddr_t, struct buf *); -int nandfs_bmap_dirty_blocks(struct nandfs_node *, struct buf *, int); -int nandfs_bmap_truncate_mapping(struct nandfs_node *, nandfs_lbn_t, - nandfs_lbn_t); -int nandfs_bmap_lookup(struct nandfs_node *, nandfs_lbn_t, nandfs_daddr_t *); - -/* dirent */ -int nandfs_add_dirent(struct vnode *, uint64_t, char *, long, uint8_t); -int nandfs_remove_dirent(struct vnode *, struct nandfs_node *, - struct componentname *); -int nandfs_update_dirent(struct vnode *, struct nandfs_node *, - struct nandfs_node *); -int nandfs_init_dir(struct vnode *, uint64_t, uint64_t); -int nandfs_update_parent_dir(struct vnode *, uint64_t); - -void nandfs_vblk_set(struct buf *, nandfs_daddr_t); -nandfs_daddr_t nandfs_vblk_get(struct buf *); - -void nandfs_inode_init(struct nandfs_inode *, uint16_t); -void nandfs_inode_destroy(struct nandfs_inode *); - -/* ioctl */ -int nandfs_get_seg_stat(struct nandfs_device *, struct nandfs_seg_stat *); -int nandfs_chng_cpmode(struct nandfs_node *, struct nandfs_cpmode *); -int nandfs_get_cpinfo_ioctl(struct nandfs_node *, struct nandfs_argv *); -int nandfs_delete_cp(struct nandfs_node *, uint64_t start, uint64_t); -int nandfs_make_snap(struct nandfs_device *, uint64_t *); -int nandfs_delete_snap(struct nandfs_device *, uint64_t); -int nandfs_get_cpstat(struct nandfs_node *, struct nandfs_cpstat *); -int nandfs_get_segment_info_ioctl(struct nandfs_device *, struct nandfs_argv *); -int nandfs_get_dat_vinfo_ioctl(struct nandfs_device *, struct nandfs_argv *); -int nandfs_get_dat_bdescs_ioctl(struct nandfs_device *, struct nandfs_argv *); -int nandfs_get_fsinfo(struct nandfsmount *, struct nandfs_fsinfo *); - -int nandfs_get_cpinfo(struct nandfs_node *, uint64_t, uint16_t, - struct nandfs_cpinfo *, uint32_t, uint32_t *); - -nandfs_lbn_t nandfs_get_maxfilesize(struct nandfs_device *); - -int nandfs_write_superblock(struct nandfs_device *); - -extern int nandfs_sync_interval; -extern int nandfs_max_dirty_segs; -extern int nandfs_cps_between_sblocks; - -struct buf *nandfs_geteblk(int, int); - -void nandfs_dirty_bufs_increment(struct nandfs_device *); -void nandfs_dirty_bufs_decrement(struct nandfs_device *); - -int nandfs_start_cleaner(struct nandfs_device *); -int nandfs_stop_cleaner(struct nandfs_device *); - -int nandfs_segsum_valid(struct nandfs_segment_summary *); -int nandfs_load_segsum(struct nandfs_device *, nandfs_daddr_t, - struct nandfs_segment_summary *); -int nandfs_get_segment_info(struct nandfs_device *, struct nandfs_suinfo *, - uint32_t, uint64_t); -int nandfs_get_segment_info_filter(struct nandfs_device *, - struct nandfs_suinfo *, uint32_t, uint64_t, uint64_t *, uint32_t, uint32_t); -int nandfs_get_dat_vinfo(struct nandfs_device *, struct nandfs_vinfo *, - uint32_t); -int nandfs_get_dat_bdescs(struct nandfs_device *, struct nandfs_bdesc *, - uint32_t); - -#define NANDFS_VBLK_ASSIGNED 1 - -#define NANDFS_IS_INDIRECT(bp) ((bp)->b_lblkno < 0) - -int nandfs_erase(struct nandfs_device *, off_t, size_t); - -#define NANDFS_VOP_ISLOCKED(vp) nandfs_vop_islocked((vp)) -int nandfs_vop_islocked(struct vnode *vp); - -nandfs_daddr_t nandfs_block_to_dblock(struct nandfs_device *, nandfs_lbn_t); - -#define DEBUG_MODE -#if defined(DEBUG_MODE) -#define nandfs_error panic -#define nandfs_warning printf -#elif defined(TEST_MODE) -#define nandfs_error printf -#define nandfs_warning printf -#else -#define nandfs_error(...) -#define nandfs_warning(...) -#endif - -#endif /* !_FS_NANDFS_NANDFS_SUBR_H_ */ diff --git a/sys/fs/nandfs/nandfs_sufile.c b/sys/fs/nandfs/nandfs_sufile.c deleted file mode 100644 index a4fa954a2b0..00000000000 --- a/sys/fs/nandfs/nandfs_sufile.c +++ /dev/null @@ -1,570 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2010-2012 Semihalf. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include -#include - -#include -#include -#include - -#define SU_USAGE_OFF(bp, offset) \ - ((struct nandfs_segment_usage *)((bp)->b_data + offset)) - -static int -nandfs_seg_usage_blk_offset(struct nandfs_device *fsdev, uint64_t seg, - uint64_t *blk, uint64_t *offset) -{ - uint64_t off; - uint16_t seg_size; - - seg_size = fsdev->nd_fsdata.f_segment_usage_size; - - off = roundup(sizeof(struct nandfs_sufile_header), seg_size); - off += (seg * seg_size); - - *blk = off / fsdev->nd_blocksize; - *offset = off % fsdev->nd_blocksize; - return (0); -} - -/* Alloc new segment */ -int -nandfs_alloc_segment(struct nandfs_device *fsdev, uint64_t *seg) -{ - struct nandfs_node *su_node; - struct nandfs_sufile_header *su_header; - struct nandfs_segment_usage *su_usage; - struct buf *bp_header, *bp; - uint64_t blk, vblk, offset, i, rest, nsegments; - uint16_t seg_size; - int error, found; - - seg_size = fsdev->nd_fsdata.f_segment_usage_size; - nsegments = fsdev->nd_fsdata.f_nsegments; - - su_node = fsdev->nd_su_node; - ASSERT_VOP_LOCKED(NTOV(su_node), __func__); - - /* Read header buffer */ - error = nandfs_bread(su_node, 0, NOCRED, 0, &bp_header); - if (error) { - brelse(bp_header); - return (error); - } - - su_header = (struct nandfs_sufile_header *)bp_header->b_data; - - /* Get last allocated segment */ - i = su_header->sh_last_alloc + 1; - - found = 0; - bp = NULL; - while (!found) { - nandfs_seg_usage_blk_offset(fsdev, i, &blk, &offset); - if(blk != 0) { - error = nandfs_bmap_lookup(su_node, blk, &vblk); - if (error) { - nandfs_error("%s: cannot find vblk for blk " - "blk:%jx\n", __func__, blk); - return (error); - } - if (vblk) - error = nandfs_bread(su_node, blk, NOCRED, 0, - &bp); - else - error = nandfs_bcreate(su_node, blk, NOCRED, 0, - &bp); - if (error) { - nandfs_error("%s: cannot create/read " - "vblk:%jx\n", __func__, vblk); - if (bp) - brelse(bp); - return (error); - } - - su_usage = SU_USAGE_OFF(bp, offset); - } else { - su_usage = SU_USAGE_OFF(bp_header, offset); - bp = bp_header; - } - - rest = (fsdev->nd_blocksize - offset) / seg_size; - /* Go through all su usage in block */ - while (rest) { - /* When last check start from beginning */ - if (i == nsegments) - break; - - if (!su_usage->su_flags) { - su_usage->su_flags = 1; - found = 1; - break; - } - su_usage++; - i++; - - /* If all checked return error */ - if (i == su_header->sh_last_alloc) { - DPRINTF(SEG, ("%s: cannot allocate segment \n", - __func__)); - brelse(bp_header); - if (blk != 0) - brelse(bp); - return (1); - } - rest--; - } - if (!found) { - /* Otherwise read another block */ - if (blk != 0) - brelse(bp); - if (i == nsegments) { - blk = 0; - i = 0; - } else - blk++; - offset = 0; - } - } - - if (found) { - *seg = i; - su_header->sh_last_alloc = i; - su_header->sh_ncleansegs--; - su_header->sh_ndirtysegs++; - - fsdev->nd_super.s_free_blocks_count = su_header->sh_ncleansegs * - fsdev->nd_fsdata.f_blocks_per_segment; - fsdev->nd_clean_segs--; - - /* - * It is mostly called from syncer() so we want to force - * making buf dirty. - */ - error = nandfs_dirty_buf(bp_header, 1); - if (error) { - if (bp && bp != bp_header) - brelse(bp); - return (error); - } - if (bp && bp != bp_header) - nandfs_dirty_buf(bp, 1); - - DPRINTF(SEG, ("%s: seg:%#jx\n", __func__, (uintmax_t)i)); - - return (0); - } - - DPRINTF(SEG, ("%s: failed\n", __func__)); - - return (1); -} - -/* - * Make buffer dirty, it will be updated soon but first it need to be - * gathered by syncer. - */ -int -nandfs_touch_segment(struct nandfs_device *fsdev, uint64_t seg) -{ - struct nandfs_node *su_node; - struct buf *bp; - uint64_t blk, offset; - int error; - - su_node = fsdev->nd_su_node; - ASSERT_VOP_LOCKED(NTOV(su_node), __func__); - - nandfs_seg_usage_blk_offset(fsdev, seg, &blk, &offset); - - error = nandfs_bread(su_node, blk, NOCRED, 0, &bp); - if (error) { - brelse(bp); - nandfs_error("%s: cannot preallocate new segment\n", __func__); - return (error); - } else - nandfs_dirty_buf(bp, 1); - - DPRINTF(SEG, ("%s: seg:%#jx\n", __func__, (uintmax_t)seg)); - return (error); -} - -/* Update block count of segment */ -int -nandfs_update_segment(struct nandfs_device *fsdev, uint64_t seg, uint32_t nblks) -{ - struct nandfs_node *su_node; - struct nandfs_segment_usage *su_usage; - struct buf *bp; - uint64_t blk, offset; - int error; - - su_node = fsdev->nd_su_node; - ASSERT_VOP_LOCKED(NTOV(su_node), __func__); - - nandfs_seg_usage_blk_offset(fsdev, seg, &blk, &offset); - - error = nandfs_bread(su_node, blk, NOCRED, 0, &bp); - if (error) { - nandfs_error("%s: read block:%jx to update\n", - __func__, blk); - brelse(bp); - return (error); - } - - su_usage = SU_USAGE_OFF(bp, offset); - su_usage->su_lastmod = fsdev->nd_ts.tv_sec; - su_usage->su_flags = NANDFS_SEGMENT_USAGE_DIRTY; - su_usage->su_nblocks += nblks; - - DPRINTF(SEG, ("%s: seg:%#jx inc:%#x cur:%#x\n", __func__, - (uintmax_t)seg, nblks, su_usage->su_nblocks)); - - nandfs_dirty_buf(bp, 1); - - return (0); -} - -/* Make segment free */ -int -nandfs_free_segment(struct nandfs_device *fsdev, uint64_t seg) -{ - struct nandfs_node *su_node; - struct nandfs_sufile_header *su_header; - struct nandfs_segment_usage *su_usage; - struct buf *bp_header, *bp; - uint64_t blk, offset; - int error; - - su_node = fsdev->nd_su_node; - ASSERT_VOP_LOCKED(NTOV(su_node), __func__); - - /* Read su header */ - error = nandfs_bread(su_node, 0, NOCRED, 0, &bp_header); - if (error) { - brelse(bp_header); - return (error); - } - - su_header = (struct nandfs_sufile_header *)bp_header->b_data; - nandfs_seg_usage_blk_offset(fsdev, seg, &blk, &offset); - - /* Read su usage block if other than su header block */ - if (blk != 0) { - error = nandfs_bread(su_node, blk, NOCRED, 0, &bp); - if (error) { - brelse(bp); - brelse(bp_header); - return (error); - } - } else - bp = bp_header; - - /* Reset su usage data */ - su_usage = SU_USAGE_OFF(bp, offset); - su_usage->su_lastmod = fsdev->nd_ts.tv_sec; - su_usage->su_nblocks = 0; - su_usage->su_flags = 0; - - /* Update clean/dirty counter in header */ - su_header->sh_ncleansegs++; - su_header->sh_ndirtysegs--; - - /* - * Make buffers dirty, called by cleaner - * so force dirty even if no much space left - * on device - */ - nandfs_dirty_buf(bp_header, 1); - if (bp != bp_header) - nandfs_dirty_buf(bp, 1); - - /* Update free block count */ - fsdev->nd_super.s_free_blocks_count = su_header->sh_ncleansegs * - fsdev->nd_fsdata.f_blocks_per_segment; - fsdev->nd_clean_segs++; - - DPRINTF(SEG, ("%s: seg:%#jx\n", __func__, (uintmax_t)seg)); - - return (0); -} - -static int -nandfs_bad_segment(struct nandfs_device *fsdev, uint64_t seg) -{ - struct nandfs_node *su_node; - struct nandfs_segment_usage *su_usage; - struct buf *bp; - uint64_t blk, offset; - int error; - - su_node = fsdev->nd_su_node; - ASSERT_VOP_LOCKED(NTOV(su_node), __func__); - - nandfs_seg_usage_blk_offset(fsdev, seg, &blk, &offset); - - error = nandfs_bread(su_node, blk, NOCRED, 0, &bp); - if (error) { - brelse(bp); - return (error); - } - - su_usage = SU_USAGE_OFF(bp, offset); - su_usage->su_lastmod = fsdev->nd_ts.tv_sec; - su_usage->su_flags = NANDFS_SEGMENT_USAGE_ERROR; - - DPRINTF(SEG, ("%s: seg:%#jx\n", __func__, (uintmax_t)seg)); - - nandfs_dirty_buf(bp, 1); - - return (0); -} - -int -nandfs_markgc_segment(struct nandfs_device *fsdev, uint64_t seg) -{ - struct nandfs_node *su_node; - struct nandfs_segment_usage *su_usage; - struct buf *bp; - uint64_t blk, offset; - int error; - - su_node = fsdev->nd_su_node; - - VOP_LOCK(NTOV(su_node), LK_EXCLUSIVE); - - nandfs_seg_usage_blk_offset(fsdev, seg, &blk, &offset); - - error = nandfs_bread(su_node, blk, NOCRED, 0, &bp); - if (error) { - brelse(bp); - VOP_UNLOCK(NTOV(su_node), 0); - return (error); - } - - su_usage = SU_USAGE_OFF(bp, offset); - MPASS((su_usage->su_flags & NANDFS_SEGMENT_USAGE_GC) == 0); - su_usage->su_flags |= NANDFS_SEGMENT_USAGE_GC; - - brelse(bp); - VOP_UNLOCK(NTOV(su_node), 0); - - DPRINTF(SEG, ("%s: seg:%#jx\n", __func__, (uintmax_t)seg)); - - return (0); -} - -int -nandfs_clear_segment(struct nandfs_device *fsdev, uint64_t seg) -{ - uint64_t offset, segsize; - uint32_t bps, bsize; - int error = 0; - - bps = fsdev->nd_fsdata.f_blocks_per_segment; - bsize = fsdev->nd_blocksize; - segsize = bsize * bps; - nandfs_get_segment_range(fsdev, seg, &offset, NULL); - offset *= bsize; - - DPRINTF(SEG, ("%s: seg:%#jx\n", __func__, (uintmax_t)seg)); - - /* Erase it and mark it bad when fail */ - if (nandfs_erase(fsdev, offset, segsize)) - error = nandfs_bad_segment(fsdev, seg); - - if (error) - return (error); - - /* Mark it free */ - error = nandfs_free_segment(fsdev, seg); - - return (error); -} - -int -nandfs_get_seg_stat(struct nandfs_device *nandfsdev, - struct nandfs_seg_stat *nss) -{ - struct nandfs_sufile_header *suhdr; - struct nandfs_node *su_node; - struct buf *bp; - int err; - - su_node = nandfsdev->nd_su_node; - - NANDFS_WRITELOCK(nandfsdev); - VOP_LOCK(NTOV(su_node), LK_SHARED); - err = nandfs_bread(nandfsdev->nd_su_node, 0, NOCRED, 0, &bp); - if (err) { - brelse(bp); - VOP_UNLOCK(NTOV(su_node), 0); - NANDFS_WRITEUNLOCK(nandfsdev); - return (-1); - } - - suhdr = (struct nandfs_sufile_header *)bp->b_data; - nss->nss_nsegs = nandfsdev->nd_fsdata.f_nsegments; - nss->nss_ncleansegs = suhdr->sh_ncleansegs; - nss->nss_ndirtysegs = suhdr->sh_ndirtysegs; - nss->nss_ctime = 0; - nss->nss_nongc_ctime = nandfsdev->nd_ts.tv_sec; - nss->nss_prot_seq = nandfsdev->nd_seg_sequence; - - brelse(bp); - VOP_UNLOCK(NTOV(su_node), 0); - - NANDFS_WRITEUNLOCK(nandfsdev); - - return (0); -} - -int -nandfs_get_segment_info_ioctl(struct nandfs_device *fsdev, - struct nandfs_argv *nargv) -{ - struct nandfs_suinfo *nsi; - int error; - - if (nargv->nv_nmembs > NANDFS_SEGMENTS_MAX) - return (EINVAL); - - nsi = malloc(sizeof(struct nandfs_suinfo) * nargv->nv_nmembs, - M_NANDFSTEMP, M_WAITOK | M_ZERO); - - error = nandfs_get_segment_info(fsdev, nsi, nargv->nv_nmembs, - nargv->nv_index); - - if (error == 0) - error = copyout(nsi, (void *)(uintptr_t)nargv->nv_base, - sizeof(struct nandfs_suinfo) * nargv->nv_nmembs); - - free(nsi, M_NANDFSTEMP); - return (error); -} - -int -nandfs_get_segment_info(struct nandfs_device *fsdev, struct nandfs_suinfo *nsi, - uint32_t nmembs, uint64_t segment) -{ - - return (nandfs_get_segment_info_filter(fsdev, nsi, nmembs, segment, - NULL, 0, 0)); -} - -int -nandfs_get_segment_info_filter(struct nandfs_device *fsdev, - struct nandfs_suinfo *nsi, uint32_t nmembs, uint64_t segment, - uint64_t *nsegs, uint32_t filter, uint32_t nfilter) -{ - struct nandfs_segment_usage *su; - struct nandfs_node *su_node; - struct buf *bp; - uint64_t curr, blocknr, blockoff, i; - uint32_t flags; - int err = 0; - - curr = ~(0); - - lockmgr(&fsdev->nd_seg_const, LK_EXCLUSIVE, NULL); - su_node = fsdev->nd_su_node; - - VOP_LOCK(NTOV(su_node), LK_SHARED); - - bp = NULL; - if (nsegs != NULL) - *nsegs = 0; - for (i = 0; i < nmembs; segment++) { - if (segment == fsdev->nd_fsdata.f_nsegments) - break; - - nandfs_seg_usage_blk_offset(fsdev, segment, &blocknr, - &blockoff); - - if (i == 0 || curr != blocknr) { - if (bp != NULL) - brelse(bp); - err = nandfs_bread(su_node, blocknr, NOCRED, - 0, &bp); - if (err) { - goto out; - } - curr = blocknr; - } - - su = SU_USAGE_OFF(bp, blockoff); - flags = su->su_flags; - if (segment == fsdev->nd_seg_num || - segment == fsdev->nd_next_seg_num) - flags |= NANDFS_SEGMENT_USAGE_ACTIVE; - - if (nfilter != 0 && (flags & nfilter) != 0) - continue; - if (filter != 0 && (flags & filter) == 0) - continue; - - nsi->nsi_num = segment; - nsi->nsi_lastmod = su->su_lastmod; - nsi->nsi_blocks = su->su_nblocks; - nsi->nsi_flags = flags; - nsi++; - i++; - if (nsegs != NULL) - (*nsegs)++; - } - -out: - if (bp != NULL) - brelse(bp); - VOP_UNLOCK(NTOV(su_node), 0); - lockmgr(&fsdev->nd_seg_const, LK_RELEASE, NULL); - - return (err); -} diff --git a/sys/fs/nandfs/nandfs_vfsops.c b/sys/fs/nandfs/nandfs_vfsops.c deleted file mode 100644 index 3df2a9c4ff2..00000000000 --- a/sys/fs/nandfs/nandfs_vfsops.c +++ /dev/null @@ -1,1600 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2010-2012 Semihalf - * Copyright (c) 2008, 2009 Reinoud Zandijk - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * From: NetBSD: nilfs_vfsops.c,v 1.1 2009/07/18 16:31:42 reinoud Exp - */ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include - -#include -#include -#include - -static MALLOC_DEFINE(M_NANDFSMNT, "nandfs_mount", "NANDFS mount structure"); - -#define NANDFS_SET_SYSTEMFILE(vp) { \ - (vp)->v_vflag |= VV_SYSTEM; \ - vref(vp); \ - vput(vp); } - -#define NANDFS_UNSET_SYSTEMFILE(vp) { \ - VOP_LOCK(vp, LK_EXCLUSIVE); \ - MPASS(vp->v_bufobj.bo_dirty.bv_cnt == 0); \ - (vp)->v_vflag &= ~VV_SYSTEM; \ - vgone(vp); \ - vput(vp); } - -/* Globals */ -struct _nandfs_devices nandfs_devices; - -/* Parameters */ -int nandfs_verbose = 0; - -static void -nandfs_tunable_init(void *arg) -{ - - TUNABLE_INT_FETCH("vfs.nandfs.verbose", &nandfs_verbose); -} -SYSINIT(nandfs_tunables, SI_SUB_VFS, SI_ORDER_ANY, nandfs_tunable_init, NULL); - -static SYSCTL_NODE(_vfs, OID_AUTO, nandfs, CTLFLAG_RD, 0, "NAND filesystem"); -static SYSCTL_NODE(_vfs_nandfs, OID_AUTO, mount, CTLFLAG_RD, 0, - "NANDFS mountpoints"); -SYSCTL_INT(_vfs_nandfs, OID_AUTO, verbose, CTLFLAG_RW, &nandfs_verbose, 0, ""); - -#define NANDFS_CONSTR_INTERVAL 5 -int nandfs_sync_interval = NANDFS_CONSTR_INTERVAL; /* sync every 5 seconds */ -SYSCTL_UINT(_vfs_nandfs, OID_AUTO, sync_interval, CTLFLAG_RW, - &nandfs_sync_interval, 0, ""); - -#define NANDFS_MAX_DIRTY_SEGS 5 -int nandfs_max_dirty_segs = NANDFS_MAX_DIRTY_SEGS; /* sync when 5 dirty seg */ -SYSCTL_UINT(_vfs_nandfs, OID_AUTO, max_dirty_segs, CTLFLAG_RW, - &nandfs_max_dirty_segs, 0, ""); - -#define NANDFS_CPS_BETWEEN_SBLOCKS 5 -int nandfs_cps_between_sblocks = NANDFS_CPS_BETWEEN_SBLOCKS; /* write superblock every 5 checkpoints */ -SYSCTL_UINT(_vfs_nandfs, OID_AUTO, cps_between_sblocks, CTLFLAG_RW, - &nandfs_cps_between_sblocks, 0, ""); - -#define NANDFS_CLEANER_ENABLE 1 -int nandfs_cleaner_enable = NANDFS_CLEANER_ENABLE; -SYSCTL_UINT(_vfs_nandfs, OID_AUTO, cleaner_enable, CTLFLAG_RW, - &nandfs_cleaner_enable, 0, ""); - -#define NANDFS_CLEANER_INTERVAL 5 -int nandfs_cleaner_interval = NANDFS_CLEANER_INTERVAL; -SYSCTL_UINT(_vfs_nandfs, OID_AUTO, cleaner_interval, CTLFLAG_RW, - &nandfs_cleaner_interval, 0, ""); - -#define NANDFS_CLEANER_SEGMENTS 5 -int nandfs_cleaner_segments = NANDFS_CLEANER_SEGMENTS; -SYSCTL_UINT(_vfs_nandfs, OID_AUTO, cleaner_segments, CTLFLAG_RW, - &nandfs_cleaner_segments, 0, ""); - -static int nandfs_mountfs(struct vnode *devvp, struct mount *mp); -static vfs_mount_t nandfs_mount; -static vfs_root_t nandfs_root; -static vfs_statfs_t nandfs_statfs; -static vfs_unmount_t nandfs_unmount; -static vfs_vget_t nandfs_vget; -static vfs_sync_t nandfs_sync; -static const char *nandfs_opts[] = { - "snap", "from", "noatime", NULL -}; - -/* System nodes */ -static int -nandfs_create_system_nodes(struct nandfs_device *nandfsdev) -{ - int error; - - error = nandfs_get_node_raw(nandfsdev, NULL, NANDFS_DAT_INO, - &nandfsdev->nd_super_root.sr_dat, &nandfsdev->nd_dat_node); - if (error) - goto errorout; - - error = nandfs_get_node_raw(nandfsdev, NULL, NANDFS_CPFILE_INO, - &nandfsdev->nd_super_root.sr_cpfile, &nandfsdev->nd_cp_node); - if (error) - goto errorout; - - error = nandfs_get_node_raw(nandfsdev, NULL, NANDFS_SUFILE_INO, - &nandfsdev->nd_super_root.sr_sufile, &nandfsdev->nd_su_node); - if (error) - goto errorout; - - error = nandfs_get_node_raw(nandfsdev, NULL, NANDFS_GC_INO, - NULL, &nandfsdev->nd_gc_node); - if (error) - goto errorout; - - NANDFS_SET_SYSTEMFILE(NTOV(nandfsdev->nd_dat_node)); - NANDFS_SET_SYSTEMFILE(NTOV(nandfsdev->nd_cp_node)); - NANDFS_SET_SYSTEMFILE(NTOV(nandfsdev->nd_su_node)); - NANDFS_SET_SYSTEMFILE(NTOV(nandfsdev->nd_gc_node)); - - DPRINTF(VOLUMES, ("System vnodes: dat: %p cp: %p su: %p\n", - NTOV(nandfsdev->nd_dat_node), NTOV(nandfsdev->nd_cp_node), - NTOV(nandfsdev->nd_su_node))); - return (0); - -errorout: - nandfs_dispose_node(&nandfsdev->nd_gc_node); - nandfs_dispose_node(&nandfsdev->nd_dat_node); - nandfs_dispose_node(&nandfsdev->nd_cp_node); - nandfs_dispose_node(&nandfsdev->nd_su_node); - - return (error); -} - -static void -nandfs_release_system_nodes(struct nandfs_device *nandfsdev) -{ - - if (!nandfsdev) - return; - if (nandfsdev->nd_refcnt > 0) - return; - - if (nandfsdev->nd_gc_node) - NANDFS_UNSET_SYSTEMFILE(NTOV(nandfsdev->nd_gc_node)); - if (nandfsdev->nd_dat_node) - NANDFS_UNSET_SYSTEMFILE(NTOV(nandfsdev->nd_dat_node)); - if (nandfsdev->nd_cp_node) - NANDFS_UNSET_SYSTEMFILE(NTOV(nandfsdev->nd_cp_node)); - if (nandfsdev->nd_su_node) - NANDFS_UNSET_SYSTEMFILE(NTOV(nandfsdev->nd_su_node)); -} - -static int -nandfs_check_fsdata_crc(struct nandfs_fsdata *fsdata) -{ - uint32_t fsdata_crc, comp_crc; - - if (fsdata->f_magic != NANDFS_FSDATA_MAGIC) - return (0); - - /* Preserve CRC */ - fsdata_crc = fsdata->f_sum; - - /* Calculate */ - fsdata->f_sum = (0); - comp_crc = crc32((uint8_t *)fsdata, fsdata->f_bytes); - - /* Restore */ - fsdata->f_sum = fsdata_crc; - - /* Check CRC */ - return (fsdata_crc == comp_crc); -} - -static int -nandfs_check_superblock_crc(struct nandfs_fsdata *fsdata, - struct nandfs_super_block *super) -{ - uint32_t super_crc, comp_crc; - - /* Check super block magic */ - if (super->s_magic != NANDFS_SUPER_MAGIC) - return (0); - - /* Preserve CRC */ - super_crc = super->s_sum; - - /* Calculate */ - super->s_sum = (0); - comp_crc = crc32((uint8_t *)super, fsdata->f_sbbytes); - - /* Restore */ - super->s_sum = super_crc; - - /* Check CRC */ - return (super_crc == comp_crc); -} - -static void -nandfs_calc_superblock_crc(struct nandfs_fsdata *fsdata, - struct nandfs_super_block *super) -{ - uint32_t comp_crc; - - /* Calculate */ - super->s_sum = 0; - comp_crc = crc32((uint8_t *)super, fsdata->f_sbbytes); - - /* Restore */ - super->s_sum = comp_crc; -} - -static int -nandfs_is_empty(u_char *area, int size) -{ - int i; - - for (i = 0; i < size; i++) - if (area[i] != 0xff) - return (0); - - return (1); -} - -static __inline int -nandfs_sblocks_in_esize(struct nandfs_device *fsdev) -{ - - return ((fsdev->nd_erasesize - NANDFS_SBLOCK_OFFSET_BYTES) / - sizeof(struct nandfs_super_block)); -} - -static __inline int -nandfs_max_sblocks(struct nandfs_device *fsdev) -{ - - return (NANDFS_NFSAREAS * nandfs_sblocks_in_esize(fsdev)); -} - -static __inline int -nandfs_sblocks_in_block(struct nandfs_device *fsdev) -{ - - return (fsdev->nd_devblocksize / sizeof(struct nandfs_super_block)); -} - -#if 0 -static __inline int -nandfs_sblocks_in_first_block(struct nandfs_device *fsdev) -{ - int n; - - n = nandfs_sblocks_in_block(fsdev) - - NANDFS_SBLOCK_OFFSET_BYTES / sizeof(struct nandfs_super_block); - if (n < 0) - n = 0; - - return (n); -} -#endif - -static int -nandfs_write_superblock_at(struct nandfs_device *fsdev, - struct nandfs_fsarea *fstp) -{ - struct nandfs_super_block *super, *supert; - struct buf *bp; - int sb_per_sector, sbs_in_fsd, read_block; - int index, pos, error; - off_t offset; - - DPRINTF(SYNC, ("%s: last_used %d nandfs_sblocks_in_esize %d\n", - __func__, fstp->last_used, nandfs_sblocks_in_esize(fsdev))); - if (fstp->last_used == nandfs_sblocks_in_esize(fsdev) - 1) - index = 0; - else - index = fstp->last_used + 1; - - super = &fsdev->nd_super; - supert = NULL; - - sb_per_sector = nandfs_sblocks_in_block(fsdev); - sbs_in_fsd = sizeof(struct nandfs_fsdata) / - sizeof(struct nandfs_super_block); - index += sbs_in_fsd; - offset = fstp->offset; - - DPRINTF(SYNC, ("%s: offset %#jx s_last_pseg %#jx s_last_cno %#jx " - "s_last_seq %#jx wtime %jd index %d\n", __func__, offset, - super->s_last_pseg, super->s_last_cno, super->s_last_seq, - super->s_wtime, index)); - - read_block = btodb(offset + rounddown(index, sb_per_sector) * - sizeof(struct nandfs_super_block)); - - DPRINTF(SYNC, ("%s: read_block %#x\n", __func__, read_block)); - - if (index == sbs_in_fsd) { - error = nandfs_erase(fsdev, offset, fsdev->nd_erasesize); - if (error) - return (error); - - error = bread(fsdev->nd_devvp, btodb(offset), - fsdev->nd_devblocksize, NOCRED, &bp); - if (error) { - printf("NANDFS: couldn't read initial data: %d\n", - error); - brelse(bp); - return (error); - } - memcpy(bp->b_data, &fsdev->nd_fsdata, sizeof(fsdev->nd_fsdata)); - /* - * 0xff-out the rest. This bp could be cached, so potentially - * b_data contains stale super blocks. - * - * We don't mind cached bp since most of the time we just add - * super blocks to already 0xff-out b_data and don't need to - * perform actual read. - */ - if (fsdev->nd_devblocksize > sizeof(fsdev->nd_fsdata)) - memset(bp->b_data + sizeof(fsdev->nd_fsdata), 0xff, - fsdev->nd_devblocksize - sizeof(fsdev->nd_fsdata)); - error = bwrite(bp); - if (error) { - printf("NANDFS: cannot rewrite initial data at %jx\n", - offset); - return (error); - } - } - - error = bread(fsdev->nd_devvp, read_block, fsdev->nd_devblocksize, - NOCRED, &bp); - if (error) { - brelse(bp); - return (error); - } - - supert = (struct nandfs_super_block *)(bp->b_data); - pos = index % sb_per_sector; - - DPRINTF(SYNC, ("%s: storing at %d\n", __func__, pos)); - memcpy(&supert[pos], super, sizeof(struct nandfs_super_block)); - - /* - * See comment above in code that performs erase. - */ - if (pos == 0) - memset(&supert[1], 0xff, - (sb_per_sector - 1) * sizeof(struct nandfs_super_block)); - - error = bwrite(bp); - if (error) { - printf("NANDFS: cannot update superblock at %jx\n", offset); - return (error); - } - - DPRINTF(SYNC, ("%s: fstp->last_used %d -> %d\n", __func__, - fstp->last_used, index - sbs_in_fsd)); - fstp->last_used = index - sbs_in_fsd; - - return (0); -} - -int -nandfs_write_superblock(struct nandfs_device *fsdev) -{ - struct nandfs_super_block *super; - struct timespec ts; - int error; - int i, j; - - vfs_timestamp(&ts); - - super = &fsdev->nd_super; - - super->s_last_pseg = fsdev->nd_last_pseg; - super->s_last_cno = fsdev->nd_last_cno; - super->s_last_seq = fsdev->nd_seg_sequence; - super->s_wtime = ts.tv_sec; - - nandfs_calc_superblock_crc(&fsdev->nd_fsdata, super); - - error = 0; - for (i = 0, j = fsdev->nd_last_fsarea; i < NANDFS_NFSAREAS; - i++, j = (j + 1 % NANDFS_NFSAREAS)) { - if (fsdev->nd_fsarea[j].flags & NANDFS_FSSTOR_FAILED) { - DPRINTF(SYNC, ("%s: skipping %d\n", __func__, j)); - continue; - } - error = nandfs_write_superblock_at(fsdev, &fsdev->nd_fsarea[j]); - if (error) { - printf("NANDFS: writing superblock at offset %d failed:" - "%d\n", j * fsdev->nd_erasesize, error); - fsdev->nd_fsarea[j].flags |= NANDFS_FSSTOR_FAILED; - } else - break; - } - - if (i == NANDFS_NFSAREAS) { - printf("NANDFS: superblock was not written\n"); - /* - * TODO: switch to read-only? - */ - return (error); - } else - fsdev->nd_last_fsarea = (j + 1) % NANDFS_NFSAREAS; - - return (0); -} - -static int -nandfs_select_fsdata(struct nandfs_device *fsdev, - struct nandfs_fsdata *fsdatat, struct nandfs_fsdata **fsdata, int nfsds) -{ - int i; - - *fsdata = NULL; - for (i = 0; i < nfsds; i++) { - DPRINTF(VOLUMES, ("%s: i %d f_magic %x f_crc %x\n", __func__, - i, fsdatat[i].f_magic, fsdatat[i].f_sum)); - if (!nandfs_check_fsdata_crc(&fsdatat[i])) - continue; - *fsdata = &fsdatat[i]; - break; - } - - return (*fsdata != NULL ? 0 : EINVAL); -} - -static int -nandfs_select_sb(struct nandfs_device *fsdev, - struct nandfs_super_block *supert, struct nandfs_super_block **super, - int nsbs) -{ - int i; - - *super = NULL; - for (i = 0; i < nsbs; i++) { - if (!nandfs_check_superblock_crc(&fsdev->nd_fsdata, &supert[i])) - continue; - DPRINTF(SYNC, ("%s: i %d s_last_cno %jx s_magic %x " - "s_wtime %jd\n", __func__, i, supert[i].s_last_cno, - supert[i].s_magic, supert[i].s_wtime)); - if (*super == NULL || supert[i].s_last_cno > - (*super)->s_last_cno) - *super = &supert[i]; - } - - return (*super != NULL ? 0 : EINVAL); -} - -static int -nandfs_read_structures_at(struct nandfs_device *fsdev, - struct nandfs_fsarea *fstp, struct nandfs_fsdata *fsdata, - struct nandfs_super_block *super) -{ - struct nandfs_super_block *tsuper, *tsuperd; - struct buf *bp; - int error, read_size; - int i; - int offset; - - offset = fstp->offset; - - if (fsdev->nd_erasesize > MAXBSIZE) - read_size = MAXBSIZE; - else - read_size = fsdev->nd_erasesize; - - error = bread(fsdev->nd_devvp, btodb(offset), read_size, NOCRED, &bp); - if (error) { - printf("couldn't read: %d\n", error); - brelse(bp); - fstp->flags |= NANDFS_FSSTOR_FAILED; - return (error); - } - - tsuper = super; - - memcpy(fsdata, bp->b_data, sizeof(struct nandfs_fsdata)); - memcpy(tsuper, (bp->b_data + sizeof(struct nandfs_fsdata)), - read_size - sizeof(struct nandfs_fsdata)); - brelse(bp); - - tsuper += (read_size - sizeof(struct nandfs_fsdata)) / - sizeof(struct nandfs_super_block); - - for (i = 1; i < fsdev->nd_erasesize / read_size; i++) { - error = bread(fsdev->nd_devvp, btodb(offset + i * read_size), - read_size, NOCRED, &bp); - if (error) { - printf("couldn't read: %d\n", error); - brelse(bp); - fstp->flags |= NANDFS_FSSTOR_FAILED; - return (error); - } - memcpy(tsuper, bp->b_data, read_size); - tsuper += read_size / sizeof(struct nandfs_super_block); - brelse(bp); - } - - tsuper -= 1; - fstp->last_used = nandfs_sblocks_in_esize(fsdev) - 1; - for (tsuperd = super - 1; (tsuper != tsuperd); tsuper -= 1) { - if (nandfs_is_empty((u_char *)tsuper, sizeof(*tsuper))) - fstp->last_used--; - else - break; - } - - DPRINTF(VOLUMES, ("%s: last_used %d\n", __func__, fstp->last_used)); - - return (0); -} - -static int -nandfs_read_structures(struct nandfs_device *fsdev) -{ - struct nandfs_fsdata *fsdata, *fsdatat; - struct nandfs_super_block *sblocks, *ssblock; - u_int nsbs, nfsds, i; - int error = 0; - int nrsbs; - - nfsds = NANDFS_NFSAREAS; - nsbs = nandfs_max_sblocks(fsdev); - - fsdatat = malloc(sizeof(struct nandfs_fsdata) * nfsds, M_NANDFSTEMP, - M_WAITOK | M_ZERO); - sblocks = malloc(sizeof(struct nandfs_super_block) * nsbs, M_NANDFSTEMP, - M_WAITOK | M_ZERO); - - nrsbs = 0; - for (i = 0; i < NANDFS_NFSAREAS; i++) { - fsdev->nd_fsarea[i].offset = i * fsdev->nd_erasesize; - error = nandfs_read_structures_at(fsdev, &fsdev->nd_fsarea[i], - &fsdatat[i], sblocks + nrsbs); - if (error) - continue; - nrsbs += (fsdev->nd_fsarea[i].last_used + 1); - if (fsdev->nd_fsarea[fsdev->nd_last_fsarea].last_used > - fsdev->nd_fsarea[i].last_used) - fsdev->nd_last_fsarea = i; - } - - if (nrsbs == 0) { - printf("nandfs: no valid superblocks found\n"); - error = EINVAL; - goto out; - } - - error = nandfs_select_fsdata(fsdev, fsdatat, &fsdata, nfsds); - if (error) - goto out; - memcpy(&fsdev->nd_fsdata, fsdata, sizeof(struct nandfs_fsdata)); - - error = nandfs_select_sb(fsdev, sblocks, &ssblock, nsbs); - if (error) - goto out; - - memcpy(&fsdev->nd_super, ssblock, sizeof(struct nandfs_super_block)); -out: - free(fsdatat, M_NANDFSTEMP); - free(sblocks, M_NANDFSTEMP); - - if (error == 0) - DPRINTF(VOLUMES, ("%s: selected sb with w_time %jd " - "last_pseg %#jx\n", __func__, fsdev->nd_super.s_wtime, - fsdev->nd_super.s_last_pseg)); - - return (error); -} - -static void -nandfs_unmount_base(struct nandfs_device *nandfsdev) -{ - int error; - - if (!nandfsdev) - return; - - /* Remove all our information */ - error = vinvalbuf(nandfsdev->nd_devvp, V_SAVE, 0, 0); - if (error) { - /* - * Flushing buffers failed when fs was umounting, can't do - * much now, just printf error and continue with umount. - */ - nandfs_error("%s(): error:%d when umounting FS\n", - __func__, error); - } - - /* Release the device's system nodes */ - nandfs_release_system_nodes(nandfsdev); -} - -static void -nandfs_get_ncleanseg(struct nandfs_device *nandfsdev) -{ - struct nandfs_seg_stat nss; - - nandfs_get_seg_stat(nandfsdev, &nss); - nandfsdev->nd_clean_segs = nss.nss_ncleansegs; - DPRINTF(VOLUMES, ("nandfs_mount: clean segs: %jx\n", - (uintmax_t)nandfsdev->nd_clean_segs)); -} - - -static int -nandfs_mount_base(struct nandfs_device *nandfsdev, struct mount *mp, - struct nandfs_args *args) -{ - uint32_t log_blocksize; - int error; - - /* Flush out any old buffers remaining from a previous use. */ - if ((error = vinvalbuf(nandfsdev->nd_devvp, V_SAVE, 0, 0))) - return (error); - - error = nandfs_read_structures(nandfsdev); - if (error) { - printf("nandfs: could not get valid filesystem structures\n"); - return (error); - } - - if (nandfsdev->nd_fsdata.f_rev_level != NANDFS_CURRENT_REV) { - printf("nandfs: unsupported file system revision: %d " - "(supported is %d).\n", nandfsdev->nd_fsdata.f_rev_level, - NANDFS_CURRENT_REV); - return (EINVAL); - } - - if (nandfsdev->nd_fsdata.f_erasesize != nandfsdev->nd_erasesize) { - printf("nandfs: erasesize mismatch (device %#x, fs %#x)\n", - nandfsdev->nd_erasesize, nandfsdev->nd_fsdata.f_erasesize); - return (EINVAL); - } - - /* Get our blocksize */ - log_blocksize = nandfsdev->nd_fsdata.f_log_block_size; - nandfsdev->nd_blocksize = (uint64_t) 1 << (log_blocksize + 10); - DPRINTF(VOLUMES, ("%s: blocksize:%x\n", __func__, - nandfsdev->nd_blocksize)); - - DPRINTF(VOLUMES, ("%s: accepted super block with cp %#jx\n", __func__, - (uintmax_t)nandfsdev->nd_super.s_last_cno)); - - /* Calculate dat structure parameters */ - nandfs_calc_mdt_consts(nandfsdev, &nandfsdev->nd_dat_mdt, - nandfsdev->nd_fsdata.f_dat_entry_size); - nandfs_calc_mdt_consts(nandfsdev, &nandfsdev->nd_ifile_mdt, - nandfsdev->nd_fsdata.f_inode_size); - - /* Search for the super root and roll forward when needed */ - if (nandfs_search_super_root(nandfsdev)) { - printf("Cannot find valid SuperRoot\n"); - return (EINVAL); - } - - nandfsdev->nd_mount_state = nandfsdev->nd_super.s_state; - if (nandfsdev->nd_mount_state != NANDFS_VALID_FS) { - printf("FS is seriously damaged, needs repairing\n"); - printf("aborting mount\n"); - return (EINVAL); - } - - /* - * FS should be ok now. The superblock and the last segsum could be - * updated from the repair so extract running values again. - */ - nandfsdev->nd_last_pseg = nandfsdev->nd_super.s_last_pseg; - nandfsdev->nd_seg_sequence = nandfsdev->nd_super.s_last_seq; - nandfsdev->nd_seg_num = nandfs_get_segnum_of_block(nandfsdev, - nandfsdev->nd_last_pseg); - nandfsdev->nd_next_seg_num = nandfs_get_segnum_of_block(nandfsdev, - nandfsdev->nd_last_segsum.ss_next); - nandfsdev->nd_ts.tv_sec = nandfsdev->nd_last_segsum.ss_create; - nandfsdev->nd_last_cno = nandfsdev->nd_super.s_last_cno; - nandfsdev->nd_fakevblk = 1; - /* - * FIXME: bogus calculation. Should use actual number of usable segments - * instead of total amount. - */ - nandfsdev->nd_segs_reserved = - nandfsdev->nd_fsdata.f_nsegments * - nandfsdev->nd_fsdata.f_r_segments_percentage / 100; - nandfsdev->nd_last_ino = NANDFS_USER_INO; - DPRINTF(VOLUMES, ("%s: last_pseg %#jx last_cno %#jx last_seq %#jx\n" - "fsdev: last_seg: seq %#jx num %#jx, next_seg_num %#jx " - "segs_reserved %#jx\n", - __func__, (uintmax_t)nandfsdev->nd_last_pseg, - (uintmax_t)nandfsdev->nd_last_cno, - (uintmax_t)nandfsdev->nd_seg_sequence, - (uintmax_t)nandfsdev->nd_seg_sequence, - (uintmax_t)nandfsdev->nd_seg_num, - (uintmax_t)nandfsdev->nd_next_seg_num, - (uintmax_t)nandfsdev->nd_segs_reserved)); - - DPRINTF(VOLUMES, ("nandfs_mount: accepted super root\n")); - - /* Create system vnodes for DAT, CP and SEGSUM */ - error = nandfs_create_system_nodes(nandfsdev); - if (error) - nandfs_unmount_base(nandfsdev); - - nandfs_get_ncleanseg(nandfsdev); - - return (error); -} - -static void -nandfs_unmount_device(struct nandfs_device *nandfsdev) -{ - - /* Is there anything? */ - if (nandfsdev == NULL) - return; - - /* Remove the device only if we're the last reference */ - nandfsdev->nd_refcnt--; - if (nandfsdev->nd_refcnt >= 1) - return; - - MPASS(nandfsdev->nd_syncer == NULL); - MPASS(nandfsdev->nd_cleaner == NULL); - MPASS(nandfsdev->nd_free_base == NULL); - - /* Unmount our base */ - nandfs_unmount_base(nandfsdev); - - /* Remove from our device list */ - SLIST_REMOVE(&nandfs_devices, nandfsdev, nandfs_device, nd_next_device); - - DROP_GIANT(); - g_topology_lock(); - g_vfs_close(nandfsdev->nd_gconsumer); - g_topology_unlock(); - PICKUP_GIANT(); - - DPRINTF(VOLUMES, ("closing device\n")); - - /* Clear our mount reference and release device node */ - vrele(nandfsdev->nd_devvp); - - dev_rel(nandfsdev->nd_devvp->v_rdev); - - /* Free our device info */ - cv_destroy(&nandfsdev->nd_sync_cv); - mtx_destroy(&nandfsdev->nd_sync_mtx); - cv_destroy(&nandfsdev->nd_clean_cv); - mtx_destroy(&nandfsdev->nd_clean_mtx); - mtx_destroy(&nandfsdev->nd_mutex); - lockdestroy(&nandfsdev->nd_seg_const); - free(nandfsdev, M_NANDFSMNT); -} - -static int -nandfs_check_mounts(struct nandfs_device *nandfsdev, struct mount *mp, - struct nandfs_args *args) -{ - struct nandfsmount *nmp; - uint64_t last_cno; - - /* no double-mounting of the same checkpoint */ - STAILQ_FOREACH(nmp, &nandfsdev->nd_mounts, nm_next_mount) { - if (nmp->nm_mount_args.cpno == args->cpno) - return (EBUSY); - } - - /* Allow readonly mounts without questioning here */ - if (mp->mnt_flag & MNT_RDONLY) - return (0); - - /* Read/write mount */ - STAILQ_FOREACH(nmp, &nandfsdev->nd_mounts, nm_next_mount) { - /* Only one RW mount on this device! */ - if ((nmp->nm_vfs_mountp->mnt_flag & MNT_RDONLY)==0) - return (EROFS); - /* RDONLY on last mountpoint is device busy */ - last_cno = nmp->nm_nandfsdev->nd_super.s_last_cno; - if (nmp->nm_mount_args.cpno == last_cno) - return (EBUSY); - } - - /* OK for now */ - return (0); -} - -static int -nandfs_mount_device(struct vnode *devvp, struct mount *mp, - struct nandfs_args *args, struct nandfs_device **nandfsdev_p) -{ - struct nandfs_device *nandfsdev; - struct g_provider *pp; - struct g_consumer *cp; - struct cdev *dev; - uint32_t erasesize; - int error, size; - int ronly; - - DPRINTF(VOLUMES, ("Mounting NANDFS device\n")); - - ronly = (mp->mnt_flag & MNT_RDONLY) != 0; - - /* Look up device in our nandfs_mountpoints */ - *nandfsdev_p = NULL; - SLIST_FOREACH(nandfsdev, &nandfs_devices, nd_next_device) - if (nandfsdev->nd_devvp == devvp) - break; - - if (nandfsdev) { - DPRINTF(VOLUMES, ("device already mounted\n")); - error = nandfs_check_mounts(nandfsdev, mp, args); - if (error) - return error; - nandfsdev->nd_refcnt++; - *nandfsdev_p = nandfsdev; - - if (!ronly) { - DROP_GIANT(); - g_topology_lock(); - error = g_access(nandfsdev->nd_gconsumer, 0, 1, 0); - g_topology_unlock(); - PICKUP_GIANT(); - } - return (error); - } - - vn_lock(devvp, LK_EXCLUSIVE | LK_RETRY); - dev = devvp->v_rdev; - dev_ref(dev); - DROP_GIANT(); - g_topology_lock(); - error = g_vfs_open(devvp, &cp, "nandfs", ronly ? 0 : 1); - pp = g_dev_getprovider(dev); - g_topology_unlock(); - PICKUP_GIANT(); - VOP_UNLOCK(devvp, 0); - if (error) { - dev_rel(dev); - return (error); - } - - nandfsdev = malloc(sizeof(struct nandfs_device), M_NANDFSMNT, M_WAITOK | M_ZERO); - - /* Initialise */ - nandfsdev->nd_refcnt = 1; - nandfsdev->nd_devvp = devvp; - nandfsdev->nd_syncing = 0; - nandfsdev->nd_cleaning = 0; - nandfsdev->nd_gconsumer = cp; - cv_init(&nandfsdev->nd_sync_cv, "nandfssync"); - mtx_init(&nandfsdev->nd_sync_mtx, "nffssyncmtx", NULL, MTX_DEF); - cv_init(&nandfsdev->nd_clean_cv, "nandfsclean"); - mtx_init(&nandfsdev->nd_clean_mtx, "nffscleanmtx", NULL, MTX_DEF); - mtx_init(&nandfsdev->nd_mutex, "nandfsdev lock", NULL, MTX_DEF); - lockinit(&nandfsdev->nd_seg_const, PVFS, "nffssegcon", VLKTIMEOUT, - LK_CANRECURSE); - STAILQ_INIT(&nandfsdev->nd_mounts); - - nandfsdev->nd_devsize = pp->mediasize; - nandfsdev->nd_devblocksize = pp->sectorsize; - - size = sizeof(erasesize); - error = g_io_getattr("NAND::blocksize", nandfsdev->nd_gconsumer, &size, - &erasesize); - if (error) { - DPRINTF(VOLUMES, ("couldn't get erasesize: %d\n", error)); - - if (error == ENOIOCTL || error == EOPNOTSUPP) { - /* - * We conclude that this is not NAND storage - */ - erasesize = NANDFS_DEF_ERASESIZE; - } else { - DROP_GIANT(); - g_topology_lock(); - g_vfs_close(nandfsdev->nd_gconsumer); - g_topology_unlock(); - PICKUP_GIANT(); - dev_rel(dev); - free(nandfsdev, M_NANDFSMNT); - return (error); - } - } - nandfsdev->nd_erasesize = erasesize; - - DPRINTF(VOLUMES, ("%s: erasesize %x\n", __func__, - nandfsdev->nd_erasesize)); - - /* Register nandfs_device in list */ - SLIST_INSERT_HEAD(&nandfs_devices, nandfsdev, nd_next_device); - - error = nandfs_mount_base(nandfsdev, mp, args); - if (error) { - /* Remove all our information */ - nandfs_unmount_device(nandfsdev); - return (EINVAL); - } - - nandfsdev->nd_maxfilesize = nandfs_get_maxfilesize(nandfsdev); - - *nandfsdev_p = nandfsdev; - DPRINTF(VOLUMES, ("NANDFS device mounted ok\n")); - - return (0); -} - -static int -nandfs_mount_checkpoint(struct nandfsmount *nmp) -{ - struct nandfs_cpfile_header *cphdr; - struct nandfs_checkpoint *cp; - struct nandfs_inode ifile_inode; - struct nandfs_node *cp_node; - struct buf *bp; - uint64_t ncp, nsn, cpno, fcpno, blocknr, last_cno; - uint32_t off, dlen; - int cp_per_block, error; - - cpno = nmp->nm_mount_args.cpno; - if (cpno == 0) - cpno = nmp->nm_nandfsdev->nd_super.s_last_cno; - - DPRINTF(VOLUMES, ("%s: trying to mount checkpoint number %"PRIu64"\n", - __func__, cpno)); - - cp_node = nmp->nm_nandfsdev->nd_cp_node; - - VOP_LOCK(NTOV(cp_node), LK_SHARED); - /* Get cpfile header from 1st block of cp file */ - error = nandfs_bread(cp_node, 0, NOCRED, 0, &bp); - if (error) { - brelse(bp); - VOP_UNLOCK(NTOV(cp_node), 0); - return (error); - } - - cphdr = (struct nandfs_cpfile_header *) bp->b_data; - ncp = cphdr->ch_ncheckpoints; - nsn = cphdr->ch_nsnapshots; - - brelse(bp); - - DPRINTF(VOLUMES, ("mount_nandfs: checkpoint header read in\n")); - DPRINTF(VOLUMES, ("\tNumber of checkpoints %"PRIu64"\n", ncp)); - DPRINTF(VOLUMES, ("\tNumber of snapshots %"PRIu64"\n", nsn)); - - /* Read in our specified checkpoint */ - dlen = nmp->nm_nandfsdev->nd_fsdata.f_checkpoint_size; - cp_per_block = nmp->nm_nandfsdev->nd_blocksize / dlen; - - fcpno = cpno + NANDFS_CPFILE_FIRST_CHECKPOINT_OFFSET - 1; - blocknr = fcpno / cp_per_block; - off = (fcpno % cp_per_block) * dlen; - error = nandfs_bread(cp_node, blocknr, NOCRED, 0, &bp); - if (error) { - brelse(bp); - VOP_UNLOCK(NTOV(cp_node), 0); - printf("mount_nandfs: couldn't read cp block %"PRIu64"\n", - fcpno); - return (EINVAL); - } - - /* Needs to be a valid checkpoint */ - cp = (struct nandfs_checkpoint *) ((uint8_t *) bp->b_data + off); - if (cp->cp_flags & NANDFS_CHECKPOINT_INVALID) { - printf("mount_nandfs: checkpoint marked invalid\n"); - brelse(bp); - VOP_UNLOCK(NTOV(cp_node), 0); - return (EINVAL); - } - - /* Is this really the checkpoint we want? */ - if (cp->cp_cno != cpno) { - printf("mount_nandfs: checkpoint file corrupt? " - "expected cpno %"PRIu64", found cpno %"PRIu64"\n", - cpno, cp->cp_cno); - brelse(bp); - VOP_UNLOCK(NTOV(cp_node), 0); - return (EINVAL); - } - - /* Check if it's a snapshot ! */ - last_cno = nmp->nm_nandfsdev->nd_super.s_last_cno; - if (cpno != last_cno) { - /* Only allow snapshots if not mounting on the last cp */ - if ((cp->cp_flags & NANDFS_CHECKPOINT_SNAPSHOT) == 0) { - printf( "mount_nandfs: checkpoint %"PRIu64" is not a " - "snapshot\n", cpno); - brelse(bp); - VOP_UNLOCK(NTOV(cp_node), 0); - return (EINVAL); - } - } - - ifile_inode = cp->cp_ifile_inode; - brelse(bp); - - /* Get ifile inode */ - error = nandfs_get_node_raw(nmp->nm_nandfsdev, NULL, NANDFS_IFILE_INO, - &ifile_inode, &nmp->nm_ifile_node); - if (error) { - printf("mount_nandfs: can't read ifile node\n"); - VOP_UNLOCK(NTOV(cp_node), 0); - return (EINVAL); - } - - NANDFS_SET_SYSTEMFILE(NTOV(nmp->nm_ifile_node)); - VOP_UNLOCK(NTOV(cp_node), 0); - /* Get root node? */ - - return (0); -} - -static void -free_nandfs_mountinfo(struct mount *mp) -{ - struct nandfsmount *nmp = VFSTONANDFS(mp); - - if (nmp == NULL) - return; - - free(nmp, M_NANDFSMNT); -} - -void -nandfs_wakeup_wait_sync(struct nandfs_device *nffsdev, int reason) -{ - char *reasons[] = { - "umount", - "vfssync", - "bdflush", - "fforce", - "fsync", - "ro_upd" - }; - - DPRINTF(SYNC, ("%s: %s\n", __func__, reasons[reason])); - mtx_lock(&nffsdev->nd_sync_mtx); - if (nffsdev->nd_syncing) - cv_wait(&nffsdev->nd_sync_cv, &nffsdev->nd_sync_mtx); - if (reason == SYNCER_UMOUNT) - nffsdev->nd_syncer_exit = 1; - nffsdev->nd_syncing = 1; - wakeup(&nffsdev->nd_syncing); - cv_wait(&nffsdev->nd_sync_cv, &nffsdev->nd_sync_mtx); - - mtx_unlock(&nffsdev->nd_sync_mtx); -} - -static void -nandfs_gc_finished(struct nandfs_device *nffsdev, int exit) -{ - int error; - - mtx_lock(&nffsdev->nd_sync_mtx); - nffsdev->nd_syncing = 0; - DPRINTF(SYNC, ("%s: cleaner finish\n", __func__)); - cv_broadcast(&nffsdev->nd_sync_cv); - mtx_unlock(&nffsdev->nd_sync_mtx); - if (!exit) { - error = tsleep(&nffsdev->nd_syncing, PRIBIO, "-", - hz * nandfs_sync_interval); - DPRINTF(SYNC, ("%s: cleaner waked up: %d\n", - __func__, error)); - } -} - -static void -nandfs_syncer(struct nandfsmount *nmp) -{ - struct nandfs_device *nffsdev; - struct mount *mp; - int flags, error; - - mp = nmp->nm_vfs_mountp; - nffsdev = nmp->nm_nandfsdev; - tsleep(&nffsdev->nd_syncing, PRIBIO, "-", hz * nandfs_sync_interval); - - while (!nffsdev->nd_syncer_exit) { - DPRINTF(SYNC, ("%s: syncer run\n", __func__)); - nffsdev->nd_syncing = 1; - - flags = (nmp->nm_flags & (NANDFS_FORCE_SYNCER | NANDFS_UMOUNT)); - - error = nandfs_segment_constructor(nmp, flags); - if (error) - nandfs_error("%s: error:%d when creating segments\n", - __func__, error); - - nmp->nm_flags &= ~flags; - - nandfs_gc_finished(nffsdev, 0); - } - - MPASS(nffsdev->nd_cleaner == NULL); - error = nandfs_segment_constructor(nmp, - NANDFS_FORCE_SYNCER | NANDFS_UMOUNT); - if (error) - nandfs_error("%s: error:%d when creating segments\n", - __func__, error); - nandfs_gc_finished(nffsdev, 1); - nffsdev->nd_syncer = NULL; - MPASS(nffsdev->nd_free_base == NULL); - - DPRINTF(SYNC, ("%s: exiting\n", __func__)); - kthread_exit(); -} - -static int -start_syncer(struct nandfsmount *nmp) -{ - int error; - - MPASS(nmp->nm_nandfsdev->nd_syncer == NULL); - - DPRINTF(SYNC, ("%s: start syncer\n", __func__)); - - nmp->nm_nandfsdev->nd_syncer_exit = 0; - - error = kthread_add((void(*)(void *))nandfs_syncer, nmp, NULL, - &nmp->nm_nandfsdev->nd_syncer, 0, 0, "nandfs_syncer"); - - if (error) - printf("nandfs: could not start syncer: %d\n", error); - - return (error); -} - -static int -stop_syncer(struct nandfsmount *nmp) -{ - - MPASS(nmp->nm_nandfsdev->nd_syncer != NULL); - - nandfs_wakeup_wait_sync(nmp->nm_nandfsdev, SYNCER_UMOUNT); - - DPRINTF(SYNC, ("%s: stop syncer\n", __func__)); - return (0); -} - -/* - * Mount null layer - */ -static int -nandfs_mount(struct mount *mp) -{ - struct nandfsmount *nmp; - struct vnode *devvp; - struct nameidata nd; - struct vfsoptlist *opts; - struct thread *td; - char *from; - int error = 0, flags; - - DPRINTF(VOLUMES, ("%s: mp = %p\n", __func__, (void *)mp)); - - td = curthread; - opts = mp->mnt_optnew; - - if (vfs_filteropt(opts, nandfs_opts)) - return (EINVAL); - - /* - * Update is a no-op - */ - if (mp->mnt_flag & MNT_UPDATE) { - nmp = VFSTONANDFS(mp); - if (vfs_flagopt(mp->mnt_optnew, "export", NULL, 0)) { - return (error); - } - if (!(nmp->nm_ronly) && vfs_flagopt(opts, "ro", NULL, 0)) { - vn_start_write(NULL, &mp, V_WAIT); - error = VFS_SYNC(mp, MNT_WAIT); - if (error) - return (error); - vn_finished_write(mp); - - flags = WRITECLOSE; - if (mp->mnt_flag & MNT_FORCE) - flags |= FORCECLOSE; - - nandfs_wakeup_wait_sync(nmp->nm_nandfsdev, - SYNCER_ROUPD); - error = vflush(mp, 0, flags, td); - if (error) - return (error); - - nandfs_stop_cleaner(nmp->nm_nandfsdev); - stop_syncer(nmp); - DROP_GIANT(); - g_topology_lock(); - g_access(nmp->nm_nandfsdev->nd_gconsumer, 0, -1, 0); - g_topology_unlock(); - PICKUP_GIANT(); - MNT_ILOCK(mp); - mp->mnt_flag |= MNT_RDONLY; - MNT_IUNLOCK(mp); - nmp->nm_ronly = 1; - - } else if ((nmp->nm_ronly) && - !vfs_flagopt(opts, "ro", NULL, 0)) { - /* - * Don't allow read-write snapshots. - */ - if (nmp->nm_mount_args.cpno != 0) - return (EROFS); - /* - * If upgrade to read-write by non-root, then verify - * that user has necessary permissions on the device. - */ - devvp = nmp->nm_nandfsdev->nd_devvp; - vn_lock(devvp, LK_EXCLUSIVE | LK_RETRY); - error = VOP_ACCESS(devvp, VREAD | VWRITE, - td->td_ucred, td); - if (error) { - error = priv_check(td, PRIV_VFS_MOUNT_PERM); - if (error) { - VOP_UNLOCK(devvp, 0); - return (error); - } - } - - VOP_UNLOCK(devvp, 0); - DROP_GIANT(); - g_topology_lock(); - error = g_access(nmp->nm_nandfsdev->nd_gconsumer, 0, 1, - 0); - g_topology_unlock(); - PICKUP_GIANT(); - if (error) - return (error); - - MNT_ILOCK(mp); - mp->mnt_flag &= ~MNT_RDONLY; - MNT_IUNLOCK(mp); - error = start_syncer(nmp); - if (error == 0) - error = nandfs_start_cleaner(nmp->nm_nandfsdev); - if (error) { - DROP_GIANT(); - g_topology_lock(); - g_access(nmp->nm_nandfsdev->nd_gconsumer, 0, -1, - 0); - g_topology_unlock(); - PICKUP_GIANT(); - return (error); - } - - nmp->nm_ronly = 0; - } - return (0); - } - - from = vfs_getopts(opts, "from", &error); - if (error) - return (error); - - /* - * Find device node - */ - NDINIT(&nd, LOOKUP, FOLLOW|LOCKLEAF, UIO_SYSSPACE, from, curthread); - error = namei(&nd); - if (error) - return (error); - NDFREE(&nd, NDF_ONLY_PNBUF); - - devvp = nd.ni_vp; - - if (!vn_isdisk(devvp, &error)) { - vput(devvp); - return (error); - } - - /* Check the access rights on the mount device */ - error = VOP_ACCESS(devvp, VREAD, curthread->td_ucred, curthread); - if (error) - error = priv_check(curthread, PRIV_VFS_MOUNT_PERM); - if (error) { - vput(devvp); - return (error); - } - - vfs_getnewfsid(mp); - - error = nandfs_mountfs(devvp, mp); - if (error) - return (error); - vfs_mountedfrom(mp, from); - - return (0); -} - -static int -nandfs_mountfs(struct vnode *devvp, struct mount *mp) -{ - struct nandfsmount *nmp = NULL; - struct nandfs_args *args = NULL; - struct nandfs_device *nandfsdev; - char *from; - int error, ronly; - char *cpno; - - ronly = (mp->mnt_flag & MNT_RDONLY) != 0; - - if (devvp->v_rdev->si_iosize_max != 0) - mp->mnt_iosize_max = devvp->v_rdev->si_iosize_max; - VOP_UNLOCK(devvp, 0); - - if (mp->mnt_iosize_max > MAXPHYS) - mp->mnt_iosize_max = MAXPHYS; - - from = vfs_getopts(mp->mnt_optnew, "from", &error); - if (error) - goto error; - - error = vfs_getopt(mp->mnt_optnew, "snap", (void **)&cpno, NULL); - if (error == ENOENT) - cpno = NULL; - else if (error) - goto error; - - args = (struct nandfs_args *)malloc(sizeof(struct nandfs_args), - M_NANDFSMNT, M_WAITOK | M_ZERO); - - if (cpno != NULL) - args->cpno = strtoul(cpno, (char **)NULL, 10); - else - args->cpno = 0; - args->fspec = from; - - if (args->cpno != 0 && !ronly) { - error = EROFS; - goto error; - } - - printf("WARNING: NANDFS is considered to be a highly experimental " - "feature in MidnightBSD.\n"); - - error = nandfs_mount_device(devvp, mp, args, &nandfsdev); - if (error) - goto error; - - nmp = (struct nandfsmount *) malloc(sizeof(struct nandfsmount), - M_NANDFSMNT, M_WAITOK | M_ZERO); - - mp->mnt_data = nmp; - nmp->nm_vfs_mountp = mp; - nmp->nm_ronly = ronly; - MNT_ILOCK(mp); - mp->mnt_flag |= MNT_LOCAL; - mp->mnt_kern_flag |= MNTK_USES_BCACHE; - MNT_IUNLOCK(mp); - nmp->nm_nandfsdev = nandfsdev; - /* Add our mountpoint */ - STAILQ_INSERT_TAIL(&nandfsdev->nd_mounts, nmp, nm_next_mount); - - if (args->cpno > nandfsdev->nd_last_cno) { - printf("WARNING: supplied checkpoint number (%jd) is greater " - "than last known checkpoint on filesystem (%jd). Mounting" - " checkpoint %jd\n", (uintmax_t)args->cpno, - (uintmax_t)nandfsdev->nd_last_cno, - (uintmax_t)nandfsdev->nd_last_cno); - args->cpno = nandfsdev->nd_last_cno; - } - - /* Setting up other parameters */ - nmp->nm_mount_args = *args; - free(args, M_NANDFSMNT); - error = nandfs_mount_checkpoint(nmp); - if (error) { - nandfs_unmount(mp, MNT_FORCE); - goto unmounted; - } - - if (!ronly) { - error = start_syncer(nmp); - if (error == 0) - error = nandfs_start_cleaner(nmp->nm_nandfsdev); - if (error) - nandfs_unmount(mp, MNT_FORCE); - } - - return (0); - -error: - if (args != NULL) - free(args, M_NANDFSMNT); - - if (nmp != NULL) { - free(nmp, M_NANDFSMNT); - mp->mnt_data = NULL; - } -unmounted: - return (error); -} - -static int -nandfs_unmount(struct mount *mp, int mntflags) -{ - struct nandfs_device *nandfsdev; - struct nandfsmount *nmp; - int error; - int flags = 0; - - DPRINTF(VOLUMES, ("%s: mp = %p\n", __func__, (void *)mp)); - - if (mntflags & MNT_FORCE) - flags |= FORCECLOSE; - - nmp = mp->mnt_data; - nandfsdev = nmp->nm_nandfsdev; - - error = vflush(mp, 0, flags | SKIPSYSTEM, curthread); - if (error) - return (error); - - if (!(nmp->nm_ronly)) { - nandfs_stop_cleaner(nandfsdev); - stop_syncer(nmp); - } - - if (nmp->nm_ifile_node) - NANDFS_UNSET_SYSTEMFILE(NTOV(nmp->nm_ifile_node)); - - /* Remove our mount point */ - STAILQ_REMOVE(&nandfsdev->nd_mounts, nmp, nandfsmount, nm_next_mount); - - /* Unmount the device itself when we're the last one */ - nandfs_unmount_device(nandfsdev); - - free_nandfs_mountinfo(mp); - - /* - * Finally, throw away the null_mount structure - */ - mp->mnt_data = 0; - MNT_ILOCK(mp); - mp->mnt_flag &= ~MNT_LOCAL; - MNT_IUNLOCK(mp); - - return (0); -} - -static int -nandfs_statfs(struct mount *mp, struct statfs *sbp) -{ - struct nandfsmount *nmp; - struct nandfs_device *nandfsdev; - struct nandfs_fsdata *fsdata; - struct nandfs_super_block *sb; - struct nandfs_block_group_desc *groups; - struct nandfs_node *ifile; - struct nandfs_mdt *mdt; - struct buf *bp; - int i, error; - uint32_t entries_per_group; - uint64_t files = 0; - - nmp = mp->mnt_data; - nandfsdev = nmp->nm_nandfsdev; - fsdata = &nandfsdev->nd_fsdata; - sb = &nandfsdev->nd_super; - ifile = nmp->nm_ifile_node; - mdt = &nandfsdev->nd_ifile_mdt; - entries_per_group = mdt->entries_per_group; - - VOP_LOCK(NTOV(ifile), LK_SHARED); - error = nandfs_bread(ifile, 0, NOCRED, 0, &bp); - if (error) { - brelse(bp); - VOP_UNLOCK(NTOV(ifile), 0); - return (error); - } - - groups = (struct nandfs_block_group_desc *)bp->b_data; - - for (i = 0; i < mdt->groups_per_desc_block; i++) - files += (entries_per_group - groups[i].bg_nfrees); - - brelse(bp); - VOP_UNLOCK(NTOV(ifile), 0); - - sbp->f_bsize = nandfsdev->nd_blocksize; - sbp->f_iosize = sbp->f_bsize; - sbp->f_blocks = fsdata->f_blocks_per_segment * fsdata->f_nsegments; - sbp->f_bfree = sb->s_free_blocks_count; - sbp->f_bavail = sbp->f_bfree; - sbp->f_files = files; - sbp->f_ffree = 0; - return (0); -} - -static int -nandfs_root(struct mount *mp, int flags, struct vnode **vpp) -{ - struct nandfsmount *nmp = VFSTONANDFS(mp); - struct nandfs_node *node; - int error; - - error = nandfs_get_node(nmp, NANDFS_ROOT_INO, &node); - if (error) - return (error); - - KASSERT(NTOV(node)->v_vflag & VV_ROOT, - ("root_vp->v_vflag & VV_ROOT")); - - *vpp = NTOV(node); - - return (error); -} - -static int -nandfs_vget(struct mount *mp, ino_t ino, int flags, struct vnode **vpp) -{ - struct nandfsmount *nmp = VFSTONANDFS(mp); - struct nandfs_node *node; - int error; - - error = nandfs_get_node(nmp, ino, &node); - if (node) - *vpp = NTOV(node); - - return (error); -} - -static int -nandfs_sync(struct mount *mp, int waitfor) -{ - struct nandfsmount *nmp = VFSTONANDFS(mp); - - DPRINTF(SYNC, ("%s: mp %p waitfor %d\n", __func__, mp, waitfor)); - - /* - * XXX: A hack to be removed soon - */ - if (waitfor == MNT_LAZY) - return (0); - if (waitfor == MNT_SUSPEND) - return (0); - nandfs_wakeup_wait_sync(nmp->nm_nandfsdev, SYNCER_VFS_SYNC); - return (0); -} - -static struct vfsops nandfs_vfsops = { - .vfs_init = nandfs_init, - .vfs_mount = nandfs_mount, - .vfs_root = nandfs_root, - .vfs_statfs = nandfs_statfs, - .vfs_uninit = nandfs_uninit, - .vfs_unmount = nandfs_unmount, - .vfs_vget = nandfs_vget, - .vfs_sync = nandfs_sync, -}; - -VFS_SET(nandfs_vfsops, nandfs, VFCF_LOOPBACK); diff --git a/sys/fs/nandfs/nandfs_vnops.c b/sys/fs/nandfs/nandfs_vnops.c deleted file mode 100644 index ecdf27700a8..00000000000 --- a/sys/fs/nandfs/nandfs_vnops.c +++ /dev/null @@ -1,2453 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2010-2012 Semihalf - * Copyright (c) 2008, 2009 Reinoud Zandijk - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * From: NetBSD: nilfs_vnops.c,v 1.2 2009/08/26 03:40:48 elad - */ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include - -#include -#include -#include - -extern uma_zone_t nandfs_node_zone; -static void nandfs_read_filebuf(struct nandfs_node *, struct buf *); -static void nandfs_itimes_locked(struct vnode *); -static int nandfs_truncate(struct vnode *, uint64_t); - -static vop_pathconf_t nandfs_pathconf; - -#define UPDATE_CLOSE 0 -#define UPDATE_WAIT 0 - -static int -nandfs_inactive(struct vop_inactive_args *ap) -{ - struct vnode *vp = ap->a_vp; - struct nandfs_node *node = VTON(vp); - int error = 0; - - DPRINTF(VNCALL, ("%s: vp:%p node:%p\n", __func__, vp, node)); - - if (node == NULL) { - DPRINTF(NODE, ("%s: inactive NULL node\n", __func__)); - return (0); - } - - if (node->nn_inode.i_mode != 0 && !(node->nn_inode.i_links_count)) { - nandfs_truncate(vp, 0); - error = nandfs_node_destroy(node); - if (error) - nandfs_error("%s: destroy node: %p\n", __func__, node); - node->nn_flags = 0; - vrecycle(vp); - } - - return (error); -} - -static int -nandfs_reclaim(struct vop_reclaim_args *ap) -{ - struct vnode *vp = ap->a_vp; - struct nandfs_node *nandfs_node = VTON(vp); - struct nandfs_device *fsdev = nandfs_node->nn_nandfsdev; - uint64_t ino = nandfs_node->nn_ino; - - DPRINTF(VNCALL, ("%s: vp:%p node:%p\n", __func__, vp, nandfs_node)); - - /* Invalidate all entries to a particular vnode. */ - cache_purge(vp); - - /* Destroy the vm object and flush associated pages. */ - vnode_destroy_vobject(vp); - - /* Remove from vfs hash if not system vnode */ - if (!NANDFS_SYS_NODE(nandfs_node->nn_ino)) - vfs_hash_remove(vp); - - /* Dispose all node knowledge */ - nandfs_dispose_node(&nandfs_node); - - if (!NANDFS_SYS_NODE(ino)) - NANDFS_WRITEUNLOCK(fsdev); - - return (0); -} - -static int -nandfs_read(struct vop_read_args *ap) -{ - struct vnode *vp = ap->a_vp; - struct nandfs_node *node = VTON(vp); - struct nandfs_device *nandfsdev = node->nn_nandfsdev; - struct uio *uio = ap->a_uio; - struct buf *bp; - uint64_t size; - uint32_t blocksize; - off_t bytesinfile; - ssize_t toread, off; - daddr_t lbn; - ssize_t resid; - int error = 0; - - if (uio->uio_resid == 0) - return (0); - - size = node->nn_inode.i_size; - if (uio->uio_offset >= size) - return (0); - - blocksize = nandfsdev->nd_blocksize; - bytesinfile = size - uio->uio_offset; - - resid = omin(uio->uio_resid, bytesinfile); - - while (resid) { - lbn = uio->uio_offset / blocksize; - off = uio->uio_offset & (blocksize - 1); - - toread = omin(resid, blocksize - off); - - DPRINTF(READ, ("nandfs_read bn: 0x%jx toread: 0x%zx (0x%x)\n", - (uintmax_t)lbn, toread, blocksize)); - - error = nandfs_bread(node, lbn, NOCRED, 0, &bp); - if (error) { - brelse(bp); - break; - } - - error = uiomove(bp->b_data + off, toread, uio); - if (error) { - brelse(bp); - break; - } - - brelse(bp); - resid -= toread; - } - - return (error); -} - -static int -nandfs_write(struct vop_write_args *ap) -{ - struct nandfs_device *fsdev; - struct nandfs_node *node; - struct vnode *vp; - struct uio *uio; - struct buf *bp; - uint64_t file_size, vblk; - uint32_t blocksize; - ssize_t towrite, off; - daddr_t lbn; - ssize_t resid; - int error, ioflag, modified; - - vp = ap->a_vp; - uio = ap->a_uio; - ioflag = ap->a_ioflag; - node = VTON(vp); - fsdev = node->nn_nandfsdev; - - if (nandfs_fs_full(fsdev)) - return (ENOSPC); - - DPRINTF(WRITE, ("nandfs_write called %#zx at %#jx\n", - uio->uio_resid, (uintmax_t)uio->uio_offset)); - - if (uio->uio_offset < 0) - return (EINVAL); - if (uio->uio_resid == 0) - return (0); - - blocksize = fsdev->nd_blocksize; - file_size = node->nn_inode.i_size; - - switch (vp->v_type) { - case VREG: - if (ioflag & IO_APPEND) - uio->uio_offset = file_size; - break; - case VDIR: - return (EISDIR); - case VLNK: - break; - default: - panic("%s: bad file type vp: %p", __func__, vp); - } - - /* If explicitly asked to append, uio_offset can be wrong? */ - if (ioflag & IO_APPEND) - uio->uio_offset = file_size; - - resid = uio->uio_resid; - modified = error = 0; - - while (uio->uio_resid) { - lbn = uio->uio_offset / blocksize; - off = uio->uio_offset & (blocksize - 1); - - towrite = omin(uio->uio_resid, blocksize - off); - - DPRINTF(WRITE, ("%s: lbn: 0x%jd toread: 0x%zx (0x%x)\n", - __func__, (uintmax_t)lbn, towrite, blocksize)); - - error = nandfs_bmap_lookup(node, lbn, &vblk); - if (error) - break; - - DPRINTF(WRITE, ("%s: lbn: 0x%jd toread: 0x%zx (0x%x) " - "vblk=%jx\n", __func__, (uintmax_t)lbn, towrite, blocksize, - vblk)); - - if (vblk != 0) - error = nandfs_bread(node, lbn, NOCRED, 0, &bp); - else - error = nandfs_bcreate(node, lbn, NOCRED, 0, &bp); - - DPRINTF(WRITE, ("%s: vp %p bread bp %p lbn %#jx\n", __func__, - vp, bp, (uintmax_t)lbn)); - if (error) { - if (bp) - brelse(bp); - break; - } - - error = uiomove((char *)bp->b_data + off, (int)towrite, uio); - if (error) - break; - - error = nandfs_dirty_buf(bp, 0); - if (error) - break; - - modified++; - } - - /* XXX proper handling when only part of file was properly written */ - if (modified) { - if (resid > uio->uio_resid && ap->a_cred && - ap->a_cred->cr_uid != 0) - node->nn_inode.i_mode &= ~(ISUID | ISGID); - - if (file_size < uio->uio_offset + uio->uio_resid) { - node->nn_inode.i_size = uio->uio_offset + - uio->uio_resid; - node->nn_flags |= IN_CHANGE | IN_UPDATE; - vnode_pager_setsize(vp, uio->uio_offset + - uio->uio_resid); - nandfs_itimes(vp); - } - } - - DPRINTF(WRITE, ("%s: return:%d\n", __func__, error)); - - return (error); -} - -static int -nandfs_lookup(struct vop_cachedlookup_args *ap) -{ - struct vnode *dvp, **vpp; - struct componentname *cnp; - struct ucred *cred; - struct thread *td; - struct nandfs_node *dir_node, *node; - struct nandfsmount *nmp; - uint64_t ino, off; - const char *name; - int namelen, nameiop, islastcn, mounted_ro; - int error, found; - - DPRINTF(VNCALL, ("%s\n", __func__)); - - dvp = ap->a_dvp; - vpp = ap->a_vpp; - *vpp = NULL; - - cnp = ap->a_cnp; - cred = cnp->cn_cred; - td = cnp->cn_thread; - - dir_node = VTON(dvp); - nmp = dir_node->nn_nmp; - - /* Simplify/clarification flags */ - nameiop = cnp->cn_nameiop; - islastcn = cnp->cn_flags & ISLASTCN; - mounted_ro = dvp->v_mount->mnt_flag & MNT_RDONLY; - - /* - * If requesting a modify on the last path element on a read-only - * filingsystem, reject lookup; - */ - if (islastcn && mounted_ro && (nameiop == DELETE || nameiop == RENAME)) - return (EROFS); - - if (dir_node->nn_inode.i_links_count == 0) - return (ENOENT); - - /* - * Obviously, the file is not (anymore) in the namecache, we have to - * search for it. There are three basic cases: '.', '..' and others. - * - * Following the guidelines of VOP_LOOKUP manpage and tmpfs. - */ - error = 0; - if ((cnp->cn_namelen == 1) && (cnp->cn_nameptr[0] == '.')) { - DPRINTF(LOOKUP, ("\tlookup '.'\n")); - /* Special case 1 '.' */ - VREF(dvp); - *vpp = dvp; - /* Done */ - } else if (cnp->cn_flags & ISDOTDOT) { - /* Special case 2 '..' */ - DPRINTF(LOOKUP, ("\tlookup '..'\n")); - - /* Get our node */ - name = ".."; - namelen = 2; - error = nandfs_lookup_name_in_dir(dvp, name, namelen, &ino, - &found, &off); - if (error) - goto out; - if (!found) - error = ENOENT; - - /* First unlock parent */ - VOP_UNLOCK(dvp, 0); - - if (error == 0) { - DPRINTF(LOOKUP, ("\tfound '..'\n")); - /* Try to create/reuse the node */ - error = nandfs_get_node(nmp, ino, &node); - - if (!error) { - DPRINTF(LOOKUP, - ("\tnode retrieved/created OK\n")); - *vpp = NTOV(node); - } - } - - /* Try to relock parent */ - vn_lock(dvp, LK_EXCLUSIVE | LK_RETRY); - } else { - DPRINTF(LOOKUP, ("\tlookup file\n")); - /* All other files */ - /* Look up filename in the directory returning its inode */ - name = cnp->cn_nameptr; - namelen = cnp->cn_namelen; - error = nandfs_lookup_name_in_dir(dvp, name, namelen, - &ino, &found, &off); - if (error) - goto out; - if (!found) { - DPRINTF(LOOKUP, ("\tNOT found\n")); - /* - * UGH, didn't find name. If we're creating or - * renaming on the last name this is OK and we ought - * to return EJUSTRETURN if its allowed to be created. - */ - error = ENOENT; - if ((nameiop == CREATE || nameiop == RENAME) && - islastcn) { - error = VOP_ACCESS(dvp, VWRITE, cred, td); - if (!error) { - /* keep the component name */ - cnp->cn_flags |= SAVENAME; - error = EJUSTRETURN; - } - } - /* Done */ - } else { - if (ino == NANDFS_WHT_INO) - cnp->cn_flags |= ISWHITEOUT; - - if ((cnp->cn_flags & ISWHITEOUT) && - (nameiop == LOOKUP)) - return (ENOENT); - - if ((nameiop == DELETE) && islastcn) { - if ((cnp->cn_flags & ISWHITEOUT) && - (cnp->cn_flags & DOWHITEOUT)) { - cnp->cn_flags |= SAVENAME; - dir_node->nn_diroff = off; - return (EJUSTRETURN); - } - - error = VOP_ACCESS(dvp, VWRITE, cred, - cnp->cn_thread); - if (error) - return (error); - - /* Try to create/reuse the node */ - error = nandfs_get_node(nmp, ino, &node); - if (!error) { - *vpp = NTOV(node); - node->nn_diroff = off; - } - - if ((dir_node->nn_inode.i_mode & ISVTX) && - cred->cr_uid != 0 && - cred->cr_uid != dir_node->nn_inode.i_uid && - node->nn_inode.i_uid != cred->cr_uid) { - vput(*vpp); - *vpp = NULL; - return (EPERM); - } - } else if ((nameiop == RENAME) && islastcn) { - error = VOP_ACCESS(dvp, VWRITE, cred, - cnp->cn_thread); - if (error) - return (error); - - /* Try to create/reuse the node */ - error = nandfs_get_node(nmp, ino, &node); - if (!error) { - *vpp = NTOV(node); - node->nn_diroff = off; - } - } else { - /* Try to create/reuse the node */ - error = nandfs_get_node(nmp, ino, &node); - if (!error) { - *vpp = NTOV(node); - node->nn_diroff = off; - } - } - } - } - -out: - /* - * Store result in the cache if requested. If we are creating a file, - * the file might not be found and thus putting it into the namecache - * might be seen as negative caching. - */ - if ((cnp->cn_flags & MAKEENTRY) != 0) - cache_enter(dvp, *vpp, cnp); - - return (error); - -} - -static int -nandfs_getattr(struct vop_getattr_args *ap) -{ - struct vnode *vp = ap->a_vp; - struct vattr *vap = ap->a_vap; - struct nandfs_node *node = VTON(vp); - struct nandfs_inode *inode = &node->nn_inode; - - DPRINTF(VNCALL, ("%s: vp: %p\n", __func__, vp)); - nandfs_itimes(vp); - - /* Basic info */ - VATTR_NULL(vap); - vap->va_atime.tv_sec = inode->i_mtime; - vap->va_atime.tv_nsec = inode->i_mtime_nsec; - vap->va_mtime.tv_sec = inode->i_mtime; - vap->va_mtime.tv_nsec = inode->i_mtime_nsec; - vap->va_ctime.tv_sec = inode->i_ctime; - vap->va_ctime.tv_nsec = inode->i_ctime_nsec; - vap->va_type = IFTOVT(inode->i_mode); - vap->va_mode = inode->i_mode & ~S_IFMT; - vap->va_nlink = inode->i_links_count; - vap->va_uid = inode->i_uid; - vap->va_gid = inode->i_gid; - vap->va_rdev = inode->i_special; - vap->va_fsid = vp->v_mount->mnt_stat.f_fsid.val[0]; - vap->va_fileid = node->nn_ino; - vap->va_size = inode->i_size; - vap->va_blocksize = node->nn_nandfsdev->nd_blocksize; - vap->va_gen = 0; - vap->va_flags = inode->i_flags; - vap->va_bytes = inode->i_blocks * vap->va_blocksize; - vap->va_filerev = 0; - vap->va_vaflags = 0; - - return (0); -} - -static int -nandfs_vtruncbuf(struct vnode *vp, uint64_t nblks) -{ - struct nandfs_device *nffsdev; - struct bufobj *bo; - struct buf *bp, *nbp; - - bo = &vp->v_bufobj; - nffsdev = VTON(vp)->nn_nandfsdev; - - ASSERT_VOP_LOCKED(vp, "nandfs_truncate"); -restart: - BO_LOCK(bo); -restart_locked: - TAILQ_FOREACH_SAFE(bp, &bo->bo_clean.bv_hd, b_bobufs, nbp) { - if (bp->b_lblkno < nblks) - continue; - if (BUF_LOCK(bp, LK_EXCLUSIVE | LK_NOWAIT, NULL)) - goto restart_locked; - - bremfree(bp); - bp->b_flags |= (B_INVAL | B_RELBUF); - bp->b_flags &= ~(B_ASYNC | B_MANAGED); - BO_UNLOCK(bo); - brelse(bp); - BO_LOCK(bo); - } - - TAILQ_FOREACH_SAFE(bp, &bo->bo_dirty.bv_hd, b_bobufs, nbp) { - if (bp->b_lblkno < nblks) - continue; - if (BUF_LOCK(bp, - LK_EXCLUSIVE | LK_SLEEPFAIL | LK_INTERLOCK, - BO_LOCKPTR(bo)) == ENOLCK) - goto restart; - bp->b_flags |= (B_INVAL | B_RELBUF); - bp->b_flags &= ~(B_ASYNC | B_MANAGED); - brelse(bp); - nandfs_dirty_bufs_decrement(nffsdev); - BO_LOCK(bo); - } - - BO_UNLOCK(bo); - - return (0); -} - -static int -nandfs_truncate(struct vnode *vp, uint64_t newsize) -{ - struct nandfs_device *nffsdev; - struct nandfs_node *node; - struct nandfs_inode *inode; - struct buf *bp = NULL; - uint64_t oblks, nblks, vblk, size, rest; - int error; - - node = VTON(vp); - nffsdev = node->nn_nandfsdev; - inode = &node->nn_inode; - - /* Calculate end of file */ - size = inode->i_size; - - if (newsize == size) { - node->nn_flags |= IN_CHANGE | IN_UPDATE; - nandfs_itimes(vp); - return (0); - } - - if (newsize > size) { - inode->i_size = newsize; - vnode_pager_setsize(vp, newsize); - node->nn_flags |= IN_CHANGE | IN_UPDATE; - nandfs_itimes(vp); - return (0); - } - - nblks = howmany(newsize, nffsdev->nd_blocksize); - oblks = howmany(size, nffsdev->nd_blocksize); - rest = newsize % nffsdev->nd_blocksize; - - if (rest) { - error = nandfs_bmap_lookup(node, nblks - 1, &vblk); - if (error) - return (error); - - if (vblk != 0) - error = nandfs_bread(node, nblks - 1, NOCRED, 0, &bp); - else - error = nandfs_bcreate(node, nblks - 1, NOCRED, 0, &bp); - - if (error) { - if (bp) - brelse(bp); - return (error); - } - - bzero((char *)bp->b_data + rest, - (u_int)(nffsdev->nd_blocksize - rest)); - error = nandfs_dirty_buf(bp, 0); - if (error) - return (error); - } - - DPRINTF(VNCALL, ("%s: vp %p oblks %jx nblks %jx\n", __func__, vp, oblks, - nblks)); - - error = nandfs_bmap_truncate_mapping(node, oblks - 1, nblks - 1); - if (error) { - if (bp) - nandfs_undirty_buf(bp); - return (error); - } - - error = nandfs_vtruncbuf(vp, nblks); - if (error) { - if (bp) - nandfs_undirty_buf(bp); - return (error); - } - - inode->i_size = newsize; - vnode_pager_setsize(vp, newsize); - node->nn_flags |= IN_CHANGE | IN_UPDATE; - nandfs_itimes(vp); - - return (error); -} - -static void -nandfs_itimes_locked(struct vnode *vp) -{ - struct nandfs_node *node; - struct nandfs_inode *inode; - struct timespec ts; - - ASSERT_VI_LOCKED(vp, __func__); - - node = VTON(vp); - inode = &node->nn_inode; - - if ((node->nn_flags & (IN_ACCESS | IN_CHANGE | IN_UPDATE)) == 0) - return; - - if (((vp->v_mount->mnt_kern_flag & - (MNTK_SUSPENDED | MNTK_SUSPEND)) == 0) || - (node->nn_flags & (IN_CHANGE | IN_UPDATE))) - node->nn_flags |= IN_MODIFIED; - - vfs_timestamp(&ts); - if (node->nn_flags & IN_UPDATE) { - inode->i_mtime = ts.tv_sec; - inode->i_mtime_nsec = ts.tv_nsec; - } - if (node->nn_flags & IN_CHANGE) { - inode->i_ctime = ts.tv_sec; - inode->i_ctime_nsec = ts.tv_nsec; - } - - node->nn_flags &= ~(IN_ACCESS | IN_CHANGE | IN_UPDATE); -} - -void -nandfs_itimes(struct vnode *vp) -{ - - VI_LOCK(vp); - nandfs_itimes_locked(vp); - VI_UNLOCK(vp); -} - -static int -nandfs_chmod(struct vnode *vp, int mode, struct ucred *cred, struct thread *td) -{ - struct nandfs_node *node = VTON(vp); - struct nandfs_inode *inode = &node->nn_inode; - uint16_t nmode; - int error = 0; - - DPRINTF(VNCALL, ("%s: vp %p, mode %x, cred %p, td %p\n", __func__, vp, - mode, cred, td)); - /* - * To modify the permissions on a file, must possess VADMIN - * for that file. - */ - if ((error = VOP_ACCESS(vp, VADMIN, cred, td))) - return (error); - - /* - * Privileged processes may set the sticky bit on non-directories, - * as well as set the setgid bit on a file with a group that the - * process is not a member of. Both of these are allowed in - * jail(8). - */ - if (vp->v_type != VDIR && (mode & S_ISTXT)) { - if (priv_check_cred(cred, PRIV_VFS_STICKYFILE, 0)) - return (EFTYPE); - } - if (!groupmember(inode->i_gid, cred) && (mode & ISGID)) { - error = priv_check_cred(cred, PRIV_VFS_SETGID, 0); - if (error) - return (error); - } - - /* - * Deny setting setuid if we are not the file owner. - */ - if ((mode & ISUID) && inode->i_uid != cred->cr_uid) { - error = priv_check_cred(cred, PRIV_VFS_ADMIN, 0); - if (error) - return (error); - } - - nmode = inode->i_mode; - nmode &= ~ALLPERMS; - nmode |= (mode & ALLPERMS); - inode->i_mode = nmode; - node->nn_flags |= IN_CHANGE; - - DPRINTF(VNCALL, ("%s: to mode %x\n", __func__, nmode)); - - return (error); -} - -static int -nandfs_chown(struct vnode *vp, uid_t uid, gid_t gid, struct ucred *cred, - struct thread *td) -{ - struct nandfs_node *node = VTON(vp); - struct nandfs_inode *inode = &node->nn_inode; - uid_t ouid; - gid_t ogid; - int error = 0; - - if (uid == (uid_t)VNOVAL) - uid = inode->i_uid; - if (gid == (gid_t)VNOVAL) - gid = inode->i_gid; - /* - * To modify the ownership of a file, must possess VADMIN for that - * file. - */ - if ((error = VOP_ACCESSX(vp, VWRITE_OWNER, cred, td))) - return (error); - /* - * To change the owner of a file, or change the group of a file to a - * group of which we are not a member, the caller must have - * privilege. - */ - if (((uid != inode->i_uid && uid != cred->cr_uid) || - (gid != inode->i_gid && !groupmember(gid, cred))) && - (error = priv_check_cred(cred, PRIV_VFS_CHOWN, 0))) - return (error); - ogid = inode->i_gid; - ouid = inode->i_uid; - - inode->i_gid = gid; - inode->i_uid = uid; - - node->nn_flags |= IN_CHANGE; - if ((inode->i_mode & (ISUID | ISGID)) && - (ouid != uid || ogid != gid)) { - if (priv_check_cred(cred, PRIV_VFS_RETAINSUGID, 0)) - inode->i_mode &= ~(ISUID | ISGID); - } - DPRINTF(VNCALL, ("%s: vp %p, cred %p, td %p - ret OK\n", __func__, vp, - cred, td)); - return (0); -} - -static int -nandfs_setattr(struct vop_setattr_args *ap) -{ - struct vnode *vp = ap->a_vp; - struct nandfs_node *node = VTON(vp); - struct nandfs_inode *inode = &node->nn_inode; - struct vattr *vap = ap->a_vap; - struct ucred *cred = ap->a_cred; - struct thread *td = curthread; - uint32_t flags; - int error = 0; - - if ((vap->va_type != VNON) || (vap->va_nlink != VNOVAL) || - (vap->va_fsid != VNOVAL) || (vap->va_fileid != VNOVAL) || - (vap->va_blocksize != VNOVAL) || (vap->va_rdev != VNOVAL) || - (vap->va_bytes != VNOVAL) || (vap->va_gen != VNOVAL)) { - DPRINTF(VNCALL, ("%s: unsettable attribute\n", __func__)); - return (EINVAL); - } - - if (vap->va_flags != VNOVAL) { - DPRINTF(VNCALL, ("%s: vp:%p td:%p flags:%lx\n", __func__, vp, - td, vap->va_flags)); - - if (vp->v_mount->mnt_flag & MNT_RDONLY) - return (EROFS); - /* - * Callers may only modify the file flags on objects they - * have VADMIN rights for. - */ - if ((error = VOP_ACCESS(vp, VADMIN, cred, td))) - return (error); - /* - * Unprivileged processes are not permitted to unset system - * flags, or modify flags if any system flags are set. - * Privileged non-jail processes may not modify system flags - * if securelevel > 0 and any existing system flags are set. - * Privileged jail processes behave like privileged non-jail - * processes if the PR_ALLOW_CHFLAGS permission bit is set; - * otherwise, they behave like unprivileged processes. - */ - - flags = inode->i_flags; - if (!priv_check_cred(cred, PRIV_VFS_SYSFLAGS, 0)) { - if (flags & (SF_NOUNLINK | SF_IMMUTABLE | SF_APPEND)) { - error = securelevel_gt(cred, 0); - if (error) - return (error); - } - /* Snapshot flag cannot be set or cleared */ - if (((vap->va_flags & SF_SNAPSHOT) != 0 && - (flags & SF_SNAPSHOT) == 0) || - ((vap->va_flags & SF_SNAPSHOT) == 0 && - (flags & SF_SNAPSHOT) != 0)) - return (EPERM); - - inode->i_flags = vap->va_flags; - } else { - if (flags & (SF_NOUNLINK | SF_IMMUTABLE | SF_APPEND) || - (vap->va_flags & UF_SETTABLE) != vap->va_flags) - return (EPERM); - - flags &= SF_SETTABLE; - flags |= (vap->va_flags & UF_SETTABLE); - inode->i_flags = flags; - } - node->nn_flags |= IN_CHANGE; - if (vap->va_flags & (IMMUTABLE | APPEND)) - return (0); - } - if (inode->i_flags & (IMMUTABLE | APPEND)) - return (EPERM); - - if (vap->va_size != (u_quad_t)VNOVAL) { - DPRINTF(VNCALL, ("%s: vp:%p td:%p size:%jx\n", __func__, vp, td, - (uintmax_t)vap->va_size)); - - switch (vp->v_type) { - case VDIR: - return (EISDIR); - case VLNK: - case VREG: - if (vp->v_mount->mnt_flag & MNT_RDONLY) - return (EROFS); - if ((inode->i_flags & SF_SNAPSHOT) != 0) - return (EPERM); - break; - default: - return (0); - } - - if (vap->va_size > node->nn_nandfsdev->nd_maxfilesize) - return (EFBIG); - - KASSERT((vp->v_type == VREG), ("Set size %d", vp->v_type)); - nandfs_truncate(vp, vap->va_size); - node->nn_flags |= IN_CHANGE; - - return (0); - } - - if (vap->va_uid != (uid_t)VNOVAL || vap->va_gid != (gid_t)VNOVAL) { - if (vp->v_mount->mnt_flag & MNT_RDONLY) - return (EROFS); - DPRINTF(VNCALL, ("%s: vp:%p td:%p uid/gid %x/%x\n", __func__, - vp, td, vap->va_uid, vap->va_gid)); - error = nandfs_chown(vp, vap->va_uid, vap->va_gid, cred, td); - if (error) - return (error); - } - - if (vap->va_mode != (mode_t)VNOVAL) { - if (vp->v_mount->mnt_flag & MNT_RDONLY) - return (EROFS); - DPRINTF(VNCALL, ("%s: vp:%p td:%p mode %x\n", __func__, vp, td, - vap->va_mode)); - - error = nandfs_chmod(vp, (int)vap->va_mode, cred, td); - if (error) - return (error); - } - if (vap->va_atime.tv_sec != VNOVAL || - vap->va_mtime.tv_sec != VNOVAL || - vap->va_birthtime.tv_sec != VNOVAL) { - DPRINTF(VNCALL, ("%s: vp:%p td:%p time a/m/b %jx/%jx/%jx\n", - __func__, vp, td, (uintmax_t)vap->va_atime.tv_sec, - (uintmax_t)vap->va_mtime.tv_sec, - (uintmax_t)vap->va_birthtime.tv_sec)); - - if (vap->va_atime.tv_sec != VNOVAL) - node->nn_flags |= IN_ACCESS; - if (vap->va_mtime.tv_sec != VNOVAL) - node->nn_flags |= IN_CHANGE | IN_UPDATE; - if (vap->va_birthtime.tv_sec != VNOVAL) - node->nn_flags |= IN_MODIFIED; - nandfs_itimes(vp); - return (0); - } - - return (0); -} - -static int -nandfs_open(struct vop_open_args *ap) -{ - struct nandfs_node *node = VTON(ap->a_vp); - uint64_t filesize; - - DPRINTF(VNCALL, ("nandfs_open called ap->a_mode %x\n", ap->a_mode)); - - if (ap->a_vp->v_type == VCHR || ap->a_vp->v_type == VBLK) - return (EOPNOTSUPP); - - if ((node->nn_inode.i_flags & APPEND) && - (ap->a_mode & (FWRITE | O_APPEND)) == FWRITE) - return (EPERM); - - filesize = node->nn_inode.i_size; - vnode_create_vobject(ap->a_vp, filesize, ap->a_td); - - return (0); -} - -static int -nandfs_close(struct vop_close_args *ap) -{ - struct vnode *vp = ap->a_vp; - struct nandfs_node *node = VTON(vp); - - DPRINTF(VNCALL, ("%s: vp %p node %p\n", __func__, vp, node)); - - mtx_lock(&vp->v_interlock); - if (vp->v_usecount > 1) - nandfs_itimes_locked(vp); - mtx_unlock(&vp->v_interlock); - - return (0); -} - -static int -nandfs_check_possible(struct vnode *vp, struct vattr *vap, mode_t mode) -{ - - /* Check if we are allowed to write */ - switch (vap->va_type) { - case VDIR: - case VLNK: - case VREG: - /* - * Normal nodes: check if we're on a read-only mounted - * filingsystem and bomb out if we're trying to write. - */ - if ((mode & VMODIFY_PERMS) && (vp->v_mount->mnt_flag & MNT_RDONLY)) - return (EROFS); - break; - case VBLK: - case VCHR: - case VSOCK: - case VFIFO: - /* - * Special nodes: even on read-only mounted filingsystems - * these are allowed to be written to if permissions allow. - */ - break; - default: - /* No idea what this is */ - return (EINVAL); - } - - /* No one may write immutable files */ - if ((mode & VWRITE) && (VTON(vp)->nn_inode.i_flags & IMMUTABLE)) - return (EPERM); - - return (0); -} - -static int -nandfs_check_permitted(struct vnode *vp, struct vattr *vap, mode_t mode, - struct ucred *cred) -{ - - return (vaccess(vp->v_type, vap->va_mode, vap->va_uid, vap->va_gid, mode, - cred, NULL)); -} - -static int -nandfs_advlock(struct vop_advlock_args *ap) -{ - struct nandfs_node *nvp; - quad_t size; - - nvp = VTON(ap->a_vp); - size = nvp->nn_inode.i_size; - return (lf_advlock(ap, &(nvp->nn_lockf), size)); -} - -static int -nandfs_access(struct vop_access_args *ap) -{ - struct vnode *vp = ap->a_vp; - accmode_t accmode = ap->a_accmode; - struct ucred *cred = ap->a_cred; - struct vattr vap; - int error; - - DPRINTF(VNCALL, ("%s: vp:%p mode: %x\n", __func__, vp, accmode)); - - error = VOP_GETATTR(vp, &vap, NULL); - if (error) - return (error); - - error = nandfs_check_possible(vp, &vap, accmode); - if (error) - return (error); - - error = nandfs_check_permitted(vp, &vap, accmode, cred); - - return (error); -} - -static int -nandfs_print(struct vop_print_args *ap) -{ - struct vnode *vp = ap->a_vp; - struct nandfs_node *nvp = VTON(vp); - - printf("\tvp=%p, nandfs_node=%p\n", vp, nvp); - printf("nandfs inode %#jx\n", (uintmax_t)nvp->nn_ino); - printf("flags = 0x%b\n", (u_int)nvp->nn_flags, PRINT_NODE_FLAGS); - - return (0); -} - -static void -nandfs_read_filebuf(struct nandfs_node *node, struct buf *bp) -{ - struct nandfs_device *nandfsdev = node->nn_nandfsdev; - struct buf *nbp; - nandfs_daddr_t vblk, pblk; - nandfs_lbn_t from; - uint32_t blocksize; - int error = 0; - int blk2dev = nandfsdev->nd_blocksize / DEV_BSIZE; - - /* - * Translate all the block sectors into a series of buffers to read - * asynchronously from the nandfs device. Note that this lookup may - * induce readin's too. - */ - - blocksize = nandfsdev->nd_blocksize; - if (bp->b_bcount / blocksize != 1) - panic("invalid b_count in bp %p\n", bp); - - from = bp->b_blkno; - - DPRINTF(READ, ("\tread in from inode %#jx blkno %#jx" - " count %#lx\n", (uintmax_t)node->nn_ino, from, - bp->b_bcount)); - - /* Get virtual block numbers for the vnode's buffer span */ - error = nandfs_bmap_lookup(node, from, &vblk); - if (error) { - bp->b_error = EINVAL; - bp->b_ioflags |= BIO_ERROR; - bufdone(bp); - return; - } - - /* Translate virtual block numbers to physical block numbers */ - error = nandfs_vtop(node, vblk, &pblk); - if (error) { - bp->b_error = EINVAL; - bp->b_ioflags |= BIO_ERROR; - bufdone(bp); - return; - } - - /* Issue translated blocks */ - bp->b_resid = bp->b_bcount; - - /* Note virtual block 0 marks not mapped */ - if (vblk == 0) { - vfs_bio_clrbuf(bp); - bufdone(bp); - return; - } - - nbp = bp; - nbp->b_blkno = pblk * blk2dev; - bp->b_iooffset = dbtob(nbp->b_blkno); - MPASS(bp->b_iooffset >= 0); - BO_STRATEGY(&nandfsdev->nd_devvp->v_bufobj, nbp); - nandfs_vblk_set(bp, vblk); - DPRINTF(READ, ("read_filebuf : ino %#jx blk %#jx -> " - "%#jx -> %#jx [bp %p]\n", (uintmax_t)node->nn_ino, - (uintmax_t)(from), (uintmax_t)vblk, - (uintmax_t)pblk, nbp)); -} - -static void -nandfs_write_filebuf(struct nandfs_node *node, struct buf *bp) -{ - struct nandfs_device *nandfsdev = node->nn_nandfsdev; - - bp->b_iooffset = dbtob(bp->b_blkno); - MPASS(bp->b_iooffset >= 0); - BO_STRATEGY(&nandfsdev->nd_devvp->v_bufobj, bp); -} - -static int -nandfs_strategy(struct vop_strategy_args *ap) -{ - struct vnode *vp = ap->a_vp; - struct buf *bp = ap->a_bp; - struct nandfs_node *node = VTON(vp); - - - /* check if we ought to be here */ - KASSERT((vp->v_type != VBLK && vp->v_type != VCHR), - ("nandfs_strategy on type %d", vp->v_type)); - - /* Translate if needed and pass on */ - if (bp->b_iocmd == BIO_READ) { - nandfs_read_filebuf(node, bp); - return (0); - } - - /* Send to segment collector */ - nandfs_write_filebuf(node, bp); - return (0); -} - -static int -nandfs_readdir(struct vop_readdir_args *ap) -{ - struct uio *uio = ap->a_uio; - struct vnode *vp = ap->a_vp; - struct nandfs_node *node = VTON(vp); - struct nandfs_dir_entry *ndirent; - struct dirent dirent; - struct buf *bp; - uint64_t file_size, diroffset, transoffset, blkoff; - uint64_t blocknr; - uint32_t blocksize = node->nn_nandfsdev->nd_blocksize; - uint8_t *pos, name_len; - int error; - - DPRINTF(READDIR, ("nandfs_readdir called\n")); - - if (vp->v_type != VDIR) - return (ENOTDIR); - - file_size = node->nn_inode.i_size; - DPRINTF(READDIR, ("nandfs_readdir filesize %jd resid %zd\n", - (uintmax_t)file_size, uio->uio_resid )); - - /* We are called just as long as we keep on pushing data in */ - error = 0; - if ((uio->uio_offset < file_size) && - (uio->uio_resid >= sizeof(struct dirent))) { - diroffset = uio->uio_offset; - transoffset = diroffset; - - blocknr = diroffset / blocksize; - blkoff = diroffset % blocksize; - error = nandfs_bread(node, blocknr, NOCRED, 0, &bp); - if (error) { - brelse(bp); - return (EIO); - } - while (diroffset < file_size) { - DPRINTF(READDIR, ("readdir : offset = %"PRIu64"\n", - diroffset)); - if (blkoff >= blocksize) { - blkoff = 0; blocknr++; - brelse(bp); - error = nandfs_bread(node, blocknr, NOCRED, 0, - &bp); - if (error) { - brelse(bp); - return (EIO); - } - } - - /* Read in one dirent */ - pos = (uint8_t *)bp->b_data + blkoff; - ndirent = (struct nandfs_dir_entry *)pos; - - name_len = ndirent->name_len; - memset(&dirent, 0, sizeof(dirent)); - dirent.d_fileno = ndirent->inode; - if (dirent.d_fileno) { - dirent.d_type = ndirent->file_type; - dirent.d_namlen = name_len; - strncpy(dirent.d_name, ndirent->name, name_len); - dirent.d_reclen = GENERIC_DIRSIZ(&dirent); - /* NOTE: d_off is the offset of the *next* entry. */ - dirent.d_off = diroffset + ndirent->rec_len; - dirent_terminate(&dirent); - DPRINTF(READDIR, ("copying `%*.*s`\n", name_len, - name_len, dirent.d_name)); - } - - /* - * If there isn't enough space in the uio to return a - * whole dirent, break off read - */ - if (uio->uio_resid < GENERIC_DIRSIZ(&dirent)) - break; - - /* Transfer */ - if (dirent.d_fileno) - uiomove(&dirent, dirent.d_reclen, uio); - - /* Advance */ - diroffset += ndirent->rec_len; - blkoff += ndirent->rec_len; - - /* Remember the last entry we transferred */ - transoffset = diroffset; - } - brelse(bp); - - /* Pass on last transferred offset */ - uio->uio_offset = transoffset; - } - - if (ap->a_eofflag) - *ap->a_eofflag = (uio->uio_offset >= file_size); - - return (error); -} - -static int -nandfs_dirempty(struct vnode *dvp, uint64_t parentino, struct ucred *cred) -{ - struct nandfs_node *dnode = VTON(dvp); - struct nandfs_dir_entry *dirent; - uint64_t file_size = dnode->nn_inode.i_size; - uint64_t blockcount = dnode->nn_inode.i_blocks; - uint64_t blocknr; - uint32_t blocksize = dnode->nn_nandfsdev->nd_blocksize; - uint32_t limit; - uint32_t off; - uint8_t *pos; - struct buf *bp; - int error; - - DPRINTF(LOOKUP, ("%s: dvp %p parentino %#jx cred %p\n", __func__, dvp, - (uintmax_t)parentino, cred)); - - KASSERT((file_size != 0), ("nandfs_dirempty for NULL dir %p", dvp)); - - blocknr = 0; - while (blocknr < blockcount) { - error = nandfs_bread(dnode, blocknr, NOCRED, 0, &bp); - if (error) { - brelse(bp); - return (0); - } - - pos = (uint8_t *)bp->b_data; - off = 0; - - if (blocknr == (blockcount - 1)) - limit = file_size % blocksize; - else - limit = blocksize; - - while (off < limit) { - dirent = (struct nandfs_dir_entry *)(pos + off); - off += dirent->rec_len; - - if (dirent->inode == 0) - continue; - - switch (dirent->name_len) { - case 0: - break; - case 1: - if (dirent->name[0] != '.') - goto notempty; - - KASSERT(dirent->inode == dnode->nn_ino, - (".'s inode does not match dir")); - break; - case 2: - if (dirent->name[0] != '.' && - dirent->name[1] != '.') - goto notempty; - - KASSERT(dirent->inode == parentino, - ("..'s inode does not match parent")); - break; - default: - goto notempty; - } - } - - brelse(bp); - blocknr++; - } - - return (1); -notempty: - brelse(bp); - return (0); -} - -static int -nandfs_link(struct vop_link_args *ap) -{ - struct vnode *tdvp = ap->a_tdvp; - struct vnode *vp = ap->a_vp; - struct componentname *cnp = ap->a_cnp; - struct nandfs_node *node = VTON(vp); - struct nandfs_inode *inode = &node->nn_inode; - int error; - - if (inode->i_links_count >= NANDFS_LINK_MAX) - return (EMLINK); - - if (inode->i_flags & (IMMUTABLE | APPEND)) - return (EPERM); - - /* Update link count */ - inode->i_links_count++; - - /* Add dir entry */ - error = nandfs_add_dirent(tdvp, node->nn_ino, cnp->cn_nameptr, - cnp->cn_namelen, IFTODT(inode->i_mode)); - if (error) { - inode->i_links_count--; - } - - node->nn_flags |= IN_CHANGE; - nandfs_itimes(vp); - DPRINTF(VNCALL, ("%s: tdvp %p vp %p cnp %p\n", - __func__, tdvp, vp, cnp)); - - return (0); -} - -static int -nandfs_create(struct vop_create_args *ap) -{ - struct vnode *dvp = ap->a_dvp; - struct vnode **vpp = ap->a_vpp; - struct componentname *cnp = ap->a_cnp; - uint16_t mode = MAKEIMODE(ap->a_vap->va_type, ap->a_vap->va_mode); - struct nandfs_node *dir_node = VTON(dvp); - struct nandfsmount *nmp = dir_node->nn_nmp; - struct nandfs_node *node; - int error; - - DPRINTF(VNCALL, ("%s: dvp %p\n", __func__, dvp)); - - if (nandfs_fs_full(dir_node->nn_nandfsdev)) - return (ENOSPC); - - /* Create new vnode/inode */ - error = nandfs_node_create(nmp, &node, mode); - if (error) - return (error); - node->nn_inode.i_gid = dir_node->nn_inode.i_gid; - node->nn_inode.i_uid = cnp->cn_cred->cr_uid; - - /* Add new dir entry */ - error = nandfs_add_dirent(dvp, node->nn_ino, cnp->cn_nameptr, - cnp->cn_namelen, IFTODT(mode)); - if (error) { - if (nandfs_node_destroy(node)) { - nandfs_error("%s: error destroying node %p\n", - __func__, node); - } - return (error); - } - *vpp = NTOV(node); - if ((cnp->cn_flags & MAKEENTRY) != 0) - cache_enter(dvp, *vpp, cnp); - - DPRINTF(VNCALL, ("created file vp %p nandnode %p ino %jx\n", *vpp, node, - (uintmax_t)node->nn_ino)); - return (0); -} - -static int -nandfs_remove(struct vop_remove_args *ap) -{ - struct vnode *vp = ap->a_vp; - struct vnode *dvp = ap->a_dvp; - struct nandfs_node *node = VTON(vp); - struct nandfs_node *dnode = VTON(dvp); - struct componentname *cnp = ap->a_cnp; - - DPRINTF(VNCALL, ("%s: dvp %p vp %p nandnode %p ino %#jx link %d\n", - __func__, dvp, vp, node, (uintmax_t)node->nn_ino, - node->nn_inode.i_links_count)); - - if (vp->v_type == VDIR) - return (EISDIR); - - /* Files marked as immutable or append-only cannot be deleted. */ - if ((node->nn_inode.i_flags & (IMMUTABLE | APPEND | NOUNLINK)) || - (dnode->nn_inode.i_flags & APPEND)) - return (EPERM); - - nandfs_remove_dirent(dvp, node, cnp); - node->nn_inode.i_links_count--; - node->nn_flags |= IN_CHANGE; - - return (0); -} - -/* - * Check if source directory is in the path of the target directory. - * Target is supplied locked, source is unlocked. - * The target is always vput before returning. - */ -static int -nandfs_checkpath(struct nandfs_node *src, struct nandfs_node *dest, - struct ucred *cred) -{ - struct vnode *vp; - int error, rootino; - struct nandfs_dir_entry dirent; - - vp = NTOV(dest); - if (src->nn_ino == dest->nn_ino) { - error = EEXIST; - goto out; - } - rootino = NANDFS_ROOT_INO; - error = 0; - if (dest->nn_ino == rootino) - goto out; - - for (;;) { - if (vp->v_type != VDIR) { - error = ENOTDIR; - break; - } - - error = vn_rdwr(UIO_READ, vp, (caddr_t)&dirent, - NANDFS_DIR_REC_LEN(2), (off_t)0, UIO_SYSSPACE, - IO_NODELOCKED | IO_NOMACCHECK, cred, NOCRED, - NULL, NULL); - if (error != 0) - break; - if (dirent.name_len != 2 || - dirent.name[0] != '.' || - dirent.name[1] != '.') { - error = ENOTDIR; - break; - } - if (dirent.inode == src->nn_ino) { - error = EINVAL; - break; - } - if (dirent.inode == rootino) - break; - vput(vp); - if ((error = VFS_VGET(vp->v_mount, dirent.inode, - LK_EXCLUSIVE, &vp)) != 0) { - vp = NULL; - break; - } - } - -out: - if (error == ENOTDIR) - printf("checkpath: .. not a directory\n"); - if (vp != NULL) - vput(vp); - return (error); -} - -static int -nandfs_rename(struct vop_rename_args *ap) -{ - struct vnode *tvp = ap->a_tvp; - struct vnode *tdvp = ap->a_tdvp; - struct vnode *fvp = ap->a_fvp; - struct vnode *fdvp = ap->a_fdvp; - struct componentname *tcnp = ap->a_tcnp; - struct componentname *fcnp = ap->a_fcnp; - int doingdirectory = 0, oldparent = 0, newparent = 0; - int error = 0; - - struct nandfs_node *fdnode, *fnode, *fnode1; - struct nandfs_node *tdnode = VTON(tdvp); - struct nandfs_node *tnode; - - uint32_t tdflags, fflags, fdflags; - uint16_t mode; - - DPRINTF(VNCALL, ("%s: fdvp:%p fvp:%p tdvp:%p tdp:%p\n", __func__, fdvp, - fvp, tdvp, tvp)); - - /* - * Check for cross-device rename. - */ - if ((fvp->v_mount != tdvp->v_mount) || - (tvp && (fvp->v_mount != tvp->v_mount))) { - error = EXDEV; -abortit: - if (tdvp == tvp) - vrele(tdvp); - else - vput(tdvp); - if (tvp) - vput(tvp); - vrele(fdvp); - vrele(fvp); - return (error); - } - - tdflags = tdnode->nn_inode.i_flags; - if (tvp && - ((VTON(tvp)->nn_inode.i_flags & (NOUNLINK | IMMUTABLE | APPEND)) || - (tdflags & APPEND))) { - error = EPERM; - goto abortit; - } - - /* - * Renaming a file to itself has no effect. The upper layers should - * not call us in that case. Temporarily just warn if they do. - */ - if (fvp == tvp) { - printf("nandfs_rename: fvp == tvp (can't happen)\n"); - error = 0; - goto abortit; - } - - if ((error = vn_lock(fvp, LK_EXCLUSIVE)) != 0) - goto abortit; - - fdnode = VTON(fdvp); - fnode = VTON(fvp); - - if (fnode->nn_inode.i_links_count >= NANDFS_LINK_MAX) { - VOP_UNLOCK(fvp, 0); - error = EMLINK; - goto abortit; - } - - fflags = fnode->nn_inode.i_flags; - fdflags = fdnode->nn_inode.i_flags; - - if ((fflags & (NOUNLINK | IMMUTABLE | APPEND)) || - (fdflags & APPEND)) { - VOP_UNLOCK(fvp, 0); - error = EPERM; - goto abortit; - } - - mode = fnode->nn_inode.i_mode; - if ((mode & S_IFMT) == S_IFDIR) { - /* - * Avoid ".", "..", and aliases of "." for obvious reasons. - */ - - if ((fcnp->cn_namelen == 1 && fcnp->cn_nameptr[0] == '.') || - (fdvp == fvp) || - ((fcnp->cn_flags | tcnp->cn_flags) & ISDOTDOT) || - (fnode->nn_flags & IN_RENAME)) { - VOP_UNLOCK(fvp, 0); - error = EINVAL; - goto abortit; - } - fnode->nn_flags |= IN_RENAME; - doingdirectory = 1; - DPRINTF(VNCALL, ("%s: doingdirectory dvp %p\n", __func__, - tdvp)); - oldparent = fdnode->nn_ino; - } - - vrele(fdvp); - - tnode = NULL; - if (tvp) - tnode = VTON(tvp); - - /* - * Bump link count on fvp while we are moving stuff around. If we - * crash before completing the work, the link count may be wrong - * but correctable. - */ - fnode->nn_inode.i_links_count++; - - /* Check for in path moving XXX */ - error = VOP_ACCESS(fvp, VWRITE, tcnp->cn_cred, tcnp->cn_thread); - VOP_UNLOCK(fvp, 0); - if (oldparent != tdnode->nn_ino) - newparent = tdnode->nn_ino; - if (doingdirectory && newparent) { - if (error) /* write access check above */ - goto bad; - if (tnode != NULL) - vput(tvp); - - error = nandfs_checkpath(fnode, tdnode, tcnp->cn_cred); - if (error) - goto out; - - VREF(tdvp); - error = relookup(tdvp, &tvp, tcnp); - if (error) - goto out; - vrele(tdvp); - tdnode = VTON(tdvp); - tnode = NULL; - if (tvp) - tnode = VTON(tvp); - } - - /* - * If the target doesn't exist, link the target to the source and - * unlink the source. Otherwise, rewrite the target directory to - * reference the source and remove the original entry. - */ - - if (tvp == NULL) { - /* - * Account for ".." in new directory. - */ - if (doingdirectory && fdvp != tdvp) - tdnode->nn_inode.i_links_count++; - - DPRINTF(VNCALL, ("%s: new entry in dvp:%p\n", __func__, tdvp)); - /* - * Add name in new directory. - */ - error = nandfs_add_dirent(tdvp, fnode->nn_ino, tcnp->cn_nameptr, - tcnp->cn_namelen, IFTODT(fnode->nn_inode.i_mode)); - if (error) { - if (doingdirectory && fdvp != tdvp) - tdnode->nn_inode.i_links_count--; - goto bad; - } - - vput(tdvp); - } else { - /* - * If the parent directory is "sticky", then the user must - * own the parent directory, or the destination of the rename, - * otherwise the destination may not be changed (except by - * root). This implements append-only directories. - */ - if ((tdnode->nn_inode.i_mode & S_ISTXT) && - tcnp->cn_cred->cr_uid != 0 && - tcnp->cn_cred->cr_uid != tdnode->nn_inode.i_uid && - tnode->nn_inode.i_uid != tcnp->cn_cred->cr_uid) { - error = EPERM; - goto bad; - } - /* - * Target must be empty if a directory and have no links - * to it. Also, ensure source and target are compatible - * (both directories, or both not directories). - */ - mode = tnode->nn_inode.i_mode; - if ((mode & S_IFMT) == S_IFDIR) { - if (!nandfs_dirempty(tvp, tdnode->nn_ino, - tcnp->cn_cred)) { - error = ENOTEMPTY; - goto bad; - } - if (!doingdirectory) { - error = ENOTDIR; - goto bad; - } - /* - * Update name cache since directory is going away. - */ - cache_purge(tdvp); - } else if (doingdirectory) { - error = EISDIR; - goto bad; - } - - DPRINTF(VNCALL, ("%s: update entry dvp:%p\n", __func__, tdvp)); - /* - * Change name tcnp in tdvp to point at fvp. - */ - error = nandfs_update_dirent(tdvp, fnode, tnode); - if (error) - goto bad; - - if (doingdirectory && !newparent) - tdnode->nn_inode.i_links_count--; - - vput(tdvp); - - tnode->nn_inode.i_links_count--; - vput(tvp); - tnode = NULL; - } - - /* - * Unlink the source. - */ - fcnp->cn_flags &= ~MODMASK; - fcnp->cn_flags |= LOCKPARENT | LOCKLEAF; - VREF(fdvp); - error = relookup(fdvp, &fvp, fcnp); - if (error == 0) - vrele(fdvp); - if (fvp != NULL) { - fnode1 = VTON(fvp); - fdnode = VTON(fdvp); - } else { - /* - * From name has disappeared. - */ - if (doingdirectory) - panic("nandfs_rename: lost dir entry"); - vrele(ap->a_fvp); - return (0); - } - - DPRINTF(VNCALL, ("%s: unlink source fnode:%p\n", __func__, fnode)); - - /* - * Ensure that the directory entry still exists and has not - * changed while the new name has been entered. If the source is - * a file then the entry may have been unlinked or renamed. In - * either case there is no further work to be done. If the source - * is a directory then it cannot have been rmdir'ed; its link - * count of three would cause a rmdir to fail with ENOTEMPTY. - * The IN_RENAME flag ensures that it cannot be moved by another - * rename. - */ - if (fnode != fnode1) { - if (doingdirectory) - panic("nandfs: lost dir entry"); - } else { - /* - * If the source is a directory with a - * new parent, the link count of the old - * parent directory must be decremented - * and ".." set to point to the new parent. - */ - if (doingdirectory && newparent) { - DPRINTF(VNCALL, ("%s: new parent %#jx -> %#jx\n", - __func__, (uintmax_t) oldparent, - (uintmax_t) newparent)); - error = nandfs_update_parent_dir(fvp, newparent); - if (!error) { - fdnode->nn_inode.i_links_count--; - fdnode->nn_flags |= IN_CHANGE; - } - } - error = nandfs_remove_dirent(fdvp, fnode, fcnp); - if (!error) { - fnode->nn_inode.i_links_count--; - fnode->nn_flags |= IN_CHANGE; - } - fnode->nn_flags &= ~IN_RENAME; - } - if (fdnode) - vput(fdvp); - if (fnode) - vput(fvp); - vrele(ap->a_fvp); - return (error); - -bad: - DPRINTF(VNCALL, ("%s: error:%d\n", __func__, error)); - if (tnode) - vput(NTOV(tnode)); - vput(NTOV(tdnode)); -out: - if (doingdirectory) - fnode->nn_flags &= ~IN_RENAME; - if (vn_lock(fvp, LK_EXCLUSIVE) == 0) { - fnode->nn_inode.i_links_count--; - fnode->nn_flags |= IN_CHANGE; - fnode->nn_flags &= ~IN_RENAME; - vput(fvp); - } else - vrele(fvp); - return (error); -} - -static int -nandfs_mkdir(struct vop_mkdir_args *ap) -{ - struct vnode *dvp = ap->a_dvp; - struct vnode **vpp = ap->a_vpp; - struct componentname *cnp = ap->a_cnp; - struct nandfs_node *dir_node = VTON(dvp); - struct nandfs_inode *dir_inode = &dir_node->nn_inode; - struct nandfs_node *node; - struct nandfsmount *nmp = dir_node->nn_nmp; - uint16_t mode = MAKEIMODE(ap->a_vap->va_type, ap->a_vap->va_mode); - int error; - - DPRINTF(VNCALL, ("%s: dvp %p\n", __func__, dvp)); - - if (nandfs_fs_full(dir_node->nn_nandfsdev)) - return (ENOSPC); - - if (dir_inode->i_links_count >= NANDFS_LINK_MAX) - return (EMLINK); - - error = nandfs_node_create(nmp, &node, mode); - if (error) - return (error); - - node->nn_inode.i_gid = dir_node->nn_inode.i_gid; - node->nn_inode.i_uid = cnp->cn_cred->cr_uid; - - *vpp = NTOV(node); - - error = nandfs_add_dirent(dvp, node->nn_ino, cnp->cn_nameptr, - cnp->cn_namelen, IFTODT(mode)); - if (error) { - vput(*vpp); - return (error); - } - - dir_node->nn_inode.i_links_count++; - dir_node->nn_flags |= IN_CHANGE; - - error = nandfs_init_dir(NTOV(node), node->nn_ino, dir_node->nn_ino); - if (error) { - vput(NTOV(node)); - return (error); - } - - DPRINTF(VNCALL, ("created dir vp %p nandnode %p ino %jx\n", *vpp, node, - (uintmax_t)node->nn_ino)); - return (0); -} - -static int -nandfs_mknod(struct vop_mknod_args *ap) -{ - struct vnode *dvp = ap->a_dvp; - struct vnode **vpp = ap->a_vpp; - struct vattr *vap = ap->a_vap; - uint16_t mode = MAKEIMODE(vap->va_type, vap->va_mode); - struct componentname *cnp = ap->a_cnp; - struct nandfs_node *dir_node = VTON(dvp); - struct nandfsmount *nmp = dir_node->nn_nmp; - struct nandfs_node *node; - int error; - - if (nandfs_fs_full(dir_node->nn_nandfsdev)) - return (ENOSPC); - - error = nandfs_node_create(nmp, &node, mode); - if (error) - return (error); - node->nn_inode.i_gid = dir_node->nn_inode.i_gid; - node->nn_inode.i_uid = cnp->cn_cred->cr_uid; - if (vap->va_rdev != VNOVAL) - node->nn_inode.i_special = vap->va_rdev; - - *vpp = NTOV(node); - - if (nandfs_add_dirent(dvp, node->nn_ino, cnp->cn_nameptr, - cnp->cn_namelen, IFTODT(mode))) { - vput(*vpp); - return (ENOTDIR); - } - - node->nn_flags |= IN_ACCESS | IN_CHANGE | IN_UPDATE; - - return (0); -} - -static int -nandfs_symlink(struct vop_symlink_args *ap) -{ - struct vnode **vpp = ap->a_vpp; - struct vnode *dvp = ap->a_dvp; - uint16_t mode = MAKEIMODE(ap->a_vap->va_type, ap->a_vap->va_mode); - struct componentname *cnp = ap->a_cnp; - struct nandfs_node *dir_node = VTON(dvp); - struct nandfsmount *nmp = dir_node->nn_nmp; - struct nandfs_node *node; - int len, error; - - if (nandfs_fs_full(dir_node->nn_nandfsdev)) - return (ENOSPC); - - error = nandfs_node_create(nmp, &node, S_IFLNK | mode); - if (error) - return (error); - node->nn_inode.i_gid = dir_node->nn_inode.i_gid; - node->nn_inode.i_uid = cnp->cn_cred->cr_uid; - - *vpp = NTOV(node); - - if (nandfs_add_dirent(dvp, node->nn_ino, cnp->cn_nameptr, - cnp->cn_namelen, IFTODT(mode))) { - vput(*vpp); - return (ENOTDIR); - } - - - len = strlen(ap->a_target); - error = vn_rdwr(UIO_WRITE, *vpp, ap->a_target, len, (off_t)0, - UIO_SYSSPACE, IO_NODELOCKED | IO_NOMACCHECK, - cnp->cn_cred, NOCRED, NULL, NULL); - if (error) - vput(*vpp); - - return (error); -} - -static int -nandfs_readlink(struct vop_readlink_args *ap) -{ - struct vnode *vp = ap->a_vp; - - return (VOP_READ(vp, ap->a_uio, 0, ap->a_cred)); -} - -static int -nandfs_rmdir(struct vop_rmdir_args *ap) -{ - struct vnode *vp = ap->a_vp; - struct vnode *dvp = ap->a_dvp; - struct componentname *cnp = ap->a_cnp; - struct nandfs_node *node, *dnode; - uint32_t dflag, flag; - int error = 0; - - node = VTON(vp); - dnode = VTON(dvp); - - /* Files marked as immutable or append-only cannot be deleted. */ - if ((node->nn_inode.i_flags & (IMMUTABLE | APPEND | NOUNLINK)) || - (dnode->nn_inode.i_flags & APPEND)) - return (EPERM); - - DPRINTF(VNCALL, ("%s: dvp %p vp %p nandnode %p ino %#jx\n", __func__, - dvp, vp, node, (uintmax_t)node->nn_ino)); - - if (node->nn_inode.i_links_count < 2) - return (EINVAL); - - if (!nandfs_dirempty(vp, dnode->nn_ino, cnp->cn_cred)) - return (ENOTEMPTY); - - /* Files marked as immutable or append-only cannot be deleted. */ - dflag = dnode->nn_inode.i_flags; - flag = node->nn_inode.i_flags; - if ((dflag & APPEND) || - (flag & (NOUNLINK | IMMUTABLE | APPEND))) { - return (EPERM); - } - - if (vp->v_mountedhere != 0) - return (EINVAL); - - nandfs_remove_dirent(dvp, node, cnp); - dnode->nn_inode.i_links_count -= 1; - dnode->nn_flags |= IN_CHANGE; - - cache_purge(dvp); - - error = nandfs_truncate(vp, (uint64_t)0); - if (error) - return (error); - - node->nn_inode.i_links_count -= 2; - node->nn_flags |= IN_CHANGE; - - cache_purge(vp); - - return (error); -} - -static int -nandfs_fsync(struct vop_fsync_args *ap) -{ - struct vnode *vp = ap->a_vp; - struct nandfs_node *node = VTON(vp); - int locked; - - DPRINTF(VNCALL, ("%s: vp %p nandnode %p ino %#jx\n", __func__, vp, - node, (uintmax_t)node->nn_ino)); - - /* - * Start syncing vnode only if inode was modified or - * there are some dirty buffers - */ - if (VTON(vp)->nn_flags & IN_MODIFIED || - vp->v_bufobj.bo_dirty.bv_cnt) { - locked = VOP_ISLOCKED(vp); - VOP_UNLOCK(vp, 0); - nandfs_wakeup_wait_sync(node->nn_nandfsdev, SYNCER_FSYNC); - VOP_LOCK(vp, locked | LK_RETRY); - } - - return (0); -} - -static int -nandfs_bmap(struct vop_bmap_args *ap) -{ - struct vnode *vp = ap->a_vp; - struct nandfs_node *nnode = VTON(vp); - struct nandfs_device *nandfsdev = nnode->nn_nandfsdev; - nandfs_daddr_t l2vmap, v2pmap; - int error; - int blk2dev = nandfsdev->nd_blocksize / DEV_BSIZE; - - DPRINTF(VNCALL, ("%s: vp %p nandnode %p ino %#jx\n", __func__, vp, - nnode, (uintmax_t)nnode->nn_ino)); - - if (ap->a_bop != NULL) - *ap->a_bop = &nandfsdev->nd_devvp->v_bufobj; - if (ap->a_bnp == NULL) - return (0); - if (ap->a_runp != NULL) - *ap->a_runp = 0; - if (ap->a_runb != NULL) - *ap->a_runb = 0; - - /* - * Translate all the block sectors into a series of buffers to read - * asynchronously from the nandfs device. Note that this lookup may - * induce readin's too. - */ - - /* Get virtual block numbers for the vnode's buffer span */ - error = nandfs_bmap_lookup(nnode, ap->a_bn, &l2vmap); - if (error) - return (-1); - - /* Translate virtual block numbers to physical block numbers */ - error = nandfs_vtop(nnode, l2vmap, &v2pmap); - if (error) - return (-1); - - /* Note virtual block 0 marks not mapped */ - if (l2vmap == 0) - *ap->a_bnp = -1; - else - *ap->a_bnp = v2pmap * blk2dev; /* in DEV_BSIZE */ - - DPRINTF(VNCALL, ("%s: vp %p nandnode %p ino %#jx lblk %jx -> blk %jx\n", - __func__, vp, nnode, (uintmax_t)nnode->nn_ino, (uintmax_t)ap->a_bn, - (uintmax_t)*ap->a_bnp )); - - return (0); -} - -static void -nandfs_force_syncer(struct nandfsmount *nmp) -{ - - nmp->nm_flags |= NANDFS_FORCE_SYNCER; - nandfs_wakeup_wait_sync(nmp->nm_nandfsdev, SYNCER_FFORCE); -} - -static int -nandfs_ioctl(struct vop_ioctl_args *ap) -{ - struct vnode *vp = ap->a_vp; - u_long command = ap->a_command; - caddr_t data = ap->a_data; - struct nandfs_node *node = VTON(vp); - struct nandfs_device *nandfsdev = node->nn_nandfsdev; - struct nandfsmount *nmp = node->nn_nmp; - uint64_t *tab, *cno; - struct nandfs_seg_stat *nss; - struct nandfs_cpmode *ncpm; - struct nandfs_argv *nargv; - struct nandfs_cpstat *ncp; - int error; - - DPRINTF(VNCALL, ("%s: %x\n", __func__, (uint32_t)command)); - - error = priv_check(ap->a_td, PRIV_VFS_MOUNT); - if (error) - return (error); - - if (nmp->nm_ronly) { - switch (command) { - case NANDFS_IOCTL_GET_FSINFO: - case NANDFS_IOCTL_GET_SUSTAT: - case NANDFS_IOCTL_GET_CPINFO: - case NANDFS_IOCTL_GET_CPSTAT: - case NANDFS_IOCTL_GET_SUINFO: - case NANDFS_IOCTL_GET_VINFO: - case NANDFS_IOCTL_GET_BDESCS: - break; - default: - return (EROFS); - } - } - - switch (command) { - case NANDFS_IOCTL_GET_FSINFO: - error = nandfs_get_fsinfo(nmp, (struct nandfs_fsinfo *)data); - break; - case NANDFS_IOCTL_GET_SUSTAT: - nss = (struct nandfs_seg_stat *)data; - error = nandfs_get_seg_stat(nandfsdev, nss); - break; - case NANDFS_IOCTL_CHANGE_CPMODE: - ncpm = (struct nandfs_cpmode *)data; - error = nandfs_chng_cpmode(nandfsdev->nd_cp_node, ncpm); - nandfs_force_syncer(nmp); - break; - case NANDFS_IOCTL_GET_CPINFO: - nargv = (struct nandfs_argv *)data; - error = nandfs_get_cpinfo_ioctl(nandfsdev->nd_cp_node, nargv); - break; - case NANDFS_IOCTL_DELETE_CP: - tab = (uint64_t *)data; - error = nandfs_delete_cp(nandfsdev->nd_cp_node, tab[0], tab[1]); - nandfs_force_syncer(nmp); - break; - case NANDFS_IOCTL_GET_CPSTAT: - ncp = (struct nandfs_cpstat *)data; - error = nandfs_get_cpstat(nandfsdev->nd_cp_node, ncp); - break; - case NANDFS_IOCTL_GET_SUINFO: - nargv = (struct nandfs_argv *)data; - error = nandfs_get_segment_info_ioctl(nandfsdev, nargv); - break; - case NANDFS_IOCTL_GET_VINFO: - nargv = (struct nandfs_argv *)data; - error = nandfs_get_dat_vinfo_ioctl(nandfsdev, nargv); - break; - case NANDFS_IOCTL_GET_BDESCS: - nargv = (struct nandfs_argv *)data; - error = nandfs_get_dat_bdescs_ioctl(nandfsdev, nargv); - break; - case NANDFS_IOCTL_SYNC: - cno = (uint64_t *)data; - nandfs_force_syncer(nmp); - *cno = nandfsdev->nd_last_cno; - error = 0; - break; - case NANDFS_IOCTL_MAKE_SNAP: - cno = (uint64_t *)data; - error = nandfs_make_snap(nandfsdev, cno); - nandfs_force_syncer(nmp); - break; - case NANDFS_IOCTL_DELETE_SNAP: - cno = (uint64_t *)data; - error = nandfs_delete_snap(nandfsdev, *cno); - nandfs_force_syncer(nmp); - break; - default: - error = ENOTTY; - break; - } - - return (error); -} - -/* - * Whiteout vnode call - */ -static int -nandfs_whiteout(struct vop_whiteout_args *ap) -{ - struct vnode *dvp = ap->a_dvp; - struct componentname *cnp = ap->a_cnp; - int error = 0; - - switch (ap->a_flags) { - case LOOKUP: - return (0); - case CREATE: - /* Create a new directory whiteout */ -#ifdef INVARIANTS - if ((cnp->cn_flags & SAVENAME) == 0) - panic("nandfs_whiteout: missing name"); -#endif - error = nandfs_add_dirent(dvp, NANDFS_WHT_INO, cnp->cn_nameptr, - cnp->cn_namelen, DT_WHT); - break; - - case DELETE: - /* Remove an existing directory whiteout */ - cnp->cn_flags &= ~DOWHITEOUT; - error = nandfs_remove_dirent(dvp, NULL, cnp); - break; - default: - panic("nandf_whiteout: unknown op: %d", ap->a_flags); - } - - return (error); -} - -static int -nandfs_pathconf(struct vop_pathconf_args *ap) -{ - int error; - - error = 0; - switch (ap->a_name) { - case _PC_LINK_MAX: - *ap->a_retval = NANDFS_LINK_MAX; - break; - case _PC_NAME_MAX: - *ap->a_retval = NANDFS_NAME_LEN; - break; - case _PC_PIPE_BUF: - if (ap->a_vp->v_type == VDIR || ap->a_vp->v_type == VFIFO) - *ap->a_retval = PIPE_BUF; - else - error = EINVAL; - break; - case _PC_CHOWN_RESTRICTED: - *ap->a_retval = 1; - break; - case _PC_NO_TRUNC: - *ap->a_retval = 1; - break; - case _PC_ALLOC_SIZE_MIN: - *ap->a_retval = ap->a_vp->v_mount->mnt_stat.f_bsize; - break; - case _PC_FILESIZEBITS: - *ap->a_retval = 64; - break; - case _PC_REC_INCR_XFER_SIZE: - *ap->a_retval = ap->a_vp->v_mount->mnt_stat.f_iosize; - break; - case _PC_REC_MAX_XFER_SIZE: - *ap->a_retval = -1; /* means ``unlimited'' */ - break; - case _PC_REC_MIN_XFER_SIZE: - *ap->a_retval = ap->a_vp->v_mount->mnt_stat.f_iosize; - break; - default: - error = vop_stdpathconf(ap); - break; - } - return (error); -} - -static int -nandfs_vnlock1(struct vop_lock1_args *ap) -{ - struct vnode *vp = ap->a_vp; - struct nandfs_node *node = VTON(vp); - int error, vi_locked; - - /* - * XXX can vnode go away while we are sleeping? - */ - vi_locked = mtx_owned(&vp->v_interlock); - if (vi_locked) - VI_UNLOCK(vp); - error = NANDFS_WRITELOCKFLAGS(node->nn_nandfsdev, - ap->a_flags & LK_NOWAIT); - if (vi_locked && !error) - VI_LOCK(vp); - if (error) - return (error); - - error = vop_stdlock(ap); - if (error) { - NANDFS_WRITEUNLOCK(node->nn_nandfsdev); - return (error); - } - - return (0); -} - -static int -nandfs_vnunlock(struct vop_unlock_args *ap) -{ - struct vnode *vp = ap->a_vp; - struct nandfs_node *node = VTON(vp); - int error; - - error = vop_stdunlock(ap); - if (error) - return (error); - - NANDFS_WRITEUNLOCK(node->nn_nandfsdev); - - return (0); -} - -/* - * Global vfs data structures - */ -struct vop_vector nandfs_vnodeops = { - .vop_default = &default_vnodeops, - .vop_access = nandfs_access, - .vop_advlock = nandfs_advlock, - .vop_bmap = nandfs_bmap, - .vop_close = nandfs_close, - .vop_create = nandfs_create, - .vop_fsync = nandfs_fsync, - .vop_getattr = nandfs_getattr, - .vop_inactive = nandfs_inactive, - .vop_cachedlookup = nandfs_lookup, - .vop_ioctl = nandfs_ioctl, - .vop_link = nandfs_link, - .vop_lookup = vfs_cache_lookup, - .vop_mkdir = nandfs_mkdir, - .vop_mknod = nandfs_mknod, - .vop_open = nandfs_open, - .vop_pathconf = nandfs_pathconf, - .vop_print = nandfs_print, - .vop_read = nandfs_read, - .vop_readdir = nandfs_readdir, - .vop_readlink = nandfs_readlink, - .vop_reclaim = nandfs_reclaim, - .vop_remove = nandfs_remove, - .vop_rename = nandfs_rename, - .vop_rmdir = nandfs_rmdir, - .vop_whiteout = nandfs_whiteout, - .vop_write = nandfs_write, - .vop_setattr = nandfs_setattr, - .vop_strategy = nandfs_strategy, - .vop_symlink = nandfs_symlink, - .vop_lock1 = nandfs_vnlock1, - .vop_unlock = nandfs_vnunlock, -}; - -struct vop_vector nandfs_system_vnodeops = { - .vop_default = &default_vnodeops, - .vop_close = nandfs_close, - .vop_inactive = nandfs_inactive, - .vop_reclaim = nandfs_reclaim, - .vop_strategy = nandfs_strategy, - .vop_fsync = nandfs_fsync, - .vop_bmap = nandfs_bmap, - .vop_access = VOP_PANIC, - .vop_advlock = VOP_PANIC, - .vop_create = VOP_PANIC, - .vop_getattr = VOP_PANIC, - .vop_cachedlookup = VOP_PANIC, - .vop_ioctl = VOP_PANIC, - .vop_link = VOP_PANIC, - .vop_lookup = VOP_PANIC, - .vop_mkdir = VOP_PANIC, - .vop_mknod = VOP_PANIC, - .vop_open = VOP_PANIC, - .vop_pathconf = VOP_PANIC, - .vop_print = VOP_PANIC, - .vop_read = VOP_PANIC, - .vop_readdir = VOP_PANIC, - .vop_readlink = VOP_PANIC, - .vop_remove = VOP_PANIC, - .vop_rename = VOP_PANIC, - .vop_rmdir = VOP_PANIC, - .vop_whiteout = VOP_PANIC, - .vop_write = VOP_PANIC, - .vop_setattr = VOP_PANIC, - .vop_symlink = VOP_PANIC, -}; - -static int -nandfsfifo_close(struct vop_close_args *ap) -{ - struct vnode *vp = ap->a_vp; - struct nandfs_node *node = VTON(vp); - - DPRINTF(VNCALL, ("%s: vp %p node %p\n", __func__, vp, node)); - - mtx_lock(&vp->v_interlock); - if (vp->v_usecount > 1) - nandfs_itimes_locked(vp); - mtx_unlock(&vp->v_interlock); - - return (fifo_specops.vop_close(ap)); -} - -struct vop_vector nandfs_fifoops = { - .vop_default = &fifo_specops, - .vop_fsync = VOP_PANIC, - .vop_access = nandfs_access, - .vop_close = nandfsfifo_close, - .vop_getattr = nandfs_getattr, - .vop_inactive = nandfs_inactive, - .vop_pathconf = nandfs_pathconf, - .vop_print = nandfs_print, - .vop_read = VOP_PANIC, - .vop_reclaim = nandfs_reclaim, - .vop_setattr = nandfs_setattr, - .vop_write = VOP_PANIC, - .vop_lock1 = nandfs_vnlock1, - .vop_unlock = nandfs_vnunlock, -}; - -int -nandfs_vinit(struct vnode *vp, uint64_t ino) -{ - struct nandfs_node *node; - - ASSERT_VOP_LOCKED(vp, __func__); - - node = VTON(vp); - - /* Check if we're fetching the root */ - if (ino == NANDFS_ROOT_INO) - vp->v_vflag |= VV_ROOT; - - if (ino != NANDFS_GC_INO) - vp->v_type = IFTOVT(node->nn_inode.i_mode); - else - vp->v_type = VREG; - - if (vp->v_type == VFIFO) - vp->v_op = &nandfs_fifoops; - - return (0); -} diff --git a/sys/fs/ntfs/ntfs.h b/sys/fs/ntfs/ntfs.h deleted file mode 100644 index 932d30a23eb..00000000000 --- a/sys/fs/ntfs/ntfs.h +++ /dev/null @@ -1,307 +0,0 @@ -/* $NetBSD: ntfs.h,v 1.9 1999/10/31 19:45:26 jdolecek Exp $ */ - -/*- - * Copyright (c) 1998, 1999 Semen Ustimenko - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - */ - -/*#define NTFS_DEBUG 1*/ - -typedef u_int64_t cn_t; -typedef u_int16_t wchar; - -#pragma pack(1) -#define BBSIZE 1024 -#define BBOFF ((off_t)(0)) -#define BBLOCK 0 -#define NTFS_MFTINO 0 -#define NTFS_VOLUMEINO 3 -#define NTFS_ATTRDEFINO 4 -#define NTFS_ROOTINO 5 -#define NTFS_BITMAPINO 6 -#define NTFS_BOOTINO 7 -#define NTFS_BADCLUSINO 8 -#define NTFS_UPCASEINO 10 -#define NTFS_MAXFILENAME 255 - -struct fixuphdr { - u_int32_t fh_magic; - u_int16_t fh_foff; - u_int16_t fh_fnum; -}; - -#define NTFS_AF_INRUN 0x00000001 -struct attrhdr { - u_int32_t a_type; - u_int32_t reclen; - u_int8_t a_flag; - u_int8_t a_namelen; - u_int8_t a_nameoff; - u_int8_t reserved1; - u_int8_t a_compression; - u_int8_t reserved2; - u_int16_t a_index; -}; -#define NTFS_A_STD 0x10 -#define NTFS_A_ATTRLIST 0x20 -#define NTFS_A_NAME 0x30 -#define NTFS_A_VOLUMENAME 0x60 -#define NTFS_A_DATA 0x80 -#define NTFS_A_INDXROOT 0x90 -#define NTFS_A_INDX 0xA0 -#define NTFS_A_INDXBITMAP 0xB0 - -#define NTFS_MAXATTRNAME 255 -struct attr { - struct attrhdr a_hdr; - union { - struct { - u_int16_t a_datalen; - u_int16_t reserved1; - u_int16_t a_dataoff; - u_int16_t a_indexed; - } a_S_r; - struct { - cn_t a_vcnstart; - cn_t a_vcnend; - u_int16_t a_dataoff; - u_int16_t a_compressalg; - u_int32_t reserved1; - u_int64_t a_allocated; - u_int64_t a_datalen; - u_int64_t a_initialized; - } a_S_nr; - } a_S; -}; -#define a_r a_S.a_S_r -#define a_nr a_S.a_S_nr - -typedef struct { - u_int64_t t_create; - u_int64_t t_write; - u_int64_t t_mftwrite; - u_int64_t t_access; -} ntfs_times_t; - -#define NTFS_FFLAG_RDONLY 0x01LL -#define NTFS_FFLAG_HIDDEN 0x02LL -#define NTFS_FFLAG_SYSTEM 0x04LL -#define NTFS_FFLAG_ARCHIVE 0x20LL -#define NTFS_FFLAG_COMPRESSED 0x0800LL -#define NTFS_FFLAG_DIR 0x10000000LL - -struct attr_name { - u_int32_t n_pnumber; /* Parent ntnode */ - u_int32_t reserved; - ntfs_times_t n_times; - u_int64_t n_size; - u_int64_t n_attrsz; - u_int64_t n_flag; - u_int8_t n_namelen; - u_int8_t n_nametype; - u_int16_t n_name[1]; -}; - -#define NTFS_IRFLAG_INDXALLOC 0x00000001 -struct attr_indexroot { - u_int32_t ir_unkn1; /* always 0x30 */ - u_int32_t ir_unkn2; /* always 0x1 */ - u_int32_t ir_size;/* ??? */ - u_int32_t ir_unkn3; /* number of cluster */ - u_int32_t ir_unkn4; /* always 0x10 */ - u_int32_t ir_datalen; /* sizeof simething */ - u_int32_t ir_allocated; /* same as above */ - u_int16_t ir_flag;/* ?? always 1 */ - u_int16_t ir_unkn7; -}; - -struct attr_attrlist { - u_int32_t al_type; /* Attribute type */ - u_int16_t reclen; /* length of this entry */ - u_int8_t al_namelen; /* Attribute name len */ - u_int8_t al_nameoff; /* Name offset from entry start */ - u_int64_t al_vcnstart; /* VCN number */ - u_int32_t al_inumber; /* Parent ntnode */ - u_int32_t reserved; - u_int16_t al_index; /* Attribute index in MFT record */ - u_int16_t al_name[1]; /* Name */ -}; - -#define NTFS_INDXMAGIC (u_int32_t)(0x58444E49) -struct attr_indexalloc { - struct fixuphdr ia_fixup; - u_int64_t unknown1; - cn_t ia_bufcn; - u_int16_t ia_hdrsize; - u_int16_t unknown2; - u_int32_t ia_inuse; - u_int32_t ia_allocated; -}; - -#define NTFS_IEFLAG_SUBNODE 0x00000001 -#define NTFS_IEFLAG_LAST 0x00000002 - -struct attr_indexentry { - u_int32_t ie_number; - u_int32_t unknown1; - u_int16_t reclen; - u_int16_t ie_size; - u_int32_t ie_flag;/* 1 - has subnodes, 2 - last */ - u_int32_t ie_fpnumber; - u_int32_t unknown2; - ntfs_times_t ie_ftimes; - u_int64_t ie_fallocated; - u_int64_t ie_fsize; - u_int64_t ie_fflag; - u_int8_t ie_fnamelen; - u_int8_t ie_fnametype; - wchar ie_fname[NTFS_MAXFILENAME]; - /* cn_t ie_bufcn; buffer with subnodes */ -}; - -#define NTFS_FILEMAGIC (u_int32_t)(0x454C4946) -#define NTFS_BLOCK_SIZE 512 -#define NTFS_FRFLAG_DIR 0x0002 -struct filerec { - struct fixuphdr fr_fixup; - u_int8_t reserved[8]; - u_int16_t fr_seqnum; /* Sequence number */ - u_int16_t fr_nlink; - u_int16_t fr_attroff; /* offset to attributes */ - u_int16_t fr_flags; /* 1-nonresident attr, 2-directory */ - u_int32_t fr_size;/* hdr + attributes */ - u_int32_t fr_allocated; /* allocated length of record */ - u_int64_t fr_mainrec; /* main record */ - u_int16_t fr_attrnum; /* maximum attr number + 1 ??? */ -}; - -#define NTFS_ATTRNAME_MAXLEN 0x40 -#define NTFS_ADFLAG_NONRES 0x0080 /* Attrib can be non resident */ -#define NTFS_ADFLAG_INDEX 0x0002 /* Attrib can be indexed */ -struct attrdef { - wchar ad_name[NTFS_ATTRNAME_MAXLEN]; - u_int32_t ad_type; - u_int32_t reserved1[2]; - u_int32_t ad_flag; - u_int64_t ad_minlen; - u_int64_t ad_maxlen; /* -1 for nonlimited */ -}; - -struct ntvattrdef { - char ad_name[0x40]; - int ad_namelen; - u_int32_t ad_type; -}; - -#define NTFS_BBID "NTFS " -#define NTFS_BBIDLEN 8 -struct bootfile { - u_int8_t reserved1[3]; /* asm jmp near ... */ - u_int8_t bf_sysid[8]; /* 'NTFS ' */ - u_int16_t bf_bps; /* bytes per sector */ - u_int8_t bf_spc; /* sectors per cluster */ - u_int8_t reserved2[7]; /* unused (zeroed) */ - u_int8_t bf_media; /* media desc. (0xF8) */ - u_int8_t reserved3[2]; - u_int16_t bf_spt; /* sectors per track */ - u_int16_t bf_heads; /* number of heads */ - u_int8_t reserver4[12]; - u_int64_t bf_spv; /* sectors per volume */ - cn_t bf_mftcn; /* $MFT cluster number */ - cn_t bf_mftmirrcn; /* $MFTMirr cn */ - u_int8_t bf_mftrecsz; /* MFT record size (clust) */ - /* 0xF6 inducates 1/4 */ - u_int32_t bf_ibsz; /* index buffer size */ - u_int32_t bf_volsn; /* volume ser. num. */ -}; - -#define NTFS_SYSNODESNUM 0x0B -struct ntfsmount { - struct mount *ntm_mountp; /* filesystem vfs structure */ - struct bootfile ntm_bootfile; - struct g_consumer *ntm_cp; - struct bufobj *ntm_bo; - struct vnode *ntm_devvp; /* block device mounted vnode */ - struct vnode *ntm_sysvn[NTFS_SYSNODESNUM]; - u_int32_t ntm_bpmftrec; - uid_t ntm_uid; - gid_t ntm_gid; - mode_t ntm_mode; - uint64_t ntm_flag; - cn_t ntm_cfree; - struct ntvattrdef *ntm_ad; - int ntm_adnum; - wchar * ntm_82u; /* 8bit to Unicode */ - char ** ntm_u28; /* Unicode to 8 bit */ - void * ntm_ic_l2u; /* Local to Unicode (iconv) */ - void * ntm_ic_u2l; /* Unicode to Local (iconv) */ - u_int8_t ntm_multiplier; /* NTFS blockno to DEV_BSIZE sectorno */ -}; - -#define ntm_mftcn ntm_bootfile.bf_mftcn -#define ntm_mftmirrcn ntm_bootfile.bf_mftmirrcn -#define ntm_mftrecsz ntm_bootfile.bf_mftrecsz -#define ntm_spc ntm_bootfile.bf_spc -#define ntm_bps ntm_bootfile.bf_bps - -#pragma pack() - -#define NTFS_NEXTREC(s, type) ((type)(((caddr_t) s) + (s)->reclen)) - -/* Convert mount ptr to ntfsmount ptr. */ -#define VFSTONTFS(mp) ((struct ntfsmount *)((mp)->mnt_data)) -#define VTONT(v) FTONT(VTOF(v)) -#define VTOF(v) ((struct fnode *)((v)->v_data)) -#define FTOV(f) ((f)->f_vp) -#define FTONT(f) ((f)->f_ip) -#define ntfs_cntobn(cn) (daddr_t)((cn) * (ntmp->ntm_spc)) -#define ntfs_cntob(cn) (off_t)((cn) * (ntmp)->ntm_spc * (ntmp)->ntm_bps) -#define ntfs_btocn(off) (cn_t)((off) / ((ntmp)->ntm_spc * (ntmp)->ntm_bps)) -#define ntfs_btocl(off) (cn_t)((off + ntfs_cntob(1) - 1) / ((ntmp)->ntm_spc * (ntmp)->ntm_bps)) -#define ntfs_btocnoff(off) (off_t)((off) % ((ntmp)->ntm_spc * (ntmp)->ntm_bps)) -#define ntfs_bntob(bn) (daddr_t)((bn) * (ntmp)->ntm_bps) - -#define ntfs_bpbl (daddr_t)((ntmp)->ntm_bps) - -#ifdef MALLOC_DECLARE -MALLOC_DECLARE(M_NTFSNTNODE); -MALLOC_DECLARE(M_NTFSFNODE); -MALLOC_DECLARE(M_NTFSDIR); -MALLOC_DECLARE(M_NTFSNTHASH); -#endif - -#if defined(NTFS_DEBUG) -#define dprintf(a) printf a -#if NTFS_DEBUG > 1 -#define ddprintf(a) printf a -#else -#define ddprintf(a) (void)0 -#endif -#else -#define dprintf(a) (void)0 -#define ddprintf(a) (void)0 -#endif - -extern struct vop_vector ntfs_vnodeops; diff --git a/sys/fs/ntfs/ntfs_compr.c b/sys/fs/ntfs/ntfs_compr.c deleted file mode 100644 index 662818c9107..00000000000 --- a/sys/fs/ntfs/ntfs_compr.c +++ /dev/null @@ -1,110 +0,0 @@ -/* $NetBSD: ntfs_compr.c,v 1.3 1999/07/26 14:02:31 jdolecek Exp $ */ - -/*- - * Copyright (c) 1998, 1999 Semen Ustimenko - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - */ - -#include -#include -#include -#include -#include -#include - -#include -#include - -#define GET_UINT16(addr) (*((u_int16_t *)(addr))) - -int -ntfs_uncompblock( - u_int8_t * buf, - u_int8_t * cbuf) -{ - u_int32_t ctag; - int len, dshift, lmask; - int blen, boff; - int i, j; - int pos, cpos; - - len = GET_UINT16(cbuf) & 0xFFF; - dprintf(("ntfs_uncompblock: block length: %d + 3, 0x%x,0x%04x\n", - len, len, GET_UINT16(cbuf))); - - if (!(GET_UINT16(cbuf) & 0x8000)) { - if ((len + 1) != NTFS_COMPBLOCK_SIZE) { - dprintf(("ntfs_uncompblock: len: %x instead of %d\n", - len, 0xfff)); - } - memcpy(buf, cbuf + 2, len + 1); - bzero(buf + len + 1, NTFS_COMPBLOCK_SIZE - 1 - len); - return len + 3; - } - cpos = 2; - pos = 0; - while ((cpos < len + 3) && (pos < NTFS_COMPBLOCK_SIZE)) { - ctag = cbuf[cpos++]; - for (i = 0; (i < 8) && (pos < NTFS_COMPBLOCK_SIZE); i++) { - if (ctag & 1) { - for (j = pos - 1, lmask = 0xFFF, dshift = 12; - j >= 0x10; j >>= 1) { - dshift--; - lmask >>= 1; - } - boff = -1 - (GET_UINT16(cbuf + cpos) >> dshift); - blen = 3 + (GET_UINT16(cbuf + cpos) & lmask); - for (j = 0; (j < blen) && (pos < NTFS_COMPBLOCK_SIZE); j++) { - buf[pos] = buf[pos + boff]; - pos++; - } - cpos += 2; - } else { - buf[pos++] = cbuf[cpos++]; - } - ctag >>= 1; - } - } - return len + 3; -} - -int -ntfs_uncompunit( - struct ntfsmount * ntmp, - u_int8_t * uup, - u_int8_t * cup) -{ - int i; - int off = 0; - int new; - - for (i = 0; i * NTFS_COMPBLOCK_SIZE < ntfs_cntob(NTFS_COMPUNIT_CL); i++) { - new = ntfs_uncompblock(uup + i * NTFS_COMPBLOCK_SIZE, cup + off); - if (new == 0) - return (EINVAL); - off += new; - } - return (0); -} diff --git a/sys/fs/ntfs/ntfs_compr.h b/sys/fs/ntfs/ntfs_compr.h deleted file mode 100644 index 2740285b82a..00000000000 --- a/sys/fs/ntfs/ntfs_compr.h +++ /dev/null @@ -1,34 +0,0 @@ -/* $NetBSD: ntfs_compr.h,v 1.3 1999/07/26 14:02:31 jdolecek Exp $ */ - -/*- - * Copyright (c) 1998, 1999 Semen Ustimenko - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - */ - -#define NTFS_COMPBLOCK_SIZE 0x1000 -#define NTFS_COMPUNIT_CL 16 - -int ntfs_uncompblock(u_int8_t *, u_int8_t *); -int ntfs_uncompunit(struct ntfsmount *, u_int8_t *, u_int8_t *); diff --git a/sys/fs/ntfs/ntfs_iconv.c b/sys/fs/ntfs/ntfs_iconv.c deleted file mode 100644 index 73c9bc72840..00000000000 --- a/sys/fs/ntfs/ntfs_iconv.c +++ /dev/null @@ -1,35 +0,0 @@ -/*- - * Copyright (c) 2003 Ryuichiro Imura - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include - -#include -#include -#include -#include -#include - -VFS_DECLARE_ICONV(ntfs); diff --git a/sys/fs/ntfs/ntfs_ihash.c b/sys/fs/ntfs/ntfs_ihash.c deleted file mode 100644 index 27c8384eb79..00000000000 --- a/sys/fs/ntfs/ntfs_ihash.c +++ /dev/null @@ -1,129 +0,0 @@ -/* $NetBSD: ntfs_ihash.c,v 1.5 1999/09/30 16:56:40 jdolecek Exp $ */ - -/*- - * Copyright (c) 1982, 1986, 1989, 1991, 1993, 1995 - * The Regents of the University of California. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 4. Neither the name of the University nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @(#)ufs_ihash.c 8.7 (Berkeley) 5/17/95 - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -MALLOC_DEFINE(M_NTFSNTHASH, "ntfs_nthash", "NTFS ntnode hash tables"); - -/* - * Structures associated with inode cacheing. - */ -static LIST_HEAD(nthashhead, ntnode) *ntfs_nthashtbl; -static u_long ntfs_nthash; /* size of hash table - 1 */ -#define NTNOHASH(inum) (&ntfs_nthashtbl[(inum) & ntfs_nthash]) -static struct mtx ntfs_nthash_mtx; -struct lock ntfs_hashlock; - -/* - * Initialize inode hash table. - */ -void -ntfs_nthashinit() -{ - lockinit(&ntfs_hashlock, PINOD, "ntfs_nthashlock", 0, 0); - ntfs_nthashtbl = hashinit(desiredvnodes, M_NTFSNTHASH, &ntfs_nthash); - mtx_init(&ntfs_nthash_mtx, "ntfs nthash", NULL, MTX_DEF); -} - -/* - * Destroy inode hash table. - */ -void -ntfs_nthashdestroy(void) -{ - hashdestroy(ntfs_nthashtbl, M_NTFSNTHASH, ntfs_nthash); - lockdestroy(&ntfs_hashlock); - mtx_destroy(&ntfs_nthash_mtx); -} - -/* - * Use the device/inum pair to find the incore inode, and return a pointer - * to it. If it is in core, return it, even if it is locked. - */ -struct ntnode * -ntfs_nthashlookup(dev, inum) - struct cdev *dev; - ino_t inum; -{ - struct ntnode *ip; - - mtx_lock(&ntfs_nthash_mtx); - LIST_FOREACH(ip, NTNOHASH(inum), i_hash) - if (inum == ip->i_number && dev == ip->i_dev) - break; - mtx_unlock(&ntfs_nthash_mtx); - - return (ip); -} - -/* - * Insert the ntnode into the hash table. - */ -void -ntfs_nthashins(ip) - struct ntnode *ip; -{ - struct nthashhead *ipp; - - mtx_lock(&ntfs_nthash_mtx); - ipp = NTNOHASH(ip->i_number); - LIST_INSERT_HEAD(ipp, ip, i_hash); - ip->i_flag |= IN_HASHED; - mtx_unlock(&ntfs_nthash_mtx); -} - -/* - * Remove the inode from the hash table. - */ -void -ntfs_nthashrem(ip) - struct ntnode *ip; -{ - mtx_lock(&ntfs_nthash_mtx); - if (ip->i_flag & IN_HASHED) { - ip->i_flag &= ~IN_HASHED; - LIST_REMOVE(ip, i_hash); - } - mtx_unlock(&ntfs_nthash_mtx); -} diff --git a/sys/fs/ntfs/ntfs_ihash.h b/sys/fs/ntfs/ntfs_ihash.h deleted file mode 100644 index be6fb59f779..00000000000 --- a/sys/fs/ntfs/ntfs_ihash.h +++ /dev/null @@ -1,36 +0,0 @@ -/* $NetBSD: ntfs_ihash.h,v 1.4 1999/09/30 16:56:40 jdolecek Exp $ */ - -/*- - * Copyright (c) 1998, 1999 Semen Ustimenko - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - */ - -extern struct lock ntfs_hashlock; -void ntfs_nthashinit(void); -void ntfs_nthashdestroy(void); -struct ntnode *ntfs_nthashlookup(struct cdev *, ino_t); -struct ntnode *ntfs_nthashget(struct cdev *, ino_t); -void ntfs_nthashins(struct ntnode *); -void ntfs_nthashrem(register struct ntnode *); diff --git a/sys/fs/ntfs/ntfs_inode.h b/sys/fs/ntfs/ntfs_inode.h deleted file mode 100644 index 8e20bc6b3d0..00000000000 --- a/sys/fs/ntfs/ntfs_inode.h +++ /dev/null @@ -1,100 +0,0 @@ -/* $NetBSD: ntfs_inode.h,v 1.8 1999/10/31 19:45:26 jdolecek Exp $ */ - -/*- - * Copyright (c) 1998, 1999 Semen Ustimenko - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - */ - -/* These flags are kept in i_flag. */ -#define IN_ACCESS 0x0001 /* Access time update request. */ -#define IN_CHANGE 0x0002 /* Inode change time update request. */ -#define IN_UPDATE 0x0004 /* Modification time update request. */ -#define IN_MODIFIED 0x0008 /* Inode has been modified. */ -#define IN_RENAME 0x0010 /* Inode is being renamed. */ -#define IN_SHLOCK 0x0020 /* File has shared lock. */ -#define IN_EXLOCK 0x0040 /* File has exclusive lock. */ -#define IN_LAZYMOD 0x0080 /* Modified, but don't write yet. */ -#define IN_HASHED 0x0800 /* Inode is on hash list */ -#define IN_LOADED 0x8000 /* ntvattrs loaded */ -#define IN_PRELOADED 0x4000 /* loaded from directory entry */ - -struct ntnode { - struct vnode *i_devvp; /* vnode of blk dev we live on */ - struct cdev *i_dev; /* Device associated with the inode. */ - - LIST_ENTRY(ntnode) i_hash; - struct ntnode *i_next; - struct ntnode **i_prev; - struct ntfsmount *i_mp; - ino_t i_number; - u_int32_t i_flag; - - /* locking */ - struct lock i_lock; - struct mtx i_interlock; - int i_usecount; - - LIST_HEAD(,fnode) i_fnlist; - LIST_HEAD(,ntvattr) i_valist; - - long i_nlink; /* MFR */ - ino_t i_mainrec; /* MFR */ - u_int32_t i_frflag; /* MFR */ -}; - -#define FN_PRELOADED 0x0001 -#define FN_VALID 0x0002 -#define FN_AATTRNAME 0x0004 /* space allocated for f_attrname */ -struct fnode { - LIST_ENTRY(fnode) f_fnlist; - struct vnode *f_vp; /* Associatied vnode */ - struct ntnode *f_ip; /* Associated ntnode */ - u_long f_flag; - - ntfs_times_t f_times; /* $NAME/dirinfo */ - ino_t f_pnumber; /* $NAME/dirinfo */ - u_int32_t f_fflag; /* $NAME/dirinfo */ - u_int64_t f_size; /* defattr/dirinfo: */ - u_int64_t f_allocated; /* defattr/dirinfo */ - - u_int32_t f_attrtype; - char *f_attrname; - - /* for ntreaddir */ - u_int32_t f_lastdattr; - u_int32_t f_lastdblnum; - u_int32_t f_lastdoff; - u_int32_t f_lastdnum; - caddr_t f_dirblbuf; - u_int32_t f_dirblsz; -}; - -/* This overlays the fid structure (see ) */ -struct ntfid { - u_int16_t ntfid_len; /* Length of structure. */ - u_int16_t ntfid_pad; /* Force 32-bit alignment. */ - ino_t ntfid_ino; /* File number (ino). */ - int32_t ntfid_gen; /* Generation number. */ -}; diff --git a/sys/fs/ntfs/ntfs_subr.c b/sys/fs/ntfs/ntfs_subr.c deleted file mode 100644 index be842e3195e..00000000000 --- a/sys/fs/ntfs/ntfs_subr.c +++ /dev/null @@ -1,2192 +0,0 @@ -/* $NetBSD: ntfs_subr.c,v 1.23 1999/10/31 19:45:26 jdolecek Exp $ */ - -/*- - * Copyright (c) 1998, 1999 Semen Ustimenko (semenu@FreeBSD.org) - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* #define NTFS_DEBUG 1 */ -#include -#include -#include -#include -#include -#include -#include - -static MALLOC_DEFINE(M_NTFSNTVATTR, "ntfs_vattr", - "NTFS file attribute information"); -static MALLOC_DEFINE(M_NTFSRDATA, "ntfsd_resdata", "NTFS resident data"); -static MALLOC_DEFINE(M_NTFSRUN, "ntfs_vrun", "NTFS vrun storage"); -static MALLOC_DEFINE(M_NTFSDECOMP, "ntfs_decomp", - "NTFS decompression temporary"); - -static int ntfs_ntlookupattr(struct ntfsmount *, const char *, int, int *, char **); -static int ntfs_findvattr(struct ntfsmount *, struct ntnode *, struct ntvattr **, struct ntvattr **, u_int32_t, const char *, size_t, cn_t); -static int ntfs_uastricmp(struct ntfsmount *, const wchar *, size_t, const char *, size_t); -static int ntfs_uastrcmp(struct ntfsmount *, const wchar *, size_t, const char *, size_t); - -/* table for mapping Unicode chars into uppercase; it's filled upon first - * ntfs mount, freed upon last ntfs umount */ -static wchar *ntfs_toupper_tab; -#define NTFS_TOUPPER(ch) (ntfs_toupper_tab[(ch)]) -static struct lock ntfs_toupper_lock; -static signed int ntfs_toupper_usecount; - -struct iconv_functions *ntfs_iconv = NULL; - -/* support macro for ntfs_ntvattrget() */ -#define NTFS_AALPCMP(aalp,type,name,namelen) ( \ - (aalp->al_type == type) && (aalp->al_namelen == namelen) && \ - !NTFS_UASTRCMP(aalp->al_name,aalp->al_namelen,name,namelen) ) - -/* - * - */ -int -ntfs_ntvattrrele(vap) - struct ntvattr * vap; -{ - dprintf(("ntfs_ntvattrrele: ino: %d, type: 0x%x\n", - vap->va_ip->i_number, vap->va_type)); - - ntfs_ntrele(vap->va_ip); - - return (0); -} - -/* - * find the attribute in the ntnode - */ -static int -ntfs_findvattr(ntmp, ip, lvapp, vapp, type, name, namelen, vcn) - struct ntfsmount *ntmp; - struct ntnode *ip; - struct ntvattr **lvapp, **vapp; - u_int32_t type; - const char *name; - size_t namelen; - cn_t vcn; -{ - int error; - struct ntvattr *vap; - - if((ip->i_flag & IN_LOADED) == 0) { - dprintf(("ntfs_findvattr: node not loaded, ino: %d\n", - ip->i_number)); - error = ntfs_loadntnode(ntmp,ip); - if (error) { - printf("ntfs_findvattr: FAILED TO LOAD INO: %d\n", - ip->i_number); - return (error); - } - } - - *lvapp = NULL; - *vapp = NULL; - LIST_FOREACH(vap, &ip->i_valist, va_list) { - ddprintf(("ntfs_findvattr: type: 0x%x, vcn: %d - %d\n", \ - vap->va_type, (u_int32_t) vap->va_vcnstart, \ - (u_int32_t) vap->va_vcnend)); - if ((vap->va_type == type) && - (vap->va_vcnstart <= vcn) && (vap->va_vcnend >= vcn) && - (vap->va_namelen == namelen) && - (strncmp(name, vap->va_name, namelen) == 0)) { - *vapp = vap; - ntfs_ntref(vap->va_ip); - return (0); - } - if (vap->va_type == NTFS_A_ATTRLIST) - *lvapp = vap; - } - - return (-1); -} - -/* - * Search attribute specifed in ntnode (load ntnode if nessecary). - * If not found but ATTR_A_ATTRLIST present, read it in and search throught. - * VOP_VGET node needed, and lookup througth it's ntnode (load if nessesary). - * - * ntnode should be locked - */ -int -ntfs_ntvattrget( - struct ntfsmount * ntmp, - struct ntnode * ip, - u_int32_t type, - const char *name, - cn_t vcn, - struct ntvattr ** vapp) -{ - struct ntvattr *lvap = NULL; - struct attr_attrlist *aalp; - struct attr_attrlist *nextaalp; - struct vnode *newvp; - struct ntnode *newip; - caddr_t alpool; - size_t namelen, len; - int error; - - *vapp = NULL; - - if (name) { - dprintf(("ntfs_ntvattrget: " \ - "ino: %d, type: 0x%x, name: %s, vcn: %d\n", \ - ip->i_number, type, name, (u_int32_t) vcn)); - namelen = strlen(name); - } else { - dprintf(("ntfs_ntvattrget: " \ - "ino: %d, type: 0x%x, vcn: %d\n", \ - ip->i_number, type, (u_int32_t) vcn)); - name = ""; - namelen = 0; - } - - error = ntfs_findvattr(ntmp, ip, &lvap, vapp, type, name, namelen, vcn); - if (error >= 0) - return (error); - - if (!lvap) { - dprintf(("ntfs_ntvattrget: UNEXISTED ATTRIBUTE: " \ - "ino: %d, type: 0x%x, name: %s, vcn: %d\n", \ - ip->i_number, type, name, (u_int32_t) vcn)); - return (ENOENT); - } - /* Scan $ATTRIBUTE_LIST for requested attribute */ - len = lvap->va_datalen; - alpool = malloc(len, M_TEMP, M_WAITOK); - error = ntfs_readntvattr_plain(ntmp, ip, lvap, 0, len, alpool, &len, - NULL); - if (error) - goto out; - - aalp = (struct attr_attrlist *) alpool; - nextaalp = NULL; - - for(; len > 0; aalp = nextaalp) { - dprintf(("ntfs_ntvattrget: " \ - "attrlist: ino: %d, attr: 0x%x, vcn: %d\n", \ - aalp->al_inumber, aalp->al_type, \ - (u_int32_t) aalp->al_vcnstart)); - - if (len > aalp->reclen) { - nextaalp = NTFS_NEXTREC(aalp, struct attr_attrlist *); - } else { - nextaalp = NULL; - } - len -= aalp->reclen; - - if (!NTFS_AALPCMP(aalp, type, name, namelen) || - (nextaalp && (nextaalp->al_vcnstart <= vcn) && - NTFS_AALPCMP(nextaalp, type, name, namelen))) - continue; - - dprintf(("ntfs_ntvattrget: attribute in ino: %d\n", - aalp->al_inumber)); - - /* this is not a main record, so we can't use just plain - vget() */ - error = ntfs_vgetex(ntmp->ntm_mountp, aalp->al_inumber, - NTFS_A_DATA, NULL, LK_EXCLUSIVE, - VG_EXT, curthread, &newvp); - if (error) { - printf("ntfs_ntvattrget: CAN'T VGET INO: %d\n", - aalp->al_inumber); - goto out; - } - newip = VTONT(newvp); - /* XXX have to lock ntnode */ - error = ntfs_findvattr(ntmp, newip, &lvap, vapp, - type, name, namelen, vcn); - vput(newvp); - if (error == 0) - goto out; - printf("ntfs_ntvattrget: ATTRLIST ERROR.\n"); - break; - } - error = ENOENT; - - dprintf(("ntfs_ntvattrget: UNEXISTED ATTRIBUTE: " \ - "ino: %d, type: 0x%x, name: %.*s, vcn: %d\n", \ - ip->i_number, type, (int) namelen, name, (u_int32_t) vcn)); -out: - free(alpool, M_TEMP); - return (error); -} - -/* - * Read ntnode from disk, make ntvattr list. - * - * ntnode should be locked - */ -int -ntfs_loadntnode( - struct ntfsmount * ntmp, - struct ntnode * ip) -{ - struct filerec *mfrp; - daddr_t bn; - int error,off; - struct attr *ap; - struct ntvattr *nvap; - - dprintf(("ntfs_loadntnode: loading ino: %d\n",ip->i_number)); - - mfrp = malloc(ntfs_bntob(ntmp->ntm_bpmftrec), - M_TEMP, M_WAITOK); - - if (ip->i_number < NTFS_SYSNODESNUM) { - struct buf *bp; - - dprintf(("ntfs_loadntnode: read system node\n")); - - bn = ntfs_cntobn(ntmp->ntm_mftcn) + - ntmp->ntm_bpmftrec * ip->i_number; - bn *= ntmp->ntm_multiplier; - - error = bread(ntmp->ntm_devvp, - bn, ntfs_bntob(ntmp->ntm_bpmftrec), - NOCRED, &bp); - if (error) { - printf("ntfs_loadntnode: BREAD FAILED\n"); - brelse(bp); - goto out; - } - memcpy(mfrp, bp->b_data, ntfs_bntob(ntmp->ntm_bpmftrec)); - bqrelse(bp); - } else { - struct vnode *vp; - - vp = ntmp->ntm_sysvn[NTFS_MFTINO]; - error = ntfs_readattr(ntmp, VTONT(vp), NTFS_A_DATA, NULL, - ip->i_number * ntfs_bntob(ntmp->ntm_bpmftrec), - ntfs_bntob(ntmp->ntm_bpmftrec), mfrp, NULL); - if (error) { - printf("ntfs_loadntnode: ntfs_readattr failed\n"); - goto out; - } - } - - /* Check if magic and fixups are correct */ - error = ntfs_procfixups(ntmp, NTFS_FILEMAGIC, (caddr_t)mfrp, - ntfs_bntob(ntmp->ntm_bpmftrec)); - if (error) { - printf("ntfs_loadntnode: BAD MFT RECORD %d\n", - (u_int32_t) ip->i_number); - goto out; - } - - dprintf(("ntfs_loadntnode: load attrs for ino: %d\n",ip->i_number)); - off = mfrp->fr_attroff; - ap = (struct attr *) ((caddr_t)mfrp + off); - - LIST_INIT(&ip->i_valist); - - while (ap->a_hdr.a_type != -1) { - error = ntfs_attrtontvattr(ntmp, &nvap, ap); - if (error) - break; - nvap->va_ip = ip; - - LIST_INSERT_HEAD(&ip->i_valist, nvap, va_list); - - off += ap->a_hdr.reclen; - ap = (struct attr *) ((caddr_t)mfrp + off); - } - if (error) { - printf("ntfs_loadntnode: failed to load attr ino: %d\n", - ip->i_number); - goto out; - } - - ip->i_mainrec = mfrp->fr_mainrec; - ip->i_nlink = mfrp->fr_nlink; - ip->i_frflag = mfrp->fr_flags; - - ip->i_flag |= IN_LOADED; - -out: - free(mfrp, M_TEMP); - return (error); -} - -/* - * Routine locks ntnode and increase usecount, just opposite of - * ntfs_ntput(). - */ -int -ntfs_ntget(ip) - struct ntnode *ip; -{ - dprintf(("ntfs_ntget: get ntnode %d: %p, usecount: %d\n", - ip->i_number, ip, ip->i_usecount)); - - mtx_lock(&ip->i_interlock); - ip->i_usecount++; - lockmgr(&ip->i_lock, LK_EXCLUSIVE | LK_INTERLOCK, &ip->i_interlock); - - return 0; -} - -/* - * Routine search ntnode in hash, if found: lock, inc usecount and return. - * If not in hash allocate structure for ntnode, prefill it, lock, - * inc count and return. - * - * ntnode returned locked - */ -int -ntfs_ntlookup( - struct ntfsmount * ntmp, - ino_t ino, - struct ntnode ** ipp) -{ - struct ntnode *ip; - - dprintf(("ntfs_ntlookup: looking for ntnode %d\n", ino)); - - do { - ip = ntfs_nthashlookup(ntmp->ntm_devvp->v_rdev, ino); - if (ip != NULL) { - ntfs_ntget(ip); - dprintf(("ntfs_ntlookup: ntnode %d: %p, usecount: %d\n", - ino, ip, ip->i_usecount)); - *ipp = ip; - return (0); - } - } while (lockmgr(&ntfs_hashlock, LK_EXCLUSIVE | LK_SLEEPFAIL, NULL)); - - ip = malloc(sizeof(struct ntnode), M_NTFSNTNODE, - M_WAITOK | M_ZERO); - ddprintf(("ntfs_ntlookup: allocating ntnode: %d: %p\n", ino, ip)); - - /* Generic initialization */ - ip->i_devvp = ntmp->ntm_devvp; - ip->i_dev = ntmp->ntm_devvp->v_rdev; - ip->i_number = ino; - ip->i_mp = ntmp; - - LIST_INIT(&ip->i_fnlist); - VREF(ip->i_devvp); - - /* init lock and lock the newborn ntnode */ - lockinit(&ip->i_lock, PINOD, "ntnode", 0, 0); - mtx_init(&ip->i_interlock, "ntnode interlock", NULL, MTX_DEF); - ntfs_ntget(ip); - - ntfs_nthashins(ip); - - lockmgr(&ntfs_hashlock, LK_RELEASE, NULL); - - *ipp = ip; - - dprintf(("ntfs_ntlookup: ntnode %d: %p, usecount: %d\n", - ino, ip, ip->i_usecount)); - - return (0); -} - -/* - * Decrement usecount of ntnode and unlock it, if usecount reach zero, - * deallocate ntnode. - * - * ntnode should be locked on entry, and unlocked on return. - */ -void -ntfs_ntput(ip) - struct ntnode *ip; -{ - struct ntvattr *vap; - - dprintf(("ntfs_ntput: rele ntnode %d: %p, usecount: %d\n", - ip->i_number, ip, ip->i_usecount)); - - mtx_lock(&ip->i_interlock); - ip->i_usecount--; - -#ifdef DIAGNOSTIC - if (ip->i_usecount < 0) { - panic("ntfs_ntput: ino: %d usecount: %d \n", - ip->i_number,ip->i_usecount); - } -#endif - - if (ip->i_usecount > 0) { - lockmgr(&ip->i_lock, LK_RELEASE|LK_INTERLOCK, &ip->i_interlock); - return; - } - - dprintf(("ntfs_ntput: deallocating ntnode: %d\n", ip->i_number)); - - if (LIST_FIRST(&ip->i_fnlist)) - panic("ntfs_ntput: ntnode has fnodes\n"); - - ntfs_nthashrem(ip); - - while ((vap = LIST_FIRST(&ip->i_valist)) != NULL) { - LIST_REMOVE(vap,va_list); - ntfs_freentvattr(vap); - } - lockmgr(&ip->i_lock, LK_RELEASE | LK_INTERLOCK, &ip->i_interlock); - mtx_destroy(&ip->i_interlock); - lockdestroy(&ip->i_lock); - vrele(ip->i_devvp); - free(ip, M_NTFSNTNODE); -} - -/* - * increment usecount of ntnode - */ -void -ntfs_ntref(ip) - struct ntnode *ip; -{ - mtx_lock(&ip->i_interlock); - ip->i_usecount++; - mtx_unlock(&ip->i_interlock); - - dprintf(("ntfs_ntref: ino %d, usecount: %d\n", - ip->i_number, ip->i_usecount)); - -} - -/* - * Decrement usecount of ntnode. - */ -void -ntfs_ntrele(ip) - struct ntnode *ip; -{ - dprintf(("ntfs_ntrele: rele ntnode %d: %p, usecount: %d\n", - ip->i_number, ip, ip->i_usecount)); - - mtx_lock(&ip->i_interlock); - ip->i_usecount--; - - if (ip->i_usecount < 0) - panic("ntfs_ntrele: ino: %d usecount: %d \n", - ip->i_number,ip->i_usecount); - mtx_unlock(&ip->i_interlock); -} - -/* - * Deallocate all memory allocated for ntvattr - */ -void -ntfs_freentvattr(vap) - struct ntvattr * vap; -{ - if (vap->va_flag & NTFS_AF_INRUN) { - if (vap->va_vruncn) - free(vap->va_vruncn, M_NTFSRUN); - if (vap->va_vruncl) - free(vap->va_vruncl, M_NTFSRUN); - } else { - if (vap->va_datap) - free(vap->va_datap, M_NTFSRDATA); - } - free(vap, M_NTFSNTVATTR); -} - -/* - * Convert disk image of attribute into ntvattr structure, - * runs are expanded also. - */ -int -ntfs_attrtontvattr( - struct ntfsmount * ntmp, - struct ntvattr ** rvapp, - struct attr * rap) -{ - int error, i; - struct ntvattr *vap; - - error = 0; - *rvapp = NULL; - - vap = malloc(sizeof(struct ntvattr), - M_NTFSNTVATTR, M_WAITOK | M_ZERO); - vap->va_ip = NULL; - vap->va_flag = rap->a_hdr.a_flag; - vap->va_type = rap->a_hdr.a_type; - vap->va_compression = rap->a_hdr.a_compression; - vap->va_index = rap->a_hdr.a_index; - - ddprintf(("type: 0x%x, index: %d", vap->va_type, vap->va_index)); - - vap->va_namelen = rap->a_hdr.a_namelen; - if (rap->a_hdr.a_namelen) { - wchar *unp = (wchar *) ((caddr_t) rap + rap->a_hdr.a_nameoff); - ddprintf((", name:[")); - for (i = 0; i < vap->va_namelen; i++) { - vap->va_name[i] = unp[i]; - ddprintf(("%c", vap->va_name[i])); - } - ddprintf(("]")); - } - if (vap->va_flag & NTFS_AF_INRUN) { - ddprintf((", nonres.")); - vap->va_datalen = rap->a_nr.a_datalen; - vap->va_allocated = rap->a_nr.a_allocated; - vap->va_vcnstart = rap->a_nr.a_vcnstart; - vap->va_vcnend = rap->a_nr.a_vcnend; - vap->va_compressalg = rap->a_nr.a_compressalg; - error = ntfs_runtovrun(&(vap->va_vruncn), &(vap->va_vruncl), - &(vap->va_vruncnt), - (caddr_t) rap + rap->a_nr.a_dataoff); - } else { - vap->va_compressalg = 0; - ddprintf((", res.")); - vap->va_datalen = rap->a_r.a_datalen; - vap->va_allocated = rap->a_r.a_datalen; - vap->va_vcnstart = 0; - vap->va_vcnend = ntfs_btocn(vap->va_allocated); - vap->va_datap = malloc(vap->va_datalen, - M_NTFSRDATA, M_WAITOK); - memcpy(vap->va_datap, (caddr_t) rap + rap->a_r.a_dataoff, - rap->a_r.a_datalen); - } - ddprintf((", len: %lld", vap->va_datalen)); - - if (error) - free(vap, M_NTFSNTVATTR); - else - *rvapp = vap; - - ddprintf(("\n")); - - return (error); -} - -/* - * Expand run into more utilizable and more memory eating format. - */ -int -ntfs_runtovrun( - cn_t ** rcnp, - cn_t ** rclp, - u_long * rcntp, - u_int8_t * run) -{ - u_int32_t off; - u_int32_t sz, i; - cn_t *cn; - cn_t *cl; - u_long cnt; - cn_t prev; - cn_t tmp; - - off = 0; - cnt = 0; - i = 0; - while (run[off]) { - off += (run[off] & 0xF) + ((run[off] >> 4) & 0xF) + 1; - cnt++; - } - cn = malloc(cnt * sizeof(cn_t), M_NTFSRUN, M_WAITOK); - cl = malloc(cnt * sizeof(cn_t), M_NTFSRUN, M_WAITOK); - - off = 0; - cnt = 0; - prev = 0; - while (run[off]) { - - sz = run[off++]; - cl[cnt] = 0; - - for (i = 0; i < (sz & 0xF); i++) - cl[cnt] += (u_int32_t) run[off++] << (i << 3); - - sz >>= 4; - if (run[off + sz - 1] & 0x80) { - tmp = ((u_int64_t) - 1) << (sz << 3); - for (i = 0; i < sz; i++) - tmp |= (u_int64_t) run[off++] << (i << 3); - } else { - tmp = 0; - for (i = 0; i < sz; i++) - tmp |= (u_int64_t) run[off++] << (i << 3); - } - if (tmp) - prev = cn[cnt] = prev + tmp; - else - cn[cnt] = tmp; - - cnt++; - } - *rcnp = cn; - *rclp = cl; - *rcntp = cnt; - return (0); -} - -/* - * Compare unicode and ascii string case insens. - */ -static int -ntfs_uastricmp(ntmp, ustr, ustrlen, astr, astrlen) - struct ntfsmount *ntmp; - const wchar *ustr; - size_t ustrlen; - const char *astr; - size_t astrlen; -{ - const char *astrp = astr; - char tmpbuf[5]; - int len, res; - size_t i, j, mbstrlen = astrlen; - - if (ntmp->ntm_ic_l2u) { - for (i = 0, j = 0; i < ustrlen && j < astrlen; i++) { - len = 4; - res = ((int) NTFS_TOUPPER(ustr[i])) - - ((int)NTFS_TOUPPER(NTFS_82U(astrp, &len))); - astrp += len; - j += len; - mbstrlen -= len - 1; - - if (res) - return res; - } - } else { - /* - * We use NTFS_82U(NTFS_U28(c)) to get rid of unicode - * symbols not covered by translation table - */ - for (i = 0; i < ustrlen && i < astrlen; i++) { - res = ((int) NTFS_TOUPPER(NTFS_82U(NTFS_U28(ustr[i]), &len))) - - ((int)NTFS_TOUPPER(NTFS_82U(astrp, &len))); - astrp++; - if (res) - return res; - } - } - return (ustrlen - mbstrlen); -} - -/* - * Compare unicode and ascii string case sens. - */ -static int -ntfs_uastrcmp(ntmp, ustr, ustrlen, astr, astrlen) - struct ntfsmount *ntmp; - const wchar *ustr; - size_t ustrlen; - const char *astr; - size_t astrlen; -{ - char *c, tmpbuf[5]; - size_t i, j, mbstrlen = astrlen; - int res; - - for (i = 0, j = 0; (i < ustrlen) && (j < astrlen); i++, mbstrlen++) { - c = NTFS_U28(ustr[i]); - while (*c != '\0') { - res = (int) (*c++ - astr[j++]); - if (res) - return res; - mbstrlen--; - } - } - return (ustrlen - mbstrlen); -} - -/* - * Search fnode in ntnode, if not found allocate and preinitialize. - * - * ntnode should be locked on entry. - */ -int -ntfs_fget( - struct ntfsmount *ntmp, - struct ntnode *ip, - int attrtype, - char *attrname, - struct fnode **fpp) -{ - struct fnode *fp; - - dprintf(("ntfs_fget: ino: %d, attrtype: 0x%x, attrname: %s\n", - ip->i_number,attrtype, attrname?attrname:"")); - *fpp = NULL; - LIST_FOREACH(fp, &ip->i_fnlist, f_fnlist){ - dprintf(("ntfs_fget: fnode: attrtype: %d, attrname: %s\n", - fp->f_attrtype, fp->f_attrname?fp->f_attrname:"")); - - if ((attrtype == fp->f_attrtype) && - ((!attrname && !fp->f_attrname) || - (attrname && fp->f_attrname && - !strcmp(attrname,fp->f_attrname)))){ - dprintf(("ntfs_fget: found existed: %p\n",fp)); - *fpp = fp; - } - } - - if (*fpp) - return (0); - - fp = malloc(sizeof(struct fnode), M_NTFSFNODE, - M_WAITOK | M_ZERO); - dprintf(("ntfs_fget: allocating fnode: %p\n",fp)); - - fp->f_ip = ip; - if (attrname) { - fp->f_flag |= FN_AATTRNAME; - fp->f_attrname = malloc(strlen(attrname)+1, M_TEMP, M_WAITOK); - strcpy(fp->f_attrname, attrname); - } else - fp->f_attrname = NULL; - fp->f_attrtype = attrtype; - - ntfs_ntref(ip); - - LIST_INSERT_HEAD(&ip->i_fnlist, fp, f_fnlist); - - *fpp = fp; - - return (0); -} - -/* - * Deallocate fnode, remove it from ntnode's fnode list. - * - * ntnode should be locked. - */ -void -ntfs_frele( - struct fnode *fp) -{ - struct ntnode *ip = FTONT(fp); - - dprintf(("ntfs_frele: fnode: %p for %d: %p\n", fp, ip->i_number, ip)); - - dprintf(("ntfs_frele: deallocating fnode\n")); - LIST_REMOVE(fp,f_fnlist); - if (fp->f_flag & FN_AATTRNAME) - free(fp->f_attrname, M_TEMP); - if (fp->f_dirblbuf) - free(fp->f_dirblbuf, M_NTFSDIR); - free(fp, M_NTFSFNODE); - ntfs_ntrele(ip); -} - -/* - * Lookup attribute name in format: [[:$ATTR_TYPE]:$ATTR_NAME], - * $ATTR_TYPE is searched in attrdefs read from $AttrDefs. - * If $ATTR_TYPE nott specifed, ATTR_A_DATA assumed. - */ -static int -ntfs_ntlookupattr( - struct ntfsmount * ntmp, - const char * name, - int namelen, - int *attrtype, - char **attrname) -{ - const char *sys; - size_t syslen, i; - struct ntvattrdef *adp; - - if (namelen == 0) - return (0); - - if (name[0] == '$') { - sys = name; - for (syslen = 0; syslen < namelen; syslen++) { - if(sys[syslen] == ':') { - name++; - namelen--; - break; - } - } - name += syslen; - namelen -= syslen; - - adp = ntmp->ntm_ad; - for (i = 0; i < ntmp->ntm_adnum; i++, adp++){ - if (syslen != adp->ad_namelen || - strncmp(sys, adp->ad_name, syslen) != 0) - continue; - - *attrtype = adp->ad_type; - goto out; - } - return (ENOENT); - } else - *attrtype = NTFS_A_DATA; - - out: - if (namelen) { - (*attrname) = malloc(namelen, M_TEMP, M_WAITOK); - memcpy((*attrname), name, namelen); - (*attrname)[namelen] = '\0'; - } - - return (0); -} - -/* - * Lookup specifed node for filename, matching cnp, - * return fnode filled. - */ -int -ntfs_ntlookupfile( - struct ntfsmount * ntmp, - struct vnode * vp, - struct componentname * cnp, - struct vnode ** vpp) -{ - struct fnode *fp = VTOF(vp); - struct ntnode *ip = FTONT(fp); - struct ntvattr *vap; /* Root attribute */ - cn_t cn; /* VCN in current attribute */ - caddr_t rdbuf; /* Buffer to read directory's blocks */ - u_int32_t blsize; - u_int64_t rdsize; /* Length of data to read from current block */ - struct attr_indexentry *iep; - int error, res, anamelen, fnamelen; - const char *fname,*aname; - u_int32_t aoff; - int attrtype = NTFS_A_DATA; - char *attrname = NULL; - struct fnode *nfp; - struct vnode *nvp; - enum vtype f_type; - - error = ntfs_ntget(ip); - if (error) - return (error); - - error = ntfs_ntvattrget(ntmp, ip, NTFS_A_INDXROOT, "$I30", 0, &vap); - if (error || (vap->va_flag & NTFS_AF_INRUN)) - return (ENOTDIR); - - blsize = vap->va_a_iroot->ir_size; - rdsize = vap->va_datalen; - - /* - * Divide file name into: foofilefoofilefoofile[:attrspec] - * Store like this: fname:fnamelen [aname:anamelen] - */ - fname = cnp->cn_nameptr; - aname = NULL; - anamelen = 0; - for (fnamelen = 0; fnamelen < cnp->cn_namelen; fnamelen++) - if(fname[fnamelen] == ':') { - aname = fname + fnamelen + 1; - anamelen = cnp->cn_namelen - fnamelen - 1; - dprintf(("ntfs_ntlookupfile: %s (%d), attr: %s (%d)\n", - fname, fnamelen, aname, anamelen)); - break; - } - - dprintf(("ntfs_ntlookupfile: blksz: %d, rdsz: %jd\n", blsize, rdsize)); - - rdbuf = malloc(blsize, M_TEMP, M_WAITOK); - - error = ntfs_readattr(ntmp, ip, NTFS_A_INDXROOT, "$I30", - 0, rdsize, rdbuf, NULL); - if (error) - goto fail; - - aoff = sizeof(struct attr_indexroot); - - do { - iep = (struct attr_indexentry *) (rdbuf + aoff); - - for (; !(iep->ie_flag & NTFS_IEFLAG_LAST) && (rdsize > aoff); - aoff += iep->reclen, - iep = (struct attr_indexentry *) (rdbuf + aoff)) - { - ddprintf(("scan: %d, %d\n", - (u_int32_t) iep->ie_number, - (u_int32_t) iep->ie_fnametype)); - - /* check the name - the case-insensitible check - * has to come first, to break from this for loop - * if needed, so we can dive correctly */ - res = NTFS_UASTRICMP(iep->ie_fname, iep->ie_fnamelen, - fname, fnamelen); - if (res > 0) break; - if (res < 0) continue; - - if (iep->ie_fnametype == 0 || - !(ntmp->ntm_flag & NTFS_MFLAG_CASEINS)) - { - res = NTFS_UASTRCMP(iep->ie_fname, - iep->ie_fnamelen, fname, fnamelen); - if (res != 0) continue; - } - - if (aname) { - error = ntfs_ntlookupattr(ntmp, - aname, anamelen, - &attrtype, &attrname); - if (error) - goto fail; - } - - /* Check if we've found ourself */ - if ((iep->ie_number == ip->i_number) && - (attrtype == fp->f_attrtype) && - ((!attrname && !fp->f_attrname) || - (attrname && fp->f_attrname && - !strcmp(attrname, fp->f_attrname)))) - { - VREF(vp); - *vpp = vp; - error = 0; - goto fail; - } - - /* vget node, but don't load it */ - error = ntfs_vgetex(ntmp->ntm_mountp, - iep->ie_number, attrtype, attrname, - LK_EXCLUSIVE, VG_DONTLOADIN | VG_DONTVALIDFN, - curthread, &nvp); - - /* free the buffer returned by ntfs_ntlookupattr() */ - if (attrname) { - free(attrname, M_TEMP); - attrname = NULL; - } - - if (error) - goto fail; - - nfp = VTOF(nvp); - - if (nfp->f_flag & FN_VALID) { - *vpp = nvp; - goto fail; - } - - nfp->f_fflag = iep->ie_fflag; - nfp->f_pnumber = iep->ie_fpnumber; - nfp->f_times = iep->ie_ftimes; - - if((nfp->f_fflag & NTFS_FFLAG_DIR) && - (nfp->f_attrtype == NTFS_A_DATA) && - (nfp->f_attrname == NULL)) - f_type = VDIR; - else - f_type = VREG; - - nvp->v_type = f_type; - - if ((nfp->f_attrtype == NTFS_A_DATA) && - (nfp->f_attrname == NULL)) - { - /* Opening default attribute */ - nfp->f_size = iep->ie_fsize; - nfp->f_allocated = iep->ie_fallocated; - nfp->f_flag |= FN_PRELOADED; - } else { - error = ntfs_filesize(ntmp, nfp, - &nfp->f_size, &nfp->f_allocated); - if (error) { - vput(nvp); - goto fail; - } - } - - nfp->f_flag &= ~FN_VALID; - *vpp = nvp; - goto fail; - } - - /* Dive if possible */ - if (iep->ie_flag & NTFS_IEFLAG_SUBNODE) { - dprintf(("ntfs_ntlookupfile: diving\n")); - - cn = *(cn_t *) (rdbuf + aoff + - iep->reclen - sizeof(cn_t)); - rdsize = blsize; - - error = ntfs_readattr(ntmp, ip, NTFS_A_INDX, "$I30", - ntfs_cntob(cn), rdsize, rdbuf, NULL); - if (error) - goto fail; - - error = ntfs_procfixups(ntmp, NTFS_INDXMAGIC, - rdbuf, rdsize); - if (error) - goto fail; - - aoff = (((struct attr_indexalloc *) rdbuf)->ia_hdrsize + - 0x18); - } else { - dprintf(("ntfs_ntlookupfile: nowhere to dive :-(\n")); - error = ENOENT; - break; - } - } while (1); - - dprintf(("finish\n")); - -fail: - if (attrname) free(attrname, M_TEMP); - ntfs_ntvattrrele(vap); - ntfs_ntput(ip); - free(rdbuf, M_TEMP); - return (error); -} - -/* - * Check if name type is permitted to show. - */ -int -ntfs_isnamepermitted( - struct ntfsmount * ntmp, - struct attr_indexentry * iep) -{ - if (ntmp->ntm_flag & NTFS_MFLAG_ALLNAMES) - return 1; - - switch (iep->ie_fnametype) { - case 2: - ddprintf(("ntfs_isnamepermitted: skipped DOS name\n")); - return 0; - case 0: case 1: case 3: - return 1; - default: - printf("ntfs_isnamepermitted: " \ - "WARNING! Unknown file name type: %d\n", - iep->ie_fnametype); - break; - } - return 0; -} - -/* - * Read ntfs dir like stream of attr_indexentry, not like btree of them. - * This is done by scaning $BITMAP:$I30 for busy clusters and reading them. - * Ofcouse $INDEX_ROOT:$I30 is read before. Last read values are stored in - * fnode, so we can skip toward record number num almost immediatly. - * Anyway this is rather slow routine. The problem is that we don't know - * how many records are there in $INDEX_ALLOCATION:$I30 block. - */ -int -ntfs_ntreaddir( - struct ntfsmount * ntmp, - struct fnode * fp, - u_int32_t num, - struct attr_indexentry ** riepp) -{ - struct ntnode *ip = FTONT(fp); - struct ntvattr *vap = NULL; /* IndexRoot attribute */ - struct ntvattr *bmvap = NULL; /* BitMap attribute */ - struct ntvattr *iavap = NULL; /* IndexAllocation attribute */ - caddr_t rdbuf; /* Buffer to read directory's blocks */ - u_int8_t *bmp = NULL; /* Bitmap */ - u_int32_t blsize; /* Index allocation size (2048) */ - u_int32_t rdsize; /* Length of data to read */ - u_int32_t attrnum; /* Current attribute type */ - u_int32_t cpbl = 1; /* Clusters per directory block */ - u_int32_t blnum; - struct attr_indexentry *iep; - int error = ENOENT; - u_int32_t aoff, cnum; - - dprintf(("ntfs_ntreaddir: read ino: %d, num: %d\n", ip->i_number, num)); - error = ntfs_ntget(ip); - if (error) - return (error); - - error = ntfs_ntvattrget(ntmp, ip, NTFS_A_INDXROOT, "$I30", 0, &vap); - if (error) - return (ENOTDIR); - - if (fp->f_dirblbuf == NULL) { - fp->f_dirblsz = vap->va_a_iroot->ir_size; - fp->f_dirblbuf = malloc(max(vap->va_datalen,fp->f_dirblsz), - M_NTFSDIR, M_WAITOK); - } - - blsize = fp->f_dirblsz; - rdbuf = fp->f_dirblbuf; - - dprintf(("ntfs_ntreaddir: rdbuf: %p, blsize: %d\n", rdbuf, blsize)); - - if (vap->va_a_iroot->ir_flag & NTFS_IRFLAG_INDXALLOC) { - error = ntfs_ntvattrget(ntmp, ip, NTFS_A_INDXBITMAP, "$I30", - 0, &bmvap); - if (error) { - error = ENOTDIR; - goto fail; - } - bmp = malloc(bmvap->va_datalen, M_TEMP, M_WAITOK); - error = ntfs_readattr(ntmp, ip, NTFS_A_INDXBITMAP, "$I30", 0, - bmvap->va_datalen, bmp, NULL); - if (error) - goto fail; - - error = ntfs_ntvattrget(ntmp, ip, NTFS_A_INDX, "$I30", - 0, &iavap); - if (error) { - error = ENOTDIR; - goto fail; - } - cpbl = ntfs_btocn(blsize + ntfs_cntob(1) - 1); - dprintf(("ntfs_ntreaddir: indexalloc: %jd, cpbl: %d\n", - iavap->va_datalen, cpbl)); - } else { - dprintf(("ntfs_ntreadidir: w/o BitMap and IndexAllocation\n")); - iavap = bmvap = NULL; - bmp = NULL; - } - - /* Try use previous values */ - if ((fp->f_lastdnum < num) && (fp->f_lastdnum != 0)) { - attrnum = fp->f_lastdattr; - aoff = fp->f_lastdoff; - blnum = fp->f_lastdblnum; - cnum = fp->f_lastdnum; - } else { - attrnum = NTFS_A_INDXROOT; - aoff = sizeof(struct attr_indexroot); - blnum = 0; - cnum = 0; - } - - do { - dprintf(("ntfs_ntreaddir: scan: 0x%x, %d, %d, %d, %d\n", - attrnum, (u_int32_t) blnum, cnum, num, aoff)); - rdsize = (attrnum == NTFS_A_INDXROOT) ? vap->va_datalen : blsize; - error = ntfs_readattr(ntmp, ip, attrnum, "$I30", - ntfs_cntob(blnum * cpbl), rdsize, rdbuf, NULL); - if (error) - goto fail; - - if (attrnum == NTFS_A_INDX) { - error = ntfs_procfixups(ntmp, NTFS_INDXMAGIC, - rdbuf, rdsize); - if (error) - goto fail; - } - if (aoff == 0) - aoff = (attrnum == NTFS_A_INDX) ? - (0x18 + ((struct attr_indexalloc *) rdbuf)->ia_hdrsize) : - sizeof(struct attr_indexroot); - - iep = (struct attr_indexentry *) (rdbuf + aoff); - for (; !(iep->ie_flag & NTFS_IEFLAG_LAST) && (rdsize > aoff); - aoff += iep->reclen, - iep = (struct attr_indexentry *) (rdbuf + aoff)) - { - if (!ntfs_isnamepermitted(ntmp, iep)) continue; - - if (cnum >= num) { - fp->f_lastdnum = cnum; - fp->f_lastdoff = aoff; - fp->f_lastdblnum = blnum; - fp->f_lastdattr = attrnum; - - *riepp = iep; - - error = 0; - goto fail; - } - cnum++; - } - - if (iavap) { - if (attrnum == NTFS_A_INDXROOT) - blnum = 0; - else - blnum++; - - while (ntfs_cntob(blnum * cpbl) < iavap->va_datalen) { - if (bmp[blnum >> 3] & (1 << (blnum & 7))) - break; - blnum++; - } - - attrnum = NTFS_A_INDX; - aoff = 0; - if (ntfs_cntob(blnum * cpbl) >= iavap->va_datalen) - break; - dprintf(("ntfs_ntreaddir: blnum: %d\n", (u_int32_t) blnum)); - } - } while (iavap); - - *riepp = NULL; - fp->f_lastdnum = 0; - -fail: - if (vap) - ntfs_ntvattrrele(vap); - if (bmvap) - ntfs_ntvattrrele(bmvap); - if (iavap) - ntfs_ntvattrrele(iavap); - if (bmp) - free(bmp, M_TEMP); - ntfs_ntput(ip); - return (error); -} - -/* - * Convert NTFS times that are in 100 ns units and begins from - * 1601 Jan 1 into unix times. - */ -struct timespec -ntfs_nttimetounix( - u_int64_t nt) -{ - struct timespec t; - - /* WindowNT times are in 100 ns and from 1601 Jan 1 */ - t.tv_nsec = (nt % (1000 * 1000 * 10)) * 100; - t.tv_sec = nt / (1000 * 1000 * 10) - - 369LL * 365LL * 24LL * 60LL * 60LL - - 89LL * 1LL * 24LL * 60LL * 60LL; - return (t); -} - -/* - * Get file times from NTFS_A_NAME attribute. - */ -int -ntfs_times( - struct ntfsmount * ntmp, - struct ntnode * ip, - ntfs_times_t * tm) -{ - struct ntvattr *vap; - int error; - - dprintf(("ntfs_times: ino: %d...\n", ip->i_number)); - - error = ntfs_ntget(ip); - if (error) - return (error); - - error = ntfs_ntvattrget(ntmp, ip, NTFS_A_NAME, NULL, 0, &vap); - if (error) { - ntfs_ntput(ip); - return (error); - } - *tm = vap->va_a_name->n_times; - ntfs_ntvattrrele(vap); - ntfs_ntput(ip); - - return (0); -} - -/* - * Get file sizes from corresponding attribute. - * - * ntnode under fnode should be locked. - */ -int -ntfs_filesize( - struct ntfsmount * ntmp, - struct fnode * fp, - u_int64_t * size, - u_int64_t * bytes) -{ - struct ntvattr *vap; - struct ntnode *ip = FTONT(fp); - u_int64_t sz, bn; - int error; - - dprintf(("ntfs_filesize: ino: %d\n", ip->i_number)); - - error = ntfs_ntvattrget(ntmp, ip, - fp->f_attrtype, fp->f_attrname, 0, &vap); - if (error) - return (error); - - bn = vap->va_allocated; - sz = vap->va_datalen; - - dprintf(("ntfs_filesize: %d bytes (%d bytes allocated)\n", - (u_int32_t) sz, (u_int32_t) bn)); - - if (size) - *size = sz; - if (bytes) - *bytes = bn; - - ntfs_ntvattrrele(vap); - - return (0); -} - -/* - * This is one of write routine. - */ -int -ntfs_writeattr_plain( - struct ntfsmount * ntmp, - struct ntnode * ip, - u_int32_t attrnum, - char *attrname, - off_t roff, - size_t rsize, - void *rdata, - size_t * initp, - struct uio *uio) -{ - size_t init; - int error = 0; - off_t off = roff, left = rsize, towrite; - caddr_t data = rdata; - struct ntvattr *vap; - *initp = 0; - - while (left) { - error = ntfs_ntvattrget(ntmp, ip, attrnum, attrname, - ntfs_btocn(off), &vap); - if (error) - return (error); - towrite = MIN(left, ntfs_cntob(vap->va_vcnend + 1) - off); - ddprintf(("ntfs_writeattr_plain: o: %d, s: %d (%d - %d)\n", - (u_int32_t) off, (u_int32_t) towrite, - (u_int32_t) vap->va_vcnstart, - (u_int32_t) vap->va_vcnend)); - error = ntfs_writentvattr_plain(ntmp, ip, vap, - off - ntfs_cntob(vap->va_vcnstart), - towrite, data, &init, uio); - if (error) { - printf("ntfs_writeattr_plain: " \ - "ntfs_writentvattr_plain failed: o: %d, s: %d\n", - (u_int32_t) off, (u_int32_t) towrite); - printf("ntfs_writeattr_plain: attrib: %d - %d\n", - (u_int32_t) vap->va_vcnstart, - (u_int32_t) vap->va_vcnend); - ntfs_ntvattrrele(vap); - break; - } - ntfs_ntvattrrele(vap); - left -= towrite; - off += towrite; - data = data + towrite; - *initp += init; - } - - return (error); -} - -/* - * This is one of write routine. - * - * ntnode should be locked. - */ -int -ntfs_writentvattr_plain( - struct ntfsmount * ntmp, - struct ntnode * ip, - struct ntvattr * vap, - off_t roff, - size_t rsize, - void *rdata, - size_t * initp, - struct uio *uio) -{ - int error = 0; - off_t off; - int cnt; - cn_t ccn, ccl, cn, left, cl; - caddr_t data = rdata; - struct buf *bp; - size_t tocopy; - - *initp = 0; - - if ((vap->va_flag & NTFS_AF_INRUN) == 0) { - printf("ntfs_writevattr_plain: CAN'T WRITE RES. ATTRIBUTE\n"); - return ENOTTY; - } - - ddprintf(("ntfs_writentvattr_plain: data in run: %ld chains\n", - vap->va_vruncnt)); - - off = roff; - left = rsize; - ccl = 0; - ccn = 0; - cnt = 0; - for (; left && (cnt < vap->va_vruncnt); cnt++) { - ccn = vap->va_vruncn[cnt]; - ccl = vap->va_vruncl[cnt]; - - ddprintf(("ntfs_writentvattr_plain: " \ - "left %d, cn: 0x%x, cl: %d, off: %d\n", \ - (u_int32_t) left, (u_int32_t) ccn, \ - (u_int32_t) ccl, (u_int32_t) off)); - - if (ntfs_cntob(ccl) < off) { - off -= ntfs_cntob(ccl); - cnt++; - continue; - } - if (!ccn && ip->i_number != NTFS_BOOTINO) - continue; /* XXX */ - - ccl -= ntfs_btocn(off); - cn = ccn + ntfs_btocn(off); - off = ntfs_btocnoff(off); - - while (left && ccl) { - /* - * Always read and write single clusters at a time - - * we need to avoid requesting differently-sized - * blocks at the same disk offsets to avoid - * confusing the buffer cache. - */ - tocopy = MIN(left, ntfs_cntob(1) - off); - cl = ntfs_btocl(tocopy + off); - KASSERT(cl == 1 && tocopy <= ntfs_cntob(1), - ("single cluster limit mistake")); - ddprintf(("ntfs_writentvattr_plain: write: " \ - "cn: 0x%x cl: %d, off: %d len: %d, left: %d\n", - (u_int32_t) cn, (u_int32_t) cl, - (u_int32_t) off, (u_int32_t) tocopy, - (u_int32_t) left)); - if ((off == 0) && (tocopy == ntfs_cntob(cl))) - { - bp = getblk(ntmp->ntm_devvp, ntfs_cntobn(cn) - * ntmp->ntm_multiplier, - ntfs_cntob(cl), 0, 0, 0); - clrbuf(bp); - } else { - error = bread(ntmp->ntm_devvp, ntfs_cntobn(cn) - * ntmp->ntm_multiplier, - ntfs_cntob(cl), NOCRED, &bp); - if (error) { - brelse(bp); - return (error); - } - } - if (uio) - uiomove(bp->b_data + off, tocopy, uio); - else - memcpy(bp->b_data + off, data, tocopy); - bawrite(bp); - data = data + tocopy; - *initp += tocopy; - off = 0; - left -= tocopy; - cn += cl; - ccl -= cl; - } - } - - if (left) { - printf("ntfs_writentvattr_plain: POSSIBLE RUN ERROR\n"); - error = EINVAL; - } - - return (error); -} - -/* - * This is one of read routines. - * - * ntnode should be locked. - */ -int -ntfs_readntvattr_plain( - struct ntfsmount * ntmp, - struct ntnode * ip, - struct ntvattr * vap, - off_t roff, - size_t rsize, - void *rdata, - size_t * initp, - struct uio *uio) -{ - int error = 0; - off_t off; - - *initp = 0; - if (vap->va_flag & NTFS_AF_INRUN) { - int cnt; - cn_t ccn, ccl, cn, left, cl; - caddr_t data = rdata; - struct buf *bp; - size_t tocopy; - - ddprintf(("ntfs_readntvattr_plain: data in run: %ld chains\n", - vap->va_vruncnt)); - - off = roff; - left = rsize; - ccl = 0; - ccn = 0; - cnt = 0; - while (left && (cnt < vap->va_vruncnt)) { - ccn = vap->va_vruncn[cnt]; - ccl = vap->va_vruncl[cnt]; - - ddprintf(("ntfs_readntvattr_plain: " \ - "left %d, cn: 0x%x, cl: %d, off: %d\n", \ - (u_int32_t) left, (u_int32_t) ccn, \ - (u_int32_t) ccl, (u_int32_t) off)); - - if (ntfs_cntob(ccl) < off) { - off -= ntfs_cntob(ccl); - cnt++; - continue; - } - if (ccn || ip->i_number == NTFS_BOOTINO) { - ccl -= ntfs_btocn(off); - cn = ccn + ntfs_btocn(off); - off = ntfs_btocnoff(off); - - while (left && ccl) { - /* - * Always read single clusters at a - * time - we need to avoid reading - * differently-sized blocks at the - * same disk offsets to avoid - * confusing the buffer cache. - */ - tocopy = MIN(left, - ntfs_cntob(1) - off); - cl = ntfs_btocl(tocopy + off); - KASSERT(cl == 1 && - tocopy <= ntfs_cntob(1), - ("single cluster limit mistake")); - - ddprintf(("ntfs_readntvattr_plain: " \ - "read: cn: 0x%x cl: %d, " \ - "off: %d len: %d, left: %d\n", - (u_int32_t) cn, - (u_int32_t) cl, - (u_int32_t) off, - (u_int32_t) tocopy, - (u_int32_t) left)); - error = bread(ntmp->ntm_devvp, - ntfs_cntobn(cn) - * ntmp->ntm_multiplier, - ntfs_cntob(cl), - NOCRED, &bp); - if (error) { - brelse(bp); - return (error); - } - if (uio) { - uiomove(bp->b_data + off, - tocopy, uio); - } else { - memcpy(data, bp->b_data + off, - tocopy); - } - brelse(bp); - data = data + tocopy; - *initp += tocopy; - off = 0; - left -= tocopy; - cn += cl; - ccl -= cl; - } - } else { - tocopy = MIN(left, ntfs_cntob(ccl) - off); - ddprintf(("ntfs_readntvattr_plain: " - "hole: ccn: 0x%x ccl: %d, off: %d, " \ - " len: %d, left: %d\n", - (u_int32_t) ccn, (u_int32_t) ccl, - (u_int32_t) off, (u_int32_t) tocopy, - (u_int32_t) left)); - left -= tocopy; - off = 0; - if (uio) { - size_t remains = tocopy; - for(; remains; remains--) - uiomove("", 1, uio); - } else - bzero(data, tocopy); - data = data + tocopy; - } - cnt++; - } - if (left) { - printf("ntfs_readntvattr_plain: POSSIBLE RUN ERROR\n"); - error = E2BIG; - } - } else { - ddprintf(("ntfs_readnvattr_plain: data is in mft record\n")); - if (uio) - uiomove(vap->va_datap + roff, rsize, uio); - else - memcpy(rdata, vap->va_datap + roff, rsize); - *initp += rsize; - } - - return (error); -} - -/* - * This is one of read routines. - */ -int -ntfs_readattr_plain( - struct ntfsmount * ntmp, - struct ntnode * ip, - u_int32_t attrnum, - char *attrname, - off_t roff, - size_t rsize, - void *rdata, - size_t * initp, - struct uio *uio) -{ - size_t init; - int error = 0; - off_t off = roff, left = rsize, toread; - caddr_t data = rdata; - struct ntvattr *vap; - *initp = 0; - - while (left) { - error = ntfs_ntvattrget(ntmp, ip, attrnum, attrname, - ntfs_btocn(off), &vap); - if (error) - return (error); - toread = MIN(left, ntfs_cntob(vap->va_vcnend + 1) - off); - ddprintf(("ntfs_readattr_plain: o: %d, s: %d (%d - %d)\n", - (u_int32_t) off, (u_int32_t) toread, - (u_int32_t) vap->va_vcnstart, - (u_int32_t) vap->va_vcnend)); - error = ntfs_readntvattr_plain(ntmp, ip, vap, - off - ntfs_cntob(vap->va_vcnstart), - toread, data, &init, uio); - if (error) { - printf("ntfs_readattr_plain: " \ - "ntfs_readntvattr_plain failed: o: %d, s: %d\n", - (u_int32_t) off, (u_int32_t) toread); - printf("ntfs_readattr_plain: attrib: %d - %d\n", - (u_int32_t) vap->va_vcnstart, - (u_int32_t) vap->va_vcnend); - ntfs_ntvattrrele(vap); - break; - } - ntfs_ntvattrrele(vap); - left -= toread; - off += toread; - data = data + toread; - *initp += init; - } - - return (error); -} - -/* - * This is one of read routines. - */ -int -ntfs_readattr( - struct ntfsmount * ntmp, - struct ntnode * ip, - u_int32_t attrnum, - char *attrname, - off_t roff, - size_t rsize, - void *rdata, - struct uio *uio) -{ - int error = 0; - struct ntvattr *vap; - size_t init; - - ddprintf(("ntfs_readattr: reading %d: 0x%x, from %d size %d bytes\n", - ip->i_number, attrnum, (u_int32_t) roff, (u_int32_t) rsize)); - - error = ntfs_ntvattrget(ntmp, ip, attrnum, attrname, 0, &vap); - if (error) - return (error); - - if ((roff > vap->va_datalen) || - (roff + rsize > vap->va_datalen)) { - ddprintf(("ntfs_readattr: offset too big\n")); - ntfs_ntvattrrele(vap); - return (E2BIG); - } - if (vap->va_compression && vap->va_compressalg) { - u_int8_t *cup; - u_int8_t *uup; - off_t off = roff, left = rsize, tocopy; - caddr_t data = rdata; - cn_t cn; - - ddprintf(("ntfs_ntreadattr: compression: %d\n", - vap->va_compressalg)); - - cup = malloc(ntfs_cntob(NTFS_COMPUNIT_CL), - M_NTFSDECOMP, M_WAITOK); - uup = malloc(ntfs_cntob(NTFS_COMPUNIT_CL), - M_NTFSDECOMP, M_WAITOK); - - cn = (ntfs_btocn(roff)) & (~(NTFS_COMPUNIT_CL - 1)); - off = roff - ntfs_cntob(cn); - - while (left) { - error = ntfs_readattr_plain(ntmp, ip, attrnum, - attrname, ntfs_cntob(cn), - ntfs_cntob(NTFS_COMPUNIT_CL), - cup, &init, NULL); - if (error) - break; - - tocopy = MIN(left, ntfs_cntob(NTFS_COMPUNIT_CL) - off); - - if (init == ntfs_cntob(NTFS_COMPUNIT_CL)) { - if (uio) - uiomove(cup + off, tocopy, uio); - else - memcpy(data, cup + off, tocopy); - } else if (init == 0) { - if (uio) { - size_t remains = tocopy; - for(; remains; remains--) - uiomove("", 1, uio); - } - else - bzero(data, tocopy); - } else { - error = ntfs_uncompunit(ntmp, uup, cup); - if (error) - break; - if (uio) - uiomove(uup + off, tocopy, uio); - else - memcpy(data, uup + off, tocopy); - } - - left -= tocopy; - data = data + tocopy; - off += tocopy - ntfs_cntob(NTFS_COMPUNIT_CL); - cn += NTFS_COMPUNIT_CL; - } - - free(uup, M_NTFSDECOMP); - free(cup, M_NTFSDECOMP); - } else - error = ntfs_readattr_plain(ntmp, ip, attrnum, attrname, - roff, rsize, rdata, &init, uio); - ntfs_ntvattrrele(vap); - return (error); -} - -#if 0 -int -ntfs_parserun( - cn_t * cn, - cn_t * cl, - u_int8_t * run, - u_long len, - u_long *off) -{ - u_int8_t sz; - int i; - - if (NULL == run) { - printf("ntfs_parsetun: run == NULL\n"); - return (EINVAL); - } - sz = run[(*off)++]; - if (0 == sz) { - printf("ntfs_parserun: trying to go out of run\n"); - return (E2BIG); - } - *cl = 0; - if ((sz & 0xF) > 8 || (*off) + (sz & 0xF) > len) { - printf("ntfs_parserun: " \ - "bad run: length too big: sz: 0x%02x (%ld < %ld + sz)\n", - sz, len, *off); - return (EINVAL); - } - for (i = 0; i < (sz & 0xF); i++) - *cl += (u_int32_t) run[(*off)++] << (i << 3); - - sz >>= 4; - if ((sz & 0xF) > 8 || (*off) + (sz & 0xF) > len) { - printf("ntfs_parserun: " \ - "bad run: length too big: sz: 0x%02x (%ld < %ld + sz)\n", - sz, len, *off); - return (EINVAL); - } - for (i = 0; i < (sz & 0xF); i++) - *cn += (u_int32_t) run[(*off)++] << (i << 3); - - return (0); -} -#endif - -/* - * Process fixup routine on given buffer. - */ -int -ntfs_procfixups( - struct ntfsmount * ntmp, - u_int32_t magic, - caddr_t buf, - size_t len) -{ - struct fixuphdr *fhp = (struct fixuphdr *) buf; - int i; - u_int16_t fixup; - u_int16_t *fxp; - u_int16_t *cfxp; - - if (fhp->fh_magic != magic) { - printf("ntfs_procfixups: magic doesn't match: %08x != %08x\n", - fhp->fh_magic, magic); - return (EINVAL); - } - if ((fhp->fh_fnum - 1) * NTFS_BLOCK_SIZE != len) { - printf("ntfs_procfixups: " \ - "bad fixups number: %d for %ld bytes block\n", - fhp->fh_fnum, (long)len); /* XXX printf kludge */ - return (EINVAL); - } - if (fhp->fh_foff >= ntmp->ntm_spc * ntmp->ntm_mftrecsz * ntmp->ntm_bps) { - printf("ntfs_procfixups: invalid offset: %x", fhp->fh_foff); - return (EINVAL); - } - fxp = (u_int16_t *) (buf + fhp->fh_foff); - cfxp = (u_int16_t *) (buf + NTFS_BLOCK_SIZE - 2); - fixup = *fxp++; - for (i = 1; i < fhp->fh_fnum; i++, fxp++) { - if (*cfxp != fixup) { - printf("ntfs_procfixups: fixup %d doesn't match\n", i); - return (EINVAL); - } - *cfxp = *fxp; - cfxp = (u_int16_t *) ((caddr_t) cfxp + NTFS_BLOCK_SIZE); - } - return (0); -} - -#if 0 -int -ntfs_runtocn( - cn_t * cn, - struct ntfsmount * ntmp, - u_int8_t * run, - u_long len, - cn_t vcn) -{ - cn_t ccn = 0; - cn_t ccl = 0; - u_long off = 0; - int error = 0; - -#if NTFS_DEBUG - int i; - printf("ntfs_runtocn: run: %p, %ld bytes, vcn:%ld\n", - run, len, (u_long) vcn); - printf("ntfs_runtocn: run: "); - for (i = 0; i < len; i++) - printf("0x%02x ", run[i]); - printf("\n"); -#endif - - if (NULL == run) { - printf("ntfs_runtocn: run == NULL\n"); - return (EINVAL); - } - do { - if (run[off] == 0) { - printf("ntfs_runtocn: vcn too big\n"); - return (E2BIG); - } - vcn -= ccl; - error = ntfs_parserun(&ccn, &ccl, run, len, &off); - if (error) { - printf("ntfs_runtocn: ntfs_parserun failed\n"); - return (error); - } - } while (ccl <= vcn); - *cn = ccn + vcn; - return (0); -} -#endif - -/* - * this initializes toupper table & dependant variables to be ready for - * later work - */ -void -ntfs_toupper_init() -{ - ntfs_toupper_tab = (wchar *) NULL; - lockinit(&ntfs_toupper_lock, PVFS, "ntfs_toupper", 0, 0); - ntfs_toupper_usecount = 0; -} - -void -ntfs_toupper_destroy(void) -{ - - lockdestroy(&ntfs_toupper_lock); -} - -/* - * if the ntfs_toupper_tab[] is filled already, just raise use count; - * otherwise read the data from the filesystem we are currently mounting - */ -int -ntfs_toupper_use(mp, ntmp) - struct mount *mp; - struct ntfsmount *ntmp; -{ - int error = 0; - struct vnode *vp; - - /* get exclusive access */ - lockmgr(&ntfs_toupper_lock, LK_EXCLUSIVE, NULL); - - /* only read the translation data from a file if it hasn't been - * read already */ - if (ntfs_toupper_tab) - goto out; - - /* - * Read in Unicode lowercase -> uppercase translation file. - * XXX for now, just the first 256 entries are used anyway, - * so don't bother reading more - */ - ntfs_toupper_tab = malloc(65536 * sizeof(wchar), - M_NTFSRDATA, M_WAITOK); - - if ((error = VFS_VGET(mp, NTFS_UPCASEINO, LK_EXCLUSIVE, &vp))) - goto out; - error = ntfs_readattr(ntmp, VTONT(vp), NTFS_A_DATA, NULL, - 0, 65536*sizeof(wchar), (char *) ntfs_toupper_tab, NULL); - vput(vp); - - out: - ntfs_toupper_usecount++; - lockmgr(&ntfs_toupper_lock, LK_RELEASE, NULL); - return (error); -} - -/* - * lower the use count and if it reaches zero, free the memory - * tied by toupper table - */ -void -ntfs_toupper_unuse() -{ - /* get exclusive access */ - lockmgr(&ntfs_toupper_lock, LK_EXCLUSIVE, NULL); - - ntfs_toupper_usecount--; - if (ntfs_toupper_usecount == 0) { - free(ntfs_toupper_tab, M_NTFSRDATA); - ntfs_toupper_tab = NULL; - } -#ifdef DIAGNOSTIC - else if (ntfs_toupper_usecount < 0) { - panic("ntfs_toupper_unuse(): use count negative: %d\n", - ntfs_toupper_usecount); - } -#endif - - /* release the lock */ - lockmgr(&ntfs_toupper_lock, LK_RELEASE, NULL); -} - -int -ntfs_u28_init( - struct ntfsmount *ntmp, - wchar *u2w, - char *cs_local, - char *cs_ntfs) -{ - char ** u28; - int i, j, h, l; - - if (ntfs_iconv && cs_local) { - ntfs_iconv->open(cs_local, cs_ntfs, &ntmp->ntm_ic_u2l); - return (0); - } - - u28 = malloc(256 * sizeof(char*), M_TEMP, M_WAITOK | M_ZERO); - - for (i=0; i<256; i++) { - h = (u2w[i] >> 8) & 0xFF; - l = (u2w[i]) &0xFF; - - if (u28[h] == NULL) { - u28[h] = malloc(256 * sizeof(char), M_TEMP, M_WAITOK); - for (j=0; j<256; j++) - u28[h][j] = '_'; - } - - u28[h][l] = i & 0xFF; - } - - ntmp->ntm_u28 = u28; - - return (0); -} - -int -ntfs_u28_uninit(struct ntfsmount *ntmp) -{ - char ** u28; - int i; - - if (ntmp->ntm_u28 == NULL) { - if (ntfs_iconv && ntmp->ntm_ic_u2l) { - ntfs_iconv->close(ntmp->ntm_ic_u2l); - } - return (0); - } - - u28 = ntmp->ntm_u28; - - for (i=0; i<256; i++) - if (u28[i] != NULL) - free(u28[i], M_TEMP); - - free(u28, M_TEMP); - - return (0); -} - -int -ntfs_82u_init( - struct ntfsmount *ntmp, - char *cs_local, - char *cs_ntfs) -{ - wchar * _82u; - int i; - - if (ntfs_iconv && cs_local) { - ntfs_iconv->open(cs_ntfs, cs_local, &ntmp->ntm_ic_l2u); - return (0); - } - - _82u = malloc(256 * sizeof(wchar), M_TEMP, M_WAITOK); - - for (i=0; i<256; i++) - _82u[i] = i; - - ntmp->ntm_82u = _82u; - - return (0); -} - -int -ntfs_82u_uninit(struct ntfsmount *ntmp) -{ - - if (ntmp->ntm_82u == NULL) { - if (ntfs_iconv && ntmp->ntm_ic_l2u) { - ntfs_iconv->close(ntmp->ntm_ic_l2u); - } - return (0); - } - - free(ntmp->ntm_82u, M_TEMP); - return (0); -} - -/* - * maps the Unicode char to local character - */ -char * -ntfs_u28( - char *outbuf, - struct ntfsmount *ntmp, - wchar wc) -{ - char *p, *outp, inbuf[3]; - size_t ilen, olen; - - outp = outbuf; - if (ntfs_iconv && ntmp->ntm_ic_u2l) { - ilen = 2; - olen = 4; - - inbuf[0] = (char)(wc>>8); - inbuf[1] = (char)wc; - inbuf[2] = '\0'; - p = inbuf; - ntfs_iconv->convchr(ntmp->ntm_ic_u2l, (const char **)&p, &ilen, - &outp, &olen); - if (olen == 4) - *outp++ = '?'; - *outp = '\0'; - outp = outbuf; - return (outp); - } - - p = ntmp->ntm_u28[(wc>>8)&0xFF]; - outbuf[0] = (p == NULL) ? '_' : p[wc&0xFF] & 0xFF; - outbuf[1] = '\0'; - return (outp); -} - -wchar -ntfs_82u( - struct ntfsmount *ntmp, - const char *c, - int *len) -{ - char *outp, outbuf[3]; - wchar uc; - size_t ilen, olen; - - if (ntfs_iconv && ntmp->ntm_ic_l2u) { - ilen = (size_t)*len; - olen = 2; - - outp = outbuf; - ntfs_iconv->convchr(ntmp->ntm_ic_l2u, &c, &ilen, &outp, &olen); - *len -= (int)ilen; - uc = (wchar)((outbuf[0]<<8) | (outbuf[1]&0xFF)); - - return (uc); - } - - if (ntmp->ntm_82u != NULL) - return (ntmp->ntm_82u[*c&0xFF]); - - return ('?'); -} - diff --git a/sys/fs/ntfs/ntfs_subr.h b/sys/fs/ntfs/ntfs_subr.h deleted file mode 100644 index 7ec33213c38..00000000000 --- a/sys/fs/ntfs/ntfs_subr.h +++ /dev/null @@ -1,121 +0,0 @@ -/* $NetBSD: ntfs_subr.h,v 1.8 1999/10/10 14:48:37 jdolecek Exp $ */ - -/*- - * Copyright (c) 1998, 1999 Semen Ustimenko - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - */ - -#define VA_LOADED 0x0001 -#define VA_PRELOADED 0x0002 - -struct ntvattr { - LIST_ENTRY(ntvattr) va_list; - - u_int32_t va_vflag; - struct vnode *va_vp; - struct ntnode *va_ip; - - u_int32_t va_flag; - u_int32_t va_type; - u_int8_t va_namelen; - char va_name[NTFS_MAXATTRNAME]; - - u_int32_t va_compression; - u_int32_t va_compressalg; - u_int64_t va_datalen; - u_int64_t va_allocated; - cn_t va_vcnstart; - cn_t va_vcnend; - u_int16_t va_index; - union { - struct { - cn_t * cn; - cn_t * cl; - u_long cnt; - } vrun; - caddr_t datap; - struct attr_name *name; - struct attr_indexroot *iroot; - struct attr_indexalloc *ialloc; - } va_d; -}; -#define va_vruncn va_d.vrun.cn -#define va_vruncl va_d.vrun.cl -#define va_vruncnt va_d.vrun.cnt -#define va_datap va_d.datap -#define va_a_name va_d.name -#define va_a_iroot va_d.iroot -#define va_a_ialloc va_d.ialloc - -struct componentname; -struct fnode; -struct uio; - -int ntfs_procfixups( struct ntfsmount *, u_int32_t, caddr_t, size_t ); -int ntfs_parserun( cn_t *, cn_t *, u_int8_t *, u_long, u_long *); -int ntfs_runtocn( cn_t *, struct ntfsmount *, u_int8_t *, u_long, cn_t); -int ntfs_readntvattr_plain( struct ntfsmount *, struct ntnode *, struct ntvattr *, off_t, size_t, void *,size_t *, struct uio *); -int ntfs_readattr_plain( struct ntfsmount *, struct ntnode *, u_int32_t, char *, off_t, size_t, void *,size_t *, struct uio *); -int ntfs_readattr( struct ntfsmount *, struct ntnode *, u_int32_t, char *, off_t, size_t, void *, struct uio *); -int ntfs_filesize( struct ntfsmount *, struct fnode *, u_int64_t *, u_int64_t *); -int ntfs_times( struct ntfsmount *, struct ntnode *, ntfs_times_t *); -struct timespec ntfs_nttimetounix( u_int64_t ); -int ntfs_ntreaddir( struct ntfsmount *, struct fnode *, u_int32_t, struct attr_indexentry **); -int ntfs_runtovrun( cn_t **, cn_t **, u_long *, u_int8_t *); -int ntfs_attrtontvattr( struct ntfsmount *, struct ntvattr **, struct attr * ); -void ntfs_freentvattr( struct ntvattr * ); -int ntfs_loadntvattrs( struct ntfsmount *, struct vnode *, caddr_t, struct ntvattr **); -struct ntvattr * ntfs_findntvattr( struct ntfsmount *, struct ntnode *, u_int32_t, cn_t ); -int ntfs_ntlookupfile(struct ntfsmount *, struct vnode *, struct componentname *, struct vnode **); -int ntfs_isnamepermitted(struct ntfsmount *, struct attr_indexentry * ); -int ntfs_ntvattrrele(struct ntvattr * ); -int ntfs_ntvattrget(struct ntfsmount *, struct ntnode *, u_int32_t, const char *, cn_t , struct ntvattr **); -int ntfs_ntlookup(struct ntfsmount *, ino_t, struct ntnode **); -int ntfs_ntget(struct ntnode *); -void ntfs_ntref(struct ntnode *); -void ntfs_ntrele(struct ntnode *); -void ntfs_ntput(struct ntnode *); -int ntfs_loadntnode( struct ntfsmount *, struct ntnode * ); -int ntfs_writentvattr_plain(struct ntfsmount *, struct ntnode *, struct ntvattr *, off_t, size_t, void *, size_t *, struct uio *); -int ntfs_writeattr_plain(struct ntfsmount *, struct ntnode *, u_int32_t, char *, off_t, size_t, void *, size_t *, struct uio *); -void ntfs_toupper_init(void); -void ntfs_toupper_destroy(void); -int ntfs_toupper_use(struct mount *, struct ntfsmount *); -void ntfs_toupper_unuse(void); -int ntfs_fget(struct ntfsmount *, struct ntnode *, int, char *, struct fnode **); -void ntfs_frele(struct fnode *); - -int ntfs_u28_init(struct ntfsmount *ntmp, wchar *u2w, char *cs_local, char *cs_ntfs); -int ntfs_u28_uninit(struct ntfsmount *ntmp); -int ntfs_82u_init(struct ntfsmount *ntmp, char *cs_local, char *cs_ntfs); -int ntfs_82u_uninit(struct ntfsmount *ntmp); -char * ntfs_u28(char *outbuf, struct ntfsmount *ntmp, wchar wc); -wchar ntfs_82u(struct ntfsmount *ntmp, const char *c, int *len); -#define NTFS_U28(ch) ntfs_u28(tmpbuf, ntmp, (ch)) -#define NTFS_82U(ch, len) ntfs_82u(ntmp, (ch), len) -#define NTFS_UASTRCMP(ustr, ustrlen, astr, astrlen) \ - ntfs_uastrcmp(ntmp, (ustr), (ustrlen), (astr), (astrlen)) -#define NTFS_UASTRICMP(ustr, ustrlen, astr, astrlen) \ - ntfs_uastricmp(ntmp, (ustr), (ustrlen), (astr), (astrlen)) diff --git a/sys/fs/ntfs/ntfs_vfsops.c b/sys/fs/ntfs/ntfs_vfsops.c deleted file mode 100644 index 914863711f1..00000000000 --- a/sys/fs/ntfs/ntfs_vfsops.c +++ /dev/null @@ -1,811 +0,0 @@ -/* $NetBSD: ntfs_vfsops.c,v 1.23 1999/11/15 19:38:14 jdolecek Exp $ */ - -/*- - * Copyright (c) 1998, 1999 Semen Ustimenko - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - */ - - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include -#include -#include -#include -#include - -/*#define NTFS_DEBUG 1*/ -#include -#include -#include -#include -#include -#include - -static MALLOC_DEFINE(M_NTFSMNT, "ntfs_mount", "NTFS mount structure"); -MALLOC_DEFINE(M_NTFSNTNODE,"ntfs_ntnode", "NTFS ntnode information"); -MALLOC_DEFINE(M_NTFSFNODE,"ntfs_fnode", "NTFS fnode information"); -MALLOC_DEFINE(M_NTFSDIR,"ntfs_dir", "NTFS dir buffer"); - -static int ntfs_mountfs(register struct vnode *, struct mount *, - struct thread *); -static int ntfs_calccfree(struct ntfsmount *ntmp, cn_t *cfreep); - -static vfs_init_t ntfs_init; -static vfs_uninit_t ntfs_uninit; -static vfs_vget_t ntfs_vget; -static vfs_fhtovp_t ntfs_fhtovp; -static vfs_cmount_t ntfs_cmount; -static vfs_mount_t ntfs_mount; -static vfs_root_t ntfs_root; -static vfs_statfs_t ntfs_statfs; -static vfs_unmount_t ntfs_unmount; - -static b_strategy_t ntfs_bufstrategy; - -/* - * Buffer operations for NTFS vnodes. - * We punt on VOP_BMAP, so we need to do - * strategy on the file's vnode rather - * than the underlying device's - */ -static struct buf_ops ntfs_vnbufops = { - .bop_name = "NTFS", - .bop_strategy = ntfs_bufstrategy, -}; - -static int -ntfs_init ( - struct vfsconf *vcp ) -{ - ntfs_nthashinit(); - ntfs_toupper_init(); - return 0; -} - -static int -ntfs_uninit ( - struct vfsconf *vcp ) -{ - ntfs_toupper_destroy(); - ntfs_nthashdestroy(); - return 0; -} - -static int -ntfs_cmount ( - struct mntarg *ma, - void *data, - uint64_t flags) -{ - struct ntfs_args args; - struct export_args exp; - int error; - - error = copyin(data, &args, sizeof(args)); - if (error) - return (error); - vfs_oexport_conv(&args.export, &exp); - ma = mount_argsu(ma, "from", args.fspec, MAXPATHLEN); - ma = mount_arg(ma, "export", &exp, sizeof(exp)); - ma = mount_argf(ma, "uid", "%d", args.uid); - ma = mount_argf(ma, "gid", "%d", args.gid); - ma = mount_argf(ma, "mode", "%d", args.mode); - ma = mount_argb(ma, args.flag & NTFS_MFLAG_CASEINS, "nocaseins"); - ma = mount_argb(ma, args.flag & NTFS_MFLAG_ALLNAMES, "noallnames"); - if (args.flag & NTFS_MFLAG_KICONV) { - ma = mount_argsu(ma, "cs_ntfs", args.cs_ntfs, 64); - ma = mount_argsu(ma, "cs_local", args.cs_local, 64); - } - - error = kernel_mount(ma, flags); - - return (error); -} - -static const char *ntfs_opts[] = { - "from", "export", "uid", "gid", "mode", "caseins", "allnames", - "kiconv", "cs_ntfs", "cs_local", NULL -}; - -static int -ntfs_mount(struct mount *mp) -{ - int err = 0, error; - accmode_t accmode; - struct vnode *devvp; - struct nameidata ndp; - struct thread *td; - char *from; - - td = curthread; - if (vfs_filteropt(mp->mnt_optnew, ntfs_opts)) - return (EINVAL); - - from = vfs_getopts(mp->mnt_optnew, "from", &error); - if (error) - return (error); - - /* - * If updating, check whether changing from read-only to - * read/write. - */ - if (mp->mnt_flag & MNT_UPDATE) { - if (vfs_flagopt(mp->mnt_optnew, "export", NULL, 0)) { - /* Process export requests in vfs_mount.c */ - goto success; - } else { - printf("ntfs_mount(): MNT_UPDATE not supported\n"); - err = EINVAL; - goto error_1; - } - } - - /* - * Not an update, or updating the name: look up the name - * and verify that it refers to a sensible block device. - */ - NDINIT(&ndp, LOOKUP, FOLLOW | LOCKLEAF, UIO_SYSSPACE, from, td); - err = namei(&ndp); - if (err) { - /* can't get devvp!*/ - goto error_1; - } - NDFREE(&ndp, NDF_ONLY_PNBUF); - devvp = ndp.ni_vp; - - if (!vn_isdisk(devvp, &err)) { - vput(devvp); - return (err); - } - - /* - * If mount by non-root, then verify that user has necessary - * permissions on the device. - */ - accmode = VREAD; - if ((mp->mnt_flag & MNT_RDONLY) == 0) - accmode |= VWRITE; - err = VOP_ACCESS(devvp, accmode, td->td_ucred, td); - if (err) - err = priv_check(td, PRIV_VFS_MOUNT_PERM); - if (err) { - vput(devvp); - return (err); - } - - if (mp->mnt_flag & MNT_UPDATE) { -#if 0 - /* - ******************** - * UPDATE - ******************** - */ - - if (devvp != ntmp->um_devvp) - err = EINVAL; /* needs translation */ - vput(devvp); - if (err) - return (err); -#endif - } else { - /* - ******************** - * NEW MOUNT - ******************** - */ - - /* - * Since this is a new mount, we want the names for - * the device and the mount point copied in. If an - * error occurs, the mountpoint is discarded by the - * upper level code. Note that vfs_mount() handles - * copying the mountpoint f_mntonname for us, so we - * don't have to do it here unless we want to set it - * to something other than "path" for some rason. - */ - /* Save "mounted from" info for mount point (NULL pad)*/ - vfs_mountedfrom(mp, from); - - err = ntfs_mountfs(devvp, mp, td); - } - if (err) { - vrele(devvp); - return (err); - } - - goto success; - -error_1: /* no state to back out*/ - /* XXX: missing NDFREE(&ndp, ...) */ - -success: - return (err); -} - -/* - * Common code for mount and mountroot - */ -int -ntfs_mountfs(devvp, mp, td) - register struct vnode *devvp; - struct mount *mp; - struct thread *td; -{ - struct buf *bp; - struct ntfsmount *ntmp; - struct cdev *dev = devvp->v_rdev; - int error, ronly, i, v; - struct vnode *vp; - struct g_consumer *cp; - struct g_provider *pp; - char *cs_ntfs, *cs_local; - - ronly = (mp->mnt_flag & MNT_RDONLY) != 0; - DROP_GIANT(); - g_topology_lock(); - - /* - * XXX: Do not allow more than one consumer to open a device - * associated with a particular GEOM provider. - * This disables multiple read-only mounts of a device, - * but it gets rid of panics in vget() when you try to - * mount the same device more than once. - */ - pp = g_dev_getprovider(devvp->v_rdev); - if ((pp != NULL) && ((pp->acr | pp->acw | pp->ace ) != 0)) - error = EPERM; - else - error = g_vfs_open(devvp, &cp, "ntfs", ronly ? 0 : 1); - - g_topology_unlock(); - PICKUP_GIANT(); - VOP_UNLOCK(devvp, 0); - if (error) - return (error); - - bp = NULL; - - error = bread(devvp, BBLOCK, BBSIZE, NOCRED, &bp); - if (error) - goto out; - ntmp = malloc( sizeof *ntmp, M_NTFSMNT, M_WAITOK | M_ZERO); - bcopy( bp->b_data, &ntmp->ntm_bootfile, sizeof(struct bootfile) ); - /* - * We must not cache the boot block if its size is not exactly - * one cluster in order to avoid confusing the buffer cache when - * the boot file is read later by ntfs_readntvattr_plain(), which - * reads a cluster at a time. - */ - if (ntfs_cntob(1) != BBSIZE) - bp->b_flags |= B_NOCACHE; - brelse( bp ); - bp = NULL; - - if (strncmp((const char *)ntmp->ntm_bootfile.bf_sysid, NTFS_BBID, NTFS_BBIDLEN)) { - error = EINVAL; - dprintf(("ntfs_mountfs: invalid boot block\n")); - goto out; - } - - { - int8_t cpr = ntmp->ntm_mftrecsz; - if( cpr > 0 ) - ntmp->ntm_bpmftrec = ntmp->ntm_spc * cpr; - else - ntmp->ntm_bpmftrec = (1 << (-cpr)) / ntmp->ntm_bps; - } - ntmp->ntm_multiplier = ntmp->ntm_bps / DEV_BSIZE; - - dprintf(("ntfs_mountfs(): bps: %d, spc: %d, media: %x, mftrecsz: %d (%d sects)\n", - ntmp->ntm_bps,ntmp->ntm_spc,ntmp->ntm_bootfile.bf_media, - ntmp->ntm_mftrecsz,ntmp->ntm_bpmftrec)); - dprintf(("ntfs_mountfs(): mftcn: 0x%x|0x%x\n", - (u_int32_t)ntmp->ntm_mftcn,(u_int32_t)ntmp->ntm_mftmirrcn)); - - ntmp->ntm_mountp = mp; - ntmp->ntm_devvp = devvp; - if (vfs_scanopt(mp->mnt_optnew, "uid", "%d", &v) == 1) - ntmp->ntm_uid = v; - if (vfs_scanopt(mp->mnt_optnew, "gid", "%d", &v) == 1) - ntmp->ntm_gid = v; - if (vfs_scanopt(mp->mnt_optnew, "mode", "%d", &v) == 1) - ntmp->ntm_mode = v & ACCESSPERMS; - vfs_flagopt(mp->mnt_optnew, - "caseins", &ntmp->ntm_flag, NTFS_MFLAG_CASEINS); - vfs_flagopt(mp->mnt_optnew, - "allnames", &ntmp->ntm_flag, NTFS_MFLAG_ALLNAMES); - ntmp->ntm_cp = cp; - ntmp->ntm_bo = &devvp->v_bufobj; - - cs_local = vfs_getopts(mp->mnt_optnew, "cs_local", &error); - if (error && error != ENOENT) - goto out; - cs_ntfs = vfs_getopts(mp->mnt_optnew, "cs_ntfs", &error); - if (error && error != ENOENT) - goto out; - /* Copy in the 8-bit to Unicode conversion table */ - /* Initialize Unicode to 8-bit table from 8toU table */ - ntfs_82u_init(ntmp, cs_local, cs_ntfs); - if (cs_local != NULL && cs_ntfs != NULL) - ntfs_u28_init(ntmp, NULL, cs_local, cs_ntfs); - else - ntfs_u28_init(ntmp, ntmp->ntm_82u, cs_local, cs_ntfs); - - mp->mnt_data = ntmp; - - dprintf(("ntfs_mountfs(): case-%s,%s uid: %d, gid: %d, mode: %o\n", - (ntmp->ntm_flag & NTFS_MFLAG_CASEINS)?"insens.":"sens.", - (ntmp->ntm_flag & NTFS_MFLAG_ALLNAMES)?" allnames,":"", - ntmp->ntm_uid, ntmp->ntm_gid, ntmp->ntm_mode)); - - /* - * We read in some system nodes to do not allow - * reclaim them and to have everytime access to them. - */ - { - int pi[3] = { NTFS_MFTINO, NTFS_ROOTINO, NTFS_BITMAPINO }; - for (i=0; i<3; i++) { - error = VFS_VGET(mp, pi[i], LK_EXCLUSIVE, - &(ntmp->ntm_sysvn[pi[i]])); - if(error) - goto out1; - ntmp->ntm_sysvn[pi[i]]->v_vflag |= VV_SYSTEM; - VREF(ntmp->ntm_sysvn[pi[i]]); - vput(ntmp->ntm_sysvn[pi[i]]); - } - } - - /* read the Unicode lowercase --> uppercase translation table, - * if necessary */ - if ((error = ntfs_toupper_use(mp, ntmp))) - goto out1; - - /* - * Scan $BitMap and count free clusters - */ - error = ntfs_calccfree(ntmp, &ntmp->ntm_cfree); - if(error) - goto out1; - - /* - * Read and translate to internal format attribute - * definition file. - */ - { - int num,j; - struct attrdef ad; - - /* Open $AttrDef */ - error = VFS_VGET(mp, NTFS_ATTRDEFINO, LK_EXCLUSIVE, &vp ); - if(error) - goto out1; - - /* Count valid entries */ - for(num=0;;num++) { - error = ntfs_readattr(ntmp, VTONT(vp), - NTFS_A_DATA, NULL, - num * sizeof(ad), sizeof(ad), - &ad, NULL); - if (error) - goto out1; - if (ad.ad_name[0] == 0) - break; - } - - /* Alloc memory for attribute definitions */ - ntmp->ntm_ad = malloc(num * sizeof(struct ntvattrdef), - M_NTFSMNT, M_WAITOK); - - ntmp->ntm_adnum = num; - - /* Read them and translate */ - for(i=0;intm_ad[i].ad_name[j] = ad.ad_name[j]; - } while(ad.ad_name[j++]); - ntmp->ntm_ad[i].ad_namelen = j - 1; - ntmp->ntm_ad[i].ad_type = ad.ad_type; - } - - vput(vp); - } - - mp->mnt_stat.f_fsid.val[0] = dev2udev(dev); - mp->mnt_stat.f_fsid.val[1] = mp->mnt_vfc->vfc_typenum; - mp->mnt_maxsymlinklen = 0; - MNT_ILOCK(mp); - mp->mnt_flag |= MNT_LOCAL; - MNT_IUNLOCK(mp); - return (0); - -out1: - for(i=0;intm_sysvn[i]) vrele(ntmp->ntm_sysvn[i]); - - if (vflush(mp, 0, 0, td)) - dprintf(("ntfs_mountfs: vflush failed\n")); - -out: - if (bp) - brelse(bp); - - DROP_GIANT(); - g_topology_lock(); - g_vfs_close(cp); - g_topology_unlock(); - PICKUP_GIANT(); - - return (error); -} - -static int -ntfs_unmount( - struct mount *mp, - int mntflags) -{ - struct thread *td; - struct ntfsmount *ntmp; - int error, flags, i; - - dprintf(("ntfs_unmount: unmounting...\n")); - td = curthread; - ntmp = VFSTONTFS(mp); - - flags = 0; - if(mntflags & MNT_FORCE) - flags |= FORCECLOSE; - - dprintf(("ntfs_unmount: vflushing...\n")); - error = vflush(mp, 0, flags | SKIPSYSTEM, td); - if (error) { - printf("ntfs_unmount: vflush failed: %d\n",error); - return (error); - } - - /* Check if only system vnodes are rest */ - for(i=0;intm_sysvn[i]) && - (vrefcnt(ntmp->ntm_sysvn[i]) > 1)) return (EBUSY); - - /* Dereference all system vnodes */ - for(i=0;intm_sysvn[i]) vrele(ntmp->ntm_sysvn[i]); - - /* vflush system vnodes */ - error = vflush(mp, 0, flags, td); - if (error) - printf("ntfs_unmount: vflush failed(sysnodes): %d\n",error); - - vinvalbuf(ntmp->ntm_devvp, V_SAVE, 0, 0); - - DROP_GIANT(); - g_topology_lock(); - g_vfs_close(ntmp->ntm_cp); - g_topology_unlock(); - PICKUP_GIANT(); - - vrele(ntmp->ntm_devvp); - - /* free the toupper table, if this has been last mounted ntfs volume */ - ntfs_toupper_unuse(); - - dprintf(("ntfs_umount: freeing memory...\n")); - ntfs_u28_uninit(ntmp); - ntfs_82u_uninit(ntmp); - mp->mnt_data = NULL; - MNT_ILOCK(mp); - mp->mnt_flag &= ~MNT_LOCAL; - MNT_IUNLOCK(mp); - free(ntmp->ntm_ad, M_NTFSMNT); - free(ntmp, M_NTFSMNT); - return (error); -} - -static int -ntfs_root( - struct mount *mp, - int flags, - struct vnode **vpp) -{ - struct vnode *nvp; - int error = 0; - - dprintf(("ntfs_root(): sysvn: %p\n", - VFSTONTFS(mp)->ntm_sysvn[NTFS_ROOTINO])); - error = VFS_VGET(mp, (ino_t)NTFS_ROOTINO, LK_EXCLUSIVE, &nvp); - if(error) { - printf("ntfs_root: VFS_VGET failed: %d\n",error); - return (error); - } - - *vpp = nvp; - return (0); -} - -static int -ntfs_calccfree( - struct ntfsmount *ntmp, - cn_t *cfreep) -{ - struct vnode *vp; - u_int8_t *tmp; - int j, error; - long cfree = 0; - size_t bmsize, i; - - vp = ntmp->ntm_sysvn[NTFS_BITMAPINO]; - - bmsize = VTOF(vp)->f_size; - - tmp = malloc(bmsize, M_TEMP, M_WAITOK); - - error = ntfs_readattr(ntmp, VTONT(vp), NTFS_A_DATA, NULL, - 0, bmsize, tmp, NULL); - if (error) - goto out; - - for(i=0;intm_sysvn[NTFS_MFTINO])->f_size; - mftallocated = VTOF(ntmp->ntm_sysvn[NTFS_MFTINO])->f_allocated; - - sbp->f_type = mp->mnt_vfc->vfc_typenum; - sbp->f_bsize = ntmp->ntm_bps; - sbp->f_iosize = ntmp->ntm_bps * ntmp->ntm_spc; - sbp->f_blocks = ntmp->ntm_bootfile.bf_spv; - sbp->f_bfree = sbp->f_bavail = ntfs_cntobn(ntmp->ntm_cfree); - sbp->f_ffree = sbp->f_bfree / ntmp->ntm_bpmftrec; - sbp->f_files = mftallocated / ntfs_bntob(ntmp->ntm_bpmftrec) + - sbp->f_ffree; - sbp->f_flags = mp->mnt_flag; - - return (0); -} - -/*ARGSUSED*/ -static int -ntfs_fhtovp( - struct mount *mp, - struct fid *fhp, - int flags, - struct vnode **vpp) -{ - struct vnode *nvp; - struct ntfid *ntfhp = (struct ntfid *)fhp; - int error; - - ddprintf(("ntfs_fhtovp(): %d\n", ntfhp->ntfid_ino)); - - if ((error = VFS_VGET(mp, ntfhp->ntfid_ino, LK_EXCLUSIVE, &nvp)) != 0) { - *vpp = NULLVP; - return (error); - } - /* XXX as unlink/rmdir/mkdir/creat are not currently possible - * with NTFS, we don't need to check anything else for now */ - *vpp = nvp; - vnode_create_vobject(nvp, VTOF(nvp)->f_size, curthread); - return (0); -} - -int -ntfs_vgetex( - struct mount *mp, - ino_t ino, - u_int32_t attrtype, - char *attrname, - u_long lkflags, - u_long flags, - struct thread *td, - struct vnode **vpp) -{ - int error; - register struct ntfsmount *ntmp; - struct ntnode *ip; - struct fnode *fp; - struct vnode *vp; - enum vtype f_type; - - dprintf(("ntfs_vgetex: ino: %d, attr: 0x%x:%s, lkf: 0x%lx, f: 0x%lx\n", - ino, attrtype, attrname?attrname:"", (u_long)lkflags, - (u_long)flags)); - - ntmp = VFSTONTFS(mp); - *vpp = NULL; - - /* Get ntnode */ - error = ntfs_ntlookup(ntmp, ino, &ip); - if (error) { - printf("ntfs_vget: ntfs_ntget failed\n"); - return (error); - } - - /* It may be not initialized fully, so force load it */ - if (!(flags & VG_DONTLOADIN) && !(ip->i_flag & IN_LOADED)) { - error = ntfs_loadntnode(ntmp, ip); - if(error) { - printf("ntfs_vget: CAN'T LOAD ATTRIBUTES FOR INO: %d\n", - ip->i_number); - ntfs_ntput(ip); - return (error); - } - } - - error = ntfs_fget(ntmp, ip, attrtype, attrname, &fp); - if (error) { - printf("ntfs_vget: ntfs_fget failed\n"); - ntfs_ntput(ip); - return (error); - } - - f_type = VNON; - if (!(flags & VG_DONTVALIDFN) && !(fp->f_flag & FN_VALID)) { - if ((ip->i_frflag & NTFS_FRFLAG_DIR) && - (fp->f_attrtype == NTFS_A_DATA && fp->f_attrname == NULL)) { - f_type = VDIR; - } else if (flags & VG_EXT) { - f_type = VNON; - fp->f_size = fp->f_allocated = 0; - } else { - f_type = VREG; - - error = ntfs_filesize(ntmp, fp, - &fp->f_size, &fp->f_allocated); - if (error) { - ntfs_ntput(ip); - return (error); - } - } - - fp->f_flag |= FN_VALID; - } - - if (FTOV(fp)) { - vget(FTOV(fp), lkflags, td); - *vpp = FTOV(fp); - ntfs_ntput(ip); - return (0); - } - - error = getnewvnode("ntfs", ntmp->ntm_mountp, &ntfs_vnodeops, &vp); - if(error) { - ntfs_frele(fp); - ntfs_ntput(ip); - return (error); - } - /* XXX: Too early for mpsafe fs, lacks vnode lock */ - error = insmntque(vp, ntmp->ntm_mountp); - if (error) { - ntfs_frele(fp); - ntfs_ntput(ip); - return (error); - } - dprintf(("ntfs_vget: vnode: %p for ntnode: %d\n", vp,ino)); - - fp->f_vp = vp; - vp->v_data = fp; - vp->v_type = f_type; - - vp->v_bufobj.bo_ops = &ntfs_vnbufops; - vp->v_bufobj.bo_private = vp; - - if (ino == NTFS_ROOTINO) - vp->v_vflag |= VV_ROOT; - - ntfs_ntput(ip); - - if (lkflags & LK_TYPE_MASK) { - error = vn_lock(vp, lkflags); - if (error) { - vput(vp); - return (error); - } - } - - *vpp = vp; - return (0); - -} - -static int -ntfs_vget( - struct mount *mp, - ino_t ino, - int lkflags, - struct vnode **vpp) -{ - return ntfs_vgetex(mp, ino, NTFS_A_DATA, NULL, lkflags, 0, - curthread, vpp); -} - -static void -ntfs_bufstrategy(struct bufobj *bo, struct buf *bp) -{ - struct vnode *vp; - int rc; - - vp = bo->bo_private; - KASSERT(bo == &vp->v_bufobj, ("BO/VP mismatch: vp %p bo %p != %p", - vp, &vp->v_bufobj, bo)); - rc = VOP_STRATEGY(vp, bp); - KASSERT(rc == 0, ("NTFS VOP_STRATEGY failed: bp=%p, " - "vp=%p, rc=%d", bp, vp, rc)); -} - -static struct vfsops ntfs_vfsops = { - .vfs_fhtovp = ntfs_fhtovp, - .vfs_init = ntfs_init, - .vfs_cmount = ntfs_cmount, - .vfs_mount = ntfs_mount, - .vfs_root = ntfs_root, - .vfs_statfs = ntfs_statfs, - .vfs_uninit = ntfs_uninit, - .vfs_unmount = ntfs_unmount, - .vfs_vget = ntfs_vget, -}; -VFS_SET(ntfs_vfsops, ntfs, 0); -MODULE_VERSION(ntfs, 1); diff --git a/sys/fs/ntfs/ntfs_vfsops.h b/sys/fs/ntfs/ntfs_vfsops.h deleted file mode 100644 index 26efad93324..00000000000 --- a/sys/fs/ntfs/ntfs_vfsops.h +++ /dev/null @@ -1,42 +0,0 @@ -/* $NetBSD: ntfs_vfsops.h,v 1.4 1999/10/10 14:20:33 jdolecek Exp $ */ - -/*- - * Copyright (c) 1998, 1999 Semen Ustimenko (semenu@FreeBSD.org) - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - */ -#define VG_DONTLOADIN 0x0001 /* Tells ntfs_vgetex to do not call */ - /* ntfs_loadntnode() on ntnode, even if */ - /* ntnode not loaded */ -#define VG_DONTVALIDFN 0x0002 /* Tells ntfs_vgetex to do not validate */ - /* fnode */ -#define VG_EXT 0x0004 /* This is not main record */ - -struct mount; -struct ntfsmount; -struct thread; -struct vnode; - -int ntfs_vgetex(struct mount *, ino_t, u_int32_t, char *, u_long, u_long, - struct thread *, struct vnode **); diff --git a/sys/fs/ntfs/ntfs_vnops.c b/sys/fs/ntfs/ntfs_vnops.c deleted file mode 100644 index 3619a277c17..00000000000 --- a/sys/fs/ntfs/ntfs_vnops.c +++ /dev/null @@ -1,760 +0,0 @@ -/* $NetBSD: ntfs_vnops.c,v 1.23 1999/10/31 19:45:27 jdolecek Exp $ */ - -/*- - * Copyright (c) 1992, 1993 - * The Regents of the University of California. All rights reserved. - * - * This code is derived from software contributed to Berkeley by - * John Heidemann of the UCLA Ficus project. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 4. Neither the name of the University nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include - -#include - -/*#define NTFS_DEBUG 1*/ -#include -#include -#include - -#include /* for pathconf(2) constants */ - -static vop_read_t ntfs_read; -static vop_write_t ntfs_write; -static vop_getattr_t ntfs_getattr; -static vop_inactive_t ntfs_inactive; -static vop_reclaim_t ntfs_reclaim; -static vop_bmap_t ntfs_bmap; -static vop_strategy_t ntfs_strategy; -static vop_access_t ntfs_access; -static vop_open_t ntfs_open; -static vop_close_t ntfs_close; -static vop_readdir_t ntfs_readdir; -static vop_cachedlookup_t ntfs_lookup; -static vop_fsync_t ntfs_fsync; -static vop_pathconf_t ntfs_pathconf; -static vop_vptofh_t ntfs_vptofh; - -/* - * This is a noop, simply returning what one has been given. - */ -int -ntfs_bmap(ap) - struct vop_bmap_args /* { - struct vnode *a_vp; - daddr_t a_bn; - struct bufobj **a_bop; - daddr_t *a_bnp; - int *a_runp; - int *a_runb; - } */ *ap; -{ - struct vnode *vp = ap->a_vp; - - dprintf(("ntfs_bmap: vn: %p, blk: %d\n", ap->a_vp,(u_int32_t)ap->a_bn)); - if (ap->a_bop != NULL) - *ap->a_bop = &vp->v_bufobj; - if (ap->a_bnp != NULL) - *ap->a_bnp = ap->a_bn; - if (ap->a_runp != NULL) - *ap->a_runp = 0; - if (ap->a_runb != NULL) - *ap->a_runb = 0; - return (0); -} - -static int -ntfs_read(ap) - struct vop_read_args /* { - struct vnode *a_vp; - struct uio *a_uio; - int a_ioflag; - struct ucred *a_cred; - } */ *ap; -{ - register struct vnode *vp = ap->a_vp; - register struct fnode *fp = VTOF(vp); - register struct ntnode *ip = FTONT(fp); - struct uio *uio = ap->a_uio; - struct ntfsmount *ntmp = ip->i_mp; - struct buf *bp; - daddr_t cn; - int resid, off, toread; - int error; - - dprintf(("ntfs_read: ino: %d, off: %d resid: %d, segflg: %d\n",ip->i_number,(u_int32_t)uio->uio_offset,uio->uio_resid,uio->uio_segflg)); - - dprintf(("ntfs_read: filesize: %d",(u_int32_t)fp->f_size)); - - /* don't allow reading after end of file */ - if (uio->uio_offset > fp->f_size) - return (0); - - resid = MIN(uio->uio_resid, fp->f_size - uio->uio_offset); - - dprintf((", resid: %d\n", resid)); - - error = 0; - while (resid) { - cn = ntfs_btocn(uio->uio_offset); - off = ntfs_btocnoff(uio->uio_offset); - - toread = MIN(off + resid, ntfs_cntob(1)); - - error = bread(vp, cn, ntfs_cntob(1), NOCRED, &bp); - if (error) { - brelse(bp); - break; - } - - error = uiomove(bp->b_data + off, toread - off, uio); - if(error) { - brelse(bp); - break; - } - brelse(bp); - - resid -= toread - off; - } - - return (error); -} - -static int -ntfs_getattr(ap) - struct vop_getattr_args /* { - struct vnode *a_vp; - struct vattr *a_vap; - struct ucred *a_cred; - struct thread *a_td; - } */ *ap; -{ - register struct vnode *vp = ap->a_vp; - register struct fnode *fp = VTOF(vp); - register struct ntnode *ip = FTONT(fp); - register struct vattr *vap = ap->a_vap; - - dprintf(("ntfs_getattr: %d, flags: %d\n",ip->i_number,ip->i_flag)); - - vap->va_fsid = dev2udev(ip->i_dev); - vap->va_fileid = ip->i_number; - vap->va_mode = ip->i_mp->ntm_mode; - vap->va_nlink = (ip->i_nlink || ip->i_flag & IN_LOADED ? ip->i_nlink : 1); - vap->va_uid = ip->i_mp->ntm_uid; - vap->va_gid = ip->i_mp->ntm_gid; - vap->va_rdev = NODEV; - vap->va_size = fp->f_size; - vap->va_bytes = fp->f_allocated; - vap->va_atime = ntfs_nttimetounix(fp->f_times.t_access); - vap->va_mtime = ntfs_nttimetounix(fp->f_times.t_write); - vap->va_ctime = ntfs_nttimetounix(fp->f_times.t_create); - vap->va_flags = ip->i_flag; - vap->va_gen = 0; - vap->va_blocksize = ip->i_mp->ntm_spc * ip->i_mp->ntm_bps; - vap->va_type = vp->v_type; - vap->va_filerev = 0; - return (0); -} - -/* - * Last reference to an ntnode. If necessary, write or delete it. - */ -int -ntfs_inactive(ap) - struct vop_inactive_args /* { - struct vnode *a_vp; - } */ *ap; -{ -#ifdef NTFS_DEBUG - register struct ntnode *ip = VTONT(ap->a_vp); -#endif - - dprintf(("ntfs_inactive: vnode: %p, ntnode: %d\n", ap->a_vp, - ip->i_number)); - - /* XXX since we don't support any filesystem changes - * right now, nothing more needs to be done - */ - return (0); -} - -/* - * Reclaim an fnode/ntnode so that it can be used for other purposes. - */ -int -ntfs_reclaim(ap) - struct vop_reclaim_args /* { - struct vnode *a_vp; - } */ *ap; -{ - register struct vnode *vp = ap->a_vp; - register struct fnode *fp = VTOF(vp); - register struct ntnode *ip = FTONT(fp); - int error; - - dprintf(("ntfs_reclaim: vnode: %p, ntnode: %d\n", vp, ip->i_number)); - - /* - * Destroy the vm object and flush associated pages. - */ - vnode_destroy_vobject(vp); - - if ((error = ntfs_ntget(ip)) != 0) - return (error); - - /* Purge old data structures associated with the inode. */ - ntfs_frele(fp); - ntfs_ntput(ip); - vp->v_data = NULL; - - return (0); -} - -/* - * Calculate the logical to physical mapping if not done already, - * then call the device strategy routine. - */ -int -ntfs_strategy(ap) - struct vop_strategy_args /* { - struct buf *a_bp; - } */ *ap; -{ - register struct buf *bp = ap->a_bp; - register struct vnode *vp = ap->a_vp; - register struct fnode *fp = VTOF(vp); - register struct ntnode *ip = FTONT(fp); - struct ntfsmount *ntmp = ip->i_mp; - int error; - - dprintf(("ntfs_strategy: offset: %d, blkno: %d, lblkno: %d\n", - (u_int32_t)bp->b_offset,(u_int32_t)bp->b_blkno, - (u_int32_t)bp->b_lblkno)); - - dprintf(("strategy: bcount: %d flags: 0x%x\n", - (u_int32_t)bp->b_bcount,bp->b_flags)); - - if (bp->b_iocmd == BIO_READ) { - u_int32_t toread; - - if (ntfs_cntob(bp->b_blkno) >= fp->f_size) { - clrbuf(bp); - error = 0; - } else { - toread = MIN(bp->b_bcount, - fp->f_size-ntfs_cntob(bp->b_blkno)); - dprintf(("ntfs_strategy: toread: %d, fsize: %d\n", - toread,(u_int32_t)fp->f_size)); - - error = ntfs_readattr(ntmp, ip, fp->f_attrtype, - fp->f_attrname, ntfs_cntob(bp->b_blkno), - toread, bp->b_data, NULL); - - if (error) { - printf("ntfs_strategy: ntfs_readattr failed\n"); - bp->b_error = error; - bp->b_ioflags |= BIO_ERROR; - } - - bzero(bp->b_data + toread, bp->b_bcount - toread); - } - } else { - size_t tmp; - u_int32_t towrite; - - if (ntfs_cntob(bp->b_blkno) + bp->b_bcount >= fp->f_size) { - printf("ntfs_strategy: CAN'T EXTEND FILE\n"); - bp->b_error = error = EFBIG; - bp->b_ioflags |= BIO_ERROR; - } else { - towrite = MIN(bp->b_bcount, - fp->f_size-ntfs_cntob(bp->b_blkno)); - dprintf(("ntfs_strategy: towrite: %d, fsize: %d\n", - towrite,(u_int32_t)fp->f_size)); - - error = ntfs_writeattr_plain(ntmp, ip, fp->f_attrtype, - fp->f_attrname, ntfs_cntob(bp->b_blkno),towrite, - bp->b_data, &tmp, NULL); - - if (error) { - printf("ntfs_strategy: ntfs_writeattr fail\n"); - bp->b_error = error; - bp->b_ioflags |= BIO_ERROR; - } - } - } - bufdone(bp); - return (0); -} - -static int -ntfs_write(ap) - struct vop_write_args /* { - struct vnode *a_vp; - struct uio *a_uio; - int a_ioflag; - struct ucred *a_cred; - } */ *ap; -{ - register struct vnode *vp = ap->a_vp; - register struct fnode *fp = VTOF(vp); - register struct ntnode *ip = FTONT(fp); - struct uio *uio = ap->a_uio; - struct ntfsmount *ntmp = ip->i_mp; - u_int64_t towrite; - size_t written; - int error; - - dprintf(("ntfs_write: ino: %d, off: %d resid: %d, segflg: %d\n",ip->i_number,(u_int32_t)uio->uio_offset,uio->uio_resid,uio->uio_segflg)); - dprintf(("ntfs_write: filesize: %d",(u_int32_t)fp->f_size)); - - if (uio->uio_resid + uio->uio_offset > fp->f_size) { - printf("ntfs_write: CAN'T WRITE BEYOND END OF FILE\n"); - return (EFBIG); - } - - towrite = MIN(uio->uio_resid, fp->f_size - uio->uio_offset); - - dprintf((", towrite: %d\n",(u_int32_t)towrite)); - - error = ntfs_writeattr_plain(ntmp, ip, fp->f_attrtype, - fp->f_attrname, uio->uio_offset, towrite, NULL, &written, uio); -#ifdef NTFS_DEBUG - if (error) - printf("ntfs_write: ntfs_writeattr failed: %d\n", error); -#endif - - return (error); -} - -int -ntfs_access(ap) - struct vop_access_args /* { - struct vnode *a_vp; - accmode_t a_accmode; - struct ucred *a_cred; - struct thread *a_td; - } */ *ap; -{ - struct vnode *vp = ap->a_vp; - struct ntnode *ip = VTONT(vp); - accmode_t accmode = ap->a_accmode; - - dprintf(("ntfs_access: %d\n",ip->i_number)); - - /* - * Disallow write attempts on read-only filesystems; - * unless the file is a socket, fifo, or a block or - * character device resident on the filesystem. - */ - if (accmode & VWRITE) { - switch ((int)vp->v_type) { - case VDIR: - case VLNK: - case VREG: - if (vp->v_mount->mnt_flag & MNT_RDONLY) - return (EROFS); - break; - } - } - - return (vaccess(vp->v_type, ip->i_mp->ntm_mode, ip->i_mp->ntm_uid, - ip->i_mp->ntm_gid, ap->a_accmode, ap->a_cred, NULL)); -} - -/* - * Open called. - * - * Nothing to do. - */ -/* ARGSUSED */ -static int -ntfs_open(ap) - struct vop_open_args /* { - struct vnode *a_vp; - int a_mode; - struct ucred *a_cred; - struct thread *a_td; - } */ *ap; -{ -#ifdef NTFS_DEBUG - register struct vnode *vp = ap->a_vp; - register struct ntnode *ip = VTONT(vp); - - printf("ntfs_open: %d\n",ip->i_number); -#endif - - vnode_create_vobject(ap->a_vp, VTOF(ap->a_vp)->f_size, ap->a_td); - - /* - * Files marked append-only must be opened for appending. - */ - - return (0); -} - -/* - * Close called. - * - * Update the times on the inode. - */ -/* ARGSUSED */ -static int -ntfs_close(ap) - struct vop_close_args /* { - struct vnode *a_vp; - int a_fflag; - struct ucred *a_cred; - struct thread *a_td; - } */ *ap; -{ -#ifdef NTFS_DEBUG - register struct vnode *vp = ap->a_vp; - register struct ntnode *ip = VTONT(vp); - - printf("ntfs_close: %d\n",ip->i_number); -#endif - - return (0); -} - -int -ntfs_readdir(ap) - struct vop_readdir_args /* { - struct vnode *a_vp; - struct uio *a_uio; - struct ucred *a_cred; - int *a_ncookies; - u_int **cookies; - } */ *ap; -{ - register struct vnode *vp = ap->a_vp; - register struct fnode *fp = VTOF(vp); - register struct ntnode *ip = FTONT(fp); - struct uio *uio = ap->a_uio; - struct ntfsmount *ntmp = ip->i_mp; - int i, j, error = 0; - char *c, tmpbuf[5]; - u_int32_t faked = 0, num; - int ncookies = 0; - struct dirent cde; - off_t off; - - dprintf(("ntfs_readdir %d off: %d resid: %d\n",ip->i_number,(u_int32_t)uio->uio_offset,uio->uio_resid)); - - off = uio->uio_offset; - - /* Simulate . in every dir except ROOT */ - if( ip->i_number != NTFS_ROOTINO ) { - struct dirent dot = { NTFS_ROOTINO, - sizeof(struct dirent), DT_DIR, 1, "." }; - - if( uio->uio_offset < sizeof(struct dirent) ) { - dot.d_fileno = ip->i_number; - error = uiomove((char *)&dot,sizeof(struct dirent),uio); - if(error) - return (error); - - ncookies ++; - } - } - - /* Simulate .. in every dir including ROOT */ - if( uio->uio_offset < 2 * sizeof(struct dirent) ) { - struct dirent dotdot = { NTFS_ROOTINO, - sizeof(struct dirent), DT_DIR, 2, ".." }; - - error = uiomove((char *)&dotdot,sizeof(struct dirent),uio); - if(error) - return (error); - - ncookies ++; - } - - faked = (ip->i_number == NTFS_ROOTINO) ? 1 : 2; - num = uio->uio_offset / sizeof(struct dirent) - faked; - - while( uio->uio_resid >= sizeof(struct dirent) ) { - struct attr_indexentry *iep; - - error = ntfs_ntreaddir(ntmp, fp, num, &iep); - - if(error) - return (error); - - if( NULL == iep ) - break; - - for(; !(iep->ie_flag & NTFS_IEFLAG_LAST) && (uio->uio_resid >= sizeof(struct dirent)); - iep = NTFS_NEXTREC(iep, struct attr_indexentry *)) - { - if(!ntfs_isnamepermitted(ntmp,iep)) - continue; - - for(i=0, j=0; iie_fnamelen; i++) { - c = NTFS_U28(iep->ie_fname[i]); - while (*c != '\0') - cde.d_name[j++] = *c++; - } - cde.d_name[j] = '\0'; - dprintf(("ntfs_readdir: elem: %d, fname:[%s] type: %d, flag: %d, ", - num, cde.d_name, iep->ie_fnametype, - iep->ie_flag)); - cde.d_namlen = j; - cde.d_fileno = iep->ie_number; - cde.d_type = (iep->ie_fflag & NTFS_FFLAG_DIR) ? DT_DIR : DT_REG; - cde.d_reclen = sizeof(struct dirent); - dprintf(("%s\n", (cde.d_type == DT_DIR) ? "dir":"reg")); - - error = uiomove((char *)&cde, sizeof(struct dirent), uio); - if(error) - return (error); - - ncookies++; - num++; - } - } - - dprintf(("ntfs_readdir: %d entries (%d bytes) read\n", - ncookies,(u_int)(uio->uio_offset - off))); - dprintf(("ntfs_readdir: off: %d resid: %d\n", - (u_int32_t)uio->uio_offset,uio->uio_resid)); - - if (!error && ap->a_ncookies != NULL) { - struct dirent* dpStart; - struct dirent* dp; - u_long *cookies; - u_long *cookiep; - - ddprintf(("ntfs_readdir: %d cookies\n",ncookies)); - if (uio->uio_segflg != UIO_SYSSPACE || uio->uio_iovcnt != 1) - panic("ntfs_readdir: unexpected uio from NFS server"); - dpStart = (struct dirent *) - ((caddr_t)uio->uio_iov->iov_base - - (uio->uio_offset - off)); - cookies = malloc(ncookies * sizeof(u_long), - M_TEMP, M_WAITOK); - for (dp = dpStart, cookiep = cookies, i=0; - i < ncookies; - dp = (struct dirent *)((caddr_t) dp + dp->d_reclen), i++) { - off += dp->d_reclen; - *cookiep++ = (u_int) off; - } - *ap->a_ncookies = ncookies; - *ap->a_cookies = cookies; - } -/* - if (ap->a_eofflag) - *ap->a_eofflag = VTONT(ap->a_vp)->i_size <= uio->uio_offset; -*/ - return (error); -} - -int -ntfs_lookup(ap) - struct vop_cachedlookup_args /* { - struct vnode *a_dvp; - struct vnode **a_vpp; - struct componentname *a_cnp; - } */ *ap; -{ - register struct vnode *dvp = ap->a_dvp; - register struct ntnode *dip = VTONT(dvp); - struct ntfsmount *ntmp = dip->i_mp; - struct componentname *cnp = ap->a_cnp; - struct ucred *cred = cnp->cn_cred; - int error; - dprintf(("ntfs_lookup: \"%.*s\" (%ld bytes) in %d\n", - (int)cnp->cn_namelen, cnp->cn_nameptr, cnp->cn_namelen, - dip->i_number)); - - error = VOP_ACCESS(dvp, VEXEC, cred, cnp->cn_thread); - if(error) - return (error); - - if ((cnp->cn_flags & ISLASTCN) && - (dvp->v_mount->mnt_flag & MNT_RDONLY) && - (cnp->cn_nameiop == DELETE || cnp->cn_nameiop == RENAME)) - return (EROFS); - - if(cnp->cn_namelen == 1 && cnp->cn_nameptr[0] == '.') { - dprintf(("ntfs_lookup: faking . directory in %d\n", - dip->i_number)); - - VREF(dvp); - *ap->a_vpp = dvp; - error = 0; - } else if (cnp->cn_flags & ISDOTDOT) { - struct ntvattr *vap; - - dprintf(("ntfs_lookup: faking .. directory in %d\n", - dip->i_number)); - - error = ntfs_ntvattrget(ntmp, dip, NTFS_A_NAME, NULL, 0, &vap); - if(error) - return (error); - - VOP_UNLOCK(dvp,0); - dprintf(("ntfs_lookup: parentdir: %d\n", - vap->va_a_name->n_pnumber)); - error = VFS_VGET(ntmp->ntm_mountp, vap->va_a_name->n_pnumber, - LK_EXCLUSIVE, ap->a_vpp); - ntfs_ntvattrrele(vap); - if (error) { - vn_lock(dvp,LK_EXCLUSIVE|LK_RETRY); - return (error); - } - } else { - error = ntfs_ntlookupfile(ntmp, dvp, cnp, ap->a_vpp); - if (error) { - dprintf(("ntfs_ntlookupfile: returned %d\n", error)); - return (error); - } - - dprintf(("ntfs_lookup: found ino: %d\n", - VTONT(*ap->a_vpp)->i_number)); - } - - if (cnp->cn_flags & MAKEENTRY) - cache_enter(dvp, *ap->a_vpp, cnp); - - return (error); -} - -/* - * Flush the blocks of a file to disk. - * - * This function is worthless for vnodes that represent directories. Maybe we - * could just do a sync if they try an fsync on a directory file. - */ -static int -ntfs_fsync(ap) - struct vop_fsync_args /* { - struct vnode *a_vp; - struct ucred *a_cred; - int a_waitfor; - struct thread *a_td; - } */ *ap; -{ - return (0); -} - -/* - * Return POSIX pathconf information applicable to NTFS filesystem - */ -int -ntfs_pathconf(ap) - struct vop_pathconf_args *ap; -{ - - switch (ap->a_name) { - case _PC_LINK_MAX: - *ap->a_retval = 1; - return (0); - case _PC_NAME_MAX: - *ap->a_retval = NTFS_MAXFILENAME; - return (0); - case _PC_PATH_MAX: - *ap->a_retval = PATH_MAX; - return (0); - case _PC_CHOWN_RESTRICTED: - *ap->a_retval = 1; - return (0); - case _PC_NO_TRUNC: - *ap->a_retval = 0; - return (0); - default: - return (EINVAL); - } - /* NOTREACHED */ -} - -int -ntfs_vptofh(ap) - struct vop_vptofh_args /* { - struct vnode *a_vp; - struct fid *a_fhp; - } */ *ap; -{ - register struct ntnode *ntp; - register struct ntfid *ntfhp; - - ddprintf(("ntfs_fhtovp(): %p\n", ap->a_vp)); - - ntp = VTONT(ap->a_vp); - ntfhp = (struct ntfid *)ap->a_fhp; - ntfhp->ntfid_len = sizeof(struct ntfid); - ntfhp->ntfid_ino = ntp->i_number; - /* ntfhp->ntfid_gen = ntp->i_gen; */ - return (0); -} - -/* - * Global vfs data structures - */ -struct vop_vector ntfs_vnodeops = { - .vop_default = &default_vnodeops, - - .vop_access = ntfs_access, - .vop_bmap = ntfs_bmap, - .vop_cachedlookup = ntfs_lookup, - .vop_close = ntfs_close, - .vop_fsync = ntfs_fsync, - .vop_getattr = ntfs_getattr, - .vop_inactive = ntfs_inactive, - .vop_lookup = vfs_cache_lookup, - .vop_open = ntfs_open, - .vop_pathconf = ntfs_pathconf, - .vop_read = ntfs_read, - .vop_readdir = ntfs_readdir, - .vop_reclaim = ntfs_reclaim, - .vop_strategy = ntfs_strategy, - .vop_write = ntfs_write, - .vop_vptofh = ntfs_vptofh, -}; diff --git a/sys/fs/ntfs/ntfsmount.h b/sys/fs/ntfs/ntfsmount.h deleted file mode 100644 index 9fd2bbe7d26..00000000000 --- a/sys/fs/ntfs/ntfsmount.h +++ /dev/null @@ -1,43 +0,0 @@ -/* $NetBSD: ntfsmount.h,v 1.3 1999/07/26 14:02:32 jdolecek Exp $ */ - -/*- - * Copyright (c) 1998, 1999 Semen Ustimenko - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - */ - -#define NTFS_MFLAG_CASEINS 0x00000001 -#define NTFS_MFLAG_ALLNAMES 0x00000002 -#define NTFS_MFLAG_KICONV 0x00000004 - -struct ntfs_args { - char *fspec; /* block special device to mount */ - struct oexport_args export; /* network export information */ - uid_t uid; /* uid that owns ntfs files */ - gid_t gid; /* gid that owns ntfs files */ - mode_t mode; /* mask to be applied for ntfs perms */ - u_long flag; /* additional flags */ - char *cs_ntfs; /* NTFS Charset */ - char *cs_local; /* Local Charset */ -}; diff --git a/sys/fs/procfs/README b/sys/fs/procfs/README deleted file mode 100644 index a4f3ad0e878..00000000000 --- a/sys/fs/procfs/README +++ /dev/null @@ -1,113 +0,0 @@ -saute procfs lyonnais - -procfs supports two levels of directory. the filesystem root -directory contains a representation of the system process table. -this consists of an entry for each active and zombie process, and -an additional entry "curproc" which always represents the process -making the lookup request. - -each of the sub-directories contains several files. these files -are used to control and interrogate processes. the files implemented -are: - - file - xxx. the exec'ed file. - - status - r/o. returns process status. - - ctl - w/o. sends a control message to the process. - for example: - echo hup > /proc/curproc/note - will send a SIGHUP to the shell. - whereas - echo attach > /proc/1293/ctl - would set up process 1293 for debugging. - see below for more details. - - mem - r/w. virtual memory image of the process. - parts of the address space are readable - only if they exist in the target process. - a more reasonable alternative might be - to return zero pages instead of an error. - comments? - - note - w/o. writing a string here sends the - equivalent note to the process. - [ not implemented. ] - - notepg - w/o. the same as note, but sends to all - members of the process group. - [ not implemented. ] - - regs - r/w. process register set. this can be read - or written any time even if the process - is not stopped. since the bsd kernel - is single-processor, this implementation - will get the "right" register values. - a multi-proc kernel would need to do some - synchronisation. - -this then looks like: - -% ls -li /proc -total 0 - 9 dr-xr-xr-x 2 root wheel 0 Sep 21 15:06 0 - 17 dr-xr-xr-x 2 root wheel 0 Sep 21 15:06 1 - 89 dr-xr-xr-x 2 root wheel 0 Sep 21 15:06 10 - 25 dr-xr-xr-x 2 root wheel 0 Sep 21 15:06 2 -2065 dr-xr-xr-x 2 root wheel 0 Sep 21 15:06 257 -2481 dr-xr-xr-x 2 jsp staff 0 Sep 21 15:06 309 - 265 dr-xr-xr-x 2 root wheel 0 Sep 21 15:06 32 -3129 dr-xr-xr-x 2 jsp staff 0 Sep 21 15:06 390 -3209 dr-xr-xr-x 2 jsp staff 0 Sep 21 15:06 400 -3217 dr-xr-xr-x 2 jsp staff 0 Sep 21 15:06 401 -3273 dr-xr-xr-x 2 jsp staff 0 Sep 21 15:06 408 - 393 dr-xr-xr-x 2 root wheel 0 Sep 21 15:06 48 - 409 dr-xr-xr-x 2 root wheel 0 Sep 21 15:06 50 - 465 dr-xr-xr-x 2 root wheel 0 Sep 21 15:06 57 - 481 dr-xr-xr-x 2 root wheel 0 Sep 21 15:06 59 - 537 dr-xr-xr-x 2 root kmem 0 Sep 21 15:06 66 - 545 dr-xr-xr-x 2 root wheel 0 Sep 21 15:06 67 - 657 dr-xr-xr-x 2 jsp staff 0 Sep 21 15:06 81 - 665 dr-xr-xr-x 2 jsp staff 0 Sep 21 15:06 82 - 673 dr-xr-xr-x 2 jsp staff 0 Sep 21 15:06 83 - 681 dr-xr-xr-x 2 root wheel 0 Sep 21 15:06 84 -3273 dr-xr-xr-x 2 jsp staff 0 Sep 21 15:06 curproc -% ls -li /proc/curproc -total 408 -3341 --w------- 1 jsp staff 0 Sep 21 15:06 ctl -1554 -r-xr-xr-x 1 bin bin 90112 Mar 29 04:52 file -3339 -rw------- 1 jsp staff 118784 Sep 21 15:06 mem -3343 --w------- 1 jsp staff 0 Sep 21 15:06 note -3344 --w------- 1 jsp staff 0 Sep 21 15:06 notepg -3340 -rw------- 1 jsp staff 0 Sep 21 15:06 regs -3342 -r--r--r-- 1 jsp staff 0 Sep 21 15:06 status -% df /proc/curproc /proc/curproc/file -Filesystem 512-blocks Used Avail Capacity Mounted on -proc 2 2 0 100% /proc -/dev/wd0a 16186 13548 1018 93% / -% cat /proc/curproc/status -cat 446 439 400 81 12,0 ctty 748620684 270000 0 0 0 20000 nochan 11 20 20 20 0 21 117 - - - -the basic sequence of commands written to "ctl" would be - - attach - this stops the target process and - arranges for the sending process - to become the debug control process - wait - wait for the target process to come to - a steady state ready for debugging. - step - single step, with no signal delivery. - run - continue running, with no signal delivery, - until next trap or breakpoint. - - deliver signal and continue running. - detach - continue execution of the target process - and remove it from control by the debug process - -in a normal debugging environment, where the target is fork/exec'd by -the debugger, the debugger should fork and the child should stop itself -(with a self-inflicted SIGSTOP). the parent should do a "wait" then an -"attach". as before, the child will hit a breakpoint on the first -instruction in any newly exec'd image. - -$FreeBSD: stable/11/sys/fs/procfs/README 50477 1999-08-28 01:08:13Z peter $ diff --git a/sys/fs/procfs/procfs_ctl.c b/sys/fs/procfs/procfs_ctl.c deleted file mode 100644 index 729b01d448a..00000000000 --- a/sys/fs/procfs/procfs_ctl.c +++ /dev/null @@ -1,359 +0,0 @@ -/*- - * Copyright (c) 1993 Jan-Simon Pendry - * Copyright (c) 1993 - * The Regents of the University of California. All rights reserved. - * - * This code is derived from software contributed to Berkeley by - * Jan-Simon Pendry. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 4. Neither the name of the University nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @(#)procfs_ctl.c 8.4 (Berkeley) 6/15/94 - * - * From: - * $Id: procfs_ctl.c,v 1.51 2003/12/07 17:40:00 des Exp $ - * $FreeBSD: stable/11/sys/fs/procfs/procfs_ctl.c 285670 2015-07-18 09:02:50Z kib $ - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include - -/* - * True iff process (p) is in trace wait state - * relative to process (curp) - */ -#define TRACE_WAIT_P(curp, p) \ - (P_SHOULDSTOP(p) && \ - (p)->p_pptr == (curp) && \ - ((p)->p_flag & P_TRACED)) - -#define PROCFS_CTL_ATTACH 1 -#define PROCFS_CTL_DETACH 2 -#define PROCFS_CTL_STEP 3 -#define PROCFS_CTL_RUN 4 -#define PROCFS_CTL_WAIT 5 - -struct namemap { - const char *nm_name; - int nm_val; -}; - -static struct namemap ctlnames[] = { - /* special /proc commands */ - { "attach", PROCFS_CTL_ATTACH }, - { "detach", PROCFS_CTL_DETACH }, - { "step", PROCFS_CTL_STEP }, - { "run", PROCFS_CTL_RUN }, - { "wait", PROCFS_CTL_WAIT }, - { 0 }, -}; - -static struct namemap signames[] = { - /* regular signal names */ - { "hup", SIGHUP }, { "int", SIGINT }, - { "quit", SIGQUIT }, { "ill", SIGILL }, - { "trap", SIGTRAP }, { "abrt", SIGABRT }, - { "iot", SIGIOT }, { "emt", SIGEMT }, - { "fpe", SIGFPE }, { "kill", SIGKILL }, - { "bus", SIGBUS }, { "segv", SIGSEGV }, - { "sys", SIGSYS }, { "pipe", SIGPIPE }, - { "alrm", SIGALRM }, { "term", SIGTERM }, - { "urg", SIGURG }, { "stop", SIGSTOP }, - { "tstp", SIGTSTP }, { "cont", SIGCONT }, - { "chld", SIGCHLD }, { "ttin", SIGTTIN }, - { "ttou", SIGTTOU }, { "io", SIGIO }, - { "xcpu", SIGXCPU }, { "xfsz", SIGXFSZ }, - { "vtalrm", SIGVTALRM }, { "prof", SIGPROF }, - { "winch", SIGWINCH }, { "info", SIGINFO }, - { "usr1", SIGUSR1 }, { "usr2", SIGUSR2 }, - { 0 }, -}; - -static int procfs_control(struct thread *td, struct proc *p, int op); - -static int -procfs_control(struct thread *td, struct proc *p, int op) -{ - int error = 0; - struct thread *temp; - - /* - * Attach - attaches the target process for debugging - * by the calling process. - */ - if (op == PROCFS_CTL_ATTACH) { - sx_xlock(&proctree_lock); - PROC_LOCK(p); - if ((error = p_candebug(td, p)) != 0) - goto out; - if (p->p_flag & P_TRACED) { - error = EBUSY; - goto out; - } - - /* Can't trace yourself! */ - if (p->p_pid == td->td_proc->p_pid) { - error = EINVAL; - goto out; - } - - /* - * Go ahead and set the trace flag. - * Save the old parent (it's reset in - * _DETACH, and also in kern_exit.c:wait4() - * Reparent the process so that the tracing - * proc gets to see all the action. - * Stop the target. - */ - p->p_flag |= P_TRACED; - faultin(p); - p->p_xsig = 0; /* XXX ? */ - p->p_oppid = p->p_pptr->p_pid; - if (p->p_pptr != td->td_proc) { - proc_reparent(p, td->td_proc); - } - kern_psignal(p, SIGSTOP); -out: - PROC_UNLOCK(p); - sx_xunlock(&proctree_lock); - return (error); - } - - /* - * Authorization check: rely on normal debugging protection, except - * allow processes to disengage debugging on a process onto which - * they have previously attached, but no longer have permission to - * debug. - */ - PROC_LOCK(p); - if (op != PROCFS_CTL_DETACH && - ((error = p_candebug(td, p)))) { - PROC_UNLOCK(p); - return (error); - } - - /* - * Target process must be stopped, owned by (td) and - * be set up for tracing (P_TRACED flag set). - * Allow DETACH to take place at any time for sanity. - * Allow WAIT any time, of course. - */ - switch (op) { - case PROCFS_CTL_DETACH: - case PROCFS_CTL_WAIT: - break; - - default: - if (!TRACE_WAIT_P(td->td_proc, p)) { - PROC_UNLOCK(p); - return (EBUSY); - } - } - - -#ifdef FIX_SSTEP - /* - * do single-step fixup if needed - */ - FIX_SSTEP(FIRST_THREAD_IN_PROC(p)); -#endif - - /* - * Don't deliver any signal by default. - * To continue with a signal, just send - * the signal name to the ctl file - */ - p->p_xsig = 0; - - switch (op) { - /* - * Detach. Cleans up the target process, reparent it if possible - * and set it running once more. - */ - case PROCFS_CTL_DETACH: - /* if not being traced, then this is a painless no-op */ - if ((p->p_flag & P_TRACED) == 0) { - PROC_UNLOCK(p); - return (0); - } - - /* not being traced any more */ - p->p_flag &= ~(P_TRACED | P_STOPPED_TRACE); - - /* remove pending SIGTRAP, else the process will die */ - sigqueue_delete_proc(p, SIGTRAP); - FOREACH_THREAD_IN_PROC(p, temp) - temp->td_dbgflags &= ~TDB_SUSPEND; - PROC_UNLOCK(p); - - /* give process back to original parent */ - sx_xlock(&proctree_lock); - if (p->p_oppid != p->p_pptr->p_pid) { - struct proc *pp; - - pp = pfind(p->p_oppid); - PROC_LOCK(p); - if (pp) { - PROC_UNLOCK(pp); - proc_reparent(p, pp); - } - } else - PROC_LOCK(p); - p->p_oppid = 0; - p->p_stops = 0; - p->p_flag &= ~P_WAITED; /* XXX ? */ - sx_xunlock(&proctree_lock); - - wakeup(td->td_proc); /* XXX for CTL_WAIT below ? */ - - break; - - /* - * Step. Let the target process execute a single instruction. - * What does it mean to single step a threaded program? - */ - case PROCFS_CTL_STEP: - error = proc_sstep(FIRST_THREAD_IN_PROC(p)); - if (error) { - PROC_UNLOCK(p); - return (error); - } - break; - - /* - * Run. Let the target process continue running until a breakpoint - * or some other trap. - */ - case PROCFS_CTL_RUN: - p->p_flag &= ~P_STOPPED_SIG; /* this uses SIGSTOP */ - break; - - /* - * Wait for the target process to stop. - * If the target is not being traced then just wait - * to enter - */ - case PROCFS_CTL_WAIT: - if (p->p_flag & P_TRACED) { - while (error == 0 && - (P_SHOULDSTOP(p)) && - (p->p_flag & P_TRACED) && - (p->p_pptr == td->td_proc)) - error = msleep(p, &p->p_mtx, - PWAIT|PCATCH, "procfsx", 0); - if (error == 0 && !TRACE_WAIT_P(td->td_proc, p)) - error = EBUSY; - } else { - while (error == 0 && P_SHOULDSTOP(p)) - error = msleep(p, &p->p_mtx, - PWAIT|PCATCH, "procfs", 0); - } - PROC_UNLOCK(p); - return (error); - default: - panic("procfs_control"); - } - - PROC_SLOCK(p); - thread_unsuspend(p); /* If it can run, let it do so. */ - PROC_SUNLOCK(p); - PROC_UNLOCK(p); - return (0); -} - -static struct namemap * -findname(struct namemap *nm, char *buf, int buflen) -{ - - for (; nm->nm_name; nm++) - if (bcmp(buf, nm->nm_name, buflen+1) == 0) - return (nm); - - return (0); -} - -int -procfs_doprocctl(PFS_FILL_ARGS) -{ - int error; - struct namemap *nm; - - if (uio == NULL || uio->uio_rw != UIO_WRITE) - return (EOPNOTSUPP); - - /* - * Map signal names into signal generation - * or debug control. Unknown commands and/or signals - * return EOPNOTSUPP. - * - * Sending a signal while the process is being debugged - * also has the side effect of letting the target continue - * to run. There is no way to single-step a signal delivery. - */ - error = EOPNOTSUPP; - - sbuf_trim(sb); - sbuf_finish(sb); - nm = findname(ctlnames, sbuf_data(sb), sbuf_len(sb)); - if (nm) { - printf("procfs: got a %s command\n", sbuf_data(sb)); - error = procfs_control(td, p, nm->nm_val); - } else { - nm = findname(signames, sbuf_data(sb), sbuf_len(sb)); - if (nm) { - printf("procfs: got a sig%s\n", sbuf_data(sb)); - PROC_LOCK(p); - - if (TRACE_WAIT_P(td->td_proc, p)) { - p->p_xsig = nm->nm_val; -#ifdef FIX_SSTEP - FIX_SSTEP(FIRST_THREAD_IN_PROC(p)); -#endif - p->p_flag &= ~P_STOPPED_SIG; - PROC_SLOCK(p); - thread_unsuspend(p); - PROC_SUNLOCK(p); - } else - kern_psignal(p, nm->nm_val); - PROC_UNLOCK(p); - error = 0; - } - } - - return (error); -} diff --git a/sys/fs/procfs/procfs_ioctl.c b/sys/fs/procfs/procfs_ioctl.c deleted file mode 100644 index 95481c894e2..00000000000 --- a/sys/fs/procfs/procfs_ioctl.c +++ /dev/null @@ -1,262 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-3-Clause - * - * Copyright (c) 2001 Dag-Erling Coïdan Smørgrav - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer - * in this position and unchanged. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#ifdef COMPAT_FREEBSD32 -struct procfs_status32 { - int state; /* Running, stopped, something else? */ - int flags; /* Any flags */ - unsigned int events; /* Events to stop on */ - int why; /* What event, if any, proc stopped on */ - unsigned int val; /* Any extra data */ -}; - -#define PIOCWAIT32 _IOR('p', 4, struct procfs_status32) -#define PIOCSTATUS32 _IOR('p', 6, struct procfs_status32) -#endif - -/* - * Process ioctls - */ -int -procfs_ioctl(PFS_IOCTL_ARGS) -{ - struct procfs_status *ps; -#ifdef COMPAT_FREEBSD32 - struct procfs_status32 *ps32; -#endif - int error, flags, sig; -#ifdef COMPAT_FREEBSD6 - int ival; -#endif - static struct timeval lasttime; - static struct timeval interval = { .tv_sec = 1, .tv_usec = 0 }; - - KASSERT(p != NULL, - ("%s() called without a process", __func__)); - PROC_LOCK_ASSERT(p, MA_OWNED); - - switch (cmd) { -#if defined(COMPAT_FREEBSD5) || defined(COMPAT_FREEBSD4) || defined(COMPAT_43) - case _IOC(IOC_IN, 'p', 1, 0): -#endif -#ifdef COMPAT_FREEBSD6 - case _IO('p', 1): -#endif - case PIOCBIS: -#if defined(COMPAT_FREEBSD5) || defined(COMPAT_FREEBSD4) || defined(COMPAT_43) - case _IOC(IOC_IN, 'p', 2, 0): -#endif -#ifdef COMPAT_FREEBSD6 - case _IO('p', 2): -#endif - case PIOCBIC: -#if defined(COMPAT_FREEBSD5) || defined(COMPAT_FREEBSD4) || defined(COMPAT_43) - case _IOC(IOC_IN, 'p', 3, 0): -#endif -#ifdef COMPAT_FREEBSD6 - case _IO('p', 3): -#endif - case PIOCSFL: - case PIOCGFL: - case PIOCWAIT: - case PIOCSTATUS: -#ifdef COMPAT_FREEBSD32 - case PIOCWAIT32: - case PIOCSTATUS32: -#endif -#if defined(COMPAT_FREEBSD5) || defined(COMPAT_FREEBSD4) || defined(COMPAT_43) - case _IOC(IOC_IN, 'p', 5, 0): -#endif -#ifdef COMPAT_FREEBSD6 - case _IO('p', 5): -#endif - case PIOCCONT: - if (ratecheck(&lasttime, &interval) != 0) - gone_in(13, "procfs-based process debugging"); - break; - } - - error = 0; - switch (cmd) { -#if defined(COMPAT_FREEBSD5) || defined(COMPAT_FREEBSD4) || defined(COMPAT_43) - case _IOC(IOC_IN, 'p', 1, 0): -#endif -#ifdef COMPAT_FREEBSD6 - case _IO('p', 1): - ival = IOCPARM_IVAL(data); - data = &ival; -#endif - case PIOCBIS: - p->p_stops |= *(unsigned int *)data; - break; -#if defined(COMPAT_FREEBSD5) || defined(COMPAT_FREEBSD4) || defined(COMPAT_43) - case _IOC(IOC_IN, 'p', 2, 0): -#endif -#ifdef COMPAT_FREEBSD6 - case _IO('p', 2): - ival = IOCPARM_IVAL(data); - data = &ival; -#endif - case PIOCBIC: - p->p_stops &= ~*(unsigned int *)data; - break; -#if defined(COMPAT_FREEBSD5) || defined(COMPAT_FREEBSD4) || defined(COMPAT_43) - case _IOC(IOC_IN, 'p', 3, 0): -#endif -#ifdef COMPAT_FREEBSD6 - case _IO('p', 3): - ival = IOCPARM_IVAL(data); - data = &ival; -#endif - case PIOCSFL: - flags = *(unsigned int *)data; - if (flags & PF_ISUGID) { - /* - * XXXRW: Is this specific check required here, as - * p_candebug() should implement it, or other checks - * are missing. - */ - error = priv_check(td, PRIV_DEBUG_SUGID); - if (error) - break; - } - p->p_pfsflags = flags; - break; - case PIOCGFL: - *(unsigned int *)data = p->p_pfsflags; - break; - case PIOCWAIT: - while (p->p_step == 0 && (p->p_flag & P_WEXIT) == 0) { - /* sleep until p stops */ - _PHOLD(p); - error = msleep(&p->p_stype, &p->p_mtx, - PWAIT|PCATCH, "pioctl", 0); - _PRELE(p); - if (error != 0) - break; - } - /* fall through to PIOCSTATUS */ - case PIOCSTATUS: - ps = (struct procfs_status *)data; - ps->state = (p->p_step == 0); - ps->flags = 0; /* nope */ - ps->events = p->p_stops; - ps->why = p->p_step ? p->p_stype : 0; - ps->val = p->p_step ? p->p_xsig : 0; - break; -#ifdef COMPAT_FREEBSD32 - case PIOCWAIT32: - while (p->p_step == 0 && (p->p_flag & P_WEXIT) == 0) { - /* sleep until p stops */ - _PHOLD(p); - error = msleep(&p->p_stype, &p->p_mtx, - PWAIT|PCATCH, "pioctl", 0); - _PRELE(p); - if (error != 0) - break; - } - /* fall through to PIOCSTATUS32 */ - case PIOCSTATUS32: - ps32 = (struct procfs_status32 *)data; - ps32->state = (p->p_step == 0); - ps32->flags = 0; /* nope */ - ps32->events = p->p_stops; - ps32->why = p->p_step ? p->p_stype : 0; - ps32->val = p->p_step ? p->p_xsig : 0; - break; -#endif -#if defined(COMPAT_FREEBSD5) || defined(COMPAT_FREEBSD4) || defined(COMPAT_43) - case _IOC(IOC_IN, 'p', 5, 0): -#endif -#ifdef COMPAT_FREEBSD6 - case _IO('p', 5): - ival = IOCPARM_IVAL(data); - data = &ival; -#endif - case PIOCCONT: - if (p->p_step == 0) - break; - sig = *(unsigned int *)data; - if (sig != 0 && !_SIG_VALID(sig)) { - error = EINVAL; - break; - } -#if 0 - p->p_step = 0; - if (P_SHOULDSTOP(p)) { - p->p_xsig = sig; - p->p_flag &= ~(P_STOPPED_TRACE|P_STOPPED_SIG); - PROC_SLOCK(p); - thread_unsuspend(p); - PROC_SUNLOCK(p); - } else if (sig) - kern_psignal(p, sig); -#else - if (sig) - kern_psignal(p, sig); - p->p_step = 0; - wakeup(&p->p_step); -#endif - break; - default: - error = (ENOTTY); - } - - return (error); -} - -/* - * Clean up on last close - */ -int -procfs_close(PFS_CLOSE_ARGS) -{ - if (p != NULL && (p->p_pfsflags & PF_LINGER) == 0) { - PROC_LOCK_ASSERT(p, MA_OWNED); - p->p_pfsflags = 0; - p->p_stops = 0; - p->p_step = 0; - wakeup(&p->p_step); - } - return (0); -} diff --git a/sys/geom/geom_bsd.c b/sys/geom/geom_bsd.c deleted file mode 100644 index 3bbe3656470..00000000000 --- a/sys/geom/geom_bsd.c +++ /dev/null @@ -1,618 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-3-Clause - * - * Copyright (c) 2002 Poul-Henning Kamp - * Copyright (c) 2002 Networks Associates Technology, Inc. - * All rights reserved. - * - * This software was developed for the FreeBSD Project by Poul-Henning Kamp - * and NAI Labs, the Security Research Division of Network Associates, Inc. - * under DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the - * DARPA CHATS research program. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The names of the authors may not be used to endorse or promote - * products derived from this software without specific prior written - * permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -/* - * This is the method for dealing with BSD disklabels. It has been - * extensively (by my standards at least) commented, in the vain hope that - * it will serve as the source in future copy&paste operations. - */ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -FEATURE(geom_bsd, "GEOM BSD disklabels support"); - -#define BSD_CLASS_NAME "BSD" - -#define ALPHA_LABEL_OFFSET 64 -#define HISTORIC_LABEL_OFFSET 512 - -#define LABELSIZE (148 + 16 * MAXPARTITIONS) - -static int g_bsd_once; - -static void g_bsd_hotwrite(void *arg, int flag); -/* - * Our private data about one instance. All the rest is handled by the - * slice code and stored in its softc, so this is just the stuff - * specific to BSD disklabels. - */ -struct g_bsd_softc { - off_t labeloffset; - off_t mbroffset; - off_t rawoffset; - struct disklabel ondisk; - u_char label[LABELSIZE]; - u_char labelsum[16]; -}; - -/* - * Modify our slicer to match proposed disklabel, if possible. - * This is where we make sure we don't do something stupid. - */ -static int -g_bsd_modify(struct g_geom *gp, u_char *label) -{ - int i, error; - struct partition *ppp; - struct g_slicer *gsp; - struct g_consumer *cp; - struct g_bsd_softc *ms; - u_int secsize, u; - off_t rawoffset, o; - struct disklabel dl; - MD5_CTX md5sum; - - g_topology_assert(); - gsp = gp->softc; - ms = gsp->softc; - - error = bsd_disklabel_le_dec(label, &dl, MAXPARTITIONS); - if (error) { - return (error); - } - - /* Get dimensions of our device. */ - cp = LIST_FIRST(&gp->consumer); - secsize = cp->provider->sectorsize; - - /* ... or a smaller sector size. */ - if (dl.d_secsize < secsize) { - return (EINVAL); - } - - /* ... or a non-multiple sector size. */ - if (dl.d_secsize % secsize != 0) { - return (EINVAL); - } - - /* Historical braindamage... */ - rawoffset = (off_t)dl.d_partitions[RAW_PART].p_offset * dl.d_secsize; - - for (i = 0; i < dl.d_npartitions; i++) { - ppp = &dl.d_partitions[i]; - if (ppp->p_size == 0) - continue; - o = (off_t)ppp->p_offset * dl.d_secsize; - - if (o < rawoffset) - rawoffset = 0; - } - - if (rawoffset != 0 && (off_t)rawoffset != ms->mbroffset) - printf("WARNING: %s expected rawoffset %jd, found %jd\n", - gp->name, - (intmax_t)ms->mbroffset/dl.d_secsize, - (intmax_t)rawoffset/dl.d_secsize); - - /* Don't munge open partitions. */ - for (i = 0; i < dl.d_npartitions; i++) { - ppp = &dl.d_partitions[i]; - - o = (off_t)ppp->p_offset * dl.d_secsize; - if (o == 0) - o = rawoffset; - error = g_slice_config(gp, i, G_SLICE_CONFIG_CHECK, - o - rawoffset, - (off_t)ppp->p_size * dl.d_secsize, - dl.d_secsize, - "%s%c", gp->name, 'a' + i); - if (error) - return (error); - } - - /* Look good, go for it... */ - for (u = 0; u < gsp->nslice; u++) { - ppp = &dl.d_partitions[u]; - o = (off_t)ppp->p_offset * dl.d_secsize; - if (o == 0) - o = rawoffset; - g_slice_config(gp, u, G_SLICE_CONFIG_SET, - o - rawoffset, - (off_t)ppp->p_size * dl.d_secsize, - dl.d_secsize, - "%s%c", gp->name, 'a' + u); - } - - /* Update our softc */ - ms->ondisk = dl; - if (label != ms->label) - bcopy(label, ms->label, LABELSIZE); - ms->rawoffset = rawoffset; - - /* - * In order to avoid recursively attaching to the same - * on-disk label (it's usually visible through the 'c' - * partition) we calculate an MD5 and ask if other BSD's - * below us love that label. If they do, we don't. - */ - MD5Init(&md5sum); - MD5Update(&md5sum, ms->label, sizeof(ms->label)); - MD5Final(ms->labelsum, &md5sum); - - return (0); -} - -/* - * This is an internal helper function, called multiple times from the taste - * function to try to locate a disklabel on the disk. More civilized formats - * will not need this, as there is only one possible place on disk to look - * for the magic spot. - */ - -static int -g_bsd_try(struct g_geom *gp, struct g_slicer *gsp, struct g_consumer *cp, int secsize, struct g_bsd_softc *ms, off_t offset) -{ - int error; - u_char *buf; - struct disklabel *dl; - off_t secoff; - - /* - * We need to read entire aligned sectors, and we assume that the - * disklabel does not span sectors, so one sector is enough. - */ - secoff = offset % secsize; - buf = g_read_data(cp, offset - secoff, secsize, NULL); - if (buf == NULL) - return (ENOENT); - - /* Decode into our native format. */ - dl = &ms->ondisk; - error = bsd_disklabel_le_dec(buf + secoff, dl, MAXPARTITIONS); - if (!error) - bcopy(buf + secoff, ms->label, LABELSIZE); - - /* Remember to free the buffer g_read_data() gave us. */ - g_free(buf); - - ms->labeloffset = offset; - return (error); -} - -/* - * This function writes the current label to disk, possibly updating - * the alpha SRM checksum. - */ - -static int -g_bsd_writelabel(struct g_geom *gp, u_char *bootcode) -{ - off_t secoff; - u_int secsize; - struct g_consumer *cp; - struct g_slicer *gsp; - struct g_bsd_softc *ms; - u_char *buf; - uint64_t sum; - int error, i; - - gsp = gp->softc; - ms = gsp->softc; - cp = LIST_FIRST(&gp->consumer); - /* Get sector size, we need it to read data. */ - secsize = cp->provider->sectorsize; - secoff = ms->labeloffset % secsize; - if (bootcode == NULL) { - buf = g_read_data(cp, ms->labeloffset - secoff, secsize, &error); - if (buf == NULL) - return (error); - bcopy(ms->label, buf + secoff, sizeof(ms->label)); - } else { - buf = bootcode; - bcopy(ms->label, buf + ms->labeloffset, sizeof(ms->label)); - } - if (ms->labeloffset == ALPHA_LABEL_OFFSET) { - sum = 0; - for (i = 0; i < 63; i++) - sum += le64dec(buf + i * 8); - le64enc(buf + 504, sum); - } - if (bootcode == NULL) { - error = g_write_data(cp, ms->labeloffset - secoff, buf, secsize); - g_free(buf); - } else { - error = g_write_data(cp, 0, bootcode, BBSIZE); - } - return(error); -} - -/* - * If the user tries to overwrite our disklabel through an open partition - * or via a magicwrite config call, we end up here and try to prevent - * footshooting as best we can. - */ -static void -g_bsd_hotwrite(void *arg, int flag) -{ - struct bio *bp; - struct g_geom *gp; - struct g_slicer *gsp; - struct g_slice *gsl; - struct g_bsd_softc *ms; - u_char *p; - int error; - - g_topology_assert(); - /* - * We should never get canceled, because that would amount to a removal - * of the geom while there was outstanding I/O requests. - */ - KASSERT(flag != EV_CANCEL, ("g_bsd_hotwrite cancelled")); - bp = arg; - gp = bp->bio_to->geom; - gsp = gp->softc; - ms = gsp->softc; - gsl = &gsp->slices[bp->bio_to->index]; - p = (u_char*)bp->bio_data + ms->labeloffset - - (bp->bio_offset + gsl->offset); - error = g_bsd_modify(gp, p); - if (error) { - g_io_deliver(bp, EPERM); - return; - } - g_slice_finish_hot(bp); -} - -static int -g_bsd_start(struct bio *bp) -{ - struct g_geom *gp; - struct g_bsd_softc *ms; - struct g_slicer *gsp; - - gp = bp->bio_to->geom; - gsp = gp->softc; - ms = gsp->softc; - if (bp->bio_cmd == BIO_GETATTR) { - if (g_handleattr(bp, "BSD::labelsum", ms->labelsum, - sizeof(ms->labelsum))) - return (1); - } - return (0); -} - -/* - * Dump configuration information in XML format. - * Notice that the function is called once for the geom and once for each - * consumer and provider. We let g_slice_dumpconf() do most of the work. - */ -static void -g_bsd_dumpconf(struct sbuf *sb, const char *indent, struct g_geom *gp, struct g_consumer *cp, struct g_provider *pp) -{ - struct g_bsd_softc *ms; - struct g_slicer *gsp; - - gsp = gp->softc; - ms = gsp->softc; - g_slice_dumpconf(sb, indent, gp, cp, pp); - if (indent != NULL && pp == NULL && cp == NULL) { - sbuf_printf(sb, "%s%jd\n", - indent, (intmax_t)ms->labeloffset); - sbuf_printf(sb, "%s%jd\n", - indent, (intmax_t)ms->rawoffset); - sbuf_printf(sb, "%s%jd\n", - indent, (intmax_t)ms->mbroffset); - } else if (pp != NULL) { - if (indent == NULL) - sbuf_printf(sb, " ty %d", - ms->ondisk.d_partitions[pp->index].p_fstype); - else - sbuf_printf(sb, "%s%d\n", indent, - ms->ondisk.d_partitions[pp->index].p_fstype); - } -} - -/* - * The taste function is called from the event-handler, with the topology - * lock already held and a provider to examine. The flags are unused. - * - * If flags == G_TF_NORMAL, the idea is to take a bite of the provider and - * if we find valid, consistent magic on it, build a geom on it. - * - * There may be cases where the operator would like to put a BSD-geom on - * providers which do not meet all of the requirements. This can be done - * by instead passing the G_TF_INSIST flag, which will override these - * checks. - * - * The final flags value is G_TF_TRANSPARENT, which instructs the method - * to put a geom on top of the provider and configure it to be as transparent - * as possible. This is not really relevant to the BSD method and therefore - * not implemented here. - */ - -static struct uuid midnightbsd_slice = GPT_ENT_TYPE_MIDNIGHTBSD; -static struct uuid freebsd_slice = GPT_ENT_TYPE_FREEBSD; - -static struct g_geom * -g_bsd_taste(struct g_class *mp, struct g_provider *pp, int flags) -{ - struct g_geom *gp; - struct g_consumer *cp; - int error, i; - struct g_bsd_softc *ms; - u_int secsize; - struct g_slicer *gsp; - u_char hash[16]; - MD5_CTX md5sum; - struct uuid uuid; - - g_trace(G_T_TOPOLOGY, "bsd_taste(%s,%s)", mp->name, pp->name); - g_topology_assert(); - - /* We don't implement transparent inserts. */ - if (flags == G_TF_TRANSPARENT) - return (NULL); - - /* - * BSD labels are a subclass of the general "slicing" topology so - * a lot of the work can be done by the common "slice" code. - * Create a geom with space for MAXPARTITIONS providers, one consumer - * and a softc structure for us. Specify the provider to attach - * the consumer to and our "start" routine for special requests. - * The provider is opened with mode (1,0,0) so we can do reads - * from it. - */ - gp = g_slice_new(mp, MAXPARTITIONS, pp, &cp, &ms, - sizeof(*ms), g_bsd_start); - if (gp == NULL) - return (NULL); - - /* Get the geom_slicer softc from the geom. */ - gsp = gp->softc; - - /* - * The do...while loop here allows us to have multiple escapes - * using a simple "break". This improves code clarity without - * ending up in deep nesting and without using goto or come from. - */ - do { - /* - * If the provider is an MBR we will only auto attach - * to type 165 slices in the G_TF_NORMAL case. We will - * attach to any other type. - */ - error = g_getattr("MBR::type", cp, &i); - if (!error) { - if (i != 165 && flags == G_TF_NORMAL) - break; - error = g_getattr("MBR::offset", cp, &ms->mbroffset); - if (error) - break; - } - - /* Same thing if we are inside a GPT */ - error = g_getattr("GPT::type", cp, &uuid); - if (!error) { - if (memcmp(&uuid, &freebsd_slice, sizeof(uuid)) != 0 && - memcmp(&uuid, &midnightbsd_slice, sizeof(uuid)) != 0 && - flags == G_TF_NORMAL) - break; - } - - /* Get sector size, we need it to read data. */ - secsize = cp->provider->sectorsize; - if (secsize < 512) - break; - - /* First look for a label at the start of the second sector. */ - error = g_bsd_try(gp, gsp, cp, secsize, ms, secsize); - - /* - * If sector size is not 512 the label still can be at - * offset 512, not at the start of the second sector. At least - * it's true for labels created by the FreeBSD's bsdlabel(8). - */ - if (error && secsize != HISTORIC_LABEL_OFFSET) - error = g_bsd_try(gp, gsp, cp, secsize, ms, - HISTORIC_LABEL_OFFSET); - - /* Next, look for alpha labels */ - if (error) - error = g_bsd_try(gp, gsp, cp, secsize, ms, - ALPHA_LABEL_OFFSET); - - /* If we didn't find a label, punt. */ - if (error) - break; - - /* - * In order to avoid recursively attaching to the same - * on-disk label (it's usually visible through the 'c' - * partition) we calculate an MD5 and ask if other BSD's - * below us love that label. If they do, we don't. - */ - MD5Init(&md5sum); - MD5Update(&md5sum, ms->label, sizeof(ms->label)); - MD5Final(ms->labelsum, &md5sum); - - error = g_getattr("BSD::labelsum", cp, &hash); - if (!error && !bcmp(ms->labelsum, hash, sizeof(hash))) - break; - - /* - * Process the found disklabel, and modify our "slice" - * instance to match it, if possible. - */ - error = g_bsd_modify(gp, ms->label); - } while (0); - - /* Success or failure, we can close our provider now. */ - g_access(cp, -1, 0, 0); - - /* If we have configured any providers, return the new geom. */ - if (gsp->nprovider > 0) { - g_slice_conf_hot(gp, 0, ms->labeloffset, LABELSIZE, - G_SLICE_HOT_ALLOW, G_SLICE_HOT_DENY, G_SLICE_HOT_CALL); - gsp->hot = g_bsd_hotwrite; - if (!g_bsd_once) { - g_bsd_once = 1; - printf( - "WARNING: geom_bsd (geom %s) is deprecated, " - "use gpart instead.\n", gp->name); - } - return (gp); - } - /* - * ...else push the "self-destruct" button, by spoiling our own - * consumer. This triggers a call to g_slice_spoiled which will - * dismantle what was setup. - */ - g_slice_spoiled(cp); - return (NULL); -} - -struct h0h0 { - struct g_geom *gp; - struct g_bsd_softc *ms; - u_char *label; - int error; -}; - -static void -g_bsd_callconfig(void *arg, int flag) -{ - struct h0h0 *hp; - - hp = arg; - hp->error = g_bsd_modify(hp->gp, hp->label); - if (!hp->error) - hp->error = g_bsd_writelabel(hp->gp, NULL); -} - -/* - * NB! curthread is user process which GCTL'ed. - */ -static void -g_bsd_config(struct gctl_req *req, struct g_class *mp, char const *verb) -{ - u_char *label; - int error; - struct h0h0 h0h0; - struct g_geom *gp; - struct g_slicer *gsp; - struct g_consumer *cp; - struct g_bsd_softc *ms; - - g_topology_assert(); - gp = gctl_get_geom(req, mp, "geom"); - if (gp == NULL) - return; - cp = LIST_FIRST(&gp->consumer); - gsp = gp->softc; - ms = gsp->softc; - if (!strcmp(verb, "read mbroffset")) { - gctl_set_param_err(req, "mbroffset", &ms->mbroffset, - sizeof(ms->mbroffset)); - return; - } else if (!strcmp(verb, "write label")) { - label = gctl_get_paraml(req, "label", LABELSIZE); - if (label == NULL) - return; - h0h0.gp = gp; - h0h0.ms = gsp->softc; - h0h0.label = label; - h0h0.error = -1; - /* XXX: Does this reference register with our selfdestruct code ? */ - error = g_access(cp, 1, 1, 1); - if (error) { - gctl_error(req, "could not access consumer"); - return; - } - g_bsd_callconfig(&h0h0, 0); - error = h0h0.error; - g_access(cp, -1, -1, -1); - } else if (!strcmp(verb, "write bootcode")) { - label = gctl_get_paraml(req, "bootcode", BBSIZE); - if (label == NULL) - return; - /* XXX: Does this reference register with our selfdestruct code ? */ - error = g_access(cp, 1, 1, 1); - if (error) { - gctl_error(req, "could not access consumer"); - return; - } - error = g_bsd_writelabel(gp, label); - g_access(cp, -1, -1, -1); - } else { - gctl_error(req, "Unknown verb parameter"); - } - - return; -} - -/* Finally, register with GEOM infrastructure. */ -static struct g_class g_bsd_class = { - .name = BSD_CLASS_NAME, - .version = G_VERSION, - .taste = g_bsd_taste, - .ctlreq = g_bsd_config, - .dumpconf = g_bsd_dumpconf, -}; - -DECLARE_GEOM_CLASS(g_bsd_class, g_bsd); -MODULE_VERSION(geom_bsd, 0); diff --git a/sys/geom/geom_fox.c b/sys/geom/geom_fox.c deleted file mode 100644 index e39c9b886d6..00000000000 --- a/sys/geom/geom_fox.c +++ /dev/null @@ -1,487 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-3-Clause - * - * Copyright (c) 2003 Poul-Henning Kamp - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The names of the authors may not be used to endorse or promote - * products derived from this software without specific prior written - * permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - */ - -/* This is a GEOM module for handling path selection for multi-path - * storage devices. It is named "fox" because it, like they, prefer - * to have multiple exits to choose from. - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define FOX_CLASS_NAME "FOX" -#define FOX_MAGIC "GEOM::FOX" - -static int g_fox_once; - -FEATURE(geom_fox, "GEOM FOX redundant path mitigation support"); - -struct g_fox_softc { - off_t mediasize; - u_int sectorsize; - TAILQ_HEAD(, bio) queue; - struct mtx lock; - u_char magic[16]; - struct g_consumer *path; - struct g_consumer *opath; - int waiting; - int cr, cw, ce; -}; - -/* - * This function is called whenever we need to select a new path. - */ -static void -g_fox_select_path(void *arg, int flag) -{ - struct g_geom *gp; - struct g_fox_softc *sc; - struct g_consumer *cp1; - struct bio *bp; - int error; - - g_topology_assert(); - if (flag == EV_CANCEL) - return; - gp = arg; - sc = gp->softc; - - if (sc->opath != NULL) { - /* - * First, close the old path entirely. - */ - printf("Closing old path (%s) on fox (%s)\n", - sc->opath->provider->name, gp->name); - - cp1 = LIST_NEXT(sc->opath, consumer); - - g_access(sc->opath, -sc->cr, -sc->cw, -(sc->ce + 1)); - - /* - * The attempt to reopen it with a exclusive count - */ - error = g_access(sc->opath, 0, 0, 1); - if (error) { - /* - * Ok, ditch this consumer, we can't use it. - */ - printf("Drop old path (%s) on fox (%s)\n", - sc->opath->provider->name, gp->name); - g_detach(sc->opath); - g_destroy_consumer(sc->opath); - if (LIST_EMPTY(&gp->consumer)) { - /* No consumers left */ - g_wither_geom(gp, ENXIO); - for (;;) { - bp = TAILQ_FIRST(&sc->queue); - if (bp == NULL) - break; - TAILQ_REMOVE(&sc->queue, bp, bio_queue); - bp->bio_error = ENXIO; - g_std_done(bp); - } - return; - } - } else { - printf("Got e-bit on old path (%s) on fox (%s)\n", - sc->opath->provider->name, gp->name); - } - sc->opath = NULL; - } else { - cp1 = LIST_FIRST(&gp->consumer); - } - if (cp1 == NULL) - cp1 = LIST_FIRST(&gp->consumer); - printf("Open new path (%s) on fox (%s)\n", - cp1->provider->name, gp->name); - error = g_access(cp1, sc->cr, sc->cw, sc->ce); - if (error) { - /* - * If we failed, we take another trip through here - */ - printf("Open new path (%s) on fox (%s) failed, reselect.\n", - cp1->provider->name, gp->name); - sc->opath = cp1; - g_post_event(g_fox_select_path, gp, M_WAITOK, gp, NULL); - } else { - printf("Open new path (%s) on fox (%s) succeeded\n", - cp1->provider->name, gp->name); - mtx_lock(&sc->lock); - sc->path = cp1; - sc->waiting = 0; - for (;;) { - bp = TAILQ_FIRST(&sc->queue); - if (bp == NULL) - break; - TAILQ_REMOVE(&sc->queue, bp, bio_queue); - g_io_request(bp, sc->path); - } - mtx_unlock(&sc->lock); - } -} - -static void -g_fox_orphan(struct g_consumer *cp) -{ - struct g_geom *gp; - struct g_fox_softc *sc; - int error, mark; - - g_topology_assert(); - gp = cp->geom; - sc = gp->softc; - printf("Removing path (%s) from fox (%s)\n", - cp->provider->name, gp->name); - mtx_lock(&sc->lock); - if (cp == sc->path) { - sc->opath = NULL; - sc->path = NULL; - sc->waiting = 1; - mark = 1; - } else { - mark = 0; - } - mtx_unlock(&sc->lock); - - g_access(cp, -cp->acr, -cp->acw, -cp->ace); - error = cp->provider->error; - g_detach(cp); - g_destroy_consumer(cp); - if (!LIST_EMPTY(&gp->consumer)) { - if (mark) - g_post_event(g_fox_select_path, gp, M_WAITOK, gp, NULL); - return; - } - - mtx_destroy(&sc->lock); - g_free(gp->softc); - gp->softc = NULL; - g_wither_geom(gp, ENXIO); -} - -static void -g_fox_done(struct bio *bp) -{ - struct g_geom *gp; - struct g_fox_softc *sc; - int error; - - if (bp->bio_error == 0) { - g_std_done(bp); - return; - } - gp = bp->bio_from->geom; - sc = gp->softc; - if (bp->bio_from != sc->path) { - g_io_request(bp, sc->path); - return; - } - mtx_lock(&sc->lock); - sc->opath = sc->path; - sc->path = NULL; - error = g_post_event(g_fox_select_path, gp, M_NOWAIT, gp, NULL); - if (error) { - bp->bio_error = ENOMEM; - g_std_done(bp); - } else { - sc->waiting = 1; - TAILQ_INSERT_TAIL(&sc->queue, bp, bio_queue); - } - mtx_unlock(&sc->lock); -} - -static void -g_fox_start(struct bio *bp) -{ - struct g_geom *gp; - struct bio *bp2; - struct g_fox_softc *sc; - int error; - - gp = bp->bio_to->geom; - sc = gp->softc; - if (sc == NULL) { - g_io_deliver(bp, ENXIO); - return; - } - switch(bp->bio_cmd) { - case BIO_READ: - case BIO_WRITE: - case BIO_DELETE: - bp2 = g_clone_bio(bp); - if (bp2 == NULL) { - g_io_deliver(bp, ENOMEM); - break; - } - bp2->bio_offset += sc->sectorsize; - bp2->bio_done = g_fox_done; - mtx_lock(&sc->lock); - if (sc->path == NULL || !TAILQ_EMPTY(&sc->queue)) { - if (sc->waiting == 0) { - error = g_post_event(g_fox_select_path, gp, - M_NOWAIT, gp, NULL); - if (error) { - g_destroy_bio(bp2); - bp2 = NULL; - g_io_deliver(bp, error); - } else { - sc->waiting = 1; - } - } - if (bp2 != NULL) - TAILQ_INSERT_TAIL(&sc->queue, bp2, - bio_queue); - } else { - g_io_request(bp2, sc->path); - } - mtx_unlock(&sc->lock); - break; - default: - g_io_deliver(bp, EOPNOTSUPP); - break; - } - return; -} - -static int -g_fox_access(struct g_provider *pp, int dr, int dw, int de) -{ - struct g_geom *gp; - struct g_fox_softc *sc; - struct g_consumer *cp1; - int error; - - g_topology_assert(); - gp = pp->geom; - sc = gp->softc; - if (sc == NULL) { - if (dr <= 0 && dw <= 0 && de <= 0) - return (0); - else - return (ENXIO); - } - - if (sc->cr == 0 && sc->cw == 0 && sc->ce == 0) { - /* - * First open, open all consumers with an exclusive bit - */ - error = 0; - LIST_FOREACH(cp1, &gp->consumer, consumer) { - error = g_access(cp1, 0, 0, 1); - if (error) { - printf("FOX: access(%s,0,0,1) = %d\n", - cp1->provider->name, error); - break; - } - } - if (error) { - LIST_FOREACH(cp1, &gp->consumer, consumer) { - if (cp1->ace) - g_access(cp1, 0, 0, -1); - } - return (error); - } - } - if (sc->path == NULL) - g_fox_select_path(gp, 0); - if (sc->path == NULL) - error = ENXIO; - else - error = g_access(sc->path, dr, dw, de); - if (error == 0) { - sc->cr += dr; - sc->cw += dw; - sc->ce += de; - if (sc->cr == 0 && sc->cw == 0 && sc->ce == 0) { - /* - * Last close, remove e-bit on all consumers - */ - LIST_FOREACH(cp1, &gp->consumer, consumer) - g_access(cp1, 0, 0, -1); - } - } - return (error); -} - -static struct g_geom * -g_fox_taste(struct g_class *mp, struct g_provider *pp, int flags __unused) -{ - struct g_geom *gp, *gp2; - struct g_provider *pp2; - struct g_consumer *cp, *cp2; - struct g_fox_softc *sc, *sc2; - int error; - u_int sectorsize; - u_char *buf; - - g_trace(G_T_TOPOLOGY, "fox_taste(%s, %s)", mp->name, pp->name); - g_topology_assert(); - if (!strcmp(pp->geom->class->name, mp->name)) - return (NULL); - gp = g_new_geomf(mp, "%s.fox", pp->name); - gp->softc = g_malloc(sizeof(struct g_fox_softc), M_WAITOK | M_ZERO); - sc = gp->softc; - - cp = g_new_consumer(gp); - g_attach(cp, pp); - error = g_access(cp, 1, 0, 0); - if (error) { - g_free(sc); - g_detach(cp); - g_destroy_consumer(cp); - g_destroy_geom(gp); - return(NULL); - } - do { - sectorsize = cp->provider->sectorsize; - g_topology_unlock(); - buf = g_read_data(cp, 0, sectorsize, NULL); - g_topology_lock(); - if (buf == NULL) - break; - if (memcmp(buf, FOX_MAGIC, strlen(FOX_MAGIC))) - break; - - /* - * First we need to see if this a new path for an existing fox. - */ - LIST_FOREACH(gp2, &mp->geom, geom) { - sc2 = gp2->softc; - if (sc2 == NULL) - continue; - if (memcmp(buf + 16, sc2->magic, sizeof sc2->magic)) - continue; - break; - } - if (gp2 != NULL) { - /* - * It was. Create a new consumer for that fox, - * attach it, and if the fox is open, open this - * path with an exclusive count of one. - */ - printf("Adding path (%s) to fox (%s)\n", - pp->name, gp2->name); - cp2 = g_new_consumer(gp2); - g_attach(cp2, pp); - pp2 = LIST_FIRST(&gp2->provider); - if (pp2->acr > 0 || pp2->acw > 0 || pp2->ace > 0) { - error = g_access(cp2, 0, 0, 1); - if (error) { - /* - * This is bad, or more likely, - * the user is doing something stupid - */ - printf( - "WARNING: New path (%s) to fox(%s) not added: %s\n%s", - cp2->provider->name, gp2->name, - "Could not get exclusive bit.", - "WARNING: This indicates a risk of data inconsistency." - ); - g_detach(cp2); - g_destroy_consumer(cp2); - } - } - break; - } - printf("Creating new fox (%s)\n", pp->name); - sc->path = cp; - memcpy(sc->magic, buf + 16, sizeof sc->magic); - pp2 = g_new_providerf(gp, "%s", gp->name); - pp2->mediasize = sc->mediasize = pp->mediasize - pp->sectorsize; - pp2->sectorsize = sc->sectorsize = pp->sectorsize; -printf("fox %s lock %p\n", gp->name, &sc->lock); - - mtx_init(&sc->lock, "fox queue", NULL, MTX_DEF); - TAILQ_INIT(&sc->queue); - g_error_provider(pp2, 0); - } while (0); - if (buf != NULL) - g_free(buf); - g_access(cp, -1, 0, 0); - - if (!LIST_EMPTY(&gp->provider)) { - if (!g_fox_once) { - g_fox_once = 1; - printf( - "WARNING: geom_fox (geom %s) is deprecated, " - "use gmultipath instead.\n", gp->name); - } - return (gp); - } - - g_free(gp->softc); - g_detach(cp); - g_destroy_consumer(cp); - g_destroy_geom(gp); - return (NULL); -} - -static int -g_fox_destroy_geom(struct gctl_req *req, struct g_class *mp, struct g_geom *gp) -{ - struct g_fox_softc *sc; - - g_topology_assert(); - sc = gp->softc; - mtx_destroy(&sc->lock); - g_free(gp->softc); - gp->softc = NULL; - g_wither_geom(gp, ENXIO); - return (0); -} - -static struct g_class g_fox_class = { - .name = FOX_CLASS_NAME, - .version = G_VERSION, - .taste = g_fox_taste, - .destroy_geom = g_fox_destroy_geom, - .start = g_fox_start, - .spoiled = g_fox_orphan, - .orphan = g_fox_orphan, - .access= g_fox_access, -}; - -DECLARE_GEOM_CLASS(g_fox_class, g_fox); -MODULE_VERSION(geom_fox, 0); diff --git a/sys/geom/geom_mbr.c b/sys/geom/geom_mbr.c deleted file mode 100644 index 342cb4d7860..00000000000 --- a/sys/geom/geom_mbr.c +++ /dev/null @@ -1,530 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2002 Poul-Henning Kamp - * Copyright (c) 2002 Networks Associates Technology, Inc. - * All rights reserved. - * - * This software was developed for the FreeBSD Project by Poul-Henning Kamp - * and NAI Labs, the Security Research Division of Network Associates, Inc. - * under DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the - * DARPA CHATS research program. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -FEATURE(geom_mbr, "GEOM DOS/MBR partitioning support"); - -#define MBR_CLASS_NAME "MBR" -#define MBREXT_CLASS_NAME "MBREXT" - -static int g_mbr_once = 0; - -static struct dos_partition historical_bogus_partition_table[NDOSPART] = { - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, - { 0x80, 0, 1, 0, DOSPTYP_386BSD, 255, 255, 255, 0, 50000, }, -}; - -static struct dos_partition historical_bogus_partition_table_fixed[NDOSPART] = { - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, - { 0x80, 0, 1, 0, DOSPTYP_386BSD, 254, 255, 255, 0, 50000, }, -}; - -static void -g_mbr_print(int i, struct dos_partition *dp) -{ - - printf("[%d] f:%02x typ:%d", i, dp->dp_flag, dp->dp_typ); - printf(" s(CHS):%d/%d/%d", DPCYL(dp->dp_scyl, dp->dp_ssect), - dp->dp_shd, DPSECT(dp->dp_ssect)); - printf(" e(CHS):%d/%d/%d", DPCYL(dp->dp_ecyl, dp->dp_esect), - dp->dp_ehd, DPSECT(dp->dp_esect)); - printf(" s:%d l:%d\n", dp->dp_start, dp->dp_size); -} - -struct g_mbr_softc { - int type [NDOSPART]; - u_int sectorsize; - u_char sec0[512]; - u_char slicesum[16]; -}; - -/* - * XXX: Add gctl_req arg and give good error msgs. - * XXX: Check that length argument does not bring boot code inside any slice. - */ -static int -g_mbr_modify(struct g_geom *gp, struct g_mbr_softc *ms, u_char *sec0, int len __unused) -{ - int i, error; - off_t l[NDOSPART]; - struct dos_partition ndp[NDOSPART], *dp; - MD5_CTX md5sum; - - g_topology_assert(); - - if (sec0[0x1fe] != 0x55 && sec0[0x1ff] != 0xaa) - return (EBUSY); - - dp = ndp; - for (i = 0; i < NDOSPART; i++) { - dos_partition_dec( - sec0 + DOSPARTOFF + i * sizeof(struct dos_partition), - dp + i); - } - if ((!bcmp(dp, historical_bogus_partition_table, - sizeof historical_bogus_partition_table)) || - (!bcmp(dp, historical_bogus_partition_table_fixed, - sizeof historical_bogus_partition_table_fixed))) { - /* - * We will not allow people to write these from "the inside", - * Since properly selfdestructing takes too much code. If - * people really want to do this, they cannot have any - * providers of this geom open, and in that case they can just - * as easily overwrite the MBR in the parent device. - */ - return(EBUSY); - } - for (i = 0; i < NDOSPART; i++) { - /* - * A Protective MBR (PMBR) has a single partition of - * type 0xEE spanning the whole disk. Such a MBR - * protects a GPT on the disk from MBR tools that - * don't know anything about GPT. We're interpreting - * it a bit more loosely: any partition of type 0xEE - * is to be skipped as it doesn't contain any data - * that we should care about. We still allow other - * partitions to be present in the MBR. A PMBR will - * be handled correctly anyway. - */ - if (dp[i].dp_typ == DOSPTYP_PMBR) - l[i] = 0; - else if (dp[i].dp_flag != 0 && dp[i].dp_flag != 0x80) - l[i] = 0; - else if (dp[i].dp_typ == 0) - l[i] = 0; - else - l[i] = (off_t)dp[i].dp_size * ms->sectorsize; - error = g_slice_config(gp, i, G_SLICE_CONFIG_CHECK, - (off_t)dp[i].dp_start * ms->sectorsize, l[i], - ms->sectorsize, "%ss%d", gp->name, 1 + i); - if (error) - return (error); - } - for (i = 0; i < NDOSPART; i++) { - ms->type[i] = dp[i].dp_typ; - g_slice_config(gp, i, G_SLICE_CONFIG_SET, - (off_t)dp[i].dp_start * ms->sectorsize, l[i], - ms->sectorsize, "%ss%d", gp->name, 1 + i); - } - bcopy(sec0, ms->sec0, 512); - - /* - * Calculate MD5 from the first sector and use it for avoiding - * recursive slices creation. - */ - MD5Init(&md5sum); - MD5Update(&md5sum, ms->sec0, sizeof(ms->sec0)); - MD5Final(ms->slicesum, &md5sum); - - return (0); -} - -static int -g_mbr_ioctl(struct g_provider *pp, u_long cmd, void *data, int fflag, struct thread *td) -{ - struct g_geom *gp; - struct g_mbr_softc *ms; - struct g_slicer *gsp; - struct g_consumer *cp; - int error, opened; - - gp = pp->geom; - gsp = gp->softc; - ms = gsp->softc; - - opened = 0; - error = 0; - switch(cmd) { - case DIOCSMBR: { - if (!(fflag & FWRITE)) - return (EPERM); - g_topology_lock(); - cp = LIST_FIRST(&gp->consumer); - if (cp->acw == 0) { - error = g_access(cp, 0, 1, 0); - if (error == 0) - opened = 1; - } - if (!error) - error = g_mbr_modify(gp, ms, data, 512); - if (!error) - error = g_write_data(cp, 0, data, 512); - if (opened) - g_access(cp, 0, -1 , 0); - g_topology_unlock(); - return(error); - } - default: - return (ENOIOCTL); - } -} - -static int -g_mbr_start(struct bio *bp) -{ - struct g_provider *pp; - struct g_geom *gp; - struct g_mbr_softc *mp; - struct g_slicer *gsp; - int idx; - - pp = bp->bio_to; - idx = pp->index; - gp = pp->geom; - gsp = gp->softc; - mp = gsp->softc; - if (bp->bio_cmd == BIO_GETATTR) { - if (g_handleattr_int(bp, "MBR::type", mp->type[idx])) - return (1); - if (g_handleattr_off_t(bp, "MBR::offset", - gsp->slices[idx].offset)) - return (1); - if (g_handleattr(bp, "MBR::slicesum", mp->slicesum, - sizeof(mp->slicesum))) - return (1); - } - - return (0); -} - -static void -g_mbr_dumpconf(struct sbuf *sb, const char *indent, struct g_geom *gp, struct g_consumer *cp __unused, struct g_provider *pp) -{ - struct g_mbr_softc *mp; - struct g_slicer *gsp; - - gsp = gp->softc; - mp = gsp->softc; - g_slice_dumpconf(sb, indent, gp, cp, pp); - if (pp != NULL) { - if (indent == NULL) - sbuf_printf(sb, " ty %d", mp->type[pp->index]); - else - sbuf_printf(sb, "%s%d\n", indent, - mp->type[pp->index]); - } -} - -static struct g_geom * -g_mbr_taste(struct g_class *mp, struct g_provider *pp, int insist) -{ - struct g_geom *gp; - struct g_consumer *cp; - int error; - struct g_mbr_softc *ms; - u_int fwsectors, sectorsize; - u_char *buf; - u_char hash[16]; - MD5_CTX md5sum; - - g_trace(G_T_TOPOLOGY, "mbr_taste(%s,%s)", mp->name, pp->name); - g_topology_assert(); - if (!strcmp(pp->geom->class->name, MBR_CLASS_NAME)) - return (NULL); - gp = g_slice_new(mp, NDOSPART, pp, &cp, &ms, sizeof *ms, g_mbr_start); - if (gp == NULL) - return (NULL); - g_topology_unlock(); - do { - error = g_getattr("GEOM::fwsectors", cp, &fwsectors); - if (error) - fwsectors = 17; - sectorsize = cp->provider->sectorsize; - if (sectorsize < 512) - break; - ms->sectorsize = sectorsize; - buf = g_read_data(cp, 0, sectorsize, NULL); - if (buf == NULL) - break; - - /* - * Calculate MD5 from the first sector and use it for avoiding - * recursive slices creation. - */ - bcopy(buf, ms->sec0, 512); - MD5Init(&md5sum); - MD5Update(&md5sum, ms->sec0, sizeof(ms->sec0)); - MD5Final(ms->slicesum, &md5sum); - - error = g_getattr("MBR::slicesum", cp, &hash); - if (!error && !bcmp(ms->slicesum, hash, sizeof(hash))) { - g_free(buf); - break; - } - - g_topology_lock(); - g_mbr_modify(gp, ms, buf, 512); - g_topology_unlock(); - g_free(buf); - break; - } while (0); - g_topology_lock(); - g_access(cp, -1, 0, 0); - if (LIST_EMPTY(&gp->provider)) { - g_slice_spoiled(cp); - return (NULL); - } - if (!g_mbr_once) { - g_mbr_once = 1; - printf( - "WARNING: geom_mbr (geom %s) is deprecated, " - "use gpart instead.\n", gp->name); - } - return (gp); -} - -static void -g_mbr_config(struct gctl_req *req, struct g_class *mp, const char *verb) -{ - struct g_geom *gp; - struct g_consumer *cp; - struct g_mbr_softc *ms; - struct g_slicer *gsp; - int opened = 0, error = 0; - void *data; - int len; - - g_topology_assert(); - gp = gctl_get_geom(req, mp, "geom"); - if (gp == NULL) - return; - if (strcmp(verb, "write MBR")) { - gctl_error(req, "Unknown verb"); - return; - } - gsp = gp->softc; - ms = gsp->softc; - data = gctl_get_param(req, "data", &len); - if (data == NULL) - return; - if (len < 512 || (len % 512)) { - gctl_error(req, "Wrong request length"); - return; - } - cp = LIST_FIRST(&gp->consumer); - if (cp->acw == 0) { - error = g_access(cp, 0, 1, 0); - if (error == 0) - opened = 1; - } - if (!error) - error = g_mbr_modify(gp, ms, data, len); - if (error) - gctl_error(req, "conflict with open slices"); - if (!error) - error = g_write_data(cp, 0, data, len); - if (error) - gctl_error(req, "sector zero write failed"); - if (opened) - g_access(cp, 0, -1 , 0); - return; -} - -static struct g_class g_mbr_class = { - .name = MBR_CLASS_NAME, - .version = G_VERSION, - .taste = g_mbr_taste, - .dumpconf = g_mbr_dumpconf, - .ctlreq = g_mbr_config, - .ioctl = g_mbr_ioctl, -}; - -DECLARE_GEOM_CLASS(g_mbr_class, g_mbr); - -#define NDOSEXTPART 32 -struct g_mbrext_softc { - int type [NDOSEXTPART]; -}; - -static int -g_mbrext_start(struct bio *bp) -{ - struct g_provider *pp; - struct g_geom *gp; - struct g_mbrext_softc *mp; - struct g_slicer *gsp; - int idx; - - pp = bp->bio_to; - idx = pp->index; - gp = pp->geom; - gsp = gp->softc; - mp = gsp->softc; - if (bp->bio_cmd == BIO_GETATTR) { - if (g_handleattr_int(bp, "MBR::type", mp->type[idx])) - return (1); - } - return (0); -} - -static void -g_mbrext_dumpconf(struct sbuf *sb, const char *indent, struct g_geom *gp, struct g_consumer *cp __unused, struct g_provider *pp) -{ - struct g_mbrext_softc *mp; - struct g_slicer *gsp; - - g_slice_dumpconf(sb, indent, gp, cp, pp); - gsp = gp->softc; - mp = gsp->softc; - if (pp != NULL) { - if (indent == NULL) - sbuf_printf(sb, " ty %d", mp->type[pp->index]); - else - sbuf_printf(sb, "%s%d\n", indent, - mp->type[pp->index]); - } -} - -static struct g_geom * -g_mbrext_taste(struct g_class *mp, struct g_provider *pp, int insist __unused) -{ - struct g_geom *gp; - struct g_consumer *cp; - int error, i, slice; - struct g_mbrext_softc *ms; - off_t off; - u_char *buf; - struct dos_partition dp[4]; - u_int fwsectors, sectorsize; - - g_trace(G_T_TOPOLOGY, "g_mbrext_taste(%s,%s)", mp->name, pp->name); - g_topology_assert(); - if (strcmp(pp->geom->class->name, MBR_CLASS_NAME)) - return (NULL); - gp = g_slice_new(mp, NDOSEXTPART, pp, &cp, &ms, sizeof *ms, - g_mbrext_start); - if (gp == NULL) - return (NULL); - g_topology_unlock(); - off = 0; - slice = 0; - do { - error = g_getattr("MBR::type", cp, &i); - if (error || (i != DOSPTYP_EXT && i != DOSPTYP_EXTLBA)) - break; - error = g_getattr("GEOM::fwsectors", cp, &fwsectors); - if (error) - fwsectors = 17; - sectorsize = cp->provider->sectorsize; - if (sectorsize != 512) - break; - for (;;) { - buf = g_read_data(cp, off, sectorsize, NULL); - if (buf == NULL) - break; - if (buf[0x1fe] != 0x55 && buf[0x1ff] != 0xaa) { - g_free(buf); - break; - } - for (i = 0; i < NDOSPART; i++) - dos_partition_dec( - buf + DOSPARTOFF + - i * sizeof(struct dos_partition), dp + i); - g_free(buf); - if (0 && bootverbose) { - printf("MBREXT Slice %d on %s:\n", - slice + 5, gp->name); - g_mbr_print(0, dp); - g_mbr_print(1, dp + 1); - } - if ((dp[0].dp_flag & 0x7f) == 0 && - dp[0].dp_size != 0 && dp[0].dp_typ != 0) { - g_topology_lock(); - g_slice_config(gp, slice, G_SLICE_CONFIG_SET, - (((off_t)dp[0].dp_start) << 9ULL) + off, - ((off_t)dp[0].dp_size) << 9ULL, - sectorsize, - "%*.*s%d", - (int)strlen(gp->name) - 1, - (int)strlen(gp->name) - 1, - gp->name, - slice + 5); - g_topology_unlock(); - ms->type[slice] = dp[0].dp_typ; - slice++; - } - if (dp[1].dp_flag != 0) - break; - if (dp[1].dp_typ != DOSPTYP_EXT && - dp[1].dp_typ != DOSPTYP_EXTLBA) - break; - if (dp[1].dp_size == 0) - break; - off = ((off_t)dp[1].dp_start) << 9ULL; - } - break; - } while (0); - g_topology_lock(); - g_access(cp, -1, 0, 0); - if (LIST_EMPTY(&gp->provider)) { - g_slice_spoiled(cp); - return (NULL); - } - return (gp); -} - - -static struct g_class g_mbrext_class = { - .name = MBREXT_CLASS_NAME, - .version = G_VERSION, - .taste = g_mbrext_taste, - .dumpconf = g_mbrext_dumpconf, -}; - -DECLARE_GEOM_CLASS(g_mbrext_class, g_mbrext); -MODULE_VERSION(geom_mbr, 0); diff --git a/sys/geom/geom_mbr_enc.c b/sys/geom/geom_mbr_enc.c deleted file mode 100644 index 2f78086ecec..00000000000 --- a/sys/geom/geom_mbr_enc.c +++ /dev/null @@ -1,74 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2003 Poul-Henning Kamp - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -/* Functions to encode or decode struct dos_partition into a bytestream - * of correct endianness and packing. These functions do no validation - * or sanity checking, they only pack/unpack the fields correctly. - * - * NB! This file must be usable both in kernel and userland. - */ - -#include - -#include -#include -#include - -void -dos_partition_dec(void const *pp, struct dos_partition *d) -{ - unsigned char const *p = pp; - - d->dp_flag = p[0]; - d->dp_shd = p[1]; - d->dp_ssect = p[2]; - d->dp_scyl = p[3]; - d->dp_typ = p[4]; - d->dp_ehd = p[5]; - d->dp_esect = p[6]; - d->dp_ecyl = p[7]; - d->dp_start = le32dec(p + 8); - d->dp_size = le32dec(p + 12); -} - -void -dos_partition_enc(void *pp, struct dos_partition *d) -{ - unsigned char *p = pp; - - p[0] = d->dp_flag; - p[1] = d->dp_shd; - p[2] = d->dp_ssect; - p[3] = d->dp_scyl; - p[4] = d->dp_typ; - p[5] = d->dp_ehd; - p[6] = d->dp_esect; - p[7] = d->dp_ecyl; - le32enc(p + 8, d->dp_start); - le32enc(p + 12, d->dp_size); -} diff --git a/sys/geom/geom_sunlabel.c b/sys/geom/geom_sunlabel.c deleted file mode 100644 index cb15e6d215e..00000000000 --- a/sys/geom/geom_sunlabel.c +++ /dev/null @@ -1,336 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-3-Clause - * - * Copyright (c) 2002 Poul-Henning Kamp - * Copyright (c) 2002 Networks Associates Technology, Inc. - * All rights reserved. - * - * This software was developed for the FreeBSD Project by Poul-Henning Kamp - * and NAI Labs, the Security Research Division of Network Associates, Inc. - * under DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the - * DARPA CHATS research program. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The names of the authors may not be used to endorse or promote - * products derived from this software without specific prior written - * permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -FEATURE(geom_sunlabel, "GEOM Sun/Solaris partitioning support"); - -#define SUNLABEL_CLASS_NAME "SUN" - -struct g_sunlabel_softc { - int sectorsize; - int nheads; - int nsects; - int nalt; - u_char labelsum[16]; -}; - -static int g_sunlabel_once = 0; - -static int -g_sunlabel_modify(struct g_geom *gp, struct g_sunlabel_softc *ms, u_char *sec0) -{ - int i, error; - u_int u, v, csize; - struct sun_disklabel sl; - MD5_CTX md5sum; - - error = sunlabel_dec(sec0, &sl); - if (error) - return (error); - - csize = sl.sl_ntracks * sl.sl_nsectors; - - for (i = 0; i < SUN_NPART; i++) { - v = sl.sl_part[i].sdkp_cyloffset; - u = sl.sl_part[i].sdkp_nsectors; - error = g_slice_config(gp, i, G_SLICE_CONFIG_CHECK, - ((off_t)v * csize) << 9ULL, - ((off_t)u) << 9ULL, - ms->sectorsize, - "%s%c", gp->name, 'a' + i); - if (error) - return (error); - } - for (i = 0; i < SUN_NPART; i++) { - v = sl.sl_part[i].sdkp_cyloffset; - u = sl.sl_part[i].sdkp_nsectors; - g_slice_config(gp, i, G_SLICE_CONFIG_SET, - ((off_t)v * csize) << 9ULL, - ((off_t)u) << 9ULL, - ms->sectorsize, - "%s%c", gp->name, 'a' + i); - } - ms->nalt = sl.sl_acylinders; - ms->nheads = sl.sl_ntracks; - ms->nsects = sl.sl_nsectors; - - /* - * Calculate MD5 from the first sector and use it for avoiding - * recursive labels creation. - */ - MD5Init(&md5sum); - MD5Update(&md5sum, sec0, ms->sectorsize); - MD5Final(ms->labelsum, &md5sum); - - return (0); -} - -static void -g_sunlabel_hotwrite(void *arg, int flag) -{ - struct bio *bp; - struct g_geom *gp; - struct g_slicer *gsp; - struct g_slice *gsl; - struct g_sunlabel_softc *ms; - u_char *p; - int error; - - KASSERT(flag != EV_CANCEL, ("g_sunlabel_hotwrite cancelled")); - bp = arg; - gp = bp->bio_to->geom; - gsp = gp->softc; - ms = gsp->softc; - gsl = &gsp->slices[bp->bio_to->index]; - /* - * XXX: For all practical purposes, this whould be equvivalent to - * XXX: "p = (u_char *)bp->bio_data;" because the label is always - * XXX: in the first sector and we refuse sectors smaller than the - * XXX: label. - */ - p = (u_char *)bp->bio_data - (bp->bio_offset + gsl->offset); - - error = g_sunlabel_modify(gp, ms, p); - if (error) { - g_io_deliver(bp, EPERM); - return; - } - g_slice_finish_hot(bp); -} - -static void -g_sunlabel_dumpconf(struct sbuf *sb, const char *indent, struct g_geom *gp, struct g_consumer *cp __unused, struct g_provider *pp) -{ - struct g_slicer *gsp; - struct g_sunlabel_softc *ms; - - gsp = gp->softc; - ms = gsp->softc; - g_slice_dumpconf(sb, indent, gp, cp, pp); - if (indent == NULL) { - sbuf_printf(sb, " sc %u hd %u alt %u", - ms->nsects, ms->nheads, ms->nalt); - } -} - -struct g_hh01 { - struct g_geom *gp; - struct g_sunlabel_softc *ms; - u_char *label; - int error; -}; - -static void -g_sunlabel_callconfig(void *arg, int flag) -{ - struct g_hh01 *hp; - - hp = arg; - hp->error = g_sunlabel_modify(hp->gp, hp->ms, hp->label); - if (!hp->error) - hp->error = g_write_data(LIST_FIRST(&hp->gp->consumer), - 0, hp->label, SUN_SIZE); -} - -/* - * NB! curthread is user process which GCTL'ed. - */ -static void -g_sunlabel_config(struct gctl_req *req, struct g_class *mp, const char *verb) -{ - u_char *label; - int error, i; - struct g_hh01 h0h0; - struct g_slicer *gsp; - struct g_geom *gp; - struct g_consumer *cp; - - g_topology_assert(); - gp = gctl_get_geom(req, mp, "geom"); - if (gp == NULL) - return; - cp = LIST_FIRST(&gp->consumer); - gsp = gp->softc; - if (!strcmp(verb, "write label")) { - label = gctl_get_paraml(req, "label", SUN_SIZE); - if (label == NULL) - return; - h0h0.gp = gp; - h0h0.ms = gsp->softc; - h0h0.label = label; - h0h0.error = -1; - /* XXX: Does this reference register with our selfdestruct code ? */ - error = g_access(cp, 1, 1, 1); - if (error) { - gctl_error(req, "could not access consumer"); - return; - } - g_sunlabel_callconfig(&h0h0, 0); - g_access(cp, -1, -1, -1); - } else if (!strcmp(verb, "write bootcode")) { - label = gctl_get_paraml(req, "bootcode", SUN_BOOTSIZE); - if (label == NULL) - return; - /* XXX: Does this reference register with our selfdestruct code ? */ - error = g_access(cp, 1, 1, 1); - if (error) { - gctl_error(req, "could not access consumer"); - return; - } - for (i = 0; i < SUN_NPART; i++) { - if (gsp->slices[i].length <= SUN_BOOTSIZE) - continue; - g_write_data(cp, - gsp->slices[i].offset + SUN_SIZE, label + SUN_SIZE, - SUN_BOOTSIZE - SUN_SIZE); - } - g_access(cp, -1, -1, -1); - } else { - gctl_error(req, "Unknown verb parameter"); - } -} - -static int -g_sunlabel_start(struct bio *bp) -{ - struct g_sunlabel_softc *mp; - struct g_slicer *gsp; - - gsp = bp->bio_to->geom->softc; - mp = gsp->softc; - if (bp->bio_cmd == BIO_GETATTR) { - if (g_handleattr(bp, "SUN::labelsum", mp->labelsum, - sizeof(mp->labelsum))) - return (1); - } - return (0); -} - -static struct g_geom * -g_sunlabel_taste(struct g_class *mp, struct g_provider *pp, int flags) -{ - struct g_geom *gp; - struct g_consumer *cp; - struct g_sunlabel_softc *ms; - struct g_slicer *gsp; - u_char *buf, hash[16]; - MD5_CTX md5sum; - int error; - - g_trace(G_T_TOPOLOGY, "g_sunlabel_taste(%s,%s)", mp->name, pp->name); - g_topology_assert(); - if (flags == G_TF_NORMAL && - !strcmp(pp->geom->class->name, SUNLABEL_CLASS_NAME)) - return (NULL); - gp = g_slice_new(mp, 8, pp, &cp, &ms, sizeof *ms, g_sunlabel_start); - if (gp == NULL) - return (NULL); - gsp = gp->softc; - do { - ms->sectorsize = cp->provider->sectorsize; - if (ms->sectorsize < 512) - break; - g_topology_unlock(); - buf = g_read_data(cp, 0, ms->sectorsize, NULL); - g_topology_lock(); - if (buf == NULL) - break; - - /* - * Calculate MD5 from the first sector and use it for avoiding - * recursive labels creation. - */ - MD5Init(&md5sum); - MD5Update(&md5sum, buf, ms->sectorsize); - MD5Final(ms->labelsum, &md5sum); - - error = g_getattr("SUN::labelsum", cp, &hash); - if (!error && !bcmp(ms->labelsum, hash, sizeof(hash))) { - g_free(buf); - break; - } - - g_sunlabel_modify(gp, ms, buf); - g_free(buf); - - break; - } while (0); - g_access(cp, -1, 0, 0); - if (LIST_EMPTY(&gp->provider)) { - g_slice_spoiled(cp); - return (NULL); - } - g_slice_conf_hot(gp, 0, 0, SUN_SIZE, - G_SLICE_HOT_ALLOW, G_SLICE_HOT_DENY, G_SLICE_HOT_CALL); - gsp->hot = g_sunlabel_hotwrite; - if (!g_sunlabel_once) { - g_sunlabel_once = 1; - printf( - "WARNING: geom_sunlabel (geom %s) is deprecated, " - "use gpart instead.\n", gp->name); - } - return (gp); -} - -static struct g_class g_sunlabel_class = { - .name = SUNLABEL_CLASS_NAME, - .version = G_VERSION, - .taste = g_sunlabel_taste, - .ctlreq = g_sunlabel_config, - .dumpconf = g_sunlabel_dumpconf, -}; - -DECLARE_GEOM_CLASS(g_sunlabel_class, g_sunlabel); -MODULE_VERSION(geom_sunlabel, 0); diff --git a/sys/geom/geom_sunlabel_enc.c b/sys/geom/geom_sunlabel_enc.c deleted file mode 100644 index 3e93010a9ff..00000000000 --- a/sys/geom/geom_sunlabel_enc.c +++ /dev/null @@ -1,183 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2003 Jake Burkholder - * Copyright (c) 2003 Poul-Henning Kamp - * Copyright (c) 2004,2005 Joerg Wunsch - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ -/* Functions to encode or decode struct sun_disklabel into a bytestream - * of correct endianness and packing. - * - * NB! This file must be usable both in kernel and userland. - */ - -#include - -#include -#include -#include -#include -#ifdef _KERNEL -#include -#else -#include -#endif - -#define SL_TEXT 0x0 -#define SL_TEXT_SIZEOF 0x80 -#define SL_VTOC_VERS 0x80 -#define SL_VTOC_VOLNAME 0x84 -#define SL_VTOC_NPART 0x8c -#define SL_VTOC_MAP 0x8e -#define SL_VTOC_SANITY 0xbc -#define SL_RPM 0x1a4 -#define SL_PCYLINDERS 0x1a6 -#define SL_SPARESPERCYL 0x1a8 -#define SL_INTERLEAVE 0x1ae -#define SL_NCYLINDERS 0x1b0 -#define SL_ACYLINDERS 0x1b2 -#define SL_NTRACKS 0x1b4 -#define SL_NSECTORS 0x1b6 -#define SL_PART 0x1bc -#define SL_MAGIC 0x1fc -#define SL_CKSUM 0x1fe - -#define SDKP_CYLOFFSET 0 -#define SDKP_NSECTORS 0x4 -#define SDKP_SIZEOF 0x8 /* size of a partition entry */ - -#define SVTOC_TAG 0 -#define SVTOC_FLAG 0x2 -#define SVTOC_SIZEOF 0x4 /* size of a VTOC tag/flag entry */ - -/* - * Decode the relevant fields of a sun disk label, and return zero if the - * magic and checksum works out OK. - */ -int -sunlabel_dec(void const *pp, struct sun_disklabel *sl) -{ - const uint8_t *p; - size_t i; - u_int u; - uint32_t vtocsane; - uint16_t npart; - - p = pp; - for (i = 0; i < sizeof(sl->sl_text); i++) - sl->sl_text[i] = p[SL_TEXT + i]; - sl->sl_rpm = be16dec(p + SL_RPM); - sl->sl_pcylinders = be16dec(p + SL_PCYLINDERS); - sl->sl_sparespercyl = be16dec(p + SL_SPARESPERCYL); - sl->sl_interleave = be16dec(p + SL_INTERLEAVE); - sl->sl_ncylinders = be16dec(p + SL_NCYLINDERS); - sl->sl_acylinders = be16dec(p + SL_ACYLINDERS); - sl->sl_ntracks = be16dec(p + SL_NTRACKS); - sl->sl_nsectors = be16dec(p + SL_NSECTORS); - for (i = 0; i < SUN_NPART; i++) { - sl->sl_part[i].sdkp_cyloffset = be32dec(p + SL_PART + - (i * SDKP_SIZEOF) + SDKP_CYLOFFSET); - sl->sl_part[i].sdkp_nsectors = be32dec(p + SL_PART + - (i * SDKP_SIZEOF) + SDKP_NSECTORS); - } - sl->sl_magic = be16dec(p + SL_MAGIC); - vtocsane = be32dec(p + SL_VTOC_SANITY); - npart = be16dec(p + SL_VTOC_NPART); - if (vtocsane == SUN_VTOC_SANE && npart == SUN_NPART) { - /* - * Seems we've got SVR4-compatible VTOC information - * as well, decode it. - */ - sl->sl_vtoc_sane = vtocsane; - sl->sl_vtoc_vers = be32dec(p + SL_VTOC_VERS); - memcpy(sl->sl_vtoc_volname, p + SL_VTOC_VOLNAME, - SUN_VOLNAME_LEN); - sl->sl_vtoc_nparts = SUN_NPART; - for (i = 0; i < SUN_NPART; i++) { - sl->sl_vtoc_map[i].svtoc_tag = be16dec(p + - SL_VTOC_MAP + (i * SVTOC_SIZEOF) + SVTOC_TAG); - sl->sl_vtoc_map[i].svtoc_flag = be16dec(p + - SL_VTOC_MAP + (i * SVTOC_SIZEOF) + SVTOC_FLAG); - } - } - for (i = u = 0; i < SUN_SIZE; i += 2) - u ^= be16dec(p + i); - if (u == 0 && sl->sl_magic == SUN_DKMAGIC) - return (0); - else - return (EINVAL); -} - -/* - * Encode the relevant fields into a sun disklabel, compute new checksum. - */ -void -sunlabel_enc(void *pp, struct sun_disklabel *sl) -{ - uint8_t *p; - size_t i; - u_int u; - - p = pp; - for (i = 0; i < SL_TEXT_SIZEOF; i++) - p[SL_TEXT + i] = sl->sl_text[i]; - be16enc(p + SL_RPM, sl->sl_rpm); - be16enc(p + SL_PCYLINDERS, sl->sl_pcylinders); - be16enc(p + SL_SPARESPERCYL, sl->sl_sparespercyl); - be16enc(p + SL_INTERLEAVE, sl->sl_interleave); - be16enc(p + SL_NCYLINDERS, sl->sl_ncylinders); - be16enc(p + SL_ACYLINDERS, sl->sl_acylinders); - be16enc(p + SL_NTRACKS, sl->sl_ntracks); - be16enc(p + SL_NSECTORS, sl->sl_nsectors); - for (i = 0; i < SUN_NPART; i++) { - be32enc(p + SL_PART + (i * SDKP_SIZEOF) + SDKP_CYLOFFSET, - sl->sl_part[i].sdkp_cyloffset); - be32enc(p + SL_PART + (i * SDKP_SIZEOF) + SDKP_NSECTORS, - sl->sl_part[i].sdkp_nsectors); - } - be16enc(p + SL_MAGIC, sl->sl_magic); - if (sl->sl_vtoc_sane == SUN_VTOC_SANE - && sl->sl_vtoc_nparts == SUN_NPART) { - /* - * Write SVR4-compatible VTOC elements. - */ - be32enc(p + SL_VTOC_VERS, sl->sl_vtoc_vers); - be32enc(p + SL_VTOC_SANITY, SUN_VTOC_SANE); - memcpy(p + SL_VTOC_VOLNAME, sl->sl_vtoc_volname, - SUN_VOLNAME_LEN); - be16enc(p + SL_VTOC_NPART, SUN_NPART); - for (i = 0; i < SUN_NPART; i++) { - be16enc(p + SL_VTOC_MAP + (i * SVTOC_SIZEOF) - + SVTOC_TAG, - sl->sl_vtoc_map[i].svtoc_tag); - be16enc(p + SL_VTOC_MAP + (i * SVTOC_SIZEOF) - + SVTOC_FLAG, - sl->sl_vtoc_map[i].svtoc_flag); - } - } - for (i = u = 0; i < SUN_SIZE; i += 2) - u ^= be16dec(p + i); - be16enc(p + SL_CKSUM, u); -} diff --git a/sys/geom/geom_vol_ffs.c b/sys/geom/geom_vol_ffs.c deleted file mode 100644 index 9fa9ff72b5c..00000000000 --- a/sys/geom/geom_vol_ffs.c +++ /dev/null @@ -1,166 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2002, 2003 Gordon Tetlow - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include -#include - -FEATURE(geom_vol, "GEOM support for volume names from UFS superblock"); - -#define VOL_FFS_CLASS_NAME "VOL_FFS" - -static int superblocks[] = SBLOCKSEARCH; -static int g_vol_ffs_once; - -struct g_vol_ffs_softc { - char * vol; -}; - -static int -g_vol_ffs_start(struct bio *bp __unused) -{ - return(0); -} - -static struct g_geom * -g_vol_ffs_taste(struct g_class *mp, struct g_provider *pp, int flags) -{ - struct g_geom *gp; - struct g_consumer *cp; - struct g_vol_ffs_softc *ms; - int sb, superblock; - struct fs *fs; - - g_trace(G_T_TOPOLOGY, "vol_taste(%s,%s)", mp->name, pp->name); - g_topology_assert(); - - /* - * XXX This is a really weak way to make sure we don't recurse. - * Probably ought to use BIO_GETATTR to check for this. - */ - if (flags == G_TF_NORMAL && - !strcmp(pp->geom->class->name, VOL_FFS_CLASS_NAME)) - return (NULL); - - gp = g_slice_new(mp, 1, pp, &cp, &ms, sizeof(*ms), g_vol_ffs_start); - if (gp == NULL) - return (NULL); - g_topology_unlock(); - /* - * Walk through the standard places that superblocks hide and look - * for UFS magic. If we find magic, then check that the size in the - * superblock corresponds to the size of the underlying provider. - * Finally, look for a volume label and create an appropriate - * provider based on that. - */ - for (sb=0; (superblock = superblocks[sb]) != -1; sb++) { - /* - * Take care not to issue an invalid I/O request. The - * offset and size of the superblock candidate must be - * multiples of the provider's sector size, otherwise an - * FFS can't exist on the provider anyway. - */ - if (superblock % cp->provider->sectorsize != 0 || - SBLOCKSIZE % cp->provider->sectorsize != 0) - continue; - - fs = (struct fs *) g_read_data(cp, superblock, - SBLOCKSIZE, NULL); - if (fs == NULL) - continue; - /* Check for magic and make sure things are the right size */ - if (fs->fs_magic == FS_UFS1_MAGIC) { - if (fs->fs_old_size * fs->fs_fsize != - (int32_t) pp->mediasize) { - g_free(fs); - continue; - } - } else if (fs->fs_magic == FS_UFS2_MAGIC) { - if (fs->fs_size * fs->fs_fsize != - (int64_t) pp->mediasize) { - g_free(fs); - continue; - } - } else { - g_free(fs); - continue; - } - /* Check for volume label */ - if (fs->fs_volname[0] == '\0') { - g_free(fs); - continue; - } - /* XXX We need to check for namespace conflicts. */ - /* XXX How do you handle a mirror set? */ - /* XXX We don't validate the volume name. */ - g_topology_lock(); - /* Alright, we have a label and a volume name, reconfig. */ - g_slice_config(gp, 0, G_SLICE_CONFIG_SET, (off_t) 0, - pp->mediasize, pp->sectorsize, "vol/%s", - fs->fs_volname); - g_free(fs); - g_topology_unlock(); - break; - } - g_topology_lock(); - g_access(cp, -1, 0, 0); - if (LIST_EMPTY(&gp->provider)) { - g_slice_spoiled(cp); - return (NULL); - } - if (!g_vol_ffs_once) { - g_vol_ffs_once = 1; - printf( - "WARNING: geom_vol_Ffs (geom %s) is deprecated, " - "use glabel instead.\n", gp->name); - } - return (gp); -} - -static struct g_class g_vol_ffs_class = { - .name = VOL_FFS_CLASS_NAME, - .version = G_VERSION, - .taste = g_vol_ffs_taste, -}; - -DECLARE_GEOM_CLASS(g_vol_ffs_class, g_vol_ffs); -MODULE_VERSION(geom_vol_ffs, 0); diff --git a/sys/geom/part/g_part_vtoc8.c b/sys/geom/part/g_part_vtoc8.c deleted file mode 100644 index 531f9c6ea83..00000000000 --- a/sys/geom/part/g_part_vtoc8.c +++ /dev/null @@ -1,601 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2008 Marcel Moolenaar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "g_part_if.h" - -FEATURE(geom_part_vtoc8, "GEOM partitioning class for SMI VTOC8 disk labels"); - -struct g_part_vtoc8_table { - struct g_part_table base; - struct vtoc8 vtoc; - uint32_t secpercyl; -}; - -static int g_part_vtoc8_add(struct g_part_table *, struct g_part_entry *, - struct g_part_parms *); -static int g_part_vtoc8_create(struct g_part_table *, struct g_part_parms *); -static int g_part_vtoc8_destroy(struct g_part_table *, struct g_part_parms *); -static void g_part_vtoc8_dumpconf(struct g_part_table *, - struct g_part_entry *, struct sbuf *, const char *); -static int g_part_vtoc8_dumpto(struct g_part_table *, struct g_part_entry *); -static int g_part_vtoc8_modify(struct g_part_table *, struct g_part_entry *, - struct g_part_parms *); -static const char *g_part_vtoc8_name(struct g_part_table *, - struct g_part_entry *, char *, size_t); -static int g_part_vtoc8_probe(struct g_part_table *, struct g_consumer *); -static int g_part_vtoc8_read(struct g_part_table *, struct g_consumer *); -static const char *g_part_vtoc8_type(struct g_part_table *, - struct g_part_entry *, char *, size_t); -static int g_part_vtoc8_write(struct g_part_table *, struct g_consumer *); -static int g_part_vtoc8_resize(struct g_part_table *, struct g_part_entry *, - struct g_part_parms *); - -static kobj_method_t g_part_vtoc8_methods[] = { - KOBJMETHOD(g_part_add, g_part_vtoc8_add), - KOBJMETHOD(g_part_create, g_part_vtoc8_create), - KOBJMETHOD(g_part_destroy, g_part_vtoc8_destroy), - KOBJMETHOD(g_part_dumpconf, g_part_vtoc8_dumpconf), - KOBJMETHOD(g_part_dumpto, g_part_vtoc8_dumpto), - KOBJMETHOD(g_part_modify, g_part_vtoc8_modify), - KOBJMETHOD(g_part_resize, g_part_vtoc8_resize), - KOBJMETHOD(g_part_name, g_part_vtoc8_name), - KOBJMETHOD(g_part_probe, g_part_vtoc8_probe), - KOBJMETHOD(g_part_read, g_part_vtoc8_read), - KOBJMETHOD(g_part_type, g_part_vtoc8_type), - KOBJMETHOD(g_part_write, g_part_vtoc8_write), - { 0, 0 } -}; - -static struct g_part_scheme g_part_vtoc8_scheme = { - "VTOC8", - g_part_vtoc8_methods, - sizeof(struct g_part_vtoc8_table), - .gps_entrysz = sizeof(struct g_part_entry), - .gps_minent = VTOC8_NPARTS, - .gps_maxent = VTOC8_NPARTS, -}; -G_PART_SCHEME_DECLARE(g_part_vtoc8); -MODULE_VERSION(geom_part_vtoc8, 0); - -static int -vtoc8_parse_type(const char *type, uint16_t *tag) -{ - const char *alias; - char *endp; - long lt; - - if (type[0] == '!') { - lt = strtol(type + 1, &endp, 0); - if (type[1] == '\0' || *endp != '\0' || lt <= 0 || - lt >= 65536) - return (EINVAL); - *tag = (uint16_t)lt; - return (0); - } - alias = g_part_alias_name(G_PART_ALIAS_MIDNIGHTBSD_NANDFS); - if (!strcasecmp(type, alias)) { - *tag = VTOC_TAG_MIDNIGHTBSD_NANDFS; - return (0); - } - alias = g_part_alias_name(G_PART_ALIAS_MIDNIGHTBSD_SWAP); - if (!strcasecmp(type, alias)) { - *tag = VTOC_TAG_MIDNIGHTBSD_SWAP; - return (0); - } - alias = g_part_alias_name(G_PART_ALIAS_MIDNIGHTBSD_UFS); - if (!strcasecmp(type, alias)) { - *tag = VTOC_TAG_MIDNIGHTBSD_UFS; - return (0); - } - alias = g_part_alias_name(G_PART_ALIAS_MIDNIGHTBSD_VINUM); - if (!strcasecmp(type, alias)) { - *tag = VTOC_TAG_MIDNIGHTBSD_VINUM; - return (0); - } - alias = g_part_alias_name(G_PART_ALIAS_MIDNIGHTBSD_ZFS); - if (!strcasecmp(type, alias)) { - *tag = VTOC_TAG_MIDNIGHTBSD_ZFS; - return (0); - } - return (EINVAL); -} - -static int -vtoc8_align(struct g_part_vtoc8_table *table, uint64_t *start, uint64_t *size) -{ - - if (*size < table->secpercyl) - return (EINVAL); - if (start != NULL && (*start % table->secpercyl)) { - *size += (*start % table->secpercyl) - table->secpercyl; - *start -= (*start % table->secpercyl) - table->secpercyl; - } - if (*size % table->secpercyl) - *size -= (*size % table->secpercyl); - if (*size < table->secpercyl) - return (EINVAL); - return (0); -} - -static int -g_part_vtoc8_add(struct g_part_table *basetable, struct g_part_entry *entry, - struct g_part_parms *gpp) -{ - struct g_part_vtoc8_table *table; - int error, index; - uint64_t start, size; - uint16_t tag; - - if (gpp->gpp_parms & G_PART_PARM_LABEL) - return (EINVAL); - - error = vtoc8_parse_type(gpp->gpp_type, &tag); - if (error) - return (error); - - table = (struct g_part_vtoc8_table *)basetable; - index = entry->gpe_index - 1; - start = gpp->gpp_start; - size = gpp->gpp_size; - if (vtoc8_align(table, &start, &size) != 0) - return (EINVAL); - - KASSERT(entry->gpe_start <= start, (__func__)); - KASSERT(entry->gpe_end >= start + size - 1, (__func__)); - entry->gpe_start = start; - entry->gpe_end = start + size - 1; - - be16enc(&table->vtoc.part[index].tag, tag); - be16enc(&table->vtoc.part[index].flag, 0); - be32enc(&table->vtoc.timestamp[index], 0); - be32enc(&table->vtoc.map[index].cyl, start / table->secpercyl); - be32enc(&table->vtoc.map[index].nblks, size); - return (0); -} - -static int -g_part_vtoc8_create(struct g_part_table *basetable, struct g_part_parms *gpp) -{ - struct g_provider *pp; - struct g_part_entry *entry; - struct g_part_vtoc8_table *table; - uint64_t msize; - uint32_t acyls, ncyls, pcyls; - - pp = gpp->gpp_provider; - - if (pp->sectorsize < sizeof(struct vtoc8)) - return (ENOSPC); - if (pp->sectorsize > sizeof(struct vtoc8)) - return (ENXIO); - - table = (struct g_part_vtoc8_table *)basetable; - - msize = MIN(pp->mediasize / pp->sectorsize, UINT32_MAX); - table->secpercyl = basetable->gpt_sectors * basetable->gpt_heads; - pcyls = msize / table->secpercyl; - acyls = 2; - ncyls = pcyls - acyls; - msize = ncyls * table->secpercyl; - - sprintf(table->vtoc.ascii, "MidnightBSD%lldM cyl %u alt %u hd %u sec %u", - (long long)(msize / 2048), ncyls, acyls, basetable->gpt_heads, - basetable->gpt_sectors); - be32enc(&table->vtoc.version, VTOC_VERSION); - be16enc(&table->vtoc.nparts, VTOC8_NPARTS); - be32enc(&table->vtoc.sanity, VTOC_SANITY); - be16enc(&table->vtoc.rpm, 3600); - be16enc(&table->vtoc.physcyls, pcyls); - be16enc(&table->vtoc.ncyls, ncyls); - be16enc(&table->vtoc.altcyls, acyls); - be16enc(&table->vtoc.nheads, basetable->gpt_heads); - be16enc(&table->vtoc.nsecs, basetable->gpt_sectors); - be16enc(&table->vtoc.magic, VTOC_MAGIC); - - basetable->gpt_first = 0; - basetable->gpt_last = msize - 1; - basetable->gpt_isleaf = 1; - - entry = g_part_new_entry(basetable, VTOC_RAW_PART + 1, - basetable->gpt_first, basetable->gpt_last); - entry->gpe_internal = 1; - be16enc(&table->vtoc.part[VTOC_RAW_PART].tag, VTOC_TAG_BACKUP); - be32enc(&table->vtoc.map[VTOC_RAW_PART].nblks, msize); - return (0); -} - -static int -g_part_vtoc8_destroy(struct g_part_table *basetable, struct g_part_parms *gpp) -{ - - /* Wipe the first sector to clear the partitioning. */ - basetable->gpt_smhead |= 1; - return (0); -} - -static void -g_part_vtoc8_dumpconf(struct g_part_table *basetable, - struct g_part_entry *entry, struct sbuf *sb, const char *indent) -{ - struct g_part_vtoc8_table *table; - - table = (struct g_part_vtoc8_table *)basetable; - if (indent == NULL) { - /* conftxt: libdisk compatibility */ - sbuf_printf(sb, " xs SUN sc %u hd %u alt %u", - be16dec(&table->vtoc.nsecs), be16dec(&table->vtoc.nheads), - be16dec(&table->vtoc.altcyls)); - } else if (entry != NULL) { - /* confxml: partition entry information */ - sbuf_printf(sb, "%s%u\n", indent, - be16dec(&table->vtoc.part[entry->gpe_index - 1].tag)); - } else { - /* confxml: scheme information */ - } -} - -static int -g_part_vtoc8_dumpto(struct g_part_table *basetable, - struct g_part_entry *entry) -{ - struct g_part_vtoc8_table *table; - uint16_t tag; - - /* - * Allow dumping to a swap partition or a partition that - * has no type. - */ - table = (struct g_part_vtoc8_table *)basetable; - tag = be16dec(&table->vtoc.part[entry->gpe_index - 1].tag); - return ((tag == 0 || tag == VTOC_TAG_MIDNIGHTBSD_SWAP || - tag == VTOC_TAG_SWAP) ? 1 : 0); -} - -static int -g_part_vtoc8_modify(struct g_part_table *basetable, - struct g_part_entry *entry, struct g_part_parms *gpp) -{ - struct g_part_vtoc8_table *table; - int error; - uint16_t tag; - - if (gpp->gpp_parms & G_PART_PARM_LABEL) - return (EINVAL); - - table = (struct g_part_vtoc8_table *)basetable; - if (gpp->gpp_parms & G_PART_PARM_TYPE) { - error = vtoc8_parse_type(gpp->gpp_type, &tag); - if (error) - return(error); - - be16enc(&table->vtoc.part[entry->gpe_index - 1].tag, tag); - } - return (0); -} - -static int -vtoc8_set_rawsize(struct g_part_table *basetable, struct g_provider *pp) -{ - struct g_part_vtoc8_table *table; - struct g_part_entry *baseentry; - off_t msize; - uint32_t acyls, ncyls, pcyls; - - table = (struct g_part_vtoc8_table *)basetable; - msize = MIN(pp->mediasize / pp->sectorsize, UINT32_MAX); - pcyls = msize / table->secpercyl; - if (pcyls > UINT16_MAX) - return (ERANGE); - acyls = be16dec(&table->vtoc.altcyls); - ncyls = pcyls - acyls; - msize = ncyls * table->secpercyl; - basetable->gpt_last = msize - 1; - - bzero(table->vtoc.ascii, sizeof(table->vtoc.ascii)); - sprintf(table->vtoc.ascii, "MidnightBSD%lldM cyl %u alt %u hd %u sec %u", - (long long)(msize / 2048), ncyls, acyls, basetable->gpt_heads, - basetable->gpt_sectors); - be16enc(&table->vtoc.physcyls, pcyls); - be16enc(&table->vtoc.ncyls, ncyls); - be32enc(&table->vtoc.map[VTOC_RAW_PART].nblks, msize); - if (be32dec(&table->vtoc.sanity) == VTOC_SANITY) - be16enc(&table->vtoc.part[VTOC_RAW_PART].tag, VTOC_TAG_BACKUP); - LIST_FOREACH(baseentry, &basetable->gpt_entry, gpe_entry) { - if (baseentry->gpe_index == VTOC_RAW_PART + 1) { - baseentry->gpe_end = basetable->gpt_last; - return (0); - } - } - return (ENXIO); -} - -static int -g_part_vtoc8_resize(struct g_part_table *basetable, - struct g_part_entry *entry, struct g_part_parms *gpp) -{ - struct g_part_vtoc8_table *table; - struct g_provider *pp; - uint64_t size; - - if (entry == NULL) { - pp = LIST_FIRST(&basetable->gpt_gp->consumer)->provider; - return (vtoc8_set_rawsize(basetable, pp)); - } - table = (struct g_part_vtoc8_table *)basetable; - size = gpp->gpp_size; - if (vtoc8_align(table, NULL, &size) != 0) - return (EINVAL); - /* XXX: prevent unexpected shrinking. */ - pp = entry->gpe_pp; - if ((g_debugflags & G_F_FOOTSHOOTING) == 0 && size < gpp->gpp_size && - pp->mediasize / pp->sectorsize > size) - return (EBUSY); - entry->gpe_end = entry->gpe_start + size - 1; - be32enc(&table->vtoc.map[entry->gpe_index - 1].nblks, size); - - return (0); -} - -static const char * -g_part_vtoc8_name(struct g_part_table *table, struct g_part_entry *baseentry, - char *buf, size_t bufsz) -{ - - snprintf(buf, bufsz, "%c", 'a' + baseentry->gpe_index - 1); - return (buf); -} - -static int -g_part_vtoc8_probe(struct g_part_table *table, struct g_consumer *cp) -{ - struct g_provider *pp; - u_char *buf; - int error, ofs, res; - uint16_t cksum, magic; - - pp = cp->provider; - - /* Sanity-check the provider. */ - if (pp->sectorsize != sizeof(struct vtoc8)) - return (ENOSPC); - - /* Check that there's a disklabel. */ - buf = g_read_data(cp, 0, pp->sectorsize, &error); - if (buf == NULL) - return (error); - - res = ENXIO; /* Assume mismatch */ - - /* Check the magic */ - magic = be16dec(buf + offsetof(struct vtoc8, magic)); - if (magic != VTOC_MAGIC) - goto out; - - /* Check the sum */ - cksum = 0; - for (ofs = 0; ofs < sizeof(struct vtoc8); ofs += 2) - cksum ^= be16dec(buf + ofs); - if (cksum != 0) - goto out; - - res = G_PART_PROBE_PRI_NORM; - - out: - g_free(buf); - return (res); -} - -static int -g_part_vtoc8_read(struct g_part_table *basetable, struct g_consumer *cp) -{ - struct g_provider *pp; - struct g_part_vtoc8_table *table; - struct g_part_entry *entry; - u_char *buf; - off_t chs, msize; - uint64_t offset, size; - u_int cyls, heads, sectors; - int error, index, withtags; - uint16_t tag; - - pp = cp->provider; - buf = g_read_data(cp, 0, pp->sectorsize, &error); - if (buf == NULL) - return (error); - - table = (struct g_part_vtoc8_table *)basetable; - bcopy(buf, &table->vtoc, sizeof(table->vtoc)); - g_free(buf); - - msize = MIN(pp->mediasize / pp->sectorsize, UINT32_MAX); - sectors = be16dec(&table->vtoc.nsecs); - if (sectors < 1) - goto invalid_label; - if (sectors != basetable->gpt_sectors && !basetable->gpt_fixgeom) { - g_part_geometry_heads(msize, sectors, &chs, &heads); - if (chs != 0) { - basetable->gpt_sectors = sectors; - basetable->gpt_heads = heads; - } - } - - heads = be16dec(&table->vtoc.nheads); - if (heads < 1) - goto invalid_label; - if (heads != basetable->gpt_heads && !basetable->gpt_fixgeom) - basetable->gpt_heads = heads; - /* - * Except for ATA disks > 32GB, Solaris uses the native geometry - * as reported by the target for the labels while da(4) typically - * uses a synthetic one so we don't complain too loudly if these - * geometries don't match. - */ - if (bootverbose && (sectors != basetable->gpt_sectors || - heads != basetable->gpt_heads)) - printf("GEOM: %s: geometry does not match VTOC8 label " - "(label: %uh,%us GEOM: %uh,%us).\n", pp->name, heads, - sectors, basetable->gpt_heads, basetable->gpt_sectors); - - table->secpercyl = heads * sectors; - cyls = be16dec(&table->vtoc.ncyls); - chs = cyls * table->secpercyl; - if (chs < 1 || chs > msize) - goto invalid_label; - - basetable->gpt_first = 0; - basetable->gpt_last = chs - 1; - basetable->gpt_isleaf = 1; - - withtags = (be32dec(&table->vtoc.sanity) == VTOC_SANITY) ? 1 : 0; - if (!withtags) { - printf("GEOM: %s: adding VTOC8 information.\n", pp->name); - be32enc(&table->vtoc.version, VTOC_VERSION); - bzero(&table->vtoc.volume, VTOC_VOLUME_LEN); - be16enc(&table->vtoc.nparts, VTOC8_NPARTS); - bzero(&table->vtoc.part, sizeof(table->vtoc.part)); - be32enc(&table->vtoc.sanity, VTOC_SANITY); - } - - basetable->gpt_entries = be16dec(&table->vtoc.nparts); - if (basetable->gpt_entries < g_part_vtoc8_scheme.gps_minent || - basetable->gpt_entries > g_part_vtoc8_scheme.gps_maxent) - goto invalid_label; - - for (index = basetable->gpt_entries - 1; index >= 0; index--) { - offset = be32dec(&table->vtoc.map[index].cyl) * - table->secpercyl; - size = be32dec(&table->vtoc.map[index].nblks); - if (size == 0) - continue; - if (withtags) - tag = be16dec(&table->vtoc.part[index].tag); - else - tag = (index == VTOC_RAW_PART) - ? VTOC_TAG_BACKUP - : VTOC_TAG_UNASSIGNED; - - if (index == VTOC_RAW_PART && tag != VTOC_TAG_BACKUP) - continue; - if (index != VTOC_RAW_PART && tag == VTOC_TAG_BACKUP) - continue; - entry = g_part_new_entry(basetable, index + 1, offset, - offset + size - 1); - if (tag == VTOC_TAG_BACKUP) - entry->gpe_internal = 1; - - if (!withtags) - be16enc(&table->vtoc.part[index].tag, tag); - } - - return (0); - - invalid_label: - printf("GEOM: %s: invalid VTOC8 label.\n", pp->name); - return (EINVAL); -} - -static const char * -g_part_vtoc8_type(struct g_part_table *basetable, struct g_part_entry *entry, - char *buf, size_t bufsz) -{ - struct g_part_vtoc8_table *table; - uint16_t tag; - - table = (struct g_part_vtoc8_table *)basetable; - tag = be16dec(&table->vtoc.part[entry->gpe_index - 1].tag); - if (tag == VTOC_TAG_MIDNIGHTBSD_NANDFS) - return (g_part_alias_name(G_PART_ALIAS_MIDNIGHTBSD_NANDFS)); - if (tag == VTOC_TAG_MIDNIGHTBSD_SWAP) - return (g_part_alias_name(G_PART_ALIAS_MIDNIGHTBSD_SWAP)); - if (tag == VTOC_TAG_MIDNIGHTBSD_UFS) - return (g_part_alias_name(G_PART_ALIAS_MIDNIGHTBSD_UFS)); - if (tag == VTOC_TAG_MIDNIGHTBSD_VINUM) - return (g_part_alias_name(G_PART_ALIAS_MIDNIGHTBSD_VINUM)); - if (tag == VTOC_TAG_MIDNIGHTBSD_ZFS) - return (g_part_alias_name(G_PART_ALIAS_MIDNIGHTBSD_ZFS)); - snprintf(buf, bufsz, "!%d", tag); - return (buf); -} - -static int -g_part_vtoc8_write(struct g_part_table *basetable, struct g_consumer *cp) -{ - struct g_provider *pp; - struct g_part_entry *entry; - struct g_part_vtoc8_table *table; - uint16_t sum; - u_char *p; - int error, index, match, offset; - - pp = cp->provider; - table = (struct g_part_vtoc8_table *)basetable; - entry = LIST_FIRST(&basetable->gpt_entry); - for (index = 0; index < basetable->gpt_entries; index++) { - match = (entry != NULL && index == entry->gpe_index - 1) - ? 1 : 0; - if (match) { - if (entry->gpe_deleted) { - be16enc(&table->vtoc.part[index].tag, 0); - be16enc(&table->vtoc.part[index].flag, 0); - be32enc(&table->vtoc.map[index].cyl, 0); - be32enc(&table->vtoc.map[index].nblks, 0); - } - entry = LIST_NEXT(entry, gpe_entry); - } - } - - /* Calculate checksum. */ - sum = 0; - p = (void *)&table->vtoc; - for (offset = 0; offset < sizeof(table->vtoc) - 2; offset += 2) - sum ^= be16dec(p + offset); - be16enc(&table->vtoc.cksum, sum); - - error = g_write_data(cp, 0, p, pp->sectorsize); - return (error); -} diff --git a/sys/geom/sched/README b/sys/geom/sched/README deleted file mode 100644 index 798d7214095..00000000000 --- a/sys/geom/sched/README +++ /dev/null @@ -1,141 +0,0 @@ - - --- GEOM BASED DISK SCHEDULERS FOR FREEBSD --- - -This code contains a framework for GEOM-based disk schedulers and a -couple of sample scheduling algorithms that use the framework and -implement two forms of "anticipatory scheduling" (see below for more -details). - -As a quick example of what this code can give you, try to run "dd", -"tar", or some other program with highly SEQUENTIAL access patterns, -together with "cvs", "cvsup", "svn" or other highly RANDOM access patterns -(this is not a made-up example: it is pretty common for developers -to have one or more apps doing random accesses, and others that do -sequential accesses e.g., loading large binaries from disk, checking -the integrity of tarballs, watching media streams and so on). - -These are the results we get on a local machine (AMD BE2400 dual -core CPU, SATA 250GB disk): - - /mnt is a partition mounted on /dev/ad0s1f - - cvs: cvs -d /mnt/home/ncvs-local update -Pd /mnt/ports - dd-read: dd bs=128k of=/dev/null if=/dev/ad0 (or ad0-sched-) - dd-writew dd bs=128k if=/dev/zero of=/mnt/largefile - - NO SCHEDULER RR SCHEDULER - dd cvs dd cvs - - dd-read only 72 MB/s ---- 72 MB/s --- - dd-write only 55 MB/s --- 55 MB/s --- - dd-read+cvs 6 MB/s ok 30 MB/s ok - dd-write+cvs 55 MB/s slooow 14 MB/s ok - -As you can see, when a cvs is running concurrently with dd, the -performance drops dramatically, and depending on read or write mode, -one of the two is severely penalized. The use of the RR scheduler -in this example makes the dd-reader go much faster when competing -with cvs, and lets cvs progress when competing with a writer. - -To try it out: - -1. PLEASE MAKE SURE THAT THE DISK THAT YOU WILL BE USING FOR TESTS - DOES NOT CONTAIN PRECIOUS DATA. - This is experimental code, so we make no guarantees, though - I am routinely using it on my desktop and laptop. - -2. EXTRACT AND BUILD THE PROGRAMS - A 'make install' in the directory should work (with root privs), - or you can even try the binary modules. - If you want to build the modules yourself, look at the Makefile. - -3. LOAD THE MODULE, CREATE A GEOM NODE, RUN TESTS - - The scheduler's module must be loaded first: - - # kldload gsched_rr - - substitute with gsched_as to test AS. Then, supposing that you are - using /dev/ad0 for testing, a scheduler can be attached to it with: - - # geom sched insert ad0 - - The scheduler is inserted transparently in the geom chain, so - mounted partitions and filesystems will keep working, but - now requests will go through the scheduler. - - To change scheduler on-the-fly, you can reconfigure the geom: - - # geom sched configure -a as ad0.sched. - - assuming that gsched_as was loaded previously. - -5. SCHEDULER REMOVAL - - In principle it is possible to remove the scheduler module - even on an active chain by doing - - # geom sched destroy ad0.sched. - - However, there is some race in the geom subsystem which makes - the removal unsafe if there are active requests on a chain. - So, in order to reduce the risk of data losses, make sure - you don't remove a scheduler from a chain with ongoing transactions. - ---- NOTES ON THE SCHEDULERS --- - -The important contribution of this code is the framework to experiment -with different scheduling algorithms. 'Anticipatory scheduling' -is a very powerful technique based on the following reasoning: - - The disk throughput is much better if it serves sequential requests. - If we have a mix of sequential and random requests, and we see a - non-sequential request, do not serve it immediately but instead wait - a little bit (2..5ms) to see if there is another one coming that - the disk can serve more efficiently. - -There are many details that should be added to make sure that the -mechanism is effective with different workloads and systems, to -gain a few extra percent in performance, to improve fairness, -insulation among processes etc. A discussion of the vast literature -on the subject is beyond the purpose of this short note. - --------------------------------------------------------------------------- - -TRANSPARENT INSERT/DELETE - -geom_sched is an ordinary geom module, however it is convenient -to plug it transparently into the geom graph, so that one can -enable or disable scheduling on a mounted filesystem, and the -names in /etc/fstab do not depend on the presence of the scheduler. - -To understand how this works in practice, remember that in GEOM -we have "providers" and "geom" objects. -Say that we want to hook a scheduler on provider "ad0", -accessible through pointer 'pp'. Originally, pp is attached to -geom "ad0" (same name, different object) accessible through pointer old_gp - - BEFORE ---> [ pp --> old_gp ...] - -A normal "geom sched create ad0" call would create a new geom node -on top of provider ad0/pp, and export a newly created provider -("ad0.sched." accessible through pointer newpp). - - AFTER create ---> [ newpp --> gp --> cp ] ---> [ pp --> old_gp ... ] - -On top of newpp, a whole tree will be created automatically, and we -can e.g. mount partitions on /dev/ad0.sched.s1d, and those requests -will go through the scheduler, whereas any partition mounted on -the pre-existing device entries will not go through the scheduler. - -With the transparent insert mechanism, the original provider "ad0"/pp -is hooked to the newly created geom, as follows: - - AFTER insert ---> [ pp --> gp --> cp ] ---> [ newpp --> old_gp ... ] - -so anything that was previously using provider pp will now have -the requests routed through the scheduler node. - -A removal ("geom sched destroy ad0.sched.") will restore the original -configuration. - diff --git a/sys/geom/sched/g_sched.c b/sys/geom/sched/g_sched.c deleted file mode 100644 index 3d03243e3ca..00000000000 --- a/sys/geom/sched/g_sched.c +++ /dev/null @@ -1,1727 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2009-2010 Fabio Checconi - * Copyright (c) 2009-2010 Luigi Rizzo, Universita` di Pisa - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -/* - * $Id$ - * - * Main control module for geom-based disk schedulers ('sched'). - * - * USER VIEW - * A 'sched' node is typically inserted transparently between - * an existing provider pp and its original geom gp - * - * [pp --> gp ..] - * - * using the command "geom sched insert " and - * resulting in the following topology - * - * [pp --> sched_gp --> cp] [new_pp --> gp ... ] - * - * Deletion "geom sched destroy .sched." restores the - * original chain. The normal "geom sched create " - * is also supported. - * - * INTERNALS - * Internally, the 'sched' uses the following data structures - * - * geom{} g_sched_softc{} g_gsched{} - * +----------+ +---------------+ +-------------+ - * | softc *-|--->| sc_gsched *-|-->| gs_init | - * | ... | | | | gs_fini | - * | | | [ hash table] | | gs_start | - * +----------+ | | | ... | - * | | +-------------+ - * | | - * | | g_*_softc{} - * | | +-------------+ - * | sc_data *-|-->| | - * +---------------+ | algorithm- | - * | specific | - * +-------------+ - * - * A g_sched_softc{} is created with a "geom sched insert" call. - * In turn this instantiates a specific scheduling algorithm, - * which sets sc_gsched to point to the algorithm callbacks, - * and calls gs_init() to create the g_*_softc{} . - * The other callbacks (gs_start, gs_next, ...) are invoked - * as needed - * - * g_sched_softc{} is defined in g_sched.h and mostly used here; - * g_gsched{}, and the gs_callbacks, are documented in gs_scheduler.h; - * g_*_softc{} is defined/implemented by each algorithm (gs_*.c) - * - * DATA MOVING - * When a bio is received on the provider, it goes to the - * g_sched_start() which calls gs_start() to initially queue it; - * then we call g_sched_dispatch() that loops around gs_next() - * to select zero or more bio's to be sent downstream. - * - * g_sched_dispatch() can also be called as a result of a timeout, - * e.g. when doing anticipation or pacing requests. - * - * When a bio comes back, it goes to g_sched_done() which in turn - * calls gs_done(). The latter does any necessary housekeeping in - * the scheduling algorithm, and may decide to call g_sched_dispatch() - * to send more bio's downstream. - * - * If an algorithm needs per-flow queues, these are created - * calling gs_init_class() and destroyed with gs_fini_class(), - * and they are also inserted in the hash table implemented in - * the g_sched_softc{} - * - * If an algorithm is replaced, or a transparently-inserted node is - * removed with "geom sched destroy", we need to remove all references - * to the g_*_softc{} and g_sched_softc from the bio's still in - * the scheduler. g_sched_forced_dispatch() helps doing this. - * XXX need to explain better. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include /* we access curthread */ -#include -#include "gs_scheduler.h" -#include "g_sched.h" /* geom hooks */ - -/* - * Size of the per-geom hash table storing traffic classes. - * We may decide to change it at a later time, it has no ABI - * implications as it is only used for run-time allocations. - */ -#define G_SCHED_HASH_SIZE 32 - -static int g_sched_destroy(struct g_geom *gp, boolean_t force); -static int g_sched_destroy_geom(struct gctl_req *req, - struct g_class *mp, struct g_geom *gp); -static void g_sched_config(struct gctl_req *req, struct g_class *mp, - const char *verb); -static struct g_geom *g_sched_taste(struct g_class *mp, - struct g_provider *pp, int flags __unused); -static void g_sched_dumpconf(struct sbuf *sb, const char *indent, - struct g_geom *gp, struct g_consumer *cp, struct g_provider *pp); -static void g_sched_init(struct g_class *mp); -static void g_sched_fini(struct g_class *mp); -static int g_sched_ioctl(struct g_provider *pp, u_long cmd, void *data, - int fflag, struct thread *td); - -struct g_class g_sched_class = { - .name = G_SCHED_CLASS_NAME, - .version = G_VERSION, - .ctlreq = g_sched_config, - .taste = g_sched_taste, - .destroy_geom = g_sched_destroy_geom, - .init = g_sched_init, - .ioctl = g_sched_ioctl, - .fini = g_sched_fini -}; - -MALLOC_DEFINE(M_GEOM_SCHED, "GEOM_SCHED", "Geom schedulers data structures"); - -/* - * Global variables describing the state of the geom_sched module. - * There is only one static instance of this structure. - */ -LIST_HEAD(gs_list, g_gsched); /* type, link field */ -struct geom_sched_vars { - struct mtx gs_mtx; - struct gs_list gs_scheds; /* list of algorithms */ - u_int gs_debug; - u_int gs_sched_count; /* how many algorithms ? */ - u_int gs_patched; /* g_io_request was patched */ - - u_int gs_initialized; - u_int gs_expire_secs; /* expiration of hash entries */ - - struct bio_queue_head gs_pending; - u_int gs_npending; - - /* The following are for stats, usually protected by gs_mtx. */ - u_long gs_requests; /* total requests */ - u_long gs_done; /* total done */ - u_int gs_in_flight; /* requests in flight */ - u_int gs_writes_in_flight; - u_int gs_bytes_in_flight; - u_int gs_write_bytes_in_flight; - - char gs_names[256]; /* names of schedulers */ -}; - -static struct geom_sched_vars me = { - .gs_expire_secs = 10, -}; - -SYSCTL_DECL(_kern_geom); -SYSCTL_NODE(_kern_geom, OID_AUTO, sched, CTLFLAG_RW, 0, - "GEOM_SCHED stuff"); - -SYSCTL_UINT(_kern_geom_sched, OID_AUTO, in_flight_wb, CTLFLAG_RD, - &me.gs_write_bytes_in_flight, 0, "Write bytes in flight"); - -SYSCTL_UINT(_kern_geom_sched, OID_AUTO, in_flight_b, CTLFLAG_RD, - &me.gs_bytes_in_flight, 0, "Bytes in flight"); - -SYSCTL_UINT(_kern_geom_sched, OID_AUTO, in_flight_w, CTLFLAG_RD, - &me.gs_writes_in_flight, 0, "Write Requests in flight"); - -SYSCTL_UINT(_kern_geom_sched, OID_AUTO, in_flight, CTLFLAG_RD, - &me.gs_in_flight, 0, "Requests in flight"); - -SYSCTL_ULONG(_kern_geom_sched, OID_AUTO, done, CTLFLAG_RD, - &me.gs_done, 0, "Total done"); - -SYSCTL_ULONG(_kern_geom_sched, OID_AUTO, requests, CTLFLAG_RD, - &me.gs_requests, 0, "Total requests"); - -SYSCTL_STRING(_kern_geom_sched, OID_AUTO, algorithms, CTLFLAG_RD, - &me.gs_names, 0, "Algorithm names"); - -SYSCTL_UINT(_kern_geom_sched, OID_AUTO, alg_count, CTLFLAG_RD, - &me.gs_sched_count, 0, "Number of algorithms"); - -SYSCTL_UINT(_kern_geom_sched, OID_AUTO, debug, CTLFLAG_RW, - &me.gs_debug, 0, "Debug level"); - -SYSCTL_UINT(_kern_geom_sched, OID_AUTO, expire_secs, CTLFLAG_RW, - &me.gs_expire_secs, 0, "Expire time in seconds"); - -/* - * g_sched calls the scheduler algorithms with this lock held. - * The locking functions are exposed so the scheduler algorithms can also - * protect themselves e.g. when running a callout handler. - */ -void -g_sched_lock(struct g_geom *gp) -{ - struct g_sched_softc *sc = gp->softc; - - mtx_lock(&sc->sc_mtx); -} - -void -g_sched_unlock(struct g_geom *gp) -{ - struct g_sched_softc *sc = gp->softc; - - mtx_unlock(&sc->sc_mtx); -} - -/* - * Support functions to handle references to the module, - * which are coming from devices using this scheduler. - */ -static inline void -g_gsched_ref(struct g_gsched *gsp) -{ - - atomic_add_int(&gsp->gs_refs, 1); -} - -static inline void -g_gsched_unref(struct g_gsched *gsp) -{ - - atomic_add_int(&gsp->gs_refs, -1); -} - -/* - * Update the stats when this request is done. - */ -static void -g_sched_update_stats(struct bio *bio) -{ - - me.gs_done++; - me.gs_in_flight--; - me.gs_bytes_in_flight -= bio->bio_length; - if (bio->bio_cmd == BIO_WRITE) { - me.gs_writes_in_flight--; - me.gs_write_bytes_in_flight -= bio->bio_length; - } -} - -/* - * Dispatch any pending request. - */ -static void -g_sched_forced_dispatch(struct g_geom *gp) -{ - struct g_sched_softc *sc = gp->softc; - struct g_gsched *gsp = sc->sc_gsched; - struct bio *bp; - - KASSERT(mtx_owned(&sc->sc_mtx), - ("sc_mtx not owned during forced dispatch")); - - while ((bp = gsp->gs_next(sc->sc_data, 1)) != NULL) - g_io_request(bp, LIST_FIRST(&gp->consumer)); -} - -/* - * The main dispatch loop, called either here after the start - * routine, or by scheduling algorithms when they receive a timeout - * or a 'done' notification. Does not share code with the forced - * dispatch path, since the gs_done() callback can call us. - */ -void -g_sched_dispatch(struct g_geom *gp) -{ - struct g_sched_softc *sc = gp->softc; - struct g_gsched *gsp = sc->sc_gsched; - struct bio *bp; - - KASSERT(mtx_owned(&sc->sc_mtx), ("sc_mtx not owned during dispatch")); - - if ((sc->sc_flags & G_SCHED_FLUSHING)) - return; - - while ((bp = gsp->gs_next(sc->sc_data, 0)) != NULL) - g_io_request(bp, LIST_FIRST(&gp->consumer)); -} - -/* - * Recent (8.0 and above) versions of FreeBSD have support to - * register classifiers of disk requests. The classifier is - * invoked by g_io_request(), and stores the information into - * bp->bio_classifier1. - * - * Support for older versions, which is left here only for - * documentation purposes, relies on two hacks: - * 1. classification info is written into the bio_caller1 - * field of the topmost node in the bio chain. This field - * is rarely used, but this module is incompatible with - * those that use bio_caller1 for other purposes, - * such as ZFS and gjournal; - * 2. g_io_request() is patched in-memory when the module is - * loaded, so that the function calls a classifier as its - * first thing. g_io_request() is restored when the module - * is unloaded. This functionality is only supported for - * x86 and amd64, other architectures need source code changes. - */ - -/* - * Lookup the identity of the issuer of the original request. - * In the current implementation we use the curthread of the - * issuer, but different mechanisms may be implemented later - * so we do not make assumptions on the return value which for - * us is just an opaque identifier. - */ - -static inline u_long -g_sched_classify(struct bio *bp) -{ - - /* we have classifier fields in the struct bio */ - return ((u_long)bp->bio_classifier1); -} - -/* Return the hash chain for the given key. */ -static inline struct g_hash * -g_sched_hash(struct g_sched_softc *sc, u_long key) -{ - - return (&sc->sc_hash[key & sc->sc_mask]); -} - -/* - * Helper function for the children classes, which takes - * a geom and a bio and returns the private descriptor - * associated to the request. This involves fetching - * the classification field and [al]locating the - * corresponding entry in the hash table. - */ -void * -g_sched_get_class(struct g_geom *gp, struct bio *bp) -{ - struct g_sched_softc *sc; - struct g_sched_class *gsc; - struct g_gsched *gsp; - struct g_hash *bucket; - u_long key; - - sc = gp->softc; - key = g_sched_classify(bp); - bucket = g_sched_hash(sc, key); - LIST_FOREACH(gsc, bucket, gsc_clist) { - if (key == gsc->gsc_key) { - gsc->gsc_refs++; - return (gsc->gsc_priv); - } - } - - gsp = sc->sc_gsched; - gsc = malloc(sizeof(*gsc) + gsp->gs_priv_size, - M_GEOM_SCHED, M_NOWAIT | M_ZERO); - if (!gsc) - return (NULL); - - if (gsp->gs_init_class(sc->sc_data, gsc->gsc_priv)) { - free(gsc, M_GEOM_SCHED); - return (NULL); - } - - gsc->gsc_refs = 2; /* 1 for the hash table, 1 for the caller. */ - gsc->gsc_key = key; - LIST_INSERT_HEAD(bucket, gsc, gsc_clist); - - gsc->gsc_expire = ticks + me.gs_expire_secs * hz; - - return (gsc->gsc_priv); -} - -/* - * Release a reference to the per-client descriptor, - */ -void -g_sched_put_class(struct g_geom *gp, void *priv) -{ - struct g_sched_class *gsc; - struct g_sched_softc *sc; - - gsc = g_sched_priv2class(priv); - gsc->gsc_expire = ticks + me.gs_expire_secs * hz; - - if (--gsc->gsc_refs > 0) - return; - - sc = gp->softc; - sc->sc_gsched->gs_fini_class(sc->sc_data, priv); - - LIST_REMOVE(gsc, gsc_clist); - free(gsc, M_GEOM_SCHED); -} - -static void -g_sched_hash_fini(struct g_geom *gp, struct g_hash *hp, u_long mask, - struct g_gsched *gsp, void *data) -{ - struct g_sched_class *cp, *cp2; - int i; - - if (!hp) - return; - - if (data && gsp->gs_hash_unref) - gsp->gs_hash_unref(data); - - for (i = 0; i < G_SCHED_HASH_SIZE; i++) { - LIST_FOREACH_SAFE(cp, &hp[i], gsc_clist, cp2) - g_sched_put_class(gp, cp->gsc_priv); - } - - hashdestroy(hp, M_GEOM_SCHED, mask); -} - -static struct g_hash * -g_sched_hash_init(struct g_gsched *gsp, u_long *mask, int flags) -{ - struct g_hash *hash; - - if (gsp->gs_priv_size == 0) - return (NULL); - - hash = hashinit_flags(G_SCHED_HASH_SIZE, M_GEOM_SCHED, mask, flags); - - return (hash); -} - -static void -g_sched_flush_classes(struct g_geom *gp) -{ - struct g_sched_softc *sc; - struct g_sched_class *cp, *cp2; - int i; - - sc = gp->softc; - - if (!sc->sc_hash || ticks - sc->sc_flush_ticks <= 0) - return; - - for (i = 0; i < G_SCHED_HASH_SIZE; i++) { - LIST_FOREACH_SAFE(cp, &sc->sc_hash[i], gsc_clist, cp2) { - if (cp->gsc_refs == 1 && ticks - cp->gsc_expire > 0) - g_sched_put_class(gp, cp->gsc_priv); - } - } - - sc->sc_flush_ticks = ticks + me.gs_expire_secs * hz; -} - -/* - * Wait for the completion of any outstanding request. To ensure - * that this does not take forever the caller has to make sure that - * no new request enter the scehduler before calling us. - * - * Must be called with the gp mutex held and topology locked. - */ -static int -g_sched_wait_pending(struct g_geom *gp) -{ - struct g_sched_softc *sc = gp->softc; - int endticks = ticks + hz; - - g_topology_assert(); - - while (sc->sc_pending && endticks - ticks >= 0) - msleep(gp, &sc->sc_mtx, 0, "sched_wait_pending", hz / 4); - - return (sc->sc_pending ? ETIMEDOUT : 0); -} - -static int -g_sched_remove_locked(struct g_geom *gp, struct g_gsched *gsp) -{ - struct g_sched_softc *sc = gp->softc; - int error; - - /* Set the flushing flag: new bios will not enter the scheduler. */ - sc->sc_flags |= G_SCHED_FLUSHING; - - g_sched_forced_dispatch(gp); - error = g_sched_wait_pending(gp); - if (error) - goto failed; - - /* No more requests pending or in flight from the old gsp. */ - - g_sched_hash_fini(gp, sc->sc_hash, sc->sc_mask, gsp, sc->sc_data); - sc->sc_hash = NULL; - - /* - * Avoid deadlock here by releasing the gp mutex and reacquiring - * it once done. It should be safe, since no reconfiguration or - * destruction can take place due to the geom topology lock; no - * new request can use the current sc_data since we flagged the - * geom as being flushed. - */ - g_sched_unlock(gp); - gsp->gs_fini(sc->sc_data); - g_sched_lock(gp); - - sc->sc_gsched = NULL; - sc->sc_data = NULL; - g_gsched_unref(gsp); - -failed: - sc->sc_flags &= ~G_SCHED_FLUSHING; - - return (error); -} - -static int -g_sched_remove(struct g_geom *gp, struct g_gsched *gsp) -{ - int error; - - g_sched_lock(gp); - error = g_sched_remove_locked(gp, gsp); /* gsp is surely non-null */ - g_sched_unlock(gp); - - return (error); -} - -/* - * Support function for create/taste -- locate the desired - * algorithm and grab a reference to it. - */ -static struct g_gsched * -g_gsched_find(const char *name) -{ - struct g_gsched *gsp = NULL; - - mtx_lock(&me.gs_mtx); - LIST_FOREACH(gsp, &me.gs_scheds, glist) { - if (strcmp(name, gsp->gs_name) == 0) { - g_gsched_ref(gsp); - break; - } - } - mtx_unlock(&me.gs_mtx); - - return (gsp); -} - -/* - * Rebuild the list of scheduler names. - * To be called with me.gs_mtx lock held. - */ -static void -g_gsched_build_names(struct g_gsched *gsp) -{ - int pos, l; - struct g_gsched *cur; - - pos = 0; - LIST_FOREACH(cur, &me.gs_scheds, glist) { - l = strlen(cur->gs_name); - if (l + pos + 1 + 1 < sizeof(me.gs_names)) { - if (pos != 0) - me.gs_names[pos++] = ' '; - strcpy(me.gs_names + pos, cur->gs_name); - pos += l; - } - } - me.gs_names[pos] = '\0'; -} - -/* - * Register or unregister individual scheduling algorithms. - */ -static int -g_gsched_register(struct g_gsched *gsp) -{ - struct g_gsched *cur; - int error = 0; - - mtx_lock(&me.gs_mtx); - LIST_FOREACH(cur, &me.gs_scheds, glist) { - if (strcmp(gsp->gs_name, cur->gs_name) == 0) - break; - } - if (cur != NULL) { - G_SCHED_DEBUG(0, "A scheduler named %s already" - "exists.", gsp->gs_name); - error = EEXIST; - } else { - LIST_INSERT_HEAD(&me.gs_scheds, gsp, glist); - gsp->gs_refs = 1; - me.gs_sched_count++; - g_gsched_build_names(gsp); - } - mtx_unlock(&me.gs_mtx); - - return (error); -} - -struct g_gsched_unregparm { - struct g_gsched *gup_gsp; - int gup_error; -}; - -static void -g_gsched_unregister(void *arg, int flag) -{ - struct g_gsched_unregparm *parm = arg; - struct g_gsched *gsp = parm->gup_gsp, *cur, *tmp; - struct g_sched_softc *sc; - struct g_geom *gp, *gp_tmp; - int error; - - parm->gup_error = 0; - - g_topology_assert(); - - if (flag == EV_CANCEL) - return; - - mtx_lock(&me.gs_mtx); - - LIST_FOREACH_SAFE(gp, &g_sched_class.geom, geom, gp_tmp) { - if (gp->class != &g_sched_class) - continue; /* Should not happen. */ - - sc = gp->softc; - if (sc->sc_gsched == gsp) { - error = g_sched_remove(gp, gsp); - if (error) - goto failed; - } - } - - LIST_FOREACH_SAFE(cur, &me.gs_scheds, glist, tmp) { - if (cur != gsp) - continue; - - if (gsp->gs_refs != 1) { - G_SCHED_DEBUG(0, "%s still in use.", - gsp->gs_name); - parm->gup_error = EBUSY; - } else { - LIST_REMOVE(gsp, glist); - me.gs_sched_count--; - g_gsched_build_names(gsp); - } - break; - } - - if (cur == NULL) { - G_SCHED_DEBUG(0, "%s not registered.", gsp->gs_name); - parm->gup_error = ENOENT; - } - -failed: - mtx_unlock(&me.gs_mtx); -} - -static inline void -g_gsched_global_init(void) -{ - - if (!me.gs_initialized) { - G_SCHED_DEBUG(0, "Initializing global data."); - mtx_init(&me.gs_mtx, "gsched", NULL, MTX_DEF); - LIST_INIT(&me.gs_scheds); - bioq_init(&me.gs_pending); - me.gs_initialized = 1; - } -} - -/* - * Module event called when a scheduling algorithm module is loaded or - * unloaded. - */ -int -g_gsched_modevent(module_t mod, int cmd, void *arg) -{ - struct g_gsched *gsp = arg; - struct g_gsched_unregparm parm; - int error; - - G_SCHED_DEBUG(0, "Modevent %d.", cmd); - - /* - * If the module is loaded at boot, the geom thread that calls - * g_sched_init() might actually run after g_gsched_modevent(), - * so make sure that the module is properly initialized. - */ - g_gsched_global_init(); - - error = EOPNOTSUPP; - switch (cmd) { - case MOD_LOAD: - error = g_gsched_register(gsp); - G_SCHED_DEBUG(0, "Loaded module %s error %d.", - gsp->gs_name, error); - if (error == 0) - g_retaste(&g_sched_class); - break; - - case MOD_UNLOAD: - parm.gup_gsp = gsp; - parm.gup_error = 0; - - error = g_waitfor_event(g_gsched_unregister, - &parm, M_WAITOK, NULL); - if (error == 0) - error = parm.gup_error; - G_SCHED_DEBUG(0, "Unloaded module %s error %d.", - gsp->gs_name, error); - break; - } - - return (error); -} - -#ifdef KTR -#define TRC_BIO_EVENT(e, bp) g_sched_trace_bio_ ## e (bp) - -static inline char -g_sched_type(struct bio *bp) -{ - - if (bp->bio_cmd == BIO_READ) - return ('R'); - else if (bp->bio_cmd == BIO_WRITE) - return ('W'); - return ('U'); -} - -static inline void -g_sched_trace_bio_START(struct bio *bp) -{ - - CTR5(KTR_GSCHED, "S %lu %c %lu/%lu %lu", g_sched_classify(bp), - g_sched_type(bp), bp->bio_offset / ULONG_MAX, - bp->bio_offset, bp->bio_length); -} - -static inline void -g_sched_trace_bio_DONE(struct bio *bp) -{ - - CTR5(KTR_GSCHED, "D %lu %c %lu/%lu %lu", g_sched_classify(bp), - g_sched_type(bp), bp->bio_offset / ULONG_MAX, - bp->bio_offset, bp->bio_length); -} -#else /* !KTR */ -#define TRC_BIO_EVENT(e, bp) -#endif /* !KTR */ - -/* - * g_sched_done() and g_sched_start() dispatch the geom requests to - * the scheduling algorithm in use. - */ -static void -g_sched_done(struct bio *bio) -{ - struct g_geom *gp = bio->bio_caller2; - struct g_sched_softc *sc = gp->softc; - - TRC_BIO_EVENT(DONE, bio); - - KASSERT(bio->bio_caller1, ("null bio_caller1 in g_sched_done")); - - g_sched_lock(gp); - - g_sched_update_stats(bio); - sc->sc_gsched->gs_done(sc->sc_data, bio); - if (!--sc->sc_pending) - wakeup(gp); - - g_sched_flush_classes(gp); - g_sched_unlock(gp); - - g_std_done(bio); -} - -static void -g_sched_start(struct bio *bp) -{ - struct g_geom *gp = bp->bio_to->geom; - struct g_sched_softc *sc = gp->softc; - struct bio *cbp; - - TRC_BIO_EVENT(START, bp); - G_SCHED_LOGREQ(bp, "Request received."); - - cbp = g_clone_bio(bp); - if (cbp == NULL) { - g_io_deliver(bp, ENOMEM); - return; - } - cbp->bio_done = g_sched_done; - cbp->bio_to = LIST_FIRST(&gp->provider); - KASSERT(cbp->bio_to != NULL, ("NULL provider")); - - /* We only schedule reads and writes. */ - if (bp->bio_cmd != BIO_READ && bp->bio_cmd != BIO_WRITE) - goto bypass; - - G_SCHED_LOGREQ(cbp, "Sending request."); - - g_sched_lock(gp); - /* - * Call the algorithm's gs_start to queue the request in the - * scheduler. If gs_start fails then pass the request down, - * otherwise call g_sched_dispatch() which tries to push - * one or more requests down. - */ - if (!sc->sc_gsched || (sc->sc_flags & G_SCHED_FLUSHING) || - sc->sc_gsched->gs_start(sc->sc_data, cbp)) { - g_sched_unlock(gp); - goto bypass; - } - /* - * We use bio_caller1 to mark requests that are scheduled - * so make sure it is not NULL. - */ - if (cbp->bio_caller1 == NULL) - cbp->bio_caller1 = &me; /* anything not NULL */ - - cbp->bio_caller2 = gp; - sc->sc_pending++; - - /* Update general stats. */ - me.gs_in_flight++; - me.gs_requests++; - me.gs_bytes_in_flight += bp->bio_length; - if (bp->bio_cmd == BIO_WRITE) { - me.gs_writes_in_flight++; - me.gs_write_bytes_in_flight += bp->bio_length; - } - g_sched_dispatch(gp); - g_sched_unlock(gp); - return; - -bypass: - cbp->bio_done = g_std_done; - cbp->bio_caller1 = NULL; /* not scheduled */ - g_io_request(cbp, LIST_FIRST(&gp->consumer)); -} - -/* - * The next few functions are the geom glue. - */ -static void -g_sched_orphan(struct g_consumer *cp) -{ - - g_topology_assert(); - g_sched_destroy(cp->geom, 1); -} - -static int -g_sched_access(struct g_provider *pp, int dr, int dw, int de) -{ - struct g_geom *gp; - struct g_consumer *cp; - int error; - - gp = pp->geom; - cp = LIST_FIRST(&gp->consumer); - error = g_access(cp, dr, dw, de); - - return (error); -} - -static void -g_sched_temporary_start(struct bio *bio) -{ - - mtx_lock(&me.gs_mtx); - me.gs_npending++; - bioq_disksort(&me.gs_pending, bio); - mtx_unlock(&me.gs_mtx); -} - -static void -g_sched_flush_pending(g_start_t *start) -{ - struct bio *bp; - - while ((bp = bioq_takefirst(&me.gs_pending))) - start(bp); -} - -static int -g_insert_proxy(struct g_geom *gp, struct g_provider *newpp, - struct g_geom *dstgp, struct g_provider *pp, struct g_consumer *cp) -{ - struct g_sched_softc *sc = gp->softc; - g_start_t *saved_start, *flush = g_sched_start; - int error = 0, endticks = ticks + hz; - - g_cancel_event(newpp); /* prevent taste() */ - /* copy private fields */ - newpp->private = pp->private; - newpp->index = pp->index; - - /* Queue all the early requests coming for us. */ - me.gs_npending = 0; - saved_start = pp->geom->start; - dstgp->start = g_sched_temporary_start; - - while (pp->nstart - pp->nend != me.gs_npending && - endticks - ticks >= 0) - tsleep(pp, PRIBIO, "-", hz/10); - - if (pp->nstart - pp->nend != me.gs_npending) { - flush = saved_start; - error = ETIMEDOUT; - goto fail; - } - - /* link pp to this geom */ - LIST_REMOVE(pp, provider); - pp->geom = gp; - LIST_INSERT_HEAD(&gp->provider, pp, provider); - - /* - * replicate the counts from the parent in the - * new provider and consumer nodes - */ - cp->acr = newpp->acr = pp->acr; - cp->acw = newpp->acw = pp->acw; - cp->ace = newpp->ace = pp->ace; - sc->sc_flags |= G_SCHED_PROXYING; - -fail: - dstgp->start = saved_start; - - g_sched_flush_pending(flush); - - return (error); -} - -/* - * Create a geom node for the device passed as *pp. - * If successful, add a reference to this gsp. - */ -static int -g_sched_create(struct gctl_req *req, struct g_class *mp, - struct g_provider *pp, struct g_gsched *gsp, int proxy) -{ - struct g_sched_softc *sc = NULL; - struct g_geom *gp, *dstgp; - struct g_provider *newpp = NULL; - struct g_consumer *cp = NULL; - char name[64]; - int error; - - g_topology_assert(); - - snprintf(name, sizeof(name), "%s%s", pp->name, G_SCHED_SUFFIX); - LIST_FOREACH(gp, &mp->geom, geom) { - if (strcmp(gp->name, name) == 0) { - gctl_error(req, "Geom %s already exists.", - name); - return (EEXIST); - } - } - - gp = g_new_geomf(mp, "%s", name); - dstgp = proxy ? pp->geom : gp; /* where do we link the provider */ - - sc = g_malloc(sizeof(*sc), M_WAITOK | M_ZERO); - sc->sc_gsched = gsp; - sc->sc_data = gsp->gs_init(gp); - if (sc->sc_data == NULL) { - error = ENOMEM; - goto fail; - } - - sc->sc_hash = g_sched_hash_init(gsp, &sc->sc_mask, HASH_WAITOK); - - /* - * Do not initialize the flush mechanism, will be initialized - * on the first insertion on the hash table. - */ - - mtx_init(&sc->sc_mtx, "g_sched_mtx", NULL, MTX_DEF); - - gp->softc = sc; - gp->start = g_sched_start; - gp->orphan = g_sched_orphan; - gp->access = g_sched_access; - gp->dumpconf = g_sched_dumpconf; - - newpp = g_new_providerf(dstgp, "%s", gp->name); - newpp->mediasize = pp->mediasize; - newpp->sectorsize = pp->sectorsize; - - cp = g_new_consumer(gp); - error = g_attach(cp, proxy ? newpp : pp); - if (error != 0) { - gctl_error(req, "Cannot attach to provider %s.", - pp->name); - goto fail; - } - - g_error_provider(newpp, 0); - if (proxy) { - error = g_insert_proxy(gp, newpp, dstgp, pp, cp); - if (error) - goto fail; - } - G_SCHED_DEBUG(0, "Device %s created.", gp->name); - - g_gsched_ref(gsp); - - return (0); - -fail: - if (cp != NULL) { - if (cp->provider != NULL) - g_detach(cp); - g_destroy_consumer(cp); - } - if (newpp != NULL) - g_destroy_provider(newpp); - if (sc->sc_hash) - g_sched_hash_fini(gp, sc->sc_hash, sc->sc_mask, - gsp, sc->sc_data); - if (sc->sc_data) - gsp->gs_fini(sc->sc_data); - g_free(gp->softc); - g_destroy_geom(gp); - - return (error); -} - -/* - * Support for dynamic switching of scheduling algorithms. - * First initialize the data structures for the new algorithm, - * then call g_sched_remove_locked() to flush all references - * to the old one, finally link the new algorithm. - */ -static int -g_sched_change_algo(struct gctl_req *req, struct g_class *mp, - struct g_provider *pp, struct g_gsched *gsp) -{ - struct g_sched_softc *sc; - struct g_geom *gp; - struct g_hash *newh; - void *data; - u_long mask; - int error = 0; - - gp = pp->geom; - sc = gp->softc; - - data = gsp->gs_init(gp); - if (data == NULL) - return (ENOMEM); - - newh = g_sched_hash_init(gsp, &mask, HASH_WAITOK); - if (gsp->gs_priv_size && !newh) { - error = ENOMEM; - goto fail; - } - - g_sched_lock(gp); - if (sc->sc_gsched) { /* can be NULL in some cases */ - error = g_sched_remove_locked(gp, sc->sc_gsched); - if (error) - goto fail; - } - - g_gsched_ref(gsp); - sc->sc_gsched = gsp; - sc->sc_data = data; - sc->sc_hash = newh; - sc->sc_mask = mask; - - g_sched_unlock(gp); - - return (0); - -fail: - if (newh) - g_sched_hash_fini(gp, newh, mask, gsp, data); - - if (data) - gsp->gs_fini(data); - - g_sched_unlock(gp); - - return (error); -} - -/* - * Stop the request flow directed to the proxy, redirecting the new - * requests to the me.gs_pending queue. - */ -static struct g_provider * -g_detach_proxy(struct g_geom *gp) -{ - struct g_consumer *cp; - struct g_provider *pp, *newpp; - - do { - pp = LIST_FIRST(&gp->provider); - if (pp == NULL) - break; - cp = LIST_FIRST(&gp->consumer); - if (cp == NULL) - break; - newpp = cp->provider; - if (newpp == NULL) - break; - - me.gs_npending = 0; - pp->geom->start = g_sched_temporary_start; - - return (pp); - } while (0); - printf("%s error detaching proxy %s\n", __FUNCTION__, gp->name); - - return (NULL); -} - -static void -g_sched_blackhole(struct bio *bp) -{ - - g_io_deliver(bp, ENXIO); -} - -static inline void -g_reparent_provider(struct g_provider *pp, struct g_geom *gp, - struct g_provider *newpp) -{ - - LIST_REMOVE(pp, provider); - if (newpp) { - pp->private = newpp->private; - pp->index = newpp->index; - } - pp->geom = gp; - LIST_INSERT_HEAD(&gp->provider, pp, provider); -} - -static inline void -g_unproxy_provider(struct g_provider *oldpp, struct g_provider *newpp) -{ - struct g_geom *gp = oldpp->geom; - - g_reparent_provider(oldpp, newpp->geom, newpp); - - /* - * Hackish: let the system destroy the old provider for us, just - * in case someone attached a consumer to it, in which case a - * direct call to g_destroy_provider() would not work. - */ - g_reparent_provider(newpp, gp, NULL); -} - -/* - * Complete the proxy destruction, linking the old provider to its - * original geom, and destroying the proxy provider. Also take care - * of issuing the pending requests collected in me.gs_pending (if any). - */ -static int -g_destroy_proxy(struct g_geom *gp, struct g_provider *oldpp) -{ - struct g_consumer *cp; - struct g_provider *newpp; - - do { - cp = LIST_FIRST(&gp->consumer); - if (cp == NULL) - break; - newpp = cp->provider; - if (newpp == NULL) - break; - - /* Relink the provider to its original geom. */ - g_unproxy_provider(oldpp, newpp); - - /* Detach consumer from provider, and destroy provider. */ - cp->acr = newpp->acr = 0; - cp->acw = newpp->acw = 0; - cp->ace = newpp->ace = 0; - g_detach(cp); - - /* Send the pending bios through the right start function. */ - g_sched_flush_pending(oldpp->geom->start); - - return (0); - } while (0); - printf("%s error destroying proxy %s\n", __FUNCTION__, gp->name); - - /* We cannot send the pending bios anywhere... */ - g_sched_flush_pending(g_sched_blackhole); - - return (EINVAL); -} - -static int -g_sched_destroy(struct g_geom *gp, boolean_t force) -{ - struct g_provider *pp, *oldpp = NULL; - struct g_sched_softc *sc; - struct g_gsched *gsp; - int error; - - g_topology_assert(); - sc = gp->softc; - if (sc == NULL) - return (ENXIO); - if (!(sc->sc_flags & G_SCHED_PROXYING)) { - pp = LIST_FIRST(&gp->provider); - if (pp && (pp->acr != 0 || pp->acw != 0 || pp->ace != 0)) { - const char *msg = force ? - "but we force removal" : "cannot remove"; - - G_SCHED_DEBUG(!force, - "Device %s is still open (r%dw%de%d), %s.", - pp->name, pp->acr, pp->acw, pp->ace, msg); - if (!force) - return (EBUSY); - } else { - G_SCHED_DEBUG(0, "Device %s removed.", gp->name); - } - } else - oldpp = g_detach_proxy(gp); - - gsp = sc->sc_gsched; - if (gsp) { - /* - * XXX bad hack here: force a dispatch to release - * any reference to the hash table still held by - * the scheduler. - */ - g_sched_lock(gp); - /* - * We are dying here, no new requests should enter - * the scheduler. This is granted by the topolgy, - * either in case we were proxying (new bios are - * being redirected) or not (see the access check - * above). - */ - g_sched_forced_dispatch(gp); - error = g_sched_wait_pending(gp); - - if (error) { - /* - * Not all the requests came home: this might happen - * under heavy load, or if we were waiting for any - * bio which is served in the event path (see - * geom_slice.c for an example of how this can - * happen). Try to restore a working configuration - * if we can fail. - */ - if ((sc->sc_flags & G_SCHED_PROXYING) && oldpp) { - g_sched_flush_pending(force ? - g_sched_blackhole : g_sched_start); - } - - /* - * In the forced destroy case there is not so much - * we can do, we have pending bios that will call - * g_sched_done() somehow, and we don't want them - * to crash the system using freed memory. We tell - * the user that something went wrong, and leak some - * memory here. - * Note: the callers using force = 1 ignore the - * return value. - */ - if (force) { - G_SCHED_DEBUG(0, "Pending requests while " - " destroying geom, some memory leaked."); - } - - return (error); - } - - g_sched_unlock(gp); - g_sched_hash_fini(gp, sc->sc_hash, sc->sc_mask, - gsp, sc->sc_data); - sc->sc_hash = NULL; - gsp->gs_fini(sc->sc_data); - g_gsched_unref(gsp); - sc->sc_gsched = NULL; - } else - error = 0; - - if ((sc->sc_flags & G_SCHED_PROXYING) && oldpp) { - error = g_destroy_proxy(gp, oldpp); - - if (error) { - if (force) { - G_SCHED_DEBUG(0, "Unrecoverable error while " - "destroying a proxy geom, leaking some " - " memory."); - } - - return (error); - } - } - - mtx_destroy(&sc->sc_mtx); - - g_free(gp->softc); - gp->softc = NULL; - g_wither_geom(gp, ENXIO); - - return (error); -} - -static int -g_sched_destroy_geom(struct gctl_req *req, struct g_class *mp, - struct g_geom *gp) -{ - - return (g_sched_destroy(gp, 0)); -} - -/* - * Functions related to the classification of requests. - * - * On recent FreeBSD versions (8.0 and above), we store a reference - * to the issuer of a request in bp->bio_classifier1 as soon - * as the bio is posted to the geom queue (and not later, because - * requests are managed by the g_down thread afterwards). - */ - -/* - * Classifier support for recent FreeBSD versions: we use - * a very simple classifier, only use curthread to tag a request. - * The classifier is registered at module load, and unregistered - * at module unload. - */ -static int -g_sched_tag(void *arg, struct bio *bp) -{ - - bp->bio_classifier1 = curthread; - return (1); -} - -static struct g_classifier_hook g_sched_classifier = { - .func = g_sched_tag, -}; - -static inline void -g_classifier_ini(void) -{ - - g_register_classifier(&g_sched_classifier); -} - -static inline void -g_classifier_fini(void) -{ - - g_unregister_classifier(&g_sched_classifier); -} - -static void -g_sched_init(struct g_class *mp) -{ - - g_gsched_global_init(); - - G_SCHED_DEBUG(0, "Loading: mp = %p, g_sched_class = %p.", - mp, &g_sched_class); - - /* Patch g_io_request to store classification info in the bio. */ - g_classifier_ini(); -} - -static void -g_sched_fini(struct g_class *mp) -{ - - g_classifier_fini(); - - G_SCHED_DEBUG(0, "Unloading..."); - - KASSERT(LIST_EMPTY(&me.gs_scheds), ("still registered schedulers")); - mtx_destroy(&me.gs_mtx); -} - -static int -g_sched_ioctl(struct g_provider *pp, u_long cmd, void *data, int fflag, - struct thread *td) -{ - struct g_consumer *cp; - struct g_geom *gp; - - cp = LIST_FIRST(&pp->geom->consumer); - if (cp == NULL) - return (ENOIOCTL); - gp = cp->provider->geom; - if (gp->ioctl == NULL) - return (ENOIOCTL); - return (gp->ioctl(cp->provider, cmd, data, fflag, td)); -} - -/* - * Read the i-th argument for a request, skipping the /dev/ - * prefix if present. - */ -static const char * -g_sched_argi(struct gctl_req *req, int i) -{ - static const char *dev_prefix = "/dev/"; - const char *name; - char param[16]; - int l = strlen(dev_prefix); - - snprintf(param, sizeof(param), "arg%d", i); - name = gctl_get_asciiparam(req, param); - if (name == NULL) - gctl_error(req, "No 'arg%d' argument", i); - else if (strncmp(name, dev_prefix, l) == 0) - name += l; - return (name); -} - -/* - * Fetch nargs and do appropriate checks. - */ -static int -g_sched_get_nargs(struct gctl_req *req) -{ - int *nargs; - - nargs = gctl_get_paraml(req, "nargs", sizeof(*nargs)); - if (nargs == NULL) { - gctl_error(req, "No 'nargs' argument"); - return (0); - } - if (*nargs <= 0) - gctl_error(req, "Missing device(s)."); - return (*nargs); -} - -/* - * Check whether we should add the class on certain volumes when - * this geom is created. Right now this is under control of a kenv - * variable containing the names of all devices that we care about. - * Probably we should only support transparent insertion as the - * preferred mode of operation. - */ -static struct g_geom * -g_sched_taste(struct g_class *mp, struct g_provider *pp, - int flags __unused) -{ - struct g_gsched *gsp = NULL; /* the . algorithm we want */ - const char *s; /* generic string pointer */ - const char *taste_names; /* devices we like */ - int l; - - g_trace(G_T_TOPOLOGY, "%s(%s, %s)", __func__, - mp->name, pp->name); - g_topology_assert(); - - G_SCHED_DEBUG(2, "Tasting %s.", pp->name); - - do { - /* do not taste on ourselves */ - if (pp->geom->class == mp) - break; - - taste_names = kern_getenv("geom.sched.taste"); - if (taste_names == NULL) - break; - - l = strlen(pp->name); - for (s = taste_names; *s && - (s = strstr(s, pp->name)); s++) { - /* further checks for an exact match */ - if ( (s == taste_names || s[-1] == ' ') && - (s[l] == '\0' || s[l] == ' ') ) - break; - } - if (s == NULL) - break; - G_SCHED_DEBUG(0, "Attach device %s match [%s]\n", - pp->name, s); - - /* look up the provider name in the list */ - s = kern_getenv("geom.sched.algo"); - if (s == NULL) - s = "rr"; - - gsp = g_gsched_find(s); /* also get a reference */ - if (gsp == NULL) { - G_SCHED_DEBUG(0, "Bad '%s' algorithm.", s); - break; - } - - /* XXX create with 1 as last argument ? */ - g_sched_create(NULL, mp, pp, gsp, 0); - g_gsched_unref(gsp); - } while (0); - return NULL; -} - -static void -g_sched_ctl_create(struct gctl_req *req, struct g_class *mp, int proxy) -{ - struct g_provider *pp; - struct g_gsched *gsp; - const char *name; - int i, nargs; - - g_topology_assert(); - - name = gctl_get_asciiparam(req, "algo"); - if (name == NULL) { - gctl_error(req, "No '%s' argument", "algo"); - return; - } - - gsp = g_gsched_find(name); /* also get a reference */ - if (gsp == NULL) { - gctl_error(req, "Bad algorithm '%s'", name); - return; - } - - nargs = g_sched_get_nargs(req); - - /* - * Run on the arguments, and break on any error. - * We look for a device name, but skip the /dev/ prefix if any. - */ - for (i = 0; i < nargs; i++) { - name = g_sched_argi(req, i); - if (name == NULL) - break; - pp = g_provider_by_name(name); - if (pp == NULL) { - G_SCHED_DEBUG(1, "Provider %s is invalid.", name); - gctl_error(req, "Provider %s is invalid.", name); - break; - } - if (g_sched_create(req, mp, pp, gsp, proxy) != 0) - break; - } - - g_gsched_unref(gsp); -} - -static void -g_sched_ctl_configure(struct gctl_req *req, struct g_class *mp) -{ - struct g_provider *pp; - struct g_gsched *gsp; - const char *name; - int i, nargs; - - g_topology_assert(); - - name = gctl_get_asciiparam(req, "algo"); - if (name == NULL) { - gctl_error(req, "No '%s' argument", "algo"); - return; - } - - gsp = g_gsched_find(name); /* also get a reference */ - if (gsp == NULL) { - gctl_error(req, "Bad algorithm '%s'", name); - return; - } - - nargs = g_sched_get_nargs(req); - - /* - * Run on the arguments, and break on any error. - * We look for a device name, but skip the /dev/ prefix if any. - */ - for (i = 0; i < nargs; i++) { - name = g_sched_argi(req, i); - if (name == NULL) - break; - pp = g_provider_by_name(name); - if (pp == NULL || pp->geom->class != mp) { - G_SCHED_DEBUG(1, "Provider %s is invalid.", name); - gctl_error(req, "Provider %s is invalid.", name); - break; - } - if (g_sched_change_algo(req, mp, pp, gsp) != 0) - break; - } - - g_gsched_unref(gsp); -} - -static struct g_geom * -g_sched_find_geom(struct g_class *mp, const char *name) -{ - struct g_geom *gp; - - LIST_FOREACH(gp, &mp->geom, geom) { - if (strcmp(gp->name, name) == 0) - return (gp); - } - return (NULL); -} - -static void -g_sched_ctl_destroy(struct gctl_req *req, struct g_class *mp) -{ - int nargs, *force, error, i; - struct g_geom *gp; - const char *name; - - g_topology_assert(); - - nargs = g_sched_get_nargs(req); - - force = gctl_get_paraml(req, "force", sizeof(*force)); - if (force == NULL) { - gctl_error(req, "No 'force' argument"); - return; - } - - for (i = 0; i < nargs; i++) { - name = g_sched_argi(req, i); - if (name == NULL) - break; - - gp = g_sched_find_geom(mp, name); - if (gp == NULL) { - G_SCHED_DEBUG(1, "Device %s is invalid.", name); - gctl_error(req, "Device %s is invalid.", name); - break; - } - - error = g_sched_destroy(gp, *force); - if (error != 0) { - gctl_error(req, "Cannot destroy device %s (error=%d).", - gp->name, error); - break; - } - } -} - -static void -g_sched_config(struct gctl_req *req, struct g_class *mp, const char *verb) -{ - uint32_t *version; - - g_topology_assert(); - - version = gctl_get_paraml(req, "version", sizeof(*version)); - if (version == NULL) { - gctl_error(req, "No '%s' argument.", "version"); - return; - } - - if (*version != G_SCHED_VERSION) { - gctl_error(req, "Userland and kernel parts are " - "out of sync."); - return; - } - - if (strcmp(verb, "create") == 0) { - g_sched_ctl_create(req, mp, 0); - return; - } else if (strcmp(verb, "insert") == 0) { - g_sched_ctl_create(req, mp, 1); - return; - } else if (strcmp(verb, "configure") == 0) { - g_sched_ctl_configure(req, mp); - return; - } else if (strcmp(verb, "destroy") == 0) { - g_sched_ctl_destroy(req, mp); - return; - } - - gctl_error(req, "Unknown verb."); -} - -static void -g_sched_dumpconf(struct sbuf *sb, const char *indent, struct g_geom *gp, - struct g_consumer *cp, struct g_provider *pp) -{ - struct g_sched_softc *sc = gp->softc; - struct g_gsched *gsp = sc->sc_gsched; - if (indent == NULL) { /* plaintext */ - sbuf_printf(sb, " algo %s", gsp ? gsp->gs_name : "--"); - } - if (gsp != NULL && gsp->gs_dumpconf) - gsp->gs_dumpconf(sb, indent, gp, cp, pp); -} - -DECLARE_GEOM_CLASS(g_sched_class, g_sched); -MODULE_VERSION(geom_sched, 0); diff --git a/sys/geom/sched/g_sched.h b/sys/geom/sched/g_sched.h deleted file mode 100644 index d2fcd4933b7..00000000000 --- a/sys/geom/sched/g_sched.h +++ /dev/null @@ -1,126 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2009-2010 Fabio Checconi - * Copyright (c) 2009-2010 Luigi Rizzo, Universita` di Pisa - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#ifndef _G_SCHED_H_ -#define _G_SCHED_H_ - -/* - * $Id$ - * - * Header for the geom_sched class (userland library and kernel part). - * See g_sched.c for documentation. - * The userland code only needs the three G_SCHED_* values below. - */ - -#define G_SCHED_CLASS_NAME "SCHED" -#define G_SCHED_VERSION 0 -#define G_SCHED_SUFFIX ".sched." - -#ifdef _KERNEL -#define G_SCHED_DEBUG(lvl, ...) do { \ - if (me.gs_debug >= (lvl)) { \ - printf("GEOM_SCHED"); \ - if (me.gs_debug > 0) \ - printf("[%u]", lvl); \ - printf(": "); \ - printf(__VA_ARGS__); \ - printf("\n"); \ - } \ -} while (0) - -#define G_SCHED_LOGREQ(bp, ...) do { \ - if (me.gs_debug >= 2) { \ - printf("GEOM_SCHED[2]: "); \ - printf(__VA_ARGS__); \ - printf(" "); \ - g_print_bio(bp); \ - printf("\n"); \ - } \ -} while (0) - -LIST_HEAD(g_hash, g_sched_class); - -/* - * Descriptor of a scheduler. - * In addition to the obvious fields, sc_flushing and sc_pending - * support dynamic switching of scheduling algorithm. - * Normally, sc_flushing is 0, and requests that are scheduled are - * also added to the sc_pending queue, and removed when we receive - * the 'done' event. - * - * When we are transparently inserted on an existing provider, - * sc_proxying is set. The detach procedure is slightly different. - * - * When switching schedulers, sc_flushing is set so requests bypass us, - * and at the same time we update the pointer in the pending bios - * to ignore us when they return up. - * XXX it would be more efficient to implement sc_pending with - * a generation number: the softc generation is increased when - * we change scheduling algorithm, we store the current generation - * number in the pending bios, and when they come back we ignore - * the done() call if the generation number do not match. - */ -struct g_sched_softc { - /* - * Generic fields used by any scheduling algorithm: - * a mutex, the class descriptor, flags, list of pending - * requests (used when flushing the module) and support - * for hash tables where we store per-flow queues. - */ - struct mtx sc_mtx; - struct g_gsched *sc_gsched; /* Scheduler descriptor. */ - int sc_pending; /* Pending requests. */ - int sc_flags; /* Various flags. */ - - /* - * Hash tables to store per-flow queues are generally useful - * so we handle them in the common code. - * sc_hash and sc_mask are parameters of the hash table, - * the last two fields are used to periodically remove - * expired items from the hash table. - */ - struct g_hash *sc_hash; - u_long sc_mask; - int sc_flush_ticks; /* Next tick for a flush. */ - int sc_flush_bucket; /* Next bucket to flush. */ - - /* - * Pointer to the algorithm's private data, which is the value - * returned by sc_gsched->gs_init() . A NULL here means failure. - * XXX intptr_t might be more appropriate. - */ - void *sc_data; -}; - -#define G_SCHED_PROXYING 1 -#define G_SCHED_FLUSHING 2 - -#endif /* _KERNEL */ - -#endif /* _G_SCHED_H_ */ diff --git a/sys/geom/sched/gs_delay.c b/sys/geom/sched/gs_delay.c deleted file mode 100644 index f67be076a48..00000000000 --- a/sys/geom/sched/gs_delay.c +++ /dev/null @@ -1,263 +0,0 @@ -/*- - * Copyright (c) 2015 Netflix, Inc. - * - * Derived from gs_rr.c: - * Copyright (c) 2009-2010 Fabio Checconi - * Copyright (c) 2009-2010 Luigi Rizzo, Universita` di Pisa - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -/* - * $Id$ - * - * A simple scheduler that just delays certain transactions by a certain - * amount. We collect all the transactions that are 'done' and put them on - * a queue. The queue is run through every so often and the transactions that - * have taken longer than the threshold delay are completed. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "gs_scheduler.h" - -/* Useful constants */ -#define BTFRAC_1US 18446744073709ULL /* 2^64 / 1000000 */ - -/* list of scheduler instances */ -LIST_HEAD(g_scheds, g_delay_softc); - -/* - * Per device descriptor, holding the Round Robin list of queues - * accessing the disk, a reference to the geom, and the timer. - */ -struct g_delay_softc { - struct g_geom *sc_geom; - - struct bio_queue_head sc_bioq; /* queue of pending requests */ - struct callout sc_wait; /* timer for completing with delays */ - - /* Statistics */ - int sc_in_flight; /* requests in the driver */ -}; - -/* - * parameters, config and stats - */ -struct g_delay_params { - uint64_t io; - int bypass; /* bypass scheduling */ - int units; /* how many instances */ - int latency; /* How big a latncy are hoping for */ -}; - -static struct g_delay_params me = { - .bypass = 0, - .units = 0, - .latency = 0, - .io = 0, -}; -struct g_delay_params *gs_delay_me = &me; - -SYSCTL_DECL(_kern_geom_sched); -static SYSCTL_NODE(_kern_geom_sched, OID_AUTO, delay, CTLFLAG_RW, 0, - "GEOM_SCHED DELAY stuff"); -SYSCTL_INT(_kern_geom_sched_delay, OID_AUTO, bypass, CTLFLAG_RD, - &me.bypass, 0, "Scheduler bypass"); -SYSCTL_INT(_kern_geom_sched_delay, OID_AUTO, units, CTLFLAG_RD, - &me.units, 0, "Scheduler instances"); -SYSCTL_INT(_kern_geom_sched_delay, OID_AUTO, latency, CTLFLAG_RW, - &me.latency, 0, "Minimum latency for requests, in microseconds (1/hz resolution)"); -SYSCTL_QUAD(_kern_geom_sched_delay, OID_AUTO, io, CTLFLAG_RW, - &me.io, 0, "I/Os delayed\n"); - -static int -g_delay_init_class(void *data, void *priv) -{ - return (0); -} - -static void -g_delay_fini_class(void *data, void *priv) -{ -} - -/* - * Called on a request arrival, timeout or completion. - * Try to serve a request among those queued. - */ -static struct bio * -g_delay_next(void *data, int force) -{ - struct g_delay_softc *sc = data; - struct bio *bp; - struct bintime bt; - - bp = bioq_first(&sc->sc_bioq); - if (bp == NULL) - return (NULL); - - /* - * If the time isn't yet ripe for this bp to be let loose, - * then the time isn't ripe for any of its friends either - * since we insert in-order. Terminate if the bio hasn't - * aged appropriately. Note that there's pathology here - * such that we may be up to one tick early in releasing - * this I/O. We could implement this up to a tick late too - * but choose not to. - */ - getbinuptime(&bt); /* BIO's bio_t0 is uptime */ - if (bintime_cmp(&bp->bio_t0, &bt, >)) - return (NULL); - me.io++; - - /* - * The bp has mellowed enough, let it through and update stats. - * If there's others, we'll catch them next time we get called. - */ - sc->sc_in_flight++; - - bp = bioq_takefirst(&sc->sc_bioq); - return (bp); -} - -/* - * Called when a real request for disk I/O arrives. - * Locate the queue associated with the client. - * If the queue is the one we are anticipating for, reset its timeout; - * if the queue is not in the round robin list, insert it in the list. - * On any error, do not queue the request and return -1, the caller - * will take care of this request. - */ -static int -g_delay_start(void *data, struct bio *bp) -{ - struct g_delay_softc *sc = data; - - if (me.bypass) - return (-1); /* bypass the scheduler */ - - bp->bio_caller1 = sc; - getbinuptime(&bp->bio_t0); /* BIO's bio_t0 is uptime */ - bintime_addx(&bp->bio_t0, BTFRAC_1US * me.latency); - - /* - * Keep the I/Os ordered. Lower layers will reorder as we release them down. - * We rely on this in g_delay_next() so that we delay all things equally. Even - * if we move to multiple queues to push stuff down the stack, we'll want to - * insert in order and let the lower layers do whatever reordering they want. - */ - bioq_insert_tail(&sc->sc_bioq, bp); - - return (0); -} - -static void -g_delay_timeout(void *data) -{ - struct g_delay_softc *sc = data; - - g_sched_lock(sc->sc_geom); - g_sched_dispatch(sc->sc_geom); - g_sched_unlock(sc->sc_geom); - callout_reset(&sc->sc_wait, 1, g_delay_timeout, sc); -} - -/* - * Module glue: allocate descriptor, initialize its fields. - */ -static void * -g_delay_init(struct g_geom *geom) -{ - struct g_delay_softc *sc; - - sc = malloc(sizeof *sc, M_GEOM_SCHED, M_WAITOK | M_ZERO); - sc->sc_geom = geom; - bioq_init(&sc->sc_bioq); - callout_init(&sc->sc_wait, CALLOUT_MPSAFE); - callout_reset(&sc->sc_wait, 1, g_delay_timeout, sc); - me.units++; - - return (sc); -} - -/* - * Module glue -- drain the callout structure, destroy the - * hash table and its element, and free the descriptor. - */ -static void -g_delay_fini(void *data) -{ - struct g_delay_softc *sc = data; - - /* We're force drained before getting here */ - - /* Kick out timers */ - callout_drain(&sc->sc_wait); - me.units--; - free(sc, M_GEOM_SCHED); -} - -/* - * Called when the request under service terminates. - * Start the anticipation timer if needed. - */ -static void -g_delay_done(void *data, struct bio *bp) -{ - struct g_delay_softc *sc = data; - - sc->sc_in_flight--; - - g_sched_dispatch(sc->sc_geom); -} - -static void -g_delay_dumpconf(struct sbuf *sb, const char *indent, struct g_geom *gp, - struct g_consumer *cp, struct g_provider *pp) -{ -} - -static struct g_gsched g_delay = { - .gs_name = "delay", - .gs_priv_size = 0, - .gs_init = g_delay_init, - .gs_fini = g_delay_fini, - .gs_start = g_delay_start, - .gs_done = g_delay_done, - .gs_next = g_delay_next, - .gs_dumpconf = g_delay_dumpconf, - .gs_init_class = g_delay_init_class, - .gs_fini_class = g_delay_fini_class, -}; - -DECLARE_GSCHED_MODULE(delay, &g_delay); diff --git a/sys/geom/sched/gs_rr.c b/sys/geom/sched/gs_rr.c deleted file mode 100644 index 334ba9ab58b..00000000000 --- a/sys/geom/sched/gs_rr.c +++ /dev/null @@ -1,700 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2009-2010 Fabio Checconi - * Copyright (c) 2009-2010 Luigi Rizzo, Universita` di Pisa - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -/* - * $Id$ - * - * A round-robin (RR) anticipatory scheduler, with per-client queues. - * - * The goal of this implementation is to improve throughput compared - * to the pure elevator algorithm, and insure some fairness among - * clients. - * - * Requests coming from the same client are put in the same queue. - * We use anticipation to help reducing seeks, and each queue - * is never served continuously for more than a given amount of - * time or data. Queues are then served in a round-robin fashion. - * - * Each queue can be in any of the following states: - * READY immediately serve the first pending request; - * BUSY one request is under service, wait for completion; - * IDLING do not serve incoming requests immediately, unless - * they are "eligible" as defined later. - * - * Scheduling is made looking at the status of all queues, - * and the first one in round-robin order is privileged. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "gs_scheduler.h" - -/* possible states of the scheduler */ -enum g_rr_state { - G_QUEUE_READY = 0, /* Ready to dispatch. */ - G_QUEUE_BUSY, /* Waiting for a completion. */ - G_QUEUE_IDLING /* Waiting for a new request. */ -}; - -/* possible queue flags */ -enum g_rr_flags { - /* G_FLAG_COMPLETED means that the field q_slice_end is valid. */ - G_FLAG_COMPLETED = 1, /* Completed a req. in the current budget. */ -}; - -struct g_rr_softc; - -/* - * Queue descriptor, containing reference count, scheduling - * state, a queue of pending requests, configuration parameters. - * Queues with pending request(s) and not under service are also - * stored in a Round Robin (RR) list. - */ -struct g_rr_queue { - struct g_rr_softc *q_sc; /* link to the parent */ - - enum g_rr_state q_status; - unsigned int q_service; /* service received so far */ - int q_slice_end; /* actual slice end time, in ticks */ - enum g_rr_flags q_flags; /* queue flags */ - struct bio_queue_head q_bioq; - - /* Scheduling parameters */ - unsigned int q_budget; /* slice size in bytes */ - unsigned int q_slice_duration; /* slice size in ticks */ - unsigned int q_wait_ticks; /* wait time for anticipation */ - - /* Stats to drive the various heuristics. */ - struct g_savg q_thinktime; /* Thinktime average. */ - struct g_savg q_seekdist; /* Seek distance average. */ - - int q_bionum; /* Number of requests. */ - - off_t q_lastoff; /* Last submitted req. offset. */ - int q_lastsub; /* Last submitted req. time. */ - - /* Expiration deadline for an empty queue. */ - int q_expire; - - TAILQ_ENTRY(g_rr_queue) q_tailq; /* RR list link field */ -}; - -/* List types. */ -TAILQ_HEAD(g_rr_tailq, g_rr_queue); - -/* list of scheduler instances */ -LIST_HEAD(g_scheds, g_rr_softc); - -/* Default quantum for RR between queues. */ -#define G_RR_DEFAULT_BUDGET 0x00800000 - -/* - * Per device descriptor, holding the Round Robin list of queues - * accessing the disk, a reference to the geom, and the timer. - */ -struct g_rr_softc { - struct g_geom *sc_geom; - - /* - * sc_active is the queue we are anticipating for. - * It is set only in gs_rr_next(), and possibly cleared - * only in gs_rr_next() or on a timeout. - * The active queue is never in the Round Robin list - * even if it has requests queued. - */ - struct g_rr_queue *sc_active; - struct callout sc_wait; /* timer for sc_active */ - - struct g_rr_tailq sc_rr_tailq; /* the round-robin list */ - int sc_nqueues; /* number of queues */ - - /* Statistics */ - int sc_in_flight; /* requests in the driver */ - - LIST_ENTRY(g_rr_softc) sc_next; -}; - -/* Descriptor for bounded values, min and max are constant. */ -struct x_bound { - const int x_min; - int x_cur; - const int x_max; -}; - -/* - * parameters, config and stats - */ -struct g_rr_params { - int queues; /* total number of queues */ - int w_anticipate; /* anticipate writes */ - int bypass; /* bypass scheduling writes */ - - int units; /* how many instances */ - /* sc_head is used for debugging */ - struct g_scheds sc_head; /* first scheduler instance */ - - struct x_bound queue_depth; /* max parallel requests */ - struct x_bound wait_ms; /* wait time, milliseconds */ - struct x_bound quantum_ms; /* quantum size, milliseconds */ - struct x_bound quantum_kb; /* quantum size, Kb (1024 bytes) */ - - /* statistics */ - int wait_hit; /* success in anticipation */ - int wait_miss; /* failure in anticipation */ -}; - -/* - * Default parameters for the scheduler. The quantum sizes target - * a 80MB/s disk; if the hw is faster or slower the minimum of the - * two will have effect: the clients will still be isolated but - * the fairness may be limited. A complete solution would involve - * the on-line measurement of the actual disk throughput to derive - * these parameters. Or we may just choose to ignore service domain - * fairness and accept what can be achieved with time-only budgets. - */ -static struct g_rr_params me = { - .sc_head = LIST_HEAD_INITIALIZER(&me.sc_head), - .w_anticipate = 1, - .queue_depth = { 1, 1, 50 }, - .wait_ms = { 1, 10, 30 }, - .quantum_ms = { 1, 100, 500 }, - .quantum_kb = { 16, 8192, 65536 }, -}; - -struct g_rr_params *gs_rr_me = &me; - -SYSCTL_DECL(_kern_geom_sched); -static SYSCTL_NODE(_kern_geom_sched, OID_AUTO, rr, CTLFLAG_RW, 0, - "GEOM_SCHED ROUND ROBIN stuff"); -SYSCTL_INT(_kern_geom_sched_rr, OID_AUTO, units, CTLFLAG_RD, - &me.units, 0, "Scheduler instances"); -SYSCTL_INT(_kern_geom_sched_rr, OID_AUTO, queues, CTLFLAG_RD, - &me.queues, 0, "Total rr queues"); -SYSCTL_INT(_kern_geom_sched_rr, OID_AUTO, wait_ms, CTLFLAG_RW, - &me.wait_ms.x_cur, 0, "Wait time milliseconds"); -SYSCTL_INT(_kern_geom_sched_rr, OID_AUTO, quantum_ms, CTLFLAG_RW, - &me.quantum_ms.x_cur, 0, "Quantum size milliseconds"); -SYSCTL_INT(_kern_geom_sched_rr, OID_AUTO, bypass, CTLFLAG_RW, - &me.bypass, 0, "Bypass scheduler"); -SYSCTL_INT(_kern_geom_sched_rr, OID_AUTO, w_anticipate, CTLFLAG_RW, - &me.w_anticipate, 0, "Do anticipation on writes"); -SYSCTL_INT(_kern_geom_sched_rr, OID_AUTO, quantum_kb, CTLFLAG_RW, - &me.quantum_kb.x_cur, 0, "Quantum size Kbytes"); -SYSCTL_INT(_kern_geom_sched_rr, OID_AUTO, queue_depth, CTLFLAG_RW, - &me.queue_depth.x_cur, 0, "Maximum simultaneous requests"); -SYSCTL_INT(_kern_geom_sched_rr, OID_AUTO, wait_hit, CTLFLAG_RW, - &me.wait_hit, 0, "Hits in anticipation"); -SYSCTL_INT(_kern_geom_sched_rr, OID_AUTO, wait_miss, CTLFLAG_RW, - &me.wait_miss, 0, "Misses in anticipation"); - -#ifdef DEBUG_QUEUES -/* print the status of a queue */ -static void -gs_rr_dump_q(struct g_rr_queue *qp, int index) -{ - int l = 0; - struct bio *bp; - - TAILQ_FOREACH(bp, &(qp->q_bioq.queue), bio_queue) { - l++; - } - printf("--- rr queue %d %p status %d len %d ---\n", - index, qp, qp->q_status, l); -} - -/* - * Dump the scheduler status when writing to this sysctl variable. - * XXX right now we only dump the status of the last instance created. - * not a severe issue because this is only for debugging - */ -static int -gs_rr_sysctl_status(SYSCTL_HANDLER_ARGS) -{ - int error, val = 0; - struct g_rr_softc *sc; - - error = sysctl_handle_int(oidp, &val, 0, req); - if (error || !req->newptr ) - return (error); - - printf("called %s\n", __FUNCTION__); - - LIST_FOREACH(sc, &me.sc_head, sc_next) { - int i, tot = 0; - printf("--- sc %p active %p nqueues %d " - "callout %d in_flight %d ---\n", - sc, sc->sc_active, sc->sc_nqueues, - callout_active(&sc->sc_wait), - sc->sc_in_flight); - for (i = 0; i < G_RR_HASH_SIZE; i++) { - struct g_rr_queue *qp; - LIST_FOREACH(qp, &sc->sc_hash[i], q_hash) { - gs_rr_dump_q(qp, tot); - tot++; - } - } - } - return (0); -} - -SYSCTL_PROC(_kern_geom_sched_rr, OID_AUTO, status, - CTLTYPE_UINT | CTLFLAG_RW, - 0, sizeof(int), gs_rr_sysctl_status, "I", "status"); - -#endif /* DEBUG_QUEUES */ - -/* - * Get a bounded value, optionally convert to a min of t_min ticks. - */ -static int -get_bounded(struct x_bound *v, int t_min) -{ - int x; - - x = v->x_cur; - if (x < v->x_min) - x = v->x_min; - else if (x > v->x_max) - x = v->x_max; - if (t_min) { - x = x * hz / 1000; /* convert to ticks */ - if (x < t_min) - x = t_min; - } - return x; -} - -/* - * Get a reference to the queue for bp, using the generic - * classification mechanism. - */ -static struct g_rr_queue * -g_rr_queue_get(struct g_rr_softc *sc, struct bio *bp) -{ - - return (g_sched_get_class(sc->sc_geom, bp)); -} - -static int -g_rr_init_class(void *data, void *priv) -{ - struct g_rr_softc *sc = data; - struct g_rr_queue *qp = priv; - - bioq_init(&qp->q_bioq); - - /* - * Set the initial parameters for the client: - * slice size in bytes and ticks, and wait ticks. - * Right now these are constant, but we could have - * autoconfiguration code to adjust the values based on - * the actual workload. - */ - qp->q_budget = 1024 * get_bounded(&me.quantum_kb, 0); - qp->q_slice_duration = get_bounded(&me.quantum_ms, 2); - qp->q_wait_ticks = get_bounded(&me.wait_ms, 2); - - qp->q_sc = sc; /* link to the parent */ - qp->q_sc->sc_nqueues++; - me.queues++; - - return (0); -} - -/* - * Release a reference to the queue. - */ -static void -g_rr_queue_put(struct g_rr_queue *qp) -{ - - g_sched_put_class(qp->q_sc->sc_geom, qp); -} - -static void -g_rr_fini_class(void *data, void *priv) -{ - struct g_rr_queue *qp = priv; - - KASSERT(bioq_first(&qp->q_bioq) == NULL, - ("released nonempty queue")); - qp->q_sc->sc_nqueues--; - me.queues--; -} - -static inline int -g_rr_queue_expired(struct g_rr_queue *qp) -{ - - if (qp->q_service >= qp->q_budget) - return (1); - - if ((qp->q_flags & G_FLAG_COMPLETED) && - ticks - qp->q_slice_end >= 0) - return (1); - - return (0); -} - -static inline int -g_rr_should_anticipate(struct g_rr_queue *qp, struct bio *bp) -{ - int wait = get_bounded(&me.wait_ms, 2); - - if (!me.w_anticipate && (bp->bio_cmd == BIO_WRITE)) - return (0); - - if (g_savg_valid(&qp->q_thinktime) && - g_savg_read(&qp->q_thinktime) > wait) - return (0); - - if (g_savg_valid(&qp->q_seekdist) && - g_savg_read(&qp->q_seekdist) > 8192) - return (0); - - return (1); -} - -/* - * Called on a request arrival, timeout or completion. - * Try to serve a request among those queued. - */ -static struct bio * -g_rr_next(void *data, int force) -{ - struct g_rr_softc *sc = data; - struct g_rr_queue *qp; - struct bio *bp, *next; - int expired; - - qp = sc->sc_active; - if (me.bypass == 0 && !force) { - if (sc->sc_in_flight >= get_bounded(&me.queue_depth, 0)) - return (NULL); - - /* Try with the queue under service first. */ - if (qp != NULL && qp->q_status != G_QUEUE_READY) { - /* - * Queue is anticipating, ignore request. - * We should check that we are not past - * the timeout, but in that case the timeout - * will fire immediately afterwards so we - * don't bother. - */ - return (NULL); - } - } else if (qp != NULL && qp->q_status != G_QUEUE_READY) { - g_rr_queue_put(qp); - sc->sc_active = qp = NULL; - } - - /* - * No queue under service, look for the first in RR order. - * If we find it, select if as sc_active, clear service - * and record the end time of the slice. - */ - if (qp == NULL) { - qp = TAILQ_FIRST(&sc->sc_rr_tailq); - if (qp == NULL) - return (NULL); /* no queues at all, return */ - /* otherwise select the new queue for service. */ - TAILQ_REMOVE(&sc->sc_rr_tailq, qp, q_tailq); - sc->sc_active = qp; - qp->q_service = 0; - qp->q_flags &= ~G_FLAG_COMPLETED; - } - - bp = bioq_takefirst(&qp->q_bioq); /* surely not NULL */ - qp->q_service += bp->bio_length; /* charge the service */ - - /* - * The request at the head of the active queue is always - * dispatched, and gs_rr_next() will be called again - * immediately. - * We need to prepare for what to do next: - * - * 1. have we reached the end of the (time or service) slice ? - * If so, clear sc_active and possibly requeue the previous - * active queue if it has more requests pending; - * 2. do we have more requests in sc_active ? - * If yes, do not anticipate, as gs_rr_next() will run again; - * if no, decide whether or not to anticipate depending - * on read or writes (e.g., anticipate only on reads). - */ - expired = g_rr_queue_expired(qp); /* are we expired ? */ - next = bioq_first(&qp->q_bioq); /* do we have one more ? */ - if (expired) { - sc->sc_active = NULL; - /* Either requeue or release reference. */ - if (next != NULL) - TAILQ_INSERT_TAIL(&sc->sc_rr_tailq, qp, q_tailq); - else - g_rr_queue_put(qp); - } else if (next != NULL) { - qp->q_status = G_QUEUE_READY; - } else { - if (!force && g_rr_should_anticipate(qp, bp)) { - /* anticipate */ - qp->q_status = G_QUEUE_BUSY; - } else { - /* do not anticipate, release reference */ - g_rr_queue_put(qp); - sc->sc_active = NULL; - } - } - /* If sc_active != NULL, its q_status is always correct. */ - - sc->sc_in_flight++; - - return (bp); -} - -static inline void -g_rr_update_thinktime(struct g_rr_queue *qp) -{ - int delta = ticks - qp->q_lastsub, wait = get_bounded(&me.wait_ms, 2); - - if (qp->q_sc->sc_active != qp) - return; - - qp->q_lastsub = ticks; - delta = (delta > 2 * wait) ? 2 * wait : delta; - if (qp->q_bionum > 7) - g_savg_add_sample(&qp->q_thinktime, delta); -} - -static inline void -g_rr_update_seekdist(struct g_rr_queue *qp, struct bio *bp) -{ - off_t dist; - - if (qp->q_lastoff > bp->bio_offset) - dist = qp->q_lastoff - bp->bio_offset; - else - dist = bp->bio_offset - qp->q_lastoff; - - if (dist > (8192 * 8)) - dist = 8192 * 8; - - qp->q_lastoff = bp->bio_offset + bp->bio_length; - - if (qp->q_bionum > 7) - g_savg_add_sample(&qp->q_seekdist, dist); -} - -/* - * Called when a real request for disk I/O arrives. - * Locate the queue associated with the client. - * If the queue is the one we are anticipating for, reset its timeout; - * if the queue is not in the round robin list, insert it in the list. - * On any error, do not queue the request and return -1, the caller - * will take care of this request. - */ -static int -g_rr_start(void *data, struct bio *bp) -{ - struct g_rr_softc *sc = data; - struct g_rr_queue *qp; - - if (me.bypass) - return (-1); /* bypass the scheduler */ - - /* Get the queue for the request. */ - qp = g_rr_queue_get(sc, bp); - if (qp == NULL) - return (-1); /* allocation failed, tell upstream */ - - if (bioq_first(&qp->q_bioq) == NULL) { - /* - * We are inserting into an empty queue. - * Reset its state if it is sc_active, - * otherwise insert it in the RR list. - */ - if (qp == sc->sc_active) { - qp->q_status = G_QUEUE_READY; - callout_stop(&sc->sc_wait); - } else { - g_sched_priv_ref(qp); - TAILQ_INSERT_TAIL(&sc->sc_rr_tailq, qp, q_tailq); - } - } - - qp->q_bionum = 1 + qp->q_bionum - (qp->q_bionum >> 3); - - g_rr_update_thinktime(qp); - g_rr_update_seekdist(qp, bp); - - /* Inherit the reference returned by g_rr_queue_get(). */ - bp->bio_caller1 = qp; - bioq_disksort(&qp->q_bioq, bp); - - return (0); -} - -/* - * Callout executed when a queue times out anticipating a new request. - */ -static void -g_rr_wait_timeout(void *data) -{ - struct g_rr_softc *sc = data; - struct g_geom *geom = sc->sc_geom; - - g_sched_lock(geom); - /* - * We can race with other events, so check if - * sc_active is still valid. - */ - if (sc->sc_active != NULL) { - /* Release the reference to the queue. */ - g_rr_queue_put(sc->sc_active); - sc->sc_active = NULL; - me.wait_hit--; - me.wait_miss++; /* record the miss */ - } - g_sched_dispatch(geom); - g_sched_unlock(geom); -} - -/* - * Module glue: allocate descriptor, initialize its fields. - */ -static void * -g_rr_init(struct g_geom *geom) -{ - struct g_rr_softc *sc; - - /* XXX check whether we can sleep */ - sc = malloc(sizeof *sc, M_GEOM_SCHED, M_NOWAIT | M_ZERO); - sc->sc_geom = geom; - TAILQ_INIT(&sc->sc_rr_tailq); - callout_init(&sc->sc_wait, 1); - LIST_INSERT_HEAD(&me.sc_head, sc, sc_next); - me.units++; - - return (sc); -} - -/* - * Module glue -- drain the callout structure, destroy the - * hash table and its element, and free the descriptor. - */ -static void -g_rr_fini(void *data) -{ - struct g_rr_softc *sc = data; - - callout_drain(&sc->sc_wait); - KASSERT(sc->sc_active == NULL, ("still a queue under service")); - KASSERT(TAILQ_EMPTY(&sc->sc_rr_tailq), ("still scheduled queues")); - - LIST_REMOVE(sc, sc_next); - me.units--; - free(sc, M_GEOM_SCHED); -} - -/* - * Called when the request under service terminates. - * Start the anticipation timer if needed. - */ -static void -g_rr_done(void *data, struct bio *bp) -{ - struct g_rr_softc *sc = data; - struct g_rr_queue *qp; - - sc->sc_in_flight--; - - qp = bp->bio_caller1; - - /* - * When the first request for this queue completes, update the - * duration and end of the slice. We do not do it when the - * slice starts to avoid charging to the queue the time for - * the first seek. - */ - if (!(qp->q_flags & G_FLAG_COMPLETED)) { - qp->q_flags |= G_FLAG_COMPLETED; - /* - * recompute the slice duration, in case we want - * to make it adaptive. This is not used right now. - * XXX should we do the same for q_quantum and q_wait_ticks ? - */ - qp->q_slice_duration = get_bounded(&me.quantum_ms, 2); - qp->q_slice_end = ticks + qp->q_slice_duration; - } - - if (qp == sc->sc_active && qp->q_status == G_QUEUE_BUSY) { - /* The queue is trying anticipation, start the timer. */ - qp->q_status = G_QUEUE_IDLING; - /* may make this adaptive */ - qp->q_wait_ticks = get_bounded(&me.wait_ms, 2); - me.wait_hit++; - callout_reset(&sc->sc_wait, qp->q_wait_ticks, - g_rr_wait_timeout, sc); - } else - g_sched_dispatch(sc->sc_geom); - - /* Release a reference to the queue. */ - g_rr_queue_put(qp); -} - -static void -g_rr_dumpconf(struct sbuf *sb, const char *indent, struct g_geom *gp, - struct g_consumer *cp, struct g_provider *pp) -{ - if (indent == NULL) { /* plaintext */ - sbuf_printf(sb, " units %d queues %d", - me.units, me.queues); - } -} - -static struct g_gsched g_rr = { - .gs_name = "rr", - .gs_priv_size = sizeof(struct g_rr_queue), - .gs_init = g_rr_init, - .gs_fini = g_rr_fini, - .gs_start = g_rr_start, - .gs_done = g_rr_done, - .gs_next = g_rr_next, - .gs_dumpconf = g_rr_dumpconf, - .gs_init_class = g_rr_init_class, - .gs_fini_class = g_rr_fini_class, -}; - -DECLARE_GSCHED_MODULE(rr, &g_rr); diff --git a/sys/geom/sched/gs_scheduler.h b/sys/geom/sched/gs_scheduler.h deleted file mode 100644 index 70b7438d809..00000000000 --- a/sys/geom/sched/gs_scheduler.h +++ /dev/null @@ -1,238 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2009-2010 Fabio Checconi - * Copyright (c) 2009-2010 Luigi Rizzo, Universita` di Pisa - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -/* - * $Id$ - * - * Prototypes for GEOM-based disk scheduling algorithms. - * See g_sched.c for generic documentation. - * - * This file is used by the kernel modules implementing the various - * scheduling algorithms. They should provide all the methods - * defined in struct g_gsched, and also invoke the macro - * DECLARE_GSCHED_MODULE - * which registers the scheduling algorithm with the geom_sched module. - * - * The various scheduling algorithms do not need to know anything - * about geom, they only need to handle the 'bio' requests they - * receive, pass them down when needed, and use the locking interface - * defined below. - */ - -#ifndef _G_GSCHED_H_ -#define _G_GSCHED_H_ - -#ifdef _KERNEL -#include -#include -#include -#include -#include -#include -#include "g_sched.h" - -/* - * This is the interface exported to scheduling modules. - * - * gs_init() is called when our scheduling algorithm - * starts being used by a geom 'sched' - * - * gs_fini() is called when the algorithm is released. - * - * gs_start() is called when a new request comes in. It should - * enqueue the request and return 0 if success, or return non-zero - * in case of failure (meaning the request is passed down). - * The scheduler can use bio->bio_caller1 to store a non-null - * pointer meaning the request is under its control. - * - * gs_next() is called in a loop by g_sched_dispatch(), right after - * gs_start(), or on timeouts or 'done' events. It should return - * immediately, either a pointer to the bio to be served or NULL - * if no bio should be served now. If force is specified, a - * work-conserving behavior is expected. - * - * gs_done() is called when a request under service completes. - * In turn the scheduler may decide to call the dispatch loop - * to serve other pending requests (or make sure there is a pending - * timeout to avoid stalls). - * - * gs_init_class() is called when a new client (as determined by - * the classifier) starts being used. - * - * gs_hash_unref() is called right before the class hashtable is - * destroyed; after this call, the scheduler is supposed to hold no - * more references to the elements in the table. - */ - -/* Forward declarations for prototypes. */ -struct g_geom; -struct g_sched_class; - -typedef void *gs_init_t (struct g_geom *geom); -typedef void gs_fini_t (void *data); -typedef int gs_start_t (void *data, struct bio *bio); -typedef void gs_done_t (void *data, struct bio *bio); -typedef struct bio *gs_next_t (void *data, int force); -typedef int gs_init_class_t (void *data, void *priv); -typedef void gs_fini_class_t (void *data, void *priv); -typedef void gs_hash_unref_t (void *data); - -struct g_gsched { - const char *gs_name; - int gs_refs; - int gs_priv_size; - - gs_init_t *gs_init; - gs_fini_t *gs_fini; - gs_start_t *gs_start; - gs_done_t *gs_done; - gs_next_t *gs_next; - g_dumpconf_t *gs_dumpconf; - - gs_init_class_t *gs_init_class; - gs_fini_class_t *gs_fini_class; - gs_hash_unref_t *gs_hash_unref; - - LIST_ENTRY(g_gsched) glist; -}; - -#define KTR_GSCHED KTR_SPARE4 - -MALLOC_DECLARE(M_GEOM_SCHED); - -/* - * Basic classification mechanism. Each request is associated to - * a g_sched_class, and each scheduler has the opportunity to set - * its own private data for the given (class, geom) pair. The - * private data have a base type of g_sched_private, and are - * extended at the end with the actual private fields of each - * scheduler. - */ -struct g_sched_class { - int gsc_refs; - int gsc_expire; - u_long gsc_key; - LIST_ENTRY(g_sched_class) gsc_clist; - - void *gsc_priv[0]; -}; - -/* - * Manipulate the classifier's data. g_sched_get_class() gets a reference - * to the class corresponding to bp in gp, allocating and initializing - * it if necessary. g_sched_put_class() releases the reference. - * The returned value points to the private data for the class. - */ -void *g_sched_get_class(struct g_geom *gp, struct bio *bp); -void g_sched_put_class(struct g_geom *gp, void *priv); - -static inline struct g_sched_class * -g_sched_priv2class(void *priv) -{ - - return ((struct g_sched_class *)((u_long)priv - - offsetof(struct g_sched_class, gsc_priv))); -} - -static inline void -g_sched_priv_ref(void *priv) -{ - struct g_sched_class *gsc; - - gsc = g_sched_priv2class(priv); - gsc->gsc_refs++; -} - -/* - * Locking interface. When each operation registered with the - * scheduler is invoked, a per-instance lock is taken to protect - * the data associated with it. If the scheduler needs something - * else to access the same data (e.g., a callout) it must use - * these functions. - */ -void g_sched_lock(struct g_geom *gp); -void g_sched_unlock(struct g_geom *gp); - -/* - * Restart request dispatching. Must be called with the per-instance - * mutex held. - */ -void g_sched_dispatch(struct g_geom *geom); - -/* - * Simple gathering of statistical data, used by schedulers to collect - * info on process history. Just keep an exponential average of the - * samples, with some extra bits of precision. - */ -struct g_savg { - uint64_t gs_avg; - unsigned int gs_smpl; -}; - -static inline void -g_savg_add_sample(struct g_savg *ss, uint64_t sample) -{ - - /* EMA with alpha = 0.125, fixed point, 3 bits of precision. */ - ss->gs_avg = sample + ss->gs_avg - (ss->gs_avg >> 3); - ss->gs_smpl = 1 + ss->gs_smpl - (ss->gs_smpl >> 3); -} - -static inline int -g_savg_valid(struct g_savg *ss) -{ - - /* We want at least 8 samples to deem an average as valid. */ - return (ss->gs_smpl > 7); -} - -static inline uint64_t -g_savg_read(struct g_savg *ss) -{ - - return (ss->gs_avg / ss->gs_smpl); -} - -/* - * Declaration of a scheduler module. - */ -int g_gsched_modevent(module_t mod, int cmd, void *arg); - -#define DECLARE_GSCHED_MODULE(name, gsched) \ - static moduledata_t name##_mod = { \ - #name, \ - g_gsched_modevent, \ - gsched, \ - }; \ - DECLARE_MODULE(name, name##_mod, SI_SUB_DRIVERS, SI_ORDER_MIDDLE); \ - MODULE_DEPEND(name, geom_sched, 0, 0, 0); - -#endif /* _KERNEL */ - -#endif /* _G_GSCHED_H_ */ diff --git a/sys/gnu/dts/FreeBSD-list b/sys/gnu/dts/FreeBSD-list deleted file mode 100644 index ed06978a34e..00000000000 --- a/sys/gnu/dts/FreeBSD-list +++ /dev/null @@ -1,76 +0,0 @@ -# Files to include in the import and merging.... -src/arm/animeo_ip.dts -src/arm/at91-ariag25.dts -src/arm/at91-cosino.dtsi -src/arm/at91-cosino_mega2560.dts -src/arm/at91-foxg20.dts -src/arm/at91-qil_a9260.dts -src/arm/at91-sama5d3_xplained.dts -src/arm/at91rm9200.dtsi -src/arm/at91rm9200_pqfp.dtsi -src/arm/at91rm9200ek.dts -src/arm/at91sam9260.dtsi -src/arm/at91sam9263.dtsi -src/arm/at91sam9263ek.dts -src/arm/at91sam9g15.dtsi -src/arm/at91sam9g15ek.dts -src/arm/at91sam9g20.dtsi -src/arm/at91sam9g20ek.dts -src/arm/at91sam9g20ek_2mmc.dts -src/arm/at91sam9g20ek_common.dtsi -src/arm/at91sam9g25.dtsi -src/arm/at91sam9g25ek.dts -src/arm/at91sam9g35.dtsi -src/arm/at91sam9g35ek.dts -src/arm/at91sam9g45.dtsi -src/arm/at91sam9m10g45ek.dts -src/arm/at91sam9n12.dtsi -src/arm/at91sam9n12ek.dts -src/arm/at91sam9x25.dtsi -src/arm/at91sam9x25ek.dts -src/arm/at91sam9x35.dtsi -src/arm/at91sam9x35ek.dts -src/arm/at91sam9x5.dtsi -src/arm/at91sam9x5_macb0.dtsi -src/arm/at91sam9x5_macb1.dtsi -src/arm/at91sam9x5_usart3.dtsi -src/arm/at91sam9x5cm.dtsi -src/arm/at91sam9x5ek.dtsi -src/arm/ethernut5.dts -src/arm/evk-pro3.dts -src/arm/ge863-pro3.dtsi -src/arm/kizbox.dts -src/arm/mpa1600.dts -src/arm/pm9g45.dts -src/arm/sama5d3.dtsi -src/arm/sama5d31.dtsi -src/arm/sama5d31ek.dts -src/arm/sama5d33.dtsi -src/arm/sama5d33ek.dts -src/arm/sama5d34.dtsi -src/arm/sama5d34ek.dts -src/arm/sama5d35.dtsi -src/arm/sama5d35ek.dts -src/arm/sama5d36.dtsi -src/arm/sama5d36ek.dts -src/arm/sama5d3_can.dtsi -src/arm/sama5d3_emac.dtsi -src/arm/sama5d3_gmac.dtsi -src/arm/sama5d3_lcd.dtsi -src/arm/sama5d3_mci2.dtsi -src/arm/sama5d3_tcb1.dtsi -src/arm/sama5d3_uart.dtsi -src/arm/sama5d3xcm.dtsi -src/arm/sama5d3xdm.dtsi -src/arm/sama5d3xmb.dtsi -src/arm/skeleton.dtsi -src/arm/tny_a9260.dts -src/arm/tny_a9260_common.dtsi -src/arm/tny_a9263.dts -src/arm/tny_a9g20.dts -src/arm/usb_a9260.dts -src/arm/usb_a9260_common.dtsi -src/arm/usb_a9263.dts -src/arm/usb_a9g20.dts -src/arm/usb_a9g20_common.dtsi -src/arm/usb_a9g20_lpw.dts diff --git a/sys/gnu/dts/FreeBSD-upgrade b/sys/gnu/dts/FreeBSD-upgrade deleted file mode 100644 index b0338bffe68..00000000000 --- a/sys/gnu/dts/FreeBSD-upgrade +++ /dev/null @@ -1,23 +0,0 @@ -#/bin/sh -# -# These files are imported from Ian Campbell's git tree mirroring the linux -# kernel. -# -# git clone git://xenbits.xen.org/people/ianc/device-tree-rebasing.git -# -# will grab the latest tree. It is imported into vendor/device-tree/dist and tagged -# with the svn cp command, per the handbook. -# -# We only import those files from here that we know work with some kernel, rather than -# all of them. This means we have an 'opt in' list rather than an 'opt out' list -# that's more typical for FreeBSD. The opt-in list should be relative to the top level -# directory (so a bunch of lines starting with src). We import src/$ARCH/foo into -# sys/gnu/dts/$ARCH/foo with the goal being to use as many of these files as possible -# unmodified for FreeBSD. This isn't always possible, but there are workarounds. -# -# This script should take care of all that the first time... - -s=svn+ssh://svn.freebsd.org/base/vendor/device-tree/dist/ - -args=$(grep -v ^# FreeBSD-list | sed -e"s=^=$s=") -svn cp -m "Initial import of DTS files from Linux" ${args} svn+ssh://svn.freebsd.org/base/head/sys/gnu/dts/arm diff --git a/sys/gnu/dts/arm/aks-cdu.dts b/sys/gnu/dts/arm/aks-cdu.dts deleted file mode 100644 index 742fcf525e1..00000000000 --- a/sys/gnu/dts/arm/aks-cdu.dts +++ /dev/null @@ -1,122 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * aks-cdu.dts - Device Tree file for AK signal CDU - * - * Copyright (C) 2012 AK signal Brno a.s. - * 2012 Jiri Prchal - */ - -/dts-v1/; - -#include "ge863-pro3.dtsi" - -/ { - chosen { - bootargs = "console=ttyS0,115200 ubi.mtd=4 root=ubi0:rootfs rootfstype=ubifs"; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - }; - - ahb { - apb { - usart0: serial@fffb0000 { - status = "okay"; - }; - - usart1: serial@fffb4000 { - status = "okay"; - linux,rs485-enabled-at-boot-time; - rs485-rts-delay = <0 0>; - }; - - usart2: serial@fffb8000 { - status = "okay"; - linux,rs485-enabled-at-boot-time; - rs485-rts-delay = <0 0>; - }; - - usart3: serial@fffd0000 { - status = "okay"; - linux,rs485-enabled-at-boot-time; - rs485-rts-delay = <0 0>; - }; - - macb0: ethernet@fffc4000 { - phy-mode = "rmii"; - status = "okay"; - }; - - usb1: gadget@fffa4000 { - atmel,vbus-gpio = <&pioC 15 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - }; - - usb0: ohci@500000 { - num-ports = <2>; - status = "okay"; - }; - - ebi: ebi@10000000 { - nand_controller: nand-controller { - nand: nand@3 { - partitions { - bootstrap@0 { - label = "bootstrap"; - reg = <0x0 0x40000>; - }; - - uboot@40000 { - label = "uboot"; - reg = <0x40000 0x80000>; - }; - - ubootenv@c0000 { - label = "ubootenv"; - reg = <0xc0000 0x40000>; - }; - - kernel@100000 { - label = "kernel"; - reg = <0x100000 0x400000>; - }; - - rootfs@500000 { - label = "rootfs"; - reg = <0x500000 0x7b00000>; - }; - }; - }; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - red { - gpios = <&pioC 10 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "none"; - }; - - green { - gpios = <&pioA 5 GPIO_ACTIVE_LOW>; - linux,default-trigger = "none"; - default-state = "on"; - }; - - yellow { - gpios = <&pioB 20 GPIO_ACTIVE_LOW>; - linux,default-trigger = "none"; - }; - - blue { - gpios = <&pioB 21 GPIO_ACTIVE_LOW>; - linux,default-trigger = "none"; - }; - }; -}; diff --git a/sys/gnu/dts/arm/alphascale-asm9260-devkit.dts b/sys/gnu/dts/arm/alphascale-asm9260-devkit.dts deleted file mode 100644 index c77e2c902fb..00000000000 --- a/sys/gnu/dts/arm/alphascale-asm9260-devkit.dts +++ /dev/null @@ -1,13 +0,0 @@ -/* - * Copyright 2014 Oleksij Rempel - * - * Licensed under the X11 license or the GPL v2 (or later) - */ - -/dts-v1/; -#include "alphascale-asm9260.dtsi" - -/ { - model = "Alphascale asm9260 Development Kit"; - compatible = "alphascale,asm9260devkit", "alphascale,asm9260"; -}; diff --git a/sys/gnu/dts/arm/alphascale-asm9260.dtsi b/sys/gnu/dts/arm/alphascale-asm9260.dtsi deleted file mode 100644 index 2ce6038536f..00000000000 --- a/sys/gnu/dts/arm/alphascale-asm9260.dtsi +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Copyright 2014 Oleksij Rempel - * - * Licensed under the X11 license or the GPL v2 (or later) - */ - -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&icoll>; - - memory { - device_type = "memory"; - reg = <0x20000000 0x2000000>; - }; - - cpus { - #address-cells = <0>; - #size-cells = <0>; - - cpu { - compatible = "arm,arm926ej-s"; - device_type = "cpu"; - clocks = <&acc CLKID_SYS_CPU>; - }; - }; - - osc24m: oscillator { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-accuracy = <30000>; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges; - - acc: clock-controller@80040000 { - compatible = "alphascale,asm9260-clock-controller"; - #clock-cells = <1>; - clocks = <&osc24m>; - reg = <0x80040000 0x204>; - }; - - icoll: interrupt-controller@80054000 { - compatible = "alphascale,asm9260-icoll"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x80054000 0x200>; - }; - - timer0: timer@80088000 { - compatible = "alphascale,asm9260-timer"; - reg = <0x80088000 0x4000>; - clocks = <&acc CLKID_AHB_TIMER0>; - interrupts = <29>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/alpine-db.dts b/sys/gnu/dts/arm/alpine-db.dts deleted file mode 100644 index dfb5a080227..00000000000 --- a/sys/gnu/dts/arm/alpine-db.dts +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright 2015 Annapurna Labs Ltd. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * Alternatively, redistribution and use in source and binary forms, with or - * without modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - */ - -/dts-v1/; - -#include "alpine.dtsi" - -/ { - model = "Annapurna Labs Alpine Dev Board"; - /* no need for anything outside SOC */ -}; - diff --git a/sys/gnu/dts/arm/alpine.dtsi b/sys/gnu/dts/arm/alpine.dtsi deleted file mode 100644 index d3036ea823d..00000000000 --- a/sys/gnu/dts/arm/alpine.dtsi +++ /dev/null @@ -1,176 +0,0 @@ -/* - * Copyright 2015 Annapurna Labs Ltd. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * Alternatively, redistribution and use in source and binary forms, with or - * without modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - */ - -#include - -/ { - #address-cells = <2>; - #size-cells = <2>; - /* SOC compatibility */ - compatible = "al,alpine"; - - memory { - device_type = "memory"; - reg = <0 0 0 0>; - }; - - /* CPU Configuration */ - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "al,alpine-smp"; - - cpu@0 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <0>; - clock-frequency = <1700000000>; - }; - - cpu@1 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <1>; - clock-frequency = <1700000000>; - }; - - cpu@2 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <2>; - clock-frequency = <1700000000>; - }; - - cpu@3 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <3>; - clock-frequency = <1700000000>; - }; - }; - - soc { - #address-cells = <2>; - #size-cells = <2>; - compatible = "simple-bus"; - interrupt-parent = <&gic>; - ranges; - - arch-timer { - compatible = "arm,cortex-a15-timer", - "arm,armv7-timer"; - interrupts = - , - , - , - ; - clock-frequency = <50000000>; - }; - - /* Interrupt Controller */ - gic: gic@fb001000 { - compatible = "arm,cortex-a15-gic"; - #interrupt-cells = <3>; - #size-cells = <0>; - #address-cells = <0>; - interrupt-controller; - reg = <0x0 0xfb001000 0x0 0x1000>, - <0x0 0xfb002000 0x0 0x2000>, - <0x0 0xfb004000 0x0 0x2000>, - <0x0 0xfb006000 0x0 0x2000>; - interrupts = - ; - }; - - /* CPU Resume registers */ - cpu-resume@fbff5ec0 { - compatible = "al,alpine-cpu-resume"; - reg = <0x0 0xfbff5ec0 0x0 0x30>; - }; - - /* North Bridge Service Registers */ - sysfabric-service@fb070000 { - compatible = "al,alpine-sysfabric-service", "syscon"; - reg = <0x0 0xfb070000 0x0 0x10000>; - }; - - /* Performance Monitor Unit */ - pmu { - compatible = "arm,cortex-a15-pmu"; - interrupts = , - , - , - ; - }; - - uart0: uart@fd883000 { - compatible = "ns16550a"; - reg = <0x0 0xfd883000 0x0 0x1000>; - clock-frequency = <375000000>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - }; - - uart1: uart@fd884000 { - compatible = "ns16550a"; - reg = <0x0 0xfd884000 0x0 0x1000>; - clock-frequency = <375000000>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - }; - - /* Internal PCIe Controller */ - pcie@fbc00000 { - compatible = "pci-host-ecam-generic"; - device_type = "pci"; - #size-cells = <2>; - #address-cells = <3>; - #interrupt-cells = <1>; - reg = <0x0 0xfbc00000 0x0 0x100000>; - interrupt-map-mask = <0xf800 0 0 7>; - /* Add legacy interrupts for SATA devices only */ - interrupt-map = <0x4000 0 0 1 &gic 0 43 4>, - <0x4800 0 0 1 &gic 0 44 4>; - - /* 32 bit non prefetchable memory space */ - ranges = <0x02000000 0x0 0xfe000000 0x0 0xfe000000 0x0 0x1000000>; - - bus-range = <0x00 0x00>; - msi-parent = <&msix>; - }; - - msix: msix@fbe00000 { - compatible = "al,alpine-msix"; - reg = <0x0 0xfbe00000 0x0 0x100000>; - interrupt-controller; - msi-controller; - al,msi-base-spi = <96>; - al,msi-num-spis = <64>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/am335x-baltos-ir2110.dts b/sys/gnu/dts/arm/am335x-baltos-ir2110.dts deleted file mode 100644 index 386d5f89978..00000000000 --- a/sys/gnu/dts/arm/am335x-baltos-ir2110.dts +++ /dev/null @@ -1,83 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ - */ - -/* - * VScom OnRISC - * http://www.vscom.de - */ - -/dts-v1/; - -#include "am335x-baltos.dtsi" -#include "am335x-baltos-leds.dtsi" - -/ { - model = "OnRISC Baltos iR 2110"; -}; - -&am33xx_pinmux { - uart1_pins: pinmux_uart1_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_INPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* lcd_vsync.gpio2[22] DTR */ - AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_hsync.gpio2[23] DSR */ - AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_pclk.gpio2[24] DCD */ - AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_ac_bias_en.gpio2[25] RI */ - >; - }; - - mmc1_pins: pinmux_mmc1_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT, MUX_MODE7) /* MMC1 CD */ - >; - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; - dtr-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>; - dsr-gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; - dcd-gpios = <&gpio2 24 GPIO_ACTIVE_LOW>; - rng-gpios = <&gpio2 25 GPIO_ACTIVE_LOW>; - - status = "okay"; -}; - -&usb0_phy { - status = "okay"; -}; - -&usb0 { - status = "okay"; - dr_mode = "host"; -}; - -&davinci_mdio { - phy0: ethernet-phy@0 { - reg = <1>; - }; -}; - -&cpsw_emac0 { - phy-mode = "rmii"; - dual_emac_res_vlan = <1>; - phy-handle = <&phy0>; -}; - -&cpsw_emac1 { - phy-mode = "rgmii-id"; - dual_emac_res_vlan = <2>; - phy-handle = <&phy1>; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; -}; diff --git a/sys/gnu/dts/arm/am335x-baltos-ir3220.dts b/sys/gnu/dts/arm/am335x-baltos-ir3220.dts deleted file mode 100644 index b0df7256db1..00000000000 --- a/sys/gnu/dts/arm/am335x-baltos-ir3220.dts +++ /dev/null @@ -1,125 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ - */ - -/* - * VScom OnRISC - * http://www.vscom.de - */ - -/dts-v1/; - -#include "am335x-baltos.dtsi" -#include "am335x-baltos-leds.dtsi" - -/ { - model = "OnRISC Baltos iR 3220"; -}; - -&am33xx_pinmux { - tca6416_pins: pinmux_tca6416_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_INPUT_PULLUP, MUX_MODE7) /* xdma_event_intr1.gpio0[20] tca6416 stuff */ - >; - }; - - uart1_pins: pinmux_uart1_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_INPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* lcd_vsync.gpio2[22] DTR */ - AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_hsync.gpio2[23] DSR */ - AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_pclk.gpio2[24] DCD */ - AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_ac_bias_en.gpio2[25] RI */ - >; - }; - - uart2_pins: pinmux_uart2_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE1) /* spi0_sclk.uart2_rxd_mux3 */ - AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT, MUX_MODE1) /* spi0_d0.uart2_txd_mux3 */ - AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLDOWN, MUX_MODE2) /* i2c0_sda.uart2_ctsn_mux0 */ - AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* i2c0_scl.uart2_rtsn_mux0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad12.gpio1[12] DTR */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad13.gpio1[13] DSR */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad14.gpio1[14] DCD */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad15.gpio1[15] RI */ - - AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT_PULLUP, MUX_MODE7) /* mcasp0_aclkr.gpio3[18], INPUT_PULLDOWN | MODE7 */ - >; - }; - - mmc1_pins: pinmux_mmc1_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT, MUX_MODE7) /* MMC1 CD */ - >; - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; - dtr-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>; - dsr-gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; - dcd-gpios = <&gpio2 24 GPIO_ACTIVE_LOW>; - rng-gpios = <&gpio2 25 GPIO_ACTIVE_LOW>; - - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; - dtr-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; - dsr-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; - dcd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; - rng-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; - - status = "okay"; -}; - -&i2c1 { - tca6416: gpio@20 { - compatible = "ti,tca6416"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&gpio0>; - interrupts = <20 IRQ_TYPE_EDGE_RISING>; - pinctrl-names = "default"; - pinctrl-0 = <&tca6416_pins>; - }; -}; - -&usb0_phy { - status = "okay"; -}; - -&usb0 { - status = "okay"; - dr_mode = "host"; -}; - -&cpsw_emac0 { - phy-mode = "rmii"; - dual_emac_res_vlan = <1>; - fixed-link { - speed = <100>; - full-duplex; - }; -}; - -&cpsw_emac1 { - phy-mode = "rgmii-id"; - dual_emac_res_vlan = <2>; - phy-handle = <&phy1>; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - cd-gpios = <&gpio2 18 GPIO_ACTIVE_LOW>; -}; diff --git a/sys/gnu/dts/arm/am335x-baltos-ir5221.dts b/sys/gnu/dts/arm/am335x-baltos-ir5221.dts deleted file mode 100644 index d6aa46e8700..00000000000 --- a/sys/gnu/dts/arm/am335x-baltos-ir5221.dts +++ /dev/null @@ -1,149 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ - */ - -/* - * VScom OnRISC - * http://www.vscom.de - */ - -/dts-v1/; - -#include "am335x-baltos.dtsi" -#include "am335x-baltos-leds.dtsi" - -/ { - model = "OnRISC Baltos iR 5221"; -}; - -&am33xx_pinmux { - tca6416_pins: pinmux_tca6416_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_INPUT_PULLUP, MUX_MODE7) /* xdma_event_intr1.gpio0[20] tca6416 stuff */ - >; - }; - - - dcan1_pins: pinmux_dcan1_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT, MUX_MODE2) /* uart0_ctsn.dcan1_tx_mux0 */ - AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT, MUX_MODE2) /* uart0_rtsn.dcan1_rx_mux0 */ - >; - }; - - uart1_pins: pinmux_uart1_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_INPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* lcd_vsync.gpio2[22] DTR */ - AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_hsync.gpio2[23] DSR */ - AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_pclk.gpio2[24] DCD */ - AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_ac_bias_en.gpio2[25] RI */ - >; - }; - - uart2_pins: pinmux_uart2_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE1) /* spi0_sclk.uart2_rxd_mux3 */ - AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT, MUX_MODE1) /* spi0_d0.uart2_txd_mux3 */ - AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLDOWN, MUX_MODE2) /* i2c0_sda.uart2_ctsn_mux0 */ - AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* i2c0_scl.uart2_rtsn_mux0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad12.gpio1[12] DTR */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad13.gpio1[13] DSR */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad14.gpio1[14] DCD */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad15.gpio1[15] RI */ - - AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT_PULLUP, MUX_MODE7) /* mcasp0_aclkr.gpio3[18], INPUT_PULLDOWN | MODE7 */ - >; - }; - - mmc1_pins: pinmux_mmc1_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT, MUX_MODE7) /* MMC1 CD */ - >; - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; - dtr-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>; - dsr-gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; - dcd-gpios = <&gpio2 24 GPIO_ACTIVE_LOW>; - rng-gpios = <&gpio2 25 GPIO_ACTIVE_LOW>; - - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; - dtr-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; - dsr-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; - dcd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; - rng-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; - - status = "okay"; -}; - -&i2c1 { - tca6416: gpio@20 { - compatible = "ti,tca6416"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&gpio0>; - interrupts = <20 IRQ_TYPE_EDGE_RISING>; - pinctrl-names = "default"; - pinctrl-0 = <&tca6416_pins>; - }; -}; - -&usb0_phy { - status = "okay"; -}; - -&usb1_phy { - status = "okay"; -}; - -&usb0 { - status = "okay"; - dr_mode = "host"; -}; - -&usb1 { - status = "okay"; - dr_mode = "host"; -}; - -&cpsw_emac0 { - phy-mode = "rmii"; - dual_emac_res_vlan = <1>; - fixed-link { - speed = <100>; - full-duplex; - }; -}; - -&cpsw_emac1 { - phy-mode = "rgmii-id"; - dual_emac_res_vlan = <2>; - phy-handle = <&phy1>; -}; - -&dcan1 { - pinctrl-names = "default"; - pinctrl-0 = <&dcan1_pins>; - - status = "okay"; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - cd-gpios = <&gpio2 18 GPIO_ACTIVE_LOW>; -}; diff --git a/sys/gnu/dts/arm/am335x-baltos-leds.dtsi b/sys/gnu/dts/arm/am335x-baltos-leds.dtsi deleted file mode 100644 index 4e11a160d88..00000000000 --- a/sys/gnu/dts/arm/am335x-baltos-leds.dtsi +++ /dev/null @@ -1,47 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ - */ - -/* - * VScom OnRISC - * http://www.vscom.de - */ - -/*#include "am33xx.dtsi"*/ - -/ { - leds { - pinctrl-names = "default"; - pinctrl-0 = <&user_leds>; - - compatible = "gpio-leds"; - - power { - label = "onrisc:red:power"; - linux,default-trigger = "default-on"; - gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; - default-state = "on"; - }; - wlan { - label = "onrisc:blue:wlan"; - gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - app { - label = "onrisc:green:app"; - gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; -}; - -&am33xx_pinmux { - user_leds: pinmux_user_leds { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* mii1_col.gpio3_0 PWR LED */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* mii1_txd3.gpio0_16 WLAN LED */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* mii1_txd2.gpio0_17 APP LED */ - >; - }; -}; diff --git a/sys/gnu/dts/arm/am335x-baltos.dtsi b/sys/gnu/dts/arm/am335x-baltos.dtsi deleted file mode 100644 index ed235f263e2..00000000000 --- a/sys/gnu/dts/arm/am335x-baltos.dtsi +++ /dev/null @@ -1,414 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ - */ - -/* - * VScom OnRISC - * http://www.vscom.de - */ - -#include "am33xx.dtsi" -#include -#include - -/ { - compatible = "vscom,onrisc", "ti,am33xx"; - - cpus { - cpu@0 { - cpu0-supply = <&vdd1_reg>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x10000000>; /* 256 MB */ - }; - - vbat: fixedregulator0 { - compatible = "regulator-fixed"; - regulator-name = "vbat"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - }; - - wl12xx_vmmc: fixedregulator2 { - pinctrl-names = "default"; - pinctrl-0 = <&wl12xx_gpio>; - compatible = "regulator-fixed"; - regulator-name = "vwl1271"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio3 8 0>; - startup-delay-us = <70000>; - enable-active-high; - }; -}; - -&am33xx_pinmux { - mmc2_pins: pinmux_mmc2_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_ad8.mmc1_dat0_mux0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_ad9.mmc1_dat1_mux0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_ad10.mmc1_dat2_mux0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_ad11.mmc1_dat3_mux0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk_mux0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd_mux0 */ - AM33XX_PADCONF(AM335X_PIN_EMU0, PIN_INPUT_PULLUP, MUX_MODE7) /* emu0.gpio3[7] */ - >; - }; - - wl12xx_gpio: pinmux_wl12xx_gpio { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_EMU1, PIN_OUTPUT_PULLUP, MUX_MODE7) /* emu1.gpio3[8] */ - >; - }; - - tps65910_pins: pinmux_tps65910_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_ben1.gpio1[28] */ - >; - }; - - i2c1_pins: pinmux_i2c1_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT, MUX_MODE2) /* spi0_d1.i2c1_sda_mux3 */ - AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT, MUX_MODE2) /* spi0_cs0.i2c1_scl_mux3 */ - >; - }; - - uart0_pins: pinmux_uart0_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - >; - }; - - cpsw_default: cpsw_default { - pinctrl-single,pins = < - /* Slave 1 */ - AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE1) /* mii1_crs.rmii1_crs_dv */ - AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_tx_en.rmii1_txen */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_txd1.rmii1_txd1 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_txd0.rmii1_txd0 */ - AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */ - AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */ - AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0) /* rmii1_ref_clk.rmii1_refclk */ - - - /* Slave 2 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a0.rgmii2_tctl */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a1.rgmii2_rctl */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a2.rgmii2_td3 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a3.rgmii2_td2 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a4.rgmii2_td1 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a5.rgmii2_td0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a6.rgmii2_tclk */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a7.rgmii2_rclk */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */ - >; - }; - - cpsw_sleep: cpsw_sleep { - pinctrl-single,pins = < - /* Slave 1 reset value */ - AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) - - /* Slave 2 reset value*/ - AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7) - >; - }; - - davinci_mdio_default: davinci_mdio_default { - pinctrl-single,pins = < - /* MDIO */ - AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) /* mdio_data.mdio_data */ - AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) /* mdio_clk.mdio_clk */ - >; - }; - - davinci_mdio_sleep: davinci_mdio_sleep { - pinctrl-single,pins = < - /* MDIO reset value */ - AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) - >; - }; - - nandflash_pins_s0: nandflash_pins_s0 { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_wpn.gpio0_30 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ - AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ - AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE0) /* gpmc_wen.gpmc_wen */ - AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ - >; - }; -}; - -&elm { - status = "okay"; -}; - -&gpmc { - pinctrl-names = "default"; - pinctrl-0 = <&nandflash_pins_s0>; - ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */ - status = "okay"; - - nand@0,0 { - compatible = "ti,omap2-nand"; - reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ - <1 IRQ_TYPE_NONE>; /* termcount */ - rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ - nand-bus-width = <8>; - ti,nand-ecc-opt = "bch8"; - ti,nand-xfer-type = "polled"; - - gpmc,device-nand = "true"; - gpmc,device-width = <1>; - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <44>; - gpmc,cs-wr-off-ns = <44>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <34>; - gpmc,adv-wr-off-ns = <44>; - gpmc,we-on-ns = <0>; - gpmc,we-off-ns = <40>; - gpmc,oe-on-ns = <0>; - gpmc,oe-off-ns = <54>; - gpmc,access-ns = <64>; - gpmc,rd-cycle-ns = <82>; - gpmc,wr-cycle-ns = <82>; - gpmc,bus-turnaround-ns = <0>; - gpmc,cycle2cycle-delay-ns = <0>; - gpmc,clk-activation-ns = <0>; - gpmc,wr-access-ns = <40>; - gpmc,wr-data-mux-bus-ns = <0>; - - #address-cells = <1>; - #size-cells = <1>; - ti,elm-id = <&elm>; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - - status = "okay"; - clock-frequency = <400000>; - - tps: tps@2d { - reg = <0x2d>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&gpio1>; - interrupts = <28 IRQ_TYPE_EDGE_RISING>; - pinctrl-names = "default"; - pinctrl-0 = <&tps65910_pins>; - }; - - at24@50 { - compatible = "atmel,24c02"; - pagesize = <8>; - reg = <0x50>; - }; -}; - -&usb { - status = "okay"; -}; - -&usb_ctrl_mod { - status = "okay"; -}; - -&cppi41dma { - status = "okay"; -}; - -#include "tps65910.dtsi" - -&tps { - vcc1-supply = <&vbat>; - vcc2-supply = <&vbat>; - vcc3-supply = <&vbat>; - vcc4-supply = <&vbat>; - vcc5-supply = <&vbat>; - vcc6-supply = <&vbat>; - vcc7-supply = <&vbat>; - vccio-supply = <&vbat>; - - ti,en-ck32k-xtal = <1>; - - regulators { - vrtc_reg: regulator@0 { - regulator-always-on; - }; - - vio_reg: regulator@1 { - regulator-always-on; - }; - - vdd1_reg: regulator@2 { - /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ - regulator-name = "vdd_mpu"; - regulator-min-microvolt = <912500>; - regulator-max-microvolt = <1312500>; - regulator-boot-on; - regulator-always-on; - }; - - vdd2_reg: regulator@3 { - /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ - regulator-name = "vdd_core"; - regulator-min-microvolt = <912500>; - regulator-max-microvolt = <1150000>; - regulator-boot-on; - regulator-always-on; - }; - - vdd3_reg: regulator@4 { - regulator-always-on; - }; - - vdig1_reg: regulator@5 { - regulator-always-on; - }; - - vdig2_reg: regulator@6 { - regulator-always-on; - }; - - vpll_reg: regulator@7 { - regulator-always-on; - }; - - vdac_reg: regulator@8 { - regulator-always-on; - }; - - vaux1_reg: regulator@9 { - regulator-always-on; - }; - - vaux2_reg: regulator@10 { - regulator-always-on; - }; - - vaux33_reg: regulator@11 { - regulator-always-on; - }; - - vmmc_reg: regulator@12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; -}; - -&mac { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&cpsw_default>; - pinctrl-1 = <&cpsw_sleep>; - dual_emac = <1>; - - status = "okay"; -}; - -&davinci_mdio { - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&davinci_mdio_default>; - pinctrl-1 = <&davinci_mdio_sleep>; - - phy1: ethernet-phy@1 { - reg = <7>; - eee-broken-100tx; - eee-broken-1000t; - }; -}; - -&mmc1 { - vmmc-supply = <&vmmc_reg>; - status = "okay"; -}; - -&mmc2 { - status = "okay"; - vmmc-supply = <&wl12xx_vmmc>; - ti,non-removable; - bus-width = <4>; - cap-power-off-card; - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; - - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@2 { - compatible = "ti,wl1835"; - reg = <2>; - interrupt-parent = <&gpio3>; - interrupts = <7 IRQ_TYPE_EDGE_RISING>; - }; -}; - -&sham { - status = "okay"; -}; - -&aes { - status = "okay"; -}; - -&gpio0 { - ti,no-reset-on-init; -}; - -&gpio3 { - ti,no-reset-on-init; -}; diff --git a/sys/gnu/dts/arm/am335x-base0033.dts b/sys/gnu/dts/arm/am335x-base0033.dts deleted file mode 100644 index 89c00ce42c2..00000000000 --- a/sys/gnu/dts/arm/am335x-base0033.dts +++ /dev/null @@ -1,92 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * am335x-base0033.dts - Device Tree file for IGEP AQUILA EXPANSION - * - * Copyright (C) 2013 ISEE 2007 SL - http://www.isee.biz - */ - -#include "am335x-igep0033.dtsi" - -/ { - model = "IGEP COM AM335x on AQUILA Expansion"; - compatible = "isee,am335x-base0033", "isee,am335x-igep0033", "ti,am33xx"; - - hdmi { - compatible = "ti,tilcdc,slave"; - i2c = <&i2c0>; - pinctrl-names = "default", "off"; - pinctrl-0 = <&nxp_hdmi_pins>; - pinctrl-1 = <&nxp_hdmi_off_pins>; - status = "okay"; - }; - - leds_base { - pinctrl-names = "default"; - pinctrl-0 = <&leds_base_pins>; - - compatible = "gpio-leds"; - - led0 { - label = "base:red:user"; - gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; /* gpio1_21 */ - default-state = "off"; - }; - - led1 { - label = "base:green:user"; - gpios = <&gpio2 0 GPIO_ACTIVE_HIGH>; /* gpio2_0 */ - default-state = "off"; - }; - }; -}; - -&am33xx_pinmux { - nxp_hdmi_pins: pinmux_nxp_hdmi_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT, MUX_MODE3) /* xdma_event_intr0.clkout1 */ - AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0) - >; - }; - nxp_hdmi_off_pins: pinmux_nxp_hdmi_off_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT, MUX_MODE3) /* xdma_event_intr0.clkout1 */ - >; - }; - - leds_base_pins: pinmux_leds_base_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a5.gpio1_21 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_csn3.gpio2_0 */ - >; - }; -}; - -&lcdc { - status = "okay"; -}; - -&i2c0 { - eeprom: eeprom@50 { - compatible = "atmel,24c256"; - reg = <0x50>; - }; -}; diff --git a/sys/gnu/dts/arm/am335x-bone-common.dtsi b/sys/gnu/dts/arm/am335x-bone-common.dtsi deleted file mode 100644 index 89b4cf2cb7f..00000000000 --- a/sys/gnu/dts/arm/am335x-bone-common.dtsi +++ /dev/null @@ -1,421 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ - */ - -/ { - cpus { - cpu@0 { - cpu0-supply = <&dcdc2_reg>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x10000000>; /* 256 MB */ - }; - - chosen { - stdout-path = &uart0; - }; - - leds { - pinctrl-names = "default"; - pinctrl-0 = <&user_leds_s0>; - - compatible = "gpio-leds"; - - led2 { - label = "beaglebone:green:heartbeat"; - gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - - led3 { - label = "beaglebone:green:mmc0"; - gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc0"; - default-state = "off"; - }; - - led4 { - label = "beaglebone:green:usr2"; - gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "cpu0"; - default-state = "off"; - }; - - led5 { - label = "beaglebone:green:usr3"; - gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc1"; - default-state = "off"; - }; - }; - - vmmcsd_fixed: fixedregulator0 { - compatible = "regulator-fixed"; - regulator-name = "vmmcsd_fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&am33xx_pinmux { - pinctrl-names = "default"; - pinctrl-0 = <&clkout2_pin>; - - user_leds_s0: user_leds_s0 { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a5.gpio1_21 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_a6.gpio1_22 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a7.gpio1_23 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_a8.gpio1_24 */ - >; - }; - - i2c0_pins: pinmux_i2c0_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) /* i2c0_sda.i2c0_sda */ - AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) /* i2c0_scl.i2c0_scl */ - >; - }; - - i2c2_pins: pinmux_i2c2_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart1_ctsn.i2c2_sda */ - AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart1_rtsn.i2c2_scl */ - >; - }; - - uart0_pins: pinmux_uart0_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - >; - }; - - clkout2_pin: pinmux_clkout2_pin { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* xdma_event_intr1.clkout2 */ - >; - }; - - cpsw_default: cpsw_default { - pinctrl-single,pins = < - /* Slave 1 */ - AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE0) - >; - }; - - cpsw_sleep: cpsw_sleep { - pinctrl-single,pins = < - /* Slave 1 reset value */ - AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) - >; - }; - - davinci_mdio_default: davinci_mdio_default { - pinctrl-single,pins = < - /* MDIO */ - AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) - >; - }; - - davinci_mdio_sleep: davinci_mdio_sleep { - pinctrl-single,pins = < - /* MDIO reset value */ - AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) - >; - }; - - mmc1_pins: pinmux_mmc1_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7) /* spio0_cs1.gpio0_6 */ - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) - >; - }; - - emmc_pins: pinmux_emmc_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */ - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ - >; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - - status = "okay"; -}; - -&usb { - status = "okay"; -}; - -&usb_ctrl_mod { - status = "okay"; -}; - -&usb0_phy { - status = "okay"; -}; - -&usb1_phy { - status = "okay"; -}; - -&usb0 { - status = "okay"; - dr_mode = "peripheral"; - interrupts-extended = <&intc 18 &tps 0>; - interrupt-names = "mc", "vbus"; -}; - -&usb1 { - status = "okay"; - dr_mode = "host"; -}; - -&cppi41dma { - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - - status = "okay"; - clock-frequency = <400000>; - - tps: tps@24 { - reg = <0x24>; - }; - - baseboard_eeprom: baseboard_eeprom@50 { - compatible = "atmel,24c256"; - reg = <0x50>; - - #address-cells = <1>; - #size-cells = <1>; - baseboard_data: baseboard_data@0 { - reg = <0 0x100>; - }; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - - status = "okay"; - clock-frequency = <100000>; - - cape_eeprom0: cape_eeprom0@54 { - compatible = "atmel,24c256"; - reg = <0x54>; - #address-cells = <1>; - #size-cells = <1>; - cape0_data: cape_data@0 { - reg = <0 0x100>; - }; - }; - - cape_eeprom1: cape_eeprom1@55 { - compatible = "atmel,24c256"; - reg = <0x55>; - #address-cells = <1>; - #size-cells = <1>; - cape1_data: cape_data@0 { - reg = <0 0x100>; - }; - }; - - cape_eeprom2: cape_eeprom2@56 { - compatible = "atmel,24c256"; - reg = <0x56>; - #address-cells = <1>; - #size-cells = <1>; - cape2_data: cape_data@0 { - reg = <0 0x100>; - }; - }; - - cape_eeprom3: cape_eeprom3@57 { - compatible = "atmel,24c256"; - reg = <0x57>; - #address-cells = <1>; - #size-cells = <1>; - cape3_data: cape_data@0 { - reg = <0 0x100>; - }; - }; -}; - - -/include/ "tps65217.dtsi" - -&tps { - /* - * Configure pmic to enter OFF-state instead of SLEEP-state ("RTC-only - * mode") at poweroff. Most BeagleBone versions do not support RTC-only - * mode and risk hardware damage if this mode is entered. - * - * For details, see linux-omap mailing list May 2015 thread - * [PATCH] ARM: dts: am335x-bone* enable pmic-shutdown-controller - * In particular, messages: - * http://www.spinics.net/lists/linux-omap/msg118585.html - * http://www.spinics.net/lists/linux-omap/msg118615.html - * - * You can override this later with - * &tps { /delete-property/ ti,pmic-shutdown-controller; } - * if you want to use RTC-only mode and made sure you are not affected - * by the hardware problems. (Tip: double-check by performing a current - * measurement after shutdown: it should be less than 1 mA.) - */ - - interrupts = <7>; /* NMI */ - interrupt-parent = <&intc>; - - ti,pmic-shutdown-controller; - - charger { - status = "okay"; - }; - - pwrbutton { - status = "okay"; - }; - - regulators { - dcdc1_reg: regulator@0 { - regulator-name = "vdds_dpr"; - regulator-always-on; - }; - - dcdc2_reg: regulator@1 { - /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ - regulator-name = "vdd_mpu"; - regulator-min-microvolt = <925000>; - regulator-max-microvolt = <1351500>; - regulator-boot-on; - regulator-always-on; - }; - - dcdc3_reg: regulator@2 { - /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ - regulator-name = "vdd_core"; - regulator-min-microvolt = <925000>; - regulator-max-microvolt = <1150000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1_reg: regulator@3 { - regulator-name = "vio,vrtc,vdds"; - regulator-always-on; - }; - - ldo2_reg: regulator@4 { - regulator-name = "vdd_3v3aux"; - regulator-always-on; - }; - - ldo3_reg: regulator@5 { - regulator-name = "vdd_1v8"; - regulator-always-on; - }; - - ldo4_reg: regulator@6 { - regulator-name = "vdd_3v3a"; - regulator-always-on; - }; - }; -}; - -&cpsw_emac0 { - phy-handle = <ðphy0>; - phy-mode = "mii"; -}; - -&mac { - slaves = <1>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&cpsw_default>; - pinctrl-1 = <&cpsw_sleep>; - status = "okay"; -}; - -&davinci_mdio { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&davinci_mdio_default>; - pinctrl-1 = <&davinci_mdio_sleep>; - status = "okay"; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -&mmc1 { - status = "okay"; - bus-width = <0x4>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; -}; - -&aes { - status = "okay"; -}; - -&sham { - status = "okay"; -}; - -&rtc { - clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; - clock-names = "ext-clk", "int-clk"; -}; diff --git a/sys/gnu/dts/arm/am335x-bone.dts b/sys/gnu/dts/arm/am335x-bone.dts deleted file mode 100644 index 43bfbce4104..00000000000 --- a/sys/gnu/dts/arm/am335x-bone.dts +++ /dev/null @@ -1,23 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ - */ -/dts-v1/; - -#include "am33xx.dtsi" -#include "am335x-bone-common.dtsi" - -/ { - model = "TI AM335x BeagleBone"; - compatible = "ti,am335x-bone", "ti,am33xx"; -}; - -&ldo3_reg { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; -}; - -&mmc1 { - vmmc-supply = <&ldo3_reg>; -}; diff --git a/sys/gnu/dts/arm/am335x-boneblack-common.dtsi b/sys/gnu/dts/arm/am335x-boneblack-common.dtsi deleted file mode 100644 index 7ad079861ef..00000000000 --- a/sys/gnu/dts/arm/am335x-boneblack-common.dtsi +++ /dev/null @@ -1,163 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ - */ - -#include -#include - -&ldo3_reg { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; -}; - -&mmc1 { - vmmc-supply = <&vmmcsd_fixed>; -}; - -&mmc2 { - vmmc-supply = <&vmmcsd_fixed>; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_pins>; - bus-width = <8>; - status = "okay"; -}; - -&am33xx_pinmux { - nxp_hdmi_bonelt_pins: nxp_hdmi_bonelt_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT_PULLDOWN, MUX_MODE3) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - >; - }; - - nxp_hdmi_bonelt_off_pins: nxp_hdmi_bonelt_off_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT_PULLDOWN, MUX_MODE3) - >; - }; - - mcasp0_pins: mcasp0_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLUP, MUX_MODE0) /* mcasp0_ahcklx.mcasp0_ahclkx */ - AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mcasp0_ahclkr.mcasp0_axr2*/ - AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_OUTPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a11.GPIO1_27 */ - >; - }; -}; - -&lcdc { - status = "okay"; - - /* If you want to get 24 bit RGB and 16 BGR mode instead of - * current 16 bit RGB and 24 BGR modes, set the propety - * below to "crossed" and uncomment the video-ports -property - * in tda19988 node. - */ - blue-and-red-wiring = "straight"; - - port { - lcdc_0: endpoint@0 { - remote-endpoint = <&hdmi_0>; - }; - }; -}; - -&i2c0 { - tda19988: tda19988@70 { - compatible = "nxp,tda998x"; - reg = <0x70>; - nxp,calib-gpios = <&gpio1 25 0>; - interrupts-extended = <&gpio1 25 IRQ_TYPE_LEVEL_LOW>; - - pinctrl-names = "default", "off"; - pinctrl-0 = <&nxp_hdmi_bonelt_pins>; - pinctrl-1 = <&nxp_hdmi_bonelt_off_pins>; - - /* Convert 24bit BGR to RGB, e.g. cross red and blue wiring */ - /* video-ports = <0x234501>; */ - - #sound-dai-cells = <0>; - audio-ports = < TDA998x_I2S 0x03>; - - ports { - port@0 { - hdmi_0: endpoint@0 { - remote-endpoint = <&lcdc_0>; - }; - }; - }; - }; -}; - -&rtc { - system-power-controller; -}; - -&mcasp0 { - #sound-dai-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&mcasp0_pins>; - status = "okay"; - op-mode = <0>; /* MCASP_IIS_MODE */ - tdm-slots = <2>; - serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ - 0 0 1 0 - >; - tx-num-evt = <32>; - rx-num-evt = <32>; -}; - -/ { - clk_mcasp0_fixed: clk_mcasp0_fixed { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24576000>; - }; - - clk_mcasp0: clk_mcasp0 { - #clock-cells = <0>; - compatible = "gpio-gate-clock"; - clocks = <&clk_mcasp0_fixed>; - enable-gpios = <&gpio1 27 0>; /* BeagleBone Black Clk enable on GPIO1_27 */ - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "TI BeagleBone Black"; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&dailink0_master>; - simple-audio-card,frame-master = <&dailink0_master>; - - dailink0_master: simple-audio-card,cpu { - sound-dai = <&mcasp0>; - clocks = <&clk_mcasp0>; - }; - - simple-audio-card,codec { - sound-dai = <&tda19988>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/am335x-boneblack-wireless.dts b/sys/gnu/dts/arm/am335x-boneblack-wireless.dts deleted file mode 100644 index 3124d94c0b3..00000000000 --- a/sys/gnu/dts/arm/am335x-boneblack-wireless.dts +++ /dev/null @@ -1,111 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ - */ -/dts-v1/; - -#include "am33xx.dtsi" -#include "am335x-bone-common.dtsi" -#include "am335x-boneblack-common.dtsi" -#include - -/ { - model = "TI AM335x BeagleBone Black Wireless"; - compatible = "ti,am335x-bone-black-wireless", "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx"; - - wlan_en_reg: fixedregulator@2 { - compatible = "regulator-fixed"; - regulator-name = "wlan-en-regulator"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - startup-delay-us= <70000>; - - /* WL_EN */ - gpio = <&gpio3 9 0>; - enable-active-high; - }; -}; - -&am33xx_pinmux { - bt_pins: pinmux_bt_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gmii1_txd0.gpio0_28 - BT_EN */ - >; - }; - - mmc3_pins: pinmux_mmc3_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE6 ) /* (L15) gmii1_rxd1.mmc2_clk */ - AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLUP, MUX_MODE6 ) /* (J16) gmii1_txen.mmc2_cmd */ - AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLUP, MUX_MODE5 ) /* (J17) gmii1_rxdv.mmc2_dat0 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLUP, MUX_MODE5 ) /* (J18) gmii1_txd3.mmc2_dat1 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLUP, MUX_MODE5 ) /* (K15) gmii1_txd2.mmc2_dat2 */ - AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLUP, MUX_MODE5 ) /* (H16) gmii1_col.mmc2_dat3 */ - >; - }; - - uart3_pins: pinmux_uart3_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gmii1_rxd3.uart3_rxd */ - AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* gmii1_rxd2.uart3_txd */ - AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT, MUX_MODE3) /* mdio_data.uart3_ctsn */ - AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* mdio_clk.uart3_rtsn */ - >; - }; - - wl18xx_pins: pinmux_wl18xx_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gmii1_txclk.gpio3_9 WL_EN */ - AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_refclk.gpio0_29 WL_IRQ */ - AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gmii1_rxclk.gpio3_10 LS_BUF_EN */ - >; - }; -}; - -&mac { - status = "disabled"; -}; - -&mmc3 { - dmas = <&edma_xbar 12 0 1 - &edma_xbar 13 0 2>; - dma-names = "tx", "rx"; - status = "okay"; - vmmc-supply = <&wlan_en_reg>; - bus-width = <4>; - non-removable; - cap-power-off-card; - ti,needs-special-hs-handling; - keep-power-in-suspend; - pinctrl-names = "default"; - pinctrl-0 = <&mmc3_pins &wl18xx_pins>; - - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@2 { - compatible = "ti,wl1835"; - reg = <2>; - interrupt-parent = <&gpio0>; - interrupts = <29 IRQ_TYPE_EDGE_RISING>; - }; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins &bt_pins>; - status = "okay"; - - bluetooth { - compatible = "ti,wl1835-st"; - enable-gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; - }; -}; - -&gpio3 { - ls_buf_en { - gpio-hog; - gpios = <10 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "LS_BUF_EN"; - }; -}; diff --git a/sys/gnu/dts/arm/am335x-boneblack.dts b/sys/gnu/dts/arm/am335x-boneblack.dts deleted file mode 100644 index d3928662aed..00000000000 --- a/sys/gnu/dts/arm/am335x-boneblack.dts +++ /dev/null @@ -1,25 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ - */ -/dts-v1/; - -#include "am33xx.dtsi" -#include "am335x-bone-common.dtsi" -#include "am335x-boneblack-common.dtsi" - -/ { - model = "TI AM335x BeagleBone Black"; - compatible = "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx"; -}; - -&cpu0_opp_table { - /* - * All PG 2.0 silicon may not support 1GHz but some of the early - * BeagleBone Blacks have PG 2.0 silicon which is guaranteed - * to support 1GHz OPP so enable it for PG 2.0 on this board. - */ - oppnitro-1000000000 { - opp-supported-hw = <0x06 0x0100>; - }; -}; diff --git a/sys/gnu/dts/arm/am335x-boneblue.dts b/sys/gnu/dts/arm/am335x-boneblue.dts deleted file mode 100644 index 2f6652ef9a1..00000000000 --- a/sys/gnu/dts/arm/am335x-boneblue.dts +++ /dev/null @@ -1,444 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ - */ -/dts-v1/; - -#include "am33xx.dtsi" -#include "am335x-osd335x-common.dtsi" -#include - -/ { - model = "TI AM335x BeagleBone Blue"; - compatible = "ti,am335x-bone-blue", "ti,am33xx"; - - chosen { - stdout-path = &uart0; - }; - - leds { - pinctrl-names = "default"; - pinctrl-0 = <&user_leds_s0>; - - compatible = "gpio-leds"; - - usr_0_led { - label = "beaglebone:green:usr0"; - gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - - usr_1_led { - label = "beaglebone:green:usr1"; - gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc0"; - default-state = "off"; - }; - - usr_2_led { - label = "beaglebone:green:usr2"; - gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "cpu0"; - default-state = "off"; - }; - - usr_3_led { - label = "beaglebone:green:usr3"; - gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc1"; - default-state = "off"; - }; - - wifi_led { - label = "wifi"; - gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>; - default-state = "off"; - linux,default-trigger = "phy0assoc"; - }; - - red_led { - label = "red"; - gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - green_led { - label = "green"; - gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - batt_1_led { - label = "bat25"; - gpios = <&gpio0 27 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - batt_2_led { - label = "bat50"; - gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - batt_3_led { - label = "bat75"; - gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - batt_4_led { - label = "bat100"; - gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - - vmmcsd_fixed: fixedregulator0 { - compatible = "regulator-fixed"; - regulator-name = "vmmcsd_fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - wlan_en_reg: fixedregulator@2 { - compatible = "regulator-fixed"; - regulator-name = "wlan-en-regulator"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - startup-delay-us= <70000>; - - /* WL_EN */ - gpio = <&gpio3 9 0>; - enable-active-high; - }; -}; - -&am33xx_pinmux { - user_leds_s0: user_leds_s0 { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE7) /* (V15) gpmc_a5.gpio1[21] - USR_LED_0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT, MUX_MODE7) /* (U15) gpmc_a6.gpio1[22] - USR_LED_1 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_OUTPUT, MUX_MODE7) /* (T15) gpmc_a7.gpio1[23] - USR_LED_2 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_OUTPUT, MUX_MODE7) /* (V16) gpmc_a8.gpio1[24] - USR_LED_3 */ - AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT, MUX_MODE7) /* (A15) xdma_event_intr0.gpio0[19] - WIFI_LED */ - AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE7) /* (R7) gpmc_advn_ale.gpio2[2] - P8.7, LED_RED, GP1_PIN_5 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE7) /* (T7) gpmc_oen_ren.gpio2[3] - P8.8, LED_GREEN, GP1_PIN_6 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_OUTPUT, MUX_MODE7) /* (U12) gpmc_ad11.gpio0[27] - P8.17, BATT_LED_1 */ - AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE7) /* (T5) lcd_data15.gpio0[11] - P8.32, BATT_LED_2 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE7) /* (V6) gpmc_csn0.gpio1[29] - P8.26, BATT_LED_3 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE7) /* (T11) gpmc_ad10.gpio0[26] - P8.14, BATT_LED_4 */ - - >; - }; - - i2c2_pins: pinmux_i2c2_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* (D18) uart1_ctsn.I2C2_SDA */ - AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* (D17) uart1_rtsn.I2C2_SCL */ - >; - }; - - /* UT0 */ - uart0_pins: pinmux_uart0_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - >; - }; - - /* UT1 */ - uart1_pins: pinmux_uart1_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - >; - }; - - /* GPS */ - uart2_pins: pinmux_uart2_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE1) /* (A17) spi0_sclk.uart2_rxd */ - AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* (B17) spi0_d0.uart2_txd */ - >; - }; - - /* DSM2 */ - uart4_pins: pinmux_uart4_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE6) /* (T17) gpmc_wait0.uart4_rxd */ - >; - }; - - /* UT5 */ - uart5_pins: pinmux_uart5_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_INPUT_PULLUP, MUX_MODE4) /* (U2) lcd_data9.uart5_rxd */ - AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT_PULLDOWN, MUX_MODE4) /* (U1) lcd_data8.uart5_txd */ - >; - }; - - mmc1_pins: pinmux_mmc1_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7) /* (C15) spi0_cs1.gpio0[6] */ - >; - }; - - mmc2_pins: pinmux_mmc2_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* (U9) gpmc_csn1.mmc1_clk */ - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* (V9) gpmc_csn2.mmc1_cmd */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* (U7) gpmc_ad0.mmc1_dat0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* (V7) gpmc_ad1.mmc1_dat1 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* (R8) gpmc_ad2.mmc1_dat2 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* (T8) gpmc_ad3.mmc1_dat3 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1) /* (U8) gpmc_ad4.mmc1_dat4 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1) /* (V8) gpmc_ad5.mmc1_dat5 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1) /* (R9) gpmc_ad6.mmc1_dat6 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1) /* (T9) gpmc_ad7.mmc1_dat7 */ - >; - }; - - mmc3_pins: pinmux_mmc3_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE6) /* (L15) gmii1_rxd1.mmc2_clk */ - AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLUP, MUX_MODE6) /* (J16) gmii1_txen.mmc2_cmd */ - AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLUP, MUX_MODE5) /* (J17) gmii1_rxdv.mmc2_dat0 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLUP, MUX_MODE5) /* (J18) gmii1_txd3.mmc2_dat1 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLUP, MUX_MODE5) /* (K15) gmii1_txd2.mmc2_dat2 */ - AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLUP, MUX_MODE5) /* (H16) gmii1_col.mmc2_dat3 */ - >; - }; - - bt_pins: pinmux_bt_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLUP, MUX_MODE7) /* (K17) gmii1_txd0.gpio0[28] - BT_EN */ - >; - }; - - uart3_pins: pinmux_uart3_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE1) /* (L17) gmii1_rxd3.uart3_rxd */ - AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* (L16) gmii1_rxd2.uart3_txd */ - AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT, MUX_MODE3) /* (M17) mdio_data.uart3_ctsn */ - AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* (M18) mdio_clk.uart3_rtsn */ - >; - }; - - wl18xx_pins: pinmux_wl18xx_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* (K18) gmii1_txclk.gpio3[9] - WL_EN */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) /* (K16) gmii1_txd1.gpio0[21] - WL_IRQ */ - AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_OUTPUT_PULLUP, MUX_MODE7) /* (L18) gmii1_rxclk.gpio3[10] - LS_BUF_EN */ - >; - }; - - /* DCAN */ - dcan1_pins: pinmux_dcan1_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT, MUX_MODE2) /* (E17) uart0_rtsn.dcan1_rx */ - AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT, MUX_MODE2) /* (E18) uart0_ctsn.dcan1_tx */ - AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_OUTPUT, MUX_MODE7) /* (M16) gmii1_rxd0.gpio2[21] */ - >; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; - - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; - - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&uart4_pins>; - - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&uart5_pins>; - - status = "okay"; -}; - -&usb { - status = "okay"; -}; - -&usb_ctrl_mod { - status = "okay"; -}; - -&usb0_phy { - status = "okay"; -}; - -&usb1_phy { - status = "okay"; -}; - -&usb0 { - status = "okay"; - dr_mode = "peripheral"; - interrupts-extended = <&intc 18 &tps 0>; - interrupt-names = "mc", "vbus"; -}; - -&usb1 { - status = "okay"; - dr_mode = "host"; -}; - -&cppi41dma { - status = "okay"; -}; - -&i2c0 { - baseboard_eeprom: baseboard_eeprom@50 { - compatible = "atmel,24c256"; - reg = <0x50>; - - #address-cells = <1>; - #size-cells = <1>; - baseboard_data: baseboard_data@0 { - reg = <0 0x100>; - }; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - - status = "okay"; - clock-frequency = <400000>; - - mpu9250@68 { - compatible = "invensense,mpu9250"; - reg = <0x68>; - interrupt-parent = <&gpio3>; - interrupts = <21 IRQ_TYPE_EDGE_RISING>; - i2c-gate { - #address-cells = <1>; - #size-cells = <0>; - ax8975@c { - compatible = "ak,ak8975"; - reg = <0x0c>; - }; - }; - }; - - pressure@76 { - compatible = "bosch,bmp280"; - reg = <0x76>; - }; -}; - -/include/ "tps65217.dtsi" - -&tps { - /delete-property/ ti,pmic-shutdown-controller; - - charger { - interrupts = <0>, <1>; - interrupt-names = "USB", "AC"; - status = "okay"; - }; -}; - -&mmc1 { - status = "okay"; - vmmc-supply = <&vmmcsd_fixed>; - bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; -}; - -&mmc2 { - status = "okay"; - vmmc-supply = <&vmmcsd_fixed>; - bus-width = <8>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; -}; - -&mmc3 { - dmas = <&edma_xbar 12 0 1 - &edma_xbar 13 0 2>; - dma-names = "tx", "rx"; - status = "okay"; - vmmc-supply = <&wlan_en_reg>; - bus-width = <4>; - non-removable; - cap-power-off-card; - ti,needs-special-hs-handling; - keep-power-in-suspend; - pinctrl-names = "default"; - pinctrl-0 = <&mmc3_pins &wl18xx_pins>; - - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@2 { - compatible = "ti,wl1835"; - reg = <2>; - interrupt-parent = <&gpio0>; - interrupts = <21 IRQ_TYPE_EDGE_RISING>; - }; -}; - -&tscadc { - status = "okay"; - adc { - ti,adc-channels = <0 1 2 3 4 5 6 7>; - }; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins &bt_pins>; - status = "okay"; - - bluetooth { - compatible = "ti,wl1835-st"; - enable-gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; - }; -}; - -&rtc { - system-power-controller; - clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; - clock-names = "ext-clk", "int-clk"; -}; - -&dcan1 { - pinctrl-names = "default"; - pinctrl-0 = <&dcan1_pins>; - status = "okay"; -}; - -&gpio3 { - ls_buf_en { - gpio-hog; - gpios = <10 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "LS_BUF_EN"; - }; -}; diff --git a/sys/gnu/dts/arm/am335x-bonegreen-common.dtsi b/sys/gnu/dts/arm/am335x-bonegreen-common.dtsi deleted file mode 100644 index 7a8826633ce..00000000000 --- a/sys/gnu/dts/arm/am335x-bonegreen-common.dtsi +++ /dev/null @@ -1,41 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ - */ - -&ldo3_reg { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; -}; - -&mmc1 { - vmmc-supply = <&vmmcsd_fixed>; -}; - -&mmc2 { - vmmc-supply = <&vmmcsd_fixed>; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_pins>; - bus-width = <8>; - status = "okay"; -}; - -&am33xx_pinmux { - uart2_pins: uart2_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE1) /* spi0_sclk.uart2_rxd */ - AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT, MUX_MODE1) /* spi0_d0.uart2_txd */ - >; - }; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; - status = "okay"; -}; - -&rtc { - system-power-controller; -}; diff --git a/sys/gnu/dts/arm/am335x-bonegreen-wireless.dts b/sys/gnu/dts/arm/am335x-bonegreen-wireless.dts deleted file mode 100644 index 4092cd193b8..00000000000 --- a/sys/gnu/dts/arm/am335x-bonegreen-wireless.dts +++ /dev/null @@ -1,128 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ - */ -/dts-v1/; - -#include "am33xx.dtsi" -#include "am335x-bone-common.dtsi" -#include "am335x-bonegreen-common.dtsi" -#include - -/ { - model = "TI AM335x BeagleBone Green Wireless"; - compatible = "ti,am335x-bone-green-wireless", "ti,am335x-bone-green", "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx"; - - wlan_en_reg: fixedregulator@2 { - compatible = "regulator-fixed"; - regulator-name = "wlan-en-regulator"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - startup-delay-us= <70000>; - - /* WL_EN */ - gpio = <&gpio0 26 0>; - enable-active-high; - }; -}; - -&am33xx_pinmux { - bt_pins: pinmux_bt_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_ad12.gpio1_28 BT_EN */ - >; - }; - - mmc3_pins: pinmux_mmc3_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad12.mmc2_dat0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad13.mmc2_dat1 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad14.mmc2_dat2 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad15.mmc2_dat3 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_csn3.mmc2_cmd */ - AM33XX_PADCONF(AM335X_PIN_GPMC_CLK, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_clk.mmc2_clk */ - >; - }; - - uart3_pins: pinmux_uart3_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gmii1_rxd3.uart3_rxd */ - AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* gmii1_rxd2.uart3_txd */ - AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT, MUX_MODE3) /* mdio_data.uart3_ctsn */ - AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* mdio_clk.uart3_rtsn */ - >; - }; - - wl18xx_pins: pinmux_wl18xx_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad10.gpio0_26 WL_EN */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad11.gpio0_27 WL_IRQ */ - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_csn0.gpio1_29 LS_BUF_EN */ - >; - }; -}; - -&mac { - status = "disabled"; -}; - -&mmc3 { - dmas = <&edma_xbar 12 0 1 - &edma_xbar 13 0 2>; - dma-names = "tx", "rx"; - status = "okay"; - vmmc-supply = <&wlan_en_reg>; - bus-width = <4>; - non-removable; - cap-power-off-card; - ti,needs-special-hs-handling; - keep-power-in-suspend; - pinctrl-names = "default"; - pinctrl-0 = <&mmc3_pins &wl18xx_pins>; - - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@2 { - compatible = "ti,wl1835"; - reg = <2>; - interrupt-parent = <&gpio0>; - interrupts = <27 IRQ_TYPE_EDGE_RISING>; - }; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins &bt_pins>; - status = "okay"; - - bluetooth { - compatible = "ti,wl1835-st"; - enable-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; - }; -}; - -&gpio1 { - ls_buf_en { - gpio-hog; - gpios = <29 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "LS_BUF_EN"; - }; -}; - -/* BT_AUD_OUT from wl1835 has to be pulled low when WL_EN is activated.*/ -/* in case it isn't, wilink8 ends up in one of the test modes that */ -/* intruces various issues (elp wkaeup timeouts etc.) */ -/* On the BBGW this pin is routed through the level shifter (U21) that */ -/* introduces a pullup on the line and wilink8 ends up in a bad state. */ -/* use a gpio hog to force this pin low. An alternative may be adding */ -/* an external pulldown on U21 pin 4. */ - -&gpio3 { - bt_aud_in { - gpio-hog; - gpios = <16 GPIO_ACTIVE_HIGH>; - output-low; - line-name = "MCASP0_AHCLKR"; - }; -}; diff --git a/sys/gnu/dts/arm/am335x-bonegreen.dts b/sys/gnu/dts/arm/am335x-bonegreen.dts deleted file mode 100644 index c12bb071777..00000000000 --- a/sys/gnu/dts/arm/am335x-bonegreen.dts +++ /dev/null @@ -1,14 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ - */ -/dts-v1/; - -#include "am33xx.dtsi" -#include "am335x-bone-common.dtsi" -#include "am335x-bonegreen-common.dtsi" - -/ { - model = "TI AM335x BeagleBone Green"; - compatible = "ti,am335x-bone-green", "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx"; -}; diff --git a/sys/gnu/dts/arm/am335x-chiliboard.dts b/sys/gnu/dts/arm/am335x-chiliboard.dts deleted file mode 100644 index 8cd81dc0cc7..00000000000 --- a/sys/gnu/dts/arm/am335x-chiliboard.dts +++ /dev/null @@ -1,201 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2015 Jablotron s.r.o. -- http://www.jablotron.com/ - * Author: Rostislav Lisovy - */ -/dts-v1/; -#include "am335x-chilisom.dtsi" - -/ { - model = "AM335x Chiliboard"; - compatible = "grinn,am335x-chiliboard", "grinn,am335x-chilisom", - "ti,am33xx"; - - chosen { - stdout-path = &uart0; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_gpio_pins>; - - led0 { - label = "led0"; - gpios = <&gpio3 7 GPIO_ACTIVE_LOW>; - default-state = "keep"; - linux,default-trigger = "heartbeat"; - }; - - led1 { - label = "led1"; - gpios = <&gpio3 8 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - }; -}; - -&am33xx_pinmux { - uart0_pins: pinmux_uart0_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - >; - }; - - cpsw_default: cpsw_default { - pinctrl-single,pins = < - /* Slave 1 */ - AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE1) - AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE1) - AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE1) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE1) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE1) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE1) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE1) - AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0) - >; - }; - - cpsw_sleep: cpsw_sleep { - pinctrl-single,pins = < - /* Slave 1 reset value */ - AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) - >; - }; - - davinci_mdio_default: davinci_mdio_default { - pinctrl-single,pins = < - /* mdio_data.mdio_data */ - AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) - /* mdio_clk.mdio_clk */ - AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) - >; - }; - - davinci_mdio_sleep: davinci_mdio_sleep { - pinctrl-single,pins = < - /* MDIO reset value */ - AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) - >; - }; - - usb1_drvvbus: usb1_drvvbus { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_USB1_DRVVBUS, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - >; - }; - - sd_pins: pinmux_sd_card { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7) /* spi0_cs1.gpio0_6 */ - >; - }; - - led_gpio_pins: led_gpio_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_EMU0, PIN_OUTPUT, MUX_MODE7) /* emu0.gpio3_7 */ - AM33XX_PADCONF(AM335X_PIN_EMU1, PIN_OUTPUT, MUX_MODE7) /* emu1.gpio3_8 */ - >; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - - status = "okay"; -}; - -&ldo4_reg { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; -}; - -/* Ethernet */ -&mac { - slaves = <1>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&cpsw_default>; - pinctrl-1 = <&cpsw_sleep>; - status = "okay"; -}; - -&davinci_mdio { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&davinci_mdio_default>; - pinctrl-1 = <&davinci_mdio_sleep>; - status = "okay"; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -&cpsw_emac0 { - phy-handle = <ðphy0>; - phy-mode = "rmii"; -}; - -/* USB */ -&usb { - status = "okay"; -}; - -&usb_ctrl_mod { - status = "okay"; -}; - -&usb1_phy { - status = "okay"; -}; - -&usb1 { - pinctrl-names = "default"; - pinctrl-0 = <&usb1_drvvbus>; - - status = "okay"; - dr_mode = "host"; -}; - -&cppi41dma { - status = "okay"; -}; - -/* microSD */ -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&sd_pins>; - vmmc-supply = <&ldo4_reg>; - bus-width = <0x4>; - cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&tps { - interrupt-parent = <&intc>; - interrupts = <7>; /* NNMI */ - - charger { - status = "okay"; - }; - - pwrbutton { - status = "okay"; - }; -}; diff --git a/sys/gnu/dts/arm/am335x-chilisom.dtsi b/sys/gnu/dts/arm/am335x-chilisom.dtsi deleted file mode 100644 index b31e2f7a4ad..00000000000 --- a/sys/gnu/dts/arm/am335x-chilisom.dtsi +++ /dev/null @@ -1,175 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2015 Jablotron s.r.o. -- http://www.jablotron.com/ - * Author: Rostislav Lisovy - */ -#include "am33xx.dtsi" -#include - -/ { - model = "Grinn AM335x ChiliSOM"; - compatible = "grinn,am335x-chilisom", "ti,am33xx"; - - cpus { - cpu@0 { - cpu0-supply = <&dcdc2_reg>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000>; /* 512 MB */ - }; -}; - -&am33xx_pinmux { - pinctrl-names = "default"; - - i2c0_pins: pinmux_i2c0_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) - >; - }; - - nandflash_pins: nandflash_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLDOWN, MUX_MODE0) - - AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT_PULLUP, MUX_MODE0) - >; - }; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - - status = "okay"; - clock-frequency = <400000>; - - tps: tps@24 { - reg = <0x24>; - }; - -}; - -/include/ "tps65217.dtsi" - -&tps { - regulators { - dcdc1_reg: regulator@0 { - regulator-name = "vdds_dpr"; - regulator-always-on; - }; - - dcdc2_reg: regulator@1 { - /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ - regulator-name = "vdd_mpu"; - regulator-min-microvolt = <925000>; - regulator-max-microvolt = <1325000>; - regulator-boot-on; - regulator-always-on; - }; - - dcdc3_reg: regulator@2 { - /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ - regulator-name = "vdd_core"; - regulator-min-microvolt = <925000>; - regulator-max-microvolt = <1150000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1_reg: regulator@3 { - regulator-name = "vio,vrtc,vdds"; - regulator-boot-on; - regulator-always-on; - }; - - ldo2_reg: regulator@4 { - regulator-name = "vdd_3v3aux"; - regulator-boot-on; - regulator-always-on; - }; - - ldo3_reg: regulator@5 { - regulator-name = "vdd_1v8"; - regulator-boot-on; - regulator-always-on; - }; - - ldo4_reg: regulator@6 { - regulator-name = "vdd_3v3d"; - regulator-boot-on; - regulator-always-on; - }; - }; -}; - -&rtc { - system-power-controller; - - pinctrl-0 = <&ext_wakeup>; - pinctrl-names = "default"; - - ext_wakeup: ext-wakeup { - pins = "ext_wakeup0"; - input-enable; - }; -}; - -/* NAND Flash */ -&elm { - status = "okay"; -}; - -&gpmc { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&nandflash_pins>; - ranges = <0 0 0x08000000 0x01000000>; /* CS0 0 @addr 0x08000000, size 0x01000000 */ - nand@0,0 { - compatible = "ti,omap2-nand"; - reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ - <1 IRQ_TYPE_NONE>; /* termcount */ - rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ - ti,nand-ecc-opt = "bch8"; - ti,elm-id = <&elm>; - nand-bus-width = <8>; - gpmc,device-width = <1>; - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <44>; - gpmc,cs-wr-off-ns = <44>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <34>; - gpmc,adv-wr-off-ns = <44>; - gpmc,we-on-ns = <0>; - gpmc,we-off-ns = <40>; - gpmc,oe-on-ns = <0>; - gpmc,oe-off-ns = <54>; - gpmc,access-ns = <64>; - gpmc,rd-cycle-ns = <82>; - gpmc,wr-cycle-ns = <82>; - gpmc,bus-turnaround-ns = <0>; - gpmc,cycle2cycle-delay-ns = <0>; - gpmc,clk-activation-ns = <0>; - gpmc,wr-access-ns = <40>; - gpmc,wr-data-mux-bus-ns = <0>; - }; -}; diff --git a/sys/gnu/dts/arm/am335x-cm-t335.dts b/sys/gnu/dts/arm/am335x-cm-t335.dts deleted file mode 100644 index 1fe3b566ba3..00000000000 --- a/sys/gnu/dts/arm/am335x-cm-t335.dts +++ /dev/null @@ -1,533 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * am335x-cm-t335.dts - Device Tree file for Compulab CM-T335 - * - * Copyright (C) 2014 - 2015 CompuLab Ltd. - http://www.compulab.co.il/ - */ - -/dts-v1/; - -#include "am33xx.dtsi" -#include - -/ { - model = "CompuLab CM-T335"; - compatible = "compulab,cm-t335", "ti,am33xx"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x8000000>; /* 128 MB */ - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&gpio_led_pins>; - led0 { - label = "cm_t335:green"; - gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; /* gpio2_0 */ - linux,default-trigger = "heartbeat"; - }; - }; - - /* regulator for mmc */ - vmmc_fixed: fixedregulator0 { - compatible = "regulator-fixed"; - regulator-name = "vmmc_fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - /* Regulator for WiFi */ - vwlan_fixed: fixedregulator2 { - compatible = "regulator-fixed"; - regulator-name = "vwlan_fixed"; - gpio = <&gpio0 20 GPIO_ACTIVE_HIGH>; /* gpio0_20 */ - enable-active-high; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&ecap0 0 50000 0>; - brightness-levels = <0 51 53 56 62 75 101 152 255>; - default-brightness-level = <8>; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "cm-t335"; - - simple-audio-card,widgets = - "Microphone", "Mic Jack", - "Line", "Line In", - "Headphone", "Headphone Jack"; - - simple-audio-card,routing = - "Headphone Jack", "LHPOUT", - "Headphone Jack", "RHPOUT", - "LLINEIN", "Line In", - "RLINEIN", "Line In", - "MICIN", "Mic Jack"; - - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&sound_master>; - simple-audio-card,frame-master = <&sound_master>; - - simple-audio-card,cpu { - sound-dai = <&mcasp1>; - }; - - sound_master: simple-audio-card,codec { - sound-dai = <&tlv320aic23>; - system-clock-frequency = <12000000>; - }; - }; -}; - -&am33xx_pinmux { - pinctrl-names = "default"; - pinctrl-0 = <&bluetooth_pins>; - - i2c0_pins: pinmux_i2c0_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) - >; - }; - - i2c1_pins: pinmux_i2c1_pins { - pinctrl-single,pins = < - /* uart0_ctsn.i2c1_sda */ - AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT_PULLUP, MUX_MODE2) - /* uart0_rtsn.i2c1_scl */ - AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLUP, MUX_MODE2) - >; - }; - - gpio_led_pins: pinmux_gpio_led_pins { - pinctrl-single,pins = < - /* gpmc_csn3.gpio2_0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_OUTPUT, MUX_MODE7) - >; - }; - - nandflash_pins: pinmux_nandflash_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0) - /* gpmc_wpn.gpio0_30 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0) - >; - }; - - uart0_pins: pinmux_uart0_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - >; - }; - - uart1_pins: pinmux_uart1_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - >; - }; - - dcan0_pins: pinmux_dcan0_pins { - pinctrl-single,pins = < - /* uart1_ctsn.dcan0_tx */ - AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_OUTPUT, MUX_MODE2) - /* uart1_rtsn.dcan0_rx */ - AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT, MUX_MODE2) - >; - }; - - dcan1_pins: pinmux_dcan1_pins { - pinctrl-single,pins = < - /* uart1_rxd.dcan1_tx */ - AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_OUTPUT, MUX_MODE2) - /* uart1_txd.dcan1_rx */ - AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_INPUT, MUX_MODE2) - >; - }; - - ecap0_pins: pinmux_ecap0_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, 0x0, MUX_MODE0) - >; - }; - - cpsw_default: cpsw_default { - pinctrl-single,pins = < - /* Slave 1 */ - /* mii1_tx_en.rgmii1_tctl */ - AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2) - /* mii1_rxdv.rgmii1_rctl */ - AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE2) - /* mii1_txd3.rgmii1_td3 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) - /* mii1_txd2.rgmii1_td2 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) - /* mii1_txd1.rgmii1_td1 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE2) - /* mii1_txd0.rgmii1_td0 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) - /* mii1_txclk.rgmii1_tclk */ - AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE2) - /* mii1_rxclk.rgmii1_rclk */ - AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE2) - /* mii1_rxd3.rgmii1_rd3 */ - AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE2) - /* mii1_rxd2.rgmii1_rd2 */ - AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE2) - /* mii1_rxd1.rgmii1_rd1 */ - AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE2) - /* mii1_rxd0.rgmii1_rd0 */ - AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE2) - >; - }; - - cpsw_sleep: cpsw_sleep { - pinctrl-single,pins = < - /* Slave 1 reset value */ - AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) - >; - }; - - davinci_mdio_default: davinci_mdio_default { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) - >; - }; - - davinci_mdio_sleep: davinci_mdio_sleep { - pinctrl-single,pins = < - /* MDIO reset value */ - AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) - >; - }; - - mmc1_pins: pinmux_mmc1_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) - >; - }; - - spi0_pins: pinmux_spi0_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_OUTPUT, MUX_MODE0) - >; - }; - - /* wl1271 bluetooth */ - bluetooth_pins: pinmux_bluetooth_pins { - pinctrl-single,pins = < - /* XDMA_EVENT_INTR0.gpio0_19 - bluetooth enable */ - AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT_PULLUP, MUX_MODE7) - >; - }; - - /* TLV320AIC23B codec */ - mcasp1_pins: pinmux_mcasp1_pins { - pinctrl-single,pins = < - /* MII1_CRS.mcasp1_aclkx */ - AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE4) - /* MII1_RX_ER.mcasp1_fsx */ - AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE4) - /* MII1_COL.mcasp1_axr2 */ - AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE4) - /* RMII1_REF_CLK.mcasp1_axr3 */ - AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE4) - >; - }; - - /* wl1271 WiFi */ - wifi_pins: pinmux_wifi_pins { - pinctrl-single,pins = < - /* EMU1.gpio3_8 - WiFi IRQ */ - AM33XX_PADCONF(AM335X_PIN_EMU1, PIN_INPUT_PULLUP, MUX_MODE7) - /* XDMA_EVENT_INTR1.gpio0_20 - WiFi enable */ - AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT, MUX_MODE7) - >; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - - status = "okay"; -}; - -/* WLS1271 bluetooth */ -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; - -status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - - status = "okay"; - clock-frequency = <400000>; - /* CM-T335 board EEPROM */ - eeprom: 24c02@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; - /* Real Time Clock */ - ext_rtc: em3027@56 { - compatible = "emmicro,em3027"; - reg = <0x56>; - }; - /* Audio codec */ - tlv320aic23: codec@1a { - compatible = "ti,tlv320aic23"; - reg = <0x1a>; - #sound-dai-cells= <0>; - status = "okay"; - }; -}; - -&usb { - status = "okay"; -}; - -&usb_ctrl_mod { - status = "okay"; -}; - -&usb0_phy { - status = "okay"; -}; - -&usb0 { - status = "okay"; -}; - -&cppi41dma { - status = "okay"; -}; - -&epwmss0 { - status = "okay"; - - ecap0: ecap@100 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&ecap0_pins>; - }; -}; - -&gpmc { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&nandflash_pins>; - ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */ - nand@0,0 { - compatible = "ti,omap2-nand"; - reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ - <1 IRQ_TYPE_NONE>; /* termcount */ - rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ - ti,nand-ecc-opt = "bch8"; - ti,elm-id = <&elm>; - nand-bus-width = <8>; - gpmc,device-width = <1>; - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <44>; - gpmc,cs-wr-off-ns = <44>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <34>; - gpmc,adv-wr-off-ns = <44>; - gpmc,we-on-ns = <0>; - gpmc,we-off-ns = <40>; - gpmc,oe-on-ns = <0>; - gpmc,oe-off-ns = <54>; - gpmc,access-ns = <64>; - gpmc,rd-cycle-ns = <82>; - gpmc,wr-cycle-ns = <82>; - gpmc,bus-turnaround-ns = <0>; - gpmc,cycle2cycle-delay-ns = <0>; - gpmc,clk-activation-ns = <0>; - gpmc,wr-access-ns = <40>; - gpmc,wr-data-mux-bus-ns = <0>; - /* MTD partition table */ - #address-cells = <1>; - #size-cells = <1>; - partition@0 { - label = "spl"; - reg = <0x00000000 0x00200000>; - }; - partition@1 { - label = "uboot"; - reg = <0x00200000 0x00100000>; - }; - partition@2 { - label = "uboot environment"; - reg = <0x00300000 0x00100000>; - }; - partition@3 { - label = "dtb"; - reg = <0x00400000 0x00100000>; - }; - partition@4 { - label = "splash"; - reg = <0x00500000 0x00400000>; - }; - partition@5 { - label = "linux"; - reg = <0x00900000 0x00600000>; - }; - partition@6 { - label = "rootfs"; - reg = <0x00F00000 0>; - }; - }; -}; - -&elm { - status = "okay"; -}; - -&mac { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&cpsw_default>; - pinctrl-1 = <&cpsw_sleep>; - slaves = <1>; - status = "okay"; -}; - -&davinci_mdio { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&davinci_mdio_default>; - pinctrl-1 = <&davinci_mdio_sleep>; - status = "okay"; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -&cpsw_emac0 { - phy-handle = <ðphy0>; - phy-mode = "rgmii-txid"; -}; - -&mmc1 { - status = "okay"; - vmmc-supply = <&vmmc_fixed>; - bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; -}; - -&dcan0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&dcan0_pins>; -}; - -&dcan1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&dcan1_pins>; -}; - -/* Touschscreen and analog digital converter */ -&tscadc { - status = "okay"; - tsc { - ti,wires = <4>; - ti,x-plate-resistance = <200>; - ti,coordinate-readouts = <5>; - ti,wire-config = <0x01 0x10 0x23 0x32>; - ti,charge-delay = <0x400>; - }; - - adc { - ti,adc-channels = <4 5 6 7>; - }; -}; - -/* CPU audio */ -&mcasp1 { - pinctrl-names = "default"; - pinctrl-0 = <&mcasp1_pins>; - - op-mode = <0>; /* MCASP_IIS_MODE */ - tdm-slots = <2>; - /* 16 serializers */ - num-serializer = <16>; - serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ - 0 0 2 1 0 0 0 0 0 0 0 0 0 0 0 0 - >; - tx-num-evt = <1>; - rx-num-evt = <1>; - - #sound-dai-cells= <0>; - status = "okay"; -}; - -&spi0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins>; - ti,pindir-d0-out-d1-in = <1>; - /* WLS1271 WiFi */ - wlcore: wlcore@1 { - compatible = "ti,wl1271"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_pins>; - reg = <1>; - spi-max-frequency = <48000000>; - clock-xtal; - ref-clock-frequency = <38400000>; - interrupt-parent = <&gpio3>; - interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; - vwlan-supply = <&vwlan_fixed>; - }; -}; diff --git a/sys/gnu/dts/arm/am335x-evm.dts b/sys/gnu/dts/arm/am335x-evm.dts deleted file mode 100644 index a00145705c9..00000000000 --- a/sys/gnu/dts/arm/am335x-evm.dts +++ /dev/null @@ -1,817 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ - */ -/dts-v1/; - -#include "am33xx.dtsi" -#include - -/ { - model = "TI AM335x EVM"; - compatible = "ti,am335x-evm", "ti,am33xx"; - - cpus { - cpu@0 { - cpu0-supply = <&vdd1_reg>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x10000000>; /* 256 MB */ - }; - - chosen { - stdout-path = &uart0; - }; - - vbat: fixedregulator0 { - compatible = "regulator-fixed"; - regulator-name = "vbat"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - }; - - lis3_reg: fixedregulator1 { - compatible = "regulator-fixed"; - regulator-name = "lis3_reg"; - regulator-boot-on; - }; - - wlan_en_reg: fixedregulator2 { - compatible = "regulator-fixed"; - regulator-name = "wlan-en-regulator"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - /* WLAN_EN GPIO for this board - Bank1, pin16 */ - gpio = <&gpio1 16 0>; - - /* WLAN card specific delay */ - startup-delay-us = <70000>; - enable-active-high; - }; - - /* TPS79501 */ - v1_8d_reg: fixedregulator-v1_8d { - compatible = "regulator-fixed"; - regulator-name = "v1_8d"; - vin-supply = <&vbat>; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - /* TPS79501 */ - v3_3d_reg: fixedregulator-v3_3d { - compatible = "regulator-fixed"; - regulator-name = "v3_3d"; - vin-supply = <&vbat>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - matrix_keypad: matrix_keypad0 { - compatible = "gpio-matrix-keypad"; - debounce-delay-ms = <5>; - col-scan-delay-us = <2>; - - row-gpios = <&gpio1 25 GPIO_ACTIVE_HIGH /* Bank1, pin25 */ - &gpio1 26 GPIO_ACTIVE_HIGH /* Bank1, pin26 */ - &gpio1 27 GPIO_ACTIVE_HIGH>; /* Bank1, pin27 */ - - col-gpios = <&gpio1 21 GPIO_ACTIVE_HIGH /* Bank1, pin21 */ - &gpio1 22 GPIO_ACTIVE_HIGH>; /* Bank1, pin22 */ - - linux,keymap = <0x0000008b /* MENU */ - 0x0100009e /* BACK */ - 0x02000069 /* LEFT */ - 0x0001006a /* RIGHT */ - 0x0101001c /* ENTER */ - 0x0201006c>; /* DOWN */ - }; - - gpio_keys: volume_keys0 { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - autorepeat; - - switch9 { - label = "volume-up"; - linux,code = <115>; - gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; - wakeup-source; - }; - - switch10 { - label = "volume-down"; - linux,code = <114>; - gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; - wakeup-source; - }; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&ecap0 0 50000 0>; - brightness-levels = <0 51 53 56 62 75 101 152 255>; - default-brightness-level = <8>; - }; - - panel { - compatible = "ti,tilcdc,panel"; - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&lcd_pins_s0>; - panel-info { - ac-bias = <255>; - ac-bias-intrpt = <0>; - dma-burst-sz = <16>; - bpp = <32>; - fdd = <0x80>; - sync-edge = <0>; - sync-ctrl = <1>; - raster-order = <0>; - fifo-th = <0>; - }; - - display-timings { - 800x480p62 { - clock-frequency = <30000000>; - hactive = <800>; - vactive = <480>; - hfront-porch = <39>; - hback-porch = <39>; - hsync-len = <47>; - vback-porch = <29>; - vfront-porch = <13>; - vsync-len = <2>; - hsync-active = <1>; - vsync-active = <1>; - }; - }; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "AM335x-EVM"; - simple-audio-card,widgets = - "Headphone", "Headphone Jack", - "Line", "Line In"; - simple-audio-card,routing = - "Headphone Jack", "HPLOUT", - "Headphone Jack", "HPROUT", - "LINE1L", "Line In", - "LINE1R", "Line In"; - simple-audio-card,format = "dsp_b"; - simple-audio-card,bitclock-master = <&sound_master>; - simple-audio-card,frame-master = <&sound_master>; - simple-audio-card,bitclock-inversion; - - simple-audio-card,cpu { - sound-dai = <&mcasp1>; - }; - - sound_master: simple-audio-card,codec { - sound-dai = <&tlv320aic3106>; - system-clock-frequency = <12000000>; - }; - }; -}; - -&am33xx_pinmux { - pinctrl-names = "default"; - pinctrl-0 = <&matrix_keypad_s0 &volume_keys_s0 &clkout2_pin>; - - matrix_keypad_s0: matrix_keypad_s0 { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a5.gpio1_21 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a6.gpio1_22 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_a9.gpio1_25 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_a10.gpio1_26 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_a11.gpio1_27 */ - >; - }; - - volume_keys_s0: volume_keys_s0 { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLDOWN, MUX_MODE7) /* spi0_sclk.gpio0_2 */ - AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLDOWN, MUX_MODE7) /* spi0_d0.gpio0_3 */ - >; - }; - - i2c0_pins: pinmux_i2c0_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) /* i2c0_sda.i2c0_sda */ - AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) /* i2c0_scl.i2c0_scl */ - >; - }; - - i2c1_pins: pinmux_i2c1_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE2) /* spi0_d1.i2c1_sda */ - AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE2) /* spi0_cs0.i2c1_scl */ - >; - }; - - uart0_pins: pinmux_uart0_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - >; - }; - - uart1_pins: pinmux_uart1_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - >; - }; - - clkout2_pin: pinmux_clkout2_pin { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* xdma_event_intr1.clkout2 */ - >; - }; - - nandflash_pins_s0: nandflash_pins_s0 { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_wpn.gpio0_30 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0) - >; - }; - - ecap0_pins: backlight_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, 0x0, MUX_MODE0) - >; - }; - - cpsw_default: cpsw_default { - pinctrl-single,pins = < - /* Slave 1 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txen.rgmii1_tctl */ - AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd3.rgmii1_td3 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd2.rgmii1_td2 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txclk.rgmii1_tclk */ - AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */ - AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */ - AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */ - AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ - AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ - >; - }; - - cpsw_sleep: cpsw_sleep { - pinctrl-single,pins = < - /* Slave 1 reset value */ - AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) - >; - }; - - davinci_mdio_default: davinci_mdio_default { - pinctrl-single,pins = < - /* MDIO */ - AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) - >; - }; - - davinci_mdio_sleep: davinci_mdio_sleep { - pinctrl-single,pins = < - /* MDIO reset value */ - AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) - >; - }; - - mmc1_pins: pinmux_mmc1_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7) /* spi0_cs1.gpio0_6 */ - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT, MUX_MODE4) /* mcasp0_aclkr.mmc0_sdwp */ - >; - }; - - mmc3_pins: pinmux_mmc3_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_a1.mmc2_dat0, INPUT_PULLUP | MODE3 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_a2.mmc2_dat1, INPUT_PULLUP | MODE3 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_a3.mmc2_dat2, INPUT_PULLUP | MODE3 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ben1.mmc2_dat3, INPUT_PULLUP | MODE3 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_csn3.mmc2_cmd, INPUT_PULLUP | MODE3 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_CLK, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_clk.mmc2_clk, INPUT_PULLUP | MODE3 */ - >; - }; - - wlan_pins: pinmux_wlan_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a0.gpio1_16 */ - AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_INPUT, MUX_MODE7) /* mcasp0_ahclkr.gpio3_17 */ - AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* mcasp0_ahclkx.gpio3_21 */ - >; - }; - - lcd_pins_s0: lcd_pins_s0 { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad8.lcd_data23 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad9.lcd_data22 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad10.lcd_data21 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad11.lcd_data20 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad12.lcd_data19 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad13.lcd_data18 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad14.lcd_data17 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad15.lcd_data16 */ - AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0) - >; - }; - - mcasp1_pins: mcasp1_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE4) /* mii1_crs.mcasp1_aclkx */ - AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */ - AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_OUTPUT_PULLDOWN, MUX_MODE4) /* mii1_col.mcasp1_axr2 */ - AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */ - >; - }; - - mcasp1_pins_sleep: mcasp1_pins_sleep { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) - >; - }; - - dcan1_pins_default: dcan1_pins_default { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT, MUX_MODE2) /* uart0_ctsn.d_can1_tx */ - AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLDOWN, MUX_MODE2) /* uart0_rtsn.d_can1_rx */ - >; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; - - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - - status = "okay"; - clock-frequency = <400000>; - - tps: tps@2d { - reg = <0x2d>; - }; -}; - -&usb { - status = "okay"; -}; - -&usb_ctrl_mod { - status = "okay"; -}; - -&usb0_phy { - status = "okay"; -}; - -&usb1_phy { - status = "okay"; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; - dr_mode = "host"; -}; - -&cppi41dma { - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - - status = "okay"; - clock-frequency = <100000>; - - lis331dlh: lis331dlh@18 { - compatible = "st,lis331dlh", "st,lis3lv02d"; - reg = <0x18>; - Vdd-supply = <&lis3_reg>; - Vdd_IO-supply = <&lis3_reg>; - - st,click-single-x; - st,click-single-y; - st,click-single-z; - st,click-thresh-x = <10>; - st,click-thresh-y = <10>; - st,click-thresh-z = <10>; - st,irq1-click; - st,irq2-click; - st,wakeup-x-lo; - st,wakeup-x-hi; - st,wakeup-y-lo; - st,wakeup-y-hi; - st,wakeup-z-lo; - st,wakeup-z-hi; - st,min-limit-x = <120>; - st,min-limit-y = <120>; - st,min-limit-z = <140>; - st,max-limit-x = <550>; - st,max-limit-y = <550>; - st,max-limit-z = <750>; - }; - - tsl2550: tsl2550@39 { - compatible = "taos,tsl2550"; - reg = <0x39>; - }; - - tmp275: tmp275@48 { - compatible = "ti,tmp275"; - reg = <0x48>; - }; - - tlv320aic3106: tlv320aic3106@1b { - #sound-dai-cells = <0>; - compatible = "ti,tlv320aic3106"; - reg = <0x1b>; - status = "okay"; - - /* Regulators */ - AVDD-supply = <&v3_3d_reg>; - IOVDD-supply = <&v3_3d_reg>; - DRVDD-supply = <&v3_3d_reg>; - DVDD-supply = <&v1_8d_reg>; - }; -}; - -&lcdc { - status = "okay"; - - blue-and-red-wiring = "crossed"; -}; - -&elm { - status = "okay"; -}; - -&epwmss0 { - status = "okay"; - - ecap0: ecap@100 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&ecap0_pins>; - }; -}; - -&gpmc { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&nandflash_pins_s0>; - ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */ - nand@0,0 { - compatible = "ti,omap2-nand"; - reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ - <1 IRQ_TYPE_NONE>; /* termcount */ - rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ - ti,nand-xfer-type = "prefetch-dma"; - ti,nand-ecc-opt = "bch8"; - ti,elm-id = <&elm>; - nand-bus-width = <8>; - gpmc,device-width = <1>; - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <44>; - gpmc,cs-wr-off-ns = <44>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <34>; - gpmc,adv-wr-off-ns = <44>; - gpmc,we-on-ns = <0>; - gpmc,we-off-ns = <40>; - gpmc,oe-on-ns = <0>; - gpmc,oe-off-ns = <54>; - gpmc,access-ns = <64>; - gpmc,rd-cycle-ns = <82>; - gpmc,wr-cycle-ns = <82>; - gpmc,bus-turnaround-ns = <0>; - gpmc,cycle2cycle-delay-ns = <0>; - gpmc,clk-activation-ns = <0>; - gpmc,wr-access-ns = <40>; - gpmc,wr-data-mux-bus-ns = <0>; - /* MTD partition table */ - /* All SPL-* partitions are sized to minimal length - * which can be independently programmable. For - * NAND flash this is equal to size of erase-block */ - #address-cells = <1>; - #size-cells = <1>; - partition@0 { - label = "NAND.SPL"; - reg = <0x00000000 0x000020000>; - }; - partition@1 { - label = "NAND.SPL.backup1"; - reg = <0x00020000 0x00020000>; - }; - partition@2 { - label = "NAND.SPL.backup2"; - reg = <0x00040000 0x00020000>; - }; - partition@3 { - label = "NAND.SPL.backup3"; - reg = <0x00060000 0x00020000>; - }; - partition@4 { - label = "NAND.u-boot-spl-os"; - reg = <0x00080000 0x00040000>; - }; - partition@5 { - label = "NAND.u-boot"; - reg = <0x000C0000 0x00100000>; - }; - partition@6 { - label = "NAND.u-boot-env"; - reg = <0x001C0000 0x00020000>; - }; - partition@7 { - label = "NAND.u-boot-env.backup1"; - reg = <0x001E0000 0x00020000>; - }; - partition@8 { - label = "NAND.kernel"; - reg = <0x00200000 0x00800000>; - }; - partition@9 { - label = "NAND.file-system"; - reg = <0x00A00000 0x0F600000>; - }; - }; -}; - -#include "tps65910.dtsi" - -&mcasp1 { - #sound-dai-cells = <0>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&mcasp1_pins>; - pinctrl-1 = <&mcasp1_pins_sleep>; - - status = "okay"; - - op-mode = <0>; /* MCASP_IIS_MODE */ - tdm-slots = <2>; - /* 4 serializers */ - serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ - 0 0 1 2 - >; - tx-num-evt = <32>; - rx-num-evt = <32>; -}; - -&tps { - vcc1-supply = <&vbat>; - vcc2-supply = <&vbat>; - vcc3-supply = <&vbat>; - vcc4-supply = <&vbat>; - vcc5-supply = <&vbat>; - vcc6-supply = <&vbat>; - vcc7-supply = <&vbat>; - vccio-supply = <&vbat>; - - regulators { - vrtc_reg: regulator@0 { - regulator-always-on; - }; - - vio_reg: regulator@1 { - regulator-always-on; - }; - - vdd1_reg: regulator@2 { - /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ - regulator-name = "vdd_mpu"; - regulator-min-microvolt = <912500>; - regulator-max-microvolt = <1351500>; - regulator-boot-on; - regulator-always-on; - }; - - vdd2_reg: regulator@3 { - /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ - regulator-name = "vdd_core"; - regulator-min-microvolt = <912500>; - regulator-max-microvolt = <1150000>; - regulator-boot-on; - regulator-always-on; - }; - - vdd3_reg: regulator@4 { - regulator-always-on; - }; - - vdig1_reg: regulator@5 { - regulator-always-on; - }; - - vdig2_reg: regulator@6 { - regulator-always-on; - }; - - vpll_reg: regulator@7 { - regulator-always-on; - }; - - vdac_reg: regulator@8 { - regulator-always-on; - }; - - vaux1_reg: regulator@9 { - regulator-always-on; - }; - - vaux2_reg: regulator@10 { - regulator-always-on; - }; - - vaux33_reg: regulator@11 { - regulator-always-on; - }; - - vmmc_reg: regulator@12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; -}; - -&mac { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&cpsw_default>; - pinctrl-1 = <&cpsw_sleep>; - status = "okay"; - slaves = <1>; -}; - -&davinci_mdio { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&davinci_mdio_default>; - pinctrl-1 = <&davinci_mdio_sleep>; - status = "okay"; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -&cpsw_emac0 { - phy-handle = <ðphy0>; - phy-mode = "rgmii-id"; -}; - -&tscadc { - status = "okay"; - tsc { - ti,wires = <4>; - ti,x-plate-resistance = <200>; - ti,coordinate-readouts = <5>; - ti,wire-config = <0x00 0x11 0x22 0x33>; - ti,charge-delay = <0x400>; - }; - - adc { - ti,adc-channels = <4 5 6 7>; - }; -}; - -&mmc1 { - status = "okay"; - vmmc-supply = <&vmmc_reg>; - bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; -}; - -&mmc3 { - /* these are on the crossbar and are outlined in the - xbar-event-map element */ - dmas = <&edma_xbar 12 0 1 - &edma_xbar 13 0 2>; - dma-names = "tx", "rx"; - status = "okay"; - vmmc-supply = <&wlan_en_reg>; - bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc3_pins &wlan_pins>; - ti,non-removable; - ti,needs-special-hs-handling; - cap-power-off-card; - keep-power-in-suspend; - - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@0 { - compatible = "ti,wl1835"; - reg = <2>; - interrupt-parent = <&gpio3>; - interrupts = <17 IRQ_TYPE_EDGE_RISING>; - }; -}; - -&sham { - status = "okay"; -}; - -&aes { - status = "okay"; -}; - -&dcan1 { - status = "disabled"; /* Enable only if Profile 1 is selected */ - pinctrl-names = "default"; - pinctrl-0 = <&dcan1_pins_default>; -}; - -&rtc { - clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; - clock-names = "ext-clk", "int-clk"; -}; diff --git a/sys/gnu/dts/arm/am335x-evmsk.dts b/sys/gnu/dts/arm/am335x-evmsk.dts deleted file mode 100644 index e28a5b82fdf..00000000000 --- a/sys/gnu/dts/arm/am335x-evmsk.dts +++ /dev/null @@ -1,758 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ - */ - -/* - * AM335x Starter Kit - * http://www.ti.com/tool/tmdssk3358 - */ - -/dts-v1/; - -#include "am33xx.dtsi" -#include -#include - -/ { - model = "TI AM335x EVM-SK"; - compatible = "ti,am335x-evmsk", "ti,am33xx"; - - cpus { - cpu@0 { - cpu0-supply = <&vdd1_reg>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x10000000>; /* 256 MB */ - }; - - chosen { - stdout-path = &uart0; - }; - - vbat: fixedregulator0 { - compatible = "regulator-fixed"; - regulator-name = "vbat"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - }; - - lis3_reg: fixedregulator1 { - compatible = "regulator-fixed"; - regulator-name = "lis3_reg"; - regulator-boot-on; - }; - - wl12xx_vmmc: fixedregulator2 { - pinctrl-names = "default"; - pinctrl-0 = <&wl12xx_gpio>; - compatible = "regulator-fixed"; - regulator-name = "vwl1271"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio1 29 0>; - startup-delay-us = <70000>; - enable-active-high; - }; - - vtt_fixed: fixedregulator3 { - compatible = "regulator-fixed"; - regulator-name = "vtt"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - gpio = <&gpio0 7 GPIO_ACTIVE_HIGH>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - }; - - /* TPS79518 */ - v1_8d_reg: fixedregulator-v1_8d { - compatible = "regulator-fixed"; - regulator-name = "v1_8d"; - vin-supply = <&vbat>; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - /* TPS78633 */ - v3_3d_reg: fixedregulator-v3_3d { - compatible = "regulator-fixed"; - regulator-name = "v3_3d"; - vin-supply = <&vbat>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - leds { - pinctrl-names = "default"; - pinctrl-0 = <&user_leds_s0>; - - compatible = "gpio-leds"; - - led1 { - label = "evmsk:green:usr0"; - gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led2 { - label = "evmsk:green:usr1"; - gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led3 { - label = "evmsk:green:mmc0"; - gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc0"; - default-state = "off"; - }; - - led4 { - label = "evmsk:green:heartbeat"; - gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - }; - - gpio_buttons: gpio_buttons0 { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - switch1 { - label = "button0"; - linux,code = <0x100>; - gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; - }; - - switch2 { - label = "button1"; - linux,code = <0x101>; - gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; - }; - - switch3 { - label = "button2"; - linux,code = <0x102>; - gpios = <&gpio0 30 GPIO_ACTIVE_HIGH>; - wakeup-source; - }; - - switch4 { - label = "button3"; - linux,code = <0x103>; - gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; - }; - }; - - lcd_bl: backlight { - compatible = "pwm-backlight"; - pwms = <&ecap2 0 50000 PWM_POLARITY_INVERTED>; - brightness-levels = <0 58 61 66 75 90 125 170 255>; - default-brightness-level = <8>; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "AM335x-EVMSK"; - simple-audio-card,widgets = - "Headphone", "Headphone Jack"; - simple-audio-card,routing = - "Headphone Jack", "HPLOUT", - "Headphone Jack", "HPROUT"; - simple-audio-card,format = "dsp_b"; - simple-audio-card,bitclock-master = <&sound_master>; - simple-audio-card,frame-master = <&sound_master>; - simple-audio-card,bitclock-inversion; - - simple-audio-card,cpu { - sound-dai = <&mcasp1>; - }; - - sound_master: simple-audio-card,codec { - sound-dai = <&tlv320aic3106>; - system-clock-frequency = <24000000>; - }; - }; - - panel { - compatible = "ti,tilcdc,panel"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&lcd_pins_default>; - pinctrl-1 = <&lcd_pins_sleep>; - backlight = <&lcd_bl>; - status = "okay"; - panel-info { - ac-bias = <255>; - ac-bias-intrpt = <0>; - dma-burst-sz = <16>; - bpp = <32>; - fdd = <0x80>; - sync-edge = <0>; - sync-ctrl = <1>; - raster-order = <0>; - fifo-th = <0>; - }; - display-timings { - 480x272 { - hactive = <480>; - vactive = <272>; - hback-porch = <43>; - hfront-porch = <8>; - hsync-len = <4>; - vback-porch = <12>; - vfront-porch = <4>; - vsync-len = <10>; - clock-frequency = <9000000>; - hsync-active = <0>; - vsync-active = <0>; - }; - }; - }; -}; - -&am33xx_pinmux { - pinctrl-names = "default"; - pinctrl-0 = <&gpio_keys_s0 &clkout2_pin>; - - lcd_pins_default: lcd_pins_default { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad8.lcd_data23 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad9.lcd_data22 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad10.lcd_data21 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad11.lcd_data20 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad12.lcd_data19 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad13.lcd_data18 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad14.lcd_data17 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad15.lcd_data16 */ - AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0) - >; - }; - - lcd_pins_sleep: lcd_pins_sleep { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad8.lcd_data23 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad9.lcd_data22 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad10.lcd_data21 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad11.lcd_data20 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad12.lcd_data19 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad13.lcd_data18 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad14.lcd_data17 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad15.lcd_data16 */ - AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PULL_DISABLE, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PULL_DISABLE, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PULL_DISABLE, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PULL_DISABLE, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PULL_DISABLE, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PULL_DISABLE, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PULL_DISABLE, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PULL_DISABLE, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PULL_DISABLE, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PULL_DISABLE, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PULL_DISABLE, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PULL_DISABLE, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PULL_DISABLE, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PULL_DISABLE, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PULL_DISABLE, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PULL_DISABLE, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) - >; - }; - - - user_leds_s0: user_leds_s0 { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad4.gpio1_4 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad5.gpio1_5 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad6.gpio1_6 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad7.gpio1_7 */ - >; - }; - - gpio_keys_s0: gpio_keys_s0 { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_oen_ren.gpio2_3 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_advn_ale.gpio2_2 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_wait0.gpio0_30 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ben0_cle.gpio2_5 */ - >; - }; - - i2c0_pins: pinmux_i2c0_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) - >; - }; - - uart0_pins: pinmux_uart0_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - >; - }; - - clkout2_pin: pinmux_clkout2_pin { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* xdma_event_intr1.clkout2 */ - >; - }; - - ecap2_pins: backlight_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, 0x0, MUX_MODE4) /* mcasp0_ahclkr.ecap2_in_pwm2_out */ - >; - }; - - cpsw_default: cpsw_default { - pinctrl-single,pins = < - /* Slave 1 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txen.rgmii1_tctl */ - AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd3.rgmii1_td3 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd2.rgmii1_td2 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txclk.rgmii1_tclk */ - AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */ - AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */ - AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */ - AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ - AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ - - /* Slave 2 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a0.rgmii2_tctl */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a1.rgmii2_rctl */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a2.rgmii2_td3 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a3.rgmii2_td2 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a4.rgmii2_td1 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a5.rgmii2_td0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a6.rgmii2_tclk */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a7.rgmii2_rclk */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */ - >; - }; - - cpsw_sleep: cpsw_sleep { - pinctrl-single,pins = < - /* Slave 1 reset value */ - AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) - - /* Slave 2 reset value*/ - AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7) - >; - }; - - davinci_mdio_default: davinci_mdio_default { - pinctrl-single,pins = < - /* MDIO */ - AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) - >; - }; - - davinci_mdio_sleep: davinci_mdio_sleep { - pinctrl-single,pins = < - /* MDIO reset value */ - AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) - >; - }; - - mmc1_pins: pinmux_mmc1_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7) /* spi0_cs1.gpio0_6 */ - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT, MUX_MODE4) /* mcasp0_aclkr.mmc0_sdwp */ - >; - }; - - mcasp1_pins: mcasp1_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE4) /* mii1_crs.mcasp1_aclkx */ - AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */ - AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_OUTPUT_PULLDOWN, MUX_MODE4) /* mii1_col.mcasp1_axr2 */ - AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */ - >; - }; - - mcasp1_pins_sleep: mcasp1_pins_sleep { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) - >; - }; - - mmc2_pins: pinmux_mmc2_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_wpn.gpio0_31 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */ - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ - >; - }; - - wl12xx_gpio: pinmux_wl12xx_gpio { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_csn0.gpio1_29 */ - >; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - - status = "okay"; - clock-frequency = <400000>; - - tps: tps@2d { - reg = <0x2d>; - }; - - lis331dlh: lis331dlh@18 { - compatible = "st,lis331dlh", "st,lis3lv02d"; - reg = <0x18>; - Vdd-supply = <&lis3_reg>; - Vdd_IO-supply = <&lis3_reg>; - - st,click-single-x; - st,click-single-y; - st,click-single-z; - st,click-thresh-x = <10>; - st,click-thresh-y = <10>; - st,click-thresh-z = <10>; - st,irq1-click; - st,irq2-click; - st,wakeup-x-lo; - st,wakeup-x-hi; - st,wakeup-y-lo; - st,wakeup-y-hi; - st,wakeup-z-lo; - st,wakeup-z-hi; - st,min-limit-x = <120>; - st,min-limit-y = <120>; - st,min-limit-z = <140>; - st,max-limit-x = <550>; - st,max-limit-y = <550>; - st,max-limit-z = <750>; - }; - - tlv320aic3106: tlv320aic3106@1b { - #sound-dai-cells = <0>; - compatible = "ti,tlv320aic3106"; - reg = <0x1b>; - status = "okay"; - - /* Regulators */ - AVDD-supply = <&v3_3d_reg>; - IOVDD-supply = <&v3_3d_reg>; - DRVDD-supply = <&v3_3d_reg>; - DVDD-supply = <&v1_8d_reg>; - }; -}; - -&usb { - status = "okay"; -}; - -&usb_ctrl_mod { - status = "okay"; -}; - -&usb0_phy { - status = "okay"; -}; - -&usb1_phy { - status = "okay"; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; - dr_mode = "host"; -}; - -&cppi41dma { - status = "okay"; -}; - -&epwmss2 { - status = "okay"; - - ecap2: ecap@100 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&ecap2_pins>; - }; -}; - -#include "tps65910.dtsi" - -&tps { - vcc1-supply = <&vbat>; - vcc2-supply = <&vbat>; - vcc3-supply = <&vbat>; - vcc4-supply = <&vbat>; - vcc5-supply = <&vbat>; - vcc6-supply = <&vbat>; - vcc7-supply = <&vbat>; - vccio-supply = <&vbat>; - - regulators { - vrtc_reg: regulator@0 { - regulator-always-on; - }; - - vio_reg: regulator@1 { - regulator-always-on; - }; - - vdd1_reg: regulator@2 { - /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ - regulator-name = "vdd_mpu"; - regulator-min-microvolt = <912500>; - regulator-max-microvolt = <1351500>; - regulator-boot-on; - regulator-always-on; - }; - - vdd2_reg: regulator@3 { - /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ - regulator-name = "vdd_core"; - regulator-min-microvolt = <912500>; - regulator-max-microvolt = <1150000>; - regulator-boot-on; - regulator-always-on; - }; - - vdd3_reg: regulator@4 { - regulator-always-on; - }; - - vdig1_reg: regulator@5 { - regulator-always-on; - }; - - vdig2_reg: regulator@6 { - regulator-always-on; - }; - - vpll_reg: regulator@7 { - regulator-always-on; - }; - - vdac_reg: regulator@8 { - regulator-always-on; - }; - - vaux1_reg: regulator@9 { - regulator-always-on; - }; - - vaux2_reg: regulator@10 { - regulator-always-on; - }; - - vaux33_reg: regulator@11 { - regulator-always-on; - }; - - vmmc_reg: regulator@12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; -}; - -&mac { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&cpsw_default>; - pinctrl-1 = <&cpsw_sleep>; - dual_emac = <1>; - status = "okay"; -}; - -&davinci_mdio { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&davinci_mdio_default>; - pinctrl-1 = <&davinci_mdio_sleep>; - status = "okay"; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; - - ethphy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&cpsw_emac0 { - phy-handle = <ðphy0>; - phy-mode = "rgmii-id"; - dual_emac_res_vlan = <1>; -}; - -&cpsw_emac1 { - phy-handle = <ðphy1>; - phy-mode = "rgmii-id"; - dual_emac_res_vlan = <2>; -}; - -&mmc1 { - status = "okay"; - vmmc-supply = <&vmmc_reg>; - bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; -}; - -&sham { - status = "okay"; -}; - -&aes { - status = "okay"; -}; - -&gpio0 { - ti,no-reset-on-init; -}; - -&mmc2 { - status = "okay"; - vmmc-supply = <&wl12xx_vmmc>; - ti,non-removable; - bus-width = <4>; - cap-power-off-card; - keep-power-in-suspend; - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; - - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@2 { - compatible = "ti,wl1271"; - reg = <2>; - interrupt-parent = <&gpio0>; - interrupts = <31 IRQ_TYPE_EDGE_RISING>; /* gpio 31 */ - ref-clock-frequency = <38400000>; - }; -}; - -&mcasp1 { - #sound-dai-cells = <0>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&mcasp1_pins>; - pinctrl-1 = <&mcasp1_pins_sleep>; - - status = "okay"; - - op-mode = <0>; /* MCASP_IIS_MODE */ - tdm-slots = <2>; - /* 4 serializers */ - serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ - 0 0 1 2 - >; - tx-num-evt = <32>; - rx-num-evt = <32>; -}; - -&tscadc { - status = "okay"; - tsc { - ti,wires = <4>; - ti,x-plate-resistance = <200>; - ti,coordinate-readouts = <5>; - ti,wire-config = <0x00 0x11 0x22 0x33>; - }; -}; - -&lcdc { - status = "okay"; - - blue-and-red-wiring = "crossed"; -}; - -&rtc { - clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; - clock-names = "ext-clk", "int-clk"; -}; diff --git a/sys/gnu/dts/arm/am335x-guardian.dts b/sys/gnu/dts/arm/am335x-guardian.dts deleted file mode 100644 index c9611ea4b88..00000000000 --- a/sys/gnu/dts/arm/am335x-guardian.dts +++ /dev/null @@ -1,511 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ - * Copyright (C) 2018 Robert Bosch Power Tools GmbH - */ -/dts-v1/; - -#include "am33xx.dtsi" -#include -#include - -/ { - model = "Bosch AM335x Guardian"; - compatible = "bosch,am335x-guardian", "ti,am33xx"; - - chosen { - stdout-path = &uart0; - tick-timer = &timer2; - }; - - cpus { - cpu@0 { - cpu0-supply = <&dcdc2_reg>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x10000000>; /* 256 MB */ - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&gpio_keys_pins>; - - button21 { - label = "guardian-power-button"; - linux,code = ; - gpios = <&gpio2 21 0>; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&leds_pins>; - - led1 { - label = "green:heartbeat"; - gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - - led2 { - label = "green:mmc0"; - gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc0"; - default-state = "off"; - }; - }; - - panel { - compatible = "ti,tilcdc,panel"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&lcd_pins_default &lcd_disen_pins>; - pinctrl-1 = <&lcd_pins_sleep>; - - display-timings { - 320x240 { - hactive = <320>; - vactive = <240>; - hback-porch = <68>; - hfront-porch = <20>; - hsync-len = <1>; - vback-porch = <18>; - vfront-porch = <4>; - vsync-len = <1>; - clock-frequency = <9000000>; - hsync-active = <0>; - vsync-active = <0>; - }; - }; - panel-info { - ac-bias = <255>; - ac-bias-intrpt = <0>; - dma-burst-sz = <16>; - bpp = <24>; - bus-width = <16>; - fdd = <0x80>; - sync-edge = <0>; - sync-ctrl = <1>; - raster-order = <0>; - fifo-th = <0>; - }; - - }; - - pwm7: dmtimer-pwm { - compatible = "ti,omap-dmtimer-pwm"; - ti,timers = <&timer7>; - pinctrl-names = "default"; - pinctrl-0 = <&dmtimer7_pins>; - }; - - vmmcsd_fixed: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "vmmcsd_fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&cppi41dma { - status = "okay"; -}; - -&elm { - status = "okay"; -}; - -&gpmc { - pinctrl-names = "default"; - pinctrl-0 = <&nandflash_pins>; - ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */ - status = "okay"; - - nand@0,0 { - compatible = "ti,omap2-nand"; - reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ - <1 IRQ_TYPE_NONE>; /* termcount */ - rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ - ti,nand-ecc-opt = "bch16"; - ti,elm-id = <&elm>; - nand-bus-width = <8>; - gpmc,device-width = <1>; - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <44>; - gpmc,cs-wr-off-ns = <44>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <34>; - gpmc,adv-wr-off-ns = <44>; - gpmc,we-on-ns = <0>; - gpmc,we-off-ns = <40>; - gpmc,oe-on-ns = <0>; - gpmc,oe-off-ns = <54>; - gpmc,access-ns = <64>; - gpmc,rd-cycle-ns = <82>; - gpmc,wr-cycle-ns = <82>; - gpmc,bus-turnaround-ns = <0>; - gpmc,cycle2cycle-delay-ns = <0>; - gpmc,clk-activation-ns = <0>; - gpmc,wr-access-ns = <40>; - gpmc,wr-data-mux-bus-ns = <0>; - - /* - * MTD partition table - * - * All SPL-* partitions are sized to minimal length which can - * be independently programmable. For NAND flash this is equal - * to size of erase-block. - */ - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "SPL"; - reg = <0x0 0x40000>; - }; - - partition@1 { - label = "SPL.backup1"; - reg = <0x40000 0x40000>; - }; - - partition@2 { - label = "SPL.backup2"; - reg = <0x80000 0x40000>; - }; - - partition@3 { - label = "SPL.backup3"; - reg = <0xc0000 0x40000>; - }; - - partition@4 { - label = "u-boot"; - reg = <0x100000 0x100000>; - }; - - partition@5 { - label = "u-boot.backup1"; - reg = <0x200000 0x100000>; - }; - - partition@6 { - label = "u-boot-env"; - reg = <0x300000 0x40000>; - }; - - partition@7 { - label = "u-boot-env.backup1"; - reg = <0x340000 0x40000>; - }; - - partition@8 { - label = "UBI"; - reg = <0x380000 0x1fc80000>; - }; - }; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - clock-frequency = <400000>; - status = "okay"; - - tps: tps@24 { - reg = <0x24>; - }; -}; - -&lcdc { - blue-and-red-wiring = "crossed"; - status = "okay"; -}; - -&mmc1 { - bus-width = <0x4>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; - vmmc-supply = <&vmmcsd_fixed>; - status = "okay"; -}; - -&rtc { - clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; - clock-names = "ext-clk", "int-clk"; - system-power-controller; -}; - -&spi0 { - ti,pindir-d0-out-d1-in; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins>; - status = "okay"; -}; - -#include "tps65217.dtsi" - -&tps { - ti,pmic-shutdown-controller; - interrupt-parent = <&intc>; - interrupts = <7>; /* NMI */ - - backlight { - isel = <1>; /* 1 - ISET1, 2 ISET2 */ - fdim = <100>; /* TPS65217_BL_FDIM_100HZ */ - default-brightness = <100>; - }; - - regulators { - dcdc1_reg: regulator@0 { - regulator-name = "vdds_dpr"; - regulator-always-on; - }; - - dcdc2_reg: regulator@1 { - regulator-name = "vdd_mpu"; - regulator-min-microvolt = <925000>; - regulator-max-microvolt = <1351500>; - regulator-boot-on; - regulator-always-on; - }; - - dcdc3_reg: regulator@2 { - regulator-name = "vdd_core"; - regulator-min-microvolt = <925000>; - regulator-max-microvolt = <1150000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1_reg: regulator@3 { - regulator-name = "vio,vrtc,vdds"; - regulator-always-on; - }; - - ldo2_reg: regulator@4 { - regulator-name = "vdd_3v3aux"; - regulator-always-on; - }; - - ldo3_reg: regulator@5 { - regulator-name = "vdd_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo4_reg: regulator@6 { - regulator-name = "vdd_3v3a"; - regulator-always-on; - }; - }; -}; - -&tscadc { - status = "okay"; - - adc { - ti,adc-channels = <0 1 2 3 4 5 6>; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - status = "okay"; -}; - -&usb { - status = "okay"; -}; - -&usb_ctrl_mod { - status = "okay"; -}; - -&usb0 { - dr_mode = "peripheral"; - status = "okay"; -}; - -&usb0_phy { - status = "okay"; -}; - -&usb1 { - dr_mode = "host"; - status = "okay"; -}; - -&usb1_phy { - status = "okay"; -}; - -&am33xx_pinmux { - pinctrl-names = "default"; - pinctrl-0 = <&clkout2_pin &gpio_pins>; - - clkout2_pin: pinmux_clkout2_pin { - pinctrl-single,pins = < - AM33XX_IOPAD(0x9b4, PIN_OUTPUT_PULLDOWN | MUX_MODE3) - >; - }; - - dmtimer7_pins: pinmux_dmtimer7_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x968, PIN_OUTPUT | MUX_MODE5) - >; - }; - - gpio_keys_pins: pinmux_gpio_keys_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x940, PIN_INPUT | MUX_MODE7) - >; - }; - - gpio_pins: pinmux_gpio_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x928, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x990, PIN_OUTPUT | MUX_MODE7) - >; - }; - - i2c0_pins: pinmux_i2c0_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) - AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) - >; - }; - - lcd_disen_pins: pinmux_lcd_disen_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x9a4, PIN_OUTPUT_PULLUP | SLEWCTRL_SLOW | MUX_MODE7) - >; - }; - - lcd_pins_default: pinmux_lcd_pins_default { - pinctrl-single,pins = < - AM33XX_IOPAD(0x820, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) - AM33XX_IOPAD(0x824, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) - AM33XX_IOPAD(0x828, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) - AM33XX_IOPAD(0x82c, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) - AM33XX_IOPAD(0x830, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) - AM33XX_IOPAD(0x834, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) - AM33XX_IOPAD(0x838, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) - AM33XX_IOPAD(0x83c, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) - AM33XX_IOPAD(0x8a0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) - AM33XX_IOPAD(0x8a4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) - AM33XX_IOPAD(0x8a8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) - AM33XX_IOPAD(0x8ac, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) - AM33XX_IOPAD(0x8b0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) - AM33XX_IOPAD(0x8b4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) - AM33XX_IOPAD(0x8b8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) - AM33XX_IOPAD(0x8bc, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) - AM33XX_IOPAD(0x8c0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) - AM33XX_IOPAD(0x8c4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) - AM33XX_IOPAD(0x8c8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) - AM33XX_IOPAD(0x8cc, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) - AM33XX_IOPAD(0x8d0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) - AM33XX_IOPAD(0x8d4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) - AM33XX_IOPAD(0x8d8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) - AM33XX_IOPAD(0x8dc, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) - AM33XX_IOPAD(0x8e0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) - AM33XX_IOPAD(0x8e4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) - AM33XX_IOPAD(0x8e8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) - AM33XX_IOPAD(0x8ec, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) - >; - }; - - lcd_pins_sleep: pinmux_lcd_pins_sleep { - pinctrl-single,pins = < - AM33XX_IOPAD(0x8a0, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) - AM33XX_IOPAD(0x8a4, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) - AM33XX_IOPAD(0x8a8, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) - AM33XX_IOPAD(0x8ac, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) - AM33XX_IOPAD(0x8b0, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) - AM33XX_IOPAD(0x8b4, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) - AM33XX_IOPAD(0x8b8, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) - AM33XX_IOPAD(0x8bc, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) - AM33XX_IOPAD(0x8c0, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) - AM33XX_IOPAD(0x8c4, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) - AM33XX_IOPAD(0x8c8, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) - AM33XX_IOPAD(0x8cc, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) - AM33XX_IOPAD(0x8d0, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) - AM33XX_IOPAD(0x8d4, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) - AM33XX_IOPAD(0x8d8, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) - AM33XX_IOPAD(0x8dc, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) - AM33XX_IOPAD(0x8e0, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW | MUX_MODE7) - AM33XX_IOPAD(0x8e4, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW | MUX_MODE7) - AM33XX_IOPAD(0x8e8, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW | MUX_MODE7) - AM33XX_IOPAD(0x8ec, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW | MUX_MODE7) - >; - }; - - leds_pins: pinmux_leds_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x868, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x86c, PIN_OUTPUT | MUX_MODE7) - >; - }; - - mmc1_pins: pinmux_mmc1_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) - AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) - AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) - AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) - AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) - AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) - AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7) - >; - }; - - spi0_pins: pinmux_spi0_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x950, PIN_OUTPUT_PULLDOWN | MUX_MODE0) - AM33XX_IOPAD(0x954, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0) - AM33XX_IOPAD(0x95c, PIN_OUTPUT_PULLUP | MUX_MODE0) - >; - }; - - uart0_pins: pinmux_uart0_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) - AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) - >; - }; - - nandflash_pins: pinmux_nandflash_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x800, PIN_INPUT | MUX_MODE0) - AM33XX_IOPAD(0x804, PIN_INPUT | MUX_MODE0) - AM33XX_IOPAD(0x808, PIN_INPUT | MUX_MODE0) - AM33XX_IOPAD(0x80c, PIN_INPUT | MUX_MODE0) - AM33XX_IOPAD(0x810, PIN_INPUT | MUX_MODE0) - AM33XX_IOPAD(0x814, PIN_INPUT | MUX_MODE0) - AM33XX_IOPAD(0x818, PIN_INPUT | MUX_MODE0) - AM33XX_IOPAD(0x81c, PIN_INPUT | MUX_MODE0) - AM33XX_IOPAD(0x870, PIN_INPUT | MUX_MODE0) - AM33XX_IOPAD(0x874, PIN_OUTPUT | MUX_MODE0) - AM33XX_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) - AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) - AM33XX_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) - AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) - AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) - >; - }; -}; diff --git a/sys/gnu/dts/arm/am335x-icev2.dts b/sys/gnu/dts/arm/am335x-icev2.dts deleted file mode 100644 index 204bccfcc11..00000000000 --- a/sys/gnu/dts/arm/am335x-icev2.dts +++ /dev/null @@ -1,499 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - */ - -/* - * AM335x ICE V2 board - * http://www.ti.com/tool/tmdsice3359 - */ - -/dts-v1/; - -#include "am33xx.dtsi" - -/ { - model = "TI AM3359 ICE-V2"; - compatible = "ti,am3359-icev2", "ti,am33xx"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x10000000>; /* 256 MB */ - }; - - chosen { - stdout-path = &uart3; - }; - - vbat: fixedregulator0 { - compatible = "regulator-fixed"; - regulator-name = "vbat"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - }; - - vtt_fixed: fixedregulator1 { - compatible = "regulator-fixed"; - regulator-name = "vtt"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - gpio = <&gpio0 18 GPIO_ACTIVE_HIGH>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - }; - - leds-iio { - status = "disabled"; - compatible = "gpio-leds"; - led-out0 { - label = "out0"; - gpios = <&tpic2810 0 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-out1 { - label = "out1"; - gpios = <&tpic2810 1 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-out2 { - label = "out2"; - gpios = <&tpic2810 2 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-out3 { - label = "out3"; - gpios = <&tpic2810 3 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-out4 { - label = "out4"; - gpios = <&tpic2810 4 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-out5 { - label = "out5"; - gpios = <&tpic2810 5 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-out6 { - label = "out6"; - gpios = <&tpic2810 6 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-out7 { - label = "out7"; - gpios = <&tpic2810 7 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - - /* Tricolor status LEDs */ - leds1 { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&user_leds>; - - led0 { - label = "status0:red:cpu0"; - gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>; - default-state = "off"; - linux,default-trigger = "cpu0"; - }; - - led1 { - label = "status0:green:usr"; - gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led2 { - label = "status0:yellow:usr"; - gpios = <&gpio3 9 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led3 { - label = "status1:red:mmc0"; - gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; - default-state = "off"; - linux,default-trigger = "mmc0"; - }; - - led4 { - label = "status1:green:usr"; - gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led5 { - label = "status1:yellow:usr"; - gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - gpio-decoder { - compatible = "gpio-decoder"; - gpios = <&pca9536 3 GPIO_ACTIVE_HIGH>, - <&pca9536 2 GPIO_ACTIVE_HIGH>, - <&pca9536 1 GPIO_ACTIVE_HIGH>, - <&pca9536 0 GPIO_ACTIVE_HIGH>; - linux,axis = <0>; /* ABS_X */ - decoder-max-value = <9>; - }; -}; - -&am33xx_pinmux { - user_leds: user_leds { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT, MUX_MODE7) /* (J18) gmii1_txd3.gpio0[16] */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT, MUX_MODE7) /* (K15) gmii1_txd2.gpio0[17] */ - AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT, MUX_MODE7) /* (A15) xdma_event_intr0.gpio0[19] */ - AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT, MUX_MODE7) /* (D14) xdma_event_intr1.gpio0[20] */ - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_OUTPUT, MUX_MODE7) /* (U9) gpmc_csn1.gpio1[30] */ - AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT, MUX_MODE7) /* (K18) gmii1_txclk.gpio3[9] */ - >; - }; - - mmc0_pins_default: mmc0_pins_default { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) - >; - }; - - i2c0_pins_default: i2c0_pins_default { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT, MUX_MODE0) - >; - }; - - spi0_pins_default: spi0_pins_default { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT_PULLUP, MUX_MODE7) /* (B12) mcasp0_aclkr.gpio3[18] */ - >; - }; - - uart3_pins_default: uart3_pins_default { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE1) /* (L17) gmii1_rxd3.uart3_rxd */ - AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_OUTPUT_PULLUP, MUX_MODE1) /* (L16) gmii1_rxd2.uart3_txd */ - >; - }; - - cpsw_default: cpsw_default { - pinctrl-single,pins = < - /* Slave 1, RMII mode */ - AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLUP, MUX_MODE1) /* mii1_crs.rmii1_crs_dv */ - AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE1) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE1) - AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_txd0.rmii1_txd0 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_txd1.rmii1_txd1 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_txen.rmii1_txen */ - /* Slave 2, RMII mode */ - AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_wait0.rmii2_crs_dv */ - AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLUP, MUX_MODE1) /* mii1_col.rmii2_refclk */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_a11.rmii2_rxd0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_a10.rmii2_rxd1 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_wpn.rmii2_rxerr */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* gpmc_a5.rmii2_txd0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* gpmc_a4.rmii2_txd1 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* gpmc_a0.rmii2_txen */ - >; - }; - - cpsw_sleep: cpsw_sleep { - pinctrl-single,pins = < - /* Slave 1 reset value */ - AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) - - /* Slave 2 reset value */ - AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLDOWN, MUX_MODE7) - >; - }; - - davinci_mdio_default: davinci_mdio_default { - pinctrl-single,pins = < - /* MDIO */ - AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) - >; - }; - - davinci_mdio_sleep: davinci_mdio_sleep { - pinctrl-single,pins = < - /* MDIO reset value */ - AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) - >; - }; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_default>; - - status = "okay"; - clock-frequency = <400000>; - - tps: power-controller@2d { - reg = <0x2d>; - }; - - tpic2810: gpio@60 { - compatible = "ti,tpic2810"; - reg = <0x60>; - gpio-controller; - #gpio-cells = <2>; - }; - - pca9536: gpio@41 { - compatible = "ti,pca9536"; - reg = <0x41>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -&spi0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins_default>; - - sn65hvs882@1 { - compatible = "pisosr-gpio"; - gpio-controller; - #gpio-cells = <2>; - - load-gpios = <&gpio3 18 GPIO_ACTIVE_LOW>; - - reg = <1>; - spi-max-frequency = <1000000>; - spi-cpol; - }; - - spi_nor: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "winbond,w25q64", "jedec,spi-nor"; - spi-max-frequency = <80000000>; - m25p,fast-read; - reg = <0>; - - partition@0 { - label = "u-boot-spl"; - reg = <0x0 0x80000>; - read-only; - }; - - partition@1 { - label = "u-boot"; - reg = <0x80000 0x100000>; - read-only; - }; - - partition@2 { - label = "u-boot-env"; - reg = <0x180000 0x20000>; - read-only; - }; - - partition@3 { - label = "misc"; - reg = <0x1A0000 0x660000>; - }; - }; - -}; - -&tscadc { - status = "okay"; - adc { - ti,adc-channels = <1 2 3 4 5 6 7>; - }; -}; - -#include "tps65910.dtsi" - -&tps { - vcc1-supply = <&vbat>; - vcc2-supply = <&vbat>; - vcc3-supply = <&vbat>; - vcc4-supply = <&vbat>; - vcc5-supply = <&vbat>; - vcc6-supply = <&vbat>; - vcc7-supply = <&vbat>; - vccio-supply = <&vbat>; - - regulators { - vrtc_reg: regulator@0 { - regulator-always-on; - }; - - vio_reg: regulator@1 { - regulator-always-on; - }; - - vdd1_reg: regulator@2 { - regulator-name = "vdd_mpu"; - regulator-min-microvolt = <912500>; - regulator-max-microvolt = <1326000>; - regulator-boot-on; - regulator-always-on; - }; - - vdd2_reg: regulator@3 { - regulator-name = "vdd_core"; - regulator-min-microvolt = <912500>; - regulator-max-microvolt = <1144000>; - regulator-boot-on; - regulator-always-on; - }; - - vdd3_reg: regulator@4 { - regulator-always-on; - }; - - vdig1_reg: regulator@5 { - regulator-always-on; - }; - - vdig2_reg: regulator@6 { - regulator-always-on; - }; - - vpll_reg: regulator@7 { - regulator-always-on; - }; - - vdac_reg: regulator@8 { - regulator-always-on; - }; - - vaux1_reg: regulator@9 { - regulator-always-on; - }; - - vaux2_reg: regulator@10 { - regulator-always-on; - }; - - vaux33_reg: regulator@11 { - regulator-always-on; - }; - - vmmc_reg: regulator@12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; -}; - -&mmc1 { - status = "okay"; - vmmc-supply = <&vmmc_reg>; - bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_default>; -}; - -&gpio0_target { - /* Do not idle the GPIO used for holding the VTT regulator */ - ti,no-reset-on-init; - ti,no-idle-on-init; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins_default>; - status = "okay"; -}; - -&gpio3 { - p4 { - gpio-hog; - gpios = <4 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "PR1_MII_CTRL"; - }; - - p10 { - gpio-hog; - gpios = <10 GPIO_ACTIVE_HIGH>; - /* ETH1 mux: Low for MII-PRU, high for RMII-CPSW */ - output-high; - line-name = "MUX_MII_CTL1"; - }; -}; - -&cpsw_emac0 { - phy-handle = <ðphy0>; - phy-mode = "rmii"; - dual_emac_res_vlan = <1>; -}; - -&cpsw_emac1 { - phy-handle = <ðphy1>; - phy-mode = "rmii"; - dual_emac_res_vlan = <2>; -}; - -&mac { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&cpsw_default>; - pinctrl-1 = <&cpsw_sleep>; - status = "okay"; - dual_emac; -}; - -&davinci_mdio { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&davinci_mdio_default>; - pinctrl-1 = <&davinci_mdio_sleep>; - status = "okay"; - reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; - reset-delay-us = <2>; /* PHY datasheet states 1uS min */ - - ethphy0: ethernet-phy@1 { - reg = <1>; - }; - - ethphy1: ethernet-phy@3 { - reg = <3>; - }; -}; diff --git a/sys/gnu/dts/arm/am335x-igep0033.dtsi b/sys/gnu/dts/arm/am335x-igep0033.dtsi deleted file mode 100644 index eabcc8b2e4e..00000000000 --- a/sys/gnu/dts/arm/am335x-igep0033.dtsi +++ /dev/null @@ -1,325 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * am335x-igep0033.dtsi - Device Tree file for IGEP COM AQUILA AM335x - * - * Copyright (C) 2013 ISEE 2007 SL - http://www.isee.biz - */ - -/dts-v1/; - -#include "am33xx.dtsi" -#include - -/ { - cpus { - cpu@0 { - cpu0-supply = <&vdd1_reg>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x10000000>; /* 256 MB */ - }; - - leds { - pinctrl-names = "default"; - pinctrl-0 = <&leds_pins>; - - compatible = "gpio-leds"; - - led0 { - label = "com:green:user"; - gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; - - vbat: fixedregulator0 { - compatible = "regulator-fixed"; - regulator-name = "vbat"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - }; - - vmmc: fixedregulator1 { - compatible = "regulator-fixed"; - regulator-name = "vmmc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&am33xx_pinmux { - i2c0_pins: pinmux_i2c0_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) - >; - }; - - nandflash_pins: pinmux_nandflash_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_wpn.gpio0_30 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0) - >; - }; - - uart0_pins: pinmux_uart0_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - >; - }; - - leds_pins: pinmux_leds_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a7.gpio1_23 */ - >; - }; -}; - -&mac { - status = "okay"; -}; - -&davinci_mdio { - status = "okay"; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; - - ethphy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&cpsw_emac0 { - phy-handle = <ðphy0>; - phy-mode = "rmii"; - -}; - -&cpsw_emac1 { - phy-handle = <ðphy1>; - phy-mode = "rmii"; -}; - -&elm { - status = "okay"; -}; - -&gpmc { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&nandflash_pins>; - - ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */ - - nand@0,0 { - compatible = "ti,omap2-nand"; - reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ - <1 IRQ_TYPE_NONE>; /* termcount */ - rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ - nand-bus-width = <8>; - ti,nand-ecc-opt = "bch8"; - gpmc,device-width = <1>; - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <44>; - gpmc,cs-wr-off-ns = <44>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <34>; - gpmc,adv-wr-off-ns = <44>; - gpmc,we-on-ns = <0>; - gpmc,we-off-ns = <40>; - gpmc,oe-on-ns = <0>; - gpmc,oe-off-ns = <54>; - gpmc,access-ns = <64>; - gpmc,rd-cycle-ns = <82>; - gpmc,wr-cycle-ns = <82>; - gpmc,bus-turnaround-ns = <0>; - gpmc,cycle2cycle-delay-ns = <0>; - gpmc,clk-activation-ns = <0>; - gpmc,wr-access-ns = <40>; - gpmc,wr-data-mux-bus-ns = <0>; - - #address-cells = <1>; - #size-cells = <1>; - ti,elm-id = <&elm>; - - /* MTD partition table */ - partition@0 { - label = "SPL"; - reg = <0x00000000 0x000080000>; - }; - - partition@1 { - label = "U-boot"; - reg = <0x00080000 0x001e0000>; - }; - - partition@2 { - label = "U-Boot Env"; - reg = <0x00260000 0x00020000>; - }; - - partition@3 { - label = "Kernel"; - reg = <0x00280000 0x00500000>; - }; - - partition@4 { - label = "File System"; - reg = <0x00780000 0x007880000>; - }; - }; -}; - -&i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - - clock-frequency = <400000>; - - tps: tps@2d { - reg = <0x2d>; - }; -}; - -&mmc1 { - status = "okay"; - vmmc-supply = <&vmmc>; - bus-width = <4>; -}; - -&uart0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; -}; - -&usb { - status = "okay"; -}; - -&usb_ctrl_mod { - status = "okay"; -}; - -&usb0_phy { - status = "okay"; -}; - -&usb1_phy { - status = "okay"; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; - dr_mode = "host"; -}; - -&cppi41dma { - status = "okay"; -}; - -#include "tps65910.dtsi" - -&tps { - vcc1-supply = <&vbat>; - vcc2-supply = <&vbat>; - vcc3-supply = <&vbat>; - vcc4-supply = <&vbat>; - vcc5-supply = <&vbat>; - vcc6-supply = <&vbat>; - vcc7-supply = <&vbat>; - vccio-supply = <&vbat>; - - regulators { - vrtc_reg: regulator@0 { - regulator-always-on; - }; - - vio_reg: regulator@1 { - regulator-always-on; - }; - - vdd1_reg: regulator@2 { - /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ - regulator-name = "vdd_mpu"; - regulator-min-microvolt = <912500>; - regulator-max-microvolt = <1312500>; - regulator-boot-on; - regulator-always-on; - }; - - vdd2_reg: regulator@3 { - /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ - regulator-name = "vdd_core"; - regulator-min-microvolt = <912500>; - regulator-max-microvolt = <1150000>; - regulator-boot-on; - regulator-always-on; - }; - - vdd3_reg: regulator@4 { - regulator-always-on; - }; - - vdig1_reg: regulator@5 { - regulator-always-on; - }; - - vdig2_reg: regulator@6 { - regulator-always-on; - }; - - vpll_reg: regulator@7 { - regulator-always-on; - }; - - vdac_reg: regulator@8 { - regulator-always-on; - }; - - vaux1_reg: regulator@9 { - regulator-always-on; - }; - - vaux2_reg: regulator@10 { - regulator-always-on; - }; - - vaux33_reg: regulator@11 { - regulator-always-on; - }; - - vmmc_reg: regulator@12 { - regulator-always-on; - }; - }; -}; - diff --git a/sys/gnu/dts/arm/am335x-lxm.dts b/sys/gnu/dts/arm/am335x-lxm.dts deleted file mode 100644 index a8005e975ea..00000000000 --- a/sys/gnu/dts/arm/am335x-lxm.dts +++ /dev/null @@ -1,367 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 NovaTech LLC - http://www.novatechweb.com - */ -/dts-v1/; - -#include "am33xx.dtsi" - -/ { - model = "NovaTech OrionLXm"; - compatible = "novatech,am335x-lxm", "ti,am33xx"; - - cpus { - cpu@0 { - cpu0-supply = <&vdd1_reg>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000>; /* 512 MB */ - }; - - /* Power supply provides a fixed 5V @2A */ - vbat: fixedregulator0 { - compatible = "regulator-fixed"; - regulator-name = "vbat"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - }; - - /* Power supply provides a fixed 3.3V @3A */ - vmmcsd_fixed: fixedregulator1 { - compatible = "regulator-fixed"; - regulator-name = "vmmcsd_fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; -}; - -&am33xx_pinmux { - mmc1_pins: pinmux_mmc1_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) - >; - }; - - i2c0_pins: pinmux_i2c0_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT, MUX_MODE0) - >; - }; - - cpsw_default: cpsw_default { - pinctrl-single,pins = < - /* Slave 1 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_int */ - AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE1) /* rmii1_crs_dv */ - AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE1) /* rmii1_rxer */ - AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* rmii1_txen */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* rmii1_td1 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* rmii1_td0 */ - AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE1) /* rmii1_rd1 */ - AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE1) /* rmii1_rd0 */ - AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0) - - /* Slave 2 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* rmii2_txen */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* rmii2_td1 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* rmii2_td0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_rd1 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_rd0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_crs_dv */ - AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_rxer */ - AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_int */ - AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE1) /* rmii2_refclk */ - >; - }; - - cpsw_sleep: cpsw_sleep { - pinctrl-single,pins = < - /* Slave 1 reset value */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_int */ - AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_crs_dv */ - AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_rxer */ - AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_txen */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_td1 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_td0 */ - AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_rd1 */ - AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_rd0 */ - AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_refclk */ - - /* Slave 2 reset value*/ - AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_txen */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_td1 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_td0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_rd1 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_rd0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_crs_dv */ - AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_rxer */ - AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_int */ - AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_refclk */ - >; - }; - - davinci_mdio_default: davinci_mdio_default { - pinctrl-single,pins = < - /* MDIO */ - AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) - >; - }; - - davinci_mdio_sleep: davinci_mdio_sleep { - pinctrl-single,pins = < - /* MDIO reset value */ - AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) - >; - }; - - emmc_pins: pinmux_emmc_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */ - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ - >; - }; - - uart0_pins: pinmux_uart0_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - >; - }; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - - status = "okay"; - clock-frequency = <400000>; - - serial_config1: serial_config1@20 { - compatible = "nxp,pca9539"; - reg = <0x20>; - }; - - serial_config2: serial_config2@21 { - compatible = "nxp,pca9539"; - reg = <0x21>; - }; - - tps: tps@2d { - compatible = "ti,tps65910"; - reg = <0x2d>; - }; -}; - -/include/ "tps65910.dtsi" - -&tps { - vcc1-supply = <&vbat>; - vcc2-supply = <&vbat>; - vcc3-supply = <&vbat>; - vcc4-supply = <&vbat>; - vcc5-supply = <&vbat>; - vcc6-supply = <&vbat>; - vcc7-supply = <&vbat>; - vccio-supply = <&vbat>; - - regulators { - /* vrtc - unused */ - - vio_reg: regulator@1 { - regulator-name = "vio_1v5,ddr"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - regulator-always-on; - }; - - vdd1_reg: regulator@2 { - regulator-name = "vdd1,mpu"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - regulator-always-on; - }; - - vdd2_reg: regulator@3 { - regulator-name = "vdd2_1v1,core"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-boot-on; - regulator-always-on; - }; - - /* vdd3 - unused */ - - /* vdig1 - unused */ - - vdig2_reg: regulator@6 { - regulator-name = "vdig2_1v8,vdds_pll"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - /* vpll - unused */ - - vdac_reg: regulator@8 { - regulator-name = "vdac_1v8,vdds"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - vaux1_reg: regulator@9 { - regulator-name = "vaux1_1v8,usb"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - vaux2_reg: regulator@10 { - regulator-name = "vaux2_3v3,io"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - vaux33_reg: regulator@11 { - regulator-name = "vaux33_3v3,usb"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - vmmc_reg: regulator@12 { - regulator-name = "vmmc_3v3,io"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - }; -}; - -&sham { - status = "okay"; -}; - -&aes { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - - status = "okay"; -}; - -&usb { - status = "okay"; -}; - -&usb_ctrl_mod { - status = "okay"; -}; - -&usb0_phy { - status = "okay"; -}; - -&usb1_phy { - status = "okay"; -}; - -&usb0 { - status = "okay"; - dr_mode = "host"; -}; - -&usb1 { - status = "okay"; - dr_mode = "host"; -}; - -&cppi41dma { - status = "okay"; -}; - -&cpsw_emac0 { - phy-handle = <ðphy0>; - phy-mode = "rmii"; - dual_emac_res_vlan = <2>; -}; - -&cpsw_emac1 { - phy-handle = <ðphy1>; - phy-mode = "rmii"; - dual_emac_res_vlan = <3>; -}; - -&mac { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&cpsw_default>; - pinctrl-1 = <&cpsw_sleep>; - dual_emac = <1>; - status = "okay"; -}; - -&davinci_mdio { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&davinci_mdio_default>; - pinctrl-1 = <&davinci_mdio_sleep>; - status = "okay"; - - ethphy0: ethernet-phy@5 { - reg = <5>; - }; - - ethphy1: ethernet-phy@4 { - reg = <4>; - }; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - vmmc-supply = <&vmmcsd_fixed>; - bus-width = <4>; - status = "okay"; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&emmc_pins>; - vmmc-supply = <&vmmcsd_fixed>; - bus-width = <8>; - ti,non-removable; - status = "okay"; -}; - diff --git a/sys/gnu/dts/arm/am335x-moxa-uc-2100-common.dtsi b/sys/gnu/dts/arm/am335x-moxa-uc-2100-common.dtsi deleted file mode 100644 index 671d4a5da9c..00000000000 --- a/sys/gnu/dts/arm/am335x-moxa-uc-2100-common.dtsi +++ /dev/null @@ -1,244 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2018 MOXA Inc. - https://www.moxa.com/ - * - * Authors: SZ Lin (林上智) - * Wes Huang (黃淵河) - * Fero JD Zhou (周俊達) - */ - -#include "am33xx.dtsi" - -/ { - vbat: vbat-regulator { - compatible = "regulator-fixed"; - }; - - /* Power supply provides a fixed 3.3V @3A */ - vmmcsd_fixed: vmmcsd-regulator { - compatible = "regulator-fixed"; - regulator-name = "vmmcsd_fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; - - buttons: push_button { - compatible = "gpio-keys"; - }; -}; - -&am33xx_pinmux { - pinctrl-names = "default"; - - i2c0_pins: pinmux_i2c0_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) - >; - }; - - push_button_pins: pinmux_push_button { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_hsync.gpio2_23 */ - >; - }; - - uart0_pins: pinmux_uart0_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - >; - }; - - davinci_mdio_default: davinci_mdio_default { - pinctrl-single,pins = < - /* MDIO */ - AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) - >; - }; - - mmc1_pins_default: pinmux_mmc1_pins { - pinctrl-single,pins = < - /* eMMC */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad12.mmc1_dat0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad13.mmc1_dat1 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad14.mmc1_dat2 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad15.mmc1_dat3 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad8.mmc1_dat4 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad9.mmc1_dat5 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad10.mmc1_dat6 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad11.mmc1_dat7 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */ - >; - }; - - spi0_pins: pinmux_spi0 { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0) - >; - }; -}; - -&uart0 { - /* Console */ - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - - status = "okay"; - clock-frequency = <400000>; - - eeprom: eeprom@50 { - compatible = "atmel,24c16"; - pagesize = <16>; - reg = <0x50>; - }; - - rtc_wdt: rtc_wdt@68 { - compatible = "dallas,ds1374"; - reg = <0x68>; - }; -}; - -&usb { - status = "okay"; -}; - -&usb_ctrl_mod { - status = "okay"; -}; - -&usb0_phy { - status = "okay"; -}; - -&usb0 { - status = "okay"; - dr_mode = "host"; -}; - -&cppi41dma { - status = "okay"; -}; - -/* Power */ -&vbat { - regulator-name = "vbat"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; -}; - -&mac { - pinctrl-names = "default"; - pinctrl-0 = <&cpsw_default>; - status = "okay"; -}; - -&davinci_mdio { - pinctrl-names = "default"; - pinctrl-0 = <&davinci_mdio_default>; - status = "okay"; -}; - -&cpsw_emac0 { - status = "okay"; -}; - -&cpsw_emac1 { - status = "okay"; -}; - -&sham { - status = "okay"; -}; - -&aes { - status = "okay"; -}; - -&gpio0 { - ti,no-reset-on-init; -}; - -&mmc2 { - pinctrl-names = "default"; - vmmc-supply = <&vmmcsd_fixed>; - bus-width = <8>; - pinctrl-0 = <&mmc1_pins_default>; - ti,non-removable; - status = "okay"; -}; - -&buttons { - pinctrl-names = "default"; - pinctrl-0 = <&push_button_pins>; - #address-cells = <1>; - #size-cells = <0>; - - button@0 { - label = "push_button"; - linux,code = <0x100>; - gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; - }; -}; - -/* SPI Busses */ -&spi0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins>; - - m25p80@0 { - compatible = "mx25l6405d"; - spi-max-frequency = <40000000>; - - reg = <0>; - spi-cpol; - spi-cpha; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* reg : The partition's offset and size within the mtd bank. */ - partitions@0 { - label = "MLO"; - reg = <0x0 0x80000>; - }; - - partitions@1 { - label = "U-Boot"; - reg = <0x80000 0x100000>; - }; - - partitions@2 { - label = "U-Boot Env"; - reg = <0x180000 0x40000>; - }; - }; - }; -}; - -&spi1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&spi1_pins>; - - tpm_spi_tis@0 { - compatible = "tcg,tpm_tis-spi"; - reg = <0>; - spi-max-frequency = <500000>; - }; -}; diff --git a/sys/gnu/dts/arm/am335x-moxa-uc-2101.dts b/sys/gnu/dts/arm/am335x-moxa-uc-2101.dts deleted file mode 100644 index 5923b6e7e1c..00000000000 --- a/sys/gnu/dts/arm/am335x-moxa-uc-2101.dts +++ /dev/null @@ -1,69 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2018 MOXA Inc. - https://www.moxa.com/ - * - * Authors: SZ Lin (林上智) - * Wes Huang (黃淵河) - * Fero JD Zhou (周俊達) - */ - -/dts-v1/; - -#include "am335x-moxa-uc-2100-common.dtsi" - -/ { - model = "Moxa UC-2101"; - compatible = "moxa,uc-2101", "ti,am33xx"; - - leds { - compatible = "gpio-leds"; - led1 { - label = "UC2100:GREEN:USER"; - gpios = <&gpio3 10 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; -}; - -&am33xx_pinmux { - pinctrl-names = "default"; - - cpsw_default: cpsw_default { - pinctrl-single,pins = < - /* Slave 1 */ - AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE1) /* mii1_crs.rmii1_crs_dv */ - AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */ - AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_txen.rmii1_txen */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_txd1.rmii1_txd1 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_txd0.rmii1_txd0 */ - AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */ - AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */ - AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0) - >; - }; - - spi1_pins: pinmux_spi1 { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, PIN_INPUT_PULLUP, MUX_MODE4) /* ecap0_in_pwm0_out.spi1_sclk */ - AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLUP, MUX_MODE4) /* uart1_ctsn.spi1_cs0 */ - AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT_PULLUP, MUX_MODE4) /* uart0_ctsn.spi1_d0 */ - AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLUP, MUX_MODE4) /* uart0_rtsn.spi1_d1 */ - >; - }; -}; - -&davinci_mdio { - phy0: ethernet-phy@4 { - reg = <4>; - }; -}; - -&cpsw_emac0 { - status = "okay"; - phy-handle = <&phy0>; - phy-mode = "rmii"; -}; - -&cpsw_emac1 { - status = "disabled"; -}; diff --git a/sys/gnu/dts/arm/am335x-moxa-uc-8100-me-t.dts b/sys/gnu/dts/arm/am335x-moxa-uc-8100-me-t.dts deleted file mode 100644 index 783d411f2ce..00000000000 --- a/sys/gnu/dts/arm/am335x-moxa-uc-8100-me-t.dts +++ /dev/null @@ -1,525 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2017 MOXA Inc. - https://www.moxa.com/ - * - * Author: SZ Lin (林上智) - */ - -/dts-v1/; - -#include "am33xx.dtsi" - -/ { - model = "Moxa UC-8100-ME-T"; - compatible = "moxa,uc-8100-me-t", "ti,am33xx"; - - cpus { - cpu@0 { - cpu0-supply = <&vdd1_reg>; - }; - }; - - memory { - device_type = "memory"; - reg = <0x80000000 0x20000000>; /* 512 MB */ - }; - - vbat: vbat-regulator { - compatible = "regulator-fixed"; - }; - - /* Power supply provides a fixed 3.3V @3A */ - vmmcsd_fixed: vmmcsd-regulator { - compatible = "regulator-fixed"; - regulator-name = "vmmcsd_fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; - - leds { - compatible = "gpio-leds"; - led1 { - label = "uc8100me:CEL1"; - gpios = <&gpio_xten 8 0>; - default-state = "off"; - }; - - led2 { - label = "uc8100me:CEL2"; - gpios = <&gpio_xten 9 0>; - default-state = "off"; - }; - - led3 { - label = "uc8100me:CEL3"; - gpios = <&gpio_xten 10 0>; - default-state = "off"; - }; - - led4 { - label = "uc8100me:DIA1"; - gpios = <&gpio_xten 11 0>; - default-state = "off"; - }; - led5 { - label = "uc8100me:DIA2"; - gpios = <&gpio_xten 12 0>; - default-state = "off"; - }; - led6 { - label = "uc8100me:DIA3"; - gpios = <&gpio_xten 13 0>; - default-state = "off"; - }; - led7 { - label = "uc8100me:SD"; - gpios = <&gpio_xten 14 0>; - default-state = "off"; - }; - led8 { - label = "uc8100me:USB"; - gpios = <&gpio_xten 15 0>; - default-state = "off"; - }; - led9 { - label = "uc8100me:USER"; - gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - - buttons: push_button { - compatible = "gpio-keys"; - }; - -}; - -&am33xx_pinmux { - pinctrl-names = "default"; - pinctrl-0 = <&minipcie_pins>; - - minipcie_pins: pinmux_minipcie { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_pclk.gpio2_24 */ - AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_ac_bias_en.gpio2_25 */ - AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_vsync.gpio2_22 Power off PIN*/ - >; - }; - - push_button_pins: pinmux_push_button { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLDOWN, MUX_MODE7) /* mcasp0_ahcklx.gpio3_21 */ - >; - }; - - i2c0_pins: pinmux_i2c0_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) - >; - }; - - - i2c1_pins: pinmux_i2c1_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart0_ctsn.i2c1_sda */ - AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart0_rtsn.i2c1_scl */ - >; - }; - - uart0_pins: pinmux_uart0_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - >; - }; - - uart1_pins: pinmux_uart1_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT, MUX_MODE0) - >; - }; - - uart2_pins: pinmux_uart2_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_INPUT, MUX_MODE6) /* lcd_data14.uart5_ctsn */ - AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT_PULLDOWN, MUX_MODE6) /* lcd_data15.uart5_rtsn */ - AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_INPUT_PULLUP, MUX_MODE4) /* lcd_data9.uart5_rxd */ - AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE4) /* lcd_data8.uart5_txd */ - >; - }; - - cpsw_default: cpsw_default { - pinctrl-single,pins = < - /* Slave 1 */ - AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE1) - AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE1) - AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE1) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE1) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE1) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE1) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE1) - AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0) - - /* Slave 2 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_crs_dv */ - AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_rxer */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* rmii2_txen */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* rmii2_td1 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* rmii2_td0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_rd1 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_rd0 */ - AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE1) /* rmii2_refclk */ - - >; - }; - - davinci_mdio_default: davinci_mdio_default { - pinctrl-single,pins = < - /* MDIO */ - AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) - >; - }; - - mmc0_pins_default: pinmux_mmc0_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_INPUT_PULLUP, MUX_MODE7) /* mcasp0_aclkx.gpio3_14 */ - AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT_PULLUP, MUX_MODE7) /* mcasp0_aclkx.gpio3_18 */ - >; - }; - - mmc2_pins_default: pinmux_mmc2_pins { - pinctrl-single,pins = < - /* eMMC */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad12.mmc2_dat0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad13.mmc2_dat1 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad14.mmc2_dat2 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad15.mmc2_dat3 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad8.mmc2_dat4 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad9.mmc2_dat5 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad10.mmc2_dat6 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad11.mmc2_dat7 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_csn3.mmc2_cmd */ - AM33XX_PADCONF(AM335X_PIN_GPMC_CLK, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_clk.mmc2_clk */ - >; - }; - - spi0_pins: pinmux_spi0 { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0) - >; - }; - -}; - -&uart0 { - /* Console */ - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; -}; - -&uart1 { - /* UART 1 setting */ - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; -}; - -&uart5 { - /* UART 2 setting */ - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - - status = "okay"; - clock-frequency = <400000>; - - tpm: tpm@20 { - compatible = "infineon,slb9645tt"; - reg = <0x20>; - }; - - tps: tps@2d { - compatible = "ti,tps65910"; - reg = <0x2d>; - }; - - eeprom: eeprom@50 { - compatible = "atmel,24c16"; - pagesize = <16>; - reg = <0x50>; - }; - - rtc_wdt: rtc_wdt@68 { - compatible = "dallas,ds1374"; - reg = <0x68>; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - - status = "okay"; - clock-frequency = <400000>; - gpio_xten: gpio_xten@27 { - compatible = "nxp,pca9535"; - gpio-controller; - #gpio-cells = <2>; - reg = <0x27>; - }; -}; - -&usb { - status = "okay"; -}; - -&usb_ctrl_mod { - status = "okay"; -}; - -&usb0_phy { - status = "okay"; -}; - -&usb1_phy { - status = "okay"; -}; - -&usb0 { - status = "okay"; - dr_mode = "host"; -}; - -&usb1 { - status = "okay"; - dr_mode = "host"; -}; - -&cppi41dma { - status = "okay"; -}; - -#include "tps65910.dtsi" - -&tps { - vcc1-supply = <&vbat>; - vcc2-supply = <&vbat>; - vcc3-supply = <&vbat>; - vcc4-supply = <&vbat>; - vcc5-supply = <&vbat>; - vcc6-supply = <&vbat>; - vcc7-supply = <&vbat>; - vccio-supply = <&vbat>; - - regulators { - vrtc_reg: regulator@0 { - regulator-always-on; - }; - - vio_reg: regulator@1 { - regulator-always-on; - }; - - vdd1_reg: regulator@2 { - /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ - regulator-name = "vdd_mpu"; - regulator-min-microvolt = <912500>; - regulator-max-microvolt = <1378000>; - regulator-boot-on; - regulator-always-on; - }; - - vdd2_reg: regulator@3 { - /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ - regulator-name = "vdd_core"; - regulator-min-microvolt = <912500>; - regulator-max-microvolt = <1150000>; - regulator-boot-on; - regulator-always-on; - }; - - vdd3_reg: regulator@4 { - regulator-always-on; - }; - - vdig1_reg: regulator@5 { - regulator-always-on; - }; - - vdig2_reg: regulator@6 { - regulator-always-on; - }; - - vpll_reg: regulator@7 { - regulator-always-on; - }; - - vdac_reg: regulator@8 { - regulator-always-on; - }; - - vaux1_reg: regulator@9 { - regulator-always-on; - }; - - vaux2_reg: regulator@10 { - regulator-always-on; - }; - - vaux33_reg: regulator@11 { - regulator-always-on; - }; - - vmmc_reg: regulator@12 { - compatible = "regulator-fixed"; - regulator-name = "vmmc_reg"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; -}; - -/* Power */ -&vbat { - regulator-name = "vbat"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; -}; - -&mac { - pinctrl-names = "default"; - pinctrl-0 = <&cpsw_default>; - dual_emac = <1>; - status = "okay"; -}; - -&davinci_mdio { - pinctrl-names = "default"; - pinctrl-0 = <&davinci_mdio_default>; - status = "okay"; - - ethphy0: ethernet-phy@4 { - reg = <4>; - }; - - ethphy1: ethernet-phy@5 { - reg = <5>; - }; -}; - -&cpsw_emac0 { - status = "okay"; - phy-handle = <ðphy0>; - phy-mode = "rmii"; - dual_emac_res_vlan = <1>; -}; - -&cpsw_emac1 { - status = "okay"; - phy-handle = <ðphy1>; - phy-mode = "rmii"; - dual_emac_res_vlan = <2>; -}; - -&sham { - status = "okay"; -}; - -&aes { - status = "okay"; -}; - -&gpio0 { - ti,no-reset-on-init; -}; - -&mmc1 { - pinctrl-names = "default"; - vmmc-supply = <&vmmcsd_fixed>; - bus-width = <4>; - pinctrl-0 = <&mmc0_pins_default>; - cd-gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; - wp-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&mmc3 { - dmas = <&edma_xbar 12 0 1 - &edma_xbar 13 0 2>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - vmmc-supply = <&vmmcsd_fixed>; - bus-width = <8>; - pinctrl-0 = <&mmc2_pins_default>; - ti,non-removable; - status = "okay"; -}; - -&buttons { - pinctrl-names = "default"; - pinctrl-0 = <&push_button_pins>; - #address-cells = <1>; - #size-cells = <0>; - - button@0 { - label = "push_button"; - linux,code = <0x100>; - gpios = <&gpio3 21 GPIO_ACTIVE_LOW>; - }; -}; - -/* SPI Busses */ -&spi0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins>; - - m25p80@0 { - compatible = "mx25l6405d"; - spi-max-frequency = <40000000>; - - reg = <0>; - spi-cpol; - spi-cpha; - #address-cells = <1>; - #size-cells = <1>; - - /* reg : The partition's offset and size within the mtd bank. */ - partitions@0 { - label = "MLO"; - reg = <0x0 0x80000>; - }; - - partitions@1 { - label = "U-Boot"; - reg = <0x80000 0x100000>; - }; - - partitions@2 { - label = "U-Boot Env"; - reg = <0x180000 0x20000>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/am335x-nano.dts b/sys/gnu/dts/arm/am335x-nano.dts deleted file mode 100644 index 0946fbf1b1f..00000000000 --- a/sys/gnu/dts/arm/am335x-nano.dts +++ /dev/null @@ -1,474 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2013 Newflow Ltd - http://www.newflow.co.uk/ - */ -/dts-v1/; - -#include "am33xx.dtsi" - -/ { - model = "Newflow AM335x NanoBone"; - compatible = "ti,am33xx"; - - cpus { - cpu@0 { - cpu0-supply = <&dcdc2_reg>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x10000000>; /* 256 MB */ - }; - - leds { - compatible = "gpio-leds"; - - led0 { - label = "nanobone:green:usr1"; - gpios = <&gpio1 5 0>; - default-state = "off"; - }; - }; -}; - -&am33xx_pinmux { - pinctrl-names = "default"; - pinctrl-0 = <&misc_pins>; - - misc_pins: misc_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_OUTPUT, MUX_MODE7) /* spi0_cs0.gpio0_5 */ - >; - }; - - gpmc_pins: gpmc_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLUP, MUX_MODE0) - - AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_OUTPUT, MUX_MODE0) - - AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0) - - AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE1) /* lcd_data1.gpmc_a1 */ - AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE1) /* lcd_data2.gpmc_a2 */ - AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE1) /* lcd_data3.gpmc_a3 */ - AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE1) /* lcd_data4.gpmc_a4 */ - AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE1) /* lcd_data5.gpmc_a5 */ - AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE1) /* lcd_data6.gpmc_a6 */ - AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE1) /* lcd_data7.gpmc_a7 */ - - AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE1) /* lcd_vsync.gpmc_a8 */ - AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE1) /* lcd_hsync.gpmc_a9 */ - AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE1) /* lcd_pclk.gpmc_a10 */ - >; - }; - - i2c0_pins: i2c0_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLDOWN, MUX_MODE0) - >; - }; - - uart0_pins: uart0_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT, MUX_MODE0) - >; - }; - - uart1_pins: uart1_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_OUTPUT, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT, MUX_MODE0) - >; - }; - - uart2_pins: uart2_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_INPUT_PULLUP, MUX_MODE7) /* lcd_data8.gpio2[14] */ - AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE7) /* lcd_data9.gpio2[15] */ - AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE1) /* spi0_sclk.uart2_rxd */ - AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT, MUX_MODE1) /* spi0_d0.uart2_txd */ - >; - }; - - uart3_pins: uart3_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_INPUT_PULLUP, MUX_MODE6) /* lcd_data10.uart3_ctsn */ - AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE6) /* lcd_data11.uart3_rtsn */ - AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE1) /* spi0_cs1.uart3_rxd */ - AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, PIN_OUTPUT, MUX_MODE1) /* ecap0_in_pwm0_out.uart3_txd */ - >; - }; - - uart4_pins: uart4_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_INPUT_PULLUP, MUX_MODE6) /* lcd_data12.uart4_ctsn */ - AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE6) /* lcd_data13.uart4_rtsn */ - AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT, MUX_MODE1) /* uart0_ctsn.uart4_rxd */ - AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_OUTPUT, MUX_MODE1) /* uart0_rtsn.uart4_txd */ - >; - }; - - uart5_pins: uart5_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_INPUT, MUX_MODE4) /* lcd_data14.uart5_rxd */ - AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_OUTPUT, MUX_MODE3) /* rmiii1_refclk.uart5_txd */ - >; - }; - - mmc1_pins: mmc1_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) /* mmc0_clk.mmc0_clk */ - AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) /* mmc0_cmd.mmc0_cmd */ - AM33XX_PADCONF(AM335X_PIN_EMU1, PIN_INPUT_PULLUP, MUX_MODE7) /* emu1.gpio3[8] */ - AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT_PULLUP, MUX_MODE7) /* mcasp0_aclkr.gpio3[18] */ - >; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; - status = "okay"; - rts-gpio = <&gpio0 13 GPIO_ACTIVE_HIGH>; - rs485-rts-active-high; - rs485-rx-during-tx; - rs485-rts-delay = <1 1>; - linux,rs485-enabled-at-boot-time; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; - status = "okay"; - rts-gpio = <&gpio2 15 GPIO_ACTIVE_HIGH>; - rs485-rts-active-high; - rs485-rts-delay = <1 1>; - linux,rs485-enabled-at-boot-time; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&uart4_pins>; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&uart5_pins>; - status = "okay"; -}; - -&i2c0 { - status = "okay"; - pinctrl-names = "default"; - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - - gpio@20 { - compatible = "microchip,mcp23017"; - gpio-controller; - #gpio-cells = <2>; - reg = <0x20>; - }; - - tps: tps@24 { - reg = <0x24>; - }; - - eeprom@53 { - compatible = "microchip,24c02", "atmel,24c02"; - reg = <0x53>; - pagesize = <8>; - }; - - rtc@68 { - compatible = "dallas,ds1307"; - reg = <0x68>; - }; -}; - -&elm { - status = "okay"; -}; - -&gpmc { - compatible = "ti,am3352-gpmc"; - ti,hwmods = "gpmc"; - status = "okay"; - gpmc,num-waitpins = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&gpmc_pins>; - - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0x08000000 0x08000000>, /* CS0: NOR 128M */ - <1 0 0x1c000000 0x01000000>; /* CS1: FRAM 16M */ - - nor@0,0 { - reg = <0 0x00000000 0x08000000>; - compatible = "cfi-flash"; - linux,mtd-name = "spansion,s29gl010p11t"; - bank-width = <2>; - - gpmc,mux-add-data = <2>; - - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <160>; - gpmc,cs-wr-off-ns = <160>; - gpmc,adv-on-ns = <10>; - gpmc,adv-rd-off-ns = <30>; - gpmc,adv-wr-off-ns = <30>; - gpmc,oe-on-ns = <40>; - gpmc,oe-off-ns = <160>; - gpmc,we-on-ns = <40>; - gpmc,we-off-ns = <160>; - gpmc,rd-cycle-ns = <160>; - gpmc,wr-cycle-ns = <160>; - gpmc,access-ns = <150>; - gpmc,page-burst-access-ns = <10>; - gpmc,cycle2cycle-samecsen; - gpmc,cycle2cycle-delay-ns = <20>; - gpmc,wr-data-mux-bus-ns = <70>; - gpmc,wr-access-ns = <80>; - - #address-cells = <1>; - #size-cells = <1>; - - /* - MTD partition table - =================== - +------------+-->0x00000000-> U-Boot start - | | - | |-->0x000BFFFF-> U-Boot end - | |-->0x000C0000-> ENV1 start - | | - | |-->0x000DFFFF-> ENV1 end - | |-->0x000E0000-> ENV2 start - | | - | |-->0x000FFFFF-> ENV2 end - | |-->0x00100000-> Kernel start - | | - | |-->0x004FFFFF-> Kernel end - | |-->0x00500000-> File system start - | | - | |-->0x01FFFFFF-> File system end - | |-->0x02000000-> User data start - | | - | |-->0x03FFFFFF-> User data end - | |-->0x04000000-> Data storage start - | | - +------------+-->0x08000000-> NOR end (Free end) - */ - partition@0 { - label = "boot"; - reg = <0x00000000 0x000c0000>; /* 768KB */ - }; - - partition@1 { - label = "env1"; - reg = <0x000c0000 0x00020000>; /* 128KB */ - }; - - partition@2 { - label = "env2"; - reg = <0x000e0000 0x00020000>; /* 128KB */ - }; - - partition@3 { - label = "kernel"; - reg = <0x00100000 0x00400000>; /* 4MB */ - }; - - partition@4 { - label = "rootfs"; - reg = <0x00500000 0x01b00000>; /* 27MB */ - }; - - partition@5 { - label = "user"; - reg = <0x02000000 0x02000000>; /* 32MB */ - }; - - partition@6 { - label = "data"; - reg = <0x04000000 0x04000000>; /* 64MB */ - }; - }; - - fram@1,0 { - reg = <1 0x00000000 0x01000000>; - bank-width = <2>; - - gpmc,mux-add-data = <2>; - - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <160>; - gpmc,cs-wr-off-ns = <160>; - gpmc,adv-on-ns = <10>; - gpmc,adv-rd-off-ns = <20>; - gpmc,adv-wr-off-ns = <20>; - gpmc,oe-on-ns = <30>; - gpmc,oe-off-ns = <150>; - gpmc,we-on-ns = <30>; - gpmc,we-off-ns = <150>; - gpmc,rd-cycle-ns = <160>; - gpmc,wr-cycle-ns = <160>; - gpmc,access-ns = <130>; - gpmc,page-burst-access-ns = <10>; - gpmc,cycle2cycle-samecsen; - gpmc,cycle2cycle-diffcsen; - gpmc,cycle2cycle-delay-ns = <10>; - gpmc,wr-data-mux-bus-ns = <30>; - gpmc,wr-access-ns = <0>; - }; -}; - -&mac { - dual_emac; - status = "okay"; -}; - -&davinci_mdio { - status = "okay"; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; - - ethphy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&cpsw_emac0 { - phy-handle = <ðphy0>; - phy-mode = "mii"; - dual_emac_res_vlan = <1>; -}; - -&cpsw_emac1 { - phy-handle = <ðphy1>; - phy-mode = "mii"; - dual_emac_res_vlan = <2>; -}; - -&mmc1 { - status = "okay"; - vmmc-supply = <&ldo4_reg>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - bus-width = <4>; - cd-gpios = <&gpio3 8 0>; - wp-gpios = <&gpio3 18 0>; -}; - -#include "tps65217.dtsi" - -&tps { - regulators { - dcdc1_reg: regulator@0 { - /* +1.5V voltage with ±4% tolerance */ - regulator-min-microvolt = <1450000>; - regulator-max-microvolt = <1550000>; - regulator-boot-on; - regulator-always-on; - }; - - dcdc2_reg: regulator@1 { - /* VDD_MPU voltage limits 0.95V - 1.1V with ±4% tolerance */ - regulator-name = "vdd_mpu"; - regulator-min-microvolt = <915000>; - regulator-max-microvolt = <1140000>; - regulator-boot-on; - regulator-always-on; - }; - - dcdc3_reg: regulator@2 { - /* VDD_CORE voltage limits 0.95V - 1.1V with ±4% tolerance */ - regulator-name = "vdd_core"; - regulator-min-microvolt = <915000>; - regulator-max-microvolt = <1140000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1_reg: regulator@3 { - /* +1.8V voltage with ±4% tolerance */ - regulator-min-microvolt = <1750000>; - regulator-max-microvolt = <1870000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo2_reg: regulator@4 { - /* +3.3V voltage with ±4% tolerance */ - regulator-min-microvolt = <3175000>; - regulator-max-microvolt = <3430000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo3_reg: regulator@5 { - /* +1.8V voltage with ±4% tolerance */ - regulator-min-microvolt = <1750000>; - regulator-max-microvolt = <1870000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo4_reg: regulator@6 { - /* +3.3V voltage with ±4% tolerance */ - regulator-min-microvolt = <3175000>; - regulator-max-microvolt = <3430000>; - regulator-boot-on; - regulator-always-on; - }; - }; -}; diff --git a/sys/gnu/dts/arm/am335x-netcan-plus-1xx.dts b/sys/gnu/dts/arm/am335x-netcan-plus-1xx.dts deleted file mode 100644 index e69de29bb2d..00000000000 diff --git a/sys/gnu/dts/arm/am335x-netcom-plus-2xx.dts b/sys/gnu/dts/arm/am335x-netcom-plus-2xx.dts deleted file mode 100644 index e69de29bb2d..00000000000 diff --git a/sys/gnu/dts/arm/am335x-netcom-plus-8xx.dts b/sys/gnu/dts/arm/am335x-netcom-plus-8xx.dts deleted file mode 100644 index e69de29bb2d..00000000000 diff --git a/sys/gnu/dts/arm/am335x-osd3358-sm-red.dts b/sys/gnu/dts/arm/am335x-osd3358-sm-red.dts deleted file mode 100644 index f47cc9fea25..00000000000 --- a/sys/gnu/dts/arm/am335x-osd3358-sm-red.dts +++ /dev/null @@ -1,461 +0,0 @@ -//SPDX-License-Identifier: GPL-2.0 -/* Copyright (C) 2018 Octavo Systems LLC - http://www.octavosystems.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/dts-v1/; - -#include "am33xx.dtsi" -#include "am335x-osd335x-common.dtsi" -#include - -#include - -/ { - model = "Octavo Systems OSD3358-SM-RED"; - compatible = "oct,osd3358-sm-refdesign", "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx"; -}; - -&ldo3_reg { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; -}; - -&mmc1 { - vmmc-supply = <&vmmcsd_fixed>; -}; - -&mmc2 { - vmmc-supply = <&vmmcsd_fixed>; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_pins>; - bus-width = <8>; - status = "okay"; -}; - -&am33xx_pinmux { - nxp_hdmi_bonelt_pins: nxp-hdmi-bonelt-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT_PULLDOWN, MUX_MODE3) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - >; - }; - - nxp_hdmi_bonelt_off_pins: nxp-hdmi-bonelt-off-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT_PULLDOWN, MUX_MODE3) - >; - }; - - mcasp0_pins: mcasp0-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mcasp0_ahclkr.mcasp0_axr2*/ - AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_OUTPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a11.GPIO1_27 */ - >; - }; - - flash_enable: flash-enable { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* rmii1_ref_clk.gpio0_29 */ - >; - }; - - imu_interrupt: imu-interrupt { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) /* mii1_rx_er.gpio3_2 */ - >; - }; - - ethernet_interrupt: ethernet-interrupt{ - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE7) /* mii1_col.gpio3_0 */ - >; - }; -}; - -&lcdc { - status = "okay"; - - /* If you want to get 24 bit RGB and 16 BGR mode instead of - * current 16 bit RGB and 24 BGR modes, set the propety - * below to "crossed" and uncomment the video-ports -property - * in tda19988 node. - * AM335x errata for wiring: - * http://www.ti.com/lit/er/sprz360i/sprz360i.pdf - */ - - blue-and-red-wiring = "straight"; - - port { - lcdc_0: endpoint { - remote-endpoint = <&hdmi_0>; - }; - }; -}; - -&i2c0 { - tda19988: hdmi-encoder@70 { - compatible = "nxp,tda998x"; - reg = <0x70>; - - pinctrl-names = "default", "off"; - pinctrl-0 = <&nxp_hdmi_bonelt_pins>; - pinctrl-1 = <&nxp_hdmi_bonelt_off_pins>; - - /* Convert 24bit BGR to RGB, e.g. cross red and blue wiring */ - /* video-ports = <0x234501>; */ - - #sound-dai-cells = <0>; - audio-ports = < TDA998x_I2S 0x03>; - - port { - hdmi_0: endpoint { - remote-endpoint = <&lcdc_0>; - }; - }; - }; - - mpu9250: imu@68 { - compatible = "invensense,mpu6050"; - reg = <0x68>; - interrupt-parent = <&gpio3>; - interrupts = <21 IRQ_TYPE_EDGE_RISING>; - i2c-gate { - #address-cells = <1>; - #size-cells = <0>; - ax8975@c { - compatible = "ak,ak8975"; - reg = <0x0c>; - }; - }; - /*invensense,int_config = <0x10>; - invensense,level_shifter = <0>; - invensense,orientation = [01 00 00 00 01 00 00 00 01]; - invensense,sec_slave_type = <0>; - invensense,key = [4e cc 7e eb f6 1e 35 22 00 34 0d 65 32 e9 94 89];*/ - }; - - bmp280: pressure@76 { - compatible = "bosch,bmp280"; - reg = <0x76>; - }; -}; - -&rtc { - system-power-controller; -}; - -&mcasp0 { - #sound-dai-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&mcasp0_pins>; - status = "okay"; - op-mode = <0>; /* MCASP_IIS_MODE */ - tdm-slots = <2>; - serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ - 0 0 1 0 - >; - tx-num-evt = <32>; - rx-num-evt = <32>; -}; - -/ { - clk_mcasp0_fixed: clk-mcasp0-fixed { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24576000>; - }; - - clk_mcasp0: clk-mcasp0 { - #clock-cells = <0>; - compatible = "gpio-gate-clock"; - clocks = <&clk_mcasp0_fixed>; - enable-gpios = <&gpio1 27 0>; /* BeagleBone Black Clk enable on GPIO1_27 */ - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "TI BeagleBone Black"; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&dailink0_master>; - simple-audio-card,frame-master = <&dailink0_master>; - - dailink0_master: simple-audio-card,cpu { - sound-dai = <&mcasp0>; - clocks = <&clk_mcasp0>; - }; - - simple-audio-card,codec { - sound-dai = <&tda19988>; - }; - }; - - chosen { - stdout-path = &uart0; - }; - - leds { - pinctrl-names = "default"; - pinctrl-0 = <&user_leds_s0>; - - compatible = "gpio-leds"; - - led2 { - label = "beaglebone:green:usr0"; - gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - - led3 { - label = "beaglebone:green:usr1"; - gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc0"; - default-state = "off"; - }; - - led4 { - label = "beaglebone:green:usr2"; - gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "cpu0"; - default-state = "off"; - }; - - led5 { - label = "beaglebone:green:usr3"; - gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc1"; - default-state = "off"; - }; - }; - - vmmcsd_fixed: fixedregulator0 { - compatible = "regulator-fixed"; - regulator-name = "vmmcsd_fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&am33xx_pinmux { - pinctrl-names = "default"; - pinctrl-0 = <&clkout2_pin>; - - user_leds_s0: user-leds-s0 { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a5.gpio1_21 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_a6.gpio1_22 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a7.gpio1_23 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_a8.gpio1_24 */ - >; - }; - - i2c2_pins: pinmux-i2c2-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart1_ctsn.i2c2_sda */ - AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart1_rtsn.i2c2_scl */ - >; - }; - - uart0_pins: pinmux-uart0-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - >; - }; - - clkout2_pin: pinmux-clkout2-pin { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* xdma_event_intr1.clkout2 */ - >; - }; - - cpsw_default: cpsw-default { - pinctrl-single,pins = < - /* Slave 1 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txen.rgmii1_tctl */ - AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE2) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) - AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE2) - AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE2) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE2) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE2) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE2) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE2) - >; - }; - - cpsw_sleep: cpsw-sleep { - pinctrl-single,pins = < - /* Slave 1 reset value */ - AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) - >; - }; - - davinci_mdio_default: davinci-mdio-default { - pinctrl-single,pins = < - /* MDIO */ - AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) - >; - }; - - davinci_mdio_sleep: davinci-mdio-sleep { - pinctrl-single,pins = < - /* MDIO reset value */ - AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) - >; - }; - - mmc1_pins: pinmux-mmc1-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7) /* (C15) spi0_cs1.gpio0[6] */ - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) - >; - }; - - emmc_pins: pinmux-emmc-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */ - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ - >; - }; -}; - - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - - status = "okay"; -}; - -&usb { - status = "okay"; -}; - -&usb_ctrl_mod { - status = "okay"; -}; - -&usb0_phy { - status = "okay"; -}; - -&usb1_phy { - status = "okay"; -}; - -&usb0 { - status = "okay"; - dr_mode = "peripheral"; - interrupts-extended = <&intc 18 &tps 0>; - interrupt-names = "mc", "vbus"; -}; - -&usb1 { - status = "okay"; - dr_mode = "host"; -}; - -&cppi41dma { - status = "okay"; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - status = "okay"; - clock-frequency = <100000>; -}; - -&cpsw_emac0 { - phy-handle = <ðphy0>; - phy-mode = "rgmii-txid"; -}; - -&mac { - slaves = <1>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&cpsw_default>; - pinctrl-1 = <&cpsw_sleep>; - status = "okay"; -}; - -&davinci_mdio { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&davinci_mdio_default>; - pinctrl-1 = <&davinci_mdio_sleep>; - status = "okay"; - - ethphy0: ethernet-phy@4 { - reg = <4>; - }; -}; - -&mmc1 { - status = "okay"; - bus-width = <0x4>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; -}; - -&rtc { - clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; - clock-names = "ext-clk", "int-clk"; -}; diff --git a/sys/gnu/dts/arm/am335x-osd335x-common.dtsi b/sys/gnu/dts/arm/am335x-osd335x-common.dtsi deleted file mode 100644 index a8b6842489f..00000000000 --- a/sys/gnu/dts/arm/am335x-osd335x-common.dtsi +++ /dev/null @@ -1,124 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ - * - * Author: Robert Nelson - */ - -/ { - cpus { - cpu@0 { - cpu0-supply = <&dcdc2_reg>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000>; /* 512 MB */ - }; -}; - -&cpu0_opp_table { - /* - * Octavo Systems: - * The EFUSE_SMA register is not programmed for any of the AM335x wafers - * we get and we are not programming them during our production test. - * Therefore, from a DEVICE_ID revision point of view, the silicon looks - * like it is Revision 2.1. However, from an EFUSE_SMA point of view for - * the HW OPP table, the silicon looks like it is Revision 1.0 (ie the - * EFUSE_SMA register reads as all zeros). - */ - oppnitro-1000000000 { - opp-supported-hw = <0x06 0x0100>; - }; -}; - -&am33xx_pinmux { - i2c0_pins: pinmux-i2c0-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) - >; - }; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - - status = "okay"; - clock-frequency = <400000>; - - tps: tps@24 { - reg = <0x24>; - }; -}; - -/include/ "tps65217.dtsi" - -&tps { - interrupts = <7>; /* NMI */ - interrupt-parent = <&intc>; - - ti,pmic-shutdown-controller; - - pwrbutton { - interrupts = <2>; - status = "okay"; - }; - - regulators { - dcdc1_reg: regulator@0 { - regulator-name = "vdds_dpr"; - regulator-always-on; - }; - - dcdc2_reg: regulator@1 { - /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ - regulator-name = "vdd_mpu"; - regulator-min-microvolt = <925000>; - regulator-max-microvolt = <1351500>; - regulator-boot-on; - regulator-always-on; - }; - - dcdc3_reg: regulator@2 { - /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ - regulator-name = "vdd_core"; - regulator-min-microvolt = <925000>; - regulator-max-microvolt = <1150000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1_reg: regulator@3 { - regulator-name = "vio,vrtc,vdds"; - regulator-always-on; - }; - - ldo2_reg: regulator@4 { - regulator-name = "vdd_3v3aux"; - regulator-always-on; - }; - - ldo3_reg: regulator@5 { - regulator-name = "vdd_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo4_reg: regulator@6 { - regulator-name = "vdd_3v3a"; - regulator-always-on; - }; - }; -}; - -&aes { - status = "okay"; -}; - -&sham { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/am335x-pcm-953.dtsi b/sys/gnu/dts/arm/am335x-pcm-953.dtsi deleted file mode 100644 index 9bfa032bcad..00000000000 --- a/sys/gnu/dts/arm/am335x-pcm-953.dtsi +++ /dev/null @@ -1,267 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014-2017 Phytec Messtechnik GmbH - * Author: Wadim Egorov - * Teresa Remmet - */ - -#include - -/ { - model = "Phytec AM335x PCM-953"; - compatible = "phytec,am335x-pcm-953", "phytec,am335x-phycore-som", "ti,am33xx"; - - /* Power */ - regulators { - vcc3v3: fixedregulator@1 { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; - - vcc1v8: fixedregulator@2 { - compatible = "regulator-fixed"; - regulator-name = "vcc1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - }; - }; - - /* User IO */ - user_leds: user_leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&user_leds_pins>; - - user-led0 { - gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "gpio"; - default-state = "on"; - }; - - user-led1 { - gpios = <&gpio1 31 GPIO_ACTIVE_LOW>; - linux,default-trigger = "gpio"; - default-state = "on"; - }; - }; - - user_buttons: user_buttons { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&user_buttons_pins>; - - button@0 { - label = "home"; - linux,code = ; - gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>; - wakeup-source; - }; - - button@1 { - label = "menu"; - linux,code = ; - gpios = <&gpio3 8 GPIO_ACTIVE_HIGH>; - wakeup-source; - }; - - }; -}; - -&am33xx_pinmux { - user_buttons_pins: pinmux_user_buttons { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_EMU0, PIN_INPUT_PULLDOWN, MUX_MODE7) /* emu0.gpio3_7 */ - AM33XX_PADCONF(AM335X_PIN_EMU1, PIN_INPUT_PULLDOWN, MUX_MODE7) /* emu1.gpio3_8 */ - >; - }; - - user_leds_pins: pinmux_user_leds { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_csn1.gpio1_30 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_csn2.gpio1_31 */ - >; - }; -}; - -/* CAN */ -&am33xx_pinmux { - dcan1_pins: pinmux_dcan1 { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_OUTPUT_PULLUP, MUX_MODE2) /* uart1_rxd.dcan1_tx_mux2 */ - AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_INPUT_PULLUP, MUX_MODE2) /* uart1_txd.dcan1_rx_mux2 */ - >; - }; -}; - -&dcan1 { - pinctrl-names = "default"; - pinctrl-0 = <&dcan1_pins>; - status = "okay"; -}; - -/* Ethernet */ -&am33xx_pinmux { - ethernet1_pins: pinmux_ethernet1 { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a0.rgmii2_tctl */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a1.rgmii2_rctl */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a2.rgmii2_td3 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a3.rgmii2_td2 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a4.rgmii2_td1 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a5.rgmii2_td0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a6.rgmii2_tclk */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a7.rgmii2_rclk */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */ - >; - }; -}; - -&cpsw_emac1 { - phy-handle = <&phy1>; - phy-mode = "rgmii-id"; - dual_emac_res_vlan = <2>; - status = "okay"; -}; - -&davinci_mdio { - phy1: ethernet-phy@2 { - reg = <2>; - }; -}; - -&mac { - slaves = <2>; - pinctrl-names = "default"; - pinctrl-0 = <ðernet0_pins ðernet1_pins>; - dual_emac; -}; - -/* Misc */ -&am33xx_pinmux { - pinctrl-names = "default"; - pinctrl-0 = <&cb_gpio_pins>; - - cb_gpio_pins: pinmux_cb_gpio { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* uart0_ctsn.gpio1_8 */ - AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* uart0_rtsn.gpio1_9 */ - >; - }; -}; - -/* MMC */ -&am33xx_pinmux { - mmc1_pins: pinmux_mmc1_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT_PULLUP, MUX_MODE7) /* spi0_cs1.mmc0_sdcd */ - >; - }; -}; - -&mmc1 { - vmmc-supply = <&vcc3v3>; - bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -/* UARTs */ -&am33xx_pinmux { - uart0_pins: pinmux_uart0 { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - >; - }; - - uart1_pins: pinmux_uart1 { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - >; - }; - - uart2_pins: pinmux_uart2 { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLUP, MUX_MODE1) /* mii1_tx_clk.uart2_rxd */ - AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_rx_clk.uart2_txd */ - >; - }; - - uart3_pins: pinmux_uart3 { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE1) /* mii1_rxd3.uart3_rxd */ - AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_rxd2.uart3_txd */ - >; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; - status = "okay"; -}; - -/* USB */ -&cppi41dma { - status = "okay"; -}; - -&usb_ctrl_mod { - status = "okay"; -}; - -&usb { - status = "okay"; -}; - -&usb0 { - status = "okay"; -}; - -&usb0_phy { - status = "okay"; -}; - -&usb1 { - status = "okay"; - dr_mode = "host"; -}; - -&usb1_phy { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/am335x-pdu001.dts b/sys/gnu/dts/arm/am335x-pdu001.dts deleted file mode 100644 index 3141255f72c..00000000000 --- a/sys/gnu/dts/arm/am335x-pdu001.dts +++ /dev/null @@ -1,603 +0,0 @@ -/* - * pdu001.dts - * - * EETS GmbH PDU001 board device tree file - * - * Copyright (C) 2018 EETS GmbH - http://www.eets.ch/ - * - * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/dts-v1/; - -#include "am33xx.dtsi" -#include -#include - -/ { - model = "EETS,PDU001"; - compatible = "ti,am33xx"; - - chosen { - stdout-path = &uart3; - }; - - cpus { - cpu@0 { - cpu0-supply = <&vdd1_reg>; - }; - }; - - memory { - device_type = "memory"; - reg = <0x80000000 0x10000000>; /* 256 MB */ - }; - - vbat: fixedregulator@0 { - compatible = "regulator-fixed"; - regulator-name = "vbat"; - regulator-min-microvolt = <3600000>; - regulator-max-microvolt = <3600000>; - regulator-boot-on; - }; - - lis3_reg: fixedregulator@1 { - compatible = "regulator-fixed"; - regulator-name = "lis3_reg"; - regulator-boot-on; - }; - - panel { - compatible = "ti,tilcdc,panel"; - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&lcd_pins_s0>; - panel-info { - ac-bias = <255>; - ac-bias-intrpt = <0>; - dma-burst-sz = <16>; - bpp = <16>; - fdd = <0x80>; - sync-edge = <0>; - sync-ctrl = <1>; - raster-order = <0>; - fifo-th = <0>; - }; - - display-timings { - 240x320p16 { - clock-frequency = <6500000>; - hactive = <240>; - vactive = <320>; - hfront-porch = <6>; - hback-porch = <6>; - hsync-len = <1>; - vback-porch = <6>; - vfront-porch = <6>; - vsync-len = <1>; - hsync-active = <0>; - vsync-active = <0>; - pixelclk-active = <1>; - de-active = <0>; - }; - }; - }; -}; - -&am33xx_pinmux { - pinctrl-names = "default"; - pinctrl-0 = <&clkout2_pin>; - - i2c0_pins: pinmux_i2c0_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) - >; - }; - - i2c1_pins: pinmux_i2c1_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE2) /* spi0_d1.i2c1_sda */ - AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE2) /* spi0_cs0.i2c1_scl */ - >; - }; - - i2c2_pins: pinmux_i2c2_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE2) /* spi0_clk.i2c2_sda */ - AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLUP, MUX_MODE2) /* spi0_d0.i2c2_scl */ - >; - }; - - spi1_pins: pinmux_spi1_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_OUTPUT, MUX_MODE3) /* mcasp0_aclkx.spi1_sclk */ - AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_OUTPUT, MUX_MODE3) /* mcasp0_fsx.spi1_d0 */ - AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR0, PIN_INPUT_PULLDOWN, MUX_MODE3) /* mcasp0_axr0.spi1_d1 */ - AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_OUTPUT, MUX_MODE3) /* mcasp0_ahclkr.spi1_cs0 */ - >; - }; - - uart0_pins: pinmux_uart0_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_OUTPUT, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - >; - }; - - uart1_pins: pinmux_uart1_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - >; - }; - - uart3_pins: pinmux_uart3_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT_PULLUP, MUX_MODE1) /* spi0_cs1.uart3_rxd */ - AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* ecap0_in_pwm0_out.uart3_txd */ - >; - }; - - clkout2_pin: pinmux_clkout2_pin { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* xdma_event_intr1.clkout2 */ - >; - }; - - cpsw_default: cpsw_default { - pinctrl-single,pins = < - /* Port 1 (emac0) */ - AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT, MUX_MODE0) - - /* Port 2 (emac1) */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT, MUX_MODE1) /* mii2_txen.gpmc_a0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT, MUX_MODE1) /* mii2_rxdv.gpmc_a1 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT, MUX_MODE1) /* mii2_txd3.gpmc_a2 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT, MUX_MODE1) /* mii2_txd2.gpmc_a3 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT, MUX_MODE1) /* mii2_txd1.gpmc_a4 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE1) /* mii2_txd0.gpmc_a5 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT, MUX_MODE1) /* mii2_txclk.gpmc_a6 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT, MUX_MODE1) /* mii2_rxclk.gpmc_a7 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT, MUX_MODE1) /* mii2_rxd3.gpmc_a8 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT, MUX_MODE1) /* mii2_rxd2.gpmc_a9 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT, MUX_MODE1) /* mii2_rxd1.gpmc_a10 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT, MUX_MODE1) /* mii2_rxd0.gpmc_a11 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT, MUX_MODE1) /* mii2_crs.gpmc_wait0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT, MUX_MODE1) /* mii2_rxer.gpmc_wpn */ - AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT, MUX_MODE1) /* mii2_col.gpmc_ben1 */ - >; - }; - - davinci_mdio_default: davinci_mdio_default { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) - >; - }; - - mmc1_pins: pinmux_mmc1_pins { - /* eMMC */ - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) - >; - }; - - mmc2_pins: pinmux_mmc2_pins { - /* SD cardcage */ - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */ - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ - /* card change signal for frontpanel SD cardcage */ - AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_INPUT, MUX_MODE7) /* gpmc_advn_ale.gpio2_2 */ - >; - }; - - lcd_pins_s0: lcd_pins_s0 { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0) - >; - }; - - dcan0_pins: pinmux_dcan0_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_OUTPUT, MUX_MODE2) /* uart1_ctsn.d_can0_tx */ - AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLDOWN, MUX_MODE2) /* uart1_rtsn.d_can0_rx */ - >; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - - rts-gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; - rs485-rts-active-high; - rs485-rts-delay = <0 0>; - linux,rs485-enabled-at-boot-time; - - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; - - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; - - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - - status = "okay"; - clock-frequency = <400000>; - - tps: tps@2d { - reg = <0x2d>; - }; - - m2_eeprom: m2_eeprom@50 { - compatible = "atmel,24c256"; - reg = <0x50>; - status = "okay"; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - - status = "okay"; - clock-frequency = <100000>; - - board_24aa025e48: board_24aa025e48@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - }; - - backplane_24aa025e48: backplane_24aa025e48@53 { - compatible = "atmel,24c02"; - reg = <0x53>; - }; - - pca9532: pca9532@60 { - compatible = "nxp,pca9532"; - reg = <0x60>; - psc0 = <0x97>; - pwm0 = <0x80>; - psc1 = <0x97>; - pwm1 = <0x10>; - - run.red@0 { - type = ; - }; - run.green@1 { - type = ; - default-state = "on"; - }; - s2.red@2 { - type = ; - }; - s2.green@3 { - type = ; - }; - s1.yellow@4 { - type = ; - }; - s1.green@5 { - type = ; - }; - }; - - pca9530: pca9530@61 { - compatible = "nxp,pca9530"; - reg = <0x61>; - - tft-panel@0 { - type = ; - linux,default-trigger = "backlight"; - default-state = "on"; - }; - }; - - mcp79400: mcp79400@6f { - compatible = "microchip,mcp7940x"; - reg = <0x6f>; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - - status = "okay"; - clock-frequency = <100000>; -}; - -&spi1 { - pinctrl-names = "default"; - pinctrl-0 = <&spi1_pins>; - ti,pindir-d0-out-d1-in; - status = "okay"; - - display-controller@0 { - compatible = "orisetech,otm3225a"; - reg = <0>; - spi-max-frequency = <1000000>; - // SPI mode 3 - spi-cpol; - spi-cpha; - status = "okay"; - }; -}; - -&usb { - status = "okay"; -}; - -&usb_ctrl_mod { - status = "okay"; -}; - -&usb0_phy { - status = "okay"; -}; - -&usb1_phy { - status = "okay"; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; - -&cppi41dma { - status = "okay"; -}; - -/* - * Disable soc's rtc as we have no VBAT for it. This makes the board - * rtc (Microchip MCP79400) the default rtc device 'rtc0'. - */ -&rtc { - status = "disabled"; -}; - -&lcdc { - status = "okay"; -}; - -&elm { - status = "okay"; -}; - -#include "tps65910.dtsi" - -&tps { - vcc1-supply = <&vbat>; - vcc2-supply = <&vbat>; - vcc3-supply = <&vbat>; - vcc4-supply = <&vbat>; - vcc5-supply = <&vbat>; - vcc6-supply = <&vbat>; - vcc7-supply = <&vbat>; - vccio-supply = <&vbat>; - - regulators { - vrtc_reg: regulator@0 { - regulator-name = "ldo_vrtc"; - regulator-always-on; - }; - - vio_reg: regulator@1 { - regulator-name = "buck_vdd_ddr"; - regulator-always-on; - }; - - vdd1_reg: regulator@2 { - /* VDD_MPU voltage limits */ - regulator-name = "buck_vdd_mpu"; - regulator-min-microvolt = <912500>; - regulator-max-microvolt = <1312500>; - regulator-boot-on; - regulator-always-on; - }; - - vdd2_reg: regulator@3 { - /* VDD_CORE voltage limits */ - regulator-name = "buck_vdd_core"; - regulator-min-microvolt = <912500>; - regulator-max-microvolt = <1150000>; - regulator-boot-on; - regulator-always-on; - }; - - vdd3_reg: regulator@4 { - regulator-name = "boost_res"; - regulator-always-on; - }; - - vdig1_reg: regulator@5 { - regulator-name = "ldo_vdig1"; - regulator-always-on; - }; - - vdig2_reg: regulator@6 { - regulator-name = "ldo_vdig2"; - regulator-always-on; - }; - - vpll_reg: regulator@7 { - regulator-name = "ldo_vpll"; - regulator-always-on; - }; - - vdac_reg: regulator@8 { - regulator-name = "ldo_vdac"; - regulator-always-on; - }; - - vaux1_reg: regulator@9 { - regulator-name = "ldo_vaux1"; - regulator-always-on; - }; - - vaux2_reg: regulator@10 { - regulator-name = "ldo_vaux2"; - regulator-always-on; - }; - - vaux33_reg: regulator@11 { - regulator-name = "ldo_vaux33"; - regulator-always-on; - }; - - vmmc_reg: regulator@12 { - regulator-name = "ldo_vmmc"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vbb_reg: regulator@13 { - regulator-name = "bat_vbb"; - }; - }; -}; - -&mac { - pinctrl-names = "default"; - pinctrl-0 = <&cpsw_default>; - dual_emac; /* no switch, two distinct MACs */ - status = "okay"; -}; - -&davinci_mdio { - pinctrl-names = "default"; - pinctrl-0 = <&davinci_mdio_default>; - status = "okay"; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; - - ethphy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&cpsw_emac0 { - phy-handle = <ðphy0>; - phy-mode = "mii"; - dual_emac_res_vlan = <1>; -}; - -&cpsw_emac1 { - phy-handle = <ðphy1>; - phy-mode = "mii"; - dual_emac_res_vlan = <2>; -}; - -&tscadc { - status = "okay"; - tsc { - ti,wires = <4>; - ti,x-plate-resistance = <200>; - ti,coordinate-readouts = <5>; - ti,wire-config = <0x01 0x10 0x22 0x33>; - ti,charge-delay = <0x400>; - }; - - adc { - ti,adc-channels = <4 5 6 7>; - }; -}; - -&mmc1 { - status = "okay"; - vmmc-supply = <&vmmc_reg>; - bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - non-removable; -}; - -&mmc2 { - status = "okay"; - vmmc-supply = <&vmmc_reg>; - bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; - cd-gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; -}; - -&sham { - status = "okay"; -}; - -&aes { - status = "okay"; -}; - -&dcan0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&dcan0_pins>; -}; diff --git a/sys/gnu/dts/arm/am335x-pepper.dts b/sys/gnu/dts/arm/am335x-pepper.dts deleted file mode 100644 index e7764ecdf65..00000000000 --- a/sys/gnu/dts/arm/am335x-pepper.dts +++ /dev/null @@ -1,661 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 Gumstix, Inc. - https://www.gumstix.com/ - */ -/dts-v1/; - -#include -#include "am33xx.dtsi" - -/ { - model = "Gumstix Pepper"; - compatible = "gumstix,am335x-pepper", "ti,am33xx"; - - cpus { - cpu@0 { - cpu0-supply = <&dcdc3_reg>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000>; /* 512 MB */ - }; - - buttons: user_buttons { - compatible = "gpio-keys"; - }; - - leds: user_leds { - compatible = "gpio-leds"; - }; - - panel: lcd_panel { - compatible = "ti,tilcdc,panel"; - }; - - sound: sound_iface { - compatible = "ti,da830-evm-audio"; - }; - - vbat: fixedregulator0 { - compatible = "regulator-fixed"; - }; - - v3v3c_reg: fixedregulator1 { - compatible = "regulator-fixed"; - }; - - vdd5_reg: fixedregulator2 { - compatible = "regulator-fixed"; - }; -}; - -/* I2C Busses */ -&i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - - clock-frequency = <400000>; - - tps: tps@24 { - reg = <0x24>; - }; - - eeprom: eeprom@50 { - compatible = "atmel,24c256"; - reg = <0x50>; - }; - - audio_codec: tlv320aic3106@1b { - compatible = "ti,tlv320aic3106"; - reg = <0x1b>; - ai3x-micbias-vg = <0x2>; - }; - - accel: lis331dlh@1d { - compatible = "st,lis3lv02d"; - reg = <0x1d>; - }; -}; - -&i2c1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - clock-frequency = <400000>; -}; - -&am33xx_pinmux { - i2c0_pins: pinmux_i2c0 { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) - >; - }; - i2c1_pins: pinmux_i2c1 { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLUP, MUX_MODE3) /* mii1_crs,i2c1_sda */ - AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE3) /* mii1_rxerr,i2c1_scl */ - >; - }; -}; - -/* Accelerometer */ -&accel { - pinctrl-names = "default"; - pinctrl-0 = <&accel_pins>; - - Vdd-supply = <&ldo3_reg>; - Vdd_IO-supply = <&ldo3_reg>; - st,irq1-click; - st,wakeup-x-lo; - st,wakeup-x-hi; - st,wakeup-y-lo; - st,wakeup-y-hi; - st,wakeup-z-lo; - st,wakeup-z-hi; - st,min-limit-x = <92>; - st,max-limit-x = <14>; - st,min-limit-y = <14>; - st,max-limit-y = <92>; - st,min-limit-z = <92>; - st,max-limit-z = <14>; -}; - -&am33xx_pinmux { - accel_pins: pinmux_accel { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_INPUT, MUX_MODE7) /* gpmc_wen.gpio2_4 */ - >; - }; -}; - -/* Audio */ -&audio_codec { - status = "okay"; - - reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; - AVDD-supply = <&ldo3_reg>; - IOVDD-supply = <&ldo3_reg>; - DRVDD-supply = <&ldo3_reg>; - DVDD-supply = <&dcdc1_reg>; -}; - -&sound { - ti,model = "AM335x-EVM"; - ti,audio-codec = <&audio_codec>; - ti,mcasp-controller = <&mcasp0>; - ti,codec-clock-rate = <12000000>; - ti,audio-routing = - "Headphone Jack", "HPLOUT", - "Headphone Jack", "HPROUT", - "MIC3L", "Mic3L Switch"; -}; - -&mcasp0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&audio_pins>; - - op-mode = <0>; /* MCASP_ISS_MODE */ - tdm-slots = <2>; - serial-dir = < - 1 2 0 0 - 0 0 0 0 - 0 0 0 0 - 0 0 0 0 - >; - tx-num-evt = <1>; - rx-num-evt = <1>; -}; - -&am33xx_pinmux { - audio_pins: pinmux_audio { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_INPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_INPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR0, PIN_INPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR1, PIN_INPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT, MUX_MODE7) /* gpmc_a0.gpio1_16 */ - >; - }; -}; - -/* Display: 24-bit LCD Screen */ -&panel { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&lcd_pins>; - panel-info { - ac-bias = <255>; - ac-bias-intrpt = <0>; - dma-burst-sz = <16>; - bpp = <32>; - fdd = <0x80>; - sync-edge = <0>; - sync-ctrl = <1>; - raster-order = <0>; - fifo-th = <0>; - }; - display-timings { - native-mode = <&timing0>; - timing0: 480x272 { - clock-frequency = <18400000>; - hactive = <480>; - vactive = <272>; - hfront-porch = <8>; - hback-porch = <4>; - hsync-len = <41>; - vfront-porch = <4>; - vback-porch = <2>; - vsync-len = <10>; - hsync-active = <1>; - vsync-active = <1>; - }; - }; -}; - -&lcdc { - status = "okay"; -}; - -&am33xx_pinmux { - lcd_pins: pinmux_lcd { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad8.lcd_data16 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad9.lcd_data17 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad10.lcd_data18 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad11.lcd_data19 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad12.lcd_data20 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad13.lcd_data21 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad14.lcd_data22 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad15.lcd_data23 */ - AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0) - /* Display Enable */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_a11.gpio1_27 */ - >; - }; -}; - -/* Ethernet */ -&cpsw_emac0 { - status = "okay"; - phy-handle = <ðphy0>; - phy-mode = "rgmii"; -}; - -&cpsw_emac1 { - status = "okay"; - phy-handle = <ðphy1>; - phy-mode = "rgmii"; -}; - -&davinci_mdio { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mdio_pins>; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; - - ethphy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&mac { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <ðernet_pins>; -}; - - -&am33xx_pinmux { - ethernet_pins: pinmux_ethernet { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txen.rgmii1_tctl */ - AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLUP, MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd3.rgmii1_td3 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd2.rgmii1_td2 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLUP, MUX_MODE2) - AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLUP, MUX_MODE2) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE2) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLUP, MUX_MODE2) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE2) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE2) - /* ethernet interrupt */ - AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLUP, MUX_MODE7) /* rmii2_refclk.gpio0_29 */ - /* ethernet PHY nReset */ - AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_OUTPUT_PULLUP, MUX_MODE7) /* mii1_col.gpio3_0 */ - >; - }; - - mdio_pins: pinmux_mdio { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) - >; - }; -}; - -/* MMC */ -&mmc1 { - /* Bootable SD card slot */ - status = "okay"; - vmmc-supply = <&ldo3_reg>; - bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&sd_pins>; - cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; -}; - -&mmc2 { - /* eMMC (not populated) on MMC #2 */ - status = "disabled"; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_pins>; - vmmc-supply = <&ldo3_reg>; - bus-width = <8>; - ti,non-removable; -}; - -&mmc3 { - /* Wifi & Bluetooth on MMC #3 */ - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&wireless_pins>; - vmmmc-supply = <&v3v3c_reg>; - bus-width = <4>; - ti,non-removable; - dmas = <&edma_xbar 12 0 1 - &edma_xbar 13 0 2>; - dma-names = "tx", "rx"; -}; - - -&am33xx_pinmux { - sd_pins: pinmux_sd_card { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7) /* spi0_cs1.gpio0_6 */ - >; - }; - emmc_pins: pinmux_emmc { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */ - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ - /* EMMC nReset */ - AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_wpn.gpio0_31 */ - >; - }; - wireless_pins: pinmux_wireless { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_a1.mmc2_dat0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_a2.mmc2_dat1 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_a3.mmc2_dat2 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ben1.mmc2_dat3 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_csn3.mmc2_cmd */ - AM33XX_PADCONF(AM335X_PIN_GPMC_CLK, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_clk.mmc1_clk */ - /* WLAN nReset */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_a8.gpio1_24 */ - /* WLAN nPower down */ - AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_wait0.gpio0_30 */ - /* 32kHz Clock */ - AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* xdma_event_intr1.clkout2 */ - >; - }; -}; - -/* Power */ -&vbat { - regulator-name = "vbat"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; -}; - -&v3v3c_reg { - regulator-name = "v3v3c_reg"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vbat>; -}; - -&vdd5_reg { - regulator-name = "vdd5_reg"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vbat>; -}; - -/include/ "tps65217.dtsi" - -&tps { - backlight { - isel = <1>; /* ISET1 */ - fdim = <200>; /* TPS65217_BL_FDIM_200HZ */ - default-brightness = <80>; - }; - - regulators { - dcdc1_reg: regulator@0 { - /* VDD_1V8 system supply */ - regulator-always-on; - }; - - dcdc2_reg: regulator@1 { - /* VDD_CORE voltage limits 0.95V - 1.26V with +/-4% tolerance */ - regulator-name = "vdd_core"; - regulator-min-microvolt = <925000>; - regulator-max-microvolt = <1150000>; - regulator-boot-on; - regulator-always-on; - }; - - dcdc3_reg: regulator@2 { - /* VDD_MPU voltage limits 0.95V - 1.1V with +/-4% tolerance */ - regulator-name = "vdd_mpu"; - regulator-min-microvolt = <925000>; - regulator-max-microvolt = <1325000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1_reg: regulator@3 { - /* VRTC 1.8V always-on supply */ - regulator-name = "vrtc,vdds"; - regulator-always-on; - }; - - ldo2_reg: regulator@4 { - /* 3.3V rail */ - regulator-name = "vdd_3v3aux"; - regulator-always-on; - }; - - ldo3_reg: regulator@5 { - /* VDD_3V3A 3.3V rail */ - regulator-name = "vdd_3v3a"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo4_reg: regulator@6 { - /* VDD_3V3B 3.3V rail */ - regulator-name = "vdd_3v3b"; - regulator-always-on; - }; - }; -}; - -/* SPI Busses */ -&spi0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins>; -}; - -&am33xx_pinmux { - spi0_pins: pinmux_spi0 { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0) - >; - }; -}; - -/* Touch Screen */ -&tscadc { - status = "okay"; - tsc { - ti,wires = <4>; - ti,x-plate-resistance = <200>; - ti,coordinate-readouts = <5>; - ti,wire-config = <0x00 0x11 0x22 0x33>; - }; - - adc { - ti,adc-channels = <4 5 6 7>; - }; -}; - -/* UARTs */ -&uart0 { - /* Serial Console */ - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; -}; - -&uart1 { - /* Broken out to J6 header */ - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; -}; - -&am33xx_pinmux { - uart0_pins: pinmux_uart0 { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - >; - }; - uart1_pins: pinmux_uart1 { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - >; - }; -}; - -/* USB */ -&usb { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&usb_pins>; -}; - -&usb_ctrl_mod { - status = "okay"; -}; - -&usb0_phy { - status = "okay"; -}; - -&usb1_phy { - status = "okay"; -}; - -&usb0 { - status = "okay"; - dr_mode = "host"; -}; - -&usb1 { - status = "okay"; - dr_mode = "host"; -}; - -&cppi41dma { - status = "okay"; -}; - -&am33xx_pinmux { - usb_pins: pinmux_usb { - pinctrl-single,pins = < - /* USB0 Over-Current (active low) */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT, MUX_MODE7) /* gpmc_a9.gpio1_25 */ - /* USB1 Over-Current (active low) */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT, MUX_MODE7) /* gpmc_a10.gpio1_26 */ - >; - }; -}; - -/* User IO */ -&leds { - pinctrl-names = "default"; - pinctrl-0 = <&user_leds_pins>; - - led0 { - label = "pepper:user0:blue"; - gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "none"; - default-state = "off"; - }; - - led1 { - label = "pepper:user1:red"; - gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "none"; - default-state = "off"; - }; -}; - -&buttons { - pinctrl-names = "default"; - pinctrl-0 = <&user_buttons_pins>; - #address-cells = <1>; - #size-cells = <0>; - - button0 { - label = "home"; - linux,code = ; - gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; - wakeup-source; - }; - - button1 { - label = "menu"; - linux,code = ; - gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; - wakeup-source; - }; - - buttons2 { - label = "power"; - linux,code = ; - gpios = <&gpio0 7 GPIO_ACTIVE_LOW>; - wakeup-source; - }; -}; - -&am33xx_pinmux { - user_leds_pins: pinmux_user_leds { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT, MUX_MODE7) /* gpmc_a4.gpio1_20 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE7) /* gpmc_a5.gpio1_21 */ - >; - }; - - user_buttons_pins: pinmux_user_buttons { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_a6.gpio1_22 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_a7.gpio1_21 */ - AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_a8.gpio0_7 */ - >; - }; -}; diff --git a/sys/gnu/dts/arm/am335x-phycore-rdk.dts b/sys/gnu/dts/arm/am335x-phycore-rdk.dts deleted file mode 100644 index 43907d03e67..00000000000 --- a/sys/gnu/dts/arm/am335x-phycore-rdk.dts +++ /dev/null @@ -1,28 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 PHYTEC Messtechnik GmbH - * Author: Wadim Egorov - */ - -/dts-v1/; - -#include "am335x-phycore-som.dtsi" -#include "am335x-pcm-953.dtsi" - -/* SoM */ -&gpmc { - status = "okay"; -}; - -&i2c_eeprom { - status = "okay"; -}; - -&i2c_rtc { - status = "okay"; -}; - -&serial_flash { - status = "okay"; - -}; diff --git a/sys/gnu/dts/arm/am335x-phycore-som.dtsi b/sys/gnu/dts/arm/am335x-phycore-som.dtsi deleted file mode 100644 index 3d0672b53d7..00000000000 --- a/sys/gnu/dts/arm/am335x-phycore-som.dtsi +++ /dev/null @@ -1,341 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2015 Phytec Messtechnik GmbH - * Author: Teresa Remmet - */ - -#include "am33xx.dtsi" -#include - -/ { - model = "Phytec AM335x phyCORE"; - compatible = "phytec,am335x-phycore-som", "ti,am33xx"; - - aliases { - rtc0 = &i2c_rtc; - rtc1 = &rtc; - }; - - cpus { - cpu@0 { - cpu0-supply = <&vdd1_reg>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x10000000>; /* 256 MB */ - }; - - vcc5v: fixedregulator0 { - compatible = "regulator-fixed"; - regulator-name = "vcc5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - regulator-always-on; - }; -}; - -/* Crypto Module */ -&aes { - status = "okay"; -}; - -&sham { - status = "okay"; -}; - -/* EMMC */ -&am33xx_pinmux { - emmc_pins: pinmux_emmc_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */ - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ - >; - }; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&emmc_pins>; - vmmc-supply = <&vmmc_reg>; - bus-width = <8>; - ti,non-removable; - status = "disabled"; -}; - -/* Ethernet */ -&am33xx_pinmux { - ethernet0_pins: pinmux_ethernet0 { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE1) - AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE1) - AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT, MUX_MODE1) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT, MUX_MODE1) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT, MUX_MODE1) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE1) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE1) - AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0) - >; - }; - - mdio_pins: pinmux_mdio { - pinctrl-single,pins = < - /* MDIO */ - AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) - >; - }; -}; - -&cpsw_emac0 { - phy-handle = <&phy0>; - phy-mode = "rmii"; - dual_emac_res_vlan = <1>; -}; - -&davinci_mdio { - pinctrl-names = "default"; - pinctrl-0 = <&mdio_pins>; - status = "okay"; - - phy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -&mac { - slaves = <1>; - pinctrl-names = "default"; - pinctrl-0 = <ðernet0_pins>; - status = "okay"; -}; - -/* I2C Busses */ -&am33xx_pinmux { - i2c0_pins: pinmux_i2c0 { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT, MUX_MODE0) - >; - }; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - clock-frequency = <400000>; - status = "okay"; - - tps: pmic@2d { - reg = <0x2d>; - }; - - i2c_tmp102: temp@4b { - compatible = "ti,tmp102"; - reg = <0x4b>; - status = "disabled"; - }; - - i2c_eeprom: eeprom@52 { - compatible = "atmel,24c32"; - pagesize = <32>; - reg = <0x52>; - status = "disabled"; - }; - - i2c_rtc: rtc@68 { - compatible = "microcrystal,rv4162"; - reg = <0x68>; - status = "disabled"; - }; -}; - -/* NAND memory */ -&am33xx_pinmux { - nandflash_pins: pinmux_nandflash { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0) - >; - }; -}; - -&elm { - status = "okay"; -}; - -&gpmc { - status = "disabled"; - pinctrl-names = "default"; - pinctrl-0 = <&nandflash_pins>; - ranges = <0 0 0x08000000 0x1000000>; /* CS0: NAND */ - nandflash: nand@0,0 { - compatible = "ti,omap2-nand"; - reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ - <1 IRQ_TYPE_NONE>; /* termcount */ - rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ - nand-bus-width = <8>; - ti,nand-ecc-opt = "bch8"; - gpmc,device-nand = "true"; - gpmc,device-width = <1>; - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <30>; - gpmc,cs-wr-off-ns = <30>; - gpmc,adv-on-ns = <0>; - gpmc,adv-rd-off-ns = <30>; - gpmc,adv-wr-off-ns = <30>; - gpmc,we-on-ns = <0>; - gpmc,we-off-ns = <20>; - gpmc,oe-on-ns = <10>; - gpmc,oe-off-ns = <30>; - gpmc,access-ns = <30>; - gpmc,rd-cycle-ns = <30>; - gpmc,wr-cycle-ns = <30>; - gpmc,bus-turnaround-ns = <0>; - gpmc,cycle2cycle-delay-ns = <50>; - gpmc,cycle2cycle-diffcsen; - gpmc,clk-activation-ns = <0>; - gpmc,wr-access-ns = <30>; - gpmc,wr-data-mux-bus-ns = <0>; - - ti,elm-id = <&elm>; - - #address-cells = <1>; - #size-cells = <1>; - }; -}; - -/* Power */ -#include "tps65910.dtsi" - -&tps { - vcc1-supply = <&vcc5v>; - vcc2-supply = <&vcc5v>; - vcc3-supply = <&vcc5v>; - vcc4-supply = <&vcc5v>; - vcc5-supply = <&vcc5v>; - vcc6-supply = <&vcc5v>; - vcc7-supply = <&vcc5v>; - vccio-supply = <&vcc5v>; - - regulators { - vrtc_reg: regulator@0 { - regulator-always-on; - }; - - vio_reg: regulator@1 { - regulator-always-on; - }; - - vdd1_reg: regulator@2 { - /* VDD_MPU voltage limits 0.95V - 1.325V with +/-4% tolerance */ - regulator-name = "vdd_mpu"; - regulator-min-microvolt = <912500>; - regulator-max-microvolt = <1378000>; - regulator-boot-on; - regulator-always-on; - }; - - vdd2_reg: regulator@3 { - /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ - regulator-name = "vdd_core"; - regulator-min-microvolt = <912500>; - regulator-max-microvolt = <1150000>; - regulator-boot-on; - regulator-always-on; - }; - - vdd3_reg: regulator@4 { - regulator-always-on; - }; - - vdig1_reg: regulator@5 { - regulator-name = "vdig1_1p8v"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vdig2_reg: regulator@6 { - regulator-always-on; - }; - - vpll_reg: regulator@7 { - regulator-always-on; - }; - - vdac_reg: regulator@8 { - regulator-always-on; - }; - - vaux1_reg: regulator@9 { - regulator-always-on; - }; - - vaux2_reg: regulator@10 { - regulator-always-on; - }; - - vaux33_reg: regulator@11 { - regulator-always-on; - }; - - vmmc_reg: regulator@12 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; -}; - -/* SPI Busses */ -&am33xx_pinmux { - spi0_pins: pinmux_spi0 { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0) - >; - }; -}; - -&spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins>; - status = "okay"; - - serial_flash: m25p80@0 { - compatible = "jedec,spi-nor"; - spi-max-frequency = <48000000>; - reg = <0x0>; - m25p,fast-read; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - }; -}; diff --git a/sys/gnu/dts/arm/am335x-pocketbeagle.dts b/sys/gnu/dts/arm/am335x-pocketbeagle.dts deleted file mode 100644 index ff4f919d22f..00000000000 --- a/sys/gnu/dts/arm/am335x-pocketbeagle.dts +++ /dev/null @@ -1,237 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ - * - * Author: Robert Nelson - */ -/dts-v1/; - -#include "am33xx.dtsi" -#include "am335x-osd335x-common.dtsi" - -/ { - model = "TI AM335x PocketBeagle"; - compatible = "ti,am335x-pocketbeagle", "ti,am335x-bone", "ti,am33xx"; - - chosen { - stdout-path = &uart0; - }; - - leds { - pinctrl-names = "default"; - pinctrl-0 = <&usr_leds_pins>; - - compatible = "gpio-leds"; - - usr0 { - label = "beaglebone:green:usr0"; - gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - - usr1 { - label = "beaglebone:green:usr1"; - gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc0"; - default-state = "off"; - }; - - usr2 { - label = "beaglebone:green:usr2"; - gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "cpu0"; - default-state = "off"; - }; - - usr3 { - label = "beaglebone:green:usr3"; - gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - - vmmcsd_fixed: fixedregulator0 { - compatible = "regulator-fixed"; - regulator-name = "vmmcsd_fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&am33xx_pinmux { - i2c2_pins: pinmux-i2c2-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* (D17) uart1_rtsn.I2C2_SCL */ - AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* (D18) uart1_ctsn.I2C2_SDA */ - >; - }; - - ehrpwm0_pins: pinmux-ehrpwm0-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* (A13) mcasp0_aclkx.ehrpwm0A */ - >; - }; - - ehrpwm1_pins: pinmux-ehrpwm1-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT_PULLDOWN, MUX_MODE6) /* (U14) gpmc_a2.ehrpwm1A */ - >; - }; - - mmc0_pins: pinmux-mmc0-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7) /* (C15) spi0_cs1.gpio0[6] */ - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT, MUX_MODE4) /* (B12) mcasp0_aclkr.mmc0_sdwp */ - >; - }; - - spi0_pins: pinmux-spi0-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0) - >; - }; - - spi1_pins: pinmux-spi1-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, PIN_INPUT_PULLUP, MUX_MODE4) /* (C18) eCAP0_in_PWM0_out.spi1_sclk */ - AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT_PULLUP, MUX_MODE4) /* (E18) uart0_ctsn.spi1_d0 */ - AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLUP, MUX_MODE4) /* (E17) uart0_rtsn.spi1_d1 */ - AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_INPUT_PULLUP, MUX_MODE4) /* (A15) xdma_event_intr0.spi1_cs1 */ - >; - }; - - usr_leds_pins: pinmux-usr-leds-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE7) /* (V15) gpmc_a5.gpio1[21] - USR_LED_0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT, MUX_MODE7) /* (U15) gpmc_a6.gpio1[22] - USR_LED_1 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_OUTPUT, MUX_MODE7) /* (T15) gpmc_a7.gpio1[23] - USR_LED_2 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_OUTPUT, MUX_MODE7) /* (V16) gpmc_a8.gpio1[24] - USR_LED_3 */ - >; - }; - - uart0_pins: pinmux-uart0-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - >; - }; - - uart4_pins: pinmux-uart4-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE6) /* (T17) gpmc_wait0.uart4_rxd */ - AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_OUTPUT_PULLDOWN, MUX_MODE6) /* (U17) gpmc_wpn.uart4_txd */ - >; - }; -}; - -&epwmss0 { - status = "okay"; -}; - -&ehrpwm0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&ehrpwm0_pins>; -}; - -&epwmss1 { - status = "okay"; -}; - -&ehrpwm1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&ehrpwm1_pins>; -}; - -&i2c0 { - eeprom: eeprom@50 { - compatible = "atmel,24c256"; - reg = <0x50>; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - - status = "okay"; - clock-frequency = <400000>; -}; - -&mmc1 { - status = "okay"; - vmmc-supply = <&vmmcsd_fixed>; - bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; - cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; -}; - -&rtc { - system-power-controller; -}; - -&tscadc { - status = "okay"; - adc { - ti,adc-channels = <0 1 2 3 4 5 6 7>; - ti,chan-step-avg = <16 16 16 16 16 16 16 16>; - ti,chan-step-opendelay = <0x98 0x98 0x98 0x98 0x98 0x98 0x98 0x98>; - ti,chan-step-sampledelay = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&uart4_pins>; - - status = "okay"; -}; - -&usb { - status = "okay"; -}; - -&usb_ctrl_mod { - status = "okay"; -}; - -&usb0_phy { - status = "okay"; -}; - -&usb0 { - status = "okay"; - dr_mode = "otg"; -}; - -&usb1_phy { - status = "okay"; -}; - -&usb1 { - status = "okay"; - dr_mode = "host"; -}; - -&cppi41dma { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/am335x-regor-rdk.dts b/sys/gnu/dts/arm/am335x-regor-rdk.dts deleted file mode 100644 index 66a1360b83d..00000000000 --- a/sys/gnu/dts/arm/am335x-regor-rdk.dts +++ /dev/null @@ -1,24 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2019 Phytec Messtechnik GmbH - * Author: Teresa Remmet - * - */ - -/dts-v1/; - -#include "am335x-phycore-som.dtsi" -#include "am335x-regor.dtsi" - -/* SoM */ -&gpmc { - status = "okay"; -}; - -&i2c_eeprom { - status = "okay"; -}; - -&serial_flash { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/am335x-regor.dtsi b/sys/gnu/dts/arm/am335x-regor.dtsi deleted file mode 100644 index 5aff02a9576..00000000000 --- a/sys/gnu/dts/arm/am335x-regor.dtsi +++ /dev/null @@ -1,223 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2019 Phytec Messtechnik GmbH - * Author: Teresa Remmet - * - */ - -/ { - model = "Phytec AM335x phyBOARD-REGOR"; - compatible = "phytec,am335x-regor", "phytec,am335x-phycore-som", "ti,am33xx"; - - vcc3v3: fixedregulator@1 { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; - - /* User IO */ - user_leds: user_leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&user_leds_pins>; - - run_stop-led { - gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "gpio"; - default-state = "off"; - }; - - error-led { - gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "gpio"; - default-state = "off"; - }; - }; -}; - -/* User Leds */ -&am33xx_pinmux { - user_leds_pins: pinmux_user_leds { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* lcd_hsync.gpio2_22 */ - AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* mcasp0_fsx.gpio3_15 */ - >; - }; -}; - -/* CAN Busses */ -&am33xx_pinmux { - dcan1_pins: pinmux_dcan1 { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT_PULLUP, MUX_MODE2) /* uart0_ctsn.d_can1_tx */ - AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLUP, MUX_MODE2) /* uart0_rtsn.d_can1_rx */ - >; - }; -}; - -&dcan1 { - pinctrl-names = "default"; - pinctrl-0 = <&dcan1_pins>; - status = "okay"; -}; - -/* Ethernet */ -&am33xx_pinmux { - ethernet1_pins: pinmux_ethernet1 { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT, MUX_MODE1) /* gpmc_a0.mii2_txen */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a1.mii2_rxdv */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT, MUX_MODE1) /* gpmc_a2.mii2_txd3 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT, MUX_MODE1) /* gpmc_a3.mii2_txd2 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT, MUX_MODE1) /* gpmc_a4.mii2_txd1 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE1) /* gpmc_a5.mii2_txd0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a6.mii2_txclk */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a7.mii2_rxclk */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a8.mii2_rxd3 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a9.mii2_rxd2 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a10.mii2_rxd1 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a11.mii2_rxd0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_wpn.mii2_rxerr */ - AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_ben1.mii2_col */ - >; - }; -}; - -&cpsw_emac1 { - phy-handle = <&phy1>; - phy-mode = "mii"; - dual_emac_res_vlan = <2>; -}; - -&davinci_mdio { - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&mac { - slaves = <2>; - pinctrl-names = "default"; - pinctrl-0 = <ðernet0_pins ðernet1_pins>; - dual_emac = <1>; -}; - -/* GPIOs */ -&am33xx_pinmux { - pinctrl-names = "default"; - pinctrl-0 = <&user_gpios_pins>; - - user_gpios_pins: pinmux_user_gpios { - pinctrl-single,pins = < - /* DIGIN 1-4 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT, MUX_MODE7) /* gpmc_ad11.gpio0_27 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_INPUT, MUX_MODE7) /* gpmc_ad10.gpio0_26 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT, MUX_MODE7) /* gpmc_ad9.gpio0_23 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT, MUX_MODE7) /* gpmc_ad8.gpio0_22 */ - /* DIGOUT 1-4 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_OUTPUT, MUX_MODE7) /* gpmc_ad15.gpio1_15 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_OUTPUT, MUX_MODE7) /* gpmc_ad14.gpio1_14 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_OUTPUT, MUX_MODE7) /* gpmc_ad13.gpio1_13 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT, MUX_MODE7) /* gpmc_ad12.gpio1_12 */ - >; - }; -}; - -/* MMC */ -&am33xx_pinmux { - mmc1_pins: pinmux_mmc1 { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT_PULLUP, MUX_MODE7) /* spi0_cs1.mmc0_sdcd */ - >; - }; -}; - -&mmc1 { - vmmc-supply = <&vcc3v3>; - bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -/* RTC */ -&i2c_rtc { - status = "okay"; -}; - -/* UARTs */ -&am33xx_pinmux { - uart0_pins: pinmux_uart0 { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - >; - }; - - uart2_pins: pinmux_uart2 { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLUP, MUX_MODE1) /* mii1_tx_clk.uart2_rxd */ - AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_rx_clk.uart2_txd */ - >; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; - status = "okay"; -}; - -/* RS485 - UART1 */ -&am33xx_pinmux { - uart1_rs485_pins: pinmux_uart1_rs485_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLUP, MUX_MODE0) - >; - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_rs485_pins>; - status = "okay"; - linux,rs485-enabled-at-boot-time; -}; - -/* USB */ -&cppi41dma { - status = "okay"; -}; - -&usb_ctrl_mod { - status = "okay"; -}; - -&usb { - status = "okay"; -}; - -&usb0 { - status = "okay"; -}; - -&usb0_phy { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/am335x-sancloud-bbe.dts b/sys/gnu/dts/arm/am335x-sancloud-bbe.dts deleted file mode 100644 index 8678e6e3549..00000000000 --- a/sys/gnu/dts/arm/am335x-sancloud-bbe.dts +++ /dev/null @@ -1,137 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ - */ -/dts-v1/; - -#include "am33xx.dtsi" -#include "am335x-bone-common.dtsi" -#include "am335x-boneblack-common.dtsi" -#include - -/ { - model = "SanCloud BeagleBone Enhanced"; - compatible = "sancloud,am335x-boneenhanced", "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx"; -}; - -&am33xx_pinmux { - pinctrl-names = "default"; - - cpsw_default: cpsw_default { - pinctrl-single,pins = < - /* Slave 1 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txen.rgmii1_tctl */ - AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd3.rgmii1_td3 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd2.rgmii1_td2 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txclk.rgmii1_tclk */ - AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */ - AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */ - AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */ - AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ - AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ - >; - }; - - cpsw_sleep: cpsw_sleep { - pinctrl-single,pins = < - /* Slave 1 reset value */ - AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) - >; - }; - - davinci_mdio_default: davinci_mdio_default { - pinctrl-single,pins = < - /* MDIO */ - AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) - >; - }; - - davinci_mdio_sleep: davinci_mdio_sleep { - pinctrl-single,pins = < - /* MDIO reset value */ - AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) - >; - }; - - usb_hub_ctrl: usb_hub_ctrl { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_OUTPUT_PULLUP, MUX_MODE7) /* rmii1_refclk.gpio0_29 */ - >; - }; - - mpu6050_pins: pinmux_mpu6050_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT, MUX_MODE7) /* uart0_ctsn.gpio1_8 */ - >; - }; - - lps3331ap_pins: pinmux_lps3331ap_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT, MUX_MODE7) /* gpmc_a10.gpio1_26 */ - >; - }; -}; - -&mac { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&cpsw_default>; - pinctrl-1 = <&cpsw_sleep>; - status = "okay"; -}; - -&davinci_mdio { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&davinci_mdio_default>; - pinctrl-1 = <&davinci_mdio_sleep>; - status = "okay"; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -&cpsw_emac0 { - phy-handle = <ðphy0>; - phy-mode = "rgmii-txid"; -}; - -&i2c0 { - lps331ap: barometer@5c { - compatible = "st,lps331ap-press"; - st,drdy-int-pin = <1>; - reg = <0x5c>; - interrupt-parent = <&gpio1>; - interrupts = <26 IRQ_TYPE_EDGE_RISING>; - }; - - mpu6050: accelerometer@68 { - compatible = "invensense,mpu6050"; - reg = <0x68>; - interrupt-parent = <&gpio0>; - interrupts = <2 IRQ_TYPE_EDGE_RISING>; - orientation = <0xff 0 0 0 1 0 0 0 0xff>; - }; - - usb2512b: usb-hub@2c { - compatible = "microchip,usb2512b"; - reg = <0x2c>; - reset-gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; - /* wifi on port 4 */ - }; -}; diff --git a/sys/gnu/dts/arm/am335x-sbc-t335.dts b/sys/gnu/dts/arm/am335x-sbc-t335.dts deleted file mode 100644 index a3f6bc4072d..00000000000 --- a/sys/gnu/dts/arm/am335x-sbc-t335.dts +++ /dev/null @@ -1,176 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * am335x-sbc-t335.dts - Device Tree file for Compulab SBC-T335 - * - * Copyright (C) 2014 - 2015 CompuLab Ltd. - http://www.compulab.co.il/ - */ - -#include "am335x-cm-t335.dts" - -/ { - model = "CompuLab CM-T335 on SB-T335"; - compatible = "compulab,sbc-t335", "compulab,cm-t335", "ti,am33xx"; - - /* DRM display driver */ - panel { - compatible = "ti,tilcdc,panel"; - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&lcd_pins_default>; - pinctrl-1 = <&lcd_pins_sleep>; - - panel-info { - ac-bias = <255>; - ac-bias-intrpt = <0>; - dma-burst-sz = <16>; - bpp = <32>; - fdd = <0x80>; - sync-edge = <0>; - sync-ctrl = <1>; - raster-order = <0>; - fifo-th = <0>; - }; - display-timings { - /* Timing selection performed by U-Boot */ - timing0: lcd {/* 800x480p62 */ - clock-frequency = <30000000>; - hactive = <800>; - vactive = <480>; - hfront-porch = <39>; - hback-porch = <39>; - hsync-len = <47>; - vback-porch = <29>; - vfront-porch = <13>; - vsync-len = <2>; - hsync-active = <1>; - vsync-active = <1>; - }; - timing1: dvi { /* 1024x768p60 */ - clock-frequency = <65000000>; - hactive = <1024>; - hfront-porch = <24>; - hback-porch = <160>; - hsync-len = <136>; - vactive = <768>; - vfront-porch = <3>; - vback-porch = <29>; - vsync-len = <6>; - hsync-active = <0>; - vsync-active = <0>; - }; - }; - }; -}; - -&am33xx_pinmux { - /* Display */ - lcd_pins_default: lcd_pins_default { - pinctrl-single,pins = < - /* gpmc_ad8.lcd_data23 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_OUTPUT, MUX_MODE1) - /* gpmc_ad9.lcd_data22 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_OUTPUT, MUX_MODE1) - /* gpmc_ad10.lcd_data21 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE1) - /* gpmc_ad11.lcd_data20 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_OUTPUT, MUX_MODE1) - /* gpmc_ad12.lcd_data19 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT, MUX_MODE1) - /* gpmc_ad13.lcd_data18 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_OUTPUT, MUX_MODE1) - /* gpmc_ad14.lcd_data17 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_OUTPUT, MUX_MODE1) - /* gpmc_ad15.lcd_data16 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_OUTPUT, MUX_MODE1) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0) - >; - }; - - lcd_pins_sleep: lcd_pins_sleep { - pinctrl-single,pins = < - /* gpmc_ad8.lcd_data23 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT_PULLDOWN, MUX_MODE7) - /* gpmc_ad9.lcd_data22 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT_PULLDOWN, MUX_MODE7) - /* gpmc_ad10.lcd_data21 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_INPUT_PULLDOWN, MUX_MODE7) - /* gpmc_ad11.lcd_data20 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT_PULLDOWN, MUX_MODE7) - /* gpmc_ad12.lcd_data19 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLDOWN, MUX_MODE7) - /* gpmc_ad13.lcd_data18 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLDOWN, MUX_MODE7) - /* gpmc_ad14.lcd_data17 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLDOWN, MUX_MODE7) - /* gpmc_ad15.lcd_data16 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PULL_DISABLE, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PULL_DISABLE, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PULL_DISABLE, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PULL_DISABLE, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PULL_DISABLE, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PULL_DISABLE, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PULL_DISABLE, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PULL_DISABLE, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PULL_DISABLE, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PULL_DISABLE, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PULL_DISABLE, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PULL_DISABLE, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PULL_DISABLE, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PULL_DISABLE, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PULL_DISABLE, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PULL_DISABLE, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) - >; - }; -}; - -&i2c0 { - /* GPIO extender */ - gpio_ext: pca9555@26 { - compatible = "nxp,pca9555"; - pinctrl-names = "default"; - gpio-controller; - #gpio-cells = <2>; - reg = <0x26>; - dvi_ena { - gpio-hog; - gpios = <13 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "dvi-enable"; - }; - lcd_ena { - gpio-hog; - gpios = <11 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "lcd-enable"; - }; - }; -}; - -/* Display */ -&lcdc { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/am335x-shc.dts b/sys/gnu/dts/arm/am335x-shc.dts deleted file mode 100644 index 5b036850401..00000000000 --- a/sys/gnu/dts/arm/am335x-shc.dts +++ /dev/null @@ -1,572 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * support for the bosch am335x based shc c3 board - * - * Copyright, C) 2015 Heiko Schocher - * - */ -/dts-v1/; - -#include "am33xx.dtsi" -#include - -/ { - model = "Bosch SHC"; - compatible = "ti,am335x-shc", "ti,am335x-bone", "ti,am33xx"; - - aliases { - mmcblk0 = &mmc1; - mmcblk1 = &mmc2; - }; - - cpus { - cpu@0 { - /* - * To consider voltage drop between PMIC and SoC, - * tolerance value is reduced to 2% from 4% and - * voltage value is increased as a precaution. - */ - operating-points = < - /* kHz uV */ - 594000 1225000 - 294000 1125000 - >; - voltage-tolerance = <2>; /* 2 percentage */ - cpu0-supply = <&dcdc2_reg>; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - - back_button { - label = "Back Button"; - gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; - linux,code = ; - debounce-interval = <1000>; - wakeup-source; - }; - - front_button { - label = "Front Button"; - gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>; - linux,code = ; - debounce-interval = <1000>; - wakeup-source; - }; - }; - - leds { - pinctrl-names = "default"; - pinctrl-0 = <&user_leds_s0>; - - compatible = "gpio-leds"; - - led1 { - label = "shc:power:red"; - gpios = <&gpio0 23 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led2 { - label = "shc:power:bl"; - gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "timer"; - default-state = "on"; - }; - - led3 { - label = "shc:lan:red"; - gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led4 { - label = "shc:lan:bl"; - gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led5 { - label = "shc:cloud:red"; - gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led6 { - label = "shc:cloud:bl"; - gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000>; /* 512 MB */ - }; - - vmmcsd_fixed: fixedregulator0 { - compatible = "regulator-fixed"; - regulator-name = "vmmcsd_fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&aes { - status = "okay"; -}; - -&cppi41dma { - status = "okay"; -}; - -&davinci_mdio { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&davinci_mdio_default>; - pinctrl-1 = <&davinci_mdio_sleep>; - status = "okay"; - - ethernetphy0: ethernet-phy@0 { - reg = <0>; - smsc,disable-energy-detect; - }; -}; - -&epwmss1 { - status = "okay"; - - ehrpwm1: pwm@200 { - pinctrl-names = "default"; - pinctrl-0 = <&ehrpwm1_pins>; - status = "okay"; - }; -}; - -&gpio1 { - hmtc_rst { - gpio-hog; - gpios = <24 GPIO_ACTIVE_LOW>; - output-high; - line-name = "homematic_reset"; - }; - - hmtc_prog { - gpio-hog; - gpios = <27 GPIO_ACTIVE_LOW>; - output-high; - line-name = "homematic_program"; - }; -}; - -&gpio3 { - zgb_rst { - gpio-hog; - gpios = <18 GPIO_ACTIVE_LOW>; - output-low; - line-name = "zigbee_reset"; - }; - - zgb_boot { - gpio-hog; - gpios = <19 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "zigbee_boot"; - }; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - status = "okay"; - clock-frequency = <400000>; - - tps: tps@24 { - reg = <0x24>; - }; - - at24@50 { - compatible = "atmel,24c32"; - pagesize = <32>; - reg = <0x50>; - }; - - pcf8563@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; -}; - -&mac { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&cpsw_default>; - pinctrl-1 = <&cpsw_sleep>; - status = "okay"; - slaves = <1>; - cpsw_emac0: slave@200 { - phy-mode = "mii"; - phy-handle = <ðernetphy0>; - }; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - bus-width = <0x4>; - cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; - cd-inverted; - max-frequency = <26000000>; - vmmc-supply = <&vmmcsd_fixed>; - status = "okay"; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&emmc_pins>; - bus-width = <8>; - max-frequency = <26000000>; - sd-uhs-sdr25; - vmmc-supply = <&vmmcsd_fixed>; - status = "okay"; -}; - -&mmc3 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc3_pins>; - bus-width = <4>; - cap-power-off-card; - max-frequency = <26000000>; - sd-uhs-sdr25; - vmmc-supply = <&vmmcsd_fixed>; - status = "okay"; -}; - -&rtc { - ti,no-init; -}; - -&sham { - status = "okay"; -}; - -&tps { - compatible = "ti,tps65217"; - ti,pmic-shutdown-controller; - - regulators { - #address-cells = <1>; - #size-cells = <0>; - - dcdc1_reg: regulator@0 { - reg = <0>; - regulator-name = "vdds_dpr"; - regulator-compatible = "dcdc1"; - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1450000>; - regulator-boot-on; - regulator-always-on; - }; - - dcdc2_reg: regulator@1 { - reg = <1>; - /* - * VDD_MPU voltage limits 0.95V - 1.26V with - * +/-4% tolerance - */ - regulator-compatible = "dcdc2"; - regulator-name = "vdd_mpu"; - regulator-min-microvolt = <925000>; - regulator-max-microvolt = <1375000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <70000>; - }; - - dcdc3_reg: regulator@2 { - reg = <2>; - /* - * VDD_CORE voltage limits 0.95V - 1.1V with - * +/-4% tolerance - */ - regulator-name = "vdd_core"; - regulator-compatible = "dcdc3"; - regulator-min-microvolt = <925000>; - regulator-max-microvolt = <1125000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1_reg: regulator@3 { - reg = <3>; - regulator-name = "vio,vrtc,vdds"; - regulator-compatible = "ldo1"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo2_reg: regulator@4 { - reg = <4>; - regulator-name = "vdd_3v3aux"; - regulator-compatible = "ldo2"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo3_reg: regulator@5 { - reg = <5>; - regulator-name = "vdd_1v8"; - regulator-compatible = "ldo3"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo4_reg: regulator@6 { - reg = <6>; - regulator-name = "vdd_3v3a"; - regulator-compatible = "ldo4"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&uart4_pins>; - status = "okay"; -}; - -&usb { - status = "okay"; -}; - -&usb_ctrl_mod { - status = "okay"; -}; - -&usb1_phy { - status = "okay"; -}; - -&usb1 { - status = "okay"; - dr_mode = "host"; -}; - -&am33xx_pinmux { - pinctrl-names = "default"; - pinctrl-0 = <&clkout2_pin>; - - clkout2_pin: pinmux_clkout2_pin { - pinctrl-single,pins = < - /* xdma_event_intr1.clkout2 */ - AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_INPUT, MUX_MODE6) - >; - }; - - cpsw_default: cpsw_default { - pinctrl-single,pins = < - /* Slave 1 */ - AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE0) - >; - }; - - cpsw_sleep: cpsw_sleep { - pinctrl-single,pins = < - /* Slave 1 reset value */ - AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) - >; - }; - - davinci_mdio_default: davinci_mdio_default { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) - >; - }; - - davinci_mdio_sleep: davinci_mdio_sleep { - pinctrl-single,pins = < - /* MDIO reset value */ - AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) - >; - }; - - ehrpwm1_pins: pinmux_ehrpwm1 { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT, MUX_MODE6) /* gpmc_a3.gpio1_19 */ - >; - }; - - emmc_pins: pinmux_emmc_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT, MUX_MODE2) - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1) - >; - }; - - i2c0_pins: pinmux_i2c0_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT, MUX_MODE0) - >; - }; - - mmc1_pins: pinmux_mmc1_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE5) - >; - }; - - mmc3_pins: pinmux_mmc3_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT, MUX_MODE3) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT, MUX_MODE3) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT, MUX_MODE3) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT, MUX_MODE3) - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_INPUT, MUX_MODE3) - AM33XX_PADCONF(AM335X_PIN_GPMC_CLK, PIN_INPUT, MUX_MODE3) - >; - }; - - uart0_pins: pinmux_uart0_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT, MUX_MODE0) - >; - }; - - uart1_pins: pinmux_uart1 { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT, MUX_MODE0) - >; - }; - - uart2_pins: pinmux_uart2_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE1) - AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT, MUX_MODE1) - >; - }; - - uart4_pins: pinmux_uart4_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE6) - AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_OUTPUT_PULLUP, MUX_MODE6) - >; - }; - - user_leds_s0: user_leds_s0 { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_OUTPUT, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_OUTPUT, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_OUTPUT, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_OUTPUT, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_OUTPUT_PULLUP, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_OUTPUT_PULLUP, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_INPUT, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_INPUT, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_OUTPUT, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_OUTPUT, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, PIN_OUTPUT_PULLUP, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_OUTPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MCASP0_FSR, PIN_OUTPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR1, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLUP, MUX_MODE7) - >; - }; -}; diff --git a/sys/gnu/dts/arm/am335x-sl50.dts b/sys/gnu/dts/arm/am335x-sl50.dts deleted file mode 100644 index 2f82095e721..00000000000 --- a/sys/gnu/dts/arm/am335x-sl50.dts +++ /dev/null @@ -1,739 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2015 Toby Churchill - http://www.toby-churchill.com/ - */ -/dts-v1/; - -#include "am33xx.dtsi" -#include -#include - -/ { - model = "Toby Churchill SL50 Series"; - compatible = "tcl,am335x-sl50", "ti,am33xx"; - - cpus { - cpu@0 { - cpu0-supply = <&dcdc2_reg>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000>; /* 512 MB */ - }; - - chosen { - stdout-path = &uart0; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins>; - - led0 { - label = "sl50:red:usr0"; - gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led1 { - label = "sl50:green:usr1"; - gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led2 { - label = "sl50:red:usr2"; - gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led3 { - label = "sl50:green:usr3"; - gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - }; - - backlight0: disp0 { - compatible = "pwm-backlight"; - pinctrl-names = "default"; - pinctrl-0 = <&backlight0_pins>; - pwms = <&ehrpwm1 0 500000 PWM_POLARITY_INVERTED>; - brightness-levels = < 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100>; - default-brightness-level = <50>; - enable-gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>; - power-supply = <&vdd_sys_reg>; - }; - - backlight1: disp1 { - compatible = "pwm-backlight"; - pinctrl-names = "default"; - pinctrl-0 = <&backlight1_pins>; - pwms = <&ehrpwm1 1 500000 PWM_POLARITY_INVERTED>; - brightness-levels = < 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100>; - default-brightness-level = <50>; - enable-gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>; - power-supply = <&vdd_sys_reg>; - }; - - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - /* audio external oscillator */ - audio_mclk_fixed: oscillator@0 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24576000>; /* 24.576MHz */ - }; - - audio_mclk: audio_mclk_gate@0 { - compatible = "gpio-gate-clock"; - #clock-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&audio_mclk_pins>; - clocks = <&audio_mclk_fixed>; - enable-gpios = <&gpio1 27 0>; - }; - }; - - panel: lcd_panel { - compatible = "ti,tilcdc,panel"; - pinctrl-names = "default"; - pinctrl-0 = <&lcd_pins>; - - panel-info { - ac-bias = <255>; - ac-bias-intrpt = <0>; - dma-burst-sz = <16>; - bpp = <16>; - fdd = <0x80>; - tft-alt-mode = <0>; - mono-8bit-mode = <0>; - sync-edge = <0>; - sync-ctrl = <1>; - raster-order = <0>; - fifo-th = <0>; - }; - - display-timings { - native-mode = <&timing0>; - timing0: 960x128 { - clock-frequency = <18000000>; - hactive = <960>; - vactive = <272>; - - hback-porch = <40>; - hfront-porch = <16>; - hsync-len = <24>; - hsync-active = <0>; - - vback-porch = <3>; - vfront-porch = <8>; - vsync-len = <4>; - vsync-active = <0>; - }; - }; - }; - - sound { - compatible = "audio-graph-card"; - label = "sound-card"; - pinctrl-names = "default"; - pinctrl-0 = <&audio_pa_pins>; - - widgets = "Headphone", "Headphone Jack", - "Speaker", "Speaker External", - "Line", "Line In", - "Microphone", "Microphone Jack"; - - routing = "Headphone Jack", "HPLOUT", - "Headphone Jack", "HPROUT", - "Amplifier", "MONO_LOUT", - "Speaker External", "Amplifier", - "LINE1R", "Line In", - "LINE1L", "Line In", - "MIC3L", "Microphone Jack", - "MIC3R", "Microphone Jack", - "Microphone Jack", "Mic Bias"; - - dais = <&cpu_port>; - - pa-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>; - }; - - emmc_pwrseq: pwrseq@0 { - compatible = "mmc-pwrseq-emmc"; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_pwrseq_pins>; - reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; - }; - - vdd_sys_reg: regulator@0 { - compatible = "regulator-fixed"; - regulator-name = "vdd_sys_reg"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - vmmcsd_fixed: fixedregulator0 { - compatible = "regulator-fixed"; - regulator-name = "vmmcsd_fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&am33xx_pinmux { - pinctrl-names = "default"; - pinctrl-0 = <&lwb_pins>; - - audio_pins: pinmux_audio_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_INPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_INPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR0, PIN_INPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_OUTPUT_PULLDOWN, MUX_MODE2) - >; - }; - - audio_pa_pins: pinmux_audio_pa_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT_PULLDOWN, MUX_MODE7) /* SoundPA_en - mcasp0_aclkr.gpio3_18 */ - >; - }; - - audio_mclk_pins: pinmux_audio_mclk_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_a11.gpio1_27 */ - >; - }; - - backlight0_pins: pinmux_backlight0_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE7) /* gpmc_wen.gpio2_4 */ - >; - }; - - backlight1_pins: pinmux_backlight1_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE7) /* gpmc_ad10.gpio0_26 */ - >; - }; - - lcd_pins: pinmux_lcd_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - >; - }; - - led_pins: pinmux_led_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE7) /* gpmc_a5.gpio1_21 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT, MUX_MODE7) /* gpmc_a6.gpio1_22 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_OUTPUT, MUX_MODE7) /* gpmc_a7.gpio1_23 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_OUTPUT, MUX_MODE7) /* gpmc_a8.gpio1_24 */ - >; - }; - - uart0_pins: pinmux_uart0_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - >; - }; - - uart1_pins: pinmux_uart1_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - >; - }; - - uart4_pins: pinmux_uart4_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE6) /* gpmc_wait0.uart4_rxd */ - AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_OUTPUT_PULLDOWN, MUX_MODE6) /* gpmc_wpn.uart4_txd */ - >; - }; - - i2c0_pins: pinmux_i2c0_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) - >; - }; - - i2c2_pins: pinmux_i2c2_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart1_ctsn.i2c2_sda */ - AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart1_rtsn.i2c2_scl */ - >; - }; - - cpsw_default: cpsw_default { - pinctrl-single,pins = < - /* Slave 1 */ - AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE0) - >; - }; - - cpsw_sleep: cpsw_sleep { - pinctrl-single,pins = < - /* Slave 1 reset value */ - AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) - >; - }; - - davinci_mdio_default: davinci_mdio_default { - pinctrl-single,pins = < - /* MDIO */ - AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) - /* Ethernet */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLUP, MUX_MODE7) /* Ethernet_nRST - gpmc_ad14.gpio1_14 */ - >; - }; - - davinci_mdio_sleep: davinci_mdio_sleep { - pinctrl-single,pins = < - /* MDIO reset value */ - AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) - >; - }; - - mmc1_pins: pinmux_mmc1_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT, MUX_MODE7) /* uart0_rtsn.gpio1_9 */ - >; - }; - - emmc_pwrseq_pins: pinmux_emmc_pwrseq_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_a4.gpio1_20 */ - >; - }; - - emmc_pins: pinmux_emmc_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */ - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ - >; - }; - - ehrpwm1_pins: pinmux_ehrpwm1a_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT, MUX_MODE6) /* gpmc_a2.ehrpwm1a */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT, MUX_MODE6) /* gpmc_a3.ehrpwm1b */ - >; - }; - - rtc0_irq_pins: pinmux_rtc0_irq_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_ad9.gpio0_23 */ - >; - }; - - spi0_pins: pinmux_spi0_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLUP, MUX_MODE0) /* SPI0_MOSI */ - AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0) /* SPI0_MISO */ - AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0) /* SPI0_CS0 (NBATTSS) */ - AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT_PULLUP, MUX_MODE0) /* SPI0_CS1 (FPGA_FLASH_NCS) */ - >; - }; - - lwb_pins: pinmux_lwb_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLUP, MUX_MODE7) /* nKbdInt - gpmc_ad12.gpio1_12 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLUP, MUX_MODE7) /* nKbdReset - gpmc_ad13.gpio1_13 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLUP, MUX_MODE7) /* USB1_enPower - gpmc_a1.gpio1_17 */ - /* PDI Bus - Battery system */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLUP, MUX_MODE7) /* nBattReset gpmc_a0.gpio1_16 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLUP, MUX_MODE7) /* BattPDIData gpmc_ad15.gpio1_15 */ - /* FPGA */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT_PULLUP, MUX_MODE7) /* FPGA_DONE - gpmc_ad8.gpio0_22 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLUP, MUX_MODE7) /* FPGA_NRST - gpmc_a0.gpio1_16 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE7) /* FPGA_RUN - gpmc_a1.gpio1_17 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLUP, MUX_MODE7) /* ENFPGA - gpmc_a9.gpio1_25 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7) /* FPGA_PROGRAM - gpmc_a10.gpio1_26 */ - >; - }; -}; - -&i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - - clock-frequency = <400000>; - - tps: tps@24 { - reg = <0x24>; - }; - - rtc0: rtc@68 { - compatible = "dallas,ds1339"; - pinctrl-names = "default"; - pinctrl-0 = <&rtc0_irq_pins>; - interrupt-parent = <&gpio0>; - interrupts = <23 IRQ_TYPE_EDGE_FALLING>; /* gpio 23 */ - wakeup-source; - trickle-resistor-ohms = <2000>; - reg = <0x68>; - }; - - eeprom: eeprom@50 { - compatible = "atmel,24c256"; - reg = <0x50>; - }; - - gpio_exp: mcp23017@20 { - compatible = "microchip,mcp23017"; - reg = <0x20>; - }; - -}; - -&i2c2 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - - clock-frequency = <400000>; - - audio_codec: tlv320aic3106@1b { - status = "okay"; - compatible = "ti,tlv320aic3106"; - #sound-dai-cells = <0>; - reg = <0x1b>; - ai3x-micbias-vg = <2>; /* 2.5V */ - - AVDD-supply = <&ldo4_reg>; - IOVDD-supply = <&ldo4_reg>; - DRVDD-supply = <&ldo4_reg>; - DVDD-supply = <&ldo3_reg>; - - codec_port: port { - codec_endpoint: endpoint { - remote-endpoint = <&cpu_endpoint>; - clocks = <&audio_mclk>; - }; - }; - }; - - /* Ambient Light Sensor */ - als: isl29023@44 { - compatible = "isil,isl29023"; - reg = <0x44>; - }; -}; - -&rtc { - status = "disabled"; -}; - -&usb { - status = "okay"; -}; - -&usb_ctrl_mod { - status = "okay"; -}; - -&usb0_phy { - status = "okay"; -}; - -&usb1_phy { - status = "okay"; -}; - -&usb0 { - status = "okay"; - dr_mode = "otg"; -}; - -&usb1 { - status = "okay"; - dr_mode = "host"; -}; - -&cppi41dma { - status = "okay"; -}; - -&mmc1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - bus-width = <4>; - cd-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; - vmmc-supply = <&vmmcsd_fixed>; -}; - -&mmc2 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_pins>; - bus-width = <8>; - vmmc-supply = <&vmmcsd_fixed>; - mmc-pwrseq = <&emmc_pwrseq>; -}; - -&mcasp0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&audio_pins>; - #sound-dai-cells = <0>; - op-mode = <0>; /* MCASP_ISS_MODE */ - tdm-slots = <2>; - /* 4 serializers */ - serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ - 0 0 1 2 - >; - tx-num-evt = <32>; - rx-num-evt = <32>; - - cpu_port: port { - cpu_endpoint: endpoint { - remote-endpoint = <&codec_endpoint>; - - dai-format = "dsp_b"; - bitclock-master = <&codec_port>; - frame-master = <&codec_port>; - bitclock-inversion; - clocks = <&audio_mclk>; - }; - }; -}; - -&uart0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; -}; - -&uart1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; -}; - -&uart4 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart4_pins>; -}; - -&spi0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins>; - - flash: n25q032@1 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "micron,n25q032"; - reg = <1>; - spi-max-frequency = <5000000>; - }; -}; - -#include "tps65217.dtsi" - -&tps { - ti,pmic-shutdown-controller; - - interrupt-parent = <&intc>; - interrupts = <7>; /* NNMI */ - - regulators { - dcdc1_reg: regulator@0 { - /* VDDS_DDR */ - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - }; - - dcdc2_reg: regulator@1 { - /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ - regulator-name = "vdd_mpu"; - regulator-min-microvolt = <925000>; - regulator-max-microvolt = <1325000>; - regulator-boot-on; - regulator-always-on; - }; - - dcdc3_reg: regulator@2 { - /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ - regulator-name = "vdd_core"; - regulator-min-microvolt = <925000>; - regulator-max-microvolt = <1150000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1_reg: regulator@3 { - /* VRTC / VIO / VDDS*/ - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo2_reg: regulator@4 { - /* VDD_3V3AUX */ - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo3_reg: regulator@5 { - /* VDD_1V8 */ - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo4_reg: regulator@6 { - /* VDD_3V3A */ - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; -}; - -&cpsw_emac0 { - phy-mode = "mii"; - phy-handle = <ðphy0>; -}; - -&mac { - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&cpsw_default>; - pinctrl-1 = <&cpsw_sleep>; -}; - -&davinci_mdio { - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&davinci_mdio_default>; - pinctrl-1 = <&davinci_mdio_sleep>; - reset-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; - reset-delay-us = <100>; /* PHY datasheet states 100us min */ - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -&sham { - status = "okay"; -}; - -&aes { - status = "okay"; -}; - -&epwmss1 { - status = "okay"; -}; - -&ehrpwm1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&ehrpwm1_pins>; -}; - -&lcdc { - status = "okay"; -}; - -&tscadc { - status = "okay"; -}; - -&am335x_adc { - ti,adc-channels = <0 1 2 3 4 5 6 7>; -}; diff --git a/sys/gnu/dts/arm/am335x-wega-rdk.dts b/sys/gnu/dts/arm/am335x-wega-rdk.dts deleted file mode 100644 index 866b5f0cbfb..00000000000 --- a/sys/gnu/dts/arm/am335x-wega-rdk.dts +++ /dev/null @@ -1,23 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2015 Phytec Messtechnik GmbH - * Author: Teresa Remmet - */ - -/dts-v1/; - -#include "am335x-phycore-som.dtsi" -#include "am335x-wega.dtsi" - -/* SoM */ -&gpmc { - status = "okay"; -}; - -&i2c_eeprom { - status = "okay"; -}; - -&i2c_rtc { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/am335x-wega.dtsi b/sys/gnu/dts/arm/am335x-wega.dtsi deleted file mode 100644 index 61fc4cd2d16..00000000000 --- a/sys/gnu/dts/arm/am335x-wega.dtsi +++ /dev/null @@ -1,222 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2015 Phytec Messtechnik GmbH - * Author: Teresa Remmet - */ - -/ { - model = "Phytec AM335x phyBOARD-WEGA"; - compatible = "phytec,am335x-wega", "phytec,am335x-phycore-som", "ti,am33xx"; - - sound: sound_iface { - compatible = "ti,da830-evm-audio"; - }; - - vcc3v3: fixedregulator1 { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; -}; - -/* Audio */ -&am33xx_pinmux { - mcasp0_pins: pinmux_mcasp0 { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_INPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_INPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR0, PIN_INPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR1, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - >; - }; -}; - -&i2c0 { - tlv320aic3007: tlv320aic3007@18 { - compatible = "ti,tlv320aic3007"; - reg = <0x18>; - AVDD-supply = <&vcc3v3>; - IOVDD-supply = <&vcc3v3>; - DRVDD-supply = <&vcc3v3>; - DVDD-supply = <&vdig1_reg>; - status = "okay"; - }; -}; - -&mcasp0 { - pinctrl-names = "default"; - pinctrl-0 = <&mcasp0_pins>; - op-mode = <0>; /* DAVINCI_MCASP_IIS_MODE */ - tdm-slots = <2>; - serial-dir = < - 2 1 0 0 /* # 0: INACTIVE, 1: TX, 2: RX */ - >; - tx-num-evt = <16>; - rt-num-evt = <16>; - status = "okay"; -}; - -&sound { - ti,model = "AM335x-Wega"; - ti,audio-codec = <&tlv320aic3007>; - ti,mcasp-controller = <&mcasp0>; - ti,audio-routing = - "Line Out", "LLOUT", - "Line Out", "RLOUT", - "LINE1L", "Line In", - "LINE1R", "Line In"; - clocks = <&mcasp0_fck>; - clock-names = "mclk"; - status = "okay"; -}; - -/* CAN Busses */ -&am33xx_pinmux { - dcan1_pins: pinmux_dcan1 { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT_PULLUP, MUX_MODE2) /* uart0_ctsn.d_can1_tx */ - AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLUP, MUX_MODE2) /* uart0_rtsn.d_can1_rx */ - >; - }; -}; - -&dcan1 { - pinctrl-names = "default"; - pinctrl-0 = <&dcan1_pins>; - status = "okay"; -}; - -/* Ethernet */ -&am33xx_pinmux { - ethernet1_pins: pinmux_ethernet1 { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT, MUX_MODE1) /* gpmc_a0.mii2_txen */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a1.mii2_rxdv */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT, MUX_MODE1) /* gpmc_a2.mii2_txd3 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT, MUX_MODE1) /* gpmc_a3.mii2_txd2 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT, MUX_MODE1) /* gpmc_a4.mii2_txd1 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE1) /* gpmc_a5.mii2_txd0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a6.mii2_txclk */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a7.mii2_rxclk */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a8.mii2_rxd3 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a9.mii2_rxd2 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a10.mii2_rxd1 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a11.mii2_rxd0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_wpn.mii2_rxerr */ - AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_ben1.mii2_col */ - >; - }; -}; - -&cpsw_emac1 { - phy-handle = <&phy1>; - phy-mode = "mii"; - dual_emac_res_vlan = <2>; -}; - -&davinci_mdio { - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&mac { - slaves = <2>; - pinctrl-names = "default"; - pinctrl-0 = <ðernet0_pins ðernet1_pins>; - dual_emac = <1>; -}; - -/* MMC */ -&am33xx_pinmux { - mmc1_pins: pinmux_mmc1 { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT_PULLUP, MUX_MODE7) /* spi0_cs1.mmc0_sdcd */ - >; - }; -}; - -&mmc1 { - vmmc-supply = <&vcc3v3>; - bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -/* Power */ -&vdig1_reg { - regulator-boot-on; - regulator-always-on; -}; - -/* UARTs */ -&am33xx_pinmux { - uart0_pins: pinmux_uart0 { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - >; - }; - - uart1_pins: pinmux_uart1_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - >; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; - status = "okay"; -}; - -/* USB */ -&cppi41dma { - status = "okay"; -}; - -&usb_ctrl_mod { - status = "okay"; -}; - -&usb { - status = "okay"; -}; - -&usb0 { - status = "okay"; -}; - -&usb0_phy { - status = "okay"; -}; - -&usb1 { - dr_mode = "host"; - status = "okay"; -}; - -&usb1_phy { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/am33xx-clocks.dtsi b/sys/gnu/dts/arm/am33xx-clocks.dtsi deleted file mode 100644 index dced92a8970..00000000000 --- a/sys/gnu/dts/arm/am33xx-clocks.dtsi +++ /dev/null @@ -1,676 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Device Tree Source for AM33xx clock data - * - * Copyright (C) 2013 Texas Instruments, Inc. - */ -&scm_clocks { - sys_clkin_ck: sys_clkin_ck@40 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>; - ti,bit-shift = <22>; - reg = <0x0040>; - }; - - adc_tsc_fck: adc_tsc_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&sys_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - dcan0_fck: dcan0_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&sys_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - dcan1_fck: dcan1_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&sys_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - mcasp0_fck: mcasp0_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&sys_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - mcasp1_fck: mcasp1_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&sys_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - smartreflex0_fck: smartreflex0_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&sys_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - smartreflex1_fck: smartreflex1_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&sys_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - sha0_fck: sha0_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&sys_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - aes0_fck: aes0_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&sys_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - rng_fck: rng_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&sys_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - ehrpwm0_tbclk: ehrpwm0_tbclk@44e10664 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&l4ls_gclk>; - ti,bit-shift = <0>; - reg = <0x0664>; - }; - - ehrpwm1_tbclk: ehrpwm1_tbclk@44e10664 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&l4ls_gclk>; - ti,bit-shift = <1>; - reg = <0x0664>; - }; - - ehrpwm2_tbclk: ehrpwm2_tbclk@44e10664 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&l4ls_gclk>; - ti,bit-shift = <2>; - reg = <0x0664>; - }; -}; -&prcm_clocks { - clk_32768_ck: clk_32768_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - clk_rc32k_ck: clk_rc32k_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32000>; - }; - - virt_19200000_ck: virt_19200000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <19200000>; - }; - - virt_24000000_ck: virt_24000000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - }; - - virt_25000000_ck: virt_25000000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <25000000>; - }; - - virt_26000000_ck: virt_26000000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <26000000>; - }; - - tclkin_ck: tclkin_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <12000000>; - }; - - dpll_core_ck: dpll_core_ck@490 { - #clock-cells = <0>; - compatible = "ti,am3-dpll-core-clock"; - clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x0490>, <0x045c>, <0x0468>; - }; - - dpll_core_x2_ck: dpll_core_x2_ck { - #clock-cells = <0>; - compatible = "ti,am3-dpll-x2-clock"; - clocks = <&dpll_core_ck>; - }; - - dpll_core_m4_ck: dpll_core_m4_ck@480 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <31>; - reg = <0x0480>; - ti,index-starts-at-one; - }; - - dpll_core_m5_ck: dpll_core_m5_ck@484 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <31>; - reg = <0x0484>; - ti,index-starts-at-one; - }; - - dpll_core_m6_ck: dpll_core_m6_ck@4d8 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <31>; - reg = <0x04d8>; - ti,index-starts-at-one; - }; - - dpll_mpu_ck: dpll_mpu_ck@488 { - #clock-cells = <0>; - compatible = "ti,am3-dpll-clock"; - clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x0488>, <0x0420>, <0x042c>; - }; - - dpll_mpu_m2_ck: dpll_mpu_m2_ck@4a8 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_mpu_ck>; - ti,max-div = <31>; - reg = <0x04a8>; - ti,index-starts-at-one; - }; - - dpll_ddr_ck: dpll_ddr_ck@494 { - #clock-cells = <0>; - compatible = "ti,am3-dpll-no-gate-clock"; - clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x0494>, <0x0434>, <0x0440>; - }; - - dpll_ddr_m2_ck: dpll_ddr_m2_ck@4a0 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_ddr_ck>; - ti,max-div = <31>; - reg = <0x04a0>; - ti,index-starts-at-one; - }; - - dpll_ddr_m2_div2_ck: dpll_ddr_m2_div2_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_ddr_m2_ck>; - clock-mult = <1>; - clock-div = <2>; - }; - - dpll_disp_ck: dpll_disp_ck@498 { - #clock-cells = <0>; - compatible = "ti,am3-dpll-no-gate-clock"; - clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x0498>, <0x0448>, <0x0454>; - }; - - dpll_disp_m2_ck: dpll_disp_m2_ck@4a4 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_disp_ck>; - ti,max-div = <31>; - reg = <0x04a4>; - ti,index-starts-at-one; - ti,set-rate-parent; - }; - - dpll_per_ck: dpll_per_ck@48c { - #clock-cells = <0>; - compatible = "ti,am3-dpll-no-gate-j-type-clock"; - clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x048c>, <0x0470>, <0x049c>; - }; - - dpll_per_m2_ck: dpll_per_m2_ck@4ac { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_per_ck>; - ti,max-div = <31>; - reg = <0x04ac>; - ti,index-starts-at-one; - }; - - dpll_per_m2_div4_wkupdm_ck: dpll_per_m2_div4_wkupdm_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_per_m2_ck>; - clock-mult = <1>; - clock-div = <4>; - }; - - dpll_per_m2_div4_ck: dpll_per_m2_div4_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_per_m2_ck>; - clock-mult = <1>; - clock-div = <4>; - }; - - clk_24mhz: clk_24mhz { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_per_m2_ck>; - clock-mult = <1>; - clock-div = <8>; - }; - - clkdiv32k_ck: clkdiv32k_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&clk_24mhz>; - clock-mult = <1>; - clock-div = <732>; - }; - - l3_gclk: l3_gclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_core_m4_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - pruss_ocp_gclk: pruss_ocp_gclk@530 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&l3_gclk>, <&dpll_disp_m2_ck>; - reg = <0x0530>; - }; - - mmu_fck: mmu_fck@914 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&dpll_core_m4_ck>; - ti,bit-shift = <1>; - reg = <0x0914>; - }; - - timer1_fck: timer1_fck@528 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>; - reg = <0x0528>; - }; - - timer2_fck: timer2_fck@508 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; - reg = <0x0508>; - }; - - timer3_fck: timer3_fck@50c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; - reg = <0x050c>; - }; - - timer4_fck: timer4_fck@510 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; - reg = <0x0510>; - }; - - timer5_fck: timer5_fck@518 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; - reg = <0x0518>; - }; - - timer6_fck: timer6_fck@51c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; - reg = <0x051c>; - }; - - timer7_fck: timer7_fck@504 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; - reg = <0x0504>; - }; - - usbotg_fck: usbotg_fck@47c { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&dpll_per_ck>; - ti,bit-shift = <8>; - reg = <0x047c>; - }; - - dpll_core_m4_div2_ck: dpll_core_m4_div2_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_core_m4_ck>; - clock-mult = <1>; - clock-div = <2>; - }; - - ieee5000_fck: ieee5000_fck@e4 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&dpll_core_m4_div2_ck>; - ti,bit-shift = <1>; - reg = <0x00e4>; - }; - - wdt1_fck: wdt1_fck@538 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&clk_rc32k_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; - reg = <0x0538>; - }; - - l4_rtc_gclk: l4_rtc_gclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_core_m4_ck>; - clock-mult = <1>; - clock-div = <2>; - }; - - l4hs_gclk: l4hs_gclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_core_m4_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - l3s_gclk: l3s_gclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_core_m4_div2_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - l4fw_gclk: l4fw_gclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_core_m4_div2_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - l4ls_gclk: l4ls_gclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_core_m4_div2_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - sysclk_div_ck: sysclk_div_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_core_m4_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - cpsw_125mhz_gclk: cpsw_125mhz_gclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_core_m5_ck>; - clock-mult = <1>; - clock-div = <2>; - }; - - cpsw_cpts_rft_clk: cpsw_cpts_rft_clk@520 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&dpll_core_m5_ck>, <&dpll_core_m4_ck>; - reg = <0x0520>; - }; - - gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck@53c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; - reg = <0x053c>; - }; - - lcd_gclk: lcd_gclk@534 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>; - reg = <0x0534>; - ti,set-rate-parent; - }; - - mmc_clk: mmc_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_per_m2_ck>; - clock-mult = <1>; - clock-div = <2>; - }; - - gfx_fclk_clksel_ck: gfx_fclk_clksel_ck@52c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&dpll_core_m4_ck>, <&dpll_per_m2_ck>; - ti,bit-shift = <1>; - reg = <0x052c>; - }; - - gfx_fck_div_ck: gfx_fck_div_ck@52c { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&gfx_fclk_clksel_ck>; - reg = <0x052c>; - ti,max-div = <2>; - }; - - sysclkout_pre_ck: sysclkout_pre_ck@700 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&clk_32768_ck>, <&l3_gclk>, <&dpll_ddr_m2_ck>, <&dpll_per_m2_ck>, <&lcd_gclk>; - reg = <0x0700>; - }; - - clkout2_div_ck: clkout2_div_ck@700 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&sysclkout_pre_ck>; - ti,bit-shift = <3>; - ti,max-div = <8>; - reg = <0x0700>; - }; - - clkout2_ck: clkout2_ck@700 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&clkout2_div_ck>; - ti,bit-shift = <7>; - reg = <0x0700>; - }; -}; - -&prcm { - per_cm: per-cm@0 { - compatible = "ti,omap4-cm"; - reg = <0x0 0x400>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x0 0x400>; - - l4ls_clkctrl: l4ls-clkctrl@38 { - compatible = "ti,clkctrl"; - reg = <0x38 0x2c>, <0x6c 0x28>, <0xac 0xc>, <0xc0 0x1c>, <0xec 0xc>, <0x10c 0x8>, <0x130 0x4>; - #clock-cells = <2>; - }; - - l3s_clkctrl: l3s-clkctrl@1c { - compatible = "ti,clkctrl"; - reg = <0x1c 0x4>, <0x30 0x8>, <0x68 0x4>, <0xf8 0x4>; - #clock-cells = <2>; - }; - - l3_clkctrl: l3-clkctrl@24 { - compatible = "ti,clkctrl"; - reg = <0x24 0xc>, <0x94 0x10>, <0xbc 0x4>, <0xdc 0x8>, <0xfc 0x8>; - #clock-cells = <2>; - }; - - l4hs_clkctrl: l4hs-clkctrl@120 { - compatible = "ti,clkctrl"; - reg = <0x120 0x4>; - #clock-cells = <2>; - }; - - pruss_ocp_clkctrl: pruss-ocp-clkctrl@e8 { - compatible = "ti,clkctrl"; - reg = <0xe8 0x4>; - #clock-cells = <2>; - }; - - cpsw_125mhz_clkctrl: cpsw-125mhz-clkctrl@0 { - compatible = "ti,clkctrl"; - reg = <0x0 0x18>; - #clock-cells = <2>; - }; - - lcdc_clkctrl: lcdc-clkctrl@18 { - compatible = "ti,clkctrl"; - reg = <0x18 0x4>; - #clock-cells = <2>; - }; - - clk_24mhz_clkctrl: clk-24mhz-clkctrl@14c { - compatible = "ti,clkctrl"; - reg = <0x14c 0x4>; - #clock-cells = <2>; - }; - }; - - wkup_cm: wkup-cm@400 { - compatible = "ti,omap4-cm"; - reg = <0x400 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x400 0x100>; - - l4_wkup_clkctrl: l4-wkup-clkctrl@0 { - compatible = "ti,clkctrl"; - reg = <0x0 0x10>, <0xb4 0x24>; - #clock-cells = <2>; - }; - - l3_aon_clkctrl: l3-aon-clkctrl@14 { - compatible = "ti,clkctrl"; - reg = <0x14 0x4>; - #clock-cells = <2>; - }; - - l4_wkup_aon_clkctrl: l4-wkup-aon-clkctrl@b0 { - compatible = "ti,clkctrl"; - reg = <0xb0 0x4>; - #clock-cells = <2>; - }; - }; - - mpu_cm: mpu-cm@600 { - compatible = "ti,omap4-cm"; - reg = <0x600 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x600 0x100>; - - mpu_clkctrl: mpu-clkctrl@0 { - compatible = "ti,clkctrl"; - reg = <0x0 0x8>; - #clock-cells = <2>; - }; - }; - - l4_rtc_cm: l4-rtc-cm@800 { - compatible = "ti,omap4-cm"; - reg = <0x800 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x800 0x100>; - - l4_rtc_clkctrl: l4-rtc-clkctrl@0 { - compatible = "ti,clkctrl"; - reg = <0x0 0x4>; - #clock-cells = <2>; - }; - }; - - gfx_l3_cm: gfx-l3-cm@900 { - compatible = "ti,omap4-cm"; - reg = <0x900 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x900 0x100>; - - gfx_l3_clkctrl: gfx-l3-clkctrl@0 { - compatible = "ti,clkctrl"; - reg = <0x0 0x8>; - #clock-cells = <2>; - }; - }; - - l4_cefuse_cm: l4-cefuse-cm@a00 { - compatible = "ti,omap4-cm"; - reg = <0xa00 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0xa00 0x100>; - - l4_cefuse_clkctrl: l4-cefuse-clkctrl@0 { - compatible = "ti,clkctrl"; - reg = <0x0 0x24>; - #clock-cells = <2>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/am33xx-l4.dtsi b/sys/gnu/dts/arm/am33xx-l4.dtsi deleted file mode 100644 index 7a9eb2b0d45..00000000000 --- a/sys/gnu/dts/arm/am33xx-l4.dtsi +++ /dev/null @@ -1,2135 +0,0 @@ -&l4_wkup { /* 0x44c00000 */ - compatible = "ti,am33xx-l4-wkup", "simple-bus"; - reg = <0x44c00000 0x800>, - <0x44c00800 0x800>, - <0x44c01000 0x400>, - <0x44c01400 0x400>; - reg-names = "ap", "la", "ia0", "ia1"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x44c00000 0x100000>, /* segment 0 */ - <0x00100000 0x44d00000 0x100000>, /* segment 1 */ - <0x00200000 0x44e00000 0x100000>; /* segment 2 */ - - segment@0 { /* 0x44c00000 */ - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ - <0x00000800 0x00000800 0x000800>, /* ap 1 */ - <0x00001000 0x00001000 0x000400>, /* ap 2 */ - <0x00001400 0x00001400 0x000400>; /* ap 3 */ - }; - - segment@100000 { /* 0x44d00000 */ - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00100000 0x004000>, /* ap 4 */ - <0x00004000 0x00104000 0x001000>, /* ap 5 */ - <0x00080000 0x00180000 0x002000>, /* ap 6 */ - <0x00082000 0x00182000 0x001000>; /* ap 7 */ - - target-module@0 { /* 0x44d00000, ap 4 28.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x0 0x4>; - reg-names = "rev"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x4000>; - status = "disabled"; - }; - - target-module@80000 { /* 0x44d80000, ap 6 10.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x80000 0x2000>; - }; - }; - - segment@200000 { /* 0x44e00000 */ - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00200000 0x002000>, /* ap 8 */ - <0x00002000 0x00202000 0x001000>, /* ap 9 */ - <0x00003000 0x00203000 0x001000>, /* ap 10 */ - <0x00004000 0x00204000 0x001000>, /* ap 11 */ - <0x00005000 0x00205000 0x001000>, /* ap 12 */ - <0x00006000 0x00206000 0x001000>, /* ap 13 */ - <0x00007000 0x00207000 0x001000>, /* ap 14 */ - <0x00008000 0x00208000 0x001000>, /* ap 15 */ - <0x00009000 0x00209000 0x001000>, /* ap 16 */ - <0x0000a000 0x0020a000 0x001000>, /* ap 17 */ - <0x0000b000 0x0020b000 0x001000>, /* ap 18 */ - <0x0000c000 0x0020c000 0x001000>, /* ap 19 */ - <0x0000d000 0x0020d000 0x001000>, /* ap 20 */ - <0x0000f000 0x0020f000 0x001000>, /* ap 21 */ - <0x00010000 0x00210000 0x010000>, /* ap 22 */ - <0x00020000 0x00220000 0x010000>, /* ap 23 */ - <0x00030000 0x00230000 0x001000>, /* ap 24 */ - <0x00031000 0x00231000 0x001000>, /* ap 25 */ - <0x00032000 0x00232000 0x001000>, /* ap 26 */ - <0x00033000 0x00233000 0x001000>, /* ap 27 */ - <0x00034000 0x00234000 0x001000>, /* ap 28 */ - <0x00035000 0x00235000 0x001000>, /* ap 29 */ - <0x00036000 0x00236000 0x001000>, /* ap 30 */ - <0x00037000 0x00237000 0x001000>, /* ap 31 */ - <0x00038000 0x00238000 0x001000>, /* ap 32 */ - <0x00039000 0x00239000 0x001000>, /* ap 33 */ - <0x0003a000 0x0023a000 0x001000>, /* ap 34 */ - <0x0003e000 0x0023e000 0x001000>, /* ap 35 */ - <0x0003f000 0x0023f000 0x001000>, /* ap 36 */ - <0x0000e000 0x0020e000 0x001000>, /* ap 37 */ - <0x00040000 0x00240000 0x040000>, /* ap 38 */ - <0x00080000 0x00280000 0x001000>; /* ap 39 */ - - target-module@0 { /* 0x44e00000, ap 8 58.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0 0x4>; - reg-names = "rev"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x2000>; - - prcm: prcm@0 { - compatible = "ti,am3-prcm", "simple-bus"; - reg = <0 0x2000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x2000>; - - prcm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - prcm_clockdomains: clockdomains { - }; - }; - }; - - target-module@3000 { /* 0x44e03000, ap 10 0a.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x3000 0x1000>; - }; - - target-module@5000 { /* 0x44e05000, ap 12 30.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x5000 0x1000>; - }; - - gpio0_target: target-module@7000 { /* 0x44e07000, ap 14 20.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "gpio1"; - reg = <0x7000 0x4>, - <0x7010 0x4>, - <0x7114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ - clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_GPIO1_CLKCTRL 0>, - <&l4_wkup_clkctrl AM3_L4_WKUP_GPIO1_CLKCTRL 18>; - clock-names = "fck", "dbclk"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x7000 0x1000>; - - gpio0: gpio@0 { - compatible = "ti,omap4-gpio"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x0 0x1000>; - interrupts = <96>; - }; - }; - - target-module@9000 { /* 0x44e09000, ap 16 04.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "uart1"; - reg = <0x9050 0x4>, - <0x9054 0x4>, - <0x9058 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ - clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_UART1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x9000 0x1000>; - - uart0: serial@0 { - compatible = "ti,am3352-uart", "ti,omap3-uart"; - clock-frequency = <48000000>; - reg = <0x0 0x1000>; - interrupts = <72>; - status = "disabled"; - dmas = <&edma 26 0>, <&edma 27 0>; - dma-names = "tx", "rx"; - }; - }; - - target-module@b000 { /* 0x44e0b000, ap 18 48.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "i2c1"; - reg = <0xb000 0x8>, - <0xb010 0x8>, - <0xb090 0x8>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ - clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_I2C1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xb000 0x1000>; - - i2c0: i2c@0 { - compatible = "ti,omap4-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x1000>; - interrupts = <70>; - status = "disabled"; - }; - }; - - target-module@d000 { /* 0x44e0d000, ap 20 38.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - ti,hwmods = "adc_tsc"; - reg = <0xd000 0x4>, - <0xd010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ - clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_ADC_TSC_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x0000d000 0x00001000>, - <0x00001000 0x0000e000 0x00001000>; - - tscadc: tscadc@0 { - compatible = "ti,am3359-tscadc"; - reg = <0x0 0x1000>; - interrupts = <16>; - status = "disabled"; - dmas = <&edma 53 0>, <&edma 57 0>; - dma-names = "fifo0", "fifo1"; - - tsc { - compatible = "ti,am3359-tsc"; - }; - am335x_adc: adc { - #io-channel-cells = <1>; - compatible = "ti,am3359-adc"; - }; - }; - }; - - target-module@10000 { /* 0x44e10000, ap 22 0c.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x10000 0x4>; - reg-names = "rev"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00010000 0x00010000>, - <0x00010000 0x00020000 0x00010000>; - - scm: scm@0 { - compatible = "ti,am3-scm", "simple-bus"; - reg = <0x0 0x2000>; - #address-cells = <1>; - #size-cells = <1>; - #pinctrl-cells = <1>; - ranges = <0 0 0x2000>; - - am33xx_pinmux: pinmux@800 { - compatible = "pinctrl-single"; - reg = <0x800 0x238>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0x7f>; - }; - - scm_conf: scm_conf@0 { - compatible = "syscon", "simple-bus"; - reg = <0x0 0x800>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x800>; - - phy_gmii_sel: phy-gmii-sel { - compatible = "ti,am3352-phy-gmii-sel"; - reg = <0x650 0x4>; - #phy-cells = <2>; - }; - - scm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - wkup_m3_ipc: wkup_m3_ipc@1324 { - compatible = "ti,am3352-wkup-m3-ipc"; - reg = <0x1324 0x24>; - interrupts = <78>; - ti,rproc = <&wkup_m3>; - mboxes = <&mailbox &mbox_wkupm3>; - }; - - edma_xbar: dma-router@f90 { - compatible = "ti,am335x-edma-crossbar"; - reg = <0xf90 0x40>; - #dma-cells = <3>; - dma-requests = <32>; - dma-masters = <&edma>; - }; - - scm_clockdomains: clockdomains { - }; - }; - }; - - target-module@31000 { /* 0x44e31000, ap 25 40.0 */ - compatible = "ti,sysc-omap2-timer", "ti,sysc"; - ti,hwmods = "timer1"; - reg = <0x31000 0x4>, - <0x31010 0x4>, - <0x31014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ - clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_TIMER1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x31000 0x1000>; - - timer1: timer@0 { - compatible = "ti,am335x-timer-1ms"; - reg = <0x0 0x400>; - interrupts = <67>; - ti,timer-alwon; - clocks = <&timer1_fck>; - clock-names = "fck"; - }; - }; - - target-module@33000 { /* 0x44e33000, ap 27 18.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x33000 0x1000>; - }; - - target-module@35000 { /* 0x44e35000, ap 29 50.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "wd_timer2"; - reg = <0x35000 0x4>, - <0x35010 0x4>, - <0x35014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_EMUFREE | - SYSC_OMAP2_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ - clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_WD_TIMER2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x35000 0x1000>; - - wdt2: wdt@0 { - compatible = "ti,omap3-wdt"; - reg = <0x0 0x1000>; - interrupts = <91>; - }; - }; - - target-module@37000 { /* 0x44e37000, ap 31 08.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x37000 0x1000>; - }; - - target-module@39000 { /* 0x44e39000, ap 33 02.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x39000 0x1000>; - }; - - target-module@3e000 { /* 0x44e3e000, ap 35 60.0 */ - compatible = "ti,sysc-omap4-simple", "ti,sysc"; - ti,hwmods = "rtc"; - reg = <0x3e074 0x4>, - <0x3e078 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): rtc_pwrdm, l4_rtc_clkdm */ - clocks = <&l4_rtc_clkctrl AM3_L4_RTC_RTC_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x3e000 0x1000>; - - rtc: rtc@0 { - compatible = "ti,am3352-rtc", "ti,da830-rtc"; - reg = <0x0 0x1000>; - interrupts = <75 - 76>; - }; - }; - - target-module@40000 { /* 0x44e40000, ap 38 68.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x40000 0x40000>; - }; - }; -}; - -&l4_fw { /* 0x47c00000 */ - compatible = "ti,am33xx-l4-fw", "simple-bus"; - reg = <0x47c00000 0x800>, - <0x47c00800 0x800>, - <0x47c01000 0x400>; - reg-names = "ap", "la", "ia0"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x47c00000 0x1000000>; /* segment 0 */ - - segment@0 { /* 0x47c00000 */ - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ - <0x00000800 0x00000800 0x000800>, /* ap 1 */ - <0x00001000 0x00001000 0x000400>, /* ap 2 */ - <0x0000c000 0x0000c000 0x001000>, /* ap 3 */ - <0x0000d000 0x0000d000 0x001000>, /* ap 4 */ - <0x0000e000 0x0000e000 0x001000>, /* ap 5 */ - <0x0000f000 0x0000f000 0x001000>, /* ap 6 */ - <0x00010000 0x00010000 0x001000>, /* ap 7 */ - <0x00011000 0x00011000 0x001000>, /* ap 8 */ - <0x0001a000 0x0001a000 0x001000>, /* ap 9 */ - <0x0001b000 0x0001b000 0x001000>, /* ap 10 */ - <0x00024000 0x00024000 0x001000>, /* ap 11 */ - <0x00025000 0x00025000 0x001000>, /* ap 12 */ - <0x00026000 0x00026000 0x001000>, /* ap 13 */ - <0x00027000 0x00027000 0x001000>, /* ap 14 */ - <0x00030000 0x00030000 0x001000>, /* ap 15 */ - <0x00031000 0x00031000 0x001000>, /* ap 16 */ - <0x00038000 0x00038000 0x001000>, /* ap 17 */ - <0x00039000 0x00039000 0x001000>, /* ap 18 */ - <0x0003a000 0x0003a000 0x001000>, /* ap 19 */ - <0x0003b000 0x0003b000 0x001000>, /* ap 20 */ - <0x0003e000 0x0003e000 0x001000>, /* ap 21 */ - <0x0003f000 0x0003f000 0x001000>, /* ap 22 */ - <0x0003c000 0x0003c000 0x001000>, /* ap 23 */ - <0x00040000 0x00040000 0x001000>, /* ap 24 */ - <0x00046000 0x00046000 0x001000>, /* ap 25 */ - <0x00047000 0x00047000 0x001000>, /* ap 26 */ - <0x00044000 0x00044000 0x001000>, /* ap 27 */ - <0x00045000 0x00045000 0x001000>, /* ap 28 */ - <0x00028000 0x00028000 0x001000>, /* ap 29 */ - <0x00029000 0x00029000 0x001000>, /* ap 30 */ - <0x00032000 0x00032000 0x001000>, /* ap 31 */ - <0x00033000 0x00033000 0x001000>, /* ap 32 */ - <0x0003d000 0x0003d000 0x001000>, /* ap 33 */ - <0x00041000 0x00041000 0x001000>, /* ap 34 */ - <0x00042000 0x00042000 0x001000>, /* ap 35 */ - <0x00043000 0x00043000 0x001000>, /* ap 36 */ - <0x00014000 0x00014000 0x001000>, /* ap 37 */ - <0x00015000 0x00015000 0x001000>; /* ap 38 */ - - target-module@c000 { /* 0x47c0c000, ap 3 04.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xc000 0x1000>; - }; - - target-module@e000 { /* 0x47c0e000, ap 5 0c.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xe000 0x1000>; - }; - - target-module@10000 { /* 0x47c10000, ap 7 20.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x10000 0x1000>; - }; - - target-module@14000 { /* 0x47c14000, ap 37 3c.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x14000 0x1000>; - }; - - target-module@1a000 { /* 0x47c1a000, ap 9 08.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x1a000 0x1000>; - }; - - target-module@24000 { /* 0x47c24000, ap 11 28.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x24000 0x1000>; - }; - - target-module@26000 { /* 0x47c26000, ap 13 30.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x26000 0x1000>; - }; - - target-module@28000 { /* 0x47c28000, ap 29 40.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x28000 0x1000>; - }; - - target-module@30000 { /* 0x47c30000, ap 15 14.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x30000 0x1000>; - }; - - target-module@32000 { /* 0x47c32000, ap 31 06.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x32000 0x1000>; - }; - - target-module@38000 { /* 0x47c38000, ap 17 18.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x38000 0x1000>; - }; - - target-module@3a000 { /* 0x47c3a000, ap 19 1c.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x3a000 0x1000>; - }; - - target-module@3c000 { /* 0x47c3c000, ap 23 38.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x3c000 0x1000>; - }; - - target-module@3e000 { /* 0x47c3e000, ap 21 10.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x3e000 0x1000>; - }; - - target-module@40000 { /* 0x47c40000, ap 24 02.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x40000 0x1000>; - }; - - target-module@42000 { /* 0x47c42000, ap 35 34.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x42000 0x1000>; - }; - - target-module@44000 { /* 0x47c44000, ap 27 24.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x44000 0x1000>; - }; - - target-module@46000 { /* 0x47c46000, ap 25 2c.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x46000 0x1000>; - }; - }; -}; - -&l4_fast { /* 0x4a000000 */ - compatible = "ti,am33xx-l4-fast", "simple-bus"; - reg = <0x4a000000 0x800>, - <0x4a000800 0x800>, - <0x4a001000 0x400>; - reg-names = "ap", "la", "ia0"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x4a000000 0x1000000>; /* segment 0 */ - - segment@0 { /* 0x4a000000 */ - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ - <0x00000800 0x00000800 0x000800>, /* ap 1 */ - <0x00001000 0x00001000 0x000400>, /* ap 2 */ - <0x00100000 0x00100000 0x008000>, /* ap 3 */ - <0x00108000 0x00108000 0x001000>, /* ap 4 */ - <0x00180000 0x00180000 0x020000>, /* ap 5 */ - <0x001a0000 0x001a0000 0x001000>, /* ap 6 */ - <0x00200000 0x00200000 0x080000>, /* ap 7 */ - <0x00280000 0x00280000 0x001000>, /* ap 8 */ - <0x00300000 0x00300000 0x080000>, /* ap 9 */ - <0x00380000 0x00380000 0x001000>; /* ap 10 */ - - target-module@100000 { /* 0x4a100000, ap 3 08.0 */ - compatible = "ti,sysc-omap4-simple", "ti,sysc"; - reg = <0x101200 0x4>, - <0x101208 0x4>, - <0x101204 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <0>; - ti,sysc-midle = , - ; - ti,sysc-sidle = , - ; - ti,syss-mask = <1>; - clocks = <&cpsw_125mhz_clkctrl AM3_CPSW_125MHZ_CPGMAC0_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x100000 0x8000>; - - mac: ethernet@0 { - compatible = "ti,am335x-cpsw","ti,cpsw"; - clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>; - clock-names = "fck", "cpts"; - cpdma_channels = <8>; - ale_entries = <1024>; - bd_ram_size = <0x2000>; - mac_control = <0x20>; - slaves = <2>; - active_slave = <0>; - cpts_clock_mult = <0x80000000>; - cpts_clock_shift = <29>; - reg = <0x0 0x800 - 0x1200 0x100>; - #address-cells = <1>; - #size-cells = <1>; - /* - * c0_rx_thresh_pend - * c0_rx_pend - * c0_tx_pend - * c0_misc_pend - */ - interrupts = <40 41 42 43>; - ranges = <0 0 0x8000>; - syscon = <&scm_conf>; - status = "disabled"; - - davinci_mdio: mdio@1000 { - compatible = "ti,cpsw-mdio","ti,davinci_mdio"; - clocks = <&cpsw_125mhz_clkctrl AM3_CPSW_125MHZ_CPGMAC0_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <0>; - bus_freq = <1000000>; - reg = <0x1000 0x100>; - status = "disabled"; - }; - - cpsw_emac0: slave@200 { - /* Filled in by U-Boot */ - mac-address = [ 00 00 00 00 00 00 ]; - phys = <&phy_gmii_sel 1 1>; - }; - - cpsw_emac1: slave@300 { - /* Filled in by U-Boot */ - mac-address = [ 00 00 00 00 00 00 ]; - phys = <&phy_gmii_sel 2 1>; - }; - }; - }; - - target-module@180000 { /* 0x4a180000, ap 5 10.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x180000 0x20000>; - }; - - target-module@200000 { /* 0x4a200000, ap 7 02.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x200000 0x80000>; - }; - - target-module@300000 { /* 0x4a300000, ap 9 04.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x300000 0x80000>; - }; - }; -}; - -&l4_mpuss { /* 0x4b140000 */ - compatible = "ti,am33xx-l4-mpuss", "simple-bus"; - reg = <0x4b144400 0x100>, - <0x4b144800 0x400>; - reg-names = "la", "ap"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x4b140000 0x008000>; /* segment 0 */ - - segment@0 { /* 0x4b140000 */ - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00004800 0x00004800 0x000400>, /* ap 0 */ - <0x00001000 0x00001000 0x001000>, /* ap 1 */ - <0x00002000 0x00002000 0x001000>, /* ap 2 */ - <0x00004000 0x00004000 0x000400>, /* ap 3 */ - <0x00005000 0x00005000 0x000400>, /* ap 4 */ - <0x00000000 0x00000000 0x001000>, /* ap 5 */ - <0x00003000 0x00003000 0x001000>, /* ap 6 */ - <0x00000800 0x00000800 0x000800>; /* ap 7 */ - - target-module@0 { /* 0x4b140000, ap 5 02.2 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00000000 0x00001000>, - <0x00001000 0x00001000 0x00001000>, - <0x00002000 0x00002000 0x00001000>; - }; - - target-module@3000 { /* 0x4b143000, ap 6 04.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x3000 0x1000>; - }; - }; -}; - -&l4_per { /* 0x48000000 */ - compatible = "ti,am33xx-l4-per", "simple-bus"; - reg = <0x48000000 0x800>, - <0x48000800 0x800>, - <0x48001000 0x400>, - <0x48001400 0x400>, - <0x48001800 0x400>, - <0x48001c00 0x400>; - reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x48000000 0x100000>, /* segment 0 */ - <0x00100000 0x48100000 0x100000>, /* segment 1 */ - <0x00200000 0x48200000 0x100000>, /* segment 2 */ - <0x00300000 0x48300000 0x100000>, /* segment 3 */ - <0x46000000 0x46000000 0x400000>, /* l3 data port */ - <0x46400000 0x46400000 0x400000>; /* l3 data port */ - - segment@0 { /* 0x48000000 */ - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ - <0x00000800 0x00000800 0x000800>, /* ap 1 */ - <0x00001000 0x00001000 0x000400>, /* ap 2 */ - <0x00001400 0x00001400 0x000400>, /* ap 3 */ - <0x00001800 0x00001800 0x000400>, /* ap 4 */ - <0x00001c00 0x00001c00 0x000400>, /* ap 5 */ - <0x00008000 0x00008000 0x001000>, /* ap 6 */ - <0x00009000 0x00009000 0x001000>, /* ap 7 */ - <0x00016000 0x00016000 0x001000>, /* ap 8 */ - <0x00017000 0x00017000 0x001000>, /* ap 9 */ - <0x00022000 0x00022000 0x001000>, /* ap 10 */ - <0x00023000 0x00023000 0x001000>, /* ap 11 */ - <0x00024000 0x00024000 0x001000>, /* ap 12 */ - <0x00025000 0x00025000 0x001000>, /* ap 13 */ - <0x0002a000 0x0002a000 0x001000>, /* ap 14 */ - <0x0002b000 0x0002b000 0x001000>, /* ap 15 */ - <0x00038000 0x00038000 0x002000>, /* ap 16 */ - <0x0003a000 0x0003a000 0x001000>, /* ap 17 */ - <0x00014000 0x00014000 0x001000>, /* ap 18 */ - <0x00015000 0x00015000 0x001000>, /* ap 19 */ - <0x0003c000 0x0003c000 0x002000>, /* ap 20 */ - <0x0003e000 0x0003e000 0x001000>, /* ap 21 */ - <0x00040000 0x00040000 0x001000>, /* ap 22 */ - <0x00041000 0x00041000 0x001000>, /* ap 23 */ - <0x00042000 0x00042000 0x001000>, /* ap 24 */ - <0x00043000 0x00043000 0x001000>, /* ap 25 */ - <0x00044000 0x00044000 0x001000>, /* ap 26 */ - <0x00045000 0x00045000 0x001000>, /* ap 27 */ - <0x00046000 0x00046000 0x001000>, /* ap 28 */ - <0x00047000 0x00047000 0x001000>, /* ap 29 */ - <0x00048000 0x00048000 0x001000>, /* ap 30 */ - <0x00049000 0x00049000 0x001000>, /* ap 31 */ - <0x0004c000 0x0004c000 0x001000>, /* ap 32 */ - <0x0004d000 0x0004d000 0x001000>, /* ap 33 */ - <0x00050000 0x00050000 0x002000>, /* ap 34 */ - <0x00052000 0x00052000 0x001000>, /* ap 35 */ - <0x00060000 0x00060000 0x001000>, /* ap 36 */ - <0x00061000 0x00061000 0x001000>, /* ap 37 */ - <0x00080000 0x00080000 0x010000>, /* ap 38 */ - <0x00090000 0x00090000 0x001000>, /* ap 39 */ - <0x000a0000 0x000a0000 0x010000>, /* ap 40 */ - <0x000b0000 0x000b0000 0x001000>, /* ap 41 */ - <0x00030000 0x00030000 0x001000>, /* ap 77 */ - <0x00031000 0x00031000 0x001000>, /* ap 78 */ - <0x0004a000 0x0004a000 0x001000>, /* ap 85 */ - <0x0004b000 0x0004b000 0x001000>, /* ap 86 */ - <0x000c8000 0x000c8000 0x001000>, /* ap 87 */ - <0x000c9000 0x000c9000 0x001000>, /* ap 88 */ - <0x000cc000 0x000cc000 0x001000>, /* ap 89 */ - <0x000cd000 0x000cd000 0x001000>, /* ap 90 */ - <0x000ca000 0x000ca000 0x001000>, /* ap 91 */ - <0x000cb000 0x000cb000 0x001000>, /* ap 92 */ - <0x46000000 0x46000000 0x400000>, /* l3 data port */ - <0x46400000 0x46400000 0x400000>; /* l3 data port */ - - target-module@8000 { /* 0x48008000, ap 6 10.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x8000 0x1000>; - }; - - target-module@14000 { /* 0x48014000, ap 18 58.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x14000 0x1000>; - }; - - target-module@16000 { /* 0x48016000, ap 8 3c.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x16000 0x1000>; - }; - - target-module@22000 { /* 0x48022000, ap 10 12.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "uart2"; - reg = <0x22050 0x4>, - <0x22054 0x4>, - <0x22058 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM3_L4LS_UART2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x22000 0x1000>; - - uart1: serial@0 { - compatible = "ti,am3352-uart", "ti,omap3-uart"; - clock-frequency = <48000000>; - reg = <0x0 0x1000>; - interrupts = <73>; - status = "disabled"; - dmas = <&edma 28 0>, <&edma 29 0>; - dma-names = "tx", "rx"; - }; - }; - - target-module@24000 { /* 0x48024000, ap 12 14.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "uart3"; - reg = <0x24050 0x4>, - <0x24054 0x4>, - <0x24058 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM3_L4LS_UART3_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x24000 0x1000>; - - uart2: serial@0 { - compatible = "ti,am3352-uart", "ti,omap3-uart"; - clock-frequency = <48000000>; - reg = <0x0 0x1000>; - interrupts = <74>; - status = "disabled"; - dmas = <&edma 30 0>, <&edma 31 0>; - dma-names = "tx", "rx"; - }; - }; - - target-module@2a000 { /* 0x4802a000, ap 14 2a.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "i2c2"; - reg = <0x2a000 0x8>, - <0x2a010 0x8>, - <0x2a090 0x8>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM3_L4LS_I2C2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2a000 0x1000>; - - i2c1: i2c@0 { - compatible = "ti,omap4-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x1000>; - interrupts = <71>; - status = "disabled"; - }; - }; - - target-module@30000 { /* 0x48030000, ap 77 08.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "spi0"; - reg = <0x30000 0x4>, - <0x30110 0x4>, - <0x30114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM3_L4LS_SPI0_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x30000 0x1000>; - - spi0: spi@0 { - compatible = "ti,omap4-mcspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x400>; - interrupts = <65>; - ti,spi-num-cs = <2>; - dmas = <&edma 16 0 - &edma 17 0 - &edma 18 0 - &edma 19 0>; - dma-names = "tx0", "rx0", "tx1", "rx1"; - status = "disabled"; - }; - }; - - target-module@38000 { /* 0x48038000, ap 16 02.0 */ - compatible = "ti,sysc-omap4-simple", "ti,sysc"; - ti,hwmods = "mcasp0"; - reg = <0x38000 0x4>, - <0x38004 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-sidle = , - , - ; - /* Domains (P, C): per_pwrdm, l3s_clkdm */ - clocks = <&l3s_clkctrl AM3_L3S_MCASP0_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x38000 0x2000>, - <0x46000000 0x46000000 0x400000>; - - mcasp0: mcasp@0 { - compatible = "ti,am33xx-mcasp-audio"; - reg = <0x0 0x2000>, - <0x46000000 0x400000>; - reg-names = "mpu", "dat"; - interrupts = <80>, <81>; - interrupt-names = "tx", "rx"; - status = "disabled"; - dmas = <&edma 8 2>, - <&edma 9 2>; - dma-names = "tx", "rx"; - }; - }; - - target-module@3c000 { /* 0x4803c000, ap 20 32.0 */ - compatible = "ti,sysc-omap4-simple", "ti,sysc"; - ti,hwmods = "mcasp1"; - reg = <0x3c000 0x4>, - <0x3c004 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-sidle = , - , - ; - /* Domains (P, C): per_pwrdm, l3s_clkdm */ - clocks = <&l3s_clkctrl AM3_L3S_MCASP1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x3c000 0x2000>, - <0x46400000 0x46400000 0x400000>; - - mcasp1: mcasp@0 { - compatible = "ti,am33xx-mcasp-audio"; - reg = <0x0 0x2000>, - <0x46400000 0x400000>; - reg-names = "mpu", "dat"; - interrupts = <82>, <83>; - interrupt-names = "tx", "rx"; - status = "disabled"; - dmas = <&edma 10 2>, - <&edma 11 2>; - dma-names = "tx", "rx"; - }; - }; - - target-module@40000 { /* 0x48040000, ap 22 1e.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - ti,hwmods = "timer2"; - reg = <0x40000 0x4>, - <0x40010 0x4>, - <0x40014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM3_L4LS_TIMER2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x40000 0x1000>; - - timer2: timer@0 { - compatible = "ti,am335x-timer"; - reg = <0x0 0x400>; - interrupts = <68>; - clocks = <&timer2_fck>; - clock-names = "fck"; - }; - }; - - target-module@42000 { /* 0x48042000, ap 24 1c.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - ti,hwmods = "timer3"; - reg = <0x42000 0x4>, - <0x42010 0x4>, - <0x42014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM3_L4LS_TIMER3_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x42000 0x1000>; - - timer3: timer@0 { - compatible = "ti,am335x-timer"; - reg = <0x0 0x400>; - interrupts = <69>; - }; - }; - - target-module@44000 { /* 0x48044000, ap 26 26.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - ti,hwmods = "timer4"; - reg = <0x44000 0x4>, - <0x44010 0x4>, - <0x44014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM3_L4LS_TIMER4_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x44000 0x1000>; - - timer4: timer@0 { - compatible = "ti,am335x-timer"; - reg = <0x0 0x400>; - interrupts = <92>; - ti,timer-pwm; - }; - }; - - target-module@46000 { /* 0x48046000, ap 28 28.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - ti,hwmods = "timer5"; - reg = <0x46000 0x4>, - <0x46010 0x4>, - <0x46014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM3_L4LS_TIMER5_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x46000 0x1000>; - - timer5: timer@0 { - compatible = "ti,am335x-timer"; - reg = <0x0 0x400>; - interrupts = <93>; - ti,timer-pwm; - }; - }; - - target-module@48000 { /* 0x48048000, ap 30 22.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - ti,hwmods = "timer6"; - reg = <0x48000 0x4>, - <0x48010 0x4>, - <0x48014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM3_L4LS_TIMER6_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x48000 0x1000>; - - timer6: timer@0 { - compatible = "ti,am335x-timer"; - reg = <0x0 0x400>; - interrupts = <94>; - ti,timer-pwm; - }; - }; - - target-module@4a000 { /* 0x4804a000, ap 85 60.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - ti,hwmods = "timer7"; - reg = <0x4a000 0x4>, - <0x4a010 0x4>, - <0x4a014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM3_L4LS_TIMER7_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x4a000 0x1000>; - - timer7: timer@0 { - compatible = "ti,am335x-timer"; - reg = <0x0 0x400>; - interrupts = <95>; - ti,timer-pwm; - }; - }; - - target-module@4c000 { /* 0x4804c000, ap 32 36.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "gpio2"; - reg = <0x4c000 0x4>, - <0x4c010 0x4>, - <0x4c114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM3_L4LS_GPIO2_CLKCTRL 0>, - <&l4ls_clkctrl AM3_L4LS_GPIO2_CLKCTRL 18>; - clock-names = "fck", "dbclk"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x4c000 0x1000>; - - gpio1: gpio@0 { - compatible = "ti,omap4-gpio"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x0 0x1000>; - interrupts = <98>; - }; - }; - - target-module@50000 { /* 0x48050000, ap 34 2c.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x50000 0x2000>; - }; - - target-module@60000 { /* 0x48060000, ap 36 0c.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "mmc1"; - reg = <0x602fc 0x4>, - <0x60110 0x4>, - <0x60114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM3_L4LS_MMC1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x60000 0x1000>; - - mmc1: mmc@0 { - compatible = "ti,omap4-hsmmc"; - ti,dual-volt; - ti,needs-special-reset; - ti,needs-special-hs-handling; - dmas = <&edma_xbar 24 0 0 - &edma_xbar 25 0 0>; - dma-names = "tx", "rx"; - interrupts = <64>; - reg = <0x0 0x1000>; - status = "disabled"; - }; - }; - - target-module@80000 { /* 0x48080000, ap 38 18.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "elm"; - reg = <0x80000 0x4>, - <0x80010 0x4>, - <0x80014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM3_L4LS_ELM_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x80000 0x10000>; - - elm: elm@0 { - compatible = "ti,am3352-elm"; - reg = <0x0 0x2000>; - interrupts = <4>; - status = "disabled"; - }; - }; - - target-module@a0000 { /* 0x480a0000, ap 40 5e.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xa0000 0x10000>; - }; - - target-module@c8000 { /* 0x480c8000, ap 87 06.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - ti,hwmods = "mailbox"; - reg = <0xc8000 0x4>, - <0xc8010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - ; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM3_L4LS_MAILBOX_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xc8000 0x1000>; - - mailbox: mailbox@0 { - compatible = "ti,omap4-mailbox"; - reg = <0x0 0x200>; - interrupts = <77>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <8>; - mbox_wkupm3: wkup_m3 { - ti,mbox-send-noirq; - ti,mbox-tx = <0 0 0>; - ti,mbox-rx = <0 0 3>; - }; - }; - }; - - target-module@ca000 { /* 0x480ca000, ap 91 40.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "spinlock"; - reg = <0xca000 0x4>, - <0xca010 0x4>, - <0xca014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM3_L4LS_SPINLOCK_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xca000 0x1000>; - - hwspinlock: spinlock@0 { - compatible = "ti,omap4-hwspinlock"; - reg = <0x0 0x1000>; - #hwlock-cells = <1>; - }; - }; - - target-module@cc000 { /* 0x480cc000, ap 89 0e.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xcc000 0x1000>; - }; - }; - - segment@100000 { /* 0x48100000 */ - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0008c000 0x0018c000 0x001000>, /* ap 42 */ - <0x0008d000 0x0018d000 0x001000>, /* ap 43 */ - <0x0008e000 0x0018e000 0x001000>, /* ap 44 */ - <0x0008f000 0x0018f000 0x001000>, /* ap 45 */ - <0x0009c000 0x0019c000 0x001000>, /* ap 46 */ - <0x0009d000 0x0019d000 0x001000>, /* ap 47 */ - <0x000a6000 0x001a6000 0x001000>, /* ap 48 */ - <0x000a7000 0x001a7000 0x001000>, /* ap 49 */ - <0x000a8000 0x001a8000 0x001000>, /* ap 50 */ - <0x000a9000 0x001a9000 0x001000>, /* ap 51 */ - <0x000aa000 0x001aa000 0x001000>, /* ap 52 */ - <0x000ab000 0x001ab000 0x001000>, /* ap 53 */ - <0x000ac000 0x001ac000 0x001000>, /* ap 54 */ - <0x000ad000 0x001ad000 0x001000>, /* ap 55 */ - <0x000ae000 0x001ae000 0x001000>, /* ap 56 */ - <0x000af000 0x001af000 0x001000>, /* ap 57 */ - <0x000b0000 0x001b0000 0x010000>, /* ap 58 */ - <0x000c0000 0x001c0000 0x001000>, /* ap 59 */ - <0x000cc000 0x001cc000 0x002000>, /* ap 60 */ - <0x000ce000 0x001ce000 0x002000>, /* ap 61 */ - <0x000d0000 0x001d0000 0x002000>, /* ap 62 */ - <0x000d2000 0x001d2000 0x002000>, /* ap 63 */ - <0x000d8000 0x001d8000 0x001000>, /* ap 64 */ - <0x000d9000 0x001d9000 0x001000>, /* ap 65 */ - <0x000a0000 0x001a0000 0x001000>, /* ap 79 */ - <0x000a1000 0x001a1000 0x001000>, /* ap 80 */ - <0x000a2000 0x001a2000 0x001000>, /* ap 81 */ - <0x000a3000 0x001a3000 0x001000>, /* ap 82 */ - <0x000a4000 0x001a4000 0x001000>, /* ap 83 */ - <0x000a5000 0x001a5000 0x001000>; /* ap 84 */ - - target-module@8c000 { /* 0x4818c000, ap 42 04.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x8c000 0x1000>; - }; - - target-module@8e000 { /* 0x4818e000, ap 44 0a.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x8e000 0x1000>; - }; - - target-module@9c000 { /* 0x4819c000, ap 46 5a.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "i2c3"; - reg = <0x9c000 0x8>, - <0x9c010 0x8>, - <0x9c090 0x8>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM3_L4LS_I2C3_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x9c000 0x1000>; - - i2c2: i2c@0 { - compatible = "ti,omap4-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x1000>; - interrupts = <30>; - status = "disabled"; - }; - }; - - target-module@a0000 { /* 0x481a0000, ap 79 24.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "spi1"; - reg = <0xa0000 0x4>, - <0xa0110 0x4>, - <0xa0114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM3_L4LS_SPI1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xa0000 0x1000>; - - spi1: spi@0 { - compatible = "ti,omap4-mcspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x400>; - interrupts = <125>; - ti,spi-num-cs = <2>; - dmas = <&edma 42 0 - &edma 43 0 - &edma 44 0 - &edma 45 0>; - dma-names = "tx0", "rx0", "tx1", "rx1"; - status = "disabled"; - }; - }; - - target-module@a2000 { /* 0x481a2000, ap 81 2e.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xa2000 0x1000>; - }; - - target-module@a4000 { /* 0x481a4000, ap 83 30.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xa4000 0x1000>; - }; - - target-module@a6000 { /* 0x481a6000, ap 48 16.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "uart4"; - reg = <0xa6050 0x4>, - <0xa6054 0x4>, - <0xa6058 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM3_L4LS_UART4_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xa6000 0x1000>; - - uart3: serial@0 { - compatible = "ti,am3352-uart", "ti,omap3-uart"; - clock-frequency = <48000000>; - reg = <0x0 0x1000>; - interrupts = <44>; - status = "disabled"; - }; - }; - - target-module@a8000 { /* 0x481a8000, ap 50 20.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "uart5"; - reg = <0xa8050 0x4>, - <0xa8054 0x4>, - <0xa8058 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM3_L4LS_UART5_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xa8000 0x1000>; - - uart4: serial@0 { - compatible = "ti,am3352-uart", "ti,omap3-uart"; - clock-frequency = <48000000>; - reg = <0x0 0x1000>; - interrupts = <45>; - status = "disabled"; - }; - }; - - target-module@aa000 { /* 0x481aa000, ap 52 1a.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "uart6"; - reg = <0xaa050 0x4>, - <0xaa054 0x4>, - <0xaa058 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM3_L4LS_UART6_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xaa000 0x1000>; - - uart5: serial@0 { - compatible = "ti,am3352-uart", "ti,omap3-uart"; - clock-frequency = <48000000>; - reg = <0x0 0x1000>; - interrupts = <46>; - status = "disabled"; - }; - }; - - target-module@ac000 { /* 0x481ac000, ap 54 38.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "gpio3"; - reg = <0xac000 0x4>, - <0xac010 0x4>, - <0xac114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM3_L4LS_GPIO3_CLKCTRL 0>, - <&l4ls_clkctrl AM3_L4LS_GPIO3_CLKCTRL 18>; - clock-names = "fck", "dbclk"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xac000 0x1000>; - - gpio2: gpio@0 { - compatible = "ti,omap4-gpio"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x0 0x1000>; - interrupts = <32>; - }; - }; - - target-module@ae000 { /* 0x481ae000, ap 56 3a.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "gpio4"; - reg = <0xae000 0x4>, - <0xae010 0x4>, - <0xae114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM3_L4LS_GPIO4_CLKCTRL 0>, - <&l4ls_clkctrl AM3_L4LS_GPIO4_CLKCTRL 18>; - clock-names = "fck", "dbclk"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xae000 0x1000>; - - gpio3: gpio@0 { - compatible = "ti,omap4-gpio"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x0 0x1000>; - interrupts = <62>; - }; - }; - - target-module@b0000 { /* 0x481b0000, ap 58 50.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xb0000 0x10000>; - }; - - target-module@cc000 { /* 0x481cc000, ap 60 46.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0xcc020 0x4>; - reg-names = "rev"; - ti,hwmods = "d_can0"; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM3_L4LS_D_CAN0_CLKCTRL 0>, - <&dcan0_fck>; - clock-names = "fck", "osc"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xcc000 0x2000>; - - dcan0: can@0 { - compatible = "ti,am3352-d_can"; - reg = <0x0 0x2000>; - clocks = <&dcan0_fck>; - clock-names = "fck"; - syscon-raminit = <&scm_conf 0x644 0>; - interrupts = <52>; - status = "disabled"; - }; - }; - - target-module@d0000 { /* 0x481d0000, ap 62 42.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0xd0020 0x4>; - reg-names = "rev"; - ti,hwmods = "d_can1"; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM3_L4LS_D_CAN1_CLKCTRL 0>, - <&dcan1_fck>; - clock-names = "fck", "osc"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xd0000 0x2000>; - - dcan1: can@0 { - compatible = "ti,am3352-d_can"; - reg = <0x0 0x2000>; - clocks = <&dcan1_fck>; - clock-names = "fck"; - syscon-raminit = <&scm_conf 0x644 1>; - interrupts = <55>; - status = "disabled"; - }; - }; - - target-module@d8000 { /* 0x481d8000, ap 64 66.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "mmc2"; - reg = <0xd82fc 0x4>, - <0xd8110 0x4>, - <0xd8114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM3_L4LS_MMC2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xd8000 0x1000>; - - mmc2: mmc@0 { - compatible = "ti,omap4-hsmmc"; - ti,needs-special-reset; - dmas = <&edma 2 0 - &edma 3 0>; - dma-names = "tx", "rx"; - interrupts = <28>; - reg = <0x0 0x1000>; - status = "disabled"; - }; - }; - }; - - segment@200000 { /* 0x48200000 */ - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - }; - - segment@300000 { /* 0x48300000 */ - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00300000 0x001000>, /* ap 66 */ - <0x00001000 0x00301000 0x001000>, /* ap 67 */ - <0x00002000 0x00302000 0x001000>, /* ap 68 */ - <0x00003000 0x00303000 0x001000>, /* ap 69 */ - <0x00004000 0x00304000 0x001000>, /* ap 70 */ - <0x00005000 0x00305000 0x001000>, /* ap 71 */ - <0x0000e000 0x0030e000 0x001000>, /* ap 72 */ - <0x0000f000 0x0030f000 0x001000>, /* ap 73 */ - <0x00018000 0x00318000 0x004000>, /* ap 74 */ - <0x0001c000 0x0031c000 0x001000>, /* ap 75 */ - <0x00010000 0x00310000 0x002000>, /* ap 76 */ - <0x00012000 0x00312000 0x001000>, /* ap 93 */ - <0x00015000 0x00315000 0x001000>, /* ap 94 */ - <0x00016000 0x00316000 0x001000>, /* ap 95 */ - <0x00017000 0x00317000 0x001000>, /* ap 96 */ - <0x00013000 0x00313000 0x001000>, /* ap 97 */ - <0x00014000 0x00314000 0x001000>, /* ap 98 */ - <0x00020000 0x00320000 0x001000>, /* ap 99 */ - <0x00021000 0x00321000 0x001000>, /* ap 100 */ - <0x00022000 0x00322000 0x001000>, /* ap 101 */ - <0x00023000 0x00323000 0x001000>, /* ap 102 */ - <0x00024000 0x00324000 0x001000>, /* ap 103 */ - <0x00025000 0x00325000 0x001000>; /* ap 104 */ - - target-module@0 { /* 0x48300000, ap 66 48.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - ti,hwmods = "epwmss0"; - reg = <0x0 0x4>, - <0x4 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-midle = , - , - , - ; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM3_L4LS_EPWMSS0_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x1000>; - - epwmss0: epwmss@0 { - compatible = "ti,am33xx-pwmss"; - reg = <0x0 0x10>; - #address-cells = <1>; - #size-cells = <1>; - status = "disabled"; - ranges = <0 0 0x1000>; - - ecap0: ecap@100 { - compatible = "ti,am3352-ecap", - "ti,am33xx-ecap"; - #pwm-cells = <3>; - reg = <0x100 0x80>; - clocks = <&l4ls_gclk>; - clock-names = "fck"; - interrupts = <31>; - interrupt-names = "ecap0"; - status = "disabled"; - }; - - ehrpwm0: pwm@200 { - compatible = "ti,am3352-ehrpwm", - "ti,am33xx-ehrpwm"; - #pwm-cells = <3>; - reg = <0x200 0x80>; - clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - }; - }; - - target-module@2000 { /* 0x48302000, ap 68 52.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - ti,hwmods = "epwmss1"; - reg = <0x2000 0x4>, - <0x2004 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-midle = , - , - , - ; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM3_L4LS_EPWMSS1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2000 0x1000>; - - epwmss1: epwmss@0 { - compatible = "ti,am33xx-pwmss"; - reg = <0x0 0x10>; - #address-cells = <1>; - #size-cells = <1>; - status = "disabled"; - ranges = <0 0 0x1000>; - - ecap1: ecap@100 { - compatible = "ti,am3352-ecap", - "ti,am33xx-ecap"; - #pwm-cells = <3>; - reg = <0x100 0x80>; - clocks = <&l4ls_gclk>; - clock-names = "fck"; - interrupts = <47>; - interrupt-names = "ecap1"; - status = "disabled"; - }; - - ehrpwm1: pwm@200 { - compatible = "ti,am3352-ehrpwm", - "ti,am33xx-ehrpwm"; - #pwm-cells = <3>; - reg = <0x200 0x80>; - clocks = <&ehrpwm1_tbclk>, <&l4ls_gclk>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - }; - }; - - target-module@4000 { /* 0x48304000, ap 70 44.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - ti,hwmods = "epwmss2"; - reg = <0x4000 0x4>, - <0x4004 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-midle = , - , - , - ; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM3_L4LS_EPWMSS2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x4000 0x1000>; - - epwmss2: epwmss@0 { - compatible = "ti,am33xx-pwmss"; - reg = <0x0 0x10>; - #address-cells = <1>; - #size-cells = <1>; - status = "disabled"; - ranges = <0 0 0x1000>; - - ecap2: ecap@100 { - compatible = "ti,am3352-ecap", - "ti,am33xx-ecap"; - #pwm-cells = <3>; - reg = <0x100 0x80>; - clocks = <&l4ls_gclk>; - clock-names = "fck"; - interrupts = <61>; - interrupt-names = "ecap2"; - status = "disabled"; - }; - - ehrpwm2: pwm@200 { - compatible = "ti,am3352-ehrpwm", - "ti,am33xx-ehrpwm"; - #pwm-cells = <3>; - reg = <0x200 0x80>; - clocks = <&ehrpwm2_tbclk>, <&l4ls_gclk>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - }; - }; - - target-module@e000 { /* 0x4830e000, ap 72 4a.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - ti,hwmods = "lcdc"; - reg = <0xe000 0x4>, - <0xe054 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-midle = , - , - ; - ti,sysc-sidle = , - , - ; - /* Domains (P, C): per_pwrdm, lcdc_clkdm */ - clocks = <&lcdc_clkctrl AM3_LCDC_LCDC_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xe000 0x1000>; - - lcdc: lcdc@0 { - compatible = "ti,am33xx-tilcdc"; - reg = <0x0 0x1000>; - interrupts = <36>; - status = "disabled"; - }; - }; - - target-module@10000 { /* 0x48310000, ap 76 4e.1 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "rng"; - reg = <0x11fe0 0x4>, - <0x11fe4 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = ; - ti,sysc-sidle = , - ; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM3_L4LS_RNG_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x10000 0x2000>; - - rng: rng@0 { - compatible = "ti,omap4-rng"; - reg = <0x0 0x2000>; - interrupts = <111>; - }; - }; - - target-module@13000 { /* 0x48313000, ap 97 62.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x13000 0x1000>; - }; - - target-module@15000 { /* 0x48315000, ap 94 56.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00015000 0x00001000>, - <0x00001000 0x00016000 0x00001000>; - }; - - target-module@18000 { /* 0x48318000, ap 74 4c.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x18000 0x4000>; - }; - - target-module@20000 { /* 0x48320000, ap 99 34.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x20000 0x1000>; - }; - - target-module@22000 { /* 0x48322000, ap 101 3e.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x22000 0x1000>; - }; - - target-module@24000 { /* 0x48324000, ap 103 68.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x24000 0x1000>; - }; - }; -}; - diff --git a/sys/gnu/dts/arm/am33xx.dtsi b/sys/gnu/dts/arm/am33xx.dtsi deleted file mode 100644 index b3a1fd9e39f..00000000000 --- a/sys/gnu/dts/arm/am33xx.dtsi +++ /dev/null @@ -1,468 +0,0 @@ -/* - * Device Tree Source for AM33XX SoC - * - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -#include -#include -#include -#include - -/ { - compatible = "ti,am33xx"; - interrupt-parent = <&intc>; - #address-cells = <1>; - #size-cells = <1>; - chosen { }; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - serial4 = &uart4; - serial5 = &uart5; - d-can0 = &dcan0; - d-can1 = &dcan1; - usb0 = &usb0; - usb1 = &usb1; - phy0 = &usb0_phy; - phy1 = &usb1_phy; - ethernet0 = &cpsw_emac0; - ethernet1 = &cpsw_emac1; - spi0 = &spi0; - spi1 = &spi1; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu@0 { - compatible = "arm,cortex-a8"; - device_type = "cpu"; - reg = <0>; - - operating-points-v2 = <&cpu0_opp_table>; - - clocks = <&dpll_mpu_ck>; - clock-names = "cpu"; - - clock-latency = <300000>; /* From omap-cpufreq driver */ - }; - }; - - cpu0_opp_table: opp-table { - compatible = "operating-points-v2-ti-cpu"; - syscon = <&scm_conf>; - - /* - * The three following nodes are marked with opp-suspend - * because the can not be enabled simultaneously on a - * single SoC. - */ - opp50-300000000 { - opp-hz = /bits/ 64 <300000000>; - opp-microvolt = <950000 931000 969000>; - opp-supported-hw = <0x06 0x0010>; - opp-suspend; - }; - - opp100-275000000 { - opp-hz = /bits/ 64 <275000000>; - opp-microvolt = <1100000 1078000 1122000>; - opp-supported-hw = <0x01 0x00FF>; - opp-suspend; - }; - - opp100-300000000 { - opp-hz = /bits/ 64 <300000000>; - opp-microvolt = <1100000 1078000 1122000>; - opp-supported-hw = <0x06 0x0020>; - opp-suspend; - }; - - opp100-500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <1100000 1078000 1122000>; - opp-supported-hw = <0x01 0xFFFF>; - }; - - opp100-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <1100000 1078000 1122000>; - opp-supported-hw = <0x06 0x0040>; - }; - - opp120-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <1200000 1176000 1224000>; - opp-supported-hw = <0x01 0xFFFF>; - }; - - opp120-720000000 { - opp-hz = /bits/ 64 <720000000>; - opp-microvolt = <1200000 1176000 1224000>; - opp-supported-hw = <0x06 0x0080>; - }; - - oppturbo-720000000 { - opp-hz = /bits/ 64 <720000000>; - opp-microvolt = <1260000 1234800 1285200>; - opp-supported-hw = <0x01 0xFFFF>; - }; - - oppturbo-800000000 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <1260000 1234800 1285200>; - opp-supported-hw = <0x06 0x0100>; - }; - - oppnitro-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <1325000 1298500 1351500>; - opp-supported-hw = <0x04 0x0200>; - }; - }; - - pmu@4b000000 { - compatible = "arm,cortex-a8-pmu"; - interrupts = <3>; - reg = <0x4b000000 0x1000000>; - ti,hwmods = "debugss"; - }; - - /* - * The soc node represents the soc top level view. It is used for IPs - * that are not memory mapped in the MPU view or for the MPU itself. - */ - soc { - compatible = "ti,omap-infra"; - mpu { - compatible = "ti,omap3-mpu"; - ti,hwmods = "mpu"; - pm-sram = <&pm_sram_code - &pm_sram_data>; - }; - }; - - /* - * XXX: Use a flat representation of the AM33XX interconnect. - * The real AM33XX interconnect network is quite complex. Since - * it will not bring real advantage to represent that in DT - * for the moment, just use a fake OCP bus entry to represent - * the whole bus hierarchy. - */ - ocp { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - ti,hwmods = "l3_main"; - - l4_wkup: interconnect@44c00000 { - wkup_m3: wkup_m3@100000 { - compatible = "ti,am3352-wkup-m3"; - reg = <0x100000 0x4000>, - <0x180000 0x2000>; - reg-names = "umem", "dmem"; - ti,hwmods = "wkup_m3"; - ti,pm-firmware = "am335x-pm-firmware.elf"; - }; - }; - l4_per: interconnect@48000000 { - }; - l4_fw: interconnect@47c00000 { - }; - l4_fast: interconnect@4a000000 { - }; - l4_mpuss: interconnect@4b140000 { - }; - - intc: interrupt-controller@48200000 { - compatible = "ti,am33xx-intc"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x48200000 0x1000>; - }; - - edma: edma@49000000 { - compatible = "ti,edma3-tpcc"; - ti,hwmods = "tpcc"; - reg = <0x49000000 0x10000>; - reg-names = "edma3_cc"; - interrupts = <12 13 14>; - interrupt-names = "edma3_ccint", "edma3_mperr", - "edma3_ccerrint"; - dma-requests = <64>; - #dma-cells = <2>; - - ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>, - <&edma_tptc2 0>; - - ti,edma-memcpy-channels = <20 21>; - }; - - edma_tptc0: tptc@49800000 { - compatible = "ti,edma3-tptc"; - ti,hwmods = "tptc0"; - reg = <0x49800000 0x100000>; - interrupts = <112>; - interrupt-names = "edma3_tcerrint"; - }; - - edma_tptc1: tptc@49900000 { - compatible = "ti,edma3-tptc"; - ti,hwmods = "tptc1"; - reg = <0x49900000 0x100000>; - interrupts = <113>; - interrupt-names = "edma3_tcerrint"; - }; - - edma_tptc2: tptc@49a00000 { - compatible = "ti,edma3-tptc"; - ti,hwmods = "tptc2"; - reg = <0x49a00000 0x100000>; - interrupts = <114>; - interrupt-names = "edma3_tcerrint"; - }; - - target-module@47810000 { - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "mmc3"; - reg = <0x478102fc 0x4>, - <0x47810110 0x4>, - <0x47810114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - clocks = <&l3s_clkctrl AM3_L3S_MMC3_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x47810000 0x1000>; - - mmc3: mmc@0 { - compatible = "ti,omap4-hsmmc"; - ti,needs-special-reset; - interrupts = <29>; - reg = <0x0 0x1000>; - status = "disabled"; - }; - }; - - usb: usb@47400000 { - compatible = "ti,am33xx-usb"; - reg = <0x47400000 0x1000>; - ranges; - #address-cells = <1>; - #size-cells = <1>; - ti,hwmods = "usb_otg_hs"; - status = "disabled"; - - usb_ctrl_mod: control@44e10620 { - compatible = "ti,am335x-usb-ctrl-module"; - reg = <0x44e10620 0x10 - 0x44e10648 0x4>; - reg-names = "phy_ctrl", "wakeup"; - status = "disabled"; - }; - - usb0_phy: usb-phy@47401300 { - compatible = "ti,am335x-usb-phy"; - reg = <0x47401300 0x100>; - reg-names = "phy"; - status = "disabled"; - ti,ctrl_mod = <&usb_ctrl_mod>; - #phy-cells = <0>; - }; - - usb0: usb@47401000 { - compatible = "ti,musb-am33xx"; - status = "disabled"; - reg = <0x47401400 0x400 - 0x47401000 0x200>; - reg-names = "mc", "control"; - - interrupts = <18>; - interrupt-names = "mc"; - dr_mode = "otg"; - mentor,multipoint = <1>; - mentor,num-eps = <16>; - mentor,ram-bits = <12>; - mentor,power = <500>; - phys = <&usb0_phy>; - - dmas = <&cppi41dma 0 0 &cppi41dma 1 0 - &cppi41dma 2 0 &cppi41dma 3 0 - &cppi41dma 4 0 &cppi41dma 5 0 - &cppi41dma 6 0 &cppi41dma 7 0 - &cppi41dma 8 0 &cppi41dma 9 0 - &cppi41dma 10 0 &cppi41dma 11 0 - &cppi41dma 12 0 &cppi41dma 13 0 - &cppi41dma 14 0 &cppi41dma 0 1 - &cppi41dma 1 1 &cppi41dma 2 1 - &cppi41dma 3 1 &cppi41dma 4 1 - &cppi41dma 5 1 &cppi41dma 6 1 - &cppi41dma 7 1 &cppi41dma 8 1 - &cppi41dma 9 1 &cppi41dma 10 1 - &cppi41dma 11 1 &cppi41dma 12 1 - &cppi41dma 13 1 &cppi41dma 14 1>; - dma-names = - "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7", - "rx8", "rx9", "rx10", "rx11", "rx12", "rx13", - "rx14", "rx15", - "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7", - "tx8", "tx9", "tx10", "tx11", "tx12", "tx13", - "tx14", "tx15"; - }; - - usb1_phy: usb-phy@47401b00 { - compatible = "ti,am335x-usb-phy"; - reg = <0x47401b00 0x100>; - reg-names = "phy"; - status = "disabled"; - ti,ctrl_mod = <&usb_ctrl_mod>; - #phy-cells = <0>; - }; - - usb1: usb@47401800 { - compatible = "ti,musb-am33xx"; - status = "disabled"; - reg = <0x47401c00 0x400 - 0x47401800 0x200>; - reg-names = "mc", "control"; - interrupts = <19>; - interrupt-names = "mc"; - dr_mode = "otg"; - mentor,multipoint = <1>; - mentor,num-eps = <16>; - mentor,ram-bits = <12>; - mentor,power = <500>; - phys = <&usb1_phy>; - - dmas = <&cppi41dma 15 0 &cppi41dma 16 0 - &cppi41dma 17 0 &cppi41dma 18 0 - &cppi41dma 19 0 &cppi41dma 20 0 - &cppi41dma 21 0 &cppi41dma 22 0 - &cppi41dma 23 0 &cppi41dma 24 0 - &cppi41dma 25 0 &cppi41dma 26 0 - &cppi41dma 27 0 &cppi41dma 28 0 - &cppi41dma 29 0 &cppi41dma 15 1 - &cppi41dma 16 1 &cppi41dma 17 1 - &cppi41dma 18 1 &cppi41dma 19 1 - &cppi41dma 20 1 &cppi41dma 21 1 - &cppi41dma 22 1 &cppi41dma 23 1 - &cppi41dma 24 1 &cppi41dma 25 1 - &cppi41dma 26 1 &cppi41dma 27 1 - &cppi41dma 28 1 &cppi41dma 29 1>; - dma-names = - "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7", - "rx8", "rx9", "rx10", "rx11", "rx12", "rx13", - "rx14", "rx15", - "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7", - "tx8", "tx9", "tx10", "tx11", "tx12", "tx13", - "tx14", "tx15"; - }; - - cppi41dma: dma-controller@47402000 { - compatible = "ti,am3359-cppi41"; - reg = <0x47400000 0x1000 - 0x47402000 0x1000 - 0x47403000 0x1000 - 0x47404000 0x4000>; - reg-names = "glue", "controller", "scheduler", "queuemgr"; - interrupts = <17>; - interrupt-names = "glue"; - #dma-cells = <2>; - #dma-channels = <30>; - #dma-requests = <256>; - status = "disabled"; - }; - }; - - ocmcram: ocmcram@40300000 { - compatible = "mmio-sram"; - reg = <0x40300000 0x10000>; /* 64k */ - ranges = <0x0 0x40300000 0x10000>; - #address-cells = <1>; - #size-cells = <1>; - - pm_sram_code: pm-sram-code@0 { - compatible = "ti,sram"; - reg = <0x0 0x1000>; - protect-exec; - }; - - pm_sram_data: pm-sram-data@1000 { - compatible = "ti,sram"; - reg = <0x1000 0x1000>; - pool; - }; - }; - - emif: emif@4c000000 { - compatible = "ti,emif-am3352"; - reg = <0x4c000000 0x1000000>; - ti,hwmods = "emif"; - interrupts = <101>; - sram = <&pm_sram_code - &pm_sram_data>; - ti,no-idle; - }; - - gpmc: gpmc@50000000 { - compatible = "ti,am3352-gpmc"; - ti,hwmods = "gpmc"; - ti,no-idle-on-init; - reg = <0x50000000 0x2000>; - interrupts = <100>; - dmas = <&edma 52 0>; - dma-names = "rxtx"; - gpmc,num-cs = <7>; - gpmc,num-waitpins = <2>; - #address-cells = <2>; - #size-cells = <1>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - status = "disabled"; - }; - - sham: sham@53100000 { - compatible = "ti,omap4-sham"; - ti,hwmods = "sham"; - reg = <0x53100000 0x200>; - interrupts = <109>; - dmas = <&edma 36 0>; - dma-names = "rx"; - }; - - aes: aes@53500000 { - compatible = "ti,omap4-aes"; - ti,hwmods = "aes"; - reg = <0x53500000 0xa0>; - interrupts = <103>; - dmas = <&edma 6 0>, - <&edma 5 0>; - dma-names = "tx", "rx"; - }; - }; -}; - -#include "am33xx-l4.dtsi" -#include "am33xx-clocks.dtsi" diff --git a/sys/gnu/dts/arm/am3517-craneboard.dts b/sys/gnu/dts/arm/am3517-craneboard.dts deleted file mode 100644 index eb3517dabee..00000000000 --- a/sys/gnu/dts/arm/am3517-craneboard.dts +++ /dev/null @@ -1,171 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * See craneboard.org for more details - * - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ - */ -/dts-v1/; - -#include "am3517.dtsi" - -/ { - model = "TI AM3517 CraneBoard (TMDSEVM3517)"; - compatible = "ti,am3517-craneboard", "ti,am3517", "ti,omap3"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x10000000>; /* 256 MB */ - }; - - vbat: fixedregulator { - compatible = "regulator-fixed"; - regulator-name = "vbat"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - }; -}; - -&davinci_emac { - status = "okay"; -}; - -&davinci_mdio { - status = "okay"; -}; - -&i2c1 { - clock-frequency = <2600000>; - - tps: tps@2d { - reg = <0x2d>; - }; -}; - -&i2c2 { - clock-frequency = <400000>; - /* goes to expansion connector */ - status = "disabled"; -}; - -&i2c3 { - clock-frequency = <400000>; - /* goes to expansion connector */ - status = "disabled"; -}; - -&mmc1 { - vmmc-supply = <&vdd2_reg>; - bus-width = <8>; -}; - -&mmc2 { - /* goes to expansion connector */ - status = "disabled"; -}; - -&mmc3 { - /* goes to expansion connector */ - status = "disabled"; -}; - -#include "tps65910.dtsi" - -&omap3_pmx_core { - tps_pins: pinmux_tps_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21e0, PIN_INPUT_PULLUP | MUX_MODE0) /* sys_nirq.sys_nirq */ - >; - }; -}; - -&tps { - pinctrl-names = "default"; - pinctrl-0 = <&tps_pins>; - - interrupts = <7>; /* SYS_NIRQ cascaded to intc */ - interrupt-parent = <&intc>; - - ti,en-ck32k-xtal; - - vcc1-supply = <&vbat>; - vcc2-supply = <&vbat>; - vcc3-supply = <&vbat>; - vcc4-supply = <&vbat>; - vcc5-supply = <&vbat>; - vcc6-supply = <&vbat>; - vcc7-supply = <&vbat>; - vccio-supply = <&vbat>; - - regulators { - vrtc_reg: regulator@0 { - regulator-always-on; - }; - - vio_reg: regulator@1 { - regulator-always-on; - }; - - /* - * Unused: - * VDIG1=2.7V,300mA max - * VDIG2=1.8V,300mA max - */ - - vpll_reg: regulator@7 { - /* VDDS_DPLL_1V8 */ - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vaux1_reg: regulator@9 { - /* VDDS_SRAM_1V8 */ - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vaux2_reg: regulator@10 { - /* VDDA1P8V_USBPHY */ - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - /* VAUX33 unused */ - - vdac_reg: regulator@8 { - /* VDDA_DAC_1V8 */ - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vmmc_reg: regulator@12 { - /* VDDA3P3V_USBPHY */ - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd1_reg: regulator@2 { - /* VDD_CORE */ - regulator-name = "vdd_core"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-boot-on; - regulator-always-on; - }; - - vdd2_reg: regulator@3 { - /* VDDSHV_3V3 */ - regulator-name = "vdd_shv"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - /* VDD3 unused */ - }; -}; diff --git a/sys/gnu/dts/arm/am3517-evm-ui.dtsi b/sys/gnu/dts/arm/am3517-evm-ui.dtsi deleted file mode 100644 index 48631a45da5..00000000000 --- a/sys/gnu/dts/arm/am3517-evm-ui.dtsi +++ /dev/null @@ -1,217 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2018 Logic PD, Inc - http://www.logicpd.com/ - */ - -#include - -/ { - codec1 { - compatible = "simple-audio-card"; - simple-audio-card,name = "tlv320aic23-hifi"; - - simple-audio-card,widgets = - "Microphone", "Mic In", - "Line", "Line In", - "Line", "Line Out"; - - simple-audio-card,routing = - "Line Out", "LOUT", - "Line Out", "ROUT", - "LLINEIN", "Line In", - "RLINEIN", "Line In", - "MICIN", "Mic In"; - - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&sound_master>; - simple-audio-card,frame-master = <&sound_master>; - - simple-audio-card,cpu { - sound-dai = <&mcbsp1>; - }; - - sound_master: simple-audio-card,codec { - sound-dai = <&tlv320aic23_1>; - system-clock-frequency = <12000000>; - }; - }; - - codec2 { - compatible = "simple-audio-card"; - simple-audio-card,name = "tlv320aic23-hifi"; - - simple-audio-card,widgets = - "Microphone", "Mic In", - "Line", "Line In", - "Line", "Line Out"; - - simple-audio-card,routing = - "Line Out", "LOUT", - "Line Out", "ROUT", - "LLINEIN", "Line In", - "RLINEIN", "Line In", - "MICIN", "Mic In"; - - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&sound_master2>; - simple-audio-card,frame-master = <&sound_master2>; - - simple-audio-card,cpu { - sound-dai = <&mcbsp2>; - }; - - sound_master2: simple-audio-card,codec { - sound-dai = <&tlv320aic23_2>; - system-clock-frequency = <12000000>; - }; - }; - - expander-keys { - compatible = "gpio-keys-polled"; - poll-interval = <100>; - - record { - label = "Record"; - /* linux,code = ; */ - gpios = <&tca6416_2 15 GPIO_ACTIVE_LOW>; - }; - - play { - label = "Play"; - linux,code = ; - gpios = <&tca6416_2 14 GPIO_ACTIVE_LOW>; - }; - - Stop { - label = "Stop"; - linux,code = ; - gpios = <&tca6416_2 13 GPIO_ACTIVE_LOW>; - }; - - fwd { - label = "FWD"; - linux,code = ; - gpios = <&tca6416_2 12 GPIO_ACTIVE_LOW>; - }; - - rwd { - label = "RWD"; - linux,code = ; - gpios = <&tca6416_2 11 GPIO_ACTIVE_LOW>; - }; - - shift { - label = "Shift"; - linux,code = ; - gpios = <&tca6416_2 10 GPIO_ACTIVE_LOW>; - }; - - Mode { - label = "Mode"; - linux,code = ; - gpios = <&tca6416_2 9 GPIO_ACTIVE_LOW>; - }; - - Menu { - label = "Menu"; - linux,code = ; - gpios = <&tca6416_2 8 GPIO_ACTIVE_LOW>; - }; - - Up { - label = "Up"; - linux,code = ; - gpios = <&tca6416_2 7 GPIO_ACTIVE_LOW>; - }; - - Down { - label = "Down"; - linux,code = ; - gpios = <&tca6416_2 6 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&i2c2 { - /* Audio codecs */ - tlv320aic23_1: codec@1a { - compatible = "ti,tlv320aic23"; - reg = <0x1a>; - #sound-dai-cells= <0>; - status = "okay"; - }; - - tlv320aic23_2: codec@1b { - compatible = "ti,tlv320aic23"; - reg = <0x1b>; - #sound-dai-cells= <0>; - status = "okay"; - }; -}; - -&i2c3 { - /* Audio codecs */ - tlv320aic23_3: codec@1a { - compatible = "ti,tlv320aic23"; - reg = <0x1a>; - #sound-dai-cells= <0>; - status = "okay"; - }; - - /* GPIO Expanders */ - tca6416_2: gpio@20 { - compatible = "ti,tca6416"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - vcc-supply = <&vdd_io_reg>; - }; - - tca6416_3: gpio@21 { - compatible = "ti,tca6416"; - reg = <0x21>; - gpio-controller; - #gpio-cells = <2>; - vcc-supply = <&vdd_io_reg>; - }; - - /* TVP5146 Analog Video decoder input */ - tvp5146@5c { - compatible = "ti,tvp5146m2"; - reg = <0x5c>; - }; -}; - -&mcbsp1 { - status = "ok"; - #sound-dai-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&mcbsp1_pins>; -}; - -&mcbsp2 { - status = "ok"; - #sound-dai-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&mcbsp2_pins>; -}; - -&omap3_pmx_core { - mcbsp1_pins: pinmux_mcbsp1_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2190, PIN_OUTPUT | MUX_MODE0) /* mcbsp1_dx.mcbsp1_dx */ - OMAP3_CORE1_IOPAD(0x2192, PIN_INPUT | MUX_MODE0) /* mcbsp1_dx.mcbsp1_dr */ - OMAP3_CORE1_IOPAD(0x2196, PIN_INPUT | MUX_MODE0) /* mcbsp_clks.mcbsp1_fsx */ - OMAP3_CORE1_IOPAD(0x2198, PIN_INPUT | MUX_MODE0) /* mcbsp1_clkx.mcbsp1_clkx */ - >; - }; - - mcbsp2_pins: pinmux_mcbsp2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx.mcbsp2_fsx */ - OMAP3_CORE1_IOPAD(0x213e, PIN_INPUT | MUX_MODE0) /* mcbsp2_clkx.mcbsp2_clkx */ - OMAP3_CORE1_IOPAD(0x2140, PIN_INPUT | MUX_MODE0) /* mcbsp2_dr.mcbsp2.dr */ - OMAP3_CORE1_IOPAD(0x2142, PIN_OUTPUT | MUX_MODE0) /* mcbsp2_dx.mcbsp2_dx */ - >; - }; -}; diff --git a/sys/gnu/dts/arm/am3517-evm.dts b/sys/gnu/dts/arm/am3517-evm.dts deleted file mode 100644 index a1fd3e63e86..00000000000 --- a/sys/gnu/dts/arm/am3517-evm.dts +++ /dev/null @@ -1,321 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ - */ -/dts-v1/; - -#include "am3517.dtsi" -#include "am3517-som.dtsi" -#include "am3517-evm-ui.dtsi" -#include - -/ { - model = "TI AM3517 EVM (AM3517/05 TMDSEVM3517)"; - compatible = "ti,am3517-evm", "ti,am3517", "ti,omap3"; - - aliases { - display0 = &lcd0; - }; - - chosen { - stdout-path = &uart3; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x10000000>; /* 256 MB */ - }; - - vmmc_fixed: vmmc { - compatible = "regulator-fixed"; - regulator-name = "vmmc_fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - gpio-keys { - compatible = "gpio-keys-polled"; - poll-interval = <100>; - - user_pb { - label = "User Push Button"; - linux,code = ; - gpios = <&tca6416 5 GPIO_ACTIVE_LOW>; - }; - - user_sw_1 { - label = "User Switch 1"; - linux,code = ; - gpios = <&tca6416 8 GPIO_ACTIVE_LOW>; - }; - - user_sw_2 { - label = "User Switch 2"; - linux,code = ; - gpios = <&tca6416 9 GPIO_ACTIVE_LOW>; - }; - - user_sw_3 { - label = "User Switch 3"; - linux,code = ; - gpios = <&tca6416 10 GPIO_ACTIVE_LOW>; - }; - - user_sw_4 { - label = "User Switch 4"; - linux,code = ; - gpios = <&tca6416 11 GPIO_ACTIVE_LOW>; - }; - - user_sw_5 { - label = "User Switch 5"; - linux,code = ; - gpios = <&tca6416 12 GPIO_ACTIVE_LOW>; - }; - - user_sw_6 { - label = "User Switch 6"; - linux,code = ; - gpios = <&tca6416 13 GPIO_ACTIVE_LOW>; - }; - - user_sw_7 { - label = "User Switch 7"; - linux,code = ; - gpios = <&tca6416 14 GPIO_ACTIVE_LOW>; - }; - - user_sw_8 { - label = "User Switch 8"; - linux,code = ; - gpios = <&tca6416 15 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - pinctrl-names = "default"; - pinctrl-0 = <&leds_pins>; - - user_led_1 { - label = "am3517evm:green:user_led_1"; - gpios = <&tca6416 7 GPIO_ACTIVE_LOW>; - default-state = "on"; - }; - - user_led_2 { - label = "am3517evm:green:user_led_2"; - gpios = <&tca6416 6 GPIO_ACTIVE_LOW>; - default-state = "on"; - }; - - user_led_3 { - label = "am3517evm:green:user_led_3"; - gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc0"; /* SD/MMC card activity */ - }; - - user_led_4 { - label = "am3517evm:green:user_led_4"; - gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - lcd0: display@0 { - /* This isn't the exact LCD, but the timings meet spec */ - /* To make it work, set CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=4 */ - compatible = "newhaven,nhd-4.3-480272ef-atxl"; - label = "15"; - backlight = <&bl>; - enable-gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>; /* gpio176, lcd INI */ - vcc-supply = <&vdd_io_reg>; - - port { - lcd_in: endpoint { - remote-endpoint = <&dpi_out>; - }; - }; - }; - - bl: backlight { - compatible = "pwm-backlight"; - pinctrl-names = "default"; - power-supply = <&vdd_io_reg>; - pinctrl-0 = <&backlight_pins>; - pwms = <&pwm11 0 5000000 0>; - brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; - default-brightness-level = <7>; - enable-gpios = <&gpio6 22 GPIO_ACTIVE_HIGH>; /* gpio_182 */ - }; - - pwm11: dmtimer-pwm@11 { - compatible = "ti,omap-dmtimer-pwm"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm_pins>; - ti,timers = <&timer11>; - #pwm-cells = <3>; - }; - - /* HS USB Host PHY on PORT 1 */ - hsusb1_phy: hsusb1_phy { - compatible = "usb-nop-xceiv"; - reset-gpios = <&gpio2 25 GPIO_ACTIVE_LOW>; /* gpio_57 */ - #phy-cells = <0>; - }; -}; - -&davinci_emac { - status = "okay"; -}; - -&davinci_mdio { - status = "okay"; -}; - -&dss { - status = "ok"; - - pinctrl-names = "default"; - pinctrl-0 = <&dss_dpi_pins>; - - vdds_dsi-supply = <&vdd_io_reg>; - vdda_video-supply = <&vdd_io_reg>; - - port { - dpi_out: endpoint { - remote-endpoint = <&lcd_in>; - data-lines = <16>; - }; - }; -}; - -&i2c2 { - clock-frequency = <400000>; - /* User DIP swithes [1:8] / User LEDS [1:2] */ - tca6416: gpio@21 { - compatible = "ti,tca6416"; - reg = <0x21>; - gpio-controller; - #gpio-cells = <2>; - vcc-supply = <&vdd_io_reg>; - }; -}; - -&i2c3 { - clock-frequency = <400000>; -}; - -&mmc1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - vmmc-supply = <&vmmc_fixed>; - bus-width = <4>; - wp-gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>; /* gpio_126 */ - cd-gpios = <&gpio4 31 GPIO_ACTIVE_LOW>; /* gpio_127 */ -}; - -&mmc3 { - status = "disabled"; -}; - -&usbhshost { - port1-mode = "ehci-phy"; -}; - -&usbhsehci { - phys = <&hsusb1_phy>; -}; - -&omap3_pmx_core { - pinctrl-names = "default"; - pinctrl-0 = <&hsusb1_rst_pins>; - - leds_pins: pinmux_leds_pins { - pinctrl-single,pins = < - OMAP3_WKUP_IOPAD(0x2a24, PIN_OUTPUT_PULLUP | MUX_MODE4) /* jtag_emu0.gpio_11 */ - OMAP3_WKUP_IOPAD(0x2a26, PIN_OUTPUT_PULLUP | MUX_MODE4) /* jtag_emu1.gpio_31 */ - >; - }; - - mmc1_pins: pinmux_mmc1_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ - OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ - OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ - OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ - OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ - OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ - OMAP3_CORE1_IOPAD(0x2150, PIN_INPUT_PULLUP | MUX_MODE4) /* sdmmc1_dat4.gpio_126 */ - OMAP3_CORE1_IOPAD(0x2152, PIN_INPUT_PULLUP | MUX_MODE4) /* sdmmc1_dat5.gpio_127 */ - >; - }; - - pwm_pins: pinmux_pwm_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21dc, PIN_OUTPUT | MUX_MODE1) /* mcspi2_cs0.gpt11_pwm */ - >; - }; - - backlight_pins: pinmux_backlight_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21de, PIN_OUTPUT | MUX_MODE4) /* mcspi2_cs1.gpio_182 */ - >; - }; - - dss_dpi_pins: pinmux_dss_dpi_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21d2, PIN_OUTPUT | MUX_MODE4) /* mcspi1_cs2.gpio_176 */ - OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ - OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ - OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ - OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ - OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ - OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ - OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ - OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ - OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ - OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ - OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ - OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ - OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ - OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ - OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ - OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ - OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ - OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ - OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ - OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ - >; - }; - - hsusb1_rst_pins: pinmux_hsusb1_rst_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20ba, PIN_OUTPUT | MUX_MODE4) /* gpmc_ncs6.gpio_57 */ - >; - }; -}; - -&omap3_pmx_core2 { - pinctrl-names = "default"; - pinctrl-0 = <&hsusb1_pins>; - - hsusb1_pins: pinmux_hsusb1_pins { - pinctrl-single,pins = < - OMAP3430_CORE2_IOPAD(0x25d8, PIN_OUTPUT | MUX_MODE3) /* etk_clk.hsusb1_stp */ - OMAP3430_CORE2_IOPAD(0x25da, PIN_OUTPUT | MUX_MODE3) /* etk_ctl.hsusb1_clk */ - OMAP3430_CORE2_IOPAD(0x25ec, PIN_INPUT | MUX_MODE3) /* etk_d8.hsusb1_dir */ - OMAP3430_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE3) /* etk_d9.hsusb1_nxt */ - OMAP3430_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE3) /* etk_d0.hsusb1_data0 */ - OMAP3430_CORE2_IOPAD(0x25de, PIN_INPUT | MUX_MODE3) /* etk_d1.hsusb1_data1 */ - OMAP3430_CORE2_IOPAD(0x25e0, PIN_INPUT | MUX_MODE3) /* etk_d2.hsusb1_data2 */ - OMAP3430_CORE2_IOPAD(0x25ea, PIN_INPUT | MUX_MODE3) /* etk_d7.hsusb1_data3 */ - OMAP3430_CORE2_IOPAD(0x25e4, PIN_INPUT | MUX_MODE3) /* etk_d4.hsusb1_data4 */ - OMAP3430_CORE2_IOPAD(0x25e6, PIN_INPUT | MUX_MODE3) /* etk_d5.hsusb1_data5 */ - OMAP3430_CORE2_IOPAD(0x25e8, PIN_INPUT | MUX_MODE3) /* etk_d6.hsusb1_data6 */ - OMAP3430_CORE2_IOPAD(0x25e2, PIN_INPUT | MUX_MODE3) /* etk_d3.hsusb1_data7 */ - >; - }; -}; diff --git a/sys/gnu/dts/arm/am3517-som.dtsi b/sys/gnu/dts/arm/am3517-som.dtsi deleted file mode 100644 index 8b669e2eafe..00000000000 --- a/sys/gnu/dts/arm/am3517-som.dtsi +++ /dev/null @@ -1,234 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2016 Derald D. Woods - * - * Based on am3517-evm.dts - */ - -/ { - cpus { - cpu@0 { - cpu0-supply = <&vdd_core_reg>; - }; - }; - - wl12xx_buffer: wl12xx_buf { - compatible = "regulator-fixed"; - regulator-name = "wl1271_buf"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - pinctrl-names = "default"; - pinctrl-0 = <&wl12xx_buffer_pins>; - gpio = <&gpio5 1 GPIO_ACTIVE_LOW>; /* gpio 129 */ - regulator-always-on; - vin-supply = <&vdd_1v8_reg>; - }; - - wl12xx_vmmc2: wl12xx_vmmc2 { - compatible = "regulator-fixed"; - regulator-name = "vwl1271"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - pinctrl-names = "default"; - pinctrl-0 = <&wl12xx_wkup_pins>; - gpio = <&gpio1 3 GPIO_ACTIVE_HIGH >; /* gpio 3 */ - startup-delay-us = <70000>; - enable-active-high; - regulator-always-on; - vin-supply = <&wl12xx_buffer>; - }; -}; - -&gpmc { - ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */ - - nand@0,0 { - compatible = "ti,omap2-nand"; - linux,mtd-name = "micron,mt29f4g16abchch"; - reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ - nand-bus-width = <16>; - ti,nand-ecc-opt = "bch8"; - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <44>; - gpmc,cs-wr-off-ns = <44>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <34>; - gpmc,adv-wr-off-ns = <44>; - gpmc,we-off-ns = <40>; - gpmc,oe-off-ns = <54>; - gpmc,access-ns = <64>; - gpmc,rd-cycle-ns = <82>; - gpmc,wr-cycle-ns = <82>; - gpmc,wr-access-ns = <40>; - gpmc,wr-data-mux-bus-ns = <0>; - gpmc,device-width = <2>; - #address-cells = <1>; - #size-cells = <1>; - }; -}; - -&i2c1 { - clock-frequency = <400000>; - - s35390a: s35390a@30 { - compatible = "sii,s35390a"; - reg = <0x30>; - - pinctrl-names = "default"; - pinctrl-0 = <&rtc_pins>; - interrupts-extended = <&gpio2 23 IRQ_TYPE_EDGE_FALLING>; /* gpio_55 */ - }; - - tps: tps65023@48 { - compatible = "ti,tps65023"; - reg = <0x48>; - - regulators { - vdd_core_reg: VDCDC1 { - regulator-name = "vdd_core"; - regulator-always-on; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - vdd_io_reg: VDCDC2 { - regulator-name = "vdd_io"; - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vdd_1v8_reg: VDCDC3 { - regulator-name = "vdd_1v8"; - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vdd_usb18_reg: LDO1 { - regulator-name = "vdd_usb18"; - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vdd_usb33_reg: LDO2 { - regulator-name = "vdd_usb33"; - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - }; - }; - - touchscreen: tsc2004@4b { - compatible = "ti,tsc2004"; - reg = <0x4b>; - - vio-supply = <&vdd_io_reg>; - - pinctrl-names = "default"; - pinctrl-0 = <&tsc2004_pins>; - interrupts-extended = <&gpio3 1 IRQ_TYPE_EDGE_RISING>; /* gpio_65 */ - - touchscreen-fuzz-x = <4>; - touchscreen-fuzz-y = <7>; - touchscreen-fuzz-pressure = <2>; - touchscreen-size-x = <480>; - touchscreen-size-y = <272>; - touchscreen-max-pressure = <2048>; - - ti,x-plate-ohms = <280>; - ti,esd-recovery-timeout-ms = <8000>; - }; -}; - -&mmc2 { - interrupts-extended = <&intc 86 /* &omap3_pmx_core 0x12c */>; - - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; - vmmc-supply = <&wl12xx_vmmc2>; - non-removable; - bus-width = <4>; - cap-power-off-card; - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@2 { - compatible = "ti,wl1271"; - reg = <2>; - interrupt-parent = <&gpio6>; - interrupts = <10 IRQ_TYPE_EDGE_RISING>; /* gpio_170 */ - ref-clock-frequency = <26000000>; - tcxo-clock-frequency = <26000000>; - }; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; - - bluetooth { - compatible = "ti,wl1271-st"; - enable-gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>; /* gpio 56 */ - max-speed = <3000000>; - }; -}; - -&omap3_pmx_core { - - wl12xx_buffer_pins: pinmux_wl12xx_buffer_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2156, PIN_OUTPUT | MUX_MODE4) /* mmc1_dat7.gpio_129 */ - >; - }; - - mmc2_pins: pinmux_mmc2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc2_clk.mmc2_clk */ - OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc2_cmd.mmc2_cmd */ - OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc2_dat0.mmc2_dat0 */ - OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc2_dat1.mmc2_dat1 */ - OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc2_dat2.mmc2_dat2 */ - OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc2_dat3.mmc2_dat3 */ - OMAP3_CORE1_IOPAD(0x2164, PIN_OUTPUT | MUX_MODE1) /* mmc2_dat4.mmc2_dir_dat0 */ - OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE1) /* mmc2_dat5.mmc2_dir_dat1 */ - OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE1) /* mmc2_dat6.mmc2_dir_cmd */ - OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT | MUX_MODE1) /* mmc2_dat7.mmc2_clkin */ - OMAP3_CORE1_IOPAD(0x21c6, PIN_INPUT_PULLUP | MUX_MODE4) /* hdq_sio.gpio_170 */ - >; - }; - - rtc_pins: pinmux_rtc_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20b6, PIN_INPUT_PULLUP | MUX_MODE4) /* gpmc_ncs4.gpio_55 */ - >; - }; - - tsc2004_pins: pinmux_tsc2004_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20d2, PIN_INPUT | MUX_MODE4) /* gpmc_wait3.gpio_65 */ - >; - }; - - uart2_pins: pinmux_uart2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts */ - OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT_PULLUP | MUX_MODE0) /* uart2_rts */ - OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx */ - OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx */ - OMAP3_CORE1_IOPAD(0x20b8, PIN_INPUT | MUX_MODE0) /* gpio_56 */ - >; - }; -}; - -&omap3_pmx_wkup { - - wl12xx_wkup_pins: pinmux_wl12xx_wkup_pins { - pinctrl-single,pins = < - OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE4) /* sys_boot1.gpio_3 */ - >; - }; -}; diff --git a/sys/gnu/dts/arm/am3517.dtsi b/sys/gnu/dts/arm/am3517.dtsi deleted file mode 100644 index bf3002009b0..00000000000 --- a/sys/gnu/dts/arm/am3517.dtsi +++ /dev/null @@ -1,136 +0,0 @@ -/* - * Device Tree Source for am3517 SoC - * - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -#include "omap3.dtsi" - -/ { - aliases { - serial3 = &uart4; - can = &hecc; - }; - - ocp@68000000 { - am35x_otg_hs: am35x_otg_hs@5c040000 { - compatible = "ti,omap3-musb"; - ti,hwmods = "am35x_otg_hs"; - status = "disabled"; - reg = <0x5c040000 0x1000>; - interrupts = <71>; - interrupt-names = "mc"; - }; - - davinci_emac: ethernet@5c000000 { - compatible = "ti,am3517-emac"; - ti,hwmods = "davinci_emac"; - status = "disabled"; - reg = <0x5c000000 0x30000>; - interrupts = <67 68 69 70>; - syscon = <&scm_conf>; - ti,davinci-ctrl-reg-offset = <0x10000>; - ti,davinci-ctrl-mod-reg-offset = <0>; - ti,davinci-ctrl-ram-offset = <0x20000>; - ti,davinci-ctrl-ram-size = <0x2000>; - ti,davinci-rmii-en = /bits/ 8 <1>; - local-mac-address = [ 00 00 00 00 00 00 ]; - clocks = <&emac_ick>; - clock-names = "ick"; - }; - - davinci_mdio: ethernet@5c030000 { - compatible = "ti,davinci_mdio"; - ti,hwmods = "davinci_mdio"; - status = "disabled"; - reg = <0x5c030000 0x1000>; - bus_freq = <1000000>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&emac_fck>; - clock-names = "fck"; - }; - - uart4: serial@4809e000 { - compatible = "ti,omap3-uart"; - ti,hwmods = "uart4"; - status = "disabled"; - reg = <0x4809e000 0x400>; - interrupts = <84>; - dmas = <&sdma 55 &sdma 54>; - dma-names = "tx", "rx"; - clock-frequency = <48000000>; - }; - - omap3_pmx_core2: pinmux@480025d8 { - compatible = "ti,omap3-padconf", "pinctrl-single"; - reg = <0x480025d8 0x24>; - #address-cells = <1>; - #size-cells = <0>; - #pinctrl-cells = <1>; - #interrupt-cells = <1>; - interrupt-controller; - pinctrl-single,register-width = <16>; - pinctrl-single,function-mask = <0xff1f>; - }; - - hecc: can@5c050000 { - compatible = "ti,am3517-hecc"; - status = "disabled"; - reg = <0x5c050000 0x80>, - <0x5c053000 0x180>, - <0x5c052000 0x200>; - reg-names = "hecc", "hecc-ram", "mbx"; - interrupts = <24>; - clocks = <&hecc_ck>; - }; - - /* - * On am3517 the OCP registers do not seem to be accessible - * similar to the omap34xx. Maybe SGX is permanently set to - * "OCP bypass mode", or maybe there is OCP_SYSCONFIG that is - * write-only at 0x50000e10. We detect SGX based on the SGX - * revision register instead of the unreadable OCP revision - * register. - */ - sgx_module: target-module@50000000 { - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x50000014 0x4>; - reg-names = "rev"; - clocks = <&sgx_fck>, <&sgx_ick>; - clock-names = "fck", "ick"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x50000000 0x4000>; - - /* - * Closed source PowerVR driver, no child device - * binding or driver in mainline - */ - }; - }; -}; - -/* Table Table 5-79 of the TRM shows 480ab000 is reserved */ -&usb_otg_hs { - status = "disabled"; -}; - -&iva { - status = "disabled"; -}; - -&mailbox { - status = "disabled"; -}; - -&mmu_isp { - status = "disabled"; -}; - -/include/ "am35xx-clocks.dtsi" -/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi" diff --git a/sys/gnu/dts/arm/am3517_mt_ventoux.dts b/sys/gnu/dts/arm/am3517_mt_ventoux.dts deleted file mode 100644 index e507e4ae0d8..00000000000 --- a/sys/gnu/dts/arm/am3517_mt_ventoux.dts +++ /dev/null @@ -1,24 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2011 Ilya Yanok, EmCraft Systems - */ -/dts-v1/; - -#include "omap34xx.dtsi" - -/ { - model = "TeeJet Mt.Ventoux"; - compatible = "teejet,mt_ventoux", "ti,omap3"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x10000000>; /* 256 MB */ - }; - - /* AM35xx doesn't have IVA */ - soc { - iva { - status = "disabled"; - }; - }; -}; diff --git a/sys/gnu/dts/arm/am35xx-clocks.dtsi b/sys/gnu/dts/arm/am35xx-clocks.dtsi deleted file mode 100644 index 220d0a52797..00000000000 --- a/sys/gnu/dts/arm/am35xx-clocks.dtsi +++ /dev/null @@ -1,125 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Device Tree Source for OMAP3 clock data - * - * Copyright (C) 2013 Texas Instruments, Inc. - */ -&scm_clocks { - emac_ick: emac_ick@32c { - #clock-cells = <0>; - compatible = "ti,am35xx-gate-clock"; - clocks = <&ipss_ick>; - reg = <0x032c>; - ti,bit-shift = <1>; - }; - - emac_fck: emac_fck@32c { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&rmii_ck>; - reg = <0x032c>; - ti,bit-shift = <9>; - }; - - vpfe_ick: vpfe_ick@32c { - #clock-cells = <0>; - compatible = "ti,am35xx-gate-clock"; - clocks = <&ipss_ick>; - reg = <0x032c>; - ti,bit-shift = <2>; - }; - - vpfe_fck: vpfe_fck@32c { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&pclk_ck>; - reg = <0x032c>; - ti,bit-shift = <10>; - }; - - hsotgusb_ick_am35xx: hsotgusb_ick_am35xx@32c { - #clock-cells = <0>; - compatible = "ti,am35xx-gate-clock"; - clocks = <&ipss_ick>; - reg = <0x032c>; - ti,bit-shift = <0>; - }; - - hsotgusb_fck_am35xx: hsotgusb_fck_am35xx@32c { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_ck>; - reg = <0x032c>; - ti,bit-shift = <8>; - }; - - hecc_ck: hecc_ck@32c { - #clock-cells = <0>; - compatible = "ti,am35xx-gate-clock"; - clocks = <&sys_ck>; - reg = <0x032c>; - ti,bit-shift = <3>; - }; -}; -&cm_clocks { - ipss_ick: ipss_ick@a10 { - #clock-cells = <0>; - compatible = "ti,am35xx-interface-clock"; - clocks = <&core_l3_ick>; - reg = <0x0a10>; - ti,bit-shift = <4>; - }; - - rmii_ck: rmii_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <50000000>; - }; - - pclk_ck: pclk_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <27000000>; - }; - - uart4_ick_am35xx: uart4_ick_am35xx@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <23>; - }; - - uart4_fck_am35xx: uart4_fck_am35xx@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_48m_fck>; - reg = <0x0a00>; - ti,bit-shift = <23>; - }; -}; - -&cm_clockdomains { - core_l3_clkdm: core_l3_clkdm { - compatible = "ti,clockdomain"; - clocks = <&sdrc_ick>, <&ipss_ick>, <&emac_ick>, <&vpfe_ick>, - <&hsotgusb_ick_am35xx>, <&hsotgusb_fck_am35xx>, - <&hecc_ck>; - }; - - core_l4_clkdm: core_l4_clkdm { - compatible = "ti,clockdomain"; - clocks = <&cpefuse_fck>, <&ts_fck>, <&usbtll_fck>, - <&usbtll_ick>, <&mmchs3_ick>, <&mmchs3_fck>, - <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>, - <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>, - <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>, - <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>, - <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>, - <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>, - <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>, - <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>, - <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>, - <&uart4_ick_am35xx>, <&uart4_fck_am35xx>; - }; -}; diff --git a/sys/gnu/dts/arm/am3703.dtsi b/sys/gnu/dts/arm/am3703.dtsi deleted file mode 100644 index e69de29bb2d..00000000000 diff --git a/sys/gnu/dts/arm/am3715.dtsi b/sys/gnu/dts/arm/am3715.dtsi deleted file mode 100644 index e69de29bb2d..00000000000 diff --git a/sys/gnu/dts/arm/am3874-iceboard.dts b/sys/gnu/dts/arm/am3874-iceboard.dts deleted file mode 100644 index 1b4b2b0500e..00000000000 --- a/sys/gnu/dts/arm/am3874-iceboard.dts +++ /dev/null @@ -1,489 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device tree for Winterland IceBoard - * - * http://mcgillcosmology.com - * http://threespeedlogic.com - * - * This is an ARM + FPGA instrumentation board used at telescopes in - * Antarctica (the South Pole Telescope), Chile (POLARBEAR), and at the DRAO - * observatory in British Columbia (CHIME). - * - * Copyright (c) 2019 Three-Speed Logic, Inc. - */ - -/dts-v1/; - -#include "dm814x.dtsi" -#include - -/ { - model = "Winterland IceBoard"; - compatible = "ti,dm8148", "ti,dm814"; - - chosen { - stdout-path = "serial1:115200n8"; - bootargs = "earlycon"; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x40000000>; /* 1 GB */ - }; - - vmmcsd_fixed: fixedregulator0 { - compatible = "regulator-fixed"; - regulator-name = "vmmcsd_fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; -}; - -/* The MAC provides internal delay for the transmit path ONLY, which is enabled - * provided no -id/-txid/-rxid suffix is provided to "phy-mode". - * - * The receive path is delayed at the PHY. The recommended register settings - * are 0xf0 for the control bits, and 0x7777 for the data bits. However, the - * conversion code in the kernel lies: the PHY's registers are 120 ps per tap, - * and the kernel assumes 200 ps per tap. So we have fudged the numbers here to - * obtain the correct register settings. - */ -&mac { dual_emac = <1>; }; -&cpsw_emac0 { - phy-handle = <ðphy0>; - phy-mode = "rgmii"; - dual_emac_res_vlan = <1>; -}; -&cpsw_emac1 { - phy-handle = <ðphy1>; - phy-mode = "rgmii"; - dual_emac_res_vlan = <2>; -}; - -&davinci_mdio { - ethphy0: ethernet-phy@0 { - reg = <0x2>; - - rxc-skew-ps = <3000>; - rxdv-skew-ps = <0>; - - rxd3-skew-ps = <0>; - rxd2-skew-ps = <0>; - rxd1-skew-ps = <0>; - rxd0-skew-ps = <0>; - - phy-reset-gpios = <&gpio2 8 GPIO_ACTIVE_LOW>; - }; - - ethphy1: ethernet-phy@1 { - reg = <0x1>; - - rxc-skew-ps = <3000>; - rxdv-skew-ps = <0>; - - rxd3-skew-ps = <0>; - rxd2-skew-ps = <0>; - rxd1-skew-ps = <0>; - rxd0-skew-ps = <0>; - - phy-reset-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; - }; -}; - -&mmc1 { status = "disabled"; }; -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; - vmmc-supply = <&vmmcsd_fixed>; - bus-width = <4>; -}; -&mmc3 { status = "disabled"; }; - -&i2c1 { - /* Most I2C activity happens through this port, with the sole exception - * of the backplane. Since there are multiply assigned addresses, the - * "i2c-mux-idle-disconnect" is important. - */ - - pca9548@70 { - compatible = "nxp,pca9548"; - reg = <0x70>; - #address-cells = <1>; - #size-cells = <0>; - i2c-mux-idle-disconnect; - - i2c@0 { - /* FMC A */ - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - i2c@1 { - /* FMC B */ - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - i2c@2 { - /* QSFP A */ - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - i2c@3 { - /* QSFP B */ - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - - i2c@4 { - /* SFP */ - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - - i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - - ina230@40 { compatible = "ti,ina230"; reg = <0x40>; shunt-resistor = <5000>; }; - ina230@41 { compatible = "ti,ina230"; reg = <0x41>; shunt-resistor = <5000>; }; - ina230@42 { compatible = "ti,ina230"; reg = <0x42>; shunt-resistor = <5000>; }; - - ina230@44 { compatible = "ti,ina230"; reg = <0x44>; shunt-resistor = <5000>; }; - ina230@45 { compatible = "ti,ina230"; reg = <0x45>; shunt-resistor = <5000>; }; - ina230@46 { compatible = "ti,ina230"; reg = <0x46>; shunt-resistor = <5000>; }; - - ina230@47 { compatible = "ti,ina230"; reg = <0x47>; shunt-resistor = <5500>; }; - ina230@48 { compatible = "ti,ina230"; reg = <0x48>; shunt-resistor = <2360>; }; - ina230@49 { compatible = "ti,ina230"; reg = <0x49>; shunt-resistor = <2360>; }; - ina230@43 { compatible = "ti,ina230"; reg = <0x43>; shunt-resistor = <2360>; }; - ina230@4b { compatible = "ti,ina230"; reg = <0x4b>; shunt-resistor = <5500>; }; - ina230@4c { compatible = "ti,ina230"; reg = <0x4c>; shunt-resistor = <2360>; }; - ina230@4d { compatible = "ti,ina230"; reg = <0x4d>; shunt-resistor = <770>; }; - ina230@4e { compatible = "ti,ina230"; reg = <0x4e>; shunt-resistor = <770>; }; - ina230@4f { compatible = "ti,ina230"; reg = <0x4f>; shunt-resistor = <770>; }; - }; - - i2c@6 { - /* Backplane */ - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - }; - - i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - - u41: pca9575@20 { - compatible = "nxp,pca9575"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - - gpio-line-names = - "FMCA_EN_12V0", "FMCA_EN_3V3", "FMCA_EN_VADJ", "FMCA_PG_M2C", - "FMCA_PG_C2M", "FMCA_PRSNT_M2C_L", "FMCA_CLK_DIR", "SFP_LOS", - "FMCB_EN_12V0", "FMCB_EN_3V3", "FMCB_EN_VADJ", "FMCB_PG_M2C", - "FMCB_PG_C2M", "FMCB_PRSNT_M2C_L", "FMCB_CLK_DIR", "SFP_ModPrsL"; - reset_gpios = <&gpio2 11 GPIO_ACTIVE_LOW>; - }; - - u42: pca9575@21 { - compatible = "nxp,pca9575"; - reg = <0x21>; - gpio-controller; - #gpio-cells = <2>; - gpio-line-names = - "QSFPA_ModPrsL", "QSFPA_IntL", "QSFPA_ResetL", "QSFPA_ModSelL", - "QSFPA_LPMode", "QSFPB_ModPrsL", "QSFPB_IntL", "QSFPB_ResetL", - "SFP_TxFault", "SFP_TxDisable", "SFP_RS0", "SFP_RS1", - "QSFPB_ModSelL", "QSFPB_LPMode", "SEL_SFP", "ARM_MR"; - reset_gpios = <&gpio2 11 GPIO_ACTIVE_LOW>; - }; - - u48: pca9575@22 { - compatible = "nxp,pca9575"; - reg=<0x22>; - gpio-controller; - #gpio-cells = <2>; - - sw-gpios = <&u48 0 0>, <&u48 1 0>, <&u48 2 0>, <&u48 3 0>, - <&u48 4 0>, <&u48 5 0>, <&u48 6 0>, <&u48 7 0>; - led-gpios = <&u48 7 0>, <&u48 6 0>, <&u48 5 0>, <&u48 4 0>, - <&u48 3 0>, <&u48 2 0>, <&u48 1 0>, <&u48 0 0>; - - gpio-line-names = - "GP_SW1", "GP_SW2", "GP_SW3", "GP_SW4", - "GP_SW5", "GP_SW6", "GP_SW7", "GP_SW8", - "GP_LED8", "GP_LED7", "GP_LED6", "GP_LED5", - "GP_LED4", "GP_LED3", "GP_LED2", "GP_LED1"; - reset_gpios = <&gpio2 11 GPIO_ACTIVE_LOW>; - }; - - u59: pca9575@23 { - compatible = "nxp,pca9575"; - reg=<0x23>; - gpio-controller; - #gpio-cells = <2>; - gpio-line-names = - "GP_LED9", "GP_LED10", "GP_LED11", "GP_LED12", - "GTX1V8PowerFault", "PHYAPowerFault", "PHYBPowerFault", "ArmPowerFault", - "BP_SLOW_GPIO0", "BP_SLOW_GPIO1", "BP_SLOW_GPIO2", "BP_SLOW_GPIO3", - "BP_SLOW_GPIO4", "BP_SLOW_GPIO5", "__unused_u59_p16", "__unused_u59_p17"; - reset_gpios = <&gpio2 11 GPIO_ACTIVE_LOW>; - }; - - tmp100@48 { compatible = "ti,tmp100"; reg = <0x48>; }; - tmp100@4a { compatible = "ti,tmp100"; reg = <0x4a>; }; - tmp100@4b { compatible = "ti,tmp100"; reg = <0x4b>; }; - tmp100@4c { compatible = "ti,tmp100"; reg = <0x4c>; }; - - /* EEPROM bank and serial number are treated as separate devices */ - at24c01@57 { compatible = "atmel,24c01"; reg = <0x57>; }; - at24cs01@5f { compatible = "atmel,24cs01"; reg = <0x5f>; }; - }; - }; -}; - -&i2c2 { - pca9548@71 { - compatible = "nxp,pca9548"; - reg = <0x71>; - #address-cells = <1>; - #size-cells = <0>; - - i2c@6 { - /* Backplane */ - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - multi-master; - - /* All backplanes should have this -- it's how we know they're there. */ - at24c08@54 { compatible="atmel,24c08"; reg=<0x54>; }; - at24cs08@5c { compatible="atmel,24cs08"; reg=<0x5c>; }; - - /* 16 slot backplane */ - tmp421@4d { compatible="ti,tmp421"; reg=<0x4d>; }; - tmp421@4e { compatible="ti,tmp421"; reg=<0x4e>; }; - ina230@40 { compatible = "ti,ina230"; reg = <0x40>; shunt-resistor = <2360>; }; - amc6821@18 { compatible = "ti,amc6821"; reg = <0x18>; }; - - /* Single slot backplane */ - }; - }; -}; - -&pincntl { - mmc2_pins: pinmux_mmc2_pins { - pinctrl-single,pins = < - DM814X_IOPAD(0x0800, PIN_INPUT | 0x1) /* SD1_CLK */ - DM814X_IOPAD(0x0804, PIN_INPUT_PULLUP | 0x1) /* SD1_CMD */ - DM814X_IOPAD(0x0808, PIN_INPUT_PULLUP | 0x1) /* SD1_DAT[0] */ - DM814X_IOPAD(0x080c, PIN_INPUT_PULLUP | 0x1) /* SD1_DAT[1] */ - DM814X_IOPAD(0x0810, PIN_INPUT_PULLUP | 0x1) /* SD1_DAT[2] */ - DM814X_IOPAD(0x0814, PIN_INPUT_PULLUP | 0x1) /* SD1_DAT[3] */ - DM814X_IOPAD(0x0924, PIN_INPUT_PULLUP | 0x40) /* SD1_POW */ - DM814X_IOPAD(0x0928, PIN_INPUT | 0x40) /* SD1_SDWP */ - DM814X_IOPAD(0x093C, PIN_INPUT | 0x2) /* SD1_SDCD */ - >; - }; - - usb0_pins: pinmux_usb0_pins { - pinctrl-single,pins = < - DM814X_IOPAD(0x0c34, PIN_OUTPUT | 0x1) /* USB0_DRVVBUS */ - >; - }; - - usb1_pins: pinmux_usb1_pins { - pinctrl-single,pins = < - DM814X_IOPAD(0x0834, PIN_OUTPUT | 0x80) /* USB1_DRVVBUS */ - >; - }; - - gpio1_pins: pinmux_gpio1_pins { - pinctrl-single,pins = < - DM814X_IOPAD(0x081c, PIN_OUTPUT | 0x80) /* PROGRAM_B */ - DM814X_IOPAD(0x0820, PIN_INPUT | 0x80) /* INIT_B */ - DM814X_IOPAD(0x0824, PIN_INPUT | 0x80) /* DONE */ - - DM814X_IOPAD(0x0838, PIN_INPUT_PULLUP | 0x80) /* FMCA_TMS */ - DM814X_IOPAD(0x083c, PIN_INPUT_PULLUP | 0x80) /* FMCA_TCK */ - DM814X_IOPAD(0x0898, PIN_INPUT_PULLUP | 0x80) /* FMCA_TDO */ - DM814X_IOPAD(0x089c, PIN_INPUT_PULLUP | 0x80) /* FMCA_TDI */ - DM814X_IOPAD(0x08ac, PIN_INPUT_PULLUP | 0x80) /* FMCA_TRST */ - - DM814X_IOPAD(0x08b0, PIN_INPUT_PULLUP | 0x80) /* FMCB_TMS */ - DM814X_IOPAD(0x0a88, PIN_INPUT_PULLUP | 0x80) /* FMCB_TCK */ - DM814X_IOPAD(0x0a8c, PIN_INPUT_PULLUP | 0x80) /* FMCB_TDO */ - DM814X_IOPAD(0x08bc, PIN_INPUT_PULLUP | 0x80) /* FMCB_TDI */ - DM814X_IOPAD(0x0a94, PIN_INPUT_PULLUP | 0x80) /* FMCB_TRST */ - - DM814X_IOPAD(0x08d4, PIN_INPUT_PULLUP | 0x80) /* FPGA_TMS */ - DM814X_IOPAD(0x0aa8, PIN_INPUT_PULLUP | 0x80) /* FPGA_TCK */ - DM814X_IOPAD(0x0adc, PIN_INPUT_PULLUP | 0x80) /* FPGA_TDO */ - DM814X_IOPAD(0x0ab0, PIN_INPUT_PULLUP | 0x80) /* FPGA_TDI */ - >; - }; - - gpio2_pins: pinmux_gpio2_pins { - pinctrl-single,pins = < - DM814X_IOPAD(0x090c, PIN_INPUT_PULLUP | 0x80) /* PHY A IRQ */ - DM814X_IOPAD(0x0910, PIN_INPUT_PULLUP | 0x80) /* PHY A RESET */ - DM814X_IOPAD(0x08f4, PIN_INPUT_PULLUP | 0x80) /* PHY B IRQ */ - DM814X_IOPAD(0x08f8, PIN_INPUT_PULLUP | 0x80) /* PHY B RESET */ - - //DM814X_IOPAD(0x0a14, PIN_INPUT_PULLUP | 0x80) /* ARM IRQ */ - //DM814X_IOPAD(0x0900, PIN_INPUT | 0x80) /* GPIO IRQ */ - DM814X_IOPAD(0x0a2c, PIN_INPUT_PULLUP | 0x80) /* GPIO RESET */ - >; - }; - - gpio4_pins: pinmux_gpio4_pins { - pinctrl-single,pins = < - /* The PLL doesn't react well to the SPI controller reset, so - * we force the CS lines to pull up as GPIOs until we're ready. - * See https://e2e.ti.com/support/processors/f/791/t/276011?Linux-support-for-AM3874-DM8148-in-Arago-linux-omap3 - */ - DM814X_IOPAD(0x0b3c, PIN_INPUT_PULLUP | 0x80) /* BP_ARM_GPIO0 */ - DM814X_IOPAD(0x0b40, PIN_INPUT_PULLUP | 0x80) /* BP_ARM_GPIO1 */ - DM814X_IOPAD(0x0b44, PIN_INPUT_PULLUP | 0x80) /* BP_ARM_GPIO2 */ - DM814X_IOPAD(0x0b48, PIN_INPUT_PULLUP | 0x80) /* BP_ARM_GPIO3 */ - DM814X_IOPAD(0x0b4c, PIN_INPUT_PULLUP | 0x80) /* BP_ARM_GPIO4 */ - DM814X_IOPAD(0x0b50, PIN_INPUT_PULLUP | 0x80) /* BP_ARM_GPIO5 */ - >; - }; - - spi2_pins: pinmux_spi2_pins { - pinctrl-single,pins = < - DM814X_IOPAD(0x0950, PIN_INPUT_PULLUP | 0x80) /* PLL SPI CS1 as GPIO */ - DM814X_IOPAD(0x0818, PIN_INPUT_PULLUP | 0x80) /* PLL SPI CS2 as GPIO */ - >; - }; - - spi4_pins: pinmux_spi4_pins { - pinctrl-single,pins = < - DM814X_IOPAD(0x0a7c, 0x20) - DM814X_IOPAD(0x0b74, 0x20) - DM814X_IOPAD(0x0b78, PIN_OUTPUT | 0x20) - DM814X_IOPAD(0x0b7c, PIN_OUTPUT_PULLDOWN | 0x20) - DM814X_IOPAD(0x0b80, PIN_INPUT | 0x20) - >; - }; -}; - -&gpio1 { - pinctrl-names = "default"; - pinctrl-0 = <&gpio1_pins>; - gpio-line-names = - "", "PROGRAM_B", "INIT_B", "DONE", /* 0-3 */ - "", "", "", "", /* 4-7 */ - "FMCA_TMS", "FMCA_TCK", "FMCA_TDO", "FMCA_TDI", /* 8-11 */ - "", "", "", "FMCA_TRST", /* 12-15 */ - "FMCB_TMS", "FMCB_TCK", "FMCB_TDO", "FMCB_TDI", /* 16-19 */ - "FMCB_TRST", "", "", "", /* 20-23 */ - "FPGA_TMS", "FPGA_TCK", "FPGA_TDO", "FPGA_TDI", /* 24-27 */ - "", "", "", ""; /* 28-31 */ -}; - -&gpio2 { - pinctrl-names = "default"; - pinctrl-0 = <&gpio2_pins>; - gpio-line-names = - "PHYA_IRQ_N", "PHYA_RESET_N", "", "", /* 0-3 */ - "", "", "", "PHYB_IRQ_N", /* 4-7 */ - "PHYB_RESET_N", "ARM_IRQ", "GPIO_IRQ", ""; /* 8-11 */ -}; - -&gpio3 { - pinctrl-names = "default"; - /*pinctrl-0 = <&gpio3_pins>;*/ - gpio-line-names = - "", "", "ARMClkSel0", "", /* 0-3 */ - "EnFPGARef", "", "", "ARMClkSel1"; /* 4-7 */ -}; - -&gpio4 { - pinctrl-names = "default"; - pinctrl-0 = <&gpio4_pins>; - gpio-line-names = - "BP_ARM_GPIO0", "BP_ARM_GPIO1", "BP_ARM_GPIO2", "BP_ARM_GPIO3", - "BP_ARM_GPIO4", "BP_ARM_GPIO5"; -}; - -&usb0 { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_pins>; - dr_mode = "host"; -}; - -&usb1 { - pinctrl-names = "default"; - pinctrl-0 = <&usb1_pins>; - dr_mode = "host"; -}; - -&mcspi1 { - s25fl256@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <40000000>; - - fsbl@0 { - /* 256 kB */ - label = "U-Boot-min"; - reg = <0 0x40000>; - }; - ssbl@1 { - /* 512 kB */ - label = "U-Boot"; - reg = <0x40000 0x80000>; - }; - bootenv@2 { - /* 256 kB */ - label = "U-Boot Env"; - reg = <0xc0000 0x40000>; - }; - kernel@3 { - /* 4 MB */ - label = "Kernel"; - reg = <0x100000 0x400000>; - }; - ipmi@4 { - label = "IPMI FRU"; - reg = <0x500000 0x40000>; - }; - fs@5 { - label = "File System"; - reg = <0x540000 0x1ac0000>; - }; - }; -}; - -&mcspi3 { - /* DMA event numbers stolen from MCASP */ - dmas = <&edma_xbar 8 0 16 &edma_xbar 9 0 17 - &edma_xbar 10 0 18 &edma_xbar 11 0 19>; - dma-names = "tx0", "rx0", "tx1", "rx1"; -}; - -&mcspi4 { - pinctrl-names = "default"; - pinctrl-0 = <&spi4_pins>; - - /* DMA event numbers stolen from MCASP, MCBSP */ - dmas = <&edma_xbar 12 0 20 &edma_xbar 13 0 21>; - dma-names = "tx0", "rx0"; -}; diff --git a/sys/gnu/dts/arm/am4372.dtsi b/sys/gnu/dts/arm/am4372.dtsi deleted file mode 100644 index 14bbc438055..00000000000 --- a/sys/gnu/dts/arm/am4372.dtsi +++ /dev/null @@ -1,377 +0,0 @@ -/* - * Device Tree Source for AM4372 SoC - * - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -#include -#include -#include -#include - -/ { - compatible = "ti,am4372", "ti,am43"; - interrupt-parent = <&wakeupgen>; - #address-cells = <1>; - #size-cells = <1>; - chosen { }; - - memory@0 { - device_type = "memory"; - reg = <0 0>; - }; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - serial4 = &uart4; - serial5 = &uart5; - ethernet0 = &cpsw_emac0; - ethernet1 = &cpsw_emac1; - spi0 = &qspi; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu: cpu@0 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - reg = <0>; - - clocks = <&dpll_mpu_ck>; - clock-names = "cpu"; - - operating-points-v2 = <&cpu0_opp_table>; - - clock-latency = <300000>; /* From omap-cpufreq driver */ - }; - }; - - cpu0_opp_table: opp-table { - compatible = "operating-points-v2-ti-cpu"; - syscon = <&scm_conf>; - - opp50-300000000 { - opp-hz = /bits/ 64 <300000000>; - opp-microvolt = <950000 931000 969000>; - opp-supported-hw = <0xFF 0x01>; - opp-suspend; - }; - - opp100-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <1100000 1078000 1122000>; - opp-supported-hw = <0xFF 0x04>; - }; - - opp120-720000000 { - opp-hz = /bits/ 64 <720000000>; - opp-microvolt = <1200000 1176000 1224000>; - opp-supported-hw = <0xFF 0x08>; - }; - - oppturbo-800000000 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <1260000 1234800 1285200>; - opp-supported-hw = <0xFF 0x10>; - }; - - oppnitro-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <1325000 1298500 1351500>; - opp-supported-hw = <0xFF 0x20>; - }; - }; - - soc { - compatible = "ti,omap-infra"; - mpu { - compatible = "ti,omap4-mpu"; - ti,hwmods = "mpu"; - pm-sram = <&pm_sram_code - &pm_sram_data>; - }; - }; - - gic: interrupt-controller@48241000 { - compatible = "arm,cortex-a9-gic"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0x48241000 0x1000>, - <0x48240100 0x0100>; - interrupt-parent = <&gic>; - }; - - wakeupgen: interrupt-controller@48281000 { - compatible = "ti,omap4-wugen-mpu"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0x48281000 0x1000>; - interrupt-parent = <&gic>; - }; - - scu: scu@48240000 { - compatible = "arm,cortex-a9-scu"; - reg = <0x48240000 0x100>; - }; - - global_timer: timer@48240200 { - compatible = "arm,cortex-a9-global-timer"; - reg = <0x48240200 0x100>; - interrupts = ; - interrupt-parent = <&gic>; - clocks = <&mpu_periphclk>; - }; - - local_timer: timer@48240600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0x48240600 0x100>; - interrupts = ; - interrupt-parent = <&gic>; - clocks = <&mpu_periphclk>; - }; - - l2-cache-controller@48242000 { - compatible = "arm,pl310-cache"; - reg = <0x48242000 0x1000>; - cache-unified; - cache-level = <2>; - }; - - ocp@44000000 { - compatible = "ti,am4372-l3-noc", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - ti,hwmods = "l3_main"; - ti,no-idle; - reg = <0x44000000 0x400000 - 0x44800000 0x400000>; - interrupts = , - ; - - l4_wkup: interconnect@44c00000 { - wkup_m3: wkup_m3@100000 { - compatible = "ti,am4372-wkup-m3"; - reg = <0x100000 0x4000>, - <0x180000 0x2000>; - reg-names = "umem", "dmem"; - ti,hwmods = "wkup_m3"; - ti,pm-firmware = "am335x-pm-firmware.elf"; - }; - }; - l4_per: interconnect@48000000 { - }; - l4_fast: interconnect@4a000000 { - }; - - emif: emif@4c000000 { - compatible = "ti,emif-am4372"; - reg = <0x4c000000 0x1000000>; - ti,hwmods = "emif"; - interrupts = ; - ti,no-idle; - sram = <&pm_sram_code - &pm_sram_data>; - }; - - edma: edma@49000000 { - compatible = "ti,edma3-tpcc"; - ti,hwmods = "tpcc"; - reg = <0x49000000 0x10000>; - reg-names = "edma3_cc"; - interrupts = , - , - ; - interrupt-names = "edma3_ccint", "edma3_mperr", - "edma3_ccerrint"; - dma-requests = <64>; - #dma-cells = <2>; - - ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>, - <&edma_tptc2 0>; - - ti,edma-memcpy-channels = <58 59>; - }; - - edma_tptc0: tptc@49800000 { - compatible = "ti,edma3-tptc"; - ti,hwmods = "tptc0"; - reg = <0x49800000 0x100000>; - interrupts = ; - interrupt-names = "edma3_tcerrint"; - }; - - edma_tptc1: tptc@49900000 { - compatible = "ti,edma3-tptc"; - ti,hwmods = "tptc1"; - reg = <0x49900000 0x100000>; - interrupts = ; - interrupt-names = "edma3_tcerrint"; - }; - - edma_tptc2: tptc@49a00000 { - compatible = "ti,edma3-tptc"; - ti,hwmods = "tptc2"; - reg = <0x49a00000 0x100000>; - interrupts = ; - interrupt-names = "edma3_tcerrint"; - }; - - target-module@47810000 { - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "mmc3"; - reg = <0x478102fc 0x4>, - <0x47810110 0x4>, - <0x47810114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - clocks = <&l3s_clkctrl AM4_L3S_MMC3_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x47810000 0x1000>; - - mmc3: mmc@0 { - compatible = "ti,omap4-hsmmc"; - ti,needs-special-reset; - interrupts = ; - reg = <0x0 0x1000>; - }; - }; - - sham: sham@53100000 { - compatible = "ti,omap5-sham"; - ti,hwmods = "sham"; - reg = <0x53100000 0x300>; - dmas = <&edma 36 0>; - dma-names = "rx"; - interrupts = ; - }; - - aes: aes@53501000 { - compatible = "ti,omap4-aes"; - ti,hwmods = "aes"; - reg = <0x53501000 0xa0>; - interrupts = ; - dmas = <&edma 6 0>, - <&edma 5 0>; - dma-names = "tx", "rx"; - }; - - des: des@53701000 { - compatible = "ti,omap4-des"; - ti,hwmods = "des"; - reg = <0x53701000 0xa0>; - interrupts = ; - dmas = <&edma 34 0>, - <&edma 33 0>; - dma-names = "tx", "rx"; - }; - - gpmc: gpmc@50000000 { - compatible = "ti,am3352-gpmc"; - ti,hwmods = "gpmc"; - dmas = <&edma 52 0>; - dma-names = "rxtx"; - clocks = <&l3s_gclk>; - clock-names = "fck"; - reg = <0x50000000 0x2000>; - interrupts = ; - gpmc,num-cs = <7>; - gpmc,num-waitpins = <2>; - #address-cells = <2>; - #size-cells = <1>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - status = "disabled"; - }; - - qspi: spi@47900000 { - compatible = "ti,am4372-qspi"; - reg = <0x47900000 0x100>, - <0x30000000 0x4000000>; - reg-names = "qspi_base", "qspi_mmap"; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "qspi"; - interrupts = <0 138 0x4>; - num-cs = <4>; - status = "disabled"; - }; - - dss: dss@4832a000 { - compatible = "ti,omap3-dss"; - reg = <0x4832a000 0x200>; - status = "disabled"; - ti,hwmods = "dss_core"; - clocks = <&disp_clk>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - dispc: dispc@4832a400 { - compatible = "ti,omap3-dispc"; - reg = <0x4832a400 0x400>; - interrupts = ; - ti,hwmods = "dss_dispc"; - clocks = <&disp_clk>; - clock-names = "fck"; - - max-memory-bandwidth = <230000000>; - }; - - rfbi: rfbi@4832a800 { - compatible = "ti,omap3-rfbi"; - reg = <0x4832a800 0x100>; - ti,hwmods = "dss_rfbi"; - clocks = <&disp_clk>; - clock-names = "fck"; - status = "disabled"; - }; - }; - - ocmcram: ocmcram@40300000 { - compatible = "mmio-sram"; - reg = <0x40300000 0x40000>; /* 256k */ - ranges = <0x0 0x40300000 0x40000>; - #address-cells = <1>; - #size-cells = <1>; - - pm_sram_code: pm-sram-code@0 { - compatible = "ti,sram"; - reg = <0x0 0x1000>; - protect-exec; - }; - - pm_sram_data: pm-sram-data@1000 { - compatible = "ti,sram"; - reg = <0x1000 0x1000>; - pool; - }; - }; - }; -}; - -#include "am437x-l4.dtsi" -#include "am43xx-clocks.dtsi" diff --git a/sys/gnu/dts/arm/am437x-cm-t43.dts b/sys/gnu/dts/arm/am437x-cm-t43.dts deleted file mode 100644 index 063113a5da2..00000000000 --- a/sys/gnu/dts/arm/am437x-cm-t43.dts +++ /dev/null @@ -1,420 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2015 CompuLab, Ltd. - http://www.compulab.co.il/ - */ - -/dts-v1/; - -#include -#include -#include -#include "am4372.dtsi" - -/ { - model = "CompuLab CM-T43"; - compatible = "compulab,am437x-cm-t43", "ti,am4372", "ti,am43"; - - leds { - compatible = "gpio-leds"; - - ledb { - label = "cm-t43:green"; - gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - vmmc_3v3: fixedregulator-v3_3 { - compatible = "regulator-fixed"; - regulator-name = "vmmc_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - enable-active-high; - }; -}; - -&am43xx_pinmux { - pinctrl-names = "default"; - pinctrl-0 = <&cm_t43_led_pins>; - - cm_t43_led_pins: cm_t43_led_pins { - pinctrl-single,pins = < - AM4372_IOPAD(0xa78, MUX_MODE7) - >; - }; - - i2c0_pins: i2c0_pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x988, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */ - AM4372_IOPAD(0x98c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */ - >; - }; - - emmc_pins: emmc_pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x820, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad8.mmc1_dat0 */ - AM4372_IOPAD(0x824, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad9.mmc1_dat1 */ - AM4372_IOPAD(0x828, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad10.mmc1_dat2 */ - AM4372_IOPAD(0x82c, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad11.mmc1_dat3 */ - AM4372_IOPAD(0x830, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad12.mmc1_dat4 */ - AM4372_IOPAD(0x834, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad13.mmc1_dat5 */ - AM4372_IOPAD(0x838, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad14.mmc1_dat6 */ - AM4372_IOPAD(0x83c, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad15.mmc1_dat7 */ - AM4372_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */ - AM4372_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ - >; - }; - - spi0_pins: pinmux_spi0_pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x950, PIN_INPUT | MUX_MODE0) /* spi0_sclk.spi0_sclk */ - AM4372_IOPAD(0x954, PIN_INPUT | MUX_MODE0) /* spi0_d0.spi0_d0 */ - AM4372_IOPAD(0x958, PIN_OUTPUT | MUX_MODE0) /* spi0_d1.spi0_d1 */ - AM4372_IOPAD(0x95C, PIN_OUTPUT | MUX_MODE0) /* spi0_cs0.spi0_cs0 */ - >; - }; - - nand_flash_x8: nand_flash_x8 { - pinctrl-single,pins = < - AM4372_IOPAD(0x800, PIN_INPUT | PULL_DISABLE | MUX_MODE0) - AM4372_IOPAD(0x804, PIN_INPUT | PULL_DISABLE | MUX_MODE0) - AM4372_IOPAD(0x808, PIN_INPUT | PULL_DISABLE | MUX_MODE0) - AM4372_IOPAD(0x80c, PIN_INPUT | PULL_DISABLE | MUX_MODE0) - AM4372_IOPAD(0x810, PIN_INPUT | PULL_DISABLE | MUX_MODE0) - AM4372_IOPAD(0x814, PIN_INPUT | PULL_DISABLE | MUX_MODE0) - AM4372_IOPAD(0x818, PIN_INPUT | PULL_DISABLE | MUX_MODE0) - AM4372_IOPAD(0x81c, PIN_INPUT | PULL_DISABLE | MUX_MODE0) - AM4372_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x874, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x87c, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x898, PIN_OUTPUT_PULLDOWN | MUX_MODE0) - AM4372_IOPAD(0x894, PIN_OUTPUT_PULLDOWN | MUX_MODE0) - AM4372_IOPAD(0x890, PIN_OUTPUT_PULLDOWN | MUX_MODE0) - AM4372_IOPAD(0x89c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) - >; - }; - - cpsw_default: cpsw_default { - pinctrl-single,pins = < - /* Slave 1 */ - AM4372_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_txen */ - AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rxctl */ - AM4372_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd3 */ - AM4372_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd2 */ - AM4372_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd1 */ - AM4372_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd0 */ - AM4372_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rmii1_tclk */ - AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */ - AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd3 */ - AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd2 */ - AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd1 */ - AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd0 */ - AM4372_IOPAD(0xa74, MUX_MODE3) - /* Slave 2 */ - AM4372_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a0.txen */ - AM4372_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a1.rxctl */ - AM4372_IOPAD(0x848, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a2.txd3 */ - AM4372_IOPAD(0x84c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a3.txd2 */ - AM4372_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a4.txd1 */ - AM4372_IOPAD(0x854, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a5.txd0 */ - AM4372_IOPAD(0x858, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a6.tclk */ - AM4372_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a7.rclk */ - AM4372_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a8.rxd3 */ - AM4372_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a9.rxd2 */ - AM4372_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a10.rxd1 */ - AM4372_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a11.rxd0 */ - AM4372_IOPAD(0xa38, MUX_MODE7) - >; - }; - - davinci_mdio_default: davinci_mdio_default { - pinctrl-single,pins = < - /* MDIO */ - AM4372_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ - AM4372_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ - >; - }; -}; - -&gpmc { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&nand_flash_x8>; - ranges = <0 0 0x08000000 0x1000000>; - nand@0,0 { - compatible = "ti,omap2-nand"; - reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ - <1 IRQ_TYPE_NONE>; /* termcount */ - ti,nand-ecc-opt = "bch8"; - ti,elm-id = <&elm>; - - nand-bus-width = <8>; - gpmc,device-width = <1>; - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <44>; - gpmc,cs-wr-off-ns = <44>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <34>; - gpmc,adv-wr-off-ns = <44>; - gpmc,we-on-ns = <0>; - gpmc,we-off-ns = <40>; - gpmc,oe-on-ns = <0>; - gpmc,oe-off-ns = <54>; - gpmc,access-ns = <64>; - gpmc,rd-cycle-ns = <82>; - gpmc,wr-cycle-ns = <82>; - gpmc,bus-turnaround-ns = <0>; - gpmc,cycle2cycle-delay-ns = <0>; - gpmc,clk-activation-ns = <0>; - gpmc,wr-access-ns = <40>; - gpmc,wr-data-mux-bus-ns = <0>; - - #address-cells = <1>; - #size-cells = <1>; - /* MTD partition table */ - partition@0 { - label = "kernel"; - reg = <0x0 0x00980000>; - }; - partition@980000 { - label = "dtb"; - reg = <0x00980000 0x00080000>; - }; - partition@a00000 { - label = "rootfs"; - reg = <0x00a00000 0x0>; - }; - }; -}; - -&i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - clock-frequency = <100000>; - - tps65218: tps65218@24 { - compatible = "ti,tps65218"; - reg = <0x24>; - interrupts = ; /* NMIn */ - interrupt-parent = <&gic>; - interrupt-controller; - #interrupt-cells = <2>; - - dcdc1: regulator-dcdc1 { - regulator-name = "vdd_core"; - regulator-min-microvolt = <912000>; - regulator-max-microvolt = <1144000>; - regulator-boot-on; - regulator-always-on; - }; - - dcdc2: regulator-dcdc2 { - regulator-name = "vdd_mpu"; - regulator-min-microvolt = <912000>; - regulator-max-microvolt = <1378000>; - regulator-boot-on; - regulator-always-on; - }; - - dcdc3: regulator-dcdc3 { - regulator-name = "vdcdc3"; - regulator-suspend-enable; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - regulator-always-on; - }; - - dcdc5: regulator-dcdc5 { - regulator-name = "v1_0bat"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-boot-on; - regulator-always-on; - }; - - dcdc6: regulator-dcdc6 { - regulator-name = "v1_8bat"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1: regulator-ldo1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - }; - - eeprom_module: at24@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&gpio2 { - status = "okay"; -}; - -&gpio3 { - status = "okay"; -}; - -&gpio4 { - status = "okay"; -}; - -&gpio5 { - status = "okay"; -}; - -&mmc2 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_pins>; - vmmc-supply = <&vmmc_3v3>; - bus-width = <8>; - ti,non-removable; -}; - -&spi0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins>; - dmas = <&edma 16 0 - &edma 17 0>; - dma-names = "tx0", "rx0"; - - flash: w25q64cvzpig@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <20000000>; - partition@0 { - label = "uboot"; - reg = <0x0 0xc0000>; - }; - - partition@c0000 { - label = "uboot environment"; - reg = <0xc0000 0x40000>; - }; - - partition@100000 { - label = "reserved"; - reg = <0x100000 0x100000>; - }; - }; -}; - -&mac { - pinctrl-names = "default"; - pinctrl-0 = <&cpsw_default>; - dual_emac = <1>; - status = "okay"; -}; - -&davinci_mdio { - pinctrl-names = "default"; - pinctrl-0 = <&davinci_mdio_default>; - status = "okay"; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; - - ethphy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&cpsw_emac0 { - phy-handle = <ðphy0>; - phy-mode = "rgmii-txid"; - dual_emac_res_vlan = <1>; -}; - -&cpsw_emac1 { - phy-handle = <ðphy1>; - phy-mode = "rgmii-txid"; - dual_emac_res_vlan = <2>; -}; - -&dwc3_1 { - status = "okay"; -}; - -&usb2_phy1 { - status = "okay"; -}; - -&usb1 { - dr_mode = "host"; - status = "okay"; -}; - -&dwc3_2 { - status = "okay"; -}; - -&usb2_phy2 { - status = "okay"; -}; - -&usb2 { - dr_mode = "host"; - status = "okay"; - interrupts = , - , - ; - interrupt-names = "peripheral", "host", "otg"; -}; - -&elm { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&tscadc { - status = "okay"; - tsc { - ti,wires = <4>; - ti,x-plate-resistance = <200>; - ti,coordiante-readouts = <5>; - ti,wire-config = <0x00 0x11 0x22 0x33>; - }; - - adc { - ti,adc-channels = <4 5 6 7>; - }; -}; - -&cpu { - cpu0-supply = <&dcdc2>; - operating-points = <1000000 1330000>, - <800000 1260000>, - <720000 1200000>, - <600000 1100000>, - <300000 950000>; -}; diff --git a/sys/gnu/dts/arm/am437x-gp-evm.dts b/sys/gnu/dts/arm/am437x-gp-evm.dts deleted file mode 100644 index cae4500194f..00000000000 --- a/sys/gnu/dts/arm/am437x-gp-evm.dts +++ /dev/null @@ -1,1130 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ - */ - -/* AM437x GP EVM */ - -/dts-v1/; - -#include "am4372.dtsi" -#include -#include -#include - -/ { - model = "TI AM437x GP EVM"; - compatible = "ti,am437x-gp-evm","ti,am4372","ti,am43"; - - aliases { - display0 = &lcd0; - }; - - chosen { - stdout-path = &uart0; - }; - - evm_v3_3d: fixedregulator-v3_3d { - compatible = "regulator-fixed"; - regulator-name = "evm_v3_3d"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - }; - - vtt_fixed: fixedregulator-vtt { - compatible = "regulator-fixed"; - regulator-name = "vtt_fixed"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>; - }; - - vmmcwl_fixed: fixedregulator-mmcwl { - compatible = "regulator-fixed"; - regulator-name = "vmmcwl_fixed"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio1 20 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - lcd_bl: backlight { - compatible = "pwm-backlight"; - pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>; - brightness-levels = <0 51 53 56 62 75 101 152 255>; - default-brightness-level = <8>; - }; - - matrix_keypad: matrix_keypad0 { - compatible = "gpio-matrix-keypad"; - debounce-delay-ms = <5>; - col-scan-delay-us = <2>; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&matrix_keypad_default>; - pinctrl-1 = <&matrix_keypad_sleep>; - - wakeup-source; - - row-gpios = <&gpio0 3 GPIO_ACTIVE_HIGH /* Bank0, pin3 */ - &gpio4 3 GPIO_ACTIVE_HIGH /* Bank4, pin3 */ - &gpio4 2 GPIO_ACTIVE_HIGH>; /* Bank4, pin2 */ - - col-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH /* Bank3, pin19 */ - &gpio3 20 GPIO_ACTIVE_HIGH>; /* Bank3, pin20 */ - - linux,keymap = <0x00000201 /* P1 */ - 0x00010202 /* P2 */ - 0x01000067 /* UP */ - 0x0101006a /* RIGHT */ - 0x02000069 /* LEFT */ - 0x0201006c>; /* DOWN */ - }; - - lcd0: display { - compatible = "osddisplays,osd057T0559-34ts", "panel-dpi"; - label = "lcd"; - - backlight = <&lcd_bl>; - - panel-timing { - clock-frequency = <33000000>; - hactive = <800>; - vactive = <480>; - hfront-porch = <210>; - hback-porch = <16>; - hsync-len = <30>; - vback-porch = <10>; - vfront-porch = <22>; - vsync-len = <13>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - - port { - lcd_in: endpoint { - remote-endpoint = <&dpi_out>; - }; - }; - }; - - /* fixed 12MHz oscillator */ - refclk: oscillator { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <12000000>; - }; - - /* fixed 32k external oscillator clock */ - clk_32k_rtc: clk_32k_rtc { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - sound0: sound0 { - compatible = "simple-audio-card"; - simple-audio-card,name = "AM437x-GP-EVM"; - simple-audio-card,widgets = - "Headphone", "Headphone Jack", - "Line", "Line In"; - simple-audio-card,routing = - "Headphone Jack", "HPLOUT", - "Headphone Jack", "HPROUT", - "LINE1L", "Line In", - "LINE1R", "Line In"; - simple-audio-card,format = "dsp_b"; - simple-audio-card,bitclock-master = <&sound0_master>; - simple-audio-card,frame-master = <&sound0_master>; - simple-audio-card,bitclock-inversion; - - simple-audio-card,cpu { - sound-dai = <&mcasp1>; - system-clock-frequency = <12000000>; - }; - - sound0_master: simple-audio-card,codec { - sound-dai = <&tlv320aic3106>; - system-clock-frequency = <12000000>; - }; - }; - - beeper: beeper { - compatible = "gpio-beeper"; - pinctrl-names = "default"; - pinctrl-0 = <&beeper_pins_default>; - pinctrl-1 = <&beeper_pins_sleep>; - gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>; - }; -}; - -&am43xx_pinmux { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&wlan_pins_default &ddr3_vtt_toggle_default &unused_pins &debugss_pins>; - pinctrl-1 = <&wlan_pins_sleep>; - - ddr3_vtt_toggle_default: ddr_vtt_toggle_default { - pinctrl-single,pins = < - 0x25C (DS0_PULL_UP_DOWN_EN | PIN_OUTPUT_PULLUP | DS0_FORCE_OFF_MODE | MUX_MODE7) /* spi0_cs0.gpio5_7 */ - >; - }; - - i2c0_pins: i2c0_pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x988, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */ - AM4372_IOPAD(0x98c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */ - >; - }; - - i2c1_pins: i2c1_pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x95c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_cs0.i2c1_scl */ - AM4372_IOPAD(0x958, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_d1.i2c1_sda */ - >; - }; - - mmc1_pins: pinmux_mmc1_pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ - >; - }; - - ecap0_pins: backlight_pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x964, MUX_MODE0) /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */ - >; - }; - - pixcir_ts_pins: pixcir_ts_pins { - pinctrl-single,pins = < - AM4372_IOPAD(0xa64, PIN_INPUT_PULLUP | MUX_MODE7) /* spi2_d0.gpio3_22 */ - >; - }; - - cpsw_default: cpsw_default { - pinctrl-single,pins = < - /* Slave 1 */ - AM4372_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_txen */ - AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rxctl */ - AM4372_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd3 */ - AM4372_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd2 */ - AM4372_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd1 */ - AM4372_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd0 */ - AM4372_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rmii1_tclk */ - AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */ - AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd3 */ - AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd2 */ - AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd1 */ - AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd0 */ - >; - }; - - cpsw_sleep: cpsw_sleep { - pinctrl-single,pins = < - /* Slave 1 reset value */ - AM4372_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; - - davinci_mdio_default: davinci_mdio_default { - pinctrl-single,pins = < - /* MDIO */ - AM4372_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ - AM4372_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ - >; - }; - - davinci_mdio_sleep: davinci_mdio_sleep { - pinctrl-single,pins = < - /* MDIO reset value */ - AM4372_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; - - nand_flash_x8: nand_flash_x8 { - pinctrl-single,pins = < - AM4372_IOPAD(0x800, PIN_INPUT | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ - AM4372_IOPAD(0x804, PIN_INPUT | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ - AM4372_IOPAD(0x808, PIN_INPUT | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ - AM4372_IOPAD(0x80c, PIN_INPUT | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ - AM4372_IOPAD(0x810, PIN_INPUT | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ - AM4372_IOPAD(0x814, PIN_INPUT | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ - AM4372_IOPAD(0x818, PIN_INPUT | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ - AM4372_IOPAD(0x81c, PIN_INPUT | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ - AM4372_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ - AM4372_IOPAD(0x874, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpmc_wpn */ - AM4372_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ - AM4372_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ - AM4372_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ - AM4372_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */ - AM4372_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ - >; - }; - - dss_pins: dss_pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x820, PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */ - AM4372_IOPAD(0x824, PIN_OUTPUT_PULLUP | MUX_MODE1) - AM4372_IOPAD(0x828, PIN_OUTPUT_PULLUP | MUX_MODE1) - AM4372_IOPAD(0x82c, PIN_OUTPUT_PULLUP | MUX_MODE1) - AM4372_IOPAD(0x830, PIN_OUTPUT_PULLUP | MUX_MODE1) - AM4372_IOPAD(0x834, PIN_OUTPUT_PULLUP | MUX_MODE1) - AM4372_IOPAD(0x838, PIN_OUTPUT_PULLUP | MUX_MODE1) - AM4372_IOPAD(0x83c, PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 15 -> DSS DATA 16 */ - AM4372_IOPAD(0x8a0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */ - AM4372_IOPAD(0x8a4, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8a8, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8ac, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8b0, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8b4, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8b8, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8bc, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8c0, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8c4, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8c8, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8cc, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8d0, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8d4, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8d8, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8dc, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */ - AM4372_IOPAD(0x8e0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */ - AM4372_IOPAD(0x8e4, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */ - AM4372_IOPAD(0x8e8, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */ - AM4372_IOPAD(0x8ec, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */ - - >; - }; - - display_mux_pins: display_mux_pins { - pinctrl-single,pins = < - /* GPIO 5_8 to select LCD / HDMI */ - AM4372_IOPAD(0xa38, PIN_OUTPUT_PULLUP | MUX_MODE7) - >; - }; - - dcan0_default: dcan0_default_pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x978, PIN_OUTPUT | MUX_MODE2) /* uart1_ctsn.d_can0_tx */ - AM4372_IOPAD(0x97c, PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_rtsn.d_can0_rx */ - >; - }; - - dcan0_sleep: dcan0_sleep_pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x978, PIN_INPUT_PULLUP | MUX_MODE7) /* uart1_ctsn.gpio0_12 */ - AM4372_IOPAD(0x97c, PIN_INPUT_PULLUP | MUX_MODE7) /* uart1_rtsn.gpio0_13 */ - >; - }; - - dcan1_default: dcan1_default_pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x980, PIN_OUTPUT | MUX_MODE2) /* uart1_rxd.d_can1_tx */ - AM4372_IOPAD(0x984, PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_txd.d_can1_rx */ - >; - }; - - dcan1_sleep: dcan1_sleep_pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE7) /* uart1_rxd.gpio0_14 */ - AM4372_IOPAD(0x984, PIN_INPUT_PULLUP | MUX_MODE7) /* uart1_txd.gpio0_15 */ - >; - }; - - vpfe0_pins_default: vpfe0_pins_default { - pinctrl-single,pins = < - AM4372_IOPAD(0x9b0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_hd mode 0*/ - AM4372_IOPAD(0x9b4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_vd mode 0*/ - AM4372_IOPAD(0x9c0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_pclk mode 0*/ - AM4372_IOPAD(0x9c4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data8 mode 0*/ - AM4372_IOPAD(0x9c8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data9 mode 0*/ - AM4372_IOPAD(0xa08, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data0 mode 0*/ - AM4372_IOPAD(0xa0c, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data1 mode 0*/ - AM4372_IOPAD(0xa10, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data2 mode 0*/ - AM4372_IOPAD(0xa14, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data3 mode 0*/ - AM4372_IOPAD(0xa18, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data4 mode 0*/ - AM4372_IOPAD(0xa1c, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data5 mode 0*/ - AM4372_IOPAD(0xa20, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data6 mode 0*/ - AM4372_IOPAD(0xa24, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data7 mode 0*/ - >; - }; - - vpfe0_pins_sleep: vpfe0_pins_sleep { - pinctrl-single,pins = < - AM4372_IOPAD(0x9b0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_hd mode 0*/ - AM4372_IOPAD(0x9b4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_vd mode 0*/ - AM4372_IOPAD(0x9c0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_pclk mode 0*/ - AM4372_IOPAD(0x9c4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data8 mode 0*/ - AM4372_IOPAD(0x9c8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data9 mode 0*/ - AM4372_IOPAD(0xa08, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data0 mode 0*/ - AM4372_IOPAD(0xa0c, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data1 mode 0*/ - AM4372_IOPAD(0xa10, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data2 mode 0*/ - AM4372_IOPAD(0xa14, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data3 mode 0*/ - AM4372_IOPAD(0xa18, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data4 mode 0*/ - AM4372_IOPAD(0xa1c, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data5 mode 0*/ - AM4372_IOPAD(0xa20, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data6 mode 0*/ - AM4372_IOPAD(0xa24, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data7 mode 0*/ - >; - }; - - vpfe1_pins_default: vpfe1_pins_default { - pinctrl-single,pins = < - AM4372_IOPAD(0x9cc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data9 mode 0*/ - AM4372_IOPAD(0x9d0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data8 mode 0*/ - AM4372_IOPAD(0x9d4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_hd mode 0*/ - AM4372_IOPAD(0x9d8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_vd mode 0*/ - AM4372_IOPAD(0x9dC, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_pclk mode 0*/ - AM4372_IOPAD(0x9e8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data0 mode 0*/ - AM4372_IOPAD(0x9ec, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data1 mode 0*/ - AM4372_IOPAD(0x9f0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data2 mode 0*/ - AM4372_IOPAD(0x9f4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data3 mode 0*/ - AM4372_IOPAD(0x9f8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data4 mode 0*/ - AM4372_IOPAD(0x9fc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data5 mode 0*/ - AM4372_IOPAD(0xa00, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data6 mode 0*/ - AM4372_IOPAD(0xa04, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data7 mode 0*/ - >; - }; - - vpfe1_pins_sleep: vpfe1_pins_sleep { - pinctrl-single,pins = < - AM4372_IOPAD(0x9cc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data9 mode 0*/ - AM4372_IOPAD(0x9d0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data8 mode 0*/ - AM4372_IOPAD(0x9d4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_hd mode 0*/ - AM4372_IOPAD(0x9d8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_vd mode 0*/ - AM4372_IOPAD(0x9dc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_pclk mode 0*/ - AM4372_IOPAD(0x9e8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data0 mode 0*/ - AM4372_IOPAD(0x9ec, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data1 mode 0*/ - AM4372_IOPAD(0x9f0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data2 mode 0*/ - AM4372_IOPAD(0x9f4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data3 mode 0*/ - AM4372_IOPAD(0x9f8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data4 mode 0*/ - AM4372_IOPAD(0x9fc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data5 mode 0*/ - AM4372_IOPAD(0xa00, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data6 mode 0*/ - AM4372_IOPAD(0xa04, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data7 mode 0*/ - >; - }; - - mmc3_pins_default: pinmux_mmc3_pins_default { - pinctrl-single,pins = < - AM4372_IOPAD(0x88c, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_clk.mmc2_clk */ - AM4372_IOPAD(0x888, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_csn3.mmc2_cmd */ - AM4372_IOPAD(0x844, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a1.mmc2_dat0 */ - AM4372_IOPAD(0x848, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a2.mmc2_dat1 */ - AM4372_IOPAD(0x84c, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a3.mmc2_dat2 */ - AM4372_IOPAD(0x878, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_be1n.mmc2_dat3 */ - >; - }; - - mmc3_pins_sleep: pinmux_mmc3_pins_sleep { - pinctrl-single,pins = < - AM4372_IOPAD(0x88c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_clk.mmc2_clk */ - AM4372_IOPAD(0x888, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn3.mmc2_cmd */ - AM4372_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a1.mmc2_dat0 */ - AM4372_IOPAD(0x848, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a2.mmc2_dat1 */ - AM4372_IOPAD(0x84c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a3.mmc2_dat2 */ - AM4372_IOPAD(0x878, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_be1n.mmc2_dat3 */ - >; - }; - - wlan_pins_default: pinmux_wlan_pins_default { - pinctrl-single,pins = < - AM4372_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a4.gpio1_20 WL_EN */ - AM4372_IOPAD(0x85c, PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7) /* gpmc_a7.gpio1_23 WL_IRQ*/ - AM4372_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a0.gpio1_16 BT_EN*/ - >; - }; - - wlan_pins_sleep: pinmux_wlan_pins_sleep { - pinctrl-single,pins = < - AM4372_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a4.gpio1_20 WL_EN */ - AM4372_IOPAD(0x85c, PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7) /* gpmc_a7.gpio1_23 WL_IRQ*/ - AM4372_IOPAD(0x840, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a0.gpio1_16 BT_EN*/ - >; - }; - - uart3_pins: uart3_pins { - pinctrl-single,pins = < - AM4372_IOPAD(0xa28, PIN_INPUT | MUX_MODE0) /* uart3_rxd.uart3_rxd */ - AM4372_IOPAD(0xa2c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart3_txd.uart3_txd */ - AM4372_IOPAD(0xa30, PIN_INPUT_PULLUP | MUX_MODE0) /* uart3_ctsn.uart3_ctsn */ - AM4372_IOPAD(0xa34, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart3_rtsn.uart3_rtsn */ - >; - }; - - mcasp1_pins: mcasp1_pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x908, PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */ - AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */ - AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */ - AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */ - >; - }; - - mcasp1_sleep_pins: mcasp1_sleep_pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x908, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; - - gpio0_pins: gpio0_pins { - pinctrl-single,pins = < - AM4372_IOPAD(0xa6c, PIN_OUTPUT | MUX_MODE9) /* spi2_cs0.gpio0_23 SEL_eMMCorNANDn */ - >; - }; - - emmc_pins_default: emmc_pins_default { - pinctrl-single,pins = < - AM4372_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ - AM4372_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ - AM4372_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ - AM4372_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ - AM4372_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ - AM4372_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ - AM4372_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ - AM4372_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ - AM4372_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */ - AM4372_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ - >; - }; - - emmc_pins_sleep: emmc_pins_sleep { - pinctrl-single,pins = < - AM4372_IOPAD(0x800, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad0.gpio1_0 */ - AM4372_IOPAD(0x804, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad1.gpio1_1 */ - AM4372_IOPAD(0x808, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad2.gpio1_2 */ - AM4372_IOPAD(0x80c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad3.gpio1_3 */ - AM4372_IOPAD(0x810, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad4.gpio1_4 */ - AM4372_IOPAD(0x814, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad5.gpio1_5 */ - AM4372_IOPAD(0x818, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad6.gpio1_6 */ - AM4372_IOPAD(0x81c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad7.gpio1_7 */ - AM4372_IOPAD(0x880, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn1.gpio1_30 */ - AM4372_IOPAD(0x884, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn2.gpio1_31 */ - >; - }; - - beeper_pins_default: beeper_pins_default { - pinctrl-single,pins = < - AM4372_IOPAD(0x9e0, PIN_OUTPUT_PULLUP | MUX_MODE7) /* cam1_field.gpio4_12 */ - >; - }; - - beeper_pins_sleep: beeper_pins_sleep { - pinctrl-single,pins = < - AM4372_IOPAD(0x9e0, PIN_INPUT_PULLDOWN | MUX_MODE7) /* cam1_field.gpio4_12 */ - >; - }; - - unused_pins: unused_pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x854, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x858, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x950, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x990, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x994, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x998, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x99c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x9a0, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0xa3c, PIN_INPUT | PULL_DISABLE | MUX_MODE7) - AM4372_IOPAD(0xa40, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0xa44, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0xa48, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0xa4c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0xa50, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0xa54, PIN_INPUT | PULL_DISABLE | MUX_MODE7) - AM4372_IOPAD(0xa58, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0xa60, PIN_INPUT | PULL_DISABLE | MUX_MODE7) - AM4372_IOPAD(0xa68, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0xa70, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0xa78, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0xa7c, PIN_INPUT | PULL_DISABLE) - AM4372_IOPAD(0xac8, PIN_INPUT_PULLDOWN) - AM4372_IOPAD(0xad4, PIN_INPUT_PULLDOWN) - AM4372_IOPAD(0xad8, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0xadc, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0xae0, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0xae4, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0xae8, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0xaec, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0xaf0, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0xaf4, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0xaf8, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0xafc, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0xb00, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0xb04, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0xb08, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0xb0c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0xb10, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0xb14, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0xb18, PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; - - debugss_pins: pinmux_debugss_pins { - pinctrl-single,pins = < - AM4372_IOPAD(0xa90, PIN_INPUT_PULLDOWN) - AM4372_IOPAD(0xa94, PIN_INPUT_PULLDOWN) - AM4372_IOPAD(0xa98, PIN_INPUT_PULLDOWN) - AM4372_IOPAD(0xa9c, PIN_INPUT_PULLDOWN) - AM4372_IOPAD(0xaa0, PIN_INPUT_PULLDOWN) - AM4372_IOPAD(0xaa4, PIN_INPUT_PULLDOWN) - AM4372_IOPAD(0xaa8, PIN_INPUT_PULLDOWN) - >; - }; - - uart0_pins_default: uart0_pins_default { - pinctrl-single,pins = < - AM4372_IOPAD(0x968, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE0) /* uart0_ctsn.uart0_ctsn */ - AM4372_IOPAD(0x96C, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE0) /* uart0_rtsn.uart0_rtsn */ - AM4372_IOPAD(0x970, PIN_INPUT_PULLUP | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_rxd.uart0_rxd */ - AM4372_IOPAD(0x974, PIN_INPUT | PULL_DISABLE | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_txd.uart0_txd */ - >; - }; - - uart0_pins_sleep: uart0_pins_sleep { - pinctrl-single,pins = < - AM4372_IOPAD(0x968, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* uart0_ctsn.uart0_ctsn */ - AM4372_IOPAD(0x96C, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* uart0_rtsn.uart0_rtsn */ - AM4372_IOPAD(0x970, PIN_INPUT_PULLUP | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_rxd.uart0_rxd */ - AM4372_IOPAD(0x974, PIN_INPUT_PULLDOWN | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_txd.uart0_txd */ - >; - }; - - matrix_keypad_default: matrix_keypad_default { - pinctrl-single,pins = < - AM4372_IOPAD(0x9a4, PIN_OUTPUT | MUX_MODE7) - AM4372_IOPAD(0x9a8, PIN_OUTPUT | MUX_MODE7) - AM4372_IOPAD(0x9ac, PIN_INPUT | PULL_DISABLE | MUX_MODE9) - AM4372_IOPAD(0x954, PIN_INPUT_PULLDOWN | MUX_MODE0) - >; - }; - - matrix_keypad_sleep: matrix_keypad_sleep { - pinctrl-single,pins = < - AM4372_IOPAD(0x9a4, PULL_UP | MUX_MODE7) - AM4372_IOPAD(0x9a8, PULL_UP | MUX_MODE7) - AM4372_IOPAD(0x9ac, PIN_INPUT | PULL_DISABLE | MUX_MODE9) - AM4372_IOPAD(0x954, PIN_INPUT_PULLDOWN | MUX_MODE0) - >; - }; -}; - -&uart0 { - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&uart0_pins_default>; - pinctrl-1 = <&uart0_pins_sleep>; -}; - -&i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - clock-frequency = <100000>; - - tps65218: tps65218@24 { - reg = <0x24>; - compatible = "ti,tps65218"; - interrupts = ; /* NMIn */ - interrupt-controller; - #interrupt-cells = <2>; - - dcdc1: regulator-dcdc1 { - regulator-name = "vdd_core"; - regulator-min-microvolt = <912000>; - regulator-max-microvolt = <1144000>; - regulator-boot-on; - regulator-always-on; - }; - - dcdc2: regulator-dcdc2 { - regulator-name = "vdd_mpu"; - regulator-min-microvolt = <912000>; - regulator-max-microvolt = <1378000>; - regulator-boot-on; - regulator-always-on; - }; - - dcdc3: regulator-dcdc3 { - regulator-name = "vdcdc3"; - regulator-boot-on; - regulator-always-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - regulator-state-disk { - regulator-off-in-suspend; - }; - }; - - dcdc5: regulator-dcdc5 { - regulator-name = "v1_0bat"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-boot-on; - regulator-always-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - dcdc6: regulator-dcdc6 { - regulator-name = "v1_8bat"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - ldo1: regulator-ldo1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - }; - - ov2659@30 { - compatible = "ovti,ov2659"; - reg = <0x30>; - - clocks = <&refclk 0>; - clock-names = "xvclk"; - - port { - ov2659_0: endpoint { - remote-endpoint = <&vpfe1_ep>; - link-frequencies = /bits/ 64 <70000000>; - }; - }; - }; -}; - -&i2c1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - pixcir_ts@5c { - compatible = "pixcir,pixcir_tangoc"; - pinctrl-names = "default"; - pinctrl-0 = <&pixcir_ts_pins>; - reg = <0x5c>; - - attb-gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; - - /* - * 0x264 represents the offset of padconf register of - * gpio3_22 from am43xx_pinmux base. - */ - interrupts-extended = <&gpio3 22 IRQ_TYPE_EDGE_FALLING>, - <&am43xx_pinmux 0x264>; - interrupt-names = "tsc", "wakeup"; - - touchscreen-size-x = <1024>; - touchscreen-size-y = <600>; - wakeup-source; - }; - - ov2659@30 { - compatible = "ovti,ov2659"; - reg = <0x30>; - - clocks = <&refclk 0>; - clock-names = "xvclk"; - - port { - ov2659_1: endpoint { - remote-endpoint = <&vpfe0_ep>; - link-frequencies = /bits/ 64 <70000000>; - }; - }; - }; - - tlv320aic3106: tlv320aic3106@1b { - #sound-dai-cells = <0>; - compatible = "ti,tlv320aic3106"; - reg = <0x1b>; - status = "okay"; - - /* Regulators */ - IOVDD-supply = <&evm_v3_3d>; /* V3_3D -> EN: V1_8D -> VBAT */ - AVDD-supply = <&evm_v3_3d>; /* v3_3AUD -> V3_3D -> ... */ - DRVDD-supply = <&evm_v3_3d>; /* v3_3AUD -> V3_3D -> ... */ - DVDD-supply = <&ldo1>; /* V1_8D -> LDO1 */ - }; -}; - -&epwmss0 { - status = "okay"; -}; - -&tscadc { - status = "okay"; - - adc { - ti,adc-channels = <0 1 2 3 4 5 6 7>; - }; -}; - -&ecap0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&ecap0_pins>; -}; - -&gpio0 { - pinctrl-names = "default"; - pinctrl-0 = <&gpio0_pins>; - status = "okay"; - - p23 { - gpio-hog; - gpios = <23 GPIO_ACTIVE_HIGH>; - /* SelEMMCorNAND selects between eMMC and NAND: - * Low: NAND - * High: eMMC - * When changing this line make sure the newly - * selected device node is enabled and the previously - * selected device node is disabled. - */ - output-low; - line-name = "SelEMMCorNAND"; - }; -}; - -&gpio1 { - status = "okay"; -}; - -&gpio3 { - status = "okay"; -}; - -&gpio4 { - status = "okay"; -}; - -&gpio5 { - pinctrl-names = "default"; - pinctrl-0 = <&display_mux_pins>; - status = "okay"; - ti,no-reset-on-init; - - p8 { - /* - * SelLCDorHDMI selects between display and audio paths: - * Low: HDMI display with audio via HDMI - * High: LCD display with analog audio via aic3111 codec - */ - gpio-hog; - gpios = <8 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "SelLCDorHDMI"; - }; -}; - -&mmc1 { - status = "okay"; - vmmc-supply = <&evm_v3_3d>; - bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; -}; - -/* eMMC sits on mmc2 */ -&mmc2 { - /* - * When enabling eMMC, disable GPMC/NAND and set - * SelEMMCorNAND to output-high - */ - status = "disabled"; - vmmc-supply = <&evm_v3_3d>; - bus-width = <8>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&emmc_pins_default>; - pinctrl-1 = <&emmc_pins_sleep>; - ti,non-removable; -}; - -&mmc3 { - status = "okay"; - /* these are on the crossbar and are outlined in the - xbar-event-map element */ - dmas = <&edma_xbar 30 0 1>, - <&edma_xbar 31 0 2>; - dma-names = "tx", "rx"; - vmmc-supply = <&vmmcwl_fixed>; - bus-width = <4>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&mmc3_pins_default>; - pinctrl-1 = <&mmc3_pins_sleep>; - cap-power-off-card; - keep-power-in-suspend; - ti,non-removable; - - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@0 { - compatible = "ti,wl1835"; - reg = <2>; - interrupt-parent = <&gpio1>; - interrupts = <23 IRQ_TYPE_EDGE_RISING>; - }; -}; - -&uart3 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; -}; - -&usb2_phy1 { - status = "okay"; -}; - -&usb1 { - dr_mode = "otg"; - status = "okay"; -}; - -&usb2_phy2 { - status = "okay"; -}; - -&usb2 { - dr_mode = "host"; - status = "okay"; -}; - -&mac { - slaves = <1>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&cpsw_default>; - pinctrl-1 = <&cpsw_sleep>; - status = "okay"; -}; - -&davinci_mdio { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&davinci_mdio_default>; - pinctrl-1 = <&davinci_mdio_sleep>; - status = "okay"; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -&cpsw_emac0 { - phy-handle = <ðphy0>; - phy-mode = "rgmii"; -}; - -&elm { - status = "okay"; -}; - -&gpmc { - /* - * When enabling GPMC, disable eMMC and set - * SelEMMCorNAND to output-low - */ - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&nand_flash_x8>; - ranges = <0 0 0x08000000 0x01000000>; /* CS0 space. Min partition = 16MB */ - nand@0,0 { - compatible = "ti,omap2-nand"; - reg = <0 0 4>; /* device IO registers */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ - <1 IRQ_TYPE_NONE>; /* termcount */ - rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ - ti,nand-xfer-type = "prefetch-dma"; - ti,nand-ecc-opt = "bch16"; - ti,elm-id = <&elm>; - nand-bus-width = <8>; - gpmc,device-width = <1>; - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <40>; - gpmc,cs-wr-off-ns = <40>; - gpmc,adv-on-ns = <0>; - gpmc,adv-rd-off-ns = <25>; - gpmc,adv-wr-off-ns = <25>; - gpmc,we-on-ns = <0>; - gpmc,we-off-ns = <20>; - gpmc,oe-on-ns = <3>; - gpmc,oe-off-ns = <30>; - gpmc,access-ns = <30>; - gpmc,rd-cycle-ns = <40>; - gpmc,wr-cycle-ns = <40>; - gpmc,bus-turnaround-ns = <0>; - gpmc,cycle2cycle-delay-ns = <0>; - gpmc,clk-activation-ns = <0>; - gpmc,wr-access-ns = <40>; - gpmc,wr-data-mux-bus-ns = <0>; - /* MTD partition table */ - /* All SPL-* partitions are sized to minimal length - * which can be independently programmable. For - * NAND flash this is equal to size of erase-block */ - #address-cells = <1>; - #size-cells = <1>; - partition@0 { - label = "NAND.SPL"; - reg = <0x00000000 0x00040000>; - }; - partition@1 { - label = "NAND.SPL.backup1"; - reg = <0x00040000 0x00040000>; - }; - partition@2 { - label = "NAND.SPL.backup2"; - reg = <0x00080000 0x00040000>; - }; - partition@3 { - label = "NAND.SPL.backup3"; - reg = <0x000c0000 0x00040000>; - }; - partition@4 { - label = "NAND.u-boot-spl-os"; - reg = <0x00100000 0x00080000>; - }; - partition@5 { - label = "NAND.u-boot"; - reg = <0x00180000 0x00100000>; - }; - partition@6 { - label = "NAND.u-boot-env"; - reg = <0x00280000 0x00040000>; - }; - partition@7 { - label = "NAND.u-boot-env.backup1"; - reg = <0x002c0000 0x00040000>; - }; - partition@8 { - label = "NAND.kernel"; - reg = <0x00300000 0x00700000>; - }; - partition@9 { - label = "NAND.file-system"; - reg = <0x00a00000 0x1f600000>; - }; - }; -}; - -&dss { - status = "ok"; - - pinctrl-names = "default"; - pinctrl-0 = <&dss_pins>; - - port { - dpi_out: endpoint { - remote-endpoint = <&lcd_in>; - data-lines = <24>; - }; - }; -}; - -&dcan0 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&dcan0_default>; - pinctrl-1 = <&dcan0_sleep>; - status = "okay"; -}; - -&dcan1 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&dcan1_default>; - pinctrl-1 = <&dcan1_sleep>; - status = "okay"; -}; - -&vpfe0 { - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&vpfe0_pins_default>; - pinctrl-1 = <&vpfe0_pins_sleep>; - - port { - vpfe0_ep: endpoint { - remote-endpoint = <&ov2659_1>; - ti,am437x-vpfe-interface = <0>; - bus-width = <8>; - hsync-active = <0>; - vsync-active = <0>; - }; - }; -}; - -&vpfe1 { - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&vpfe1_pins_default>; - pinctrl-1 = <&vpfe1_pins_sleep>; - - port { - vpfe1_ep: endpoint { - remote-endpoint = <&ov2659_0>; - ti,am437x-vpfe-interface = <0>; - bus-width = <8>; - hsync-active = <0>; - vsync-active = <0>; - }; - }; -}; - -&mcasp1 { - #sound-dai-cells = <0>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&mcasp1_pins>; - pinctrl-1 = <&mcasp1_sleep_pins>; - - status = "okay"; - - op-mode = <0>; /* MCASP_IIS_MODE */ - tdm-slots = <2>; - /* 4 serializers */ - serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ - 0 0 1 2 - >; - tx-num-evt = <32>; - rx-num-evt = <32>; -}; - -&rtc { - clocks = <&clk_32k_rtc>, <&clk_32768_ck>; - clock-names = "ext-clk", "int-clk"; - status = "okay"; -}; - -&cpu { - cpu0-supply = <&dcdc2>; -}; diff --git a/sys/gnu/dts/arm/am437x-idk-evm.dts b/sys/gnu/dts/arm/am437x-idk-evm.dts deleted file mode 100644 index f3ced6df0c9..00000000000 --- a/sys/gnu/dts/arm/am437x-idk-evm.dts +++ /dev/null @@ -1,536 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ - */ - -/dts-v1/; - -#include "am4372.dtsi" -#include -#include -#include -#include - -/ { - model = "TI AM437x Industrial Development Kit"; - compatible = "ti,am437x-idk-evm","ti,am4372","ti,am43"; - - chosen { - stdout-path = &uart0; - }; - - v24_0d: fixed-regulator-v24_0d { - compatible = "regulator-fixed"; - regulator-name = "V24_0D"; - regulator-min-microvolt = <24000000>; - regulator-max-microvolt = <24000000>; - regulator-always-on; - regulator-boot-on; - }; - - v3_3d: fixed-regulator-v3_3d { - compatible = "regulator-fixed"; - regulator-name = "V3_3D"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&v24_0d>; - }; - - vdd_corereg: fixed-regulator-vdd_corereg { - compatible = "regulator-fixed"; - regulator-name = "VDD_COREREG"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&v24_0d>; - }; - - vdd_core: fixed-regulator-vdd_core { - compatible = "regulator-fixed"; - regulator-name = "VDD_CORE"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vdd_corereg>; - }; - - v1_8dreg: fixed-regulator-v1_8dreg{ - compatible = "regulator-fixed"; - regulator-name = "V1_8DREG"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&v24_0d>; - }; - - v1_8d: fixed-regulator-v1_8d{ - compatible = "regulator-fixed"; - regulator-name = "V1_8D"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&v1_8dreg>; - }; - - v1_5dreg: fixed-regulator-v1_5dreg{ - compatible = "regulator-fixed"; - regulator-name = "V1_5DREG"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&v24_0d>; - }; - - v1_5d: fixed-regulator-v1_5d{ - compatible = "regulator-fixed"; - regulator-name = "V1_5D"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&v1_5dreg>; - }; - - gpio_keys: gpio_keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&gpio_keys_pins_default>; - #address-cells = <1>; - #size-cells = <0>; - - switch0 { - label = "power-button"; - linux,code = ; - gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; - }; - }; - - /* fixed 32k external oscillator clock */ - clk_32k_rtc: clk_32k_rtc { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - leds-iio { - status = "disabled"; - compatible = "gpio-leds"; - led-out0 { - label = "out0"; - gpios = <&tpic2810 0 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-out1 { - label = "out1"; - gpios = <&tpic2810 1 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-out2 { - label = "out2"; - gpios = <&tpic2810 2 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-out3 { - label = "out3"; - gpios = <&tpic2810 3 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-out4 { - label = "out4"; - gpios = <&tpic2810 4 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-out5 { - label = "out5"; - gpios = <&tpic2810 5 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-out6 { - label = "out6"; - gpios = <&tpic2810 6 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-out7 { - label = "out7"; - gpios = <&tpic2810 7 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; -}; - -&am43xx_pinmux { - gpio_keys_pins_default: gpio_keys_pins_default { - pinctrl-single,pins = < - AM4372_IOPAD(0x9b8, PIN_INPUT | MUX_MODE7) /* cam0_field.gpio4_2 */ - >; - }; - - i2c0_pins_default: i2c0_pins_default { - pinctrl-single,pins = < - AM4372_IOPAD(0x988, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */ - AM4372_IOPAD(0x98c, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */ - >; - }; - - i2c0_pins_sleep: i2c0_pins_sleep { - pinctrl-single,pins = < - AM4372_IOPAD(0x988, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x98c, PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; - - i2c2_pins_default: i2c2_pins_default { - pinctrl-single,pins = < - AM4372_IOPAD(0x9e8, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE3) /* cam1_data1.i2c2_scl */ - AM4372_IOPAD(0x9ec, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE3) /* cam1_data0.i2c2_sda */ - >; - }; - - i2c2_pins_sleep: i2c2_pins_sleep { - pinctrl-single,pins = < - AM4372_IOPAD(0x9e8, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x9ec, PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; - - mmc1_pins_default: pinmux_mmc1_pins_default { - pinctrl-single,pins = < - AM4372_IOPAD(0x900, PIN_INPUT | MUX_MODE0) /* mmc0_clk.mmc0_clk */ - AM4372_IOPAD(0x904, PIN_INPUT | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */ - AM4372_IOPAD(0x9f0, PIN_INPUT | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */ - AM4372_IOPAD(0x9f4, PIN_INPUT | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */ - AM4372_IOPAD(0x9f8, PIN_INPUT | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */ - AM4372_IOPAD(0x9fc, PIN_INPUT | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */ - AM4372_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ - >; - }; - - mmc1_pins_sleep: pinmux_mmc1_pins_sleep { - pinctrl-single,pins = < - AM4372_IOPAD(0x900, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x904, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x9f0, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x9f4, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x9f8, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x9fc, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x960, PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; - - spi1_pins_default: spi1_pins_default { - pinctrl-single,pins = < - AM4372_IOPAD(0x908, PIN_INPUT | MUX_MODE2) /* mii1_col.spi1_sclk */ - AM4372_IOPAD(0x910, PIN_INPUT | MUX_MODE2) /* mii1_rx_er.spi1_d1 */ - AM4372_IOPAD(0x944, PIN_OUTPUT | MUX_MODE2) /* rmii1_ref_clk.spi1_cs0 */ - AM4372_IOPAD(0x90c, PIN_OUTPUT | MUX_MODE7) /* mii1_crs.gpio3_1 */ - >; - }; - - spi1_pins_sleep: spi1_pins_sleep { - pinctrl-single,pins = < - AM4372_IOPAD(0x908, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; - - ecap0_pins_default: backlight_pins_default { - pinctrl-single,pins = < - AM4372_IOPAD(0x964, PIN_OUTPUT | MUX_MODE0) /* ecap0_in_pwm0_out.ecap0_in_pwm0_out */ - >; - }; - - cpsw_default: cpsw_default { - pinctrl-single,pins = < - AM4372_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */ - AM4372_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */ - AM4372_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ - AM4372_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ - AM4372_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td2 */ - AM4372_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td3 */ - AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */ - AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ - AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ - AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ - AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd2 */ - AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd3 */ - >; - }; - - cpsw_sleep: cpsw_sleep { - pinctrl-single,pins = < - AM4372_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; - - davinci_mdio_default: davinci_mdio_default { - pinctrl-single,pins = < - /* MDIO */ - AM4372_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ - AM4372_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ - >; - }; - - davinci_mdio_sleep: davinci_mdio_sleep { - pinctrl-single,pins = < - /* MDIO reset value */ - AM4372_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; - - qspi_pins_default: qspi_pins_default { - pinctrl-single,pins = < - AM4372_IOPAD(0x87c, PIN_OUTPUT_PULLUP | MUX_MODE3) /* gpmc_csn0.qspi_csn */ - AM4372_IOPAD(0x888, PIN_OUTPUT | MUX_MODE2) /* gpmc_csn3.qspi_clk */ - AM4372_IOPAD(0x890, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_advn_ale.qspi_d0 */ - AM4372_IOPAD(0x894, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_oen_ren.qspi_d1 */ - AM4372_IOPAD(0x898, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_wen.qspi_d2 */ - AM4372_IOPAD(0x89c, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_be0n_cle.qspi_d3 */ - >; - }; - - qspi_pins_sleep: qspi_pins_sleep{ - pinctrl-single,pins = < - AM4372_IOPAD(0x87c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x888, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x890, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x894, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x898, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x89c, PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; -}; - -&i2c0 { - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c0_pins_default>; - pinctrl-1 = <&i2c0_pins_sleep>; - clock-frequency = <400000>; - - at24@50 { - compatible = "atmel,24c256"; - pagesize = <64>; - reg = <0x50>; - }; - - tps: tps62362@60 { - compatible = "ti,tps62362"; - reg = <0x60>; - regulator-name = "VDD_MPU"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1330000>; - regulator-boot-on; - regulator-always-on; - ti,vsel0-state-high; - ti,vsel1-state-high; - vin-supply = <&v3_3d>; - }; -}; - -&i2c2 { - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c2_pins_default>; - pinctrl-1 = <&i2c2_pins_sleep>; - clock-frequency = <100000>; - - tpic2810: tpic2810@60 { - compatible = "ti,tpic2810"; - reg = <0x60>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -&spi1 { - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&spi1_pins_default>; - pinctrl-1 = <&spi1_pins_sleep>; - ti,pindir-d0-out-d1-in; - - sn65hvs882: sn65hvs882@0 { - compatible = "pisosr-gpio"; - gpio-controller; - #gpio-cells = <2>; - - load-gpios = <&gpio3 1 GPIO_ACTIVE_LOW>; - - reg = <0>; - spi-max-frequency = <1000000>; - spi-cpol; - }; -}; - -&epwmss0 { - status = "okay"; -}; - -&ecap0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&ecap0_pins_default>; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&gpio3 { - status = "okay"; -}; - -&gpio4 { - status = "okay"; -}; - -&gpio5 { - status = "okay"; -}; - -&mmc1 { - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&mmc1_pins_default>; - pinctrl-1 = <&mmc1_pins_sleep>; - vmmc-supply = <&v3_3d>; - bus-width = <4>; - cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; -}; - -&qspi { - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qspi_pins_default>; - pinctrl-1 = <&qspi_pins_sleep>; - - spi-max-frequency = <48000000>; - m25p80@0 { - compatible = "mx66l51235l"; - spi-max-frequency = <48000000>; - reg = <0>; - spi-cpol; - spi-cpha; - spi-tx-bus-width = <1>; - spi-rx-bus-width = <4>; - #address-cells = <1>; - #size-cells = <1>; - - /* - * MTD partition table. The ROM checks the first 512KiB for a - * valid file to boot(XIP). - */ - partition@0 { - label = "QSPI.U_BOOT"; - reg = <0x00000000 0x000080000>; - }; - partition@1 { - label = "QSPI.U_BOOT.backup"; - reg = <0x00080000 0x00080000>; - }; - partition@2 { - label = "QSPI.U-BOOT-SPL_OS"; - reg = <0x00100000 0x00010000>; - }; - partition@3 { - label = "QSPI.U_BOOT_ENV"; - reg = <0x00110000 0x00010000>; - }; - partition@4 { - label = "QSPI.U-BOOT-ENV.backup"; - reg = <0x00120000 0x00010000>; - }; - partition@5 { - label = "QSPI.KERNEL"; - reg = <0x00130000 0x0800000>; - }; - partition@6 { - label = "QSPI.FILESYSTEM"; - reg = <0x00930000 0x36D0000>; - }; - }; -}; - -&mac { - slaves = <1>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&cpsw_default>; - pinctrl-1 = <&cpsw_sleep>; - status = "okay"; -}; - -&davinci_mdio { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&davinci_mdio_default>; - pinctrl-1 = <&davinci_mdio_sleep>; - status = "okay"; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -&cpsw_emac0 { - phy-handle = <ðphy0>; - phy-mode = "rgmii"; -}; - -&rtc { - clocks = <&clk_32k_rtc>, <&clk_32768_ck>; - clock-names = "ext-clk", "int-clk"; - status = "okay"; -}; - -&wdt { - status = "okay"; -}; - -&cpu { - cpu0-supply = <&tps>; -}; - -&cpu0_opp_table { - /* - * Supply voltage supervisor on board will not allow opp50 so - * disable it and set opp100 as suspend OPP. - */ - opp50@300000000 { - status = "disabled"; - }; - - opp100@600000000 { - opp-suspend; - }; -}; diff --git a/sys/gnu/dts/arm/am437x-l4.dtsi b/sys/gnu/dts/arm/am437x-l4.dtsi deleted file mode 100644 index 59770dd3785..00000000000 --- a/sys/gnu/dts/arm/am437x-l4.dtsi +++ /dev/null @@ -1,2504 +0,0 @@ -&l4_wkup { /* 0x44c00000 */ - compatible = "ti,am4-l4-wkup", "simple-bus"; - reg = <0x44c00000 0x800>, - <0x44c00800 0x800>, - <0x44c01000 0x400>, - <0x44c01400 0x400>; - reg-names = "ap", "la", "ia0", "ia1"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x44c00000 0x100000>, /* segment 0 */ - <0x00100000 0x44d00000 0x100000>, /* segment 1 */ - <0x00200000 0x44e00000 0x100000>; /* segment 2 */ - - segment@0 { /* 0x44c00000 */ - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ - <0x00000800 0x00000800 0x000800>, /* ap 1 */ - <0x00001000 0x00001000 0x000400>, /* ap 2 */ - <0x00001400 0x00001400 0x000400>; /* ap 3 */ - }; - - segment@100000 { /* 0x44d00000 */ - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00100000 0x004000>, /* ap 4 */ - <0x00004000 0x00104000 0x001000>, /* ap 5 */ - <0x00080000 0x00180000 0x002000>, /* ap 6 */ - <0x00082000 0x00182000 0x001000>, /* ap 7 */ - <0x000f0000 0x001f0000 0x010000>; /* ap 8 */ - - target-module@0 { /* 0x44d00000, ap 4 28.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x4000>; - }; - - target-module@80000 { /* 0x44d80000, ap 6 10.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x80000 0x2000>; - }; - - target-module@f0000 { /* 0x44df0000, ap 8 58.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0xf0000 0x4>; - reg-names = "rev"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xf0000 0x10000>; - - prcm: prcm@0 { - compatible = "ti,am4-prcm", "simple-bus"; - reg = <0x0 0x11000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x11000>; - - prcm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - prcm_clockdomains: clockdomains { - }; - }; - }; - }; - - segment@200000 { /* 0x44e00000 */ - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00200000 0x001000>, /* ap 9 */ - <0x00003000 0x00203000 0x001000>, /* ap 10 */ - <0x00004000 0x00204000 0x001000>, /* ap 11 */ - <0x00005000 0x00205000 0x001000>, /* ap 12 */ - <0x00006000 0x00206000 0x001000>, /* ap 13 */ - <0x00007000 0x00207000 0x001000>, /* ap 14 */ - <0x00008000 0x00208000 0x001000>, /* ap 15 */ - <0x00009000 0x00209000 0x001000>, /* ap 16 */ - <0x0000a000 0x0020a000 0x001000>, /* ap 17 */ - <0x0000b000 0x0020b000 0x001000>, /* ap 18 */ - <0x0000c000 0x0020c000 0x001000>, /* ap 19 */ - <0x0000d000 0x0020d000 0x001000>, /* ap 20 */ - <0x0000f000 0x0020f000 0x001000>, /* ap 21 */ - <0x00010000 0x00210000 0x010000>, /* ap 22 */ - <0x00030000 0x00230000 0x001000>, /* ap 23 */ - <0x00031000 0x00231000 0x001000>, /* ap 24 */ - <0x00032000 0x00232000 0x001000>, /* ap 25 */ - <0x00033000 0x00233000 0x001000>, /* ap 26 */ - <0x00034000 0x00234000 0x001000>, /* ap 27 */ - <0x00035000 0x00235000 0x001000>, /* ap 28 */ - <0x00036000 0x00236000 0x001000>, /* ap 29 */ - <0x00037000 0x00237000 0x001000>, /* ap 30 */ - <0x00038000 0x00238000 0x001000>, /* ap 31 */ - <0x00039000 0x00239000 0x001000>, /* ap 32 */ - <0x0003a000 0x0023a000 0x001000>, /* ap 33 */ - <0x0003e000 0x0023e000 0x001000>, /* ap 34 */ - <0x0003f000 0x0023f000 0x001000>, /* ap 35 */ - <0x00040000 0x00240000 0x040000>, /* ap 36 */ - <0x00080000 0x00280000 0x001000>, /* ap 37 */ - <0x00088000 0x00288000 0x008000>, /* ap 38 */ - <0x00092000 0x00292000 0x001000>, /* ap 39 */ - <0x00086000 0x00286000 0x001000>, /* ap 40 */ - <0x00087000 0x00287000 0x001000>, /* ap 41 */ - <0x00090000 0x00290000 0x001000>, /* ap 42 */ - <0x00091000 0x00291000 0x001000>; /* ap 43 */ - - target-module@3000 { /* 0x44e03000, ap 10 0a.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x3000 0x1000>; - }; - - target-module@5000 { /* 0x44e05000, ap 12 30.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x5000 0x1000>; - }; - - target-module@7000 { /* 0x44e07000, ap 14 20.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "gpio1"; - reg = <0x7000 0x4>, - <0x7010 0x4>, - <0x7114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ - clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_GPIO1_CLKCTRL 0>, - <&l4_wkup_clkctrl AM4_L4_WKUP_GPIO1_CLKCTRL 8>; - clock-names = "fck", "dbclk"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x7000 0x1000>; - - gpio0: gpio@0 { - compatible = "ti,am4372-gpio","ti,omap4-gpio"; - reg = <0x0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - status = "disabled"; - }; - }; - - target-module@9000 { /* 0x44e09000, ap 16 04.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "uart1"; - reg = <0x9050 0x4>, - <0x9054 0x4>, - <0x9058 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ - clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_UART1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x9000 0x1000>; - - uart0: serial@0 { - compatible = "ti,am4372-uart","ti,omap2-uart"; - reg = <0x0 0x2000>; - interrupts = ; - }; - }; - - target-module@b000 { /* 0x44e0b000, ap 18 48.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "i2c1"; - reg = <0xb000 0x8>, - <0xb010 0x8>, - <0xb090 0x8>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ - clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_I2C1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xb000 0x1000>; - - i2c0: i2c@0 { - compatible = "ti,am4372-i2c","ti,omap4-i2c"; - reg = <0x0 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - target-module@d000 { /* 0x44e0d000, ap 20 38.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - ti,hwmods = "adc_tsc"; - reg = <0xd000 0x4>, - <0xd010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): wkup_pwrdm, l3s_tsc_clkdm */ - clocks = <&l3s_tsc_clkctrl AM4_L3S_TSC_ADC_TSC_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xd000 0x1000>; - - tscadc: tscadc@0 { - compatible = "ti,am3359-tscadc"; - reg = <0x0 0x1000>; - interrupts = ; - clocks = <&adc_tsc_fck>; - clock-names = "fck"; - status = "disabled"; - dmas = <&edma 53 0>, <&edma 57 0>; - dma-names = "fifo0", "fifo1"; - - tsc { - compatible = "ti,am3359-tsc"; - }; - - adc { - #io-channel-cells = <1>; - compatible = "ti,am3359-adc"; - }; - - }; - }; - - target-module@10000 { /* 0x44e10000, ap 22 0c.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x10000 0x4>; - reg-names = "rev"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x10000 0x10000>; - - scm: scm@0 { - compatible = "ti,am4-scm", "simple-bus"; - reg = <0x0 0x4000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x4000>; - - am43xx_pinmux: pinmux@800 { - compatible = "ti,am437-padconf", - "pinctrl-single"; - reg = <0x800 0x31c>; - #address-cells = <1>; - #size-cells = <0>; - #pinctrl-cells = <1>; - #interrupt-cells = <1>; - interrupt-controller; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0xffffffff>; - }; - - scm_conf: scm_conf@0 { - compatible = "syscon", "simple-bus"; - reg = <0x0 0x800>; - #address-cells = <1>; - #size-cells = <1>; - - phy_gmii_sel: phy-gmii-sel { - compatible = "ti,am43xx-phy-gmii-sel"; - reg = <0x650 0x4>; - #phy-cells = <2>; - }; - - scm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - wkup_m3_ipc: wkup_m3_ipc@1324 { - compatible = "ti,am4372-wkup-m3-ipc"; - reg = <0x1324 0x44>; - interrupts = ; - ti,rproc = <&wkup_m3>; - mboxes = <&mailbox &mbox_wkupm3>; - }; - - edma_xbar: dma-router@f90 { - compatible = "ti,am335x-edma-crossbar"; - reg = <0xf90 0x40>; - #dma-cells = <3>; - dma-requests = <64>; - dma-masters = <&edma>; - }; - - scm_clockdomains: clockdomains { - }; - }; - }; - - target-module@31000 { /* 0x44e31000, ap 24 40.0 */ - compatible = "ti,sysc-omap2-timer", "ti,sysc"; - ti,hwmods = "timer1"; - reg = <0x31000 0x4>, - <0x31010 0x4>, - <0x31014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ - clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_TIMER1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x31000 0x1000>; - - timer1: timer@0 { - compatible = "ti,am4372-timer-1ms","ti,am335x-timer-1ms"; - reg = <0x0 0x400>; - interrupts = ; - ti,timer-alwon; - clocks = <&timer1_fck>; - clock-names = "fck"; - }; - }; - - target-module@33000 { /* 0x44e33000, ap 26 18.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x33000 0x1000>; - }; - - target-module@35000 { /* 0x44e35000, ap 28 50.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "wd_timer2"; - reg = <0x35000 0x4>, - <0x35010 0x4>, - <0x35014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_EMUFREE | - SYSC_OMAP2_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ - clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_WD_TIMER2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x35000 0x1000>; - - wdt: wdt@0 { - compatible = "ti,am4372-wdt","ti,omap3-wdt"; - reg = <0x0 0x1000>; - interrupts = ; - }; - }; - - target-module@37000 { /* 0x44e37000, ap 30 08.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x37000 0x1000>; - }; - - target-module@39000 { /* 0x44e39000, ap 32 02.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x39000 0x1000>; - }; - - target-module@3e000 { /* 0x44e3e000, ap 34 60.0 */ - compatible = "ti,sysc-omap4-simple", "ti,sysc"; - ti,hwmods = "rtc"; - reg = <0x3e074 0x4>, - <0x3e078 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): rtc_pwrdm, l4_rtc_clkdm */ - clocks = <&l4_rtc_clkctrl AM4_L4_RTC_RTC_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x3e000 0x1000>; - - rtc: rtc@0 { - compatible = "ti,am4372-rtc", "ti,am3352-rtc", - "ti,da830-rtc"; - reg = <0x0 0x1000>; - interrupts = ; - clocks = <&clk_32768_ck>; - clock-names = "int-clk"; - system-power-controller; - status = "disabled"; - }; - }; - - target-module@40000 { /* 0x44e40000, ap 36 68.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x40000 0x40000>; - }; - - target-module@86000 { /* 0x44e86000, ap 40 70.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "counter_32k"; - reg = <0x86000 0x4>, - <0x86004 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-sidle = , - ; - /* Domains (P, C): wkup_pwrdm, l4_wkup_aon_clkdm */ - clocks = <&l4_wkup_aon_clkctrl AM4_L4_WKUP_AON_COUNTER_32K_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x86000 0x1000>; - - counter32k: counter@0 { - compatible = "ti,am4372-counter32k","ti,omap-counter32k"; - reg = <0x0 0x40>; - }; - }; - - target-module@88000 { /* 0x44e88000, ap 38 12.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00088000 0x00008000>, - <0x00008000 0x00090000 0x00001000>, - <0x00009000 0x00091000 0x00001000>; - }; - }; -}; - -&l4_fast { /* 0x4a000000 */ - compatible = "ti,am4-l4-fast", "simple-bus"; - reg = <0x4a000000 0x800>, - <0x4a000800 0x800>, - <0x4a001000 0x400>; - reg-names = "ap", "la", "ia0"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x4a000000 0x1000000>; /* segment 0 */ - - segment@0 { /* 0x4a000000 */ - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ - <0x00000800 0x00000800 0x000800>, /* ap 1 */ - <0x00001000 0x00001000 0x000400>, /* ap 2 */ - <0x00100000 0x00100000 0x008000>, /* ap 3 */ - <0x00108000 0x00108000 0x001000>, /* ap 4 */ - <0x00400000 0x00400000 0x002000>, /* ap 5 */ - <0x00402000 0x00402000 0x001000>, /* ap 6 */ - <0x00200000 0x00200000 0x080000>, /* ap 7 */ - <0x00280000 0x00280000 0x001000>; /* ap 8 */ - - target-module@100000 { /* 0x4a100000, ap 3 04.0 */ - compatible = "ti,sysc-omap4-simple", "ti,sysc"; - reg = <0x101200 0x4>, - <0x101208 0x4>, - <0x101204 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <0>; - ti,sysc-midle = , - ; - ti,sysc-sidle = , - ; - ti,syss-mask = <1>; - clocks = <&cpsw_125mhz_clkctrl AM4_CPSW_125MHZ_CPGMAC0_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x100000 0x8000>; - - mac: ethernet@0 { - compatible = "ti,am4372-cpsw","ti,cpsw"; - reg = <0x0 0x800 - 0x1200 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>, - <&dpll_clksel_mac_clk>; - clock-names = "fck", "cpts", "50mclk"; - assigned-clocks = <&dpll_clksel_mac_clk>; - assigned-clock-rates = <50000000>; - status = "disabled"; - cpdma_channels = <8>; - ale_entries = <1024>; - bd_ram_size = <0x2000>; - mac_control = <0x20>; - slaves = <2>; - active_slave = <0>; - cpts_clock_mult = <0x80000000>; - cpts_clock_shift = <29>; - ranges = <0 0 0x8000>; - syscon = <&scm_conf>; - - davinci_mdio: mdio@1000 { - compatible = "ti,am4372-mdio","ti,cpsw-mdio","ti,davinci_mdio"; - reg = <0x1000 0x100>; - clocks = <&cpsw_125mhz_clkctrl AM4_CPSW_125MHZ_CPGMAC0_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <0>; - bus_freq = <1000000>; - status = "disabled"; - }; - - cpsw_emac0: slave@200 { - /* Filled in by U-Boot */ - mac-address = [ 00 00 00 00 00 00 ]; - phys = <&phy_gmii_sel 1 0>; - }; - - cpsw_emac1: slave@300 { - /* Filled in by U-Boot */ - mac-address = [ 00 00 00 00 00 00 ]; - phys = <&phy_gmii_sel 2 0>; - }; - }; - }; - - target-module@200000 { /* 0x4a200000, ap 7 02.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x200000 0x80000>; - }; - - target-module@400000 { /* 0x4a400000, ap 5 08.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x400000 0x2000>; - }; - }; -}; - -&l4_per { /* 0x48000000 */ - compatible = "ti,am4-l4-per", "simple-bus"; - reg = <0x48000000 0x800>, - <0x48000800 0x800>, - <0x48001000 0x400>, - <0x48001400 0x400>, - <0x48001800 0x400>, - <0x48001c00 0x400>; - reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x48000000 0x100000>, /* segment 0 */ - <0x00100000 0x48100000 0x100000>, /* segment 1 */ - <0x00200000 0x48200000 0x100000>, /* segment 2 */ - <0x00300000 0x48300000 0x100000>, /* segment 3 */ - <0x46000000 0x46000000 0x400000>, /* l3 data port */ - <0x46400000 0x46400000 0x400000>; /* l3 data port */ - - segment@0 { /* 0x48000000 */ - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ - <0x00000800 0x00000800 0x000800>, /* ap 1 */ - <0x00001000 0x00001000 0x000400>, /* ap 2 */ - <0x00001400 0x00001400 0x000400>, /* ap 3 */ - <0x00001800 0x00001800 0x000400>, /* ap 4 */ - <0x00001c00 0x00001c00 0x000400>, /* ap 5 */ - <0x00008000 0x00008000 0x001000>, /* ap 6 */ - <0x00009000 0x00009000 0x001000>, /* ap 7 */ - <0x00022000 0x00022000 0x001000>, /* ap 8 */ - <0x00023000 0x00023000 0x001000>, /* ap 9 */ - <0x00024000 0x00024000 0x001000>, /* ap 10 */ - <0x00025000 0x00025000 0x001000>, /* ap 11 */ - <0x0002a000 0x0002a000 0x001000>, /* ap 12 */ - <0x0002b000 0x0002b000 0x001000>, /* ap 13 */ - <0x00038000 0x00038000 0x002000>, /* ap 14 */ - <0x0003a000 0x0003a000 0x001000>, /* ap 15 */ - <0x0003c000 0x0003c000 0x002000>, /* ap 16 */ - <0x0003e000 0x0003e000 0x001000>, /* ap 17 */ - <0x00040000 0x00040000 0x001000>, /* ap 18 */ - <0x00041000 0x00041000 0x001000>, /* ap 19 */ - <0x00042000 0x00042000 0x001000>, /* ap 20 */ - <0x00043000 0x00043000 0x001000>, /* ap 21 */ - <0x00044000 0x00044000 0x001000>, /* ap 22 */ - <0x00045000 0x00045000 0x001000>, /* ap 23 */ - <0x00046000 0x00046000 0x001000>, /* ap 24 */ - <0x00047000 0x00047000 0x001000>, /* ap 25 */ - <0x00048000 0x00048000 0x001000>, /* ap 26 */ - <0x00049000 0x00049000 0x001000>, /* ap 27 */ - <0x0004c000 0x0004c000 0x001000>, /* ap 28 */ - <0x0004d000 0x0004d000 0x001000>, /* ap 29 */ - <0x00060000 0x00060000 0x001000>, /* ap 30 */ - <0x00061000 0x00061000 0x001000>, /* ap 31 */ - <0x00080000 0x00080000 0x010000>, /* ap 32 */ - <0x00090000 0x00090000 0x001000>, /* ap 33 */ - <0x00030000 0x00030000 0x001000>, /* ap 65 */ - <0x00031000 0x00031000 0x001000>, /* ap 66 */ - <0x0004a000 0x0004a000 0x001000>, /* ap 71 */ - <0x0004b000 0x0004b000 0x001000>, /* ap 72 */ - <0x000c8000 0x000c8000 0x001000>, /* ap 73 */ - <0x000c9000 0x000c9000 0x001000>, /* ap 74 */ - <0x000ca000 0x000ca000 0x001000>, /* ap 77 */ - <0x000cb000 0x000cb000 0x001000>, /* ap 78 */ - <0x00034000 0x00034000 0x001000>, /* ap 80 */ - <0x00035000 0x00035000 0x001000>, /* ap 81 */ - <0x00036000 0x00036000 0x001000>, /* ap 84 */ - <0x00037000 0x00037000 0x001000>, /* ap 85 */ - <0x46000000 0x46000000 0x400000>, /* l3 data port */ - <0x46400000 0x46400000 0x400000>; /* l3 data port */ - - target-module@8000 { /* 0x48008000, ap 6 10.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x8000 0x1000>; - }; - - target-module@22000 { /* 0x48022000, ap 8 0a.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "uart2"; - reg = <0x22050 0x4>, - <0x22054 0x4>, - <0x22058 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM4_L4LS_UART2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x22000 0x1000>; - - uart1: serial@0 { - compatible = "ti,am4372-uart","ti,omap2-uart"; - reg = <0x0 0x2000>; - interrupts = ; - status = "disabled"; - }; - }; - - target-module@24000 { /* 0x48024000, ap 10 1c.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "uart3"; - reg = <0x24050 0x4>, - <0x24054 0x4>, - <0x24058 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM4_L4LS_UART3_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x24000 0x1000>; - - uart2: serial@0 { - compatible = "ti,am4372-uart","ti,omap2-uart"; - reg = <0x0 0x2000>; - interrupts = ; - status = "disabled"; - }; - }; - - target-module@2a000 { /* 0x4802a000, ap 12 22.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "i2c2"; - reg = <0x2a000 0x8>, - <0x2a010 0x8>, - <0x2a090 0x8>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM4_L4LS_I2C2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2a000 0x1000>; - - i2c1: i2c@0 { - compatible = "ti,am4372-i2c","ti,omap4-i2c"; - reg = <0x0 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - target-module@30000 { /* 0x48030000, ap 65 08.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "spi0"; - reg = <0x30000 0x4>, - <0x30110 0x4>, - <0x30114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM4_L4LS_SPI0_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x30000 0x1000>; - - spi0: spi@0 { - compatible = "ti,am4372-mcspi","ti,omap4-mcspi"; - reg = <0x0 0x400>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - target-module@34000 { /* 0x48034000, ap 80 56.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x34000 0x1000>; - }; - - target-module@36000 { /* 0x48036000, ap 84 3e.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x36000 0x1000>; - }; - - target-module@38000 { /* 0x48038000, ap 14 04.0 */ - compatible = "ti,sysc-omap4-simple", "ti,sysc"; - ti,hwmods = "mcasp0"; - reg = <0x38000 0x4>, - <0x38004 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-sidle = , - , - ; - /* Domains (P, C): per_pwrdm, l3s_clkdm */ - clocks = <&l3s_clkctrl AM4_L3S_MCASP0_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x38000 0x2000>, - <0x46000000 0x46000000 0x400000>; - - mcasp0: mcasp@0 { - compatible = "ti,am33xx-mcasp-audio"; - reg = <0x0 0x2000>, - <0x46000000 0x400000>; - reg-names = "mpu", "dat"; - interrupts = , - ; - interrupt-names = "tx", "rx"; - status = "disabled"; - dmas = <&edma 8 2>, - <&edma 9 2>; - dma-names = "tx", "rx"; - }; - }; - - target-module@3c000 { /* 0x4803c000, ap 16 2a.0 */ - compatible = "ti,sysc-omap4-simple", "ti,sysc"; - ti,hwmods = "mcasp1"; - reg = <0x3c000 0x4>, - <0x3c004 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-sidle = , - , - ; - /* Domains (P, C): per_pwrdm, l3s_clkdm */ - clocks = <&l3s_clkctrl AM4_L3S_MCASP1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x3c000 0x2000>, - <0x46400000 0x46400000 0x400000>; - - mcasp1: mcasp@0 { - compatible = "ti,am33xx-mcasp-audio"; - reg = <0x0 0x2000>, - <0x46400000 0x400000>; - reg-names = "mpu", "dat"; - interrupts = , - ; - interrupt-names = "tx", "rx"; - status = "disabled"; - dmas = <&edma 10 2>, - <&edma 11 2>; - dma-names = "tx", "rx"; - }; - }; - - target-module@40000 { /* 0x48040000, ap 18 1e.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - ti,hwmods = "timer2"; - reg = <0x40000 0x4>, - <0x40010 0x4>, - <0x40014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM4_L4LS_TIMER2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x40000 0x1000>; - - timer2: timer@0 { - compatible = "ti,am4372-timer","ti,am335x-timer"; - reg = <0x0 0x400>; - interrupts = ; - clocks = <&timer2_fck>; - clock-names = "fck"; - }; - }; - - target-module@42000 { /* 0x48042000, ap 20 24.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - ti,hwmods = "timer3"; - reg = <0x42000 0x4>, - <0x42010 0x4>, - <0x42014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM4_L4LS_TIMER3_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x42000 0x1000>; - - timer3: timer@0 { - compatible = "ti,am4372-timer","ti,am335x-timer"; - reg = <0x0 0x400>; - interrupts = ; - status = "disabled"; - }; - }; - - target-module@44000 { /* 0x48044000, ap 22 26.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - ti,hwmods = "timer4"; - reg = <0x44000 0x4>, - <0x44010 0x4>, - <0x44014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM4_L4LS_TIMER4_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x44000 0x1000>; - - timer4: timer@0 { - compatible = "ti,am4372-timer","ti,am335x-timer"; - reg = <0x0 0x400>; - interrupts = ; - ti,timer-pwm; - status = "disabled"; - }; - }; - - target-module@46000 { /* 0x48046000, ap 24 28.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - ti,hwmods = "timer5"; - reg = <0x46000 0x4>, - <0x46010 0x4>, - <0x46014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM4_L4LS_TIMER5_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x46000 0x1000>; - - timer5: timer@0 { - compatible = "ti,am4372-timer","ti,am335x-timer"; - reg = <0x0 0x400>; - interrupts = ; - ti,timer-pwm; - status = "disabled"; - }; - }; - - target-module@48000 { /* 0x48048000, ap 26 1a.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - ti,hwmods = "timer6"; - reg = <0x48000 0x4>, - <0x48010 0x4>, - <0x48014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM4_L4LS_TIMER6_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x48000 0x1000>; - - timer6: timer@0 { - compatible = "ti,am4372-timer","ti,am335x-timer"; - reg = <0x0 0x400>; - interrupts = ; - ti,timer-pwm; - status = "disabled"; - }; - }; - - target-module@4a000 { /* 0x4804a000, ap 71 48.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - ti,hwmods = "timer7"; - reg = <0x4a000 0x4>, - <0x4a010 0x4>, - <0x4a014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM4_L4LS_TIMER7_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x4a000 0x1000>; - - timer7: timer@0 { - compatible = "ti,am4372-timer","ti,am335x-timer"; - reg = <0x0 0x400>; - interrupts = ; - ti,timer-pwm; - status = "disabled"; - }; - }; - - target-module@4c000 { /* 0x4804c000, ap 28 36.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "gpio2"; - reg = <0x4c000 0x4>, - <0x4c010 0x4>, - <0x4c114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM4_L4LS_GPIO2_CLKCTRL 0>, - <&l4ls_clkctrl AM4_L4LS_GPIO2_CLKCTRL 8>; - clock-names = "fck", "dbclk"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x4c000 0x1000>; - - gpio1: gpio@0 { - compatible = "ti,am4372-gpio","ti,omap4-gpio"; - reg = <0x0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - status = "disabled"; - }; - }; - - target-module@60000 { /* 0x48060000, ap 30 14.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "mmc1"; - reg = <0x602fc 0x4>, - <0x60110 0x4>, - <0x60114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM4_L4LS_MMC1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x60000 0x1000>; - - mmc1: mmc@0 { - compatible = "ti,omap4-hsmmc"; - reg = <0x0 0x1000>; - ti,dual-volt; - ti,needs-special-reset; - dmas = <&edma 24 0>, - <&edma 25 0>; - dma-names = "tx", "rx"; - interrupts = ; - status = "disabled"; - }; - }; - - target-module@80000 { /* 0x48080000, ap 32 18.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "elm"; - reg = <0x80000 0x4>, - <0x80010 0x4>, - <0x80014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM4_L4LS_ELM_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x80000 0x10000>; - - elm: elm@0 { - compatible = "ti,am3352-elm"; - reg = <0x0 0x2000>; - interrupts = ; - clocks = <&l4ls_gclk>; - clock-names = "fck"; - status = "disabled"; - }; - }; - - target-module@c8000 { /* 0x480c8000, ap 73 06.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - ti,hwmods = "mailbox"; - reg = <0xc8000 0x4>, - <0xc8010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - ; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM4_L4LS_MAILBOX_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xc8000 0x1000>; - - mailbox: mailbox@0 { - compatible = "ti,omap4-mailbox"; - reg = <0x0 0x200>; - interrupts = ; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <8>; - mbox_wkupm3: wkup_m3 { - ti,mbox-send-noirq; - ti,mbox-tx = <0 0 0>; - ti,mbox-rx = <0 0 3>; - }; - }; - }; - - target-module@ca000 { /* 0x480ca000, ap 77 38.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "spinlock"; - reg = <0xca000 0x4>, - <0xca010 0x4>, - <0xca014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM4_L4LS_SPINLOCK_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xca000 0x1000>; - - hwspinlock: spinlock@0 { - compatible = "ti,omap4-hwspinlock"; - reg = <0x0 0x1000>; - #hwlock-cells = <1>; - }; - }; - }; - - segment@100000 { /* 0x48100000 */ - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0008c000 0x0018c000 0x001000>, /* ap 34 */ - <0x0008d000 0x0018d000 0x001000>, /* ap 35 */ - <0x0008e000 0x0018e000 0x001000>, /* ap 36 */ - <0x0008f000 0x0018f000 0x001000>, /* ap 37 */ - <0x0009c000 0x0019c000 0x001000>, /* ap 38 */ - <0x0009d000 0x0019d000 0x001000>, /* ap 39 */ - <0x000a6000 0x001a6000 0x001000>, /* ap 40 */ - <0x000a7000 0x001a7000 0x001000>, /* ap 41 */ - <0x000a8000 0x001a8000 0x001000>, /* ap 42 */ - <0x000a9000 0x001a9000 0x001000>, /* ap 43 */ - <0x000aa000 0x001aa000 0x001000>, /* ap 44 */ - <0x000ab000 0x001ab000 0x001000>, /* ap 45 */ - <0x000ac000 0x001ac000 0x001000>, /* ap 46 */ - <0x000ad000 0x001ad000 0x001000>, /* ap 47 */ - <0x000ae000 0x001ae000 0x001000>, /* ap 48 */ - <0x000af000 0x001af000 0x001000>, /* ap 49 */ - <0x000cc000 0x001cc000 0x002000>, /* ap 50 */ - <0x000ce000 0x001ce000 0x002000>, /* ap 51 */ - <0x000d0000 0x001d0000 0x002000>, /* ap 52 */ - <0x000d2000 0x001d2000 0x002000>, /* ap 53 */ - <0x000d8000 0x001d8000 0x001000>, /* ap 54 */ - <0x000d9000 0x001d9000 0x001000>, /* ap 55 */ - <0x000a0000 0x001a0000 0x001000>, /* ap 67 */ - <0x000a1000 0x001a1000 0x001000>, /* ap 68 */ - <0x000a2000 0x001a2000 0x001000>, /* ap 69 */ - <0x000a3000 0x001a3000 0x001000>, /* ap 70 */ - <0x000a4000 0x001a4000 0x001000>, /* ap 92 */ - <0x000a5000 0x001a5000 0x001000>, /* ap 93 */ - <0x000c1000 0x001c1000 0x001000>, /* ap 94 */ - <0x000c2000 0x001c2000 0x001000>; /* ap 95 */ - - target-module@8c000 { /* 0x4818c000, ap 34 0c.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x8c000 0x1000>; - }; - - target-module@8e000 { /* 0x4818e000, ap 36 02.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x8e000 0x1000>; - }; - - target-module@9c000 { /* 0x4819c000, ap 38 52.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "i2c3"; - reg = <0x9c000 0x8>, - <0x9c010 0x8>, - <0x9c090 0x8>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM4_L4LS_I2C3_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x9c000 0x1000>; - - i2c2: i2c@0 { - compatible = "ti,am4372-i2c","ti,omap4-i2c"; - reg = <0x0 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - target-module@a0000 { /* 0x481a0000, ap 67 2c.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "spi1"; - reg = <0xa0000 0x4>, - <0xa0110 0x4>, - <0xa0114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM4_L4LS_SPI1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xa0000 0x1000>; - - spi1: spi@0 { - compatible = "ti,am4372-mcspi","ti,omap4-mcspi"; - reg = <0x0 0x400>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - target-module@a2000 { /* 0x481a2000, ap 69 2e.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "spi2"; - reg = <0xa2000 0x4>, - <0xa2110 0x4>, - <0xa2114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM4_L4LS_SPI2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xa2000 0x1000>; - - spi2: spi@0 { - compatible = "ti,am4372-mcspi","ti,omap4-mcspi"; - reg = <0x0 0x400>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - target-module@a4000 { /* 0x481a4000, ap 92 62.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "spi3"; - reg = <0xa4000 0x4>, - <0xa4110 0x4>, - <0xa4114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM4_L4LS_SPI3_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xa4000 0x1000>; - - spi3: spi@0 { - compatible = "ti,am4372-mcspi","ti,omap4-mcspi"; - reg = <0x0 0x400>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - target-module@a6000 { /* 0x481a6000, ap 40 16.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "uart4"; - reg = <0xa6050 0x4>, - <0xa6054 0x4>, - <0xa6058 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM4_L4LS_UART4_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xa6000 0x1000>; - - uart3: serial@0 { - compatible = "ti,am4372-uart","ti,omap2-uart"; - reg = <0x0 0x2000>; - interrupts = ; - status = "disabled"; - }; - }; - - target-module@a8000 { /* 0x481a8000, ap 42 20.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "uart5"; - reg = <0xa8050 0x4>, - <0xa8054 0x4>, - <0xa8058 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM4_L4LS_UART5_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xa8000 0x1000>; - - uart4: serial@0 { - compatible = "ti,am4372-uart","ti,omap2-uart"; - reg = <0x0 0x2000>; - interrupts = ; - status = "disabled"; - }; - }; - - target-module@aa000 { /* 0x481aa000, ap 44 12.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "uart6"; - reg = <0xaa050 0x4>, - <0xaa054 0x4>, - <0xaa058 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM4_L4LS_UART6_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xaa000 0x1000>; - - uart5: serial@0 { - compatible = "ti,am4372-uart","ti,omap2-uart"; - reg = <0x0 0x2000>; - interrupts = ; - status = "disabled"; - }; - }; - - target-module@ac000 { /* 0x481ac000, ap 46 30.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "gpio3"; - reg = <0xac000 0x4>, - <0xac010 0x4>, - <0xac114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM4_L4LS_GPIO3_CLKCTRL 0>, - <&l4ls_clkctrl AM4_L4LS_GPIO3_CLKCTRL 8>; - clock-names = "fck", "dbclk"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xac000 0x1000>; - - gpio2: gpio@0 { - compatible = "ti,am4372-gpio","ti,omap4-gpio"; - reg = <0x0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - status = "disabled"; - }; - }; - - target-module@ae000 { /* 0x481ae000, ap 48 32.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "gpio4"; - reg = <0xae000 0x4>, - <0xae010 0x4>, - <0xae114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM4_L4LS_GPIO4_CLKCTRL 0>, - <&l4ls_clkctrl AM4_L4LS_GPIO4_CLKCTRL 8>; - clock-names = "fck", "dbclk"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xae000 0x1000>; - - gpio3: gpio@0 { - compatible = "ti,am4372-gpio","ti,omap4-gpio"; - reg = <0x0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - status = "disabled"; - }; - }; - - target-module@c1000 { /* 0x481c1000, ap 94 68.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - ti,hwmods = "timer8"; - reg = <0xc1000 0x4>, - <0xc1010 0x4>, - <0xc1014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM4_L4LS_TIMER8_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xc1000 0x1000>; - - timer8: timer@0 { - compatible = "ti,am4372-timer","ti,am335x-timer"; - reg = <0x0 0x400>; - interrupts = ; - status = "disabled"; - }; - }; - - target-module@cc000 { /* 0x481cc000, ap 50 46.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0xcc020 0x4>; - reg-names = "rev"; - ti,hwmods = "d_can0"; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM4_L4LS_D_CAN0_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xcc000 0x2000>; - - dcan0: can@0 { - compatible = "ti,am4372-d_can", "ti,am3352-d_can"; - reg = <0x0 0x2000>; - syscon-raminit = <&scm_conf 0x644 0>; - interrupts = ; - status = "disabled"; - }; - }; - - target-module@d0000 { /* 0x481d0000, ap 52 3a.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0xd0020 0x4>; - reg-names = "rev"; - ti,hwmods = "d_can1"; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM4_L4LS_D_CAN1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xd0000 0x2000>; - - dcan1: can@0 { - compatible = "ti,am4372-d_can", "ti,am3352-d_can"; - reg = <0x0 0x2000>; - syscon-raminit = <&scm_conf 0x644 1>; - interrupts = ; - status = "disabled"; - }; - }; - - target-module@d8000 { /* 0x481d8000, ap 54 5e.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "mmc2"; - reg = <0xd82fc 0x4>, - <0xd8110 0x4>, - <0xd8114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM4_L4LS_MMC2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xd8000 0x1000>; - - mmc2: mmc@0 { - compatible = "ti,omap4-hsmmc"; - reg = <0x0 0x1000>; - ti,needs-special-reset; - dmas = <&edma 2 0>, - <&edma 3 0>; - dma-names = "tx", "rx"; - interrupts = ; - status = "disabled"; - }; - }; - }; - - segment@200000 { /* 0x48200000 */ - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - }; - - segment@300000 { /* 0x48300000 */ - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00300000 0x001000>, /* ap 56 */ - <0x00001000 0x00301000 0x001000>, /* ap 57 */ - <0x00002000 0x00302000 0x001000>, /* ap 58 */ - <0x00003000 0x00303000 0x001000>, /* ap 59 */ - <0x00004000 0x00304000 0x001000>, /* ap 60 */ - <0x00005000 0x00305000 0x001000>, /* ap 61 */ - <0x00018000 0x00318000 0x004000>, /* ap 62 */ - <0x0001c000 0x0031c000 0x001000>, /* ap 63 */ - <0x00010000 0x00310000 0x002000>, /* ap 64 */ - <0x00028000 0x00328000 0x001000>, /* ap 75 */ - <0x00029000 0x00329000 0x001000>, /* ap 76 */ - <0x00012000 0x00312000 0x001000>, /* ap 79 */ - <0x00020000 0x00320000 0x001000>, /* ap 82 */ - <0x00021000 0x00321000 0x001000>, /* ap 83 */ - <0x00026000 0x00326000 0x001000>, /* ap 86 */ - <0x00027000 0x00327000 0x001000>, /* ap 87 */ - <0x0002a000 0x0032a000 0x000400>, /* ap 88 */ - <0x0002c000 0x0032c000 0x001000>, /* ap 89 */ - <0x00013000 0x00313000 0x001000>, /* ap 90 */ - <0x00014000 0x00314000 0x001000>, /* ap 91 */ - <0x00006000 0x00306000 0x001000>, /* ap 96 */ - <0x00007000 0x00307000 0x001000>, /* ap 97 */ - <0x00008000 0x00308000 0x001000>, /* ap 98 */ - <0x00009000 0x00309000 0x001000>, /* ap 99 */ - <0x0000a000 0x0030a000 0x001000>, /* ap 100 */ - <0x0000b000 0x0030b000 0x001000>, /* ap 101 */ - <0x0003d000 0x0033d000 0x001000>, /* ap 102 */ - <0x0003e000 0x0033e000 0x001000>, /* ap 103 */ - <0x0003f000 0x0033f000 0x001000>, /* ap 104 */ - <0x00040000 0x00340000 0x001000>, /* ap 105 */ - <0x00041000 0x00341000 0x001000>, /* ap 106 */ - <0x00042000 0x00342000 0x001000>, /* ap 107 */ - <0x00045000 0x00345000 0x001000>, /* ap 108 */ - <0x00046000 0x00346000 0x001000>, /* ap 109 */ - <0x00047000 0x00347000 0x001000>, /* ap 110 */ - <0x00048000 0x00348000 0x001000>, /* ap 111 */ - <0x000f2000 0x003f2000 0x002000>, /* ap 112 */ - <0x000f4000 0x003f4000 0x001000>, /* ap 113 */ - <0x0004c000 0x0034c000 0x002000>, /* ap 114 */ - <0x0004e000 0x0034e000 0x001000>, /* ap 115 */ - <0x00022000 0x00322000 0x001000>, /* ap 116 */ - <0x00023000 0x00323000 0x001000>, /* ap 117 */ - <0x000f0000 0x003f0000 0x001000>, /* ap 118 */ - <0x0002a400 0x0032a400 0x000400>, /* ap 119 */ - <0x0002a800 0x0032a800 0x000400>, /* ap 120 */ - <0x0002ac00 0x0032ac00 0x000400>, /* ap 121 */ - <0x0002b000 0x0032b000 0x001000>, /* ap 122 */ - <0x00080000 0x00380000 0x020000>, /* ap 123 */ - <0x000a0000 0x003a0000 0x001000>, /* ap 124 */ - <0x000a8000 0x003a8000 0x008000>, /* ap 125 */ - <0x000b0000 0x003b0000 0x001000>, /* ap 126 */ - <0x000c0000 0x003c0000 0x020000>, /* ap 127 */ - <0x000e0000 0x003e0000 0x001000>, /* ap 128 */ - <0x000e8000 0x003e8000 0x008000>; /* ap 129 */ - - target-module@0 { /* 0x48300000, ap 56 40.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - ti,hwmods = "epwmss0"; - reg = <0x0 0x4>, - <0x4 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-midle = , - , - , - ; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM4_L4LS_EPWMSS0_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x1000>; - - epwmss0: epwmss@0 { - compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; - reg = <0x0 0x10>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x1000>; - status = "disabled"; - - ecap0: ecap@100 { - compatible = "ti,am4372-ecap", - "ti,am3352-ecap", - "ti,am33xx-ecap"; - #pwm-cells = <3>; - reg = <0x100 0x80>; - clocks = <&l4ls_gclk>; - clock-names = "fck"; - status = "disabled"; - }; - - ehrpwm0: pwm@200 { - compatible = "ti,am4372-ehrpwm", - "ti,am3352-ehrpwm", - "ti,am33xx-ehrpwm"; - #pwm-cells = <3>; - reg = <0x200 0x80>; - clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - }; - }; - - target-module@2000 { /* 0x48302000, ap 58 4a.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - ti,hwmods = "epwmss1"; - reg = <0x2000 0x4>, - <0x2004 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-midle = , - , - , - ; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM4_L4LS_EPWMSS1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2000 0x1000>; - - epwmss1: epwmss@0 { - compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; - reg = <0x0 0x10>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x1000>; - status = "disabled"; - - ecap1: ecap@100 { - compatible = "ti,am4372-ecap", - "ti,am3352-ecap", - "ti,am33xx-ecap"; - #pwm-cells = <3>; - reg = <0x100 0x80>; - clocks = <&l4ls_gclk>; - clock-names = "fck"; - status = "disabled"; - }; - - ehrpwm1: pwm@200 { - compatible = "ti,am4372-ehrpwm", - "ti,am3352-ehrpwm", - "ti,am33xx-ehrpwm"; - #pwm-cells = <3>; - reg = <0x200 0x80>; - clocks = <&ehrpwm1_tbclk>, <&l4ls_gclk>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - }; - }; - - target-module@4000 { /* 0x48304000, ap 60 44.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - ti,hwmods = "epwmss2"; - reg = <0x4000 0x4>, - <0x4004 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-midle = , - , - , - ; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM4_L4LS_EPWMSS2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x4000 0x1000>; - - epwmss2: epwmss@0 { - compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; - reg = <0x0 0x10>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x1000>; - status = "disabled"; - - ecap2: ecap@100 { - compatible = "ti,am4372-ecap", - "ti,am3352-ecap", - "ti,am33xx-ecap"; - #pwm-cells = <3>; - reg = <0x100 0x80>; - clocks = <&l4ls_gclk>; - clock-names = "fck"; - status = "disabled"; - }; - - ehrpwm2: pwm@200 { - compatible = "ti,am4372-ehrpwm", - "ti,am3352-ehrpwm", - "ti,am33xx-ehrpwm"; - #pwm-cells = <3>; - reg = <0x200 0x80>; - clocks = <&ehrpwm2_tbclk>, <&l4ls_gclk>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - }; - }; - - target-module@6000 { /* 0x48306000, ap 96 58.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - ti,hwmods = "epwmss3"; - reg = <0x6000 0x4>, - <0x6004 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-midle = , - , - , - ; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM4_L4LS_EPWMSS3_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x6000 0x1000>; - - epwmss3: epwmss@0 { - compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; - reg = <0x0 0x10>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x1000>; - status = "disabled"; - - ehrpwm3: pwm@200 { - compatible = "ti,am4372-ehrpwm", - "ti,am3352-ehrpwm", - "ti,am33xx-ehrpwm"; - #pwm-cells = <3>; - reg = <0x200 0x80>; - clocks = <&ehrpwm3_tbclk>, <&l4ls_gclk>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - }; - }; - - target-module@8000 { /* 0x48308000, ap 98 54.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - ti,hwmods = "epwmss4"; - reg = <0x8000 0x4>, - <0x8004 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-midle = , - , - , - ; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM4_L4LS_EPWMSS4_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x8000 0x1000>; - - epwmss4: epwmss@0 { - compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; - reg = <0x0 0x10>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x1000>; - status = "disabled"; - - ehrpwm4: pwm@48308200 { - compatible = "ti,am4372-ehrpwm", - "ti,am3352-ehrpwm", - "ti,am33xx-ehrpwm"; - #pwm-cells = <3>; - reg = <0x200 0x80>; - clocks = <&ehrpwm4_tbclk>, <&l4ls_gclk>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - }; - }; - - target-module@a000 { /* 0x4830a000, ap 100 60.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - ti,hwmods = "epwmss5"; - reg = <0xa000 0x4>, - <0xa004 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-midle = , - , - , - ; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM4_L4LS_EPWMSS5_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xa000 0x1000>; - - epwmss5: epwmss@0 { - compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; - reg = <0x0 0x10>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x1000>; - status = "disabled"; - - ehrpwm5: pwm@200 { - compatible = "ti,am4372-ehrpwm", - "ti,am3352-ehrpwm", - "ti,am33xx-ehrpwm"; - #pwm-cells = <3>; - reg = <0x200 0x80>; - clocks = <&ehrpwm5_tbclk>, <&l4ls_gclk>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - }; - }; - - target-module@10000 { /* 0x48310000, ap 64 4e.1 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "rng"; - reg = <0x11fe0 0x4>, - <0x11fe4 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = ; - ti,sysc-sidle = , - ; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM4_L4LS_RNG_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x10000 0x2000>; - - rng: rng@0 { - compatible = "ti,omap4-rng"; - reg = <0x0 0x2000>; - interrupts = ; - }; - }; - - target-module@13000 { /* 0x48313000, ap 90 50.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x13000 0x1000>; - }; - - target-module@18000 { /* 0x48318000, ap 62 4c.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x18000 0x4000>; - }; - - target-module@20000 { /* 0x48320000, ap 82 34.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "gpio5"; - reg = <0x20000 0x4>, - <0x20010 0x4>, - <0x20114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM4_L4LS_GPIO5_CLKCTRL 0>, - <&l4ls_clkctrl AM4_L4LS_GPIO5_CLKCTRL 8>; - clock-names = "fck", "dbclk"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x20000 0x1000>; - - gpio4: gpio@0 { - compatible = "ti,am4372-gpio","ti,omap4-gpio"; - reg = <0x0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - status = "disabled"; - }; - }; - - target-module@22000 { /* 0x48322000, ap 116 64.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "gpio6"; - reg = <0x22000 0x4>, - <0x22010 0x4>, - <0x22114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM4_L4LS_GPIO6_CLKCTRL 0>, - <&l4ls_clkctrl AM4_L4LS_GPIO6_CLKCTRL 8>; - clock-names = "fck", "dbclk"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x22000 0x1000>; - - gpio5: gpio@0 { - compatible = "ti,am4372-gpio","ti,omap4-gpio"; - reg = <0x0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - status = "disabled"; - }; - }; - - target-module@26000 { /* 0x48326000, ap 86 66.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - ti,hwmods = "vpfe0"; - reg = <0x26000 0x4>, - <0x26104 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-midle = , - , - ; - ti,sysc-sidle = , - , - ; - /* Domains (P, C): per_pwrdm, l3s_clkdm */ - clocks = <&l3s_clkctrl AM4_L3S_VPFE0_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x26000 0x1000>; - - vpfe0: vpfe@0 { - compatible = "ti,am437x-vpfe"; - reg = <0x0 0x2000>; - interrupts = ; - status = "disabled"; - }; - }; - - target-module@28000 { /* 0x48328000, ap 75 0e.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - ti,hwmods = "vpfe1"; - reg = <0x28000 0x4>, - <0x28104 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-midle = , - , - ; - ti,sysc-sidle = , - , - ; - /* Domains (P, C): per_pwrdm, l3s_clkdm */ - clocks = <&l3s_clkctrl AM4_L3S_VPFE1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x28000 0x1000>; - - vpfe1: vpfe@0 { - compatible = "ti,am437x-vpfe"; - reg = <0x0 0x2000>; - interrupts = ; - status = "disabled"; - }; - }; - - target-module@2a000 { /* 0x4832a000, ap 88 3c.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "dss_core"; - reg = <0x2a000 0x4>, - <0x2a010 0x4>, - <0x2a014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,syss-mask = <1>; - /* Domains (P, C): per_pwrdm, dss_clkdm */ - clocks = <&dss_clkctrl AM4_DSS_DSS_CORE_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x0002a000 0x00000400>, - <0x00000400 0x0002a400 0x00000400>, - <0x00000800 0x0002a800 0x00000400>, - <0x00000c00 0x0002ac00 0x00000400>, - <0x00001000 0x0002b000 0x00001000>; - }; - - target-module@3d000 { /* 0x4833d000, ap 102 6e.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - ti,hwmods = "timer9"; - reg = <0x3d000 0x4>, - <0x3d010 0x4>, - <0x3d014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM4_L4LS_TIMER9_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x3d000 0x1000>; - - timer9: timer@0 { - compatible = "ti,am4372-timer","ti,am335x-timer"; - reg = <0x0 0x400>; - interrupts = ; - status = "disabled"; - }; - }; - - target-module@3f000 { /* 0x4833f000, ap 104 5c.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - ti,hwmods = "timer10"; - reg = <0x3f000 0x4>, - <0x3f010 0x4>, - <0x3f014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM4_L4LS_TIMER10_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x3f000 0x1000>; - - timer10: timer@0 { - compatible = "ti,am4372-timer","ti,am335x-timer"; - reg = <0x0 0x400>; - interrupts = ; - status = "disabled"; - }; - }; - - target-module@41000 { /* 0x48341000, ap 106 76.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - ti,hwmods = "timer11"; - reg = <0x41000 0x4>, - <0x41010 0x4>, - <0x41014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM4_L4LS_TIMER11_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x41000 0x1000>; - - timer11: timer@0 { - compatible = "ti,am4372-timer","ti,am335x-timer"; - reg = <0x0 0x400>; - interrupts = ; - status = "disabled"; - }; - }; - - target-module@45000 { /* 0x48345000, ap 108 6a.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "spi4"; - reg = <0x45000 0x4>, - <0x45110 0x4>, - <0x45114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM4_L4LS_SPI4_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x45000 0x1000>; - - spi4: spi@0 { - compatible = "ti,am4372-mcspi","ti,omap4-mcspi"; - reg = <0x0 0x400>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - target-module@47000 { /* 0x48347000, ap 110 70.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "hdq1w"; - reg = <0x47000 0x4>, - <0x47014 0x4>, - <0x47018 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM4_L4LS_HDQ1W_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x47000 0x1000>; - - hdq: hdq@0 { - compatible = "ti,am4372-hdq"; - reg = <0x0 0x1000>; - interrupts = ; - clocks = <&func_12m_clk>; - clock-names = "fck"; - status = "disabled"; - }; - }; - - target-module@4c000 { /* 0x4834c000, ap 114 72.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x4c000 0x2000>; - }; - - target-module@80000 { /* 0x48380000, ap 123 42.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - ti,hwmods = "usb_otg_ss0"; - reg = <0x80000 0x4>, - <0x80010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = ; - ti,sysc-midle = , - , - , - ; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): per_pwrdm, l3s_clkdm */ - clocks = <&l3s_clkctrl AM4_L3S_USB_OTG_SS0_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x80000 0x20000>; - - dwc3_1: omap_dwc3@0 { - compatible = "ti,am437x-dwc3"; - reg = <0x0 0x10000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <1>; - utmi-mode = <1>; - ranges = <0 0 0x20000>; - - usb1: usb@10000 { - compatible = "synopsys,dwc3"; - reg = <0x10000 0x10000>; - interrupts = , - , - ; - interrupt-names = "peripheral", - "host", - "otg"; - phys = <&usb2_phy1>; - phy-names = "usb2-phy"; - maximum-speed = "high-speed"; - dr_mode = "otg"; - status = "disabled"; - snps,dis_u3_susphy_quirk; - snps,dis_u2_susphy_quirk; - }; - }; - }; - - target-module@a8000 { /* 0x483a8000, ap 125 6c.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - ti,hwmods = "ocp2scp0"; - reg = <0xa8000 0x4>; - reg-names = "rev"; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM4_L4LS_OCP2SCP0_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xa8000 0x8000>; - - ocp2scp0: ocp2scp@0 { - compatible = "ti,am437x-ocp2scp", "ti,omap-ocp2scp"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x8000>; - - usb2_phy1: phy@8000 { - compatible = "ti,am437x-usb2"; - reg = <0x0 0x8000>; - syscon-phy-power = <&scm_conf 0x620>; - clocks = <&usb_phy0_always_on_clk32k>, - <&l3s_clkctrl AM4_L3S_USB_OTG_SS0_CLKCTRL 8>; - clock-names = "wkupclk", "refclk"; - #phy-cells = <0>; - status = "disabled"; - }; - }; - }; - - target-module@c0000 { /* 0x483c0000, ap 127 7a.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - ti,hwmods = "usb_otg_ss1"; - reg = <0xc0000 0x4>, - <0xc0010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = ; - ti,sysc-midle = , - , - , - ; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): per_pwrdm, l3s_clkdm */ - clocks = <&l3s_clkctrl AM4_L3S_USB_OTG_SS1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xc0000 0x20000>; - - dwc3_2: omap_dwc3@0 { - compatible = "ti,am437x-dwc3"; - reg = <0x0 0x10000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <1>; - utmi-mode = <1>; - ranges = <0 0 0x20000>; - - usb2: usb@10000 { - compatible = "synopsys,dwc3"; - reg = <0x10000 0x10000>; - interrupts = , - , - ; - interrupt-names = "peripheral", - "host", - "otg"; - phys = <&usb2_phy2>; - phy-names = "usb2-phy"; - maximum-speed = "high-speed"; - dr_mode = "otg"; - status = "disabled"; - snps,dis_u3_susphy_quirk; - snps,dis_u2_susphy_quirk; - }; - }; - }; - - target-module@e8000 { /* 0x483e8000, ap 129 78.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - ti,hwmods = "ocp2scp1"; - reg = <0xe8000 0x4>; - reg-names = "rev"; - /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM4_L4LS_OCP2SCP1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xe8000 0x8000>; - - ocp2scp1: ocp2scp@0 { - compatible = "ti,am437x-ocp2scp", "ti,omap-ocp2scp"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x8000>; - - usb2_phy2: phy@8000 { - compatible = "ti,am437x-usb2"; - reg = <0x0 0x8000>; - syscon-phy-power = <&scm_conf 0x628>; - clocks = <&usb_phy1_always_on_clk32k>, - <&l3s_clkctrl AM4_L3S_USB_OTG_SS1_CLKCTRL 8>; - clock-names = "wkupclk", "refclk"; - #phy-cells = <0>; - status = "disabled"; - }; - }; - }; - - target-module@f2000 { /* 0x483f2000, ap 112 5a.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xf2000 0x2000>; - }; - }; -}; - diff --git a/sys/gnu/dts/arm/am437x-sbc-t43.dts b/sys/gnu/dts/arm/am437x-sbc-t43.dts deleted file mode 100644 index 94cf07ea27f..00000000000 --- a/sys/gnu/dts/arm/am437x-sbc-t43.dts +++ /dev/null @@ -1,177 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2015 CompuLab, Ltd. - http://www.compulab.co.il/ - */ - -#include "am437x-cm-t43.dts" -#include "compulab-sb-som.dtsi" - -/ { - model = "CompuLab CM-T43 on SB-SOM-T43"; - compatible = "compulab,am437x-sbc-t43", "compulab,am437x-cm-t43", "ti,am4372", "ti,am43"; - - aliases { - display0 = &lcd0; - }; -}; - -&am43xx_pinmux { - mmc1_pins: pinmux_mmc1_pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk.mmc0_clk */ - AM4372_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */ - AM4372_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */ - AM4372_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */ - AM4372_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */ - AM4372_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */ - AM4372_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ - AM4372_IOPAD(0x964, PIN_INPUT | MUX_MODE7) /* ecap0_in_pwm0_out.gpio0_7 */ - >; - }; - - dss_pinctrl_default: dss_pinctrl_default { - pinctrl-single,pins = < - AM4372_IOPAD(0x9b0, PIN_OUTPUT_PULLUP | MUX_MODE2) /* cam0 hd -> DSS DATA 23 */ - AM4372_IOPAD(0x9b4, PIN_OUTPUT_PULLUP | MUX_MODE2) - AM4372_IOPAD(0x9b8, PIN_OUTPUT_PULLUP | MUX_MODE2) - AM4372_IOPAD(0x9bc, PIN_OUTPUT_PULLUP | MUX_MODE2) - AM4372_IOPAD(0x9c0, PIN_OUTPUT_PULLUP | MUX_MODE2) - AM4372_IOPAD(0x9c4, PIN_OUTPUT_PULLUP | MUX_MODE2) - AM4372_IOPAD(0x9c8, PIN_OUTPUT_PULLUP | MUX_MODE2) - AM4372_IOPAD(0x9cc, PIN_OUTPUT_PULLUP | MUX_MODE2) /* cam1 data 9 -> DSS DATA 16 */ - - AM4372_IOPAD(0x8a0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */ - AM4372_IOPAD(0x8a4, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8a8, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8ac, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8b0, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8b4, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8b8, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8bc, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8c0, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8c4, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8c8, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8cc, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8d0, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8d4, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8d8, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8dc, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */ - AM4372_IOPAD(0x8e0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */ - AM4372_IOPAD(0x8e4, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */ - AM4372_IOPAD(0x8e8, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */ - AM4372_IOPAD(0x8ec, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */ - AM4372_IOPAD(0xa20, PIN_OUTPUT_PULLUP | MUX_MODE7) - >; - }; - - uart0_pins_default: uart0_pins_default { - pinctrl-single,pins = < - AM4372_IOPAD(0x968, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE0) - AM4372_IOPAD(0x96C, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE0) - AM4372_IOPAD(0x970, PIN_INPUT_PULLUP | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_rxd.uart0_rxd */ - AM4372_IOPAD(0x974, PIN_INPUT | PULL_DISABLE | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_txd.uart0_txd */ - >; - }; - - i2c1_pins: i2c1_pins { - pinctrl-single,pins = < - AM4372_IOPAD(0xa6c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE1) /* spi2_cs0.i2c1_sda */ - AM4372_IOPAD(0xa60, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE1) /* spi2_sclk.i2c1_scl */ - >; - }; - - i2c2_pins: i2c2_pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x978, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE3) /* uart1_ctsn.i2c2_sda */ - AM4372_IOPAD(0x97c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE3) /* uart1_rtsn.i2c2_scl */ - >; - }; - - usb2_phy1_default: usb2_phy1_default { - pinctrl-single,pins = < - AM4372_IOPAD(0xac0, DS0_PULL_UP_DOWN_EN | PIN_INPUT_PULLDOWN | MUX_MODE0) - >; - }; - - usb2_phy2_default: usb2_phy2_default { - pinctrl-single,pins = < - AM4372_IOPAD(0xac4, DS0_PULL_UP_DOWN_EN | PIN_INPUT_PULLDOWN | MUX_MODE0) - >; - }; -}; - -&i2c1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - - pca9555: pca9555@20 { - compatible = "nxp,pca9555"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - }; - - eeprom_base: at24@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; -}; - -&i2c2 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; -}; - -&mmc1 { - status = "okay"; - bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - vmmc-supply = <&vsb_3v3>; - cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; - wp-gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>; -}; - -&dss { - status = "ok"; - - pinctrl-names = "default"; - pinctrl-0 = <&dss_pinctrl_default>; - - port { - dpi_lcd_out: endpoint { - remote-endpoint = <&lcd_in>; - data-lines = <24>; - }; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_default>; -}; - -&dwc3_1 { - pinctrl-names = "default"; - pinctrl-0 = <&usb2_phy1_default>; -}; - -&dwc3_2 { - pinctrl-names = "default"; - pinctrl-0 = <&usb2_phy2_default>; -}; - -&lcd0 { - enable-gpios = <&pca9555 14 GPIO_ACTIVE_HIGH - &gpio4 28 GPIO_ACTIVE_HIGH>; - - port { - lcd_in: endpoint { - remote-endpoint = <&dpi_lcd_out>; - data-lines = <24>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/am437x-sk-evm.dts b/sys/gnu/dts/arm/am437x-sk-evm.dts deleted file mode 100644 index 74eaa6a3b25..00000000000 --- a/sys/gnu/dts/arm/am437x-sk-evm.dts +++ /dev/null @@ -1,887 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ - */ - -/* AM437x SK EVM */ - -/dts-v1/; - -#include "am4372.dtsi" -#include -#include -#include -#include -#include - -/ { - model = "TI AM437x SK EVM"; - compatible = "ti,am437x-sk-evm","ti,am4372","ti,am43"; - - aliases { - display0 = &lcd0; - }; - - chosen { - stdout-path = &uart0; - }; - - /* fixed 32k external oscillator clock */ - clk_32k_rtc: clk_32k_rtc { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - lcd_bl: backlight { - compatible = "pwm-backlight"; - pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>; - brightness-levels = <0 51 53 56 62 75 101 152 255>; - default-brightness-level = <8>; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "AM437x-SK-EVM"; - simple-audio-card,widgets = - "Headphone", "Headphone Jack", - "Line", "Line In"; - simple-audio-card,routing = - "Headphone Jack", "HPLOUT", - "Headphone Jack", "HPROUT", - "LINE1L", "Line In", - "LINE1R", "Line In"; - simple-audio-card,format = "dsp_b"; - simple-audio-card,bitclock-master = <&sound_master>; - simple-audio-card,frame-master = <&sound_master>; - simple-audio-card,bitclock-inversion; - - simple-audio-card,cpu { - sound-dai = <&mcasp1>; - }; - - sound_master: simple-audio-card,codec { - sound-dai = <&tlv320aic3106>; - system-clock-frequency = <24000000>; - }; - }; - - matrix_keypad: matrix_keypad0 { - compatible = "gpio-matrix-keypad"; - - pinctrl-names = "default"; - pinctrl-0 = <&matrix_keypad_pins>; - - debounce-delay-ms = <5>; - col-scan-delay-us = <5>; - - row-gpios = <&gpio5 5 GPIO_ACTIVE_HIGH /* Bank5, pin5 */ - &gpio5 6 GPIO_ACTIVE_HIGH>; /* Bank5, pin6 */ - - col-gpios = <&gpio5 13 GPIO_ACTIVE_HIGH /* Bank5, pin13 */ - &gpio5 4 GPIO_ACTIVE_HIGH>; /* Bank5, pin4 */ - - linux,keymap = < - MATRIX_KEY(0, 0, KEY_DOWN) - MATRIX_KEY(0, 1, KEY_RIGHT) - MATRIX_KEY(1, 0, KEY_LEFT) - MATRIX_KEY(1, 1, KEY_UP) - >; - }; - - leds { - compatible = "gpio-leds"; - - pinctrl-names = "default"; - pinctrl-0 = <&leds_pins>; - - led0 { - label = "am437x-sk:red:heartbeat"; - gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 0 */ - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - - led1 { - label = "am437x-sk:green:mmc1"; - gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 1 */ - linux,default-trigger = "mmc0"; - default-state = "off"; - }; - - led2 { - label = "am437x-sk:blue:cpu0"; - gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 2 */ - linux,default-trigger = "cpu0"; - default-state = "off"; - }; - - led3 { - label = "am437x-sk:blue:usr3"; - gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 3 */ - default-state = "off"; - }; - }; - - lcd0: display { - compatible = "newhaven,nhd-4.3-480272ef-atxl", "panel-dpi"; - label = "lcd"; - - pinctrl-names = "default"; - pinctrl-0 = <&lcd_pins>; - - backlight = <&lcd_bl>; - - enable-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; - - panel-timing { - clock-frequency = <9000000>; - hactive = <480>; - vactive = <272>; - hfront-porch = <2>; - hback-porch = <2>; - hsync-len = <41>; - vfront-porch = <2>; - vback-porch = <2>; - vsync-len = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - - port { - lcd_in: endpoint { - remote-endpoint = <&dpi_out>; - }; - }; - }; - - vmmcwl_fixed: fixedregulator-mmcwl { - /* - * WL_EN is not SDIO standard compliant. It is an out of band - * signal and hard to be dealt with in a standard way by the - * SDIO core driver. - * So modelling the WL_EN line as a regulator was a natural - * choice as the MMC core already deals with MMC supplies. - */ - compatible = "regulator-fixed"; - regulator-name = "vmmcwl_fixed"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio4 8 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&am43xx_pinmux { - matrix_keypad_pins: matrix_keypad_pins { - pinctrl-single,pins = < - AM4372_IOPAD(0xa4c, PIN_OUTPUT | MUX_MODE7) /* gpio5_13.gpio5_13 */ - AM4372_IOPAD(0xa50, PIN_OUTPUT | MUX_MODE7) /* spi4_sclk.gpio5_4 */ - AM4372_IOPAD(0xa54, PIN_INPUT | MUX_MODE7) /* spi4_d0.gpio5_5 */ - AM4372_IOPAD(0xa58, PIN_INPUT | MUX_MODE7) /* spi4_d1.gpio5_5 */ - >; - }; - - leds_pins: leds_pins { - pinctrl-single,pins = < - AM4372_IOPAD(0xa28, PIN_OUTPUT | MUX_MODE7) /* uart3_rxd.gpio5_2 */ - AM4372_IOPAD(0xa2c, PIN_OUTPUT | MUX_MODE7) /* uart3_txd.gpio5_3 */ - AM4372_IOPAD(0xa30, PIN_OUTPUT | MUX_MODE7) /* uart3_ctsn.gpio5_0 */ - AM4372_IOPAD(0xa34, PIN_OUTPUT | MUX_MODE7) /* uart3_rtsn.gpio5_1 */ - >; - }; - - i2c0_pins: i2c0_pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x988, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */ - AM4372_IOPAD(0x98c, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */ - >; - }; - - i2c1_pins: i2c1_pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x95c, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE2) /* spi0_cs0.i2c1_scl */ - AM4372_IOPAD(0x958, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE2) /* spi0_d1.i2c1_sda */ - >; - }; - - mmc1_pins: pinmux_mmc1_pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x8f0, PIN_INPUT | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */ - AM4372_IOPAD(0x8f4, PIN_INPUT | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */ - AM4372_IOPAD(0x8f8, PIN_INPUT | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */ - AM4372_IOPAD(0x8fc, PIN_INPUT | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */ - AM4372_IOPAD(0x900, PIN_INPUT | MUX_MODE0) /* mmc0_clk.mmc0_clk */ - AM4372_IOPAD(0x904, PIN_INPUT | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */ - AM4372_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ - >; - }; - - ecap0_pins: backlight_pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x964, PIN_OUTPUT | MUX_MODE0) /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out */ - >; - }; - - edt_ft5306_ts_pins: edt_ft5306_ts_pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x874, PIN_INPUT | MUX_MODE7) /* gpmc_wpn.gpio0_31 */ - AM4372_IOPAD(0x878, PIN_OUTPUT | MUX_MODE7) /* gpmc_be1n.gpio1_28 */ - >; - }; - - vpfe0_pins_default: vpfe0_pins_default { - pinctrl-single,pins = < - AM4372_IOPAD(0x9b0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_hd mode 0*/ - AM4372_IOPAD(0x9b4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_vd mode 0*/ - AM4372_IOPAD(0x9b8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_field mode 0*/ - AM4372_IOPAD(0x9bc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_wen mode 0*/ - AM4372_IOPAD(0x9c0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_pclk mode 0*/ - AM4372_IOPAD(0x9c4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data8 mode 0*/ - AM4372_IOPAD(0x9c8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data9 mode 0*/ - AM4372_IOPAD(0xa08, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data0 mode 0*/ - AM4372_IOPAD(0xa0c, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data1 mode 0*/ - AM4372_IOPAD(0xa10, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data2 mode 0*/ - AM4372_IOPAD(0xa14, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data3 mode 0*/ - AM4372_IOPAD(0xa18, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data4 mode 0*/ - AM4372_IOPAD(0xa1c, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data5 mode 0*/ - AM4372_IOPAD(0xa20, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data6 mode 0*/ - AM4372_IOPAD(0xa24, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data7 mode 0*/ - >; - }; - - vpfe0_pins_sleep: vpfe0_pins_sleep { - pinctrl-single,pins = < - AM4372_IOPAD(0x9b0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - AM4372_IOPAD(0x9b4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - AM4372_IOPAD(0x9b8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - AM4372_IOPAD(0x9bc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - AM4372_IOPAD(0x9c0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - AM4372_IOPAD(0x9c4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - AM4372_IOPAD(0x9c8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - AM4372_IOPAD(0xa08, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - AM4372_IOPAD(0xa0c, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - AM4372_IOPAD(0xa10, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - AM4372_IOPAD(0xa14, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - AM4372_IOPAD(0xa18, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - AM4372_IOPAD(0xa1c, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - AM4372_IOPAD(0xa20, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - AM4372_IOPAD(0xa24, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - >; - }; - - cpsw_default: cpsw_default { - pinctrl-single,pins = < - /* Slave 1 */ - AM4372_IOPAD(0x92c, PIN_OUTPUT | MUX_MODE2) /* mii1_txclk.rmii1_tclk */ - AM4372_IOPAD(0x914, PIN_OUTPUT | MUX_MODE2) /* mii1_txen.rgmii1_tctl */ - AM4372_IOPAD(0x928, PIN_OUTPUT | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ - AM4372_IOPAD(0x924, PIN_OUTPUT | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ - AM4372_IOPAD(0x920, PIN_OUTPUT | MUX_MODE2) /* mii1_txd0.rgmii1_td2 */ - AM4372_IOPAD(0x91c, PIN_OUTPUT | MUX_MODE2) /* mii1_txd1.rgmii1_td3 */ - AM4372_IOPAD(0x930, PIN_INPUT | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */ - AM4372_IOPAD(0x918, PIN_INPUT | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ - AM4372_IOPAD(0x940, PIN_INPUT | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ - AM4372_IOPAD(0x93c, PIN_INPUT | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ - AM4372_IOPAD(0x938, PIN_INPUT | MUX_MODE2) /* mii1_rxd0.rgmii1_rd2 */ - AM4372_IOPAD(0x934, PIN_INPUT | MUX_MODE2) /* mii1_rxd1.rgmii1_rd3 */ - - /* Slave 2 */ - AM4372_IOPAD(0x858, PIN_OUTPUT | MUX_MODE2) /* gpmc_a6.rgmii2_tclk */ - AM4372_IOPAD(0x840, PIN_OUTPUT | MUX_MODE2) /* gpmc_a0.rgmii2_tctl */ - AM4372_IOPAD(0x854, PIN_OUTPUT | MUX_MODE2) /* gpmc_a5.rgmii2_td0 */ - AM4372_IOPAD(0x850, PIN_OUTPUT | MUX_MODE2) /* gpmc_a4.rgmii2_td1 */ - AM4372_IOPAD(0x84c, PIN_OUTPUT | MUX_MODE2) /* gpmc_a3.rgmii2_td2 */ - AM4372_IOPAD(0x848, PIN_OUTPUT | MUX_MODE2) /* gpmc_a2.rgmii2_td3 */ - AM4372_IOPAD(0x85c, PIN_INPUT | MUX_MODE2) /* gpmc_a7.rgmii2_rclk */ - AM4372_IOPAD(0x844, PIN_INPUT | MUX_MODE2) /* gpmc_a1.rgmii2_rtcl */ - AM4372_IOPAD(0x86c, PIN_INPUT | MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */ - AM4372_IOPAD(0x868, PIN_INPUT | MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */ - AM4372_IOPAD(0x864, PIN_INPUT | MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */ - AM4372_IOPAD(0x860, PIN_INPUT | MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */ - >; - }; - - cpsw_sleep: cpsw_sleep { - pinctrl-single,pins = < - /* Slave 1 reset value */ - AM4372_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7) - - /* Slave 2 reset value */ - AM4372_IOPAD(0x858, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x840, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x854, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x850, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x84c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x848, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; - - davinci_mdio_default: davinci_mdio_default { - pinctrl-single,pins = < - /* MDIO */ - AM4372_IOPAD(0x948, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ - AM4372_IOPAD(0x94c, PIN_OUTPUT | MUX_MODE0) /* mdio_clk.mdio_clk */ - >; - }; - - davinci_mdio_sleep: davinci_mdio_sleep { - pinctrl-single,pins = < - /* MDIO reset value */ - AM4372_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; - - dss_pins: dss_pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x820, PIN_OUTPUT | MUX_MODE1) /* gpmc ad 8 -> DSS DATA 23 */ - AM4372_IOPAD(0x824, PIN_OUTPUT | MUX_MODE1) - AM4372_IOPAD(0x828, PIN_OUTPUT | MUX_MODE1) - AM4372_IOPAD(0x82c, PIN_OUTPUT | MUX_MODE1) - AM4372_IOPAD(0x830, PIN_OUTPUT | MUX_MODE1) - AM4372_IOPAD(0x834, PIN_OUTPUT | MUX_MODE1) - AM4372_IOPAD(0x838, PIN_OUTPUT | MUX_MODE1) - AM4372_IOPAD(0x83c, PIN_OUTPUT | MUX_MODE1) /* gpmc ad 15 -> DSS DATA 16 */ - AM4372_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE0) /* DSS DATA 0 */ - AM4372_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE0) - AM4372_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE0) - AM4372_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE0) - AM4372_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE0) - AM4372_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE0) - AM4372_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE0) - AM4372_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE0) - AM4372_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE0) - AM4372_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE0) - AM4372_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE0) - AM4372_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE0) - AM4372_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE0) - AM4372_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE0) - AM4372_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE0) - AM4372_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE0) /* DSS DATA 15 */ - AM4372_IOPAD(0x8e0, PIN_OUTPUT | MUX_MODE0) /* DSS VSYNC */ - AM4372_IOPAD(0x8e4, PIN_OUTPUT | MUX_MODE0) /* DSS HSYNC */ - AM4372_IOPAD(0x8e8, PIN_OUTPUT | MUX_MODE0) /* DSS PCLK */ - AM4372_IOPAD(0x8ec, PIN_OUTPUT | MUX_MODE0) /* DSS AC BIAS EN */ - - >; - }; - - qspi_pins: qspi_pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE3) /* gpmc_csn0.qspi_csn */ - AM4372_IOPAD(0x888, PIN_OUTPUT | MUX_MODE2) /* gpmc_csn3.qspi_clk */ - AM4372_IOPAD(0x890, PIN_INPUT | MUX_MODE3) /* gpmc_advn_ale.qspi_d0 */ - AM4372_IOPAD(0x894, PIN_INPUT | MUX_MODE3) /* gpmc_oen_ren.qspi_d1 */ - AM4372_IOPAD(0x898, PIN_INPUT | MUX_MODE3) /* gpmc_wen.qspi_d2 */ - AM4372_IOPAD(0x89c, PIN_INPUT | MUX_MODE3) /* gpmc_be0n_cle.qspi_d3 */ - >; - }; - - mcasp1_pins: mcasp1_pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */ - AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */ - AM4372_IOPAD(0x908, PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */ - AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */ - >; - }; - - mcasp1_pins_sleep: mcasp1_pins_sleep { - pinctrl-single,pins = < - AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x908, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; - - lcd_pins: lcd_pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x81c, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpcm_ad7.gpio1_7 */ - >; - }; - - usb1_pins: usb1_pins { - pinctrl-single,pins = < - AM4372_IOPAD(0xac0, PIN_OUTPUT | MUX_MODE0) /* usb0_drvvbus.usb0_drvvbus */ - >; - }; - - usb2_pins: usb2_pins { - pinctrl-single,pins = < - AM4372_IOPAD(0xac4, PIN_OUTPUT | MUX_MODE0) /* usb0_drvvbus.usb0_drvvbus */ - >; - }; - - mmc3_pins_default: pinmux_mmc3_pins_default { - pinctrl-single,pins = < - AM4372_IOPAD(0x9f0, PIN_INPUT_PULLUP | MUX_MODE3) /* (AD21) cam1_data2.mmc2_clk */ - AM4372_IOPAD(0x9f4, PIN_INPUT_PULLUP | MUX_MODE3) /* (AE22) cam1_data3.mmc2_cmd */ - AM4372_IOPAD(0x9f8, PIN_INPUT_PULLUP | MUX_MODE3) /* (AD22) cam1_data4.mmc2_dat0 */ - AM4372_IOPAD(0x9fc, PIN_INPUT_PULLUP | MUX_MODE3) /* (AE23) cam1_data5.mmc2_dat1 */ - AM4372_IOPAD(0xa00, PIN_INPUT_PULLUP | MUX_MODE3) /* (AD23) cam1_data6.mmc2_dat2 */ - AM4372_IOPAD(0xa04, PIN_INPUT_PULLUP | MUX_MODE3) /* (AE24) cam1_data7.mmc2_dat3 */ - >; - }; - - mmc3_pins_sleep: pinmux_mmc3_pins_sleep { - pinctrl-single,pins = < - AM4372_IOPAD(0x9f0, PIN_INPUT_PULLDOWN | MUX_MODE7) /* (AD21) cam1_data2.mmc2_clk */ - AM4372_IOPAD(0x9f4, PIN_INPUT_PULLDOWN | MUX_MODE7) /* (AE22) cam1_data3.mmc2_cmd */ - AM4372_IOPAD(0x9f8, PIN_INPUT_PULLDOWN | MUX_MODE7) /* (AD22) cam1_data4.mmc2_dat0 */ - AM4372_IOPAD(0x9fc, PIN_INPUT_PULLDOWN | MUX_MODE7) /* (AE23) cam1_data5.mmc2_dat1 */ - AM4372_IOPAD(0xa00, PIN_INPUT_PULLDOWN | MUX_MODE7) /* (AD23) cam1_data6.mmc2_dat2 */ - AM4372_IOPAD(0xa04, PIN_INPUT_PULLDOWN | MUX_MODE7) /* (AE24) cam1_data7.mmc2_dat3 */ - >; - }; - - wlan_pins_default: pinmux_wlan_pins_default { - pinctrl-single,pins = < - AM4372_IOPAD(0x9d0, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* cam1_data8.gpio4_8 WL_EN */ - AM4372_IOPAD(0x9e4, PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7) /* cam1_wen.gpio4_13 WL_IRQ */ - >; - }; - - wlan_pins_sleep: pinmux_wlan_pins_sleep { - pinctrl-single,pins = < - AM4372_IOPAD(0x9d0, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* cam1_data8.gpio4_8 WL_EN */ - AM4372_IOPAD(0x9e4, PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7) /* cam1_wen.gpio4_13 WL_IRQ */ - >; - }; - - uart1_bt_pins_default: pinmux_uart1_bt_pins_default { - pinctrl-single,pins = < - AM4372_IOPAD(0x980, PIN_INPUT | MUX_MODE0) /* uart1_rxd.uart1_rxd */ - AM4372_IOPAD(0x984, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_txd.uart1_txd */ - AM4372_IOPAD(0x978, PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_ctsn.uart1_ctsn */ - AM4372_IOPAD(0x97c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_rtsn.uart1_rtsn */ - AM4372_IOPAD(0x9cc, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* cam1_data9.gpio4_7 BT_EN */ - >; - }; - - uart1_bt_pins_sleep: pinmux_uart1_bt_pins_sleep { - pinctrl-single,pins = < - AM4372_IOPAD(0x980, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* uart1_rxd.uart1_rxd */ - AM4372_IOPAD(0x984, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* uart1_txd.uart1_txd */ - AM4372_IOPAD(0x978, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* uart1_ctsn.uart1_ctsn */ - AM4372_IOPAD(0x97c, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* uart1_rtsn.uart1_rtsn */ - AM4372_IOPAD(0x9cc, PIN_OUTPUT_PULLUP | MUX_MODE7) /* cam1_data9.gpio4_7 BT_EN */ - >; - }; -}; - -&i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - clock-frequency = <100000>; - - tps@24 { - compatible = "ti,tps65218"; - reg = <0x24>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <2>; - - dcdc1: regulator-dcdc1 { - /* VDD_CORE limits min of OPP50 and max of OPP100 */ - regulator-name = "vdd_core"; - regulator-min-microvolt = <912000>; - regulator-max-microvolt = <1144000>; - regulator-boot-on; - regulator-always-on; - }; - - dcdc2: regulator-dcdc2 { - /* VDD_MPU limits min of OPP50 and max of OPP_NITRO */ - regulator-name = "vdd_mpu"; - regulator-min-microvolt = <912000>; - regulator-max-microvolt = <1378000>; - regulator-boot-on; - regulator-always-on; - }; - - dcdc3: regulator-dcdc3 { - regulator-name = "vdds_ddr"; - regulator-boot-on; - regulator-always-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - regulator-state-disk { - regulator-off-in-suspend; - }; - }; - - dcdc4: regulator-dcdc4 { - regulator-name = "v3_3d"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - dcdc5: regulator-dcdc5 { - compatible = "ti,tps65218-dcdc5"; - regulator-name = "v1_0bat"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-boot-on; - regulator-always-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - dcdc6: regulator-dcdc6 { - compatible = "ti,tps65218-dcdc6"; - regulator-name = "v1_8bat"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - ldo1: regulator-ldo1 { - regulator-name = "v1_8d"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - power-button { - compatible = "ti,tps65218-pwrbutton"; - status = "okay"; - interrupts = <3 IRQ_TYPE_EDGE_BOTH>; - }; - }; - - at24@50 { - compatible = "atmel,24c256"; - pagesize = <64>; - reg = <0x50>; - }; -}; - -&i2c1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - clock-frequency = <400000>; - - edt-ft5306@38 { - status = "okay"; - compatible = "edt,edt-ft5306", "edt,edt-ft5x06"; - pinctrl-names = "default"; - pinctrl-0 = <&edt_ft5306_ts_pins>; - - reg = <0x38>; - interrupt-parent = <&gpio0>; - interrupts = <31 IRQ_TYPE_EDGE_FALLING>; - - reset-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>; - - touchscreen-size-x = <480>; - touchscreen-size-y = <272>; - - wakeup-source; - }; - - tlv320aic3106: tlv320aic3106@1b { - #sound-dai-cells = <0>; - compatible = "ti,tlv320aic3106"; - reg = <0x1b>; - status = "okay"; - - /* Regulators */ - AVDD-supply = <&dcdc4>; - IOVDD-supply = <&dcdc4>; - DRVDD-supply = <&dcdc4>; - DVDD-supply = <&ldo1>; - }; - - lis331dlh@18 { - compatible = "st,lis331dlh"; - reg = <0x18>; - status = "okay"; - - Vdd-supply = <&dcdc4>; - Vdd_IO-supply = <&dcdc4>; - interrupts-extended = <&gpio1 6 0>, <&gpio2 1 0>; - }; -}; - -&epwmss0 { - status = "okay"; -}; - -&ecap0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&ecap0_pins>; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&gpio4 { - status = "okay"; -}; - -&gpio5 { - status = "okay"; -}; - -&mmc1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - - vmmc-supply = <&dcdc4>; - bus-width = <4>; - cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; -}; - -&uart1 { - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&uart1_bt_pins_default>; - pinctrl-1 = <&uart1_bt_pins_sleep>; -}; - -&mmc3 { - status = "okay"; - /* - * these are on the crossbar and are outlined in the - * xbar-event-map element - */ - dmas = <&edma_xbar 30 0 1>, - <&edma_xbar 31 0 2>; - dma-names = "tx", "rx"; - vmmc-supply = <&vmmcwl_fixed>; - bus-width = <4>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&mmc3_pins_default>; - pinctrl-1 = <&mmc3_pins_sleep>; - cap-power-off-card; - keep-power-in-suspend; - ti,non-removable; - - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@2 { - compatible = "ti,wl1835"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&wlan_pins_default>; - pinctrl-1 = <&wlan_pins_sleep>; - reg = <2>; - interrupt-parent = <&gpio4>; - interrupts = <13 IRQ_TYPE_LEVEL_HIGH>; - }; -}; - -&usb2_phy1 { - status = "okay"; -}; - -&usb1 { - dr_mode = "otg"; - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&usb1_pins>; -}; - -&usb2_phy2 { - status = "okay"; -}; - -&usb2 { - dr_mode = "host"; - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&usb2_pins>; -}; - -&qspi { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&qspi_pins>; - - spi-max-frequency = <48000000>; - m25p80@0 { - compatible = "mx66l51235l"; - spi-max-frequency = <48000000>; - reg = <0>; - spi-cpol; - spi-cpha; - spi-tx-bus-width = <1>; - spi-rx-bus-width = <4>; - #address-cells = <1>; - #size-cells = <1>; - - /* MTD partition table. - * The ROM checks the first 512KiB - * for a valid file to boot(XIP). - */ - partition@0 { - label = "QSPI.U_BOOT"; - reg = <0x00000000 0x000080000>; - }; - partition@1 { - label = "QSPI.U_BOOT.backup"; - reg = <0x00080000 0x00080000>; - }; - partition@2 { - label = "QSPI.U-BOOT-SPL_OS"; - reg = <0x00100000 0x00010000>; - }; - partition@3 { - label = "QSPI.U_BOOT_ENV"; - reg = <0x00110000 0x00010000>; - }; - partition@4 { - label = "QSPI.U-BOOT-ENV.backup"; - reg = <0x00120000 0x00010000>; - }; - partition@5 { - label = "QSPI.KERNEL"; - reg = <0x00130000 0x0800000>; - }; - partition@6 { - label = "QSPI.FILESYSTEM"; - reg = <0x00930000 0x36D0000>; - }; - }; -}; - -&mac { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&cpsw_default>; - pinctrl-1 = <&cpsw_sleep>; - dual_emac = <1>; - status = "okay"; -}; - -&davinci_mdio { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&davinci_mdio_default>; - pinctrl-1 = <&davinci_mdio_sleep>; - status = "okay"; - - ethphy0: ethernet-phy@4 { - reg = <4>; - }; - - ethphy1: ethernet-phy@5 { - reg = <5>; - }; -}; - -&cpsw_emac0 { - phy-handle = <ðphy0>; - phy-mode = "rgmii"; - dual_emac_res_vlan = <1>; -}; - -&cpsw_emac1 { - phy-handle = <ðphy1>; - phy-mode = "rgmii"; - dual_emac_res_vlan = <2>; -}; - -&elm { - status = "okay"; -}; - -&mcasp1 { - #sound-dai-cells = <0>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&mcasp1_pins>; - pinctrl-1 = <&mcasp1_pins_sleep>; - - status = "okay"; - - op-mode = <0>; - tdm-slots = <2>; - serial-dir = < - 0 0 1 2 - >; - - tx-num-evt = <1>; - rx-num-evt = <1>; -}; - -&dss { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&dss_pins>; - - port { - dpi_out: endpoint@0 { - remote-endpoint = <&lcd_in>; - data-lines = <24>; - }; - }; -}; - -&rtc { - clocks = <&clk_32k_rtc>, <&clk_32768_ck>; - clock-names = "ext-clk", "int-clk"; - status = "okay"; -}; - -&wdt { - status = "okay"; -}; - -&cpu { - cpu0-supply = <&dcdc2>; -}; - -&vpfe0 { - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&vpfe0_pins_default>; - pinctrl-1 = <&vpfe0_pins_sleep>; - - /* Camera port */ - port { - vpfe0_ep: endpoint { - /* remote-endpoint = <&sensor>; add once we have it */ - ti,am437x-vpfe-interface = <0>; - bus-width = <8>; - hsync-active = <0>; - vsync-active = <0>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/am43x-epos-evm.dts b/sys/gnu/dts/arm/am43x-epos-evm.dts deleted file mode 100644 index 95314121d11..00000000000 --- a/sys/gnu/dts/arm/am43x-epos-evm.dts +++ /dev/null @@ -1,1006 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ - */ - -/* AM43x EPOS EVM */ - -/dts-v1/; - -#include "am4372.dtsi" -#include -#include -#include -#include - -/ { - model = "TI AM43x EPOS EVM"; - compatible = "ti,am43x-epos-evm","ti,am438x","ti,am43"; - - aliases { - display0 = &lcd0; - }; - - chosen { - stdout-path = &uart0; - }; - - vmmcsd_fixed: fixedregulator-sd { - compatible = "regulator-fixed"; - regulator-name = "vmmcsd_fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - }; - - vbat: fixedregulator0 { - compatible = "regulator-fixed"; - regulator-name = "vbat"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - }; - - lcd0: display { - compatible = "osddisplays,osd057T0559-34ts", "panel-dpi"; - label = "lcd"; - - backlight = <&lcd_bl>; - - panel-timing { - clock-frequency = <33000000>; - hactive = <800>; - vactive = <480>; - hfront-porch = <210>; - hback-porch = <16>; - hsync-len = <30>; - vback-porch = <10>; - vfront-porch = <22>; - vsync-len = <13>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - - port { - lcd_in: endpoint { - remote-endpoint = <&dpi_out>; - }; - }; - }; - - matrix_keypad: matrix_keypad0 { - compatible = "gpio-matrix-keypad"; - debounce-delay-ms = <5>; - col-scan-delay-us = <2>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&matrix_keypad_default>; - pinctrl-1 = <&matrix_keypad_sleep>; - wakeup-source; - - row-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH /* Bank0, pin12 */ - &gpio0 13 GPIO_ACTIVE_HIGH /* Bank0, pin13 */ - &gpio0 14 GPIO_ACTIVE_HIGH /* Bank0, pin14 */ - &gpio0 15 GPIO_ACTIVE_HIGH>; /* Bank0, pin15 */ - - col-gpios = <&gpio3 9 GPIO_ACTIVE_HIGH /* Bank3, pin9 */ - &gpio3 10 GPIO_ACTIVE_HIGH /* Bank3, pin10 */ - &gpio2 18 GPIO_ACTIVE_HIGH /* Bank2, pin18 */ - &gpio2 19 GPIO_ACTIVE_HIGH>; /* Bank2, pin19 */ - - linux,keymap = <0x00000201 /* P1 */ - 0x01000204 /* P4 */ - 0x02000207 /* P7 */ - 0x0300020a /* NUMERIC_STAR */ - 0x00010202 /* P2 */ - 0x01010205 /* P5 */ - 0x02010208 /* P8 */ - 0x03010200 /* P0 */ - 0x00020203 /* P3 */ - 0x01020206 /* P6 */ - 0x02020209 /* P9 */ - 0x0302020b /* NUMERIC_POUND */ - 0x00030067 /* UP */ - 0x0103006a /* RIGHT */ - 0x0203006c /* DOWN */ - 0x03030069>; /* LEFT */ - }; - - lcd_bl: backlight { - compatible = "pwm-backlight"; - pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>; - brightness-levels = <0 51 53 56 62 75 101 152 255>; - default-brightness-level = <8>; - }; - - sound0: sound0 { - compatible = "simple-audio-card"; - simple-audio-card,name = "AM43-EPOS-EVM"; - simple-audio-card,widgets = - "Microphone", "Microphone Jack", - "Headphone", "Headphone Jack", - "Speaker", "Speaker"; - simple-audio-card,routing = - "MIC1LP", "Microphone Jack", - "MIC1RP", "Microphone Jack", - "MIC1LP", "MICBIAS", - "MIC1RP", "MICBIAS", - "Headphone Jack", "HPL", - "Headphone Jack", "HPR", - "Speaker", "SPL", - "Speaker", "SPR"; - simple-audio-card,format = "dsp_b"; - simple-audio-card,bitclock-master = <&sound0_master>; - simple-audio-card,frame-master = <&sound0_master>; - simple-audio-card,bitclock-inversion; - - simple-audio-card,cpu { - sound-dai = <&mcasp1>; - system-clock-frequency = <12000000>; - }; - - sound0_master: simple-audio-card,codec { - sound-dai = <&tlv320aic3111>; - system-clock-frequency = <12000000>; - }; - }; -}; - -&am43xx_pinmux { - pinctrl-names = "default"; - pinctrl-0 = <&unused_pins>; - - unused_pins: unused_pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x848, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7) - AM4372_IOPAD(0x850, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x858, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x860, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x864, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x868, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x86c, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x878, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7) - AM4372_IOPAD(0x908, DS0_PIN_INPUT_PULLDOWN | PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x91c, DS0_PIN_OUTPUT_PULLDOWN | PIN_OUTPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x920, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x9e0, DS0_PIN_INPUT_PULLDOWN | PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0xA0c, DS0_PIN_OUTPUT_PULLDOWN | PIN_OUTPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0xA38, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0xA3c, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0xA40, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0xA44, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0xA48, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0xA4c, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0xA50, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0xA54, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0xA58, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0xA5c, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0xA60, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0xA64, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7) - AM4372_IOPAD(0xA68, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0xA6C, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0xA74, DS0_PIN_INPUT_PULLDOWN | PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0xA78, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; - - cpsw_default: cpsw_default { - pinctrl-single,pins = < - /* Slave 1 */ - AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs */ - AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */ - AM4372_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txen.rmii1_txen */ - AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxdv.rmii1_rxdv */ - AM4372_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */ - AM4372_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */ - AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */ - AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */ - AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_refclk.rmii1_refclk */ - >; - }; - - cpsw_sleep: cpsw_sleep { - pinctrl-single,pins = < - /* Slave 1 reset value */ - AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; - - davinci_mdio_default: davinci_mdio_default { - pinctrl-single,pins = < - /* MDIO */ - AM4372_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ - AM4372_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ - >; - }; - - davinci_mdio_sleep: davinci_mdio_sleep { - pinctrl-single,pins = < - /* MDIO reset value */ - AM4372_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; - - i2c0_pins: pinmux_i2c0_pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x988, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */ - AM4372_IOPAD(0x98c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */ - >; - }; - - nand_flash_x8_default: nand_flash_x8_default { - pinctrl-single,pins = < - AM4372_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a0.SELQSPIorNAND/GPIO */ - AM4372_IOPAD(0x800, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ - AM4372_IOPAD(0x804, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ - AM4372_IOPAD(0x808, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ - AM4372_IOPAD(0x80c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ - AM4372_IOPAD(0x810, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ - AM4372_IOPAD(0x814, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ - AM4372_IOPAD(0x818, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ - AM4372_IOPAD(0x81c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ - AM4372_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ - AM4372_IOPAD(0x874, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpmc_wpn */ - AM4372_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ - AM4372_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ - AM4372_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ - AM4372_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */ - AM4372_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ - >; - }; - - nand_flash_x8_sleep: nand_flash_x8_sleep { - pinctrl-single,pins = < - AM4372_IOPAD(0x840, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x800, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x804, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x808, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x80c, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x810, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x814, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x818, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x81c, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x870, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) - AM4372_IOPAD(0x874, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) - AM4372_IOPAD(0x87c, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) - AM4372_IOPAD(0x890, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) - AM4372_IOPAD(0x894, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) - AM4372_IOPAD(0x898, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) - AM4372_IOPAD(0x89c, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) - >; - }; - - ecap0_pins_default: backlight_pins_default { - pinctrl-single,pins = < - AM4372_IOPAD(0x964, MUX_MODE0) /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */ - >; - }; - - ecap0_pins_sleep: backlight_pins_sleep { - pinctrl-single,pins = < - AM4372_IOPAD(0x964, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) - >; - }; - - i2c2_pins: pinmux_i2c2_pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x9c0, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE8) /* i2c2_sda.i2c2_sda */ - AM4372_IOPAD(0x9c4, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE8) /* i2c2_scl.i2c2_scl */ - >; - }; - - spi0_pins_default: pinmux_spi0_pins_default { - pinctrl-single,pins = < - AM4372_IOPAD(0x950, PIN_INPUT | MUX_MODE0) /* spi0_clk.spi0_clk */ - AM4372_IOPAD(0x954, PIN_OUTPUT | MUX_MODE0) /* spi0_d0.spi0_d0 */ - AM4372_IOPAD(0x958, PIN_INPUT | MUX_MODE0) /* spi0_d1.spi0_d1 */ - AM4372_IOPAD(0x95c, PIN_OUTPUT | MUX_MODE0) /* spi0_cs0.spi0_cs0 */ - >; - }; - - spi0_pins_sleep: pinmux_spi0_pins_sleep { - pinctrl-single,pins = < - AM4372_IOPAD(0x950, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7) - AM4372_IOPAD(0x954, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7) - AM4372_IOPAD(0x958, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7) - AM4372_IOPAD(0x95c, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7) - >; - }; - - spi1_pins_default: pinmux_spi1_pins_default { - pinctrl-single,pins = < - AM4372_IOPAD(0x990, PIN_INPUT | MUX_MODE3) /* mcasp0_aclkx.spi1_clk */ - AM4372_IOPAD(0x994, PIN_OUTPUT | MUX_MODE3) /* mcasp0_fsx.spi1_d0 */ - AM4372_IOPAD(0x998, PIN_INPUT | MUX_MODE3) /* mcasp0_axr0.spi1_d1 */ - AM4372_IOPAD(0x99c, PIN_OUTPUT | MUX_MODE3) /* mcasp0_ahclkr.spi1_cs0 */ - >; - }; - - spi1_pins_sleep: pinmux_spi1_pins_sleep { - pinctrl-single,pins = < - AM4372_IOPAD(0x990, DS0_PIN_OUTPUT_PULLDOWN | PIN_OUTPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x994, DS0_PIN_OUTPUT_PULLDOWN | PIN_OUTPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x998, DS0_PIN_OUTPUT_PULLDOWN | PIN_OUTPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x99c, DS0_PIN_OUTPUT_PULLDOWN | PIN_OUTPUT_PULLDOWN | MUX_MODE7) - >; - }; - - mmc1_pins_default: pinmux_mmc1_pins_default { - pinctrl-single,pins = < - AM4372_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ - >; - }; - - mmc1_pins_sleep: pinmux_mmc1_pins_sleep { - pinctrl-single,pins = < - AM4372_IOPAD(0x960, DS0_PIN_OUTPUT_PULLUP | PIN_INPUT | MUX_MODE7) - >; - }; - - matrix_keypad_default: matrix_keypad_default { - pinctrl-single,pins = < - AM4372_IOPAD(0x92c, PIN_OUTPUT | MUX_MODE7) /* mii1_tx_clk.gpio3_9 */ - AM4372_IOPAD(0x930, PIN_OUTPUT | MUX_MODE7) /* mii1_rx_clk.gpio3_10 */ - AM4372_IOPAD(0x934, PIN_OUTPUT | MUX_MODE7) /* mii1_rxd3.gpio2_18 */ - AM4372_IOPAD(0x938, PIN_OUTPUT | MUX_MODE7) /* mii1_rxd2.gpio2_19 */ - AM4372_IOPAD(0x978, PIN_INPUT_PULLDOWN | MUX_MODE7) /* uart1_ctsn.gpio0_12 */ - AM4372_IOPAD(0x97C, PIN_INPUT_PULLDOWN | MUX_MODE7) /* uart1_rtsn.gpio0_13 */ - AM4372_IOPAD(0x980, PIN_INPUT_PULLDOWN | MUX_MODE7) /* uart1_rxd.gpio0_14 */ - AM4372_IOPAD(0x984, PIN_INPUT_PULLDOWN | MUX_MODE7) /* uart1_txd.gpio0_15 */ - >; - }; - - matrix_keypad_sleep: matrix_keypad_sleep { - pinctrl-single,pins = < - AM4372_IOPAD(0x92c, PIN_INPUT_PULLUP | MUX_MODE7) - AM4372_IOPAD(0x930, PIN_INPUT_PULLUP | MUX_MODE7) - AM4372_IOPAD(0x934, PIN_INPUT_PULLUP | MUX_MODE7) - AM4372_IOPAD(0x938, PIN_INPUT_PULLUP | MUX_MODE7) - AM4372_IOPAD(0x978, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x97C, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x980, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x984, PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; - - qspi1_pins_default: qspi1_pins_default { - pinctrl-single,pins = < - AM4372_IOPAD(0x87c, PIN_INPUT_PULLUP | MUX_MODE3) - AM4372_IOPAD(0x888, PIN_INPUT_PULLUP | MUX_MODE2) - AM4372_IOPAD(0x890, PIN_INPUT_PULLUP | MUX_MODE3) - AM4372_IOPAD(0x894, PIN_INPUT_PULLUP | MUX_MODE3) - AM4372_IOPAD(0x898, PIN_INPUT_PULLUP | MUX_MODE3) - AM4372_IOPAD(0x89c, PIN_INPUT_PULLUP | MUX_MODE3) - >; - }; - - qspi1_pins_sleep: qspi1_pins_sleep { - pinctrl-single,pins = < - AM4372_IOPAD(0x87c, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) - AM4372_IOPAD(0x888, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) - AM4372_IOPAD(0x890, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) - AM4372_IOPAD(0x894, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) - AM4372_IOPAD(0x898, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) - AM4372_IOPAD(0x89c, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) - >; - }; - - pixcir_ts_pins_default: pixcir_ts_pins_default { - pinctrl-single,pins = < - AM4372_IOPAD(0x844, PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_a1.gpio1_17 */ - >; - }; - - pixcir_ts_pins_sleep: pixcir_ts_pins_sleep { - pinctrl-single,pins = < - AM4372_IOPAD(0x844, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a1.gpio1_17 */ - >; - }; - - hdq_pins: pinmux_hdq_pins { - pinctrl-single,pins = < - AM4372_IOPAD(0xa34, PIN_INPUT_PULLUP | MUX_MODE1) /* cam1_wen.hdq_gpio */ - >; - }; - - dss_pins: dss_pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x820, PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */ - AM4372_IOPAD(0x824, PIN_OUTPUT_PULLUP | MUX_MODE1) - AM4372_IOPAD(0x828, PIN_OUTPUT_PULLUP | MUX_MODE1) - AM4372_IOPAD(0x82c, PIN_OUTPUT_PULLUP | MUX_MODE1) - AM4372_IOPAD(0x830, PIN_OUTPUT_PULLUP | MUX_MODE1) - AM4372_IOPAD(0x834, PIN_OUTPUT_PULLUP | MUX_MODE1) - AM4372_IOPAD(0x838, PIN_OUTPUT_PULLUP | MUX_MODE1) - AM4372_IOPAD(0x83c, PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 15 -> DSS DATA 16 */ - AM4372_IOPAD(0x8a0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */ - AM4372_IOPAD(0x8a4, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8a8, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8ac, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8b0, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8b4, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8B8, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8bc, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8c0, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8c4, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8c8, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8cc, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8d0, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8d4, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8d8, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8dc, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */ - AM4372_IOPAD(0x8e0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */ - AM4372_IOPAD(0x8e4, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */ - AM4372_IOPAD(0x8e8, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */ - AM4372_IOPAD(0x8ec, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */ - >; - }; - - display_mux_pins: display_mux_pins { - pinctrl-single,pins = < - /* GPMC CLK -> GPIO 2_1 to select LCD / HDMI */ - AM4372_IOPAD(0x88C, PIN_OUTPUT_PULLUP | MUX_MODE7) - >; - }; - - vpfe1_pins_default: vpfe1_pins_default { - pinctrl-single,pins = < - AM4372_IOPAD(0x9cc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data9 mode 0 */ - AM4372_IOPAD(0x9d0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data8 mode 0 */ - AM4372_IOPAD(0x9d4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_hd mode 0 */ - AM4372_IOPAD(0x9d8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_vd mode 0 */ - AM4372_IOPAD(0x9dc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_pclk mode 0 */ - AM4372_IOPAD(0x9e8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data0 mode 0 */ - AM4372_IOPAD(0x9ec, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data1 mode 0 */ - AM4372_IOPAD(0x9f0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data2 mode 0 */ - AM4372_IOPAD(0x9f4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data3 mode 0 */ - AM4372_IOPAD(0x9f8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data4 mode 0 */ - AM4372_IOPAD(0x9fc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data5 mode 0 */ - AM4372_IOPAD(0xa00, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data6 mode 0 */ - AM4372_IOPAD(0xa04, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data7 mode 0 */ - >; - }; - - vpfe1_pins_sleep: vpfe1_pins_sleep { - pinctrl-single,pins = < - AM4372_IOPAD(0x9cc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - AM4372_IOPAD(0x9d0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - AM4372_IOPAD(0x9d4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - AM4372_IOPAD(0x9d8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - AM4372_IOPAD(0x9dc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - AM4372_IOPAD(0x9e8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - AM4372_IOPAD(0x9ec, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - AM4372_IOPAD(0x9f0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - AM4372_IOPAD(0x9f4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - AM4372_IOPAD(0x9f8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - AM4372_IOPAD(0x9fc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - AM4372_IOPAD(0xa00, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - AM4372_IOPAD(0xa04, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - >; - }; - - uart0_pins_default: uart0_pins_default { - pinctrl-single,pins = < - AM4372_IOPAD(0x968, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE0) /* uart0_ctsn.uart0_ctsn */ - AM4372_IOPAD(0x96C, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE0) /* uart0_rtsn.uart0_rtsn */ - AM4372_IOPAD(0x970, PIN_INPUT_PULLUP | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_rxd.uart0_rxd */ - AM4372_IOPAD(0x974, PIN_INPUT | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_txd.uart0_txd */ - >; - }; - - uart0_pins_sleep: uart0_pins_sleep { - pinctrl-single,pins = < - AM4372_IOPAD(0x968, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - AM4372_IOPAD(0x96C, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - AM4372_IOPAD(0x970, PIN_INPUT_PULLUP | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) - AM4372_IOPAD(0x974, PIN_INPUT | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) - >; - }; - - usb2_phy1_default: usb2_phy1_default { - pinctrl-single,pins = < - AM4372_IOPAD(0xac0, PIN_INPUT_PULLDOWN | MUX_MODE0) - >; - }; - - usb2_phy1_sleep: usb2_phy1_sleep { - pinctrl-single,pins = < - AM4372_IOPAD(0xac0, DS0_PULL_UP_DOWN_EN | PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; - - usb2_phy2_default: usb2_phy2_default { - pinctrl-single,pins = < - AM4372_IOPAD(0xac4, PIN_INPUT_PULLDOWN | MUX_MODE0) - >; - }; - - usb2_phy2_sleep: usb2_phy2_sleep { - pinctrl-single,pins = < - AM4372_IOPAD(0xac4, DS0_PULL_UP_DOWN_EN | PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; - - mcasp1_pins: mcasp1_pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x9a0, PIN_INPUT_PULLDOWN | MUX_MODE3) /* MCASP0_ACLKR/MCASP1_ACLKX */ - AM4372_IOPAD(0x9a4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* MCASP0_FSR/MCASP1_FSX */ - AM4372_IOPAD(0x9a8, PIN_OUTPUT_PULLDOWN | MUX_MODE3)/* MCASP0_AXR1/MCASP1_AXR0 */ - AM4372_IOPAD(0x9ac, PIN_INPUT_PULLDOWN | MUX_MODE3) /* MCASP0_AHCLKX/MCASP1_AXR1 */ - >; - }; - - mcasp1_sleep_pins: mcasp1_sleep_pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x9a0, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x9a4, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x9a8, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x9ac, PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; -}; - -&mmc1 { - status = "okay"; - vmmc-supply = <&vmmcsd_fixed>; - bus-width = <4>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&mmc1_pins_default>; - pinctrl-1 = <&mmc1_pins_sleep>; - cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; -}; - -&mac { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&cpsw_default>; - pinctrl-1 = <&cpsw_sleep>; - status = "okay"; - slaves = <1>; -}; - -&davinci_mdio { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&davinci_mdio_default>; - pinctrl-1 = <&davinci_mdio_sleep>; - status = "okay"; - - ethphy0: ethernet-phy@16 { - reg = <16>; - }; -}; - -&cpsw_emac0 { - phy-handle = <ðphy0>; - phy-mode = "rmii"; - phys = <&phy_gmii_sel 1 1>; -}; - -&i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - clock-frequency = <400000>; - - tps65218: tps65218@24 { - reg = <0x24>; - compatible = "ti,tps65218"; - interrupts = ; /* NMIn */ - interrupt-controller; - #interrupt-cells = <2>; - - dcdc1: regulator-dcdc1 { - regulator-name = "vdd_core"; - regulator-min-microvolt = <912000>; - regulator-max-microvolt = <1144000>; - regulator-boot-on; - regulator-always-on; - }; - - dcdc2: regulator-dcdc2 { - regulator-name = "vdd_mpu"; - regulator-min-microvolt = <912000>; - regulator-max-microvolt = <1378000>; - regulator-boot-on; - regulator-always-on; - }; - - dcdc3: regulator-dcdc3 { - regulator-name = "vdcdc3"; - regulator-boot-on; - regulator-always-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - regulator-state-disk { - regulator-off-in-suspend; - }; - }; - - dcdc4: regulator-dcdc4 { - regulator-name = "vdcdc4"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - dcdc5: regulator-dcdc5 { - regulator-name = "v1_0bat"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-boot-on; - regulator-always-on; - }; - - dcdc6: regulator-dcdc6 { - regulator-name = "v1_8bat"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1: regulator-ldo1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - }; - - at24@50 { - compatible = "atmel,24c256"; - pagesize = <64>; - reg = <0x50>; - }; - - pixcir_ts@5c { - compatible = "pixcir,pixcir_tangoc"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&pixcir_ts_pins_default>; - pinctrl-1 = <&pixcir_ts_pins_sleep>; - - reg = <0x5c>; - interrupt-parent = <&gpio1>; - interrupts = <17 IRQ_TYPE_EDGE_FALLING>; - - attb-gpio = <&gpio1 17 GPIO_ACTIVE_HIGH>; - - touchscreen-size-x = <1024>; - touchscreen-size-y = <600>; - }; - - tlv320aic3111: tlv320aic3111@18 { - #sound-dai-cells = <0>; - compatible = "ti,tlv320aic3111"; - reg = <0x18>; - status = "okay"; - - ai31xx-micbias-vg = ; - - /* Regulators */ - HPVDD-supply = <&dcdc4>; /* v3_3AUD -> V3_3D -> DCDC4 */ - SPRVDD-supply = <&vbat>; /* vbat */ - SPLVDD-supply = <&vbat>; /* vbat */ - AVDD-supply = <&dcdc4>; /* v3_3AUD -> V3_3D -> DCDC4 */ - IOVDD-supply = <&dcdc4>; /* V3_3D -> DCDC4 */ - DVDD-supply = <&ldo1>; /* V1_8AUD -> V1_8D -> LDO1 */ - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - status = "okay"; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&gpio2 { - pinctrl-names = "default"; - pinctrl-0 = <&display_mux_pins>; - status = "okay"; - - p1 { - /* - * SelLCDorHDMI selects between display and audio paths: - * Low: HDMI display with audio via HDMI - * High: LCD display with analog audio via aic3111 codec - */ - gpio-hog; - gpios = <1 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "SelLCDorHDMI"; - }; -}; - -&gpio3 { - status = "okay"; -}; - -&elm { - status = "okay"; -}; - -&gpmc { - status = "okay"; /* Disable QSPI when enabling GPMC (NAND) */ - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&nand_flash_x8_default>; - pinctrl-1 = <&nand_flash_x8_sleep>; - ranges = <0 0 0x08000000 0x01000000>; /* CS0 space. Min partition = 16MB */ - nand@0,0 { - compatible = "ti,omap2-nand"; - reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ - <1 IRQ_TYPE_NONE>; /* termcount */ - rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ - ti,nand-xfer-type = "prefetch-dma"; - ti,nand-ecc-opt = "bch16"; - ti,elm-id = <&elm>; - nand-bus-width = <8>; - gpmc,device-width = <1>; - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <40>; /* tCEA + tCHZ + 1 */ - gpmc,cs-wr-off-ns = <40>; - gpmc,adv-on-ns = <0>; /* cs-on-ns */ - gpmc,adv-rd-off-ns = <25>; /* min( tALH + tALS + 1) */ - gpmc,adv-wr-off-ns = <25>; /* min( tALH + tALS + 1) */ - gpmc,we-on-ns = <0>; /* cs-on-ns */ - gpmc,we-off-ns = <20>; /* we-on-time + tWP + 2 */ - gpmc,oe-on-ns = <3>; /* cs-on-ns + tRR + 2 */ - gpmc,oe-off-ns = <30>; /* oe-on-ns + tRP + 2 */ - gpmc,access-ns = <30>; /* tCEA + 4*/ - gpmc,rd-cycle-ns = <40>; - gpmc,wr-cycle-ns = <40>; - gpmc,bus-turnaround-ns = <0>; - gpmc,cycle2cycle-delay-ns = <0>; - gpmc,clk-activation-ns = <0>; - gpmc,wr-access-ns = <40>; - gpmc,wr-data-mux-bus-ns = <0>; - /* MTD partition table */ - /* All SPL-* partitions are sized to minimal length - * which can be independently programmable. For - * NAND flash this is equal to size of erase-block */ - #address-cells = <1>; - #size-cells = <1>; - partition@0 { - label = "NAND.SPL"; - reg = <0x00000000 0x00040000>; - }; - partition@1 { - label = "NAND.SPL.backup1"; - reg = <0x00040000 0x00040000>; - }; - partition@2 { - label = "NAND.SPL.backup2"; - reg = <0x00080000 0x00040000>; - }; - partition@3 { - label = "NAND.SPL.backup3"; - reg = <0x000C0000 0x00040000>; - }; - partition@4 { - label = "NAND.u-boot-spl-os"; - reg = <0x00100000 0x00080000>; - }; - partition@5 { - label = "NAND.u-boot"; - reg = <0x00180000 0x00100000>; - }; - partition@6 { - label = "NAND.u-boot-env"; - reg = <0x00280000 0x00040000>; - }; - partition@7 { - label = "NAND.u-boot-env.backup1"; - reg = <0x002C0000 0x00040000>; - }; - partition@8 { - label = "NAND.kernel"; - reg = <0x00300000 0x00700000>; - }; - partition@9 { - label = "NAND.file-system"; - reg = <0x00a00000 0x1f600000>; - }; - }; -}; - -&epwmss0 { - status = "okay"; -}; - -&tscadc { - status = "okay"; - - adc { - ti,adc-channels = <0 1 2 3 4 5 6 7>; - }; -}; - -&ecap0 { - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&ecap0_pins_default>; - pinctrl-1 = <&ecap0_pins_sleep>; -}; - -&spi0 { - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&spi0_pins_default>; - pinctrl-1 = <&spi0_pins_sleep>; -}; - -&spi1 { - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&spi1_pins_default>; - pinctrl-1 = <&spi1_pins_sleep>; -}; - -&usb2_phy1 { - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&usb2_phy1_default>; - pinctrl-1 = <&usb2_phy1_sleep>; -}; - -&usb1 { - dr_mode = "otg"; - status = "okay"; -}; - -&usb2_phy2 { - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&usb2_phy2_default>; - pinctrl-1 = <&usb2_phy2_sleep>; -}; - -&usb2 { - dr_mode = "host"; - status = "okay"; -}; - -&qspi { - status = "disabled"; /* Disable GPMC (NAND) when enabling QSPI */ - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qspi1_pins_default>; - pinctrl-1 = <&qspi1_pins_sleep>; - - spi-max-frequency = <48000000>; - m25p80@0 { - compatible = "mx66l51235l"; - spi-max-frequency = <48000000>; - reg = <0>; - spi-cpol; - spi-cpha; - spi-tx-bus-width = <1>; - spi-rx-bus-width = <4>; - #address-cells = <1>; - #size-cells = <1>; - - /* MTD partition table. - * The ROM checks the first 512KiB - * for a valid file to boot(XIP). - */ - partition@0 { - label = "QSPI.U_BOOT"; - reg = <0x00000000 0x000080000>; - }; - partition@1 { - label = "QSPI.U_BOOT.backup"; - reg = <0x00080000 0x00080000>; - }; - partition@2 { - label = "QSPI.U-BOOT-SPL_OS"; - reg = <0x00100000 0x00010000>; - }; - partition@3 { - label = "QSPI.U_BOOT_ENV"; - reg = <0x00110000 0x00010000>; - }; - partition@4 { - label = "QSPI.U-BOOT-ENV.backup"; - reg = <0x00120000 0x00010000>; - }; - partition@5 { - label = "QSPI.KERNEL"; - reg = <0x00130000 0x0800000>; - }; - partition@6 { - label = "QSPI.FILESYSTEM"; - reg = <0x00930000 0x36D0000>; - }; - }; -}; - -&hdq { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&hdq_pins>; -}; - -&dss { - status = "ok"; - - pinctrl-names = "default"; - pinctrl-0 = <&dss_pins>; - - port { - dpi_out: endpoint { - remote-endpoint = <&lcd_in>; - data-lines = <24>; - }; - }; -}; - -&vpfe1 { - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&vpfe1_pins_default>; - pinctrl-1 = <&vpfe1_pins_sleep>; - - port { - vpfe1_ep: endpoint { - /* remote-endpoint = <&sensor>; add once we have it */ - ti,am437x-vpfe-interface = <0>; - bus-width = <8>; - hsync-active = <0>; - vsync-active = <0>; - }; - }; -}; - -&uart0 { - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&uart0_pins_default>; - pinctrl-1 = <&uart0_pins_sleep>; -}; - -&mcasp1 { - #sound-dai-cells = <0>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&mcasp1_pins>; - pinctrl-1 = <&mcasp1_sleep_pins>; - - status = "okay"; - - op-mode = <0>; /* MCASP_IIS_MODE */ - tdm-slots = <2>; - /* 4 serializer */ - serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ - 1 2 0 0 - >; - tx-num-evt = <32>; - rx-num-evt = <32>; -}; - -&mux_synctimer32k_ck { - assigned-clocks = <&mux_synctimer32k_ck>; - assigned-clock-parents = <&clkdiv32k_ick>; -}; - -&cpu { - cpu0-supply = <&dcdc2>; -}; diff --git a/sys/gnu/dts/arm/am43xx-clocks.dtsi b/sys/gnu/dts/arm/am43xx-clocks.dtsi deleted file mode 100644 index 091356f2a8c..00000000000 --- a/sys/gnu/dts/arm/am43xx-clocks.dtsi +++ /dev/null @@ -1,829 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Device Tree Source for AM43xx clock data - * - * Copyright (C) 2013 Texas Instruments, Inc. - */ -&scm_clocks { - sys_clkin_ck: sys_clkin_ck@40 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sysboot_freq_sel_ck>, <&crystal_freq_sel_ck>; - ti,bit-shift = <31>; - reg = <0x0040>; - }; - - crystal_freq_sel_ck: crystal_freq_sel_ck@40 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>; - ti,bit-shift = <29>; - reg = <0x0040>; - }; - - sysboot_freq_sel_ck: sysboot_freq_sel_ck@44e10040 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>; - ti,bit-shift = <22>; - reg = <0x0040>; - }; - - adc_tsc_fck: adc_tsc_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&sys_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - dcan0_fck: dcan0_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&sys_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - dcan1_fck: dcan1_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&sys_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - mcasp0_fck: mcasp0_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&sys_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - mcasp1_fck: mcasp1_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&sys_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - smartreflex0_fck: smartreflex0_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&sys_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - smartreflex1_fck: smartreflex1_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&sys_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - sha0_fck: sha0_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&sys_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - aes0_fck: aes0_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&sys_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - rng_fck: rng_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&sys_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - ehrpwm0_tbclk: ehrpwm0_tbclk@664 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&l4ls_gclk>; - ti,bit-shift = <0>; - reg = <0x0664>; - }; - - ehrpwm1_tbclk: ehrpwm1_tbclk@664 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&l4ls_gclk>; - ti,bit-shift = <1>; - reg = <0x0664>; - }; - - ehrpwm2_tbclk: ehrpwm2_tbclk@664 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&l4ls_gclk>; - ti,bit-shift = <2>; - reg = <0x0664>; - }; - - ehrpwm3_tbclk: ehrpwm3_tbclk@664 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&l4ls_gclk>; - ti,bit-shift = <4>; - reg = <0x0664>; - }; - - ehrpwm4_tbclk: ehrpwm4_tbclk@664 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&l4ls_gclk>; - ti,bit-shift = <5>; - reg = <0x0664>; - }; - - ehrpwm5_tbclk: ehrpwm5_tbclk@664 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&l4ls_gclk>; - ti,bit-shift = <6>; - reg = <0x0664>; - }; -}; -&prcm_clocks { - clk_32768_ck: clk_32768_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - clk_rc32k_ck: clk_rc32k_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - virt_19200000_ck: virt_19200000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <19200000>; - }; - - virt_24000000_ck: virt_24000000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - }; - - virt_25000000_ck: virt_25000000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <25000000>; - }; - - virt_26000000_ck: virt_26000000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <26000000>; - }; - - tclkin_ck: tclkin_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <26000000>; - }; - - dpll_core_ck: dpll_core_ck@2d20 { - #clock-cells = <0>; - compatible = "ti,am3-dpll-core-clock"; - clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x2d20>, <0x2d24>, <0x2d2c>; - }; - - dpll_core_x2_ck: dpll_core_x2_ck { - #clock-cells = <0>; - compatible = "ti,am3-dpll-x2-clock"; - clocks = <&dpll_core_ck>; - }; - - dpll_core_m4_ck: dpll_core_m4_ck@2d38 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x2d38>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_core_m5_ck: dpll_core_m5_ck@2d3c { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x2d3c>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_core_m6_ck: dpll_core_m6_ck@2d40 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x2d40>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_mpu_ck: dpll_mpu_ck@2d60 { - #clock-cells = <0>; - compatible = "ti,am3-dpll-clock"; - clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x2d60>, <0x2d64>, <0x2d6c>; - }; - - dpll_mpu_m2_ck: dpll_mpu_m2_ck@2d70 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_mpu_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x2d70>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - mpu_periphclk: mpu_periphclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_mpu_m2_ck>; - clock-mult = <1>; - clock-div = <2>; - }; - - dpll_ddr_ck: dpll_ddr_ck@2da0 { - #clock-cells = <0>; - compatible = "ti,am3-dpll-clock"; - clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x2da0>, <0x2da4>, <0x2dac>; - }; - - dpll_ddr_m2_ck: dpll_ddr_m2_ck@2db0 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_ddr_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x2db0>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_disp_ck: dpll_disp_ck@2e20 { - #clock-cells = <0>; - compatible = "ti,am3-dpll-clock"; - clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x2e20>, <0x2e24>, <0x2e2c>; - }; - - dpll_disp_m2_ck: dpll_disp_m2_ck@2e30 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_disp_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x2e30>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - ti,set-rate-parent; - }; - - dpll_per_ck: dpll_per_ck@2de0 { - #clock-cells = <0>; - compatible = "ti,am3-dpll-j-type-clock"; - clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x2de0>, <0x2de4>, <0x2dec>; - }; - - dpll_per_m2_ck: dpll_per_m2_ck@2df0 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_per_ck>; - ti,max-div = <127>; - ti,autoidle-shift = <8>; - reg = <0x2df0>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_per_m2_div4_wkupdm_ck: dpll_per_m2_div4_wkupdm_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_per_m2_ck>; - clock-mult = <1>; - clock-div = <4>; - }; - - dpll_per_m2_div4_ck: dpll_per_m2_div4_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_per_m2_ck>; - clock-mult = <1>; - clock-div = <4>; - }; - - clk_24mhz: clk_24mhz { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_per_m2_ck>; - clock-mult = <1>; - clock-div = <8>; - }; - - clkdiv32k_ck: clkdiv32k_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&clk_24mhz>; - clock-mult = <1>; - clock-div = <732>; - }; - - clkdiv32k_ick: clkdiv32k_ick@2a38 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&clkdiv32k_ck>; - ti,bit-shift = <8>; - reg = <0x2a38>; - }; - - sysclk_div: sysclk_div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_core_m4_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - pruss_ocp_gclk: pruss_ocp_gclk@4248 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sysclk_div>, <&dpll_disp_m2_ck>; - reg = <0x4248>; - }; - - clk_32k_tpm_ck: clk_32k_tpm_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - timer1_fck: timer1_fck@4200 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>, <&clk_32k_tpm_ck>; - reg = <0x4200>; - }; - - timer2_fck: timer2_fck@4204 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; - reg = <0x4204>; - }; - - timer3_fck: timer3_fck@4208 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; - reg = <0x4208>; - }; - - timer4_fck: timer4_fck@420c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; - reg = <0x420c>; - }; - - timer5_fck: timer5_fck@4210 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; - reg = <0x4210>; - }; - - timer6_fck: timer6_fck@4214 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; - reg = <0x4214>; - }; - - timer7_fck: timer7_fck@4218 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; - reg = <0x4218>; - }; - - wdt1_fck: wdt1_fck@422c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&clk_rc32k_ck>, <&clkdiv32k_ick>; - reg = <0x422c>; - }; - - l3_gclk: l3_gclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_core_m4_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - dpll_core_m4_div2_ck: dpll_core_m4_div2_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&sysclk_div>; - clock-mult = <1>; - clock-div = <2>; - }; - - l4hs_gclk: l4hs_gclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_core_m4_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - l3s_gclk: l3s_gclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_core_m4_div2_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - l4ls_gclk: l4ls_gclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_core_m4_div2_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - cpsw_125mhz_gclk: cpsw_125mhz_gclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_core_m5_ck>; - clock-mult = <1>; - clock-div = <2>; - }; - - cpsw_cpts_rft_clk: cpsw_cpts_rft_clk@4238 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sysclk_div>, <&dpll_core_m5_ck>, <&dpll_disp_m2_ck>; - reg = <0x4238>; - }; - - dpll_clksel_mac_clk: dpll_clksel_mac_clk@4234 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_core_m5_ck>; - reg = <0x4234>; - ti,bit-shift = <2>; - ti,dividers = <2>, <5>; - }; - - clk_32k_mosc_ck: clk_32k_mosc_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck@4240 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clkdiv32k_ick>, <&clk_32k_mosc_ck>, <&clk_32k_tpm_ck>; - reg = <0x4240>; - }; - - mmc_clk: mmc_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_per_m2_ck>; - clock-mult = <1>; - clock-div = <2>; - }; - - gfx_fclk_clksel_ck: gfx_fclk_clksel_ck@423c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sysclk_div>, <&dpll_per_m2_ck>; - ti,bit-shift = <1>; - reg = <0x423c>; - }; - - gfx_fck_div_ck: gfx_fck_div_ck@423c { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&gfx_fclk_clksel_ck>; - reg = <0x423c>; - ti,max-div = <2>; - }; - - disp_clk: disp_clk@4244 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>; - reg = <0x4244>; - ti,set-rate-parent; - }; - - dpll_extdev_ck: dpll_extdev_ck@2e60 { - #clock-cells = <0>; - compatible = "ti,am3-dpll-clock"; - clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x2e60>, <0x2e64>, <0x2e6c>; - }; - - dpll_extdev_m2_ck: dpll_extdev_m2_ck@2e70 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_extdev_ck>; - ti,max-div = <127>; - ti,autoidle-shift = <8>; - reg = <0x2e70>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - mux_synctimer32k_ck: mux_synctimer32k_ck@4230 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>, <&clkdiv32k_ick>; - reg = <0x4230>; - }; - - timer8_fck: timer8_fck@421c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>; - reg = <0x421c>; - }; - - timer9_fck: timer9_fck@4220 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>; - reg = <0x4220>; - }; - - timer10_fck: timer10_fck@4224 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>; - reg = <0x4224>; - }; - - timer11_fck: timer11_fck@4228 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>; - reg = <0x4228>; - }; - - cpsw_50m_clkdiv: cpsw_50m_clkdiv { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_core_m5_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - cpsw_5m_clkdiv: cpsw_5m_clkdiv { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&cpsw_50m_clkdiv>; - clock-mult = <1>; - clock-div = <10>; - }; - - dpll_ddr_x2_ck: dpll_ddr_x2_ck { - #clock-cells = <0>; - compatible = "ti,am3-dpll-x2-clock"; - clocks = <&dpll_ddr_ck>; - }; - - dpll_ddr_m4_ck: dpll_ddr_m4_ck@2db8 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_ddr_x2_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x2db8>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_per_clkdcoldo: dpll_per_clkdcoldo@2e14 { - #clock-cells = <0>; - compatible = "ti,fixed-factor-clock"; - clocks = <&dpll_per_ck>; - ti,clock-mult = <1>; - ti,clock-div = <1>; - ti,autoidle-shift = <8>; - reg = <0x2e14>; - ti,invert-autoidle-bit; - }; - - dll_aging_clk_div: dll_aging_clk_div@4250 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&sys_clkin_ck>; - reg = <0x4250>; - ti,dividers = <8>, <16>, <32>; - }; - - div_core_25m_ck: div_core_25m_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&sysclk_div>; - clock-mult = <1>; - clock-div = <8>; - }; - - func_12m_clk: func_12m_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_per_m2_ck>; - clock-mult = <1>; - clock-div = <16>; - }; - - vtp_clk_div: vtp_clk_div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&sys_clkin_ck>; - clock-mult = <1>; - clock-div = <2>; - }; - - usbphy_32khz_clkmux: usbphy_32khz_clkmux@4260 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>; - reg = <0x4260>; - }; - - usb_phy0_always_on_clk32k: usb_phy0_always_on_clk32k@2a40 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&usbphy_32khz_clkmux>; - ti,bit-shift = <8>; - reg = <0x2a40>; - }; - - usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k@2a48 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&usbphy_32khz_clkmux>; - ti,bit-shift = <8>; - reg = <0x2a48>; - }; -}; - -&prcm { - wkup_cm: wkup-cm@2800 { - compatible = "ti,omap4-cm"; - reg = <0x2800 0x400>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x2800 0x400>; - - l3s_tsc_clkctrl: l3s-tsc-clkctrl@120 { - compatible = "ti,clkctrl"; - reg = <0x120 0x4>; - #clock-cells = <2>; - }; - - l4_wkup_aon_clkctrl: l4-wkup-aon-clkctrl@228 { - compatible = "ti,clkctrl"; - reg = <0x228 0xc>; - #clock-cells = <2>; - }; - - l4_wkup_clkctrl: l4-wkup-clkctrl@220 { - compatible = "ti,clkctrl"; - reg = <0x220 0x4>, <0x328 0x44>; - #clock-cells = <2>; - }; - - }; - - mpu_cm: mpu-cm@8300 { - compatible = "ti,omap4-cm"; - reg = <0x8300 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x8300 0x100>; - - mpu_clkctrl: mpu-clkctrl@20 { - compatible = "ti,clkctrl"; - reg = <0x20 0x4>; - #clock-cells = <2>; - }; - }; - - gfx_l3_cm: gfx-l3-cm@8400 { - compatible = "ti,omap4-cm"; - reg = <0x8400 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x8400 0x100>; - - gfx_l3_clkctrl: gfx-l3-clkctrl@20 { - compatible = "ti,clkctrl"; - reg = <0x20 0x4>; - #clock-cells = <2>; - }; - }; - - l4_rtc_cm: l4-rtc-cm@8500 { - compatible = "ti,omap4-cm"; - reg = <0x8500 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x8500 0x100>; - - l4_rtc_clkctrl: l4-rtc-clkctrl@20 { - compatible = "ti,clkctrl"; - reg = <0x20 0x4>; - #clock-cells = <2>; - }; - }; - - per_cm: per-cm@8800 { - compatible = "ti,omap4-cm"; - reg = <0x8800 0xc00>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x8800 0xc00>; - - l3_clkctrl: l3-clkctrl@20 { - compatible = "ti,clkctrl"; - reg = <0x20 0x3c>, <0x78 0x2c>; - #clock-cells = <2>; - }; - - l3s_clkctrl: l3s-clkctrl@68 { - compatible = "ti,clkctrl"; - reg = <0x68 0xc>, <0x220 0x4c>; - #clock-cells = <2>; - }; - - pruss_ocp_clkctrl: pruss-ocp-clkctrl@320 { - compatible = "ti,clkctrl"; - reg = <0x320 0x4>; - #clock-cells = <2>; - }; - - l4ls_clkctrl: l4ls-clkctrl@420 { - compatible = "ti,clkctrl"; - reg = <0x420 0x1a4>; - #clock-cells = <2>; - }; - - emif_clkctrl: emif-clkctrl@720 { - compatible = "ti,clkctrl"; - reg = <0x720 0x4>; - #clock-cells = <2>; - }; - - dss_clkctrl: dss-clkctrl@a20 { - compatible = "ti,clkctrl"; - reg = <0xa20 0x4>; - #clock-cells = <2>; - }; - - cpsw_125mhz_clkctrl: cpsw-125mhz-clkctrl@b20 { - compatible = "ti,clkctrl"; - reg = <0xb20 0x4>; - #clock-cells = <2>; - }; - - }; -}; diff --git a/sys/gnu/dts/arm/am5718.dtsi b/sys/gnu/dts/arm/am5718.dtsi deleted file mode 100644 index d51007c3e8c..00000000000 --- a/sys/gnu/dts/arm/am5718.dtsi +++ /dev/null @@ -1,32 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ - */ - -#include "dra72x.dtsi" - -/ { - compatible = "ti,am5718", "ti,dra7"; -}; - -/* - * These modules are not present on AM5718 - * - * ATL - * VCP1, VCP2 - * MLB - * ISS - * USB3, USB4 - */ - -&usb3_tm { - status = "disabled"; -}; - -&usb4_tm { - status = "disabled"; -}; - -&atl_tm { - status = "disabled"; -}; diff --git a/sys/gnu/dts/arm/am571x-idk.dts b/sys/gnu/dts/arm/am571x-idk.dts deleted file mode 100644 index 0aaacea1d88..00000000000 --- a/sys/gnu/dts/arm/am571x-idk.dts +++ /dev/null @@ -1,188 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/ - */ -/dts-v1/; - -#include "am5718.dtsi" -#include -#include -#include "dra7-mmc-iodelay.dtsi" -#include "dra72x-mmc-iodelay.dtsi" -#include "am57xx-idk-common.dtsi" - -/ { - model = "TI AM5718 IDK"; - compatible = "ti,am5718-idk", "ti,am5718", "ti,dra7"; - - memory@80000000 { - device_type = "memory"; - reg = <0x0 0x80000000 0x0 0x40000000>; - }; - - leds { - compatible = "gpio-leds"; - cpu0-led { - label = "status0:red:cpu0"; - gpios = <&gpio2 25 GPIO_ACTIVE_HIGH>; - default-state = "off"; - linux,default-trigger = "cpu0"; - }; - - usr0-led { - label = "status0:green:usr"; - gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - heartbeat-led { - label = "status0:blue:heartbeat"; - gpios = <&gpio2 27 GPIO_ACTIVE_HIGH>; - default-state = "off"; - linux,default-trigger = "heartbeat"; - }; - - usr1-led { - label = "status1:red:usr"; - gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - usr2-led { - label = "status1:green:usr"; - gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - mmc0-led { - label = "status1:blue:mmc0"; - gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>; - default-state = "off"; - linux,default-trigger = "mmc0"; - }; - }; - - idk-leds { - status = "disabled"; - compatible = "gpio-leds"; - red0-led { - label = "idk:red0"; - gpios = <&gpio6 19 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - green0-led { - label = "idk:green0"; - gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - blue0-led { - label = "idk:blue0"; - gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - red1-led { - label = "idk:red1"; - gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - green1-led { - label = "idk:green1"; - gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - blue1-led { - label = "idk:blue1"; - gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - red2-led { - label = "idk:red2"; - gpios = <&gpio7 9 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - green2-led { - label = "idk:green2"; - gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - blue2-led { - label = "idk:blue2"; - gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - red3-led { - label = "idk:red3"; - gpios = <&gpio7 11 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - green3-led { - label = "idk:green3"; - gpios = <&gpio7 25 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - blue3-led { - label = "idk:blue3"; - gpios = <&gpio7 24 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; -}; - -&extcon_usb2 { - id-gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>; - vbus-gpio = <&gpio7 22 GPIO_ACTIVE_HIGH>; -}; - -&sn65hvs882 { - load-gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; -}; - -&mailbox5 { - status = "okay"; - mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { - status = "okay"; - }; - mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { - status = "okay"; - }; -}; - -&mailbox6 { - status = "okay"; - mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { - status = "okay"; - }; -}; - -&pcie1_rc { - status = "okay"; - gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>; -}; - -&pcie1_ep { - gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>; -}; - -&mmc1 { - pinctrl-names = "default", "hs"; - pinctrl-0 = <&mmc1_pins_default_no_clk_pu>; - pinctrl-1 = <&mmc1_pins_hs>; -}; - -&mmc2 { - pinctrl-names = "default", "hs", "ddr_3_3v"; - pinctrl-0 = <&mmc2_pins_default>; - pinctrl-1 = <&mmc2_pins_hs>; - pinctrl-2 = <&mmc2_pins_ddr_rev20 &mmc2_iodelay_ddr_conf>; -}; diff --git a/sys/gnu/dts/arm/am5728.dtsi b/sys/gnu/dts/arm/am5728.dtsi deleted file mode 100644 index 82e5427ef6a..00000000000 --- a/sys/gnu/dts/arm/am5728.dtsi +++ /dev/null @@ -1,33 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ - */ - -#include "dra74x.dtsi" - -/ { - compatible = "ti,am5728", "ti,dra7"; -}; - -/* - * These modules are not present on AM5728 - * - * EVE1, EVE2 - * ATL - * VCP1, VCP2 - * MLB - * ISS - * USB3, USB4 - */ - -&usb3_tm { - status = "disabled"; -}; - -&usb4_tm { - status = "disabled"; -}; - -&atl_tm { - status = "disabled"; -}; diff --git a/sys/gnu/dts/arm/am572x-idk-common.dtsi b/sys/gnu/dts/arm/am572x-idk-common.dtsi deleted file mode 100644 index a064f13b388..00000000000 --- a/sys/gnu/dts/arm/am572x-idk-common.dtsi +++ /dev/null @@ -1,172 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ - */ - -#include -#include -#include "am57xx-idk-common.dtsi" - -/ { - memory@0 { - device_type = "memory"; - reg = <0x0 0x80000000 0x0 0x80000000>; - }; - - status-leds { - compatible = "gpio-leds"; - cpu0-led { - label = "status0:red:cpu0"; - gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>; - default-state = "off"; - linux,default-trigger = "cpu0"; - }; - - usr0-led { - label = "status0:green:usr"; - gpios = <&gpio3 11 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - heartbeat-led { - label = "status0:blue:heartbeat"; - gpios = <&gpio3 12 GPIO_ACTIVE_HIGH>; - default-state = "off"; - linux,default-trigger = "heartbeat"; - }; - - cpu1-led { - label = "status1:red:cpu1"; - gpios = <&gpio3 10 GPIO_ACTIVE_HIGH>; - default-state = "off"; - linux,default-trigger = "cpu1"; - }; - - usr1-led { - label = "status1:green:usr"; - gpios = <&gpio7 23 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - mmc0-led { - label = "status1:blue:mmc0"; - gpios = <&gpio7 22 GPIO_ACTIVE_HIGH>; - default-state = "off"; - linux,default-trigger = "mmc0"; - }; - }; - - idk-leds { - status = "disabled"; - compatible = "gpio-leds"; - red0-led { - label = "idk:red0"; - gpios = <&gpio6 19 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - green0-led { - label = "idk:green0"; - gpios = <&gpio3 9 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - blue0-led { - label = "idk:blue0"; - gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - red1-led { - label = "idk:red1"; - gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - green1-led { - label = "idk:green1"; - gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - blue1-led { - label = "idk:blue1"; - gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - red2-led { - label = "idk:red2"; - gpios = <&gpio7 9 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - green2-led { - label = "idk:green2"; - gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - blue2-led { - label = "idk:blue2"; - gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - red3-led { - label = "idk:red3"; - gpios = <&gpio7 11 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - green3-led { - label = "idk:green3"; - gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - blue3-led { - label = "idk:blue3"; - gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; -}; - -&extcon_usb2 { - id-gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>; - vbus-gpio = <&gpio3 26 GPIO_ACTIVE_HIGH>; -}; - -&sn65hvs882 { - load-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; -}; - -&pcie1_rc { - status = "okay"; - gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>; -}; - -&pcie1_ep { - gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>; -}; - -&mailbox5 { - status = "okay"; - mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { - status = "okay"; - }; - mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { - status = "okay"; - }; -}; - -&mailbox6 { - status = "okay"; - mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { - status = "okay"; - }; - mbox_dsp2_ipc3x: mbox_dsp2_ipc3x { - status = "okay"; - }; -}; diff --git a/sys/gnu/dts/arm/am572x-idk.dts b/sys/gnu/dts/arm/am572x-idk.dts deleted file mode 100644 index ea1c119feaa..00000000000 --- a/sys/gnu/dts/arm/am572x-idk.dts +++ /dev/null @@ -1,29 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/ - */ - -/dts-v1/; - -#include "am5728.dtsi" -#include "dra7-mmc-iodelay.dtsi" -#include "dra74x-mmc-iodelay.dtsi" -#include "am572x-idk-common.dtsi" - -/ { - model = "TI AM5728 IDK"; - compatible = "ti,am5728-idk", "ti,am5728", "ti,dra7"; -}; - -&mmc1 { - pinctrl-names = "default", "hs"; - pinctrl-0 = <&mmc1_pins_default_no_clk_pu>; - pinctrl-1 = <&mmc1_pins_hs>; -}; - -&mmc2 { - pinctrl-names = "default", "hs", "ddr_3_3v"; - pinctrl-0 = <&mmc2_pins_default>; - pinctrl-1 = <&mmc2_pins_hs>; - pinctrl-2 = <&mmc2_pins_ddr_rev20>; -}; diff --git a/sys/gnu/dts/arm/am5748.dtsi b/sys/gnu/dts/arm/am5748.dtsi deleted file mode 100644 index 5e129759d04..00000000000 --- a/sys/gnu/dts/arm/am5748.dtsi +++ /dev/null @@ -1,33 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ - */ - -#include "dra76x.dtsi" - -/ { - compatible = "ti,am5748", "ti,dra762", "ti,dra7"; -}; - -/* - * These modules are not present on AM5748 - * - * EVE1, EVE2 - * ATL - * VCP1, VCP2 - * MLB - * ISS - * USB3, USB4 - */ - -&usb3_tm { - status = "disabled"; -}; - -&usb4_tm { - status = "disabled"; -}; - -&atl_tm { - status = "disabled"; -}; diff --git a/sys/gnu/dts/arm/am574x-idk.dts b/sys/gnu/dts/arm/am574x-idk.dts deleted file mode 100644 index 7935d70874c..00000000000 --- a/sys/gnu/dts/arm/am574x-idk.dts +++ /dev/null @@ -1,37 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ - */ - - -/dts-v1/; - -#include "am5748.dtsi" -#include "dra7-mmc-iodelay.dtsi" -#include "dra76x-mmc-iodelay.dtsi" -#include "am572x-idk-common.dtsi" - -/ { - model = "TI AM5748 IDK"; - compatible = "ti,am5748-idk", "ti,am5748", "ti,dra762", "ti,dra7"; -}; - -&qspi { - spi-max-frequency = <96000000>; - m25p80@0 { - spi-max-frequency = <96000000>; - }; -}; - -&mmc1 { - pinctrl-names = "default", "hs"; - pinctrl-0 = <&mmc1_pins_default_no_clk_pu>; - pinctrl-1 = <&mmc1_pins_hs>; -}; - -&mmc2 { - pinctrl-names = "default", "hs", "ddr_3_3v"; - pinctrl-0 = <&mmc2_pins_default>; - pinctrl-1 = <&mmc2_pins_default>; - pinctrl-2 = <&mmc2_pins_default>; -}; diff --git a/sys/gnu/dts/arm/am57xx-beagle-x15-common.dtsi b/sys/gnu/dts/arm/am57xx-beagle-x15-common.dtsi deleted file mode 100644 index bc76f1705c0..00000000000 --- a/sys/gnu/dts/arm/am57xx-beagle-x15-common.dtsi +++ /dev/null @@ -1,588 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/ - */ -/dts-v1/; - -#include "am5728.dtsi" -#include "am57xx-commercial-grade.dtsi" -#include "dra74x-mmc-iodelay.dtsi" -#include -#include - -/ { - compatible = "ti,am572x-beagle-x15", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7"; - - aliases { - rtc0 = &mcp_rtc; - rtc1 = &tps659038_rtc; - rtc2 = &rtc; - display0 = &hdmi0; - }; - - chosen { - stdout-path = &uart3; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x80000000 0x0 0x80000000>; - }; - - vdd_3v3: fixedregulator-vdd_3v3 { - compatible = "regulator-fixed"; - regulator-name = "vdd_3v3"; - vin-supply = <®en1>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - aic_dvdd: fixedregulator-aic_dvdd { - compatible = "regulator-fixed"; - regulator-name = "aic_dvdd_fixed"; - vin-supply = <&vdd_3v3>; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vtt_fixed: fixedregulator-vtt { - /* TPS51200 */ - compatible = "regulator-fixed"; - regulator-name = "vtt_fixed"; - vin-supply = <&smps3_reg>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>; - }; - - leds { - compatible = "gpio-leds"; - - led0 { - label = "beagle-x15:usr0"; - gpios = <&gpio7 9 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - - led1 { - label = "beagle-x15:usr1"; - gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "cpu0"; - default-state = "off"; - }; - - led2 { - label = "beagle-x15:usr2"; - gpios = <&gpio7 14 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc0"; - default-state = "off"; - }; - - led3 { - label = "beagle-x15:usr3"; - gpios = <&gpio7 15 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "disk-activity"; - default-state = "off"; - }; - }; - - gpio_fan: gpio_fan { - /* Based on 5v 500mA AFB02505HHB */ - compatible = "gpio-fan"; - gpios = <&tps659038_gpio 2 GPIO_ACTIVE_HIGH>; - gpio-fan,speed-map = <0 0>, - <13000 1>; - #cooling-cells = <2>; - }; - - hdmi0: connector { - compatible = "hdmi-connector"; - label = "hdmi"; - - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&tpd12s015_out>; - }; - }; - }; - - tpd12s015: encoder { - compatible = "ti,tpd12s015"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - tpd12s015_in: endpoint { - remote-endpoint = <&hdmi_out>; - }; - }; - - port@1 { - reg = <1>; - - tpd12s015_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; - }; - }; - }; - - sound0: sound0 { - compatible = "simple-audio-card"; - simple-audio-card,name = "BeagleBoard-X15"; - simple-audio-card,widgets = - "Line", "Line Out", - "Line", "Line In"; - simple-audio-card,routing = - "Line Out", "LLOUT", - "Line Out", "RLOUT", - "MIC2L", "Line In", - "MIC2R", "Line In"; - simple-audio-card,format = "dsp_b"; - simple-audio-card,bitclock-master = <&sound0_master>; - simple-audio-card,frame-master = <&sound0_master>; - simple-audio-card,bitclock-inversion; - - simple-audio-card,cpu { - sound-dai = <&mcasp3>; - }; - - sound0_master: simple-audio-card,codec { - sound-dai = <&tlv320aic3104>; - clocks = <&clkout2_clk>; - }; - }; -}; - -&i2c1 { - status = "okay"; - clock-frequency = <400000>; - - tps659038: tps659038@58 { - compatible = "ti,tps659038"; - reg = <0x58>; - interrupt-parent = <&gpio1>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - - #interrupt-cells = <2>; - interrupt-controller; - - ti,system-power-controller; - ti,palmas-override-powerhold; - - tps659038_pmic { - compatible = "ti,tps659038-pmic"; - - regulators { - smps12_reg: smps12 { - /* VDD_MPU */ - regulator-name = "smps12"; - regulator-min-microvolt = < 850000>; - regulator-max-microvolt = <1250000>; - regulator-always-on; - regulator-boot-on; - }; - - smps3_reg: smps3 { - /* VDD_DDR */ - regulator-name = "smps3"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - - smps45_reg: smps45 { - /* VDD_DSPEVE, VDD_IVA, VDD_GPU */ - regulator-name = "smps45"; - regulator-min-microvolt = < 850000>; - regulator-max-microvolt = <1250000>; - regulator-always-on; - regulator-boot-on; - }; - - smps6_reg: smps6 { - /* VDD_CORE */ - regulator-name = "smps6"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1150000>; - regulator-always-on; - regulator-boot-on; - }; - - /* SMPS7 unused */ - - smps8_reg: smps8 { - /* VDD_1V8 */ - regulator-name = "smps8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - /* SMPS9 unused */ - - ldo1_reg: ldo1 { - /* VDD_SD / VDDSHV8 */ - regulator-name = "ldo1"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo2_reg: ldo2 { - /* VDD_SHV5 */ - regulator-name = "ldo2"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo3_reg: ldo3 { - /* VDDA_1V8_PHYA */ - regulator-name = "ldo3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo4_reg: ldo4 { - /* VDDA_1V8_PHYB */ - regulator-name = "ldo4"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo9_reg: ldo9 { - /* VDD_RTC */ - regulator-name = "ldo9"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - regulator-always-on; - regulator-boot-on; - }; - - ldoln_reg: ldoln { - /* VDDA_1V8_PLL */ - regulator-name = "ldoln"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldousb_reg: ldousb { - /* VDDA_3V_USB: VDDA_USBHS33 */ - regulator-name = "ldousb"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; - - regen1: regen1 { - /* VDD_3V3_ON */ - regulator-name = "regen1"; - regulator-boot-on; - regulator-always-on; - }; - }; - }; - - tps659038_rtc: tps659038_rtc { - compatible = "ti,palmas-rtc"; - interrupt-parent = <&tps659038>; - interrupts = <8 IRQ_TYPE_EDGE_FALLING>; - wakeup-source; - }; - - tps659038_pwr_button: tps659038_pwr_button { - compatible = "ti,palmas-pwrbutton"; - interrupt-parent = <&tps659038>; - interrupts = <1 IRQ_TYPE_EDGE_FALLING>; - wakeup-source; - ti,palmas-long-press-seconds = <12>; - }; - - tps659038_gpio: tps659038_gpio { - compatible = "ti,palmas-gpio"; - gpio-controller; - #gpio-cells = <2>; - }; - - extcon_usb2: tps659038_usb { - compatible = "ti,palmas-usb-vid"; - ti,enable-vbus-detection; - vbus-gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; - }; - - }; - - tmp102: tmp102@48 { - compatible = "ti,tmp102"; - reg = <0x48>; - interrupt-parent = <&gpio7>; - interrupts = <16 IRQ_TYPE_LEVEL_LOW>; - #thermal-sensor-cells = <1>; - }; - - tlv320aic3104: tlv320aic3104@18 { - #sound-dai-cells = <0>; - compatible = "ti,tlv320aic3104"; - reg = <0x18>; - assigned-clocks = <&clkoutmux2_clk_mux>; - assigned-clock-parents = <&sys_clk2_dclk_div>; - - status = "okay"; - adc-settle-ms = <40>; - - AVDD-supply = <&vdd_3v3>; - IOVDD-supply = <&vdd_3v3>; - DRVDD-supply = <&vdd_3v3>; - DVDD-supply = <&aic_dvdd>; - }; - - eeprom: eeprom@50 { - compatible = "atmel,24c32"; - reg = <0x50>; - }; -}; - -&i2c3 { - status = "okay"; - clock-frequency = <400000>; - - mcp_rtc: rtc@6f { - compatible = "microchip,mcp7941x"; - reg = <0x6f>; - interrupts-extended = <&crossbar_mpu GIC_SPI 2 IRQ_TYPE_EDGE_RISING>, - <&dra7_pmx_core 0x424>; - interrupt-names = "irq", "wakeup"; - - vcc-supply = <&vdd_3v3>; - wakeup-source; - }; -}; - -&gpio7_target { - ti,no-reset-on-init; - ti,no-idle-on-init; -}; - -&cpu0 { - vdd-supply = <&smps12_reg>; - voltage-tolerance = <1>; -}; - -&uart3 { - status = "okay"; - interrupts-extended = <&crossbar_mpu GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, - <&dra7_pmx_core 0x3f8>; -}; - -&davinci_mdio { - phy0: ethernet-phy@1 { - reg = <1>; - }; - - phy1: ethernet-phy@2 { - reg = <2>; - }; -}; - -&mac { - status = "okay"; - dual_emac; -}; - -&cpsw_emac0 { - phy-handle = <&phy0>; - phy-mode = "rgmii"; - dual_emac_res_vlan = <1>; -}; - -&cpsw_emac1 { - phy-handle = <&phy1>; - phy-mode = "rgmii"; - dual_emac_res_vlan = <2>; -}; - -&mmc1 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins_default>; - - bus-width = <4>; - cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; /* gpio 219 */ - no-1-8-v; -}; - -&mmc2 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins_default>; - - vmmc-supply = <&vdd_3v3>; - vqmmc-supply = <&vdd_3v3>; - bus-width = <8>; - non-removable; - no-1-8-v; -}; - -&sata { - status = "okay"; -}; - -&usb2_phy1 { - phy-supply = <&ldousb_reg>; -}; - -&usb2_phy2 { - phy-supply = <&ldousb_reg>; -}; - -&usb1 { - dr_mode = "host"; -}; - -&omap_dwc3_2 { - extcon = <&extcon_usb2>; -}; - -&usb2 { - /* - * Stand alone usage is peripheral only. - * However, with some resistor modifications - * this port can be used via expansion connectors - * as "host" or "dual-role". If so, provide - * the necessary dr_mode override in the expansion - * board's DT. - */ - dr_mode = "peripheral"; -}; - -&cpu_trips { - cpu_alert1: cpu_alert1 { - temperature = <50000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "active"; - }; -}; - -&cpu_cooling_maps { - map1 { - trip = <&cpu_alert1>; - cooling-device = <&gpio_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; -}; - -&thermal_zones { - board_thermal: board_thermal { - polling-delay-passive = <1250>; /* milliseconds */ - polling-delay = <1500>; /* milliseconds */ - - /* sensor ID */ - thermal-sensors = <&tmp102 0>; - - board_trips: trips { - board_alert0: board_alert { - temperature = <40000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "active"; - }; - - board_crit: board_crit { - temperature = <105000>; /* millicelsius */ - hysteresis = <0>; /* millicelsius */ - type = "critical"; - }; - }; - - board_cooling_maps: cooling-maps { - map0 { - trip = <&board_alert0>; - cooling-device = - <&gpio_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; -}; - -&dss { - status = "ok"; - - vdda_video-supply = <&ldoln_reg>; -}; - -&hdmi { - status = "ok"; - vdda-supply = <&ldo4_reg>; - - port { - hdmi_out: endpoint { - remote-endpoint = <&tpd12s015_in>; - }; - }; -}; - -&pcie1_rc { - status = "ok"; - gpios = <&gpio2 8 GPIO_ACTIVE_LOW>; -}; - -&pcie1_ep { - gpios = <&gpio2 8 GPIO_ACTIVE_LOW>; -}; - -&mcasp3 { - #sound-dai-cells = <0>; - assigned-clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>; - assigned-clock-parents = <&sys_clkin2>; - status = "okay"; - - op-mode = <0>; /* MCASP_IIS_MODE */ - tdm-slots = <2>; - /* 4 serializers */ - serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ - 1 2 0 0 - >; - tx-num-evt = <32>; - rx-num-evt = <32>; -}; - -&mailbox5 { - status = "okay"; - mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { - status = "okay"; - }; - mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { - status = "okay"; - }; -}; - -&mailbox6 { - status = "okay"; - mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { - status = "okay"; - }; - mbox_dsp2_ipc3x: mbox_dsp2_ipc3x { - status = "okay"; - }; -}; diff --git a/sys/gnu/dts/arm/am57xx-beagle-x15-revb1.dts b/sys/gnu/dts/arm/am57xx-beagle-x15-revb1.dts deleted file mode 100644 index 7b113b52c3f..00000000000 --- a/sys/gnu/dts/arm/am57xx-beagle-x15-revb1.dts +++ /dev/null @@ -1,36 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/ - */ - -#include "am57xx-beagle-x15-common.dtsi" - -/ { - model = "TI AM5728 BeagleBoard-X15 rev B1"; -}; - -&tpd12s015 { - gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>, /* gpio7_10, CT CP HPD */ - <&gpio2 30 GPIO_ACTIVE_HIGH>, /* gpio2_30, LS OE */ - <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */ -}; - -&mmc1 { - pinctrl-names = "default", "hs"; - pinctrl-0 = <&mmc1_pins_default>; - pinctrl-1 = <&mmc1_pins_hs>; - vmmc-supply = <&vdd_3v3>; - vqmmc-supply = <&ldo1_reg>; -}; - -&mmc2 { - pinctrl-names = "default", "hs", "ddr_1_8v"; - pinctrl-0 = <&mmc2_pins_default>; - pinctrl-1 = <&mmc2_pins_hs>; - pinctrl-2 = <&mmc2_pins_ddr_3_3v_rev11 &mmc2_iodelay_ddr_3_3v_rev11_conf>; -}; - -/* errata i880 "Ethernet RGMII2 Limited to 10/100 Mbps" */ -&phy1 { - max-speed = <100>; -}; diff --git a/sys/gnu/dts/arm/am57xx-beagle-x15-revc.dts b/sys/gnu/dts/arm/am57xx-beagle-x15-revc.dts deleted file mode 100644 index 30c500b15b2..00000000000 --- a/sys/gnu/dts/arm/am57xx-beagle-x15-revc.dts +++ /dev/null @@ -1,31 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014-2017 Texas Instruments Incorporated - http://www.ti.com/ - */ - -#include "am57xx-beagle-x15-common.dtsi" - -/ { - model = "TI AM5728 BeagleBoard-X15 rev C"; -}; - -&tpd12s015 { - gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>, /* gpio7_10, CT CP HPD */ - <&gpio2 30 GPIO_ACTIVE_HIGH>, /* gpio2_30, LS OE */ - <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */ -}; - -&mmc1 { - pinctrl-names = "default", "hs"; - pinctrl-0 = <&mmc1_pins_default>; - pinctrl-1 = <&mmc1_pins_hs>; - vmmc-supply = <&vdd_3v3>; - vqmmc-supply = <&ldo1_reg>; -}; - -&mmc2 { - pinctrl-names = "default", "hs", "ddr_1_8v"; - pinctrl-0 = <&mmc2_pins_default>; - pinctrl-1 = <&mmc2_pins_hs>; - pinctrl-2 = <&mmc2_pins_ddr_rev20>; -}; diff --git a/sys/gnu/dts/arm/am57xx-beagle-x15.dts b/sys/gnu/dts/arm/am57xx-beagle-x15.dts deleted file mode 100644 index a5c24ed4d12..00000000000 --- a/sys/gnu/dts/arm/am57xx-beagle-x15.dts +++ /dev/null @@ -1,38 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/ - */ - -#include "am57xx-beagle-x15-common.dtsi" - -/ { - /* NOTE: This describes the "original" pre-production A2 revision */ - model = "TI AM5728 BeagleBoard-X15"; -}; - -&tpd12s015 { - gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>, /* gpio7_10, CT CP HPD */ - <&gpio6 28 GPIO_ACTIVE_HIGH>, /* gpio6_28, LS OE */ - <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */ -}; - -&mmc1 { - pinctrl-names = "default", "hs"; - pinctrl-0 = <&mmc1_pins_default>; - pinctrl-1 = <&mmc1_pins_hs>; - - vmmc-supply = <&ldo1_reg>; - no-1-8-v; -}; - -&mmc2 { - pinctrl-names = "default", "hs", "ddr_3_3v"; - pinctrl-0 = <&mmc2_pins_default>; - pinctrl-1 = <&mmc2_pins_hs>; - pinctrl-2 = <&mmc2_pins_ddr_3_3v_rev11 &mmc2_iodelay_ddr_3_3v_rev11_conf>; -}; - -/* errata i880 "Ethernet RGMII2 Limited to 10/100 Mbps" */ -&phy1 { - max-speed = <100>; -}; diff --git a/sys/gnu/dts/arm/am57xx-cl-som-am57x.dts b/sys/gnu/dts/arm/am57xx-cl-som-am57x.dts deleted file mode 100644 index 34ca761aede..00000000000 --- a/sys/gnu/dts/arm/am57xx-cl-som-am57x.dts +++ /dev/null @@ -1,622 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Support for CompuLab CL-SOM-AM57x System-on-Module - * - * Copyright (C) 2015 CompuLab Ltd. - http://www.compulab.co.il/ - * Author: Dmitry Lifshitz - */ - -/dts-v1/; - -#include -#include -#include "am5728.dtsi" - -/ { - model = "CompuLab CL-SOM-AM57x"; - compatible = "compulab,cl-som-am57x", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7"; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x80000000 0x0 0x20000000>; /* 512 MB - minimal configuration */ - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&leds_pins_default>; - - led0 { - label = "cl-som-am57x:green"; - gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - }; - - vdd_3v3: fixedregulator-vdd_3v3 { - compatible = "regulator-fixed"; - regulator-name = "vdd_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ads7846reg: fixedregulator-ads7846-reg { - compatible = "regulator-fixed"; - regulator-name = "ads7846-reg"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - sound0: sound0 { - compatible = "simple-audio-card"; - simple-audio-card,name = "CL-SOM-AM57x-Sound-Card"; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&dailink0_master>; - simple-audio-card,frame-master = <&dailink0_master>; - simple-audio-card,widgets = - "Headphone", "Headphone Jack", - "Microphone", "Microphone Jack", - "Line", "Line Jack"; - simple-audio-card,routing = - "Headphone Jack", "RHPOUT", - "Headphone Jack", "LHPOUT", - "LLINEIN", "Line Jack", - "MICIN", "Mic Bias", - "Mic Bias", "Microphone Jack"; - - dailink0_master: simple-audio-card,cpu { - sound-dai = <&mcasp3>; - }; - - simple-audio-card,codec { - sound-dai = <&wm8731>; - system-clock-frequency = <12000000>; - }; - }; -}; - -&dra7_pmx_core { - leds_pins_default: leds_pins_default { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x347c, PIN_OUTPUT | MUX_MODE14) /* gpmc_a15.gpio2_5 */ - >; - }; - - i2c1_pins_default: i2c1_pins_default { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3800, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda.sda */ - DRA7XX_CORE_IOPAD(0x3804, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl.scl */ - >; - }; - - i2c3_pins_default: i2c3_pins_default { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x36a4, PIN_INPUT| MUX_MODE10) /* mcasp1_aclkx.i2c3_sda */ - DRA7XX_CORE_IOPAD(0x36a8, PIN_INPUT| MUX_MODE10) /* mcasp1_fsx.i2c3_scl */ - >; - }; - - i2c4_pins_default: i2c4_pins_default { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x36ac, PIN_INPUT| MUX_MODE10) /* mcasp1_acl.i2c4_sda */ - DRA7XX_CORE_IOPAD(0x36b0, PIN_INPUT| MUX_MODE10) /* mcasp1_fsr.i2c4_scl */ - >; - }; - - tps659038_pins_default: tps659038_pins_default { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3818, PIN_INPUT_PULLUP | MUX_MODE14) /* wakeup0.gpio1_0 */ - >; - }; - - mmc2_pins_default: mmc2_pins_default { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ - DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ - DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ - DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ - DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ - DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ - DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ - DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ - DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ - DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ - >; - }; - - qspi1_pins: pinmux_qspi1_pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3474, PIN_INPUT | MUX_MODE1) /* gpmc_a13.qspi1_rtclk */ - DRA7XX_CORE_IOPAD(0x3480, PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d0 */ - DRA7XX_CORE_IOPAD(0x3484, PIN_INPUT | MUX_MODE1) /* gpmc_a17.qspi1_d1 */ - DRA7XX_CORE_IOPAD(0x3488, PIN_INPUT | MUX_MODE1) /* qpmc_a18.qspi1_sclk */ - DRA7XX_CORE_IOPAD(0x34b8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs2.qspi1_cs0 */ - DRA7XX_CORE_IOPAD(0x34bc, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs3.qspi1_cs1 */ - >; - }; - - cpsw_pins_default: cpsw_pins_default { - pinctrl-single,pins = < - /* Slave at addr 0x0 */ - DRA7XX_CORE_IOPAD(0x3650, PIN_OUTPUT | MUX_MODE0) /* rgmii0_tclk */ - DRA7XX_CORE_IOPAD(0x3654, PIN_OUTPUT | MUX_MODE0) /* rgmii0_tctl */ - DRA7XX_CORE_IOPAD(0x3658, PIN_OUTPUT | MUX_MODE0) /* rgmii0_td3 */ - DRA7XX_CORE_IOPAD(0x365c, PIN_OUTPUT | MUX_MODE0) /* rgmii0_td2 */ - DRA7XX_CORE_IOPAD(0x3660, PIN_OUTPUT | MUX_MODE0) /* rgmii0_td1 */ - DRA7XX_CORE_IOPAD(0x3664, PIN_OUTPUT | MUX_MODE0) /* rgmii0_td0 */ - DRA7XX_CORE_IOPAD(0x3668, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rgmii0_rclk */ - DRA7XX_CORE_IOPAD(0x366c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rgmii0_rctl */ - DRA7XX_CORE_IOPAD(0x3670, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rgmii0_rd3 */ - DRA7XX_CORE_IOPAD(0x3674, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rgmii0_rd2 */ - DRA7XX_CORE_IOPAD(0x3678, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rgmii0_rd1 */ - DRA7XX_CORE_IOPAD(0x367c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rgmii0_rd0 */ - - /* Slave at addr 0x1 */ - DRA7XX_CORE_IOPAD(0x3598, PIN_OUTPUT | MUX_MODE3) /* vin2a_d12.rgmii1_tclk */ - DRA7XX_CORE_IOPAD(0x359c, PIN_OUTPUT | MUX_MODE3) /* vin2a_d13.rgmii1_tctl */ - DRA7XX_CORE_IOPAD(0x35a0, PIN_OUTPUT | MUX_MODE3) /* vin2a_d14.rgmii1_td3 */ - DRA7XX_CORE_IOPAD(0x35a4, PIN_OUTPUT | MUX_MODE3) /* vin2a_d15.rgmii1_td2 */ - DRA7XX_CORE_IOPAD(0x35a8, PIN_OUTPUT | MUX_MODE3) /* vin2a_d16.rgmii1_td1 */ - DRA7XX_CORE_IOPAD(0x35ac, PIN_OUTPUT | MUX_MODE3) /* vin2a_d17.rgmii1_td0 */ - DRA7XX_CORE_IOPAD(0x35b0, PIN_INPUT_PULLDOWN | MUX_MODE3) /* vin2a_d18.rgmii1_rclk */ - DRA7XX_CORE_IOPAD(0x35b4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* vin2a_d19.rgmii1_rctl */ - DRA7XX_CORE_IOPAD(0x35b8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */ - DRA7XX_CORE_IOPAD(0x35bc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */ - DRA7XX_CORE_IOPAD(0x35c0, PIN_INPUT_PULLDOWN | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */ - DRA7XX_CORE_IOPAD(0x35c4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */ - >; - }; - - cpsw_pins_sleep: cpsw_pins_sleep { - pinctrl-single,pins = < - /* Slave 1 */ - DRA7XX_CORE_IOPAD(0x3650, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x3654, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x3658, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x365c, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x3660, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x3664, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x3668, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x366c, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x3670, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x3674, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x3678, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x367c, PIN_INPUT | MUX_MODE15) - - /* Slave 2 */ - DRA7XX_CORE_IOPAD(0x3598, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x359c, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35a0, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35a4, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35a8, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35ac, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35b0, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35b4, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35b8, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35bc, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35c0, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35c4, PIN_INPUT | MUX_MODE15) - >; - }; - - davinci_mdio_pins_default: davinci_mdio_pins_default { - pinctrl-single,pins = < - /* MDIO */ - DRA7XX_CORE_IOPAD(0x3590, PIN_OUTPUT_PULLUP | MUX_MODE3)/* vin2a_d10.mdio_mclk */ - DRA7XX_CORE_IOPAD(0x3594, PIN_INPUT_PULLUP | MUX_MODE3) /* vin2a_d11.mdio_d */ - >; - }; - - davinci_mdio_pins_sleep: davinci_mdio_pins_sleep { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3590, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x3594, PIN_INPUT | MUX_MODE15) - >; - }; - - ads7846_pins: pinmux_ads7846_pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3464, PIN_INPUT_PULLDOWN | MUX_MODE14) /* gpmc_a9.gpio1_31 */ - >; - }; - - mcasp3_pins_default: mcasp3_pins_default { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3724, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_aclkx.mcasp3_aclkx */ - DRA7XX_CORE_IOPAD(0x3728, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_fsx.mcasp3_fsx */ - DRA7XX_CORE_IOPAD(0x372c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr0.mcasp3_axr0 */ - DRA7XX_CORE_IOPAD(0x3730, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr1.mcasp3_axr1 */ - >; - }; - - mcasp3_pins_sleep: mcasp3_pins_sleep { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3724, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x3728, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x372c, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x3730, PIN_INPUT | MUX_MODE15) - >; - }; -}; - -&i2c1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_default>; - clock-frequency = <400000>; -}; - -&i2c3 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_pins_default>; - clock-frequency = <400000>; -}; - -&i2c4 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_pins_default>; - clock-frequency = <400000>; - - tps659038: tps659038@58 { - compatible = "ti,tps659038"; - reg = <0x58>; - interrupt-parent = <&gpio1>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - - pinctrl-names = "default"; - pinctrl-0 = <&tps659038_pins_default>; - - #interrupt-cells = <2>; - interrupt-controller; - - ti,system-power-controller; - - tps659038_pmic { - compatible = "ti,tps659038-pmic"; - - regulators { - smps12_reg: smps12 { - /* VDD_MPU */ - regulator-name = "smps12"; - regulator-min-microvolt = < 850000>; - regulator-max-microvolt = <1250000>; - regulator-always-on; - regulator-boot-on; - }; - - smps3_reg: smps3 { - /* VDD_DDR */ - regulator-name = "smps3"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - }; - - smps45_reg: smps45 { - /* VDD_DSPEVE */ - regulator-name = "smps45"; - regulator-min-microvolt = < 850000>; - regulator-max-microvolt = <1250000>; - regulator-always-on; - regulator-boot-on; - }; - - smps6_reg: smps6 { - /* VDD_GPU */ - regulator-name = "smps6"; - regulator-min-microvolt = < 850000>; - regulator-max-microvolt = <1250000>; - regulator-always-on; - regulator-boot-on; - }; - - smps7_reg: smps7 { - /* VDD_CORE */ - regulator-name = "smps7"; - regulator-min-microvolt = < 850000>; - regulator-max-microvolt = <1160000>; - regulator-always-on; - regulator-boot-on; - }; - - smps8_reg: smps8 { - /* VDD_IVA */ - regulator-name = "smps8"; - regulator-min-microvolt = < 850000>; - regulator-max-microvolt = <1250000>; - regulator-always-on; - regulator-boot-on; - }; - - smps9_reg: smps9 { - /* PMIC_3V3 */ - regulator-name = "smps9"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - - ldo1_reg: ldo1 { - /* VDD_SD / VDDSHV8 */ - regulator-name = "ldo1"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo2_reg: ldo2 { - /* VDD_1V8 */ - regulator-name = "ldo2"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo3_reg: ldo3 { - /* VDDA_1V8_PHYA - supplies VDDA_SATA, VDDA_USB1/2/3 */ - regulator-name = "ldo3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo4_reg: ldo4 { - /* VDDA_1V8_PHYB - supplies VDDA_HDMI, VDDA_PCIE/0/1 */ - regulator-name = "ldo4"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo9_reg: ldo9 { - /* VDD_RTC */ - regulator-name = "ldo9"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - regulator-always-on; - regulator-boot-on; - }; - - ldoln_reg: ldoln { - /* VDDA_1V8_PLL */ - regulator-name = "ldoln"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldousb_reg: ldousb { - /* VDDA_3V_USB: VDDA_USBHS33 */ - regulator-name = "ldousb"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - /* regen1 not used */ - }; - }; - - tps659038_pwr_button: tps659038_pwr_button { - compatible = "ti,palmas-pwrbutton"; - interrupt-parent = <&tps659038>; - interrupts = <1 IRQ_TYPE_EDGE_FALLING>; - wakeup-source; - ti,palmas-long-press-seconds = <12>; - }; - - tps659038_gpio: tps659038_gpio { - compatible = "ti,palmas-gpio"; - gpio-controller; - #gpio-cells = <2>; - }; - }; - - rtc0: rtc@56 { - compatible = "emmicro,em3027"; - reg = <0x56>; - }; - - eeprom_module: atmel@50 { - compatible = "atmel,24c08"; - reg = <0x50>; - pagesize = <16>; - }; - - wm8731: wm8731@1a { - #sound-dai-cells = <0>; - compatible = "wlf,wm8731"; - reg = <0x1a>; - status = "okay"; - }; -}; - -&cpu0 { - cpu0-supply = <&smps12_reg>; - voltage-tolerance = <1>; -}; - -&sata { - status = "okay"; -}; - -&mailbox5 { - status = "okay"; - mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { - status = "okay"; - }; - mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { - status = "okay"; - }; -}; - -&mailbox6 { - status = "okay"; - mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { - status = "okay"; - }; - mbox_dsp2_ipc3x: mbox_dsp2_ipc3x { - status = "okay"; - }; -}; - -&mmc2 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins_default>; - - vmmc-supply = <&vdd_3v3>; - bus-width = <8>; - ti,non-removable; - cap-mmc-dual-data-rate; -}; - -&qspi { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&qspi1_pins>; - - spi-max-frequency = <48000000>; - - spi_flash: spi_flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "spansion,m25p80", "jedec,spi-nor"; - reg = <0>; /* CS0 */ - spi-max-frequency = <48000000>; - - partition@0 { - label = "uboot"; - reg = <0x0 0xc0000>; - }; - - partition@c0000 { - label = "uboot environment"; - reg = <0xc0000 0x40000>; - }; - - partition@100000 { - label = "reserved"; - reg = <0x100000 0x0>; - }; - }; - - /* touch controller */ - touchscreen@1 { - pinctrl-names = "default"; - pinctrl-0 = <&ads7846_pins>; - - compatible = "ti,ads7846"; - vcc-supply = <&ads7846reg>; - - reg = <1>; /* CS1 */ - spi-max-frequency = <1500000>; - - interrupt-parent = <&gpio1>; - interrupts = <31 0>; - pendown-gpio = <&gpio1 31 0>; - - - ti,x-min = /bits/ 16 <0x0>; - ti,x-max = /bits/ 16 <0x0fff>; - ti,y-min = /bits/ 16 <0x0>; - ti,y-max = /bits/ 16 <0x0fff>; - - ti,x-plate-ohms = /bits/ 16 <180>; - ti,pressure-max = /bits/ 16 <255>; - - ti,debounce-max = /bits/ 16 <30>; - ti,debounce-tol = /bits/ 16 <10>; - ti,debounce-rep = /bits/ 16 <1>; - - wakeup-source; - }; -}; - -&mac { - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&cpsw_pins_default>; - pinctrl-1 = <&cpsw_pins_sleep>; - dual_emac; -}; - -&cpsw_emac0 { - phy-handle = <ðphy0>; - phy-mode = "rgmii-txid"; - dual_emac_res_vlan = <0>; -}; - -&cpsw_emac1 { - phy-handle = <ðphy1>; - phy-mode = "rgmii-txid"; - dual_emac_res_vlan = <1>; -}; - -&davinci_mdio { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&davinci_mdio_pins_default>; - pinctrl-1 = <&davinci_mdio_pins_sleep>; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; - - ethphy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&usb2_phy1 { - phy-supply = <&ldousb_reg>; -}; - -&usb2_phy2 { - phy-supply = <&ldousb_reg>; -}; - -&usb1 { - dr_mode = "host"; -}; - -&usb2 { - dr_mode = "host"; -}; - -&mcasp3 { - #sound-dai-cells = <0>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&mcasp3_pins_default>; - pinctrl-1 = <&mcasp3_pins_sleep>; - status = "okay"; - - op-mode = <0>; /* MCASP_IIS_MODE */ - tdm-slots = <2>; - /* 4 serializers */ - serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ - 1 2 0 0 - >; -}; - -&gpio3 { - status = "okay"; - ti,no-reset-on-init; -}; - -&gpio2 { - status = "okay"; - ti,no-reset-on-init; -}; diff --git a/sys/gnu/dts/arm/am57xx-commercial-grade.dtsi b/sys/gnu/dts/arm/am57xx-commercial-grade.dtsi deleted file mode 100644 index 3eed6e09c88..00000000000 --- a/sys/gnu/dts/arm/am57xx-commercial-grade.dtsi +++ /dev/null @@ -1,24 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -&cpu_alert0 { - temperature = <80000>; /* milliCelsius */ -}; - -&cpu_crit { - temperature = <90000>; /* milliCelsius */ -}; - -&gpu_crit { - temperature = <90000>; /* milliCelsius */ -}; - -&core_crit { - temperature = <90000>; /* milliCelsius */ -}; - -&dspeve_crit { - temperature = <90000>; /* milliCelsius */ -}; - -&iva_crit { - temperature = <90000>; /* milliCelsius */ -}; diff --git a/sys/gnu/dts/arm/am57xx-idk-common.dtsi b/sys/gnu/dts/arm/am57xx-idk-common.dtsi deleted file mode 100644 index 423855a2a2d..00000000000 --- a/sys/gnu/dts/arm/am57xx-idk-common.dtsi +++ /dev/null @@ -1,492 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/ - */ - -#include "am57xx-industrial-grade.dtsi" - -/ { - aliases { - rtc0 = &tps659038_rtc; - rtc1 = &rtc; - }; - - chosen { - stdout-path = &uart3; - }; - - vmain: fixedregulator-vmain { - compatible = "regulator-fixed"; - regulator-name = "VMAIN"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - v3_3d: fixedregulator-v3_3d { - compatible = "regulator-fixed"; - regulator-name = "V3_3D"; - vin-supply = <&smps9_reg>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - vtt_fixed: fixedregulator-vtt { - /* TPS51200 */ - compatible = "regulator-fixed"; - regulator-name = "vtt_fixed"; - vin-supply = <&v3_3d>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - leds-iio { - status = "disabled"; - compatible = "gpio-leds"; - led-out0 { - label = "out0"; - gpios = <&tpic2810 0 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-out1 { - label = "out1"; - gpios = <&tpic2810 1 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-out2 { - label = "out2"; - gpios = <&tpic2810 2 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-out3 { - label = "out3"; - gpios = <&tpic2810 3 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-out4 { - label = "out4"; - gpios = <&tpic2810 4 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-out5 { - label = "out5"; - gpios = <&tpic2810 5 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-out6 { - label = "out6"; - gpios = <&tpic2810 6 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-out7 { - label = "out7"; - gpios = <&tpic2810 7 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; -}; - -&dra7_pmx_core { - dcan1_pins_default: dcan1_pins_default { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */ - DRA7XX_CORE_IOPAD(0x37d4, PIN_INPUT_PULLUP | MUX_MODE0) /* dcan1_rx */ - >; - }; - - dcan1_pins_sleep: dcan1_pins_sleep { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x37d0, MUX_MODE15 | PULL_UP) /* dcan1_tx.off */ - DRA7XX_CORE_IOPAD(0x37d4, MUX_MODE15 | PULL_UP) /* dcan1_rx.off */ - >; - }; -}; - -&i2c1 { - status = "okay"; - clock-frequency = <400000>; - - tps659038: tps659038@58 { - compatible = "ti,tps659038"; - reg = <0x58>; - interrupts-extended = <&gpio6 16 IRQ_TYPE_LEVEL_HIGH - &dra7_pmx_core 0x418>; - #interrupt-cells = <2>; - interrupt-controller; - ti,system-power-controller; - ti,palmas-override-powerhold; - - tps659038_pmic { - compatible = "ti,tps659038-pmic"; - - smps12-in-supply = <&vmain>; - smps3-in-supply = <&vmain>; - smps45-in-supply = <&vmain>; - smps6-in-supply = <&vmain>; - smps7-in-supply = <&vmain>; - smps8-in-supply = <&vmain>; - smps9-in-supply = <&vmain>; - ldo1-in-supply = <&vmain>; - ldo2-in-supply = <&vmain>; - ldo3-in-supply = <&vmain>; - ldo4-in-supply = <&vmain>; - ldo9-in-supply = <&vmain>; - ldoln-in-supply = <&vmain>; - ldousb-in-supply = <&vmain>; - ldortc-in-supply = <&vmain>; - - regulators { - smps12_reg: smps12 { - /* VDD_MPU */ - regulator-name = "smps12"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1250000>; - regulator-always-on; - regulator-boot-on; - }; - - smps3_reg: smps3 { - /* VDD_DDR EMIF1 EMIF2 */ - regulator-name = "smps3"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - - smps45_reg: smps45 { - /* VDD_DSPEVE on AM572 */ - /* VDD_IVA + VDD_DSP on AM571 */ - regulator-name = "smps45"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1250000>; - regulator-always-on; - regulator-boot-on; - }; - - smps6_reg: smps6 { - /* VDD_GPU */ - regulator-name = "smps6"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1250000>; - regulator-always-on; - regulator-boot-on; - }; - - smps7_reg: smps7 { - /* VDD_CORE */ - regulator-name = "smps7"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1150000>; - regulator-always-on; - regulator-boot-on; - }; - - smps8_reg: smps8 { - /* 5728 - VDD_IVAHD */ - /* 5718 - N.C. test point */ - regulator-name = "smps8"; - }; - - smps9_reg: smps9 { - /* VDD_3_3D */ - regulator-name = "smps9"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo1_reg: ldo1 { - /* VDDSHV8 - VSDMMC */ - /* NOTE: on rev 1.3a, data supply */ - regulator-name = "ldo1"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo2_reg: ldo2 { - /* VDDSH18V */ - regulator-name = "ldo2"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo3_reg: ldo3 { - /* R1.3a 572x V1_8PHY_LDO3: USB, SATA */ - regulator-name = "ldo3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo4_reg: ldo4 { - /* R1.3a 572x V1_8PHY_LDO4: PCIE, HDMI*/ - regulator-name = "ldo4"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - /* LDO5-8 unused */ - - ldo9_reg: ldo9 { - /* VDD_RTC */ - regulator-name = "ldo9"; - regulator-min-microvolt = <840000>; - regulator-max-microvolt = <1160000>; - regulator-always-on; - regulator-boot-on; - }; - - ldoln_reg: ldoln { - /* VDDA_1V8_PLL */ - regulator-name = "ldoln"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldousb_reg: ldousb { - /* VDDA_3V_USB: VDDA_USBHS33 */ - regulator-name = "ldousb"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - ldortc_reg: ldortc { - /* VDDA_RTC */ - regulator-name = "ldortc"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - regen1: regen1 { - /* VDD_3V3_ON */ - regulator-name = "regen1"; - regulator-boot-on; - regulator-always-on; - }; - - regen2: regen2 { - /* Needed for PMIC internal resource */ - regulator-name = "regen2"; - regulator-boot-on; - regulator-always-on; - }; - }; - }; - - tps659038_rtc: tps659038_rtc { - compatible = "ti,palmas-rtc"; - interrupt-parent = <&tps659038>; - interrupts = <8 IRQ_TYPE_EDGE_FALLING>; - wakeup-source; - }; - - tps659038_pwr_button: tps659038_pwr_button { - compatible = "ti,palmas-pwrbutton"; - interrupt-parent = <&tps659038>; - interrupts = <1 IRQ_TYPE_EDGE_FALLING>; - wakeup-source; - ti,palmas-long-press-seconds = <12>; - }; - - tps659038_gpio: tps659038_gpio { - compatible = "ti,palmas-gpio"; - gpio-controller; - #gpio-cells = <2>; - }; - - extcon_usb2: tps659038_usb { - compatible = "ti,palmas-usb-vid"; - ti,enable-vbus-detection; - ti,enable-id-detection; - /* ID & VBUS GPIOs provided in board dts */ - }; - }; - - tpic2810: tpic2810@60 { - compatible = "ti,tpic2810"; - reg = <0x60>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -&mcspi3 { - status = "okay"; - ti,pindir-d0-out-d1-in; - - sn65hvs882: sn65hvs882@0 { - compatible = "pisosr-gpio"; - gpio-controller; - #gpio-cells = <2>; - - reg = <0>; - spi-max-frequency = <1000000>; - spi-cpol; - }; -}; - -&uart3 { - status = "okay"; - interrupts-extended = <&crossbar_mpu GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH - &dra7_pmx_core 0x248>; -}; - -&rtc { - status = "okay"; - ext-clk-src; -}; - -&mac { - status = "okay"; - dual_emac; -}; - -&cpsw_emac0 { - phy-handle = <ðphy0>; - phy-mode = "rgmii"; - dual_emac_res_vlan = <1>; -}; - -&cpsw_emac1 { - phy-handle = <ðphy1>; - phy-mode = "rgmii"; - dual_emac_res_vlan = <2>; -}; - -&davinci_mdio { - ethphy0: ethernet-phy@0 { - reg = <0>; - }; - - ethphy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&usb2_phy1 { - phy-supply = <&ldousb_reg>; -}; - -&usb2_phy2 { - phy-supply = <&ldousb_reg>; -}; - -&usb1 { - dr_mode = "host"; -}; - -&omap_dwc3_2 { - extcon = <&extcon_usb2>; -}; - -&usb2 { - extcon = <&extcon_usb2>; - dr_mode = "otg"; -}; - -&mmc1 { - status = "okay"; - vmmc-supply = <&v3_3d>; - vqmmc-supply = <&ldo1_reg>; - bus-width = <4>; - cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; /* gpio 219 */ - no-1-8-v; -}; - -&mmc2 { - status = "okay"; - vmmc-supply = <&v3_3d>; - vqmmc-supply = <&v3_3d>; - bus-width = <8>; - non-removable; - max-frequency = <96000000>; - no-1-8-v; -}; - -&dcan1 { - status = "okay"; - pinctrl-names = "default", "sleep", "active"; - pinctrl-0 = <&dcan1_pins_sleep>; - pinctrl-1 = <&dcan1_pins_sleep>; - pinctrl-2 = <&dcan1_pins_default>; -}; - -&qspi { - status = "okay"; - - spi-max-frequency = <76800000>; - m25p80@0 { - compatible = "s25fl256s1", "jedec,spi-nor"; - spi-max-frequency = <76800000>; - reg = <0>; - spi-tx-bus-width = <1>; - spi-rx-bus-width = <4>; - #address-cells = <1>; - #size-cells = <1>; - - /* MTD partition table. - * The ROM checks the first four physical blocks - * for a valid file to boot and the flash here is - * 64KiB block size. - */ - partition@0 { - label = "QSPI.SPL"; - reg = <0x00000000 0x000040000>; - }; - partition@1 { - label = "QSPI.u-boot"; - reg = <0x00040000 0x00100000>; - }; - partition@2 { - label = "QSPI.u-boot-spl-os"; - reg = <0x00140000 0x00080000>; - }; - partition@3 { - label = "QSPI.u-boot-env"; - reg = <0x001c0000 0x00010000>; - }; - partition@4 { - label = "QSPI.u-boot-env.backup1"; - reg = <0x001d0000 0x0010000>; - }; - partition@5 { - label = "QSPI.kernel"; - reg = <0x001e0000 0x0800000>; - }; - partition@6 { - label = "QSPI.file-system"; - reg = <0x009e0000 0x01620000>; - }; - }; -}; - -&cpu0 { - vdd-supply = <&smps12_reg>; -}; diff --git a/sys/gnu/dts/arm/am57xx-industrial-grade.dtsi b/sys/gnu/dts/arm/am57xx-industrial-grade.dtsi deleted file mode 100644 index 422f953fc8d..00000000000 --- a/sys/gnu/dts/arm/am57xx-industrial-grade.dtsi +++ /dev/null @@ -1,24 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -&cpu_alert0 { - temperature = <90000>; /* milliCelsius */ -}; - -&cpu_crit { - temperature = <105000>; /* milliCelsius */ -}; - -&gpu_crit { - temperature = <105000>; /* milliCelsius */ -}; - -&core_crit { - temperature = <105000>; /* milliCelsius */ -}; - -&dspeve_crit { - temperature = <105000>; /* milliCelsius */ -}; - -&iva_crit { - temperature = <105000>; /* milliCelsius */ -}; diff --git a/sys/gnu/dts/arm/am57xx-sbc-am57x.dts b/sys/gnu/dts/arm/am57xx-sbc-am57x.dts deleted file mode 100644 index ce5bf1d92ea..00000000000 --- a/sys/gnu/dts/arm/am57xx-sbc-am57x.dts +++ /dev/null @@ -1,176 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Support for CompuLab SBC-AM57x single board computer - * - * Copyright (C) 2015 CompuLab Ltd. - http://www.compulab.co.il/ - * Author: Dmitry Lifshitz - */ - -#include "am57xx-cl-som-am57x.dts" -#include "compulab-sb-som.dtsi" - -/ { - model = "CompuLab CL-SOM-AM57x on SB-SOM-AM57x"; - compatible = "compulab,sbc-am57x", "compulab,cl-som-am57x", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7"; - - aliases { - display0 = &lcd0; - display1 = &hdmi; - }; -}; - -&dra7_pmx_core { - uart3_pins_default: uart3_pins_default { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3648, PIN_INPUT_SLEW | MUX_MODE0) /* uart3_rxd */ - DRA7XX_CORE_IOPAD(0x364c, PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */ - >; - }; - - mmc1_pins_default: mmc1_pins_default { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ - DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ - DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ - DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ - DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ - DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ - DRA7XX_CORE_IOPAD(0x376c, PIN_INPUT | MUX_MODE14) /* mmc1_sdcd.gpio6_27 */ - DRA7XX_CORE_IOPAD(0x377c, PIN_INPUT | MUX_MODE14) /* mmc1_sdwp.gpio6_28 */ - >; - }; - - usb1_pins: pinmux_usb1_pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3680, PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */ - >; - }; - - i2c5_pins_default: i2c5_pins_default { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x36b4, PIN_INPUT| MUX_MODE10) /* mcasp1_axr0.i2c5_sda */ - DRA7XX_CORE_IOPAD(0x36b8, PIN_INPUT| MUX_MODE10) /* mcasp1_axr1.i2c5_scl */ - >; - }; - - lcd_pins_default: lcd_pins_default { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3564, PIN_OUTPUT | MUX_MODE14) /* vin2a_vsync0.gpio4_0 */ - >; - }; - - hdmi_pins: pinmux_hdmi_pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3808, PIN_INPUT | MUX_MODE1) /* i2c2_sda.hdmi1_ddc_scl */ - DRA7XX_CORE_IOPAD(0x380c, PIN_INPUT | MUX_MODE1) /* i2c2_scl.hdmi1_ddc_sda */ - >; - }; - - hdmi_conn_pins: pinmux_hdmi_conn_pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x37b8, PIN_INPUT | MUX_MODE14) /* spi1_cs2.gpio7_12 */ - >; - }; -}; - -&uart3 { - status = "okay"; - interrupts-extended = <&crossbar_mpu GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, - <&dra7_pmx_core 0x3f8>; - - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins_default>; -}; - -&mmc1 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins_default>; - - vmmc-supply = <&ldo1_reg>; - bus-width = <4>; - cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio6 28 GPIO_ACTIVE_HIGH>; -}; - -&usb1 { - pinctrl-names = "default"; - pinctrl-0 = <&usb1_pins>; -}; - -&i2c5 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c5_pins_default>; - clock-frequency = <400000>; - - eeprom_base: atmel@54 { - compatible = "atmel,24c08"; - reg = <0x54>; - pagesize = <16>; - }; - - pca9555: pca9555@20 { - compatible = "nxp,pca9555"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -&dss { - status = "ok"; - - vdda_video-supply = <&ldoln_reg>; - - port { - dpi_lcd_out: endpoint { - remote-endpoint = <&lcd_in>; - data-lines = <24>; - }; - }; -}; - -&lcd0 { - pinctrl-names = "default"; - pinctrl-0 = <&lcd_pins_default>; - - enable-gpios = <&pca9555 14 GPIO_ACTIVE_HIGH - &gpio4 0 GPIO_ACTIVE_HIGH>; - - port { - lcd_in: endpoint { - remote-endpoint = <&dpi_lcd_out>; - data-lines = <24>; - }; - }; -}; - -&hdmi { - status = "ok"; - vdda-supply = <&ldo4_reg>; - - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_pins>; - - port { - hdmi_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - lanes = <1 0 3 2 5 4 7 6>; - }; - }; -}; - -&hdmi_conn { - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_conn_pins>; - - hpd-gpios = <&gpio7 12 GPIO_ACTIVE_HIGH>; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_out>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/animeo_ip.dts b/sys/gnu/dts/arm/animeo_ip.dts deleted file mode 100644 index c36d28c295d..00000000000 --- a/sys/gnu/dts/arm/animeo_ip.dts +++ /dev/null @@ -1,196 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * animeo_ip.dts - Device Tree file for Somfy Animeo IP Boards - * - * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD - */ - -/dts-v1/; -#include "at91sam9260.dtsi" - -/ { - model = "Somfy Animeo IP"; - compatible = "somfy,animeo-ip", "atmel,at91sam9260", "atmel,at91sam9"; - - aliases { - serial0 = &usart1; - serial1 = &usart2; - serial2 = &usart0; - serial3 = &dbgu; - serial4 = &usart3; - serial5 = &uart0; - serial6 = &uart1; - }; - - chosen { - stdout-path = &usart2; - }; - - memory { - reg = <0x20000000 0x4000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <18432000>; - }; - }; - - ahb { - apb { - tcb0: timer@fffa0000 { - timer@0 { - compatible = "atmel,tcb-timer"; - reg = <0>, <1>; - }; - - timer@2 { - compatible = "atmel,tcb-timer"; - reg = <2>; - }; - }; - - usart0: serial@fffb0000 { - pinctrl-0 = <&pinctrl_usart0 &pinctrl_usart0_rts>; - linux,rs485-enabled-at-boot-time; - status = "okay"; - }; - - usart1: serial@fffb4000 { - pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts>; - linux,rs485-enabled-at-boot-time; - status = "okay"; - }; - - usart2: serial@fffb8000 { - pinctrl-0 = <&pinctrl_usart2>; - status = "okay"; - }; - - macb0: ethernet@fffc4000 { - pinctrl-0 = <&pinctrl_macb_rmii &pinctrl_macb_rmii_mii>; - phy-mode = "mii"; - status = "okay"; - }; - - mmc0: mmc@fffa8000 { - pinctrl-0 = <&pinctrl_mmc0_clk - &pinctrl_mmc0_slot1_cmd_dat0 - &pinctrl_mmc0_slot1_dat1_3>; - status = "okay"; - - slot@1 { - reg = <1>; - bus-width = <4>; - }; - }; - - watchdog@fffffd40 { - status = "okay"; - }; - }; - - ebi: ebi@10000000 { - status = "okay"; - - nand_controller: nand-controller { - status = "okay"; - pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>; - pinctrl-names = "default"; - - nand@3 { - reg = <0x3 0x0 0x800000>; - rb-gpios = <&pioC 13 GPIO_ACTIVE_HIGH>; - cs-gpios = <&pioC 14 GPIO_ACTIVE_HIGH>; - nand-bus-width = <8>; - nand-ecc-mode = "soft"; - nand-on-flash-bbt; - label = "atmel_nand"; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - barebox@0 { - label = "barebox"; - reg = <0x0 0x58000>; - }; - - u_boot_env@58000 { - label = "u_boot_env"; - reg = <0x58000 0x8000>; - }; - - ubi@60000 { - label = "ubi"; - reg = <0x60000 0x1FA0000>; - }; - }; - }; - }; - }; - - usb0: ohci@500000 { - num-ports = <2>; - atmel,vbus-gpio = <&pioB 15 GPIO_ACTIVE_LOW>; - status = "okay"; - }; - }; - - leds { - compatible = "gpio-leds"; - - power_green { - label = "power_green"; - gpios = <&pioC 17 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - - power_red { - label = "power_red"; - gpios = <&pioA 2 GPIO_ACTIVE_HIGH>; - }; - - tx_green { - label = "tx_green"; - gpios = <&pioC 19 GPIO_ACTIVE_HIGH>; - }; - - tx_red { - label = "tx_red"; - gpios = <&pioC 18 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - keyswitch_in { - label = "keyswitch_in"; - gpios = <&pioB 1 GPIO_ACTIVE_HIGH>; - linux,code = <28>; - wakeup-source; - }; - - error_in { - label = "error_in"; - gpios = <&pioB 2 GPIO_ACTIVE_HIGH>; - linux,code = <29>; - wakeup-source; - }; - - btn { - label = "btn"; - gpios = <&pioC 23 GPIO_ACTIVE_HIGH>; - linux,code = <31>; - wakeup-source; - }; - }; -}; diff --git a/sys/gnu/dts/arm/arm-realview-eb-11mp-bbrevd-ctrevb.dts b/sys/gnu/dts/arm/arm-realview-eb-11mp-bbrevd-ctrevb.dts deleted file mode 100644 index e18769df9fd..00000000000 --- a/sys/gnu/dts/arm/arm-realview-eb-11mp-bbrevd-ctrevb.dts +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Copyright 2016 Linaro Ltd - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include "arm-realview-eb-11mp-ctrevb.dts" -#include "arm-realview-eb-bbrevd.dtsi" - -/* - * This is the EB with the new Revision D baseboard with SMSC9118 ethernet and - * the Rev B core tile. - */ -/ { - model = "ARM RealView Emulation Baseboard Rev D with ARM11MPCore Core Tile Rev B"; -}; diff --git a/sys/gnu/dts/arm/arm-realview-eb-11mp-bbrevd.dts b/sys/gnu/dts/arm/arm-realview-eb-11mp-bbrevd.dts deleted file mode 100644 index 26b1c69e9f4..00000000000 --- a/sys/gnu/dts/arm/arm-realview-eb-11mp-bbrevd.dts +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Copyright 2016 Linaro Ltd - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include "arm-realview-eb-11mp.dts" -#include "arm-realview-eb-bbrevd.dtsi" - -/ { - model = "ARM RealView Emulation Baseboard Rev D with ARM11MPCore Rev C Core Tile"; -}; diff --git a/sys/gnu/dts/arm/arm-realview-eb-11mp-ctrevb.dts b/sys/gnu/dts/arm/arm-realview-eb-11mp-ctrevb.dts deleted file mode 100644 index e68527b0d55..00000000000 --- a/sys/gnu/dts/arm/arm-realview-eb-11mp-ctrevb.dts +++ /dev/null @@ -1,93 +0,0 @@ -/* - * Copyright 2016 Linaro Ltd - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include "arm-realview-eb-11mp.dts" - -/ { - model = "ARM RealView Emulation Baseboard with ARM11MPCore Rev B"; -}; - -/* - * The revision B has a distinctly different layout of the syscon, so - * append a specific compatible-string. - */ -&syscon { - compatible = "arm,realview-eb11mp-revb-syscon", "arm,realview-eb-syscon", "syscon", "simple-mfd"; -}; - -&intc { - reg = <0x10101000 0x1000>, - <0x10100100 0x100>; -}; - -&L2 { - reg = <0x10102000 0x1000>; -}; - -&scu { - reg = <0x10100000 0x100>; -}; - -&twd_timer { - reg = <0x10100600 0x20>; -}; - -&twd_wdog { - reg = <0x10100620 0x20>; -}; - -/* - * On revision B, we cannot reach the secondary interrupt - * controller, as a result, some peripherals that are dependent - * on their IRQ cannot be reached, so disable them. - */ -&intc_second { - status = "disabled"; -}; - -&gpio0 { - status = "disabled"; -}; - -&gpio1 { - status = "disabled"; -}; - -&gpio2 { - status = "disabled"; -}; - -&serial2 { - status = "disabled"; -}; - -&serial3 { - status = "disabled"; -}; - -&ssp { - status = "disabled"; -}; - -&wdog { - status = "disabled"; -}; diff --git a/sys/gnu/dts/arm/arm-realview-eb-11mp-revb.dts b/sys/gnu/dts/arm/arm-realview-eb-11mp-revb.dts deleted file mode 100644 index e68527b0d55..00000000000 --- a/sys/gnu/dts/arm/arm-realview-eb-11mp-revb.dts +++ /dev/null @@ -1,93 +0,0 @@ -/* - * Copyright 2016 Linaro Ltd - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include "arm-realview-eb-11mp.dts" - -/ { - model = "ARM RealView Emulation Baseboard with ARM11MPCore Rev B"; -}; - -/* - * The revision B has a distinctly different layout of the syscon, so - * append a specific compatible-string. - */ -&syscon { - compatible = "arm,realview-eb11mp-revb-syscon", "arm,realview-eb-syscon", "syscon", "simple-mfd"; -}; - -&intc { - reg = <0x10101000 0x1000>, - <0x10100100 0x100>; -}; - -&L2 { - reg = <0x10102000 0x1000>; -}; - -&scu { - reg = <0x10100000 0x100>; -}; - -&twd_timer { - reg = <0x10100600 0x20>; -}; - -&twd_wdog { - reg = <0x10100620 0x20>; -}; - -/* - * On revision B, we cannot reach the secondary interrupt - * controller, as a result, some peripherals that are dependent - * on their IRQ cannot be reached, so disable them. - */ -&intc_second { - status = "disabled"; -}; - -&gpio0 { - status = "disabled"; -}; - -&gpio1 { - status = "disabled"; -}; - -&gpio2 { - status = "disabled"; -}; - -&serial2 { - status = "disabled"; -}; - -&serial3 { - status = "disabled"; -}; - -&ssp { - status = "disabled"; -}; - -&wdog { - status = "disabled"; -}; diff --git a/sys/gnu/dts/arm/arm-realview-eb-11mp.dts b/sys/gnu/dts/arm/arm-realview-eb-11mp.dts deleted file mode 100644 index aac1edd4b22..00000000000 --- a/sys/gnu/dts/arm/arm-realview-eb-11mp.dts +++ /dev/null @@ -1,74 +0,0 @@ -/* - * Copyright 2016 Linaro Ltd - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -/dts-v1/; -#include "arm-realview-eb-mp.dtsi" - -/ { - model = "ARM RealView Emulation Baseboard with ARM11MPCore Rev C Core Tile"; - arm,hbi = <0x146>; - - /* - * This is the ARM11 MPCore tile (HBI-0146) used with the RealView EB. - * Reference: ARM DUI 0318F - * - * To run this machine with QEMU, specify the following: - * qemu-system-arm -M realview-eb-mpcore -smp cpus=4 - */ - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "arm,realview-smp"; - - MP11_0: cpu@0 { - device_type = "cpu"; - compatible = "arm,arm11mpcore"; - reg = <0>; - next-level-cache = <&L2>; - }; - - MP11_1: cpu@1 { - device_type = "cpu"; - compatible = "arm,arm11mpcore"; - reg = <1>; - next-level-cache = <&L2>; - }; - - MP11_2: cpu@2 { - device_type = "cpu"; - compatible = "arm,arm11mpcore"; - reg = <2>; - next-level-cache = <&L2>; - }; - - MP11_3: cpu@3 { - device_type = "cpu"; - compatible = "arm,arm11mpcore"; - reg = <3>; - next-level-cache = <&L2>; - }; - }; -}; - -&pmu { - interrupt-affinity = <&MP11_0>, <&MP11_1>, <&MP11_2>, <&MP11_3>; -}; diff --git a/sys/gnu/dts/arm/arm-realview-eb-a9mp-bbrevd.dts b/sys/gnu/dts/arm/arm-realview-eb-a9mp-bbrevd.dts deleted file mode 100644 index 42efac7496e..00000000000 --- a/sys/gnu/dts/arm/arm-realview-eb-a9mp-bbrevd.dts +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Copyright 2016 Linaro Ltd - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include "arm-realview-eb-a9mp.dts" -#include "arm-realview-eb-bbrevd.dtsi" - -/ { - model = "ARM RealView EB Baseboard Rev D Cortex A9 MPCore"; -}; diff --git a/sys/gnu/dts/arm/arm-realview-eb-a9mp.dts b/sys/gnu/dts/arm/arm-realview-eb-a9mp.dts deleted file mode 100644 index 967684b3636..00000000000 --- a/sys/gnu/dts/arm/arm-realview-eb-a9mp.dts +++ /dev/null @@ -1,70 +0,0 @@ -/* - * Copyright 2016 Linaro Ltd - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -/dts-v1/; -#include "arm-realview-eb-mp.dtsi" - -/ { - model = "ARM RealView EB Cortex A9 MPCore"; - - /* - * This is the Cortex A9 MPCore tile used with the - * RealView EB. - */ - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "arm,realview-smp"; - - A9_0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - next-level-cache = <&L2>; - }; - - A9_1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <1>; - next-level-cache = <&L2>; - }; - - A9_2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <2>; - next-level-cache = <&L2>; - }; - - A9_3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <3>; - next-level-cache = <&L2>; - }; - }; -}; - -&pmu { - interrupt-affinity = <&A9_0>, <&A9_1>, <&A9_2>, <&A9_3>; -}; diff --git a/sys/gnu/dts/arm/arm-realview-eb-bbrevd.dts b/sys/gnu/dts/arm/arm-realview-eb-bbrevd.dts deleted file mode 100644 index f533c8b49d9..00000000000 --- a/sys/gnu/dts/arm/arm-realview-eb-bbrevd.dts +++ /dev/null @@ -1,29 +0,0 @@ -/* - * Copyright 2016 Linaro Ltd - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -/* This derives from the Realview Baseboard, and overlays the new ethernet */ -#include "arm-realview-eb.dts" -#include "arm-realview-eb-bbrevd.dtsi" - -/ { - model = "ARM RealView Emulation Baseboard Rev D"; -}; diff --git a/sys/gnu/dts/arm/arm-realview-eb-bbrevd.dtsi b/sys/gnu/dts/arm/arm-realview-eb-bbrevd.dtsi deleted file mode 100644 index a79e1d1d30a..00000000000 --- a/sys/gnu/dts/arm/arm-realview-eb-bbrevd.dtsi +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright 2016 Linaro Ltd - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -/ { - /* Introduce a fixed regulator for the new ethernet controller */ - veth: fixedregulator@0 { - compatible = "regulator-fixed"; - regulator-name = "veth"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; -}; - -/* - * The revision D has a different ethernet controller that the elder boards: - * the older board uses LAN91C111 but the new one uses LAN9118. - */ -ðernet { - compatible = "smsc,lan9118", "smsc,lan9115"; - phy-mode = "mii"; - smsc,irq-active-high; - smsc,irq-push-pull; - vdd33a-supply = <&veth>; - vddvario-supply = <&veth>; -}; diff --git a/sys/gnu/dts/arm/arm-realview-eb-mp.dtsi b/sys/gnu/dts/arm/arm-realview-eb-mp.dtsi deleted file mode 100644 index 29b636fce23..00000000000 --- a/sys/gnu/dts/arm/arm-realview-eb-mp.dtsi +++ /dev/null @@ -1,220 +0,0 @@ -/* - * Copyright 2016 Linaro Ltd - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include -#include -#include "arm-realview-eb.dtsi" - -/* - * This is the common include file for all MPCore variants of the - * Evaluation Baseboard, i.e. ARM11MPCore, ARM11MPCore Revision B - * and Cortex-A9 MPCore. - */ -/ { - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "arm,realview-eb-soc", "simple-bus"; - regmap = <&syscon>; - ranges; - - /* Primary interrupt controller in the test chip */ - intc: interrupt-controller@1f000100 { - compatible = "arm,eb11mp-gic"; - #interrupt-cells = <3>; - #address-cells = <1>; - interrupt-controller; - reg = <0x1f001000 0x1000>, - <0x1f000100 0x100>; - }; - - /* Secondary interrupt controller on the FPGA */ - intc_second: interrupt-controller@10040000 { - compatible = "arm,pl390"; - #interrupt-cells = <3>; - #address-cells = <1>; - interrupt-controller; - reg = <0x10041000 0x1000>, - <0x10040000 0x100>; - interrupt-parent = <&intc>; - interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; - }; - - L2: l2-cache { - compatible = "arm,l220-cache"; - reg = <0x1f002000 0x1000>; - interrupt-parent = <&intc>; - interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>, - <0 30 IRQ_TYPE_LEVEL_HIGH>, - <0 31 IRQ_TYPE_LEVEL_HIGH>; - cache-unified; - cache-level = <2>; - /* - * Override default cache size, sets and - * associativity as these may be erroneously set - * up by boot loader(s), probably for safety - * since th outer sync operation can cause the - * cache to hang unless disabled. - */ - cache-size = <1048576>; // 1MB - cache-sets = <4096>; - cache-line-size = <32>; - arm,shared-override; - arm,parity-enable; - arm,outer-sync-disable; - }; - - scu: scu@1f000000 { - compatible = "arm,arm11mp-scu"; - reg = <0x1f000000 0x100>; - }; - - twd_timer: timer@1f000600 { - compatible = "arm,arm11mp-twd-timer"; - reg = <0x1f000600 0x20>; - interrupt-parent = <&intc>; - interrupts = <1 13 0xf04>; - }; - - twd_wdog: watchdog@1f000620 { - compatible = "arm,arm11mp-twd-wdt"; - reg = <0x1f000620 0x20>; - interrupt-parent = <&intc>; - interrupts = <1 14 0xf04>; - }; - - /* PMU with one IRQ line per core */ - pmu: pmu@0 { - compatible = "arm,arm11mpcore-pmu"; - interrupt-parent = <&intc>; - interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>, - <0 18 IRQ_TYPE_LEVEL_HIGH>, - <0 19 IRQ_TYPE_LEVEL_HIGH>, - <0 20 IRQ_TYPE_LEVEL_HIGH>; - }; - }; -}; - -/* - * This adapts all the peripherals to the interrupt routing - * to the GIC on the core tile. - */ - -ðernet { - interrupt-parent = <&intc>; - interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; -}; - -&usb { - interrupt-parent = <&intc>; - interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>; -}; - -&aaci { - interrupt-parent = <&intc>; - interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>; -}; - -&mmc { - interrupt-parent = <&intc>; - interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>, - <0 15 IRQ_TYPE_LEVEL_HIGH>; -}; - -&kmi0 { - interrupt-parent = <&intc>; - interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; -}; - -&kmi1 { - interrupt-parent = <&intc>; - interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; -}; - -&serial0 { - interrupt-parent = <&intc>; - interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>; -}; - -&serial1 { - interrupt-parent = <&intc>; - interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>; -}; - -&timer01 { - interrupt-parent = <&intc>; - interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH>; -}; - -&timer23 { - interrupt-parent = <&intc>; - interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>; -}; - -&rtc { - interrupt-parent = <&intc>; - interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; -}; - -/* - * On revision A, these peripherals does not have their IRQ lines - * routed to the core tile, but they can be reached on the secondary - * GIC. - */ -&gpio0 { - interrupt-parent = <&intc_second>; - interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; -}; - -&gpio1 { - interrupt-parent = <&intc_second>; - interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; -}; - -&gpio2 { - interrupt-parent = <&intc_second>; - interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; -}; - -&serial2 { - interrupt-parent = <&intc_second>; - interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; - status = "okay"; -}; - -&serial3 { - interrupt-parent = <&intc_second>; - interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>; - status = "okay"; -}; - -&ssp { - interrupt-parent = <&intc_second>; - interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; - status = "okay"; -}; - -&wdog { - interrupt-parent = <&intc_second>; - interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/arm-realview-eb.dts b/sys/gnu/dts/arm/arm-realview-eb.dts deleted file mode 100644 index 15431077f00..00000000000 --- a/sys/gnu/dts/arm/arm-realview-eb.dts +++ /dev/null @@ -1,166 +0,0 @@ -/* - * Copyright 2016 Linaro Ltd - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -/dts-v1/; -#include -#include -#include "arm-realview-eb.dtsi" - -/ { - model = "ARM RealView Emulation Baseboard"; - compatible = "arm,realview-eb"; - arm,hbi = <0x140>; - - /* - * This is the core tile with the CPU and GIC etc for the - * ARM926EJ-S, ARM1136, ARM1176 that does not have L2 cache - * or PMU. - * - * To run this machine with QEMU, specify the following: - * qemu-system-arm -M realview-eb - * Unless specified, QEMU will emulate an ARM926EJ-S core tile. - * Switches -cpu arm1136 or -cpu arm1176 emulates the other - * core tiles. - */ - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "arm,realview-eb-soc", "simple-bus"; - regmap = <&syscon>; - ranges; - - intc: interrupt-controller@10040000 { - compatible = "arm,pl390"; - #interrupt-cells = <3>; - #address-cells = <1>; - interrupt-controller; - reg = <0x10041000 0x1000>, - <0x10040000 0x100>; - }; - }; -}; - -/* - * This adapts all the peripherals to the interrupt routing - * to the GIC on the core tile. - */ - -ðernet { - interrupt-parent = <&intc>; - interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>; -}; - -&usb { - interrupt-parent = <&intc>; - interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>; -}; - -&aaci { - interrupt-parent = <&intc>; - interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>; -}; - -&mmc { - interrupt-parent = <&intc>; - interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>, - <0 18 IRQ_TYPE_LEVEL_HIGH>; -}; - -&kmi0 { - interrupt-parent = <&intc>; - interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>; -}; - -&kmi1 { - interrupt-parent = <&intc>; - interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>; -}; - -&charlcd { - interrupt-parent = <&intc>; - interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>; -}; - -&serial0 { - interrupt-parent = <&intc>; - interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>; -}; - -&serial1 { - interrupt-parent = <&intc>; - interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>; -}; - -&serial2 { - interrupt-parent = <&intc>; - interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; -}; - -&serial3 { - interrupt-parent = <&intc>; - interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>; -}; - -&ssp { - interrupt-parent = <&intc>; - interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; -}; - -&wdog { - interrupt-parent = <&intc>; - interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>; -}; - -&timer01 { - interrupt-parent = <&intc>; - interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>; -}; - -&timer23 { - interrupt-parent = <&intc>; - interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>; -}; - -&gpio0 { - interrupt-parent = <&intc>; - interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; -}; - -&gpio1 { - interrupt-parent = <&intc>; - interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; -}; - -&gpio2 { - interrupt-parent = <&intc>; - interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; -}; - -&rtc { - interrupt-parent = <&intc>; - interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; -}; - -&clcd { - interrupt-parent = <&intc>; - interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; -}; diff --git a/sys/gnu/dts/arm/arm-realview-eb.dtsi b/sys/gnu/dts/arm/arm-realview-eb.dtsi deleted file mode 100644 index fe0207b8805..00000000000 --- a/sys/gnu/dts/arm/arm-realview-eb.dtsi +++ /dev/null @@ -1,468 +0,0 @@ -/* - * Copyright 2016 Linaro Ltd - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - compatible = "arm,realview-eb"; - - chosen { }; - - aliases { - serial0 = &serial0; - serial1 = &serial1; - serial2 = &serial2; - serial3 = &serial3; - i2c0 = &i2c; - }; - - memory { - device_type = "memory"; - /* 128 MiB memory @ 0x0 */ - reg = <0x00000000 0x08000000>; - }; - - /* The voltage to the MMC card is hardwired at 3.3V */ - vmmc: fixedregulator@0 { - compatible = "regulator-fixed"; - regulator-name = "vmmc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; - - xtal24mhz: xtal24mhz@24M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - }; - - timclk: timclk@1M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <24>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - mclk: mclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - kmiclk: kmiclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - sspclk: sspclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - uartclk: uartclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - wdogclk: wdogclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - /* FIXME: this actually hangs off the PLL clocks */ - pclk: pclk@0 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - flash0@40000000 { - /* 2 * 32MiB NOR Flash memory */ - compatible = "arm,versatile-flash", "cfi-flash"; - reg = <0x40000000 0x04000000>; - bank-width = <4>; - partitions { - compatible = "arm,arm-firmware-suite"; - }; - }; - - flash1@44000000 { - /* 2 * 32MiB NOR Flash memory */ - compatible = "arm,versatile-flash", "cfi-flash"; - reg = <0x44000000 0x04000000>; - bank-width = <4>; - partitions { - compatible = "arm,arm-firmware-suite"; - }; - }; - - /* SMSC LAN91C111 ethernet with PHY and EEPROM */ - ethernet: ethernet@4e000000 { - compatible = "smsc,lan91c111"; - reg = <0x4e000000 0x10000>; - /* - * This means the adapter can be accessed with 8, 16 or - * 32 bit reads/writes. - */ - reg-io-width = <7>; - }; - - usb: usb@4f000000 { - compatible = "nxp,usb-isp1761"; - reg = <0x4f000000 0x20000>; - port1-otg; - }; - - bridge { - compatible = "ti,ths8134a", "ti,ths8134"; - #address-cells = <1>; - #size-cells = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - vga_bridge_in: endpoint { - remote-endpoint = <&clcd_pads>; - }; - }; - - port@1 { - reg = <1>; - - vga_bridge_out: endpoint { - remote-endpoint = <&vga_con_in>; - }; - }; - }; - }; - - vga { - compatible = "vga-connector"; - - port { - vga_con_in: endpoint { - remote-endpoint = <&vga_bridge_out>; - }; - }; - }; - - /* These peripherals are inside the FPGA */ - fpga { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges; - - syscon: syscon@10000000 { - compatible = "arm,realview-eb-syscon", "syscon", "simple-mfd"; - reg = <0x10000000 0x1000>; - - led@08.0 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x01>; - label = "versatile:0"; - linux,default-trigger = "heartbeat"; - default-state = "on"; - }; - led@08.1 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x02>; - label = "versatile:1"; - linux,default-trigger = "mmc0"; - default-state = "off"; - }; - led@08.2 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x04>; - label = "versatile:2"; - linux,default-trigger = "cpu0"; - default-state = "off"; - }; - led@08.3 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x08>; - label = "versatile:3"; - default-state = "off"; - }; - led@08.4 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x10>; - label = "versatile:4"; - default-state = "off"; - }; - led@08.5 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x20>; - label = "versatile:5"; - default-state = "off"; - }; - led@08.6 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x40>; - label = "versatile:6"; - default-state = "off"; - }; - led@08.7 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x80>; - label = "versatile:7"; - default-state = "off"; - }; - oscclk0: osc0@0c { - compatible = "arm,syscon-icst307"; - #clock-cells = <0>; - lock-offset = <0x20>; - vco-offset = <0x0C>; - clocks = <&xtal24mhz>; - }; - oscclk1: osc1@10 { - compatible = "arm,syscon-icst307"; - #clock-cells = <0>; - lock-offset = <0x20>; - vco-offset = <0x10>; - clocks = <&xtal24mhz>; - }; - oscclk2: osc2@14 { - compatible = "arm,syscon-icst307"; - #clock-cells = <0>; - lock-offset = <0x20>; - vco-offset = <0x14>; - clocks = <&xtal24mhz>; - }; - oscclk3: osc3@18 { - compatible = "arm,syscon-icst307"; - #clock-cells = <0>; - lock-offset = <0x20>; - vco-offset = <0x18>; - clocks = <&xtal24mhz>; - }; - oscclk4: osc4@1c { - compatible = "arm,syscon-icst307"; - #clock-cells = <0>; - lock-offset = <0x20>; - vco-offset = <0x1c>; - clocks = <&xtal24mhz>; - }; - }; - - i2c: i2c@10002000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "arm,versatile-i2c"; - reg = <0x10002000 0x1000>; - - rtc@68 { - compatible = "dallas,ds1338"; - reg = <0x68>; - }; - }; - - aaci: aaci@10004000 { - compatible = "arm,pl041", "arm,primecell"; - reg = <0x10004000 0x1000>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - mmc: mmcsd@10005000 { - compatible = "arm,pl18x", "arm,primecell"; - reg = <0x10005000 0x1000>; - - /* Due to frequent FIFO overruns, use just 500 kHz */ - max-frequency = <500000>; - bus-width = <4>; - cap-sd-highspeed; - cap-mmc-highspeed; - clocks = <&mclk>, <&pclk>; - clock-names = "mclk", "apb_pclk"; - vmmc-supply = <&vmmc>; - cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; - }; - - kmi0: kmi@10006000 { - compatible = "arm,pl050", "arm,primecell"; - reg = <0x10006000 0x1000>; - clocks = <&kmiclk>, <&pclk>; - clock-names = "KMIREFCLK", "apb_pclk"; - }; - - kmi1: kmi@10007000 { - compatible = "arm,pl050", "arm,primecell"; - reg = <0x10007000 0x1000>; - clocks = <&kmiclk>, <&pclk>; - clock-names = "KMIREFCLK", "apb_pclk"; - }; - - charlcd: fpga_charlcd: charlcd@10008000 { - compatible = "arm,versatile-lcd"; - reg = <0x10008000 0x1000>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - serial0: serial@10009000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x10009000 0x1000>; - clocks = <&uartclk>, <&pclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - serial1: serial@1000a000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x1000a000 0x1000>; - clocks = <&uartclk>, <&pclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - serial2: serial@1000b000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x1000b000 0x1000>; - clocks = <&uartclk>, <&pclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - serial3: serial@1000c000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x1000c000 0x1000>; - clocks = <&uartclk>, <&pclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - ssp: spi@1000d000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x1000d000 0x1000>; - clocks = <&sspclk>, <&pclk>; - clock-names = "SSPCLK", "apb_pclk"; - }; - - wdog: watchdog@10010000 { - compatible = "arm,sp805", "arm,primecell"; - reg = <0x10010000 0x1000>; - clocks = <&wdogclk>, <&pclk>; - clock-names = "wdogclk", "apb_pclk"; - status = "disabled"; - }; - - timer01: timer@10011000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x10011000 0x1000>; - clocks = <&timclk>, <&timclk>, <&pclk>; - clock-names = "timer1", "timer2", "apb_pclk"; - }; - - timer23: timer@10012000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x10012000 0x1000>; - clocks = <&timclk>, <&timclk>, <&pclk>; - clock-names = "timer1", "timer2", "apb_pclk"; - }; - - gpio0: gpio@10013000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x10013000 0x1000>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - gpio1: gpio@10014000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x10014000 0x1000>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - gpio2: gpio@10015000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x10015000 0x1000>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - rtc: rtc@10017000 { - compatible = "arm,pl031", "arm,primecell"; - reg = <0x10017000 0x1000>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - clcd: clcd@10020000 { - compatible = "arm,pl111", "arm,primecell"; - reg = <0x10020000 0x1000>; - interrupt-names = "combined"; - clocks = <&oscclk0>, <&pclk>; - clock-names = "clcdclk", "apb_pclk"; - /* 1024x768 16bpp @65MHz works fine */ - max-memory-bandwidth = <95000000>; - - port { - clcd_pads: endpoint { - remote-endpoint = <&vga_bridge_in>; - arm,pl11x,tft-r0g0b0-pads = <0 8 16>; - }; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/arm-realview-pb1176.dts b/sys/gnu/dts/arm/arm-realview-pb1176.dts deleted file mode 100644 index 2625ce66f8e..00000000000 --- a/sys/gnu/dts/arm/arm-realview-pb1176.dts +++ /dev/null @@ -1,592 +0,0 @@ -/* - * Copyright 2014 Linaro Ltd - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -/dts-v1/; -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - model = "ARM RealView PB1176"; - compatible = "arm,realview-pb1176"; - - chosen { }; - - aliases { - serial0 = &pb1176_serial0; - serial1 = &pb1176_serial1; - serial2 = &pb1176_serial2; - serial3 = &pb1176_serial3; - serial4 = &fpga_serial; - }; - - memory { - device_type = "memory"; - /* 128 MiB memory @ 0x0 */ - reg = <0x00000000 0x08000000>; - }; - - /* The voltage to the MMC card is hardwired at 3.3V */ - vmmc: regulator-vmmc { - compatible = "regulator-fixed"; - regulator-name = "vmmc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; - - veth: regulator-veth { - compatible = "regulator-fixed"; - regulator-name = "veth"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; - - xtal24mhz: xtal24mhz@24M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - }; - - timclk: timclk@1M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <24>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - mclk: mclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - kmiclk: kmiclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - sspclk: sspclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - uartclk: uartclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - /* FIXME: this actually hangs off the PLL clocks */ - pclk: pclk@0 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - flash@30000000 { - compatible = "arm,versatile-flash", "cfi-flash"; - reg = <0x30000000 0x4000000>; - bank-width = <4>; - partitions { - compatible = "arm,arm-firmware-suite"; - }; - }; - - fpga_flash@38000000 { - compatible = "arm,versatile-flash", "cfi-flash"; - reg = <0x38000000 0x800000>; - bank-width = <4>; - partitions { - compatible = "arm,arm-firmware-suite"; - }; - }; - - /* - * The "secure flash" contains things like the boot - * monitor so we don't want people to accidentally - * screw this up. Mark the device tree node disabled - * by default. - */ - secflash@3c000000 { - compatible = "arm,versatile-flash", "cfi-flash"; - reg = <0x3c000000 0x4000000>; - bank-width = <4>; - status = "disabled"; - }; - - /* SMSC 9118 ethernet with PHY and EEPROM */ - ethernet@3a000000 { - compatible = "smsc,lan9118", "smsc,lan9115"; - reg = <0x3a000000 0x10000>; - interrupt-parent = <&intc_fpga1176>; - interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; - phy-mode = "mii"; - reg-io-width = <4>; - smsc,irq-active-high; - smsc,irq-push-pull; - vdd33a-supply = <&veth>; - vddvario-supply = <&veth>; - }; - - usb@3b000000 { - compatible = "nxp,usb-isp1761"; - reg = <0x3b000000 0x20000>; - interrupt-parent = <&intc_fpga1176>; - interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; - port1-otg; - }; - - bridge { - compatible = "ti,ths8134a", "ti,ths8134"; - #address-cells = <1>; - #size-cells = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - vga_bridge_in: endpoint { - remote-endpoint = <&clcd_pads>; - }; - }; - - port@1 { - reg = <1>; - - vga_bridge_out: endpoint { - remote-endpoint = <&vga_con_in>; - }; - }; - }; - }; - - vga { - compatible = "vga-connector"; - - port { - vga_con_in: endpoint { - remote-endpoint = <&vga_bridge_out>; - }; - }; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "arm,realview-pb1176-soc", "simple-bus"; - regmap = <&syscon>; - ranges; - - syscon: syscon@10000000 { - compatible = "arm,realview-pb1176-syscon", "syscon", "simple-mfd"; - reg = <0x10000000 0x1000>; - - led@08.0 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x01>; - label = "versatile:0"; - linux,default-trigger = "heartbeat"; - default-state = "on"; - }; - led@08.1 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x02>; - label = "versatile:1"; - linux,default-trigger = "mmc0"; - default-state = "off"; - }; - led@08.2 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x04>; - label = "versatile:2"; - linux,default-trigger = "cpu0"; - default-state = "off"; - }; - led@08.3 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x08>; - label = "versatile:3"; - default-state = "off"; - }; - led@08.4 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x10>; - label = "versatile:4"; - default-state = "off"; - }; - led@08.5 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x20>; - label = "versatile:5"; - default-state = "off"; - }; - led@08.6 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x40>; - label = "versatile:6"; - default-state = "off"; - }; - led@08.7 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x80>; - label = "versatile:7"; - default-state = "off"; - }; - oscclk0: osc0@0c { - compatible = "arm,syscon-icst307"; - #clock-cells = <0>; - lock-offset = <0x20>; - vco-offset = <0x0C>; - clocks = <&xtal24mhz>; - }; - oscclk1: osc1@10 { - compatible = "arm,syscon-icst307"; - #clock-cells = <0>; - lock-offset = <0x20>; - vco-offset = <0x10>; - clocks = <&xtal24mhz>; - }; - oscclk2: osc2@14 { - compatible = "arm,syscon-icst307"; - #clock-cells = <0>; - lock-offset = <0x20>; - vco-offset = <0x14>; - clocks = <&xtal24mhz>; - }; - oscclk3: osc3@18 { - compatible = "arm,syscon-icst307"; - #clock-cells = <0>; - lock-offset = <0x20>; - vco-offset = <0x18>; - clocks = <&xtal24mhz>; - }; - oscclk4: osc4@1c { - compatible = "arm,syscon-icst307"; - #clock-cells = <0>; - lock-offset = <0x20>; - vco-offset = <0x1c>; - clocks = <&xtal24mhz>; - }; - }; - - /* Primary DevChip GIC synthesized with the CPU */ - intc_dc1176: interrupt-controller@10120000 { - compatible = "arm,arm1176jzf-devchip-gic", "arm,arm11mp-gic"; - #interrupt-cells = <3>; - #address-cells = <1>; - interrupt-controller; - reg = <0x10121000 0x1000>, - <0x10120000 0x100>; - }; - - L2: l2-cache { - compatible = "arm,l220-cache"; - reg = <0x10110000 0x1000>; - interrupt-parent = <&intc_dc1176>; - interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>; - cache-unified; - cache-level = <2>; - /* - * Override default cache size, sets and - * associativity as these may be erroneously set - * up by boot loader(s). - */ - arm,override-auxreg; - cache-size = <131072>; // 128kB - cache-sets = <512>; - cache-line-size = <32>; - }; - - pmu { - compatible = "arm,arm1176-pmu"; - interrupt-parent = <&intc_dc1176>; - interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; - }; - - timer01: timer@10104000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x10104000 0x1000>; - interrupt-parent = <&intc_dc1176>; - interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>, <0 9 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&timclk>, <&timclk>, <&pclk>; - clock-names = "timer1", "timer2", "apb_pclk"; - }; - - timer23: timer@10105000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x10105000 0x1000>; - interrupt-parent = <&intc_dc1176>; - interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; - arm,sp804-has-irq = <1>; - clocks = <&timclk>, <&timclk>, <&pclk>; - clock-names = "timer1", "timer2", "apb_pclk"; - }; - - pb1176_rtc: rtc@10108000 { - compatible = "arm,pl031", "arm,primecell"; - reg = <0x10108000 0x1000>; - interrupt-parent = <&intc_dc1176>; - interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - pb1176_gpio0: gpio@1010a000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x1010a000 0x1000>; - gpio-controller; - interrupt-parent = <&intc_dc1176>; - interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - pb1176_ssp: spi@1010b000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x1010b000 0x1000>; - interrupt-parent = <&intc_dc1176>; - interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&sspclk>, <&pclk>; - clock-names = "SSPCLK", "apb_pclk"; - }; - - pb1176_serial0: serial@1010c000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x1010c000 0x1000>; - interrupt-parent = <&intc_dc1176>; - interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&uartclk>, <&pclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - pb1176_serial1: serial@1010d000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x1010d000 0x1000>; - interrupt-parent = <&intc_dc1176>; - interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&uartclk>, <&pclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - pb1176_serial2: serial@1010e000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x1010e000 0x1000>; - interrupt-parent = <&intc_dc1176>; - interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&uartclk>, <&pclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - pb1176_serial3: serial@1010f000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x1010f000 0x1000>; - interrupt-parent = <&intc_dc1176>; - interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&uartclk>, <&pclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - /* Direct-mapped development chip ROM */ - pb1176_rom@10200000 { - compatible = "direct-mapped"; - reg = <0x10200000 0x4000>; - bank-width = <1>; - }; - - clcd@10112000 { - compatible = "arm,pl111", "arm,primecell"; - reg = <0x10112000 0x1000>; - interrupt-parent = <&intc_dc1176>; - interrupt-names = "combined"; - interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&oscclk0>, <&pclk>; - clock-names = "clcdclk", "apb_pclk"; - /* 1024x768 16bpp @65MHz works fine */ - max-memory-bandwidth = <95000000>; - - port { - clcd_pads: endpoint { - remote-endpoint = <&vga_bridge_in>; - arm,pl11x,tft-r0g0b0-pads = <0 8 16>; - }; - }; - }; - }; - - /* These peripherals are inside the FPGA rather than the DevChip */ - fpga { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges; - - i2c0: i2c@10002000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "arm,versatile-i2c"; - reg = <0x10002000 0x1000>; - - rtc@68 { - compatible = "dallas,ds1338"; - reg = <0x68>; - }; - }; - - fpga_aaci: aaci@10004000 { - compatible = "arm,pl041", "arm,primecell"; - reg = <0x10004000 0x1000>; - interrupt-parent = <&intc_fpga1176>; - interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - fpga_mci: mmcsd@10005000 { - compatible = "arm,pl18x", "arm,primecell"; - reg = <0x10005000 0x1000>; - interrupt-parent = <&intc_fpga1176>; - interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH>, - <0 2 IRQ_TYPE_LEVEL_HIGH>; - /* Due to frequent FIFO overruns, use just 500 kHz */ - max-frequency = <500000>; - bus-width = <4>; - cap-sd-highspeed; - cap-mmc-highspeed; - clocks = <&mclk>, <&pclk>; - clock-names = "mclk", "apb_pclk"; - vmmc-supply = <&vmmc>; - cd-gpios = <&fpga_gpio1 0 GPIO_ACTIVE_LOW>; - wp-gpios = <&fpga_gpio1 1 GPIO_ACTIVE_HIGH>; - }; - - fpga_kmi0: kmi@10006000 { - compatible = "arm,pl050", "arm,primecell"; - reg = <0x10006000 0x1000>; - interrupt-parent = <&intc_fpga1176>; - interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&kmiclk>, <&pclk>; - clock-names = "KMIREFCLK", "apb_pclk"; - }; - - fpga_kmi1: kmi@10007000 { - compatible = "arm,pl050", "arm,primecell"; - reg = <0x10007000 0x1000>; - interrupt-parent = <&intc_fpga1176>; - interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&kmiclk>, <&pclk>; - clock-names = "KMIREFCLK", "apb_pclk"; - }; - - fpga_charlcd: charlcd@10008000 { - compatible = "arm,versatile-lcd"; - reg = <0x10008000 0x1000>; - interrupt-parent = <&intc_fpga1176>; - interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - fpga_serial: serial@10009000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x10009000 0x1000>; - interrupt-parent = <&intc_fpga1176>; - interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&uartclk>, <&pclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - /* This GIC on the board is cascaded off the DevChip GIC */ - intc_fpga1176: interrupt-controller@10040000 { - compatible = "arm,arm1176jzf-devchip-gic", "arm,arm11mp-gic"; - #interrupt-cells = <3>; - #address-cells = <1>; - interrupt-controller; - reg = <0x10041000 0x1000>, - <0x10040000 0x100>; - interrupt-parent = <&intc_dc1176>; - interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; - }; - - fpga_gpio0: gpio@10014000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x10014000 0x1000>; - gpio-controller; - interrupt-parent = <&intc_fpga1176>; - interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - fpga_gpio1: gpio@10015000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x10015000 0x1000>; - gpio-controller; - interrupt-parent = <&intc_fpga1176>; - interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - fpga_rtc: rtc@10017000 { - compatible = "arm,pl031", "arm,primecell"; - reg = <0x10017000 0x1000>; - interrupt-parent = <&intc_fpga1176>; - interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - }; -}; diff --git a/sys/gnu/dts/arm/arm-realview-pb11mp.dts b/sys/gnu/dts/arm/arm-realview-pb11mp.dts deleted file mode 100644 index c69cf7ddbe6..00000000000 --- a/sys/gnu/dts/arm/arm-realview-pb11mp.dts +++ /dev/null @@ -1,718 +0,0 @@ -/* - * Copyright 2015 Linaro Ltd - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -/dts-v1/; -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - model = "ARM RealView PB11MPcore"; - compatible = "arm,realview-pb11mp"; - - chosen { }; - - aliases { - serial0 = &pb11mp_serial0; - serial1 = &pb11mp_serial1; - serial2 = &pb11mp_serial2; - serial3 = &pb11mp_serial3; - }; - - memory { - device_type = "memory"; - /* - * The PB11MPCore has 512 MiB memory @ 0x70000000 - * and the first 256 are also remapped @ 0x00000000 - */ - reg = <0x70000000 0x20000000>; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "arm,realview-smp"; - - MP11_0: cpu@0 { - device_type = "cpu"; - compatible = "arm,arm11mpcore"; - reg = <0>; - next-level-cache = <&L2>; - }; - - MP11_1: cpu@1 { - device_type = "cpu"; - compatible = "arm,arm11mpcore"; - reg = <1>; - next-level-cache = <&L2>; - }; - - MP11_2: cpu@2 { - device_type = "cpu"; - compatible = "arm,arm11mpcore"; - reg = <2>; - next-level-cache = <&L2>; - }; - - MP11_3: cpu@3 { - device_type = "cpu"; - compatible = "arm,arm11mpcore"; - reg = <3>; - next-level-cache = <&L2>; - }; - }; - - /* Primary TestChip GIC synthesized with the CPU */ - intc_tc11mp: interrupt-controller@1f000100 { - compatible = "arm,tc11mp-gic"; - #interrupt-cells = <3>; - #address-cells = <1>; - interrupt-controller; - reg = <0x1f001000 0x1000>, - <0x1f000100 0x100>; - }; - - L2: l2-cache { - compatible = "arm,l220-cache"; - reg = <0x1f002000 0x1000>; - interrupt-parent = <&intc_tc11mp>; - interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>, - <0 30 IRQ_TYPE_LEVEL_HIGH>, - <0 31 IRQ_TYPE_LEVEL_HIGH>; - cache-unified; - cache-level = <2>; - /* - * Override default cache size, sets and - * associativity as these may be erroneously set - * up by boot loader(s), probably for safety - * since th outer sync operation can cause the - * cache to hang unless disabled. - */ - cache-size = <1048576>; // 1MB - cache-sets = <4096>; - cache-line-size = <32>; - arm,shared-override; - arm,parity-enable; - arm,outer-sync-disable; - }; - - scu@1f000000 { - compatible = "arm,arm11mp-scu"; - reg = <0x1f000000 0x100>; - }; - - timer@1f000600 { - compatible = "arm,arm11mp-twd-timer"; - reg = <0x1f000600 0x20>; - interrupt-parent = <&intc_tc11mp>; - interrupts = <1 13 0xf04>; - }; - - watchdog@1f000620 { - compatible = "arm,arm11mp-twd-wdt"; - reg = <0x1f000620 0x20>; - interrupt-parent = <&intc_tc11mp>; - interrupts = <1 14 0xf04>; - }; - - /* PMU with one IRQ line per core */ - pmu { - compatible = "arm,arm11mpcore-pmu"; - interrupt-parent = <&intc_tc11mp>; - interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>, - <0 18 IRQ_TYPE_LEVEL_HIGH>, - <0 19 IRQ_TYPE_LEVEL_HIGH>, - <0 20 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&MP11_0>, <&MP11_1>, <&MP11_2>, <&MP11_3>; - }; - - /* The voltage to the MMC card is hardwired at 3.3V */ - vmmc: regulator-vmmc { - compatible = "regulator-fixed"; - regulator-name = "vmmc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; - - veth: regulator-veth { - compatible = "regulator-fixed"; - regulator-name = "veth"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; - - xtal24mhz: xtal24mhz@24M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - }; - - refclk32khz: refclk32khz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - - timclk: timclk@1M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <24>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - mclk: mclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - kmiclk: kmiclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - sspclk: sspclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - uartclk: uartclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - wdogclk: wdogclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - /* FIXME: this actually hangs off the PLL clocks */ - pclk: pclk@0 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - flash0@40000000 { - /* 2 * 32MiB NOR Flash memory */ - compatible = "arm,versatile-flash", "cfi-flash"; - reg = <0x40000000 0x04000000>; - bank-width = <4>; - partitions { - compatible = "arm,arm-firmware-suite"; - }; - }; - - flash1@44000000 { - // 2 * 32MiB NOR Flash memory - compatible = "arm,versatile-flash", "cfi-flash"; - reg = <0x44000000 0x04000000>; - bank-width = <4>; - partitions { - compatible = "arm,arm-firmware-suite"; - }; - }; - - bridge { - compatible = "ti,ths8134a", "ti,ths8134"; - #address-cells = <1>; - #size-cells = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - vga_bridge_in: endpoint { - remote-endpoint = <&clcd_pads>; - }; - }; - - port@1 { - reg = <1>; - - vga_bridge_out: endpoint { - remote-endpoint = <&vga_con_in>; - }; - }; - }; - }; - - vga { - /* - * This DDC I2C is connected directly to the DVI portions - * of the connector, so it's not really working when the - * monitor is connected to the VGA connector. - */ - compatible = "vga-connector"; - ddc-i2c-bus = <&i2c1>; - - port { - vga_con_in: endpoint { - remote-endpoint = <&vga_bridge_out>; - }; - }; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "arm,realview-pb11mp-soc", "simple-bus"; - regmap = <&pb11mp_syscon>; - ranges; - - pb11mp_syscon: syscon@10000000 { - compatible = "arm,realview-pb11mp-syscon", "syscon", "simple-mfd"; - reg = <0x10000000 0x1000>; - - led@08.0 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x01>; - label = "versatile:0"; - linux,default-trigger = "heartbeat"; - default-state = "on"; - }; - led@08.1 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x02>; - label = "versatile:1"; - linux,default-trigger = "mmc0"; - default-state = "off"; - }; - led@08.2 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x04>; - label = "versatile:2"; - linux,default-trigger = "cpu0"; - default-state = "off"; - }; - led@08.3 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x08>; - label = "versatile:3"; - linux,default-trigger = "cpu1"; - default-state = "off"; - }; - led@08.4 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x10>; - label = "versatile:4"; - linux,default-trigger = "cpu2"; - default-state = "off"; - }; - led@08.5 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x20>; - label = "versatile:5"; - linux,default-trigger = "cpu3"; - default-state = "off"; - }; - led@08.6 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x40>; - label = "versatile:6"; - default-state = "off"; - }; - led@08.7 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x80>; - label = "versatile:7"; - default-state = "off"; - }; - - oscclk0: osc0@0c { - compatible = "arm,syscon-icst307"; - #clock-cells = <0>; - lock-offset = <0x20>; - vco-offset = <0x0C>; - clocks = <&xtal24mhz>; - }; - oscclk1: osc1@10 { - compatible = "arm,syscon-icst307"; - #clock-cells = <0>; - lock-offset = <0x20>; - vco-offset = <0x10>; - clocks = <&xtal24mhz>; - }; - oscclk2: osc2@14 { - compatible = "arm,syscon-icst307"; - #clock-cells = <0>; - lock-offset = <0x20>; - vco-offset = <0x14>; - clocks = <&xtal24mhz>; - }; - oscclk3: osc3@18 { - compatible = "arm,syscon-icst307"; - #clock-cells = <0>; - lock-offset = <0x20>; - vco-offset = <0x18>; - clocks = <&xtal24mhz>; - }; - oscclk4: osc4@1c { - compatible = "arm,syscon-icst307"; - #clock-cells = <0>; - lock-offset = <0x20>; - vco-offset = <0x1c>; - clocks = <&xtal24mhz>; - }; - oscclk5: osc5@d4 { - compatible = "arm,syscon-icst307"; - #clock-cells = <0>; - lock-offset = <0x20>; - vco-offset = <0xd4>; - clocks = <&xtal24mhz>; - }; - oscclk6: osc6@d8 { - compatible = "arm,syscon-icst307"; - #clock-cells = <0>; - lock-offset = <0x20>; - vco-offset = <0xd8>; - clocks = <&xtal24mhz>; - }; - }; - - sp810_syscon: sysctl@10001000 { - compatible = "arm,sp810", "arm,primecell"; - reg = <0x10001000 0x1000>; - clocks = <&refclk32khz>, <&timclk>, <&xtal24mhz>; - clock-names = "refclk", "timclk", "apb_pclk"; - #clock-cells = <1>; - clock-output-names = "timerclk0", - "timerclk1", - "timerclk2", - "timerclk3"; - assigned-clocks = <&sp810_syscon 0>, - <&sp810_syscon 1>, - <&sp810_syscon 2>, - <&sp810_syscon 3>; - assigned-clock-parents = <&timclk>, - <&timclk>, - <&timclk>, - <&timclk>; - }; - - i2c0: i2c@10002000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "arm,versatile-i2c"; - reg = <0x10002000 0x1000>; - - rtc@68 { - compatible = "dallas,ds1338"; - reg = <0x68>; - }; - }; - - aaci: aaci@10004000 { - compatible = "arm,pl041", "arm,primecell"; - reg = <0x10004000 0x1000>; - interrupt-parent = <&intc_tc11mp>; - interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - mci: mmcsd@10005000 { - compatible = "arm,pl18x", "arm,primecell"; - reg = <0x10005000 0x1000>; - interrupt-parent = <&intc_tc11mp>; - interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>, - <0 15 IRQ_TYPE_LEVEL_HIGH>; - /* Due to frequent FIFO overruns, use just 500 kHz */ - max-frequency = <500000>; - bus-width = <4>; - cap-sd-highspeed; - cap-mmc-highspeed; - clocks = <&mclk>, <&pclk>; - clock-names = "mclk", "apb_pclk"; - vmmc-supply = <&vmmc>; - cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; - }; - - kmi0: kmi@10006000 { - compatible = "arm,pl050", "arm,primecell"; - reg = <0x10006000 0x1000>; - interrupt-parent = <&intc_tc11mp>; - interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&kmiclk>, <&pclk>; - clock-names = "KMIREFCLK", "apb_pclk"; - }; - - kmi1: kmi@10007000 { - compatible = "arm,pl050", "arm,primecell"; - reg = <0x10007000 0x1000>; - interrupt-parent = <&intc_tc11mp>; - interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&kmiclk>, <&pclk>; - clock-names = "KMIREFCLK", "apb_pclk"; - }; - - pb11mp_serial0: serial@10009000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x10009000 0x1000>; - interrupt-parent = <&intc_tc11mp>; - interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&uartclk>, <&pclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - pb11mp_serial1: serial@1000a000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x1000a000 0x1000>; - interrupt-parent = <&intc_tc11mp>; - interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&uartclk>, <&pclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - pb11mp_serial2: serial@1000b000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x1000b000 0x1000>; - interrupt-parent = <&intc_pb11mp>; - interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&uartclk>, <&pclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - pb11mp_serial3: serial@1000c000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x1000c000 0x1000>; - interrupt-parent = <&intc_pb11mp>; - interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&uartclk>, <&pclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - spi@1000d000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x1000d000 0x1000>; - interrupt-parent = <&intc_pb11mp>; - interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&sspclk>, <&pclk>; - clock-names = "SSPCLK", "apb_pclk"; - }; - - watchdog@1000f000 { - compatible = "arm,sp805", "arm,primecell"; - reg = <0x1000f000 0x1000>; - interrupt-parent = <&intc_pb11mp>; - interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&wdogclk>, <&pclk>; - clock-names = "wdogclk", "apb_pclk"; - status = "disabled"; - }; - - watchdog@10010000 { - compatible = "arm,sp805", "arm,primecell"; - reg = <0x10010000 0x1000>; - interrupt-parent = <&intc_pb11mp>; - interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&wdogclk>, <&pclk>; - clock-names = "wdogclk", "apb_pclk"; - }; - - timer01: timer@10011000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x10011000 0x1000>; - interrupt-parent = <&intc_tc11mp>; - interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH>; - arm,sp804-has-irq = <1>; - clocks = <&sp810_syscon 0>, - <&sp810_syscon 1>, - <&pclk>; - clock-names = "timerclk0", - "timerclk1", - "apb_pclk"; - }; - - timer23: timer@10012000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x10012000 0x1000>; - interrupt-parent = <&intc_tc11mp>; - interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>; - arm,sp804-has-irq = <1>; - clocks = <&sp810_syscon 2>, - <&sp810_syscon 3>, - <&pclk>; - clock-names = "timerclk2", - "timerclk3", - "apb_pclk"; - }; - - gpio0: gpio@10013000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x10013000 0x1000>; - gpio-controller; - interrupt-parent = <&intc_pb11mp>; - interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - gpio1: gpio@10014000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x10014000 0x1000>; - gpio-controller; - interrupt-parent = <&intc_pb11mp>; - interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - gpio2: gpio@10015000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x10015000 0x1000>; - gpio-controller; - interrupt-parent = <&intc_pb11mp>; - interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - i2c1: i2c@10016000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "arm,versatile-i2c"; - reg = <0x10016000 0x1000>; - }; - - rtc: rtc@10017000 { - compatible = "arm,pl031", "arm,primecell"; - reg = <0x10017000 0x1000>; - interrupt-parent = <&intc_tc11mp>; - interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - timer45: timer@10018000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x10018000 0x1000>; - clocks = <&timclk>, <&pclk>; - clock-names = "timer", "apb_pclk"; - status = "disabled"; - }; - - timer67: timer@10019000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x10019000 0x1000>; - clocks = <&timclk>, <&pclk>; - clock-names = "timer", "apb_pclk"; - status = "disabled"; - }; - - - clcd@10020000 { - compatible = "arm,pl111", "arm,primecell"; - reg = <0x10020000 0x1000>; - interrupt-parent = <&intc_pb11mp>; - interrupt-names = "combined"; - interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&oscclk4>, <&pclk>; - clock-names = "clcdclk", "apb_pclk"; - /* 1024x768 16bpp @65MHz works fine */ - max-memory-bandwidth = <95000000>; - - port { - clcd_pads: endpoint { - remote-endpoint = <&vga_bridge_in>; - arm,pl11x,tft-r0g0b0-pads = <0 8 16>; - }; - }; - }; - - /* - * This GIC on the Platform Baseboard is cascaded off the - * TestChip GIC - */ - intc_pb11mp: interrupt-controller@1e000000 { - compatible = "arm,arm11mp-gic"; - #interrupt-cells = <3>; - #address-cells = <1>; - interrupt-controller; - reg = <0x1e001000 0x1000>, - <0x1e000000 0x100>; - interrupt-parent = <&intc_tc11mp>; - interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; - }; - - /* SMSC 9118 ethernet with PHY and EEPROM */ - ethernet@4e000000 { - compatible = "smsc,lan9118", "smsc,lan9115"; - reg = <0x4e000000 0x10000>; - interrupt-parent = <&intc_tc11mp>; - interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; - phy-mode = "mii"; - reg-io-width = <4>; - smsc,irq-active-high; - smsc,irq-push-pull; - vdd33a-supply = <&veth>; - vddvario-supply = <&veth>; - }; - - usb@4f000000 { - compatible = "nxp,usb-isp1761"; - reg = <0x4f000000 0x20000>; - interrupt-parent = <&intc_tc11mp>; - interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>; - port1-otg; - }; - }; -}; diff --git a/sys/gnu/dts/arm/arm-realview-pba8.dts b/sys/gnu/dts/arm/arm-realview-pba8.dts deleted file mode 100644 index d3238c252b5..00000000000 --- a/sys/gnu/dts/arm/arm-realview-pba8.dts +++ /dev/null @@ -1,178 +0,0 @@ -/* - * Copyright 2016 Linaro Ltd - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -/dts-v1/; -#include "arm-realview-pbx.dtsi" - -/ { - model = "ARM RealView Platform Baseboard for Cortex-A8"; - compatible = "arm,realview-pba8"; - arm,hbi = <0x178>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "arm,realview-smp"; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a8"; - reg = <0>; - }; - }; - - pmu: pmu@0 { - compatible = "arm,cortex-a8-pmu"; - interrupt-parent = <&intc>; - interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&cpu0>; - }; - - /* Primary GIC PL390 interrupt controller in the test chip */ - intc: interrupt-controller@1e000000 { - compatible = "arm,pl390"; - #interrupt-cells = <3>; - #address-cells = <1>; - interrupt-controller; - reg = <0x1e001000 0x1000>, - <0x1e000000 0x100>; - }; -}; - -ðernet { - interrupt-parent = <&intc>; - interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>; -}; - -&usb { - interrupt-parent = <&intc>; - interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>; -}; - -&soc { - compatible = "arm,realview-pba8-soc", "simple-bus"; -}; - -&syscon { - compatible = "arm,realview-pba8-syscon", "syscon", "simple-mfd"; -}; - -&serial0 { - interrupt-parent = <&intc>; - interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>; -}; - -&serial1 { - interrupt-parent = <&intc>; - interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>; -}; - -&serial2 { - interrupt-parent = <&intc>; - interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; -}; - -&serial3 { - interrupt-parent = <&intc>; - interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>; -}; - -&ssp { - interrupt-parent = <&intc>; - interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; -}; - -&wdog0 { - interrupt-parent = <&intc>; - interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>; -}; - -&wdog1 { - interrupt-parent = <&intc>; - interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>; -}; - -&timer01 { - interrupt-parent = <&intc>; - interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>; -}; - -&timer23 { - interrupt-parent = <&intc>; - interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>; -}; - -&gpio0 { - interrupt-parent = <&intc>; - interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; -}; - -&gpio1 { - interrupt-parent = <&intc>; - interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; -}; - -&gpio2 { - interrupt-parent = <&intc>; - interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; -}; - -&rtc { - interrupt-parent = <&intc>; - interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; -}; - -&timer45 { - interrupt-parent = <&intc>; - interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>; -}; - -&timer67 { - interrupt-parent = <&intc>; - interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>; -}; - -&aaci { - interrupt-parent = <&intc>; - interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>; -}; - -&mmc { - interrupt-parent = <&intc>; - interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>, - <0 18 IRQ_TYPE_LEVEL_HIGH>; -}; - -&kmi0 { - interrupt-parent = <&intc>; - interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>; -}; - -&kmi1 { - interrupt-parent = <&intc>; - interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>; -}; - -&clcd { - interrupt-parent = <&intc>; - interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; -}; diff --git a/sys/gnu/dts/arm/arm-realview-pbx-a9.dts b/sys/gnu/dts/arm/arm-realview-pbx-a9.dts deleted file mode 100644 index 90d00b407f8..00000000000 --- a/sys/gnu/dts/arm/arm-realview-pbx-a9.dts +++ /dev/null @@ -1,228 +0,0 @@ -/* - * Copyright 2016 Linaro Ltd - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -/dts-v1/; -#include "arm-realview-pbx.dtsi" - -/ { - /* - * This is the RealView Platform Baseboard Explore for Cortex-A9 - * (HBI0182 + HBI0183) as described in ARM DUI 0440B - */ - model = "ARM RealView Platform Baseboard Explore for Cortex-A9"; - arm,hbi = <0x182>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "arm,realview-smp"; - - cpu-map { - cluster0 { - core0 { - cpu = <&CPU0>; - }; - core1 { - cpu = <&CPU1>; - }; - }; - }; - CPU0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0x0>; - next-level-cache = <&L2>; - }; - CPU1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0x1>; - next-level-cache = <&L2>; - }; - }; - - L2: l2-cache { - compatible = "arm,pl310-cache"; - reg = <0x1f002000 0x1000>; - cache-unified; - cache-level = <2>; - /* - * Override default cache size, sets and - * associativity as these may be erroneously set - * up by boot loader(s). - */ - cache-size = <131072>; // 128KB - cache-sets = <512>; - cache-line-size = <32>; - arm,parity-disable; - arm,tag-latency = <1 1 1>; - arm,data-latency = <1 1 1>; - }; - - scu: scu@1f000000 { - compatible = "arm,cortex-a9-scu"; - reg = <0x1f000000 0x100>; - }; - - twd_timer: timer@1f000600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0x1f000600 0x20>; - interrupt-parent = <&intc>; - interrupts = <1 13 0xf04>; - }; - - twd_wdog: watchdog@1f000620 { - compatible = "arm,cortex-a9-twd-wdt"; - reg = <0x1f000620 0x20>; - interrupt-parent = <&intc>; - interrupts = <1 14 0xf04>; - }; - - pmu: pmu@0 { - compatible = "arm,cortex-a9-pmu"; - interrupt-parent = <&intc>; - interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>, - <0 45 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&CPU0>, <&CPU1>; - }; - - /* Primary GIC PL390 interrupt controller in the test chip */ - intc: interrupt-controller@1f000000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <1>; - interrupt-controller; - reg = <0x1f001000 0x1000>, - <0x1f000100 0x100>; - }; -}; - -ðernet { - interrupt-parent = <&intc>; - interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>; -}; - -&usb { - interrupt-parent = <&intc>; - interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>; -}; - -&serial0 { - interrupt-parent = <&intc>; - interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>; -}; - -&serial1 { - interrupt-parent = <&intc>; - interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>; -}; - -&serial2 { - interrupt-parent = <&intc>; - interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; -}; - -&serial3 { - interrupt-parent = <&intc>; - interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>; -}; - -&ssp { - interrupt-parent = <&intc>; - interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; -}; - -&wdog0 { - interrupt-parent = <&intc>; - interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>; -}; - -&wdog1 { - interrupt-parent = <&intc>; - interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>; -}; - -&timer01 { - interrupt-parent = <&intc>; - interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>; -}; - -&timer23 { - interrupt-parent = <&intc>; - interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>; -}; - -&gpio0 { - interrupt-parent = <&intc>; - interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; -}; - -&gpio1 { - interrupt-parent = <&intc>; - interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; -}; - -&gpio2 { - interrupt-parent = <&intc>; - interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; -}; - -&rtc { - interrupt-parent = <&intc>; - interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; -}; - -&timer45 { - interrupt-parent = <&intc>; - interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>; -}; - -&timer67 { - interrupt-parent = <&intc>; - interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>; -}; - -&aaci { - interrupt-parent = <&intc>; - interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>; -}; - -&mmc { - interrupt-parent = <&intc>; - interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>, - <0 18 IRQ_TYPE_LEVEL_HIGH>; -}; - -&kmi0 { - interrupt-parent = <&intc>; - interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>; -}; - -&kmi1 { - interrupt-parent = <&intc>; - interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>; -}; - -&clcd { - interrupt-parent = <&intc>; - interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; -}; diff --git a/sys/gnu/dts/arm/arm-realview-pbx.dtsi b/sys/gnu/dts/arm/arm-realview-pbx.dtsi deleted file mode 100644 index 09f3f544f3a..00000000000 --- a/sys/gnu/dts/arm/arm-realview-pbx.dtsi +++ /dev/null @@ -1,577 +0,0 @@ -/* - * Copyright 2016 Linaro Ltd - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - compatible = "arm,realview-pbx"; - - chosen { }; - - aliases { - serial0 = &serial0; - serial1 = &serial1; - serial2 = &serial2; - serial3 = &serial3; - i2c0 = &i2c0; - i2c1 = &i2c1; - }; - - memory { - device_type = "memory"; - /* 128 MiB memory @ 0x0 */ - reg = <0x00000000 0x08000000>; - }; - - /* The voltage to the MMC card is hardwired at 3.3V */ - vmmc: regulator-vmmc { - compatible = "regulator-fixed"; - regulator-name = "vmmc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; - - veth: regulator-veth { - compatible = "regulator-fixed"; - regulator-name = "veth"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; - - xtal24mhz: xtal24mhz@24M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - }; - - refclk32khz: refclk32khz { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - timclk: timclk@1M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <24>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - mclk: mclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - kmiclk: kmiclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - sspclk: sspclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - uartclk: uartclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - wdogclk: wdogclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - /* FIXME: this actually hangs off the PLL clocks */ - pclk: pclk@0 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - flash0@40000000 { - /* 2 * 32MiB NOR Flash memory */ - compatible = "arm,versatile-flash", "cfi-flash"; - reg = <0x40000000 0x04000000>; - bank-width = <4>; - partitions { - compatible = "arm,arm-firmware-suite"; - }; - }; - - flash1@44000000 { - /* 2 * 32MiB NOR Flash memory */ - compatible = "arm,versatile-flash", "cfi-flash"; - reg = <0x44000000 0x04000000>; - bank-width = <4>; - partitions { - compatible = "arm,arm-firmware-suite"; - }; - }; - - /* SMSC 9118 ethernet with PHY and EEPROM */ - ethernet: ethernet@4e000000 { - compatible = "smsc,lan9118", "smsc,lan9115"; - reg = <0x4e000000 0x10000>; - phy-mode = "mii"; - reg-io-width = <4>; - smsc,irq-active-high; - smsc,irq-push-pull; - vdd33a-supply = <&veth>; - vddvario-supply = <&veth>; - }; - - usb: usb@4f000000 { - compatible = "nxp,usb-isp1761"; - reg = <0x4f000000 0x20000>; - port1-otg; - }; - - bridge { - compatible = "ti,ths8134a", "ti,ths8134"; - #address-cells = <1>; - #size-cells = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - vga_bridge_in: endpoint { - remote-endpoint = <&clcd_pads>; - }; - }; - - port@1 { - reg = <1>; - - vga_bridge_out: endpoint { - remote-endpoint = <&vga_con_in>; - }; - }; - }; - }; - - vga { - /* - * This DDC I2C is connected directly to the DVI portions - * of the connector, so it's not really working when the - * monitor is connected to the VGA connector. - */ - compatible = "vga-connector"; - ddc-i2c-bus = <&i2c1>; - - port { - vga_con_in: endpoint { - remote-endpoint = <&vga_bridge_out>; - }; - }; - }; - - soc: soc@0 { - compatible = "arm,realview-pbx-soc", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - regmap = <&syscon>; - ranges; - - syscon: syscon@10000000 { - compatible = "arm,realview-pbx-syscon", "syscon", "simple-mfd"; - reg = <0x10000000 0x1000>; - - led@08.0 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x01>; - label = "versatile:0"; - linux,default-trigger = "heartbeat"; - default-state = "on"; - }; - led@08.1 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x02>; - label = "versatile:1"; - linux,default-trigger = "mmc0"; - default-state = "off"; - }; - led@08.2 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x04>; - label = "versatile:2"; - linux,default-trigger = "cpu0"; - default-state = "off"; - }; - led@08.3 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x08>; - label = "versatile:3"; - default-state = "off"; - }; - led@08.4 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x10>; - label = "versatile:4"; - default-state = "off"; - }; - led@08.5 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x20>; - label = "versatile:5"; - default-state = "off"; - }; - led@08.6 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x40>; - label = "versatile:6"; - default-state = "off"; - }; - led@08.7 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x80>; - label = "versatile:7"; - default-state = "off"; - }; - oscclk0: osc0@0c { - compatible = "arm,syscon-icst307"; - #clock-cells = <0>; - lock-offset = <0x20>; - vco-offset = <0x0C>; - clocks = <&xtal24mhz>; - }; - oscclk1: osc1@10 { - compatible = "arm,syscon-icst307"; - #clock-cells = <0>; - lock-offset = <0x20>; - vco-offset = <0x10>; - clocks = <&xtal24mhz>; - }; - oscclk2: osc2@14 { - compatible = "arm,syscon-icst307"; - #clock-cells = <0>; - lock-offset = <0x20>; - vco-offset = <0x14>; - clocks = <&xtal24mhz>; - }; - oscclk3: osc3@18 { - compatible = "arm,syscon-icst307"; - #clock-cells = <0>; - lock-offset = <0x20>; - vco-offset = <0x18>; - clocks = <&xtal24mhz>; - }; - oscclk4: osc4@1c { - compatible = "arm,syscon-icst307"; - #clock-cells = <0>; - lock-offset = <0x20>; - vco-offset = <0x1c>; - clocks = <&xtal24mhz>; - }; - }; - - sp810_syscon0: sysctl@10001000 { - compatible = "arm,sp810", "arm,primecell"; - reg = <0x10001000 0x1000>; - clocks = <&refclk32khz>, <&timclk>, <&xtal24mhz>; - clock-names = "refclk", "timclk", "apb_pclk"; - #clock-cells = <1>; - clock-output-names = "timerclk0", - "timerclk1", - "timerclk2", - "timerclk3"; - assigned-clocks = <&sp810_syscon0 0>, - <&sp810_syscon0 1>, - <&sp810_syscon0 2>, - <&sp810_syscon0 3>; - assigned-clock-parents = <&timclk>, - <&timclk>, - <&timclk>, - <&timclk>; - }; - - i2c0: i2c@10002000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "arm,versatile-i2c"; - reg = <0x10002000 0x1000>; - - rtc@68 { - compatible = "dallas,ds1338"; - reg = <0x68>; - }; - }; - - serial0: serial@10009000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x10009000 0x1000>; - clocks = <&uartclk>, <&pclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - serial1: serial@1000a000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x1000a000 0x1000>; - clocks = <&uartclk>, <&pclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - serial2: serial@1000b000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x1000b000 0x1000>; - clocks = <&uartclk>, <&pclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - ssp: spi@1000d000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x1000d000 0x1000>; - clocks = <&sspclk>, <&pclk>; - clock-names = "SSPCLK", "apb_pclk"; - }; - - wdog0: watchdog@1000f000 { - compatible = "arm,sp805", "arm,primecell"; - reg = <0x1000f000 0x1000>; - clocks = <&wdogclk>, <&pclk>; - clock-names = "wdogclk", "apb_pclk"; - status = "disabled"; - }; - - wdog1: watchdog@10010000 { - compatible = "arm,sp805", "arm,primecell"; - reg = <0x10010000 0x1000>; - clocks = <&wdogclk>, <&pclk>; - clock-names = "wdogclk", "apb_pclk"; - status = "disabled"; - }; - - timer01: timer@10011000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x10011000 0x1000>; - clocks = <&sp810_syscon0 0>, - <&sp810_syscon0 1>, - <&pclk>; - clock-names = "timerclk0", - "timerclk1", - "apb_pclk"; - }; - - timer23: timer@10012000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x10012000 0x1000>; - clocks = <&sp810_syscon0 2>, - <&sp810_syscon0 3>, - <&pclk>; - clock-names = "timerclk2", - "timerclk3", - "apb_pclk"; - }; - - gpio0: gpio@10013000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x10013000 0x1000>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - gpio1: gpio@10014000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x10014000 0x1000>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - gpio2: gpio@10015000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x10015000 0x1000>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - i2c1: i2c@10016000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "arm,versatile-i2c"; - reg = <0x10016000 0x1000>; - }; - - rtc: rtc@10017000 { - compatible = "arm,pl031", "arm,primecell"; - reg = <0x10017000 0x1000>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - timer45: timer@10018000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x10018000 0x1000>; - clocks = <&timclk>, <&timclk>, <&pclk>; - clock-names = "timerclk4", "timerclk5", "apb_pclk"; - }; - - timer67: timer@10019000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x10019000 0x1000>; - clocks = <&timclk>, <&timclk>, <&pclk>; - clock-names = "timerclk6", "timerclk7", "apb_pclk"; - }; - - sp810_syscon1: sysctl@1001a000 { - compatible = "arm,sp810", "arm,primecell"; - reg = <0x1001a000 0x1000>; - clocks = <&refclk32khz>, <&timclk>, <&xtal24mhz>; - clock-names = "refclk", "timclk", "apb_pclk"; - #clock-cells = <1>; - clock-output-names = "timerclk4", - "timerclk5", - "timerclk6", - "timerclk7"; - assigned-clocks = <&sp810_syscon1 0>, - <&sp810_syscon1 1>, - <&sp810_syscon1 2>, - <&sp810_syscon1 3>; - assigned-clock-parents = <&timclk>, - <&timclk>, - <&timclk>, - <&timclk>; - }; - }; - - - /* These peripherals are inside the FPGA */ - fpga { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges; - - aaci: aaci@10004000 { - compatible = "arm,pl041", "arm,primecell"; - reg = <0x10004000 0x1000>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - mmc: mmcsd@10005000 { - compatible = "arm,pl18x", "arm,primecell"; - reg = <0x10005000 0x1000>; - - /* Due to frequent FIFO overruns, use just 500 kHz */ - max-frequency = <500000>; - bus-width = <4>; - cap-sd-highspeed; - cap-mmc-highspeed; - clocks = <&mclk>, <&pclk>; - clock-names = "mclk", "apb_pclk"; - vmmc-supply = <&vmmc>; - cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; - }; - - kmi0: kmi@10006000 { - compatible = "arm,pl050", "arm,primecell"; - reg = <0x10006000 0x1000>; - clocks = <&kmiclk>, <&pclk>; - clock-names = "KMIREFCLK", "apb_pclk"; - }; - - kmi1: kmi@10007000 { - compatible = "arm,pl050", "arm,primecell"; - reg = <0x10007000 0x1000>; - clocks = <&kmiclk>, <&pclk>; - clock-names = "KMIREFCLK", "apb_pclk"; - }; - - serial3: serial@1000c000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x1000c000 0x1000>; - clocks = <&uartclk>, <&pclk>; - clock-names = "uartclk", "apb_pclk"; - }; - }; - - /* These peripherals are inside the NEC ISSP */ - issp { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges; - - clcd: clcd@10020000 { - compatible = "arm,pl111", "arm,primecell"; - reg = <0x10020000 0x1000>; - interrupt-names = "combined"; - clocks = <&oscclk4>, <&pclk>; - clock-names = "clcdclk", "apb_pclk"; - /* 1024x768 16bpp @65MHz works fine */ - max-memory-bandwidth = <95000000>; - - port { - clcd_pads: endpoint { - remote-endpoint = <&vga_bridge_in>; - arm,pl11x,tft-r0g0b0-pads = <0 8 16>; - }; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/armada-370-db.dts b/sys/gnu/dts/arm/armada-370-db.dts deleted file mode 100644 index 77261a2fb94..00000000000 --- a/sys/gnu/dts/arm/armada-370-db.dts +++ /dev/null @@ -1,244 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for Marvell Armada 370 evaluation board - * (DB-88F6710-BP-DDR3) - * - * Copyright (C) 2012 Marvell - * - * Lior Amsalem - * Gregory CLEMENT - * Thomas Petazzoni - * - * Note: this Device Tree assumes that the bootloader has remapped the - * internal registers to 0xf1000000 (instead of the default - * 0xd0000000). The 0xf1000000 is the default used by the recent, - * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier - * boards were delivered with an older version of the bootloader that - * left internal registers mapped at 0xd0000000. If you are in this - * situation, you should either update your bootloader (preferred - * solution) or the below Device Tree should be adjusted. - */ - -/dts-v1/; -#include "armada-370.dtsi" - -/ { - model = "Marvell Armada 370 Evaluation Board"; - compatible = "marvell,a370-db", "marvell,armada370", "marvell,armada-370-xp"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x40000000>; /* 1 GB */ - }; - - soc { - ranges = ; - - internal-regs { - serial@12000 { - status = "okay"; - }; - sata@a0000 { - nr-ports = <2>; - status = "okay"; - }; - - ethernet@70000 { - pinctrl-0 = <&ge0_rgmii_pins>; - pinctrl-names = "default"; - status = "okay"; - phy = <&phy0>; - phy-mode = "rgmii-id"; - }; - ethernet@74000 { - pinctrl-0 = <&ge1_rgmii_pins>; - pinctrl-names = "default"; - status = "okay"; - phy = <&phy1>; - phy-mode = "rgmii-id"; - }; - - i2c@11000 { - pinctrl-0 = <&i2c0_pins>; - pinctrl-names = "default"; - clock-frequency = <100000>; - status = "okay"; - audio_codec: audio-codec@4a { - #sound-dai-cells = <0>; - compatible = "cirrus,cs42l51"; - reg = <0x4a>; - }; - }; - - audio-controller@30000 { - pinctrl-0 = <&i2s_pins2>; - pinctrl-names = "default"; - status = "okay"; - }; - - mvsdio@d4000 { - pinctrl-0 = <&sdio_pins1>; - pinctrl-names = "default"; - /* - * This device is disabled by default, because - * using the SD card connector requires - * changing the default CON40 connector - * "DB-88F6710_MPP_2xRGMII_DEVICE_Jumper" to a - * different connector - * "DB-88F6710_MPP_RGMII_SD_Jumper". - */ - status = "disabled"; - /* No CD or WP GPIOs */ - broken-cd; - }; - - usb@50000 { - status = "okay"; - }; - - usb@51000 { - status = "okay"; - }; - }; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "Armada 370 DB Audio"; - simple-audio-card,mclk-fs = <256>; - simple-audio-card,widgets = - "Headphone", "Out Jack", - "Line", "In Jack"; - simple-audio-card,routing = - "Out Jack", "HPL", - "Out Jack", "HPR", - "AIN1L", "In Jack", - "AIN1L", "In Jack"; - status = "okay"; - - simple-audio-card,dai-link@0 { - format = "i2s"; - cpu { - sound-dai = <&audio_controller 0>; - }; - - codec { - sound-dai = <&audio_codec>; - }; - }; - - simple-audio-card,dai-link@1 { - format = "i2s"; - cpu { - sound-dai = <&audio_controller 1>; - }; - - codec { - sound-dai = <&spdif_out>; - }; - }; - - simple-audio-card,dai-link@2 { - format = "i2s"; - cpu { - sound-dai = <&audio_controller 1>; - }; - - codec { - sound-dai = <&spdif_in>; - }; - }; - }; - - spdif_out: spdif-out { - #sound-dai-cells = <0>; - compatible = "linux,spdif-dit"; - }; - - spdif_in: spdif-in { - #sound-dai-cells = <0>; - compatible = "linux,spdif-dir"; - }; -}; - -&pciec { - status = "okay"; - /* - * The two PCIe units are accessible through - * both standard PCIe slots and mini-PCIe - * slots on the board. - */ - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - - pcie@2,0 { - /* Port 1, Lane 0 */ - status = "okay"; - }; -}; - -&mdio { - pinctrl-0 = <&mdio_pins>; - pinctrl-names = "default"; - phy0: ethernet-phy@0 { - reg = <0>; - }; - - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - - -&spi0 { - pinctrl-0 = <&spi0_pins2>; - pinctrl-names = "default"; - status = "okay"; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "mx25l25635e", "jedec,spi-nor"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <50000000>; - }; -}; - -&nand_controller { - status = "okay"; - - nand@0 { - reg = <0>; - label = "pxa3xx_nand-0"; - nand-rb = <0>; - marvell,nand-keep-config; - nand-on-flash-bbt; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "U-Boot"; - reg = <0 0x800000>; - }; - partition@800000 { - label = "Linux"; - reg = <0x800000 0x800000>; - }; - partition@1000000 { - label = "Filesystem"; - reg = <0x1000000 0x3f000000>; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/armada-370-dlink-dns327l.dts b/sys/gnu/dts/arm/armada-370-dlink-dns327l.dts deleted file mode 100644 index baa459dd51e..00000000000 --- a/sys/gnu/dts/arm/armada-370-dlink-dns327l.dts +++ /dev/null @@ -1,331 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for D-Link DNS-327L - * - * Copyright (C) 2015, Andrew Andrianov - */ - -/* Remaining unsolved: - * There's still some unknown device on i2c address 0x13 - */ - -/dts-v1/; - -#include -#include -#include "armada-370.dtsi" - -/ { - model = "D-Link DNS-327L"; - compatible = "dlink,dns327l", - "marvell,armada370", - "marvell,armada-370-xp"; - - chosen { - stdout-path = &uart0; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x20000000>; /* 512 MiB */ - }; - - soc { - ranges = ; - - internal-regs { - sata@a0000 { - nr-ports = <2>; - status = "okay"; - }; - - usb@50000 { - status = "okay"; - }; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-0 = < - &backup_button_pin - &power_button_pin - &reset_button_pin>; - pinctrl-names = "default"; - - power-button { - label = "Power Button"; - linux,code = ; - gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; - }; - - backup-button { - label = "Backup Button"; - linux,code = ; - gpios = <&gpio1 31 GPIO_ACTIVE_LOW>; - }; - - reset-button { - label = "Reset Button"; - linux,code = ; - gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = < - &sata_l_amber_pin - &sata_r_amber_pin - &backup_led_pin - /* Ensure these are managed by hardware */ - &sata_l_white_pin - &sata_r_white_pin>; - - pinctrl-names = "default"; - - sata-r-amber-pin { - label = "dns327l:amber:sata-r"; - gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - - sata-l-amber-pin { - label = "dns327l:amber:sata-l"; - gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - - backup-led-pin { - label = "dns327l:white:usb"; - gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - usb_power: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - pinctrl-0 = <&xhci_pwr_pin>; - pinctrl-names = "default"; - regulator-name = "USB3.0 Port Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-boot-on; - regulator-always-on; - gpio = <&gpio0 13 GPIO_ACTIVE_HIGH>; - }; - - sata_r_power: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - pinctrl-0 = <&sata_r_pwr_pin>; - pinctrl-names = "default"; - regulator-name = "SATA-R Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - startup-delay-us = <2000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>; - }; - - sata_l_power: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - pinctrl-0 = <&sata_l_pwr_pin>; - pinctrl-names = "default"; - regulator-name = "SATA-L Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - startup-delay-us = <4000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio1 24 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&pciec { - status = "okay"; - - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - - pcie@2,0 { - /* Port 1, Lane 0 */ - status = "okay"; - }; -}; - -&pinctrl { - sata_l_white_pin: sata-l-white-pin { - marvell,pins = "mpp57"; - marvell,function = "sata0"; - }; - - sata_r_white_pin: sata-r-white-pin { - marvell,pins = "mpp55"; - marvell,function = "sata1"; - }; - - sata_r_amber_pin: sata-r-amber-pin { - marvell,pins = "mpp52"; - marvell,function = "gpio"; - }; - - sata_l_amber_pin: sata-l-amber-pin { - marvell,pins = "mpp53"; - marvell,function = "gpio"; - }; - - backup_led_pin: backup-led-pin { - marvell,pins = "mpp61"; - marvell,function = "gpo"; - }; - - xhci_pwr_pin: xhci-pwr-pin { - marvell,pins = "mpp13"; - marvell,function = "gpio"; - }; - - sata_r_pwr_pin: sata-r-pwr-pin { - marvell,pins = "mpp54"; - marvell,function = "gpio"; - }; - - sata_l_pwr_pin: sata-l-pwr-pin { - marvell,pins = "mpp56"; - marvell,function = "gpio"; - }; - - uart1_pins: uart1-pins { - marvell,pins = "mpp60", "mpp61"; - marvell,function = "uart1"; - }; - - power_button_pin: power-button-pin { - marvell,pins = "mpp65"; - marvell,function = "gpio"; - }; - - backup_button_pin: backup-button-pin { - marvell,pins = "mpp63"; - marvell,function = "gpio"; - }; - - reset_button_pin: reset-button-pin { - marvell,pins = "mpp64"; - marvell,function = "gpio"; - }; -}; - -/* Serial console */ -&uart0 { - status = "okay"; -}; - -/* Connected to Weltrend MCU */ -&uart1 { - pinctrl-0 = <&uart1_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&mdio { - phy0: ethernet-phy@0 { /* Marvell 88E1318 */ - reg = <0>; - marvell,reg-init = <0x0 0x16 0x0 0x0002>, - <0x0 0x19 0x0 0x0077>, - <0x0 0x18 0x0 0x5747>; - }; -}; - -ð1 { - phy = <&phy0>; - phy-mode = "rgmii-id"; - status = "okay"; -}; - -&i2c0 { - compatible = "marvell,mv64xxx-i2c"; - clock-frequency = <100000>; - status = "okay"; -}; - -&nand_controller { - status = "okay"; - - nand@0 { - reg = <0>; - label = "pxa3xx_nand-0"; - nand-rb = <0>; - marvell,nand-keep-config; - nand-on-flash-bbt; - nand-ecc-strength = <4>; - nand-ecc-step-size = <512>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - /* 1.0 MiB */ - reg = <0x0000000 0x100000>; - read-only; - }; - - partition@100000 { - label = "u-boot-env"; - /* 128 KiB */ - reg = <0x100000 0x20000>; - read-only; - }; - - partition@120000 { - label = "uImage"; - /* 7 MiB */ - reg = <0x120000 0x700000>; - }; - - partition@820000 { - label = "ubifs"; - /* ~ 84 MiB */ - reg = <0x820000 0x54e0000>; - }; - - /* Hardcoded into stock bootloader */ - partition@5d00000 { - label = "failsafe-uImage"; - /* 5 MiB */ - reg = <0x5d00000 0x500000>; - }; - - partition@6200000 { - label = "failsafe-fs"; - /* 29 MiB */ - reg = <0x6200000 0x1d00000>; - }; - - partition@7f00000 { - label = "bbt"; - /* 1 MiB for BBT */ - reg = <0x7f00000 0x100000>; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/armada-370-mirabox.dts b/sys/gnu/dts/arm/armada-370-mirabox.dts deleted file mode 100644 index 7c2f5a79b50..00000000000 --- a/sys/gnu/dts/arm/armada-370-mirabox.dts +++ /dev/null @@ -1,184 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for Globalscale Mirabox - * - * Gregory CLEMENT - */ - -/dts-v1/; -#include -#include "armada-370.dtsi" - -/ { - model = "Globalscale Mirabox"; - compatible = "globalscale,mirabox", "marvell,armada370", "marvell,armada-370-xp"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x20000000>; /* 512 MB */ - }; - - soc { - ranges = ; - - internal-regs { - serial@12000 { - status = "okay"; - }; - timer@20300 { - clock-frequency = <600000000>; - status = "okay"; - }; - - gpio_leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pwr_led_pin &stat_led_pins>; - - green_pwr_led { - label = "mirabox:green:pwr"; - gpios = <&gpio1 31 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - - blue_stat_led { - label = "mirabox:blue:stat"; - gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - green_stat_led { - label = "mirabox:green:stat"; - gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - }; - - ethernet@70000 { - pinctrl-0 = <&ge0_rgmii_pins>; - pinctrl-names = "default"; - status = "okay"; - phy = <&phy0>; - phy-mode = "rgmii-id"; - }; - ethernet@74000 { - pinctrl-0 = <&ge1_rgmii_pins>; - pinctrl-names = "default"; - status = "okay"; - phy = <&phy1>; - phy-mode = "rgmii-id"; - }; - - crypto@90000 { - status = "okay"; - }; - - mvsdio@d4000 { - pinctrl-0 = <&sdio_pins3>; - pinctrl-names = "default"; - status = "okay"; - /* - * No CD or WP GPIOs: SDIO interface used for - * Wifi/Bluetooth chip - */ - broken-cd; - }; - - usb@50000 { - status = "okay"; - }; - - usb@51000 { - status = "okay"; - }; - - i2c@11000 { - status = "okay"; - clock-frequency = <100000>; - pca9505: pca9505@25 { - compatible = "nxp,pca9505"; - gpio-controller; - #gpio-cells = <2>; - reg = <0x25>; - }; - }; - }; - }; -}; - -&pciec { - status = "okay"; - - /* Internal mini-PCIe connector */ - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - - /* Connected on the PCB to a USB 3.0 XHCI controller */ - pcie@2,0 { - /* Port 1, Lane 0 */ - status = "okay"; - }; -}; - -&mdio { - pinctrl-0 = <&mdio_pins>; - pinctrl-names = "default"; - phy0: ethernet-phy@0 { - reg = <0>; - }; - - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&pinctrl { - pwr_led_pin: pwr-led-pin { - marvell,pins = "mpp63"; - marvell,function = "gpio"; - }; - - stat_led_pins: stat-led-pins { - marvell,pins = "mpp64", "mpp65"; - marvell,function = "gpio"; - }; -}; - -&nand_controller { - status = "okay"; - - nand@0 { - reg = <0>; - label = "pxa3xx_nand-0"; - nand-rb = <0>; - marvell,nand-keep-config; - nand-on-flash-bbt; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "U-Boot"; - reg = <0 0x400000>; - }; - partition@400000 { - label = "Linux"; - reg = <0x400000 0x400000>; - }; - partition@800000 { - label = "Filesystem"; - reg = <0x800000 0x3f800000>; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/armada-370-netgear-rn102.dts b/sys/gnu/dts/arm/armada-370-netgear-rn102.dts deleted file mode 100644 index b0b640b7de4..00000000000 --- a/sys/gnu/dts/arm/armada-370-netgear-rn102.dts +++ /dev/null @@ -1,276 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for NETGEAR ReadyNAS 102 - * - * Copyright (C) 2013, Arnaud EBALARD - */ - -/dts-v1/; - -#include -#include -#include "armada-370.dtsi" - -/ { - model = "NETGEAR ReadyNAS 102"; - compatible = "netgear,readynas-102", "marvell,armada370", "marvell,armada-370-xp"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x20000000>; /* 512 MB */ - }; - - soc { - ranges = ; - - internal-regs { - - /* RTC is provided by Intersil ISL12057 I2C RTC chip */ - rtc@10300 { - status = "disabled"; - }; - - serial@12000 { - status = "okay"; - }; - - /* eSATA interface */ - sata@a0000 { - nr-ports = <1>; - status = "okay"; - }; - - ethernet@74000 { - pinctrl-0 = <&ge1_rgmii_pins>; - pinctrl-names = "default"; - status = "okay"; - phy = <&phy0>; - phy-mode = "rgmii-id"; - }; - - usb@50000 { - status = "okay"; - }; - - i2c@11000 { - clock-frequency = <100000>; - - pinctrl-0 = <&i2c0_pins>; - pinctrl-names = "default"; - - status = "okay"; - - isl12057: rtc@68 { - compatible = "isil,isl12057"; - reg = <0x68>; - wakeup-source; - }; - - g762: g762@3e { - compatible = "gmt,g762"; - reg = <0x3e>; - clocks = <&g762_clk>; /* input clock */ - fan_gear_mode = <0>; - fan_startv = <1>; - pwm_polarity = <0>; - }; - }; - }; - }; - - clocks { - g762_clk: g762-oscillator { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <8192>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&power_led_pin - &sata1_led_pin - &sata2_led_pin - &backup_led_pin>; - pinctrl-names = "default"; - - blue-power-led { - label = "rn102:blue:pwr"; - gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - - blue-sata1-led { - label = "rn102:blue:sata1"; - gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; - default-state = "on"; - }; - - blue-sata2-led { - label = "rn102:blue:sata2"; - gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; - default-state = "on"; - }; - - blue-backup-led { - label = "rn102:blue:backup"; - gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; - default-state = "on"; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-0 = <&power_button_pin - &reset_button_pin - &backup_button_pin>; - pinctrl-names = "default"; - - power-button { - label = "Power Button"; - linux,code = ; - gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; - }; - - reset-button { - label = "Reset Button"; - linux,code = ; - gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; - }; - - backup-button { - label = "Backup Button"; - linux,code = ; - gpios = <&gpio1 26 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-poweroff { - compatible = "gpio-poweroff"; - pinctrl-0 = <&poweroff>; - pinctrl-names = "default"; - gpios = <&gpio0 8 GPIO_ACTIVE_LOW>; - }; -}; - -&pciec { - status = "okay"; - - /* Connected to Marvell 88SE9170 SATA controller */ - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - - /* Connected to FL1009 USB 3.0 controller */ - pcie@2,0 { - /* Port 1, Lane 0 */ - status = "okay"; - }; -}; - -&mdio { - pinctrl-0 = <&mdio_pins>; - pinctrl-names = "default"; - phy0: ethernet-phy@0 { /* Marvell 88E1318 */ - reg = <0>; - }; -}; - -&pinctrl { - power_led_pin: power-led-pin { - marvell,pins = "mpp57"; - marvell,function = "gpio"; - }; - - sata1_led_pin: sata1-led-pin { - marvell,pins = "mpp15"; - marvell,function = "gpio"; - }; - - sata2_led_pin: sata2-led-pin { - marvell,pins = "mpp14"; - marvell,function = "gpio"; - }; - - backup_led_pin: backup-led-pin { - marvell,pins = "mpp56"; - marvell,function = "gpio"; - }; - - backup_button_pin: backup-button-pin { - marvell,pins = "mpp58"; - marvell,function = "gpio"; - }; - - power_button_pin: power-button-pin { - marvell,pins = "mpp62"; - marvell,function = "gpio"; - }; - - reset_button_pin: reset-button-pin { - marvell,pins = "mpp6"; - marvell,function = "gpio"; - }; - - poweroff: poweroff { - marvell,pins = "mpp8"; - marvell,function = "gpio"; - }; -}; - -&nand_controller { - status = "okay"; - - nand@0 { - reg = <0>; - label = "pxa3xx_nand-0"; - nand-rb = <0>; - marvell,nand-keep-config; - nand-on-flash-bbt; - - /* Use Hardware BCH ECC */ - nand-ecc-strength = <4>; - nand-ecc-step-size = <512>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0x180000>; /* 1.5MB */ - read-only; - }; - - partition@180000 { - label = "u-boot-env"; - reg = <0x180000 0x20000>; /* 128KB */ - read-only; - }; - - partition@200000 { - label = "uImage"; - reg = <0x0200000 0x600000>; /* 6MB */ - }; - - partition@800000 { - label = "minirootfs"; - reg = <0x0800000 0x400000>; /* 4MB */ - }; - - /* Last MB is for the BBT, i.e. not writable */ - partition@c00000 { - label = "ubifs"; - reg = <0x0c00000 0x7400000>; /* 116MB */ - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/armada-370-netgear-rn104.dts b/sys/gnu/dts/arm/armada-370-netgear-rn104.dts deleted file mode 100644 index 85e2e9e27a9..00000000000 --- a/sys/gnu/dts/arm/armada-370-netgear-rn104.dts +++ /dev/null @@ -1,302 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for NETGEAR ReadyNAS 104 - * - * Copyright (C) 2013, Arnaud EBALARD - */ - -/dts-v1/; - -#include -#include -#include "armada-370.dtsi" - -/ { - model = "NETGEAR ReadyNAS 104"; - compatible = "netgear,readynas-104", "marvell,armada370", "marvell,armada-370-xp"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x20000000>; /* 512 MB */ - }; - - soc { - ranges = ; - - internal-regs { - - /* RTC is provided by Intersil ISL12057 I2C RTC chip */ - rtc@10300 { - status = "disabled"; - }; - - serial@12000 { - status = "okay"; - }; - - ethernet@70000 { - pinctrl-0 = <&ge0_rgmii_pins>; - pinctrl-names = "default"; - status = "okay"; - phy = <&phy0>; - phy-mode = "rgmii-id"; - }; - - ethernet@74000 { - pinctrl-0 = <&ge1_rgmii_pins>; - pinctrl-names = "default"; - status = "okay"; - phy = <&phy1>; - phy-mode = "rgmii-id"; - }; - - usb@50000 { - status = "okay"; - }; - - i2c@11000 { - clock-frequency = <100000>; - - pinctrl-0 = <&i2c0_pins>; - pinctrl-names = "default"; - - status = "okay"; - - isl12057: rtc@68 { - compatible = "isil,isl12057"; - reg = <0x68>; - wakeup-source; - }; - - g762: g762@3e { - compatible = "gmt,g762"; - reg = <0x3e>; - clocks = <&g762_clk>; /* input clock */ - fan_gear_mode = <0>; - fan_startv = <1>; - pwm_polarity = <0>; - }; - - pca9554: pca9554@23 { - compatible = "nxp,pca9554"; - gpio-controller; - #gpio-cells = <2>; - reg = <0x23>; - }; - }; - }; - }; - - clocks { - g762_clk: g762-oscillator { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <8192>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&backup_led_pin &power_led_pin>; - pinctrl-names = "default"; - - blue-backup-led { - label = "rn104:blue:backup"; - gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - blue-power-led { - label = "rn104:blue:pwr"; - gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; - linux,default-trigger = "keep"; - }; - - blue-sata1-led { - label = "rn104:blue:sata1"; - gpios = <&pca9554 0 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - blue-sata2-led { - label = "rn104:blue:sata2"; - gpios = <&pca9554 1 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - blue-sata3-led { - label = "rn104:blue:sata3"; - gpios = <&pca9554 2 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - blue-sata4-led { - label = "rn104:blue:sata4"; - gpios = <&pca9554 3 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - }; - - auxdisplay { - compatible = "hit,hd44780"; - data-gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>, - <&gpio1 26 GPIO_ACTIVE_HIGH>, - <&gpio1 27 GPIO_ACTIVE_HIGH>, - <&gpio1 29 GPIO_ACTIVE_HIGH>; - enable-gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>; - rs-gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>; - rw-gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>; - backlight-gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; - display-height-chars = <2>; - display-width-chars = <16>; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-0 = <&backup_button_pin - &power_button_pin - &reset_button_pin>; - pinctrl-names = "default"; - - backup-button { - label = "Backup Button"; - linux,code = ; - gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; - }; - - power-button { - label = "Power Button"; - linux,code = ; - gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; - }; - - reset-button { - label = "Reset Button"; - linux,code = ; - gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-poweroff { - compatible = "gpio-poweroff"; - pinctrl-0 = <&poweroff>; - pinctrl-names = "default"; - gpios = <&gpio1 28 GPIO_ACTIVE_LOW>; - }; -}; - -&pciec { - status = "okay"; - - /* Connected to FL1009 USB 3.0 controller */ - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - - /* Connected to Marvell 88SE9215 SATA controller */ - pcie@2,0 { - /* Port 1, Lane 0 */ - status = "okay"; - }; -}; - -&mdio { - pinctrl-0 = <&mdio_pins>; - pinctrl-names = "default"; - phy0: ethernet-phy@0 { /* Marvell 88E1318 */ - reg = <0>; - }; - - phy1: ethernet-phy@1 { /* Marvell 88E1318 */ - reg = <1>; - }; -}; - -&pinctrl { - poweroff: poweroff { - marvell,pins = "mpp60"; - marvell,function = "gpio"; - }; - - backup_button_pin: backup-button-pin { - marvell,pins = "mpp52"; - marvell,function = "gpio"; - }; - - power_button_pin: power-button-pin { - marvell,pins = "mpp62"; - marvell,function = "gpio"; - }; - - backup_led_pin: backup-led-pin { - marvell,pins = "mpp63"; - marvell,function = "gpio"; - }; - - power_led_pin: power-led-pin { - marvell,pins = "mpp64"; - marvell,function = "gpio"; - }; - - reset_button_pin: reset-button-pin { - marvell,pins = "mpp65"; - marvell,function = "gpio"; - }; -}; - -&nand_controller { - status = "okay"; - - nand@0 { - reg = <0>; - label = "pxa3xx_nand-0"; - nand-rb = <0>; - marvell,nand-keep-config; - nand-on-flash-bbt; - - /* Use Hardware BCH ECC */ - nand-ecc-strength = <4>; - nand-ecc-step-size = <512>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0x180000>; /* 1.5MB */ - read-only; - }; - - partition@180000 { - label = "u-boot-env"; - reg = <0x180000 0x20000>; /* 128KB */ - read-only; - }; - - partition@200000 { - label = "uImage"; - reg = <0x0200000 0x600000>; /* 6MB */ - }; - - partition@800000 { - label = "minirootfs"; - reg = <0x0800000 0x400000>; /* 4MB */ - }; - - /* Last MB is for the BBT, i.e. not writable */ - partition@c00000 { - label = "ubifs"; - reg = <0x0c00000 0x7400000>; /* 116MB */ - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/armada-370-rd.dts b/sys/gnu/dts/arm/armada-370-rd.dts deleted file mode 100644 index c910d157a68..00000000000 --- a/sys/gnu/dts/arm/armada-370-rd.dts +++ /dev/null @@ -1,258 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for Marvell Armada 370 Reference Design board - * (RD-88F6710-A1) - * - * Copied from arch/arm/boot/dts/armada-370-db.dts - * - * Copyright (C) 2013 Florian Fainelli - * - * Note: this Device Tree assumes that the bootloader has remapped the - * internal registers to 0xf1000000 (instead of the default - * 0xd0000000). The 0xf1000000 is the default used by the recent, - * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier - * boards were delivered with an older version of the bootloader that - * left internal registers mapped at 0xd0000000. If you are in this - * situation, you should either update your bootloader (preferred - * solution) or the below Device Tree should be adjusted. - */ - -/dts-v1/; -#include -#include -#include -#include "armada-370.dtsi" - -/ { - model = "Marvell Armada 370 Reference Design"; - compatible = "marvell,a370-rd", "marvell,armada370", "marvell,armada-370-xp"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x20000000>; /* 512 MB */ - }; - - soc { - ranges = ; - - internal-regs { - serial@12000 { - status = "okay"; - }; - sata@a0000 { - nr-ports = <2>; - status = "okay"; - }; - - ethernet@70000 { - status = "okay"; - phy = <&phy0>; - phy-mode = "sgmii"; - }; - ethernet@74000 { - pinctrl-0 = <&ge1_rgmii_pins>; - pinctrl-names = "default"; - status = "okay"; - phy-mode = "rgmii-id"; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - - mvsdio@d4000 { - pinctrl-0 = <&sdio_pins1>; - pinctrl-names = "default"; - status = "okay"; - /* No CD or WP GPIOs */ - broken-cd; - }; - - usb@50000 { - status = "okay"; - }; - - usb@51000 { - status = "okay"; - }; - - gpio-keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - button { - label = "Software Button"; - linux,code = ; - gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-fan { - compatible = "gpio-fan"; - gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>; - gpio-fan,speed-map = <0 0 3000 1>; - pinctrl-0 = <&fan_pins>; - pinctrl-names = "default"; - }; - - gpio_leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins>; - - sw_led { - label = "370rd:green:sw"; - gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - }; - }; - }; -}; - -&pciec { - status = "okay"; - - /* Internal mini-PCIe connector */ - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - - /* Internal mini-PCIe connector */ - pcie@2,0 { - /* Port 1, Lane 0 */ - status = "okay"; - }; -}; - -&mdio { - pinctrl-0 = <&mdio_pins>; - pinctrl-names = "default"; - phy0: ethernet-phy@0 { - reg = <0>; - }; - - switch: switch@10 { - compatible = "marvell,mv88e6085"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x10>; - interrupt-controller; - #interrupt-cells = <2>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "lan0"; - }; - - port@1 { - reg = <1>; - label = "lan1"; - }; - - port@2 { - reg = <2>; - label = "lan2"; - }; - - port@3 { - reg = <3>; - label = "lan3"; - }; - - port@5 { - reg = <5>; - label = "cpu"; - ethernet = <ð1>; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - switchphy0: switchphy@0 { - reg = <0>; - interrupt-parent = <&switch>; - interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; - }; - - switchphy1: switchphy@1 { - reg = <1>; - interrupt-parent = <&switch>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; - }; - - switchphy2: switchphy@2 { - reg = <2>; - interrupt-parent = <&switch>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; - }; - - switchphy3: switchphy@3 { - reg = <3>; - interrupt-parent = <&switch>; - interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - }; -}; - - -&pinctrl { - fan_pins: fan-pins { - marvell,pins = "mpp8"; - marvell,function = "gpio"; - }; - - led_pins: led-pins { - marvell,pins = "mpp32"; - marvell,function = "gpio"; - }; -}; - -&nand_controller { - status = "okay"; - - nand@0 { - reg = <0>; - label = "pxa3xx_nand-0"; - nand-rb = <0>; - marvell,nand-keep-config; - nand-on-flash-bbt; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "U-Boot"; - reg = <0 0x800000>; - }; - partition@800000 { - label = "Linux"; - reg = <0x800000 0x800000>; - }; - partition@1000000 { - label = "Filesystem"; - reg = <0x1000000 0x3f000000>; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/armada-370-seagate-nas-2bay.dts b/sys/gnu/dts/arm/armada-370-seagate-nas-2bay.dts deleted file mode 100644 index 8dd242e668e..00000000000 --- a/sys/gnu/dts/arm/armada-370-seagate-nas-2bay.dts +++ /dev/null @@ -1,33 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree file for Seagate NAS 2-Bay (Armada 370 SoC). - * - * Copyright (C) 2015 Seagate - * - * Author: Vincent Donnefort - */ - -/* - * Here are some information allowing to identify the device: - * - * Product name : Seagate NAS 2-Bay - * Code name (board/PCB) : Dart 2-Bay - * Model name (case sticker) : SRPD20 - * Material desc (product spec) : STCTxxxxxxx - */ - -/dts-v1/; -#include "armada-370-seagate-nas-xbay.dtsi" - -/ { - model = "Seagate NAS 2-Bay (Dart, SRPD20)"; - compatible = "seagate,dart-2", "marvell,armada370", "marvell,armada-370-xp"; - - gpio-fan { - gpio-fan,speed-map = - < 0 3 - 950 2 - 1400 1 - 1800 0>; - }; -}; diff --git a/sys/gnu/dts/arm/armada-370-seagate-nas-4bay.dts b/sys/gnu/dts/arm/armada-370-seagate-nas-4bay.dts deleted file mode 100644 index 3cf70c72c5c..00000000000 --- a/sys/gnu/dts/arm/armada-370-seagate-nas-4bay.dts +++ /dev/null @@ -1,131 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree file for Seagate NAS 4-Bay (Armada 370 SoC). - * - * Copyright (C) 2015 Seagate - * - * Author: Vincent Donnefort - */ - -/* - * Here are some information allowing to identify the device: - * - * Product name : Seagate NAS 4-Bay - * Code name (board/PCB) : Dart 4-Bay - * Model name (case sticker) : SRPD40 - * Material desc (product spec) : STCUxxxxxxx - */ - -/dts-v1/; -#include "armada-370-seagate-nas-xbay.dtsi" -#include - -/ { - model = "Seagate NAS 4-Bay (Dart, SRPD40)"; - compatible = "seagate,dart-4", "marvell,armada370", "marvell,armada-370-xp"; - - soc { - internal-regs { - ethernet@74000 { - status = "okay"; - pinctrl-0 = <&ge1_rgmii_pins>; - pinctrl-names = "default"; - phy = <&phy1>; - phy-mode = "rgmii-id"; - }; - - i2c@11000 { - /* I2C GPIO expander (PCA9554A) */ - pca9554: pca9554@21 { - compatible = "nxp,pca9554"; - reg = <0x21>; - #gpio-cells = <2>; - gpio-controller; - }; - }; - }; - }; - - regulators { - regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "SATA2 power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&pca9554 6 GPIO_ACTIVE_HIGH>; - }; - regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "SATA3 power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&pca9554 7 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio-leds { - red-sata2 { - label = "dart:red:sata2"; - gpios = <&pca9554 0 GPIO_ACTIVE_LOW>; - }; - red-sata3 { - label = "dart:red:sata3"; - gpios = <&pca9554 3 GPIO_ACTIVE_LOW>; - }; - }; - - leds-ns2 { - compatible = "lacie,ns2-leds"; - - white-sata2 { - label = "dart:white:sata2"; - cmd-gpio = <&pca9554 1 GPIO_ACTIVE_HIGH>; - slow-gpio = <&pca9554 2 GPIO_ACTIVE_HIGH>; - num-modes = <4>; - modes-map = ; - }; - white-sata3 { - label = "dart:white:sata3"; - cmd-gpio = <&pca9554 4 GPIO_ACTIVE_HIGH>; - slow-gpio = <&pca9554 5 GPIO_ACTIVE_HIGH>; - num-modes = <4>; - modes-map = ; - }; - }; - - gpio-fan { - gpio-fan,speed-map = - < 0 3 - 800 2 - 1050 1 - 1300 0>; - }; -}; - -&pciec { - /* SATA AHCI controller 88SE9170 */ - pcie@1,0 { - status = "okay"; - }; -}; - -&mdio { - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - diff --git a/sys/gnu/dts/arm/armada-370-seagate-nas-xbay.dtsi b/sys/gnu/dts/arm/armada-370-seagate-nas-xbay.dtsi deleted file mode 100644 index b52634ecf1d..00000000000 --- a/sys/gnu/dts/arm/armada-370-seagate-nas-xbay.dtsi +++ /dev/null @@ -1,239 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree common file for the Seagate NAS 2 and 4-bay (Armada 370 SoC). - * - * Copyright (C) 2015 Seagate - * - * Author: Vincent Donnefort - */ - -/* - * TODO: add support for the white SATA LEDs associated with HDD 0 and 1. - */ - -#include "armada-370.dtsi" -#include -#include - -/ { - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x20000000>; /* 512 MB */ - }; - - soc { - ranges = ; - - internal-regs { - serial@12000 { - status = "okay"; - }; - - sata@a0000 { - nr-ports = <2>; - status = "okay"; - }; - - ethernet@70000 { - status = "okay"; - pinctrl-0 = <&ge0_rgmii_pins>; - pinctrl-names = "default"; - phy = <&phy0>; - phy-mode = "rgmii-id"; - }; - - i2c@11000 { - status = "okay"; - pinctrl-0 = <&i2c0_pins>; - pinctrl-names = "default"; - clock-frequency = <100000>; - - /* RTC - NXP 8563T (second source) */ - rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - interrupts = <110>; - }; - /* RTC - MCP7940NT */ - rtc@6f { - compatible = "microchip,mcp7941x"; - reg = <0x6f>; - interrupts = <110>; - }; - }; - }; - - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - - regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "SATA0 power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio1 18 GPIO_ACTIVE_HIGH>; - }; - regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "SATA1 power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio-fan { - compatible = "gpio-fan"; - gpios = <&gpio2 0 GPIO_ACTIVE_HIGH - &gpio2 1 GPIO_ACTIVE_HIGH>; - }; - - gpio-keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - power { - label = "Power button"; - linux,code = ; - gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; - debounce-interval = <100>; - }; - backup { - label = "Backup button"; - linux,code = ; - gpios = <&gpio0 31 GPIO_ACTIVE_LOW>; - debounce-interval = <100>; - }; - reset { - label = "Reset Button"; - linux,code = ; - gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; - debounce-interval = <100>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - white-power { - label = "dart:white:power"; - gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "timer"; - - }; - red-power { - label = "dart:red:power"; - gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>; - }; - red-sata0 { - label = "dart:red:sata0"; - gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; - }; - red-sata1 { - label = "dart:red:sata1"; - gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; - }; - }; - - gpio_poweroff { - compatible = "gpio-poweroff"; - gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; - }; -}; - -&pciec { - status = "okay"; - - /* USB 3.0 bridge ASM1042A */ - pcie@2,0 { - status = "okay"; - }; -}; - - -&mdio { - pinctrl-0 = <&mdio_pins>; - pinctrl-names = "default"; - - phy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -&pinctrl { - pinctrl-0 = <&hdd0_led_sata_pin>, <&hdd1_led_sata_pin>; - pinctrl-names = "default"; - - hdd0_led_sata_pin: hdd0-led-sata-pin { - marvell,pins = "mpp48"; - marvell,function = "sata1"; - }; - hdd0_led_gpio_pin: hdd0-led-gpio-pin { - marvell,pins = "mpp48"; - marvell,function = "gpio"; - }; - hdd1_led_sata_pin: hdd1-led-sata-pin { - marvell,pins = "mpp57"; - marvell,function = "sata0"; - }; - hdd1_led_gpio_pin: hdd1-led-gpio-pin { - marvell,pins = "mpp57"; - marvell,function = "gpio"; - }; -}; - -&nand_controller { - status = "okay"; - - nand@0 { - reg = <0>; - label = "pxa3xx_nand-0"; - nand-rb = <0>; - marvell,nand-keep-config; - nand-on-flash-bbt; - nand-ecc-strength = <4>; - nand-ecc-step-size = <512>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x300000>; - }; - partition@300000 { - label = "device-tree"; - reg = <0x300000 0x20000>; - }; - partition@320000 { - label = "linux"; - reg = <0x320000 0x2000000>; - }; - partition@2320000 { - label = "rootfs"; - reg = <0x2320000 0xdce0000>; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/armada-370-seagate-personal-cloud-2bay.dts b/sys/gnu/dts/arm/armada-370-seagate-personal-cloud-2bay.dts deleted file mode 100644 index 5ee572dc924..00000000000 --- a/sys/gnu/dts/arm/armada-370-seagate-personal-cloud-2bay.dts +++ /dev/null @@ -1,48 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree file for Seagate Personal Cloud NAS 2-Bay (Armada 370 SoC). - * - * Copyright (C) 2015 Seagate - * - * Author: Simon Guinot - */ - -/* - * Here are some information allowing to identify the device: - * - * Product name : Seagate Personal Cloud 2-Bay - * Code name (board/PCB) : Cumulus Max - * Model name (case sticker) : SRN22C - * Material desc (product spec) : STCSxxxxxxx - */ - -/dts-v1/; -#include "armada-370-seagate-personal-cloud.dtsi" - -/ { - model = "Seagate Personal Cloud 2-Bay (Cumulus, SRN22C)"; - compatible = "seagate,cumulus-max", "marvell,armada370", "marvell,armada-370-xp"; - - soc { - internal-regs { - sata@a0000 { - status = "okay"; - nr-ports = <2>; - }; - }; - }; - - regulators { - regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "SATA1 power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/armada-370-seagate-personal-cloud.dts b/sys/gnu/dts/arm/armada-370-seagate-personal-cloud.dts deleted file mode 100644 index 578b54b39c8..00000000000 --- a/sys/gnu/dts/arm/armada-370-seagate-personal-cloud.dts +++ /dev/null @@ -1,34 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree file for Seagate Personal Cloud NAS (Armada 370 SoC). - * - * Copyright (C) 2015 Seagate - * - * Author: Simon Guinot - */ - -/* - * Here are some information allowing to identify the device: - * - * Product name : Seagate Personal Cloud - * Code name (board/PCB) : Cumulus - * Model name (case sticker) : SRN21C - * Material desc (product spec) : STCRxxxxxxx - */ - -/dts-v1/; -#include "armada-370-seagate-personal-cloud.dtsi" - -/ { - model = "Seagate Personal Cloud (Cumulus, SRN21C)"; - compatible = "seagate,cumulus", "marvell,armada370", "marvell,armada-370-xp"; - - soc { - internal-regs { - sata@a0000 { - status = "okay"; - nr-ports = <1>; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/armada-370-seagate-personal-cloud.dtsi b/sys/gnu/dts/arm/armada-370-seagate-personal-cloud.dtsi deleted file mode 100644 index a624b2371fb..00000000000 --- a/sys/gnu/dts/arm/armada-370-seagate-personal-cloud.dtsi +++ /dev/null @@ -1,175 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree common file for the Seagate Personal Cloud NAS 1 and 2-Bay - * (Armada 370 SoC). - * - * Copyright (C) 2015 Seagate - * - * Author: Simon Guinot - */ - -/* - * TODO: add support for the white SATA LED. - */ - -#include "armada-370.dtsi" -#include -#include - -/ { - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x20000000>; /* 512 MB */ - }; - - soc { - ranges = ; - - internal-regs { - coherency-fabric@20200 { - broken-idle; - }; - - serial@12000 { - status = "okay"; - }; - - ethernet@74000 { - status = "okay"; - pinctrl-0 = <&ge1_rgmii_pins>; - pinctrl-names = "default"; - phy = <&phy0>; - phy-mode = "rgmii-id"; - }; - - usb@50000 { - status = "okay"; - }; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "USB Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio1 27 GPIO_ACTIVE_LOW>; - }; - regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "SATA0 power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio1 18 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - power { - label = "Power button"; - linux,code = ; - gpios = <&gpio1 19 GPIO_ACTIVE_HIGH>; - debounce-interval = <100>; - }; - reset { - label = "Reset Button"; - linux,code = ; - gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; - debounce-interval = <100>; - }; - button { - label = "USB VBUS error"; - linux,code = ; - gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; - debounce-interval = <100>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - red-sata0 { - label = "cumulus:red:sata0"; - gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - - gpio_poweroff { - compatible = "gpio-poweroff"; - gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>; - }; -}; - -&pciec { - status = "okay"; - - /* USB 3.0 Bridge ASM1042A */ - pcie@1,0 { - status = "okay"; - }; -}; - -&mdio { - pinctrl-0 = <&mdio_pins>; - pinctrl-names = "default"; - - phy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -&pinctrl { - pinctrl-0 = <&sata_led_pin>; - pinctrl-names = "default"; - - sata_led_pin: sata-led-pin { - marvell,pins = "mpp60"; - marvell,function = "sata0"; - }; - gpio_led_pin: gpio-led-pin { - marvell,pins = "mpp60"; - marvell,function = "gpio"; - }; -}; - -&spi0 { - status = "okay"; - pinctrl-0 = <&spi0_pins2>; - pinctrl-names = "default"; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - /* MX25L8006E */ - compatible = "mxicy,mx25l8005", "jedec,spi-nor"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <50000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x100000>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/armada-370-synology-ds213j.dts b/sys/gnu/dts/arm/armada-370-synology-ds213j.dts deleted file mode 100644 index 64f2ce254fb..00000000000 --- a/sys/gnu/dts/arm/armada-370-synology-ds213j.dts +++ /dev/null @@ -1,312 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for Synology DS213j - * - * Copyright (C) 2014, Arnaud EBALARD - * - * Note: this Device Tree assumes that the bootloader has remapped the - * internal registers to 0xf1000000 (instead of the old 0xd0000000). - * The 0xf1000000 is the default used by the recent, DT-capable, U-Boot - * bootloaders provided by Marvell. It is used in recent versions of - * DSM software provided by Synology. Nonetheless, some earlier boards - * were delivered with an older version of u-boot that left internal - * registers mapped at 0xd0000000. If you have such a device you will - * not be able to directly boot a kernel based on this Device Tree. In - * that case, the preferred solution is to update your bootloader (e.g. - * by upgrading to latest version of DSM, or building a new one and - * installing it from u-boot prompt) or adjust the Devive Tree - * (s/0xf1000000/0xd0000000/ in 'ranges' below). - */ - -/dts-v1/; - -#include -#include -#include "armada-370.dtsi" - -/ { - model = "Synology DS213j"; - compatible = "synology,ds213j", "marvell,armada370", - "marvell,armada-370-xp"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x20000000>; /* 512 MB */ - }; - - soc { - ranges = ; - - internal-regs { - - /* RTC provided by Seiko S-35390A I2C RTC chip below */ - rtc@10300 { - status = "disabled"; - }; - - i2c@11000 { - compatible = "marvell,mv64xxx-i2c"; - pinctrl-0 = <&i2c0_pins>; - pinctrl-names = "default"; - clock-frequency = <400000>; - status = "okay"; - - /* Main device RTC chip */ - s35390a: s35390a@30 { - compatible = "sii,s35390a"; - reg = <0x30>; - }; - }; - - /* Connected to a header on device's PCB */ - serial@12000 { - status = "okay"; - }; - - /* Connected to a TI MSP430F2111 for power control */ - serial@12100 { - status = "okay"; - }; - - poweroff@12100 { - compatible = "synology,power-off"; - reg = <0x12100 0x100>; - clocks = <&coreclk 0>; - }; - - /* rear USB port, near reset button */ - usb@50000 { - status = "okay"; - }; - - /* rear USB port, near RJ45 port */ - usb@51000 { - status = "okay"; - }; - - ethernet@70000 { - status = "okay"; - phy = <&phy1>; - phy-mode = "sgmii"; - }; - - sata@a0000 { - nr-ports = <2>; - status = "okay"; - }; - }; - }; - - gpio-fan-32-38 { - status = "okay"; - compatible = "gpio-fan"; - pinctrl-0 = <&fan_ctrl_low_pin &fan_ctrl_mid_pin - &fan_ctrl_high_pin &fan_alarm_pin>; - pinctrl-names = "default"; - gpios = <&gpio1 31 GPIO_ACTIVE_HIGH - &gpio2 0 GPIO_ACTIVE_HIGH - &gpio2 1 GPIO_ACTIVE_HIGH>; - alarm-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; - gpio-fan,speed-map = < 0 0 - 1000 1 - 1150 2 - 1350 4 - 1500 3 - 1650 5 - 1750 6 - 1900 7 >; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&disk1_led_pin - &disk2_led_pin>; - pinctrl-names = "default"; - - disk1-led-amber { - label = "synology:amber:disk1"; - gpios = <&gpio0 31 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - - disk2-led-amber { - label = "synology:amber:disk2"; - gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&sata1_pwr_pin &sata2_pwr_pin>; - pinctrl-names = "default"; - - sata1_regulator: sata1-regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "SATA1 Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - startup-delay-us = <2000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; - }; - - sata2_regulator: sata2-regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "SATA2 Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - startup-delay-us = <4000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio1 30 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&mdio { - phy1: ethernet-phy@1 { /* Marvell 88E1512 */ - reg = <1>; - }; -}; - -&pinctrl { - disk1_led_pin: disk1-led-pin { - marvell,pins = "mpp31"; - marvell,function = "gpio"; - }; - - disk2_led_pin: disk2-led-pin { - marvell,pins = "mpp32"; - marvell,function = "gpio"; - }; - - sata1_pwr_pin: sata1-pwr-pin { - marvell,pins = "mpp37"; - marvell,function = "gpio"; - }; - - sata2_pwr_pin: sata2-pwr-pin { - marvell,pins = "mpp62"; - marvell,function = "gpio"; - }; - - sata1_pres_pin: sata1-pres-pin { - marvell,pins = "mpp60"; - marvell,function = "gpio"; - }; - - sata2_pres_pin: sata2-pres-pin { - marvell,pins = "mpp48"; - marvell,function = "gpio"; - }; - - syno_id_bit0_pin: syno-id-bit0-pin { - marvell,pins = "mpp55"; - marvell,function = "gpio"; - }; - - syno_id_bit1_pin: syno-id-bit1-pin { - marvell,pins = "mpp56"; - marvell,function = "gpio"; - }; - - syno_id_bit2_pin: syno-id-bit2-pin { - marvell,pins = "mpp57"; - marvell,function = "gpio"; - }; - - syno_id_bit3_pin: syno-id-bit3-pin { - marvell,pins = "mpp58"; - marvell,function = "gpio"; - }; - - fan_ctrl_low_pin: fan-ctrl-low-pin { - marvell,pins = "mpp65"; - marvell,function = "gpio"; - }; - - fan_ctrl_mid_pin: fan-ctrl-mid-pin { - marvell,pins = "mpp64"; - marvell,function = "gpio"; - }; - - fan_ctrl_high_pin: fan-ctrl-high-pin { - marvell,pins = "mpp63"; - marvell,function = "gpio"; - }; - - fan_alarm_pin: fan-alarm-pin { - marvell,pins = "mpp38"; - marvell,function = "gpio"; - }; -}; - -&spi0 { - status = "okay"; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "micron,n25q064", "jedec,spi-nor"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <20000000>; - - /* - * Warning! - * - * Synology u-boot uses its compiled-in environment - * and it seems Synology did not care to change u-boot - * default configuration in order to allow saving a - * modified environment at a sensible location. So, - * if you do a 'saveenv' under u-boot, your modified - * environment will be saved at 1MB after the start - * of the flash, i.e. in the middle of the uImage. - * For that reason, it is strongly advised not to - * change the default environment, unless you know - * what you are doing. - */ - partition@0 { /* u-boot */ - label = "RedBoot"; - reg = <0x00000000 0x000c0000>; /* 768KB */ - }; - - partition@c0000 { /* uImage */ - label = "zImage"; - reg = <0x000c0000 0x002d0000>; /* 2880KB */ - }; - - partition@390000 { /* uInitramfs */ - label = "rd.gz"; - reg = <0x00390000 0x00440000>; /* 4250KB */ - }; - - partition@7d0000 { /* MAC address and serial number */ - label = "vendor"; - reg = <0x007d0000 0x00010000>; /* 64KB */ - }; - - partition@7e0000 { - label = "RedBoot config"; - reg = <0x007e0000 0x00010000>; /* 64KB */ - }; - - partition@7f0000 { - label = "FIS directory"; - reg = <0x007f0000 0x00010000>; /* 64KB */ - }; - }; -}; diff --git a/sys/gnu/dts/arm/armada-370-xp.dtsi b/sys/gnu/dts/arm/armada-370-xp.dtsi deleted file mode 100644 index c15f5e92f97..00000000000 --- a/sys/gnu/dts/arm/armada-370-xp.dtsi +++ /dev/null @@ -1,315 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree Include file for Marvell Armada 370 and Armada XP SoC - * - * Copyright (C) 2012 Marvell - * - * Lior Amsalem - * Gregory CLEMENT - * Thomas Petazzoni - * Ben Dooks - * - * This file contains the definitions that are common to the Armada - * 370 and Armada XP SoC. - */ - -#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) - -/ { - model = "Marvell Armada 370 and XP SoC"; - compatible = "marvell,armada-370-xp"; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu@0 { - compatible = "marvell,sheeva-v7"; - device_type = "cpu"; - reg = <0>; - }; - }; - - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts-extended = <&mpic 3>; - }; - - soc { - #address-cells = <2>; - #size-cells = <1>; - controller = <&mbusc>; - interrupt-parent = <&mpic>; - pcie-mem-aperture = <0xf8000000 0x7e00000>; - pcie-io-aperture = <0xffe00000 0x100000>; - - devbus_bootcs: devbus-bootcs { - compatible = "marvell,mvebu-devbus"; - reg = ; - ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - devbus_cs0: devbus-cs0 { - compatible = "marvell,mvebu-devbus"; - reg = ; - ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - devbus_cs1: devbus-cs1 { - compatible = "marvell,mvebu-devbus"; - reg = ; - ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - devbus_cs2: devbus-cs2 { - compatible = "marvell,mvebu-devbus"; - reg = ; - ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - devbus_cs3: devbus-cs3 { - compatible = "marvell,mvebu-devbus"; - reg = ; - ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - internal-regs { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>; - - rtc: rtc@10300 { - compatible = "marvell,orion-rtc"; - reg = <0x10300 0x20>; - interrupts = <50>; - }; - - i2c0: i2c@11000 { - compatible = "marvell,mv64xxx-i2c"; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <31>; - timeout-ms = <1000>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - i2c1: i2c@11100 { - compatible = "marvell,mv64xxx-i2c"; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <32>; - timeout-ms = <1000>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - uart0: serial@12000 { - compatible = "snps,dw-apb-uart"; - reg = <0x12000 0x100>; - reg-shift = <2>; - interrupts = <41>; - reg-io-width = <1>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - uart1: serial@12100 { - compatible = "snps,dw-apb-uart"; - reg = <0x12100 0x100>; - reg-shift = <2>; - interrupts = <42>; - reg-io-width = <1>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - pinctrl: pin-ctrl@18000 { - reg = <0x18000 0x38>; - }; - - coredivclk: corediv-clock@18740 { - compatible = "marvell,armada-370-corediv-clock"; - reg = <0x18740 0xc>; - #clock-cells = <1>; - clocks = <&mainpll>; - clock-output-names = "nand"; - }; - - mbusc: mbus-controller@20000 { - compatible = "marvell,mbus-controller"; - reg = <0x20000 0x100>, <0x20180 0x20>, - <0x20250 0x8>; - }; - - mpic: interrupt-controller@20a00 { - compatible = "marvell,mpic"; - #interrupt-cells = <1>; - #size-cells = <1>; - interrupt-controller; - msi-controller; - }; - - coherencyfab: coherency-fabric@20200 { - compatible = "marvell,coherency-fabric"; - reg = <0x20200 0xb0>, <0x21010 0x1c>; - }; - - timer: timer@20300 { - reg = <0x20300 0x30>, <0x21040 0x30>; - interrupts = <37>, <38>, <39>, <40>, <5>, <6>; - }; - - watchdog: watchdog@20300 { - reg = <0x20300 0x34>, <0x20704 0x4>; - }; - - cpurst: cpurst@20800 { - compatible = "marvell,armada-370-cpu-reset"; - reg = <0x20800 0x8>; - }; - - pmsu: pmsu@22000 { - compatible = "marvell,armada-370-pmsu"; - reg = <0x22000 0x1000>; - }; - - usb0: usb@50000 { - compatible = "marvell,orion-ehci"; - reg = <0x50000 0x500>; - interrupts = <45>; - status = "disabled"; - }; - - usb1: usb@51000 { - compatible = "marvell,orion-ehci"; - reg = <0x51000 0x500>; - interrupts = <46>; - status = "disabled"; - }; - - eth0: ethernet@70000 { - reg = <0x70000 0x4000>; - interrupts = <8>; - clocks = <&gateclk 4>; - status = "disabled"; - }; - - mdio: mdio@72004 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "marvell,orion-mdio"; - reg = <0x72004 0x4>; - clocks = <&gateclk 4>; - }; - - eth1: ethernet@74000 { - reg = <0x74000 0x4000>; - interrupts = <10>; - clocks = <&gateclk 3>; - status = "disabled"; - }; - - sata: sata@a0000 { - compatible = "marvell,armada-370-sata"; - reg = <0xa0000 0x5000>; - interrupts = <55>; - clocks = <&gateclk 15>, <&gateclk 30>; - clock-names = "0", "1"; - status = "disabled"; - }; - - nand_controller: nand-controller@d0000 { - compatible = "marvell,armada370-nand-controller"; - reg = <0xd0000 0x54>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <113>; - clocks = <&coredivclk 0>; - status = "disabled"; - }; - - sdio: mvsdio@d4000 { - compatible = "marvell,orion-sdio"; - reg = <0xd4000 0x200>; - interrupts = <54>; - clocks = <&gateclk 17>; - bus-width = <4>; - cap-sdio-irq; - cap-sd-highspeed; - cap-mmc-highspeed; - status = "disabled"; - }; - }; - - spi0: spi@10600 { - reg = , /* control */ - , /* CS0 */ - , /* CS1 */ - , /* CS2 */ - , /* CS3 */ - , /* CS4 */ - , /* CS5 */ - , /* CS6 */ - ; /* CS7 */ - #address-cells = <1>; - #size-cells = <0>; - cell-index = <0>; - interrupts = <30>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - spi1: spi@10680 { - reg = , /* control */ - , /* CS0 */ - , /* CS1 */ - , /* CS2 */ - , /* CS3 */ - , /* CS4 */ - , /* CS5 */ - , /* CS6 */ - ; /* CS7 */ - #address-cells = <1>; - #size-cells = <0>; - cell-index = <1>; - interrupts = <92>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - }; - - clocks { - /* 2 GHz fixed main PLL */ - mainpll: mainpll { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <2000000000>; - }; - }; - }; diff --git a/sys/gnu/dts/arm/armada-370.dtsi b/sys/gnu/dts/arm/armada-370.dtsi deleted file mode 100644 index 46e6d3ed8f3..00000000000 --- a/sys/gnu/dts/arm/armada-370.dtsi +++ /dev/null @@ -1,419 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree Include file for Marvell Armada 370 family SoC - * - * Copyright (C) 2012 Marvell - * - * Lior Amsalem - * Gregory CLEMENT - * Thomas Petazzoni - * - * Contains definitions specific to the Armada 370 SoC that are not - * common to all Armada SoCs. - */ - -#include "armada-370-xp.dtsi" - -/ { - #address-cells = <1>; - #size-cells = <1>; - - model = "Marvell Armada 370 family SoC"; - compatible = "marvell,armada370", "marvell,armada-370-xp"; - - aliases { - gpio0 = &gpio0; - gpio1 = &gpio1; - gpio2 = &gpio2; - }; - - soc { - compatible = "marvell,armada370-mbus", "simple-bus"; - - bootrom { - compatible = "marvell,bootrom"; - reg = ; - }; - - pciec: pcie@82000000 { - compatible = "marvell,armada-370-pcie"; - status = "disabled"; - device_type = "pci"; - - #address-cells = <3>; - #size-cells = <2>; - - msi-parent = <&mpic>; - bus-range = <0x00 0xff>; - - ranges = - <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 - 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 - 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ - 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ - 0x82000000 0x2 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */ - 0x81000000 0x2 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */>; - - pcie0: pcie@1,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; - reg = <0x0800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 - 0x81000000 0 0 0x81000000 0x1 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 58>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 5>; - status = "disabled"; - }; - - pcie2: pcie@2,0 { - device_type = "pci"; - assigned-addresses = <0x82002800 0 0x80000 0 0x2000>; - reg = <0x1000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 - 0x81000000 0 0 0x81000000 0x2 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 62>; - marvell,pcie-port = <1>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 9>; - status = "disabled"; - }; - }; - - internal-regs { - L2: l2-cache@8000 { - compatible = "marvell,aurora-outer-cache"; - reg = <0x08000 0x1000>; - cache-id-part = <0x100>; - cache-level = <2>; - cache-unified; - wt-override; - }; - - gpio0: gpio@18100 { - compatible = "marvell,armada-370-gpio", - "marvell,orion-gpio"; - reg = <0x18100 0x40>, <0x181c0 0x08>; - reg-names = "gpio", "pwm"; - ngpios = <32>; - gpio-controller; - #gpio-cells = <2>; - #pwm-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <82>, <83>, <84>, <85>; - clocks = <&coreclk 0>; - }; - - gpio1: gpio@18140 { - compatible = "marvell,armada-370-gpio", - "marvell,orion-gpio"; - reg = <0x18140 0x40>, <0x181c8 0x08>; - reg-names = "gpio", "pwm"; - ngpios = <32>; - gpio-controller; - #gpio-cells = <2>; - #pwm-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <87>, <88>, <89>, <90>; - clocks = <&coreclk 0>; - }; - - gpio2: gpio@18180 { - compatible = "marvell,armada-370-gpio", - "marvell,orion-gpio"; - reg = <0x18180 0x40>; - ngpios = <2>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <91>; - }; - - - systemc: system-controller@18200 { - compatible = "marvell,armada-370-xp-system-controller"; - reg = <0x18200 0x100>; - }; - - gateclk: clock-gating-control@18220 { - compatible = "marvell,armada-370-gating-clock"; - reg = <0x18220 0x4>; - clocks = <&coreclk 0>; - #clock-cells = <1>; - }; - - coreclk: mvebu-sar@18230 { - compatible = "marvell,armada-370-core-clock"; - reg = <0x18230 0x08>; - #clock-cells = <1>; - }; - - thermal: thermal@18300 { - compatible = "marvell,armada370-thermal"; - reg = <0x18300 0x4 - 0x18304 0x4>; - status = "okay"; - }; - - sscg: sscg@18330 { - reg = <0x18330 0x4>; - }; - - cpuconf: cpu-config@21000 { - compatible = "marvell,armada-370-cpu-config"; - reg = <0x21000 0x8>; - }; - - audio_controller: audio-controller@30000 { - #sound-dai-cells = <1>; - compatible = "marvell,armada370-audio"; - reg = <0x30000 0x4000>; - interrupts = <93>; - clocks = <&gateclk 0>; - clock-names = "internal"; - status = "disabled"; - }; - - xor0: xor@60800 { - compatible = "marvell,orion-xor"; - reg = <0x60800 0x100 - 0x60A00 0x100>; - status = "okay"; - - xor00 { - interrupts = <51>; - dmacap,memcpy; - dmacap,xor; - }; - xor01 { - interrupts = <52>; - dmacap,memcpy; - dmacap,xor; - dmacap,memset; - }; - }; - - xor1: xor@60900 { - compatible = "marvell,orion-xor"; - reg = <0x60900 0x100 - 0x60b00 0x100>; - status = "okay"; - - xor10 { - interrupts = <94>; - dmacap,memcpy; - dmacap,xor; - }; - xor11 { - interrupts = <95>; - dmacap,memcpy; - dmacap,xor; - dmacap,memset; - }; - }; - - cesa: crypto@90000 { - compatible = "marvell,armada-370-crypto"; - reg = <0x90000 0x10000>; - reg-names = "regs"; - interrupts = <48>; - clocks = <&gateclk 23>; - clock-names = "cesa0"; - marvell,crypto-srams = <&crypto_sram>; - marvell,crypto-sram-size = <0x7e0>; - }; - }; - - crypto_sram: sa-sram { - compatible = "mmio-sram"; - reg = ; - reg-names = "sram"; - clocks = <&gateclk 23>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 MBUS_ID(0x09, 0x01) 0 0x800>; - - /* - * The Armada 370 has an erratum preventing the use of - * the standard workflow for CPU idle support (relying - * on the BootROM code to enter/exit idle state). - * Reserve some amount of the crypto SRAM to put the - * cpuidle workaround. - */ - idle-sram@0 { - reg = <0x0 0x20>; - }; - }; - }; -}; - -/* - * Default UART pinctrl setting without RTS/CTS, can be overwritten on - * board level if a different configuration is used. - */ - -&uart0 { - pinctrl-0 = <&uart0_pins>; - pinctrl-names = "default"; -}; - -&uart1 { - pinctrl-0 = <&uart1_pins>; - pinctrl-names = "default"; -}; - -&i2c0 { - reg = <0x11000 0x20>; -}; - -&i2c1 { - reg = <0x11100 0x20>; -}; - -&mpic { - reg = <0x20a00 0x1d0>, <0x21870 0x58>; -}; - -&timer { - compatible = "marvell,armada-370-timer"; - clocks = <&coreclk 2>; -}; - -&watchdog { - compatible = "marvell,armada-370-wdt"; - clocks = <&coreclk 2>; -}; - -&usb0 { - clocks = <&coreclk 0>; -}; - -&usb1 { - clocks = <&coreclk 0>; -}; - -ð0 { - compatible = "marvell,armada-370-neta"; -}; - -ð1 { - compatible = "marvell,armada-370-neta"; -}; - -&pinctrl { - compatible = "marvell,mv88f6710-pinctrl"; - - spi0_pins1: spi0-pins1 { - marvell,pins = "mpp33", "mpp34", - "mpp35", "mpp36"; - marvell,function = "spi0"; - }; - - spi0_pins2: spi0_pins2 { - marvell,pins = "mpp32", "mpp63", - "mpp64", "mpp65"; - marvell,function = "spi0"; - }; - - spi1_pins: spi1-pins { - marvell,pins = "mpp49", "mpp50", - "mpp51", "mpp52"; - marvell,function = "spi1"; - }; - - uart0_pins: uart0-pins { - marvell,pins = "mpp0", "mpp1"; - marvell,function = "uart0"; - }; - - uart1_pins: uart1-pins { - marvell,pins = "mpp41", "mpp42"; - marvell,function = "uart1"; - }; - - sdio_pins1: sdio-pins1 { - marvell,pins = "mpp9", "mpp11", "mpp12", - "mpp13", "mpp14", "mpp15"; - marvell,function = "sd0"; - }; - - sdio_pins2: sdio-pins2 { - marvell,pins = "mpp47", "mpp48", "mpp49", - "mpp50", "mpp51", "mpp52"; - marvell,function = "sd0"; - }; - - sdio_pins3: sdio-pins3 { - marvell,pins = "mpp48", "mpp49", "mpp50", - "mpp51", "mpp52", "mpp53"; - marvell,function = "sd0"; - }; - - i2c0_pins: i2c0-pins { - marvell,pins = "mpp2", "mpp3"; - marvell,function = "i2c0"; - }; - - i2s_pins1: i2s-pins1 { - marvell,pins = "mpp5", "mpp6", "mpp7", - "mpp8", "mpp9", "mpp10", - "mpp12", "mpp13"; - marvell,function = "audio"; - }; - - i2s_pins2: i2s-pins2 { - marvell,pins = "mpp49", "mpp47", "mpp50", - "mpp59", "mpp57", "mpp61", - "mpp62", "mpp60", "mpp58"; - marvell,function = "audio"; - }; - - mdio_pins: mdio-pins { - marvell,pins = "mpp17", "mpp18"; - marvell,function = "ge"; - }; - - ge0_rgmii_pins: ge0-rgmii-pins { - marvell,pins = "mpp5", "mpp6", "mpp7", "mpp8", - "mpp9", "mpp10", "mpp11", "mpp12", - "mpp13", "mpp14", "mpp15", "mpp16"; - marvell,function = "ge0"; - }; - - ge1_rgmii_pins: ge1-rgmii-pins { - marvell,pins = "mpp19", "mpp20", "mpp21", "mpp22", - "mpp23", "mpp24", "mpp25", "mpp26", - "mpp27", "mpp28", "mpp29", "mpp30"; - marvell,function = "ge1"; - }; -}; - -/* - * Default SPI pinctrl setting, can be overwritten on - * board level if a different configuration is used. - */ -&spi0 { - compatible = "marvell,armada-370-spi", "marvell,orion-spi"; - pinctrl-0 = <&spi0_pins1>; - pinctrl-names = "default"; -}; - -&spi1 { - compatible = "marvell,armada-370-spi", "marvell,orion-spi"; - pinctrl-0 = <&spi1_pins>; - pinctrl-names = "default"; -}; diff --git a/sys/gnu/dts/arm/armada-375-db.dts b/sys/gnu/dts/arm/armada-375-db.dts deleted file mode 100644 index 0e679465cbb..00000000000 --- a/sys/gnu/dts/arm/armada-375-db.dts +++ /dev/null @@ -1,182 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for Marvell Armada 375 evaluation board - * (DB-88F6720) - * - * Copyright (C) 2014 Marvell - * - * Gregory CLEMENT - * Thomas Petazzoni - */ - -/dts-v1/; -#include -#include "armada-375.dtsi" - -/ { - model = "Marvell Armada 375 Development Board"; - compatible = "marvell,a375-db", "marvell,armada375"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x40000000>; /* 1 GB */ - }; - - soc { - ranges = ; - - }; -}; -&pciec { - status = "okay"; -}; - -/* - * The two PCIe units are accessible through - * standard PCIe slots on the board. - */ -&pcie0 { - /* Port 0, Lane 0 */ - status = "okay"; -}; - -&pcie1 { - /* Port 1, Lane 0 */ - status = "okay"; -}; - - -&spi0 { - pinctrl-0 = <&spi0_pins>; - pinctrl-names = "default"; - - /* - * SPI conflicts with NAND, so we disable it here, and - * select NAND as the enabled device by default. - */ - - status = "disabled"; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "n25q128a13", "jedec,spi-nor"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <108000000>; - }; -}; - -&i2c0 { - status = "okay"; - clock-frequency = <100000>; - pinctrl-0 = <&i2c0_pins>; - pinctrl-names = "default"; -}; - -&i2c1 { - status = "okay"; - clock-frequency = <100000>; - pinctrl-0 = <&i2c1_pins>; - pinctrl-names = "default"; -}; - -&uart0 { - status = "okay"; -}; - -&pinctrl { - sdio_st_pins: sdio-st-pins { - marvell,pins = "mpp44", "mpp45"; - marvell,function = "gpio"; - }; -}; - -&sata { - status = "okay"; - nr-ports = <2>; -}; - -&nand_controller { - status = "okay"; - pinctrl-0 = <&nand_pins>; - pinctrl-names = "default"; - - nand@0 { - reg = <0>; - label = "pxa3xx_nand-0"; - nand-rb = <0>; - marvell,nand-keep-config; - nand-on-flash-bbt; - nand-ecc-strength = <4>; - nand-ecc-step-size = <512>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "U-Boot"; - reg = <0 0x800000>; - }; - partition@800000 { - label = "Linux"; - reg = <0x800000 0x800000>; - }; - partition@1000000 { - label = "Filesystem"; - reg = <0x1000000 0x3f000000>; - }; - }; - }; -}; - -&usb1 { - status = "okay"; -}; - -&usb2 { - status = "okay"; -}; - -&sdio { - pinctrl-0 = <&sdio_pins &sdio_st_pins>; - pinctrl-names = "default"; - status = "okay"; - cd-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; - wp-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; -}; - -&mdio { - phy0: ethernet-phy@0 { - reg = <0>; - }; - - phy3: ethernet-phy@3 { - reg = <3>; - }; -}; - -ðernet { - status = "okay"; -}; - - -ð0 { - status = "okay"; - phy = <&phy0>; - phy-mode = "rgmii-id"; -}; - -ð1 { - status = "okay"; - phy = <&phy3>; - phy-mode = "gmii"; -}; diff --git a/sys/gnu/dts/arm/armada-375.dtsi b/sys/gnu/dts/arm/armada-375.dtsi deleted file mode 100644 index 2932a29ae27..00000000000 --- a/sys/gnu/dts/arm/armada-375.dtsi +++ /dev/null @@ -1,623 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree Include file for Marvell Armada 375 family SoC - * - * Copyright (C) 2014 Marvell - * - * Gregory CLEMENT - * Thomas Petazzoni - */ - -#include -#include -#include - -#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) - -/ { - #address-cells = <1>; - #size-cells = <1>; - - model = "Marvell Armada 375 family SoC"; - compatible = "marvell,armada375"; - - aliases { - gpio0 = &gpio0; - gpio1 = &gpio1; - gpio2 = &gpio2; - serial0 = &uart0; - serial1 = &uart1; - }; - - clocks { - /* 1 GHz fixed main PLL */ - mainpll: mainpll { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <1000000000>; - }; - /* 25 MHz reference crystal */ - refclk: oscillator { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "marvell,armada-375-smp"; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - }; - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <1>; - }; - }; - - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts-extended = <&mpic 3>; - }; - - soc { - compatible = "marvell,armada375-mbus", "simple-bus"; - #address-cells = <2>; - #size-cells = <1>; - controller = <&mbusc>; - interrupt-parent = <&gic>; - pcie-mem-aperture = <0xe0000000 0x8000000>; - pcie-io-aperture = <0xe8000000 0x100000>; - - bootrom { - compatible = "marvell,bootrom"; - reg = ; - }; - - devbus_bootcs: devbus-bootcs { - compatible = "marvell,mvebu-devbus"; - reg = ; - ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - devbus_cs0: devbus-cs0 { - compatible = "marvell,mvebu-devbus"; - reg = ; - ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - devbus_cs1: devbus-cs1 { - compatible = "marvell,mvebu-devbus"; - reg = ; - ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - devbus_cs2: devbus-cs2 { - compatible = "marvell,mvebu-devbus"; - reg = ; - ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - devbus_cs3: devbus-cs3 { - compatible = "marvell,mvebu-devbus"; - reg = ; - ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - internal-regs { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>; - - L2: cache-controller@8000 { - compatible = "arm,pl310-cache"; - reg = <0x8000 0x1000>; - cache-unified; - cache-level = <2>; - arm,double-linefill-incr = <0>; - arm,double-linefill-wrap = <0>; - arm,double-linefill = <0>; - prefetch-data = <1>; - }; - - scu: scu@c000 { - compatible = "arm,cortex-a9-scu"; - reg = <0xc000 0x58>; - }; - - timer0: timer@c600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0xc600 0x20>; - interrupts = ; - clocks = <&coreclk 2>; - }; - - gic: interrupt-controller@d000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #size-cells = <0>; - interrupt-controller; - reg = <0xd000 0x1000>, - <0xc100 0x100>; - }; - - mdio: mdio@c0054 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "marvell,orion-mdio"; - reg = <0xc0054 0x4>; - clocks = <&gateclk 19>; - }; - - /* Network controller */ - ethernet: ethernet@f0000 { - compatible = "marvell,armada-375-pp2"; - reg = <0xf0000 0xa000>, /* Packet Processor regs */ - <0xc0000 0x3060>, /* LMS regs */ - <0xc4000 0x100>, /* eth0 regs */ - <0xc5000 0x100>; /* eth1 regs */ - clocks = <&gateclk 3>, <&gateclk 19>; - clock-names = "pp_clk", "gop_clk"; - status = "disabled"; - - eth0: eth0 { - interrupts = ; - port-id = <0>; - status = "disabled"; - }; - - eth1: eth1 { - interrupts = ; - port-id = <1>; - status = "disabled"; - }; - }; - - rtc: rtc@10300 { - compatible = "marvell,orion-rtc"; - reg = <0x10300 0x20>; - interrupts = ; - }; - - spi0: spi@10600 { - compatible = "marvell,armada-375-spi", - "marvell,orion-spi"; - reg = <0x10600 0x50>; - #address-cells = <1>; - #size-cells = <0>; - cell-index = <0>; - interrupts = ; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - spi1: spi@10680 { - compatible = "marvell,armada-375-spi", - "marvell,orion-spi"; - reg = <0x10680 0x50>; - #address-cells = <1>; - #size-cells = <0>; - cell-index = <1>; - interrupts = ; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - i2c0: i2c@11000 { - compatible = "marvell,mv64xxx-i2c"; - reg = <0x11000 0x20>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - timeout-ms = <1000>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - i2c1: i2c@11100 { - compatible = "marvell,mv64xxx-i2c"; - reg = <0x11100 0x20>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - timeout-ms = <1000>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - uart0: serial@12000 { - compatible = "snps,dw-apb-uart"; - reg = <0x12000 0x100>; - reg-shift = <2>; - interrupts = ; - reg-io-width = <1>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - uart1: serial@12100 { - compatible = "snps,dw-apb-uart"; - reg = <0x12100 0x100>; - reg-shift = <2>; - interrupts = ; - reg-io-width = <1>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - pinctrl: pinctrl@18000 { - compatible = "marvell,mv88f6720-pinctrl"; - reg = <0x18000 0x24>; - - i2c0_pins: i2c0-pins { - marvell,pins = "mpp14", "mpp15"; - marvell,function = "i2c0"; - }; - - i2c1_pins: i2c1-pins { - marvell,pins = "mpp61", "mpp62"; - marvell,function = "i2c1"; - }; - - nand_pins: nand-pins { - marvell,pins = "mpp0", "mpp1", "mpp2", - "mpp3", "mpp4", "mpp5", - "mpp6", "mpp7", "mpp8", - "mpp9", "mpp10", "mpp11", - "mpp12", "mpp13"; - marvell,function = "nand"; - }; - - sdio_pins: sdio-pins { - marvell,pins = "mpp24", "mpp25", "mpp26", - "mpp27", "mpp28", "mpp29"; - marvell,function = "sd"; - }; - - spi0_pins: spi0-pins { - marvell,pins = "mpp0", "mpp1", "mpp4", - "mpp5", "mpp8", "mpp9"; - marvell,function = "spi0"; - }; - }; - - gpio0: gpio@18100 { - compatible = "marvell,orion-gpio"; - reg = <0x18100 0x40>; - ngpios = <32>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = , - , - , - ; - }; - - gpio1: gpio@18140 { - compatible = "marvell,orion-gpio"; - reg = <0x18140 0x40>; - ngpios = <32>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = , - , - , - ; - }; - - gpio2: gpio@18180 { - compatible = "marvell,orion-gpio"; - reg = <0x18180 0x40>; - ngpios = <3>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = ; - }; - - systemc: system-controller@18200 { - compatible = "marvell,armada-375-system-controller"; - reg = <0x18200 0x100>; - }; - - gateclk: clock-gating-control@18220 { - compatible = "marvell,armada-375-gating-clock"; - reg = <0x18220 0x4>; - clocks = <&coreclk 0>; - #clock-cells = <1>; - }; - - usbcluster: usb-cluster@18400 { - compatible = "marvell,armada-375-usb-cluster"; - reg = <0x18400 0x4>; - #phy-cells = <1>; - }; - - mbusc: mbus-controller@20000 { - compatible = "marvell,mbus-controller"; - reg = <0x20000 0x100>, <0x20180 0x20>; - }; - - mpic: interrupt-controller@20a00 { - compatible = "marvell,mpic"; - reg = <0x20a00 0x2d0>, <0x21070 0x58>; - #interrupt-cells = <1>; - #size-cells = <1>; - interrupt-controller; - msi-controller; - interrupts = ; - }; - - timer1: timer@20300 { - compatible = "marvell,armada-375-timer", "marvell,armada-370-timer"; - reg = <0x20300 0x30>, <0x21040 0x30>; - interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, - <&mpic 5>, - <&mpic 6>; - clocks = <&coreclk 0>, <&refclk>; - clock-names = "nbclk", "fixed"; - }; - - watchdog: watchdog@20300 { - compatible = "marvell,armada-375-wdt"; - reg = <0x20300 0x34>, <0x20704 0x4>, <0x18254 0x4>; - clocks = <&coreclk 0>, <&refclk>; - clock-names = "nbclk", "fixed"; - }; - - cpurst: cpurst@20800 { - compatible = "marvell,armada-370-cpu-reset"; - reg = <0x20800 0x10>; - }; - - coherencyfab: coherency-fabric@21010 { - compatible = "marvell,armada-375-coherency-fabric"; - reg = <0x21010 0x1c>; - }; - - usb0: usb@50000 { - compatible = "marvell,orion-ehci"; - reg = <0x50000 0x500>; - interrupts = ; - clocks = <&gateclk 18>; - phys = <&usbcluster PHY_TYPE_USB2>; - phy-names = "usb"; - status = "disabled"; - }; - - usb1: usb@54000 { - compatible = "marvell,orion-ehci"; - reg = <0x54000 0x500>; - interrupts = ; - clocks = <&gateclk 26>; - status = "disabled"; - }; - - usb2: usb3@58000 { - compatible = "marvell,armada-375-xhci"; - reg = <0x58000 0x20000>,<0x5b880 0x80>; - interrupts = ; - clocks = <&gateclk 16>; - phys = <&usbcluster PHY_TYPE_USB3>; - phy-names = "usb"; - status = "disabled"; - }; - - xor0: xor@60800 { - compatible = "marvell,orion-xor"; - reg = <0x60800 0x100 - 0x60A00 0x100>; - clocks = <&gateclk 22>; - status = "okay"; - - xor00 { - interrupts = ; - dmacap,memcpy; - dmacap,xor; - }; - xor01 { - interrupts = ; - dmacap,memcpy; - dmacap,xor; - dmacap,memset; - }; - }; - - xor1: xor@60900 { - compatible = "marvell,orion-xor"; - reg = <0x60900 0x100 - 0x60b00 0x100>; - clocks = <&gateclk 23>; - status = "okay"; - - xor10 { - interrupts = ; - dmacap,memcpy; - dmacap,xor; - }; - xor11 { - interrupts = ; - dmacap,memcpy; - dmacap,xor; - dmacap,memset; - }; - }; - - cesa: crypto@90000 { - compatible = "marvell,armada-375-crypto"; - reg = <0x90000 0x10000>; - reg-names = "regs"; - interrupts = , - ; - clocks = <&gateclk 30>, <&gateclk 31>, - <&gateclk 28>, <&gateclk 29>; - clock-names = "cesa0", "cesa1", - "cesaz0", "cesaz1"; - marvell,crypto-srams = <&crypto_sram0>, - <&crypto_sram1>; - marvell,crypto-sram-size = <0x800>; - }; - - sata: sata@a0000 { - compatible = "marvell,armada-370-sata"; - reg = <0xa0000 0x5000>; - interrupts = ; - clocks = <&gateclk 14>, <&gateclk 20>; - clock-names = "0", "1"; - status = "disabled"; - }; - - nand_controller: nand-controller@d0000 { - compatible = "marvell,armada370-nand-controller"; - reg = <0xd0000 0x54>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clocks = <&gateclk 11>; - status = "disabled"; - }; - - sdio: mvsdio@d4000 { - compatible = "marvell,orion-sdio"; - reg = <0xd4000 0x200>; - interrupts = ; - clocks = <&gateclk 17>; - bus-width = <4>; - cap-sdio-irq; - cap-sd-highspeed; - cap-mmc-highspeed; - status = "disabled"; - }; - - thermal: thermal@e8078 { - compatible = "marvell,armada375-thermal"; - reg = <0xe8078 0x4>, <0xe807c 0x8>; - status = "okay"; - }; - - coreclk: mvebu-sar@e8204 { - compatible = "marvell,armada-375-core-clock"; - reg = <0xe8204 0x04>; - #clock-cells = <1>; - }; - - coredivclk: corediv-clock@e8250 { - compatible = "marvell,armada-375-corediv-clock"; - reg = <0xe8250 0xc>; - #clock-cells = <1>; - clocks = <&mainpll>; - clock-output-names = "nand"; - }; - }; - - pciec: pcie@82000000 { - compatible = "marvell,armada-370-pcie"; - status = "disabled"; - device_type = "pci"; - - #address-cells = <3>; - #size-cells = <2>; - - msi-parent = <&mpic>; - bus-range = <0x00 0xff>; - - ranges = - <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 - 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 - 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0 MEM */ - 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0 IO */ - 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1 MEM */ - 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1 IO */>; - - pcie0: pcie@1,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; - reg = <0x0800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 - 0x81000000 0 0 0x81000000 0x1 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 5>; - status = "disabled"; - }; - - pcie1: pcie@2,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; - reg = <0x1000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 - 0x81000000 0 0 0x81000000 0x2 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <1>; - clocks = <&gateclk 6>; - status = "disabled"; - }; - - }; - - crypto_sram0: sa-sram0 { - compatible = "mmio-sram"; - reg = ; - clocks = <&gateclk 30>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 MBUS_ID(0x09, 0x09) 0 0x800>; - }; - - crypto_sram1: sa-sram1 { - compatible = "mmio-sram"; - reg = ; - clocks = <&gateclk 31>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 MBUS_ID(0x09, 0x05) 0 0x800>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/armada-380.dtsi b/sys/gnu/dts/arm/armada-380.dtsi deleted file mode 100644 index cff1269f3fb..00000000000 --- a/sys/gnu/dts/arm/armada-380.dtsi +++ /dev/null @@ -1,118 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree Include file for Marvell Armada 380 SoC. - * - * Copyright (C) 2014 Marvell - * - * Lior Amsalem - * Gregory CLEMENT - * Thomas Petazzoni - */ - -#include "armada-38x.dtsi" - -/ { - model = "Marvell Armada 380 family SoC"; - compatible = "marvell,armada380"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "marvell,armada-380-smp"; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - }; - }; - - soc { - internal-regs { - pinctrl@18000 { - compatible = "marvell,mv88f6810-pinctrl"; - }; - }; - - pcie { - compatible = "marvell,armada-370-pcie"; - status = "disabled"; - device_type = "pci"; - - #address-cells = <3>; - #size-cells = <2>; - - msi-parent = <&mpic>; - bus-range = <0x00 0xff>; - - ranges = - <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 - 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 - 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 - 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 - 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */ - 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */ - 0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */ - 0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */ - 0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */ - 0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */>; - - /* x1 port */ - pcie@1,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x80000 0 0x2000>; - reg = <0x0800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 - 0x81000000 0 0 0x81000000 0x1 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 8>; - status = "disabled"; - }; - - /* x1 port */ - pcie@2,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; - reg = <0x1000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 - 0x81000000 0 0 0x81000000 0x2 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; - marvell,pcie-port = <1>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 5>; - status = "disabled"; - }; - - /* x1 port */ - pcie@3,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; - reg = <0x1800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 - 0x81000000 0 0 0x81000000 0x3 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; - marvell,pcie-port = <2>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 6>; - status = "disabled"; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/armada-385-clearfog-gtr-l8.dts b/sys/gnu/dts/arm/armada-385-clearfog-gtr-l8.dts deleted file mode 100644 index c9ac630e587..00000000000 --- a/sys/gnu/dts/arm/armada-385-clearfog-gtr-l8.dts +++ /dev/null @@ -1,115 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) - -#include "armada-385-clearfog-gtr.dtsi" - -/ { - model = "SolidRun Clearfog GTR L8"; -}; - -&mdio { - switch0: switch0@4 { - compatible = "marvell,mv88e6190"; - reg = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&cf_gtr_switch_reset_pins>; - reset-gpios = <&gpio0 18 GPIO_ACTIVE_LOW>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - label = "lan8"; - phy-handle = <&switch0phy0>; - }; - - port@2 { - reg = <2>; - label = "lan7"; - phy-handle = <&switch0phy1>; - }; - - port@3 { - reg = <3>; - label = "lan6"; - phy-handle = <&switch0phy2>; - }; - - port@4 { - reg = <4>; - label = "lan5"; - phy-handle = <&switch0phy3>; - }; - - port@5 { - reg = <5>; - label = "lan4"; - phy-handle = <&switch0phy4>; - }; - - port@6 { - reg = <6>; - label = "lan3"; - phy-handle = <&switch0phy5>; - }; - - port@7 { - reg = <7>; - label = "lan2"; - phy-handle = <&switch0phy6>; - }; - - port@8 { - reg = <8>; - label = "lan1"; - phy-handle = <&switch0phy7>; - }; - - port@10 { - reg = <10>; - label = "cpu"; - ethernet = <ð1>; - }; - - }; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - switch0phy0: switch0phy0@1 { - reg = <0x1>; - }; - - switch0phy1: switch0phy1@2 { - reg = <0x2>; - }; - - switch0phy2: switch0phy2@3 { - reg = <0x3>; - }; - - switch0phy3: switch0phy3@4 { - reg = <0x4>; - }; - - switch0phy4: switch0phy4@5 { - reg = <0x5>; - }; - - switch0phy5: switch0phy5@6 { - reg = <0x6>; - }; - - switch0phy6: switch0phy6@7 { - reg = <0x7>; - }; - - switch0phy7: switch0phy7@8 { - reg = <0x8>; - }; - }; - - }; -}; diff --git a/sys/gnu/dts/arm/armada-385-clearfog-gtr-s4.dts b/sys/gnu/dts/arm/armada-385-clearfog-gtr-s4.dts deleted file mode 100644 index fa653b37949..00000000000 --- a/sys/gnu/dts/arm/armada-385-clearfog-gtr-s4.dts +++ /dev/null @@ -1,79 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) - -#include "armada-385-clearfog-gtr.dtsi" - -/ { - model = "SolidRun Clearfog GTR S4"; -}; - -&sfp0 { - tx-fault-gpio = <&gpio0 24 GPIO_ACTIVE_HIGH>; -}; - -&mdio { - switch0: switch0@4 { - compatible = "marvell,mv88e6085"; - reg = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&cf_gtr_switch_reset_pins>; - reset-gpios = <&gpio0 18 GPIO_ACTIVE_LOW>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - label = "lan2"; - phy-handle = <&switch0phy0>; - }; - - port@2 { - reg = <2>; - label = "lan1"; - phy-handle = <&switch0phy1>; - }; - - port@3 { - reg = <3>; - label = "lan4"; - phy-handle = <&switch0phy2>; - }; - - port@4 { - reg = <4>; - label = "lan3"; - phy-handle = <&switch0phy3>; - }; - - port@5 { - reg = <5>; - label = "cpu"; - ethernet = <ð1>; - }; - - }; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - switch0phy0: switch0phy0@11 { - reg = <0x11>; - }; - - switch0phy1: switch0phy1@12 { - reg = <0x12>; - }; - - switch0phy2: switch0phy2@13 { - reg = <0x13>; - }; - - switch0phy3: switch0phy3@14 { - reg = <0x14>; - }; - }; - - }; -}; diff --git a/sys/gnu/dts/arm/armada-385-clearfog-gtr.dtsi b/sys/gnu/dts/arm/armada-385-clearfog-gtr.dtsi deleted file mode 100644 index 624bbcae68c..00000000000 --- a/sys/gnu/dts/arm/armada-385-clearfog-gtr.dtsi +++ /dev/null @@ -1,450 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Device Tree file for Clearfog GTR machines rev 1.0 (88F6825) - * - * Rabeeh Khoury , based on Russell King clearfog work - */ - -/* - SERDES mapping - - 0. SATA1 on CON18, or optionally mini PCIe CON3 - PCIe0 - 1. 6141 switch (2.5Gbps capable) - 2. SATA0 on CON17, or optionally mini PCIe CON4 - PCIe1 - 3. USB 3.0 Host - 4. mini PCIe CON2 - PCIe2 - 5. SFP connector, or optionally SGMII Ethernet 1512 PHY - - USB 2.0 mapping - - 0. USB 2.0 - 0 USB pins header CON12 - 1. USB 2.0 - 1 mini PCIe CON2 - 2. USB 2.0 - 2 to USB 3.0 connector (used with SERDES #3) - - Pin mapping - - 0,1 - console UART - 2,3 - I2C0 - connected to I2C EEPROM, two temperature sensors, - front panel and PSE controller - 4,5 - MDC/MDIO - 6..17 - RGMII - 18 - Topaz switch reset (active low) - 19 - 1512 phy reset - 20 - 1512 phy reset (eth2, optional) - 21,28,37,38,39,40 - SD0 - 22 - USB 3.0 current limiter enable (active high) - 24 - SFP TX fault (input active high) - 25 - SFP present (input active low) - 26,27 - I2C1 - connected to SFP - 29 - Fan PWM - 30 - CON4 mini PCIe wifi disable - 31 - CON3 mini PCIe wifi disable - 32 - Fuse programming power toggle (1.8v) - 33 - CON4 mini PCIe reset - 34 - CON2 mini PCIe wifi disable - 35 - CON3 mini PCIe reset - 36 - Rear button (GPIO active low) - 41 - CON1 front panel connector - 42 - Front LED1, or front panel CON1 - 43 - Micron L-PBGA 24 ball SPI (1Gb) CS, or TPM SPI CS - 44 - CON2 mini PCIe reset - 45 - TPM PIRQ signal, or front panel CON1 - 46 - SFP TX disable - 47 - Control isolation of boot sensitive SAR signals - 48 - PSE reset - 49 - PSE OSS signal - 50 - PSE interrupt - 52 - Front LED2, or front panel - 53 - Front button - 54 - SFP LOS (input active high) - 55 - Fan sense - 56(mosi),57(clk),58(miso) - SPI interface - 32Mb SPI, 1Gb SPI and TPM - 59 - SPI 32Mb W25Q32BVZPIG CS0 chip select (bootable) -*/ - -/dts-v1/; -#include -#include -#include -#include "armada-385.dtsi" - -/ { - compatible = "marvell,armada385", "marvell,armada380"; - - aliases { - /* So that mvebu u-boot can update the MAC addresses */ - ethernet1 = ð0; - ethernet2 = ð1; - ethernet3 = ð2; - i2c0 = &i2c0; - i2c1 = &i2c1; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - device_type = "memory"; - reg = <0x00000000 0x10000000>; /* 256 MB */ - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_5p0v: regulator-5p0v { - compatible = "regulator-fixed"; - regulator-name = "5P0V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - v_usb3_con: regulator-v-usb3-con { - compatible = "regulator-fixed"; - gpio = <&gpio0 22 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&cf_gtr_usb3_con_vbus>; - regulator-max-microvolt = <5000000>; - regulator-min-microvolt = <5000000>; - regulator-name = "v_usb3_con"; - vin-supply = <®_5p0v>; - regulator-boot-on; - regulator-always-on; - }; - - soc { - ranges = ; - - internal-regs { - - rtc@a3800 { - status = "okay"; - }; - - i2c@11000 { /* ROM, temp sensor and front panel */ - pinctrl-0 = <&i2c0_pins>; - pinctrl-names = "default"; - status = "okay"; - }; - - i2c@11100 { /* SFP (CON5/CON6) */ - pinctrl-0 = <&cf_gtr_i2c1_pins>; - pinctrl-names = "default"; - status = "okay"; - }; - - pinctrl@18000 { - cf_gtr_switch_reset_pins: cf-gtr-switch-reset-pins { - marvell,pins = "mpp18"; - marvell,function = "gpio"; - }; - - cf_gtr_usb3_con_vbus: cf-gtr-usb3-con-vbus { - marvell,pins = "mpp22"; - marvell,function = "gpio"; - }; - - cf_gtr_fan_pwm: cf-gtr-fan-pwm { - marvell,pins = "mpp23"; - marvell,function = "gpio"; - }; - - cf_gtr_i2c1_pins: i2c1-pins { - /* SFP */ - marvell,pins = "mpp26", "mpp27"; - marvell,function = "i2c1"; - }; - - cf_gtr_sdhci_pins: cf-gtr-sdhci-pins { - marvell,pins = "mpp21", "mpp28", - "mpp37", "mpp38", - "mpp39", "mpp40"; - marvell,function = "sd0"; - }; - - cf_gtr_isolation_pins: cf-gtr-isolation-pins { - marvell,pins = "mpp47"; - marvell,function = "gpio"; - }; - - cf_gtr_poe_reset_pins: cf-gtr-poe-reset-pins { - marvell,pins = "mpp48"; - marvell,function = "gpio"; - }; - - cf_gtr_spi1_cs_pins: spi1-cs-pins { - marvell,pins = "mpp59"; - marvell,function = "spi1"; - }; - - cf_gtr_front_button_pins: cf-gtr-front-button-pins { - marvell,pins = "mpp53"; - marvell,function = "gpio"; - }; - - cf_gtr_rear_button_pins: cf-gtr-rear-button-pins { - marvell,pins = "mpp36"; - marvell,function = "gpio"; - }; - }; - - sdhci@d8000 { - bus-width = <4>; - no-1-8-v; - non-removable; - pinctrl-0 = <&cf_gtr_sdhci_pins>; - pinctrl-names = "default"; - status = "okay"; - vmmc = <®_3p3v>; - wp-inverted; - }; - - usb@58000 { - status = "okay"; - }; - - usb3@f0000 { - status = "okay"; - }; - - usb3@f8000 { - vbus-supply = <&v_usb3_con>; - status = "okay"; - }; - }; - - pcie { - status = "okay"; - /* - * The PCIe units are accessible through - * the mini-PCIe connectors on the board. - */ - pcie@1,0 { - reset-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; - status = "okay"; - }; - - pcie@2,0 { - reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; - status = "okay"; - }; - - pcie@3,0 { - reset-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; - status = "okay"; - }; - }; - }; - - sfp0: sfp { - compatible = "sff,sfp"; - i2c-bus = <&i2c1>; - los-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>; - mod-def0-gpio = <&gpio0 25 GPIO_ACTIVE_LOW>; - tx-disable-gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-0 = <&cf_gtr_rear_button_pins &cf_gtr_front_button_pins>; - pinctrl-names = "default"; - - button_0 { - label = "Rear Button"; - gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - linux,can-disable; - linux,code = ; - }; - - button_1 { - label = "Front Button"; - gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; - linux,can-disable; - linux,code = ; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - led1 { - function = LED_FUNCTION_CPU; - color = ; - gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; - }; - - led2 { - function = LED_FUNCTION_HEARTBEAT; - color = ; - gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&bm { - status = "okay"; -}; - -&bm_bppi { - status = "okay"; -}; - -ð0 { - /* ethernet@70000 */ - pinctrl-0 = <&ge0_rgmii_pins>; - pinctrl-names = "default"; - phy = <&phy_dedicated>; - phy-mode = "rgmii-id"; - buffer-manager = <&bm>; - bm,pool-long = <0>; - bm,pool-short = <1>; - status = "okay"; -}; - -ð1 { - /* ethernet@30000 */ - bm,pool-long = <2>; - bm,pool-short = <1>; - buffer-manager = <&bm>; - phys = <&comphy1 1>; - phy-mode = "2500base-x"; - status = "okay"; - - fixed-link { - speed = <2500>; - full-duplex; - }; -}; - -ð2 { - /* ethernet@34000 */ - bm,pool-long = <3>; - bm,pool-short = <1>; - buffer-manager = <&bm>; - managed = "in-band-status"; - phys = <&comphy5 1>; - phy-mode = "sgmii"; - sfp = <&sfp0>; - status = "okay"; -}; - -&mdio { - pinctrl-names = "default"; - pinctrl-0 = <&mdio_pins>; - status = "okay"; - - phy_dedicated: ethernet-phy@0 { - /* - * Annoyingly, the marvell phy driver configures the LED - * register, rather than preserving reset-loaded setting. - * We undo that rubbish here. - */ - marvell,reg-init = <3 16 0 0x1017>; - reg = <0>; - }; -}; - -&uart0 { - pinctrl-0 = <&uart0_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&spi1 { - /* - * CS0: W25Q32 flash - */ - pinctrl-0 = <&spi1_pins &cf_gtr_spi1_cs_pins>; - pinctrl-names = "default"; - status = "okay"; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "w25q32", "jedec,spi-nor"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <3000000>; - status = "okay"; - }; -}; - -&i2c0 { - pinctrl-0 = <&i2c0_pins>; - pinctrl-names = "default"; - status = "okay"; - - /* U26 temperature sensor placed near SoC */ - temp1: nct75@4c { - compatible = "lm75"; - reg = <0x4c>; - }; - - /* U27 temperature sensor placed near RTC battery */ - temp2: nct75@4d { - compatible = "lm75"; - reg = <0x4d>; - }; - - /* 2Kb eeprom */ - eeprom@53 { - compatible = "atmel,24c02"; - reg = <0x53>; - }; -}; - -&ahci0 { - status = "okay"; -}; - -&ahci1 { - status = "okay"; -}; - -&gpio0 { - pinctrl-0 = <&cf_gtr_fan_pwm>; - pinctrl-names = "default"; - - wifi-disable { - gpio-hog; - gpios = <30 GPIO_ACTIVE_LOW>, <31 GPIO_ACTIVE_LOW>; - output-low; - line-name = "wifi-disable"; - }; -}; - -&gpio1 { - pinctrl-0 = <&cf_gtr_isolation_pins &cf_gtr_poe_reset_pins>; - pinctrl-names = "default"; - - lte-disable { - gpio-hog; - gpios = <2 GPIO_ACTIVE_LOW>; - output-low; - line-name = "lte-disable"; - }; - - /* - * This signal, when asserted, isolates Armada 38x sample at reset pins - * from control of external devices. Should be de-asserted after reset. - */ - sar-isolation { - gpio-hog; - gpios = <15 GPIO_ACTIVE_LOW>; - output-low; - line-name = "sar-isolation"; - }; - - poe-reset { - gpio-hog; - gpios = <16 GPIO_ACTIVE_LOW>; - output-low; - line-name = "poe-reset"; - }; -}; diff --git a/sys/gnu/dts/arm/armada-385-db-88f6820-amc.dts b/sys/gnu/dts/arm/armada-385-db-88f6820-amc.dts deleted file mode 100644 index 7881df3b28a..00000000000 --- a/sys/gnu/dts/arm/armada-385-db-88f6820-amc.dts +++ /dev/null @@ -1,155 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Device Tree file for Marvell Armada 385 AMC board - * (DB-88F6820-AMC) - * - * Copyright (C) 2017 Allied Telesis Labs - */ - -/dts-v1/; -#include "armada-385.dtsi" - -#include - -/ { - model = "Marvell Armada 385 AMC"; - compatible = "marvell,a385-db-amc", "marvell,armada385", "marvell,armada380"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - aliases { - ethernet0 = ð0; - ethernet1 = ð1; - spi1 = &spi1; - }; - - memory { - device_type = "memory"; - reg = <0x00000000 0x80000000>; /* 2GB */ - }; - - soc { - ranges = ; - }; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - status = "okay"; -}; - -&uart0 { - /* - * Exported on the micro USB connector CON3 - * through an FTDI - */ - - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - status = "okay"; -}; - - -ð0 { - pinctrl-names = "default"; - /* - * The Reference Clock 0 is used to provide a - * clock to the PHY - */ - pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>; - status = "okay"; - phy = <&phy0>; - phy-mode = "rgmii-id"; -}; - -ð2 { - status = "okay"; - phy = <&phy1>; - phy-mode = "sgmii"; -}; - -&usb0 { - status = "okay"; -}; - - - -&mdio { - pinctrl-names = "default"; - pinctrl-0 = <&mdio_pins>; - - phy0: ethernet-phy@1 { - reg = <1>; - }; - - phy1: ethernet-phy@0 { - reg = <0>; - }; -}; - -&nand_controller { - status = "okay"; - - nand@0 { - reg = <0>; - label = "pxa3xx_nand-0"; - nand-rb = <0>; - nand-on-flash-bbt; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - partition@0 { - reg = <0x00000000 0x40000000>; - label = "user"; - }; - }; - }; -}; - -&pciec { - status = "okay"; -}; - -&pcie1 { - /* Port 0, Lane 0 */ - status = "okay"; -}; - -&spi1 { - pinctrl-names = "default"; - pinctrl-0 = <&spi1_pins>; - status = "okay"; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <50000000>; - m25p,fast-read; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - partition@0 { - reg = <0x00000000 0x00100000>; - label = "u-boot"; - }; - partition@100000 { - reg = <0x00100000 0x00040000>; - label = "u-boot-env"; - }; - }; - }; -}; - -&refclk { - clock-frequency = <20000000>; -}; diff --git a/sys/gnu/dts/arm/armada-385-db-ap.dts b/sys/gnu/dts/arm/armada-385-db-ap.dts deleted file mode 100644 index 0e4613bb56e..00000000000 --- a/sys/gnu/dts/arm/armada-385-db-ap.dts +++ /dev/null @@ -1,238 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Device Tree file for Marvell Armada 385 Access Point Development board - * (DB-88F6820-AP) - * - * Copyright (C) 2014 Marvell - * - * Nadav Haklai - */ - -/dts-v1/; -#include "armada-385.dtsi" - -#include - -/ { - model = "Marvell Armada 385 Access Point Development Board"; - compatible = "marvell,a385-db-ap", "marvell,armada385", "marvell,armada380"; - - chosen { - stdout-path = "serial1:115200n8"; - }; - - memory { - device_type = "memory"; - reg = <0x00000000 0x80000000>; /* 2GB */ - }; - - soc { - ranges = ; - - internal-regs { - i2c0: i2c@11000 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - status = "okay"; - - /* - * This bus is wired to two EEPROM - * sockets, one of which holding the - * board ID used by the bootloader. - * Erasing this EEPROM's content will - * brick the board. - * Use this bus with caution. - */ - }; - - mdio@72004 { - pinctrl-names = "default"; - pinctrl-0 = <&mdio_pins>; - - phy0: ethernet-phy@1 { - reg = <1>; - }; - - phy1: ethernet-phy@4 { - reg = <4>; - }; - - phy2: ethernet-phy@6 { - reg = <6>; - }; - }; - - /* UART0 is exposed through the JP8 connector */ - uart0: serial@12000 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - status = "okay"; - }; - - /* - * UART1 is exposed through a FTDI chip - * wired to the mini-USB connector - */ - uart1: serial@12100 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; - status = "okay"; - }; - - pinctrl@18000 { - xhci0_vbus_pins: xhci0-vbus-pins { - marvell,pins = "mpp44"; - marvell,function = "gpio"; - }; - }; - - /* CON3 */ - ethernet@30000 { - status = "okay"; - phy = <&phy2>; - phy-mode = "sgmii"; - buffer-manager = <&bm>; - bm,pool-long = <1>; - bm,pool-short = <3>; - }; - - /* CON2 */ - ethernet@34000 { - status = "okay"; - phy = <&phy1>; - phy-mode = "sgmii"; - buffer-manager = <&bm>; - bm,pool-long = <2>; - bm,pool-short = <3>; - }; - - usb@58000 { - status = "okay"; - }; - - /* CON4 */ - ethernet@70000 { - pinctrl-names = "default"; - - /* - * The Reference Clock 0 is used to - * provide a clock to the PHY - */ - pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>; - status = "okay"; - phy = <&phy0>; - phy-mode = "rgmii-id"; - buffer-manager = <&bm>; - bm,pool-long = <0>; - bm,pool-short = <3>; - }; - - bm@c8000 { - status = "okay"; - }; - - usb3@f0000 { - status = "okay"; - usb-phy = <&usb3_phy>; - }; - }; - - bm-bppi { - status = "okay"; - }; - - pcie { - status = "okay"; - - /* - * The three PCIe units are accessible through - * standard mini-PCIe slots on the board. - */ - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - - pcie@2,0 { - /* Port 1, Lane 0 */ - status = "okay"; - }; - - pcie@3,0 { - /* Port 2, Lane 0 */ - status = "okay"; - }; - }; - }; - - usb3_phy: usb3_phy { - compatible = "usb-nop-xceiv"; - vcc-supply = <®_xhci0_vbus>; - #phy-cells = <0>; - }; - - reg_xhci0_vbus: xhci0-vbus { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&xhci0_vbus_pins>; - regulator-name = "xhci0-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; - }; -}; - -&spi1 { - pinctrl-names = "default"; - pinctrl-0 = <&spi1_pins>; - status = "okay"; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,m25p128", "jedec,spi-nor"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <54000000>; - }; -}; - -&nand_controller { - status = "okay"; - - nand@0 { - reg = <0>; - label = "pxa3xx_nand-0"; - nand-rb = <0>; - nand-on-flash-bbt; - nand-ecc-strength = <4>; - nand-ecc-step-size = <512>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "U-Boot"; - reg = <0x00000000 0x00800000>; - read-only; - }; - - partition@800000 { - label = "uImage"; - reg = <0x00800000 0x00400000>; - read-only; - }; - - partition@c00000 { - label = "Root"; - reg = <0x00c00000 0x3f400000>; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/armada-385-linksys-caiman.dts b/sys/gnu/dts/arm/armada-385-linksys-caiman.dts deleted file mode 100644 index a03050c9708..00000000000 --- a/sys/gnu/dts/arm/armada-385-linksys-caiman.dts +++ /dev/null @@ -1,144 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Device Tree include for the Linksys WRT1200AC (Caiman) - * - * Copyright (C) 2015 Imre Kaloz - */ - -/dts-v1/; -#include "armada-385-linksys.dtsi" - -/ { - model = "Linksys WRT1200AC"; - compatible = "linksys,caiman", "linksys,armada385", "marvell,armada385", - "marvell,armada380"; -}; - -&expander0 { - wan_amber@0 { - label = "caiman:amber:wan"; - reg = <0x0>; - }; - - wan_white@1 { - label = "caiman:white:wan"; - reg = <0x1>; - }; - - wlan_2g@2 { - label = "caiman:white:wlan_2g"; - reg = <0x2>; - }; - - wlan_5g@3 { - label = "caiman:white:wlan_5g"; - reg = <0x3>; - }; - - usb2@5 { - label = "caiman:white:usb2"; - reg = <0x5>; - }; - - usb3_1@6 { - label = "caiman:white:usb3_1"; - reg = <0x6>; - }; - - usb3_2@7 { - label = "caiman:white:usb3_2"; - reg = <0x7>; - }; - - wps_white@8 { - label = "caiman:white:wps"; - reg = <0x8>; - }; - - wps_amber@9 { - label = "caiman:amber:wps"; - reg = <0x9>; - }; -}; - -&gpio_leds { - power { - label = "caiman:white:power"; - }; - - sata { - label = "caiman:white:sata"; - }; -}; - -&nand { - /* 128MiB */ - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0x200000>; /* 2MiB */ - read-only; - }; - - partition@100000 { - label = "u_env"; - reg = <0x200000 0x40000>; /* 256KiB */ - }; - - partition@140000 { - label = "s_env"; - reg = <0x240000 0x40000>; /* 256KiB */ - }; - - partition@900000 { - label = "devinfo"; - reg = <0x900000 0x100000>; /* 1MiB */ - read-only; - }; - - /* kernel1 overlaps with rootfs1 by design */ - partition@a00000 { - label = "kernel1"; - reg = <0xa00000 0x2800000>; /* 40MiB */ - }; - - partition@1000000 { - label = "rootfs1"; - reg = <0x1000000 0x2200000>; /* 34MiB */ - }; - - /* kernel2 overlaps with rootfs2 by design */ - partition@3200000 { - label = "kernel2"; - reg = <0x3200000 0x2800000>; /* 40MiB */ - }; - - partition@3800000 { - label = "rootfs2"; - reg = <0x3800000 0x2200000>; /* 34MiB */ - }; - - /* - * 38MiB, last MiB is for the BBT, not writable - */ - partition@5a00000 { - label = "syscfg"; - reg = <0x5a00000 0x2600000>; - }; - - /* - * Unused area between "s_env" and "devinfo". - * Moved here because otherwise the renumbered - * partitions would break the bootloader - * supplied bootargs - */ - partition@180000 { - label = "unused_area"; - reg = <0x280000 0x680000>; /* 6.5MiB */ - }; - }; -}; diff --git a/sys/gnu/dts/arm/armada-385-linksys-cobra.dts b/sys/gnu/dts/arm/armada-385-linksys-cobra.dts deleted file mode 100644 index e3e4877a6f4..00000000000 --- a/sys/gnu/dts/arm/armada-385-linksys-cobra.dts +++ /dev/null @@ -1,144 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Device Tree file for the Linksys WRT1900ACv2 (Cobra) - * - * Copyright (C) 2015 Imre Kaloz - */ - -/dts-v1/; -#include "armada-385-linksys.dtsi" - -/ { - model = "Linksys WRT1900ACv2"; - compatible = "linksys,cobra", "linksys,armada385", "marvell,armada385", - "marvell,armada380"; -}; - -&expander0 { - wan_amber@0 { - label = "cobra:amber:wan"; - reg = <0x0>; - }; - - wan_white@1 { - label = "cobra:white:wan"; - reg = <0x1>; - }; - - wlan_2g@2 { - label = "cobra:white:wlan_2g"; - reg = <0x2>; - }; - - wlan_5g@3 { - label = "cobra:white:wlan_5g"; - reg = <0x3>; - }; - - usb2@5 { - label = "cobra:white:usb2"; - reg = <0x5>; - }; - - usb3_1@6 { - label = "cobra:white:usb3_1"; - reg = <0x6>; - }; - - usb3_2@7 { - label = "cobra:white:usb3_2"; - reg = <0x7>; - }; - - wps_white@8 { - label = "cobra:white:wps"; - reg = <0x8>; - }; - - wps_amber@9 { - label = "cobra:amber:wps"; - reg = <0x9>; - }; -}; - -&gpio_leds { - power { - label = "cobra:white:power"; - }; - - sata { - label = "cobra:white:sata"; - }; -}; - -&nand { - /* 128MiB */ - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0x200000>; /* 2MiB */ - read-only; - }; - - partition@100000 { - label = "u_env"; - reg = <0x200000 0x40000>; /* 256KiB */ - }; - - partition@140000 { - label = "s_env"; - reg = <0x240000 0x40000>; /* 256KiB */ - }; - - partition@900000 { - label = "devinfo"; - reg = <0x900000 0x100000>; /* 1MiB */ - read-only; - }; - - /* kernel1 overlaps with rootfs1 by design */ - partition@a00000 { - label = "kernel1"; - reg = <0xa00000 0x2800000>; /* 40MiB */ - }; - - partition@1000000 { - label = "rootfs1"; - reg = <0x1000000 0x2200000>; /* 34MiB */ - }; - - /* kernel2 overlaps with rootfs2 by design */ - partition@3200000 { - label = "kernel2"; - reg = <0x3200000 0x2800000>; /* 40MiB */ - }; - - partition@3800000 { - label = "rootfs2"; - reg = <0x3800000 0x2200000>; /* 34MiB */ - }; - - /* - * 38MiB, last MiB is for the BBT, not writable - */ - partition@5a00000 { - label = "syscfg"; - reg = <0x5a00000 0x2600000>; - }; - - /* - * Unused area between "s_env" and "devinfo". - * Moved here because otherwise the renumbered - * partitions would break the bootloader - * supplied bootargs - */ - partition@180000 { - label = "unused_area"; - reg = <0x280000 0x680000>; /* 6.5MiB */ - }; - }; -}; diff --git a/sys/gnu/dts/arm/armada-385-linksys-rango.dts b/sys/gnu/dts/arm/armada-385-linksys-rango.dts deleted file mode 100644 index 3c4af57ec2b..00000000000 --- a/sys/gnu/dts/arm/armada-385-linksys-rango.dts +++ /dev/null @@ -1,176 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Device Tree file for the Linksys WRT3200ACM (Rango) - * - * Copyright (C) 2016 Imre Kaloz - */ - -/dts-v1/; -#include -#include -#include "armada-385-linksys.dtsi" - -/ { - model = "Linksys WRT3200ACM"; - compatible = "linksys,rango", "linksys,armada385", "marvell,armada385", - "marvell,armada380"; -}; - -&expander0 { - wan_amber@0 { - label = "rango:amber:wan"; - reg = <0x0>; - }; - - wan_white@1 { - label = "rango:white:wan"; - reg = <0x1>; - }; - - usb2@5 { - label = "rango:white:usb2"; - reg = <0x5>; - }; - - usb3_1@6 { - label = "rango:white:usb3_1"; - reg = <0x6>; - }; - - usb3_2@7 { - label = "rango:white:usb3_2"; - reg = <0x7>; - }; - - wps_white@8 { - label = "rango:white:wps"; - reg = <0x8>; - }; - - wps_amber@9 { - label = "rango:amber:wps"; - reg = <0x9>; - }; -}; - -&gpio_leds { - power { - gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>; - label = "rango:white:power"; - }; - - sata { - gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; - label = "rango:white:sata"; - }; - - wlan_2g { - gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; - label = "rango:white:wlan_2g"; - }; - - wlan_5g { - gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; - label = "rango:white:wlan_5g"; - }; -}; - -&gpio_leds_pins { - marvell,pins = "mpp21", "mpp45", "mpp46", "mpp56"; -}; - -&nand { - /* AMD/Spansion S34ML02G2 256MiB, OEM Layout */ - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0x200000>; /* 2MiB */ - read-only; - }; - - partition@200000 { - label = "u_env"; - reg = <0x200000 0x20000>; /* 128KiB */ - }; - - partition@220000 { - label = "s_env"; - reg = <0x220000 0x40000>; /* 256KiB */ - }; - - partition@7e0000 { - label = "devinfo"; - reg = <0x7e0000 0x40000>; /* 256KiB */ - read-only; - }; - - partition@820000 { - label = "sysdiag"; - reg = <0x820000 0x1e0000>; /* 1920KiB */ - read-only; - }; - - /* kernel1 overlaps with rootfs1 by design */ - partition@a00000 { - label = "kernel1"; - reg = <0xa00000 0x5000000>; /* 80MiB */ - }; - - partition@1000000 { - label = "rootfs1"; - reg = <0x1000000 0x4a00000>; /* 74MiB */ - }; - - /* kernel2 overlaps with rootfs2 by design */ - partition@5a00000 { - label = "kernel2"; - reg = <0x5a00000 0x5000000>; /* 80MiB */ - }; - - partition@6000000 { - label = "rootfs2"; - reg = <0x6000000 0x4a00000>; /* 74MiB */ - }; - - /* - * 86MiB, last MiB is for the BBT, not writable - */ - partition@aa00000 { - label = "syscfg"; - reg = <0xaa00000 0x5600000>; - }; - - /* - * Unused area between "s_env" and "devinfo". - * Moved here because otherwise the renumbered - * partitions would break the bootloader - * supplied bootargs - */ - partition@180000 { - label = "unused_area"; - reg = <0x260000 0x5c0000>; /* 5.75MiB */ - }; - }; -}; - -&sdhci { - pinctrl-names = "default"; - pinctrl-0 = <&sdhci_pins>; - no-1-8-v; - non-removable; - wp-inverted; - bus-width = <8>; - status = "okay"; -}; - -&usb3_1_vbus { - gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; -}; - -&usb3_1_vbus_pins { - marvell,pins = "mpp44"; -}; diff --git a/sys/gnu/dts/arm/armada-385-linksys-shelby.dts b/sys/gnu/dts/arm/armada-385-linksys-shelby.dts deleted file mode 100644 index 3451cd3e5df..00000000000 --- a/sys/gnu/dts/arm/armada-385-linksys-shelby.dts +++ /dev/null @@ -1,144 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Device Tree file for the Linksys WRT1900ACS (Shelby) - * - * Copyright (C) 2015 Imre Kaloz - */ - -/dts-v1/; -#include "armada-385-linksys.dtsi" - -/ { - model = "Linksys WRT1900ACS"; - compatible = "linksys,shelby", "linksys,armada385", "marvell,armada385", - "marvell,armada380"; -}; - -&expander0 { - wan_amber@0 { - label = "shelby:amber:wan"; - reg = <0x0>; - }; - - wan_white@1 { - label = "shelby:white:wan"; - reg = <0x1>; - }; - - wlan_2g@2 { - label = "shelby:white:wlan_2g"; - reg = <0x2>; - }; - - wlan_5g@3 { - label = "shelby:white:wlan_5g"; - reg = <0x3>; - }; - - usb2@5 { - label = "shelby:white:usb2"; - reg = <0x5>; - }; - - usb3_1@6 { - label = "shelby:white:usb3_1"; - reg = <0x6>; - }; - - usb3_2@7 { - label = "shelby:white:usb3_2"; - reg = <0x7>; - }; - - wps_white@8 { - label = "shelby:white:wps"; - reg = <0x8>; - }; - - wps_amber@9 { - label = "shelby:amber:wps"; - reg = <0x9>; - }; -}; - -&gpio_leds { - power { - label = "shelby:white:power"; - }; - - sata { - label = "shelby:white:sata"; - }; -}; - -&nand { - /* 128MiB */ - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0x200000>; /* 2MiB */ - read-only; - }; - - partition@100000 { - label = "u_env"; - reg = <0x200000 0x40000>; /* 256KiB */ - }; - - partition@140000 { - label = "s_env"; - reg = <0x240000 0x40000>; /* 256KiB */ - }; - - partition@900000 { - label = "devinfo"; - reg = <0x900000 0x100000>; /* 1MiB */ - read-only; - }; - - /* kernel1 overlaps with rootfs1 by design */ - partition@a00000 { - label = "kernel1"; - reg = <0xa00000 0x2800000>; /* 40MiB */ - }; - - partition@1000000 { - label = "rootfs1"; - reg = <0x1000000 0x2200000>; /* 34MiB */ - }; - - /* kernel2 overlaps with rootfs2 by design */ - partition@3200000 { - label = "kernel2"; - reg = <0x3200000 0x2800000>; /* 40MiB */ - }; - - partition@3800000 { - label = "rootfs2"; - reg = <0x3800000 0x2200000>; /* 34MiB */ - }; - - /* - * 38MiB, last MiB is for the BBT, not writable - */ - partition@5a00000 { - label = "syscfg"; - reg = <0x5a00000 0x2600000>; - }; - - /* - * Unused area between "s_env" and "devinfo". - * Moved here because otherwise the renumbered - * partitions would break the bootloader - * supplied bootargs - */ - partition@180000 { - label = "unused_area"; - reg = <0x280000 0x680000>; /* 6.5MiB */ - }; - }; -}; diff --git a/sys/gnu/dts/arm/armada-385-linksys.dtsi b/sys/gnu/dts/arm/armada-385-linksys.dtsi deleted file mode 100644 index 827e82be220..00000000000 --- a/sys/gnu/dts/arm/armada-385-linksys.dtsi +++ /dev/null @@ -1,263 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Device Tree include file for Armada 385 based Linksys boards - * - * Copyright (C) 2015 Imre Kaloz - */ - -#include -#include -#include "armada-385.dtsi" - -/ { - model = "Linksys boards based on Armada 385"; - compatible = "linksys,armada385", "marvell,armada385", - "marvell,armada380"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - device_type = "memory"; - reg = <0x00000000 0x20000000>; /* 512 MiB */ - }; - - soc { - ranges = ; - }; - - usb3_1_phy: usb3_1-phy { - compatible = "usb-nop-xceiv"; - vcc-supply = <&usb3_1_vbus>; - #phy-cells = <0>; - }; - - usb3_1_vbus: usb3_1-vbus { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&usb3_1_vbus_pins>; - regulator-name = "usb3_1-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio1 18 GPIO_ACTIVE_HIGH>; - }; - - gpio_keys: gpio-keys { - compatible = "gpio-keys"; - pinctrl-0 = <&gpio_keys_pins>; - pinctrl-names = "default"; - - wps { - label = "WPS"; - linux,code = ; - gpios = <&gpio0 24 GPIO_ACTIVE_LOW>; - }; - - reset { - label = "Factory Reset Button"; - linux,code = ; - gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; - }; - }; - - gpio_leds: gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&gpio_leds_pins>; - pinctrl-names = "default"; - - power { - gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - sata { - gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; - default-state = "off"; - linux,default-trigger = "disk-activity"; - }; - }; -}; - -&ahci0 { - status = "okay"; -}; - -&bm { - status = "okay"; -}; - -&bm_bppi { - status = "okay"; -}; - -ð0 { - status = "okay"; - phy-mode = "rgmii-id"; - buffer-manager = <&bm>; - bm,pool-long = <0>; - bm,pool-short = <1>; - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -ð2 { - status = "okay"; - phy-mode = "sgmii"; - buffer-manager = <&bm>; - bm,pool-long = <2>; - bm,pool-short = <3>; - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - status = "okay"; - - tmp421@4c { - compatible = "ti,tmp421"; - reg = <0x4c>; - }; - - expander0: pca9635@68 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "nxp,pca9635"; - reg = <0x68>; - }; -}; - -&nand_controller { - /* 128MiB or 256MiB */ - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - - nand: nand@0 { - reg = <0>; - label = "pxa3xx_nand-0"; - nand-rb = <0>; - marvell,nand-keep-config; - nand-on-flash-bbt; - }; -}; - -&mdio { - status = "okay"; - - switch@0 { - compatible = "marvell,mv88e6085"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "lan4"; - }; - - port@1 { - reg = <1>; - label = "lan3"; - }; - - port@2 { - reg = <2>; - label = "lan2"; - }; - - port@3 { - reg = <3>; - label = "lan1"; - }; - - port@4 { - reg = <4>; - label = "wan"; - }; - - port@5 { - reg = <5>; - label = "cpu"; - ethernet = <ð2>; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; - }; -}; - -&pciec { - status = "okay"; -}; - -&pcie1 { - /* Marvell 88W8864, 5GHz-only */ - status = "okay"; -}; - -&pcie2 { - /* Marvell 88W8864, 2GHz-only */ - status = "okay"; -}; - -&pinctrl { - gpio_keys_pins: gpio-keys-pins { - /* mpp24: wps, mpp29: reset */ - marvell,pins = "mpp24", "mpp29"; - marvell,function = "gpio"; - }; - - gpio_leds_pins: gpio-leds-pins { - /* mpp54: sata, mpp55: power */ - marvell,pins = "mpp54", "mpp55"; - marvell,function = "gpio"; - }; - - usb3_1_vbus_pins: usb3_1-vbus-pins { - marvell,pins = "mpp50"; - marvell,function = "gpio"; - }; -}; - -&spi0 { - status = "disabled"; -}; - -&uart0 { - /* J10: VCC, NC, RX, NC, TX, GND */ - status = "okay"; -}; - -&usb0 { - /* USB part of the eSATA/USB 2.0 port */ - status = "okay"; -}; - -&usb3_1 { - status = "okay"; - usb-phy = <&usb3_1_phy>; -}; - -&rtc { - /* No crystal connected to the internal RTC */ - status = "disabled"; -}; diff --git a/sys/gnu/dts/arm/armada-385-synology-ds116.dts b/sys/gnu/dts/arm/armada-385-synology-ds116.dts deleted file mode 100644 index d8769956cbf..00000000000 --- a/sys/gnu/dts/arm/armada-385-synology-ds116.dts +++ /dev/null @@ -1,292 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Device Tree file for Synology DS116 NAS - * - * Copyright (C) 2017 Willy Tarreau - */ - -/dts-v1/; -#include "armada-385.dtsi" -#include - -/ { - model = "Synology DS116"; - compatible = "marvell,a385-gp", "marvell,armada385", "marvell,armada380"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - device_type = "memory"; - reg = <0x00000000 0x40000000>; /* 1 GB */ - }; - - soc { - ranges = ; - - internal-regs { - i2c@11000 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - status = "okay"; - clock-frequency = <100000>; - - eeprom@57 { - compatible = "atmel,24c64"; - reg = <0x57>; - }; - }; - - serial@12000 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - status = "okay"; - }; - - serial@12100 { - /* A PIC16F1829 is connected to uart1 at 9600 bps, - * and takes single-character orders : - * "1" : power off // already handled by the poweroff node - * "2" : short beep - * "3" : long beep - * "4" : turn the power LED ON - * "5" : flash the power LED - * "6" : turn the power LED OFF - * "7" : turn the status LED OFF - * "8" : turn the status LED ON - * "9" : flash the status LED - * "A" : flash the motherboard LED (D8) - * "B" : turn the motherboard LED OFF - * "C" : hard reset - */ - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; - status = "okay"; - }; - - poweroff@12100 { - compatible = "synology,power-off"; - reg = <0x12100 0x100>; - clocks = <&coreclk 0>; - }; - - ethernet@70000 { - pinctrl-names = "default"; - phy = <&phy0>; - phy-mode = "sgmii"; - buffer-manager = <&bm>; - bm,pool-long = <0>; - status = "okay"; - }; - - - mdio@72004 { - pinctrl-names = "default"; - pinctrl-0 = <&mdio_pins>; - - phy0: ethernet-phy@1 { - reg = <1>; - }; - }; - - sata@a8000 { - pinctrl-names = "default"; - pinctrl-0 = <&sata0_pins>; - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - - sata0: sata-port@0 { - reg = <0>; - target-supply = <®_5v_sata0>; - }; - }; - - bm@c8000 { - status = "okay"; - }; - - usb3@f0000 { - usb-phy = <&usb3_0_phy>; - status = "okay"; - }; - - usb3@f8000 { - usb-phy = <&usb3_1_phy>; - status = "okay"; - }; - }; - - bm-bppi { - status = "okay"; - }; - - gpio-fan { - compatible = "gpio-fan"; - gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>, - <&gpio1 17 GPIO_ACTIVE_HIGH>, - <&gpio1 16 GPIO_ACTIVE_HIGH>; - gpio-fan,speed-map = < 0 0 - 1500 1 - 2500 2 - 3000 3 - 3400 4 - 3700 5 - 3900 6 - 4000 7>; - #cooling-cells = <2>; - }; - - gpio-leds { - compatible = "gpio-leds"; - - /* The green part is on gpio0.20 which is also used by - * sata0, and accesses to SATA disk 0 make it blink so it - * doesn't need to be declared here. - */ - orange { - gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; - label = "ds116:orange:disk"; - default-state = "off"; - }; - }; - }; - - usb3_0_phy: usb3_0_phy { - compatible = "usb-nop-xceiv"; - vcc-supply = <®_usb3_0_vbus>; - #phy-cells = <0>; - }; - - usb3_1_phy: usb3_1_phy { - compatible = "usb-nop-xceiv"; - vcc-supply = <®_usb3_1_vbus>; - #phy-cells = <0>; - }; - - reg_usb3_0_vbus: usb3-vbus0 { - compatible = "regulator-fixed"; - regulator-name = "usb3-vbus0"; - pinctrl-names = "default"; - pinctrl-0 = <&xhci0_vbus_pins>; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>; - }; - - reg_usb3_1_vbus: usb3-vbus1 { - compatible = "regulator-fixed"; - regulator-name = "usb3-vbus1"; - pinctrl-names = "default"; - pinctrl-0 = <&xhci1_vbus_pins>; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio1 27 GPIO_ACTIVE_HIGH>; - }; - - reg_sata0: pwr-sata0 { - compatible = "regulator-fixed"; - regulator-name = "pwr_en_sata0"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - enable-active-high; - regulator-boot-on; - gpio = <&gpio0 15 GPIO_ACTIVE_HIGH>; - }; - - reg_5v_sata0: v5-sata0 { - compatible = "regulator-fixed"; - regulator-name = "v5.0-sata0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <®_sata0>; - }; - - reg_12v_sata0: v12-sata0 { - compatible = "regulator-fixed"; - regulator-name = "v12.0-sata0"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - vin-supply = <®_sata0>; - }; -}; - -&spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins>; - status = "okay"; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "macronix,mx25l6405d", "jedec,spi-nor"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <50000000>; - m25p,fast-read; - - /* Note: there is a redboot partition table despite u-boot - * being used. The names presented here are the same as those - * found in the FIS directory. There is also a small device - * tree in the last 64kB of the RedBoot partition which is not - * enumerated. The MAC address and the serial number are listed - * in the "vendor" partition. - */ - partition@0 { - label = "RedBoot"; - reg = <0x00000000 0x000f0000>; - read-only; - }; - - partition@c0000 { - label = "zImage"; - reg = <0x000f0000 0x002d0000>; - }; - - partition@390000 { - label = "rd.gz"; - reg = <0x003c0000 0x00410000>; - }; - - partition@7d0000 { - label = "vendor"; - reg = <0x007d0000 0x00010000>; - read-only; - }; - - partition@7e0000 { - label = "RedBoot config"; - reg = <0x007e0000 0x00010000>; - read-only; - }; - - partition@7f0000 { - label = "FIS directory"; - reg = <0x007f0000 0x00010000>; - read-only; - }; - }; -}; - -&pinctrl { - /* use only one pin for UART1, as mpp20 is used by sata0 */ - uart1_pins: uart-pins-1 { - marvell,pins = "mpp19"; - marvell,function = "ua1"; - }; - - xhci0_vbus_pins: xhci0_vbus_pins { - marvell,pins = "mpp58"; - marvell,function = "gpio"; - }; - xhci1_vbus_pins: xhci1_vbus_pins { - marvell,pins = "mpp59"; - marvell,function = "gpio"; - }; -}; diff --git a/sys/gnu/dts/arm/armada-385-turris-omnia.dts b/sys/gnu/dts/arm/armada-385-turris-omnia.dts deleted file mode 100644 index 768b6c5d212..00000000000 --- a/sys/gnu/dts/arm/armada-385-turris-omnia.dts +++ /dev/null @@ -1,359 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Device Tree file for the Turris Omnia - * - * Copyright (C) 2016 Uwe Kleine-König - * Copyright (C) 2016 Tomas Hlavacek - * - * Schematic available at https://www.turris.cz/doc/_media/rtrom01-schema.pdf - */ - -/dts-v1/; - -#include -#include -#include "armada-385.dtsi" - -/ { - model = "Turris Omnia"; - compatible = "cznic,turris-omnia", "marvell,armada385", "marvell,armada380"; - - chosen { - stdout-path = &uart0; - }; - - memory { - device_type = "memory"; - reg = <0x00000000 0x40000000>; /* 1024 MB */ - }; - - soc { - ranges = ; - - internal-regs { - - /* USB part of the PCIe2/USB 2.0 port */ - usb@58000 { - status = "okay"; - }; - - sata@a8000 { - status = "okay"; - }; - - sdhci@d8000 { - pinctrl-names = "default"; - pinctrl-0 = <&sdhci_pins>; - status = "okay"; - - bus-width = <8>; - no-1-8-v; - non-removable; - }; - - usb3@f0000 { - status = "okay"; - }; - - usb3@f8000 { - status = "okay"; - }; - }; - - pcie { - status = "okay"; - - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - - pcie@2,0 { - /* Port 1, Lane 0 */ - status = "okay"; - }; - - pcie@3,0 { - /* Port 2, Lane 0 */ - status = "okay"; - }; - }; - }; -}; - -/* Connected to 88E6176 switch, port 6 */ -ð0 { - pinctrl-names = "default"; - pinctrl-0 = <&ge0_rgmii_pins>; - status = "okay"; - phy-mode = "rgmii"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -/* Connected to 88E6176 switch, port 5 */ -ð1 { - pinctrl-names = "default"; - pinctrl-0 = <&ge1_rgmii_pins>; - status = "okay"; - phy-mode = "rgmii"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -/* WAN port */ -ð2 { - status = "okay"; - phy-mode = "sgmii"; - phy = <&phy1>; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - status = "okay"; - - i2cmux@70 { - compatible = "nxp,pca9547"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x70>; - status = "okay"; - - i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - /* STM32F0 command interface at address 0x2a */ - /* leds device (in STM32F0) at address 0x2b */ - - eeprom@54 { - compatible = "atmel,24c64"; - reg = <0x54>; - - /* The EEPROM contains data for bootloader. - * Contents: - * struct omnia_eeprom { - * u32 magic; (=0x0341a034 in LE) - * u32 ramsize; (in GiB) - * char regdomain[4]; - * u32 crc32; - * }; - */ - }; - }; - - i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - /* routed to PCIe0/mSATA connector (CN7A) */ - }; - - i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - - /* routed to PCIe1/USB2 connector (CN61A) */ - }; - - i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - - /* routed to PCIe2 connector (CN62A) */ - }; - - i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - - /* routed to SFP+ */ - }; - - i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - - /* ATSHA204A at address 0x64 */ - }; - - i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - - /* exposed on pin header */ - }; - - i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - - pcawan: gpio@71 { - /* - * GPIO expander for SFP+ signals and - * and phy irq - */ - compatible = "nxp,pca9538"; - reg = <0x71>; - - pinctrl-names = "default"; - pinctrl-0 = <&pcawan_pins>; - - interrupt-parent = <&gpio1>; - interrupts = <14 IRQ_TYPE_LEVEL_LOW>; - - gpio-controller; - #gpio-cells = <2>; - }; - }; - }; -}; - -&mdio { - pinctrl-names = "default"; - pinctrl-0 = <&mdio_pins>; - status = "okay"; - - phy1: phy@1 { - status = "okay"; - compatible = "ethernet-phy-id0141.0DD1", "ethernet-phy-ieee802.3-c22"; - reg = <1>; - - /* irq is connected to &pcawan pin 7 */ - }; - - /* Switch MV88E6176 at address 0x10 */ - switch@10 { - compatible = "marvell,mv88e6085"; - #address-cells = <1>; - #size-cells = <0>; - dsa,member = <0 0>; - - reg = <0x10>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - ports@0 { - reg = <0>; - label = "lan0"; - }; - - ports@1 { - reg = <1>; - label = "lan1"; - }; - - ports@2 { - reg = <2>; - label = "lan2"; - }; - - ports@3 { - reg = <3>; - label = "lan3"; - }; - - ports@4 { - reg = <4>; - label = "lan4"; - }; - - ports@5 { - reg = <5>; - label = "cpu"; - ethernet = <ð1>; - phy-mode = "rgmii-id"; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - - /* port 6 is connected to eth0 */ - }; - }; -}; - -&pinctrl { - pcawan_pins: pcawan-pins { - marvell,pins = "mpp46"; - marvell,function = "gpio"; - }; - - spi0cs0_pins: spi0cs0-pins { - marvell,pins = "mpp25"; - marvell,function = "spi0"; - }; - - spi0cs1_pins: spi0cs1-pins { - marvell,pins = "mpp26"; - marvell,function = "spi0"; - }; -}; - -&spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins &spi0cs0_pins>; - status = "okay"; - - spi-nor@0 { - compatible = "spansion,s25fl164k", "jedec,spi-nor"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0>; - spi-max-frequency = <40000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - reg = <0x0 0x00100000>; - label = "U-Boot"; - }; - - partition@100000 { - reg = <0x00100000 0x00700000>; - label = "Rescue system"; - }; - }; - }; - - /* MISO, MOSI, SCLK and CS1 are routed to pin header CN11 */ -}; - -&uart0 { - /* Pin header CN10 */ - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - status = "okay"; -}; - -&uart1 { - /* Pin header CN11 */ - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/armada-385.dtsi b/sys/gnu/dts/arm/armada-385.dtsi deleted file mode 100644 index f0022d10c71..00000000000 --- a/sys/gnu/dts/arm/armada-385.dtsi +++ /dev/null @@ -1,149 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree Include file for Marvell Armada 385 SoC. - * - * Copyright (C) 2014 Marvell - * - * Lior Amsalem - * Gregory CLEMENT - * Thomas Petazzoni - */ - -#include "armada-38x.dtsi" - -/ { - model = "Marvell Armada 385 family SoC"; - compatible = "marvell,armada385", "marvell,armada380"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "marvell,armada-380-smp"; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - }; - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <1>; - }; - }; - - soc { - pciec: pcie { - compatible = "marvell,armada-370-pcie"; - status = "disabled"; - device_type = "pci"; - - #address-cells = <3>; - #size-cells = <2>; - - msi-parent = <&mpic>; - bus-range = <0x00 0xff>; - - ranges = - <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 - 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 - 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 - 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 - 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */ - 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */ - 0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */ - 0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */ - 0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */ - 0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */ - 0x82000000 0x4 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 3 MEM */ - 0x81000000 0x4 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 3 IO */>; - - /* - * This port can be either x4 or x1. When - * configured in x4 by the bootloader, then - * pcie@4,0 is not available. - */ - pcie1: pcie@1,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x80000 0 0x2000>; - reg = <0x0800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 - 0x81000000 0 0 0x81000000 0x1 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 8>; - status = "disabled"; - }; - - /* x1 port */ - pcie2: pcie@2,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; - reg = <0x1000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 - 0x81000000 0 0 0x81000000 0x2 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; - marvell,pcie-port = <1>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 5>; - status = "disabled"; - }; - - /* x1 port */ - pcie3: pcie@3,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; - reg = <0x1800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 - 0x81000000 0 0 0x81000000 0x3 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; - marvell,pcie-port = <2>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 6>; - status = "disabled"; - }; - - /* - * x1 port only available when pcie@1,0 is - * configured as a x1 port - */ - pcie4: pcie@4,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x48000 0 0x2000>; - reg = <0x2000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 - 0x81000000 0 0 0x81000000 0x4 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; - marvell,pcie-port = <3>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 7>; - status = "disabled"; - }; - }; - }; -}; - -&pinctrl { - compatible = "marvell,mv88f6820-pinctrl"; -}; diff --git a/sys/gnu/dts/arm/armada-388-clearfog-base.dts b/sys/gnu/dts/arm/armada-388-clearfog-base.dts deleted file mode 100644 index 53b4bd35522..00000000000 --- a/sys/gnu/dts/arm/armada-388-clearfog-base.dts +++ /dev/null @@ -1,68 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Device Tree file for SolidRun Clearfog Base revision A1 rev 2.0 (88F6828) - * - * Copyright (C) 2015 Russell King - */ - -/dts-v1/; -#include "armada-388-clearfog.dtsi" - -/ { - model = "SolidRun Clearfog Base A1"; - compatible = "solidrun,clearfog-base-a1", - "solidrun,clearfog-a1", "marvell,armada388", - "marvell,armada385", "marvell,armada380"; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-0 = <&rear_button_pins>; - pinctrl-names = "default"; - - button_0 { - /* The rear SW3 button */ - label = "Rear Button"; - gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; - linux,can-disable; - linux,code = ; - }; - }; -}; - -ð1 { - phy = <&phy1>; -}; - -&gpio0 { - phy1_reset { - gpio-hog; - gpios = <19 GPIO_ACTIVE_LOW>; - output-low; - line-name = "phy1-reset"; - }; -}; - -&mdio { - pinctrl-0 = <&mdio_pins µsom_phy_clk_pins &clearfog_phy_pins>; - phy1: ethernet-phy@1 { - /* - * Annoyingly, the marvell phy driver configures the LED - * register, rather than preserving reset-loaded setting. - * We undo that rubbish here. - */ - marvell,reg-init = <3 16 0 0x101e>; - reg = <1>; - }; -}; - -&pinctrl { - /* phy1 reset */ - clearfog_phy_pins: clearfog-phy-pins { - marvell,pins = "mpp19"; - marvell,function = "gpio"; - }; - rear_button_pins: rear-button-pins { - marvell,pins = "mpp44"; - marvell,function = "gpio"; - }; -}; diff --git a/sys/gnu/dts/arm/armada-388-clearfog-pro.dts b/sys/gnu/dts/arm/armada-388-clearfog-pro.dts deleted file mode 100644 index ff890c09c3e..00000000000 --- a/sys/gnu/dts/arm/armada-388-clearfog-pro.dts +++ /dev/null @@ -1,14 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Device Tree file for SolidRun Clearfog Pro revision A1 rev 2.0 (88F6828) - * - * Copyright (C) 2015 Russell King - */ -#include "armada-388-clearfog.dts" - -/ { - model = "SolidRun Clearfog Pro A1"; - compatible = "solidrun,clearfog-pro-a1", - "solidrun,clearfog-a1", "marvell,armada388", - "marvell,armada385", "marvell,armada380"; -}; diff --git a/sys/gnu/dts/arm/armada-388-clearfog.dts b/sys/gnu/dts/arm/armada-388-clearfog.dts deleted file mode 100644 index 20f8d466775..00000000000 --- a/sys/gnu/dts/arm/armada-388-clearfog.dts +++ /dev/null @@ -1,180 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Device Tree file for SolidRun Clearfog Pro revision A1 rev 2.0 (88F6828) - * - * Copyright (C) 2015 Russell King - */ - -/dts-v1/; -#include "armada-388-clearfog.dtsi" - -/ { - model = "SolidRun Clearfog A1"; - compatible = "solidrun,clearfog-a1", "marvell,armada388", - "marvell,armada385", "marvell,armada380"; - - soc { - internal-regs { - usb3@f0000 { - /* CON2, nearest CPU, USB2 only. */ - status = "okay"; - }; - }; - - pcie { - pcie@3,0 { - /* Port 2, Lane 0. CON2, nearest CPU. */ - reset-gpios = <&expander0 2 GPIO_ACTIVE_LOW>; - status = "okay"; - }; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-0 = <&rear_button_pins>; - pinctrl-names = "default"; - - button_0 { - /* The rear SW3 button */ - label = "Rear Button"; - gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; - linux,can-disable; - linux,code = ; - }; - }; -}; - -ð1 { - /* ethernet@30000 */ - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&expander0 { - /* - * PCA9655 GPIO expander: - * 0-CON3 CLKREQ# - * 1-CON3 PERST# - * 2-CON2 PERST# - * 3-CON3 W_DISABLE - * 4-CON2 CLKREQ# - * 5-USB3 overcurrent - * 6-USB3 power - * 7-CON2 W_DISABLE - * 8-JP4 P1 - * 9-JP4 P4 - * 10-JP4 P5 - * 11-m.2 DEVSLP - * 12-SFP_LOS - * 13-SFP_TX_FAULT - * 14-SFP_TX_DISABLE - * 15-SFP_MOD_DEF0 - */ - pcie2_0_clkreq { - gpio-hog; - gpios = <4 GPIO_ACTIVE_LOW>; - input; - line-name = "pcie2.0-clkreq"; - }; - pcie2_0_w_disable { - gpio-hog; - gpios = <7 GPIO_ACTIVE_LOW>; - output-low; - line-name = "pcie2.0-w-disable"; - }; -}; - -&mdio { - status = "okay"; - - switch@4 { - compatible = "marvell,mv88e6085"; - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - pinctrl-0 = <&clearfog_dsa0_clk_pins &clearfog_dsa0_pins>; - pinctrl-names = "default"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "lan5"; - }; - - port@1 { - reg = <1>; - label = "lan4"; - }; - - port@2 { - reg = <2>; - label = "lan3"; - }; - - port@3 { - reg = <3>; - label = "lan2"; - }; - - port@4 { - reg = <4>; - label = "lan1"; - }; - - port@5 { - reg = <5>; - label = "cpu"; - ethernet = <ð1>; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - - port@6 { - /* 88E1512 external phy */ - reg = <6>; - label = "lan6"; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; - }; -}; - -&pinctrl { - clearfog_dsa0_clk_pins: clearfog-dsa0-clk-pins { - marvell,pins = "mpp46"; - marvell,function = "ref"; - }; - clearfog_dsa0_pins: clearfog-dsa0-pins { - marvell,pins = "mpp23", "mpp41"; - marvell,function = "gpio"; - }; - clearfog_spi1_cs_pins: spi1-cs-pins { - marvell,pins = "mpp55"; - marvell,function = "spi1"; - }; - rear_button_pins: rear-button-pins { - marvell,pins = "mpp34"; - marvell,function = "gpio"; - }; -}; - -&spi1 { - /* - * Add SPI CS pins for clearfog: - * CS0: W25Q32 - * CS1: - * CS2: mikrobus - */ - pinctrl-0 = <&spi1_pins &clearfog_spi1_cs_pins &mikro_spi_pins>; -}; diff --git a/sys/gnu/dts/arm/armada-388-clearfog.dtsi b/sys/gnu/dts/arm/armada-388-clearfog.dtsi deleted file mode 100644 index a0aa1d188f0..00000000000 --- a/sys/gnu/dts/arm/armada-388-clearfog.dtsi +++ /dev/null @@ -1,245 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Device Tree include file for SolidRun Clearfog 88F6828 based boards - * - * Copyright (C) 2015 Russell King - */ - -#include "armada-388.dtsi" -#include "armada-38x-solidrun-microsom.dtsi" - -/ { - aliases { - /* So that mvebu u-boot can update the MAC addresses */ - ethernet1 = ð0; - ethernet2 = ð1; - ethernet3 = ð2; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - soc { - internal-regs { - sata@a8000 { - /* pinctrl? */ - status = "okay"; - }; - - sata@e0000 { - /* pinctrl? */ - status = "okay"; - }; - - sdhci@d8000 { - bus-width = <4>; - cd-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; - no-1-8-v; - pinctrl-0 = <µsom_sdhci_pins - &clearfog_sdhci_cd_pins>; - pinctrl-names = "default"; - status = "okay"; - vmmc-supply = <®_3p3v>; - wp-inverted; - }; - - usb@58000 { - /* CON3, nearest power. */ - status = "okay"; - }; - - usb3@f8000 { - /* CON7 */ - status = "okay"; - }; - }; - - pcie { - status = "okay"; - /* - * The two PCIe units are accessible through - * the mini-PCIe connectors on the board. - */ - pcie@2,0 { - /* Port 1, Lane 0. CON3, nearest power. */ - reset-gpios = <&expander0 1 GPIO_ACTIVE_LOW>; - status = "okay"; - }; - }; - }; - - sfp: sfp { - compatible = "sff,sfp"; - i2c-bus = <&i2c1>; - los-gpio = <&expander0 12 GPIO_ACTIVE_HIGH>; - mod-def0-gpio = <&expander0 15 GPIO_ACTIVE_LOW>; - tx-disable-gpio = <&expander0 14 GPIO_ACTIVE_HIGH>; - tx-fault-gpio = <&expander0 13 GPIO_ACTIVE_HIGH>; - maximum-power-milliwatt = <2000>; - }; -}; - -ð1 { - /* ethernet@30000 */ - bm,pool-long = <2>; - bm,pool-short = <1>; - buffer-manager = <&bm>; - phys = <&comphy1 1>; - phy-mode = "sgmii"; - status = "okay"; -}; - -ð2 { - /* ethernet@34000 */ - bm,pool-long = <3>; - bm,pool-short = <1>; - buffer-manager = <&bm>; - managed = "in-band-status"; - phys = <&comphy5 2>; - phy-mode = "sgmii"; - sfp = <&sfp>; - status = "okay"; -}; - -&i2c0 { - /* - * PCA9655 GPIO expander, up to 1MHz clock. - * 0-CON3 CLKREQ# - * 1-CON3 PERST# - * 2- - * 3-CON3 W_DISABLE - * 4- - * 5-USB3 overcurrent - * 6-USB3 power - * 7- - * 8-JP4 P1 - * 9-JP4 P4 - * 10-JP4 P5 - * 11-m.2 DEVSLP - * 12-SFP_LOS - * 13-SFP_TX_FAULT - * 14-SFP_TX_DISABLE - * 15-SFP_MOD_DEF0 - */ - expander0: gpio-expander@20 { - /* - * This is how it should be: - * compatible = "onnn,pca9655", "nxp,pca9555"; - * but you can't do this because of the way I2C works. - */ - compatible = "nxp,pca9555"; - gpio-controller; - #gpio-cells = <2>; - reg = <0x20>; - - pcie1_0_clkreq { - gpio-hog; - gpios = <0 GPIO_ACTIVE_LOW>; - input; - line-name = "pcie1.0-clkreq"; - }; - pcie1_0_w_disable { - gpio-hog; - gpios = <3 GPIO_ACTIVE_LOW>; - output-low; - line-name = "pcie1.0-w-disable"; - }; - usb3_ilimit { - gpio-hog; - gpios = <5 GPIO_ACTIVE_LOW>; - input; - line-name = "usb3-current-limit"; - }; - usb3_power { - gpio-hog; - gpios = <6 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "usb3-power"; - }; - m2_devslp { - gpio-hog; - gpios = <11 GPIO_ACTIVE_HIGH>; - output-low; - line-name = "m.2 devslp"; - }; - }; - - /* The MCP3021 supports standard and fast modes */ - mikrobus_adc: mcp3021@4c { - compatible = "microchip,mcp3021"; - reg = <0x4c>; - }; - - eeprom@52 { - compatible = "atmel,24c02"; - reg = <0x52>; - pagesize = <16>; - }; -}; - -&i2c1 { - /* - * Routed to SFP, mikrobus, and PCIe. - * SFP limits this to 100kHz, and requires an AT24C01A/02/04 with - * address pins tied low, which takes addresses 0x50 and 0x51. - * Mikrobus doesn't specify beyond an I2C bus being present. - * PCIe uses ARP to assign addresses, or 0x63-0x64. - */ - clock-frequency = <100000>; - pinctrl-0 = <&clearfog_i2c1_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&pinctrl { - clearfog_i2c1_pins: i2c1-pins { - /* SFP, PCIe, mSATA, mikrobus */ - marvell,pins = "mpp26", "mpp27"; - marvell,function = "i2c1"; - }; - clearfog_sdhci_cd_pins: clearfog-sdhci-cd-pins { - marvell,pins = "mpp20"; - marvell,function = "gpio"; - }; - mikro_pins: mikro-pins { - /* int: mpp22 rst: mpp29 */ - marvell,pins = "mpp22", "mpp29"; - marvell,function = "gpio"; - }; - mikro_spi_pins: mikro-spi-pins { - marvell,pins = "mpp43"; - marvell,function = "spi1"; - }; - mikro_uart_pins: mikro-uart-pins { - marvell,pins = "mpp24", "mpp25"; - marvell,function = "ua1"; - }; -}; - -&spi1 { - /* - * Add SPI CS pins for clearfog: - * CS0: W25Q32 - * CS1: PIC microcontroller (Pro models) - * CS2: mikrobus - */ - pinctrl-0 = <&spi1_pins &mikro_spi_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&uart1 { - /* mikrobus uart */ - pinctrl-0 = <&mikro_uart_pins>; - pinctrl-names = "default"; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/armada-388-db.dts b/sys/gnu/dts/arm/armada-388-db.dts deleted file mode 100644 index a2bec07bf4c..00000000000 --- a/sys/gnu/dts/arm/armada-388-db.dts +++ /dev/null @@ -1,176 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for Marvell Armada 388 evaluation board - * (DB-88F6820) - * - * Copyright (C) 2014 Marvell - * - * Thomas Petazzoni - */ - -/dts-v1/; -#include "armada-388.dtsi" - -/ { - model = "Marvell Armada 385 Development Board"; - compatible = "marvell,a385-db", "marvell,armada388", - "marvell,armada385", "marvell,armada380"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - device_type = "memory"; - reg = <0x00000000 0x10000000>; /* 256 MB */ - }; - - soc { - ranges = ; - - internal-regs { - i2c@11000 { - status = "okay"; - clock-frequency = <100000>; - }; - - i2c@11100 { - status = "okay"; - clock-frequency = <100000>; - }; - - serial@12000 { - status = "okay"; - }; - - ethernet@30000 { - status = "okay"; - phy = <&phy1>; - phy-mode = "rgmii-id"; - buffer-manager = <&bm>; - bm,pool-long = <2>; - bm,pool-short = <3>; - }; - - usb@58000 { - status = "ok"; - }; - - ethernet@70000 { - status = "okay"; - phy = <&phy0>; - phy-mode = "rgmii-id"; - buffer-manager = <&bm>; - bm,pool-long = <0>; - bm,pool-short = <1>; - }; - - mdio@72004 { - phy0: ethernet-phy@0 { - reg = <0>; - }; - - phy1: ethernet-phy@1 { - reg = <1>; - }; - }; - - sata@a8000 { - status = "okay"; - }; - - sata@e0000 { - status = "okay"; - }; - - bm@c8000 { - status = "okay"; - }; - - sdhci@d8000 { - broken-cd; - wp-inverted; - bus-width = <8>; - status = "okay"; - no-1-8-v; - }; - - usb3@f0000 { - status = "okay"; - }; - - usb3@f8000 { - status = "okay"; - }; - }; - - bm-bppi { - status = "okay"; - }; - - pcie { - status = "okay"; - /* - * The two PCIe units are accessible through - * standard PCIe slots on the board. - */ - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - pcie@2,0 { - /* Port 1, Lane 0 */ - status = "okay"; - }; - }; - }; -}; - -&spi0 { - status = "okay"; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "w25q32", "jedec,spi-nor"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <108000000>; - }; -}; - -&nand_controller { - status = "okay"; - - nand@0 { - reg = <0>; - label = "pxa3xx_nand-0"; - nand-rb = <0>; - marvell,nand-keep-config; - nand-on-flash-bbt; - nand-ecc-strength = <4>; - nand-ecc-step-size = <512>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "U-Boot"; - reg = <0 0x800000>; - }; - partition@800000 { - label = "Linux"; - reg = <0x800000 0x800000>; - }; - partition@1000000 { - label = "Filesystem"; - reg = <0x1000000 0x3f000000>; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/armada-388-gp.dts b/sys/gnu/dts/arm/armada-388-gp.dts deleted file mode 100644 index 9d873257ac4..00000000000 --- a/sys/gnu/dts/arm/armada-388-gp.dts +++ /dev/null @@ -1,406 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Device Tree file for Marvell Armada 385 development board - * (RD-88F6820-GP) - * - * Copyright (C) 2014 Marvell - * - * Gregory CLEMENT - */ - -/dts-v1/; -#include "armada-388.dtsi" -#include - -/ { - model = "Marvell Armada 388 DB-88F6820-GP"; - compatible = "marvell,a388-gp", "marvell,armada388", "marvell,armada380"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - device_type = "memory"; - reg = <0x00000000 0x80000000>; /* 2 GB */ - }; - - soc { - ranges = ; - - internal-regs { - i2c@11000 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - status = "okay"; - clock-frequency = <100000>; - - expander0: pca9555@20 { - compatible = "nxp,pca9555"; - pinctrl-names = "default"; - pinctrl-0 = <&pca0_pins>; - interrupt-parent = <&gpio0>; - interrupts = <18 IRQ_TYPE_LEVEL_LOW>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x20>; - }; - - expander1: pca9555@21 { - compatible = "nxp,pca9555"; - pinctrl-names = "default"; - interrupt-parent = <&gpio0>; - interrupts = <18 IRQ_TYPE_LEVEL_LOW>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x21>; - }; - - eeprom@57 { - compatible = "atmel,24c64"; - reg = <0x57>; - }; - }; - - serial@12000 { - /* - * Exported on the micro USB connector CON16 - * through an FTDI - */ - - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - status = "okay"; - }; - - /* GE1 CON15 */ - ethernet@30000 { - pinctrl-names = "default"; - pinctrl-0 = <&ge1_rgmii_pins>; - status = "okay"; - phy = <&phy1>; - phy-mode = "rgmii-id"; - buffer-manager = <&bm>; - bm,pool-long = <2>; - bm,pool-short = <3>; - }; - - /* CON4 */ - usb@58000 { - vcc-supply = <®_usb2_0_vbus>; - status = "okay"; - }; - - /* GE0 CON1 */ - ethernet@70000 { - pinctrl-names = "default"; - /* - * The Reference Clock 0 is used to provide a - * clock to the PHY - */ - pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>; - status = "okay"; - phy = <&phy0>; - phy-mode = "rgmii-id"; - buffer-manager = <&bm>; - bm,pool-long = <0>; - bm,pool-short = <1>; - }; - - - mdio@72004 { - pinctrl-names = "default"; - pinctrl-0 = <&mdio_pins>; - - phy0: ethernet-phy@1 { - reg = <1>; - }; - - phy1: ethernet-phy@0 { - reg = <0>; - }; - }; - - sata@a8000 { - pinctrl-names = "default"; - pinctrl-0 = <&sata0_pins>, <&sata1_pins>; - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - - sata0: sata-port@0 { - reg = <0>; - target-supply = <®_5v_sata0>; - }; - - sata1: sata-port@1 { - reg = <1>; - target-supply = <®_5v_sata1>; - }; - }; - - bm@c8000 { - status = "okay"; - }; - - sata@e0000 { - pinctrl-names = "default"; - pinctrl-0 = <&sata2_pins>, <&sata3_pins>; - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - - sata2: sata-port@0 { - reg = <0>; - target-supply = <®_5v_sata2>; - }; - - sata3: sata-port@1 { - reg = <1>; - target-supply = <®_5v_sata3>; - }; - }; - - sdhci@d8000 { - pinctrl-names = "default"; - pinctrl-0 = <&sdhci_pins>; - no-1-8-v; - /* - * A388-GP board v1.5 and higher replace - * hitherto card detection method based on GPIO - * with the one using DAT3 pin. As they are - * incompatible, software-based polling is - * enabled with 'broken-cd' property. For boards - * older than v1.5 it can be replaced with: - * 'cd-gpios = <&expander0 5 GPIO_ACTIVE_LOW>;', - * whereas for the newer ones following can be - * used instead: - * 'dat3-cd;' - * 'cd-inverted;' - */ - broken-cd; - wp-inverted; - bus-width = <8>; - status = "okay"; - }; - - /* CON5 */ - usb3@f0000 { - usb-phy = <&usb2_1_phy>; - status = "okay"; - }; - - /* CON7 */ - usb3@f8000 { - usb-phy = <&usb3_phy>; - status = "okay"; - }; - }; - - bm-bppi { - status = "okay"; - }; - - pcie { - status = "okay"; - /* - * One PCIe units is accessible through - * standard PCIe slot on the board. - */ - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - - /* - * The two other PCIe units are accessible - * through mini PCIe slot on the board. - */ - pcie@2,0 { - /* Port 1, Lane 0 */ - status = "okay"; - }; - pcie@3,0 { - /* Port 2, Lane 0 */ - status = "okay"; - }; - }; - - gpio-fan { - compatible = "gpio-fan"; - gpios = <&expander1 3 GPIO_ACTIVE_HIGH>; - gpio-fan,speed-map = < 0 0 - 3000 1>; - }; - }; - - usb2_1_phy: usb2_1_phy { - compatible = "usb-nop-xceiv"; - vcc-supply = <®_usb2_1_vbus>; - #phy-cells = <0>; - }; - - usb3_phy: usb3_phy { - compatible = "usb-nop-xceiv"; - vcc-supply = <®_usb3_vbus>; - #phy-cells = <0>; - }; - - reg_usb3_vbus: usb3-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb3-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&expander1 15 GPIO_ACTIVE_HIGH>; - }; - - reg_usb2_0_vbus: v5-vbus0 { - compatible = "regulator-fixed"; - regulator-name = "v5.0-vbus0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - gpio = <&expander1 14 GPIO_ACTIVE_HIGH>; - }; - - reg_usb2_1_vbus: v5-vbus1 { - compatible = "regulator-fixed"; - regulator-name = "v5.0-vbus1"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&expander0 4 GPIO_ACTIVE_HIGH>; - }; - - reg_sata0: pwr-sata0 { - compatible = "regulator-fixed"; - regulator-name = "pwr_en_sata0"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - enable-active-high; - regulator-boot-on; - gpio = <&expander0 2 GPIO_ACTIVE_HIGH>; - }; - - reg_5v_sata0: v5-sata0 { - compatible = "regulator-fixed"; - regulator-name = "v5.0-sata0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <®_sata0>; - }; - - reg_12v_sata0: v12-sata0 { - compatible = "regulator-fixed"; - regulator-name = "v12.0-sata0"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - vin-supply = <®_sata0>; - }; - - reg_sata1: pwr-sata1 { - regulator-name = "pwr_en_sata1"; - compatible = "regulator-fixed"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - enable-active-high; - regulator-boot-on; - gpio = <&expander0 3 GPIO_ACTIVE_HIGH>; - }; - - reg_5v_sata1: v5-sata1 { - compatible = "regulator-fixed"; - regulator-name = "v5.0-sata1"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <®_sata1>; - }; - - reg_12v_sata1: v12-sata1 { - compatible = "regulator-fixed"; - regulator-name = "v12.0-sata1"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - vin-supply = <®_sata1>; - }; - - reg_sata2: pwr-sata2 { - compatible = "regulator-fixed"; - regulator-name = "pwr_en_sata2"; - enable-active-high; - regulator-boot-on; - gpio = <&expander0 11 GPIO_ACTIVE_HIGH>; - }; - - reg_5v_sata2: v5-sata2 { - compatible = "regulator-fixed"; - regulator-name = "v5.0-sata2"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <®_sata2>; - }; - - reg_12v_sata2: v12-sata2 { - compatible = "regulator-fixed"; - regulator-name = "v12.0-sata2"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - vin-supply = <®_sata2>; - }; - - reg_sata3: pwr-sata3 { - compatible = "regulator-fixed"; - regulator-name = "pwr_en_sata3"; - enable-active-high; - regulator-boot-on; - gpio = <&expander0 12 GPIO_ACTIVE_HIGH>; - }; - - reg_5v_sata3: v5-sata3 { - compatible = "regulator-fixed"; - regulator-name = "v5.0-sata3"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <®_sata3>; - }; - - reg_12v_sata3: v12-sata3 { - compatible = "regulator-fixed"; - regulator-name = "v12.0-sata3"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - vin-supply = <®_sata3>; - }; -}; - -&pinctrl { - pca0_pins: pca0_pins { - marvell,pins = "mpp18"; - marvell,function = "gpio"; - }; -}; - -&spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins>; - status = "okay"; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,m25p128", "jedec,spi-nor"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <50000000>; - m25p,fast-read; - }; -}; diff --git a/sys/gnu/dts/arm/armada-388-helios4.dts b/sys/gnu/dts/arm/armada-388-helios4.dts deleted file mode 100644 index fb49df2a3bc..00000000000 --- a/sys/gnu/dts/arm/armada-388-helios4.dts +++ /dev/null @@ -1,308 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Device Tree file for Helios4 - * based on SolidRun Clearfog revision A1 rev 2.0 (88F6828) - * - * Copyright (C) 2017 Aditya Prayoga - * - */ - -/dts-v1/; -#include "armada-388.dtsi" -#include "armada-38x-solidrun-microsom.dtsi" - -/ { - model = "Helios4"; - compatible = "kobol,helios4", "marvell,armada388", - "marvell,armada385", "marvell,armada380"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x80000000>; /* 2 GB */ - }; - - aliases { - /* So that mvebu u-boot can update the MAC addresses */ - ethernet1 = ð0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - reg_12v: regulator-12v { - compatible = "regulator-fixed"; - regulator-name = "power_brick_12V"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-always-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - vin-supply = <®_12v>; - }; - - reg_5p0v_hdd: regulator-5v-hdd { - compatible = "regulator-fixed"; - regulator-name = "5V_HDD"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - vin-supply = <®_12v>; - }; - - reg_5p0v_usb: regulator-5v-usb { - compatible = "regulator-fixed"; - regulator-name = "USB-PWR"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - regulator-always-on; - enable-active-high; - gpio = <&expander0 6 GPIO_ACTIVE_HIGH>; - vin-supply = <®_12v>; - }; - - system-leds { - compatible = "gpio-leds"; - status-led { - label = "helios4:green:status"; - gpios = <&gpio0 24 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - default-state = "on"; - }; - - fault-led { - label = "helios4:red:fault"; - gpios = <&gpio0 25 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - }; - - io-leds { - compatible = "gpio-leds"; - sata1-led { - label = "helios4:green:ata1"; - gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; - linux,default-trigger = "ata1"; - default-state = "off"; - }; - sata2-led { - label = "helios4:green:ata2"; - gpios = <&gpio1 18 GPIO_ACTIVE_LOW>; - linux,default-trigger = "ata2"; - default-state = "off"; - }; - sata3-led { - label = "helios4:green:ata3"; - gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; - linux,default-trigger = "ata3"; - default-state = "off"; - }; - sata4-led { - label = "helios4:green:ata4"; - gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; - linux,default-trigger = "ata4"; - default-state = "off"; - }; - usb-led { - label = "helios4:green:usb"; - gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; - linux,default-trigger = "usb-host"; - default-state = "off"; - }; - }; - - fan1: j10-pwm { - compatible = "pwm-fan"; - pwms = <&gpio1 9 40000>; /* Target freq:25 kHz */ - }; - - fan2: j17-pwm { - compatible = "pwm-fan"; - pwms = <&gpio1 23 40000>; /* Target freq:25 kHz */ - }; - - usb2_phy: usb2-phy { - compatible = "usb-nop-xceiv"; - vbus-regulator = <®_5p0v_usb>; - }; - - usb3_phy: usb3-phy { - compatible = "usb-nop-xceiv"; - }; - - soc { - internal-regs { - i2c@11000 { - /* - * PCA9655 GPIO expander, up to 1MHz clock. - * 0-Board Revision bit 0 # - * 1-Board Revision bit 1 # - * 5-USB3 overcurrent - * 6-USB3 power - */ - expander0: gpio-expander@20 { - /* - * This is how it should be: - * compatible = "onnn,pca9655", - * "nxp,pca9555"; - * but you can't do this because of - * the way I2C works. - */ - compatible = "nxp,pca9555"; - gpio-controller; - #gpio-cells = <2>; - reg = <0x20>; - pinctrl-names = "default"; - pinctrl-0 = <&pca0_pins>; - interrupt-parent = <&gpio0>; - interrupts = <23 IRQ_TYPE_EDGE_FALLING>; - interrupt-controller; - #interrupt-cells = <2>; - - board_rev_bit_0 { - gpio-hog; - gpios = <0 GPIO_ACTIVE_LOW>; - input; - line-name = "board-rev-0"; - }; - board_rev_bit_1 { - gpio-hog; - gpios = <1 GPIO_ACTIVE_LOW>; - input; - line-name = "board-rev-1"; - }; - usb3_ilimit { - gpio-hog; - gpios = <5 GPIO_ACTIVE_HIGH>; - input; - line-name = "usb-overcurrent-status"; - }; - }; - - temp_sensor: temp@4c { - compatible = "ti,lm75"; - reg = <0x4c>; - vcc-supply = <®_3p3v>; - }; - }; - - i2c@11100 { - /* - * External I2C Bus for user peripheral - */ - clock-frequency = <400000>; - pinctrl-0 = <&helios_i2c1_pins>; - pinctrl-names = "default"; - status = "okay"; - }; - - sata@a8000 { - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - - sata0: sata-port@0 { - reg = <0>; - }; - - sata1: sata-port@1 { - reg = <1>; - }; - }; - - sata@e0000 { - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - - sata2: sata-port@0 { - reg = <0>; - }; - - sata3: sata-port@1 { - reg = <1>; - }; - }; - - spi@10680 { - pinctrl-0 = <&spi1_pins - µsom_spi1_cs_pins>; - pinctrl-names = "default"; - status = "okay"; - }; - - sdhci@d8000 { - bus-width = <4>; - cd-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; - no-1-8-v; - pinctrl-0 = <&helios_sdhci_pins - &helios_sdhci_cd_pins>; - pinctrl-names = "default"; - status = "okay"; - vmmc = <®_3p3v>; - wp-inverted; - }; - - usb@58000 { - usb-phy = <&usb2_phy>; - status = "okay"; - }; - - usb3@f0000 { - status = "okay"; - }; - - usb3@f8000 { - status = "okay"; - }; - - pinctrl@18000 { - pca0_pins: pca0-pins { - marvell,pins = "mpp23"; - marvell,function = "gpio"; - }; - microsom_phy0_int_pins: microsom-phy0-int-pins { - marvell,pins = "mpp18"; - marvell,function = "gpio"; - }; - helios_i2c1_pins: i2c1-pins { - marvell,pins = "mpp26", "mpp27"; - marvell,function = "i2c1"; - }; - helios_sdhci_cd_pins: helios-sdhci-cd-pins { - marvell,pins = "mpp20"; - marvell,function = "gpio"; - }; - helios_sdhci_pins: helios-sdhci-pins { - marvell,pins = "mpp21", "mpp28", - "mpp37", "mpp38", - "mpp39", "mpp40"; - marvell,function = "sd0"; - }; - helios_led_pins: helios-led-pins { - marvell,pins = "mpp24", "mpp25", - "mpp49", "mpp50", - "mpp52", "mpp53", - "mpp54"; - marvell,function = "gpio"; - }; - helios_fan_pins: helios-fan-pins { - marvell,pins = "mpp41", "mpp43", - "mpp48", "mpp55"; - marvell,function = "gpio"; - }; - microsom_spi1_cs_pins: spi1-cs-pins { - marvell,pins = "mpp59"; - marvell,function = "spi1"; - }; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/armada-388-rd.dts b/sys/gnu/dts/arm/armada-388-rd.dts deleted file mode 100644 index 328a4d6afd2..00000000000 --- a/sys/gnu/dts/arm/armada-388-rd.dts +++ /dev/null @@ -1,108 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for Marvell Armada 388 Reference Design board - * (RD-88F6820-AP) - * - * Copyright (C) 2014 Marvell - * - * Gregory CLEMENT - * Thomas Petazzoni - */ - -/dts-v1/; -#include "armada-388.dtsi" - -/ { - model = "Marvell Armada 385 Reference Design"; - compatible = "marvell,a385-rd", "marvell,armada388", - "marvell,armada385","marvell,armada380"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - device_type = "memory"; - reg = <0x00000000 0x10000000>; /* 256 MB */ - }; - - soc { - ranges = ; - - internal-regs { - i2c@11000 { - status = "okay"; - clock-frequency = <100000>; - }; - - sdhci@d8000 { - pinctrl-names = "default"; - pinctrl-0 = <&sdhci_pins>; - broken-cd; - no-1-8-v; - wp-inverted; - bus-width = <8>; - status = "okay"; - }; - - serial@12000 { - status = "okay"; - }; - - ethernet@30000 { - status = "okay"; - phy = <&phy0>; - phy-mode = "rgmii-id"; - }; - - ethernet@70000 { - status = "okay"; - phy = <&phy1>; - phy-mode = "rgmii-id"; - }; - - - mdio@72004 { - phy0: ethernet-phy@0 { - reg = <0>; - }; - - phy1: ethernet-phy@1 { - reg = <1>; - }; - }; - - usb3@f0000 { - status = "okay"; - }; - }; - - pcie { - status = "okay"; - /* - * One PCIe units is accessible through - * standard PCIe slot on the board. - */ - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - }; - }; -}; - -&spi0 { - status = "okay"; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,m25p128", "jedec,spi-nor"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <108000000>; - }; -}; - diff --git a/sys/gnu/dts/arm/armada-388.dtsi b/sys/gnu/dts/arm/armada-388.dtsi deleted file mode 100644 index f3a020ff577..00000000000 --- a/sys/gnu/dts/arm/armada-388.dtsi +++ /dev/null @@ -1,37 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree Include file for Marvell Armada 388 SoC. - * - * Copyright (C) 2015 Marvell - * - * Gregory CLEMENT - * - * The main difference with the Armada 385 is that the 388 can handle two more - * SATA ports. So we can reuse the dtsi of the Armada 385, override the pinctrl - * property and the name of the SoC, and add the second SATA host which control - * the 2 other ports. - */ - -#include "armada-385.dtsi" - -/ { - model = "Marvell Armada 388 family SoC"; - compatible = "marvell,armada388", "marvell,armada385", - "marvell,armada380"; - soc { - internal-regs { - sata@e0000 { - compatible = "marvell,armada-380-ahci"; - reg = <0xe0000 0x2000>; - interrupts = ; - clocks = <&gateclk 30>; - status = "disabled"; - }; - - }; - }; -}; - -&pinctrl { - compatible = "marvell,mv88f6828-pinctrl"; -}; diff --git a/sys/gnu/dts/arm/armada-38x-solidrun-microsom.dtsi b/sys/gnu/dts/arm/armada-38x-solidrun-microsom.dtsi deleted file mode 100644 index 363ac423885..00000000000 --- a/sys/gnu/dts/arm/armada-38x-solidrun-microsom.dtsi +++ /dev/null @@ -1,117 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Device Tree file for SolidRun Armada 38x Microsom - * - * Copyright (C) 2015 Russell King - */ -#include -#include - -/ { - memory { - device_type = "memory"; - reg = <0x00000000 0x10000000>; /* 256 MB */ - }; - - soc { - ranges = ; - - internal-regs { - rtc@a3800 { - /* - * If the rtc doesn't work, run "date reset" - * twice in u-boot. - */ - status = "okay"; - }; - }; - }; -}; - -&bm { - status = "okay"; -}; - -&bm_bppi { - status = "okay"; -}; - -ð0 { - /* ethernet@70000 */ - pinctrl-0 = <&ge0_rgmii_pins>; - pinctrl-names = "default"; - phy = <&phy_dedicated>; - phy-mode = "rgmii-id"; - buffer-manager = <&bm>; - bm,pool-long = <0>; - bm,pool-short = <1>; - status = "okay"; -}; - -&mdio { - /* - * Add the phy clock here, so the phy can be accessed to read its - * IDs prior to binding with the driver. - */ - pinctrl-0 = <&mdio_pins µsom_phy_clk_pins>; - pinctrl-names = "default"; - - phy_dedicated: ethernet-phy@0 { - /* - * Annoyingly, the marvell phy driver configures the LED - * register, rather than preserving reset-loaded setting. - * We undo that rubbish here. - */ - marvell,reg-init = <3 16 0 0x101e>; - reg = <0>; - }; -}; - -&i2c0 { - clock-frequency = <400000>; - pinctrl-0 = <&i2c0_pins>; - pinctrl-names = "default"; - status = "okay"; - - eeprom@53 { - compatible = "atmel,24c02"; - reg = <0x53>; - pagesize = <16>; - }; -}; - -&pinctrl { - microsom_phy_clk_pins: microsom-phy-clk-pins { - marvell,pins = "mpp45"; - marvell,function = "ref"; - }; - /* Optional eMMC */ - microsom_sdhci_pins: microsom-sdhci-pins { - marvell,pins = "mpp21", "mpp28", "mpp37", - "mpp38", "mpp39", "mpp40"; - marvell,function = "sd0"; - }; -}; - -&spi1 { - /* The microsom has an optional W25Q32 on board, connected to CS0 */ - pinctrl-0 = <&spi1_pins>; - - w25q32: spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "w25q32", "jedec,spi-nor"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <3000000>; - }; -}; - -&uart0 { - pinctrl-0 = <&uart0_pins>; - pinctrl-names = "default"; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/armada-38x.dtsi b/sys/gnu/dts/arm/armada-38x.dtsi deleted file mode 100644 index e038abc0c6b..00000000000 --- a/sys/gnu/dts/arm/armada-38x.dtsi +++ /dev/null @@ -1,708 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree Include file for Marvell Armada 38x family of SoCs. - * - * Copyright (C) 2014 Marvell - * - * Lior Amsalem - * Gregory CLEMENT - * Thomas Petazzoni - */ - -#include -#include - -#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) - -/ { - #address-cells = <1>; - #size-cells = <1>; - - model = "Marvell Armada 38x family SoC"; - compatible = "marvell,armada380"; - - aliases { - gpio0 = &gpio0; - gpio1 = &gpio1; - serial0 = &uart0; - serial1 = &uart1; - }; - - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts-extended = <&mpic 3>; - }; - - soc { - compatible = "marvell,armada380-mbus", "simple-bus"; - #address-cells = <2>; - #size-cells = <1>; - controller = <&mbusc>; - interrupt-parent = <&gic>; - pcie-mem-aperture = <0xe0000000 0x8000000>; - pcie-io-aperture = <0xe8000000 0x100000>; - - bootrom { - compatible = "marvell,bootrom"; - reg = ; - }; - - devbus_bootcs: devbus-bootcs { - compatible = "marvell,mvebu-devbus"; - reg = ; - ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - devbus_cs0: devbus-cs0 { - compatible = "marvell,mvebu-devbus"; - reg = ; - ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - devbus_cs1: devbus-cs1 { - compatible = "marvell,mvebu-devbus"; - reg = ; - ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - devbus_cs2: devbus-cs2 { - compatible = "marvell,mvebu-devbus"; - reg = ; - ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - devbus_cs3: devbus-cs3 { - compatible = "marvell,mvebu-devbus"; - reg = ; - ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - internal-regs { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>; - - sdramc: sdramc@1400 { - compatible = "marvell,armada-xp-sdram-controller"; - reg = <0x1400 0x500>; - }; - - L2: cache-controller@8000 { - compatible = "arm,pl310-cache"; - reg = <0x8000 0x1000>; - cache-unified; - cache-level = <2>; - arm,double-linefill-incr = <0>; - arm,double-linefill-wrap = <0>; - arm,double-linefill = <0>; - prefetch-data = <1>; - }; - - scu@c000 { - compatible = "arm,cortex-a9-scu"; - reg = <0xc000 0x58>; - }; - - timer@c200 { - compatible = "arm,cortex-a9-global-timer"; - reg = <0xc200 0x20>; - interrupts = ; - clocks = <&coreclk 2>; - }; - - timer@c600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0xc600 0x20>; - interrupts = ; - clocks = <&coreclk 2>; - }; - - gic: interrupt-controller@d000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #size-cells = <0>; - interrupt-controller; - reg = <0xd000 0x1000>, - <0xc100 0x100>; - }; - - i2c0: i2c@11000 { - compatible = "marvell,mv78230-a0-i2c", "marvell,mv64xxx-i2c"; - reg = <0x11000 0x20>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - timeout-ms = <1000>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - i2c1: i2c@11100 { - compatible = "marvell,mv78230-a0-i2c", "marvell,mv64xxx-i2c"; - reg = <0x11100 0x20>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - timeout-ms = <1000>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - uart0: serial@12000 { - compatible = "marvell,armada-38x-uart"; - reg = <0x12000 0x100>; - reg-shift = <2>; - interrupts = ; - reg-io-width = <1>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - uart1: serial@12100 { - compatible = "marvell,armada-38x-uart"; - reg = <0x12100 0x100>; - reg-shift = <2>; - interrupts = ; - reg-io-width = <1>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - pinctrl: pinctrl@18000 { - reg = <0x18000 0x20>; - - ge0_rgmii_pins: ge-rgmii-pins-0 { - marvell,pins = "mpp6", "mpp7", "mpp8", - "mpp9", "mpp10", "mpp11", - "mpp12", "mpp13", "mpp14", - "mpp15", "mpp16", "mpp17"; - marvell,function = "ge0"; - }; - - ge1_rgmii_pins: ge-rgmii-pins-1 { - marvell,pins = "mpp21", "mpp27", "mpp28", - "mpp29", "mpp30", "mpp31", - "mpp32", "mpp37", "mpp38", - "mpp39", "mpp40", "mpp41"; - marvell,function = "ge1"; - }; - - i2c0_pins: i2c-pins-0 { - marvell,pins = "mpp2", "mpp3"; - marvell,function = "i2c0"; - }; - - mdio_pins: mdio-pins { - marvell,pins = "mpp4", "mpp5"; - marvell,function = "ge"; - }; - - ref_clk0_pins: ref-clk-pins-0 { - marvell,pins = "mpp45"; - marvell,function = "ref"; - }; - - ref_clk1_pins: ref-clk-pins-1 { - marvell,pins = "mpp46"; - marvell,function = "ref"; - }; - - spi0_pins: spi-pins-0 { - marvell,pins = "mpp22", "mpp23", "mpp24", - "mpp25"; - marvell,function = "spi0"; - }; - - spi1_pins: spi-pins-1 { - marvell,pins = "mpp56", "mpp57", "mpp58", - "mpp59"; - marvell,function = "spi1"; - }; - - nand_pins: nand-pins { - marvell,pins = "mpp22", "mpp34", "mpp23", - "mpp33", "mpp38", "mpp28", - "mpp40", "mpp42", "mpp35", - "mpp36", "mpp25", "mpp30", - "mpp32"; - marvell,function = "dev"; - }; - - nand_rb: nand-rb { - marvell,pins = "mpp41"; - marvell,function = "nand"; - }; - - uart0_pins: uart-pins-0 { - marvell,pins = "mpp0", "mpp1"; - marvell,function = "ua0"; - }; - - uart1_pins: uart-pins-1 { - marvell,pins = "mpp19", "mpp20"; - marvell,function = "ua1"; - }; - - sdhci_pins: sdhci-pins { - marvell,pins = "mpp48", "mpp49", "mpp50", - "mpp52", "mpp53", "mpp54", - "mpp55", "mpp57", "mpp58", - "mpp59"; - marvell,function = "sd0"; - }; - - sata0_pins: sata-pins-0 { - marvell,pins = "mpp20"; - marvell,function = "sata0"; - }; - - sata1_pins: sata-pins-1 { - marvell,pins = "mpp19"; - marvell,function = "sata1"; - }; - - sata2_pins: sata-pins-2 { - marvell,pins = "mpp47"; - marvell,function = "sata2"; - }; - - sata3_pins: sata-pins-3 { - marvell,pins = "mpp44"; - marvell,function = "sata3"; - }; - }; - - gpio0: gpio@18100 { - compatible = "marvell,armada-370-gpio", - "marvell,orion-gpio"; - reg = <0x18100 0x40>, <0x181c0 0x08>; - reg-names = "gpio", "pwm"; - ngpios = <32>; - gpio-controller; - #gpio-cells = <2>; - #pwm-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = , - , - , - ; - clocks = <&coreclk 0>; - }; - - gpio1: gpio@18140 { - compatible = "marvell,armada-370-gpio", - "marvell,orion-gpio"; - reg = <0x18140 0x40>, <0x181c8 0x08>; - reg-names = "gpio", "pwm"; - ngpios = <28>; - gpio-controller; - #gpio-cells = <2>; - #pwm-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = , - , - , - ; - clocks = <&coreclk 0>; - }; - - systemc: system-controller@18200 { - compatible = "marvell,armada-380-system-controller", - "marvell,armada-370-xp-system-controller"; - reg = <0x18200 0x100>; - }; - - gateclk: clock-gating-control@18220 { - compatible = "marvell,armada-380-gating-clock"; - reg = <0x18220 0x4>; - clocks = <&coreclk 0>; - #clock-cells = <1>; - }; - - comphy: phy@18300 { - compatible = "marvell,armada-380-comphy"; - reg = <0x18300 0x100>; - #address-cells = <1>; - #size-cells = <0>; - - comphy0: phy@0 { - reg = <0>; - #phy-cells = <1>; - }; - - comphy1: phy@1 { - reg = <1>; - #phy-cells = <1>; - }; - - comphy2: phy@2 { - reg = <2>; - #phy-cells = <1>; - }; - - comphy3: phy@3 { - reg = <3>; - #phy-cells = <1>; - }; - - comphy4: phy@4 { - reg = <4>; - #phy-cells = <1>; - }; - - comphy5: phy@5 { - reg = <5>; - #phy-cells = <1>; - }; - }; - - coreclk: mvebu-sar@18600 { - compatible = "marvell,armada-380-core-clock"; - reg = <0x18600 0x04>; - #clock-cells = <1>; - }; - - mbusc: mbus-controller@20000 { - compatible = "marvell,mbus-controller"; - reg = <0x20000 0x100>, <0x20180 0x20>, - <0x20250 0x8>; - }; - - mpic: interrupt-controller@20a00 { - compatible = "marvell,mpic"; - reg = <0x20a00 0x2d0>, <0x21070 0x58>; - #interrupt-cells = <1>; - #size-cells = <1>; - interrupt-controller; - msi-controller; - interrupts = ; - }; - - timer: timer@20300 { - compatible = "marvell,armada-380-timer", - "marvell,armada-xp-timer"; - reg = <0x20300 0x30>, <0x21040 0x30>; - interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, - <&mpic 5>, - <&mpic 6>; - clocks = <&coreclk 2>, <&refclk>; - clock-names = "nbclk", "fixed"; - }; - - watchdog: watchdog@20300 { - compatible = "marvell,armada-380-wdt"; - reg = <0x20300 0x34>, <0x20704 0x4>, <0x18260 0x4>; - clocks = <&coreclk 2>, <&refclk>; - clock-names = "nbclk", "fixed"; - interrupts-extended = <&gic GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; - }; - - cpurst: cpurst@20800 { - compatible = "marvell,armada-370-cpu-reset"; - reg = <0x20800 0x10>; - }; - - mpcore-soc-ctrl@20d20 { - compatible = "marvell,armada-380-mpcore-soc-ctrl"; - reg = <0x20d20 0x6c>; - }; - - coherencyfab: coherency-fabric@21010 { - compatible = "marvell,armada-380-coherency-fabric"; - reg = <0x21010 0x1c>; - }; - - pmsu: pmsu@22000 { - compatible = "marvell,armada-380-pmsu"; - reg = <0x22000 0x1000>; - }; - - /* - * As a special exception to the "order by - * register address" rule, the eth0 node is - * placed here to ensure that it gets - * registered as the first interface, since - * the network subsystem doesn't allow naming - * interfaces using DT aliases. Without this, - * the ordering of interfaces is different - * from the one used in U-Boot and the - * labeling of interfaces on the boards, which - * is very confusing for users. - */ - eth0: ethernet@70000 { - compatible = "marvell,armada-370-neta"; - reg = <0x70000 0x4000>; - interrupts-extended = <&mpic 8>; - clocks = <&gateclk 4>; - tx-csum-limit = <9800>; - status = "disabled"; - }; - - eth1: ethernet@30000 { - compatible = "marvell,armada-370-neta"; - reg = <0x30000 0x4000>; - interrupts-extended = <&mpic 10>; - clocks = <&gateclk 3>; - status = "disabled"; - }; - - eth2: ethernet@34000 { - compatible = "marvell,armada-370-neta"; - reg = <0x34000 0x4000>; - interrupts-extended = <&mpic 12>; - clocks = <&gateclk 2>; - status = "disabled"; - }; - - usb0: usb@58000 { - compatible = "marvell,orion-ehci"; - reg = <0x58000 0x500>; - interrupts = ; - clocks = <&gateclk 18>; - status = "disabled"; - }; - - xor0: xor@60800 { - compatible = "marvell,armada-380-xor", "marvell,orion-xor"; - reg = <0x60800 0x100 - 0x60a00 0x100>; - clocks = <&gateclk 22>; - status = "okay"; - - xor00 { - interrupts = ; - dmacap,memcpy; - dmacap,xor; - }; - xor01 { - interrupts = ; - dmacap,memcpy; - dmacap,xor; - dmacap,memset; - }; - }; - - xor1: xor@60900 { - compatible = "marvell,armada-380-xor", "marvell,orion-xor"; - reg = <0x60900 0x100 - 0x60b00 0x100>; - clocks = <&gateclk 28>; - status = "okay"; - - xor10 { - interrupts = ; - dmacap,memcpy; - dmacap,xor; - }; - xor11 { - interrupts = ; - dmacap,memcpy; - dmacap,xor; - dmacap,memset; - }; - }; - - mdio: mdio@72004 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "marvell,orion-mdio"; - reg = <0x72004 0x4>; - clocks = <&gateclk 4>; - }; - - cesa: crypto@90000 { - compatible = "marvell,armada-38x-crypto"; - reg = <0x90000 0x10000>; - reg-names = "regs"; - interrupts = , - ; - clocks = <&gateclk 23>, <&gateclk 21>, - <&gateclk 14>, <&gateclk 16>; - clock-names = "cesa0", "cesa1", - "cesaz0", "cesaz1"; - marvell,crypto-srams = <&crypto_sram0>, - <&crypto_sram1>; - marvell,crypto-sram-size = <0x800>; - }; - - rtc: rtc@a3800 { - compatible = "marvell,armada-380-rtc"; - reg = <0xa3800 0x20>, <0x184a0 0x0c>; - reg-names = "rtc", "rtc-soc"; - interrupts = ; - }; - - ahci0: sata@a8000 { - compatible = "marvell,armada-380-ahci"; - reg = <0xa8000 0x2000>; - interrupts = ; - clocks = <&gateclk 15>; - status = "disabled"; - }; - - bm: bm@c8000 { - compatible = "marvell,armada-380-neta-bm"; - reg = <0xc8000 0xac>; - clocks = <&gateclk 13>; - internal-mem = <&bm_bppi>; - status = "disabled"; - }; - - ahci1: sata@e0000 { - compatible = "marvell,armada-380-ahci"; - reg = <0xe0000 0x2000>; - interrupts = ; - clocks = <&gateclk 30>; - status = "disabled"; - }; - - coredivclk: clock@e4250 { - compatible = "marvell,armada-380-corediv-clock"; - reg = <0xe4250 0xc>; - #clock-cells = <1>; - clocks = <&mainpll>; - clock-output-names = "nand"; - }; - - thermal: thermal@e8078 { - compatible = "marvell,armada380-thermal"; - reg = <0xe4078 0x4>, <0xe4070 0x8>; - status = "okay"; - }; - - nand_controller: nand-controller@d0000 { - compatible = "marvell,armada370-nand-controller"; - reg = <0xd0000 0x54>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clocks = <&coredivclk 0>; - status = "disabled"; - }; - - sdhci: sdhci@d8000 { - compatible = "marvell,armada-380-sdhci"; - reg-names = "sdhci", "mbus", "conf-sdio3"; - reg = <0xd8000 0x1000>, - <0xdc000 0x100>, - <0x18454 0x4>; - interrupts = ; - clocks = <&gateclk 17>; - mrvl,clk-delay-cycles = <0x1F>; - status = "disabled"; - }; - - usb3_0: usb3@f0000 { - compatible = "marvell,armada-380-xhci"; - reg = <0xf0000 0x4000>,<0xf4000 0x4000>; - interrupts = ; - clocks = <&gateclk 9>; - status = "disabled"; - }; - - usb3_1: usb3@f8000 { - compatible = "marvell,armada-380-xhci"; - reg = <0xf8000 0x4000>,<0xfc000 0x4000>; - interrupts = ; - clocks = <&gateclk 10>; - status = "disabled"; - }; - }; - - crypto_sram0: sa-sram0 { - compatible = "mmio-sram"; - reg = ; - clocks = <&gateclk 23>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 MBUS_ID(0x09, 0x19) 0 0x800>; - }; - - crypto_sram1: sa-sram1 { - compatible = "mmio-sram"; - reg = ; - clocks = <&gateclk 21>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 MBUS_ID(0x09, 0x15) 0 0x800>; - }; - - bm_bppi: bm-bppi { - compatible = "mmio-sram"; - reg = ; - ranges = <0 MBUS_ID(0x0c, 0x04) 0 0x100000>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&gateclk 13>; - no-memory-wc; - status = "disabled"; - }; - - spi0: spi@10600 { - compatible = "marvell,armada-380-spi", - "marvell,orion-spi"; - reg = ; - #address-cells = <1>; - #size-cells = <0>; - cell-index = <0>; - interrupts = ; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - spi1: spi@10680 { - compatible = "marvell,armada-380-spi", - "marvell,orion-spi"; - reg = ; - #address-cells = <1>; - #size-cells = <0>; - cell-index = <1>; - interrupts = ; - clocks = <&coreclk 0>; - status = "disabled"; - }; - }; - - clocks { - /* 1 GHz fixed main PLL */ - mainpll: mainpll { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <1000000000>; - }; - - /* 25 MHz reference crystal */ - refclk: oscillator { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/armada-390-db.dts b/sys/gnu/dts/arm/armada-390-db.dts deleted file mode 100644 index 0e29474ae9a..00000000000 --- a/sys/gnu/dts/arm/armada-390-db.dts +++ /dev/null @@ -1,142 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for Marvell Armada 390 Development Board - * (DB-88F6920) - * - * Copyright (C) 2016 Marvell - * - * Grzegorz Jaszczyk - */ - -/dts-v1/; -#include "armada-390.dtsi" - -/ { - model = "Marvell Armada 390 Development Board"; - compatible = "marvell,a390-db", "marvell,armada390"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - device_type = "memory"; - reg = <0x00000000 0x80000000>; /* 2 GB */ - }; - - soc { - ranges = ; - - internal-regs { - i2c@11000 { - status = "okay"; - clock-frequency = <100000>; - - eeprom@50 { - compatible = "atmel,24c64"; - reg = <0x50>; - }; - }; - - /* CON104 */ - serial@12000 { - status = "okay"; - }; - - /* CON97 */ - usb@58000 { - status = "okay"; - }; - - /* CON98 */ - usb3@f8000 { - status = "okay"; - }; - }; - - pcie { - status = "okay"; - - /* CON30 */ - pcie@1,0 { - status = "okay"; - }; - - /* CON44 */ - pcie@2,0 { - status = "okay"; - }; - - /* CON61 */ - pcie@3,0 { - status = "okay"; - }; - }; - }; -}; - -&spi1 { - status = "okay"; - pinctrl-0 = <&spi1_pins>; - pinctrl-names = "default"; - - spi-flash@1 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "n25q128a13", - "jedec,spi-nor"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <108000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "U-Boot"; - reg = <0 0x400000>; - }; - partition@400000 { - label = "Filesystem"; - reg = <0x400000 0xc00000>; - }; - }; - }; -}; - -&nand_controller { - status = "okay"; - pinctrl-0 = <&nand_pins>; - pinctrl-names = "default"; - - nand@0 { - reg = <0>; - label = "pxa3xx_nand-0"; - nand-rb = <0>; - marvell,nand-keep-config; - nand-on-flash-bbt; - nand-ecc-strength = <8>; - nand-ecc-step-size = <512>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "U-Boot"; - reg = <0 0x800000>; - }; - partition@800000 { - label = "Linux"; - reg = <0x800000 0x800000>; - }; - partition@1000000 { - label = "Filesystem"; - reg = <0x1000000 0x3f000000>; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/armada-390.dtsi b/sys/gnu/dts/arm/armada-390.dtsi deleted file mode 100644 index aa2057d4d6f..00000000000 --- a/sys/gnu/dts/arm/armada-390.dtsi +++ /dev/null @@ -1,23 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree Include file for Marvell Armada 390 SoC. - * - * Copyright (C) 2015 Marvell - * - * Thomas Petazzoni - */ - -#include "armada-39x.dtsi" - -/ { - compatible = "marvell,armada390"; - - soc { - internal-regs { - pinctrl@18000 { - compatible = "marvell,mv88f6920-pinctrl"; - reg = <0x18000 0x20>; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/armada-395-gp.dts b/sys/gnu/dts/arm/armada-395-gp.dts deleted file mode 100644 index 6dd9e9077f8..00000000000 --- a/sys/gnu/dts/arm/armada-395-gp.dts +++ /dev/null @@ -1,136 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Device Tree file for Marvell Armada 395 GP board - * - * Copyright (C) 2016 Marvell - * - * Grzegorz Jaszczyk - */ - -/dts-v1/; -#include "armada-395.dtsi" - -/ { - model = "Marvell Armada 395 GP Board"; - compatible = "marvell,a395-gp", "marvell,armada395", - "marvell,armada390"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - device_type = "memory"; - reg = <0x00000000 0x40000000>; /* 1 GB */ - }; - - soc { - ranges = ; - - internal-regs { - i2c@11000 { - status = "okay"; - clock-frequency = <100000>; - - eeprom@57 { - compatible = "atmel,24c64"; - reg = <0x57>; - }; - }; - - serial@12000 { - /* - * Exported on the micro USB connector CON17 - * through an FTDI - */ - status = "okay"; - }; - - /* CON1 */ - usb@58000 { - status = "okay"; - }; - - /* CON2 */ - sata@a8000 { - status = "okay"; - }; - - /* CON18 */ - sdhci@d8000 { - clock-frequency = <200000000>; - broken-cd; - wp-inverted; - bus-width = <8>; - status = "okay"; - no-1-8-v; - }; - - /* CON4 */ - usb3@f0000 { - status = "okay"; - }; - }; - - pcie { - status = "okay"; - - /* - * The two PCIe units are accessible through - * mini PCIe slot on the board. - */ - - /* CON7 */ - pcie@2,0 { - /* Port 1, Lane 0 */ - status = "okay"; - }; - - /* CON8 */ - pcie@4,0 { - /* Port 3, Lane 0 */ - status = "okay"; - }; - }; - }; -}; - -&nand_controller { - status = "okay"; - pinctrl-0 = <&nand_pins>; - pinctrl-names = "default"; - - nand@0 { - reg = <0>; - label = "pxa3xx_nand-0"; - nand-rb = <0>; - marvell,nand-keep-config; - nand-on-flash-bbt; - nand-ecc-strength = <4>; - nand-ecc-step-size = <512>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "U-Boot"; - reg = <0x00000000 0x00600000>; - read-only; - }; - - partition@800000 { - label = "uImage"; - reg = <0x00600000 0x00400000>; - read-only; - }; - - partition@1000000 { - label = "Root"; - reg = <0x00a00000 0x3f600000>; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/armada-395.dtsi b/sys/gnu/dts/arm/armada-395.dtsi deleted file mode 100644 index e18a7d9cd7d..00000000000 --- a/sys/gnu/dts/arm/armada-395.dtsi +++ /dev/null @@ -1,39 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree Include file for Marvell Armada 395 SoC. - * - * Copyright (C) 2016 Marvell - * - * Grzegorz Jaszczyk - */ - -#include "armada-39x.dtsi" - -/ { - compatible = "marvell,armada395", "marvell,armada390"; - - soc { - internal-regs { - pinctrl@18000 { - compatible = "marvell,mv88f6925-pinctrl"; - reg = <0x18000 0x20>; - }; - - sata@a8000 { - compatible = "marvell,armada-380-ahci"; - reg = <0xa8000 0x2000>; - interrupts = ; - clocks = <&gateclk 15>; - status = "disabled"; - }; - - usb3@f0000 { - compatible = "marvell,armada-380-xhci"; - reg = <0xf0000 0x4000>,<0xf4000 0x4000>; - interrupts = ; - clocks = <&gateclk 9>; - status = "disabled"; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/armada-398-db.dts b/sys/gnu/dts/arm/armada-398-db.dts deleted file mode 100644 index fc28308e5bc..00000000000 --- a/sys/gnu/dts/arm/armada-398-db.dts +++ /dev/null @@ -1,134 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree Include file for Marvell Armada 398 Development Board - * - * Copyright (C) 2015 Marvell - * - * Thomas Petazzoni - */ - -/dts-v1/; -#include "armada-398.dtsi" - -/ { - model = "Marvell Armada 398 Development Board"; - compatible = "marvell,a398-db", "marvell,armada398", "marvell,armada390"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - device_type = "memory"; - reg = <0x00000000 0x80000000>; /* 2 GB */ - }; - - soc { - ranges = ; - - internal-regs { - i2c@11000 { - pinctrl-0 = <&i2c0_pins>; - pinctrl-names = "default"; - status = "okay"; - clock-frequency = <100000>; - }; - - serial@12000 { - pinctrl-0 = <&uart0_pins>; - pinctrl-names = "default"; - status = "okay"; - }; - - serial@12100 { - pinctrl-0 = <&uart1_pins>; - pinctrl-names = "default"; - status = "okay"; - }; - - usb@58000 { - status = "okay"; - }; - - usb3@f8000 { - status = "okay"; - }; - }; - - pcie { - status = "okay"; - - pcie@1,0 { - status = "okay"; - }; - - pcie@2,0 { - status = "okay"; - }; - - pcie@3,0 { - status = "okay"; - }; - }; - }; -}; - -&spi1 { - status = "okay"; - pinctrl-0 = <&spi1_pins>; - pinctrl-names = "default"; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "n25q128a13", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <108000000>; - - partition@0 { - label = "U-Boot"; - reg = <0 0x400000>; - }; - - partition@400000 { - label = "Filesystem"; - reg = <0x400000 0x1000000>; - }; - }; -}; - -&nand_controller { - status = "okay"; - pinctrl-0 = <&nand_pins>; - pinctrl-names = "default"; - - nand@0 { - reg = <0>; - label = "pxa3xx_nand-0"; - nand-rb = <0>; - marvell,nand-keep-config; - nand-on-flash-bbt; - nand-ecc-strength = <8>; - nand-ecc-step-size = <512>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "U-Boot"; - reg = <0 0x800000>; - }; - partition@800000 { - label = "Linux"; - reg = <0x800000 0x800000>; - }; - partition@1000000 { - label = "Filesystem"; - reg = <0x1000000 0x3f000000>; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/armada-398.dtsi b/sys/gnu/dts/arm/armada-398.dtsi deleted file mode 100644 index c5ac89399ce..00000000000 --- a/sys/gnu/dts/arm/armada-398.dtsi +++ /dev/null @@ -1,31 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree Include file for Marvell Armada 398 SoC. - * - * Copyright (C) 2015 Marvell - * - * Thomas Petazzoni - */ - -#include "armada-395.dtsi" - -/ { - compatible = "marvell,armada398", "marvell,armada390"; - - soc { - internal-regs { - pinctrl@18000 { - compatible = "marvell,mv88f6928-pinctrl"; - reg = <0x18000 0x20>; - }; - - sata@e0000 { - compatible = "marvell,armada-380-ahci"; - reg = <0xe0000 0x2000>; - interrupts = ; - clocks = <&gateclk 30>; - status = "disabled"; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/armada-39x.dtsi b/sys/gnu/dts/arm/armada-39x.dtsi deleted file mode 100644 index b1b86934c68..00000000000 --- a/sys/gnu/dts/arm/armada-39x.dtsi +++ /dev/null @@ -1,558 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree Include file for Marvell Armada 39x family of SoCs. - * - * Copyright (C) 2015 Marvell - * - * Thomas Petazzoni - */ - -#include -#include - -#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) - -/ { - #address-cells = <1>; - #size-cells = <1>; - model = "Marvell Armada 39x family SoC"; - compatible = "marvell,armada390"; - - aliases { - gpio0 = &gpio0; - gpio1 = &gpio1; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "marvell,armada-390-smp"; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - }; - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <1>; - }; - }; - - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts-extended = <&mpic 3>; - }; - - soc { - compatible = "marvell,armada390-mbus", "marvell,armadaxp-mbus", - "simple-bus"; - #address-cells = <2>; - #size-cells = <1>; - controller = <&mbusc>; - interrupt-parent = <&gic>; - pcie-mem-aperture = <0xe0000000 0x8000000>; - pcie-io-aperture = <0xe8000000 0x100000>; - - bootrom { - compatible = "marvell,bootrom"; - reg = ; - }; - - internal-regs { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>; - - L2: cache-controller@8000 { - compatible = "arm,pl310-cache"; - reg = <0x8000 0x1000>; - cache-unified; - cache-level = <2>; - arm,double-linefill-incr = <0>; - arm,double-linefill-wrap = <0>; - arm,double-linefill = <0>; - prefetch-data = <1>; - }; - - scu@c000 { - compatible = "arm,cortex-a9-scu"; - reg = <0xc000 0x100>; - }; - - timer@c600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0xc600 0x20>; - interrupts = ; - clocks = <&coreclk 2>; - }; - - gic: interrupt-controller@d000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #size-cells = <0>; - interrupt-controller; - reg = <0xd000 0x1000>, - <0xc100 0x100>; - }; - - i2c0: i2c@11000 { - compatible = "marvell,mv64xxx-i2c"; - reg = <0x11000 0x20>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - timeout-ms = <1000>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - i2c1: i2c@11100 { - compatible = "marvell,mv64xxx-i2c"; - reg = <0x11100 0x20>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - timeout-ms = <1000>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - i2c2: i2c@11200 { - compatible = "marvell,mv64xxx-i2c"; - reg = <0x11200 0x20>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - timeout-ms = <1000>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - i2c3: i2c@11300 { - compatible = "marvell,mv64xxx-i2c"; - reg = <0x11300 0x20>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - timeout-ms = <1000>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - uart0: serial@12000 { - compatible = "snps,dw-apb-uart"; - reg = <0x12000 0x100>; - reg-shift = <2>; - interrupts = ; - reg-io-width = <1>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - uart1: serial@12100 { - compatible = "snps,dw-apb-uart"; - reg = <0x12100 0x100>; - reg-shift = <2>; - interrupts = ; - reg-io-width = <1>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - uart2: serial@12200 { - compatible = "snps,dw-apb-uart"; - reg = <0x12200 0x100>; - reg-shift = <2>; - interrupts = ; - reg-io-width = <1>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - uart3: serial@12300 { - compatible = "snps,dw-apb-uart"; - reg = <0x12300 0x100>; - reg-shift = <2>; - interrupts = ; - reg-io-width = <1>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - pinctrl@18000 { - i2c0_pins: i2c0-pins { - marvell,pins = "mpp2", "mpp3"; - marvell,function = "i2c0"; - }; - - uart0_pins: uart0-pins { - marvell,pins = "mpp0", "mpp1"; - marvell,function = "ua0"; - }; - - uart1_pins: uart1-pins { - marvell,pins = "mpp19", "mpp20"; - marvell,function = "ua1"; - }; - - spi1_pins: spi1-pins { - marvell,pins = "mpp56", "mpp57", "mpp58", "mpp59"; - marvell,function = "spi1"; - }; - - nand_pins: nand-pins { - marvell,pins = "mpp22", "mpp34", "mpp23", "mpp33", - "mpp38", "mpp28", "mpp40", "mpp42", - "mpp35", "mpp36", "mpp25", "mpp30", - "mpp32"; - marvell,function = "dev"; - }; - }; - - gpio0: gpio@18100 { - compatible = "marvell,orion-gpio"; - reg = <0x18100 0x40>; - ngpios = <32>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = , - , - , - ; - }; - - gpio1: gpio@18140 { - compatible = "marvell,orion-gpio"; - reg = <0x18140 0x40>; - ngpios = <28>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = , - , - , - ; - }; - - system-controller@18200 { - compatible = "marvell,armada-390-system-controller", - "marvell,armada-370-xp-system-controller"; - reg = <0x18200 0x100>; - }; - - gateclk: clock-gating-control@18220 { - compatible = "marvell,armada-390-gating-clock"; - reg = <0x18220 0x4>; - clocks = <&coreclk 0>; - #clock-cells = <1>; - }; - - coreclk: mvebu-sar@18600 { - compatible = "marvell,armada-390-core-clock"; - reg = <0x18600 0x04>; - #clock-cells = <1>; - }; - - mbusc: mbus-controller@20000 { - compatible = "marvell,mbus-controller"; - reg = <0x20000 0x100>, <0x20180 0x20>, <0x20250 0x8>; - }; - - mpic: interrupt-controller@20a00 { - compatible = "marvell,mpic"; - reg = <0x20a00 0x2d0>, <0x21070 0x58>; - #interrupt-cells = <1>; - #size-cells = <1>; - interrupt-controller; - msi-controller; - interrupts = ; - }; - - timer@20300 { - compatible = "marvell,armada-380-timer", - "marvell,armada-xp-timer"; - reg = <0x20300 0x30>, <0x21040 0x30>; - interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, - <&mpic 5>, - <&mpic 6>; - clocks = <&coreclk 2>, <&coreclk 5>; - clock-names = "nbclk", "fixed"; - }; - - watchdog@20300 { - compatible = "marvell,armada-380-wdt"; - reg = <0x20300 0x34>, <0x20704 0x4>, - <0x18260 0x4>; - clocks = <&coreclk 2>, <&refclk>; - clock-names = "nbclk", "fixed"; - }; - - cpurst@20800 { - compatible = "marvell,armada-370-cpu-reset"; - reg = <0x20800 0x10>; - }; - - mpcore-soc-ctrl@20d20 { - compatible = "marvell,armada-380-mpcore-soc-ctrl"; - reg = <0x20d20 0x6c>; - }; - - coherency-fabric@21010 { - compatible = "marvell,armada-380-coherency-fabric"; - reg = <0x21010 0x1c>; - }; - - pmsu@22000 { - compatible = "marvell,armada-390-pmsu", - "marvell,armada-380-pmsu"; - reg = <0x22000 0x1000>; - }; - - xor@60800 { - compatible = "marvell,armada-380-xor", "marvell,orion-xor"; - reg = <0x60800 0x100 - 0x60a00 0x100>; - clocks = <&gateclk 22>; - status = "okay"; - - xor00 { - interrupts = ; - dmacap,memcpy; - dmacap,xor; - }; - xor01 { - interrupts = ; - dmacap,memcpy; - dmacap,xor; - dmacap,memset; - }; - }; - - xor@60900 { - compatible = "marvell,armada-380-xor", "marvell,orion-xor"; - reg = <0x60900 0x100 - 0x60b00 0x100>; - clocks = <&gateclk 28>; - status = "okay"; - - xor10 { - interrupts = ; - dmacap,memcpy; - dmacap,xor; - }; - xor11 { - interrupts = ; - dmacap,memcpy; - dmacap,xor; - dmacap,memset; - }; - }; - - rtc@a3800 { - compatible = "marvell,armada-380-rtc"; - reg = <0xa3800 0x20>, <0x184a0 0x0c>; - reg-names = "rtc", "rtc-soc"; - interrupts = ; - }; - - nand_controller: nand-controller@d0000 { - compatible = "marvell,armada370-nand-controller"; - reg = <0xd0000 0x54>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clocks = <&coredivclk 0>; - status = "disabled"; - }; - - sdhci@d8000 { - compatible = "marvell,armada-380-sdhci"; - reg-names = "sdhci", "mbus", "conf-sdio3"; - reg = <0xd8000 0x1000>, - <0xdc000 0x100>, - <0x18454 0x4>; - interrupts = ; - clocks = <&gateclk 17>; - mrvl,clk-delay-cycles = <0x1F>; - status = "disabled"; - }; - - coredivclk: clock@e4250 { - compatible = "marvell,armada-390-corediv-clock", - "marvell,armada-380-corediv-clock"; - reg = <0xe4250 0xc>; - #clock-cells = <1>; - clocks = <&mainpll>; - clock-output-names = "nand"; - }; - - thermal@e8078 { - compatible = "marvell,armada380-thermal"; - reg = <0xe4078 0x4>, <0xe4074 0x4>; - status = "okay"; - }; - }; - - pcie { - compatible = "marvell,armada-370-pcie"; - status = "disabled"; - device_type = "pci"; - - #address-cells = <3>; - #size-cells = <2>; - - msi-parent = <&mpic>; - bus-range = <0x00 0xff>; - - ranges = - <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 - 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 - 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 - 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 - 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */ - 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */ - 0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */ - 0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */ - 0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */ - 0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */ - 0x82000000 0x4 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 3 MEM */ - 0x81000000 0x4 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 3 IO */>; - - /* - * This port can be either x4 or x1. When - * configured in x4 by the bootloader, then - * pcie@4,0 is not available. - */ - pcie@1,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x80000 0 0x2000>; - reg = <0x0800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 - 0x81000000 0 0 0x81000000 0x1 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 8>; - status = "disabled"; - }; - - /* x1 port */ - pcie@2,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; - reg = <0x1000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 - 0x81000000 0 0 0x81000000 0x2 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; - marvell,pcie-port = <1>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 5>; - status = "disabled"; - }; - - /* x1 port */ - pcie@3,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; - reg = <0x1800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 - 0x81000000 0 0 0x81000000 0x3 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; - marvell,pcie-port = <2>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 6>; - status = "disabled"; - }; - - /* - * x1 port only available when pcie@1,0 is - * configured as a x1 port - */ - pcie@4,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x48000 0 0x2000>; - reg = <0x2000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 - 0x81000000 0 0 0x81000000 0x4 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; - marvell,pcie-port = <3>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 7>; - status = "disabled"; - }; - }; - - spi0: spi@10600 { - compatible = "marvell,armada-390-spi", - "marvell,orion-spi"; - reg = ; - #address-cells = <1>; - #size-cells = <0>; - cell-index = <0>; - interrupts = ; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - spi1: spi@10680 { - compatible = "marvell,armada-390-spi", - "marvell,orion-spi"; - reg = ; - #address-cells = <1>; - #size-cells = <0>; - cell-index = <1>; - interrupts = ; - clocks = <&coreclk 0>; - status = "disabled"; - }; - }; - - clocks { - /* 1 GHz fixed main PLL */ - mainpll: mainpll { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <1000000000>; - }; - - /* 25 MHz reference crystal */ - refclk: oscillator { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/armada-xp-98dx3236.dtsi b/sys/gnu/dts/arm/armada-xp-98dx3236.dtsi deleted file mode 100644 index 654648b05c7..00000000000 --- a/sys/gnu/dts/arm/armada-xp-98dx3236.dtsi +++ /dev/null @@ -1,346 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree Include file for Marvell 98dx3236 family SoC - * - * Copyright (C) 2016 Allied Telesis Labs - * - * Contains definitions specific to the 98dx3236 SoC that are not - * common to all Armada XP SoCs. - */ - -#include "armada-370-xp.dtsi" - -/ { - #address-cells = <2>; - #size-cells = <2>; - - model = "Marvell 98DX3236 SoC"; - compatible = "marvell,armadaxp-98dx3236", "marvell,armada-370-xp"; - - aliases { - gpio0 = &gpio0; - gpio1 = &gpio1; - gpio2 = &gpio2; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "marvell,98dx3236-smp"; - - cpu@0 { - device_type = "cpu"; - compatible = "marvell,sheeva-v7"; - reg = <0>; - clocks = <&cpuclk 0>; - clock-latency = <1000000>; - }; - }; - - soc { - compatible = "marvell,armadaxp-mbus", "simple-bus"; - - ranges = ; - - bootrom { - compatible = "marvell,bootrom"; - reg = ; - }; - - /* - * 98DX3236 has 1 x1 PCIe unit Gen2.0 - */ - pciec: pcie@82000000 { - compatible = "marvell,armada-xp-pcie"; - status = "disabled"; - device_type = "pci"; - - #address-cells = <3>; - #size-cells = <2>; - - msi-parent = <&mpic>; - bus-range = <0x00 0xff>; - - ranges = - <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */ - 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ - 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>; - - pcie1: pcie@1,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; - reg = <0x0800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 - 0x81000000 0 0 0x81000000 0x1 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 58>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 5>; - status = "disabled"; - }; - }; - - internal-regs { - sdramc: sdramc@1400 { - compatible = "marvell,armada-xp-sdram-controller"; - reg = <0x1400 0x500>; - }; - - L2: l2-cache@8000 { - compatible = "marvell,aurora-system-cache"; - reg = <0x08000 0x1000>; - cache-id-part = <0x100>; - cache-level = <2>; - cache-unified; - wt-override; - }; - - gpio0: gpio@18100 { - compatible = "marvell,orion-gpio"; - reg = <0x18100 0x40>; - ngpios = <32>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <82>, <83>, <84>, <85>; - }; - - /* does not exist */ - gpio1: gpio@18140 { - compatible = "marvell,orion-gpio"; - reg = <0x18140 0x40>; - status = "disabled"; - }; - - gpio2: gpio@18180 { /* rework some properties */ - compatible = "marvell,orion-gpio"; - reg = <0x18180 0x40>; - ngpios = <1>; /* only gpio #32 */ - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <87>; - }; - - systemc: system-controller@18200 { - compatible = "marvell,armada-370-xp-system-controller"; - reg = <0x18200 0x500>; - }; - - gateclk: clock-gating-control@18220 { - compatible = "marvell,mv98dx3236-gating-clock"; - reg = <0x18220 0x4>; - clocks = <&coreclk 0>; - #clock-cells = <1>; - }; - - cpuclk: clock-complex@18700 { - #clock-cells = <1>; - compatible = "marvell,mv98dx3236-cpu-clock"; - reg = <0x18700 0x24>, <0x1c054 0x10>; - clocks = <&coreclk 1>; - }; - - corediv-clock@18740 { - status = "disabled"; - }; - - cpu-config@21000 { - compatible = "marvell,armada-xp-cpu-config"; - reg = <0x21000 0x8>; - }; - - ethernet@70000 { - compatible = "marvell,armada-xp-neta"; - }; - - ethernet@74000 { - compatible = "marvell,armada-xp-neta"; - }; - - xor1: xor@f0800 { - compatible = "marvell,orion-xor"; - reg = <0xf0800 0x100 - 0xf0a00 0x100>; - clocks = <&gateclk 22>; - status = "okay"; - - xor10 { - interrupts = <51>; - dmacap,memcpy; - dmacap,xor; - }; - xor11 { - interrupts = <52>; - dmacap,memcpy; - dmacap,xor; - dmacap,memset; - }; - }; - - nand_controller: nand-controller@d0000 { - clocks = <&dfx_coredivclk 0>; - }; - - xor0: xor@f0900 { - compatible = "marvell,orion-xor"; - reg = <0xF0900 0x100 - 0xF0B00 0x100>; - clocks = <&gateclk 28>; - status = "okay"; - - xor00 { - interrupts = <94>; - dmacap,memcpy; - dmacap,xor; - }; - xor01 { - interrupts = <95>; - dmacap,memcpy; - dmacap,xor; - dmacap,memset; - }; - }; - }; - - dfx: dfx-server@ac000000 { - compatible = "marvell,dfx-server", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 MBUS_ID(0x08, 0x00) 0 0x100000>; - reg = ; - - coreclk: mvebu-sar@f8204 { - compatible = "marvell,mv98dx3236-core-clock"; - reg = <0xf8204 0x4>; - #clock-cells = <1>; - }; - - dfx_coredivclk: corediv-clock@f8268 { - compatible = "marvell,mv98dx3236-corediv-clock"; - reg = <0xf8268 0xc>; - #clock-cells = <1>; - clocks = <&mainpll>; - clock-output-names = "nand"; - }; - }; - - switch: switch@a8000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 MBUS_ID(0x03, 0x00) 0 0x100000>; - - pp0: packet-processor@0 { - compatible = "marvell,prestera-98dx3236", "marvell,prestera"; - reg = <0 0x4000000>; - interrupts = <33>, <34>, <35>; - dfx = <&dfx>; - }; - }; - }; - - clocks { - /* 25 MHz reference crystal */ - refclk: oscillator { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - }; -}; - -&i2c0 { - compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c"; - reg = <0x11000 0x100>; -}; - -&i2c1 { - compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c"; - reg = <0x11100 0x100>; -}; - -&mpic { - reg = <0x20a00 0x2d0>, <0x21070 0x58>; -}; - -&rtc { - status = "disabled"; -}; - -&timer { - compatible = "marvell,armada-xp-timer"; - clocks = <&coreclk 2>, <&refclk>; - clock-names = "nbclk", "fixed"; -}; - -&watchdog { - compatible = "marvell,armada-xp-wdt"; - clocks = <&coreclk 2>, <&refclk>; - clock-names = "nbclk", "fixed"; -}; - -&cpurst { - reg = <0x20800 0x20>; -}; - -&usb0 { - clocks = <&gateclk 18>; -}; - -&usb1 { - clocks = <&gateclk 19>; -}; - -&pinctrl { - compatible = "marvell,98dx3236-pinctrl"; - - nand_pins: nand-pins { - marvell,pins = "mpp20", "mpp21", "mpp22", - "mpp23", "mpp24", "mpp25", - "mpp26", "mpp27", "mpp28", - "mpp29", "mpp30"; - marvell,function = "dev"; - }; - - nand_rb: nand-rb { - marvell,pins = "mpp19"; - marvell,function = "nand"; - }; - - spi0_pins: spi0-pins { - marvell,pins = "mpp0", "mpp1", - "mpp2", "mpp3"; - marvell,function = "spi0"; - }; -}; - -&spi0 { - compatible = "marvell,armada-xp-spi", "marvell,orion-spi"; - pinctrl-0 = <&spi0_pins>; - pinctrl-names = "default"; -}; - -&sdio { - status = "disabled"; -}; - -&uart0 { - compatible = "marvell,armada-38x-uart"; -}; - -&uart1 { - compatible = "marvell,armada-38x-uart"; -}; - diff --git a/sys/gnu/dts/arm/armada-xp-98dx3336.dtsi b/sys/gnu/dts/arm/armada-xp-98dx3336.dtsi deleted file mode 100644 index 1d9d8a8ea60..00000000000 --- a/sys/gnu/dts/arm/armada-xp-98dx3336.dtsi +++ /dev/null @@ -1,39 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree Include file for Marvell 98dx3336 family SoC - * - * Copyright (C) 2016 Allied Telesis Labs - * - * Contains definitions specific to the 98dx3236 SoC that are not - * common to all Armada XP SoCs. - */ - -#include "armada-xp-98dx3236.dtsi" - -/ { - model = "Marvell 98DX3336 SoC"; - compatible = "marvell,armadaxp-98dx3336", "marvell,armadaxp-98dx3236", "marvell,armada-370-xp"; - - cpus { - cpu@1 { - device_type = "cpu"; - compatible = "marvell,sheeva-v7"; - reg = <1>; - clocks = <&cpuclk 1>; - clock-latency = <1000000>; - }; - }; - - soc { - internal-regs { - resume@20980 { - compatible = "marvell,98dx3336-resume-ctrl"; - reg = <0x20980 0x10>; - }; - }; - }; -}; - -&pp0 { - compatible = "marvell,prestera-98dx3336", "marvell,prestera"; -}; diff --git a/sys/gnu/dts/arm/armada-xp-98dx4251.dtsi b/sys/gnu/dts/arm/armada-xp-98dx4251.dtsi deleted file mode 100644 index 48ffdc72bfc..00000000000 --- a/sys/gnu/dts/arm/armada-xp-98dx4251.dtsi +++ /dev/null @@ -1,54 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree Include file for Marvell 98dx4521 family SoC - * - * Copyright (C) 2016 Allied Telesis Labs - * - * Contains definitions specific to the 98dx4521 SoC that are not - * common to all Armada XP SoCs. - */ - -#include "armada-xp-98dx3236.dtsi" - -/ { - model = "Marvell 98DX4251 SoC"; - compatible = "marvell,armadaxp-98dx4251", "marvell,armadaxp-98dx3236", "marvell,armada-370-xp"; - - cpus { - cpu@1 { - device_type = "cpu"; - compatible = "marvell,sheeva-v7"; - reg = <1>; - clocks = <&cpuclk 1>; - clock-latency = <1000000>; - }; - }; - - soc { - internal-regs { - resume@20980 { - compatible = "marvell,98dx3336-resume-ctrl"; - reg = <0x20980 0x10>; - }; - }; - }; -}; - -&sdio { - status = "okay"; -}; - -&pinctrl { - compatible = "marvell,98dx4251-pinctrl"; - - sdio_pins: sdio-pins { - marvell,pins = "mpp5", "mpp6", "mpp7", - "mpp8", "mpp9", "mpp10"; - marvell,function = "sd0"; - }; -}; - -&pp0 { - compatible = "marvell,prestera-98dx4251", "marvell,prestera"; - interrupts = <33>, <34>, <35>, <36>; -}; diff --git a/sys/gnu/dts/arm/armada-xp-axpwifiap.dts b/sys/gnu/dts/arm/armada-xp-axpwifiap.dts deleted file mode 100644 index 606fd3476a5..00000000000 --- a/sys/gnu/dts/arm/armada-xp-axpwifiap.dts +++ /dev/null @@ -1,144 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for Marvell RD-AXPWiFiAP. - * - * Note: this board is shipped with a new generation boot loader that - * remaps internal registers at 0xf1000000. Therefore, if earlyprintk - * is used, the CONFIG_DEBUG_MVEBU_UART0_ALTERNATE option or the - * CONFIG_DEBUG_MVEBU_UART1_ALTERNATE option should be used. - * - * Copyright (C) 2013 Marvell - * - * Thomas Petazzoni - */ - -/dts-v1/; -#include -#include -#include "armada-xp-mv78230.dtsi" - -/ { - model = "Marvell RD-AXPWiFiAP"; - compatible = "marvell,rd-axpwifiap", "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x00000000 0x00000000 0x40000000>; /* 1GB */ - }; - - soc { - ranges = ; - - internal-regs { - /* UART0 */ - serial@12000 { - status = "okay"; - }; - - /* UART1 */ - serial@12100 { - status = "okay"; - }; - - sata@a0000 { - nr-ports = <1>; - status = "okay"; - }; - - ethernet@70000 { - pinctrl-0 = <&ge0_rgmii_pins>; - pinctrl-names = "default"; - status = "okay"; - phy = <&phy0>; - phy-mode = "rgmii-id"; - }; - ethernet@74000 { - pinctrl-0 = <&ge1_rgmii_pins>; - pinctrl-names = "default"; - status = "okay"; - phy = <&phy1>; - phy-mode = "rgmii-id"; - }; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&keys_pin>; - pinctrl-names = "default"; - - reset { - label = "Factory Reset Button"; - linux,code = ; - gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&mdio { - phy0: ethernet-phy@0 { - reg = <0>; - }; - - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&pciec { - status = "okay"; - - /* First mini-PCIe port */ - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - - /* Second mini-PCIe port */ - pcie@2,0 { - /* Port 0, Lane 1 */ - status = "okay"; - }; - - /* Renesas uPD720202 USB 3.0 controller */ - pcie@3,0 { - /* Port 0, Lane 3 */ - status = "okay"; - }; -}; - -&pinctrl { - pinctrl-0 = <&phy_int_pin>; - pinctrl-names = "default"; - - keys_pin: keys-pin { - marvell,pins = "mpp33"; - marvell,function = "gpio"; - }; - - phy_int_pin: phy-int-pin { - marvell,pins = "mpp32"; - marvell,function = "gpio"; - }; -}; - -&spi0 { - status = "okay"; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "n25q128a13", "jedec,spi-nor"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <108000000>; - }; -}; diff --git a/sys/gnu/dts/arm/armada-xp-db-dxbc2.dts b/sys/gnu/dts/arm/armada-xp-db-dxbc2.dts deleted file mode 100644 index 8a3aa616bbd..00000000000 --- a/sys/gnu/dts/arm/armada-xp-db-dxbc2.dts +++ /dev/null @@ -1,118 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for DB-DXBC2 board - * - * Copyright (C) 2016 Allied Telesis Labs - * - * Based on armada-xp-db.dts - * - * Note: this Device Tree assumes that the bootloader has remapped the - * internal registers to 0xf1000000 (instead of the default - * 0xd0000000). The 0xf1000000 is the default used by the recent, - * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier - * boards were delivered with an older version of the bootloader that - * left internal registers mapped at 0xd0000000. If you are in this - * situation, you should either update your bootloader (preferred - * solution) or the below Device Tree should be adjusted. - */ - -/dts-v1/; -#include "armada-xp-98dx4251.dtsi" - -/ { - model = "Marvell Bobcat2 Evaluation Board"; - compatible = "marvell,db-dxbc2", "marvell,armadaxp-98dx4251", "marvell,armada-370-xp"; - - chosen { - bootargs = "console=ttyS0,115200 earlyprintk"; - }; - - memory { - device_type = "memory"; - reg = <0 0x00000000 0 0x20000000>; /* 512 MB */ - }; - -}; - -&devbus_bootcs { - status = "okay"; - - /* Device Bus parameters are required */ - - /* Read parameters */ - devbus,bus-width = <16>; - devbus,turn-off-ps = <60000>; - devbus,badr-skew-ps = <0>; - devbus,acc-first-ps = <124000>; - devbus,acc-next-ps = <248000>; - devbus,rd-setup-ps = <0>; - devbus,rd-hold-ps = <0>; - - /* Write parameters */ - devbus,sync-enable = <0>; - devbus,wr-high-ps = <60000>; - devbus,wr-low-ps = <60000>; - devbus,ale-wr-ps = <60000>; -}; - -&i2c0 { - clock-frequency = <100000>; - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&nand_controller { - status = "okay"; - - nand@0 { - reg = <0>; - label = "pxa3xx_nand-0"; - nand-rb = <0>; - marvell,nand-keep-config; - nand-on-flash-bbt; - nand-ecc-strength = <4>; - nand-ecc-step-size = <512>; - }; -}; - -&sdio { - pinctrl-0 = <&sdio_pins>; - pinctrl-names = "default"; - status = "okay"; - /* No CD or WP GPIOs */ - broken-cd; -}; - -&spi0 { - status = "okay"; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "m25p64"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <20000000>; - m25p,fast-read; - - partition@u-boot { - reg = <0x00000000 0x00100000>; - label = "u-boot"; - }; - partition@u-boot-env { - reg = <0x00100000 0x00040000>; - label = "u-boot-env"; - }; - partition@unused { - reg = <0x00140000 0x00ec0000>; - label = "unused"; - }; - - }; -}; diff --git a/sys/gnu/dts/arm/armada-xp-db-xc3-24g4xg.dts b/sys/gnu/dts/arm/armada-xp-db-xc3-24g4xg.dts deleted file mode 100644 index 4ec0ae01b61..00000000000 --- a/sys/gnu/dts/arm/armada-xp-db-xc3-24g4xg.dts +++ /dev/null @@ -1,114 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for DB-XC3-24G4XG board - * - * Copyright (C) 2016 Allied Telesis Labs - * - * Based on armada-xp-db.dts - * - * Note: this Device Tree assumes that the bootloader has remapped the - * internal registers to 0xf1000000 (instead of the default - * 0xd0000000). The 0xf1000000 is the default used by the recent, - * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier - * boards were delivered with an older version of the bootloader that - * left internal registers mapped at 0xd0000000. If you are in this - * situation, you should either update your bootloader (preferred - * solution) or the below Device Tree should be adjusted. - */ - -/dts-v1/; -#include "armada-xp-98dx3336.dtsi" - -/ { - model = "DB-XC3-24G4XG"; - compatible = "marvell,db-xc3-24g4xg", "marvell,armadaxp-98dx3336", "marvell,armada-370-xp"; - - chosen { - bootargs = "console=ttyS0,115200 earlyprintk"; - }; - - memory { - device_type = "memory"; - reg = <0 0x00000000 0 0x40000000>; /* 1 GB */ - }; -}; - -&L2 { - arm,parity-enable; - marvell,ecc-enable; -}; - -&devbus_bootcs { - status = "okay"; - - /* Device Bus parameters are required */ - - /* Read parameters */ - devbus,bus-width = <16>; - devbus,turn-off-ps = <60000>; - devbus,badr-skew-ps = <0>; - devbus,acc-first-ps = <124000>; - devbus,acc-next-ps = <248000>; - devbus,rd-setup-ps = <0>; - devbus,rd-hold-ps = <0>; - - /* Write parameters */ - devbus,sync-enable = <0>; - devbus,wr-high-ps = <60000>; - devbus,wr-low-ps = <60000>; - devbus,ale-wr-ps = <60000>; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&i2c0 { - clock-frequency = <100000>; - status = "okay"; -}; - -&nand_controller { - status = "okay"; - - nand@0 { - reg = <0>; - label = "pxa3xx_nand-0"; - nand-rb = <0>; - marvell,nand-keep-config; - nand-on-flash-bbt; - nand-ecc-strength = <4>; - nand-ecc-step-size = <512>; - }; -}; - -&spi0 { - status = "okay"; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "m25p64"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <20000000>; - m25p,fast-read; - - partition@u-boot { - reg = <0x00000000 0x00100000>; - label = "u-boot"; - }; - partition@u-boot-env { - reg = <0x00100000 0x00040000>; - label = "u-boot-env"; - }; - partition@unused { - reg = <0x00140000 0x00ec0000>; - label = "unused"; - }; - - }; -}; diff --git a/sys/gnu/dts/arm/armada-xp-db.dts b/sys/gnu/dts/arm/armada-xp-db.dts deleted file mode 100644 index 5d04dc68cf5..00000000000 --- a/sys/gnu/dts/arm/armada-xp-db.dts +++ /dev/null @@ -1,245 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for Marvell Armada XP evaluation board - * (DB-78460-BP) - * - * Copyright (C) 2012-2014 Marvell - * - * Lior Amsalem - * Gregory CLEMENT - * Thomas Petazzoni - * - * - * Note: this Device Tree assumes that the bootloader has remapped the - * internal registers to 0xf1000000 (instead of the default - * 0xd0000000). The 0xf1000000 is the default used by the recent, - * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier - * boards were delivered with an older version of the bootloader that - * left internal registers mapped at 0xd0000000. If you are in this - * situation, you should either update your bootloader (preferred - * solution) or the below Device Tree should be adjusted. - */ - -/dts-v1/; -#include "armada-xp-mv78460.dtsi" - -/ { - model = "Marvell Armada XP Evaluation Board"; - compatible = "marvell,axp-db", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0 0x00000000 0 0x80000000>; /* 2 GB */ - }; - - soc { - ranges = ; - - devbus-bootcs { - status = "okay"; - - /* Device Bus parameters are required */ - - /* Read parameters */ - devbus,bus-width = <16>; - devbus,turn-off-ps = <60000>; - devbus,badr-skew-ps = <0>; - devbus,acc-first-ps = <124000>; - devbus,acc-next-ps = <248000>; - devbus,rd-setup-ps = <0>; - devbus,rd-hold-ps = <0>; - - /* Write parameters */ - devbus,sync-enable = <0>; - devbus,wr-high-ps = <60000>; - devbus,wr-low-ps = <60000>; - devbus,ale-wr-ps = <60000>; - - /* NOR 16 MiB */ - nor@0 { - compatible = "cfi-flash"; - reg = <0 0x1000000>; - bank-width = <2>; - }; - }; - - internal-regs { - serial@12000 { - status = "okay"; - }; - serial@12100 { - status = "okay"; - }; - serial@12200 { - status = "okay"; - }; - serial@12300 { - status = "okay"; - }; - - sata@a0000 { - nr-ports = <2>; - status = "okay"; - }; - - ethernet@70000 { - status = "okay"; - phy = <&phy0>; - phy-mode = "rgmii-id"; - buffer-manager = <&bm>; - bm,pool-long = <0>; - }; - ethernet@74000 { - status = "okay"; - phy = <&phy1>; - phy-mode = "rgmii-id"; - buffer-manager = <&bm>; - bm,pool-long = <1>; - }; - ethernet@30000 { - status = "okay"; - phy = <&phy2>; - phy-mode = "sgmii"; - buffer-manager = <&bm>; - bm,pool-long = <2>; - }; - ethernet@34000 { - status = "okay"; - phy = <&phy3>; - phy-mode = "sgmii"; - buffer-manager = <&bm>; - bm,pool-long = <3>; - }; - - bm@c0000 { - status = "okay"; - }; - - mvsdio@d4000 { - pinctrl-0 = <&sdio_pins>; - pinctrl-names = "default"; - status = "okay"; - /* No CD or WP GPIOs */ - broken-cd; - }; - - usb@50000 { - status = "okay"; - }; - - usb@51000 { - status = "okay"; - }; - - usb@52000 { - status = "okay"; - }; - - nand-controller@d0000 { - status = "okay"; - - nand@0 { - reg = <0>; - label = "pxa3xx_nand-0"; - nand-rb = <0>; - nand-on-flash-bbt; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "U-Boot"; - reg = <0 0x800000>; - }; - partition@800000 { - label = "Linux"; - reg = <0x800000 0x800000>; - }; - partition@1000000 { - label = "Filesystem"; - reg = <0x1000000 0x3f000000>; - }; - }; - }; - }; - }; - - bm-bppi { - status = "okay"; - }; - }; -}; - -&pciec { - status = "okay"; - - /* - * All 6 slots are physically present as - * standard PCIe slots on the board. - */ - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - pcie@2,0 { - /* Port 0, Lane 1 */ - status = "okay"; - }; - pcie@3,0 { - /* Port 0, Lane 2 */ - status = "okay"; - }; - pcie@4,0 { - /* Port 0, Lane 3 */ - status = "okay"; - }; - pcie@9,0 { - /* Port 2, Lane 0 */ - status = "okay"; - }; - pcie@a,0 { - /* Port 3, Lane 0 */ - status = "okay"; - }; -}; - -&mdio { - phy0: ethernet-phy@0 { - reg = <0>; - }; - - phy1: ethernet-phy@1 { - reg = <1>; - }; - - phy2: ethernet-phy@2 { - reg = <25>; - }; - - phy3: ethernet-phy@3 { - reg = <27>; - }; -}; - -&spi0 { - status = "okay"; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "m25p64", "jedec,spi-nor"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <20000000>; - }; -}; diff --git a/sys/gnu/dts/arm/armada-xp-gp.dts b/sys/gnu/dts/arm/armada-xp-gp.dts deleted file mode 100644 index b4cca507cf1..00000000000 --- a/sys/gnu/dts/arm/armada-xp-gp.dts +++ /dev/null @@ -1,230 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for Marvell Armada XP development board - * (DB-MV784MP-GP) - * - * Copyright (C) 2013-2014 Marvell - * - * Lior Amsalem - * Gregory CLEMENT - * Thomas Petazzoni - * - * Note: this Device Tree assumes that the bootloader has remapped the - * internal registers to 0xf1000000 (instead of the default - * 0xd0000000). The 0xf1000000 is the default used by the recent, - * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier - * boards were delivered with an older version of the bootloader that - * left internal registers mapped at 0xd0000000. If you are in this - * situation, you should either update your bootloader (preferred - * solution) or the below Device Tree should be adjusted. - */ - -/dts-v1/; -#include -#include "armada-xp-mv78460.dtsi" - -/ { - model = "Marvell Armada XP Development Board DB-MV784MP-GP"; - compatible = "marvell,axp-gp", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - /* - * 8 GB of plug-in RAM modules by default.The amount - * of memory available can be changed by the - * bootloader according the size of the module - * actually plugged. However, memory between - * 0xF0000000 to 0xFFFFFFFF cannot be used, as it is - * the address range used for I/O (internal registers, - * MBus windows). - */ - reg = <0x00000000 0x00000000 0x00000000 0xf0000000>, - <0x00000001 0x00000000 0x00000001 0x00000000>; - }; - - cpus { - pm_pic { - ctrl-gpios = <&gpio0 16 GPIO_ACTIVE_LOW>, - <&gpio0 17 GPIO_ACTIVE_LOW>, - <&gpio0 18 GPIO_ACTIVE_LOW>; - }; - }; - - soc { - ranges = ; - - devbus-bootcs { - status = "okay"; - - /* Device Bus parameters are required */ - - /* Read parameters */ - devbus,bus-width = <16>; - devbus,turn-off-ps = <60000>; - devbus,badr-skew-ps = <0>; - devbus,acc-first-ps = <124000>; - devbus,acc-next-ps = <248000>; - devbus,rd-setup-ps = <0>; - devbus,rd-hold-ps = <0>; - - /* Write parameters */ - devbus,sync-enable = <0>; - devbus,wr-high-ps = <60000>; - devbus,wr-low-ps = <60000>; - devbus,ale-wr-ps = <60000>; - - /* NOR 16 MiB */ - nor@0 { - compatible = "cfi-flash"; - reg = <0 0x1000000>; - bank-width = <2>; - }; - }; - - internal-regs { - serial@12000 { - status = "okay"; - }; - serial@12100 { - status = "okay"; - }; - serial@12200 { - status = "okay"; - }; - serial@12300 { - status = "okay"; - }; - pinctrl { - pinctrl-0 = <&pic_pins>; - pinctrl-names = "default"; - pic_pins: pic-pins-0 { - marvell,pins = "mpp16", "mpp17", - "mpp18"; - marvell,function = "gpio"; - }; - }; - sata@a0000 { - nr-ports = <2>; - status = "okay"; - }; - - ethernet@70000 { - status = "okay"; - phy = <&phy0>; - phy-mode = "qsgmii"; - buffer-manager = <&bm>; - bm,pool-long = <0>; - }; - ethernet@74000 { - status = "okay"; - phy = <&phy1>; - phy-mode = "qsgmii"; - buffer-manager = <&bm>; - bm,pool-long = <1>; - }; - ethernet@30000 { - status = "okay"; - phy = <&phy2>; - phy-mode = "qsgmii"; - buffer-manager = <&bm>; - bm,pool-long = <2>; - }; - ethernet@34000 { - status = "okay"; - phy = <&phy3>; - phy-mode = "qsgmii"; - buffer-manager = <&bm>; - bm,pool-long = <3>; - }; - - /* Front-side USB slot */ - usb@50000 { - status = "okay"; - }; - - /* Back-side USB slot */ - usb@51000 { - status = "okay"; - }; - - bm@c0000 { - status = "okay"; - }; - - nand-controller@d0000 { - status = "okay"; - - nand@0 { - reg = <0>; - label = "pxa3xx_nand-0"; - nand-rb = <0>; - nand-on-flash-bbt; - }; - }; - }; - - bm-bppi { - status = "okay"; - }; - }; -}; - -&pciec { - status = "okay"; - - /* - * The 3 slots are physically present as - * standard PCIe slots on the board. - */ - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - pcie@9,0 { - /* Port 2, Lane 0 */ - status = "okay"; - }; - pcie@a,0 { - /* Port 3, Lane 0 */ - status = "okay"; - }; -}; - -&mdio { - phy0: ethernet-phy@0 { - reg = <16>; - }; - - phy1: ethernet-phy@1 { - reg = <17>; - }; - - phy2: ethernet-phy@2 { - reg = <18>; - }; - - phy3: ethernet-phy@3 { - reg = <19>; - }; -}; - -&spi0 { - status = "okay"; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "n25q128a13", "jedec,spi-nor"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <108000000>; - }; -}; diff --git a/sys/gnu/dts/arm/armada-xp-lenovo-ix4-300d.dts b/sys/gnu/dts/arm/armada-xp-lenovo-ix4-300d.dts deleted file mode 100644 index 87dcb502f72..00000000000 --- a/sys/gnu/dts/arm/armada-xp-lenovo-ix4-300d.dts +++ /dev/null @@ -1,293 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for Lenovo Iomega ix4-300d - * - * Copyright (C) 2014, Benoit Masson - */ - -/dts-v1/; - -#include -#include -#include "armada-xp-mv78230.dtsi" - -/ { - model = "Lenovo Iomega ix4-300d"; - compatible = "lenovo,ix4-300d", "marvell,armadaxp-mv78230", - "marvell,armadaxp", "marvell,armada-370-xp"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0 0x00000000 0 0x20000000>; /* 512MB */ - }; - - soc { - ranges = ; - - internal-regs { - serial@12000 { - status = "okay"; - }; - - ethernet@70000 { - pinctrl-0 = <&ge0_rgmii_pins>; - pinctrl-names = "default"; - status = "okay"; - phy = <&phy0>; - phy-mode = "rgmii-id"; - }; - - ethernet@74000 { - pinctrl-0 = <&ge1_rgmii_pins>; - pinctrl-names = "default"; - status = "okay"; - phy = <&phy1>; - phy-mode = "rgmii-id"; - }; - - usb@50000 { - status = "okay"; - }; - - usb@51000 { - status = "okay"; - }; - - i2c@11000 { - clock-frequency = <400000>; - status = "okay"; - - adt7473@2e { - compatible = "adi,adt7473"; - reg = <0x2e>; - }; - - eeprom@50 { - compatible = "atmel,24c64"; - reg = <0x50>; - }; - - pcf8563@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; - - }; - - nand-controller@d0000 { - status = "okay"; - - nand@0 { - reg = <0>; - label = "pxa3xx_nand-0"; - nand-rb = <0>; - nand-on-flash-bbt; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x00000000 0x000e0000>; - read-only; - }; - - partition@e0000 { - label = "u-boot-env"; - reg = <0x000e0000 0x00020000>; - read-only; - }; - - partition@100000 { - label = "u-boot-env2"; - reg = <0x00100000 0x00020000>; - read-only; - }; - - partition@120000 { - label = "zImage"; - reg = <0x00120000 0x00400000>; - }; - - partition@520000 { - label = "initrd"; - reg = <0x00520000 0x00400000>; - }; - - partition@e00000 { - label = "boot"; - reg = <0x00e00000 0x3f200000>; - }; - }; - }; - }; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-0 = <&power_button_pin &reset_button_pin - &select_button_pin &scroll_button_pin>; - pinctrl-names = "default"; - - power-button { - label = "Power Button"; - linux,code = ; - gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; - }; - - reset-button { - label = "Reset Button"; - linux,code = ; - gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; - }; - - select-button { - label = "Select Button"; - linux,code = ; - gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; - }; - - scroll-button { - label = "Scroll Button"; - linux,code = ; - gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; - }; - }; - - spi3 { - compatible = "spi-gpio"; - status = "okay"; - gpio-sck = <&gpio0 25 GPIO_ACTIVE_LOW>; - gpio-mosi = <&gpio1 15 GPIO_ACTIVE_LOW>; /*gpio 47*/ - cs-gpios = <&gpio0 27 GPIO_ACTIVE_LOW>; - num-chipselects = <1>; - #address-cells = <1>; - #size-cells = <0>; - - gpio_spi: gpio_spi@0 { - compatible = "fairchild,74hc595"; - gpio-controller; - #gpio-cells = <2>; - reg = <0>; - registers-number = <1>; - spi-max-frequency = <100000>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&hdd_led_pin>; - pinctrl-names = "default"; - - hdd-led { - label = "ix4-300d:hdd:blue"; - gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - power-led { - label = "ix4-300d:power:white"; - gpios = <&gpio_spi 1 GPIO_ACTIVE_LOW>; - /* init blinking while booting */ - linux,default-trigger = "timer"; - default-state = "on"; - }; - - sysfail-led { - label = "ix4-300d:sysfail:red"; - gpios = <&gpio_spi 2 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - sys-led { - label = "ix4-300d:sys:blue"; - gpios = <&gpio_spi 3 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - hddfail-led { - label = "ix4-300d:hddfail:red"; - gpios = <&gpio_spi 4 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - }; - - /* - * Warning: you need both eth1 & 0 PHY initialized (i.e having - * them up does the tweak) for poweroff to shutdown otherwise it - * reboots - */ - gpio-poweroff { - compatible = "gpio-poweroff"; - pinctrl-0 = <&poweroff_pin>; - pinctrl-names = "default"; - gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>; - }; -}; -&pciec { - status = "okay"; - - /* Quad port sata: Marvell 88SX7042 */ - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - - /* USB 3.0 xHCI controller: NEC D720200F1 */ - pcie@5,0 { - /* Port 1, Lane 0 */ - status = "okay"; - }; -}; - -&mdio { - phy0: ethernet-phy@0 { /* Marvell 88E1318 */ - reg = <0>; - }; - - phy1: ethernet-phy@1 { /* Marvell 88E1318 */ - reg = <1>; - }; -}; - -&pinctrl { - poweroff_pin: poweroff-pin { - marvell,pins = "mpp24"; - marvell,function = "gpio"; - }; - - power_button_pin: power-button-pin { - marvell,pins = "mpp44"; - marvell,function = "gpio"; - }; - - reset_button_pin: reset-button-pin { - marvell,pins = "mpp45"; - marvell,function = "gpio"; - }; - select_button_pin: select-button-pin { - marvell,pins = "mpp41"; - marvell,function = "gpio"; - }; - - scroll_button_pin: scroll-button-pin { - marvell,pins = "mpp42"; - marvell,function = "gpio"; - }; - - hdd_led_pin: hdd-led-pin { - marvell,pins = "mpp26"; - marvell,function = "gpio"; - }; -}; diff --git a/sys/gnu/dts/arm/armada-xp-linksys-mamba.dts b/sys/gnu/dts/arm/armada-xp-linksys-mamba.dts deleted file mode 100644 index 8480a16919a..00000000000 --- a/sys/gnu/dts/arm/armada-xp-linksys-mamba.dts +++ /dev/null @@ -1,399 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Device Tree file for the Linksys WRT1900AC (Mamba). - * - * Note: this board is shipped with a new generation boot loader that - * remaps internal registers at 0xf1000000. Therefore, if earlyprintk - * is used, the CONFIG_DEBUG_MVEBU_UART0_ALTERNATE option should be - * used. - * - * Copyright (C) 2014 Imre Kaloz - * - * Based on armada-xp-axpwifiap.dts: - * - * Copyright (C) 2013 Marvell - * - * Thomas Petazzoni - */ - -/dts-v1/; -#include -#include -#include "armada-xp-mv78230.dtsi" - -/ { - model = "Linksys WRT1900AC"; - compatible = "linksys,mamba", "marvell,armadaxp-mv78230", - "marvell,armadaxp", "marvell,armada-370-xp"; - - chosen { - bootargs = "console=ttyS0,115200"; - stdout-path = &uart0; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x00000000 0x00000000 0x10000000>; /* 256MB */ - }; - - soc { - ranges = ; - - internal-regs { - - rtc@10300 { - /* No crystal connected to the internal RTC */ - status = "disabled"; - }; - - /* J10: VCC, NC, RX, NC, TX, GND */ - serial@12000 { - status = "okay"; - }; - - sata@a0000 { - nr-ports = <1>; - status = "okay"; - }; - - ethernet@70000 { - pinctrl-0 = <&ge0_rgmii_pins>; - pinctrl-names = "default"; - status = "okay"; - phy-mode = "rgmii-id"; - buffer-manager = <&bm>; - bm,pool-long = <0>; - bm,pool-short = <1>; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - - ethernet@74000 { - pinctrl-0 = <&ge1_rgmii_pins>; - pinctrl-names = "default"; - status = "okay"; - phy-mode = "rgmii-id"; - buffer-manager = <&bm>; - bm,pool-long = <2>; - bm,pool-short = <3>; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - - /* USB part of the eSATA/USB 2.0 port */ - usb@50000 { - status = "okay"; - }; - - i2c@11000 { - status = "okay"; - clock-frequency = <100000>; - - tmp421@4c { - compatible = "ti,tmp421"; - reg = <0x4c>; - }; - - tlc59116@68 { - #address-cells = <1>; - #size-cells = <0>; - #gpio-cells = <2>; - compatible = "ti,tlc59116"; - reg = <0x68>; - - wan_amber@0 { - label = "mamba:amber:wan"; - reg = <0x0>; - }; - - wan_white@1 { - label = "mamba:white:wan"; - reg = <0x1>; - }; - - wlan_2g@2 { - label = "mamba:white:wlan_2g"; - reg = <0x2>; - }; - - wlan_5g@3 { - label = "mamba:white:wlan_5g"; - reg = <0x3>; - }; - - esata@4 { - label = "mamba:white:esata"; - reg = <0x4>; - linux,default-trigger = "disk-activity"; - }; - - usb2@5 { - label = "mamba:white:usb2"; - reg = <0x5>; - }; - - usb3_1@6 { - label = "mamba:white:usb3_1"; - reg = <0x6>; - }; - - usb3_2@7 { - label = "mamba:white:usb3_2"; - reg = <0x7>; - }; - - wps_white@8 { - label = "mamba:white:wps"; - reg = <0x8>; - }; - - wps_amber@9 { - label = "mamba:amber:wps"; - reg = <0x9>; - }; - }; - }; - - bm@c8000 { - status = "okay"; - }; - }; - - bm-bppi { - status = "okay"; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&keys_pin>; - pinctrl-names = "default"; - - wps { - label = "WPS"; - linux,code = ; - gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; - }; - - reset { - label = "Factory Reset Button"; - linux,code = ; - gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&power_led_pin>; - pinctrl-names = "default"; - - power { - label = "mamba:white:power"; - gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; - - pwm_fan { - /* SUNON HA4010V4-0000-C99 */ - - compatible = "pwm-fan"; - pwms = <&gpio0 24 4000>; - }; -}; - -&pciec { - status = "okay"; - - /* Etron EJ168 USB 3.0 controller */ - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - - /* First mini-PCIe port */ - pcie@2,0 { - /* Port 0, Lane 1 */ - status = "okay"; - }; - - /* Second mini-PCIe port */ - pcie@3,0 { - /* Port 0, Lane 3 */ - status = "okay"; - }; -}; - -&pinctrl { - - keys_pin: keys-pin { - marvell,pins = "mpp32", "mpp33"; - marvell,function = "gpio"; - }; - - power_led_pin: power-led-pin { - marvell,pins = "mpp40"; - marvell,function = "gpio"; - }; - - gpio_fan_pin: gpio-fan-pin { - marvell,pins = "mpp24"; - marvell,function = "gpio"; - }; -}; - -&spi0 { - status = "okay"; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "everspin,mr25h256"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <40000000>; - }; -}; - -&mdio { - status = "okay"; - - switch@0 { - compatible = "marvell,mv88e6085"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "lan4"; - }; - - port@1 { - reg = <1>; - label = "lan3"; - }; - - port@2 { - reg = <2>; - label = "lan2"; - }; - - port@3 { - reg = <3>; - label = "lan1"; - }; - - port@4 { - reg = <4>; - label = "internet"; - }; - - port@5 { - reg = <5>; - label = "cpu"; - ethernet = <ð0>; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; - }; -}; - -&nand_controller { - status = "okay"; - - nand@0 { - reg = <0>; - label = "pxa3xx_nand-0"; - nand-rb = <0>; - marvell,nand-keep-config; - nand-on-flash-bbt; - nand-ecc-strength = <4>; - nand-ecc-step-size = <512>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0x100000>; /* 1MB */ - read-only; - }; - - partition@100000 { - label = "u_env"; - reg = <0x100000 0x40000>; /* 256KB */ - }; - - partition@140000 { - label = "s_env"; - reg = <0x140000 0x40000>; /* 256KB */ - }; - - partition@900000 { - label = "devinfo"; - reg = <0x900000 0x100000>; /* 1MB */ - read-only; - }; - - /* kernel1 overlaps with rootfs1 by design */ - partition@a00000 { - label = "kernel1"; - reg = <0xa00000 0x2800000>; /* 40MB */ - }; - - partition@d00000 { - label = "rootfs1"; - reg = <0xd00000 0x2500000>; /* 37MB */ - }; - - /* kernel2 overlaps with rootfs2 by design */ - partition@3200000 { - label = "kernel2"; - reg = <0x3200000 0x2800000>; /* 40MB */ - }; - - partition@3500000 { - label = "rootfs2"; - reg = <0x3500000 0x2500000>; /* 37MB */ - }; - - /* - * 38MB, last MB is for the BBT, not writable - */ - partition@5a00000 { - label = "syscfg"; - reg = <0x5a00000 0x2600000>; - }; - - /* - * Unused area between "s_env" and "devinfo". - * Moved here because otherwise the renumbered - * partitions would break the bootloader - * supplied bootargs - */ - partition@180000 { - label = "unused_area"; - reg = <0x180000 0x780000>; /* 7.5MB */ - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/armada-xp-matrix.dts b/sys/gnu/dts/arm/armada-xp-matrix.dts deleted file mode 100644 index 1395cea1275..00000000000 --- a/sys/gnu/dts/arm/armada-xp-matrix.dts +++ /dev/null @@ -1,79 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for Marvell Armada XP Matrix board - * - * Copyright (C) 2013 Marvell - * - * Lior Amsalem - */ - -/dts-v1/; -#include "armada-xp-mv78460.dtsi" - -/ { - model = "Marvell Armada XP Matrix Board"; - compatible = "marvell,axp-matrix", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - /* - * This board has 4 GB of RAM, but the last 256 MB of - * RAM are not usable due to the overlap with the MBus - * Window address range - */ - reg = <0 0x00000000 0 0xf0000000>; - }; - - soc { - ranges = ; - - internal-regs { - serial@12000 { - status = "okay"; - }; - serial@12100 { - status = "okay"; - }; - serial@12200 { - status = "okay"; - }; - serial@12300 { - status = "okay"; - }; - - sata@a0000 { - nr-ports = <2>; - status = "okay"; - }; - - ethernet@30000 { - status = "okay"; - phy-mode = "sgmii"; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - - usb@50000 { - status = "okay"; - }; - }; - }; -}; - -&pciec { - status = "okay"; - - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; -}; diff --git a/sys/gnu/dts/arm/armada-xp-mv78230.dtsi b/sys/gnu/dts/arm/armada-xp-mv78230.dtsi deleted file mode 100644 index 8558bf6bb54..00000000000 --- a/sys/gnu/dts/arm/armada-xp-mv78230.dtsi +++ /dev/null @@ -1,207 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree Include file for Marvell Armada XP family SoC - * - * Copyright (C) 2012 Marvell - * - * Thomas Petazzoni - * - * Contains definitions specific to the Armada XP MV78230 SoC that are not - * common to all Armada XP SoCs. - */ - -#include "armada-xp.dtsi" - -/ { - model = "Marvell Armada XP MV78230 SoC"; - compatible = "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp"; - - aliases { - gpio0 = &gpio0; - gpio1 = &gpio1; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "marvell,armada-xp-smp"; - - cpu@0 { - device_type = "cpu"; - compatible = "marvell,sheeva-v7"; - reg = <0>; - clocks = <&cpuclk 0>; - clock-latency = <1000000>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "marvell,sheeva-v7"; - reg = <1>; - clocks = <&cpuclk 1>; - clock-latency = <1000000>; - }; - }; - - soc { - /* - * MV78230 has 2 PCIe units Gen2.0: One unit can be - * configured as x4 or quad x1 lanes. One unit is - * x1 only. - */ - pciec: pcie@82000000 { - compatible = "marvell,armada-xp-pcie"; - status = "disabled"; - device_type = "pci"; - - #address-cells = <3>; - #size-cells = <2>; - - msi-parent = <&mpic>; - bus-range = <0x00 0xff>; - - ranges = - <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */ - 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */ - 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */ - 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */ - 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */ - 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ - 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ - 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */ - 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */ - 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */ - 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */ - 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */ - 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */ - 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */ - 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */>; - - pcie1: pcie@1,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; - reg = <0x0800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 - 0x81000000 0 0 0x81000000 0x1 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 58>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 5>; - status = "disabled"; - }; - - pcie2: pcie@2,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; - reg = <0x1000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 - 0x81000000 0 0 0x81000000 0x2 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 59>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <1>; - clocks = <&gateclk 6>; - status = "disabled"; - }; - - pcie3: pcie@3,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x48000 0 0x2000>; - reg = <0x1800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 - 0x81000000 0 0 0x81000000 0x3 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 60>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <2>; - clocks = <&gateclk 7>; - status = "disabled"; - }; - - pcie4: pcie@4,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>; - reg = <0x2000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 - 0x81000000 0 0 0x81000000 0x4 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 61>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <3>; - clocks = <&gateclk 8>; - status = "disabled"; - }; - - pcie5: pcie@5,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x80000 0 0x2000>; - reg = <0x2800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0 - 0x81000000 0 0 0x81000000 0x5 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 62>; - marvell,pcie-port = <1>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 9>; - status = "disabled"; - }; - }; - - internal-regs { - gpio0: gpio@18100 { - compatible = "marvell,armada-370-gpio", - "marvell,orion-gpio"; - reg = <0x18100 0x40>, <0x181c0 0x08>; - reg-names = "gpio", "pwm"; - ngpios = <32>; - gpio-controller; - #gpio-cells = <2>; - #pwm-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <82>, <83>, <84>, <85>; - clocks = <&coreclk 0>; - }; - - gpio1: gpio@18140 { - compatible = "marvell,armada-370-gpio", - "marvell,orion-gpio"; - reg = <0x18140 0x40>, <0x181c8 0x08>; - reg-names = "gpio", "pwm"; - ngpios = <17>; - gpio-controller; - #gpio-cells = <2>; - #pwm-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <87>, <88>, <89>; - clocks = <&coreclk 0>; - }; - }; - }; -}; - -&pinctrl { - compatible = "marvell,mv78230-pinctrl"; -}; diff --git a/sys/gnu/dts/arm/armada-xp-mv78260.dtsi b/sys/gnu/dts/arm/armada-xp-mv78260.dtsi deleted file mode 100644 index 2d85fe8ac32..00000000000 --- a/sys/gnu/dts/arm/armada-xp-mv78260.dtsi +++ /dev/null @@ -1,314 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree Include file for Marvell Armada XP family SoC - * - * Copyright (C) 2012 Marvell - * - * Thomas Petazzoni - * - * Contains definitions specific to the Armada XP MV78260 SoC that are not - * common to all Armada XP SoCs. - */ - -#include "armada-xp.dtsi" - -/ { - model = "Marvell Armada XP MV78260 SoC"; - compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp"; - - aliases { - gpio0 = &gpio0; - gpio1 = &gpio1; - gpio2 = &gpio2; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "marvell,armada-xp-smp"; - - cpu@0 { - device_type = "cpu"; - compatible = "marvell,sheeva-v7"; - reg = <0>; - clocks = <&cpuclk 0>; - clock-latency = <1000000>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "marvell,sheeva-v7"; - reg = <1>; - clocks = <&cpuclk 1>; - clock-latency = <1000000>; - }; - }; - - soc { - /* - * MV78260 has 3 PCIe units Gen2.0: Two units can be - * configured as x4 or quad x1 lanes. One unit is - * x4 only. - */ - pciec: pcie@82000000 { - compatible = "marvell,armada-xp-pcie"; - status = "disabled"; - device_type = "pci"; - - #address-cells = <3>; - #size-cells = <2>; - - msi-parent = <&mpic>; - bus-range = <0x00 0xff>; - - ranges = - <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */ - 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */ - 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */ - 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */ - 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */ - 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */ - 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */ - 0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */ - 0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */ - 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ - 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ - 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */ - 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */ - 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */ - 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */ - 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */ - 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */ - - 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */ - 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */ - 0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */ - 0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */ - 0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */ - 0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */ - 0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */ - 0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */ - - 0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */ - 0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */>; - - pcie1: pcie@1,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; - reg = <0x0800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 - 0x81000000 0 0 0x81000000 0x1 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 58>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 5>; - status = "disabled"; - }; - - pcie2: pcie@2,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; - reg = <0x1000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 - 0x81000000 0 0 0x81000000 0x2 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 59>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <1>; - clocks = <&gateclk 6>; - status = "disabled"; - }; - - pcie3: pcie@3,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x48000 0 0x2000>; - reg = <0x1800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 - 0x81000000 0 0 0x81000000 0x3 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 60>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <2>; - clocks = <&gateclk 7>; - status = "disabled"; - }; - - pcie4: pcie@4,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>; - reg = <0x2000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 - 0x81000000 0 0 0x81000000 0x4 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 61>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <3>; - clocks = <&gateclk 8>; - status = "disabled"; - }; - - pcie5: pcie@5,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x80000 0 0x2000>; - reg = <0x2800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0 - 0x81000000 0 0 0x81000000 0x5 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 62>; - marvell,pcie-port = <1>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 9>; - status = "disabled"; - }; - - pcie6: pcie@6,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x84000 0 0x2000>; - reg = <0x3000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0 - 0x81000000 0 0 0x81000000 0x6 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 63>; - marvell,pcie-port = <1>; - marvell,pcie-lane = <1>; - clocks = <&gateclk 10>; - status = "disabled"; - }; - - pcie7: pcie@7,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x88000 0 0x2000>; - reg = <0x3800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0 - 0x81000000 0 0 0x81000000 0x7 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 64>; - marvell,pcie-port = <1>; - marvell,pcie-lane = <2>; - clocks = <&gateclk 11>; - status = "disabled"; - }; - - pcie8: pcie@8,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x8c000 0 0x2000>; - reg = <0x4000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0 - 0x81000000 0 0 0x81000000 0x8 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 65>; - marvell,pcie-port = <1>; - marvell,pcie-lane = <3>; - clocks = <&gateclk 12>; - status = "disabled"; - }; - - pcie9: pcie@9,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x42000 0 0x2000>; - reg = <0x4800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0 - 0x81000000 0 0 0x81000000 0x9 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 99>; - marvell,pcie-port = <2>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 26>; - status = "disabled"; - }; - }; - - internal-regs { - gpio0: gpio@18100 { - compatible = "marvell,armada-370-gpio", - "marvell,orion-gpio"; - reg = <0x18100 0x40>, <0x181c0 0x08>; - reg-names = "gpio", "pwm"; - ngpios = <32>; - gpio-controller; - #gpio-cells = <2>; - #pwm-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <82>, <83>, <84>, <85>; - clocks = <&coreclk 0>; - }; - - gpio1: gpio@18140 { - compatible = "marvell,armada-370-gpio", - "marvell,orion-gpio"; - reg = <0x18140 0x40>, <0x181c8 0x08>; - reg-names = "gpio", "pwm"; - ngpios = <32>; - gpio-controller; - #gpio-cells = <2>; - #pwm-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <87>, <88>, <89>, <90>; - clocks = <&coreclk 0>; - }; - - gpio2: gpio@18180 { - compatible = "marvell,armada-370-gpio", - "marvell,orion-gpio"; - reg = <0x18180 0x40>; - ngpios = <3>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <91>; - }; - - eth3: ethernet@34000 { - compatible = "marvell,armada-xp-neta"; - reg = <0x34000 0x4000>; - interrupts = <14>; - clocks = <&gateclk 1>; - status = "disabled"; - }; - }; - }; -}; - -&pinctrl { - compatible = "marvell,mv78260-pinctrl"; -}; diff --git a/sys/gnu/dts/arm/armada-xp-mv78460.dtsi b/sys/gnu/dts/arm/armada-xp-mv78460.dtsi deleted file mode 100644 index 230a3fd36b3..00000000000 --- a/sys/gnu/dts/arm/armada-xp-mv78460.dtsi +++ /dev/null @@ -1,353 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree Include file for Marvell Armada XP family SoC - * - * Copyright (C) 2012 Marvell - * - * Thomas Petazzoni - * - * Contains definitions specific to the Armada XP MV78460 SoC that are not - * common to all Armada XP SoCs. - */ - -#include "armada-xp.dtsi" - -/ { - model = "Marvell Armada XP MV78460 SoC"; - compatible = "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp"; - - aliases { - gpio0 = &gpio0; - gpio1 = &gpio1; - gpio2 = &gpio2; - }; - - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "marvell,armada-xp-smp"; - - cpu@0 { - device_type = "cpu"; - compatible = "marvell,sheeva-v7"; - reg = <0>; - clocks = <&cpuclk 0>; - clock-latency = <1000000>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "marvell,sheeva-v7"; - reg = <1>; - clocks = <&cpuclk 1>; - clock-latency = <1000000>; - }; - - cpu@2 { - device_type = "cpu"; - compatible = "marvell,sheeva-v7"; - reg = <2>; - clocks = <&cpuclk 2>; - clock-latency = <1000000>; - }; - - cpu@3 { - device_type = "cpu"; - compatible = "marvell,sheeva-v7"; - reg = <3>; - clocks = <&cpuclk 3>; - clock-latency = <1000000>; - }; - }; - - soc { - /* - * MV78460 has 4 PCIe units Gen2.0: Two units can be - * configured as x4 or quad x1 lanes. Two units are - * x4/x1. - */ - pciec: pcie@82000000 { - compatible = "marvell,armada-xp-pcie"; - status = "disabled"; - device_type = "pci"; - - #address-cells = <3>; - #size-cells = <2>; - - msi-parent = <&mpic>; - bus-range = <0x00 0xff>; - - ranges = - <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */ - 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */ - 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */ - 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */ - 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */ - 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */ - 0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000 /* Port 3.0 registers */ - 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */ - 0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */ - 0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */ - 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ - 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ - 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */ - 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */ - 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */ - 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */ - 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */ - 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */ - - 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */ - 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */ - 0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */ - 0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */ - 0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */ - 0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */ - 0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */ - 0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */ - - 0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */ - 0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */ - - 0x82000000 0xa 0 MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */ - 0x81000000 0xa 0 MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO */>; - - pcie1: pcie@1,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; - reg = <0x0800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 - 0x81000000 0 0 0x81000000 0x1 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 58>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 5>; - status = "disabled"; - }; - - pcie2: pcie@2,0 { - device_type = "pci"; - assigned-addresses = <0x82001000 0 0x44000 0 0x2000>; - reg = <0x1000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 - 0x81000000 0 0 0x81000000 0x2 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 59>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <1>; - clocks = <&gateclk 6>; - status = "disabled"; - }; - - pcie3: pcie@3,0 { - device_type = "pci"; - assigned-addresses = <0x82001800 0 0x48000 0 0x2000>; - reg = <0x1800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 - 0x81000000 0 0 0x81000000 0x3 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 60>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <2>; - clocks = <&gateclk 7>; - status = "disabled"; - }; - - pcie4: pcie@4,0 { - device_type = "pci"; - assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>; - reg = <0x2000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 - 0x81000000 0 0 0x81000000 0x4 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 61>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <3>; - clocks = <&gateclk 8>; - status = "disabled"; - }; - - pcie5: pcie@5,0 { - device_type = "pci"; - assigned-addresses = <0x82002800 0 0x80000 0 0x2000>; - reg = <0x2800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0 - 0x81000000 0 0 0x81000000 0x5 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 62>; - marvell,pcie-port = <1>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 9>; - status = "disabled"; - }; - - pcie6: pcie@6,0 { - device_type = "pci"; - assigned-addresses = <0x82003000 0 0x84000 0 0x2000>; - reg = <0x3000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0 - 0x81000000 0 0 0x81000000 0x6 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 63>; - marvell,pcie-port = <1>; - marvell,pcie-lane = <1>; - clocks = <&gateclk 10>; - status = "disabled"; - }; - - pcie7: pcie@7,0 { - device_type = "pci"; - assigned-addresses = <0x82003800 0 0x88000 0 0x2000>; - reg = <0x3800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0 - 0x81000000 0 0 0x81000000 0x7 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 64>; - marvell,pcie-port = <1>; - marvell,pcie-lane = <2>; - clocks = <&gateclk 11>; - status = "disabled"; - }; - - pcie8: pcie@8,0 { - device_type = "pci"; - assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>; - reg = <0x4000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0 - 0x81000000 0 0 0x81000000 0x8 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 65>; - marvell,pcie-port = <1>; - marvell,pcie-lane = <3>; - clocks = <&gateclk 12>; - status = "disabled"; - }; - - pcie9: pcie@9,0 { - device_type = "pci"; - assigned-addresses = <0x82004800 0 0x42000 0 0x2000>; - reg = <0x4800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0 - 0x81000000 0 0 0x81000000 0x9 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 99>; - marvell,pcie-port = <2>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 26>; - status = "disabled"; - }; - - pcie10: pcie@a,0 { - device_type = "pci"; - assigned-addresses = <0x82005000 0 0x82000 0 0x2000>; - reg = <0x5000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0 - 0x81000000 0 0 0x81000000 0xa 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 103>; - marvell,pcie-port = <3>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 27>; - status = "disabled"; - }; - }; - - internal-regs { - gpio0: gpio@18100 { - compatible = "marvell,armada-370-gpio", - "marvell,orion-gpio"; - reg = <0x18100 0x40>, <0x181c0 0x08>; - reg-names = "gpio", "pwm"; - ngpios = <32>; - gpio-controller; - #gpio-cells = <2>; - #pwm-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <82>, <83>, <84>, <85>; - clocks = <&coreclk 0>; - }; - - gpio1: gpio@18140 { - compatible = "marvell,armada-370-gpio", - "marvell,orion-gpio"; - reg = <0x18140 0x40>, <0x181c8 0x08>; - reg-names = "gpio", "pwm"; - ngpios = <32>; - gpio-controller; - #gpio-cells = <2>; - #pwm-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <87>, <88>, <89>, <90>; - clocks = <&coreclk 0>; - }; - - gpio2: gpio@18180 { - compatible = "marvell,armada-370-gpio", - "marvell,orion-gpio"; - reg = <0x18180 0x40>; - ngpios = <3>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <91>; - }; - - eth3: ethernet@34000 { - compatible = "marvell,armada-xp-neta"; - reg = <0x34000 0x4000>; - interrupts = <14>; - clocks = <&gateclk 1>; - status = "disabled"; - }; - }; - }; -}; - -&pinctrl { - compatible = "marvell,mv78460-pinctrl"; -}; diff --git a/sys/gnu/dts/arm/armada-xp-netgear-rn2120.dts b/sys/gnu/dts/arm/armada-xp-netgear-rn2120.dts deleted file mode 100644 index 8ea73587db8..00000000000 --- a/sys/gnu/dts/arm/armada-xp-netgear-rn2120.dts +++ /dev/null @@ -1,357 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for NETGEAR ReadyNAS 2120 - * - * Copyright (C) 2013, Arnaud EBALARD - */ - -/dts-v1/; - -#include -#include -#include "armada-xp-mv78230.dtsi" - -/ { - model = "NETGEAR ReadyNAS 2120"; - compatible = "netgear,readynas-2120", "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0 0x00000000 0 0x80000000>; /* 2GB */ - }; - - soc { - ranges = ; - - internal-regs { - - /* RTC is provided by Intersil ISL12057 I2C RTC chip */ - rtc@10300 { - status = "disabled"; - }; - - i2c@11000 { - clock-frequency = <400000>; - status = "okay"; - - /* Controller for rear fan #1 of 3 (Protechnic - * MGT4012XB-O20, 8000RPM) near eSATA port */ - g762_fan1: g762@3e { - compatible = "gmt,g762"; - reg = <0x3e>; - clocks = <&g762_clk>; /* input clock */ - fan_gear_mode = <0>; - fan_startv = <1>; - pwm_polarity = <0>; - }; - - /* Controller for rear (center) fan #2 of 3 */ - g762_fan2: g762@48 { - compatible = "gmt,g762"; - reg = <0x48>; - clocks = <&g762_clk>; /* input clock */ - fan_gear_mode = <0>; - fan_startv = <1>; - pwm_polarity = <0>; - }; - - /* Controller for rear fan #3 of 3 */ - g762_fan3: g762@49 { - compatible = "gmt,g762"; - reg = <0x49>; - clocks = <&g762_clk>; /* input clock */ - fan_gear_mode = <0>; - fan_startv = <1>; - pwm_polarity = <0>; - }; - - /* Temperature sensor */ - g751: g751@4c { - compatible = "gmt,g751"; - reg = <0x4c>; - }; - - isl12057: rtc@68 { - compatible = "isil,isl12057"; - reg = <0x68>; - wakeup-source; - }; - }; - - serial@12000 { - status = "okay"; - }; - - /* Front USB 2.0 port */ - usb@50000 { - status = "okay"; - }; - - ethernet@70000 { - pinctrl-0 = <&ge0_rgmii_pins>; - pinctrl-names = "default"; - - status = "okay"; - phy = <&phy0>; - phy-mode = "rgmii-id"; - }; - - ethernet@74000 { - pinctrl-0 = <&ge1_rgmii_pins>; - pinctrl-names = "default"; - - status = "okay"; - phy = <&phy1>; - phy-mode = "rgmii-id"; - }; - - /* Two rear eSATA ports */ - sata@a0000 { - nr-ports = <2>; - status = "okay"; - }; - }; - }; - - clocks { - g762_clk: g762-oscillator { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&sata1_led_pin &sata2_led_pin &err_led_pin - &sata3_led_pin &sata4_led_pin>; - pinctrl-names = "default"; - - red-sata1-led { - label = "rn2120:red:sata1"; - gpios = <&gpio0 31 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - red-sata2-led { - label = "rn2120:red:sata2"; - gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - red-sata3-led { - label = "rn2120:red:sata3"; - gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - red-sata4-led { - label = "rn2120:red:sata4"; - gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - red-err-led { - label = "rn2120:red:err"; - gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-0 = <&power_button_pin &reset_button_pin>; - pinctrl-names = "default"; - - power-button { - label = "Power Button"; - linux,code = ; - gpios = <&gpio0 27 GPIO_ACTIVE_HIGH>; - }; - - reset-button { - label = "Reset Button"; - linux,code = ; - gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-poweroff { - compatible = "gpio-poweroff"; - pinctrl-0 = <&poweroff>; - pinctrl-names = "default"; - gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; - }; -}; - -&pciec { - status = "okay"; - - /* Connected to first Marvell 88SE9170 SATA controller */ - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - - /* Connected to second Marvell 88SE9170 SATA controller */ - pcie@2,0 { - /* Port 0, Lane 1 */ - status = "okay"; - }; - - /* Connected to Fresco Logic FL1009 USB 3.0 controller */ - pcie@5,0 { - /* Port 1, Lane 0 */ - status = "okay"; - }; -}; - -&mdio { - phy0: ethernet-phy@0 { /* Marvell 88E1318 */ - reg = <0>; - }; - - phy1: ethernet-phy@1 { /* Marvell 88E1318 */ - reg = <1>; - }; -}; - - -&pinctrl { - poweroff: poweroff { - marvell,pins = "mpp42"; - marvell,function = "gpio"; - }; - - power_button_pin: power-button-pin { - marvell,pins = "mpp27"; - marvell,function = "gpio"; - }; - - reset_button_pin: reset-button-pin { - marvell,pins = "mpp41"; - marvell,function = "gpio"; - }; - - sata1_led_pin: sata1-led-pin { - marvell,pins = "mpp31"; - marvell,function = "gpio"; - }; - - sata2_led_pin: sata2-led-pin { - marvell,pins = "mpp40"; - marvell,function = "gpio"; - }; - - sata3_led_pin: sata3-led-pin { - marvell,pins = "mpp44"; - marvell,function = "gpio"; - }; - - sata4_led_pin: sata4-led-pin { - marvell,pins = "mpp47"; - marvell,function = "gpio"; - }; - - sata1_power_pin: sata1-power-pin { - marvell,pins = "mpp24"; - marvell,function = "gpio"; - }; - - sata2_power_pin: sata2-power-pin { - marvell,pins = "mpp25"; - marvell,function = "gpio"; - }; - - sata3_power_pin: sata3-power-pin { - marvell,pins = "mpp26"; - marvell,function = "gpio"; - }; - - sata4_power_pin: sata4-power-pin { - marvell,pins = "mpp28"; - marvell,function = "gpio"; - }; - - sata1_pres_pin: sata1-pres-pin { - marvell,pins = "mpp32"; - marvell,function = "gpio"; - }; - - sata2_pres_pin: sata2-pres-pin { - marvell,pins = "mpp33"; - marvell,function = "gpio"; - }; - - sata3_pres_pin: sata3-pres-pin { - marvell,pins = "mpp34"; - marvell,function = "gpio"; - }; - - sata4_pres_pin: sata4-pres-pin { - marvell,pins = "mpp35"; - marvell,function = "gpio"; - }; - - err_led_pin: err-led-pin { - marvell,pins = "mpp45"; - marvell,function = "gpio"; - }; -}; - -&nand_controller { - status = "okay"; - - nand@0 { - reg = <0>; - label = "pxa3xx_nand-0"; - nand-rb = <0>; - marvell,nand-keep-config; - nand-on-flash-bbt; - - /* Use Hardware BCH ECC */ - nand-ecc-strength = <4>; - nand-ecc-step-size = <512>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0x180000>; /* 1.5MB */ - read-only; - }; - - partition@180000 { - label = "u-boot-env"; - reg = <0x180000 0x20000>; /* 128KB */ - read-only; - }; - - partition@200000 { - label = "uImage"; - reg = <0x0200000 0x600000>; /* 6MB */ - }; - - partition@800000 { - label = "minirootfs"; - reg = <0x0800000 0x400000>; /* 4MB */ - }; - - /* Last MB is for the BBT, i.e. not writable */ - partition@c00000 { - label = "ubifs"; - reg = <0x0c00000 0x7400000>; /* 116MB */ - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/armada-xp-openblocks-ax3-4.dts b/sys/gnu/dts/arm/armada-xp-openblocks-ax3-4.dts deleted file mode 100644 index 0efcc166dab..00000000000 --- a/sys/gnu/dts/arm/armada-xp-openblocks-ax3-4.dts +++ /dev/null @@ -1,211 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for OpenBlocks AX3-4 board - * - * Copyright (C) 2012 Marvell - * - * Thomas Petazzoni - */ - -/dts-v1/; -#include -#include -#include "armada-xp-mv78260.dtsi" - -/ { - model = "PlatHome OpenBlocks AX3-4 board"; - compatible = "plathome,openblocks-ax3-4", "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0 0x00000000 0 0x40000000>; /* 1 GB soldered on */ - }; - - soc { - ranges = ; - - devbus-bootcs { - status = "okay"; - - /* Device Bus parameters are required */ - - /* Read parameters */ - devbus,bus-width = <16>; - devbus,turn-off-ps = <60000>; - devbus,badr-skew-ps = <0>; - devbus,acc-first-ps = <124000>; - devbus,acc-next-ps = <248000>; - devbus,rd-setup-ps = <0>; - devbus,rd-hold-ps = <0>; - - /* Write parameters */ - devbus,sync-enable = <0>; - devbus,wr-high-ps = <60000>; - devbus,wr-low-ps = <60000>; - devbus,ale-wr-ps = <60000>; - - /* NOR 128 MiB */ - nor@0 { - compatible = "cfi-flash"; - reg = <0 0x8000000>; - bank-width = <2>; - }; - }; - - internal-regs { - rtc@10300 { - /* No crystal connected to the internal RTC */ - status = "disabled"; - }; - serial@12000 { - status = "okay"; - }; - serial@12100 { - status = "okay"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins>; - - red_led { - label = "red_led"; - gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - yellow_led { - label = "yellow_led"; - gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - green_led { - label = "green_led"; - gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - init { - label = "Init Button"; - linux,code = ; - gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; - }; - }; - - ethernet@70000 { - status = "okay"; - phy = <&phy0>; - phy-mode = "sgmii"; - buffer-manager = <&bm>; - bm,pool-long = <0>; - }; - ethernet@74000 { - status = "okay"; - phy = <&phy1>; - phy-mode = "sgmii"; - buffer-manager = <&bm>; - bm,pool-long = <1>; - }; - ethernet@30000 { - status = "okay"; - phy = <&phy2>; - phy-mode = "sgmii"; - buffer-manager = <&bm>; - bm,pool-long = <2>; - }; - ethernet@34000 { - status = "okay"; - phy = <&phy3>; - phy-mode = "sgmii"; - buffer-manager = <&bm>; - bm,pool-long = <3>; - }; - i2c@11000 { - status = "okay"; - clock-frequency = <400000>; - }; - i2c@11100 { - status = "okay"; - clock-frequency = <400000>; - - s35390a: s35390a@30 { - compatible = "s35390a"; - reg = <0x30>; - }; - }; - sata@a0000 { - nr-ports = <2>; - status = "okay"; - }; - - /* Front side USB 0 */ - usb@50000 { - status = "okay"; - }; - - /* Front side USB 1 */ - usb@51000 { - status = "okay"; - }; - - bm@c0000 { - status = "okay"; - }; - }; - - bm-bppi { - status = "okay"; - }; - }; -}; - -&pciec { - status = "okay"; - /* Internal mini-PCIe connector */ - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; -}; - -&mdio { - phy0: ethernet-phy@0 { - reg = <0>; - }; - - phy1: ethernet-phy@1 { - reg = <1>; - }; - - phy2: ethernet-phy@2 { - reg = <2>; - }; - - phy3: ethernet-phy@3 { - reg = <3>; - }; -}; - -&pinctrl { - led_pins: led-pins-0 { - marvell,pins = "mpp49", "mpp51", "mpp53"; - marvell,function = "gpio"; - }; -}; diff --git a/sys/gnu/dts/arm/armada-xp-synology-ds414.dts b/sys/gnu/dts/arm/armada-xp-synology-ds414.dts deleted file mode 100644 index 809e821d739..00000000000 --- a/sys/gnu/dts/arm/armada-xp-synology-ds414.dts +++ /dev/null @@ -1,328 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for Synology DS414 - * - * Copyright (C) 2014, Arnaud EBALARD - * - * Note: this Device Tree assumes that the bootloader has remapped the - * internal registers to 0xf1000000 (instead of the old 0xd0000000). - * The 0xf1000000 is the default used by the recent, DT-capable, U-Boot - * bootloaders provided by Marvell. It is used in recent versions of - * DSM software provided by Synology. Nonetheless, some earlier boards - * were delivered with an older version of u-boot that left internal - * registers mapped at 0xd0000000. If you have such a device you will - * not be able to directly boot a kernel based on this Device Tree. In - * that case, the preferred solution is to update your bootloader (e.g. - * by upgrading to latest version of DSM, or building a new one and - * installing it from u-boot prompt) or adjust the Devive Tree - * (s/0xf1000000/0xd0000000/ in 'ranges' below). - */ - -/dts-v1/; - -#include -#include -#include "armada-xp-mv78230.dtsi" - -/ { - model = "Synology DS414"; - compatible = "synology,ds414", "marvell,armadaxp-mv78230", - "marvell,armadaxp", "marvell,armada-370-xp"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0 0x00000000 0 0x40000000>; /* 1GB */ - }; - - soc { - ranges = ; - - internal-regs { - - /* RTC is provided by Seiko S-35390A below */ - rtc@10300 { - status = "disabled"; - }; - - i2c@11000 { - clock-frequency = <400000>; - status = "okay"; - - s35390a: s35390a@30 { - compatible = "sii,s35390a"; - reg = <0x30>; - }; - }; - - /* Connected to a header on device's PCB. This - * provides the main console for the device. - * - * Warning: the device may not boot with a 3.3V - * USB-serial converter connected when the power - * button is pressed. The converter needs to be - * connected a few seconds after pressing the - * power button. This is possibly due to UART0_TXD - * pin being sampled at reset (bit 0 of SAR). - */ - serial@12000 { - status = "okay"; - }; - - /* Connected to a Microchip PIC16F883 for power control */ - serial@12100 { - status = "okay"; - }; - - poweroff@12100 { - compatible = "synology,power-off"; - reg = <0x12100 0x100>; - clocks = <&coreclk 0>; - }; - - /* Front USB 2.0 port */ - usb@50000 { - status = "okay"; - }; - - ethernet@70000 { - status = "okay"; - pinctrl-0 = <&ge0_rgmii_pins>; - pinctrl-names = "default"; - phy = <&phy1>; - phy-mode = "rgmii-id"; - }; - - ethernet@74000 { - pinctrl-0 = <&ge1_rgmii_pins>; - pinctrl-names = "default"; - status = "okay"; - phy = <&phy0>; - phy-mode = "rgmii-id"; - }; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&sata1_pwr_pin &sata2_pwr_pin - &sata3_pwr_pin &sata4_pwr_pin>; - pinctrl-names = "default"; - - sata1_regulator: sata1-regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "SATA1 Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - startup-delay-us = <2000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>; - }; - - sata2_regulator: sata2-regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "SATA2 Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - startup-delay-us = <4000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; - }; - - sata3_regulator: sata3-regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "SATA3 Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - startup-delay-us = <6000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>; - }; - - sata4_regulator: sata4-regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "SATA4 Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - startup-delay-us = <8000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&pciec { - status = "okay"; - - /* - * Connected to Marvell 88SX7042 SATA-II controller - * handling the four disks. - */ - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - - /* - * Connected to EtronTech EJ168A XHCI controller - * providing the two rear USB 3.0 ports. - */ - pcie@5,0 { - /* Port 1, Lane 0 */ - status = "okay"; - }; -}; - - -&mdio { - phy0: ethernet-phy@0 { /* Marvell 88E1512 */ - reg = <0>; - }; - - phy1: ethernet-phy@1 { /* Marvell 88E1512 */ - reg = <1>; - }; -}; - -&pinctrl { - sata1_pwr_pin: sata1-pwr-pin { - marvell,pins = "mpp42"; - marvell,function = "gpio"; - }; - - sata2_pwr_pin: sata2-pwr-pin { - marvell,pins = "mpp44"; - marvell,function = "gpio"; - }; - - sata3_pwr_pin: sata3-pwr-pin { - marvell,pins = "mpp45"; - marvell,function = "gpio"; - }; - - sata4_pwr_pin: sata4-pwr-pin { - marvell,pins = "mpp46"; - marvell,function = "gpio"; - }; - - sata1_pres_pin: sata1-pres-pin { - marvell,pins = "mpp34"; - marvell,function = "gpio"; - }; - - sata2_pres_pin: sata2-pres-pin { - marvell,pins = "mpp35"; - marvell,function = "gpio"; - }; - - sata3_pres_pin: sata3-pres-pin { - marvell,pins = "mpp40"; - marvell,function = "gpio"; - }; - - sata4_pres_pin: sata4-pres-pin { - marvell,pins = "mpp41"; - marvell,function = "gpio"; - }; - - syno_id_bit0_pin: syno-id-bit0-pin { - marvell,pins = "mpp26"; - marvell,function = "gpio"; - }; - - syno_id_bit1_pin: syno-id-bit1-pin { - marvell,pins = "mpp28"; - marvell,function = "gpio"; - }; - - syno_id_bit2_pin: syno-id-bit2-pin { - marvell,pins = "mpp29"; - marvell,function = "gpio"; - }; - - fan1_alarm_pin: fan1-alarm-pin { - marvell,pins = "mpp33"; - marvell,function = "gpio"; - }; - - fan2_alarm_pin: fan2-alarm-pin { - marvell,pins = "mpp32"; - marvell,function = "gpio"; - }; -}; - -&spi0 { - status = "okay"; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "micron,n25q064", "jedec,spi-nor"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <20000000>; - - /* - * Warning! - * - * Synology u-boot uses its compiled-in environment - * and it seems Synology did not care to change u-boot - * default configuration in order to allow saving a - * modified environment at a sensible location. So, - * if you do a 'saveenv' under u-boot, your modified - * environment will be saved at 1MB after the start - * of the flash, i.e. in the middle of the uImage. - * For that reason, it is strongly advised not to - * change the default environment, unless you know - * what you are doing. - */ - partition@0 { /* u-boot */ - label = "RedBoot"; - reg = <0x00000000 0x000d0000>; /* 832KB */ - }; - - partition@c0000 { /* uImage */ - label = "zImage"; - reg = <0x000d0000 0x002d0000>; /* 2880KB */ - }; - - partition@3a0000 { /* uInitramfs */ - label = "rd.gz"; - reg = <0x003a0000 0x00430000>; /* 4250KB */ - }; - - partition@7d0000 { /* MAC address and serial number */ - label = "vendor"; - reg = <0x007d0000 0x00010000>; /* 64KB */ - }; - - partition@7e0000 { - label = "RedBoot config"; - reg = <0x007e0000 0x00010000>; /* 64KB */ - }; - - partition@7f0000 { - label = "FIS directory"; - reg = <0x007f0000 0x00010000>; /* 64KB */ - }; - }; -}; diff --git a/sys/gnu/dts/arm/armada-xp.dtsi b/sys/gnu/dts/arm/armada-xp.dtsi deleted file mode 100644 index 6c19984d668..00000000000 --- a/sys/gnu/dts/arm/armada-xp.dtsi +++ /dev/null @@ -1,344 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree Include file for Marvell Armada XP family SoC - * - * Copyright (C) 2012 Marvell - * - * Lior Amsalem - * Gregory CLEMENT - * Thomas Petazzoni - * Ben Dooks - * - * Contains definitions specific to the Armada XP SoC that are not - * common to all Armada SoCs. - */ - -#include "armada-370-xp.dtsi" - -/ { - #address-cells = <2>; - #size-cells = <2>; - - model = "Marvell Armada XP family SoC"; - compatible = "marvell,armadaxp", "marvell,armada-370-xp"; - - aliases { - serial2 = &uart2; - serial3 = &uart3; - }; - - soc { - compatible = "marvell,armadaxp-mbus", "simple-bus"; - - bootrom { - compatible = "marvell,bootrom"; - reg = ; - }; - - internal-regs { - sdramc: sdramc@1400 { - compatible = "marvell,armada-xp-sdram-controller"; - reg = <0x1400 0x500>; - }; - - L2: l2-cache@8000 { - compatible = "marvell,aurora-system-cache"; - reg = <0x08000 0x1000>; - cache-id-part = <0x100>; - cache-level = <2>; - cache-unified; - wt-override; - }; - - uart2: serial@12200 { - compatible = "snps,dw-apb-uart"; - pinctrl-0 = <&uart2_pins>; - pinctrl-names = "default"; - reg = <0x12200 0x100>; - reg-shift = <2>; - interrupts = <43>; - reg-io-width = <1>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - uart3: serial@12300 { - compatible = "snps,dw-apb-uart"; - pinctrl-0 = <&uart3_pins>; - pinctrl-names = "default"; - reg = <0x12300 0x100>; - reg-shift = <2>; - interrupts = <44>; - reg-io-width = <1>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - systemc: system-controller@18200 { - compatible = "marvell,armada-370-xp-system-controller"; - reg = <0x18200 0x500>; - }; - - gateclk: clock-gating-control@18220 { - compatible = "marvell,armada-xp-gating-clock"; - reg = <0x18220 0x4>; - clocks = <&coreclk 0>; - #clock-cells = <1>; - }; - - coreclk: mvebu-sar@18230 { - compatible = "marvell,armada-xp-core-clock"; - reg = <0x18230 0x08>; - #clock-cells = <1>; - }; - - thermal: thermal@182b0 { - compatible = "marvell,armadaxp-thermal"; - reg = <0x182b0 0x4 - 0x184d0 0x4>; - status = "okay"; - }; - - cpuclk: clock-complex@18700 { - #clock-cells = <1>; - compatible = "marvell,armada-xp-cpu-clock"; - reg = <0x18700 0x24>, <0x1c054 0x10>; - clocks = <&coreclk 1>; - }; - - cpu-config@21000 { - compatible = "marvell,armada-xp-cpu-config"; - reg = <0x21000 0x8>; - }; - - eth2: ethernet@30000 { - compatible = "marvell,armada-xp-neta"; - reg = <0x30000 0x4000>; - interrupts = <12>; - clocks = <&gateclk 2>; - status = "disabled"; - }; - - usb2: usb@52000 { - compatible = "marvell,orion-ehci"; - reg = <0x52000 0x500>; - interrupts = <47>; - clocks = <&gateclk 20>; - status = "disabled"; - }; - - xor1: xor@60900 { - compatible = "marvell,orion-xor"; - reg = <0x60900 0x100 - 0x60b00 0x100>; - clocks = <&gateclk 22>; - status = "okay"; - - xor10 { - interrupts = <51>; - dmacap,memcpy; - dmacap,xor; - }; - xor11 { - interrupts = <52>; - dmacap,memcpy; - dmacap,xor; - dmacap,memset; - }; - }; - - ethernet@70000 { - compatible = "marvell,armada-xp-neta"; - }; - - ethernet@74000 { - compatible = "marvell,armada-xp-neta"; - }; - - cesa: crypto@90000 { - compatible = "marvell,armada-xp-crypto"; - reg = <0x90000 0x10000>; - reg-names = "regs"; - interrupts = <48>, <49>; - clocks = <&gateclk 23>, <&gateclk 23>; - clock-names = "cesa0", "cesa1"; - marvell,crypto-srams = <&crypto_sram0>, - <&crypto_sram1>; - marvell,crypto-sram-size = <0x800>; - }; - - bm: bm@c0000 { - compatible = "marvell,armada-380-neta-bm"; - reg = <0xc0000 0xac>; - clocks = <&gateclk 13>; - internal-mem = <&bm_bppi>; - status = "disabled"; - }; - - xor0: xor@f0900 { - compatible = "marvell,orion-xor"; - reg = <0xF0900 0x100 - 0xF0B00 0x100>; - clocks = <&gateclk 28>; - status = "okay"; - - xor00 { - interrupts = <94>; - dmacap,memcpy; - dmacap,xor; - }; - xor01 { - interrupts = <95>; - dmacap,memcpy; - dmacap,xor; - dmacap,memset; - }; - }; - }; - - crypto_sram0: sa-sram0 { - compatible = "mmio-sram"; - reg = ; - clocks = <&gateclk 23>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 MBUS_ID(0x09, 0x09) 0 0x800>; - }; - - crypto_sram1: sa-sram1 { - compatible = "mmio-sram"; - reg = ; - clocks = <&gateclk 23>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 MBUS_ID(0x09, 0x05) 0 0x800>; - }; - - bm_bppi: bm-bppi { - compatible = "mmio-sram"; - reg = ; - ranges = <0 MBUS_ID(0x0c, 0x04) 0 0x100000>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&gateclk 13>; - no-memory-wc; - status = "disabled"; - }; - }; - - clocks { - /* 25 MHz reference crystal */ - refclk: oscillator { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - }; -}; - -&i2c0 { - compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c"; - reg = <0x11000 0x100>; -}; - -&i2c1 { - compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c"; - reg = <0x11100 0x100>; -}; - -&mpic { - reg = <0x20a00 0x2d0>, <0x21070 0x58>; -}; - -&timer { - compatible = "marvell,armada-xp-timer"; - clocks = <&coreclk 2>, <&refclk>; - clock-names = "nbclk", "fixed"; -}; - -&watchdog { - compatible = "marvell,armada-xp-wdt"; - clocks = <&coreclk 2>, <&refclk>; - clock-names = "nbclk", "fixed"; -}; - -&cpurst { - reg = <0x20800 0x20>; -}; - -&usb0 { - clocks = <&gateclk 18>; -}; - -&usb1 { - clocks = <&gateclk 19>; -}; - -&pinctrl { - ge0_gmii_pins: ge0-gmii-pins { - marvell,pins = - "mpp0", "mpp1", "mpp2", "mpp3", - "mpp4", "mpp5", "mpp6", "mpp7", - "mpp8", "mpp9", "mpp10", "mpp11", - "mpp12", "mpp13", "mpp14", "mpp15", - "mpp16", "mpp17", "mpp18", "mpp19", - "mpp20", "mpp21", "mpp22", "mpp23"; - marvell,function = "ge0"; - }; - - ge0_rgmii_pins: ge0-rgmii-pins { - marvell,pins = - "mpp0", "mpp1", "mpp2", "mpp3", - "mpp4", "mpp5", "mpp6", "mpp7", - "mpp8", "mpp9", "mpp10", "mpp11"; - marvell,function = "ge0"; - }; - - ge1_rgmii_pins: ge1-rgmii-pins { - marvell,pins = - "mpp12", "mpp13", "mpp14", "mpp15", - "mpp16", "mpp17", "mpp18", "mpp19", - "mpp20", "mpp21", "mpp22", "mpp23"; - marvell,function = "ge1"; - }; - - sdio_pins: sdio-pins { - marvell,pins = "mpp30", "mpp31", "mpp32", - "mpp33", "mpp34", "mpp35"; - marvell,function = "sd0"; - }; - - spi0_pins: spi0-pins { - marvell,pins = "mpp36", "mpp37", - "mpp38", "mpp39"; - marvell,function = "spi0"; - }; - - spi1_pins: spi1-pins { - marvell,pins = "mpp13", "mpp14", - "mpp16", "mpp17"; - marvell,function = "spi1"; - }; - - uart2_pins: uart2-pins { - marvell,pins = "mpp42", "mpp43"; - marvell,function = "uart2"; - }; - - uart3_pins: uart3-pins { - marvell,pins = "mpp44", "mpp45"; - marvell,function = "uart3"; - }; -}; - -&spi0 { - compatible = "marvell,armada-xp-spi", "marvell,orion-spi"; - pinctrl-0 = <&spi0_pins>; - pinctrl-names = "default"; -}; - -&spi1 { - compatible = "marvell,armada-xp-spi", "marvell,orion-spi"; - pinctrl-0 = <&spi1_pins>; - pinctrl-names = "default"; -}; diff --git a/sys/gnu/dts/arm/armv7-m.dtsi b/sys/gnu/dts/arm/armv7-m.dtsi deleted file mode 100644 index 26f5443d85e..00000000000 --- a/sys/gnu/dts/arm/armv7-m.dtsi +++ /dev/null @@ -1,23 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/ { - nvic: interrupt-controller@e000e100 { - compatible = "arm,armv7m-nvic"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0xe000e100 0xc00>; - }; - - systick: timer@e000e010 { - compatible = "arm,armv7m-systick"; - reg = <0xe000e010 0x10>; - status = "disabled"; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&nvic>; - ranges; - }; -}; diff --git a/sys/gnu/dts/arm/artpec6-devboard.dts b/sys/gnu/dts/arm/artpec6-devboard.dts deleted file mode 100644 index d20d95359b2..00000000000 --- a/sys/gnu/dts/arm/artpec6-devboard.dts +++ /dev/null @@ -1,69 +0,0 @@ -/* - * Axis ARTPEC-6 development board. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -/dts-v1/; -#include "artpec6.dtsi" - -/ { - model = "ARTPEC-6 development board"; - compatible = "axis,artpec6-dev-board", "axis,artpec6"; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - }; - - chosen { - stdout-path = "serial3:115200n8"; - }; - - memory { - device_type = "memory"; - reg = <0x0 0x40000000>; - }; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&pcie { - status = "okay"; -}; - -ðernet { - status = "okay"; - - phy-handle = <&phy1>; - phy-mode = "gmii"; - - mdio { - #address-cells = <0x1>; - #size-cells = <0x0>; - compatible = "snps,dwmac-mdio"; - phy1: phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - device_type = "ethernet-phy"; - reg = <0x0>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/artpec6.dtsi b/sys/gnu/dts/arm/artpec6.dtsi deleted file mode 100644 index 037157e6c5e..00000000000 --- a/sys/gnu/dts/arm/artpec6.dtsi +++ /dev/null @@ -1,388 +0,0 @@ -/* - * Device Tree Source for the Axis ARTPEC-6 SoC - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - compatible = "axis,artpec6"; - interrupt-parent = <&intc>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - next-level-cache = <&pl310>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <1>; - next-level-cache = <&pl310>; - }; - }; - - syscon: syscon@f8000000 { - compatible = "axis,artpec6-syscon", "syscon"; - reg = <0xf8000000 0x48>; - }; - - psci { - compatible = "arm,psci-0.2", "arm,psci"; - method = "smc"; - psci_version = <0x84000000>; - cpu_on = <0x84000003>; - system_reset = <0x84000009>; - }; - - scu@faf00000 { - compatible = "arm,cortex-a9-scu"; - reg = <0xfaf00000 0x58>; - }; - - /* Main external clock driving CPU and peripherals */ - ext_clk: ext_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <50000000>; - }; - - eth_phy_ref_clk: eth_phy_ref_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <125000000>; - }; - - clkctrl: clkctrl@f8000000 { - #clock-cells = <1>; - compatible = "axis,artpec6-clkctrl"; - reg = <0xf8000000 0x48>; - clocks = <&ext_clk>; - clock-names = "sys_refclk"; - }; - - gtimer@faf00200 { - compatible = "arm,cortex-a9-global-timer"; - reg = <0xfaf00200 0x20>; - interrupts = ; - clocks = <&clkctrl ARTPEC6_CLK_CPU_PERIPH>; - }; - - timer@faf00600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0xfaf00600 0x20>; - interrupts = ; - clocks = <&clkctrl ARTPEC6_CLK_CPU_PERIPH>; - status = "disabled"; - }; - - intc: interrupt-controller@faf01000 { - interrupt-controller; - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - reg = < 0xfaf01000 0x1000 >, < 0xfaf00100 0x0100 >; - }; - - pl310: cache-controller@faf10000 { - compatible = "arm,pl310-cache"; - cache-unified; - cache-level = <2>; - reg = <0xfaf10000 0x1000>; - interrupts = ; - arm,data-latency = <1 1 1>; - arm,tag-latency = <1 1 1>; - arm,filter-ranges = <0x0 0x80000000>; - arm,double-linefill = <1>; - arm,double-linefill-incr = <0>; - arm,double-linefill-wrap = <0>; - prefetch-data = <1>; - prefetch-instr = <1>; - arm,prefetch-offset = <0>; - arm,prefetch-drop = <1>; - }; - - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts = , - ; - interrupt-affinity = <&cpu0>, <&cpu1>; - }; - - /* - * Both pci nodes cannot be enabled at the same time, - * leave the unwanted node as disabled. - */ - pcie: pcie@f8050000 { - compatible = "axis,artpec6-pcie", "snps,dw-pcie"; - reg = <0xf8050000 0x2000 - 0xf8040000 0x1000 - 0xc0000000 0x2000>; - reg-names = "dbi", "phy", "config"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - /* downstream I/O */ - ranges = <0x81000000 0 0 0xc0002000 0 0x00010000 - /* non-prefetchable memory */ - 0x82000000 0 0xc0012000 0xc0012000 0 0x1ffee000>; - num-lanes = <2>; - bus-range = <0x00 0xff>; - interrupts = ; - interrupt-names = "msi"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &intc GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &intc GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &intc GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; - axis,syscon-pcie = <&syscon>; - status = "disabled"; - }; - - pcie_ep: pcie_ep@f8050000 { - compatible = "axis,artpec6-pcie-ep", "snps,dw-pcie"; - reg = <0xf8050000 0x2000 - 0xf8051000 0x2000 - 0xf8040000 0x1000 - 0xc0000000 0x20000000>; - reg-names = "dbi", "dbi2", "phy", "addr_space"; - num-ib-windows = <6>; - num-ob-windows = <2>; - num-lanes = <2>; - axis,syscon-pcie = <&syscon>; - status = "disabled"; - }; - - pinctrl: pinctrl@f801d000 { - compatible = "axis,artpec6-pinctrl"; - reg = <0xf801d000 0x400>; - - pinctrl_uart0: uart0grp { - function = "uart0"; - groups = "uart0grp2"; - bias-pull-up; - }; - pinctrl_uart1: uart1grp { - function = "uart1"; - groups = "uart1grp0"; - bias-pull-up; - }; - pinctrl_uart2: uart2grp { - function = "uart2"; - groups = "uart2grp1"; - bias-pull-up; - }; - pinctrl_uart3: uart3grp { - function = "uart3"; - groups = "uart3grp0"; - bias-pull-up; - }; - }; - - amba@0 { - compatible = "simple-bus"; - #address-cells = <0x1>; - #size-cells = <0x1>; - ranges; - dma-ranges; - - crypto@f4264000 { - compatible = "axis,artpec6-crypto"; - reg = <0xf4264000 0x4000>; - interrupts = ; - }; - - dma0: dma@f8019000 { - compatible = "renesas,nbpfaxi64dmac8b16"; - reg = <0xf8019000 0x400>; - interrupts = , /* error */ - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch12", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&clkctrl ARTPEC6_CLK_DMA_ACLK>; - #dma-cells = <2>; - dma-channels = <8>; - dma-requests = <8>; - }; - dma1: dma@f8019400 { - compatible = "renesas,nbpfaxi64dmac8b16"; - reg = <0xf8019400 0x400>; - interrupts = , /* error */ - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch12", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&clkctrl ARTPEC6_CLK_DMA_ACLK>; - #dma-cells = <2>; - dma-channels = <8>; - dma-requests = <8>; - }; - - ethernet: ethernet@f8010000 { - clock-names = "stmmaceth", "ptp_ref"; - clocks = <&clkctrl ARTPEC6_CLK_ETH_ACLK>, - <&clkctrl ARTPEC6_CLK_PTP_REF>; - compatible = "snps,dwmac-4.10a", "snps,dwmac"; - interrupts = , - ; - interrupt-names = "macirq", "eth_lpi"; - reg = <0xf8010000 0x4000>; - - snps,axi-config = <&stmmac_axi_setup>; - snps,mtl-rx-config = <&mtl_rx_setup>; - snps,mtl-tx-config = <&mtl_tx_setup>; - - snps,txpbl = <8>; - snps,rxpbl = <2>; - snps,aal; - snps,tso; - - status = "disabled"; - - stmmac_axi_setup: stmmac-axi-config { - snps,wr_osr_lmt = <1>; - snps,rd_osr_lmt = <15>; - /* If FB is disabled, the AXI master chooses - * a burst length of any value less than the - * maximum enabled burst length - * (all lesser burst length enables are redundant). - */ - snps,blen = <0 0 0 0 16 0 0>; - }; - - mtl_rx_setup: rx-queues-config { - snps,rx-queues-to-use = <1>; - queue0 {}; - }; - - mtl_tx_setup: tx-queues-config { - snps,tx-queues-to-use = <2>; - queue0 {}; - queue1 {}; - }; - }; - - uart0: serial@f8036000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0xf8036000 0x1000>; - interrupts = ; - clocks = <&clkctrl ARTPEC6_CLK_UART_REFCLK>, - <&clkctrl ARTPEC6_CLK_UART_PCLK>; - clock-names = "uart_clk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0>; - dmas = <&dma0 4 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)>, - <&dma0 5 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - uart1: serial@f8037000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0xf8037000 0x1000>; - interrupts = ; - clocks = <&clkctrl ARTPEC6_CLK_UART_REFCLK>, - <&clkctrl ARTPEC6_CLK_UART_PCLK>; - clock-names = "uart_clk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - dmas = <&dma0 6 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)>, - <&dma0 7 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - uart2: serial@f8038000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0xf8038000 0x1000>; - interrupts = ; - clocks = <&clkctrl ARTPEC6_CLK_UART_REFCLK>, - <&clkctrl ARTPEC6_CLK_UART_PCLK>; - clock-names = "uart_clk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - dmas = <&dma1 0 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)>, - <&dma1 1 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - uart3: serial@f8039000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0xf8039000 0x1000>; - interrupts = ; - clocks = <&clkctrl ARTPEC6_CLK_UART_REFCLK>, - <&clkctrl ARTPEC6_CLK_UART_PCLK>; - clock-names = "uart_clk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - dmas = <&dma1 2 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)>, - <&dma1 3 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - }; -}; diff --git a/sys/gnu/dts/arm/aspeed-ast2500-evb.dts b/sys/gnu/dts/arm/aspeed-ast2500-evb.dts deleted file mode 100644 index 8bec21ed0de..00000000000 --- a/sys/gnu/dts/arm/aspeed-ast2500-evb.dts +++ /dev/null @@ -1,131 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/dts-v1/; - -#include "aspeed-g5.dtsi" - -/ { - model = "AST2500 EVB"; - compatible = "aspeed,ast2500"; - - aliases { - serial4 = &uart5; - }; - - chosen { - stdout-path = &uart5; - bootargs = "console=tty0 console=ttyS4,115200 earlyprintk"; - }; - - memory@80000000 { - reg = <0x80000000 0x20000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gfx_memory: framebuffer { - size = <0x01000000>; - alignment = <0x01000000>; - compatible = "shared-dma-pool"; - reusable; - }; - }; -}; - -&fmc { - status = "okay"; - flash@0 { - status = "okay"; - m25p,fast-read; - label = "bmc"; - spi-max-frequency = <50000000>; -#include "openbmc-flash-layout.dtsi" - }; -}; - -&spi1 { - status = "okay"; - flash@0 { - status = "okay"; - m25p,fast-read; - label = "pnor"; - spi-max-frequency = <100000000>; - }; -}; - -&spi2 { - status = "okay"; -}; - -&uart5 { - status = "okay"; -}; - -&mac0 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rgmii1_default &pinctrl_mdio1_default>; -}; - -&mac1 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; -}; - -&i2c3 { - status = "okay"; - - eeprom@50 { - compatible = "atmel,24c08"; - reg = <0x50>; - pagesize = <16>; - }; -}; - -&i2c7 { - status = "okay"; - - lm75@4d { - compatible = "national,lm75"; - reg = <0x4d>; - }; -}; - -&sdmmc { - status = "okay"; -}; - -&sdhci0 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sd1_default>; -}; - -/* - * Enable port A as device (via the virtual hub) and port B as - * host by default on the eval board. This can be easily changed - * by replacing the override below with &ehci0 { ... } to enable - * host on both ports. - */ -&vhub { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&uhci { - status = "okay"; -}; - -&gfx { - status = "okay"; - memory-region = <&gfx_memory>; -}; diff --git a/sys/gnu/dts/arm/aspeed-ast2600-evb.dts b/sys/gnu/dts/arm/aspeed-ast2600-evb.dts deleted file mode 100644 index 4afa8662c4e..00000000000 --- a/sys/gnu/dts/arm/aspeed-ast2600-evb.dts +++ /dev/null @@ -1,215 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -// Copyright 2019 IBM Corp. - -/dts-v1/; - -#include "aspeed-g6.dtsi" - -/ { - model = "AST2600 EVB"; - compatible = "aspeed,ast2600"; - - aliases { - serial4 = &uart5; - }; - - chosen { - bootargs = "console=ttyS4,115200n8"; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x80000000>; - }; -}; - -&mdio1 { - status = "okay"; - - ethphy1: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - }; -}; - -&mdio2 { - status = "okay"; - - ethphy2: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - }; -}; - -&mdio3 { - status = "okay"; - - ethphy3: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - }; -}; - -&mac1 { - status = "okay"; - - phy-mode = "rgmii"; - phy-handle = <ðphy1>; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rgmii2_default>; -}; - -&mac2 { - status = "okay"; - - phy-mode = "rgmii"; - phy-handle = <ðphy2>; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rgmii3_default>; -}; - -&mac3 { - status = "okay"; - - phy-mode = "rgmii"; - phy-handle = <ðphy3>; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rgmii4_default>; -}; - -&emmc_controller { - status = "okay"; -}; - -&emmc { - non-removable; - bus-width = <4>; - max-frequency = <52000000>; -}; - -&rtc { - status = "okay"; -}; - -&fmc { - status = "okay"; - flash@0 { - status = "okay"; - m25p,fast-read; - label = "bmc"; - spi-max-frequency = <50000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - u-boot@0 { - reg = <0x0 0xe0000>; // 896KB - label = "u-boot"; - }; - - u-boot-env@e0000 { - reg = <0xe0000 0x20000>; // 128KB - label = "u-boot-env"; - }; - - kernel@100000 { - reg = <0x100000 0x900000>; // 9MB - label = "kernel"; - }; - - rofs@a00000 { - reg = <0xa00000 0x2000000>; // 32MB - label = "rofs"; - }; - - rwfs@6000000 { - reg = <0x2a00000 0x1600000>; // 22MB - label = "rwfs"; - }; - }; - }; -}; - -&spi1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1_default>; - - flash@0 { - status = "okay"; - m25p,fast-read; - label = "pnor"; - spi-max-frequency = <100000000>; - }; -}; - -&uart5 { - // Workaround for A0 - compatible = "snps,dw-apb-uart"; -}; - -&i2c0 { - status = "okay"; - - temp@2e { - compatible = "adi,adt7490"; - reg = <0x2e>; - }; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c3 { - status = "okay"; -}; - -&i2c4 { - status = "okay"; -}; - -&i2c5 { - status = "okay"; -}; - -&i2c6 { - status = "okay"; -}; - -&i2c7 { - status = "okay"; -}; - -&i2c8 { - status = "okay"; -}; - -&i2c9 { - status = "okay"; -}; - -&i2c12 { - status = "okay"; -}; - -&i2c13 { - status = "okay"; -}; - -&i2c14 { - status = "okay"; -}; - -&i2c15 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/aspeed-bmc-arm-centriq2400-rep.dts b/sys/gnu/dts/arm/aspeed-bmc-arm-centriq2400-rep.dts deleted file mode 100644 index c2ece0b9188..00000000000 --- a/sys/gnu/dts/arm/aspeed-bmc-arm-centriq2400-rep.dts +++ /dev/null @@ -1,225 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/dts-v1/; - -#include "aspeed-g5.dtsi" -#include - -/ { - model = "Qualcomm Centriq 2400 REP AST2520"; - compatible = "qualcomm,centriq2400-rep-bmc", "aspeed,ast2500"; - - chosen { - stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlyprintk"; - }; - - memory@80000000 { - reg = <0x80000000 0x40000000>; - }; - - iio-hwmon { - compatible = "iio-hwmon"; - io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, - <&adc 4>, <&adc 5>, <&adc 6>, <&adc 8>; - }; - - iio-hwmon-battery { - compatible = "iio-hwmon"; - io-channels = <&adc 7>; - }; - - leds { - compatible = "gpio-leds"; - - uid_led { - label = "UID_LED"; - gpios = <&gpio ASPEED_GPIO(Q, 5) GPIO_ACTIVE_LOW>; - }; - - ras_error_led { - label = "RAS_ERROR_LED"; - gpios = <&gpio ASPEED_GPIO(F, 6) GPIO_ACTIVE_LOW>; - }; - - system_fault { - label = "System_fault"; - gpios = <&gpio ASPEED_GPIO(A, 1) GPIO_ACTIVE_LOW>; - }; - }; -}; - -&fmc { - status = "okay"; - flash@0 { - status = "okay"; - m25p,fast-read; - label = "bmc"; -#include "openbmc-flash-layout.dtsi" - }; -}; - -&spi1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1_default>; - flash@0 { - status = "okay"; - }; -}; - -&spi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi2ck_default - &pinctrl_spi2miso_default - &pinctrl_spi2mosi_default - &pinctrl_spi2cs0_default>; -}; - -&uart3 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd3_default &pinctrl_rxd3_default>; - current-speed = <115200>; -}; - -&uart5 { - status = "okay"; -}; - -&mac0 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rgmii1_default &pinctrl_mdio1_default>; -}; - -&i2c0 { - status = "okay"; -}; - -&i2c1 { - status = "okay"; - - tmp421@1e { - compatible = "ti,tmp421"; - reg = <0x1e>; - }; - tmp421@2a { - compatible = "ti,tmp421"; - reg = <0x2a>; - }; - tmp421@4e { - compatible = "ti,tmp421"; - reg = <0x4e>; - }; - tmp421@1c { - compatible = "ti,tmp421"; - reg = <0x1c>; - }; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c3 { - status = "okay"; -}; - -&i2c4 { - status = "okay"; -}; - -&i2c5 { - status = "okay"; -}; - -&i2c6 { - status = "okay"; - - tmp421@1d { - compatible = "ti,tmp421"; - reg = <0x1d>; - }; - tmp421@1f { - compatible = "ti,tmp421"; - reg = <0x1f>; - }; - tmp421@4d { - compatible = "ti,tmp421"; - reg = <0x4d>; - }; - tmp421@4f { - compatible = "ti,tmp421"; - reg = <0x4f>; - }; - nvt210@4c { - compatible = "nvt210"; - reg = <0x4c>; - }; - eeprom@50 { - compatible = "atmel,24c128"; - reg = <0x50>; - pagesize = <128>; - }; -}; - -&i2c7 { - status = "okay"; -}; - -&i2c8 { - status = "okay"; - - pca9641@70 { - compatible = "nxp,pca9641"; - reg = <0x70>; - i2c-arb { - #address-cells = <1>; - #size-cells = <0>; - tmp421@1d { - compatible = "tmp421"; - reg = <0x1d>; - }; - adm1278@12 { - compatible = "adi,adm1278"; - reg = <0x12>; - Rsense = <500>; - }; - eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - }; - ds1100@58 { - compatible = "ds1100"; - reg = <0x58>; - }; - }; - }; -}; - -&i2c9 { - status = "okay"; -}; - -&vuart { - status = "okay"; -}; - -&gfx { - status = "okay"; -}; - -&pinctrl { - aspeed,external-nodes = <&gfx &lhc>; -}; - -&gpio { - pin_gpio_c7 { - gpio-hog; - gpios = ; - output; - line-name = "BIOS_SPI_MUX_S"; - }; -}; diff --git a/sys/gnu/dts/arm/aspeed-bmc-arm-stardragon4800-rep2.dts b/sys/gnu/dts/arm/aspeed-bmc-arm-stardragon4800-rep2.dts deleted file mode 100644 index 2c29ac037d3..00000000000 --- a/sys/gnu/dts/arm/aspeed-bmc-arm-stardragon4800-rep2.dts +++ /dev/null @@ -1,220 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/dts-v1/; - -#include "aspeed-g5.dtsi" -#include - -/ { - model = "HXT StarDragon 4800 REP2 AST2520"; - compatible = "hxt,stardragon4800-rep2-bmc", "aspeed,ast2500"; - - chosen { - stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlyprintk"; - }; - - memory@80000000 { - reg = <0x80000000 0x40000000>; - }; - - iio-hwmon { - compatible = "iio-hwmon"; - io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, - <&adc 4>, <&adc 5>, <&adc 6>, <&adc 8>; - }; - - iio-hwmon-battery { - compatible = "iio-hwmon"; - io-channels = <&adc 7>; - }; - - leds { - compatible = "gpio-leds"; - - system_fault1 { - label = "System_fault1"; - gpios = <&gpio ASPEED_GPIO(I, 3) GPIO_ACTIVE_LOW>; - }; - - system_fault2 { - label = "System_fault2"; - gpios = <&gpio ASPEED_GPIO(I, 2) GPIO_ACTIVE_LOW>; - }; - }; -}; - -&fmc { - status = "okay"; - flash@0 { - status = "okay"; - m25p,fast-read; - label = "bmc"; -#include "openbmc-flash-layout.dtsi" - }; -}; - -&spi1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1_default>; - flash@0 { - status = "okay"; - }; -}; - -&spi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi2ck_default - &pinctrl_spi2miso_default - &pinctrl_spi2mosi_default - &pinctrl_spi2cs0_default>; -}; - -&uart3 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd3_default &pinctrl_rxd3_default>; - current-speed = <115200>; -}; - -&uart5 { - status = "okay"; -}; - -&mac0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rgmii1_default &pinctrl_mdio1_default>; -}; - -&mac1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rmii2_default>; - clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>, - <&syscon ASPEED_CLK_MAC2RCLK>; - clock-names = "MACCLK", "RCLK"; - use-ncsi; -}; - -&i2c0 { - status = "okay"; -}; - -&i2c1 { - status = "okay"; - - tmp421@1e { - compatible = "ti,tmp421"; - reg = <0x1e>; - }; - tmp421@2a { - compatible = "ti,tmp421"; - reg = <0x2a>; - }; - tmp421@1c { - compatible = "ti,tmp421"; - reg = <0x1c>; - }; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c3 { - status = "okay"; -}; - -&i2c4 { - status = "okay"; -}; - -&i2c5 { - status = "okay"; -}; - -&i2c6 { - status = "okay"; - - tmp421@1f { - compatible = "ti,tmp421"; - reg = <0x1f>; - }; - nvt210@4c { - compatible = "nvt210"; - reg = <0x4c>; - }; - eeprom@50 { - compatible = "atmel,24c128"; - reg = <0x50>; - pagesize = <128>; - }; -}; - -&i2c7 { - status = "okay"; -}; - -&i2c8 { - status = "okay"; - - pca9641@70 { - compatible = "nxp,pca9641"; - reg = <0x70>; - i2c-arb { - #address-cells = <1>; - #size-cells = <0>; - eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - }; - dps650ab@58 { - compatible = "dps650ab"; - reg = <0x58>; - }; - }; - }; - - dps650ab@58 { - compatible = "delta,dps650ab"; - reg = <0x58>; - }; - - dps650ab@59 { - compatible = "delta,dps650ab"; - reg = <0x59>; - }; -}; - -&i2c9 { - status = "okay"; -}; - -&vuart { - status = "okay"; -}; - -&gfx { - status = "okay"; -}; - -&pinctrl { - aspeed,external-nodes = <&gfx &lhc>; -}; - -&gpio { - pin_gpio_c7 { - gpio-hog; - gpios = ; - output-low; - line-name = "BIOS_SPI_MUX_S"; - }; - pin_gpio_d1 { - gpio-hog; - gpios = ; - output-high; - line-name = "PHY2_RESET_N"; - }; -}; diff --git a/sys/gnu/dts/arm/aspeed-bmc-facebook-cmm.dts b/sys/gnu/dts/arm/aspeed-bmc-facebook-cmm.dts deleted file mode 100644 index 016bbcb99bb..00000000000 --- a/sys/gnu/dts/arm/aspeed-bmc-facebook-cmm.dts +++ /dev/null @@ -1,348 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// Copyright (c) 2018 Facebook Inc. -/dts-v1/; - -#include "ast2500-facebook-netbmc-common.dtsi" - -/ { - model = "Facebook Backpack CMM BMC"; - compatible = "facebook,cmm-bmc", "aspeed,ast2500"; - - aliases { - /* - * Override the default uart aliases to avoid breaking - * the legacy applications. - */ - serial0 = &uart5; - serial1 = &uart1; - serial2 = &uart3; - serial3 = &uart4; - - /* - * Hardcode the bus number of i2c switches' channels to - * avoid breaking the legacy applications. - */ - i2c16 = &imux16; - i2c17 = &imux17; - i2c18 = &imux18; - i2c19 = &imux19; - i2c20 = &imux20; - i2c21 = &imux21; - i2c22 = &imux22; - i2c23 = &imux23; - i2c24 = &imux24; - i2c25 = &imux25; - i2c26 = &imux26; - i2c27 = &imux27; - i2c28 = &imux28; - i2c29 = &imux29; - i2c30 = &imux30; - i2c31 = &imux31; - i2c32 = &imux32; - i2c33 = &imux33; - i2c34 = &imux34; - i2c35 = &imux35; - i2c36 = &imux36; - i2c37 = &imux37; - i2c38 = &imux38; - i2c39 = &imux39; - }; - - chosen { - stdout-path = &uart1; - bootargs = "console=ttyS1,9600n8 root=/dev/ram rw earlyprintk"; - }; - - ast-adc-hwmon { - compatible = "iio-hwmon"; - io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, - <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>; - }; -}; - -&uart1 { - pinctrl-0 = <&pinctrl_txd1_default - &pinctrl_rxd1_default - &pinctrl_ncts1_default - &pinctrl_ndcd1_default - &pinctrl_ndsr1_default - &pinctrl_ndtr1_default - &pinctrl_nrts1_default>; -}; - -&uart3 { - pinctrl-0 = <&pinctrl_txd3_default - &pinctrl_rxd3_default - &pinctrl_ncts3_default - &pinctrl_ndcd3_default - &pinctrl_nri3_default>; -}; - -&uart4 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd4_default - &pinctrl_rxd4_default>; -}; - -/* - * I2C bus reserved for communication with COM-E. - */ -&i2c0 { - status = "okay"; -}; - -/* - * I2C bus to Line Cards and Fabric Cards. - */ -&i2c1 { - status = "okay"; - - i2c-switch@77 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x77>; - - imux16: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - imux17: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - imux18: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - imux19: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - - imux20: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - - imux21: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - - imux22: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - }; - - imux23: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - }; -}; - -/* - * I2C bus to Power Distribution Board. - */ -&i2c2 { - status = "okay"; - - i2c-switch@71 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x71>; - - imux24: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - imux25: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - imux26: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - imux27: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - - imux28: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - - imux29: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - - imux30: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - }; - - imux31: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - }; -}; - -/* - * I2c bus connected with temperature sensors on CMM. - */ -&i2c3 { - status = "okay"; -}; - -/* - * I2C bus reserved for communication with COM-E. - */ -&i2c4 { - status = "okay"; -}; - -/* - * I2c bus connected with ADM1278. - */ -&i2c5 { - status = "okay"; -}; - -/* - * I2c bus connected with I/O Expander. - */ -&i2c6 { - status = "okay"; -}; - -/* - * I2c bus connected with I/O Expander and EPROMs. - */ -&i2c7 { - status = "okay"; -}; - -/* - * I2C bus to Fan Control Board. - */ -&i2c8 { - status = "okay"; - - i2c-switch@77 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x77>; - - imux32: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - imux33: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - imux34: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - imux35: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - - imux36: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - - imux37: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - - imux38: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - }; - - imux39: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - }; -}; - -/* - * I2C bus to CMM CPLD. - */ -&i2c13 { - status = "okay"; -}; - -&adc { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&vhub { - status = "disabled"; -}; - -&sdhci0 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sd1_default>; -}; - -&sdhci1 { - status = "disabled"; -}; diff --git a/sys/gnu/dts/arm/aspeed-bmc-facebook-minipack.dts b/sys/gnu/dts/arm/aspeed-bmc-facebook-minipack.dts deleted file mode 100644 index 88ce4ff9f47..00000000000 --- a/sys/gnu/dts/arm/aspeed-bmc-facebook-minipack.dts +++ /dev/null @@ -1,408 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// Copyright (c) 2018 Facebook Inc. -/dts-v1/; - -#include "ast2500-facebook-netbmc-common.dtsi" - -/ { - model = "Facebook Minipack 100 BMC"; - compatible = "facebook,minipack-bmc", "aspeed,ast2500"; - - aliases { - /* - * Override the default serial aliases to avoid breaking - * the legacy applications. - */ - serial0 = &uart5; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - serial4 = &uart4; - - /* - * i2c switch 2-0070, pca9548, 8 child channels assigned - * with bus number 16-23. - */ - i2c16 = &imux16; - i2c17 = &imux17; - i2c18 = &imux18; - i2c19 = &imux19; - i2c20 = &imux20; - i2c21 = &imux21; - i2c22 = &imux22; - i2c23 = &imux23; - - /* - * i2c switch 8-0070, pca9548, 8 child channels assigned - * with bus number 24-31. - */ - i2c24 = &imux24; - i2c25 = &imux25; - i2c26 = &imux26; - i2c27 = &imux27; - i2c28 = &imux28; - i2c29 = &imux29; - i2c30 = &imux30; - i2c31 = &imux31; - - /* - * i2c switch 9-0070, pca9548, 8 child channels assigned - * with bus number 32-39. - */ - i2c32 = &imux32; - i2c33 = &imux33; - i2c34 = &imux34; - i2c35 = &imux35; - i2c36 = &imux36; - i2c37 = &imux37; - i2c38 = &imux38; - i2c39 = &imux39; - - /* - * i2c switch 11-0070, pca9548, 8 child channels assigned - * with bus number 40-47. - */ - i2c40 = &imux40; - i2c41 = &imux41; - i2c42 = &imux42; - i2c43 = &imux43; - i2c44 = &imux44; - i2c45 = &imux45; - i2c46 = &imux46; - i2c47 = &imux47; - }; - - chosen { - stdout-path = &uart1; - bootargs = "debug console=ttyS1,9600n8 root=/dev/ram rw"; - }; -}; - -&wdt2 { - status = "okay"; - aspeed,reset-type = "system"; -}; - -/* - * Both firmware flashes are 64MB on Minipack BMC. - */ -&fmc_flash0 { - partitions { - data0@1c00000 { - reg = <0x1c00000 0x2400000>; - }; - flash0@0 { - reg = <0x0 0x4000000>; - }; - }; -}; - -&fmc_flash1 { - partitions { - flash1@0 { - reg = <0x0 0x4000000>; - }; - }; -}; - -&uart1 { - pinctrl-0 = <&pinctrl_txd1_default - &pinctrl_rxd1_default - &pinctrl_ncts1_default - &pinctrl_ndsr1_default - &pinctrl_ndtr1_default - &pinctrl_nrts1_default>; -}; - -&uart2 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd2_default - &pinctrl_rxd2_default>; -}; - -&uart4 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd4_default - &pinctrl_rxd4_default>; -}; - -&i2c0 { - status = "okay"; - bus-frequency = <400000>; - multi-master; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; - - i2c-switch@70 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x70>; - - imux16: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - imux17: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - imux18: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - imux19: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - - imux20: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - - imux21: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - - imux22: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - }; - - imux23: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - }; -}; - -&i2c3 { - status = "okay"; -}; - -&i2c4 { - status = "okay"; - multi-master; -}; - -&i2c5 { - status = "okay"; -}; - -&i2c6 { - status = "okay"; -}; - -&i2c7 { - status = "okay"; -}; - -&i2c8 { - status = "okay"; - - i2c-switch@70 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x70>; - - imux24: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - imux25: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - imux26: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - imux27: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - - imux28: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - - imux29: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - - imux30: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - }; - - imux31: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - }; -}; - -&i2c9 { - status = "okay"; - - i2c-switch@70 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x70>; - - imux32: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - imux33: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - imux34: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - imux35: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - - imux36: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - - imux37: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - - imux38: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - }; - - imux39: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - }; -}; - -&i2c10 { - status = "okay"; -}; - -&i2c11 { - status = "okay"; - - i2c-switch@70 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x70>; - - imux40: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - imux41: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - imux42: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - imux43: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - - imux44: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - - imux45: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - - imux46: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - }; - - imux47: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - }; -}; - -&i2c12 { - status = "okay"; -}; - -&i2c13 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/aspeed-bmc-facebook-tiogapass.dts b/sys/gnu/dts/arm/aspeed-bmc-facebook-tiogapass.dts deleted file mode 100644 index 5d7cbd9164d..00000000000 --- a/sys/gnu/dts/arm/aspeed-bmc-facebook-tiogapass.dts +++ /dev/null @@ -1,467 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// Copyright (c) 2018 Facebook Inc. -// Author: Vijay Khemka -/dts-v1/; - -#include "aspeed-g5.dtsi" -#include - -/ { - model = "Facebook TiogaPass BMC"; - compatible = "facebook,tiogapass-bmc", "aspeed,ast2500"; - aliases { - serial0 = &uart1; - serial4 = &uart5; - - /* - * Hardcode the bus number of i2c switches' channels to - * avoid breaking the legacy applications. - */ - i2c16 = &imux16; - i2c17 = &imux17; - i2c18 = &imux18; - i2c19 = &imux19; - i2c20 = &imux20; - i2c21 = &imux21; - i2c22 = &imux22; - i2c23 = &imux23; - i2c24 = &imux24; - i2c25 = &imux25; - i2c26 = &imux26; - i2c27 = &imux27; - i2c28 = &imux28; - i2c29 = &imux29; - i2c30 = &imux30; - i2c31 = &imux31; - }; - chosen { - stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlyprintk"; - }; - - memory@80000000 { - reg = <0x80000000 0x20000000>; - }; - - iio-hwmon { - compatible = "iio-hwmon"; - io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, - <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>; - }; - -}; - -&fmc { - status = "okay"; - flash@0 { - status = "okay"; - m25p,fast-read; -#include "openbmc-flash-layout.dtsi" - }; -}; - -&spi1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1_default>; - flash@0 { - status = "okay"; - m25p,fast-read; - label = "pnor"; - }; -}; - -&lpc_snoop { - status = "okay"; - snoop-ports = <0x80>; -}; - -&lpc_ctrl { - // Enable lpc clock - status = "okay"; -}; - -&vuart { - // VUART Host Console - status = "okay"; -}; - -&uart1 { - // Host Console - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd1_default - &pinctrl_rxd1_default>; -}; - -&uart2 { - // SoL Host Console - status = "okay"; -}; - -&uart3 { - // SoL BMC Console - status = "okay"; -}; - -&uart5 { - // BMC Console - status = "okay"; -}; - -&kcs2 { - // BMC KCS channel 2 - status = "okay"; - kcs_addr = <0xca8>; -}; - -&kcs3 { - // BMC KCS channel 3 - status = "okay"; - kcs_addr = <0xca2>; -}; - -&mac0 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rmii1_default>; - clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, - <&syscon ASPEED_CLK_MAC1RCLK>; - clock-names = "MACCLK", "RCLK"; - use-ncsi; -}; - -&adc { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - //Airmax Conn B, CPU0 PIROM, CPU1 PIROM -}; - -&i2c1 { - status = "okay"; - //X24 Riser - i2c-switch@71 { - compatible = "nxp,pca9544"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x71>; - - imux16: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - ina230@45 { - compatible = "ti,ina230"; - reg = <0x45>; - }; - - tmp75@48 { - compatible = "ti,tmp75"; - reg = <0x48>; - }; - - tmp421@49 { - compatible = "ti,tmp75"; - reg = <0x49>; - }; - - eeprom@50 { - compatible = "atmel,24c64"; - reg = <0x50>; - pagesize = <32>; - }; - - i2c-switch@73 { - compatible = "nxp,pca9546"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x73>; - - imux20: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - imux21: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - imux22: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - imux23: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - - }; - - }; - - imux17: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - ina230@45 { - compatible = "ti,ina230"; - reg = <0x45>; - }; - - tmp421@48 { - compatible = "ti,tmp75"; - reg = <0x48>; - }; - - tmp421@49 { - compatible = "ti,tmp75"; - reg = <0x49>; - }; - - eeprom@50 { - compatible = "atmel,24c64"; - reg = <0x50>; - pagesize = <32>; - }; - - i2c-switch@73 { - compatible = "nxp,pca9546"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x73>; - - imux24: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - imux25: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - imux26: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - imux27: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - - }; - - }; - - imux18: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - - ina230@45 { - compatible = "ti,ina230"; - reg = <0x45>; - }; - - tmp421@48 { - compatible = "ti,tmp75"; - reg = <0x48>; - }; - - tmp421@49 { - compatible = "ti,tmp75"; - reg = <0x49>; - }; - - eeprom@50 { - compatible = "atmel,24c64"; - reg = <0x50>; - pagesize = <32>; - }; - - i2c-switch@73 { - compatible = "nxp,pca9546"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x73>; - - imux28: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - imux29: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - imux30: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - imux31: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - - }; - - }; - - imux19: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - - i2c-switch@40 { - compatible = "ti,ina230"; - reg = <0x40>; - }; - - i2c-switch@41 { - compatible = "ti,ina230"; - reg = <0x41>; - }; - - i2c-switch@45 { - compatible = "ti,ina230"; - reg = <0x45>; - }; - - }; - - }; -}; - -&i2c2 { - status = "okay"; - // Mezz Management SMBus -}; - -&i2c3 { - status = "okay"; - // SMBus to Board ID EEPROM -}; - -&i2c4 { - status = "okay"; - // BMC Debug Header -}; - -&i2c5 { - status = "okay"; - // CPU Voltage regulators - regulator@48 { - compatible = "infineon,pxe1610"; - reg = <0x48>; - }; - regulator@4a { - compatible = "infineon,pxe1610"; - reg = <0x4a>; - }; - regulator@50 { - compatible = "infineon,pxe1610"; - reg = <0x50>; - }; - regulator@52 { - compatible = "infineon,pxe1610"; - reg = <0x52>; - }; - regulator@58 { - compatible = "infineon,pxe1610"; - reg = <0x58>; - }; - regulator@5a { - compatible = "infineon,pxe1610"; - reg = <0x5a>; - }; - regulator@68 { - compatible = "infineon,pxe1610"; - reg = <0x68>; - }; - regulator@70 { - compatible = "infineon,pxe1610"; - reg = <0x70>; - }; - regulator@72 { - compatible = "infineon,pxe1610"; - reg = <0x72>; - }; -}; - -&i2c6 { - status = "okay"; - tpm@20 { - compatible = "infineon,slb9645tt"; - reg = <0x20>; - }; - tmp421@4e { - compatible = "ti,tmp421"; - reg = <0x4e>; - }; - tmp421@4f { - compatible = "ti,tmp421"; - reg = <0x4f>; - }; - eeprom@54 { - compatible = "atmel,24c64"; - reg = <0x54>; - pagesize = <32>; - }; -}; - -&i2c7 { - status = "okay"; - //HSC, AirMax Conn A -}; - -&i2c8 { - status = "okay"; - tmp421@1f { - compatible = "ti,tmp421"; - reg = <0x1f>; - }; - //Mezz Sensor SMBus -}; - -&i2c9 { - status = "okay"; - //USB Debug Connector -}; - -&pwm_tacho { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default>; - fan@0 { - reg = <0x00>; - aspeed,fan-tach-ch = /bits/ 8 <0x00>; - }; - - fan@1 { - reg = <0x01>; - aspeed,fan-tach-ch = /bits/ 8 <0x02>; - }; -}; diff --git a/sys/gnu/dts/arm/aspeed-bmc-facebook-wedge100.dts b/sys/gnu/dts/arm/aspeed-bmc-facebook-wedge100.dts deleted file mode 100644 index 322587b7b67..00000000000 --- a/sys/gnu/dts/arm/aspeed-bmc-facebook-wedge100.dts +++ /dev/null @@ -1,148 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// Copyright (c) 2018 Facebook Inc. -/dts-v1/; - -#include "aspeed-g4.dtsi" - -/ { - model = "Facebook Wedge 100 BMC"; - compatible = "facebook,wedge100-bmc", "aspeed,ast2400"; - - aliases { - /* - * Override the default uart aliases to avoid breaking - * the legacy applications. - */ - serial0 = &uart5; - serial1 = &uart1; - serial2 = &uart3; - serial3 = &uart4; - }; - - chosen { - stdout-path = &uart3; - bootargs = "console=ttyS2,9600n8 root=/dev/ram rw"; - }; - - memory@40000000 { - reg = <0x40000000 0x20000000>; - }; -}; - -&wdt1 { - status = "okay"; - aspeed,reset-type = "system"; -}; - -&wdt2 { - status = "okay"; - aspeed,reset-type = "system"; -}; - -&fmc { - status = "okay"; - flash@0 { - status = "okay"; - m25p,fast-read; - label = "fmc0"; -#include "facebook-bmc-flash-layout.dtsi" - }; -}; - -&uart1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd1_default - &pinctrl_rxd1_default>; -}; - -&uart3 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd3_default - &pinctrl_rxd3_default>; -}; - -&uart4 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd4_default - &pinctrl_rxd4_default>; -}; - -&uart5 { - status = "okay"; -}; - -&mac1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; -}; - -&i2c0 { - status = "okay"; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c3 { - status = "okay"; -}; - -&i2c4 { - status = "okay"; -}; - -&i2c5 { - status = "okay"; -}; - -&i2c6 { - status = "okay"; -}; - -&i2c7 { - status = "okay"; - - i2c-switch@70 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x70>; - }; -}; - -&i2c8 { - status = "okay"; -}; - -&i2c9 { - status = "okay"; -}; - -&i2c10 { - status = "okay"; -}; - -&i2c11 { - status = "okay"; -}; - -&i2c12 { - status = "okay"; -}; - -&i2c13 { - status = "okay"; -}; - -&vhub { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/aspeed-bmc-facebook-wedge40.dts b/sys/gnu/dts/arm/aspeed-bmc-facebook-wedge40.dts deleted file mode 100644 index 54e508530dc..00000000000 --- a/sys/gnu/dts/arm/aspeed-bmc-facebook-wedge40.dts +++ /dev/null @@ -1,140 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// Copyright (c) 2018 Facebook Inc. -/dts-v1/; - -#include "aspeed-g4.dtsi" - -/ { - model = "Facebook Wedge 40 BMC"; - compatible = "facebook,wedge40-bmc", "aspeed,ast2400"; - - aliases { - /* - * Override the default uart aliases to avoid breaking - * the legacy applications. - */ - serial0 = &uart5; - serial1 = &uart1; - serial2 = &uart3; - serial3 = &uart4; - }; - - chosen { - stdout-path = &uart3; - bootargs = "console=ttyS2,9600n8 root=/dev/ram rw"; - }; - - memory@40000000 { - reg = <0x40000000 0x20000000>; - }; -}; - -&wdt1 { - status = "okay"; - aspeed,reset-type = "system"; -}; - -&wdt2 { - status = "disabled"; -}; - -&fmc { - status = "okay"; - flash@0 { - status = "okay"; - m25p,fast-read; - label = "fmc0"; -#include "facebook-bmc-flash-layout.dtsi" - }; -}; - -&uart1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd1_default - &pinctrl_rxd1_default>; -}; - -&uart3 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd3_default - &pinctrl_rxd3_default>; -}; - -&uart4 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd4_default - &pinctrl_rxd4_default>; -}; - -&uart5 { - status = "okay"; -}; - -&mac1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; -}; - -&i2c0 { - status = "okay"; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c3 { - status = "okay"; -}; - -&i2c4 { - status = "okay"; -}; - -&i2c5 { - status = "okay"; -}; - -&i2c6 { - status = "okay"; -}; - -&i2c7 { - status = "okay"; -}; - -&i2c8 { - status = "okay"; -}; - -&i2c9 { - status = "okay"; -}; - -&i2c10 { - status = "okay"; -}; - -&i2c11 { - status = "okay"; -}; - -&i2c12 { - status = "okay"; -}; - -&i2c13 { - status = "okay"; -}; - -&vhub { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/aspeed-bmc-facebook-yamp.dts b/sys/gnu/dts/arm/aspeed-bmc-facebook-yamp.dts deleted file mode 100644 index fe2e11c2da1..00000000000 --- a/sys/gnu/dts/arm/aspeed-bmc-facebook-yamp.dts +++ /dev/null @@ -1,110 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// Copyright (c) 2018 Facebook Inc. -/dts-v1/; - -#include "ast2500-facebook-netbmc-common.dtsi" - -/ { - model = "Facebook YAMP 100 BMC"; - compatible = "facebook,yamp-bmc", "aspeed,ast2500"; - - aliases { - /* - * Override the default uart aliases to avoid breaking - * the legacy applications. - */ - serial0 = &uart5; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - }; - - chosen { - stdout-path = &uart5; - bootargs = "console=ttyS0,9600n8 root=/dev/ram rw"; - }; -}; - -&uart2 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd2_default - &pinctrl_rxd2_default>; -}; - -&mac0 { - status = "okay"; - use-ncsi; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rmii1_default>; - clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, - <&syscon ASPEED_CLK_MAC1RCLK>; - clock-names = "MACCLK", "RCLK"; -}; - -&mac1 { - status = "disabled"; -}; - -&i2c0 { - status = "okay"; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; - - i2c-switch@75 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x75>; - }; -}; - -&i2c3 { - status = "okay"; -}; - -&i2c4 { - status = "okay"; -}; - -&i2c5 { - status = "okay"; -}; - -&i2c6 { - status = "okay"; -}; - -&i2c7 { - status = "okay"; -}; - -&i2c8 { - status = "okay"; -}; - -&i2c9 { - status = "okay"; -}; - -&i2c10 { - status = "okay"; -}; - -&i2c11 { - status = "okay"; -}; - -&i2c12 { - status = "okay"; -}; - -&i2c13 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/aspeed-bmc-ibm-rainier.dts b/sys/gnu/dts/arm/aspeed-bmc-ibm-rainier.dts deleted file mode 100644 index 6232cd726a7..00000000000 --- a/sys/gnu/dts/arm/aspeed-bmc-ibm-rainier.dts +++ /dev/null @@ -1,597 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -// Copyright 2019 IBM Corp. -/dts-v1/; - -#include "aspeed-g6.dtsi" -#include - -/ { - model = "Rainier"; - compatible = "ibm,rainier-bmc", "aspeed,ast2600"; - - aliases { - serial4 = &uart5; - }; - - chosen { - stdout-path = &uart5; - bootargs = "console=ttyS4,115200n8"; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x40000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - flash_memory: region@B8000000 { - no-map; - reg = <0xB8000000 0x04000000>; /* 64M */ - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - ps0-presence { - label = "ps0-presence"; - gpios = <&gpio0 ASPEED_GPIO(S, 0) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - ps1-presence { - label = "ps1-presence"; - gpios = <&gpio0 ASPEED_GPIO(S, 1) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - ps2-presence { - label = "ps2-presence"; - gpios = <&gpio0 ASPEED_GPIO(S, 2) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - ps3-presence { - label = "ps3-presence"; - gpios = <&gpio0 ASPEED_GPIO(S, 3) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - -}; - -&emmc_controller { - status = "okay"; -}; - -&emmc { - status = "okay"; -}; - -&ibt { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - eeprom@51 { - compatible = "atmel,24c64"; - reg = <0x51>; - }; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c3 { - status = "okay"; - - power-supply@68 { - compatible = "ibm,cffps"; - reg = <0x68>; - }; - - power-supply@69 { - compatible = "ibm,cffps"; - reg = <0x69>; - }; - - power-supply@6a { - compatible = "ibm,cffps"; - reg = <0x6a>; - }; - - power-supply@6b { - compatible = "ibm,cffps"; - reg = <0x6b>; - }; -}; - -&i2c4 { - status = "okay"; - - tmp275@48 { - compatible = "ti,tmp275"; - reg = <0x48>; - }; - - tmp275@49 { - compatible = "ti,tmp275"; - reg = <0x49>; - }; - - tmp275@4a { - compatible = "ti,tmp275"; - reg = <0x4a>; - }; - - eeprom@50 { - compatible = "atmel,24c64"; - reg = <0x50>; - }; - - eeprom@51 { - compatible = "atmel,24c64"; - reg = <0x51>; - }; - - eeprom@52 { - compatible = "atmel,24c64"; - reg = <0x52>; - }; -}; - -&i2c5 { - status = "okay"; - - tmp275@48 { - compatible = "ti,tmp275"; - reg = <0x48>; - }; - - tmp275@49 { - compatible = "ti,tmp275"; - reg = <0x49>; - }; - - eeprom@50 { - compatible = "atmel,24c64"; - reg = <0x50>; - }; - - eeprom@51 { - compatible = "atmel,24c64"; - reg = <0x51>; - }; -}; - -&i2c6 { - status = "okay"; - - tmp275@48 { - compatible = "ti,tmp275"; - reg = <0x48>; - }; - - tmp275@4a { - compatible = "ti,tmp275"; - reg = <0x4a>; - }; - - tmp275@4b { - compatible = "ti,tmp275"; - reg = <0x4b>; - }; - - eeprom@50 { - compatible = "atmel,24c64"; - reg = <0x50>; - }; - - eeprom@51 { - compatible = "atmel,24c64"; - reg = <0x51>; - }; - - eeprom@52 { - compatible = "atmel,24c64"; - reg = <0x52>; - }; - - eeprom@53 { - compatible = "atmel,24c64"; - reg = <0x53>; - }; -}; - -&i2c7 { - status = "okay"; - - si7021-a20@20 { - compatible = "silabs,si7020"; - reg = <0x20>; - }; - - tmp275@48 { - compatible = "ti,tmp275"; - reg = <0x48>; - }; - - max31785@52 { - compatible = "maxim,max31785a"; - reg = <0x52>; - #address-cells = <1>; - #size-cells = <0>; - - fan@0 { - compatible = "pmbus-fan"; - reg = <0>; - tach-pulses = <2>; - }; - - fan@1 { - compatible = "pmbus-fan"; - reg = <1>; - tach-pulses = <2>; - }; - - fan@2 { - compatible = "pmbus-fan"; - reg = <2>; - tach-pulses = <2>; - }; - - fan@3 { - compatible = "pmbus-fan"; - reg = <3>; - tach-pulses = <2>; - }; - }; - - pca0: pca9552@61 { - compatible = "nxp,pca9552"; - reg = <0x61>; - #address-cells = <1>; - #size-cells = <0>; - - gpio-controller; - #gpio-cells = <2>; - - gpio@0 { - reg = <0>; - }; - - gpio@1 { - reg = <1>; - }; - - gpio@2 { - reg = <2>; - }; - - gpio@3 { - reg = <3>; - }; - - gpio@4 { - reg = <4>; - }; - - gpio@5 { - reg = <5>; - }; - - gpio@6 { - reg = <6>; - }; - - gpio@7 { - reg = <7>; - }; - - gpio@8 { - reg = <8>; - }; - - gpio@9 { - reg = <9>; - }; - - gpio@10 { - reg = <10>; - }; - - gpio@11 { - reg = <11>; - }; - - gpio@12 { - reg = <12>; - }; - - gpio@13 { - reg = <13>; - }; - - gpio@14 { - reg = <14>; - }; - - gpio@15 { - reg = <15>; - }; - }; - - dps: dps310@76 { - compatible = "infineon,dps310"; - reg = <0x76>; - #io-channel-cells = <0>; - }; - - eeprom@50 { - compatible = "atmel,24c64"; - reg = <0x50>; - }; - - eeprom@51 { - compatible = "atmel,24c64"; - reg = <0x51>; - }; -}; - -&i2c8 { - status = "okay"; - - ucd90320@11 { - compatible = "ti,ucd90320"; - reg = <0x11>; - }; - - rtc@32 { - compatible = "epson,rx8900"; - reg = <0x32>; - }; - - tmp275@48 { - compatible = "ti,tmp275"; - reg = <0x48>; - }; - - tmp275@4a { - compatible = "ti,tmp275"; - reg = <0x4a>; - }; - - eeprom@50 { - compatible = "atmel,24c64"; - reg = <0x50>; - }; - - eeprom@51 { - compatible = "atmel,24c64"; - reg = <0x51>; - }; -}; - -&i2c9 { - status = "okay"; - - ir35221@42 { - compatible = "infineon,ir35221"; - reg = <0x42>; - }; - - ir35221@43 { - compatible = "infineon,ir35221"; - reg = <0x43>; - }; - - ir35221@44 { - compatible = "infineon,ir35221"; - reg = <0x44>; - }; - - tmp423a@4c { - compatible = "ti,tmp423"; - reg = <0x4c>; - }; - - tmp423b@4d { - compatible = "ti,tmp423"; - reg = <0x4d>; - }; - - ir35221@72 { - compatible = "infineon,ir35221"; - reg = <0x72>; - }; - - ir35221@73 { - compatible = "infineon,ir35221"; - reg = <0x73>; - }; - - ir35221@74 { - compatible = "infineon,ir35221"; - reg = <0x74>; - }; - - eeprom@50 { - compatible = "atmel,24c128"; - reg = <0x50>; - }; -}; - -&i2c10 { - status = "okay"; - - ir35221@42 { - compatible = "infineon,ir35221"; - reg = <0x42>; - }; - - ir35221@43 { - compatible = "infineon,ir35221"; - reg = <0x43>; - }; - - ir35221@44 { - compatible = "infineon,ir35221"; - reg = <0x44>; - }; - - tmp423a@4c { - compatible = "ti,tmp423"; - reg = <0x4c>; - }; - - tmp423b@4d { - compatible = "ti,tmp423"; - reg = <0x4d>; - }; - - ir35221@72 { - compatible = "infineon,ir35221"; - reg = <0x72>; - }; - - ir35221@73 { - compatible = "infineon,ir35221"; - reg = <0x73>; - }; - - ir35221@74 { - compatible = "infineon,ir35221"; - reg = <0x74>; - }; - - eeprom@50 { - compatible = "atmel,24c128"; - reg = <0x50>; - }; -}; - -&i2c11 { - status = "okay"; - - tmp275@48 { - compatible = "ti,tmp275"; - reg = <0x48>; - }; - - tmp275@49 { - compatible = "ti,tmp275"; - reg = <0x49>; - }; - - eeprom@50 { - compatible = "atmel,24c64"; - reg = <0x50>; - }; - - eeprom@51 { - compatible = "atmel,24c64"; - reg = <0x51>; - }; -}; - -&i2c12 { - status = "okay"; -}; - -&i2c13 { - status = "okay"; - - eeprom@50 { - compatible = "atmel,24c64"; - reg = <0x50>; - }; -}; - -&i2c14 { - status = "okay"; - - eeprom@50 { - compatible = "atmel,24c64"; - reg = <0x50>; - }; -}; - -&i2c15 { - status = "okay"; - - eeprom@50 { - compatible = "atmel,24c64"; - reg = <0x50>; - }; -}; - -&vuart1 { - status = "okay"; -}; - -&lpc_ctrl { - status = "okay"; - memory-region = <&flash_memory>; -}; - -&mac2 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rmii3_default>; - clocks = <&syscon ASPEED_CLK_GATE_MAC3CLK>, - <&syscon ASPEED_CLK_MAC3RCLK>; - clock-names = "MACCLK", "RCLK"; - use-ncsi; -}; - -&mac3 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rmii4_default>; - clocks = <&syscon ASPEED_CLK_GATE_MAC4CLK>, - <&syscon ASPEED_CLK_MAC4RCLK>; - clock-names = "MACCLK", "RCLK"; - use-ncsi; -}; - -&fmc { - status = "okay"; - flash@0 { - status = "okay"; - m25p,fast-read; - label = "bmc"; - spi-max-frequency = <50000000>; -#include "openbmc-flash-layout-128.dtsi" - }; - - flash@1 { - status = "okay"; - m25p,fast-read; - label = "alt-bmc"; - spi-max-frequency = <50000000>; - }; -}; - -&spi1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1_default>; - - flash@0 { - status = "okay"; - m25p,fast-read; - label = "pnor"; - spi-max-frequency = <100000000>; - }; -}; diff --git a/sys/gnu/dts/arm/aspeed-bmc-inspur-fp5280g2.dts b/sys/gnu/dts/arm/aspeed-bmc-inspur-fp5280g2.dts deleted file mode 100644 index 62a3ab4c186..00000000000 --- a/sys/gnu/dts/arm/aspeed-bmc-inspur-fp5280g2.dts +++ /dev/null @@ -1,872 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/dts-v1/; -#include "aspeed-g5.dtsi" -#include -#include - -/ { - model = "FP5280G2 BMC"; - compatible = "inspur,fp5280g2-bmc", "aspeed,ast2500"; - - chosen { - stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlyprintk"; - }; - - memory@80000000 { - reg = <0x80000000 0x20000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - vga_memory: framebuffer@9f000000 { - no-map; - reg = <0x9f000000 0x01000000>; /* 16M */ - }; - - flash_memory: region@98000000 { - no-map; - reg = <0x98000000 0x04000000>; /* 64M */ - }; - - coldfire_memory: codefire_memory@9ef00000 { - reg = <0x9ef00000 0x00100000>; - no-map; - }; - - gfx_memory: framebuffer { - size = <0x01000000>; - alignment = <0x01000000>; - compatible = "shared-dma-pool"; - reusable; - }; - - video_engine_memory: jpegbuffer { - size = <0x02000000>; /* 32M */ - alignment = <0x01000000>; - compatible = "shared-dma-pool"; - reusable; - }; - }; - - fsi: gpio-fsi { - compatible = "aspeed,ast2500-cf-fsi-master", "fsi-master"; - #address-cells = <2>; - #size-cells = <0>; - no-gpio-delays; - - memory-region = <&coldfire_memory>; - aspeed,sram = <&sram>; - aspeed,cvic = <&cvic>; - - clock-gpios = <&gpio ASPEED_GPIO(AA, 0) GPIO_ACTIVE_HIGH>; - data-gpios = <&gpio ASPEED_GPIO(AA, 2) GPIO_ACTIVE_HIGH>; - mux-gpios = <&gpio ASPEED_GPIO(I, 2) GPIO_ACTIVE_HIGH>; - enable-gpios = <&gpio ASPEED_GPIO(I, 3) GPIO_ACTIVE_HIGH>; - trans-gpios = <&gpio ASPEED_GPIO(R, 2) GPIO_ACTIVE_HIGH>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - checkstop { - label = "checkstop"; - gpios = <&gpio ASPEED_GPIO(B, 3) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - ps0-presence { - label = "ps0-presence"; - gpios = <&gpio ASPEED_GPIO(F, 0) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - ps1-presence { - label = "ps1-presence"; - gpios = <&gpio ASPEED_GPIO(F, 1) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - poll-interval = <1000>; - - fan0-presence { - label = "fan0-presence"; - gpios = <&pca1 0 GPIO_ACTIVE_LOW>; - linux,code = <1>; - }; - - fan1-presence { - label = "fan1-presence"; - gpios = <&pca1 1 GPIO_ACTIVE_LOW>; - linux,code = <2>; - }; - - fan2-presence { - label = "fan2-presence"; - gpios = <&pca1 2 GPIO_ACTIVE_LOW>; - linux,code = <3>; - }; - - fan3-presence { - label = "fan3-presence"; - gpios = <&pca1 3 GPIO_ACTIVE_LOW>; - linux,code = <4>; - }; - - fan4-presence { - label = "fan4-presence"; - gpios = <&pca1 4 GPIO_ACTIVE_LOW>; - linux,code = <5>; - }; - - fan5-presence { - label = "fan5-presence"; - gpios = <&pca1 5 GPIO_ACTIVE_LOW>; - linux,code = <6>; - }; - - fan6-presence { - label = "fan6-presence"; - gpios = <&pca1 6 GPIO_ACTIVE_LOW>; - linux,code = <7>; - }; - - fan7-presence { - label = "fan7-presence"; - gpios = <&pca1 7 GPIO_ACTIVE_LOW>; - linux,code = <8>; - }; - }; - - leds { - compatible = "gpio-leds"; - - power { - label = "power"; - /* TODO: dummy gpio */ - gpios = <&gpio ASPEED_GPIO(R, 1) GPIO_ACTIVE_LOW>; - }; - - init-ok { - label = "init-ok"; - gpios = <&gpio ASPEED_GPIO(B, 7) GPIO_ACTIVE_LOW>; - }; - - front-memory { - label = "front-memory"; - gpios = <&gpio ASPEED_GPIO(F, 4) GPIO_ACTIVE_LOW>; - }; - - front-syshot { - label = "front-syshot"; - gpios = <&gpio ASPEED_GPIO(I, 1) GPIO_ACTIVE_LOW>; - }; - - front-syshealth { - label = "front-syshealth"; - gpios = <&gpio ASPEED_GPIO(I, 0) GPIO_ACTIVE_LOW>; - }; - - front-fan { - label = "front-fan"; - gpios = <&gpio ASPEED_GPIO(H, 4) GPIO_ACTIVE_LOW>; - }; - - front-psu { - label = "front-psu"; - gpios = <&gpio ASPEED_GPIO(B, 2) GPIO_ACTIVE_LOW>; - }; - - identify { - label = "identify"; - gpios = <&gpio ASPEED_GPIO(Z, 7) GPIO_ACTIVE_LOW>; - }; - }; - - iio-hwmon-battery { - compatible = "iio-hwmon"; - io-channels = <&adc 15>; - }; - - iio-hwmon { - compatible = "iio-hwmon"; - io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, <&adc 4>, - <&adc 5>, <&adc 6>, <&adc 7>, <&adc 8>, <&adc 9>, - <&adc 10>, <&adc 11>, <&adc 12>, <&adc 13>, <&adc 14>; - }; - -}; - -&fmc { - status = "okay"; - - flash@0 { - status = "okay"; - label = "bmc"; - m25p,fast-read; - spi-max-frequency = <50000000>; -#include "openbmc-flash-layout.dtsi" - }; -}; - -&spi1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1_default>; - - flash@0 { - status = "okay"; - label = "pnor"; - m25p,fast-read; - spi-max-frequency = <100000000>; - }; -}; - -&uart1 { - /* Rear RS-232 connector */ - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd1_default - &pinctrl_rxd1_default - &pinctrl_nrts1_default - &pinctrl_ndtr1_default - &pinctrl_ndsr1_default - &pinctrl_ncts1_default - &pinctrl_ndcd1_default - &pinctrl_nri1_default>; -}; - -&uart2 { - /* Test Point */ - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd2_default &pinctrl_rxd2_default>; -}; - -&uart3 { - /* APSS */ - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd3_default &pinctrl_rxd3_default>; -}; - -&uart5 { - status = "okay"; -}; - -&lpc_ctrl { - status = "okay"; - memory-region = <&flash_memory>; - flash = <&spi1>; -}; - -&mac0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rmii1_default>; - clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, - <&syscon ASPEED_CLK_MAC1RCLK>; - clock-names = "MACCLK", "RCLK"; - use-ncsi; -}; - -&mac1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; -}; - -&i2c0 { - /* LCD */ - status = "okay"; -}; - -&i2c1 { - status = "okay"; - - eeprom@50 { - compatible = "atmel,24c256"; - reg = <0x50>; - label = "fru"; - }; - -}; - -&i2c2 { - status = "okay"; - - tmp112@48 { - compatible = "ti,tmp112"; - reg = <0x48>; - label = "inlet"; - }; - - tmp112@49 { - compatible = "ti,tmp112"; - reg = <0x49>; - label = "outlet"; - }; - - i2c-switch@70 { - compatible = "nxp,pca9546"; - reg = <0x70>; - #address-cells = <1>; - #size-cells = <0>; - - i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - tmp112@4a { - compatible = "ti,tmp112"; - reg = <0x4a>; - label = "psu_inlet"; - }; - - }; - - i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - tmp112@4a { - compatible = "ti,tmp112"; - reg = <0x4a>; - label = "ocp_zone"; - }; - }; - - i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - - tmp112@4a { - compatible = "ti,tmp112"; - reg = <0x4a>; - label = "bmc_zone"; - }; - }; - - i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - - tmp112@7c { - compatible = "microchip,emc1413"; - reg = <0x7c>; - }; - }; - - }; -}; - -&i2c3 { - /* Riser Card */ - status = "okay"; -}; - -&i2c4 { - status = "okay"; - - rtc@68 { - compatible = "dallas,ds3232"; - reg = <0x68>; - }; -}; - -&i2c5 { - /* vr */ - status = "okay"; -}; - -&i2c6 { - /* bp card */ - status = "okay"; -}; - -&i2c7 { - status = "okay"; - - i2c-switch@70 { - compatible = "nxp,pca9546"; - reg = <0x70>; - #address-cells = <1>; - #size-cells = <0>; - - i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - adm1278@10 { - compatible = "adi,adm1278"; - reg = <0x10>; - }; - - adm1278@13 { - compatible = "adi,adm1278"; - reg = <0x13>; - }; - - adm1278@50 { - compatible = "adi,adm1278"; - reg = <0x50>; - }; - - adm1278@53 { - compatible = "adi,adm1278"; - reg = <0x53>; - }; - - }; - - /*pcie riser*/ - - }; -}; - -&i2c8 { - status = "okay"; - - pca0: pca9555@20 { - compatible = "nxp,pca9555"; - reg = <0x20>; - #address-cells = <1>; - #size-cells = <0>; - - gpio-controller; - #gpio-cells = <2>; - - gpio@0 { - reg = <0>; - type = ; - }; - - gpio@1 { - reg = <1>; - type = ; - }; - - gpio@2 { - reg = <2>; - type = ; - }; - - gpio@3 { - reg = <3>; - type = ; - }; - - gpio@4 { - reg = <4>; - type = ; - }; - - gpio@5 { - reg = <5>; - type = ; - }; - - gpio@6 { - reg = <6>; - type = ; - }; - - gpio@7 { - reg = <7>; - type = ; - }; - - }; - - pca1: pca9555@21 { - compatible = "nxp,pca9555"; - reg = <0x21>; - #address-cells = <1>; - #size-cells = <0>; - - gpio-controller; - #gpio-cells = <2>; - - gpio@0 { - reg = <0>; - type = ; - }; - - gpio@1 { - reg = <1>; - type = ; - }; - - gpio@2 { - reg = <2>; - type = ; - }; - - gpio@3 { - reg = <3>; - type = ; - }; - - gpio@4 { - reg = <4>; - type = ; - }; - - gpio@5 { - reg = <5>; - type = ; - }; - - gpio@6 { - reg = <6>; - type = ; - }; - - gpio@7 { - reg = <7>; - type = ; - }; - }; - - pca2: pca9555@22 { - compatible = "nxp,pca9555"; - reg = <0x22>; - #address-cells = <1>; - #size-cells = <0>; - - gpio-controller; - #gpio-cells = <2>; - - gpio@0 { - reg = <0>; - type = ; - }; - - gpio@1 { - reg = <1>; - type = ; - }; - - gpio@2 { - reg = <2>; - type = ; - }; - - gpio@3 { - reg = <3>; - type = ; - }; - - gpio@4 { - reg = <4>; - type = ; - }; - - gpio@5 { - reg = <5>; - type = ; - }; - - gpio@6 { - reg = <6>; - type = ; - }; - - gpio@7 { - reg = <7>; - type = ; - }; - }; - - pca3: pca9555@23 { - compatible = "nxp,pca9555"; - reg = <0x23>; - #address-cells = <1>; - #size-cells = <0>; - - gpio-controller; - #gpio-cells = <2>; - - gpio@0 { - reg = <0>; - type = ; - }; - - gpio@1 { - reg = <1>; - type = ; - }; - - gpio@2 { - reg = <2>; - type = ; - }; - - gpio@3 { - reg = <3>; - type = ; - }; - - gpio@4 { - reg = <4>; - type = ; - }; - - gpio@5 { - reg = <5>; - type = ; - }; - - gpio@6 { - reg = <6>; - type = ; - }; - - gpio@7 { - reg = <7>; - type = ; - }; - }; - - pca4: pca9555@24 { - compatible = "nxp,pca9555"; - reg = <0x24>; - #address-cells = <1>; - #size-cells = <0>; - - gpio-controller; - #gpio-cells = <2>; - - gpio@0 { - reg = <0>; - type = ; - }; - - gpio@1 { - reg = <1>; - type = ; - }; - - gpio@2 { - reg = <2>; - type = ; - }; - - gpio@3 { - reg = <3>; - type = ; - }; - - gpio@4 { - reg = <4>; - type = ; - }; - - gpio@5 { - reg = <5>; - type = ; - }; - - gpio@6 { - reg = <6>; - type = ; - }; - - gpio@7 { - reg = <7>; - type = ; - }; - }; - - pca5: pca9555@25 { - compatible = "nxp,pca9555"; - reg = <0x25>; - #address-cells = <1>; - #size-cells = <0>; - - gpio-controller; - #gpio-cells = <2>; - - gpio@0 { - reg = <0>; - type = ; - }; - - gpio@1 { - reg = <1>; - type = ; - }; - - gpio@2 { - reg = <2>; - type = ; - }; - - gpio@3 { - reg = <3>; - type = ; - }; - - gpio@4 { - reg = <4>; - type = ; - }; - - gpio@5 { - reg = <5>; - type = ; - }; - - gpio@6 { - reg = <6>; - type = ; - }; - - gpio@7 { - reg = <7>; - type = ; - }; - }; - -}; - -&i2c9 { - /* cpld */ - status = "okay"; -}; - -&i2c10 { - /* hdd bp */ - status = "okay"; -}; - -&i2c11 { - status = "okay"; - - power-supply@58 { - compatible = "pmbus"; - reg = <0x58>; - }; - - power-supply@59 { - compatible = "pmbus"; - reg = <0x59>; - }; -}; - -&i2c12 { - /* odcc */ - status = "okay"; -}; - -&vuart { - status = "okay"; -}; - -&gfx { - status = "okay"; - memory-region = <&gfx_memory>; -}; - -&pinctrl { - aspeed,external-nodes = <&gfx &lhc>; -}; - -&wdt1 { - aspeed,reset-type = "none"; - aspeed,external-signal; - aspeed,ext-push-pull; - aspeed,ext-active-high; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdtrst1_default>; -}; - -&ibt { - status = "okay"; - -}; - -&adc { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_adc0_default &pinctrl_adc1_default - &pinctrl_adc2_default &pinctrl_adc3_default &pinctrl_adc4_default - &pinctrl_adc5_default &pinctrl_adc6_default &pinctrl_adc7_default - &pinctrl_adc8_default &pinctrl_adc9_default &pinctrl_adc10_default - &pinctrl_adc11_default &pinctrl_adc12_default &pinctrl_adc13_default - &pinctrl_adc14_default &pinctrl_adc15_default>; -}; - -&vhub { - status = "okay"; -}; - -&video { - status = "okay"; - memory-region = <&video_engine_memory>; -}; - -&pwm_tacho { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default - &pinctrl_pwm2_default &pinctrl_pwm3_default - &pinctrl_pwm4_default &pinctrl_pwm5_default - &pinctrl_pwm6_default &pinctrl_pwm7_default>; - - fan@0 { - reg = <0x00>; - aspeed,fan-tach-ch = /bits/ 8 <0x00 0x01>; - }; - - fan@1 { - reg = <0x01>; - aspeed,fan-tach-ch = /bits/ 8 <0x02 0x03>; - }; - - fan@2 { - reg = <0x02>; - aspeed,fan-tach-ch = /bits/ 8 <0x04 0x05>; - }; - - fan@3 { - reg = <0x03>; - aspeed,fan-tach-ch = /bits/ 8 <0x06 0x07>; - }; - - fan@4 { - reg = <0x04>; - aspeed,fan-tach-ch = /bits/ 8 <0x08 0x09>; - }; - - fan@5 { - reg = <0x05>; - aspeed,fan-tach-ch = /bits/ 8 <0x0a 0x0b>; - }; - - fan@6 { - reg = <0x06>; - aspeed,fan-tach-ch = /bits/ 8 <0x0c 0x0d>; - }; - - fan@7 { - reg = <0x07>; - aspeed,fan-tach-ch = /bits/ 8 <0x0e 0x0f>; - }; - -}; - -#include "ibm-power9-dual.dtsi" diff --git a/sys/gnu/dts/arm/aspeed-bmc-inspur-on5263m5.dts b/sys/gnu/dts/arm/aspeed-bmc-inspur-on5263m5.dts deleted file mode 100644 index 80c92e065a1..00000000000 --- a/sys/gnu/dts/arm/aspeed-bmc-inspur-on5263m5.dts +++ /dev/null @@ -1,148 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (c) 2018 Inspur Corporation -/dts-v1/; - -#include "aspeed-g5.dtsi" -#include - -/ { - model = "ON5263M5 BMC"; - compatible = "inspur,on5263m5-bmc", "aspeed,ast2500"; - - chosen { - stdout-path = &uart5; - bootargs = "earlyprintk"; - }; - - memory { - reg = <0x80000000 0x20000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - vga_memory: framebuffer@9f000000 { - no-map; - reg = <0x9f000000 0x01000000>; - }; - }; - - leds { - compatible = "gpio-leds"; - bmc_alive { - label = "bmc_alive"; - gpios = <&gpio ASPEED_GPIO(I, 1) GPIO_ACTIVE_LOW>; - linux,default-trigger = "timer"; - }; - }; - - iio-hwmon { - compatible = "iio-hwmon"; - io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, - <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>; - }; - -}; - -&fmc { - status = "okay"; - flash@0 { - status = "okay"; - m25p,fast-read; - label = "bmc"; -#include "openbmc-flash-layout.dtsi" - }; -}; - -&spi1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1_default>; - - flash@0 { - status = "okay"; - m25p,fast-read; - label = "pnor"; - }; -}; - -&uart5 { - status = "okay"; -}; - -&mac0 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rmii1_default>; - clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, - <&syscon ASPEED_CLK_MAC1RCLK>; - clock-names = "MACCLK", "RCLK"; - use-ncsi; -}; - -&mac1 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; -}; - -&i2c6 { - status = "okay"; - - tmp421@4e { - compatible = "ti,tmp421"; - reg = <0x4e>; - }; - - tmp112@48 { - compatible = "ti,tmp112"; - reg = <0x48>; - }; - - eeprom@54 { - compatible = "atmel,24c64"; - reg = <0x54>; - pagesize = <32>; - }; -}; - -&i2c7 { - status = "okay"; - - adm1278@11 { - compatible = "adi,adm1278"; - reg = <0x11>; - }; -}; - -&gfx { - status = "okay"; -}; - -&pinctrl { - aspeed,external-nodes = <&gfx &lhc>; -}; - -&pwm_tacho { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default>; - - fan@0 { - reg = <0x00>; - aspeed,fan-tach-ch = /bits/ 8 <0x00 0x01>; - }; - - fan@1 { - reg = <0x01>; - aspeed,fan-tach-ch = /bits/ 8 <0x02 0x03>; - }; -}; - -&adc { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/aspeed-bmc-intel-s2600wf.dts b/sys/gnu/dts/arm/aspeed-bmc-intel-s2600wf.dts deleted file mode 100644 index 1deb30ec912..00000000000 --- a/sys/gnu/dts/arm/aspeed-bmc-intel-s2600wf.dts +++ /dev/null @@ -1,132 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (c) 2017 Intel Corporation -/dts-v1/; - -#include "aspeed-g5.dtsi" - -/ { - model = "S2600WF BMC"; - compatible = "intel,s2600wf-bmc", "aspeed,ast2500"; - - chosen { - stdout-path = &uart5; - bootargs = "earlyprintk"; - }; - - memory@80000000 { - reg = <0x80000000 0x20000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - vga_memory: framebuffer@7f000000 { - no-map; - reg = <0x7f000000 0x01000000>; - }; - }; - - iio-hwmon { - compatible = "iio-hwmon"; - io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, - <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>, - <&adc 8>, <&adc 9>, <&adc 10>, <&adc 11>, - <&adc 12>, <&adc 13>, <&adc 14>, <&adc 15>; - }; - -}; - -&fmc { - status = "okay"; - flash@0 { - status = "okay"; - m25p,fast-read; - label = "bmc"; -#include "openbmc-flash-layout.dtsi" - }; -}; - -&spi1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1_default>; - - flash@0 { - status = "okay"; - m25p,fast-read; - label = "pnor"; - }; -}; - -&uart5 { - status = "okay"; -}; - -&mac0 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rmii1_default>; - clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, - <&syscon ASPEED_CLK_MAC1RCLK>; - clock-names = "MACCLK", "RCLK"; - use-ncsi; -}; - -&mac1 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c3 { - status = "okay"; -}; - -&i2c4 { - status = "okay"; -}; - -&i2c5 { - status = "okay"; -}; - -&i2c6 { - status = "okay"; -}; - -&i2c7 { - status = "okay"; -}; - -&i2c13 { - status = "okay"; -}; - -&gfx { - status = "okay"; -}; - -&pinctrl { - aspeed,external-nodes = <&gfx &lhc>; -}; - -&pwm_tacho { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default - &pinctrl_pwm2_default &pinctrl_pwm3_default - &pinctrl_pwm4_default &pinctrl_pwm5_default - &pinctrl_pwm6_default &pinctrl_pwm7_default>; -}; diff --git a/sys/gnu/dts/arm/aspeed-bmc-lenovo-hr630.dts b/sys/gnu/dts/arm/aspeed-bmc-lenovo-hr630.dts deleted file mode 100644 index c29e5f4d86a..00000000000 --- a/sys/gnu/dts/arm/aspeed-bmc-lenovo-hr630.dts +++ /dev/null @@ -1,569 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Device Tree file for Lenovo Hr630 platform - * - * Copyright (C) 2019-present Lenovo - */ - -/dts-v1/; - -#include "aspeed-g5.dtsi" -#include - -/ { - model = "HR630 BMC"; - compatible = "lenovo,hr630-bmc", "aspeed,ast2500"; - - aliases { - i2c14 = &i2c_rbp; - i2c15 = &i2c_fbp1; - i2c16 = &i2c_fbp2; - i2c17 = &i2c_fbp3; - i2c18 = &i2c_riser2; - i2c19 = &i2c_pcie4; - i2c20 = &i2c_riser1; - i2c21 = &i2c_ocp; - }; - - chosen { - stdout-path = &uart5; - bootargs = "console=tty0 console=ttyS4,115200 earlyprintk"; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - flash_memory: region@98000000 { - no-map; - reg = <0x98000000 0x00100000>; /* 1M */ - }; - - gfx_memory: framebuffer { - size = <0x01000000>; - alignment = <0x01000000>; - compatible = "shared-dma-pool"; - reusable; - }; - }; - - leds { - compatible = "gpio-leds"; - - heartbeat { - gpios = <&gpio ASPEED_GPIO(J, 1) GPIO_ACTIVE_LOW>; - }; - - fault { - gpios = <&gpio ASPEED_GPIO(J, 0) GPIO_ACTIVE_LOW>; - }; - }; - - iio-hwmon { - compatible = "iio-hwmon"; - io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, - <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>, - <&adc 8>, <&adc 9>, <&adc 10>, - <&adc 12>, <&adc 13>, <&adc 14>; - }; - -}; - -&fmc { - status = "okay"; - flash@0 { - status = "okay"; - m25p,fast-read; - label = "bmc"; - spi-max-frequency = <50000000>; -#include "openbmc-flash-layout.dtsi" - }; -}; - -&lpc_ctrl { - status = "okay"; - memory-region = <&flash_memory>; - flash = <&spi1>; -}; - -&uart1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd1_default - &pinctrl_rxd1_default>; -}; - -&uart2 { - /* Rear RS-232 connector */ - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd2_default - &pinctrl_rxd2_default - &pinctrl_nrts2_default - &pinctrl_ndtr2_default - &pinctrl_ndsr2_default - &pinctrl_ncts2_default - &pinctrl_ndcd2_default - &pinctrl_nri2_default>; -}; - -&uart3 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd3_default - &pinctrl_rxd3_default>; -}; - -&uart5 { - status = "okay"; -}; - -&ibt { - status = "okay"; -}; - -&mac0 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rmii1_default>; - clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, - <&syscon ASPEED_CLK_MAC1RCLK>; - clock-names = "MACCLK", "RCLK"; - use-ncsi; -}; - -&mac1 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; -}; - -&adc { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_adc0_default - &pinctrl_adc1_default - &pinctrl_adc2_default - &pinctrl_adc3_default - &pinctrl_adc4_default - &pinctrl_adc5_default - &pinctrl_adc6_default - &pinctrl_adc7_default - &pinctrl_adc8_default - &pinctrl_adc9_default - &pinctrl_adc10_default - &pinctrl_adc12_default - &pinctrl_adc13_default - &pinctrl_adc14_default>; -}; - -&i2c0 { - status = "okay"; - /* temp1 inlet */ - tmp75@4e { - compatible = "national,lm75"; - reg = <0x4e>; - }; -}; - -&i2c1 { - status = "okay"; - /* temp2 outlet */ - tmp75@4d { - compatible = "national,lm75"; - reg = <0x4d>; - }; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c3 { - status = "okay"; -}; - -&i2c4 { - status = "okay"; -}; - -&i2c5 { - status = "okay"; -}; - -&i2c6 { - status = "okay"; - /* Slot 0, - * Slot 1, - * Slot 2, - * Slot 3 - */ - - i2c-switch@70 { - compatible = "nxp,pca9545"; - reg = <0x70>; - #address-cells = <1>; - #size-cells = <0>; - i2c-mux-idle-disconnect; /* may use mux@70 next. */ - - i2c_rbp: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - i2c_fbp1: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - i2c_fbp2: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - i2c_fbp3: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - }; -}; - -&i2c7 { - status = "okay"; - - /* Slot 0, - * Slot 1, - * Slot 2, - * Slot 3 - */ - i2c-switch@76 { - compatible = "nxp,pca9546"; - reg = <0x76>; - #address-cells = <1>; - #size-cells = <0>; - i2c-mux-idle-disconnect; /* may use mux@76 next. */ - - i2c_riser2: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - i2c_pcie4: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - i2c_riser1: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - i2c_ocp: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - }; -}; - -&i2c8 { - status = "okay"; - - eeprom@57 { - compatible = "atmel,24c256"; - reg = <0x57>; - pagesize = <16>; - }; -}; - -&i2c9 { - status = "okay"; -}; - -&i2c10 { - status = "okay"; -}; - -&i2c11 { - status = "okay"; -}; - -&i2c12 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&uhci { - status = "okay"; -}; - -&gfx { - status = "okay"; - memory-region = <&gfx_memory>; -}; - -&pwm_tacho { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm0_default - &pinctrl_pwm1_default - &pinctrl_pwm2_default - &pinctrl_pwm3_default - &pinctrl_pwm4_default - &pinctrl_pwm5_default - &pinctrl_pwm6_default>; - - fan@0 { - reg = <0x00>; - aspeed,fan-tach-ch = /bits/ 8 <0x00>; - }; - - fan@1 { - reg = <0x00>; - aspeed,fan-tach-ch = /bits/ 8 <0x01>; - }; - - fan@2 { - reg = <0x01>; - aspeed,fan-tach-ch = /bits/ 8 <0x02>; - }; - - fan@3 { - reg = <0x01>; - aspeed,fan-tach-ch = /bits/ 8 <0x03>; - }; - - fan@4 { - reg = <0x02>; - aspeed,fan-tach-ch = /bits/ 8 <0x04>; - }; - - fan@5 { - reg = <0x02>; - aspeed,fan-tach-ch = /bits/ 8 <0x05>; - }; - - fan@6 { - reg = <0x03>; - aspeed,fan-tach-ch = /bits/ 8 <0x06>; - }; - - fan@7 { - reg = <0x03>; - aspeed,fan-tach-ch = /bits/ 8 <0x07>; - }; - - fan@8 { - reg = <0x04>; - aspeed,fan-tach-ch = /bits/ 8 <0x08>; - }; - - fan@9 { - reg = <0x04>; - aspeed,fan-tach-ch = /bits/ 8 <0x09>; - }; - - fan@10 { - reg = <0x05>; - aspeed,fan-tach-ch = /bits/ 8 <0x0a>; - }; - - fan@11 { - reg = <0x05>; - aspeed,fan-tach-ch = /bits/ 8 <0x0b>; - }; - - fan@12 { - reg = <0x06>; - aspeed,fan-tach-ch = /bits/ 8 <0x0c>; - }; - - fan@13 { - reg = <0x06>; - aspeed,fan-tach-ch = /bits/ 8 <0x0d>; - }; -}; - -&gpio { - - pin_gpio_b5 { - gpio-hog; - gpios = ; - output-high; - line-name = "IRQ_BMC_PCH_SMI_LPC_N"; - }; - - pin_gpio_f0 { - gpio-hog; - gpios = ; - output-low; - line-name = "IRQ_BMC_PCH_NMI_R"; - }; - - pin_gpio_f3 { - gpio-hog; - gpios = ; - output-high; - line-name = "I2C_BUS0_RST_OUT_N"; - }; - - pin_gpio_f4 { - gpio-hog; - gpios = ; - output-low; - line-name = "FM_SKT0_FAULT_LED"; - }; - - pin_gpio_f5 { - gpio-hog; - gpios = ; - output-low; - line-name = "FM_SKT1_FAULT_LED"; - }; - - pin_gpio_g4 { - gpio-hog; - gpios = ; - output-high; - line-name = "FAN_PWR_CTL_N"; - }; - - pin_gpio_g7 { - gpio-hog; - gpios = ; - output-high; - line-name = "RST_BMC_PCIE_I2CMUX_N"; - }; - - pin_gpio_h2 { - gpio-hog; - gpios = ; - output-high; - line-name = "PSU1_FFS_N_R"; - }; - - pin_gpio_h3 { - gpio-hog; - gpios = ; - output-high; - line-name = "PSU2_FFS_N_R"; - }; - - pin_gpio_i3 { - gpio-hog; - gpios = ; - output-high; - line-name = "BMC_INTRUDED_COVER"; - }; - - pin_gpio_j2 { - gpio-hog; - gpios = ; - output-high; - line-name = "BMC_BIOS_UPDATE_N"; - }; - - pin_gpio_j3 { - gpio-hog; - gpios = ; - output-high; - line-name = "RST_BMC_HDD_I2CMUX_N"; - }; - - pin_gpio_s2 { - gpio-hog; - gpios = ; - output-high; - line-name = "BMC_VGA_SW"; - }; - - pin_gpio_s4 { - gpio-hog; - gpios = ; - output; - line-name = "VBAT_EN_N"; - }; - - pin_gpio_s6 { - gpio-hog; - gpios = ; - output-high; - line-name = "PU_BMC_GPIOS6"; - }; - - pin_gpio_y0 { - gpio-hog; - gpios = ; - output-low; - line-name = "BMC_NCSI_MUX_CTL_S0"; - }; - - pin_gpio_y1 { - gpio-hog; - gpios = ; - output-low; - line-name = "BMC_NCSI_MUX_CTL_S1"; - }; - - pin_gpio_z0 { - gpio-hog; - gpios = ; - output-high; - line-name = "I2C_RISER2_INT_N"; - }; - - pin_gpio_z2 { - gpio-hog; - gpios = ; - output-high; - line-name = "I2C_RISER2_RESET_N"; - }; - - pin_gpio_z3 { - gpio-hog; - gpios = ; - output-high; - line-name = "FM_BMC_PCH_SCI_LPC_N"; - }; - - pin_gpio_z7 { - gpio-hog; - gpios = ; - output-low; - line-name = "BMC_POST_CMPLT_N"; - }; - - pin_gpio_aa0 { - gpio-hog; - gpios = ; - output-low; - line-name = "HOST_BMC_USB_SEL"; - }; - - pin_gpio_aa5 { - gpio-hog; - gpios = ; - output-high; - line-name = "I2C_BUS1_RST_OUT_N"; - }; - -}; diff --git a/sys/gnu/dts/arm/aspeed-bmc-lenovo-hr855xg2.dts b/sys/gnu/dts/arm/aspeed-bmc-lenovo-hr855xg2.dts deleted file mode 100644 index 084c455ad4c..00000000000 --- a/sys/gnu/dts/arm/aspeed-bmc-lenovo-hr855xg2.dts +++ /dev/null @@ -1,666 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Device Tree file for Lenovo Hr855xg2 platform - * - * Copyright (C) 2019-present Lenovo - */ - -/dts-v1/; - -#include "aspeed-g5.dtsi" -#include - -/ { - model = "HR855XG2 BMC"; - compatible = "lenovo,hr855xg2-bmc", "aspeed,ast2500"; - - aliases { - i2c14 = &i2c_riser1; - i2c15 = &i2c_riser2; - i2c16 = &i2c_riser3; - i2c17 = &i2c_M2; - i2c18 = &channel_0; - i2c19 = &channel_1; - i2c20 = &channel_2; - i2c21 = &channel_3; - }; - - chosen { - stdout-path = &uart5; - bootargs = "console=tty0 console=ttyS4,115200 earlyprintk"; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - flash_memory: region@98000000 { - no-map; - reg = <0x98000000 0x00100000>; /* 1M */ - }; - - gfx_memory: framebuffer { - size = <0x01000000>; - alignment = <0x01000000>; - compatible = "shared-dma-pool"; - reusable; - }; - }; - - leds { - compatible = "gpio-leds"; - - heartbeat { - gpios = <&gpio ASPEED_GPIO(C, 7) GPIO_ACTIVE_LOW>; - }; - - fault { - gpios = <&gpio ASPEED_GPIO(G, 3) GPIO_ACTIVE_LOW>; - }; - }; - - iio-hwmon { - compatible = "iio-hwmon"; - io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, - <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>, - <&adc 8>, <&adc 9>, <&adc 10>,<&adc 11>, - <&adc 12>,<&adc 13>,<&adc 14>; - }; - - iio-hwmon-battery { - compatible = "iio-hwmon"; - io-channels = <&adc 15>; - }; - -}; - -&fmc { - status = "okay"; - flash@0 { - status = "okay"; - m25p,fast-read; - label = "bmc"; - spi-max-frequency = <50000000>; -#include "openbmc-flash-layout.dtsi" - }; -}; - -&lpc_ctrl { - status = "okay"; - memory-region = <&flash_memory>; - flash = <&spi1>; -}; - -&lpc_snoop { - status = "okay"; - snoop-ports = <0x80>; -}; - -&uart1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd1_default - &pinctrl_rxd1_default>; -}; - -&uart2 { - /* Rear RS-232 connector */ - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd2_default - &pinctrl_rxd2_default - &pinctrl_nrts2_default - &pinctrl_ndtr2_default - &pinctrl_ndsr2_default - &pinctrl_ncts2_default - &pinctrl_ndcd2_default - &pinctrl_nri2_default>; -}; - -&uart3 { - status = "okay"; -}; - -&uart5 { - status = "okay"; -}; - -&ibt { - status = "okay"; -}; - -&mac0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rmii1_default>; - clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, - <&syscon ASPEED_CLK_MAC1RCLK>; - clock-names = "MACCLK", "RCLK"; - use-ncsi; -}; - -&mac1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; -}; - -&adc{ - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_adc0_default - &pinctrl_adc1_default - &pinctrl_adc2_default - &pinctrl_adc3_default - &pinctrl_adc4_default - &pinctrl_adc5_default - &pinctrl_adc6_default - &pinctrl_adc7_default - &pinctrl_adc8_default - &pinctrl_adc9_default - &pinctrl_adc10_default - &pinctrl_adc11_default - &pinctrl_adc12_default - &pinctrl_adc13_default - &pinctrl_adc14_default - &pinctrl_adc15_default>; -}; - -&i2c0 { - status = "okay"; - - i2c-switch@70 { - compatible = "nxp,pca9545"; - reg = <0x70>; - #address-cells = <1>; - #size-cells = <0>; - - i2c_riser1: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - i2c_riser2: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - i2c_riser3: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - i2c_M2: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - }; -}; - -&i2c1 { - status = "okay"; - bus-frequency = <90000>; - HotSwap@10 { - compatible = "adm1272"; - reg = <0x10>; - }; - - VR@45 { - compatible = "pmbus"; - reg = <0x45>; - }; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c3 { - status = "okay"; - i2c-switch@70 { - compatible = "nxp,pca9546"; - reg = <0x70>; - #address-cells = <1>; - #size-cells = <0>; - - channel_0: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - channel_1: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - channel_2: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - channel_3: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - }; -}; - -&i2c4 { - status = "okay"; -}; - -&i2c5 { - status = "okay"; -}; - -&i2c6 { - status = "okay"; - /* temp1 */ - tmp75@49 { - compatible = "national,lm75"; - reg = <0x49>; - }; - - /* temp2 */ - tmp75@4d { - compatible = "national,lm75"; - reg = <0x4d>; - }; - - eeprom@54 { - compatible = "atmel,24c256"; - reg = <0x54>; - pagesize = <16>; - }; -}; - -&i2c7 { - status = "okay"; -}; - -&i2c8 { - status = "okay"; -}; - -&i2c9 { - status = "okay"; -}; - -&i2c10 { - status = "okay"; -}; - -&i2c11 { - status = "okay"; -}; - -&i2c13 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&uhci { - status = "okay"; -}; - -&gfx { - status = "okay"; - memory-region = <&gfx_memory>; -}; - -&pwm_tacho { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm0_default - &pinctrl_pwm1_default - &pinctrl_pwm2_default - &pinctrl_pwm3_default - &pinctrl_pwm4_default - &pinctrl_pwm5_default - &pinctrl_pwm6_default - &pinctrl_pwm7_default>; - - fan@0 { - reg = <0x00>; - aspeed,fan-tach-ch = /bits/ 8 <0x00>; - }; - - fan@1 { - reg = <0x00>; - aspeed,fan-tach-ch = /bits/ 8 <0x01>; - }; - - fan@2 { - reg = <0x01>; - aspeed,fan-tach-ch = /bits/ 8 <0x02>; - }; - - fan@3 { - reg = <0x01>; - aspeed,fan-tach-ch = /bits/ 8 <0x03>; - }; - - fan@4 { - reg = <0x02>; - aspeed,fan-tach-ch = /bits/ 8 <0x04>; - }; - - fan@5 { - reg = <0x02>; - aspeed,fan-tach-ch = /bits/ 8 <0x05>; - }; - - fan@6 { - reg = <0x03>; - aspeed,fan-tach-ch = /bits/ 8 <0x06>; - }; - - fan@7 { - reg = <0x03>; - aspeed,fan-tach-ch = /bits/ 8 <0x07>; - }; - - fan@8 { - reg = <0x04>; - aspeed,fan-tach-ch = /bits/ 8 <0x08>; - }; - - fan@9 { - reg = <0x04>; - aspeed,fan-tach-ch = /bits/ 8 <0x09>; - }; - - fan@10 { - reg = <0x05>; - aspeed,fan-tach-ch = /bits/ 8 <0x0a>; - }; - - fan@11 { - reg = <0x05>; - aspeed,fan-tach-ch = /bits/ 8 <0x0b>; - }; - - fan@12 { - reg = <0x06>; - aspeed,fan-tach-ch = /bits/ 8 <0x0c>; - }; - - fan@13 { - reg = <0x06>; - aspeed,fan-tach-ch = /bits/ 8 <0x0d>; - }; - - fan@14 { - reg = <0x07>; - aspeed,fan-tach-ch = /bits/ 8 <0x0e>; - }; - - fan@15 { - reg = <0x07>; - aspeed,fan-tach-ch = /bits/ 8 <0x0f>; - }; - - fan@16 { - reg = <0x07>; - aspeed,fan-tach-ch = /bits/ 8 <0x0f>; - }; -}; - -&gpio { - - pin_gpio_a1 { - gpio-hog; - gpios = ; - output-high; - line-name = "BMC_EMMC_RST_N"; - }; - - pin_gpio_a3 { - gpio-hog; - gpios = ; - output-high; - line-name = "PCH_PWROK_BMC_FPGA"; - }; - - pin_gpio_b5 { - gpio-hog; - gpios = ; - output-high; - line-name = "IRQ_BMC_PCH_SMI_LPC_N"; - }; - - pin_gpio_b7 { - gpio-hog; - gpios = ; - output-low; - line-name = "CPU_SM_WP"; - }; - - pin_gpio_e0 { - gpio-hog; - gpios = ; - input; - line-name = "PDB_PSU_SEL"; - }; - - pin_gpio_e2 { - gpio-hog; - gpios = ; - output-high; - line-name = "LOCATOR_LED_N"; - }; - - pin_gpio_e5 { - gpio-hog; - gpios = ; - output-high; - line-name = "FM_BMC_DBP_PRESENT_R1_N"; - }; - - pin_gpio_e6 { - gpio-hog; - gpios = ; - output-high; - line-name = "BMC_ME_SECURITY_OVERRIDE_N"; - }; - - pin_gpio_f0 { - gpio-hog; - gpios = ; - output-high; - line-name = "IRQ_BMC_PCH_NMI_R"; - }; - - pin_gpio_f1 { - gpio-hog; - gpios = ; - input; - line-name = "CPU2_PROCDIS_BMC_N"; - }; - - pin_gpio_f2 { - gpio-hog; - gpios = ; - output-high; - line-name = "RM_THROTTLE_EN_N"; - }; - - pin_gpio_f3 { - gpio-hog; - gpios = ; - output-low; - line-name = "FM_PMBUS_ALERT_B_EN"; - }; - - pin_gpio_f4 { - gpio-hog; - gpios = ; - output-high; - line-name = "BMC_FORCE_NM_THROTTLE_N"; - }; - - pin_gpio_f6 { - gpio-hog; - gpios = ; - output-high; - line-name = "FM_BMC_CPU_PWR_DEBUG_N"; - }; - - pin_gpio_g7 { - gpio-hog; - gpios = ; - output-high; - line-name = "BMC_PCIE_I2C_MUX_RST_N"; - }; - - pin_gpio_h6 { - gpio-hog; - gpios = ; - output-high; - line-name = "FM_BMC_DBP_PRESENT_R2_N"; - }; - - pin_gpio_i3 { - gpio-hog; - gpios = ; - output-high; - line-name = "SPI_BMC_BIOS_WP_N"; - }; - - pin_gpio_j1 { - gpio-hog; - gpios = ; - output-high; - line-name = "BMC_USB_SEL"; - }; - - pin_gpio_j2 { - gpio-hog; - gpios = ; - output-high; - line-name = "PDB_SMB_RST_N"; - }; - - pin_gpio_j3 { - gpio-hog; - gpios = ; - output-high; - line-name = "SPI_BMC_BIOS_HOLD_N"; - }; - - pin_gpio_l0 { - gpio-hog; - gpios = ; - output-high; - line-name = "PDB_FAN_TACH_SEL"; - }; - - pin_gpio_l1 { - gpio-hog; - gpios = ; - output-high; - line-name = "SYS_RESET_BMC_FPGA_N"; - }; - - pin_gpio_l4 { - gpio-hog; - gpios = ; - output-high; - line-name = "FM_EFUSE_FAN_G1_EN"; - }; - - pin_gpio_l5 { - gpio-hog; - gpios = ; - output-high; - line-name = "FM_EFUSE_FAN_G2_EN"; - }; - - pin_gpio_r6 { - gpio-hog; - gpios = ; - input; - line-name = "CPU3_PROCDIS_BMC_N"; - }; - - pin_gpio_r7 { - gpio-hog; - gpios = ; - input; - line-name = "CPU4_PROCDIS_BMC_N"; - }; - - pin_gpio_s1 { - gpio-hog; - gpios = ; - output-low; - line-name = "DBP_SYSPWROK_BMC"; - }; - - pin_gpio_s2 { - gpio-hog; - gpios = ; - output-high; - line-name = "PCH_RST_RSMRST_N"; - }; - - pin_gpio_s6 { - gpio-hog; - gpios = ; - output-high; - line-name = "BMC_HW_STRAP_5"; - }; - - pin_gpio_z3 { - gpio-hog; - gpios = ; - output-high; - line-name = "FM_BMC_PCH_SCI_LPC_N"; - }; - - pin_gpio_aa0 { - gpio-hog; - gpios = ; - output-low; - line-name = "FW_PSU_ALERT_EN_N"; - }; - - pin_gpio_aa4 { - gpio-hog; - gpios = ; - output-high; - line-name = "DBP_CPU_PREQ_N"; - }; - - pin_gpio_ab3 { - gpio-hog; - gpios = ; - output-low; - line-name = "BMC_WDTRST"; - }; - - pin_gpio_ac6 { - gpio-hog; - gpios = ; - output-high; - line-name = "ESPI_BMC_ALERT_N"; - }; - -}; diff --git a/sys/gnu/dts/arm/aspeed-bmc-microsoft-olympus.dts b/sys/gnu/dts/arm/aspeed-bmc-microsoft-olympus.dts deleted file mode 100644 index 73319917cb7..00000000000 --- a/sys/gnu/dts/arm/aspeed-bmc-microsoft-olympus.dts +++ /dev/null @@ -1,207 +0,0 @@ -//SPDX-License-Identifier: GPL-2.0+ - -/dts-v1/; - -#include "aspeed-g4.dtsi" -#include - -/ { - model = "Olympus BMC"; - compatible = "microsoft,olympus-bmc", "aspeed,ast2400"; - - chosen { - stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlyprintk"; - }; - - memory@40000000 { - reg = <0x40000000 0x20000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - vga_memory: framebuffer@5f000000 { - no-map; - reg = <0x5f000000 0x01000000>; /* 16M */ - }; - }; - - leds { - compatible = "gpio-leds"; - - bmc_heartbeat { - gpios = <&gpio ASPEED_GPIO(B, 0) GPIO_ACTIVE_LOW>; - }; - - power_green { - gpios = <&gpio ASPEED_GPIO(U, 2) GPIO_ACTIVE_HIGH>; - }; - - power_amber { - gpios = <&gpio ASPEED_GPIO(U, 3) GPIO_ACTIVE_HIGH>; - }; - - identify { - gpios = <&gpio ASPEED_GPIO(Q, 5) GPIO_ACTIVE_LOW>; - }; - - fault { - gpios = <&gpio ASPEED_GPIO(A, 1) GPIO_ACTIVE_LOW>; - }; - }; - - - iio-hwmon { - compatible = "iio-hwmon"; - io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, - <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>; - }; -}; - -&adc { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_adc0_default - &pinctrl_adc1_default - &pinctrl_adc2_default - &pinctrl_adc3_default - &pinctrl_adc4_default - &pinctrl_adc5_default - &pinctrl_adc6_default - &pinctrl_adc7_default>; -}; - -&fmc { - status = "okay"; - - flash@0 { - status = "okay"; - m25p,fast-read; - label = "bmc"; -#include "openbmc-flash-layout.dtsi" - }; -}; - -&spi { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1_default>; - - flash@0 { - status = "okay"; - m25p,fast-read; - label = "pnor"; - }; -}; - -&uart5 { - status = "okay"; -}; - -&mac0 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rgmii1_default &pinctrl_mdio1_default>; -}; - -&i2c0 { - status = "okay"; -}; - -&i2c1 { - status = "okay"; - - tmp421@4c { - compatible = "ti,tmp421"; - reg = <0x4c>; - }; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c3 { - status = "okay"; -}; - -&i2c4 { - status = "okay"; - clock-frequency = <100000>; -}; - -&i2c5 { - status = "okay"; -}; - -&i2c6 { - status = "okay"; - - tmp421@4c { - compatible = "ti,tmp421"; - reg = <0x4c>; - }; -}; - -&i2c7 { - status = "okay"; -}; - -&vuart { - status = "okay"; -}; - -&wdt2 { - status = "okay"; -}; - -&lpc_ctrl { - status = "okay"; -}; - -&pwm_tacho { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm0_default - &pinctrl_pwm1_default - &pinctrl_pwm2_default - &pinctrl_pwm3_default - &pinctrl_pwm4_default - &pinctrl_pwm5_default - &pinctrl_pwm6_default>; - - fan@0 { - reg = <0x00>; - aspeed,fan-tach-ch = /bits/ 8 <0x00>; - }; - - fan@1 { - reg = <0x01>; - aspeed,fan-tach-ch = /bits/ 8 <0x01>; - }; - - fan@2 { - reg = <0x02>; - aspeed,fan-tach-ch = /bits/ 8 <0x02>; - }; - - fan@3 { - reg = <0x03>; - aspeed,fan-tach-ch = /bits/ 8 <0x03>; - }; - - fan@4 { - reg = <0x04>; - aspeed,fan-tach-ch = /bits/ 8 <0x04>; - }; - - fan@5 { - reg = <0x05>; - aspeed,fan-tach-ch = /bits/ 8 <0x05>; - }; - -}; diff --git a/sys/gnu/dts/arm/aspeed-bmc-opp-lanyang.dts b/sys/gnu/dts/arm/aspeed-bmc-opp-lanyang.dts deleted file mode 100644 index 42b37a20424..00000000000 --- a/sys/gnu/dts/arm/aspeed-bmc-opp-lanyang.dts +++ /dev/null @@ -1,329 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// Copyright (c) 2018 Inventec Corporation -/dts-v1/; - -#include "aspeed-g5.dtsi" -#include - -/ { - model = "Lanyang BMC"; - compatible = "inventec,lanyang-bmc", "aspeed,ast2500"; - - chosen { - stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlyprintk"; - }; - - memory@80000000 { - reg = <0x80000000 0x40000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - flash_memory: region@98000000 { - no-map; - reg = <0x98000000 0x04000000>; /* 64M */ - }; - }; - - leds { - compatible = "gpio-leds"; - - sys_boot_status { - label = "System_boot_status"; - gpios = <&gpio ASPEED_GPIO(B, 6) GPIO_ACTIVE_LOW>; - }; - - attention { - label = "Attention_locator"; - gpios = <&gpio ASPEED_GPIO(B, 7) GPIO_ACTIVE_HIGH>; - }; - - plt_fault { - label = "Platform_fault"; - gpios = <&gpio ASPEED_GPIO(B, 1) GPIO_ACTIVE_HIGH>; - }; - - hdd_fault { - label = "Onboard_drive_fault"; - gpios = <&gpio ASPEED_GPIO(B, 3) GPIO_ACTIVE_HIGH>; - }; - bmc_err { - lable = "BMC_fault"; - gpios = <&gpio ASPEED_GPIO(H, 6) GPIO_ACTIVE_HIGH>; - }; - - sys_err { - lable = "Sys_fault"; - gpios = <&gpio ASPEED_GPIO(H, 7) GPIO_ACTIVE_HIGH>; - }; - }; - - fsi: gpio-fsi { - compatible = "fsi-master-gpio", "fsi-master"; - #address-cells = <2>; - #size-cells = <0>; - - clock-gpios = <&gpio ASPEED_GPIO(J, 0) GPIO_ACTIVE_HIGH>; - data-gpios = <&gpio ASPEED_GPIO(J, 1) GPIO_ACTIVE_HIGH>; - trans-gpios = <&gpio ASPEED_GPIO(D, 5) GPIO_ACTIVE_HIGH>; - enable-gpios = <&gpio ASPEED_GPIO(D, 0) GPIO_ACTIVE_HIGH>; - mux-gpios = <&gpio ASPEED_GPIO(H, 2) GPIO_ACTIVE_HIGH>; - }; - - iio-hwmon { - compatible = "iio-hwmon"; - io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, - <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>, - <&adc 8>, <&adc 9>, <&adc 10>, <&adc 11>, - <&adc 13>, <&adc 14>, <&adc 15>; - }; - - iio-hwmon-battery { - compatible = "iio-hwmon"; - io-channels = <&adc 12>; - }; -}; - -&pwm_tacho { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default - &pinctrl_pwm2_default &pinctrl_pwm3_default>; - - fan@0 { - reg = <0x00>; - aspeed,fan-tach-ch = /bits/ 8 <0x00>; - }; - - fan@1 { - reg = <0x01>; - aspeed,fan-tach-ch = /bits/ 8 <0x01>; - }; - - fan@2 { - reg = <0x02>; - aspeed,fan-tach-ch = /bits/ 8 <0x02>; - }; - - fan@3 { - reg = <0x03>; - aspeed,fan-tach-ch = /bits/ 8 <0x03>; - }; -}; - -&fmc { - status = "okay"; - flash@0 { - status = "okay"; - m25p,fast-read; - label = "bmc"; -#include "openbmc-flash-layout.dtsi" - }; -}; - -&spi1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1_default>; - - flash@0 { - status = "okay"; - label = "pnor"; - m25p,fast-read; - }; -}; - -&spi2 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi2ck_default - &pinctrl_spi2cs0_default - &pinctrl_spi2cs1_default - &pinctrl_spi2miso_default - &pinctrl_spi2mosi_default>; - - flash@0 { - status = "okay"; - }; -}; - -&uart1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd1_default - &pinctrl_rxd1_default>; -}; - -&lpc_ctrl { - status = "okay"; - memory-region = <&flash_memory>; - flash = <&spi1>; -}; - -&lpc_snoop { - status = "okay"; - snoop-ports = <0x80>; -}; - -&uart5 { - status = "okay"; -}; - -&mac0 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rmii1_default>; - clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, - <&syscon ASPEED_CLK_MAC1RCLK>; - clock-names = "MACCLK", "RCLK"; - use-ncsi; -}; - -&mac1 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; -}; - -&i2c0 { - status = "okay"; - - eeprom@55 { - compatible = "atmel,24c64"; - reg = <0x55>; - pagesize = <32>; - }; - - rtc@68 { - compatible = "nxp,pcf8523"; - reg = <0x68>; - }; - - tmp75@48 { - compatible = "ti,tmp75"; - reg = <0x48>; - }; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c3 { - status = "okay"; -}; - -&i2c4 { - status = "okay"; -}; - -&i2c5 { - status = "okay"; -}; - -&i2c6 { - status = "okay"; -}; - -&i2c7 { - status = "okay"; -}; - -&i2c8 { - status = "okay"; -}; - -&i2c9 { - status = "okay"; -}; - -&i2c10 { - status = "okay"; -}; - -&i2c11 { - status = "okay"; -}; - -&vuart { - status = "okay"; -}; - -&gfx { - status = "okay"; -}; - -&pinctrl { - aspeed,external-nodes = <&gfx &lhc>; -}; - -&gpio { - pin_gpio_b0 { - gpio-hog; - gpios = ; - output-high; - line-name = "BMC_HDD1_PWR_EN"; - }; - - pin_gpio_b5 { - gpio-hog; - gpios = ; - input; - line-name = "BMC_USB1_OCI2"; - }; - - pin_gpio_h5 { - gpio-hog; - gpios = ; - output-high; - line-name = "BMC_CP0_PERST_ENABLE_R"; - }; - - pin_gpio_z2 { - gpio-hog; - gpios = ; - output-high; - line-name = "RST_PCA9546_U177_N"; - }; - - pin_gpio_aa6 { - gpio-hog; - gpios = ; - output-high; - line-name = "BMC_CP0_RESET_N"; - }; - - pin_gpio_aa7 { - gpio-hog; - gpios = ; - output-high; - line-name = "BMC_TPM_RESET_N"; - }; - - pin_gpio_ab0 { - gpio-hog; - gpios = ; - output-high; - line-name = "BMC_USB_PWRON_N"; - }; -}; - -&ibt { - status = "okay"; -}; - -&adc { - status = "okay"; -}; - -#include "ibm-power9-dual.dtsi" diff --git a/sys/gnu/dts/arm/aspeed-bmc-opp-mihawk.dts b/sys/gnu/dts/arm/aspeed-bmc-opp-mihawk.dts deleted file mode 100644 index f7e935ede91..00000000000 --- a/sys/gnu/dts/arm/aspeed-bmc-opp-mihawk.dts +++ /dev/null @@ -1,921 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/dts-v1/; -#include "aspeed-g5.dtsi" -#include -#include - -/ { - model = "Mihawk BMC"; - compatible = "ibm,mihawk-bmc", "aspeed,ast2500"; - - - chosen { - stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlyprintk"; - }; - - memory@80000000 { - reg = <0x80000000 0x20000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - flash_memory: region@98000000 { - no-map; - reg = <0x98000000 0x04000000>; /* 64M */ - }; - - gfx_memory: framebuffer { - size = <0x01000000>; - alignment = <0x01000000>; - compatible = "shared-dma-pool"; - reusable; - }; - - video_engine_memory: jpegbuffer { - size = <0x02000000>; - alignment = <0x01000000>; - compatible = "shared-dma-pool"; - reusable; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - air-water { - label = "air-water"; - gpios = <&gpio ASPEED_GPIO(F, 6) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - checkstop { - label = "checkstop"; - gpios = <&gpio ASPEED_GPIO(J, 2) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - ps0-presence { - label = "ps0-presence"; - gpios = <&gpio ASPEED_GPIO(Z, 2) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - ps1-presence { - label = "ps1-presence"; - gpios = <&gpio ASPEED_GPIO(Z, 0) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - id-button { - label = "id-button"; - gpios = <&gpio ASPEED_GPIO(F, 1) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - poll-interval = <1000>; - - fan0-presence { - label = "fan0-presence"; - gpios = <&pca9552 9 GPIO_ACTIVE_LOW>; - linux,code = <9>; - }; - - fan1-presence { - label = "fan1-presence"; - gpios = <&pca9552 10 GPIO_ACTIVE_LOW>; - linux,code = <10>; - }; - - fan2-presence { - label = "fan2-presence"; - gpios = <&pca9552 11 GPIO_ACTIVE_LOW>; - linux,code = <11>; - }; - - fan3-presence { - label = "fan3-presence"; - gpios = <&pca9552 12 GPIO_ACTIVE_LOW>; - linux,code = <12>; - }; - - fan4-presence { - label = "fan4-presence"; - gpios = <&pca9552 13 GPIO_ACTIVE_LOW>; - linux,code = <13>; - }; - - fan5-presence { - label = "fan5-presence"; - gpios = <&pca9552 14 GPIO_ACTIVE_LOW>; - linux,code = <14>; - }; - }; - - leds { - compatible = "gpio-leds"; - - fault { - retain-state-shutdown; - default-state = "keep"; - gpios = <&gpio ASPEED_GPIO(AA, 0) GPIO_ACTIVE_LOW>; - }; - - power { - retain-state-shutdown; - default-state = "keep"; - gpios = <&gpio ASPEED_GPIO(AA, 1) GPIO_ACTIVE_LOW>; - }; - - rear-id { - retain-state-shutdown; - default-state = "keep"; - gpios = <&gpio ASPEED_GPIO(AA, 2) GPIO_ACTIVE_LOW>; - }; - - rear-g { - retain-state-shutdown; - default-state = "keep"; - gpios = <&gpio ASPEED_GPIO(AA, 4) GPIO_ACTIVE_LOW>; - }; - - rear-ok { - retain-state-shutdown; - default-state = "keep"; - gpios = <&gpio ASPEED_GPIO(Y, 0) GPIO_ACTIVE_LOW>; - }; - - fan0 { - retain-state-shutdown; - default-state = "keep"; - gpios = <&pca9552 0 GPIO_ACTIVE_LOW>; - }; - - fan1 { - retain-state-shutdown; - default-state = "keep"; - gpios = <&pca9552 1 GPIO_ACTIVE_LOW>; - }; - - fan2 { - retain-state-shutdown; - default-state = "keep"; - gpios = <&pca9552 2 GPIO_ACTIVE_LOW>; - }; - - fan3 { - retain-state-shutdown; - default-state = "keep"; - gpios = <&pca9552 3 GPIO_ACTIVE_LOW>; - }; - - fan4 { - retain-state-shutdown; - default-state = "keep"; - gpios = <&pca9552 4 GPIO_ACTIVE_LOW>; - }; - - fan5 { - retain-state-shutdown; - default-state = "keep"; - gpios = <&pca9552 5 GPIO_ACTIVE_LOW>; - }; - }; - - fsi: gpio-fsi { - compatible = "fsi-master-gpio", "fsi-master"; - #address-cells = <2>; - #size-cells = <0>; - no-gpio-delays; - - clock-gpios = <&gpio ASPEED_GPIO(E, 6) GPIO_ACTIVE_HIGH>; - data-gpios = <&gpio ASPEED_GPIO(E, 7) GPIO_ACTIVE_HIGH>; - mux-gpios = <&gpio ASPEED_GPIO(E, 5) GPIO_ACTIVE_HIGH>; - enable-gpios = <&gpio ASPEED_GPIO(D, 0) GPIO_ACTIVE_HIGH>; - trans-gpios = <&gpio ASPEED_GPIO(R, 2) GPIO_ACTIVE_HIGH>; - }; - iio-hwmon-12v { - compatible = "iio-hwmon"; - io-channels = <&adc 0>; - }; - - iio-hwmon-5v { - compatible = "iio-hwmon"; - io-channels = <&adc 1>; - }; - - iio-hwmon-3v { - compatible = "iio-hwmon"; - io-channels = <&adc 2>; - }; - - iio-hwmon-vdd0 { - compatible = "iio-hwmon"; - io-channels = <&adc 3>; - }; - - iio-hwmon-vdd1 { - compatible = "iio-hwmon"; - io-channels = <&adc 4>; - }; - - iio-hwmon-vcs0 { - compatible = "iio-hwmon"; - io-channels = <&adc 5>; - }; - - iio-hwmon-vcs1 { - compatible = "iio-hwmon"; - io-channels = <&adc 6>; - }; - - iio-hwmon-vdn0 { - compatible = "iio-hwmon"; - io-channels = <&adc 7>; - }; - - iio-hwmon-vdn1 { - compatible = "iio-hwmon"; - io-channels = <&adc 8>; - }; - - iio-hwmon-vio0 { - compatible = "iio-hwmon"; - io-channels = <&adc 9>; - }; - - iio-hwmon-vio1 { - compatible = "iio-hwmon"; - io-channels = <&adc 10>; - }; - - iio-hwmon-vddra { - compatible = "iio-hwmon"; - io-channels = <&adc 11>; - }; - - iio-hwmon-battery { - compatible = "iio-hwmon"; - io-channels = <&adc 12>; - }; - - iio-hwmon-vddrb { - compatible = "iio-hwmon"; - io-channels = <&adc 13>; - }; - - iio-hwmon-vddrc { - compatible = "iio-hwmon"; - io-channels = <&adc 14>; - }; - - iio-hwmon-vddrd { - compatible = "iio-hwmon"; - io-channels = <&adc 15>; - }; -}; - -&pwm_tacho { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default - &pinctrl_pwm2_default &pinctrl_pwm3_default - &pinctrl_pwm4_default &pinctrl_pwm5_default>; - - fan@0 { - reg = <0x00>; - aspeed,fan-tach-ch = /bits/ 8 <0x00>; - }; - - fan@1 { - reg = <0x01>; - aspeed,fan-tach-ch = /bits/ 8 <0x01>; - }; - - fan@2 { - reg = <0x02>; - aspeed,fan-tach-ch = /bits/ 8 <0x02>; - }; - - fan@3 { - reg = <0x03>; - aspeed,fan-tach-ch = /bits/ 8 <0x03>; - }; - - fan@4 { - reg = <0x04>; - aspeed,fan-tach-ch = /bits/ 8 <0x04>; - }; - - fan@5 { - reg = <0x05>; - aspeed,fan-tach-ch = /bits/ 8 <0x05>; - }; - - fan@6 { - reg = <0x00>; - aspeed,fan-tach-ch = /bits/ 8 <0x06>; - }; - - fan@7 { - reg = <0x01>; - aspeed,fan-tach-ch = /bits/ 8 <0x07>; - }; - - fan@8 { - reg = <0x02>; - aspeed,fan-tach-ch = /bits/ 8 <0x08>; - }; - - fan@9 { - reg = <0x03>; - aspeed,fan-tach-ch = /bits/ 8 <0x09>; - }; - - fan@10 { - reg = <0x04>; - aspeed,fan-tach-ch = /bits/ 8 <0x0a>; - }; - - fan@11 { - reg = <0x05>; - aspeed,fan-tach-ch = /bits/ 8 <0x0b>; - }; -}; - -&fmc { - status = "okay"; - flash@0 { - status = "okay"; - label = "bmc"; - m25p,fast-read; - spi-max-frequency = <50000000>; - partitions { - #address-cells = < 1 >; - #size-cells = < 1 >; - compatible = "fixed-partitions"; - u-boot@0 { - reg = < 0 0x60000 >; - label = "u-boot"; - }; - u-boot-env@60000 { - reg = < 0x60000 0x20000 >; - label = "u-boot-env"; - }; - obmc-ubi@80000 { - reg = < 0x80000 0x1F80000 >; - label = "obmc-ubi"; - }; - }; - }; - flash@1 { - status = "okay"; - label = "alt-bmc"; - m25p,fast-read; - spi-max-frequency = <50000000>; - partitions { - #address-cells = < 1 >; - #size-cells = < 1 >; - compatible = "fixed-partitions"; - u-boot@0 { - reg = < 0 0x60000 >; - label = "alt-u-boot"; - }; - u-boot-env@60000 { - reg = < 0x60000 0x20000 >; - label = "alt-u-boot-env"; - }; - obmc-ubi@80000 { - reg = < 0x80000 0x1F80000 >; - label = "alt-obmc-ubi"; - }; - }; - }; -}; - -&spi1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1_default>; - - flash@0 { - status = "okay"; - label = "pnor"; - m25p,fast-read; - spi-max-frequency = <100000000>; - }; -}; - -&lpc_ctrl { - status = "okay"; - memory-region = <&flash_memory>; - flash = <&spi1>; -}; - -&uart1 { - /* Rear RS-232 connector */ - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd1_default - &pinctrl_rxd1_default - &pinctrl_nrts1_default - &pinctrl_ndtr1_default - &pinctrl_ndsr1_default - &pinctrl_ncts1_default - &pinctrl_ndcd1_default - &pinctrl_nri1_default>; -}; - -&uart2 { - /* APSS */ - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd2_default &pinctrl_rxd2_default>; -}; - -&uart5 { - status = "okay"; -}; - -&mac0 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rmii1_default>; - clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, - <&syscon ASPEED_CLK_MAC1RCLK>; - clock-names = "MACCLK", "RCLK"; - use-ncsi; -}; - -&mac1 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; -}; - -&i2c0 { - status = "disabled"; -}; - -&i2c1 { - status = "disabled"; -}; - -&i2c2 { - status = "okay"; - - /* SAMTEC P0 */ - /* SAMTEC P1 */ - -}; - -&i2c3 { - status = "okay"; - - /* APSS */ - /* CPLD */ - - /* PCA9516 (repeater) -> - * CLK Buffer 9FGS9092 - * CLK Buffer 9DBL0651BKILFT - * CLK Buffer 9DBL0651BKILFT - * Power Supply 0 - * Power Supply 1 - * PCA 9552 LED - */ - - power-supply@58 { - compatible = "ibm,cffps1"; - reg = <0x58>; - }; - - power-supply@5b { - compatible = "ibm,cffps1"; - reg = <0x5b>; - }; - - pca9552: pca9552@60 { - compatible = "nxp,pca9552"; - reg = <0x60>; - #address-cells = <1>; - #size-cells = <0>; - gpio-controller; - #gpio-cells = <2>; - - gpio@0 { - reg = <0>; - type = ; - }; - gpio@1 { - reg = <1>; - type = ; - }; - gpio@2 { - reg = <2>; - type = ; - }; - gpio@3 { - reg = <3>; - type = ; - }; - gpio@4 { - reg = <4>; - type = ; - }; - gpio@5 { - reg = <5>; - type = ; - }; - gpio@6 { - reg = <6>; - type = ; - }; - gpio@7 { - reg = <7>; - type = ; - }; - gpio@8 { - reg = <8>; - type = ; - }; - gpio@9 { - reg = <9>; - type = ; - }; - gpio@10 { - reg = <10>; - type = ; - }; - gpio@11 { - reg = <11>; - type = ; - }; - gpio@12 { - reg = <12>; - type = ; - }; - gpio@13 { - reg = <13>; - type = ; - }; - gpio@14 { - reg = <14>; - type = ; - }; - gpio@15 { - reg = <15>; - type = ; - }; - - }; - -}; - -&i2c4 { - status = "okay"; - - /* CP0 VDD & VCS : IR35221 */ - /* CP0 VDN : IR35221 */ - /* CP0 VIO : IR38064 */ - /* CP0 VDDR : PXM1330 */ - - ir35221@70 { - compatible = "infineon,ir35221"; - reg = <0x70>; - }; - - ir35221@72 { - compatible = "infineon,ir35221"; - reg = <0x72>; - }; - -}; - -&i2c5 { - status = "okay"; - - /* CP0 VDD & VCS : IR35221 */ - /* CP0 VDN : IR35221 */ - /* CP0 VIO : IR38064 */ - /* CP0 VDDR : PXM1330 */ - - ir35221@70 { - compatible = "infineon,ir35221"; - reg = <0x70>; - }; - - ir35221@72 { - compatible = "infineon,ir35221"; - reg = <0x72>; - }; - -}; - -&i2c6 { - status = "okay"; - - /* pca9548 -> NVMe1 to 8 */ - - pca9548@70 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x70>; - }; - -}; - -&i2c7 { - status = "okay"; - - /* pca9548 -> NVMe9 to 16 */ - - pca9548@70 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x70>; - }; - -}; - -&i2c8 { - status = "okay"; - - eeprom@50 { - compatible = "atmel,24c64"; - reg = <0x50>; - }; -}; - -&i2c9 { - status = "okay"; - - /* pca9545 Riser -> - * PCIe x8 Slot3 - * PCIe x16 slot4 - * PCIe x8 slot5 - * I2C BMC RISER PCA9554 - * BMC SCL/SDA PCA9554 - * PCA9554 - */ - - /* pca9545 -> - * PCIe x16 Slot1 - * PCIe x8 slot2 - * PEX8748 - */ - - pca9545riser@70 { - compatible = "nxp,pca9545"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x70>; - - i2c-mux-idle-disconnect; - interrupt-controller; - #interrupt-cells = <2>; - }; - - pca9545@71 { - compatible = "nxp,pca9545"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x71>; - - i2c-mux-idle-disconnect; - interrupt-controller; - #interrupt-cells = <2>; - }; -}; - -&i2c10 { - status = "okay"; - - /* pca9545 Riser -> - * PCIe x8 Slot8 - * PCIe x16 slot9 - * PCIe x8 slot10 - * I2C BMC RISER PCA9554 - * BMC SCL/SDA PCA9554 - * PCA9554 - */ - - /* pca9545 -> - * PCIe x16 Slot1 - * PCIe x8 slot2 - * PEX8748 - */ - - pca9545riser@70 { - compatible = "nxp,pca9545"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x70>; - - i2c-mux-idle-disconnect; - interrupt-controller; - #interrupt-cells = <2>; - }; - - pca9545@71 { - compatible = "nxp,pca9545"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x71>; - - i2c-mux-idle-disconnect; - interrupt-controller; - #interrupt-cells = <2>; - }; -}; - -&i2c11 { - status = "okay"; - - /* TPM */ - /* RTC RX8900CE */ - /* FPGA for power sequence */ - /* TMP275A */ - /* TMP275A */ - /* EMC1462 */ - - tpm@57 { - compatible = "infineon,slb9645tt"; - reg = <0x57>; - }; - - rtc@32 { - compatible = "epson,rx8900"; - reg = <0x32>; - }; - - tmp275@48 { - compatible = "ti,tmp275"; - reg = <0x48>; - }; - - tmp275@49 { - compatible = "ti,tmp275"; - reg = <0x49>; - }; - - /* chip emc1462 use emc1403 driver */ - emc1403@4c { - compatible = "smsc,emc1403"; - reg = <0x4c>; - }; - -}; - -&i2c12 { - status = "okay"; - - /* pca9545 -> - * SAS BP1 - * SAS BP2 - * NVMe BP - * M.2 riser - */ - - pca9545@70 { - compatible = "nxp,pca9545"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x70>; - - interrupt-controller; - #interrupt-cells = <2>; - - i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - eeprom@50 { - compatible = "atmel,24c64"; - reg = <0x50>; - }; - }; - - i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - eeprom@50 { - compatible = "atmel,24c64"; - reg = <0x50>; - }; - }; - - i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - - eeprom@50 { - compatible = "atmel,24c64"; - reg = <0x50>; - }; - }; - - i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - - tmp275@48 { - compatible = "ti,tmp275"; - reg = <0x48>; - }; - }; - - }; - -}; - -&i2c13 { - status = "okay"; - - /* pca9548 -> - * NVMe BP - * NVMe HDD17 to 24 - */ - - pca9548@70 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x70>; - }; -}; - -&vuart { - status = "okay"; -}; - -&gfx { - status = "okay"; - memory-region = <&gfx_memory>; -}; - -&adc { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_adc0_default - &pinctrl_adc1_default - &pinctrl_adc2_default - &pinctrl_adc3_default - &pinctrl_adc4_default - &pinctrl_adc5_default - &pinctrl_adc6_default - &pinctrl_adc7_default - &pinctrl_adc8_default - &pinctrl_adc9_default - &pinctrl_adc10_default - &pinctrl_adc11_default - &pinctrl_adc12_default - &pinctrl_adc13_default - &pinctrl_adc14_default - &pinctrl_adc15_default>; -}; - -&wdt1 { - aspeed,reset-type = "none"; - aspeed,external-signal; - aspeed,ext-push-pull; - aspeed,ext-active-high; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdtrst1_default>; -}; - -&wdt2 { - aspeed,alt-boot; -}; - -&ibt { - status = "okay"; -}; - -&vhub { - status = "okay"; -}; - -&video { - status = "okay"; - memory-region = <&video_engine_memory>; -}; - -#include "ibm-power9-dual.dtsi" - diff --git a/sys/gnu/dts/arm/aspeed-bmc-opp-palmetto.dts b/sys/gnu/dts/arm/aspeed-bmc-opp-palmetto.dts deleted file mode 100644 index eb4e93a57ff..00000000000 --- a/sys/gnu/dts/arm/aspeed-bmc-opp-palmetto.dts +++ /dev/null @@ -1,373 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/dts-v1/; - -#include "aspeed-g4.dtsi" -#include - -/ { - model = "Palmetto BMC"; - compatible = "tyan,palmetto-bmc", "aspeed,ast2400"; - - chosen { - stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlyprintk"; - }; - - memory@40000000 { - reg = <0x40000000 0x20000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - vga_memory: framebuffer@5f000000 { - no-map; - reg = <0x5f000000 0x01000000>; /* 16M */ - }; - - coldfire_memory: codefire_memory@5ee00000 { - reg = <0x5ee00000 0x00200000>; - no-map; - }; - - flash_memory: region@5c000000 { - no-map; - reg = <0x5C000000 0x02000000>; /* 32MB */ - }; - }; - - leds { - compatible = "gpio-leds"; - - heartbeat { - gpios = <&gpio ASPEED_GPIO(R, 4) GPIO_ACTIVE_LOW>; - }; - - power { - gpios = <&gpio ASPEED_GPIO(R, 5) GPIO_ACTIVE_LOW>; - }; - - identify { - gpios = <&gpio ASPEED_GPIO(A, 2) GPIO_ACTIVE_LOW>; - }; - }; - - fsi: gpio-fsi { - compatible = "aspeed,ast2400-cf-fsi-master", "fsi-master"; - #address-cells = <2>; - #size-cells = <0>; - - memory-region = <&coldfire_memory>; - aspeed,sram = <&sram>; - aspeed,cvic = <&cvic>; - - clock-gpios = <&gpio ASPEED_GPIO(A, 4) GPIO_ACTIVE_HIGH>; - data-gpios = <&gpio ASPEED_GPIO(A, 5) GPIO_ACTIVE_HIGH>; - mux-gpios = <&gpio ASPEED_GPIO(A, 6) GPIO_ACTIVE_HIGH>; - enable-gpios = <&gpio ASPEED_GPIO(D, 0) GPIO_ACTIVE_HIGH>; - trans-gpios = <&gpio ASPEED_GPIO(H, 6) GPIO_ACTIVE_HIGH>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - checkstop { - label = "checkstop"; - gpios = <&gpio ASPEED_GPIO(P, 5) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; -}; - -&fmc { - status = "okay"; - flash@0 { - status = "okay"; - m25p,fast-read; - label = "bmc"; - spi-max-frequency = <50000000>; -#include "openbmc-flash-layout.dtsi" - }; -}; - -&spi { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1debug_default>; - - flash@0 { - status = "okay"; - m25p,fast-read; - spi-max-frequency = <50000000>; - label = "pnor"; - }; -}; - -&pinctrl { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flbusy_default &pinctrl_flwp_default - - &pinctrl_vgahs_default &pinctrl_vgavs_default - &pinctrl_ddcclk_default &pinctrl_ddcdat_default>; -}; - -&uart1 { - /* Rear RS-232 connector */ - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd1_default - &pinctrl_rxd1_default - &pinctrl_nrts1_default - &pinctrl_ndtr1_default - &pinctrl_ndsr1_default - &pinctrl_ncts1_default - &pinctrl_ndcd1_default - &pinctrl_nri1_default>; -}; - -&uart5 { - status = "okay"; -}; - -&mac0 { - status = "okay"; - - use-ncsi; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rmii1_default>; -}; - -&i2c0 { - status = "okay"; - - eeprom@50 { - compatible = "atmel,24c256"; - reg = <0x50>; - pagesize = <64>; - }; - - rtc@68 { - compatible = "dallas,ds3231"; - reg = <0x68>; - }; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; - - tmp423@4c { - compatible = "ti,tmp423"; - reg = <0x4c>; - }; -}; - -&i2c3 { - status = "okay"; - - occ-hwmon@50 { - compatible = "ibm,p8-occ-hwmon"; - reg = <0x50>; - }; -}; - -&i2c4 { - status = "okay"; -}; - -&i2c5 { - status = "okay"; -}; - -&i2c6 { - status = "okay"; -}; - -&i2c7 { - status = "okay"; -}; - -&vuart { - status = "okay"; -}; - -&ibt { - status = "okay"; -}; - -&lpc_ctrl { - status = "okay"; - memory-region = <&flash_memory>; - flash = <&spi>; -}; - -&gpio { - pin_func_mode0 { - gpio-hog; - gpios = ; - output-low; - line-name = "func_mode0"; - }; - - pin_func_mode1 { - gpio-hog; - gpios = ; - output-low; - line-name = "func_mode1"; - }; - - pin_func_mode2 { - gpio-hog; - gpios = ; - output-low; - line-name = "func_mode2"; - }; - - pin_gpio_a0 { - gpio-hog; - gpios = ; - input; - line-name = "BMC_FAN_RESERVED_N"; - }; - - pin_gpio_a1 { - gpio-hog; - gpios = ; - output-high; - line-name = "APSS_WDT_N"; - }; - - pin_gpio_b1 { - gpio-hog; - gpios = ; - output-high; - line-name = "APSS_BOOT_MODE"; - }; - - pin_gpio_b2 { - gpio-hog; - gpios = ; - output-high; - line-name = "APSS_RESET_N"; - }; - - pin_gpio_b7 { - gpio-hog; - gpios = ; - output-high; - line-name = "SPIVID_STBY_RESET_N"; - }; - - pin_gpio_d1 { - gpio-hog; - gpios = ; - output-high; - line-name = "BMC_POWER_UP"; - }; - - pin_gpio_f1 { - gpio-hog; - gpios = ; - input; - line-name = "BMC_BATTERY_TEST"; - }; - - pin_gpio_f4 { - gpio-hog; - gpios = ; - input; - line-name = "AST_HW_FAULT_N"; - }; - - pin_gpio_f5 { - gpio-hog; - gpios = ; - input; - line-name = "AST_SYS_FAULT_N"; - }; - - pin_gpio_f7 { - gpio-hog; - gpios = ; - output-high; - line-name = "BMC_FULL_SPEED_N"; - }; - - pin_gpio_g3 { - gpio-hog; - gpios = ; - output-high; - line-name = "BMC_FAN_ERROR_N"; - }; - - pin_gpio_g4 { - gpio-hog; - gpios = ; - input; - line-name = "BMC_WDT_RST1_P"; - }; - - pin_gpio_g5 { - gpio-hog; - gpios = ; - input; - line-name = "BMC_WDT_RST2_P"; - }; - - pin_gpio_h0 { - gpio-hog; - gpios = ; - input; - line-name = "PE_SLOT_TEST_EN_N"; - }; - - pin_gpio_h1 { - gpio-hog; - gpios = ; - input; - line-name = "BMC_RTCRST_N"; - }; - - pin_gpio_h2 { - gpio-hog; - gpios = ; - output-high; - line-name = "SYS_PWROK_BMC"; - }; - - pin_gpio_h7 { - gpio-hog; - gpios = ; - output-high; - line-name = "BMC_TPM_INT_N"; - }; -}; - -&fsi { - cfam@0,0 { - reg = <0 0>; - #address-cells = <1>; - #size-cells = <1>; - chip-id = <0>; - - scom@1000 { - compatible = "ibm,fsi2pib"; - reg = <0x1000 0x400>; - }; - - fsi_hub0: hub@3400 { - compatible = "ibm,fsi-master-hub"; - reg = <0x3400 0x400>; - #address-cells = <2>; - #size-cells = <0>; - no-scan-on-init; - }; - }; -}; diff --git a/sys/gnu/dts/arm/aspeed-bmc-opp-romulus.dts b/sys/gnu/dts/arm/aspeed-bmc-opp-romulus.dts deleted file mode 100644 index edfa44fe1f7..00000000000 --- a/sys/gnu/dts/arm/aspeed-bmc-opp-romulus.dts +++ /dev/null @@ -1,325 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/dts-v1/; -#include "aspeed-g5.dtsi" -#include - -/ { - model = "Romulus BMC"; - compatible = "ibm,romulus-bmc", "aspeed,ast2500"; - - chosen { - stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlyprintk"; - }; - - memory@80000000 { - reg = <0x80000000 0x20000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - vga_memory: framebuffer@9f000000 { - no-map; - reg = <0x9f000000 0x01000000>; /* 16M */ - }; - - flash_memory: region@98000000 { - no-map; - reg = <0x98000000 0x04000000>; /* 64M */ - }; - - coldfire_memory: codefire_memory@9ef00000 { - reg = <0x9ef00000 0x00100000>; - no-map; - }; - - gfx_memory: framebuffer { - size = <0x01000000>; - alignment = <0x01000000>; - compatible = "shared-dma-pool"; - reusable; - }; - - video_engine_memory: jpegbuffer { - size = <0x02000000>; /* 32M */ - alignment = <0x01000000>; - compatible = "shared-dma-pool"; - reusable; - }; - }; - - leds { - compatible = "gpio-leds"; - - fault { - gpios = <&gpio ASPEED_GPIO(N, 2) GPIO_ACTIVE_LOW>; - }; - - identify { - gpios = <&gpio ASPEED_GPIO(N, 4) GPIO_ACTIVE_HIGH>; - }; - - power { - gpios = <&gpio ASPEED_GPIO(R, 5) GPIO_ACTIVE_LOW>; - }; - }; - - fsi: gpio-fsi { - compatible = "aspeed,ast2500-cf-fsi-master", "fsi-master"; - #address-cells = <2>; - #size-cells = <0>; - no-gpio-delays; - - memory-region = <&coldfire_memory>; - aspeed,sram = <&sram>; - aspeed,cvic = <&cvic>; - - clock-gpios = <&gpio ASPEED_GPIO(AA, 0) GPIO_ACTIVE_HIGH>; - data-gpios = <&gpio ASPEED_GPIO(AA, 2) GPIO_ACTIVE_HIGH>; - mux-gpios = <&gpio ASPEED_GPIO(A, 6) GPIO_ACTIVE_HIGH>; - enable-gpios = <&gpio ASPEED_GPIO(D, 0) GPIO_ACTIVE_HIGH>; - trans-gpios = <&gpio ASPEED_GPIO(R, 2) GPIO_ACTIVE_HIGH>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - checkstop { - label = "checkstop"; - gpios = <&gpio ASPEED_GPIO(J, 2) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - id-button { - label = "id-button"; - gpios = <&gpio ASPEED_GPIO(Q, 7) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - iio-hwmon-battery { - compatible = "iio-hwmon"; - io-channels = <&adc 12>; - }; -}; - -&fmc { - status = "okay"; - flash@0 { - status = "okay"; - m25p,fast-read; - label = "bmc"; - spi-max-frequency = <50000000>; -#include "openbmc-flash-layout.dtsi" - }; -}; - -&spi1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1_default>; - - flash@0 { - status = "okay"; - m25p,fast-read; - label = "pnor"; - spi-max-frequency = <100000000>; - }; -}; - -&lpc_ctrl { - status = "okay"; - memory-region = <&flash_memory>; - flash = <&spi1>; -}; - -&uart1 { - /* Rear RS-232 connector */ - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd1_default - &pinctrl_rxd1_default - &pinctrl_nrts1_default - &pinctrl_ndtr1_default - &pinctrl_ndsr1_default - &pinctrl_ncts1_default - &pinctrl_ndcd1_default - &pinctrl_nri1_default>; -}; - -&uart5 { - status = "okay"; -}; - -&mac0 { - status = "okay"; - - use-ncsi; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rmii1_default>; - clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, - <&syscon ASPEED_CLK_MAC1RCLK>; - clock-names = "MACCLK", "RCLK"; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c3 { - status = "okay"; -}; - -&i2c4 { - status = "okay"; -}; - -&i2c5 { - status = "okay"; -}; - -&i2c6 { - /* PCIe slot 1 (x8) */ - status = "okay"; -}; - -&i2c7 { - /* PCIe slot 2 (x16) */ - status = "okay"; -}; - -&i2c8 { - /* PCIe slot 3 (x16) */ - status = "okay"; -}; - -&i2c9 { - /* PCIe slot 4 (x16) */ - status = "okay"; -}; - -&i2c10 { - /* PCIe slot 5 (x8) */ - status = "okay"; -}; - -&i2c11 { - status = "okay"; - - rtc@32 { - compatible = "epson,rx8900"; - reg = <0x32>; - }; -}; - -&i2c12 { - status = "okay"; - - w83773g@4c { - compatible = "nuvoton,w83773g"; - reg = <0x4c>; - }; -}; - -&gpio { - nic_func_mode0 { - gpio-hog; - gpios = ; - output-low; - line-name = "nic_func_mode0"; - }; - nic_func_mode1 { - gpio-hog; - gpios = ; - output-low; - line-name = "nic_func_mode1"; - }; - seq_cont { - gpio-hog; - gpios = ; - output-low; - line-name = "seq_cont"; - }; -}; - -&vuart { - status = "okay"; -}; - -&gfx { - status = "okay"; - memory-region = <&gfx_memory>; -}; - -&pinctrl { - aspeed,external-nodes = <&gfx &lhc>; -}; - -&pwm_tacho { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default>; - - fan@0 { - reg = <0x00>; - aspeed,fan-tach-ch = /bits/ 8 <0x08>; - }; - - fan@1 { - reg = <0x00>; - aspeed,fan-tach-ch = /bits/ 8 <0x09>; - }; - - fan@2 { - reg = <0x01>; - aspeed,fan-tach-ch = /bits/ 8 <0x0a>; - }; - - fan@3 { - reg = <0x01>; - aspeed,fan-tach-ch = /bits/ 8 <0x0b>; - }; - - fan@4 { - reg = <0x00>; - aspeed,fan-tach-ch = /bits/ 8 <0x0c>; - }; - - fan@5 { - reg = <0x00>; - aspeed,fan-tach-ch = /bits/ 8 <0x0d>; - }; - - fan@6 { - reg = <0x01>; - aspeed,fan-tach-ch = /bits/ 8 <0x0e>; - }; -}; - -&ibt { - status = "okay"; -}; - -&vhub { - status = "okay"; -}; - -&adc { - status = "okay"; -}; - -&video { - status = "okay"; - memory-region = <&video_engine_memory>; -}; - -#include "ibm-power9-dual.dtsi" diff --git a/sys/gnu/dts/arm/aspeed-bmc-opp-swift.dts b/sys/gnu/dts/arm/aspeed-bmc-opp-swift.dts deleted file mode 100644 index d56b5ed09b3..00000000000 --- a/sys/gnu/dts/arm/aspeed-bmc-opp-swift.dts +++ /dev/null @@ -1,978 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/dts-v1/; -#include "aspeed-g5.dtsi" -#include -#include - -/ { - model = "Swift BMC"; - compatible = "ibm,swift-bmc", "aspeed,ast2500"; - - chosen { - stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlyprintk"; - }; - - memory@80000000 { - reg = <0x80000000 0x20000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - flash_memory: region@98000000 { - no-map; - reg = <0x98000000 0x04000000>; /* 64M */ - }; - - gfx_memory: framebuffer { - size = <0x01000000>; - alignment = <0x01000000>; - compatible = "shared-dma-pool"; - reusable; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - air-water { - label = "air-water"; - gpios = <&gpio ASPEED_GPIO(B, 5) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - checkstop { - label = "checkstop"; - gpios = <&gpio ASPEED_GPIO(J, 2) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - ps0-presence { - label = "ps0-presence"; - gpios = <&gpio ASPEED_GPIO(R, 7) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - ps1-presence { - label = "ps1-presence"; - gpios = <&gpio ASPEED_GPIO(N, 0) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - oppanel-presence { - label = "oppanel-presence"; - gpios = <&gpio ASPEED_GPIO(A, 7) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - opencapi-riser-presence { - label = "opencapi-riser-presence"; - gpios = <&gpio ASPEED_GPIO(I, 0) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - iio-hwmon-battery { - compatible = "iio-hwmon"; - io-channels = <&adc 12>; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - poll-interval = <1000>; - - scm0-presence { - label = "scm0-presence"; - gpios = <&pca9552 6 GPIO_ACTIVE_LOW>; - linux,code = <6>; - }; - - scm1-presence { - label = "scm1-presence"; - gpios = <&pca9552 7 GPIO_ACTIVE_LOW>; - linux,code = <7>; - }; - - cpu0vrm-presence { - label = "cpu0vrm-presence"; - gpios = <&pca9552 12 GPIO_ACTIVE_LOW>; - linux,code = <12>; - }; - - cpu1vrm-presence { - label = "cpu1vrm-presence"; - gpios = <&pca9552 13 GPIO_ACTIVE_LOW>; - linux,code = <13>; - }; - - fan0-presence { - label = "fan0-presence"; - gpios = <&pca0 5 GPIO_ACTIVE_LOW>; - linux,code = <5>; - }; - - fan1-presence { - label = "fan1-presence"; - gpios = <&pca0 6 GPIO_ACTIVE_LOW>; - linux,code = <6>; - }; - - fan2-presence { - label = "fan2-presence"; - gpios = <&pca0 7 GPIO_ACTIVE_LOW>; - linux,code = <7>; - }; - - fan3-presence { - label = "fan3-presence"; - gpios = <&pca0 8 GPIO_ACTIVE_LOW>; - linux,code = <8>; - }; - - fanboost-presence { - label = "fanboost-presence"; - gpios = <&pca0 9 GPIO_ACTIVE_LOW>; - linux,code = <9>; - }; - }; - - leds { - compatible = "gpio-leds"; - - fan0 { - retain-state-shutdown; - default-state = "keep"; - gpios = <&pca0 0 GPIO_ACTIVE_LOW>; - }; - - fan1 { - retain-state-shutdown; - default-state = "keep"; - gpios = <&pca0 1 GPIO_ACTIVE_LOW>; - }; - - fan2 { - retain-state-shutdown; - default-state = "keep"; - gpios = <&pca0 2 GPIO_ACTIVE_LOW>; - }; - - fan3 { - retain-state-shutdown; - default-state = "keep"; - gpios = <&pca0 3 GPIO_ACTIVE_LOW>; - }; - - fanboost { - retain-state-shutdown; - default-state = "keep"; - gpios = <&pca0 4 GPIO_ACTIVE_LOW>; - }; - - front-fault { - retain-state-shutdown; - default-state = "keep"; - gpios = <&pca1 2 GPIO_ACTIVE_LOW>; - }; - - front-power { - retain-state-shutdown; - default-state = "keep"; - gpios = <&pca1 3 GPIO_ACTIVE_LOW>; - }; - - front-id { - retain-state-shutdown; - default-state = "keep"; - gpios = <&pca1 0 GPIO_ACTIVE_LOW>; - }; - - rear-fault { - gpios = <&gpio ASPEED_GPIO(N, 2) GPIO_ACTIVE_LOW>; - }; - - rear-id { - gpios = <&gpio ASPEED_GPIO(N, 4) GPIO_ACTIVE_LOW>; - }; - }; - - fsi: gpio-fsi { - compatible = "fsi-master-gpio", "fsi-master"; - #address-cells = <2>; - #size-cells = <0>; - no-gpio-delays; - - clock-gpios = <&gpio ASPEED_GPIO(P, 1) GPIO_ACTIVE_HIGH>; - data-gpios = <&gpio ASPEED_GPIO(P, 2) GPIO_ACTIVE_HIGH>; - mux-gpios = <&gpio ASPEED_GPIO(P, 4) GPIO_ACTIVE_HIGH>; - enable-gpios = <&gpio ASPEED_GPIO(P, 0) GPIO_ACTIVE_HIGH>; - trans-gpios = <&gpio ASPEED_GPIO(P, 3) GPIO_ACTIVE_HIGH>; - }; - - iio-hwmon-dps310 { - compatible = "iio-hwmon"; - io-channels = <&dps 0>; - }; - -}; - -&fmc { - status = "okay"; - - flash@0 { - status = "okay"; - label = "bmc"; - m25p,fast-read; - spi-max-frequency = <100000000>; - partitions { - #address-cells = < 1 >; - #size-cells = < 1 >; - compatible = "fixed-partitions"; - u-boot@0 { - reg = < 0 0x60000 >; - label = "u-boot"; - }; - u-boot-env@60000 { - reg = < 0x60000 0x20000 >; - label = "u-boot-env"; - }; - obmc-ubi@80000 { - reg = < 0x80000 0x7F80000>; - label = "obmc-ubi"; - }; - }; - }; - - flash@1 { - status = "okay"; - label = "alt-bmc"; - m25p,fast-read; - spi-max-frequency = <100000000>; - partitions { - #address-cells = < 1 >; - #size-cells = < 1 >; - compatible = "fixed-partitions"; - u-boot@0 { - reg = < 0 0x60000 >; - label = "alt-u-boot"; - }; - u-boot-env@60000 { - reg = < 0x60000 0x20000 >; - label = "alt-u-boot-env"; - }; - obmc-ubi@80000 { - reg = < 0x80000 0x7F80000>; - label = "alt-obmc-ubi"; - }; - }; - }; -}; - -&spi1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1_default>; - - flash@0 { - status = "okay"; - label = "pnor"; - m25p,fast-read; - spi-max-frequency = <100000000>; - }; -}; - -&uart1 { - /* Rear RS-232 connector */ - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd1_default - &pinctrl_rxd1_default - &pinctrl_nrts1_default - &pinctrl_ndtr1_default - &pinctrl_ndsr1_default - &pinctrl_ncts1_default - &pinctrl_ndcd1_default - &pinctrl_nri1_default>; -}; - -&uart2 { - /* APSS */ - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd2_default &pinctrl_rxd2_default>; -}; - -&uart5 { - status = "okay"; -}; - -&lpc_ctrl { - status = "okay"; - memory-region = <&flash_memory>; - flash = <&spi1>; -}; - -&mac0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rmii1_default>; - use-ncsi; - clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, - <&syscon ASPEED_CLK_MAC1RCLK>; - clock-names = "MACCLK", "RCLK"; -}; - -&i2c2 { - status = "okay"; - - /* MUX -> - * Samtec 1 - * Samtec 2 - */ -}; - -&i2c3 { - status = "okay"; - - max31785@52 { - compatible = "maxim,max31785a"; - reg = <0x52>; - #address-cells = <1>; - #size-cells = <0>; - - fan@0 { - compatible = "pmbus-fan"; - reg = <0>; - tach-pulses = <2>; - maxim,fan-rotor-input = "tach"; - maxim,fan-pwm-freq = <25000>; - maxim,fan-no-watchdog; - maxim,fan-no-fault-ramp; - maxim,fan-ramp = <2>; - maxim,fan-fault-pin-mon; - }; - - fan@1 { - compatible = "pmbus-fan"; - reg = <1>; - tach-pulses = <2>; - maxim,fan-rotor-input = "tach"; - maxim,fan-pwm-freq = <25000>; - maxim,fan-no-watchdog; - maxim,fan-no-fault-ramp; - maxim,fan-ramp = <2>; - maxim,fan-fault-pin-mon; - }; - - fan@2 { - compatible = "pmbus-fan"; - reg = <2>; - tach-pulses = <2>; - maxim,fan-rotor-input = "tach"; - maxim,fan-pwm-freq = <25000>; - maxim,fan-no-watchdog; - maxim,fan-no-fault-ramp; - maxim,fan-ramp = <2>; - maxim,fan-fault-pin-mon; - }; - - fan@3 { - compatible = "pmbus-fan"; - reg = <3>; - tach-pulses = <2>; - maxim,fan-rotor-input = "tach"; - maxim,fan-pwm-freq = <25000>; - maxim,fan-no-watchdog; - maxim,fan-no-fault-ramp; - maxim,fan-ramp = <2>; - maxim,fan-fault-pin-mon; - }; - - fan@4 { - compatible = "pmbus-fan"; - reg = <4>; - tach-pulses = <2>; - maxim,fan-rotor-input = "tach"; - maxim,fan-pwm-freq = <25000>; - maxim,fan-no-watchdog; - maxim,fan-no-fault-ramp; - maxim,fan-ramp = <2>; - maxim,fan-fault-pin-mon; - }; - }; - - pca0: pca9552@60 { - compatible = "nxp,pca9552"; - reg = <0x60>; - #address-cells = <1>; - #size-cells = <0>; - - gpio-controller; - #gpio-cells = <2>; - - gpio@0 { - reg = <0>; - type = ; - }; - - gpio@1 { - reg = <1>; - type = ; - }; - - gpio@2 { - reg = <2>; - type = ; - }; - - gpio@3 { - reg = <3>; - type = ; - }; - - gpio@4 { - reg = <4>; - type = ; - }; - - gpio@5 { - reg = <5>; - type = ; - }; - - gpio@6 { - reg = <6>; - type = ; - }; - - gpio@7 { - reg = <7>; - type = ; - }; - - gpio@8 { - reg = <8>; - type = ; - }; - - gpio@9 { - reg = <9>; - type = ; - }; - - gpio@10 { - reg = <10>; - type = ; - }; - - gpio@11 { - reg = <11>; - type = ; - }; - - gpio@12 { - reg = <12>; - type = ; - }; - - gpio@13 { - reg = <13>; - type = ; - }; - - gpio@14 { - reg = <14>; - type = ; - }; - - gpio@15 { - reg = <15>; - type = ; - }; - }; - - power-supply@68 { - compatible = "ibm,cffps2"; - reg = <0x68>; - }; - - eeprom@50 { - compatible = "atmel,24c64"; - reg = <0x50>; - }; - - power-supply@69 { - compatible = "ibm,cffps2"; - reg = <0x69>; - }; - - eeprom@51 { - compatible = "atmel,24c64"; - reg = <0x51>; - }; -}; - -&i2c7 { - status = "okay"; - - dps: dps310@76 { - compatible = "infineon,dps310"; - reg = <0x76>; - #io-channel-cells = <0>; - }; - - tmp275@48 { - compatible = "ti,tmp275"; - reg = <0x48>; - }; - - si7021a20@20 { - compatible = "si,si7021a20"; - reg = <0x20>; - }; - - eeprom@50 { - compatible = "atmel,24c64"; - reg = <0x50>; - }; - - pca1: pca9551@60 { - compatible = "nxp,pca9551"; - reg = <0x60>; - #address-cells = <1>; - #size-cells = <0>; - - gpio-controller; - #gpio-cells = <2>; - - gpio@0 { - reg = <0>; - type = ; - }; - - gpio@1 { - reg = <1>; - type = ; - }; - - gpio@2 { - reg = <2>; - type = ; - }; - - gpio@3 { - reg = <3>; - type = ; - }; - - gpio@4 { - reg = <4>; - type = ; - }; - - gpio@5 { - reg = <5>; - type = ; - }; - - gpio@6 { - reg = <6>; - type = ; - }; - - gpio@7 { - reg = <7>; - type = ; - }; - }; -}; - -&i2c8 { - status = "okay"; - - pca9552: pca9552@60 { - compatible = "nxp,pca9552"; - reg = <0x60>; - #address-cells = <1>; - #size-cells = <0>; - gpio-controller; - #gpio-cells = <2>; - - gpio-line-names = "PS_SMBUS_RESET_N", "APSS_RESET_N", - "GPU0_TH_OVERT_N_BUFF", "GPU1_TH_OVERT_N_BUFF", - "GPU2_TH_OVERT_N_BUFF", "GPU3_TH_OVERT_N_BUFF", - "P9_SCM0_PRES", "P9_SCM1_PRES", - "GPU0_PWR_GOOD_BUFF", "GPU1_PWR_GOOD_BUFF", - "GPU2_PWR_GOOD_BUFF", "GPU3_PWR_GOOD_BUFF", - "PRESENT_VRM_CP0_N", "PRESENT_VRM_CP1_N", - "12V_BREAKER_FLT_N", "THROTTLE_UNLATCHED_N"; - - gpio@0 { - reg = <0>; - type = ; - }; - - gpio@1 { - reg = <1>; - type = ; - }; - - gpio@2 { - reg = <2>; - type = ; - }; - - gpio@3 { - reg = <3>; - type = ; - }; - - gpio@4 { - reg = <4>; - type = ; - }; - - gpio@5 { - reg = <5>; - type = ; - }; - - gpio@6 { - reg = <6>; - type = ; - }; - - gpio@7 { - reg = <7>; - type = ; - }; - - gpio@8 { - reg = <8>; - type = ; - }; - - gpio@9 { - reg = <9>; - type = ; - }; - - gpio@10 { - reg = <10>; - type = ; - }; - - gpio@11 { - reg = <11>; - type = ; - }; - - gpio@12 { - reg = <12>; - type = ; - }; - - gpio@13 { - reg = <13>; - type = ; - }; - - gpio@14 { - reg = <14>; - type = ; - }; - - gpio@15 { - reg = <15>; - type = ; - }; - }; - - rtc@32 { - compatible = "epson,rx8900"; - reg = <0x32>; - }; - - eeprom@51 { - compatible = "atmel,24c64"; - reg = <0x51>; - }; - - ucd90160@64 { - compatible = "ti,ucd90160"; - reg = <0x64>; - }; -}; - -&i2c9 { - status = "okay"; - - eeprom@50 { - compatible = "atmel,24c64"; - reg = <0x50>; - }; - - tmp423a@4c { - compatible = "ti,tmp423"; - reg = <0x4c>; - }; - - ir35221@71 { - compatible = "infineon,ir35221"; - reg = <0x71>; - }; - - ir35221@72 { - compatible = "infineon,ir35221"; - reg = <0x72>; - }; - - pca2: pca9539@74 { - compatible = "nxp,pca9539"; - reg = <0x74>; - #address-cells = <1>; - #size-cells = <0>; - gpio-controller; - #gpio-cells = <2>; - - gpio@0 { - reg = <0>; - }; - - gpio@1 { - reg = <1>; - }; - - gpio@2 { - reg = <2>; - }; - - gpio@3 { - reg = <3>; - }; - - gpio@4 { - reg = <4>; - }; - - gpio@5 { - reg = <5>; - }; - - gpio@6 { - reg = <6>; - }; - - gpio@7 { - reg = <7>; - }; - - gpio@8 { - reg = <8>; - }; - - gpio@9 { - reg = <9>; - }; - - gpio@10 { - reg = <10>; - }; - - gpio@11 { - reg = <11>; - }; - - gpio@12 { - reg = <12>; - }; - - gpio@13 { - reg = <13>; - }; - - gpio@14 { - reg = <14>; - }; - - gpio@15 { - reg = <15>; - }; - }; -}; - -&i2c10 { - status = "okay"; - - eeprom@50 { - compatible = "atmel,24c64"; - reg = <0x50>; - }; - - tmp423a@4c { - compatible = "ti,tmp423"; - reg = <0x4c>; - }; - - ir35221@71 { - compatible = "infineon,ir35221"; - reg = <0x71>; - }; - - ir35221@72 { - compatible = "infineon,ir35221"; - reg = <0x72>; - }; - - pca3: pca9539@74 { - compatible = "nxp,pca9539"; - reg = <0x74>; - #address-cells = <1>; - #size-cells = <0>; - gpio-controller; - #gpio-cells = <2>; - - gpio@0 { - reg = <0>; - }; - - gpio@1 { - reg = <1>; - }; - - gpio@2 { - reg = <2>; - }; - - gpio@3 { - reg = <3>; - }; - - gpio@4 { - reg = <4>; - }; - - gpio@5 { - reg = <5>; - }; - - gpio@6 { - reg = <6>; - }; - - gpio@7 { - reg = <7>; - }; - - gpio@8 { - reg = <8>; - }; - - gpio@9 { - reg = <9>; - }; - - gpio@10 { - reg = <10>; - }; - - gpio@11 { - reg = <11>; - }; - - gpio@12 { - reg = <12>; - }; - - gpio@13 { - reg = <13>; - }; - - gpio@14 { - reg = <14>; - }; - - gpio@15 { - reg = <15>; - }; - }; -}; - -&i2c11 { - /* MUX - * -> PCIe Slot 0 - * -> PCIe Slot 1 - * -> PCIe Slot 2 - * -> PCIe Slot 3 - */ - status = "okay"; -}; - -&i2c12 { - status = "okay"; - - tmp275@48 { - compatible = "ti,tmp275"; - reg = <0x48>; - }; - - tmp275@4a { - compatible = "ti,tmp275"; - reg = <0x4a>; - }; -}; - -&i2c13 { - status = "okay"; -}; - -&vuart { - status = "okay"; -}; - -&gfx { - status = "okay"; - memory-region = <&gfx_memory>; -}; - -&pinctrl { - aspeed,external-nodes = <&gfx &lhc>; -}; - -&wdt1 { - aspeed,reset-type = "none"; - aspeed,external-signal; - aspeed,ext-push-pull; - aspeed,ext-active-high; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdtrst1_default>; -}; - -&wdt2 { - aspeed,alt-boot; -}; - -&ibt { - status = "okay"; -}; - -&adc { - status = "okay"; -}; - -&sdmmc { - status = "okay"; -}; - -&sdhci1 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sd2_default>; -}; - -#include "ibm-power9-dual.dtsi" diff --git a/sys/gnu/dts/arm/aspeed-bmc-opp-tacoma.dts b/sys/gnu/dts/arm/aspeed-bmc-opp-tacoma.dts deleted file mode 100644 index ff49ec76fa7..00000000000 --- a/sys/gnu/dts/arm/aspeed-bmc-opp-tacoma.dts +++ /dev/null @@ -1,802 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -// Copyright 2019 IBM Corp. -/dts-v1/; - -#include "aspeed-g6.dtsi" -#include -#include - -/ { - model = "Tacoma"; - compatible = "ibm,tacoma-bmc", "aspeed,ast2600"; - - chosen { - stdout-path = &uart5; - bootargs = "console=ttyS4,115200n8"; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x40000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - flash_memory: region@ba000000 { - no-map; - reg = <0xb8000000 0x4000000>; /* 64M */ - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - air-water { - label = "air-water"; - gpios = <&gpio0 ASPEED_GPIO(Q, 7) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - checkstop { - label = "checkstop"; - gpios = <&gpio0 ASPEED_GPIO(E, 3) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - ps0-presence { - label = "ps0-presence"; - gpios = <&gpio0 ASPEED_GPIO(H, 3) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - ps1-presence { - label = "ps1-presence"; - gpios = <&gpio0 ASPEED_GPIO(E, 5) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <1000>; - - fan0-presence { - label = "fan0-presence"; - gpios = <&pca0 4 GPIO_ACTIVE_LOW>; - linux,code = <4>; - }; - - fan1-presence { - label = "fan1-presence"; - gpios = <&pca0 5 GPIO_ACTIVE_LOW>; - linux,code = <5>; - }; - - fan2-presence { - label = "fan2-presence"; - gpios = <&pca0 6 GPIO_ACTIVE_LOW>; - linux,code = <6>; - }; - - fan3-presence { - label = "fan3-presence"; - gpios = <&pca0 7 GPIO_ACTIVE_LOW>; - linux,code = <7>; - }; - }; -}; - -&fmc { - status = "okay"; - flash@0 { - status = "okay"; - m25p,fast-read; - label = "bmc"; - spi-max-frequency = <50000000>; -#include "openbmc-flash-layout-128.dtsi" - }; - - flash@1 { - status = "okay"; - m25p,fast-read; - label = "alt-bmc"; - spi-max-frequency = <50000000>; - }; -}; - -&spi1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1_default>; - - flash@0 { - status = "okay"; - m25p,fast-read; - label = "pnor"; - spi-max-frequency = <100000000>; - }; -}; - -&mac2 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rmii3_default>; - clocks = <&syscon ASPEED_CLK_GATE_MAC3CLK>, - <&syscon ASPEED_CLK_MAC3RCLK>; - clock-names = "MACCLK", "RCLK"; - use-ncsi; -}; - -&emmc { - status = "okay"; -}; - -&fsim0 { - status = "okay"; - - #address-cells = <2>; - #size-cells = <0>; - - cfam@0,0 { - reg = <0 0>; - #address-cells = <1>; - #size-cells = <1>; - chip-id = <0>; - - scom@1000 { - compatible = "ibm,fsi2pib"; - reg = <0x1000 0x400>; - }; - - i2c@1800 { - compatible = "ibm,fsi-i2c-master"; - reg = <0x1800 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - cfam0_i2c0: i2c-bus@0 { - reg = <0>; - }; - - cfam0_i2c1: i2c-bus@1 { - reg = <1>; - }; - - cfam0_i2c2: i2c-bus@2 { - reg = <2>; - }; - - cfam0_i2c3: i2c-bus@3 { - reg = <3>; - }; - - cfam0_i2c4: i2c-bus@4 { - reg = <4>; - }; - - cfam0_i2c5: i2c-bus@5 { - reg = <5>; - }; - - cfam0_i2c6: i2c-bus@6 { - reg = <6>; - }; - - cfam0_i2c7: i2c-bus@7 { - reg = <7>; - }; - - cfam0_i2c8: i2c-bus@8 { - reg = <8>; - }; - - cfam0_i2c9: i2c-bus@9 { - reg = <9>; - }; - - cfam0_i2c10: i2c-bus@a { - reg = <10>; - }; - - cfam0_i2c11: i2c-bus@b { - reg = <11>; - }; - - cfam0_i2c12: i2c-bus@c { - reg = <12>; - }; - - cfam0_i2c13: i2c-bus@d { - reg = <13>; - }; - - cfam0_i2c14: i2c-bus@e { - reg = <14>; - }; - }; - - sbefifo@2400 { - compatible = "ibm,p9-sbefifo"; - reg = <0x2400 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - fsi_occ0: occ { - compatible = "ibm,p9-occ"; - }; - }; - - fsi_hub0: hub@3400 { - compatible = "fsi-master-hub"; - reg = <0x3400 0x400>; - #address-cells = <2>; - #size-cells = <0>; - - no-scan-on-init; - }; - }; -}; - -&fsi_hub0 { - cfam@1,0 { - reg = <1 0>; - #address-cells = <1>; - #size-cells = <1>; - chip-id = <1>; - - scom@1000 { - compatible = "ibm,fsi2pib"; - reg = <0x1000 0x400>; - }; - - i2c@1800 { - compatible = "ibm,fsi-i2c-master"; - reg = <0x1800 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - cfam1_i2c0: i2c-bus@0 { - reg = <0>; - }; - - cfam1_i2c1: i2c-bus@1 { - reg = <1>; - }; - - cfam1_i2c2: i2c-bus@2 { - reg = <2>; - }; - - cfam1_i2c3: i2c-bus@3 { - reg = <3>; - }; - - cfam1_i2c4: i2c-bus@4 { - reg = <4>; - }; - - cfam1_i2c5: i2c-bus@5 { - reg = <5>; - }; - - cfam1_i2c6: i2c-bus@6 { - reg = <6>; - }; - - cfam1_i2c7: i2c-bus@7 { - reg = <7>; - }; - - cfam1_i2c8: i2c-bus@8 { - reg = <8>; - }; - - cfam1_i2c9: i2c-bus@9 { - reg = <9>; - }; - - cfam1_i2c10: i2c-bus@a { - reg = <10>; - }; - - cfam1_i2c11: i2c-bus@b { - reg = <11>; - }; - - cfam1_i2c12: i2c-bus@c { - reg = <12>; - }; - - cfam1_i2c13: i2c-bus@d { - reg = <13>; - }; - - cfam1_i2c14: i2c-bus@e { - reg = <14>; - }; - }; - - sbefifo@2400 { - compatible = "ibm,p9-sbefifo"; - reg = <0x2400 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - fsi_occ1: occ { - compatible = "ibm,p9-occ"; - }; - }; - - fsi_hub1: hub@3400 { - compatible = "fsi-master-hub"; - reg = <0x3400 0x400>; - #address-cells = <2>; - #size-cells = <0>; - - no-scan-on-init; - }; - }; -}; - -/* Legacy OCC numbering (to get rid of when userspace is fixed) */ -&fsi_occ0 { - reg = <1>; -}; - -&fsi_occ1 { - reg = <2>; -}; - -/ { - aliases { - i2c100 = &cfam0_i2c0; - i2c101 = &cfam0_i2c1; - i2c102 = &cfam0_i2c2; - i2c103 = &cfam0_i2c3; - i2c104 = &cfam0_i2c4; - i2c105 = &cfam0_i2c5; - i2c106 = &cfam0_i2c6; - i2c107 = &cfam0_i2c7; - i2c108 = &cfam0_i2c8; - i2c109 = &cfam0_i2c9; - i2c110 = &cfam0_i2c10; - i2c111 = &cfam0_i2c11; - i2c112 = &cfam0_i2c12; - i2c113 = &cfam0_i2c13; - i2c114 = &cfam0_i2c14; - i2c200 = &cfam1_i2c0; - i2c201 = &cfam1_i2c1; - i2c202 = &cfam1_i2c2; - i2c203 = &cfam1_i2c3; - i2c204 = &cfam1_i2c4; - i2c205 = &cfam1_i2c5; - i2c206 = &cfam1_i2c6; - i2c207 = &cfam1_i2c7; - i2c208 = &cfam1_i2c8; - i2c209 = &cfam1_i2c9; - i2c210 = &cfam1_i2c10; - i2c211 = &cfam1_i2c11; - i2c212 = &cfam1_i2c12; - i2c213 = &cfam1_i2c13; - i2c214 = &cfam1_i2c14; - }; - -}; - -&i2c0 { - status = "okay"; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c3 { - status = "okay"; - - bmp: bmp280@77 { - compatible = "bosch,bmp280"; - reg = <0x77>; - #io-channel-cells = <1>; - }; - - max31785@52 { - compatible = "maxim,max31785a"; - reg = <0x52>; - #address-cells = <1>; - #size-cells = <0>; - - fan@0 { - compatible = "pmbus-fan"; - reg = <0>; - tach-pulses = <2>; - maxim,fan-rotor-input = "tach"; - maxim,fan-pwm-freq = <25000>; - maxim,fan-dual-tach; - maxim,fan-no-watchdog; - maxim,fan-no-fault-ramp; - maxim,fan-ramp = <2>; - maxim,fan-fault-pin-mon; - }; - - fan@1 { - compatible = "pmbus-fan"; - reg = <1>; - tach-pulses = <2>; - maxim,fan-rotor-input = "tach"; - maxim,fan-pwm-freq = <25000>; - maxim,fan-dual-tach; - maxim,fan-no-watchdog; - maxim,fan-no-fault-ramp; - maxim,fan-ramp = <2>; - maxim,fan-fault-pin-mon; - }; - - fan@2 { - compatible = "pmbus-fan"; - reg = <2>; - tach-pulses = <2>; - maxim,fan-rotor-input = "tach"; - maxim,fan-pwm-freq = <25000>; - maxim,fan-dual-tach; - maxim,fan-no-watchdog; - maxim,fan-no-fault-ramp; - maxim,fan-ramp = <2>; - maxim,fan-fault-pin-mon; - }; - - fan@3 { - compatible = "pmbus-fan"; - reg = <3>; - tach-pulses = <2>; - maxim,fan-rotor-input = "tach"; - maxim,fan-pwm-freq = <25000>; - maxim,fan-dual-tach; - maxim,fan-no-watchdog; - maxim,fan-no-fault-ramp; - maxim,fan-ramp = <2>; - maxim,fan-fault-pin-mon; - }; - }; - - dps: dps310@76 { - compatible = "infineon,dps310"; - reg = <0x76>; - #io-channel-cells = <0>; - }; - - pca0: pca9552@60 { - compatible = "nxp,pca9552"; - reg = <0x60>; - #address-cells = <1>; - #size-cells = <0>; - - gpio-controller; - #gpio-cells = <2>; - - gpio@0 { - reg = <0>; - type = ; - }; - - gpio@1 { - reg = <1>; - type = ; - }; - - gpio@2 { - reg = <2>; - type = ; - }; - - gpio@3 { - reg = <3>; - type = ; - }; - - gpio@4 { - reg = <4>; - type = ; - }; - - gpio@5 { - reg = <5>; - type = ; - }; - - gpio@6 { - reg = <6>; - type = ; - }; - - gpio@7 { - reg = <7>; - type = ; - }; - - gpio@8 { - reg = <8>; - type = ; - }; - - gpio@9 { - reg = <9>; - type = ; - }; - - gpio@10 { - reg = <10>; - type = ; - }; - - gpio@11 { - reg = <11>; - type = ; - }; - - gpio@12 { - reg = <12>; - type = ; - }; - - gpio@13 { - reg = <13>; - type = ; - }; - - gpio@14 { - reg = <14>; - type = ; - }; - - gpio@15 { - reg = <15>; - type = ; - }; - }; - - power-supply@68 { - compatible = "ibm,cffps1"; - reg = <0x68>; - }; - - power-supply@69 { - compatible = "ibm,cffps1"; - reg = <0x69>; - }; -}; - -&i2c4 { - status = "okay"; - - tmp423a@4c { - compatible = "ti,tmp423"; - reg = <0x4c>; - }; - - ir35221@70 { - compatible = "infineon,ir35221"; - reg = <0x70>; - }; - - ir35221@71 { - compatible = "infineon,ir35221"; - reg = <0x71>; - }; -}; - -&i2c5 { - status = "okay"; - - tmp423a@4c { - compatible = "ti,tmp423"; - reg = <0x4c>; - }; - - ir35221@70 { - compatible = "infineon,ir35221"; - reg = <0x70>; - }; - - ir35221@71 { - compatible = "infineon,ir35221"; - reg = <0x71>; - }; -}; - -&i2c7 { - status = "okay"; -}; - -&i2c9 { - status = "okay"; - - tmp275@4a { - compatible = "ti,tmp275"; - reg = <0x4a>; - }; -}; - -&i2c10 { - status = "okay"; -}; - -&i2c11 { - status = "okay"; - - pca9552: pca9552@60 { - compatible = "nxp,pca9552"; - reg = <0x60>; - #address-cells = <1>; - #size-cells = <0>; - gpio-controller; - #gpio-cells = <2>; - - gpio-line-names = "PS_SMBUS_RESET_N", "APSS_RESET_N", - "GPU0_TH_OVERT_N_BUFF", "GPU1_TH_OVERT_N_BUFF", - "GPU2_TH_OVERT_N_BUFF", "GPU3_TH_OVERT_N_BUFF", - "GPU4_TH_OVERT_N_BUFF", "GPU5_TH_OVERT_N_BUFF", - "GPU0_PWR_GOOD_BUFF", "GPU1_PWR_GOOD_BUFF", - "GPU2_PWR_GOOD_BUFF", "GPU3_PWR_GOOD_BUFF", - "GPU4_PWR_GOOD_BUFF", "GPU5_PWR_GOOD_BUFF", - "12V_BREAKER_FLT_N", "THROTTLE_UNLATCHED_N"; - - gpio@0 { - reg = <0>; - type = ; - }; - - gpio@1 { - reg = <1>; - type = ; - }; - - gpio@2 { - reg = <2>; - type = ; - }; - - gpio@3 { - reg = <3>; - type = ; - }; - - gpio@4 { - reg = <4>; - type = ; - }; - - gpio@5 { - reg = <5>; - type = ; - }; - - gpio@6 { - reg = <6>; - type = ; - }; - - gpio@7 { - reg = <7>; - type = ; - }; - - gpio@8 { - reg = <8>; - type = ; - }; - - gpio@9 { - reg = <9>; - type = ; - }; - - gpio@10 { - reg = <10>; - type = ; - }; - - gpio@11 { - reg = <11>; - type = ; - }; - - gpio@12 { - reg = <12>; - type = ; - }; - - gpio@13 { - reg = <13>; - type = ; - }; - - gpio@14 { - reg = <14>; - type = ; - }; - - gpio@15 { - reg = <15>; - type = ; - }; - }; - - rtc@32 { - compatible = "epson,rx8900"; - reg = <0x32>; - }; - - eeprom@51 { - compatible = "atmel,24c64"; - reg = <0x51>; - }; - - ucd90160@64 { - compatible = "ti,ucd90160"; - reg = <0x64>; - }; -}; - -&i2c12 { - status = "okay"; -}; - -&i2c13 { - status = "okay"; -}; - -&ibt { - status = "okay"; -}; - -&uart1 { - status = "okay"; - // Workaround for A0 - compatible = "snps,dw-apb-uart"; -}; - -&uart5 { - // Workaround for A0 - compatible = "snps,dw-apb-uart"; -}; - -&vuart1 { - status = "okay"; -}; - -&lpc_ctrl { - status = "okay"; - memory-region = <&flash_memory>; - flash = <&spi1>; -}; - -&wdt1 { - aspeed,reset-type = "none"; - aspeed,external-signal; - aspeed,ext-push-pull; - aspeed,ext-active-high; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdtrst1_default>; -}; - -&wdt2 { - status = "okay"; -}; - -&pinctrl { - /* Hog these as no driver is probed for the entire LPC block */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpc_default>, - <&pinctrl_lsirq_default>; -}; diff --git a/sys/gnu/dts/arm/aspeed-bmc-opp-vesnin.dts b/sys/gnu/dts/arm/aspeed-bmc-opp-vesnin.dts deleted file mode 100644 index 01074b6e3e0..00000000000 --- a/sys/gnu/dts/arm/aspeed-bmc-opp-vesnin.dts +++ /dev/null @@ -1,248 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// Copyright 2019 YADRO -/dts-v1/; - -#include "aspeed-g4.dtsi" -#include - -/ { - model = "Vesnin BMC"; - compatible = "yadro,vesnin-bmc", "aspeed,ast2400"; - - chosen { - stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlyprintk"; - }; - - memory@40000000 { - reg = <0x40000000 0x20000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - vga_memory: framebuffer@5f000000 { - no-map; - reg = <0x5f000000 0x01000000>; /* 16MB */ - }; - flash_memory: region@5c000000 { - no-map; - reg = <0x5c000000 0x02000000>; /* 32M */ - }; - }; - - leds { - compatible = "gpio-leds"; - - heartbeat { - gpios = <&gpio ASPEED_GPIO(R, 4) GPIO_ACTIVE_LOW>; - }; - power_red { - gpios = <&gpio ASPEED_GPIO(N, 1) GPIO_ACTIVE_LOW>; - }; - - power_green { - gpios = <&gpio ASPEED_GPIO(F, 1) GPIO_ACTIVE_LOW>; - }; - - id_blue { - gpios = <&gpio ASPEED_GPIO(O, 0) GPIO_ACTIVE_LOW>; - }; - - alarm_red { - gpios = <&gpio ASPEED_GPIO(N, 6) GPIO_ACTIVE_LOW>; - }; - - alarm_yel { - gpios = <&gpio ASPEED_GPIO(N, 7) GPIO_ACTIVE_HIGH>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - button_checkstop { - label = "checkstop"; - linux,code = <74>; - gpios = <&gpio ASPEED_GPIO(P, 5) GPIO_ACTIVE_LOW>; - }; - - button_identify { - label = "identify"; - linux,code = <152>; - gpios = <&gpio ASPEED_GPIO(O, 7) GPIO_ACTIVE_LOW>; - }; - }; -}; - -&fmc { - status = "okay"; - flash@0 { - status = "okay"; - m25p,fast-read; - label = "bmc"; -#include "openbmc-flash-layout.dtsi" - }; - - flash@1 { - status = "okay"; - m25p,fast-read; - label = "alt"; - }; -}; - -&spi { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1debug_default>; - - flash@0 { - status = "okay"; - label = "pnor"; - m25p,fast-read; - }; -}; - -&mac0 { - status = "okay"; - use-ncsi; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rmii1_default>; -}; - - -&uart5 { - status = "okay"; -}; - -&lpc_ctrl { - status = "okay"; - memory-region = <&flash_memory>; - flash = <&spi>; -}; - -&ibt { - status = "okay"; -}; - -&uart3 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd2_default &pinctrl_rxd2_default>; -}; - -&i2c0 { - status = "okay"; - - eeprom@50 { - compatible = "atmel,24c256"; - reg = <0x50>; - pagesize = <64>; - }; -}; - -&i2c1 { - status = "okay"; - - tmp75@49 { - compatible = "ti,tmp75"; - reg = <0x49>; - }; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c3 { - status = "okay"; -}; - -&i2c4 { - status = "okay"; - - occ-hwmon@50 { - compatible = "ibm,p8-occ-hwmon"; - reg = <0x50>; - }; -}; - -&i2c5 { - status = "okay"; - - occ-hwmon@51 { - compatible = "ibm,p8-occ-hwmon"; - reg = <0x51>; - }; -}; - -&i2c6 { - status = "okay"; - - w83795g@2f { - compatible = "nuvoton,w83795g"; - reg = <0x2f>; - }; -}; - -&i2c7 { - status = "okay"; - - occ-hwmon@56 { - compatible = "ibm,p8-occ-hwmon"; - reg = <0x56>; - }; -}; - -&i2c9 { - status = "okay"; -}; - -&i2c10 { - status = "okay"; -}; - -&i2c11 { - status = "okay"; - - occ-hwmon@57 { - compatible = "ibm,p8-occ-hwmon"; - reg = <0x57>; - }; -}; - -&i2c12 { - status = "okay"; - - rtc@68 { - compatible = "maxim,ds3231"; - reg = <0x68>; - }; -}; - -&i2c13 { - status = "okay"; -}; - -&vuart { - status = "okay"; -}; - -&wdt2 { - aspeed,alt-boot; -}; - -&sdmmc { - status = "okay"; -}; - -&sdhci1 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sd2_default>; - cd-inverted; - disable-wp; -}; diff --git a/sys/gnu/dts/arm/aspeed-bmc-opp-witherspoon.dts b/sys/gnu/dts/arm/aspeed-bmc-opp-witherspoon.dts deleted file mode 100644 index 421aa600148..00000000000 --- a/sys/gnu/dts/arm/aspeed-bmc-opp-witherspoon.dts +++ /dev/null @@ -1,659 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/dts-v1/; -#include "aspeed-g5.dtsi" -#include -#include - -/ { - model = "Witherspoon BMC"; - compatible = "ibm,witherspoon-bmc", "aspeed,ast2500"; - - chosen { - stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlyprintk"; - }; - - memory@80000000 { - reg = <0x80000000 0x20000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - flash_memory: region@98000000 { - no-map; - reg = <0x98000000 0x04000000>; /* 64M */ - }; - - gfx_memory: framebuffer { - size = <0x01000000>; - alignment = <0x01000000>; - compatible = "shared-dma-pool"; - reusable; - }; - - video_engine_memory: jpegbuffer { - size = <0x02000000>; /* 32MM */ - alignment = <0x01000000>; - compatible = "shared-dma-pool"; - reusable; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - air-water { - label = "air-water"; - gpios = <&gpio ASPEED_GPIO(B, 5) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - checkstop { - label = "checkstop"; - gpios = <&gpio ASPEED_GPIO(J, 2) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - ps0-presence { - label = "ps0-presence"; - gpios = <&gpio ASPEED_GPIO(P, 7) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - ps1-presence { - label = "ps1-presence"; - gpios = <&gpio ASPEED_GPIO(N, 0) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - iio-hwmon-battery { - compatible = "iio-hwmon"; - io-channels = <&adc 12>; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - poll-interval = <1000>; - - fan0-presence { - label = "fan0-presence"; - gpios = <&pca0 4 GPIO_ACTIVE_LOW>; - linux,code = <4>; - }; - - fan1-presence { - label = "fan1-presence"; - gpios = <&pca0 5 GPIO_ACTIVE_LOW>; - linux,code = <5>; - }; - - fan2-presence { - label = "fan2-presence"; - gpios = <&pca0 6 GPIO_ACTIVE_LOW>; - linux,code = <6>; - }; - - fan3-presence { - label = "fan3-presence"; - gpios = <&pca0 7 GPIO_ACTIVE_LOW>; - linux,code = <7>; - }; - }; - - leds { - compatible = "gpio-leds"; - - fan0 { - retain-state-shutdown; - default-state = "keep"; - gpios = <&pca0 0 GPIO_ACTIVE_LOW>; - }; - - fan1 { - retain-state-shutdown; - default-state = "keep"; - gpios = <&pca0 1 GPIO_ACTIVE_LOW>; - }; - - fan2 { - retain-state-shutdown; - default-state = "keep"; - gpios = <&pca0 2 GPIO_ACTIVE_LOW>; - }; - - fan3 { - retain-state-shutdown; - default-state = "keep"; - gpios = <&pca0 3 GPIO_ACTIVE_LOW>; - }; - - front-fault { - retain-state-shutdown; - default-state = "keep"; - gpios = <&pca0 13 GPIO_ACTIVE_LOW>; - }; - - front-power { - retain-state-shutdown; - default-state = "keep"; - gpios = <&pca0 14 GPIO_ACTIVE_LOW>; - }; - - front-id { - retain-state-shutdown; - default-state = "keep"; - gpios = <&pca0 15 GPIO_ACTIVE_LOW>; - }; - - rear-fault { - gpios = <&gpio ASPEED_GPIO(N, 2) GPIO_ACTIVE_LOW>; - }; - - rear-id { - gpios = <&gpio ASPEED_GPIO(N, 4) GPIO_ACTIVE_LOW>; - }; - - rear-power { - gpios = <&gpio ASPEED_GPIO(N, 3) GPIO_ACTIVE_LOW>; - }; - - power-button { - gpios = <&gpio ASPEED_GPIO(R, 5) GPIO_ACTIVE_LOW>; - }; - }; - - fsi: gpio-fsi { - compatible = "fsi-master-gpio", "fsi-master"; - #address-cells = <2>; - #size-cells = <0>; - no-gpio-delays; - - clock-gpios = <&gpio ASPEED_GPIO(AA, 0) GPIO_ACTIVE_HIGH>; - data-gpios = <&gpio ASPEED_GPIO(E, 0) GPIO_ACTIVE_HIGH>; - mux-gpios = <&gpio ASPEED_GPIO(A, 6) GPIO_ACTIVE_HIGH>; - enable-gpios = <&gpio ASPEED_GPIO(D, 0) GPIO_ACTIVE_HIGH>; - trans-gpios = <&gpio ASPEED_GPIO(R, 2) GPIO_ACTIVE_HIGH>; - }; - - iio-hwmon-dps310 { - compatible = "iio-hwmon"; - io-channels = <&dps 0>; - }; - - iio-hwmon-bmp280 { - compatible = "iio-hwmon"; - io-channels = <&bmp 1>; - }; - -}; - -&fmc { - status = "okay"; - - flash@0 { - status = "okay"; - label = "bmc"; - m25p,fast-read; - spi-max-frequency = <50000000>; - - partitions { - #address-cells = < 1 >; - #size-cells = < 1 >; - compatible = "fixed-partitions"; - u-boot@0 { - reg = < 0 0x60000 >; - label = "u-boot"; - }; - u-boot-env@60000 { - reg = < 0x60000 0x20000 >; - label = "u-boot-env"; - }; - obmc-ubi@80000 { - reg = < 0x80000 0x1F80000 >; - label = "obmc-ubi"; - }; - }; - }; - - flash@1 { - status = "okay"; - label = "alt-bmc"; - m25p,fast-read; - spi-max-frequency = <50000000>; - - partitions { - #address-cells = < 1 >; - #size-cells = < 1 >; - compatible = "fixed-partitions"; - u-boot@0 { - reg = < 0 0x60000 >; - label = "alt-u-boot"; - }; - u-boot-env@60000 { - reg = < 0x60000 0x20000 >; - label = "alt-u-boot-env"; - }; - obmc-ubi@80000 { - reg = < 0x80000 0x1F80000 >; - label = "alt-obmc-ubi"; - }; - }; - }; -}; - -&spi1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1_default>; - - flash@0 { - status = "okay"; - label = "pnor"; - m25p,fast-read; - spi-max-frequency = <100000000>; - }; -}; - -&uart1 { - /* Rear RS-232 connector */ - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd1_default - &pinctrl_rxd1_default - &pinctrl_nrts1_default - &pinctrl_ndtr1_default - &pinctrl_ndsr1_default - &pinctrl_ncts1_default - &pinctrl_ndcd1_default - &pinctrl_nri1_default>; -}; - -&uart2 { - /* APSS */ - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd2_default &pinctrl_rxd2_default>; -}; - -&uart5 { - status = "okay"; -}; - -&lpc_ctrl { - status = "okay"; - memory-region = <&flash_memory>; - flash = <&spi1>; -}; - -&mac0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rmii1_default>; - clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, - <&syscon ASPEED_CLK_MAC1RCLK>; - clock-names = "MACCLK", "RCLK"; - use-ncsi; -}; - -&i2c2 { - status = "okay"; - - /* MUX -> - * Samtec 1 - * Samtec 2 - */ -}; - -&i2c3 { - status = "okay"; - - bmp: bmp280@77 { - compatible = "bosch,bmp280"; - reg = <0x77>; - #io-channel-cells = <1>; - }; - - max31785@52 { - compatible = "maxim,max31785a"; - reg = <0x52>; - #address-cells = <1>; - #size-cells = <0>; - }; - - dps: dps310@76 { - compatible = "infineon,dps310"; - reg = <0x76>; - #io-channel-cells = <0>; - }; - - pca0: pca9552@60 { - compatible = "nxp,pca9552"; - reg = <0x60>; - #address-cells = <1>; - #size-cells = <0>; - - gpio-controller; - #gpio-cells = <2>; - - gpio@0 { - reg = <0>; - type = ; - }; - - gpio@1 { - reg = <1>; - type = ; - }; - - gpio@2 { - reg = <2>; - type = ; - }; - - gpio@3 { - reg = <3>; - type = ; - }; - - gpio@4 { - reg = <4>; - type = ; - }; - - gpio@5 { - reg = <5>; - type = ; - }; - - gpio@6 { - reg = <6>; - type = ; - }; - - gpio@7 { - reg = <7>; - type = ; - }; - - gpio@8 { - reg = <8>; - type = ; - }; - - gpio@9 { - reg = <9>; - type = ; - }; - - gpio@10 { - reg = <10>; - type = ; - }; - - gpio@11 { - reg = <11>; - type = ; - }; - - gpio@12 { - reg = <12>; - type = ; - }; - - gpio@13 { - reg = <13>; - type = ; - }; - - gpio@14 { - reg = <14>; - type = ; - }; - - gpio@15 { - reg = <15>; - type = ; - }; - }; - - power-supply@68 { - compatible = "ibm,cffps1"; - reg = <0x68>; - }; - - power-supply@69 { - compatible = "ibm,cffps1"; - reg = <0x69>; - }; -}; - -&i2c4 { - status = "okay"; - - tmp423a@4c { - compatible = "ti,tmp423"; - reg = <0x4c>; - }; - - ir35221@70 { - compatible = "infineon,ir35221"; - reg = <0x70>; - }; - - ir35221@71 { - compatible = "infineon,ir35221"; - reg = <0x71>; - }; -}; - - -&i2c5 { - status = "okay"; - - tmp423a@4c { - compatible = "ti,tmp423"; - reg = <0x4c>; - }; - - ir35221@70 { - compatible = "infineon,ir35221"; - reg = <0x70>; - }; - - ir35221@71 { - compatible = "infineon,ir35221"; - reg = <0x71>; - }; -}; - -&i2c9 { - status = "okay"; - - tmp275@4a { - compatible = "ti,tmp275"; - reg = <0x4a>; - }; -}; - -&i2c10 { - /* MUX - * -> PCIe Slot 3 - * -> PCIe Slot 4 - */ - status = "okay"; -}; - -&i2c11 { - status = "okay"; - - pca9552: pca9552@60 { - compatible = "nxp,pca9552"; - reg = <0x60>; - #address-cells = <1>; - #size-cells = <0>; - gpio-controller; - #gpio-cells = <2>; - - gpio-line-names = "PS_SMBUS_RESET_N", "APSS_RESET_N", - "GPU0_TH_OVERT_N_BUFF", "GPU1_TH_OVERT_N_BUFF", - "GPU2_TH_OVERT_N_BUFF", "GPU3_TH_OVERT_N_BUFF", - "GPU4_TH_OVERT_N_BUFF", "GPU5_TH_OVERT_N_BUFF", - "GPU0_PWR_GOOD_BUFF", "GPU1_PWR_GOOD_BUFF", - "GPU2_PWR_GOOD_BUFF", "GPU3_PWR_GOOD_BUFF", - "GPU4_PWR_GOOD_BUFF", "GPU5_PWR_GOOD_BUFF", - "12V_BREAKER_FLT_N", "THROTTLE_UNLATCHED_N"; - - gpio@0 { - reg = <0>; - type = ; - }; - - gpio@1 { - reg = <1>; - type = ; - }; - - gpio@2 { - reg = <2>; - type = ; - }; - - gpio@3 { - reg = <3>; - type = ; - }; - - gpio@4 { - reg = <4>; - type = ; - }; - - gpio@5 { - reg = <5>; - type = ; - }; - - gpio@6 { - reg = <6>; - type = ; - }; - - gpio@7 { - reg = <7>; - type = ; - }; - - gpio@8 { - reg = <8>; - type = ; - }; - - gpio@9 { - reg = <9>; - type = ; - }; - - gpio@10 { - reg = <10>; - type = ; - }; - - gpio@11 { - reg = <11>; - type = ; - }; - - gpio@12 { - reg = <12>; - type = ; - }; - - gpio@13 { - reg = <13>; - type = ; - }; - - gpio@14 { - reg = <14>; - type = ; - }; - - gpio@15 { - reg = <15>; - type = ; - }; - }; - - rtc@32 { - compatible = "epson,rx8900"; - reg = <0x32>; - }; - - eeprom@51 { - compatible = "atmel,24c64"; - reg = <0x51>; - }; - - ucd90160@64 { - compatible = "ti,ucd90160"; - reg = <0x64>; - }; -}; - -&i2c12 { - status = "okay"; -}; - -&i2c13 { - status = "okay"; -}; - -&vuart { - status = "okay"; -}; - -&gfx { - status = "okay"; - memory-region = <&gfx_memory>; -}; - -&pinctrl { - aspeed,external-nodes = <&gfx &lhc>; -}; - -&wdt1 { - aspeed,reset-type = "none"; - aspeed,external-signal; - aspeed,ext-push-pull; - aspeed,ext-active-high; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdtrst1_default>; -}; - -&wdt2 { - aspeed,alt-boot; -}; - -&ibt { - status = "okay"; -}; - -&adc { - status = "okay"; -}; - -&vhub { - status = "okay"; -}; - -&video { - status = "okay"; - memory-region = <&video_engine_memory>; -}; - -#include "ibm-power9-dual.dtsi" diff --git a/sys/gnu/dts/arm/aspeed-bmc-opp-zaius.dts b/sys/gnu/dts/arm/aspeed-bmc-opp-zaius.dts deleted file mode 100644 index bc60ec29168..00000000000 --- a/sys/gnu/dts/arm/aspeed-bmc-opp-zaius.dts +++ /dev/null @@ -1,549 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; -#include "aspeed-g5.dtsi" -#include - -/ { - model = "Zaius BMC"; - compatible = "ingrasys,zaius-bmc", "aspeed,ast2500"; - - aliases { - i2c15 = &i2cpcie0; - i2c16 = &i2cpcie1; - i2c17 = &i2cpcie2; - i2c19 = &i2cpcie3; - i2c20 = &i2cpcie4; - }; - - chosen { - stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlyprintk"; - }; - - memory@80000000 { - reg = <0x80000000 0x40000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - flash_memory: region@98000000 { - no-map; - reg = <0x98000000 0x04000000>; /* 64M */ - }; - }; - - onewire0 { - compatible = "w1-gpio"; - gpios = <&gpio ASPEED_GPIO(H, 0) GPIO_ACTIVE_HIGH>; - }; - - onewire1 { - compatible = "w1-gpio"; - gpios = <&gpio ASPEED_GPIO(H, 1) GPIO_ACTIVE_HIGH>; - }; - - onewire2 { - compatible = "w1-gpio"; - gpios = <&gpio ASPEED_GPIO(H, 2) GPIO_ACTIVE_HIGH>; - }; - - onewire3 { - compatible = "w1-gpio"; - gpios = <&gpio ASPEED_GPIO(H, 3) GPIO_ACTIVE_HIGH>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - checkstop { - label = "checkstop"; - gpios = <&gpio ASPEED_GPIO(F, 7) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - pcie-e2b-present{ - label = "pcie-e2b-present"; - gpios = <&gpio ASPEED_GPIO(E, 7) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - leds { - compatible = "gpio-leds"; - - sys_boot_status { - label = "System boot status"; - gpios = <&gpio ASPEED_GPIO(D, 5) GPIO_ACTIVE_LOW>; - }; - - attention { - label = "Attention"; - gpios = <&gpio ASPEED_GPIO(D, 6) GPIO_ACTIVE_LOW>; - }; - - plt_fault { - label = "Platform fault"; - gpios = <&gpio ASPEED_GPIO(D, 7) GPIO_ACTIVE_LOW>; - }; - - hdd_fault { - label = "Onboard drive fault"; - gpios = <&gpio ASPEED_GPIO(AA, 2) GPIO_ACTIVE_LOW>; - }; - }; - - fsi: gpio-fsi { - compatible = "fsi-master-gpio", "fsi-master"; - #address-cells = <2>; - #size-cells = <0>; - no-gpio-delays; - - trans-gpios = <&gpio ASPEED_GPIO(O, 6) GPIO_ACTIVE_HIGH>; - enable-gpios = <&gpio ASPEED_GPIO(D, 0) GPIO_ACTIVE_HIGH>; - clock-gpios = <&gpio ASPEED_GPIO(G, 0) GPIO_ACTIVE_HIGH>; - data-gpios = <&gpio ASPEED_GPIO(G, 1) GPIO_ACTIVE_HIGH>; - mux-gpios = <&gpio ASPEED_GPIO(P, 6) GPIO_ACTIVE_HIGH>; - }; - - iio-hwmon { - compatible = "iio-hwmon"; - io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, - <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>, - <&adc 8>, <&adc 9>, <&adc 10>, <&adc 11>, - <&adc 13>, <&adc 14>, <&adc 15>; - }; - - iio-hwmon-battery { - compatible = "iio-hwmon"; - io-channels = <&adc 12>; - }; - -}; - -&fmc { - status = "okay"; - - flash@0 { - status = "okay"; - label = "bmc"; - m25p,fast-read; - spi-max-frequency = <50000000>; -#include "openbmc-flash-layout.dtsi" - }; -}; - -&spi1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1_default>; - - flash@0 { - status = "okay"; - label = "pnor"; - m25p,fast-read; - spi-max-frequency = <100000000>; - }; -}; - -&spi2 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi2ck_default - &pinctrl_spi2cs0_default - &pinctrl_spi2cs1_default - &pinctrl_spi2miso_default - &pinctrl_spi2mosi_default>; - - flash@0 { - status = "okay"; - }; -}; - -&uart1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd1_default - &pinctrl_rxd1_default>; -}; - -&lpc_ctrl { - status = "okay"; - memory-region = <&flash_memory>; - flash = <&spi1>; -}; - -&lpc_snoop { - status = "okay"; - snoop-ports = <0x80>; -}; - - -&uart5 { - status = "okay"; -}; - -&mac0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rmii1_default>; - clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, - <&syscon ASPEED_CLK_MAC1RCLK>; - clock-names = "MACCLK", "RCLK"; - use-ncsi; -}; - -&mac1 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; -}; - -&i2c0 { - status = "okay"; - - eeprom@50 { - compatible = "atmel,24c64"; - reg = <0x50>; - pagesize = <32>; - }; - - rtc@68 { - compatible = "nxp,pcf8523"; - reg = <0x68>; - }; - - ucd90160@64 { - compatible = "ti,ucd90160"; - reg = <0x64>; - }; - - /* Power sequencer UCD90160 PMBUS @64h - * FRU AT24C64D @50h - * RTC PCF8523 @68h - * Clock buffer 9DBL04 @6dh - */ -}; - -&i2c1 { - status = "okay"; - - i2c-switch@71 { - compatible = "nxp,pca9546"; - reg = <0x71>; - #address-cells = <1>; - #size-cells = <0>; - - i2cpcie0: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - i2cpcie1: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - i2cpcie2: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - i2ctpm: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - }; - - /* MUX1 PCA9546A @71h - * PCIe 0 - * PCIe 1 - * PCIe 2 - * TPM header - */ -}; - -&i2c2 { - status = "disabled"; - - /* OCP Mezz Connector A (OOB SMBUS) */ -}; - -&i2c3 { - status = "disabled"; - - /* OCP Mezz Connector A (PCIe slot SMBUS) */ -}; - -&i2c4 { - status = "okay"; - - i2c-switch@71 { - compatible = "nxp,pca9546"; - reg = <0x71>; - #address-cells = <1>; - #size-cells = <0>; - - i2cpcie3: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - i2cpcie4: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - }; - - /* MUX1 PCA9546A @71h - * PCIe 3 - * PCIe 4 - */ -}; - - -&i2c5 { - status = "disabled"; - - /* CPU0 PRM 0.7V */ - /* CPU0 PRM 1.2V CH03 */ - /* CPU0 PRM 0.8V */ - /* CPU0 PRM 1.2V CH47 */ -}; - -&i2c6 { - status = "disabled"; - - /* CPU1 PRM 0.7V */ - /* CPU1 PRM 1.2V CH03 */ - /* CPU1 PRM 0.8V */ - /* CPU1 PRM 1.2V CH47 */ -}; - -&i2c7 { - status = "okay"; - - pca9541a@70 { - compatible = "nxp,pca9541"; - reg = <0x70>; - - i2c-arb { - #address-cells = <1>; - #size-cells = <0>; - - hotswap@54 { - compatible = "ti,lm5066i"; - reg = <0x54>; - }; - }; - - }; - - vrm@64 { - compatible = "isil,isl68137"; - reg = <0x64>; - }; - - vrm@40 { - compatible = "isil,isl68137"; - reg = <0x40>; - }; - - vrm@60 { - compatible = "isil,isl68137"; - reg = <0x60>; - }; - - vrm@43 { - compatible = "infineon,ir38064"; - reg = <0x43>; - }; - - vrm@41 { - compatible = "isil,isl68137"; - reg = <0x41>; - }; - - /* Master selector PCA9541A @70h (other master: CPU0) - * LM5066I PMBUS @10h - */ - - /* - * Brick will be one of these types/addresses. Depending - * on the board SKU only one is actually present and will successfully - * instantiate while the others will fail the probe operation. - * These are the PVT (and presumably beyond) addresses: - * 12V Quarter Brick DC/DC Converter Q54SJ12050 @6Ah - * 12V Quarter Brick DC/DC Converter Q54SH12050 @30h - */ - power-brick@6a { - compatible = "delta,dps800"; - reg = <0x6a>; - }; - power-brick@30 { - compatible = "delta,dps800"; - reg = <0x30>; - }; - - /* CPU0 VR ISL68137 0.7V, 0.96V PMBUS @64h */ - /* CPU0 VR ISL68137 1.2V CH03 PMBUS @40h */ - /* CPU0 VR ISL68137 0.8V PMBUS @60h */ - /* CPU0 VR 1.0V IR38064 I2C @11h, PMBUS @43h */ - /* CPU0 VR ISL68137 1.2V CH47 PMBUS @41h */ - /* Master selector PCA9541A @70h (other master: CPU0) - * LM5066I PMBUS @10h - */ -}; - -&i2c8 { - status = "okay"; - - vrm@64 { - compatible = "isil,isl68137"; - reg = <0x64>; - }; - - vrm@40 { - compatible = "isil,isl68137"; - reg = <0x40>; - }; - - vrm@41 { - compatible = "isil,isl68137"; - reg = <0x41>; - }; - - vrm@42 { - compatible = "infineon,ir38064"; - reg = <0x42>; - }; - - vrm@60 { - compatible = "isil,isl68137"; - reg = <0x60>; - }; - - /* CPU1 VR ISL68137 0.7V, 0.96V PMBUS @64h */ - /* CPU1 VR ISL68137 1.2V CH03 PMBUS @40h */ - /* CPU1 VR ISL68137 1.2V CH47 PMBUS @41h */ - /* CPU1 VR 1.0V IR38064 I2C @12h, PMBUS @42h */ - /* CPU1 VR ISL68137 0.8V PMBUS @60h */ -}; - - -&i2c9 { - status = "disabled"; - - /* Fan board */ -}; - -&i2c10 { - status = "disabled"; -}; - -&i2c11 { - status = "disabled"; - - /* GPU sideband */ -}; - -&i2c12 { - status = "disabled"; -}; - -&i2c13 { - status = "disabled"; - - /* MUX PI3USB102 - * CPU0 debug - * CPU1 debug - */ -}; - -&pinctrl { - aspeed,external-nodes = <&gfx &lhc>; - - pinctrl_gpioh_unbiased: gpioi_unbiased { - pins = "A8", "C7", "B7", "A7", "D7", "B6", "A6", "E7"; - bias-disable; - }; -}; - -&gpio { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpioh_unbiased>; - - line_iso_u146_en { - gpio-hog; - gpios = ; - output-high; - line-name = "iso_u164_en"; - }; - - ncsi_mux_en_n { - gpio-hog; - gpios = ; - output-low; - line-name = "ncsi_mux_en_n"; - }; - - line_bmc_i2c2_sw_rst_n { - gpio-hog; - gpios = ; - output-high; - line-name = "bmc_i2c2_sw_rst_n"; - }; - - line_bmc_i2c5_sw_rst_n { - gpio-hog; - gpios = ; - output-high; - line-name = "bmc_i2c5_sw_rst_n"; - }; -}; - -&vuart { - status = "okay"; -}; - -&gfx { - status = "okay"; -}; - -&pwm_tacho { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default - &pinctrl_pwm2_default &pinctrl_pwm3_default>; - - fan@0 { - reg = <0x00>; - aspeed,fan-tach-ch = /bits/ 8 <0x00>; - }; - - fan@1 { - reg = <0x01>; - aspeed,fan-tach-ch = /bits/ 8 <0x01>; - }; - - fan@2 { - reg = <0x02>; - aspeed,fan-tach-ch = /bits/ 8 <0x02>; - }; - - fan@3 { - reg = <0x03>; - aspeed,fan-tach-ch = /bits/ 8 <0x03>; - }; -}; - -&ibt { - status = "okay"; -}; - -#include "ibm-power9-dual.dtsi" diff --git a/sys/gnu/dts/arm/aspeed-bmc-portwell-neptune.dts b/sys/gnu/dts/arm/aspeed-bmc-portwell-neptune.dts deleted file mode 100644 index 4a1ca8f5b6a..00000000000 --- a/sys/gnu/dts/arm/aspeed-bmc-portwell-neptune.dts +++ /dev/null @@ -1,165 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (c) 2017 Facebook Inc. -/dts-v1/; - -#include "aspeed-g5.dtsi" -#include - -/ { - model = "Portwell Neptune BMC"; - compatible = "portwell,neptune-bmc", "aspeed,ast2500"; - aliases { - serial0 = &uart1; - serial4 = &uart5; - }; - chosen { - stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlyprintk"; - }; - - memory@80000000 { - reg = <0x80000000 0x20000000>; - }; - - leds { - compatible = "gpio-leds"; - postcode0 { - label="BMC_UP"; - gpios = <&gpio ASPEED_GPIO(H, 0) GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - postcode1 { - label="BMC_HB"; - gpios = <&gpio ASPEED_GPIO(H, 1) GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - postcode2 { - label="FAULT"; - gpios = <&gpio ASPEED_GPIO(H, 2) GPIO_ACTIVE_HIGH>; - }; - // postcode3-7 are GPIOH3-H7 - }; -}; - -&fmc { - status = "okay"; - flash@0 { - status = "okay"; - m25p,fast-read; -#include "openbmc-flash-layout.dtsi" - }; -}; - -&spi1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1_default>; - flash@0 { - status = "okay"; - m25p,fast-read; - label = "pnor"; - }; -}; - -&uart1 { - // Host Console - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd1_default - &pinctrl_rxd1_default>; -}; - -&uart5 { - // BMC Console - status = "okay"; -}; - -&mac0 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rmii1_default - &pinctrl_mdio1_default>; - clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, - <&syscon ASPEED_CLK_MAC1RCLK>; - clock-names = "MACCLK", "RCLK"; -}; - -&mac1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rmii2_default>; - clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>, - <&syscon ASPEED_CLK_MAC2RCLK>; - clock-names = "MACCLK", "RCLK"; - use-ncsi; -}; - -&i2c1 { - status = "okay"; - // To PCIe slot SMBUS -}; - -&i2c2 { - status = "okay"; - // To LAN I210 -}; - -&i2c3 { - status = "okay"; - // SMBus to COMe AB -}; - -&i2c4 { - status = "okay"; - // I2C to COMe AB -}; - -&i2c5 { - status = "okay"; -// USB Debug card - pca9555@27 { - compatible = "nxp,pca9555"; - reg = <0x27>; - }; -}; - -&i2c6 { - status = "okay"; - tpm@20 { - compatible = "infineon,slb9645tt"; - reg = <0x20>; - }; - tmp421@4e { - compatible = "ti,tmp421"; - reg = <0x4e>; - }; - tmp421@4f { - compatible = "ti,tmp421"; - reg = <0x4f>; - }; -}; - -&i2c8 { - status = "okay"; - eeprom@51 { - compatible = "atmel,24c128"; - reg = <0x51>; - pagesize = <32>; - }; -}; - -&pwm_tacho { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default>; - fan@0 { - reg = <0x00>; - aspeed,fan-tach-ch = /bits/ 8 <0x00>; - }; - - fan@1 { - reg = <0x00>; - aspeed,fan-tach-ch = /bits/ 8 <0x01>; - }; -}; diff --git a/sys/gnu/dts/arm/aspeed-bmc-quanta-q71l.dts b/sys/gnu/dts/arm/aspeed-bmc-quanta-q71l.dts deleted file mode 100644 index a68ff0675c2..00000000000 --- a/sys/gnu/dts/arm/aspeed-bmc-quanta-q71l.dts +++ /dev/null @@ -1,518 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; -#include "aspeed-g4.dtsi" -#include - -/ { - model = "Quanta Q71L BMC"; - compatible = "quanta,q71l-bmc", "aspeed,ast2400"; - - aliases { - i2c14 = &i2c_pcie2; - i2c15 = &i2c_pcie3; - i2c16 = &i2c_pcie6; - i2c17 = &i2c_pcie7; - i2c18 = &i2c_pcie1; - i2c19 = &i2c_pcie4; - i2c20 = &i2c_pcie5; - i2c21 = &i2c_pcie8; - i2c22 = &i2c_pcie9; - i2c23 = &i2c_pcie10; - i2c24 = &i2c_ssd1; - i2c25 = &i2c_ssd2; - i2c26 = &i2c_psu4; - i2c27 = &i2c_psu1; - i2c28 = &i2c_psu3; - i2c29 = &i2c_psu2; - }; - - chosen { - stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlyprintk"; - }; - - memory@40000000 { - reg = <0x40000000 0x8000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - vga_memory: framebuffer@47800000 { - no-map; - reg = <0x47800000 0x00800000>; /* 8MB */ - }; - }; - - leds { - compatible = "gpio-leds"; - - heartbeat { - gpios = <&gpio ASPEED_GPIO(B, 0) GPIO_ACTIVE_LOW>; - }; - - power { - gpios = <&gpio ASPEED_GPIO(B, 2) GPIO_ACTIVE_LOW>; - }; - - identify { - gpios = <&gpio ASPEED_GPIO(B, 3) GPIO_ACTIVE_LOW>; - }; - }; - - iio-hwmon { - compatible = "iio-hwmon"; - io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, - <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>, - <&adc 8>, <&adc 9>, <&adc 10>; - }; - - iio-hwmon-battery { - compatible = "iio-hwmon"; - io-channels = <&adc 11>; - }; - - i2c1mux: i2cmux { - compatible = "i2c-mux-gpio"; - #address-cells = <1>; - #size-cells = <0>; - - /* mux-gpios = <&sgpio 10 GPIO_ACTIVE_HIGH> */ - i2c-parent = <&i2c1>; - }; -}; - -&fmc { - status = "okay"; - flash@0 { - status = "okay"; - label = "bmc"; - m25p,fast-read; -#include "openbmc-flash-layout.dtsi" - }; -}; - -&spi { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1_default>; - - flash@0 { - status = "okay"; - m25p,fast-read; - label = "pnor"; - }; -}; - -&pinctrl { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_vgahs_default &pinctrl_vgavs_default - &pinctrl_ddcclk_default &pinctrl_ddcdat_default>; -}; - -&p2a { - status = "okay"; - memory-region = <&vga_memory>; -}; - -&ibt { - status = "okay"; -}; - -&lpc_ctrl { - status = "okay"; -}; - -&lpc_snoop { - status = "okay"; - snoop-ports = <0x80>; -}; - -&mac0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rmii1_default>; - use-ncsi; -}; - -&mac1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; -}; - -&uart1 { - status = "okay"; -}; - -&uart5 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; -}; - -&i2c1 { - status = "okay"; - - /* temp2 inlet */ - tmp75@4c { - compatible = "ti,tmp75"; - reg = <0x4c>; - }; - - /* temp3 */ - tmp75@4e { - compatible = "ti,tmp75"; - reg = <0x4e>; - }; - - /* temp1 */ - tmp75@4f { - compatible = "ti,tmp75"; - reg = <0x4f>; - }; - - /* Baseboard FRU */ - eeprom@54 { - compatible = "atmel,24c64"; - reg = <0x54>; - }; - - /* FP FRU */ - eeprom@57 { - compatible = "atmel,24c64"; - reg = <0x57>; - }; -}; - -&i2c2 { - status = "okay"; - - /* 0: PCIe Slot 2, - * Slot 3, - * Slot 6, - * Slot 7 - */ - i2c-switch@74 { - compatible = "nxp,pca9546"; - reg = <0x74>; - #address-cells = <1>; - #size-cells = <0>; - i2c-mux-idle-disconnect; /* may use mux@77 next. */ - - i2c_pcie2: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - i2c_pcie3: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - i2c_pcie6: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - i2c_pcie7: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - }; - - /* 0: PCIe Slot 1, - * Slot 4, - * Slot 5, - * Slot 8, - * Slot 9, - * Slot 10, - * SSD 1, - * SSD 2 - */ - i2c-switch@77 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x77>; - i2c-mux-idle-disconnect; /* may use mux@74 next. */ - - i2c_pcie1: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - i2c_pcie4: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - i2c_pcie5: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - i2c_pcie8: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - - i2c_pcie9: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - - i2c_pcie10: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - - i2c_ssd1: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - }; - - i2c_ssd2: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - }; -}; - -&i2c3 { - status = "okay"; - - /* BIOS FRU */ - eeprom@56 { - compatible = "atmel,24c64"; - reg = <0x56>; - }; -}; - -&i2c4 { - status = "okay"; -}; - -&i2c5 { - status = "okay"; -}; - -&i2c6 { - status = "okay"; -}; - -&i2c7 { - status = "okay"; - - /* 0: PSU4 - * PSU1 - * PSU3 - * PSU2 - */ - i2c-switch@70 { - compatible = "nxp,pca9546"; - reg = <0x70>; - #address-cells = <1>; - #size-cells = <0>; - - i2c_psu4: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - psu@59 { - compatible = "pmbus"; - reg = <0x59>; - }; - }; - - i2c_psu1: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - psu@58 { - compatible = "pmbus"; - reg = <0x58>; - }; - }; - - i2c_psu3: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - - psu@58 { - compatible = "pmbus"; - reg = <0x58>; - }; - }; - - i2c_psu2: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - - psu@59 { - compatible = "pmbus"; - reg = <0x59>; - }; - }; - }; - - /* PDB FRU */ - eeprom@52 { - compatible = "atmel,24c64"; - reg = <0x52>; - }; -}; - -&i2c8 { - status = "okay"; - - /* BMC FRU */ - eeprom@50 { - compatible = "atmel,24c64"; - reg = <0x50>; - }; -}; - -&vuart { - status = "okay"; -}; - -&wdt2 { - status = "okay"; -}; - -&adc { - status = "okay"; -}; - -&pwm_tacho { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm0_default - &pinctrl_pwm1_default - &pinctrl_pwm2_default - &pinctrl_pwm3_default>; - - fan@0 { - reg = <0x00>; - aspeed,fan-tach-ch = /bits/ 8 <0x00>; - }; - - fan@1 { - reg = <0x01>; - aspeed,fan-tach-ch = /bits/ 8 <0x01>; - }; - - fan@2 { - reg = <0x02>; - aspeed,fan-tach-ch = /bits/ 8 <0x02>; - }; - - fan@3 { - reg = <0x03>; - aspeed,fan-tach-ch = /bits/ 8 <0x03>; - }; - - fan@4 { - reg = <0x00>; - aspeed,fan-tach-ch = /bits/ 8 <0x04>; - }; - - fan@5 { - reg = <0x01>; - aspeed,fan-tach-ch = /bits/ 8 <0x05>; - }; - - fan@6 { - reg = <0x02>; - aspeed,fan-tach-ch = /bits/ 8 <0x06>; - }; - - fan@7 { - reg = <0x03>; - aspeed,fan-tach-ch = /bits/ 8 <0x07>; - }; -}; - -&i2c1mux { - i2c@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - /* Memory Riser 1 FRU */ - eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - }; - - /* Memory Riser 2 FRU */ - eeprom@51 { - compatible = "atmel,24c02"; - reg = <0x51>; - }; - - /* Memory Riser 3 FRU */ - eeprom@52 { - compatible = "atmel,24c02"; - reg = <0x52>; - }; - - /* Memory Riser 4 FRU */ - eeprom@53 { - compatible = "atmel,24c02"; - reg = <0x53>; - }; - }; - - i2c@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - /* Memory Riser 5 FRU */ - eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - }; - - /* Memory Riser 6 FRU */ - eeprom@51 { - compatible = "atmel,24c02"; - reg = <0x51>; - }; - - /* Memory Riser 7 FRU */ - eeprom@52 { - compatible = "atmel,24c02"; - reg = <0x52>; - }; - - /* Memory Riser 8 FRU */ - eeprom@53 { - compatible = "atmel,24c02"; - reg = <0x53>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/aspeed-g4.dtsi b/sys/gnu/dts/arm/aspeed-g4.dtsi deleted file mode 100644 index 807a0fc2067..00000000000 --- a/sys/gnu/dts/arm/aspeed-g4.dtsi +++ /dev/null @@ -1,1423 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -#include - -/ { - model = "Aspeed BMC"; - compatible = "aspeed,ast2400"; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&vic>; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - i2c6 = &i2c6; - i2c7 = &i2c7; - i2c8 = &i2c8; - i2c9 = &i2c9; - i2c10 = &i2c10; - i2c11 = &i2c11; - i2c12 = &i2c12; - i2c13 = &i2c13; - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - serial3 = &uart4; - serial4 = &uart5; - serial5 = &vuart; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "arm,arm926ej-s"; - device_type = "cpu"; - reg = <0>; - }; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0>; - }; - - ahb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - fmc: spi@1e620000 { - reg = < 0x1e620000 0x94 - 0x20000000 0x10000000 >; - #address-cells = <1>; - #size-cells = <0>; - compatible = "aspeed,ast2400-fmc"; - clocks = <&syscon ASPEED_CLK_AHB>; - status = "disabled"; - interrupts = <19>; - flash@0 { - reg = < 0 >; - compatible = "jedec,spi-nor"; - spi-max-frequency = <50000000>; - status = "disabled"; - }; - flash@1 { - reg = < 1 >; - compatible = "jedec,spi-nor"; - status = "disabled"; - }; - flash@2 { - reg = < 2 >; - compatible = "jedec,spi-nor"; - status = "disabled"; - }; - flash@3 { - reg = < 3 >; - compatible = "jedec,spi-nor"; - status = "disabled"; - }; - flash@4 { - reg = < 4 >; - compatible = "jedec,spi-nor"; - status = "disabled"; - }; - }; - - spi: spi@1e630000 { - reg = < 0x1e630000 0x18 - 0x30000000 0x10000000 >; - #address-cells = <1>; - #size-cells = <0>; - compatible = "aspeed,ast2400-spi"; - clocks = <&syscon ASPEED_CLK_AHB>; - status = "disabled"; - flash@0 { - reg = < 0 >; - compatible = "jedec,spi-nor"; - spi-max-frequency = <50000000>; - status = "disabled"; - }; - }; - - vic: interrupt-controller@1e6c0080 { - compatible = "aspeed,ast2400-vic"; - interrupt-controller; - #interrupt-cells = <1>; - valid-sources = <0xffffffff 0x0007ffff>; - reg = <0x1e6c0080 0x80>; - }; - - cvic: copro-interrupt-controller@1e6c2000 { - compatible = "aspeed,ast2400-cvic", "aspeed-cvic"; - valid-sources = <0x7fffffff>; - reg = <0x1e6c2000 0x80>; - }; - - mac0: ethernet@1e660000 { - compatible = "aspeed,ast2400-mac", "faraday,ftgmac100"; - reg = <0x1e660000 0x180>; - interrupts = <2>; - clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>; - status = "disabled"; - }; - - mac1: ethernet@1e680000 { - compatible = "aspeed,ast2400-mac", "faraday,ftgmac100"; - reg = <0x1e680000 0x180>; - interrupts = <3>; - clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>; - status = "disabled"; - }; - - ehci0: usb@1e6a1000 { - compatible = "aspeed,ast2400-ehci", "generic-ehci"; - reg = <0x1e6a1000 0x100>; - interrupts = <5>; - clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb2h_default>; - status = "disabled"; - }; - - uhci: usb@1e6b0000 { - compatible = "aspeed,ast2400-uhci", "generic-uhci"; - reg = <0x1e6b0000 0x100>; - interrupts = <14>; - #ports = <3>; - clocks = <&syscon ASPEED_CLK_GATE_USBUHCICLK>; - status = "disabled"; - /* - * No default pinmux, it will follow EHCI, use an explicit pinmux - * override if you don't enable EHCI - */ - }; - - vhub: usb-vhub@1e6a0000 { - compatible = "aspeed,ast2400-usb-vhub"; - reg = <0x1e6a0000 0x300>; - interrupts = <5>; - clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb2d_default>; - status = "disabled"; - }; - - apb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - syscon: syscon@1e6e2000 { - compatible = "aspeed,ast2400-scu", "syscon", "simple-mfd"; - reg = <0x1e6e2000 0x1a8>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1e6e2000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - - p2a: p2a-control@2c { - reg = <0x2c 0x4>; - compatible = "aspeed,ast2400-p2a-ctrl"; - status = "disabled"; - }; - - pinctrl: pinctrl@80 { - reg = <0x80 0x18>, <0xa0 0x10>; - compatible = "aspeed,ast2400-pinctrl"; - }; - }; - - rng: hwrng@1e6e2078 { - compatible = "timeriomem_rng"; - reg = <0x1e6e2078 0x4>; - period = <1>; - quality = <100>; - }; - - adc: adc@1e6e9000 { - compatible = "aspeed,ast2400-adc"; - reg = <0x1e6e9000 0xb0>; - clocks = <&syscon ASPEED_CLK_APB>; - resets = <&syscon ASPEED_RESET_ADC>; - #io-channel-cells = <1>; - status = "disabled"; - }; - - sram: sram@1e720000 { - compatible = "mmio-sram"; - reg = <0x1e720000 0x8000>; // 32K - }; - - sdmmc: sd-controller@1e740000 { - compatible = "aspeed,ast2400-sd-controller"; - reg = <0x1e740000 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1e740000 0x10000>; - clocks = <&syscon ASPEED_CLK_GATE_SDCLK>; - status = "disabled"; - - sdhci0: sdhci@100 { - compatible = "aspeed,ast2400-sdhci"; - reg = <0x100 0x100>; - interrupts = <26>; - sdhci,auto-cmd12; - clocks = <&syscon ASPEED_CLK_SDIO>; - status = "disabled"; - }; - - sdhci1: sdhci@200 { - compatible = "aspeed,ast2400-sdhci"; - reg = <0x200 0x100>; - interrupts = <26>; - sdhci,auto-cmd12; - clocks = <&syscon ASPEED_CLK_SDIO>; - status = "disabled"; - }; - }; - - gpio: gpio@1e780000 { - #gpio-cells = <2>; - gpio-controller; - compatible = "aspeed,ast2400-gpio"; - reg = <0x1e780000 0x1000>; - interrupts = <20>; - gpio-ranges = <&pinctrl 0 0 220>; - clocks = <&syscon ASPEED_CLK_APB>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - timer: timer@1e782000 { - /* This timer is a Faraday FTTMR010 derivative */ - compatible = "aspeed,ast2400-timer"; - reg = <0x1e782000 0x90>; - interrupts = <16 17 18 35 36 37 38 39>; - clocks = <&syscon ASPEED_CLK_APB>; - clock-names = "PCLK"; - }; - - rtc: rtc@1e781000 { - compatible = "aspeed,ast2400-rtc"; - reg = <0x1e781000 0x18>; - status = "disabled"; - }; - - uart1: serial@1e783000 { - compatible = "ns16550a"; - reg = <0x1e783000 0x20>; - reg-shift = <2>; - interrupts = <9>; - clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>; - resets = <&lpc_reset 4>; - no-loopback-test; - status = "disabled"; - }; - - uart5: serial@1e784000 { - compatible = "ns16550a"; - reg = <0x1e784000 0x20>; - reg-shift = <2>; - interrupts = <10>; - clocks = <&syscon ASPEED_CLK_GATE_UART5CLK>; - no-loopback-test; - status = "disabled"; - }; - - wdt1: watchdog@1e785000 { - compatible = "aspeed,ast2400-wdt"; - reg = <0x1e785000 0x1c>; - clocks = <&syscon ASPEED_CLK_APB>; - }; - - wdt2: watchdog@1e785020 { - compatible = "aspeed,ast2400-wdt"; - reg = <0x1e785020 0x1c>; - clocks = <&syscon ASPEED_CLK_APB>; - }; - - pwm_tacho: pwm-tacho-controller@1e786000 { - compatible = "aspeed,ast2400-pwm-tacho"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x1e786000 0x1000>; - clocks = <&syscon ASPEED_CLK_24M>; - resets = <&syscon ASPEED_RESET_PWM>; - status = "disabled"; - }; - - vuart: serial@1e787000 { - compatible = "aspeed,ast2400-vuart"; - reg = <0x1e787000 0x40>; - reg-shift = <2>; - interrupts = <8>; - clocks = <&syscon ASPEED_CLK_APB>; - no-loopback-test; - status = "disabled"; - }; - - lpc: lpc@1e789000 { - compatible = "aspeed,ast2400-lpc", "simple-mfd"; - reg = <0x1e789000 0x1000>; - - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x1e789000 0x1000>; - - lpc_bmc: lpc-bmc@0 { - compatible = "aspeed,ast2400-lpc-bmc"; - reg = <0x0 0x80>; - }; - - lpc_host: lpc-host@80 { - compatible = "aspeed,ast2400-lpc-host", "simple-mfd", "syscon"; - reg = <0x80 0x1e0>; - reg-io-width = <4>; - - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x80 0x1e0>; - - lpc_ctrl: lpc-ctrl@0 { - compatible = "aspeed,ast2400-lpc-ctrl"; - reg = <0x0 0x10>; - clocks = <&syscon ASPEED_CLK_GATE_LCLK>; - status = "disabled"; - }; - - lpc_snoop: lpc-snoop@10 { - compatible = "aspeed,ast2400-lpc-snoop"; - reg = <0x10 0x8>; - interrupts = <8>; - status = "disabled"; - }; - - lhc: lhc@20 { - compatible = "aspeed,ast2400-lhc"; - reg = <0x20 0x24 0x48 0x8>; - }; - - lpc_reset: reset-controller@18 { - compatible = "aspeed,ast2400-lpc-reset"; - reg = <0x18 0x4>; - #reset-cells = <1>; - }; - - ibt: ibt@c0 { - compatible = "aspeed,ast2400-ibt-bmc"; - reg = <0xc0 0x18>; - interrupts = <8>; - status = "disabled"; - }; - }; - }; - - uart2: serial@1e78d000 { - compatible = "ns16550a"; - reg = <0x1e78d000 0x20>; - reg-shift = <2>; - interrupts = <32>; - clocks = <&syscon ASPEED_CLK_GATE_UART2CLK>; - resets = <&lpc_reset 5>; - no-loopback-test; - status = "disabled"; - }; - - uart3: serial@1e78e000 { - compatible = "ns16550a"; - reg = <0x1e78e000 0x20>; - reg-shift = <2>; - interrupts = <33>; - clocks = <&syscon ASPEED_CLK_GATE_UART3CLK>; - resets = <&lpc_reset 6>; - no-loopback-test; - status = "disabled"; - }; - - uart4: serial@1e78f000 { - compatible = "ns16550a"; - reg = <0x1e78f000 0x20>; - reg-shift = <2>; - interrupts = <34>; - clocks = <&syscon ASPEED_CLK_GATE_UART4CLK>; - resets = <&lpc_reset 7>; - no-loopback-test; - status = "disabled"; - }; - - i2c: bus@1e78a000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1e78a000 0x1000>; - }; - }; - }; -}; - -&i2c { - i2c_ic: interrupt-controller@0 { - #interrupt-cells = <1>; - compatible = "aspeed,ast2400-i2c-ic"; - reg = <0x0 0x40>; - interrupts = <12>; - interrupt-controller; - }; - - i2c0: i2c-bus@40 { - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - - reg = <0x40 0x40>; - compatible = "aspeed,ast2400-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB>; - resets = <&syscon ASPEED_RESET_I2C>; - bus-frequency = <100000>; - interrupts = <0>; - interrupt-parent = <&i2c_ic>; - status = "disabled"; - /* Does not need pinctrl properties */ - }; - - i2c1: i2c-bus@80 { - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - - reg = <0x80 0x40>; - compatible = "aspeed,ast2400-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB>; - resets = <&syscon ASPEED_RESET_I2C>; - bus-frequency = <100000>; - interrupts = <1>; - interrupt-parent = <&i2c_ic>; - status = "disabled"; - /* Does not need pinctrl properties */ - }; - - i2c2: i2c-bus@c0 { - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - - reg = <0xc0 0x40>; - compatible = "aspeed,ast2400-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB>; - resets = <&syscon ASPEED_RESET_I2C>; - bus-frequency = <100000>; - interrupts = <2>; - interrupt-parent = <&i2c_ic>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3_default>; - status = "disabled"; - }; - - i2c3: i2c-bus@100 { - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - - reg = <0x100 0x40>; - compatible = "aspeed,ast2400-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB>; - resets = <&syscon ASPEED_RESET_I2C>; - bus-frequency = <100000>; - interrupts = <3>; - interrupt-parent = <&i2c_ic>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4_default>; - status = "disabled"; - }; - - i2c4: i2c-bus@140 { - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - - reg = <0x140 0x40>; - compatible = "aspeed,ast2400-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB>; - resets = <&syscon ASPEED_RESET_I2C>; - bus-frequency = <100000>; - interrupts = <4>; - interrupt-parent = <&i2c_ic>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c5_default>; - status = "disabled"; - }; - - i2c5: i2c-bus@180 { - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - - reg = <0x180 0x40>; - compatible = "aspeed,ast2400-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB>; - resets = <&syscon ASPEED_RESET_I2C>; - bus-frequency = <100000>; - interrupts = <5>; - interrupt-parent = <&i2c_ic>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c6_default>; - status = "disabled"; - }; - - i2c6: i2c-bus@1c0 { - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - - reg = <0x1c0 0x40>; - compatible = "aspeed,ast2400-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB>; - resets = <&syscon ASPEED_RESET_I2C>; - bus-frequency = <100000>; - interrupts = <6>; - interrupt-parent = <&i2c_ic>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c7_default>; - status = "disabled"; - }; - - i2c7: i2c-bus@300 { - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - - reg = <0x300 0x40>; - compatible = "aspeed,ast2400-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB>; - resets = <&syscon ASPEED_RESET_I2C>; - bus-frequency = <100000>; - interrupts = <7>; - interrupt-parent = <&i2c_ic>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c8_default>; - status = "disabled"; - }; - - i2c8: i2c-bus@340 { - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - - reg = <0x340 0x40>; - compatible = "aspeed,ast2400-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB>; - resets = <&syscon ASPEED_RESET_I2C>; - bus-frequency = <100000>; - interrupts = <8>; - interrupt-parent = <&i2c_ic>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c9_default>; - status = "disabled"; - }; - - i2c9: i2c-bus@380 { - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - - reg = <0x380 0x40>; - compatible = "aspeed,ast2400-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB>; - resets = <&syscon ASPEED_RESET_I2C>; - bus-frequency = <100000>; - interrupts = <9>; - interrupt-parent = <&i2c_ic>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c10_default>; - status = "disabled"; - }; - - i2c10: i2c-bus@3c0 { - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - - reg = <0x3c0 0x40>; - compatible = "aspeed,ast2400-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB>; - resets = <&syscon ASPEED_RESET_I2C>; - bus-frequency = <100000>; - interrupts = <10>; - interrupt-parent = <&i2c_ic>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c11_default>; - status = "disabled"; - }; - - i2c11: i2c-bus@400 { - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - - reg = <0x400 0x40>; - compatible = "aspeed,ast2400-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB>; - resets = <&syscon ASPEED_RESET_I2C>; - bus-frequency = <100000>; - interrupts = <11>; - interrupt-parent = <&i2c_ic>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c12_default>; - status = "disabled"; - }; - - i2c12: i2c-bus@440 { - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - - reg = <0x440 0x40>; - compatible = "aspeed,ast2400-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB>; - resets = <&syscon ASPEED_RESET_I2C>; - bus-frequency = <100000>; - interrupts = <12>; - interrupt-parent = <&i2c_ic>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c13_default>; - status = "disabled"; - }; - - i2c13: i2c-bus@480 { - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - - reg = <0x480 0x40>; - compatible = "aspeed,ast2400-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB>; - resets = <&syscon ASPEED_RESET_I2C>; - bus-frequency = <100000>; - interrupts = <13>; - interrupt-parent = <&i2c_ic>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c14_default>; - status = "disabled"; - }; -}; - -&pinctrl { - pinctrl_acpi_default: acpi_default { - function = "ACPI"; - groups = "ACPI"; - }; - - pinctrl_adc0_default: adc0_default { - function = "ADC0"; - groups = "ADC0"; - }; - - pinctrl_adc1_default: adc1_default { - function = "ADC1"; - groups = "ADC1"; - }; - - pinctrl_adc10_default: adc10_default { - function = "ADC10"; - groups = "ADC10"; - }; - - pinctrl_adc11_default: adc11_default { - function = "ADC11"; - groups = "ADC11"; - }; - - pinctrl_adc12_default: adc12_default { - function = "ADC12"; - groups = "ADC12"; - }; - - pinctrl_adc13_default: adc13_default { - function = "ADC13"; - groups = "ADC13"; - }; - - pinctrl_adc14_default: adc14_default { - function = "ADC14"; - groups = "ADC14"; - }; - - pinctrl_adc15_default: adc15_default { - function = "ADC15"; - groups = "ADC15"; - }; - - pinctrl_adc2_default: adc2_default { - function = "ADC2"; - groups = "ADC2"; - }; - - pinctrl_adc3_default: adc3_default { - function = "ADC3"; - groups = "ADC3"; - }; - - pinctrl_adc4_default: adc4_default { - function = "ADC4"; - groups = "ADC4"; - }; - - pinctrl_adc5_default: adc5_default { - function = "ADC5"; - groups = "ADC5"; - }; - - pinctrl_adc6_default: adc6_default { - function = "ADC6"; - groups = "ADC6"; - }; - - pinctrl_adc7_default: adc7_default { - function = "ADC7"; - groups = "ADC7"; - }; - - pinctrl_adc8_default: adc8_default { - function = "ADC8"; - groups = "ADC8"; - }; - - pinctrl_adc9_default: adc9_default { - function = "ADC9"; - groups = "ADC9"; - }; - - pinctrl_bmcint_default: bmcint_default { - function = "BMCINT"; - groups = "BMCINT"; - }; - - pinctrl_ddcclk_default: ddcclk_default { - function = "DDCCLK"; - groups = "DDCCLK"; - }; - - pinctrl_ddcdat_default: ddcdat_default { - function = "DDCDAT"; - groups = "DDCDAT"; - }; - - pinctrl_extrst_default: extrst_default { - function = "EXTRST"; - groups = "EXTRST"; - }; - - pinctrl_flack_default: flack_default { - function = "FLACK"; - groups = "FLACK"; - }; - - pinctrl_flbusy_default: flbusy_default { - function = "FLBUSY"; - groups = "FLBUSY"; - }; - - pinctrl_flwp_default: flwp_default { - function = "FLWP"; - groups = "FLWP"; - }; - - pinctrl_gpid_default: gpid_default { - function = "GPID"; - groups = "GPID"; - }; - - pinctrl_gpid0_default: gpid0_default { - function = "GPID0"; - groups = "GPID0"; - }; - - pinctrl_gpid2_default: gpid2_default { - function = "GPID2"; - groups = "GPID2"; - }; - - pinctrl_gpid4_default: gpid4_default { - function = "GPID4"; - groups = "GPID4"; - }; - - pinctrl_gpid6_default: gpid6_default { - function = "GPID6"; - groups = "GPID6"; - }; - - pinctrl_gpie0_default: gpie0_default { - function = "GPIE0"; - groups = "GPIE0"; - }; - - pinctrl_gpie2_default: gpie2_default { - function = "GPIE2"; - groups = "GPIE2"; - }; - - pinctrl_gpie4_default: gpie4_default { - function = "GPIE4"; - groups = "GPIE4"; - }; - - pinctrl_gpie6_default: gpie6_default { - function = "GPIE6"; - groups = "GPIE6"; - }; - - pinctrl_i2c10_default: i2c10_default { - function = "I2C10"; - groups = "I2C10"; - }; - - pinctrl_i2c11_default: i2c11_default { - function = "I2C11"; - groups = "I2C11"; - }; - - pinctrl_i2c12_default: i2c12_default { - function = "I2C12"; - groups = "I2C12"; - }; - - pinctrl_i2c13_default: i2c13_default { - function = "I2C13"; - groups = "I2C13"; - }; - - pinctrl_i2c14_default: i2c14_default { - function = "I2C14"; - groups = "I2C14"; - }; - - pinctrl_i2c3_default: i2c3_default { - function = "I2C3"; - groups = "I2C3"; - }; - - pinctrl_i2c4_default: i2c4_default { - function = "I2C4"; - groups = "I2C4"; - }; - - pinctrl_i2c5_default: i2c5_default { - function = "I2C5"; - groups = "I2C5"; - }; - - pinctrl_i2c6_default: i2c6_default { - function = "I2C6"; - groups = "I2C6"; - }; - - pinctrl_i2c7_default: i2c7_default { - function = "I2C7"; - groups = "I2C7"; - }; - - pinctrl_i2c8_default: i2c8_default { - function = "I2C8"; - groups = "I2C8"; - }; - - pinctrl_i2c9_default: i2c9_default { - function = "I2C9"; - groups = "I2C9"; - }; - - pinctrl_lpcpd_default: lpcpd_default { - function = "LPCPD"; - groups = "LPCPD"; - }; - - pinctrl_lpcpme_default: lpcpme_default { - function = "LPCPME"; - groups = "LPCPME"; - }; - - pinctrl_lpcrst_default: lpcrst_default { - function = "LPCRST"; - groups = "LPCRST"; - }; - - pinctrl_lpcsmi_default: lpcsmi_default { - function = "LPCSMI"; - groups = "LPCSMI"; - }; - - pinctrl_mac1link_default: mac1link_default { - function = "MAC1LINK"; - groups = "MAC1LINK"; - }; - - pinctrl_mac2link_default: mac2link_default { - function = "MAC2LINK"; - groups = "MAC2LINK"; - }; - - pinctrl_mdio1_default: mdio1_default { - function = "MDIO1"; - groups = "MDIO1"; - }; - - pinctrl_mdio2_default: mdio2_default { - function = "MDIO2"; - groups = "MDIO2"; - }; - - pinctrl_ncts1_default: ncts1_default { - function = "NCTS1"; - groups = "NCTS1"; - }; - - pinctrl_ncts2_default: ncts2_default { - function = "NCTS2"; - groups = "NCTS2"; - }; - - pinctrl_ncts3_default: ncts3_default { - function = "NCTS3"; - groups = "NCTS3"; - }; - - pinctrl_ncts4_default: ncts4_default { - function = "NCTS4"; - groups = "NCTS4"; - }; - - pinctrl_ndcd1_default: ndcd1_default { - function = "NDCD1"; - groups = "NDCD1"; - }; - - pinctrl_ndcd2_default: ndcd2_default { - function = "NDCD2"; - groups = "NDCD2"; - }; - - pinctrl_ndcd3_default: ndcd3_default { - function = "NDCD3"; - groups = "NDCD3"; - }; - - pinctrl_ndcd4_default: ndcd4_default { - function = "NDCD4"; - groups = "NDCD4"; - }; - - pinctrl_ndsr1_default: ndsr1_default { - function = "NDSR1"; - groups = "NDSR1"; - }; - - pinctrl_ndsr2_default: ndsr2_default { - function = "NDSR2"; - groups = "NDSR2"; - }; - - pinctrl_ndsr3_default: ndsr3_default { - function = "NDSR3"; - groups = "NDSR3"; - }; - - pinctrl_ndsr4_default: ndsr4_default { - function = "NDSR4"; - groups = "NDSR4"; - }; - - pinctrl_ndtr1_default: ndtr1_default { - function = "NDTR1"; - groups = "NDTR1"; - }; - - pinctrl_ndtr2_default: ndtr2_default { - function = "NDTR2"; - groups = "NDTR2"; - }; - - pinctrl_ndtr3_default: ndtr3_default { - function = "NDTR3"; - groups = "NDTR3"; - }; - - pinctrl_ndtr4_default: ndtr4_default { - function = "NDTR4"; - groups = "NDTR4"; - }; - - pinctrl_ndts4_default: ndts4_default { - function = "NDTS4"; - groups = "NDTS4"; - }; - - pinctrl_nri1_default: nri1_default { - function = "NRI1"; - groups = "NRI1"; - }; - - pinctrl_nri2_default: nri2_default { - function = "NRI2"; - groups = "NRI2"; - }; - - pinctrl_nri3_default: nri3_default { - function = "NRI3"; - groups = "NRI3"; - }; - - pinctrl_nri4_default: nri4_default { - function = "NRI4"; - groups = "NRI4"; - }; - - pinctrl_nrts1_default: nrts1_default { - function = "NRTS1"; - groups = "NRTS1"; - }; - - pinctrl_nrts2_default: nrts2_default { - function = "NRTS2"; - groups = "NRTS2"; - }; - - pinctrl_nrts3_default: nrts3_default { - function = "NRTS3"; - groups = "NRTS3"; - }; - - pinctrl_oscclk_default: oscclk_default { - function = "OSCCLK"; - groups = "OSCCLK"; - }; - - pinctrl_pwm0_default: pwm0_default { - function = "PWM0"; - groups = "PWM0"; - }; - - pinctrl_pwm1_default: pwm1_default { - function = "PWM1"; - groups = "PWM1"; - }; - - pinctrl_pwm2_default: pwm2_default { - function = "PWM2"; - groups = "PWM2"; - }; - - pinctrl_pwm3_default: pwm3_default { - function = "PWM3"; - groups = "PWM3"; - }; - - pinctrl_pwm4_default: pwm4_default { - function = "PWM4"; - groups = "PWM4"; - }; - - pinctrl_pwm5_default: pwm5_default { - function = "PWM5"; - groups = "PWM5"; - }; - - pinctrl_pwm6_default: pwm6_default { - function = "PWM6"; - groups = "PWM6"; - }; - - pinctrl_pwm7_default: pwm7_default { - function = "PWM7"; - groups = "PWM7"; - }; - - pinctrl_rgmii1_default: rgmii1_default { - function = "RGMII1"; - groups = "RGMII1"; - }; - - pinctrl_rgmii2_default: rgmii2_default { - function = "RGMII2"; - groups = "RGMII2"; - }; - - pinctrl_rmii1_default: rmii1_default { - function = "RMII1"; - groups = "RMII1"; - }; - - pinctrl_rmii2_default: rmii2_default { - function = "RMII2"; - groups = "RMII2"; - }; - - pinctrl_rom16_default: rom16_default { - function = "ROM16"; - groups = "ROM16"; - }; - - pinctrl_rom8_default: rom8_default { - function = "ROM8"; - groups = "ROM8"; - }; - - pinctrl_romcs1_default: romcs1_default { - function = "ROMCS1"; - groups = "ROMCS1"; - }; - - pinctrl_romcs2_default: romcs2_default { - function = "ROMCS2"; - groups = "ROMCS2"; - }; - - pinctrl_romcs3_default: romcs3_default { - function = "ROMCS3"; - groups = "ROMCS3"; - }; - - pinctrl_romcs4_default: romcs4_default { - function = "ROMCS4"; - groups = "ROMCS4"; - }; - - pinctrl_rxd1_default: rxd1_default { - function = "RXD1"; - groups = "RXD1"; - }; - - pinctrl_rxd2_default: rxd2_default { - function = "RXD2"; - groups = "RXD2"; - }; - - pinctrl_rxd3_default: rxd3_default { - function = "RXD3"; - groups = "RXD3"; - }; - - pinctrl_rxd4_default: rxd4_default { - function = "RXD4"; - groups = "RXD4"; - }; - - pinctrl_salt1_default: salt1_default { - function = "SALT1"; - groups = "SALT1"; - }; - - pinctrl_salt2_default: salt2_default { - function = "SALT2"; - groups = "SALT2"; - }; - - pinctrl_salt3_default: salt3_default { - function = "SALT3"; - groups = "SALT3"; - }; - - pinctrl_salt4_default: salt4_default { - function = "SALT4"; - groups = "SALT4"; - }; - - pinctrl_sd1_default: sd1_default { - function = "SD1"; - groups = "SD1"; - }; - - pinctrl_sd2_default: sd2_default { - function = "SD2"; - groups = "SD2"; - }; - - pinctrl_sgpmck_default: sgpmck_default { - function = "SGPMCK"; - groups = "SGPMCK"; - }; - - pinctrl_sgpmi_default: sgpmi_default { - function = "SGPMI"; - groups = "SGPMI"; - }; - - pinctrl_sgpmld_default: sgpmld_default { - function = "SGPMLD"; - groups = "SGPMLD"; - }; - - pinctrl_sgpmo_default: sgpmo_default { - function = "SGPMO"; - groups = "SGPMO"; - }; - - pinctrl_sgpsck_default: sgpsck_default { - function = "SGPSCK"; - groups = "SGPSCK"; - }; - - pinctrl_sgpsi0_default: sgpsi0_default { - function = "SGPSI0"; - groups = "SGPSI0"; - }; - - pinctrl_sgpsi1_default: sgpsi1_default { - function = "SGPSI1"; - groups = "SGPSI1"; - }; - - pinctrl_sgpsld_default: sgpsld_default { - function = "SGPSLD"; - groups = "SGPSLD"; - }; - - pinctrl_sioonctrl_default: sioonctrl_default { - function = "SIOONCTRL"; - groups = "SIOONCTRL"; - }; - - pinctrl_siopbi_default: siopbi_default { - function = "SIOPBI"; - groups = "SIOPBI"; - }; - - pinctrl_siopbo_default: siopbo_default { - function = "SIOPBO"; - groups = "SIOPBO"; - }; - - pinctrl_siopwreq_default: siopwreq_default { - function = "SIOPWREQ"; - groups = "SIOPWREQ"; - }; - - pinctrl_siopwrgd_default: siopwrgd_default { - function = "SIOPWRGD"; - groups = "SIOPWRGD"; - }; - - pinctrl_sios3_default: sios3_default { - function = "SIOS3"; - groups = "SIOS3"; - }; - - pinctrl_sios5_default: sios5_default { - function = "SIOS5"; - groups = "SIOS5"; - }; - - pinctrl_siosci_default: siosci_default { - function = "SIOSCI"; - groups = "SIOSCI"; - }; - - pinctrl_spi1_default: spi1_default { - function = "SPI1"; - groups = "SPI1"; - }; - - pinctrl_spi1debug_default: spi1debug_default { - function = "SPI1DEBUG"; - groups = "SPI1DEBUG"; - }; - - pinctrl_spi1passthru_default: spi1passthru_default { - function = "SPI1PASSTHRU"; - groups = "SPI1PASSTHRU"; - }; - - pinctrl_spics1_default: spics1_default { - function = "SPICS1"; - groups = "SPICS1"; - }; - - pinctrl_timer3_default: timer3_default { - function = "TIMER3"; - groups = "TIMER3"; - }; - - pinctrl_timer4_default: timer4_default { - function = "TIMER4"; - groups = "TIMER4"; - }; - - pinctrl_timer5_default: timer5_default { - function = "TIMER5"; - groups = "TIMER5"; - }; - - pinctrl_timer6_default: timer6_default { - function = "TIMER6"; - groups = "TIMER6"; - }; - - pinctrl_timer7_default: timer7_default { - function = "TIMER7"; - groups = "TIMER7"; - }; - - pinctrl_timer8_default: timer8_default { - function = "TIMER8"; - groups = "TIMER8"; - }; - - pinctrl_txd1_default: txd1_default { - function = "TXD1"; - groups = "TXD1"; - }; - - pinctrl_txd2_default: txd2_default { - function = "TXD2"; - groups = "TXD2"; - }; - - pinctrl_txd3_default: txd3_default { - function = "TXD3"; - groups = "TXD3"; - }; - - pinctrl_txd4_default: txd4_default { - function = "TXD4"; - groups = "TXD4"; - }; - - pinctrl_uart6_default: uart6_default { - function = "UART6"; - groups = "UART6"; - }; - - pinctrl_usbcki_default: usbcki_default { - function = "USBCKI"; - groups = "USBCKI"; - }; - - pinctrl_usb2h_default: usb2h_default { - function = "USB2H1"; - groups = "USB2H1"; - }; - - pinctrl_usb2d_default: usb2d_default { - function = "USB2D1"; - groups = "USB2D1"; - }; - - pinctrl_vgabios_rom_default: vgabios_rom_default { - function = "VGABIOS_ROM"; - groups = "VGABIOS_ROM"; - }; - - pinctrl_vgahs_default: vgahs_default { - function = "VGAHS"; - groups = "VGAHS"; - }; - - pinctrl_vgavs_default: vgavs_default { - function = "VGAVS"; - groups = "VGAVS"; - }; - - pinctrl_vpi18_default: vpi18_default { - function = "VPI18"; - groups = "VPI18"; - }; - - pinctrl_vpi24_default: vpi24_default { - function = "VPI24"; - groups = "VPI24"; - }; - - pinctrl_vpi30_default: vpi30_default { - function = "VPI30"; - groups = "VPI30"; - }; - - pinctrl_vpo12_default: vpo12_default { - function = "VPO12"; - groups = "VPO12"; - }; - - pinctrl_vpo24_default: vpo24_default { - function = "VPO24"; - groups = "VPO24"; - }; - - pinctrl_wdtrst1_default: wdtrst1_default { - function = "WDTRST1"; - groups = "WDTRST1"; - }; - - pinctrl_wdtrst2_default: wdtrst2_default { - function = "WDTRST2"; - groups = "WDTRST2"; - }; -}; diff --git a/sys/gnu/dts/arm/aspeed-g5.dtsi b/sys/gnu/dts/arm/aspeed-g5.dtsi deleted file mode 100644 index ebec0fa8baa..00000000000 --- a/sys/gnu/dts/arm/aspeed-g5.dtsi +++ /dev/null @@ -1,1617 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -#include - -/ { - model = "Aspeed BMC"; - compatible = "aspeed,ast2500"; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&vic>; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - i2c6 = &i2c6; - i2c7 = &i2c7; - i2c8 = &i2c8; - i2c9 = &i2c9; - i2c10 = &i2c10; - i2c11 = &i2c11; - i2c12 = &i2c12; - i2c13 = &i2c13; - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - serial3 = &uart4; - serial4 = &uart5; - serial5 = &vuart; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "arm,arm1176jzf-s"; - device_type = "cpu"; - reg = <0>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0>; - }; - - ahb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - fmc: spi@1e620000 { - reg = < 0x1e620000 0xc4 - 0x20000000 0x10000000 >; - #address-cells = <1>; - #size-cells = <0>; - compatible = "aspeed,ast2500-fmc"; - clocks = <&syscon ASPEED_CLK_AHB>; - status = "disabled"; - interrupts = <19>; - flash@0 { - reg = < 0 >; - compatible = "jedec,spi-nor"; - spi-max-frequency = <50000000>; - status = "disabled"; - }; - flash@1 { - reg = < 1 >; - compatible = "jedec,spi-nor"; - spi-max-frequency = <50000000>; - status = "disabled"; - }; - flash@2 { - reg = < 2 >; - compatible = "jedec,spi-nor"; - spi-max-frequency = <50000000>; - status = "disabled"; - }; - }; - - spi1: spi@1e630000 { - reg = < 0x1e630000 0xc4 - 0x30000000 0x08000000 >; - #address-cells = <1>; - #size-cells = <0>; - compatible = "aspeed,ast2500-spi"; - clocks = <&syscon ASPEED_CLK_AHB>; - status = "disabled"; - flash@0 { - reg = < 0 >; - compatible = "jedec,spi-nor"; - spi-max-frequency = <50000000>; - status = "disabled"; - }; - flash@1 { - reg = < 1 >; - compatible = "jedec,spi-nor"; - spi-max-frequency = <50000000>; - status = "disabled"; - }; - }; - - spi2: spi@1e631000 { - reg = < 0x1e631000 0xc4 - 0x38000000 0x08000000 >; - #address-cells = <1>; - #size-cells = <0>; - compatible = "aspeed,ast2500-spi"; - clocks = <&syscon ASPEED_CLK_AHB>; - status = "disabled"; - flash@0 { - reg = < 0 >; - compatible = "jedec,spi-nor"; - spi-max-frequency = <50000000>; - status = "disabled"; - }; - flash@1 { - reg = < 1 >; - compatible = "jedec,spi-nor"; - spi-max-frequency = <50000000>; - status = "disabled"; - }; - }; - - vic: interrupt-controller@1e6c0080 { - compatible = "aspeed,ast2400-vic"; - interrupt-controller; - #interrupt-cells = <1>; - valid-sources = <0xfefff7ff 0x0807ffff>; - reg = <0x1e6c0080 0x80>; - }; - - cvic: copro-interrupt-controller@1e6c2000 { - compatible = "aspeed,ast2500-cvic", "aspeed-cvic"; - valid-sources = <0xffffffff>; - copro-sw-interrupts = <1>; - reg = <0x1e6c2000 0x80>; - }; - - mac0: ethernet@1e660000 { - compatible = "aspeed,ast2500-mac", "faraday,ftgmac100"; - reg = <0x1e660000 0x180>; - interrupts = <2>; - clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>; - status = "disabled"; - }; - - mac1: ethernet@1e680000 { - compatible = "aspeed,ast2500-mac", "faraday,ftgmac100"; - reg = <0x1e680000 0x180>; - interrupts = <3>; - clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>; - status = "disabled"; - }; - - ehci0: usb@1e6a1000 { - compatible = "aspeed,ast2500-ehci", "generic-ehci"; - reg = <0x1e6a1000 0x100>; - interrupts = <5>; - clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb2ah_default>; - status = "disabled"; - }; - - ehci1: usb@1e6a3000 { - compatible = "aspeed,ast2500-ehci", "generic-ehci"; - reg = <0x1e6a3000 0x100>; - interrupts = <13>; - clocks = <&syscon ASPEED_CLK_GATE_USBPORT2CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb2bh_default>; - status = "disabled"; - }; - - uhci: usb@1e6b0000 { - compatible = "aspeed,ast2500-uhci", "generic-uhci"; - reg = <0x1e6b0000 0x100>; - interrupts = <14>; - #ports = <2>; - clocks = <&syscon ASPEED_CLK_GATE_USBUHCICLK>; - status = "disabled"; - /* - * No default pinmux, it will follow EHCI, use an explicit pinmux - * override if you don't enable EHCI - */ - }; - - vhub: usb-vhub@1e6a0000 { - compatible = "aspeed,ast2500-usb-vhub"; - reg = <0x1e6a0000 0x300>; - interrupts = <5>; - clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb2ad_default>; - status = "disabled"; - }; - - apb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - edac: memory-controller@1e6e0000 { - compatible = "aspeed,ast2500-sdram-edac"; - reg = <0x1e6e0000 0x174>; - interrupts = <0>; - status = "disabled"; - }; - - syscon: syscon@1e6e2000 { - compatible = "aspeed,ast2500-scu", "syscon", "simple-mfd"; - reg = <0x1e6e2000 0x1a8>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1e6e2000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - - p2a: p2a-control@2c { - compatible = "aspeed,ast2500-p2a-ctrl"; - reg = <0x2c 0x4>; - status = "disabled"; - }; - - pinctrl: pinctrl@80 { - compatible = "aspeed,ast2500-pinctrl"; - reg = <0x80 0x18>, <0xa0 0x10>; - aspeed,external-nodes = <&gfx>, <&lhc>; - }; - }; - - rng: hwrng@1e6e2078 { - compatible = "timeriomem_rng"; - reg = <0x1e6e2078 0x4>; - period = <1>; - quality = <100>; - }; - - gfx: display@1e6e6000 { - compatible = "aspeed,ast2500-gfx", "syscon"; - reg = <0x1e6e6000 0x1000>; - reg-io-width = <4>; - clocks = <&syscon ASPEED_CLK_GATE_D1CLK>; - resets = <&syscon ASPEED_RESET_CRT1>; - status = "disabled"; - interrupts = <0x19>; - }; - - adc: adc@1e6e9000 { - compatible = "aspeed,ast2500-adc"; - reg = <0x1e6e9000 0xb0>; - clocks = <&syscon ASPEED_CLK_APB>; - resets = <&syscon ASPEED_RESET_ADC>; - #io-channel-cells = <1>; - status = "disabled"; - }; - - video: video@1e700000 { - compatible = "aspeed,ast2500-video-engine"; - reg = <0x1e700000 0x1000>; - clocks = <&syscon ASPEED_CLK_GATE_VCLK>, - <&syscon ASPEED_CLK_GATE_ECLK>; - clock-names = "vclk", "eclk"; - interrupts = <7>; - status = "disabled"; - }; - - sram: sram@1e720000 { - compatible = "mmio-sram"; - reg = <0x1e720000 0x9000>; // 36K - }; - - sdmmc: sd-controller@1e740000 { - compatible = "aspeed,ast2500-sd-controller"; - reg = <0x1e740000 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1e740000 0x10000>; - clocks = <&syscon ASPEED_CLK_GATE_SDCLK>; - status = "disabled"; - - sdhci0: sdhci@100 { - compatible = "aspeed,ast2500-sdhci"; - reg = <0x100 0x100>; - interrupts = <26>; - sdhci,auto-cmd12; - clocks = <&syscon ASPEED_CLK_SDIO>; - status = "disabled"; - }; - - sdhci1: sdhci@200 { - compatible = "aspeed,ast2500-sdhci"; - reg = <0x200 0x100>; - interrupts = <26>; - sdhci,auto-cmd12; - clocks = <&syscon ASPEED_CLK_SDIO>; - status = "disabled"; - }; - }; - - gpio: gpio@1e780000 { - #gpio-cells = <2>; - gpio-controller; - compatible = "aspeed,ast2500-gpio"; - reg = <0x1e780000 0x200>; - interrupts = <20>; - gpio-ranges = <&pinctrl 0 0 232>; - clocks = <&syscon ASPEED_CLK_APB>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - sgpio: sgpio@1e780200 { - #gpio-cells = <2>; - compatible = "aspeed,ast2500-sgpio"; - gpio-controller; - interrupts = <40>; - reg = <0x1e780200 0x0100>; - clocks = <&syscon ASPEED_CLK_APB>; - interrupt-controller; - ngpios = <8>; - bus-frequency = <12000000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sgpm_default>; - status = "disabled"; - }; - - rtc: rtc@1e781000 { - compatible = "aspeed,ast2500-rtc"; - reg = <0x1e781000 0x18>; - status = "disabled"; - }; - - timer: timer@1e782000 { - /* This timer is a Faraday FTTMR010 derivative */ - compatible = "aspeed,ast2400-timer"; - reg = <0x1e782000 0x90>; - interrupts = <16 17 18 35 36 37 38 39>; - clocks = <&syscon ASPEED_CLK_APB>; - clock-names = "PCLK"; - }; - - uart1: serial@1e783000 { - compatible = "ns16550a"; - reg = <0x1e783000 0x20>; - reg-shift = <2>; - interrupts = <9>; - clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>; - resets = <&lpc_reset 4>; - no-loopback-test; - status = "disabled"; - }; - - uart5: serial@1e784000 { - compatible = "ns16550a"; - reg = <0x1e784000 0x20>; - reg-shift = <2>; - interrupts = <10>; - clocks = <&syscon ASPEED_CLK_GATE_UART5CLK>; - no-loopback-test; - status = "disabled"; - }; - - wdt1: watchdog@1e785000 { - compatible = "aspeed,ast2500-wdt"; - reg = <0x1e785000 0x20>; - clocks = <&syscon ASPEED_CLK_APB>; - }; - - wdt2: watchdog@1e785020 { - compatible = "aspeed,ast2500-wdt"; - reg = <0x1e785020 0x20>; - clocks = <&syscon ASPEED_CLK_APB>; - }; - - wdt3: watchdog@1e785040 { - compatible = "aspeed,ast2500-wdt"; - reg = <0x1e785040 0x20>; - clocks = <&syscon ASPEED_CLK_APB>; - status = "disabled"; - }; - - pwm_tacho: pwm-tacho-controller@1e786000 { - compatible = "aspeed,ast2500-pwm-tacho"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x1e786000 0x1000>; - clocks = <&syscon ASPEED_CLK_24M>; - resets = <&syscon ASPEED_RESET_PWM>; - status = "disabled"; - }; - - vuart: serial@1e787000 { - compatible = "aspeed,ast2500-vuart"; - reg = <0x1e787000 0x40>; - reg-shift = <2>; - interrupts = <8>; - clocks = <&syscon ASPEED_CLK_APB>; - no-loopback-test; - aspeed,sirq-polarity-sense = <&syscon 0x70 25>; - status = "disabled"; - }; - - lpc: lpc@1e789000 { - compatible = "aspeed,ast2500-lpc", "simple-mfd"; - reg = <0x1e789000 0x1000>; - - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x1e789000 0x1000>; - - lpc_bmc: lpc-bmc@0 { - compatible = "aspeed,ast2500-lpc-bmc", "simple-mfd", "syscon"; - reg = <0x0 0x80>; - reg-io-width = <4>; - - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x80>; - - kcs1: kcs1@0 { - compatible = "aspeed,ast2500-kcs-bmc"; - interrupts = <8>; - kcs_chan = <1>; - status = "disabled"; - }; - kcs2: kcs2@0 { - compatible = "aspeed,ast2500-kcs-bmc"; - interrupts = <8>; - kcs_chan = <2>; - status = "disabled"; - }; - kcs3: kcs3@0 { - compatible = "aspeed,ast2500-kcs-bmc"; - interrupts = <8>; - kcs_chan = <3>; - status = "disabled"; - }; - }; - - lpc_host: lpc-host@80 { - compatible = "aspeed,ast2500-lpc-host", "simple-mfd", "syscon"; - reg = <0x80 0x1e0>; - reg-io-width = <4>; - - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x80 0x1e0>; - - kcs4: kcs4@0 { - compatible = "aspeed,ast2500-kcs-bmc"; - interrupts = <8>; - kcs_chan = <4>; - status = "disabled"; - }; - - lpc_ctrl: lpc-ctrl@0 { - compatible = "aspeed,ast2500-lpc-ctrl"; - reg = <0x0 0x10>; - clocks = <&syscon ASPEED_CLK_GATE_LCLK>; - status = "disabled"; - }; - - lpc_snoop: lpc-snoop@10 { - compatible = "aspeed,ast2500-lpc-snoop"; - reg = <0x10 0x8>; - interrupts = <8>; - status = "disabled"; - }; - - lpc_reset: reset-controller@18 { - compatible = "aspeed,ast2500-lpc-reset"; - reg = <0x18 0x4>; - #reset-cells = <1>; - }; - - lhc: lhc@20 { - compatible = "aspeed,ast2500-lhc"; - reg = <0x20 0x24 0x48 0x8>; - }; - - - ibt: ibt@c0 { - compatible = "aspeed,ast2500-ibt-bmc"; - reg = <0xc0 0x18>; - interrupts = <8>; - status = "disabled"; - }; - }; - }; - - uart2: serial@1e78d000 { - compatible = "ns16550a"; - reg = <0x1e78d000 0x20>; - reg-shift = <2>; - interrupts = <32>; - clocks = <&syscon ASPEED_CLK_GATE_UART2CLK>; - resets = <&lpc_reset 5>; - no-loopback-test; - status = "disabled"; - }; - - uart3: serial@1e78e000 { - compatible = "ns16550a"; - reg = <0x1e78e000 0x20>; - reg-shift = <2>; - interrupts = <33>; - clocks = <&syscon ASPEED_CLK_GATE_UART3CLK>; - resets = <&lpc_reset 6>; - no-loopback-test; - status = "disabled"; - }; - - uart4: serial@1e78f000 { - compatible = "ns16550a"; - reg = <0x1e78f000 0x20>; - reg-shift = <2>; - interrupts = <34>; - clocks = <&syscon ASPEED_CLK_GATE_UART4CLK>; - resets = <&lpc_reset 7>; - no-loopback-test; - status = "disabled"; - }; - - i2c: bus@1e78a000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1e78a000 0x1000>; - }; - }; - }; -}; - -&i2c { - i2c_ic: interrupt-controller@0 { - #interrupt-cells = <1>; - compatible = "aspeed,ast2500-i2c-ic"; - reg = <0x0 0x40>; - interrupts = <12>; - interrupt-controller; - }; - - i2c0: i2c-bus@40 { - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - - reg = <0x40 0x40>; - compatible = "aspeed,ast2500-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB>; - resets = <&syscon ASPEED_RESET_I2C>; - bus-frequency = <100000>; - interrupts = <0>; - interrupt-parent = <&i2c_ic>; - status = "disabled"; - /* Does not need pinctrl properties */ - }; - - i2c1: i2c-bus@80 { - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - - reg = <0x80 0x40>; - compatible = "aspeed,ast2500-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB>; - resets = <&syscon ASPEED_RESET_I2C>; - bus-frequency = <100000>; - interrupts = <1>; - interrupt-parent = <&i2c_ic>; - status = "disabled"; - /* Does not need pinctrl properties */ - }; - - i2c2: i2c-bus@c0 { - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - - reg = <0xc0 0x40>; - compatible = "aspeed,ast2500-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB>; - resets = <&syscon ASPEED_RESET_I2C>; - bus-frequency = <100000>; - interrupts = <2>; - interrupt-parent = <&i2c_ic>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3_default>; - status = "disabled"; - }; - - i2c3: i2c-bus@100 { - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - - reg = <0x100 0x40>; - compatible = "aspeed,ast2500-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB>; - resets = <&syscon ASPEED_RESET_I2C>; - bus-frequency = <100000>; - interrupts = <3>; - interrupt-parent = <&i2c_ic>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4_default>; - status = "disabled"; - }; - - i2c4: i2c-bus@140 { - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - - reg = <0x140 0x40>; - compatible = "aspeed,ast2500-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB>; - resets = <&syscon ASPEED_RESET_I2C>; - bus-frequency = <100000>; - interrupts = <4>; - interrupt-parent = <&i2c_ic>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c5_default>; - status = "disabled"; - }; - - i2c5: i2c-bus@180 { - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - - reg = <0x180 0x40>; - compatible = "aspeed,ast2500-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB>; - resets = <&syscon ASPEED_RESET_I2C>; - bus-frequency = <100000>; - interrupts = <5>; - interrupt-parent = <&i2c_ic>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c6_default>; - status = "disabled"; - }; - - i2c6: i2c-bus@1c0 { - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - - reg = <0x1c0 0x40>; - compatible = "aspeed,ast2500-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB>; - resets = <&syscon ASPEED_RESET_I2C>; - bus-frequency = <100000>; - interrupts = <6>; - interrupt-parent = <&i2c_ic>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c7_default>; - status = "disabled"; - }; - - i2c7: i2c-bus@300 { - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - - reg = <0x300 0x40>; - compatible = "aspeed,ast2500-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB>; - resets = <&syscon ASPEED_RESET_I2C>; - bus-frequency = <100000>; - interrupts = <7>; - interrupt-parent = <&i2c_ic>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c8_default>; - status = "disabled"; - }; - - i2c8: i2c-bus@340 { - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - - reg = <0x340 0x40>; - compatible = "aspeed,ast2500-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB>; - resets = <&syscon ASPEED_RESET_I2C>; - bus-frequency = <100000>; - interrupts = <8>; - interrupt-parent = <&i2c_ic>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c9_default>; - status = "disabled"; - }; - - i2c9: i2c-bus@380 { - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - - reg = <0x380 0x40>; - compatible = "aspeed,ast2500-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB>; - resets = <&syscon ASPEED_RESET_I2C>; - bus-frequency = <100000>; - interrupts = <9>; - interrupt-parent = <&i2c_ic>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c10_default>; - status = "disabled"; - }; - - i2c10: i2c-bus@3c0 { - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - - reg = <0x3c0 0x40>; - compatible = "aspeed,ast2500-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB>; - resets = <&syscon ASPEED_RESET_I2C>; - bus-frequency = <100000>; - interrupts = <10>; - interrupt-parent = <&i2c_ic>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c11_default>; - status = "disabled"; - }; - - i2c11: i2c-bus@400 { - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - - reg = <0x400 0x40>; - compatible = "aspeed,ast2500-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB>; - resets = <&syscon ASPEED_RESET_I2C>; - bus-frequency = <100000>; - interrupts = <11>; - interrupt-parent = <&i2c_ic>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c12_default>; - status = "disabled"; - }; - - i2c12: i2c-bus@440 { - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - - reg = <0x440 0x40>; - compatible = "aspeed,ast2500-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB>; - resets = <&syscon ASPEED_RESET_I2C>; - bus-frequency = <100000>; - interrupts = <12>; - interrupt-parent = <&i2c_ic>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c13_default>; - status = "disabled"; - }; - - i2c13: i2c-bus@480 { - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - - reg = <0x480 0x40>; - compatible = "aspeed,ast2500-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB>; - resets = <&syscon ASPEED_RESET_I2C>; - bus-frequency = <100000>; - interrupts = <13>; - interrupt-parent = <&i2c_ic>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c14_default>; - status = "disabled"; - }; -}; - -&pinctrl { - pinctrl_acpi_default: acpi_default { - function = "ACPI"; - groups = "ACPI"; - }; - - pinctrl_adc0_default: adc0_default { - function = "ADC0"; - groups = "ADC0"; - }; - - pinctrl_adc1_default: adc1_default { - function = "ADC1"; - groups = "ADC1"; - }; - - pinctrl_adc10_default: adc10_default { - function = "ADC10"; - groups = "ADC10"; - }; - - pinctrl_adc11_default: adc11_default { - function = "ADC11"; - groups = "ADC11"; - }; - - pinctrl_adc12_default: adc12_default { - function = "ADC12"; - groups = "ADC12"; - }; - - pinctrl_adc13_default: adc13_default { - function = "ADC13"; - groups = "ADC13"; - }; - - pinctrl_adc14_default: adc14_default { - function = "ADC14"; - groups = "ADC14"; - }; - - pinctrl_adc15_default: adc15_default { - function = "ADC15"; - groups = "ADC15"; - }; - - pinctrl_adc2_default: adc2_default { - function = "ADC2"; - groups = "ADC2"; - }; - - pinctrl_adc3_default: adc3_default { - function = "ADC3"; - groups = "ADC3"; - }; - - pinctrl_adc4_default: adc4_default { - function = "ADC4"; - groups = "ADC4"; - }; - - pinctrl_adc5_default: adc5_default { - function = "ADC5"; - groups = "ADC5"; - }; - - pinctrl_adc6_default: adc6_default { - function = "ADC6"; - groups = "ADC6"; - }; - - pinctrl_adc7_default: adc7_default { - function = "ADC7"; - groups = "ADC7"; - }; - - pinctrl_adc8_default: adc8_default { - function = "ADC8"; - groups = "ADC8"; - }; - - pinctrl_adc9_default: adc9_default { - function = "ADC9"; - groups = "ADC9"; - }; - - pinctrl_bmcint_default: bmcint_default { - function = "BMCINT"; - groups = "BMCINT"; - }; - - pinctrl_ddcclk_default: ddcclk_default { - function = "DDCCLK"; - groups = "DDCCLK"; - }; - - pinctrl_ddcdat_default: ddcdat_default { - function = "DDCDAT"; - groups = "DDCDAT"; - }; - - pinctrl_espi_default: espi_default { - function = "ESPI"; - groups = "ESPI"; - }; - - pinctrl_fwspics1_default: fwspics1_default { - function = "FWSPICS1"; - groups = "FWSPICS1"; - }; - - pinctrl_fwspics2_default: fwspics2_default { - function = "FWSPICS2"; - groups = "FWSPICS2"; - }; - - pinctrl_gpid0_default: gpid0_default { - function = "GPID0"; - groups = "GPID0"; - }; - - pinctrl_gpid2_default: gpid2_default { - function = "GPID2"; - groups = "GPID2"; - }; - - pinctrl_gpid4_default: gpid4_default { - function = "GPID4"; - groups = "GPID4"; - }; - - pinctrl_gpid6_default: gpid6_default { - function = "GPID6"; - groups = "GPID6"; - }; - - pinctrl_gpie0_default: gpie0_default { - function = "GPIE0"; - groups = "GPIE0"; - }; - - pinctrl_gpie2_default: gpie2_default { - function = "GPIE2"; - groups = "GPIE2"; - }; - - pinctrl_gpie4_default: gpie4_default { - function = "GPIE4"; - groups = "GPIE4"; - }; - - pinctrl_gpie6_default: gpie6_default { - function = "GPIE6"; - groups = "GPIE6"; - }; - - pinctrl_i2c10_default: i2c10_default { - function = "I2C10"; - groups = "I2C10"; - }; - - pinctrl_i2c11_default: i2c11_default { - function = "I2C11"; - groups = "I2C11"; - }; - - pinctrl_i2c12_default: i2c12_default { - function = "I2C12"; - groups = "I2C12"; - }; - - pinctrl_i2c13_default: i2c13_default { - function = "I2C13"; - groups = "I2C13"; - }; - - pinctrl_i2c14_default: i2c14_default { - function = "I2C14"; - groups = "I2C14"; - }; - - pinctrl_i2c3_default: i2c3_default { - function = "I2C3"; - groups = "I2C3"; - }; - - pinctrl_i2c4_default: i2c4_default { - function = "I2C4"; - groups = "I2C4"; - }; - - pinctrl_i2c5_default: i2c5_default { - function = "I2C5"; - groups = "I2C5"; - }; - - pinctrl_i2c6_default: i2c6_default { - function = "I2C6"; - groups = "I2C6"; - }; - - pinctrl_i2c7_default: i2c7_default { - function = "I2C7"; - groups = "I2C7"; - }; - - pinctrl_i2c8_default: i2c8_default { - function = "I2C8"; - groups = "I2C8"; - }; - - pinctrl_i2c9_default: i2c9_default { - function = "I2C9"; - groups = "I2C9"; - }; - - pinctrl_lad0_default: lad0_default { - function = "LAD0"; - groups = "LAD0"; - }; - - pinctrl_lad1_default: lad1_default { - function = "LAD1"; - groups = "LAD1"; - }; - - pinctrl_lad2_default: lad2_default { - function = "LAD2"; - groups = "LAD2"; - }; - - pinctrl_lad3_default: lad3_default { - function = "LAD3"; - groups = "LAD3"; - }; - - pinctrl_lclk_default: lclk_default { - function = "LCLK"; - groups = "LCLK"; - }; - - pinctrl_lframe_default: lframe_default { - function = "LFRAME"; - groups = "LFRAME"; - }; - - pinctrl_lpchc_default: lpchc_default { - function = "LPCHC"; - groups = "LPCHC"; - }; - - pinctrl_lpcpd_default: lpcpd_default { - function = "LPCPD"; - groups = "LPCPD"; - }; - - pinctrl_lpcplus_default: lpcplus_default { - function = "LPCPLUS"; - groups = "LPCPLUS"; - }; - - pinctrl_lpcpme_default: lpcpme_default { - function = "LPCPME"; - groups = "LPCPME"; - }; - - pinctrl_lpcrst_default: lpcrst_default { - function = "LPCRST"; - groups = "LPCRST"; - }; - - pinctrl_lpcsmi_default: lpcsmi_default { - function = "LPCSMI"; - groups = "LPCSMI"; - }; - - pinctrl_lsirq_default: lsirq_default { - function = "LSIRQ"; - groups = "LSIRQ"; - }; - - pinctrl_mac1link_default: mac1link_default { - function = "MAC1LINK"; - groups = "MAC1LINK"; - }; - - pinctrl_mac2link_default: mac2link_default { - function = "MAC2LINK"; - groups = "MAC2LINK"; - }; - - pinctrl_mdio1_default: mdio1_default { - function = "MDIO1"; - groups = "MDIO1"; - }; - - pinctrl_mdio2_default: mdio2_default { - function = "MDIO2"; - groups = "MDIO2"; - }; - - pinctrl_ncts1_default: ncts1_default { - function = "NCTS1"; - groups = "NCTS1"; - }; - - pinctrl_ncts2_default: ncts2_default { - function = "NCTS2"; - groups = "NCTS2"; - }; - - pinctrl_ncts3_default: ncts3_default { - function = "NCTS3"; - groups = "NCTS3"; - }; - - pinctrl_ncts4_default: ncts4_default { - function = "NCTS4"; - groups = "NCTS4"; - }; - - pinctrl_ndcd1_default: ndcd1_default { - function = "NDCD1"; - groups = "NDCD1"; - }; - - pinctrl_ndcd2_default: ndcd2_default { - function = "NDCD2"; - groups = "NDCD2"; - }; - - pinctrl_ndcd3_default: ndcd3_default { - function = "NDCD3"; - groups = "NDCD3"; - }; - - pinctrl_ndcd4_default: ndcd4_default { - function = "NDCD4"; - groups = "NDCD4"; - }; - - pinctrl_ndsr1_default: ndsr1_default { - function = "NDSR1"; - groups = "NDSR1"; - }; - - pinctrl_ndsr2_default: ndsr2_default { - function = "NDSR2"; - groups = "NDSR2"; - }; - - pinctrl_ndsr3_default: ndsr3_default { - function = "NDSR3"; - groups = "NDSR3"; - }; - - pinctrl_ndsr4_default: ndsr4_default { - function = "NDSR4"; - groups = "NDSR4"; - }; - - pinctrl_ndtr1_default: ndtr1_default { - function = "NDTR1"; - groups = "NDTR1"; - }; - - pinctrl_ndtr2_default: ndtr2_default { - function = "NDTR2"; - groups = "NDTR2"; - }; - - pinctrl_ndtr3_default: ndtr3_default { - function = "NDTR3"; - groups = "NDTR3"; - }; - - pinctrl_ndtr4_default: ndtr4_default { - function = "NDTR4"; - groups = "NDTR4"; - }; - - pinctrl_nri1_default: nri1_default { - function = "NRI1"; - groups = "NRI1"; - }; - - pinctrl_nri2_default: nri2_default { - function = "NRI2"; - groups = "NRI2"; - }; - - pinctrl_nri3_default: nri3_default { - function = "NRI3"; - groups = "NRI3"; - }; - - pinctrl_nri4_default: nri4_default { - function = "NRI4"; - groups = "NRI4"; - }; - - pinctrl_nrts1_default: nrts1_default { - function = "NRTS1"; - groups = "NRTS1"; - }; - - pinctrl_nrts2_default: nrts2_default { - function = "NRTS2"; - groups = "NRTS2"; - }; - - pinctrl_nrts3_default: nrts3_default { - function = "NRTS3"; - groups = "NRTS3"; - }; - - pinctrl_nrts4_default: nrts4_default { - function = "NRTS4"; - groups = "NRTS4"; - }; - - pinctrl_oscclk_default: oscclk_default { - function = "OSCCLK"; - groups = "OSCCLK"; - }; - - pinctrl_pewake_default: pewake_default { - function = "PEWAKE"; - groups = "PEWAKE"; - }; - - pinctrl_pnor_default: pnor_default { - function = "PNOR"; - groups = "PNOR"; - }; - - pinctrl_pwm0_default: pwm0_default { - function = "PWM0"; - groups = "PWM0"; - }; - - pinctrl_pwm1_default: pwm1_default { - function = "PWM1"; - groups = "PWM1"; - }; - - pinctrl_pwm2_default: pwm2_default { - function = "PWM2"; - groups = "PWM2"; - }; - - pinctrl_pwm3_default: pwm3_default { - function = "PWM3"; - groups = "PWM3"; - }; - - pinctrl_pwm4_default: pwm4_default { - function = "PWM4"; - groups = "PWM4"; - }; - - pinctrl_pwm5_default: pwm5_default { - function = "PWM5"; - groups = "PWM5"; - }; - - pinctrl_pwm6_default: pwm6_default { - function = "PWM6"; - groups = "PWM6"; - }; - - pinctrl_pwm7_default: pwm7_default { - function = "PWM7"; - groups = "PWM7"; - }; - - pinctrl_rgmii1_default: rgmii1_default { - function = "RGMII1"; - groups = "RGMII1"; - }; - - pinctrl_rgmii2_default: rgmii2_default { - function = "RGMII2"; - groups = "RGMII2"; - }; - - pinctrl_rmii1_default: rmii1_default { - function = "RMII1"; - groups = "RMII1"; - }; - - pinctrl_rmii2_default: rmii2_default { - function = "RMII2"; - groups = "RMII2"; - }; - - pinctrl_rxd1_default: rxd1_default { - function = "RXD1"; - groups = "RXD1"; - }; - - pinctrl_rxd2_default: rxd2_default { - function = "RXD2"; - groups = "RXD2"; - }; - - pinctrl_rxd3_default: rxd3_default { - function = "RXD3"; - groups = "RXD3"; - }; - - pinctrl_rxd4_default: rxd4_default { - function = "RXD4"; - groups = "RXD4"; - }; - - pinctrl_salt1_default: salt1_default { - function = "SALT1"; - groups = "SALT1"; - }; - - pinctrl_salt10_default: salt10_default { - function = "SALT10"; - groups = "SALT10"; - }; - - pinctrl_salt11_default: salt11_default { - function = "SALT11"; - groups = "SALT11"; - }; - - pinctrl_salt12_default: salt12_default { - function = "SALT12"; - groups = "SALT12"; - }; - - pinctrl_salt13_default: salt13_default { - function = "SALT13"; - groups = "SALT13"; - }; - - pinctrl_salt14_default: salt14_default { - function = "SALT14"; - groups = "SALT14"; - }; - - pinctrl_salt2_default: salt2_default { - function = "SALT2"; - groups = "SALT2"; - }; - - pinctrl_salt3_default: salt3_default { - function = "SALT3"; - groups = "SALT3"; - }; - - pinctrl_salt4_default: salt4_default { - function = "SALT4"; - groups = "SALT4"; - }; - - pinctrl_salt5_default: salt5_default { - function = "SALT5"; - groups = "SALT5"; - }; - - pinctrl_salt6_default: salt6_default { - function = "SALT6"; - groups = "SALT6"; - }; - - pinctrl_salt7_default: salt7_default { - function = "SALT7"; - groups = "SALT7"; - }; - - pinctrl_salt8_default: salt8_default { - function = "SALT8"; - groups = "SALT8"; - }; - - pinctrl_salt9_default: salt9_default { - function = "SALT9"; - groups = "SALT9"; - }; - - pinctrl_scl1_default: scl1_default { - function = "SCL1"; - groups = "SCL1"; - }; - - pinctrl_scl2_default: scl2_default { - function = "SCL2"; - groups = "SCL2"; - }; - - pinctrl_sd1_default: sd1_default { - function = "SD1"; - groups = "SD1"; - }; - - pinctrl_sd2_default: sd2_default { - function = "SD2"; - groups = "SD2"; - }; - - pinctrl_sda1_default: sda1_default { - function = "SDA1"; - groups = "SDA1"; - }; - - pinctrl_sda2_default: sda2_default { - function = "SDA2"; - groups = "SDA2"; - }; - - pinctrl_sgpm_default: sgpm_default { - function = "SGPM"; - groups = "SGPM"; - }; - - pinctrl_sgps1_default: sgps1_default { - function = "SGPS1"; - groups = "SGPS1"; - }; - - pinctrl_sgps2_default: sgps2_default { - function = "SGPS2"; - groups = "SGPS2"; - }; - - pinctrl_sioonctrl_default: sioonctrl_default { - function = "SIOONCTRL"; - groups = "SIOONCTRL"; - }; - - pinctrl_siopbi_default: siopbi_default { - function = "SIOPBI"; - groups = "SIOPBI"; - }; - - pinctrl_siopbo_default: siopbo_default { - function = "SIOPBO"; - groups = "SIOPBO"; - }; - - pinctrl_siopwreq_default: siopwreq_default { - function = "SIOPWREQ"; - groups = "SIOPWREQ"; - }; - - pinctrl_siopwrgd_default: siopwrgd_default { - function = "SIOPWRGD"; - groups = "SIOPWRGD"; - }; - - pinctrl_sios3_default: sios3_default { - function = "SIOS3"; - groups = "SIOS3"; - }; - - pinctrl_sios5_default: sios5_default { - function = "SIOS5"; - groups = "SIOS5"; - }; - - pinctrl_siosci_default: siosci_default { - function = "SIOSCI"; - groups = "SIOSCI"; - }; - - pinctrl_spi1_default: spi1_default { - function = "SPI1"; - groups = "SPI1"; - }; - - pinctrl_spi1cs1_default: spi1cs1_default { - function = "SPI1CS1"; - groups = "SPI1CS1"; - }; - - pinctrl_spi1debug_default: spi1debug_default { - function = "SPI1DEBUG"; - groups = "SPI1DEBUG"; - }; - - pinctrl_spi1passthru_default: spi1passthru_default { - function = "SPI1PASSTHRU"; - groups = "SPI1PASSTHRU"; - }; - - pinctrl_spi2ck_default: spi2ck_default { - function = "SPI2CK"; - groups = "SPI2CK"; - }; - - pinctrl_spi2cs0_default: spi2cs0_default { - function = "SPI2CS0"; - groups = "SPI2CS0"; - }; - - pinctrl_spi2cs1_default: spi2cs1_default { - function = "SPI2CS1"; - groups = "SPI2CS1"; - }; - - pinctrl_spi2miso_default: spi2miso_default { - function = "SPI2MISO"; - groups = "SPI2MISO"; - }; - - pinctrl_spi2mosi_default: spi2mosi_default { - function = "SPI2MOSI"; - groups = "SPI2MOSI"; - }; - - pinctrl_timer3_default: timer3_default { - function = "TIMER3"; - groups = "TIMER3"; - }; - - pinctrl_timer4_default: timer4_default { - function = "TIMER4"; - groups = "TIMER4"; - }; - - pinctrl_timer5_default: timer5_default { - function = "TIMER5"; - groups = "TIMER5"; - }; - - pinctrl_timer6_default: timer6_default { - function = "TIMER6"; - groups = "TIMER6"; - }; - - pinctrl_timer7_default: timer7_default { - function = "TIMER7"; - groups = "TIMER7"; - }; - - pinctrl_timer8_default: timer8_default { - function = "TIMER8"; - groups = "TIMER8"; - }; - - pinctrl_txd1_default: txd1_default { - function = "TXD1"; - groups = "TXD1"; - }; - - pinctrl_txd2_default: txd2_default { - function = "TXD2"; - groups = "TXD2"; - }; - - pinctrl_txd3_default: txd3_default { - function = "TXD3"; - groups = "TXD3"; - }; - - pinctrl_txd4_default: txd4_default { - function = "TXD4"; - groups = "TXD4"; - }; - - pinctrl_uart6_default: uart6_default { - function = "UART6"; - groups = "UART6"; - }; - - pinctrl_usbcki_default: usbcki_default { - function = "USBCKI"; - groups = "USBCKI"; - }; - - pinctrl_usb2ah_default: usb2ah_default { - function = "USB2AH"; - groups = "USB2AH"; - }; - - pinctrl_usb2ad_default: usb2ad_default { - function = "USB2AD"; - groups = "USB2AD"; - }; - - pinctrl_usb11bhid_default: usb11bhid_default { - function = "USB11BHID"; - groups = "USB11BHID"; - }; - - pinctrl_usb2bh_default: usb2bh_default { - function = "USB2BH"; - groups = "USB2BH"; - }; - - pinctrl_vgabiosrom_default: vgabiosrom_default { - function = "VGABIOSROM"; - groups = "VGABIOSROM"; - }; - - pinctrl_vgahs_default: vgahs_default { - function = "VGAHS"; - groups = "VGAHS"; - }; - - pinctrl_vgavs_default: vgavs_default { - function = "VGAVS"; - groups = "VGAVS"; - }; - - pinctrl_vpi24_default: vpi24_default { - function = "VPI24"; - groups = "VPI24"; - }; - - pinctrl_vpo_default: vpo_default { - function = "VPO"; - groups = "VPO"; - }; - - pinctrl_wdtrst1_default: wdtrst1_default { - function = "WDTRST1"; - groups = "WDTRST1"; - }; - - pinctrl_wdtrst2_default: wdtrst2_default { - function = "WDTRST2"; - groups = "WDTRST2"; - }; -}; diff --git a/sys/gnu/dts/arm/aspeed-g6-pinctrl.dtsi b/sys/gnu/dts/arm/aspeed-g6-pinctrl.dtsi deleted file mode 100644 index 045ce66ca87..00000000000 --- a/sys/gnu/dts/arm/aspeed-g6-pinctrl.dtsi +++ /dev/null @@ -1,1149 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -// Copyright 2019 IBM Corp. - -&pinctrl { - pinctrl_adc0_default: adc0_default { - function = "ADC0"; - groups = "ADC0"; - }; - - pinctrl_adc1_default: adc1_default { - function = "ADC1"; - groups = "ADC1"; - }; - - pinctrl_adc10_default: adc10_default { - function = "ADC10"; - groups = "ADC10"; - }; - - pinctrl_adc11_default: adc11_default { - function = "ADC11"; - groups = "ADC11"; - }; - - pinctrl_adc12_default: adc12_default { - function = "ADC12"; - groups = "ADC12"; - }; - - pinctrl_adc13_default: adc13_default { - function = "ADC13"; - groups = "ADC13"; - }; - - pinctrl_adc14_default: adc14_default { - function = "ADC14"; - groups = "ADC14"; - }; - - pinctrl_adc15_default: adc15_default { - function = "ADC15"; - groups = "ADC15"; - }; - - pinctrl_adc2_default: adc2_default { - function = "ADC2"; - groups = "ADC2"; - }; - - pinctrl_adc3_default: adc3_default { - function = "ADC3"; - groups = "ADC3"; - }; - - pinctrl_adc4_default: adc4_default { - function = "ADC4"; - groups = "ADC4"; - }; - - pinctrl_adc5_default: adc5_default { - function = "ADC5"; - groups = "ADC5"; - }; - - pinctrl_adc6_default: adc6_default { - function = "ADC6"; - groups = "ADC6"; - }; - - pinctrl_adc7_default: adc7_default { - function = "ADC7"; - groups = "ADC7"; - }; - - pinctrl_adc8_default: adc8_default { - function = "ADC8"; - groups = "ADC8"; - }; - - pinctrl_adc9_default: adc9_default { - function = "ADC9"; - groups = "ADC9"; - }; - - pinctrl_bmcint_default: bmcint_default { - function = "BMCINT"; - groups = "BMCINT"; - }; - - pinctrl_espi_default: espi_default { - function = "ESPI"; - groups = "ESPI"; - }; - - pinctrl_espialt_default: espialt_default { - function = "ESPIALT"; - groups = "ESPIALT"; - }; - - pinctrl_fsi1_default: fsi1_default { - function = "FSI1"; - groups = "FSI1"; - }; - - pinctrl_fsi2_default: fsi2_default { - function = "FSI2"; - groups = "FSI2"; - }; - - pinctrl_fwspiabr_default: fwspiabr_default { - function = "FWSPIABR"; - groups = "FWSPIABR"; - }; - - pinctrl_fwspid_default: fwspid_default { - function = "FWSPID"; - groups = "FWSPID"; - }; - - pinctrl_fwqspid_default: fwqspid_default { - function = "FWQSPID"; - groups = "FWQSPID"; - }; - - pinctrl_fwspiwp_default: fwspiwp_default { - function = "FWSPIWP"; - groups = "FWSPIWP"; - }; - - pinctrl_gpit0_default: gpit0_default { - function = "GPIT0"; - groups = "GPIT0"; - }; - - pinctrl_gpit1_default: gpit1_default { - function = "GPIT1"; - groups = "GPIT1"; - }; - - pinctrl_gpit2_default: gpit2_default { - function = "GPIT2"; - groups = "GPIT2"; - }; - - pinctrl_gpit3_default: gpit3_default { - function = "GPIT3"; - groups = "GPIT3"; - }; - - pinctrl_gpit4_default: gpit4_default { - function = "GPIT4"; - groups = "GPIT4"; - }; - - pinctrl_gpit5_default: gpit5_default { - function = "GPIT5"; - groups = "GPIT5"; - }; - - pinctrl_gpit6_default: gpit6_default { - function = "GPIT6"; - groups = "GPIT6"; - }; - - pinctrl_gpit7_default: gpit7_default { - function = "GPIT7"; - groups = "GPIT7"; - }; - - pinctrl_gpiu0_default: gpiu0_default { - function = "GPIU0"; - groups = "GPIU0"; - }; - - pinctrl_gpiu1_default: gpiu1_default { - function = "GPIU1"; - groups = "GPIU1"; - }; - - pinctrl_gpiu2_default: gpiu2_default { - function = "GPIU2"; - groups = "GPIU2"; - }; - - pinctrl_gpiu3_default: gpiu3_default { - function = "GPIU3"; - groups = "GPIU3"; - }; - - pinctrl_gpiu4_default: gpiu4_default { - function = "GPIU4"; - groups = "GPIU4"; - }; - - pinctrl_gpiu5_default: gpiu5_default { - function = "GPIU5"; - groups = "GPIU5"; - }; - - pinctrl_gpiu6_default: gpiu6_default { - function = "GPIU6"; - groups = "GPIU6"; - }; - - pinctrl_gpiu7_default: gpiu7_default { - function = "GPIU7"; - groups = "GPIU7"; - }; - - pinctrl_hvi3c3_default: hvi3c3_default { - function = "HVI3C3"; - groups = "HVI3C3"; - }; - - pinctrl_hvi3c4_default: hvi3c4_default { - function = "HVI3C4"; - groups = "HVI3C4"; - }; - - pinctrl_i2c1_default: i2c1_default { - function = "I2C1"; - groups = "I2C1"; - }; - - pinctrl_i2c10_default: i2c10_default { - function = "I2C10"; - groups = "I2C10"; - }; - - pinctrl_i2c11_default: i2c11_default { - function = "I2C11"; - groups = "I2C11"; - }; - - pinctrl_i2c12_default: i2c12_default { - function = "I2C12"; - groups = "I2C12"; - }; - - pinctrl_i2c13_default: i2c13_default { - function = "I2C13"; - groups = "I2C13"; - }; - - pinctrl_i2c14_default: i2c14_default { - function = "I2C14"; - groups = "I2C14"; - }; - - pinctrl_i2c15_default: i2c15_default { - function = "I2C15"; - groups = "I2C15"; - }; - - pinctrl_i2c16_default: i2c16_default { - function = "I2C16"; - groups = "I2C16"; - }; - - pinctrl_i2c2_default: i2c2_default { - function = "I2C2"; - groups = "I2C2"; - }; - - pinctrl_i2c3_default: i2c3_default { - function = "I2C3"; - groups = "I2C3"; - }; - - pinctrl_i2c4_default: i2c4_default { - function = "I2C4"; - groups = "I2C4"; - }; - - pinctrl_i2c5_default: i2c5_default { - function = "I2C5"; - groups = "I2C5"; - }; - - pinctrl_i2c6_default: i2c6_default { - function = "I2C6"; - groups = "I2C6"; - }; - - pinctrl_i2c7_default: i2c7_default { - function = "I2C7"; - groups = "I2C7"; - }; - - pinctrl_i2c8_default: i2c8_default { - function = "I2C8"; - groups = "I2C8"; - }; - - pinctrl_i2c9_default: i2c9_default { - function = "I2C9"; - groups = "I2C9"; - }; - - pinctrl_i3c3_default: i3c3_default { - function = "I3C3"; - groups = "I3C3"; - }; - - pinctrl_i3c4_default: i3c4_default { - function = "I3C4"; - groups = "I3C4"; - }; - - pinctrl_i3c5_default: i3c5_default { - function = "I3C5"; - groups = "I3C5"; - }; - - pinctrl_i3c6_default: i3c6_default { - function = "I3C6"; - groups = "I3C6"; - }; - - pinctrl_jtagm_default: jtagm_default { - function = "JTAGM"; - groups = "JTAGM"; - }; - - pinctrl_lhpd_default: lhpd_default { - function = "LHPD"; - groups = "LHPD"; - }; - - pinctrl_lhsirq_default: lhsirq_default { - function = "LHSIRQ"; - groups = "LHSIRQ"; - }; - - pinctrl_lpc_default: lpc_default { - function = "LPC"; - groups = "LPC"; - }; - - pinctrl_lpchc_default: lpchc_default { - function = "LPCHC"; - groups = "LPCHC"; - }; - - pinctrl_lpcpd_default: lpcpd_default { - function = "LPCPD"; - groups = "LPCPD"; - }; - - pinctrl_lpcpme_default: lpcpme_default { - function = "LPCPME"; - groups = "LPCPME"; - }; - - pinctrl_lpcsmi_default: lpcsmi_default { - function = "LPCSMI"; - groups = "LPCSMI"; - }; - - pinctrl_lsirq_default: lsirq_default { - function = "LSIRQ"; - groups = "LSIRQ"; - }; - - pinctrl_maclink1_default: maclink1_default { - function = "MACLINK1"; - groups = "MACLINK1"; - }; - - pinctrl_maclink2_default: maclink2_default { - function = "MACLINK2"; - groups = "MACLINK2"; - }; - - pinctrl_maclink3_default: maclink3_default { - function = "MACLINK3"; - groups = "MACLINK3"; - }; - - pinctrl_maclink4_default: maclink4_default { - function = "MACLINK4"; - groups = "MACLINK4"; - }; - - pinctrl_mdio1_default: mdio1_default { - function = "MDIO1"; - groups = "MDIO1"; - }; - - pinctrl_mdio2_default: mdio2_default { - function = "MDIO2"; - groups = "MDIO2"; - }; - - pinctrl_mdio3_default: mdio3_default { - function = "MDIO3"; - groups = "MDIO3"; - }; - - pinctrl_mdio4_default: mdio4_default { - function = "MDIO4"; - groups = "MDIO4"; - }; - - pinctrl_ncts1_default: ncts1_default { - function = "NCTS1"; - groups = "NCTS1"; - }; - - pinctrl_ncts2_default: ncts2_default { - function = "NCTS2"; - groups = "NCTS2"; - }; - - pinctrl_ncts3_default: ncts3_default { - function = "NCTS3"; - groups = "NCTS3"; - }; - - pinctrl_ncts4_default: ncts4_default { - function = "NCTS4"; - groups = "NCTS4"; - }; - - pinctrl_ndcd1_default: ndcd1_default { - function = "NDCD1"; - groups = "NDCD1"; - }; - - pinctrl_ndcd2_default: ndcd2_default { - function = "NDCD2"; - groups = "NDCD2"; - }; - - pinctrl_ndcd3_default: ndcd3_default { - function = "NDCD3"; - groups = "NDCD3"; - }; - - pinctrl_ndcd4_default: ndcd4_default { - function = "NDCD4"; - groups = "NDCD4"; - }; - - pinctrl_ndsr1_default: ndsr1_default { - function = "NDSR1"; - groups = "NDSR1"; - }; - - pinctrl_ndsr2_default: ndsr2_default { - function = "NDSR2"; - groups = "NDSR2"; - }; - - pinctrl_ndsr3_default: ndsr3_default { - function = "NDSR3"; - groups = "NDSR3"; - }; - - pinctrl_ndsr4_default: ndsr4_default { - function = "NDSR4"; - groups = "NDSR4"; - }; - - pinctrl_ndtr1_default: ndtr1_default { - function = "NDTR1"; - groups = "NDTR1"; - }; - - pinctrl_ndtr2_default: ndtr2_default { - function = "NDTR2"; - groups = "NDTR2"; - }; - - pinctrl_ndtr3_default: ndtr3_default { - function = "NDTR3"; - groups = "NDTR3"; - }; - - pinctrl_ndtr4_default: ndtr4_default { - function = "NDTR4"; - groups = "NDTR4"; - }; - - pinctrl_nri1_default: nri1_default { - function = "NRI1"; - groups = "NRI1"; - }; - - pinctrl_nri2_default: nri2_default { - function = "NRI2"; - groups = "NRI2"; - }; - - pinctrl_nri3_default: nri3_default { - function = "NRI3"; - groups = "NRI3"; - }; - - pinctrl_nri4_default: nri4_default { - function = "NRI4"; - groups = "NRI4"; - }; - - pinctrl_nrts1_default: nrts1_default { - function = "NRTS1"; - groups = "NRTS1"; - }; - - pinctrl_nrts2_default: nrts2_default { - function = "NRTS2"; - groups = "NRTS2"; - }; - - pinctrl_nrts3_default: nrts3_default { - function = "NRTS3"; - groups = "NRTS3"; - }; - - pinctrl_nrts4_default: nrts4_default { - function = "NRTS4"; - groups = "NRTS4"; - }; - - pinctrl_oscclk_default: oscclk_default { - function = "OSCCLK"; - groups = "OSCCLK"; - }; - - pinctrl_pewake_default: pewake_default { - function = "PEWAKE"; - groups = "PEWAKE"; - }; - - pinctrl_pwm0_default: pwm0_default { - function = "PWM0"; - groups = "PWM0"; - }; - - pinctrl_pwm1_default: pwm1_default { - function = "PWM1"; - groups = "PWM1"; - }; - - pinctrl_pwm10g0_default: pwm10g0_default { - function = "PWM10"; - groups = "PWM10G0"; - }; - - pinctrl_pwm10g1_default: pwm10g1_default { - function = "PWM10"; - groups = "PWM10G1"; - }; - - pinctrl_pwm11g0_default: pwm11g0_default { - function = "PWM11"; - groups = "PWM11G0"; - }; - - pinctrl_pwm11g1_default: pwm11g1_default { - function = "PWM11"; - groups = "PWM11G1"; - }; - - pinctrl_pwm12g0_default: pwm12g0_default { - function = "PWM12"; - groups = "PWM12G0"; - }; - - pinctrl_pwm12g1_default: pwm12g1_default { - function = "PWM12"; - groups = "PWM12G1"; - }; - - pinctrl_pwm13g0_default: pwm13g0_default { - function = "PWM13"; - groups = "PWM13G0"; - }; - - pinctrl_pwm13g1_default: pwm13g1_default { - function = "PWM13"; - groups = "PWM13G1"; - }; - - pinctrl_pwm14g0_default: pwm14g0_default { - function = "PWM14"; - groups = "PWM14G0"; - }; - - pinctrl_pwm14g1_default: pwm14g1_default { - function = "PWM14"; - groups = "PWM14G1"; - }; - - pinctrl_pwm15g0_default: pwm15g0_default { - function = "PWM15"; - groups = "PWM15G0"; - }; - - pinctrl_pwm15g1_default: pwm15g1_default { - function = "PWM15"; - groups = "PWM15G1"; - }; - - pinctrl_pwm2_default: pwm2_default { - function = "PWM2"; - groups = "PWM2"; - }; - - pinctrl_pwm3_default: pwm3_default { - function = "PWM3"; - groups = "PWM3"; - }; - - pinctrl_pwm4_default: pwm4_default { - function = "PWM4"; - groups = "PWM4"; - }; - - pinctrl_pwm5_default: pwm5_default { - function = "PWM5"; - groups = "PWM5"; - }; - - pinctrl_pwm6_default: pwm6_default { - function = "PWM6"; - groups = "PWM6"; - }; - - pinctrl_pwm7_default: pwm7_default { - function = "PWM7"; - groups = "PWM7"; - }; - - pinctrl_pwm8g0_default: pwm8g0_default { - function = "PWM8"; - groups = "PWM8G0"; - }; - - pinctrl_pwm8g1_default: pwm8g1_default { - function = "PWM8"; - groups = "PWM8G1"; - }; - - pinctrl_pwm9g0_default: pwm9g0_default { - function = "PWM9"; - groups = "PWM9G0"; - }; - - pinctrl_pwm9g1_default: pwm9g1_default { - function = "PWM9"; - groups = "PWM9G1"; - }; - - pinctrl_qspi1_default: qspi1_default { - function = "QSPI1"; - groups = "QSPI1"; - }; - - pinctrl_qspi2_default: qspi2_default { - function = "QSPI2"; - groups = "QSPI2"; - }; - - pinctrl_rgmii1_default: rgmii1_default { - function = "RGMII1"; - groups = "RGMII1"; - }; - - pinctrl_rgmii2_default: rgmii2_default { - function = "RGMII2"; - groups = "RGMII2"; - }; - - pinctrl_rgmii3_default: rgmii3_default { - function = "RGMII3"; - groups = "RGMII3"; - }; - - pinctrl_rgmii4_default: rgmii4_default { - function = "RGMII4"; - groups = "RGMII4"; - }; - - pinctrl_rmii1_default: rmii1_default { - function = "RMII1"; - groups = "RMII1"; - }; - - pinctrl_rmii2_default: rmii2_default { - function = "RMII2"; - groups = "RMII2"; - }; - - pinctrl_rmii3_default: rmii3_default { - function = "RMII3"; - groups = "RMII3"; - }; - - pinctrl_rmii4_default: rmii4_default { - function = "RMII4"; - groups = "RMII4"; - }; - - pinctrl_rxd1_default: rxd1_default { - function = "RXD1"; - groups = "RXD1"; - }; - - pinctrl_rxd2_default: rxd2_default { - function = "RXD2"; - groups = "RXD2"; - }; - - pinctrl_rxd3_default: rxd3_default { - function = "RXD3"; - groups = "RXD3"; - }; - - pinctrl_rxd4_default: rxd4_default { - function = "RXD4"; - groups = "RXD4"; - }; - - pinctrl_salt1_default: salt1_default { - function = "SALT1"; - groups = "SALT1"; - }; - - pinctrl_salt10g0_default: salt10g0_default { - function = "SALT10"; - groups = "SALT10G0"; - }; - - pinctrl_salt10g1_default: salt10g1_default { - function = "SALT10"; - groups = "SALT10G1"; - }; - - pinctrl_salt11g0_default: salt11g0_default { - function = "SALT11"; - groups = "SALT11G0"; - }; - - pinctrl_salt11g1_default: salt11g1_default { - function = "SALT11"; - groups = "SALT11G1"; - }; - - pinctrl_salt12g0_default: salt12g0_default { - function = "SALT12"; - groups = "SALT12G0"; - }; - - pinctrl_salt12g1_default: salt12g1_default { - function = "SALT12"; - groups = "SALT12G1"; - }; - - pinctrl_salt13g0_default: salt13g0_default { - function = "SALT13"; - groups = "SALT13G0"; - }; - - pinctrl_salt13g1_default: salt13g1_default { - function = "SALT13"; - groups = "SALT13G1"; - }; - - pinctrl_salt14g0_default: salt14g0_default { - function = "SALT14"; - groups = "SALT14G0"; - }; - - pinctrl_salt14g1_default: salt14g1_default { - function = "SALT14"; - groups = "SALT14G1"; - }; - - pinctrl_salt15g0_default: salt15g0_default { - function = "SALT15"; - groups = "SALT15G0"; - }; - - pinctrl_salt15g1_default: salt15g1_default { - function = "SALT15"; - groups = "SALT15G1"; - }; - - pinctrl_salt16g0_default: salt16g0_default { - function = "SALT16"; - groups = "SALT16G0"; - }; - - pinctrl_salt16g1_default: salt16g1_default { - function = "SALT16"; - groups = "SALT16G1"; - }; - - pinctrl_salt2_default: salt2_default { - function = "SALT2"; - groups = "SALT2"; - }; - - pinctrl_salt3_default: salt3_default { - function = "SALT3"; - groups = "SALT3"; - }; - - pinctrl_salt4_default: salt4_default { - function = "SALT4"; - groups = "SALT4"; - }; - - pinctrl_salt5_default: salt5_default { - function = "SALT5"; - groups = "SALT5"; - }; - - pinctrl_salt6_default: salt6_default { - function = "SALT6"; - groups = "SALT6"; - }; - - pinctrl_salt7_default: salt7_default { - function = "SALT7"; - groups = "SALT7"; - }; - - pinctrl_salt8_default: salt8_default { - function = "SALT8"; - groups = "SALT8"; - }; - - pinctrl_salt9g0_default: salt9g0_default { - function = "SALT9"; - groups = "SALT9G0"; - }; - - pinctrl_salt9g1_default: salt9g1_default { - function = "SALT9"; - groups = "SALT9G1"; - }; - - pinctrl_sd1_default: sd1_default { - function = "SD1"; - groups = "SD1"; - }; - - pinctrl_sd2_default: sd2_default { - function = "SD2"; - groups = "SD2"; - }; - - pinctrl_emmc_default: emmc_default { - function = "EMMC"; - groups = "EMMCG4"; - }; - - pinctrl_sgpm1_default: sgpm1_default { - function = "SGPM1"; - groups = "SGPM1"; - }; - - pinctrl_sgps1_default: sgps1_default { - function = "SGPS1"; - groups = "SGPS1"; - }; - - pinctrl_sioonctrl_default: sioonctrl_default { - function = "SIOONCTRL"; - groups = "SIOONCTRL"; - }; - - pinctrl_siopbi_default: siopbi_default { - function = "SIOPBI"; - groups = "SIOPBI"; - }; - - pinctrl_siopbo_default: siopbo_default { - function = "SIOPBO"; - groups = "SIOPBO"; - }; - - pinctrl_siopwreq_default: siopwreq_default { - function = "SIOPWREQ"; - groups = "SIOPWREQ"; - }; - - pinctrl_siopwrgd_default: siopwrgd_default { - function = "SIOPWRGD"; - groups = "SIOPWRGD"; - }; - - pinctrl_sios3_default: sios3_default { - function = "SIOS3"; - groups = "SIOS3"; - }; - - pinctrl_sios5_default: sios5_default { - function = "SIOS5"; - groups = "SIOS5"; - }; - - pinctrl_siosci_default: siosci_default { - function = "SIOSCI"; - groups = "SIOSCI"; - }; - - pinctrl_spi1_default: spi1_default { - function = "SPI1"; - groups = "SPI1"; - }; - - pinctrl_spi1abr_default: spi1abr_default { - function = "SPI1ABR"; - groups = "SPI1ABR"; - }; - - pinctrl_spi1cs1_default: spi1cs1_default { - function = "SPI1CS1"; - groups = "SPI1CS1"; - }; - - pinctrl_spi1wp_default: spi1wp_default { - function = "SPI1WP"; - groups = "SPI1WP"; - }; - - pinctrl_spi2_default: spi2_default { - function = "SPI2"; - groups = "SPI2"; - }; - - pinctrl_spi2cs1_default: spi2cs1_default { - function = "SPI2CS1"; - groups = "SPI2CS1"; - }; - - pinctrl_spi2cs2_default: spi2cs2_default { - function = "SPI2CS2"; - groups = "SPI2CS2"; - }; - - pinctrl_tach0_default: tach0_default { - function = "TACH0"; - groups = "TACH0"; - }; - - pinctrl_tach1_default: tach1_default { - function = "TACH1"; - groups = "TACH1"; - }; - - pinctrl_tach10_default: tach10_default { - function = "TACH10"; - groups = "TACH10"; - }; - - pinctrl_tach11_default: tach11_default { - function = "TACH11"; - groups = "TACH11"; - }; - - pinctrl_tach12_default: tach12_default { - function = "TACH12"; - groups = "TACH12"; - }; - - pinctrl_tach13_default: tach13_default { - function = "TACH13"; - groups = "TACH13"; - }; - - pinctrl_tach14_default: tach14_default { - function = "TACH14"; - groups = "TACH14"; - }; - - pinctrl_tach15_default: tach15_default { - function = "TACH15"; - groups = "TACH15"; - }; - - pinctrl_tach2_default: tach2_default { - function = "TACH2"; - groups = "TACH2"; - }; - - pinctrl_tach3_default: tach3_default { - function = "TACH3"; - groups = "TACH3"; - }; - - pinctrl_tach4_default: tach4_default { - function = "TACH4"; - groups = "TACH4"; - }; - - pinctrl_tach5_default: tach5_default { - function = "TACH5"; - groups = "TACH5"; - }; - - pinctrl_tach6_default: tach6_default { - function = "TACH6"; - groups = "TACH6"; - }; - - pinctrl_tach7_default: tach7_default { - function = "TACH7"; - groups = "TACH7"; - }; - - pinctrl_tach8_default: tach8_default { - function = "TACH8"; - groups = "TACH8"; - }; - - pinctrl_tach9_default: tach9_default { - function = "TACH9"; - groups = "TACH9"; - }; - - pinctrl_thru0_default: thru0_default { - function = "THRU0"; - groups = "THRU0"; - }; - - pinctrl_thru1_default: thru1_default { - function = "THRU1"; - groups = "THRU1"; - }; - - pinctrl_thru2_default: thru2_default { - function = "THRU2"; - groups = "THRU2"; - }; - - pinctrl_thru3_default: thru3_default { - function = "THRU3"; - groups = "THRU3"; - }; - - pinctrl_txd1_default: txd1_default { - function = "TXD1"; - groups = "TXD1"; - }; - - pinctrl_txd2_default: txd2_default { - function = "TXD2"; - groups = "TXD2"; - }; - - pinctrl_txd3_default: txd3_default { - function = "TXD3"; - groups = "TXD3"; - }; - - pinctrl_txd4_default: txd4_default { - function = "TXD4"; - groups = "TXD4"; - }; - - pinctrl_uart10_default: uart10_default { - function = "UART10"; - groups = "UART10"; - }; - - pinctrl_uart11_default: uart11_default { - function = "UART11"; - groups = "UART11"; - }; - - pinctrl_uart12g0_default: uart12g0_default { - function = "UART12"; - groups = "UART12G0"; - }; - - pinctrl_uart12g1_default: uart12g1_default { - function = "UART12"; - groups = "UART12G1"; - }; - - pinctrl_uart13g0_default: uart13g0_default { - function = "UART13"; - groups = "UART13G0"; - }; - - pinctrl_uart13g1_default: uart13g1_default { - function = "UART13"; - groups = "UART13G1"; - }; - - pinctrl_uart6_default: uart6_default { - function = "UART6"; - groups = "UART6"; - }; - - pinctrl_uart7_default: uart7_default { - function = "UART7"; - groups = "UART7"; - }; - - pinctrl_uart8_default: uart8_default { - function = "UART8"; - groups = "UART8"; - }; - - pinctrl_uart9_default: uart9_default { - function = "UART9"; - groups = "UART9"; - }; - - pinctrl_vb_default: vb_default { - function = "VB"; - groups = "VB"; - }; - - pinctrl_vgahs_default: vgahs_default { - function = "VGAHS"; - groups = "VGAHS"; - }; - - pinctrl_vgavs_default: vgavs_default { - function = "VGAVS"; - groups = "VGAVS"; - }; - - pinctrl_wdtrst1_default: wdtrst1_default { - function = "WDTRST1"; - groups = "WDTRST1"; - }; - - pinctrl_wdtrst2_default: wdtrst2_default { - function = "WDTRST2"; - groups = "WDTRST2"; - }; - - pinctrl_wdtrst3_default: wdtrst3_default { - function = "WDTRST3"; - groups = "WDTRST3"; - }; - - pinctrl_wdtrst4_default: wdtrst4_default { - function = "WDTRST4"; - groups = "WDTRST4"; - }; -}; diff --git a/sys/gnu/dts/arm/aspeed-g6.dtsi b/sys/gnu/dts/arm/aspeed-g6.dtsi deleted file mode 100644 index 796976d275e..00000000000 --- a/sys/gnu/dts/arm/aspeed-g6.dtsi +++ /dev/null @@ -1,843 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -// Copyright 2019 IBM Corp. - -#include -#include - -/ { - model = "Aspeed BMC"; - compatible = "aspeed,ast2600"; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&gic>; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - i2c6 = &i2c6; - i2c7 = &i2c7; - i2c8 = &i2c8; - i2c9 = &i2c9; - i2c10 = &i2c10; - i2c11 = &i2c11; - i2c12 = &i2c12; - i2c13 = &i2c13; - i2c14 = &i2c14; - i2c15 = &i2c15; - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - serial3 = &uart4; - serial4 = &uart5; - serial5 = &vuart1; - serial6 = &vuart2; - }; - - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "aspeed,ast2600-smp"; - - cpu@f00 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <0xf00>; - }; - - cpu@f01 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <0xf01>; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupt-parent = <&gic>; - interrupts = , - , - , - ; - clocks = <&syscon ASPEED_CLK_HPLL>; - arm,cpu-registers-not-fw-configured; - }; - - ahb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - device_type = "soc"; - ranges; - - gic: interrupt-controller@40461000 { - compatible = "arm,cortex-a7-gic"; - interrupts = ; - #interrupt-cells = <3>; - interrupt-controller; - interrupt-parent = <&gic>; - reg = <0x40461000 0x1000>, - <0x40462000 0x1000>, - <0x40464000 0x2000>, - <0x40466000 0x2000>; - }; - - fmc: spi@1e620000 { - reg = < 0x1e620000 0xc4 - 0x20000000 0x10000000 >; - #address-cells = <1>; - #size-cells = <0>; - compatible = "aspeed,ast2600-fmc"; - clocks = <&syscon ASPEED_CLK_AHB>; - status = "disabled"; - interrupts = ; - flash@0 { - reg = < 0 >; - compatible = "jedec,spi-nor"; - spi-max-frequency = <50000000>; - status = "disabled"; - }; - flash@1 { - reg = < 1 >; - compatible = "jedec,spi-nor"; - spi-max-frequency = <50000000>; - status = "disabled"; - }; - flash@2 { - reg = < 2 >; - compatible = "jedec,spi-nor"; - spi-max-frequency = <50000000>; - status = "disabled"; - }; - }; - - spi1: spi@1e630000 { - reg = < 0x1e630000 0xc4 - 0x30000000 0x10000000 >; - #address-cells = <1>; - #size-cells = <0>; - compatible = "aspeed,ast2600-spi"; - clocks = <&syscon ASPEED_CLK_AHB>; - status = "disabled"; - flash@0 { - reg = < 0 >; - compatible = "jedec,spi-nor"; - spi-max-frequency = <50000000>; - status = "disabled"; - }; - flash@1 { - reg = < 1 >; - compatible = "jedec,spi-nor"; - spi-max-frequency = <50000000>; - status = "disabled"; - }; - }; - - spi2: spi@1e631000 { - reg = < 0x1e631000 0xc4 - 0x50000000 0x10000000 >; - #address-cells = <1>; - #size-cells = <0>; - compatible = "aspeed,ast2600-spi"; - clocks = <&syscon ASPEED_CLK_AHB>; - status = "disabled"; - flash@0 { - reg = < 0 >; - compatible = "jedec,spi-nor"; - spi-max-frequency = <50000000>; - status = "disabled"; - }; - flash@1 { - reg = < 1 >; - compatible = "jedec,spi-nor"; - spi-max-frequency = <50000000>; - status = "disabled"; - }; - flash@2 { - reg = < 2 >; - compatible = "jedec,spi-nor"; - spi-max-frequency = <50000000>; - status = "disabled"; - }; - }; - - mdio0: mdio@1e650000 { - compatible = "aspeed,ast2600-mdio"; - reg = <0x1e650000 0x8>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mdio1_default>; - }; - - mdio1: mdio@1e650008 { - compatible = "aspeed,ast2600-mdio"; - reg = <0x1e650008 0x8>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mdio2_default>; - }; - - mdio2: mdio@1e650010 { - compatible = "aspeed,ast2600-mdio"; - reg = <0x1e650010 0x8>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mdio3_default>; - }; - - mdio3: mdio@1e650018 { - compatible = "aspeed,ast2600-mdio"; - reg = <0x1e650018 0x8>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mdio4_default>; - }; - - mac0: ftgmac@1e660000 { - compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; - reg = <0x1e660000 0x180>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>; - status = "disabled"; - }; - - mac1: ftgmac@1e680000 { - compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; - reg = <0x1e680000 0x180>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>; - status = "disabled"; - }; - - mac2: ftgmac@1e670000 { - compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; - reg = <0x1e670000 0x180>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clocks = <&syscon ASPEED_CLK_GATE_MAC3CLK>; - status = "disabled"; - }; - - mac3: ftgmac@1e690000 { - compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; - reg = <0x1e690000 0x180>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clocks = <&syscon ASPEED_CLK_GATE_MAC4CLK>; - status = "disabled"; - }; - - apb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - syscon: syscon@1e6e2000 { - compatible = "aspeed,ast2600-scu", "syscon", "simple-mfd"; - reg = <0x1e6e2000 0x1000>; - ranges = <0 0x1e6e2000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - #clock-cells = <1>; - #reset-cells = <1>; - - pinctrl: pinctrl { - compatible = "aspeed,ast2600-pinctrl"; - }; - - smp-memram@180 { - compatible = "aspeed,ast2600-smpmem"; - reg = <0x180 0x40>; - }; - }; - - rng: hwrng@1e6e2524 { - compatible = "timeriomem_rng"; - reg = <0x1e6e2524 0x4>; - period = <1>; - quality = <100>; - }; - - gpio0: gpio@1e780000 { - #gpio-cells = <2>; - gpio-controller; - compatible = "aspeed,ast2600-gpio"; - reg = <0x1e780000 0x800>; - interrupts = ; - gpio-ranges = <&pinctrl 0 0 208>; - ngpios = <208>; - clocks = <&syscon ASPEED_CLK_APB2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio@1e780800 { - #gpio-cells = <2>; - gpio-controller; - compatible = "aspeed,ast2600-gpio"; - reg = <0x1e780800 0x800>; - interrupts = ; - gpio-ranges = <&pinctrl 0 208 36>; - ngpios = <36>; - clocks = <&syscon ASPEED_CLK_APB1>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - rtc: rtc@1e781000 { - compatible = "aspeed,ast2600-rtc"; - reg = <0x1e781000 0x18>; - interrupts = ; - status = "disabled"; - }; - - timer: timer@1e782000 { - compatible = "aspeed,ast2600-timer"; - reg = <0x1e782000 0x90>; - interrupts-extended = <&gic GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&syscon ASPEED_CLK_APB1>; - clock-names = "PCLK"; - }; - - uart1: serial@1e783000 { - compatible = "ns16550a"; - reg = <0x1e783000 0x20>; - reg-shift = <2>; - reg-io-width = <4>; - interrupts = ; - clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>; - resets = <&lpc_reset 4>; - no-loopback-test; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd1_default &pinctrl_rxd1_default>; - status = "disabled"; - }; - - uart5: serial@1e784000 { - compatible = "ns16550a"; - reg = <0x1e784000 0x1000>; - reg-shift = <2>; - interrupts = ; - clocks = <&syscon ASPEED_CLK_GATE_UART5CLK>; - no-loopback-test; - }; - - wdt1: watchdog@1e785000 { - compatible = "aspeed,ast2600-wdt"; - reg = <0x1e785000 0x40>; - }; - - wdt2: watchdog@1e785040 { - compatible = "aspeed,ast2600-wdt"; - reg = <0x1e785040 0x40>; - status = "disabled"; - }; - - wdt3: watchdog@1e785080 { - compatible = "aspeed,ast2600-wdt"; - reg = <0x1e785080 0x40>; - status = "disabled"; - }; - - wdt4: watchdog@1e7850c0 { - compatible = "aspeed,ast2600-wdt"; - reg = <0x1e7850C0 0x40>; - status = "disabled"; - }; - - lpc: lpc@1e789000 { - compatible = "aspeed,ast2600-lpc", "simple-mfd"; - reg = <0x1e789000 0x1000>; - - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x1e789000 0x1000>; - - lpc_bmc: lpc-bmc@0 { - compatible = "aspeed,ast2600-lpc-bmc", "simple-mfd", "syscon"; - reg = <0x0 0x80>; - reg-io-width = <4>; - - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x80>; - - kcs1: kcs1@0 { - compatible = "aspeed,ast2600-kcs-bmc"; - interrupts = ; - kcs_chan = <1>; - status = "disabled"; - }; - kcs2: kcs2@0 { - compatible = "aspeed,ast2600-kcs-bmc"; - interrupts = ; - kcs_chan = <2>; - status = "disabled"; - }; - kcs3: kcs3@0 { - compatible = "aspeed,ast2600-kcs-bmc"; - interrupts = ; - kcs_chan = <3>; - status = "disabled"; - }; - }; - - lpc_host: lpc-host@80 { - compatible = "aspeed,ast2600-lpc-host", "simple-mfd", "syscon"; - reg = <0x80 0x1e0>; - reg-io-width = <4>; - - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x80 0x1e0>; - - kcs4: kcs4@0 { - compatible = "aspeed,ast2600-kcs-bmc"; - interrupts = ; - kcs_chan = <4>; - status = "disabled"; - }; - - lpc_ctrl: lpc-ctrl@0 { - compatible = "aspeed,ast2600-lpc-ctrl"; - reg = <0x0 0x80>; - clocks = <&syscon ASPEED_CLK_GATE_LCLK>; - status = "disabled"; - }; - - lpc_snoop: lpc-snoop@0 { - compatible = "aspeed,ast2600-lpc-snoop"; - reg = <0x0 0x80>; - interrupts = ; - status = "disabled"; - }; - - lhc: lhc@20 { - compatible = "aspeed,ast2600-lhc"; - reg = <0x20 0x24 0x48 0x8>; - }; - - lpc_reset: reset-controller@18 { - compatible = "aspeed,ast2600-lpc-reset"; - reg = <0x18 0x4>; - #reset-cells = <1>; - }; - - ibt: ibt@c0 { - compatible = "aspeed,ast2600-ibt-bmc"; - reg = <0xc0 0x18>; - interrupts = ; - status = "disabled"; - }; - }; - }; - - sdc: sdc@1e740000 { - compatible = "aspeed,ast2600-sd-controller"; - reg = <0x1e740000 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1e740000 0x10000>; - clocks = <&syscon ASPEED_CLK_GATE_SDCLK>; - status = "disabled"; - - sdhci0: sdhci@1e740100 { - compatible = "aspeed,ast2600-sdhci", "sdhci"; - reg = <0x100 0x100>; - interrupts = ; - sdhci,auto-cmd12; - clocks = <&syscon ASPEED_CLK_SDIO>; - status = "disabled"; - }; - - sdhci1: sdhci@1e740200 { - compatible = "aspeed,ast2600-sdhci", "sdhci"; - reg = <0x200 0x100>; - interrupts = ; - sdhci,auto-cmd12; - clocks = <&syscon ASPEED_CLK_SDIO>; - status = "disabled"; - }; - }; - - emmc_controller: sdc@1e750000 { - compatible = "aspeed,ast2600-sd-controller"; - reg = <0x1e750000 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1e750000 0x10000>; - clocks = <&syscon ASPEED_CLK_GATE_EMMCCLK>; - status = "disabled"; - - emmc: sdhci@1e750100 { - compatible = "aspeed,ast2600-sdhci"; - reg = <0x100 0x100>; - sdhci,auto-cmd12; - interrupts = ; - clocks = <&syscon ASPEED_CLK_EMMC>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_emmc_default>; - }; - }; - - vuart1: serial@1e787000 { - compatible = "aspeed,ast2500-vuart"; - reg = <0x1e787000 0x40>; - reg-shift = <2>; - interrupts = ; - clocks = <&syscon ASPEED_CLK_APB1>; - no-loopback-test; - status = "disabled"; - }; - - vuart2: serial@1e788000 { - compatible = "aspeed,ast2500-vuart"; - reg = <0x1e788000 0x40>; - reg-shift = <2>; - interrupts = ; - clocks = <&syscon ASPEED_CLK_APB1>; - no-loopback-test; - status = "disabled"; - }; - - uart2: serial@1e78d000 { - compatible = "ns16550a"; - reg = <0x1e78d000 0x20>; - reg-shift = <2>; - reg-io-width = <4>; - interrupts = ; - clocks = <&syscon ASPEED_CLK_GATE_UART2CLK>; - resets = <&lpc_reset 5>; - no-loopback-test; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd2_default &pinctrl_rxd2_default>; - status = "disabled"; - }; - - uart3: serial@1e78e000 { - compatible = "ns16550a"; - reg = <0x1e78e000 0x20>; - reg-shift = <2>; - reg-io-width = <4>; - interrupts = ; - clocks = <&syscon ASPEED_CLK_GATE_UART3CLK>; - resets = <&lpc_reset 6>; - no-loopback-test; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd3_default &pinctrl_rxd3_default>; - status = "disabled"; - }; - - uart4: serial@1e78f000 { - compatible = "ns16550a"; - reg = <0x1e78f000 0x20>; - reg-shift = <2>; - reg-io-width = <4>; - interrupts = ; - clocks = <&syscon ASPEED_CLK_GATE_UART4CLK>; - resets = <&lpc_reset 7>; - no-loopback-test; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd4_default &pinctrl_rxd4_default>; - status = "disabled"; - }; - - i2c: bus@1e78a000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1e78a000 0x1000>; - }; - - fsim0: fsi@1e79b000 { - compatible = "aspeed,ast2600-fsi-master", "fsi-master"; - reg = <0x1e79b000 0x94>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fsi1_default>; - clocks = <&syscon ASPEED_CLK_GATE_FSICLK>; - status = "disabled"; - }; - - fsim1: fsi@1e79b100 { - compatible = "aspeed,ast2600-fsi-master", "fsi-master"; - reg = <0x1e79b100 0x94>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fsi2_default>; - clocks = <&syscon ASPEED_CLK_GATE_FSICLK>; - status = "disabled"; - }; - }; - }; -}; - -#include "aspeed-g6-pinctrl.dtsi" - -&i2c { - i2c0: i2c-bus@80 { - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - reg = <0x80 0x80>; - compatible = "aspeed,ast2600-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB2>; - resets = <&syscon ASPEED_RESET_I2C>; - interrupts = ; - bus-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1_default>; - status = "disabled"; - }; - - i2c1: i2c-bus@100 { - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - reg = <0x100 0x80>; - compatible = "aspeed,ast2600-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB2>; - resets = <&syscon ASPEED_RESET_I2C>; - interrupts = ; - bus-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2_default>; - status = "disabled"; - }; - - i2c2: i2c-bus@180 { - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - reg = <0x180 0x80>; - compatible = "aspeed,ast2600-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB2>; - resets = <&syscon ASPEED_RESET_I2C>; - interrupts = ; - bus-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3_default>; - status = "disabled"; - }; - - i2c3: i2c-bus@200 { - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - reg = <0x200 0x80>; - compatible = "aspeed,ast2600-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB2>; - resets = <&syscon ASPEED_RESET_I2C>; - interrupts = ; - bus-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4_default>; - status = "disabled"; - }; - - i2c4: i2c-bus@280 { - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - reg = <0x280 0x80>; - compatible = "aspeed,ast2600-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB2>; - resets = <&syscon ASPEED_RESET_I2C>; - interrupts = ; - bus-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c5_default>; - status = "disabled"; - }; - - i2c5: i2c-bus@300 { - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - reg = <0x300 0x80>; - compatible = "aspeed,ast2600-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB2>; - resets = <&syscon ASPEED_RESET_I2C>; - interrupts = ; - bus-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c6_default>; - status = "disabled"; - }; - - i2c6: i2c-bus@380 { - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - reg = <0x380 0x80>; - compatible = "aspeed,ast2600-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB2>; - resets = <&syscon ASPEED_RESET_I2C>; - interrupts = ; - bus-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c7_default>; - status = "disabled"; - }; - - i2c7: i2c-bus@400 { - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - reg = <0x400 0x80>; - compatible = "aspeed,ast2600-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB2>; - resets = <&syscon ASPEED_RESET_I2C>; - interrupts = ; - bus-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c8_default>; - status = "disabled"; - }; - - i2c8: i2c-bus@480 { - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - reg = <0x480 0x80>; - compatible = "aspeed,ast2600-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB2>; - resets = <&syscon ASPEED_RESET_I2C>; - interrupts = ; - bus-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c9_default>; - status = "disabled"; - }; - - i2c9: i2c-bus@500 { - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - reg = <0x500 0x80>; - compatible = "aspeed,ast2600-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB2>; - resets = <&syscon ASPEED_RESET_I2C>; - interrupts = ; - bus-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c10_default>; - status = "disabled"; - }; - - i2c10: i2c-bus@580 { - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - reg = <0x580 0x80>; - compatible = "aspeed,ast2600-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB2>; - resets = <&syscon ASPEED_RESET_I2C>; - interrupts = ; - bus-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c11_default>; - status = "disabled"; - }; - - i2c11: i2c-bus@600 { - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - reg = <0x600 0x80>; - compatible = "aspeed,ast2600-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB2>; - resets = <&syscon ASPEED_RESET_I2C>; - interrupts = ; - bus-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c12_default>; - status = "disabled"; - }; - - i2c12: i2c-bus@680 { - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - reg = <0x680 0x80>; - compatible = "aspeed,ast2600-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB2>; - resets = <&syscon ASPEED_RESET_I2C>; - interrupts = ; - bus-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c13_default>; - status = "disabled"; - }; - - i2c13: i2c-bus@700 { - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - reg = <0x700 0x80>; - compatible = "aspeed,ast2600-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB2>; - resets = <&syscon ASPEED_RESET_I2C>; - interrupts = ; - bus-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c14_default>; - status = "disabled"; - }; - - i2c14: i2c-bus@780 { - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - reg = <0x780 0x80>; - compatible = "aspeed,ast2600-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB2>; - resets = <&syscon ASPEED_RESET_I2C>; - interrupts = ; - bus-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c15_default>; - status = "disabled"; - }; - - i2c15: i2c-bus@800 { - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - reg = <0x800 0x80>; - compatible = "aspeed,ast2600-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB2>; - resets = <&syscon ASPEED_RESET_I2C>; - interrupts = ; - bus-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c16_default>; - status = "disabled"; - }; -}; diff --git a/sys/gnu/dts/arm/ast2500-facebook-netbmc-common.dtsi b/sys/gnu/dts/arm/ast2500-facebook-netbmc-common.dtsi deleted file mode 100644 index 7468f102bd7..00000000000 --- a/sys/gnu/dts/arm/ast2500-facebook-netbmc-common.dtsi +++ /dev/null @@ -1,95 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// Copyright (c) 2019 Facebook Inc. - -#include "aspeed-g5.dtsi" - -/ { - memory@80000000 { - reg = <0x80000000 0x40000000>; - }; -}; - -/* - * Update reset type to "system" (full chip) to fix warm reboot hang issue - * when reset type is set to default ("soc", gated by reset mask registers). - */ -&wdt1 { - status = "okay"; - aspeed,reset-type = "system"; -}; - -&wdt2 { - status = "disabled"; -}; - -&uart1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd1_default - &pinctrl_rxd1_default>; -}; - -&uart3 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd3_default - &pinctrl_rxd3_default>; -}; - -&uart5 { - status = "okay"; -}; - -&fmc { - status = "okay"; - - fmc_flash0: flash@0 { - status = "okay"; - m25p,fast-read; - label = "spi0.0"; - -#include "facebook-bmc-flash-layout.dtsi" - }; - - fmc_flash1: flash@1 { - status = "okay"; - m25p,fast-read; - label = "spi0.1"; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - flash1@0 { - reg = <0x0 0x2000000>; - label = "flash1"; - }; - }; - }; -}; - -&mac1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; -}; - -&rtc { - status = "okay"; -}; - -&vhub { - status = "okay"; -}; - -&sdmmc { - status = "okay"; -}; - -&sdhci1 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sd2_default>; -}; diff --git a/sys/gnu/dts/arm/at91-ariag25.dts b/sys/gnu/dts/arm/at91-ariag25.dts deleted file mode 100644 index dbfefef2869..00000000000 --- a/sys/gnu/dts/arm/at91-ariag25.dts +++ /dev/null @@ -1,182 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * at91-ariag25.dts - Device Tree file for Acme Systems Aria G25 (AT91SAM9G25 based) - * - * Copyright (C) 2013 Douglas Gilbert , - * Robert Nelson - */ -/dts-v1/; -#include "at91sam9g25.dtsi" - -/ { - model = "Acme Systems Aria G25"; - compatible = "acme,ariag25", "atmel,at91sam9x5ek", - "atmel,at91sam9x5", "atmel,at91sam9"; - - aliases { - serial5 = &uart0; - serial6 = &uart1; - }; - - chosen { - bootargs = "console=ttyS0,115200 root=/dev/mmcblk0p2 rw rootwait"; - }; - - memory { - /* 128 MB, change this for 256 MB revision */ - reg = <0x20000000 0x8000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <12000000>; - }; - }; - - leds { - compatible = "gpio-leds"; - - /* little green LED in middle of Aria G25 module */ - aria_led { - label = "aria_led"; - gpios = <&pioB 8 GPIO_ACTIVE_HIGH>; /* PB8 */ - linux,default-trigger = "heartbeat"; - }; - - }; - - onewire { - compatible = "w1-gpio"; - gpios = <&pioA 21 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_w1_0>; - }; -}; - -&adc0 { - status = "okay"; - atmel,adc-channels-used = <0xf>; -}; - -&dbgu { - status = "okay"; -}; - -&i2c0 { - status = "okay"; -}; - -&i2c1 { - status = "okay"; -}; - -/* TWD2+TCLK2 hidden behind ethernet, so no i2c2 */ - -&macb0 { - phy-mode = "rmii"; - /* - * following can be overwritten by bootloader: - * for example u-boot 'ftd set' command - */ - local-mac-address = [00 00 00 00 00 00]; - status = "okay"; -}; - - -&mmc0 { - /* N.B. Aria has no SD card detect (CD), assumed present */ - - pinctrl-0 = < - &pinctrl_mmc0_slot0_clk_cmd_dat0 - &pinctrl_mmc0_slot0_dat1_3>; - status = "okay"; - - slot@0 { - reg = <0>; - bus-width = <4>; - }; -}; - -&pinctrl { - w1_0 { - pinctrl_w1_0: w1_0-0 { - atmel,pins = <0 21 0x0 0x1>; /* PA21 PIO, pull-up */ - }; - }; -}; - -&rtc { - status = "okay"; -}; - -&tcb0 { - timer@0 { - compatible = "atmel,tcb-timer"; - reg = <0>; - }; - - timer@1 { - compatible = "atmel,tcb-timer"; - reg = <1>; - }; -}; - -/* - * UART0/1 pins are marked as GPIO on - * Aria documentation. - * Change to "okay" if you need additional serial ports - */ -&uart0 { - status = "disabled"; -}; - -&uart1 { - status = "disabled"; -}; - -&usart0 { - pinctrl-0 = <&pinctrl_usart0 - &pinctrl_usart0_rts - &pinctrl_usart0_cts>; - status = "okay"; -}; - -&usart1 { - pinctrl-0 = <&pinctrl_usart1 - /* &pinctrl_usart1_rts */ - /* &pinctrl_usart1_cts */ - >; - status = "okay"; -}; - -&usart2 { - /* cannot activate RTS2+CTS2, clash with - * ethernet on PB0 and PB1 */ - pinctrl-0 = <&pinctrl_usart2>; - status = "okay"; -}; - -&usart3 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xf8028000 0x200>; - interrupts = <8 4 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart3 - /* &pinctrl_usart3_rts */ - /* &pinctrl_usart3_cts */ - >; - status = "okay"; -}; - -&usb0 { - status = "okay"; - num-ports = <3>; -}; - -&usb1 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/at91-ariettag25.dts b/sys/gnu/dts/arm/at91-ariettag25.dts deleted file mode 100644 index 0267e72c074..00000000000 --- a/sys/gnu/dts/arm/at91-ariettag25.dts +++ /dev/null @@ -1,86 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree file for Arietta G25 - * This device tree is minimal, to activate more peripherals, see: - * http://dts.acmesystems.it/arietta/ - */ -/dts-v1/; -#include "at91sam9g25.dtsi" - -/ { - model = "Acme Systems Arietta G25"; - compatible = "acme,ariettag25", "atmel,at91sam9x5", "atmel,at91sam9"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - reg = <0x20000000 0x8000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <12000000>; - }; - }; - - leds { - compatible = "gpio-leds"; - - arietta_led { - label = "arietta_led"; - gpios = <&pioB 8 GPIO_ACTIVE_HIGH>; /* PB8 */ - linux,default-trigger = "heartbeat"; - }; - }; -}; - -&dbgu { - status = "okay"; -}; - -&mmc0 { - pinctrl-0 = < - &pinctrl_mmc0_slot0_clk_cmd_dat0 - &pinctrl_mmc0_slot0_dat1_3>; - status = "okay"; - - slot@0 { - reg = <0>; - bus-width = <4>; - }; -}; - -&rtc { - status = "okay"; -}; - -&tcb0 { - timer@0 { - compatible = "atmel,tcb-timer"; - reg = <0>; - }; - - timer@1 { - compatible = "atmel,tcb-timer"; - reg = <1>; - }; -}; - -&usb0 { - num-ports = <3>; - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; - -&usb2 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/at91-cosino.dtsi b/sys/gnu/dts/arm/at91-cosino.dtsi deleted file mode 100644 index feebd54f670..00000000000 --- a/sys/gnu/dts/arm/at91-cosino.dtsi +++ /dev/null @@ -1,151 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * at91-cosino.dtsi - Device Tree file for Cosino core module - * - * Copyright (C) 2013 - Rodolfo Giometti - * HCE Engineering - * - * Derived from at91sam9x5ek.dtsi by: - * Copyright (C) 2012 Atmel, - * 2012 Nicolas Ferre - */ - -#include "at91sam9g35.dtsi" - -/ { - model = "HCE Cosino core module"; - compatible = "hce,cosino", "atmel,at91sam9x5", "atmel,at91sam9"; - - chosen { - bootargs = "console=ttyS0,115200 root=/dev/mmcblk0p2 rw rootfstype=ext3 rootwait"; - }; - - memory { - reg = <0x20000000 0x8000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <12000000>; - }; - }; -}; - -&adc0 { - atmel,adc-ts-wires = <4>; - atmel,adc-ts-pressure-threshold = <10000>; - status = "okay"; -}; - -&dbgu { - status = "okay"; -}; - -&ebi { - pinctrl-0 = <&pinctrl_ebi_addr_nand - &pinctrl_ebi_data_0_7>; - pinctrl-names = "default"; - status = "okay"; - - nand-controller { - pinctrl-0 = <&pinctrl_nand_oe_we - &pinctrl_nand_cs - &pinctrl_nand_rb>; - pinctrl-names = "default"; - status = "okay"; - - nand@3 { - reg = <0x3 0x0 0x800000>; - rb-gpios = <&pioD 5 GPIO_ACTIVE_HIGH>; - cs-gpios = <&pioD 4 GPIO_ACTIVE_HIGH>; - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - nand-ecc-strength = <4>; - nand-ecc-step-size = <512>; - nand-on-flash-bbt; - label = "atmel_nand"; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - at91bootstrap@0 { - label = "at91bootstrap"; - reg = <0x0 0x40000>; - }; - - uboot@40000 { - label = "u-boot"; - reg = <0x40000 0x80000>; - }; - - ubootenv@c0000 { - label = "U-Boot Env"; - reg = <0xc0000 0x140000>; - }; - - kernel@200000 { - label = "kernel"; - reg = <0x200000 0x600000>; - }; - - rootfs@800000 { - label = "rootfs"; - reg = <0x800000 0x0f800000>; - }; - }; - }; - }; -}; - -&i2c0 { - status = "okay"; -}; - -&mmc0 { - pinctrl-0 = < - &pinctrl_board_mmc0 - &pinctrl_mmc0_slot0_clk_cmd_dat0 - &pinctrl_mmc0_slot0_dat1_3>; - status = "okay"; - - slot@0 { - reg = <0>; - bus-width = <4>; - cd-gpios = <&pioD 15 GPIO_ACTIVE_HIGH>; - }; -}; - -&pinctrl { - mmc0 { - pinctrl_board_mmc0: mmc0-board { - atmel,pins = - ; /* PD15 gpio CD pin pull up and deglitch */ - }; - }; -}; - -&tcb0 { - timer@0 { - compatible = "atmel,tcb-timer"; - reg = <0>; - }; - - timer@1 { - compatible = "atmel,tcb-timer"; - reg = <1>; - }; -}; - -&usart0 { - status = "okay"; -}; - -&watchdog { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/at91-cosino_mega2560.dts b/sys/gnu/dts/arm/at91-cosino_mega2560.dts deleted file mode 100644 index 73e88d1ba4e..00000000000 --- a/sys/gnu/dts/arm/at91-cosino_mega2560.dts +++ /dev/null @@ -1,74 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * at91-cosino_mega2560.dts - Device Tree file for Cosino board with - * Mega 2560 extension - * - * Copyright (C) 2013 - Rodolfo Giometti - * HCE Engineering - * - * Derived from at91sam9g35ek.dts by: - * Copyright (C) 2012 Atmel, - * 2012 Nicolas Ferre - */ - -/dts-v1/; -#include "at91-cosino.dtsi" - -/ { - model = "HCE Cosino Mega 2560"; - compatible = "hce,cosino_mega2560", "atmel,at91sam9x5", "atmel,at91sam9"; -}; - -&adc0 { - atmel,adc-ts-wires = <4>; - atmel,adc-ts-pressure-threshold = <10000>; - status = "okay"; -}; - -&macb0 { - phy-mode = "rmii"; - status = "okay"; -}; - -&mmc1 { - pinctrl-0 = < - &pinctrl_mmc1_slot0_clk_cmd_dat0 - &pinctrl_mmc1_slot0_dat1_3>; - status = "okay"; - - slot@0 { - reg = <0>; - bus-width = <4>; - non-removable; - }; -}; - -&rtc { - status = "okay"; -}; - -&usart1 { - status = "okay"; -}; - -&usart2 { - status = "okay"; -}; - -&usb0 { - num-ports = <3>; - atmel,vbus-gpio = <0 /* &pioD 18 GPIO_ACTIVE_LOW */ - &pioD 19 GPIO_ACTIVE_LOW - &pioD 20 GPIO_ACTIVE_LOW - >; - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; - -&usb2 { - atmel,vbus-gpio = <&pioB 16 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/at91-dvk_som60.dts b/sys/gnu/dts/arm/at91-dvk_som60.dts deleted file mode 100644 index ededd5b0d27..00000000000 --- a/sys/gnu/dts/arm/at91-dvk_som60.dts +++ /dev/null @@ -1,95 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * at91-dvk_som60.dts - Device Tree file for the DVK SOM60 board - * - * Copyright (C) 2018 Laird, - * 2018 Ben Whitten - * - */ -/dts-v1/; -#include "at91-som60.dtsi" -#include "at91-dvk_su60_somc.dtsi" -#include "at91-dvk_su60_somc_lcm.dtsi" - -/ { - model = "Laird DVK SOM60"; - compatible = "laird,dvk-som60", "laird,som60", "atmel,sama5d36", "atmel,sama5d3", "atmel,sama5"; - - chosen { - stdout-path = &dbgu; - tick-timer = &pit; - }; -}; - -&mmc0 { - status = "okay"; -}; - -&spi0 { - status = "okay"; -}; - -&ssc0 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; -}; - -&i2c1 { - status = "okay"; -}; - -&usart1 { - status = "okay"; -}; - -&usart2 { - status = "okay"; -}; - -&usart3 { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&dbgu { - status = "okay"; -}; - -&pit { - status = "okay"; -}; - -&adc0 { - status = "okay"; -}; - -&can1 { - status = "okay"; -}; - -&macb0 { - status = "okay"; -}; - -&macb1 { - status = "okay"; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; - -&usb2 { - status = "okay"; -}; - diff --git a/sys/gnu/dts/arm/at91-dvk_su60_somc.dtsi b/sys/gnu/dts/arm/at91-dvk_su60_somc.dtsi deleted file mode 100644 index 21876da7c44..00000000000 --- a/sys/gnu/dts/arm/at91-dvk_su60_somc.dtsi +++ /dev/null @@ -1,159 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * at91-dvk_su60_somc.dtsi - Device Tree file for the DVK SOM60 base board - * - * Copyright (C) 2018 Laird, - * 2018 Ben Whitten - * - */ - -/ { - sound { - compatible = "atmel,asoc-wm8904"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pck2_as_audio_mck>; - - atmel,model = "wm8904 @ DVK-SOM60"; - atmel,audio-routing = - "Headphone Jack", "HPOUTL", - "Headphone Jack", "HPOUTR", - "IN2L", "Line In Jack", - "IN2R", "Line In Jack", - "Mic", "MICBIAS", - "IN1L", "Mic"; - - atmel,ssc-controller = <&ssc0>; - atmel,audio-codec = <&wm8904>; - - status = "okay"; - }; -}; - -&mmc0 { - status = "okay"; - - pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_cd>; - slot@0 { - bus-width = <4>; - cd-gpios = <&pioE 31 GPIO_ACTIVE_HIGH>; - cd-inverted; - }; -}; - -&spi0 { - status = "okay"; - - /* spi0.0: 4M Flash Macronix MX25R4035FM1IL0 */ - spi-flash@0 { - compatible = "mxicy,mx25u4035", "jedec,spi-nor"; - spi-max-frequency = <33000000>; - reg = <0>; - }; -}; - -&ssc0 { - atmel,clk-from-rk-pin; - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - wm8904: wm8904@1a { - compatible = "wlf,wm8904"; - reg = <0x1a>; - clocks = <&pck2>; - clock-names = "mclk"; - }; -}; - -&i2c1 { - status = "okay"; - - eeprom@57 { - compatible = "giantec,gt24c32a", "atmel,24c32"; - reg = <0x57>; - pagesize = <32>; - }; -}; - -&usart1 { - status = "okay"; -}; - -&usart2 { - status = "okay"; -}; - -&usart3 { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&dbgu { - status = "okay"; -}; - -&pit { - status = "okay"; -}; - -&adc0 { - status = "okay"; -}; - -&can1 { - status = "okay"; -}; - -&macb0 { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - ethernet-phy@7 { - reg = <7>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_geth_int>; - interrupt-parent = <&pioB>; - interrupts = <25 IRQ_TYPE_EDGE_FALLING>; - txen-skew-ps = <800>; - txc-skew-ps = <3000>; - rxdv-skew-ps = <400>; - rxc-skew-ps = <3000>; - rxd0-skew-ps = <400>; - rxd1-skew-ps = <400>; - rxd2-skew-ps = <400>; - rxd3-skew-ps = <400>; - }; -}; - -&macb1 { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - ethernet-phy@1 { - reg = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_eth_int>; - interrupt-parent = <&pioC>; - interrupts = <10 IRQ_TYPE_EDGE_FALLING>; - }; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; - -&usb2 { - status = "okay"; -}; - diff --git a/sys/gnu/dts/arm/at91-dvk_su60_somc_lcm.dtsi b/sys/gnu/dts/arm/at91-dvk_su60_somc_lcm.dtsi deleted file mode 100644 index df0f0cc575c..00000000000 --- a/sys/gnu/dts/arm/at91-dvk_su60_somc_lcm.dtsi +++ /dev/null @@ -1,90 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * at91-dvk_su60_somc_lcm.dtsi - Device Tree file for the DVK SOM60 LCD board - * - * Copyright (C) 2018 Laird, - * 2018 Ben Whitten - * - */ - -/ { - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&hlcdc_pwm 0 50000 0>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - status = "okay"; - }; - - panel: panel { - compatible = "winstar,wf70gtiagdng0", "innolux,at070tn92", "simple-panel"; - backlight = <&backlight>; - power-supply = <&vcc_lcd_reg>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - panel_input: endpoint@0 { - reg = <0>; - remote-endpoint = <&hlcdc_panel_output>; - }; - }; - }; - - vcc_lcd_reg: fixedregulator_lcd { - compatible = "regulator-fixed"; - regulator-name = "VCC LCM"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - regulator-always-on; - status = "okay"; - }; -}; - -&pinctrl { - board { - pinctrl_lcd_ctp_int: lcd_ctp_int { - atmel,pins = - ; - }; - }; -}; - -&i2c1 { - status = "okay"; - - ft5426@38 { - compatible = "focaltech,ft5426", "edt,edt-ft5406"; - reg = <0x38>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd_ctp_int>; - - interrupt-parent = <&pioC>; - interrupts = <28 IRQ_TYPE_EDGE_FALLING>; - - touchscreen-size-x = <800>; - touchscreen-size-y = <480>; - }; -}; - -&hlcdc { - status = "okay"; - - hlcdc-display-controller { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_rgb888>; - - port@0 { - hlcdc_panel_output: endpoint@0 { - reg = <0>; - remote-endpoint = <&panel_input>; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/at91-foxg20.dts b/sys/gnu/dts/arm/at91-foxg20.dts deleted file mode 100644 index 683b9e37f9c..00000000000 --- a/sys/gnu/dts/arm/at91-foxg20.dts +++ /dev/null @@ -1,167 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * at91-foxg20.dts - Device Tree file for Acme Systems FoxG20 board - * - * Based on DT files for at91sam9g20ek evaluation board (AT91SAM9G20 SoC) - * - * Copyright (C) 2013 Douglas Gilbert - */ -/dts-v1/; -#include "at91sam9g20.dtsi" - -/ { - model = "Acme Systems FoxG20"; - compatible = "acme,foxg20", "atmel,at91sam9g20", "atmel,at91sam9"; - - chosen { - bootargs = "console=ttyS0,115200 root=/dev/mmcblk0p2 rw rootwait"; - }; - - memory { - reg = <0x20000000 0x4000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <18432000>; - }; - }; - - ahb { - apb { - tcb0: timer@fffa0000 { - timer@0 { - compatible = "atmel,tcb-timer"; - reg = <0>, <1>; - }; - - timer@2 { - compatible = "atmel,tcb-timer"; - reg = <2>; - }; - }; - - usb1: gadget@fffa4000 { - atmel,vbus-gpio = <&pioC 6 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - mmc0: mmc@fffa8000 { - pinctrl-0 = < - &pinctrl_mmc0_clk - &pinctrl_mmc0_slot1_cmd_dat0 - &pinctrl_mmc0_slot1_dat1_3>; - status = "okay"; - - slot@1 { - reg = <1>; - bus-width = <4>; - }; - }; - - usart0: serial@fffb0000 { - pinctrl-0 = - <&pinctrl_usart0 - &pinctrl_usart0_rts - &pinctrl_usart0_cts - >; - status = "okay"; - }; - - usart1: serial@fffb4000 { - status = "okay"; - }; - - usart2: serial@fffb8000 { - status = "okay"; - }; - - macb0: ethernet@fffc4000 { - phy-mode = "rmii"; - status = "okay"; - }; - - usart3: serial@fffd0000 { - status = "okay"; - }; - - uart0: serial@fffd4000 { - status = "okay"; - }; - - uart1: serial@fffd8000 { - status = "okay"; - }; - - dbgu: serial@fffff200 { - status = "okay"; - }; - - pinctrl@fffff400 { - board { - pinctrl_pck0_as_mck: pck0_as_mck { - atmel,pins = - ; - }; - }; - - mmc0_slot1 { - pinctrl_board_mmc0_slot1: mmc0_slot1-board { - atmel,pins = - ; /* CD pin */ - }; - }; - - i2c0 { - pinctrl_i2c0: i2c0-0 { - atmel,pins = - ; /* TWCK (SCL), open drain */ - }; - }; - }; - - watchdog@fffffd40 { - status = "okay"; - }; - }; - - usb0: ohci@500000 { - num-ports = <2>; - status = "okay"; - }; - }; - - i2c-gpio-0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - i2c-gpio,delay-us = <5>; /* ~85 kHz */ - status = "okay"; - }; - - leds { - compatible = "gpio-leds"; - - /* red LED marked "PC7" near mini USB (device) receptacle */ - user_led { - label = "user_led"; - gpios = <&pioC 7 GPIO_ACTIVE_HIGH>; /* PC7 */ - linux,default-trigger = "heartbeat"; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - - btn { - label = "Button"; - gpios = <&pioC 4 GPIO_ACTIVE_LOW>; - linux,code = <0x103>; - wakeup-source; - }; - }; -}; diff --git a/sys/gnu/dts/arm/at91-gatwick.dts b/sys/gnu/dts/arm/at91-gatwick.dts deleted file mode 100644 index 5a81cab5fc3..00000000000 --- a/sys/gnu/dts/arm/at91-gatwick.dts +++ /dev/null @@ -1,121 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * at91-gatwick.dts - Device Tree file for the Gatwick board - * - * Copyright (C) 2018 Laird - * - */ -/dts-v1/; -#include "at91-wb50n.dtsi" -#include - -/ { - model = "Laird Workgroup Bridge 50N - Project Gatwick"; - compatible = "laird,gatwick", "laird,wb50n", "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5"; - - gpio_keys { - compatible = "gpio-keys"; - autorepeat; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_key_gpio>; - - reset-button { - label = "Reset Button"; - linux,code = ; - gpios = <&pioE 31 GPIO_ACTIVE_LOW>; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - - ethernet { - label = "gatwick:yellow:ethernet"; - gpios = <&pioA 10 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - wifi { - label = "gatwick:green:wifi"; - gpios = <&pioA 28 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - ble { - label = "gatwick:blue:ble"; - gpios = <&pioA 22 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - lora { - label = "gatwick:orange:lora"; - gpios = <&pioA 26 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - blank { - label = "gatwick:green:blank"; - gpios = <&pioA 24 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - user { - label = "gatwick:yellow:user"; - gpios = <&pioA 12 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - }; -}; - -&pinctrl { - board { - pinctrl_key_gpio: key_gpio_0 { - atmel,pins = - ; /* PE31 GPIO with pullup deglitch */ - }; - }; -}; - -&mmc0 { - status = "okay"; -}; - -&macb1 { - status = "okay"; -}; - -&dbgu { - status = "okay"; -}; - -/* FTDI USART */ -&usart0 { - status = "okay"; -}; - -/* GPS USART */ -&usart1 { - pinctrl-0 = <&pinctrl_usart1>; - status = "okay"; -}; - -&spi1 { - status = "okay"; - - spidev@0 { - compatible = "semtech,sx1301"; - reg = <0>; - spi-max-frequency = <8000000>; - }; -}; - -&usb1 { - status = "okay"; - /delete-property/atmel,oc-gpio; -}; - -&usb2 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/at91-kizbox.dts b/sys/gnu/dts/arm/at91-kizbox.dts deleted file mode 100644 index 7d938ccf71b..00000000000 --- a/sys/gnu/dts/arm/at91-kizbox.dts +++ /dev/null @@ -1,177 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * at91-kizbox.dts - Device Tree file for Overkiz Kizbox board - * - * Copyright (C) 2012-2014 Boris BREZILLON - * 2014-2015 Gaël PORTAY - */ -/dts-v1/; -#include "at91sam9g20.dtsi" -#include - -/ { - model = "Overkiz Kizbox"; - compatible = "overkiz,kizbox", "atmel,at91sam9g20", "atmel,at91sam9"; - - chosen { - bootargs = "ubi.mtd=ubi"; - stdout-path = &dbgu; - }; - - memory { - reg = <0x20000000 0x2000000>; - }; - - clocks { - main_xtal { - clock-frequency = <18432000>; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - reset { - label = "PB_RST"; - gpios = <&pioB 30 GPIO_ACTIVE_HIGH>; - linux,code = <0x100>; - wakeup-source; - }; - - user { - label = "PB_USER"; - gpios = <&pioB 31 GPIO_ACTIVE_HIGH>; - linux,code = <0x101>; - wakeup-source; - }; - }; - - pwm_leds { - compatible = "pwm-leds"; - - network_green { - label = "pwm:green:network"; - pwms = <&tcb_pwm 2 10000000 PWM_POLARITY_INVERTED>; - max-brightness = <255>; - linux,default-trigger = "default-on"; - }; - - network_red { - label = "pwm:red:network"; - pwms = <&tcb_pwm 4 10000000 PWM_POLARITY_INVERTED>; - max-brightness = <255>; - linux,default-trigger = "default-on"; - }; - - user_green { - label = "pwm:green:user"; - pwms = <&tcb_pwm 0 10000000 PWM_POLARITY_INVERTED>; - max-brightness = <255>; - linux,default-trigger = "default-on"; - }; - - user_red { - label = "pwm:red:user"; - pwms = <&tcb_pwm 1 10000000 PWM_POLARITY_INVERTED>; - max-brightness = <255>; - linux,default-trigger = "default-on"; - }; - }; - - tcb_pwm: pwm { - compatible = "atmel,tcb-pwm"; - #pwm-cells = <3>; - tc-block = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_tcb1_tioa0 - &pinctrl_tcb1_tioa1 - &pinctrl_tcb1_tioa2 - &pinctrl_tcb1_tiob0>; - }; -}; - -&tcb0 { - timer@0 { - compatible = "atmel,tcb-timer"; - reg = <0>, <1>; - }; - - timer@2 { - compatible = "atmel,tcb-timer"; - reg = <2>; - }; -}; - -&ebi { - status = "okay"; -}; - -&nand_controller { - status = "okay"; - pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>; - pinctrl-names = "default"; - - nand@3 { - reg = <0x3 0x0 0x800000>; - rb-gpios = <&pioC 13 GPIO_ACTIVE_HIGH>; - cs-gpios = <&pioC 14 GPIO_ACTIVE_HIGH>; - nand-bus-width = <8>; - nand-ecc-mode = "soft"; - nand-on-flash-bbt; - label = "atmel_nand"; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - bootstrap@0 { - label = "bootstrap"; - reg = <0x0 0x20000>; - }; - - ubi@20000 { - label = "ubi"; - reg = <0x20000 0x7fe0000>; - }; - }; - }; -}; - -&macb0 { - phy-mode = "mii"; - pinctrl-0 = <&pinctrl_macb_rmii - &pinctrl_macb_rmii_mii_alt>; - status = "okay"; -}; - -&usart3 { - status = "okay"; -}; - -&dbgu { - status = "okay"; -}; - -&watchdog { - timeout-sec = <15>; - atmel,max-heartbeat-sec = <16>; - atmel,min-heartbeat-sec = <0>; - status = "okay"; -}; - -&usb0 { - num-ports = <1>; - status = "okay"; -}; - -&i2c_gpio0 { - status = "okay"; - - rtc: pcf8563@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; -}; diff --git a/sys/gnu/dts/arm/at91-kizbox2-2.dts b/sys/gnu/dts/arm/at91-kizbox2-2.dts deleted file mode 100644 index cab8b3579ef..00000000000 --- a/sys/gnu/dts/arm/at91-kizbox2-2.dts +++ /dev/null @@ -1,26 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * at91-kizbox2-2.dts - Device Tree file for the Kizbox2 with - * two head board - * - * Copyright (C) 2015 Overkiz SAS - * - * Authors: Antoine Aubert - * Kévin Raymond - */ -/dts-v1/; -#include "at91-kizbox2-common.dtsi" - -/ { - model = "Overkiz Kizbox 2 with two heads"; - compatible = "overkiz,kizbox2-2", "atmel,sama5d31", - "atmel,sama5d3", "atmel,sama5"; -}; - -&usart1 { - status = "okay"; -}; - -&usart2 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/at91-kizbox2-common.dtsi b/sys/gnu/dts/arm/at91-kizbox2-common.dtsi deleted file mode 100644 index af38253a6e7..00000000000 --- a/sys/gnu/dts/arm/at91-kizbox2-common.dtsi +++ /dev/null @@ -1,258 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * at91-kizbox2_common.dtsi - Device Tree Include file for - * Overkiz Kizbox 2 family SoC - * - * Copyright (C) 2014-2018 Overkiz SAS - * - * Authors: Antoine Aubert - * Gaël Portay - * Kévin Raymond - */ -#include "sama5d31.dtsi" - -/ { - chosen { - bootargs = "ubi.mtd=ubi"; - stdout-path = &dbgu; - }; - - memory { - reg = <0x20000000 0x10000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <12000000>; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - prog { - label = "PB_PROG"; - gpios = <&pioE 27 GPIO_ACTIVE_LOW>; - linux,code = <0x102>; - wakeup-source; - }; - - reset { - label = "PB_RST"; - gpios = <&pioE 29 GPIO_ACTIVE_LOW>; - linux,code = <0x100>; - wakeup-source; - }; - - user { - label = "PB_USER"; - gpios = <&pioE 31 GPIO_ACTIVE_HIGH>; - linux,code = <0x101>; - wakeup-source; - }; - }; - - pwm_leds { - compatible = "pwm-leds"; - - blue { - label = "pwm:blue:user"; - pwms = <&pwm0 2 10000000 0>; - max-brightness = <255>; - linux,default-trigger = "none"; - }; - - green { - label = "pwm:green:user"; - pwms = <&pwm0 1 10000000 0>; - max-brightness = <255>; - linux,default-trigger = "default-on"; - }; - - red { - label = "pwm:red:user"; - pwms = <&pwm0 0 10000000 0>; - max-brightness = <255>; - linux,default-trigger = "default-on"; - }; - }; -}; - -&i2c1 { - status = "okay"; - - pmic: act8865@5b { - compatible = "active-semi,act8865"; - reg = <0x5b>; - status = "okay"; - - regulators { - vcc_1v8_reg: DCDC_REG1 { - regulator-name = "VCC_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vcc_1v2_reg: DCDC_REG2 { - regulator-name = "VCC_1V2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - vcc_3v3_reg: DCDC_REG3 { - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vddfuse_reg: LDO_REG1 { - regulator-name = "FUSE_2V5"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - }; - - vddana_reg: LDO_REG2 { - regulator-name = "VDDANA"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vled_reg: LDO_REG3 { - regulator-name = "VLED"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - v3v8_rf_reg: LDO_REG4 { - regulator-name = "V3V8_RF"; - regulator-min-microvolt = <3800000>; - regulator-max-microvolt = <3800000>; - regulator-always-on; - }; - }; - }; -}; - -&usart0 { - atmel,use-dma-rx; - atmel,use-dma-tx; - status = "disabled"; -}; - -&usart1 { - atmel,use-dma-rx; - atmel,use-dma-tx; - status = "disabled"; -}; - -&usart2 { - atmel,use-dma-rx; - atmel,use-dma-tx; - status = "disabled"; -}; - -&pwm0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm0_pwmh0_1 - &pinctrl_pwm0_pwmh1_1 - &pinctrl_pwm0_pwmh2_0>; - status = "okay"; -}; - -&adc0 { - atmel,adc-vref = <3333>; - status = "okay"; -}; - -&macb1 { - phy-mode = "rmii"; - status = "okay"; -}; - -&dbgu { - status = "okay"; -}; - -&watchdog { - status = "okay"; -}; - -&ebi { - pinctrl-0 = <&pinctrl_ebi_nand_addr>; - pinctrl-names = "default"; - status = "okay"; -}; - -&nand_controller { - status = "okay"; - - nand@3 { - reg = <0x3 0x0 0x2>; - atmel,rb = <0>; - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - nand-ecc-strength = <4>; - nand-ecc-step-size = <512>; - nand-on-flash-bbt; - label = "atmel_nand"; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - bootstrap@0 { - label = "bootstrap"; - reg = <0x0 0x20000>; - }; - - ubi@20000 { - label = "ubi"; - reg = <0x20000 0x7fe0000>; - }; - }; - }; -}; - -&usb1 { - status = "okay"; -}; - -&usb2 { - status = "okay"; -}; - -/* WMBUS (inverted with IO in the latest schematic) */ -&pinctrl_usart0 { - atmel,pins = - ; -}; - -/* RTS */ -&pinctrl_usart1 { - atmel,pins = - ; -}; - -/* IO (inverted with WMBUS in the latest schematic) */ -&pinctrl_usart2 { - atmel,pins = - ; -}; diff --git a/sys/gnu/dts/arm/at91-kizbox2.dts b/sys/gnu/dts/arm/at91-kizbox2.dts deleted file mode 100644 index 50a14568f09..00000000000 --- a/sys/gnu/dts/arm/at91-kizbox2.dts +++ /dev/null @@ -1,216 +0,0 @@ -/* - * at91-kizbox2.dts - Device Tree file for Overkiz Kizbox 2 board - * - * Copyright (C) 2014 Gaël PORTAY - * - * Licensed under GPLv2 or later. - */ -/dts-v1/; -#include "sama5d31.dtsi" -#include - -/ { - model = "Overkiz Kizbox 2"; - compatible = "overkiz,kizbox2", "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5"; - - chosen { - bootargs = "ubi.mtd=ubi"; - stdout-path = &dbgu; - }; - - memory { - reg = <0x20000000 0x10000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <12000000>; - }; - }; - - ahb { - apb { - i2c1: i2c@f0018000 { - status = "okay"; - - pmic: act8865@5b { - compatible = "active-semi,act8865"; - reg = <0x5b>; - status = "okay"; - - regulators { - vcc_1v8_reg: DCDC_REG1 { - regulator-name = "VCC_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vcc_1v2_reg: DCDC_REG2 { - regulator-name = "VCC_1V2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - vcc_3v3_reg: DCDC_REG3 { - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vddfuse_reg: LDO_REG1 { - regulator-name = "FUSE_2V5"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - }; - - vddana_reg: LDO_REG2 { - regulator-name = "VDDANA"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vled_reg: LDO_REG3 { - regulator-name = "VLED"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - v3v8_rf_reg: LDO_REG4 { - regulator-name = "V3V8_RF"; - regulator-min-microvolt = <3800000>; - regulator-max-microvolt = <3800000>; - regulator-always-on; - }; - }; - }; - }; - - usart0: serial@f001c000 { - status = "okay"; - }; - - usart1: serial@f0020000 { - status = "okay"; - }; - - pwm0: pwm@f002c000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm0_pwmh0_1 - &pinctrl_pwm0_pwmh1_1 - &pinctrl_pwm0_pwmh2_0>; - status = "okay"; - }; - - adc0: adc@f8018000 { - atmel,adc-vref = <3333>; - status = "okay"; - }; - - usart2: serial@f8020000 { - status = "okay"; - }; - - macb1: ethernet@f802c000 { - phy-mode = "rmii"; - status = "okay"; - }; - - dbgu: serial@ffffee00 { - status = "okay"; - }; - - watchdog@fffffe40 { - status = "okay"; - }; - }; - - usb1: ohci@00600000 { - status = "okay"; - }; - - usb2: ehci@00700000 { - status = "okay"; - }; - - nand0: nand@60000000 { - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - atmel,has-pmecc; - atmel,pmecc-cap = <4>; - atmel,pmecc-sector-size = <512>; - nand-on-flash-bbt; - status = "okay"; - - bootstrap@0 { - label = "bootstrap"; - reg = <0x0 0x20000>; - }; - - ubi@20000 { - label = "ubi"; - reg = <0x20000 0x7fe0000>; - }; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - prog { - label = "PB_PROG"; - gpios = <&pioE 27 GPIO_ACTIVE_LOW>; - linux,code = <0x102>; - wakeup-source; - }; - - reset { - label = "PB_RST"; - gpios = <&pioE 29 GPIO_ACTIVE_LOW>; - linux,code = <0x100>; - wakeup-source; - }; - - user { - label = "PB_USER"; - gpios = <&pioE 31 GPIO_ACTIVE_HIGH>; - linux,code = <0x101>; - wakeup-source; - }; - }; - - pwm_leds { - compatible = "pwm-leds"; - - blue { - label = "pwm:blue:user"; - pwms = <&pwm0 2 10000000 0>; - max-brightness = <255>; - linux,default-trigger = "default-on"; - }; - - green { - label = "pwm:green:user"; - pwms = <&pwm0 1 10000000 0>; - max-brightness = <255>; - linux,default-trigger = "default-on"; - }; - - red { - label = "pwm:red:user"; - pwms = <&pwm0 0 10000000 0>; - max-brightness = <255>; - linux,default-trigger = "default-on"; - }; - }; -}; diff --git a/sys/gnu/dts/arm/at91-kizbox3-hs.dts b/sys/gnu/dts/arm/at91-kizbox3-hs.dts deleted file mode 100644 index 8734e7f8939..00000000000 --- a/sys/gnu/dts/arm/at91-kizbox3-hs.dts +++ /dev/null @@ -1,309 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * at91-kizbox3-hs.dts - Device Tree file for Overkiz KIZBOX3-HS board - * - * Copyright (C) 2018 Overkiz SAS - * - * Authors: Dorian Rocipon - * Kevin Carli - * Mickael Gardet - */ -/dts-v1/; -#include "at91-kizbox3_common.dtsi" - -/ { - model = "Overkiz KIZBOX3-HS"; - compatible = "overkiz,kizbox3-hs", "atmel,sama5d2", "atmel,sama5"; - - pwm_leds { - status = "okay"; - - red { - status = "okay"; - }; - - green { - status = "okay"; - }; - - blue { - status = "okay"; - }; - - white { - status = "okay"; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_led_red - &pinctrl_led_white>; - status = "okay"; - - red { - label = "pio:red:user"; - gpios = <&pioA PIN_PB1 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - white { - label = "pio:white:user"; - gpios = <&pioA PIN_PB8 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - pinctrl-names = "default" , "default", "default", - "default", "default" ; - pinctrl-0 = <&pinctrl_key_gpio_default>; - pinctrl-1 = <&pinctrl_pio_rf &pinctrl_pio_wifi>; - pinctrl-2 = <&pinctrl_pio_io_boot - &pinctrl_pio_io_reset - &pinctrl_pio_io_test_radio>; - pinctrl-3 = <&pinctrl_pio_zbe_test_radio - &pinctrl_pio_zbe_rst>; - pinctrl-4 = <&pinctrl_pio_input>; - - SW1 { - label = "SW1"; - gpios = <&pioA PIN_PA29 GPIO_ACTIVE_LOW>; - linux,code = <0x101>; - wakeup-source; - }; - - SW2 { - label = "SW2"; - gpios = <&pioA PIN_PA18 GPIO_ACTIVE_LOW>; - linux,code = <0x102>; - wakeup-source; - }; - - SW3 { - label = "SW3"; - gpios = <&pioA PIN_PA22 GPIO_ACTIVE_LOW>; - linux,code = <0x103>; - wakeup-source; - }; - - SW7 { - label = "SW7"; - gpios = <&pioA PIN_PA26 GPIO_ACTIVE_LOW>; - linux,code = <0x107>; - wakeup-source; - }; - - SW8 { - label = "SW8"; - gpios = <&pioA PIN_PA24 GPIO_ACTIVE_LOW>; - linux,code = <0x108>; - wakeup-source; - }; - }; - - gpios { - compatible = "gpio"; - status = "okay"; - - rf_on { - label = "rf on"; - gpio = <&pioA PIN_PC19 GPIO_ACTIVE_HIGH>; - output; - init-low; - }; - - wifi_on { - label = "wifi on"; - gpio = <&pioA PIN_PC20 GPIO_ACTIVE_HIGH>; - output; - init-low; - }; - - zbe_test_radio { - label = "zbe test radio"; - gpio = <&pioA PIN_PB21 GPIO_ACTIVE_HIGH>; - output; - init-low; - }; - - zbe_rst { - label = "zbe rst"; - gpio = <&pioA PIN_PB25 GPIO_ACTIVE_HIGH>; - output; - init-low; - }; - - io_reset { - label = "io reset"; - gpio = <&pioA PIN_PB30 GPIO_ACTIVE_HIGH>; - output; - init-low; - }; - - io_test_radio { - label = "io test radio"; - gpio = <&pioA PIN_PC9 GPIO_ACTIVE_HIGH>; - output; - init-low; - }; - - io_boot_0 { - label = "io boot 0"; - gpio = <&pioA PIN_PC11 GPIO_ACTIVE_HIGH>; - output; - init-low; - }; - - io_boot_1 { - label = "io boot 1"; - gpio = <&pioA PIN_PC17 GPIO_ACTIVE_HIGH>; - output; - init-low; - }; - - verbose_bootloader { - label = "verbose bootloader"; - gpio = <&pioA PIN_PB11 GPIO_ACTIVE_HIGH>; - input; - }; - - nail_bed_detection { - label = "nail bed detection"; - gpio = <&pioA PIN_PB12 GPIO_ACTIVE_HIGH>; - input; - }; - - id_usba { - label = "id usba"; - gpio = <&pioA PIN_PC0 GPIO_ACTIVE_LOW>; - input; - }; - }; -}; - -&pioA { - pinctrl_key_gpio_default: key_gpio_default { - pinmux= , - , - , - , - ; - bias-disable; - }; - - pinctrl_gpio { - pinctrl_pio_rf: gpio_rf { - pinmux = ; - bias-disable; - }; - pinctrl_pio_wifi: gpio_wifi { - pinmux = ; - bias-disable; - }; - pinctrl_pio_io_boot: gpio_io_boot { - pinmux = - , - ; - bias-disable; - }; - pinctrl_pio_io_test_radio: gpio_io_test_radio { - pinmux = ; - bias-disable; - }; - pinctrl_pio_zbe_test_radio: gpio_zbe_test_radio { - pinmux = ; - bias-disable; - }; - pinctrl_pio_zbe_rst: gpio_zbe_rst { - pinmux = ; - bias-disable; - }; - /* stm32 reset must be open drain (internal pull up) */ - pinctrl_pio_io_reset: gpio_io_reset { - pinmux = ; - bias-disable; - drive-open-drain = <1>; - output-low; - }; - pinctrl_pio_input: gpio_input { - pinmux = - , - , - ; - bias-disable; - }; - }; - - pinctrl_leds { - pinctrl_led_red: led_red { - pinmux = ; - bias-disable; - }; - pinctrl_led_white: led_white { - pinmux = ; - bias-disable; - }; - }; -}; - -&adc { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&uart4 { - status = "okay"; -}; - -&flx0 { - status = "okay"; - - uart5: serial@200 { - status = "okay"; - }; -}; - -&flx3 { - status = "okay"; - uart6: serial@200 { - status = "okay"; - }; -}; - -&flx4 { - status = "okay"; - - i2c2: i2c@600 { - status = "okay"; - }; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; - -&usb2 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/at91-kizbox3_common.dtsi b/sys/gnu/dts/arm/at91-kizbox3_common.dtsi deleted file mode 100644 index 299e74d2318..00000000000 --- a/sys/gnu/dts/arm/at91-kizbox3_common.dtsi +++ /dev/null @@ -1,412 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * at91-kizbox3.dts - Device Tree Include file for Overkiz Kizbox 3 - * family SoC boards - * - * Copyright (C) 2018 Overkiz SAS - * - * Authors: Dorian Rocipon - * Kevin Carli - * Mickael Gardet - */ -/dts-v1/; -#include "sama5d2.dtsi" -#include "sama5d2-pinfunc.h" -#include -#include -#include -#include - -/ { - model = "Overkiz Kizbox3"; - compatible = "overkiz,kizbox3", "atmel,sama5d2", "atmel,sama5"; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - serial4 = &uart4; - serial5 = &uart5; - serial6 = &uart6; - }; - - chosen { - bootargs = "ubi.mtd=ubi"; - stdout-path = "serial1:115200n8"; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <12000000>; - }; - }; - - vdd_adc_vddana: supply_3v3_ana { - compatible = "regulator-fixed"; - regulator-name = "adc-vddana"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_adc_vref: supply_3v3_ref { - compatible = "regulator-fixed"; - regulator-name = "adc-vref"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - pwm_leds { - compatible = "pwm-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm0_pwm_h0 - &pinctrl_pwm0_pwm_h1 - &pinctrl_pwm0_pwm_h2 - &pinctrl_pwm0_pwm_h3>; - status = "disabled"; - - red { - label = "pwm:red:user"; - pwms = <&pwm0 0 10000000 0>; - max-brightness = <255>; - linux,default-trigger = "default-on"; - status = "disabled"; - }; - - green { - label = "pwm:green:user"; - pwms = <&pwm0 1 10000000 0>; - max-brightness = <255>; - linux,default-trigger = "default-on"; - status = "disabled"; - }; - - blue { - label = "pwm:blue:user"; - pwms = <&pwm0 2 10000000 0>; - max-brightness = <255>; - status = "disabled"; - }; - - white { - label = "pwm:white:user"; - pwms = <&pwm0 3 10000000 0>; - max-brightness = <255>; - status = "disabled"; - }; - }; -}; - -&ebi { - status = "okay"; -}; - -&nand_controller { - status = "okay"; - - nand@3 { - pinctrl-0 = <&pinctrl_ebi_nand_addr>; - pinctrl-names = "default"; - reg = <0x3 0x0 0x800000>; - - atmel,rb = <0>; - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - nand-ecc-strength = <4>; - nand-ecc-step-size = <512>; - nand-on-flash-bbt; - label = "atmel_nand"; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - bootstrap@0 { - label = "bootstrap"; - reg = <0x0 0x20000>; - }; - - u-boot@20000 { - label = "u-boot"; - reg = <0x20000 0x140000>; - }; - - u-boot-factory@160000 { - label = "u-boot-factory"; - reg = <0x160000 0x140000>; - }; - - ubi@2A0000 { - label = "ubi"; - reg = <0x2A0000 0x7D60000>; - }; - }; - - }; -}; - -&rtc { - status = "okay"; -}; - -&pioA { - pinctrl_ebi_nand_addr: ebi-addr-1 { - pinmux = , - , - , - , - , - , - , - , - , - , - , - , - ; - bias-disable; - }; - - pinctrl_usart { - pinctrl_usart_0: usart0-0 { - pinmux = < PIN_PB26__URXD0>, ; - bias-disable; - }; - pinctrl_usart_1: usart1-0 { - pinmux = < PIN_PD2__URXD1>, ; - bias-disable; - }; - pinctrl_usart_2: usart2-0 { - pinmux = < PIN_PD4__URXD2>, ; - bias-disable; - }; - pinctrl_usart_3: usart3-0 { - pinmux = < PIN_PC12__URXD3>, ; - bias-disable; - }; - pinctrl_usart_4: usart4-0 { - pinmux = < PIN_PB3__URXD4>, ; - bias-disable; - }; - pinctrl_flx0_default: flx0_usart_default { - pinmux = , //TX - ; //RX - bias-disable; - }; - pinctrl_flx3_default: flx3_usart_default { - pinmux = , //RX - ; //TX - bias-disable; - }; - }; - - pinctrl_flx4_default: flx4_i2c2_default { - pinmux = , //DATA - ; //CLK - bias-disable; - drive-open-drain = <1>; - }; - - pinctrl_pwm0 { - pinctrl_pwm0_pwm_h0: pwm0_pwm_h0 { - pinmux = ; - bias-disable; - }; - pinctrl_pwm0_pwm_h1: pwm0_pwmh1 { - pinmux = ; - bias-disable; - }; - pinctrl_pwm0_pwm_h2: pwm0_pwm_h2 { - pinmux = ; - bias-disable; - }; - pinctrl_pwm0_pwm_h3: pwm0_pwm_h3 { - pinmux = ; - bias-disable; - }; - }; - - pinctrl_adc { - pinctrl_adc2: adc2 { - pinmux = ; - bias-disable; - }; - pinctrl_adc3: adc3 { - pinmux = ; - bias-disable; - }; - pinctrl_adc4: adc4 { - pinmux = ; - bias-disable; - }; - pinctrl_adc5: adc5 { - pinmux = ; - bias-disable; - }; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart_0>; - atmel,use-dma-rx; - atmel,use-dma-tx; - status = "disabled"; -}; - -/* debug uart */ -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart_1>; - atmel,use-dma-rx; - atmel,use-dma-tx; - status = "disabled"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart_2>; - atmel,use-dma-rx; - atmel,use-dma-tx; - status = "disabled"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart_3>; - atmel,use-dma-rx; - atmel,use-dma-tx; - status = "disabled"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart_4>; - atmel,use-dma-rx; - atmel,use-dma-tx; - status = "disabled"; -}; - -&flx0 { - atmel,flexcom-mode = ; - status = "disabled"; - - uart5: serial@200 { - compatible = "atmel,at91sam9260-usart"; - reg = <0x200 0x400>; - interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(11))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(12))>; - dma-names = "tx", "rx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; - clock-names = "usart"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flx0_default>; - atmel,fifo-size = <32>; - atmel,use-dma-rx; - atmel,use-dma-tx; - status = "disabled"; - }; -}; - -&flx3 { - atmel,flexcom-mode = ; - status = "disabled"; - - uart6: serial@200 { - compatible = "atmel,at91sam9260-usart"; - reg = <0x200 0x400>; - interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(17))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(18))>; - dma-names = "tx", "rx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; - clock-names = "usart"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flx3_default>; - atmel,fifo-size = <32>; - atmel,use-dma-rx; - atmel,use-dma-tx; - status = "disabled"; - }; -}; - -&flx4 { - atmel,flexcom-mode = ; - status = "disabled"; - - i2c2: i2c@600 { - compatible = "atmel,sama5d2-i2c"; - reg = <0x600 0x200>; - interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(19))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(20))>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flx4_default>; - atmel,fifo-size = <16>; - status = "disabled"; - }; -}; - -&pwm0 { - status = "okay"; -}; - -&shutdown_controller { - atmel,shdwc-debouncer = <976>; - atmel,wakeup-rtc-timer; - - input@0 { - reg = <0>; - atmel,wakeup-type = "low"; - }; -}; - -&watchdog { - status = "okay"; -}; - -&adc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_adc2 - &pinctrl_adc3 - &pinctrl_adc4 - &pinctrl_adc5>; - - vddana-supply = <&vdd_adc_vddana>; - vref-supply = <&vdd_adc_vref>; - status = "disabled"; -}; - -&securam { - export; - - /* export overkiz u-boot mode/version and factory */ - uboot@1400 { - reg = <0x1400 0x20>; - export; - }; -}; diff --git a/sys/gnu/dts/arm/at91-kizboxmini-base.dts b/sys/gnu/dts/arm/at91-kizboxmini-base.dts deleted file mode 100644 index 81c29ca5cc1..00000000000 --- a/sys/gnu/dts/arm/at91-kizboxmini-base.dts +++ /dev/null @@ -1,24 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * at91-kizboxmini-base.dts - Device Tree file for Overkiz Kizbox mini - * base board - * - * Copyright (C) 2015 Overkiz SAS - * Author: Antoine Aubert - * Kévin Raymond - */ -/dts-v1/; -#include "at91-kizboxmini-common.dtsi" - -/ { - model = "Overkiz Kizbox Mini"; - compatible = "overkiz,kizboxmini-base", "atmel,at91sam9g25", - "atmel,at91sam9x5", "atmel,at91sam9"; -}; - -&pinctrl_usart0 { - atmel,pins = - ; -}; diff --git a/sys/gnu/dts/arm/at91-kizboxmini-common.dtsi b/sys/gnu/dts/arm/at91-kizboxmini-common.dtsi deleted file mode 100644 index fddf267b2d1..00000000000 --- a/sys/gnu/dts/arm/at91-kizboxmini-common.dtsi +++ /dev/null @@ -1,170 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * at91-kizboxmini.dts - Device Tree file for Overkiz Kizbox mini board - * - * Copyright (C) 2014-2018 Overkiz SAS - * Author: Antoine Aubert - * Gaël Portay - * Kévin Raymond - * Dorian Rocipon - */ -#include "at91sam9g25.dtsi" - -/ { - chosen { - bootargs = "ubi.mtd=ubi"; - stdout-path = &dbgu; - }; - - memory { - reg = <0x20000000 0x8000000>; - }; - - clocks { - main_xtal { - clock-frequency = <12000000>; - }; - - slow_xtal { - clock-frequency = <32768>; - }; - - adc_op_clk { - status = "disabled"; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - prog { - label = "PB_PROG"; - gpios = <&pioC 17 GPIO_ACTIVE_LOW>; - linux,code = <0x102>; - wakeup-source; - }; - - reset { - label = "PB_RST"; - gpios = <&pioC 16 GPIO_ACTIVE_LOW>; - linux,code = <0x100>; - wakeup-source; - }; - }; - - leds: pwm_leds { - compatible = "pwm-leds"; - - led_blue: pwm_blue { - label = "pwm:blue:user"; - pwms = <&pwm0 2 10000000 0>; - max-brightness = <255>; - linux,default-trigger = "none"; - status = "disabled"; - }; - - led_green: pwm_green { - label = "pwm:green:user"; - pwms = <&pwm0 0 10000000 0>; - max-brightness = <255>; - linux,default-trigger = "default-on"; - }; - - led_red: pwm_red { - label = "pwm:red:user"; - pwms = <&pwm0 1 10000000 0>; - max-brightness = <255>; - linux,default-trigger = "default-on"; - }; - }; -}; - -&usart0 { - atmel,use-dma-rx; - atmel,use-dma-tx; - status = "okay"; -}; - -&macb0 { - phy-mode = "rmii"; - status = "okay"; -}; - -&pwm0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm0_pwm0_1 - &pinctrl_pwm0_pwm1_1 - &pinctrl_pwm0_pwm2_1>; - status = "okay"; -}; - -&dbgu { - status = "okay"; -}; - -&watchdog { - status = "okay"; -}; - -&adc0 { - status = "disabled"; -}; - -&rtc { - status = "disabled"; -}; - -&ebi { - pinctrl-0 = <&pinctrl_ebi_addr_nand - &pinctrl_ebi_data_0_7>; - pinctrl-names = "default"; - status = "okay"; -}; - -&nand_controller { - status = "okay"; - pinctrl-0 = <&pinctrl_nand_oe_we - &pinctrl_nand_cs - &pinctrl_nand_rb>; - pinctrl-names = "default"; - - nand@3 { - reg = <0x3 0x0 0x800000>; - rb-gpios = <&pioD 5 GPIO_ACTIVE_HIGH>; - cs-gpios = <&pioD 4 GPIO_ACTIVE_HIGH>; - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - nand-ecc-strength = <4>; - nand-ecc-step-size = <512>; - nand-on-flash-bbt; - label = "atmel_nand"; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - bootstrap@0 { - label = "bootstrap"; - reg = <0x0 0x20000>; - }; - - ubi@20000 { - label = "ubi"; - reg = <0x20000 0x7fe0000>; - }; - }; - }; -}; - -&usb0 { - num-ports = <1>; - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; - diff --git a/sys/gnu/dts/arm/at91-kizboxmini-mb.dts b/sys/gnu/dts/arm/at91-kizboxmini-mb.dts deleted file mode 100644 index c07d3076a9b..00000000000 --- a/sys/gnu/dts/arm/at91-kizboxmini-mb.dts +++ /dev/null @@ -1,26 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2015-2018 Overkiz SAS - * Author: Mickael Gardet - * Kévin Raymond - */ -/dts-v1/; -#include "at91-kizboxmini-common.dtsi" - -/ { - model = "Overkiz Kizbox Mini Mother Board"; - compatible = "overkiz,kizboxmini-mb", "atmel,at91sam9g25", - "atmel,at91sam9x5", "atmel,at91sam9"; -}; - -&usb0 { - num-ports = <2>; -}; - -&rtc { - status = "okay"; -}; - -&led_blue { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/at91-kizboxmini-rd.dts b/sys/gnu/dts/arm/at91-kizboxmini-rd.dts deleted file mode 100644 index ab50f4d2238..00000000000 --- a/sys/gnu/dts/arm/at91-kizboxmini-rd.dts +++ /dev/null @@ -1,49 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2015-2018 Overkiz SAS - * Author: Mickael Gardet - * Kévin Raymond - */ -/dts-v1/; -#include "at91-kizboxmini-common.dtsi" - -/ { - model = "Overkiz Kizbox Mini RailDIN"; - compatible = "overkiz,kizboxmini-rd", "atmel,at91sam9g25", - "atmel,at91sam9x5", "atmel,at91sam9"; - - clocks { - adc_op_clk { - status = "okay"; - }; - }; -}; - -&pinctrl { - adc0 { - pinctrl_adc0_ad5: adc0_ad5-0 { - /* pull-up disable */ - atmel,pins = ; - }; - }; -}; - -&usart0 { - status = "disabled"; -}; - -&rtc { - status = "okay"; -}; - -&led_blue { - status = "okay"; -}; - -&adc0 { - atmel,adc-vref = <2500>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_adc0_ad5>; - atmel,adc-channels-used = <0x0020>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/at91-kizboxmini.dts b/sys/gnu/dts/arm/at91-kizboxmini.dts deleted file mode 100644 index 9682d105d4d..00000000000 --- a/sys/gnu/dts/arm/at91-kizboxmini.dts +++ /dev/null @@ -1,129 +0,0 @@ -/* - * at91-kizboxmini.dts - Device Tree file for Overkiz Kizbox mini board - * - * Copyright (C) 2014 Gaël PORTAY - * - * Licensed under GPLv2 or later. - */ -/dts-v1/; -#include "at91sam9g25.dtsi" -#include - -/ { - model = "Overkiz Kizbox mini"; - compatible = "overkiz,kizboxmini", "atmel,at91sam9g25", "atmel,at91sam9x5", "atmel,at91sam9"; - - chosen { - bootargs = "ubi.mtd=ubi"; - stdout-path = &dbgu; - }; - - memory { - reg = <0x20000000 0x8000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <12000000>; - }; - }; - - ahb { - apb { - usart0: serial@f801c000 { - status = "okay"; - }; - - macb0: ethernet@f802c000 { - phy-mode = "rmii"; - status = "okay"; - }; - - pwm0: pwm@f8034000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm0_pwm0_1 - &pinctrl_pwm0_pwm1_1>; - status = "okay"; - }; - - dbgu: serial@fffff200 { - status = "okay"; - }; - - watchdog@fffffe40 { - status = "okay"; - }; - }; - - usb0: ohci@00600000 { - num-ports = <1>; - status = "okay"; - }; - - usb1: ehci@00700000 { - status = "okay"; - }; - - nand0: nand@40000000 { - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - atmel,has-pmecc; - atmel,pmecc-cap = <4>; - atmel,pmecc-sector-size = <512>; - nand-on-flash-bbt; - status = "okay"; - - bootstrap@0 { - label = "bootstrap"; - reg = <0x0 0x20000>; - }; - - ubi@20000 { - label = "ubi"; - reg = <0x20000 0x7fe0000>; - }; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - prog { - label = "PB_PROG"; - gpios = <&pioC 17 GPIO_ACTIVE_LOW>; - linux,code = <0x102>; - wakeup-source; - }; - - reset { - label = "PB_RST"; - gpios = <&pioC 16 GPIO_ACTIVE_LOW>; - linux,code = <0x100>; - wakeup-source; - }; - }; - - pwm_leds { - compatible = "pwm-leds"; - - green { - label = "pwm:green:user"; - pwms = <&pwm0 0 10000000 0>; - max-brightness = <255>; - linux,default-trigger = "default-on"; - }; - - red { - label = "pwm:red:user"; - pwms = <&pwm0 1 10000000 0>; - max-brightness = <255>; - linux,default-trigger = "default-on"; - }; - }; -}; diff --git a/sys/gnu/dts/arm/at91-linea.dtsi b/sys/gnu/dts/arm/at91-linea.dtsi deleted file mode 100644 index 41f163955b1..00000000000 --- a/sys/gnu/dts/arm/at91-linea.dtsi +++ /dev/null @@ -1,71 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * at91-linea.dtsi - Device Tree Include file for the Axentia Linea Module. - * - * Copyright (C) 2017 Axentia Technologies AB - * - * Author: Peter Rosin - */ - -#include "sama5d31.dtsi" - -/ { - compatible = "axentia,linea", - "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5"; - - memory { - reg = <0x20000000 0x4000000>; - }; -}; - -&slow_xtal { - clock-frequency = <32768>; -}; - -&main_xtal { - clock-frequency = <12000000>; -}; - -&tcb0 { - timer@0 { - compatible = "atmel,tcb-timer"; - reg = <0>; - }; - - timer@1 { - compatible = "atmel,tcb-timer"; - reg = <1>; - }; -}; - -&i2c0 { - status = "okay"; - - eeprom@51 { - compatible = "st,24c64", "atmel,24c64"; - reg = <0x51>; - pagesize = <32>; - }; -}; - -&ebi { - pinctrl-0 = <&pinctrl_ebi_nand_addr>; - pinctrl-names = "default"; - status = "okay"; -}; - - -&nand_controller { - status = "okay"; - - nand: nand@3 { - reg = <0x3 0x0 0x2>; - atmel,rb = <0>; - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - nand-ecc-strength = <4>; - nand-ecc-step-size = <512>; - nand-on-flash-bbt; - label = "atmel_nand"; - }; -}; diff --git a/sys/gnu/dts/arm/at91-natte.dtsi b/sys/gnu/dts/arm/at91-natte.dtsi deleted file mode 100644 index 49f0a0c46cd..00000000000 --- a/sys/gnu/dts/arm/at91-natte.dtsi +++ /dev/null @@ -1,244 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * at91-natte.dts - Device Tree include file for the Natte board - * - * Copyright (C) 2017 Axentia Technologies AB - * - * Author: Peter Rosin - */ - -/ { - mux: mux-controller { - compatible = "gpio-mux"; - #mux-control-cells = <0>; - - mux-gpios = <&ioexp 0 GPIO_ACTIVE_HIGH>, - <&ioexp 1 GPIO_ACTIVE_HIGH>, - <&ioexp 2 GPIO_ACTIVE_HIGH>; - }; - - batntc-mux { - compatible = "io-channel-mux"; - io-channels = <&adc 5>; - io-channel-names = "parent"; - mux-controls = <&mux>; - - channels = - "batntc0", "batntc1", "batntc2", "batntc3", - "batntc4", "batntc5", "batntc6", "batntc7"; - }; - - batv-mux { - compatible = "io-channel-mux"; - io-channels = <&adc 6>; - io-channel-names = "parent"; - mux-controls = <&mux>; - - channels = - "batv0", "batv1", "batv2", "batv3", - "batv4", "batv5", "batv6", "batv7"; - }; - - iout-mux { - compatible = "io-channel-mux"; - io-channels = <&adc 7>; - io-channel-names = "parent"; - mux-controls = <&mux>; - - channels = - "iout0", "iout1", "iout2", "iout3", - "iout4", "iout5", "iout6", "iout7"; - }; - - i2c-mux { - compatible = "i2c-mux"; - mux-locked; - i2c-parent = <&i2c0>; - mux-controls = <&mux>; - - #address-cells = <1>; - #size-cells = <0>; - - i2c@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - charger@9 { - compatible = "ti,bq24735"; - reg = <0x9>; - - ti,charge-current = <2000>; - ti,charge-voltage = <16800>; - - poll-interval = <20000>; - }; - }; - - i2c@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - charger@9 { - compatible = "ti,bq24735"; - reg = <0x9>; - - ti,charge-current = <2000>; - ti,charge-voltage = <16800>; - - poll-interval = <20000>; - }; - }; - - i2c@2 { - reg = <2>; - #address-cells = <1>; - #size-cells = <0>; - - charger@9 { - compatible = "ti,bq24735"; - reg = <0x9>; - - ti,charge-current = <2000>; - ti,charge-voltage = <16800>; - - poll-interval = <20000>; - }; - }; - - i2c@3 { - reg = <3>; - #address-cells = <1>; - #size-cells = <0>; - - charger@9 { - compatible = "ti,bq24735"; - reg = <0x9>; - - ti,charge-current = <2000>; - ti,charge-voltage = <16800>; - - poll-interval = <20000>; - }; - }; - - i2c@4 { - reg = <4>; - #address-cells = <1>; - #size-cells = <0>; - - charger@9 { - compatible = "ti,bq24735"; - reg = <0x9>; - - ti,charge-current = <2000>; - ti,charge-voltage = <16800>; - - poll-interval = <20000>; - }; - }; - - i2c@5 { - reg = <5>; - #address-cells = <1>; - #size-cells = <0>; - - charger@9 { - compatible = "ti,bq24735"; - reg = <0x9>; - - ti,charge-current = <2000>; - ti,charge-voltage = <16800>; - - poll-interval = <20000>; - }; - }; - - i2c@6 { - reg = <6>; - #address-cells = <1>; - #size-cells = <0>; - - charger@9 { - compatible = "ti,bq24735"; - reg = <0x9>; - - ti,charge-current = <2000>; - ti,charge-voltage = <16800>; - - poll-interval = <20000>; - }; - }; - - i2c@7 { - reg = <7>; - #address-cells = <1>; - #size-cells = <0>; - - charger@9 { - compatible = "ti,bq24735"; - reg = <0x9>; - - ti,charge-current = <2000>; - ti,charge-voltage = <16800>; - - poll-interval = <20000>; - }; - }; - }; -}; - -&i2c0 { - status = "okay"; - - ioexp: ioexp@20 { - #gpio-cells = <2>; - compatible = "semtech,sx1502q"; - reg = <0x20>; - - gpio-controller; - ngpios = <8>; - - pinctrl-names = "default"; - pinctrl-0 = <&gpio3_cfg_pins>; - - gpio3_cfg_pins: gpio3_cfg { - pins = "gpio3"; - bias-pull-up; - }; - }; - - adc: adc@48 { - compatible = "ti,ads1015"; - reg = <0x48>; - #io-channel-cells = <1>; - - #address-cells = <1>; - #size-cells = <0>; - - channel@4 { - reg = <4>; - ti,gain = <2>; - ti,datarate = <4>; - }; - - channel@5 { - reg = <5>; - ti,gain = <2>; - ti,datarate = <4>; - }; - - channel@6 { - reg = <6>; - ti,gain = <1>; - ti,datarate = <4>; - }; - - channel@7 { - reg = <7>; - ti,gain = <3>; - ti,datarate = <4>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/at91-nattis-2-natte-2.dts b/sys/gnu/dts/arm/at91-nattis-2-natte-2.dts deleted file mode 100644 index 4f123477e63..00000000000 --- a/sys/gnu/dts/arm/at91-nattis-2-natte-2.dts +++ /dev/null @@ -1,306 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * at91-nattis-2-natte-2.dts - Device Tree file for the Linea/Nattis board - * - * Copyright (C) 2017 Axentia Technologies AB - * - * Author: Peter Rosin - */ -/dts-v1/; -#include "at91-linea.dtsi" -#include "at91-natte.dtsi" - -/ { - model = "Axentia Linea-Nattis v2 Natte v2"; - compatible = "axentia,nattis-2", "axentia,natte-2", "axentia,linea", - "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5"; - - gpio-keys { - compatible = "gpio-keys"; - - wakeup { - label = "Wakeup"; - linux,code = <10>; - wakeup-source; - gpios = <&pioB 27 GPIO_ACTIVE_LOW>; - }; - }; - - panel_reg: panel-regulator { - compatible = "regulator-fixed"; - regulator-name = "panel-VCC"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - bl_reg: backlight-regulator { - compatible = "regulator-fixed"; - regulator-name = "panel-VDD"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - panel_bl: backlight { - compatible = "pwm-backlight"; - pwms = <&hlcdc_pwm 0 100000 0>; - - brightness-levels = < 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100>; - default-brightness-level = <40>; - - power-supply = <&bl_reg>; - enable-gpios = <&pioA 20 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_blon>; - }; - - panel: panel { - compatible = "sharp,lq150x1lg11", "panel-lvds"; - - backlight = <&panel_bl>; - power-supply = <&panel_reg>; - - width-mm = <304>; - height-mm = <228>; - - data-mapping = "jeida-18"; - - panel-timing { - // 1024x768 @ 60Hz (typical) - clock-frequency = <50000000 65000000 80000000>; - hactive = <1024>; - vactive = <768>; - hfront-porch = <48 88 88>; - hback-porch = <96 168 168>; - hsync-len = <32 64 64>; - vsync-len = <3 13 74>; - vfront-porch = <3 13 74>; - vback-porch = <3 12 74>; - }; - - port { - panel_input: endpoint { - remote-endpoint = <&lvds_encoder_output>; - }; - }; - }; - - lvds-encoder { - compatible = "ti,ds90c185", "lvds-encoder"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lvds_prlud0 &pinctrl_lvds_hipow0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - lvds_encoder_input: endpoint { - remote-endpoint = <&hlcdc_output>; - }; - }; - - port@1 { - reg = <1>; - - lvds_encoder_output: endpoint { - remote-endpoint = <&panel_input>; - }; - }; - }; - }; - - sound { - compatible = "simple-audio-card"; - - simple-audio-card,name = "nattis-tfa9879"; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&cpu_dai>; - simple-audio-card,frame-master = <&cpu_dai>; - simple-audio-card,widgets = "Line", "Line Out Jack"; - simple-audio-card,routing = "Line Out Jack", "LINEOUT"; - - cpu_dai: simple-audio-card,cpu { - sound-dai = <&ssc0>; - }; - - simple-audio-card,codec { - sound-dai = <&>; - }; - }; -}; - -&pinctrl { - nattis { - pinctrl_usba_vbus: usba_vbus { - atmel,pins = ; - }; - - pinctrl_mmc0_cd: mmc0_cd { - atmel,pins = ; - }; - - pinctrl_lvds_prlud0: lvds_prlud0 { - atmel,pins = ; - }; - - pinctrl_lvds_hipow0: lvds_hipow0 { - atmel,pins = ; - }; - - pinctrl_blon: blon { - atmel,pins = ; - }; - }; -}; - -&watchdog { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - clock-frequency = <100000>; - - temp@18 { - compatible = "nxp,se97b", "jedec,jc-42.4-temp"; - reg = <0x18>; - smbus-timeout-disable; - }; - - eeprom@50 { - compatible = "nxp,se97b", "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; - - amp: amplifier@6c { - compatible = "nxp,tfa9879"; - reg = <0x6c>; - #sound-dai-cells = <0>; - }; -}; - -&ssc0 { - status = "okay"; - - atmel,clk-from-rk-pin; - #sound-dai-cells = <0>; -}; - -&hlcdc { - status = "okay"; - - hlcdc-display-controller { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_rgb565>; - - port@0 { - hlcdc_output: endpoint { - remote-endpoint = <&lvds_encoder_input>; - bus-width = <16>; - }; - }; - }; -}; - -&mmc0 { - status = "okay"; - - pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 - &pinctrl_mmc0_dat1_3 - &pinctrl_mmc0_cd>; - - slot@0 { - reg = <0>; - bus-width = <4>; - cd-gpios = <&pioD 5 GPIO_ACTIVE_HIGH>; - cd-inverted; - }; -}; - -&usart0 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart0>; - atmel,use-dma-rx; -}; - -&nand { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - at91bootstrap@0 { - label = "at91bootstrap"; - reg = <0x0 0x40000>; - }; - - barebox@40000 { - label = "barebox"; - reg = <0x40000 0x60000>; - }; - - bareboxenv@c0000 { - label = "bareboxenv"; - reg = <0xc0000 0x40000>; - }; - - bareboxenv2@100000 { - label = "bareboxenv2"; - reg = <0x100000 0x40000>; - }; - - oftree@180000 { - label = "oftree"; - reg = <0x180000 0x20000>; - }; - - kernel@200000 { - label = "kernel"; - reg = <0x200000 0x500000>; - }; - - rootfs@800000 { - label = "rootfs"; - reg = <0x800000 0x1f800000>; - }; - }; -}; - -&dbgu { - status = "okay"; - - atmel,use-dma-rx; -}; - -&usb0 { - status = "okay"; - - atmel,vbus-gpio = <&pioD 28 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usba_vbus>; -}; diff --git a/sys/gnu/dts/arm/at91-qil_a9260.dts b/sys/gnu/dts/arm/at91-qil_a9260.dts deleted file mode 100644 index a50b7fd2149..00000000000 --- a/sys/gnu/dts/arm/at91-qil_a9260.dts +++ /dev/null @@ -1,214 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * at91-qil_a9260.dts - Device Tree file for Calao QIL A9260 board - * - * Copyright (C) 2011-2013 Jean-Christophe PLAGNIOL-VILLARD - */ -/dts-v1/; -#include "at91sam9260.dtsi" -/ { - model = "Calao QIL A9260"; - compatible = "calao,qil-a9260", "atmel,at91sam9260", "atmel,at91sam9"; - - chosen { - bootargs = "console=ttyS0,115200"; - }; - - memory { - reg = <0x20000000 0x4000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <12000000>; - }; - }; - - ahb { - apb { - tcb0: timer@fffa0000 { - timer@0 { - compatible = "atmel,tcb-timer"; - reg = <0>, <1>; - }; - - timer@2 { - compatible = "atmel,tcb-timer"; - reg = <2>; - }; - }; - - usb1: gadget@fffa4000 { - atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - mmc0: mmc@fffa8000 { - pinctrl-0 = < - &pinctrl_mmc0_clk - &pinctrl_mmc0_slot0_cmd_dat0 - &pinctrl_mmc0_slot0_dat1_3>; - status = "okay"; - slot@0 { - reg = <0>; - bus-width = <4>; - }; - }; - - usart0: serial@fffb0000 { - pinctrl-0 = - <&pinctrl_usart0 - &pinctrl_usart0_rts - &pinctrl_usart0_cts - &pinctrl_usart0_dtr_dsr - &pinctrl_usart0_dcd - &pinctrl_usart0_ri>; - status = "okay"; - }; - - usart1: serial@fffb4000 { - pinctrl-0 = - <&pinctrl_usart1 - &pinctrl_usart1_rts - &pinctrl_usart1_cts>; - status = "okay"; - }; - - usart2: serial@fffb8000 { - pinctrl-0 = - <&pinctrl_usart2 - &pinctrl_usart2_rts - &pinctrl_usart2_cts>; - status = "okay"; - }; - - macb0: ethernet@fffc4000 { - phy-mode = "rmii"; - status = "okay"; - }; - - spi0: spi@fffc8000 { - status = "okay"; - cs-gpios = <&pioA 3 GPIO_ACTIVE_HIGH>; - - m41t94@0 { - compatible = "st,m41t94"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - - }; - - dbgu: serial@fffff200 { - status = "okay"; - }; - - shdwc@fffffd10 { - atmel,wakeup-counter = <10>; - atmel,wakeup-rtt-timer; - }; - }; - - usb0: ohci@500000 { - num-ports = <2>; - status = "okay"; - }; - - ebi: ebi@10000000 { - status = "okay"; - - nand_controller: nand-controller { - status = "okay"; - pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>; - pinctrl-names = "default"; - - nand@3 { - reg = <0x3 0x0 0x800000>; - rb-gpios = <&pioC 13 GPIO_ACTIVE_HIGH>; - cs-gpios = <&pioC 14 GPIO_ACTIVE_HIGH>; - nand-bus-width = <8>; - nand-ecc-mode = "soft"; - nand-on-flash-bbt; - label = "atmel_nand"; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - at91bootstrap@0 { - label = "at91bootstrap"; - reg = <0x0 0x20000>; - }; - - barebox@20000 { - label = "barebox"; - reg = <0x20000 0x40000>; - }; - - bareboxenv@60000 { - label = "bareboxenv"; - reg = <0x60000 0x20000>; - }; - - bareboxenv2@80000 { - label = "bareboxenv2"; - reg = <0x80000 0x20000>; - }; - - oftree@a0000 { - label = "oftree"; - reg = <0xa0000 0x20000>; - }; - - kernel@c0000 { - label = "kernel"; - reg = <0xc0000 0x400000>; - }; - - rootfs@4c0000 { - label = "rootfs"; - reg = <0x4c0000 0x7800000>; - }; - - data@7cc0000 { - label = "data"; - reg = <0x7cc0000 0x8340000>; - }; - }; - }; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - user_led { - label = "user_led"; - gpios = <&pioB 21 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - user_pb { - label = "user_pb"; - gpios = <&pioB 10 GPIO_ACTIVE_LOW>; - linux,code = <28>; - wakeup-source; - }; - }; - - i2c-gpio-0 { - status = "okay"; - }; -}; diff --git a/sys/gnu/dts/arm/at91-sam9_l9260.dts b/sys/gnu/dts/arm/at91-sam9_l9260.dts deleted file mode 100644 index 954404ed815..00000000000 --- a/sys/gnu/dts/arm/at91-sam9_l9260.dts +++ /dev/null @@ -1,132 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * at91-sam9_l9260.dts - Device Tree file for Olimex SAM9-L9260 board - * - * Copyright (C) 2016 Raashid Muhammed - */ -/dts-v1/; -#include "at91sam9260.dtsi" - -/ { - model = "Olimex sam9-l9260"; - compatible = "olimex,sam9-l9260", "atmel,at91sam9260", "atmel,at91sam9"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - reg = <0x20000000 0x4000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <18432000>; - }; - }; - - ahb { - apb { - tcb0: timer@fffa0000 { - timer@0 { - compatible = "atmel,tcb-timer"; - reg = <0>, <1>; - }; - - timer@2 { - compatible = "atmel,tcb-timer"; - reg = <2>; - }; - }; - - mmc0: mmc@fffa8000 { - pinctrl-0 = < - &pinctrl_board_mmc0 - &pinctrl_mmc0_clk - &pinctrl_mmc0_slot1_cmd_dat0 - &pinctrl_mmc0_slot1_dat1_3>; - status = "okay"; - - slot@1 { - reg = <1>; - bus-width = <4>; - cd-gpios = <&pioC 8 GPIO_ACTIVE_HIGH>; - wp-gpios = <&pioC 4 GPIO_ACTIVE_HIGH>; - }; - }; - - macb0: ethernet@fffc4000 { - pinctrl-0 = <&pinctrl_macb_rmii &pinctrl_macb_rmii_mii_alt>; - phy-mode = "mii"; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - ethernet-phy@1 { - reg = <0x1>; - }; - }; - - spi0: spi@fffc8000 { - cs-gpios = <&pioC 11 0>, <0>, <0>, <0>; - status = "okay"; - - flash@0 { - compatible = "atmel,at45", "atmel,dataflash"; - spi-max-frequency = <15000000>; - reg = <0>; - }; - }; - - dbgu: serial@fffff200 { - status = "okay"; - }; - - pinctrl@fffff400 { - mmc0 { - pinctrl_board_mmc0: mmc0-board { - atmel,pins = - ; /* WP pin */ - }; - }; - }; - }; - - nand0: nand@40000000 { - nand-bus-width = <8>; - nand-ecc-mode = "soft"; - nand-on-flash-bbt = <1>; - status = "okay"; - }; - - usb0: ohci@500000 { - status = "okay"; - }; - - }; - - i2c-gpio-0 { - status = "okay"; - }; - - leds { - compatible = "gpio-leds"; - - pwr_led { - label = "sam9-l9260:yellow:pwr"; - gpios = <&pioA 9 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "cpu0"; - }; - - status_led { - label = "sam9-l9260:green:status"; - gpios = <&pioA 6 GPIO_ACTIVE_LOW>; - linux,default-trigger = "timer"; - }; - }; -}; diff --git a/sys/gnu/dts/arm/at91-sam9x60ek.dts b/sys/gnu/dts/arm/at91-sam9x60ek.dts deleted file mode 100644 index 9f30132d7d7..00000000000 --- a/sys/gnu/dts/arm/at91-sam9x60ek.dts +++ /dev/null @@ -1,647 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * at91-sam9x60ek.dts - Device Tree file for Microchip SAM9X60-EK board - * - * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries - * - * Author: Sandeep Sheriker M - */ -/dts-v1/; -#include "sam9x60.dtsi" - -/ { - model = "Microchip SAM9X60-EK"; - compatible = "microchip,sam9x60ek", "microchip,sam9x60", "atmel,at91sam9"; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - serial1 = &uart1; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <24000000>; - }; - }; - - regulators: regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - vdd_1v8: fixed-regulator-vdd_1v8@0 { - compatible = "regulator-fixed"; - regulator-name = "VDD_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - status = "okay"; - }; - - vdd_1v5: fixed-regulator-vdd_1v5@1 { - compatible = "regulator-fixed"; - regulator-name = "VDD_1V5"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - status = "okay"; - }; - - vdd1_3v3: fixed-regulator-vdd1_3v3@2 { - compatible = "regulator-fixed"; - regulator-name = "VDD1_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - status = "okay"; - }; - - vdd2_3v3: regulator-fixed-vdd2_3v3@3 { - compatible = "regulator-fixed"; - regulator-name = "VDD2_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - status = "okay"; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_key_gpio_default>; - status = "okay"; - - sw1 { - label = "SW1"; - gpios = <&pioD 18 GPIO_ACTIVE_LOW>; - linux,code=<0x104>; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - status = "okay"; /* Conflict with pwm0. */ - - red { - label = "red"; - gpios = <&pioB 11 GPIO_ACTIVE_HIGH>; - }; - - green { - label = "green"; - gpios = <&pioB 12 GPIO_ACTIVE_HIGH>; - }; - - blue { - label = "blue"; - gpios = <&pioB 13 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; -}; - -&adc { - vddana-supply = <&vdd1_3v3>; - vref-supply = <&vdd1_3v3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_adc_default &pinctrl_adtrg_default>; - status = "okay"; -}; - -&can0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can0_rx_tx>; - status = "disabled"; /* Conflict with dbgu. */ -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can1_rx_tx>; - status = "okay"; -}; - -&classd { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_classd_default>; - atmel,pwm-type = "diff"; - atmel,non-overlap-time = <10>; - status = "okay"; -}; - -&dbgu { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_dbgu>; - status = "okay"; /* Conflict with can0. */ -}; - -&ebi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ebi_addr_nand &pinctrl_ebi_data_0_7>; - status = "okay"; - - nand_controller: nand-controller { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nand_oe_we &pinctrl_nand_cs &pinctrl_nand_rb>; - status = "okay"; - - nand@3 { - reg = <0x3 0x0 0x800000>; - rb-gpios = <&pioD 5 GPIO_ACTIVE_HIGH>; - cs-gpios = <&pioD 4 GPIO_ACTIVE_HIGH>; - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - nand-ecc-strength = <8>; - nand-ecc-step-size = <512>; - nand-on-flash-bbt; - label = "atmel_nand"; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - at91bootstrap@0 { - label = "at91bootstrap"; - reg = <0x0 0x40000>; - }; - - uboot@40000 { - label = "u-boot"; - reg = <0x40000 0xc0000>; - }; - - ubootenvred@100000 { - label = "U-Boot Env Redundant"; - reg = <0x100000 0x40000>; - }; - - ubootenv@140000 { - label = "U-Boot Env"; - reg = <0x140000 0x40000>; - }; - - dtb@180000 { - label = "device tree"; - reg = <0x180000 0x80000>; - }; - - kernel@200000 { - label = "kernel"; - reg = <0x200000 0x600000>; - }; - - rootfs@800000 { - label = "rootfs"; - reg = <0x800000 0x1f800000>; - }; - }; - }; - }; -}; - -&flx0 { - atmel,flexcom-mode = ; - status = "okay"; - - i2c0: i2c@600 { - compatible = "microchip,sam9x60-i2c"; - reg = <0x600 0x200>; - interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flx0_default>; - atmel,fifo-size = <16>; - i2c-analog-filter; - i2c-digital-filter; - i2c-digital-filter-width-ns = <35>; - status = "okay"; - - eeprom@53 { - compatible = "atmel,24c32"; - reg = <0x53>; - pagesize = <16>; - size = <128>; - status = "okay"; - }; - }; -}; - -&flx4 { - atmel,flexcom-mode = ; - status = "disabled"; - - spi0: spi@400 { - compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi"; - reg = <0x400 0x200>; - interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; - clock-names = "spi_clk"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flx4_default>; - atmel,fifo-size = <16>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; -}; - -&flx5 { - atmel,flexcom-mode = ; - status = "okay"; - - uart1: serial@200 { - compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart"; - reg = <0x200 0x200>; - interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(10))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(11))>; - dma-names = "tx", "rx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; - clock-names = "usart"; - pinctrl-0 = <&pinctrl_flx5_default>; - pinctrl-names = "default"; - atmel,use-dma-rx; - atmel,use-dma-tx; - status = "okay"; - }; -}; - -&flx6 { - atmel,flexcom-mode = ; - status = "okay"; - - i2c1: i2c@600 { - compatible = "microchip,sam9x60-i2c"; - reg = <0x600 0x200>; - interrupts = <9 IRQ_TYPE_LEVEL_HIGH 7>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flx6_default>; - atmel,fifo-size = <16>; - i2c-analog-filter; - i2c-digital-filter; - i2c-digital-filter-width-ns = <35>; - status = "okay"; - - gpio_exp: mcp23008@20 { - compatible = "microchip,mcp23008"; - reg = <0x20>; - }; - }; -}; - -&i2s { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2s_default>; - #sound-dai-cells = <0>; - status = "disabled"; /* Conflict with QSPI. */ -}; - -&macb0 { - phy-mode = "rmii"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_macb0_rmii>; - status = "okay"; - - ethernet-phy@0 { - reg = <0x0>; - }; -}; - -&pinctrl { - atmel,mux-mask = < - /* A B C */ - 0xFFFFFE7F 0xC0E0397F 0xEF00019D /* pioA */ - 0x03FFFFFF 0x02FC7E68 0x00780000 /* pioB */ - 0xffffffff 0xF83FFFFF 0xB800F3FC /* pioC */ - 0x003FFFFF 0x003F8000 0x00000000 /* pioD */ - >; - - adc { - pinctrl_adc_default: adc_default { - atmel,pins = ; - }; - - pinctrl_adtrg_default: adtrg_default { - atmel,pins = ; - }; - }; - - dbgu { - pinctrl_dbgu: dbgu-0 { - atmel,pins = ; - }; - }; - - i2s { - pinctrl_i2s_default: i2s { - atmel,pins = - ; /* I2SMCK */ - }; - }; - - qspi { - pinctrl_qspi: qspi { - atmel,pins = - ; - }; - }; - - nand { - pinctrl_nand_oe_we: nand-oe-we-0 { - atmel,pins = - ; - }; - - pinctrl_nand_rb: nand-rb-0 { - atmel,pins = - ; - }; - - pinctrl_nand_cs: nand-cs-0 { - atmel,pins = - ; - }; - }; - - ebi { - pinctrl_ebi_data_0_7: ebi-data-lsb-0 { - atmel,pins = - ; - }; - - pinctrl_ebi_data_0_15: ebi-data-msb-0 { - atmel,pins = - ; - }; - - pinctrl_ebi_addr_nand: ebi-addr-0 { - atmel,pins = - ; - }; - }; - - flexcom { - pinctrl_flx0_default: flx0_twi { - atmel,pins = - ; - }; - - pinctrl_flx4_default: flx4_spi { - atmel,pins = - ; - }; - - pinctrl_flx5_default: flx_uart { - atmel,pins = - ; - }; - - pinctrl_flx6_default: flx6_twi { - atmel,pins = - ; - }; - }; - - classd { - pinctrl_classd_default: classd { - atmel,pins = - ; - }; - }; - - can0 { - pinctrl_can0_rx_tx: can0_rx_tx { - atmel,pins = - ; /* Enable CAN Transceivers */ - }; - }; - - can1 { - pinctrl_can1_rx_tx: can1_rx_tx { - atmel,pins = - ; /* Enable CAN Transceivers */ - }; - }; - - macb0 { - pinctrl_macb0_rmii: macb0_rmii-0 { - atmel,pins = - ; /* PB10 periph A */ - }; - }; - - pwm0 { - pinctrl_pwm0_0: pwm0_0 { - atmel,pins = ; - }; - - pinctrl_pwm0_1: pwm0_1 { - atmel,pins = ; - }; - - pinctrl_pwm0_2: pwm0_2 { - atmel,pins = ; - }; - - pinctrl_pwm0_3: pwm0_3 { - atmel,pins = ; - }; - }; - - sdmmc0 { - pinctrl_sdmmc0_default: sdmmc0 { - atmel,pins = - ; /* PA20 DAT3 periph A with pullup */ - }; - }; - - gpio_keys { - pinctrl_key_gpio_default: pinctrl_key_gpio { - atmel,pins = ; - }; - }; -}; /* pinctrl */ - -&pmc { - atmel,osc-bypass; -}; - -&pwm0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm0_0 &pinctrl_pwm0_1 &pinctrl_pwm0_2 &pinctrl_pwm0_3>; - status = "disabled"; /* Conflict with leds. */ -}; - -&sdmmc0 { - bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sdmmc0_default>; - status = "okay"; - cd-gpios = <&pioA 23 GPIO_ACTIVE_LOW>; - disable-wp; -}; - -&qspi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_qspi>; - status = "okay"; /* Conflict with i2s. */ - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <80000000>; - m25p,fast-read; - - at91bootstrap@0 { - label = "qspi: at91bootstrap"; - reg = <0x0 0x40000>; - }; - - bootloader@40000 { - label = "qspi: bootloader"; - reg = <0x40000 0xc0000>; - }; - - bootloaderenvred@100000 { - label = "qspi: bootloader env redundant"; - reg = <0x100000 0x40000>; - }; - - bootloaderenv@140000 { - label = "qspi: bootloader env"; - reg = <0x140000 0x40000>; - }; - - dtb@180000 { - label = "qspi: device tree"; - reg = <0x180000 0x80000>; - }; - - kernel@200000 { - label = "qspi: kernel"; - reg = <0x200000 0x600000>; - }; - }; -}; - -&shutdown_controller { - atmel,shdwc-debouncer = <976>; - status = "okay"; - - input@0 { - reg = <0>; - }; -}; - -&tcb0 { - timer0: timer@0 { - compatible = "atmel,tcb-timer"; - reg = <0>; - }; - - timer1: timer@1 { - compatible = "atmel,tcb-timer"; - reg = <1>; - }; -}; - -&usb1 { - num-ports = <3>; - atmel,vbus-gpio = <0 - &pioD 15 GPIO_ACTIVE_HIGH - &pioD 16 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&usb2 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/at91-sama5d27_som1.dtsi b/sys/gnu/dts/arm/at91-sama5d27_som1.dtsi deleted file mode 100644 index 6281590150c..00000000000 --- a/sys/gnu/dts/arm/at91-sama5d27_som1.dtsi +++ /dev/null @@ -1,99 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * at91-sama5d27_som1.dtsi - Device Tree file for SAMA5D27 SoM1 board - * - * Copyright (c) 2017, Microchip Technology Inc. - * 2017 Cristian Birsan - * 2017 Claudiu Beznea - */ -#include "sama5d2.dtsi" -#include "sama5d2-pinfunc.h" - -/ { - model = "Atmel SAMA5D27 SoM1"; - compatible = "atmel,sama5d27-som1", "atmel,sama5d27", "atmel,sama5d2", "atmel,sama5"; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <24000000>; - }; - }; - - ahb { - sdmmc0: sdio-host@a0000000 { - microchip,sdcal-inverted; - }; - - apb { - qspi1: spi@f0024000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_qspi1_default>; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <80000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - m25p,fast-read; - }; - }; - - macb0: ethernet@f8008000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_macb0_default>; - phy-mode = "rmii"; - - ethernet-phy@0 { - reg = <0x0>; - interrupt-parent = <&pioA>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_macb0_phy_irq>; - }; - }; - - pinctrl@fc038000 { - - pinctrl_qspi1_default: qspi1_default { - sck_cs { - pinmux = , - ; - bias-disable; - }; - - data { - pinmux = , - , - , - ; - bias-pull-up; - }; - }; - - pinctrl_macb0_default: macb0_default { - pinmux = , - , - , - , - , - , - , - , - , - ; - bias-disable; - }; - - pinctrl_macb0_phy_irq: macb0_phy_irq { - pinmux = ; - bias-disable; - }; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/at91-sama5d27_som1_ek.dts b/sys/gnu/dts/arm/at91-sama5d27_som1_ek.dts deleted file mode 100644 index b0853bf7901..00000000000 --- a/sys/gnu/dts/arm/at91-sama5d27_som1_ek.dts +++ /dev/null @@ -1,568 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * at91-sama5d27_som1_ek.dts - Device Tree file for SAMA5D27-SOM1-EK board - * - * Copyright (c) 2017, Microchip Technology Inc. - * 2016 Nicolas Ferre - * 2017 Cristian Birsan - * 2017 Claudiu Beznea - */ -/dts-v1/; -#include "at91-sama5d27_som1.dtsi" -#include -#include - -/ { - model = "Atmel SAMA5D27 SOM1 EK"; - compatible = "atmel,sama5d27-som1-ek", "atmel,sama5d27-som1", "atmel,sama5d27", "atmel,sama5d2", "atmel,sama5"; - - aliases { - serial0 = &uart1; /* DBGU */ - serial1 = &uart4; /* mikro BUS 1 */ - serial2 = &uart2; /* mikro BUS 2 */ - i2c1 = &i2c1; - i2c2 = &i2c2; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - ahb { - usb0: gadget@300000 { - atmel,vbus-gpio = <&pioA PIN_PD20 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usba_vbus>; - status = "okay"; - }; - - usb1: ohci@400000 { - num-ports = <3>; - atmel,vbus-gpio = <0 /* &pioA PIN_PD20 GPIO_ACTIVE_HIGH */ - &pioA PIN_PA27 GPIO_ACTIVE_HIGH - 0 - >; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_default>; - status = "okay"; - }; - - usb2: ehci@500000 { - status = "okay"; - }; - - sdmmc0: sdio-host@a0000000 { - bus-width = <8>; - mmc-ddr-3_3v; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sdmmc0_default>; - status = "okay"; - }; - - sdmmc1: sdio-host@b0000000 { - bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sdmmc1_default>; - status = "okay"; - }; - - apb { - isc: isc@f0008000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_isc_base &pinctrl_isc_data_8bit &pinctrl_isc_data_9_10 &pinctrl_isc_data_11_12>; - status = "okay"; - }; - - qspi1: spi@f0024000 { - status = "okay"; - }; - - spi0: spi@f8000000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi0_default>; - status = "okay"; - }; - - macb0: ethernet@f8008000 { - status = "okay"; - }; - - tcb0: timer@f800c000 { - timer0: timer@0 { - compatible = "atmel,tcb-timer"; - reg = <0>; - }; - - timer1: timer@1 { - compatible = "atmel,tcb-timer"; - reg = <1>; - }; - }; - - uart1: serial@f8020000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1_default>; - atmel,use-dma-rx; - atmel,use-dma-tx; - status = "okay"; - }; - - uart2: serial@f8024000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mikrobus2_uart>; - atmel,use-dma-rx; - atmel,use-dma-tx; - status = "okay"; - }; - - pwm0: pwm@f802c000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mikrobus1_pwm &pinctrl_mikrobus2_pwm>; - status = "disabled"; /* Conflict with leds. */ - }; - - flx1: flexcom@f8038000 { - atmel,flexcom-mode = ; - status = "okay"; - - i2c2: i2c@600 { - compatible = "atmel,sama5d2-i2c"; - reg = <0x600 0x200>; - interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>; - dmas = <0>, <0>; - dma-names = "tx", "rx"; - i2c-analog-filter; - i2c-digital-filter; - i2c-digital-filter-width-ns = <35>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mikrobus_i2c>; - atmel,fifo-size = <16>; - status = "okay"; - }; - }; - - shdwc@f8048010 { - atmel,shdwc-debouncer = <976>; - atmel,wakeup-rtc-timer; - - input@0 { - reg = <0>; - atmel,wakeup-type = "low"; - }; - }; - - watchdog@f8048040 { - status = "okay"; - }; - - uart3: serial@fc008000 { - atmel,use-dma-rx; - atmel,use-dma-tx; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3_default>; - status = "disabled"; /* Conflict with isc. */ - }; - - uart4: serial@fc00c000 { - atmel,use-dma-rx; - atmel,use-dma-tx; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mikrobus1_uart>; - status = "okay"; - }; - - flx3: flexcom@fc014000 { - atmel,flexcom-mode = ; - status = "disabled"; - - uart7: serial@200 { - compatible = "atmel,at91sam9260-usart"; - reg = <0x200 0x200>; - interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; - clock-names = "usart"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flx3_default>; - atmel,fifo-size = <32>; - status = "disabled"; /* Conflict with isc. */ - }; - - spi2: spi@400 { - compatible = "atmel,at91rm9200-spi"; - reg = <0x400 0x200>; - interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; - clock-names = "spi_clk"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flx3_default>; - atmel,fifo-size = <16>; - status = "disabled"; /* Conflict with isc. */ - }; - }; - - flx4: flexcom@fc018000 { - atmel,flexcom-mode = ; - status = "okay"; - - uart6: serial@200 { - compatible = "atmel,at91sam9260-usart"; - reg = <0x200 0x200>; - interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; - clock-names = "usart"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flx4_default>; - atmel,fifo-size = <32>; - status = "disabled"; /* Conflict with spi3 and i2c3. */ - }; - - spi3: spi@400 { - compatible = "atmel,at91rm9200-spi"; - reg = <0x400 0x200>; - interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; - clock-names = "spi_clk"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mikrobus_spi &pinctrl_mikrobus1_spi_cs &pinctrl_mikrobus2_spi_cs>; - atmel,fifo-size = <16>; - status = "okay"; /* Conflict with uart6 and i2c3. */ - }; - - i2c3: i2c@600 { - compatible = "atmel,sama5d2-i2c"; - reg = <0x600 0x200>; - interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; - dmas = <0>, <0>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flx4_default>; - atmel,fifo-size = <16>; - status = "disabled"; /* Conflict with uart6 and spi3. */ - }; - }; - - i2c1: i2c@fc028000 { - dmas = <0>, <0>; - i2c-analog-filter; - i2c-digital-filter; - i2c-digital-filter-width-ns = <35>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1_default>; - status = "okay"; - }; - - adc: adc@fc030000 { - vddana-supply = <&vddana>; - vref-supply = <&advref>; - - status = "disabled"; - }; - - pinctrl@fc038000 { - - pinctrl_can1_default: can1_default { - pinmux = , - ; - bias-disable; - }; - - pinctrl_flx3_default: flx3_default { - pinmux = , - , - , - , - ; - bias-disable; - }; - - pinctrl_i2c1_default: i2c1_default { - pinmux = , - ; - bias-disable; - }; - - pinctrl_isc_base: isc_base { - pinmux = , - , - , - ; - bias-disable; - }; - - pinctrl_isc_data_8bit: isc_data_8bit { - pinmux = , - , - , - , - , - , - , - ; - bias-disable; - }; - - pinctrl_isc_data_9_10: isc_data_9_10 { - pinmux = , - ; - bias-disable; - }; - - pinctrl_isc_data_11_12: isc_data_11_12 { - pinmux = , - ; - bias-disable; - }; - - pinctrl_key_gpio_default: key_gpio_default { - pinmux = ; - bias-pull-up; - }; - - pinctrl_led_gpio_default: led_gpio_default { - pinmux = , - , - ; - bias-pull-up; - }; - - pinctrl_sdmmc0_default: sdmmc0_default { - cmd_data { - pinmux = , - , - , - , - , - , - , - , - ; - bias-disable; - }; - - ck_cd_vddsel { - pinmux = , - , - ; - bias-disable; - }; - }; - - pinctrl_sdmmc1_default: sdmmc1_default { - cmd_data { - pinmux = , - , - , - , - ; - bias-disable; - }; - - conf-ck_cd { - pinmux = , - ; - bias-disable; - }; - }; - - pinctrl_spi0_default: spi0_default { - pinmux = , - , - , - ; - bias-disable; - }; - - pinctrl_uart1_default: uart1_default { - pinmux = , - ; - bias-disable; - }; - - pinctrl_uart3_default: uart3_default { - pinmux = , - ; - bias-disable; - }; - - pinctrl_usb_default: usb_default { - pinmux = , - ; - bias-disable; - }; - - pinctrl_usba_vbus: usba_vbus { - pinmux = ; - bias-disable; - }; - - pinctrl_mikrobus1_an: mikrobus1_an { - pinmux = ; - bias-disable; - }; - - pinctrl_mikrobus2_an: mikrobus2_an { - pinmux = ; - bias-disable; - }; - - pinctrl_mikrobus1_rst: mikrobus1_rst { - pinmux = ; - bias-disable; - }; - - pinctrl_mikrobus2_rst: mikrobus2_rst { - pinmux = ; - bias-disable; - }; - - pinctrl_mikrobus1_spi_cs: mikrobus1_spi_cs { - pinmux = ; - bias-disable; - }; - - pinctrl_mikrobus2_spi_cs: mikrobus2_spi_cs { - pinmux = ; - bias-disable; - }; - - pinctrl_mikrobus_spi: mikrobus_spi { - pinmux = , - , - ; - bias-disable; - }; - - pinctrl_mikrobus1_pwm: mikrobus1_pwm { - pinmux = ; - bias-disable; - }; - - pinctrl_mikrobus2_pwm: mikrobus2_pwm { - pinmux = ; - bias-disable; - }; - - pinctrl_mikrobus1_int: mikrobus1_int { - pinmux = ; - bias-disable; - }; - - pinctrl_mikrobus2_int: mikrobus2_int { - pinmux = ; - bias-disable; - }; - - pinctrl_mikrobus1_uart: mikrobus1_uart { - pinmux = , - ; - bias-disable; - }; - - pinctrl_mikrobus2_uart: mikrobus2_uart { - pinmux = , - ; - bias-disable; - }; - - pinctrl_mikrobus_i2c: mikrobus1_i2c { - pinmux = , - ; - bias-disable; - }; - - pinctrl_flx4_default: flx4_uart_default { - pinmux = , - , - , - , - ; - bias-disable; - }; - }; - - can1: can@fc050000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can1_default>; - status = "okay"; - }; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_key_gpio_default>; - - pb4 { - label = "USER"; - gpios = <&pioA PIN_PA29 GPIO_ACTIVE_LOW>; - linux,code = <0x104>; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_led_gpio_default>; - status = "okay"; /* Conflict with pwm0. */ - - red { - label = "red"; - gpios = <&pioA PIN_PA10 GPIO_ACTIVE_HIGH>; - }; - - green { - label = "green"; - gpios = <&pioA PIN_PB1 GPIO_ACTIVE_HIGH>; - }; - - blue { - label = "blue"; - gpios = <&pioA PIN_PA31 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - vddin_3v3: fixed-regulator-vddin_3v3 { - compatible = "regulator-fixed"; - - regulator-name = "VDDIN_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - status = "okay"; - }; - - vddana: fixed-regulator-vddana { - compatible = "regulator-fixed"; - - regulator-name = "VDDANA"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vddin_3v3>; - status = "okay"; - }; - - advref: fixed-regulator-advref { - compatible = "regulator-fixed"; - - regulator-name = "advref"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vddana>; - status = "okay"; - }; -}; diff --git a/sys/gnu/dts/arm/at91-sama5d27_wlsom1.dtsi b/sys/gnu/dts/arm/at91-sama5d27_wlsom1.dtsi deleted file mode 100644 index db3e2239eee..00000000000 --- a/sys/gnu/dts/arm/at91-sama5d27_wlsom1.dtsi +++ /dev/null @@ -1,304 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * at91-sama5d27_wlsom1.dtsi - Device Tree file for SAMA5D27 WLSOM1 - * - * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries - * - * Author: Nicolas Ferre - * Author: Eugen Hristev - */ -#include "sama5d2.dtsi" -#include "sama5d2-pinfunc.h" -#include -#include -#include - -/ { - model = "Microchip SAMA5D27 WLSOM1"; - compatible = "microchip,sama5d27-wlsom1", "atmel,sama5d27", "atmel,sama5d2", "atmel,sama5"; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <24000000>; - }; - }; -}; - -&flx1 { - atmel,flexcom-mode = ; - - uart6: serial@200 { - compatible = "atmel,at91sam9260-usart"; - reg = <0x200 0x200>; - interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(13))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(14))>; - dma-names = "tx", "rx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; - clock-names = "usart"; - pinctrl-0 = <&pinctrl_flx1_default>; - pinctrl-names = "default"; - }; -}; - -&i2c0 { - pinctrl-0 = <&pinctrl_i2c0_default>; - pinctrl-names = "default"; - status = "okay"; -}; - -&i2c1 { - dmas = <0>, <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1_default>; - status = "okay"; - - mcp16502@5b { - compatible = "microchip,mcp16502"; - reg = <0x5b>; - status = "okay"; - lpm-gpios = <&pioBU 0 GPIO_ACTIVE_LOW>; - - regulators { - vdd_3v3: VDD_IO { - regulator-name = "VDD_IO"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3700000>; - regulator-initial-mode = <2>; - regulator-allowed-modes = <2>, <4>; - regulator-always-on; - - regulator-state-standby { - regulator-on-in-suspend; - regulator-mode = <4>; - }; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-mode = <4>; - }; - }; - - vddio_ddr: VDD_DDR { - regulator-name = "VDD_DDR"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1850000>; - regulator-initial-mode = <2>; - regulator-allowed-modes = <2>, <4>; - regulator-always-on; - - regulator-state-standby { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1200000>; - regulator-changeable-in-suspend; - regulator-mode = <4>; - }; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1200000>; - regulator-changeable-in-suspend; - regulator-mode = <4>; - }; - }; - - vdd_core: VDD_CORE { - regulator-name = "VDD_CORE"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1850000>; - regulator-initial-mode = <2>; - regulator-allowed-modes = <2>, <4>; - regulator-always-on; - - regulator-state-standby { - regulator-on-in-suspend; - regulator-mode = <4>; - }; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-mode = <4>; - }; - }; - - vdd_ddr: VDD_OTHER { - regulator-name = "VDD_OTHER"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = <2>; - regulator-allowed-modes = <2>, <4>; - regulator-always-on; - - regulator-state-standby { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - regulator-changeable-in-suspend; - regulator-mode = <4>; - }; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - regulator-changeable-in-suspend; - regulator-mode = <4>; - }; - }; - - LDO1 { - regulator-name = "LDO1"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3700000>; - regulator-always-on; - - regulator-state-standby { - regulator-on-in-suspend; - }; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - LDO2 { - regulator-name = "LDO2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3700000>; - regulator-always-on; - - regulator-state-standby { - regulator-on-in-suspend; - }; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; -}; - -&macb0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_macb0_default>; - phy-mode = "rmii"; - - ethernet-phy@0 { - reg = <0x0>; - interrupt-parent = <&pioA>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_macb0_phy_irq>; - }; -}; - -&pmc { - atmel,osc-bypass; -}; - -&qspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_qspi1_default>; - status = "disabled"; - - qspi1_flash: spi_flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <80000000>; - spi-rx-bus-width = <4>; - spi-tx-bus-width = <4>; - m25p,fast-read; - status = "disabled"; - - at91bootstrap@0 { - label = "at91bootstrap"; - reg = <0x0 0x40000>; - }; - - bootloader@40000 { - label = "bootloader"; - reg = <0x40000 0xc0000>; - }; - - bootloaderenvred@100000 { - label = "bootloader env redundant"; - reg = <0x100000 0x40000>; - }; - - bootloaderenv@140000 { - label = "bootloader env"; - reg = <0x140000 0x40000>; - }; - - dtb@180000 { - label = "device tree"; - reg = <0x180000 0x80000>; - }; - - kernel@200000 { - label = "kernel"; - reg = <0x200000 0x600000>; - }; - }; -}; - -&pioA { - pinctrl_flx1_default: flx1_usart_default { - pinmux = , - , - , - ; - bias-disable; - }; - - pinctrl_i2c0_default: i2c0_default { - pinmux = , - ; - bias-disable; - }; - - pinctrl_i2c1_default: i2c1_default { - pinmux = , - ; - bias-disable; - }; - - pinctrl_macb0_default: macb0_default { - pinmux = , - , - , - , - , - , - , - , - , - ; - bias-disable; - }; - - pinctrl_macb0_phy_irq: macb0_phy_irq { - pinmux = ; - bias-disable; - }; - - pinctrl_qspi1_default: qspi1_default { - pinmux = , - , - , - , - , - ; - bias-pull-up; - }; -}; - diff --git a/sys/gnu/dts/arm/at91-sama5d27_wlsom1_ek.dts b/sys/gnu/dts/arm/at91-sama5d27_wlsom1_ek.dts deleted file mode 100644 index 0b9fa2942df..00000000000 --- a/sys/gnu/dts/arm/at91-sama5d27_wlsom1_ek.dts +++ /dev/null @@ -1,270 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * at91-sama5d27_wlsom1_ek.dts - Device Tree file for SAMA5D27 WLSOM1 EK - * - * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries - * - * Author: Nicolas Ferre - */ -/dts-v1/; -#include "at91-sama5d27_wlsom1.dtsi" - -/ { - model = "Microchip SAMA5D27 WLSOM1 EK"; - compatible = "microchip,sama5d27-wlsom1-ek", "microchip,sama5d27-wlsom1", "atmel,sama5d27", "atmel,sama5d2", "atmel,sama5"; - - aliases { - serial0 = &uart0; /* DBGU */ - serial1 = &uart6; /* BT */ - serial2 = &uart5; /* mikro BUS 2 */ - serial3 = &uart3; /* mikro BUS 1 */ - i2c1 = &i2c1; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - gpio_keys { - compatible = "gpio-keys"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_key_gpio_default>; - status = "okay"; - - sw4 { - label = "USER BUTTON"; - gpios = <&pioA PIN_PB2 GPIO_ACTIVE_LOW>; - linux,code = <0x104>; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_led_gpio_default>; - status = "okay"; - - red { - label = "red"; - gpios = <&pioA PIN_PA6 GPIO_ACTIVE_HIGH>; - }; - - green { - label = "green"; - gpios = <&pioA PIN_PA7 GPIO_ACTIVE_HIGH>; - }; - - blue { - label = "blue"; - gpios = <&pioA PIN_PA8 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; -}; - -&adc { - vddana-supply = <&vdd_3v3>; - vref-supply = <&vdd_3v3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_adc_default>; - status = "okay"; -}; - -&flx0 { - atmel,flexcom-mode = ; - status = "okay"; - - uart5: serial@200 { - compatible = "atmel,at91sam9260-usart"; - reg = <0x200 0x200>; - interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(11))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(12))>; - dma-names = "tx", "rx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; - clock-names = "usart"; - pinctrl-0 = <&pinctrl_flx0_default>; - pinctrl-names = "default"; - atmel,use-dma-rx; - atmel,use-dma-tx; - status = "okay"; - }; -}; - -&flx1 { - status = "okay"; - - uart6: serial@200 { - atmel,use-dma-rx; - atmel,use-dma-tx; - status = "okay"; - }; -}; - -&macb0 { - status = "okay"; -}; - -&pioA { - /* - * There is no real pinmux for ADC, if the pin - * is not requested by another peripheral then - * the muxing is done when channel is enabled. - * Requesting pins for ADC is GPIO is - * encouraged to prevent conflicts and to - * disable bias in order to be in the same - * state when the pin is not muxed to the adc. - */ - pinctrl_adc_default: adc_default { - pinmux = , - ; - bias-disable; - }; - - pinctrl_flx0_default: flx0_usart_default { - pinmux = , - ; - bias-disable; - }; - - pinctrl_key_gpio_default: key_gpio_default { - pinmux = ; - bias-pull-up; - }; - - pinctrl_led_gpio_default: led_gpio_default { - pinmux = , - , - ; - bias-pull-down; - }; - - pinctrl_sdmmc0_default: sdmmc0_default { - cmd_data { - pinmux = , - , - , - , - ; - bias-disable; - }; - - ck_cd_vddsel { - pinmux = , - , - , - ; - bias-disable; - }; - }; - - pinctrl_uart0_default: uart0_default { - pinmux = , - ; - bias-disable; - }; - - pinctrl_uart3_default: uart3_default { - pinmux = , - ; - bias-disable; - }; - - pinctrl_pwm0_default: pwm0_default { - pinmux = , - ; - bias-disable; - }; - - pinctrl_usb_default: usb_default { - pinmux = ; - bias-disable; - }; -}; - -&pwm0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm0_default>; - status = "okay"; -}; - -&qspi1 { - status = "okay"; - - qspi1_flash: spi_flash@0 { - status = "okay"; - }; -}; - -&sdmmc0 { - bus-width = <4>; - mmc-ddr-3_3v; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sdmmc0_default>; - status = "okay"; -}; - -&shutdown_controller { - atmel,shdwc-debouncer = <976>; - atmel,wakeup-rtc-timer; - - input@0 { - reg = <0>; - atmel,wakeup-type = "low"; - }; -}; - -&tcb0 { - timer0: timer@0 { - compatible = "atmel,tcb-timer"; - reg = <0>; - }; - - timer1: timer@1 { - compatible = "atmel,tcb-timer"; - reg = <1>; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0_default>; - atmel,use-dma-rx; - atmel,use-dma-tx; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3_default>; - atmel,use-dma-rx; - atmel,use-dma-tx; - status = "okay"; -}; - -&usb1 { - num-ports = <3>; - atmel,vbus-gpio = <0 - &pioA PIN_PA10 GPIO_ACTIVE_HIGH - 0 - >; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_default>; - status = "okay"; -}; - -&usb2 { - phy_type = "hsic"; - status = "okay"; -}; - -&watchdog { - status = "okay"; -}; - diff --git a/sys/gnu/dts/arm/at91-sama5d2_ptc_ek.dts b/sys/gnu/dts/arm/at91-sama5d2_ptc_ek.dts deleted file mode 100644 index ba7f3e646c2..00000000000 --- a/sys/gnu/dts/arm/at91-sama5d2_ptc_ek.dts +++ /dev/null @@ -1,415 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR X11) -/* - * at91-sama5d2_ptc_ek.dts - Device Tree file for SAMA5D2 PTC EK board - * - * Copyright (C) 2017 Microchip/Atmel, - * 2017 Wenyou Yang - * 2017 Ludovic Desroches - */ -/dts-v1/; -#include "sama5d2.dtsi" -#include "sama5d2-pinfunc.h" -#include -#include -#include - -/ { - model = "Atmel SAMA5D2 PTC EK"; - compatible = "atmel,sama5d2-ptc_ek", "atmel,sama5d2", "atmel,sama5"; - - aliases { - serial0 = &uart0; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <24000000>; - }; - }; - - ahb { - usb0: gadget@300000 { - atmel,vbus-gpio = <&pioA PIN_PA27 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usba_vbus>; - status = "okay"; - }; - - usb1: ohci@400000 { - num-ports = <3>; - atmel,vbus-gpio = <0 - &pioA PIN_PB12 GPIO_ACTIVE_HIGH - 0 - >; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_default>; - status = "okay"; - }; - - usb2: ehci@500000 { - status = "okay"; - }; - - ebi: ebi@10000000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nand_default>; - status = "okay"; /* conflicts with sdmmc1 and qspi0 */ - - nand_controller: nand-controller { - status = "okay"; - - nand@3 { - reg = <0x3 0x0 0x2>; - atmel,rb = <0>; - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - nand-on-flash-bbt; - label = "atmel_nand"; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - at91bootstrap@0 { - label = "bootstrap"; - reg = <0x0 0x40000>; - }; - - bootloader@40000 { - label = "bootloader"; - reg = <0x40000 0xc0000>; - }; - - bootloaderenvred@0x100000 { - label = "bootloader env redundant"; - reg = <0x100000 0x40000>; - }; - - bootloaderenv@0x140000 { - label = "bootloader env"; - reg = <0x140000 0x40000>; - }; - - dtb@180000 { - label = "device tree"; - reg = <0x180000 0x80000>; - }; - - kernel@200000 { - label = "kernel"; - reg = <0x200000 0x600000>; - }; - - rootfs@800000 { - label = "rootfs"; - reg = <0x800000 0x1f800000>; - }; - }; - }; - }; - }; - - sdmmc0: sdio-host@a0000000 { - bus-width = <8>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sdmmc0_default>; - non-removable; - mmc-ddr-1_8v; - status = "okay"; - }; - - apb { - spi0: spi@f8000000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi0_default>; - status = "okay"; - }; - - macb0: ethernet@f8008000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_macb0_default &pinctrl_macb0_phy_irq>; - phy-mode = "rmii"; - status = "okay"; - - ethernet-phy@1 { - reg = <0x1>; - interrupt-parent = <&pioA>; - interrupts = <56 IRQ_TYPE_LEVEL_LOW>; - }; - }; - - tcb0: timer@f800c000 { - timer0: timer@0 { - compatible = "atmel,tcb-timer"; - reg = <0>; - }; - - timer1: timer@1 { - compatible = "atmel,tcb-timer"; - reg = <1>; - }; - }; - - uart0: serial@f801c000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0_default>; - atmel,use-dma-rx; - atmel,use-dma-tx; - status = "okay"; - }; - - uart2: serial@f8024000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2_default>; - atmel,use-dma-rx; - atmel,use-dma-tx; - status = "okay"; - }; - - i2c0: i2c@f8028000 { - dmas = <0>, <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0_default>; - status = "okay"; - }; - - flx0: flexcom@f8034000 { - atmel,flexcom-mode = ; - status = "okay"; - - i2c2: i2c@600 { - compatible = "atmel,sama5d2-i2c"; - reg = <0x600 0x200>; - interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; - dmas = <0>, <0>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flx0_default>; - atmel,fifo-size = <16>; - status = "okay"; - }; - }; - - shdwc@f8048010 { - atmel,shdwc-debouncer = <976>; - - input@0 { - reg = <0>; - atmel,wakeup-type = "low"; - }; - }; - - watchdog@f8048040 { - status = "okay"; - }; - - spi1: spi@fc000000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1_default>; - status = "okay"; - }; - - i2c1: i2c@fc028000 { - dmas = <0>, <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1_default>; - status = "okay"; - - at24@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - pagesize = <8>; - }; - }; - - pinctrl@fc038000 { - pinctrl_flx0_default: flx0_default { - pinmux = , - ; - bias-disable; - }; - - pinctrl_i2c0_default: i2c0_default { - pinmux = , - ; - bias-disable; - }; - - pinctrl_i2c1_default: i2c1_default { - pinmux = , - ; - bias-disable; - }; - - pinctrl_key_gpio_default: key_gpio_default { - pinmux = ; - bias-pull-up; - }; - - pinctrl_led_gpio_default: led_gpio_default { - pinmux = , - , - ; - bias-pull-up; - }; - - pinctrl_macb0_default: macb0_default { - pinmux = , - , - , - , - , - , - , - , - , - ; - bias-disable; - }; - - pinctrl_macb0_phy_irq: macb0_phy_irq { - pinmux = ; - bias-disable; - }; - - pinctrl_nand_default: nand_default { - re_we_data { - pinmux = , - , - , - , - , - , - , - , - , - ; - bias-pull-up; - atmel,drive-strength = ; - }; - - ale_cle_rdy_cs { - pinmux = , - , - , - ; - bias-pull-up; - }; - }; - - pinctrl_sdmmc0_default: sdmmc0_default { - cmd_data { - pinmux = , - , - , - , - , - , - , - , - ; - bias-pull-up; - }; - - ck_cd_vddsel { - pinmux = , - , - ; - bias-disable; - }; - }; - - pinctrl_spi0_default: spi0_default { - pinmux = , - , - , - ; - bias-disable; - }; - - pinctrl_spi1_default: spi1_default { - pinmux = , - , - , - ; - bias-disable; - }; - - pinctrl_uart0_default: uart0_default { - pinmux = , - ; - bias-disable; - }; - - pinctrl_uart2_default: uart2_default { - pinmux = , - ; - bias-disable; - }; - - pinctrl_usb_default: usb_default { - pinmux = ; - bias-disable; - }; - - pinctrl_usba_vbus: usba_vbus { - pinmux = ; - bias-disable; - }; - - }; - - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_key_gpio_default>; - - bp1 { - label = "PB_USER"; - gpios = <&pioA PIN_PA10 GPIO_ACTIVE_LOW>; - linux,code = <0x104>; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_led_gpio_default>; - status = "okay"; - - red { - label = "red"; - gpios = <&pioA PIN_PB10 GPIO_ACTIVE_HIGH>; - }; - - green { - label = "green"; - gpios = <&pioA PIN_PB8 GPIO_ACTIVE_HIGH>; - }; - - blue { - label = "blue"; - gpios = <&pioA PIN_PB6 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; -}; diff --git a/sys/gnu/dts/arm/at91-sama5d2_xplained.dts b/sys/gnu/dts/arm/at91-sama5d2_xplained.dts deleted file mode 100644 index 9d0a7fbea72..00000000000 --- a/sys/gnu/dts/arm/at91-sama5d2_xplained.dts +++ /dev/null @@ -1,647 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * at91-sama5d2_xplained.dts - Device Tree file for SAMA5D2 Xplained board - * - * Copyright (C) 2015 Atmel, - * 2015 Nicolas Ferre - */ -/dts-v1/; -#include "sama5d2.dtsi" -#include "sama5d2-pinfunc.h" -#include -#include -#include - -/ { - model = "Atmel SAMA5D2 Xplained"; - compatible = "atmel,sama5d2-xplained", "atmel,sama5d2", "atmel,sama5"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <12000000>; - }; - }; - - ahb { - usb0: gadget@300000 { - atmel,vbus-gpio = <&pioA PIN_PA31 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usba_vbus>; - status = "okay"; - }; - - usb1: ohci@400000 { - num-ports = <3>; - atmel,vbus-gpio = <0 /* &pioA PIN_PB9 GPIO_ACTIVE_HIGH */ - &pioA PIN_PB10 GPIO_ACTIVE_HIGH - 0 - >; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_default>; - status = "okay"; - }; - - usb2: ehci@500000 { - status = "okay"; - }; - - sdmmc0: sdio-host@a0000000 { - bus-width = <8>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sdmmc0_default>; - non-removable; - mmc-ddr-1_8v; - status = "okay"; - }; - - sdmmc1: sdio-host@b0000000 { - bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sdmmc1_default>; - status = "okay"; /* conflict with qspi0 */ - vqmmc-supply = <&vdd_3v3_reg>; - vmmc-supply = <&vdd_3v3_reg>; - }; - - apb { - spi0: spi@f8000000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi0_default>; - status = "okay"; - - m25p80@0 { - compatible = "atmel,at25df321a"; - reg = <0>; - spi-max-frequency = <50000000>; - }; - }; - - macb0: ethernet@f8008000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_macb0_default &pinctrl_macb0_phy_irq>; - phy-mode = "rmii"; - status = "okay"; - - ethernet-phy@1 { - reg = <0x1>; - interrupt-parent = <&pioA>; - interrupts = ; - }; - }; - - tcb0: timer@f800c000 { - timer0: timer@0 { - compatible = "atmel,tcb-timer"; - reg = <0>; - }; - - timer1: timer@1 { - compatible = "atmel,tcb-timer"; - reg = <1>; - }; - }; - - pdmic@f8018000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pdmic_default>; - atmel,model = "PDMIC @ sama5d2_xplained"; - atmel,mic-min-freq = <1000000>; - atmel,mic-max-freq = <3246000>; - atmel,mic-offset = <0x0>; - status = "okay"; - }; - - uart1: serial@f8020000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1_default>; - atmel,use-dma-rx; - atmel,use-dma-tx; - status = "okay"; - }; - - i2c0: i2c@f8028000 { - dmas = <0>, <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0_default>; - i2c-sda-hold-time-ns = <350>; - status = "okay"; - - pmic@5b { - compatible = "active-semi,act8945a"; - reg = <0x5b>; - active-semi,vsel-high; - status = "okay"; - - regulators { - vdd_1v35_reg: REG_DCDC1 { - regulator-name = "VDD_1V35"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-allowed-modes = , - ; - regulator-initial-mode = ; - regulator-always-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-min-microvolt=<1400000>; - regulator-suspend-max-microvolt=<1400000>; - regulator-changeable-in-suspend; - regulator-mode=; - }; - }; - - vdd_1v2_reg: REG_DCDC2 { - regulator-name = "VDD_1V2"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1300000>; - regulator-allowed-modes = , - ; - regulator-initial-mode = ; - regulator-always-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_3v3_reg: REG_DCDC3 { - regulator-name = "VDD_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-allowed-modes = , - ; - regulator-initial-mode = ; - regulator-always-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_fuse_reg: REG_LDO1 { - regulator-name = "VDD_FUSE"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-allowed-modes = , - ; - regulator-initial-mode = ; - regulator-always-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_3v3_lp_reg: REG_LDO2 { - regulator-name = "VDD_3V3_LP"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-allowed-modes = , - ; - regulator-initial-mode = ; - regulator-always-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_led_reg: REG_LDO3 { - regulator-name = "VDD_LED"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-allowed-modes = , - ; - regulator-initial-mode = ; - regulator-always-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_sdhc_1v8_reg: REG_LDO4 { - regulator-name = "VDD_SDHC_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-allowed-modes = , - ; - regulator-initial-mode = ; - regulator-always-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - - charger { - compatible = "active-semi,act8945a-charger"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_charger_chglev &pinctrl_charger_lbo &pinctrl_charger_irq>; - interrupt-parent = <&pioA>; - interrupts = ; - - active-semi,chglev-gpios = <&pioA PIN_PA12 GPIO_ACTIVE_HIGH>; - active-semi,lbo-gpios = <&pioA PIN_PC8 GPIO_ACTIVE_LOW>; - active-semi,input-voltage-threshold-microvolt = <6600>; - active-semi,precondition-timeout = <40>; - active-semi,total-timeout = <3>; - status = "okay"; - }; - }; - }; - - pwm0: pwm@f802c000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm0_pwm2_default>; - status = "disabled"; /* conflict with leds */ - }; - - flx0: flexcom@f8034000 { - atmel,flexcom-mode = ; - status = "disabled"; /* conflict with ISC_D2 & ISC_D3 data pins */ - - uart5: serial@200 { - compatible = "atmel,at91sam9260-usart"; - reg = <0x200 0x200>; - interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; - clock-names = "usart"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flx0_default>; - atmel,fifo-size = <32>; - status = "okay"; - }; - }; - - shdwc@f8048010 { - atmel,shdwc-debouncer = <976>; - atmel,wakeup-rtc-timer; - - input@0 { - reg = <0>; - atmel,wakeup-type = "low"; - }; - }; - - watchdog@f8048040 { - status = "okay"; - }; - - i2s0: i2s@f8050000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2s0_default>; - status = "disabled"; /* conflict with can0 */ - }; - - can0: can@f8054000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can0_default>; - status = "okay"; - }; - - uart3: serial@fc008000 { - atmel,use-dma-rx; - atmel,use-dma-tx; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3_default>; - status = "okay"; - }; - - flx4: flexcom@fc018000 { - atmel,flexcom-mode = ; - status = "okay"; - - i2c2: i2c@600 { - compatible = "atmel,sama5d2-i2c"; - reg = <0x600 0x200>; - interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; - dmas = <0>, <0>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flx4_default>; - atmel,fifo-size = <16>; - i2c-analog-filter; - i2c-digital-filter; - i2c-digital-filter-width-ns = <35>; - status = "okay"; - }; - }; - - i2c1: i2c@fc028000 { - dmas = <0>, <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1_default>; - i2c-analog-filter; - i2c-digital-filter; - i2c-digital-filter-width-ns = <35>; - status = "okay"; - - at24@54 { - compatible = "atmel,24c02"; - reg = <0x54>; - pagesize = <16>; - }; - }; - - adc: adc@fc030000 { - vddana-supply = <&vdd_3v3_lp_reg>; - vref-supply = <&vdd_3v3_lp_reg>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_adc_default &pinctrl_adtrg_default>; - status = "okay"; - }; - - pinctrl@fc038000 { - /* - * There is no real pinmux for ADC, if the pin - * is not requested by another peripheral then - * the muxing is done when channel is enabled. - * Requesting pins for ADC is GPIO is - * encouraged to prevent conflicts and to - * disable bias in order to be in the same - * state when the pin is not muxed to the adc. - */ - pinctrl_adc_default: adc_default { - pinmux = ; - bias-disable; - }; - - pinctrl_can0_default: can0_default { - pinmux = , - ; - bias-disable; - }; - - pinctrl_can1_default: can1_default { - pinmux = , - ; - bias-disable; - }; - - /* - * The ADTRG pin can work on any edge type. - * In here it's being pulled up, so need to - * connect it to ground to get an edge e.g. - * Trigger can be configured on falling, rise - * or any edge, and the pull-up can be changed - * to pull-down or left floating according to - * needs. - */ - pinctrl_adtrg_default: adtrg_default { - pinmux = ; - bias-pull-up; - }; - - pinctrl_charger_chglev: charger_chglev { - pinmux = ; - bias-disable; - }; - - pinctrl_charger_irq: charger_irq { - pinmux = ; - bias-disable; - }; - - pinctrl_charger_lbo: charger_lbo { - pinmux = ; - bias-pull-up; - }; - - pinctrl_classd_default: classd_default { - pinmux = , - , - , - ; - bias-pull-up; - }; - - pinctrl_flx0_default: flx0_default { - pinmux = , - ; - bias-disable; - }; - - pinctrl_flx4_default: flx4_default { - pinmux = , - ; - bias-disable; - }; - - pinctrl_i2c0_default: i2c0_default { - pinmux = , - ; - bias-disable; - }; - - pinctrl_i2c1_default: i2c1_default { - pinmux = , - ; - bias-disable; - }; - - pinctrl_i2s0_default: i2s0_default { - pinmux = , - , - , - , - ; - bias-disable; - }; - - pinctrl_i2s1_default: i2s1_default { - pinmux = , - , - , - , - ; - bias-disable; - }; - - pinctrl_key_gpio_default: key_gpio_default { - pinmux = ; - bias-pull-up; - }; - - pinctrl_led_gpio_default: led_gpio_default { - pinmux = , - , - ; - bias-pull-up; - }; - - pinctrl_macb0_default: macb0_default { - pinmux = , - , - , - , - , - , - , - , - , - ; - bias-disable; - }; - - pinctrl_macb0_phy_irq: macb0_phy_irq { - pinmux = ; - bias-disable; - }; - - pinctrl_pdmic_default: pdmic_default { - pinmux = , - ; - bias-disable; - }; - - pinctrl_sdmmc0_default: sdmmc0_default { - cmd_data { - pinmux = , - , - , - , - , - , - , - , - ; - bias-disable; - }; - - ck_cd_rstn_vddsel { - pinmux = , - , - , - ; - bias-disable; - }; - }; - - pinctrl_sdmmc1_default: sdmmc1_default { - cmd_data { - pinmux = , - , - , - , - ; - bias-disable; - }; - - conf-ck_cd { - pinmux = , - ; - bias-disable; - }; - }; - - pinctrl_spi0_default: spi0_default { - pinmux = , - , - , - ; - bias-disable; - }; - - pinctrl_uart1_default: uart1_default { - pinmux = , - ; - bias-disable; - }; - - pinctrl_uart3_default: uart3_default { - pinmux = , - ; - bias-disable; - }; - - pinctrl_usb_default: usb_default { - pinmux = ; - bias-disable; - }; - - pinctrl_usba_vbus: usba_vbus { - pinmux = ; - bias-disable; - }; - - pinctrl_pwm0_pwm2_default: pwm0_pwm2_default { - pinmux = , - ; - bias-pull-up; - }; - }; - - classd: classd@fc048000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_classd_default>; - atmel,pwm-type = "diff"; - atmel,non-overlap-time = <10>; - status = "okay"; - }; - - i2s1: i2s@fc04c000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2s1_default>; - status = "disabled"; /* conflict with spi0, sdmmc1 */ - }; - - can1: can@fc050000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can1_default>; - status = "okay"; - }; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_key_gpio_default>; - - bp1 { - label = "PB_USER"; - gpios = <&pioA PIN_PB9 GPIO_ACTIVE_LOW>; - linux,code = <0x104>; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_led_gpio_default>; - status = "okay"; /* conflict with pwm0 */ - - red { - label = "red"; - gpios = <&pioA PIN_PB6 GPIO_ACTIVE_LOW>; - }; - - - green { - label = "green"; - gpios = <&pioA PIN_PB5 GPIO_ACTIVE_LOW>; - }; - - blue { - label = "blue"; - gpios = <&pioA PIN_PB0 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - }; - }; -}; diff --git a/sys/gnu/dts/arm/at91-sama5d3_xplained.dts b/sys/gnu/dts/arm/at91-sama5d3_xplained.dts deleted file mode 100644 index 61f068a7b36..00000000000 --- a/sys/gnu/dts/arm/at91-sama5d3_xplained.dts +++ /dev/null @@ -1,369 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * at91-sama5d3_xplained.dts - Device Tree file for the SAMA5D3 Xplained board - * - * Copyright (C) 2014 Atmel, - * 2014 Nicolas Ferre - */ -/dts-v1/; -#include "sama5d36.dtsi" - -/ { - model = "SAMA5D3 Xplained"; - compatible = "atmel,sama5d3-xplained", "atmel,sama5d3", "atmel,sama5"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - reg = <0x20000000 0x10000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <12000000>; - }; - }; - - ahb { - apb { - mmc0: mmc@f0000000 { - pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_dat4_7 &pinctrl_mmc0_cd>; - vmmc-supply = <&vcc_mmc0_reg>; - vqmmc-supply = <&vcc_3v3_reg>; - status = "okay"; - slot@0 { - reg = <0>; - bus-width = <8>; - cd-gpios = <&pioE 0 GPIO_ACTIVE_LOW>; - }; - }; - - mmc1: mmc@f8000000 { - vmmc-supply = <&vcc_3v3_reg>; - vqmmc-supply = <&vcc_3v3_reg>; - status = "disabled"; - slot@0 { - reg = <0>; - bus-width = <4>; - cd-gpios = <&pioE 1 GPIO_ACTIVE_LOW>; - }; - }; - - spi0: spi@f0004000 { - cs-gpios = <&pioD 13 0>, <0>, <0>, <&pioD 16 0>; - status = "okay"; - }; - - can0: can@f000c000 { - status = "okay"; - }; - - tcb0: timer@f0010000 { - timer0: timer@0 { - compatible = "atmel,tcb-timer"; - reg = <0>; - }; - - timer1: timer@1 { - compatible = "atmel,tcb-timer"; - reg = <1>; - }; - }; - - i2c0: i2c@f0014000 { - pinctrl-0 = <&pinctrl_i2c0_pu>; - status = "okay"; - }; - - i2c1: i2c@f0018000 { - status = "okay"; - - pmic: act8865@5b { - compatible = "active-semi,act8865"; - reg = <0x5b>; - status = "disabled"; - - regulators { - vcc_1v8_reg: DCDC_REG1 { - regulator-name = "VCC_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vcc_1v2_reg: DCDC_REG2 { - regulator-name = "VCC_1V2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - vcc_3v3_reg: DCDC_REG3 { - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vddfuse_reg: LDO_REG1 { - regulator-name = "FUSE_2V5"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - }; - - vddana_reg: LDO_REG2 { - regulator-name = "VDDANA"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; - }; - - macb0: ethernet@f0028000 { - phy-mode = "rgmii"; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - ethernet-phy@7 { - reg = <0x7>; - }; - }; - - pwm0: pwm@f002c000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm0_pwmh0_0 &pinctrl_pwm0_pwmh1_0>; - status = "okay"; - }; - - usart0: serial@f001c000 { - status = "okay"; - }; - - usart1: serial@f0020000 { - pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts_cts>; - status = "okay"; - }; - - uart0: serial@f0024000 { - status = "okay"; - }; - - mmc1: mmc@f8000000 { - pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3 &pinctrl_mmc1_cd>; - status = "okay"; - slot@0 { - reg = <0>; - bus-width = <4>; - cd-gpios = <&pioE 1 GPIO_ACTIVE_HIGH>; - }; - }; - - spi1: spi@f8008000 { - cs-gpios = <&pioC 25 0>; - status = "okay"; - }; - - adc0: adc@f8018000 { - atmel,adc-vref = <3300>; - atmel,adc-channels-used = <0xfe>; - pinctrl-0 = < - &pinctrl_adc0_adtrg - &pinctrl_adc0_ad1 - &pinctrl_adc0_ad2 - &pinctrl_adc0_ad3 - &pinctrl_adc0_ad4 - &pinctrl_adc0_ad5 - &pinctrl_adc0_ad6 - &pinctrl_adc0_ad7 - >; - status = "okay"; - }; - - i2c2: i2c@f801c000 { - dmas = <0>, <0>; /* Do not use DMA for i2c2 */ - pinctrl-0 = <&pinctrl_i2c2_pu>; - status = "okay"; - }; - - macb1: ethernet@f802c000 { - phy-mode = "rmii"; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - ethernet-phy@1 { - reg = <0x1>; - }; - }; - - dbgu: serial@ffffee00 { - status = "okay"; - }; - - pinctrl@fffff200 { - board { - pinctrl_i2c0_pu: i2c0_pu { - atmel,pins = - , - ; - }; - - pinctrl_i2c2_pu: i2c2_pu { - atmel,pins = - , - ; - }; - - pinctrl_key_gpio: key_gpio_0 { - atmel,pins = - ; - }; - - pinctrl_mmc0_cd: mmc0_cd { - atmel,pins = - ; - }; - - pinctrl_mmc1_cd: mmc1_cd { - atmel,pins = - ; - }; - - pinctrl_usba_vbus: usba_vbus { - atmel,pins = - ; /* PE9, conflicts with A9 */ - }; - }; - }; - }; - - usb0: gadget@500000 { - atmel,vbus-gpio = <&pioE 9 GPIO_ACTIVE_HIGH>; /* PE9, conflicts with A9 */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usba_vbus>; - status = "okay"; - }; - - usb1: ohci@600000 { - num-ports = <3>; - atmel,vbus-gpio = <0 - &pioE 3 GPIO_ACTIVE_LOW - &pioE 4 GPIO_ACTIVE_LOW - >; - status = "okay"; - }; - - usb2: ehci@700000 { - status = "okay"; - }; - - ebi: ebi@10000000 { - pinctrl-0 = <&pinctrl_ebi_nand_addr>; - pinctrl-names = "default"; - status = "okay"; - - nand_controller: nand-controller { - status = "okay"; - - nand@3 { - reg = <0x3 0x0 0x2>; - atmel,rb = <0>; - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - nand-ecc-strength = <4>; - nand-ecc-step-size = <512>; - nand-on-flash-bbt; - label = "atmel_nand"; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - at91bootstrap@0 { - label = "at91bootstrap"; - reg = <0x0 0x40000>; - }; - - bootloader@40000 { - label = "bootloader"; - reg = <0x40000 0xc0000>; - }; - - bootloaderenvred@100000 { - label = "bootloader env redundant"; - reg = <0x100000 0x40000>; - }; - - bootloaderenv@140000 { - label = "bootloader env"; - reg = <0x140000 0x40000>; - }; - - dtb@180000 { - label = "device tree"; - reg = <0x180000 0x80000>; - }; - - kernel@200000 { - label = "kernel"; - reg = <0x200000 0x600000>; - }; - - rootfs@800000 { - label = "rootfs"; - reg = <0x800000 0x0f800000>; - }; - }; - }; - }; - }; - }; - - vcc_mmc0_reg: fixedregulator_mmc0 { - compatible = "regulator-fixed"; - gpio = <&pioE 2 GPIO_ACTIVE_LOW>; - regulator-name = "mmc0-card-supply"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - gpio_keys { - compatible = "gpio-keys"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_key_gpio>; - - bp3 { - label = "PB_USER"; - gpios = <&pioE 29 GPIO_ACTIVE_LOW>; - linux,code = <0x104>; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - - d2 { - label = "d2"; - gpios = <&pioE 23 GPIO_ACTIVE_LOW>; /* PE23, conflicts with A23, CTS2 */ - linux,default-trigger = "heartbeat"; - }; - - d3 { - label = "d3"; - gpios = <&pioE 24 GPIO_ACTIVE_HIGH>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/at91-sama5d4_ma5d4.dtsi b/sys/gnu/dts/arm/at91-sama5d4_ma5d4.dtsi deleted file mode 100644 index 0be184a870e..00000000000 --- a/sys/gnu/dts/arm/at91-sama5d4_ma5d4.dtsi +++ /dev/null @@ -1,136 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (C) 2015 Marek Vasut - */ - -#include "sama5d4.dtsi" - -/ { - model = "Aries/DENX MA5D4"; - compatible = "aries,ma5d4", "denx,ma5d4", "atmel,sama5d4", "atmel,sama5"; - - memory { - reg = <0x20000000 0x10000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <12000000>; - }; - - clk20m: clk20m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <20000000>; - clock-output-names = "clk20m"; - }; - }; - - ahb { - apb { - mmc0: mmc@f8000000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_dat4_7>; - vmmc-supply = <&vcc_mmc0_reg>; - vqmmc-supply = <&vcc_3v3_reg>; - status = "okay"; - slot@0 { - reg = <0>; - bus-width = <8>; - broken-cd; - }; - }; - - spi0: spi@f8010000 { - cs-gpios = <&pioC 3 0>, <0>, <0>, <0>; - status = "okay"; - - m25p80@0 { - compatible = "atmel,at25df321a"; - spi-max-frequency = <50000000>; - reg = <0>; - }; - }; - - i2c0: i2c@f8014000 { - status = "okay"; - }; - - spi1: spi@fc018000 { - cs-gpios = <&pioB 22 0>, <&pioB 23 0>, <0>, <0>; - status = "okay"; - - can0: can@0 { - compatible = "microchip,mcp2515"; - reg = <0>; - clocks = <&clk20m>; - interrupt-parent = <&pioE>; - interrupts = <6 IRQ_TYPE_EDGE_RISING>; - spi-max-frequency = <10000000>; - }; - - can1: can@1 { - compatible = "microchip,mcp2515"; - reg = <1>; - clocks = <&clk20m>; - interrupt-parent = <&pioE>; - interrupts = <7 IRQ_TYPE_EDGE_RISING>; - spi-max-frequency = <10000000>; - }; - }; - - tcb2: timer@fc024000 { - timer@0 { - compatible = "atmel,tcb-timer"; - reg = <0>; - }; - - timer@1 { - compatible = "atmel,tcb-timer"; - reg = <1>; - }; - }; - - adc0: adc@fc034000 { - pinctrl-names = "default"; - pinctrl-0 = < - /* external trigger conflicts with USBA_VBUS */ - &pinctrl_adc0_ad0 - &pinctrl_adc0_ad1 - &pinctrl_adc0_ad2 - &pinctrl_adc0_ad3 - &pinctrl_adc0_ad4 - >; - atmel,adc-vref = <3300>; - status = "okay"; - }; - - watchdog@fc068640 { - status = "okay"; - }; - }; - }; - - vcc_3v3_reg: fixedregulator_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC 3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - vcc_mmc0_reg: fixedregulator_mmc0 { - compatible = "regulator-fixed"; - gpio = <&pioE 15 GPIO_ACTIVE_HIGH>; - regulator-name = "RST_n MCI0"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_3v3_reg>; - regulator-boot-on; - }; -}; diff --git a/sys/gnu/dts/arm/at91-sama5d4_ma5d4evk.dts b/sys/gnu/dts/arm/at91-sama5d4_ma5d4evk.dts deleted file mode 100644 index af4969485c8..00000000000 --- a/sys/gnu/dts/arm/at91-sama5d4_ma5d4evk.dts +++ /dev/null @@ -1,164 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (C) 2015 Marek Vasut - */ - -/dts-v1/; -#include "at91-sama5d4_ma5d4.dtsi" - -/ { - model = "Aries/DENX MA5D4EVK"; - compatible = "aries,ma5d4evk", "denx,ma5d4evk", "atmel,sama5d4", "atmel,sama5"; - - chosen { - stdout-path = "serial3:115200n8"; - }; - - ahb { - usb0: gadget@400000 { - atmel,vbus-gpio = <&pioE 31 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usba_vbus>; - status = "okay"; - }; - - usb1: ohci@500000 { - num-ports = <3>; - atmel,vbus-gpio = <0 - &pioE 11 GPIO_ACTIVE_LOW - &pioE 14 GPIO_ACTIVE_LOW - >; - status = "okay"; - }; - - usb2: ehci@600000 { - status = "okay"; - }; - - apb { - hlcdc: hlcdc@f0000000 { - status = "okay"; - - hlcdc-display-controller { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_rgb888>; - - port@0 { - hlcdc_panel_output: endpoint@0 { - reg = <0>; - remote-endpoint = <&panel_input>; - }; - }; - }; - - }; - - macb0: ethernet@f8020000 { - phy-mode = "rmii"; - status = "okay"; - - phy0: ethernet-phy@0 { - reg = <0>; - }; - }; - - usart0: serial@f802c000 { - status = "okay"; - }; - - usart1: serial@f8030000 { - status = "okay"; - }; - - mmc1: mmc@fc000000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3 &pinctrl_mmc1_cd>; - vmmc-supply = <&vcc_mmc1_reg>; - vqmmc-supply = <&vcc_3v3_reg>; - status = "okay"; - slot@0 { - reg = <0>; - bus-width = <4>; - cd-gpios = <&pioE 5 0>; - }; - }; - - adc0: adc@fc034000 { - atmel,adc-ts-wires = <4>; - atmel,adc-ts-pressure-threshold = <10000>; - }; - - - pinctrl@fc06a000 { - board { - pinctrl_mmc1_cd: mmc1_cd { - atmel,pins = ; - }; - pinctrl_usba_vbus: usba_vbus { - atmel,pins = - ; - }; - }; - }; - }; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&hlcdc_pwm 0 50000 0>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - status = "okay"; - }; - - leds { - compatible = "gpio-leds"; - status = "okay"; - - user1 { - label = "user1"; - gpios = <&pioD 28 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - - user2 { - label = "user2"; - gpios = <&pioD 29 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - - user3 { - label = "user3"; - gpios = <&pioD 30 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - panel: panel { - /* Actually Ampire 800480R2 */ - compatible = "foxlink,fl500wvr00-a0t", "simple-panel"; - backlight = <&backlight>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - port@0 { - #address-cells = <1>; - #size-cells = <0>; - - panel_input: endpoint@0 { - reg = <0>; - remote-endpoint = <&hlcdc_panel_output>; - }; - }; - }; - - vcc_mmc1_reg: fixedregulator_mmc1 { - compatible = "regulator-fixed"; - gpio = <&pioE 17 GPIO_ACTIVE_LOW>; - regulator-name = "VDD MCI1"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_3v3_reg>; - }; -}; diff --git a/sys/gnu/dts/arm/at91-sama5d4_xplained.dts b/sys/gnu/dts/arm/at91-sama5d4_xplained.dts deleted file mode 100644 index 924d9491780..00000000000 --- a/sys/gnu/dts/arm/at91-sama5d4_xplained.dts +++ /dev/null @@ -1,281 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * at91-sama5d4_xplained.dts - Device Tree file for SAMA5D4 Xplained board - * - * Copyright (C) 2015 Atmel, - * 2015 Josh Wu - */ -/dts-v1/; -#include "sama5d4.dtsi" - -/ { - model = "Atmel SAMA5D4 Xplained"; - compatible = "atmel,sama5d4-xplained", "atmel,sama5d4", "atmel,sama5"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - reg = <0x20000000 0x20000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <12000000>; - }; - }; - - ahb { - apb { - uart0: serial@f8004000 { - atmel,use-dma-rx; - atmel,use-dma-tx; - status = "okay"; - }; - - spi0: spi@f8010000 { - cs-gpios = <&pioC 3 0>, <0>, <0>, <0>; - status = "okay"; - m25p80@0 { - compatible = "atmel,at25df321a"; - spi-max-frequency = <50000000>; - reg = <0>; - }; - }; - - i2c0: i2c@f8014000 { - i2c-digital-filter; - status = "okay"; - }; - - macb0: ethernet@f8020000 { - phy-mode = "rmii"; - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_macb0_rmii &pinctrl_macb0_phy_irq>; - - phy0: ethernet-phy@1 { - interrupt-parent = <&pioE>; - interrupts = <1 IRQ_TYPE_LEVEL_LOW>; - reg = <1>; - }; - }; - - mmc1: mmc@fc000000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3 &pinctrl_mmc1_cd>; - vmmc-supply = <&vcc_mmc1_reg>; - vqmmc-supply = <&vcc_3v3_reg>; - status = "okay"; - slot@0 { - reg = <0>; - bus-width = <4>; - cd-gpios = <&pioE 3 0>; - }; - }; - - usart3: serial@fc00c000 { - atmel,use-dma-rx; - atmel,use-dma-tx; - status = "okay"; - }; - - usart4: serial@fc010000 { - status = "okay"; - }; - - spi1: spi@fc018000 { - cs-gpios = <&pioB 21 0>; - status = "okay"; - }; - - tcb2: timer@fc024000 { - timer0: timer@0 { - compatible = "atmel,tcb-timer"; - reg = <0>; - }; - - timer1: timer@1 { - compatible = "atmel,tcb-timer"; - reg = <1>; - }; - }; - - adc0: adc@fc034000 { - pinctrl-names = "default"; - pinctrl-0 = < - /* external trigger conflicts with USBA_VBUS */ - &pinctrl_adc0_ad0 - &pinctrl_adc0_ad1 - &pinctrl_adc0_ad2 - &pinctrl_adc0_ad3 - &pinctrl_adc0_ad4 - >; - atmel,adc-vref = <3300>; - status = "okay"; - }; - - watchdog@fc068640 { - status = "okay"; - }; - - pinctrl@fc06a000 { - board { - pinctrl_mmc1_cd: mmc1_cd { - atmel,pins = - ; - }; - pinctrl_usba_vbus: usba_vbus { - atmel,pins = - ; - }; - pinctrl_key_gpio: key_gpio_0 { - atmel,pins = - ; - }; - pinctrl_macb0_phy_irq: macb0_phy_irq_0 { - atmel,pins = - ; - }; - }; - }; - }; - - usb0: gadget@400000 { - atmel,vbus-gpio = <&pioE 31 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usba_vbus>; - status = "okay"; - }; - - usb1: ohci@500000 { - num-ports = <3>; - atmel,vbus-gpio = <0 - &pioE 11 GPIO_ACTIVE_HIGH - &pioE 14 GPIO_ACTIVE_HIGH - >; - status = "okay"; - }; - - usb2: ehci@600000 { - status = "okay"; - }; - - ebi: ebi@10000000 { - pinctrl-0 = <&pinctrl_ebi_cs3 &pinctrl_ebi_nrd_nandoe - &pinctrl_ebi_nwe_nandwe &pinctrl_ebi_nandrdy - &pinctrl_ebi_data_0_7 &pinctrl_ebi_nand_addr>; - pinctrl-names = "default"; - status = "okay"; - - nand_controller: nand-controller { - status = "okay"; - - nand@3 { - reg = <0x3 0x0 0x2>; - atmel,rb = <0>; - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - nand-on-flash-bbt; - label = "atmel_nand"; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - at91bootstrap@0 { - label = "at91bootstrap"; - reg = <0x0 0x40000>; - }; - - bootloader@40000 { - label = "bootloader"; - reg = <0x40000 0xc0000>; - }; - - bootloaderenvred@100000 { - label = "bootloader env redundant"; - reg = <0x100000 0x40000>; - }; - - bootloaderenv@140000 { - label = "bootloader env"; - reg = <0x140000 0x40000>; - }; - - dtb@180000 { - label = "device tree"; - reg = <0x180000 0x80000>; - }; - - kernel@200000 { - label = "kernel"; - reg = <0x200000 0x600000>; - }; - - rootfs@800000 { - label = "rootfs"; - reg = <0x800000 0x1f800000>; - }; - }; - }; - }; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_key_gpio>; - - pb_user1 { - label = "pb_user1"; - gpios = <&pioE 8 GPIO_ACTIVE_HIGH>; - linux,code = <0x100>; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - status = "okay"; - - d8 { - label = "d8"; - gpios = <&pioD 30 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - d10 { - label = "d10"; - gpios = <&pioE 15 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - }; - }; - - vcc_3v3_reg: fixedregulator_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC 3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - vcc_mmc1_reg: fixedregulator_mmc1 { - compatible = "regulator-fixed"; - gpio = <&pioE 4 GPIO_ACTIVE_LOW>; - regulator-name = "VDD MCI1"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_3v3_reg>; - regulator-always-on; - }; -}; diff --git a/sys/gnu/dts/arm/at91-sama5d4ek.dts b/sys/gnu/dts/arm/at91-sama5d4ek.dts deleted file mode 100644 index 0cc1cff13e4..00000000000 --- a/sys/gnu/dts/arm/at91-sama5d4ek.dts +++ /dev/null @@ -1,323 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * at91-sama5d4ek.dts - Device Tree file for SAMA5D4 Evaluation Kit - * - * Copyright (C) 2014 Atmel, - * 2014 Nicolas Ferre - */ -/dts-v1/; -#include "sama5d4.dtsi" - -/ { - model = "Atmel SAMA5D4-EK"; - compatible = "atmel,sama5d4ek", "atmel,sama5d4", "atmel,sama5"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - reg = <0x20000000 0x20000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <12000000>; - }; - }; - - ahb { - apb { - adc0: adc@fc034000 { - pinctrl-names = "default"; - pinctrl-0 = < - /* external trigger conflicts with USBA_VBUS */ - &pinctrl_adc0_ad0 - &pinctrl_adc0_ad1 - &pinctrl_adc0_ad2 - &pinctrl_adc0_ad3 - &pinctrl_adc0_ad4 - >; - /* The vref depends on JP22 of EK. If connect 1-2 then use 3.3V. connect 2-3 use 3.0V */ - atmel,adc-vref = <3300>; - /*atmel,adc-ts-wires = <4>;*/ /* Set up ADC touch screen */ - status = "okay"; /* Enable ADC IIO support */ - }; - - mmc0: mmc@f8000000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_cd>; - slot@0 { - reg = <0>; - bus-width = <4>; - cd-gpios = <&pioE 5 0>; - }; - }; - - ssc0: ssc@f8008000 { - status = "okay"; - }; - - spi0: spi@f8010000 { - cs-gpios = <&pioC 3 0>, <0>, <0>, <0>; - status = "okay"; - m25p80@0 { - compatible = "atmel,at25df321a"; - spi-max-frequency = <50000000>; - reg = <0>; - }; - }; - - i2c0: i2c@f8014000 { - status = "okay"; - - wm8904: codec@1a { - compatible = "wlf,wm8904"; - reg = <0x1a>; - clocks = <&pmc PMC_TYPE_SYSTEM 10>; - clock-names = "mclk"; - }; - - qt1070:keyboard@1b { - compatible = "qt1070"; - reg = <0x1b>; - interrupt-parent = <&pioE>; - interrupts = <25 0x0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_qt1070_irq>; - wakeup-source; - }; - - touchscreen@4c { - compatible = "atmel,maxtouch"; - reg = <0x4c>; - interrupt-parent = <&pioE>; - interrupts = <24 0x0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mxt_ts>; - }; - }; - - macb0: ethernet@f8020000 { - pinctrl-0 = <&pinctrl_macb0_rmii &pinctrl_macb0_phy_irq>; - phy-mode = "rmii"; - status = "okay"; - - ethernet-phy@1 { - reg = <0x1>; - interrupt-parent = <&pioE>; - interrupts = <1 IRQ_TYPE_LEVEL_LOW>; - }; - }; - - mmc1: mmc@fc000000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3 &pinctrl_mmc1_cd>; - status = "okay"; - slot@0 { - reg = <0>; - bus-width = <4>; - cd-gpios = <&pioE 6 0>; - }; - }; - - usart2: serial@fc008000 { - status = "okay"; - }; - - usart3: serial@fc00c000 { - status = "okay"; - }; - - usart4: serial@fc010000 { - status = "okay"; - }; - - tcb2: timer@fc024000 { - timer@0 { - compatible = "atmel,tcb-timer"; - reg = <0>; - }; - - timer@1 { - compatible = "atmel,tcb-timer"; - reg = <1>; - }; - }; - - watchdog@fc068640 { - status = "okay"; - }; - - pinctrl@fc06a000 { - board { - pinctrl_macb0_phy_irq: macb0_phy_irq { - atmel,pins = - ; - }; - pinctrl_mmc0_cd: mmc0_cd { - atmel,pins = - ; - }; - pinctrl_mmc1_cd: mmc1_cd { - atmel,pins = - ; - }; - pinctrl_pck2_as_audio_mck: pck2_as_audio_mck { - atmel,pins = - ; - }; - pinctrl_usba_vbus: usba_vbus { - atmel,pins = - ; - }; - pinctrl_key_gpio: key_gpio_0 { - atmel,pins = - ; /* PE13 gpio */ - }; - pinctrl_qt1070_irq: qt1070_irq { - atmel,pins = - ; - }; - pinctrl_mxt_ts: mxt_irq { - atmel,pins = - ; - }; - }; - }; - }; - - usb0: gadget@400000 { - atmel,vbus-gpio = <&pioE 31 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usba_vbus>; - status = "okay"; - }; - - usb1: ohci@500000 { - num-ports = <3>; - atmel,vbus-gpio = <0 /* &pioE 10 GPIO_ACTIVE_LOW */ - &pioE 11 GPIO_ACTIVE_LOW - &pioE 12 GPIO_ACTIVE_LOW - >; - status = "okay"; - }; - - usb2: ehci@600000 { - status = "okay"; - }; - - ebi: ebi@10000000 { - pinctrl-0 = <&pinctrl_ebi_cs3 &pinctrl_ebi_nrd_nandoe - &pinctrl_ebi_nwe_nandwe &pinctrl_ebi_nandrdy - &pinctrl_ebi_data_0_7 &pinctrl_ebi_nand_addr>; - pinctrl-names = "default"; - status = "okay"; - - nand_controller: nand-controller { - status = "okay"; - - nand@3 { - reg = <0x3 0x0 0x2>; - atmel,rb = <0>; - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - nand-on-flash-bbt; - label = "atmel_nand"; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - at91bootstrap@0 { - label = "at91bootstrap"; - reg = <0x0 0x40000>; - }; - - bootloader@40000 { - label = "bootloader"; - reg = <0x40000 0x80000>; - }; - - bootloaderenv@c0000 { - label = "bootloader env"; - reg = <0xc0000 0xc0000>; - }; - - dtb@180000 { - label = "device tree"; - reg = <0x180000 0x80000>; - }; - - kernel@200000 { - label = "kernel"; - reg = <0x200000 0x600000>; - }; - - rootfs@800000 { - label = "rootfs"; - reg = <0x800000 0x0f800000>; - }; - }; - }; - }; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_key_gpio>; - - pb_user1 { - label = "pb_user1"; - gpios = <&pioE 13 GPIO_ACTIVE_HIGH>; - linux,code = <0x100>; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - status = "okay"; - - d8 { - label = "d8"; - /* PE28, conflicts with usart4 rts pin */ - gpios = <&pioE 28 GPIO_ACTIVE_LOW>; - }; - - d9 { - label = "d9"; - gpios = <&pioE 9 GPIO_ACTIVE_HIGH>; - }; - - d10 { - label = "d10"; - gpios = <&pioE 8 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - }; - }; - - sound { - compatible = "atmel,asoc-wm8904"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pck2_as_audio_mck>; - - atmel,model = "wm8904 @ SAMA5D4EK"; - atmel,audio-routing = - "Headphone Jack", "HPOUTL", - "Headphone Jack", "HPOUTR", - "IN1L", "Line In Jack", - "IN1R", "Line In Jack"; - - atmel,ssc-controller = <&ssc0>; - atmel,audio-codec = <&wm8904>; - }; -}; diff --git a/sys/gnu/dts/arm/at91-smartkiz.dts b/sys/gnu/dts/arm/at91-smartkiz.dts deleted file mode 100644 index 106f23ba4a3..00000000000 --- a/sys/gnu/dts/arm/at91-smartkiz.dts +++ /dev/null @@ -1,109 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2017-2018 Overkiz SAS - * Author: Mickael Gardet - * Kévin Raymond - * Dorian Rocipon - */ -/dts-v1/; -#include "at91-kizboxmini-common.dtsi" - -/ { - model = "Overkiz SmartKiz"; - compatible = "overkiz,smartkiz", "atmel,at91sam9g25", - "atmel,at91sam9x5", "atmel,at91sam9"; - - clocks { - adc_op_clk { - status = "okay"; - }; - }; - - aliases { - serial5 = &uart0; - }; - - pio_keys { - hk_reset { - label = "HK_RESET"; - gpios = <&pioC 13 GPIO_ACTIVE_HIGH>; - }; - - power_rf { - label = "POWER_RF"; - gpios = <&pioA 20 GPIO_ACTIVE_HIGH>; - }; - - power_wifi { - label = "POWER_WIFI"; - gpios = <&pioA 21 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&pinctrl { - i2c1 { - pinctrl_i2c1: i2c1-0 { - atmel,pins = - ; - }; - }; - - adc0 { - pinctrl_adc0_ad0: adc0_ad0-0 { - /* pull-up disable */ - atmel,pins = ; - }; - pinctrl_adc0_ad5: adc0_ad5-0 { - /* pull-up disable */ - atmel,pins = ; - }; - pinctrl_adc0_ad6: adc0_ad6-0 { - /* pull-up disable */ - atmel,pins = ; - }; - pinctrl_adc0_ad11: adc0_ad11-0 { - /* pull-up disable */ - atmel,pins = ; - }; - }; -}; - -&i2c1 { - dmas = <0>, <0>; - pinctrl-0 = <&pinctrl_i2c1>; - status = "disabled"; -}; - -&macb0 { - status = "disabled"; -}; - -&rtc { - status = "okay"; -}; - -&leds { - blue { - status = "okay"; - }; -}; - -&adc0 { - atmel,adc-vref = <2500>; - pinctrl-names = "default"; - pinctrl-0 = < - &pinctrl_adc0_ad0 - &pinctrl_adc0_ad5 - &pinctrl_adc0_ad6 - &pinctrl_adc0_ad11 - >; - atmel,adc-channels-used = <0x0861>; - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - diff --git a/sys/gnu/dts/arm/at91-som60.dtsi b/sys/gnu/dts/arm/at91-som60.dtsi deleted file mode 100644 index 241682a207c..00000000000 --- a/sys/gnu/dts/arm/at91-som60.dtsi +++ /dev/null @@ -1,230 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * at91-som60.dtsi - Device Tree file for the SOM60 module - * - * Copyright (C) 2018 Laird, - * 2018 Ben Whitten - * - */ -#include "sama5d36.dtsi" - -/ { - model = "Laird SOM60"; - compatible = "laird,som60", "atmel,sama5d36", "atmel,sama5d3", "atmel,sama5"; - - chosen { - stdout-path = &dbgu; - }; - - memory { - reg = <0x20000000 0x8000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <12000000>; - }; - }; -}; - -&pinctrl { - board { - pinctrl_mmc0_cd: mmc0_cd { - atmel,pins = - ; - }; - - pinctrl_mmc0_en: mmc0_en { - atmel,pins = - ; - }; - - pinctrl_nand0_wp: nand0_wp { - atmel,pins = - ; - }; - - pinctrl_usb_vbus: usb_vbus { - atmel,pins = - ; - /* Conflicts with USART2_SCK */ - }; - - pinctrl_usart2_sck: usart2_sck { - atmel,pins = - ; - /* Conflicts with USB_VBUS */ - }; - - pinctrl_usb_oc: usb_oc { - atmel,pins = - ; - /* Conflicts with USART3_SCK */ - }; - - pinctrl_usart3_sck: usart3_sck { - atmel,pins = - ; - /* Conflicts with USB_OC */ - }; - - pinctrl_usba_vbus: usba_vbus { - atmel,pins = - ; - }; - - pinctrl_geth_int: geth_int { - atmel,pins = - ; - /* Conflicts with USART1_SCK */ - }; - - pinctrl_usart1_sck: usart1_sck { - atmel,pins = - ; - /* Conflicts with GETH_INT */ - }; - - pinctrl_eth_int: eth_int { - atmel,pins = - ; - }; - - pinctrl_pck2_as_audio_mck: pck2_as_audio_mck { - atmel,pins = - ; - }; - }; -}; - -&mmc0 { - slot@0 { - reg = <0>; - bus-width = <8>; - }; -}; - -&mmc1 { - status = "okay"; - slot@0 { - reg = <0>; - bus-width = <4>; - }; -}; - -&spi0 { - cs-gpios = <&pioD 13 0>, <0>, <0>, <0>; -}; - -&usart0 { - atmel,use-dma-rx; - atmel,use-dma-tx; - status = "okay"; - pinctrl-0 = <&pinctrl_usart0 &pinctrl_usart0_rts_cts>; -}; - -&usart1 { - pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts_cts>; -}; - -&usart2 { - pinctrl-0 = <&pinctrl_usart2 &pinctrl_usart2_rts_cts>; -}; - -&usart3 { - pinctrl-0 = <&pinctrl_usart3 &pinctrl_usart3_rts_cts>; -}; - -&adc0 { - pinctrl-0 = < - &pinctrl_adc0_adtrg - &pinctrl_adc0_ad0 - &pinctrl_adc0_ad1 - &pinctrl_adc0_ad2 - &pinctrl_adc0_ad3 - &pinctrl_adc0_ad4 - &pinctrl_adc0_ad5 - >; -}; - -&macb0 { - phy-mode = "rgmii"; -}; - -&macb1 { - phy-mode = "rmii"; -}; - -&ebi { - pinctrl-0 = <&pinctrl_ebi_nand_addr>; - pinctrl-names = "default"; - status = "okay"; -}; - -&nand_controller { - status = "okay"; - - nand: nand@3 { - reg = <0x3 0x0 0x2>; - atmel,rb = <0>; - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - nand-ecc-strength = <8>; - nand-ecc-step-size = <512>; - nand-on-flash-bbt; - label = "atmel_nand"; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - ubootspl@0 { - label = "u-boot-spl"; - reg = <0x0 0x20000>; - }; - - uboot@20000 { - label = "u-boot"; - reg = <0x20000 0x80000>; - }; - - ubootenv@a0000 { - label = "u-boot-env"; - reg = <0xa0000 0x20000>; - }; - - ubootenv@c0000 { - label = "u-boot-env"; - reg = <0xc0000 0x20000>; - }; - - ubi@e0000 { - label = "ubi"; - reg = <0xe0000 0xfe00000>; - }; - }; - }; -}; - -&usb0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usba_vbus>; - atmel,vbus-gpio = <&pioC 14 GPIO_ACTIVE_HIGH>; -}; - -&usb1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_vbus &pinctrl_usb_oc>; - num-ports = <3>; - atmel,vbus-gpio = <0 - &pioE 20 GPIO_ACTIVE_HIGH - 0>; - atmel,oc-gpio = <0 - &pioE 15 GPIO_ACTIVE_LOW - 0>; -}; diff --git a/sys/gnu/dts/arm/at91-tse850-3.dts b/sys/gnu/dts/arm/at91-tse850-3.dts deleted file mode 100644 index 3ca97b47c69..00000000000 --- a/sys/gnu/dts/arm/at91-tse850-3.dts +++ /dev/null @@ -1,302 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * at91-tse850-3.dts - Device Tree file for the Axentia TSE-850 3.0 board - * - * Copyright (C) 2017 Axentia Technologies AB - * - * Author: Peter Rosin - */ -/dts-v1/; -#include -#include "at91-linea.dtsi" - -/ { - model = "Axentia TSE-850 3.0"; - compatible = "axentia,tse850v3", "axentia,linea", - "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5"; - - sck: oscillator { - compatible = "fixed-clock"; - - #clock-cells = <0>; - clock-frequency = <16000000>; - clock-output-names = "sck"; - }; - - reg_3v3: regulator { - compatible = "regulator-fixed"; - - regulator-name = "3v3-supply"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ana: reg-ana { - compatible = "pwm-regulator"; - - regulator-name = "ANA"; - - pwms = <&pwm0 2 1000 PWM_POLARITY_INVERTED>; - pwm-dutycycle-unit = <1000>; - pwm-dutycycle-range = <100 1000>; - - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <20000000>; - regulator-ramp-delay = <1000>; - }; - - sound { - compatible = "axentia,tse850-pcm5142"; - - axentia,cpu-dai = <&ssc0>; - axentia,audio-codec = <&pcm5142>; - - axentia,add-gpios = <&pioA 8 GPIO_ACTIVE_LOW>; - axentia,loop1-gpios = <&pioA 10 GPIO_ACTIVE_LOW>; - axentia,loop2-gpios = <&pioA 11 GPIO_ACTIVE_LOW>; - - axentia,ana-supply = <&ana>; - }; - - dac: dpot-dac { - compatible = "dpot-dac"; - vref-supply = <®_3v3>; - io-channels = <&dpot 0>; - io-channel-names = "dpot"; - #io-channel-cells = <1>; - }; - - env_det: envelope-detector { - compatible = "axentia,tse850-envelope-detector"; - io-channels = <&dac 0>; - io-channel-names = "dac"; - #io-channel-cells = <1>; - - interrupt-parent = <&pioA>; - interrupts = <3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "comp"; - }; - - mux: mux-controller { - compatible = "gpio-mux"; - #mux-control-cells = <0>; - - mux-gpios = <&pioA 0 GPIO_ACTIVE_HIGH>, - <&pioA 1 GPIO_ACTIVE_HIGH>, - <&pioA 2 GPIO_ACTIVE_HIGH>; - idle-state = <0>; - }; - - envelope-detector-mux { - compatible = "io-channel-mux"; - io-channels = <&env_det 0>; - io-channel-names = "parent"; - - mux-controls = <&mux>; - - channels = "", "", - "sync-1", - "in", - "out", - "sync-2", - "sys-reg", - "ana-reg"; - }; - - leds { - compatible = "gpio-leds"; - - ch1-red { - label = "ch-1:red"; - gpios = <&pioA 23 GPIO_ACTIVE_LOW>; - }; - ch1-green { - label = "ch-1:green"; - gpios = <&pioA 22 GPIO_ACTIVE_LOW>; - }; - ch2-red { - label = "ch-2:red"; - gpios = <&pioA 21 GPIO_ACTIVE_LOW>; - }; - ch2-green { - label = "ch-2:green"; - gpios = <&pioA 20 GPIO_ACTIVE_LOW>; - }; - data-red { - label = "data:red"; - gpios = <&pioA 19 GPIO_ACTIVE_LOW>; - }; - data-green { - label = "data:green"; - gpios = <&pioA 18 GPIO_ACTIVE_LOW>; - }; - alarm-red { - label = "alarm:red"; - gpios = <&pioA 17 GPIO_ACTIVE_LOW>; - }; - alarm-green { - label = "alarm:green"; - gpios = <&pioA 16 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&nand { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - at91bootstrap@0 { - label = "at91bootstrap"; - reg = <0x0 0x40000>; - }; - - barebox@40000 { - label = "bootloader"; - reg = <0x40000 0x60000>; - }; - - bareboxenv@c0000 { - label = "bareboxenv"; - reg = <0xc0000 0x40000>; - }; - - bareboxenv2@100000 { - label = "bareboxenv2"; - reg = <0x100000 0x40000>; - }; - - oftree@180000 { - label = "oftree"; - reg = <0x180000 0x20000>; - }; - - kernel@200000 { - label = "kernel"; - reg = <0x200000 0x500000>; - }; - - rootfs@800000 { - label = "rootfs"; - reg = <0x800000 0x0f800000>; - }; - - ovlfs@10000000 { - label = "ovlfs"; - reg = <0x10000000 0x10000000>; - }; - }; -}; - -&ssc0 { - #sound-dai-cells = <0>; - - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - jc42@18 { - compatible = "nxp,se97b", "jedec,jc-42.4-temp"; - reg = <0x18>; - smbus-timeout-disable; - }; - - dpot: mcp4651-104@28 { - compatible = "microchip,mcp4651-104"; - reg = <0x28>; - #io-channel-cells = <1>; - }; - - pcm5142: pcm5142@4c { - compatible = "ti,pcm5142"; - - reg = <0x4c>; - #sound-dai-cells = <0>; - - AVDD-supply = <®_3v3>; - DVDD-supply = <®_3v3>; - CPVDD-supply = <®_3v3>; - - clocks = <&sck>; - - pll-in = <3>; - pll-out = <6>; - }; - - eeprom@50 { - compatible = "nxp,se97b", "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; -}; - -&pinctrl { - tse850 { - pinctrl_usba_vbus: usba-vbus { - atmel,pins = ; - }; - }; -}; - -&watchdog { - status = "okay"; -}; - -&usart0 { - status = "okay"; - - atmel,use-dma-rx; -}; - -&pwm0 { - status = "okay"; - - pinctrl-0 = <&pinctrl_pwm0_pwml2_1>; - pinctrl-names = "default"; -}; - -&macb1 { - status = "okay"; - - phy-mode = "rgmii"; - - #address-cells = <1>; - #size-cells = <0>; - - phy0: ethernet-phy@3 { - reg = <3>; - - interrupt-parent = <&pioE>; - interrupts = <31 IRQ_TYPE_EDGE_FALLING>; - }; -}; - -&usb0 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usba_vbus>; - atmel,vbus-gpio = <&pioC 31 GPIO_ACTIVE_HIGH>; -}; - -&usb1 { - status = "okay"; - - num-ports = <1>; - atmel,vbus-gpio = <&pioD 29 GPIO_ACTIVE_HIGH>; - atmel,oc-gpio = <&pioC 15 GPIO_ACTIVE_LOW>; -}; - -&usb2 { - status = "okay"; -}; - -&dbgu { - status = "okay"; - - dmas = <0>, <0>; /* Do not use DMA for dbgu */ -}; diff --git a/sys/gnu/dts/arm/at91-vinco.dts b/sys/gnu/dts/arm/at91-vinco.dts deleted file mode 100644 index 15050fdd479..00000000000 --- a/sys/gnu/dts/arm/at91-vinco.dts +++ /dev/null @@ -1,231 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for VInCo platform - * - * Copyright (C) 2014 Atmel, - * 2014 Nicolas Ferre - * 2015 Gregory CLEMENT - */ -/dts-v1/; -#include "sama5d4.dtsi" - -/ { - model = "L+G VInCo platform"; - compatible = "l+g,vinco", "atmel,sama5d4", "atmel,sama5"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - reg = <0x20000000 0x4000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <12000000>; - }; - }; - - ahb { - apb { - - adc0: adc@fc034000 { - status = "okay"; /* Enable ADC IIO support */ - }; - - mmc0: mmc@f8000000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 - &pinctrl_mmc0_dat1_3 - &pinctrl_mmc0_dat4_7>; - vqmmc-supply = <&vcc_3v3_reg>; - vmmc-supply = <&vcc_3v3_reg>; - no-1-8-v; - status = "okay"; - slot@0 { - reg = <0>; - bus-width = <8>; - non-removable; - broken-cd; - status = "okay"; - }; - }; - - spi0: spi@f8010000 { - cs-gpios = <&pioC 3 0>, <0>, <0>, <0>; - status = "okay"; - m25p80@0 { - compatible = "n25q32b", "jedec,spi-nor"; - spi-max-frequency = <50000000>; - reg = <0>; - }; - }; - - i2c0: i2c@f8014000 { - status = "okay"; - }; - - i2c1: i2c@f8018000 { - status = "okay"; - /* kerkey security module */ - }; - - macb0: ethernet@f8020000 { - phy-mode = "rmii"; - status = "okay"; - - ethernet-phy@1 { - reg = <0x1>; - reset-gpios = <&pioE 8 GPIO_ACTIVE_LOW>; - interrupt-parent = <&pioB>; - interrupts = <15 IRQ_TYPE_EDGE_FALLING>; - }; - - }; - - i2c2: i2c@f8024000 { - status = "okay"; - - rtc1: rtc@32 { - compatible = "epson,rx8900"; - reg = <0x32>; - }; - }; - - usart2: serial@fc008000 { - /* MBUS */ - status = "okay"; - }; - - usart3: serial@fc00c000 { - /* debug */ - status = "okay"; - }; - - usart4: serial@fc010000 { - /* LMN */ - pinctrl-0 = <&pinctrl_usart4 &pinctrl_usart4_rts>; - linux,rs485-enabled-at-boot-time; - status = "okay"; - }; - - tcb2: timer@fc024000 { - timer@0 { - compatible = "atmel,tcb-timer"; - reg = <0>; - }; - - timer@1 { - compatible = "atmel,tcb-timer"; - reg = <1>; - }; - }; - - macb1: ethernet@fc028000 { - phy-mode = "rmii"; - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - ethernet-phy@1 { - reg = <0x1>; - interrupt-parent = <&pioB>; - interrupts = <31 IRQ_TYPE_EDGE_FALLING>; - reset-gpios = <&pioE 6 GPIO_ACTIVE_LOW>; - }; - }; - - watchdog@fc068640 { - status = "okay"; - }; - - pinctrl@fc06a000 { - board { - pinctrl_usba_vbus: usba_vbus { - atmel,pins = - ; - }; - }; - }; - }; - - usb0: gadget@400000 { - atmel,vbus-gpio = <&pioE 31 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usba_vbus>; - status = "disable"; - }; - - usb1: ohci@500000 { - num-ports = <3>; - atmel,vbus-gpio = <0 - &pioE 11 GPIO_ACTIVE_LOW - &pioE 12 GPIO_ACTIVE_LOW - >; - status = "disable"; - }; - - usb2: ehci@600000 { - /* 4G Modem */ - status = "okay"; - }; - - }; - - leds { - compatible = "gpio-leds"; - status = "okay"; - - led_err { - label = "err"; - gpios = <&pioA 7 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led_rssi { - label = "rssi"; - gpios = <&pioA 9 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led_tls { - label = "tls"; - gpios = <&pioA 24 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led_lmc { - label = "lmc"; - gpios = <&pioA 25 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led_wmt { - label = "wmt"; - gpios = <&pioA 29 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led_pwr { - label = "pwr"; - gpios = <&pioA 26 GPIO_ACTIVE_LOW>; - default-state = "on"; - }; - - }; - - vcc_3v3_reg: fixedregulator_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC 3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; -}; diff --git a/sys/gnu/dts/arm/at91-wb45n.dts b/sys/gnu/dts/arm/at91-wb45n.dts deleted file mode 100644 index 54d130c9218..00000000000 --- a/sys/gnu/dts/arm/at91-wb45n.dts +++ /dev/null @@ -1,64 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * at91-wb45n.dts - Device Tree file for WB45NBT board - * - * Copyright (C) 2018 Laird - * - */ -/dts-v1/; -#include "at91-wb45n.dtsi" - -/ { - model = "Laird Workgroup Bridge 45N - Atmel AT91SAM (dt)"; - compatible = "laird,wb45n", "laird,wbxx", "atmel,at91sam9x5", "atmel,at91sam9"; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - irqbtn@18 { - reg = <18>; - label = "IRQBTN"; - linux,code = <99>; - gpios = <&pioB 18 GPIO_ACTIVE_LOW>; - wakeup-source; - }; - }; -}; - -&watchdog { - status = "okay"; -}; - -&usb0 { - status = "okay"; -}; - -&mmc0 { - status = "okay"; -}; - -&spi0 { - status = "okay"; -}; - -&macb0 { - status = "okay"; -}; - -&dbgu { - status = "okay"; -}; - -&usart0 { - status = "okay"; -}; - -&usart3 { - status = "okay"; -}; - -&i2c1 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/at91-wb45n.dtsi b/sys/gnu/dts/arm/at91-wb45n.dtsi deleted file mode 100644 index ebe61a25ca9..00000000000 --- a/sys/gnu/dts/arm/at91-wb45n.dtsi +++ /dev/null @@ -1,165 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * at91-wb45n.dtsi - Device Tree file for WB45NBT board - * - * Copyright (C) 2018 Laird - * - */ - -#include "at91sam9g25.dtsi" - -/ { - model = "Laird Workgroup Bridge 45N - Atmel AT91SAM (dt)"; - compatible = "laird,wb45n", "laird,wbxx", "atmel,at91sam9x5", "atmel,at91sam9"; - - chosen { - bootargs = "ubi.mtd=6 root=ubi0:rootfs rootfstype=ubifs rw"; - stdout-path = "serial0:115200n8"; - }; - - memory { - reg = <0x20000000 0x4000000>; - }; - - atheros { - compatible = "atheros,ath6kl"; - atheros,board-id = "SD32"; - }; -}; - -&reset_controller { - compatible = "atmel,sama5d3-rstc"; -}; - -&shutdown_controller { - atmel,wakeup-mode = "low"; -}; - -&slow_xtal { - clock-frequency = <32768>; -}; - -&main_xtal { - clock-frequency = <12000000>; -}; - -&ebi { - status = "okay"; - nand_controller: nand-controller { - pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb &pinctrl_nand_oe_we>; - pinctrl-names = "default"; - status = "okay"; - - nand@3 { - reg = <0x3 0x0 0x800000>; - rb-gpios = <&pioD 5 GPIO_ACTIVE_HIGH>; - cs-gpios = <&pioD 4 GPIO_ACTIVE_HIGH>; - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - nand-ecc-strength = <4>; - nand-ecc-step-size = <512>; - nand-on-flash-bbt; - label = "atmel_nand"; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - at91bootstrap@0 { - label = "at91bs"; - reg = <0x0 0x20000>; - }; - - uboot@20000 { - label = "u-boot"; - reg = <0x20000 0x80000>; - }; - - ubootenv@a0000 { - label = "u-boot-env"; - reg = <0xa0000 0x20000>; - }; - - ubootenv@c0000 { - label = "redund-env"; - reg = <0xc0000 0x20000>; - }; - - kernel-a@e0000 { - label = "kernel-a"; - reg = <0xe0000 0x280000>; - }; - - kernel-b@360000 { - label = "kernel-b"; - reg = <0x360000 0x280000>; - }; - - rootfs-a@5e0000 { - label = "rootfs-a"; - reg = <0x5e0000 0x2600000>; - }; - - rootfs-b@2be0000 { - label = "rootfs-b"; - reg = <0x2be0000 0x2600000>; - }; - - user@51e0000 { - label = "user"; - reg = <0x51e0000 0x2dc0000>; - }; - - logs@7fa0000 { - label = "logs"; - reg = <0x7fa0000 0x60000>; - }; - - }; - }; - }; -}; - -&usb0 { - num-ports = <2>; - atmel,vbus-gpio = < - &pioB 12 GPIO_ACTIVE_HIGH - &pioA 31 GPIO_ACTIVE_HIGH - >; - atmel,oc-gpio = <&pioB 13 GPIO_ACTIVE_LOW>; -}; - -&macb0 { - phy-mode = "rmii"; -}; - -&spi0 { - cs-gpios = <&pioA 14 0>, <&pioA 7 0>, <0>, <0>; -}; - -&usb2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_board_usb2>; - atmel,vbus-gpio = <&pioB 11 GPIO_ACTIVE_HIGH>; -}; - -&mmc0 { - pinctrl-0 = < - &pinctrl_mmc0_slot0_clk_cmd_dat0 - &pinctrl_mmc0_slot0_dat1_3>; - slot@0 { - reg = <0>; - bus-width = <4>; - }; -}; - -&pinctrl { - usb2 { - pinctrl_board_usb2: usb2-board { - atmel,pins = - ; /* PB11 gpio vbus sense, deglitch */ - }; - }; -}; - diff --git a/sys/gnu/dts/arm/at91-wb50n.dts b/sys/gnu/dts/arm/at91-wb50n.dts deleted file mode 100644 index a5e45bb95c0..00000000000 --- a/sys/gnu/dts/arm/at91-wb50n.dts +++ /dev/null @@ -1,112 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * at91-wb50n.dts - Device Tree file for wb50n evaluation board - * - * Copyright (C) 2018 Laird - * - */ - -/dts-v1/; -#include "at91-wb50n.dtsi" - -/ { - model = "Laird Workgroup Bridge 50N - Atmel SAMA5D"; - compatible = "laird,wb50n", "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5"; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - btn0@10 { - reg = <10>; - label = "BTNESC"; - linux,code = <1>; /* ESC button */ - gpios = <&pioA 10 GPIO_ACTIVE_LOW>; - wakeup-source; - }; - - irqbtn@31 { - reg = <31>; - label = "IRQBTN"; - linux,code = <99>; /* SysReq button */ - gpios = <&pioE 31 GPIO_ACTIVE_LOW>; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - - led0 { - label = "wb50n:blue:led0"; - gpios = <&pioA 12 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led1 { - label = "wb50n:green:led1"; - gpios = <&pioA 24 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led2 { - label = "wb50n:red:led2"; - gpios = <&pioA 26 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - }; -}; - -&watchdog { - status = "okay"; -}; - -&mmc0 { - status = "okay"; -}; - -&macb1 { - status = "okay"; -}; - -&dbgu { - status = "okay"; -}; - -/* On BB40 this port is labeled UART1 */ -&usart0 { - status = "okay"; -}; - -/* On BB40 this port is labeled UART0 */ -&usart1 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; -}; - -&spi1 { - status = "okay"; - - spidev@0 { - compatible = "spidev"; - reg = <0>; - spi-max-frequency = <8000000>; - }; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; - -&usb2 { - status = "okay"; -}; - diff --git a/sys/gnu/dts/arm/at91-wb50n.dtsi b/sys/gnu/dts/arm/at91-wb50n.dtsi deleted file mode 100644 index 4ed8500a5cb..00000000000 --- a/sys/gnu/dts/arm/at91-wb50n.dtsi +++ /dev/null @@ -1,198 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * at91-wb50n.dtsi - Device Tree include file for wb50n cpu module - * - * Copyright (C) 2018 Laird - * - */ - -#include "sama5d31.dtsi" - -/ { - model = "Laird Workgroup Bridge 50N - Atmel SAMA5D"; - compatible = "laird,wb50n", "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5"; - - chosen { - bootargs = "ubi.mtd=6 root=ubi0:rootfs rootfstype=ubifs rw"; - stdout-path = "serial0:115200n8"; - }; - - memory { - reg = <0x20000000 0x4000000>; - }; -}; - -&pinctrl { - board { - pinctrl_mmc0_cd: mmc0_cd { - atmel,pins = ; /* PC26 GPIO with pullup deglitch */ - }; - - pinctrl_usba_vbus: usba_vbus { - atmel,pins = ; /* PB13 GPIO with deglitch */ - }; - }; -}; - -&slow_xtal { - clock-frequency = <32768>; -}; - -&main_xtal { - clock-frequency = <12000000>; -}; - -&clk32k { - atmel,osc-bypass; -}; - -&usart1_clk { - atmel,clk-output-range = <0 132000000>; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_cd>; - cd-gpios = <&pioC 26 GPIO_ACTIVE_LOW>; - slot@0 { - reg = <0>; - bus-width = <4>; - }; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>; - status = "okay"; - atheros@0 { - compatible = "atheros,ath6kl"; - atheros,board-id = "SD32"; - reg = <0>; - bus-width = <4>; - }; -}; - -&macb1 { - phy-mode = "rmii"; -}; - -&dbgu { - dmas = <0>, <0>; /* Do not use DMA for dbgu */ -}; - -/* On BB40 this port is labeled UART1 */ -&usart0 { - atmel,use-dma-rx; - atmel,use-dma-tx; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart0 &pinctrl_usart0_rts_cts>; -}; - -/* On BB40 this port is labeled UART0 */ -&usart1 { - atmel,use-dma-rx; - atmel,use-dma-tx; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts_cts>; - dtr-gpios = <&pioD 13 GPIO_ACTIVE_LOW>; - dsr-gpios = <&pioD 11 GPIO_ACTIVE_LOW>; - dcd-gpios = <&pioD 7 GPIO_ACTIVE_LOW>; - rng-gpios = <&pioD 8 GPIO_ACTIVE_LOW>; -}; - -/* USART3 is direct-connect to the Bluetooth UART on the radio SIP */ -&usart3 { - atmel,use-dma-rx; - atmel,use-dma-tx; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart3 &pinctrl_usart3_rts_cts>; - status = "okay"; -}; - -&spi1 { - cs-gpios = <&pioC 25 0>, <0>, <0>, <0>; -}; - -&ebi { - pinctrl-0 = <&pinctrl_ebi_nand_addr>; - pinctrl-names = "default"; - status = "okay"; -}; - -&nand_controller { - status = "okay"; - - nand: nand@3 { - reg = <0x3 0x0 0x2>; - atmel,rb = <0>; - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - nand-ecc-strength = <8>; - nand-ecc-step-size = <512>; - nand-on-flash-bbt; - label = "atmel_nand"; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - at91bootstrap@0 { - label = "at91bs"; - reg = <0x0 0x20000>; - }; - - uboot@20000 { - label = "u-boot"; - reg = <0x20000 0x80000>; - }; - - ubootenv@a0000 { - label = "u-boot-env"; - reg = <0xa0000 0x20000>; - }; - - ubootenv@c0000 { - label = "u-boot-env"; - reg = <0xc0000 0x20000>; - }; - - kernel-a@e0000 { - label = "kernel-a"; - reg = <0xe0000 0x500000>; - }; - - kernel-b@5e0000 { - label = "kernel-b"; - reg = <0x5e0000 0x500000>; - }; - - rootfs-a@ae0000 { - label = "rootfs-a"; - reg = <0xae0000 0x3000000>; - }; - - rootfs-b@3ae0000 { - label = "rootfs-b"; - reg = <0x3ae0000 0x3000000>; - }; - - user@6ae0000 { - label = "user"; - reg = <0x6ae0000 0x14e0000>; - }; - }; - }; -}; - -&usb0 { - atmel,vbus-gpio = <&pioB 13 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usba_vbus>; -}; - -&usb1 { - num-ports = <3>; - atmel,vbus-gpio = <&pioA 2 GPIO_ACTIVE_LOW>; - atmel,oc-gpio = <&pioA 4 GPIO_ACTIVE_LOW>; -}; diff --git a/sys/gnu/dts/arm/at91rm9200.dtsi b/sys/gnu/dts/arm/at91rm9200.dtsi deleted file mode 100644 index 44385718d9d..00000000000 --- a/sys/gnu/dts/arm/at91rm9200.dtsi +++ /dev/null @@ -1,970 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * at91rm9200.dtsi - Device Tree Include file for AT91RM9200 family SoC - * - * Copyright (C) 2011 Atmel, - * 2011 Nicolas Ferre , - * 2012 Joachim Eastwood - * - * Based on at91sam9260.dtsi - */ - -#include -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - model = "Atmel AT91RM9200 family SoC"; - compatible = "atmel,at91rm9200"; - interrupt-parent = <&aic>; - - aliases { - serial0 = &dbgu; - serial1 = &usart0; - serial2 = &usart1; - serial3 = &usart2; - serial4 = &usart3; - gpio0 = &pioA; - gpio1 = &pioB; - gpio2 = &pioC; - gpio3 = &pioD; - tcb0 = &tcb0; - tcb1 = &tcb1; - i2c0 = &i2c0; - ssc0 = &ssc0; - ssc1 = &ssc1; - ssc2 = &ssc2; - }; - cpus { - #address-cells = <0>; - #size-cells = <0>; - - cpu { - compatible = "arm,arm920t"; - device_type = "cpu"; - }; - }; - - memory { - device_type = "memory"; - reg = <0x20000000 0x04000000>; - }; - - clocks { - slow_xtal: slow_xtal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - main_xtal: main_xtal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - }; - - sram: sram@200000 { - compatible = "mmio-sram"; - reg = <0x00200000 0x4000>; - }; - - ahb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - apb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - aic: interrupt-controller@fffff000 { - #interrupt-cells = <3>; - compatible = "atmel,at91rm9200-aic"; - interrupt-controller; - reg = <0xfffff000 0x200>; - atmel,external-irqs = <25 26 27 28 29 30 31>; - }; - - ramc0: ramc@ffffff00 { - compatible = "atmel,at91rm9200-sdramc", "syscon"; - reg = <0xffffff00 0x100>; - }; - - pmc: pmc@fffffc00 { - compatible = "atmel,at91rm9200-pmc", "syscon"; - reg = <0xfffffc00 0x100>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - interrupt-controller; - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - - main_osc: main_osc { - compatible = "atmel,at91rm9200-clk-main-osc"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_MOSCS>; - clocks = <&main_xtal>; - }; - - main: mainck { - compatible = "atmel,at91rm9200-clk-main"; - #clock-cells = <0>; - clocks = <&main_osc>; - }; - - plla: pllack { - compatible = "atmel,at91rm9200-clk-pll"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_LOCKA>; - clocks = <&main>; - reg = <0>; - atmel,clk-input-range = <1000000 32000000>; - #atmel,pll-clk-output-range-cells = <3>; - atmel,pll-clk-output-ranges = <80000000 160000000 0>, - <150000000 180000000 2>; - }; - - pllb: pllbck { - compatible = "atmel,at91rm9200-clk-pll"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_LOCKB>; - clocks = <&main>; - reg = <1>; - atmel,clk-input-range = <1000000 32000000>; - #atmel,pll-clk-output-range-cells = <3>; - atmel,pll-clk-output-ranges = <80000000 160000000 0>, - <150000000 180000000 2>; - }; - - mck: masterck { - compatible = "atmel,at91rm9200-clk-master"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_MCKRDY>; - clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>; - atmel,clk-output-range = <0 80000000>; - atmel,clk-divisors = <1 2 3 4>; - }; - - usb: usbck { - compatible = "atmel,at91rm9200-clk-usb"; - #clock-cells = <0>; - atmel,clk-divisors = <1 2 0 0>; - clocks = <&pllb>; - }; - - prog: progck { - compatible = "atmel,at91rm9200-clk-programmable"; - #address-cells = <1>; - #size-cells = <0>; - interrupt-parent = <&pmc>; - clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>; - - prog0: prog0 { - #clock-cells = <0>; - reg = <0>; - interrupts = ; - }; - - prog1: prog1 { - #clock-cells = <0>; - reg = <1>; - interrupts = ; - }; - - prog2: prog2 { - #clock-cells = <0>; - reg = <2>; - interrupts = ; - }; - - prog3: prog3 { - #clock-cells = <0>; - reg = <3>; - interrupts = ; - }; - }; - - systemck { - compatible = "atmel,at91rm9200-clk-system"; - #address-cells = <1>; - #size-cells = <0>; - - udpck: udpck { - #clock-cells = <0>; - reg = <2>; - clocks = <&usb>; - }; - - uhpck: uhpck { - #clock-cells = <0>; - reg = <4>; - clocks = <&usb>; - }; - - pck0: pck0 { - #clock-cells = <0>; - reg = <8>; - clocks = <&prog0>; - }; - - pck1: pck1 { - #clock-cells = <0>; - reg = <9>; - clocks = <&prog1>; - }; - - pck2: pck2 { - #clock-cells = <0>; - reg = <10>; - clocks = <&prog2>; - }; - - pck3: pck3 { - #clock-cells = <0>; - reg = <11>; - clocks = <&prog3>; - }; - }; - - periphck { - compatible = "atmel,at91rm9200-clk-peripheral"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&mck>; - - pioA_clk: pioA_clk { - #clock-cells = <0>; - reg = <2>; - }; - - pioB_clk: pioB_clk { - #clock-cells = <0>; - reg = <3>; - }; - - pioC_clk: pioC_clk { - #clock-cells = <0>; - reg = <4>; - }; - - pioD_clk: pioD_clk { - #clock-cells = <0>; - reg = <5>; - }; - - usart0_clk: usart0_clk { - #clock-cells = <0>; - reg = <6>; - }; - - usart1_clk: usart1_clk { - #clock-cells = <0>; - reg = <7>; - }; - - usart2_clk: usart2_clk { - #clock-cells = <0>; - reg = <8>; - }; - - usart3_clk: usart3_clk { - #clock-cells = <0>; - reg = <9>; - }; - - mci0_clk: mci0_clk { - #clock-cells = <0>; - reg = <10>; - }; - - udc_clk: udc_clk { - #clock-cells = <0>; - reg = <11>; - }; - - twi0_clk: twi0_clk { - reg = <12>; - #clock-cells = <0>; - }; - - spi0_clk: spi0_clk { - #clock-cells = <0>; - reg = <13>; - }; - - ssc0_clk: ssc0_clk { - #clock-cells = <0>; - reg = <14>; - }; - - ssc1_clk: ssc1_clk { - #clock-cells = <0>; - reg = <15>; - }; - - ssc2_clk: ssc2_clk { - #clock-cells = <0>; - reg = <16>; - }; - - tc0_clk: tc0_clk { - #clock-cells = <0>; - reg = <17>; - }; - - tc1_clk: tc1_clk { - #clock-cells = <0>; - reg = <18>; - }; - - tc2_clk: tc2_clk { - #clock-cells = <0>; - reg = <19>; - }; - - tc3_clk: tc3_clk { - #clock-cells = <0>; - reg = <20>; - }; - - tc4_clk: tc4_clk { - #clock-cells = <0>; - reg = <21>; - }; - - tc5_clk: tc5_clk { - #clock-cells = <0>; - reg = <22>; - }; - - ohci_clk: ohci_clk { - #clock-cells = <0>; - reg = <23>; - }; - - macb0_clk: macb0_clk { - #clock-cells = <0>; - reg = <24>; - }; - }; - }; - - st: timer@fffffd00 { - compatible = "atmel,at91rm9200-st", "syscon", "simple-mfd"; - reg = <0xfffffd00 0x100>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&slow_xtal>; - - watchdog { - compatible = "atmel,at91rm9200-wdt"; - }; - }; - - rtc: rtc@fffffe00 { - compatible = "atmel,at91rm9200-rtc"; - reg = <0xfffffe00 0x40>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&slow_xtal>; - status = "disabled"; - }; - - tcb0: timer@fffa0000 { - compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xfffa0000 0x100>; - interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0 - 18 IRQ_TYPE_LEVEL_HIGH 0 - 19 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>, <&slow_xtal>; - clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; - }; - - tcb1: timer@fffa4000 { - compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xfffa4000 0x100>; - interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0 - 21 IRQ_TYPE_LEVEL_HIGH 0 - 22 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tc3_clk>, <&tc4_clk>, <&tc5_clk>, <&slow_xtal>; - clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; - }; - - i2c0: i2c@fffb8000 { - compatible = "atmel,at91rm9200-i2c"; - reg = <0xfffb8000 0x4000>; - interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_twi>; - clocks = <&twi0_clk>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - mmc0: mmc@fffb4000 { - compatible = "atmel,hsmci"; - reg = <0xfffb4000 0x4000>; - interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&mci0_clk>; - clock-names = "mci_clk"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - status = "disabled"; - }; - - ssc0: ssc@fffd0000 { - compatible = "atmel,at91rm9200-ssc"; - reg = <0xfffd0000 0x4000>; - interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; - clocks = <&ssc0_clk>; - clock-names = "pclk"; - status = "disabled"; - }; - - ssc1: ssc@fffd4000 { - compatible = "atmel,at91rm9200-ssc"; - reg = <0xfffd4000 0x4000>; - interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; - clocks = <&ssc1_clk>; - clock-names = "pclk"; - status = "disabled"; - }; - - ssc2: ssc@fffd8000 { - compatible = "atmel,at91rm9200-ssc"; - reg = <0xfffd8000 0x4000>; - interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ssc2_tx &pinctrl_ssc2_rx>; - clocks = <&ssc2_clk>; - clock-names = "pclk"; - status = "disabled"; - }; - - macb0: ethernet@fffbc000 { - compatible = "cdns,at91rm9200-emac", "cdns,emac"; - reg = <0xfffbc000 0x4000>; - interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>; - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_macb_rmii>; - clocks = <&macb0_clk>; - clock-names = "ether_clk"; - status = "disabled"; - }; - - pinctrl@fffff400 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "atmel,at91rm9200-pinctrl", "simple-bus"; - ranges = <0xfffff400 0xfffff400 0x800>; - - atmel,mux-mask = < - /* A B */ - 0xffffffff 0xffffffff /* pioA */ - 0xffffffff 0x083fffff /* pioB */ - 0xffff3fff 0x00000000 /* pioC */ - 0x03ff87ff 0x0fffff80 /* pioD */ - >; - - /* shared pinctrl settings */ - dbgu { - pinctrl_dbgu: dbgu-0 { - atmel,pins = - ; - }; - }; - - uart0 { - pinctrl_uart0: uart0-0 { - atmel,pins = - ; - }; - - pinctrl_uart0_cts: uart0_cts-0 { - atmel,pins = - ; /* PA20 periph A */ - }; - - pinctrl_uart0_rts: uart0_rts-0 { - atmel,pins = - ; /* PA21 periph A */ - }; - }; - - uart1 { - pinctrl_uart1: uart1-0 { - atmel,pins = - ; - }; - - pinctrl_uart1_rts: uart1_rts-0 { - atmel,pins = - ; /* PB24 periph A */ - }; - - pinctrl_uart1_cts: uart1_cts-0 { - atmel,pins = - ; /* PB26 periph A */ - }; - - pinctrl_uart1_dtr_dsr: uart1_dtr_dsr-0 { - atmel,pins = - ; /* PB25 periph A */ - }; - - pinctrl_uart1_dcd: uart1_dcd-0 { - atmel,pins = - ; /* PB23 periph A */ - }; - - pinctrl_uart1_ri: uart1_ri-0 { - atmel,pins = - ; /* PB18 periph A */ - }; - }; - - uart2 { - pinctrl_uart2: uart2-0 { - atmel,pins = - ; - }; - - pinctrl_uart2_rts: uart2_rts-0 { - atmel,pins = - ; /* PA30 periph B */ - }; - - pinctrl_uart2_cts: uart2_cts-0 { - atmel,pins = - ; /* PA31 periph B */ - }; - }; - - uart3 { - pinctrl_uart3: uart3-0 { - atmel,pins = - ; - }; - - pinctrl_uart3_rts: uart3_rts-0 { - atmel,pins = - ; /* PB0 periph B */ - }; - - pinctrl_uart3_cts: uart3_cts-0 { - atmel,pins = - ; /* PB1 periph B */ - }; - }; - - nand { - pinctrl_nand: nand-0 { - atmel,pins = - ; /* PB1 gpio CD pin pull_up */ - }; - }; - - macb { - pinctrl_macb_rmii: macb_rmii-0 { - atmel,pins = - ; /* PA16 periph A */ - }; - - pinctrl_macb_rmii_mii: macb_rmii_mii-0 { - atmel,pins = - ; /* PB19 periph B */ - }; - }; - - mmc0 { - pinctrl_mmc0_clk: mmc0_clk-0 { - atmel,pins = - ; /* PA27 periph A */ - }; - - pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 { - atmel,pins = - ; /* PA29 periph A with pullup */ - }; - - pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { - atmel,pins = - ; /* PB5 periph B with pullup */ - }; - - pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 { - atmel,pins = - ; /* PA9 periph B with pullup */ - }; - - pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 { - atmel,pins = - ; /* PA12 periph B with pullup */ - }; - }; - - ssc0 { - pinctrl_ssc0_tx: ssc0_tx-0 { - atmel,pins = - ; /* PB2 periph A */ - }; - - pinctrl_ssc0_rx: ssc0_rx-0 { - atmel,pins = - ; /* PB5 periph A */ - }; - }; - - ssc1 { - pinctrl_ssc1_tx: ssc1_tx-0 { - atmel,pins = - ; /* PB8 periph A */ - }; - - pinctrl_ssc1_rx: ssc1_rx-0 { - atmel,pins = - ; /* PB11 periph A */ - }; - }; - - ssc2 { - pinctrl_ssc2_tx: ssc2_tx-0 { - atmel,pins = - ; /* PB14 periph A */ - }; - - pinctrl_ssc2_rx: ssc2_rx-0 { - atmel,pins = - ; /* PB17 periph A */ - }; - }; - - twi { - pinctrl_twi: twi-0 { - atmel,pins = - ; /* PA26 periph A with multi drive */ - }; - - pinctrl_twi_gpio: twi_gpio-0 { - atmel,pins = - ; /* PA26 GPIO with multi drive */ - }; - }; - - tcb0 { - pinctrl_tcb0_tclk0: tcb0_tclk0-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tclk1: tcb0_tclk1-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tclk2: tcb0_tclk2-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tioa0: tcb0_tioa0-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tioa1: tcb0_tioa1-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tioa2: tcb0_tioa2-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tiob0: tcb0_tiob0-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tiob1: tcb0_tiob1-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tiob2: tcb0_tiob2-0 { - atmel,pins = ; - }; - }; - - tcb1 { - pinctrl_tcb1_tclk0: tcb1_tclk0-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tclk1: tcb1_tclk1-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tclk2: tcb1_tclk2-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tioa0: tcb1_tioa0-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tioa1: tcb1_tioa1-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tioa2: tcb1_tioa2-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tiob0: tcb1_tiob0-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tiob1: tcb1_tiob1-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tiob2: tcb1_tiob2-0 { - atmel,pins = ; - }; - }; - - spi0 { - pinctrl_spi0: spi0-0 { - atmel,pins = - ; /* PA2 periph A SPI0_SPCK pin */ - }; - }; - - pioA: gpio@fffff400 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff400 0x200>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioA_clk>; - }; - - pioB: gpio@fffff600 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff600 0x200>; - interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioB_clk>; - }; - - pioC: gpio@fffff800 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff800 0x200>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioC_clk>; - }; - - pioD: gpio@fffffa00 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffffa00 0x200>; - interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioD_clk>; - }; - }; - - dbgu: serial@fffff200 { - compatible = "atmel,at91rm9200-dbgu", "atmel,at91rm9200-usart"; - reg = <0xfffff200 0x200>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_dbgu>; - clocks = <&mck>; - clock-names = "usart"; - status = "disabled"; - }; - - usart0: serial@fffc0000 { - compatible = "atmel,at91rm9200-usart"; - reg = <0xfffc0000 0x200>; - interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; - atmel,use-dma-rx; - atmel,use-dma-tx; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0>; - clocks = <&usart0_clk>; - clock-names = "usart"; - status = "disabled"; - }; - - usart1: serial@fffc4000 { - compatible = "atmel,at91rm9200-usart"; - reg = <0xfffc4000 0x200>; - interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; - atmel,use-dma-rx; - atmel,use-dma-tx; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - clocks = <&usart1_clk>; - clock-names = "usart"; - status = "disabled"; - }; - - usart2: serial@fffc8000 { - compatible = "atmel,at91rm9200-usart"; - reg = <0xfffc8000 0x200>; - interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; - atmel,use-dma-rx; - atmel,use-dma-tx; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - clocks = <&usart2_clk>; - clock-names = "usart"; - status = "disabled"; - }; - - usart3: serial@fffcc000 { - compatible = "atmel,at91rm9200-usart"; - reg = <0xfffcc000 0x200>; - interrupts = <23 IRQ_TYPE_LEVEL_HIGH 5>; - atmel,use-dma-rx; - atmel,use-dma-tx; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - clocks = <&usart3_clk>; - clock-names = "usart"; - status = "disabled"; - }; - - usb1: gadget@fffb0000 { - compatible = "atmel,at91rm9200-udc"; - reg = <0xfffb0000 0x4000>; - interrupts = <11 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&udc_clk>, <&udpck>; - clock-names = "pclk", "hclk"; - status = "disabled"; - }; - - spi0: spi@fffe0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "atmel,at91rm9200-spi"; - reg = <0xfffe0000 0x200>; - interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi0>; - clocks = <&spi0_clk>; - clock-names = "spi_clk"; - status = "disabled"; - }; - }; - - nand0: nand@40000000 { - compatible = "atmel,at91rm9200-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x40000000 0x10000000>; - atmel,nand-addr-offset = <21>; - atmel,nand-cmd-offset = <22>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nand>; - nand-ecc-mode = "soft"; - gpios = <&pioC 2 GPIO_ACTIVE_HIGH - 0 - &pioB 1 GPIO_ACTIVE_HIGH - >; - status = "disabled"; - }; - - usb0: ohci@300000 { - compatible = "atmel,at91rm9200-ohci", "usb-ohci"; - reg = <0x00300000 0x100000>; - interrupts = <23 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&ohci_clk>, <&ohci_clk>, <&uhpck>; - clock-names = "ohci_clk", "hclk", "uhpck"; - status = "disabled"; - }; - }; - - i2c-gpio-0 { - compatible = "i2c-gpio"; - gpios = <&pioA 25 GPIO_ACTIVE_HIGH /* sda */ - &pioA 26 GPIO_ACTIVE_HIGH /* scl */ - >; - i2c-gpio,sda-open-drain; - i2c-gpio,scl-open-drain; - i2c-gpio,delay-us = <2>; /* ~100 kHz */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_twi_gpio>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; -}; diff --git a/sys/gnu/dts/arm/at91rm9200_pqfp.dtsi b/sys/gnu/dts/arm/at91rm9200_pqfp.dtsi deleted file mode 100644 index c3d4177b982..00000000000 --- a/sys/gnu/dts/arm/at91rm9200_pqfp.dtsi +++ /dev/null @@ -1,16 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * at91rm9200_pqfp.dtsi - Device Tree Include file for AT91RM9200 PQFP family SoC - * - * Copyright (C) 2013 Jean-Christophe PLAGNIOL-VILLARD - */ - -#include "at91rm9200.dtsi" - -/ { - compatible = "atmel,at91rm9200-pqfp", "atmel,at91rm9200"; -}; - -&pioD { - status = "disabled"; -}; diff --git a/sys/gnu/dts/arm/at91rm9200ek.dts b/sys/gnu/dts/arm/at91rm9200ek.dts deleted file mode 100644 index 1e0bf5afa91..00000000000 --- a/sys/gnu/dts/arm/at91rm9200ek.dts +++ /dev/null @@ -1,147 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * at91rm9200ek.dts - Device Tree file for Atmel AT91RM9200 evaluation kit - * - * Copyright (C) 2012 Joachim Eastwood - */ -/dts-v1/; -#include "at91rm9200.dtsi" - -/ { - model = "Atmel AT91RM9200 evaluation kit"; - compatible = "atmel,at91rm9200ek", "atmel,at91rm9200"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - reg = <0x20000000 0x4000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <18432000>; - }; - }; - - ahb { - apb { - tcb0: timer@fffa0000 { - timer@0 { - compatible = "atmel,tcb-timer"; - reg = <0>, <1>; - }; - - timer@2 { - compatible = "atmel,tcb-timer"; - reg = <2>; - }; - }; - - usb1: gadget@fffb0000 { - atmel,vbus-gpio = <&pioD 4 GPIO_ACTIVE_HIGH>; - atmel,pullup-gpio = <&pioD 5 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - macb0: ethernet@fffbc000 { - phy-mode = "rmii"; - status = "okay"; - - phy0: ethernet-phy { - interrupt-parent = <&pioC>; - interrupts = <4 IRQ_TYPE_EDGE_BOTH>; - }; - }; - - usart1: serial@fffc4000 { - pinctrl-0 = - <&pinctrl_uart1 - &pinctrl_uart1_rts - &pinctrl_uart1_cts - &pinctrl_uart1_dtr_dsr - &pinctrl_uart1_dcd - &pinctrl_uart1_ri>; - status = "okay"; - }; - - spi0: spi@fffe0000 { - status = "okay"; - cs-gpios = <&pioA 3 0>, <0>, <0>, <0>; - mtd_dataflash@0 { - compatible = "atmel,at45", "atmel,dataflash"; - spi-max-frequency = <15000000>; - reg = <0>; - }; - }; - - dbgu: serial@fffff200 { - status = "okay"; - }; - - rtc: rtc@fffffe00 { - status = "okay"; - }; - }; - - usb0: ohci@300000 { - num-ports = <2>; - status = "okay"; - }; - - nor_flash@10000000 { - compatible = "cfi-flash"; - reg = <0x10000000 0x800000>; - linux,mtd-name = "physmap-flash.0"; - bank-width = <2>; - #address-cells = <1>; - #size-cells = <1>; - - barebox@0 { - label = "barebox"; - reg = <0x00000 0x40000>; - }; - - bareboxenv@40000 { - label = "bareboxenv"; - reg = <0x40000 0x10000>; - }; - - kernel@50000 { - label = "kernel"; - reg = <0x50000 0x300000>; - }; - - root@350000 { - label = "root"; - reg = <0x350000 0x4B0000>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - ds2 { - label = "green"; - gpios = <&pioB 0 GPIO_ACTIVE_LOW>; - linux,default-trigger = "mmc0"; - }; - - ds4 { - label = "yellow"; - gpios = <&pioB 1 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - }; - - ds6 { - label = "red"; - gpios = <&pioB 2 GPIO_ACTIVE_LOW>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/at91sam9260.dtsi b/sys/gnu/dts/arm/at91sam9260.dtsi deleted file mode 100644 index 6afbb48e7ff..00000000000 --- a/sys/gnu/dts/arm/at91sam9260.dtsi +++ /dev/null @@ -1,810 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * at91sam9260.dtsi - Device Tree Include file for AT91SAM9260 family SoC - * - * Copyright (C) 2011 Atmel, - * 2011 Nicolas Ferre , - * 2011 Jean-Christophe PLAGNIOL-VILLARD - */ - -#include -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - model = "Atmel AT91SAM9260 family SoC"; - compatible = "atmel,at91sam9260"; - interrupt-parent = <&aic>; - - aliases { - serial0 = &dbgu; - serial1 = &usart0; - serial2 = &usart1; - serial3 = &usart2; - serial4 = &usart3; - serial5 = &uart0; - serial6 = &uart1; - gpio0 = &pioA; - gpio1 = &pioB; - gpio2 = &pioC; - tcb0 = &tcb0; - tcb1 = &tcb1; - i2c0 = &i2c0; - ssc0 = &ssc0; - }; - cpus { - #address-cells = <0>; - #size-cells = <0>; - - cpu { - compatible = "arm,arm926ej-s"; - device_type = "cpu"; - }; - }; - - memory { - device_type = "memory"; - reg = <0x20000000 0x04000000>; - }; - - clocks { - slow_xtal: slow_xtal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - main_xtal: main_xtal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - adc_op_clk: adc_op_clk{ - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <5000000>; - }; - }; - - sram0: sram@2ff000 { - compatible = "mmio-sram"; - reg = <0x002ff000 0x2000>; - }; - - ahb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - apb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - aic: interrupt-controller@fffff000 { - #interrupt-cells = <3>; - compatible = "atmel,at91rm9200-aic"; - interrupt-controller; - reg = <0xfffff000 0x200>; - atmel,external-irqs = <29 30 31>; - }; - - ramc0: ramc@ffffea00 { - compatible = "atmel,at91sam9260-sdramc"; - reg = <0xffffea00 0x200>; - }; - - smc: smc@ffffec00 { - compatible = "atmel,at91sam9260-smc", "syscon"; - reg = <0xffffec00 0x200>; - }; - - matrix: matrix@ffffee00 { - compatible = "atmel,at91sam9260-matrix", "syscon"; - reg = <0xffffee00 0x200>; - }; - - pmc: pmc@fffffc00 { - compatible = "atmel,at91sam9260-pmc", "syscon"; - reg = <0xfffffc00 0x100>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - #clock-cells = <2>; - clocks = <&slow_xtal>, <&main_xtal>; - clock-names = "slow_xtal", "main_xtal"; - }; - - rstc@fffffd00 { - compatible = "atmel,at91sam9260-rstc"; - reg = <0xfffffd00 0x10>; - clocks = <&pmc PMC_TYPE_CORE PMC_SLOW>; - }; - - shdwc@fffffd10 { - compatible = "atmel,at91sam9260-shdwc"; - reg = <0xfffffd10 0x10>; - clocks = <&pmc PMC_TYPE_CORE PMC_SLOW>; - }; - - pit: timer@fffffd30 { - compatible = "atmel,at91sam9260-pit"; - reg = <0xfffffd30 0xf>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; - }; - - tcb0: timer@fffa0000 { - compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xfffa0000 0x100>; - interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0 - 18 IRQ_TYPE_LEVEL_HIGH 0 - 19 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&pmc PMC_TYPE_PERIPHERAL 18>, <&pmc PMC_TYPE_PERIPHERAL 19>, <&pmc PMC_TYPE_CORE PMC_SLOW>; - clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; - }; - - tcb1: timer@fffdc000 { - compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xfffdc000 0x100>; - interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0 - 27 IRQ_TYPE_LEVEL_HIGH 0 - 28 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 26>, <&pmc PMC_TYPE_PERIPHERAL 27>, <&pmc PMC_TYPE_PERIPHERAL 28>, <&pmc PMC_TYPE_CORE PMC_SLOW>; - clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; - }; - - pinctrl@fffff400 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "atmel,at91rm9200-pinctrl", "simple-bus"; - ranges = <0xfffff400 0xfffff400 0x600>; - - atmel,mux-mask = < - /* A B */ - 0xffffffff 0xffc00c3b /* pioA */ - 0xffffffff 0x7fff3ccf /* pioB */ - 0xffffffff 0x007fffff /* pioC */ - >; - - /* shared pinctrl settings */ - dbgu { - pinctrl_dbgu: dbgu-0 { - atmel,pins = - ; - }; - }; - - usart0 { - pinctrl_usart0: usart0-0 { - atmel,pins = - ; - }; - - pinctrl_usart0_rts: usart0_rts-0 { - atmel,pins = - ; /* PB26 periph A */ - }; - - pinctrl_usart0_cts: usart0_cts-0 { - atmel,pins = - ; /* PB27 periph A */ - }; - - pinctrl_usart0_dtr_dsr: usart0_dtr_dsr-0 { - atmel,pins = - ; /* PB22 periph A */ - }; - - pinctrl_usart0_dcd: usart0_dcd-0 { - atmel,pins = - ; /* PB23 periph A */ - }; - - pinctrl_usart0_ri: usart0_ri-0 { - atmel,pins = - ; /* PB25 periph A */ - }; - }; - - usart1 { - pinctrl_usart1: usart1-0 { - atmel,pins = - ; - }; - - pinctrl_usart1_rts: usart1_rts-0 { - atmel,pins = - ; /* PB28 periph A */ - }; - - pinctrl_usart1_cts: usart1_cts-0 { - atmel,pins = - ; /* PB29 periph A */ - }; - }; - - usart2 { - pinctrl_usart2: usart2-0 { - atmel,pins = - ; - }; - - pinctrl_usart2_rts: usart2_rts-0 { - atmel,pins = - ; /* PA4 periph A */ - }; - - pinctrl_usart2_cts: usart2_cts-0 { - atmel,pins = - ; /* PA5 periph A */ - }; - }; - - usart3 { - pinctrl_usart3: usart3-0 { - atmel,pins = - ; - }; - - pinctrl_usart3_rts: usart3_rts-0 { - atmel,pins = - ; - }; - - pinctrl_usart3_cts: usart3_cts-0 { - atmel,pins = - ; - }; - }; - - uart0 { - pinctrl_uart0: uart0-0 { - atmel,pins = - ; - }; - }; - - uart1 { - pinctrl_uart1: uart1-0 { - atmel,pins = - ; - }; - }; - - nand { - pinctrl_nand_rb: nand-rb-0 { - atmel,pins = - ; - }; - - pinctrl_nand_cs: nand-cs-0 { - atmel,pins = - ; - }; - }; - - macb { - pinctrl_macb_rmii: macb_rmii-0 { - atmel,pins = - ; /* PA21 periph A */ - }; - - pinctrl_macb_rmii_mii: macb_rmii_mii-0 { - atmel,pins = - ; /* PA29 periph B */ - }; - - pinctrl_macb_rmii_mii_alt: macb_rmii_mii-1 { - atmel,pins = - ; /* PA29 periph B */ - }; - }; - - mmc0 { - pinctrl_mmc0_clk: mmc0_clk-0 { - atmel,pins = - ; /* PA8 periph A */ - }; - - pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 { - atmel,pins = - ; /* PA6 periph A with pullup */ - }; - - pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { - atmel,pins = - ; /* PA11 periph A with pullup */ - }; - - pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 { - atmel,pins = - ; /* PA0 periph B with pullup */ - }; - - pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 { - atmel,pins = - ; /* PA3 periph B with pullup */ - }; - }; - - ssc0 { - pinctrl_ssc0_tx: ssc0_tx-0 { - atmel,pins = - ; /* PB18 periph A */ - }; - - pinctrl_ssc0_rx: ssc0_rx-0 { - atmel,pins = - ; /* PB21 periph A */ - }; - }; - - spi0 { - pinctrl_spi0: spi0-0 { - atmel,pins = - ; /* PA2 periph A SPI0_SPCK pin */ - }; - }; - - spi1 { - pinctrl_spi1: spi1-0 { - atmel,pins = - ; /* PB2 periph A SPI1_SPCK pin */ - }; - }; - - i2c_gpio0 { - pinctrl_i2c_gpio0: i2c_gpio0-0 { - atmel,pins = - ; - }; - }; - - tcb0 { - pinctrl_tcb0_tclk0: tcb0_tclk0-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tclk1: tcb0_tclk1-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tclk2: tcb0_tclk2-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tioa0: tcb0_tioa0-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tioa1: tcb0_tioa1-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tioa2: tcb0_tioa2-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tiob0: tcb0_tiob0-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tiob1: tcb0_tiob1-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tiob2: tcb0_tiob2-0 { - atmel,pins = ; - }; - }; - - tcb1 { - pinctrl_tcb1_tclk0: tcb1_tclk0-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tclk1: tcb1_tclk1-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tclk2: tcb1_tclk2-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tioa0: tcb1_tioa0-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tioa1: tcb1_tioa1-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tioa2: tcb1_tioa2-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tiob0: tcb1_tiob0-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tiob1: tcb1_tiob1-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tiob2: tcb1_tiob2-0 { - atmel,pins = ; - }; - }; - - pioA: gpio@fffff400 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff400 0x200>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; - }; - - pioB: gpio@fffff600 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff600 0x200>; - interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 3>; - }; - - pioC: gpio@fffff800 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff800 0x200>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 4>; - }; - }; - - dbgu: serial@fffff200 { - compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; - reg = <0xfffff200 0x200>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_dbgu>; - clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; - clock-names = "usart"; - status = "disabled"; - }; - - usart0: serial@fffb0000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xfffb0000 0x200>; - interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; - atmel,use-dma-rx; - atmel,use-dma-tx; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; - clock-names = "usart"; - status = "disabled"; - }; - - usart1: serial@fffb4000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xfffb4000 0x200>; - interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; - atmel,use-dma-rx; - atmel,use-dma-tx; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart1>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; - clock-names = "usart"; - status = "disabled"; - }; - - usart2: serial@fffb8000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xfffb8000 0x200>; - interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; - atmel,use-dma-rx; - atmel,use-dma-tx; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; - clock-names = "usart"; - status = "disabled"; - }; - - usart3: serial@fffd0000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xfffd0000 0x200>; - interrupts = <23 IRQ_TYPE_LEVEL_HIGH 5>; - atmel,use-dma-rx; - atmel,use-dma-tx; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart3>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; - clock-names = "usart"; - status = "disabled"; - }; - - uart0: serial@fffd4000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xfffd4000 0x200>; - interrupts = <24 IRQ_TYPE_LEVEL_HIGH 5>; - atmel,use-dma-rx; - atmel,use-dma-tx; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 24>; - clock-names = "usart"; - status = "disabled"; - }; - - uart1: serial@fffd8000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xfffd8000 0x200>; - interrupts = <25 IRQ_TYPE_LEVEL_HIGH 5>; - atmel,use-dma-rx; - atmel,use-dma-tx; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 25>; - clock-names = "usart"; - status = "disabled"; - }; - - macb0: ethernet@fffc4000 { - compatible = "cdns,at91sam9260-macb", "cdns,macb"; - reg = <0xfffc4000 0x100>; - interrupts = <21 IRQ_TYPE_LEVEL_HIGH 3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_macb_rmii>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 21>, <&pmc PMC_TYPE_PERIPHERAL 21>; - clock-names = "hclk", "pclk"; - status = "disabled"; - }; - - usb1: gadget@fffa4000 { - compatible = "atmel,at91sam9260-udc"; - reg = <0xfffa4000 0x4000>; - interrupts = <10 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 10>, <&pmc PMC_TYPE_SYSTEM 7>; - clock-names = "pclk", "hclk"; - status = "disabled"; - }; - - i2c0: i2c@fffac000 { - compatible = "atmel,at91sam9260-i2c"; - reg = <0xfffac000 0x100>; - interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; - status = "disabled"; - }; - - mmc0: mmc@fffa8000 { - compatible = "atmel,hsmci"; - reg = <0xfffa8000 0x600>; - interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; - clock-names = "mci_clk"; - status = "disabled"; - }; - - ssc0: ssc@fffbc000 { - compatible = "atmel,at91rm9200-ssc"; - reg = <0xfffbc000 0x4000>; - interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; - clock-names = "pclk"; - status = "disabled"; - }; - - spi0: spi@fffc8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "atmel,at91rm9200-spi"; - reg = <0xfffc8000 0x200>; - interrupts = <12 IRQ_TYPE_LEVEL_HIGH 3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 12>; - clock-names = "spi_clk"; - status = "disabled"; - }; - - spi1: spi@fffcc000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "atmel,at91rm9200-spi"; - reg = <0xfffcc000 0x200>; - interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; - clock-names = "spi_clk"; - status = "disabled"; - }; - - adc0: adc@fffe0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "atmel,at91sam9260-adc"; - reg = <0xfffe0000 0x100>; - interrupts = <5 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 5>, <&adc_op_clk>; - clock-names = "adc_clk", "adc_op_clk"; - atmel,adc-use-external-triggers; - atmel,adc-channels-used = <0xf>; - atmel,adc-vref = <3300>; - atmel,adc-startup-time = <15>; - atmel,adc-res = <8 10>; - atmel,adc-res-names = "lowres", "highres"; - atmel,adc-use-res = "highres"; - - trigger0 { - trigger-name = "timer-counter-0"; - trigger-value = <0x1>; - }; - trigger1 { - trigger-name = "timer-counter-1"; - trigger-value = <0x3>; - }; - - trigger2 { - trigger-name = "timer-counter-2"; - trigger-value = <0x5>; - }; - - trigger3 { - trigger-name = "external"; - trigger-value = <0xd>; - trigger-external; - }; - }; - - rtc@fffffd20 { - compatible = "atmel,at91sam9260-rtt"; - reg = <0xfffffd20 0x10>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&pmc PMC_TYPE_CORE PMC_SLOW>; - status = "disabled"; - }; - - watchdog: watchdog@fffffd40 { - compatible = "atmel,at91sam9260-wdt"; - reg = <0xfffffd40 0x10>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&pmc PMC_TYPE_CORE PMC_SLOW>; - atmel,watchdog-type = "hardware"; - atmel,reset-type = "all"; - atmel,dbg-halt; - status = "disabled"; - }; - - gpbr: syscon@fffffd50 { - compatible = "atmel,at91sam9260-gpbr", "syscon"; - reg = <0xfffffd50 0x10>; - status = "disabled"; - }; - }; - - usb0: ohci@500000 { - compatible = "atmel,at91rm9200-ohci", "usb-ohci"; - reg = <0x00500000 0x100000>; - interrupts = <20 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 20>, <&pmc PMC_TYPE_PERIPHERAL 20>, <&pmc PMC_TYPE_SYSTEM 6>; - clock-names = "ohci_clk", "hclk", "uhpck"; - status = "disabled"; - }; - - ebi: ebi@10000000 { - compatible = "atmel,at91sam9260-ebi"; - #address-cells = <2>; - #size-cells = <1>; - atmel,smc = <&smc>; - atmel,matrix = <&matrix>; - reg = <0x10000000 0x80000000>; - ranges = <0x0 0x0 0x10000000 0x10000000 - 0x1 0x0 0x20000000 0x10000000 - 0x2 0x0 0x30000000 0x10000000 - 0x3 0x0 0x40000000 0x10000000 - 0x4 0x0 0x50000000 0x10000000 - 0x5 0x0 0x60000000 0x10000000 - 0x6 0x0 0x70000000 0x10000000 - 0x7 0x0 0x80000000 0x10000000>; - clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; - status = "disabled"; - - nand_controller: nand-controller { - compatible = "atmel,at91sam9260-nand-controller"; - #address-cells = <2>; - #size-cells = <1>; - ranges; - status = "disabled"; - }; - }; - }; - - i2c_gpio0: i2c-gpio-0 { - compatible = "i2c-gpio"; - gpios = <&pioA 23 GPIO_ACTIVE_HIGH /* sda */ - &pioA 24 GPIO_ACTIVE_HIGH /* scl */ - >; - i2c-gpio,sda-open-drain; - i2c-gpio,scl-open-drain; - i2c-gpio,delay-us = <2>; /* ~100 kHz */ - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c_gpio0>; - status = "disabled"; - }; -}; diff --git a/sys/gnu/dts/arm/at91sam9260ek.dts b/sys/gnu/dts/arm/at91sam9260ek.dts deleted file mode 100644 index 81f808a1093..00000000000 --- a/sys/gnu/dts/arm/at91sam9260ek.dts +++ /dev/null @@ -1,186 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for Atmel at91sam9260 Evaluation Kit - * - * Copyright (C) 2016 Atmel, - * 2016 Nicolas Ferre - */ -/dts-v1/; -#include "at91sam9260.dtsi" - -/ { - model = "Atmel at91sam9260ek"; - compatible = "atmel,at91sam9260ek", "atmel,at91sam9260", "atmel,at91sam9"; - - chosen { - stdout-path = &dbgu; - }; - - memory { - reg = <0x20000000 0x4000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <18432000>; - }; - }; - - ahb { - apb { - tcb0: timer@fffa0000 { - timer@0 { - compatible = "atmel,tcb-timer"; - reg = <0>, <1>; - }; - - timer@2 { - compatible = "atmel,tcb-timer"; - reg = <2>; - }; - }; - - usb1: gadget@fffa4000 { - atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - mmc0: mmc@fffa8000 { - pinctrl-0 = < - &pinctrl_board_mmc0_slot1 - &pinctrl_mmc0_clk - &pinctrl_mmc0_slot1_cmd_dat0 - &pinctrl_mmc0_slot1_dat1_3>; - status = "okay"; - slot@1 { - reg = <1>; - bus-width = <4>; - cd-gpios = <&pioC 9 GPIO_ACTIVE_HIGH>; - }; - }; - - usart0: serial@fffb0000 { - pinctrl-0 = - <&pinctrl_usart0 - &pinctrl_usart0_rts - &pinctrl_usart0_cts - &pinctrl_usart0_dtr_dsr - &pinctrl_usart0_dcd - &pinctrl_usart0_ri>; - status = "okay"; - }; - - usart1: serial@fffb4000 { - status = "okay"; - }; - - ssc0: ssc@fffbc000 { - status = "okay"; - pinctrl-0 = <&pinctrl_ssc0_tx>; - }; - - macb0: ethernet@fffc4000 { - phy-mode = "rmii"; - status = "okay"; - }; - - spi0: spi@fffc8000 { - cs-gpios = <0>, <&pioC 11 0>, <0>, <0>; - mtd_dataflash@1 { - compatible = "atmel,at45", "atmel,dataflash"; - spi-max-frequency = <50000000>; - reg = <1>; - }; - }; - - dbgu: serial@fffff200 { - status = "okay"; - }; - - pinctrl@fffff400 { - board { - pinctrl_board_mmc0_slot1: mmc0_slot1-board { - atmel,pins = - ; - }; - }; - }; - - shdwc@fffffd10 { - atmel,wakeup-counter = <10>; - atmel,wakeup-rtt-timer; - }; - - rtc@fffffd20 { - atmel,rtt-rtc-time-reg = <&gpbr 0x0>; - status = "okay"; - }; - - watchdog@fffffd40 { - status = "okay"; - }; - - gpbr: syscon@fffffd50 { - status = "okay"; - }; - }; - - usb0: ohci@500000 { - num-ports = <2>; - status = "okay"; - }; - - nand0: nand@40000000 { - nand-bus-width = <8>; - nand-ecc-mode = "soft"; - nand-on-flash-bbt; - status = "okay"; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - - btn3 { - label = "Button 3"; - gpios = <&pioA 30 GPIO_ACTIVE_LOW>; - linux,code = <0x103>; - wakeup-source; - }; - - btn4 { - label = "Button 4"; - gpios = <&pioA 31 GPIO_ACTIVE_LOW>; - linux,code = <0x104>; - wakeup-source; - }; - }; - - i2c-gpio-0 { - status = "okay"; - - 24c512@50 { - compatible = "atmel,24c512"; - reg = <0x50>; - }; - }; - - leds { - compatible = "gpio-leds"; - - ds1 { - label = "ds1"; - gpios = <&pioA 9 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - - ds5 { - label = "ds5"; - gpios = <&pioA 6 GPIO_ACTIVE_LOW>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/at91sam9261.dtsi b/sys/gnu/dts/arm/at91sam9261.dtsi deleted file mode 100644 index 5ed3d745ac8..00000000000 --- a/sys/gnu/dts/arm/at91sam9261.dtsi +++ /dev/null @@ -1,658 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * at91sam9261.dtsi - Device Tree Include file for AT91SAM9261 SoC - * - * Copyright (C) 2013 Jean-Jacques Hiblot - */ - -#include -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - model = "Atmel AT91SAM9261 family SoC"; - compatible = "atmel,at91sam9261"; - interrupt-parent = <&aic>; - - aliases { - serial0 = &dbgu; - serial1 = &usart0; - serial2 = &usart1; - serial3 = &usart2; - gpio0 = &pioA; - gpio1 = &pioB; - gpio2 = &pioC; - tcb0 = &tcb0; - i2c0 = &i2c0; - ssc0 = &ssc0; - ssc1 = &ssc1; - ssc2 = &ssc2; - }; - - cpus { - #address-cells = <0>; - #size-cells = <0>; - - cpu { - compatible = "arm,arm926ej-s"; - device_type = "cpu"; - }; - }; - - memory { - device_type = "memory"; - reg = <0x20000000 0x08000000>; - }; - - clocks { - main_xtal: main_xtal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - slow_xtal: slow_xtal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - }; - - sram: sram@300000 { - compatible = "mmio-sram"; - reg = <0x00300000 0x28000>; - }; - - ahb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - usb0: ohci@500000 { - compatible = "atmel,at91rm9200-ohci", "usb-ohci"; - reg = <0x00500000 0x100000>; - interrupts = <20 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 20>, <&pmc PMC_TYPE_SYSTEM 16>, <&pmc PMC_TYPE_SYSTEM 6>; - clock-names = "ohci_clk", "hclk", "uhpck"; - status = "disabled"; - }; - - fb0: fb@600000 { - compatible = "atmel,at91sam9261-lcdc"; - reg = <0x00600000 0x1000>; - interrupts = <21 IRQ_TYPE_LEVEL_HIGH 3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fb>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 21>, <&pmc PMC_TYPE_SYSTEM 17>; - clock-names = "lcdc_clk", "hclk"; - status = "disabled"; - }; - - ebi: ebi@10000000 { - compatible = "atmel,at91sam9261-ebi"; - #address-cells = <2>; - #size-cells = <1>; - atmel,smc = <&smc>; - atmel,matrix = <&matrix>; - reg = <0x10000000 0x80000000>; - ranges = <0x0 0x0 0x10000000 0x10000000 - 0x1 0x0 0x20000000 0x10000000 - 0x2 0x0 0x30000000 0x10000000 - 0x3 0x0 0x40000000 0x10000000 - 0x4 0x0 0x50000000 0x10000000 - 0x5 0x0 0x60000000 0x10000000 - 0x6 0x0 0x70000000 0x10000000 - 0x7 0x0 0x80000000 0x10000000>; - clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; - status = "disabled"; - - nand_controller: nand-controller { - compatible = "atmel,at91sam9261-nand-controller"; - #address-cells = <2>; - #size-cells = <1>; - ranges; - status = "disabled"; - }; - }; - - apb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - tcb0: timer@fffa0000 { - compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xfffa0000 0x100>; - interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>, - <18 IRQ_TYPE_LEVEL_HIGH 0>, - <19 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&pmc PMC_TYPE_PERIPHERAL 18>, <&pmc PMC_TYPE_PERIPHERAL 19>, <&slow_xtal>; - clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; - }; - - usb1: gadget@fffa4000 { - compatible = "atmel,at91sam9261-udc"; - reg = <0xfffa4000 0x4000>; - interrupts = <10 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 10>, <&pmc PMC_TYPE_SYSTEM 7>; - clock-names = "pclk", "hclk"; - atmel,matrix = <&matrix>; - status = "disabled"; - }; - - mmc0: mmc@fffa8000 { - compatible = "atmel,hsmci"; - reg = <0xfffa8000 0x600>; - interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mmc0_clk>, <&pinctrl_mmc0_slot0_cmd_dat0>, <&pinctrl_mmc0_slot0_dat1_3>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; - clock-names = "mci_clk"; - status = "disabled"; - }; - - i2c0: i2c@fffac000 { - compatible = "atmel,at91sam9261-i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c_twi>; - reg = <0xfffac000 0x100>; - interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; - status = "disabled"; - }; - - usart0: serial@fffb0000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xfffb0000 0x200>; - interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; - atmel,use-dma-rx; - atmel,use-dma-tx; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; - clock-names = "usart"; - status = "disabled"; - }; - - usart1: serial@fffb4000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xfffb4000 0x200>; - interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; - atmel,use-dma-rx; - atmel,use-dma-tx; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart1>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; - clock-names = "usart"; - status = "disabled"; - }; - - usart2: serial@fffb8000{ - compatible = "atmel,at91sam9260-usart"; - reg = <0xfffb8000 0x200>; - interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; - atmel,use-dma-rx; - atmel,use-dma-tx; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; - clock-names = "usart"; - status = "disabled"; - }; - - ssc0: ssc@fffbc000 { - compatible = "atmel,at91rm9200-ssc"; - reg = <0xfffbc000 0x4000>; - interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; - clock-names = "pclk"; - status = "disabled"; - }; - - ssc1: ssc@fffc0000 { - compatible = "atmel,at91rm9200-ssc"; - reg = <0xfffc0000 0x4000>; - interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 15>; - clock-names = "pclk"; - status = "disabled"; - }; - - ssc2: ssc@fffc4000 { - compatible = "atmel,at91rm9200-ssc"; - reg = <0xfffc4000 0x4000>; - interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ssc2_tx &pinctrl_ssc2_rx>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 16>; - clock-names = "pclk"; - status = "disabled"; - }; - - spi0: spi@fffc8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "atmel,at91rm9200-spi"; - reg = <0xfffc8000 0x200>; - cs-gpios = <0>, <0>, <0>, <0>; - interrupts = <12 IRQ_TYPE_LEVEL_HIGH 3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 12>; - clock-names = "spi_clk"; - status = "disabled"; - }; - - spi1: spi@fffcc000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "atmel,at91rm9200-spi"; - reg = <0xfffcc000 0x200>; - interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; - clock-names = "spi_clk"; - status = "disabled"; - }; - - ramc: ramc@ffffea00 { - compatible = "atmel,at91sam9260-sdramc"; - reg = <0xffffea00 0x200>; - }; - - smc: smc@ffffec00 { - compatible = "atmel,at91sam9260-smc", "syscon"; - reg = <0xffffec00 0x200>; - }; - - matrix: matrix@ffffee00 { - compatible = "atmel,at91sam9261-matrix", "syscon"; - reg = <0xffffee00 0x200>; - }; - - aic: interrupt-controller@fffff000 { - #interrupt-cells = <3>; - compatible = "atmel,at91rm9200-aic"; - interrupt-controller; - reg = <0xfffff000 0x200>; - atmel,external-irqs = <29 30 31>; - }; - - dbgu: serial@fffff200 { - compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; - reg = <0xfffff200 0x200>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_dbgu>; - clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; - clock-names = "usart"; - status = "disabled"; - }; - - pinctrl@fffff400 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "atmel,at91rm9200-pinctrl", "simple-bus"; - ranges = <0xfffff400 0xfffff400 0x600>; - - atmel,mux-mask = - /* A B */ - <0xffffffff 0xfffffff7>, /* pioA */ - <0xffffffff 0xfffffff4>, /* pioB */ - <0xffffffff 0xffffff07>; /* pioC */ - - /* shared pinctrl settings */ - dbgu { - pinctrl_dbgu: dbgu-0 { - atmel,pins = - , - ; - }; - }; - - usart0 { - pinctrl_usart0: usart0-0 { - atmel,pins = - , - ; - }; - - pinctrl_usart0_rts: usart0_rts-0 { - atmel,pins = - ; - }; - - pinctrl_usart0_cts: usart0_cts-0 { - atmel,pins = - ; - }; - }; - - usart1 { - pinctrl_usart1: usart1-0 { - atmel,pins = - , - ; - }; - - pinctrl_usart1_rts: usart1_rts-0 { - atmel,pins = - ; - }; - - pinctrl_usart1_cts: usart1_cts-0 { - atmel,pins = - ; - }; - }; - - usart2 { - pinctrl_usart2: usart2-0 { - atmel,pins = - , - ; - }; - - pinctrl_usart2_rts: usart2_rts-0 { - atmel,pins = - ; - }; - - pinctrl_usart2_cts: usart2_cts-0 { - atmel,pins = - ; - }; - }; - - nand { - pinctrl_nand_rb: nand-rb-0 { - atmel,pins = - ; - }; - - pinctrl_nand_cs: nand-cs-0 { - atmel,pins = - ; - }; - }; - - mmc0 { - pinctrl_mmc0_clk: mmc0_clk-0 { - atmel,pins = - ; - }; - - pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 { - atmel,pins = - , - ; - }; - - pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { - atmel,pins = - , - , - ; - }; - }; - - ssc0 { - pinctrl_ssc0_tx: ssc0_tx-0 { - atmel,pins = - , - , - ; - }; - - pinctrl_ssc0_rx: ssc0_rx-0 { - atmel,pins = - , - , - ; - }; - }; - - ssc1 { - pinctrl_ssc1_tx: ssc1_tx-0 { - atmel,pins = - , - , - ; - }; - - pinctrl_ssc1_rx: ssc1_rx-0 { - atmel,pins = - , - , - ; - }; - }; - - ssc2 { - pinctrl_ssc2_tx: ssc2_tx-0 { - atmel,pins = - , - , - ; - }; - - pinctrl_ssc2_rx: ssc2_rx-0 { - atmel,pins = - , - , - ; - }; - }; - - spi0 { - pinctrl_spi0: spi0-0 { - atmel,pins = - , - , - ; - }; - }; - - spi1 { - pinctrl_spi1: spi1-0 { - atmel,pins = - , - , - ; - }; - }; - - tcb0 { - pinctrl_tcb0_tclk0: tcb0_tclk0-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tclk1: tcb0_tclk1-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tclk2: tcb0_tclk2-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tioa0: tcb0_tioa0-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tioa1: tcb0_tioa1-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tioa2: tcb0_tioa2-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tiob0: tcb0_tiob0-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tiob1: tcb0_tiob1-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tiob2: tcb0_tiob2-0 { - atmel,pins = ; - }; - }; - - i2c0 { - pinctrl_i2c_bitbang: i2c-0-bitbang { - atmel,pins = - , - ; - }; - pinctrl_i2c_twi: i2c-0-twi { - atmel,pins = - , - ; - }; - }; - - fb { - pinctrl_fb: fb-0 { - atmel,pins = - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - }; - }; - - pioA: gpio@fffff400 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff400 0x200>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; - }; - - pioB: gpio@fffff600 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff600 0x200>; - interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 3>; - }; - - pioC: gpio@fffff800 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff800 0x200>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 4>; - }; - }; - - pmc: pmc@fffffc00 { - compatible = "atmel,at91sam9261-pmc", "syscon"; - reg = <0xfffffc00 0x100>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - #clock-cells = <2>; - clocks = <&slow_xtal>, <&main_xtal>; - clock-names = "slow_xtal", "main_xtal"; - }; - - rstc@fffffd00 { - compatible = "atmel,at91sam9260-rstc"; - reg = <0xfffffd00 0x10>; - clocks = <&slow_xtal>; - }; - - shdwc@fffffd10 { - compatible = "atmel,at91sam9260-shdwc"; - reg = <0xfffffd10 0x10>; - clocks = <&slow_xtal>; - }; - - pit: timer@fffffd30 { - compatible = "atmel,at91sam9260-pit"; - reg = <0xfffffd30 0xf>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; - }; - - rtc@fffffd20 { - compatible = "atmel,at91sam9260-rtt"; - reg = <0xfffffd20 0x10>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&slow_xtal>; - status = "disabled"; - }; - - watchdog@fffffd40 { - compatible = "atmel,at91sam9260-wdt"; - reg = <0xfffffd40 0x10>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&slow_xtal>; - status = "disabled"; - }; - - gpbr: syscon@fffffd50 { - compatible = "atmel,at91sam9260-gpbr", "syscon"; - reg = <0xfffffd50 0x10>; - status = "disabled"; - }; - }; - }; - - i2c-gpio-0 { - compatible = "i2c-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c_bitbang>; - gpios = <&pioA 7 GPIO_ACTIVE_HIGH>, /* sda */ - <&pioA 8 GPIO_ACTIVE_HIGH>; /* scl */ - i2c-gpio,sda-open-drain; - i2c-gpio,scl-open-drain; - i2c-gpio,delay-us = <2>; /* ~100 kHz */ - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; -}; diff --git a/sys/gnu/dts/arm/at91sam9261ek.dts b/sys/gnu/dts/arm/at91sam9261ek.dts deleted file mode 100644 index c4ef74fea97..00000000000 --- a/sys/gnu/dts/arm/at91sam9261ek.dts +++ /dev/null @@ -1,241 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * at91sam9261ek.dts - Device Tree file for Atmel at91sam9261 reference board - * - * Copyright (C) 2013 Jean-Jacques Hiblot - */ -/dts-v1/; -#include "at91sam9261.dtsi" - -/ { - model = "Atmel at91sam9261ek"; - compatible = "atmel,at91sam9261ek", "atmel,at91sam9261", "atmel,at91sam9"; - - chosen { - bootargs = "rootfstype=ubifs ubi.mtd=5 root=ubi0:rootfs rw"; - stdout-path = "serial0:115200n8"; - }; - - memory { - reg = <0x20000000 0x4000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <18432000>; - }; - }; - - ahb { - usb0: ohci@500000 { - status = "okay"; - }; - - fb0: fb@600000 { - display = <&display0>; - atmel,power-control-gpio = <&pioA 12 GPIO_ACTIVE_LOW>; - status = "okay"; - - display0: panel { - bits-per-pixel = <16>; - atmel,lcdcon-backlight; - atmel,dmacon = <0x1>; - atmel,lcdcon2 = <0x80008002>; - atmel,guard-time = <1>; - atmel,lcd-wiring-mode = "BRG"; - - display-timings { - native-mode = <&timing0>; - timing0: timing0 { - clock-frequency = <4965000>; - hactive = <240>; - vactive = <320>; - hback-porch = <1>; - hfront-porch = <33>; - vback-porch = <1>; - vfront-porch = <0>; - hsync-len = <5>; - vsync-len = <1>; - hsync-active = <1>; - vsync-active = <1>; - }; - }; - }; - }; - - ebi: ebi@10000000 { - status = "okay"; - - nand_controller: nand-controller { - status = "okay"; - pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>; - pinctrl-names = "default"; - - nand@3 { - reg = <0x3 0x0 0x800000>; - rb-gpios = <&pioC 15 GPIO_ACTIVE_HIGH>; - cs-gpios = <&pioC 14 GPIO_ACTIVE_HIGH>; - nand-bus-width = <8>; - nand-ecc-mode = "soft"; - nand-on-flash-bbt; - label = "atmel_nand"; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - at91bootstrap@0 { - label = "at91bootstrap"; - reg = <0x0 0x40000>; - }; - - bootloader@40000 { - label = "bootloader"; - reg = <0x40000 0x80000>; - }; - - bootloaderenv@c0000 { - label = "bootloader env"; - reg = <0xc0000 0xc0000>; - }; - - dtb@180000 { - label = "device tree"; - reg = <0x180000 0x80000>; - }; - - kernel@200000 { - label = "kernel"; - reg = <0x200000 0x600000>; - }; - - rootfs@800000 { - label = "rootfs"; - reg = <0x800000 0x0f800000>; - }; - }; - }; - }; - }; - - apb { - tcb0: timer@fffa0000 { - timer0: timer@0 { - compatible = "atmel,tcb-timer"; - reg = <0>, <1>; - }; - - timer1: timer@2 { - compatible = "atmel,tcb-timer"; - reg = <2>; - }; - }; - - usb1: gadget@fffa4000 { - atmel,vbus-gpio = <&pioB 29 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - spi0: spi@fffc8000 { - cs-gpios = <&pioA 3 0>, <0>, <&pioA 28 0>, <0>; - status = "okay"; - - mtd_dataflash@0 { - compatible = "atmel,at45", "atmel,dataflash"; - reg = <0>; - spi-max-frequency = <15000000>; - }; - - tsc2046@2 { - reg = <2>; - compatible = "ti,ads7843"; - interrupts-extended = <&pioC 2 IRQ_TYPE_EDGE_BOTH>; - spi-max-frequency = <3000000>; - pendown-gpio = <&pioC 2 GPIO_ACTIVE_HIGH>; - - ti,x-min = /bits/ 16 <150>; - ti,x-max = /bits/ 16 <3830>; - ti,y-min = /bits/ 16 <190>; - ti,y-max = /bits/ 16 <3830>; - ti,vref-delay-usecs = /bits/ 16 <450>; - ti,x-plate-ohms = /bits/ 16 <450>; - ti,y-plate-ohms = /bits/ 16 <250>; - ti,pressure-max = /bits/ 16 <15000>; - ti,debounce-rep = /bits/ 16 <0>; - ti,debounce-tol = /bits/ 16 <65535>; - ti,debounce-max = /bits/ 16 <1>; - - wakeup-source; - }; - }; - - dbgu: serial@fffff200 { - status = "okay"; - }; - - watchdog@fffffd40 { - status = "okay"; - }; - - }; - }; - - leds { - compatible = "gpio-leds"; - - ds8 { - label = "ds8"; - gpios = <&pioA 13 GPIO_ACTIVE_LOW>; - linux,default-trigger = "none"; - }; - - ds7 { - label = "ds7"; - gpios = <&pioA 14 GPIO_ACTIVE_LOW>; - linux,default-trigger = "nand-disk"; - }; - - ds1 { - label = "ds1"; - gpios = <&pioA 23 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - - button_0 { - label = "button_0"; - gpios = <&pioA 27 GPIO_ACTIVE_LOW>; - linux,code = <256>; - wakeup-source; - }; - - button_1 { - label = "button_1"; - gpios = <&pioA 26 GPIO_ACTIVE_LOW>; - linux,code = <257>; - wakeup-source; - }; - - button_2 { - label = "button_2"; - gpios = <&pioA 25 GPIO_ACTIVE_LOW>; - linux,code = <258>; - wakeup-source; - }; - - button_3 { - label = "button_3"; - gpios = <&pioA 24 GPIO_ACTIVE_LOW>; - linux,code = <259>; - wakeup-source; - }; - }; -}; diff --git a/sys/gnu/dts/arm/at91sam9263.dtsi b/sys/gnu/dts/arm/at91sam9263.dtsi deleted file mode 100644 index 5c990cfae25..00000000000 --- a/sys/gnu/dts/arm/at91sam9263.dtsi +++ /dev/null @@ -1,829 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * at91sam9263.dtsi - Device Tree Include file for AT91SAM9263 family SoC - * - * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD - */ - -#include -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - model = "Atmel AT91SAM9263 family SoC"; - compatible = "atmel,at91sam9263"; - interrupt-parent = <&aic>; - - aliases { - serial0 = &dbgu; - serial1 = &usart0; - serial2 = &usart1; - serial3 = &usart2; - gpio0 = &pioA; - gpio1 = &pioB; - gpio2 = &pioC; - gpio3 = &pioD; - gpio4 = &pioE; - tcb0 = &tcb0; - i2c0 = &i2c0; - ssc0 = &ssc0; - ssc1 = &ssc1; - pwm0 = &pwm0; - }; - - cpus { - #address-cells = <0>; - #size-cells = <0>; - - cpu { - compatible = "arm,arm926ej-s"; - device_type = "cpu"; - }; - }; - - memory { - device_type = "memory"; - reg = <0x20000000 0x08000000>; - }; - - clocks { - main_xtal: main_xtal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - slow_xtal: slow_xtal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - }; - - sram0: sram@300000 { - compatible = "mmio-sram"; - reg = <0x00300000 0x14000>; - }; - - sram1: sram@500000 { - compatible = "mmio-sram"; - reg = <0x00500000 0x4000>; - }; - - ahb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - apb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - aic: interrupt-controller@fffff000 { - #interrupt-cells = <3>; - compatible = "atmel,at91rm9200-aic"; - interrupt-controller; - reg = <0xfffff000 0x200>; - atmel,external-irqs = <30 31>; - }; - - pmc: pmc@fffffc00 { - compatible = "atmel,at91sam9263-pmc", "syscon"; - reg = <0xfffffc00 0x100>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - #clock-cells = <2>; - clocks = <&slow_xtal>, <&main_xtal>; - clock-names = "slow_xtal", "main_xtal"; - }; - - ramc0: ramc@ffffe200 { - compatible = "atmel,at91sam9260-sdramc"; - reg = <0xffffe200 0x200>; - }; - - smc0: smc@ffffe400 { - compatible = "atmel,at91sam9260-smc", "syscon"; - reg = <0xffffe400 0x200>; - }; - - ramc1: ramc@ffffe800 { - compatible = "atmel,at91sam9260-sdramc"; - reg = <0xffffe800 0x200>; - }; - - smc1: smc@ffffea00 { - compatible = "atmel,at91sam9260-smc", "syscon"; - reg = <0xffffea00 0x200>; - }; - - matrix: matrix@ffffec00 { - compatible = "atmel,at91sam9263-matrix", "syscon"; - reg = <0xffffec00 0x200>; - }; - - pit: timer@fffffd30 { - compatible = "atmel,at91sam9260-pit"; - reg = <0xfffffd30 0xf>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; - }; - - tcb0: timer@fff7c000 { - compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xfff7c000 0x100>; - interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 19>, <&slow_xtal>; - clock-names = "t0_clk", "slow_clk"; - }; - - rstc@fffffd00 { - compatible = "atmel,at91sam9260-rstc"; - reg = <0xfffffd00 0x10>; - clocks = <&slow_xtal>; - }; - - shdwc@fffffd10 { - compatible = "atmel,at91sam9260-shdwc"; - reg = <0xfffffd10 0x10>; - clocks = <&slow_xtal>; - }; - - pinctrl@fffff200 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "atmel,at91rm9200-pinctrl", "simple-bus"; - ranges = <0xfffff200 0xfffff200 0xa00>; - - atmel,mux-mask = < - /* A B */ - 0xfffffffb 0xffffe07f /* pioA */ - 0x0007ffff 0x39072fff /* pioB */ - 0xffffffff 0x3ffffff8 /* pioC */ - 0xfffffbff 0xffffffff /* pioD */ - 0xffe00fff 0xfbfcff00 /* pioE */ - >; - - /* shared pinctrl settings */ - dbgu { - pinctrl_dbgu: dbgu-0 { - atmel,pins = - ; - }; - }; - - usart0 { - pinctrl_usart0: usart0-0 { - atmel,pins = - ; - }; - - pinctrl_usart0_rts: usart0_rts-0 { - atmel,pins = - ; /* PA28 periph A */ - }; - - pinctrl_usart0_cts: usart0_cts-0 { - atmel,pins = - ; /* PA29 periph A */ - }; - }; - - usart1 { - pinctrl_usart1: usart1-0 { - atmel,pins = - ; - }; - - pinctrl_usart1_rts: usart1_rts-0 { - atmel,pins = - ; /* PD7 periph B */ - }; - - pinctrl_usart1_cts: usart1_cts-0 { - atmel,pins = - ; /* PD8 periph B */ - }; - }; - - usart2 { - pinctrl_usart2: usart2-0 { - atmel,pins = - ; - }; - - pinctrl_usart2_rts: usart2_rts-0 { - atmel,pins = - ; /* PD5 periph B */ - }; - - pinctrl_usart2_cts: usart2_cts-0 { - atmel,pins = - ; /* PD6 periph B */ - }; - }; - - nand { - pinctrl_nand_rb: nand-rb-0 { - atmel,pins = - ; - }; - - pinctrl_nand_cs: nand-cs-0 { - atmel,pins = - ; - }; - }; - - macb { - pinctrl_macb_rmii: macb_rmii-0 { - atmel,pins = - ; /* PE30 periph A */ - }; - - pinctrl_macb_rmii_mii: macb_rmii_mii-0 { - atmel,pins = - ; /* PE22 periph B */ - }; - }; - - mmc0 { - pinctrl_mmc0_clk: mmc0_clk-0 { - atmel,pins = - ; /* PA12 periph A */ - }; - - pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 { - atmel,pins = - ; /* PA0 periph A with pullup */ - }; - - pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { - atmel,pins = - ; /* PA5 periph A with pullup */ - }; - - pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 { - atmel,pins = - ; /* PA17 periph A with pullup */ - }; - - pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 { - atmel,pins = - ; /* PA20 periph A with pullup */ - }; - }; - - mmc1 { - pinctrl_mmc1_clk: mmc1_clk-0 { - atmel,pins = - ; /* PA6 periph A */ - }; - - pinctrl_mmc1_slot0_cmd_dat0: mmc1_slot0_cmd_dat0-0 { - atmel,pins = - ; /* PA8 periph A with pullup */ - }; - - pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 { - atmel,pins = - ; /* PA11 periph A with pullup */ - }; - - pinctrl_mmc1_slot1_cmd_dat0: mmc1_slot1_cmd_dat0-0 { - atmel,pins = - ; /* PA22 periph A with pullup */ - }; - - pinctrl_mmc1_slot1_dat1_3: mmc1_slot1_dat1_3-0 { - atmel,pins = - ; /* PA25 periph A with pullup */ - }; - }; - - ssc0 { - pinctrl_ssc0_tx: ssc0_tx-0 { - atmel,pins = - ; /* PB2 periph B */ - }; - - pinctrl_ssc0_rx: ssc0_rx-0 { - atmel,pins = - ; /* PB5 periph B */ - }; - }; - - ssc1 { - pinctrl_ssc1_tx: ssc1_tx-0 { - atmel,pins = - ; /* PB8 periph A */ - }; - - pinctrl_ssc1_rx: ssc1_rx-0 { - atmel,pins = - ; /* PB11 periph A */ - }; - }; - - spi0 { - pinctrl_spi0: spi0-0 { - atmel,pins = - ; /* PA2 periph B SPI0_SPCK pin */ - }; - }; - - spi1 { - pinctrl_spi1: spi1-0 { - atmel,pins = - ; /* PB14 periph A SPI1_SPCK pin */ - }; - }; - - tcb0 { - pinctrl_tcb0_tclk0: tcb0_tclk0-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tclk1: tcb0_tclk1-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tclk2: tcb0_tclk2-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tioa0: tcb0_tioa0-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tioa1: tcb0_tioa1-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tioa2: tcb0_tioa2-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tiob0: tcb0_tiob0-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tiob1: tcb0_tiob1-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tiob2: tcb0_tiob2-0 { - atmel,pins = ; - }; - }; - - fb { - pinctrl_fb: fb-0 { - atmel,pins = - ; /* PC27 periph A */ - }; - }; - - can { - pinctrl_can_rx_tx: can_rx_tx { - atmel,pins = - ; /* CANTX, conflicts with PCK0 */ - }; - }; - - ac97 { - pinctrl_ac97: ac97-0 { - atmel,pins = - ; /* PB14 periph A AC97RX pin */ - }; - }; - - pioA: gpio@fffff200 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff200 0x200>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; - }; - - pioB: gpio@fffff400 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff400 0x200>; - interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 3>; - }; - - pioC: gpio@fffff600 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff600 0x200>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 4>; - }; - - pioD: gpio@fffff800 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff800 0x200>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 4>; - }; - - pioE: gpio@fffffa00 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffffa00 0x200>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 4>; - }; - }; - - dbgu: serial@ffffee00 { - compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; - reg = <0xffffee00 0x200>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_dbgu>; - clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; - clock-names = "usart"; - status = "disabled"; - }; - - usart0: serial@fff8c000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xfff8c000 0x200>; - interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; - atmel,use-dma-rx; - atmel,use-dma-tx; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; - clock-names = "usart"; - status = "disabled"; - }; - - usart1: serial@fff90000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xfff90000 0x200>; - interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; - atmel,use-dma-rx; - atmel,use-dma-tx; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart1>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; - clock-names = "usart"; - status = "disabled"; - }; - - usart2: serial@fff94000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xfff94000 0x200>; - interrupts = <9 IRQ_TYPE_LEVEL_HIGH 5>; - atmel,use-dma-rx; - atmel,use-dma-tx; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; - clock-names = "usart"; - status = "disabled"; - }; - - ssc0: ssc@fff98000 { - compatible = "atmel,at91rm9200-ssc"; - reg = <0xfff98000 0x4000>; - interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 16>; - clock-names = "pclk"; - status = "disabled"; - }; - - ssc1: ssc@fff9c000 { - compatible = "atmel,at91rm9200-ssc"; - reg = <0xfff9c000 0x4000>; - interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 17>; - clock-names = "pclk"; - status = "disabled"; - }; - - ac97: sound@fffa0000 { - compatible = "atmel,at91sam9263-ac97c"; - reg = <0xfffa0000 0x4000>; - interrupts = <18 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ac97>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 18>; - clock-names = "ac97_clk"; - status = "disabled"; - }; - - macb0: ethernet@fffbc000 { - compatible = "cdns,at91sam9260-macb", "cdns,macb"; - reg = <0xfffbc000 0x100>; - interrupts = <21 IRQ_TYPE_LEVEL_HIGH 3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_macb_rmii>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 21>, <&pmc PMC_TYPE_PERIPHERAL 21>; - clock-names = "hclk", "pclk"; - status = "disabled"; - }; - - usb1: gadget@fff78000 { - compatible = "atmel,at91sam9263-udc"; - reg = <0xfff78000 0x4000>; - interrupts = <24 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 24>, <&pmc PMC_TYPE_SYSTEM 7>; - clock-names = "pclk", "hclk"; - status = "disabled"; - }; - - i2c0: i2c@fff88000 { - compatible = "atmel,at91sam9260-i2c"; - reg = <0xfff88000 0x100>; - interrupts = <13 IRQ_TYPE_LEVEL_HIGH 6>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; - status = "disabled"; - }; - - mmc0: mmc@fff80000 { - compatible = "atmel,hsmci"; - reg = <0xfff80000 0x600>; - interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; - clock-names = "mci_clk"; - status = "disabled"; - }; - - mmc1: mmc@fff84000 { - compatible = "atmel,hsmci"; - reg = <0xfff84000 0x600>; - interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; - clock-names = "mci_clk"; - status = "disabled"; - }; - - watchdog@fffffd40 { - compatible = "atmel,at91sam9260-wdt"; - reg = <0xfffffd40 0x10>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&slow_xtal>; - atmel,watchdog-type = "hardware"; - atmel,reset-type = "all"; - atmel,dbg-halt; - status = "disabled"; - }; - - spi0: spi@fffa4000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "atmel,at91rm9200-spi"; - reg = <0xfffa4000 0x200>; - interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; - clock-names = "spi_clk"; - status = "disabled"; - }; - - spi1: spi@fffa8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "atmel,at91rm9200-spi"; - reg = <0xfffa8000 0x200>; - interrupts = <15 IRQ_TYPE_LEVEL_HIGH 3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 15>; - clock-names = "spi_clk"; - status = "disabled"; - }; - - pwm0: pwm@fffb8000 { - compatible = "atmel,at91sam9rl-pwm"; - reg = <0xfffb8000 0x300>; - interrupts = <20 IRQ_TYPE_LEVEL_HIGH 4>; - #pwm-cells = <3>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; - clock-names = "pwm_clk"; - status = "disabled"; - }; - - can: can@fffac000 { - compatible = "atmel,at91sam9263-can"; - reg = <0xfffac000 0x300>; - interrupts = <12 IRQ_TYPE_LEVEL_HIGH 3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can_rx_tx>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 12>; - clock-names = "can_clk"; - }; - - rtc@fffffd20 { - compatible = "atmel,at91sam9260-rtt"; - reg = <0xfffffd20 0x10>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&slow_xtal>; - status = "disabled"; - }; - - rtc@fffffd50 { - compatible = "atmel,at91sam9260-rtt"; - reg = <0xfffffd50 0x10>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&slow_xtal>; - status = "disabled"; - }; - - gpbr: syscon@fffffd60 { - compatible = "atmel,at91sam9260-gpbr", "syscon"; - reg = <0xfffffd60 0x50>; - status = "disabled"; - }; - }; - - fb0: fb@700000 { - compatible = "atmel,at91sam9263-lcdc"; - reg = <0x00700000 0x1000>; - interrupts = <26 IRQ_TYPE_LEVEL_HIGH 3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fb>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 26>, <&pmc PMC_TYPE_PERIPHERAL 26>; - clock-names = "lcdc_clk", "hclk"; - status = "disabled"; - }; - - usb0: ohci@a00000 { - compatible = "atmel,at91rm9200-ohci", "usb-ohci"; - reg = <0x00a00000 0x100000>; - interrupts = <29 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 29>, <&pmc PMC_TYPE_PERIPHERAL 29>, <&pmc PMC_TYPE_SYSTEM 6>; - clock-names = "ohci_clk", "hclk", "uhpck"; - status = "disabled"; - }; - - ebi0: ebi@10000000 { - compatible = "atmel,at91sam9263-ebi0"; - #address-cells = <2>; - #size-cells = <1>; - atmel,smc = <&smc0>; - atmel,matrix = <&matrix>; - reg = <0x10000000 0x80000000>; - ranges = <0x0 0x0 0x10000000 0x10000000 - 0x1 0x0 0x20000000 0x10000000 - 0x2 0x0 0x30000000 0x10000000 - 0x3 0x0 0x40000000 0x10000000 - 0x4 0x0 0x50000000 0x10000000 - 0x5 0x0 0x60000000 0x10000000>; - clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; - status = "disabled"; - - nand_controller0: nand-controller { - compatible = "atmel,at91sam9260-nand-controller"; - #address-cells = <2>; - #size-cells = <1>; - ranges; - status = "disabled"; - }; - }; - - ebi1: ebi@70000000 { - compatible = "atmel,at91sam9263-ebi1"; - #address-cells = <2>; - #size-cells = <1>; - atmel,smc = <&smc1>; - atmel,matrix = <&matrix>; - reg = <0x80000000 0x20000000>; - ranges = <0x0 0x0 0x80000000 0x10000000 - 0x1 0x0 0x90000000 0x10000000>; - clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; - status = "disabled"; - - nand_controller1: nand-controller { - compatible = "atmel,at91sam9260-nand-controller"; - #address-cells = <2>; - #size-cells = <1>; - ranges; - status = "disabled"; - }; - }; - }; - - i2c-gpio-0 { - compatible = "i2c-gpio"; - gpios = <&pioB 4 GPIO_ACTIVE_HIGH /* sda */ - &pioB 5 GPIO_ACTIVE_HIGH /* scl */ - >; - i2c-gpio,sda-open-drain; - i2c-gpio,scl-open-drain; - i2c-gpio,delay-us = <2>; /* ~100 kHz */ - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; -}; diff --git a/sys/gnu/dts/arm/at91sam9263ek.dts b/sys/gnu/dts/arm/at91sam9263ek.dts deleted file mode 100644 index 62d218542a4..00000000000 --- a/sys/gnu/dts/arm/at91sam9263ek.dts +++ /dev/null @@ -1,257 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * at91sam9263ek.dts - Device Tree file for Atmel at91sam9263 reference board - * - * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD - */ -/dts-v1/; -#include "at91sam9263.dtsi" - -/ { - model = "Atmel at91sam9263ek"; - compatible = "atmel,at91sam9263ek", "atmel,at91sam9263", "atmel,at91sam9"; - - chosen { - bootargs = "mem=64M root=/dev/mtdblock5 rw rootfstype=ubifs"; - stdout-path = "serial0:115200n8"; - }; - - memory { - reg = <0x20000000 0x4000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <16367660>; - }; - }; - - ahb { - apb { - dbgu: serial@ffffee00 { - status = "okay"; - }; - - tcb0: timer@fff7c000 { - timer@0 { - compatible = "atmel,tcb-timer"; - reg = <0>, <1>; - }; - - timer@2 { - compatible = "atmel,tcb-timer"; - reg = <2>; - }; - }; - - usart0: serial@fff8c000 { - pinctrl-0 = < - &pinctrl_usart0 - &pinctrl_usart0_rts - &pinctrl_usart0_cts>; - status = "okay"; - }; - - macb0: ethernet@fffbc000 { - phy-mode = "rmii"; - status = "okay"; - }; - - usb1: gadget@fff78000 { - atmel,vbus-gpio = <&pioA 25 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - mmc0: mmc@fff80000 { - pinctrl-0 = < - &pinctrl_board_mmc0 - &pinctrl_mmc0_clk - &pinctrl_mmc0_slot0_cmd_dat0 - &pinctrl_mmc0_slot0_dat1_3>; - status = "okay"; - slot@0 { - reg = <0>; - bus-width = <4>; - cd-gpios = <&pioE 18 GPIO_ACTIVE_HIGH>; - wp-gpios = <&pioE 19 GPIO_ACTIVE_HIGH>; - }; - }; - - pinctrl@fffff200 { - mmc0 { - pinctrl_board_mmc0: mmc0-board { - atmel,pins = - ; /* PE19 gpio WP pin pull up */ - }; - }; - }; - - spi0: spi@fffa4000 { - status = "okay"; - cs-gpios = <&pioA 5 0>, <0>, <0>, <0>; - mtd_dataflash@0 { - compatible = "atmel,at45", "atmel,dataflash"; - spi-max-frequency = <50000000>; - reg = <0>; - }; - }; - - watchdog@fffffd40 { - status = "okay"; - }; - }; - - fb0: fb@700000 { - display = <&display0>; - status = "okay"; - - display0: panel { - bits-per-pixel = <16>; - atmel,lcdcon-backlight; - atmel,dmacon = <0x1>; - atmel,lcdcon2 = <0x80008002>; - atmel,guard-time = <1>; - - display-timings { - native-mode = <&timing0>; - timing0: timing0 { - clock-frequency = <4965000>; - hactive = <240>; - vactive = <320>; - hback-porch = <1>; - hfront-porch = <33>; - vback-porch = <1>; - vfront-porch = <0>; - hsync-len = <5>; - vsync-len = <1>; - hsync-active = <1>; - vsync-active = <1>; - }; - }; - }; - }; - - ebi0: ebi@10000000 { - status = "okay"; - - nand_controller: nand-controller { - status = "okay"; - pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>; - pinctrl-names = "default"; - - nand@3 { - reg = <0x3 0x0 0x800000>; - rb-gpios = <&pioA 22 GPIO_ACTIVE_HIGH>; - cs-gpios = <&pioA 15 GPIO_ACTIVE_HIGH>; - nand-bus-width = <8>; - nand-ecc-mode = "soft"; - nand-on-flash-bbt; - label = "atmel_nand"; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - at91bootstrap@0 { - label = "at91bootstrap"; - reg = <0x0 0x20000>; - }; - - barebox@20000 { - label = "barebox"; - reg = <0x20000 0x40000>; - }; - - bareboxenv@60000 { - label = "bareboxenv"; - reg = <0x60000 0x20000>; - }; - - bareboxenv2@80000 { - label = "bareboxenv2"; - reg = <0x80000 0x20000>; - }; - - oftree@80000 { - label = "oftree"; - reg = <0xa0000 0x20000>; - }; - - kernel@a0000 { - label = "kernel"; - reg = <0xc0000 0x400000>; - }; - - rootfs@4a0000 { - label = "rootfs"; - reg = <0x4c0000 0x7800000>; - }; - - data@7ca0000 { - label = "data"; - reg = <0x7cc0000 0x8340000>; - }; - }; - }; - }; - }; - - usb0: ohci@a00000 { - num-ports = <2>; - status = "okay"; - atmel,vbus-gpio = <&pioA 24 GPIO_ACTIVE_HIGH - &pioA 21 GPIO_ACTIVE_HIGH - >; - }; - }; - - leds { - compatible = "gpio-leds"; - - d3 { - label = "d3"; - gpios = <&pioB 7 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - - d2 { - label = "d2"; - gpios = <&pioC 29 GPIO_ACTIVE_LOW>; - linux,default-trigger = "nand-disk"; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - - left_click { - label = "left_click"; - gpios = <&pioC 5 GPIO_ACTIVE_LOW>; - linux,code = <272>; - wakeup-source; - }; - - right_click { - label = "right_click"; - gpios = <&pioC 4 GPIO_ACTIVE_LOW>; - linux,code = <273>; - wakeup-source; - }; - }; - - i2c-gpio-0 { - status = "okay"; - - 24c512@50 { - compatible = "atmel,24c512"; - reg = <0x50>; - pagesize = <128>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/at91sam9g15.dtsi b/sys/gnu/dts/arm/at91sam9g15.dtsi deleted file mode 100644 index dde88276fe5..00000000000 --- a/sys/gnu/dts/arm/at91sam9g15.dtsi +++ /dev/null @@ -1,28 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * at91sam9g15.dtsi - Device Tree Include file for AT91SAM9G15 SoC - * - * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD - */ - -#include "at91sam9x5.dtsi" -#include "at91sam9x5_lcd.dtsi" - -/ { - model = "Atmel AT91SAM9G15 SoC"; - compatible = "atmel,at91sam9g15", "atmel,at91sam9x5"; -}; - -&pinctrl { - atmel,mux-mask = < - /* A B C */ - 0xffffffff 0xffe0399f 0x00000000 /* pioA */ - 0x00040000 0x00047e3f 0x00000000 /* pioB */ - 0xfdffffff 0x00000000 0xb83fffff /* pioC */ - 0x003fffff 0x003f8000 0x00000000 /* pioD */ - >; -}; - -&pmc { - compatible = "atmel,at91sam9g15-pmc", "atmel,at91sam9x5-pmc", "syscon"; -}; diff --git a/sys/gnu/dts/arm/at91sam9g15ek.dts b/sys/gnu/dts/arm/at91sam9g15ek.dts deleted file mode 100644 index 889a5097eb2..00000000000 --- a/sys/gnu/dts/arm/at91sam9g15ek.dts +++ /dev/null @@ -1,36 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * at91sam9g15ek.dts - Device Tree file for AT91SAM9G15-EK board - * - * Copyright (C) 2012 Atmel, - * 2012 Nicolas Ferre - */ -/dts-v1/; -#include "at91sam9g15.dtsi" -#include "at91sam9x5dm.dtsi" -#include "at91sam9x5ek.dtsi" - -/ { - model = "Atmel AT91SAM9G15-EK"; - compatible = "atmel,at91sam9g15ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9"; - - backlight: backlight { - status = "okay"; - }; - - bl_reg: backlight_regulator { - status = "okay"; - }; - - panel: panel { - status = "okay"; - }; - - panel_reg: panel_regulator { - status = "okay"; - }; -}; - -&hlcdc { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/at91sam9g20.dtsi b/sys/gnu/dts/arm/at91sam9g20.dtsi deleted file mode 100644 index 4117cf88050..00000000000 --- a/sys/gnu/dts/arm/at91sam9g20.dtsi +++ /dev/null @@ -1,46 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * at91sam9g20.dtsi - Device Tree Include file for AT91SAM9G20 family SoC - * - * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD - */ - -#include "at91sam9260.dtsi" - -/ { - model = "Atmel AT91SAM9G20 family SoC"; - compatible = "atmel,at91sam9g20"; - - memory { - reg = <0x20000000 0x08000000>; - }; - - sram0: sram@2ff000 { - status = "disabled"; - }; - - sram1: sram@2fc000 { - compatible = "mmio-sram"; - reg = <0x002fc000 0x8000>; - }; - - ahb { - apb { - i2c0: i2c@fffac000 { - compatible = "atmel,at91sam9g20-i2c"; - }; - - ssc0: ssc@fffbc000 { - compatible = "atmel,at91sam9rl-ssc"; - }; - - adc0: adc@fffe0000 { - atmel,adc-startup-time = <40>; - }; - - pmc: pmc@fffffc00 { - compatible = "atmel,at91sam9g20-pmc", "atmel,at91sam9260-pmc", "syscon"; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/at91sam9g20ek.dts b/sys/gnu/dts/arm/at91sam9g20ek.dts deleted file mode 100644 index 6de7a7cd3c0..00000000000 --- a/sys/gnu/dts/arm/at91sam9g20ek.dts +++ /dev/null @@ -1,28 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * at91sam9g20ek.dts - Device Tree file for Atmel at91sam9g20ek board - * - * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD - */ -/dts-v1/; -#include "at91sam9g20ek_common.dtsi" - -/ { - model = "Atmel at91sam9g20ek"; - compatible = "atmel,at91sam9g20ek", "atmel,at91sam9g20", "atmel,at91sam9"; - - leds { - compatible = "gpio-leds"; - - ds1 { - label = "ds1"; - gpios = <&pioA 9 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - - ds5 { - label = "ds5"; - gpios = <&pioA 6 GPIO_ACTIVE_LOW>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/at91sam9g20ek_2mmc.dts b/sys/gnu/dts/arm/at91sam9g20ek_2mmc.dts deleted file mode 100644 index 2db95e8ffc6..00000000000 --- a/sys/gnu/dts/arm/at91sam9g20ek_2mmc.dts +++ /dev/null @@ -1,54 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * at91sam9g20ek_2mmc.dts - Device Tree file for Atmel at91sam9g20ek 2 MMC board - * - * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD - */ -/dts-v1/; -#include "at91sam9g20ek_common.dtsi" - -/ { - model = "Atmel at91sam9g20ek 2 mmc"; - compatible = "atmel,at91sam9g20ek_2mmc", "atmel,at91sam9g20", "atmel,at91sam9"; - - ahb { - apb{ - mmc0: mmc@fffa8000 { - /* clk already mux wuth slot0 */ - pinctrl-0 = < - &pinctrl_board_mmc0_slot0 - &pinctrl_mmc0_slot0_cmd_dat0 - &pinctrl_mmc0_slot0_dat1_3>; - slot@0 { - reg = <0>; - bus-width = <4>; - cd-gpios = <&pioC 2 GPIO_ACTIVE_HIGH>; - }; - }; - - pinctrl@fffff400 { - mmc0_slot0 { - pinctrl_board_mmc0_slot0: mmc0_slot0-board { - atmel,pins = - ; /* PC2 gpio CD pin pull up and deglitch */ - }; - }; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - ds1 { - label = "ds1"; - gpios = <&pioB 9 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - - ds5 { - label = "ds5"; - gpios = <&pioB 8 GPIO_ACTIVE_LOW>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/at91sam9g20ek_common.dtsi b/sys/gnu/dts/arm/at91sam9g20ek_common.dtsi deleted file mode 100644 index bda22700110..00000000000 --- a/sys/gnu/dts/arm/at91sam9g20ek_common.dtsi +++ /dev/null @@ -1,255 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * at91sam9g20ek_common.dtsi - Device Tree file for Atmel at91sam9g20ek board - * - * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD - */ -#include "at91sam9g20.dtsi" - -/ { - - chosen { - bootargs = "mem=64M root=/dev/mtdblock5 rw rootfstype=ubifs"; - stdout-path = "serial0:115200n8"; - }; - - memory { - reg = <0x20000000 0x4000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <18432000>; - }; - }; - - ahb { - apb { - pinctrl@fffff400 { - board { - pinctrl_pck0_as_mck: pck0_as_mck { - atmel,pins = - ; /* PC1 periph B */ - }; - - }; - - mmc0_slot1 { - pinctrl_board_mmc0_slot1: mmc0_slot1-board { - atmel,pins = - ; /* PC9 gpio CD pin pull up and deglitch */ - }; - }; - }; - - dbgu: serial@fffff200 { - status = "okay"; - }; - - tcb0: timer@fffa0000 { - timer@0 { - compatible = "atmel,tcb-timer"; - reg = <0>, <1>; - }; - - timer@2 { - compatible = "atmel,tcb-timer"; - reg = <2>; - }; - }; - - usart0: serial@fffb0000 { - pinctrl-0 = - <&pinctrl_usart0 - &pinctrl_usart0_rts - &pinctrl_usart0_cts - &pinctrl_usart0_dtr_dsr - &pinctrl_usart0_dcd - &pinctrl_usart0_ri>; - status = "okay"; - }; - - usart1: serial@fffb4000 { - status = "okay"; - }; - - macb0: ethernet@fffc4000 { - phy-mode = "rmii"; - status = "okay"; - }; - - usb1: gadget@fffa4000 { - atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - mmc0: mmc@fffa8000 { - pinctrl-0 = < - &pinctrl_board_mmc0_slot1 - &pinctrl_mmc0_clk - &pinctrl_mmc0_slot1_cmd_dat0 - &pinctrl_mmc0_slot1_dat1_3>; - status = "okay"; - slot@1 { - reg = <1>; - bus-width = <4>; - cd-gpios = <&pioC 9 GPIO_ACTIVE_HIGH>; - }; - }; - - ssc0: ssc@fffbc000 { - status = "okay"; - pinctrl-0 = <&pinctrl_ssc0_tx>; - }; - - spi0: spi@fffc8000 { - cs-gpios = <0>, <&pioC 11 0>, <0>, <0>; - mtd_dataflash@1 { - compatible = "atmel,at45", "atmel,dataflash"; - spi-max-frequency = <50000000>; - reg = <1>; - }; - }; - - shdwc@fffffd10 { - atmel,wakeup-counter = <10>; - atmel,wakeup-rtt-timer; - }; - - rtc@fffffd20 { - atmel,rtt-rtc-time-reg = <&gpbr 0x0>; - status = "okay"; - }; - - watchdog@fffffd40 { - status = "okay"; - }; - - gpbr: syscon@fffffd50 { - status = "okay"; - }; - }; - - ebi: ebi@10000000 { - status = "okay"; - - nand_controller: nand-controller { - status = "okay"; - pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>; - pinctrl-names = "default"; - - nand@3 { - reg = <0x3 0x0 0x800000>; - rb-gpios = <&pioC 13 GPIO_ACTIVE_HIGH>; - cs-gpios = <&pioC 14 GPIO_ACTIVE_HIGH>; - nand-bus-width = <8>; - nand-ecc-mode = "soft"; - nand-on-flash-bbt; - label = "atmel_nand"; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - at91bootstrap@0 { - label = "at91bootstrap"; - reg = <0x0 0x20000>; - }; - - barebox@20000 { - label = "barebox"; - reg = <0x20000 0x40000>; - }; - - bareboxenv@60000 { - label = "bareboxenv"; - reg = <0x60000 0x20000>; - }; - - bareboxenv2@80000 { - label = "bareboxenv2"; - reg = <0x80000 0x20000>; - }; - - oftree@80000 { - label = "oftree"; - reg = <0xa0000 0x20000>; - }; - - kernel@a0000 { - label = "kernel"; - reg = <0xc0000 0x400000>; - }; - - rootfs@4a0000 { - label = "rootfs"; - reg = <0x4c0000 0x7800000>; - }; - - data@7ca0000 { - label = "data"; - reg = <0x7cc0000 0x8340000>; - }; - }; - }; - }; - }; - - usb0: ohci@500000 { - num-ports = <2>; - status = "okay"; - }; - }; - - i2c-gpio-0 { - status = "okay"; - - 24c512@50 { - compatible = "atmel,24c512"; - reg = <0x50>; - }; - - wm8731: wm8731@1b { - compatible = "wm8731"; - reg = <0x1b>; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - - btn3 { - label = "Button 3"; - gpios = <&pioA 30 GPIO_ACTIVE_LOW>; - linux,code = <0x103>; - wakeup-source; - }; - - btn4 { - label = "Button 4"; - gpios = <&pioA 31 GPIO_ACTIVE_LOW>; - linux,code = <0x104>; - wakeup-source; - }; - }; - - sound { - compatible = "atmel,at91sam9g20ek-wm8731-audio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pck0_as_mck>; - - atmel,model = "wm8731 @ AT91SAMG20EK"; - - atmel,audio-routing = - "Ext Spk", "LHPOUT", - "Int Mic", "MICIN"; - - atmel,ssc-controller = <&ssc0>; - atmel,audio-codec = <&wm8731>; - }; -}; diff --git a/sys/gnu/dts/arm/at91sam9g25.dtsi b/sys/gnu/dts/arm/at91sam9g25.dtsi deleted file mode 100644 index d2f13afb35e..00000000000 --- a/sys/gnu/dts/arm/at91sam9g25.dtsi +++ /dev/null @@ -1,34 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * at91sam9g25.dtsi - Device Tree Include file for AT91SAM9G25 SoC - * - * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD - */ - -#include "at91sam9x5.dtsi" -#include "at91sam9x5_isi.dtsi" -#include "at91sam9x5_usart3.dtsi" -#include "at91sam9x5_macb0.dtsi" - -/ { - model = "Atmel AT91SAM9G25 SoC"; - compatible = "atmel,at91sam9g25", "atmel,at91sam9x5"; - - ahb { - apb { - pinctrl@fffff400 { - atmel,mux-mask = < - /* A B C */ - 0xffffffff 0xffe0399f 0xc000001c /* pioA */ - 0x0007ffff 0x00047e3f 0x00000000 /* pioB */ - 0x80000000 0x07c0ffff 0xb83fffff /* pioC */ - 0x003fffff 0x003f8000 0x00000000 /* pioD */ - >; - }; - - pmc: pmc@fffffc00 { - compatible = "atmel,at91sam9g25-pmc", "atmel,at91sam9x5-pmc", "syscon"; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/at91sam9g25ek.dts b/sys/gnu/dts/arm/at91sam9g25ek.dts deleted file mode 100644 index 61b0bdb615d..00000000000 --- a/sys/gnu/dts/arm/at91sam9g25ek.dts +++ /dev/null @@ -1,65 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * at91sam9g25ek.dts - Device Tree file for AT91SAM9G25-EK board - * - * Copyright (C) 2012 Atmel, - * 2012 Nicolas Ferre - */ -/dts-v1/; -#include "at91sam9g25.dtsi" -#include "at91sam9x5ek.dtsi" - -/ { - model = "Atmel AT91SAM9G25-EK"; - compatible = "atmel,at91sam9g25ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9"; -}; - -&i2c0 { - camera@30 { - compatible = "ovti,ov2640"; - reg = <0x30>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pck0_as_isi_mck &pinctrl_sensor_power &pinctrl_sensor_reset>; - resetb-gpios = <&pioA 7 GPIO_ACTIVE_LOW>; - pwdn-gpios = <&pioA 13 GPIO_ACTIVE_HIGH>; - clocks = <&pmc PMC_TYPE_SYSTEM 8>; - clock-names = "xvclk"; - assigned-clocks = <&pmc PMC_TYPE_SYSTEM 8>; - assigned-clock-rates = <25000000>; - status = "okay"; - - port { - ov2640_0: endpoint { - remote-endpoint = <&isi_0>; - bus-width = <8>; - }; - }; - }; -}; - -&isi { - status = "okay"; - - port { - isi_0: endpoint@0 { - reg = <0>; - remote-endpoint = <&ov2640_0>; - bus-width = <8>; - vsync-active = <1>; - hsync-active = <1>; - }; - }; -}; - -&macb0 { - phy-mode = "rmii"; - status = "okay"; -}; - -&mmc1 { - status = "disabled"; -}; - -&spi0 { - status = "disabled"; -}; diff --git a/sys/gnu/dts/arm/at91sam9g35.dtsi b/sys/gnu/dts/arm/at91sam9g35.dtsi deleted file mode 100644 index 48c2bc4a775..00000000000 --- a/sys/gnu/dts/arm/at91sam9g35.dtsi +++ /dev/null @@ -1,33 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * at91sam9g35.dtsi - Device Tree Include file for AT91SAM9G35 SoC - * - * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD - */ - -#include "at91sam9x5.dtsi" -#include "at91sam9x5_lcd.dtsi" -#include "at91sam9x5_macb0.dtsi" - -/ { - model = "Atmel AT91SAM9G35 SoC"; - compatible = "atmel,at91sam9g35", "atmel,at91sam9x5"; - - ahb { - apb { - pinctrl@fffff400 { - atmel,mux-mask = < - /* A B C */ - 0xffffffff 0xffe0399f 0xc000000c /* pioA */ - 0x000406ff 0x00047e3f 0x00000000 /* pioB */ - 0xfdffffff 0x00000000 0xb83fffff /* pioC */ - 0x003fffff 0x003f8000 0x00000000 /* pioD */ - >; - }; - - pmc: pmc@fffffc00 { - compatible = "atmel,at91sam9g35-pmc", "atmel,at91sam9x5-pmc", "syscon"; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/at91sam9g35ek.dts b/sys/gnu/dts/arm/at91sam9g35ek.dts deleted file mode 100644 index f966b56de63..00000000000 --- a/sys/gnu/dts/arm/at91sam9g35ek.dts +++ /dev/null @@ -1,41 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * at91sam9g35ek.dts - Device Tree file for AT91SAM9G35-EK board - * - * Copyright (C) 2012 Atmel, - * 2012 Nicolas Ferre - */ -/dts-v1/; -#include "at91sam9g35.dtsi" -#include "at91sam9x5dm.dtsi" -#include "at91sam9x5ek.dtsi" - -/ { - model = "Atmel AT91SAM9G35-EK"; - compatible = "atmel,at91sam9g35ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9"; - - backlight: backlight { - status = "okay"; - }; - - bl_reg: backlight_regulator { - status = "okay"; - }; - - panel: panel { - status = "okay"; - }; - - panel_reg: panel_regulator { - status = "okay"; - }; -}; - -&hlcdc { - status = "okay"; -}; - -&macb0 { - phy-mode = "rmii"; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/at91sam9g45.dtsi b/sys/gnu/dts/arm/at91sam9g45.dtsi deleted file mode 100644 index fd179097a4b..00000000000 --- a/sys/gnu/dts/arm/at91sam9g45.dtsi +++ /dev/null @@ -1,1358 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * at91sam9g45.dtsi - Device Tree Include file for AT91SAM9G45 family SoC - * applies to AT91SAM9G45, AT91SAM9M10, - * AT91SAM9G46, AT91SAM9M11 SoC - * - * Copyright (C) 2011 Atmel, - * 2011 Nicolas Ferre - */ - -#include -#include -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - model = "Atmel AT91SAM9G45 family SoC"; - compatible = "atmel,at91sam9g45"; - interrupt-parent = <&aic>; - - aliases { - serial0 = &dbgu; - serial1 = &usart0; - serial2 = &usart1; - serial3 = &usart2; - serial4 = &usart3; - gpio0 = &pioA; - gpio1 = &pioB; - gpio2 = &pioC; - gpio3 = &pioD; - gpio4 = &pioE; - tcb0 = &tcb0; - tcb1 = &tcb1; - i2c0 = &i2c0; - i2c1 = &i2c1; - ssc0 = &ssc0; - ssc1 = &ssc1; - pwm0 = &pwm0; - }; - cpus { - #address-cells = <0>; - #size-cells = <0>; - - cpu { - compatible = "arm,arm926ej-s"; - device_type = "cpu"; - }; - }; - - memory { - device_type = "memory"; - reg = <0x70000000 0x10000000>; - }; - - clocks { - slow_xtal: slow_xtal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - main_xtal: main_xtal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - adc_op_clk: adc_op_clk{ - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <300000>; - }; - }; - - sram: sram@300000 { - compatible = "mmio-sram"; - reg = <0x00300000 0x10000>; - }; - - ahb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - apb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - aic: interrupt-controller@fffff000 { - #interrupt-cells = <3>; - compatible = "atmel,at91rm9200-aic"; - interrupt-controller; - reg = <0xfffff000 0x200>; - atmel,external-irqs = <31>; - }; - - ramc0: ramc@ffffe400 { - compatible = "atmel,at91sam9g45-ddramc"; - reg = <0xffffe400 0x200>; - clocks = <&ddrck>; - clock-names = "ddrck"; - }; - - ramc1: ramc@ffffe600 { - compatible = "atmel,at91sam9g45-ddramc"; - reg = <0xffffe600 0x200>; - clocks = <&ddrck>; - clock-names = "ddrck"; - }; - - smc: smc@ffffe800 { - compatible = "atmel,at91sam9260-smc", "syscon"; - reg = <0xffffe800 0x200>; - }; - - matrix: matrix@ffffea00 { - compatible = "atmel,at91sam9g45-matrix", "syscon"; - reg = <0xffffea00 0x200>; - }; - - pmc: pmc@fffffc00 { - compatible = "atmel,at91sam9g45-pmc", "syscon"; - reg = <0xfffffc00 0x100>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - interrupt-controller; - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - - main_osc: main_osc { - compatible = "atmel,at91rm9200-clk-main-osc"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_MOSCS>; - clocks = <&main_xtal>; - }; - - main: mainck { - compatible = "atmel,at91rm9200-clk-main"; - #clock-cells = <0>; - clocks = <&main_osc>; - }; - - plla: pllack { - compatible = "atmel,at91rm9200-clk-pll"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_LOCKA>; - clocks = <&main>; - reg = <0>; - atmel,clk-input-range = <2000000 32000000>; - #atmel,pll-clk-output-range-cells = <4>; - atmel,pll-clk-output-ranges = <745000000 800000000 0 0 - 695000000 750000000 1 0 - 645000000 700000000 2 0 - 595000000 650000000 3 0 - 545000000 600000000 0 1 - 495000000 555000000 1 1 - 445000000 500000000 2 1 - 400000000 450000000 3 1>; - }; - - plladiv: plladivck { - compatible = "atmel,at91sam9x5-clk-plldiv"; - #clock-cells = <0>; - clocks = <&plla>; - }; - - utmi: utmick { - compatible = "atmel,at91sam9x5-clk-utmi"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_LOCKU>; - clocks = <&main>; - }; - - mck: masterck { - compatible = "atmel,at91rm9200-clk-master"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_MCKRDY>; - clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>; - atmel,clk-output-range = <0 133333333>; - atmel,clk-divisors = <1 2 4 3>; - }; - - usb: usbck { - compatible = "atmel,at91sam9x5-clk-usb"; - #clock-cells = <0>; - clocks = <&plladiv>, <&utmi>; - }; - - prog: progck { - compatible = "atmel,at91sam9g45-clk-programmable"; - #address-cells = <1>; - #size-cells = <0>; - interrupt-parent = <&pmc>; - clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>; - - prog0: prog0 { - #clock-cells = <0>; - reg = <0>; - interrupts = ; - }; - - prog1: prog1 { - #clock-cells = <0>; - reg = <1>; - interrupts = ; - }; - }; - - systemck { - compatible = "atmel,at91rm9200-clk-system"; - #address-cells = <1>; - #size-cells = <0>; - - ddrck: ddrck { - #clock-cells = <0>; - reg = <2>; - clocks = <&mck>; - }; - - uhpck: uhpck { - #clock-cells = <0>; - reg = <6>; - clocks = <&usb>; - }; - - pck0: pck0 { - #clock-cells = <0>; - reg = <8>; - clocks = <&prog0>; - }; - - pck1: pck1 { - #clock-cells = <0>; - reg = <9>; - clocks = <&prog1>; - }; - }; - - periphck { - compatible = "atmel,at91rm9200-clk-peripheral"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&mck>; - - pioA_clk: pioA_clk { - #clock-cells = <0>; - reg = <2>; - }; - - pioB_clk: pioB_clk { - #clock-cells = <0>; - reg = <3>; - }; - - pioC_clk: pioC_clk { - #clock-cells = <0>; - reg = <4>; - }; - - pioDE_clk: pioDE_clk { - #clock-cells = <0>; - reg = <5>; - }; - - trng_clk: trng_clk { - #clock-cells = <0>; - reg = <6>; - }; - - usart0_clk: usart0_clk { - #clock-cells = <0>; - reg = <7>; - }; - - usart1_clk: usart1_clk { - #clock-cells = <0>; - reg = <8>; - }; - - usart2_clk: usart2_clk { - #clock-cells = <0>; - reg = <9>; - }; - - usart3_clk: usart3_clk { - #clock-cells = <0>; - reg = <10>; - }; - - mci0_clk: mci0_clk { - #clock-cells = <0>; - reg = <11>; - }; - - twi0_clk: twi0_clk { - #clock-cells = <0>; - reg = <12>; - }; - - twi1_clk: twi1_clk { - #clock-cells = <0>; - reg = <13>; - }; - - spi0_clk: spi0_clk { - #clock-cells = <0>; - reg = <14>; - }; - - spi1_clk: spi1_clk { - #clock-cells = <0>; - reg = <15>; - }; - - ssc0_clk: ssc0_clk { - #clock-cells = <0>; - reg = <16>; - }; - - ssc1_clk: ssc1_clk { - #clock-cells = <0>; - reg = <17>; - }; - - tcb0_clk: tcb0_clk { - #clock-cells = <0>; - reg = <18>; - }; - - pwm_clk: pwm_clk { - #clock-cells = <0>; - reg = <19>; - }; - - adc_clk: adc_clk { - #clock-cells = <0>; - reg = <20>; - }; - - dma0_clk: dma0_clk { - #clock-cells = <0>; - reg = <21>; - }; - - uhphs_clk: uhphs_clk { - #clock-cells = <0>; - reg = <22>; - }; - - lcd_clk: lcd_clk { - #clock-cells = <0>; - reg = <23>; - }; - - ac97_clk: ac97_clk { - #clock-cells = <0>; - reg = <24>; - }; - - macb0_clk: macb0_clk { - #clock-cells = <0>; - reg = <25>; - }; - - isi_clk: isi_clk { - #clock-cells = <0>; - reg = <26>; - }; - - udphs_clk: udphs_clk { - #clock-cells = <0>; - reg = <27>; - }; - - aestdessha_clk: aestdessha_clk { - #clock-cells = <0>; - reg = <28>; - }; - - mci1_clk: mci1_clk { - #clock-cells = <0>; - reg = <29>; - }; - - vdec_clk: vdec_clk { - #clock-cells = <0>; - reg = <30>; - }; - }; - }; - - rstc@fffffd00 { - compatible = "atmel,at91sam9g45-rstc"; - reg = <0xfffffd00 0x10>; - clocks = <&clk32k>; - }; - - pit: timer@fffffd30 { - compatible = "atmel,at91sam9260-pit"; - reg = <0xfffffd30 0xf>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&mck>; - }; - - - shdwc@fffffd10 { - compatible = "atmel,at91sam9rl-shdwc"; - reg = <0xfffffd10 0x10>; - clocks = <&clk32k>; - }; - - tcb0: timer@fff7c000 { - compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xfff7c000 0x100>; - interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tcb0_clk>, <&tcb0_clk>, <&tcb0_clk>, <&clk32k>; - clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; - }; - - tcb1: timer@fffd4000 { - compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xfffd4000 0x100>; - interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tcb0_clk>, <&tcb0_clk>, <&tcb0_clk>, <&clk32k>; - clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; - }; - - dma: dma-controller@ffffec00 { - compatible = "atmel,at91sam9g45-dma"; - reg = <0xffffec00 0x200>; - interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>; - #dma-cells = <2>; - clocks = <&dma0_clk>; - clock-names = "dma_clk"; - }; - - pinctrl@fffff200 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "atmel,at91rm9200-pinctrl", "simple-bus"; - ranges = <0xfffff200 0xfffff200 0xa00>; - - atmel,mux-mask = < - /* A B */ - 0xffffffff 0xffc003ff /* pioA */ - 0xffffffff 0x800f8f00 /* pioB */ - 0xffffffff 0x00000e00 /* pioC */ - 0xffffffff 0xff0c1381 /* pioD */ - 0xffffffff 0x81ffff81 /* pioE */ - >; - - /* shared pinctrl settings */ - ac97 { - pinctrl_ac97: ac97-0 { - atmel,pins = - ; /* AC97CK */ - }; - }; - - adc0 { - pinctrl_adc0_adtrg: adc0_adtrg { - atmel,pins = ; - }; - pinctrl_adc0_ad0: adc0_ad0 { - atmel,pins = ; - }; - pinctrl_adc0_ad1: adc0_ad1 { - atmel,pins = ; - }; - pinctrl_adc0_ad2: adc0_ad2 { - atmel,pins = ; - }; - pinctrl_adc0_ad3: adc0_ad3 { - atmel,pins = ; - }; - pinctrl_adc0_ad4: adc0_ad4 { - atmel,pins = ; - }; - pinctrl_adc0_ad5: adc0_ad5 { - atmel,pins = ; - }; - pinctrl_adc0_ad6: adc0_ad6 { - atmel,pins = ; - }; - pinctrl_adc0_ad7: adc0_ad7 { - atmel,pins = ; - }; - }; - - dbgu { - pinctrl_dbgu: dbgu-0 { - atmel,pins = - ; - }; - }; - - i2c0 { - pinctrl_i2c0: i2c0-0 { - atmel,pins = - ; /* PA20 periph A TWD0 */ - }; - }; - - i2c1 { - pinctrl_i2c1: i2c1-0 { - atmel,pins = - ; /* PB10 periph A TWD1 */ - }; - }; - - isi { - pinctrl_isi_data_0_7: isi-0-data-0-7 { - atmel,pins = - ; /* HSYNC */ - }; - - pinctrl_isi_data_8_9: isi-0-data-8-9 { - atmel,pins = - ; /* D9 */ - }; - - pinctrl_isi_data_10_11: isi-0-data-10-11 { - atmel,pins = - ; /* D11 */ - }; - }; - - usart0 { - pinctrl_usart0: usart0-0 { - atmel,pins = - ; - }; - - pinctrl_usart0_rts: usart0_rts-0 { - atmel,pins = - ; /* PB17 periph B */ - }; - - pinctrl_usart0_cts: usart0_cts-0 { - atmel,pins = - ; /* PB15 periph B */ - }; - }; - - usart1 { - pinctrl_usart1: usart1-0 { - atmel,pins = - ; - }; - - pinctrl_usart1_rts: usart1_rts-0 { - atmel,pins = - ; /* PD16 periph A */ - }; - - pinctrl_usart1_cts: usart1_cts-0 { - atmel,pins = - ; /* PD17 periph A */ - }; - }; - - usart2 { - pinctrl_usart2: usart2-0 { - atmel,pins = - ; - }; - - pinctrl_usart2_rts: usart2_rts-0 { - atmel,pins = - ; /* PC9 periph B */ - }; - - pinctrl_usart2_cts: usart2_cts-0 { - atmel,pins = - ; /* PC11 periph B */ - }; - }; - - usart3 { - pinctrl_usart3: usart3-0 { - atmel,pins = - ; - }; - - pinctrl_usart3_rts: usart3_rts-0 { - atmel,pins = - ; /* PA23 periph B */ - }; - - pinctrl_usart3_cts: usart3_cts-0 { - atmel,pins = - ; /* PA24 periph B */ - }; - }; - - nand { - pinctrl_nand_rb: nand-rb-0 { - atmel,pins = - ; - }; - - pinctrl_nand_cs: nand-cs-0 { - atmel,pins = - ; - }; - }; - - macb { - pinctrl_macb_rmii: macb_rmii-0 { - atmel,pins = - ; /* PA19 periph A */ - }; - - pinctrl_macb_rmii_mii: macb_rmii_mii-0 { - atmel,pins = - ; /* PA30 periph B */ - }; - }; - - mmc0 { - pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 { - atmel,pins = - ; /* PA2 periph A with pullup */ - }; - - pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { - atmel,pins = - ; /* PA5 periph A with pullup */ - }; - - pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 { - atmel,pins = - ; /* PA9 periph A with pullup */ - }; - }; - - mmc1 { - pinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 { - atmel,pins = - ; /* PA23 periph A with pullup */ - }; - - pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 { - atmel,pins = - ; /* PA26 periph A with pullup */ - }; - - pinctrl_mmc1_slot0_dat4_7: mmc1_slot0_dat4_7-0 { - atmel,pins = - ; /* PA30 periph A with pullup */ - }; - }; - - ssc0 { - pinctrl_ssc0_tx: ssc0_tx-0 { - atmel,pins = - ; /* PD2 periph A */ - }; - - pinctrl_ssc0_rx: ssc0_rx-0 { - atmel,pins = - ; /* PD5 periph A */ - }; - }; - - ssc1 { - pinctrl_ssc1_tx: ssc1_tx-0 { - atmel,pins = - ; /* PD12 periph A */ - }; - - pinctrl_ssc1_rx: ssc1_rx-0 { - atmel,pins = - ; /* PD15 periph A */ - }; - }; - - spi0 { - pinctrl_spi0: spi0-0 { - atmel,pins = - ; /* PB2 periph A SPI0_SPCK pin */ - }; - }; - - spi1 { - pinctrl_spi1: spi1-0 { - atmel,pins = - ; /* PB16 periph A SPI1_SPCK pin */ - }; - }; - - tcb0 { - pinctrl_tcb0_tclk0: tcb0_tclk0-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tclk1: tcb0_tclk1-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tclk2: tcb0_tclk2-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tioa0: tcb0_tioa0-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tioa1: tcb0_tioa1-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tioa2: tcb0_tioa2-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tiob0: tcb0_tiob0-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tiob1: tcb0_tiob1-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tiob2: tcb0_tiob2-0 { - atmel,pins = ; - }; - }; - - tcb1 { - pinctrl_tcb1_tclk0: tcb1_tclk0-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tclk1: tcb1_tclk1-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tclk2: tcb1_tclk2-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tioa0: tcb1_tioa0-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tioa1: tcb1_tioa1-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tioa2: tcb1_tioa2-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tiob0: tcb1_tiob0-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tiob1: tcb1_tiob1-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tiob2: tcb1_tiob2-0 { - atmel,pins = ; - }; - }; - - fb { - pinctrl_fb: fb-0 { - atmel,pins = - ; /* PE30 periph A */ - }; - }; - - pioA: gpio@fffff200 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff200 0x200>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioA_clk>; - }; - - pioB: gpio@fffff400 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff400 0x200>; - interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioB_clk>; - }; - - pioC: gpio@fffff600 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff600 0x200>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioC_clk>; - }; - - pioD: gpio@fffff800 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff800 0x200>; - interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioDE_clk>; - }; - - pioE: gpio@fffffa00 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffffa00 0x200>; - interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioDE_clk>; - }; - }; - - dbgu: serial@ffffee00 { - compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; - reg = <0xffffee00 0x200>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_dbgu>; - clocks = <&mck>; - clock-names = "usart"; - status = "disabled"; - }; - - usart0: serial@fff8c000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xfff8c000 0x200>; - interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; - atmel,use-dma-rx; - atmel,use-dma-tx; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart0>; - clocks = <&usart0_clk>; - clock-names = "usart"; - status = "disabled"; - }; - - usart1: serial@fff90000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xfff90000 0x200>; - interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; - atmel,use-dma-rx; - atmel,use-dma-tx; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart1>; - clocks = <&usart1_clk>; - clock-names = "usart"; - status = "disabled"; - }; - - usart2: serial@fff94000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xfff94000 0x200>; - interrupts = <9 IRQ_TYPE_LEVEL_HIGH 5>; - atmel,use-dma-rx; - atmel,use-dma-tx; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart2>; - clocks = <&usart2_clk>; - clock-names = "usart"; - status = "disabled"; - }; - - usart3: serial@fff98000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xfff98000 0x200>; - interrupts = <10 IRQ_TYPE_LEVEL_HIGH 5>; - atmel,use-dma-rx; - atmel,use-dma-tx; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart3>; - clocks = <&usart3_clk>; - clock-names = "usart"; - status = "disabled"; - }; - - macb0: ethernet@fffbc000 { - compatible = "cdns,at91sam9260-macb", "cdns,macb"; - reg = <0xfffbc000 0x100>; - interrupts = <25 IRQ_TYPE_LEVEL_HIGH 3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_macb_rmii>; - clocks = <&macb0_clk>, <&macb0_clk>; - clock-names = "hclk", "pclk"; - status = "disabled"; - }; - - trng@fffcc000 { - compatible = "atmel,at91sam9g45-trng"; - reg = <0xfffcc000 0x100>; - interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&trng_clk>; - }; - - i2c0: i2c@fff84000 { - compatible = "atmel,at91sam9g10-i2c"; - reg = <0xfff84000 0x100>; - interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&twi0_clk>; - status = "disabled"; - }; - - i2c1: i2c@fff88000 { - compatible = "atmel,at91sam9g10-i2c"; - reg = <0xfff88000 0x100>; - interrupts = <13 IRQ_TYPE_LEVEL_HIGH 6>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&twi1_clk>; - status = "disabled"; - }; - - ssc0: ssc@fff9c000 { - compatible = "atmel,at91sam9g45-ssc"; - reg = <0xfff9c000 0x4000>; - interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; - clocks = <&ssc0_clk>; - clock-names = "pclk"; - status = "disabled"; - }; - - ssc1: ssc@fffa0000 { - compatible = "atmel,at91sam9g45-ssc"; - reg = <0xfffa0000 0x4000>; - interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; - clocks = <&ssc1_clk>; - clock-names = "pclk"; - status = "disabled"; - }; - - ac97: sound@fffac000 { - compatible = "atmel,at91sam9263-ac97c"; - reg = <0xfffac000 0x4000>; - interrupts = <24 IRQ_TYPE_LEVEL_HIGH 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ac97>; - clocks = <&ac97_clk>; - clock-names = "ac97_clk"; - status = "disabled"; - }; - - adc0: adc@fffb0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "atmel,at91sam9g45-adc"; - reg = <0xfffb0000 0x100>; - interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&adc_clk>, <&adc_op_clk>; - clock-names = "adc_clk", "adc_op_clk"; - atmel,adc-channels-used = <0xff>; - atmel,adc-vref = <3300>; - atmel,adc-startup-time = <40>; - atmel,adc-res = <8 10>; - atmel,adc-res-names = "lowres", "highres"; - atmel,adc-use-res = "highres"; - - trigger0 { - trigger-name = "external-rising"; - trigger-value = <0x1>; - trigger-external; - }; - trigger1 { - trigger-name = "external-falling"; - trigger-value = <0x2>; - trigger-external; - }; - - trigger2 { - trigger-name = "external-any"; - trigger-value = <0x3>; - trigger-external; - }; - - trigger3 { - trigger-name = "continuous"; - trigger-value = <0x6>; - }; - }; - - isi@fffb4000 { - compatible = "atmel,at91sam9g45-isi"; - reg = <0xfffb4000 0x4000>; - interrupts = <26 IRQ_TYPE_LEVEL_HIGH 5>; - clocks = <&isi_clk>; - clock-names = "isi_clk"; - status = "disabled"; - port { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - pwm0: pwm@fffb8000 { - compatible = "atmel,at91sam9rl-pwm"; - reg = <0xfffb8000 0x300>; - interrupts = <19 IRQ_TYPE_LEVEL_HIGH 4>; - #pwm-cells = <3>; - clocks = <&pwm_clk>; - status = "disabled"; - }; - - mmc0: mmc@fff80000 { - compatible = "atmel,hsmci"; - reg = <0xfff80000 0x600>; - interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>; - pinctrl-names = "default"; - dmas = <&dma 1 AT91_DMA_CFG_PER_ID(0)>; - dma-names = "rxtx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&mci0_clk>; - clock-names = "mci_clk"; - status = "disabled"; - }; - - mmc1: mmc@fffd0000 { - compatible = "atmel,hsmci"; - reg = <0xfffd0000 0x600>; - interrupts = <29 IRQ_TYPE_LEVEL_HIGH 0>; - pinctrl-names = "default"; - dmas = <&dma 1 AT91_DMA_CFG_PER_ID(13)>; - dma-names = "rxtx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&mci1_clk>; - clock-names = "mci_clk"; - status = "disabled"; - }; - - watchdog@fffffd40 { - compatible = "atmel,at91sam9260-wdt"; - reg = <0xfffffd40 0x10>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&clk32k>; - atmel,watchdog-type = "hardware"; - atmel,reset-type = "all"; - atmel,dbg-halt; - status = "disabled"; - }; - - spi0: spi@fffa4000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "atmel,at91rm9200-spi"; - reg = <0xfffa4000 0x200>; - interrupts = <14 4 3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi0>; - clocks = <&spi0_clk>; - clock-names = "spi_clk"; - status = "disabled"; - }; - - spi1: spi@fffa8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "atmel,at91rm9200-spi"; - reg = <0xfffa8000 0x200>; - interrupts = <15 4 3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1>; - clocks = <&spi1_clk>; - clock-names = "spi_clk"; - status = "disabled"; - }; - - usb2: gadget@fff78000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "atmel,at91sam9g45-udc"; - reg = <0x00600000 0x80000 - 0xfff78000 0x400>; - interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&udphs_clk>, <&utmi>; - clock-names = "pclk", "hclk"; - status = "disabled"; - - ep@0 { - reg = <0>; - atmel,fifo-size = <64>; - atmel,nb-banks = <1>; - }; - - ep@1 { - reg = <1>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@2 { - reg = <2>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@3 { - reg = <3>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <3>; - atmel,can-dma; - }; - - ep@4 { - reg = <4>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <3>; - atmel,can-dma; - }; - - ep@5 { - reg = <5>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <3>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@6 { - reg = <6>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <3>; - atmel,can-dma; - atmel,can-isoc; - }; - }; - - clk32k: sckc@fffffd50 { - compatible = "atmel,at91sam9x5-sckc"; - reg = <0xfffffd50 0x4>; - clocks = <&slow_xtal>; - #clock-cells = <0>; - }; - - rtc@fffffd20 { - compatible = "atmel,at91sam9260-rtt"; - reg = <0xfffffd20 0x10>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&clk32k>; - status = "disabled"; - }; - - rtc@fffffdb0 { - compatible = "atmel,at91rm9200-rtc"; - reg = <0xfffffdb0 0x30>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&clk32k>; - status = "disabled"; - }; - - gpbr: syscon@fffffd60 { - compatible = "atmel,at91sam9260-gpbr", "syscon"; - reg = <0xfffffd60 0x10>; - status = "disabled"; - }; - }; - - fb0: fb@500000 { - compatible = "atmel,at91sam9g45-lcdc"; - reg = <0x00500000 0x1000>; - interrupts = <23 IRQ_TYPE_LEVEL_HIGH 3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fb>; - clocks = <&lcd_clk>, <&lcd_clk>; - clock-names = "hclk", "lcdc_clk"; - status = "disabled"; - }; - - usb0: ohci@700000 { - compatible = "atmel,at91rm9200-ohci", "usb-ohci"; - reg = <0x00700000 0x100000>; - interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>; - clock-names = "ohci_clk", "hclk", "uhpck"; - status = "disabled"; - }; - - usb1: ehci@800000 { - compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; - reg = <0x00800000 0x100000>; - interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&utmi>, <&uhphs_clk>; - clock-names = "usb_clk", "ehci_clk"; - status = "disabled"; - }; - - ebi: ebi@10000000 { - compatible = "atmel,at91sam9g45-ebi"; - #address-cells = <2>; - #size-cells = <1>; - atmel,smc = <&smc>; - atmel,matrix = <&matrix>; - reg = <0x10000000 0x80000000>; - ranges = <0x0 0x0 0x10000000 0x10000000 - 0x1 0x0 0x20000000 0x10000000 - 0x2 0x0 0x30000000 0x10000000 - 0x3 0x0 0x40000000 0x10000000 - 0x4 0x0 0x50000000 0x10000000 - 0x5 0x0 0x60000000 0x10000000>; - clocks = <&mck>; - status = "disabled"; - - nand_controller: nand-controller { - compatible = "atmel,at91sam9g45-nand-controller"; - #address-cells = <2>; - #size-cells = <1>; - ranges; - status = "disabled"; - }; - }; - }; - - i2c-gpio-0 { - compatible = "i2c-gpio"; - gpios = <&pioA 20 GPIO_ACTIVE_HIGH /* sda */ - &pioA 21 GPIO_ACTIVE_HIGH /* scl */ - >; - i2c-gpio,sda-open-drain; - i2c-gpio,scl-open-drain; - i2c-gpio,delay-us = <5>; /* ~100 kHz */ - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; -}; diff --git a/sys/gnu/dts/arm/at91sam9m10g45ek.dts b/sys/gnu/dts/arm/at91sam9m10g45ek.dts deleted file mode 100644 index 84bed6f55fc..00000000000 --- a/sys/gnu/dts/arm/at91sam9m10g45ek.dts +++ /dev/null @@ -1,391 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * at91sam9m10g45ek.dts - Device Tree file for AT91SAM9M10G45-EK board - * - * Copyright (C) 2011 Atmel, - * 2011 Nicolas Ferre - */ -/dts-v1/; -#include "at91sam9g45.dtsi" -#include - -/ { - model = "Atmel AT91SAM9M10G45-EK"; - compatible = "atmel,at91sam9m10g45ek", "atmel,at91sam9g45", "atmel,at91sam9"; - - chosen { - bootargs = "mem=64M root=/dev/mtdblock1 rw rootfstype=jffs2"; - stdout-path = "serial0:115200n8"; - }; - - memory { - reg = <0x70000000 0x4000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <12000000>; - }; - }; - - ahb { - apb { - dbgu: serial@ffffee00 { - status = "okay"; - }; - - tcb0: timer@fff7c000 { - timer@0 { - compatible = "atmel,tcb-timer"; - reg = <0>, <1>; - }; - - timer@2 { - compatible = "atmel,tcb-timer"; - reg = <2>; - }; - }; - - usart1: serial@fff90000 { - pinctrl-0 = - <&pinctrl_usart1 - &pinctrl_usart1_rts - &pinctrl_usart1_cts>; - status = "okay"; - }; - - macb0: ethernet@fffbc000 { - phy-mode = "rmii"; - status = "okay"; - }; - - i2c0: i2c@fff84000 { - status = "okay"; - ov2640: camera@30 { - compatible = "ovti,ov2640"; - reg = <0x30>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pck1_as_isi_mck &pinctrl_sensor_power &pinctrl_sensor_reset>; - resetb-gpios = <&pioD 12 GPIO_ACTIVE_LOW>; - pwdn-gpios = <&pioD 13 GPIO_ACTIVE_HIGH>; - clocks = <&pck1>; - clock-names = "xvclk"; - assigned-clocks = <&pck1>; - assigned-clock-rates = <25000000>; - - port { - ov2640_0: endpoint { - remote-endpoint = <&isi_0>; - bus-width = <8>; - }; - }; - }; - }; - - i2c1: i2c@fff88000 { - status = "okay"; - }; - - watchdog@fffffd40 { - status = "okay"; - }; - - mmc0: mmc@fff80000 { - pinctrl-0 = < - &pinctrl_board_mmc0 - &pinctrl_mmc0_slot0_clk_cmd_dat0 - &pinctrl_mmc0_slot0_dat1_3>; - status = "okay"; - slot@0 { - reg = <0>; - bus-width = <4>; - cd-gpios = <&pioD 10 GPIO_ACTIVE_HIGH>; - }; - }; - - mmc1: mmc@fffd0000 { - pinctrl-0 = < - &pinctrl_board_mmc1 - &pinctrl_mmc1_slot0_clk_cmd_dat0 - &pinctrl_mmc1_slot0_dat1_3>; - status = "okay"; - slot@0 { - reg = <0>; - bus-width = <4>; - cd-gpios = <&pioD 11 GPIO_ACTIVE_HIGH>; - wp-gpios = <&pioD 29 GPIO_ACTIVE_HIGH>; - }; - }; - - pinctrl@fffff200 { - camera_sensor { - pinctrl_pck1_as_isi_mck: pck1_as_isi_mck-0 { - atmel,pins = - ; - }; - - pinctrl_sensor_reset: sensor_reset-0 { - atmel,pins = - ; - }; - - pinctrl_sensor_power: sensor_power-0 { - atmel,pins = - ; - }; - }; - mmc0 { - pinctrl_board_mmc0: mmc0-board { - atmel,pins = - ; /* PD10 gpio CD pin pull up and deglitch */ - }; - }; - - mmc1 { - pinctrl_board_mmc1: mmc1-board { - atmel,pins = - ; /* PD29 gpio WP pin pull up */ - }; - }; - - pwm0 { - pinctrl_pwm_leds: pwm-led { - atmel,pins = - ; /* PD31 periph B */ - }; - }; - }; - - spi0: spi@fffa4000{ - status = "okay"; - cs-gpios = <&pioB 3 0>, <0>, <0>, <0>; - mtd_dataflash@0 { - compatible = "atmel,at45", "atmel,dataflash"; - spi-max-frequency = <13000000>; - reg = <0>; - }; - }; - - usb2: gadget@fff78000 { - atmel,vbus-gpio = <&pioB 19 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - ac97: sound@fffac000 { - status = "okay"; - }; - - adc0: adc@fffb0000 { - pinctrl-names = "default"; - pinctrl-0 = < - &pinctrl_adc0_ad0 - &pinctrl_adc0_ad1 - &pinctrl_adc0_ad2 - &pinctrl_adc0_ad3 - &pinctrl_adc0_ad4 - &pinctrl_adc0_ad5 - &pinctrl_adc0_ad6 - &pinctrl_adc0_ad7>; - atmel,adc-ts-wires = <4>; - status = "okay"; - }; - - isi@fffb4000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_isi_data_0_7>; - status = "okay"; - port { - isi_0: endpoint { - remote-endpoint = <&ov2640_0>; - bus-width = <8>; - vsync-active = <1>; - hsync-active = <1>; - }; - }; - }; - - pwm0: pwm@fffb8000 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm_leds>; - }; - - rtc@fffffd20 { - atmel,rtt-rtc-time-reg = <&gpbr 0x0>; - status = "okay"; - }; - - gpbr: syscon@fffffd60 { - status = "okay"; - }; - - rtc@fffffdb0 { - status = "okay"; - }; - }; - - fb0: fb@500000 { - display = <&display0>; - status = "okay"; - - display0: panel { - bits-per-pixel = <32>; - atmel,lcdcon-backlight; - atmel,dmacon = <0x1>; - atmel,lcdcon2 = <0x80008002>; - atmel,guard-time = <9>; - atmel,lcd-wiring-mode = "RGB"; - - display-timings { - native-mode = <&timing0>; - timing0: timing0 { - clock-frequency = <9000000>; - hactive = <480>; - vactive = <272>; - hback-porch = <1>; - hfront-porch = <1>; - vback-porch = <40>; - vfront-porch = <1>; - hsync-len = <45>; - vsync-len = <1>; - }; - }; - }; - }; - - ebi: ebi@10000000 { - status = "okay"; - - nand_controller: nand-controller { - status = "okay"; - pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>; - pinctrl-names = "default"; - - nand@3 { - reg = <0x3 0x0 0x800000>; - rb-gpios = <&pioC 8 GPIO_ACTIVE_HIGH>; - cs-gpios = <&pioC 14 GPIO_ACTIVE_HIGH>; - nand-bus-width = <8>; - nand-ecc-mode = "soft"; - nand-on-flash-bbt; - label = "atmel_nand"; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot@0 { - label = "bootstrap/uboot/kernel"; - reg = <0x0 0x400000>; - }; - - rootfs@400000 { - label = "rootfs"; - reg = <0x400000 0x3C00000>; - }; - - data@4000000 { - label = "data"; - reg = <0x4000000 0xC000000>; - }; - }; - }; - }; - }; - - usb0: ohci@700000 { - status = "okay"; - num-ports = <2>; - atmel,vbus-gpio = <&pioD 1 GPIO_ACTIVE_LOW - &pioD 3 GPIO_ACTIVE_LOW>; - }; - - usb1: ehci@800000 { - status = "okay"; - }; - }; - - leds { - compatible = "gpio-leds"; - - d8 { - label = "d8"; - gpios = <&pioD 30 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - pwmleds { - compatible = "pwm-leds"; - - d6 { - label = "d6"; - pwms = <&pwm0 3 5000 PWM_POLARITY_INVERTED>; - max-brightness = <255>; - linux,default-trigger = "nand-disk"; - }; - - d7 { - label = "d7"; - pwms = <&pwm0 1 5000 PWM_POLARITY_INVERTED>; - max-brightness = <255>; - linux,default-trigger = "mmc0"; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - - left_click { - label = "left_click"; - gpios = <&pioB 6 GPIO_ACTIVE_LOW>; - linux,code = <272>; - wakeup-source; - }; - - right_click { - label = "right_click"; - gpios = <&pioB 7 GPIO_ACTIVE_LOW>; - linux,code = <273>; - wakeup-source; - }; - - left { - label = "Joystick Left"; - gpios = <&pioB 14 GPIO_ACTIVE_LOW>; - linux,code = <105>; - }; - - right { - label = "Joystick Right"; - gpios = <&pioB 15 GPIO_ACTIVE_LOW>; - linux,code = <106>; - }; - - up { - label = "Joystick Up"; - gpios = <&pioB 16 GPIO_ACTIVE_LOW>; - linux,code = <103>; - }; - - down { - label = "Joystick Down"; - gpios = <&pioB 17 GPIO_ACTIVE_LOW>; - linux,code = <108>; - }; - - enter { - label = "Joystick Press"; - gpios = <&pioB 18 GPIO_ACTIVE_LOW>; - linux,code = <28>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/at91sam9n12.dtsi b/sys/gnu/dts/arm/at91sam9n12.dtsi deleted file mode 100644 index ea675174432..00000000000 --- a/sys/gnu/dts/arm/at91sam9n12.dtsi +++ /dev/null @@ -1,1074 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * at91sam9n12.dtsi - Device Tree include file for AT91SAM9N12 SoC - * - * Copyright (C) 2012 Atmel, - * 2012 Hong Xu - */ - -#include -#include -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - model = "Atmel AT91SAM9N12 SoC"; - compatible = "atmel,at91sam9n12"; - interrupt-parent = <&aic>; - - aliases { - serial0 = &dbgu; - serial1 = &usart0; - serial2 = &usart1; - serial3 = &usart2; - serial4 = &usart3; - gpio0 = &pioA; - gpio1 = &pioB; - gpio2 = &pioC; - gpio3 = &pioD; - tcb0 = &tcb0; - tcb1 = &tcb1; - i2c0 = &i2c0; - i2c1 = &i2c1; - ssc0 = &ssc0; - pwm0 = &pwm0; - }; - cpus { - #address-cells = <0>; - #size-cells = <0>; - - cpu { - compatible = "arm,arm926ej-s"; - device_type = "cpu"; - }; - }; - - memory { - device_type = "memory"; - reg = <0x20000000 0x10000000>; - }; - - clocks { - slow_xtal: slow_xtal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - main_xtal: main_xtal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - }; - - sram: sram@300000 { - compatible = "mmio-sram"; - reg = <0x00300000 0x8000>; - }; - - ahb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - apb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - aic: interrupt-controller@fffff000 { - #interrupt-cells = <3>; - compatible = "atmel,at91rm9200-aic"; - interrupt-controller; - reg = <0xfffff000 0x200>; - atmel,external-irqs = <31>; - }; - - matrix: matrix@ffffde00 { - compatible = "atmel,at91sam9n12-matrix", "syscon"; - reg = <0xffffde00 0x100>; - }; - - pmecc: ecc-engine@ffffe000 { - compatible = "atmel,at91sam9g45-pmecc"; - reg = <0xffffe000 0x600>, - <0xffffe600 0x200>; - }; - - ramc0: ramc@ffffe800 { - compatible = "atmel,at91sam9g45-ddramc"; - reg = <0xffffe800 0x200>; - clocks = <&ddrck>; - clock-names = "ddrck"; - }; - - smc: smc@ffffea00 { - compatible = "atmel,at91sam9260-smc", "syscon"; - reg = <0xffffea00 0x200>; - }; - - pmc: pmc@fffffc00 { - compatible = "atmel,at91sam9n12-pmc", "syscon"; - reg = <0xfffffc00 0x200>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - interrupt-controller; - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - - main_rc_osc: main_rc_osc { - compatible = "atmel,at91sam9x5-clk-main-rc-osc"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_MOSCRCS>; - clock-frequency = <12000000>; - clock-accuracy = <50000000>; - }; - - main_osc: main_osc { - compatible = "atmel,at91rm9200-clk-main-osc"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_MOSCS>; - clocks = <&main_xtal>; - }; - - main: mainck { - compatible = "atmel,at91sam9x5-clk-main"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_MOSCSELS>; - clocks = <&main_rc_osc>, <&main_osc>; - }; - - plla: pllack { - compatible = "atmel,at91rm9200-clk-pll"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_LOCKA>; - clocks = <&main>; - reg = <0>; - atmel,clk-input-range = <2000000 32000000>; - #atmel,pll-clk-output-range-cells = <4>; - atmel,pll-clk-output-ranges = <745000000 800000000 0 0>, - <695000000 750000000 1 0>, - <645000000 700000000 2 0>, - <595000000 650000000 3 0>, - <545000000 600000000 0 1>, - <495000000 555000000 1 1>, - <445000000 500000000 2 1>, - <400000000 450000000 3 1>; - }; - - plladiv: plladivck { - compatible = "atmel,at91sam9x5-clk-plldiv"; - #clock-cells = <0>; - clocks = <&plla>; - }; - - pllb: pllbck { - compatible = "atmel,at91rm9200-clk-pll"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_LOCKB>; - clocks = <&main>; - reg = <1>; - atmel,clk-input-range = <2000000 32000000>; - #atmel,pll-clk-output-range-cells = <3>; - atmel,pll-clk-output-ranges = <30000000 100000000 0>; - }; - - mck: masterck { - compatible = "atmel,at91sam9x5-clk-master"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_MCKRDY>; - clocks = <&clk32k>, <&main>, <&plladiv>, <&pllb>; - atmel,clk-output-range = <0 133333333>; - atmel,clk-divisors = <1 2 4 3>; - atmel,master-clk-have-div3-pres; - }; - - usb: usbck { - compatible = "atmel,at91sam9n12-clk-usb"; - #clock-cells = <0>; - clocks = <&pllb>; - }; - - prog: progck { - compatible = "atmel,at91sam9x5-clk-programmable"; - #address-cells = <1>; - #size-cells = <0>; - interrupt-parent = <&pmc>; - clocks = <&clk32k>, <&main>, <&plladiv>, <&pllb>, <&mck>; - - prog0: prog0 { - #clock-cells = <0>; - reg = <0>; - interrupts = ; - }; - - prog1: prog1 { - #clock-cells = <0>; - reg = <1>; - interrupts = ; - }; - }; - - systemck { - compatible = "atmel,at91rm9200-clk-system"; - #address-cells = <1>; - #size-cells = <0>; - - ddrck: ddrck { - #clock-cells = <0>; - reg = <2>; - clocks = <&mck>; - }; - - lcdck: lcdck { - #clock-cells = <0>; - reg = <3>; - clocks = <&mck>; - }; - - uhpck: uhpck { - #clock-cells = <0>; - reg = <6>; - clocks = <&usb>; - }; - - udpck: udpck { - #clock-cells = <0>; - reg = <7>; - clocks = <&usb>; - }; - - pck0: pck0 { - #clock-cells = <0>; - reg = <8>; - clocks = <&prog0>; - }; - - pck1: pck1 { - #clock-cells = <0>; - reg = <9>; - clocks = <&prog1>; - }; - }; - - periphck { - compatible = "atmel,at91sam9x5-clk-peripheral"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&mck>; - - pioAB_clk: pioAB_clk { - #clock-cells = <0>; - reg = <2>; - }; - - pioCD_clk: pioCD_clk { - #clock-cells = <0>; - reg = <3>; - }; - - fuse_clk: fuse_clk { - #clock-cells = <0>; - reg = <4>; - }; - - usart0_clk: usart0_clk { - #clock-cells = <0>; - reg = <5>; - }; - - usart1_clk: usart1_clk { - #clock-cells = <0>; - reg = <6>; - }; - - usart2_clk: usart2_clk { - #clock-cells = <0>; - reg = <7>; - }; - - usart3_clk: usart3_clk { - #clock-cells = <0>; - reg = <8>; - }; - - twi0_clk: twi0_clk { - reg = <9>; - #clock-cells = <0>; - }; - - twi1_clk: twi1_clk { - #clock-cells = <0>; - reg = <10>; - }; - - mci0_clk: mci0_clk { - #clock-cells = <0>; - reg = <12>; - }; - - spi0_clk: spi0_clk { - #clock-cells = <0>; - reg = <13>; - }; - - spi1_clk: spi1_clk { - #clock-cells = <0>; - reg = <14>; - }; - - uart0_clk: uart0_clk { - #clock-cells = <0>; - reg = <15>; - }; - - uart1_clk: uart1_clk { - #clock-cells = <0>; - reg = <16>; - }; - - tcb_clk: tcb_clk { - #clock-cells = <0>; - reg = <17>; - }; - - pwm_clk: pwm_clk { - #clock-cells = <0>; - reg = <18>; - }; - - adc_clk: adc_clk { - #clock-cells = <0>; - reg = <19>; - }; - - dma0_clk: dma0_clk { - #clock-cells = <0>; - reg = <20>; - }; - - uhphs_clk: uhphs_clk { - #clock-cells = <0>; - reg = <22>; - }; - - udphs_clk: udphs_clk { - #clock-cells = <0>; - reg = <23>; - }; - - lcdc_clk: lcdc_clk { - #clock-cells = <0>; - reg = <25>; - }; - - sha_clk: sha_clk { - #clock-cells = <0>; - reg = <27>; - }; - - ssc0_clk: ssc0_clk { - #clock-cells = <0>; - reg = <28>; - }; - - aes_clk: aes_clk { - #clock-cells = <0>; - reg = <29>; - }; - - trng_clk: trng_clk { - #clock-cells = <0>; - reg = <30>; - }; - }; - }; - - rstc@fffffe00 { - compatible = "atmel,at91sam9g45-rstc"; - reg = <0xfffffe00 0x10>; - clocks = <&clk32k>; - }; - - pit: timer@fffffe30 { - compatible = "atmel,at91sam9260-pit"; - reg = <0xfffffe30 0xf>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&mck>; - }; - - shdwc@fffffe10 { - compatible = "atmel,at91sam9x5-shdwc"; - reg = <0xfffffe10 0x10>; - clocks = <&clk32k>; - }; - - sckc@fffffe50 { - compatible = "atmel,at91sam9x5-sckc"; - reg = <0xfffffe50 0x4>; - - slow_osc: slow_osc { - compatible = "atmel,at91sam9x5-clk-slow-osc"; - #clock-cells = <0>; - clocks = <&slow_xtal>; - }; - - slow_rc_osc: slow_rc_osc { - compatible = "atmel,at91sam9x5-clk-slow-rc-osc"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-accuracy = <50000000>; - }; - - clk32k: slck { - compatible = "atmel,at91sam9x5-clk-slow"; - #clock-cells = <0>; - clocks = <&slow_rc_osc>, <&slow_osc>; - }; - }; - - mmc0: mmc@f0008000 { - compatible = "atmel,hsmci"; - reg = <0xf0008000 0x600>; - interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; - dmas = <&dma 1 AT91_DMA_CFG_PER_ID(0)>; - dma-names = "rxtx"; - clocks = <&mci0_clk>; - clock-names = "mci_clk"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - tcb0: timer@f8008000 { - compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xf8008000 0x100>; - interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tcb_clk>, <&clk32k>; - clock-names = "t0_clk", "slow_clk"; - }; - - tcb1: timer@f800c000 { - compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xf800c000 0x100>; - interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tcb_clk>, <&clk32k>; - clock-names = "t0_clk", "slow_clk"; - }; - - hlcdc: hlcdc@f8038000 { - compatible = "atmel,at91sam9n12-hlcdc"; - reg = <0xf8038000 0x2000>; - interrupts = <25 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>; - clock-names = "periph_clk", "sys_clk", "slow_clk"; - status = "disabled"; - - hlcdc-display-controller { - compatible = "atmel,hlcdc-display-controller"; - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - }; - - hlcdc_pwm: hlcdc-pwm { - compatible = "atmel,hlcdc-pwm"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd_pwm>; - #pwm-cells = <3>; - }; - }; - - dma: dma-controller@ffffec00 { - compatible = "atmel,at91sam9g45-dma"; - reg = <0xffffec00 0x200>; - interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; - #dma-cells = <2>; - clocks = <&dma0_clk>; - clock-names = "dma_clk"; - }; - - pinctrl@fffff400 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus"; - ranges = <0xfffff400 0xfffff400 0x800>; - - atmel,mux-mask = < - /* A B C */ - 0xffffffff 0xffe07983 0x00000000 /* pioA */ - 0x00040000 0x00047e0f 0x00000000 /* pioB */ - 0xfdffffff 0x07c00000 0xb83fffff /* pioC */ - 0x003fffff 0x003f8000 0x00000000 /* pioD */ - >; - - /* shared pinctrl settings */ - dbgu { - pinctrl_dbgu: dbgu-0 { - atmel,pins = - ; - }; - }; - - lcd { - pinctrl_lcd_base: lcd-base-0 { - atmel,pins = - ; /* LCDPCK */ - }; - - pinctrl_lcd_pwm: lcd-pwm-0 { - atmel,pins = ; /* LCDPWM */ - }; - - pinctrl_lcd_rgb888: lcd-rgb-3 { - atmel,pins = - ; /* LCDD23 pin */ - }; - }; - - usart0 { - pinctrl_usart0: usart0-0 { - atmel,pins = - ; /* PA0 periph A */ - }; - - pinctrl_usart0_rts: usart0_rts-0 { - atmel,pins = - ; /* PA2 periph A */ - }; - - pinctrl_usart0_cts: usart0_cts-0 { - atmel,pins = - ; /* PA3 periph A */ - }; - }; - - usart1 { - pinctrl_usart1: usart1-0 { - atmel,pins = - ; /* PA5 periph A */ - }; - }; - - usart2 { - pinctrl_usart2: usart2-0 { - atmel,pins = - ; /* PA7 periph A */ - }; - - pinctrl_usart2_rts: usart2_rts-0 { - atmel,pins = - ; /* PB0 periph B */ - }; - - pinctrl_usart2_cts: usart2_cts-0 { - atmel,pins = - ; /* PB1 periph B */ - }; - }; - - usart3 { - pinctrl_usart3: usart3-0 { - atmel,pins = - ; /* PC22 periph B */ - }; - - pinctrl_usart3_rts: usart3_rts-0 { - atmel,pins = - ; /* PC24 periph B */ - }; - - pinctrl_usart3_cts: usart3_cts-0 { - atmel,pins = - ; /* PC25 periph B */ - }; - }; - - uart0 { - pinctrl_uart0: uart0-0 { - atmel,pins = - ; /* PC8 periph C */ - }; - }; - - uart1 { - pinctrl_uart1: uart1-0 { - atmel,pins = - ; - }; - }; - - nand { - pinctrl_nand_rb: nand-rb-0 { - atmel,pins = - ; - }; - - pinctrl_nand_cs: nand-cs-0 { - atmel,pins = - ; - }; - }; - - mmc0 { - pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 { - atmel,pins = - ; /* PA15 periph A with pullup */ - }; - - pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { - atmel,pins = - ; /* PA20 periph A with pullup */ - }; - - pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 { - atmel,pins = - ; /* PA14 periph B with pullup */ - }; - }; - - ssc0 { - pinctrl_ssc0_tx: ssc0_tx-0 { - atmel,pins = - ; /* PA26 periph B */ - }; - - pinctrl_ssc0_rx: ssc0_rx-0 { - atmel,pins = - ; /* PA29 periph B */ - }; - }; - - spi0 { - pinctrl_spi0: spi0-0 { - atmel,pins = - ; /* PA13 periph A SPI0_SPCK pin */ - }; - }; - - spi1 { - pinctrl_spi1: spi1-0 { - atmel,pins = - ; /* PA23 periph B SPI1_SPCK pin */ - }; - }; - - i2c0 { - pinctrl_i2c0: i2c0-0 { - atmel,pins = - ; - }; - }; - - i2c1 { - pinctrl_i2c1: i2c1-0 { - atmel,pins = - ; - }; - }; - - tcb0 { - pinctrl_tcb0_tclk0: tcb0_tclk0-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tclk1: tcb0_tclk1-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tclk2: tcb0_tclk2-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tioa0: tcb0_tioa0-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tioa1: tcb0_tioa1-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tioa2: tcb0_tioa2-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tiob0: tcb0_tiob0-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tiob1: tcb0_tiob1-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tiob2: tcb0_tiob2-0 { - atmel,pins = ; - }; - }; - - tcb1 { - pinctrl_tcb1_tclk0: tcb1_tclk0-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tclk1: tcb1_tclk1-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tclk2: tcb1_tclk2-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tioa0: tcb1_tioa0-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tioa1: tcb1_tioa1-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tioa2: tcb1_tioa2-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tiob0: tcb1_tiob0-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tiob1: tcb1_tiob1-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tiob2: tcb1_tiob2-0 { - atmel,pins = ; - }; - }; - - pioA: gpio@fffff400 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfffff400 0x200>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioAB_clk>; - }; - - pioB: gpio@fffff600 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfffff600 0x200>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioAB_clk>; - }; - - pioC: gpio@fffff800 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfffff800 0x200>; - interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioCD_clk>; - }; - - pioD: gpio@fffffa00 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfffffa00 0x200>; - interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioCD_clk>; - }; - }; - - dbgu: serial@fffff200 { - compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; - reg = <0xfffff200 0x200>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_dbgu>; - clocks = <&mck>; - clock-names = "usart"; - status = "disabled"; - }; - - ssc0: ssc@f0010000 { - compatible = "atmel,at91sam9g45-ssc"; - reg = <0xf0010000 0x4000>; - interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>; - dmas = <&dma 0 AT91_DMA_CFG_PER_ID(21)>, - <&dma 0 AT91_DMA_CFG_PER_ID(22)>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; - clocks = <&ssc0_clk>; - clock-names = "pclk"; - status = "disabled"; - }; - - usart0: serial@f801c000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xf801c000 0x4000>; - interrupts = <5 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart0>; - clocks = <&usart0_clk>; - clock-names = "usart"; - status = "disabled"; - }; - - usart1: serial@f8020000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xf8020000 0x4000>; - interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart1>; - clocks = <&usart1_clk>; - clock-names = "usart"; - status = "disabled"; - }; - - usart2: serial@f8024000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xf8024000 0x4000>; - interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart2>; - clocks = <&usart2_clk>; - clock-names = "usart"; - status = "disabled"; - }; - - usart3: serial@f8028000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xf8028000 0x4000>; - interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart3>; - clocks = <&usart3_clk>; - clock-names = "usart"; - status = "disabled"; - }; - - i2c0: i2c@f8010000 { - compatible = "atmel,at91sam9x5-i2c"; - reg = <0xf8010000 0x100>; - interrupts = <9 IRQ_TYPE_LEVEL_HIGH 6>; - dmas = <&dma 1 AT91_DMA_CFG_PER_ID(13)>, - <&dma 1 AT91_DMA_CFG_PER_ID(14)>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - clocks = <&twi0_clk>; - status = "disabled"; - }; - - i2c1: i2c@f8014000 { - compatible = "atmel,at91sam9x5-i2c"; - reg = <0xf8014000 0x100>; - interrupts = <10 IRQ_TYPE_LEVEL_HIGH 6>; - dmas = <&dma 1 AT91_DMA_CFG_PER_ID(15)>, - <&dma 1 AT91_DMA_CFG_PER_ID(16)>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - clocks = <&twi1_clk>; - status = "disabled"; - }; - - spi0: spi@f0000000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "atmel,at91rm9200-spi"; - reg = <0xf0000000 0x100>; - interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>; - dmas = <&dma 1 AT91_DMA_CFG_PER_ID(1)>, - <&dma 1 AT91_DMA_CFG_PER_ID(2)>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi0>; - clocks = <&spi0_clk>; - clock-names = "spi_clk"; - status = "disabled"; - }; - - spi1: spi@f0004000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "atmel,at91rm9200-spi"; - reg = <0xf0004000 0x100>; - interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>; - dmas = <&dma 1 AT91_DMA_CFG_PER_ID(3)>, - <&dma 1 AT91_DMA_CFG_PER_ID(4)>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1>; - clocks = <&spi1_clk>; - clock-names = "spi_clk"; - status = "disabled"; - }; - - watchdog@fffffe40 { - compatible = "atmel,at91sam9260-wdt"; - reg = <0xfffffe40 0x10>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&clk32k>; - atmel,watchdog-type = "hardware"; - atmel,reset-type = "all"; - atmel,dbg-halt; - status = "disabled"; - }; - - rtc@fffffeb0 { - compatible = "atmel,at91rm9200-rtc"; - reg = <0xfffffeb0 0x40>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&clk32k>; - status = "disabled"; - }; - - pwm0: pwm@f8034000 { - compatible = "atmel,at91sam9rl-pwm"; - reg = <0xf8034000 0x300>; - interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>; - #pwm-cells = <3>; - clocks = <&pwm_clk>; - status = "disabled"; - }; - - usb1: gadget@f803c000 { - compatible = "atmel,at91sam9260-udc"; - reg = <0xf803c000 0x4000>; - interrupts = <23 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&udphs_clk>, <&udpck>; - clock-names = "pclk", "hclk"; - status = "disabled"; - }; - }; - - usb0: ohci@500000 { - compatible = "atmel,at91rm9200-ohci", "usb-ohci"; - reg = <0x00500000 0x00100000>; - interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>; - clock-names = "ohci_clk", "hclk", "uhpck"; - status = "disabled"; - }; - - ebi: ebi@10000000 { - compatible = "atmel,at91sam9x5-ebi"; - #address-cells = <2>; - #size-cells = <1>; - atmel,smc = <&smc>; - atmel,matrix = <&matrix>; - reg = <0x10000000 0x60000000>; - ranges = <0x0 0x0 0x10000000 0x10000000 - 0x1 0x0 0x20000000 0x10000000 - 0x2 0x0 0x30000000 0x10000000 - 0x3 0x0 0x40000000 0x10000000 - 0x4 0x0 0x50000000 0x10000000 - 0x5 0x0 0x60000000 0x10000000>; - clocks = <&mck>; - status = "disabled"; - - nand_controller: nand-controller { - compatible = "atmel,at91sam9g45-nand-controller"; - ecc-engine = <&pmecc>; - #address-cells = <2>; - #size-cells = <1>; - ranges; - status = "disabled"; - }; - }; - }; - - i2c-gpio-0 { - compatible = "i2c-gpio"; - gpios = <&pioA 30 GPIO_ACTIVE_HIGH /* sda */ - &pioA 31 GPIO_ACTIVE_HIGH /* scl */ - >; - i2c-gpio,sda-open-drain; - i2c-gpio,scl-open-drain; - i2c-gpio,delay-us = <2>; /* ~100 kHz */ - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; -}; diff --git a/sys/gnu/dts/arm/at91sam9n12ek.dts b/sys/gnu/dts/arm/at91sam9n12ek.dts deleted file mode 100644 index ea5cef0b097..00000000000 --- a/sys/gnu/dts/arm/at91sam9n12ek.dts +++ /dev/null @@ -1,285 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * at91sam9n12ek.dts - Device Tree file for AT91SAM9N12-EK board - * - * Copyright (C) 2012 Atmel, - * 2012 Hong Xu - */ -/dts-v1/; -#include "at91sam9n12.dtsi" - -/ { - model = "Atmel AT91SAM9N12-EK"; - compatible = "atmel,at91sam9n12ek", "atmel,at91sam9n12", "atmel,at91sam9"; - - chosen { - bootargs = "root=/dev/mtdblock1 rw rootfstype=jffs2"; - stdout-path = "serial0:115200n8"; - }; - - memory { - reg = <0x20000000 0x8000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <16000000>; - }; - }; - - ahb { - apb { - dbgu: serial@fffff200 { - status = "okay"; - }; - - ssc0: ssc@f0010000 { - status = "okay"; - }; - - tcb0: timer@f8008000 { - timer@0 { - compatible = "atmel,tcb-timer"; - reg = <0>; - }; - - timer@1 { - compatible = "atmel,tcb-timer"; - reg = <1>; - }; - }; - - i2c0: i2c@f8010000 { - status = "okay"; - - wm8904: codec@1a { - compatible = "wlf,wm8904"; - reg = <0x1a>; - clocks = <&pck0>; - clock-names = "mclk"; - }; - - qt1070: keyboard@1b { - compatible = "qt1070"; - reg = <0x1b>; - interrupt-parent = <&pioA>; - interrupts = <2 IRQ_TYPE_EDGE_FALLING>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_qt1070_irq>; - }; - }; - - mmc0: mmc@f0008000 { - pinctrl-0 = < - &pinctrl_board_mmc0 - &pinctrl_mmc0_slot0_clk_cmd_dat0 - &pinctrl_mmc0_slot0_dat1_3>; - status = "okay"; - slot@0 { - reg = <0>; - bus-width = <4>; - cd-gpios = <&pioA 7 GPIO_ACTIVE_HIGH>; - }; - }; - - pinctrl@fffff400 { - mmc0 { - pinctrl_board_mmc0: mmc0-board { - atmel,pins = - ; /* PA7 gpio CD pin pull up and deglitch */ - }; - }; - - qt1070 { - pinctrl_qt1070_irq: qt1070_irq { - atmel,pins = - ; - }; - }; - - sound { - pinctrl_pck0_as_audio_mck: pck0_as_audio_mck { - atmel,pins = - ; - }; - }; - - usb1 { - pinctrl_usb1_vbus_sense: usb1_vbus_sense { - atmel,pins = - ; /* PB16 gpio usb vbus sense, no pull up and deglitch */ - }; - }; - }; - - spi0: spi@f0000000 { - status = "okay"; - cs-gpios = <&pioA 14 0>, <0>, <0>, <0>; - m25p80@0 { - compatible = "atmel,at25df321a"; - spi-max-frequency = <50000000>; - reg = <0>; - }; - }; - - hlcdc: hlcdc@f8038000 { - status = "okay"; - - hlcdc-display-controller { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_rgb888>; - - port@0 { - hlcdc_panel_output: endpoint@0 { - reg = <0>; - remote-endpoint = <&panel_input>; - }; - }; - }; - }; - - usb1: gadget@f803c000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb1_vbus_sense>; - atmel,vbus-gpio = <&pioB 16 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - watchdog@fffffe40 { - status = "okay"; - }; - - rtc@fffffeb0 { - status = "okay"; - }; - }; - - ebi: ebi@10000000 { - status = "okay"; - - nand_controller: nand-controller { - status = "okay"; - pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>; - pinctrl-names = "default"; - - nand@3 { - reg = <0x3 0x0 0x800000>; - rb-gpios = <&pioD 5 GPIO_ACTIVE_HIGH>; - cs-gpios = <&pioD 4 GPIO_ACTIVE_HIGH>; - nand-bus-width = <8>; - nand-ecc-mode = "soft"; - nand-ecc-strength = <2>; - nand-ecc-step-size = <512>; - nand-on-flash-bbt; - label = "atmel_nand"; - }; - }; - }; - - usb0: ohci@500000 { - num-ports = <1>; - atmel,vbus-gpio = <&pioB 7 GPIO_ACTIVE_LOW>; - status = "okay"; - }; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&hlcdc_pwm 0 50000 0>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - power-supply = <&bl_reg>; - status = "okay"; - }; - - bl_reg: backlight_regulator { - compatible = "regulator-fixed"; - regulator-name = "backlight-power-supply"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - status = "okay"; - }; - - leds { - compatible = "gpio-leds"; - - d8 { - label = "d8"; - gpios = <&pioB 4 GPIO_ACTIVE_LOW>; - linux,default-trigger = "mmc0"; - }; - - d9 { - label = "d9"; - gpios = <&pioB 5 GPIO_ACTIVE_LOW>; - linux,default-trigger = "nand-disk"; - }; - - d10 { - label = "d10"; - gpios = <&pioB 6 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - - enter { - label = "Enter"; - gpios = <&pioB 3 GPIO_ACTIVE_LOW>; - linux,code = <28>; - wakeup-source; - }; - }; - - panel: panel { - compatible = "qiaodian,qd43003c0-40", "simple-panel"; - backlight = <&backlight>; - power-supply = <&panel_reg>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - panel_input: endpoint@0 { - reg = <0>; - remote-endpoint = <&hlcdc_panel_output>; - }; - }; - }; - - panel_reg: panel_regulator { - compatible = "regulator-fixed"; - regulator-name = "panel-power-supply"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - status = "okay"; - }; - - sound { - compatible = "atmel,asoc-wm8904"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pck0_as_audio_mck>; - - atmel,model = "wm8904 @ AT91SAM9N12"; - atmel,audio-routing = - "Headphone Jack", "HPOUTL", - "Headphone Jack", "HPOUTR", - "IN2L", "Line In Jack", - "IN2R", "Line In Jack", - "Mic", "MICBIAS", - "IN1L", "Mic"; - - atmel,ssc-controller = <&ssc0>; - atmel,audio-codec = <&wm8904>; - }; -}; diff --git a/sys/gnu/dts/arm/at91sam9rl.dtsi b/sys/gnu/dts/arm/at91sam9rl.dtsi deleted file mode 100644 index ea024e4b6e0..00000000000 --- a/sys/gnu/dts/arm/at91sam9rl.dtsi +++ /dev/null @@ -1,930 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * at91sam9rl.dtsi - Device Tree Include file for AT91SAM9RL family SoC - * - * Copyright (C) 2014 Microchip - * Alexandre Belloni - */ - -#include -#include -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - model = "Atmel AT91SAM9RL family SoC"; - compatible = "atmel,at91sam9rl", "atmel,at91sam9"; - interrupt-parent = <&aic>; - - aliases { - serial0 = &dbgu; - serial1 = &usart0; - serial2 = &usart1; - serial3 = &usart2; - serial4 = &usart3; - gpio0 = &pioA; - gpio1 = &pioB; - gpio2 = &pioC; - gpio3 = &pioD; - tcb0 = &tcb0; - i2c0 = &i2c0; - i2c1 = &i2c1; - ssc0 = &ssc0; - ssc1 = &ssc1; - pwm0 = &pwm0; - }; - - cpus { - #address-cells = <0>; - #size-cells = <0>; - - cpu { - compatible = "arm,arm926ej-s"; - device_type = "cpu"; - }; - }; - - memory { - device_type = "memory"; - reg = <0x20000000 0x04000000>; - }; - - clocks { - slow_xtal: slow_xtal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - main_xtal: main_xtal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - adc_op_clk: adc_op_clk{ - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <1000000>; - }; - }; - - sram: sram@300000 { - compatible = "mmio-sram"; - reg = <0x00300000 0x10000>; - }; - - ahb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - fb0: fb@500000 { - compatible = "atmel,at91sam9rl-lcdc"; - reg = <0x00500000 0x1000>; - interrupts = <23 IRQ_TYPE_LEVEL_HIGH 3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fb>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 23>, <&pmc PMC_TYPE_PERIPHERAL 23>; - clock-names = "hclk", "lcdc_clk"; - status = "disabled"; - }; - - ebi: ebi@10000000 { - compatible = "atmel,at91sam9rl-ebi"; - #address-cells = <2>; - #size-cells = <1>; - atmel,smc = <&smc>; - atmel,matrix = <&matrix>; - reg = <0x10000000 0x80000000>; - ranges = <0x0 0x0 0x10000000 0x10000000 - 0x1 0x0 0x20000000 0x10000000 - 0x2 0x0 0x30000000 0x10000000 - 0x3 0x0 0x40000000 0x10000000 - 0x4 0x0 0x50000000 0x10000000 - 0x5 0x0 0x60000000 0x10000000>; - clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; - status = "disabled"; - - nand_controller: nand-controller { - compatible = "atmel,at91sam9g45-nand-controller"; - #address-cells = <2>; - #size-cells = <1>; - ranges; - status = "disabled"; - }; - }; - - apb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - tcb0: timer@fffa0000 { - compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xfffa0000 0x100>; - interrupts = <16 IRQ_TYPE_LEVEL_HIGH 0>, - <17 IRQ_TYPE_LEVEL_HIGH 0>, - <18 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 16>, <&pmc PMC_TYPE_PERIPHERAL 17>, <&pmc PMC_TYPE_PERIPHERAL 18>, <&clk32k>; - clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; - }; - - mmc0: mmc@fffa4000 { - compatible = "atmel,hsmci"; - reg = <0xfffa4000 0x600>; - interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; - clock-names = "mci_clk"; - status = "disabled"; - }; - - i2c0: i2c@fffa8000 { - compatible = "atmel,at91sam9260-i2c"; - reg = <0xfffa8000 0x100>; - interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; - status = "disabled"; - }; - - i2c1: i2c@fffac000 { - compatible = "atmel,at91sam9260-i2c"; - reg = <0xfffac000 0x100>; - interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - usart0: serial@fffb0000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xfffb0000 0x200>; - interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; - atmel,use-dma-rx; - atmel,use-dma-tx; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; - clock-names = "usart"; - status = "disabled"; - }; - - usart1: serial@fffb4000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xfffb4000 0x200>; - interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; - atmel,use-dma-rx; - atmel,use-dma-tx; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart1>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; - clock-names = "usart"; - status = "disabled"; - }; - - usart2: serial@fffb8000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xfffb8000 0x200>; - interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; - atmel,use-dma-rx; - atmel,use-dma-tx; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; - clock-names = "usart"; - status = "disabled"; - }; - - usart3: serial@fffbc000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xfffbc000 0x200>; - interrupts = <9 IRQ_TYPE_LEVEL_HIGH 5>; - atmel,use-dma-rx; - atmel,use-dma-tx; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart3>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; - clock-names = "usart"; - status = "disabled"; - }; - - ssc0: ssc@fffc0000 { - compatible = "atmel,at91sam9rl-ssc"; - reg = <0xfffc0000 0x4000>; - interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; - status = "disabled"; - }; - - ssc1: ssc@fffc4000 { - compatible = "atmel,at91sam9rl-ssc"; - reg = <0xfffc4000 0x4000>; - interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; - status = "disabled"; - }; - - pwm0: pwm@fffc8000 { - compatible = "atmel,at91sam9rl-pwm"; - reg = <0xfffc8000 0x300>; - interrupts = <19 IRQ_TYPE_LEVEL_HIGH 4>; - #pwm-cells = <3>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; - clock-names = "pwm_clk"; - status = "disabled"; - }; - - spi0: spi@fffcc000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "atmel,at91rm9200-spi"; - reg = <0xfffcc000 0x200>; - interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; - clock-names = "spi_clk"; - status = "disabled"; - }; - - adc0: adc@fffd0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "atmel,at91sam9rl-adc"; - reg = <0xfffd0000 0x100>; - interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 20>, <&adc_op_clk>; - clock-names = "adc_clk", "adc_op_clk"; - atmel,adc-use-external-triggers; - atmel,adc-channels-used = <0x3f>; - atmel,adc-vref = <3300>; - atmel,adc-startup-time = <40>; - atmel,adc-res = <8 10>; - atmel,adc-res-names = "lowres", "highres"; - atmel,adc-use-res = "highres"; - - trigger0 { - trigger-name = "timer-counter-0"; - trigger-value = <0x1>; - }; - trigger1 { - trigger-name = "timer-counter-1"; - trigger-value = <0x3>; - }; - - trigger2 { - trigger-name = "timer-counter-2"; - trigger-value = <0x5>; - }; - - trigger3 { - trigger-name = "external"; - trigger-value = <0x13>; - trigger-external; - }; - }; - - usb0: gadget@fffd4000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "atmel,at91sam9rl-udc"; - reg = <0x00600000 0x100000>, - <0xfffd4000 0x4000>; - interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_CORE PMC_UTMI>; - clock-names = "pclk", "hclk"; - status = "disabled"; - - ep@0 { - reg = <0>; - atmel,fifo-size = <64>; - atmel,nb-banks = <1>; - }; - - ep@1 { - reg = <1>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@2 { - reg = <2>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@3 { - reg = <3>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <3>; - atmel,can-dma; - }; - - ep@4 { - reg = <4>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <3>; - atmel,can-dma; - }; - - ep@5 { - reg = <5>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <3>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@6 { - reg = <6>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <3>; - atmel,can-dma; - atmel,can-isoc; - }; - }; - - dma0: dma-controller@ffffe600 { - compatible = "atmel,at91sam9rl-dma"; - reg = <0xffffe600 0x200>; - interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>; - #dma-cells = <2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; - clock-names = "dma_clk"; - }; - - ramc0: ramc@ffffea00 { - compatible = "atmel,at91sam9260-sdramc"; - reg = <0xffffea00 0x200>; - }; - - smc: smc@ffffec00 { - compatible = "atmel,at91sam9260-smc", "syscon"; - reg = <0xffffec00 0x200>; - }; - - matrix: matrix@ffffee00 { - compatible = "atmel,at91sam9rl-matrix", "syscon"; - reg = <0xffffee00 0x200>; - }; - - aic: interrupt-controller@fffff000 { - #interrupt-cells = <3>; - compatible = "atmel,at91rm9200-aic"; - interrupt-controller; - reg = <0xfffff000 0x200>; - atmel,external-irqs = <31>; - }; - - dbgu: serial@fffff200 { - compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; - reg = <0xfffff200 0x200>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_dbgu>; - clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; - clock-names = "usart"; - status = "disabled"; - }; - - pinctrl@fffff400 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "atmel,at91rm9200-pinctrl", "simple-bus"; - ranges = <0xfffff400 0xfffff400 0x800>; - - atmel,mux-mask = - /* A B */ - <0xffffffff 0xe05c6738>, /* pioA */ - <0xffffffff 0x0000c780>, /* pioB */ - <0xffffffff 0xe3ffff0e>, /* pioC */ - <0x003fffff 0x0001ff3c>; /* pioD */ - - /* shared pinctrl settings */ - adc0 { - pinctrl_adc0_ts: adc0_ts-0 { - atmel,pins = - , - , - , - ; - }; - - pinctrl_adc0_ad0: adc0_ad0-0 { - atmel,pins = ; - }; - - pinctrl_adc0_ad1: adc0_ad1-0 { - atmel,pins = ; - }; - - pinctrl_adc0_ad2: adc0_ad2-0 { - atmel,pins = ; - }; - - pinctrl_adc0_ad3: adc0_ad3-0 { - atmel,pins = ; - }; - - pinctrl_adc0_ad4: adc0_ad4-0 { - atmel,pins = ; - }; - - pinctrl_adc0_ad5: adc0_ad5-0 { - atmel,pins = ; - }; - - pinctrl_adc0_adtrg: adc0_adtrg-0 { - atmel,pins = ; - }; - }; - - dbgu { - pinctrl_dbgu: dbgu-0 { - atmel,pins = - , - ; - }; - }; - - ebi { - pinctrl_ebi_addr_nand: ebi-addr-0 { - atmel,pins = - , - ; - }; - }; - - fb { - pinctrl_fb: fb-0 { - atmel,pins = - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - }; - }; - - i2c_gpio0 { - pinctrl_i2c_gpio0: i2c_gpio0-0 { - atmel,pins = - , - ; - }; - }; - - i2c_gpio1 { - pinctrl_i2c_gpio1: i2c_gpio1-0 { - atmel,pins = - , - ; - }; - }; - - mmc0 { - pinctrl_mmc0_clk: mmc0_clk-0 { - atmel,pins = - ; - }; - - pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 { - atmel,pins = - , - ; - }; - - pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { - atmel,pins = - , - , - ; - }; - }; - - nand { - pinctrl_nand_rb: nand-rb-0 { - atmel,pins = - ; - }; - - pinctrl_nand_cs: nand-cs-0 { - atmel,pins = - ; - }; - - pinctrl_nand_oe_we: nand-oe-we-0 { - atmel,pins = - , - ; - }; - }; - - pwm0 { - pinctrl_pwm0_pwm0_0: pwm0_pwm0-0 { - atmel,pins = ; - }; - - pinctrl_pwm0_pwm0_1: pwm0_pwm0-1 { - atmel,pins = ; - }; - - pinctrl_pwm0_pwm0_2: pwm0_pwm0-2 { - atmel,pins = ; - }; - - pinctrl_pwm0_pwm1_0: pwm0_pwm1-0 { - atmel,pins = ; - }; - - pinctrl_pwm0_pwm1_1: pwm0_pwm1-1 { - atmel,pins = ; - }; - - pinctrl_pwm0_pwm1_2: pwm0_pwm1-2 { - atmel,pins = ; - }; - - pinctrl_pwm0_pwm2_0: pwm0_pwm2-0 { - atmel,pins = ; - }; - - pinctrl_pwm0_pwm2_1: pwm0_pwm2-1 { - atmel,pins = ; - }; - - pinctrl_pwm0_pwm2_2: pwm0_pwm2-2 { - atmel,pins = ; - }; - - pinctrl_pwm0_pwm3_0: pwm0_pwm3-0 { - atmel,pins = ; - }; - - pinctrl_pwm0_pwm3_1: pwm0_pwm3-1 { - atmel,pins = ; - }; - }; - - spi0 { - pinctrl_spi0: spi0-0 { - atmel,pins = - , - , - ; - }; - }; - - ssc0 { - pinctrl_ssc0_tx: ssc0_tx-0 { - atmel,pins = - , - , - ; - }; - - pinctrl_ssc0_rx: ssc0_rx-0 { - atmel,pins = - , - , - ; - }; - }; - - ssc1 { - pinctrl_ssc1_tx: ssc1_tx-0 { - atmel,pins = - , - , - ; - }; - - pinctrl_ssc1_rx: ssc1_rx-0 { - atmel,pins = - , - , - ; - }; - }; - - tcb0 { - pinctrl_tcb0_tclk0: tcb0_tclk0-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tclk1: tcb0_tclk1-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tclk2: tcb0_tclk2-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tioa0: tcb0_tioa0-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tioa1: tcb0_tioa1-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tioa2: tcb0_tioa2-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tiob0: tcb0_tiob0-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tiob1: tcb0_tiob1-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tiob2: tcb0_tiob2-0 { - atmel,pins = ; - }; - }; - - usart0 { - pinctrl_usart0: usart0-0 { - atmel,pins = - , - ; - }; - - pinctrl_usart0_rts: usart0_rts-0 { - atmel,pins = - ; - }; - - pinctrl_usart0_cts: usart0_cts-0 { - atmel,pins = - ; - }; - - pinctrl_usart0_dtr_dsr: usart0_dtr_dsr-0 { - atmel,pins = - , - ; - }; - - pinctrl_usart0_dcd: usart0_dcd-0 { - atmel,pins = - ; - }; - - pinctrl_usart0_ri: usart0_ri-0 { - atmel,pins = - ; - }; - - pinctrl_usart0_sck: usart0_sck-0 { - atmel,pins = - ; - }; - }; - - usart1 { - pinctrl_usart1: usart1-0 { - atmel,pins = - , - ; - }; - - pinctrl_usart1_rts: usart1_rts-0 { - atmel,pins = - ; - }; - - pinctrl_usart1_cts: usart1_cts-0 { - atmel,pins = - ; - }; - - pinctrl_usart1_sck: usart1_sck-0 { - atmel,pins = - ; - }; - }; - - usart2 { - pinctrl_usart2: usart2-0 { - atmel,pins = - , - ; - }; - - pinctrl_usart2_rts: usart2_rts-0 { - atmel,pins = - ; - }; - - pinctrl_usart2_cts: usart2_cts-0 { - atmel,pins = - ; - }; - - pinctrl_usart2_sck: usart2_sck-0 { - atmel,pins = - ; - }; - }; - - usart3 { - pinctrl_usart3: usart3-0 { - atmel,pins = - , - ; - }; - - pinctrl_usart3_rts: usart3_rts-0 { - atmel,pins = - ; - }; - - pinctrl_usart3_cts: usart3_cts-0 { - atmel,pins = - ; - }; - - pinctrl_usart3_sck: usart3_sck-0 { - atmel,pins = - ; - }; - }; - - pioA: gpio@fffff400 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff400 0x200>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; - }; - - pioB: gpio@fffff600 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff600 0x200>; - interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 3>; - }; - - pioC: gpio@fffff800 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff800 0x200>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 4>; - }; - - pioD: gpio@fffffa00 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffffa00 0x200>; - interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; - }; - }; - - pmc: pmc@fffffc00 { - compatible = "atmel,at91sam9rl-pmc", "syscon"; - reg = <0xfffffc00 0x100>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - #clock-cells = <2>; - clocks = <&clk32k>, <&main_xtal>; - clock-names = "slow_clk", "main_xtal"; - }; - - rstc@fffffd00 { - compatible = "atmel,at91sam9260-rstc"; - reg = <0xfffffd00 0x10>; - clocks = <&clk32k>; - }; - - shdwc@fffffd10 { - compatible = "atmel,at91sam9260-shdwc"; - reg = <0xfffffd10 0x10>; - clocks = <&clk32k>; - }; - - pit: timer@fffffd30 { - compatible = "atmel,at91sam9260-pit"; - reg = <0xfffffd30 0xf>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; - }; - - watchdog@fffffd40 { - compatible = "atmel,at91sam9260-wdt"; - reg = <0xfffffd40 0x10>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&clk32k>; - status = "disabled"; - }; - - clk32k: sckc@fffffd50 { - compatible = "atmel,at91sam9x5-sckc"; - reg = <0xfffffd50 0x4>; - clocks = <&slow_xtal>; - #clock-cells = <0>; - }; - - rtc@fffffd20 { - compatible = "atmel,at91sam9260-rtt"; - reg = <0xfffffd20 0x10>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&clk32k>; - status = "disabled"; - }; - - gpbr: syscon@fffffd60 { - compatible = "atmel,at91sam9260-gpbr", "syscon"; - reg = <0xfffffd60 0x10>; - status = "disabled"; - }; - - rtc@fffffe00 { - compatible = "atmel,at91rm9200-rtc"; - reg = <0xfffffe00 0x40>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&clk32k>; - status = "disabled"; - }; - - }; - }; - - i2c-gpio-0 { - compatible = "i2c-gpio"; - gpios = <&pioA 23 GPIO_ACTIVE_HIGH>, /* sda */ - <&pioA 24 GPIO_ACTIVE_HIGH>; /* scl */ - i2c-gpio,sda-open-drain; - i2c-gpio,scl-open-drain; - i2c-gpio,delay-us = <2>; /* ~100 kHz */ - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c_gpio0>; - status = "disabled"; - }; - - i2c-gpio-1 { - compatible = "i2c-gpio"; - gpios = <&pioD 10 GPIO_ACTIVE_HIGH>, /* sda */ - <&pioD 11 GPIO_ACTIVE_HIGH>; /* scl */ - i2c-gpio,sda-open-drain; - i2c-gpio,scl-open-drain; - i2c-gpio,delay-us = <2>; /* ~100 kHz */ - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c_gpio1>; - status = "disabled"; - }; -}; diff --git a/sys/gnu/dts/arm/at91sam9rlek.dts b/sys/gnu/dts/arm/at91sam9rlek.dts deleted file mode 100644 index 0de75d3c4f1..00000000000 --- a/sys/gnu/dts/arm/at91sam9rlek.dts +++ /dev/null @@ -1,272 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * at91sam9rlek.dts - Device Tree file for Atmel at91sam9rl reference board - * - * Copyright (C) 2014 Microchip - * Alexandre Belloni - */ -/dts-v1/; -#include "at91sam9rl.dtsi" - -/ { - model = "Atmel at91sam9rlek"; - compatible = "atmel,at91sam9rlek", "atmel,at91sam9rl", "atmel,at91sam9"; - - chosen { - bootargs = "rootfstype=ubifs root=ubi0:rootfs ubi.mtd=5 rw"; - stdout-path = "serial0:115200n8"; - }; - - memory { - reg = <0x20000000 0x4000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <12000000>; - }; - }; - - ahb { - fb0: fb@500000 { - display = <&display0>; - status = "okay"; - - display0: panel { - bits-per-pixel = <16>; - atmel,lcdcon-backlight; - atmel,dmacon = <0x1>; - atmel,lcdcon2 = <0x80008002>; - atmel,guard-time = <1>; - atmel,lcd-wiring-mode = "RGB"; - - display-timings { - native-mode = <&timing0>; - timing0: timing0 { - clock-frequency = <4965000>; - hactive = <240>; - vactive = <320>; - hback-porch = <1>; - hfront-porch = <33>; - vback-porch = <1>; - vfront-porch = <0>; - hsync-len = <5>; - vsync-len = <1>; - hsync-active = <1>; - vsync-active = <1>; - }; - }; - }; - }; - - ebi: ebi@10000000 { - pinctrl-0 = <&pinctrl_ebi_addr_nand>; - pinctrl-names = "default"; - status = "okay"; - - nand_controller: nand-controller { - status = "okay"; - pinctrl-0 = <&pinctrl_nand_oe_we - &pinctrl_nand_cs - &pinctrl_nand_rb>; - pinctrl-names = "default"; - - nand@3 { - reg = <0x3 0x0 0x800000>; - rb-gpios = <&pioD 17 GPIO_ACTIVE_HIGH>; - cs-gpios = <&pioB 6 GPIO_ACTIVE_HIGH>; - nand-bus-width = <8>; - nand-ecc-mode = "soft"; - nand-on-flash-bbt; - label = "atmel_nand"; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - at91bootstrap@0 { - label = "at91bootstrap"; - reg = <0x0 0x40000>; - }; - - bootloader@40000 { - label = "bootloader"; - reg = <0x40000 0x80000>; - }; - - bootloaderenv@c0000 { - label = "bootloader env"; - reg = <0xc0000 0xc0000>; - }; - - dtb@180000 { - label = "device tree"; - reg = <0x180000 0x80000>; - }; - - kernel@200000 { - label = "kernel"; - reg = <0x200000 0x600000>; - }; - - rootfs@800000 { - label = "rootfs"; - reg = <0x800000 0x0f800000>; - }; - }; - }; - }; - }; - - apb { - tcb0: timer@fffa0000 { - timer@0 { - compatible = "atmel,tcb-timer"; - reg = <0>, <1>; - }; - - timer@2 { - compatible = "atmel,tcb-timer"; - reg = <2>; - }; - }; - - mmc0: mmc@fffa4000 { - pinctrl-0 = < - &pinctrl_board_mmc0 - &pinctrl_mmc0_clk - &pinctrl_mmc0_slot0_cmd_dat0 - &pinctrl_mmc0_slot0_dat1_3>; - status = "okay"; - slot@0 { - reg = <0>; - bus-width = <4>; - cd-gpios = <&pioA 15 GPIO_ACTIVE_HIGH>; - }; - }; - - usart0: serial@fffb0000 { - pinctrl-0 = < - &pinctrl_usart0 - &pinctrl_usart0_rts - &pinctrl_usart0_cts>; - status = "okay"; - }; - - adc0: adc@fffd0000 { - pinctrl-names = "default"; - pinctrl-0 = < - &pinctrl_adc0_ad0 - &pinctrl_adc0_ad1 - &pinctrl_adc0_ad2 - &pinctrl_adc0_ad3 - &pinctrl_adc0_ad4 - &pinctrl_adc0_ad5 - &pinctrl_adc0_adtrg>; - atmel,adc-ts-wires = <4>; - status = "okay"; - }; - - usb0: gadget@fffd4000 { - atmel,vbus-gpio = <&pioA 8 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - spi0: spi@fffcc000 { - status = "okay"; - cs-gpios = <&pioA 28 0>, <0>, <0>, <0>; - mtd_dataflash@0 { - compatible = "atmel,at45", "atmel,dataflash"; - spi-max-frequency = <15000000>; - reg = <0>; - }; - }; - - pwm0: pwm@fffc8000 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm0_pwm1_2>, - <&pinctrl_pwm0_pwm2_2>; - }; - - dbgu: serial@fffff200 { - status = "okay"; - }; - - pinctrl@fffff400 { - mmc0 { - pinctrl_board_mmc0: mmc0-board { - atmel,pins = - ; - }; - }; - }; - - watchdog@fffffd40 { - status = "okay"; - }; - - rtc@fffffe00 { - status = "okay"; - }; - }; - }; - - pwmleds { - compatible = "pwm-leds"; - - ds1 { - label = "ds1"; - pwms = <&pwm0 1 5000 PWM_POLARITY_INVERTED>; - max-brightness = <255>; - }; - - ds2 { - label = "ds2"; - pwms = <&pwm0 2 5000 PWM_POLARITY_INVERTED>; - max-brightness = <255>; - }; - }; - - leds { - compatible = "gpio-leds"; - - ds3 { - label = "ds3"; - gpios = <&pioD 14 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - - right_click { - label = "right_click"; - gpios = <&pioB 0 GPIO_ACTIVE_LOW>; - linux,code = <273>; - wakeup-source; - }; - - left_click { - label = "left_click"; - gpios = <&pioB 1 GPIO_ACTIVE_LOW>; - linux,code = <272>; - wakeup-source; - }; - }; - - i2c-gpio-0 { - status = "okay"; - }; - - i2c-gpio-1 { - status = "okay"; - }; -}; diff --git a/sys/gnu/dts/arm/at91sam9x25.dtsi b/sys/gnu/dts/arm/at91sam9x25.dtsi deleted file mode 100644 index 0fe8802e124..00000000000 --- a/sys/gnu/dts/arm/at91sam9x25.dtsi +++ /dev/null @@ -1,35 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * at91sam9x25.dtsi - Device Tree Include file for AT91SAM9X25 SoC - * - * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD - */ - -#include "at91sam9x5.dtsi" -#include "at91sam9x5_usart3.dtsi" -#include "at91sam9x5_macb0.dtsi" -#include "at91sam9x5_macb1.dtsi" -#include "at91sam9x5_can.dtsi" - -/ { - model = "Atmel AT91SAM9X25 SoC"; - compatible = "atmel,at91sam9x25", "atmel,at91sam9x5"; - - ahb { - apb { - pinctrl@fffff400 { - atmel,mux-mask = < - /* A B C */ - 0xffffffff 0xffe03fff 0xc000001c /* pioA */ - 0x0007ffff 0x00047e3f 0x00000000 /* pioB */ - 0x80000000 0xfffd0000 0xb83fffff /* pioC */ - 0x003fffff 0x003f8000 0x00000000 /* pioD */ - >; - }; - - pmc: pmc@fffffc00 { - compatible = "atmel,at91sam9x25-pmc", "atmel,at91sam9x5-pmc", "syscon"; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/at91sam9x25ek.dts b/sys/gnu/dts/arm/at91sam9x25ek.dts deleted file mode 100644 index ad7c6b36f0b..00000000000 --- a/sys/gnu/dts/arm/at91sam9x25ek.dts +++ /dev/null @@ -1,35 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * at91sam9x25ek.dts - Device Tree file for AT91SAM9X25-EK board - * - * Copyright (C) 2012 Atmel, - * 2012 Nicolas Ferre - */ -/dts-v1/; -#include "at91sam9x25.dtsi" -#include "at91sam9x5ek.dtsi" - -/ { - model = "Atmel AT91SAM9X25-EK"; - compatible = "atmel,at91sam9x25ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9"; -}; - -&can1 { - status = "okay"; -}; - -&macb0 { - phy-mode = "rmii"; - status = "okay"; -}; - -&macb1 { - phy-mode = "rmii"; - status = "okay"; -}; - -&pwm0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm0_pwm0_1>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/at91sam9x35.dtsi b/sys/gnu/dts/arm/at91sam9x35.dtsi deleted file mode 100644 index 0bfa21f18f8..00000000000 --- a/sys/gnu/dts/arm/at91sam9x35.dtsi +++ /dev/null @@ -1,34 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * at91sam9x35.dtsi - Device Tree Include file for AT91SAM9X35 SoC - * - * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD - */ - -#include "at91sam9x5.dtsi" -#include "at91sam9x5_lcd.dtsi" -#include "at91sam9x5_macb0.dtsi" -#include "at91sam9x5_can.dtsi" - -/ { - model = "Atmel AT91SAM9X35 SoC"; - compatible = "atmel,at91sam9x35", "atmel,at91sam9x5"; - - ahb { - apb { - pinctrl@fffff400 { - atmel,mux-mask = < - /* A B C */ - 0xffffffff 0xffe03fff 0xc000000c /* pioA */ - 0x000406ff 0x00047e3f 0x00000000 /* pioB */ - 0xfdffffff 0x00000000 0xb83fffff /* pioC */ - 0x003fffff 0x003f8000 0x00000000 /* pioD */ - >; - }; - - pmc: pmc@fffffc00 { - compatible = "atmel,at91sam9x35-pmc", "atmel,at91sam9x5-pmc", "syscon"; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/at91sam9x35ek.dts b/sys/gnu/dts/arm/at91sam9x35ek.dts deleted file mode 100644 index 66675c787b9..00000000000 --- a/sys/gnu/dts/arm/at91sam9x35ek.dts +++ /dev/null @@ -1,41 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * at91sam9x35ek.dts - Device Tree file for AT91SAM9X35-EK board - * - * Copyright (C) 2012 Atmel, - * 2012 Nicolas Ferre - */ -/dts-v1/; -#include "at91sam9x35.dtsi" -#include "at91sam9x5dm.dtsi" -#include "at91sam9x5ek.dtsi" - -/ { - model = "Atmel AT91SAM9X35-EK"; - compatible = "atmel,at91sam9x35ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9"; -}; - -&backlight { - status = "okay"; -}; - -&bl_reg { - status = "okay"; -}; - -&hlcdc { - status = "okay"; -}; - -&macb0 { - phy-mode = "rmii"; - status = "okay"; -}; - -&panel { - status = "okay"; -}; - -&panel_reg { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/at91sam9x5.dtsi b/sys/gnu/dts/arm/at91sam9x5.dtsi deleted file mode 100644 index 7c2eb93f8ca..00000000000 --- a/sys/gnu/dts/arm/at91sam9x5.dtsi +++ /dev/null @@ -1,1051 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * at91sam9x5.dtsi - Device Tree Include file for AT91SAM9x5 family SoC - * applies to AT91SAM9G15, AT91SAM9G25, AT91SAM9G35, - * AT91SAM9X25, AT91SAM9X35 SoC - * - * Copyright (C) 2012 Atmel, - * 2012 Nicolas Ferre - */ - -#include -#include -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - model = "Atmel AT91SAM9x5 family SoC"; - compatible = "atmel,at91sam9x5"; - interrupt-parent = <&aic>; - - aliases { - serial0 = &dbgu; - serial1 = &usart0; - serial2 = &usart1; - serial3 = &usart2; - gpio0 = &pioA; - gpio1 = &pioB; - gpio2 = &pioC; - gpio3 = &pioD; - tcb0 = &tcb0; - tcb1 = &tcb1; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - ssc0 = &ssc0; - pwm0 = &pwm0; - }; - cpus { - #address-cells = <0>; - #size-cells = <0>; - - cpu { - compatible = "arm,arm926ej-s"; - device_type = "cpu"; - }; - }; - - memory { - device_type = "memory"; - reg = <0x20000000 0x10000000>; - }; - - clocks { - slow_xtal: slow_xtal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - main_xtal: main_xtal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - adc_op_clk: adc_op_clk{ - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <1000000>; - }; - }; - - sram: sram@300000 { - compatible = "mmio-sram"; - reg = <0x00300000 0x8000>; - }; - - ahb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - apb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - aic: interrupt-controller@fffff000 { - #interrupt-cells = <3>; - compatible = "atmel,at91rm9200-aic"; - interrupt-controller; - reg = <0xfffff000 0x200>; - atmel,external-irqs = <31>; - }; - - matrix: matrix@ffffde00 { - compatible = "atmel,at91sam9x5-matrix", "syscon"; - reg = <0xffffde00 0x100>; - }; - - pmecc: ecc-engine@ffffe000 { - compatible = "atmel,at91sam9g45-pmecc"; - reg = <0xffffe000 0x600>, - <0xffffe600 0x200>; - }; - - ramc0: ramc@ffffe800 { - compatible = "atmel,at91sam9g45-ddramc"; - reg = <0xffffe800 0x200>; - clocks = <&pmc PMC_TYPE_SYSTEM 2>; - clock-names = "ddrck"; - }; - - smc: smc@ffffea00 { - compatible = "atmel,at91sam9260-smc", "syscon"; - reg = <0xffffea00 0x200>; - }; - - pmc: pmc@fffffc00 { - compatible = "atmel,at91sam9x5-pmc", "syscon"; - reg = <0xfffffc00 0x200>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - #clock-cells = <2>; - clocks = <&clk32k>, <&main_xtal>; - clock-names = "slow_clk", "main_xtal"; - }; - - reset_controller: rstc@fffffe00 { - compatible = "atmel,at91sam9g45-rstc"; - reg = <0xfffffe00 0x10>; - clocks = <&clk32k>; - }; - - shutdown_controller: shdwc@fffffe10 { - compatible = "atmel,at91sam9x5-shdwc"; - reg = <0xfffffe10 0x10>; - clocks = <&clk32k>; - }; - - pit: timer@fffffe30 { - compatible = "atmel,at91sam9260-pit"; - reg = <0xfffffe30 0xf>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; - }; - - clk32k: sckc@fffffe50 { - compatible = "atmel,at91sam9x5-sckc"; - reg = <0xfffffe50 0x4>; - clocks = <&slow_xtal>; - #clock-cells = <0>; - }; - - tcb0: timer@f8008000 { - compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xf8008000 0x100>; - interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&clk32k>; - clock-names = "t0_clk", "slow_clk"; - }; - - tcb1: timer@f800c000 { - compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xf800c000 0x100>; - interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&clk32k>; - clock-names = "t0_clk", "slow_clk"; - }; - - dma0: dma-controller@ffffec00 { - compatible = "atmel,at91sam9g45-dma"; - reg = <0xffffec00 0x200>; - interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; - #dma-cells = <2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; - clock-names = "dma_clk"; - }; - - dma1: dma-controller@ffffee00 { - compatible = "atmel,at91sam9g45-dma"; - reg = <0xffffee00 0x200>; - interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>; - #dma-cells = <2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; - clock-names = "dma_clk"; - }; - - pinctrl: pinctrl@fffff400 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus"; - ranges = <0xfffff400 0xfffff400 0x800>; - - /* shared pinctrl settings */ - dbgu { - pinctrl_dbgu: dbgu-0 { - atmel,pins = - ; - }; - }; - - ebi { - pinctrl_ebi_data_0_7: ebi-data-lsb-0 { - atmel,pins = - ; - }; - - pinctrl_ebi_data_8_15: ebi-data-msb-0 { - atmel,pins = - ; - }; - - pinctrl_ebi_addr_nand: ebi-addr-0 { - atmel,pins = - ; - }; - }; - - usart0 { - pinctrl_usart0: usart0-0 { - atmel,pins = - ; - }; - - pinctrl_usart0_rts: usart0_rts-0 { - atmel,pins = - ; /* PA2 periph A */ - }; - - pinctrl_usart0_cts: usart0_cts-0 { - atmel,pins = - ; /* PA3 periph A */ - }; - - pinctrl_usart0_sck: usart0_sck-0 { - atmel,pins = - ; /* PA4 periph A */ - }; - }; - - usart1 { - pinctrl_usart1: usart1-0 { - atmel,pins = - ; - }; - - pinctrl_usart1_rts: usart1_rts-0 { - atmel,pins = - ; /* PC27 periph C */ - }; - - pinctrl_usart1_cts: usart1_cts-0 { - atmel,pins = - ; /* PC28 periph C */ - }; - - pinctrl_usart1_sck: usart1_sck-0 { - atmel,pins = - ; /* PC29 periph C */ - }; - }; - - usart2 { - pinctrl_usart2: usart2-0 { - atmel,pins = - ; - }; - - pinctrl_usart2_rts: usart2_rts-0 { - atmel,pins = - ; /* PB0 periph B */ - }; - - pinctrl_usart2_cts: usart2_cts-0 { - atmel,pins = - ; /* PB1 periph B */ - }; - - pinctrl_usart2_sck: usart2_sck-0 { - atmel,pins = - ; /* PB2 periph B */ - }; - }; - - uart0 { - pinctrl_uart0: uart0-0 { - atmel,pins = - ; /* PC9 periph C with pullup */ - }; - }; - - uart1 { - pinctrl_uart1: uart1-0 { - atmel,pins = - ; /* PC17 periph C with pullup */ - }; - }; - - nand { - pinctrl_nand_oe_we: nand-oe-we-0 { - atmel,pins = - ; - }; - - pinctrl_nand_rb: nand-rb-0 { - atmel,pins = - ; - }; - - pinctrl_nand_cs: nand-cs-0 { - atmel,pins = - ; - }; - }; - - mmc0 { - pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 { - atmel,pins = - ; /* PA15 periph A with pullup */ - }; - - pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { - atmel,pins = - ; /* PA20 periph A with pullup */ - }; - }; - - mmc1 { - pinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 { - atmel,pins = - ; /* PA11 periph B with pullup */ - }; - - pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 { - atmel,pins = - ; /* PA4 periph B with pullup */ - }; - }; - - ssc0 { - pinctrl_ssc0_tx: ssc0_tx-0 { - atmel,pins = - ; /* PA26 periph B */ - }; - - pinctrl_ssc0_rx: ssc0_rx-0 { - atmel,pins = - ; /* PA29 periph B */ - }; - }; - - spi0 { - pinctrl_spi0: spi0-0 { - atmel,pins = - ; /* PA13 periph A SPI0_SPCK pin */ - }; - }; - - spi1 { - pinctrl_spi1: spi1-0 { - atmel,pins = - ; /* PA23 periph B SPI1_SPCK pin */ - }; - }; - - i2c0 { - pinctrl_i2c0: i2c0-0 { - atmel,pins = - ; /* PA31 periph A I2C0 clock */ - }; - }; - - i2c1 { - pinctrl_i2c1: i2c1-0 { - atmel,pins = - ; /* PC1 periph C I2C1 clock */ - }; - }; - - i2c2 { - pinctrl_i2c2: i2c2-0 { - atmel,pins = - ; /* PB5 periph B I2C2 clock */ - }; - }; - - i2c_gpio0 { - pinctrl_i2c_gpio0: i2c_gpio0-0 { - atmel,pins = - ; /* PA31 gpio multidrive I2C0 clock */ - }; - }; - - i2c_gpio1 { - pinctrl_i2c_gpio1: i2c_gpio1-0 { - atmel,pins = - ; /* PC1 gpio multidrive I2C1 clock */ - }; - }; - - i2c_gpio2 { - pinctrl_i2c_gpio2: i2c_gpio2-0 { - atmel,pins = - ; /* PB5 gpio multidrive I2C2 clock */ - }; - }; - - pwm0 { - pinctrl_pwm0_pwm0_0: pwm0_pwm0-0 { - atmel,pins = - ; - }; - pinctrl_pwm0_pwm0_1: pwm0_pwm0-1 { - atmel,pins = - ; - }; - pinctrl_pwm0_pwm0_2: pwm0_pwm0-2 { - atmel,pins = - ; - }; - - pinctrl_pwm0_pwm1_0: pwm0_pwm1-0 { - atmel,pins = - ; - }; - pinctrl_pwm0_pwm1_1: pwm0_pwm1-1 { - atmel,pins = - ; - }; - pinctrl_pwm0_pwm1_2: pwm0_pwm1-2 { - atmel,pins = - ; - }; - - pinctrl_pwm0_pwm2_0: pwm0_pwm2-0 { - atmel,pins = - ; - }; - pinctrl_pwm0_pwm2_1: pwm0_pwm2-1 { - atmel,pins = - ; - }; - - pinctrl_pwm0_pwm3_0: pwm0_pwm3-0 { - atmel,pins = - ; - }; - pinctrl_pwm0_pwm3_1: pwm0_pwm3-1 { - atmel,pins = - ; - }; - }; - - tcb0 { - pinctrl_tcb0_tclk0: tcb0_tclk0-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tclk1: tcb0_tclk1-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tclk2: tcb0_tclk2-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tioa0: tcb0_tioa0-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tioa1: tcb0_tioa1-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tioa2: tcb0_tioa2-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tiob0: tcb0_tiob0-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tiob1: tcb0_tiob1-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tiob2: tcb0_tiob2-0 { - atmel,pins = ; - }; - }; - - tcb1 { - pinctrl_tcb1_tclk0: tcb1_tclk0-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tclk1: tcb1_tclk1-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tclk2: tcb1_tclk2-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tioa0: tcb1_tioa0-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tioa1: tcb1_tioa1-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tioa2: tcb1_tioa2-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tiob0: tcb1_tiob0-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tiob1: tcb1_tiob1-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tiob2: tcb1_tiob2-0 { - atmel,pins = ; - }; - }; - - pioA: gpio@fffff400 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfffff400 0x200>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; - }; - - pioB: gpio@fffff600 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfffff600 0x200>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - #gpio-lines = <19>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; - }; - - pioC: gpio@fffff800 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfffff800 0x200>; - interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 3>; - }; - - pioD: gpio@fffffa00 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfffffa00 0x200>; - interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - #gpio-lines = <22>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 3>; - }; - }; - - ssc0: ssc@f0010000 { - compatible = "atmel,at91sam9g45-ssc"; - reg = <0xf0010000 0x4000>; - interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>; - dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(13)>, - <&dma0 1 AT91_DMA_CFG_PER_ID(14)>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 28>; - clock-names = "pclk"; - status = "disabled"; - }; - - mmc0: mmc@f0008000 { - compatible = "atmel,hsmci"; - reg = <0xf0008000 0x600>; - interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; - dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(0)>; - dma-names = "rxtx"; - pinctrl-names = "default"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 12>; - clock-names = "mci_clk"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - mmc1: mmc@f000c000 { - compatible = "atmel,hsmci"; - reg = <0xf000c000 0x600>; - interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>; - dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(0)>; - dma-names = "rxtx"; - pinctrl-names = "default"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 26>; - clock-names = "mci_clk"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - dbgu: serial@fffff200 { - compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; - reg = <0xfffff200 0x200>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_dbgu>; - dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(8)>, - <&dma1 1 (AT91_DMA_CFG_PER_ID(9) | AT91_DMA_CFG_FIFOCFG_ASAP)>; - dma-names = "tx", "rx"; - clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; - clock-names = "usart"; - status = "disabled"; - }; - - usart0: serial@f801c000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xf801c000 0x200>; - interrupts = <5 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart0>; - dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(3)>, - <&dma0 1 (AT91_DMA_CFG_PER_ID(4) | AT91_DMA_CFG_FIFOCFG_ASAP)>; - dma-names = "tx", "rx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; - clock-names = "usart"; - status = "disabled"; - }; - - usart1: serial@f8020000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xf8020000 0x200>; - interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart1>; - dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(5)>, - <&dma0 1 (AT91_DMA_CFG_PER_ID(6) | AT91_DMA_CFG_FIFOCFG_ASAP)>; - dma-names = "tx", "rx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; - clock-names = "usart"; - status = "disabled"; - }; - - usart2: serial@f8024000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xf8024000 0x200>; - interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart2>; - dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(12)>, - <&dma1 1 (AT91_DMA_CFG_PER_ID(13) | AT91_DMA_CFG_FIFOCFG_ASAP)>; - dma-names = "tx", "rx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; - clock-names = "usart"; - status = "disabled"; - }; - - i2c0: i2c@f8010000 { - compatible = "atmel,at91sam9x5-i2c"; - reg = <0xf8010000 0x100>; - interrupts = <9 IRQ_TYPE_LEVEL_HIGH 6>; - dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(7)>, - <&dma0 1 AT91_DMA_CFG_PER_ID(8)>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; - status = "disabled"; - }; - - i2c1: i2c@f8014000 { - compatible = "atmel,at91sam9x5-i2c"; - reg = <0xf8014000 0x100>; - interrupts = <10 IRQ_TYPE_LEVEL_HIGH 6>; - dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(5)>, - <&dma1 1 AT91_DMA_CFG_PER_ID(6)>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; - status = "disabled"; - }; - - i2c2: i2c@f8018000 { - compatible = "atmel,at91sam9x5-i2c"; - reg = <0xf8018000 0x100>; - interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>; - dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(9)>, - <&dma0 1 AT91_DMA_CFG_PER_ID(10)>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; - status = "disabled"; - }; - - uart0: serial@f8040000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xf8040000 0x200>; - interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 15>; - clock-names = "usart"; - status = "disabled"; - }; - - uart1: serial@f8044000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xf8044000 0x200>; - interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 16>; - clock-names = "usart"; - status = "disabled"; - }; - - adc0: adc@f804c000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "atmel,at91sam9x5-adc"; - reg = <0xf804c000 0x100>; - interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 19>, - <&adc_op_clk>; - clock-names = "adc_clk", "adc_op_clk"; - atmel,adc-use-external-triggers; - atmel,adc-channels-used = <0xffff>; - atmel,adc-vref = <3300>; - atmel,adc-startup-time = <40>; - atmel,adc-sample-hold-time = <11>; - atmel,adc-res = <8 10>; - atmel,adc-res-names = "lowres", "highres"; - atmel,adc-use-res = "highres"; - - trigger0 { - trigger-name = "external-rising"; - trigger-value = <0x1>; - trigger-external; - }; - - trigger1 { - trigger-name = "external-falling"; - trigger-value = <0x2>; - trigger-external; - }; - - trigger2 { - trigger-name = "external-any"; - trigger-value = <0x3>; - trigger-external; - }; - - trigger3 { - trigger-name = "continuous"; - trigger-value = <0x6>; - }; - }; - - spi0: spi@f0000000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "atmel,at91rm9200-spi"; - reg = <0xf0000000 0x100>; - interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>; - dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(1)>, - <&dma0 1 AT91_DMA_CFG_PER_ID(2)>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; - clock-names = "spi_clk"; - status = "disabled"; - }; - - spi1: spi@f0004000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "atmel,at91rm9200-spi"; - reg = <0xf0004000 0x100>; - interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>; - dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(1)>, - <&dma1 1 AT91_DMA_CFG_PER_ID(2)>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; - clock-names = "spi_clk"; - status = "disabled"; - }; - - usb2: gadget@f803c000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "atmel,at91sam9g45-udc"; - reg = <0x00500000 0x80000 - 0xf803c000 0x400>; - interrupts = <23 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 23>; - clock-names = "hclk", "pclk"; - status = "disabled"; - - ep@0 { - reg = <0>; - atmel,fifo-size = <64>; - atmel,nb-banks = <1>; - }; - - ep@1 { - reg = <1>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@2 { - reg = <2>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@3 { - reg = <3>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <3>; - atmel,can-dma; - }; - - ep@4 { - reg = <4>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <3>; - atmel,can-dma; - }; - - ep@5 { - reg = <5>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <3>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@6 { - reg = <6>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <3>; - atmel,can-dma; - atmel,can-isoc; - }; - }; - - watchdog: watchdog@fffffe40 { - compatible = "atmel,at91sam9260-wdt"; - reg = <0xfffffe40 0x10>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&clk32k>; - atmel,watchdog-type = "hardware"; - atmel,reset-type = "all"; - atmel,dbg-halt; - status = "disabled"; - }; - - rtc: rtc@fffffeb0 { - compatible = "atmel,at91sam9x5-rtc"; - reg = <0xfffffeb0 0x40>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&clk32k>; - status = "disabled"; - }; - - pwm0: pwm@f8034000 { - compatible = "atmel,at91sam9rl-pwm"; - reg = <0xf8034000 0x300>; - interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 18>; - #pwm-cells = <3>; - status = "disabled"; - }; - }; - - usb0: ohci@600000 { - compatible = "atmel,at91rm9200-ohci", "usb-ohci"; - reg = <0x00600000 0x100000>; - interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_SYSTEM 6>; - clock-names = "ohci_clk", "hclk", "uhpck"; - status = "disabled"; - }; - - usb1: ehci@700000 { - compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; - reg = <0x00700000 0x100000>; - interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 22>; - clock-names = "usb_clk", "ehci_clk"; - status = "disabled"; - }; - - ebi: ebi@10000000 { - compatible = "atmel,at91sam9x5-ebi"; - #address-cells = <2>; - #size-cells = <1>; - atmel,smc = <&smc>; - atmel,matrix = <&matrix>; - reg = <0x10000000 0x60000000>; - ranges = <0x0 0x0 0x10000000 0x10000000 - 0x1 0x0 0x20000000 0x10000000 - 0x2 0x0 0x30000000 0x10000000 - 0x3 0x0 0x40000000 0x10000000 - 0x4 0x0 0x50000000 0x10000000 - 0x5 0x0 0x60000000 0x10000000>; - clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; - status = "disabled"; - - nand_controller: nand-controller { - compatible = "atmel,at91sam9g45-nand-controller"; - ecc-engine = <&pmecc>; - #address-cells = <2>; - #size-cells = <1>; - ranges; - status = "disabled"; - }; - }; - }; - - i2c-gpio-0 { - compatible = "i2c-gpio"; - gpios = <&pioA 30 GPIO_ACTIVE_HIGH /* sda */ - &pioA 31 GPIO_ACTIVE_HIGH /* scl */ - >; - i2c-gpio,sda-open-drain; - i2c-gpio,scl-open-drain; - i2c-gpio,delay-us = <2>; /* ~100 kHz */ - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c_gpio0>; - status = "disabled"; - }; - - i2c-gpio-1 { - compatible = "i2c-gpio"; - gpios = <&pioC 0 GPIO_ACTIVE_HIGH /* sda */ - &pioC 1 GPIO_ACTIVE_HIGH /* scl */ - >; - i2c-gpio,sda-open-drain; - i2c-gpio,scl-open-drain; - i2c-gpio,delay-us = <2>; /* ~100 kHz */ - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c_gpio1>; - status = "disabled"; - }; - - i2c-gpio-2 { - compatible = "i2c-gpio"; - gpios = <&pioB 4 GPIO_ACTIVE_HIGH /* sda */ - &pioB 5 GPIO_ACTIVE_HIGH /* scl */ - >; - i2c-gpio,sda-open-drain; - i2c-gpio,scl-open-drain; - i2c-gpio,delay-us = <2>; /* ~100 kHz */ - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c_gpio2>; - status = "disabled"; - }; -}; diff --git a/sys/gnu/dts/arm/at91sam9x5_can.dtsi b/sys/gnu/dts/arm/at91sam9x5_can.dtsi deleted file mode 100644 index 04ccb25d342..00000000000 --- a/sys/gnu/dts/arm/at91sam9x5_can.dtsi +++ /dev/null @@ -1,56 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * at91sam9x5_can.dtsi - Device Tree Include file for AT91SAM9x5 SoC with 1 - * Ethernet interface. - * - * Copyright (C) 2013 Boris BREZILLON - */ - -#include -#include - -/ { - ahb { - apb { - can0: can@f8000000 { - compatible = "atmel,at91sam9x5-can"; - reg = <0xf8000000 0x300>; - interrupts = <29 IRQ_TYPE_LEVEL_HIGH 3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can0_rx_tx>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 29>; - clock-names = "can_clk"; - status = "disabled"; - }; - - can1: can@f8004000 { - compatible = "atmel,at91sam9x5-can"; - reg = <0xf8004000 0x300>; - interrupts = <30 IRQ_TYPE_LEVEL_HIGH 3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can1_rx_tx>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 30>; - clock-names = "can_clk"; - status = "disabled"; - }; - - pinctrl@fffff400 { - can0 { - pinctrl_can0_rx_tx: can0_rx_tx { - atmel,pins = - ; /* CANTX0, conflicts with DTXD */ - }; - }; - - can1 { - pinctrl_can1_rx_tx: can1_rx_tx { - atmel,pins = - ; /* CANTX1, conflicts with TXD1 */ - }; - }; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/at91sam9x5_isi.dtsi b/sys/gnu/dts/arm/at91sam9x5_isi.dtsi deleted file mode 100644 index 4ce98f05d7d..00000000000 --- a/sys/gnu/dts/arm/at91sam9x5_isi.dtsi +++ /dev/null @@ -1,62 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * at91sam9x5_isi.dtsi - Device Tree Include file for AT91SAM9x5 SoC with an - * Image Sensor Interface. - * - * Copyright (C) 2013 Boris BREZILLON - */ - -#include -#include - -/ { - ahb { - apb { - pinctrl@fffff400 { - isi { - pinctrl_isi_data_0_7: isi-0-data-0-7 { - atmel,pins = - ; /* ISI_VSYNC, conflicts with LCDDAT13 */ - }; - - pinctrl_isi_data_8_9: isi-0-data-8-9 { - atmel,pins = - ; /* ISI_D9, conflicts with LCDDAT9 */ - }; - - pinctrl_isi_data_10_11: isi-0-data-10-11 { - atmel,pins = - ; /* ISI_D11, conflicts with LCDDAT11 */ - }; - }; - }; - - isi: isi@f8048000 { - compatible = "atmel,at91sam9g45-isi"; - reg = <0xf8048000 0x4000>; - interrupts = <25 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_isi_data_0_7>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 25>; - clock-names = "isi_clk"; - status = "disabled"; - port { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/at91sam9x5_lcd.dtsi b/sys/gnu/dts/arm/at91sam9x5_lcd.dtsi deleted file mode 100644 index f81c9d1691e..00000000000 --- a/sys/gnu/dts/arm/at91sam9x5_lcd.dtsi +++ /dev/null @@ -1,147 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * at91sam9x5_lcd.dtsi - Device Tree Include file for AT91SAM9x5 SoC with an - * LCD controller. - * - * Copyright (C) 2013 Boris BREZILLON - */ - -#include -#include - -/ { - ahb { - apb { - hlcdc: hlcdc@f8038000 { - compatible = "atmel,at91sam9x5-hlcdc"; - reg = <0xf8038000 0x4000>; - interrupts = <25 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 25>, <&pmc PMC_TYPE_SYSTEM 3>, <&clk32k>; - clock-names = "periph_clk","sys_clk", "slow_clk"; - status = "disabled"; - - hlcdc-display-controller { - compatible = "atmel,hlcdc-display-controller"; - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - }; - - hlcdc_pwm: hlcdc-pwm { - compatible = "atmel,hlcdc-pwm"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd_pwm>; - #pwm-cells = <3>; - }; - }; - }; - }; -}; - -&pinctrl { - lcd { - pinctrl_lcd_base: lcd-base-0 { - atmel,pins = - ; /* LCDPCK */ - }; - - pinctrl_lcd_pwm: lcd-pwm-0 { - atmel,pins = ; /* LCDPWM */ - }; - - pinctrl_lcd_rgb444: lcd-rgb-0 { - atmel,pins = - ; /* LCDD11 pin */ - }; - - pinctrl_lcd_rgb565: lcd-rgb-1 { - atmel,pins = - ; /* LCDD15 pin */ - }; - - pinctrl_lcd_rgb666: lcd-rgb-2 { - atmel,pins = - ; /* LCDD17 pin */ - }; - - pinctrl_lcd_rgb888: lcd-rgb-3 { - atmel,pins = - ; /* LCDD23 pin */ - }; - }; -}; diff --git a/sys/gnu/dts/arm/at91sam9x5_macb0.dtsi b/sys/gnu/dts/arm/at91sam9x5_macb0.dtsi deleted file mode 100644 index 222aa30f686..00000000000 --- a/sys/gnu/dts/arm/at91sam9x5_macb0.dtsi +++ /dev/null @@ -1,57 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * at91sam9x5_macb0.dtsi - Device Tree Include file for AT91SAM9x5 SoC with 1 - * Ethernet interface. - * - * Copyright (C) 2013 Boris BREZILLON - */ - -#include -#include - -/ { - ahb { - apb { - pinctrl@fffff400 { - macb0 { - pinctrl_macb0_rmii: macb0_rmii-0 { - atmel,pins = - ; /* PB10 periph A */ - }; - - pinctrl_macb0_rmii_mii: macb0_rmii_mii-0 { - atmel,pins = - ; /* PB17 periph A */ - }; - }; - }; - - macb0: ethernet@f802c000 { - compatible = "cdns,at91sam9260-macb", "cdns,macb"; - reg = <0xf802c000 0x100>; - interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_macb0_rmii>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 24>, <&pmc PMC_TYPE_PERIPHERAL 24>; - clock-names = "hclk", "pclk"; - status = "disabled"; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/at91sam9x5_macb1.dtsi b/sys/gnu/dts/arm/at91sam9x5_macb1.dtsi deleted file mode 100644 index 26bf9b5de9e..00000000000 --- a/sys/gnu/dts/arm/at91sam9x5_macb1.dtsi +++ /dev/null @@ -1,45 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * at91sam9x5_macb1.dtsi - Device Tree Include file for AT91SAM9x5 SoC with 2 - * Ethernet interfaces. - * - * Copyright (C) 2013 Boris BREZILLON - */ - -#include -#include - -/ { - ahb { - apb { - pinctrl@fffff400 { - macb1 { - pinctrl_macb1_rmii: macb1_rmii-0 { - atmel,pins = - ; /* PC31 periph B */ - }; - }; - }; - - macb1: ethernet@f8030000 { - compatible = "cdns,at91sam9260-macb", "cdns,macb"; - reg = <0xf8030000 0x100>; - interrupts = <27 IRQ_TYPE_LEVEL_HIGH 3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_macb1_rmii>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 27>, <&pmc PMC_TYPE_PERIPHERAL 27>; - clock-names = "hclk", "pclk"; - status = "disabled"; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/at91sam9x5_usart3.dtsi b/sys/gnu/dts/arm/at91sam9x5_usart3.dtsi deleted file mode 100644 index 098d3fef5c3..00000000000 --- a/sys/gnu/dts/arm/at91sam9x5_usart3.dtsi +++ /dev/null @@ -1,59 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * at91sam9x5_usart3.dtsi - Device Tree Include file for AT91SAM9x5 SoC with - * 4 USART. - * - * Copyright (C) 2013 Boris BREZILLON - */ - -#include -#include - -/ { - aliases { - serial4 = &usart3; - }; - - ahb { - apb { - pinctrl@fffff400 { - usart3 { - pinctrl_usart3: usart3-0 { - atmel,pins = - ; - }; - - pinctrl_usart3_rts: usart3_rts-0 { - atmel,pins = - ; /* PC24 periph B */ - }; - - pinctrl_usart3_cts: usart3_cts-0 { - atmel,pins = - ; /* PC25 periph B */ - }; - - pinctrl_usart3_sck: usart3_sck-0 { - atmel,pins = - ; /* PC26 periph B */ - }; - }; - }; - - usart3: serial@f8028000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xf8028000 0x200>; - interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart3>; - dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(14)>, - <&dma1 1 (AT91_DMA_CFG_PER_ID(15) | AT91_DMA_CFG_FIFOCFG_ASAP)>; - dma-names = "tx", "rx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; - clock-names = "usart"; - status = "disabled"; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/at91sam9x5cm.dtsi b/sys/gnu/dts/arm/at91sam9x5cm.dtsi deleted file mode 100644 index 75d2f7fd314..00000000000 --- a/sys/gnu/dts/arm/at91sam9x5cm.dtsi +++ /dev/null @@ -1,144 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * at91sam9x5cm.dtsi - Device Tree Include file for AT91SAM9x5 CPU Module - * - * Copyright (C) 2012 Atmel, - * 2012 Nicolas Ferre - */ - -/ { - memory { - reg = <0x20000000 0x8000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <12000000>; - }; - }; - - ahb { - apb { - tcb0: timer@f8008000 { - timer@0 { - compatible = "atmel,tcb-timer"; - reg = <0>; - }; - - timer@1 { - compatible = "atmel,tcb-timer"; - reg = <1>; - }; - }; - - pinctrl@fffff400 { - 1wire_cm { - pinctrl_1wire_cm: 1wire_cm-0 { - atmel,pins = ; /* PB18 multidrive, conflicts with led */ - }; - }; - }; - - rtc@fffffeb0 { - status = "okay"; - }; - }; - - ebi: ebi@10000000 { - pinctrl-0 = <&pinctrl_ebi_addr_nand - &pinctrl_ebi_data_0_7>; - pinctrl-names = "default"; - status = "okay"; - - nand_controller: nand-controller { - status = "okay"; - pinctrl-0 = <&pinctrl_nand_oe_we - &pinctrl_nand_cs - &pinctrl_nand_rb>; - pinctrl-names = "default"; - - nand@3 { - reg = <0x3 0x0 0x800000>; - rb-gpios = <&pioD 5 GPIO_ACTIVE_HIGH>; - cs-gpios = <&pioD 4 GPIO_ACTIVE_HIGH>; - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - nand-ecc-strength = <2>; - nand-ecc-step-size = <512>; - nand-on-flash-bbt; - label = "atmel_nand"; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - at91bootstrap@0 { - label = "at91bootstrap"; - reg = <0x0 0x40000>; - }; - - uboot@40000 { - label = "u-boot"; - reg = <0x40000 0xc0000>; - }; - - ubootenvred@100000 { - label = "U-Boot Env Redundant"; - reg = <0x100000 0x40000>; - }; - - ubootenv@140000 { - label = "U-Boot Env"; - reg = <0x140000 0x40000>; - }; - - dtb@180000 { - label = "device tree"; - reg = <0x180000 0x80000>; - }; - - kernel@200000 { - label = "kernel"; - reg = <0x200000 0x600000>; - }; - - rootfs@800000 { - label = "rootfs"; - reg = <0x800000 0x0f800000>; - }; - }; - }; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - pb18 { - label = "pb18"; - gpios = <&pioB 18 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - }; - - pd21 { - label = "pd21"; - gpios = <&pioD 21 GPIO_ACTIVE_HIGH>; - }; - }; - - 1wire_cm { - compatible = "w1-gpio"; - gpios = <&pioB 18 GPIO_ACTIVE_HIGH>; - linux,open-drain; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_1wire_cm>; - status = "okay"; - }; - -}; diff --git a/sys/gnu/dts/arm/at91sam9x5dm.dtsi b/sys/gnu/dts/arm/at91sam9x5dm.dtsi deleted file mode 100644 index 7f00c1f57b9..00000000000 --- a/sys/gnu/dts/arm/at91sam9x5dm.dtsi +++ /dev/null @@ -1,96 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * at91sam9x5dm.dtsi - Device Tree file for SAM9x5 display module - * - * Copyright (C) 2014 Atmel, - * 2014 Free Electrons - * - * Author: Boris Brezillon - */ - -/ { - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&hlcdc_pwm 0 50000 0>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - power-supply = <&bl_reg>; - status = "disabled"; - }; - - bl_reg: backlight_regulator { - compatible = "regulator-fixed"; - regulator-name = "backlight-power-supply"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - status = "disabled"; - }; - - panel: panel { - compatible = "foxlink,fl500wvr00-a0t", "simple-panel"; - backlight = <&backlight>; - power-supply = <&panel_reg>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - port@0 { - #address-cells = <1>; - #size-cells = <0>; - - panel_input: endpoint@0 { - reg = <0>; - remote-endpoint = <&hlcdc_panel_output>; - }; - }; - }; - - panel_reg: panel_regulator { - compatible = "regulator-fixed"; - regulator-name = "panel-power-supply"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - status = "disabled"; - }; -}; - -&adc0 { - atmel,adc-ts-wires = <4>; - atmel,adc-ts-pressure-threshold = <10000>; - status = "okay"; -}; - -&i2c0 { - keyboard@1b { - compatible = "qt1070"; - reg = <0x1b>; - interrupt-parent = <&pioA>; - interrupts = <7 0x0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_qt1070_irq>; - wakeup-source; - }; -}; - -&hlcdc { - hlcdc-display-controller { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_rgb888>; - - port@0 { - hlcdc_panel_output: endpoint@0 { - reg = <0>; - remote-endpoint = <&panel_input>; - }; - }; - }; -}; - -&pinctrl { - board { - pinctrl_qt1070_irq: qt1070_irq { - atmel,pins = - ; - }; - }; -}; diff --git a/sys/gnu/dts/arm/at91sam9x5ek.dtsi b/sys/gnu/dts/arm/at91sam9x5ek.dtsi deleted file mode 100644 index c934928742b..00000000000 --- a/sys/gnu/dts/arm/at91sam9x5ek.dtsi +++ /dev/null @@ -1,165 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * at91sam9x5ek.dtsi - Device Tree file for AT91SAM9x5CM Base board - * - * Copyright (C) 2012 Atmel, - * 2012 Nicolas Ferre - */ -#include "at91sam9x5cm.dtsi" - -/ { - model = "Atmel AT91SAM9X5-EK"; - compatible = "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9"; - - chosen { - bootargs = "root=/dev/mtdblock1 rw rootfstype=ubifs ubi.mtd=1 root=ubi0:rootfs"; - stdout-path = "serial0:115200n8"; - }; - - sound { - compatible = "atmel,sam9x5-wm8731-audio"; - - atmel,model = "wm8731 @ AT91SAM9X5EK"; - - atmel,audio-routing = - "Headphone Jack", "RHPOUT", - "Headphone Jack", "LHPOUT", - "LLINEIN", "Line In Jack", - "RLINEIN", "Line In Jack"; - - atmel,ssc-controller = <&ssc0>; - atmel,audio-codec = <&wm8731>; - }; -}; - -&adc0 { - atmel,adc-ts-wires = <4>; - atmel,adc-ts-pressure-threshold = <10000>; - status = "okay"; -}; - -&dbgu { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - wm8731: wm8731@1a { - compatible = "wm8731"; - reg = <0x1a>; - }; -}; - -&mmc0 { - pinctrl-0 = < - &pinctrl_board_mmc0 - &pinctrl_mmc0_slot0_clk_cmd_dat0 - &pinctrl_mmc0_slot0_dat1_3>; - status = "okay"; - - slot@0 { - reg = <0>; - bus-width = <4>; - cd-gpios = <&pioD 15 GPIO_ACTIVE_HIGH>; - }; -}; - -&mmc1 { - pinctrl-0 = < - &pinctrl_board_mmc1 - &pinctrl_mmc1_slot0_clk_cmd_dat0 - &pinctrl_mmc1_slot0_dat1_3>; - status = "okay"; - - slot@0 { - reg = <0>; - bus-width = <4>; - cd-gpios = <&pioD 14 GPIO_ACTIVE_HIGH>; - }; -}; - -&pinctrl { - camera_sensor { - pinctrl_pck0_as_isi_mck: pck0_as_isi_mck-0 { - atmel,pins = - ; /* ISI_MCK */ - }; - - pinctrl_sensor_power: sensor_power-0 { - atmel,pins = - ; - }; - - pinctrl_sensor_reset: sensor_reset-0 { - atmel,pins = - ; - }; - }; - - mmc0 { - pinctrl_board_mmc0: mmc0-board { - atmel,pins = - ; /* PD15 gpio CD pin pull up and deglitch */ - }; - }; - - mmc1 { - pinctrl_board_mmc1: mmc1-board { - atmel,pins = - ; /* PD14 gpio CD pin pull up and deglitch */ - }; - }; - - usb2 { - pinctrl_board_usb2: usb2-board { - atmel,pins = - ; /* PB16 gpio vbus sense, deglitch */ - }; - }; -}; - -&spi0 { - cs-gpios = <&pioA 14 0>, <0>, <0>, <0>; - status = "disabled"; /* conflicts with mmc1 */ - - m25p80@0 { - compatible = "atmel,at25df321a"; - spi-max-frequency = <50000000>; - reg = <0>; - }; -}; - -&ssc0 { - status = "okay"; -}; - -&usart0 { - atmel,use-dma-rx; - atmel,use-dma-tx; - status = "okay"; -}; - -&usb0 { - num-ports = <3>; - atmel,vbus-gpio = <0 /* &pioD 18 GPIO_ACTIVE_LOW *//* Activate to have access to port A */ - &pioD 19 GPIO_ACTIVE_LOW - &pioD 20 GPIO_ACTIVE_LOW - >; - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; - -&usb2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_board_usb2>; - atmel,vbus-gpio = <&pioB 16 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&watchdog { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/at91sam9xe.dtsi b/sys/gnu/dts/arm/at91sam9xe.dtsi deleted file mode 100644 index 3f9d8caf8b0..00000000000 --- a/sys/gnu/dts/arm/at91sam9xe.dtsi +++ /dev/null @@ -1,23 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * at91sam9xe.dtsi - Device Tree Include file for AT91SAM9XE family SoC - * - * Copyright (C) 2015 Atmel, - * 2015 Alexandre Belloni - */ - -#include "at91sam9260.dtsi" - -/ { - model = "Atmel AT91SAM9XE family SoC"; - compatible = "atmel,at91sam9xe", "atmel,at91sam9260"; - - sram0: sram@2ff000 { - status = "disabled"; - }; - - sram1: sram@300000 { - compatible = "mmio-sram"; - reg = <0x00300000 0x4000>; - }; -}; diff --git a/sys/gnu/dts/arm/atlas6-evb.dts b/sys/gnu/dts/arm/atlas6-evb.dts deleted file mode 100644 index 89e430392f2..00000000000 --- a/sys/gnu/dts/arm/atlas6-evb.dts +++ /dev/null @@ -1,78 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * DTS file for CSR SiRFatlas6 Evaluation Board - * - * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company. - */ - -/dts-v1/; - -/include/ "atlas6.dtsi" - -/ { - model = "CSR SiRFatlas6 Evaluation Board"; - compatible = "sirf,atlas6-cb", "sirf,atlas6"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x20000000>; - }; - - axi { - peri-iobg { - uart@b0060000 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins_a>; - }; - spi@b00d0000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins_a>; - spi@0 { - compatible = "spidev"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - }; - spi@b0170000 { - pinctrl-names = "default"; - pinctrl-0 = <&spi1_pins_a>; - }; - i2c0: i2c@b00e0000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - lcd@40 { - compatible = "sirf,lcd"; - reg = <0x40>; - }; - }; - - }; - disp-iobg { - lcd@90010000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&lcd_24pins_a>; - }; - }; - }; - display: display@0 { - panels { - panel0: panel@0 { - panel-name = "Innolux TFT"; - hactive = <800>; - vactive = <480>; - left_margin = <20>; - right_margin = <234>; - upper_margin = <3>; - lower_margin = <41>; - hsync_len = <3>; - vsync_len = <2>; - pixclock = <33264000>; - sync = <3>; - timing = <0x88>; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/atlas6.dtsi b/sys/gnu/dts/arm/atlas6.dtsi deleted file mode 100644 index 8ac5d1524a4..00000000000 --- a/sys/gnu/dts/arm/atlas6.dtsi +++ /dev/null @@ -1,800 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * DTS file for CSR SiRFatlas6 SoC - * - * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company. - */ - -/ { - compatible = "sirf,atlas6"; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&intc>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - reg = <0x0>; - d-cache-line-size = <32>; - i-cache-line-size = <32>; - d-cache-size = <32768>; - i-cache-size = <32768>; - /* from bootloader */ - timebase-frequency = <0>; - bus-frequency = <0>; - clock-frequency = <0>; - clocks = <&clks 12>; - operating-points = < - /* kHz uV */ - 200000 1025000 - 400000 1025000 - 600000 1050000 - 800000 1100000 - >; - clock-latency = <150000>; - }; - }; - - arm-pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts = <29>; - }; - - axi { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x40000000 0x40000000 0x80000000>; - - intc: interrupt-controller@80020000 { - #interrupt-cells = <1>; - interrupt-controller; - compatible = "sirf,prima2-intc"; - reg = <0x80020000 0x1000>; - }; - - sys-iobg { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x88000000 0x88000000 0x40000>; - - clks: clock-controller@88000000 { - compatible = "sirf,atlas6-clkc"; - reg = <0x88000000 0x1000>; - interrupts = <3>; - #clock-cells = <1>; - }; - - rstc: reset-controller@88010000 { - compatible = "sirf,prima2-rstc"; - reg = <0x88010000 0x1000>; - #reset-cells = <1>; - }; - - rsc-controller@88020000 { - compatible = "sirf,prima2-rsc"; - reg = <0x88020000 0x1000>; - }; - - cphifbg@88030000 { - compatible = "sirf,prima2-cphifbg"; - reg = <0x88030000 0x1000>; - clocks = <&clks 42>; - }; - }; - - mem-iobg { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x90000000 0x90000000 0x10000>; - - memory-controller@90000000 { - compatible = "sirf,prima2-memc"; - reg = <0x90000000 0x2000>; - interrupts = <27>; - clocks = <&clks 5>; - }; - - memc-monitor { - compatible = "sirf,prima2-memcmon"; - reg = <0x90002000 0x200>; - interrupts = <4>; - clocks = <&clks 32>; - }; - }; - - disp-iobg { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x90010000 0x90010000 0x30000>; - - lcd@90010000 { - compatible = "sirf,prima2-lcd"; - reg = <0x90010000 0x20000>; - interrupts = <30>; - clocks = <&clks 34>; - display=<&display>; - /* later transfer to pwm */ - bl-gpio = <&gpio 7 0>; - default-panel = <&panel0>; - }; - - vpp@90020000 { - compatible = "sirf,prima2-vpp"; - reg = <0x90020000 0x10000>; - interrupts = <31>; - clocks = <&clks 35>; - resets = <&rstc 6>; - }; - }; - - graphics-iobg { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x98000000 0x98000000 0x8000000>; - - graphics@98000000 { - compatible = "powervr,sgx510"; - reg = <0x98000000 0x8000000>; - interrupts = <6>; - clocks = <&clks 32>; - }; - }; - - graphics2d-iobg { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0xa0000000 0xa0000000 0x8000000>; - - ble@a0000000 { - compatible = "sirf,atlas6-ble"; - reg = <0xa0000000 0x2000>; - interrupts = <5>; - clocks = <&clks 33>; - }; - }; - - dsp-iobg { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0xa8000000 0xa8000000 0x2000000>; - - dspif@a8000000 { - compatible = "sirf,prima2-dspif"; - reg = <0xa8000000 0x10000>; - interrupts = <9>; - resets = <&rstc 1>; - }; - - gps@a8010000 { - compatible = "sirf,prima2-gps"; - reg = <0xa8010000 0x10000>; - interrupts = <7>; - clocks = <&clks 9>; - resets = <&rstc 2>; - }; - - dsp@a9000000 { - compatible = "sirf,prima2-dsp"; - reg = <0xa9000000 0x1000000>; - interrupts = <8>; - clocks = <&clks 8>; - resets = <&rstc 0>; - }; - }; - - peri-iobg { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0xb0000000 0xb0000000 0x180000>, - <0x56000000 0x56000000 0x1b00000>; - - timer@b0020000 { - compatible = "sirf,prima2-tick"; - reg = <0xb0020000 0x1000>; - interrupts = <0>; - clocks = <&clks 11>; - }; - - nand@b0030000 { - compatible = "sirf,prima2-nand"; - reg = <0xb0030000 0x10000>; - interrupts = <41>; - clocks = <&clks 26>; - }; - - audio@b0040000 { - compatible = "sirf,prima2-audio"; - reg = <0xb0040000 0x10000>; - interrupts = <35>; - clocks = <&clks 27>; - }; - - uart0: uart@b0050000 { - cell-index = <0>; - compatible = "sirf,prima2-uart"; - reg = <0xb0050000 0x1000>; - interrupts = <17>; - fifosize = <128>; - clocks = <&clks 13>; - dmas = <&dmac1 5>, <&dmac0 2>; - dma-names = "rx", "tx"; - }; - - uart1: uart@b0060000 { - cell-index = <1>; - compatible = "sirf,prima2-uart"; - reg = <0xb0060000 0x1000>; - interrupts = <18>; - fifosize = <32>; - clocks = <&clks 14>; - dma-names = "no-rx", "no-tx"; - }; - - uart2: uart@b0070000 { - cell-index = <2>; - compatible = "sirf,prima2-uart"; - reg = <0xb0070000 0x1000>; - interrupts = <19>; - fifosize = <128>; - clocks = <&clks 15>; - dmas = <&dmac0 6>, <&dmac0 7>; - dma-names = "rx", "tx"; - }; - - usp0: usp@b0080000 { - cell-index = <0>; - compatible = "sirf,prima2-usp"; - reg = <0xb0080000 0x10000>; - interrupts = <20>; - fifosize = <128>; - clocks = <&clks 28>; - dmas = <&dmac1 1>, <&dmac1 2>; - dma-names = "rx", "tx"; - }; - - usp1: usp@b0090000 { - cell-index = <1>; - compatible = "sirf,prima2-usp"; - reg = <0xb0090000 0x10000>; - interrupts = <21>; - fifosize = <128>; - clocks = <&clks 29>; - dmas = <&dmac0 14>, <&dmac0 15>; - dma-names = "rx", "tx"; - }; - - dmac0: dma-controller@b00b0000 { - cell-index = <0>; - compatible = "sirf,prima2-dmac"; - reg = <0xb00b0000 0x10000>; - interrupts = <12>; - clocks = <&clks 24>; - #dma-cells = <1>; - }; - - dmac1: dma-controller@b0160000 { - cell-index = <1>; - compatible = "sirf,prima2-dmac"; - reg = <0xb0160000 0x10000>; - interrupts = <13>; - clocks = <&clks 25>; - #dma-cells = <1>; - }; - - vip@b00C0000 { - compatible = "sirf,prima2-vip"; - reg = <0xb00C0000 0x10000>; - clocks = <&clks 31>; - interrupts = <14>; - sirf,vip-dma-rx-channel = <16>; - }; - - spi0: spi@b00d0000 { - cell-index = <0>; - compatible = "sirf,prima2-spi"; - reg = <0xb00d0000 0x10000>; - interrupts = <15>; - sirf,spi-num-chipselects = <1>; - dmas = <&dmac1 9>, - <&dmac1 4>; - dma-names = "rx", "tx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clks 19>; - resets = <&rstc 26>; - status = "disabled"; - }; - - spi1: spi@b0170000 { - cell-index = <1>; - compatible = "sirf,prima2-spi"; - reg = <0xb0170000 0x10000>; - interrupts = <16>; - sirf,spi-num-chipselects = <1>; - dmas = <&dmac0 12>, - <&dmac0 13>; - dma-names = "rx", "tx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clks 20>; - resets = <&rstc 27>; - status = "disabled"; - }; - - i2c0: i2c@b00e0000 { - cell-index = <0>; - compatible = "sirf,prima2-i2c"; - reg = <0xb00e0000 0x10000>; - interrupts = <24>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clks 17>; - }; - - i2c1: i2c@b00f0000 { - cell-index = <1>; - compatible = "sirf,prima2-i2c"; - reg = <0xb00f0000 0x10000>; - interrupts = <25>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clks 18>; - }; - - tsc@b0110000 { - compatible = "sirf,prima2-tsc"; - reg = <0xb0110000 0x10000>; - interrupts = <33>; - clocks = <&clks 16>; - }; - - gpio: pinctrl@b0120000 { - #gpio-cells = <2>; - #interrupt-cells = <2>; - compatible = "sirf,atlas6-pinctrl"; - reg = <0xb0120000 0x10000>; - interrupts = <43 44 45 46 47>; - gpio-controller; - interrupt-controller; - - lcd_16pins_a: lcd0@0 { - lcd { - sirf,pins = "lcd_16bitsgrp"; - sirf,function = "lcd_16bits"; - }; - }; - lcd_18pins_a: lcd0@1 { - lcd { - sirf,pins = "lcd_18bitsgrp"; - sirf,function = "lcd_18bits"; - }; - }; - lcd_24pins_a: lcd0@2 { - lcd { - sirf,pins = "lcd_24bitsgrp"; - sirf,function = "lcd_24bits"; - }; - }; - lcdrom_pins_a: lcdrom0@0 { - lcd { - sirf,pins = "lcdromgrp"; - sirf,function = "lcdrom"; - }; - }; - uart0_pins_a: uart0@0 { - uart { - sirf,pins = "uart0grp"; - sirf,function = "uart0"; - }; - }; - uart0_noflow_pins_a: uart0@1 { - uart { - sirf,pins = "uart0_nostreamctrlgrp"; - sirf,function = "uart0_nostreamctrl"; - }; - }; - uart1_pins_a: uart1@0 { - uart { - sirf,pins = "uart1grp"; - sirf,function = "uart1"; - }; - }; - uart2_pins_a: uart2@0 { - uart { - sirf,pins = "uart2grp"; - sirf,function = "uart2"; - }; - }; - uart2_noflow_pins_a: uart2@1 { - uart { - sirf,pins = "uart2_nostreamctrlgrp"; - sirf,function = "uart2_nostreamctrl"; - }; - }; - spi0_pins_a: spi0@0 { - spi { - sirf,pins = "spi0grp"; - sirf,function = "spi0"; - }; - }; - spi1_pins_a: spi1@0 { - spi { - sirf,pins = "spi1grp"; - sirf,function = "spi1"; - }; - }; - i2c0_pins_a: i2c0@0 { - i2c { - sirf,pins = "i2c0grp"; - sirf,function = "i2c0"; - }; - }; - i2c1_pins_a: i2c1@0 { - i2c { - sirf,pins = "i2c1grp"; - sirf,function = "i2c1"; - }; - }; - pwm0_pins_a: pwm0@0 { - pwm { - sirf,pins = "pwm0grp"; - sirf,function = "pwm0"; - }; - }; - pwm1_pins_a: pwm1@0 { - pwm { - sirf,pins = "pwm1grp"; - sirf,function = "pwm1"; - }; - }; - pwm2_pins_a: pwm2@0 { - pwm { - sirf,pins = "pwm2grp"; - sirf,function = "pwm2"; - }; - }; - pwm3_pins_a: pwm3@0 { - pwm { - sirf,pins = "pwm3grp"; - sirf,function = "pwm3"; - }; - }; - pwm4_pins_a: pwm4@0 { - pwm { - sirf,pins = "pwm4grp"; - sirf,function = "pwm4"; - }; - }; - gps_pins_a: gps@0 { - gps { - sirf,pins = "gpsgrp"; - sirf,function = "gps"; - }; - }; - vip_pins_a: vip@0 { - vip { - sirf,pins = "vipgrp"; - sirf,function = "vip"; - }; - }; - sdmmc0_pins_a: sdmmc0@0 { - sdmmc0 { - sirf,pins = "sdmmc0grp"; - sirf,function = "sdmmc0"; - }; - }; - sdmmc1_pins_a: sdmmc1@0 { - sdmmc1 { - sirf,pins = "sdmmc1grp"; - sirf,function = "sdmmc1"; - }; - }; - sdmmc2_pins_a: sdmmc2@0 { - sdmmc2 { - sirf,pins = "sdmmc2grp"; - sirf,function = "sdmmc2"; - }; - }; - sdmmc2_nowp_pins_a: sdmmc2_nowp@0 { - sdmmc2_nowp { - sirf,pins = "sdmmc2_nowpgrp"; - sirf,function = "sdmmc2_nowp"; - }; - }; - sdmmc3_pins_a: sdmmc3@0 { - sdmmc3 { - sirf,pins = "sdmmc3grp"; - sirf,function = "sdmmc3"; - }; - }; - sdmmc5_pins_a: sdmmc5@0 { - sdmmc5 { - sirf,pins = "sdmmc5grp"; - sirf,function = "sdmmc5"; - }; - }; - i2s_mclk_pins_a: i2s_mclk@0 { - i2s_mclk { - sirf,pins = "i2smclkgrp"; - sirf,function = "i2s_mclk"; - }; - }; - i2s_ext_clk_input_pins_a: i2s_ext_clk_input@0 { - i2s_ext_clk_input { - sirf,pins = "i2s_ext_clk_inputgrp"; - sirf,function = "i2s_ext_clk_input"; - }; - }; - i2s_pins_a: i2s@0 { - i2s { - sirf,pins = "i2sgrp"; - sirf,function = "i2s"; - }; - }; - i2s_no_din_pins_a: i2s_no_din@0 { - i2s_no_din { - sirf,pins = "i2s_no_dingrp"; - sirf,function = "i2s_no_din"; - }; - }; - i2s_6chn_pins_a: i2s_6chn@0 { - i2s_6chn { - sirf,pins = "i2s_6chngrp"; - sirf,function = "i2s_6chn"; - }; - }; - ac97_pins_a: ac97@0 { - ac97 { - sirf,pins = "ac97grp"; - sirf,function = "ac97"; - }; - }; - nand_pins_a: nand@0 { - nand { - sirf,pins = "nandgrp"; - sirf,function = "nand"; - }; - }; - usp0_pins_a: usp0@0 { - usp0 { - sirf,pins = "usp0grp"; - sirf,function = "usp0"; - }; - }; - usp0_uart_nostreamctrl_pins_a: usp0@1 { - usp0 { - sirf,pins = "usp0_uart_nostreamctrl_grp"; - sirf,function = "usp0_uart_nostreamctrl"; - }; - }; - usp0_only_utfs_pins_a: usp0@2 { - usp0 { - sirf,pins = "usp0_only_utfs_grp"; - sirf,function = "usp0_only_utfs"; - }; - }; - usp0_only_urfs_pins_a: usp0@3 { - usp0 { - sirf,pins = "usp0_only_urfs_grp"; - sirf,function = "usp0_only_urfs"; - }; - }; - usp1_pins_a: usp1@0 { - usp1 { - sirf,pins = "usp1grp"; - sirf,function = "usp1"; - }; - }; - usp1_uart_nostreamctrl_pins_a: usp1@1 { - usp1 { - sirf,pins = "usp1_uart_nostreamctrl_grp"; - sirf,function = "usp1_uart_nostreamctrl"; - }; - }; - usb0_upli_drvbus_pins_a: usb0_upli_drvbus@0 { - usb0_upli_drvbus { - sirf,pins = "usb0_upli_drvbusgrp"; - sirf,function = "usb0_upli_drvbus"; - }; - }; - usb1_utmi_drvbus_pins_a: usb1_utmi_drvbus@0 { - usb1_utmi_drvbus { - sirf,pins = "usb1_utmi_drvbusgrp"; - sirf,function = "usb1_utmi_drvbus"; - }; - }; - usb1_dp_dn_pins_a: usb1_dp_dn@0 { - usb1_dp_dn { - sirf,pins = "usb1_dp_dngrp"; - sirf,function = "usb1_dp_dn"; - }; - }; - uart1_route_io_usb1_pins_a: uart1_route_io_usb1@0 { - uart1_route_io_usb1 { - sirf,pins = "uart1_route_io_usb1grp"; - sirf,function = "uart1_route_io_usb1"; - }; - }; - warm_rst_pins_a: warm_rst@0 { - warm_rst { - sirf,pins = "warm_rstgrp"; - sirf,function = "warm_rst"; - }; - }; - pulse_count_pins_a: pulse_count@0 { - pulse_count { - sirf,pins = "pulse_countgrp"; - sirf,function = "pulse_count"; - }; - }; - cko0_pins_a: cko0@0 { - cko0 { - sirf,pins = "cko0grp"; - sirf,function = "cko0"; - }; - }; - cko1_pins_a: cko1@0 { - cko1 { - sirf,pins = "cko1grp"; - sirf,function = "cko1"; - }; - }; - }; - - pwm@b0130000 { - compatible = "sirf,prima2-pwm"; - reg = <0xb0130000 0x10000>; - clocks = <&clks 21>; - }; - - efusesys@b0140000 { - compatible = "sirf,prima2-efuse"; - reg = <0xb0140000 0x10000>; - clocks = <&clks 22>; - }; - - pulsec@b0150000 { - compatible = "sirf,prima2-pulsec"; - reg = <0xb0150000 0x10000>; - interrupts = <48>; - clocks = <&clks 23>; - }; - - pci-iobg { - compatible = "sirf,prima2-pciiobg", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x56000000 0x56000000 0x1b00000>; - - sd0: sdhci@56000000 { - cell-index = <0>; - compatible = "sirf,prima2-sdhc"; - reg = <0x56000000 0x100000>; - interrupts = <38>; - bus-width = <8>; - clocks = <&clks 36>; - }; - - sd1: sdhci@56100000 { - cell-index = <1>; - compatible = "sirf,prima2-sdhc"; - reg = <0x56100000 0x100000>; - interrupts = <38>; - status = "disabled"; - bus-width = <4>; - clocks = <&clks 36>; - }; - - sd2: sdhci@56200000 { - cell-index = <2>; - compatible = "sirf,prima2-sdhc"; - reg = <0x56200000 0x100000>; - interrupts = <23>; - status = "disabled"; - bus-width = <4>; - clocks = <&clks 37>; - }; - - sd3: sdhci@56300000 { - cell-index = <3>; - compatible = "sirf,prima2-sdhc"; - reg = <0x56300000 0x100000>; - interrupts = <23>; - status = "disabled"; - bus-width = <4>; - clocks = <&clks 37>; - }; - - sd5: sdhci@56500000 { - cell-index = <5>; - compatible = "sirf,prima2-sdhc"; - reg = <0x56500000 0x100000>; - interrupts = <39>; - status = "disabled"; - bus-width = <4>; - clocks = <&clks 38>; - }; - - pci-copy@57900000 { - compatible = "sirf,prima2-pcicp"; - reg = <0x57900000 0x100000>; - interrupts = <40>; - }; - - rom-interface@57a00000 { - compatible = "sirf,prima2-romif"; - reg = <0x57a00000 0x100000>; - }; - }; - }; - - rtc-iobg { - compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x80030000 0x10000>; - - gpsrtc@1000 { - compatible = "sirf,prima2-gpsrtc"; - reg = <0x1000 0x1000>; - interrupts = <55 56 57>; - }; - - sysrtc@2000 { - compatible = "sirf,prima2-sysrtc"; - reg = <0x2000 0x1000>; - interrupts = <52 53 54>; - }; - - minigpsrtc@2000 { - compatible = "sirf,prima2-minigpsrtc"; - reg = <0x2000 0x1000>; - interrupts = <54>; - }; - - pwrc@3000 { - compatible = "sirf,prima2-pwrc"; - reg = <0x3000 0x1000>; - interrupts = <32>; - }; - }; - - uus-iobg { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0xb8000000 0xb8000000 0x40000>; - - usb0: usb@b00e0000 { - compatible = "chipidea,ci13611a-prima2"; - reg = <0xb8000000 0x10000>; - interrupts = <10>; - clocks = <&clks 40>; - }; - - usb1: usb@b00f0000 { - compatible = "chipidea,ci13611a-prima2"; - reg = <0xb8010000 0x10000>; - interrupts = <11>; - clocks = <&clks 41>; - }; - - security@b00f0000 { - compatible = "sirf,prima2-security"; - reg = <0xb8030000 0x10000>; - interrupts = <42>; - clocks = <&clks 7>; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/atlas7-evb.dts b/sys/gnu/dts/arm/atlas7-evb.dts deleted file mode 100644 index e0515043d14..00000000000 --- a/sys/gnu/dts/arm/atlas7-evb.dts +++ /dev/null @@ -1,127 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * DTS file for CSR SiRFatlas7 Evaluation Board - * - * Copyright (c) 2014 Cambridge Silicon Radio Limited, a CSR plc group company. - */ - -/dts-v1/; - -/include/ "atlas7.dtsi" - -#include -#include - -/ { - model = "CSR SiRFatlas7 Evaluation Board"; - compatible = "sirf,atlas7-cb", "sirf,atlas7"; - - chosen { - bootargs = "console=ttySiRF1,115200 earlyprintk"; - }; - - memory { - device_type = "memory"; - reg = <0x40000000 0x20000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - vpp_reserved: vpp_mem@5e800000 { - compatible = "sirf,reserved-memory"; - reg = <0x5e800000 0x800000>; - }; - - nanddisk_reserved: nanddisk@46000000 { - reg = <0x46000000 0x200000>; - no-map; - }; - }; - - - noc { - mediam { - nand@17050000 { - memory-region = <&nanddisk_reserved>; - }; - }; - - gnssm { - spi1: spi@18200000 { - status = "okay"; - spiflash: macronix@0{ - status = "okay"; - compatible = "macronix,mx25l6405d"; - reg = <0>; - spi-max-frequency = <37500000>; - spi-cpha; - spi-cpol; - #address-cells = <1>; - #size-cells = <1>; - partitions@0 { - label = "myspiboot"; - reg = <0x0 0x800000>; - }; - }; - }; - }; - - btm { - uart6: uart@11000000 { - status = "okay"; - uart-has-rtscts; - }; - }; - - disp-iobg { - vpp@13110000 { - memory-region = <&vpp_reserved>; - }; - }; - - display0: display@0 { - compatible = "lvds-panel"; - source = "lvds.0"; - - bl-gpios = <&gpio_1 63 0>; - data-lines = <24>; - - display-timings { - native-mode = <&timing0>; - timing0: timing0 { - clock-frequency = <60000000>; - hactive = <1024>; - vactive = <600>; - hfront-porch = <220>; - hback-porch = <100>; - hsync-len = <1>; - vback-porch = <10>; - vfront-porch = <25>; - vsync-len = <1>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - - rearview_key { - label = "rearview key"; - linux,code = ; - gpios = <&gpio_1 3 GPIO_ACTIVE_LOW>; - debounce-interval = <100>; - }; - }; - - }; -}; diff --git a/sys/gnu/dts/arm/atlas7.dtsi b/sys/gnu/dts/arm/atlas7.dtsi deleted file mode 100644 index 99c9d9d9267..00000000000 --- a/sys/gnu/dts/arm/atlas7.dtsi +++ /dev/null @@ -1,1955 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * DTS file for CSR SiRFatlas7 SoC - * - * Copyright (c) 2014 Cambridge Silicon Radio Limited, a CSR plc group company. - */ - -/ { - compatible = "sirf,atlas7"; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&gic>; - aliases { - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - serial4 = &uart4; - serial5 = &uart5; - serial6 = &uart6; - serial9 = &usp2; - spi1 = &spi1; - spi2 = &usp1; - spi3 = &usp2; - spi4 = &usp3; - }; - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0>; - }; - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <1>; - }; - }; - - clocks { - xinw { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "xinw"; - }; - xin { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <26000000>; - clock-output-names = "xin"; - }; - }; - - arm-pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts = <0 29 4>, <0 82 4>; - }; - - noc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x10000000 0x10000000 0xc0000000>; - - gic: interrupt-controller@10301000 { - compatible = "arm,cortex-a9-gic"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0x10301000 0x1000>, - <0x10302000 0x0100>; - }; - - pmu_regulator: pmu_regulator@10E30020 { - compatible = "sirf,atlas7-pmu-ldo"; - reg = <0x10E30020 0x4>; - ldo: ldo { - regulator-name = "ldo"; - }; - }; - - atlas7_codec: atlas7_codec@10E30000 { - #sound-dai-cells = <0>; - compatible = "sirf,atlas7-codec"; - reg = <0x10E30000 0x400>; - clocks = <&car 62>; - ldo-supply = <&ldo>; - }; - - atlas7_iacc: atlas7_iacc@10D01000 { - #sound-dai-cells = <0>; - compatible = "sirf,atlas7-iacc"; - reg = <0x10D01000 0x100>; - dmas = <&dmac3 0>, <&dmac3 7>, <&dmac3 8>, - <&dmac3 3>, <&dmac3 9>; - dma-names = "rx", "tx0", "tx1", "tx2", "tx3"; - clocks = <&car 62>; - }; - - ipc@13240000 { - compatible = "sirf,atlas7-ipc"; - ranges = <0x13240000 0x13240000 0x00010000>; - #address-cells = <1>; - #size-cells = <1>; - - hwspinlock { - compatible = "sirf,hwspinlock"; - reg = <0x13240000 0x00010000>; - - num-spinlocks = <30>; - }; - - ns_m3_rproc@0 { - compatible = "sirf,ns2m30-rproc"; - reg = <0x13240000 0x00010000>; - interrupts = <0 123 0>; - }; - - ns_m3_rproc@1 { - compatible = "sirf,ns2m31-rproc"; - reg = <0x13240000 0x00010000>; - interrupts = <0 126 0>; - }; - - ns_kal_rproc@0 { - compatible = "sirf,ns2kal0-rproc"; - reg = <0x13240000 0x00010000>; - interrupts = <0 124 0>; - }; - - ns_kal_rproc@1 { - compatible = "sirf,ns2kal1-rproc"; - reg = <0x13240000 0x00010000>; - interrupts = <0 127 0>; - }; - }; - - pinctrl: ioc@18880000 { - compatible = "sirf,atlas7-ioc"; - reg = <0x18880000 0x1000>, - <0x10E40000 0x1000>; - - audio_ac97_pmx: audio_ac97@0 { - audio_ac97 { - groups = "audio_ac97_grp"; - function = "audio_ac97"; - }; - }; - - audio_func_dbg_pmx: audio_func_dbg@0 { - audio_func_dbg { - groups = "audio_func_dbg_grp"; - function = "audio_func_dbg"; - }; - }; - - audio_i2s_pmx: audio_i2s@0 { - audio_i2s { - groups = "audio_i2s_grp"; - function = "audio_i2s"; - }; - }; - - audio_i2s_2ch_pmx: audio_i2s_2ch@0 { - audio_i2s_2ch { - groups = "audio_i2s_2ch_grp"; - function = "audio_i2s_2ch"; - }; - }; - - audio_i2s_extclk_pmx: audio_i2s_extclk@0 { - audio_i2s_extclk { - groups = "audio_i2s_extclk_grp"; - function = "audio_i2s_extclk"; - }; - }; - - audio_uart0_pmx: audio_uart0@0 { - audio_uart0 { - groups = "audio_uart0_grp"; - function = "audio_uart0"; - }; - }; - - audio_uart1_pmx: audio_uart1@0 { - audio_uart1 { - groups = "audio_uart1_grp"; - function = "audio_uart1"; - }; - }; - - audio_uart2_pmx0: audio_uart2@0 { - audio_uart2_0 { - groups = "audio_uart2_grp0"; - function = "audio_uart2_m0"; - }; - }; - - audio_uart2_pmx1: audio_uart2@1 { - audio_uart2_1 { - groups = "audio_uart2_grp1"; - function = "audio_uart2_m1"; - }; - }; - - c_can_trnsvr_pmx: c_can_trnsvr@0 { - c_can_trnsvr { - groups = "c_can_trnsvr_grp"; - function = "c_can_trnsvr"; - }; - }; - - c0_can_pmx0: c0_can@0 { - c0_can_0 { - groups = "c0_can_grp0"; - function = "c0_can_m0"; - }; - }; - - c0_can_pmx1: c0_can@1 { - c0_can_1 { - groups = "c0_can_grp1"; - function = "c0_can_m1"; - }; - }; - - c1_can_pmx0: c1_can@0 { - c1_can_0 { - groups = "c1_can_grp0"; - function = "c1_can_m0"; - }; - }; - - c1_can_pmx1: c1_can@1 { - c1_can_1 { - groups = "c1_can_grp1"; - function = "c1_can_m1"; - }; - }; - - c1_can_pmx2: c1_can@2 { - c1_can_2 { - groups = "c1_can_grp2"; - function = "c1_can_m2"; - }; - }; - - ca_audio_lpc_pmx: ca_audio_lpc@0 { - ca_audio_lpc { - groups = "ca_audio_lpc_grp"; - function = "ca_audio_lpc"; - }; - }; - - ca_bt_lpc_pmx: ca_bt_lpc@0 { - ca_bt_lpc { - groups = "ca_bt_lpc_grp"; - function = "ca_bt_lpc"; - }; - }; - - ca_coex_pmx: ca_coex@0 { - ca_coex { - groups = "ca_coex_grp"; - function = "ca_coex"; - }; - }; - - ca_curator_lpc_pmx: ca_curator_lpc@0 { - ca_curator_lpc { - groups = "ca_curator_lpc_grp"; - function = "ca_curator_lpc"; - }; - }; - - ca_pcm_debug_pmx: ca_pcm_debug@0 { - ca_pcm_debug { - groups = "ca_pcm_debug_grp"; - function = "ca_pcm_debug"; - }; - }; - - ca_pio_pmx: ca_pio@0 { - ca_pio { - groups = "ca_pio_grp"; - function = "ca_pio"; - }; - }; - - ca_sdio_debug_pmx: ca_sdio_debug@0 { - ca_sdio_debug { - groups = "ca_sdio_debug_grp"; - function = "ca_sdio_debug"; - }; - }; - - ca_spi_pmx: ca_spi@0 { - ca_spi { - groups = "ca_spi_grp"; - function = "ca_spi"; - }; - }; - - ca_trb_pmx: ca_trb@0 { - ca_trb { - groups = "ca_trb_grp"; - function = "ca_trb"; - }; - }; - - ca_uart_debug_pmx: ca_uart_debug@0 { - ca_uart_debug { - groups = "ca_uart_debug_grp"; - function = "ca_uart_debug"; - }; - }; - - clkc_pmx0: clkc@0 { - clkc_0 { - groups = "clkc_grp0"; - function = "clkc_m0"; - }; - }; - - clkc_pmx1: clkc@1 { - clkc_1 { - groups = "clkc_grp1"; - function = "clkc_m1"; - }; - }; - - gn_gnss_i2c_pmx: gn_gnss_i2c@0 { - gn_gnss_i2c { - groups = "gn_gnss_i2c_grp"; - function = "gn_gnss_i2c"; - }; - }; - - gn_gnss_uart_nopause_pmx: gn_gnss_uart_nopause@0 { - gn_gnss_uart_nopause { - groups = "gn_gnss_uart_nopause_grp"; - function = "gn_gnss_uart_nopause"; - }; - }; - - gn_gnss_uart_pmx: gn_gnss_uart@0 { - gn_gnss_uart { - groups = "gn_gnss_uart_grp"; - function = "gn_gnss_uart"; - }; - }; - - gn_trg_spi_pmx0: gn_trg_spi@0 { - gn_trg_spi_0 { - groups = "gn_trg_spi_grp0"; - function = "gn_trg_spi_m0"; - }; - }; - - gn_trg_spi_pmx1: gn_trg_spi@1 { - gn_trg_spi_1 { - groups = "gn_trg_spi_grp1"; - function = "gn_trg_spi_m1"; - }; - }; - - cvbs_dbg_pmx: cvbs_dbg@0 { - cvbs_dbg { - groups = "cvbs_dbg_grp"; - function = "cvbs_dbg"; - }; - }; - - cvbs_dbg_test_pmx0: cvbs_dbg_test@0 { - cvbs_dbg_test_0 { - groups = "cvbs_dbg_test_grp0"; - function = "cvbs_dbg_test_m0"; - }; - }; - - cvbs_dbg_test_pmx1: cvbs_dbg_test@1 { - cvbs_dbg_test_1 { - groups = "cvbs_dbg_test_grp1"; - function = "cvbs_dbg_test_m1"; - }; - }; - - cvbs_dbg_test_pmx2: cvbs_dbg_test@2 { - cvbs_dbg_test_2 { - groups = "cvbs_dbg_test_grp2"; - function = "cvbs_dbg_test_m2"; - }; - }; - - cvbs_dbg_test_pmx3: cvbs_dbg_test@3 { - cvbs_dbg_test_3 { - groups = "cvbs_dbg_test_grp3"; - function = "cvbs_dbg_test_m3"; - }; - }; - - cvbs_dbg_test_pmx4: cvbs_dbg_test@4 { - cvbs_dbg_test_4 { - groups = "cvbs_dbg_test_grp4"; - function = "cvbs_dbg_test_m4"; - }; - }; - - cvbs_dbg_test_pmx5: cvbs_dbg_test@5 { - cvbs_dbg_test_5 { - groups = "cvbs_dbg_test_grp5"; - function = "cvbs_dbg_test_m5"; - }; - }; - - cvbs_dbg_test_pmx6: cvbs_dbg_test@6 { - cvbs_dbg_test_6 { - groups = "cvbs_dbg_test_grp6"; - function = "cvbs_dbg_test_m6"; - }; - }; - - cvbs_dbg_test_pmx7: cvbs_dbg_test@7 { - cvbs_dbg_test_7 { - groups = "cvbs_dbg_test_grp7"; - function = "cvbs_dbg_test_m7"; - }; - }; - - cvbs_dbg_test_pmx8: cvbs_dbg_test@8 { - cvbs_dbg_test_8 { - groups = "cvbs_dbg_test_grp8"; - function = "cvbs_dbg_test_m8"; - }; - }; - - cvbs_dbg_test_pmx9: cvbs_dbg_test@9 { - cvbs_dbg_test_9 { - groups = "cvbs_dbg_test_grp9"; - function = "cvbs_dbg_test_m9"; - }; - }; - - cvbs_dbg_test_pmx10: cvbs_dbg_test@10 { - cvbs_dbg_test_10 { - groups = "cvbs_dbg_test_grp10"; - function = "cvbs_dbg_test_m10"; - }; - }; - - cvbs_dbg_test_pmx11: cvbs_dbg_test@11 { - cvbs_dbg_test_11 { - groups = "cvbs_dbg_test_grp11"; - function = "cvbs_dbg_test_m11"; - }; - }; - - cvbs_dbg_test_pmx12: cvbs_dbg_test@12 { - cvbs_dbg_test_12 { - groups = "cvbs_dbg_test_grp12"; - function = "cvbs_dbg_test_m12"; - }; - }; - - cvbs_dbg_test_pmx13: cvbs_dbg_test@13 { - cvbs_dbg_test_13 { - groups = "cvbs_dbg_test_grp13"; - function = "cvbs_dbg_test_m13"; - }; - }; - - cvbs_dbg_test_pmx14: cvbs_dbg_test@14 { - cvbs_dbg_test_14 { - groups = "cvbs_dbg_test_grp14"; - function = "cvbs_dbg_test_m14"; - }; - }; - - cvbs_dbg_test_pmx15: cvbs_dbg_test@15 { - cvbs_dbg_test_15 { - groups = "cvbs_dbg_test_grp15"; - function = "cvbs_dbg_test_m15"; - }; - }; - - gn_gnss_power_pmx: gn_gnss_power@0 { - gn_gnss_power { - groups = "gn_gnss_power_grp"; - function = "gn_gnss_power"; - }; - }; - - gn_gnss_sw_status_pmx: gn_gnss_sw_status@0 { - gn_gnss_sw_status { - groups = "gn_gnss_sw_status_grp"; - function = "gn_gnss_sw_status"; - }; - }; - - gn_gnss_eclk_pmx: gn_gnss_eclk@0 { - gn_gnss_eclk { - groups = "gn_gnss_eclk_grp"; - function = "gn_gnss_eclk"; - }; - }; - - gn_gnss_irq1_pmx0: gn_gnss_irq1@0 { - gn_gnss_irq1_0 { - groups = "gn_gnss_irq1_grp0"; - function = "gn_gnss_irq1_m0"; - }; - }; - - gn_gnss_irq2_pmx0: gn_gnss_irq2@0 { - gn_gnss_irq2_0 { - groups = "gn_gnss_irq2_grp0"; - function = "gn_gnss_irq2_m0"; - }; - }; - - gn_gnss_tm_pmx: gn_gnss_tm@0 { - gn_gnss_tm { - groups = "gn_gnss_tm_grp"; - function = "gn_gnss_tm"; - }; - }; - - gn_gnss_tsync_pmx: gn_gnss_tsync@0 { - gn_gnss_tsync { - groups = "gn_gnss_tsync_grp"; - function = "gn_gnss_tsync"; - }; - }; - - gn_io_gnsssys_sw_cfg_pmx: gn_io_gnsssys_sw_cfg@0 { - gn_io_gnsssys_sw_cfg { - groups = "gn_io_gnsssys_sw_cfg_grp"; - function = "gn_io_gnsssys_sw_cfg"; - }; - }; - - gn_trg_pmx0: gn_trg@0 { - gn_trg_0 { - groups = "gn_trg_grp0"; - function = "gn_trg_m0"; - }; - }; - - gn_trg_pmx1: gn_trg@1 { - gn_trg_1 { - groups = "gn_trg_grp1"; - function = "gn_trg_m1"; - }; - }; - - gn_trg_shutdown_pmx0: gn_trg_shutdown@0 { - gn_trg_shutdown_0 { - groups = "gn_trg_shutdown_grp0"; - function = "gn_trg_shutdown_m0"; - }; - }; - - gn_trg_shutdown_pmx1: gn_trg_shutdown@1 { - gn_trg_shutdown_1 { - groups = "gn_trg_shutdown_grp1"; - function = "gn_trg_shutdown_m1"; - }; - }; - - gn_trg_shutdown_pmx2: gn_trg_shutdown@2 { - gn_trg_shutdown_2 { - groups = "gn_trg_shutdown_grp2"; - function = "gn_trg_shutdown_m2"; - }; - }; - - gn_trg_shutdown_pmx3: gn_trg_shutdown@3 { - gn_trg_shutdown_3 { - groups = "gn_trg_shutdown_grp3"; - function = "gn_trg_shutdown_m3"; - }; - }; - - i2c0_pmx: i2c0@0 { - i2c0 { - groups = "i2c0_grp"; - function = "i2c0"; - }; - }; - - i2c1_pmx: i2c1@0 { - i2c1 { - groups = "i2c1_grp"; - function = "i2c1"; - }; - }; - - jtag_pmx0: jtag@0 { - jtag_0 { - groups = "jtag_grp0"; - function = "jtag_m0"; - }; - }; - - ks_kas_spi_pmx0: ks_kas_spi@0 { - ks_kas_spi_0 { - groups = "ks_kas_spi_grp0"; - function = "ks_kas_spi_m0"; - }; - }; - - ld_ldd_pmx: ld_ldd@0 { - ld_ldd { - groups = "ld_ldd_grp"; - function = "ld_ldd"; - }; - }; - - ld_ldd_16bit_pmx: ld_ldd_16bit@0 { - ld_ldd_16bit { - groups = "ld_ldd_16bit_grp"; - function = "ld_ldd_16bit"; - }; - }; - - ld_ldd_fck_pmx: ld_ldd_fck@0 { - ld_ldd_fck { - groups = "ld_ldd_fck_grp"; - function = "ld_ldd_fck"; - }; - }; - - ld_ldd_lck_pmx: ld_ldd_lck@0 { - ld_ldd_lck { - groups = "ld_ldd_lck_grp"; - function = "ld_ldd_lck"; - }; - }; - - lr_lcdrom_pmx: lr_lcdrom@0 { - lr_lcdrom { - groups = "lr_lcdrom_grp"; - function = "lr_lcdrom"; - }; - }; - - lvds_analog_pmx: lvds_analog@0 { - lvds_analog { - groups = "lvds_analog_grp"; - function = "lvds_analog"; - }; - }; - - nd_df_pmx: nd_df@0 { - nd_df { - groups = "nd_df_grp"; - function = "nd_df"; - }; - }; - - nd_df_nowp_pmx: nd_df_nowp@0 { - nd_df_nowp { - groups = "nd_df_nowp_grp"; - function = "nd_df_nowp"; - }; - }; - - ps_pmx: ps@0 { - ps { - groups = "ps_grp"; - function = "ps"; - }; - }; - - pwc_core_on_pmx: pwc_core_on@0 { - pwc_core_on { - groups = "pwc_core_on_grp"; - function = "pwc_core_on"; - }; - }; - - pwc_ext_on_pmx: pwc_ext_on@0 { - pwc_ext_on { - groups = "pwc_ext_on_grp"; - function = "pwc_ext_on"; - }; - }; - - pwc_gpio3_clk_pmx: pwc_gpio3_clk@0 { - pwc_gpio3_clk { - groups = "pwc_gpio3_clk_grp"; - function = "pwc_gpio3_clk"; - }; - }; - - pwc_io_on_pmx: pwc_io_on@0 { - pwc_io_on { - groups = "pwc_io_on_grp"; - function = "pwc_io_on"; - }; - }; - - pwc_lowbatt_b_pmx0: pwc_lowbatt_b@0 { - pwc_lowbatt_b_0 { - groups = "pwc_lowbatt_b_grp0"; - function = "pwc_lowbatt_b_m0"; - }; - }; - - pwc_mem_on_pmx: pwc_mem_on@0 { - pwc_mem_on { - groups = "pwc_mem_on_grp"; - function = "pwc_mem_on"; - }; - }; - - pwc_on_key_b_pmx0: pwc_on_key_b@0 { - pwc_on_key_b_0 { - groups = "pwc_on_key_b_grp0"; - function = "pwc_on_key_b_m0"; - }; - }; - - pwc_wakeup_src0_pmx: pwc_wakeup_src0@0 { - pwc_wakeup_src0 { - groups = "pwc_wakeup_src0_grp"; - function = "pwc_wakeup_src0"; - }; - }; - - pwc_wakeup_src1_pmx: pwc_wakeup_src1@0 { - pwc_wakeup_src1 { - groups = "pwc_wakeup_src1_grp"; - function = "pwc_wakeup_src1"; - }; - }; - - pwc_wakeup_src2_pmx: pwc_wakeup_src2@0 { - pwc_wakeup_src2 { - groups = "pwc_wakeup_src2_grp"; - function = "pwc_wakeup_src2"; - }; - }; - - pwc_wakeup_src3_pmx: pwc_wakeup_src3@0 { - pwc_wakeup_src3 { - groups = "pwc_wakeup_src3_grp"; - function = "pwc_wakeup_src3"; - }; - }; - - pw_cko0_pmx0: pw_cko0@0 { - pw_cko0_0 { - groups = "pw_cko0_grp0"; - function = "pw_cko0_m0"; - }; - }; - - pw_cko0_pmx1: pw_cko0@1 { - pw_cko0_1 { - groups = "pw_cko0_grp1"; - function = "pw_cko0_m1"; - }; - }; - - pw_cko0_pmx2: pw_cko0@2 { - pw_cko0_2 { - groups = "pw_cko0_grp2"; - function = "pw_cko0_m2"; - }; - }; - - pw_cko1_pmx0: pw_cko1@0 { - pw_cko1_0 { - groups = "pw_cko1_grp0"; - function = "pw_cko1_m0"; - }; - }; - - pw_cko1_pmx1: pw_cko1@1 { - pw_cko1_1 { - groups = "pw_cko1_grp1"; - function = "pw_cko1_m1"; - }; - }; - - pw_i2s01_clk_pmx0: pw_i2s01_clk@0 { - pw_i2s01_clk_0 { - groups = "pw_i2s01_clk_grp0"; - function = "pw_i2s01_clk_m0"; - }; - }; - - pw_i2s01_clk_pmx1: pw_i2s01_clk@1 { - pw_i2s01_clk_1 { - groups = "pw_i2s01_clk_grp1"; - function = "pw_i2s01_clk_m1"; - }; - }; - - pw_pwm0_pmx: pw_pwm0@0 { - pw_pwm0 { - groups = "pw_pwm0_grp"; - function = "pw_pwm0"; - }; - }; - - pw_pwm1_pmx: pw_pwm1@0 { - pw_pwm1 { - groups = "pw_pwm1_grp"; - function = "pw_pwm1"; - }; - }; - - pw_pwm2_pmx0: pw_pwm2@0 { - pw_pwm2_0 { - groups = "pw_pwm2_grp0"; - function = "pw_pwm2_m0"; - }; - }; - - pw_pwm2_pmx1: pw_pwm2@1 { - pw_pwm2_1 { - groups = "pw_pwm2_grp1"; - function = "pw_pwm2_m1"; - }; - }; - - pw_pwm3_pmx0: pw_pwm3@0 { - pw_pwm3_0 { - groups = "pw_pwm3_grp0"; - function = "pw_pwm3_m0"; - }; - }; - - pw_pwm3_pmx1: pw_pwm3@1 { - pw_pwm3_1 { - groups = "pw_pwm3_grp1"; - function = "pw_pwm3_m1"; - }; - }; - - pw_pwm_cpu_vol_pmx0: pw_pwm_cpu_vol@0 { - pw_pwm_cpu_vol_0 { - groups = "pw_pwm_cpu_vol_grp0"; - function = "pw_pwm_cpu_vol_m0"; - }; - }; - - pw_pwm_cpu_vol_pmx1: pw_pwm_cpu_vol@1 { - pw_pwm_cpu_vol_1 { - groups = "pw_pwm_cpu_vol_grp1"; - function = "pw_pwm_cpu_vol_m1"; - }; - }; - - pw_backlight_pmx0: pw_backlight@0 { - pw_backlight_0 { - groups = "pw_backlight_grp0"; - function = "pw_backlight_m0"; - }; - }; - - pw_backlight_pmx1: pw_backlight@1 { - pw_backlight_1 { - groups = "pw_backlight_grp1"; - function = "pw_backlight_m1"; - }; - }; - - rg_eth_mac_pmx: rg_eth_mac@0 { - rg_eth_mac { - groups = "rg_eth_mac_grp"; - function = "rg_eth_mac"; - }; - }; - - rg_gmac_phy_intr_n_pmx: rg_gmac_phy_intr_n@0 { - rg_gmac_phy_intr_n { - groups = "rg_gmac_phy_intr_n_grp"; - function = "rg_gmac_phy_intr_n"; - }; - }; - - rg_rgmii_mac_pmx: rg_rgmii_mac@0 { - rg_rgmii_mac { - groups = "rg_rgmii_mac_grp"; - function = "rg_rgmii_mac"; - }; - }; - - rg_rgmii_phy_ref_clk_pmx0: rg_rgmii_phy_ref_clk@0 { - rg_rgmii_phy_ref_clk_0 { - groups = - "rg_rgmii_phy_ref_clk_grp0"; - function = - "rg_rgmii_phy_ref_clk_m0"; - }; - }; - - rg_rgmii_phy_ref_clk_pmx1: rg_rgmii_phy_ref_clk@1 { - rg_rgmii_phy_ref_clk_1 { - groups = - "rg_rgmii_phy_ref_clk_grp1"; - function = - "rg_rgmii_phy_ref_clk_m1"; - }; - }; - - sd0_pmx: sd0@0 { - sd0 { - groups = "sd0_grp"; - function = "sd0"; - }; - }; - - sd0_4bit_pmx: sd0_4bit@0 { - sd0_4bit { - groups = "sd0_4bit_grp"; - function = "sd0_4bit"; - }; - }; - - sd1_pmx: sd1@0 { - sd1 { - groups = "sd1_grp"; - function = "sd1"; - }; - }; - - sd1_4bit_pmx0: sd1_4bit@0 { - sd1_4bit_0 { - groups = "sd1_4bit_grp0"; - function = "sd1_4bit_m0"; - }; - }; - - sd1_4bit_pmx1: sd1_4bit@1 { - sd1_4bit_1 { - groups = "sd1_4bit_grp1"; - function = "sd1_4bit_m1"; - }; - }; - - sd2_pmx0: sd2@0 { - sd2_0 { - groups = "sd2_grp0"; - function = "sd2_m0"; - }; - }; - - sd2_no_cdb_pmx0: sd2_no_cdb@0 { - sd2_no_cdb_0 { - groups = "sd2_no_cdb_grp0"; - function = "sd2_no_cdb_m0"; - }; - }; - - sd3_pmx: sd3@0 { - sd3 { - groups = "sd3_grp"; - function = "sd3"; - }; - }; - - sd5_pmx: sd5@0 { - sd5 { - groups = "sd5_grp"; - function = "sd5"; - }; - }; - - sd6_pmx0: sd6@0 { - sd6_0 { - groups = "sd6_grp0"; - function = "sd6_m0"; - }; - }; - - sd6_pmx1: sd6@1 { - sd6_1 { - groups = "sd6_grp1"; - function = "sd6_m1"; - }; - }; - - sp0_ext_ldo_on_pmx: sp0_ext_ldo_on@0 { - sp0_ext_ldo_on { - groups = "sp0_ext_ldo_on_grp"; - function = "sp0_ext_ldo_on"; - }; - }; - - sp0_qspi_pmx: sp0_qspi@0 { - sp0_qspi { - groups = "sp0_qspi_grp"; - function = "sp0_qspi"; - }; - }; - - sp1_spi_pmx: sp1_spi@0 { - sp1_spi { - groups = "sp1_spi_grp"; - function = "sp1_spi"; - }; - }; - - tpiu_trace_pmx: tpiu_trace@0 { - tpiu_trace { - groups = "tpiu_trace_grp"; - function = "tpiu_trace"; - }; - }; - - uart0_pmx: uart0@0 { - uart0 { - groups = "uart0_grp"; - function = "uart0"; - }; - }; - - uart0_nopause_pmx: uart0_nopause@0 { - uart0_nopause { - groups = "uart0_nopause_grp"; - function = "uart0_nopause"; - }; - }; - - uart1_pmx: uart1@0 { - uart1 { - groups = "uart1_grp"; - function = "uart1"; - }; - }; - - uart2_pmx: uart2@0 { - uart2 { - groups = "uart2_grp"; - function = "uart2"; - }; - }; - - uart3_pmx0: uart3@0 { - uart3_0 { - groups = "uart3_grp0"; - function = "uart3_m0"; - }; - }; - - uart3_pmx1: uart3@1 { - uart3_1 { - groups = "uart3_grp1"; - function = "uart3_m1"; - }; - }; - - uart3_pmx2: uart3@2 { - uart3_2 { - groups = "uart3_grp2"; - function = "uart3_m2"; - }; - }; - - uart3_pmx3: uart3@3 { - uart3_3 { - groups = "uart3_grp3"; - function = "uart3_m3"; - }; - }; - - uart3_nopause_pmx0: uart3_nopause@0 { - uart3_nopause_0 { - groups = "uart3_nopause_grp0"; - function = "uart3_nopause_m0"; - }; - }; - - uart3_nopause_pmx1: uart3_nopause@1 { - uart3_nopause_1 { - groups = "uart3_nopause_grp1"; - function = "uart3_nopause_m1"; - }; - }; - - uart4_pmx0: uart4@0 { - uart4_0 { - groups = "uart4_grp0"; - function = "uart4_m0"; - }; - }; - - uart4_pmx1: uart4@1 { - uart4_1 { - groups = "uart4_grp1"; - function = "uart4_m1"; - }; - }; - - uart4_pmx2: uart4@2 { - uart4_2 { - groups = "uart4_grp2"; - function = "uart4_m2"; - }; - }; - - uart4_nopause_pmx: uart4_nopause@0 { - uart4_nopause { - groups = "uart4_nopause_grp"; - function = "uart4_nopause"; - }; - }; - - usb0_drvvbus_pmx: usb0_drvvbus@0 { - usb0_drvvbus { - groups = "usb0_drvvbus_grp"; - function = "usb0_drvvbus"; - }; - }; - - usb1_drvvbus_pmx: usb1_drvvbus@0 { - usb1_drvvbus { - groups = "usb1_drvvbus_grp"; - function = "usb1_drvvbus"; - }; - }; - - visbus_dout_pmx: visbus_dout@0 { - visbus_dout { - groups = "visbus_dout_grp"; - function = "visbus_dout"; - }; - }; - - vi_vip1_pmx: vi_vip1@0 { - vi_vip1 { - groups = "vi_vip1_grp"; - function = "vi_vip1"; - }; - }; - - vi_vip1_ext_pmx: vi_vip1_ext@0 { - vi_vip1_ext { - groups = "vi_vip1_ext_grp"; - function = "vi_vip1_ext"; - }; - }; - - vi_vip1_low8bit_pmx: vi_vip1_low8bit@0 { - vi_vip1_low8bit { - groups = "vi_vip1_low8bit_grp"; - function = "vi_vip1_low8bit"; - }; - }; - - vi_vip1_high8bit_pmx: vi_vip1_high8bit@0 { - vi_vip1_high8bit { - groups = "vi_vip1_high8bit_grp"; - function = "vi_vip1_high8bit"; - }; - }; - }; - - pmipc { - compatible = "arteris, flexnoc", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x13240000 0x13240000 0x00010000>; - pmipc@0x13240000 { - compatible = "sirf,atlas7-pmipc"; - reg = <0x13240000 0x00010000>; - }; - }; - - dramfw { - compatible = "arteris, flexnoc", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x10830000 0x10830000 0x18000>; - dramfw@10820000 { - compatible = "sirf,nocfw-dramfw"; - reg = <0x10830000 0x18000>; - }; - }; - - spramfw { - compatible = "arteris, flexnoc", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x10250000 0x10250000 0x3000>; - spramfw@10820000 { - compatible = "sirf,nocfw-spramfw"; - reg = <0x10250000 0x3000>; - }; - }; - - cpum { - compatible = "arteris, flexnoc", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x10200000 0x10200000 0x3000>; - cpum@10200000 { - compatible = "sirf,nocfw-cpum"; - reg = <0x10200000 0x3000>; - }; - }; - - cgum { - compatible = "arteris, flexnoc", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x18641000 0x18641000 0x3000>, - <0x18620000 0x18620000 0x1000>, - <0x18630000 0x18630000 0x10000>; - - cgum@18641000 { - compatible = "sirf,nocfw-cgum"; - reg = <0x18641000 0x3000>; - }; - - car: clock-controller@18620000 { - compatible = "sirf,atlas7-car"; - reg = <0x18620000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - pwm: pwm@18630000 { - compatible = "sirf,prima2-pwm"; - #pwm-cells = <2>; - reg = <0x18630000 0x10000>; - clocks = <&car 138>, <&car 139>, <&car 237>, - <&car 240>, <&car 140>, <&car 246>; - clock-names = "pwmc", "sigsrc0", "sigsrc1", - "sigsrc2", "sigsrc3", "sigsrc4"; - }; - }; - - gnssm { - compatible = "arteris, flexnoc", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x18000000 0x18000000 0x0000ffff>, - <0x18010000 0x18010000 0x1000>, - <0x18020000 0x18020000 0x1000>, - <0x18030000 0x18030000 0x1000>, - <0x18040000 0x18040000 0x1000>, - <0x18050000 0x18050000 0x1000>, - <0x18060000 0x18060000 0x1000>, - <0x180b0000 0x180b0000 0x4000>, - <0x18100000 0x18100000 0x3000>, - <0x18250000 0x18250000 0x10000>, - <0x18200000 0x18200000 0x1000>; - - dmac0: dma-controller@18000000 { - cell-index = <0>; - compatible = "sirf,atlas7-dmac"; - reg = <0x18000000 0x1000>; - interrupts = <0 12 0>; - clocks = <&car 89>; - dma-channels = <16>; - #dma-cells = <1>; - }; - - gnssmfw@0x18100000 { - compatible = "sirf,nocfw-gnssm"; - reg = <0x18100000 0x3000>; - }; - - uart0: uart@18010000 { - cell-index = <0>; - compatible = "sirf,atlas7-uart"; - reg = <0x18010000 0x1000>; - interrupts = <0 17 0>; - clocks = <&car 90>; - fifosize = <128>; - dmas = <&dmac0 3>, <&dmac0 2>; - dma-names = "rx", "tx"; - }; - - uart1: uart@18020000 { - cell-index = <1>; - compatible = "sirf,atlas7-uart"; - reg = <0x18020000 0x1000>; - interrupts = <0 18 0>; - clocks = <&car 88>; - fifosize = <32>; - }; - - uart2: uart@18030000 { - cell-index = <2>; - compatible = "sirf,atlas7-uart"; - reg = <0x18030000 0x1000>; - interrupts = <0 19 0>; - clocks = <&car 91>; - fifosize = <128>; - dmas = <&dmac0 6>, <&dmac0 7>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - uart3: uart@18040000 { - cell-index = <3>; - compatible = "sirf,atlas7-uart"; - reg = <0x18040000 0x1000>; - interrupts = <0 66 0>; - clocks = <&car 92>; - fifosize = <128>; - dmas = <&dmac0 4>, <&dmac0 5>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - uart4: uart@18050000 { - cell-index = <4>; - compatible = "sirf,atlas7-uart"; - reg = <0x18050000 0x1000>; - interrupts = <0 69 0>; - clocks = <&car 93>; - fifosize = <128>; - dmas = <&dmac0 0>, <&dmac0 1>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - uart5: uart@18060000 { - cell-index = <5>; - compatible = "sirf,atlas7-uart"; - reg = <0x18060000 0x1000>; - interrupts = <0 71 0>; - clocks = <&car 94>; - fifosize = <128>; - dmas = <&dmac0 8>, <&dmac0 9>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - gmac: eth@180b0000 { - compatible = "snps, dwc-eth-qos"; - reg = <0x180b0000 0x4000>; - interrupts = <0 59 0>, <0 70 0>; - interrupt-names = "macirq", "macpmt"; - clocks = <&car 39>, <&car 45>, - <&car 86>, <&car 87>; - clock-names = "gnssm_rgmii", "gnssm_gmac", - "rgmii", "gmac"; - local-mac-address = [00 00 00 00 00 00]; - phy-mode = "rgmii"; - }; - dspub@18250000 { - compatible = "dx,cc44p"; - reg = <0x18250000 0x10000>; - interrupts = <0 27 0>; - }; - - spi1: spi@18200000 { - compatible = "sirf,prima2-spi"; - reg = <0x18200000 0x1000>; - interrupts = <0 16 0>; - clocks = <&car 95>; - #address-cells = <1>; - #size-cells = <0>; - dmas = <&dmac0 12>, <&dmac0 13>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - }; - - - gpum { - compatible = "arteris, flexnoc", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x13000000 0x13000000 0x3000>, - <0x13010000 0x13010000 0x1400>, - <0x13010800 0x13010800 0x100>, - <0x13011000 0x13011000 0x100>; - gpum@0x13000000 { - compatible = "sirf,nocfw-gpum"; - reg = <0x13000000 0x3000>; - }; - dmacsdrr: dma-controller@13010800 { - cell-index = <5>; - compatible = "sirf,atlas7-dmac-v2"; - reg = <0x13010800 0x100>; - interrupts = <0 8 0>; - clocks = <&car 127>; - #dma-cells = <1>; - #dma-channels = <1>; - }; - dmacsdrw: dma-controller@13011000 { - cell-index = <6>; - compatible = "sirf,atlas7-dmac-v2"; - reg = <0x13011000 0x100>; - interrupts = <0 9 0>; - clocks = <&car 127>; - #dma-cells = <1>; - #dma-channels = <1>; - }; - sdr@0x13010000 { - compatible = "sirf,atlas7-sdr"; - reg = <0x13010000 0x1400>; - interrupts = <0 7 0>, - <0 8 0>, - <0 9 0>; - clocks = <&car 127>; - dmas = <&dmacsdrr 0>, <&dmacsdrw 0>; - dma-names = "tx", "rx"; - }; - }; - - mediam { - compatible = "arteris, flexnoc", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x15000000 0x15000000 0x00600000>, - <0x16000000 0x16000000 0x00200000>, - <0x17000000 0x17000000 0x10000>, - <0x17020000 0x17020000 0x1000>, - <0x17030000 0x17030000 0x1000>, - <0x17040000 0x17040000 0x1000>, - <0x17050000 0x17050000 0x10000>, - <0x17060000 0x17060000 0x200>, - <0x17060200 0x17060200 0x100>, - <0x17070000 0x17070000 0x200>, - <0x17070200 0x17070200 0x100>, - <0x170A0000 0x170A0000 0x3000>; - - multimedia@15000000 { - compatible = "sirf,atlas7-video-codec"; - reg = <0x15000000 0x10000>; - interrupts = <0 5 0>; - clocks = <&car 102>; - }; - - mediam@170A0000 { - compatible = "sirf,nocfw-mediam"; - reg = <0x170A0000 0x3000>; - }; - - gpio_0: gpio_mediam@17040000 { - #gpio-cells = <2>; - #interrupt-cells = <2>; - compatible = "sirf,atlas7-gpio"; - reg = <0x17040000 0x1000>; - interrupts = <0 13 0>, <0 14 0>; - clocks = <&car 107>; - clock-names = "gpio0_io"; - gpio-controller; - interrupt-controller; - - gpio-banks = <2>; - gpio-ranges = <&pinctrl 0 0 0>, - <&pinctrl 32 0 0>; - gpio-ranges-group-names = "lvds_gpio_grp", - "uart_nand_gpio_grp"; - }; - - nand@17050000 { - compatible = "sirf,atlas7-nand"; - reg = <0x17050000 0x10000>; - pinctrl-names = "default"; - pinctrl-0 = <&nd_df_pmx>; - interrupts = <0 41 0>; - clocks = <&car 108>, <&car 112>; - clock-names = "nand_io", "nand_nand"; - }; - - sd0: sdhci@16000000 { - cell-index = <0>; - compatible = "sirf,atlas7-sdhc"; - reg = <0x16000000 0x100000>; - interrupts = <0 38 0>; - clocks = <&car 109>, <&car 111>; - clock-names = "core", "iface"; - wp-inverted; - non-removable; - status = "disabled"; - bus-width = <8>; - }; - - sd1: sdhci@16100000 { - cell-index = <1>; - compatible = "sirf,atlas7-sdhc"; - reg = <0x16100000 0x100000>; - interrupts = <0 38 0>; - clocks = <&car 109>, <&car 111>; - clock-names = "core", "iface"; - non-removable; - status = "disabled"; - bus-width = <8>; - }; - - jpeg@17000000 { - compatible = "sirf,atlas7-jpeg"; - reg = <0x17000000 0x10000>; - interrupts = <0 72 0>, - <0 73 0>; - clocks = <&car 103>; - }; - - usb0: usb@17060000 { - cell-index = <0>; - compatible = "sirf,atlas7-usb"; - reg = <0x17060000 0x200>; - interrupts = <0 10 0>; - clocks = <&car 113>; - sirf,usbphy = <&usbphy0>; - phy_type = "utmi"; - dr_mode = "otg"; - maximum-speed = "high-speed"; - status = "okay"; - }; - - usb1: usb@17070000 { - cell-index = <1>; - compatible = "sirf,atlas7-usb"; - reg = <0x17070000 0x200>; - interrupts = <0 11 0>; - clocks = <&car 114>; - sirf,usbphy = <&usbphy1>; - phy_type = "utmi"; - dr_mode = "host"; - maximum-speed = "high-speed"; - status = "okay"; - }; - - usbphy0: usbphy@0 { - compatible = "sirf,atlas7-usbphy"; - reg = <0x17060200 0x100>; - clocks = <&car 115>; - status = "okay"; - }; - - usbphy1: usbphy@1 { - compatible = "sirf,atlas7-usbphy"; - reg = <0x17070200 0x100>; - clocks = <&car 116>; - status = "okay"; - }; - - i2c0: i2c@17020000 { - cell-index = <0>; - compatible = "sirf,prima2-i2c"; - reg = <0x17020000 0x1000>; - interrupts = <0 24 0>; - clocks = <&car 105>; - #address-cells = <1>; - #size-cells = <0>; - }; - - }; - - vdifm { - compatible = "arteris, flexnoc", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x13290000 0x13290000 0x3000>, - <0x13300000 0x13300000 0x1000>, - <0x14200000 0x14200000 0x600000>; - - vdifm@13290000 { - compatible = "sirf,nocfw-vdifm"; - reg = <0x13290000 0x3000>; - }; - - gpio_1: gpio_vdifm@13300000 { - #gpio-cells = <2>; - #interrupt-cells = <2>; - compatible = "sirf,atlas7-gpio"; - reg = <0x13300000 0x1000>; - interrupts = <0 43 0>, <0 44 0>, - <0 45 0>, <0 46 0>; - clocks = <&car 84>; - clock-names = "gpio1_io"; - gpio-controller; - interrupt-controller; - - gpio-banks = <4>; - gpio-ranges = <&pinctrl 0 0 0>, - <&pinctrl 32 0 0>, - <&pinctrl 64 0 0>, - <&pinctrl 96 0 0>; - gpio-ranges-group-names = "gnss_gpio_grp", - "lcd_vip_gpio_grp", - "sdio_i2s_gpio_grp", - "sp_rgmii_gpio_grp"; - }; - - sd2: sdhci@14200000 { - cell-index = <2>; - compatible = "sirf,atlas7-sdhc"; - reg = <0x14200000 0x100000>; - interrupts = <0 23 0>; - clocks = <&car 70>, <&car 75>; - clock-names = "core", "iface"; - status = "disabled"; - bus-width = <4>; - sd-uhs-sdr50; - vqmmc-supply = <&vqmmc>; - vqmmc: vqmmc@2 { - regulator-min-microvolt = <1650000>; - regulator-max-microvolt = <1950000>; - regulator-name = "vqmmc-ldo"; - regulator-type = "voltage"; - regulator-boot-on; - regulator-allow-bypass; - }; - }; - - sd3: sdhci@14300000 { - cell-index = <3>; - compatible = "sirf,atlas7-sdhc"; - reg = <0x14300000 0x100000>; - interrupts = <0 23 0>; - clocks = <&car 76>, <&car 81>; - clock-names = "core", "iface"; - status = "disabled"; - bus-width = <4>; - }; - - sd5: sdhci@14500000 { - cell-index = <5>; - compatible = "sirf,atlas7-sdhc"; - reg = <0x14500000 0x100000>; - interrupts = <0 39 0>; - clocks = <&car 71>, <&car 76>; - clock-names = "core", "iface"; - status = "disabled"; - bus-width = <4>; - loop-dma; - }; - - sd6: sdhci@14600000 { - cell-index = <6>; - compatible = "sirf,atlas7-sdhc"; - reg = <0x14600000 0x100000>; - interrupts = <0 98 0>; - clocks = <&car 72>, <&car 77>; - clock-names = "core", "iface"; - status = "disabled"; - bus-width = <4>; - }; - - sd7: sdhci@14700000 { - cell-index = <7>; - compatible = "sirf,atlas7-sdhc"; - reg = <0x14700000 0x100000>; - interrupts = <0 98 0>; - clocks = <&car 72>, <&car 77>; - clock-names = "core", "iface"; - status = "disabled"; - bus-width = <4>; - }; - }; - - audiom { - compatible = "arteris, flexnoc", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x10d50000 0x10d50000 0x0000ffff>, - <0x10d60000 0x10d60000 0x0000ffff>, - <0x10d80000 0x10d80000 0x0000ffff>, - <0x10d90000 0x10d90000 0x0000ffff>, - <0x10ED0000 0x10ED0000 0x3000>, - <0x10dc8000 0x10dc8000 0x1000>, - <0x10dc0000 0x10dc0000 0x1000>, - <0x10db0000 0x10db0000 0x4000>, - <0x10d40000 0x10d40000 0x1000>, - <0x10d30000 0x10d30000 0x1000>; - - timer@10dc0000 { - compatible = "sirf,atlas7-tick"; - reg = <0x10dc0000 0x1000>; - interrupts = <0 0 0>, - <0 1 0>, - <0 2 0>, - <0 49 0>, - <0 50 0>, - <0 51 0>; - clocks = <&car 47>; - }; - - timerb@10dc8000 { - compatible = "sirf,atlas7-tick"; - reg = <0x10dc8000 0x1000>; - interrupts = <0 74 0>, - <0 75 0>, - <0 76 0>, - <0 77 0>, - <0 78 0>, - <0 79 0>; - clocks = <&car 47>; - }; - - vip0@10db0000 { - compatible = "sirf,atlas7-vip0"; - reg = <0x10db0000 0x2000>; - interrupts = <0 85 0>; - sirf,vip_cma_size = <0xC00000>; - }; - - cvd@10db2000 { - compatible = "sirf,cvd"; - reg = <0x10db2000 0x2000>; - clocks = <&car 46>; - }; - - dmac2: dma-controller@10d50000 { - cell-index = <2>; - compatible = "sirf,atlas7-dmac"; - reg = <0x10d50000 0xffff>; - interrupts = <0 55 0>; - clocks = <&car 60>; - dma-channels = <16>; - #dma-cells = <1>; - }; - - dmac3: dma-controller@10d60000 { - cell-index = <3>; - compatible = "sirf,atlas7-dmac"; - reg = <0x10d60000 0xffff>; - interrupts = <0 56 0>; - clocks = <&car 61>; - dma-channels = <16>; - #dma-cells = <1>; - }; - - adc: adc@10d80000 { - compatible = "sirf,atlas7-adc"; - reg = <0x10d80000 0xffff>; - interrupts = <0 34 0>; - clocks = <&car 49>; - #io-channel-cells = <1>; - }; - - pulsec@10d90000 { - compatible = "sirf,prima2-pulsec"; - reg = <0x10d90000 0xffff>; - interrupts = <0 42 0>; - clocks = <&car 54>; - }; - - audiom@10ED0000 { - compatible = "sirf,nocfw-audiom"; - reg = <0x10ED0000 0x3000>; - interrupts = <0 102 0>; - }; - - usp1: usp@10d30000 { - cell-index = <1>; - reg = <0x10d30000 0x1000>; - fifosize = <512>; - clocks = <&car 58>; - dmas = <&dmac2 6>, <&dmac2 7>; - dma-names = "rx", "tx"; - }; - - usp2: usp@10d40000 { - cell-index = <2>; - reg = <0x10d40000 0x1000>; - interrupts = <0 22 0>; - clocks = <&car 59>; - dmas = <&dmac2 12>, <&dmac2 13>; - dma-names = "rx", "tx"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - ddrm { - compatible = "arteris, flexnoc", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x10820000 0x10820000 0x3000>, - <0x10800000 0x10800000 0x2000>; - ddrm@10820000 { - compatible = "sirf,nocfw-ddrm"; - reg = <0x10820000 0x3000>; - interrupts = <0 105 0>; - }; - - memory-controller@0x10800000 { - compatible = "sirf,atlas7-memc"; - reg = <0x10800000 0x2000>; - }; - - }; - - btm { - compatible = "arteris, flexnoc", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x11002000 0x11002000 0x0000ffff>, - <0x11010000 0x11010000 0x3000>, - <0x11000000 0x11000000 0x1000>, - <0x11001000 0x11001000 0x1000>; - - dmac4: dma-controller@11002000 { - cell-index = <4>; - compatible = "sirf,atlas7-dmac"; - reg = <0x11002000 0x1000>; - interrupts = <0 99 0>; - clocks = <&car 130>; - dma-channels = <16>; - #dma-cells = <1>; - }; - uart6: uart@11000000 { - cell-index = <6>; - compatible = "sirf,atlas7-bt-uart", - "sirf,atlas7-uart"; - reg = <0x11000000 0x1000>; - interrupts = <0 100 0>; - clocks = <&car 131>, <&car 133>, <&car 134>; - clock-names = "uart", "general", "noc"; - fifosize = <128>; - dmas = <&dmac4 12>, <&dmac4 13>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - usp3: usp@11001000 { - compatible = "sirf,atlas7-bt-usp", - "sirf,prima2-usp-pcm"; - cell-index = <3>; - reg = <0x11001000 0x1000>; - fifosize = <512>; - clocks = <&car 132>, <&car 129>, <&car 133>, - <&car 134>, <&car 135>; - clock-names = "usp3_io", "a7ca_btss", "a7ca_io", - "noc_btm_io", "thbtm_io"; - dmas = <&dmac4 0>, <&dmac4 1>; - dma-names = "rx", "tx"; - }; - - btm@11010000 { - compatible = "sirf,nocfw-btm"; - reg = <0x11010000 0x3000>; - }; - }; - - rtcm { - compatible = "arteris, flexnoc", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x18810000 0x18810000 0x3000>, - <0x18840000 0x18840000 0x1000>, - <0x18890000 0x18890000 0x1000>, - <0x188B0000 0x188B0000 0x10000>, - <0x188D0000 0x188D0000 0x1000>; - rtcm@18810000 { - compatible = "sirf,nocfw-rtcm"; - reg = <0x18810000 0x3000>; - interrupts = <0 109 0>; - }; - - gpio_2: gpio_rtcm@18890000 { - #gpio-cells = <2>; - #interrupt-cells = <2>; - compatible = "sirf,atlas7-gpio"; - reg = <0x18890000 0x1000>; - interrupts = <0 47 0>; - gpio-controller; - interrupt-controller; - - gpio-banks = <1>; - gpio-ranges = <&pinctrl 0 0 0>; - gpio-ranges-group-names = "rtc_gpio_grp"; - }; - - rtc-iobg@18840000 { - compatible = "sirf,prima2-rtciobg", - "sirf-prima2-rtciobg-bus", - "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x18840000 0x1000>; - - sysrtc@2000 { - compatible = "sirf,prima2-sysrtc"; - reg = <0x2000 0x100>; - interrupts = <0 52 0>; - }; - pwrc@3000 { - compatible = "sirf,atlas7-pwrc"; - reg = <0x3000 0x100>; - }; - }; - - qspi: flash@188B0000 { - cell-index = <0>; - compatible = "sirf,atlas7-qspi-nor"; - reg = <0x188B0000 0x10000>; - interrupts = <0 15 0>; - #address-cells = <1>; - #size-cells = <0>; - }; - - retain@0x188D0000 { - compatible = "sirf,atlas7-retain"; - reg = <0x188D0000 0x1000>; - }; - - }; - disp-iobg { - /* lcdc0 */ - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x13100000 0x13100000 0x20000>, - <0x10e10000 0x10e10000 0x10000>, - <0x17010000 0x17010000 0x10000>; - - lcd@13100000 { - compatible = "sirf,atlas7-lcdc"; - reg = <0x13100000 0x10000>; - interrupts = <0 30 0>; - clocks = <&car 79>; - }; - vpp@13110000 { - compatible = "sirf,atlas7-vpp"; - reg = <0x13110000 0x10000>; - interrupts = <0 31 0>; - clocks = <&car 78>; - resets = <&car 29>; - }; - lvds@10e10000 { - compatible = "sirf,atlas7-lvdsc"; - reg = <0x10e10000 0x10000>; - interrupts = <0 64 0>; - clocks = <&car 54>; - resets = <&car 29>; - }; - g2d@17010000 { - compatible = "sirf, atlas7-g2d"; - reg = <0x17010000 0x10000>; - interrupts = <0 61 0>; - clocks = <&car 104>; - }; - - }; - - graphics-iobg { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x12000000 0x12000000 0x1000000>; - - graphics@12000000 { - compatible = "powervr,sgx531"; - reg = <0x12000000 0x1000000>; - interrupts = <0 6 0>; - clocks = <&car 126>; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/axm5516-amarillo.dts b/sys/gnu/dts/arm/axm5516-amarillo.dts deleted file mode 100644 index 2e2ad3c7ee7..00000000000 --- a/sys/gnu/dts/arm/axm5516-amarillo.dts +++ /dev/null @@ -1,47 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * arch/arm/boot/dts/axm5516-amarillo.dts - * - * Copyright (C) 2013 LSI - */ - -/dts-v1/; - -/memreserve/ 0x00000000 0x00400000; - -#include "axm55xx.dtsi" -#include "axm5516-cpus.dtsi" - -/ { - model = "Amarillo AXM5516"; - compatible = "lsi,axm5516-amarillo", "lsi,axm5516"; - - memory { - device_type = "memory"; - reg = <0 0x00000000 0x02 0x00000000>; - }; -}; - -&serial0 { - status = "okay"; -}; - -&serial1 { - status = "okay"; -}; - -&serial2 { - status = "okay"; -}; - -&serial3 { - status = "okay"; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/axm5516-cpus.dtsi b/sys/gnu/dts/arm/axm5516-cpus.dtsi deleted file mode 100644 index 3bcf4e0a3c8..00000000000 --- a/sys/gnu/dts/arm/axm5516-cpus.dtsi +++ /dev/null @@ -1,200 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * arch/arm/boot/dts/axm5516-cpus.dtsi - * - * Copyright (C) 2013 LSI - */ - -/ { - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu-map { - cluster0 { - core0 { - cpu = <&CPU0>; - }; - core1 { - cpu = <&CPU1>; - }; - core2 { - cpu = <&CPU2>; - }; - core3 { - cpu = <&CPU3>; - }; - }; - cluster1 { - core0 { - cpu = <&CPU4>; - }; - core1 { - cpu = <&CPU5>; - }; - core2 { - cpu = <&CPU6>; - }; - core3 { - cpu = <&CPU7>; - }; - }; - cluster2 { - core0 { - cpu = <&CPU8>; - }; - core1 { - cpu = <&CPU9>; - }; - core2 { - cpu = <&CPU10>; - }; - core3 { - cpu = <&CPU11>; - }; - }; - cluster3 { - core0 { - cpu = <&CPU12>; - }; - core1 { - cpu = <&CPU13>; - }; - core2 { - cpu = <&CPU14>; - }; - core3 { - cpu = <&CPU15>; - }; - }; - }; - - CPU0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x00>; - clock-frequency= <1400000000>; - cpu-release-addr = <0>; // Fixed by the boot loader - }; - - CPU1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x01>; - clock-frequency= <1400000000>; - cpu-release-addr = <0>; // Fixed by the boot loader - }; - - CPU2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x02>; - clock-frequency= <1400000000>; - cpu-release-addr = <0>; // Fixed by the boot loader - }; - - CPU3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x03>; - clock-frequency= <1400000000>; - cpu-release-addr = <0>; // Fixed by the boot loader - }; - - CPU4: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x100>; - clock-frequency= <1400000000>; - cpu-release-addr = <0>; // Fixed by the boot loader - }; - - CPU5: cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x101>; - clock-frequency= <1400000000>; - cpu-release-addr = <0>; // Fixed by the boot loader - }; - - CPU6: cpu@102 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x102>; - clock-frequency= <1400000000>; - cpu-release-addr = <0>; // Fixed by the boot loader - }; - - CPU7: cpu@103 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x103>; - clock-frequency= <1400000000>; - cpu-release-addr = <0>; // Fixed by the boot loader - }; - - CPU8: cpu@200 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x200>; - clock-frequency= <1400000000>; - cpu-release-addr = <0>; // Fixed by the boot loader - }; - - CPU9: cpu@201 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x201>; - clock-frequency= <1400000000>; - cpu-release-addr = <0>; // Fixed by the boot loader - }; - - CPU10: cpu@202 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x202>; - clock-frequency= <1400000000>; - cpu-release-addr = <0>; // Fixed by the boot loader - }; - - CPU11: cpu@203 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x203>; - clock-frequency= <1400000000>; - cpu-release-addr = <0>; // Fixed by the boot loader - }; - - CPU12: cpu@300 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x300>; - clock-frequency= <1400000000>; - cpu-release-addr = <0>; // Fixed by the boot loader - }; - - CPU13: cpu@301 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x301>; - clock-frequency= <1400000000>; - cpu-release-addr = <0>; // Fixed by the boot loader - }; - - CPU14: cpu@302 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x302>; - clock-frequency= <1400000000>; - cpu-release-addr = <0>; // Fixed by the boot loader - }; - - CPU15: cpu@303 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x303>; - clock-frequency= <1400000000>; - cpu-release-addr = <0>; // Fixed by the boot loader - }; - }; -}; diff --git a/sys/gnu/dts/arm/axm55xx.dtsi b/sys/gnu/dts/arm/axm55xx.dtsi deleted file mode 100644 index 7676a65059a..00000000000 --- a/sys/gnu/dts/arm/axm55xx.dtsi +++ /dev/null @@ -1,200 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * arch/arm/boot/dts/axm55xx.dtsi - * - * Copyright (C) 2013 LSI - */ - -#include -#include - -/ { - #address-cells = <2>; - #size-cells = <2>; - interrupt-parent = <&gic>; - - aliases { - serial0 = &serial0; - serial1 = &serial1; - serial2 = &serial2; - serial3 = &serial3; - timer = &timer0; - }; - - clocks { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - clk_ref0: clk_ref0 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <125000000>; - }; - - clk_ref1: clk_ref1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <125000000>; - }; - - clk_ref2: clk_ref2 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <125000000>; - }; - - clks: clock-controller@2010020000 { - compatible = "lsi,axm5516-clks"; - #clock-cells = <1>; - reg = <0x20 0x10020000 0 0x20000>; - }; - }; - - gic: interrupt-controller@2001001000 { - compatible = "arm,cortex-a15-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x20 0x01001000 0 0x1000>, - <0x20 0x01002000 0 0x2000>, - <0x20 0x01004000 0 0x2000>, - <0x20 0x01006000 0 0x2000>; - interrupts = ; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = - , - , - , - ; - }; - - - pmu { - compatible = "arm,cortex-a15-pmu"; - interrupts = ; - }; - - soc { - compatible = "simple-bus"; - device_type = "soc"; - #address-cells = <2>; - #size-cells = <2>; - interrupt-parent = <&gic>; - ranges; - - syscon: syscon@2010030000 { - compatible = "lsi,axxia-syscon", "syscon"; - reg = <0x20 0x10030000 0 0x2000>; - }; - - reset: reset@2010031000 { - compatible = "lsi,axm55xx-reset"; - syscon = <&syscon>; - }; - - amba { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - serial0: uart@2010080000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x20 0x10080000 0 0x1000>; - interrupts = ; - clocks = <&clks AXXIA_CLK_PER>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - serial1: uart@2010081000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x20 0x10081000 0 0x1000>; - interrupts = ; - clocks = <&clks AXXIA_CLK_PER>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - serial2: uart@2010082000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x20 0x10082000 0 0x1000>; - interrupts = ; - clocks = <&clks AXXIA_CLK_PER>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - serial3: uart@2010083000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x20 0x10083000 0 0x1000>; - interrupts = ; - clocks = <&clks AXXIA_CLK_PER>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - timer0: timer@2010091000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x20 0x10091000 0 0x1000>; - interrupts = , - , - , - , - , - , - , - , - ; - clocks = <&clks AXXIA_CLK_PER>; - clock-names = "apb_pclk"; - status = "okay"; - }; - - gpio0: gpio@2010092000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0x20 0x10092000 0x00 0x1000>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&clks AXXIA_CLK_PER>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - gpio1: gpio@2010093000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0x20 0x10093000 0x00 0x1000>; - interrupts = ; - clocks = <&clks AXXIA_CLK_PER>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - }; - }; -}; - -/* - Local Variables: - mode: C - End: -*/ diff --git a/sys/gnu/dts/arm/axp152.dtsi b/sys/gnu/dts/arm/axp152.dtsi deleted file mode 100644 index f90ad6c64a0..00000000000 --- a/sys/gnu/dts/arm/axp152.dtsi +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright 2015 Chen-Yu Tsai - * - * Chen-Yu Tsai - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -&axp152 { - compatible = "x-powers,axp152"; - interrupt-controller; - #interrupt-cells = <1>; -}; diff --git a/sys/gnu/dts/arm/axp209.dtsi b/sys/gnu/dts/arm/axp209.dtsi deleted file mode 100644 index 0d9ff12bdf2..00000000000 --- a/sys/gnu/dts/arm/axp209.dtsi +++ /dev/null @@ -1,119 +0,0 @@ -/* - * Copyright 2015 Chen-Yu Tsai - * - * Chen-Yu Tsai - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/* - * AXP202/209 Integrated Power Management Chip - * http://www.x-powers.com/product/AXP20X.php - * http://dl.linux-sunxi.org/AXP/AXP209%20Datasheet%20v1.0_cn.pdf - */ - -&axp209 { - compatible = "x-powers,axp209"; - interrupt-controller; - #interrupt-cells = <1>; - - ac_power_supply: ac-power-supply { - compatible = "x-powers,axp202-ac-power-supply"; - status = "disabled"; - }; - - axp_adc: adc { - compatible = "x-powers,axp209-adc"; - #io-channel-cells = <1>; - }; - - axp_gpio: gpio { - compatible = "x-powers,axp209-gpio"; - gpio-controller; - #gpio-cells = <2>; - }; - - battery_power_supply: battery-power-supply { - compatible = "x-powers,axp209-battery-power-supply"; - status = "disabled"; - }; - - regulators { - /* Default work frequency for buck regulators */ - x-powers,dcdc-freq = <1500>; - - reg_dcdc2: dcdc2 { - regulator-name = "dcdc2"; - }; - - reg_dcdc3: dcdc3 { - regulator-name = "dcdc3"; - }; - - reg_ldo1: ldo1 { - /* LDO1 is a fixed output regulator */ - regulator-always-on; - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - regulator-name = "ldo1"; - }; - - reg_ldo2: ldo2 { - regulator-name = "ldo2"; - }; - - reg_ldo3: ldo3 { - regulator-name = "ldo3"; - }; - - reg_ldo4: ldo4 { - regulator-name = "ldo4"; - }; - - reg_ldo5: ldo5 { - regulator-name = "ldo5"; - status = "disabled"; - }; - }; - - usb_power_supply: usb-power-supply { - compatible = "x-powers,axp202-usb-power-supply"; - status = "disabled"; - }; -}; diff --git a/sys/gnu/dts/arm/axp223.dtsi b/sys/gnu/dts/arm/axp223.dtsi deleted file mode 100644 index b91b6c1278c..00000000000 --- a/sys/gnu/dts/arm/axp223.dtsi +++ /dev/null @@ -1,58 +0,0 @@ -/* - * Copyright 2016 Free Electrons - * - * Quentin Schulz - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/* - * AXP223 Integrated Power Management Chip - * http://www.x-powers.com/product/AXP22X.php - * http://dl.linux-sunxi.org/AXP/AXP223-en.pdf - * - * The AXP223 shares most of its logic with the AXP221 but it has some - * differences, for the VBUS driver for example. - */ - -#include "axp22x.dtsi" - -&usb_power_supply { - compatible = "x-powers,axp223-usb-power-supply"; -}; diff --git a/sys/gnu/dts/arm/axp22x.dtsi b/sys/gnu/dts/arm/axp22x.dtsi deleted file mode 100644 index 65a07a67aca..00000000000 --- a/sys/gnu/dts/arm/axp22x.dtsi +++ /dev/null @@ -1,170 +0,0 @@ -/* - * Copyright 2015 Chen-Yu Tsai - * - * Chen-Yu Tsai - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/* - * AXP221/221s/223 Integrated Power Management Chip - * http://www.x-powers.com/product/AXP22X.php - * http://dl.linux-sunxi.org/AXP/AXP221%20Datasheet%20V1.2%2020130326%20.pdf - */ - -&axp22x { - interrupt-controller; - #interrupt-cells = <1>; - - ac_power_supply: ac-power-supply { - compatible = "x-powers,axp221-ac-power-supply"; - status = "disabled"; - }; - - axp_adc: adc { - compatible = "x-powers,axp221-adc"; - #io-channel-cells = <1>; - }; - - battery_power_supply: battery-power-supply { - compatible = "x-powers,axp221-battery-power-supply"; - status = "disabled"; - }; - - regulators { - /* Default work frequency for buck regulators */ - x-powers,dcdc-freq = <3000>; - - reg_dcdc1: dcdc1 { - regulator-name = "dcdc1"; - }; - - reg_dcdc2: dcdc2 { - regulator-name = "dcdc2"; - }; - - reg_dcdc3: dcdc3 { - regulator-name = "dcdc3"; - }; - - reg_dcdc4: dcdc4 { - regulator-name = "dcdc4"; - }; - - reg_dcdc5: dcdc5 { - regulator-name = "dcdc5"; - }; - - reg_dc1sw: dc1sw { - regulator-name = "dc1sw"; - }; - - reg_dc5ldo: dc5ldo { - regulator-name = "dc5ldo"; - }; - - reg_aldo1: aldo1 { - regulator-name = "aldo1"; - }; - - reg_aldo2: aldo2 { - regulator-name = "aldo2"; - }; - - reg_aldo3: aldo3 { - regulator-name = "aldo3"; - }; - - reg_dldo1: dldo1 { - regulator-name = "dldo1"; - }; - - reg_dldo2: dldo2 { - regulator-name = "dldo2"; - }; - - reg_dldo3: dldo3 { - regulator-name = "dldo3"; - }; - - reg_dldo4: dldo4 { - regulator-name = "dldo4"; - }; - - reg_eldo1: eldo1 { - regulator-name = "eldo1"; - }; - - reg_eldo2: eldo2 { - regulator-name = "eldo2"; - }; - - reg_eldo3: eldo3 { - regulator-name = "eldo3"; - }; - - reg_ldo_io0: ldo_io0 { - regulator-name = "ldo_io0"; - status = "disabled"; - }; - - reg_ldo_io1: ldo_io1 { - regulator-name = "ldo_io1"; - status = "disabled"; - }; - - reg_rtc_ldo: rtc_ldo { - /* RTC_LDO is a fixed, always-on regulator */ - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "rtc_ldo"; - }; - - reg_drivevbus: drivevbus { - regulator-name = "drivevbus"; - status = "disabled"; - }; - }; - - usb_power_supply: usb_power_supply { - compatible = "x-powers,axp221-usb-power-supply"; - status = "disabled"; - }; -}; diff --git a/sys/gnu/dts/arm/axp809.dtsi b/sys/gnu/dts/arm/axp809.dtsi deleted file mode 100644 index ab8e5f2d924..00000000000 --- a/sys/gnu/dts/arm/axp809.dtsi +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright 2015 Chen-Yu Tsai - * - * Chen-Yu Tsai - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/* - * AXP809 Integrated Power Management Chip - */ - -&axp809 { - compatible = "x-powers,axp809"; - interrupt-controller; - #interrupt-cells = <1>; -}; diff --git a/sys/gnu/dts/arm/axp81x.dtsi b/sys/gnu/dts/arm/axp81x.dtsi deleted file mode 100644 index 1dfeeceabf4..00000000000 --- a/sys/gnu/dts/arm/axp81x.dtsi +++ /dev/null @@ -1,178 +0,0 @@ -/* - * Copyright 2017 Chen-Yu Tsai - * - * Chen-Yu Tsai - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/* AXP813/818 Integrated Power Management Chip */ - -&axp81x { - interrupt-controller; - #interrupt-cells = <1>; - - ac_power_supply: ac-power-supply { - compatible = "x-powers,axp813-ac-power-supply"; - status = "disabled"; - }; - - axp_adc: adc { - compatible = "x-powers,axp813-adc"; - #io-channel-cells = <1>; - }; - - axp_gpio: gpio { - compatible = "x-powers,axp813-gpio"; - gpio-controller; - #gpio-cells = <2>; - - gpio0_ldo: gpio0-ldo { - pins = "GPIO0"; - function = "ldo"; - }; - - gpio1_ldo: gpio1-ldo { - pins = "GPIO1"; - function = "ldo"; - }; - }; - - battery_power_supply: battery-power-supply { - compatible = "x-powers,axp813-battery-power-supply"; - status = "disabled"; - }; - - regulators { - /* Default work frequency for buck regulators */ - x-powers,dcdc-freq = <3000>; - - reg_dcdc1: dcdc1 { - }; - - reg_dcdc2: dcdc2 { - }; - - reg_dcdc3: dcdc3 { - }; - - reg_dcdc4: dcdc4 { - }; - - reg_dcdc5: dcdc5 { - }; - - reg_dcdc6: dcdc6 { - }; - - reg_dcdc7: dcdc7 { - }; - - reg_aldo1: aldo1 { - }; - - reg_aldo2: aldo2 { - }; - - reg_aldo3: aldo3 { - }; - - reg_dldo1: dldo1 { - }; - - reg_dldo2: dldo2 { - }; - - reg_dldo3: dldo3 { - }; - - reg_dldo4: dldo4 { - }; - - reg_eldo1: eldo1 { - }; - - reg_eldo2: eldo2 { - }; - - reg_eldo3: eldo3 { - }; - - reg_fldo1: fldo1 { - }; - - reg_fldo2: fldo2 { - }; - - reg_fldo3: fldo3 { - }; - - reg_ldo_io0: ldo-io0 { - pinctrl-names = "default"; - pinctrl-0 = <&gpio0_ldo>; - /* Disable by default to avoid conflicts with GPIO */ - status = "disabled"; - }; - - reg_ldo_io1: ldo-io1 { - pinctrl-names = "default"; - pinctrl-0 = <&gpio1_ldo>; - /* Disable by default to avoid conflicts with GPIO */ - status = "disabled"; - }; - - reg_rtc_ldo: rtc-ldo { - /* RTC_LDO is a fixed, always-on regulator */ - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - reg_sw: sw { - }; - - reg_drivevbus: drivevbus { - status = "disabled"; - }; - }; - - usb_power_supply: usb-power-supply { - compatible = "x-powers,axp813-usb-power-supply"; - }; -}; diff --git a/sys/gnu/dts/arm/bcm-cygnus-clock.dtsi b/sys/gnu/dts/arm/bcm-cygnus-clock.dtsi deleted file mode 100644 index 52f91a12a99..00000000000 --- a/sys/gnu/dts/arm/bcm-cygnus-clock.dtsi +++ /dev/null @@ -1,133 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright(c) 2014 Broadcom Corporation. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - osc: oscillator { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <25000000>; - }; - - /* Cygnus ARM PLL */ - armpll: armpll@19000000 { - #clock-cells = <0>; - compatible = "brcm,cygnus-armpll"; - clocks = <&osc>; - reg = <0x19000000 0x1000>; - }; - - /* peripheral clock for system timer */ - periph_clk: arm_periph_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&armpll>; - clock-div = <2>; - clock-mult = <1>; - }; - - /* APB bus clock */ - apb_clk: apb_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&armpll>; - clock-div = <4>; - clock-mult = <1>; - }; - - genpll: genpll@301d000 { - #clock-cells = <1>; - compatible = "brcm,cygnus-genpll"; - reg = <0x0301d000 0x2c>, <0x0301c020 0x4>; - clocks = <&osc>; - clock-output-names = "genpll", "axi21", "250mhz", "ihost_sys", - "enet_sw", "audio_125", "can"; - }; - - /* always 1/2 of the axi21 clock */ - axi41_clk: axi41_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&genpll 1>; - clock-div = <2>; - clock-mult = <1>; - }; - - /* always 1/4 of the axi21 clock */ - axi81_clk: axi81_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&genpll 1>; - clock-div = <4>; - clock-mult = <1>; - }; - - lcpll0: lcpll0@301d02c { - #clock-cells = <1>; - compatible = "brcm,cygnus-lcpll0"; - reg = <0x0301d02c 0x1c>, <0x0301c020 0x4>; - clocks = <&osc>; - clock-output-names = "lcpll0", "pcie_phy", "ddr_phy", "sdio", - "usb_phy", "smart_card", "ch5"; - }; - - mipipll: mipipll@180a9800 { - #clock-cells = <1>; - compatible = "brcm,cygnus-mipipll"; - reg = <0x180a9800 0x2c>, <0x0301c020 0x4>, <0x180aa024 0x4>; - clocks = <&osc>; - clock-output-names = "mipipll", "ch0_unused", "ch1_lcd", - "ch2_v3d", "ch3_unused", "ch4_unused", - "ch5_unused"; - }; - - asiu_clks: asiu_clks@301d048 { - #clock-cells = <1>; - compatible = "brcm,cygnus-asiu-clk"; - reg = <0x0301d048 0xc>, <0x180aa024 0x4>; - - clocks = <&osc>; - clock-output-names = "keypad", "adc/touch", "pwm"; - }; - - audiopll: audiopll@180aeb00 { - #clock-cells = <1>; - compatible = "brcm,cygnus-audiopll"; - reg = <0x180aeb00 0x68>; - clocks = <&osc>; - clock-output-names = "audiopll", "ch0_audio", - "ch1_audio", "ch2_audio"; - }; -}; diff --git a/sys/gnu/dts/arm/bcm-cygnus.dtsi b/sys/gnu/dts/arm/bcm-cygnus.dtsi deleted file mode 100644 index 1bc45cfd545..00000000000 --- a/sys/gnu/dts/arm/bcm-cygnus.dtsi +++ /dev/null @@ -1,624 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright(c) 2014 Broadcom Corporation. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - compatible = "brcm,cygnus"; - model = "Broadcom Cygnus SoC"; - interrupt-parent = <&gic>; - - aliases { - ethernet0 = ð0; - }; - - memory@0 { - device_type = "memory"; - reg = <0 0>; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - next-level-cache = <&L2>; - reg = <0x0>; - }; - }; - - /include/ "bcm-cygnus-clock.dtsi" - - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts = ; - }; - - core@19000000 { - compatible = "simple-bus"; - ranges = <0x00000000 0x19000000 0x1000000>; - #address-cells = <1>; - #size-cells = <1>; - - timer@20200 { - compatible = "arm,cortex-a9-global-timer"; - reg = <0x20200 0x100>; - interrupts = ; - clocks = <&periph_clk>; - }; - - gic: interrupt-controller@21000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x21000 0x1000>, - <0x20100 0x100>; - }; - - L2: l2-cache@22000 { - compatible = "arm,pl310-cache"; - reg = <0x22000 0x1000>; - cache-unified; - cache-level = <2>; - }; - }; - - axi { - compatible = "simple-bus"; - ranges; - #address-cells = <1>; - #size-cells = <1>; - - otp: otp@301c800 { - compatible = "brcm,ocotp"; - reg = <0x0301c800 0x2c>; - brcm,ocotp-size = <2048>; - status = "disabled"; - }; - - pcie_phy: phy@301d0a0 { - compatible = "brcm,cygnus-pcie-phy"; - reg = <0x0301d0a0 0x14>; - #address-cells = <1>; - #size-cells = <0>; - - pcie0_phy: phy@0 { - reg = <0>; - #phy-cells = <0>; - }; - - pcie1_phy: phy@1 { - reg = <1>; - #phy-cells = <0>; - }; - }; - - pinctrl: pinctrl@301d0c8 { - compatible = "brcm,cygnus-pinmux"; - reg = <0x0301d0c8 0x30>, - <0x0301d24c 0x2c>; - - spi_0: spi_0 { - function = "spi0"; - groups = "spi0_grp"; - }; - - spi_1: spi_1 { - function = "spi1"; - groups = "spi1_grp"; - }; - - spi_2: spi_2 { - function = "spi2"; - groups = "spi2_grp"; - }; - }; - - mailbox: mailbox@3024024 { - compatible = "brcm,iproc-mailbox"; - reg = <0x03024024 0x40>; - interrupts = ; - #interrupt-cells = <1>; - interrupt-controller; - #mbox-cells = <1>; - }; - - gpio_crmu: gpio@3024800 { - compatible = "brcm,cygnus-crmu-gpio"; - reg = <0x03024800 0x50>, - <0x03024008 0x18>; - ngpios = <6>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - interrupt-parent = <&mailbox>; - interrupts = <0>; - }; - - mdio: mdio@18002000 { - compatible = "brcm,iproc-mdio"; - reg = <0x18002000 0x8>; - #size-cells = <0>; - #address-cells = <1>; - status = "disabled"; - - gphy0: ethernet-phy@0 { - reg = <0>; - }; - - gphy1: ethernet-phy@1 { - reg = <1>; - }; - }; - - switch: switch@18007000 { - compatible = "brcm,bcm11360-srab", "brcm,cygnus-srab"; - reg = <0x18007000 0x1000>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - phy-handle = <&gphy0>; - phy-mode = "rgmii"; - }; - - port@1 { - reg = <1>; - phy-handle = <&gphy1>; - phy-mode = "rgmii"; - }; - - port@8 { - reg = <8>; - label = "cpu"; - ethernet = <ð0>; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; - }; - - i2c0: i2c@18008000 { - compatible = "brcm,cygnus-iproc-i2c", "brcm,iproc-i2c"; - reg = <0x18008000 0x100>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clock-frequency = <100000>; - status = "disabled"; - }; - - wdt0: wdt@18009000 { - compatible = "arm,sp805" , "arm,primecell"; - reg = <0x18009000 0x1000>; - interrupts = ; - clocks = <&axi81_clk>; - clock-names = "apb_pclk"; - }; - - gpio_ccm: gpio@1800a000 { - compatible = "brcm,cygnus-ccm-gpio"; - reg = <0x1800a000 0x50>, - <0x0301d164 0x20>; - ngpios = <24>; - #gpio-cells = <2>; - gpio-controller; - interrupts = ; - interrupt-controller; - }; - - i2c1: i2c@1800b000 { - compatible = "brcm,cygnus-iproc-i2c", "brcm,iproc-i2c"; - reg = <0x1800b000 0x100>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clock-frequency = <100000>; - status = "disabled"; - }; - - pcie0: pcie@18012000 { - compatible = "brcm,iproc-pcie"; - reg = <0x18012000 0x1000>; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; - - linux,pci-domain = <0>; - - bus-range = <0x00 0xff>; - - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges = <0x81000000 0 0 0x28000000 0 0x00010000 - 0x82000000 0 0x20000000 0x20000000 0 0x04000000>; - - phys = <&pcie0_phy>; - phy-names = "pcie-phy"; - - status = "disabled"; - - msi-parent = <&msi0>; - msi0: msi-controller { - compatible = "brcm,iproc-msi"; - msi-controller; - interrupt-parent = <&gic>; - interrupts = , - , - , - ; - }; - }; - - pcie1: pcie@18013000 { - compatible = "brcm,iproc-pcie"; - reg = <0x18013000 0x1000>; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; - - linux,pci-domain = <1>; - - bus-range = <0x00 0xff>; - - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges = <0x81000000 0 0 0x48000000 0 0x00010000 - 0x82000000 0 0x40000000 0x40000000 0 0x04000000>; - - phys = <&pcie1_phy>; - phy-names = "pcie-phy"; - - status = "disabled"; - - msi-parent = <&msi1>; - msi1: msi-controller { - compatible = "brcm,iproc-msi"; - msi-controller; - interrupt-parent = <&gic>; - interrupts = , - , - , - ; - }; - }; - - dma0: dma@18018000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x18018000 0x1000>; - interrupts = , - , - , - , - , - , - , - , - ; - clocks = <&apb_clk>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - }; - - uart0: serial@18020000 { - compatible = "snps,dw-apb-uart"; - reg = <0x18020000 0x100>; - reg-shift = <2>; - reg-io-width = <4>; - interrupts = ; - clocks = <&axi81_clk>; - clock-frequency = <100000000>; - status = "disabled"; - }; - - uart1: serial@18021000 { - compatible = "snps,dw-apb-uart"; - reg = <0x18021000 0x100>; - reg-shift = <2>; - reg-io-width = <4>; - interrupts = ; - clocks = <&axi81_clk>; - clock-frequency = <100000000>; - status = "disabled"; - }; - - uart2: serial@18022000 { - compatible = "snps,dw-apb-uart"; - reg = <0x18022000 0x100>; - reg-shift = <2>; - reg-io-width = <4>; - interrupts = ; - clocks = <&axi81_clk>; - clock-frequency = <100000000>; - status = "disabled"; - }; - - uart3: serial@18023000 { - compatible = "snps,dw-apb-uart"; - reg = <0x18023000 0x100>; - reg-shift = <2>; - reg-io-width = <4>; - interrupts = ; - clocks = <&axi81_clk>; - clock-frequency = <100000000>; - status = "disabled"; - }; - - spi0: spi@18028000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x18028000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - pinctrl-0 = <&spi_0>; - clocks = <&axi81_clk>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - spi1: spi@18029000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x18029000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - pinctrl-0 = <&spi_1>; - clocks = <&axi81_clk>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - spi2: spi@1802a000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x1802a000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - pinctrl-0 = <&spi_2>; - clocks = <&axi81_clk>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - rng: rng@18032000 { - compatible = "brcm,iproc-rng200"; - reg = <0x18032000 0x28>; - }; - - sdhci0: sdhci@18041000 { - compatible = "brcm,sdhci-iproc-cygnus"; - reg = <0x18041000 0x100>; - interrupts = ; - clocks = <&lcpll0 BCM_CYGNUS_LCPLL0_SDIO_CLK>; - bus-width = <4>; - sdhci,auto-cmd12; - status = "disabled"; - }; - - eth0: ethernet@18042000 { - compatible = "brcm,amac"; - reg = <0x18042000 0x1000>, - <0x18110000 0x1000>; - reg-names = "amac_base", "idm_base"; - interrupts = ; - status = "disabled"; - }; - - sdhci1: sdhci@18043000 { - compatible = "brcm,sdhci-iproc-cygnus"; - reg = <0x18043000 0x100>; - interrupts = ; - clocks = <&lcpll0 BCM_CYGNUS_LCPLL0_SDIO_CLK>; - bus-width = <4>; - sdhci,auto-cmd12; - status = "disabled"; - }; - - nand: nand@18046000 { - compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1"; - reg = <0x18046000 0x600>, <0xf8105408 0x600>, - <0x18046f00 0x20>; - reg-names = "nand", "iproc-idm", "iproc-ext"; - interrupts = ; - - #address-cells = <1>; - #size-cells = <0>; - - brcm,nand-has-wp; - }; - - ehci0: usb@18048000 { - compatible = "generic-ehci"; - reg = <0x18048000 0x100>; - interrupts = ; - status = "disabled"; - }; - - ohci0: usb@18048800 { - compatible = "generic-ohci"; - reg = <0x18048800 0x100>; - interrupts = ; - status = "disabled"; - }; - - clcd: clcd@180a0000 { - compatible = "arm,pl111", "arm,primecell"; - reg = <0x180a0000 0x1000>; - interrupts = ; - interrupt-names = "combined"; - clocks = <&axi41_clk>, <&apb_clk>; - clock-names = "clcdclk", "apb_pclk"; - status = "disabled"; - }; - - v3d: v3d@180a2000 { - compatible = "brcm,cygnus-v3d"; - reg = <0x180a2000 0x1000>; - clocks = <&mipipll BCM_CYGNUS_MIPIPLL_CH2_V3D>; - clock-names = "v3d_clk"; - interrupts = ; - status = "disabled"; - }; - - vc4: gpu { - compatible = "brcm,cygnus-vc4"; - }; - - gpio_asiu: gpio@180a5000 { - compatible = "brcm,cygnus-asiu-gpio"; - reg = <0x180a5000 0x668>; - ngpios = <146>; - #gpio-cells = <2>; - gpio-controller; - - interrupt-controller; - interrupts = ; - gpio-ranges = <&pinctrl 0 42 1>, - <&pinctrl 1 44 3>, - <&pinctrl 4 48 1>, - <&pinctrl 5 50 3>, - <&pinctrl 8 126 1>, - <&pinctrl 9 155 1>, - <&pinctrl 10 152 1>, - <&pinctrl 11 154 1>, - <&pinctrl 12 153 1>, - <&pinctrl 13 127 3>, - <&pinctrl 16 140 1>, - <&pinctrl 17 145 7>, - <&pinctrl 24 130 10>, - <&pinctrl 34 141 4>, - <&pinctrl 38 54 1>, - <&pinctrl 39 56 3>, - <&pinctrl 42 60 3>, - <&pinctrl 45 64 3>, - <&pinctrl 48 68 2>, - <&pinctrl 50 84 6>, - <&pinctrl 56 94 6>, - <&pinctrl 62 72 1>, - <&pinctrl 63 70 1>, - <&pinctrl 64 80 1>, - <&pinctrl 65 74 3>, - <&pinctrl 68 78 1>, - <&pinctrl 69 82 1>, - <&pinctrl 70 156 17>, - <&pinctrl 87 104 12>, - <&pinctrl 99 102 2>, - <&pinctrl 101 90 4>, - <&pinctrl 105 116 6>, - <&pinctrl 111 100 2>, - <&pinctrl 113 122 4>, - <&pinctrl 123 11 1>, - <&pinctrl 124 38 4>, - <&pinctrl 128 43 1>, - <&pinctrl 129 47 1>, - <&pinctrl 130 49 1>, - <&pinctrl 131 53 1>, - <&pinctrl 132 55 1>, - <&pinctrl 133 59 1>, - <&pinctrl 134 63 1>, - <&pinctrl 135 67 1>, - <&pinctrl 136 71 1>, - <&pinctrl 137 73 1>, - <&pinctrl 138 77 1>, - <&pinctrl 139 79 1>, - <&pinctrl 140 81 1>, - <&pinctrl 141 83 1>, - <&pinctrl 142 10 1>; - }; - - ts_adc_syscon: ts_adc_syscon@180a6000 { - compatible = "brcm,iproc-ts-adc-syscon", "syscon"; - reg = <0x180a6000 0xc30>; - }; - - touchscreen: touchscreen@180a6000 { - compatible = "brcm,iproc-touchscreen"; - #address-cells = <1>; - #size-cells = <1>; - ts_syscon = <&ts_adc_syscon>; - clocks = <&asiu_clks BCM_CYGNUS_ASIU_ADC_CLK>; - clock-names = "tsc_clk"; - interrupts = ; - status = "disabled"; - }; - - adc: adc@180a6000 { - compatible = "brcm,iproc-static-adc"; - #io-channel-cells = <1>; - io-channel-ranges; - adc-syscon = <&ts_adc_syscon>; - clocks = <&asiu_clks BCM_CYGNUS_ASIU_ADC_CLK>; - clock-names = "tsc_clk"; - interrupts = ; - status = "disabled"; - }; - - pwm: pwm@180aa500 { - compatible = "brcm,kona-pwm"; - reg = <0x180aa500 0xc4>; - #pwm-cells = <3>; - clocks = <&asiu_clks BCM_CYGNUS_ASIU_PWM_CLK>; - status = "disabled"; - }; - - keypad: keypad@180ac000 { - compatible = "brcm,bcm-keypad"; - reg = <0x180ac000 0x14c>; - interrupts = ; - clocks = <&asiu_clks BCM_CYGNUS_ASIU_KEYPAD_CLK>; - clock-names = "peri_clk"; - clock-frequency = <31250>; - pull-up-enabled; - col-debounce-filter-period = <0>; - status-debounce-filter-period = <0>; - row-output-enabled; - status = "disabled"; - }; - }; -}; diff --git a/sys/gnu/dts/arm/bcm-hr2.dtsi b/sys/gnu/dts/arm/bcm-hr2.dtsi deleted file mode 100644 index 6142c672811..00000000000 --- a/sys/gnu/dts/arm/bcm-hr2.dtsi +++ /dev/null @@ -1,368 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright(c) 2017 Broadcom. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include - -/ { - compatible = "brcm,hr2"; - model = "Broadcom Hurricane 2 SoC"; - interrupt-parent = <&gic>; - #address-cells = <1>; - #size-cells = <1>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - next-level-cache = <&L2>; - reg = <0x0>; - }; - }; - - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts = ; - interrupt-affinity = <&cpu0>; - }; - - mpcore@19000000 { - compatible = "simple-bus"; - ranges = <0x00000000 0x19000000 0x00023000>; - #address-cells = <1>; - #size-cells = <1>; - - a9pll: arm_clk@0 { - #clock-cells = <0>; - compatible = "brcm,hr2-armpll"; - clocks = <&osc>; - reg = <0x0 0x1000>; - }; - - timer@20200 { - compatible = "arm,cortex-a9-global-timer"; - reg = <0x20200 0x100>; - interrupts = ; - clocks = <&periph_clk>; - }; - - twd-timer@20600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0x20600 0x20>; - interrupts = ; - clocks = <&periph_clk>; - }; - - twd-watchdog@20620 { - compatible = "arm,cortex-a9-twd-wdt"; - reg = <0x20620 0x20>; - interrupts = ; - clocks = <&periph_clk>; - }; - - gic: interrupt-controller@21000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x21000 0x1000>, - <0x20100 0x100>; - }; - - L2: l2-cache@22000 { - compatible = "arm,pl310-cache"; - reg = <0x22000 0x1000>; - cache-unified; - cache-level = <2>; - }; - }; - - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - osc: oscillator { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <25000000>; - }; - - periph_clk: periph_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&a9pll>; - clock-div = <2>; - clock-mult = <1>; - }; - }; - - axi@18000000 { - compatible = "simple-bus"; - ranges = <0x00000000 0x18000000 0x0011c40c>; - #address-cells = <1>; - #size-cells = <1>; - - uart0: serial@300 { - compatible = "ns16550a"; - reg = <0x0300 0x100>; - interrupts = ; - clocks = <&osc>; - status = "disabled"; - }; - - uart1: serial@400 { - compatible = "ns16550a"; - reg = <0x0400 0x100>; - interrupts = ; - clocks = <&osc>; - status = "disabled"; - }; - - dma@20000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x20000 0x1000>; - interrupts = , - , - , - , - , - , - , - , - ; - #dma-cells = <1>; - status = "disabled"; - }; - - amac0: ethernet@22000 { - compatible = "brcm,nsp-amac"; - reg = <0x22000 0x1000>, - <0x110000 0x1000>; - reg-names = "amac_base", "idm_base"; - interrupts = ; - status = "disabled"; - }; - - nand: nand@26000 { - compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1"; - reg = <0x26000 0x600>, - <0x11b408 0x600>, - <0x026f00 0x20>; - reg-names = "nand", "iproc-idm", "iproc-ext"; - interrupts = ; - - #address-cells = <1>; - #size-cells = <0>; - - brcm,nand-has-wp; - }; - - gpiob: gpio@30000 { - compatible = "brcm,iproc-hr2-gpio", "brcm,iproc-gpio"; - reg = <0x30000 0x50>; - #gpio-cells = <2>; - gpio-controller; - ngpios = <4>; - interrupt-controller; - interrupts = ; - }; - - pwm: pwm@31000 { - compatible = "brcm,iproc-pwm"; - reg = <0x31000 0x28>; - clocks = <&osc>; - #pwm-cells = <3>; - status = "disabled"; - }; - - rng: rng@33000 { - compatible = "brcm,bcm-nsp-rng"; - reg = <0x33000 0x14>; - }; - - qspi: spi@27200 { - compatible = "brcm,spi-bcm-qspi", "brcm,spi-nsp-qspi"; - reg = <0x027200 0x184>, - <0x027000 0x124>, - <0x11c408 0x004>, - <0x0273a0 0x01c>; - reg-names = "mspi", "bspi", "intr_regs", - "intr_status_reg"; - interrupts = , - , - , - , - , - , - ; - interrupt-names = "spi_lr_fullness_reached", - "spi_lr_session_aborted", - "spi_lr_impatient", - "spi_lr_session_done", - "spi_lr_overhead", - "mspi_done", - "mspi_halted"; - num-cs = <2>; - #address-cells = <1>; - #size-cells = <0>; - - /* partitions defined in board DTS */ - }; - - ccbtimer0: timer@34000 { - compatible = "arm,sp804"; - reg = <0x34000 0x1000>; - interrupts = , - ; - }; - - ccbtimer1: timer@35000 { - compatible = "arm,sp804"; - reg = <0x35000 0x1000>; - interrupts = , - ; - }; - - i2c0: i2c@38000 { - compatible = "brcm,iproc-i2c"; - reg = <0x38000 0x50>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clock-frequency = <100000>; - }; - - watchdog: watchdog@39000 { - compatible = "arm,sp805", "arm,primecell"; - reg = <0x39000 0x1000>; - interrupts = ; - }; - - i2c1: i2c@3b000 { - compatible = "brcm,iproc-i2c"; - reg = <0x3b000 0x50>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clock-frequency = <100000>; - }; - }; - - pflash: nor@20000000 { - compatible = "cfi-flash", "jedec-flash"; - reg = <0x20000000 0x04000000>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - - /* partitions defined in board DTS */ - }; - - pcie0: pcie@18012000 { - compatible = "brcm,iproc-pcie"; - reg = <0x18012000 0x1000>; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; - - linux,pci-domain = <0>; - - bus-range = <0x00 0xff>; - - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - - /* Note: The HW does not support I/O resources. So, - * only the memory resource range is being specified. - */ - ranges = <0x82000000 0 0x08000000 0x08000000 0 0x8000000>; - - status = "disabled"; - - msi-parent = <&msi0>; - msi0: msi-controller { - compatible = "brcm,iproc-msi"; - msi-controller; - interrupt-parent = <&gic>; - interrupts = , - , - , - ; - brcm,pcie-msi-inten; - }; - }; - - pcie1: pcie@18013000 { - compatible = "brcm,iproc-pcie"; - reg = <0x18013000 0x1000>; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; - - linux,pci-domain = <1>; - - bus-range = <0x00 0xff>; - - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - - /* Note: The HW does not support I/O resources. So, - * only the memory resource range is being specified. - */ - ranges = <0x82000000 0 0x40000000 0x40000000 0 0x8000000>; - - status = "disabled"; - - msi-parent = <&msi1>; - msi1: msi-controller { - compatible = "brcm,iproc-msi"; - msi-controller; - interrupt-parent = <&gic>; - interrupts = , - , - , - ; - brcm,pcie-msi-inten; - }; - }; -}; diff --git a/sys/gnu/dts/arm/bcm-nsp.dtsi b/sys/gnu/dts/arm/bcm-nsp.dtsi deleted file mode 100644 index da6d70f09ef..00000000000 --- a/sys/gnu/dts/arm/bcm-nsp.dtsi +++ /dev/null @@ -1,657 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright(c) 2015 Broadcom Corporation. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - compatible = "brcm,nsp"; - model = "Broadcom Northstar Plus SoC"; - interrupt-parent = <&gic>; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - ethernet0 = &amac0; - ethernet1 = &amac1; - ethernet2 = &amac2; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - next-level-cache = <&L2>; - reg = <0x0>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - next-level-cache = <&L2>; - enable-method = "brcm,bcm-nsp-smp"; - secondary-boot-reg = <0xffff0fec>; - reg = <0x1>; - }; - }; - - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts = ; - interrupt-affinity = <&cpu0>, <&cpu1>; - }; - - mpcore@19000000 { - compatible = "simple-bus"; - ranges = <0x00000000 0x19000000 0x00023000>; - #address-cells = <1>; - #size-cells = <1>; - - a9pll: arm_clk@0 { - #clock-cells = <0>; - compatible = "brcm,nsp-armpll"; - clocks = <&osc>; - reg = <0x00000 0x1000>; - }; - - timer@20200 { - compatible = "arm,cortex-a9-global-timer"; - reg = <0x20200 0x100>; - interrupts = ; - clocks = <&periph_clk>; - }; - - twd-timer@20600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0x20600 0x20>; - interrupts = ; - clocks = <&periph_clk>; - }; - - twd-watchdog@20620 { - compatible = "arm,cortex-a9-twd-wdt"; - reg = <0x20620 0x20>; - interrupts = ; - clocks = <&periph_clk>; - }; - - gic: interrupt-controller@21000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x21000 0x1000>, - <0x20100 0x100>; - }; - - L2: l2-cache@22000 { - compatible = "arm,pl310-cache"; - reg = <0x22000 0x1000>; - cache-unified; - cache-level = <2>; - }; - }; - - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - osc: oscillator { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <25000000>; - }; - - iprocmed: iprocmed { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>; - clock-div = <2>; - clock-mult = <1>; - }; - - iprocslow: iprocslow { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>; - clock-div = <4>; - clock-mult = <1>; - }; - - periph_clk: periph_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&a9pll>; - clock-div = <2>; - clock-mult = <1>; - }; - }; - - axi@18000000 { - compatible = "simple-bus"; - ranges = <0x00000000 0x18000000 0x0011c40c>; - #address-cells = <1>; - #size-cells = <1>; - - gpioa: gpio@20 { - compatible = "brcm,nsp-gpio-a"; - reg = <0x0020 0x70>, - <0x3f1c4 0x1c>; - #gpio-cells = <2>; - gpio-controller; - ngpios = <32>; - interrupt-controller; - interrupts = ; - gpio-ranges = <&pinctrl 0 0 32>; - }; - - uart0: serial@300 { - compatible = "ns16550a"; - reg = <0x0300 0x100>; - interrupts = ; - clocks = <&osc>; - status = "disabled"; - }; - - uart1: serial@400 { - compatible = "ns16550a"; - reg = <0x0400 0x100>; - interrupts = ; - clocks = <&osc>; - status = "disabled"; - }; - - dma@20000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x20000 0x1000>; - interrupts = , - , - , - , - , - , - , - , - ; - clocks = <&iprocslow>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - }; - - sdio: sdhci@21000 { - compatible = "brcm,sdhci-iproc-cygnus"; - reg = <0x21000 0x100>; - interrupts = ; - sdhci,auto-cmd12; - clocks = <&lcpll0 BCM_NSP_LCPLL0_SDIO_CLK>; - dma-coherent; - status = "disabled"; - }; - - amac0: ethernet@22000 { - compatible = "brcm,nsp-amac"; - reg = <0x022000 0x1000>, - <0x110000 0x1000>; - reg-names = "amac_base", "idm_base"; - interrupts = ; - dma-coherent; - status = "disabled"; - }; - - amac1: ethernet@23000 { - compatible = "brcm,nsp-amac"; - reg = <0x023000 0x1000>, - <0x111000 0x1000>; - reg-names = "amac_base", "idm_base"; - interrupts = ; - dma-coherent; - status = "disabled"; - }; - - amac2: ethernet@24000 { - compatible = "brcm,nsp-amac"; - reg = <0x024000 0x1000>, - <0x112000 0x1000>; - reg-names = "amac_base", "idm_base"; - interrupts = ; - dma-coherent; - status = "disabled"; - }; - - mailbox: mailbox@25000 { - compatible = "brcm,iproc-fa2-mbox"; - reg = <0x25000 0x445>; - interrupts = ; - #mbox-cells = <1>; - brcm,rx-status-len = <32>; - brcm,use-bcm-hdr; - dma-coherent; - }; - - nand: nand@26000 { - compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1"; - reg = <0x026000 0x600>, - <0x11b408 0x600>, - <0x026f00 0x20>; - reg-names = "nand", "iproc-idm", "iproc-ext"; - interrupts = ; - - #address-cells = <1>; - #size-cells = <0>; - - brcm,nand-has-wp; - }; - - qspi: spi@27200 { - compatible = "brcm,spi-bcm-qspi", "brcm,spi-nsp-qspi"; - reg = <0x027200 0x184>, - <0x027000 0x124>, - <0x11c408 0x004>, - <0x0273a0 0x01c>; - reg-names = "mspi", "bspi", "intr_regs", - "intr_status_reg"; - interrupts = , - , - , - , - , - , - ; - interrupt-names = "spi_lr_fullness_reached", - "spi_lr_session_aborted", - "spi_lr_impatient", - "spi_lr_session_done", - "spi_lr_overhead", - "mspi_done", - "mspi_halted"; - clocks = <&iprocmed>; - clock-names = "iprocmed"; - num-cs = <2>; - #address-cells = <1>; - #size-cells = <0>; - }; - - xhci: usb@29000 { - compatible = "generic-xhci"; - reg = <0x29000 0x1000>; - interrupts = ; - phys = <&usb3_phy>; - phy-names = "usb3-phy"; - dma-coherent; - status = "disabled"; - }; - - ehci0: usb@2a000 { - compatible = "generic-ehci"; - reg = <0x2a000 0x100>; - interrupts = ; - dma-coherent; - status = "disabled"; - }; - - ohci0: usb@2b000 { - compatible = "generic-ohci"; - reg = <0x2b000 0x100>; - interrupts = ; - dma-coherent; - status = "disabled"; - }; - - crypto@2f000 { - compatible = "brcm,spum-nsp-crypto"; - reg = <0x2f000 0x900>; - mboxes = <&mailbox 0>; - }; - - gpiob: gpio@30000 { - compatible = "brcm,iproc-nsp-gpio", "brcm,iproc-gpio"; - reg = <0x30000 0x50>; - #gpio-cells = <2>; - gpio-controller; - ngpios = <4>; - interrupt-controller; - interrupts = ; - }; - - pwm: pwm@31000 { - compatible = "brcm,iproc-pwm"; - reg = <0x31000 0x28>; - clocks = <&osc>; - #pwm-cells = <3>; - status = "disabled"; - }; - - rng: rng@33000 { - compatible = "brcm,bcm-nsp-rng"; - reg = <0x33000 0x14>; - }; - - ccbtimer0: timer@34000 { - compatible = "arm,sp804"; - reg = <0x34000 0x1000>; - interrupts = , - ; - clocks = <&iprocslow>; - clock-names = "apb_pclk"; - }; - - ccbtimer1: timer@35000 { - compatible = "arm,sp804"; - reg = <0x35000 0x1000>; - interrupts = , - ; - clocks = <&iprocslow>; - clock-names = "apb_pclk"; - }; - - srab: srab@36000 { - compatible = "brcm,nsp-srab"; - reg = <0x36000 0x1000>, - <0x3f308 0x8>, - <0x3f410 0xc>; - reg-names = "srab", "mux_config", "sgmii"; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "link_state_p0", - "link_state_p1", - "link_state_p2", - "link_state_p3", - "link_state_p4", - "link_state_p5", - "link_state_p7", - "link_state_p8", - "phy", - "ts", - "imp_sleep_timer_p5", - "imp_sleep_timer_p7", - "imp_sleep_timer_p8"; - status = "disabled"; - - /* ports are defined in board DTS */ - }; - - i2c0: i2c@38000 { - compatible = "brcm,iproc-i2c"; - reg = <0x38000 0x50>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clock-frequency = <100000>; - dma-coherent; - status = "disabled"; - }; - - watchdog@39000 { - compatible = "arm,sp805", "arm,primecell"; - reg = <0x39000 0x1000>; - interrupts = ; - clocks = <&iprocslow>, <&iprocslow>; - clock-names = "wdogclk", "apb_pclk"; - }; - - lcpll0: lcpll0@3f100 { - #clock-cells = <1>; - compatible = "brcm,nsp-lcpll0"; - reg = <0x3f100 0x14>; - clocks = <&osc>; - clock-output-names = "lcpll0", "pcie_phy", "sdio", - "ddr_phy"; - }; - - genpll: genpll@3f140 { - #clock-cells = <1>; - compatible = "brcm,nsp-genpll"; - reg = <0x3f140 0x24>; - clocks = <&osc>; - clock-output-names = "genpll", "phy", "ethernetclk", - "usbclk", "iprocfast", "sata1", - "sata2"; - }; - - pinctrl: pinctrl@3f1c0 { - compatible = "brcm,nsp-pinmux"; - reg = <0x3f1c0 0x04>, - <0x30028 0x04>, - <0x3f408 0x04>; - }; - - thermal: thermal@3f2c0 { - compatible = "brcm,ns-thermal"; - reg = <0x3f2c0 0x10>; - #thermal-sensor-cells = <0>; - }; - - sata_phy: sata_phy@40100 { - compatible = "brcm,iproc-nsp-sata-phy"; - reg = <0x40100 0x340>; - reg-names = "phy"; - #address-cells = <1>; - #size-cells = <0>; - - sata_phy0: sata-phy@0 { - reg = <0>; - #phy-cells = <0>; - status = "disabled"; - }; - - sata_phy1: sata-phy@1 { - reg = <1>; - #phy-cells = <0>; - status = "disabled"; - }; - }; - - sata: ahci@41000 { - compatible = "brcm,bcm-nsp-ahci"; - reg-names = "ahci", "top-ctrl"; - reg = <0x41000 0x1000>, <0x40020 0x1c>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - dma-coherent; - status = "disabled"; - - sata0: sata-port@0 { - reg = <0>; - phys = <&sata_phy0>; - phy-names = "sata-phy"; - }; - - sata1: sata-port@1 { - reg = <1>; - phys = <&sata_phy1>; - phy-names = "sata-phy"; - }; - }; - - usb3_phy: usb3-phy@104000 { - compatible = "brcm,ns-bx-usb3-phy"; - reg = <0x104000 0x1000>, - <0x032000 0x1000>; - reg-names = "dmp", "ccb-mii"; - #phy-cells = <0>; - status = "disabled"; - }; - }; - - pcie0: pcie@18012000 { - compatible = "brcm,iproc-pcie"; - reg = <0x18012000 0x1000>; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; - - linux,pci-domain = <0>; - - bus-range = <0x00 0xff>; - - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - - /* Note: The HW does not support I/O resources. So, - * only the memory resource range is being specified. - */ - ranges = <0x82000000 0 0x08000000 0x08000000 0 0x8000000>; - - dma-coherent; - status = "disabled"; - - msi-parent = <&msi0>; - msi0: msi-controller { - compatible = "brcm,iproc-msi"; - msi-controller; - interrupt-parent = <&gic>; - interrupts = , - , - , - ; - brcm,pcie-msi-inten; - }; - }; - - pcie1: pcie@18013000 { - compatible = "brcm,iproc-pcie"; - reg = <0x18013000 0x1000>; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; - - linux,pci-domain = <1>; - - bus-range = <0x00 0xff>; - - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - - /* Note: The HW does not support I/O resources. So, - * only the memory resource range is being specified. - */ - ranges = <0x82000000 0 0x40000000 0x40000000 0 0x8000000>; - - dma-coherent; - status = "disabled"; - - msi-parent = <&msi1>; - msi1: msi-controller { - compatible = "brcm,iproc-msi"; - msi-controller; - interrupt-parent = <&gic>; - interrupts = , - , - , - ; - brcm,pcie-msi-inten; - }; - }; - - pcie2: pcie@18014000 { - compatible = "brcm,iproc-pcie"; - reg = <0x18014000 0x1000>; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; - - linux,pci-domain = <2>; - - bus-range = <0x00 0xff>; - - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - - /* Note: The HW does not support I/O resources. So, - * only the memory resource range is being specified. - */ - ranges = <0x82000000 0 0x48000000 0x48000000 0 0x8000000>; - - dma-coherent; - status = "disabled"; - - msi-parent = <&msi2>; - msi2: msi-controller { - compatible = "brcm,iproc-msi"; - msi-controller; - interrupt-parent = <&gic>; - interrupts = , - , - , - ; - brcm,pcie-msi-inten; - }; - }; - - thermal-zones { - cpu-thermal { - polling-delay-passive = <0>; - polling-delay = <1000>; - coefficients = <(-556) 418000>; - thermal-sensors = <&thermal>; - - trips { - cpu-crit { - temperature = <125000>; - hysteresis = <0>; - type = "critical"; - }; - }; - - cooling-maps { - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/bcm11351.dtsi b/sys/gnu/dts/arm/bcm11351.dtsi deleted file mode 100644 index 6197e7d80e3..00000000000 --- a/sys/gnu/dts/arm/bcm11351.dtsi +++ /dev/null @@ -1,424 +0,0 @@ -/* - * Copyright (C) 2012-2013 Broadcom Corporation - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include - -#include "dt-bindings/clock/bcm281xx.h" - -/ { - #address-cells = <1>; - #size-cells = <1>; - model = "BCM11351 SoC"; - compatible = "brcm,bcm11351"; - interrupt-parent = <&gic>; - - chosen { - bootargs = "console=ttyS0,115200n8"; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - enable-method = "brcm,bcm11351-cpu-method"; - secondary-boot-reg = <0x3500417c>; - reg = <1>; - }; - }; - - gic: interrupt-controller@3ff00100 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x3ff01000 0x1000>, - <0x3ff00100 0x100>; - }; - - smc@3404c000 { - compatible = "brcm,bcm11351-smc", "brcm,kona-smc"; - reg = <0x3404c000 0x400>; /* 1 KiB in SRAM */ - }; - - uart@3e000000 { - compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart"; - status = "disabled"; - reg = <0x3e000000 0x1000>; - clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - }; - - uart@3e001000 { - compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart"; - status = "disabled"; - reg = <0x3e001000 0x1000>; - clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB2>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - }; - - uart@3e002000 { - compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart"; - status = "disabled"; - reg = <0x3e002000 0x1000>; - clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB3>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - }; - - uart@3e003000 { - compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart"; - status = "disabled"; - reg = <0x3e003000 0x1000>; - clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB4>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - }; - - L2: l2-cache@3ff20000 { - compatible = "brcm,bcm11351-a2-pl310-cache"; - reg = <0x3ff20000 0x1000>; - cache-unified; - cache-level = <2>; - }; - - watchdog@35002f40 { - compatible = "brcm,bcm11351-wdt", "brcm,kona-wdt"; - reg = <0x35002f40 0x6c>; - }; - - timer@35006000 { - compatible = "brcm,kona-timer"; - reg = <0x35006000 0x1000>; - interrupts = ; - clocks = <&aon_ccu BCM281XX_AON_CCU_HUB_TIMER>; - }; - - gpio: gpio@35003000 { - compatible = "brcm,bcm11351-gpio", "brcm,kona-gpio"; - reg = <0x35003000 0x800>; - interrupts = - ; - #gpio-cells = <2>; - #interrupt-cells = <2>; - gpio-controller; - interrupt-controller; - }; - - sdio1: sdio@3f180000 { - compatible = "brcm,kona-sdhci"; - reg = <0x3f180000 0x10000>; - interrupts = ; - clocks = <&master_ccu BCM281XX_MASTER_CCU_SDIO1>; - status = "disabled"; - }; - - sdio2: sdio@3f190000 { - compatible = "brcm,kona-sdhci"; - reg = <0x3f190000 0x10000>; - interrupts = ; - clocks = <&master_ccu BCM281XX_MASTER_CCU_SDIO2>; - status = "disabled"; - }; - - sdio3: sdio@3f1a0000 { - compatible = "brcm,kona-sdhci"; - reg = <0x3f1a0000 0x10000>; - interrupts = ; - clocks = <&master_ccu BCM281XX_MASTER_CCU_SDIO3>; - status = "disabled"; - }; - - sdio4: sdio@3f1b0000 { - compatible = "brcm,kona-sdhci"; - reg = <0x3f1b0000 0x10000>; - interrupts = ; - clocks = <&master_ccu BCM281XX_MASTER_CCU_SDIO4>; - status = "disabled"; - }; - - pinctrl@35004800 { - compatible = "brcm,bcm11351-pinctrl"; - reg = <0x35004800 0x430>; - }; - - i2c@3e016000 { - compatible = "brcm,bcm11351-i2c", "brcm,kona-i2c"; - reg = <0x3e016000 0x80>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&slave_ccu BCM281XX_SLAVE_CCU_BSC1>; - status = "disabled"; - }; - - i2c@3e017000 { - compatible = "brcm,bcm11351-i2c", "brcm,kona-i2c"; - reg = <0x3e017000 0x80>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&slave_ccu BCM281XX_SLAVE_CCU_BSC2>; - status = "disabled"; - }; - - i2c@3e018000 { - compatible = "brcm,bcm11351-i2c", "brcm,kona-i2c"; - reg = <0x3e018000 0x80>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&slave_ccu BCM281XX_SLAVE_CCU_BSC3>; - status = "disabled"; - }; - - i2c@3500d000 { - compatible = "brcm,bcm11351-i2c", "brcm,kona-i2c"; - reg = <0x3500d000 0x80>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&aon_ccu BCM281XX_AON_CCU_PMU_BSC>; - status = "disabled"; - }; - - pwm: pwm@3e01a000 { - compatible = "brcm,bcm11351-pwm", "brcm,kona-pwm"; - reg = <0x3e01a000 0xcc>; - clocks = <&slave_ccu BCM281XX_SLAVE_CCU_PWM>; - #pwm-cells = <3>; - status = "disabled"; - }; - - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - root_ccu: root_ccu@35001000 { - compatible = "brcm,bcm11351-root-ccu"; - reg = <0x35001000 0x0f00>; - #clock-cells = <1>; - clock-output-names = "frac_1m"; - }; - - hub_ccu: hub_ccu@34000000 { - compatible = "brcm,bcm11351-hub-ccu"; - reg = <0x34000000 0x0f00>; - #clock-cells = <1>; - clock-output-names = "tmon_1m"; - }; - - aon_ccu: aon_ccu@35002000 { - compatible = "brcm,bcm11351-aon-ccu"; - reg = <0x35002000 0x0f00>; - #clock-cells = <1>; - clock-output-names = "hub_timer", - "pmu_bsc", - "pmu_bsc_var"; - }; - - master_ccu: master_ccu@3f001000 { - compatible = "brcm,bcm11351-master-ccu"; - reg = <0x3f001000 0x0f00>; - #clock-cells = <1>; - clock-output-names = "sdio1", - "sdio2", - "sdio3", - "sdio4", - "usb_ic", - "hsic2_48m", - "hsic2_12m"; - }; - - slave_ccu: slave_ccu@3e011000 { - compatible = "brcm,bcm11351-slave-ccu"; - reg = <0x3e011000 0x0f00>; - #clock-cells = <1>; - clock-output-names = "uartb", - "uartb2", - "uartb3", - "uartb4", - "ssp0", - "ssp2", - "bsc1", - "bsc2", - "bsc3", - "pwm"; - }; - - ref_1m_clk: ref_1m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <1000000>; - }; - - ref_32k_clk: ref_32k { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - bbl_32k_clk: bbl_32k { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - ref_13m_clk: ref_13m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <13000000>; - }; - - var_13m_clk: var_13m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <13000000>; - }; - - dft_19_5m_clk: dft_19_5m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <19500000>; - }; - - ref_crystal_clk: ref_crystal { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <26000000>; - }; - - ref_cx40_clk: ref_cx40 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <40000000>; - }; - - ref_52m_clk: ref_52m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <52000000>; - }; - - var_52m_clk: var_52m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <52000000>; - }; - - usb_otg_ahb_clk: usb_otg_ahb { - compatible = "fixed-clock"; - clock-frequency = <52000000>; - #clock-cells = <0>; - }; - - ref_96m_clk: ref_96m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <96000000>; - }; - - var_96m_clk: var_96m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <96000000>; - }; - - ref_104m_clk: ref_104m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <104000000>; - }; - - var_104m_clk: var_104m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <104000000>; - }; - - ref_156m_clk: ref_156m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <156000000>; - }; - - var_156m_clk: var_156m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <156000000>; - }; - - ref_208m_clk: ref_208m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <208000000>; - }; - - var_208m_clk: var_208m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <208000000>; - }; - - ref_312m_clk: ref_312m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <312000000>; - }; - - var_312m_clk: var_312m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <312000000>; - }; - }; - - usbotg: usb@3f120000 { - compatible = "snps,dwc2"; - reg = <0x3f120000 0x10000>; - interrupts = ; - clocks = <&usb_otg_ahb_clk>; - clock-names = "otg"; - phys = <&usbphy>; - phy-names = "usb2-phy"; - status = "disabled"; - }; - - usbphy: usb-phy@3f130000 { - compatible = "brcm,kona-usb2-phy"; - reg = <0x3f130000 0x28>; - #phy-cells = <0>; - status = "disabled"; - }; -}; diff --git a/sys/gnu/dts/arm/bcm21664-garnet.dts b/sys/gnu/dts/arm/bcm21664-garnet.dts deleted file mode 100644 index be468f4adc3..00000000000 --- a/sys/gnu/dts/arm/bcm21664-garnet.dts +++ /dev/null @@ -1,57 +0,0 @@ -/* - * Copyright (C) 2014 Broadcom Corporation - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/dts-v1/; - -#include - -#include "bcm21664.dtsi" - -/ { - model = "BCM21664 Garnet board"; - compatible = "brcm,bcm21664-garnet", "brcm,bcm21664"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x40000000>; /* 1 GB */ - }; - - uart@3e000000 { - status = "okay"; - }; - - sdio1: sdio@3f180000 { - max-frequency = <48000000>; - status = "okay"; - }; - - sdio2: sdio@3f190000 { - non-removable; - max-frequency = <48000000>; - status = "okay"; - }; - - sdio4: sdio@3f1b0000 { - max-frequency = <48000000>; - cd-gpios = <&gpio 91 GPIO_ACTIVE_LOW>; - status = "okay"; - }; - - usbotg: usb@3f120000 { - status = "okay"; - }; - - usbphy: usb-phy@3f130000 { - status = "okay"; - }; -}; diff --git a/sys/gnu/dts/arm/bcm21664.dtsi b/sys/gnu/dts/arm/bcm21664.dtsi deleted file mode 100644 index 3cf66faf3b5..00000000000 --- a/sys/gnu/dts/arm/bcm21664.dtsi +++ /dev/null @@ -1,357 +0,0 @@ -/* - * Copyright (C) 2014 Broadcom Corporation - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include - -#include "dt-bindings/clock/bcm21664.h" - -/ { - #address-cells = <1>; - #size-cells = <1>; - model = "BCM21664 SoC"; - compatible = "brcm,bcm21664"; - interrupt-parent = <&gic>; - - chosen { - bootargs = "console=ttyS0,115200n8"; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - enable-method = "brcm,bcm11351-cpu-method"; - secondary-boot-reg = <0x35004178>; - reg = <1>; - }; - }; - - gic: interrupt-controller@3ff00100 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x3ff01000 0x1000>, - <0x3ff00100 0x100>; - }; - - smc@3404e000 { - compatible = "brcm,bcm21664-smc", "brcm,kona-smc"; - reg = <0x3404e000 0x400>; /* 1 KiB in SRAM */ - }; - - uart@3e000000 { - compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart"; - status = "disabled"; - reg = <0x3e000000 0x118>; - clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - }; - - uart@3e001000 { - compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart"; - status = "disabled"; - reg = <0x3e001000 0x118>; - clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB2>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - }; - - uart@3e002000 { - compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart"; - status = "disabled"; - reg = <0x3e002000 0x118>; - clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB3>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - }; - - L2: l2-cache@3ff20000 { - compatible = "arm,pl310-cache"; - reg = <0x3ff20000 0x1000>; - cache-unified; - cache-level = <2>; - }; - - brcm,resetmgr@35001f00 { - compatible = "brcm,bcm21664-resetmgr"; - reg = <0x35001f00 0x24>; - }; - - timer@35006000 { - compatible = "brcm,kona-timer"; - reg = <0x35006000 0x1c>; - interrupts = ; - clocks = <&aon_ccu BCM21664_AON_CCU_HUB_TIMER>; - }; - - gpio: gpio@35003000 { - compatible = "brcm,bcm21664-gpio", "brcm,kona-gpio"; - reg = <0x35003000 0x524>; - interrupts = - ; - #gpio-cells = <2>; - #interrupt-cells = <2>; - gpio-controller; - interrupt-controller; - }; - - sdio1: sdio@3f180000 { - compatible = "brcm,kona-sdhci"; - reg = <0x3f180000 0x801c>; - interrupts = ; - clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO1>; - status = "disabled"; - }; - - sdio2: sdio@3f190000 { - compatible = "brcm,kona-sdhci"; - reg = <0x3f190000 0x801c>; - interrupts = ; - clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO2>; - status = "disabled"; - }; - - sdio3: sdio@3f1a0000 { - compatible = "brcm,kona-sdhci"; - reg = <0x3f1a0000 0x801c>; - interrupts = ; - clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO3>; - status = "disabled"; - }; - - sdio4: sdio@3f1b0000 { - compatible = "brcm,kona-sdhci"; - reg = <0x3f1b0000 0x801c>; - interrupts = ; - clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO4>; - status = "disabled"; - }; - - i2c@3e016000 { - compatible = "brcm,bcm21664-i2c", "brcm,kona-i2c"; - reg = <0x3e016000 0x70>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC1>; - status = "disabled"; - }; - - i2c@3e017000 { - compatible = "brcm,bcm21664-i2c", "brcm,kona-i2c"; - reg = <0x3e017000 0x70>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC2>; - status = "disabled"; - }; - - i2c@3e018000 { - compatible = "brcm,bcm21664-i2c", "brcm,kona-i2c"; - reg = <0x3e018000 0x70>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC3>; - status = "disabled"; - }; - - i2c@3e01c000 { - compatible = "brcm,bcm21664-i2c", "brcm,kona-i2c"; - reg = <0x3e01c000 0x70>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC4>; - status = "disabled"; - }; - - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - /* - * Fixed clocks are defined before CCUs whose - * clocks may depend on them. - */ - - ref_32k_clk: ref_32k { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - bbl_32k_clk: bbl_32k { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - ref_13m_clk: ref_13m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <13000000>; - }; - - var_13m_clk: var_13m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <13000000>; - }; - - dft_19_5m_clk: dft_19_5m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <19500000>; - }; - - ref_crystal_clk: ref_crystal { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <26000000>; - }; - - ref_52m_clk: ref_52m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <52000000>; - }; - - var_52m_clk: var_52m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <52000000>; - }; - - usb_otg_ahb_clk: usb_otg_ahb { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <52000000>; - }; - - ref_96m_clk: ref_96m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <96000000>; - }; - - var_96m_clk: var_96m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <96000000>; - }; - - ref_104m_clk: ref_104m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <104000000>; - }; - - var_104m_clk: var_104m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <104000000>; - }; - - ref_156m_clk: ref_156m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <156000000>; - }; - - var_156m_clk: var_156m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <156000000>; - }; - - root_ccu: root_ccu@35001000 { - compatible = BCM21664_DT_ROOT_CCU_COMPAT; - reg = <0x35001000 0x0f00>; - #clock-cells = <1>; - clock-output-names = "frac_1m"; - }; - - aon_ccu: aon_ccu@35002000 { - compatible = BCM21664_DT_AON_CCU_COMPAT; - reg = <0x35002000 0x0f00>; - #clock-cells = <1>; - clock-output-names = "hub_timer"; - }; - - master_ccu: master_ccu@3f001000 { - compatible = BCM21664_DT_MASTER_CCU_COMPAT; - reg = <0x3f001000 0x0f00>; - #clock-cells = <1>; - clock-output-names = "sdio1", - "sdio2", - "sdio3", - "sdio4", - "sdio1_sleep", - "sdio2_sleep", - "sdio3_sleep", - "sdio4_sleep"; - }; - - slave_ccu: slave_ccu@3e011000 { - compatible = BCM21664_DT_SLAVE_CCU_COMPAT; - reg = <0x3e011000 0x0f00>; - #clock-cells = <1>; - clock-output-names = "uartb", - "uartb2", - "uartb3", - "bsc1", - "bsc2", - "bsc3", - "bsc4"; - }; - }; - - usbotg: usb@3f120000 { - compatible = "snps,dwc2"; - reg = <0x3f120000 0x10000>; - interrupts = ; - clocks = <&usb_otg_ahb_clk>; - clock-names = "otg"; - phys = <&usbphy>; - phy-names = "usb2-phy"; - status = "disabled"; - }; - - usbphy: usb-phy@3f130000 { - compatible = "brcm,kona-usb2-phy"; - reg = <0x3f130000 0x28>; - #phy-cells = <0>; - status = "disabled"; - }; -}; diff --git a/sys/gnu/dts/arm/bcm23550-sparrow.dts b/sys/gnu/dts/arm/bcm23550-sparrow.dts deleted file mode 100644 index ace77709f46..00000000000 --- a/sys/gnu/dts/arm/bcm23550-sparrow.dts +++ /dev/null @@ -1,81 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright(c) 2016 Broadcom. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/dts-v1/; - -#include - -#include "bcm23550.dtsi" - -/ { - model = "BCM23550 Sparrow board"; - compatible = "brcm,bcm23550-sparrow", "brcm,bcm23550"; - - chosen { - stdout-path = "/slaves@3e000000/serial@0:115200n8"; - bootargs = "console=ttyS0,115200n8"; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000>; /* 512 MB */ - }; -}; - -&uartb { - status = "okay"; -}; - -&usbotg { - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; - -&sdio1 { - max-frequency = <48000000>; - status = "okay"; -}; - -&sdio2 { - non-removable; - max-frequency = <48000000>; - status = "okay"; -}; - -&sdio4 { - max-frequency = <48000000>; - cd-gpios = <&gpio 91 GPIO_ACTIVE_LOW>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/bcm23550.dtsi b/sys/gnu/dts/arm/bcm23550.dtsi deleted file mode 100644 index a36c9b1d23c..00000000000 --- a/sys/gnu/dts/arm/bcm23550.dtsi +++ /dev/null @@ -1,415 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright(c) 2016 Broadcom. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include - -/* BCM23550 and BCM21664 have almost identical clocks */ -#include "dt-bindings/clock/bcm21664.h" - -/ { - #address-cells = <1>; - #size-cells = <1>; - model = "BCM23550 SoC"; - compatible = "brcm,bcm23550"; - interrupt-parent = <&gic>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0>; - clock-frequency = <1000000000>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - enable-method = "brcm,bcm23550"; - secondary-boot-reg = <0x35004178>; - reg = <1>; - clock-frequency = <1000000000>; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - enable-method = "brcm,bcm23550"; - secondary-boot-reg = <0x35004178>; - reg = <2>; - clock-frequency = <1000000000>; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - enable-method = "brcm,bcm23550"; - secondary-boot-reg = <0x35004178>; - reg = <3>; - clock-frequency = <1000000000>; - }; - }; - - /* Hub bus */ - hub@34000000 { - compatible = "simple-bus"; - ranges = <0 0x34000000 0x102f83ac>; - #address-cells = <1>; - #size-cells = <1>; - - smc@4e000 { - compatible = "brcm,bcm23550-smc", "brcm,kona-smc"; - reg = <0x0004e000 0x400>; /* 1 KiB in SRAM */ - }; - - resetmgr: reset-controller@1001f00 { - compatible = "brcm,bcm21664-resetmgr"; - reg = <0x01001f00 0x24>; - }; - - gpio: gpio@1003000 { - compatible = "brcm,bcm23550-gpio", "brcm,kona-gpio"; - reg = <0x01003000 0x524>; - interrupts = - ; - #gpio-cells = <2>; - #interrupt-cells = <2>; - gpio-controller; - interrupt-controller; - }; - - timer@1006000 { - compatible = "brcm,kona-timer"; - reg = <0x01006000 0x1c>; - interrupts = ; - clocks = <&aon_ccu BCM21664_AON_CCU_HUB_TIMER>; - }; - }; - - /* Slaves bus */ - slaves@3e000000 { - compatible = "simple-bus"; - ranges = <0 0x3e000000 0x0001c070>; - #address-cells = <1>; - #size-cells = <1>; - - uartb: serial@0 { - compatible = "snps,dw-apb-uart"; - status = "disabled"; - reg = <0x00000000 0x118>; - clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - }; - - uartb2: serial@1000 { - compatible = "snps,dw-apb-uart"; - status = "disabled"; - reg = <0x00001000 0x118>; - clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB2>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - }; - - uartb3: serial@2000 { - compatible = "snps,dw-apb-uart"; - status = "disabled"; - reg = <0x00002000 0x118>; - clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB3>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - }; - - bsc1: i2c@16000 { - compatible = "brcm,kona-i2c"; - reg = <0x00016000 0x70>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC1>; - status = "disabled"; - }; - - bsc2: i2c@17000 { - compatible = "brcm,kona-i2c"; - reg = <0x00017000 0x70>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC2>; - status = "disabled"; - }; - - bsc3: i2c@18000 { - compatible = "brcm,kona-i2c"; - reg = <0x00018000 0x70>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC3>; - status = "disabled"; - }; - - bsc4: i2c@1c000 { - compatible = "brcm,kona-i2c"; - reg = <0x0001c000 0x70>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC4>; - status = "disabled"; - }; - }; - - /* Apps bus */ - apps@3e300000 { - compatible = "simple-bus"; - ranges = <0 0x3e300000 0x01b77000>; - #address-cells = <1>; - #size-cells = <1>; - - usbotg: usb@e20000 { - compatible = "snps,dwc2"; - reg = <0x00e20000 0x10000>; - interrupts = ; - clocks = <&usb_otg_ahb_clk>; - clock-names = "otg"; - phys = <&usbphy>; - phy-names = "usb2-phy"; - status = "disabled"; - }; - - usbphy: usb-phy@e30000 { - compatible = "brcm,kona-usb2-phy"; - reg = <0x00e30000 0x28>; - #phy-cells = <0>; - status = "disabled"; - }; - - sdio1: sdio@e80000 { - compatible = "brcm,kona-sdhci"; - reg = <0x00e80000 0x801c>; - interrupts = ; - clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO1>; - status = "disabled"; - }; - - sdio2: sdio@e90000 { - compatible = "brcm,kona-sdhci"; - reg = <0x00e90000 0x801c>; - interrupts = ; - clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO2>; - status = "disabled"; - }; - - sdio3: sdio@ea0000 { - compatible = "brcm,kona-sdhci"; - reg = <0x00ea0000 0x801c>; - interrupts = ; - clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO3>; - status = "disabled"; - }; - - sdio4: sdio@eb0000 { - compatible = "brcm,kona-sdhci"; - reg = <0x00eb0000 0x801c>; - interrupts = ; - clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO4>; - status = "disabled"; - }; - - cdc: cdc@1b0e000 { - compatible = "brcm,bcm23550-cdc"; - reg = <0x01b0e000 0x78>; - }; - - gic: interrupt-controller@1b21000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x01b21000 0x1000>, - <0x01b22000 0x1000>; - }; - }; - - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - /* - * Fixed clocks are defined before CCUs whose - * clocks may depend on them. - */ - - ref_32k_clk: ref_32k { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - bbl_32k_clk: bbl_32k { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - ref_13m_clk: ref_13m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <13000000>; - }; - - var_13m_clk: var_13m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <13000000>; - }; - - dft_19_5m_clk: dft_19_5m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <19500000>; - }; - - ref_crystal_clk: ref_crystal { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <26000000>; - }; - - ref_52m_clk: ref_52m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <52000000>; - }; - - var_52m_clk: var_52m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <52000000>; - }; - - usb_otg_ahb_clk: usb_otg_ahb { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <52000000>; - }; - - ref_96m_clk: ref_96m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <96000000>; - }; - - var_96m_clk: var_96m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <96000000>; - }; - - ref_104m_clk: ref_104m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <104000000>; - }; - - var_104m_clk: var_104m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <104000000>; - }; - - ref_156m_clk: ref_156m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <156000000>; - }; - - var_156m_clk: var_156m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <156000000>; - }; - - root_ccu: root_ccu@35001000 { - compatible = BCM21664_DT_ROOT_CCU_COMPAT; - reg = <0x35001000 0x0f00>; - #clock-cells = <1>; - clock-output-names = "frac_1m"; - }; - - aon_ccu: aon_ccu@35002000 { - compatible = BCM21664_DT_AON_CCU_COMPAT; - reg = <0x35002000 0x0f00>; - #clock-cells = <1>; - clock-output-names = "hub_timer"; - }; - - slave_ccu: slave_ccu@3e011000 { - compatible = BCM21664_DT_SLAVE_CCU_COMPAT; - reg = <0x3e011000 0x0f00>; - #clock-cells = <1>; - clock-output-names = "uartb", - "uartb2", - "uartb3", - "bsc1", - "bsc2", - "bsc3", - "bsc4"; - }; - - master_ccu: master_ccu@3f001000 { - compatible = BCM21664_DT_MASTER_CCU_COMPAT; - reg = <0x3f001000 0x0f00>; - #clock-cells = <1>; - clock-output-names = "sdio1", - "sdio2", - "sdio3", - "sdio4", - "sdio1_sleep", - "sdio2_sleep", - "sdio3_sleep", - "sdio4_sleep"; - }; - }; -}; diff --git a/sys/gnu/dts/arm/bcm2711-rpi-4-b.dts b/sys/gnu/dts/arm/bcm2711-rpi-4-b.dts deleted file mode 100644 index efea891b1a7..00000000000 --- a/sys/gnu/dts/arm/bcm2711-rpi-4-b.dts +++ /dev/null @@ -1,143 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; -#include "bcm2711.dtsi" -#include "bcm2835-rpi.dtsi" -#include "bcm283x-rpi-usb-peripheral.dtsi" - -/ { - compatible = "raspberrypi,4-model-b", "brcm,bcm2711"; - model = "Raspberry Pi 4 Model B"; - - chosen { - /* 8250 auxiliary UART instead of pl011 */ - stdout-path = "serial1:115200n8"; - }; - - /* Will be filled by the bootloader */ - memory@0 { - device_type = "memory"; - reg = <0 0 0>; - }; - - aliases { - ethernet0 = &genet; - pcie0 = &pcie0; - }; - - leds { - act { - gpios = <&gpio 42 GPIO_ACTIVE_HIGH>; - }; - - pwr { - label = "PWR"; - gpios = <&expgpio 2 GPIO_ACTIVE_LOW>; - default-state = "keep"; - linux,default-trigger = "default-on"; - }; - }; - - wifi_pwrseq: wifi-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&expgpio 1 GPIO_ACTIVE_LOW>; - }; - - sd_io_1v8_reg: sd_io_1v8_reg { - compatible = "regulator-gpio"; - regulator-name = "vdd-sd-io"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - regulator-settling-time-us = <5000>; - gpios = <&expgpio 4 GPIO_ACTIVE_HIGH>; - states = <1800000 0x1 - 3300000 0x0>; - status = "okay"; - }; -}; - -&firmware { - expgpio: gpio { - compatible = "raspberrypi,firmware-gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio-line-names = "BT_ON", - "WL_ON", - "PWR_LED_OFF", - "GLOBAL_RESET", - "VDD_SD_IO_SEL", - "CAM_GPIO", - "", - ""; - status = "okay"; - }; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pwm1_0_gpio40 &pwm1_1_gpio41>; - status = "okay"; -}; - -/* SDHCI is used to control the SDIO for wireless */ -&sdhci { - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_gpio34>; - bus-width = <4>; - non-removable; - mmc-pwrseq = <&wifi_pwrseq>; - status = "okay"; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - }; -}; - -/* EMMC2 is used to drive the SD card */ -&emmc2 { - vqmmc-supply = <&sd_io_1v8_reg>; - broken-cd; - status = "okay"; -}; - -&genet { - phy-handle = <&phy1>; - phy-mode = "rgmii-rxid"; - status = "okay"; -}; - -&genet_mdio { - phy1: ethernet-phy@1 { - /* No PHY interrupt */ - reg = <0x1>; - }; -}; - -/* uart0 communicates with the BT module */ -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_ctsrts_gpio30 &uart0_gpio32>; - uart-has-rtscts; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - max-speed = <2000000>; - shutdown-gpios = <&expgpio 0 GPIO_ACTIVE_HIGH>; - }; -}; - -/* uart1 is mapped to the pin header */ -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_gpio14>; - status = "okay"; -}; - -&vchiq { - interrupts = ; -}; diff --git a/sys/gnu/dts/arm/bcm2711.dtsi b/sys/gnu/dts/arm/bcm2711.dtsi deleted file mode 100644 index d1e684d0acf..00000000000 --- a/sys/gnu/dts/arm/bcm2711.dtsi +++ /dev/null @@ -1,922 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "bcm283x.dtsi" - -#include -#include - -/ { - compatible = "brcm,bcm2711"; - - #address-cells = <2>; - #size-cells = <1>; - - interrupt-parent = <&gicv2>; - - soc { - /* - * Defined ranges: - * Common BCM283x peripherals - * BCM2711-specific peripherals - * ARM-local peripherals - */ - ranges = <0x7e000000 0x0 0xfe000000 0x01800000>, - <0x7c000000 0x0 0xfc000000 0x02000000>, - <0x40000000 0x0 0xff800000 0x00800000>; - /* Emulate a contiguous 30-bit address range for DMA */ - dma-ranges = <0xc0000000 0x0 0x00000000 0x40000000>; - - /* - * This node is the provider for the enable-method for - * bringing up secondary cores. - */ - local_intc: local_intc@40000000 { - compatible = "brcm,bcm2836-l1-intc"; - reg = <0x40000000 0x100>; - }; - - gicv2: interrupt-controller@40041000 { - interrupt-controller; - #interrupt-cells = <3>; - compatible = "arm,gic-400"; - reg = <0x40041000 0x1000>, - <0x40042000 0x2000>, - <0x40044000 0x2000>, - <0x40046000 0x2000>; - interrupts = ; - }; - - avs_monitor: avs-monitor@7d5d2000 { - compatible = "brcm,bcm2711-avs-monitor", - "syscon", "simple-mfd"; - reg = <0x7d5d2000 0xf00>; - - thermal: thermal { - compatible = "brcm,bcm2711-thermal"; - #thermal-sensor-cells = <0>; - }; - }; - - dma: dma@7e007000 { - compatible = "brcm,bcm2835-dma"; - reg = <0x7e007000 0xb00>; - interrupts = , - , - , - , - , - , - , - /* DMA lite 7 - 10 */ - , - , - , - ; - interrupt-names = "dma0", - "dma1", - "dma2", - "dma3", - "dma4", - "dma5", - "dma6", - "dma7", - "dma8", - "dma9", - "dma10"; - #dma-cells = <1>; - brcm,dma-channel-mask = <0x07f5>; - }; - - pm: watchdog@7e100000 { - compatible = "brcm,bcm2835-pm", "brcm,bcm2835-pm-wdt"; - #power-domain-cells = <1>; - #reset-cells = <1>; - reg = <0x7e100000 0x114>, - <0x7e00a000 0x24>, - <0x7ec11000 0x20>; - clocks = <&clocks BCM2835_CLOCK_V3D>, - <&clocks BCM2835_CLOCK_PERI_IMAGE>, - <&clocks BCM2835_CLOCK_H264>, - <&clocks BCM2835_CLOCK_ISP>; - clock-names = "v3d", "peri_image", "h264", "isp"; - system-power-controller; - }; - - rng@7e104000 { - compatible = "brcm,bcm2711-rng200"; - reg = <0x7e104000 0x28>; - }; - - uart2: serial@7e201400 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x7e201400 0x200>; - interrupts = ; - clocks = <&clocks BCM2835_CLOCK_UART>, - <&clocks BCM2835_CLOCK_VPU>; - clock-names = "uartclk", "apb_pclk"; - arm,primecell-periphid = <0x00241011>; - status = "disabled"; - }; - - uart3: serial@7e201600 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x7e201600 0x200>; - interrupts = ; - clocks = <&clocks BCM2835_CLOCK_UART>, - <&clocks BCM2835_CLOCK_VPU>; - clock-names = "uartclk", "apb_pclk"; - arm,primecell-periphid = <0x00241011>; - status = "disabled"; - }; - - uart4: serial@7e201800 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x7e201800 0x200>; - interrupts = ; - clocks = <&clocks BCM2835_CLOCK_UART>, - <&clocks BCM2835_CLOCK_VPU>; - clock-names = "uartclk", "apb_pclk"; - arm,primecell-periphid = <0x00241011>; - status = "disabled"; - }; - - uart5: serial@7e201a00 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x7e201a00 0x200>; - interrupts = ; - clocks = <&clocks BCM2835_CLOCK_UART>, - <&clocks BCM2835_CLOCK_VPU>; - clock-names = "uartclk", "apb_pclk"; - arm,primecell-periphid = <0x00241011>; - status = "disabled"; - }; - - spi3: spi@7e204600 { - compatible = "brcm,bcm2835-spi"; - reg = <0x7e204600 0x0200>; - interrupts = ; - clocks = <&clocks BCM2835_CLOCK_VPU>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi4: spi@7e204800 { - compatible = "brcm,bcm2835-spi"; - reg = <0x7e204800 0x0200>; - interrupts = ; - clocks = <&clocks BCM2835_CLOCK_VPU>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi5: spi@7e204a00 { - compatible = "brcm,bcm2835-spi"; - reg = <0x7e204a00 0x0200>; - interrupts = ; - clocks = <&clocks BCM2835_CLOCK_VPU>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi6: spi@7e204c00 { - compatible = "brcm,bcm2835-spi"; - reg = <0x7e204c00 0x0200>; - interrupts = ; - clocks = <&clocks BCM2835_CLOCK_VPU>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c3: i2c@7e205600 { - compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; - reg = <0x7e205600 0x200>; - interrupts = ; - clocks = <&clocks BCM2835_CLOCK_VPU>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c4: i2c@7e205800 { - compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; - reg = <0x7e205800 0x200>; - interrupts = ; - clocks = <&clocks BCM2835_CLOCK_VPU>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c5: i2c@7e205a00 { - compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; - reg = <0x7e205a00 0x200>; - interrupts = ; - clocks = <&clocks BCM2835_CLOCK_VPU>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c6: i2c@7e205c00 { - compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; - reg = <0x7e205c00 0x200>; - interrupts = ; - clocks = <&clocks BCM2835_CLOCK_VPU>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - pwm1: pwm@7e20c800 { - compatible = "brcm,bcm2835-pwm"; - reg = <0x7e20c800 0x28>; - clocks = <&clocks BCM2835_CLOCK_PWM>; - assigned-clocks = <&clocks BCM2835_CLOCK_PWM>; - assigned-clock-rates = <10000000>; - #pwm-cells = <2>; - status = "disabled"; - }; - - emmc2: emmc2@7e340000 { - compatible = "brcm,bcm2711-emmc2"; - reg = <0x7e340000 0x100>; - interrupts = ; - clocks = <&clocks BCM2711_CLOCK_EMMC2>; - status = "disabled"; - }; - - hvs@7e400000 { - interrupts = ; - }; - }; - - arm-pmu { - compatible = "arm,cortex-a72-pmu", "arm,armv8-pmuv3"; - interrupts = , - , - , - ; - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - /* This only applies to the ARMv7 stub */ - arm,cpu-registers-not-fw-configured; - }; - - cpus: cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0>; - enable-method = "spin-table"; - cpu-release-addr = <0x0 0x000000d8>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <1>; - enable-method = "spin-table"; - cpu-release-addr = <0x0 0x000000e0>; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <2>; - enable-method = "spin-table"; - cpu-release-addr = <0x0 0x000000e8>; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <3>; - enable-method = "spin-table"; - cpu-release-addr = <0x0 0x000000f0>; - }; - }; - - scb { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <1>; - - ranges = <0x0 0x7c000000 0x0 0xfc000000 0x03800000>, - <0x6 0x00000000 0x6 0x00000000 0x40000000>; - - pcie0: pcie@7d500000 { - compatible = "brcm,bcm2711-pcie"; - reg = <0x0 0x7d500000 0x9310>; - device_type = "pci"; - #address-cells = <3>; - #interrupt-cells = <1>; - #size-cells = <2>; - interrupts = , - ; - interrupt-names = "pcie", "msi"; - interrupt-map-mask = <0x0 0x0 0x0 0x7>; - interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143 - IRQ_TYPE_LEVEL_HIGH>; - msi-controller; - msi-parent = <&pcie0>; - - ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000 - 0x0 0x04000000>; - /* - * The wrapper around the PCIe block has a bug - * preventing it from accessing beyond the first 3GB of - * memory. - */ - dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000 - 0x0 0xc0000000>; - brcm,enable-ssc; - }; - - genet: ethernet@7d580000 { - compatible = "brcm,bcm2711-genet-v5"; - reg = <0x0 0x7d580000 0x10000>; - #address-cells = <0x1>; - #size-cells = <0x1>; - interrupts = , - ; - status = "disabled"; - - genet_mdio: mdio@e14 { - compatible = "brcm,genet-mdio-v5"; - reg = <0xe14 0x8>; - reg-names = "mdio"; - #address-cells = <0x0>; - #size-cells = <0x1>; - }; - }; - }; -}; - -&clk_osc { - clock-frequency = <54000000>; -}; - -&clocks { - compatible = "brcm,bcm2711-cprman"; -}; - -&cpu_thermal { - coefficients = <(-487) 410040>; - thermal-sensors = <&thermal>; -}; - -&dsi0 { - interrupts = ; -}; - -&dsi1 { - interrupts = ; -}; - -&gpio { - compatible = "brcm,bcm2711-gpio"; - interrupts = , - , - , - ; - - gpclk0_gpio49: gpclk0_gpio49 { - pin-gpclk { - pins = "gpio49"; - function = "alt1"; - bias-disable; - }; - }; - gpclk1_gpio50: gpclk1_gpio50 { - pin-gpclk { - pins = "gpio50"; - function = "alt1"; - bias-disable; - }; - }; - gpclk2_gpio51: gpclk2_gpio51 { - pin-gpclk { - pins = "gpio51"; - function = "alt1"; - bias-disable; - }; - }; - - i2c0_gpio46: i2c0_gpio46 { - pin-sda { - function = "alt0"; - pins = "gpio46"; - bias-pull-up; - }; - pin-scl { - function = "alt0"; - pins = "gpio47"; - bias-disable; - }; - }; - i2c1_gpio46: i2c1_gpio46 { - pin-sda { - function = "alt1"; - pins = "gpio46"; - bias-pull-up; - }; - pin-scl { - function = "alt1"; - pins = "gpio47"; - bias-disable; - }; - }; - i2c3_gpio2: i2c3_gpio2 { - pin-sda { - function = "alt5"; - pins = "gpio2"; - bias-pull-up; - }; - pin-scl { - function = "alt5"; - pins = "gpio3"; - bias-disable; - }; - }; - i2c3_gpio4: i2c3_gpio4 { - pin-sda { - function = "alt5"; - pins = "gpio4"; - bias-pull-up; - }; - pin-scl { - function = "alt5"; - pins = "gpio5"; - bias-disable; - }; - }; - i2c4_gpio6: i2c4_gpio6 { - pin-sda { - function = "alt5"; - pins = "gpio6"; - bias-pull-up; - }; - pin-scl { - function = "alt5"; - pins = "gpio7"; - bias-disable; - }; - }; - i2c4_gpio8: i2c4_gpio8 { - pin-sda { - function = "alt5"; - pins = "gpio8"; - bias-pull-up; - }; - pin-scl { - function = "alt5"; - pins = "gpio9"; - bias-disable; - }; - }; - i2c5_gpio10: i2c5_gpio10 { - pin-sda { - function = "alt5"; - pins = "gpio10"; - bias-pull-up; - }; - pin-scl { - function = "alt5"; - pins = "gpio11"; - bias-disable; - }; - }; - i2c5_gpio12: i2c5_gpio12 { - pin-sda { - function = "alt5"; - pins = "gpio12"; - bias-pull-up; - }; - pin-scl { - function = "alt5"; - pins = "gpio13"; - bias-disable; - }; - }; - i2c6_gpio0: i2c6_gpio0 { - pin-sda { - function = "alt5"; - pins = "gpio0"; - bias-pull-up; - }; - pin-scl { - function = "alt5"; - pins = "gpio1"; - bias-disable; - }; - }; - i2c6_gpio22: i2c6_gpio22 { - pin-sda { - function = "alt5"; - pins = "gpio22"; - bias-pull-up; - }; - pin-scl { - function = "alt5"; - pins = "gpio23"; - bias-disable; - }; - }; - i2c_slave_gpio8: i2c_slave_gpio8 { - pins-i2c-slave { - pins = "gpio8", - "gpio9", - "gpio10", - "gpio11"; - function = "alt3"; - }; - }; - - jtag_gpio48: jtag_gpio48 { - pins-jtag { - pins = "gpio48", - "gpio49", - "gpio50", - "gpio51", - "gpio52", - "gpio53"; - function = "alt4"; - }; - }; - - mii_gpio28: mii_gpio28 { - pins-mii { - pins = "gpio28", - "gpio29", - "gpio30", - "gpio31"; - function = "alt4"; - }; - }; - mii_gpio36: mii_gpio36 { - pins-mii { - pins = "gpio36", - "gpio37", - "gpio38", - "gpio39"; - function = "alt5"; - }; - }; - - pcm_gpio50: pcm_gpio50 { - pins-pcm { - pins = "gpio50", - "gpio51", - "gpio52", - "gpio53"; - function = "alt2"; - }; - }; - - pwm0_0_gpio12: pwm0_0_gpio12 { - pin-pwm { - pins = "gpio12"; - function = "alt0"; - bias-disable; - }; - }; - pwm0_0_gpio18: pwm0_0_gpio18 { - pin-pwm { - pins = "gpio18"; - function = "alt5"; - bias-disable; - }; - }; - pwm1_0_gpio40: pwm1_0_gpio40 { - pin-pwm { - pins = "gpio40"; - function = "alt0"; - bias-disable; - }; - }; - pwm0_1_gpio13: pwm0_1_gpio13 { - pin-pwm { - pins = "gpio13"; - function = "alt0"; - bias-disable; - }; - }; - pwm0_1_gpio19: pwm0_1_gpio19 { - pin-pwm { - pins = "gpio19"; - function = "alt5"; - bias-disable; - }; - }; - pwm1_1_gpio41: pwm1_1_gpio41 { - pin-pwm { - pins = "gpio41"; - function = "alt0"; - bias-disable; - }; - }; - pwm0_1_gpio45: pwm0_1_gpio45 { - pin-pwm { - pins = "gpio45"; - function = "alt0"; - bias-disable; - }; - }; - pwm0_0_gpio52: pwm0_0_gpio52 { - pin-pwm { - pins = "gpio52"; - function = "alt1"; - bias-disable; - }; - }; - pwm0_1_gpio53: pwm0_1_gpio53 { - pin-pwm { - pins = "gpio53"; - function = "alt1"; - bias-disable; - }; - }; - - rgmii_gpio35: rgmii_gpio35 { - pin-start-stop { - pins = "gpio35"; - function = "alt4"; - }; - pin-rx-ok { - pins = "gpio36"; - function = "alt4"; - }; - }; - rgmii_irq_gpio34: rgmii_irq_gpio34 { - pin-irq { - pins = "gpio34"; - function = "alt5"; - }; - }; - rgmii_irq_gpio39: rgmii_irq_gpio39 { - pin-irq { - pins = "gpio39"; - function = "alt4"; - }; - }; - rgmii_mdio_gpio28: rgmii_mdio_gpio28 { - pins-mdio { - pins = "gpio28", - "gpio29"; - function = "alt5"; - }; - }; - rgmii_mdio_gpio37: rgmii_mdio_gpio37 { - pins-mdio { - pins = "gpio37", - "gpio38"; - function = "alt4"; - }; - }; - - spi0_gpio46: spi0_gpio46 { - pins-spi { - pins = "gpio46", - "gpio47", - "gpio48", - "gpio49"; - function = "alt2"; - }; - }; - spi2_gpio46: spi2_gpio46 { - pins-spi { - pins = "gpio46", - "gpio47", - "gpio48", - "gpio49", - "gpio50"; - function = "alt5"; - }; - }; - spi3_gpio0: spi3_gpio0 { - pins-spi { - pins = "gpio0", - "gpio1", - "gpio2", - "gpio3"; - function = "alt3"; - }; - }; - spi4_gpio4: spi4_gpio4 { - pins-spi { - pins = "gpio4", - "gpio5", - "gpio6", - "gpio7"; - function = "alt3"; - }; - }; - spi5_gpio12: spi5_gpio12 { - pins-spi { - pins = "gpio12", - "gpio13", - "gpio14", - "gpio15"; - function = "alt3"; - }; - }; - spi6_gpio18: spi6_gpio18 { - pins-spi { - pins = "gpio18", - "gpio19", - "gpio20", - "gpio21"; - function = "alt3"; - }; - }; - - uart2_gpio0: uart2_gpio0 { - pin-tx { - pins = "gpio0"; - function = "alt4"; - bias-disable; - }; - pin-rx { - pins = "gpio1"; - function = "alt4"; - bias-pull-up; - }; - }; - uart2_ctsrts_gpio2: uart2_ctsrts_gpio2 { - pin-cts { - pins = "gpio2"; - function = "alt4"; - bias-pull-up; - }; - pin-rts { - pins = "gpio3"; - function = "alt4"; - bias-disable; - }; - }; - uart3_gpio4: uart3_gpio4 { - pin-tx { - pins = "gpio4"; - function = "alt4"; - bias-disable; - }; - pin-rx { - pins = "gpio5"; - function = "alt4"; - bias-pull-up; - }; - }; - uart3_ctsrts_gpio6: uart3_ctsrts_gpio6 { - pin-cts { - pins = "gpio6"; - function = "alt4"; - bias-pull-up; - }; - pin-rts { - pins = "gpio7"; - function = "alt4"; - bias-disable; - }; - }; - uart4_gpio8: uart4_gpio8 { - pin-tx { - pins = "gpio8"; - function = "alt4"; - bias-disable; - }; - pin-rx { - pins = "gpio9"; - function = "alt4"; - bias-pull-up; - }; - }; - uart4_ctsrts_gpio10: uart4_ctsrts_gpio10 { - pin-cts { - pins = "gpio10"; - function = "alt4"; - bias-pull-up; - }; - pin-rts { - pins = "gpio11"; - function = "alt4"; - bias-disable; - }; - }; - uart5_gpio12: uart5_gpio12 { - pin-tx { - pins = "gpio12"; - function = "alt4"; - bias-disable; - }; - pin-rx { - pins = "gpio13"; - function = "alt4"; - bias-pull-up; - }; - }; - uart5_ctsrts_gpio14: uart5_ctsrts_gpio14 { - pin-cts { - pins = "gpio14"; - function = "alt4"; - bias-pull-up; - }; - pin-rts { - pins = "gpio15"; - function = "alt4"; - bias-disable; - }; - }; -}; - -&rmem { - #address-cells = <2>; -}; - -&cma { - /* - * arm64 reserves the CMA by default somewhere in ZONE_DMA32, - * that's not good enough for the BCM2711 as some devices can - * only address the lower 1G of memory (ZONE_DMA). - */ - alloc-ranges = <0x0 0x00000000 0x40000000>; -}; - -&i2c0 { - compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; - interrupts = ; -}; - -&i2c1 { - compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; - interrupts = ; -}; - -&mailbox { - interrupts = ; -}; - -&sdhci { - interrupts = ; -}; - -&sdhost { - interrupts = ; -}; - -&spi { - interrupts = ; -}; - -&spi1 { - interrupts = ; -}; - -&spi2 { - interrupts = ; -}; - -&system_timer { - interrupts = , - , - , - ; -}; - -&txp { - interrupts = ; -}; - -&uart0 { - interrupts = ; -}; - -&uart1 { - interrupts = ; -}; - -&usb { - interrupts = ; -}; - -&vec { - interrupts = ; -}; diff --git a/sys/gnu/dts/arm/bcm28155-ap.dts b/sys/gnu/dts/arm/bcm28155-ap.dts deleted file mode 100644 index ead6e9804db..00000000000 --- a/sys/gnu/dts/arm/bcm28155-ap.dts +++ /dev/null @@ -1,122 +0,0 @@ -/* - * Copyright (C) 2013 Broadcom Corporation - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/dts-v1/; - -#include - -#include "bcm11351.dtsi" - -/ { - model = "BCM28155 AP board"; - compatible = "brcm,bcm28155-ap", "brcm,bcm11351"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x40000000>; /* 1 GB */ - }; - - uart@3e000000 { - status = "okay"; - }; - - i2c@3e016000 { - status="okay"; - clock-frequency = <400000>; - }; - - i2c@3e017000 { - status="okay"; - clock-frequency = <400000>; - }; - - i2c@3e018000 { - status="okay"; - clock-frequency = <400000>; - }; - - i2c@3500d000 { - status="okay"; - clock-frequency = <100000>; - - pmu: pmu@8 { - reg = <0x08>; - }; - }; - - sdio2: sdio@3f190000 { - non-removable; - max-frequency = <48000000>; - vmmc-supply = <&camldo1_reg>; - vqmmc-supply = <&iosr1_reg>; - status = "okay"; - }; - - sdio4: sdio@3f1b0000 { - max-frequency = <48000000>; - cd-gpios = <&gpio 14 GPIO_ACTIVE_LOW>; - vmmc-supply = <&sdldo_reg>; - vqmmc-supply = <&sdxldo_reg>; - status = "okay"; - }; - - pwm: pwm@3e01a000 { - status = "okay"; - }; - - usbotg: usb@3f120000 { - vusb_d-supply = <&usbldo_reg>; - vusb_a-supply = <&iosr1_reg>; - status = "okay"; - }; - - usbphy: usb-phy@3f130000 { - status = "okay"; - }; -}; - -#include "bcm59056.dtsi" - -&pmu { - compatible = "brcm,bcm59056"; - interrupts = ; - regulators { - camldo1_reg: camldo1 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - sdldo_reg: sdldo { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - sdxldo_reg: sdxldo { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <3300000>; - }; - - usbldo_reg: usbldo { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - iosr1_reg: iosr1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - }; -}; diff --git a/sys/gnu/dts/arm/bcm2835-common.dtsi b/sys/gnu/dts/arm/bcm2835-common.dtsi deleted file mode 100644 index 2b1d9d4c0cd..00000000000 --- a/sys/gnu/dts/arm/bcm2835-common.dtsi +++ /dev/null @@ -1,200 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -/* This include file covers the common peripherals and configuration between - * bcm2835, bcm2836 and bcm2837 implementations. - */ - -/ { - interrupt-parent = <&intc>; - - soc { - dma: dma@7e007000 { - compatible = "brcm,bcm2835-dma"; - reg = <0x7e007000 0xf00>; - interrupts = <1 16>, - <1 17>, - <1 18>, - <1 19>, - <1 20>, - <1 21>, - <1 22>, - <1 23>, - <1 24>, - <1 25>, - <1 26>, - /* dma channel 11-14 share one irq */ - <1 27>, - <1 27>, - <1 27>, - <1 27>, - /* unused shared irq for all channels */ - <1 28>; - interrupt-names = "dma0", - "dma1", - "dma2", - "dma3", - "dma4", - "dma5", - "dma6", - "dma7", - "dma8", - "dma9", - "dma10", - "dma11", - "dma12", - "dma13", - "dma14", - "dma-shared-all"; - #dma-cells = <1>; - brcm,dma-channel-mask = <0x7f35>; - }; - - intc: interrupt-controller@7e00b200 { - compatible = "brcm,bcm2835-armctrl-ic"; - reg = <0x7e00b200 0x200>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - pm: watchdog@7e100000 { - compatible = "brcm,bcm2835-pm", "brcm,bcm2835-pm-wdt"; - #power-domain-cells = <1>; - #reset-cells = <1>; - reg = <0x7e100000 0x114>, - <0x7e00a000 0x24>; - clocks = <&clocks BCM2835_CLOCK_V3D>, - <&clocks BCM2835_CLOCK_PERI_IMAGE>, - <&clocks BCM2835_CLOCK_H264>, - <&clocks BCM2835_CLOCK_ISP>; - clock-names = "v3d", "peri_image", "h264", "isp"; - system-power-controller; - }; - - rng@7e104000 { - compatible = "brcm,bcm2835-rng"; - reg = <0x7e104000 0x10>; - interrupts = <2 29>; - }; - - pixelvalve@7e206000 { - compatible = "brcm,bcm2835-pixelvalve0"; - reg = <0x7e206000 0x100>; - interrupts = <2 13>; /* pwa0 */ - }; - - pixelvalve@7e207000 { - compatible = "brcm,bcm2835-pixelvalve1"; - reg = <0x7e207000 0x100>; - interrupts = <2 14>; /* pwa1 */ - }; - - thermal: thermal@7e212000 { - compatible = "brcm,bcm2835-thermal"; - reg = <0x7e212000 0x8>; - clocks = <&clocks BCM2835_CLOCK_TSENS>; - #thermal-sensor-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@7e805000 { - compatible = "brcm,bcm2835-i2c"; - reg = <0x7e805000 0x1000>; - interrupts = <2 21>; - clocks = <&clocks BCM2835_CLOCK_VPU>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - }; - - pixelvalve@7e807000 { - compatible = "brcm,bcm2835-pixelvalve2"; - reg = <0x7e807000 0x100>; - interrupts = <2 10>; /* pixelvalve */ - }; - - hdmi: hdmi@7e902000 { - compatible = "brcm,bcm2835-hdmi"; - reg = <0x7e902000 0x600>, - <0x7e808000 0x100>; - interrupts = <2 8>, <2 9>; - ddc = <&i2c2>; - clocks = <&clocks BCM2835_PLLH_PIX>, - <&clocks BCM2835_CLOCK_HSM>; - clock-names = "pixel", "hdmi"; - dmas = <&dma 17>; - dma-names = "audio-rx"; - status = "disabled"; - }; - - v3d: v3d@7ec00000 { - compatible = "brcm,bcm2835-v3d"; - reg = <0x7ec00000 0x1000>; - interrupts = <1 10>; - power-domains = <&pm BCM2835_POWER_DOMAIN_GRAFX_V3D>; - }; - - vc4: gpu { - compatible = "brcm,bcm2835-vc4"; - }; - }; -}; - -&cpu_thermal { - thermal-sensors = <&thermal>; -}; - -&gpio { - i2c_slave_gpio18: i2c_slave_gpio18 { - brcm,pins = <18 19 20 21>; - brcm,function = ; - }; - - jtag_gpio4: jtag_gpio4 { - brcm,pins = <4 5 6 12 13>; - brcm,function = ; - }; - - pwm0_gpio12: pwm0_gpio12 { - brcm,pins = <12>; - brcm,function = ; - }; - pwm0_gpio18: pwm0_gpio18 { - brcm,pins = <18>; - brcm,function = ; - }; - pwm0_gpio40: pwm0_gpio40 { - brcm,pins = <40>; - brcm,function = ; - }; - pwm1_gpio13: pwm1_gpio13 { - brcm,pins = <13>; - brcm,function = ; - }; - pwm1_gpio19: pwm1_gpio19 { - brcm,pins = <19>; - brcm,function = ; - }; - pwm1_gpio41: pwm1_gpio41 { - brcm,pins = <41>; - brcm,function = ; - }; - pwm1_gpio45: pwm1_gpio45 { - brcm,pins = <45>; - brcm,function = ; - }; -}; - -&i2s { - dmas = <&dma 2>, <&dma 3>; - dma-names = "tx", "rx"; -}; - -&sdhost { - dmas = <&dma 13>; - dma-names = "rx-tx"; -}; - -&spi { - dmas = <&dma 6>, <&dma 7>; - dma-names = "tx", "rx"; -}; diff --git a/sys/gnu/dts/arm/bcm2835-rpi-a-plus.dts b/sys/gnu/dts/arm/bcm2835-rpi-a-plus.dts deleted file mode 100644 index 6c8ce39833b..00000000000 --- a/sys/gnu/dts/arm/bcm2835-rpi-a-plus.dts +++ /dev/null @@ -1,128 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; -#include "bcm2835.dtsi" -#include "bcm2835-rpi.dtsi" -#include "bcm283x-rpi-usb-host.dtsi" - -/ { - compatible = "raspberrypi,model-a-plus", "brcm,bcm2835"; - model = "Raspberry Pi Model A+"; - - memory@0 { - device_type = "memory"; - reg = <0 0x10000000>; - }; - - leds { - act { - gpios = <&gpio 47 GPIO_ACTIVE_HIGH>; - }; - - pwr { - label = "PWR"; - gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - linux,default-trigger = "default-on"; - }; - }; -}; - -&gpio { - /* - * This is based on the unreleased schematic for the Model A+. - * - * Legend: - * "NC" = not connected (no rail from the SoC) - * "FOO" = GPIO line named "FOO" on the schematic - * "FOO_N" = GPIO line named "FOO" on schematic, active low - */ - gpio-line-names = "ID_SDA", - "ID_SCL", - "SDA1", - "SCL1", - "GPIO_GCLK", - "GPIO5", - "GPIO6", - "SPI_CE1_N", - "SPI_CE0_N", - "SPI_MISO", - "SPI_MOSI", - "SPI_SCLK", - "GPIO12", - "GPIO13", - /* Serial port */ - "TXD0", - "RXD0", - "GPIO16", - "GPIO17", - "GPIO18", - "GPIO19", - "GPIO20", - "GPIO21", - "GPIO22", - "GPIO23", - "GPIO24", - "GPIO25", - "GPIO26", - "GPIO27", - "SDA0", - "SCL0", - "NC", /* GPIO30 */ - "NC", /* GPIO31 */ - "CAM_GPIO1", /* GPIO32 */ - "NC", /* GPIO33 */ - "NC", /* GPIO34 */ - "PWR_LOW_N", /* GPIO35 */ - "NC", /* GPIO36 */ - "NC", /* GPIO37 */ - "USB_LIMIT", /* GPIO38 */ - "NC", /* GPIO39 */ - "PWM0_OUT", /* GPIO40 */ - "CAM_GPIO0", /* GPIO41 */ - "NC", /* GPIO42 */ - "NC", /* GPIO43 */ - "NC", /* GPIO44 */ - "PWM1_OUT", /* GPIO45 */ - "HDMI_HPD_N", - "STATUS_LED", - /* Used by SD Card */ - "SD_CLK_R", - "SD_CMD_R", - "SD_DATA0_R", - "SD_DATA1_R", - "SD_DATA2_R", - "SD_DATA3_R"; - - pinctrl-0 = <&gpioout &alt0 &i2s_alt0>; - - /* I2S interface */ - i2s_alt0: i2s_alt0 { - brcm,pins = <18 19 20 21>; - brcm,function = ; - }; -}; - -&hdmi { - hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>; - power-domains = <&power RPI_POWER_DOMAIN_HDMI>; - status = "okay"; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio45>; - status = "okay"; -}; - -&sdhost { - pinctrl-names = "default"; - pinctrl-0 = <&sdhost_gpio48>; - bus-width = <4>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_gpio14>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/bcm2835-rpi-a.dts b/sys/gnu/dts/arm/bcm2835-rpi-a.dts deleted file mode 100644 index 17fdd48346f..00000000000 --- a/sys/gnu/dts/arm/bcm2835-rpi-a.dts +++ /dev/null @@ -1,123 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; -#include "bcm2835.dtsi" -#include "bcm2835-rpi.dtsi" -#include "bcm283x-rpi-usb-host.dtsi" - -/ { - compatible = "raspberrypi,model-a", "brcm,bcm2835"; - model = "Raspberry Pi Model A"; - - memory@0 { - device_type = "memory"; - reg = <0 0x10000000>; - }; - - leds { - act { - gpios = <&gpio 16 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&gpio { - /* - * Taken from Raspberry-Pi-Rev-1.0-Model-AB-Schematics.pdf - * RPI00021 sheet 02 - * - * Legend: - * "NC" = not connected (no rail from the SoC) - * "FOO" = GPIO line named "FOO" on the schematic - * "FOO_N" = GPIO line named "FOO" on schematic, active low - */ - gpio-line-names = "SDA0", - "SCL0", - "SDA1", - "SCL1", - "GPIO_GCLK", - "CAM_GPIO1", - "LAN_RUN", - "SPI_CE1_N", - "SPI_CE0_N", - "SPI_MISO", - "SPI_MOSI", - "SPI_SCLK", - "NC", /* GPIO12 */ - "NC", /* GPIO13 */ - /* Serial port */ - "TXD0", - "RXD0", - "STATUS_LED_N", - "GPIO17", - "GPIO18", - "NC", /* GPIO19 */ - "NC", /* GPIO20 */ - "GPIO21", - "GPIO22", - "GPIO23", - "GPIO24", - "GPIO25", - "NC", /* GPIO26 */ - "CAM_GPIO0", - /* Binary number representing build/revision */ - "CONFIG0", - "CONFIG1", - "CONFIG2", - "CONFIG3", - "NC", /* GPIO32 */ - "NC", /* GPIO33 */ - "NC", /* GPIO34 */ - "NC", /* GPIO35 */ - "NC", /* GPIO36 */ - "NC", /* GPIO37 */ - "NC", /* GPIO38 */ - "NC", /* GPIO39 */ - "PWM0_OUT", - "NC", /* GPIO41 */ - "NC", /* GPIO42 */ - "NC", /* GPIO43 */ - "NC", /* GPIO44 */ - "PWM1_OUT", - "HDMI_HPD_P", - "SD_CARD_DET", - /* Used by SD Card */ - "SD_CLK_R", - "SD_CMD_R", - "SD_DATA0_R", - "SD_DATA1_R", - "SD_DATA2_R", - "SD_DATA3_R"; - - pinctrl-0 = <&gpioout &alt0 &i2s_alt2>; - - /* I2S interface */ - i2s_alt2: i2s_alt2 { - brcm,pins = <28 29 30 31>; - brcm,function = ; - }; -}; - -&hdmi { - hpd-gpios = <&gpio 46 GPIO_ACTIVE_HIGH>; - power-domains = <&power RPI_POWER_DOMAIN_HDMI>; - status = "okay"; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio45>; - status = "okay"; -}; - -&sdhost { - pinctrl-names = "default"; - pinctrl-0 = <&sdhost_gpio48>; - bus-width = <4>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_gpio14>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/bcm2835-rpi-b-plus.dts b/sys/gnu/dts/arm/bcm2835-rpi-b-plus.dts deleted file mode 100644 index b0355c229cd..00000000000 --- a/sys/gnu/dts/arm/bcm2835-rpi-b-plus.dts +++ /dev/null @@ -1,130 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; -#include "bcm2835.dtsi" -#include "bcm2835-rpi.dtsi" -#include "bcm283x-rpi-smsc9514.dtsi" -#include "bcm283x-rpi-usb-host.dtsi" - -/ { - compatible = "raspberrypi,model-b-plus", "brcm,bcm2835"; - model = "Raspberry Pi Model B+"; - - memory@0 { - device_type = "memory"; - reg = <0 0x20000000>; - }; - - leds { - act { - gpios = <&gpio 47 GPIO_ACTIVE_HIGH>; - }; - - pwr { - label = "PWR"; - gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - linux,default-trigger = "default-on"; - }; - }; -}; - -&gpio { - /* - * Taken from Raspberry-Pi-B-Plus-V1.2-Schematics.pdf - * RPI-BPLUS sheet 1 - * - * Legend: - * "NC" = not connected (no rail from the SoC) - * "FOO" = GPIO line named "FOO" on the schematic - * "FOO_N" = GPIO line named "FOO" on schematic, active low - */ - gpio-line-names = "ID_SDA", - "ID_SCL", - "SDA1", - "SCL1", - "GPIO_GCLK", - "GPIO5", - "GPIO6", - "SPI_CE1_N", - "SPI_CE0_N", - "SPI_MISO", - "SPI_MOSI", - "SPI_SCLK", - "GPIO12", - "GPIO13", - /* Serial port */ - "TXD0", - "RXD0", - "GPIO16", - "GPIO17", - "GPIO18", - "GPIO19", - "GPIO20", - "GPIO21", - "GPIO22", - "GPIO23", - "GPIO24", - "GPIO25", - "GPIO26", - "GPIO27", - "SDA0", - "SCL0", - "NC", /* GPIO30 */ - "LAN_RUN", /* GPIO31 */ - "CAM_GPIO1", /* GPIO32 */ - "NC", /* GPIO33 */ - "NC", /* GPIO34 */ - "PWR_LOW_N", /* GPIO35 */ - "NC", /* GPIO36 */ - "NC", /* GPIO37 */ - "USB_LIMIT", /* GPIO38 */ - "NC", /* GPIO39 */ - "PWM0_OUT", /* GPIO40 */ - "CAM_GPIO0", /* GPIO41 */ - "NC", /* GPIO42 */ - "NC", /* GPIO43 */ - "ETHCLK", /* GPIO44 */ - "PWM1_OUT", /* GPIO45 */ - "HDMI_HPD_N", - "STATUS_LED", - /* Used by SD Card */ - "SD_CLK_R", - "SD_CMD_R", - "SD_DATA0_R", - "SD_DATA1_R", - "SD_DATA2_R", - "SD_DATA3_R"; - - pinctrl-0 = <&gpioout &alt0 &i2s_alt0>; - - /* I2S interface */ - i2s_alt0: i2s_alt0 { - brcm,pins = <18 19 20 21>; - brcm,function = ; - }; -}; - -&hdmi { - hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>; - power-domains = <&power RPI_POWER_DOMAIN_HDMI>; - status = "okay"; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio45>; - status = "okay"; -}; - -&sdhost { - pinctrl-names = "default"; - pinctrl-0 = <&sdhost_gpio48>; - bus-width = <4>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_gpio14>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/bcm2835-rpi-b-rev2.dts b/sys/gnu/dts/arm/bcm2835-rpi-b-rev2.dts deleted file mode 100644 index 33b3b5c0252..00000000000 --- a/sys/gnu/dts/arm/bcm2835-rpi-b-rev2.dts +++ /dev/null @@ -1,123 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; -#include "bcm2835.dtsi" -#include "bcm2835-rpi.dtsi" -#include "bcm283x-rpi-smsc9512.dtsi" -#include "bcm283x-rpi-usb-host.dtsi" - -/ { - compatible = "raspberrypi,model-b-rev2", "brcm,bcm2835"; - model = "Raspberry Pi Model B rev2"; - - memory@0 { - device_type = "memory"; - reg = <0 0x10000000>; - }; - - leds { - act { - gpios = <&gpio 16 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&gpio { - /* - * Taken from Raspberry-Pi-Rev-2.0-Model-AB-Schematics.pdf - * RPI00022 sheet 02 - * - * Legend: - * "NC" = not connected (no rail from the SoC) - * "FOO" = GPIO line named "FOO" on the schematic - * "FOO_N" = GPIO line named "FOO" on schematic, active low - */ - gpio-line-names = "SDA0", - "SCL0", - "SDA1", - "SCL1", - "GPIO_GCLK", - "CAM_CLK", - "LAN_RUN", - "SPI_CE1_N", - "SPI_CE0_N", - "SPI_MISO", - "SPI_MOSI", - "SPI_SCLK", - "NC", /* GPIO12 */ - "NC", /* GPIO13 */ - /* Serial port */ - "TXD0", - "RXD0", - "STATUS_LED_N", - "GPIO17", - "GPIO18", - "NC", /* GPIO19 */ - "NC", /* GPIO20 */ - "CAM_GPIO", - "GPIO22", - "GPIO23", - "GPIO24", - "GPIO25", - "NC", /* GPIO26 */ - "GPIO27", - "GPIO28", - "GPIO29", - "GPIO30", - "GPIO31", - "NC", /* GPIO32 */ - "NC", /* GPIO33 */ - "NC", /* GPIO34 */ - "NC", /* GPIO35 */ - "NC", /* GPIO36 */ - "NC", /* GPIO37 */ - "NC", /* GPIO38 */ - "NC", /* GPIO39 */ - "PWM0_OUT", - "NC", /* GPIO41 */ - "NC", /* GPIO42 */ - "NC", /* GPIO43 */ - "NC", /* GPIO44 */ - "PWM1_OUT", - "HDMI_HPD_P", - "SD_CARD_DET", - /* Used by SD Card */ - "SD_CLK_R", - "SD_CMD_R", - "SD_DATA0_R", - "SD_DATA1_R", - "SD_DATA2_R", - "SD_DATA3_R"; - - pinctrl-0 = <&gpioout &alt0 &i2s_alt2>; - - /* I2S interface */ - i2s_alt2: i2s_alt2 { - brcm,pins = <28 29 30 31>; - brcm,function = ; - }; -}; - -&hdmi { - hpd-gpios = <&gpio 46 GPIO_ACTIVE_HIGH>; - power-domains = <&power RPI_POWER_DOMAIN_HDMI>; - status = "okay"; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio45>; - status = "okay"; -}; - -&sdhost { - pinctrl-names = "default"; - pinctrl-0 = <&sdhost_gpio48>; - bus-width = <4>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_gpio14>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/bcm2835-rpi-b.dts b/sys/gnu/dts/arm/bcm2835-rpi-b.dts deleted file mode 100644 index 2b69957e011..00000000000 --- a/sys/gnu/dts/arm/bcm2835-rpi-b.dts +++ /dev/null @@ -1,118 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; -#include "bcm2835.dtsi" -#include "bcm2835-rpi.dtsi" -#include "bcm283x-rpi-smsc9512.dtsi" -#include "bcm283x-rpi-usb-host.dtsi" - -/ { - compatible = "raspberrypi,model-b", "brcm,bcm2835"; - model = "Raspberry Pi Model B"; - - memory@0 { - device_type = "memory"; - reg = <0 0x10000000>; - }; - - leds { - act { - gpios = <&gpio 16 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&gpio { - /* - * Taken from Raspberry-Pi-Rev-1.0-Model-AB-Schematics.pdf - * RPI00021 sheet 02 - * - * Legend: - * "NC" = not connected (no rail from the SoC) - * "FOO" = GPIO line named "FOO" on the schematic - * "FOO_N" = GPIO line named "FOO" on schematic, active low - */ - gpio-line-names = "SDA0", - "SCL0", - "SDA1", - "SCL1", - "GPIO_GCLK", - "CAM_GPIO1", - "LAN_RUN", - "SPI_CE1_N", - "SPI_CE0_N", - "SPI_MISO", - "SPI_MOSI", - "SPI_SCLK", - "NC", /* GPIO12 */ - "NC", /* GPIO13 */ - /* Serial port */ - "TXD0", - "RXD0", - "STATUS_LED_N", - "GPIO17", - "GPIO18", - "NC", /* GPIO19 */ - "NC", /* GPIO20 */ - "GPIO21", - "GPIO22", - "GPIO23", - "GPIO24", - "GPIO25", - "NC", /* GPIO26 */ - "CAM_GPIO0", - /* Binary number representing build/revision */ - "CONFIG0", - "CONFIG1", - "CONFIG2", - "CONFIG3", - "NC", /* GPIO32 */ - "NC", /* GPIO33 */ - "NC", /* GPIO34 */ - "NC", /* GPIO35 */ - "NC", /* GPIO36 */ - "NC", /* GPIO37 */ - "NC", /* GPIO38 */ - "NC", /* GPIO39 */ - "PWM0_OUT", - "NC", /* GPIO41 */ - "NC", /* GPIO42 */ - "NC", /* GPIO43 */ - "NC", /* GPIO44 */ - "PWM1_OUT", - "HDMI_HPD_P", - "SD_CARD_DET", - /* Used by SD Card */ - "SD_CLK_R", - "SD_CMD_R", - "SD_DATA0_R", - "SD_DATA1_R", - "SD_DATA2_R", - "SD_DATA3_R"; - - pinctrl-0 = <&gpioout &alt0>; -}; - -&hdmi { - hpd-gpios = <&gpio 46 GPIO_ACTIVE_HIGH>; - power-domains = <&power RPI_POWER_DOMAIN_HDMI>; - status = "okay"; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio45>; - status = "okay"; -}; - -&sdhost { - pinctrl-names = "default"; - pinctrl-0 = <&sdhost_gpio48>; - bus-width = <4>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_gpio14>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/bcm2835-rpi-cm1-io1.dts b/sys/gnu/dts/arm/bcm2835-rpi-cm1-io1.dts deleted file mode 100644 index a75c882e657..00000000000 --- a/sys/gnu/dts/arm/bcm2835-rpi-cm1-io1.dts +++ /dev/null @@ -1,97 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; -#include "bcm2835-rpi-cm1.dtsi" -#include "bcm283x-rpi-usb-host.dtsi" - -/ { - compatible = "raspberrypi,compute-module", "brcm,bcm2835"; - model = "Raspberry Pi Compute Module IO board rev1"; -}; - -&gpio { - /* - * This is based on the official GPU firmware DT blob. - * - * Legend: - * "NC" = not connected (no rail from the SoC) - * "FOO" = GPIO line named "FOO" on the schematic - * "FOO_N" = GPIO line named "FOO" on schematic, active low - */ - gpio-line-names = "GPIO0", - "GPIO1", - "GPIO2", - "GPIO3", - "GPIO4", - "GPIO5", - "GPIO6", - "GPIO7", - "GPIO8", - "GPIO9", - "GPIO10", - "GPIO11", - "GPIO12", - "GPIO13", - "GPIO14", - "GPIO15", - "GPIO16", - "GPIO17", - "GPIO18", - "GPIO19", - "GPIO20", - "GPIO21", - "GPIO22", - "GPIO23", - "GPIO24", - "GPIO25", - "GPIO26", - "GPIO27", - "GPIO28", - "GPIO29", - "GPIO30", - "GPIO31", - "GPIO32", - "GPIO33", - "GPIO34", - "GPIO35", - "GPIO36", - "GPIO37", - "GPIO38", - "GPIO39", - "GPIO40", - "GPIO41", - "GPIO42", - "GPIO43", - "GPIO44", - "GPIO45", - "HDMI_HPD_N", - /* Also used as ACT LED */ - "EMMC_EN_N", - /* Used by eMMC */ - "SD_CLK_R", - "SD_CMD_R", - "SD_DATA0_R", - "SD_DATA1_R", - "SD_DATA2_R", - "SD_DATA3_R"; - - pinctrl-0 = <&gpioout &alt0>; -}; - -&hdmi { - hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>; - power-domains = <&power RPI_POWER_DOMAIN_HDMI>; - status = "okay"; -}; - -&sdhost { - pinctrl-names = "default"; - pinctrl-0 = <&sdhost_gpio48>; - bus-width = <4>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_gpio14>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/bcm2835-rpi-cm1.dtsi b/sys/gnu/dts/arm/bcm2835-rpi-cm1.dtsi deleted file mode 100644 index 58059c2ce12..00000000000 --- a/sys/gnu/dts/arm/bcm2835-rpi-cm1.dtsi +++ /dev/null @@ -1,39 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; -#include "bcm2835.dtsi" -#include "bcm2835-rpi.dtsi" - -/ { - leds { - act { - gpios = <&gpio 47 GPIO_ACTIVE_LOW>; - }; - }; - - memory@0 { - device_type = "memory"; - reg = <0 0x20000000>; - }; - - reg_3v3: fixed-regulator { - compatible = "regulator-fixed"; - regulator-name = "3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_1v8: fixed-regulator { - compatible = "regulator-fixed"; - regulator-name = "1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; -}; - -&sdhost { - non-removable; - vmmc-supply = <®_3v3>; - vqmmc-supply = <®_1v8>; -}; diff --git a/sys/gnu/dts/arm/bcm2835-rpi-zero-w.dts b/sys/gnu/dts/arm/bcm2835-rpi-zero-w.dts deleted file mode 100644 index 4c3f606e5b8..00000000000 --- a/sys/gnu/dts/arm/bcm2835-rpi-zero-w.dts +++ /dev/null @@ -1,151 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2017 Stefan Wahren - */ - -/dts-v1/; -#include "bcm2835.dtsi" -#include "bcm2835-rpi.dtsi" -#include "bcm283x-rpi-usb-otg.dtsi" - -/ { - compatible = "raspberrypi,model-zero-w", "brcm,bcm2835"; - model = "Raspberry Pi Zero W"; - - memory@0 { - device_type = "memory"; - reg = <0 0x20000000>; - }; - - chosen { - /* 8250 auxiliary UART instead of pl011 */ - stdout-path = "serial1:115200n8"; - }; - - leds { - act { - gpios = <&gpio 47 GPIO_ACTIVE_HIGH>; - }; - }; - - wifi_pwrseq: wifi-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio 41 GPIO_ACTIVE_LOW>; - }; -}; - -&gpio { - /* - * This is based on the official GPU firmware DT blob. - * - * Legend: - * "NC" = not connected (no rail from the SoC) - * "FOO" = GPIO line named "FOO" on the schematic - * "FOO_N" = GPIO line named "FOO" on schematic, active low - */ - gpio-line-names = "ID_SDA", - "ID_SCL", - "SDA1", - "SCL1", - "GPIO_GCLK", - "GPIO5", - "GPIO6", - "SPI_CE1_N", - "SPI_CE0_N", - "SPI_MISO", - "SPI_MOSI", - "SPI_SCLK", - "GPIO12", - "GPIO13", - /* Serial port */ - "TXD0", - "RXD0", - "GPIO16", - "GPIO17", - "GPIO18", - "GPIO19", - "GPIO20", - "GPIO21", - "GPIO22", - "GPIO23", - "GPIO24", - "GPIO25", - "GPIO26", - "GPIO27", - "SDA0", - "SCL0", - "NC", /* GPIO30 */ - "NC", /* GPIO31 */ - "NC", /* GPIO32 */ - "NC", /* GPIO33 */ - "NC", /* GPIO34 */ - "NC", /* GPIO35 */ - "NC", /* GPIO36 */ - "NC", /* GPIO37 */ - "NC", /* GPIO38 */ - "NC", /* GPIO39 */ - "CAM_GPIO1", /* GPIO40 */ - "WL_ON", /* GPIO41 */ - "NC", /* GPIO42 */ - "WIFI_CLK", /* GPIO43 */ - "CAM_GPIO0", /* GPIO44 */ - "BT_ON", /* GPIO45 */ - "HDMI_HPD_N", - "STATUS_LED_N", - /* Used by SD Card */ - "SD_CLK_R", - "SD_CMD_R", - "SD_DATA0_R", - "SD_DATA1_R", - "SD_DATA2_R", - "SD_DATA3_R"; - - pinctrl-0 = <&gpioout &alt0>; -}; - -&hdmi { - hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>; - power-domains = <&power RPI_POWER_DOMAIN_HDMI>; - status = "okay"; -}; - -&sdhci { - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_gpio34 &gpclk2_gpio43>; - bus-width = <4>; - mmc-pwrseq = <&wifi_pwrseq>; - non-removable; - status = "okay"; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - }; -}; - -&sdhost { - pinctrl-names = "default"; - pinctrl-0 = <&sdhost_gpio48>; - bus-width = <4>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_gpio32 &uart0_ctsrts_gpio30>; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - max-speed = <2000000>; - shutdown-gpios = <&gpio 45 GPIO_ACTIVE_HIGH>; - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_gpio14>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/bcm2835-rpi-zero.dts b/sys/gnu/dts/arm/bcm2835-rpi-zero.dts deleted file mode 100644 index 6dd93c6f496..00000000000 --- a/sys/gnu/dts/arm/bcm2835-rpi-zero.dts +++ /dev/null @@ -1,119 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2016 Stefan Wahren - */ - -/dts-v1/; -#include "bcm2835.dtsi" -#include "bcm2835-rpi.dtsi" -#include "bcm283x-rpi-usb-otg.dtsi" - -/ { - compatible = "raspberrypi,model-zero", "brcm,bcm2835"; - model = "Raspberry Pi Zero"; - - memory@0 { - device_type = "memory"; - reg = <0 0x20000000>; - }; - - leds { - act { - gpios = <&gpio 47 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&gpio { - /* - * This is based on the official GPU firmware DT blob. - * - * Legend: - * "NC" = not connected (no rail from the SoC) - * "FOO" = GPIO line named "FOO" on the schematic - * "FOO_N" = GPIO line named "FOO" on schematic, active low - */ - gpio-line-names = "ID_SDA", - "ID_SCL", - "SDA1", - "SCL1", - "GPIO_GCLK", - "GPIO5", - "GPIO6", - "SPI_CE1_N", - "SPI_CE0_N", - "SPI_MISO", - "SPI_MOSI", - "SPI_SCLK", - "GPIO12", - "GPIO13", - /* Serial port */ - "TXD0", - "RXD0", - "GPIO16", - "GPIO17", - "GPIO18", - "GPIO19", - "GPIO20", - "GPIO21", - "GPIO22", - "GPIO23", - "GPIO24", - "GPIO25", - "GPIO26", - "GPIO27", - "SDA0", - "SCL0", - "NC", /* GPIO30 */ - "NC", /* GPIO31 */ - "CAM_GPIO1", /* GPIO32 */ - "NC", /* GPIO33 */ - "NC", /* GPIO34 */ - "NC", /* GPIO35 */ - "NC", /* GPIO36 */ - "NC", /* GPIO37 */ - "NC", /* GPIO38 */ - "NC", /* GPIO39 */ - "NC", /* GPIO40 */ - "CAM_GPIO0", /* GPIO41 */ - "NC", /* GPIO42 */ - "NC", /* GPIO43 */ - "NC", /* GPIO44 */ - "NC", /* GPIO45 */ - "HDMI_HPD_N", - "STATUS_LED_N", - /* Used by SD Card */ - "SD_CLK_R", - "SD_CMD_R", - "SD_DATA0_R", - "SD_DATA1_R", - "SD_DATA2_R", - "SD_DATA3_R"; - - pinctrl-0 = <&gpioout &alt0 &i2s_alt0>; - - /* I2S interface */ - i2s_alt0: i2s_alt0 { - brcm,pins = <18 19 20 21>; - brcm,function = ; - }; -}; - -&hdmi { - hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>; - power-domains = <&power RPI_POWER_DOMAIN_HDMI>; - status = "okay"; -}; - -&sdhost { - pinctrl-names = "default"; - pinctrl-0 = <&sdhost_gpio48>; - bus-width = <4>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_gpio14>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/bcm2835-rpi.dtsi b/sys/gnu/dts/arm/bcm2835-rpi.dtsi deleted file mode 100644 index fd2c766e0f7..00000000000 --- a/sys/gnu/dts/arm/bcm2835-rpi.dtsi +++ /dev/null @@ -1,78 +0,0 @@ -#include - -/ { - leds { - compatible = "gpio-leds"; - - act { - label = "ACT"; - default-state = "keep"; - linux,default-trigger = "heartbeat"; - }; - }; - - soc { - firmware: firmware { - compatible = "raspberrypi,bcm2835-firmware", "simple-bus"; - mboxes = <&mailbox>; - dma-ranges; - }; - - power: power { - compatible = "raspberrypi,bcm2835-power"; - firmware = <&firmware>; - #power-domain-cells = <1>; - }; - - vchiq: mailbox@7e00b840 { - compatible = "brcm,bcm2835-vchiq"; - reg = <0x7e00b840 0x3c>; - interrupts = <0 2>; - }; - }; -}; - -&gpio { - pinctrl-names = "default"; - - gpioout: gpioout { - brcm,pins = <6>; - brcm,function = ; - }; - - alt0: alt0 { - brcm,pins = <4 5 7 8 9 10 11>; - brcm,function = ; - }; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_gpio0>; - status = "okay"; - clock-frequency = <100000>; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_gpio2>; - status = "okay"; - clock-frequency = <100000>; -}; - -&usb { - power-domains = <&power RPI_POWER_DOMAIN_USB>; -}; - -&vec { - power-domains = <&power RPI_POWER_DOMAIN_VEC>; - status = "okay"; -}; - -&dsi0 { - power-domains = <&power RPI_POWER_DOMAIN_DSI0>; -}; - -&dsi1 { - power-domains = <&power RPI_POWER_DOMAIN_DSI1>; -}; diff --git a/sys/gnu/dts/arm/bcm2835.dtsi b/sys/gnu/dts/arm/bcm2835.dtsi deleted file mode 100644 index 53bf4579cc2..00000000000 --- a/sys/gnu/dts/arm/bcm2835.dtsi +++ /dev/null @@ -1,37 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "bcm283x.dtsi" -#include "bcm2835-common.dtsi" - -/ { - compatible = "brcm,bcm2835"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,arm1176jzf-s"; - reg = <0x0>; - }; - }; - - soc { - ranges = <0x7e000000 0x20000000 0x02000000>; - dma-ranges = <0x40000000 0x00000000 0x20000000>; - }; - - arm-pmu { - compatible = "arm,arm1176-pmu"; - }; -}; - -&cpu_thermal { - coefficients = <(-538) 407000>; -}; - -/* enable thermal sensor with the correct compatible property set */ -&thermal { - compatible = "brcm,bcm2835-thermal"; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/bcm2836-rpi-2-b.dts b/sys/gnu/dts/arm/bcm2836-rpi-2-b.dts deleted file mode 100644 index 0455a680394..00000000000 --- a/sys/gnu/dts/arm/bcm2836-rpi-2-b.dts +++ /dev/null @@ -1,130 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; -#include "bcm2836.dtsi" -#include "bcm2836-rpi.dtsi" -#include "bcm283x-rpi-smsc9514.dtsi" -#include "bcm283x-rpi-usb-host.dtsi" - -/ { - compatible = "raspberrypi,2-model-b", "brcm,bcm2836"; - model = "Raspberry Pi 2 Model B"; - - memory@0 { - device_type = "memory"; - reg = <0 0x40000000>; - }; - - leds { - act { - gpios = <&gpio 47 GPIO_ACTIVE_HIGH>; - }; - - pwr { - label = "PWR"; - gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - linux,default-trigger = "default-on"; - }; - }; -}; - -&gpio { - /* - * Taken from rpi_SCH_2b_1p2_reduced.pdf and - * the official GPU firmware DT blob. - * - * Legend: - * "NC" = not connected (no rail from the SoC) - * "FOO" = GPIO line named "FOO" on the schematic - * "FOO_N" = GPIO line named "FOO" on schematic, active low - */ - gpio-line-names = "ID_SDA", - "ID_SCL", - "SDA1", - "SCL1", - "GPIO_GCLK", - "GPIO5", - "GPIO6", - "SPI_CE1_N", - "SPI_CE0_N", - "SPI_MISO", - "SPI_MOSI", - "SPI_SCLK", - "GPIO12", - "GPIO13", - /* Serial port */ - "TXD0", - "RXD0", - "GPIO16", - "GPIO17", - "GPIO18", - "GPIO19", - "GPIO20", - "GPIO21", - "GPIO22", - "GPIO23", - "GPIO24", - "GPIO25", - "GPIO26", - "GPIO27", - "SDA0", - "SCL0", - "", /* GPIO30 */ - "LAN_RUN", - "CAM_GPIO1", - "", /* GPIO33 */ - "", /* GPIO34 */ - "PWR_LOW_N", - "", /* GPIO36 */ - "", /* GPIO37 */ - "USB_LIMIT", - "", /* GPIO39 */ - "PWM0_OUT", - "CAM_GPIO0", - "SMPS_SCL", - "SMPS_SDA", - "ETHCLK", - "PWM1_OUT", - "HDMI_HPD_N", - "STATUS_LED", - /* Used by SD Card */ - "SD_CLK_R", - "SD_CMD_R", - "SD_DATA0_R", - "SD_DATA1_R", - "SD_DATA2_R", - "SD_DATA3_R"; - - pinctrl-0 = <&gpioout &alt0 &i2s_alt0>; - - /* I2S interface */ - i2s_alt0: i2s_alt0 { - brcm,pins = <18 19 20 21>; - brcm,function = ; - }; -}; - -&hdmi { - hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>; - power-domains = <&power RPI_POWER_DOMAIN_HDMI>; - status = "okay"; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio45>; - status = "okay"; -}; - -&sdhost { - pinctrl-names = "default"; - pinctrl-0 = <&sdhost_gpio48>; - bus-width = <4>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_gpio14>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/bcm2836-rpi.dtsi b/sys/gnu/dts/arm/bcm2836-rpi.dtsi deleted file mode 100644 index c4c858b984c..00000000000 --- a/sys/gnu/dts/arm/bcm2836-rpi.dtsi +++ /dev/null @@ -1,6 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "bcm2835-rpi.dtsi" - -&vchiq { - compatible = "brcm,bcm2836-vchiq", "brcm,bcm2835-vchiq"; -}; diff --git a/sys/gnu/dts/arm/bcm2836.dtsi b/sys/gnu/dts/arm/bcm2836.dtsi deleted file mode 100644 index 82d6c4662ae..00000000000 --- a/sys/gnu/dts/arm/bcm2836.dtsi +++ /dev/null @@ -1,91 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "bcm283x.dtsi" -#include "bcm2835-common.dtsi" - -/ { - compatible = "brcm,bcm2836"; - - soc { - ranges = <0x7e000000 0x3f000000 0x1000000>, - <0x40000000 0x40000000 0x00001000>; - dma-ranges = <0xc0000000 0x00000000 0x3f000000>; - - local_intc: local_intc@40000000 { - compatible = "brcm,bcm2836-l1-intc"; - reg = <0x40000000 0x100>; - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&local_intc>; - }; - }; - - arm-pmu { - compatible = "arm,cortex-a7-pmu"; - interrupt-parent = <&local_intc>; - interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupt-parent = <&local_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_HIGH>, // PHYS_SECURE_PPI - <1 IRQ_TYPE_LEVEL_HIGH>, // PHYS_NONSECURE_PPI - <3 IRQ_TYPE_LEVEL_HIGH>, // VIRT_PPI - <2 IRQ_TYPE_LEVEL_HIGH>; // HYP_PPI - always-on; - }; - - cpus: cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "brcm,bcm2836-smp"; - - v7_cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0xf00>; - clock-frequency = <800000000>; - }; - - v7_cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0xf01>; - clock-frequency = <800000000>; - }; - - v7_cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0xf02>; - clock-frequency = <800000000>; - }; - - v7_cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0xf03>; - clock-frequency = <800000000>; - }; - }; -}; - -/* Make the BCM2835-style global interrupt controller be a child of the - * CPU-local interrupt controller. - */ -&intc { - compatible = "brcm,bcm2836-armctrl-ic"; - reg = <0x7e00b200 0x200>; - interrupt-parent = <&local_intc>; - interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; -}; - -&cpu_thermal { - coefficients = <(-538) 407000>; -}; - -/* enable thermal sensor with the correct compatible property set */ -&thermal { - compatible = "brcm,bcm2836-thermal"; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/bcm2837-rpi-3-a-plus.dts b/sys/gnu/dts/arm/bcm2837-rpi-3-a-plus.dts deleted file mode 100644 index 28be0332c1c..00000000000 --- a/sys/gnu/dts/arm/bcm2837-rpi-3-a-plus.dts +++ /dev/null @@ -1,180 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; -#include "bcm2837.dtsi" -#include "bcm2836-rpi.dtsi" -#include "bcm283x-rpi-usb-host.dtsi" - -/ { - compatible = "raspberrypi,3-model-a-plus", "brcm,bcm2837"; - model = "Raspberry Pi 3 Model A+"; - - chosen { - /* 8250 auxiliary UART instead of pl011 */ - stdout-path = "serial1:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0 0x20000000>; - }; - - leds { - act { - gpios = <&gpio 29 GPIO_ACTIVE_HIGH>; - }; - - pwr { - label = "PWR"; - gpios = <&expgpio 2 GPIO_ACTIVE_LOW>; - default-state = "keep"; - linux,default-trigger = "default-on"; - }; - }; -}; - -&firmware { - expgpio: gpio { - compatible = "raspberrypi,firmware-gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio-line-names = "", - "BT_WL_ON", - "STATUS_LED_R", - "", - "", - "CAM_GPIO0", - "CAM_GPIO1", - ""; - status = "okay"; - }; -}; - -&gpio { - /* - * This is mostly based on the official GPU firmware DT blob. - * - * Legend: - * "NC" = not connected (no rail from the SoC) - * "FOO" = GPIO line named "FOO" on the schematic - * "FOO_N" = GPIO line named "FOO" on schematic, active low - */ - gpio-line-names = "ID_SDA", - "ID_SCL", - "SDA1", - "SCL1", - "GPIO_GCLK", - "GPIO5", - "GPIO6", - "SPI_CE1_N", - "SPI_CE0_N", - "SPI_MISO", - "SPI_MOSI", - "SPI_SCLK", - "GPIO12", - "GPIO13", - /* Serial port */ - "TXD1", - "RXD1", - "GPIO16", - "GPIO17", - "GPIO18", - "GPIO19", - "GPIO20", - "GPIO21", - "GPIO22", - "GPIO23", - "GPIO24", - "GPIO25", - "GPIO26", - "GPIO27", - "HDMI_HPD_N", - "STATUS_LED_G", - /* Used by BT module */ - "CTS0", - "RTS0", - "TXD0", - "RXD0", - /* Used by Wifi */ - "SD1_CLK", - "SD1_CMD", - "SD1_DATA0", - "SD1_DATA1", - "SD1_DATA2", - "SD1_DATA3", - "PWM0_OUT", - "PWM1_OUT", - "", /* GPIO42 */ - "WIFI_CLK", - "SDA0", - "SCL0", - "SMPS_SCL", - "SMPS_SDA", - /* Used by SD Card */ - "SD_CLK_R", - "SD_CMD_R", - "SD_DATA0_R", - "SD_DATA1_R", - "SD_DATA2_R", - "SD_DATA3_R"; -}; - -&hdmi { - hpd-gpios = <&gpio 28 GPIO_ACTIVE_LOW>; - power-domains = <&power RPI_POWER_DOMAIN_HDMI>; - status = "okay"; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio41>; - status = "okay"; -}; - -/* - * SDHCI is used to control the SDIO for wireless - * - * WL_REG_ON and BT_REG_ON of the CYW43455 Wifi/BT module are driven - * by a single GPIO. We can't give GPIO control to one of the drivers, - * otherwise the other part would get unexpectedly disturbed. - */ -&sdhci { - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_gpio34>; - status = "okay"; - bus-width = <4>; - non-removable; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - }; -}; - -/* SDHOST is used to drive the SD card */ -&sdhost { - pinctrl-names = "default"; - pinctrl-0 = <&sdhost_gpio48>; - status = "okay"; - bus-width = <4>; -}; - -/* uart0 communicates with the BT module */ -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_ctsrts_gpio30 &uart0_gpio32 &gpclk2_gpio43>; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - max-speed = <2000000>; - }; -}; - -/* uart1 is mapped to the pin header */ -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_gpio14>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/bcm2837-rpi-3-b-plus.dts b/sys/gnu/dts/arm/bcm2837-rpi-3-b-plus.dts deleted file mode 100644 index 37343148643..00000000000 --- a/sys/gnu/dts/arm/bcm2837-rpi-3-b-plus.dts +++ /dev/null @@ -1,183 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; -#include "bcm2837.dtsi" -#include "bcm2836-rpi.dtsi" -#include "bcm283x-rpi-lan7515.dtsi" -#include "bcm283x-rpi-usb-host.dtsi" - -/ { - compatible = "raspberrypi,3-model-b-plus", "brcm,bcm2837"; - model = "Raspberry Pi 3 Model B+"; - - chosen { - /* 8250 auxiliary UART instead of pl011 */ - stdout-path = "serial1:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0 0x40000000>; - }; - - leds { - act { - gpios = <&gpio 29 GPIO_ACTIVE_HIGH>; - }; - - pwr { - label = "PWR"; - gpios = <&expgpio 2 GPIO_ACTIVE_LOW>; - default-state = "keep"; - linux,default-trigger = "default-on"; - }; - }; - - wifi_pwrseq: wifi-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&expgpio 1 GPIO_ACTIVE_LOW>; - }; -}; - -&firmware { - expgpio: gpio { - compatible = "raspberrypi,firmware-gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio-line-names = "BT_ON", - "WL_ON", - "STATUS_LED_R", - "LAN_RUN", - "", - "CAM_GPIO0", - "CAM_GPIO1", - ""; - status = "okay"; - }; -}; - -&gpio { - /* - * Taken from rpi_SCH_3bplus_1p0_reduced.pdf and - * the official GPU firmware DT blob. - * - * Legend: - * "NC" = not connected (no rail from the SoC) - * "FOO" = GPIO line named "FOO" on the schematic - * "FOO_N" = GPIO line named "FOO" on schematic, active low - */ - gpio-line-names = "ID_SDA", - "ID_SCL", - "SDA1", - "SCL1", - "GPIO_GCLK", - "GPIO5", - "GPIO6", - "SPI_CE1_N", - "SPI_CE0_N", - "SPI_MISO", - "SPI_MOSI", - "SPI_SCLK", - "GPIO12", - "GPIO13", - /* Serial port */ - "TXD1", - "RXD1", - "GPIO16", - "GPIO17", - "GPIO18", - "GPIO19", - "GPIO20", - "GPIO21", - "GPIO22", - "GPIO23", - "GPIO24", - "GPIO25", - "GPIO26", - "GPIO27", - "HDMI_HPD_N", - "STATUS_LED_G", - /* Used by BT module */ - "CTS0", - "RTS0", - "TXD0", - "RXD0", - /* Used by Wifi */ - "SD1_CLK", - "SD1_CMD", - "SD1_DATA0", - "SD1_DATA1", - "SD1_DATA2", - "SD1_DATA3", - "PWM0_OUT", - "PWM1_OUT", - "ETHCLK", - "WIFI_CLK", - "SDA0", - "SCL0", - "SMPS_SCL", - "SMPS_SDA", - /* Used by SD Card */ - "SD_CLK_R", - "SD_CMD_R", - "SD_DATA0_R", - "SD_DATA1_R", - "SD_DATA2_R", - "SD_DATA3_R"; -}; - -&hdmi { - hpd-gpios = <&gpio 28 GPIO_ACTIVE_LOW>; - power-domains = <&power RPI_POWER_DOMAIN_HDMI>; - status = "okay"; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio41>; - status = "okay"; -}; - -/* SDHCI is used to control the SDIO for wireless */ -&sdhci { - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_gpio34>; - status = "okay"; - bus-width = <4>; - non-removable; - mmc-pwrseq = <&wifi_pwrseq>; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - }; -}; - -/* SDHOST is used to drive the SD card */ -&sdhost { - pinctrl-names = "default"; - pinctrl-0 = <&sdhost_gpio48>; - status = "okay"; - bus-width = <4>; -}; - -/* uart0 communicates with the BT module */ -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_ctsrts_gpio30 &uart0_gpio32 &gpclk2_gpio43>; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - max-speed = <2000000>; - shutdown-gpios = <&expgpio 0 GPIO_ACTIVE_HIGH>; - }; -}; - -/* uart1 is mapped to the pin header */ -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_gpio14>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/bcm2837-rpi-3-b.dts b/sys/gnu/dts/arm/bcm2837-rpi-3-b.dts deleted file mode 100644 index 054ecaa355c..00000000000 --- a/sys/gnu/dts/arm/bcm2837-rpi-3-b.dts +++ /dev/null @@ -1,176 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; -#include "bcm2837.dtsi" -#include "bcm2836-rpi.dtsi" -#include "bcm283x-rpi-smsc9514.dtsi" -#include "bcm283x-rpi-usb-host.dtsi" - -/ { - compatible = "raspberrypi,3-model-b", "brcm,bcm2837"; - model = "Raspberry Pi 3 Model B"; - - chosen { - /* 8250 auxiliary UART instead of pl011 */ - stdout-path = "serial1:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0 0x40000000>; - }; - - leds { - act { - gpios = <&expgpio 2 GPIO_ACTIVE_HIGH>; - }; - }; - - wifi_pwrseq: wifi-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&expgpio 1 GPIO_ACTIVE_LOW>; - }; -}; - -&firmware { - expgpio: gpio { - compatible = "raspberrypi,firmware-gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio-line-names = "BT_ON", - "WL_ON", - "STATUS_LED", - "LAN_RUN", - "HDMI_HPD_N", - "CAM_GPIO0", - "CAM_GPIO1", - "PWR_LOW_N"; - status = "okay"; - }; -}; - -&gpio { - /* - * Taken from rpi_SCH_3b_1p2_reduced.pdf and - * the official GPU firmware DT blob. - * - * Legend: - * "NC" = not connected (no rail from the SoC) - * "FOO" = GPIO line named "FOO" on the schematic - * "FOO_N" = GPIO line named "FOO" on schematic, active low - */ - gpio-line-names = "ID_SDA", - "ID_SCL", - "SDA1", - "SCL1", - "GPIO_GCLK", - "GPIO5", - "GPIO6", - "SPI_CE1_N", - "SPI_CE0_N", - "SPI_MISO", - "SPI_MOSI", - "SPI_SCLK", - "GPIO12", - "GPIO13", - /* Serial port */ - "TXD1", - "RXD1", - "GPIO16", - "GPIO17", - "GPIO18", - "GPIO19", - "GPIO20", - "GPIO21", - "GPIO22", - "GPIO23", - "GPIO24", - "GPIO25", - "GPIO26", - "GPIO27", - "", /* GPIO 28 */ - "LAN_RUN_BOOT", - /* Used by BT module */ - "CTS0", - "RTS0", - "TXD0", - "RXD0", - /* Used by Wifi */ - "SD1_CLK", - "SD1_CMD", - "SD1_DATA0", - "SD1_DATA1", - "SD1_DATA2", - "SD1_DATA3", - "PWM0_OUT", - "PWM1_OUT", - "ETHCLK", - "WIFI_CLK", - "SDA0", - "SCL0", - "SMPS_SCL", - "SMPS_SDA", - /* Used by SD Card */ - "SD_CLK_R", - "SD_CMD_R", - "SD_DATA0_R", - "SD_DATA1_R", - "SD_DATA2_R", - "SD_DATA3_R"; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio41>; - status = "okay"; -}; - -&hdmi { - hpd-gpios = <&expgpio 4 GPIO_ACTIVE_LOW>; - power-domains = <&power RPI_POWER_DOMAIN_HDMI>; - status = "okay"; -}; - -/* uart0 communicates with the BT module */ -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_gpio32 &gpclk2_gpio43>; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - max-speed = <2000000>; - shutdown-gpios = <&expgpio 0 GPIO_ACTIVE_HIGH>; - }; -}; - -/* uart1 is mapped to the pin header */ -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_gpio14>; - status = "okay"; -}; - -/* SDHCI is used to control the SDIO for wireless */ -&sdhci { - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_gpio34>; - status = "okay"; - bus-width = <4>; - non-removable; - mmc-pwrseq = <&wifi_pwrseq>; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - }; -}; - -/* SDHOST is used to drive the SD card */ -&sdhost { - pinctrl-names = "default"; - pinctrl-0 = <&sdhost_gpio48>; - status = "okay"; - bus-width = <4>; -}; diff --git a/sys/gnu/dts/arm/bcm2837-rpi-cm3-io3.dts b/sys/gnu/dts/arm/bcm2837-rpi-cm3-io3.dts deleted file mode 100644 index 588d9411ceb..00000000000 --- a/sys/gnu/dts/arm/bcm2837-rpi-cm3-io3.dts +++ /dev/null @@ -1,96 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; -#include "bcm2837-rpi-cm3.dtsi" -#include "bcm283x-rpi-usb-host.dtsi" - -/ { - compatible = "raspberrypi,3-compute-module", "brcm,bcm2837"; - model = "Raspberry Pi Compute Module 3 IO board V3.0"; -}; - -&gpio { - /* - * This is based on the official GPU firmware DT blob. - * - * Legend: - * "NC" = not connected (no rail from the SoC) - * "FOO" = GPIO line named "FOO" on the schematic - * "FOO_N" = GPIO line named "FOO" on schematic, active low - */ - gpio-line-names = "GPIO0", - "GPIO1", - "GPIO2", - "GPIO3", - "GPIO4", - "GPIO5", - "GPIO6", - "GPIO7", - "GPIO8", - "GPIO9", - "GPIO10", - "GPIO11", - "GPIO12", - "GPIO13", - "GPIO14", - "GPIO15", - "GPIO16", - "GPIO17", - "GPIO18", - "GPIO19", - "GPIO20", - "GPIO21", - "GPIO22", - "GPIO23", - "GPIO24", - "GPIO25", - "GPIO26", - "GPIO27", - "GPIO28", - "GPIO29", - "GPIO30", - "GPIO31", - "GPIO32", - "GPIO33", - "GPIO34", - "GPIO35", - "GPIO36", - "GPIO37", - "GPIO38", - "GPIO39", - "GPIO40", - "GPIO41", - "GPIO42", - "GPIO43", - "GPIO44", - "GPIO45", - "GPIO46", - "GPIO47", - /* Used by eMMC */ - "SD_CLK_R", - "SD_CMD_R", - "SD_DATA0_R", - "SD_DATA1_R", - "SD_DATA2_R", - "SD_DATA3_R"; - - pinctrl-0 = <&gpioout &alt0>; -}; - -&hdmi { - hpd-gpios = <&expgpio 1 GPIO_ACTIVE_LOW>; - power-domains = <&power RPI_POWER_DOMAIN_HDMI>; - status = "okay"; -}; - -&sdhost { - pinctrl-names = "default"; - pinctrl-0 = <&sdhost_gpio48>; - bus-width = <4>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_gpio14>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/bcm2837-rpi-cm3.dtsi b/sys/gnu/dts/arm/bcm2837-rpi-cm3.dtsi deleted file mode 100644 index 925cb37c22f..00000000000 --- a/sys/gnu/dts/arm/bcm2837-rpi-cm3.dtsi +++ /dev/null @@ -1,61 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; -#include "bcm2837.dtsi" -#include "bcm2836-rpi.dtsi" - -/ { - memory@0 { - device_type = "memory"; - reg = <0 0x40000000>; - }; - - leds { - /* - * Since there is no upstream GPIO driver yet, - * remove the incomplete node. - */ - /delete-node/ act; - }; - - reg_3v3: fixed-regulator { - compatible = "regulator-fixed"; - regulator-name = "3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_1v8: fixed-regulator { - compatible = "regulator-fixed"; - regulator-name = "1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; -}; - -&firmware { - expgpio: gpio { - compatible = "raspberrypi,firmware-gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio-line-names = "HDMI_HPD_N", - "EMMC_EN_N", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC"; - status = "okay"; - }; -}; - -&sdhost { - pinctrl-names = "default"; - pinctrl-0 = <&sdhost_gpio48>; - bus-width = <4>; - vmmc-supply = <®_3v3>; - vqmmc-supply = <®_1v8>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/bcm2837.dtsi b/sys/gnu/dts/arm/bcm2837.dtsi deleted file mode 100644 index 9e95fee78e1..00000000000 --- a/sys/gnu/dts/arm/bcm2837.dtsi +++ /dev/null @@ -1,94 +0,0 @@ -#include "bcm283x.dtsi" -#include "bcm2835-common.dtsi" - -/ { - compatible = "brcm,bcm2837"; - - soc { - ranges = <0x7e000000 0x3f000000 0x1000000>, - <0x40000000 0x40000000 0x00001000>; - dma-ranges = <0xc0000000 0x00000000 0x3f000000>; - - local_intc: local_intc@40000000 { - compatible = "brcm,bcm2836-l1-intc"; - reg = <0x40000000 0x100>; - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&local_intc>; - }; - }; - - arm-pmu { - compatible = "arm,cortex-a53-pmu"; - interrupt-parent = <&local_intc>; - interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupt-parent = <&local_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_HIGH>, // PHYS_SECURE_PPI - <1 IRQ_TYPE_LEVEL_HIGH>, // PHYS_NONSECURE_PPI - <3 IRQ_TYPE_LEVEL_HIGH>, // VIRT_PPI - <2 IRQ_TYPE_LEVEL_HIGH>; // HYP_PPI - always-on; - }; - - cpus: cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0>; - enable-method = "spin-table"; - cpu-release-addr = <0x0 0x000000d8>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <1>; - enable-method = "spin-table"; - cpu-release-addr = <0x0 0x000000e0>; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <2>; - enable-method = "spin-table"; - cpu-release-addr = <0x0 0x000000e8>; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <3>; - enable-method = "spin-table"; - cpu-release-addr = <0x0 0x000000f0>; - }; - }; -}; - -/* Make the BCM2835-style global interrupt controller be a child of the - * CPU-local interrupt controller. - */ -&intc { - compatible = "brcm,bcm2836-armctrl-ic"; - reg = <0x7e00b200 0x200>; - interrupt-parent = <&local_intc>; - interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; -}; - -&cpu_thermal { - coefficients = <(-538) 412000>; -}; - -/* enable thermal sensor with the correct compatible property set */ -&thermal { - compatible = "brcm,bcm2837-thermal"; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/bcm283x-rpi-lan7515.dtsi b/sys/gnu/dts/arm/bcm283x-rpi-lan7515.dtsi deleted file mode 100644 index 70bece63f9a..00000000000 --- a/sys/gnu/dts/arm/bcm283x-rpi-lan7515.dtsi +++ /dev/null @@ -1,41 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include - -/ { - aliases { - ethernet0 = ðernet; - }; -}; - -&usb { - usb-port@1 { - compatible = "usb424,2514"; - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - usb-port@1 { - compatible = "usb424,2514"; - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - ethernet: ethernet@1 { - compatible = "usb424,7800"; - reg = <1>; - - mdio { - #address-cells = <0x1>; - #size-cells = <0x0>; - eth_phy: ethernet-phy@1 { - reg = <1>; - microchip,led-modes = < - LAN78XX_LINK_1000_ACTIVITY - LAN78XX_LINK_10_100_ACTIVITY - >; - }; - }; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/bcm283x-rpi-smsc9512.dtsi b/sys/gnu/dts/arm/bcm283x-rpi-smsc9512.dtsi deleted file mode 100644 index 967e081cb9c..00000000000 --- a/sys/gnu/dts/arm/bcm283x-rpi-smsc9512.dtsi +++ /dev/null @@ -1,20 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/ { - aliases { - ethernet0 = ðernet; - }; -}; - -&usb { - usb1@1 { - compatible = "usb424,9512"; - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - ethernet: usbether@1 { - compatible = "usb424,ec00"; - reg = <1>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/bcm283x-rpi-smsc9514.dtsi b/sys/gnu/dts/arm/bcm283x-rpi-smsc9514.dtsi deleted file mode 100644 index dc7ae776db5..00000000000 --- a/sys/gnu/dts/arm/bcm283x-rpi-smsc9514.dtsi +++ /dev/null @@ -1,19 +0,0 @@ -/ { - aliases { - ethernet0 = ðernet; - }; -}; - -&usb { - usb1@1 { - compatible = "usb424,9514"; - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - ethernet: usbether@1 { - compatible = "usb424,ec00"; - reg = <1>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/bcm283x-rpi-usb-host.dtsi b/sys/gnu/dts/arm/bcm283x-rpi-usb-host.dtsi deleted file mode 100644 index 73f4ece8dcd..00000000000 --- a/sys/gnu/dts/arm/bcm283x-rpi-usb-host.dtsi +++ /dev/null @@ -1,3 +0,0 @@ -&usb { - dr_mode = "host"; -}; diff --git a/sys/gnu/dts/arm/bcm283x-rpi-usb-otg.dtsi b/sys/gnu/dts/arm/bcm283x-rpi-usb-otg.dtsi deleted file mode 100644 index e2fd9610e12..00000000000 --- a/sys/gnu/dts/arm/bcm283x-rpi-usb-otg.dtsi +++ /dev/null @@ -1,11 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -&usb { - dr_mode = "otg"; - g-rx-fifo-size = <256>; - g-np-tx-fifo-size = <32>; - /* - * According to dwc2 the sum of all device EP - * fifo sizes shouldn't exceed 3776 bytes. - */ - g-tx-fifo-size = <256 256 512 512 512 768 768>; -}; diff --git a/sys/gnu/dts/arm/bcm283x-rpi-usb-peripheral.dtsi b/sys/gnu/dts/arm/bcm283x-rpi-usb-peripheral.dtsi deleted file mode 100644 index 0ff0e9e2532..00000000000 --- a/sys/gnu/dts/arm/bcm283x-rpi-usb-peripheral.dtsi +++ /dev/null @@ -1,7 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -&usb { - dr_mode = "peripheral"; - g-rx-fifo-size = <256>; - g-np-tx-fifo-size = <32>; - g-tx-fifo-size = <256 256 512 512 512 768 768>; -}; diff --git a/sys/gnu/dts/arm/bcm283x.dtsi b/sys/gnu/dts/arm/bcm283x.dtsi deleted file mode 100644 index e1abe8c730c..00000000000 --- a/sys/gnu/dts/arm/bcm283x.dtsi +++ /dev/null @@ -1,508 +0,0 @@ -#include -#include -#include -#include -#include -#include - -/* firmware-provided startup stubs live here, where the secondary CPUs are - * spinning. - */ -/memreserve/ 0x00000000 0x00001000; - -/* This include file covers the common peripherals and configuration between - * bcm2835 and bcm2836 implementations, leaving the CPU configuration to - * bcm2835.dtsi and bcm2836.dtsi. - */ - -/ { - compatible = "brcm,bcm2835"; - model = "BCM2835"; - #address-cells = <1>; - #size-cells = <1>; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - rmem: reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - cma: linux,cma { - compatible = "shared-dma-pool"; - size = <0x4000000>; /* 64MB */ - reusable; - linux,cma-default; - }; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <0>; - polling-delay = <1000>; - - trips { - cpu-crit { - temperature = <90000>; - hysteresis = <0>; - type = "critical"; - }; - }; - - cooling-maps { - }; - }; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - - system_timer: timer@7e003000 { - compatible = "brcm,bcm2835-system-timer"; - reg = <0x7e003000 0x1000>; - interrupts = <1 0>, <1 1>, <1 2>, <1 3>; - /* This could be a reference to BCM2835_CLOCK_TIMER, - * but we don't have the driver using the common clock - * support yet. - */ - clock-frequency = <1000000>; - }; - - txp: txp@7e004000 { - compatible = "brcm,bcm2835-txp"; - reg = <0x7e004000 0x20>; - interrupts = <1 11>; - }; - - clocks: cprman@7e101000 { - compatible = "brcm,bcm2835-cprman"; - #clock-cells = <1>; - reg = <0x7e101000 0x2000>; - - /* CPRMAN derives almost everything from the - * platform's oscillator. However, the DSI - * pixel clocks come from the DSI analog PHY. - */ - clocks = <&clk_osc>, - <&dsi0 0>, <&dsi0 1>, <&dsi0 2>, - <&dsi1 0>, <&dsi1 1>, <&dsi1 2>; - }; - - mailbox: mailbox@7e00b880 { - compatible = "brcm,bcm2835-mbox"; - reg = <0x7e00b880 0x40>; - interrupts = <0 1>; - #mbox-cells = <0>; - }; - - gpio: gpio@7e200000 { - compatible = "brcm,bcm2835-gpio"; - reg = <0x7e200000 0xb4>; - /* - * The GPIO IP block is designed for 3 banks of GPIOs. - * Each bank has a GPIO interrupt for itself. - * There is an overall "any bank" interrupt. - * In order, these are GIC interrupts 17, 18, 19, 20. - * Since the BCM2835 only has 2 banks, the 2nd bank - * interrupt output appears to be mirrored onto the - * 3rd bank's interrupt signal. - * So, a bank0 interrupt shows up on 17, 20, and - * a bank1 interrupt shows up on 18, 19, 20! - */ - interrupts = <2 17>, <2 18>, <2 19>, <2 20>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - - /* Defines common pin muxing groups - * - * While each pin can have its mux selected - * for various functions individually, some - * groups only make sense to switch to a - * particular function together. - */ - dpi_gpio0: dpi_gpio0 { - brcm,pins = <0 1 2 3 4 5 6 7 8 9 10 11 - 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27>; - brcm,function = ; - }; - emmc_gpio22: emmc_gpio22 { - brcm,pins = <22 23 24 25 26 27>; - brcm,function = ; - }; - emmc_gpio34: emmc_gpio34 { - brcm,pins = <34 35 36 37 38 39>; - brcm,function = ; - brcm,pull = ; - }; - emmc_gpio48: emmc_gpio48 { - brcm,pins = <48 49 50 51 52 53>; - brcm,function = ; - }; - - gpclk0_gpio4: gpclk0_gpio4 { - brcm,pins = <4>; - brcm,function = ; - }; - gpclk1_gpio5: gpclk1_gpio5 { - brcm,pins = <5>; - brcm,function = ; - }; - gpclk1_gpio42: gpclk1_gpio42 { - brcm,pins = <42>; - brcm,function = ; - }; - gpclk1_gpio44: gpclk1_gpio44 { - brcm,pins = <44>; - brcm,function = ; - }; - gpclk2_gpio6: gpclk2_gpio6 { - brcm,pins = <6>; - brcm,function = ; - }; - gpclk2_gpio43: gpclk2_gpio43 { - brcm,pins = <43>; - brcm,function = ; - brcm,pull = ; - }; - - i2c0_gpio0: i2c0_gpio0 { - brcm,pins = <0 1>; - brcm,function = ; - }; - i2c0_gpio28: i2c0_gpio28 { - brcm,pins = <28 29>; - brcm,function = ; - }; - i2c0_gpio44: i2c0_gpio44 { - brcm,pins = <44 45>; - brcm,function = ; - }; - i2c1_gpio2: i2c1_gpio2 { - brcm,pins = <2 3>; - brcm,function = ; - }; - i2c1_gpio44: i2c1_gpio44 { - brcm,pins = <44 45>; - brcm,function = ; - }; - - jtag_gpio22: jtag_gpio22 { - brcm,pins = <22 23 24 25 26 27>; - brcm,function = ; - }; - - pcm_gpio18: pcm_gpio18 { - brcm,pins = <18 19 20 21>; - brcm,function = ; - }; - pcm_gpio28: pcm_gpio28 { - brcm,pins = <28 29 30 31>; - brcm,function = ; - }; - - sdhost_gpio48: sdhost_gpio48 { - brcm,pins = <48 49 50 51 52 53>; - brcm,function = ; - }; - - spi0_gpio7: spi0_gpio7 { - brcm,pins = <7 8 9 10 11>; - brcm,function = ; - }; - spi0_gpio35: spi0_gpio35 { - brcm,pins = <35 36 37 38 39>; - brcm,function = ; - }; - spi1_gpio16: spi1_gpio16 { - brcm,pins = <16 17 18 19 20 21>; - brcm,function = ; - }; - spi2_gpio40: spi2_gpio40 { - brcm,pins = <40 41 42 43 44 45>; - brcm,function = ; - }; - - uart0_gpio14: uart0_gpio14 { - brcm,pins = <14 15>; - brcm,function = ; - }; - /* Separate from the uart0_gpio14 group - * because it conflicts with spi1_gpio16, and - * people often run uart0 on the two pins - * without flow control. - */ - uart0_ctsrts_gpio16: uart0_ctsrts_gpio16 { - brcm,pins = <16 17>; - brcm,function = ; - }; - uart0_ctsrts_gpio30: uart0_ctsrts_gpio30 { - brcm,pins = <30 31>; - brcm,function = ; - brcm,pull = ; - }; - uart0_gpio32: uart0_gpio32 { - brcm,pins = <32 33>; - brcm,function = ; - brcm,pull = ; - }; - uart0_gpio36: uart0_gpio36 { - brcm,pins = <36 37>; - brcm,function = ; - }; - uart0_ctsrts_gpio38: uart0_ctsrts_gpio38 { - brcm,pins = <38 39>; - brcm,function = ; - }; - - uart1_gpio14: uart1_gpio14 { - brcm,pins = <14 15>; - brcm,function = ; - }; - uart1_ctsrts_gpio16: uart1_ctsrts_gpio16 { - brcm,pins = <16 17>; - brcm,function = ; - }; - uart1_gpio32: uart1_gpio32 { - brcm,pins = <32 33>; - brcm,function = ; - }; - uart1_ctsrts_gpio30: uart1_ctsrts_gpio30 { - brcm,pins = <30 31>; - brcm,function = ; - }; - uart1_gpio40: uart1_gpio40 { - brcm,pins = <40 41>; - brcm,function = ; - }; - uart1_ctsrts_gpio42: uart1_ctsrts_gpio42 { - brcm,pins = <42 43>; - brcm,function = ; - }; - }; - - uart0: serial@7e201000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x7e201000 0x200>; - interrupts = <2 25>; - clocks = <&clocks BCM2835_CLOCK_UART>, - <&clocks BCM2835_CLOCK_VPU>; - clock-names = "uartclk", "apb_pclk"; - arm,primecell-periphid = <0x00241011>; - }; - - sdhost: mmc@7e202000 { - compatible = "brcm,bcm2835-sdhost"; - reg = <0x7e202000 0x100>; - interrupts = <2 24>; - clocks = <&clocks BCM2835_CLOCK_VPU>; - status = "disabled"; - }; - - i2s: i2s@7e203000 { - compatible = "brcm,bcm2835-i2s"; - reg = <0x7e203000 0x24>; - clocks = <&clocks BCM2835_CLOCK_PCM>; - status = "disabled"; - }; - - spi: spi@7e204000 { - compatible = "brcm,bcm2835-spi"; - reg = <0x7e204000 0x200>; - interrupts = <2 22>; - clocks = <&clocks BCM2835_CLOCK_VPU>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c0: i2c@7e205000 { - compatible = "brcm,bcm2835-i2c"; - reg = <0x7e205000 0x200>; - interrupts = <2 21>; - clocks = <&clocks BCM2835_CLOCK_VPU>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - dpi: dpi@7e208000 { - compatible = "brcm,bcm2835-dpi"; - reg = <0x7e208000 0x8c>; - clocks = <&clocks BCM2835_CLOCK_VPU>, - <&clocks BCM2835_CLOCK_DPI>; - clock-names = "core", "pixel"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - dsi0: dsi@7e209000 { - compatible = "brcm,bcm2835-dsi0"; - reg = <0x7e209000 0x78>; - interrupts = <2 4>; - #address-cells = <1>; - #size-cells = <0>; - #clock-cells = <1>; - - clocks = <&clocks BCM2835_PLLA_DSI0>, - <&clocks BCM2835_CLOCK_DSI0E>, - <&clocks BCM2835_CLOCK_DSI0P>; - clock-names = "phy", "escape", "pixel"; - - clock-output-names = "dsi0_byte", - "dsi0_ddr2", - "dsi0_ddr"; - - }; - - aux: aux@7e215000 { - compatible = "brcm,bcm2835-aux"; - #clock-cells = <1>; - reg = <0x7e215000 0x8>; - clocks = <&clocks BCM2835_CLOCK_VPU>; - }; - - uart1: serial@7e215040 { - compatible = "brcm,bcm2835-aux-uart"; - reg = <0x7e215040 0x40>; - interrupts = <1 29>; - clocks = <&aux BCM2835_AUX_CLOCK_UART>; - status = "disabled"; - }; - - spi1: spi@7e215080 { - compatible = "brcm,bcm2835-aux-spi"; - reg = <0x7e215080 0x40>; - interrupts = <1 29>; - clocks = <&aux BCM2835_AUX_CLOCK_SPI1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi2: spi@7e2150c0 { - compatible = "brcm,bcm2835-aux-spi"; - reg = <0x7e2150c0 0x40>; - interrupts = <1 29>; - clocks = <&aux BCM2835_AUX_CLOCK_SPI2>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - pwm: pwm@7e20c000 { - compatible = "brcm,bcm2835-pwm"; - reg = <0x7e20c000 0x28>; - clocks = <&clocks BCM2835_CLOCK_PWM>; - assigned-clocks = <&clocks BCM2835_CLOCK_PWM>; - assigned-clock-rates = <10000000>; - #pwm-cells = <2>; - status = "disabled"; - }; - - sdhci: sdhci@7e300000 { - compatible = "brcm,bcm2835-sdhci"; - reg = <0x7e300000 0x100>; - interrupts = <2 30>; - clocks = <&clocks BCM2835_CLOCK_EMMC>; - status = "disabled"; - }; - - hvs@7e400000 { - compatible = "brcm,bcm2835-hvs"; - reg = <0x7e400000 0x6000>; - interrupts = <2 1>; - }; - - dsi1: dsi@7e700000 { - compatible = "brcm,bcm2835-dsi1"; - reg = <0x7e700000 0x8c>; - interrupts = <2 12>; - #address-cells = <1>; - #size-cells = <0>; - #clock-cells = <1>; - - clocks = <&clocks BCM2835_PLLD_DSI1>, - <&clocks BCM2835_CLOCK_DSI1E>, - <&clocks BCM2835_CLOCK_DSI1P>; - clock-names = "phy", "escape", "pixel"; - - clock-output-names = "dsi1_byte", - "dsi1_ddr2", - "dsi1_ddr"; - - status = "disabled"; - }; - - i2c1: i2c@7e804000 { - compatible = "brcm,bcm2835-i2c"; - reg = <0x7e804000 0x1000>; - interrupts = <2 21>; - clocks = <&clocks BCM2835_CLOCK_VPU>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - vec: vec@7e806000 { - compatible = "brcm,bcm2835-vec"; - reg = <0x7e806000 0x1000>; - clocks = <&clocks BCM2835_CLOCK_VEC>; - interrupts = <2 27>; - status = "disabled"; - }; - - usb: usb@7e980000 { - compatible = "brcm,bcm2835-usb"; - reg = <0x7e980000 0x10000>; - interrupts = <1 9>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clk_usb>; - clock-names = "otg"; - phys = <&usbphy>; - phy-names = "usb2-phy"; - }; - }; - - clocks { - /* The oscillator is the root of the clock tree. */ - clk_osc: clk-osc { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-output-names = "osc"; - clock-frequency = <19200000>; - }; - - clk_usb: clk-usb { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-output-names = "otg"; - clock-frequency = <480000000>; - }; - }; - - usbphy: phy { - compatible = "usb-nop-xceiv"; - #phy-cells = <0>; - }; -}; diff --git a/sys/gnu/dts/arm/bcm4708-asus-rt-ac56u.dts b/sys/gnu/dts/arm/bcm4708-asus-rt-ac56u.dts deleted file mode 100644 index 6a96655d862..00000000000 --- a/sys/gnu/dts/arm/bcm4708-asus-rt-ac56u.dts +++ /dev/null @@ -1,95 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Broadcom BCM470X / BCM5301X ARM platform code. - * DTS for Asus RT-AC56U - * - * Copyright (C) 2015 Rafał Miłecki - */ - -/dts-v1/; - -#include "bcm4708.dtsi" -#include "bcm5301x-nand-cs0-bch8.dtsi" - -/ { - compatible = "asus,rt-ac56u", "brcm,bcm4708"; - model = "Asus RT-AC56U (BCM4708)"; - - chosen { - bootargs = "console=ttyS0,115200"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x08000000 - 0x88000000 0x08000000>; - }; - - leds { - compatible = "gpio-leds"; - - usb3 { - label = "bcm53xx:blue:usb3"; - gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; - }; - - wan { - label = "bcm53xx:blue:wan"; - gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>; - }; - - lan { - label = "bcm53xx:blue:lan"; - gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; - }; - - power { - label = "bcm53xx:blue:power"; - gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-on"; - }; - - all { - label = "bcm53xx:blue:all"; - gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-on"; - }; - - 2ghz { - label = "bcm53xx:blue:2ghz"; - gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>; - }; - - - usb2 { - label = "bcm53xx:blue:usb2"; - gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - rfkill { - label = "WiFi"; - linux,code = ; - gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; - }; - - restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; - }; - - wps { - label = "WPS"; - linux,code = ; - gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&usb3_phy { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/bcm4708-asus-rt-ac68u.dts b/sys/gnu/dts/arm/bcm4708-asus-rt-ac68u.dts deleted file mode 100644 index 3b0029e61b4..00000000000 --- a/sys/gnu/dts/arm/bcm4708-asus-rt-ac68u.dts +++ /dev/null @@ -1,85 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Broadcom BCM470X / BCM5301X ARM platform code. - * DTS for Asus RT-AC68U - * - * Copyright (C) 2015 Rafał Miłecki - */ - -/dts-v1/; - -#include "bcm4708.dtsi" -#include "bcm5301x-nand-cs0-bch8.dtsi" - -/ { - compatible = "asus,rt-ac68u", "brcm,bcm4708"; - model = "Asus RT-AC68U (BCM4708)"; - - chosen { - bootargs = "console=ttyS0,115200"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x08000000 - 0x88000000 0x08000000>; - }; - - leds { - compatible = "gpio-leds"; - - usb2 { - label = "bcm53xx:blue:usb2"; - gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; - }; - - power { - label = "bcm53xx:blue:power"; - gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-on"; - }; - - logo { - label = "bcm53xx:white:logo"; - gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-on"; - }; - - usb3 { - label = "bcm53xx:blue:usb3"; - gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - brightness { - label = "Backlight"; - linux,code = ; - gpios = <&chipcommon 5 GPIO_ACTIVE_LOW>; - }; - - wps { - label = "WPS"; - linux,code = ; - gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; - }; - - restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; - }; - - rfkill { - label = "WiFi"; - linux,code = ; - gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&usb3_phy { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/bcm4708-buffalo-wzr-1750dhp.dts b/sys/gnu/dts/arm/bcm4708-buffalo-wzr-1750dhp.dts deleted file mode 100644 index 90f57bad6b2..00000000000 --- a/sys/gnu/dts/arm/bcm4708-buffalo-wzr-1750dhp.dts +++ /dev/null @@ -1,151 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Broadcom BCM470X / BCM5301X ARM platform code. - * DTS for Buffalo WZR-1750DHP - * - * Copyright (C) 2014 Rafał Miłecki - */ - -/dts-v1/; - -#include "bcm4708.dtsi" -#include "bcm5301x-nand-cs0-bch8.dtsi" - -/ { - compatible = "buffalo,wzr-1750dhp", "brcm,bcm4708"; - model = "Buffalo WZR-1750DHP (BCM4708)"; - - chosen { - bootargs = "console=ttyS0,115200 earlycon"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x08000000 - 0x88000000 0x18000000>; - }; - - spi { - compatible = "spi-gpio"; - num-chipselects = <1>; - gpio-sck = <&chipcommon 7 0>; - gpio-mosi = <&chipcommon 4 0>; - cs-gpios = <&chipcommon 6 0>; - #address-cells = <1>; - #size-cells = <0>; - - hc595: gpio_spi@0 { - compatible = "fairchild,74hc595"; - reg = <0>; - registers-number = <1>; - spi-max-frequency = <100000>; - - gpio-controller; - #gpio-cells = <2>; - - }; - }; - - leds { - compatible = "gpio-leds"; - - usb { - label = "bcm53xx:blue:usb"; - gpios = <&hc595 0 GPIO_ACTIVE_HIGH>; - trigger-sources = <&ohci_port1>, <&ehci_port1>, - <&xhci_port1>, <&ohci_port2>, - <&ehci_port2>; - linux,default-trigger = "usbport"; - }; - - power0 { - label = "bcm53xx:red:power"; - gpios = <&hc595 1 GPIO_ACTIVE_HIGH>; - }; - - power1 { - label = "bcm53xx:white:power"; - gpios = <&hc595 2 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - }; - - router0 { - label = "bcm53xx:blue:router"; - gpios = <&hc595 3 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - }; - - router1 { - label = "bcm53xx:amber:router"; - gpios = <&hc595 4 GPIO_ACTIVE_HIGH>; - }; - - wan { - label = "bcm53xx:blue:wan"; - gpios = <&hc595 5 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - }; - - wireless0 { - label = "bcm53xx:blue:wireless"; - gpios = <&hc595 6 GPIO_ACTIVE_HIGH>; - }; - - wireless1 { - label = "bcm53xx:amber:wireless"; - gpios = <&hc595 7 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; - }; - - aoss { - label = "AOSS"; - linux,code = ; - gpios = <&chipcommon 12 GPIO_ACTIVE_LOW>; - }; - - /* Commit mode set by switch? */ - mode { - label = "Mode"; - linux,code = ; - gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; - }; - - /* Switch: AP mode */ - sw_ap { - label = "AP"; - linux,code = ; - gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; - }; - - eject { - label = "USB eject"; - linux,code = ; - gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&usb2 { - vcc-gpio = <&chipcommon 9 GPIO_ACTIVE_HIGH>; -}; - -&usb3 { - vcc-gpio = <&chipcommon 10 GPIO_ACTIVE_LOW>; -}; - -&spi_nor { - status = "okay"; -}; - -&usb3_phy { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/bcm4708-linksys-ea6300-v1.dts b/sys/gnu/dts/arm/bcm4708-linksys-ea6300-v1.dts deleted file mode 100644 index 41548d6d479..00000000000 --- a/sys/gnu/dts/arm/bcm4708-linksys-ea6300-v1.dts +++ /dev/null @@ -1,43 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright (C) 2017 Rafał Miłecki - */ - -/dts-v1/; - -#include "bcm4708.dtsi" -#include "bcm5301x-nand-cs0-bch8.dtsi" - -/ { - compatible = "linksys,ea6300-v1", "brcm,bcm4708"; - model = "Linksys EA6300 V1"; - - chosen { - bootargs = "console=ttyS0,115200"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x08000000>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - wps { - label = "WPS"; - linux,code = ; - gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; - }; - - restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&usb3_phy { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/bcm4708-linksys-ea6500-v2.dts b/sys/gnu/dts/arm/bcm4708-linksys-ea6500-v2.dts deleted file mode 100644 index cd797b4202a..00000000000 --- a/sys/gnu/dts/arm/bcm4708-linksys-ea6500-v2.dts +++ /dev/null @@ -1,44 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright (C) 2017 Rafał Miłecki - * Copyright (C) 2018 Rene Kjellerup - */ - -/dts-v1/; - -#include "bcm4708.dtsi" -#include "bcm5301x-nand-cs0-bch8.dtsi" - -/ { - compatible = "linksys,ea6500-v2", "brcm,bcm4708"; - model = "Linksys EA6500 V2"; - - chosen { - bootargs = "console=ttyS0,115200"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x08000000>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - wps { - label = "WPS"; - linux,code = ; - gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; - }; - - restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&usb3_phy { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/bcm4708-luxul-xap-1510.dts b/sys/gnu/dts/arm/bcm4708-luxul-xap-1510.dts deleted file mode 100644 index e58c8077be1..00000000000 --- a/sys/gnu/dts/arm/bcm4708-luxul-xap-1510.dts +++ /dev/null @@ -1,62 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2016 Luxul Inc. - */ - -/dts-v1/; - -#include "bcm4708.dtsi" - -/ { - compatible = "luxul,xap-1510v1", "brcm,bcm4708"; - model = "Luxul XAP-1510 V1"; - - chosen { - bootargs = "console=ttyS0,115200 earlycon"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x08000000>; - }; - - leds { - compatible = "gpio-leds"; - - 5ghz { - label = "bcm53xx:blue:5ghz"; - gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; - linux,default-trigger = "none"; - }; - - 2ghz { - label = "bcm53xx:blue:2ghz"; - gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; - linux,default-trigger = "none"; - }; - - status { - label = "bcm53xx:green:status"; - gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; - linux,default-trigger = "timer"; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&spi_nor { - status = "okay"; -}; - -&usb3_phy { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/bcm4708-luxul-xwc-1000.dts b/sys/gnu/dts/arm/bcm4708-luxul-xwc-1000.dts deleted file mode 100644 index 766db617455..00000000000 --- a/sys/gnu/dts/arm/bcm4708-luxul-xwc-1000.dts +++ /dev/null @@ -1,69 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Broadcom BCM470X / BCM5301X ARM platform code. - * DTS for Luxul XWC-1000 - * - * Copyright 2014 Luxul Inc. - */ - -/dts-v1/; - -#include "bcm4708.dtsi" -#include "bcm5301x-nand-cs0-bch8.dtsi" - -/ { - compatible = "luxul,xwc-1000", "brcm,bcm4708"; - model = "Luxul XWC-1000 (BCM4708)"; - - chosen { - bootargs = "console=ttyS0,115200 earlycon"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x08000000>; - }; - - nand: nand@18028000 { - nandcs@0 { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "ubi"; - reg = <0x00000000 0x08000000>; - }; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - status { - label = "bcm53xx:green:status"; - gpios = <&chipcommon 0 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "timer"; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&spi_nor { - status = "okay"; -}; - -&usb3_phy { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/bcm4708-netgear-r6250.dts b/sys/gnu/dts/arm/bcm4708-netgear-r6250.dts deleted file mode 100644 index fed75e6ab58..00000000000 --- a/sys/gnu/dts/arm/bcm4708-netgear-r6250.dts +++ /dev/null @@ -1,96 +0,0 @@ -/* - * Broadcom BCM470X / BCM5301X arm platform code. - * DTS for Netgear R6250 V1 - * - * Copyright 2013 Hauke Mehrtens - * - * Licensed under the GNU/GPL. See COPYING for details. - */ - -/dts-v1/; - -#include "bcm4708.dtsi" -#include "bcm5301x-nand-cs0-bch8.dtsi" - -/ { - compatible = "netgear,r6250v1", "brcm,bcm4708"; - model = "Netgear R6250 V1 (BCM4708)"; - - chosen { - bootargs = "console=ttyS0,115200 earlycon"; - }; - - memory { - device_type = "memory"; - reg = <0x00000000 0x08000000 - 0x88000000 0x08000000>; - }; - - leds { - compatible = "gpio-leds"; - - logo { - label = "bcm53xx:white:logo"; - gpios = <&chipcommon 1 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - }; - - power0 { - label = "bcm53xx:green:power"; - gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-on"; - }; - - power1 { - label = "bcm53xx:amber:power"; - gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; - }; - - usb { - label = "bcm53xx:blue:usb"; - gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>; - trigger-sources = <&ohci_port1>, <&ehci_port1>, - <&xhci_port1>; - linux,default-trigger = "usbport"; - }; - - wireless { - label = "bcm53xx:blue:wireless"; - gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - wps { - label = "WPS"; - linux,code = ; - gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; - }; - - rfkill { - label = "WiFi"; - linux,code = ; - gpios = <&chipcommon 5 GPIO_ACTIVE_LOW>; - }; - - restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&usb3 { - vcc-gpio = <&chipcommon 0 GPIO_ACTIVE_HIGH>; -}; - -&spi_nor { - status = "okay"; -}; - -&usb3_phy { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/bcm4708-netgear-r6300-v2.dts b/sys/gnu/dts/arm/bcm4708-netgear-r6300-v2.dts deleted file mode 100644 index 79542e18915..00000000000 --- a/sys/gnu/dts/arm/bcm4708-netgear-r6300-v2.dts +++ /dev/null @@ -1,88 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Broadcom BCM470X / BCM5301X ARM platform code. - * DTS for Netgear R6300 V2 - * - * Copyright (C) 2014 Rafał Miłecki - */ - -/dts-v1/; - -#include "bcm4708.dtsi" -#include "bcm5301x-nand-cs0-bch8.dtsi" - -/ { - compatible = "netgear,r6300v2", "brcm,bcm4708"; - model = "Netgear R6300 V2 (BCM4708)"; - - chosen { - bootargs = "console=ttyS0,115200"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x08000000 - 0x88000000 0x08000000>; - }; - - leds { - compatible = "gpio-leds"; - - logo { - label = "bcm53xx:white:logo"; - gpios = <&chipcommon 1 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - }; - - power0 { - label = "bcm53xx:green:power"; - gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; - }; - - power1 { - label = "bcm53xx:amber:power"; - gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-on"; - }; - - usb { - label = "bcm53xx:blue:usb"; - gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>; - }; - - wireless { - label = "bcm53xx:blue:wireless"; - gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - wps { - label = "WPS"; - linux,code = ; - gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; - }; - - rfkill { - label = "WiFi"; - linux,code = ; - gpios = <&chipcommon 5 GPIO_ACTIVE_LOW>; - }; - - restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&spi_nor { - status = "okay"; -}; - -&usb3_phy { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/bcm4708-smartrg-sr400ac.dts b/sys/gnu/dts/arm/bcm4708-smartrg-sr400ac.dts deleted file mode 100644 index abd35a51804..00000000000 --- a/sys/gnu/dts/arm/bcm4708-smartrg-sr400ac.dts +++ /dev/null @@ -1,163 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Broadcom BCM470X / BCM5301X arm platform code. - * DTS for SmartRG SR400ac - * - * Copyright (C) 2015 Rafał Miłecki - */ - -/dts-v1/; - -#include "bcm4708.dtsi" -#include "bcm5301x-nand-cs0-bch8.dtsi" - -/ { - compatible = "smartrg,sr400ac", "brcm,bcm4708"; - model = "SmartRG SR400ac"; - - chosen { - bootargs = "console=ttyS0,115200 earlycon"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x08000000 - 0x88000000 0x08000000>; - }; - - leds { - compatible = "gpio-leds"; - - power-white { - label = "bcm53xx:white:power"; - gpios = <&chipcommon 1 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - }; - - power-amber { - label = "bcm53xx:amber:power"; - gpios = <&chipcommon 2 GPIO_ACTIVE_HIGH>; - }; - - usb2 { - label = "bcm53xx:white:usb2"; - gpios = <&chipcommon 3 GPIO_ACTIVE_HIGH>; - trigger-sources = <&ohci_port2>, <&ehci_port2>; - linux,default-trigger = "usbport"; - }; - - usb3-white { - label = "bcm53xx:white:usb3"; - gpios = <&chipcommon 4 GPIO_ACTIVE_HIGH>; - trigger-sources = <&xhci_port1>; - linux,default-trigger = "usbport"; - }; - - usb3-green { - label = "bcm53xx:green:usb3"; - gpios = <&chipcommon 5 GPIO_ACTIVE_HIGH>; - trigger-sources = <&ohci_port1>, <&ehci_port1>; - linux,default-trigger = "usbport"; - }; - - wps { - label = "bcm53xx:white:wps"; - gpios = <&chipcommon 6 GPIO_ACTIVE_HIGH>; - }; - - status-red { - label = "bcm53xx:red:status"; - gpios = <&chipcommon 8 GPIO_ACTIVE_HIGH>; - }; - - status-green { - label = "bcm53xx:green:status"; - gpios = <&chipcommon 9 GPIO_ACTIVE_HIGH>; - }; - - status-blue { - label = "bcm53xx:blue:status"; - gpios = <&chipcommon 10 GPIO_ACTIVE_HIGH>; - }; - - wan-white { - label = "bcm53xx:white:wan"; - gpios = <&chipcommon 12 GPIO_ACTIVE_HIGH>; - }; - - wan-red { - label = "bcm53xx:red:wan"; - gpios = <&chipcommon 13 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - rfkill { - label = "WiFi"; - linux,code = ; - gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; - }; - - wps { - label = "WPS"; - linux,code = ; - gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; - }; - - restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&spi_nor { - status = "okay"; -}; - -&srab { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "lan4"; - }; - - port@1 { - reg = <1>; - label = "lan3"; - }; - - port@2 { - reg = <2>; - label = "lan2"; - }; - - port@3 { - reg = <3>; - label = "lan1"; - }; - - port@4 { - reg = <4>; - label = "wan"; - }; - - port@5 { - reg = <5>; - label = "cpu"; - ethernet = <&gmac0>; - }; - }; -}; - -&usb3_phy { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/bcm4708.dtsi b/sys/gnu/dts/arm/bcm4708.dtsi deleted file mode 100644 index 1a19e97a987..00000000000 --- a/sys/gnu/dts/arm/bcm4708.dtsi +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Broadcom BCM470X / BCM5301X ARM platform code. - * DTS for BCM4708 SoC. - * - * Copyright 2013-2014 Hauke Mehrtens - * - * Licensed under the GNU/GPL. See COPYING for details. - */ - -#include "bcm5301x.dtsi" - -/ { - compatible = "brcm,bcm4708"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "brcm,bcm-nsp-smp"; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - next-level-cache = <&L2>; - reg = <0x0>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - next-level-cache = <&L2>; - secondary-boot-reg = <0xffff0400>; - reg = <0x1>; - }; - }; - -}; - -&uart0 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/bcm47081-asus-rt-n18u.dts b/sys/gnu/dts/arm/bcm47081-asus-rt-n18u.dts deleted file mode 100644 index c29950b43a9..00000000000 --- a/sys/gnu/dts/arm/bcm47081-asus-rt-n18u.dts +++ /dev/null @@ -1,79 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Broadcom BCM470X / BCM5301X ARM platform code. - * DTS for Asus RT-N18U - * - * Copyright (C) 2014 Rafał Miłecki - */ - -/dts-v1/; - -#include "bcm47081.dtsi" -#include "bcm5301x-nand-cs0-bch8.dtsi" - -/ { - compatible = "asus,rt-n18u", "brcm,bcm47081", "brcm,bcm4708"; - model = "Asus RT-N18U (BCM47081)"; - - chosen { - bootargs = "console=ttyS0,115200"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x08000000 - 0x88000000 0x08000000>; - }; - - leds { - compatible = "gpio-leds"; - - power { - label = "bcm53xx:blue:power"; - gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-on"; - }; - - usb2 { - label = "bcm53xx:blue:usb2"; - gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; - }; - - wan { - label = "bcm53xx:blue:wan"; - gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-on"; - }; - - lan { - label = "bcm53xx:blue:lan"; - gpios = <&chipcommon 9 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-on"; - }; - - usb3 { - label = "bcm53xx:blue:usb3"; - gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; - }; - - wps { - label = "WPS"; - linux,code = ; - gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&usb3_phy { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/bcm47081-buffalo-wzr-600dhp2.dts b/sys/gnu/dts/arm/bcm47081-buffalo-wzr-600dhp2.dts deleted file mode 100644 index 4dcec686546..00000000000 --- a/sys/gnu/dts/arm/bcm47081-buffalo-wzr-600dhp2.dts +++ /dev/null @@ -1,123 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Broadcom BCM470X / BCM5301X ARM platform code. - * DTS for Buffalo WZR-600DHP2 - * - * Copyright (C) 2014 Rafał Miłecki - */ - -/dts-v1/; - -#include "bcm47081.dtsi" -#include "bcm5301x-nand-cs0-bch8.dtsi" - -/ { - compatible = "buffalo,wzr-600dhp2", "brcm,bcm47081", "brcm,bcm4708"; - model = "Buffalo WZR-600DHP2 (BCM47081)"; - - chosen { - bootargs = "console=ttyS0,115200 earlycon"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x08000000 - 0x88000000 0x08000000>; - }; - - spi { - compatible = "spi-gpio"; - num-chipselects = <1>; - gpio-sck = <&chipcommon 7 0>; - gpio-mosi = <&chipcommon 4 0>; - cs-gpios = <&chipcommon 6 0>; - #address-cells = <1>; - #size-cells = <0>; - - hc595: gpio_spi@0 { - compatible = "fairchild,74hc595"; - reg = <0>; - registers-number = <1>; - spi-max-frequency = <100000>; - - gpio-controller; - #gpio-cells = <2>; - - }; - }; - - leds { - compatible = "gpio-leds"; - - power0 { - label = "bcm53xx:green:power"; - gpios = <&hc595 1 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - }; - - power1 { - label = "bcm53xx:red:power"; - gpios = <&hc595 2 GPIO_ACTIVE_HIGH>; - }; - - router0 { - label = "bcm53xx:green:router"; - gpios = <&hc595 3 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - }; - - router1 { - label = "bcm53xx:amber:router"; - gpios = <&hc595 4 GPIO_ACTIVE_HIGH>; - }; - - wan { - label = "bcm53xx:green:wan"; - gpios = <&hc595 5 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - }; - - wireless0 { - label = "bcm53xx:green:wireless"; - gpios = <&hc595 6 GPIO_ACTIVE_HIGH>; - }; - - wireless1 { - label = "bcm53xx:amber:wireless"; - gpios = <&hc595 7 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - aoss { - label = "AOSS"; - linux,code = ; - gpios = <&chipcommon 9 GPIO_ACTIVE_LOW>; - }; - - restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; - }; - - /* Switch device mode? */ - mode { - label = "Mode"; - linux,code = ; - gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; - }; - - eject { - label = "USB eject"; - linux,code = ; - gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&usb3_phy { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/bcm47081-buffalo-wzr-900dhp.dts b/sys/gnu/dts/arm/bcm47081-buffalo-wzr-900dhp.dts deleted file mode 100644 index 0e349e39f60..00000000000 --- a/sys/gnu/dts/arm/bcm47081-buffalo-wzr-900dhp.dts +++ /dev/null @@ -1,109 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Broadcom BCM470X / BCM5301X ARM platform code. - * DTS for Buffalo WZR-900DHP - * - * Copyright (C) 2015 Rafał Miłecki - */ - -/dts-v1/; - -#include "bcm47081.dtsi" -#include "bcm5301x-nand-cs0-bch8.dtsi" - -/ { - compatible = "buffalo,wzr-900dhp", "brcm,bcm47081", "brcm,bcm4708"; - model = "Buffalo WZR-900DHP (BCM47081)"; - - chosen { - bootargs = "console=ttyS0,115200"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x08000000 - 0x88000000 0x08000000>; - }; - - spi { - compatible = "spi-gpio"; - num-chipselects = <1>; - gpio-sck = <&chipcommon 7 0>; - gpio-mosi = <&chipcommon 4 0>; - cs-gpios = <&chipcommon 6 0>; - #address-cells = <1>; - #size-cells = <0>; - - hc595: gpio_spi@0 { - compatible = "fairchild,74hc595"; - reg = <0>; - registers-number = <1>; - spi-max-frequency = <100000>; - - gpio-controller; - #gpio-cells = <2>; - - }; - }; - - leds { - compatible = "gpio-leds"; - - usb { - label = "bcm53xx:green:usb"; - gpios = <&hc595 0 GPIO_ACTIVE_HIGH>; - }; - - power0 { - label = "bcm53xx:green:power"; - gpios = <&hc595 1 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - }; - - power1 { - label = "bcm53xx:red:power"; - gpios = <&hc595 2 GPIO_ACTIVE_HIGH>; - }; - - router0 { - label = "bcm53xx:green:router"; - gpios = <&hc595 3 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - }; - - router1 { - label = "bcm53xx:amber:router"; - gpios = <&hc595 4 GPIO_ACTIVE_HIGH>; - }; - - wan { - label = "bcm53xx:green:wan"; - gpios = <&hc595 5 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - }; - - wireless0 { - label = "bcm53xx:green:wireless"; - gpios = <&hc595 6 GPIO_ACTIVE_HIGH>; - }; - - wireless1 { - label = "bcm53xx:amber:wireless"; - gpios = <&hc595 7 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&usb3_phy { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/bcm47081-luxul-xap-1410.dts b/sys/gnu/dts/arm/bcm47081-luxul-xap-1410.dts deleted file mode 100644 index b9d95011637..00000000000 --- a/sys/gnu/dts/arm/bcm47081-luxul-xap-1410.dts +++ /dev/null @@ -1,62 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2017 Luxul Inc. - */ - -/dts-v1/; - -#include "bcm47081.dtsi" - -/ { - compatible = "luxul,xap-1410v1", "brcm,bcm47081", "brcm,bcm4708"; - model = "Luxul XAP-1410 V1"; - - chosen { - bootargs = "console=ttyS0,115200"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x08000000>; - }; - - leds { - compatible = "gpio-leds"; - - 5ghz { - label = "bcm53xx:blue:5ghz"; - gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; - linux,default-trigger = "none"; - }; - - 2ghz { - label = "bcm53xx:blue:2ghz"; - gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; - linux,default-trigger = "none"; - }; - - status { - label = "bcm53xx:green:status"; - gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; - linux,default-trigger = "timer"; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&spi_nor { - status = "okay"; -}; - -&usb3_phy { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/bcm47081-luxul-xwr-1200.dts b/sys/gnu/dts/arm/bcm47081-luxul-xwr-1200.dts deleted file mode 100644 index 0052e1b2413..00000000000 --- a/sys/gnu/dts/arm/bcm47081-luxul-xwr-1200.dts +++ /dev/null @@ -1,110 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2017 Luxul Inc. - */ - -/dts-v1/; - -#include "bcm47081.dtsi" -#include "bcm5301x-nand-cs0-bch4.dtsi" - -/ { - compatible = "luxul,xwr-1200v1", "brcm,bcm47081", "brcm,bcm4708"; - model = "Luxul XWR-1200 V1"; - - chosen { - bootargs = "console=ttyS0,115200"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x08000000>; - }; - - leds { - compatible = "gpio-leds"; - - power { - label = "bcm53xx:green:power"; - gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-on"; - }; - - lan3 { - label = "bcm53xx:green:lan3"; - gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>; - linux,default-trigger = "none"; - }; - - lan4 { - label = "bcm53xx:green:lan4"; - gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; - linux,default-trigger = "none"; - }; - - wan { - label = "bcm53xx:green:wan"; - gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; - linux,default-trigger = "none"; - }; - - lan2 { - label = "bcm53xx:green:lan2"; - gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>; - linux,default-trigger = "none"; - }; - - usb { - label = "bcm53xx:green:usb"; - gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>; - trigger-sources = <&ohci_port2>, <&ehci_port2>; - linux,default-trigger = "usbport"; - }; - - status { - label = "bcm53xx:green:status"; - gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>; - linux,default-trigger = "timer"; - }; - - 2ghz { - label = "bcm53xx:green:2ghz"; - gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; - linux,default-trigger = "none"; - }; - - 5ghz { - label = "bcm53xx:green:5ghz"; - gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; - linux,default-trigger = "none"; - }; - - lan1 { - label = "bcm53xx:green:lan1"; - gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; - linux,default-trigger = "none"; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&usb2 { - vcc-gpio = <&chipcommon 9 GPIO_ACTIVE_HIGH>; -}; - -&spi_nor { - status = "okay"; -}; - -&usb3_phy { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/bcm47081-tplink-archer-c5-v2.dts b/sys/gnu/dts/arm/bcm47081-tplink-archer-c5-v2.dts deleted file mode 100644 index 01c390ed48e..00000000000 --- a/sys/gnu/dts/arm/bcm47081-tplink-archer-c5-v2.dts +++ /dev/null @@ -1,132 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright (C) 2017 Rafał Miłecki - */ - -/dts-v1/; - -#include "bcm47081.dtsi" - -/ { - compatible = "tplink,archer-c5-v2", "brcm,bcm47081", "brcm,bcm4708"; - model = "TP-LINK Archer C5 V2"; - - chosen { - bootargs = "earlycon"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x08000000>; - }; - - leds { - compatible = "gpio-leds"; - - 2ghz { - label = "bcm53xx:green:2ghz"; - gpios = <&chipcommon 0 GPIO_ACTIVE_HIGH>; - }; - - lan { - label = "bcm53xx:green:lan"; - gpios = <&chipcommon 1 GPIO_ACTIVE_HIGH>; - }; - - usb2-port1 { - label = "bcm53xx:green:usb2-port1"; - gpios = <&chipcommon 2 GPIO_ACTIVE_HIGH>; - trigger-sources = <&ohci_port1>, <&ehci_port1>; - linux,default-trigger = "usbport"; - }; - - power { - label = "bcm53xx:green:power"; - gpios = <&chipcommon 4 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - }; - - wan-green { - label = "bcm53xx:green:wan"; - gpios = <&chipcommon 5 GPIO_ACTIVE_HIGH>; - }; - - wps { - label = "bcm53xx:green:wps"; - gpios = <&chipcommon 6 GPIO_ACTIVE_HIGH>; - }; - - wan-amber { - label = "bcm53xx:amber:wan"; - gpios = <&chipcommon 8 GPIO_ACTIVE_HIGH>; - }; - - 5ghz { - label = "bcm53xx:green:5ghz"; - gpios = <&chipcommon 12 GPIO_ACTIVE_HIGH>; - }; - - usb2-port2 { - label = "bcm53xx:green:usb2-port2"; - gpios = <&chipcommon 13 GPIO_ACTIVE_HIGH>; - trigger-sources = <&ohci_port2>, <&ehci_port2>; - linux,default-trigger = "usbport"; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - rfkill { - label = "WiFi"; - linux,code = ; - gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; - }; - - restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&spi_nor { - status = "okay"; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot@0 { - label = "boot"; - reg = <0x000000 0x040000>; - read-only; - }; - - os-image@100000 { - label = "os-image"; - reg = <0x040000 0x200000>; - compatible = "brcm,trx"; - }; - - rootfs@240000 { - label = "rootfs"; - reg = <0x240000 0xc00000>; - }; - - nvram@ff0000 { - label = "nvram"; - reg = <0xff0000 0x010000>; - }; - }; -}; - -&usb2 { - vcc-gpio = <&chipcommon 9 GPIO_ACTIVE_HIGH>; -}; - -&usb3_phy { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/bcm47081.dtsi b/sys/gnu/dts/arm/bcm47081.dtsi deleted file mode 100644 index ed13af02852..00000000000 --- a/sys/gnu/dts/arm/bcm47081.dtsi +++ /dev/null @@ -1,37 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Broadcom BCM470X / BCM5301X ARM platform code. - * DTS for BCM47081 SoC. - * - * Copyright © 2014 Rafał Miłecki - */ - -#include "bcm5301x.dtsi" - -/ { - compatible = "brcm,bcm47081"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - next-level-cache = <&L2>; - reg = <0x0>; - }; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/bcm4709-asus-rt-ac87u.dts b/sys/gnu/dts/arm/bcm4709-asus-rt-ac87u.dts deleted file mode 100644 index 8f1e565c3db..00000000000 --- a/sys/gnu/dts/arm/bcm4709-asus-rt-ac87u.dts +++ /dev/null @@ -1,100 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Broadcom BCM470X / BCM5301X ARM platform code. - * DTS for Asus RT-AC87U - * - * Copyright (C) 2015 Rafał Miłecki - */ - -/dts-v1/; - -#include "bcm4709.dtsi" -#include "bcm5301x-nand-cs0-bch8.dtsi" - -/ { - compatible = "asus,rt-ac87u", "brcm,bcm4709", "brcm,bcm4708"; - model = "Asus RT-AC87U"; - - chosen { - bootargs = "console=ttyS0,115200"; - }; - - memory { - device_type = "memory"; - reg = <0x00000000 0x08000000 - 0x88000000 0x08000000>; - }; - - leds { - compatible = "gpio-leds"; - - wps { - label = "bcm53xx:blue:wps"; - gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>; - }; - - power { - label = "bcm53xx:blue:power"; - gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-on"; - }; - - wan { - label = "bcm53xx:red:wan"; - gpios = <&chipcommon 5 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - wps { - label = "WPS"; - linux,code = ; - gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; - }; - - restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&usb3_phy { - status = "okay"; -}; - -&nandcs { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot@0 { - label = "boot"; - reg = <0x00000000 0x00080000>; - read-only; - }; - - nvram@80000 { - label = "nvram"; - reg = <0x00080000 0x00180000>; - }; - - firmware@200000 { - label = "firmware"; - reg = <0x00200000 0x07cc0000>; - compatible = "brcm,trx"; - }; - - asus@7ec0000 { - label = "asus"; - reg = <0x07ec0000 0x00140000>; - read-only; - }; - }; -}; diff --git a/sys/gnu/dts/arm/bcm4709-buffalo-wxr-1900dhp.dts b/sys/gnu/dts/arm/bcm4709-buffalo-wxr-1900dhp.dts deleted file mode 100644 index ce888b1835d..00000000000 --- a/sys/gnu/dts/arm/bcm4709-buffalo-wxr-1900dhp.dts +++ /dev/null @@ -1,134 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Broadcom BCM470X / BCM5301X ARM platform code. - * DTS for Buffalo WXR-1900DHP - * - * Copyright (C) 2015 Felix Fietkau - */ - -/dts-v1/; - -#include "bcm4709.dtsi" -#include "bcm5301x-nand-cs0-bch8.dtsi" - -/ { - compatible = "buffalo,wxr-1900dhp", "brcm,bcm4709", "brcm,bcm4708"; - model = "Buffalo WXR-1900DHP"; - - chosen { - bootargs = "console=ttyS0,115200"; - }; - - memory { - device_type = "memory"; - reg = <0x00000000 0x08000000 - 0x88000000 0x18000000>; - }; - - leds { - compatible = "gpio-leds"; - - usb { - label = "bcm53xx:green:usb"; - gpios = <&chipcommon 4 GPIO_ACTIVE_HIGH>; - }; - - power-amber { - label = "bcm53xx:amber:power"; - gpios = <&chipcommon 5 GPIO_ACTIVE_HIGH>; - }; - - power-white { - label = "bcm53xx:white:power"; - gpios = <&chipcommon 6 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - }; - - router-amber { - label = "bcm53xx:amber:router"; - gpios = <&chipcommon 7 GPIO_ACTIVE_HIGH>; - }; - - router-white { - label = "bcm53xx:white:router"; - gpios = <&chipcommon 8 GPIO_ACTIVE_HIGH>; - }; - - wan-amber { - label = "bcm53xx:amber:wan"; - gpios = <&chipcommon 9 GPIO_ACTIVE_HIGH>; - }; - - wan-white { - label = "bcm53xx:white:wan"; - gpios = <&chipcommon 10 GPIO_ACTIVE_HIGH>; - }; - - wireless-amber { - label = "bcm53xx:amber:wireless"; - gpios = <&chipcommon 11 GPIO_ACTIVE_HIGH>; - }; - - wireless-white { - label = "bcm53xx:white:wireless"; - gpios = <&chipcommon 12 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - power { - label = "Power"; - linux,code = ; - gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>; - }; - - restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; - }; - - aoss { - label = "AOSS"; - linux,code = ; - gpios = <&chipcommon 16 GPIO_ACTIVE_LOW>; - }; - - /* Commit mode set by switch? */ - mode { - label = "Mode"; - linux,code = ; - gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; - }; - - /* Switch: AP mode */ - sw_ap { - label = "AP"; - linux,code = ; - gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>; - }; - - eject { - label = "USB eject"; - linux,code = ; - gpios = <&chipcommon 20 GPIO_ACTIVE_LOW>; - }; - }; -}; - - -&usb2 { - vcc-gpio = <&chipcommon 13 GPIO_ACTIVE_HIGH>; -}; - -&spi_nor { - status = "okay"; -}; - -&usb3_phy { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/bcm4709-linksys-ea9200.dts b/sys/gnu/dts/arm/bcm4709-linksys-ea9200.dts deleted file mode 100644 index ed8619b54d6..00000000000 --- a/sys/gnu/dts/arm/bcm4709-linksys-ea9200.dts +++ /dev/null @@ -1,46 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright (C) 2017 Rafał Miłecki - */ - -/dts-v1/; - -#include "bcm4709.dtsi" -#include "bcm5301x-nand-cs0-bch8.dtsi" - -/ { - compatible = "linksys,ea9200", "brcm,bcm4709", "brcm,bcm4708"; - model = "Linksys EA9200"; - - chosen { - bootargs = "console=ttyS0,115200"; - }; - - memory { - device_type = "memory"; - reg = <0x00000000 0x08000000 - 0x88000000 0x08000000>; - }; - - gpio-keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - wps { - label = "WPS"; - linux,code = ; - gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; - }; - - restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&usb3_phy { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/bcm4709-netgear-r7000.dts b/sys/gnu/dts/arm/bcm4709-netgear-r7000.dts deleted file mode 100644 index 1f87993eae1..00000000000 --- a/sys/gnu/dts/arm/bcm4709-netgear-r7000.dts +++ /dev/null @@ -1,108 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Broadcom BCM470X / BCM5301X ARM platform code. - * DTS for Netgear R7000 - * - * Copyright (C) 2015 Rafał Miłecki - */ - -/dts-v1/; - -#include "bcm4709.dtsi" -#include "bcm5301x-nand-cs0-bch8.dtsi" - -/ { - compatible = "netgear,r7000", "brcm,bcm4709", "brcm,bcm4708"; - model = "Netgear R7000"; - - chosen { - bootargs = "console=ttyS0,115200"; - }; - - memory { - device_type = "memory"; - reg = <0x00000000 0x08000000 - 0x88000000 0x08000000>; - }; - - leds { - compatible = "gpio-leds"; - - power-white { - label = "bcm53xx:white:power"; - gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-on"; - }; - - power-amber { - label = "bcm53xx:amber:power"; - gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; - }; - - 5ghz { - label = "bcm53xx:white:5ghz"; - gpios = <&chipcommon 12 GPIO_ACTIVE_LOW>; - }; - - 2ghz { - label = "bcm53xx:white:2ghz"; - gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; - }; - - wps { - label = "bcm53xx:white:wps"; - gpios = <&chipcommon 14 GPIO_ACTIVE_HIGH>; - }; - - wireless { - label = "bcm53xx:white:wireless"; - gpios = <&chipcommon 15 GPIO_ACTIVE_HIGH>; - }; - - usb3 { - label = "bcm53xx:white:usb3"; - gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; - }; - - usb2 { - label = "bcm53xx:white:usb2"; - gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - wps { - label = "WPS"; - linux,code = ; - gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; - }; - - rfkill { - label = "WiFi"; - linux,code = ; - gpios = <&chipcommon 5 GPIO_ACTIVE_LOW>; - }; - - restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&usb2 { - vcc-gpio = <&chipcommon 0 GPIO_ACTIVE_HIGH>; -}; - -&usb3 { - vcc-gpio = <&chipcommon 0 GPIO_ACTIVE_HIGH>; -}; - -&usb3_phy { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/bcm4709-netgear-r8000.dts b/sys/gnu/dts/arm/bcm4709-netgear-r8000.dts deleted file mode 100644 index 6c6199a53d0..00000000000 --- a/sys/gnu/dts/arm/bcm4709-netgear-r8000.dts +++ /dev/null @@ -1,189 +0,0 @@ -/* - * Broadcom BCM470X / BCM5301X ARM platform code. - * DTS for Netgear R8000 - * - * Copyright (C) 2015 Rafał Miłecki - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH - * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY - * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, - * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM - * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE - * OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR - * PERFORMANCE OF THIS SOFTWARE. - */ - -/dts-v1/; - -#include "bcm4709.dtsi" -#include "bcm5301x-nand-cs0-bch8.dtsi" - -/ { - compatible = "netgear,r8000", "brcm,bcm4709", "brcm,bcm4708"; - model = "Netgear R8000 (BCM4709)"; - - chosen { - bootargs = "console=ttyS0,115200"; - }; - - memory { - device_type = "memory"; - reg = <0x00000000 0x08000000 - 0x88000000 0x08000000>; - }; - - leds { - compatible = "gpio-leds"; - - power-white { - label = "bcm53xx:white:power"; - gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-on"; - }; - - power-amber { - label = "bcm53xx:amber:power"; - gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; - }; - - wan-white { - label = "bcm53xx:white:wan"; - gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-on"; - }; - - wan-amber { - label = "bcm53xx:amber:wan"; - gpios = <&chipcommon 9 GPIO_ACTIVE_HIGH>; - }; - - 5ghz-1 { - label = "bcm53xx:white:5ghz-1"; - gpios = <&chipcommon 12 GPIO_ACTIVE_LOW>; - }; - - 2ghz { - label = "bcm53xx:white:2ghz"; - gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; - }; - - wireless { - label = "bcm53xx:white:wireless"; - gpios = <&chipcommon 14 GPIO_ACTIVE_HIGH>; - }; - - wps { - label = "bcm53xx:white:wps"; - gpios = <&chipcommon 15 GPIO_ACTIVE_HIGH>; - }; - - 5ghz-2 { - label = "bcm53xx:white:5ghz-2"; - gpios = <&chipcommon 16 GPIO_ACTIVE_LOW>; - }; - - usb3 { - label = "bcm53xx:white:usb3"; - gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; - }; - - usb2 { - label = "bcm53xx:white:usb2"; - gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - rfkill { - label = "WiFi"; - linux,code = ; - gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; - }; - - wps { - label = "WPS"; - linux,code = ; - gpios = <&chipcommon 5 GPIO_ACTIVE_LOW>; - }; - - restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>; - }; - - brightness { - label = "Backlight"; - linux,code = ; - gpios = <&chipcommon 19 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&pcie0 { - #address-cells = <3>; - #size-cells = <2>; - - bridge@0,0,0 { - reg = <0x0000 0 0 0 0>; - - #address-cells = <3>; - #size-cells = <2>; - - wifi@0,1,0 { - reg = <0x0000 0 0 0 0>; - ieee80211-freq-limit = <5735000 5835000>; - }; - }; -}; - -&pcie1 { - #address-cells = <3>; - #size-cells = <2>; - - bridge@1,0,0 { - reg = <0x0000 0 0 0 0>; - - #address-cells = <3>; - #size-cells = <2>; - - bridge@1,1,0 { - reg = <0x0000 0 0 0 0>; - - #address-cells = <3>; - #size-cells = <2>; - - bridge@1,2,2 { - reg = <0x1000 0 0 0 0>; - - #address-cells = <3>; - #size-cells = <2>; - - wifi@1,4,0 { - reg = <0x0000 0 0 0 0>; - ieee80211-freq-limit = <5170000 5730000>; - }; - }; - }; - }; -}; - -&usb2 { - vcc-gpio = <&chipcommon 0 GPIO_ACTIVE_HIGH>; -}; - -&usb3 { - vcc-gpio = <&chipcommon 0 GPIO_ACTIVE_HIGH>; -}; - -&usb3_phy { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/bcm4709-tplink-archer-c9-v1.dts b/sys/gnu/dts/arm/bcm4709-tplink-archer-c9-v1.dts deleted file mode 100644 index f806be5da72..00000000000 --- a/sys/gnu/dts/arm/bcm4709-tplink-archer-c9-v1.dts +++ /dev/null @@ -1,139 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright (C) 2016 Rafał Miłecki - */ - -/dts-v1/; - -#include "bcm4709.dtsi" - -/ { - compatible = "tplink,archer-c9-v1", "brcm,bcm4709", "brcm,bcm4708"; - model = "TP-LINK Archer C9 V1"; - - chosen { - bootargs = "console=ttyS0,115200 earlycon"; - }; - - memory { - device_type = "memory"; - reg = <0x00000000 0x08000000>; - }; - - leds { - compatible = "gpio-leds"; - - lan { - label = "bcm53xx:blue:lan"; - gpios = <&chipcommon 1 GPIO_ACTIVE_HIGH>; - }; - - wps { - label = "bcm53xx:blue:wps"; - gpios = <&chipcommon 2 GPIO_ACTIVE_HIGH>; - }; - - 2ghz { - label = "bcm53xx:blue:2ghz"; - gpios = <&chipcommon 4 GPIO_ACTIVE_HIGH>; - }; - - 5ghz { - label = "bcm53xx:blue:5ghz"; - gpios = <&chipcommon 5 GPIO_ACTIVE_HIGH>; - }; - - usb3 { - label = "bcm53xx:blue:usb3"; - gpios = <&chipcommon 6 GPIO_ACTIVE_HIGH>; - trigger-sources = <&ohci_port1>, <&ehci_port1>, - <&xhci_port1>; - linux,default-trigger = "usbport"; - }; - - usb2 { - label = "bcm53xx:blue:usb2"; - gpios = <&chipcommon 7 GPIO_ACTIVE_HIGH>; - trigger-sources = <&ohci_port2>, <&ehci_port2>; - linux,default-trigger = "usbport"; - }; - - wan-blue { - label = "bcm53xx:blue:wan"; - gpios = <&chipcommon 14 GPIO_ACTIVE_HIGH>; - }; - - wan-amber { - label = "bcm53xx:amber:wan"; - gpios = <&chipcommon 15 GPIO_ACTIVE_HIGH>; - }; - - power { - label = "bcm53xx:blue:power"; - gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-on"; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - wps { - label = "WPS"; - linux,code = ; - gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; - }; - - restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&usb2 { - vcc-gpio = <&chipcommon 13 GPIO_ACTIVE_HIGH>; -}; - -&usb3 { - vcc-gpio = <&chipcommon 12 GPIO_ACTIVE_HIGH>; -}; - -&spi_nor { - status = "okay"; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot@0 { - label = "boot"; - reg = <0x000000 0x040000>; - read-only; - }; - - os-image@100000 { - label = "os-image"; - reg = <0x040000 0x200000>; - compatible = "brcm,trx"; - }; - - rootfs@240000 { - label = "rootfs"; - reg = <0x240000 0xc00000>; - }; - - nvram@ff0000 { - label = "nvram"; - reg = <0xff0000 0x010000>; - }; - }; -}; - -&usb3_phy { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/bcm4709.dtsi b/sys/gnu/dts/arm/bcm4709.dtsi deleted file mode 100644 index e1bb8661955..00000000000 --- a/sys/gnu/dts/arm/bcm4709.dtsi +++ /dev/null @@ -1,11 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright (C) 2016 Rafał Miłecki - */ - -#include "bcm4708.dtsi" - -&uart0 { - clock-frequency = <125000000>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/bcm47094-dlink-dir-885l.dts b/sys/gnu/dts/arm/bcm47094-dlink-dir-885l.dts deleted file mode 100644 index 911c65fbf25..00000000000 --- a/sys/gnu/dts/arm/bcm47094-dlink-dir-885l.dts +++ /dev/null @@ -1,120 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Broadcom BCM470X / BCM5301X ARM platform code. - * DTS for D-Link DIR-885L - * - * Copyright (C) 2016 Rafał Miłecki - */ - -/dts-v1/; - -#include "bcm47094.dtsi" -#include "bcm5301x-nand-cs0-bch1.dtsi" - -/ { - compatible = "dlink,dir-885l", "brcm,bcm47094", "brcm,bcm4708"; - model = "D-Link DIR-885L"; - - chosen { - bootargs = "console=ttyS0,115200 earlycon"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x08000000 - 0x88000000 0x08000000>; - }; - - nand: nand@18028000 { - nandcs@0 { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "firmware"; - reg = <0x00000000 0x08000000>; - }; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - power-white { - label = "bcm53xx:white:power"; - gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-on"; - }; - - wan-white { - label = "bcm53xx:white:wan"; - gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>; - }; - - power-amber { - label = "bcm53xx:amber:power"; - gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; - }; - - wan-amber { - label = "bcm53xx:amber:wan"; - gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; - }; - - usb3-white { - label = "bcm53xx:white:usb3"; - gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>; - trigger-sources = <&ohci_port1>, <&ehci_port1>, - <&xhci_port1>; - linux,default-trigger = "usbport"; - }; - - 2ghz { - label = "bcm53xx:white:2ghz"; - gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; - }; - - 5ghz { - label = "bcm53xx:white:5ghz"; - gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - wps { - label = "WPS"; - linux,code = ; - gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; - }; - - /* Switch: router / extender */ - extender { - label = "Extender"; - linux,code = ; - gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>; - }; - - restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&usb3 { - vcc-gpio = <&chipcommon 18 GPIO_ACTIVE_HIGH>; -}; - -&spi_nor { - status = "okay"; -}; - -&usb3_phy { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/bcm47094-linksys-panamera.dts b/sys/gnu/dts/arm/bcm47094-linksys-panamera.dts deleted file mode 100644 index 0faae895037..00000000000 --- a/sys/gnu/dts/arm/bcm47094-linksys-panamera.dts +++ /dev/null @@ -1,270 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright (C) 2017 Rafał Miłecki - */ - -/dts-v1/; - -#include "bcm47094.dtsi" -#include "bcm5301x-nand-cs0-bch8.dtsi" - -/ { - compatible = "linksys,panamera", "brcm,bcm47094", "brcm,bcm4708"; - model = "Linksys EA9500"; - - chosen { - bootargs = "console=ttyS0,115200"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x08000000 - 0x88000000 0x08000000>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - wps { - label = "WPS"; - linux,code = ; - gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; - }; - - rfkill { - label = "WiFi"; - linux,code = ; - gpios = <&chipcommon 16 GPIO_ACTIVE_LOW>; - }; - - reset { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; - }; - }; - - leds { - compatible = "gpio-leds"; - - wps { - label = "bcm53xx:white:wps"; - gpios = <&chipcommon 22 GPIO_ACTIVE_LOW>; - }; - - usb2 { - label = "bcm53xx:green:usb2"; - gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>; - trigger-sources = <&ohci_port2>, <&ehci_port2>; - linux,default-trigger = "usbport"; - }; - - usb3 { - label = "bcm53xx:green:usb3"; - gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; - trigger-sources = <&ohci_port1>, <&ehci_port1>, - <&xhci_port1>; - linux,default-trigger = "usbport"; - }; - - power { - label = "bcm53xx:white:power"; - gpios = <&chipcommon 4 GPIO_ACTIVE_HIGH>; - }; - - wifi-disabled { - label = "bcm53xx:amber:wifi-disabled"; - gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; - }; - - wifi-enabled { - label = "bcm53xx:white:wifi-enabled"; - gpios = <&chipcommon 5 GPIO_ACTIVE_HIGH>; - }; - - bluebar1 { - label = "bcm53xx:white:bluebar1"; - gpios = <&chipcommon 11 GPIO_ACTIVE_HIGH>; - }; - - bluebar2 { - label = "bcm53xx:white:bluebar2"; - gpios = <&chipcommon 12 GPIO_ACTIVE_HIGH>; - }; - - bluebar3 { - label = "bcm53xx:white:bluebar3"; - gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; - }; - - bluebar4 { - label = "bcm53xx:white:bluebar4"; - gpios = <&chipcommon 18 GPIO_ACTIVE_HIGH>; - }; - - bluebar5 { - label = "bcm53xx:white:bluebar5"; - gpios = <&chipcommon 19 GPIO_ACTIVE_HIGH>; - }; - - bluebar6 { - label = "bcm53xx:white:bluebar6"; - gpios = <&chipcommon 20 GPIO_ACTIVE_HIGH>; - }; - - bluebar7 { - label = "bcm53xx:white:bluebar7"; - gpios = <&chipcommon 21 GPIO_ACTIVE_HIGH>; - }; - - bluebar8 { - label = "bcm53xx:white:bluebar8"; - gpios = <&chipcommon 8 GPIO_ACTIVE_HIGH>; - }; - }; - - mdio-bus-mux { - #address-cells = <1>; - #size-cells = <0>; - - /* BIT(9) = 1 => external mdio */ - mdio_ext: mdio@200 { - reg = <0x200>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - mdio-mii-mux { - compatible = "mdio-mux-mmioreg"; - mdio-parent-bus = <&mdio_ext>; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x1800c1c0 0x4>; - - /* BIT(6) = mdc, BIT(7) = mdio */ - mux-mask = <0xc0>; - - mdio-mii@0 { - /* Enable MII function */ - reg = <0x0>; - #address-cells = <1>; - #size-cells = <0>; - - switch@0 { - compatible = "brcm,bcm53125"; - #address-cells = <1>; - #size-cells = <0>; - reset-gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>; - reset-names = "robo_reset"; - reg = <0>; - dsa,member = <1 0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "lan1"; - }; - - port@1 { - reg = <1>; - label = "lan5"; - }; - - port@2 { - reg = <2>; - label = "lan2"; - }; - - port@3 { - reg = <3>; - label = "lan6"; - }; - - port@4 { - reg = <4>; - label = "lan3"; - }; - - sw1_p8: port@8 { - reg = <8>; - ethernet = <&sw0_p0>; - label = "cpu"; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; - }; - }; - }; -}; - -&usb2 { - vcc-gpio = <&chipcommon 13 GPIO_ACTIVE_HIGH>; -}; - -&usb3 { - vcc-gpio = <&chipcommon 14 GPIO_ACTIVE_HIGH>; -}; - -&srab { - compatible = "brcm,bcm53012-srab", "brcm,bcm5301x-srab"; - status = "okay"; - dsa,member = <0 0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - label = "lan7"; - }; - - port@2 { - reg = <2>; - label = "lan4"; - }; - - port@3 { - reg = <3>; - label = "lan8"; - }; - - port@4 { - reg = <4>; - label = "wan"; - }; - - port@8 { - reg = <8>; - ethernet = <&gmac2>; - label = "cpu"; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - - sw0_p0: port@0 { - reg = <0>; - label = "extsw"; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; -}; - -&usb3_phy { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/bcm47094-luxul-abr-4500.dts b/sys/gnu/dts/arm/bcm47094-luxul-abr-4500.dts deleted file mode 100644 index 50f7cd08cfb..00000000000 --- a/sys/gnu/dts/arm/bcm47094-luxul-abr-4500.dts +++ /dev/null @@ -1,65 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright (C) 2017 Luxul Inc. - */ - -/dts-v1/; - -#include "bcm4708.dtsi" -#include "bcm5301x-nand-cs0-bch8.dtsi" - -/ { - compatible = "luxul,abr-4500-v1", "brcm,bcm47094", "brcm,bcm4708"; - model = "Luxul ABR-4500 V1"; - - chosen { - bootargs = "earlycon"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x08000000 - 0x88000000 0x18000000>; - }; - - leds { - compatible = "gpio-leds"; - - status { - label = "bcm53xx:green:status"; - gpios = <&chipcommon 20 GPIO_ACTIVE_LOW>; - linux,default-trigger = "timer"; - }; - - usb3 { - label = "bcm53xx:green:usb3"; - gpios = <&chipcommon 19 GPIO_ACTIVE_LOW>; - trigger-sources = <&ohci_port1>, <&ehci_port1>, - <&xhci_port1>; - linux,default-trigger = "usbport"; - }; - - }; - - gpio-keys { - compatible = "gpio-keys"; - - restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&usb3 { - vcc-gpio = <&chipcommon 18 GPIO_ACTIVE_HIGH>; -}; - -&spi_nor { - status = "okay"; -}; - -&usb3_phy { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/bcm47094-luxul-xap-1610.dts b/sys/gnu/dts/arm/bcm47094-luxul-xap-1610.dts deleted file mode 100644 index b47fb0700a1..00000000000 --- a/sys/gnu/dts/arm/bcm47094-luxul-xap-1610.dts +++ /dev/null @@ -1,56 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2018 Luxul Inc. - */ - -/dts-v1/; - -#include "bcm47094.dtsi" - -/ { - compatible = "luxul,xap-1610-v1", "brcm,bcm47094", "brcm,bcm4708"; - model = "Luxul XAP-1610 V1"; - - chosen { - bootargs = "earlycon"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x08000000>; - }; - - leds { - compatible = "gpio-leds"; - - status { - label = "bcm53xx:green:status"; - gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; - linux,default-trigger = "timer"; - }; - - 2ghz { - label = "bcm53xx:blue:2ghz"; - gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; - }; - - 5ghz { - label = "bcm53xx:blue:5ghz"; - gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&spi_nor { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/bcm47094-luxul-xbr-4500.dts b/sys/gnu/dts/arm/bcm47094-luxul-xbr-4500.dts deleted file mode 100644 index bcc420f85b5..00000000000 --- a/sys/gnu/dts/arm/bcm47094-luxul-xbr-4500.dts +++ /dev/null @@ -1,65 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright (C) 2017 Luxul Inc. - */ - -/dts-v1/; - -#include "bcm4708.dtsi" -#include "bcm5301x-nand-cs0-bch8.dtsi" - -/ { - compatible = "luxul,xbr-4500-v1", "brcm,bcm47094", "brcm,bcm4708"; - model = "Luxul XBR-4500 V1"; - - chosen { - bootargs = "earlycon"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x08000000 - 0x88000000 0x18000000>; - }; - - leds { - compatible = "gpio-leds"; - - status { - label = "bcm53xx:green:status"; - gpios = <&chipcommon 20 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "timer"; - }; - - usb3 { - label = "bcm53xx:green:usb3"; - gpios = <&chipcommon 19 GPIO_ACTIVE_HIGH>; - trigger-sources = <&ohci_port1>, <&ehci_port1>, - <&xhci_port1>; - linux,default-trigger = "usbport"; - }; - - }; - - gpio-keys { - compatible = "gpio-keys"; - - restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&usb3 { - vcc-gpio = <&chipcommon 18 GPIO_ACTIVE_HIGH>; -}; - -&spi_nor { - status = "okay"; -}; - -&usb3_phy { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/bcm47094-luxul-xwc-2000.dts b/sys/gnu/dts/arm/bcm47094-luxul-xwc-2000.dts deleted file mode 100644 index 334325390ae..00000000000 --- a/sys/gnu/dts/arm/bcm47094-luxul-xwc-2000.dts +++ /dev/null @@ -1,53 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2019 Legrand AV Inc. - */ - -/dts-v1/; - -#include "bcm47094.dtsi" -#include "bcm5301x-nand-cs0-bch8.dtsi" - -/ { - compatible = "luxul,xwc-2000-v1", "brcm,bcm47094", "brcm,bcm4708"; - model = "Luxul XWC-2000 V1"; - - chosen { - bootargs = "earlycon"; - }; - - memory { - reg = <0x00000000 0x08000000 - 0x88000000 0x18000000>; - }; - - leds { - compatible = "gpio-leds"; - - status { - label = "bcm53xx:green:status"; - gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>; - linux,default-trigger = "timer"; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 19 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&uart1 { - status = "okay"; -}; - -&spi_nor { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/bcm47094-luxul-xwr-3100.dts b/sys/gnu/dts/arm/bcm47094-luxul-xwr-3100.dts deleted file mode 100644 index ac751542347..00000000000 --- a/sys/gnu/dts/arm/bcm47094-luxul-xwr-3100.dts +++ /dev/null @@ -1,105 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2016 Luxul Inc. - */ - -/dts-v1/; - -#include "bcm47094.dtsi" -#include "bcm5301x-nand-cs0-bch4.dtsi" - -/ { - compatible = "luxul,xwr-3100v1", "brcm,bcm47094", "brcm,bcm4708"; - model = "Luxul XWR-3100 V1"; - - chosen { - bootargs = "console=ttyS0,115200 earlycon"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x08000000 - 0x88000000 0x08000000>; - }; - - leds { - compatible = "gpio-leds"; - - power { - label = "bcm53xx:green:power"; - gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-on"; - }; - - lan3 { - label = "bcm53xx:green:lan3"; - gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>; - }; - - lan4 { - label = "bcm53xx:green:lan4"; - gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; - }; - - wan { - label = "bcm53xx:green:wan"; - gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; - }; - - lan1 { - label = "bcm53xx:green:lan1"; - gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; - }; - - lan2 { - label = "bcm53xx:green:lan2"; - gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>; - }; - - usb3 { - label = "bcm53xx:green:usb3"; - gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>; - trigger-sources = <&ohci_port1>, <&ehci_port1>, - <&xhci_port1>; - linux,default-trigger = "usbport"; - }; - - status { - label = "bcm53xx:green:status"; - gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>; - linux,default-trigger = "timer"; - }; - - 2ghz { - label = "bcm53xx:green:2ghz"; - gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; - }; - - 5ghz { - label = "bcm53xx:green:5ghz"; - gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&usb3 { - vcc-gpio = <&chipcommon 18 GPIO_ACTIVE_HIGH>; -}; - -&spi_nor { - status = "okay"; -}; - -&usb3_phy { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/bcm47094-luxul-xwr-3150-v1.dts b/sys/gnu/dts/arm/bcm47094-luxul-xwr-3150-v1.dts deleted file mode 100644 index 6d28b7dacd0..00000000000 --- a/sys/gnu/dts/arm/bcm47094-luxul-xwr-3150-v1.dts +++ /dev/null @@ -1,76 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2018 Luxul Inc. - */ - -/dts-v1/; - -#include "bcm47094.dtsi" -#include "bcm5301x-nand-cs0-bch8.dtsi" - -/ { - compatible = "luxul,xwr-3150-v1", "brcm,bcm47094", "brcm,bcm4708"; - model = "Luxul XWR-3150 V1"; - - chosen { - bootargs = "earlycon"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x08000000 - 0x88000000 0x18000000>; - }; - - leds { - compatible = "gpio-leds"; - - power { - label = "bcm53xx:green:power"; - gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-on"; - }; - - usb3 { - label = "bcm53xx:green:usb3"; - gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>; - trigger-sources = <&ohci_port1>, <&ehci_port1>, - <&xhci_port1>; - linux,default-trigger = "usbport"; - }; - - status { - label = "bcm53xx:green:status"; - gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>; - linux,default-trigger = "timer"; - }; - - 2ghz { - label = "bcm53xx:green:2ghz"; - gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; - }; - - 5ghz { - label = "bcm53xx:green:5ghz"; - gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&usb3 { - vcc-gpio = <&chipcommon 18 GPIO_ACTIVE_HIGH>; -}; - -&spi_nor { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/bcm47094-netgear-r8500.dts b/sys/gnu/dts/arm/bcm47094-netgear-r8500.dts deleted file mode 100644 index f42a1703f4a..00000000000 --- a/sys/gnu/dts/arm/bcm47094-netgear-r8500.dts +++ /dev/null @@ -1,96 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright (C) 2016 Rafał Miłecki - */ - -/dts-v1/; - -#include "bcm47094.dtsi" -#include "bcm5301x-nand-cs0-bch8.dtsi" - -/ { - compatible = "netgear,r8500", "brcm,bcm47094", "brcm,bcm4708"; - model = "Netgear R8500"; - - chosen { - bootargs = "console=ttyS0,115200"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x08000000 - 0x88000000 0x18000000>; - }; - - leds { - compatible = "gpio-leds"; - - power0 { - label = "bcm53xx:white:power"; - gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-on"; - }; - - power1 { - label = "bcm53xx:amber:power"; - gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; - }; - - 5ghz-1 { - label = "bcm53xx:white:5ghz-1"; - gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; - }; - - 5ghz-2 { - label = "bcm53xx:white:5ghz-2"; - gpios = <&chipcommon 12 GPIO_ACTIVE_LOW>; - }; - - 2ghz { - label = "bcm53xx:white:2ghz"; - gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; - }; - - usb2 { - label = "bcm53xx:white:usb2"; - gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; - }; - - usb3 { - label = "bcm53xx:white:usb3"; - gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - brightness { - label = "Backlight"; - linux,code = ; - gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>; - }; - - restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>; - }; - - wps { - label = "WPS"; - linux,code = ; - gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; - }; - - rfkill { - label = "WiFi"; - linux,code = ; - gpios = <&chipcommon 20 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&usb3_phy { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/bcm47094-phicomm-k3.dts b/sys/gnu/dts/arm/bcm47094-phicomm-k3.dts deleted file mode 100644 index ac3a4483dcb..00000000000 --- a/sys/gnu/dts/arm/bcm47094-phicomm-k3.dts +++ /dev/null @@ -1,70 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright (C) 2017 Hamster Tian - * Copyright (C) 2019 Hao Dong - */ - -/dts-v1/; - -#include "bcm47094.dtsi" -#include "bcm5301x-nand-cs0-bch4.dtsi" - -/ { - compatible = "phicomm,k3", "brcm,bcm47094", "brcm,bcm4708"; - model = "Phicomm K3"; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x08000000 - 0x88000000 0x18000000>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&uart1 { - status = "okay"; -}; - -&usb3_phy { - status = "okay"; -}; - -&nandcs { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "boot"; - reg = <0x0000000 0x0080000>; - read-only; - }; - - partition@80000 { - label = "nvram"; - reg = <0x0080000 0x0100000>; - }; - - partition@180000{ - label = "phicomm"; - reg = <0x0180000 0x0280000>; - read-only; - }; - - partition@400000 { - label = "firmware"; - reg = <0x0400000 0x7C00000>; - compatible = "brcm,trx"; - }; - }; -}; diff --git a/sys/gnu/dts/arm/bcm47094.dtsi b/sys/gnu/dts/arm/bcm47094.dtsi deleted file mode 100644 index cdc5ff593ad..00000000000 --- a/sys/gnu/dts/arm/bcm47094.dtsi +++ /dev/null @@ -1,18 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright (C) 2016 Rafał Miłecki - */ - -#include "bcm4708.dtsi" - -/ { -}; - -&usb3_phy { - compatible = "brcm,ns-bx-usb3-phy"; -}; - -&uart0 { - clock-frequency = <125000000>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/bcm47189-luxul-xap-1440.dts b/sys/gnu/dts/arm/bcm47189-luxul-xap-1440.dts deleted file mode 100644 index 57ca1cfaecd..00000000000 --- a/sys/gnu/dts/arm/bcm47189-luxul-xap-1440.dts +++ /dev/null @@ -1,48 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2017 Luxul Inc. - */ - -/dts-v1/; - -#include "bcm53573.dtsi" - -/ { - compatible = "luxul,xap-1440-v1", "brcm,bcm47189", "brcm,bcm53573"; - model = "Luxul XAP-1440 V1"; - - chosen { - bootargs = "earlycon"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x08000000>; - }; - - leds { - compatible = "gpio-leds"; - - wlan { - label = "bcm53xx:blue:wlan"; - gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-off"; - }; - - system { - label = "bcm53xx:green:system"; - gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; - linux,default-trigger = "timer"; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/bcm47189-luxul-xap-810.dts b/sys/gnu/dts/arm/bcm47189-luxul-xap-810.dts deleted file mode 100644 index 2e1a7e382cb..00000000000 --- a/sys/gnu/dts/arm/bcm47189-luxul-xap-810.dts +++ /dev/null @@ -1,85 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2017 Luxul Inc. - */ - -/dts-v1/; - -#include "bcm53573.dtsi" - -/ { - compatible = "luxul,xap-810-v1", "brcm,bcm47189", "brcm,bcm53573"; - model = "Luxul XAP-810 V1"; - - chosen { - bootargs = "earlycon"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x08000000>; - }; - - leds { - compatible = "gpio-leds"; - - 5ghz { - label = "bcm53xx:blue:5ghz"; - gpios = <&chipcommon 11 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-off"; - }; - - system { - label = "bcm53xx:green:system"; - gpios = <&chipcommon 15 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "timer"; - }; - }; - - pcie0_leds { - compatible = "gpio-leds"; - - 2ghz { - label = "bcm53xx:blue:2ghz"; - gpios = <&pcie0_chipcommon 3 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-off"; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&pcie0 { - ranges = <0x00000000 0 0 0 0 0x00100000>; - #address-cells = <3>; - #size-cells = <2>; - - bridge@0,0,0 { - reg = <0x0000 0 0 0 0>; - ranges = <0x00000000 0 0 0 0 0 0 0x00100000>; - #address-cells = <3>; - #size-cells = <2>; - - wifi@0,1,0 { - reg = <0x0000 0 0 0 0>; - ranges = <0x00000000 0 0 0 0x00100000>; - #address-cells = <1>; - #size-cells = <1>; - - pcie0_chipcommon: chipcommon@0 { - reg = <0 0x1000>; - - gpio-controller; - #gpio-cells = <2>; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/bcm47189-tenda-ac9.dts b/sys/gnu/dts/arm/bcm47189-tenda-ac9.dts deleted file mode 100644 index 049cdfd9270..00000000000 --- a/sys/gnu/dts/arm/bcm47189-tenda-ac9.dts +++ /dev/null @@ -1,107 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright (C) 2016 Rafał Miłecki - */ - -/dts-v1/; - -#include "bcm53573.dtsi" - -/ { - compatible = "tenda,ac9", "brcm,bcm47189", "brcm,bcm53573"; - model = "Tenda AC9"; - - chosen { - bootargs = "console=ttyS0,115200 earlycon"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x08000000>; - }; - - leds { - compatible = "gpio-leds"; - - usb { - label = "bcm53xx:blue:usb"; - gpios = <&chipcommon 1 GPIO_ACTIVE_HIGH>; - trigger-sources = <&ohci_port1>, <&ehci_port1>; - linux,default-trigger = "usbport"; - }; - - wps { - label = "bcm53xx:blue:wps"; - gpios = <&chipcommon 10 GPIO_ACTIVE_HIGH>; - }; - - 5ghz { - label = "bcm53xx:blue:5ghz"; - gpios = <&chipcommon 11 GPIO_ACTIVE_HIGH>; - }; - - system { - label = "bcm53xx:blue:system"; - gpios = <&chipcommon 15 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "timer"; - }; - }; - - pcie0_leds { - compatible = "gpio-leds"; - - 2ghz { - label = "bcm53xx:blue:2ghz"; - gpios = <&pcie0_chipcommon 3 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - rfkill { - label = "WiFi"; - linux,code = ; - gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; - }; - - restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; - }; - - wps { - label = "WPS"; - linux,code = ; - gpios = <&chipcommon 9 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&pcie0 { - ranges = <0x00000000 0 0 0 0 0x00100000>; - #address-cells = <3>; - #size-cells = <2>; - - bridge@0,0,0 { - reg = <0x0000 0 0 0 0>; - ranges = <0x00000000 0 0 0 0 0 0 0x00100000>; - #address-cells = <3>; - #size-cells = <2>; - - wifi@0,1,0 { - reg = <0x0000 0 0 0 0>; - ranges = <0x00000000 0 0 0 0x00100000>; - #address-cells = <1>; - #size-cells = <1>; - - pcie0_chipcommon: chipcommon@0 { - reg = <0 0x1000>; - - gpio-controller; - #gpio-cells = <2>; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/bcm5301x-nand-cs0-bch1.dtsi b/sys/gnu/dts/arm/bcm5301x-nand-cs0-bch1.dtsi deleted file mode 100644 index c349e8f0afc..00000000000 --- a/sys/gnu/dts/arm/bcm5301x-nand-cs0-bch1.dtsi +++ /dev/null @@ -1,14 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Broadcom Northstar NAND. - * - * Copyright (C) 2016 Rafał Miłecki - */ - -#include "bcm5301x-nand-cs0.dtsi" - -&nandcs { - nand-ecc-algo = "bch"; - nand-ecc-strength = <1>; - nand-ecc-step-size = <512>; -}; diff --git a/sys/gnu/dts/arm/bcm5301x-nand-cs0-bch4.dtsi b/sys/gnu/dts/arm/bcm5301x-nand-cs0-bch4.dtsi deleted file mode 100644 index 18e25e302b1..00000000000 --- a/sys/gnu/dts/arm/bcm5301x-nand-cs0-bch4.dtsi +++ /dev/null @@ -1,12 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2016 Luxul Inc. - */ - -#include "bcm5301x-nand-cs0.dtsi" - -&nandcs { - nand-ecc-algo = "bch"; - nand-ecc-strength = <4>; - nand-ecc-step-size = <512>; -}; diff --git a/sys/gnu/dts/arm/bcm5301x-nand-cs0-bch8.dtsi b/sys/gnu/dts/arm/bcm5301x-nand-cs0-bch8.dtsi deleted file mode 100644 index c8e56d30bd6..00000000000 --- a/sys/gnu/dts/arm/bcm5301x-nand-cs0-bch8.dtsi +++ /dev/null @@ -1,17 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Broadcom BCM470X / BCM5301X Nand chip defaults. - * - * This should be included if the NAND controller is on chip select 0 - * and uses 8 bit ECC. - * - * Copyright (C) 2015 Hauke Mehrtens - */ - -#include "bcm5301x-nand-cs0.dtsi" - -&nandcs { - nand-ecc-algo = "bch"; - nand-ecc-strength = <8>; - nand-ecc-step-size = <512>; -}; diff --git a/sys/gnu/dts/arm/bcm5301x-nand-cs0.dtsi b/sys/gnu/dts/arm/bcm5301x-nand-cs0.dtsi deleted file mode 100644 index 925a7c9ce5b..00000000000 --- a/sys/gnu/dts/arm/bcm5301x-nand-cs0.dtsi +++ /dev/null @@ -1,21 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Broadcom Northstar NAND. - * - * Copyright (C) 2015 Hauke Mehrtens - */ - -/ { - nand@18028000 { - nandcs: nandcs@0 { - compatible = "brcm,nandcs"; - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; - - partitions { - compatible = "brcm,bcm947xx-cfe-partitions"; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/bcm5301x.dtsi b/sys/gnu/dts/arm/bcm5301x.dtsi deleted file mode 100644 index 2d9b4dd0583..00000000000 --- a/sys/gnu/dts/arm/bcm5301x.dtsi +++ /dev/null @@ -1,548 +0,0 @@ -/* - * Broadcom BCM470X / BCM5301X ARM platform code. - * Generic DTS part for all BCM53010, BCM53011, BCM53012, BCM53014, BCM53015, - * BCM53016, BCM53017, BCM53018, BCM4707, BCM4708 and BCM4709 SoCs - * - * Copyright 2013-2014 Hauke Mehrtens - * - * Licensed under the GNU/GPL. See COPYING for details. - */ - -#include -#include -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&gic>; - - chipcommonA@18000000 { - compatible = "simple-bus"; - ranges = <0x00000000 0x18000000 0x00001000>; - #address-cells = <1>; - #size-cells = <1>; - - uart0: serial@300 { - compatible = "ns16550"; - reg = <0x0300 0x100>; - interrupts = ; - clocks = <&iprocslow>; - status = "disabled"; - }; - - uart1: serial@400 { - compatible = "ns16550"; - reg = <0x0400 0x100>; - interrupts = ; - clocks = <&iprocslow>; - pinctrl-names = "default"; - pinctrl-0 = <&pinmux_uart1>; - status = "disabled"; - }; - }; - - mpcore@19000000 { - compatible = "simple-bus"; - ranges = <0x00000000 0x19000000 0x00023000>; - #address-cells = <1>; - #size-cells = <1>; - - a9pll: arm_clk@0 { - #clock-cells = <0>; - compatible = "brcm,nsp-armpll"; - clocks = <&osc>; - reg = <0x00000 0x1000>; - }; - - scu@20000 { - compatible = "arm,cortex-a9-scu"; - reg = <0x20000 0x100>; - }; - - timer@20200 { - compatible = "arm,cortex-a9-global-timer"; - reg = <0x20200 0x100>; - interrupts = ; - clocks = <&periph_clk>; - }; - - timer@20600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0x20600 0x20>; - interrupts = ; - clocks = <&periph_clk>; - }; - - watchdog@20620 { - compatible = "arm,cortex-a9-twd-wdt"; - reg = <0x20620 0x20>; - interrupts = ; - clocks = <&periph_clk>; - }; - - gic: interrupt-controller@21000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x21000 0x1000>, - <0x20100 0x100>; - }; - - L2: cache-controller@22000 { - compatible = "arm,pl310-cache"; - reg = <0x22000 0x1000>; - cache-unified; - arm,shared-override; - prefetch-data = <1>; - prefetch-instr = <1>; - cache-level = <2>; - }; - }; - - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts = - , - ; - }; - - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - osc: oscillator { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <25000000>; - }; - - iprocmed: iprocmed { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>; - clock-div = <2>; - clock-mult = <1>; - }; - - iprocslow: iprocslow { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>; - clock-div = <4>; - clock-mult = <1>; - }; - - periph_clk: periph_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&a9pll>; - clock-div = <2>; - clock-mult = <1>; - }; - }; - - usb2_phy: usb2-phy@1800c000 { - compatible = "brcm,ns-usb2-phy"; - reg = <0x1800c000 0x1000>; - reg-names = "dmu"; - #phy-cells = <0>; - clocks = <&genpll BCM_NSP_GENPLL_USB_PHY_REF_CLK>; - clock-names = "phy-ref-clk"; - }; - - axi@18000000 { - compatible = "brcm,bus-axi"; - reg = <0x18000000 0x1000>; - ranges = <0x00000000 0x18000000 0x00100000>; - #address-cells = <1>; - #size-cells = <1>; - - #interrupt-cells = <1>; - interrupt-map-mask = <0x000fffff 0xffff>; - interrupt-map = - /* ChipCommon */ - <0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, - - /* Switch Register Access Block */ - <0x00007000 0 &gic GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, - <0x00007000 1 &gic GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, - <0x00007000 2 &gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, - <0x00007000 3 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, - <0x00007000 4 &gic GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, - <0x00007000 5 &gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, - <0x00007000 6 &gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, - <0x00007000 7 &gic GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, - <0x00007000 8 &gic GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, - <0x00007000 9 &gic GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, - <0x00007000 10 &gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, - <0x00007000 11 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, - <0x00007000 12 &gic GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, - - /* PCIe Controller 0 */ - <0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, - <0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, - <0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, - <0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, - <0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, - <0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, - - /* PCIe Controller 1 */ - <0x00013000 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, - <0x00013000 1 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, - <0x00013000 2 &gic GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, - <0x00013000 3 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, - <0x00013000 4 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, - <0x00013000 5 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, - - /* PCIe Controller 2 */ - <0x00014000 0 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, - <0x00014000 1 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, - <0x00014000 2 &gic GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, - <0x00014000 3 &gic GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, - <0x00014000 4 &gic GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, - <0x00014000 5 &gic GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, - - /* USB 2.0 Controller */ - <0x00021000 0 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, - - /* USB 3.0 Controller */ - <0x00023000 0 &gic GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, - - /* Ethernet Controller 0 */ - <0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, - - /* Ethernet Controller 1 */ - <0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, - - /* Ethernet Controller 2 */ - <0x00026000 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, - - /* Ethernet Controller 3 */ - <0x00027000 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, - - /* NAND Controller */ - <0x00028000 0 &gic GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, - <0x00028000 1 &gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, - <0x00028000 2 &gic GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, - <0x00028000 3 &gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, - <0x00028000 4 &gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, - <0x00028000 5 &gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, - <0x00028000 6 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, - <0x00028000 7 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; - - chipcommon: chipcommon@0 { - reg = <0x00000000 0x1000>; - - gpio-controller; - #gpio-cells = <2>; - }; - - pcie0: pcie@12000 { - reg = <0x00012000 0x1000>; - }; - - pcie1: pcie@13000 { - reg = <0x00013000 0x1000>; - }; - - usb2: usb2@21000 { - reg = <0x00021000 0x1000>; - - #address-cells = <1>; - #size-cells = <1>; - ranges; - - interrupt-parent = <&gic>; - - ehci: ehci@21000 { - #usb-cells = <0>; - - compatible = "generic-ehci"; - reg = <0x00021000 0x1000>; - interrupts = ; - phys = <&usb2_phy>; - - #address-cells = <1>; - #size-cells = <0>; - - ehci_port1: port@1 { - reg = <1>; - #trigger-source-cells = <0>; - }; - - ehci_port2: port@2 { - reg = <2>; - #trigger-source-cells = <0>; - }; - }; - - ohci: ohci@22000 { - #usb-cells = <0>; - - compatible = "generic-ohci"; - reg = <0x00022000 0x1000>; - interrupts = ; - - #address-cells = <1>; - #size-cells = <0>; - - ohci_port1: port@1 { - reg = <1>; - #trigger-source-cells = <0>; - }; - - ohci_port2: port@2 { - reg = <2>; - #trigger-source-cells = <0>; - }; - }; - }; - - usb3: usb3@23000 { - reg = <0x00023000 0x1000>; - - #address-cells = <1>; - #size-cells = <1>; - ranges; - - interrupt-parent = <&gic>; - - xhci: xhci@23000 { - #usb-cells = <0>; - - compatible = "generic-xhci"; - reg = <0x00023000 0x1000>; - interrupts = ; - phys = <&usb3_phy>; - phy-names = "usb"; - - #address-cells = <1>; - #size-cells = <0>; - - xhci_port1: port@1 { - reg = <1>; - #trigger-source-cells = <0>; - }; - }; - }; - - gmac0: ethernet@24000 { - reg = <0x24000 0x800>; - }; - - gmac1: ethernet@25000 { - reg = <0x25000 0x800>; - }; - - gmac2: ethernet@26000 { - reg = <0x26000 0x800>; - }; - - gmac3: ethernet@27000 { - reg = <0x27000 0x800>; - }; - }; - - mdio: mdio@18003000 { - compatible = "brcm,iproc-mdio"; - reg = <0x18003000 0x8>; - #size-cells = <0>; - #address-cells = <1>; - }; - - mdio-bus-mux@18003000 { - compatible = "mdio-mux-mmioreg"; - mdio-parent-bus = <&mdio>; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x18003000 0x4>; - mux-mask = <0x200>; - - mdio@0 { - reg = <0x0>; - #address-cells = <1>; - #size-cells = <0>; - - usb3_phy: usb3-phy@10 { - compatible = "brcm,ns-ax-usb3-phy"; - reg = <0x10>; - usb3-dmp-syscon = <&usb3_dmp>; - #phy-cells = <0>; - status = "disabled"; - }; - }; - }; - - usb3_dmp: syscon@18105000 { - reg = <0x18105000 0x1000>; - }; - - i2c0: i2c@18009000 { - compatible = "brcm,iproc-i2c"; - reg = <0x18009000 0x50>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-frequency = <100000>; - status = "disabled"; - }; - - dmu@1800c000 { - compatible = "simple-bus"; - ranges = <0 0x1800c000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - - cru@100 { - compatible = "simple-bus"; - reg = <0x100 0x1a4>; - ranges; - #address-cells = <1>; - #size-cells = <1>; - - pin-controller@1c0 { - compatible = "brcm,bcm4708-pinmux"; - reg = <0x1c0 0x24>; - reg-names = "cru_gpio_control"; - - spi-pins { - groups = "spi_grp"; - function = "spi"; - }; - - i2c { - groups = "i2c_grp"; - function = "i2c"; - }; - - pwm { - groups = "pwm0_grp", "pwm1_grp", - "pwm2_grp", "pwm3_grp"; - function = "pwm"; - }; - - pinmux_uart1: uart1 { - groups = "uart1_grp"; - function = "uart1"; - }; - }; - }; - }; - - lcpll0: lcpll0@1800c100 { - #clock-cells = <1>; - compatible = "brcm,nsp-lcpll0"; - reg = <0x1800c100 0x14>; - clocks = <&osc>; - clock-output-names = "lcpll0", "pcie_phy", "sdio", - "ddr_phy"; - }; - - genpll: genpll@1800c140 { - #clock-cells = <1>; - compatible = "brcm,nsp-genpll"; - reg = <0x1800c140 0x24>; - clocks = <&osc>; - clock-output-names = "genpll", "phy", "ethernetclk", - "usbclk", "iprocfast", "sata1", - "sata2"; - }; - - thermal: thermal@1800c2c0 { - compatible = "brcm,ns-thermal"; - reg = <0x1800c2c0 0x10>; - #thermal-sensor-cells = <0>; - }; - - srab: srab@18007000 { - compatible = "brcm,bcm5301x-srab"; - reg = <0x18007000 0x1000>; - - status = "disabled"; - - /* ports are defined in board DTS */ - }; - - rng: rng@18004000 { - compatible = "brcm,bcm5301x-rng"; - reg = <0x18004000 0x14>; - }; - - nand: nand@18028000 { - compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand"; - reg = <0x18028000 0x600>, <0x1811a408 0x600>, <0x18028f00 0x20>; - reg-names = "nand", "iproc-idm", "iproc-ext"; - interrupts = ; - - #address-cells = <1>; - #size-cells = <0>; - - brcm,nand-has-wp; - }; - - spi@18029200 { - compatible = "brcm,spi-bcm-qspi", "brcm,spi-nsp-qspi"; - reg = <0x18029200 0x184>, - <0x18029000 0x124>, - <0x1811b408 0x004>, - <0x180293a0 0x01c>; - reg-names = "mspi", "bspi", "intr_regs", "intr_status_reg"; - interrupts = , - , - , - , - , - , - ; - interrupt-names = "spi_lr_fullness_reached", - "spi_lr_session_aborted", - "spi_lr_impatient", - "spi_lr_session_done", - "spi_lr_overhead", - "mspi_done", - "mspi_halted"; - clocks = <&iprocmed>; - clock-names = "iprocmed"; - num-cs = <2>; - #address-cells = <1>; - #size-cells = <0>; - - spi_nor: spi-nor@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <20000000>; - status = "disabled"; - - partitions { - compatible = "brcm,bcm947xx-cfe-partitions"; - }; - }; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <0>; - polling-delay = <1000>; - coefficients = <(-556) 418000>; - thermal-sensors = <&thermal>; - - trips { - cpu-crit { - temperature = <125000>; - hysteresis = <0>; - type = "critical"; - }; - }; - - cooling-maps { - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/bcm53340-ubnt-unifi-switch8.dts b/sys/gnu/dts/arm/bcm53340-ubnt-unifi-switch8.dts deleted file mode 100644 index 2e7fda9b998..00000000000 --- a/sys/gnu/dts/arm/bcm53340-ubnt-unifi-switch8.dts +++ /dev/null @@ -1,86 +0,0 @@ -/* - * DTS for Unifi Switch 8 port - * - * Copyright (C) 2017 Florian Fainelli - * - * Licensed under the GNU/GPL. See COPYING for details. - */ - -/dts-v1/; - -#include "bcm-hr2.dtsi" - -/ { - compatible = "ubnt,unifi-switch8", "brcm,bcm53342", "brcm,hr2"; - model = "Ubiquiti UniFi Switch 8 (BCM53342)"; - - /* Hurricane 2 designs use the second UART */ - chosen { - bootargs = "console=ttyS1,115200 earlyprintk"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x08000000>, - <0x68000000 0x08000000>; - }; -}; - -&uart1 { - status = "okay"; -}; - -&qspi { - status = "okay"; - bspi-sel = <0>; - - flash: m25p80@0 { - compatible = "m25p80"; - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; - spi-max-frequency = <12500000>; - spi-cpol; - spi-cpha; - - partition@0 { - label = "u-boot"; - reg = <0x0 0xc0000>; - }; - - partition@c0000 { - label = "u-boot-env"; - reg = <0xc0000 0x10000>; - }; - - partition@d0000 { - label = "shmoo"; - reg = <0xd0000 0x10000>; - }; - - partition@e0000 { - label = "kernel0"; - reg = <0xe0000 0xf00000>; - }; - - partition@fe0000 { - label = "kernel1"; - reg = <0xfe0000 0xf10000>; - }; - - partition@1ef0000 { - label = "cfg"; - reg = <0x1ef0000 0x100000>; - }; - - partition@1ff0000 { - label = "EEPROM"; - reg = <0x1ff0000 0x10000>; - }; - }; -}; - -&pcie0 { - /* Attaches to the internal switch */ - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/bcm53573.dtsi b/sys/gnu/dts/arm/bcm53573.dtsi deleted file mode 100644 index 4af8e3293cf..00000000000 --- a/sys/gnu/dts/arm/bcm53573.dtsi +++ /dev/null @@ -1,201 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright (C) 2016 Rafał Miłecki - */ - -#include -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&gic>; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x0>; - }; - }; - - mpcore@18310000 { - compatible = "simple-bus"; - ranges = <0x00000000 0x18310000 0x00008000>; - #address-cells = <1>; - #size-cells = <1>; - - gic: interrupt-controller@1000 { - compatible = "arm,cortex-a7-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x1000 0x1000>, - <0x2000 0x0100>; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; - }; - - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - alp: oscillator { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <40000000>; - }; - }; - - axi@18000000 { - compatible = "brcm,bus-axi"; - reg = <0x18000000 0x1000>; - ranges = <0x00000000 0x18000000 0x00100000>; - #address-cells = <1>; - #size-cells = <1>; - - #interrupt-cells = <1>; - interrupt-map-mask = <0x000fffff 0xffff>; - interrupt-map = - /* ChipCommon */ - <0x00000000 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, - - /* IEEE 802.11 0 */ - <0x00001000 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, - - /* PCIe Controller 0 */ - <0x00002000 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, - <0x00002000 1 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, - <0x00002000 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, - <0x00002000 3 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, - <0x00002000 4 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, - <0x00002000 5 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, - - /* USB 2.0 Controller */ - <0x00004000 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, - - /* Ethernet Controller 0 */ - <0x00005000 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, - - /* IEEE 802.11 1 */ - <0x0000a000 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, - - /* Ethernet Controller 1 */ - <0x0000b000 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; - - chipcommon: chipcommon@0 { - compatible = "simple-bus"; - reg = <0x00000000 0x1000>; - ranges; - - #address-cells = <1>; - #size-cells = <1>; - - gpio-controller; - #gpio-cells = <2>; - - uart0: serial@300 { - compatible = "ns16550a"; - reg = <0x0300 0x100>; - interrupt-parent = <&gic>; - interrupts = ; - clocks = <&alp>; - status = "okay"; - }; - }; - - pcie0: pcie@2000 { - reg = <0x00002000 0x1000>; - }; - - usb2: usb2@4000 { - reg = <0x4000 0x1000>; - ranges; - #address-cells = <1>; - #size-cells = <1>; - - ehci: ehci@4000 { - compatible = "generic-ehci"; - reg = <0x4000 0x1000>; - interrupt-parent = <&gic>; - interrupts = ; - - #address-cells = <1>; - #size-cells = <0>; - - ehci_port1: port@1 { - reg = <1>; - #trigger-source-cells = <0>; - }; - - ehci_port2: port@2 { - reg = <2>; - #trigger-source-cells = <0>; - }; - }; - - ohci: ohci@d000 { - #usb-cells = <0>; - - compatible = "generic-ohci"; - reg = <0xd000 0x1000>; - interrupt-parent = <&gic>; - interrupts = ; - - #address-cells = <1>; - #size-cells = <0>; - - ohci_port1: port@1 { - reg = <1>; - #trigger-source-cells = <0>; - }; - - ohci_port2: port@2 { - reg = <2>; - #trigger-source-cells = <0>; - }; - }; - }; - - gmac0: ethernet@5000 { - reg = <0x5000 0x1000>; - }; - - gmac1: ethernet@b000 { - reg = <0xb000 0x1000>; - }; - - pmu@12000 { - compatible = "simple-mfd", "syscon"; - reg = <0x00012000 0x00001000>; - - ilp: ilp { - compatible = "brcm,bcm53573-ilp"; - clocks = <&alp>; - #clock-cells = <0>; - clock-output-names = "ilp"; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/bcm59056.dtsi b/sys/gnu/dts/arm/bcm59056.dtsi deleted file mode 100644 index a9bb7ad8137..00000000000 --- a/sys/gnu/dts/arm/bcm59056.dtsi +++ /dev/null @@ -1,91 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* -* Copyright 2014 Linaro Limited -* Author: Matt Porter -*/ - -&pmu { - compatible = "brcm,bcm59056"; - regulators { - rfldo_reg: rfldo { - }; - - camldo1_reg: camldo1 { - }; - - camldo2_reg: camldo2 { - }; - - simldo1_reg: simldo1 { - }; - - simldo2_reg: simldo2 { - }; - - sdldo_reg: sdldo { - }; - - sdxldo_reg: sdxldo { - }; - - mmcldo1_reg: mmcldo1 { - }; - - mmcldo2_reg: mmcldo2 { - }; - - audldo_reg: audldo { - }; - - micldo_reg: micldo { - }; - - usbldo_reg: usbldo { - }; - - vibldo_reg: vibldo { - }; - - csr_reg: csr { - }; - - iosr1_reg: iosr1 { - }; - - iosr2_reg: iosr2 { - }; - - msr_reg: msr { - }; - - sdsr1_reg: sdsr1 { - }; - - sdsr2_reg: sdsr2 { - }; - - vsr_reg: vsr { - }; - - gpldo1_reg: gpldo1 { - }; - - gpldo2_reg: gpldo2 { - }; - - gpldo3_reg: gpldo3 { - }; - - gpldo4_reg: gpldo4 { - }; - - gpldo5_reg: gpldo5 { - }; - - gpldo6_reg: gpldo6 { - }; - - vbus_reg: vbus { - }; - }; -}; diff --git a/sys/gnu/dts/arm/bcm63138.dtsi b/sys/gnu/dts/arm/bcm63138.dtsi deleted file mode 100644 index 9c0325cf9e2..00000000000 --- a/sys/gnu/dts/arm/bcm63138.dtsi +++ /dev/null @@ -1,229 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Broadcom BCM63138 DSL SoCs Device Tree - */ - -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - compatible = "brcm,bcm63138"; - model = "Broadcom BCM63138 DSL SoC"; - interrupt-parent = <&gic>; - - aliases { - uart0 = &serial0; - uart1 = &serial1; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - next-level-cache = <&L2>; - reg = <0>; - enable-method = "brcm,bcm63138"; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - next-level-cache = <&L2>; - reg = <1>; - enable-method = "brcm,bcm63138"; - resets = <&pmb0 4 1>; - }; - }; - - clocks { - /* UBUS peripheral clock */ - periph_clk: periph_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <50000000>; - clock-output-names = "periph"; - }; - - /* peripheral clock for system timer */ - axi_clk: axi_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&armpll>; - clock-div = <2>; - clock-mult = <1>; - }; - - /* APB bus clock */ - apb_clk: apb_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&armpll>; - clock-div = <4>; - clock-mult = <1>; - }; - }; - - /* ARM bus */ - axi@80000000 { - compatible = "simple-bus"; - ranges = <0 0x80000000 0x784000>; - #address-cells = <1>; - #size-cells = <1>; - - L2: cache-controller@1d000 { - compatible = "arm,pl310-cache"; - reg = <0x1d000 0x1000>; - cache-unified; - cache-level = <2>; - cache-size = <524288>; - cache-sets = <1024>; - cache-line-size = <32>; - interrupts = ; - }; - - scu: scu@1e000 { - compatible = "arm,cortex-a9-scu"; - reg = <0x1e000 0x100>; - }; - - gic: interrupt-controller@1f000 { - compatible = "arm,cortex-a9-gic"; - reg = <0x1f000 0x1000 - 0x1e100 0x100>; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - }; - - global_timer: timer@1e200 { - compatible = "arm,cortex-a9-global-timer"; - reg = <0x1e200 0x20>; - interrupts = ; - clocks = <&axi_clk>; - }; - - local_timer: local-timer@1e600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0x1e600 0x20>; - interrupts = ; - clocks = <&axi_clk>; - }; - - twd_watchdog: watchdog@1e620 { - compatible = "arm,cortex-a9-twd-wdt"; - reg = <0x1e620 0x20>; - interrupts = ; - }; - - armpll: armpll@20000 { - #clock-cells = <0>; - compatible = "brcm,bcm63138-armpll"; - clocks = <&periph_clk>; - reg = <0x20000 0xf00>; - }; - - pmb0: reset-controller@4800c0 { - compatible = "brcm,bcm63138-pmb"; - reg = <0x4800c0 0x10>; - #reset-cells = <2>; - }; - - pmb1: reset-controller@4800e0 { - compatible = "brcm,bcm63138-pmb"; - reg = <0x4800e0 0x10>; - #reset-cells = <2>; - }; - - ahci: sata@a000 { - compatible = "brcm,bcm63138-ahci", "brcm,sata3-ahci"; - reg-names = "ahci", "top-ctrl"; - reg = <0xa000 0x9ac>, <0x8040 0x24>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - resets = <&pmb0 3 1>; - reset-names = "ahci"; - status = "disabled"; - - sata0: sata-port@0 { - reg = <0>; - phys = <&sata_phy0>; - }; - }; - - sata_phy: sata-phy@8100 { - compatible = "brcm,bcm63138-sata-phy", "brcm,phy-sata3"; - reg = <0x8100 0x1e00>; - reg-names = "phy"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - sata_phy0: sata-phy@0 { - reg = <0>; - #phy-cells = <0>; - }; - }; - }; - - /* Legacy UBUS base */ - ubus@fffe8000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0xfffe8000 0x8100>; - - timer: timer@80 { - compatible = "brcm,bcm6328-timer", "syscon"; - reg = <0x80 0x3c>; - }; - - serial0: serial@600 { - compatible = "brcm,bcm6345-uart"; - reg = <0x600 0x1b>; - interrupts = ; - clocks = <&periph_clk>; - clock-names = "periph"; - status = "disabled"; - }; - - serial1: serial@620 { - compatible = "brcm,bcm6345-uart"; - reg = <0x620 0x1b>; - interrupts = ; - clocks = <&periph_clk>; - clock-names = "periph"; - status = "disabled"; - }; - - nand: nand@2000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.0", "brcm,brcmnand"; - reg = <0x2000 0x600>, <0xf0 0x10>; - reg-names = "nand", "nand-int-base"; - status = "disabled"; - interrupts = ; - interrupt-names = "nand"; - }; - - bootlut: bootlut@8000 { - compatible = "brcm,bcm63138-bootlut"; - reg = <0x8000 0x50>; - }; - - reboot { - compatible = "syscon-reboot"; - regmap = <&timer>; - offset = <0x34>; - mask = <1>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/bcm7445-bcm97445svmb.dts b/sys/gnu/dts/arm/bcm7445-bcm97445svmb.dts deleted file mode 100644 index 8313b7cad54..00000000000 --- a/sys/gnu/dts/arm/bcm7445-bcm97445svmb.dts +++ /dev/null @@ -1,38 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; -#include "bcm7445.dtsi" - -/ { - model = "Broadcom STB (bcm7445), SVMB reference board"; - compatible = "brcm,bcm7445", "brcm,brcmstb"; - - memory@0 { - device_type = "memory"; - reg = <0x00 0x00000000 0x00 0x40000000>, - <0x00 0x40000000 0x00 0x40000000>, - <0x00 0x80000000 0x00 0x40000000>; - }; -}; - -&nand { - status = "okay"; - - nandcs@1 { - compatible = "brcm,nandcs"; - reg = <1>; - nand-ecc-step-size = <512>; - nand-ecc-strength = <8>; - nand-on-flash-bbt; - - #size-cells = <2>; - #address-cells = <2>; - - flash1.rootfs0@0 { - reg = <0x0 0x0 0x0 0x80000000>; - }; - - flash1.rootfs1@80000000 { - reg = <0x0 0x80000000 0x0 0x80000000>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/bcm7445.dtsi b/sys/gnu/dts/arm/bcm7445.dtsi deleted file mode 100644 index 58f67c9b830..00000000000 --- a/sys/gnu/dts/arm/bcm7445.dtsi +++ /dev/null @@ -1,315 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include - -/ { - #address-cells = <2>; - #size-cells = <2>; - model = "Broadcom STB (bcm7445)"; - compatible = "brcm,bcm7445", "brcm,brcmstb"; - interrupt-parent = <&gic>; - - chosen { - bootargs = "console=ttyS0,115200 earlyprintk"; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "brcm,brahma-b15"; - device_type = "cpu"; - enable-method = "brcm,brahma-b15"; - reg = <0>; - }; - - cpu@1 { - compatible = "brcm,brahma-b15"; - device_type = "cpu"; - enable-method = "brcm,brahma-b15"; - reg = <1>; - }; - - cpu@2 { - compatible = "brcm,brahma-b15"; - device_type = "cpu"; - enable-method = "brcm,brahma-b15"; - reg = <2>; - }; - - cpu@3 { - compatible = "brcm,brahma-b15"; - device_type = "cpu"; - enable-method = "brcm,brahma-b15"; - reg = <3>; - }; - }; - - gic: interrupt-controller@ffd00000 { - compatible = "brcm,brahma-b15-gic", "arm,cortex-a15-gic"; - reg = <0x00 0xffd01000 0x00 0x1000>, - <0x00 0xffd02000 0x00 0x2000>, - <0x00 0xffd04000 0x00 0x2000>, - <0x00 0xffd06000 0x00 0x2000>; - interrupt-controller; - #interrupt-cells = <3>; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; - }; - - rdb@f0000000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0 0x00 0xf0000000 0x1000000>; - - serial@40ab00 { - compatible = "ns16550a"; - reg = <0x40ab00 0x20>; - reg-shift = <2>; - reg-io-width = <4>; - interrupts = ; - clock-frequency = <81000000>; - }; - - sun_top_ctrl: syscon@404000 { - compatible = "brcm,bcm7445-sun-top-ctrl", - "syscon"; - reg = <0x404000 0x51c>; - }; - - hif_cpubiuctrl: syscon@3e2400 { - compatible = "brcm,bcm7445-hif-cpubiuctrl", - "syscon"; - reg = <0x3e2400 0x5b4>; - }; - - hif_continuation: syscon@452000 { - compatible = "brcm,bcm7445-hif-continuation", - "syscon"; - reg = <0x452000 0x100>; - }; - - irq0_intc: interrupt-controller@40a780 { - compatible = "brcm,bcm7120-l2-intc"; - interrupt-parent = <&gic>; - #interrupt-cells = <1>; - reg = <0x40a780 0x8>; - interrupt-controller; - interrupts = , - ; - brcm,int-map-mask = <0x25c>, <0x7000000>; - brcm,int-fwd-mask = <0x70000>; - }; - - irq0_aon_intc: interrupt-controller@417280 { - compatible = "brcm,bcm7120-l2-intc"; - reg = <0x417280 0x8>; - interrupt-parent = <&gic>; - #interrupt-cells = <1>; - interrupt-controller; - interrupts = , - , - ; - brcm,int-map-mask = <0x1e3 0x18000000 0x100000>; - brcm,int-fwd-mask = <0x0>; - brcm,irq-can-wake; - }; - - hif_intr2_intc: interrupt-controller@3e1000 { - compatible = "brcm,l2-intc"; - reg = <0x3e1000 0x30>; - interrupt-controller; - #interrupt-cells = <1>; - interrupts = ; - interrupt-parent = <&gic>; - interrupt-names = "hif"; - }; - - aon_pm_l2_intc: interrupt-controller@410640 { - compatible = "brcm,l2-intc"; - reg = <0x410640 0x30>; - interrupt-controller; - #interrupt-cells = <1>; - interrupts = ; - interrupt-parent = <&gic>; - brcm,irq-can-wake; - }; - - aon-ctrl@410000 { - compatible = "brcm,brcmstb-aon-ctrl"; - reg = <0x410000 0x200>, <0x410200 0x400>; - reg-names = "aon-ctrl", "aon-sram"; - }; - - nand: nand@3e2800 { - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - compatible = "brcm,brcmnand-v7.1", "brcm,brcmnand"; - reg-names = "nand", "flash-dma"; - reg = <0x3e2800 0x600>, <0x3e3000 0x2c>; - interrupt-parent = <&hif_intr2_intc>; - interrupts = <24>, <4>; - interrupt-names = "nand_ctlrdy", "flash_dma_done"; - }; - - sata@45a000 { - compatible = "brcm,bcm7445-ahci", "brcm,sata3-ahci"; - reg-names = "ahci", "top-ctrl"; - reg = <0x45a000 0xa9c>, <0x458040 0x24>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - - sata0: sata-port@0 { - reg = <0>; - phys = <&sata_phy0>; - }; - - sata1: sata-port@1 { - reg = <1>; - phys = <&sata_phy1>; - }; - }; - - sata_phy: sata-phy@458100 { - compatible = "brcm,bcm7445-sata-phy", "brcm,phy-sata3"; - reg = <0x458100 0x1f00>; - reg-names = "phy"; - #address-cells = <0x1>; - #size-cells = <0x0>; - - sata_phy0: sata-phy@0 { - reg = <0>; - #phy-cells = <0>; - }; - - sata_phy1: sata-phy@1 { - reg = <1>; - #phy-cells = <0>; - }; - }; - - upg_gio: gpio@40a700 { - compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio"; - reg = <0x40a700 0x80>; - #gpio-cells = <2>; - #interrupt-cells = <2>; - gpio-controller; - interrupt-controller; - interrupt-parent = <&irq0_intc>; - interrupts = <6>; - brcm,gpio-bank-widths = <32 32 32 24>; - }; - - upg_gio_aon: gpio@4172c0 { - compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio"; - reg = <0x4172c0 0x40>; - #gpio-cells = <2>; - #interrupt-cells = <2>; - gpio-controller; - interrupt-controller; - interrupts-extended = <&irq0_aon_intc 0x6>, - <&aon_pm_l2_intc 0x5>; - wakeup-source; - brcm,gpio-bank-widths = <18 4>; - }; - - }; - - memory_controllers@f1100000 { - compatible = "simple-bus"; - ranges = <0x0 0x0 0xf1100000 0x200000>; - #address-cells = <1>; - #size-cells = <1>; - - memc@0 { - compatible = "brcm,brcmstb-memc", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x80000>; - - memc-ddr@2000 { - compatible = "brcm,brcmstb-memc-ddr"; - reg = <0x2000 0x800>; - }; - - ddr-phy@6000 { - compatible = "brcm,brcmstb-ddr-phy-v240.1"; - reg = <0x6000 0x21c>; - }; - - shimphy@8000 { - compatible = "brcm,brcmstb-ddr-shimphy-v1.0"; - reg = <0x8000 0xe4>; - }; - }; - - memc@80000 { - compatible = "brcm,brcmstb-memc", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x80000 0x80000>; - - memc-ddr@2000 { - compatible = "brcm,brcmstb-memc-ddr"; - reg = <0x2000 0x800>; - }; - - ddr-phy@6000 { - compatible = "brcm,brcmstb-ddr-phy-v240.1"; - reg = <0x6000 0x21c>; - }; - - shimphy@8000 { - compatible = "brcm,brcmstb-ddr-shimphy-v1.0"; - reg = <0x8000 0xe4>; - }; - }; - - memc@100000 { - compatible = "brcm,brcmstb-memc", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x100000 0x80000>; - - memc-ddr@2000 { - compatible = "brcm,brcmstb-memc-ddr"; - reg = <0x2000 0x800>; - }; - - ddr-phy@6000 { - compatible = "brcm,brcmstb-ddr-phy-v240.1"; - reg = <0x6000 0x21c>; - }; - - shimphy@8000 { - compatible = "brcm,brcmstb-ddr-shimphy-v1.0"; - reg = <0x8000 0xe4>; - }; - }; - }; - - sram@ffe00000 { - compatible = "brcm,boot-sram", "mmio-sram"; - reg = <0x0 0xffe00000 0x0 0x10000>; - }; - - smpboot { - compatible = "brcm,brcmstb-smpboot"; - syscon-cpu = <&hif_cpubiuctrl 0x88 0x178>; - syscon-cont = <&hif_continuation>; - }; - - reboot { - compatible = "brcm,brcmstb-reboot"; - syscon = <&sun_top_ctrl 0x304 0x308>; - }; -}; diff --git a/sys/gnu/dts/arm/bcm911360_entphn.dts b/sys/gnu/dts/arm/bcm911360_entphn.dts deleted file mode 100644 index b2d323f4a5a..00000000000 --- a/sys/gnu/dts/arm/bcm911360_entphn.dts +++ /dev/null @@ -1,99 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright(c) 2014 Broadcom Corporation. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/dts-v1/; - -#include "bcm-cygnus.dtsi" -#include "dt-bindings/input/input.h" - -/ { - model = "Cygnus Enterprise Phone (BCM911360_ENTPHN)"; - compatible = "brcm,bcm11360", "brcm,cygnus"; - - aliases { - serial0 = &uart3; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - gpio_keys { - compatible = "gpio-keys"; - - hook { - label = "HOOK"; - linux,code = ; - gpios = <&gpio_asiu 48 0>; - }; - }; -}; - -ð0 { - status = "okay"; -}; - -&mdio { - status = "okay"; -}; - -&switch { - status = "okay"; -}; - -&v3d { - assigned-clocks = - <&mipipll BCM_CYGNUS_MIPIPLL>, - <&mipipll BCM_CYGNUS_MIPIPLL_CH2_V3D>; - assigned-clock-rates = <525000000>, <300000000>; - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&nand { - nandcs@1 { - compatible = "brcm,nandcs"; - reg = <0>; - nand-on-flash-bbt; - - #address-cells = <1>; - #size-cells = <1>; - - nand-ecc-strength = <24>; - nand-ecc-step-size = <1024>; - - brcm,nand-oob-sector-size = <27>; - }; -}; diff --git a/sys/gnu/dts/arm/bcm911360k.dts b/sys/gnu/dts/arm/bcm911360k.dts deleted file mode 100644 index 091c73a46e0..00000000000 --- a/sys/gnu/dts/arm/bcm911360k.dts +++ /dev/null @@ -1,52 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright(c) 2014 Broadcom Corporation. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/dts-v1/; - -#include "bcm-cygnus.dtsi" - -/ { - model = "Cygnus SVK (BCM911360K)"; - compatible = "brcm,bcm11360", "brcm,cygnus"; - - aliases { - serial0 = &uart3; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&uart3 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/bcm94708.dts b/sys/gnu/dts/arm/bcm94708.dts deleted file mode 100644 index 3d13e46c694..00000000000 --- a/sys/gnu/dts/arm/bcm94708.dts +++ /dev/null @@ -1,49 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright(c) 2015 Broadcom Corporation. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/dts-v1/; - -#include "bcm4708.dtsi" - -/ { - model = "NorthStar SVK (BCM94708)"; - compatible = "brcm,bcm94708", "brcm,bcm4708"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x08000000>; - }; -}; - -&usb3_phy { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/bcm94709.dts b/sys/gnu/dts/arm/bcm94709.dts deleted file mode 100644 index 5017b7b259c..00000000000 --- a/sys/gnu/dts/arm/bcm94709.dts +++ /dev/null @@ -1,49 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright(c) 2015 Broadcom Corporation. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/dts-v1/; - -#include "bcm4708.dtsi" - -/ { - model = "NorthStar SVK (BCM94709)"; - compatible = "brcm,bcm94709", "brcm,bcm4709", "brcm,bcm4708"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x08000000>; - }; -}; - -&usb3_phy { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/bcm947189acdbmr.dts b/sys/gnu/dts/arm/bcm947189acdbmr.dts deleted file mode 100644 index b0b8c774a37..00000000000 --- a/sys/gnu/dts/arm/bcm947189acdbmr.dts +++ /dev/null @@ -1,96 +0,0 @@ -/* - * Copyright (C) 2017 Broadcom - * Author: Florian Fainelli - * - * Licensed under the ISC license. - */ - -/dts-v1/; - -#include "bcm53573.dtsi" - -/ { - compatible = "brcm,bcm947189acdbmr", "brcm,bcm47189", "brcm,bcm53573"; - model = "Broadcom BCM947189ACDBMR"; - - chosen { - bootargs = "console=ttyS0,115200 earlycon"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x08000000>; - }; - - leds { - compatible = "gpio-leds"; - - wps { - label = "bcm53xx:blue:wps"; - gpios = <&chipcommon 10 GPIO_ACTIVE_HIGH>; - }; - - 5ghz { - label = "bcm53xx:blue:5ghz"; - gpios = <&chipcommon 11 GPIO_ACTIVE_HIGH>; - }; - - 2ghz { - label = "bcm53xx:blue:2ghz"; - gpios = <&chipcommon 12 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 7 GPIO_ACTIVE_HIGH>; - }; - - wps { - label = "WPS"; - linux,code = ; - gpios = <&chipcommon 9 GPIO_ACTIVE_LOW>; - }; - }; - - spi { - compatible = "spi-gpio"; - num-chipselects = <1>; - gpio-sck = <&chipcommon 21 0>; - gpio-miso = <&chipcommon 22 0>; - gpio-mosi = <&chipcommon 23 0>; - cs-gpios = <&chipcommon 24 0>; - #address-cells = <1>; - #size-cells = <0>; - - /* External BCM6802 MoCA chip is connected */ - }; -}; - -&pcie0 { - ranges = <0x00000000 0 0 0 0 0x00100000>; - #address-cells = <3>; - #size-cells = <2>; - - bridge@0,0,0 { - reg = <0x0000 0 0 0 0>; - ranges = <0x00000000 0 0 0 0 0 0 0x00100000>; - #address-cells = <3>; - #size-cells = <2>; - - wifi@0,1,0 { - reg = <0x0000 0 0 0 0>; - ranges = <0x00000000 0 0 0 0x00100000>; - #address-cells = <1>; - #size-cells = <1>; - }; - }; -}; - -&usb2 { - vcc-gpio = <&chipcommon 8 GPIO_ACTIVE_HIGH>; -}; diff --git a/sys/gnu/dts/arm/bcm953012er.dts b/sys/gnu/dts/arm/bcm953012er.dts deleted file mode 100644 index 95746822462..00000000000 --- a/sys/gnu/dts/arm/bcm953012er.dts +++ /dev/null @@ -1,95 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright(c) 2016 Broadcom. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/dts-v1/; - -#include "bcm4708.dtsi" -#include "bcm5301x-nand-cs0-bch8.dtsi" - -/ { - model = "NorthStar Enterprise Router (BCM953012ER)"; - compatible = "brcm,bcm953012er", "brcm,brcm53012", "brcm,bcm4708"; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - wps { - label = "WPS"; - linux,code = ; - gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>; - }; - - restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&spi_nor { - status = "okay"; -}; - -&srab { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "port0"; - }; - - port@1 { - reg = <1>; - label = "port1"; - }; - - port@5 { - reg = <5>; - label = "cpu"; - ethernet = <&gmac0>; - }; - }; -}; - -&usb3_phy { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/bcm953012hr.dts b/sys/gnu/dts/arm/bcm953012hr.dts deleted file mode 100644 index 9140be7ec05..00000000000 --- a/sys/gnu/dts/arm/bcm953012hr.dts +++ /dev/null @@ -1,102 +0,0 @@ -/* - * SPDX-License-Identifier: BSD-3-Clause - * - * Copyright(c) 2017 Broadcom - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom nor the names of its contributors - * may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/dts-v1/; - -#include "bcm4708.dtsi" -#include "bcm5301x-nand-cs0-bch4.dtsi" - -/ { - model = "NorthStar HR (BCM953012HR)"; - compatible = "brcm,bcm953012hr", "brcm,brcm53012", "brcm,bcm4708"; - - aliases { - ethernet0 = &gmac0; - ethernet1 = &gmac1; - ethernet2 = &gmac2; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x10000000>; - }; -}; - -&nandcs { - partition@0 { - label = "nboot"; - reg = <0x00000000 0x00200000>; - read-only; - }; - partition@200000 { - label = "nenv"; - reg = <0x00200000 0x00400000>; - }; - partition@600000 { - label = "nsystem"; - reg = <0x00600000 0x00a00000>; - }; - partition@1000000 { - label = "nrootfs"; - reg = <0x01000000 0x07000000>; - }; -}; - -&spi_nor { - status = "okay"; - spi-max-frequency = <62500000>; - m25p,default-addr-width = <3>; - - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "boot"; - reg = <0x00000000 0x000d0000>; - }; - partition@d000 { - label = "env"; - reg = <0x000d0000 0x00030000>; - }; - partition@100000 { - label = "system"; - reg = <0x00100000 0x00600000>; - }; - partition@700000 { - label = "rootfs"; - reg = <0x00700000 0x00900000>; - }; -}; - -&usb3_phy { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/bcm953012k.dts b/sys/gnu/dts/arm/bcm953012k.dts deleted file mode 100644 index 046c59fb484..00000000000 --- a/sys/gnu/dts/arm/bcm953012k.dts +++ /dev/null @@ -1,120 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright(c) 2015 Broadcom Corporation. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/dts-v1/; - -#include "bcm4708.dtsi" - -/ { - model = "NorthStar SVK (BCM953012K)"; - compatible = "brcm,bcm953012k", "brcm,brcm53012", "brcm,bcm4708"; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x10000000>; - }; -}; - -&nand { - nandcs@0 { - compatible = "brcm,nandcs"; - reg = <0>; - nand-on-flash-bbt; - - #address-cells = <1>; - #size-cells = <1>; - - nand-ecc-strength = <4>; - nand-ecc-step-size = <512>; - - partition@0 { - label = "nboot"; - reg = <0x00000000 0x00200000>; - read-only; - }; - partition@200000 { - label = "nenv"; - reg = <0x00200000 0x00400000>; - }; - partition@600000 { - label = "nsystem"; - reg = <0x00600000 0x00a00000>; - }; - partition@1000000 { - label = "nrootfs"; - reg = <0x01000000 0x07000000>; - }; - }; -}; - -&spi_nor { - status = "okay"; - spi-max-frequency = <62500000>; - m25p,default-addr-width = <3>; - - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "boot"; - reg = <0x00000000 0x000d0000>; - }; - partition@d000 { - label = "env"; - reg = <0x000d0000 0x00030000>; - }; - partition@100000 { - label = "system"; - reg = <0x00100000 0x00600000>; - }; - partition@700000 { - label = "rootfs"; - reg = <0x00700000 0x00900000>; - }; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&usb3_phy { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/bcm958300k.dts b/sys/gnu/dts/arm/bcm958300k.dts deleted file mode 100644 index b4a1392bd5a..00000000000 --- a/sys/gnu/dts/arm/bcm958300k.dts +++ /dev/null @@ -1,77 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright(c) 2014 Broadcom Corporation. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/dts-v1/; - -#include "bcm-cygnus.dtsi" -#include "bcm9hmidc.dtsi" - -/ { - model = "Cygnus SVK (BCM958300K)"; - compatible = "brcm,bcm58300", "brcm,cygnus"; - - aliases { - serial0 = &uart3; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&pcie0 { - status = "okay"; -}; - -&pcie1 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&nand { - nandcs@1 { - compatible = "brcm,nandcs"; - reg = <0>; - nand-on-flash-bbt; - - #address-cells = <1>; - #size-cells = <1>; - - nand-ecc-strength = <24>; - nand-ecc-step-size = <1024>; - - brcm,nand-oob-sector-size = <27>; - }; -}; diff --git a/sys/gnu/dts/arm/bcm958305k.dts b/sys/gnu/dts/arm/bcm958305k.dts deleted file mode 100644 index 3378683321d..00000000000 --- a/sys/gnu/dts/arm/bcm958305k.dts +++ /dev/null @@ -1,85 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright(c) 2015 Broadcom Corporation. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/dts-v1/; - -#include "bcm-cygnus.dtsi" -#include "bcm9hmidc.dtsi" - -/ { - model = "Cygnus Wireless Audio (BCM958305K)"; - compatible = "brcm,bcm58305", "brcm,cygnus"; - - aliases { - serial0 = &uart3; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&i2c0 { - status = "okay"; -}; - -&i2c1 { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; - -&pcie1 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&nand { - nandcs@1 { - compatible = "brcm,nandcs"; - reg = <0>; - nand-on-flash-bbt; - - #address-cells = <1>; - #size-cells = <1>; - - nand-ecc-strength = <24>; - nand-ecc-step-size = <1024>; - - brcm,nand-oob-sector-size = <27>; - }; -}; diff --git a/sys/gnu/dts/arm/bcm958522er.dts b/sys/gnu/dts/arm/bcm958522er.dts deleted file mode 100644 index 8c388eb8a08..00000000000 --- a/sys/gnu/dts/arm/bcm958522er.dts +++ /dev/null @@ -1,176 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright(c) 2016 Broadcom. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/dts-v1/; - -#include "bcm-nsp.dtsi" -#include - -/ { - model = "NorthStar Plus SVK (BCM958522ER)"; - compatible = "brcm,bcm58522", "brcm,nsp"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@60000000 { - device_type = "memory"; - reg = <0x60000000 0x80000000>; - }; - - gpio-restart { - compatible = "gpio-restart"; - gpios = <&gpioa 15 GPIO_ACTIVE_LOW>; - open-source; - priority = <200>; - }; -}; - -/* USB 3 support needed to be complete */ - -&amac0 { - status = "okay"; -}; - -&amac1 { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&nand { - nandcs@0 { - compatible = "brcm,nandcs"; - reg = <0>; - nand-on-flash-bbt; - - #address-cells = <1>; - #size-cells = <1>; - - nand-ecc-strength = <24>; - nand-ecc-step-size = <1024>; - - brcm,nand-oob-sector-size = <27>; - - partition@0 { - label = "nboot"; - reg = <0x00000000 0x00200000>; - read-only; - }; - partition@200000 { - label = "nenv"; - reg = <0x00200000 0x00400000>; - }; - partition@600000 { - label = "nsystem"; - reg = <0x00600000 0x00a00000>; - }; - partition@1000000 { - label = "nrootfs"; - reg = <0x01000000 0x03000000>; - }; - partition@4000000 { - label = "ncustfs"; - reg = <0x04000000 0x3c000000>; - }; - }; -}; - -&ohci0 { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; - -&pcie1 { - status = "okay"; -}; - -&pinctrl { - pinctrl-names = "default"; - pinctrl-0 = <&nand_sel>; - nand_sel: nand_sel { - function = "nand"; - groups = "nand_grp"; - }; -}; - -&qspi { - bspi-sel = <0>; - flash: m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "m25p80"; - reg = <0x0>; - spi-max-frequency = <12500000>; - m25p,fast-read; - spi-cpol; - spi-cpha; - - partition@0 { - label = "boot"; - reg = <0x00000000 0x000a0000>; - }; - - partition@a0000 { - label = "env"; - reg = <0x000a0000 0x00060000>; - }; - - partition@100000 { - label = "system"; - reg = <0x00100000 0x00600000>; - }; - - partition@700000 { - label = "rootfs"; - reg = <0x00700000 0x01900000>; - }; - }; -}; - -&uart0 { - status = "okay"; -}; - -&usb3_phy { - status = "okay"; -}; - -&xhci { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/bcm958525er.dts b/sys/gnu/dts/arm/bcm958525er.dts deleted file mode 100644 index c339771bb22..00000000000 --- a/sys/gnu/dts/arm/bcm958525er.dts +++ /dev/null @@ -1,188 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright(c) 2016 Broadcom. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/dts-v1/; - -#include "bcm-nsp.dtsi" -#include - -/ { - model = "NorthStar Plus SVK (BCM958525ER)"; - compatible = "brcm,bcm58525", "brcm,nsp"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@60000000 { - device_type = "memory"; - reg = <0x60000000 0x80000000>; - }; - - gpio-restart { - compatible = "gpio-restart"; - gpios = <&gpioa 15 GPIO_ACTIVE_LOW>; - open-source; - priority = <200>; - }; -}; - -/* USB 3 support needed to be complete */ - -&amac0 { - status = "okay"; -}; - -&amac1 { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&nand { - nandcs@0 { - compatible = "brcm,nandcs"; - reg = <0>; - nand-on-flash-bbt; - - #address-cells = <1>; - #size-cells = <1>; - - nand-ecc-strength = <24>; - nand-ecc-step-size = <1024>; - - brcm,nand-oob-sector-size = <27>; - - partition@0 { - label = "nboot"; - reg = <0x00000000 0x00200000>; - read-only; - }; - partition@200000 { - label = "nenv"; - reg = <0x00200000 0x00400000>; - }; - partition@600000 { - label = "nsystem"; - reg = <0x00600000 0x00a00000>; - }; - partition@1000000 { - label = "nrootfs"; - reg = <0x01000000 0x03000000>; - }; - partition@4000000 { - label = "ncustfs"; - reg = <0x04000000 0x3c000000>; - }; - }; -}; - -&ohci0 { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; - -&pcie1 { - status = "okay"; -}; - -&pinctrl { - pinctrl-names = "default"; - pinctrl-0 = <&nand_sel>; - nand_sel: nand_sel { - function = "nand"; - groups = "nand_grp"; - }; -}; - -&qspi { - bspi-sel = <0>; - flash: m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "m25p80"; - reg = <0x0>; - spi-max-frequency = <12500000>; - m25p,fast-read; - spi-cpol; - spi-cpha; - - partition@0 { - label = "boot"; - reg = <0x00000000 0x000a0000>; - }; - - partition@a0000 { - label = "env"; - reg = <0x000a0000 0x00060000>; - }; - - partition@100000 { - label = "system"; - reg = <0x00100000 0x00600000>; - }; - - partition@700000 { - label = "rootfs"; - reg = <0x00700000 0x01900000>; - }; - }; -}; - -&sata_phy0 { - status = "okay"; -}; - -&sata_phy1 { - status = "okay"; -}; - -&sata { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&usb3_phy { - status = "okay"; -}; - -&xhci { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/bcm958525xmc.dts b/sys/gnu/dts/arm/bcm958525xmc.dts deleted file mode 100644 index 1c72ec8288d..00000000000 --- a/sys/gnu/dts/arm/bcm958525xmc.dts +++ /dev/null @@ -1,208 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright(c) 2016 Broadcom. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/dts-v1/; - -#include "bcm-nsp.dtsi" -#include - -/ { - model = "NorthStar Plus XMC (BCM958525xmc)"; - compatible = "brcm,bcm58525", "brcm,nsp"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@60000000 { - device_type = "memory"; - reg = <0x60000000 0x40000000>; - }; - - gpio-restart { - compatible = "gpio-restart"; - gpios = <&gpioa 31 GPIO_ACTIVE_LOW>; - open-source; - priority = <200>; - }; -}; - -/* XHCI support needed to be complete */ - -&amac0 { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - temperature-sensor@4c { - compatible = "adi,adt7461a"; - reg = <0x4c>; - }; - - eeprom@52 { - compatible = "atmel,24c02"; - reg = <0x52>; - pagesize = <16>; - }; - - rtc@68 { - compatible = "st,m41t81"; - reg = <0x68>; - }; -}; - -&nand { - nandcs@0 { - compatible = "brcm,nandcs"; - reg = <0>; - nand-on-flash-bbt; - - #address-cells = <1>; - #size-cells = <1>; - - nand-ecc-strength = <24>; - nand-ecc-step-size = <1024>; - - brcm,nand-oob-sector-size = <27>; - - partition@0 { - label = "nboot"; - reg = <0x00000000 0x00200000>; - read-only; - }; - partition@200000 { - label = "nenv"; - reg = <0x00200000 0x00400000>; - }; - partition@600000 { - label = "nsystem"; - reg = <0x00600000 0x00a00000>; - }; - partition@1000000 { - label = "nrootfs"; - reg = <0x01000000 0x03000000>; - }; - partition@4000000 { - label = "ncustfs"; - reg = <0x04000000 0x3c000000>; - }; - }; -}; - -&ohci0 { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; - -&pcie1 { - status = "okay"; -}; - -&pinctrl { - pinctrl-names = "default"; - pinctrl-0 = <&nand_sel>; - nand_sel: nand_sel { - function = "nand"; - groups = "nand_grp"; - }; -}; - -&qspi { - bspi-sel = <0>; - flash: m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "m25p80"; - reg = <0x0>; - spi-max-frequency = <12500000>; - m25p,fast-read; - spi-cpol; - spi-cpha; - - partition@0 { - label = "boot"; - reg = <0x00000000 0x000a0000>; - }; - - partition@a0000 { - label = "env"; - reg = <0x000a0000 0x00060000>; - }; - - partition@100000 { - label = "system"; - reg = <0x00100000 0x00600000>; - }; - - partition@700000 { - label = "rootfs"; - reg = <0x00700000 0x01900000>; - }; - }; -}; - -&sata_phy0 { - status = "okay"; -}; - -&sata_phy1 { - status = "okay"; -}; - -&sata { - status = "okay"; -}; - -&sdio { - status = "ok"; -}; - -&uart0 { - status = "okay"; -}; - -&usb3_phy { - status = "okay"; -}; - -&xhci { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/bcm958622hr.dts b/sys/gnu/dts/arm/bcm958622hr.dts deleted file mode 100644 index 96a021cebd9..00000000000 --- a/sys/gnu/dts/arm/bcm958622hr.dts +++ /dev/null @@ -1,225 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright(c) 2016 Broadcom. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/dts-v1/; - -#include "bcm-nsp.dtsi" -#include - -/ { - model = "NorthStar Plus SVK (BCM958622HR)"; - compatible = "brcm,bcm58622", "brcm,nsp"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@60000000 { - device_type = "memory"; - reg = <0x60000000 0x80000000>; - }; - - gpio-restart { - compatible = "gpio-restart"; - gpios = <&gpioa 15 GPIO_ACTIVE_LOW>; - open-source; - priority = <200>; - }; -}; - -/* USB 3 and SLIC support needed to be complete */ - -&amac0 { - status = "okay"; -}; - -&amac1 { - status = "okay"; -}; - -&amac2 { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&nand { - nandcs@0 { - compatible = "brcm,nandcs"; - reg = <0>; - nand-on-flash-bbt; - - #address-cells = <1>; - #size-cells = <1>; - - nand-ecc-strength = <24>; - nand-ecc-step-size = <1024>; - - brcm,nand-oob-sector-size = <27>; - - partition@0 { - label = "nboot"; - reg = <0x00000000 0x00200000>; - read-only; - }; - partition@200000 { - label = "nenv"; - reg = <0x00200000 0x00400000>; - }; - partition@600000 { - label = "nsystem"; - reg = <0x00600000 0x00a00000>; - }; - partition@1000000 { - label = "nrootfs"; - reg = <0x01000000 0x03000000>; - }; - partition@4000000 { - label = "ncustfs"; - reg = <0x04000000 0x3c000000>; - }; - }; -}; - -&ohci0 { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; - -&pcie1 { - status = "okay"; -}; - -&pinctrl { - pinctrl-names = "default"; - pinctrl-0 = <&nand_sel>; - nand_sel: nand_sel { - function = "nand"; - groups = "nand_grp"; - }; -}; - -&qspi { - bspi-sel = <0>; - flash: m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "m25p80"; - reg = <0x0>; - spi-max-frequency = <12500000>; - m25p,fast-read; - spi-cpol; - spi-cpha; - - partition@0 { - label = "boot"; - reg = <0x00000000 0x000a0000>; - }; - - partition@a0000 { - label = "env"; - reg = <0x000a0000 0x00060000>; - }; - - partition@100000 { - label = "system"; - reg = <0x00100000 0x00600000>; - }; - - partition@700000 { - label = "rootfs"; - reg = <0x00700000 0x01900000>; - }; - }; -}; - -&srab { - compatible = "brcm,bcm58622-srab", "brcm,nsp-srab"; - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - label = "port0"; - reg = <0>; - }; - - port@1 { - label = "port1"; - reg = <1>; - }; - - port@2 { - label = "port2"; - reg = <2>; - }; - - port@3 { - label = "port3"; - reg = <3>; - }; - - port@4 { - label = "port4"; - reg = <4>; - }; - - port@8 { - ethernet = <&amac2>; - label = "cpu"; - reg = <8>; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; -}; - -&uart0 { - status = "okay"; -}; - -&usb3_phy { - status = "okay"; -}; - -&xhci { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/bcm958623hr.dts b/sys/gnu/dts/arm/bcm958623hr.dts deleted file mode 100644 index b2c7f21d471..00000000000 --- a/sys/gnu/dts/arm/bcm958623hr.dts +++ /dev/null @@ -1,229 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright(c) 2016 Broadcom. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/dts-v1/; - -#include "bcm-nsp.dtsi" -#include - -/ { - model = "NorthStar Plus SVK (BCM958623HR)"; - compatible = "brcm,bcm58623", "brcm,nsp"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@60000000 { - device_type = "memory"; - reg = <0x60000000 0x80000000>; - }; - - gpio-restart { - compatible = "gpio-restart"; - gpios = <&gpioa 15 GPIO_ACTIVE_LOW>; - open-source; - priority = <200>; - }; -}; - -/* USB 3 and SLIC support needed to be complete */ - -&amac0 { - status = "okay"; -}; - -&amac1 { - status = "okay"; -}; - -&amac2 { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&nand { - nandcs@0 { - compatible = "brcm,nandcs"; - reg = <0>; - nand-on-flash-bbt; - - #address-cells = <1>; - #size-cells = <1>; - - nand-ecc-strength = <24>; - nand-ecc-step-size = <1024>; - - brcm,nand-oob-sector-size = <27>; - - partition@0 { - label = "nboot"; - reg = <0x00000000 0x00200000>; - read-only; - }; - partition@200000 { - label = "nenv"; - reg = <0x00200000 0x00400000>; - }; - partition@600000 { - label = "nsystem"; - reg = <0x00600000 0x00a00000>; - }; - partition@1000000 { - label = "nrootfs"; - reg = <0x01000000 0x03000000>; - }; - partition@4000000 { - label = "ncustfs"; - reg = <0x04000000 0x3c000000>; - }; - }; -}; - -&ohci0 { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; - -&pcie1 { - status = "okay"; -}; - -&pinctrl { - pinctrl-names = "default"; - pinctrl-0 = <&nand_sel>; - nand_sel: nand_sel { - function = "nand"; - groups = "nand_grp"; - }; -}; - -&sata_phy0 { - status = "okay"; -}; - -&qspi { - bspi-sel = <0>; - flash: m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "m25p80"; - reg = <0x0>; - spi-max-frequency = <12500000>; - m25p,fast-read; - spi-cpol; - spi-cpha; - - partition@0 { - label = "boot"; - reg = <0x00000000 0x000a0000>; - }; - - partition@a0000 { - label = "env"; - reg = <0x000a0000 0x00060000>; - }; - - partition@100000 { - label = "system"; - reg = <0x00100000 0x00600000>; - }; - - partition@700000 { - label = "rootfs"; - reg = <0x00700000 0x01900000>; - }; - }; -}; - -&srab { - compatible = "brcm,bcm58623-srab", "brcm,nsp-srab"; - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - label = "port0"; - reg = <0>; - }; - - port@1 { - label = "port1"; - reg = <1>; - }; - - port@2 { - label = "port2"; - reg = <2>; - }; - - port@3 { - label = "port3"; - reg = <3>; - }; - - port@4 { - label = "port4"; - reg = <4>; - }; - - port@8 { - ethernet = <&amac2>; - label = "cpu"; - reg = <8>; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; -}; - -&uart0 { - status = "okay"; -}; - -&usb3_phy { - status = "okay"; -}; - -&xhci { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/bcm958625hr.dts b/sys/gnu/dts/arm/bcm958625hr.dts deleted file mode 100644 index 536fb24f38b..00000000000 --- a/sys/gnu/dts/arm/bcm958625hr.dts +++ /dev/null @@ -1,252 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright(c) 2016 Broadcom. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/dts-v1/; - -#include "bcm-nsp.dtsi" -#include - -/ { - model = "NorthStar Plus SVK (BCM958625HR)"; - compatible = "brcm,bcm58625", "brcm,nsp"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@60000000 { - device_type = "memory"; - reg = <0x60000000 0x20000000>; - }; - - gpio-restart { - compatible = "gpio-restart"; - gpios = <&gpioa 15 GPIO_ACTIVE_LOW>; - open-source; - priority = <200>; - }; - - sfp: sfp { - compatible = "sff,sfp"; - i2c-bus = <&i2c0>; - mod-def0-gpios = <&gpioa 28 GPIO_ACTIVE_LOW>; - los-gpios = <&gpioa 24 GPIO_ACTIVE_HIGH>; - tx-fault-gpios = <&gpioa 30 GPIO_ACTIVE_HIGH>; - tx-disable-gpios = <&gpioa 26 GPIO_ACTIVE_HIGH>; - }; -}; - -&i2c0 { - status = "okay"; -}; - -&amac0 { - status = "okay"; -}; - -&amac1 { - status = "okay"; -}; - -&amac2 { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&nand { - nandcs@0 { - compatible = "brcm,nandcs"; - reg = <0>; - nand-on-flash-bbt; - - #address-cells = <1>; - #size-cells = <1>; - - nand-ecc-strength = <24>; - nand-ecc-step-size = <1024>; - - brcm,nand-oob-sector-size = <27>; - - partition@0 { - label = "nboot"; - reg = <0x00000000 0x00200000>; - read-only; - }; - partition@200000 { - label = "nenv"; - reg = <0x00200000 0x00400000>; - }; - partition@600000 { - label = "nsystem"; - reg = <0x00600000 0x00a00000>; - }; - partition@1000000 { - label = "nrootfs"; - reg = <0x01000000 0x03000000>; - }; - partition@4000000 { - label = "ncustfs"; - reg = <0x04000000 0x3c000000>; - }; - }; -}; - -&ohci0 { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; - -&pcie1 { - status = "okay"; -}; - -&pinctrl { - pinctrl-names = "default"; - pinctrl-0 = <&nand_sel>; - nand_sel: nand_sel { - function = "nand"; - groups = "nand_grp"; - }; -}; - -&qspi { - bspi-sel = <0>; - flash: m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "m25p80"; - reg = <0x0>; - spi-max-frequency = <12500000>; - m25p,fast-read; - spi-cpol; - spi-cpha; - - partition@0 { - label = "boot"; - reg = <0x00000000 0x000a0000>; - }; - - partition@a0000 { - label = "env"; - reg = <0x000a0000 0x00060000>; - }; - - partition@100000 { - label = "system"; - reg = <0x00100000 0x00600000>; - }; - - partition@700000 { - label = "rootfs"; - reg = <0x00700000 0x01900000>; - }; - }; -}; - -&sata_phy0 { - status = "okay"; -}; - -&sata_phy1 { - status = "okay"; -}; - -&srab { - compatible = "brcm,bcm58625-srab", "brcm,nsp-srab"; - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - label = "port0"; - reg = <0>; - }; - - port@1 { - label = "port1"; - reg = <1>; - }; - - port@2 { - label = "port2"; - reg = <2>; - }; - - port@3 { - label = "port3"; - reg = <3>; - }; - - port@4 { - label = "port4"; - reg = <4>; - }; - - port@5 { - label = "sfp"; - phy-mode = "sgmii"; - reg = <5>; - sfp = <&sfp>; - managed = "in-band-status"; - }; - - port@8 { - ethernet = <&amac2>; - label = "cpu"; - reg = <8>; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; -}; - -&uart0 { - status = "okay"; -}; - -&usb3_phy { - status = "okay"; -}; - -&xhci { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/bcm958625k.dts b/sys/gnu/dts/arm/bcm958625k.dts deleted file mode 100644 index 3fcca12d83c..00000000000 --- a/sys/gnu/dts/arm/bcm958625k.dts +++ /dev/null @@ -1,269 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright(c) 2015 Broadcom Corporation. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/dts-v1/; - -#include "bcm-nsp.dtsi" - -/ { - model = "NorthStar Plus SVK (BCM958625K)"; - compatible = "brcm,bcm58625", "brcm,nsp"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@60000000 { - device_type = "memory"; - reg = <0x60000000 0x80000000>; - }; -}; - -&amac0 { - status = "okay"; -}; - -&amac1 { - status = "okay"; -}; - -&amac2 { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&nand { - nandcs@0 { - compatible = "brcm,nandcs"; - reg = <0>; - nand-on-flash-bbt; - - #address-cells = <1>; - #size-cells = <1>; - - nand-ecc-strength = <24>; - nand-ecc-step-size = <1024>; - - brcm,nand-oob-sector-size = <27>; - - partition@0 { - label = "nboot"; - reg = <0x00000000 0x00200000>; - read-only; - }; - partition@200000 { - label = "nenv"; - reg = <0x00200000 0x00400000>; - }; - partition@600000 { - label = "nsystem"; - reg = <0x00600000 0x00a00000>; - }; - partition@1000000 { - label = "nrootfs"; - reg = <0x01000000 0x03000000>; - }; - partition@4000000 { - label = "ncustfs"; - reg = <0x04000000 0x3c000000>; - }; - }; -}; - -&ohci0 { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; - -&pcie1 { - status = "okay"; -}; - -&pcie2 { - status = "okay"; -}; - -&pinctrl { - pinctrl-names = "default"; - pinctrl-0 = <&nand_sel>, <&gpiobs>, <&pwmc>; - - nand_sel: nand_sel { - function = "nand"; - groups = "nand_grp"; - }; - - gpiobs: gpiobs { - function = "gpio_b"; - groups = "gpio_b_0_grp", "gpio_b_1_grp", "gpio_b_2_grp", - "gpio_b_3_grp"; - }; - - pwmc: pwmc { - function = "pwm"; - groups = "pwm0_grp", "pwm1_grp", "pwm2_grp", "pwm3_grp"; - }; - - emmc_sel: emmc_sel { - function = "emmc"; - groups = "emmc_grp"; - }; -}; - -&pwm { - status = "okay"; -}; - -&qspi { - bspi-sel = <0>; - flash: m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "m25p80"; - reg = <0x0>; - spi-max-frequency = <12500000>; - m25p,fast-read; - spi-cpol; - spi-cpha; - - partition@0 { - label = "boot"; - reg = <0x00000000 0x000a0000>; - }; - - partition@a0000 { - label = "env"; - reg = <0x000a0000 0x00060000>; - }; - - partition@100000 { - label = "system"; - reg = <0x00100000 0x00600000>; - }; - - partition@700000 { - label = "rootfs"; - reg = <0x00700000 0x01900000>; - }; - }; -}; - -&sata_phy0 { - status = "okay"; -}; - -&sata_phy1 { - status = "okay"; -}; - -&sata { - status = "okay"; -}; - -/* - * By default the sd slot is functional. For emmc to work add "<&emmc_sel>" - * and delete "<&nand_sel>" in "pinctrl-0" property of pinctrl node. Remove the - * bus-width property here and disable the nand node with status = "disabled";. - * - * Ex: pinctrl-0 = <&emmc_sel>, <&gpiobs>, <&pwmc>; - */ -&sdio { - bus-width = <4>; - no-1-8-v; - status = "ok"; -}; - -&srab { - compatible = "brcm,bcm58625-srab", "brcm,nsp-srab"; - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - label = "port0"; - reg = <0>; - }; - - port@1 { - label = "port1"; - reg = <1>; - }; - - port@2 { - label = "port2"; - reg = <2>; - }; - - port@3 { - label = "port3"; - reg = <3>; - }; - - port@4 { - label = "port4"; - reg = <4>; - }; - - port@8 { - ethernet = <&amac2>; - label = "cpu"; - reg = <8>; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&usb3_phy { - status = "okay"; -}; - -&xhci { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/bcm963138dvt.dts b/sys/gnu/dts/arm/bcm963138dvt.dts deleted file mode 100644 index 5b177274f18..00000000000 --- a/sys/gnu/dts/arm/bcm963138dvt.dts +++ /dev/null @@ -1,52 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Broadcom BCM63138 Reference Board DTS - */ - -/dts-v1/; - -#include "bcm63138.dtsi" - -/ { - compatible = "brcm,BCM963138DVT", "brcm,bcm63138"; - model = "Broadcom BCM963138DVT"; - - chosen { - bootargs = "console=ttyS0,115200"; - stdout-path = &serial0; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x08000000>; - }; - -}; - -&serial0 { - status = "okay"; -}; - -&serial1 { - status = "okay"; -}; - -&nand { - status = "okay"; - - nandcs@0 { - compatible = "brcm,nandcs"; - reg = <0>; - nand-ecc-strength = <4>; - nand-ecc-step-size = <512>; - brcm,nand-oob-sectors-size = <16>; - }; -}; - -&ahci { - status = "okay"; -}; - -&sata_phy { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/bcm988312hr.dts b/sys/gnu/dts/arm/bcm988312hr.dts deleted file mode 100644 index edd0f630e02..00000000000 --- a/sys/gnu/dts/arm/bcm988312hr.dts +++ /dev/null @@ -1,229 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright(c) 2016 Broadcom. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/dts-v1/; - -#include "bcm-nsp.dtsi" -#include - -/ { - model = "NorthStar Plus SVK (BCM988312HR)"; - compatible = "brcm,bcm88312", "brcm,nsp"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@60000000 { - device_type = "memory"; - reg = <0x60000000 0x80000000>; - }; - - gpio-restart { - compatible = "gpio-restart"; - gpios = <&gpioa 15 GPIO_ACTIVE_LOW>; - open-source; - priority = <200>; - }; -}; - -/* USB 3 support needed to be complete */ - -&amac0 { - status = "okay"; -}; - -&amac1 { - status = "okay"; -}; - -&amac2 { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&nand { - nandcs@0 { - compatible = "brcm,nandcs"; - reg = <0>; - nand-on-flash-bbt; - - #address-cells = <1>; - #size-cells = <1>; - - nand-ecc-strength = <24>; - nand-ecc-step-size = <1024>; - - brcm,nand-oob-sector-size = <27>; - - partition@0 { - label = "nboot"; - reg = <0x00000000 0x00200000>; - read-only; - }; - partition@200000 { - label = "nenv"; - reg = <0x00200000 0x00400000>; - }; - partition@600000 { - label = "nsystem"; - reg = <0x00600000 0x00a00000>; - }; - partition@1000000 { - label = "nrootfs"; - reg = <0x01000000 0x03000000>; - }; - partition@4000000 { - label = "ncustfs"; - reg = <0x04000000 0x3c000000>; - }; - }; -}; - -&ohci0 { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; - -&pcie1 { - status = "okay"; -}; - -&pinctrl { - pinctrl-names = "default"; - pinctrl-0 = <&nand_sel>; - nand_sel: nand_sel { - function = "nand"; - groups = "nand_grp"; - }; -}; - -&qspi { - bspi-sel = <0>; - flash: m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "m25p80"; - reg = <0x0>; - spi-max-frequency = <12500000>; - m25p,fast-read; - spi-cpol; - spi-cpha; - - partition@0 { - label = "boot"; - reg = <0x00000000 0x000a0000>; - }; - - partition@a0000 { - label = "env"; - reg = <0x000a0000 0x00060000>; - }; - - partition@100000 { - label = "system"; - reg = <0x00100000 0x00600000>; - }; - - partition@700000 { - label = "rootfs"; - reg = <0x00700000 0x01900000>; - }; - }; -}; - -&sata_phy0 { - status = "okay"; -}; - -&sata_phy1 { - status = "okay"; -}; - -&sata { - status = "okay"; -}; - -&srab { - compatible = "brcm,bcm88312-srab", "brcm,nsp-srab"; - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - label = "port0"; - reg = <0>; - }; - - port@1 { - label = "port1"; - reg = <1>; - }; - - port@2 { - label = "port2"; - reg = <2>; - }; - - port@3 { - label = "port3"; - reg = <3>; - }; - - port@4 { - label = "port4"; - reg = <4>; - }; - - port@8 { - ethernet = <&amac2>; - label = "cpu"; - reg = <8>; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/bcm9hmidc.dtsi b/sys/gnu/dts/arm/bcm9hmidc.dtsi deleted file mode 100644 index 65397c08833..00000000000 --- a/sys/gnu/dts/arm/bcm9hmidc.dtsi +++ /dev/null @@ -1,42 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright(c) 2015 Broadcom Corporation. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/* - * Broadcom human machine interface daughter card (bcm9hmidc) installed on - * bcm958300k/bcm958305k boards - */ - -&touchscreen { - touchscreen-inverted-x; - touchscreen-inverted-y; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/berlin2-sony-nsz-gs7.dts b/sys/gnu/dts/arm/berlin2-sony-nsz-gs7.dts deleted file mode 100644 index 64a297759eb..00000000000 --- a/sys/gnu/dts/arm/berlin2-sony-nsz-gs7.dts +++ /dev/null @@ -1,43 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Device Tree file for Sony NSZ-GS7 - * - * Sebastian Hesselbarth - */ - -/dts-v1/; - -#include "berlin2.dtsi" - -/ { - model = "Sony NSZ-GS7"; - compatible = "sony,nsz-gs7", "marvell,berlin2", "marvell,berlin"; - - chosen { - bootargs = "earlyprintk"; - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x40000000>; /* 1 GB */ - }; -}; - -&ahci { status = "okay"; }; - -ð1 { status = "okay"; }; - -/* Unpopulated SATA plug on solder side */ -&sata0 { status = "okay"; }; - -&sata_phy { status = "okay"; }; - -/* Samsung M8G2FA 8GB eMMC */ -&sdhci2 { - non-removable; - bus-width = <8>; - status = "okay"; -}; - -&uart0 { status = "okay"; }; diff --git a/sys/gnu/dts/arm/berlin2.dtsi b/sys/gnu/dts/arm/berlin2.dtsi deleted file mode 100644 index d2f7d984bba..00000000000 --- a/sys/gnu/dts/arm/berlin2.dtsi +++ /dev/null @@ -1,540 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Device Tree Include file for Marvell Armada 1500 (Berlin BG2) SoC - * - * Sebastian Hesselbarth - * - * based on GPL'ed 2.6 kernel sources - * (c) Marvell International Ltd. - */ - -#include -#include - -/ { - model = "Marvell Armada 1500 (BG2) SoC"; - compatible = "marvell,berlin2", "marvell,berlin"; - #address-cells = <1>; - #size-cells = <1>; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "marvell,berlin-smp"; - - cpu@0 { - compatible = "marvell,pj4b"; - device_type = "cpu"; - next-level-cache = <&l2>; - reg = <0>; - - clocks = <&chip_clk CLKID_CPU>; - clock-latency = <100000>; - operating-points = < - /* kHz uV */ - 1200000 1200000 - 1000000 1200000 - 800000 1200000 - 600000 1200000 - >; - }; - - cpu@1 { - compatible = "marvell,pj4b"; - device_type = "cpu"; - next-level-cache = <&l2>; - reg = <1>; - - clocks = <&chip_clk CLKID_CPU>; - clock-latency = <100000>; - operating-points = < - /* kHz uV */ - 1200000 1200000 - 1000000 1200000 - 800000 1200000 - 600000 1200000 - >; - }; - }; - - refclk: oscillator { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - - soc@f7000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&gic>; - - ranges = <0 0xf7000000 0x1000000>; - - sdhci0: sdhci@ab0000 { - compatible = "mrvl,pxav3-mmc"; - reg = <0xab0000 0x200>; - clocks = <&chip_clk CLKID_SDIO0XIN>, <&chip_clk CLKID_SDIO0>; - clock-names = "io", "core"; - interrupts = ; - status = "disabled"; - }; - - sdhci1: sdhci@ab0800 { - compatible = "mrvl,pxav3-mmc"; - reg = <0xab0800 0x200>; - clocks = <&chip_clk CLKID_SDIO1XIN>, <&chip_clk CLKID_SDIO1>; - clock-names = "io", "core"; - interrupts = ; - status = "disabled"; - }; - - sdhci2: sdhci@ab1000 { - compatible = "mrvl,pxav3-mmc"; - reg = <0xab1000 0x200>; - interrupts = ; - clocks = <&chip_clk CLKID_NFC_ECC>, <&chip_clk CLKID_NFC>; - clock-names = "io", "core"; - pinctrl-0 = <&emmc_pmux>; - pinctrl-names = "default"; - status = "disabled"; - }; - - l2: l2-cache-controller@ac0000 { - compatible = "marvell,tauros3-cache", "arm,pl310-cache"; - reg = <0xac0000 0x1000>; - cache-unified; - cache-level = <2>; - }; - - scu: snoop-control-unit@ad0000 { - compatible = "arm,cortex-a9-scu"; - reg = <0xad0000 0x58>; - }; - - gic: interrupt-controller@ad1000 { - compatible = "arm,cortex-a9-gic"; - reg = <0xad1000 0x1000>, <0xad0100 0x0100>; - interrupt-controller; - #interrupt-cells = <3>; - }; - - local-timer@ad0600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0xad0600 0x20>; - interrupts = ; - clocks = <&chip_clk CLKID_TWD>; - }; - - eth1: ethernet@b90000 { - compatible = "marvell,pxa168-eth"; - reg = <0xb90000 0x10000>; - clocks = <&chip_clk CLKID_GETH1>; - interrupts = ; - /* set by bootloader */ - local-mac-address = [00 00 00 00 00 00]; - #address-cells = <1>; - #size-cells = <0>; - phy-connection-type = "mii"; - phy-handle = <ðphy1>; - status = "disabled"; - - ethphy1: ethernet-phy@0 { - reg = <0>; - }; - }; - - cpu-ctrl@dd0000 { - compatible = "marvell,berlin-cpu-ctrl"; - reg = <0xdd0000 0x10000>; - }; - - eth0: ethernet@e50000 { - compatible = "marvell,pxa168-eth"; - reg = <0xe50000 0x10000>; - clocks = <&chip_clk CLKID_GETH0>; - interrupts = ; - /* set by bootloader */ - local-mac-address = [00 00 00 00 00 00]; - #address-cells = <1>; - #size-cells = <0>; - phy-connection-type = "mii"; - phy-handle = <ðphy0>; - status = "disabled"; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; - }; - - apb@e80000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - - ranges = <0 0xe80000 0x10000>; - interrupt-parent = <&aic>; - - gpio0: gpio@400 { - compatible = "snps,dw-apb-gpio"; - reg = <0x0400 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - porta: gpio-port@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <8>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <0>; - }; - }; - - gpio1: gpio@800 { - compatible = "snps,dw-apb-gpio"; - reg = <0x0800 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - portb: gpio-port@1 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <8>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <1>; - }; - }; - - gpio2: gpio@c00 { - compatible = "snps,dw-apb-gpio"; - reg = <0x0c00 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - portc: gpio-port@2 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <8>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <2>; - }; - }; - - gpio3: gpio@1000 { - compatible = "snps,dw-apb-gpio"; - reg = <0x1000 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - portd: gpio-port@3 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <8>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <3>; - }; - }; - - timer0: timer@2c00 { - compatible = "snps,dw-apb-timer"; - reg = <0x2c00 0x14>; - interrupts = <8>; - clocks = <&chip_clk CLKID_CFG>; - clock-names = "timer"; - status = "okay"; - }; - - timer1: timer@2c14 { - compatible = "snps,dw-apb-timer"; - reg = <0x2c14 0x14>; - interrupts = <9>; - clocks = <&chip_clk CLKID_CFG>; - clock-names = "timer"; - status = "okay"; - }; - - timer2: timer@2c28 { - compatible = "snps,dw-apb-timer"; - reg = <0x2c28 0x14>; - interrupts = <10>; - clocks = <&chip_clk CLKID_CFG>; - clock-names = "timer"; - status = "disabled"; - }; - - timer3: timer@2c3c { - compatible = "snps,dw-apb-timer"; - reg = <0x2c3c 0x14>; - interrupts = <11>; - clocks = <&chip_clk CLKID_CFG>; - clock-names = "timer"; - status = "disabled"; - }; - - timer4: timer@2c50 { - compatible = "snps,dw-apb-timer"; - reg = <0x2c50 0x14>; - interrupts = <12>; - clocks = <&chip_clk CLKID_CFG>; - clock-names = "timer"; - status = "disabled"; - }; - - timer5: timer@2c64 { - compatible = "snps,dw-apb-timer"; - reg = <0x2c64 0x14>; - interrupts = <13>; - clocks = <&chip_clk CLKID_CFG>; - clock-names = "timer"; - status = "disabled"; - }; - - timer6: timer@2c78 { - compatible = "snps,dw-apb-timer"; - reg = <0x2c78 0x14>; - interrupts = <14>; - clocks = <&chip_clk CLKID_CFG>; - clock-names = "timer"; - status = "disabled"; - }; - - timer7: timer@2c8c { - compatible = "snps,dw-apb-timer"; - reg = <0x2c8c 0x14>; - interrupts = <15>; - clocks = <&chip_clk CLKID_CFG>; - clock-names = "timer"; - status = "disabled"; - }; - - aic: interrupt-controller@3000 { - compatible = "snps,dw-apb-ictl"; - reg = <0x3000 0xc00>; - interrupt-controller; - #interrupt-cells = <1>; - interrupt-parent = <&gic>; - interrupts = ; - }; - }; - - ahci: sata@e90000 { - compatible = "marvell,berlin2-ahci", "generic-ahci"; - reg = <0xe90000 0x1000>; - interrupts = ; - clocks = <&chip_clk CLKID_SATA>; - #address-cells = <1>; - #size-cells = <0>; - - sata0: sata-port@0 { - reg = <0>; - phys = <&sata_phy 0>; - status = "disabled"; - }; - - sata1: sata-port@1 { - reg = <1>; - phys = <&sata_phy 1>; - status = "disabled"; - }; - }; - - sata_phy: phy@e900a0 { - compatible = "marvell,berlin2-sata-phy"; - reg = <0xe900a0 0x200>; - clocks = <&chip_clk CLKID_SATA>; - #address-cells = <1>; - #size-cells = <0>; - #phy-cells = <1>; - status = "disabled"; - - sata-phy@0 { - reg = <0>; - }; - - sata-phy@1 { - reg = <1>; - }; - }; - - chip: chip-control@ea0000 { - compatible = "simple-mfd", "syscon"; - reg = <0xea0000 0x400>; - - chip_clk: clock { - compatible = "marvell,berlin2-clk"; - #clock-cells = <1>; - clocks = <&refclk>; - clock-names = "refclk"; - }; - - soc_pinctrl: pin-controller { - compatible = "marvell,berlin2-soc-pinctrl"; - - emmc_pmux: emmc-pmux { - groups = "G26"; - function = "emmc"; - }; - }; - - chip_rst: reset { - compatible = "marvell,berlin2-reset"; - #reset-cells = <2>; - }; - }; - - pwm: pwm@f20000 { - compatible = "marvell,berlin-pwm"; - reg = <0xf20000 0x40>; - clocks = <&chip_clk CLKID_CFG>; - #pwm-cells = <3>; - }; - - apb@fc0000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - - ranges = <0 0xfc0000 0x10000>; - interrupt-parent = <&sic>; - - wdt0: watchdog@1000 { - compatible = "snps,dw-wdt"; - reg = <0x1000 0x100>; - clocks = <&refclk>; - interrupts = <0>; - }; - - wdt1: watchdog@2000 { - compatible = "snps,dw-wdt"; - reg = <0x2000 0x100>; - clocks = <&refclk>; - interrupts = <1>; - }; - - wdt2: watchdog@3000 { - compatible = "snps,dw-wdt"; - reg = <0x3000 0x100>; - clocks = <&refclk>; - interrupts = <2>; - }; - - sm_gpio1: gpio@5000 { - compatible = "snps,dw-apb-gpio"; - reg = <0x5000 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - portf: gpio-port@5 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <8>; - reg = <0>; - }; - }; - - sm_gpio0: gpio@c000 { - compatible = "snps,dw-apb-gpio"; - reg = <0xc000 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - porte: gpio-port@4 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <8>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <11>; - }; - }; - - uart0: serial@9000 { - compatible = "snps,dw-apb-uart"; - reg = <0x9000 0x100>; - reg-shift = <2>; - reg-io-width = <1>; - interrupts = <8>; - clocks = <&refclk>; - pinctrl-0 = <&uart0_pmux>; - pinctrl-names = "default"; - status = "disabled"; - }; - - uart1: serial@a000 { - compatible = "snps,dw-apb-uart"; - reg = <0xa000 0x100>; - reg-shift = <2>; - reg-io-width = <1>; - interrupts = <9>; - clocks = <&refclk>; - pinctrl-0 = <&uart1_pmux>; - pinctrl-names = "default"; - status = "disabled"; - }; - - uart2: serial@b000 { - compatible = "snps,dw-apb-uart"; - reg = <0xb000 0x100>; - reg-shift = <2>; - reg-io-width = <1>; - interrupts = <10>; - clocks = <&refclk>; - pinctrl-0 = <&uart2_pmux>; - pinctrl-names = "default"; - status = "disabled"; - }; - - sysctrl: system-controller@d000 { - compatible = "simple-mfd", "syscon"; - reg = <0xd000 0x100>; - - sys_pinctrl: pin-controller { - compatible = "marvell,berlin2-system-pinctrl"; - uart0_pmux: uart0-pmux { - groups = "GSM4"; - function = "uart0"; - }; - - uart1_pmux: uart1-pmux { - groups = "GSM5"; - function = "uart1"; - }; - uart2_pmux: uart2-pmux { - groups = "GSM3"; - function = "uart2"; - }; - }; - }; - - sic: interrupt-controller@e000 { - compatible = "snps,dw-apb-ictl"; - reg = <0xe000 0x400>; - interrupt-controller; - #interrupt-cells = <1>; - interrupt-parent = <&gic>; - interrupts = ; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/berlin2cd-google-chromecast.dts b/sys/gnu/dts/arm/berlin2cd-google-chromecast.dts deleted file mode 100644 index 56fa951bc86..00000000000 --- a/sys/gnu/dts/arm/berlin2cd-google-chromecast.dts +++ /dev/null @@ -1,77 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Device Tree file for Google Chromecast - * - * Sebastian Hesselbarth - */ - -/dts-v1/; - -#include "berlin2cd.dtsi" -#include - -/ { - model = "Google Chromecast"; - compatible = "google,chromecast", "marvell,berlin2cd", "marvell,berlin"; - - chosen { - bootargs = "earlyprintk"; - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - - /* - * We're using "linux,usable-memory" instead of "reg" here - * because the (signed and encrypted) bootloader that shipped - * with this device provides an incorrect memory range in - * ATAG_MEM. Linux helpfully overrides the "reg" property with - * data from the ATAG, so we can't specify the proper range - * normally. Fortunately, this alternate property is checked - * first by the OF driver, so we can (ab)use it instead. - */ - linux,usable-memory = <0x00000000 0x20000000>; /* 512 MB */ - }; - - leds { - compatible = "pwm-leds"; - pinctrl-0 = <&ledpwm_pmux>; - pinctrl-names = "default"; - - white { - label = "white"; - pwms = <&pwm 0 600000 0>; - max-brightness = <255>; - linux,default-trigger = "default-on"; - }; - - red { - label = "red"; - pwms = <&pwm 1 600000 0>; - max-brightness = <255>; - }; - }; -}; - -/* - * AzureWave AW-NH387 (Marvell 88W8787) - * 802.11b/g/n + Bluetooth 2.1 - */ -&sdhci0 { - non-removable; - status = "okay"; -}; - -&uart0 { status = "okay"; }; - -&usb_phy1 { status = "okay"; }; - -&usb1 { status = "okay"; }; - -&soc_pinctrl { - ledpwm_pmux: ledpwm-pmux { - groups = "G0"; - function = "pwm"; - }; -}; diff --git a/sys/gnu/dts/arm/berlin2cd-valve-steamlink.dts b/sys/gnu/dts/arm/berlin2cd-valve-steamlink.dts deleted file mode 100644 index 79ac842ae46..00000000000 --- a/sys/gnu/dts/arm/berlin2cd-valve-steamlink.dts +++ /dev/null @@ -1,79 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright 2018 Alexander Monakov - */ -/dts-v1/; - -#include "berlin2cd.dtsi" -#include - -/ { - model = "Valve Steam Link"; - compatible = "valve,steamlink", "marvell,berlin2cd", "marvell,berlin"; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x20000000>; /* 512 MB */ - }; - - gpio-restart { - compatible = "gpio-restart"; - gpios = <&porta 6 GPIO_ACTIVE_HIGH>; - active-delay = <100>; - inactive-delay = <10>; - wait-delay = <100>; - priority = <200>; - }; -}; - -&cpu { - cpu-supply = <&vcpu>; - operating-points = < - /* kHz uV */ - 1000000 1325000 - >; -}; - -&i2c0 { - status = "okay"; - - /* There are two regulators on the board. One is accessible via I2C, - * with buck1 providing SoC power (set up by bootloader to 1.325V or - * less depending on leakage value in OTP), and buck2 likely used for - * DRAM (providing 1.35V). The other regulator on the opposite side - * of the board is probably supplying SDIO and NAND fixed voltages. */ - regulator@19 { - compatible = "marvell,88pg868"; - reg = <0x19>; - - vcpu: buck1 { - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1325000>; - }; - }; -}; - -/* Fixed interface to on-board Marvell 8897 Wi-Fi/Bluetooth/NFC chip. */ -&sdhci0 { - keep-power-in-suspend; - non-removable; - status = "okay"; -}; - -&uart0 { - /* RX/TX are routed to TP50/TP51 on the board. */ - status = "okay"; -}; - -/* The SoC is connected to on-board USB hub that in turn has one downstream - * port wired to the on-board Steam Controller wireless receiver chip. */ -&usb_phy1 { status = "okay"; }; - -&usb1 { - dr_mode = "host"; - status = "okay"; -}; - -ð1 { status = "okay"; }; diff --git a/sys/gnu/dts/arm/berlin2cd.dtsi b/sys/gnu/dts/arm/berlin2cd.dtsi deleted file mode 100644 index e5c1f4213ff..00000000000 --- a/sys/gnu/dts/arm/berlin2cd.dtsi +++ /dev/null @@ -1,583 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Device Tree Include file for Marvell Armada 1500-mini (Berlin BG2CD) SoC - * - * Sebastian Hesselbarth - * - * based on GPL'ed 2.6 kernel sources - * (c) Marvell International Ltd. - */ - -#include -#include - -/ { - model = "Marvell Armada 1500-mini (BG2CD) SoC"; - compatible = "marvell,berlin2cd", "marvell,berlin"; - #address-cells = <1>; - #size-cells = <1>; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu: cpu@0 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - next-level-cache = <&l2>; - reg = <0>; - - clocks = <&chip_clk CLKID_CPU>; - clock-latency = <100000>; - operating-points = < - /* kHz uV */ - 800000 1200000 - 600000 1200000 - >; - }; - }; - - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupt-parent = <&gic>; - interrupts = ; - }; - - refclk: oscillator { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - - soc@f7000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&gic>; - - ranges = <0 0xf7000000 0x1000000>; - - sdhci0: sdhci@ab0000 { - compatible = "mrvl,pxav3-mmc"; - reg = <0xab0000 0x200>; - clocks = <&chip_clk CLKID_SDIO0XIN>, <&chip_clk CLKID_SDIO0>; - clock-names = "io", "core"; - interrupts = ; - status = "disabled"; - }; - - l2: l2-cache-controller@ac0000 { - compatible = "arm,pl310-cache"; - reg = <0xac0000 0x1000>; - cache-unified; - cache-level = <2>; - }; - - snoop-control-unit@ad0000 { - compatible = "arm,cortex-a9-scu"; - reg = <0xad0000 0x100>; - }; - - gic: interrupt-controller@ad1000 { - compatible = "arm,cortex-a9-gic"; - reg = <0xad1000 0x1000>, <0xad0100 0x0100>; - interrupt-controller; - #interrupt-cells = <3>; - }; - - global-timer@ad0200 { - compatible = "arm,cortex-a9-global-timer"; - reg = <0xad0200 0x20>; - interrupts = ; - clocks = <&chip_clk CLKID_TWD>; - }; - - local-timer@ad0600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0xad0600 0x20>; - interrupts = ; - clocks = <&chip_clk CLKID_TWD>; - }; - - local-wdt@ad0620 { - compatible = "arm,cortex-a9-twd-wdt"; - reg = <0xad0620 0x20>; - interrupts = ; - clocks = <&chip_clk CLKID_TWD>; - }; - - usb_phy0: usb-phy@b74000 { - compatible = "marvell,berlin2cd-usb-phy"; - reg = <0xb74000 0x128>; - #phy-cells = <0>; - resets = <&chip_rst 0x178 23>; - status = "disabled"; - }; - - usb_phy1: usb-phy@b78000 { - compatible = "marvell,berlin2cd-usb-phy"; - reg = <0xb78000 0x128>; - #phy-cells = <0>; - resets = <&chip_rst 0x178 24>; - status = "disabled"; - }; - - eth1: ethernet@b90000 { - compatible = "marvell,pxa168-eth"; - reg = <0xb90000 0x10000>; - clocks = <&chip_clk CLKID_GETH1>; - interrupts = ; - /* set by bootloader */ - local-mac-address = [00 00 00 00 00 00]; - #address-cells = <1>; - #size-cells = <0>; - phy-connection-type = "mii"; - phy-handle = <ðphy1>; - status = "disabled"; - - ethphy1: ethernet-phy@0 { - reg = <0>; - }; - }; - - eth0: ethernet@e50000 { - compatible = "marvell,pxa168-eth"; - reg = <0xe50000 0x10000>; - clocks = <&chip_clk CLKID_GETH0>; - interrupts = ; - /* set by bootloader */ - local-mac-address = [00 00 00 00 00 00]; - #address-cells = <1>; - #size-cells = <0>; - phy-connection-type = "mii"; - phy-handle = <ðphy0>; - status = "disabled"; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; - }; - - apb@e80000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - - ranges = <0 0xe80000 0x10000>; - interrupt-parent = <&aic>; - - gpio0: gpio@400 { - compatible = "snps,dw-apb-gpio"; - reg = <0x0400 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - porta: gpio-port@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <8>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <0>; - }; - }; - - gpio1: gpio@800 { - compatible = "snps,dw-apb-gpio"; - reg = <0x0800 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - portb: gpio-port@1 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <8>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <1>; - }; - }; - - gpio2: gpio@c00 { - compatible = "snps,dw-apb-gpio"; - reg = <0x0c00 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - portc: gpio-port@2 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <8>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <2>; - }; - }; - - gpio3: gpio@1000 { - compatible = "snps,dw-apb-gpio"; - reg = <0x1000 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - portd: gpio-port@3 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <8>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <3>; - }; - }; - - i2c0: i2c@1400 { - compatible = "snps,designware-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x1400 0x100>; - interrupts = <16>; - clocks = <&chip_clk CLKID_CFG>; - status = "disabled"; - }; - - i2c1: i2c@1800 { - compatible = "snps,designware-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x1800 0x100>; - interrupts = <17>; - clocks = <&chip_clk CLKID_CFG>; - status = "disabled"; - }; - - spi0: spi@1c00 { - compatible = "snps,dw-apb-ssi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x1c00 0x100>; - interrupts = <4>; - clocks = <&chip_clk CLKID_CFG>; - status = "disabled"; - }; - - wdt4: watchdog@2000 { - compatible = "snps,dw-wdt"; - reg = <0x2000 0x100>; - clocks = <&chip_clk CLKID_CFG>; - interrupts = <5>; - status = "disabled"; - }; - - wdt5: watchdog@2400 { - compatible = "snps,dw-wdt"; - reg = <0x2400 0x100>; - clocks = <&chip_clk CLKID_CFG>; - interrupts = <6>; - status = "disabled"; - }; - - wdt6: watchdog@2800 { - compatible = "snps,dw-wdt"; - reg = <0x2800 0x100>; - clocks = <&chip_clk CLKID_CFG>; - interrupts = <7>; - status = "disabled"; - }; - - timer0: timer@2c00 { - compatible = "snps,dw-apb-timer"; - reg = <0x2c00 0x14>; - interrupts = <8>; - clocks = <&chip_clk CLKID_CFG>; - clock-names = "timer"; - status = "okay"; - }; - - timer1: timer@2c14 { - compatible = "snps,dw-apb-timer"; - reg = <0x2c14 0x14>; - interrupts = <9>; - clocks = <&chip_clk CLKID_CFG>; - clock-names = "timer"; - status = "okay"; - }; - - timer2: timer@2c28 { - compatible = "snps,dw-apb-timer"; - reg = <0x2c28 0x14>; - interrupts = <10>; - clocks = <&chip_clk CLKID_CFG>; - clock-names = "timer"; - status = "disabled"; - }; - - timer3: timer@2c3c { - compatible = "snps,dw-apb-timer"; - reg = <0x2c3c 0x14>; - interrupts = <11>; - clocks = <&chip_clk CLKID_CFG>; - clock-names = "timer"; - status = "disabled"; - }; - - timer4: timer@2c50 { - compatible = "snps,dw-apb-timer"; - reg = <0x2c50 0x14>; - interrupts = <12>; - clocks = <&chip_clk CLKID_CFG>; - clock-names = "timer"; - status = "disabled"; - }; - - timer5: timer@2c64 { - compatible = "snps,dw-apb-timer"; - reg = <0x2c64 0x14>; - interrupts = <13>; - clocks = <&chip_clk CLKID_CFG>; - clock-names = "timer"; - status = "disabled"; - }; - - timer6: timer@2c78 { - compatible = "snps,dw-apb-timer"; - reg = <0x2c78 0x14>; - interrupts = <14>; - clocks = <&chip_clk CLKID_CFG>; - clock-names = "timer"; - status = "disabled"; - }; - - timer7: timer@2c8c { - compatible = "snps,dw-apb-timer"; - reg = <0x2c8c 0x14>; - interrupts = <15>; - clocks = <&chip_clk CLKID_CFG>; - clock-names = "timer"; - status = "disabled"; - }; - - aic: interrupt-controller@3000 { - compatible = "snps,dw-apb-ictl"; - reg = <0x3000 0xc00>; - interrupt-controller; - #interrupt-cells = <1>; - interrupt-parent = <&gic>; - interrupts = ; - }; - }; - - chip: chip-control@ea0000 { - compatible = "simple-mfd", "syscon"; - reg = <0xea0000 0x400>; - - chip_clk: clock { - compatible = "marvell,berlin2-clk"; - #clock-cells = <1>; - clocks = <&refclk>; - clock-names = "refclk"; - }; - - soc_pinctrl: pin-controller { - compatible = "marvell,berlin2cd-soc-pinctrl"; - - uart0_pmux: uart0-pmux { - groups = "G6"; - function = "uart0"; - }; - }; - - chip_rst: reset { - compatible = "marvell,berlin2-reset"; - #reset-cells = <2>; - }; - }; - - usb0: usb@ed0000 { - compatible = "chipidea,usb2"; - reg = <0xed0000 0x200>; - interrupts = ; - clocks = <&chip_clk CLKID_USB0>; - phys = <&usb_phy0>; - phy-names = "usb-phy"; - status = "disabled"; - }; - - usb1: usb@ee0000 { - compatible = "chipidea,usb2"; - reg = <0xee0000 0x200>; - interrupts = ; - clocks = <&chip_clk CLKID_USB1>; - phys = <&usb_phy1>; - phy-names = "usb-phy"; - status = "disabled"; - }; - - pwm: pwm@f20000 { - compatible = "marvell,berlin-pwm"; - reg = <0xf20000 0x40>; - clocks = <&chip_clk CLKID_CFG>; - #pwm-cells = <3>; - }; - - apb@fc0000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - - ranges = <0 0xfc0000 0x10000>; - interrupt-parent = <&sic>; - - wdt0: watchdog@1000 { - compatible = "snps,dw-wdt"; - reg = <0x1000 0x100>; - clocks = <&refclk>; - interrupts = <0>; - }; - - wdt1: watchdog@2000 { - compatible = "snps,dw-wdt"; - reg = <0x2000 0x100>; - clocks = <&refclk>; - interrupts = <1>; - status = "disabled"; - }; - - wdt2: watchdog@3000 { - compatible = "snps,dw-wdt"; - reg = <0x3000 0x100>; - clocks = <&refclk>; - interrupts = <2>; - status = "disabled"; - }; - - sm_gpio1: gpio@5000 { - compatible = "snps,dw-apb-gpio"; - reg = <0x5000 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - portf: gpio-port@5 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <8>; - reg = <0>; - }; - }; - - spi1: spi@6000 { - compatible = "snps,dw-apb-ssi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x6000 0x100>; - clocks = <&refclk>; - interrupts = <5>; - status = "disabled"; - }; - - i2c2: i2c@7000 { - compatible = "snps,designware-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x7000 0x100>; - interrupts = <6>; - clocks = <&refclk>; - status = "disabled"; - }; - - i2c3: i2c@8000 { - compatible = "snps,designware-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x8000 0x100>; - interrupts = <7>; - clocks = <&refclk>; - status = "disabled"; - }; - - sm_gpio0: gpio@c000 { - compatible = "snps,dw-apb-gpio"; - reg = <0xc000 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - porte: gpio-port@4 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <8>; - reg = <0>; - }; - }; - - uart0: serial@9000 { - compatible = "snps,dw-apb-uart"; - reg = <0x9000 0x100>; - reg-shift = <2>; - reg-io-width = <1>; - interrupts = <8>; - clocks = <&refclk>; - pinctrl-0 = <&uart0_pmux>; - pinctrl-names = "default"; - status = "disabled"; - }; - - uart1: serial@a000 { - compatible = "snps,dw-apb-uart"; - reg = <0xa000 0x100>; - reg-shift = <2>; - reg-io-width = <1>; - interrupts = <9>; - clocks = <&refclk>; - status = "disabled"; - }; - - uart2: serial@b000 { - compatible = "snps,dw-apb-uart"; - reg = <0xb000 0x100>; - reg-shift = <2>; - reg-io-width = <1>; - interrupts = <10>; - clocks = <&refclk>; - status = "disabled"; - }; - - sysctrl: system-controller@d000 { - compatible = "simple-mfd", "syscon"; - reg = <0xd000 0x100>; - - sys_pinctrl: pin-controller { - compatible = "marvell,berlin2cd-system-pinctrl"; - }; - - adc: adc { - compatible = "marvell,berlin2-adc"; - interrupts = <12>, <14>; - interrupt-names = "adc", "tsen"; - }; - }; - - sic: interrupt-controller@e000 { - compatible = "snps,dw-apb-ictl"; - reg = <0xe000 0x400>; - interrupt-controller; - #interrupt-cells = <1>; - interrupt-parent = <&gic>; - interrupts = ; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/berlin2q-marvell-dmp.dts b/sys/gnu/dts/arm/berlin2q-marvell-dmp.dts deleted file mode 100644 index c162f98cb8e..00000000000 --- a/sys/gnu/dts/arm/berlin2q-marvell-dmp.dts +++ /dev/null @@ -1,144 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2014 Antoine Ténart - */ - -/dts-v1/; - -#include -#include "berlin2q.dtsi" - -/ { - model = "Marvell BG2-Q DMP"; - compatible = "marvell,berlin2q-dmp", "marvell,berlin2q", "marvell,berlin"; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x80000000>; - }; - - chosen { - bootargs = "earlyprintk"; - stdout-path = "serial0:115200n8"; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_usb0_vbus: regulator_usb0 { - compatible = "regulator-fixed"; - regulator-name = "usb0_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&portb 8 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usb1_vbus: regulator_usb1 { - compatible = "regulator-fixed"; - regulator-name = "usb1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&portb 10 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usb2_vbus: regulator_usb2 { - compatible = "regulator-fixed"; - regulator-name = "usb2_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&portb 12 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_sdio1_vmmc: regulator_sdio1_vmmc { - compatible = "regulator-fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "sdio1_vmmc"; - enable-active-high; - regulator-boot-on; - gpio = <&portb 21 GPIO_ACTIVE_HIGH>; - }; - - reg_sdio1_vqmmc: regulator_sido1_vqmmc { - compatible = "regulator-gpio"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-name = "sdio1_vqmmc"; - regulator-type = "voltage"; - enable-active-high; - gpios = <&portb 16 GPIO_ACTIVE_HIGH>; - states = <3300000 0x1 - 1800000 0x0>; - }; - }; -}; - -&soc_pinctrl { - sd1gpio_pmux: sd1pwr-pmux { - groups = "G23", "G32"; - function = "gpio"; - }; -}; - -&sdhci1 { - vmmc-supply = <®_sdio1_vmmc>; - vqmmc-supply = <®_sdio1_vqmmc>; - cd-gpios = <&portc 30 GPIO_ACTIVE_LOW>; - wp-gpios = <&portd 0 GPIO_ACTIVE_HIGH>; - pinctrl-0 = <&sd1gpio_pmux>, <&sd1_pmux>; - pinctrl-names = "default"; - status = "okay"; -}; - -&sdhci2 { - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&i2c0 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&usb_phy0 { - status = "okay"; -}; - -&usb_phy2 { - status = "okay"; -}; - -&usb0 { - vbus-supply = <®_usb0_vbus>; - status = "okay"; -}; - -&usb2 { - vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; - -ð0 { - status = "okay"; -}; - -&sata0 { - status = "okay"; -}; - -&sata_phy { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/berlin2q.dtsi b/sys/gnu/dts/arm/berlin2q.dtsi deleted file mode 100644 index 99d6872a6df..00000000000 --- a/sys/gnu/dts/arm/berlin2q.dtsi +++ /dev/null @@ -1,666 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2014 Antoine Ténart - */ - -#include -#include - -/ { - model = "Marvell Armada 1500 pro (BG2-Q) SoC"; - compatible = "marvell,berlin2q", "marvell,berlin"; - #address-cells = <1>; - #size-cells = <1>; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "marvell,berlin-smp"; - - cpu0: cpu@0 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - next-level-cache = <&l2>; - reg = <0>; - - clocks = <&chip_clk CLKID_CPU>; - clock-latency = <100000>; - /* Can be modified by the bootloader */ - operating-points = < - /* kHz uV */ - 1200000 1200000 - 1000000 1200000 - 800000 1200000 - 600000 1200000 - >; - }; - - cpu1: cpu@1 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - next-level-cache = <&l2>; - reg = <1>; - - clocks = <&chip_clk CLKID_CPU>; - clock-latency = <100000>; - /* Can be modified by the bootloader */ - operating-points = < - /* kHz uV */ - 1200000 1200000 - 1000000 1200000 - 800000 1200000 - 600000 1200000 - >; - }; - - cpu2: cpu@2 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - next-level-cache = <&l2>; - reg = <2>; - - clocks = <&chip_clk CLKID_CPU>; - clock-latency = <100000>; - /* Can be modified by the bootloader */ - operating-points = < - /* kHz uV */ - 1200000 1200000 - 1000000 1200000 - 800000 1200000 - 600000 1200000 - >; - }; - - cpu3: cpu@3 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - next-level-cache = <&l2>; - reg = <3>; - - clocks = <&chip_clk CLKID_CPU>; - clock-latency = <100000>; - /* Can be modified by the bootloader */ - operating-points = < - /* kHz uV */ - 1200000 1200000 - 1000000 1200000 - 800000 1200000 - 600000 1200000 - >; - }; - }; - - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupt-parent = <&gic>; - interrupts = , - , - , - ; - interrupt-affinity = <&cpu0>, - <&cpu1>, - <&cpu2>, - <&cpu3>; - }; - - refclk: oscillator { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - - soc@f7000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - - ranges = <0 0xf7000000 0x1000000>; - interrupt-parent = <&gic>; - - sdhci0: sdhci@ab0000 { - compatible = "mrvl,pxav3-mmc"; - reg = <0xab0000 0x200>; - clocks = <&chip_clk CLKID_SDIO1XIN>, <&chip_clk CLKID_SDIO>; - clock-names = "io", "core"; - interrupts = ; - status = "disabled"; - }; - - sdhci1: sdhci@ab0800 { - compatible = "mrvl,pxav3-mmc"; - reg = <0xab0800 0x200>; - clocks = <&chip_clk CLKID_SDIO1XIN>, <&chip_clk CLKID_SDIO>; - clock-names = "io", "core"; - interrupts = ; - status = "disabled"; - }; - - sdhci2: sdhci@ab1000 { - compatible = "mrvl,pxav3-mmc"; - reg = <0xab1000 0x200>; - interrupts = ; - clocks = <&chip_clk CLKID_NFC_ECC>, <&chip_clk CLKID_SDIO>; - clock-names = "io", "core"; - status = "disabled"; - }; - - l2: l2-cache-controller@ac0000 { - compatible = "arm,pl310-cache"; - reg = <0xac0000 0x1000>; - cache-unified; - cache-level = <2>; - arm,data-latency = <2 2 2>; - arm,tag-latency = <2 2 2>; - }; - - scu: snoop-control-unit@ad0000 { - compatible = "arm,cortex-a9-scu"; - reg = <0xad0000 0x58>; - }; - - local-timer@ad0600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0xad0600 0x20>; - clocks = <&chip_clk CLKID_TWD>; - interrupts = ; - }; - - gic: interrupt-controller@ad1000 { - compatible = "arm,cortex-a9-gic"; - reg = <0xad1000 0x1000>, <0xad0100 0x100>; - interrupt-controller; - #interrupt-cells = <3>; - }; - - usb_phy2: phy@a2f400 { - compatible = "marvell,berlin2cd-usb-phy"; - reg = <0xa2f400 0x128>; - #phy-cells = <0>; - resets = <&chip_rst 0x104 14>; - status = "disabled"; - }; - - usb2: usb@a30000 { - compatible = "chipidea,usb2"; - reg = <0xa30000 0x10000>; - interrupts = ; - clocks = <&chip_clk CLKID_USB2>; - phys = <&usb_phy2>; - phy-names = "usb-phy"; - status = "disabled"; - }; - - usb_phy0: phy@b74000 { - compatible = "marvell,berlin2cd-usb-phy"; - reg = <0xb74000 0x128>; - #phy-cells = <0>; - resets = <&chip_rst 0x104 12>; - status = "disabled"; - }; - - usb_phy1: phy@b78000 { - compatible = "marvell,berlin2cd-usb-phy"; - reg = <0xb78000 0x128>; - #phy-cells = <0>; - resets = <&chip_rst 0x104 13>; - status = "disabled"; - }; - - eth0: ethernet@b90000 { - compatible = "marvell,pxa168-eth"; - reg = <0xb90000 0x10000>; - clocks = <&chip_clk CLKID_GETH0>; - interrupts = ; - /* set by bootloader */ - local-mac-address = [00 00 00 00 00 00]; - #address-cells = <1>; - #size-cells = <0>; - phy-connection-type = "mii"; - phy-handle = <ðphy0>; - status = "disabled"; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; - }; - - cpu-ctrl@dd0000 { - compatible = "marvell,berlin-cpu-ctrl"; - reg = <0xdd0000 0x10000>; - }; - - apb@e80000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - - ranges = <0 0xe80000 0x10000>; - interrupt-parent = <&aic>; - - gpio0: gpio@400 { - compatible = "snps,dw-apb-gpio"; - reg = <0x0400 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - porta: gpio-port@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <32>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <0>; - }; - }; - - gpio1: gpio@800 { - compatible = "snps,dw-apb-gpio"; - reg = <0x0800 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - portb: gpio-port@1 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <32>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <1>; - }; - }; - - gpio2: gpio@c00 { - compatible = "snps,dw-apb-gpio"; - reg = <0x0c00 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - portc: gpio-port@2 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <32>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <2>; - }; - }; - - gpio3: gpio@1000 { - compatible = "snps,dw-apb-gpio"; - reg = <0x1000 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - portd: gpio-port@3 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <32>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <3>; - }; - }; - - i2c0: i2c@1400 { - compatible = "snps,designware-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x1400 0x100>; - interrupts = <4>; - clocks = <&chip_clk CLKID_CFG>; - pinctrl-0 = <&twsi0_pmux>; - pinctrl-names = "default"; - status = "disabled"; - }; - - i2c1: i2c@1800 { - compatible = "snps,designware-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x1800 0x100>; - interrupts = <5>; - clocks = <&chip_clk CLKID_CFG>; - pinctrl-0 = <&twsi1_pmux>; - pinctrl-names = "default"; - status = "disabled"; - }; - - timer0: timer@2c00 { - compatible = "snps,dw-apb-timer"; - reg = <0x2c00 0x14>; - clocks = <&chip_clk CLKID_CFG>; - clock-names = "timer"; - interrupts = <8>; - }; - - timer1: timer@2c14 { - compatible = "snps,dw-apb-timer"; - reg = <0x2c14 0x14>; - clocks = <&chip_clk CLKID_CFG>; - clock-names = "timer"; - }; - - timer2: timer@2c28 { - compatible = "snps,dw-apb-timer"; - reg = <0x2c28 0x14>; - clocks = <&chip_clk CLKID_CFG>; - clock-names = "timer"; - status = "disabled"; - }; - - timer3: timer@2c3c { - compatible = "snps,dw-apb-timer"; - reg = <0x2c3c 0x14>; - clocks = <&chip_clk CLKID_CFG>; - clock-names = "timer"; - status = "disabled"; - }; - - timer4: timer@2c50 { - compatible = "snps,dw-apb-timer"; - reg = <0x2c50 0x14>; - clocks = <&chip_clk CLKID_CFG>; - clock-names = "timer"; - status = "disabled"; - }; - - timer5: timer@2c64 { - compatible = "snps,dw-apb-timer"; - reg = <0x2c64 0x14>; - clocks = <&chip_clk CLKID_CFG>; - clock-names = "timer"; - status = "disabled"; - }; - - timer6: timer@2c78 { - compatible = "snps,dw-apb-timer"; - reg = <0x2c78 0x14>; - clocks = <&chip_clk CLKID_CFG>; - clock-names = "timer"; - status = "disabled"; - }; - - timer7: timer@2c8c { - compatible = "snps,dw-apb-timer"; - reg = <0x2c8c 0x14>; - clocks = <&chip_clk CLKID_CFG>; - clock-names = "timer"; - status = "disabled"; - }; - - aic: interrupt-controller@3800 { - compatible = "snps,dw-apb-ictl"; - reg = <0x3800 0x30>; - interrupt-controller; - #interrupt-cells = <1>; - interrupt-parent = <&gic>; - interrupts = ; - }; - }; - - chip: chip-control@ea0000 { - compatible = "simple-mfd", "syscon"; - reg = <0xea0000 0x400>, <0xdd0170 0x10>; - - chip_clk: clock { - compatible = "marvell,berlin2q-clk"; - #clock-cells = <1>; - clocks = <&refclk>; - clock-names = "refclk"; - }; - - soc_pinctrl: pin-controller { - compatible = "marvell,berlin2q-soc-pinctrl"; - - sd1_pmux: sd1-pmux { - groups = "G31"; - function = "sd1"; - }; - - twsi0_pmux: twsi0-pmux { - groups = "G6"; - function = "twsi0"; - }; - - twsi1_pmux: twsi1-pmux { - groups = "G7"; - function = "twsi1"; - }; - }; - - chip_rst: reset { - compatible = "marvell,berlin2-reset"; - #reset-cells = <2>; - }; - }; - - ahci: sata@e90000 { - compatible = "marvell,berlin2q-ahci", "generic-ahci"; - reg = <0xe90000 0x1000>; - interrupts = ; - clocks = <&chip_clk CLKID_SATA>; - #address-cells = <1>; - #size-cells = <0>; - - sata0: sata-port@0 { - reg = <0>; - phys = <&sata_phy 0>; - status = "disabled"; - }; - - sata1: sata-port@1 { - reg = <1>; - phys = <&sata_phy 1>; - status = "disabled"; - }; - }; - - sata_phy: phy@e900a0 { - compatible = "marvell,berlin2q-sata-phy"; - reg = <0xe900a0 0x200>; - clocks = <&chip_clk CLKID_SATA>; - #address-cells = <1>; - #size-cells = <0>; - #phy-cells = <1>; - status = "disabled"; - - sata-phy@0 { - reg = <0>; - }; - - sata-phy@1 { - reg = <1>; - }; - }; - - usb0: usb@ed0000 { - compatible = "chipidea,usb2"; - reg = <0xed0000 0x10000>; - interrupts = ; - clocks = <&chip_clk CLKID_USB0>; - phys = <&usb_phy0>; - phy-names = "usb-phy"; - status = "disabled"; - }; - - usb1: usb@ee0000 { - compatible = "chipidea,usb2"; - reg = <0xee0000 0x10000>; - interrupts = ; - clocks = <&chip_clk CLKID_USB1>; - phys = <&usb_phy1>; - phy-names = "usb-phy"; - status = "disabled"; - }; - - pwm: pwm@f20000 { - compatible = "marvell,berlin-pwm"; - reg = <0xf20000 0x40>; - clocks = <&chip_clk CLKID_CFG>; - #pwm-cells = <3>; - }; - - apb@fc0000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - - ranges = <0 0xfc0000 0x10000>; - interrupt-parent = <&sic>; - - wdt0: watchdog@1000 { - compatible = "snps,dw-wdt"; - reg = <0x1000 0x100>; - clocks = <&refclk>; - interrupts = <0>; - }; - - wdt1: watchdog@2000 { - compatible = "snps,dw-wdt"; - reg = <0x2000 0x100>; - clocks = <&refclk>; - interrupts = <1>; - }; - - wdt2: watchdog@3000 { - compatible = "snps,dw-wdt"; - reg = <0x3000 0x100>; - clocks = <&refclk>; - interrupts = <2>; - }; - - sm_gpio1: gpio@5000 { - compatible = "snps,dw-apb-gpio"; - reg = <0x5000 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - portf: gpio-port@5 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <32>; - reg = <0>; - }; - }; - - i2c2: i2c@7000 { - compatible = "snps,designware-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x7000 0x100>; - interrupts = <6>; - clocks = <&refclk>; - pinctrl-0 = <&twsi2_pmux>; - pinctrl-names = "default"; - status = "disabled"; - }; - - i2c3: i2c@8000 { - compatible = "snps,designware-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x8000 0x100>; - interrupts = <7>; - clocks = <&refclk>; - pinctrl-0 = <&twsi3_pmux>; - pinctrl-names = "default"; - status = "disabled"; - }; - - uart0: uart@9000 { - compatible = "snps,dw-apb-uart"; - reg = <0x9000 0x100>; - interrupts = <8>; - clocks = <&refclk>; - reg-shift = <2>; - pinctrl-0 = <&uart0_pmux>; - pinctrl-names = "default"; - status = "disabled"; - }; - - uart1: uart@a000 { - compatible = "snps,dw-apb-uart"; - reg = <0xa000 0x100>; - interrupts = <9>; - clocks = <&refclk>; - reg-shift = <2>; - pinctrl-0 = <&uart1_pmux>; - pinctrl-names = "default"; - status = "disabled"; - }; - - sm_gpio0: gpio@c000 { - compatible = "snps,dw-apb-gpio"; - reg = <0xc000 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - porte: gpio-port@4 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <32>; - reg = <0>; - }; - }; - - sysctrl: pin-controller@d000 { - compatible = "simple-mfd", "syscon"; - reg = <0xd000 0x100>; - - sys_pinctrl: pin-controller { - compatible = "marvell,berlin2q-system-pinctrl"; - - uart0_pmux: uart0-pmux { - groups = "GSM12"; - function = "uart0"; - }; - - uart1_pmux: uart1-pmux { - groups = "GSM14"; - function = "uart1"; - }; - - twsi2_pmux: twsi2-pmux { - groups = "GSM13"; - function = "twsi2"; - }; - - twsi3_pmux: twsi3-pmux { - groups = "GSM14"; - function = "twsi3"; - }; - }; - - adc: adc { - compatible = "marvell,berlin2-adc"; - interrupts = <12>, <14>; - interrupt-names = "adc", "tsen"; - }; - }; - - sic: interrupt-controller@e000 { - compatible = "snps,dw-apb-ictl"; - reg = <0xe000 0x30>; - interrupt-controller; - #interrupt-cells = <1>; - interrupt-parent = <&gic>; - interrupts = ; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/compulab-sb-som.dtsi b/sys/gnu/dts/arm/compulab-sb-som.dtsi deleted file mode 100644 index f5e6216718d..00000000000 --- a/sys/gnu/dts/arm/compulab-sb-som.dtsi +++ /dev/null @@ -1,46 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2015 CompuLab, Ltd. - http://www.compulab.co.il/ - */ - -/ { - model = "CompuLab SB-SOM"; - compatible = "compulab,sb-som"; - - vsb_3v3: fixedregulator-v3_3 { - compatible = "regulator-fixed"; - regulator-name = "vsb_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - enable-active-high; - }; - - lcd0: display { - compatible = "startek,startek-kd050c", "panel-dpi"; - label = "lcd"; - - panel-timing { - clock-frequency = <33000000>; - hactive = <800>; - vactive = <480>; - hfront-porch = <40>; - hback-porch = <40>; - hsync-len = <43>; - vback-porch = <29>; - vfront-porch = <13>; - vsync-len = <3>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - - hdmi_conn: connector { - compatible = "hdmi-connector"; - label = "hdmi"; - - type = "a"; - }; -}; diff --git a/sys/gnu/dts/arm/cros-adc-thermistors.dtsi b/sys/gnu/dts/arm/cros-adc-thermistors.dtsi deleted file mode 100644 index 97e616f7b84..00000000000 --- a/sys/gnu/dts/arm/cros-adc-thermistors.dtsi +++ /dev/null @@ -1,41 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Thermistor dts fragment for devices that use Thermistors as - * children of the IIO based ADC. - * - * Currently, used by Exynos5420 based Peach PIT and - * Exynos5800 based Peach PI. - * - * Copyright (c) 2014 Samsung Electronics Co., Ltd. -*/ - -&adc { - thermistor3 { - compatible = "murata,ncp15wb473"; - pullup-uv = <1800000>; - pullup-ohm = <47000>; - pulldown-ohm = <0>; - io-channels = <&adc 3>; - }; - thermistor4 { - compatible = "murata,ncp15wb473"; - pullup-uv = <1800000>; - pullup-ohm = <47000>; - pulldown-ohm = <0>; - io-channels = <&adc 4>; - }; - thermistor5 { - compatible = "murata,ncp15wb473"; - pullup-uv = <1800000>; - pullup-ohm = <47000>; - pulldown-ohm = <0>; - io-channels = <&adc 5>; - }; - thermistor6 { - compatible = "murata,ncp15wb473"; - pullup-uv = <1800000>; - pullup-ohm = <47000>; - pulldown-ohm = <0>; - io-channels = <&adc 6>; - }; -}; diff --git a/sys/gnu/dts/arm/cros-ec-keyboard.dtsi b/sys/gnu/dts/arm/cros-ec-keyboard.dtsi deleted file mode 100644 index 4a0c1037fbc..00000000000 --- a/sys/gnu/dts/arm/cros-ec-keyboard.dtsi +++ /dev/null @@ -1,107 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Keyboard dts fragment for devices that use cros-ec-keyboard - * - * Copyright (c) 2014 Google, Inc -*/ - -#include - -&cros_ec { - keyboard-controller { - compatible = "google,cros-ec-keyb"; - keypad,num-rows = <8>; - keypad,num-columns = <13>; - google,needs-ghost-filter; - - linux,keymap = < - MATRIX_KEY(0x00, 0x01, KEY_LEFTMETA) - MATRIX_KEY(0x00, 0x02, KEY_F1) - MATRIX_KEY(0x00, 0x03, KEY_B) - MATRIX_KEY(0x00, 0x04, KEY_F10) - MATRIX_KEY(0x00, 0x05, KEY_RO) - MATRIX_KEY(0x00, 0x06, KEY_N) - MATRIX_KEY(0x00, 0x08, KEY_EQUAL) - MATRIX_KEY(0x00, 0x0a, KEY_RIGHTALT) - - MATRIX_KEY(0x01, 0x01, KEY_ESC) - MATRIX_KEY(0x01, 0x02, KEY_F4) - MATRIX_KEY(0x01, 0x03, KEY_G) - MATRIX_KEY(0x01, 0x04, KEY_F7) - MATRIX_KEY(0x01, 0x06, KEY_H) - MATRIX_KEY(0x01, 0x08, KEY_APOSTROPHE) - MATRIX_KEY(0x01, 0x09, KEY_F9) - MATRIX_KEY(0x01, 0x0b, KEY_BACKSPACE) - MATRIX_KEY(0x01, 0x0c, KEY_HENKAN) - - MATRIX_KEY(0x02, 0x00, KEY_LEFTCTRL) - MATRIX_KEY(0x02, 0x01, KEY_TAB) - MATRIX_KEY(0x02, 0x02, KEY_F3) - MATRIX_KEY(0x02, 0x03, KEY_T) - MATRIX_KEY(0x02, 0x04, KEY_F6) - MATRIX_KEY(0x02, 0x05, KEY_RIGHTBRACE) - MATRIX_KEY(0x02, 0x06, KEY_Y) - MATRIX_KEY(0x02, 0x07, KEY_102ND) - MATRIX_KEY(0x02, 0x08, KEY_LEFTBRACE) - MATRIX_KEY(0x02, 0x09, KEY_F8) - MATRIX_KEY(0x02, 0x0a, KEY_YEN) - - MATRIX_KEY(0x03, 0x01, KEY_GRAVE) - MATRIX_KEY(0x03, 0x02, KEY_F2) - MATRIX_KEY(0x03, 0x03, KEY_5) - MATRIX_KEY(0x03, 0x04, KEY_F5) - MATRIX_KEY(0x03, 0x06, KEY_6) - MATRIX_KEY(0x03, 0x08, KEY_MINUS) - MATRIX_KEY(0x03, 0x09, KEY_F13) - MATRIX_KEY(0x03, 0x0b, KEY_BACKSLASH) - MATRIX_KEY(0x03, 0x0c, KEY_MUHENKAN) - - MATRIX_KEY(0x04, 0x00, KEY_RIGHTCTRL) - MATRIX_KEY(0x04, 0x01, KEY_A) - MATRIX_KEY(0x04, 0x02, KEY_D) - MATRIX_KEY(0x04, 0x03, KEY_F) - MATRIX_KEY(0x04, 0x04, KEY_S) - MATRIX_KEY(0x04, 0x05, KEY_K) - MATRIX_KEY(0x04, 0x06, KEY_J) - MATRIX_KEY(0x04, 0x08, KEY_SEMICOLON) - MATRIX_KEY(0x04, 0x09, KEY_L) - MATRIX_KEY(0x04, 0x0a, KEY_BACKSLASH) - MATRIX_KEY(0x04, 0x0b, KEY_ENTER) - - MATRIX_KEY(0x05, 0x01, KEY_Z) - MATRIX_KEY(0x05, 0x02, KEY_C) - MATRIX_KEY(0x05, 0x03, KEY_V) - MATRIX_KEY(0x05, 0x04, KEY_X) - MATRIX_KEY(0x05, 0x05, KEY_COMMA) - MATRIX_KEY(0x05, 0x06, KEY_M) - MATRIX_KEY(0x05, 0x07, KEY_LEFTSHIFT) - MATRIX_KEY(0x05, 0x08, KEY_SLASH) - MATRIX_KEY(0x05, 0x09, KEY_DOT) - MATRIX_KEY(0x05, 0x0b, KEY_SPACE) - - MATRIX_KEY(0x06, 0x01, KEY_1) - MATRIX_KEY(0x06, 0x02, KEY_3) - MATRIX_KEY(0x06, 0x03, KEY_4) - MATRIX_KEY(0x06, 0x04, KEY_2) - MATRIX_KEY(0x06, 0x05, KEY_8) - MATRIX_KEY(0x06, 0x06, KEY_7) - MATRIX_KEY(0x06, 0x08, KEY_0) - MATRIX_KEY(0x06, 0x09, KEY_9) - MATRIX_KEY(0x06, 0x0a, KEY_LEFTALT) - MATRIX_KEY(0x06, 0x0b, KEY_DOWN) - MATRIX_KEY(0x06, 0x0c, KEY_RIGHT) - - MATRIX_KEY(0x07, 0x01, KEY_Q) - MATRIX_KEY(0x07, 0x02, KEY_E) - MATRIX_KEY(0x07, 0x03, KEY_R) - MATRIX_KEY(0x07, 0x04, KEY_W) - MATRIX_KEY(0x07, 0x05, KEY_I) - MATRIX_KEY(0x07, 0x06, KEY_U) - MATRIX_KEY(0x07, 0x07, KEY_RIGHTSHIFT) - MATRIX_KEY(0x07, 0x08, KEY_P) - MATRIX_KEY(0x07, 0x09, KEY_O) - MATRIX_KEY(0x07, 0x0b, KEY_UP) - MATRIX_KEY(0x07, 0x0c, KEY_LEFT) - >; - }; -}; diff --git a/sys/gnu/dts/arm/cros-ec-sbs.dtsi b/sys/gnu/dts/arm/cros-ec-sbs.dtsi deleted file mode 100644 index 71f5c5ecce4..00000000000 --- a/sys/gnu/dts/arm/cros-ec-sbs.dtsi +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Smart battery dts fragment for devices that use cros-ec-sbs - * - * Copyright (c) 2015 Google, Inc - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -&i2c_tunnel { - battery: sbs-battery@b { - compatible = "sbs,sbs-battery"; - reg = <0xb>; - sbs,i2c-retry-count = <2>; - sbs,poll-retry-count = <1>; - }; -}; diff --git a/sys/gnu/dts/arm/cx92755.dtsi b/sys/gnu/dts/arm/cx92755.dtsi deleted file mode 100644 index d2e8f36f8c6..00000000000 --- a/sys/gnu/dts/arm/cx92755.dtsi +++ /dev/null @@ -1,144 +0,0 @@ -/* - * Device Tree Include file for the Conexant Digicolor CX92755 SoC - * - * Author: Baruch Siach - * - * Copyright (C) 2014 Paradox Innovation Ltd. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/ { - #address-cells = <1>; - #size-cells = <1>; - compatible = "cnxt,cx92755"; - - interrupt-parent = <&intc>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a8"; - reg = <0x0>; - }; - }; - - main_clk: main_clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <200000000>; - }; - - intc: interrupt-controller@f0000040 { - compatible = "cnxt,cx92755-ic"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0xf0000040 0x40>; - syscon = <&uc_regs>; - }; - - timer@f0000fc0 { - compatible = "cnxt,cx92755-timer"; - reg = <0xf0000fc0 0x40>; - interrupts = <19>, <31>, <34>, <35>, <52>, <53>, <54>, <55>; - clocks = <&main_clk>; - }; - - rtc@f0000c30 { - compatible = "cnxt,cx92755-rtc"; - reg = <0xf0000c30 0x18>; - interrupts = <25>; - }; - - watchdog@f0000fc0 { - compatible = "cnxt,cx92755-wdt"; - reg = <0xf0000fc0 0x8>; - clocks = <&main_clk>; - timeout-sec = <15>; - }; - - pinctrl: pinctrl@f0000e20 { - compatible = "cnxt,cx92755-pinctrl"; - reg = <0xf0000e20 0x100>; - gpio-controller; - #gpio-cells = <2>; - }; - - uc_regs: syscon@f00003a0 { - compatible = "cnxt,cx92755-uc", "syscon"; - reg = <0xf00003a0 0x10>; - }; - - uart0: uart@f0000740 { - compatible = "cnxt,cx92755-usart"; - reg = <0xf0000740 0x20>; - clocks = <&main_clk>; - interrupts = <44>; - status = "disabled"; - }; - - uart1: uart@f0000760 { - compatible = "cnxt,cx92755-usart"; - reg = <0xf0000760 0x20>; - clocks = <&main_clk>; - interrupts = <45>; - status = "disabled"; - }; - - uart2: uart@f0000780 { - compatible = "cnxt,cx92755-usart"; - reg = <0xf0000780 0x20>; - clocks = <&main_clk>; - interrupts = <46>; - status = "disabled"; - }; - - i2c: i2c@f0000120 { - compatible = "cnxt,cx92755-i2c"; - reg = <0xf0000120 0x10>; - interrupts = <28>; - clocks = <&main_clk>; - clock-frequency = <100000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; -}; diff --git a/sys/gnu/dts/arm/cx92755_equinox.dts b/sys/gnu/dts/arm/cx92755_equinox.dts deleted file mode 100644 index 026f556c8c5..00000000000 --- a/sys/gnu/dts/arm/cx92755_equinox.dts +++ /dev/null @@ -1,86 +0,0 @@ -/* - * Device Tree file for the Conexant Equinox CX92755 EVK - * - * Author: Baruch Siach - * - * Copyright (C) 2014 Paradox Innovation Ltd. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include "cx92755.dtsi" - -/ { - model = "Conexant Equinox CX92755 EVK"; - compatible = "cnxt,equinox", "cnxt,cx92755"; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - }; - - memory@0 { - reg = <0 0x8000000>; - device_type = "memory"; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&uart0 { - status = "okay"; - pinctrl-0 = <&uart0_default>; - pinctrl-names = "default"; -}; - -&i2c { - status = "okay"; -}; - -&pinctrl { - uart0_default: uart0_active { - pins = "GP_O0", "GP_O1"; - function = "client_b"; - }; -}; diff --git a/sys/gnu/dts/arm/da850-enbw-cmc.dts b/sys/gnu/dts/arm/da850-enbw-cmc.dts deleted file mode 100644 index d4a5237cee0..00000000000 --- a/sys/gnu/dts/arm/da850-enbw-cmc.dts +++ /dev/null @@ -1,44 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Device Tree for AM1808 EnBW CMC board - * - * Copyright 2012 DENX Software Engineering GmbH - * Heiko Schocher - */ -/dts-v1/; -#include "da850.dtsi" - -/ { - compatible = "enbw,cmc", "ti,da850"; - model = "EnBW CMC"; - - soc@1c00000 { - serial0: serial@42000 { - status = "okay"; - }; - serial1: serial@10c000 { - status = "okay"; - }; - serial2: serial@10d000 { - status = "okay"; - }; - mdio: mdio@224000 { - status = "okay"; - }; - eth0: ethernet@220000 { - status = "okay"; - }; - }; -}; - -&ref_clk { - clock-frequency = <24000000>; -}; - -&edma0 { - ti,edma-reserved-slot-ranges = <32 50>; -}; - -&edma1 { - ti,edma-reserved-slot-ranges = <32 90>; -}; diff --git a/sys/gnu/dts/arm/da850-evm.dts b/sys/gnu/dts/arm/da850-evm.dts deleted file mode 100644 index f2e7609e534..00000000000 --- a/sys/gnu/dts/arm/da850-evm.dts +++ /dev/null @@ -1,466 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Device Tree for DA850 EVM board - * - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ - */ -/dts-v1/; -#include "da850.dtsi" -#include - -/ { - compatible = "ti,da850-evm", "ti,da850"; - model = "DA850/AM1808/OMAP-L138 EVM"; - - chosen { - stdout-path = &serial2; - }; - - aliases { - serial0 = &serial0; - serial1 = &serial1; - serial2 = &serial2; - ethernet0 = ð0; - spi0 = &spi1; - }; - - backlight: backlight-pwm { - pinctrl-names = "default"; - pinctrl-0 = <&ecap2_pins>; - power-supply = <&backlight_lcd>; - compatible = "pwm-backlight"; - /* - * The PWM here corresponds to production hardware. The - * schematic needs to be 1015171 (15 March 2010), Rev A - * or newer. - */ - pwms = <&ecap2 0 50000 0>; - brightness-levels = <0 10 20 30 40 50 60 70 80 90 99>; - default-brightness-level = <7>; - }; - - panel { - compatible = "ti,tilcdc,panel"; - pinctrl-names = "default"; - pinctrl-0 = <&lcd_pins>; - /* - * The vpif and the LCD are mutually exclusive. - * To enable VPIF, change the status below to 'disabled' then - * then change the status of the vpif below to 'okay' - */ - status = "okay"; - enable-gpios = <&gpio 40 GPIO_ACTIVE_HIGH>; /* lcd_panel_pwr */ - - panel-info { - ac-bias = <255>; - ac-bias-intrpt = <0>; - dma-burst-sz = <16>; - bpp = <16>; - fdd = <0x80>; - sync-edge = <0>; - sync-ctrl = <1>; - raster-order = <0>; - fifo-th = <0>; - }; - - display-timings { - native-mode = <&timing0>; - timing0: 480x272 { - clock-frequency = <9000000>; - hactive = <480>; - vactive = <272>; - hfront-porch = <3>; - hback-porch = <2>; - hsync-len = <42>; - vback-porch = <3>; - vfront-porch = <4>; - vsync-len = <11>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - }; - - vbat: fixedregulator0 { - compatible = "regulator-fixed"; - regulator-name = "vbat"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - }; - - baseboard_3v3: fixedregulator-3v3 { - /* TPS73701DCQ */ - compatible = "regulator-fixed"; - regulator-name = "baseboard_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vbat>; - regulator-always-on; - regulator-boot-on; - }; - - baseboard_1v8: fixedregulator-1v8 { - /* TPS73701DCQ */ - compatible = "regulator-fixed"; - regulator-name = "baseboard_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vbat>; - regulator-always-on; - regulator-boot-on; - }; - - backlight_lcd: backlight-regulator { - compatible = "regulator-fixed"; - regulator-name = "lcd_backlight_pwr"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio 47 GPIO_ACTIVE_HIGH>; /* lcd_backlight_pwr */ - enable-active-high; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "DA850-OMAPL138 EVM"; - simple-audio-card,widgets = - "Line", "Line In", - "Line", "Line Out"; - simple-audio-card,routing = - "LINE1L", "Line In", - "LINE1R", "Line In", - "Line Out", "LLOUT", - "Line Out", "RLOUT"; - simple-audio-card,format = "dsp_b"; - simple-audio-card,bitclock-master = <&link0_codec>; - simple-audio-card,frame-master = <&link0_codec>; - simple-audio-card,bitclock-inversion; - - simple-audio-card,cpu { - sound-dai = <&mcasp0>; - system-clock-frequency = <24576000>; - }; - - link0_codec: simple-audio-card,codec { - sound-dai = <&tlv320aic3106>; - system-clock-frequency = <24576000>; - }; - }; -}; - -&ecap2 { - status = "okay"; -}; - -&ref_clk { - clock-frequency = <24000000>; -}; - -&pmx_core { - status = "okay"; - - mcasp0_pins: pinmux_mcasp0_pins { - pinctrl-single,bits = < - /* - * AHCLKX, ACLKX, AFSX, AHCLKR, ACLKR, - * AFSR, AMUTE - */ - 0x00 0x11111111 0xffffffff - /* AXR11, AXR12 */ - 0x04 0x00011000 0x000ff000 - >; - }; - nand_pins: nand_pins { - pinctrl-single,bits = < - /* EMA_WAIT[0], EMA_OE, EMA_WE, EMA_CS[4], EMA_CS[3] */ - 0x1c 0x10110110 0xf0ff0ff0 - /* - * EMA_D[0], EMA_D[1], EMA_D[2], - * EMA_D[3], EMA_D[4], EMA_D[5], - * EMA_D[6], EMA_D[7] - */ - 0x24 0x11111111 0xffffffff - /* EMA_A[1], EMA_A[2] */ - 0x30 0x01100000 0x0ff00000 - >; - }; -}; - -&cpu { - cpu-supply = <&vdcdc3_reg>; -}; - -/* - * The standard da850-evm kits and SOM's are 375MHz so enable this operating - * point by default. Higher frequencies must be enabled for custom boards with - * other variants of the SoC. - */ -&opp_375 { - status = "okay"; -}; - -&sata { - status = "okay"; -}; - -&serial0 { - status = "okay"; -}; - -&serial1 { - status = "okay"; -}; - -&serial2 { - status = "okay"; -}; - -&rtc0 { - status = "okay"; -}; - -&lcdc { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - - tps: tps@48 { - reg = <0x48>; - }; - tlv320aic3106: tlv320aic3106@18 { - #sound-dai-cells = <0>; - compatible = "ti,tlv320aic3106"; - reg = <0x18>; - status = "okay"; - - /* Regulators */ - IOVDD-supply = <&vdcdc2_reg>; - AVDD-supply = <&baseboard_3v3>; - DRVDD-supply = <&baseboard_3v3>; - DVDD-supply = <&baseboard_1v8>; - }; - tca6416: gpio@20 { - compatible = "ti,tca6416"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - }; - tca6416_bb: gpio@21 { - compatible = "ti,tca6416"; - reg = <0x21>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -&wdt { - status = "okay"; -}; - -&mmc0 { - max-frequency = <50000000>; - bus-width = <4>; - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; - cd-gpios = <&gpio 64 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio 65 GPIO_ACTIVE_HIGH>; -}; - -&spi1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&spi1_pins &spi1_cs0_pin>; - flash: m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - spi-max-frequency = <30000000>; - m25p,fast-read; - reg = <0>; - partition@0 { - label = "U-Boot-SPL"; - reg = <0x00000000 0x00010000>; - read-only; - }; - partition@1 { - label = "U-Boot"; - reg = <0x00010000 0x00080000>; - read-only; - }; - partition@2 { - label = "U-Boot-Env"; - reg = <0x00090000 0x00010000>; - read-only; - }; - partition@3 { - label = "Kernel"; - reg = <0x000a0000 0x00280000>; - }; - partition@4 { - label = "Filesystem"; - reg = <0x00320000 0x00400000>; - }; - partition@5 { - label = "MAC-Address"; - reg = <0x007f0000 0x00010000>; - read-only; - }; - }; -}; - -&mdio { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mdio_pins>; - bus_freq = <2200000>; -}; - -ð0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mii_pins>; -}; - -&gpio { - status = "okay"; -}; - -/include/ "tps6507x.dtsi" - -&tps { - vdcdc1_2-supply = <&vbat>; - vdcdc3-supply = <&vbat>; - vldo1_2-supply = <&vbat>; - - regulators { - vdcdc1_reg: regulator@0 { - regulator-name = "VDCDC1_3.3V"; - regulator-min-microvolt = <3150000>; - regulator-max-microvolt = <3450000>; - regulator-always-on; - regulator-boot-on; - }; - - vdcdc2_reg: regulator@1 { - regulator-name = "VDCDC2_3.3V"; - regulator-min-microvolt = <1710000>; - regulator-max-microvolt = <3450000>; - regulator-always-on; - regulator-boot-on; - ti,defdcdc_default = <1>; - }; - - vdcdc3_reg: regulator@2 { - regulator-name = "VDCDC3_1.2V"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - ti,defdcdc_default = <1>; - }; - - ldo1_reg: regulator@3 { - regulator-name = "LDO1_1.8V"; - regulator-min-microvolt = <1710000>; - regulator-max-microvolt = <1890000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo2_reg: regulator@4 { - regulator-name = "LDO2_1.2V"; - regulator-min-microvolt = <1140000>; - regulator-max-microvolt = <1320000>; - regulator-always-on; - regulator-boot-on; - }; - }; -}; - -&mcasp0 { - #sound-dai-cells = <0>; - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mcasp0_pins>; - - op-mode = <0>; /* MCASP_IIS_MODE */ - tdm-slots = <2>; - /* 4 serializer */ - serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ - 0 0 0 0 - 0 0 0 0 - 0 0 0 1 - 2 0 0 0 - >; - tx-num-evt = <32>; - rx-num-evt = <32>; -}; - -&edma0 { - ti,edma-reserved-slot-ranges = <32 50>; -}; - -&edma1 { - ti,edma-reserved-slot-ranges = <32 90>; -}; - -&aemif { - pinctrl-names = "default"; - pinctrl-0 = <&nand_pins>; - status = "ok"; - cs3 { - #address-cells = <2>; - #size-cells = <1>; - clock-ranges; - ranges; - - ti,cs-chipselect = <3>; - - nand@2000000,0 { - compatible = "ti,davinci-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0 0x02000000 0x02000000 - 1 0x00000000 0x00008000>; - - ti,davinci-chipselect = <1>; - ti,davinci-mask-ale = <0>; - ti,davinci-mask-cle = <0>; - ti,davinci-mask-chipsel = <0>; - ti,davinci-ecc-mode = "hw"; - ti,davinci-ecc-bits = <4>; - ti,davinci-nand-use-bbt; - }; - }; -}; - -&usb_phy { - status = "okay"; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; - -&vpif { - pinctrl-names = "default"; - pinctrl-0 = <&vpif_capture_pins>, <&vpif_display_pins>; - /* - * The vpif and the LCD are mutually exclusive. - * To enable VPIF, disable the ti,tilcdc,panel then - * change the status below to 'okay' - */ - status = "disabled"; -}; diff --git a/sys/gnu/dts/arm/da850-lcdk.dts b/sys/gnu/dts/arm/da850-lcdk.dts deleted file mode 100644 index e379d6e7ad4..00000000000 --- a/sys/gnu/dts/arm/da850-lcdk.dts +++ /dev/null @@ -1,425 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2016 BayLibre, Inc. - */ -/dts-v1/; -#include "da850.dtsi" -#include -#include - -/ { - model = "DA850/AM1808/OMAP-L138 LCDK"; - compatible = "ti,da850-lcdk", "ti,da850"; - - aliases { - serial2 = &serial2; - ethernet0 = ð0; - }; - - chosen { - stdout-path = "serial2:115200n8"; - }; - - memory@c0000000 { - /* 128 MB DDR2 SDRAM @ 0xc0000000 */ - reg = <0xc0000000 0x08000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - dsp_memory_region: dsp-memory@c3000000 { - compatible = "shared-dma-pool"; - reg = <0xc3000000 0x1000000>; - reusable; - status = "okay"; - }; - }; - - vcc_5vd: fixedregulator-vcc_5vd { - compatible = "regulator-fixed"; - regulator-name = "vcc_5vd"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - }; - - vcc_3v3d: fixedregulator-vcc_3v3d { - /* TPS650250 - VDCDC1 */ - compatible = "regulator-fixed"; - regulator-name = "vcc_3v3d"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_5vd>; - regulator-always-on; - regulator-boot-on; - }; - - vcc_1v8d: fixedregulator-vcc_1v8d { - /* TPS650250 - VDCDC2 */ - compatible = "regulator-fixed"; - regulator-name = "vcc_1v8d"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_5vd>; - regulator-always-on; - regulator-boot-on; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "DA850-OMAPL138 LCDK"; - simple-audio-card,widgets = - "Line", "Line In", - "Line", "Line Out", - "Microphone", "Mic Jack"; - simple-audio-card,routing = - "LINE1L", "Line In", - "LINE1R", "Line In", - "Line Out", "LLOUT", - "Line Out", "RLOUT", - "MIC3L", "Mic Jack", - "MIC3R", "Mic Jack", - "Mic Jack", "Mic Bias"; - simple-audio-card,format = "dsp_b"; - simple-audio-card,bitclock-master = <&link0_codec>; - simple-audio-card,frame-master = <&link0_codec>; - simple-audio-card,bitclock-inversion; - - simple-audio-card,cpu { - sound-dai = <&mcasp0>; - system-clock-frequency = <24576000>; - }; - - link0_codec: simple-audio-card,codec { - sound-dai = <&tlv320aic3106>; - system-clock-frequency = <24576000>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - - user1 { - label = "GPIO Key USER1"; - linux,code = ; - gpios = <&gpio 36 GPIO_ACTIVE_LOW>; - }; - - user2 { - label = "GPIO Key USER2"; - linux,code = ; - gpios = <&gpio 37 GPIO_ACTIVE_LOW>; - }; - }; - - vga-bridge { - compatible = "ti,ths8135"; - #address-cells = <1>; - #size-cells = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - vga_bridge_in: endpoint { - remote-endpoint = <&lcdc_out_vga>; - }; - }; - - port@1 { - reg = <1>; - - vga_bridge_out: endpoint { - remote-endpoint = <&vga_con_in>; - }; - }; - }; - }; - - vga { - compatible = "vga-connector"; - - ddc-i2c-bus = <&i2c0>; - - port { - vga_con_in: endpoint { - remote-endpoint = <&vga_bridge_out>; - }; - }; - }; - - cvdd: regulator0 { - compatible = "regulator-fixed"; - regulator-name = "cvdd"; - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - }; -}; - -&ref_clk { - clock-frequency = <24000000>; -}; - -&cpu { - cpu-supply = <&cvdd>; -}; - -/* - * LCDK has a fixed CVDD of 1.3V, so only operating points >= 300MHz are - * valid. Unfortunately due to a problem with the DA8XX OHCI controller, we - * can't enable more than one OPP by default, since the controller sometimes - * becomes unresponsive after a transition. Fix the frequency at 456 MHz. - */ - -&opp_100 { - status = "disabled"; -}; - -&opp_200 { - status = "disabled"; -}; - -&opp_300 { - status = "disabled"; -}; - -&opp_456 { - status = "okay"; -}; - -&pmx_core { - status = "okay"; - - mcasp0_pins: pinmux_mcasp0_pins { - pinctrl-single,bits = < - /* AHCLKX AFSX ACLKX */ - 0x00 0x00101010 0x00f0f0f0 - /* ARX13 ARX14 */ - 0x04 0x00000110 0x00000ff0 - >; - }; - - nand_pins: nand_pins { - pinctrl-single,bits = < - /* EMA_WAIT[0], EMA_OE, EMA_WE, EMA_CS[3] */ - 0x1c 0x10110010 0xf0ff00f0 - /* - * EMA_D[0], EMA_D[1], EMA_D[2], - * EMA_D[3], EMA_D[4], EMA_D[5], - * EMA_D[6], EMA_D[7] - */ - 0x24 0x11111111 0xffffffff - /* - * EMA_D[8], EMA_D[9], EMA_D[10], - * EMA_D[11], EMA_D[12], EMA_D[13], - * EMA_D[14], EMA_D[15] - */ - 0x20 0x11111111 0xffffffff - /* EMA_A[1], EMA_A[2] */ - 0x30 0x01100000 0x0ff00000 - >; - }; -}; - -&serial2 { - pinctrl-names = "default"; - pinctrl-0 = <&serial2_rxtx_pins>; - status = "okay"; -}; - -&wdt { - status = "okay"; -}; - -&rtc0 { - status = "okay"; -}; - -&gpio { - status = "okay"; -}; - -&sata_refclk { - status = "okay"; - clock-frequency = <100000000>; -}; - -&sata { - status = "okay"; -}; - -&mdio { - pinctrl-names = "default"; - pinctrl-0 = <&mdio_pins>; - bus_freq = <2200000>; - status = "okay"; -}; - -ð0 { - pinctrl-names = "default"; - pinctrl-0 = <&mii_pins>; - status = "okay"; -}; - -&mmc0 { - max-frequency = <50000000>; - bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; - cd-gpios = <&gpio 64 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - clock-frequency = <100000>; - status = "okay"; - - tlv320aic3106: tlv320aic3106@18 { - #sound-dai-cells = <0>; - compatible = "ti,tlv320aic3106"; - reg = <0x18>; - adc-settle-ms = <40>; - ai3x-micbias-vg = <1>; /* 2.0V */ - status = "okay"; - - /* Regulators */ - IOVDD-supply = <&vcc_3v3d>; - AVDD-supply = <&vcc_3v3d>; - DRVDD-supply = <&vcc_3v3d>; - DVDD-supply = <&vcc_1v8d>; - }; -}; - -&mcasp0 { - #sound-dai-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&mcasp0_pins>; - status = "okay"; - - op-mode = <0>; /* DAVINCI_MCASP_IIS_MODE */ - tdm-slots = <2>; - serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ - 0 0 0 0 - 0 0 0 0 - 0 0 0 0 - 0 1 2 0 - >; - tx-num-evt = <32>; - rx-num-evt = <32>; -}; - -&usb_phy { - status = "okay"; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; - -&aemif { - pinctrl-names = "default"; - pinctrl-0 = <&nand_pins>; - status = "okay"; - cs3 { - #address-cells = <2>; - #size-cells = <1>; - clock-ranges; - ranges; - - ti,cs-chipselect = <3>; - - nand@2000000,0 { - compatible = "ti,davinci-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0 0x02000000 0x02000000 - 1 0x00000000 0x00008000>; - - ti,davinci-chipselect = <1>; - ti,davinci-mask-ale = <0>; - ti,davinci-mask-cle = <0>; - ti,davinci-mask-chipsel = <0>; - - ti,davinci-nand-buswidth = <16>; - ti,davinci-ecc-mode = "hw"; - ti,davinci-ecc-bits = <4>; - ti,davinci-nand-use-bbt; - - /* - * The OMAP-L132/L138 Bootloader doc SPRAB41E reads: - * "To boot from NAND Flash, the AIS should be written - * to NAND block 1 (NAND block 0 is not used by default)". - * The same doc mentions that for ROM "Silicon Revision 2.1", - * "Updated NAND boot mode to offer boot from block 0 or block 1". - * However the limitaion is left here by default for compatibility - * with older silicon and because it needs new boot pin settings - * not possible in stock LCDK. - */ - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot env"; - reg = <0 0x020000>; - }; - partition@20000 { - /* The LCDK defaults to booting from this partition */ - label = "u-boot"; - reg = <0x020000 0x080000>; - }; - partition@a0000 { - label = "free space"; - reg = <0x0a0000 0>; - }; - }; - }; - }; -}; - -&prictrl { - status = "okay"; -}; - -&memctrl { - status = "okay"; -}; - -&lcdc { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&lcd_pins>; - - port { - lcdc_out_vga: endpoint { - remote-endpoint = <&vga_bridge_in>; - }; - }; -}; - -&vpif { - pinctrl-names = "default"; - pinctrl-0 = <&vpif_capture_pins>; - status = "okay"; -}; - -&dsp { - memory-region = <&dsp_memory_region>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/da850-lego-ev3.dts b/sys/gnu/dts/arm/da850-lego-ev3.dts deleted file mode 100644 index afd04a42385..00000000000 --- a/sys/gnu/dts/arm/da850-lego-ev3.dts +++ /dev/null @@ -1,466 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Device tree for LEGO MINDSTORMS EV3 - * - * Copyright (C) 2017 David Lechner - */ - -/dts-v1/; -#include -#include -#include - -#include "da850.dtsi" - -/ { - compatible = "lego,ev3", "ti,da850"; - model = "LEGO MINDSTORMS EV3"; - - aliases { - serial1 = &serial1; - }; - - memory@c0000000 { - device_type = "memory"; - reg = <0xc0000000 0x04000000>; - }; - - /* - * The buttons on the EV3 are mapped to keyboard keys. - */ - gpio_keys { - compatible = "gpio-keys"; - label = "EV3 Brick Buttons"; - pinctrl-names = "default"; - pinctrl-0 = <&button_bias>; - - center { - label = "Center"; - linux,code = ; - gpios = <&gpio 29 GPIO_ACTIVE_HIGH>; - }; - - left { - label = "Left"; - linux,code = ; - gpios = <&gpio 102 GPIO_ACTIVE_HIGH>; - }; - - back { - label = "Back"; - linux,code = ; - gpios = <&gpio 106 GPIO_ACTIVE_HIGH>; - }; - - right { - label = "Right"; - linux,code = ; - gpios = <&gpio 124 GPIO_ACTIVE_HIGH>; - }; - - down { - label = "Down"; - linux,code = ; - gpios = <&gpio 126 GPIO_ACTIVE_HIGH>; - }; - - up { - label = "Up"; - linux,code = ; - gpios = <&gpio 127 GPIO_ACTIVE_HIGH>; - }; - }; - - /* - * The EV3 has two built-in bi-color LEDs behind the buttons. - */ - leds { - compatible = "gpio-leds"; - - left_green { - label = "led0:green:brick-status"; - /* GP6[13] */ - gpios = <&gpio 103 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - }; - - right_red { - label = "led1:red:brick-status"; - /* GP6[7] */ - gpios = <&gpio 108 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - }; - - left_red { - label = "led0:red:brick-status"; - /* GP6[12] */ - gpios = <&gpio 109 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - }; - - right_green { - label = "led1:green:brick-status"; - /* GP6[14] */ - gpios = <&gpio 110 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - }; - }; - - /* - * The EV3 is powered down by turning off the main 5V supply. - */ - gpio-poweroff { - compatible = "gpio-poweroff"; - gpios = <&gpio 107 GPIO_ACTIVE_LOW>; - }; - - sound { - compatible = "pwm-beeper"; - pinctrl-names = "default"; - pinctrl-0 = <&ehrpwm0b_pins>; - pwms = <&ehrpwm0 1 1000000 0>; - amp-supply = <&>; - }; - - cvdd: regulator0 { - compatible = "regulator-fixed"; - regulator-name = "cvdd"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - }; - - /* - * This is a 5V current limiting regulator that is shared by USB, - * the sensor (input) ports, the motor (output) ports and the A/DC. - */ - vcc5v: regulator1 { - compatible = "regulator-fixed"; - regulator-name = "vcc5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio 101 0>; - over-current-gpios = <&gpio 99 GPIO_ACTIVE_LOW>; - enable-active-high; - regulator-boot-on; - }; - - /* - * This is a simple voltage divider on VCC5V to provide a 2.5V - * reference signal to the ADC. - */ - adc_ref: regulator2 { - compatible = "regulator-fixed"; - regulator-name = "adc ref"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-boot-on; - vin-supply = <&vcc5v>; - }; - - /* - * This is the amplifier for the speaker. - */ - amp: regulator3 { - compatible = "regulator-fixed"; - regulator-name = "amp"; - gpio = <&gpio 111 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - /* - * The EV3 can use 6-AA batteries or a rechargeable Li-ion battery pack. - */ - battery { - compatible = "lego,ev3-battery"; - io-channels = <&adc 4>, <&adc 3>; - io-channel-names = "voltage", "current"; - rechargeable-gpios = <&gpio 136 GPIO_ACTIVE_LOW>; - }; - - bt_slow_clk: bt-clock { - pinctrl-names = "default"; - pinctrl-0 = <&ecap2_pins>, <&bt_clock_bias>; - compatible = "pwm-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - pwms = <&ecap2 0 30518 0>; - }; - - /* ARM local RAM */ - memory@ffff0000 { - compatible = "syscon", "simple-mfd"; - reg = <0xffff0000 0x2000>; /* 8k */ - - /* - * The I2C bootloader looks for this magic value to either - * boot normally or boot into a firmware update mode. - */ - reboot-mode { - compatible = "syscon-reboot-mode"; - offset = <0x1ffc>; - mode-normal = <0x00000000>; - mode-loader = <0x5555aaaa>; - }; - }; -}; - -&ref_clk { - clock-frequency = <24000000>; -}; - -&cpu { - cpu-supply = <&cvdd>; -}; - -/* since we have a fixed regulator, we can't run at these points */ -&opp_100 { - status = "disabled"; -}; - -&opp_200 { - status = "disabled"; -}; - -/* - * The SoC is actually the 456MHz version, but because of the fixed regulator - * This is the fastest we can go. - */ -&opp_375 { - status = "okay"; -}; - -&pmx_core { - status = "okay"; - - ev3_lcd_pins: pinmux_lcd { - pinctrl-single,bits = < - /* SIMO, CLK */ - 0x14 0x00100100 0x00f00f00 - >; - }; -}; - -&pinconf { - status = "okay"; - - /* Buttons have external pulldown resistors */ - button_bias: button-bias-groups { - disable { - groups = "cp5", "cp24", "cp25", "cp28"; - bias-disable; - }; - }; - - bt_clock_bias: bt-clock-bias-groups { - disable { - groups = "cp2"; - bias-disable; - }; - }; - - bt_pic_bias: bt-pic-bias-groups { - disable { - groups = "cp20"; - bias-disable; - }; - }; -}; - -/* Input port 1 */ -&serial1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&serial1_rxtx_pins>; -}; - -&serial2 { - pinctrl-names = "default"; - pinctrl-0 = <&serial2_rxtx_pins>, <&serial2_rtscts_pins>, <&bt_pic_bias>; - status = "okay"; - - bluetooth { - compatible = "ti,cc2560"; - clocks = <&bt_slow_clk>; - clock-names = "ext_clock"; - enable-gpios = <&gpio 73 GPIO_ACTIVE_HIGH>; - max-speed = <2000000>; - nvmem-cells = <&bdaddr>; - nvmem-cell-names = "bd-address"; - }; -}; - -&rtc0 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - - /* - * EEPROM contains the first stage bootloader, HW ID and Bluetooth MAC. - */ - eeprom@50 { - compatible = "microchip,24c128", "atmel,24c128"; - pagesize = <64>; - read-only; - reg = <0x50>; - #address-cells = <1>; - #size-cells = <1>; - - bdaddr: bdaddr@3f06 { - reg = <0x3f06 0x06>; - }; - }; -}; - -&wdt { - status = "okay"; -}; - -&mmc0 { - status = "okay"; - max-frequency = <50000000>; - bus-width = <4>; - cd-gpios = <&gpio 94 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; -}; - -&spi0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins>, <&spi0_cs0_pin>, <&spi0_cs3_pin>; - - flash@0 { - compatible = "n25q128a13", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <50000000>; - ti,spi-wdelay = <8>; - - /* Partitions are based on the official firmware from LEGO */ - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "U-Boot"; - reg = <0 0x40000>; - }; - - partition@40000 { - label = "U-Boot Env"; - reg = <0x40000 0x10000>; - }; - - partition@50000 { - label = "Kernel"; - reg = <0x50000 0x200000>; - }; - - partition@250000 { - label = "Filesystem"; - reg = <0x250000 0xa50000>; - }; - - partition@cb0000 { - label = "Storage"; - reg = <0xcb0000 0x2f0000>; - }; - }; - }; - - adc: adc@3 { - compatible = "ti,ads7957"; - reg = <3>; - #io-channel-cells = <1>; - spi-max-frequency = <1000000>; - ti,spi-wdelay = <63>; - vref-supply = <&adc_ref>; - }; -}; - -&spi1 { - status = "okay"; - pinctrl-0 = <&ev3_lcd_pins>; - pinctrl-names = "default"; - cs-gpios = <&gpio 44 GPIO_ACTIVE_LOW>; - - display@0{ - compatible = "lego,ev3-lcd"; - reg = <0>; - spi-max-frequency = <10000000>; - a0-gpios = <&gpio 43 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio 80 GPIO_ACTIVE_HIGH>; - }; -}; - -&ecap2 { - status = "okay"; -}; - -&ehrpwm0 { - status = "okay"; -}; - -&gpio { - status = "okay"; - - /* Don't pull down battery voltage adc io channel */ - batt_volt_en { - gpio-hog; - gpios = <6 GPIO_ACTIVE_HIGH>; - output-high; - }; - - /* Don't impede Bluetooth clock signal */ - bt_clock_en { - gpio-hog; - gpios = <5 GPIO_ACTIVE_HIGH>; - input; - }; - - /* - * There is a PIC microcontroller for interfacing with an Apple MFi - * chip. This interferes with normal Bluetooth operation, so we need - * to make sure it is turned off. Note: The publicly available - * schematics from LEGO don't show that these pins are connected to - * anything, but they are present in the source code from LEGO. - */ - - bt_pic_en { - gpio-hog; - gpios = <51 GPIO_ACTIVE_HIGH>; - output-low; - }; - - bt_pic_rst { - gpio-hog; - gpios = <78 GPIO_ACTIVE_HIGH>; - output-high; - }; - - bt_pic_cts { - gpio-hog; - gpios = <87 GPIO_ACTIVE_HIGH>; - input; - }; -}; - -&usb_phy { - status = "okay"; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; - vbus-supply = <&vcc5v>; -}; diff --git a/sys/gnu/dts/arm/da850.dtsi b/sys/gnu/dts/arm/da850.dtsi deleted file mode 100644 index 7cf31b6e48b..00000000000 --- a/sys/gnu/dts/arm/da850.dtsi +++ /dev/null @@ -1,967 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2012 DENX Software Engineering GmbH - * Heiko Schocher - */ -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - chosen { }; - aliases { }; - - memory@c0000000 { - device_type = "memory"; - reg = <0xc0000000 0x0>; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu: cpu@0 { - compatible = "arm,arm926ej-s"; - device_type = "cpu"; - reg = <0>; - clocks = <&psc0 14>; - operating-points-v2 = <&opp_table>; - }; - }; - - opp_table: opp-table { - compatible = "operating-points-v2"; - - opp_100: opp100-100000000 { - opp-hz = /bits/ 64 <100000000>; - opp-microvolt = <1000000 950000 1050000>; - }; - - opp_200: opp110-200000000 { - opp-hz = /bits/ 64 <200000000>; - opp-microvolt = <1100000 1050000 1160000>; - }; - - opp_300: opp120-300000000 { - opp-hz = /bits/ 64 <300000000>; - opp-microvolt = <1200000 1140000 1320000>; - }; - - /* - * Original silicon was 300MHz max, so higher frequencies - * need to be enabled on a per-board basis if the chip is - * capable. - */ - - opp_375: opp120-375000000 { - status = "disabled"; - opp-hz = /bits/ 64 <375000000>; - opp-microvolt = <1200000 1140000 1320000>; - }; - - opp_456: opp130-456000000 { - status = "disabled"; - opp-hz = /bits/ 64 <456000000>; - opp-microvolt = <1300000 1250000 1350000>; - }; - }; - - arm { - #address-cells = <1>; - #size-cells = <1>; - ranges; - intc: interrupt-controller@fffee000 { - compatible = "ti,cp-intc"; - interrupt-controller; - #interrupt-cells = <1>; - ti,intc-size = <101>; - reg = <0xfffee000 0x2000>; - }; - }; - clocks: clocks { - ref_clk: ref_clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-output-names = "ref_clk"; - }; - sata_refclk: sata_refclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-output-names = "sata_refclk"; - status = "disabled"; - }; - usb_refclkin: usb_refclkin { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-output-names = "usb_refclkin"; - status = "disabled"; - }; - }; - dsp: dsp@11800000 { - compatible = "ti,da850-dsp"; - reg = <0x11800000 0x40000>, - <0x11e00000 0x8000>, - <0x11f00000 0x8000>, - <0x01c14044 0x4>, - <0x01c14174 0x8>; - reg-names = "l2sram", "l1pram", "l1dram", "host1cfg", "chipsig"; - interrupt-parent = <&intc>; - interrupts = <28>; - clocks = <&psc0 15>; - resets = <&psc0 15>; - status = "disabled"; - }; - soc@1c00000 { - compatible = "simple-bus"; - model = "da850"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x01c00000 0x400000>; - interrupt-parent = <&intc>; - - psc0: clock-controller@10000 { - compatible = "ti,da850-psc0"; - reg = <0x10000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - clocks = <&pll0_sysclk 1>, <&pll0_sysclk 2>, - <&pll0_sysclk 4>, <&pll0_sysclk 6>, - <&async1_clk>; - clock-names = "pll0_sysclk1", "pll0_sysclk2", - "pll0_sysclk4", "pll0_sysclk6", - "async1"; - }; - pll0: clock-controller@11000 { - compatible = "ti,da850-pll0"; - reg = <0x11000 0x1000>; - clocks = <&ref_clk>, <&pll1_sysclk 3>; - clock-names = "clksrc", "extclksrc"; - - pll0_pllout: pllout { - #clock-cells = <0>; - }; - pll0_sysclk: sysclk { - #clock-cells = <1>; - }; - pll0_auxclk: auxclk { - #clock-cells = <0>; - }; - pll0_obsclk: obsclk { - #clock-cells = <0>; - }; - }; - pmx_core: pinmux@14120 { - compatible = "pinctrl-single"; - reg = <0x14120 0x50>; - #pinctrl-cells = <2>; - pinctrl-single,bit-per-mux; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0xf>; - /* pin base, nr pins & gpio function */ - pinctrl-single,gpio-range = <&range 0 17 0x8>, - <&range 17 8 0x4>, - <&range 26 8 0x4>, - <&range 34 80 0x8>, - <&range 129 31 0x8>; - status = "disabled"; - - range: gpio-range { - #pinctrl-single,gpio-range-cells = <3>; - }; - - serial0_rtscts_pins: pinmux_serial0_rtscts_pins { - pinctrl-single,bits = < - /* UART0_RTS UART0_CTS */ - 0x0c 0x22000000 0xff000000 - >; - }; - serial0_rxtx_pins: pinmux_serial0_rxtx_pins { - pinctrl-single,bits = < - /* UART0_TXD UART0_RXD */ - 0x0c 0x00220000 0x00ff0000 - >; - }; - serial1_rtscts_pins: pinmux_serial1_rtscts_pins { - pinctrl-single,bits = < - /* UART1_CTS UART1_RTS */ - 0x00 0x00440000 0x00ff0000 - >; - }; - serial1_rxtx_pins: pinmux_serial1_rxtx_pins { - pinctrl-single,bits = < - /* UART1_TXD UART1_RXD */ - 0x10 0x22000000 0xff000000 - >; - }; - serial2_rtscts_pins: pinmux_serial2_rtscts_pins { - pinctrl-single,bits = < - /* UART2_CTS UART2_RTS */ - 0x00 0x44000000 0xff000000 - >; - }; - serial2_rxtx_pins: pinmux_serial2_rxtx_pins { - pinctrl-single,bits = < - /* UART2_TXD UART2_RXD */ - 0x10 0x00220000 0x00ff0000 - >; - }; - i2c0_pins: pinmux_i2c0_pins { - pinctrl-single,bits = < - /* I2C0_SDA,I2C0_SCL */ - 0x10 0x00002200 0x0000ff00 - >; - }; - i2c1_pins: pinmux_i2c1_pins { - pinctrl-single,bits = < - /* I2C1_SDA, I2C1_SCL */ - 0x10 0x00440000 0x00ff0000 - >; - }; - mmc0_pins: pinmux_mmc_pins { - pinctrl-single,bits = < - /* MMCSD0_DAT[3] MMCSD0_DAT[2] - * MMCSD0_DAT[1] MMCSD0_DAT[0] - * MMCSD0_CMD MMCSD0_CLK - */ - 0x28 0x00222222 0x00ffffff - >; - }; - ehrpwm0a_pins: pinmux_ehrpwm0a_pins { - pinctrl-single,bits = < - /* EPWM0A */ - 0xc 0x00000002 0x0000000f - >; - }; - ehrpwm0b_pins: pinmux_ehrpwm0b_pins { - pinctrl-single,bits = < - /* EPWM0B */ - 0xc 0x00000020 0x000000f0 - >; - }; - ehrpwm1a_pins: pinmux_ehrpwm1a_pins { - pinctrl-single,bits = < - /* EPWM1A */ - 0x14 0x00000002 0x0000000f - >; - }; - ehrpwm1b_pins: pinmux_ehrpwm1b_pins { - pinctrl-single,bits = < - /* EPWM1B */ - 0x14 0x00000020 0x000000f0 - >; - }; - ecap0_pins: pinmux_ecap0_pins { - pinctrl-single,bits = < - /* ECAP0_APWM0 */ - 0x8 0x20000000 0xf0000000 - >; - }; - ecap1_pins: pinmux_ecap1_pins { - pinctrl-single,bits = < - /* ECAP1_APWM1 */ - 0x4 0x40000000 0xf0000000 - >; - }; - ecap2_pins: pinmux_ecap2_pins { - pinctrl-single,bits = < - /* ECAP2_APWM2 */ - 0x4 0x00000004 0x0000000f - >; - }; - spi0_pins: pinmux_spi0_pins { - pinctrl-single,bits = < - /* SIMO, SOMI, CLK */ - 0xc 0x00001101 0x0000ff0f - >; - }; - spi0_cs0_pin: pinmux_spi0_cs0 { - pinctrl-single,bits = < - /* CS0 */ - 0x10 0x00000010 0x000000f0 - >; - }; - spi0_cs3_pin: pinmux_spi0_cs3_pin { - pinctrl-single,bits = < - /* CS3 */ - 0xc 0x01000000 0x0f000000 - >; - }; - spi1_pins: pinmux_spi1_pins { - pinctrl-single,bits = < - /* SIMO, SOMI, CLK */ - 0x14 0x00110100 0x00ff0f00 - >; - }; - spi1_cs0_pin: pinmux_spi1_cs0 { - pinctrl-single,bits = < - /* CS0 */ - 0x14 0x00000010 0x000000f0 - >; - }; - mdio_pins: pinmux_mdio_pins { - pinctrl-single,bits = < - /* MDIO_CLK, MDIO_D */ - 0x10 0x00000088 0x000000ff - >; - }; - mii_pins: pinmux_mii_pins { - pinctrl-single,bits = < - /* - * MII_TXEN, MII_TXCLK, MII_COL - * MII_TXD_3, MII_TXD_2, MII_TXD_1 - * MII_TXD_0 - */ - 0x8 0x88888880 0xfffffff0 - /* - * MII_RXER, MII_CRS, MII_RXCLK - * MII_RXDV, MII_RXD_3, MII_RXD_2 - * MII_RXD_1, MII_RXD_0 - */ - 0xc 0x88888888 0xffffffff - >; - }; - lcd_pins: pinmux_lcd_pins { - pinctrl-single,bits = < - /* - * LCD_D[2], LCD_D[3], LCD_D[4], LCD_D[5], - * LCD_D[6], LCD_D[7] - */ - 0x40 0x22222200 0xffffff00 - /* - * LCD_D[10], LCD_D[11], LCD_D[12], LCD_D[13], - * LCD_D[14], LCD_D[15], LCD_D[0], LCD_D[1] - */ - 0x44 0x22222222 0xffffffff - /* LCD_D[8], LCD_D[9] */ - 0x48 0x00000022 0x000000ff - - /* LCD_PCLK */ - 0x48 0x02000000 0x0f000000 - /* LCD_AC_ENB_CS, LCD_VSYNC, LCD_HSYNC */ - 0x4c 0x02000022 0x0f0000ff - >; - }; - vpif_capture_pins: vpif_capture_pins { - pinctrl-single,bits = < - /* VP_DIN[2..7], VP_CLKIN1, VP_CLKIN0 */ - 0x38 0x11111111 0xffffffff - /* VP_DIN[10..15,0..1] */ - 0x3c 0x11111111 0xffffffff - /* VP_DIN[8..9] */ - 0x40 0x00000011 0x000000ff - >; - }; - vpif_display_pins: vpif_display_pins { - pinctrl-single,bits = < - /* VP_DOUT[2..7] */ - 0x40 0x11111100 0xffffff00 - /* VP_DOUT[10..15,0..1] */ - 0x44 0x11111111 0xffffffff - /* VP_DOUT[8..9] */ - 0x48 0x00000011 0x000000ff - /* - * VP_CLKOUT3, VP_CLKIN3, - * VP_CLKOUT2, VP_CLKIN2 - */ - 0x4c 0x00111100 0x00ffff00 - >; - }; - }; - prictrl: priority-controller@14110 { - compatible = "ti,da850-mstpri"; - reg = <0x14110 0x0c>; - status = "disabled"; - }; - cfgchip: chip-controller@1417c { - compatible = "ti,da830-cfgchip", "syscon", "simple-mfd"; - reg = <0x1417c 0x14>; - - usb_phy: usb-phy { - compatible = "ti,da830-usb-phy"; - #phy-cells = <1>; - clocks = <&usb_phy_clk 0>, <&usb_phy_clk 1>; - clock-names = "usb0_clk48", "usb1_clk48"; - status = "disabled"; - }; - usb_phy_clk: usb-phy-clocks { - compatible = "ti,da830-usb-phy-clocks"; - #clock-cells = <1>; - clocks = <&psc1 1>, <&usb_refclkin>, - <&pll0_auxclk>; - clock-names = "fck", "usb_refclkin", "auxclk"; - }; - ehrpwm_tbclk: ehrpwm_tbclk { - compatible = "ti,da830-tbclksync"; - #clock-cells = <0>; - clocks = <&psc1 17>; - clock-names = "fck"; - }; - div4p5_clk: div4.5 { - compatible = "ti,da830-div4p5ena"; - #clock-cells = <0>; - clocks = <&pll0_pllout>; - clock-names = "pll0_pllout"; - }; - async1_clk: async1 { - compatible = "ti,da850-async1-clksrc"; - #clock-cells = <0>; - clocks = <&pll0_sysclk 3>, <&div4p5_clk>; - clock-names = "pll0_sysclk3", "div4.5"; - }; - async3_clk: async3 { - compatible = "ti,da850-async3-clksrc"; - #clock-cells = <0>; - clocks = <&pll0_sysclk 2>, <&pll1_sysclk 2>; - clock-names = "pll0_sysclk2", "pll1_sysclk2"; - }; - }; - edma0: edma@0 { - compatible = "ti,edma3-tpcc"; - /* eDMA3 CC0: 0x01c0 0000 - 0x01c0 7fff */ - reg = <0x0 0x8000>; - reg-names = "edma3_cc"; - interrupts = <11 12>; - interrupt-names = "edma3_ccint", "edma3_ccerrint"; - #dma-cells = <2>; - - ti,tptcs = <&edma0_tptc0 7>, <&edma0_tptc1 0>; - power-domains = <&psc0 0>; - }; - edma0_tptc0: tptc@8000 { - compatible = "ti,edma3-tptc"; - reg = <0x8000 0x400>; - interrupts = <13>; - interrupt-names = "edm3_tcerrint"; - power-domains = <&psc0 1>; - }; - edma0_tptc1: tptc@8400 { - compatible = "ti,edma3-tptc"; - reg = <0x8400 0x400>; - interrupts = <32>; - interrupt-names = "edm3_tcerrint"; - power-domains = <&psc0 2>; - }; - edma1: edma@230000 { - compatible = "ti,edma3-tpcc"; - /* eDMA3 CC1: 0x01e3 0000 - 0x01e3 7fff */ - reg = <0x230000 0x8000>; - reg-names = "edma3_cc"; - interrupts = <93 94>; - interrupt-names = "edma3_ccint", "edma3_ccerrint"; - #dma-cells = <2>; - - ti,tptcs = <&edma1_tptc0 7>; - power-domains = <&psc1 0>; - }; - edma1_tptc0: tptc@238000 { - compatible = "ti,edma3-tptc"; - reg = <0x238000 0x400>; - interrupts = <95>; - interrupt-names = "edm3_tcerrint"; - power-domains = <&psc1 21>; - }; - serial0: serial@42000 { - compatible = "ti,da830-uart", "ns16550a"; - reg = <0x42000 0x100>; - reg-io-width = <4>; - reg-shift = <2>; - interrupts = <25>; - clocks = <&psc0 9>; - power-domains = <&psc0 9>; - status = "disabled"; - }; - serial1: serial@10c000 { - compatible = "ti,da830-uart", "ns16550a"; - reg = <0x10c000 0x100>; - reg-io-width = <4>; - reg-shift = <2>; - interrupts = <53>; - clocks = <&psc1 12>; - power-domains = <&psc1 12>; - status = "disabled"; - }; - serial2: serial@10d000 { - compatible = "ti,da830-uart", "ns16550a"; - reg = <0x10d000 0x100>; - reg-io-width = <4>; - reg-shift = <2>; - interrupts = <61>; - clocks = <&psc1 13>; - power-domains = <&psc1 13>; - status = "disabled"; - }; - rtc0: rtc@23000 { - compatible = "ti,da830-rtc"; - reg = <0x23000 0x1000>; - interrupts = <19 - 19>; - clocks = <&pll0_auxclk>; - clock-names = "int-clk"; - status = "disabled"; - }; - i2c0: i2c@22000 { - compatible = "ti,davinci-i2c"; - reg = <0x22000 0x1000>; - interrupts = <15>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&pll0_auxclk>; - status = "disabled"; - }; - i2c1: i2c@228000 { - compatible = "ti,davinci-i2c"; - reg = <0x228000 0x1000>; - interrupts = <51>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&psc1 11>; - power-domains = <&psc1 11>; - status = "disabled"; - }; - clocksource: timer@20000 { - compatible = "ti,da830-timer"; - reg = <0x20000 0x1000>; - interrupts = <21>, <22>; - interrupt-names = "tint12", "tint34"; - clocks = <&pll0_auxclk>; - }; - wdt: wdt@21000 { - compatible = "ti,davinci-wdt"; - reg = <0x21000 0x1000>; - clocks = <&pll0_auxclk>; - status = "disabled"; - }; - mmc0: mmc@40000 { - compatible = "ti,da830-mmc"; - reg = <0x40000 0x1000>; - cap-sd-highspeed; - cap-mmc-highspeed; - interrupts = <16>; - dmas = <&edma0 16 0>, <&edma0 17 0>; - dma-names = "rx", "tx"; - clocks = <&psc0 5>; - status = "disabled"; - }; - vpif: video@217000 { - compatible = "ti,da850-vpif"; - reg = <0x217000 0x1000>; - interrupts = <92>; - power-domains = <&psc1 9>; - status = "disabled"; - - /* VPIF capture port */ - port@0 { - #address-cells = <1>; - #size-cells = <0>; - }; - - /* VPIF display port */ - port@1 { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - mmc1: mmc@21b000 { - compatible = "ti,da830-mmc"; - reg = <0x21b000 0x1000>; - cap-sd-highspeed; - cap-mmc-highspeed; - interrupts = <72>; - dmas = <&edma1 28 0>, <&edma1 29 0>; - dma-names = "rx", "tx"; - clocks = <&psc1 18>; - status = "disabled"; - }; - ehrpwm0: pwm@300000 { - compatible = "ti,da850-ehrpwm", "ti,am3352-ehrpwm", - "ti,am33xx-ehrpwm"; - #pwm-cells = <3>; - reg = <0x300000 0x2000>; - clocks = <&psc1 17>, <&ehrpwm_tbclk>; - clock-names = "fck", "tbclk"; - power-domains = <&psc1 17>; - status = "disabled"; - }; - ehrpwm1: pwm@302000 { - compatible = "ti,da850-ehrpwm", "ti,am3352-ehrpwm", - "ti,am33xx-ehrpwm"; - #pwm-cells = <3>; - reg = <0x302000 0x2000>; - clocks = <&psc1 17>, <&ehrpwm_tbclk>; - clock-names = "fck", "tbclk"; - power-domains = <&psc1 17>; - status = "disabled"; - }; - ecap0: ecap@306000 { - compatible = "ti,da850-ecap", "ti,am3352-ecap", - "ti,am33xx-ecap"; - #pwm-cells = <3>; - reg = <0x306000 0x80>; - clocks = <&psc1 20>; - clock-names = "fck"; - power-domains = <&psc1 20>; - status = "disabled"; - }; - ecap1: ecap@307000 { - compatible = "ti,da850-ecap", "ti,am3352-ecap", - "ti,am33xx-ecap"; - #pwm-cells = <3>; - reg = <0x307000 0x80>; - clocks = <&psc1 20>; - clock-names = "fck"; - power-domains = <&psc1 20>; - status = "disabled"; - }; - ecap2: ecap@308000 { - compatible = "ti,da850-ecap", "ti,am3352-ecap", - "ti,am33xx-ecap"; - #pwm-cells = <3>; - reg = <0x308000 0x80>; - clocks = <&psc1 20>; - clock-names = "fck"; - power-domains = <&psc1 20>; - status = "disabled"; - }; - spi0: spi@41000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "ti,da830-spi"; - reg = <0x41000 0x1000>; - num-cs = <6>; - ti,davinci-spi-intr-line = <1>; - interrupts = <20>; - dmas = <&edma0 14 0>, <&edma0 15 0>; - dma-names = "rx", "tx"; - clocks = <&psc0 4>; - power-domains = <&psc0 4>; - status = "disabled"; - }; - spi1: spi@30e000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "ti,da830-spi"; - reg = <0x30e000 0x1000>; - num-cs = <4>; - ti,davinci-spi-intr-line = <1>; - interrupts = <56>; - dmas = <&edma0 18 0>, <&edma0 19 0>; - dma-names = "rx", "tx"; - clocks = <&psc1 10>; - power-domains = <&psc1 10>; - status = "disabled"; - }; - usb0: usb@200000 { - compatible = "ti,da830-musb"; - reg = <0x200000 0x1000>; - ranges; - interrupts = <58>; - interrupt-names = "mc"; - dr_mode = "otg"; - phys = <&usb_phy 0>; - phy-names = "usb-phy"; - clocks = <&psc1 1>; - clock-ranges; - status = "disabled"; - - #address-cells = <1>; - #size-cells = <1>; - - dmas = <&cppi41dma 0 0 &cppi41dma 1 0 - &cppi41dma 2 0 &cppi41dma 3 0 - &cppi41dma 0 1 &cppi41dma 1 1 - &cppi41dma 2 1 &cppi41dma 3 1>; - dma-names = - "rx1", "rx2", "rx3", "rx4", - "tx1", "tx2", "tx3", "tx4"; - - cppi41dma: dma-controller@201000 { - compatible = "ti,da830-cppi41"; - reg = <0x201000 0x1000 - 0x202000 0x1000 - 0x204000 0x4000>; - reg-names = "controller", - "scheduler", "queuemgr"; - interrupts = <58>; - #dma-cells = <2>; - #dma-channels = <4>; - power-domains = <&psc1 1>; - status = "okay"; - }; - }; - sata: sata@218000 { - compatible = "ti,da850-ahci"; - reg = <0x218000 0x2000>, <0x22c018 0x4>; - interrupts = <67>; - clocks = <&psc1 8>, <&sata_refclk>; - clock-names = "fck", "refclk"; - status = "disabled"; - }; - pll1: clock-controller@21a000 { - compatible = "ti,da850-pll1"; - reg = <0x21a000 0x1000>; - clocks = <&ref_clk>; - clock-names = "clksrc"; - - pll1_sysclk: sysclk { - #clock-cells = <1>; - }; - pll1_obsclk: obsclk { - #clock-cells = <0>; - }; - }; - mdio: mdio@224000 { - compatible = "ti,davinci_mdio"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x224000 0x1000>; - clocks = <&psc1 5>; - clock-names = "fck"; - power-domains = <&psc1 5>; - status = "disabled"; - }; - eth0: ethernet@220000 { - compatible = "ti,davinci-dm6467-emac"; - reg = <0x220000 0x4000>; - ti,davinci-ctrl-reg-offset = <0x3000>; - ti,davinci-ctrl-mod-reg-offset = <0x2000>; - ti,davinci-ctrl-ram-offset = <0>; - ti,davinci-ctrl-ram-size = <0x2000>; - local-mac-address = [ 00 00 00 00 00 00 ]; - interrupts = <33 - 34 - 35 - 36 - >; - clocks = <&psc1 5>; - power-domains = <&psc1 5>; - status = "disabled"; - }; - usb1: usb@225000 { - compatible = "ti,da830-ohci"; - reg = <0x225000 0x1000>; - interrupts = <59>; - phys = <&usb_phy 1>; - phy-names = "usb-phy"; - clocks = <&psc1 2>; - status = "disabled"; - }; - gpio: gpio@226000 { - compatible = "ti,dm6441-gpio"; - gpio-controller; - #gpio-cells = <2>; - reg = <0x226000 0x1000>; - interrupts = <42 43 44 45 46 47 48 49 50>; - ti,ngpio = <144>; - ti,davinci-gpio-unbanked = <0>; - clocks = <&psc1 3>; - clock-names = "gpio"; - status = "disabled"; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&pmx_core 0 15 1>, - <&pmx_core 1 14 1>, - <&pmx_core 2 13 1>, - <&pmx_core 3 12 1>, - <&pmx_core 4 11 1>, - <&pmx_core 5 10 1>, - <&pmx_core 6 9 1>, - <&pmx_core 7 8 1>, - <&pmx_core 8 7 1>, - <&pmx_core 9 6 1>, - <&pmx_core 10 5 1>, - <&pmx_core 11 4 1>, - <&pmx_core 12 3 1>, - <&pmx_core 13 2 1>, - <&pmx_core 14 1 1>, - <&pmx_core 15 0 1>, - <&pmx_core 16 39 1>, - <&pmx_core 17 38 1>, - <&pmx_core 18 37 1>, - <&pmx_core 19 36 1>, - <&pmx_core 20 35 1>, - <&pmx_core 21 34 1>, - <&pmx_core 22 33 1>, - <&pmx_core 23 32 1>, - <&pmx_core 24 24 1>, - <&pmx_core 25 22 1>, - <&pmx_core 26 21 1>, - <&pmx_core 27 20 1>, - <&pmx_core 28 19 1>, - <&pmx_core 29 18 1>, - <&pmx_core 30 17 1>, - <&pmx_core 31 16 1>, - <&pmx_core 32 55 1>, - <&pmx_core 33 54 1>, - <&pmx_core 34 53 1>, - <&pmx_core 35 52 1>, - <&pmx_core 36 51 1>, - <&pmx_core 37 50 1>, - <&pmx_core 38 49 1>, - <&pmx_core 39 48 1>, - <&pmx_core 40 47 1>, - <&pmx_core 41 46 1>, - <&pmx_core 42 45 1>, - <&pmx_core 43 44 1>, - <&pmx_core 44 43 1>, - <&pmx_core 45 42 1>, - <&pmx_core 46 41 1>, - <&pmx_core 47 40 1>, - <&pmx_core 48 71 1>, - <&pmx_core 49 70 1>, - <&pmx_core 50 69 1>, - <&pmx_core 51 68 1>, - <&pmx_core 52 67 1>, - <&pmx_core 53 66 1>, - <&pmx_core 54 65 1>, - <&pmx_core 55 64 1>, - <&pmx_core 56 63 1>, - <&pmx_core 57 62 1>, - <&pmx_core 58 61 1>, - <&pmx_core 59 60 1>, - <&pmx_core 60 59 1>, - <&pmx_core 61 58 1>, - <&pmx_core 62 57 1>, - <&pmx_core 63 56 1>, - <&pmx_core 64 87 1>, - <&pmx_core 65 86 1>, - <&pmx_core 66 85 1>, - <&pmx_core 67 84 1>, - <&pmx_core 68 83 1>, - <&pmx_core 69 82 1>, - <&pmx_core 70 81 1>, - <&pmx_core 71 80 1>, - <&pmx_core 72 70 1>, - <&pmx_core 73 78 1>, - <&pmx_core 74 77 1>, - <&pmx_core 75 76 1>, - <&pmx_core 76 75 1>, - <&pmx_core 77 74 1>, - <&pmx_core 78 73 1>, - <&pmx_core 79 72 1>, - <&pmx_core 80 103 1>, - <&pmx_core 81 102 1>, - <&pmx_core 82 101 1>, - <&pmx_core 83 100 1>, - <&pmx_core 84 99 1>, - <&pmx_core 85 98 1>, - <&pmx_core 86 97 1>, - <&pmx_core 87 96 1>, - <&pmx_core 88 95 1>, - <&pmx_core 89 94 1>, - <&pmx_core 90 93 1>, - <&pmx_core 91 92 1>, - <&pmx_core 92 91 1>, - <&pmx_core 93 90 1>, - <&pmx_core 94 89 1>, - <&pmx_core 95 88 1>, - <&pmx_core 96 158 1>, - <&pmx_core 97 157 1>, - <&pmx_core 98 156 1>, - <&pmx_core 99 155 1>, - <&pmx_core 100 154 1>, - <&pmx_core 101 129 1>, - <&pmx_core 102 113 1>, - <&pmx_core 103 112 1>, - <&pmx_core 104 111 1>, - <&pmx_core 105 110 1>, - <&pmx_core 106 109 1>, - <&pmx_core 107 108 1>, - <&pmx_core 108 107 1>, - <&pmx_core 109 106 1>, - <&pmx_core 110 105 1>, - <&pmx_core 111 104 1>, - <&pmx_core 112 145 1>, - <&pmx_core 113 144 1>, - <&pmx_core 114 143 1>, - <&pmx_core 115 142 1>, - <&pmx_core 116 141 1>, - <&pmx_core 117 140 1>, - <&pmx_core 118 139 1>, - <&pmx_core 119 138 1>, - <&pmx_core 120 137 1>, - <&pmx_core 121 136 1>, - <&pmx_core 122 135 1>, - <&pmx_core 123 134 1>, - <&pmx_core 124 133 1>, - <&pmx_core 125 132 1>, - <&pmx_core 126 131 1>, - <&pmx_core 127 130 1>, - <&pmx_core 128 159 1>, - <&pmx_core 129 31 1>, - <&pmx_core 130 30 1>, - <&pmx_core 131 20 1>, - <&pmx_core 132 28 1>, - <&pmx_core 133 27 1>, - <&pmx_core 134 26 1>, - <&pmx_core 135 23 1>, - <&pmx_core 136 153 1>, - <&pmx_core 137 152 1>, - <&pmx_core 138 151 1>, - <&pmx_core 139 150 1>, - <&pmx_core 140 149 1>, - <&pmx_core 141 148 1>, - <&pmx_core 142 147 1>, - <&pmx_core 143 146 1>; - }; - psc1: clock-controller@227000 { - compatible = "ti,da850-psc1"; - reg = <0x227000 0x1000>; - #clock-cells = <1>; - #power-domain-cells = <1>; - clocks = <&pll0_sysclk 2>, <&pll0_sysclk 4>, - <&async3_clk>; - clock-names = "pll0_sysclk2", "pll0_sysclk4", "async3"; - assigned-clocks = <&async3_clk>; - assigned-clock-parents = <&pll1_sysclk 2>; - }; - pinconf: pin-controller@22c00c { - compatible = "ti,da850-pupd"; - reg = <0x22c00c 0x8>; - status = "disabled"; - }; - - mcasp0: mcasp@100000 { - compatible = "ti,da830-mcasp-audio"; - reg = <0x100000 0x2000>, - <0x102000 0x400000>; - reg-names = "mpu", "dat"; - interrupts = <54>; - interrupt-names = "common"; - power-domains = <&psc1 7>; - status = "disabled"; - dmas = <&edma0 1 1>, - <&edma0 0 1>; - dma-names = "tx", "rx"; - }; - - lcdc: display@213000 { - compatible = "ti,da850-tilcdc"; - reg = <0x213000 0x1000>; - interrupts = <52>; - max-pixelclock = <37500>; - clocks = <&psc1 16>; - clock-names = "fck"; - power-domains = <&psc1 16>; - status = "disabled"; - }; - }; - aemif: aemif@68000000 { - compatible = "ti,da850-aemif"; - #address-cells = <2>; - #size-cells = <1>; - - reg = <0x68000000 0x00008000>; - ranges = <0 0 0x60000000 0x08000000 - 1 0 0x68000000 0x00008000>; - clocks = <&psc0 3>; - clock-names = "aemif"; - clock-ranges; - status = "disabled"; - }; - memctrl: memory-controller@b0000000 { - compatible = "ti,da850-ddr-controller"; - reg = <0xb0000000 0xe8>; - status = "disabled"; - }; -}; diff --git a/sys/gnu/dts/arm/dm3725.dtsi b/sys/gnu/dts/arm/dm3725.dtsi deleted file mode 100644 index e69de29bb2d..00000000000 diff --git a/sys/gnu/dts/arm/dm8148-evm.dts b/sys/gnu/dts/arm/dm8148-evm.dts deleted file mode 100644 index 91d1018ab75..00000000000 --- a/sys/gnu/dts/arm/dm8148-evm.dts +++ /dev/null @@ -1,155 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/dts-v1/; - -#include "dm814x.dtsi" -#include - -/ { - model = "DM8148 EVM"; - compatible = "ti,dm8148-evm", "ti,dm8148", "ti,dm814"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x40000000>; /* 1 GB */ - }; - - /* MIC94060YC6 controlled by SD1_POW pin */ - vmmcsd_fixed: fixedregulator0 { - compatible = "regulator-fixed"; - regulator-name = "vmmcsd_fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&cpsw_emac0 { - phy-handle = <ðphy0>; - phy-mode = "rgmii-id"; -}; - -&cpsw_emac1 { - phy-handle = <ðphy1>; - phy-mode = "rgmii-id"; -}; - -&davinci_mdio { - ethphy0: ethernet-phy@0 { - reg = <0>; - }; - - ethphy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&gpmc { - ranges = <0 0 0x04000000 0x01000000>; /* CS0: 16MB for NAND */ - - nand@0,0 { - compatible = "ti,omap2-nand"; - reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ - <1 IRQ_TYPE_NONE>; /* termcount */ - linux,mtd-name= "micron,mt29f2g16aadwp"; - #address-cells = <1>; - #size-cells = <1>; - ti,nand-ecc-opt = "bch8"; - nand-bus-width = <16>; - gpmc,device-width = <2>; - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <44>; - gpmc,cs-wr-off-ns = <44>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <34>; - gpmc,adv-wr-off-ns = <44>; - gpmc,we-on-ns = <0>; - gpmc,we-off-ns = <40>; - gpmc,oe-on-ns = <0>; - gpmc,oe-off-ns = <54>; - gpmc,access-ns = <64>; - gpmc,rd-cycle-ns = <82>; - gpmc,wr-cycle-ns = <82>; - gpmc,bus-turnaround-ns = <0>; - gpmc,cycle2cycle-delay-ns = <0>; - gpmc,clk-activation-ns = <0>; - gpmc,wr-access-ns = <40>; - gpmc,wr-data-mux-bus-ns = <0>; - partition@0 { - label = "X-Loader"; - reg = <0 0x80000>; - }; - partition@0x80000 { - label = "U-Boot"; - reg = <0x80000 0x1c0000>; - }; - partition@0x1c0000 { - label = "Environment"; - reg = <0x240000 0x40000>; - }; - partition@0x280000 { - label = "Kernel"; - reg = <0x280000 0x500000>; - }; - partition@0x780000 { - label = "Filesystem"; - reg = <0x780000 0xf880000>; - }; - }; -}; - -&mmc1 { - status = "disabled"; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&sd1_pins>; - vmmc-supply = <&vmmcsd_fixed>; - bus-width = <4>; - cd-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>; -}; - -&mmc3 { - status = "disabled"; -}; - -&pincntl { - sd1_pins: pinmux_sd1_pins { - pinctrl-single,pins = < - DM814X_IOPAD(0x0800, PIN_INPUT | 0x1) /* SD1_CLK */ - DM814X_IOPAD(0x0804, PIN_INPUT_PULLUP | 0x1) /* SD1_CMD */ - DM814X_IOPAD(0x0808, PIN_INPUT_PULLUP | 0x1) /* SD1_DAT[0] */ - DM814X_IOPAD(0x080c, PIN_INPUT_PULLUP | 0x1) /* SD1_DAT[1] */ - DM814X_IOPAD(0x0810, PIN_INPUT_PULLUP | 0x1) /* SD1_DAT[2] */ - DM814X_IOPAD(0x0814, PIN_INPUT_PULLUP | 0x1) /* SD1_DAT[3] */ - DM814X_IOPAD(0x0924, PIN_OUTPUT | 0x40) /* SD1_POW */ - DM814X_IOPAD(0x093C, PIN_INPUT_PULLUP | 0x80) /* GP1[6] */ - >; - }; - - usb0_pins: pinmux_usb0_pins { - pinctrl-single,pins = < - DM814X_IOPAD(0x0c34, PIN_OUTPUT | 0x1) /* USB0_DRVVBUS */ - >; - }; - - usb1_pins: pinmux_usb1_pins { - pinctrl-single,pins = < - DM814X_IOPAD(0x0834, PIN_OUTPUT | 0x80) /* USB1_DRVVBUS */ - >; - }; -}; - -&usb0 { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_pins>; - dr_mode = "host"; -}; - -&usb1 { - pinctrl-names = "default"; - pinctrl-0 = <&usb1_pins>; - dr_mode = "host"; -}; diff --git a/sys/gnu/dts/arm/dm8148-t410.dts b/sys/gnu/dts/arm/dm8148-t410.dts deleted file mode 100644 index 79ccdd4470f..00000000000 --- a/sys/gnu/dts/arm/dm8148-t410.dts +++ /dev/null @@ -1,113 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/dts-v1/; - -#include "dm814x.dtsi" - -/ { - model = "HP t410 Smart Zero Client"; - compatible = "hp,t410", "ti,dm8148", "ti,dm814"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x40000000>; /* 1 GB */ - }; - - /* gpio9 seems to control USB VBUS regulator and/or hub power */ - usb_power: regulator@9 { - compatible = "regulator-fixed"; - regulator-name = "usb_power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - }; - - vmmcsd_fixed: fixedregulator0 { - compatible = "regulator-fixed"; - regulator-name = "vmmcsd_fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&cpsw_emac0 { - phy-handle = <ðphy0>; - phy-mode = "rgmii-id"; -}; - -&cpsw_emac1 { - phy-handle = <ðphy1>; - phy-mode = "rgmii-id"; -}; - -&davinci_mdio { - ethphy0: ethernet-phy@0 { - reg = <0>; - }; - - ethphy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&mmc1 { - status = "disabled"; -}; - -&mmc2 { - status = "disabled"; -}; - -&mmc3 { - pinctrl-names = "default"; - pinctrl-0 = <&sd2_pins>; - vmmc-supply = <&vmmcsd_fixed>; - bus-width = <8>; - dmas = <&edma_xbar 8 0 1 /* use SDTXEVT1 instead of MCASP0TX */ - &edma_xbar 9 0 2>; /* use SDRXEVT1 instead of MCASP0RX */ - dma-names = "tx", "rx"; - non-removable; -}; - -&pincntl { - sd2_pins: pinmux_sd2_pins { - pinctrl-single,pins = < - DM814X_IOPAD(0x09c0, PIN_INPUT_PULLUP | 0x1) /* SD2_DAT[7] */ - DM814X_IOPAD(0x09c4, PIN_INPUT_PULLUP | 0x1) /* SD2_DAT[6] */ - DM814X_IOPAD(0x09c8, PIN_INPUT_PULLUP | 0x1) /* SD2_DAT[5] */ - DM814X_IOPAD(0x09cc, PIN_INPUT_PULLUP | 0x1) /* SD2_DAT[4] */ - DM814X_IOPAD(0x09d0, PIN_INPUT_PULLUP | 0x1) /* SD2_DAT[3] */ - DM814X_IOPAD(0x09d4, PIN_INPUT_PULLUP | 0x1) /* SD2_DAT[2] */ - DM814X_IOPAD(0x09d8, PIN_INPUT_PULLUP | 0x1) /* SD2_DAT[1] */ - DM814X_IOPAD(0x09dc, PIN_INPUT_PULLUP | 0x1) /* SD2_DAT[0] */ - DM814X_IOPAD(0x09e0, PIN_INPUT | 0x1) /* SD2_CLK */ - DM814X_IOPAD(0x09f4, PIN_INPUT_PULLUP | 0x2) /* SD2_CMD */ - DM814X_IOPAD(0x0920, PIN_INPUT | 0x40) /* SD2_SDCD */ - >; - }; - - usb0_pins: pinmux_usb0_pins { - pinctrl-single,pins = < - DM814X_IOPAD(0x0c34, PIN_OUTPUT | 0x1) /* USB0_DRVVBUS */ - >; - }; - - usb1_pins: pinmux_usb1_pins { - pinctrl-single,pins = < - DM814X_IOPAD(0x0834, PIN_OUTPUT | 0x80) /* USB1_DRVVBUS */ - >; - }; -}; - -&usb0 { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_pins>; - dr_mode = "host"; -}; - -&usb1 { - pinctrl-names = "default"; - pinctrl-0 = <&usb1_pins>; - dr_mode = "host"; -}; diff --git a/sys/gnu/dts/arm/dm814x-clocks.dtsi b/sys/gnu/dts/arm/dm814x-clocks.dtsi deleted file mode 100644 index e5e4d0affef..00000000000 --- a/sys/gnu/dts/arm/dm814x-clocks.dtsi +++ /dev/null @@ -1,365 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only - -&pllss { - /* - * See TRM "2.6.10 Connected outputso DPLLS" and - * "2.6.11 Connected Outputs of DPLLJ". Only clkout is - * connected except for hdmi and usb. - */ - adpll_mpu_ck: adpll@40 { - #clock-cells = <1>; - compatible = "ti,dm814-adpll-s-clock"; - reg = <0x40 0x40>; - clocks = <&devosc_ck &devosc_ck &devosc_ck>; - clock-names = "clkinp", "clkinpulow", "clkinphif"; - clock-output-names = "481c5040.adpll.dcoclkldo", - "481c5040.adpll.clkout", - "481c5040.adpll.clkoutx2", - "481c5040.adpll.clkouthif"; - }; - - adpll_dsp_ck: adpll@80 { - #clock-cells = <1>; - compatible = "ti,dm814-adpll-lj-clock"; - reg = <0x80 0x30>; - clocks = <&devosc_ck &devosc_ck>; - clock-names = "clkinp", "clkinpulow"; - clock-output-names = "481c5080.adpll.dcoclkldo", - "481c5080.adpll.clkout", - "481c5080.adpll.clkoutldo"; - }; - - adpll_sgx_ck: adpll@b0 { - #clock-cells = <1>; - compatible = "ti,dm814-adpll-lj-clock"; - reg = <0xb0 0x30>; - clocks = <&devosc_ck &devosc_ck>; - clock-names = "clkinp", "clkinpulow"; - clock-output-names = "481c50b0.adpll.dcoclkldo", - "481c50b0.adpll.clkout", - "481c50b0.adpll.clkoutldo"; - }; - - adpll_hdvic_ck: adpll@e0 { - #clock-cells = <1>; - compatible = "ti,dm814-adpll-lj-clock"; - reg = <0xe0 0x30>; - clocks = <&devosc_ck &devosc_ck>; - clock-names = "clkinp", "clkinpulow"; - clock-output-names = "481c50e0.adpll.dcoclkldo", - "481c50e0.adpll.clkout", - "481c50e0.adpll.clkoutldo"; - }; - - adpll_l3_ck: adpll@110 { - #clock-cells = <1>; - compatible = "ti,dm814-adpll-lj-clock"; - reg = <0x110 0x30>; - clocks = <&devosc_ck &devosc_ck>; - clock-names = "clkinp", "clkinpulow"; - clock-output-names = "481c5110.adpll.dcoclkldo", - "481c5110.adpll.clkout", - "481c5110.adpll.clkoutldo"; - }; - - adpll_isp_ck: adpll@140 { - #clock-cells = <1>; - compatible = "ti,dm814-adpll-lj-clock"; - reg = <0x140 0x30>; - clocks = <&devosc_ck &devosc_ck>; - clock-names = "clkinp", "clkinpulow"; - clock-output-names = "481c5140.adpll.dcoclkldo", - "481c5140.adpll.clkout", - "481c5140.adpll.clkoutldo"; - }; - - adpll_dss_ck: adpll@170 { - #clock-cells = <1>; - compatible = "ti,dm814-adpll-lj-clock"; - reg = <0x170 0x30>; - clocks = <&devosc_ck &devosc_ck>; - clock-names = "clkinp", "clkinpulow"; - clock-output-names = "481c5170.adpll.dcoclkldo", - "481c5170.adpll.clkout", - "481c5170.adpll.clkoutldo"; - }; - - adpll_video0_ck: adpll@1a0 { - #clock-cells = <1>; - compatible = "ti,dm814-adpll-lj-clock"; - reg = <0x1a0 0x30>; - clocks = <&devosc_ck &devosc_ck>; - clock-names = "clkinp", "clkinpulow"; - clock-output-names = "481c51a0.adpll.dcoclkldo", - "481c51a0.adpll.clkout", - "481c51a0.adpll.clkoutldo"; - }; - - adpll_video1_ck: adpll@1d0 { - #clock-cells = <1>; - compatible = "ti,dm814-adpll-lj-clock"; - reg = <0x1d0 0x30>; - clocks = <&devosc_ck &devosc_ck>; - clock-names = "clkinp", "clkinpulow"; - clock-output-names = "481c51d0.adpll.dcoclkldo", - "481c51d0.adpll.clkout", - "481c51d0.adpll.clkoutldo"; - }; - - adpll_hdmi_ck: adpll@200 { - #clock-cells = <1>; - compatible = "ti,dm814-adpll-lj-clock"; - reg = <0x200 0x30>; - clocks = <&devosc_ck &devosc_ck>; - clock-names = "clkinp", "clkinpulow"; - clock-output-names = "481c5200.adpll.dcoclkldo", - "481c5200.adpll.clkout", - "481c5200.adpll.clkoutldo"; - }; - - adpll_audio_ck: adpll@230 { - #clock-cells = <1>; - compatible = "ti,dm814-adpll-lj-clock"; - reg = <0x230 0x30>; - clocks = <&devosc_ck &devosc_ck>; - clock-names = "clkinp", "clkinpulow"; - clock-output-names = "481c5230.adpll.dcoclkldo", - "481c5230.adpll.clkout", - "481c5230.adpll.clkoutldo"; - }; - - adpll_usb_ck: adpll@260 { - #clock-cells = <1>; - compatible = "ti,dm814-adpll-lj-clock"; - reg = <0x260 0x30>; - clocks = <&devosc_ck &devosc_ck>; - clock-names = "clkinp", "clkinpulow"; - clock-output-names = "481c5260.adpll.dcoclkldo", - "481c5260.adpll.clkout", - "481c5260.adpll.clkoutldo"; - }; - - adpll_ddr_ck: adpll@290 { - #clock-cells = <1>; - compatible = "ti,dm814-adpll-lj-clock"; - reg = <0x290 0x30>; - clocks = <&devosc_ck &devosc_ck>; - clock-names = "clkinp", "clkinpulow"; - clock-output-names = "481c5290.adpll.dcoclkldo", - "481c5290.adpll.clkout", - "481c5290.adpll.clkoutldo"; - }; -}; - -&pllss_clocks { - timer1_fck: timer1_fck@2e0 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sysclk18_ck &aud_clkin0_ck &aud_clkin1_ck - &aud_clkin2_ck &devosc_ck &auxosc_ck &tclkin_ck>; - ti,bit-shift = <3>; - reg = <0x2e0>; - }; - - timer2_fck: timer2_fck@2e0 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sysclk18_ck &aud_clkin0_ck &aud_clkin1_ck - &aud_clkin2_ck &devosc_ck &auxosc_ck &tclkin_ck>; - ti,bit-shift = <6>; - reg = <0x2e0>; - }; - - /* CPTS_RFT_CLK in RMII_REFCLK_SRC, usually sourced from auiod */ - cpsw_cpts_rft_clk: cpsw_cpts_rft_clk { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&adpll_video0_ck 1 - &adpll_video1_ck 1 - &adpll_audio_ck 1>; - ti,bit-shift = <1>; - reg = <0x2e8>; - }; - - /* REVISIT: Set up with a proper mux using RMII_REFCLK_SRC */ - cpsw_125mhz_gclk: cpsw_125mhz_gclk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <125000000>; - }; - - sysclk18_ck: sysclk18_ck@2f0 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&rtcosc_ck>, <&rtcdivider_ck>; - ti,bit-shift = <0>; - reg = <0x02f0>; - }; -}; - -&scm_clocks { - devosc_ck: devosc_ck@40 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&virt_20000000_ck>, <&virt_19200000_ck>; - ti,bit-shift = <21>; - reg = <0x0040>; - }; - - /* Optional auxosc, 20 - 30 MHz range, assume 22.5729 MHz by default */ - auxosc_ck: auxosc_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <22572900>; - }; - - /* Optional 32768Hz crystal or clock on RTCOSC pins */ - rtcosc_ck: rtcosc_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - /* Optional external clock on TCLKIN pin, set rate in baord dts file */ - tclkin_ck: tclkin_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - virt_20000000_ck: virt_20000000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <20000000>; - }; - - virt_19200000_ck: virt_19200000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <19200000>; - }; - - mpu_ck: mpu_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <1000000000>; - }; -}; - -&prcm_clocks { - osc_src_ck: osc_src_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&devosc_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - mpu_clksrc_ck: mpu_clksrc_ck@40 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&devosc_ck>, <&rtcdivider_ck>; - ti,bit-shift = <0>; - reg = <0x0040>; - }; - - /* Fixed divider clock 0.0016384 * devosc */ - rtcdivider_ck: rtcdivider_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&devosc_ck>; - clock-mult = <128>; - clock-div = <78125>; - }; - - /* L4_HS 220 MHz*/ - sysclk4_ck: sysclk4_ck { - #clock-cells = <0>; - compatible = "ti,fixed-factor-clock"; - clocks = <&adpll_l3_ck 1>; - ti,clock-mult = <1>; - ti,clock-div = <1>; - }; - - /* L4_FWCFG */ - sysclk5_ck: sysclk5_ck { - #clock-cells = <0>; - compatible = "ti,fixed-factor-clock"; - clocks = <&adpll_l3_ck 1>; - ti,clock-mult = <1>; - ti,clock-div = <2>; - }; - - /* L4_LS 110 MHz */ - sysclk6_ck: sysclk6_ck { - #clock-cells = <0>; - compatible = "ti,fixed-factor-clock"; - clocks = <&adpll_l3_ck 1>; - ti,clock-mult = <1>; - ti,clock-div = <2>; - }; - - sysclk8_ck: sysclk8_ck { - #clock-cells = <0>; - compatible = "ti,fixed-factor-clock"; - clocks = <&adpll_usb_ck 1>; - ti,clock-mult = <1>; - ti,clock-div = <1>; - }; - - sysclk10_ck: sysclk10_ck { - compatible = "ti,divider-clock"; - reg = <0x324>; - ti,max-div = <7>; - #clock-cells = <0>; - clocks = <&adpll_usb_ck 1>; - }; - - aud_clkin0_ck: aud_clkin0_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <20000000>; - }; - - aud_clkin1_ck: aud_clkin1_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <20000000>; - }; - - aud_clkin2_ck: aud_clkin2_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <20000000>; - }; -}; - -&prcm { - default_cm: default_cm@500 { - compatible = "ti,omap4-cm"; - reg = <0x500 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x500 0x100>; - - default_clkctrl: clk@0 { - compatible = "ti,clkctrl"; - reg = <0x0 0x5c>; - #clock-cells = <2>; - }; - }; - - alwon_cm: alwon_cm@1400 { - compatible = "ti,omap4-cm"; - reg = <0x1400 0x300>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1400 0x300>; - - alwon_clkctrl: clk@0 { - compatible = "ti,clkctrl"; - reg = <0x0 0x228>; - #clock-cells = <2>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/dm814x.dtsi b/sys/gnu/dts/arm/dm814x.dtsi deleted file mode 100644 index 95de9f214c1..00000000000 --- a/sys/gnu/dts/arm/dm814x.dtsi +++ /dev/null @@ -1,649 +0,0 @@ -/* - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -#include -#include - -/ { - compatible = "ti,dm814"; - interrupt-parent = <&intc>; - #address-cells = <1>; - #size-cells = <1>; - chosen { }; - - aliases { - i2c0 = &i2c1; - i2c1 = &i2c2; - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - ethernet0 = &cpsw_emac0; - ethernet1 = &cpsw_emac1; - usb0 = &usb0; - usb1 = &usb1; - phy0 = &usb0_phy; - phy1 = &usb1_phy; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu@0 { - compatible = "arm,cortex-a8"; - device_type = "cpu"; - reg = <0>; - }; - }; - - pmu { - compatible = "arm,cortex-a8-pmu"; - interrupts = <3>; - }; - - /* - * The soc node represents the soc top level view. It is used for IPs - * that are not memory mapped in the MPU view or for the MPU itself. - */ - soc { - compatible = "ti,omap-infra"; - mpu { - compatible = "ti,omap3-mpu"; - ti,hwmods = "mpu"; - }; - }; - - ocp { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - ti,hwmods = "l3_main"; - - usb: usb@47400000 { - compatible = "ti,am33xx-usb"; - reg = <0x47400000 0x1000>; - ranges; - #address-cells = <1>; - #size-cells = <1>; - ti,hwmods = "usb_otg_hs"; - - usb0_phy: usb-phy@47401300 { - compatible = "ti,am335x-usb-phy"; - reg = <0x47401300 0x100>; - reg-names = "phy"; - ti,ctrl_mod = <&usb_ctrl_mod>; - #phy-cells = <0>; - }; - - usb0: usb@47401000 { - compatible = "ti,musb-am33xx"; - reg = <0x47401400 0x400 - 0x47401000 0x200>; - reg-names = "mc", "control"; - - interrupts = <18>; - interrupt-names = "mc"; - dr_mode = "otg"; - mentor,multipoint = <1>; - mentor,num-eps = <16>; - mentor,ram-bits = <12>; - mentor,power = <500>; - phys = <&usb0_phy>; - - dmas = <&cppi41dma 0 0 &cppi41dma 1 0 - &cppi41dma 2 0 &cppi41dma 3 0 - &cppi41dma 4 0 &cppi41dma 5 0 - &cppi41dma 6 0 &cppi41dma 7 0 - &cppi41dma 8 0 &cppi41dma 9 0 - &cppi41dma 10 0 &cppi41dma 11 0 - &cppi41dma 12 0 &cppi41dma 13 0 - &cppi41dma 14 0 &cppi41dma 0 1 - &cppi41dma 1 1 &cppi41dma 2 1 - &cppi41dma 3 1 &cppi41dma 4 1 - &cppi41dma 5 1 &cppi41dma 6 1 - &cppi41dma 7 1 &cppi41dma 8 1 - &cppi41dma 9 1 &cppi41dma 10 1 - &cppi41dma 11 1 &cppi41dma 12 1 - &cppi41dma 13 1 &cppi41dma 14 1>; - dma-names = - "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7", - "rx8", "rx9", "rx10", "rx11", "rx12", "rx13", - "rx14", "rx15", - "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7", - "tx8", "tx9", "tx10", "tx11", "tx12", "tx13", - "tx14", "tx15"; - }; - - usb1: usb@47401800 { - compatible = "ti,musb-am33xx"; - reg = <0x47401c00 0x400 - 0x47401800 0x200>; - reg-names = "mc", "control"; - interrupts = <19>; - interrupt-names = "mc"; - dr_mode = "otg"; - mentor,multipoint = <1>; - mentor,num-eps = <16>; - mentor,ram-bits = <12>; - mentor,power = <500>; - phys = <&usb1_phy>; - - dmas = <&cppi41dma 15 0 &cppi41dma 16 0 - &cppi41dma 17 0 &cppi41dma 18 0 - &cppi41dma 19 0 &cppi41dma 20 0 - &cppi41dma 21 0 &cppi41dma 22 0 - &cppi41dma 23 0 &cppi41dma 24 0 - &cppi41dma 25 0 &cppi41dma 26 0 - &cppi41dma 27 0 &cppi41dma 28 0 - &cppi41dma 29 0 &cppi41dma 15 1 - &cppi41dma 16 1 &cppi41dma 17 1 - &cppi41dma 18 1 &cppi41dma 19 1 - &cppi41dma 20 1 &cppi41dma 21 1 - &cppi41dma 22 1 &cppi41dma 23 1 - &cppi41dma 24 1 &cppi41dma 25 1 - &cppi41dma 26 1 &cppi41dma 27 1 - &cppi41dma 28 1 &cppi41dma 29 1>; - dma-names = - "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7", - "rx8", "rx9", "rx10", "rx11", "rx12", "rx13", - "rx14", "rx15", - "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7", - "tx8", "tx9", "tx10", "tx11", "tx12", "tx13", - "tx14", "tx15"; - }; - - cppi41dma: dma-controller@47402000 { - compatible = "ti,am3359-cppi41"; - reg = <0x47400000 0x1000 - 0x47402000 0x1000 - 0x47403000 0x1000 - 0x47404000 0x4000>; - reg-names = "glue", "controller", "scheduler", "queuemgr"; - interrupts = <17>; - interrupt-names = "glue"; - #dma-cells = <2>; - #dma-channels = <30>; - #dma-requests = <256>; - }; - }; - - /* - * See TRM "Table 1-317. L4LS Instance Summary" for hints. - * It shows the module target agent registers though, so the - * actual device is typically 0x1000 before the target agent - * except in cases where the module is larger than 0x1000. - */ - l4ls: l4ls@48000000 { - compatible = "ti,dm814-l4ls", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x48000000 0x2000000>; - - i2c1: i2c@28000 { - compatible = "ti,omap4-i2c"; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "i2c1"; - reg = <0x28000 0x1000>; - interrupts = <70>; - }; - - elm: elm@80000 { - compatible = "ti,814-elm"; - ti,hwmods = "elm"; - reg = <0x80000 0x2000>; - interrupts = <4>; - }; - - gpio1: gpio@32000 { - compatible = "ti,omap4-gpio"; - ti,hwmods = "gpio1"; - ti,gpio-always-on; - reg = <0x32000 0x2000>; - interrupts = <96>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@4c000 { - compatible = "ti,omap4-gpio"; - ti,hwmods = "gpio2"; - ti,gpio-always-on; - reg = <0x4c000 0x2000>; - interrupts = <98>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio@1ac000 { - compatible = "ti,omap4-gpio"; - ti,hwmods = "gpio3"; - ti,gpio-always-on; - reg = <0x1ac000 0x2000>; - interrupts = <32>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio4: gpio@1ae000 { - compatible = "ti,omap4-gpio"; - ti,hwmods = "gpio4"; - ti,gpio-always-on; - reg = <0x1ae000 0x2000>; - interrupts = <62>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - i2c2: i2c@2a000 { - compatible = "ti,omap4-i2c"; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "i2c2"; - reg = <0x2a000 0x1000>; - interrupts = <71>; - }; - - mcspi1: spi@30000 { - compatible = "ti,omap4-mcspi"; - reg = <0x30000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <65>; - ti,spi-num-cs = <4>; - ti,hwmods = "mcspi1"; - dmas = <&edma 16 0 &edma 17 0 - &edma 18 0 &edma 19 0 - &edma 20 0 &edma 21 0 - &edma 22 0 &edma 23 0>; - - dma-names = "tx0", "rx0", "tx1", "rx1", - "tx2", "rx2", "tx3", "rx3"; - }; - - mcspi2: spi@1a0000 { - compatible = "ti,omap4-mcspi"; - reg = <0x1a0000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <125>; - ti,spi-num-cs = <4>; - ti,hwmods = "mcspi2"; - dmas = <&edma 42 0 &edma 43 0 - &edma 44 0 &edma 45 0>; - dma-names = "tx0", "rx0", "tx1", "rx1"; - }; - - /* Board must configure dmas with edma_xbar for EDMA */ - mcspi3: spi@1a2000 { - compatible = "ti,omap4-mcspi"; - reg = <0x1a2000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <126>; - ti,spi-num-cs = <4>; - ti,hwmods = "mcspi3"; - }; - - mcspi4: spi@1a4000 { - compatible = "ti,omap4-mcspi"; - reg = <0x1a4000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <127>; - ti,spi-num-cs = <4>; - ti,hwmods = "mcspi4"; - }; - - timer1: timer@2e000 { - compatible = "ti,dm814-timer"; - reg = <0x2e000 0x2000>; - interrupts = <67>; - ti,hwmods = "timer1"; - ti,timer-alwon; - clocks = <&timer1_fck>; - clock-names = "fck"; - }; - - uart1: uart@20000 { - compatible = "ti,am3352-uart", "ti,omap3-uart"; - ti,hwmods = "uart1"; - reg = <0x20000 0x2000>; - clock-frequency = <48000000>; - interrupts = <72>; - dmas = <&edma 26 0 &edma 27 0>; - dma-names = "tx", "rx"; - }; - - uart2: uart@22000 { - compatible = "ti,am3352-uart", "ti,omap3-uart"; - ti,hwmods = "uart2"; - reg = <0x22000 0x2000>; - clock-frequency = <48000000>; - interrupts = <73>; - dmas = <&edma 28 0 &edma 29 0>; - dma-names = "tx", "rx"; - }; - - uart3: uart@24000 { - compatible = "ti,am3352-uart", "ti,omap3-uart"; - ti,hwmods = "uart3"; - reg = <0x24000 0x2000>; - clock-frequency = <48000000>; - interrupts = <74>; - dmas = <&edma 30 0 &edma 31 0>; - dma-names = "tx", "rx"; - }; - - timer2: timer@40000 { - compatible = "ti,dm814-timer"; - reg = <0x40000 0x2000>; - interrupts = <68>; - ti,hwmods = "timer2"; - clocks = <&timer2_fck>; - clock-names = "fck"; - }; - - timer3: timer@42000 { - compatible = "ti,dm814-timer"; - reg = <0x42000 0x2000>; - interrupts = <69>; - ti,hwmods = "timer3"; - }; - - mmc1: mmc@60000 { - compatible = "ti,omap4-hsmmc"; - ti,hwmods = "mmc1"; - dmas = <&edma 24 0 - &edma 25 0>; - dma-names = "tx", "rx"; - interrupts = <64>; - interrupt-parent = <&intc>; - reg = <0x60000 0x1000>; - }; - - rtc: rtc@c0000 { - compatible = "ti,am3352-rtc", "ti,da830-rtc"; - reg = <0xc0000 0x1000>; - interrupts = <75 76>; - ti,hwmods = "rtc"; - }; - - mmc2: mmc@1d8000 { - compatible = "ti,omap4-hsmmc"; - ti,hwmods = "mmc2"; - dmas = <&edma 2 0 - &edma 3 0>; - dma-names = "tx", "rx"; - interrupts = <28>; - interrupt-parent = <&intc>; - reg = <0x1d8000 0x1000>; - }; - - control: control@140000 { - compatible = "ti,dm814-scm", "simple-bus"; - reg = <0x140000 0x20000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x140000 0x20000>; - - scm_conf: scm_conf@0 { - compatible = "syscon", "simple-bus"; - reg = <0x0 0x800>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x800>; - - phy_gmii_sel: phy-gmii-sel { - compatible = "ti,dm814-phy-gmii-sel"; - reg = <0x650 0x4>; - #phy-cells = <1>; - }; - - scm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - scm_clockdomains: clockdomains { - }; - }; - - usb_ctrl_mod: control@620 { - compatible = "ti,am335x-usb-ctrl-module"; - reg = <0x620 0x10 - 0x648 0x4>; - reg-names = "phy_ctrl", "wakeup"; - }; - - edma_xbar: dma-router@f90 { - compatible = "ti,am335x-edma-crossbar"; - reg = <0xf90 0x40>; - #dma-cells = <3>; - dma-requests = <32>; - dma-masters = <&edma>; - }; - - /* - * Note that silicon revision 2.1 and older - * require input enabled (bit 18 set) for all - * 3.3V I/Os to avoid cumulative hardware damage. - * For more info, see errata advisory 2.1.87. - * We leave bit 18 out of function-mask and rely - * on the bootloader for it. - */ - pincntl: pinmux@800 { - compatible = "pinctrl-single"; - reg = <0x800 0x438>; - #address-cells = <1>; - #size-cells = <0>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0x307ff>; - }; - - usb1_phy: usb-phy@1b00 { - compatible = "ti,am335x-usb-phy"; - reg = <0x1b00 0x100>; - reg-names = "phy"; - ti,ctrl_mod = <&usb_ctrl_mod>; - #phy-cells = <0>; - }; - }; - - prcm: prcm@180000 { - compatible = "ti,dm814-prcm", "simple-bus"; - reg = <0x180000 0x2000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x180000 0x2000>; - - prcm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - prcm_clockdomains: clockdomains { - }; - }; - - /* See TRM PLL_SUBSYS_BASE and "PLLSS Registers" */ - pllss: pllss@1c5000 { - compatible = "ti,dm814-pllss", "simple-bus"; - reg = <0x1c5000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1c5000 0x1000>; - - pllss_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - pllss_clockdomains: clockdomains { - }; - }; - - wdt1: wdt@1c7000 { - compatible = "ti,omap3-wdt"; - ti,hwmods = "wd_timer"; - reg = <0x1c7000 0x1000>; - interrupts = <91>; - }; - }; - - intc: interrupt-controller@48200000 { - compatible = "ti,dm814-intc"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x48200000 0x1000>; - }; - - /* Board must configure evtmux with edma_xbar for EDMA */ - mmc3: mmc@47810000 { - compatible = "ti,omap4-hsmmc"; - ti,hwmods = "mmc3"; - interrupts = <29>; - interrupt-parent = <&intc>; - reg = <0x47810000 0x1000>; - }; - - edma: edma@49000000 { - compatible = "ti,edma3-tpcc"; - ti,hwmods = "tpcc"; - reg = <0x49000000 0x10000>; - reg-names = "edma3_cc"; - interrupts = <12 13 14>; - interrupt-names = "edma3_ccint", "edma3_mperr", - "edma3_ccerrint"; - dma-requests = <64>; - #dma-cells = <2>; - - ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>, - <&edma_tptc2 3>, <&edma_tptc3 0>; - - ti,edma-memcpy-channels = <20 21>; - }; - - edma_tptc0: tptc@49800000 { - compatible = "ti,edma3-tptc"; - ti,hwmods = "tptc0"; - reg = <0x49800000 0x100000>; - interrupts = <112>; - interrupt-names = "edma3_tcerrint"; - }; - - edma_tptc1: tptc@49900000 { - compatible = "ti,edma3-tptc"; - ti,hwmods = "tptc1"; - reg = <0x49900000 0x100000>; - interrupts = <113>; - interrupt-names = "edma3_tcerrint"; - }; - - edma_tptc2: tptc@49a00000 { - compatible = "ti,edma3-tptc"; - ti,hwmods = "tptc2"; - reg = <0x49a00000 0x100000>; - interrupts = <114>; - interrupt-names = "edma3_tcerrint"; - }; - - edma_tptc3: tptc@49b00000 { - compatible = "ti,edma3-tptc"; - ti,hwmods = "tptc3"; - reg = <0x49b00000 0x100000>; - interrupts = <115>; - interrupt-names = "edma3_tcerrint"; - }; - - /* See TRM "Table 1-318. L4HS Instance Summary" */ - l4hs: l4hs@4a000000 { - compatible = "ti,dm814-l4hs", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x4a000000 0x1b4040>; - }; - - /* REVISIT: Move to live under l4hs once driver is fixed */ - mac: ethernet@4a100000 { - compatible = "ti,cpsw"; - ti,hwmods = "cpgmac0"; - clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>; - clock-names = "fck", "cpts"; - cpdma_channels = <8>; - ale_entries = <1024>; - bd_ram_size = <0x2000>; - mac_control = <0x20>; - slaves = <2>; - active_slave = <0>; - cpts_clock_mult = <0x80000000>; - cpts_clock_shift = <29>; - reg = <0x4a100000 0x800 - 0x4a100900 0x100>; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&intc>; - /* - * c0_rx_thresh_pend - * c0_rx_pend - * c0_tx_pend - * c0_misc_pend - */ - interrupts = <40 41 42 43>; - ranges; - syscon = <&scm_conf>; - - davinci_mdio: mdio@4a100800 { - compatible = "ti,davinci_mdio"; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "davinci_mdio"; - bus_freq = <1000000>; - reg = <0x4a100800 0x100>; - }; - - cpsw_emac0: slave@4a100200 { - /* Filled in by U-Boot */ - mac-address = [ 00 00 00 00 00 00 ]; - phys = <&phy_gmii_sel 1>; - - }; - - cpsw_emac1: slave@4a100300 { - /* Filled in by U-Boot */ - mac-address = [ 00 00 00 00 00 00 ]; - phys = <&phy_gmii_sel 2>; - }; - }; - - gpmc: gpmc@50000000 { - compatible = "ti,am3352-gpmc"; - ti,hwmods = "gpmc"; - ti,no-idle-on-init; - reg = <0x50000000 0x2000>; - interrupts = <100>; - gpmc,num-cs = <7>; - gpmc,num-waitpins = <2>; - #address-cells = <2>; - #size-cells = <1>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - }; - }; -}; - -#include "dm814x-clocks.dtsi" diff --git a/sys/gnu/dts/arm/dm8168-evm.dts b/sys/gnu/dts/arm/dm8168-evm.dts deleted file mode 100644 index cf05d532db6..00000000000 --- a/sys/gnu/dts/arm/dm8168-evm.dts +++ /dev/null @@ -1,213 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/dts-v1/; - -#include "dm816x.dtsi" -#include - -/ { - model = "DM8168 EVM"; - compatible = "ti,dm8168-evm", "ti,dm8168", "ti,dm816"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x40000000 /* 1 GB */ - 0xc0000000 0x40000000>; /* 1 GB */ - }; - - /* FDC6331L controlled by SD_POW pin */ - vmmcsd_fixed: fixedregulator0 { - compatible = "regulator-fixed"; - regulator-name = "vmmcsd_fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - sata_refclk: fixedclock0 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - }; -}; - -&dm816x_pinmux { - mcspi1_pins: pinmux_mcspi1_pins { - pinctrl-single,pins = < - DM816X_IOPAD(0x0a94, MUX_MODE0) /* SPI_SCLK */ - DM816X_IOPAD(0x0a98, MUX_MODE0) /* SPI_SCS0 */ - DM816X_IOPAD(0x0aa8, MUX_MODE0) /* SPI_D0 */ - DM816X_IOPAD(0x0aac, MUX_MODE0) /* SPI_D1 */ - >; - }; - - mmc_pins: pinmux_mmc_pins { - pinctrl-single,pins = < - DM816X_IOPAD(0x0a70, MUX_MODE0) /* SD_POW */ - DM816X_IOPAD(0x0a74, MUX_MODE0) /* SD_CLK */ - DM816X_IOPAD(0x0a78, MUX_MODE0) /* SD_CMD */ - DM816X_IOPAD(0x0a7C, MUX_MODE0) /* SD_DAT0 */ - DM816X_IOPAD(0x0a80, MUX_MODE0) /* SD_DAT1 */ - DM816X_IOPAD(0x0a84, MUX_MODE0) /* SD_DAT2 */ - DM816X_IOPAD(0x0a88, MUX_MODE0) /* SD_DAT2 */ - DM816X_IOPAD(0x0a8c, MUX_MODE2) /* GP1[7] */ - DM816X_IOPAD(0x0a90, MUX_MODE2) /* GP1[8] */ - >; - }; - - usb0_pins: pinmux_usb0_pins { - pinctrl-single,pins = < - DM816X_IOPAD(0x0d04, MUX_MODE0) /* USB0_DRVVBUS */ - >; - }; - - usb1_pins: pinmux_usb1_pins { - pinctrl-single,pins = < - DM816X_IOPAD(0x0d08, MUX_MODE0) /* USB1_DRVVBUS */ - >; - }; - - nandflash_pins: nandflash_pins { - pinctrl-single,pins = < - DM816X_IOPAD(0x0b38, PULL_UP | MUX_MODE0) /* PINCTRL207 GPMC_CS0*/ - DM816X_IOPAD(0x0b60, PULL_ENA | MUX_MODE0) /* PINCTRL217 GPMC_ADV_ALE */ - DM816X_IOPAD(0x0b54, PULL_UP | PULL_ENA | MUX_MODE0) /* PINCTRL214 GPMC_OE_RE */ - DM816X_IOPAD(0x0b58, PULL_ENA | MUX_MODE0) /* PINCTRL215 GPMC_BE0_CLE */ - DM816X_IOPAD(0x0b50, PULL_UP | MUX_MODE0) /* PINCTRL213 GPMC_WE */ - DM816X_IOPAD(0x0b6c, MUX_MODE0) /* PINCTRL220 GPMC_WAIT */ - DM816X_IOPAD(0x0be4, PULL_ENA | MUX_MODE0) /* PINCTRL250 GPMC_CLK */ - DM816X_IOPAD(0x0ba4, MUX_MODE0) /* PINCTRL234 GPMC_D0 */ - DM816X_IOPAD(0x0ba8, MUX_MODE0) /* PINCTRL234 GPMC_D1 */ - DM816X_IOPAD(0x0bac, MUX_MODE0) /* PINCTRL234 GPMC_D2 */ - DM816X_IOPAD(0x0bb0, MUX_MODE0) /* PINCTRL234 GPMC_D3 */ - DM816X_IOPAD(0x0bb4, MUX_MODE0) /* PINCTRL234 GPMC_D4 */ - DM816X_IOPAD(0x0bb8, MUX_MODE0) /* PINCTRL234 GPMC_D5 */ - DM816X_IOPAD(0x0bbc, MUX_MODE0) /* PINCTRL234 GPMC_D6 */ - DM816X_IOPAD(0x0bc0, MUX_MODE0) /* PINCTRL234 GPMC_D7 */ - DM816X_IOPAD(0x0bc4, MUX_MODE0) /* PINCTRL234 GPMC_D8 */ - DM816X_IOPAD(0x0bc8, MUX_MODE0) /* PINCTRL234 GPMC_D9 */ - DM816X_IOPAD(0x0bcc, MUX_MODE0) /* PINCTRL234 GPMC_D10 */ - DM816X_IOPAD(0x0bd0, MUX_MODE0) /* PINCTRL234 GPMC_D11 */ - DM816X_IOPAD(0x0bd4, MUX_MODE0) /* PINCTRL234 GPMC_D12 */ - DM816X_IOPAD(0x0bd8, MUX_MODE0) /* PINCTRL234 GPMC_D13 */ - DM816X_IOPAD(0x0bdc, MUX_MODE0) /* PINCTRL234 GPMC_D14 */ - DM816X_IOPAD(0x0be0, MUX_MODE0) /* PINCTRL234 GPMC_D15 */ - >; - }; -}; - -&i2c1 { - extgpio0: pcf8575@20 { - compatible = "nxp,pcf8575"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -&i2c2 { - extgpio1: pcf8575@20 { - compatible = "nxp,pcf8575"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -&gpmc { - ranges = <0 0 0x04000000 0x01000000>; /* CS0: 16MB for NAND */ - pinctrl-names = "default"; - pinctrl-0 = <&nandflash_pins>; - - nand@0,0 { - compatible = "ti,omap2-nand"; - linux,mtd-name= "micron,mt29f2g16aadwp"; - reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ - <1 IRQ_TYPE_NONE>; /* termcount */ - rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ - #address-cells = <1>; - #size-cells = <1>; - ti,nand-ecc-opt = "bch8"; - ti,elm-id = <&elm>; - nand-bus-width = <16>; - gpmc,device-width = <2>; - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <44>; - gpmc,cs-wr-off-ns = <44>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <34>; - gpmc,adv-wr-off-ns = <44>; - gpmc,we-on-ns = <0>; - gpmc,we-off-ns = <40>; - gpmc,oe-on-ns = <0>; - gpmc,oe-off-ns = <54>; - gpmc,access-ns = <64>; - gpmc,rd-cycle-ns = <82>; - gpmc,wr-cycle-ns = <82>; - gpmc,bus-turnaround-ns = <0>; - gpmc,cycle2cycle-delay-ns = <0>; - gpmc,clk-activation-ns = <0>; - gpmc,wr-access-ns = <40>; - gpmc,wr-data-mux-bus-ns = <0>; - partition@0 { - label = "X-Loader"; - reg = <0 0x80000>; - }; - partition@0x80000 { - label = "U-Boot"; - reg = <0x80000 0x1c0000>; - }; - partition@0x1c0000 { - label = "Environment"; - reg = <0x240000 0x40000>; - }; - partition@0x280000 { - label = "Kernel"; - reg = <0x280000 0x500000>; - }; - partition@0x780000 { - label = "Filesystem"; - reg = <0x780000 0xf880000>; - }; - }; -}; - -&mcspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&mcspi1_pins>; - - m25p80@0 { - compatible = "w25x32"; - spi-max-frequency = <48000000>; - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; - }; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc_pins>; - vmmc-supply = <&vmmcsd_fixed>; - bus-width = <4>; - cd-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; -}; - -/* At least dm8168-evm rev c won't support multipoint, later may */ -&usb0 { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_pins>; - mentor,multipoint = <0>; -}; - -&usb1 { - pinctrl-names = "default"; - pinctrl-0 = <&usb1_pins>; - mentor,multipoint = <0>; -}; - -&sata { - clocks = <&sysclk5_ck>, <&sata_refclk>; -}; diff --git a/sys/gnu/dts/arm/dm816x-clocks.dtsi b/sys/gnu/dts/arm/dm816x-clocks.dtsi deleted file mode 100644 index 338449b32a1..00000000000 --- a/sys/gnu/dts/arm/dm816x-clocks.dtsi +++ /dev/null @@ -1,276 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only - -&scrm { - main_fapll: main_fapll { - #clock-cells = <1>; - compatible = "ti,dm816-fapll-clock"; - reg = <0x400 0x40>; - clocks = <&sys_clkin_ck &sys_clkin_ck>; - clock-indices = <1>, <2>, <3>, <4>, <5>, - <6>, <7>; - clock-output-names = "main_pll_clk1", - "main_pll_clk2", - "main_pll_clk3", - "main_pll_clk4", - "main_pll_clk5", - "main_pll_clk6", - "main_pll_clk7"; - }; - - ddr_fapll: ddr_fapll { - #clock-cells = <1>; - compatible = "ti,dm816-fapll-clock"; - reg = <0x440 0x30>; - clocks = <&sys_clkin_ck &sys_clkin_ck>; - clock-indices = <1>, <2>, <3>, <4>; - clock-output-names = "ddr_pll_clk1", - "ddr_pll_clk2", - "ddr_pll_clk3", - "ddr_pll_clk4"; - }; - - video_fapll: video_fapll { - #clock-cells = <1>; - compatible = "ti,dm816-fapll-clock"; - reg = <0x470 0x30>; - clocks = <&sys_clkin_ck &sys_clkin_ck>; - clock-indices = <1>, <2>, <3>; - clock-output-names = "video_pll_clk1", - "video_pll_clk2", - "video_pll_clk3"; - }; - - audio_fapll: audio_fapll { - #clock-cells = <1>; - compatible = "ti,dm816-fapll-clock"; - reg = <0x4a0 0x30>; - clocks = <&main_fapll 7>, < &sys_clkin_ck>; - clock-indices = <1>, <2>, <3>, <4>, <5>; - clock-output-names = "audio_pll_clk1", - "audio_pll_clk2", - "audio_pll_clk3", - "audio_pll_clk4", - "audio_pll_clk5"; - }; -}; - -&scrm_clocks { - secure_32k_ck: secure_32k_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - sys_32k_ck: sys_32k_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - tclkin_ck: tclkin_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - sys_clkin_ck: sys_clkin_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <27000000>; - }; -}; - -/* 0x48180000 */ -&prcm_clocks { - clkout_pre_ck: clkout_pre_ck@100 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&main_fapll 5 &ddr_fapll 1 &video_fapll 1 - &audio_fapll 1>; - reg = <0x100>; - }; - - clkout_div_ck: clkout_div_ck@100 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&clkout_pre_ck>; - ti,bit-shift = <3>; - ti,max-div = <8>; - reg = <0x100>; - }; - - clkout_ck: clkout_ck@100 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&clkout_div_ck>; - ti,bit-shift = <7>; - reg = <0x100>; - }; - - /* CM_DPLL clocks p1795 */ - sysclk1_ck: sysclk1_ck@300 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&main_fapll 1>; - ti,max-div = <7>; - reg = <0x0300>; - }; - - sysclk2_ck: sysclk2_ck@304 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&main_fapll 2>; - ti,max-div = <7>; - reg = <0x0304>; - }; - - sysclk3_ck: sysclk3_ck@308 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&main_fapll 3>; - ti,max-div = <7>; - reg = <0x0308>; - }; - - sysclk4_ck: sysclk4_ck@30c { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&main_fapll 4>; - ti,max-div = <1>; - reg = <0x030c>; - }; - - sysclk5_ck: sysclk5_ck@310 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&sysclk4_ck>; - ti,max-div = <1>; - reg = <0x0310>; - }; - - sysclk6_ck: sysclk6_ck@314 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&main_fapll 4>; - ti,dividers = <2>, <4>; - reg = <0x0314>; - }; - - sysclk10_ck: sysclk10_ck@324 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&ddr_fapll 2>; - ti,max-div = <7>; - reg = <0x0324>; - }; - - sysclk24_ck: sysclk24_ck@3b4 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&main_fapll 5>; - ti,max-div = <7>; - reg = <0x03b4>; - }; - - mpu_ck: mpu_ck@15dc { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sysclk2_ck>; - ti,bit-shift = <1>; - reg = <0x15dc>; - }; - - audio_pll_a_ck: audio_pll_a_ck@35c { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&audio_fapll 1>; - ti,max-div = <7>; - reg = <0x035c>; - }; - - sysclk18_ck: sysclk18_ck@378 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_32k_ck>, <&audio_pll_a_ck>; - reg = <0x0378>; - }; - - timer1_fck: timer1_fck@390 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>; - reg = <0x0390>; - }; - - timer2_fck: timer2_fck@394 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>; - reg = <0x0394>; - }; - - timer3_fck: timer3_fck@398 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>; - reg = <0x0398>; - }; - - timer4_fck: timer4_fck@39c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>; - reg = <0x039c>; - }; - - timer5_fck: timer5_fck@3a0 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>; - reg = <0x03a0>; - }; - - timer6_fck: timer6_fck@3a4 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>; - reg = <0x03a4>; - }; - - timer7_fck: timer7_fck@3a8 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>; - reg = <0x03a8>; - }; -}; - -&prcm { - default_cm: default_cm@500 { - compatible = "ti,omap4-cm"; - reg = <0x500 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x500 0x100>; - - default_clkctrl: clk@0 { - compatible = "ti,clkctrl"; - reg = <0x0 0x5c>; - #clock-cells = <2>; - }; - }; - - alwon_cm: alwon_cm@1400 { - compatible = "ti,omap4-cm"; - reg = <0x1400 0x300>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1400 0x300>; - - alwon_clkctrl: clk@0 { - compatible = "ti,clkctrl"; - reg = <0x0 0x208>; - #clock-cells = <2>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/dm816x.dtsi b/sys/gnu/dts/arm/dm816x.dtsi deleted file mode 100644 index 1edc2b48b25..00000000000 --- a/sys/gnu/dts/arm/dm816x.dtsi +++ /dev/null @@ -1,532 +0,0 @@ -/* - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -#include -#include - -/ { - compatible = "ti,dm816"; - interrupt-parent = <&intc>; - #address-cells = <1>; - #size-cells = <1>; - chosen { }; - - aliases { - i2c0 = &i2c1; - i2c1 = &i2c2; - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - ethernet0 = ð0; - ethernet1 = ð1; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu@0 { - compatible = "arm,cortex-a8"; - device_type = "cpu"; - reg = <0>; - }; - }; - - pmu { - compatible = "arm,cortex-a8-pmu"; - interrupts = <3>; - }; - - /* - * The soc node represents the soc top level view. It is used for IPs - * that are not memory mapped in the MPU view or for the MPU itself. - */ - soc { - compatible = "ti,omap-infra"; - mpu { - compatible = "ti,omap3-mpu"; - ti,hwmods = "mpu"; - }; - }; - - /* - * XXX: Use a flat representation of the dm816x interconnect. - * The real dm816x interconnect network is quite complex. Since - * it will not bring real advantage to represent that in DT - * for the moment, just use a fake OCP bus entry to represent - * the whole bus hierarchy. - */ - ocp { - compatible = "simple-bus"; - reg = <0x44000000 0x10000>; - interrupts = <9 10>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - prcm: prcm@48180000 { - compatible = "ti,dm816-prcm", "simple-bus"; - reg = <0x48180000 0x4000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x48180000 0x4000>; - - prcm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - prcm_clockdomains: clockdomains { - }; - }; - - scrm: scrm@48140000 { - compatible = "ti,dm816-scrm", "simple-bus"; - reg = <0x48140000 0x21000>; - #address-cells = <1>; - #size-cells = <1>; - #pinctrl-cells = <1>; - ranges = <0 0x48140000 0x21000>; - - dm816x_pinmux: pinmux@800 { - compatible = "pinctrl-single"; - reg = <0x800 0x50a>; - #address-cells = <1>; - #size-cells = <0>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <16>; - pinctrl-single,function-mask = <0xf>; - }; - - /* Device Configuration Registers */ - scm_conf: syscon@600 { - compatible = "syscon", "simple-bus"; - reg = <0x600 0x110>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x600 0x110>; - - usb_phy0: usb-phy@20 { - compatible = "ti,dm8168-usb-phy"; - reg = <0x20 0x8>; - reg-names = "phy"; - clocks = <&main_fapll 6>; - clock-names = "refclk"; - #phy-cells = <0>; - syscon = <&scm_conf>; - }; - - usb_phy1: usb-phy@28 { - compatible = "ti,dm8168-usb-phy"; - reg = <0x28 0x8>; - reg-names = "phy"; - clocks = <&main_fapll 6>; - clock-names = "refclk"; - #phy-cells = <0>; - syscon = <&scm_conf>; - }; - }; - - scrm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - scrm_clockdomains: clockdomains { - }; - }; - - edma: edma@49000000 { - compatible = "ti,edma3"; - ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2", "tptc3"; - reg = <0x49000000 0x10000>, - <0x44e10f90 0x40>; - interrupts = <12 13 14>; - #dma-cells = <1>; - }; - - elm: elm@48080000 { - compatible = "ti,am3352-elm"; - ti,hwmods = "elm"; - reg = <0x48080000 0x2000>; - interrupts = <4>; - }; - - gpio1: gpio@48032000 { - compatible = "ti,omap4-gpio"; - ti,hwmods = "gpio1"; - ti,gpio-always-on; - reg = <0x48032000 0x1000>; - interrupts = <96>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@4804c000 { - compatible = "ti,omap4-gpio"; - ti,hwmods = "gpio2"; - ti,gpio-always-on; - reg = <0x4804c000 0x1000>; - interrupts = <98>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpmc: gpmc@50000000 { - compatible = "ti,am3352-gpmc"; - ti,hwmods = "gpmc"; - reg = <0x50000000 0x2000>; - #address-cells = <2>; - #size-cells = <1>; - interrupts = <100>; - dmas = <&edma 52>; - dma-names = "rxtx"; - gpmc,num-cs = <6>; - gpmc,num-waitpins = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - }; - - i2c1: i2c@48028000 { - compatible = "ti,omap4-i2c"; - ti,hwmods = "i2c1"; - reg = <0x48028000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <70>; - dmas = <&edma 58 &edma 59>; - dma-names = "tx", "rx"; - }; - - i2c2: i2c@4802a000 { - compatible = "ti,omap4-i2c"; - ti,hwmods = "i2c2"; - reg = <0x4802a000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <71>; - dmas = <&edma 60 &edma 61>; - dma-names = "tx", "rx"; - }; - - intc: interrupt-controller@48200000 { - compatible = "ti,dm816-intc"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x48200000 0x1000>; - }; - - rtc: rtc@480c0000 { - compatible = "ti,am3352-rtc", "ti,da830-rtc"; - reg = <0x480c0000 0x1000>; - interrupts = <75 76>; - ti,hwmods = "rtc"; - }; - - mailbox: mailbox@480c8000 { - compatible = "ti,omap4-mailbox"; - reg = <0x480c8000 0x2000>; - interrupts = <77>; - ti,hwmods = "mailbox"; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <12>; - mbox_dsp: mbox_dsp { - ti,mbox-tx = <3 0 0>; - ti,mbox-rx = <0 0 0>; - }; - }; - - spinbox: spinbox@480ca000 { - compatible = "ti,omap4-hwspinlock"; - reg = <0x480ca000 0x2000>; - ti,hwmods = "spinbox"; - #hwlock-cells = <1>; - }; - - mdio: mdio@4a100800 { - compatible = "ti,davinci_mdio"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x4a100800 0x100>; - ti,hwmods = "davinci_mdio"; - bus_freq = <1000000>; - phy0: ethernet-phy@0 { - reg = <1>; - }; - phy1: ethernet-phy@1 { - reg = <2>; - }; - }; - - eth0: ethernet@4a100000 { - compatible = "ti,dm816-emac"; - ti,hwmods = "emac0"; - reg = <0x4a100000 0x800 - 0x4a100900 0x3700>; - clocks = <&sysclk24_ck>; - syscon = <&scm_conf>; - ti,davinci-ctrl-reg-offset = <0>; - ti,davinci-ctrl-mod-reg-offset = <0x900>; - ti,davinci-ctrl-ram-offset = <0x2000>; - ti,davinci-ctrl-ram-size = <0x2000>; - interrupts = <40 41 42 43>; - phy-handle = <&phy0>; - }; - - eth1: ethernet@4a120000 { - compatible = "ti,dm816-emac"; - ti,hwmods = "emac1"; - reg = <0x4a120000 0x4000>; - clocks = <&sysclk24_ck>; - syscon = <&scm_conf>; - ti,davinci-ctrl-reg-offset = <0>; - ti,davinci-ctrl-mod-reg-offset = <0x900>; - ti,davinci-ctrl-ram-offset = <0x2000>; - ti,davinci-ctrl-ram-size = <0x2000>; - interrupts = <44 45 46 47>; - phy-handle = <&phy1>; - }; - - sata: sata@4a140000 { - compatible = "ti,dm816-ahci"; - reg = <0x4a140000 0x10000>; - interrupts = <16>; - ti,hwmods = "sata"; - }; - - mcspi1: spi@48030000 { - compatible = "ti,omap4-mcspi"; - reg = <0x48030000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <65>; - ti,spi-num-cs = <4>; - ti,hwmods = "mcspi1"; - dmas = <&edma 16 &edma 17 - &edma 18 &edma 19 - &edma 20 &edma 21 - &edma 22 &edma 23>; - dma-names = "tx0", "rx0", "tx1", "rx1", - "tx2", "rx2", "tx3", "rx3"; - }; - - mmc1: mmc@48060000 { - compatible = "ti,omap4-hsmmc"; - reg = <0x48060000 0x11000>; - ti,hwmods = "mmc1"; - interrupts = <64>; - dmas = <&edma 24 &edma 25>; - dma-names = "tx", "rx"; - }; - - timer1: timer@4802e000 { - compatible = "ti,dm816-timer"; - reg = <0x4802e000 0x2000>; - interrupts = <67>; - ti,hwmods = "timer1"; - ti,timer-alwon; - clocks = <&timer1_fck>; - clock-names = "fck"; - }; - - timer2: timer@48040000 { - compatible = "ti,dm816-timer"; - reg = <0x48040000 0x2000>; - interrupts = <68>; - ti,hwmods = "timer2"; - clocks = <&timer2_fck>; - clock-names = "fck"; - }; - - timer3: timer@48042000 { - compatible = "ti,dm816-timer"; - reg = <0x48042000 0x2000>; - interrupts = <69>; - ti,hwmods = "timer3"; - }; - - timer4: timer@48044000 { - compatible = "ti,dm816-timer"; - reg = <0x48044000 0x2000>; - interrupts = <92>; - ti,hwmods = "timer4"; - ti,timer-pwm; - }; - - timer5: timer@48046000 { - compatible = "ti,dm816-timer"; - reg = <0x48046000 0x2000>; - interrupts = <93>; - ti,hwmods = "timer5"; - ti,timer-pwm; - }; - - timer6: timer@48048000 { - compatible = "ti,dm816-timer"; - reg = <0x48048000 0x2000>; - interrupts = <94>; - ti,hwmods = "timer6"; - ti,timer-pwm; - }; - - timer7: timer@4804a000 { - compatible = "ti,dm816-timer"; - reg = <0x4804a000 0x2000>; - interrupts = <95>; - ti,hwmods = "timer7"; - ti,timer-pwm; - }; - - uart1: uart@48020000 { - compatible = "ti,am3352-uart", "ti,omap3-uart"; - ti,hwmods = "uart1"; - reg = <0x48020000 0x2000>; - clock-frequency = <48000000>; - interrupts = <72>; - dmas = <&edma 26 &edma 27>; - dma-names = "tx", "rx"; - }; - - uart2: uart@48022000 { - compatible = "ti,am3352-uart", "ti,omap3-uart"; - ti,hwmods = "uart2"; - reg = <0x48022000 0x2000>; - clock-frequency = <48000000>; - interrupts = <73>; - dmas = <&edma 28 &edma 29>; - dma-names = "tx", "rx"; - }; - - uart3: uart@48024000 { - compatible = "ti,am3352-uart", "ti,omap3-uart"; - ti,hwmods = "uart3"; - reg = <0x48024000 0x2000>; - clock-frequency = <48000000>; - interrupts = <74>; - dmas = <&edma 30 &edma 31>; - dma-names = "tx", "rx"; - }; - - /* NOTE: USB needs a transceiver driver for phys to work */ - usb: usb_otg_hs@47401000 { - compatible = "ti,am33xx-usb"; - reg = <0x47401000 0x400000>; - ranges; - #address-cells = <1>; - #size-cells = <1>; - ti,hwmods = "usb_otg_hs"; - - usb0: usb@47401000 { - compatible = "ti,musb-dm816"; - reg = <0x47401400 0x400 - 0x47401000 0x200>; - reg-names = "mc", "control"; - interrupts = <18>; - interrupt-names = "mc"; - dr_mode = "host"; - interface-type = <0>; - phys = <&usb_phy0>; - phy-names = "usb2-phy"; - mentor,multipoint = <1>; - mentor,num-eps = <16>; - mentor,ram-bits = <12>; - mentor,power = <500>; - - dmas = <&cppi41dma 0 0 &cppi41dma 1 0 - &cppi41dma 2 0 &cppi41dma 3 0 - &cppi41dma 4 0 &cppi41dma 5 0 - &cppi41dma 6 0 &cppi41dma 7 0 - &cppi41dma 8 0 &cppi41dma 9 0 - &cppi41dma 10 0 &cppi41dma 11 0 - &cppi41dma 12 0 &cppi41dma 13 0 - &cppi41dma 14 0 &cppi41dma 0 1 - &cppi41dma 1 1 &cppi41dma 2 1 - &cppi41dma 3 1 &cppi41dma 4 1 - &cppi41dma 5 1 &cppi41dma 6 1 - &cppi41dma 7 1 &cppi41dma 8 1 - &cppi41dma 9 1 &cppi41dma 10 1 - &cppi41dma 11 1 &cppi41dma 12 1 - &cppi41dma 13 1 &cppi41dma 14 1>; - dma-names = - "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7", - "rx8", "rx9", "rx10", "rx11", "rx12", "rx13", - "rx14", "rx15", - "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7", - "tx8", "tx9", "tx10", "tx11", "tx12", "tx13", - "tx14", "tx15"; - }; - - usb1: usb@47401800 { - compatible = "ti,musb-dm816"; - reg = <0x47401c00 0x400 - 0x47401800 0x200>; - reg-names = "mc", "control"; - interrupts = <19>; - interrupt-names = "mc"; - dr_mode = "host"; - interface-type = <0>; - phys = <&usb_phy1>; - phy-names = "usb2-phy"; - mentor,multipoint = <1>; - mentor,num-eps = <16>; - mentor,ram-bits = <12>; - mentor,power = <500>; - - dmas = <&cppi41dma 15 0 &cppi41dma 16 0 - &cppi41dma 17 0 &cppi41dma 18 0 - &cppi41dma 19 0 &cppi41dma 20 0 - &cppi41dma 21 0 &cppi41dma 22 0 - &cppi41dma 23 0 &cppi41dma 24 0 - &cppi41dma 25 0 &cppi41dma 26 0 - &cppi41dma 27 0 &cppi41dma 28 0 - &cppi41dma 29 0 &cppi41dma 15 1 - &cppi41dma 16 1 &cppi41dma 17 1 - &cppi41dma 18 1 &cppi41dma 19 1 - &cppi41dma 20 1 &cppi41dma 21 1 - &cppi41dma 22 1 &cppi41dma 23 1 - &cppi41dma 24 1 &cppi41dma 25 1 - &cppi41dma 26 1 &cppi41dma 27 1 - &cppi41dma 28 1 &cppi41dma 29 1>; - dma-names = - "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7", - "rx8", "rx9", "rx10", "rx11", "rx12", "rx13", - "rx14", "rx15", - "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7", - "tx8", "tx9", "tx10", "tx11", "tx12", "tx13", - "tx14", "tx15"; - }; - - cppi41dma: dma-controller@47402000 { - compatible = "ti,am3359-cppi41"; - reg = <0x47400000 0x1000 - 0x47402000 0x1000 - 0x47403000 0x1000 - 0x47404000 0x4000>; - reg-names = "glue", "controller", "scheduler", "queuemgr"; - interrupts = <17>; - interrupt-names = "glue"; - #dma-cells = <2>; - #dma-channels = <30>; - #dma-requests = <256>; - }; - }; - - wd_timer2: wd_timer@480c2000 { - compatible = "ti,omap3-wdt"; - ti,hwmods = "wd_timer"; - reg = <0x480c2000 0x1000>; - interrupts = <0>; - }; - }; -}; - -#include "dm816x-clocks.dtsi" diff --git a/sys/gnu/dts/arm/dove-cm-a510.dtsi b/sys/gnu/dts/arm/dove-cm-a510.dtsi deleted file mode 100644 index 9b9dfbe07be..00000000000 --- a/sys/gnu/dts/arm/dove-cm-a510.dtsi +++ /dev/null @@ -1,195 +0,0 @@ -/* - * Device Tree include for Compulab CM-A510 System-on-Module - * - * Copyright (C) 2015, Sebastian Hesselbarth - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the - * License. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/* - * The CM-A510 comes with several optional components: - * - * Memory options: - * D512: 512M - * D1024: 1G - * - * NAND options: - * N512: 512M NAND - * - * Ethernet options: - * E1: PHY RTL8211D on internal GbE (SMI address 0x03) - * E2: Additional ethernet NIC RTL8111D on PCIe1 - * - * Audio options: - * A: TI TLV320AIC23b audio codec (I2C address 0x1a) - * - * Touchscreen options: - * I: TI TSC2046 touchscreen controller (on SPI1) - * - * USB options: - * U2: 2 dual-role USB2.0 ports - * U4: 2 additional USB2.0 host ports (via USB1) - * - * WiFi options: - * W: Broadcom BCM4319 802.11b/g/n (USI WM-N-BM-01 on SDIO1) - * - * GPIOs used on CM-A510: - * 1 GbE PHY reset (active low) - * 3 WakeUp - * 8 PowerOff (active low) - * 13 Touchscreen pen irq (active low) - * 65 System LED (active high) - * 69 USB Hub reset (active low) - * 70 WLAN reset (active low) - * 71 WLAN regulator (active high) - */ - -#include "dove.dtsi" - -/ { - model = "Compulab CM-A510"; - compatible = "compulab,cm-a510", "marvell,dove"; - - /* - * Set the minimum memory size here and let the - * bootloader set the real size. - */ - memory { - device_type = "memory"; - reg = <0x00000000 0x20000000>; - }; - - leds { - compatible = "gpio-leds"; - /* Set upper NAND data bit to GPO */ - pinctrl-0 = <&pmx_nand_gpo>; - pinctrl-names = "default"; - - system { - label = "cm-a510:system:green"; - gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - wifi_power: regulator@1 { - compatible = "regulator-fixed"; - regulator-name = "WiFi Power"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 7 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -/* Optional RTL8211D GbE PHY on SMI address 0x03 */ -ðphy { - reg = <3>; - status = "disabled"; -}; - -&i2c0 { - /* Optional TI TLV320AIC23b audio codec */ - opt_audio: audio@1a { - compatible = "ti,tlv320aic23"; - reg = <0x1a>; - status = "disabled"; - }; -}; - -/* Optional RTL8111D GbE NIC on PCIe1 */ -&pcie { status = "disabled"; }; - -&pcie1 { - pinctrl-0 = <&pmx_pcie1_clkreq>; - pinctrl-names = "default"; - status = "disabled"; -}; - -&pinctrl { - pmx_uart2: pmx-uart2 { - marvell,pins = "mpp14", "mpp15"; - marvell,function = "uart2"; - }; -}; - -/* Optional Broadcom BCM4319 802.11b/g/n WiFi module */ -&sdio1 { - non-removable; - vmmc-supply = <&wifi_power>; - reset-gpio = <&gpio2 6 GPIO_ACTIVE_LOW>; - status = "disabled"; -}; - -&spi0 { - status = "okay"; - - /* 1M Flash Winbond W25Q80BL */ - flash@0 { - compatible = "winbond,w25q80"; - spi-max-frequency = <80000000>; - reg = <0>; - }; -}; - -&spi1 { - pinctrl-0 = <&pmx_spi1_20_23>; - pinctrl-names = "default"; - status = "disabled"; - - /* Optional TI TSC2046 touchscreen controller */ - opt_touch: touchscreen@0 { - compatible = "ti,tsc2046"; - spi-max-frequency = <2500000>; - reg = <0>; - pinctrl-0 = <&pmx_gpio_13>; - pinctrl-names = "default"; - interrupts-extended = <&gpio0 13 IRQ_TYPE_EDGE_FALLING>; - }; -}; - -&uart2 { - pinctrl-0 = <&pmx_uart2>; - pinctrl-names = "default"; -}; diff --git a/sys/gnu/dts/arm/dove-cubox-es.dts b/sys/gnu/dts/arm/dove-cubox-es.dts deleted file mode 100644 index ad361ec1361..00000000000 --- a/sys/gnu/dts/arm/dove-cubox-es.dts +++ /dev/null @@ -1,13 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "dove-cubox.dts" - -/ { - model = "SolidRun CuBox (Engineering Sample)"; - compatible = "solidrun,cubox-es", "solidrun,cubox", "marvell,dove"; -}; - -&sdio0 { - /* sdio0 card detect is connected to wrong pin on CuBox ES */ - cd-gpios = <&gpio0 12 1>; - pinctrl-0 = <&pmx_sdio0 &pmx_gpio_12>; -}; diff --git a/sys/gnu/dts/arm/dove-cubox.dts b/sys/gnu/dts/arm/dove-cubox.dts deleted file mode 100644 index 3e1584e787a..00000000000 --- a/sys/gnu/dts/arm/dove-cubox.dts +++ /dev/null @@ -1,143 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "dove.dtsi" - -/ { - model = "SolidRun CuBox"; - compatible = "solidrun,cubox", "marvell,dove"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x40000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_gpio_18>; - pinctrl-names = "default"; - - power { - label = "Power"; - gpios = <&gpio0 18 1>; - default-state = "keep"; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - usb_power: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "USB Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 1 0>; - pinctrl-0 = <&pmx_gpio_1>; - pinctrl-names = "default"; - }; - }; - - clocks { - /* 25MHz reference crystal */ - ref25: oscillator { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - }; - - ir_recv: ir-receiver { - compatible = "gpio-ir-receiver"; - gpios = <&gpio0 19 1>; - pinctrl-0 = <&pmx_gpio_19>; - pinctrl-names = "default"; - }; - - gpu-subsystem { - status = "okay"; - }; -}; - -&uart0 { status = "okay"; }; -&sata0 { status = "okay"; }; -&mdio { status = "okay"; }; -ð { status = "okay"; }; - -ðphy { - compatible = "marvell,88e1310"; - reg = <1>; -}; - -&gpu { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - clock-frequency = <100000>; - - si5351: clock-generator@60 { - compatible = "silabs,si5351a-msop"; - reg = <0x60>; - #address-cells = <1>; - #size-cells = <0>; - #clock-cells = <1>; - - /* connect xtal input to 25MHz reference */ - clocks = <&ref25>; - clock-names = "xtal"; - - /* connect xtal input as source of pll0 and pll1 */ - silabs,pll-source = <0 0>, <1 0>; - - clkout0 { - reg = <0>; - silabs,drive-strength = <8>; - silabs,multisynth-source = <0>; - silabs,clock-source = <0>; - silabs,pll-master; - }; - - clkout2 { - reg = <2>; - silabs,drive-strength = <8>; - silabs,multisynth-source = <1>; - silabs,clock-source = <0>; - silabs,pll-master; - }; - }; -}; - -&sdio0 { - status = "okay"; -}; - -&spi0 { - status = "okay"; - - /* spi0.0: 4M Flash Winbond W25Q32BV */ - spi-flash@0 { - compatible = "st,w25q32"; - spi-max-frequency = <20000000>; - reg = <0>; - }; -}; - -&audio1 { - status = "okay"; - clocks = <&gate_clk 13>, <&si5351 2>; - clock-names = "internal", "extclk"; - pinctrl-0 = <&pmx_audio1_i2s1_spdifo &pmx_audio1_extclk>; - pinctrl-names = "default"; -}; diff --git a/sys/gnu/dts/arm/dove-d2plug.dts b/sys/gnu/dts/arm/dove-d2plug.dts deleted file mode 100644 index 273f12ca251..00000000000 --- a/sys/gnu/dts/arm/dove-d2plug.dts +++ /dev/null @@ -1,70 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "dove.dtsi" - -/ { - model = "Globalscale D2Plug"; - compatible = "globalscale,d2plug", "marvell,dove"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x40000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_gpio_0 &pmx_gpio_1 &pmx_gpio_2>; - pinctrl-names = "default"; - - wlan-ap { - label = "wlan-ap"; - gpios = <&gpio0 0 1>; - }; - - wlan-act { - label = "wlan-act"; - gpios = <&gpio0 1 1>; - }; - - bluetooth-act { - label = "bt-act"; - gpios = <&gpio0 2 1>; - }; - }; -}; - -&uart0 { status = "okay"; }; -&sata0 { status = "okay"; }; -&i2c0 { status = "okay"; }; -&mdio { status = "okay"; }; -ð { status = "okay"; }; - -/* Samsung M8G2F eMMC */ -&sdio0 { - status = "okay"; - non-removable; - bus-width = <4>; -}; - -/* Marvell SD8787 WLAN/BT */ -&sdio1 { - status = "okay"; - non-removable; - bus-width = <4>; -}; - -&spi0 { - status = "okay"; - - /* spi0.0: 4M Flash Macronix MX25L3205D */ - spi-flash@0 { - compatible = "st,m25l3205d"; - spi-max-frequency = <20000000>; - reg = <0>; - }; -}; diff --git a/sys/gnu/dts/arm/dove-d3plug.dts b/sys/gnu/dts/arm/dove-d3plug.dts deleted file mode 100644 index 826026c28f9..00000000000 --- a/sys/gnu/dts/arm/dove-d3plug.dts +++ /dev/null @@ -1,104 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "dove.dtsi" - -/ { - model = "Globalscale D3Plug"; - compatible = "globalscale,d3plug", "marvell,dove"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x40000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk root=/dev/mmcblk0p2 rw rootwait"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_gpio_0 &pmx_gpio_1 &pmx_gpio_2>; - pinctrl-names = "default"; - - wlan-act { - label = "wlan-act"; - gpios = <&gpio0 0 1>; - }; - - wlan-ap { - label = "wlan-ap"; - gpios = <&gpio0 1 1>; - }; - - status { - label = "status"; - gpios = <&gpio0 2 1>; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - usb_power: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "USB Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 8 0>; - pinctrl-0 = <&pmx_gpio_8>; - pinctrl-names = "default"; - }; - }; -}; - -&uart0 { status = "okay"; }; -&sata0 { status = "okay"; }; -&i2c0 { status = "okay"; }; - -/* Samsung M8G2F eMMC */ -&sdio0 { - status = "okay"; - non-removable; - bus-width = <4>; -}; - -/* Marvell SD8787 WLAN/BT */ -&sdio1 { - status = "okay"; - non-removable; -}; - -&spi0 { - status = "okay"; - - /* spi0.0: 2M Flash Macronix MX25L1605D */ - spi-flash@0 { - compatible = "st,m25l1605d"; - spi-max-frequency = <86000000>; - reg = <0>; - }; -}; - -&pcie { - status = "okay"; - /* Fresco Logic USB3.0 xHCI controller */ - pcie@1 { - status = "okay"; - reset-gpios = <&gpio0 26 1>; - reset-delay-us = <20000>; - pinctrl-0 = <&pmx_camera_gpio>; - pinctrl-names = "default"; - }; - /* Mini-PCIe slot */ - pcie@2 { - status = "okay"; - reset-gpios = <&gpio0 25 1>; - }; -}; diff --git a/sys/gnu/dts/arm/dove-dove-db.dts b/sys/gnu/dts/arm/dove-dove-db.dts deleted file mode 100644 index 1754a62e014..00000000000 --- a/sys/gnu/dts/arm/dove-dove-db.dts +++ /dev/null @@ -1,39 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "dove.dtsi" - -/ { - model = "Marvell DB-MV88AP510-BP Development Board"; - compatible = "marvell,dove-db", "marvell,dove"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x40000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - }; -}; - -&uart0 { status = "okay"; }; -&uart1 { status = "okay"; }; -&sdio0 { status = "okay"; }; -&sdio1 { status = "okay"; }; -&sata0 { status = "okay"; }; - -&spi0 { - status = "okay"; - - /* spi0.0: 4M Flash ST-M25P32-VMF6P */ - spi-flash@0 { - compatible = "st,m25p32"; - spi-max-frequency = <20000000>; - reg = <0>; - }; -}; - -&i2c0 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/dove-sbc-a510.dts b/sys/gnu/dts/arm/dove-sbc-a510.dts deleted file mode 100644 index 2bb85a9b761..00000000000 --- a/sys/gnu/dts/arm/dove-sbc-a510.dts +++ /dev/null @@ -1,182 +0,0 @@ -/* - * Device Tree file for Compulab SBC-A510 Single Board Computer - * - * Copyright (C) 2015, Sebastian Hesselbarth - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the - * License. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/* - * SBC-A510 comprises a PCA9555 I2C GPIO expander its GPIO lines connected to - * - * 0.0 USB0 VBUS_EN (active high) - * 0.1 USB0 VBUS_GOOD - * 0.2 DVI transmitter TI TFP410 MSEN - * 0.3 DVI transmitter TI TFP410 PD# (active low power down) - * 0.4 LVDS transmitter DS90C365 PD# (active low power down) - * 0.5 LCD nRST (active low reset) - * 0.6 PCIe0 nRST (active low reset) - * 0.7 mini-PCIe slot W_DISABLE# - * - * 1.0 MMC WP - * 1.1 Camera Input FPC FLASH_STB and P21.5 - * 1.2 Camera Input FPC WE and P21.22 - * 1.3 MMC VCC_EN (active high) and P21.7 - * 1.4 Camera Input FPC AFTR_RST and P21.17 - * 1.5 Camera Input FPC OE and P21.19 - * 1.6 Camera Input FPC SNPSHT and P21.6 - * 1.7 Camera Input FPC SHTR and P21.10 - */ - -/dts-v1/; - -#include "dove-cm-a510.dtsi" - -/ { - model = "Compulab SBC-A510"; - compatible = "compulab,sbc-a510", "compulab,cm-a510", "marvell,dove"; - - chosen { - stdout-path = &uart0; - }; - - regulators { - usb0_power: regulator@2 { - compatible = "regulator-fixed"; - regulator-name = "USB Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio_ext 0 GPIO_ACTIVE_HIGH>; - }; - - mmc_power: regulator@3 { - compatible = "regulator-fixed"; - regulator-name = "MMC Power"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio_ext 13 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -/* Ethernet0 depends on CM-A510 option E1 */ -&mdio { status = "disabled"; }; -ð { status = "disabled"; }; -ðphy { status = "disabled"; }; - -/* - * USB port 0 can be powered and monitored by I2C GPIO expander: - * VBUS_ENABLE on GPIO0, VBUS_GOOD on GPIO1 - */ -&ehci0 { - status = "okay"; - vbus-supply = <&usb0_power>; -}; - -/* USB port 1 (and ports 2, 3 if CM-A510 has U4 option) */ -&ehci1 { status = "okay"; }; - -/* - * I2C bus layout: - * i2c0: - * - Audio Codec, 0x1a (option from CM-A510) - * - DVI transmitter TI TFP410, 0x39 - * - HDMI/DVI DDC channel - * i2c1: - * - GPIO expander, NXP PCA9555, 0x20 - * - VGA DDC channel - */ -&i2c { - pinctrl-0 = <&pmx_i2c1>; - pinctrl-names = "default"; -}; - -&i2c0 { - /* TI TFP410 DVI transmitter */ - dvi: video@39 { - compatible = "ti,tfp410"; - reg = <0x39>; - powerdown-gpio = <&gpio_ext 3 GPIO_ACTIVE_LOW>; - }; -}; - -&i2c1 { - status = "okay"; - - /* NXP PCA9555 GPIO expander */ - gpio_ext: gpio@20 { - compatible = "nxp,pca9555"; - reg = <0x20>; - #gpio-cells = <2>; - }; -}; - -&pcie { status = "okay"; }; - -/* - * PCIe0 can be configured by Jumper E1 to be either connected to - * a mini-PCIe slot or a Pericom PI7C9X111 PCIe-to-PCI bridge. - */ -&pcie0 { - status = "okay"; - pinctrl-0 = <&pmx_pcie0_clkreq>; - pinctrl-names = "default"; - reset-gpios = <&gpio_ext 6 GPIO_ACTIVE_LOW>; -}; - -/* Ethernet1 depends on CM-A510 option E2 */ -&pcie1 { status = "disabled"; }; - -/* SATA connector */ -&sata0 { status = "okay"; }; - -/* - * SDIO0 is connected to a MMC/SD/SDIO socket, I2C GPIO expander has - * VCC_MMC_ENABLE on GPIO13, MMC_WP on GPIO10 - */ -&sdio0 { - vmmc-supply = <&mmc_power>; - wp-gpios = <&gpio_ext 10 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -/* UART0 on RS232 mini-connector */ -&uart0 { status = "okay"; }; -/* UART2 on pin headers */ -&uart2 { status = "okay"; }; diff --git a/sys/gnu/dts/arm/dove.dtsi b/sys/gnu/dts/arm/dove.dtsi deleted file mode 100644 index 3081b04e8c0..00000000000 --- a/sys/gnu/dts/arm/dove.dtsi +++ /dev/null @@ -1,806 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include -#include - -#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) - -/ { - #address-cells = <1>; - #size-cells = <1>; - compatible = "marvell,dove"; - model = "Marvell Armada 88AP510 SoC"; - interrupt-parent = <&intc>; - - aliases { - gpio0 = &gpio0; - gpio1 = &gpio1; - gpio2 = &gpio2; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "marvell,pj4a", "marvell,sheeva-v7"; - device_type = "cpu"; - next-level-cache = <&l2>; - reg = <0>; - }; - }; - - l2: l2-cache { - compatible = "marvell,tauros2-cache"; - marvell,tauros2-cache-features = <0>; - }; - - gpu-subsystem { - compatible = "marvell,dove-gpu-subsystem"; - cores = <&gpu>; - status = "disabled"; - }; - - i2c-mux { - compatible = "i2c-mux-pinctrl"; - #address-cells = <1>; - #size-cells = <0>; - - i2c-parent = <&i2c>; - - pinctrl-names = "i2c0", "i2c1", "i2c2"; - pinctrl-0 = <&pmx_i2cmux_0>; - pinctrl-1 = <&pmx_i2cmux_1>; - pinctrl-2 = <&pmx_i2cmux_2>; - - i2c0: i2c@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - }; - - i2c1: i2c@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - /* Requires pmx_i2c1 on i2c controller node */ - status = "disabled"; - }; - - i2c2: i2c@2 { - reg = <2>; - #address-cells = <1>; - #size-cells = <0>; - /* Requires pmx_i2c2 on i2c controller node */ - status = "disabled"; - }; - }; - - mbus { - compatible = "marvell,dove-mbus", "marvell,mbus", "simple-bus"; - #address-cells = <2>; - #size-cells = <1>; - controller = <&mbusc>; - pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256M MEM space */ - pcie-io-aperture = <0xf2000000 0x00200000>; /* 2M I/O space */ - - ranges = ; /* PMU SRAM 1M */ - - pcie: pcie { - compatible = "marvell,dove-pcie"; - status = "disabled"; - device_type = "pci"; - #address-cells = <3>; - #size-cells = <2>; - - msi-parent = <&intc>; - bus-range = <0x00 0xff>; - - ranges = <0x82000000 0x0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x2000 - 0x82000000 0x0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x2000 - 0x82000000 0x1 0x0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 Mem */ - 0x81000000 0x1 0x0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 I/O */ - 0x82000000 0x2 0x0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 Mem */ - 0x81000000 0x2 0x0 MBUS_ID(0x08, 0xe0) 0 1 0>; /* Port 1.0 I/O */ - - pcie0: pcie@1 { - device_type = "pci"; - status = "disabled"; - assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; - reg = <0x0800 0 0 0 0>; - clocks = <&gate_clk 4>; - marvell,pcie-port = <0>; - - #address-cells = <3>; - #size-cells = <2>; - ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 - 0x81000000 0 0 0x81000000 0x1 0 1 0>; - bus-range = <0x00 0xff>; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &intc 16>; - }; - - pcie1: pcie@2 { - device_type = "pci"; - status = "disabled"; - assigned-addresses = <0x82002800 0 0x80000 0 0x2000>; - reg = <0x1000 0 0 0 0>; - clocks = <&gate_clk 5>; - marvell,pcie-port = <1>; - - #address-cells = <3>; - #size-cells = <2>; - ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 - 0x81000000 0 0 0x81000000 0x2 0 1 0>; - bus-range = <0x00 0xff>; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &intc 18>; - }; - }; - - internal-regs { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 MBUS_ID(0xf0, 0x01) 0 0x0100000 /* MBUS regs 1M */ - 0x00800000 MBUS_ID(0xf0, 0x02) 0 0x1000000 /* AXI regs 16M */ - 0xffffe000 MBUS_ID(0x03, 0x01) 0 0x0000800 /* CESA SRAM 2k */ - 0xfffff000 MBUS_ID(0x0d, 0x00) 0 0x0000800>; /* PMU SRAM 2k */ - - spi0: spi@10600 { - compatible = "marvell,orion-spi"; - #address-cells = <1>; - #size-cells = <0>; - cell-index = <0>; - interrupts = <6>; - reg = <0x10600 0x28>; - clocks = <&core_clk 0>; - pinctrl-0 = <&pmx_spi0>; - pinctrl-names = "default"; - status = "disabled"; - }; - - i2c: i2c@11000 { - compatible = "marvell,mv64xxx-i2c"; - reg = <0x11000 0x20>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <11>; - clock-frequency = <400000>; - timeout-ms = <1000>; - clocks = <&core_clk 0>; - status = "okay"; - }; - - uart0: serial@12000 { - compatible = "ns16550a"; - reg = <0x12000 0x100>; - reg-shift = <2>; - interrupts = <7>; - clocks = <&core_clk 0>; - status = "disabled"; - }; - - uart1: serial@12100 { - compatible = "ns16550a"; - reg = <0x12100 0x100>; - reg-shift = <2>; - interrupts = <8>; - clocks = <&core_clk 0>; - pinctrl-0 = <&pmx_uart1>; - pinctrl-names = "default"; - status = "disabled"; - }; - - uart2: serial@12200 { - compatible = "ns16550a"; - reg = <0x12200 0x100>; - reg-shift = <2>; - interrupts = <9>; - clocks = <&core_clk 0>; - status = "disabled"; - }; - - uart3: serial@12300 { - compatible = "ns16550a"; - reg = <0x12300 0x100>; - reg-shift = <2>; - interrupts = <10>; - clocks = <&core_clk 0>; - status = "disabled"; - }; - - spi1: spi@14600 { - compatible = "marvell,orion-spi"; - #address-cells = <1>; - #size-cells = <0>; - cell-index = <1>; - interrupts = <5>; - reg = <0x14600 0x28>; - clocks = <&core_clk 0>; - status = "disabled"; - }; - - mbusc: mbus-ctrl@20000 { - compatible = "marvell,mbus-controller"; - reg = <0x20000 0x80>, <0x800100 0x8>; - }; - - sysc: system-ctrl@20000 { - compatible = "marvell,orion-system-controller"; - reg = <0x20000 0x110>; - }; - - bridge_intc: bridge-interrupt-ctrl@20110 { - compatible = "marvell,orion-bridge-intc"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x20110 0x8>; - interrupts = <0>; - marvell,#interrupts = <5>; - }; - - intc: main-interrupt-ctrl@20200 { - compatible = "marvell,orion-intc"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x20200 0x10>, <0x20210 0x10>; - }; - - timer: timer@20300 { - compatible = "marvell,orion-timer"; - reg = <0x20300 0x20>; - interrupt-parent = <&bridge_intc>; - interrupts = <1>, <2>; - clocks = <&core_clk 0>; - }; - - watchdog@20300 { - compatible = "marvell,orion-wdt"; - reg = <0x20300 0x28>, <0x20108 0x4>; - interrupt-parent = <&bridge_intc>; - interrupts = <3>; - clocks = <&core_clk 0>; - }; - - crypto: crypto-engine@30000 { - compatible = "marvell,dove-crypto"; - reg = <0x30000 0x10000>; - reg-names = "regs"; - interrupts = <31>; - clocks = <&gate_clk 15>; - marvell,crypto-srams = <&crypto_sram>; - marvell,crypto-sram-size = <0x800>; - status = "okay"; - }; - - ehci0: usb-host@50000 { - compatible = "marvell,orion-ehci"; - reg = <0x50000 0x1000>; - interrupts = <24>; - clocks = <&gate_clk 0>; - status = "okay"; - }; - - ehci1: usb-host@51000 { - compatible = "marvell,orion-ehci"; - reg = <0x51000 0x1000>; - interrupts = <25>; - clocks = <&gate_clk 1>; - status = "okay"; - }; - - xor0: dma-engine@60800 { - compatible = "marvell,orion-xor"; - reg = <0x60800 0x100 - 0x60a00 0x100>; - clocks = <&gate_clk 23>; - status = "okay"; - - channel0 { - interrupts = <39>; - dmacap,memcpy; - dmacap,xor; - }; - - channel1 { - interrupts = <40>; - dmacap,memcpy; - dmacap,xor; - }; - }; - - xor1: dma-engine@60900 { - compatible = "marvell,orion-xor"; - reg = <0x60900 0x100 - 0x60b00 0x100>; - clocks = <&gate_clk 24>; - status = "okay"; - - channel0 { - interrupts = <42>; - dmacap,memcpy; - dmacap,xor; - }; - - channel1 { - interrupts = <43>; - dmacap,memcpy; - dmacap,xor; - }; - }; - - sdio1: sdio-host@90000 { - compatible = "marvell,dove-sdhci"; - reg = <0x90000 0x100>; - interrupts = <36>, <38>; - clocks = <&gate_clk 9>; - pinctrl-0 = <&pmx_sdio1>; - pinctrl-names = "default"; - status = "disabled"; - }; - - eth: ethernet-ctrl@72000 { - compatible = "marvell,orion-eth"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x72000 0x4000>; - clocks = <&gate_clk 2>; - marvell,tx-checksum-limit = <1600>; - status = "disabled"; - - ethernet-port@0 { - compatible = "marvell,orion-eth-port"; - reg = <0>; - interrupts = <29>; - /* overwrite MAC address in bootloader */ - local-mac-address = [00 00 00 00 00 00]; - phy-handle = <ðphy>; - }; - }; - - mdio: mdio-bus@72004 { - compatible = "marvell,orion-mdio"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x72004 0x84>; - interrupts = <30>; - clocks = <&gate_clk 2>; - status = "disabled"; - - ethphy: ethernet-phy { - /* set phy address in board file */ - }; - }; - - sdio0: sdio-host@92000 { - compatible = "marvell,dove-sdhci"; - reg = <0x92000 0x100>; - interrupts = <35>, <37>; - clocks = <&gate_clk 8>; - pinctrl-0 = <&pmx_sdio0>; - pinctrl-names = "default"; - status = "disabled"; - }; - - sata0: sata-host@a0000 { - compatible = "marvell,orion-sata"; - reg = <0xa0000 0x2400>; - interrupts = <62>; - clocks = <&gate_clk 3>; - phys = <&sata_phy0>; - phy-names = "port0"; - nr-ports = <1>; - status = "disabled"; - }; - - sata_phy0: sata-phy@a2000 { - compatible = "marvell,mvebu-sata-phy"; - reg = <0xa2000 0x0334>; - clocks = <&gate_clk 3>; - clock-names = "sata"; - #phy-cells = <0>; - status = "ok"; - }; - - audio0: audio-controller@b0000 { - compatible = "marvell,dove-audio"; - reg = <0xb0000 0x2210>; - interrupts = <19>, <20>; - clocks = <&gate_clk 12>; - clock-names = "internal"; - status = "disabled"; - }; - - audio1: audio-controller@b4000 { - compatible = "marvell,dove-audio"; - reg = <0xb4000 0x2210>; - interrupts = <21>, <22>; - clocks = <&gate_clk 13>; - clock-names = "internal"; - status = "disabled"; - }; - - pmu: power-management@d0000 { - compatible = "marvell,dove-pmu", "simple-bus"; - reg = <0xd0000 0x8000>, <0xd8000 0x8000>; - ranges = <0x00000000 0x000d0000 0x8000 - 0x00008000 0x000d8000 0x8000>; - interrupts = <33>; - interrupt-controller; - #address-cells = <1>; - #size-cells = <1>; - #interrupt-cells = <1>; - #reset-cells = <1>; - - domains { - vpu_domain: vpu-domain { - #power-domain-cells = <0>; - marvell,pmu_pwr_mask = <0x00000008>; - marvell,pmu_iso_mask = <0x00000001>; - resets = <&pmu 16>; - }; - - gpu_domain: gpu-domain { - #power-domain-cells = <0>; - marvell,pmu_pwr_mask = <0x00000004>; - marvell,pmu_iso_mask = <0x00000002>; - resets = <&pmu 18>; - }; - }; - - thermal: thermal-diode@1c { - compatible = "marvell,dove-thermal"; - reg = <0x001c 0x0c>, <0x005c 0x08>; - }; - - gate_clk: clock-gating-ctrl@38 { - compatible = "marvell,dove-gating-clock"; - reg = <0x0038 0x4>; - clocks = <&core_clk 0>; - #clock-cells = <1>; - }; - - divider_clk: core-clock@64 { - compatible = "marvell,dove-divider-clock"; - reg = <0x0064 0x8>; - #clock-cells = <1>; - }; - - pinctrl: pin-ctrl@200 { - compatible = "marvell,dove-pinctrl"; - reg = <0x0200 0x14>, - <0x0440 0x04>; - clocks = <&gate_clk 22>; - - pmx_gpio_0: pmx-gpio-0 { - marvell,pins = "mpp0"; - marvell,function = "gpio"; - }; - - pmx_gpio_1: pmx-gpio-1 { - marvell,pins = "mpp1"; - marvell,function = "gpio"; - }; - - pmx_gpio_2: pmx-gpio-2 { - marvell,pins = "mpp2"; - marvell,function = "gpio"; - }; - - pmx_gpio_3: pmx-gpio-3 { - marvell,pins = "mpp3"; - marvell,function = "gpio"; - }; - - pmx_gpio_4: pmx-gpio-4 { - marvell,pins = "mpp4"; - marvell,function = "gpio"; - }; - - pmx_gpio_5: pmx-gpio-5 { - marvell,pins = "mpp5"; - marvell,function = "gpio"; - }; - - pmx_gpio_6: pmx-gpio-6 { - marvell,pins = "mpp6"; - marvell,function = "gpio"; - }; - - pmx_gpio_7: pmx-gpio-7 { - marvell,pins = "mpp7"; - marvell,function = "gpio"; - }; - - pmx_gpio_8: pmx-gpio-8 { - marvell,pins = "mpp8"; - marvell,function = "gpio"; - }; - - pmx_gpio_9: pmx-gpio-9 { - marvell,pins = "mpp9"; - marvell,function = "gpio"; - }; - - pmx_pcie1_clkreq: pmx-pcie1-clkreq { - marvell,pins = "mpp9"; - marvell,function = "pex1"; - }; - - pmx_gpio_10: pmx-gpio-10 { - marvell,pins = "mpp10"; - marvell,function = "gpio"; - }; - - pmx_gpio_11: pmx-gpio-11 { - marvell,pins = "mpp11"; - marvell,function = "gpio"; - }; - - pmx_pcie0_clkreq: pmx-pcie0-clkreq { - marvell,pins = "mpp11"; - marvell,function = "pex0"; - }; - - pmx_gpio_12: pmx-gpio-12 { - marvell,pins = "mpp12"; - marvell,function = "gpio"; - }; - - pmx_gpio_13: pmx-gpio-13 { - marvell,pins = "mpp13"; - marvell,function = "gpio"; - }; - - pmx_audio1_extclk: pmx-audio1-extclk { - marvell,pins = "mpp13"; - marvell,function = "audio1"; - }; - - pmx_gpio_14: pmx-gpio-14 { - marvell,pins = "mpp14"; - marvell,function = "gpio"; - }; - - pmx_gpio_15: pmx-gpio-15 { - marvell,pins = "mpp15"; - marvell,function = "gpio"; - }; - - pmx_gpio_16: pmx-gpio-16 { - marvell,pins = "mpp16"; - marvell,function = "gpio"; - }; - - pmx_gpio_17: pmx-gpio-17 { - marvell,pins = "mpp17"; - marvell,function = "gpio"; - }; - - pmx_gpio_18: pmx-gpio-18 { - marvell,pins = "mpp18"; - marvell,function = "gpio"; - }; - - pmx_gpio_19: pmx-gpio-19 { - marvell,pins = "mpp19"; - marvell,function = "gpio"; - }; - - pmx_gpio_20: pmx-gpio-20 { - marvell,pins = "mpp20"; - marvell,function = "gpio"; - }; - - pmx_gpio_21: pmx-gpio-21 { - marvell,pins = "mpp21"; - marvell,function = "gpio"; - }; - - pmx_camera: pmx-camera { - marvell,pins = "mpp_camera"; - marvell,function = "camera"; - }; - - pmx_camera_gpio: pmx-camera-gpio { - marvell,pins = "mpp_camera"; - marvell,function = "gpio"; - }; - - pmx_sdio0: pmx-sdio0 { - marvell,pins = "mpp_sdio0"; - marvell,function = "sdio0"; - }; - - pmx_sdio0_gpio: pmx-sdio0-gpio { - marvell,pins = "mpp_sdio0"; - marvell,function = "gpio"; - }; - - pmx_sdio1: pmx-sdio1 { - marvell,pins = "mpp_sdio1"; - marvell,function = "sdio1"; - }; - - pmx_sdio1_gpio: pmx-sdio1-gpio { - marvell,pins = "mpp_sdio1"; - marvell,function = "gpio"; - }; - - pmx_audio1_gpio: pmx-audio1-gpio { - marvell,pins = "mpp_audio1"; - marvell,function = "gpio"; - }; - - pmx_audio1_i2s1_spdifo: pmx-audio1-i2s1-spdifo { - marvell,pins = "mpp_audio1"; - marvell,function = "i2s1/spdifo"; - }; - - pmx_spi0: pmx-spi0 { - marvell,pins = "mpp_spi0"; - marvell,function = "spi0"; - }; - - pmx_spi0_gpio: pmx-spi0-gpio { - marvell,pins = "mpp_spi0"; - marvell,function = "gpio"; - }; - - pmx_spi1_4_7: pmx-spi1-4-7 { - marvell,pins = "mpp4", "mpp5", - "mpp6", "mpp7"; - marvell,function = "spi1"; - }; - - pmx_spi1_20_23: pmx-spi1-20-23 { - marvell,pins = "mpp20", "mpp21", - "mpp22", "mpp23"; - marvell,function = "spi1"; - }; - - pmx_uart1: pmx-uart1 { - marvell,pins = "mpp_uart1"; - marvell,function = "uart1"; - }; - - pmx_uart1_gpio: pmx-uart1-gpio { - marvell,pins = "mpp_uart1"; - marvell,function = "gpio"; - }; - - pmx_nand: pmx-nand { - marvell,pins = "mpp_nand"; - marvell,function = "nand"; - }; - - pmx_nand_gpo: pmx-nand-gpo { - marvell,pins = "mpp_nand"; - marvell,function = "gpo"; - }; - - pmx_i2c1: pmx-i2c1 { - marvell,pins = "mpp17", "mpp19"; - marvell,function = "twsi"; - }; - - pmx_i2c2: pmx-i2c2 { - marvell,pins = "mpp_audio1"; - marvell,function = "twsi"; - }; - - pmx_ssp_i2c2: pmx-ssp-i2c2 { - marvell,pins = "mpp_audio1"; - marvell,function = "ssp/twsi"; - }; - - pmx_i2cmux_0: pmx-i2cmux-0 { - marvell,pins = "twsi"; - marvell,function = "twsi-opt1"; - }; - - pmx_i2cmux_1: pmx-i2cmux-1 { - marvell,pins = "twsi"; - marvell,function = "twsi-opt2"; - }; - - pmx_i2cmux_2: pmx-i2cmux-2 { - marvell,pins = "twsi"; - marvell,function = "twsi-opt3"; - }; - }; - - core_clk: core-clocks@214 { - compatible = "marvell,dove-core-clock"; - reg = <0x0214 0x4>; - #clock-cells = <1>; - }; - - gpio0: gpio-ctrl@400 { - compatible = "marvell,orion-gpio"; - #gpio-cells = <2>; - gpio-controller; - reg = <0x0400 0x20>; - ngpios = <32>; - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&intc>; - interrupts = <12>, <13>, <14>, <60>; - }; - - gpio1: gpio-ctrl@420 { - compatible = "marvell,orion-gpio"; - #gpio-cells = <2>; - gpio-controller; - reg = <0x0420 0x20>; - ngpios = <32>; - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&intc>; - interrupts = <61>; - }; - - rtc: real-time-clock@8500 { - compatible = "marvell,orion-rtc"; - reg = <0x8500 0x20>; - interrupts = <5>; - }; - }; - - gconf: global-config@e802c { - compatible = "marvell,dove-global-config", - "syscon"; - reg = <0xe802c 0x14>; - }; - - gpio2: gpio-ctrl@e8400 { - compatible = "marvell,orion-gpio"; - #gpio-cells = <2>; - gpio-controller; - reg = <0xe8400 0x0c>; - ngpios = <8>; - }; - - lcd1: lcd-controller@810000 { - compatible = "marvell,dove-lcd"; - reg = <0x810000 0x1000>; - interrupts = <46>; - status = "disabled"; - }; - - lcd0: lcd-controller@820000 { - compatible = "marvell,dove-lcd"; - reg = <0x820000 0x1000>; - interrupts = <47>; - status = "disabled"; - }; - - crypto_sram: sram@ffffe000 { - compatible = "mmio-sram"; - reg = <0xffffe000 0x800>; - clocks = <&gate_clk 15>; - #address-cells = <1>; - #size-cells = <1>; - }; - - gpu: gpu@840000 { - clocks = <÷r_clk 1>; - clock-names = "core"; - compatible = "vivante,gc"; - interrupts = <48>; - power-domains = <&gpu_domain>; - reg = <0x840000 0x4000>; - status = "disabled"; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/dra62x-clocks.dtsi b/sys/gnu/dts/arm/dra62x-clocks.dtsi deleted file mode 100644 index 11d1241b0e1..00000000000 --- a/sys/gnu/dts/arm/dra62x-clocks.dtsi +++ /dev/null @@ -1,45 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only - -#include "dm814x-clocks.dtsi" - -/* Compared to dm814x, dra62x does not have hdic, l3 or dss PLLs */ -&adpll_hdvic_ck { - status = "disabled"; -}; - -&adpll_l3_ck { - status = "disabled"; -}; - -&adpll_dss_ck { - status = "disabled"; -}; - -/* Compared to dm814x, dra62x has interconnect clocks on isp PLL */ -&sysclk4_ck { - clocks = <&adpll_isp_ck 1>; -}; - -&sysclk5_ck { - clocks = <&adpll_isp_ck 1>; -}; - -&sysclk6_ck { - clocks = <&adpll_isp_ck 1>; -}; - -/* - * Compared to dm814x, dra62x has different shifts and more mux options. - * Please add the extra options for ysclk_14 and 16 if really needed. - */ -&timer1_fck { - clocks = <&sysclk18_ck &aud_clkin0_ck &aud_clkin1_ck - &aud_clkin2_ck &devosc_ck &auxosc_ck &tclkin_ck>; - ti,bit-shift = <4>; -}; - -&timer2_fck { - clocks = <&sysclk18_ck &aud_clkin0_ck &aud_clkin1_ck - &aud_clkin2_ck &devosc_ck &auxosc_ck &tclkin_ck>; - ti,bit-shift = <8>; -}; diff --git a/sys/gnu/dts/arm/dra62x-j5eco-evm.dts b/sys/gnu/dts/arm/dra62x-j5eco-evm.dts deleted file mode 100644 index 861ab90a3f3..00000000000 --- a/sys/gnu/dts/arm/dra62x-j5eco-evm.dts +++ /dev/null @@ -1,144 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/dts-v1/; - -#include "dra62x.dtsi" -#include - -/ { - model = "DRA62x J5 Eco EVM"; - compatible = "ti,dra62x-j5eco-evm", "ti,dra62x", "ti,dm8148", "ti,dm814"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x40000000>; /* 1 GB */ - }; - - /* MIC94060YC6 controlled by SD1_POW pin */ - vmmcsd_fixed: fixedregulator0 { - compatible = "regulator-fixed"; - regulator-name = "vmmcsd_fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&cpsw_emac0 { - phy-handle = <ðphy0>; - phy-mode = "rgmii"; -}; - -&cpsw_emac1 { - phy-handle = <ðphy1>; - phy-mode = "rgmii"; -}; - -&davinci_mdio { - ethphy0: ethernet-phy@0 { - reg = <0>; - }; - - ethphy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&gpmc { - ranges = <0 0 0x04000000 0x01000000>; /* CS0: 16MB for NAND */ - - nand@0,0 { - compatible = "ti,omap2-nand"; - reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ - <1 IRQ_TYPE_NONE>; /* termcount */ - linux,mtd-name= "micron,mt29f2g16aadwp"; - #address-cells = <1>; - #size-cells = <1>; - ti,nand-ecc-opt = "bch8"; - nand-bus-width = <16>; - gpmc,device-width = <2>; - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <44>; - gpmc,cs-wr-off-ns = <44>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <34>; - gpmc,adv-wr-off-ns = <44>; - gpmc,we-on-ns = <0>; - gpmc,we-off-ns = <40>; - gpmc,oe-on-ns = <0>; - gpmc,oe-off-ns = <54>; - gpmc,access-ns = <64>; - gpmc,rd-cycle-ns = <82>; - gpmc,wr-cycle-ns = <82>; - gpmc,bus-turnaround-ns = <0>; - gpmc,cycle2cycle-delay-ns = <0>; - gpmc,clk-activation-ns = <0>; - gpmc,wr-access-ns = <40>; - gpmc,wr-data-mux-bus-ns = <0>; - partition@0 { - label = "X-Loader"; - reg = <0 0x80000>; - }; - partition@80000 { - label = "U-Boot"; - reg = <0x80000 0x1c0000>; - }; - partition@1c0000 { - label = "Environment"; - reg = <0x240000 0x40000>; - }; - partition@280000 { - label = "Kernel"; - reg = <0x280000 0x500000>; - }; - partition@780000 { - label = "Filesystem"; - reg = <0x780000 0xf880000>; - }; - }; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&sd1_pins>; - vmmc-supply = <&vmmcsd_fixed>; - bus-width = <4>; - cd-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>; -}; - -&pincntl { - sd1_pins: pinmux_sd1_pins { - pinctrl-single,pins = < - DM814X_IOPAD(0x0800, PIN_INPUT | 0x1) /* SD1_CLK */ - DM814X_IOPAD(0x0804, PIN_INPUT_PULLUP | 0x1) /* SD1_CMD */ - DM814X_IOPAD(0x0808, PIN_INPUT_PULLUP | 0x1) /* SD1_DAT[0] */ - DM814X_IOPAD(0x080c, PIN_INPUT_PULLUP | 0x1) /* SD1_DAT[1] */ - DM814X_IOPAD(0x0810, PIN_INPUT_PULLUP | 0x1) /* SD1_DAT[2] */ - DM814X_IOPAD(0x0814, PIN_INPUT_PULLUP | 0x1) /* SD1_DAT[3] */ - DM814X_IOPAD(0x0924, PIN_OUTPUT | 0x40) /* SD1_POW */ - DM814X_IOPAD(0x093C, PIN_INPUT_PULLUP | 0x80) /* GP1[6] */ - >; - }; - - usb0_pins: pinmux_usb0_pins { - pinctrl-single,pins = < - DM814X_IOPAD(0x0c34, PIN_OUTPUT | 0x1) /* USB0_DRVVBUS */ - >; - }; -}; - -/* USB0_ID pin state: SW10[1] = 0 cable detection, SW10[1] = 1 ID grounded */ -&usb0 { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_pins>; - dr_mode = "otg"; -}; - -&usb1_phy { - status = "disabled"; -}; - -&usb1 { - status = "disabled"; -}; diff --git a/sys/gnu/dts/arm/dra62x.dtsi b/sys/gnu/dts/arm/dra62x.dtsi deleted file mode 100644 index d3cbb4ea35a..00000000000 --- a/sys/gnu/dts/arm/dra62x.dtsi +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -#include "dm814x.dtsi" - -/ { - compatible = "ti,dra62x"; -}; - -/* Compared to dm814x, dra62x has different offsets for Ethernet */ -&mac { - reg = <0x4a100000 0x800 - 0x4a101200 0x100>; -}; - -&davinci_mdio { - reg = <0x4a101000 0x100>; -}; - -#include "dra62x-clocks.dtsi" diff --git a/sys/gnu/dts/arm/dra7-dspeve-thermal.dtsi b/sys/gnu/dts/arm/dra7-dspeve-thermal.dtsi deleted file mode 100644 index 1c39a8459b3..00000000000 --- a/sys/gnu/dts/arm/dra7-dspeve-thermal.dtsi +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Device Tree Source for DRA7x SoC DSPEVE thermal - * - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -#include - -dspeve_thermal: dspeve_thermal { - polling-delay-passive = <250>; /* milliseconds */ - polling-delay = <500>; /* milliseconds */ - - /* sensor ID */ - thermal-sensors = <&bandgap 3>; - - trips { - dspeve_crit: dspeve_crit { - temperature = <125000>; /* milliCelsius */ - hysteresis = <2000>; /* milliCelsius */ - type = "critical"; - }; - }; -}; diff --git a/sys/gnu/dts/arm/dra7-evm-common.dtsi b/sys/gnu/dts/arm/dra7-evm-common.dtsi deleted file mode 100644 index 82eeba8faef..00000000000 --- a/sys/gnu/dts/arm/dra7-evm-common.dtsi +++ /dev/null @@ -1,284 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ - */ - -#include -#include -#include - -/ { - chosen { - stdout-path = &uart1; - }; - - extcon_usb1: extcon_usb1 { - compatible = "linux,extcon-usb-gpio"; - id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>; - }; - - extcon_usb2: extcon_usb2 { - compatible = "linux,extcon-usb-gpio"; - id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>; - }; - - sound0: sound0 { - compatible = "simple-audio-card"; - simple-audio-card,name = "DRA7xx-EVM"; - simple-audio-card,widgets = - "Headphone", "Headphone Jack", - "Line", "Line Out", - "Microphone", "Mic Jack", - "Line", "Line In"; - simple-audio-card,routing = - "Headphone Jack", "HPLOUT", - "Headphone Jack", "HPROUT", - "Line Out", "LLOUT", - "Line Out", "RLOUT", - "MIC3L", "Mic Jack", - "MIC3R", "Mic Jack", - "Mic Jack", "Mic Bias", - "LINE1L", "Line In", - "LINE1R", "Line In"; - simple-audio-card,format = "dsp_b"; - simple-audio-card,bitclock-master = <&sound0_master>; - simple-audio-card,frame-master = <&sound0_master>; - simple-audio-card,bitclock-inversion; - - sound0_master: simple-audio-card,cpu { - sound-dai = <&mcasp3>; - system-clock-frequency = <5644800>; - }; - - simple-audio-card,codec { - sound-dai = <&tlv320aic3106>; - clocks = <&atl_clkin2_ck>; - }; - }; - - leds { - compatible = "gpio-leds"; - led0 { - label = "dra7:usr1"; - gpios = <&pcf_lcd 4 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led1 { - label = "dra7:usr2"; - gpios = <&pcf_lcd 5 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led2 { - label = "dra7:usr3"; - gpios = <&pcf_lcd 6 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led3 { - label = "dra7:usr4"; - gpios = <&pcf_lcd 7 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - autorepeat; - - USER1 { - label = "btnUser1"; - linux,code = ; - gpios = <&pcf_lcd 2 GPIO_ACTIVE_LOW>; - }; - - USER2 { - label = "btnUser2"; - linux,code = ; - gpios = <&pcf_lcd 3 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&i2c3 { - status = "okay"; - clock-frequency = <400000>; -}; - -&mcspi1 { - status = "okay"; -}; - -&mcspi2 { - status = "okay"; -}; - -&uart1 { - status = "okay"; - interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, - <&dra7_pmx_core 0x3e0>; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&qspi { - status = "okay"; - - spi-max-frequency = <76800000>; - m25p80@0 { - compatible = "s25fl256s1"; - spi-max-frequency = <76800000>; - reg = <0>; - spi-tx-bus-width = <1>; - spi-rx-bus-width = <4>; - #address-cells = <1>; - #size-cells = <1>; - - /* MTD partition table. - * The ROM checks the first four physical blocks - * for a valid file to boot and the flash here is - * 64KiB block size. - */ - partition@0 { - label = "QSPI.SPL"; - reg = <0x00000000 0x000010000>; - }; - partition@1 { - label = "QSPI.SPL.backup1"; - reg = <0x00010000 0x00010000>; - }; - partition@2 { - label = "QSPI.SPL.backup2"; - reg = <0x00020000 0x00010000>; - }; - partition@3 { - label = "QSPI.SPL.backup3"; - reg = <0x00030000 0x00010000>; - }; - partition@4 { - label = "QSPI.u-boot"; - reg = <0x00040000 0x00100000>; - }; - partition@5 { - label = "QSPI.u-boot-spl-os"; - reg = <0x00140000 0x00080000>; - }; - partition@6 { - label = "QSPI.u-boot-env"; - reg = <0x001c0000 0x00010000>; - }; - partition@7 { - label = "QSPI.u-boot-env.backup1"; - reg = <0x001d0000 0x0010000>; - }; - partition@8 { - label = "QSPI.kernel"; - reg = <0x001e0000 0x0800000>; - }; - partition@9 { - label = "QSPI.file-system"; - reg = <0x009e0000 0x01620000>; - }; - }; -}; - -&omap_dwc3_1 { - extcon = <&extcon_usb1>; -}; - -&usb1 { - dr_mode = "otg"; - extcon = <&extcon_usb1>; -}; - -&omap_dwc3_2 { - extcon = <&extcon_usb2>; -}; - -&usb2 { - dr_mode = "host"; - extcon = <&extcon_usb2>; -}; - -&atl { - assigned-clocks = <&abe_dpll_sys_clk_mux>, - <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>, - <&dpll_abe_ck>, - <&dpll_abe_m2x2_ck>, - <&atl_clkin2_ck>; - assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>; - assigned-clock-rates = <0>, <0>, <180633600>, <361267200>, <5644800>; - - status = "okay"; - - atl2 { - bws = ; - aws = ; - }; -}; - -&mcasp3 { - #sound-dai-cells = <0>; - - assigned-clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>; - assigned-clock-parents = <&atl_clkin2_ck>; - - status = "okay"; - - op-mode = <0>; /* MCASP_IIS_MODE */ - tdm-slots = <2>; - /* 4 serializer */ - serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ - 1 2 0 0 - >; - tx-num-evt = <32>; - rx-num-evt = <32>; -}; - -&mailbox5 { - status = "okay"; - mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { - status = "okay"; - }; - mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { - status = "okay"; - }; -}; - -&mailbox6 { - status = "okay"; - mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { - status = "okay"; - }; - mbox_dsp2_ipc3x: mbox_dsp2_ipc3x { - status = "okay"; - }; -}; - -&pcie1_rc { - status = "okay"; -}; - -&mmc4 { - bus-width = <4>; - cap-power-off-card; - keep-power-in-suspend; - non-removable; - #address-cells = <1>; - #size-cells = <0>; - wifi@2 { - compatible = "ti,wl1835"; - reg = <2>; - interrupt-parent = <&gpio5>; - interrupts = <7 IRQ_TYPE_EDGE_RISING>; - }; -}; diff --git a/sys/gnu/dts/arm/dra7-evm.dts b/sys/gnu/dts/arm/dra7-evm.dts deleted file mode 100644 index de7f85efaa5..00000000000 --- a/sys/gnu/dts/arm/dra7-evm.dts +++ /dev/null @@ -1,539 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ - */ -/dts-v1/; - -#include "dra74x.dtsi" -#include "dra7-evm-common.dtsi" -#include "dra74x-mmc-iodelay.dtsi" - -/ { - model = "TI DRA742"; - compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7"; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x80000000 0x0 0x60000000>; /* 1536 MB */ - }; - - evm_12v0: fixedregulator-evm_12v0 { - /* main supply */ - compatible = "regulator-fixed"; - regulator-name = "evm_12v0"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-always-on; - regulator-boot-on; - }; - - evm_1v8_sw: fixedregulator-evm_1v8 { - compatible = "regulator-fixed"; - regulator-name = "evm_1v8"; - vin-supply = <&smps9_reg>; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - evm_3v3_sd: fixedregulator-sd { - compatible = "regulator-fixed"; - regulator-name = "evm_3v3_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>; - }; - - evm_3v3_sw: fixedregulator-evm_3v3_sw { - compatible = "regulator-fixed"; - regulator-name = "evm_3v3_sw"; - vin-supply = <&sysen1>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - aic_dvdd: fixedregulator-aic_dvdd { - /* TPS77018DBVT */ - compatible = "regulator-fixed"; - regulator-name = "aic_dvdd"; - vin-supply = <&evm_3v3_sw>; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - evm_3v3: fixedregulator-evm3v3 { - /* Output of Cntlr A of TPS43351-Q1 on dra7-evm */ - compatible = "regulator-fixed"; - regulator-name = "evm_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&evm_12v0>; - regulator-always-on; - regulator-boot-on; - }; - - evm_5v0: fixedregulator-evm_5v0 { - /* Output of Cntlr B of TPS43351-Q1 on dra7-evm */ - compatible = "regulator-fixed"; - regulator-name = "evm_5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&evm_12v0>; - regulator-always-on; - regulator-boot-on; - }; - - evm_3v6: fixedregulator-evm_3v6 { - compatible = "regulator-fixed"; - regulator-name = "evm_3v6"; - regulator-min-microvolt = <3600000>; - regulator-max-microvolt = <3600000>; - vin-supply = <&evm_5v0>; - regulator-always-on; - regulator-boot-on; - }; - - vmmcwl_fixed: fixedregulator-mmcwl { - compatible = "regulator-fixed"; - regulator-name = "vmmcwl_fixed"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio5 8 0>; - startup-delay-us = <70000>; - enable-active-high; - }; - - vtt_fixed: fixedregulator-vtt { - compatible = "regulator-fixed"; - regulator-name = "vtt_fixed"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - vin-supply = <&sysen2>; - gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>; - }; - -}; - -&dra7_pmx_core { - dcan1_pins_default: dcan1_pins_default { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */ - DRA7XX_CORE_IOPAD(0x3818, PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */ - >; - }; - - dcan1_pins_sleep: dcan1_pins_sleep { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x37d0, MUX_MODE15 | PULL_UP) /* dcan1_tx.off */ - DRA7XX_CORE_IOPAD(0x3818, MUX_MODE15 | PULL_UP) /* wakeup0.off */ - >; - }; -}; - -&i2c1 { - status = "okay"; - clock-frequency = <400000>; - - tps659038: tps659038@58 { - compatible = "ti,tps659038"; - reg = <0x58>; - ti,palmas-override-powerhold; - ti,system-power-controller; - - tps659038_pmic { - compatible = "ti,tps659038-pmic"; - - regulators { - smps123_reg: smps123 { - /* VDD_MPU */ - regulator-name = "smps123"; - regulator-min-microvolt = < 850000>; - regulator-max-microvolt = <1250000>; - regulator-always-on; - regulator-boot-on; - }; - - smps45_reg: smps45 { - /* VDD_DSPEVE */ - regulator-name = "smps45"; - regulator-min-microvolt = < 850000>; - regulator-max-microvolt = <1250000>; - regulator-always-on; - regulator-boot-on; - }; - - smps6_reg: smps6 { - /* VDD_GPU - over VDD_SMPS6 */ - regulator-name = "smps6"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1250000>; - regulator-always-on; - regulator-boot-on; - }; - - smps7_reg: smps7 { - /* CORE_VDD */ - regulator-name = "smps7"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1150000>; - regulator-always-on; - regulator-boot-on; - }; - - smps8_reg: smps8 { - /* VDD_IVAHD */ - regulator-name = "smps8"; - regulator-min-microvolt = < 850000>; - regulator-max-microvolt = <1250000>; - regulator-always-on; - regulator-boot-on; - }; - - smps9_reg: smps9 { - /* VDDS1V8 */ - regulator-name = "smps9"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo1_reg: ldo1 { - /* LDO1_OUT --> SDIO */ - regulator-name = "ldo1"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo2_reg: ldo2 { - /* VDD_RTCIO */ - /* LDO2 -> VDDSHV5, LDO2 also goes to CAN_PHY_3V3 */ - regulator-name = "ldo2"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo3_reg: ldo3 { - /* VDDA_1V8_PHY */ - regulator-name = "ldo3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo9_reg: ldo9 { - /* VDD_RTC */ - regulator-name = "ldo9"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - regulator-always-on; - regulator-boot-on; - regulator-allow-bypass; - }; - - ldoln_reg: ldoln { - /* VDDA_1V8_PLL */ - regulator-name = "ldoln"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldousb_reg: ldousb { - /* VDDA_3V_USB: VDDA_USBHS33 */ - regulator-name = "ldousb"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; - - /* REGEN1 is unused */ - - regen2: regen2 { - /* Needed for PMIC internal resources */ - regulator-name = "regen2"; - regulator-boot-on; - regulator-always-on; - }; - - /* REGEN3 is unused */ - - sysen1: sysen1 { - /* PMIC_REGEN_3V3 */ - regulator-name = "sysen1"; - regulator-boot-on; - regulator-always-on; - }; - - sysen2: sysen2 { - /* PMIC_REGEN_DDR */ - regulator-name = "sysen2"; - regulator-boot-on; - regulator-always-on; - }; - }; - }; - }; - - pcf_lcd: gpio@20 { - compatible = "ti,pcf8575", "nxp,pcf8575"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&gpio6>; - interrupts = <11 IRQ_TYPE_EDGE_FALLING>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - pcf_gpio_21: gpio@21 { - compatible = "ti,pcf8575", "nxp,pcf8575"; - reg = <0x21>; - lines-initial-states = <0x1408>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&gpio6>; - interrupts = <11 IRQ_TYPE_EDGE_FALLING>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - tlv320aic3106: tlv320aic3106@19 { - #sound-dai-cells = <0>; - compatible = "ti,tlv320aic3106"; - reg = <0x19>; - adc-settle-ms = <40>; - ai3x-micbias-vg = <1>; /* 2.0V */ - status = "okay"; - - /* Regulators */ - AVDD-supply = <&evm_3v3_sw>; - IOVDD-supply = <&evm_3v3_sw>; - DRVDD-supply = <&evm_3v3_sw>; - DVDD-supply = <&aic_dvdd>; - }; -}; - -&i2c2 { - status = "okay"; - clock-frequency = <400000>; - - pcf_hdmi: gpio@26 { - compatible = "ti,pcf8575", "nxp,pcf8575"; - reg = <0x26>; - gpio-controller; - #gpio-cells = <2>; - p1 { - /* vin6_sel_s0: high: VIN6, low: audio */ - gpio-hog; - gpios = <1 GPIO_ACTIVE_HIGH>; - output-low; - line-name = "vin6_sel_s0"; - }; - }; -}; - -&mmc1 { - status = "okay"; - vmmc-supply = <&evm_3v3_sd>; - vqmmc-supply = <&ldo1_reg>; - bus-width = <4>; - /* - * SDCD signal is not being used here - using the fact that GPIO mode - * is always hardwired. - */ - cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; - pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50-rev11", "sdr104-rev11", "ddr50", "sdr104"; - pinctrl-0 = <&mmc1_pins_default>; - pinctrl-1 = <&mmc1_pins_hs>; - pinctrl-2 = <&mmc1_pins_sdr12>; - pinctrl-3 = <&mmc1_pins_sdr25>; - pinctrl-4 = <&mmc1_pins_sdr50>; - pinctrl-5 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr_rev11_conf>; - pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev11_conf>; - pinctrl-7 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr_rev20_conf>; - pinctrl-8 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>; -}; - -&mmc2 { - status = "okay"; - vmmc-supply = <&evm_1v8_sw>; - vqmmc-supply = <&evm_1v8_sw>; - bus-width = <8>; - non-removable; - pinctrl-names = "default", "hs", "ddr_1_8v-rev11", "ddr_1_8v", "hs200_1_8v-rev11", "hs200_1_8v"; - pinctrl-0 = <&mmc2_pins_default>; - pinctrl-1 = <&mmc2_pins_hs>; - pinctrl-2 = <&mmc2_pins_ddr_1_8v_rev11 &mmc2_iodelay_ddr_1_8v_rev11_conf>; - pinctrl-3 = <&mmc2_pins_ddr_rev20>; - pinctrl-4 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev11_conf>; - pinctrl-5 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev20_conf>; -}; - -&mmc4 { - status = "okay"; - vmmc-supply = <&evm_3v6>; - vqmmc-supply = <&vmmcwl_fixed>; - pinctrl-names = "default-rev11", "default", "hs-rev11", "hs", "sdr12-rev11", "sdr12", "sdr25-rev11", "sdr25"; - pinctrl-0 = <&mmc4_pins_default &mmc4_iodelay_ds_rev11_conf>; - pinctrl-1 = <&mmc4_pins_default &mmc4_iodelay_ds_rev20_conf>; - pinctrl-2 = <&mmc4_pins_hs &mmc4_iodelay_sdr12_hs_sdr25_rev11_conf>; - pinctrl-3 = <&mmc4_pins_hs &mmc4_iodelay_sdr12_hs_sdr25_rev20_conf>; - pinctrl-4 = <&mmc4_pins_sdr12 &mmc4_iodelay_sdr12_hs_sdr25_rev11_conf>; - pinctrl-5 = <&mmc4_pins_sdr12 &mmc4_iodelay_sdr12_hs_sdr25_rev20_conf>; - pinctrl-6 = <&mmc4_pins_sdr25 &mmc4_iodelay_sdr12_hs_sdr25_rev11_conf>; - pinctrl-7 = <&mmc4_pins_sdr25 &mmc4_iodelay_sdr12_hs_sdr25_rev20_conf>; -}; - -&cpu0 { - vdd-supply = <&smps123_reg>; -}; - -&elm { - status = "okay"; -}; - -&gpmc { - /* - * For the existing IOdelay configuration via U-Boot we don't - * support NAND on dra7-evm. Keep it disabled. Enabling it - * requires a different configuration by U-Boot. - */ - status = "disabled"; - ranges = <0 0 0x08000000 0x01000000>; /* minimum GPMC partition = 16MB */ - nand@0,0 { - compatible = "ti,omap2-nand"; - reg = <0 0 4>; /* device IO registers */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ - <1 IRQ_TYPE_NONE>; /* termcount */ - rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */ - ti,nand-xfer-type = "prefetch-dma"; - ti,nand-ecc-opt = "bch8"; - ti,elm-id = <&elm>; - nand-bus-width = <16>; - gpmc,device-width = <2>; - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <80>; - gpmc,cs-wr-off-ns = <80>; - gpmc,adv-on-ns = <0>; - gpmc,adv-rd-off-ns = <60>; - gpmc,adv-wr-off-ns = <60>; - gpmc,we-on-ns = <10>; - gpmc,we-off-ns = <50>; - gpmc,oe-on-ns = <4>; - gpmc,oe-off-ns = <40>; - gpmc,access-ns = <40>; - gpmc,wr-access-ns = <80>; - gpmc,rd-cycle-ns = <80>; - gpmc,wr-cycle-ns = <80>; - gpmc,bus-turnaround-ns = <0>; - gpmc,cycle2cycle-delay-ns = <0>; - gpmc,clk-activation-ns = <0>; - gpmc,wr-data-mux-bus-ns = <0>; - /* MTD partition table */ - /* All SPL-* partitions are sized to minimal length - * which can be independently programmable. For - * NAND flash this is equal to size of erase-block */ - #address-cells = <1>; - #size-cells = <1>; - partition@0 { - label = "NAND.SPL"; - reg = <0x00000000 0x000020000>; - }; - partition@1 { - label = "NAND.SPL.backup1"; - reg = <0x00020000 0x00020000>; - }; - partition@2 { - label = "NAND.SPL.backup2"; - reg = <0x00040000 0x00020000>; - }; - partition@3 { - label = "NAND.SPL.backup3"; - reg = <0x00060000 0x00020000>; - }; - partition@4 { - label = "NAND.u-boot-spl-os"; - reg = <0x00080000 0x00040000>; - }; - partition@5 { - label = "NAND.u-boot"; - reg = <0x000c0000 0x00100000>; - }; - partition@6 { - label = "NAND.u-boot-env"; - reg = <0x001c0000 0x00020000>; - }; - partition@7 { - label = "NAND.u-boot-env.backup1"; - reg = <0x001e0000 0x00020000>; - }; - partition@8 { - label = "NAND.kernel"; - reg = <0x00200000 0x00800000>; - }; - partition@9 { - label = "NAND.file-system"; - reg = <0x00a00000 0x0f600000>; - }; - }; -}; - -&usb2_phy1 { - phy-supply = <&ldousb_reg>; -}; - -&usb2_phy2 { - phy-supply = <&ldousb_reg>; -}; - -&gpio7_target { - ti,no-reset-on-init; - ti,no-idle-on-init; -}; - -&mac { - status = "okay"; - dual_emac; -}; - -&cpsw_emac0 { - phy-handle = <ðphy0>; - phy-mode = "rgmii"; - dual_emac_res_vlan = <1>; -}; - -&cpsw_emac1 { - phy-handle = <ðphy1>; - phy-mode = "rgmii"; - dual_emac_res_vlan = <2>; -}; - -&davinci_mdio { - ethphy0: ethernet-phy@2 { - reg = <2>; - }; - - ethphy1: ethernet-phy@3 { - reg = <3>; - }; -}; - -&dcan1 { - status = "ok"; - pinctrl-names = "default", "sleep", "active"; - pinctrl-0 = <&dcan1_pins_sleep>; - pinctrl-1 = <&dcan1_pins_sleep>; - pinctrl-2 = <&dcan1_pins_default>; -}; diff --git a/sys/gnu/dts/arm/dra7-iva-thermal.dtsi b/sys/gnu/dts/arm/dra7-iva-thermal.dtsi deleted file mode 100644 index dd74a5337d1..00000000000 --- a/sys/gnu/dts/arm/dra7-iva-thermal.dtsi +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Device Tree Source for DRA7x SoC IVA thermal - * - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -#include - -iva_thermal: iva_thermal { - polling-delay-passive = <250>; /* milliseconds */ - polling-delay = <500>; /* milliseconds */ - - /* sensor ID */ - thermal-sensors = <&bandgap 4>; - - trips { - iva_crit: iva_crit { - temperature = <125000>; /* milliCelsius */ - hysteresis = <2000>; /* milliCelsius */ - type = "critical"; - }; - }; -}; diff --git a/sys/gnu/dts/arm/dra7-l4.dtsi b/sys/gnu/dts/arm/dra7-l4.dtsi deleted file mode 100644 index 5cac2dd5824..00000000000 --- a/sys/gnu/dts/arm/dra7-l4.dtsi +++ /dev/null @@ -1,4554 +0,0 @@ -&l4_cfg { /* 0x4a000000 */ - compatible = "ti,dra7-l4-cfg", "simple-bus"; - reg = <0x4a000000 0x800>, - <0x4a000800 0x800>, - <0x4a001000 0x1000>; - reg-names = "ap", "la", "ia0"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x4a000000 0x100000>, /* segment 0 */ - <0x00100000 0x4a100000 0x100000>, /* segment 1 */ - <0x00200000 0x4a200000 0x100000>; /* segment 2 */ - - segment@0 { /* 0x4a000000 */ - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ - <0x00000800 0x00000800 0x000800>, /* ap 1 */ - <0x00001000 0x00001000 0x001000>, /* ap 2 */ - <0x00002000 0x00002000 0x002000>, /* ap 3 */ - <0x00004000 0x00004000 0x001000>, /* ap 4 */ - <0x00005000 0x00005000 0x001000>, /* ap 5 */ - <0x00006000 0x00006000 0x001000>, /* ap 6 */ - <0x00008000 0x00008000 0x002000>, /* ap 7 */ - <0x0000a000 0x0000a000 0x001000>, /* ap 8 */ - <0x00056000 0x00056000 0x001000>, /* ap 9 */ - <0x00057000 0x00057000 0x001000>, /* ap 10 */ - <0x0005e000 0x0005e000 0x002000>, /* ap 11 */ - <0x00060000 0x00060000 0x001000>, /* ap 12 */ - <0x00080000 0x00080000 0x008000>, /* ap 13 */ - <0x00088000 0x00088000 0x001000>, /* ap 14 */ - <0x000a0000 0x000a0000 0x008000>, /* ap 15 */ - <0x000a8000 0x000a8000 0x001000>, /* ap 16 */ - <0x000d9000 0x000d9000 0x001000>, /* ap 17 */ - <0x000da000 0x000da000 0x001000>, /* ap 18 */ - <0x000dd000 0x000dd000 0x001000>, /* ap 19 */ - <0x000de000 0x000de000 0x001000>, /* ap 20 */ - <0x000e0000 0x000e0000 0x001000>, /* ap 21 */ - <0x000e1000 0x000e1000 0x001000>, /* ap 22 */ - <0x000f4000 0x000f4000 0x001000>, /* ap 23 */ - <0x000f5000 0x000f5000 0x001000>, /* ap 24 */ - <0x000f6000 0x000f6000 0x001000>, /* ap 25 */ - <0x000f7000 0x000f7000 0x001000>, /* ap 26 */ - <0x00090000 0x00090000 0x008000>, /* ap 59 */ - <0x00098000 0x00098000 0x001000>; /* ap 60 */ - - target-module@2000 { /* 0x4a002000, ap 3 08.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x2000 0x4>; - reg-names = "rev"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2000 0x2000>; - - scm: scm@0 { - compatible = "ti,dra7-scm-core", "simple-bus"; - reg = <0 0x2000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x2000>; - - scm_conf: scm_conf@0 { - compatible = "syscon", "simple-bus"; - reg = <0x0 0x1400>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x0 0x1400>; - - pbias_regulator: pbias_regulator@e00 { - compatible = "ti,pbias-dra7", "ti,pbias-omap"; - reg = <0xe00 0x4>; - syscon = <&scm_conf>; - pbias_mmc_reg: pbias_mmc_omap5 { - regulator-name = "pbias_mmc_omap5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - }; - - phy_gmii_sel: phy-gmii-sel { - compatible = "ti,dra7xx-phy-gmii-sel"; - reg = <0x554 0x4>; - #phy-cells = <1>; - }; - - scm_conf_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - dra7_pmx_core: pinmux@1400 { - compatible = "ti,dra7-padconf", - "pinctrl-single"; - reg = <0x1400 0x0468>; - #address-cells = <1>; - #size-cells = <0>; - #pinctrl-cells = <1>; - #interrupt-cells = <1>; - interrupt-controller; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0x3fffffff>; - }; - - scm_conf1: scm_conf@1c04 { - compatible = "syscon"; - reg = <0x1c04 0x0020>; - #syscon-cells = <2>; - }; - - scm_conf_pcie: scm_conf@1c24 { - compatible = "syscon"; - reg = <0x1c24 0x0024>; - }; - - sdma_xbar: dma-router@b78 { - compatible = "ti,dra7-dma-crossbar"; - reg = <0xb78 0xfc>; - #dma-cells = <1>; - dma-requests = <205>; - ti,dma-safe-map = <0>; - dma-masters = <&sdma>; - }; - - edma_xbar: dma-router@c78 { - compatible = "ti,dra7-dma-crossbar"; - reg = <0xc78 0x7c>; - #dma-cells = <2>; - dma-requests = <204>; - ti,dma-safe-map = <0>; - dma-masters = <&edma>; - }; - }; - }; - - target-module@5000 { /* 0x4a005000, ap 5 10.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x5000 0x4>; - reg-names = "rev"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x5000 0x1000>; - - cm_core_aon: cm_core_aon@0 { - compatible = "ti,dra7-cm-core-aon", - "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0 0x2000>; - ranges = <0 0 0x2000>; - - cm_core_aon_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - cm_core_aon_clockdomains: clockdomains { - }; - }; - }; - - target-module@8000 { /* 0x4a008000, ap 7 0e.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x8000 0x4>; - reg-names = "rev"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x8000 0x2000>; - - cm_core: cm_core@0 { - compatible = "ti,dra7-cm-core", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0 0x3000>; - ranges = <0 0 0x3000>; - - cm_core_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - cm_core_clockdomains: clockdomains { - }; - }; - }; - - target-module@56000 { /* 0x4a056000, ap 9 02.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "dma_system"; - reg = <0x56000 0x4>, - <0x5602c 0x4>, - <0x56028 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_EMUFREE | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-midle = , - , - , - ; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): core_pwrdm, dma_clkdm */ - clocks = <&dma_clkctrl DRA7_DMA_DMA_SYSTEM_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x56000 0x1000>; - - sdma: dma-controller@0 { - compatible = "ti,omap4430-sdma"; - reg = <0x0 0x1000>; - interrupts = , - , - , - ; - #dma-cells = <1>; - dma-channels = <32>; - dma-requests = <127>; - }; - }; - - target-module@5e000 { /* 0x4a05e000, ap 11 1a.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x5e000 0x2000>; - }; - - target-module@80000 { /* 0x4a080000, ap 13 20.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "ocp2scp1"; - reg = <0x80000 0x4>, - <0x80010 0x4>, - <0x80014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): l3init_pwrdm, l3init_clkdm */ - clocks = <&l3init_clkctrl DRA7_L3INIT_OCP2SCP1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x80000 0x8000>; - - ocp2scp@0 { - compatible = "ti,omap-ocp2scp"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x8000>; - reg = <0x0 0x20>; - - usb2_phy1: phy@4000 { - compatible = "ti,dra7x-usb2", "ti,omap-usb2"; - reg = <0x4000 0x400>; - syscon-phy-power = <&scm_conf 0x300>; - clocks = <&usb_phy1_always_on_clk32k>, - <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS1_CLKCTRL 8>; - clock-names = "wkupclk", - "refclk"; - #phy-cells = <0>; - }; - - usb2_phy2: phy@5000 { - compatible = "ti,dra7x-usb2-phy2", - "ti,omap-usb2"; - reg = <0x5000 0x400>; - syscon-phy-power = <&scm_conf 0xe74>; - clocks = <&usb_phy2_always_on_clk32k>, - <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS2_CLKCTRL 8>; - clock-names = "wkupclk", - "refclk"; - #phy-cells = <0>; - }; - - usb3_phy1: phy@4400 { - compatible = "ti,omap-usb3"; - reg = <0x4400 0x80>, - <0x4800 0x64>, - <0x4c00 0x40>; - reg-names = "phy_rx", "phy_tx", "pll_ctrl"; - syscon-phy-power = <&scm_conf 0x370>; - clocks = <&usb_phy3_always_on_clk32k>, - <&sys_clkin1>, - <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS1_CLKCTRL 8>; - clock-names = "wkupclk", - "sysclk", - "refclk"; - #phy-cells = <0>; - }; - }; - }; - - target-module@90000 { /* 0x4a090000, ap 59 42.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "ocp2scp3"; - reg = <0x90000 0x4>, - <0x90010 0x4>, - <0x90014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): l3init_pwrdm, l3init_clkdm */ - clocks = <&l3init_clkctrl DRA7_L3INIT_OCP2SCP3_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x90000 0x8000>; - - ocp2scp@0 { - compatible = "ti,omap-ocp2scp"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x8000>; - reg = <0x0 0x20>; - - pcie1_phy: pciephy@4000 { - compatible = "ti,phy-pipe3-pcie"; - reg = <0x4000 0x80>, /* phy_rx */ - <0x4400 0x64>; /* phy_tx */ - reg-names = "phy_rx", "phy_tx"; - syscon-phy-power = <&scm_conf_pcie 0x1c>; - syscon-pcs = <&scm_conf_pcie 0x10>; - clocks = <&dpll_pcie_ref_ck>, - <&dpll_pcie_ref_m2ldo_ck>, - <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 8>, - <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 9>, - <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 10>, - <&optfclk_pciephy_div>, - <&sys_clkin1>; - clock-names = "dpll_ref", "dpll_ref_m2", - "wkupclk", "refclk", - "div-clk", "phy-div", "sysclk"; - #phy-cells = <0>; - }; - - pcie2_phy: pciephy@5000 { - compatible = "ti,phy-pipe3-pcie"; - reg = <0x5000 0x80>, /* phy_rx */ - <0x5400 0x64>; /* phy_tx */ - reg-names = "phy_rx", "phy_tx"; - syscon-phy-power = <&scm_conf_pcie 0x20>; - syscon-pcs = <&scm_conf_pcie 0x10>; - clocks = <&dpll_pcie_ref_ck>, - <&dpll_pcie_ref_m2ldo_ck>, - <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 8>, - <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 9>, - <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 10>, - <&optfclk_pciephy_div>, - <&sys_clkin1>; - clock-names = "dpll_ref", "dpll_ref_m2", - "wkupclk", "refclk", - "div-clk", "phy-div", "sysclk"; - #phy-cells = <0>; - status = "disabled"; - }; - - sata_phy: phy@6000 { - compatible = "ti,phy-pipe3-sata"; - reg = <0x6000 0x80>, /* phy_rx */ - <0x6400 0x64>, /* phy_tx */ - <0x6800 0x40>; /* pll_ctrl */ - reg-names = "phy_rx", "phy_tx", "pll_ctrl"; - syscon-phy-power = <&scm_conf 0x374>; - clocks = <&sys_clkin1>, - <&l3init_clkctrl DRA7_L3INIT_SATA_CLKCTRL 8>; - clock-names = "sysclk", "refclk"; - syscon-pllreset = <&scm_conf 0x3fc>; - #phy-cells = <0>; - }; - }; - }; - - target-module@a0000 { /* 0x4a0a0000, ap 15 40.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xa0000 0x8000>; - }; - - target-module@d9000 { /* 0x4a0d9000, ap 17 72.0 */ - compatible = "ti,sysc-omap4-sr", "ti,sysc"; - ti,hwmods = "smartreflex_mpu"; - reg = <0xd9038 0x4>; - reg-names = "sysc"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): coreaon_pwrdm, coreaon_clkdm */ - clocks = <&coreaon_clkctrl DRA7_COREAON_SMARTREFLEX_MPU_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xd9000 0x1000>; - - /* SmartReflex child device marked reserved in TRM */ - }; - - target-module@dd000 { /* 0x4a0dd000, ap 19 18.0 */ - compatible = "ti,sysc-omap4-sr", "ti,sysc"; - ti,hwmods = "smartreflex_core"; - reg = <0xdd038 0x4>; - reg-names = "sysc"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): coreaon_pwrdm, coreaon_clkdm */ - clocks = <&coreaon_clkctrl DRA7_COREAON_SMARTREFLEX_CORE_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xdd000 0x1000>; - - /* SmartReflex child device marked reserved in TRM */ - }; - - target-module@e0000 { /* 0x4a0e0000, ap 21 28.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xe0000 0x1000>; - }; - - target-module@f4000 { /* 0x4a0f4000, ap 23 04.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - ti,hwmods = "mailbox1"; - reg = <0xf4000 0x4>, - <0xf4010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - ; - /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ - clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xf4000 0x1000>; - - mailbox1: mailbox@0 { - compatible = "ti,omap4-mailbox"; - reg = <0x0 0x200>; - interrupts = , - , - ; - #mbox-cells = <1>; - ti,mbox-num-users = <3>; - ti,mbox-num-fifos = <8>; - status = "disabled"; - }; - }; - - target-module@f6000 { /* 0x4a0f6000, ap 25 78.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "spinlock"; - reg = <0xf6000 0x4>, - <0xf6010 0x4>, - <0xf6014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ - clocks = <&l4cfg_clkctrl DRA7_L4CFG_SPINLOCK_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xf6000 0x1000>; - - hwspinlock: spinlock@0 { - compatible = "ti,omap4-hwspinlock"; - reg = <0x0 0x1000>; - #hwlock-cells = <1>; - }; - }; - }; - - segment@100000 { /* 0x4a100000 */ - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00002000 0x00102000 0x001000>, /* ap 27 */ - <0x00003000 0x00103000 0x001000>, /* ap 28 */ - <0x00008000 0x00108000 0x001000>, /* ap 29 */ - <0x00009000 0x00109000 0x001000>, /* ap 30 */ - <0x00040000 0x00140000 0x010000>, /* ap 31 */ - <0x00050000 0x00150000 0x001000>, /* ap 32 */ - <0x00051000 0x00151000 0x001000>, /* ap 33 */ - <0x00052000 0x00152000 0x001000>, /* ap 34 */ - <0x00053000 0x00153000 0x001000>, /* ap 35 */ - <0x00054000 0x00154000 0x001000>, /* ap 36 */ - <0x00055000 0x00155000 0x001000>, /* ap 37 */ - <0x00056000 0x00156000 0x001000>, /* ap 38 */ - <0x00057000 0x00157000 0x001000>, /* ap 39 */ - <0x00058000 0x00158000 0x001000>, /* ap 40 */ - <0x0005b000 0x0015b000 0x001000>, /* ap 41 */ - <0x0005c000 0x0015c000 0x001000>, /* ap 42 */ - <0x0005d000 0x0015d000 0x001000>, /* ap 45 */ - <0x0005e000 0x0015e000 0x001000>, /* ap 46 */ - <0x0005f000 0x0015f000 0x001000>, /* ap 47 */ - <0x00060000 0x00160000 0x001000>, /* ap 48 */ - <0x00061000 0x00161000 0x001000>, /* ap 49 */ - <0x00062000 0x00162000 0x001000>, /* ap 50 */ - <0x00063000 0x00163000 0x001000>, /* ap 51 */ - <0x00064000 0x00164000 0x001000>, /* ap 52 */ - <0x00065000 0x00165000 0x001000>, /* ap 53 */ - <0x00066000 0x00166000 0x001000>, /* ap 54 */ - <0x00067000 0x00167000 0x001000>, /* ap 55 */ - <0x00068000 0x00168000 0x001000>, /* ap 56 */ - <0x0006d000 0x0016d000 0x001000>, /* ap 57 */ - <0x0006e000 0x0016e000 0x001000>, /* ap 58 */ - <0x00071000 0x00171000 0x001000>, /* ap 61 */ - <0x00072000 0x00172000 0x001000>, /* ap 62 */ - <0x00073000 0x00173000 0x001000>, /* ap 63 */ - <0x00074000 0x00174000 0x001000>, /* ap 64 */ - <0x00075000 0x00175000 0x001000>, /* ap 65 */ - <0x00076000 0x00176000 0x001000>, /* ap 66 */ - <0x00077000 0x00177000 0x001000>, /* ap 67 */ - <0x00078000 0x00178000 0x001000>, /* ap 68 */ - <0x00081000 0x00181000 0x001000>, /* ap 69 */ - <0x00082000 0x00182000 0x001000>, /* ap 70 */ - <0x00083000 0x00183000 0x001000>, /* ap 71 */ - <0x00084000 0x00184000 0x001000>, /* ap 72 */ - <0x00085000 0x00185000 0x001000>, /* ap 73 */ - <0x00086000 0x00186000 0x001000>, /* ap 74 */ - <0x00087000 0x00187000 0x001000>, /* ap 75 */ - <0x00088000 0x00188000 0x001000>, /* ap 76 */ - <0x00069000 0x00169000 0x001000>, /* ap 103 */ - <0x0006a000 0x0016a000 0x001000>, /* ap 104 */ - <0x00079000 0x00179000 0x001000>, /* ap 105 */ - <0x0007a000 0x0017a000 0x001000>, /* ap 106 */ - <0x0006b000 0x0016b000 0x001000>, /* ap 107 */ - <0x0006c000 0x0016c000 0x001000>, /* ap 108 */ - <0x0007b000 0x0017b000 0x001000>, /* ap 121 */ - <0x0007c000 0x0017c000 0x001000>, /* ap 122 */ - <0x0007d000 0x0017d000 0x001000>, /* ap 123 */ - <0x0007e000 0x0017e000 0x001000>, /* ap 124 */ - <0x00059000 0x00159000 0x001000>, /* ap 125 */ - <0x0005a000 0x0015a000 0x001000>; /* ap 126 */ - - target-module@2000 { /* 0x4a102000, ap 27 3c.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2000 0x1000>; - }; - - target-module@8000 { /* 0x4a108000, ap 29 1e.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x8000 0x1000>; - }; - - target-module@40000 { /* 0x4a140000, ap 31 06.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x40000 0x10000>; - }; - - target-module@51000 { /* 0x4a151000, ap 33 50.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x51000 0x1000>; - }; - - target-module@53000 { /* 0x4a153000, ap 35 54.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x53000 0x1000>; - }; - - target-module@55000 { /* 0x4a155000, ap 37 46.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x55000 0x1000>; - }; - - target-module@57000 { /* 0x4a157000, ap 39 58.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x57000 0x1000>; - }; - - target-module@59000 { /* 0x4a159000, ap 125 6a.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x59000 0x1000>; - }; - - target-module@5b000 { /* 0x4a15b000, ap 41 60.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x5b000 0x1000>; - }; - - target-module@5d000 { /* 0x4a15d000, ap 45 3a.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x5d000 0x1000>; - }; - - target-module@5f000 { /* 0x4a15f000, ap 47 56.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x5f000 0x1000>; - }; - - target-module@61000 { /* 0x4a161000, ap 49 32.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x61000 0x1000>; - }; - - target-module@63000 { /* 0x4a163000, ap 51 5c.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x63000 0x1000>; - }; - - target-module@65000 { /* 0x4a165000, ap 53 4e.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x65000 0x1000>; - }; - - target-module@67000 { /* 0x4a167000, ap 55 5e.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x67000 0x1000>; - }; - - target-module@69000 { /* 0x4a169000, ap 103 4a.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x69000 0x1000>; - }; - - target-module@6b000 { /* 0x4a16b000, ap 107 52.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x6b000 0x1000>; - }; - - target-module@6d000 { /* 0x4a16d000, ap 57 68.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x6d000 0x1000>; - }; - - target-module@71000 { /* 0x4a171000, ap 61 48.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x71000 0x1000>; - }; - - target-module@73000 { /* 0x4a173000, ap 63 2a.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x73000 0x1000>; - }; - - target-module@75000 { /* 0x4a175000, ap 65 64.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x75000 0x1000>; - }; - - target-module@77000 { /* 0x4a177000, ap 67 66.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x77000 0x1000>; - }; - - target-module@79000 { /* 0x4a179000, ap 105 34.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x79000 0x1000>; - }; - - target-module@7b000 { /* 0x4a17b000, ap 121 7c.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x7b000 0x1000>; - }; - - target-module@7d000 { /* 0x4a17d000, ap 123 7e.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x7d000 0x1000>; - }; - - target-module@81000 { /* 0x4a181000, ap 69 26.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x81000 0x1000>; - }; - - target-module@83000 { /* 0x4a183000, ap 71 2e.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x83000 0x1000>; - }; - - target-module@85000 { /* 0x4a185000, ap 73 36.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x85000 0x1000>; - }; - - target-module@87000 { /* 0x4a187000, ap 75 74.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x87000 0x1000>; - }; - }; - - segment@200000 { /* 0x4a200000 */ - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00018000 0x00218000 0x001000>, /* ap 43 */ - <0x00019000 0x00219000 0x001000>, /* ap 44 */ - <0x00000000 0x00200000 0x001000>, /* ap 77 */ - <0x00001000 0x00201000 0x001000>, /* ap 78 */ - <0x0000a000 0x0020a000 0x001000>, /* ap 79 */ - <0x0000b000 0x0020b000 0x001000>, /* ap 80 */ - <0x0000c000 0x0020c000 0x001000>, /* ap 81 */ - <0x0000d000 0x0020d000 0x001000>, /* ap 82 */ - <0x0000e000 0x0020e000 0x001000>, /* ap 83 */ - <0x0000f000 0x0020f000 0x001000>, /* ap 84 */ - <0x00010000 0x00210000 0x001000>, /* ap 85 */ - <0x00011000 0x00211000 0x001000>, /* ap 86 */ - <0x00012000 0x00212000 0x001000>, /* ap 87 */ - <0x00013000 0x00213000 0x001000>, /* ap 88 */ - <0x00014000 0x00214000 0x001000>, /* ap 89 */ - <0x00015000 0x00215000 0x001000>, /* ap 90 */ - <0x0002a000 0x0022a000 0x001000>, /* ap 91 */ - <0x0002b000 0x0022b000 0x001000>, /* ap 92 */ - <0x0001c000 0x0021c000 0x001000>, /* ap 93 */ - <0x0001d000 0x0021d000 0x001000>, /* ap 94 */ - <0x0001e000 0x0021e000 0x001000>, /* ap 95 */ - <0x0001f000 0x0021f000 0x001000>, /* ap 96 */ - <0x00020000 0x00220000 0x001000>, /* ap 97 */ - <0x00021000 0x00221000 0x001000>, /* ap 98 */ - <0x00024000 0x00224000 0x001000>, /* ap 99 */ - <0x00025000 0x00225000 0x001000>, /* ap 100 */ - <0x00026000 0x00226000 0x001000>, /* ap 101 */ - <0x00027000 0x00227000 0x001000>, /* ap 102 */ - <0x0002c000 0x0022c000 0x001000>, /* ap 109 */ - <0x0002d000 0x0022d000 0x001000>, /* ap 110 */ - <0x0002e000 0x0022e000 0x001000>, /* ap 111 */ - <0x0002f000 0x0022f000 0x001000>, /* ap 112 */ - <0x00030000 0x00230000 0x001000>, /* ap 113 */ - <0x00031000 0x00231000 0x001000>, /* ap 114 */ - <0x00032000 0x00232000 0x001000>, /* ap 115 */ - <0x00033000 0x00233000 0x001000>, /* ap 116 */ - <0x00034000 0x00234000 0x001000>, /* ap 117 */ - <0x00035000 0x00235000 0x001000>, /* ap 118 */ - <0x00036000 0x00236000 0x001000>, /* ap 119 */ - <0x00037000 0x00237000 0x001000>, /* ap 120 */ - <0x0001a000 0x0021a000 0x001000>, /* ap 127 */ - <0x0001b000 0x0021b000 0x001000>; /* ap 128 */ - - target-module@0 { /* 0x4a200000, ap 77 3e.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x1000>; - }; - - target-module@a000 { /* 0x4a20a000, ap 79 30.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xa000 0x1000>; - }; - - target-module@c000 { /* 0x4a20c000, ap 81 0c.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xc000 0x1000>; - }; - - target-module@e000 { /* 0x4a20e000, ap 83 22.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xe000 0x1000>; - }; - - target-module@10000 { /* 0x4a210000, ap 85 14.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x10000 0x1000>; - }; - - target-module@12000 { /* 0x4a212000, ap 87 16.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x12000 0x1000>; - }; - - target-module@14000 { /* 0x4a214000, ap 89 1c.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x14000 0x1000>; - }; - - target-module@18000 { /* 0x4a218000, ap 43 12.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x18000 0x1000>; - }; - - target-module@1a000 { /* 0x4a21a000, ap 127 7a.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x1a000 0x1000>; - }; - - target-module@1c000 { /* 0x4a21c000, ap 93 38.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x1c000 0x1000>; - }; - - target-module@1e000 { /* 0x4a21e000, ap 95 0a.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x1e000 0x1000>; - }; - - target-module@20000 { /* 0x4a220000, ap 97 24.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x20000 0x1000>; - }; - - target-module@24000 { /* 0x4a224000, ap 99 44.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x24000 0x1000>; - }; - - target-module@26000 { /* 0x4a226000, ap 101 2c.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x26000 0x1000>; - }; - - target-module@2a000 { /* 0x4a22a000, ap 91 4c.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2a000 0x1000>; - }; - - target-module@2c000 { /* 0x4a22c000, ap 109 6c.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2c000 0x1000>; - }; - - target-module@2e000 { /* 0x4a22e000, ap 111 6e.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2e000 0x1000>; - }; - - target-module@30000 { /* 0x4a230000, ap 113 70.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x30000 0x1000>; - }; - - target-module@32000 { /* 0x4a232000, ap 115 5a.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x32000 0x1000>; - }; - - target-module@34000 { /* 0x4a234000, ap 117 76.1 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x34000 0x1000>; - }; - - target-module@36000 { /* 0x4a236000, ap 119 62.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x36000 0x1000>; - }; - }; -}; - -&l4_per1 { /* 0x48000000 */ - compatible = "ti,dra7-l4-per1", "simple-bus"; - reg = <0x48000000 0x800>, - <0x48000800 0x800>, - <0x48001000 0x400>, - <0x48001400 0x400>, - <0x48001800 0x400>, - <0x48001c00 0x400>; - reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x48000000 0x200000>, /* segment 0 */ - <0x00200000 0x48200000 0x200000>; /* segment 1 */ - - segment@0 { /* 0x48000000 */ - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ - <0x00001000 0x00001000 0x000400>, /* ap 1 */ - <0x00000800 0x00000800 0x000800>, /* ap 2 */ - <0x00020000 0x00020000 0x001000>, /* ap 3 */ - <0x00021000 0x00021000 0x001000>, /* ap 4 */ - <0x00032000 0x00032000 0x001000>, /* ap 5 */ - <0x00033000 0x00033000 0x001000>, /* ap 6 */ - <0x00034000 0x00034000 0x001000>, /* ap 7 */ - <0x00035000 0x00035000 0x001000>, /* ap 8 */ - <0x00036000 0x00036000 0x001000>, /* ap 9 */ - <0x00037000 0x00037000 0x001000>, /* ap 10 */ - <0x0003e000 0x0003e000 0x001000>, /* ap 11 */ - <0x0003f000 0x0003f000 0x001000>, /* ap 12 */ - <0x00055000 0x00055000 0x001000>, /* ap 13 */ - <0x00056000 0x00056000 0x001000>, /* ap 14 */ - <0x00057000 0x00057000 0x001000>, /* ap 15 */ - <0x00058000 0x00058000 0x001000>, /* ap 16 */ - <0x00059000 0x00059000 0x001000>, /* ap 17 */ - <0x0005a000 0x0005a000 0x001000>, /* ap 18 */ - <0x0005b000 0x0005b000 0x001000>, /* ap 19 */ - <0x0005c000 0x0005c000 0x001000>, /* ap 20 */ - <0x0005d000 0x0005d000 0x001000>, /* ap 21 */ - <0x0005e000 0x0005e000 0x001000>, /* ap 22 */ - <0x00060000 0x00060000 0x001000>, /* ap 23 */ - <0x0006a000 0x0006a000 0x001000>, /* ap 24 */ - <0x0006b000 0x0006b000 0x001000>, /* ap 25 */ - <0x0006c000 0x0006c000 0x001000>, /* ap 26 */ - <0x0006d000 0x0006d000 0x001000>, /* ap 27 */ - <0x0006e000 0x0006e000 0x001000>, /* ap 28 */ - <0x0006f000 0x0006f000 0x001000>, /* ap 29 */ - <0x00070000 0x00070000 0x001000>, /* ap 30 */ - <0x00071000 0x00071000 0x001000>, /* ap 31 */ - <0x00072000 0x00072000 0x001000>, /* ap 32 */ - <0x00073000 0x00073000 0x001000>, /* ap 33 */ - <0x00061000 0x00061000 0x001000>, /* ap 34 */ - <0x00053000 0x00053000 0x001000>, /* ap 35 */ - <0x00054000 0x00054000 0x001000>, /* ap 36 */ - <0x000b2000 0x000b2000 0x001000>, /* ap 37 */ - <0x000b3000 0x000b3000 0x001000>, /* ap 38 */ - <0x00078000 0x00078000 0x001000>, /* ap 39 */ - <0x00079000 0x00079000 0x001000>, /* ap 40 */ - <0x00086000 0x00086000 0x001000>, /* ap 41 */ - <0x00087000 0x00087000 0x001000>, /* ap 42 */ - <0x00088000 0x00088000 0x001000>, /* ap 43 */ - <0x00089000 0x00089000 0x001000>, /* ap 44 */ - <0x00051000 0x00051000 0x001000>, /* ap 45 */ - <0x00052000 0x00052000 0x001000>, /* ap 46 */ - <0x00098000 0x00098000 0x001000>, /* ap 47 */ - <0x00099000 0x00099000 0x001000>, /* ap 48 */ - <0x0009a000 0x0009a000 0x001000>, /* ap 49 */ - <0x0009b000 0x0009b000 0x001000>, /* ap 50 */ - <0x0009c000 0x0009c000 0x001000>, /* ap 51 */ - <0x0009d000 0x0009d000 0x001000>, /* ap 52 */ - <0x00068000 0x00068000 0x001000>, /* ap 53 */ - <0x00069000 0x00069000 0x001000>, /* ap 54 */ - <0x00090000 0x00090000 0x002000>, /* ap 55 */ - <0x00092000 0x00092000 0x001000>, /* ap 56 */ - <0x000a4000 0x000a4000 0x001000>, /* ap 57 */ - <0x000a6000 0x000a6000 0x001000>, /* ap 58 */ - <0x000a8000 0x000a8000 0x004000>, /* ap 59 */ - <0x000ac000 0x000ac000 0x001000>, /* ap 60 */ - <0x000ad000 0x000ad000 0x001000>, /* ap 61 */ - <0x000ae000 0x000ae000 0x001000>, /* ap 62 */ - <0x00066000 0x00066000 0x001000>, /* ap 63 */ - <0x00067000 0x00067000 0x001000>, /* ap 64 */ - <0x000b4000 0x000b4000 0x001000>, /* ap 65 */ - <0x000b5000 0x000b5000 0x001000>, /* ap 66 */ - <0x000b8000 0x000b8000 0x001000>, /* ap 67 */ - <0x000b9000 0x000b9000 0x001000>, /* ap 68 */ - <0x000ba000 0x000ba000 0x001000>, /* ap 69 */ - <0x000bb000 0x000bb000 0x001000>, /* ap 70 */ - <0x000d1000 0x000d1000 0x001000>, /* ap 71 */ - <0x000d2000 0x000d2000 0x001000>, /* ap 72 */ - <0x000d5000 0x000d5000 0x001000>, /* ap 73 */ - <0x000d6000 0x000d6000 0x001000>, /* ap 74 */ - <0x000a2000 0x000a2000 0x001000>, /* ap 75 */ - <0x000a3000 0x000a3000 0x001000>, /* ap 76 */ - <0x00001400 0x00001400 0x000400>, /* ap 77 */ - <0x00001800 0x00001800 0x000400>, /* ap 78 */ - <0x00001c00 0x00001c00 0x000400>, /* ap 79 */ - <0x000a5000 0x000a5000 0x001000>, /* ap 80 */ - <0x0007a000 0x0007a000 0x001000>, /* ap 81 */ - <0x0007b000 0x0007b000 0x001000>, /* ap 82 */ - <0x0007c000 0x0007c000 0x001000>, /* ap 83 */ - <0x0007d000 0x0007d000 0x001000>; /* ap 84 */ - - target-module@20000 { /* 0x48020000, ap 3 04.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x20050 0x4>, - <0x20054 0x4>, - <0x20058 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl DRA7_L4PER_UART3_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x20000 0x1000>; - - uart3: serial@0 { - compatible = "ti,dra742-uart", "ti,omap4-uart"; - reg = <0x0 0x100>; - interrupts = ; - clock-frequency = <48000000>; - status = "disabled"; - dmas = <&sdma_xbar 53>, <&sdma_xbar 54>; - dma-names = "tx", "rx"; - }; - }; - - target-module@32000 { /* 0x48032000, ap 5 3e.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - ti,hwmods = "timer2"; - reg = <0x32000 0x4>, - <0x32010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl DRA7_L4PER_TIMER2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x32000 0x1000>; - - timer2: timer@0 { - compatible = "ti,omap5430-timer"; - reg = <0x0 0x80>; - clocks = <&l4per_clkctrl DRA7_L4PER_TIMER2_CLKCTRL 24>; - clock-names = "fck"; - interrupts = ; - }; - }; - - target-module@34000 { /* 0x48034000, ap 7 46.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - ti,hwmods = "timer3"; - reg = <0x34000 0x4>, - <0x34010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl DRA7_L4PER_TIMER3_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x34000 0x1000>; - - timer3: timer@0 { - compatible = "ti,omap5430-timer"; - reg = <0x0 0x80>; - clocks = <&l4per_clkctrl DRA7_L4PER_TIMER3_CLKCTRL 24>; - clock-names = "fck"; - interrupts = ; - }; - }; - - target-module@36000 { /* 0x48036000, ap 9 4e.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - ti,hwmods = "timer4"; - reg = <0x36000 0x4>, - <0x36010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl DRA7_L4PER_TIMER4_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x36000 0x1000>; - - timer4: timer@0 { - compatible = "ti,omap5430-timer"; - reg = <0x0 0x80>; - clocks = <&l4per_clkctrl DRA7_L4PER_TIMER4_CLKCTRL 24>; - clock-names = "fck"; - interrupts = ; - }; - }; - - target-module@3e000 { /* 0x4803e000, ap 11 56.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - ti,hwmods = "timer9"; - reg = <0x3e000 0x4>, - <0x3e010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl DRA7_L4PER_TIMER9_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x3e000 0x1000>; - - timer9: timer@0 { - compatible = "ti,omap5430-timer"; - reg = <0x0 0x80>; - clocks = <&l4per_clkctrl DRA7_L4PER_TIMER9_CLKCTRL 24>; - clock-names = "fck"; - interrupts = ; - }; - }; - - gpio7_target: target-module@51000 { /* 0x48051000, ap 45 2e.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x51000 0x4>, - <0x51010 0x4>, - <0x51114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl DRA7_L4PER_GPIO7_CLKCTRL 0>, - <&l4per_clkctrl DRA7_L4PER_GPIO7_CLKCTRL 8>; - clock-names = "fck", "dbclk"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x51000 0x1000>; - - gpio7: gpio@0 { - compatible = "ti,omap4-gpio"; - reg = <0x0 0x200>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - target-module@53000 { /* 0x48053000, ap 35 36.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x53000 0x4>, - <0x53010 0x4>, - <0x53114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl DRA7_L4PER_GPIO8_CLKCTRL 0>, - <&l4per_clkctrl DRA7_L4PER_GPIO8_CLKCTRL 8>; - clock-names = "fck", "dbclk"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x53000 0x1000>; - - gpio8: gpio@0 { - compatible = "ti,omap4-gpio"; - reg = <0x0 0x200>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - target-module@55000 { /* 0x48055000, ap 13 0e.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x55000 0x4>, - <0x55010 0x4>, - <0x55114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl DRA7_L4PER_GPIO2_CLKCTRL 0>, - <&l4per_clkctrl DRA7_L4PER_GPIO2_CLKCTRL 8>; - clock-names = "fck", "dbclk"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x55000 0x1000>; - - gpio2: gpio@0 { - compatible = "ti,omap4-gpio"; - reg = <0x0 0x200>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - target-module@57000 { /* 0x48057000, ap 15 06.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x57000 0x4>, - <0x57010 0x4>, - <0x57114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl DRA7_L4PER_GPIO3_CLKCTRL 0>, - <&l4per_clkctrl DRA7_L4PER_GPIO3_CLKCTRL 8>; - clock-names = "fck", "dbclk"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x57000 0x1000>; - - gpio3: gpio@0 { - compatible = "ti,omap4-gpio"; - reg = <0x0 0x200>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - target-module@59000 { /* 0x48059000, ap 17 16.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x59000 0x4>, - <0x59010 0x4>, - <0x59114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl DRA7_L4PER_GPIO4_CLKCTRL 0>, - <&l4per_clkctrl DRA7_L4PER_GPIO4_CLKCTRL 8>; - clock-names = "fck", "dbclk"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x59000 0x1000>; - - gpio4: gpio@0 { - compatible = "ti,omap4-gpio"; - reg = <0x0 0x200>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - target-module@5b000 { /* 0x4805b000, ap 19 1e.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x5b000 0x4>, - <0x5b010 0x4>, - <0x5b114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl DRA7_L4PER_GPIO5_CLKCTRL 0>, - <&l4per_clkctrl DRA7_L4PER_GPIO5_CLKCTRL 8>; - clock-names = "fck", "dbclk"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x5b000 0x1000>; - - gpio5: gpio@0 { - compatible = "ti,omap4-gpio"; - reg = <0x0 0x200>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - target-module@5d000 { /* 0x4805d000, ap 21 26.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x5d000 0x4>, - <0x5d010 0x4>, - <0x5d114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl DRA7_L4PER_GPIO6_CLKCTRL 0>, - <&l4per_clkctrl DRA7_L4PER_GPIO6_CLKCTRL 8>; - clock-names = "fck", "dbclk"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x5d000 0x1000>; - - gpio6: gpio@0 { - compatible = "ti,omap4-gpio"; - reg = <0x0 0x200>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - target-module@60000 { /* 0x48060000, ap 23 32.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x60000 0x8>, - <0x60010 0x8>, - <0x60090 0x8>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl DRA7_L4PER_I2C3_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x60000 0x1000>; - - i2c3: i2c@0 { - compatible = "ti,omap4-i2c"; - reg = <0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - target-module@66000 { /* 0x48066000, ap 63 14.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x66050 0x4>, - <0x66054 0x4>, - <0x66058 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl DRA7_L4PER_UART5_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x66000 0x1000>; - - uart5: serial@0 { - compatible = "ti,dra742-uart", "ti,omap4-uart"; - reg = <0x0 0x100>; - interrupts = ; - clock-frequency = <48000000>; - status = "disabled"; - dmas = <&sdma_xbar 63>, <&sdma_xbar 64>; - dma-names = "tx", "rx"; - }; - }; - - target-module@68000 { /* 0x48068000, ap 53 1c.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x68050 0x4>, - <0x68054 0x4>, - <0x68058 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): ipu_pwrdm, ipu_clkdm */ - clocks = <&ipu_clkctrl DRA7_IPU_UART6_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x68000 0x1000>; - - uart6: serial@0 { - compatible = "ti,dra742-uart", "ti,omap4-uart"; - reg = <0x0 0x100>; - interrupts = ; - clock-frequency = <48000000>; - status = "disabled"; - dmas = <&sdma_xbar 79>, <&sdma_xbar 80>; - dma-names = "tx", "rx"; - }; - }; - - target-module@6a000 { /* 0x4806a000, ap 24 24.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x6a050 0x4>, - <0x6a054 0x4>, - <0x6a058 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl DRA7_L4PER_UART1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x6a000 0x1000>; - - uart1: serial@0 { - compatible = "ti,dra742-uart", "ti,omap4-uart"; - reg = <0x0 0x100>; - interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <48000000>; - status = "disabled"; - dmas = <&sdma_xbar 49>, <&sdma_xbar 50>; - dma-names = "tx", "rx"; - }; - }; - - target-module@6c000 { /* 0x4806c000, ap 26 2c.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x6c050 0x4>, - <0x6c054 0x4>, - <0x6c058 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl DRA7_L4PER_UART2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x6c000 0x1000>; - - uart2: serial@0 { - compatible = "ti,dra742-uart", "ti,omap4-uart"; - reg = <0x0 0x100>; - interrupts = ; - clock-frequency = <48000000>; - status = "disabled"; - dmas = <&sdma_xbar 51>, <&sdma_xbar 52>; - dma-names = "tx", "rx"; - }; - }; - - target-module@6e000 { /* 0x4806e000, ap 28 0c.1 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x6e050 0x4>, - <0x6e054 0x4>, - <0x6e058 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl DRA7_L4PER_UART4_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x6e000 0x1000>; - - uart4: serial@0 { - compatible = "ti,dra742-uart", "ti,omap4-uart"; - reg = <0x0 0x100>; - interrupts = ; - clock-frequency = <48000000>; - status = "disabled"; - dmas = <&sdma_xbar 55>, <&sdma_xbar 56>; - dma-names = "tx", "rx"; - }; - }; - - target-module@70000 { /* 0x48070000, ap 30 22.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x70000 0x8>, - <0x70010 0x8>, - <0x70090 0x8>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl DRA7_L4PER_I2C1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x70000 0x1000>; - - i2c1: i2c@0 { - compatible = "ti,omap4-i2c"; - reg = <0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - target-module@72000 { /* 0x48072000, ap 32 2a.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x72000 0x8>, - <0x72010 0x8>, - <0x72090 0x8>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl DRA7_L4PER_I2C2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x72000 0x1000>; - - i2c2: i2c@0 { - compatible = "ti,omap4-i2c"; - reg = <0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - target-module@78000 { /* 0x48078000, ap 39 0a.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "elm"; - reg = <0x78000 0x4>, - <0x78010 0x4>, - <0x78014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl DRA7_L4PER_ELM_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x78000 0x1000>; - - elm: elm@0 { - compatible = "ti,am3352-elm"; - reg = <0x0 0xfc0>; /* device IO registers */ - interrupts = ; - status = "disabled"; - }; - }; - - target-module@7a000 { /* 0x4807a000, ap 81 3a.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x7a000 0x8>, - <0x7a010 0x8>, - <0x7a090 0x8>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl DRA7_L4PER_I2C4_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x7a000 0x1000>; - - i2c4: i2c@0 { - compatible = "ti,omap4-i2c"; - reg = <0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - target-module@7c000 { /* 0x4807c000, ap 83 4a.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x7c000 0x8>, - <0x7c010 0x8>, - <0x7c090 0x8>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): ipu_pwrdm, ipu_clkdm */ - clocks = <&ipu_clkctrl DRA7_IPU_I2C5_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x7c000 0x1000>; - - i2c5: i2c@0 { - compatible = "ti,omap4-i2c"; - reg = <0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - target-module@86000 { /* 0x48086000, ap 41 5e.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - ti,hwmods = "timer10"; - reg = <0x86000 0x4>, - <0x86010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl DRA7_L4PER_TIMER10_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x86000 0x1000>; - - timer10: timer@0 { - compatible = "ti,omap5430-timer"; - reg = <0x0 0x80>; - clocks = <&l4per_clkctrl DRA7_L4PER_TIMER10_CLKCTRL 24>; - clock-names = "fck"; - interrupts = ; - }; - }; - - target-module@88000 { /* 0x48088000, ap 43 66.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - ti,hwmods = "timer11"; - reg = <0x88000 0x4>, - <0x88010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl DRA7_L4PER_TIMER11_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x88000 0x1000>; - - timer11: timer@0 { - compatible = "ti,omap5430-timer"; - reg = <0x0 0x80>; - clocks = <&l4per_clkctrl DRA7_L4PER_TIMER11_CLKCTRL 24>; - clock-names = "fck"; - interrupts = ; - }; - }; - - target-module@90000 { /* 0x48090000, ap 55 12.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "rng"; - reg = <0x91fe0 0x4>, - <0x91fe4 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = ; - ti,sysc-sidle = , - ; - /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */ - clocks = <&l4sec_clkctrl DRA7_L4SEC_RNG_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x90000 0x2000>; - - rng: rng@0 { - compatible = "ti,omap4-rng"; - reg = <0x0 0x2000>; - interrupts = ; - clocks = <&l3_iclk_div>; - clock-names = "fck"; - }; - }; - - target-module@98000 { /* 0x48098000, ap 47 08.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x98000 0x4>, - <0x98010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x98000 0x1000>; - - mcspi1: spi@0 { - compatible = "ti,omap4-mcspi"; - reg = <0x0 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - ti,spi-num-cs = <4>; - dmas = <&sdma_xbar 35>, - <&sdma_xbar 36>, - <&sdma_xbar 37>, - <&sdma_xbar 38>, - <&sdma_xbar 39>, - <&sdma_xbar 40>, - <&sdma_xbar 41>, - <&sdma_xbar 42>; - dma-names = "tx0", "rx0", "tx1", "rx1", - "tx2", "rx2", "tx3", "rx3"; - status = "disabled"; - }; - }; - - target-module@9a000 { /* 0x4809a000, ap 49 10.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x9a000 0x4>, - <0x9a010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x9a000 0x1000>; - - mcspi2: spi@0 { - compatible = "ti,omap4-mcspi"; - reg = <0x0 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - ti,spi-num-cs = <2>; - dmas = <&sdma_xbar 43>, - <&sdma_xbar 44>, - <&sdma_xbar 45>, - <&sdma_xbar 46>; - dma-names = "tx0", "rx0", "tx1", "rx1"; - status = "disabled"; - }; - }; - - target-module@9c000 { /* 0x4809c000, ap 51 38.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x9c000 0x4>, - <0x9c010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-midle = , - , - , - ; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): l3init_pwrdm, l3init_clkdm */ - clocks = <&l3init_clkctrl DRA7_L3INIT_MMC1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x9c000 0x1000>; - - mmc1: mmc@0 { - compatible = "ti,dra7-sdhci"; - reg = <0x0 0x400>; - interrupts = ; - status = "disabled"; - pbias-supply = <&pbias_mmc_reg>; - max-frequency = <192000000>; - mmc-ddr-1_8v; - mmc-ddr-3_3v; - }; - }; - - target-module@a2000 { /* 0x480a2000, ap 75 02.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xa2000 0x1000>; - }; - - target-module@a4000 { /* 0x480a4000, ap 57 42.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x000a4000 0x00001000>, - <0x00001000 0x000a5000 0x00001000>; - }; - - target-module@a8000 { /* 0x480a8000, ap 59 1a.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xa8000 0x4000>; - }; - - target-module@ad000 { /* 0x480ad000, ap 61 20.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0xad000 0x4>, - <0xad010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-midle = , - , - , - ; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl DRA7_L4PER_MMC3_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xad000 0x1000>; - - mmc3: mmc@0 { - compatible = "ti,dra7-sdhci"; - reg = <0x0 0x400>; - interrupts = ; - status = "disabled"; - /* Errata i887 limits max-frequency of MMC3 to 64 MHz */ - max-frequency = <64000000>; - /* SDMA is not supported */ - sdhci-caps-mask = <0x0 0x400000>; - }; - }; - - target-module@b2000 { /* 0x480b2000, ap 37 52.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "hdq1w"; - reg = <0xb2000 0x4>, - <0xb2014 0x4>, - <0xb2018 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,syss-mask = <1>; - ti,no-reset-on-init; - /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl DRA7_L4PER_HDQ1W_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xb2000 0x1000>; - - hdqw1w: 1w@0 { - compatible = "ti,omap3-1w"; - reg = <0x0 0x1000>; - interrupts = ; - }; - }; - - target-module@b4000 { /* 0x480b4000, ap 65 40.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0xb4000 0x4>, - <0xb4010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-midle = , - , - , - ; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): l3init_pwrdm, l3init_clkdm */ - clocks = <&l3init_clkctrl DRA7_L3INIT_MMC2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xb4000 0x1000>; - - mmc2: mmc@0 { - compatible = "ti,dra7-sdhci"; - reg = <0x0 0x400>; - interrupts = ; - status = "disabled"; - max-frequency = <192000000>; - /* SDR104/DDR50/SDR50 bits in CAPA2 is not supported */ - sdhci-caps-mask = <0x7 0x0>; - mmc-hs200-1_8v; - mmc-ddr-1_8v; - mmc-ddr-3_3v; - }; - }; - - target-module@b8000 { /* 0x480b8000, ap 67 48.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0xb8000 0x4>, - <0xb8010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI3_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xb8000 0x1000>; - - mcspi3: spi@0 { - compatible = "ti,omap4-mcspi"; - reg = <0x0 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - ti,spi-num-cs = <2>; - dmas = <&sdma_xbar 15>, <&sdma_xbar 16>; - dma-names = "tx0", "rx0"; - status = "disabled"; - }; - }; - - target-module@ba000 { /* 0x480ba000, ap 69 18.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0xba000 0x4>, - <0xba010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI4_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xba000 0x1000>; - - mcspi4: spi@0 { - compatible = "ti,omap4-mcspi"; - reg = <0x0 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - ti,spi-num-cs = <1>; - dmas = <&sdma_xbar 70>, <&sdma_xbar 71>; - dma-names = "tx0", "rx0"; - status = "disabled"; - }; - }; - - target-module@d1000 { /* 0x480d1000, ap 71 28.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0xd1000 0x4>, - <0xd1010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-midle = , - , - , - ; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl DRA7_L4PER_MMC4_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xd1000 0x1000>; - - mmc4: mmc@0 { - compatible = "ti,dra7-sdhci"; - reg = <0x0 0x400>; - interrupts = ; - status = "disabled"; - max-frequency = <192000000>; - /* SDMA is not supported */ - sdhci-caps-mask = <0x0 0x400000>; - }; - }; - - target-module@d5000 { /* 0x480d5000, ap 73 30.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xd5000 0x1000>; - }; - }; - - segment@200000 { /* 0x48200000 */ - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - }; -}; - -&l4_per2 { /* 0x48400000 */ - compatible = "ti,dra7-l4-per2", "simple-bus"; - reg = <0x48400000 0x800>, - <0x48400800 0x800>, - <0x48401000 0x400>, - <0x48401400 0x400>, - <0x48401800 0x400>; - reg-names = "ap", "la", "ia0", "ia1", "ia2"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x48400000 0x400000>, /* segment 0 */ - <0x45800000 0x45800000 0x400000>, /* L3 data port */ - <0x45c00000 0x45c00000 0x400000>, /* L3 data port */ - <0x46000000 0x46000000 0x400000>, /* L3 data port */ - <0x48436000 0x48436000 0x400000>, /* L3 data port */ - <0x4843a000 0x4843a000 0x400000>, /* L3 data port */ - <0x4844c000 0x4844c000 0x400000>, /* L3 data port */ - <0x48450000 0x48450000 0x400000>, /* L3 data port */ - <0x48454000 0x48454000 0x400000>; /* L3 data port */ - - segment@0 { /* 0x48400000 */ - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ - <0x00001000 0x00001000 0x000400>, /* ap 1 */ - <0x00000800 0x00000800 0x000800>, /* ap 2 */ - <0x00084000 0x00084000 0x004000>, /* ap 3 */ - <0x00001400 0x00001400 0x000400>, /* ap 4 */ - <0x00001800 0x00001800 0x000400>, /* ap 5 */ - <0x00088000 0x00088000 0x001000>, /* ap 6 */ - <0x0002c000 0x0002c000 0x001000>, /* ap 7 */ - <0x0002d000 0x0002d000 0x001000>, /* ap 8 */ - <0x00060000 0x00060000 0x002000>, /* ap 9 */ - <0x00062000 0x00062000 0x001000>, /* ap 10 */ - <0x00064000 0x00064000 0x002000>, /* ap 11 */ - <0x00066000 0x00066000 0x001000>, /* ap 12 */ - <0x00068000 0x00068000 0x002000>, /* ap 13 */ - <0x0006a000 0x0006a000 0x001000>, /* ap 14 */ - <0x0006c000 0x0006c000 0x002000>, /* ap 15 */ - <0x0006e000 0x0006e000 0x001000>, /* ap 16 */ - <0x00036000 0x00036000 0x001000>, /* ap 17 */ - <0x00037000 0x00037000 0x001000>, /* ap 18 */ - <0x00070000 0x00070000 0x002000>, /* ap 19 */ - <0x00072000 0x00072000 0x001000>, /* ap 20 */ - <0x0003a000 0x0003a000 0x001000>, /* ap 21 */ - <0x0003b000 0x0003b000 0x001000>, /* ap 22 */ - <0x0003c000 0x0003c000 0x001000>, /* ap 23 */ - <0x0003d000 0x0003d000 0x001000>, /* ap 24 */ - <0x0003e000 0x0003e000 0x001000>, /* ap 25 */ - <0x0003f000 0x0003f000 0x001000>, /* ap 26 */ - <0x00040000 0x00040000 0x001000>, /* ap 27 */ - <0x00041000 0x00041000 0x001000>, /* ap 28 */ - <0x00042000 0x00042000 0x001000>, /* ap 29 */ - <0x00043000 0x00043000 0x001000>, /* ap 30 */ - <0x00080000 0x00080000 0x002000>, /* ap 31 */ - <0x00082000 0x00082000 0x001000>, /* ap 32 */ - <0x0004a000 0x0004a000 0x001000>, /* ap 33 */ - <0x0004b000 0x0004b000 0x001000>, /* ap 34 */ - <0x00074000 0x00074000 0x002000>, /* ap 35 */ - <0x00076000 0x00076000 0x001000>, /* ap 36 */ - <0x00050000 0x00050000 0x001000>, /* ap 37 */ - <0x00051000 0x00051000 0x001000>, /* ap 38 */ - <0x00078000 0x00078000 0x002000>, /* ap 39 */ - <0x0007a000 0x0007a000 0x001000>, /* ap 40 */ - <0x00054000 0x00054000 0x001000>, /* ap 41 */ - <0x00055000 0x00055000 0x001000>, /* ap 42 */ - <0x0007c000 0x0007c000 0x002000>, /* ap 43 */ - <0x0007e000 0x0007e000 0x001000>, /* ap 44 */ - <0x0004c000 0x0004c000 0x001000>, /* ap 45 */ - <0x0004d000 0x0004d000 0x001000>, /* ap 46 */ - <0x00020000 0x00020000 0x001000>, /* ap 47 */ - <0x00021000 0x00021000 0x001000>, /* ap 48 */ - <0x00022000 0x00022000 0x001000>, /* ap 49 */ - <0x00023000 0x00023000 0x001000>, /* ap 50 */ - <0x00024000 0x00024000 0x001000>, /* ap 51 */ - <0x00025000 0x00025000 0x001000>, /* ap 52 */ - <0x00046000 0x00046000 0x001000>, /* ap 53 */ - <0x00047000 0x00047000 0x001000>, /* ap 54 */ - <0x00048000 0x00048000 0x001000>, /* ap 55 */ - <0x00049000 0x00049000 0x001000>, /* ap 56 */ - <0x00058000 0x00058000 0x002000>, /* ap 57 */ - <0x0005a000 0x0005a000 0x001000>, /* ap 58 */ - <0x0005b000 0x0005b000 0x001000>, /* ap 59 */ - <0x0005c000 0x0005c000 0x001000>, /* ap 60 */ - <0x0005d000 0x0005d000 0x001000>, /* ap 61 */ - <0x0005e000 0x0005e000 0x001000>, /* ap 62 */ - <0x45800000 0x45800000 0x400000>, /* L3 data port */ - <0x45c00000 0x45c00000 0x400000>, /* L3 data port */ - <0x46000000 0x46000000 0x400000>, /* L3 data port */ - <0x48436000 0x48436000 0x400000>, /* L3 data port */ - <0x4843a000 0x4843a000 0x400000>, /* L3 data port */ - <0x4844c000 0x4844c000 0x400000>, /* L3 data port */ - <0x48450000 0x48450000 0x400000>, /* L3 data port */ - <0x48454000 0x48454000 0x400000>; /* L3 data port */ - - target-module@20000 { /* 0x48420000, ap 47 02.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x20050 0x4>, - <0x20054 0x4>, - <0x20058 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ - clocks = <&l4per2_clkctrl DRA7_L4PER2_UART7_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x20000 0x1000>; - - uart7: serial@0 { - compatible = "ti,dra742-uart", "ti,omap4-uart"; - reg = <0x0 0x100>; - interrupts = ; - clock-frequency = <48000000>; - status = "disabled"; - }; - }; - - target-module@22000 { /* 0x48422000, ap 49 0a.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x22050 0x4>, - <0x22054 0x4>, - <0x22058 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ - clocks = <&l4per2_clkctrl DRA7_L4PER2_UART8_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x22000 0x1000>; - - uart8: serial@0 { - compatible = "ti,dra742-uart", "ti,omap4-uart"; - reg = <0x0 0x100>; - interrupts = ; - clock-frequency = <48000000>; - status = "disabled"; - }; - }; - - target-module@24000 { /* 0x48424000, ap 51 12.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x24050 0x4>, - <0x24054 0x4>, - <0x24058 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ - clocks = <&l4per2_clkctrl DRA7_L4PER2_UART9_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x24000 0x1000>; - - uart9: serial@0 { - compatible = "ti,dra742-uart", "ti,omap4-uart"; - reg = <0x0 0x100>; - interrupts = ; - clock-frequency = <48000000>; - status = "disabled"; - }; - }; - - target-module@2c000 { /* 0x4842c000, ap 7 18.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2c000 0x1000>; - }; - - target-module@36000 { /* 0x48436000, ap 17 06.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x36000 0x1000>; - }; - - target-module@3a000 { /* 0x4843a000, ap 21 3e.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x3a000 0x1000>; - }; - - atl_tm: target-module@3c000 { /* 0x4843c000, ap 23 08.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x3c000 0x4>; - reg-names = "rev"; - clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x3c000 0x1000>; - - atl: atl@0 { - compatible = "ti,dra7-atl"; - reg = <0x0 0x3ff>; - ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>, - <&atl_clkin2_ck>, <&atl_clkin3_ck>; - clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>; - clock-names = "fck"; - status = "disabled"; - }; - }; - - target-module@3e000 { /* 0x4843e000, ap 25 30.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - ti,hwmods = "epwmss0"; - reg = <0x3e000 0x4>, - <0x3e004 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - ; - /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ - clocks = <&l4per2_clkctrl DRA7_L4PER2_EPWMSS0_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x3e000 0x1000>; - - epwmss0: epwmss@0 { - compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss"; - reg = <0x0 0x30>; - #address-cells = <1>; - #size-cells = <1>; - status = "disabled"; - ranges = <0 0 0x1000>; - - ecap0: ecap@100 { - compatible = "ti,dra746-ecap", - "ti,am3352-ecap"; - #pwm-cells = <3>; - reg = <0x100 0x80>; - clocks = <&l4_root_clk_div>; - clock-names = "fck"; - status = "disabled"; - }; - - ehrpwm0: pwm@200 { - compatible = "ti,dra746-ehrpwm", - "ti,am3352-ehrpwm"; - #pwm-cells = <3>; - reg = <0x200 0x80>; - clocks = <&ehrpwm0_tbclk>, <&l4_root_clk_div>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - }; - }; - - target-module@40000 { /* 0x48440000, ap 27 38.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - ti,hwmods = "epwmss1"; - reg = <0x40000 0x4>, - <0x40004 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - ; - /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ - clocks = <&l4per2_clkctrl DRA7_L4PER2_EPWMSS1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x40000 0x1000>; - - epwmss1: epwmss@0 { - compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss"; - reg = <0x0 0x30>; - #address-cells = <1>; - #size-cells = <1>; - status = "disabled"; - ranges = <0 0 0x1000>; - - ecap1: ecap@100 { - compatible = "ti,dra746-ecap", - "ti,am3352-ecap"; - #pwm-cells = <3>; - reg = <0x100 0x80>; - clocks = <&l4_root_clk_div>; - clock-names = "fck"; - status = "disabled"; - }; - - ehrpwm1: pwm@200 { - compatible = "ti,dra746-ehrpwm", - "ti,am3352-ehrpwm"; - #pwm-cells = <3>; - reg = <0x200 0x80>; - clocks = <&ehrpwm1_tbclk>, <&l4_root_clk_div>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - }; - }; - - target-module@42000 { /* 0x48442000, ap 29 20.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - ti,hwmods = "epwmss2"; - reg = <0x42000 0x4>, - <0x42004 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - ; - /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ - clocks = <&l4per2_clkctrl DRA7_L4PER2_EPWMSS2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x42000 0x1000>; - - epwmss2: epwmss@0 { - compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss"; - reg = <0x0 0x30>; - #address-cells = <1>; - #size-cells = <1>; - status = "disabled"; - ranges = <0 0 0x1000>; - - ecap2: ecap@100 { - compatible = "ti,dra746-ecap", - "ti,am3352-ecap"; - #pwm-cells = <3>; - reg = <0x100 0x80>; - clocks = <&l4_root_clk_div>; - clock-names = "fck"; - status = "disabled"; - }; - - ehrpwm2: pwm@200 { - compatible = "ti,dra746-ehrpwm", - "ti,am3352-ehrpwm"; - #pwm-cells = <3>; - reg = <0x200 0x80>; - clocks = <&ehrpwm2_tbclk>, <&l4_root_clk_div>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - }; - }; - - target-module@46000 { /* 0x48446000, ap 53 40.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x46000 0x1000>; - }; - - target-module@48000 { /* 0x48448000, ap 55 48.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x48000 0x1000>; - }; - - target-module@4a000 { /* 0x4844a000, ap 33 1a.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x4a000 0x1000>; - }; - - target-module@4c000 { /* 0x4844c000, ap 45 1c.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x4c000 0x1000>; - }; - - target-module@50000 { /* 0x48450000, ap 37 24.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x50000 0x1000>; - }; - - target-module@54000 { /* 0x48454000, ap 41 2c.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x54000 0x1000>; - }; - - target-module@58000 { /* 0x48458000, ap 57 28.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x58000 0x2000>; - }; - - target-module@5b000 { /* 0x4845b000, ap 59 46.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x5b000 0x1000>; - }; - - target-module@5d000 { /* 0x4845d000, ap 61 22.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x5d000 0x1000>; - }; - - target-module@60000 { /* 0x48460000, ap 9 0e.0 */ - compatible = "ti,sysc-dra7-mcasp", "ti,sysc"; - reg = <0x60000 0x4>, - <0x60004 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-sidle = , - , - ; - /* Domains (P, C): ipu_pwrdm, ipu_clkdm */ - clocks = <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 0>, - <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 24>, - <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 28>; - clock-names = "fck", "ahclkx", "ahclkr"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x60000 0x2000>, - <0x45800000 0x45800000 0x400000>; - - mcasp1: mcasp@0 { - compatible = "ti,dra7-mcasp-audio"; - reg = <0x0 0x2000>, - <0x45800000 0x1000>; /* L3 data port */ - reg-names = "mpu","dat"; - interrupts = , - ; - interrupt-names = "tx", "rx"; - dmas = <&edma_xbar 129 1>, <&edma_xbar 128 1>; - dma-names = "tx", "rx"; - clocks = <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 0>, - <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 24>, - <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 28>; - clock-names = "fck", "ahclkx", "ahclkr"; - status = "disabled"; - }; - }; - - target-module@64000 { /* 0x48464000, ap 11 1e.0 */ - compatible = "ti,sysc-dra7-mcasp", "ti,sysc"; - reg = <0x64000 0x4>, - <0x64004 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-sidle = , - , - ; - /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ - clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 0>, - <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 24>, - <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 28>; - clock-names = "fck", "ahclkx", "ahclkr"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x64000 0x2000>, - <0x45c00000 0x45c00000 0x400000>; - - mcasp2: mcasp@0 { - compatible = "ti,dra7-mcasp-audio"; - reg = <0x0 0x2000>, - <0x45c00000 0x1000>; /* L3 data port */ - reg-names = "mpu","dat"; - interrupts = , - ; - interrupt-names = "tx", "rx"; - dmas = <&edma_xbar 131 1>, <&edma_xbar 130 1>; - dma-names = "tx", "rx"; - clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 0>, - <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 24>, - <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 28>; - clock-names = "fck", "ahclkx", "ahclkr"; - status = "disabled"; - }; - }; - - target-module@68000 { /* 0x48468000, ap 13 26.0 */ - compatible = "ti,sysc-dra7-mcasp", "ti,sysc"; - reg = <0x68000 0x4>, - <0x68004 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-sidle = , - , - ; - /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ - clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 0>, - <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>; - clock-names = "fck", "ahclkx"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x68000 0x2000>, - <0x46000000 0x46000000 0x400000>; - - mcasp3: mcasp@0 { - compatible = "ti,dra7-mcasp-audio"; - reg = <0x0 0x2000>, - <0x46000000 0x1000>; /* L3 data port */ - reg-names = "mpu","dat"; - interrupts = , - ; - interrupt-names = "tx", "rx"; - dmas = <&edma_xbar 133 1>, <&edma_xbar 132 1>; - dma-names = "tx", "rx"; - clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 0>, - <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>; - clock-names = "fck", "ahclkx"; - status = "disabled"; - }; - }; - - target-module@6c000 { /* 0x4846c000, ap 15 2e.0 */ - compatible = "ti,sysc-dra7-mcasp", "ti,sysc"; - reg = <0x6c000 0x4>, - <0x6c004 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-sidle = , - , - ; - /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ - clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 0>, - <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 24>; - clock-names = "fck", "ahclkx"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x6c000 0x2000>, - <0x48436000 0x48436000 0x400000>; - - mcasp4: mcasp@0 { - compatible = "ti,dra7-mcasp-audio"; - reg = <0x0 0x2000>, - <0x48436000 0x1000>; /* L3 data port */ - reg-names = "mpu","dat"; - interrupts = , - ; - interrupt-names = "tx", "rx"; - dmas = <&edma_xbar 135 1>, <&edma_xbar 134 1>; - dma-names = "tx", "rx"; - clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 0>, - <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 24>; - clock-names = "fck", "ahclkx"; - status = "disabled"; - }; - }; - - target-module@70000 { /* 0x48470000, ap 19 36.0 */ - compatible = "ti,sysc-dra7-mcasp", "ti,sysc"; - reg = <0x70000 0x4>, - <0x70004 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-sidle = , - , - ; - /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ - clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 0>, - <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 24>; - clock-names = "fck", "ahclkx"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x70000 0x2000>, - <0x4843a000 0x4843a000 0x400000>; - - mcasp5: mcasp@0 { - compatible = "ti,dra7-mcasp-audio"; - reg = <0x0 0x2000>, - <0x4843a000 0x1000>; /* L3 data port */ - reg-names = "mpu","dat"; - interrupts = , - ; - interrupt-names = "tx", "rx"; - dmas = <&edma_xbar 137 1>, <&edma_xbar 136 1>; - dma-names = "tx", "rx"; - clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 0>, - <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 24>; - clock-names = "fck", "ahclkx"; - status = "disabled"; - }; - }; - - target-module@74000 { /* 0x48474000, ap 35 14.0 */ - compatible = "ti,sysc-dra7-mcasp", "ti,sysc"; - reg = <0x74000 0x4>, - <0x74004 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-sidle = , - , - ; - /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ - clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 0>, - <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 24>; - clock-names = "fck", "ahclkx"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x74000 0x2000>, - <0x4844c000 0x4844c000 0x400000>; - - mcasp6: mcasp@0 { - compatible = "ti,dra7-mcasp-audio"; - reg = <0x0 0x2000>, - <0x4844c000 0x1000>; /* L3 data port */ - reg-names = "mpu","dat"; - interrupts = , - ; - interrupt-names = "tx", "rx"; - dmas = <&edma_xbar 139 1>, <&edma_xbar 138 1>; - dma-names = "tx", "rx"; - clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 0>, - <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 24>; - clock-names = "fck", "ahclkx"; - status = "disabled"; - }; - }; - - target-module@78000 { /* 0x48478000, ap 39 0c.0 */ - compatible = "ti,sysc-dra7-mcasp", "ti,sysc"; - reg = <0x78000 0x4>, - <0x78004 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-sidle = , - , - ; - /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ - clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 0>, - <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 24>; - clock-names = "fck", "ahclkx"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x78000 0x2000>, - <0x48450000 0x48450000 0x400000>; - - mcasp7: mcasp@0 { - compatible = "ti,dra7-mcasp-audio"; - reg = <0x0 0x2000>, - <0x48450000 0x1000>; /* L3 data port */ - reg-names = "mpu","dat"; - interrupts = , - ; - interrupt-names = "tx", "rx"; - dmas = <&edma_xbar 141 1>, <&edma_xbar 140 1>; - dma-names = "tx", "rx"; - clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 0>, - <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 24>; - clock-names = "fck", "ahclkx"; - status = "disabled"; - }; - }; - - target-module@7c000 { /* 0x4847c000, ap 43 04.0 */ - compatible = "ti,sysc-dra7-mcasp", "ti,sysc"; - reg = <0x7c000 0x4>, - <0x7c004 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-sidle = , - , - ; - /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ - clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 0>, - <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 24>; - clock-names = "fck", "ahclkx"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x7c000 0x2000>, - <0x48454000 0x48454000 0x400000>; - - mcasp8: mcasp@0 { - compatible = "ti,dra7-mcasp-audio"; - reg = <0x0 0x2000>, - <0x48454000 0x1000>; /* L3 data port */ - reg-names = "mpu","dat"; - interrupts = , - ; - interrupt-names = "tx", "rx"; - dmas = <&edma_xbar 143 1>, <&edma_xbar 142 1>; - dma-names = "tx", "rx"; - clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 0>, - <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 24>; - clock-names = "fck", "ahclkx"; - status = "disabled"; - }; - }; - - target-module@80000 { /* 0x48480000, ap 31 16.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x80020 0x4>; - reg-names = "rev"; - clocks = <&l4per2_clkctrl DRA7_L4PER2_DCAN2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x80000 0x2000>; - - dcan2: can@0 { - compatible = "ti,dra7-d_can"; - reg = <0x0 0x2000>; - syscon-raminit = <&scm_conf 0x558 1>; - interrupts = ; - clocks = <&sys_clkin1>; - status = "disabled"; - }; - }; - - target-module@84000 { /* 0x48484000, ap 3 10.0 */ - compatible = "ti,sysc-omap4-simple", "ti,sysc"; - reg = <0x85200 0x4>, - <0x85208 0x4>, - <0x85204 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <0>; - ti,sysc-midle = , - ; - ti,sysc-sidle = , - ; - ti,syss-mask = <1>; - clocks = <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x84000 0x4000>; - /* - * Do not allow gating of cpsw clock as workaround - * for errata i877. Keeping internal clock disabled - * causes the device switching characteristics - * to degrade over time and eventually fail to meet - * the data manual delay time/skew specs. - */ - ti,no-idle; - - mac: ethernet@0 { - compatible = "ti,dra7-cpsw","ti,cpsw"; - clocks = <&gmac_main_clk>, <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 25>; - clock-names = "fck", "cpts"; - cpdma_channels = <8>; - ale_entries = <1024>; - bd_ram_size = <0x2000>; - mac_control = <0x20>; - slaves = <2>; - active_slave = <0>; - cpts_clock_mult = <0x784CFE14>; - cpts_clock_shift = <29>; - reg = <0x0 0x1000 - 0x1200 0x2e00>; - #address-cells = <1>; - #size-cells = <1>; - - /* - * rx_thresh_pend - * rx_pend - * tx_pend - * misc_pend - */ - interrupts = , - , - , - ; - ranges = <0 0 0x4000>; - syscon = <&scm_conf>; - status = "disabled"; - - davinci_mdio: mdio@1000 { - compatible = "ti,cpsw-mdio","ti,davinci_mdio"; - clocks = <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <0>; - bus_freq = <1000000>; - reg = <0x1000 0x100>; - }; - - cpsw_emac0: slave@200 { - /* Filled in by U-Boot */ - mac-address = [ 00 00 00 00 00 00 ]; - phys = <&phy_gmii_sel 1>; - }; - - cpsw_emac1: slave@300 { - /* Filled in by U-Boot */ - mac-address = [ 00 00 00 00 00 00 ]; - phys = <&phy_gmii_sel 2>; - }; - }; - }; - }; -}; - -&l4_per3 { /* 0x48800000 */ - compatible = "ti,dra7-l4-per3", "simple-bus"; - reg = <0x48800000 0x800>, - <0x48800800 0x800>, - <0x48801000 0x400>, - <0x48801400 0x400>, - <0x48801800 0x400>; - reg-names = "ap", "la", "ia0", "ia1", "ia2"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x48800000 0x200000>; /* segment 0 */ - - segment@0 { /* 0x48800000 */ - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ - <0x00000800 0x00000800 0x000800>, /* ap 1 */ - <0x00001000 0x00001000 0x000400>, /* ap 2 */ - <0x00001400 0x00001400 0x000400>, /* ap 3 */ - <0x00001800 0x00001800 0x000400>, /* ap 4 */ - <0x00020000 0x00020000 0x001000>, /* ap 5 */ - <0x00021000 0x00021000 0x001000>, /* ap 6 */ - <0x00022000 0x00022000 0x001000>, /* ap 7 */ - <0x00023000 0x00023000 0x001000>, /* ap 8 */ - <0x00024000 0x00024000 0x001000>, /* ap 9 */ - <0x00025000 0x00025000 0x001000>, /* ap 10 */ - <0x00026000 0x00026000 0x001000>, /* ap 11 */ - <0x00027000 0x00027000 0x001000>, /* ap 12 */ - <0x00028000 0x00028000 0x001000>, /* ap 13 */ - <0x00029000 0x00029000 0x001000>, /* ap 14 */ - <0x0002a000 0x0002a000 0x001000>, /* ap 15 */ - <0x0002b000 0x0002b000 0x001000>, /* ap 16 */ - <0x0002c000 0x0002c000 0x001000>, /* ap 17 */ - <0x0002d000 0x0002d000 0x001000>, /* ap 18 */ - <0x0002e000 0x0002e000 0x001000>, /* ap 19 */ - <0x0002f000 0x0002f000 0x001000>, /* ap 20 */ - <0x00170000 0x00170000 0x010000>, /* ap 21 */ - <0x00180000 0x00180000 0x001000>, /* ap 22 */ - <0x00190000 0x00190000 0x010000>, /* ap 23 */ - <0x001a0000 0x001a0000 0x001000>, /* ap 24 */ - <0x001b0000 0x001b0000 0x010000>, /* ap 25 */ - <0x001c0000 0x001c0000 0x001000>, /* ap 26 */ - <0x001d0000 0x001d0000 0x010000>, /* ap 27 */ - <0x001e0000 0x001e0000 0x001000>, /* ap 28 */ - <0x00038000 0x00038000 0x001000>, /* ap 29 */ - <0x00039000 0x00039000 0x001000>, /* ap 30 */ - <0x0005c000 0x0005c000 0x001000>, /* ap 31 */ - <0x0005d000 0x0005d000 0x001000>, /* ap 32 */ - <0x0003a000 0x0003a000 0x001000>, /* ap 33 */ - <0x0003b000 0x0003b000 0x001000>, /* ap 34 */ - <0x0003c000 0x0003c000 0x001000>, /* ap 35 */ - <0x0003d000 0x0003d000 0x001000>, /* ap 36 */ - <0x0003e000 0x0003e000 0x001000>, /* ap 37 */ - <0x0003f000 0x0003f000 0x001000>, /* ap 38 */ - <0x00040000 0x00040000 0x001000>, /* ap 39 */ - <0x00041000 0x00041000 0x001000>, /* ap 40 */ - <0x00042000 0x00042000 0x001000>, /* ap 41 */ - <0x00043000 0x00043000 0x001000>, /* ap 42 */ - <0x00044000 0x00044000 0x001000>, /* ap 43 */ - <0x00045000 0x00045000 0x001000>, /* ap 44 */ - <0x00046000 0x00046000 0x001000>, /* ap 45 */ - <0x00047000 0x00047000 0x001000>, /* ap 46 */ - <0x00048000 0x00048000 0x001000>, /* ap 47 */ - <0x00049000 0x00049000 0x001000>, /* ap 48 */ - <0x0004a000 0x0004a000 0x001000>, /* ap 49 */ - <0x0004b000 0x0004b000 0x001000>, /* ap 50 */ - <0x0004c000 0x0004c000 0x001000>, /* ap 51 */ - <0x0004d000 0x0004d000 0x001000>, /* ap 52 */ - <0x0004e000 0x0004e000 0x001000>, /* ap 53 */ - <0x0004f000 0x0004f000 0x001000>, /* ap 54 */ - <0x00050000 0x00050000 0x001000>, /* ap 55 */ - <0x00051000 0x00051000 0x001000>, /* ap 56 */ - <0x00052000 0x00052000 0x001000>, /* ap 57 */ - <0x00053000 0x00053000 0x001000>, /* ap 58 */ - <0x00054000 0x00054000 0x001000>, /* ap 59 */ - <0x00055000 0x00055000 0x001000>, /* ap 60 */ - <0x00056000 0x00056000 0x001000>, /* ap 61 */ - <0x00057000 0x00057000 0x001000>, /* ap 62 */ - <0x00058000 0x00058000 0x001000>, /* ap 63 */ - <0x00059000 0x00059000 0x001000>, /* ap 64 */ - <0x0005a000 0x0005a000 0x001000>, /* ap 65 */ - <0x0005b000 0x0005b000 0x001000>, /* ap 66 */ - <0x00064000 0x00064000 0x001000>, /* ap 67 */ - <0x00065000 0x00065000 0x001000>, /* ap 68 */ - <0x0005e000 0x0005e000 0x001000>, /* ap 69 */ - <0x0005f000 0x0005f000 0x001000>, /* ap 70 */ - <0x00060000 0x00060000 0x001000>, /* ap 71 */ - <0x00061000 0x00061000 0x001000>, /* ap 72 */ - <0x00062000 0x00062000 0x001000>, /* ap 73 */ - <0x00063000 0x00063000 0x001000>, /* ap 74 */ - <0x00140000 0x00140000 0x020000>, /* ap 75 */ - <0x00160000 0x00160000 0x001000>, /* ap 76 */ - <0x00016000 0x00016000 0x001000>, /* ap 77 */ - <0x00017000 0x00017000 0x001000>, /* ap 78 */ - <0x000c0000 0x000c0000 0x020000>, /* ap 79 */ - <0x000e0000 0x000e0000 0x001000>, /* ap 80 */ - <0x00004000 0x00004000 0x001000>, /* ap 81 */ - <0x00005000 0x00005000 0x001000>, /* ap 82 */ - <0x00080000 0x00080000 0x020000>, /* ap 83 */ - <0x000a0000 0x000a0000 0x001000>, /* ap 84 */ - <0x00100000 0x00100000 0x020000>, /* ap 85 */ - <0x00120000 0x00120000 0x001000>, /* ap 86 */ - <0x00010000 0x00010000 0x001000>, /* ap 87 */ - <0x00011000 0x00011000 0x001000>, /* ap 88 */ - <0x0000a000 0x0000a000 0x001000>, /* ap 89 */ - <0x0000b000 0x0000b000 0x001000>, /* ap 90 */ - <0x0001c000 0x0001c000 0x001000>, /* ap 91 */ - <0x0001d000 0x0001d000 0x001000>, /* ap 92 */ - <0x0001e000 0x0001e000 0x001000>, /* ap 93 */ - <0x0001f000 0x0001f000 0x001000>, /* ap 94 */ - <0x00002000 0x00002000 0x001000>, /* ap 95 */ - <0x00003000 0x00003000 0x001000>; /* ap 96 */ - - target-module@2000 { /* 0x48802000, ap 95 7c.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - ti,hwmods = "mailbox13"; - reg = <0x2000 0x4>, - <0x2010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - ; - /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ - clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX13_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2000 0x1000>; - - mailbox13: mailbox@0 { - compatible = "ti,omap4-mailbox"; - reg = <0x0 0x200>; - interrupts = , - , - , - ; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <12>; - status = "disabled"; - }; - }; - - target-module@4000 { /* 0x48804000, ap 81 20.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x4000 0x1000>; - }; - - target-module@a000 { /* 0x4880a000, ap 89 18.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xa000 0x1000>; - }; - - target-module@10000 { /* 0x48810000, ap 87 28.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x10000 0x1000>; - }; - - target-module@16000 { /* 0x48816000, ap 77 1e.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x16000 0x1000>; - }; - - target-module@1c000 { /* 0x4881c000, ap 91 1c.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x1c000 0x1000>; - }; - - target-module@1e000 { /* 0x4881e000, ap 93 2c.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x1e000 0x1000>; - }; - - target-module@20000 { /* 0x48820000, ap 5 08.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - ti,hwmods = "timer5"; - reg = <0x20000 0x4>, - <0x20010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): ipu_pwrdm, ipu_clkdm */ - clocks = <&ipu_clkctrl DRA7_IPU_TIMER5_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x20000 0x1000>; - - timer5: timer@0 { - compatible = "ti,omap5430-timer"; - reg = <0x0 0x80>; - clocks = <&ipu_clkctrl DRA7_IPU_TIMER5_CLKCTRL 24>; - clock-names = "fck"; - interrupts = ; - }; - }; - - target-module@22000 { /* 0x48822000, ap 7 24.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - ti,hwmods = "timer6"; - reg = <0x22000 0x4>, - <0x22010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): ipu_pwrdm, ipu_clkdm */ - clocks = <&ipu_clkctrl DRA7_IPU_TIMER6_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x22000 0x1000>; - - timer6: timer@0 { - compatible = "ti,omap5430-timer"; - reg = <0x0 0x80>; - clocks = <&ipu_clkctrl DRA7_IPU_TIMER6_CLKCTRL 24>; - clock-names = "fck"; - interrupts = ; - }; - }; - - target-module@24000 { /* 0x48824000, ap 9 26.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - ti,hwmods = "timer7"; - reg = <0x24000 0x4>, - <0x24010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): ipu_pwrdm, ipu_clkdm */ - clocks = <&ipu_clkctrl DRA7_IPU_TIMER7_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x24000 0x1000>; - - timer7: timer@0 { - compatible = "ti,omap5430-timer"; - reg = <0x0 0x80>; - clocks = <&ipu_clkctrl DRA7_IPU_TIMER7_CLKCTRL 24>; - clock-names = "fck"; - interrupts = ; - }; - }; - - target-module@26000 { /* 0x48826000, ap 11 0c.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - ti,hwmods = "timer8"; - reg = <0x26000 0x4>, - <0x26010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): ipu_pwrdm, ipu_clkdm */ - clocks = <&ipu_clkctrl DRA7_IPU_TIMER8_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x26000 0x1000>; - - timer8: timer@0 { - compatible = "ti,omap5430-timer"; - reg = <0x0 0x80>; - clocks = <&ipu_clkctrl DRA7_IPU_TIMER8_CLKCTRL 24>; - clock-names = "fck"; - interrupts = ; - }; - }; - - target-module@28000 { /* 0x48828000, ap 13 16.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - ti,hwmods = "timer13"; - reg = <0x28000 0x4>, - <0x28010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): l4per_pwrdm, l4per3_clkdm */ - clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER13_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x28000 0x1000>; - - timer13: timer@0 { - compatible = "ti,omap5430-timer"; - reg = <0x0 0x80>; - clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER13_CLKCTRL 24>; - clock-names = "fck"; - interrupts = ; - }; - }; - - target-module@2a000 { /* 0x4882a000, ap 15 10.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - ti,hwmods = "timer14"; - reg = <0x2a000 0x4>, - <0x2a010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): l4per_pwrdm, l4per3_clkdm */ - clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER14_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2a000 0x1000>; - - timer14: timer@0 { - compatible = "ti,omap5430-timer"; - reg = <0x0 0x80>; - clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER14_CLKCTRL 24>; - clock-names = "fck"; - interrupts = ; - }; - }; - - target-module@2c000 { /* 0x4882c000, ap 17 02.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - ti,hwmods = "timer15"; - reg = <0x2c000 0x4>, - <0x2c010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): l4per_pwrdm, l4per3_clkdm */ - clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER15_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2c000 0x1000>; - - timer15: timer@0 { - compatible = "ti,omap5430-timer"; - reg = <0x0 0x80>; - clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER15_CLKCTRL 24>; - clock-names = "fck"; - interrupts = ; - }; - }; - - target-module@2e000 { /* 0x4882e000, ap 19 14.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - ti,hwmods = "timer16"; - reg = <0x2e000 0x4>, - <0x2e010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): l4per_pwrdm, l4per3_clkdm */ - clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER16_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2e000 0x1000>; - - timer16: timer@0 { - compatible = "ti,omap5430-timer"; - reg = <0x0 0x80>; - clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER16_CLKCTRL 24>; - clock-names = "fck"; - interrupts = ; - }; - }; - - rtctarget: target-module@38000 { /* 0x48838000, ap 29 12.0 */ - compatible = "ti,sysc-omap4-simple", "ti,sysc"; - ti,hwmods = "rtcss"; - reg = <0x38074 0x4>, - <0x38078 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): rtc_pwrdm, rtc_clkdm */ - clocks = <&rtc_clkctrl DRA7_RTC_RTCSS_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x38000 0x1000>; - - rtc: rtc@0 { - compatible = "ti,am3352-rtc"; - reg = <0x0 0x100>; - interrupts = , - ; - clocks = <&sys_32k_ck>; - }; - }; - - target-module@3a000 { /* 0x4883a000, ap 33 3e.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - ti,hwmods = "mailbox2"; - reg = <0x3a000 0x4>, - <0x3a010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - ; - /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ - clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x3a000 0x1000>; - - mailbox2: mailbox@0 { - compatible = "ti,omap4-mailbox"; - reg = <0x0 0x200>; - interrupts = , - , - , - ; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <12>; - status = "disabled"; - }; - }; - - target-module@3c000 { /* 0x4883c000, ap 35 3a.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - ti,hwmods = "mailbox3"; - reg = <0x3c000 0x4>, - <0x3c010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - ; - /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ - clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX3_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x3c000 0x1000>; - - mailbox3: mailbox@0 { - compatible = "ti,omap4-mailbox"; - reg = <0x0 0x200>; - interrupts = , - , - , - ; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <12>; - status = "disabled"; - }; - }; - - target-module@3e000 { /* 0x4883e000, ap 37 46.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - ti,hwmods = "mailbox4"; - reg = <0x3e000 0x4>, - <0x3e010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - ; - /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ - clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX4_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x3e000 0x1000>; - - mailbox4: mailbox@0 { - compatible = "ti,omap4-mailbox"; - reg = <0x0 0x200>; - interrupts = , - , - , - ; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <12>; - status = "disabled"; - }; - }; - - target-module@40000 { /* 0x48840000, ap 39 64.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - ti,hwmods = "mailbox5"; - reg = <0x40000 0x4>, - <0x40010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - ; - /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ - clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX5_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x40000 0x1000>; - - mailbox5: mailbox@0 { - compatible = "ti,omap4-mailbox"; - reg = <0x0 0x200>; - interrupts = , - , - , - ; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <12>; - status = "disabled"; - }; - }; - - target-module@42000 { /* 0x48842000, ap 41 4e.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - ti,hwmods = "mailbox6"; - reg = <0x42000 0x4>, - <0x42010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - ; - /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ - clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX6_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x42000 0x1000>; - - mailbox6: mailbox@0 { - compatible = "ti,omap4-mailbox"; - reg = <0x0 0x200>; - interrupts = , - , - , - ; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <12>; - status = "disabled"; - }; - }; - - target-module@44000 { /* 0x48844000, ap 43 42.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - ti,hwmods = "mailbox7"; - reg = <0x44000 0x4>, - <0x44010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - ; - /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ - clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX7_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x44000 0x1000>; - - mailbox7: mailbox@0 { - compatible = "ti,omap4-mailbox"; - reg = <0x0 0x200>; - interrupts = , - , - , - ; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <12>; - status = "disabled"; - }; - }; - - target-module@46000 { /* 0x48846000, ap 45 48.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - ti,hwmods = "mailbox8"; - reg = <0x46000 0x4>, - <0x46010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - ; - /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ - clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX8_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x46000 0x1000>; - - mailbox8: mailbox@0 { - compatible = "ti,omap4-mailbox"; - reg = <0x0 0x200>; - interrupts = , - , - , - ; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <12>; - status = "disabled"; - }; - }; - - target-module@48000 { /* 0x48848000, ap 47 36.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x48000 0x1000>; - }; - - target-module@4a000 { /* 0x4884a000, ap 49 38.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x4a000 0x1000>; - }; - - target-module@4c000 { /* 0x4884c000, ap 51 44.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x4c000 0x1000>; - }; - - target-module@4e000 { /* 0x4884e000, ap 53 4c.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x4e000 0x1000>; - }; - - target-module@50000 { /* 0x48850000, ap 55 40.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x50000 0x1000>; - }; - - target-module@52000 { /* 0x48852000, ap 57 54.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x52000 0x1000>; - }; - - target-module@54000 { /* 0x48854000, ap 59 1a.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x54000 0x1000>; - }; - - target-module@56000 { /* 0x48856000, ap 61 22.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x56000 0x1000>; - }; - - target-module@58000 { /* 0x48858000, ap 63 2a.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x58000 0x1000>; - }; - - target-module@5a000 { /* 0x4885a000, ap 65 5c.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x5a000 0x1000>; - }; - - target-module@5c000 { /* 0x4885c000, ap 31 32.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x5c000 0x1000>; - }; - - target-module@5e000 { /* 0x4885e000, ap 69 6c.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - ti,hwmods = "mailbox9"; - reg = <0x5e000 0x4>, - <0x5e010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - ; - /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ - clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX9_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x5e000 0x1000>; - - mailbox9: mailbox@0 { - compatible = "ti,omap4-mailbox"; - reg = <0x0 0x200>; - interrupts = , - , - , - ; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <12>; - status = "disabled"; - }; - }; - - target-module@60000 { /* 0x48860000, ap 71 4a.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - ti,hwmods = "mailbox10"; - reg = <0x60000 0x4>, - <0x60010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - ; - /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ - clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX10_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x60000 0x1000>; - - mailbox10: mailbox@0 { - compatible = "ti,omap4-mailbox"; - reg = <0x0 0x200>; - interrupts = , - , - , - ; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <12>; - status = "disabled"; - }; - }; - - target-module@62000 { /* 0x48862000, ap 73 74.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - ti,hwmods = "mailbox11"; - reg = <0x62000 0x4>, - <0x62010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - ; - /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ - clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX11_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x62000 0x1000>; - - mailbox11: mailbox@0 { - compatible = "ti,omap4-mailbox"; - reg = <0x0 0x200>; - interrupts = , - , - , - ; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <12>; - status = "disabled"; - }; - }; - - target-module@64000 { /* 0x48864000, ap 67 52.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - ti,hwmods = "mailbox12"; - reg = <0x64000 0x4>, - <0x64010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - ; - /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ - clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX12_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x64000 0x1000>; - - mailbox12: mailbox@0 { - compatible = "ti,omap4-mailbox"; - reg = <0x0 0x200>; - interrupts = , - , - , - ; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <12>; - status = "disabled"; - }; - }; - - target-module@80000 { /* 0x48880000, ap 83 0e.1 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - ti,hwmods = "usb_otg_ss1"; - reg = <0x80000 0x4>, - <0x80010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = ; - ti,sysc-midle = , - , - , - ; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): l3init_pwrdm, l3init_clkdm */ - clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x80000 0x20000>; - - omap_dwc3_1: omap_dwc3_1@0 { - compatible = "ti,dwc3"; - reg = <0x0 0x10000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <1>; - utmi-mode = <2>; - ranges = <0 0 0x20000>; - - usb1: usb@10000 { - compatible = "snps,dwc3"; - reg = <0x10000 0x17000>; - interrupts = , - , - ; - interrupt-names = "peripheral", - "host", - "otg"; - phys = <&usb2_phy1>, <&usb3_phy1>; - phy-names = "usb2-phy", "usb3-phy"; - maximum-speed = "super-speed"; - dr_mode = "otg"; - snps,dis_u3_susphy_quirk; - snps,dis_u2_susphy_quirk; - }; - }; - }; - - target-module@c0000 { /* 0x488c0000, ap 79 06.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - ti,hwmods = "usb_otg_ss2"; - reg = <0xc0000 0x4>, - <0xc0010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = ; - ti,sysc-midle = , - , - , - ; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): l3init_pwrdm, l3init_clkdm */ - clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xc0000 0x20000>; - - omap_dwc3_2: omap_dwc3_2@0 { - compatible = "ti,dwc3"; - reg = <0x0 0x10000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <1>; - utmi-mode = <2>; - ranges = <0 0 0x20000>; - - usb2: usb@10000 { - compatible = "snps,dwc3"; - reg = <0x10000 0x17000>; - interrupts = , - , - ; - interrupt-names = "peripheral", - "host", - "otg"; - phys = <&usb2_phy2>; - phy-names = "usb2-phy"; - maximum-speed = "high-speed"; - dr_mode = "otg"; - snps,dis_u3_susphy_quirk; - snps,dis_u2_susphy_quirk; - snps,dis_metastability_quirk; - }; - }; - }; - - usb3_tm: target-module@100000 { /* 0x48900000, ap 85 04.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - ti,hwmods = "usb_otg_ss3"; - reg = <0x100000 0x4>, - <0x100010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = ; - ti,sysc-midle = , - , - , - ; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): l3init_pwrdm, l3init_clkdm */ - clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS3_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x100000 0x20000>; - - omap_dwc3_3: omap_dwc3_3@0 { - compatible = "ti,dwc3"; - reg = <0x0 0x10000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <1>; - utmi-mode = <2>; - ranges = <0 0 0x20000>; - status = "disabled"; - - usb3: usb@10000 { - compatible = "snps,dwc3"; - reg = <0x10000 0x17000>; - interrupts = , - , - ; - interrupt-names = "peripheral", - "host", - "otg"; - maximum-speed = "high-speed"; - dr_mode = "otg"; - snps,dis_u3_susphy_quirk; - snps,dis_u2_susphy_quirk; - }; - }; - }; - - usb4_tm: target-module@140000 { /* 0x48940000, ap 75 3c.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - ti,hwmods = "usb_otg_ss4"; - reg = <0x140000 0x4>, - <0x140010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = ; - ti,sysc-midle = , - , - , - ; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): l3init_pwrdm, l3init_clkdm */ - clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS4_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x140000 0x20000>; - }; - - target-module@170000 { /* 0x48970000, ap 21 0a.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x170000 0x10000>; - }; - - target-module@190000 { /* 0x48990000, ap 23 2e.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x190000 0x10000>; - }; - - target-module@1b0000 { /* 0x489b0000, ap 25 34.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x1b0000 0x10000>; - }; - - target-module@1d0000 { /* 0x489d0000, ap 27 30.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x1d0000 0x10000>; - }; - }; -}; - -&l4_wkup { /* 0x4ae00000 */ - compatible = "ti,dra7-l4-wkup", "simple-bus"; - reg = <0x4ae00000 0x800>, - <0x4ae00800 0x800>, - <0x4ae01000 0x1000>; - reg-names = "ap", "la", "ia0"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x4ae00000 0x010000>, /* segment 0 */ - <0x00010000 0x4ae10000 0x010000>, /* segment 1 */ - <0x00020000 0x4ae20000 0x010000>, /* segment 2 */ - <0x00030000 0x4ae30000 0x010000>; /* segment 3 */ - - segment@0 { /* 0x4ae00000 */ - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ - <0x00001000 0x00001000 0x001000>, /* ap 1 */ - <0x00000800 0x00000800 0x000800>, /* ap 2 */ - <0x00006000 0x00006000 0x002000>, /* ap 3 */ - <0x00008000 0x00008000 0x001000>, /* ap 4 */ - <0x00004000 0x00004000 0x001000>, /* ap 15 */ - <0x00005000 0x00005000 0x001000>, /* ap 16 */ - <0x0000c000 0x0000c000 0x001000>, /* ap 17 */ - <0x0000d000 0x0000d000 0x001000>; /* ap 18 */ - - target-module@4000 { /* 0x4ae04000, ap 15 40.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "counter_32k"; - reg = <0x4000 0x4>, - <0x4010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */ - clocks = <&wkupaon_clkctrl DRA7_WKUPAON_COUNTER_32K_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x4000 0x1000>; - - counter32k: counter@0 { - compatible = "ti,omap-counter32k"; - reg = <0x0 0x40>; - }; - }; - - target-module@6000 { /* 0x4ae06000, ap 3 10.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x6000 0x4>; - reg-names = "rev"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x6000 0x2000>; - - prm: prm@0 { - compatible = "ti,dra7-prm", "simple-bus"; - reg = <0 0x3000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x3000>; - - prm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - prm_clockdomains: clockdomains { - }; - }; - }; - - target-module@c000 { /* 0x4ae0c000, ap 17 50.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0xc000 0x4>; - reg-names = "rev"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xc000 0x1000>; - - scm_wkup: scm_conf@0 { - compatible = "syscon"; - reg = <0 0x1000>; - }; - }; - }; - - segment@10000 { /* 0x4ae10000 */ - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00010000 0x001000>, /* ap 5 */ - <0x00001000 0x00011000 0x001000>, /* ap 6 */ - <0x00004000 0x00014000 0x001000>, /* ap 7 */ - <0x00005000 0x00015000 0x001000>, /* ap 8 */ - <0x00008000 0x00018000 0x001000>, /* ap 9 */ - <0x00009000 0x00019000 0x001000>, /* ap 10 */ - <0x0000c000 0x0001c000 0x001000>, /* ap 11 */ - <0x0000d000 0x0001d000 0x001000>; /* ap 12 */ - - target-module@0 { /* 0x4ae10000, ap 5 20.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x0 0x4>, - <0x10 0x4>, - <0x114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */ - clocks = <&wkupaon_clkctrl DRA7_WKUPAON_GPIO1_CLKCTRL 0>, - <&wkupaon_clkctrl DRA7_WKUPAON_GPIO1_CLKCTRL 8>; - clock-names = "fck", "dbclk"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x1000>; - - gpio1: gpio@0 { - compatible = "ti,omap4-gpio"; - reg = <0x0 0x200>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - target-module@4000 { /* 0x4ae14000, ap 7 28.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "wd_timer2"; - reg = <0x4000 0x4>, - <0x4010 0x4>, - <0x4014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_EMUFREE | - SYSC_OMAP2_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */ - clocks = <&wkupaon_clkctrl DRA7_WKUPAON_WD_TIMER2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x4000 0x1000>; - - wdt2: wdt@0 { - compatible = "ti,omap3-wdt"; - reg = <0x0 0x80>; - interrupts = ; - }; - }; - - target-module@8000 { /* 0x4ae18000, ap 9 30.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - ti,hwmods = "timer1"; - reg = <0x8000 0x4>, - <0x8010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */ - clocks = <&wkupaon_clkctrl DRA7_WKUPAON_TIMER1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x8000 0x1000>; - - timer1: timer@0 { - compatible = "ti,omap5430-timer"; - reg = <0x0 0x80>; - clocks = <&wkupaon_clkctrl DRA7_WKUPAON_TIMER1_CLKCTRL 24>; - clock-names = "fck"; - interrupts = ; - ti,timer-alwon; - }; - }; - - target-module@c000 { /* 0x4ae1c000, ap 11 38.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xc000 0x1000>; - }; - }; - - segment@20000 { /* 0x4ae20000 */ - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00006000 0x00026000 0x001000>, /* ap 13 */ - <0x0000a000 0x0002a000 0x001000>, /* ap 14 */ - <0x00000000 0x00020000 0x001000>, /* ap 19 */ - <0x00001000 0x00021000 0x001000>, /* ap 20 */ - <0x00002000 0x00022000 0x001000>, /* ap 21 */ - <0x00003000 0x00023000 0x001000>, /* ap 22 */ - <0x00007000 0x00027000 0x000400>, /* ap 23 */ - <0x00008000 0x00028000 0x000800>, /* ap 24 */ - <0x00009000 0x00029000 0x000100>, /* ap 25 */ - <0x00008800 0x00028800 0x000200>, /* ap 26 */ - <0x00008a00 0x00028a00 0x000100>, /* ap 27 */ - <0x0000b000 0x0002b000 0x001000>, /* ap 28 */ - <0x0000c000 0x0002c000 0x001000>, /* ap 29 */ - <0x0000f000 0x0002f000 0x001000>; /* ap 32 */ - - target-module@0 { /* 0x4ae20000, ap 19 08.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - ti,hwmods = "timer12"; - reg = <0x0 0x4>, - <0x10 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */ - clocks = <&wkupaon_clkctrl DRA7_WKUPAON_TIMER12_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x1000>; - - timer12: timer@0 { - compatible = "ti,omap5430-timer"; - reg = <0x0 0x80>; - interrupts = ; - ti,timer-alwon; - ti,timer-secure; - }; - }; - - target-module@2000 { /* 0x4ae22000, ap 21 18.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2000 0x1000>; - }; - - target-module@6000 { /* 0x4ae26000, ap 13 48.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00006000 0x00001000>, - <0x00001000 0x00007000 0x00000400>, - <0x00002000 0x00008000 0x00000800>, - <0x00002800 0x00008800 0x00000200>, - <0x00002a00 0x00008a00 0x00000100>, - <0x00003000 0x00009000 0x00000100>; - }; - - target-module@b000 { /* 0x4ae2b000, ap 28 02.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0xb050 0x4>, - <0xb054 0x4>, - <0xb058 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */ - clocks = <&wkupaon_clkctrl DRA7_WKUPAON_UART10_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xb000 0x1000>; - - uart10: serial@0 { - compatible = "ti,dra742-uart", "ti,omap4-uart"; - reg = <0x0 0x100>; - interrupts = ; - clock-frequency = <48000000>; - status = "disabled"; - }; - }; - - target-module@f000 { /* 0x4ae2f000, ap 32 58.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xf000 0x1000>; - }; - }; - - segment@30000 { /* 0x4ae30000 */ - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0000c000 0x0003c000 0x002000>, /* ap 30 */ - <0x0000e000 0x0003e000 0x001000>, /* ap 31 */ - <0x00000000 0x00030000 0x001000>, /* ap 33 */ - <0x00001000 0x00031000 0x001000>, /* ap 34 */ - <0x00002000 0x00032000 0x001000>, /* ap 35 */ - <0x00003000 0x00033000 0x001000>, /* ap 36 */ - <0x00004000 0x00034000 0x001000>, /* ap 37 */ - <0x00005000 0x00035000 0x001000>, /* ap 38 */ - <0x00006000 0x00036000 0x001000>, /* ap 39 */ - <0x00007000 0x00037000 0x001000>, /* ap 40 */ - <0x00008000 0x00038000 0x001000>, /* ap 41 */ - <0x00009000 0x00039000 0x001000>, /* ap 42 */ - <0x0000a000 0x0003a000 0x001000>; /* ap 43 */ - - target-module@1000 { /* 0x4ae31000, ap 34 60.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x1000 0x1000>; - }; - - target-module@3000 { /* 0x4ae33000, ap 36 0a.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x3000 0x1000>; - }; - - target-module@5000 { /* 0x4ae35000, ap 38 0c.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x5000 0x1000>; - }; - - target-module@7000 { /* 0x4ae37000, ap 40 68.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x7000 0x1000>; - }; - - target-module@9000 { /* 0x4ae39000, ap 42 70.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x9000 0x1000>; - }; - - target-module@c000 { /* 0x4ae3c000, ap 30 04.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0xc020 0x4>; - reg-names = "rev"; - clocks = <&wkupaon_clkctrl DRA7_WKUPAON_DCAN1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xc000 0x2000>; - - dcan1: can@0 { - compatible = "ti,dra7-d_can"; - reg = <0x0 0x2000>; - syscon-raminit = <&scm_conf 0x558 0>; - interrupts = ; - clocks = <&wkupaon_clkctrl DRA7_WKUPAON_DCAN1_CLKCTRL 24>; - status = "disabled"; - }; - }; - }; -}; - diff --git a/sys/gnu/dts/arm/dra7-mmc-iodelay.dtsi b/sys/gnu/dts/arm/dra7-mmc-iodelay.dtsi deleted file mode 100644 index aa094726652..00000000000 --- a/sys/gnu/dts/arm/dra7-mmc-iodelay.dtsi +++ /dev/null @@ -1,19 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * MMC IOdelay values for TI's DRA7xx SoCs. - * Copyright (C) 2018 Texas Instruments - * Author: Kishon Vijay Abraham I - */ - -&dra7_pmx_core { - mmc1_pins_default_no_clk_pu: mmc1_pins_default_no_clk_pu { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mmc1_clk.clk */ - DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ - DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ - DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ - DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ - DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ - >; - }; -}; diff --git a/sys/gnu/dts/arm/dra7.dtsi b/sys/gnu/dts/arm/dra7.dtsi deleted file mode 100644 index 953f0ffce2a..00000000000 --- a/sys/gnu/dts/arm/dra7.dtsi +++ /dev/null @@ -1,765 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ - * - * Based on "omap4.dtsi" - */ - -#include -#include -#include -#include -#include - -#define MAX_SOURCES 400 - -/ { - #address-cells = <2>; - #size-cells = <2>; - - compatible = "ti,dra7xx"; - interrupt-parent = <&crossbar_mpu>; - chosen { }; - - aliases { - i2c0 = &i2c1; - i2c1 = &i2c2; - i2c2 = &i2c3; - i2c3 = &i2c4; - i2c4 = &i2c5; - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - serial3 = &uart4; - serial4 = &uart5; - serial5 = &uart6; - serial6 = &uart7; - serial7 = &uart8; - serial8 = &uart9; - serial9 = &uart10; - ethernet0 = &cpsw_emac0; - ethernet1 = &cpsw_emac1; - d_can0 = &dcan1; - d_can1 = &dcan2; - spi0 = &qspi; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; - interrupt-parent = <&gic>; - }; - - gic: interrupt-controller@48211000 { - compatible = "arm,cortex-a15-gic"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0x0 0x48211000 0x0 0x1000>, - <0x0 0x48212000 0x0 0x2000>, - <0x0 0x48214000 0x0 0x2000>, - <0x0 0x48216000 0x0 0x2000>; - interrupts = ; - interrupt-parent = <&gic>; - }; - - wakeupgen: interrupt-controller@48281000 { - compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0x0 0x48281000 0x0 0x1000>; - interrupt-parent = <&gic>; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0>; - - operating-points-v2 = <&cpu0_opp_table>; - - clocks = <&dpll_mpu_ck>; - clock-names = "cpu"; - - clock-latency = <300000>; /* From omap-cpufreq driver */ - - /* cooling options */ - #cooling-cells = <2>; /* min followed by max */ - - vbb-supply = <&abb_mpu>; - }; - }; - - cpu0_opp_table: opp-table { - compatible = "operating-points-v2-ti-cpu"; - syscon = <&scm_wkup>; - - opp_nom-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <1060000 850000 1150000>, - <1060000 850000 1150000>; - opp-supported-hw = <0xFF 0x01>; - opp-suspend; - }; - - opp_od-1176000000 { - opp-hz = /bits/ 64 <1176000000>; - opp-microvolt = <1160000 885000 1160000>, - <1160000 885000 1160000>; - - opp-supported-hw = <0xFF 0x02>; - }; - - opp_high@1500000000 { - opp-hz = /bits/ 64 <1500000000>; - opp-microvolt = <1210000 950000 1250000>, - <1210000 950000 1250000>; - opp-supported-hw = <0xFF 0x04>; - }; - }; - - /* - * The soc node represents the soc top level view. It is used for IPs - * that are not memory mapped in the MPU view or for the MPU itself. - */ - soc { - compatible = "ti,omap-infra"; - mpu { - compatible = "ti,omap5-mpu"; - ti,hwmods = "mpu"; - }; - }; - - /* - * XXX: Use a flat representation of the SOC interconnect. - * The real OMAP interconnect network is quite complex. - * Since it will not bring real advantage to represent that in DT for - * the moment, just use a fake OCP bus entry to represent the whole bus - * hierarchy. - */ - ocp { - compatible = "ti,dra7-l3-noc", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x0 0xc0000000>; - ti,hwmods = "l3_main_1", "l3_main_2"; - reg = <0x0 0x44000000 0x0 0x1000000>, - <0x0 0x45000000 0x0 0x1000>; - interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, - <&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; - - l4_cfg: interconnect@4a000000 { - }; - l4_wkup: interconnect@4ae00000 { - }; - l4_per1: interconnect@48000000 { - }; - l4_per2: interconnect@48400000 { - }; - l4_per3: interconnect@48800000 { - }; - - axi@0 { - compatible = "simple-bus"; - #size-cells = <1>; - #address-cells = <1>; - ranges = <0x51000000 0x51000000 0x3000 - 0x0 0x20000000 0x10000000>; - /** - * To enable PCI endpoint mode, disable the pcie1_rc - * node and enable pcie1_ep mode. - */ - pcie1_rc: pcie@51000000 { - reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>; - reg-names = "rc_dbics", "ti_conf", "config"; - interrupts = <0 232 0x4>, <0 233 0x4>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges = <0x81000000 0 0 0x03000 0 0x00010000 - 0x82000000 0 0x20013000 0x13000 0 0xffed000>; - bus-range = <0x00 0xff>; - #interrupt-cells = <1>; - num-lanes = <1>; - linux,pci-domain = <0>; - ti,hwmods = "pcie1"; - phys = <&pcie1_phy>; - phy-names = "pcie-phy0"; - ti,syscon-lane-sel = <&scm_conf_pcie 0x18>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie1_intc 1>, - <0 0 0 2 &pcie1_intc 2>, - <0 0 0 3 &pcie1_intc 3>, - <0 0 0 4 &pcie1_intc 4>; - ti,syscon-unaligned-access = <&scm_conf1 0x14 1>; - status = "disabled"; - pcie1_intc: interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - }; - }; - - pcie1_ep: pcie_ep@51000000 { - reg = <0x51000000 0x28>, <0x51002000 0x14c>, <0x51001000 0x28>, <0x1000 0x10000000>; - reg-names = "ep_dbics", "ti_conf", "ep_dbics2", "addr_space"; - interrupts = <0 232 0x4>; - num-lanes = <1>; - num-ib-windows = <4>; - num-ob-windows = <16>; - ti,hwmods = "pcie1"; - phys = <&pcie1_phy>; - phy-names = "pcie-phy0"; - ti,syscon-unaligned-access = <&scm_conf1 0x14 1>; - ti,syscon-lane-sel = <&scm_conf_pcie 0x18>; - status = "disabled"; - }; - }; - - axi@1 { - compatible = "simple-bus"; - #size-cells = <1>; - #address-cells = <1>; - ranges = <0x51800000 0x51800000 0x3000 - 0x0 0x30000000 0x10000000>; - status = "disabled"; - pcie2_rc: pcie@51800000 { - reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>; - reg-names = "rc_dbics", "ti_conf", "config"; - interrupts = <0 355 0x4>, <0 356 0x4>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges = <0x81000000 0 0 0x03000 0 0x00010000 - 0x82000000 0 0x30013000 0x13000 0 0xffed000>; - bus-range = <0x00 0xff>; - #interrupt-cells = <1>; - num-lanes = <1>; - linux,pci-domain = <1>; - ti,hwmods = "pcie2"; - phys = <&pcie2_phy>; - phy-names = "pcie-phy0"; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie2_intc 1>, - <0 0 0 2 &pcie2_intc 2>, - <0 0 0 3 &pcie2_intc 3>, - <0 0 0 4 &pcie2_intc 4>; - ti,syscon-unaligned-access = <&scm_conf1 0x14 2>; - pcie2_intc: interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - }; - }; - }; - - ocmcram1: ocmcram@40300000 { - compatible = "mmio-sram"; - reg = <0x40300000 0x80000>; - ranges = <0x0 0x40300000 0x80000>; - #address-cells = <1>; - #size-cells = <1>; - /* - * This is a placeholder for an optional reserved - * region for use by secure software. The size - * of this region is not known until runtime so it - * is set as zero to either be updated to reserve - * space or left unchanged to leave all SRAM for use. - * On HS parts that that require the reserved region - * either the bootloader can update the size to - * the required amount or the node can be overridden - * from the board dts file for the secure platform. - */ - sram-hs@0 { - compatible = "ti,secure-ram"; - reg = <0x0 0x0>; - }; - }; - - /* - * NOTE: ocmcram2 and ocmcram3 are not available on all - * DRA7xx and AM57xx variants. Confirm availability in - * the data manual for the exact part number in use - * before enabling these nodes in the board dts file. - */ - ocmcram2: ocmcram@40400000 { - status = "disabled"; - compatible = "mmio-sram"; - reg = <0x40400000 0x100000>; - ranges = <0x0 0x40400000 0x100000>; - #address-cells = <1>; - #size-cells = <1>; - }; - - ocmcram3: ocmcram@40500000 { - status = "disabled"; - compatible = "mmio-sram"; - reg = <0x40500000 0x100000>; - ranges = <0x0 0x40500000 0x100000>; - #address-cells = <1>; - #size-cells = <1>; - }; - - bandgap: bandgap@4a0021e0 { - reg = <0x4a0021e0 0xc - 0x4a00232c 0xc - 0x4a002380 0x2c - 0x4a0023C0 0x3c - 0x4a002564 0x8 - 0x4a002574 0x50>; - compatible = "ti,dra752-bandgap"; - interrupts = ; - #thermal-sensor-cells = <1>; - }; - - dsp1_system: dsp_system@40d00000 { - compatible = "syscon"; - reg = <0x40d00000 0x100>; - }; - - dra7_iodelay_core: padconf@4844a000 { - compatible = "ti,dra7-iodelay"; - reg = <0x4844a000 0x0d1c>; - #address-cells = <1>; - #size-cells = <0>; - #pinctrl-cells = <2>; - }; - - edma: edma@43300000 { - compatible = "ti,edma3-tpcc"; - ti,hwmods = "tpcc"; - reg = <0x43300000 0x100000>; - reg-names = "edma3_cc"; - interrupts = , - , - ; - interrupt-names = "edma3_ccint", "edma3_mperr", - "edma3_ccerrint"; - dma-requests = <64>; - #dma-cells = <2>; - - ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 0>; - - /* - * memcpy is disabled, can be enabled with: - * ti,edma-memcpy-channels = <20 21>; - * for example. Note that these channels need to be - * masked in the xbar as well. - */ - }; - - edma_tptc0: tptc@43400000 { - compatible = "ti,edma3-tptc"; - ti,hwmods = "tptc0"; - reg = <0x43400000 0x100000>; - interrupts = ; - interrupt-names = "edma3_tcerrint"; - }; - - edma_tptc1: tptc@43500000 { - compatible = "ti,edma3-tptc"; - ti,hwmods = "tptc1"; - reg = <0x43500000 0x100000>; - interrupts = ; - interrupt-names = "edma3_tcerrint"; - }; - - dmm@4e000000 { - compatible = "ti,omap5-dmm"; - reg = <0x4e000000 0x800>; - interrupts = ; - ti,hwmods = "dmm"; - }; - - mmu0_dsp1: mmu@40d01000 { - compatible = "ti,dra7-dsp-iommu"; - reg = <0x40d01000 0x100>; - interrupts = ; - ti,hwmods = "mmu0_dsp1"; - #iommu-cells = <0>; - ti,syscon-mmuconfig = <&dsp1_system 0x0>; - status = "disabled"; - }; - - mmu1_dsp1: mmu@40d02000 { - compatible = "ti,dra7-dsp-iommu"; - reg = <0x40d02000 0x100>; - interrupts = ; - ti,hwmods = "mmu1_dsp1"; - #iommu-cells = <0>; - ti,syscon-mmuconfig = <&dsp1_system 0x1>; - status = "disabled"; - }; - - mmu_ipu1: mmu@58882000 { - compatible = "ti,dra7-iommu"; - reg = <0x58882000 0x100>; - interrupts = ; - ti,hwmods = "mmu_ipu1"; - #iommu-cells = <0>; - ti,iommu-bus-err-back; - status = "disabled"; - }; - - mmu_ipu2: mmu@55082000 { - compatible = "ti,dra7-iommu"; - reg = <0x55082000 0x100>; - interrupts = ; - ti,hwmods = "mmu_ipu2"; - #iommu-cells = <0>; - ti,iommu-bus-err-back; - status = "disabled"; - }; - - abb_mpu: regulator-abb-mpu { - compatible = "ti,abb-v3"; - regulator-name = "abb_mpu"; - #address-cells = <0>; - #size-cells = <0>; - clocks = <&sys_clkin1>; - ti,settling-time = <50>; - ti,clock-cycles = <16>; - - reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>, - <0x4ae06014 0x4>, <0x4a003b20 0xc>, - <0x4ae0c158 0x4>; - reg-names = "setup-address", "control-address", - "int-address", "efuse-address", - "ldo-address"; - ti,tranxdone-status-mask = <0x80>; - /* LDOVBBMPU_FBB_MUX_CTRL */ - ti,ldovbb-override-mask = <0x400>; - /* LDOVBBMPU_FBB_VSET_OUT */ - ti,ldovbb-vset-mask = <0x1F>; - - /* - * NOTE: only FBB mode used but actual vset will - * determine final biasing - */ - ti,abb_info = < - /*uV ABB efuse rbb_m fbb_m vset_m*/ - 1060000 0 0x0 0 0x02000000 0x01F00000 - 1160000 0 0x4 0 0x02000000 0x01F00000 - 1210000 0 0x8 0 0x02000000 0x01F00000 - >; - }; - - abb_ivahd: regulator-abb-ivahd { - compatible = "ti,abb-v3"; - regulator-name = "abb_ivahd"; - #address-cells = <0>; - #size-cells = <0>; - clocks = <&sys_clkin1>; - ti,settling-time = <50>; - ti,clock-cycles = <16>; - - reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>, - <0x4ae06010 0x4>, <0x4a0025cc 0xc>, - <0x4a002470 0x4>; - reg-names = "setup-address", "control-address", - "int-address", "efuse-address", - "ldo-address"; - ti,tranxdone-status-mask = <0x40000000>; - /* LDOVBBIVA_FBB_MUX_CTRL */ - ti,ldovbb-override-mask = <0x400>; - /* LDOVBBIVA_FBB_VSET_OUT */ - ti,ldovbb-vset-mask = <0x1F>; - - /* - * NOTE: only FBB mode used but actual vset will - * determine final biasing - */ - ti,abb_info = < - /*uV ABB efuse rbb_m fbb_m vset_m*/ - 1055000 0 0x0 0 0x02000000 0x01F00000 - 1150000 0 0x4 0 0x02000000 0x01F00000 - 1250000 0 0x8 0 0x02000000 0x01F00000 - >; - }; - - abb_dspeve: regulator-abb-dspeve { - compatible = "ti,abb-v3"; - regulator-name = "abb_dspeve"; - #address-cells = <0>; - #size-cells = <0>; - clocks = <&sys_clkin1>; - ti,settling-time = <50>; - ti,clock-cycles = <16>; - - reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>, - <0x4ae06010 0x4>, <0x4a0025e0 0xc>, - <0x4a00246c 0x4>; - reg-names = "setup-address", "control-address", - "int-address", "efuse-address", - "ldo-address"; - ti,tranxdone-status-mask = <0x20000000>; - /* LDOVBBDSPEVE_FBB_MUX_CTRL */ - ti,ldovbb-override-mask = <0x400>; - /* LDOVBBDSPEVE_FBB_VSET_OUT */ - ti,ldovbb-vset-mask = <0x1F>; - - /* - * NOTE: only FBB mode used but actual vset will - * determine final biasing - */ - ti,abb_info = < - /*uV ABB efuse rbb_m fbb_m vset_m*/ - 1055000 0 0x0 0 0x02000000 0x01F00000 - 1150000 0 0x4 0 0x02000000 0x01F00000 - 1250000 0 0x8 0 0x02000000 0x01F00000 - >; - }; - - abb_gpu: regulator-abb-gpu { - compatible = "ti,abb-v3"; - regulator-name = "abb_gpu"; - #address-cells = <0>; - #size-cells = <0>; - clocks = <&sys_clkin1>; - ti,settling-time = <50>; - ti,clock-cycles = <16>; - - reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>, - <0x4ae06010 0x4>, <0x4a003b08 0xc>, - <0x4ae0c154 0x4>; - reg-names = "setup-address", "control-address", - "int-address", "efuse-address", - "ldo-address"; - ti,tranxdone-status-mask = <0x10000000>; - /* LDOVBBGPU_FBB_MUX_CTRL */ - ti,ldovbb-override-mask = <0x400>; - /* LDOVBBGPU_FBB_VSET_OUT */ - ti,ldovbb-vset-mask = <0x1F>; - - /* - * NOTE: only FBB mode used but actual vset will - * determine final biasing - */ - ti,abb_info = < - /*uV ABB efuse rbb_m fbb_m vset_m*/ - 1090000 0 0x0 0 0x02000000 0x01F00000 - 1210000 0 0x4 0 0x02000000 0x01F00000 - 1280000 0 0x8 0 0x02000000 0x01F00000 - >; - }; - - qspi: spi@4b300000 { - compatible = "ti,dra7xxx-qspi"; - reg = <0x4b300000 0x100>, - <0x5c000000 0x4000000>; - reg-names = "qspi_base", "qspi_mmap"; - syscon-chipselects = <&scm_conf 0x558>; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "qspi"; - clocks = <&l4per2_clkctrl DRA7_L4PER2_QSPI_CLKCTRL 25>; - clock-names = "fck"; - num-cs = <4>; - interrupts = ; - status = "disabled"; - }; - - /* OCP2SCP3 */ - sata: sata@4a141100 { - compatible = "snps,dwc-ahci"; - reg = <0x4a140000 0x1100>, <0x4a141100 0x7>; - interrupts = ; - phys = <&sata_phy>; - phy-names = "sata-phy"; - clocks = <&l3init_clkctrl DRA7_L3INIT_SATA_CLKCTRL 8>; - ti,hwmods = "sata"; - ports-implemented = <0x1>; - }; - - /* OCP2SCP1 */ - /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */ - gpmc: gpmc@50000000 { - compatible = "ti,am3352-gpmc"; - ti,hwmods = "gpmc"; - reg = <0x50000000 0x37c>; /* device IO registers */ - interrupts = ; - dmas = <&edma_xbar 4 0>; - dma-names = "rxtx"; - gpmc,num-cs = <8>; - gpmc,num-waitpins = <2>; - #address-cells = <2>; - #size-cells = <1>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - status = "disabled"; - }; - - crossbar_mpu: crossbar@4a002a48 { - compatible = "ti,irq-crossbar"; - reg = <0x4a002a48 0x130>; - interrupt-controller; - interrupt-parent = <&wakeupgen>; - #interrupt-cells = <3>; - ti,max-irqs = <160>; - ti,max-crossbar-sources = ; - ti,reg-size = <2>; - ti,irqs-reserved = <0 1 2 3 5 6 131 132>; - ti,irqs-skip = <10 133 139 140>; - ti,irqs-safe-map = <0>; - }; - - dss: dss@58000000 { - compatible = "ti,dra7-dss"; - /* 'reg' defined in dra72x.dtsi and dra74x.dtsi */ - /* 'clocks' defined in dra72x.dtsi and dra74x.dtsi */ - status = "disabled"; - ti,hwmods = "dss_core"; - /* CTRL_CORE_DSS_PLL_CONTROL */ - syscon-pll-ctrl = <&scm_conf 0x538>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - dispc@58001000 { - compatible = "ti,dra7-dispc"; - reg = <0x58001000 0x1000>; - interrupts = ; - ti,hwmods = "dss_dispc"; - clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>; - clock-names = "fck"; - /* CTRL_CORE_SMA_SW_1 */ - syscon-pol = <&scm_conf 0x534>; - }; - - hdmi: encoder@58060000 { - compatible = "ti,dra7-hdmi"; - reg = <0x58040000 0x200>, - <0x58040200 0x80>, - <0x58040300 0x80>, - <0x58060000 0x19000>; - reg-names = "wp", "pll", "phy", "core"; - interrupts = ; - status = "disabled"; - ti,hwmods = "dss_hdmi"; - clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 9>, - <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 10>; - clock-names = "fck", "sys_clk"; - dmas = <&sdma_xbar 76>; - dma-names = "audio_tx"; - }; - }; - - aes1: aes@4b500000 { - compatible = "ti,omap4-aes"; - ti,hwmods = "aes1"; - reg = <0x4b500000 0xa0>; - interrupts = ; - dmas = <&edma_xbar 111 0>, <&edma_xbar 110 0>; - dma-names = "tx", "rx"; - clocks = <&l3_iclk_div>; - clock-names = "fck"; - }; - - aes2: aes@4b700000 { - compatible = "ti,omap4-aes"; - ti,hwmods = "aes2"; - reg = <0x4b700000 0xa0>; - interrupts = ; - dmas = <&edma_xbar 114 0>, <&edma_xbar 113 0>; - dma-names = "tx", "rx"; - clocks = <&l3_iclk_div>; - clock-names = "fck"; - }; - - des: des@480a5000 { - compatible = "ti,omap4-des"; - ti,hwmods = "des"; - reg = <0x480a5000 0xa0>; - interrupts = ; - dmas = <&sdma_xbar 117>, <&sdma_xbar 116>; - dma-names = "tx", "rx"; - clocks = <&l3_iclk_div>; - clock-names = "fck"; - }; - - sham: sham@53100000 { - compatible = "ti,omap5-sham"; - ti,hwmods = "sham"; - reg = <0x4b101000 0x300>; - interrupts = ; - dmas = <&edma_xbar 119 0>; - dma-names = "rx"; - clocks = <&l3_iclk_div>; - clock-names = "fck"; - }; - - opp_supply_mpu: opp-supply@4a003b20 { - compatible = "ti,omap5-opp-supply"; - reg = <0x4a003b20 0xc>; - ti,efuse-settings = < - /* uV offset */ - 1060000 0x0 - 1160000 0x4 - 1210000 0x8 - >; - ti,absolute-max-voltage-uv = <1500000>; - }; - - }; - - thermal_zones: thermal-zones { - #include "omap4-cpu-thermal.dtsi" - #include "omap5-gpu-thermal.dtsi" - #include "omap5-core-thermal.dtsi" - #include "dra7-dspeve-thermal.dtsi" - #include "dra7-iva-thermal.dtsi" - }; - -}; - -&cpu_thermal { - polling-delay = <500>; /* milliseconds */ - coefficients = <0 2000>; -}; - -&gpu_thermal { - coefficients = <0 2000>; -}; - -&core_thermal { - coefficients = <0 2000>; -}; - -&dspeve_thermal { - coefficients = <0 2000>; -}; - -&iva_thermal { - coefficients = <0 2000>; -}; - -&cpu_crit { - temperature = <120000>; /* milli Celsius */ -}; - -&core_crit { - temperature = <120000>; /* milli Celsius */ -}; - -&gpu_crit { - temperature = <120000>; /* milli Celsius */ -}; - -&dspeve_crit { - temperature = <120000>; /* milli Celsius */ -}; - -&iva_crit { - temperature = <120000>; /* milli Celsius */ -}; - -#include "dra7-l4.dtsi" -#include "dra7xx-clocks.dtsi" diff --git a/sys/gnu/dts/arm/dra71-evm.dts b/sys/gnu/dts/arm/dra71-evm.dts deleted file mode 100644 index fabeb770475..00000000000 --- a/sys/gnu/dts/arm/dra71-evm.dts +++ /dev/null @@ -1,272 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - */ - -#include "dra71x.dtsi" -#include "dra7-mmc-iodelay.dtsi" -#include "dra72x-mmc-iodelay.dtsi" -#include - -/ { - compatible = "ti,dra718-evm", "ti,dra718", "ti,dra722", "ti,dra72", "ti,dra7"; - model = "TI DRA718 EVM"; - - memory { - device_type = "memory"; - reg = <0x0 0x80000000 0x0 0x80000000>; /* 2GB */ - }; - - vpo_sd_1v8_3v3: gpio-regulator-TPS74801 { - compatible = "regulator-gpio"; - - regulator-name = "vddshv8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - vin-supply = <&evm_5v0>; - - gpios = <&gpio7 11 GPIO_ACTIVE_HIGH>; - states = <1800000 0x0 - 3300000 0x1>; - }; - - evm_1v8_sw: fixedregulator-evm_1v8 { - compatible = "regulator-fixed"; - regulator-name = "evm_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&lp8732_buck0_reg>; - regulator-always-on; - regulator-boot-on; - }; - - poweroff: gpio-poweroff { - compatible = "gpio-poweroff"; - gpios = <&gpio7 30 GPIO_ACTIVE_HIGH>; - input; - }; -}; - -&i2c1 { - status = "okay"; - clock-frequency = <400000>; - - lp8733: lp8733@60 { - compatible = "ti,lp8733"; - reg = <0x60>; - - buck0-in-supply =<&vsys_3v3>; - buck1-in-supply =<&vsys_3v3>; - ldo0-in-supply =<&evm_5v0>; - ldo1-in-supply =<&evm_5v0>; - - lp8733_regulators: regulators { - lp8733_buck0_reg: buck0 { - /* FB_B0 -> LP8733-BUCK1 - VPO_S1_AVS - VDD_CORE_AVS (core, mpu, gpu) */ - regulator-name = "lp8733-buck0"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1250000>; - regulator-always-on; - regulator-boot-on; - }; - - lp8733_buck1_reg: buck1 { - /* FB_B1 -> LP8733-BUCK2 - VPO_S2_AVS - VDD_DSP_AVS (DSP/eve/iva) */ - regulator-name = "lp8733-buck1"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1250000>; - regulator-boot-on; - regulator-always-on; - }; - - lp8733_ldo0_reg: ldo0 { - /* LDO0 -> LP8733-LDO1 - VPO_L1_3V3 - VDDSHV8 (optional) */ - regulator-name = "lp8733-ldo0"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - lp8733_ldo1_reg: ldo1 { - /* LDO1 -> LP8733-LDO2 - VPO_L2_3V3 - VDDA_USB3V3 */ - regulator-name = "lp8733-ldo1"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - }; - }; - - lp8732: lp8732@61 { - compatible = "ti,lp8732"; - reg = <0x61>; - - buck0-in-supply =<&vsys_3v3>; - buck1-in-supply =<&vsys_3v3>; - ldo0-in-supply =<&vsys_3v3>; - ldo1-in-supply =<&vsys_3v3>; - - lp8732_regulators: regulators { - lp8732_buck0_reg: buck0 { - /* FB_B0 -> LP8732-BUCK1 - VPO_S3_1V8 - VDDS_1V8 */ - regulator-name = "lp8732-buck0"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - lp8732_buck1_reg: buck1 { - /* FB_B1 -> LP8732-BUCK2 - VPO_S4_DDR - VDD_DDR_1V35 */ - regulator-name = "lp8732-buck1"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-boot-on; - regulator-always-on; - }; - - lp8732_ldo0_reg: ldo0 { - /* LDO0 -> LP8732-LDO1 - VPO_L3_1V8 - VDA_1V8_PLL */ - regulator-name = "lp8732-ldo0"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - lp8732_ldo1_reg: ldo1 { - /* LDO1 -> LP8732-LDO2 - VPO_L4_1V8 - VDA_1V8_PHY */ - regulator-name = "lp8732-ldo1"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - }; - }; -}; - -&pcf_lcd { - interrupt-parent = <&gpio7>; - interrupts = <31 IRQ_TYPE_EDGE_FALLING>; -}; - -&pcf_gpio_21 { - interrupt-parent = <&gpio7>; - interrupts = <31 IRQ_TYPE_EDGE_FALLING>; -}; - -&pcf_hdmi { - p0 { - /* - * PM_OEn to High: Disable routing I2C3 to PM_I2C - * With this PM_SEL(p3) should not matter - */ - gpio-hog; - gpios = <0 GPIO_ACTIVE_LOW>; - output-high; - line-name = "pm_oe_n"; - }; -}; - -&mmc1 { - pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104"; - pinctrl-0 = <&mmc1_pins_default_no_clk_pu>; - pinctrl-1 = <&mmc1_pins_hs>; - pinctrl-2 = <&mmc1_pins_sdr12>; - pinctrl-3 = <&mmc1_pins_sdr25>; - pinctrl-4 = <&mmc1_pins_sdr50>; - pinctrl-5 = <&mmc1_pins_ddr50_rev20 &mmc1_iodelay_ddr50_conf>; - pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>; - vqmmc-supply = <&vpo_sd_1v8_3v3>; -}; - -&mmc2 { - pinctrl-names = "default", "hs", "ddr_1_8v", "hs200_1_8v"; - pinctrl-0 = <&mmc2_pins_default>; - pinctrl-1 = <&mmc2_pins_hs>; - pinctrl-2 = <&mmc2_pins_ddr_rev20 &mmc2_iodelay_ddr_conf>; - pinctrl-3 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev20_conf>; - vmmc-supply = <&evm_1v8_sw>; - vqmmc-supply = <&evm_1v8_sw>; -}; - -&mac { - mode-gpios = <&pcf_gpio_21 4 GPIO_ACTIVE_LOW>, - <&pcf_hdmi 9 GPIO_ACTIVE_LOW>, /* P11 */ - <&pcf_hdmi 10 GPIO_ACTIVE_LOW>; /* P12 */ - dual_emac; -}; - -&cpsw_emac0 { - phy-handle = <&dp83867_0>; - phy-mode = "rgmii-id"; - dual_emac_res_vlan = <1>; -}; - -&cpsw_emac1 { - phy-handle = <&dp83867_1>; - phy-mode = "rgmii-id"; - dual_emac_res_vlan = <2>; -}; - -&davinci_mdio { - dp83867_0: ethernet-phy@2 { - reg = <2>; - ti,rx-internal-delay = ; - ti,tx-internal-delay = ; - ti,fifo-depth = ; - ti,min-output-impedance; - ti,dp83867-rxctrl-strap-quirk; - }; - - dp83867_1: ethernet-phy@3 { - reg = <3>; - ti,rx-internal-delay = ; - ti,tx-internal-delay = ; - ti,fifo-depth = ; - ti,min-output-impedance; - ti,dp83867-rxctrl-strap-quirk; - }; -}; - -/* No Sata on this device */ -&sata_phy { - status = "disabled"; -}; - -&sata { - status = "disabled"; -}; - -/* No RTC on this device */ -&rtc { - status = "disabled"; -}; - -&usb2_phy1 { - phy-supply = <&lp8733_ldo1_reg>; -}; - -&usb2_phy2 { - phy-supply = <&lp8733_ldo1_reg>; -}; - -&dss { - /* Supplied by VDA_1V8_PLL */ - vdda_video-supply = <&lp8732_ldo0_reg>; -}; - -&hdmi { - /* Supplied by VDA_1V8_PHY */ - vdda_video-supply = <&lp8732_ldo1_reg>; -}; - -&extcon_usb1 { - vbus-gpio = <&pcf_lcd 14 GPIO_ACTIVE_HIGH>; -}; - -&extcon_usb2 { - vbus-gpio = <&pcf_lcd 15 GPIO_ACTIVE_HIGH>; -}; diff --git a/sys/gnu/dts/arm/dra71x.dtsi b/sys/gnu/dts/arm/dra71x.dtsi deleted file mode 100644 index 695a08ed036..00000000000 --- a/sys/gnu/dts/arm/dra71x.dtsi +++ /dev/null @@ -1,17 +0,0 @@ -/* - * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include "dra72-evm-common.dtsi" - -&rtctarget { - status = "disabled"; -}; - -&usb4_tm { - status = "disabled"; -}; diff --git a/sys/gnu/dts/arm/dra72-evm-common.dtsi b/sys/gnu/dts/arm/dra72-evm-common.dtsi deleted file mode 100644 index 8641a3d7d8a..00000000000 --- a/sys/gnu/dts/arm/dra72-evm-common.dtsi +++ /dev/null @@ -1,582 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/ - */ -/dts-v1/; - -#include "dra72x.dtsi" -#include -#include - -/ { - compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7"; - - aliases { - display0 = &hdmi0; - }; - - chosen { - stdout-path = &uart1; - }; - - evm_12v0: fixedregulator-evm12v0 { - /* main supply */ - compatible = "regulator-fixed"; - regulator-name = "evm_12v0"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-always-on; - regulator-boot-on; - }; - - evm_5v0: fixedregulator-evm5v0 { - /* Output 1 of TPS43351QDAPRQ1 on dra72-evm */ - /* Output 1 of LM5140QRWGTQ1 on dra71-evm */ - compatible = "regulator-fixed"; - regulator-name = "evm_5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&evm_12v0>; - regulator-always-on; - regulator-boot-on; - }; - - evm_3v6: fixedregulator-evm_3v6 { - compatible = "regulator-fixed"; - regulator-name = "evm_3v6"; - regulator-min-microvolt = <3600000>; - regulator-max-microvolt = <3600000>; - vin-supply = <&evm_5v0>; - regulator-always-on; - regulator-boot-on; - }; - - vsys_3v3: fixedregulator-vsys3v3 { - /* Output 2 of TPS43351QDAPRQ1 on dra72-evm */ - /* Output 2 of LM5140QRWGTQ1 on dra71-evm */ - compatible = "regulator-fixed"; - regulator-name = "vsys_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&evm_12v0>; - regulator-always-on; - regulator-boot-on; - }; - - evm_3v3_sw: fixedregulator-evm_3v3 { - /* TPS22965DSG */ - compatible = "regulator-fixed"; - regulator-name = "evm_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vsys_3v3>; - regulator-always-on; - regulator-boot-on; - }; - - aic_dvdd: fixedregulator-aic_dvdd { - /* TPS77018DBVT */ - compatible = "regulator-fixed"; - regulator-name = "aic_dvdd"; - vin-supply = <&evm_3v3_sw>; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - evm_3v3_sd: fixedregulator-sd { - compatible = "regulator-fixed"; - regulator-name = "evm_3v3_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&evm_3v3_sw>; - enable-active-high; - gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>; - }; - - extcon_usb1: extcon_usb1 { - compatible = "linux,extcon-usb-gpio"; - id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>; - }; - - extcon_usb2: extcon_usb2 { - compatible = "linux,extcon-usb-gpio"; - id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>; - }; - - hdmi0: connector { - compatible = "hdmi-connector"; - label = "hdmi"; - - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&tpd12s015_out>; - }; - }; - }; - - tpd12s015: encoder { - compatible = "ti,tpd12s015"; - - gpios = <&pcf_hdmi 4 GPIO_ACTIVE_HIGH>, /* P4, CT CP HPD */ - <&pcf_hdmi 5 GPIO_ACTIVE_HIGH>, /* P5, LS OE */ - <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */ - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - tpd12s015_in: endpoint { - remote-endpoint = <&hdmi_out>; - }; - }; - - port@1 { - reg = <1>; - - tpd12s015_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; - }; - }; - }; - - sound0: sound0 { - compatible = "simple-audio-card"; - simple-audio-card,name = "DRA7xx-EVM"; - simple-audio-card,widgets = - "Headphone", "Headphone Jack", - "Line", "Line Out", - "Microphone", "Mic Jack", - "Line", "Line In"; - simple-audio-card,routing = - "Headphone Jack", "HPLOUT", - "Headphone Jack", "HPROUT", - "Line Out", "LLOUT", - "Line Out", "RLOUT", - "MIC3L", "Mic Jack", - "MIC3R", "Mic Jack", - "Mic Jack", "Mic Bias", - "LINE1L", "Line In", - "LINE1R", "Line In"; - simple-audio-card,format = "dsp_b"; - simple-audio-card,bitclock-master = <&sound0_master>; - simple-audio-card,frame-master = <&sound0_master>; - simple-audio-card,bitclock-inversion; - - sound0_master: simple-audio-card,cpu { - sound-dai = <&mcasp3>; - system-clock-frequency = <5644800>; - }; - - simple-audio-card,codec { - sound-dai = <&tlv320aic3106>; - clocks = <&atl_clkin2_ck>; - }; - }; - - vmmcwl_fixed: fixedregulator-mmcwl { - compatible = "regulator-fixed"; - regulator-name = "vmmcwl_fixed"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio5 8 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&dra7_pmx_core { - dcan1_pins_default: dcan1_pins_default { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */ - DRA7XX_CORE_IOPAD(0x3818, PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */ - >; - }; - - dcan1_pins_sleep: dcan1_pins_sleep { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x37d0, MUX_MODE15 | PULL_UP) /* dcan1_tx.off */ - DRA7XX_CORE_IOPAD(0x3818, MUX_MODE15 | PULL_UP) /* wakeup0.off */ - >; - }; -}; - -&i2c1 { - status = "okay"; - clock-frequency = <400000>; - - pcf_lcd: gpio@20 { - compatible = "nxp,pcf8575"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - pcf_gpio_21: gpio@21 { - compatible = "ti,pcf8575", "nxp,pcf8575"; - reg = <0x21>; - lines-initial-states = <0x1408>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - tlv320aic3106: tlv320aic3106@19 { - #sound-dai-cells = <0>; - compatible = "ti,tlv320aic3106"; - reg = <0x19>; - adc-settle-ms = <40>; - ai3x-micbias-vg = <1>; /* 2.0V */ - status = "okay"; - - /* Regulators */ - AVDD-supply = <&evm_3v3_sw>; - IOVDD-supply = <&evm_3v3_sw>; - DRVDD-supply = <&evm_3v3_sw>; - DVDD-supply = <&aic_dvdd>; - }; -}; - -&i2c5 { - status = "okay"; - clock-frequency = <400000>; - - pcf_hdmi: pcf8575@26 { - compatible = "ti,pcf8575", "nxp,pcf8575"; - reg = <0x26>; - gpio-controller; - #gpio-cells = <2>; - /* - * initial state is used here to keep the mdio interface - * selected on RU89 through SEL_VIN4_MUX_S0, VIN2_S1 and - * VIN2_S0 driven high otherwise Ethernet stops working - * VIN6_SEL_S0 is low, thus selecting McASP3 over VIN6 - */ - lines-initial-states = <0x0f2b>; - - p1 { - /* vin6_sel_s0: high: VIN6, low: audio */ - gpio-hog; - gpios = <1 GPIO_ACTIVE_HIGH>; - output-low; - line-name = "vin6_sel_s0"; - }; - }; -}; - -&uart1 { - status = "okay"; - interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, - <&dra7_pmx_core 0x3e0>; -}; - -&elm { - status = "okay"; -}; - -&gpmc { - /* - * For the existing IOdelay configuration via U-Boot we don't - * support NAND on dra72-evm. Keep it disabled. Enabling it - * requires a different configuration by U-Boot. - */ - status = "disabled"; - ranges = <0 0 0x08000000 0x01000000>; /* minimum GPMC partition = 16MB */ - nand@0,0 { - /* To use NAND, DIP switch SW5 must be set like so: - * SW5.1 (NAND_SELn) = ON (LOW) - * SW5.9 (GPMC_WPN) = OFF (HIGH) - */ - compatible = "ti,omap2-nand"; - reg = <0 0 4>; /* device IO registers */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ - <1 IRQ_TYPE_NONE>; /* termcount */ - rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */ - ti,nand-xfer-type = "prefetch-dma"; - ti,nand-ecc-opt = "bch8"; - ti,elm-id = <&elm>; - nand-bus-width = <16>; - gpmc,device-width = <2>; - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <80>; - gpmc,cs-wr-off-ns = <80>; - gpmc,adv-on-ns = <0>; - gpmc,adv-rd-off-ns = <60>; - gpmc,adv-wr-off-ns = <60>; - gpmc,we-on-ns = <10>; - gpmc,we-off-ns = <50>; - gpmc,oe-on-ns = <4>; - gpmc,oe-off-ns = <40>; - gpmc,access-ns = <40>; - gpmc,wr-access-ns = <80>; - gpmc,rd-cycle-ns = <80>; - gpmc,wr-cycle-ns = <80>; - gpmc,bus-turnaround-ns = <0>; - gpmc,cycle2cycle-delay-ns = <0>; - gpmc,clk-activation-ns = <0>; - gpmc,wr-data-mux-bus-ns = <0>; - /* MTD partition table */ - /* All SPL-* partitions are sized to minimal length - * which can be independently programmable. For - * NAND flash this is equal to size of erase-block */ - #address-cells = <1>; - #size-cells = <1>; - partition@0 { - label = "NAND.SPL"; - reg = <0x00000000 0x000020000>; - }; - partition@1 { - label = "NAND.SPL.backup1"; - reg = <0x00020000 0x00020000>; - }; - partition@2 { - label = "NAND.SPL.backup2"; - reg = <0x00040000 0x00020000>; - }; - partition@3 { - label = "NAND.SPL.backup3"; - reg = <0x00060000 0x00020000>; - }; - partition@4 { - label = "NAND.u-boot-spl-os"; - reg = <0x00080000 0x00040000>; - }; - partition@5 { - label = "NAND.u-boot"; - reg = <0x000c0000 0x00100000>; - }; - partition@6 { - label = "NAND.u-boot-env"; - reg = <0x001c0000 0x00020000>; - }; - partition@7 { - label = "NAND.u-boot-env.backup1"; - reg = <0x001e0000 0x00020000>; - }; - partition@8 { - label = "NAND.kernel"; - reg = <0x00200000 0x00800000>; - }; - partition@9 { - label = "NAND.file-system"; - reg = <0x00a00000 0x0f600000>; - }; - }; -}; - -&omap_dwc3_1 { - extcon = <&extcon_usb1>; -}; - -&omap_dwc3_2 { - extcon = <&extcon_usb2>; -}; - -&usb1 { - dr_mode = "otg"; - extcon = <&extcon_usb1>; -}; - -&usb2 { - dr_mode = "host"; - extcon = <&extcon_usb2>; -}; - -&mmc1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins_default>; - vmmc-supply = <&evm_3v3_sd>; - bus-width = <4>; - /* - * SDCD signal is not being used here - using the fact that GPIO mode - * is a viable alternative - */ - cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; - max-frequency = <192000000>; -}; - -&mmc2 { - /* SW5-3 in ON position */ - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins_default>; - bus-width = <8>; - non-removable; - max-frequency = <192000000>; -}; - -&mmc4 { - status = "okay"; - vmmc-supply = <&evm_3v6>; - vqmmc-supply = <&vmmcwl_fixed>; - bus-width = <4>; - cap-power-off-card; - keep-power-in-suspend; - non-removable; - pinctrl-names = "default", "hs", "sdr12", "sdr25"; - pinctrl-0 = <&mmc4_pins_default>; - pinctrl-1 = <&mmc4_pins_default>; - pinctrl-2 = <&mmc4_pins_default>; - pinctrl-3 = <&mmc4_pins_default>; - #address-cells = <1>; - #size-cells = <0>; - wifi@2 { - compatible = "ti,wl1835"; - reg = <2>; - interrupt-parent = <&gpio5>; - interrupts = <7 IRQ_TYPE_EDGE_RISING>; - }; -}; - -&mac { - status = "okay"; -}; - -&dcan1 { - status = "ok"; - pinctrl-names = "default", "sleep", "active"; - pinctrl-0 = <&dcan1_pins_sleep>; - pinctrl-1 = <&dcan1_pins_sleep>; - pinctrl-2 = <&dcan1_pins_default>; -}; - -&qspi { - status = "okay"; - - spi-max-frequency = <76800000>; - m25p80@0 { - compatible = "s25fl256s1"; - spi-max-frequency = <76800000>; - reg = <0>; - spi-tx-bus-width = <1>; - spi-rx-bus-width = <4>; - #address-cells = <1>; - #size-cells = <1>; - - /* MTD partition table. - * The ROM checks the first four physical blocks - * for a valid file to boot and the flash here is - * 64KiB block size. - */ - partition@0 { - label = "QSPI.SPL"; - reg = <0x00000000 0x000010000>; - }; - partition@1 { - label = "QSPI.SPL.backup1"; - reg = <0x00010000 0x00010000>; - }; - partition@2 { - label = "QSPI.SPL.backup2"; - reg = <0x00020000 0x00010000>; - }; - partition@3 { - label = "QSPI.SPL.backup3"; - reg = <0x00030000 0x00010000>; - }; - partition@4 { - label = "QSPI.u-boot"; - reg = <0x00040000 0x00100000>; - }; - partition@5 { - label = "QSPI.u-boot-spl-os"; - reg = <0x00140000 0x00080000>; - }; - partition@6 { - label = "QSPI.u-boot-env"; - reg = <0x001c0000 0x00010000>; - }; - partition@7 { - label = "QSPI.u-boot-env.backup1"; - reg = <0x001d0000 0x0010000>; - }; - partition@8 { - label = "QSPI.kernel"; - reg = <0x001e0000 0x0800000>; - }; - partition@9 { - label = "QSPI.file-system"; - reg = <0x009e0000 0x01620000>; - }; - }; -}; - -&dss { - status = "ok"; -}; - -&hdmi { - status = "ok"; - - port { - hdmi_out: endpoint { - remote-endpoint = <&tpd12s015_in>; - }; - }; -}; - -&atl { - assigned-clocks = <&abe_dpll_sys_clk_mux>, - <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>, - <&dpll_abe_ck>, - <&dpll_abe_m2x2_ck>, - <&atl_clkin2_ck>; - assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>; - assigned-clock-rates = <0>, <0>, <180633600>, <361267200>, <5644800>; - - status = "okay"; - - atl2 { - bws = ; - aws = ; - }; -}; - -&mcasp3 { - #sound-dai-cells = <0>; - - assigned-clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>; - assigned-clock-parents = <&atl_clkin2_ck>; - - status = "okay"; - - op-mode = <0>; /* MCASP_IIS_MODE */ - tdm-slots = <2>; - /* 4 serializer */ - serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ - 1 2 0 0 - >; - tx-num-evt = <32>; - rx-num-evt = <32>; -}; - -&mailbox5 { - status = "okay"; - mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { - status = "okay"; - }; - mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { - status = "okay"; - }; -}; - -&mailbox6 { - status = "okay"; - mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { - status = "okay"; - }; -}; - -&pcie1_rc { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/dra72-evm-revc.dts b/sys/gnu/dts/arm/dra72-evm-revc.dts deleted file mode 100644 index 2bb2e8be627..00000000000 --- a/sys/gnu/dts/arm/dra72-evm-revc.dts +++ /dev/null @@ -1,115 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - */ -#include "dra72-evm-common.dtsi" -#include "dra72x-mmc-iodelay.dtsi" -#include - -/ { - model = "TI DRA722 Rev C EVM"; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x80000000 0x0 0x80000000>; /* 2GB */ - }; - - evm_1v8_sw: fixedregulator-evm_1v8 { - compatible = "regulator-fixed"; - regulator-name = "evm_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&smps4_reg>; - regulator-always-on; - regulator-boot-on; - }; -}; - -&i2c1 { - tps65917: tps65917@58 { - reg = <0x58>; - - interrupts = ; /* IRQ_SYS_1N */ - }; -}; - -#include "dra72-evm-tps65917.dtsi" - -&ldo2_reg { - /* LDO2_OUT --> VDDA_1V8_PHY2 */ - regulator-always-on; - regulator-boot-on; -}; - -&hdmi { - vdda-supply = <&ldo2_reg>; -}; - -&pcf_gpio_21 { - interrupt-parent = <&gpio3>; - interrupts = <30 IRQ_TYPE_EDGE_FALLING>; -}; - -&mac { - mode-gpios = <&pcf_gpio_21 4 GPIO_ACTIVE_LOW>, - <&pcf_hdmi 9 GPIO_ACTIVE_LOW>, /* P11 */ - <&pcf_hdmi 10 GPIO_ACTIVE_LOW>; /* P12 */ - dual_emac; -}; - -&cpsw_emac0 { - phy-handle = <&dp83867_0>; - phy-mode = "rgmii-id"; - dual_emac_res_vlan = <1>; -}; - -&cpsw_emac1 { - phy-handle = <&dp83867_1>; - phy-mode = "rgmii-id"; - dual_emac_res_vlan = <2>; -}; - -&davinci_mdio { - dp83867_0: ethernet-phy@2 { - reg = <2>; - ti,rx-internal-delay = ; - ti,tx-internal-delay = ; - ti,fifo-depth = ; - ti,min-output-impedance; - interrupt-parent = <&gpio6>; - interrupts = <16 IRQ_TYPE_EDGE_FALLING>; - ti,dp83867-rxctrl-strap-quirk; - }; - - dp83867_1: ethernet-phy@3 { - reg = <3>; - ti,rx-internal-delay = ; - ti,tx-internal-delay = ; - ti,fifo-depth = ; - ti,min-output-impedance; - interrupt-parent = <&gpio6>; - interrupts = <16 IRQ_TYPE_EDGE_FALLING>; - ti,dp83867-rxctrl-strap-quirk; - }; -}; - -&mmc1 { - pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104"; - pinctrl-0 = <&mmc1_pins_default>; - pinctrl-1 = <&mmc1_pins_hs>; - pinctrl-2 = <&mmc1_pins_sdr12>; - pinctrl-3 = <&mmc1_pins_sdr25>; - pinctrl-4 = <&mmc1_pins_sdr50>; - pinctrl-5 = <&mmc1_pins_ddr50_rev20 &mmc1_iodelay_ddr50_conf>; - pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>; - vqmmc-supply = <&ldo1_reg>; -}; - -&mmc2 { - pinctrl-names = "default", "hs", "ddr_1_8v", "hs200_1_8v"; - pinctrl-0 = <&mmc2_pins_default>; - pinctrl-1 = <&mmc2_pins_hs>; - pinctrl-2 = <&mmc2_pins_ddr_rev20 &mmc2_iodelay_ddr_conf>; - pinctrl-3 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev20_conf>; - vmmc-supply = <&evm_1v8_sw>; -}; diff --git a/sys/gnu/dts/arm/dra72-evm-tps65917.dtsi b/sys/gnu/dts/arm/dra72-evm-tps65917.dtsi deleted file mode 100644 index 5ff9c43ef30..00000000000 --- a/sys/gnu/dts/arm/dra72-evm-tps65917.dtsi +++ /dev/null @@ -1,151 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - */ - -/* - * Integrated Power Management Chip - * http://www.ti.com/lit/ds/symlink/tps65917-q1.pdf - */ - -&tps65917 { - compatible = "ti,tps65917"; - - interrupt-controller; - #interrupt-cells = <2>; - - ti,system-power-controller; - - tps65917_pmic { - compatible = "ti,tps65917-pmic"; - - smps1-in-supply = <&vsys_3v3>; - smps2-in-supply = <&vsys_3v3>; - smps3-in-supply = <&vsys_3v3>; - smps4-in-supply = <&vsys_3v3>; - smps5-in-supply = <&vsys_3v3>; - ldo1-in-supply = <&vsys_3v3>; - ldo2-in-supply = <&vsys_3v3>; - ldo3-in-supply = <&vsys_3v3>; - ldo4-in-supply = <&evm_5v0>; - ldo5-in-supply = <&vsys_3v3>; - - tps65917_regulators: regulators { - smps1_reg: smps1 { - /* VDD_MPU */ - regulator-name = "smps1"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1250000>; - regulator-always-on; - regulator-boot-on; - }; - - smps2_reg: smps2 { - /* VDD_CORE */ - regulator-name = "smps2"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1150000>; - regulator-boot-on; - regulator-always-on; - }; - - smps3_reg: smps3 { - /* VDD_GPU IVA DSPEVE */ - regulator-name = "smps3"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1250000>; - regulator-boot-on; - regulator-always-on; - }; - - smps4_reg: smps4 { - /* VDDS1V8 */ - regulator-name = "smps4"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - smps5_reg: smps5 { - /* VDD_DDR */ - regulator-name = "smps5"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1_reg: ldo1 { - /* LDO1_OUT --> SDIO */ - regulator-name = "ldo1"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - regulator-allow-bypass; - }; - - ldo2_reg: ldo2 { - regulator-name = "ldo2"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-allow-bypass; - }; - - ldo3_reg: ldo3 { - /* VDDA_1V8_PHY */ - regulator-name = "ldo3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo5_reg: ldo5 { - /* VDDA_1V8_PLL */ - regulator-name = "ldo5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo4_reg: ldo4 { - /* VDDA_3V_USB: VDDA_USBHS33 */ - regulator-name = "ldo4"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; - }; - }; - - tps65917_power_button { - compatible = "ti,palmas-pwrbutton"; - interrupt-parent = <&tps65917>; - interrupts = <1 IRQ_TYPE_NONE>; - wakeup-source; - ti,palmas-long-press-seconds = <6>; - }; -}; - -&usb2_phy1 { - phy-supply = <&ldo4_reg>; -}; - -&usb2_phy2 { - phy-supply = <&ldo4_reg>; -}; - -&dss { - vdda_video-supply = <&ldo5_reg>; -}; - -&mmc1 { - vqmmc-supply = <&ldo1_reg>; -}; - -&cpu0 { - vdd-supply = <&smps1_reg>; -}; diff --git a/sys/gnu/dts/arm/dra72-evm.dts b/sys/gnu/dts/arm/dra72-evm.dts deleted file mode 100644 index 9adb77585ef..00000000000 --- a/sys/gnu/dts/arm/dra72-evm.dts +++ /dev/null @@ -1,80 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/ - */ -#include "dra72-evm-common.dtsi" -#include "dra72x-mmc-iodelay.dtsi" -/ { - model = "TI DRA722"; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x80000000 0x0 0x40000000>; /* 1024 MB */ - }; - - evm_1v8_sw: fixedregulator-evm_1v8 { - compatible = "regulator-fixed"; - regulator-name = "evm_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&smps4_reg>; - regulator-always-on; - regulator-boot-on; - }; -}; - -&i2c1 { - tps65917: tps65917@58 { - reg = <0x58>; - - interrupts = ; /* IRQ_SYS_1N */ - }; -}; - -#include "dra72-evm-tps65917.dtsi" - -&hdmi { - vdda-supply = <&ldo3_reg>; -}; - -&pcf_gpio_21 { - interrupt-parent = <&gpio6>; - interrupts = <11 IRQ_TYPE_EDGE_FALLING>; -}; - -&mac { - slaves = <1>; - mode-gpios = <&pcf_gpio_21 4 GPIO_ACTIVE_HIGH>; -}; - -&cpsw_emac0 { - phy-handle = <ðphy0>; - phy-mode = "rgmii"; -}; - -&davinci_mdio { - ethphy0: ethernet-phy@3 { - reg = <3>; - }; -}; - -&mmc1 { - pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104"; - pinctrl-0 = <&mmc1_pins_default>; - pinctrl-1 = <&mmc1_pins_hs>; - pinctrl-2 = <&mmc1_pins_sdr12>; - pinctrl-3 = <&mmc1_pins_sdr25>; - pinctrl-4 = <&mmc1_pins_sdr50>; - pinctrl-5 = <&mmc1_pins_ddr50_rev10>; - pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev10_conf>; - vqmmc-supply = <&ldo1_reg>; -}; - -&mmc2 { - pinctrl-names = "default", "hs", "ddr_1_8v", "hs200_1_8v"; - pinctrl-0 = <&mmc2_pins_default>; - pinctrl-1 = <&mmc2_pins_hs>; - pinctrl-2 = <&mmc2_pins_ddr_rev10>; - pinctrl-3 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev10_conf>; - vmmc-supply = <&evm_1v8_sw>; -}; diff --git a/sys/gnu/dts/arm/dra72x-mmc-iodelay.dtsi b/sys/gnu/dts/arm/dra72x-mmc-iodelay.dtsi deleted file mode 100644 index edad87c4292..00000000000 --- a/sys/gnu/dts/arm/dra72x-mmc-iodelay.dtsi +++ /dev/null @@ -1,361 +0,0 @@ -/* - * MMC IOdelay values for TI's DRA72x, DRA71x and AM571x SoCs. - * - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* - * Rules for modifying this file: - * a) Update of this file should typically correspond to a datamanual revision. - * Datamanual revision that was used should be updated in comment below. - * If there is no update to datamanual, do not update the values. If you - * need to use values different from that recommended by the datamanual - * for your design, then you should consider adding values to the device- - * -tree file for your board directly. - * b) We keep the mode names as close to the datamanual as possible. So - * if the manual calls a mode, DDR50, or DDR or DDR 1.8v or DDR 3.3v, - * we follow that in code too. - * c) If the values change between multiple revisions of silicon, we add - * a revision tag to both the new and old entry. Use 'rev10' for PG 1.0, - * 'rev20' for PG 2.0 and so on. - * d) The node name and node label should be the exact same string. This is - * to curb naming creativity and achieve consistency. - * e) If in future, DRA71x and DRA72x values differ, then add 'dra71_' and - * 'dra72_' tag to entries. Both the new and old entries should gain a tag. - * - * Datamanual Revisions: - * - * AM571x Silicon Revision 2.0: SPRS957D, Revised January 2017 - * AM571x Silicon Revision 1.0: SPRS919M, Revised November 2017 - * DRA71x : SPRS960B, Revised February 2017 - */ - -&dra7_pmx_core { - mmc1_pins_default: mmc1_pins_default { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ - DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ - DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ - DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ - DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ - DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ - >; - }; - - mmc1_pins_sdr12: mmc1_pins_sdr12 { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ - DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ - DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ - DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ - DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ - DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ - >; - }; - - mmc1_pins_hs: mmc1_pins_hs { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ - DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ - DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ - DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ - DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ - DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ - >; - }; - - mmc1_pins_sdr25: mmc1_pins_sdr25 { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ - DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ - DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ - DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ - DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ - DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ - >; - }; - - mmc1_pins_sdr50: mmc1_pins_sdr50 { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_clk.clk */ - DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_cmd.cmd */ - DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_dat0.dat0 */ - DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_dat1.dat1 */ - DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_dat2.dat2 */ - DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_dat3.dat3 */ - >; - }; - - mmc1_pins_ddr50_rev10: mmc1_pins_ddr50_rev10 { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0) /* mmc1_clk.mmc1_clk */ - DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0) /* mmc1_cmd.mmc1_cmd */ - DRA7XX_CORE_IOPAD(0x375C, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0) /* mmc1_dat0.mmc1_dat0 */ - DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0) /* mmc1_dat1.mmc1_dat1 */ - DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0) /* mmc1_dat2.mmc1_dat2 */ - DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0) /* mmc1_dat3.mmc1_dat3 */ - >; - }; - - mmc1_pins_ddr50_rev20: mmc1_pins_ddr50_rev20 { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_clk.clk */ - DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_cmd.cmd */ - DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat0.dat0 */ - DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat1.dat1 */ - DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat2.dat2 */ - DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat3.dat3 */ - >; - }; - - mmc1_pins_sdr104: mmc1_pins_sdr104 { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_clk.clk */ - DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_cmd.cmd */ - DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat0.dat0 */ - DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat1.dat1 */ - DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat2.dat2 */ - DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat3.dat3 */ - >; - }; - - mmc2_pins_default: mmc2_pins_default { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ - DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ - DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ - DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ - DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ - DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ - DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ - DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ - DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ - DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ - >; - }; - - mmc2_pins_hs: mmc2_pins_hs { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ - DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ - DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ - DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ - DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ - DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ - DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ - DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ - DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ - DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ - >; - }; - - mmc2_pins_ddr_rev10: mmc2_pins_ddr_rev10 { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ - DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ - DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ - DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ - DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ - DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ - DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ - DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ - DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ - DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ - >; - }; - - mmc2_pins_ddr_rev20: mmc2_pins_ddr_rev20 { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */ - DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ - DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ - DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ - DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ - DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ - DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ - DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ - DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ - DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ - >; - }; - - mmc2_pins_hs200: mmc2_pins_hs200 { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */ - DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ - DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ - DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ - DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ - DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ - DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ - DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ - DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ - DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ - >; - }; - - mmc4_pins_default: mmc4_pins_default { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_ctsn.mmc4_clk */ - DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */ - DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */ - DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_txd.mmc4_dat1 */ - DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */ - DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */ - >; - }; -}; - -&dra7_iodelay_core { - - /* Corresponds to MMC1_MANUAL1 in datamanual */ - mmc1_iodelay_ddr50_conf: mmc1_iodelay_ddr50_conf { - pinctrl-pin-array = < - 0x618 A_DELAY_PS(588) G_DELAY_PS(0) /* CFG_MMC1_CLK_IN */ - 0x624 A_DELAY_PS(1000) G_DELAY_PS(0) /* CFG_MMC1_CMD_IN */ - 0x630 A_DELAY_PS(1375) G_DELAY_PS(0) /* CFG_MMC1_DAT0_IN */ - 0x63C A_DELAY_PS(1000) G_DELAY_PS(0) /* CFG_MMC1_DAT1_IN */ - 0x648 A_DELAY_PS(1000) G_DELAY_PS(0) /* CFG_MMC1_DAT2_IN */ - 0x654 A_DELAY_PS(1000) G_DELAY_PS(0) /* CFG_MMC1_DAT3_IN */ - 0x620 A_DELAY_PS(1230) G_DELAY_PS(0) /* CFG_MMC1_CLK_OUT */ - 0x62C A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */ - 0x638 A_DELAY_PS(56) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OUT */ - 0x644 A_DELAY_PS(76) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */ - 0x650 A_DELAY_PS(91) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */ - 0x65C A_DELAY_PS(99) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */ - 0x628 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */ - 0x634 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */ - 0x640 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */ - 0x64C A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */ - 0x658 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */ - >; - }; - - /* Corresponds to MMC1_MANUAL2 in datamanual */ - mmc1_iodelay_sdr104_rev10_conf: mmc1_iodelay_sdr104_rev10_conf { - pinctrl-pin-array = < - 0x620 A_DELAY_PS(560) G_DELAY_PS(365) /* CFG_MMC1_CLK_OUT */ - 0x62c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */ - 0x638 A_DELAY_PS(29) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OUT */ - 0x644 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */ - 0x650 A_DELAY_PS(47) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */ - 0x65c A_DELAY_PS(30) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */ - 0x628 A_DELAY_PS(125) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */ - 0x634 A_DELAY_PS(43) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */ - 0x640 A_DELAY_PS(433) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */ - 0x64c A_DELAY_PS(287) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */ - 0x658 A_DELAY_PS(351) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */ - >; - }; - - /* Corresponds to MMC1_MANUAL2 in datamanual */ - mmc1_iodelay_sdr104_rev20_conf: mmc1_iodelay_sdr104_rev20_conf { - pinctrl-pin-array = < - 0x620 A_DELAY_PS(520) G_DELAY_PS(320) /* CFG_MMC1_CLK_OUT */ - 0x62c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */ - 0x638 A_DELAY_PS(40) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OUT */ - 0x644 A_DELAY_PS(83) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */ - 0x650 A_DELAY_PS(98) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */ - 0x65c A_DELAY_PS(106) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */ - 0x628 A_DELAY_PS(51) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */ - 0x634 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */ - 0x640 A_DELAY_PS(363) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */ - 0x64c A_DELAY_PS(199) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */ - 0x658 A_DELAY_PS(273) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */ - >; - }; - - /* Corresponds to MMC2_MANUAL1 in datamanual */ - mmc2_iodelay_ddr_conf: mmc2_iodelay_ddr_conf { - pinctrl-pin-array = < - 0x18c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A19_IN */ - 0x1a4 A_DELAY_PS(119) G_DELAY_PS(0) /* CFG_GPMC_A20_IN */ - 0x1b0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A21_IN */ - 0x1bc A_DELAY_PS(18) G_DELAY_PS(0) /* CFG_GPMC_A22_IN */ - 0x1c8 A_DELAY_PS(894) G_DELAY_PS(0) /* CFG_GPMC_A23_IN */ - 0x1d4 A_DELAY_PS(30) G_DELAY_PS(0) /* CFG_GPMC_A24_IN */ - 0x1e0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_IN */ - 0x1ec A_DELAY_PS(23) G_DELAY_PS(0) /* CFG_GPMC_A26_IN */ - 0x1f8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_IN */ - 0x360 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_IN */ - 0x194 A_DELAY_PS(152) G_DELAY_PS(0) /* CFG_GPMC_A19_OUT */ - 0x1ac A_DELAY_PS(206) G_DELAY_PS(0) /* CFG_GPMC_A20_OUT */ - 0x1b8 A_DELAY_PS(78) G_DELAY_PS(0) /* CFG_GPMC_A21_OUT */ - 0x1c4 A_DELAY_PS(2) G_DELAY_PS(0) /* CFG_GPMC_A22_OUT */ - 0x1d0 A_DELAY_PS(266) G_DELAY_PS(0) /* CFG_GPMC_A23_OUT */ - 0x1dc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OUT */ - 0x1e8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_OUT */ - 0x1f4 A_DELAY_PS(43) G_DELAY_PS(0) /* CFG_GPMC_A26_OUT */ - 0x200 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OUT */ - 0x368 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_OUT */ - 0x190 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A19_OEN */ - 0x1a8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A20_OEN */ - 0x1b4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A21_OEN */ - 0x1c0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A22_OEN */ - 0x1d8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OEN */ - 0x1e4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_OEN */ - 0x1f0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A26_OEN */ - 0x1fc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OEN */ - 0x364 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_OEN */ - >; - }; - - /* Corresponds to MMC2_MANUAL3 in datamanual */ - mmc2_iodelay_hs200_rev10_conf: mmc2_iodelay_hs200_rev10_conf { - pinctrl-pin-array = < - 0x194 A_DELAY_PS(150) G_DELAY_PS(95) /* CFG_GPMC_A19_OUT */ - 0x1ac A_DELAY_PS(250) G_DELAY_PS(0) /* CFG_GPMC_A20_OUT */ - 0x1b8 A_DELAY_PS(125) G_DELAY_PS(0) /* CFG_GPMC_A21_OUT */ - 0x1c4 A_DELAY_PS(100) G_DELAY_PS(0) /* CFG_GPMC_A22_OUT */ - 0x1d0 A_DELAY_PS(870) G_DELAY_PS(415) /* CFG_GPMC_A23_OUT */ - 0x1dc A_DELAY_PS(30) G_DELAY_PS(0) /* CFG_GPMC_A24_OUT */ - 0x1e8 A_DELAY_PS(200) G_DELAY_PS(0) /* CFG_GPMC_A25_OUT */ - 0x1f4 A_DELAY_PS(200) G_DELAY_PS(0) /* CFG_GPMC_A26_OUT */ - 0x200 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OUT */ - 0x368 A_DELAY_PS(240) G_DELAY_PS(0) /* CFG_GPMC_CS1_OUT */ - 0x190 A_DELAY_PS(695) G_DELAY_PS(0) /* CFG_GPMC_A19_OEN */ - 0x1a8 A_DELAY_PS(924) G_DELAY_PS(0) /* CFG_GPMC_A20_OEN */ - 0x1b4 A_DELAY_PS(719) G_DELAY_PS(0) /* CFG_GPMC_A21_OEN */ - 0x1c0 A_DELAY_PS(824) G_DELAY_PS(0) /* CFG_GPMC_A22_OEN */ - 0x1d8 A_DELAY_PS(877) G_DELAY_PS(0) /* CFG_GPMC_A24_OEN */ - 0x1e4 A_DELAY_PS(446) G_DELAY_PS(0) /* CFG_GPMC_A25_OEN */ - 0x1f0 A_DELAY_PS(847) G_DELAY_PS(0) /* CFG_GPMC_A26_OEN */ - 0x1fc A_DELAY_PS(586) G_DELAY_PS(0) /* CFG_GPMC_A27_OEN */ - 0x364 A_DELAY_PS(1039) G_DELAY_PS(0) /* CFG_GPMC_CS1_OEN */ - >; - }; - - /* Corresponds to MMC2_MANUAL3 in datamanual */ - mmc2_iodelay_hs200_rev20_conf: mmc2_iodelay_hs200_rev20_conf { - pinctrl-pin-array = < - 0x194 A_DELAY_PS(285) G_DELAY_PS(0) /* CFG_GPMC_A19_OUT */ - 0x1ac A_DELAY_PS(189) G_DELAY_PS(0) /* CFG_GPMC_A20_OUT */ - 0x1b8 A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A21_OUT */ - 0x1c4 A_DELAY_PS(0) G_DELAY_PS(70) /* CFG_GPMC_A22_OUT */ - 0x1d0 A_DELAY_PS(730) G_DELAY_PS(360) /* CFG_GPMC_A23_OUT */ - 0x1dc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OUT */ - 0x1e8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_OUT */ - 0x1f4 A_DELAY_PS(70) G_DELAY_PS(0) /* CFG_GPMC_A26_OUT */ - 0x200 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OUT */ - 0x368 A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_CS1_OUT */ - 0x190 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A19_OEN */ - 0x1a8 A_DELAY_PS(231) G_DELAY_PS(0) /* CFG_GPMC_A20_OEN */ - 0x1b4 A_DELAY_PS(39) G_DELAY_PS(0) /* CFG_GPMC_A21_OEN */ - 0x1c0 A_DELAY_PS(91) G_DELAY_PS(0) /* CFG_GPMC_A22_OEN */ - 0x1d8 A_DELAY_PS(176) G_DELAY_PS(0) /* CFG_GPMC_A24_OEN */ - 0x1e4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_OEN */ - 0x1f0 A_DELAY_PS(101) G_DELAY_PS(0) /* CFG_GPMC_A26_OEN */ - 0x1fc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OEN */ - 0x364 A_DELAY_PS(360) G_DELAY_PS(0) /* CFG_GPMC_CS1_OEN */ - >; - }; -}; diff --git a/sys/gnu/dts/arm/dra72x.dtsi b/sys/gnu/dts/arm/dra72x.dtsi deleted file mode 100644 index f5762709c85..00000000000 --- a/sys/gnu/dts/arm/dra72x.dtsi +++ /dev/null @@ -1,66 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ - * - * Based on "omap4.dtsi" - */ - -#include "dra7.dtsi" - -/ { - compatible = "ti,dra722", "ti,dra72", "ti,dra7"; - - pmu { - compatible = "arm,cortex-a15-pmu"; - interrupt-parent = <&wakeupgen>; - interrupts = ; - }; -}; - -&dss { - reg = <0x58000000 0x80>, - <0x58004054 0x4>, - <0x58004300 0x20>; - reg-names = "dss", "pll1_clkctrl", "pll1"; - - clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>, - <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 12>; - clock-names = "fck", "video1_clk"; -}; - -&mailbox5 { - mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { - ti,mbox-tx = <6 2 2>; - ti,mbox-rx = <4 2 2>; - status = "disabled"; - }; - mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { - ti,mbox-tx = <5 2 2>; - ti,mbox-rx = <1 2 2>; - status = "disabled"; - }; -}; - -&mailbox6 { - mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { - ti,mbox-tx = <6 2 2>; - ti,mbox-rx = <4 2 2>; - status = "disabled"; - }; -}; - -&pcie1_rc { - compatible = "ti,dra726-pcie-rc", "ti,dra7-pcie"; -}; - -&pcie1_ep { - compatible = "ti,dra726-pcie-ep", "ti,dra7-pcie-ep"; -}; - -&pcie2_rc { - compatible = "ti,dra726-pcie-rc", "ti,dra7-pcie"; -}; - -&usb4_tm { - status = "disabled"; -}; diff --git a/sys/gnu/dts/arm/dra74x-mmc-iodelay.dtsi b/sys/gnu/dts/arm/dra74x-mmc-iodelay.dtsi deleted file mode 100644 index 214b9e6de2c..00000000000 --- a/sys/gnu/dts/arm/dra74x-mmc-iodelay.dtsi +++ /dev/null @@ -1,647 +0,0 @@ -/* - * MMC IOdelay values for TI's DRA74x, DRA75x and AM572x SoCs. - * - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* - * Rules for modifying this file: - * a) Update of this file should typically correspond to a datamanual revision. - * Datamanual revision that was used should be updated in comment below. - * If there is no update to datamanual, do not update the values. If you - * need to use values different from that recommended by the datamanual - * for your design, then you should consider adding values to the device- - * -tree file for your board directly. - * b) We keep the mode names as close to the datamanual as possible. So - * if the manual calls a mode, DDR50, or DDR or DDR 1.8v or DDR 3.3v, - * we follow that in code too. - * c) If the values change between multiple revisions of silicon, we add - * a revision tag to both the new and old entry. Use 'rev11' for PG 1.1, - * 'rev20' for PG 2.0 and so on. - * d) The node name and node label should be the exact same string. This is - * to curb naming creativity and achieve consistency. - * - * Datamanual Revisions: - * - * AM572x Silicon Revision 2.0: SPRS953F, Revised May 2019 - * AM572x Silicon Revision 1.1: SPRS915R, Revised November 2016 - * - */ - -&dra7_pmx_core { - mmc1_pins_default: mmc1_pins_default { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ - DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ - DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ - DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ - DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ - DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ - >; - }; - - mmc1_pins_sdr12: mmc1_pins_sdr12 { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ - DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ - DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ - DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ - DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ - DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ - >; - }; - - mmc1_pins_hs: mmc1_pins_hs { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_clk.clk */ - DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_cmd.cmd */ - DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat0.dat0 */ - DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat1.dat1 */ - DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat2.dat2 */ - DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat3.dat3 */ - >; - }; - - mmc1_pins_sdr25: mmc1_pins_sdr25 { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_clk.clk */ - DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_cmd.cmd */ - DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat0.dat0 */ - DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat1.dat1 */ - DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat2.dat2 */ - DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat3.dat3 */ - >; - }; - - mmc1_pins_sdr50: mmc1_pins_sdr50 { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_clk.clk */ - DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_cmd.cmd */ - DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat0.dat0 */ - DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat1.dat1 */ - DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat2.dat2 */ - DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat3.dat3 */ - >; - }; - - mmc1_pins_ddr50: mmc1_pins_ddr50 { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_clk.clk */ - DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_cmd.cmd */ - DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat0.dat0 */ - DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat1.dat1 */ - DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat2.dat2 */ - DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat3.dat3 */ - >; - }; - - mmc1_pins_sdr104: mmc1_pins_sdr104 { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_clk.clk */ - DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_cmd.cmd */ - DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat0.dat0 */ - DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat1.dat1 */ - DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat2.dat2 */ - DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat3.dat3 */ - >; - }; - - mmc2_pins_default: mmc2_pins_default { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ - DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ - DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ - DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ - DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ - DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ - DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ - DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ - DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ - DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ - >; - }; - - mmc2_pins_hs: mmc2_pins_hs { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ - DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ - DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ - DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ - DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ - DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ - DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ - DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ - DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ - DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ - >; - }; - - mmc2_pins_ddr_3_3v_rev11: mmc2_pins_ddr_3_3v_rev11 { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */ - DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ - DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ - DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ - DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ - DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ - DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ - DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ - DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ - DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ - >; - }; - - mmc2_pins_ddr_1_8v_rev11: mmc2_pins_ddr_1_8v_rev11 { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */ - DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ - DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ - DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ - DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ - DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ - DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ - DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ - DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ - DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ - >; - }; - - mmc2_pins_ddr_rev20: mmc2_pins_ddr_rev20 { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ - DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ - DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ - DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ - DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ - DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ - DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ - DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ - DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ - DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ - >; - }; - - mmc2_pins_hs200: mmc2_pins_hs200 { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */ - DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ - DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ - DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ - DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ - DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ - DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ - DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ - DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ - DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ - >; - }; - - mmc4_pins_default: mmc4_pins_default { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */ - DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */ - DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */ - DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_txd.mmc4_dat1 */ - DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */ - DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */ - >; - }; - - mmc4_pins_hs: mmc4_pins_hs { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */ - DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */ - DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */ - DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_txd.mmc4_dat1 */ - DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */ - DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */ - >; - }; - - mmc3_pins_default: mmc3_pins_default { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_clk.mmc3_clk */ - DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */ - DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */ - DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */ - DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */ - DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */ - >; - }; - - mmc3_pins_hs: mmc3_pins_hs { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_clk.mmc3_clk */ - DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */ - DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */ - DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */ - DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */ - DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */ - >; - }; - - mmc3_pins_sdr12: mmc3_pins_sdr12 { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_clk.mmc3_clk */ - DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */ - DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */ - DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */ - DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */ - DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */ - >; - }; - - mmc3_pins_sdr25: mmc3_pins_sdr25 { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_clk.mmc3_clk */ - DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */ - DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */ - DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */ - DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */ - DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */ - >; - }; - - mmc3_pins_sdr50: mmc3_pins_sdr50 { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_clk.mmc3_clk */ - DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */ - DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */ - DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */ - DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */ - DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */ - >; - }; - - mmc4_pins_sdr12: mmc4_pins_sdr12 { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */ - DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */ - DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */ - DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_txd.mmc4_dat1 */ - DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */ - DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */ - >; - }; - - mmc4_pins_sdr25: mmc4_pins_sdr25 { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */ - DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */ - DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */ - DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_txd.mmc4_dat1 */ - DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */ - DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */ - >; - }; -}; - -&dra7_iodelay_core { - - /* Corresponds to MMC1_DDR_MANUAL1 in datamanual */ - mmc1_iodelay_ddr_rev11_conf: mmc1_iodelay_ddr_rev11_conf { - pinctrl-pin-array = < - 0x618 A_DELAY_PS(572) G_DELAY_PS(540) /* CFG_MMC1_CLK_IN */ - 0x620 A_DELAY_PS(1525) G_DELAY_PS(0) /* CFG_MMC1_CLK_OUT */ - 0x624 A_DELAY_PS(0) G_DELAY_PS(600) /* CFG_MMC1_CMD_IN */ - 0x628 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */ - 0x62c A_DELAY_PS(55) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */ - 0x630 A_DELAY_PS(403) G_DELAY_PS(120) /* CFG_MMC1_DAT0_IN */ - 0x634 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */ - 0x638 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OUT */ - 0x63c A_DELAY_PS(23) G_DELAY_PS(60) /* CFG_MMC1_DAT1_IN */ - 0x640 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */ - 0x644 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */ - 0x648 A_DELAY_PS(25) G_DELAY_PS(60) /* CFG_MMC1_DAT2_IN */ - 0x64c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */ - 0x650 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */ - 0x654 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_IN */ - 0x658 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */ - 0x65c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */ - >; - }; - - /* Corresponds to MMC1_DDR_MANUAL1 in datamanual */ - mmc1_iodelay_ddr_rev20_conf: mmc1_iodelay_ddr50_rev20_conf { - pinctrl-pin-array = < - 0x618 A_DELAY_PS(1076) G_DELAY_PS(330) /* CFG_MMC1_CLK_IN */ - 0x620 A_DELAY_PS(1271) G_DELAY_PS(0) /* CFG_MMC1_CLK_OUT */ - 0x624 A_DELAY_PS(722) G_DELAY_PS(0) /* CFG_MMC1_CMD_IN */ - 0x628 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */ - 0x62C A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */ - 0x630 A_DELAY_PS(751) G_DELAY_PS(0) /* CFG_MMC1_DAT0_IN */ - 0x634 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */ - 0x638 A_DELAY_PS(20) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OUT */ - 0x63C A_DELAY_PS(256) G_DELAY_PS(0) /* CFG_MMC1_DAT1_IN */ - 0x640 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */ - 0x644 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */ - 0x648 A_DELAY_PS(263) G_DELAY_PS(0) /* CFG_MMC1_DAT2_IN */ - 0x64C A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */ - 0x650 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */ - 0x654 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_IN */ - 0x658 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */ - 0x65C A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */ - >; - }; - - /* Corresponds to MMC1_SDR104_MANUAL1 in datamanual */ - mmc1_iodelay_sdr104_rev11_conf: mmc1_iodelay_sdr104_rev11_conf { - pinctrl-pin-array = < - 0x620 A_DELAY_PS(1063) G_DELAY_PS(17) /* CFG_MMC1_CLK_OUT */ - 0x628 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */ - 0x62c A_DELAY_PS(23) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */ - 0x634 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */ - 0x638 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OUT */ - 0x640 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */ - 0x644 A_DELAY_PS(2) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */ - 0x64c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */ - 0x650 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */ - 0x658 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */ - 0x65c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */ - >; - }; - - /* Corresponds to MMC1_SDR104_MANUAL1 in datamanual */ - mmc1_iodelay_sdr104_rev20_conf: mmc1_iodelay_sdr104_rev20_conf { - pinctrl-pin-array = < - 0x620 A_DELAY_PS(600) G_DELAY_PS(400) /* CFG_MMC1_CLK_OUT */ - 0x628 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */ - 0x62c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */ - 0x634 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */ - 0x638 A_DELAY_PS(30) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OUT */ - 0x640 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */ - 0x644 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */ - 0x64c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */ - 0x650 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */ - 0x658 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */ - 0x65c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */ - >; - }; - - /* Corresponds to MMC2_HS200_MANUAL1 in datamanual */ - mmc2_iodelay_hs200_rev11_conf: mmc2_iodelay_hs200_rev11_conf { - pinctrl-pin-array = < - 0x190 A_DELAY_PS(621) G_DELAY_PS(600) /* CFG_GPMC_A19_OEN */ - 0x194 A_DELAY_PS(300) G_DELAY_PS(0) /* CFG_GPMC_A19_OUT */ - 0x1a8 A_DELAY_PS(739) G_DELAY_PS(600) /* CFG_GPMC_A20_OEN */ - 0x1ac A_DELAY_PS(240) G_DELAY_PS(0) /* CFG_GPMC_A20_OUT */ - 0x1b4 A_DELAY_PS(812) G_DELAY_PS(600) /* CFG_GPMC_A21_OEN */ - 0x1b8 A_DELAY_PS(240) G_DELAY_PS(0) /* CFG_GPMC_A21_OUT */ - 0x1c0 A_DELAY_PS(954) G_DELAY_PS(600) /* CFG_GPMC_A22_OEN */ - 0x1c4 A_DELAY_PS(60) G_DELAY_PS(0) /* CFG_GPMC_A22_OUT */ - 0x1d0 A_DELAY_PS(1340) G_DELAY_PS(420) /* CFG_GPMC_A23_OUT */ - 0x1d8 A_DELAY_PS(935) G_DELAY_PS(600) /* CFG_GPMC_A24_OEN */ - 0x1dc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OUT */ - 0x1e4 A_DELAY_PS(525) G_DELAY_PS(600) /* CFG_GPMC_A25_OEN */ - 0x1e8 A_DELAY_PS(120) G_DELAY_PS(0) /* CFG_GPMC_A25_OUT */ - 0x1f0 A_DELAY_PS(767) G_DELAY_PS(600) /* CFG_GPMC_A26_OEN */ - 0x1f4 A_DELAY_PS(225) G_DELAY_PS(0) /* CFG_GPMC_A26_OUT */ - 0x1fc A_DELAY_PS(565) G_DELAY_PS(600) /* CFG_GPMC_A27_OEN */ - 0x200 A_DELAY_PS(60) G_DELAY_PS(0) /* CFG_GPMC_A27_OUT */ - 0x364 A_DELAY_PS(969) G_DELAY_PS(600) /* CFG_GPMC_CS1_OEN */ - 0x368 A_DELAY_PS(180) G_DELAY_PS(0) /* CFG_GPMC_CS1_OUT */ - >; - }; - - /* Corresponds to MMC2_HS200_MANUAL1 in datamanual */ - mmc2_iodelay_hs200_rev20_conf: mmc2_iodelay_hs200_rev20_conf { - pinctrl-pin-array = < - 0x190 A_DELAY_PS(274) G_DELAY_PS(0) /* CFG_GPMC_A19_OEN */ - 0x194 A_DELAY_PS(162) G_DELAY_PS(0) /* CFG_GPMC_A19_OUT */ - 0x1a8 A_DELAY_PS(401) G_DELAY_PS(0) /* CFG_GPMC_A20_OEN */ - 0x1ac A_DELAY_PS(73) G_DELAY_PS(0) /* CFG_GPMC_A20_OUT */ - 0x1b4 A_DELAY_PS(465) G_DELAY_PS(0) /* CFG_GPMC_A21_OEN */ - 0x1b8 A_DELAY_PS(115) G_DELAY_PS(0) /* CFG_GPMC_A21_OUT */ - 0x1c0 A_DELAY_PS(633) G_DELAY_PS(0) /* CFG_GPMC_A22_OEN */ - 0x1c4 A_DELAY_PS(47) G_DELAY_PS(0) /* CFG_GPMC_A22_OUT */ - 0x1d0 A_DELAY_PS(935) G_DELAY_PS(280) /* CFG_GPMC_A23_OUT */ - 0x1d8 A_DELAY_PS(621) G_DELAY_PS(0) /* CFG_GPMC_A24_OEN */ - 0x1dc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OUT */ - 0x1e4 A_DELAY_PS(183) G_DELAY_PS(0) /* CFG_GPMC_A25_OEN */ - 0x1e8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_OUT */ - 0x1f0 A_DELAY_PS(467) G_DELAY_PS(0) /* CFG_GPMC_A26_OEN */ - 0x1f4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A26_OUT */ - 0x1fc A_DELAY_PS(262) G_DELAY_PS(0) /* CFG_GPMC_A27_OEN */ - 0x200 A_DELAY_PS(46) G_DELAY_PS(0) /* CFG_GPMC_A27_OUT */ - 0x364 A_DELAY_PS(684) G_DELAY_PS(0) /* CFG_GPMC_CS1_OEN */ - 0x368 A_DELAY_PS(76) G_DELAY_PS(0) /* CFG_GPMC_CS1_OUT */ - >; - }; - - /* Correspnds to MMC2_DDR_3V3_MANUAL1 in datamanual */ - mmc2_iodelay_ddr_3_3v_rev11_conf: mmc2_iodelay_ddr_3_3v_rev11_conf { - pinctrl-pin-array = < - 0x18c A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A19_IN */ - 0x190 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A19_OEN */ - 0x194 A_DELAY_PS(174) G_DELAY_PS(0) /* CFG_GPMC_A19_OUT */ - 0x1a4 A_DELAY_PS(265) G_DELAY_PS(360) /* CFG_GPMC_A20_IN */ - 0x1a8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A20_OEN */ - 0x1ac A_DELAY_PS(168) G_DELAY_PS(0) /* CFG_GPMC_A20_OUT */ - 0x1b0 A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A21_IN */ - 0x1b4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A21_OEN */ - 0x1b8 A_DELAY_PS(136) G_DELAY_PS(0) /* CFG_GPMC_A21_OUT */ - 0x1bc A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A22_IN */ - 0x1c0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A22_OEN */ - 0x1c4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A22_OUT */ - 0x1c8 A_DELAY_PS(287) G_DELAY_PS(420) /* CFG_GPMC_A23_IN */ - 0x1d0 A_DELAY_PS(879) G_DELAY_PS(0) /* CFG_GPMC_A23_OUT */ - 0x1d4 A_DELAY_PS(144) G_DELAY_PS(240) /* CFG_GPMC_A24_IN */ - 0x1d8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OEN */ - 0x1dc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OUT */ - 0x1e0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_IN */ - 0x1e4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_OEN */ - 0x1e8 A_DELAY_PS(34) G_DELAY_PS(0) /* CFG_GPMC_A25_OUT */ - 0x1ec A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A26_IN */ - 0x1f0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A26_OEN */ - 0x1f4 A_DELAY_PS(120) G_DELAY_PS(0) /* CFG_GPMC_A26_OUT */ - 0x1f8 A_DELAY_PS(120) G_DELAY_PS(180) /* CFG_GPMC_A27_IN */ - 0x1fc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OEN */ - 0x200 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OUT */ - 0x360 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_IN */ - 0x364 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_OEN */ - 0x368 A_DELAY_PS(11) G_DELAY_PS(0) /* CFG_GPMC_CS1_OUT */ - >; - }; - - /* Corresponds to MMC2_DDR_1V8_MANUAL1 in datamanual */ - mmc2_iodelay_ddr_1_8v_rev11_conf: mmc2_iodelay_ddr_1_8v_rev11_conf { - pinctrl-pin-array = < - 0x18c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A19_IN */ - 0x190 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A19_OEN */ - 0x194 A_DELAY_PS(174) G_DELAY_PS(0) /* CFG_GPMC_A19_OUT */ - 0x1a4 A_DELAY_PS(274) G_DELAY_PS(240) /* CFG_GPMC_A20_IN */ - 0x1a8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A20_OEN */ - 0x1ac A_DELAY_PS(168) G_DELAY_PS(0) /* CFG_GPMC_A20_OUT */ - 0x1b0 A_DELAY_PS(0) G_DELAY_PS(60) /* CFG_GPMC_A21_IN */ - 0x1b4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A21_OEN */ - 0x1b8 A_DELAY_PS(136) G_DELAY_PS(0) /* CFG_GPMC_A21_OUT */ - 0x1bc A_DELAY_PS(0) G_DELAY_PS(60) /* CFG_GPMC_A22_IN */ - 0x1c0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A22_OEN */ - 0x1c4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A22_OUT */ - 0x1c8 A_DELAY_PS(514) G_DELAY_PS(360) /* CFG_GPMC_A23_IN */ - 0x1d0 A_DELAY_PS(879) G_DELAY_PS(0) /* CFG_GPMC_A23_OUT */ - 0x1d4 A_DELAY_PS(187) G_DELAY_PS(120) /* CFG_GPMC_A24_IN */ - 0x1d8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OEN */ - 0x1dc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OUT */ - 0x1e0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_IN */ - 0x1e4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_OEN */ - 0x1e8 A_DELAY_PS(34) G_DELAY_PS(0) /* CFG_GPMC_A25_OUT */ - 0x1ec A_DELAY_PS(0) G_DELAY_PS(60) /* CFG_GPMC_A26_IN */ - 0x1f0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A26_OEN */ - 0x1f4 A_DELAY_PS(120) G_DELAY_PS(0) /* CFG_GPMC_A26_OUT */ - 0x1f8 A_DELAY_PS(121) G_DELAY_PS(60) /* CFG_GPMC_A27_IN */ - 0x1fc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OEN */ - 0x200 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OUT */ - 0x360 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_IN */ - 0x364 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_OEN */ - 0x368 A_DELAY_PS(11) G_DELAY_PS(0) /* CFG_GPMC_CS1_OUT */ - >; - }; - - /* Corresponds to MMC3_MANUAL1 in datamanual */ - mmc3_iodelay_manual1_rev20_conf: mmc3_iodelay_manual1_conf { - pinctrl-pin-array = < - 0x678 A_DELAY_PS(0) G_DELAY_PS(386) /* CFG_MMC3_CLK_IN */ - 0x680 A_DELAY_PS(605) G_DELAY_PS(0) /* CFG_MMC3_CLK_OUT */ - 0x684 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_IN */ - 0x688 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_OEN */ - 0x68c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_OUT */ - 0x690 A_DELAY_PS(171) G_DELAY_PS(0) /* CFG_MMC3_DAT0_IN */ - 0x694 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT0_OEN */ - 0x698 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT0_OUT */ - 0x69c A_DELAY_PS(221) G_DELAY_PS(0) /* CFG_MMC3_DAT1_IN */ - 0x6a0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT1_OEN */ - 0x6a4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT1_OUT */ - 0x6a8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_IN */ - 0x6ac A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_OEN */ - 0x6b0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_OUT */ - 0x6b4 A_DELAY_PS(474) G_DELAY_PS(0) /* CFG_MMC3_DAT3_IN */ - 0x6b8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT3_OEN */ - 0x6bc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT3_OUT */ - >; - }; - - /* Corresponds to MMC3_MANUAL1 in datamanual */ - mmc3_iodelay_manual1_rev11_conf: mmc3_iodelay_manual1_conf { - pinctrl-pin-array = < - 0x678 A_DELAY_PS(406) G_DELAY_PS(0) /* CFG_MMC3_CLK_IN */ - 0x680 A_DELAY_PS(659) G_DELAY_PS(0) /* CFG_MMC3_CLK_OUT */ - 0x684 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_IN */ - 0x688 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_OEN */ - 0x68c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_OUT */ - 0x690 A_DELAY_PS(130) G_DELAY_PS(0) /* CFG_MMC3_DAT0_IN */ - 0x694 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT0_OEN */ - 0x698 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT0_OUT */ - 0x69c A_DELAY_PS(169) G_DELAY_PS(0) /* CFG_MMC3_DAT1_IN */ - 0x6a0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT1_OEN */ - 0x6a4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT1_OUT */ - 0x6a8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_IN */ - 0x6ac A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_OEN */ - 0x6b0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_OUT */ - 0x6b4 A_DELAY_PS(457) G_DELAY_PS(0) /* CFG_MMC3_DAT3_IN */ - 0x6b8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT3_OEN */ - 0x6bc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT3_OUT */ - >; - }; - - /* Corresponds to MMC4_DS_MANUAL1 in datamanual */ - mmc4_iodelay_ds_rev11_conf: mmc4_iodelay_ds_rev11_conf { - pinctrl-pin-array = < - 0x840 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_IN */ - 0x848 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_OUT */ - 0x84c A_DELAY_PS(96) G_DELAY_PS(0) /* CFG_UART1_RTSN_IN */ - 0x850 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OEN */ - 0x854 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OUT */ - 0x870 A_DELAY_PS(582) G_DELAY_PS(0) /* CFG_UART2_CTSN_IN */ - 0x874 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OEN */ - 0x878 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OUT */ - 0x87c A_DELAY_PS(391) G_DELAY_PS(0) /* CFG_UART2_RTSN_IN */ - 0x880 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OEN */ - 0x884 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OUT */ - 0x888 A_DELAY_PS(561) G_DELAY_PS(0) /* CFG_UART2_RXD_IN */ - 0x88c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OEN */ - 0x890 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OUT */ - 0x894 A_DELAY_PS(588) G_DELAY_PS(0) /* CFG_UART2_TXD_IN */ - 0x898 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OEN */ - 0x89c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OUT */ - >; - }; - - /* Corresponds to MMC4_DS_MANUAL1 in datamanual */ - mmc4_iodelay_ds_rev20_conf: mmc4_iodelay_ds_rev20_conf { - pinctrl-pin-array = < - 0x840 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_IN */ - 0x848 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_OUT */ - 0x84c A_DELAY_PS(307) G_DELAY_PS(0) /* CFG_UART1_RTSN_IN */ - 0x850 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OEN */ - 0x854 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OUT */ - 0x870 A_DELAY_PS(785) G_DELAY_PS(0) /* CFG_UART2_CTSN_IN */ - 0x874 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OEN */ - 0x878 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OUT */ - 0x87c A_DELAY_PS(613) G_DELAY_PS(0) /* CFG_UART2_RTSN_IN */ - 0x880 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OEN */ - 0x884 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OUT */ - 0x888 A_DELAY_PS(683) G_DELAY_PS(0) /* CFG_UART2_RXD_IN */ - 0x88c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OEN */ - 0x890 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OUT */ - 0x894 A_DELAY_PS(835) G_DELAY_PS(0) /* CFG_UART2_TXD_IN */ - 0x898 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OEN */ - 0x89c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OUT */ - >; - }; - - /* Corresponds to MMC4_MANUAL1 in datamanual */ - mmc4_iodelay_sdr12_hs_sdr25_rev11_conf: mmc4_iodelay_sdr12_hs_sdr25_rev11_conf { - pinctrl-pin-array = < - 0x840 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_IN */ - 0x848 A_DELAY_PS(2651) G_DELAY_PS(0) /* CFG_UART1_CTSN_OUT */ - 0x84c A_DELAY_PS(1572) G_DELAY_PS(0) /* CFG_UART1_RTSN_IN */ - 0x850 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OEN */ - 0x854 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OUT */ - 0x870 A_DELAY_PS(1913) G_DELAY_PS(0) /* CFG_UART2_CTSN_IN */ - 0x874 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OEN */ - 0x878 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OUT */ - 0x87c A_DELAY_PS(1721) G_DELAY_PS(0) /* CFG_UART2_RTSN_IN */ - 0x880 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OEN */ - 0x884 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OUT */ - 0x888 A_DELAY_PS(1891) G_DELAY_PS(0) /* CFG_UART2_RXD_IN */ - 0x88c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OEN */ - 0x890 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OUT */ - 0x894 A_DELAY_PS(1919) G_DELAY_PS(0) /* CFG_UART2_TXD_IN */ - 0x898 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OEN */ - 0x89c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OUT */ - >; - }; - - /* Corresponds to MMC4_MANUAL1 in datamanual */ - mmc4_iodelay_sdr12_hs_sdr25_rev20_conf: mmc4_iodelay_sdr12_hs_sdr25_rev20_conf { - pinctrl-pin-array = < - 0x840 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_IN */ - 0x848 A_DELAY_PS(1147) G_DELAY_PS(0) /* CFG_UART1_CTSN_OUT */ - 0x84c A_DELAY_PS(1834) G_DELAY_PS(0) /* CFG_UART1_RTSN_IN */ - 0x850 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OEN */ - 0x854 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OUT */ - 0x870 A_DELAY_PS(2165) G_DELAY_PS(0) /* CFG_UART2_CTSN_IN */ - 0x874 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OEN */ - 0x878 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OUT */ - 0x87c A_DELAY_PS(1929) G_DELAY_PS(64) /* CFG_UART2_RTSN_IN */ - 0x880 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OEN */ - 0x884 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OUT */ - 0x888 A_DELAY_PS(1935) G_DELAY_PS(128) /* CFG_UART2_RXD_IN */ - 0x88c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OEN */ - 0x890 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OUT */ - 0x894 A_DELAY_PS(2172) G_DELAY_PS(44) /* CFG_UART2_TXD_IN */ - 0x898 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OEN */ - 0x89c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OUT */ - >; - }; -}; diff --git a/sys/gnu/dts/arm/dra74x.dtsi b/sys/gnu/dts/arm/dra74x.dtsi deleted file mode 100644 index d1b5b76bc5a..00000000000 --- a/sys/gnu/dts/arm/dra74x.dtsi +++ /dev/null @@ -1,146 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ - * - * Based on "omap4.dtsi" - */ - -#include "dra7.dtsi" - -/ { - compatible = "ti,dra742", "ti,dra74", "ti,dra7"; - - cpus { - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <1>; - operating-points-v2 = <&cpu0_opp_table>; - - clocks = <&dpll_mpu_ck>; - clock-names = "cpu"; - - clock-latency = <300000>; /* From omap-cpufreq driver */ - - /* cooling options */ - #cooling-cells = <2>; /* min followed by max */ - - vbb-supply = <&abb_mpu>; - }; - }; - - pmu { - compatible = "arm,cortex-a15-pmu"; - interrupt-parent = <&wakeupgen>; - interrupts = , - ; - }; - - ocp { - dsp2_system: dsp_system@41500000 { - compatible = "syscon"; - reg = <0x41500000 0x100>; - }; - - omap_dwc3_4: omap_dwc3_4@48940000 { - compatible = "ti,dwc3"; - ti,hwmods = "usb_otg_ss4"; - reg = <0x48940000 0x10000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <1>; - utmi-mode = <2>; - ranges; - status = "disabled"; - usb4: usb@48950000 { - compatible = "snps,dwc3"; - reg = <0x48950000 0x17000>; - interrupts = , - , - ; - interrupt-names = "peripheral", - "host", - "otg"; - maximum-speed = "high-speed"; - dr_mode = "otg"; - }; - }; - - mmu0_dsp2: mmu@41501000 { - compatible = "ti,dra7-dsp-iommu"; - reg = <0x41501000 0x100>; - interrupts = ; - ti,hwmods = "mmu0_dsp2"; - #iommu-cells = <0>; - ti,syscon-mmuconfig = <&dsp2_system 0x0>; - status = "disabled"; - }; - - mmu1_dsp2: mmu@41502000 { - compatible = "ti,dra7-dsp-iommu"; - reg = <0x41502000 0x100>; - interrupts = ; - ti,hwmods = "mmu1_dsp2"; - #iommu-cells = <0>; - ti,syscon-mmuconfig = <&dsp2_system 0x1>; - status = "disabled"; - }; - }; -}; - -&cpu0_opp_table { - opp-shared; -}; - -&dss { - reg = <0x58000000 0x80>, - <0x58004054 0x4>, - <0x58004300 0x20>, - <0x58009054 0x4>, - <0x58009300 0x20>; - reg-names = "dss", "pll1_clkctrl", "pll1", - "pll2_clkctrl", "pll2"; - - clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>, - <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 12>, - <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 13>; - clock-names = "fck", "video1_clk", "video2_clk"; -}; - -&mailbox5 { - mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { - ti,mbox-tx = <6 2 2>; - ti,mbox-rx = <4 2 2>; - status = "disabled"; - }; - mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { - ti,mbox-tx = <5 2 2>; - ti,mbox-rx = <1 2 2>; - status = "disabled"; - }; -}; - -&mailbox6 { - mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { - ti,mbox-tx = <6 2 2>; - ti,mbox-rx = <4 2 2>; - status = "disabled"; - }; - mbox_dsp2_ipc3x: mbox_dsp2_ipc3x { - ti,mbox-tx = <5 2 2>; - ti,mbox-rx = <1 2 2>; - status = "disabled"; - }; -}; - -&pcie1_rc { - compatible = "ti,dra746-pcie-rc", "ti,dra7-pcie"; -}; - -&pcie1_ep { - compatible = "ti,dra746-pcie-ep", "ti,dra7-pcie-ep"; -}; - -&pcie2_rc { - compatible = "ti,dra746-pcie-rc", "ti,dra7-pcie"; -}; diff --git a/sys/gnu/dts/arm/dra76-evm.dts b/sys/gnu/dts/arm/dra76-evm.dts deleted file mode 100644 index 1fb6f13fb5e..00000000000 --- a/sys/gnu/dts/arm/dra76-evm.dts +++ /dev/null @@ -1,449 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ - */ -/dts-v1/; - -#include "dra76x.dtsi" -#include "dra7-evm-common.dtsi" -#include "dra76x-mmc-iodelay.dtsi" -#include - -/ { - model = "TI DRA762 EVM"; - compatible = "ti,dra76-evm", "ti,dra762", "ti,dra7"; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x80000000 0x0 0x80000000>; - }; - - vsys_12v0: fixedregulator-vsys12v0 { - /* main supply */ - compatible = "regulator-fixed"; - regulator-name = "vsys_12v0"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-always-on; - regulator-boot-on; - }; - - vsys_5v0: fixedregulator-vsys5v0 { - /* Output of Cntlr B of TPS43351-Q1 on dra76-evm */ - compatible = "regulator-fixed"; - regulator-name = "vsys_5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vsys_12v0>; - regulator-always-on; - regulator-boot-on; - }; - - vio_3v6: fixedregulator-vio_3v6 { - compatible = "regulator-fixed"; - regulator-name = "vio_3v6"; - regulator-min-microvolt = <3600000>; - regulator-max-microvolt = <3600000>; - vin-supply = <&vsys_5v0>; - regulator-always-on; - regulator-boot-on; - }; - - vsys_3v3: fixedregulator-vsys3v3 { - /* Output of Cntlr A of TPS43351-Q1 on dra76-evm */ - compatible = "regulator-fixed"; - regulator-name = "vsys_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vsys_12v0>; - regulator-always-on; - regulator-boot-on; - }; - - vio_3v3: fixedregulator-vio_3v3 { - compatible = "regulator-fixed"; - regulator-name = "vio_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vsys_3v3>; - regulator-always-on; - regulator-boot-on; - }; - - vio_3v3_sd: fixedregulator-sd { - compatible = "regulator-fixed"; - regulator-name = "vio_3v3_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vio_3v3>; - enable-active-high; - gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; - }; - - vio_1v8: fixedregulator-vio_1v8 { - compatible = "regulator-fixed"; - regulator-name = "vio_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&smps5_reg>; - }; - - vmmcwl_fixed: fixedregulator-mmcwl { - compatible = "regulator-fixed"; - regulator-name = "vmmcwl_fixed"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio5 8 0>; /* gpio5_8 */ - startup-delay-us = <70000>; - enable-active-high; - }; - - vtt_fixed: fixedregulator-vtt { - compatible = "regulator-fixed"; - regulator-name = "vtt_fixed"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - vin-supply = <&vsys_3v3>; - regulator-always-on; - regulator-boot-on; - }; - - aic_dvdd: fixedregulator-aic_dvdd { - /* TPS77018DBVT */ - compatible = "regulator-fixed"; - regulator-name = "aic_dvdd"; - vin-supply = <&vio_3v3>; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; -}; - -&i2c1 { - status = "okay"; - clock-frequency = <400000>; - - tps65917: tps65917@58 { - compatible = "ti,tps65917"; - reg = <0x58>; - ti,system-power-controller; - ti,palmas-override-powerhold; - interrupt-controller; - #interrupt-cells = <2>; - - tps65917_pmic { - compatible = "ti,tps65917-pmic"; - - smps12-in-supply = <&vsys_3v3>; - smps3-in-supply = <&vsys_3v3>; - smps4-in-supply = <&vsys_3v3>; - smps5-in-supply = <&vsys_3v3>; - ldo1-in-supply = <&vsys_3v3>; - ldo2-in-supply = <&vsys_3v3>; - ldo3-in-supply = <&vsys_5v0>; - ldo4-in-supply = <&vsys_5v0>; - ldo5-in-supply = <&vsys_3v3>; - - tps65917_regulators: regulators { - smps12_reg: smps12 { - /* VDD_DSPEVE */ - regulator-name = "smps12"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1250000>; - regulator-always-on; - regulator-boot-on; - }; - - smps3_reg: smps3 { - /* VDD_CORE */ - regulator-name = "smps3"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1250000>; - regulator-boot-on; - regulator-always-on; - }; - - smps4_reg: smps4 { - /* VDD_IVA */ - regulator-name = "smps4"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1250000>; - regulator-always-on; - regulator-boot-on; - }; - - smps5_reg: smps5 { - /* VDDS1V8 */ - regulator-name = "smps5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1_reg: ldo1 { - /* LDO1_OUT --> VDA_PHY1_1V8 */ - regulator-name = "ldo1"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - regulator-allow-bypass; - }; - - ldo2_reg: ldo2 { - /* LDO2_OUT --> VDA_PHY2_1V8 */ - regulator-name = "ldo2"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-allow-bypass; - regulator-always-on; - }; - - ldo3_reg: ldo3 { - /* VDA_USB_3V3 */ - regulator-name = "ldo3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo5_reg: ldo5 { - /* VDDA_1V8_PLL */ - regulator-name = "ldo5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo4_reg: ldo4 { - /* VDD_SDIO_DV */ - regulator-name = "ldo4"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; - - tps65917_power_button { - compatible = "ti,palmas-pwrbutton"; - interrupt-parent = <&tps65917>; - interrupts = <1 IRQ_TYPE_NONE>; - wakeup-source; - ti,palmas-long-press-seconds = <6>; - }; - }; - - lp87565: lp87565@60 { - compatible = "ti,lp87565-q1"; - reg = <0x60>; - - buck10-in-supply =<&vsys_3v3>; - buck23-in-supply =<&vsys_3v3>; - - regulators: regulators { - buck10_reg: buck10 { - /*VDD_MPU*/ - regulator-name = "buck10"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1250000>; - regulator-always-on; - regulator-boot-on; - }; - - buck23_reg: buck23 { - /* VDD_GPU*/ - regulator-name = "buck23"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1250000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; - - pcf_lcd: pcf8757@20 { - compatible = "ti,pcf8575", "nxp,pcf8575"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&gpio1>; - interrupts = <3 IRQ_TYPE_EDGE_FALLING>; - }; - - pcf_gpio_21: pcf8757@21 { - compatible = "ti,pcf8575", "nxp,pcf8575"; - reg = <0x21>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&gpio1>; - interrupts = <3 IRQ_TYPE_EDGE_FALLING>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - pcf_hdmi: pcf8575@26 { - compatible = "ti,pcf8575", "nxp,pcf8575"; - reg = <0x26>; - gpio-controller; - #gpio-cells = <2>; - p1 { - /* vin6_sel_s0: high: VIN6, low: audio */ - gpio-hog; - gpios = <1 GPIO_ACTIVE_HIGH>; - output-low; - line-name = "vin6_sel_s0"; - }; - }; - - tlv320aic3106: tlv320aic3106@19 { - #sound-dai-cells = <0>; - compatible = "ti,tlv320aic3106"; - reg = <0x19>; - adc-settle-ms = <40>; - ai3x-micbias-vg = <1>; /* 2.0V */ - status = "okay"; - - /* Regulators */ - AVDD-supply = <&vio_3v3>; - IOVDD-supply = <&vio_3v3>; - DRVDD-supply = <&vio_3v3>; - DVDD-supply = <&aic_dvdd>; - }; -}; - -&cpu0 { - vdd-supply = <&buck10_reg>; -}; - -&mmc1 { - status = "okay"; - vmmc-supply = <&vio_3v3_sd>; - vqmmc-supply = <&ldo4_reg>; - bus-width = <4>; - /* - * SDCD signal is not being used here - using the fact that GPIO mode - * is always hardwired. - */ - cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; - pinctrl-names = "default", "hs"; - pinctrl-0 = <&mmc1_pins_default>; - pinctrl-1 = <&mmc1_pins_hs>; -}; - -&mmc2 { - status = "okay"; - vmmc-supply = <&vio_1v8>; - vqmmc-supply = <&vio_1v8>; - bus-width = <8>; - non-removable; - pinctrl-names = "default", "hs", "ddr_1_8v", "hs200_1_8v"; - pinctrl-0 = <&mmc2_pins_default>; - pinctrl-1 = <&mmc2_pins_default>; - pinctrl-2 = <&mmc2_pins_default>; - pinctrl-3 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_conf>; -}; - -&mmc4 { - status = "okay"; - vmmc-supply = <&vio_3v6>; - vqmmc-supply = <&vmmcwl_fixed>; - pinctrl-names = "default", "hs", "sdr12", "sdr25"; - pinctrl-0 = <&mmc4_pins_hs &mmc4_iodelay_default_conf>; - pinctrl-1 = <&mmc4_pins_hs &mmc4_iodelay_manual1_conf>; - pinctrl-2 = <&mmc4_pins_hs &mmc4_iodelay_manual1_conf>; - pinctrl-3 = <&mmc4_pins_hs &mmc4_iodelay_manual1_conf>; -}; - -/* No RTC on this device */ -&rtc { - status = "disabled"; -}; - -&mac { - status = "okay"; - - dual_emac; -}; - -&cpsw_emac0 { - phy-handle = <&dp83867_0>; - phy-mode = "rgmii-id"; - dual_emac_res_vlan = <1>; -}; - -&cpsw_emac1 { - phy-handle = <&dp83867_1>; - phy-mode = "rgmii-id"; - dual_emac_res_vlan = <2>; -}; - -&davinci_mdio { - dp83867_0: ethernet-phy@2 { - reg = <2>; - ti,rx-internal-delay = ; - ti,tx-internal-delay = ; - ti,fifo-depth = ; - ti,min-output-impedance; - ti,dp83867-rxctrl-strap-quirk; - }; - - dp83867_1: ethernet-phy@3 { - reg = <3>; - ti,rx-internal-delay = ; - ti,tx-internal-delay = ; - ti,fifo-depth = ; - ti,min-output-impedance; - ti,dp83867-rxctrl-strap-quirk; - }; -}; - -&usb2_phy1 { - phy-supply = <&ldo3_reg>; -}; - -&usb2_phy2 { - phy-supply = <&ldo3_reg>; -}; - -&qspi { - spi-max-frequency = <96000000>; - m25p80@0 { - spi-max-frequency = <96000000>; - }; -}; - -&pcie2_phy { - status = "okay"; -}; - -&pcie1_rc { - num-lanes = <2>; - phys = <&pcie1_phy>, <&pcie2_phy>; - phy-names = "pcie-phy0", "pcie-phy1"; -}; - -&pcie1_ep { - num-lanes = <2>; - phys = <&pcie1_phy>, <&pcie2_phy>; - phy-names = "pcie-phy0", "pcie-phy1"; -}; - -&extcon_usb1 { - vbus-gpio = <&pcf_lcd 14 GPIO_ACTIVE_HIGH>; -}; - -&extcon_usb2 { - vbus-gpio = <&pcf_lcd 15 GPIO_ACTIVE_HIGH>; -}; - -&m_can0 { - can-transceiver { - max-bitrate = <5000000>; - }; -}; diff --git a/sys/gnu/dts/arm/dra76x-mmc-iodelay.dtsi b/sys/gnu/dts/arm/dra76x-mmc-iodelay.dtsi deleted file mode 100644 index fdca4818691..00000000000 --- a/sys/gnu/dts/arm/dra76x-mmc-iodelay.dtsi +++ /dev/null @@ -1,285 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (c) 2018 Texas Instruments -// MMC IOdelay values for TI's DRA76x and AM576x SoCs. -// Author: Sekhar Nori - -/* - * Rules for modifying this file: - * a) Update of this file should typically correspond to a datamanual revision. - * Datamanual revision that was used should be updated in comment below. - * If there is no update to datamanual, do not update the values. If you - * need to use values different from that recommended by the datamanual - * for your design, then you should consider adding values to the device- - * -tree file for your board directly. - * b) We keep the mode names as close to the datamanual as possible. So - * if the manual calls a mode, DDR50, or DDR or DDR 1.8v or DDR 3.3v, - * we follow that in code too. - * c) If the values change between multiple revisions of silicon, we add - * a revision tag to both the new and old entry. Use 'rev11' for PG 1.1, - * 'rev20' for PG 2.0 and so on. - * d) The node name and node label should be the exact same string. This is - * to curb naming creativity and achieve consistency. - * - * Datamanual Revisions: - * - * DRA76x Silicon Revision 1.0: SPRS993E, Revised December 2018 - * - */ - -&dra7_pmx_core { - mmc1_pins_default: mmc1_pins_default { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ - DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ - DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ - DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ - DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ - DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ - >; - }; - - mmc1_pins_hs: mmc1_pins_hs { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_clk.clk */ - DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_cmd.cmd */ - DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat0.dat0 */ - DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat1.dat1 */ - DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat2.dat2 */ - DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat3.dat3 */ - >; - }; - - mmc1_pins_sdr50: mmc1_pins_sdr50 { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_clk.clk */ - DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_cmd.cmd */ - DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat0.dat0 */ - DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat1.dat1 */ - DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat2.dat2 */ - DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat3.dat3 */ - >; - }; - - mmc1_pins_ddr50: mmc1_pins_ddr50 { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_clk.clk */ - DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_cmd.cmd */ - DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat0.dat0 */ - DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat1.dat1 */ - DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat2.dat2 */ - DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat3.dat3 */ - >; - }; - - mmc2_pins_default: mmc2_pins_default { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ - DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ - DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ - DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ - DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ - DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ - DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ - DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ - DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ - DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ - >; - }; - - mmc2_pins_hs200: mmc2_pins_hs200 { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */ - DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ - DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ - DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ - DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ - DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ - DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ - DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ - DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ - DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ - >; - }; - - mmc3_pins_default: mmc3_pins_default { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_clk.mmc3_clk */ - DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */ - DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */ - DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */ - DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */ - DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */ - >; - }; - - mmc4_pins_hs: mmc4_pins_hs { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */ - DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */ - DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */ - DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_txd.mmc4_dat1 */ - DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */ - DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */ - >; - }; -}; - -&dra7_iodelay_core { - - /* Corresponds to MMC1_DDR_MANUAL1 in datamanual */ - mmc1_iodelay_ddr_conf: mmc1_iodelay_ddr_conf { - pinctrl-pin-array = < - 0x618 A_DELAY_PS(489) G_DELAY_PS(0) /* CFG_MMC1_CLK_IN */ - 0x624 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_IN */ - 0x630 A_DELAY_PS(374) G_DELAY_PS(0) /* CFG_MMC1_DAT0_IN */ - 0x63c A_DELAY_PS(31) G_DELAY_PS(0) /* CFG_MMC1_DAT1_IN */ - 0x648 A_DELAY_PS(56) G_DELAY_PS(0) /* CFG_MMC1_DAT2_IN */ - 0x654 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_IN */ - 0x620 A_DELAY_PS(1355) G_DELAY_PS(0) /* CFG_MMC1_CLK_OUT */ - 0x628 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */ - 0x62c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */ - 0x634 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */ - 0x638 A_DELAY_PS(0) G_DELAY_PS(4) /* CFG_MMC1_DAT0_OUT */ - 0x640 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */ - 0x644 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */ - 0x64c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */ - 0x650 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */ - 0x658 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */ - 0x65c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */ - >; - }; - - /* Corresponds to MMC1_SDR104_MANUAL1 in datamanual */ - mmc1_iodelay_sdr104_conf: mmc1_iodelay_sdr104_conf { - pinctrl-pin-array = < - 0x620 A_DELAY_PS(892) G_DELAY_PS(0) /* CFG_MMC1_CLK_OUT */ - 0x628 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */ - 0x62c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */ - 0x634 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */ - 0x638 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OUT */ - 0x640 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */ - 0x644 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */ - 0x64c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */ - 0x650 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */ - 0x658 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */ - 0x65c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */ - >; - }; - - /* Corresponds to MMC2_HS200_MANUAL1 in datamanual */ - mmc2_iodelay_hs200_conf: mmc2_iodelay_hs200_conf { - pinctrl-pin-array = < - 0x190 A_DELAY_PS(384) G_DELAY_PS(0) /* CFG_GPMC_A19_OEN */ - 0x194 A_DELAY_PS(350) G_DELAY_PS(174) /* CFG_GPMC_A19_OUT */ - 0x1a8 A_DELAY_PS(410) G_DELAY_PS(0) /* CFG_GPMC_A20_OEN */ - 0x1ac A_DELAY_PS(335) G_DELAY_PS(0) /* CFG_GPMC_A20_OUT */ - 0x1b4 A_DELAY_PS(468) G_DELAY_PS(0) /* CFG_GPMC_A21_OEN */ - 0x1b8 A_DELAY_PS(339) G_DELAY_PS(0) /* CFG_GPMC_A21_OUT */ - 0x1c0 A_DELAY_PS(676) G_DELAY_PS(0) /* CFG_GPMC_A22_OEN */ - 0x1c4 A_DELAY_PS(219) G_DELAY_PS(0) /* CFG_GPMC_A22_OUT */ - 0x1d0 A_DELAY_PS(1062) G_DELAY_PS(154) /* CFG_GPMC_A23_OUT */ - 0x1d8 A_DELAY_PS(640) G_DELAY_PS(0) /* CFG_GPMC_A24_OEN */ - 0x1dc A_DELAY_PS(150) G_DELAY_PS(0) /* CFG_GPMC_A24_OUT */ - 0x1e4 A_DELAY_PS(356) G_DELAY_PS(0) /* CFG_GPMC_A25_OEN */ - 0x1e8 A_DELAY_PS(150) G_DELAY_PS(0) /* CFG_GPMC_A25_OUT */ - 0x1f0 A_DELAY_PS(579) G_DELAY_PS(0) /* CFG_GPMC_A26_OEN */ - 0x1f4 A_DELAY_PS(200) G_DELAY_PS(0) /* CFG_GPMC_A26_OUT */ - 0x1fc A_DELAY_PS(435) G_DELAY_PS(0) /* CFG_GPMC_A27_OEN */ - 0x200 A_DELAY_PS(236) G_DELAY_PS(0) /* CFG_GPMC_A27_OUT */ - 0x364 A_DELAY_PS(759) G_DELAY_PS(0) /* CFG_GPMC_CS1_OEN */ - 0x368 A_DELAY_PS(372) G_DELAY_PS(0) /* CFG_GPMC_CS1_OUT */ - >; - }; - - /* Corresponds to MMC3_MANUAL1 in datamanual */ - mmc3_iodelay_manual1_conf: mmc3_iodelay_manual1_conf { - pinctrl-pin-array = < - 0x678 A_DELAY_PS(0) G_DELAY_PS(386) /* CFG_MMC3_CLK_IN */ - 0x680 A_DELAY_PS(605) G_DELAY_PS(0) /* CFG_MMC3_CLK_OUT */ - 0x684 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_IN */ - 0x688 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_OEN */ - 0x68c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_OUT */ - 0x690 A_DELAY_PS(171) G_DELAY_PS(0) /* CFG_MMC3_DAT0_IN */ - 0x694 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT0_OEN */ - 0x698 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT0_OUT */ - 0x69c A_DELAY_PS(221) G_DELAY_PS(0) /* CFG_MMC3_DAT1_IN */ - 0x6a0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT1_OEN */ - 0x6a4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT1_OUT */ - 0x6a8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_IN */ - 0x6ac A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_OEN */ - 0x6b0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_OUT */ - 0x6b4 A_DELAY_PS(474) G_DELAY_PS(0) /* CFG_MMC3_DAT3_IN */ - 0x6b8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT3_OEN */ - 0x6bc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT3_OUT */ - >; - }; - - /* Corresponds to MMC3_MANUAL2 in datamanual */ - mmc3_iodelay_sdr50_conf: mmc3_iodelay_sdr50_conf { - pinctrl-pin-array = < - 0x678 A_DELAY_PS(852) G_DELAY_PS(0) /* CFG_MMC3_CLK_IN */ - 0x680 A_DELAY_PS(94) G_DELAY_PS(0) /* CFG_MMC3_CLK_OUT */ - 0x684 A_DELAY_PS(122) G_DELAY_PS(0) /* CFG_MMC3_CMD_IN */ - 0x688 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_OEN */ - 0x68c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_OUT */ - 0x690 A_DELAY_PS(91) G_DELAY_PS(0) /* CFG_MMC3_DAT0_IN */ - 0x694 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT0_OEN */ - 0x698 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT0_OUT */ - 0x69c A_DELAY_PS(57) G_DELAY_PS(0) /* CFG_MMC3_DAT1_IN */ - 0x6a0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT1_OEN */ - 0x6a4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT1_OUT */ - 0x6a8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_IN */ - 0x6ac A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_OEN */ - 0x6b0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_OUT */ - 0x6b4 A_DELAY_PS(375) G_DELAY_PS(0) /* CFG_MMC3_DAT3_IN */ - 0x6b8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT3_OEN */ - 0x6bc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT3_OUT */ - >; - }; - - /* Corresponds to MMC4_MANUAL1 in datamanual */ - mmc4_iodelay_manual1_conf: mmc4_iodelay_manual1_conf { - pinctrl-pin-array = < - 0x840 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_IN */ - 0x848 A_DELAY_PS(1147) G_DELAY_PS(0) /* CFG_UART1_CTSN_OUT */ - 0x84c A_DELAY_PS(1834) G_DELAY_PS(0) /* CFG_UART1_RTSN_IN */ - 0x850 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OEN */ - 0x854 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OUT */ - 0x870 A_DELAY_PS(2165) G_DELAY_PS(0) /* CFG_UART2_CTSN_IN */ - 0x874 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OEN */ - 0x878 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OUT */ - 0x87c A_DELAY_PS(1929) G_DELAY_PS(64) /* CFG_UART2_RTSN_IN */ - 0x880 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OEN */ - 0x884 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OUT */ - 0x888 A_DELAY_PS(1935) G_DELAY_PS(128) /* CFG_UART2_RXD_IN */ - 0x88c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OEN */ - 0x890 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OUT */ - 0x894 A_DELAY_PS(2172) G_DELAY_PS(44) /* CFG_UART2_TXD_IN */ - 0x898 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OEN */ - 0x89c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OUT */ - >; - }; - - /* Corresponds to MMC4_DS_MANUAL1 in datamanual */ - mmc4_iodelay_default_conf: mmc4_iodelay_default_conf { - pinctrl-pin-array = < - 0x840 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_IN */ - 0x848 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_OUT */ - 0x84c A_DELAY_PS(307) G_DELAY_PS(0) /* CFG_UART1_RTSN_IN */ - 0x850 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OEN */ - 0x854 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OUT */ - 0x870 A_DELAY_PS(785) G_DELAY_PS(0) /* CFG_UART2_CTSN_IN */ - 0x874 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OEN */ - 0x878 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OUT */ - 0x87c A_DELAY_PS(613) G_DELAY_PS(0) /* CFG_UART2_RTSN_IN */ - 0x880 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OEN */ - 0x884 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OUT */ - 0x888 A_DELAY_PS(683) G_DELAY_PS(0) /* CFG_UART2_RXD_IN */ - 0x88c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OEN */ - 0x890 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OUT */ - 0x894 A_DELAY_PS(835) G_DELAY_PS(0) /* CFG_UART2_TXD_IN */ - 0x898 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OEN */ - 0x89c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OUT */ - >; - }; -}; diff --git a/sys/gnu/dts/arm/dra76x.dtsi b/sys/gnu/dts/arm/dra76x.dtsi deleted file mode 100644 index cdcba3f561c..00000000000 --- a/sys/gnu/dts/arm/dra76x.dtsi +++ /dev/null @@ -1,88 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ - */ - -#include "dra74x.dtsi" - -/ { - compatible = "ti,dra762", "ti,dra7"; - - ocp { - target-module@42c01900 { - compatible = "ti,sysc-dra7-mcan", "ti,sysc"; - ranges = <0x0 0x42c00000 0x2000>; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x42c01900 0x4>, - <0x42c01904 0x4>, - <0x42c01908 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET | - SYSC_DRA7_MCAN_ENAWAKEUP)>; - ti,syss-mask = <1>; - clocks = <&wkupaon_clkctrl DRA7_WKUPAON_ADC_CLKCTRL 0>; - clock-names = "fck"; - - m_can0: mcan@1a00 { - compatible = "bosch,m_can"; - reg = <0x1a00 0x4000>, <0x0 0x18FC>; - reg-names = "m_can", "message_ram"; - interrupt-parent = <&gic>; - interrupts = , - ; - interrupt-names = "int0", "int1"; - clocks = <&mcan_clk>, <&l3_iclk_div>; - clock-names = "cclk", "hclk"; - bosch,mram-cfg = <0x0 0 0 32 0 0 1 1>; - }; - }; - }; - -}; - -/* MCAN interrupts are hard-wired to irqs 67, 68 */ -&crossbar_mpu { - ti,irqs-skip = <10 67 68 133 139 140>; -}; - -&scm_conf_clocks { - dpll_gmac_h14x2_ctrl_ck: dpll_gmac_h14x2_ctrl_ck@3fc { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_gmac_x2_ck>; - ti,max-div = <63>; - reg = <0x03fc>; - ti,bit-shift=<20>; - ti,latch-bit=<26>; - assigned-clocks = <&dpll_gmac_h14x2_ctrl_ck>; - assigned-clock-rates = <80000000>; - }; - - dpll_gmac_h14x2_ctrl_mux_ck: dpll_gmac_h14x2_ctrl_mux_ck@3fc { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&dpll_gmac_ck>, <&dpll_gmac_h14x2_ctrl_ck>; - reg = <0x3fc>; - ti,bit-shift = <29>; - ti,latch-bit=<26>; - assigned-clocks = <&dpll_gmac_h14x2_ctrl_mux_ck>; - assigned-clock-parents = <&dpll_gmac_h14x2_ctrl_ck>; - }; - - mcan_clk: mcan_clk@3fc { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&dpll_gmac_h14x2_ctrl_mux_ck>; - ti,bit-shift = <27>; - reg = <0x3fc>; - }; -}; - -&rtctarget { - status = "disabled"; -}; - -&usb4_tm { - status = "disabled"; -}; diff --git a/sys/gnu/dts/arm/dra7xx-clocks.dtsi b/sys/gnu/dts/arm/dra7xx-clocks.dtsi deleted file mode 100644 index 93e1eb83bed..00000000000 --- a/sys/gnu/dts/arm/dra7xx-clocks.dtsi +++ /dev/null @@ -1,1815 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Device Tree Source for DRA7xx clock data - * - * Copyright (C) 2013 Texas Instruments, Inc. - */ -&cm_core_aon_clocks { - atl_clkin0_ck: atl_clkin0_ck { - #clock-cells = <0>; - compatible = "ti,dra7-atl-clock"; - clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>; - }; - - atl_clkin1_ck: atl_clkin1_ck { - #clock-cells = <0>; - compatible = "ti,dra7-atl-clock"; - clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>; - }; - - atl_clkin2_ck: atl_clkin2_ck { - #clock-cells = <0>; - compatible = "ti,dra7-atl-clock"; - clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>; - }; - - atl_clkin3_ck: atl_clkin3_ck { - #clock-cells = <0>; - compatible = "ti,dra7-atl-clock"; - clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>; - }; - - hdmi_clkin_ck: hdmi_clkin_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - mlb_clkin_ck: mlb_clkin_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - mlbp_clkin_ck: mlbp_clkin_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - pciesref_acs_clk_ck: pciesref_acs_clk_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <100000000>; - }; - - ref_clkin0_ck: ref_clkin0_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - ref_clkin1_ck: ref_clkin1_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - ref_clkin2_ck: ref_clkin2_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - ref_clkin3_ck: ref_clkin3_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - rmii_clk_ck: rmii_clk_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - sdvenc_clkin_ck: sdvenc_clkin_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - secure_32k_clk_src_ck: secure_32k_clk_src_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - sys_clk32_crystal_ck: sys_clk32_crystal_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - sys_clk32_pseudo_ck: sys_clk32_pseudo_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&sys_clkin1>; - clock-mult = <1>; - clock-div = <610>; - }; - - virt_12000000_ck: virt_12000000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <12000000>; - }; - - virt_13000000_ck: virt_13000000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <13000000>; - }; - - virt_16800000_ck: virt_16800000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <16800000>; - }; - - virt_19200000_ck: virt_19200000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <19200000>; - }; - - virt_20000000_ck: virt_20000000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <20000000>; - }; - - virt_26000000_ck: virt_26000000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <26000000>; - }; - - virt_27000000_ck: virt_27000000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <27000000>; - }; - - virt_38400000_ck: virt_38400000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <38400000>; - }; - - sys_clkin2: sys_clkin2 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <22579200>; - }; - - usb_otg_clkin_ck: usb_otg_clkin_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - video1_clkin_ck: video1_clkin_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - video1_m2_clkin_ck: video1_m2_clkin_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - video2_clkin_ck: video2_clkin_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - video2_m2_clkin_ck: video2_m2_clkin_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - dpll_abe_ck: dpll_abe_ck@1e0 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-m4xen-clock"; - clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>; - reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>; - }; - - dpll_abe_x2_ck: dpll_abe_x2_ck { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-x2-clock"; - clocks = <&dpll_abe_ck>; - }; - - dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@1f0 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_abe_x2_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x01f0>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - abe_clk: abe_clk@108 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_abe_m2x2_ck>; - ti,max-div = <4>; - reg = <0x0108>; - ti,index-power-of-two; - }; - - dpll_abe_m2_ck: dpll_abe_m2_ck@1f0 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_abe_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x01f0>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_abe_x2_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x01f4>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_core_byp_mux: dpll_core_byp_mux@12c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; - ti,bit-shift = <23>; - reg = <0x012c>; - }; - - dpll_core_ck: dpll_core_ck@120 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-core-clock"; - clocks = <&sys_clkin1>, <&dpll_core_byp_mux>; - reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>; - }; - - dpll_core_x2_ck: dpll_core_x2_ck { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-x2-clock"; - clocks = <&dpll_core_ck>; - }; - - dpll_core_h12x2_ck: dpll_core_h12x2_ck@13c { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <63>; - ti,autoidle-shift = <8>; - reg = <0x013c>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_core_h12x2_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - dpll_mpu_ck: dpll_mpu_ck@160 { - #clock-cells = <0>; - compatible = "ti,omap5-mpu-dpll-clock"; - clocks = <&sys_clkin1>, <&mpu_dpll_hs_clk_div>; - reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>; - }; - - dpll_mpu_m2_ck: dpll_mpu_m2_ck@170 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_mpu_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x0170>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - mpu_dclk_div: mpu_dclk_div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_mpu_m2_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - dsp_dpll_hs_clk_div: dsp_dpll_hs_clk_div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_core_h12x2_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - dpll_dsp_byp_mux: dpll_dsp_byp_mux@240 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin1>, <&dsp_dpll_hs_clk_div>; - ti,bit-shift = <23>; - reg = <0x0240>; - }; - - dpll_dsp_ck: dpll_dsp_ck@234 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-clock"; - clocks = <&sys_clkin1>, <&dpll_dsp_byp_mux>; - reg = <0x0234>, <0x0238>, <0x0240>, <0x023c>; - assigned-clocks = <&dpll_dsp_ck>; - assigned-clock-rates = <600000000>; - }; - - dpll_dsp_m2_ck: dpll_dsp_m2_ck@244 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_dsp_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x0244>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - assigned-clocks = <&dpll_dsp_m2_ck>; - assigned-clock-rates = <600000000>; - }; - - iva_dpll_hs_clk_div: iva_dpll_hs_clk_div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_core_h12x2_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - dpll_iva_byp_mux: dpll_iva_byp_mux@1ac { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>; - ti,bit-shift = <23>; - reg = <0x01ac>; - }; - - dpll_iva_ck: dpll_iva_ck@1a0 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-clock"; - clocks = <&sys_clkin1>, <&dpll_iva_byp_mux>; - reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>; - assigned-clocks = <&dpll_iva_ck>; - assigned-clock-rates = <1165000000>; - }; - - dpll_iva_m2_ck: dpll_iva_m2_ck@1b0 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_iva_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x01b0>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - assigned-clocks = <&dpll_iva_m2_ck>; - assigned-clock-rates = <388333334>; - }; - - iva_dclk: iva_dclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_iva_m2_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - dpll_gpu_byp_mux: dpll_gpu_byp_mux@2e4 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; - ti,bit-shift = <23>; - reg = <0x02e4>; - }; - - dpll_gpu_ck: dpll_gpu_ck@2d8 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-clock"; - clocks = <&sys_clkin1>, <&dpll_gpu_byp_mux>; - reg = <0x02d8>, <0x02dc>, <0x02e4>, <0x02e0>; - assigned-clocks = <&dpll_gpu_ck>; - assigned-clock-rates = <1277000000>; - }; - - dpll_gpu_m2_ck: dpll_gpu_m2_ck@2e8 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_gpu_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x02e8>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - assigned-clocks = <&dpll_gpu_m2_ck>; - assigned-clock-rates = <425666667>; - }; - - dpll_core_m2_ck: dpll_core_m2_ck@130 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_core_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x0130>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - core_dpll_out_dclk_div: core_dpll_out_dclk_div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_core_m2_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - dpll_ddr_byp_mux: dpll_ddr_byp_mux@21c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; - ti,bit-shift = <23>; - reg = <0x021c>; - }; - - dpll_ddr_ck: dpll_ddr_ck@210 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-clock"; - clocks = <&sys_clkin1>, <&dpll_ddr_byp_mux>; - reg = <0x0210>, <0x0214>, <0x021c>, <0x0218>; - }; - - dpll_ddr_m2_ck: dpll_ddr_m2_ck@220 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_ddr_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x0220>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_gmac_byp_mux: dpll_gmac_byp_mux@2b4 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; - ti,bit-shift = <23>; - reg = <0x02b4>; - }; - - dpll_gmac_ck: dpll_gmac_ck@2a8 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-clock"; - clocks = <&sys_clkin1>, <&dpll_gmac_byp_mux>; - reg = <0x02a8>, <0x02ac>, <0x02b4>, <0x02b0>; - }; - - dpll_gmac_m2_ck: dpll_gmac_m2_ck@2b8 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_gmac_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x02b8>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - video2_dclk_div: video2_dclk_div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&video2_m2_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - video1_dclk_div: video1_dclk_div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&video1_m2_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - hdmi_dclk_div: hdmi_dclk_div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&hdmi_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - per_dpll_hs_clk_div: per_dpll_hs_clk_div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_abe_m3x2_ck>; - clock-mult = <1>; - clock-div = <2>; - }; - - usb_dpll_hs_clk_div: usb_dpll_hs_clk_div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_abe_m3x2_ck>; - clock-mult = <1>; - clock-div = <3>; - }; - - eve_dpll_hs_clk_div: eve_dpll_hs_clk_div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_core_h12x2_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - dpll_eve_byp_mux: dpll_eve_byp_mux@290 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin1>, <&eve_dpll_hs_clk_div>; - ti,bit-shift = <23>; - reg = <0x0290>; - }; - - dpll_eve_ck: dpll_eve_ck@284 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-clock"; - clocks = <&sys_clkin1>, <&dpll_eve_byp_mux>; - reg = <0x0284>, <0x0288>, <0x0290>, <0x028c>; - }; - - dpll_eve_m2_ck: dpll_eve_m2_ck@294 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_eve_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x0294>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - eve_dclk_div: eve_dclk_div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_eve_m2_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - dpll_core_h13x2_ck: dpll_core_h13x2_ck@140 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <63>; - ti,autoidle-shift = <8>; - reg = <0x0140>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_core_h14x2_ck: dpll_core_h14x2_ck@144 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <63>; - ti,autoidle-shift = <8>; - reg = <0x0144>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_core_h22x2_ck: dpll_core_h22x2_ck@154 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <63>; - ti,autoidle-shift = <8>; - reg = <0x0154>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_core_h23x2_ck: dpll_core_h23x2_ck@158 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <63>; - ti,autoidle-shift = <8>; - reg = <0x0158>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_core_h24x2_ck: dpll_core_h24x2_ck@15c { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <63>; - ti,autoidle-shift = <8>; - reg = <0x015c>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_ddr_x2_ck: dpll_ddr_x2_ck { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-x2-clock"; - clocks = <&dpll_ddr_ck>; - }; - - dpll_ddr_h11x2_ck: dpll_ddr_h11x2_ck@228 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_ddr_x2_ck>; - ti,max-div = <63>; - ti,autoidle-shift = <8>; - reg = <0x0228>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_dsp_x2_ck: dpll_dsp_x2_ck { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-x2-clock"; - clocks = <&dpll_dsp_ck>; - }; - - dpll_dsp_m3x2_ck: dpll_dsp_m3x2_ck@248 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_dsp_x2_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x0248>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - assigned-clocks = <&dpll_dsp_m3x2_ck>; - assigned-clock-rates = <400000000>; - }; - - dpll_gmac_x2_ck: dpll_gmac_x2_ck { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-x2-clock"; - clocks = <&dpll_gmac_ck>; - }; - - dpll_gmac_h11x2_ck: dpll_gmac_h11x2_ck@2c0 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_gmac_x2_ck>; - ti,max-div = <63>; - ti,autoidle-shift = <8>; - reg = <0x02c0>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_gmac_h12x2_ck: dpll_gmac_h12x2_ck@2c4 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_gmac_x2_ck>; - ti,max-div = <63>; - ti,autoidle-shift = <8>; - reg = <0x02c4>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_gmac_h13x2_ck: dpll_gmac_h13x2_ck@2c8 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_gmac_x2_ck>; - ti,max-div = <63>; - ti,autoidle-shift = <8>; - reg = <0x02c8>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_gmac_m3x2_ck: dpll_gmac_m3x2_ck@2bc { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_gmac_x2_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x02bc>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - gmii_m_clk_div: gmii_m_clk_div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_gmac_h11x2_ck>; - clock-mult = <1>; - clock-div = <2>; - }; - - hdmi_clk2_div: hdmi_clk2_div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&hdmi_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - hdmi_div_clk: hdmi_div_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&hdmi_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - l3_iclk_div: l3_iclk_div@100 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - ti,max-div = <2>; - ti,bit-shift = <4>; - reg = <0x0100>; - clocks = <&dpll_core_h12x2_ck>; - ti,index-power-of-two; - }; - - l4_root_clk_div: l4_root_clk_div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&l3_iclk_div>; - clock-mult = <1>; - clock-div = <2>; - }; - - video1_clk2_div: video1_clk2_div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&video1_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - video1_div_clk: video1_div_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&video1_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - video2_clk2_div: video2_clk2_div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&video2_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - video2_div_clk: video2_div_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&video2_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - ipu1_gfclk_mux: ipu1_gfclk_mux@520 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&dpll_abe_m2x2_ck>, <&dpll_core_h22x2_ck>; - ti,bit-shift = <24>; - reg = <0x0520>; - assigned-clocks = <&ipu1_gfclk_mux>; - assigned-clock-parents = <&dpll_core_h22x2_ck>; - }; - - dummy_ck: dummy_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; -}; -&prm_clocks { - sys_clkin1: sys_clkin1@110 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&virt_12000000_ck>, <&virt_20000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>; - reg = <0x0110>; - ti,index-starts-at-one; - }; - - abe_dpll_sys_clk_mux: abe_dpll_sys_clk_mux@118 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin1>, <&sys_clkin2>; - reg = <0x0118>; - }; - - abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux@114 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>; - reg = <0x0114>; - }; - - abe_dpll_clk_mux: abe_dpll_clk_mux@10c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>; - reg = <0x010c>; - }; - - abe_24m_fclk: abe_24m_fclk@11c { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_abe_m2x2_ck>; - reg = <0x011c>; - ti,dividers = <8>, <16>; - }; - - aess_fclk: aess_fclk@178 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&abe_clk>; - reg = <0x0178>; - ti,max-div = <2>; - }; - - abe_giclk_div: abe_giclk_div@174 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&aess_fclk>; - reg = <0x0174>; - ti,max-div = <2>; - }; - - abe_lp_clk_div: abe_lp_clk_div@1d8 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_abe_m2x2_ck>; - reg = <0x01d8>; - ti,dividers = <16>, <32>; - }; - - abe_sys_clk_div: abe_sys_clk_div@120 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&sys_clkin1>; - reg = <0x0120>; - ti,max-div = <2>; - }; - - adc_gfclk_mux: adc_gfclk_mux@1dc { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin1>, <&sys_clkin2>, <&sys_32k_ck>; - reg = <0x01dc>; - }; - - sys_clk1_dclk_div: sys_clk1_dclk_div@1c8 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&sys_clkin1>; - ti,max-div = <64>; - reg = <0x01c8>; - ti,index-power-of-two; - }; - - sys_clk2_dclk_div: sys_clk2_dclk_div@1cc { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&sys_clkin2>; - ti,max-div = <64>; - reg = <0x01cc>; - ti,index-power-of-two; - }; - - per_abe_x1_dclk_div: per_abe_x1_dclk_div@1bc { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_abe_m2_ck>; - ti,max-div = <64>; - reg = <0x01bc>; - ti,index-power-of-two; - }; - - dsp_gclk_div: dsp_gclk_div@18c { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_dsp_m2_ck>; - ti,max-div = <64>; - reg = <0x018c>; - ti,index-power-of-two; - }; - - gpu_dclk: gpu_dclk@1a0 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_gpu_m2_ck>; - ti,max-div = <64>; - reg = <0x01a0>; - ti,index-power-of-two; - }; - - emif_phy_dclk_div: emif_phy_dclk_div@190 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_ddr_m2_ck>; - ti,max-div = <64>; - reg = <0x0190>; - ti,index-power-of-two; - }; - - gmac_250m_dclk_div: gmac_250m_dclk_div@19c { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_gmac_m2_ck>; - ti,max-div = <64>; - reg = <0x019c>; - ti,index-power-of-two; - }; - - gmac_main_clk: gmac_main_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&gmac_250m_dclk_div>; - clock-mult = <1>; - clock-div = <2>; - }; - - l3init_480m_dclk_div: l3init_480m_dclk_div@1ac { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_usb_m2_ck>; - ti,max-div = <64>; - reg = <0x01ac>; - ti,index-power-of-two; - }; - - usb_otg_dclk_div: usb_otg_dclk_div@184 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&usb_otg_clkin_ck>; - ti,max-div = <64>; - reg = <0x0184>; - ti,index-power-of-two; - }; - - sata_dclk_div: sata_dclk_div@1c0 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&sys_clkin1>; - ti,max-div = <64>; - reg = <0x01c0>; - ti,index-power-of-two; - }; - - pcie2_dclk_div: pcie2_dclk_div@1b8 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_pcie_ref_m2_ck>; - ti,max-div = <64>; - reg = <0x01b8>; - ti,index-power-of-two; - }; - - pcie_dclk_div: pcie_dclk_div@1b4 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&apll_pcie_m2_ck>; - ti,max-div = <64>; - reg = <0x01b4>; - ti,index-power-of-two; - }; - - emu_dclk_div: emu_dclk_div@194 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&sys_clkin1>; - ti,max-div = <64>; - reg = <0x0194>; - ti,index-power-of-two; - }; - - secure_32k_dclk_div: secure_32k_dclk_div@1c4 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&secure_32k_clk_src_ck>; - ti,max-div = <64>; - reg = <0x01c4>; - ti,index-power-of-two; - }; - - clkoutmux0_clk_mux: clkoutmux0_clk_mux@158 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>; - reg = <0x0158>; - }; - - clkoutmux1_clk_mux: clkoutmux1_clk_mux@15c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>; - reg = <0x015c>; - }; - - clkoutmux2_clk_mux: clkoutmux2_clk_mux@160 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>; - reg = <0x0160>; - }; - - custefuse_sys_gfclk_div: custefuse_sys_gfclk_div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&sys_clkin1>; - clock-mult = <1>; - clock-div = <2>; - }; - - eve_clk: eve_clk@180 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&dpll_eve_m2_ck>, <&dpll_dsp_m3x2_ck>; - reg = <0x0180>; - }; - - hdmi_dpll_clk_mux: hdmi_dpll_clk_mux@164 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin1>, <&sys_clkin2>; - reg = <0x0164>; - }; - - mlb_clk: mlb_clk@134 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&mlb_clkin_ck>; - ti,max-div = <64>; - reg = <0x0134>; - ti,index-power-of-two; - }; - - mlbp_clk: mlbp_clk@130 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&mlbp_clkin_ck>; - ti,max-div = <64>; - reg = <0x0130>; - ti,index-power-of-two; - }; - - per_abe_x1_gfclk2_div: per_abe_x1_gfclk2_div@138 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_abe_m2_ck>; - ti,max-div = <64>; - reg = <0x0138>; - ti,index-power-of-two; - }; - - timer_sys_clk_div: timer_sys_clk_div@144 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&sys_clkin1>; - reg = <0x0144>; - ti,max-div = <2>; - }; - - video1_dpll_clk_mux: video1_dpll_clk_mux@168 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin1>, <&sys_clkin2>; - reg = <0x0168>; - }; - - video2_dpll_clk_mux: video2_dpll_clk_mux@16c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin1>, <&sys_clkin2>; - reg = <0x016c>; - }; - - wkupaon_iclk_mux: wkupaon_iclk_mux@108 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin1>, <&abe_lp_clk_div>; - reg = <0x0108>; - }; -}; - -&cm_core_clocks { - dpll_pcie_ref_ck: dpll_pcie_ref_ck@200 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-clock"; - clocks = <&sys_clkin1>, <&sys_clkin1>; - reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>; - }; - - dpll_pcie_ref_m2ldo_ck: dpll_pcie_ref_m2ldo_ck@210 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_pcie_ref_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x0210>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - apll_pcie_in_clk_mux: apll_pcie_in_clk_mux@4ae06118 { - compatible = "ti,mux-clock"; - clocks = <&dpll_pcie_ref_m2ldo_ck>, <&pciesref_acs_clk_ck>; - #clock-cells = <0>; - reg = <0x021c 0x4>; - ti,bit-shift = <7>; - }; - - apll_pcie_ck: apll_pcie_ck@21c { - #clock-cells = <0>; - compatible = "ti,dra7-apll-clock"; - clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>; - reg = <0x021c>, <0x0220>; - }; - - optfclk_pciephy_div: optfclk_pciephy_div@4a00821c { - compatible = "ti,divider-clock"; - clocks = <&apll_pcie_ck>; - #clock-cells = <0>; - reg = <0x021c>; - ti,dividers = <2>, <1>; - ti,bit-shift = <8>; - ti,max-div = <2>; - }; - - apll_pcie_clkvcoldo: apll_pcie_clkvcoldo { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&apll_pcie_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - apll_pcie_clkvcoldo_div: apll_pcie_clkvcoldo_div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&apll_pcie_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - apll_pcie_m2_ck: apll_pcie_m2_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&apll_pcie_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - dpll_per_byp_mux: dpll_per_byp_mux@14c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>; - ti,bit-shift = <23>; - reg = <0x014c>; - }; - - dpll_per_ck: dpll_per_ck@140 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-clock"; - clocks = <&sys_clkin1>, <&dpll_per_byp_mux>; - reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>; - }; - - dpll_per_m2_ck: dpll_per_m2_ck@150 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_per_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x0150>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - func_96m_aon_dclk_div: func_96m_aon_dclk_div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_per_m2_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - dpll_usb_byp_mux: dpll_usb_byp_mux@18c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin1>, <&usb_dpll_hs_clk_div>; - ti,bit-shift = <23>; - reg = <0x018c>; - }; - - dpll_usb_ck: dpll_usb_ck@180 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-j-type-clock"; - clocks = <&sys_clkin1>, <&dpll_usb_byp_mux>; - reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>; - }; - - dpll_usb_m2_ck: dpll_usb_m2_ck@190 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_usb_ck>; - ti,max-div = <127>; - ti,autoidle-shift = <8>; - reg = <0x0190>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_pcie_ref_m2_ck: dpll_pcie_ref_m2_ck@210 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_pcie_ref_ck>; - ti,max-div = <127>; - ti,autoidle-shift = <8>; - reg = <0x0210>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_per_x2_ck: dpll_per_x2_ck { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-x2-clock"; - clocks = <&dpll_per_ck>; - }; - - dpll_per_h11x2_ck: dpll_per_h11x2_ck@158 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_per_x2_ck>; - ti,max-div = <63>; - ti,autoidle-shift = <8>; - reg = <0x0158>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_per_h12x2_ck: dpll_per_h12x2_ck@15c { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_per_x2_ck>; - ti,max-div = <63>; - ti,autoidle-shift = <8>; - reg = <0x015c>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_per_h13x2_ck: dpll_per_h13x2_ck@160 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_per_x2_ck>; - ti,max-div = <63>; - ti,autoidle-shift = <8>; - reg = <0x0160>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_per_h14x2_ck: dpll_per_h14x2_ck@164 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_per_x2_ck>; - ti,max-div = <63>; - ti,autoidle-shift = <8>; - reg = <0x0164>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_per_m2x2_ck: dpll_per_m2x2_ck@150 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_per_x2_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x0150>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_usb_clkdcoldo: dpll_usb_clkdcoldo { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_usb_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - func_128m_clk: func_128m_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_per_h11x2_ck>; - clock-mult = <1>; - clock-div = <2>; - }; - - func_12m_fclk: func_12m_fclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_per_m2x2_ck>; - clock-mult = <1>; - clock-div = <16>; - }; - - func_24m_clk: func_24m_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_per_m2_ck>; - clock-mult = <1>; - clock-div = <4>; - }; - - func_48m_fclk: func_48m_fclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_per_m2x2_ck>; - clock-mult = <1>; - clock-div = <4>; - }; - - func_96m_fclk: func_96m_fclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_per_m2x2_ck>; - clock-mult = <1>; - clock-div = <2>; - }; - - l3init_60m_fclk: l3init_60m_fclk@104 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_usb_m2_ck>; - reg = <0x0104>; - ti,dividers = <1>, <8>; - }; - - clkout2_clk: clkout2_clk@6b0 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&clkoutmux2_clk_mux>; - ti,bit-shift = <8>; - reg = <0x06b0>; - }; - - l3init_960m_gfclk: l3init_960m_gfclk@6c0 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&dpll_usb_clkdcoldo>; - ti,bit-shift = <8>; - reg = <0x06c0>; - }; - - usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k@640 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_32k_ck>; - ti,bit-shift = <8>; - reg = <0x0640>; - }; - - usb_phy2_always_on_clk32k: usb_phy2_always_on_clk32k@688 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_32k_ck>; - ti,bit-shift = <8>; - reg = <0x0688>; - }; - - usb_phy3_always_on_clk32k: usb_phy3_always_on_clk32k@698 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_32k_ck>; - ti,bit-shift = <8>; - reg = <0x0698>; - }; - - gpu_core_gclk_mux: gpu_core_gclk_mux@1220 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>; - ti,bit-shift = <24>; - reg = <0x1220>; - assigned-clocks = <&gpu_core_gclk_mux>; - assigned-clock-parents = <&dpll_gpu_m2_ck>; - }; - - gpu_hyd_gclk_mux: gpu_hyd_gclk_mux@1220 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>; - ti,bit-shift = <26>; - reg = <0x1220>; - assigned-clocks = <&gpu_hyd_gclk_mux>; - assigned-clock-parents = <&dpll_gpu_m2_ck>; - }; - - l3instr_ts_gclk_div: l3instr_ts_gclk_div@e50 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&wkupaon_iclk_mux>; - ti,bit-shift = <24>; - reg = <0x0e50>; - ti,dividers = <8>, <16>, <32>; - }; - - vip1_gclk_mux: vip1_gclk_mux@1020 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>; - ti,bit-shift = <24>; - reg = <0x1020>; - }; - - vip2_gclk_mux: vip2_gclk_mux@1028 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>; - ti,bit-shift = <24>; - reg = <0x1028>; - }; - - vip3_gclk_mux: vip3_gclk_mux@1030 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>; - ti,bit-shift = <24>; - reg = <0x1030>; - }; -}; - -&cm_core_clockdomains { - coreaon_clkdm: coreaon_clkdm { - compatible = "ti,clockdomain"; - clocks = <&dpll_usb_ck>; - }; -}; - -&scm_conf_clocks { - dss_deshdcp_clk: dss_deshdcp_clk@558 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&l3_iclk_div>; - ti,bit-shift = <0>; - reg = <0x558>; - }; - - ehrpwm0_tbclk: ehrpwm0_tbclk@558 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&l4_root_clk_div>; - ti,bit-shift = <20>; - reg = <0x0558>; - }; - - ehrpwm1_tbclk: ehrpwm1_tbclk@558 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&l4_root_clk_div>; - ti,bit-shift = <21>; - reg = <0x0558>; - }; - - ehrpwm2_tbclk: ehrpwm2_tbclk@558 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&l4_root_clk_div>; - ti,bit-shift = <22>; - reg = <0x0558>; - }; - - sys_32k_ck: sys_32k_ck { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clk32_crystal_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>; - ti,bit-shift = <8>; - reg = <0x6c4>; - }; -}; - -&cm_core_aon { - mpu_cm: mpu-cm@300 { - compatible = "ti,omap4-cm"; - reg = <0x300 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x300 0x100>; - - mpu_clkctrl: mpu-clkctrl@20 { - compatible = "ti,clkctrl"; - reg = <0x20 0x4>; - #clock-cells = <2>; - }; - - }; - - dsp1_cm: dsp1-cm@400 { - compatible = "ti,omap4-cm"; - reg = <0x400 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x400 0x100>; - - dsp1_clkctrl: dsp1-clkctrl@20 { - compatible = "ti,clkctrl"; - reg = <0x20 0x4>; - #clock-cells = <2>; - }; - - }; - - ipu_cm: ipu-cm@500 { - compatible = "ti,omap4-cm"; - reg = <0x500 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x500 0x100>; - - ipu1_clkctrl: ipu1-clkctrl@20 { - compatible = "ti,clkctrl"; - reg = <0x20 0x4>; - #clock-cells = <2>; - }; - - ipu_clkctrl: ipu-clkctrl@50 { - compatible = "ti,clkctrl"; - reg = <0x50 0x34>; - #clock-cells = <2>; - }; - - }; - - dsp2_cm: dsp2-cm@600 { - compatible = "ti,omap4-cm"; - reg = <0x600 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x600 0x100>; - - dsp2_clkctrl: dsp2-clkctrl@20 { - compatible = "ti,clkctrl"; - reg = <0x20 0x4>; - #clock-cells = <2>; - }; - - }; - - rtc_cm: rtc-cm@700 { - compatible = "ti,omap4-cm"; - reg = <0x700 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x700 0x100>; - - rtc_clkctrl: rtc-clkctrl@20 { - compatible = "ti,clkctrl"; - reg = <0x20 0x28>; - #clock-cells = <2>; - }; - }; - -}; - -&cm_core { - coreaon_cm: coreaon-cm@600 { - compatible = "ti,omap4-cm"; - reg = <0x600 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x600 0x100>; - - coreaon_clkctrl: coreaon-clkctrl@20 { - compatible = "ti,clkctrl"; - reg = <0x20 0x1c>; - #clock-cells = <2>; - }; - }; - - l3main1_cm: l3main1-cm@700 { - compatible = "ti,omap4-cm"; - reg = <0x700 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x700 0x100>; - - l3main1_clkctrl: l3main1-clkctrl@20 { - compatible = "ti,clkctrl"; - reg = <0x20 0x74>; - #clock-cells = <2>; - }; - - }; - - ipu2_cm: ipu2-cm@900 { - compatible = "ti,omap4-cm"; - reg = <0x900 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x900 0x100>; - - ipu2_clkctrl: ipu2-clkctrl@20 { - compatible = "ti,clkctrl"; - reg = <0x20 0x4>; - #clock-cells = <2>; - }; - - }; - - dma_cm: dma-cm@a00 { - compatible = "ti,omap4-cm"; - reg = <0xa00 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0xa00 0x100>; - - dma_clkctrl: dma-clkctrl@20 { - compatible = "ti,clkctrl"; - reg = <0x20 0x4>; - #clock-cells = <2>; - }; - }; - - emif_cm: emif-cm@b00 { - compatible = "ti,omap4-cm"; - reg = <0xb00 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0xb00 0x100>; - - emif_clkctrl: emif-clkctrl@20 { - compatible = "ti,clkctrl"; - reg = <0x20 0x4>; - #clock-cells = <2>; - }; - }; - - atl_cm: atl-cm@c00 { - compatible = "ti,omap4-cm"; - reg = <0xc00 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0xc00 0x100>; - - atl_clkctrl: atl-clkctrl@0 { - compatible = "ti,clkctrl"; - reg = <0x0 0x4>; - #clock-cells = <2>; - }; - }; - - l4cfg_cm: l4cfg-cm@d00 { - compatible = "ti,omap4-cm"; - reg = <0xd00 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0xd00 0x100>; - - l4cfg_clkctrl: l4cfg-clkctrl@20 { - compatible = "ti,clkctrl"; - reg = <0x20 0x84>; - #clock-cells = <2>; - }; - }; - - l3instr_cm: l3instr-cm@e00 { - compatible = "ti,omap4-cm"; - reg = <0xe00 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0xe00 0x100>; - - l3instr_clkctrl: l3instr-clkctrl@20 { - compatible = "ti,clkctrl"; - reg = <0x20 0xc>; - #clock-cells = <2>; - }; - }; - - dss_cm: dss-cm@1100 { - compatible = "ti,omap4-cm"; - reg = <0x1100 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1100 0x100>; - - dss_clkctrl: dss-clkctrl@20 { - compatible = "ti,clkctrl"; - reg = <0x20 0x14>; - #clock-cells = <2>; - }; - }; - - l3init_cm: l3init-cm@1300 { - compatible = "ti,omap4-cm"; - reg = <0x1300 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1300 0x100>; - - l3init_clkctrl: l3init-clkctrl@20 { - compatible = "ti,clkctrl"; - reg = <0x20 0x6c>, <0xe0 0x14>; - #clock-cells = <2>; - }; - - pcie_clkctrl: pcie-clkctrl@b0 { - compatible = "ti,clkctrl"; - reg = <0xb0 0xc>; - #clock-cells = <2>; - }; - - gmac_clkctrl: gmac-clkctrl@d0 { - compatible = "ti,clkctrl"; - reg = <0xd0 0x4>; - #clock-cells = <2>; - }; - - }; - - l4per_cm: l4per-cm@1700 { - compatible = "ti,omap4-cm"; - reg = <0x1700 0x300>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1700 0x300>; - - l4per_clkctrl: l4per-clkctrl@28 { - compatible = "ti,clkctrl"; - reg = <0x28 0x64>, <0xa0 0x24>, <0xf0 0x3c>, <0x140 0x1c>, <0x170 0x4>; - #clock-cells = <2>; - - assigned-clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>; - assigned-clock-parents = <&abe_24m_fclk>; - }; - - l4sec_clkctrl: l4sec-clkctrl@1a0 { - compatible = "ti,clkctrl"; - reg = <0x1a0 0x2c>; - #clock-cells = <2>; - }; - - l4per2_clkctrl: l4per2-clkctrl@c { - compatible = "ti,clkctrl"; - reg = <0xc 0x4>, <0x18 0xc>, <0x90 0xc>, <0xc4 0x4>, <0x138 0x4>, <0x160 0xc>, <0x178 0x24>, <0x1d0 0x3c>; - #clock-cells = <2>; - }; - - l4per3_clkctrl: l4per3-clkctrl@14 { - compatible = "ti,clkctrl"; - reg = <0x14 0x4>, <0xc8 0x14>, <0x130 0x4>; - #clock-cells = <2>; - }; - }; - -}; - -&prm { - wkupaon_cm: wkupaon-cm@1800 { - compatible = "ti,omap4-cm"; - reg = <0x1800 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1800 0x100>; - - wkupaon_clkctrl: wkupaon-clkctrl@20 { - compatible = "ti,clkctrl"; - reg = <0x20 0x6c>; - #clock-cells = <2>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/e60k02.dtsi b/sys/gnu/dts/arm/e60k02.dtsi deleted file mode 100644 index ce50c4dc6f2..00000000000 --- a/sys/gnu/dts/arm/e60k02.dtsi +++ /dev/null @@ -1,302 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2019 Andreas Kemnade - * based on works - * Copyright 2016 Freescale Semiconductor, Inc. - * and - * Copyright (C) 2014 Ricoh Electronic Devices Co., Ltd - * - * Netronix E60K02 board common. - * This board is equipped with different SoCs and - * found in ebook-readers like the Kobo Clara HD (with i.MX6SLL) and - * the Tolino Shine 3 (with i.MX6SL) - */ -#include - -/ { - - chosen { - stdout-path = &uart1; - }; - - gpio_keys: gpio-keys { - compatible = "gpio-keys"; - - power { - label = "Power"; - gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - - cover { - label = "Cover"; - gpios = <&gpio5 12 GPIO_ACTIVE_LOW>; - linux,code = ; - linux,input-type = ; - wakeup-source; - }; - }; - - leds: leds { - compatible = "gpio-leds"; - - on { - label = "e60k02:white:on"; - gpios = <&gpio5 7 GPIO_ACTIVE_LOW>; - linux,default-trigger = "timer"; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000>; - }; - - reg_wifi: regulator-wifi { - compatible = "regulator-fixed"; - regulator-name = "SD3_SPWR"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-simple"; - post-power-on-delay-ms = <20>; - reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; - }; -}; - - -&i2c1 { - clock-frequency = <100000>; - status = "okay"; - - lm3630a: backlight@36 { - reg = <0x36>; - compatible = "ti,lm3630a"; - enable-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; - - #address-cells = <1>; - #size-cells = <0>; - - led@0 { - reg = <0>; - led-sources = <0>; - label = "backlight_warm"; - default-brightness = <0>; - max-brightness = <255>; - }; - - led@1 { - reg = <1>; - led-sources = <1>; - label = "backlight_cold"; - default-brightness = <0>; - max-brightness = <255>; - }; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - status = "okay"; - - /* TODO: CYTTSP5 touch controller at 0x24 */ - - /* TODO: TPS65185 PMIC for E Ink at 0x68 */ - -}; - -&i2c3 { - clock-frequency = <100000>; - status = "okay"; - - ricoh619: pmic@32 { - compatible = "ricoh,rc5t619"; - reg = <0x32>; - system-power-controller; - - regulators { - dcdc1_reg: DCDC1 { - regulator-name = "DCDC1"; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-max-microvolt = <900000>; - regulator-suspend-min-microvolt = <900000>; - }; - }; - - /* Core3_3V3 */ - dcdc2_reg: DCDC2 { - regulator-name = "DCDC2"; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-max-microvolt = <3300000>; - regulator-suspend-min-microvolt = <3300000>; - }; - }; - - dcdc3_reg: DCDC3 { - regulator-name = "DCDC3"; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-max-microvolt = <1140000>; - regulator-suspend-min-microvolt = <1140000>; - }; - }; - - /* Core4_1V2 */ - dcdc4_reg: DCDC4 { - regulator-name = "DCDC4"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-max-microvolt = <1140000>; - regulator-suspend-min-microvolt = <1140000>; - }; - }; - - /* Core4_1V8 */ - dcdc5_reg: DCDC5 { - regulator-name = "DCDC5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-max-microvolt = <1700000>; - regulator-suspend-min-microvolt = <1700000>; - }; - }; - - /* IR_3V3 */ - ldo1_reg: LDO1 { - regulator-name = "LDO1"; - regulator-boot-on; - }; - - /* Core1_3V3 */ - ldo2_reg: LDO2 { - regulator-name = "LDO2"; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-max-microvolt = <3000000>; - regulator-suspend-min-microvolt = <3000000>; - }; - }; - - /* Core5_1V2 */ - ldo3_reg: LDO3 { - regulator-name = "LDO3"; - regulator-always-on; - regulator-boot-on; - }; - - ldo4_reg: LDO4 { - regulator-name = "LDO4"; - regulator-boot-on; - }; - - /* SPD_3V3 */ - ldo5_reg: LDO5 { - regulator-name = "LDO5"; - regulator-always-on; - regulator-boot-on; - }; - - /* DDR_0V6 */ - ldo6_reg: LDO6 { - regulator-name = "LDO6"; - regulator-always-on; - regulator-boot-on; - }; - - /* VDD_PWM */ - ldo7_reg: LDO7 { - regulator-name = "LDO7"; - regulator-always-on; - regulator-boot-on; - }; - - /* ldo_1v8 */ - ldo8_reg: LDO8 { - regulator-name = "LDO8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo9_reg: LDO9 { - regulator-name = "LDO9"; - regulator-boot-on; - }; - - ldo10_reg: LDO10 { - regulator-name = "LDO10"; - regulator-boot-on; - }; - - ldortc1_reg: LDORTC1 { - regulator-name = "LDORTC1"; - regulator-boot-on; - }; - }; - }; -}; - -&snvs_rtc { - /* we are using the rtc in the pmic, not disabled in imx6sll.dtsi */ - status = "disabled"; -}; - -&uart1 { - status = "okay"; -}; - -&usdhc2 { - non-removable; - status = "okay"; -}; - -&usdhc3 { - vmmc-supply = <®_wifi>; - mmc-pwrseq = <&wifi_pwrseq>; - cap-power-off-card; - non-removable; - status = "okay"; -}; - -&usbotg1 { - pinctrl-names = "default"; - disable-over-current; - srp-disable; - hnp-disable; - adp-disable; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/ea3250.dts b/sys/gnu/dts/arm/ea3250.dts deleted file mode 100644 index a4a281fe82a..00000000000 --- a/sys/gnu/dts/arm/ea3250.dts +++ /dev/null @@ -1,274 +0,0 @@ -/* - * Embedded Artists LPC3250 board - * - * Copyright 2012 Roland Stigge - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; -#include "lpc32xx.dtsi" - -/ { - model = "Embedded Artists LPC3250 board based on NXP LPC3250"; - compatible = "ea,ea3250", "nxp,lpc3250"; - #address-cells = <1>; - #size-cells = <1>; - - memory { - device_type = "memory"; - reg = <0x80000000 0x4000000>; - }; - - ahb { - mac: ethernet@31060000 { - phy-mode = "rmii"; - use-iram; - }; - - /* 128MB Flash via SLC NAND controller */ - slc: flash@20020000 { - status = "okay"; - #address-cells = <1>; - #size-cells = <1>; - - nxp,wdr-clks = <14>; - nxp,wwidth = <260000000>; - nxp,whold = <104000000>; - nxp,wsetup = <200000000>; - nxp,rdr-clks = <14>; - nxp,rwidth = <34666666>; - nxp,rhold = <104000000>; - nxp,rsetup = <200000000>; - nand-on-flash-bbt; - gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */ - - mtd0@00000000 { - label = "ea3250-boot"; - reg = <0x00000000 0x00080000>; - read-only; - }; - - mtd1@00080000 { - label = "ea3250-uboot"; - reg = <0x00080000 0x000c0000>; - read-only; - }; - - mtd2@00140000 { - label = "ea3250-kernel"; - reg = <0x00140000 0x00400000>; - }; - - mtd3@00540000 { - label = "ea3250-rootfs"; - reg = <0x00540000 0x07ac0000>; - }; - }; - - apb { - uart5: serial@40090000 { - status = "okay"; - }; - - uart3: serial@40080000 { - status = "okay"; - }; - - uart6: serial@40098000 { - status = "okay"; - }; - - i2c1: i2c@400A0000 { - clock-frequency = <100000>; - - eeprom@50 { - compatible = "at,24c256"; - reg = <0x50>; - }; - - eeprom@57 { - compatible = "at,24c64"; - reg = <0x57>; - }; - - uda1380: uda1380@18 { - compatible = "nxp,uda1380"; - reg = <0x18>; - power-gpio = <&gpio 0x59 0>; - reset-gpio = <&gpio 0x51 0>; - dac-clk = "wspll"; - }; - - pca9532: pca9532@60 { - compatible = "nxp,pca9532"; - gpio-controller; - #gpio-cells = <2>; - reg = <0x60>; - }; - }; - - i2c2: i2c@400A8000 { - clock-frequency = <100000>; - }; - - sd@20098000 { - wp-gpios = <&pca9532 5 0>; - cd-gpios = <&pca9532 4 0>; - cd-inverted; - bus-width = <4>; - status = "okay"; - }; - }; - - fab { - uart1: serial@40014000 { - status = "okay"; - }; - - /* 3-axis accelerometer X,Y,Z (or AD-IN instead of Z) */ - adc@40048000 { - status = "okay"; - }; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - autorepeat; - button@21 { - label = "Interrupt Key"; - linux,code = <103>; - gpios = <&gpio 4 1 0>; /* GPI_P3 1 */ - }; - key1 { - label = "KEY1"; - linux,code = <1>; - gpios = <&pca9532 0 0>; - }; - key2 { - label = "KEY2"; - linux,code = <2>; - gpios = <&pca9532 1 0>; - }; - key3 { - label = "KEY3"; - linux,code = <3>; - gpios = <&pca9532 2 0>; - }; - key4 { - label = "KEY4"; - linux,code = <4>; - gpios = <&pca9532 3 0>; - }; - joy0 { - label = "Joystick Key 0"; - linux,code = <10>; - gpios = <&gpio 2 0 0>; /* P2.0 */ - }; - joy1 { - label = "Joystick Key 1"; - linux,code = <11>; - gpios = <&gpio 2 1 0>; /* P2.1 */ - }; - joy2 { - label = "Joystick Key 2"; - linux,code = <12>; - gpios = <&gpio 2 2 0>; /* P2.2 */ - }; - joy3 { - label = "Joystick Key 3"; - linux,code = <13>; - gpios = <&gpio 2 3 0>; /* P2.3 */ - }; - joy4 { - label = "Joystick Key 4"; - linux,code = <14>; - gpios = <&gpio 2 4 0>; /* P2.4 */ - }; - }; - - leds { - compatible = "gpio-leds"; - - /* LEDs on OEM Board */ - - led1 { - gpios = <&gpio 5 14 1>; /* GPO_P3 14, GPIO 93, active low */ - linux,default-trigger = "timer"; - default-state = "off"; - }; - - led2 { - gpios = <&gpio 2 10 1>; /* P2.10, active low */ - default-state = "off"; - }; - - led3 { - gpios = <&gpio 2 11 1>; /* P2.11, active low */ - default-state = "off"; - }; - - led4 { - gpios = <&gpio 2 12 1>; /* P2.12, active low */ - default-state = "off"; - }; - - /* LEDs on Base Board */ - - lede1 { - gpios = <&pca9532 8 0>; - default-state = "off"; - }; - lede2 { - gpios = <&pca9532 9 0>; - default-state = "off"; - }; - lede3 { - gpios = <&pca9532 10 0>; - default-state = "off"; - }; - lede4 { - gpios = <&pca9532 11 0>; - default-state = "off"; - }; - lede5 { - gpios = <&pca9532 12 0>; - default-state = "off"; - }; - lede6 { - gpios = <&pca9532 13 0>; - default-state = "off"; - }; - lede7 { - gpios = <&pca9532 14 0>; - default-state = "off"; - }; - lede8 { - gpios = <&pca9532 15 0>; - default-state = "off"; - }; - }; -}; - -/* Here, choose exactly one from: ohci, usbd */ -&ohci /* &usbd */ { - transceiver = <&isp1301>; - status = "okay"; -}; - -&i2cusb { - clock-frequency = <100000>; - - isp1301: usb-transceiver@2d { - compatible = "nxp,isp1301"; - reg = <0x2d>; - }; -}; diff --git a/sys/gnu/dts/arm/ecx-2000.dts b/sys/gnu/dts/arm/ecx-2000.dts deleted file mode 100644 index 5651ae6dc96..00000000000 --- a/sys/gnu/dts/arm/ecx-2000.dts +++ /dev/null @@ -1,103 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright 2011-2012 Calxeda, Inc. - */ - -/dts-v1/; - -/* First 4KB has pen for secondary cores. */ -/memreserve/ 0x00000000 0x0001000; - -/ { - model = "Calxeda ECX-2000"; - compatible = "calxeda,ecx-2000"; - #address-cells = <2>; - #size-cells = <2>; - clock-ranges; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <0>; - clocks = <&a9pll>; - clock-names = "cpu"; - }; - - cpu@1 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <1>; - clocks = <&a9pll>; - clock-names = "cpu"; - }; - - cpu@2 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <2>; - clocks = <&a9pll>; - clock-names = "cpu"; - }; - - cpu@3 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <3>; - clocks = <&a9pll>; - clock-names = "cpu"; - }; - }; - - memory@0 { - name = "memory"; - device_type = "memory"; - reg = <0x00000000 0x00000000 0x00000000 0xff800000>; - }; - - memory@200000000 { - name = "memory"; - device_type = "memory"; - reg = <0x00000002 0x00000000 0x00000003 0x00000000>; - }; - - soc { - ranges = <0x00000000 0x00000000 0x00000000 0xffffffff>; - - timer { - compatible = "arm,cortex-a15-timer", "arm,armv7-timer"; interrupts = <1 13 0xf08>, - <1 14 0xf08>, - <1 11 0xf08>, - <1 10 0xf08>; - }; - - memory-controller@fff00000 { - compatible = "calxeda,ecx-2000-ddr-ctrl"; - reg = <0xfff00000 0x1000>; - interrupts = <0 91 4>; - }; - - intc: interrupt-controller@fff11000 { - compatible = "arm,cortex-a15-gic"; - #interrupt-cells = <3>; - #size-cells = <0>; - #address-cells = <1>; - interrupt-controller; - interrupts = <1 9 0xf04>; - reg = <0xfff11000 0x1000>, - <0xfff12000 0x2000>, - <0xfff14000 0x2000>, - <0xfff16000 0x2000>; - }; - - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts = <0 76 4 0 75 4 0 74 4 0 73 4>; - }; - }; -}; - -/include/ "ecx-common.dtsi" diff --git a/sys/gnu/dts/arm/ecx-common.dtsi b/sys/gnu/dts/arm/ecx-common.dtsi deleted file mode 100644 index 66ee1d34f72..00000000000 --- a/sys/gnu/dts/arm/ecx-common.dtsi +++ /dev/null @@ -1,230 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright 2011-2012 Calxeda, Inc. - */ - -/ { - chosen { - bootargs = "console=ttyAMA0"; - }; - - psci { - compatible = "arm,psci"; - method = "smc"; - cpu_suspend = <0x84000002>; - cpu_off = <0x84000004>; - cpu_on = <0x84000006>; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&intc>; - - sata@ffe08000 { - compatible = "calxeda,hb-ahci"; - reg = <0xffe08000 0x10000>; - interrupts = <0 83 4>; - dma-coherent; - calxeda,port-phys = <&combophy5 0 &combophy0 0 - &combophy0 1 &combophy0 2 - &combophy0 3>; - calxeda,sgpio-gpio =<&gpioh 5 1 &gpioh 6 1 &gpioh 7 1>; - calxeda,led-order = <4 0 1 2 3>; - }; - - sdhci@ffe0e000 { - compatible = "calxeda,hb-sdhci"; - reg = <0xffe0e000 0x1000>; - interrupts = <0 90 4>; - clocks = <&eclk>; - status = "disabled"; - }; - - ipc@fff20000 { - compatible = "arm,pl320", "arm,primecell"; - reg = <0xfff20000 0x1000>; - interrupts = <0 7 4>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - gpioe: gpio@fff30000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0xfff30000 0x1000>; - interrupts = <0 14 4>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - gpiof: gpio@fff31000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0xfff31000 0x1000>; - interrupts = <0 15 4>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - gpiog: gpio@fff32000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0xfff32000 0x1000>; - interrupts = <0 16 4>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - gpioh: gpio@fff33000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0xfff33000 0x1000>; - interrupts = <0 17 4>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - timer@fff34000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0xfff34000 0x1000>; - interrupts = <0 18 4>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - rtc@fff35000 { - compatible = "arm,pl031", "arm,primecell"; - reg = <0xfff35000 0x1000>; - interrupts = <0 19 4>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - serial@fff36000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0xfff36000 0x1000>; - interrupts = <0 20 4>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - smic@fff3a000 { - compatible = "ipmi-smic"; - device_type = "ipmi"; - reg = <0xfff3a000 0x1000>; - interrupts = <0 24 4>; - reg-size = <4>; - reg-spacing = <4>; - }; - - sregs@fff3c000 { - compatible = "calxeda,hb-sregs"; - reg = <0xfff3c000 0x1000>; - - clocks { - #address-cells = <1>; - #size-cells = <0>; - - osc: oscillator { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <33333000>; - }; - - ddrpll: ddrpll { - #clock-cells = <0>; - compatible = "calxeda,hb-pll-clock"; - clocks = <&osc>; - reg = <0x108>; - }; - - a9pll: a9pll { - #clock-cells = <0>; - compatible = "calxeda,hb-pll-clock"; - clocks = <&osc>; - reg = <0x100>; - }; - - a9periphclk: a9periphclk { - #clock-cells = <0>; - compatible = "calxeda,hb-a9periph-clock"; - clocks = <&a9pll>; - reg = <0x104>; - }; - - a9bclk: a9bclk { - #clock-cells = <0>; - compatible = "calxeda,hb-a9bus-clock"; - clocks = <&a9pll>; - reg = <0x104>; - }; - - emmcpll: emmcpll { - #clock-cells = <0>; - compatible = "calxeda,hb-pll-clock"; - clocks = <&osc>; - reg = <0x10C>; - }; - - eclk: eclk { - #clock-cells = <0>; - compatible = "calxeda,hb-emmc-clock"; - clocks = <&emmcpll>; - reg = <0x114>; - }; - - pclk: pclk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <150000000>; - }; - }; - }; - - dma@fff3d000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0xfff3d000 0x1000>; - interrupts = <0 92 4>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - ethernet@fff50000 { - compatible = "calxeda,hb-xgmac"; - reg = <0xfff50000 0x1000>; - interrupts = <0 77 4 0 78 4 0 79 4>; - dma-coherent; - }; - - ethernet@fff51000 { - compatible = "calxeda,hb-xgmac"; - reg = <0xfff51000 0x1000>; - interrupts = <0 80 4 0 81 4 0 82 4>; - dma-coherent; - }; - - combophy0: combo-phy@fff58000 { - compatible = "calxeda,hb-combophy"; - #phy-cells = <1>; - reg = <0xfff58000 0x1000>; - phydev = <5>; - }; - - combophy5: combo-phy@fff5d000 { - compatible = "calxeda,hb-combophy"; - #phy-cells = <1>; - reg = <0xfff5d000 0x1000>; - phydev = <31>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/efm32gg-dk3750.dts b/sys/gnu/dts/arm/efm32gg-dk3750.dts deleted file mode 100644 index adfa559a488..00000000000 --- a/sys/gnu/dts/arm/efm32gg-dk3750.dts +++ /dev/null @@ -1,88 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device tree for EFM32GG-DK3750 development board. - * - * Documentation available from - * http://www.silabs.com/Support%20Documents/TechnicalDocs/efm32gg-dk3750-ug.pdf - */ - -/dts-v1/; -#include "efm32gg.dtsi" - -/ { - model = "Energy Micro Giant Gecko Development Kit"; - compatible = "efm32,dk3750"; - - chosen { - bootargs = "console=ttyefm4,115200 init=/linuxrc ignore_loglevel ihash_entries=64 dhash_entries=64 earlyprintk uclinux.physaddr=0x8c400000 root=/dev/mtdblock0"; - }; - - memory@88000000 { - device_type = "memory"; - reg = <0x88000000 0x400000>; - }; - - soc { - adc@40002000 { - status = "ok"; - }; - - i2c@4000a000 { - energymicro,location = <3>; - status = "ok"; - - temp@48 { - compatible = "st,stds75"; - reg = <0x48>; - }; - - eeprom@50 { - compatible = "microchip,24c02", "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; - }; - - spi0: spi@4000c000 { /* USART0 */ - cs-gpios = <&gpio 68 1>; // E4 - energymicro,location = <1>; - status = "ok"; - - microsd@0 { - compatible = "mmc-spi-slot"; - spi-max-frequency = <100000>; - voltage-ranges = <3200 3400>; - broken-cd; - reg = <0>; - }; - }; - - spi1: spi@4000c400 { /* USART1 */ - cs-gpios = <&gpio 51 1>; // D3 - energymicro,location = <1>; - status = "ok"; - - ks8851@0 { - compatible = "ks8851"; - spi-max-frequency = <6000000>; - reg = <0>; - interrupt-parent = <&boardfpga>; - interrupts = <4>; - }; - }; - - uart4: uart@4000e400 { /* UART1 */ - energymicro,location = <2>; - status = "ok"; - }; - - boardfpga: boardfpga@80000000 { - compatible = "efm32board"; - reg = <0x80000000 0x400>; - irq-gpios = <&gpio 64 1>; - interrupt-controller; - #interrupt-cells = <1>; - status = "ok"; - }; - }; -}; diff --git a/sys/gnu/dts/arm/efm32gg.dtsi b/sys/gnu/dts/arm/efm32gg.dtsi deleted file mode 100644 index 8a58e49144c..00000000000 --- a/sys/gnu/dts/arm/efm32gg.dtsi +++ /dev/null @@ -1,177 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device tree for Energy Micro EFM32 Giant Gecko SoC. - * - * Documentation available from - * http://www.silabs.com/Support%20Documents/TechnicalDocs/EFM32GG-RM.pdf - */ - -#include "armv7-m.dtsi" -#include "dt-bindings/clock/efm32-cmu.h" - -/ { - #address-cells = <1>; - #size-cells = <1>; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - serial4 = &uart4; - spi0 = &spi0; - spi1 = &spi1; - spi2 = &spi2; - }; - - soc { - adc: adc@40002000 { - compatible = "energymicro,efm32-adc"; - reg = <0x40002000 0x400>; - interrupts = <7>; - clocks = <&cmu clk_HFPERCLKADC0>; - status = "disabled"; - }; - - gpio: gpio@40006000 { - compatible = "energymicro,efm32-gpio"; - reg = <0x40006000 0x1000>; - interrupts = <1 11>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <1>; - clocks = <&cmu clk_HFPERCLKGPIO>; - status = "ok"; - }; - - i2c0: i2c@4000a000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "energymicro,efm32-i2c"; - reg = <0x4000a000 0x400>; - interrupts = <9>; - clocks = <&cmu clk_HFPERCLKI2C0>; - clock-frequency = <100000>; - status = "disabled"; - }; - - i2c1: i2c@4000a400 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "energymicro,efm32-i2c"; - reg = <0x4000a400 0x400>; - interrupts = <10>; - clocks = <&cmu clk_HFPERCLKI2C1>; - clock-frequency = <100000>; - status = "disabled"; - }; - - spi0: spi@4000c000 { /* USART0 */ - #address-cells = <1>; - #size-cells = <0>; - compatible = "energymicro,efm32-spi"; - reg = <0x4000c000 0x400>; - interrupts = <3 4>; - clocks = <&cmu clk_HFPERCLKUSART0>; - status = "disabled"; - }; - - spi1: spi@4000c400 { /* USART1 */ - #address-cells = <1>; - #size-cells = <0>; - compatible = "energymicro,efm32-spi"; - reg = <0x4000c400 0x400>; - interrupts = <15 16>; - clocks = <&cmu clk_HFPERCLKUSART1>; - status = "disabled"; - }; - - spi2: spi@4000c800 { /* USART2 */ - #address-cells = <1>; - #size-cells = <0>; - compatible = "energymicro,efm32-spi"; - reg = <0x4000c800 0x400>; - interrupts = <18 19>; - clocks = <&cmu clk_HFPERCLKUSART2>; - status = "disabled"; - }; - - uart0: uart@4000c000 { /* USART0 */ - compatible = "energymicro,efm32-uart"; - reg = <0x4000c000 0x400>; - interrupts = <3 4>; - clocks = <&cmu clk_HFPERCLKUSART0>; - status = "disabled"; - }; - - uart1: uart@4000c400 { /* USART1 */ - compatible = "energymicro,efm32-uart"; - reg = <0x4000c400 0x400>; - interrupts = <15 16>; - clocks = <&cmu clk_HFPERCLKUSART1>; - status = "disabled"; - }; - - uart2: uart@4000c800 { /* USART2 */ - compatible = "energymicro,efm32-uart"; - reg = <0x4000c800 0x400>; - interrupts = <18 19>; - clocks = <&cmu clk_HFPERCLKUSART2>; - status = "disabled"; - }; - - uart3: uart@4000e000 { /* UART0 */ - compatible = "energymicro,efm32-uart"; - reg = <0x4000e000 0x400>; - interrupts = <20 21>; - clocks = <&cmu clk_HFPERCLKUART0>; - status = "disabled"; - }; - - uart4: uart@4000e400 { /* UART1 */ - compatible = "energymicro,efm32-uart"; - reg = <0x4000e400 0x400>; - interrupts = <22 23>; - clocks = <&cmu clk_HFPERCLKUART1>; - status = "disabled"; - }; - - timer0: timer@40010000 { - compatible = "energymicro,efm32-timer"; - reg = <0x40010000 0x400>; - interrupts = <2>; - clocks = <&cmu clk_HFPERCLKTIMER0>; - }; - - timer1: timer@40010400 { - compatible = "energymicro,efm32-timer"; - reg = <0x40010400 0x400>; - interrupts = <12>; - clocks = <&cmu clk_HFPERCLKTIMER1>; - }; - - timer2: timer@40010800 { - compatible = "energymicro,efm32-timer"; - reg = <0x40010800 0x400>; - interrupts = <13>; - clocks = <&cmu clk_HFPERCLKTIMER2>; - }; - - timer3: timer@40010c00 { - compatible = "energymicro,efm32-timer"; - reg = <0x40010c00 0x400>; - interrupts = <14>; - clocks = <&cmu clk_HFPERCLKTIMER3>; - }; - - cmu: cmu@400c8000 { - compatible = "efm32gg,cmu"; - reg = <0x400c8000 0x400>; - interrupts = <32>; - #clock-cells = <1>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/elpida_ecb240abacn.dtsi b/sys/gnu/dts/arm/elpida_ecb240abacn.dtsi deleted file mode 100644 index d87ee4794f8..00000000000 --- a/sys/gnu/dts/arm/elpida_ecb240abacn.dtsi +++ /dev/null @@ -1,68 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Common devices used in different OMAP boards - */ - -/ { - elpida_ECB240ABACN: lpddr2 { - compatible = "Elpida,ECB240ABACN","jedec,lpddr2-s4"; - density = <2048>; - io-width = <32>; - - tRPab-min-tck = <3>; - tRCD-min-tck = <3>; - tWR-min-tck = <3>; - tRASmin-min-tck = <3>; - tRRD-min-tck = <2>; - tWTR-min-tck = <2>; - tXP-min-tck = <2>; - tRTP-min-tck = <2>; - tCKE-min-tck = <3>; - tCKESR-min-tck = <3>; - tFAW-min-tck = <8>; - - timings_elpida_ECB240ABACN_400mhz: lpddr2-timings@0 { - compatible = "jedec,lpddr2-timings"; - min-freq = <10000000>; - max-freq = <400000000>; - tRPab = <21000>; - tRCD = <18000>; - tWR = <15000>; - tRAS-min = <42000>; - tRRD = <10000>; - tWTR = <7500>; - tXP = <7500>; - tRTP = <7500>; - tCKESR = <15000>; - tDQSCK-max = <5500>; - tFAW = <50000>; - tZQCS = <90000>; - tZQCL = <360000>; - tZQinit = <1000000>; - tRAS-max-ns = <70000>; - tDQSCK-max-derated = <6000>; - }; - - timings_elpida_ECB240ABACN_200mhz: lpddr2-timings@1 { - compatible = "jedec,lpddr2-timings"; - min-freq = <10000000>; - max-freq = <200000000>; - tRPab = <21000>; - tRCD = <18000>; - tWR = <15000>; - tRAS-min = <42000>; - tRRD = <10000>; - tWTR = <10000>; - tXP = <7500>; - tRTP = <7500>; - tCKESR = <15000>; - tDQSCK-max = <5500>; - tFAW = <50000>; - tZQCS = <90000>; - tZQCL = <360000>; - tZQinit = <1000000>; - tRAS-max-ns = <70000>; - tDQSCK-max-derated = <6000>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/emev2-kzm9d.dts b/sys/gnu/dts/arm/emev2-kzm9d.dts deleted file mode 100644 index 0a27f034dd6..00000000000 --- a/sys/gnu/dts/arm/emev2-kzm9d.dts +++ /dev/null @@ -1,115 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the KZM9D board - * - * Copyright (C) 2013 Renesas Solutions Corp. - */ -/dts-v1/; - -#include "emev2.dtsi" -#include -#include -#include - -/ { - model = "EMEV2 KZM9D Board"; - compatible = "renesas,kzm9d", "renesas,emev2"; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x8000000>; - }; - - aliases { - serial1 = &uart1; - }; - - chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; - stdout-path = "serial1:115200n8"; - }; - - gpio_keys { - compatible = "gpio-keys"; - one { - debounce-interval = <50>; - wakeup-source; - label = "DSW2-1"; - linux,code = ; - gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; - }; - two { - debounce-interval = <50>; - wakeup-source; - label = "DSW2-2"; - linux,code = ; - gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; - }; - three { - debounce-interval = <50>; - wakeup-source; - label = "DSW2-3"; - linux,code = ; - gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; - }; - four { - debounce-interval = <50>; - wakeup-source; - label = "DSW2-4"; - linux,code = ; - gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>; - }; - }; - - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-name = "fixed-1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - ethernet@20000000 { - compatible = "smsc,lan9220", "smsc,lan9115"; - reg = <0x20000000 0x10000>; - phy-mode = "mii"; - interrupt-parent = <&gpio0>; - interrupts = <1 IRQ_TYPE_EDGE_RISING>; - reg-io-width = <4>; - smsc,irq-active-high; - smsc,irq-push-pull; - vddvario-supply = <®_1p8v>; - vdd33a-supply = <®_3p3v>; - }; -}; - -&iic0 { - status = "okay"; -}; - -&iic1 { - status = "okay"; -}; - -&pfc { - uart1_pins: uart1 { - groups = "uart1_ctrl", "uart1_data"; - function = "uart1"; - }; -}; - -&uart1 { - pinctrl-0 = <&uart1_pins>; - pinctrl-names = "default"; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/emev2.dtsi b/sys/gnu/dts/arm/emev2.dtsi deleted file mode 100644 index 96678ddbb4e..00000000000 --- a/sys/gnu/dts/arm/emev2.dtsi +++ /dev/null @@ -1,289 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the Emma Mobile EV2 SoC - * - * Copyright (C) 2012 Renesas Solutions Corp. - */ - -#include -#include - -/ { - compatible = "renesas,emev2"; - interrupt-parent = <&gic>; - #address-cells = <1>; - #size-cells = <1>; - - aliases { - gpio0 = &gpio0; - gpio1 = &gpio1; - gpio2 = &gpio2; - gpio3 = &gpio3; - gpio4 = &gpio4; - i2c0 = &iic0; - i2c1 = &iic1; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - clock-frequency = <533000000>; - }; - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <1>; - clock-frequency = <533000000>; - }; - }; - - gic: interrupt-controller@e0020000 { - compatible = "arm,pl390"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0xe0028000 0x1000>, - <0xe0020000 0x0100>; - }; - - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts = , - ; - interrupt-affinity = <&cpu0>, <&cpu1>; - }; - - clocks@e0110000 { - compatible = "renesas,emev2-smu"; - reg = <0xe0110000 0x10000>; - #address-cells = <2>; - #size-cells = <0>; - - c32ki: c32ki { - compatible = "fixed-clock"; - clock-frequency = <32768>; - #clock-cells = <0>; - }; - iic0_sclkdiv: iic0_sclkdiv@624,0 { - compatible = "renesas,emev2-smu-clkdiv"; - reg = <0x624 0>; - clocks = <&pll3_fo>; - #clock-cells = <0>; - }; - iic0_sclk: iic0_sclk@48c,1 { - compatible = "renesas,emev2-smu-gclk"; - reg = <0x48c 1>; - clocks = <&iic0_sclkdiv>; - #clock-cells = <0>; - }; - iic1_sclkdiv: iic1_sclkdiv@624,16 { - compatible = "renesas,emev2-smu-clkdiv"; - reg = <0x624 16>; - clocks = <&pll3_fo>; - #clock-cells = <0>; - }; - iic1_sclk: iic1_sclk@490,1 { - compatible = "renesas,emev2-smu-gclk"; - reg = <0x490 1>; - clocks = <&iic1_sclkdiv>; - #clock-cells = <0>; - }; - pll3_fo: pll3_fo { - compatible = "fixed-factor-clock"; - clocks = <&c32ki>; - clock-div = <1>; - clock-mult = <7000>; - #clock-cells = <0>; - }; - usia_u0_sclkdiv: usia_u0_sclkdiv@610,0 { - compatible = "renesas,emev2-smu-clkdiv"; - reg = <0x610 0>; - clocks = <&pll3_fo>; - #clock-cells = <0>; - }; - usib_u1_sclkdiv: usib_u1_sclkdiv@65c,0 { - compatible = "renesas,emev2-smu-clkdiv"; - reg = <0x65c 0>; - clocks = <&pll3_fo>; - #clock-cells = <0>; - }; - usib_u2_sclkdiv: usib_u2_sclkdiv@65c,16 { - compatible = "renesas,emev2-smu-clkdiv"; - reg = <0x65c 16>; - clocks = <&pll3_fo>; - #clock-cells = <0>; - }; - usib_u3_sclkdiv: usib_u3_sclkdiv@660,0 { - compatible = "renesas,emev2-smu-clkdiv"; - reg = <0x660 0>; - clocks = <&pll3_fo>; - #clock-cells = <0>; - }; - usia_u0_sclk: usia_u0_sclk@4a0,1 { - compatible = "renesas,emev2-smu-gclk"; - reg = <0x4a0 1>; - clocks = <&usia_u0_sclkdiv>; - #clock-cells = <0>; - }; - usib_u1_sclk: usib_u1_sclk@4b8,1 { - compatible = "renesas,emev2-smu-gclk"; - reg = <0x4b8 1>; - clocks = <&usib_u1_sclkdiv>; - #clock-cells = <0>; - }; - usib_u2_sclk: usib_u2_sclk@4bc,1 { - compatible = "renesas,emev2-smu-gclk"; - reg = <0x4bc 1>; - clocks = <&usib_u2_sclkdiv>; - #clock-cells = <0>; - }; - usib_u3_sclk: usib_u3_sclk@4c0,1 { - compatible = "renesas,emev2-smu-gclk"; - reg = <0x4c0 1>; - clocks = <&usib_u3_sclkdiv>; - #clock-cells = <0>; - }; - sti_sclk: sti_sclk@528,1 { - compatible = "renesas,emev2-smu-gclk"; - reg = <0x528 1>; - clocks = <&c32ki>; - #clock-cells = <0>; - }; - }; - - timer@e0180000 { - compatible = "renesas,em-sti"; - reg = <0xe0180000 0x54>; - interrupts = ; - clocks = <&sti_sclk>; - clock-names = "sclk"; - }; - - uart0: serial@e1020000 { - compatible = "renesas,em-uart"; - reg = <0xe1020000 0x38>; - interrupts = ; - clocks = <&usia_u0_sclk>; - clock-names = "sclk"; - }; - - uart1: serial@e1030000 { - compatible = "renesas,em-uart"; - reg = <0xe1030000 0x38>; - interrupts = ; - clocks = <&usib_u1_sclk>; - clock-names = "sclk"; - }; - - uart2: serial@e1040000 { - compatible = "renesas,em-uart"; - reg = <0xe1040000 0x38>; - interrupts = ; - clocks = <&usib_u2_sclk>; - clock-names = "sclk"; - }; - - uart3: serial@e1050000 { - compatible = "renesas,em-uart"; - reg = <0xe1050000 0x38>; - interrupts = ; - clocks = <&usib_u3_sclk>; - clock-names = "sclk"; - }; - - pfc: pin-controller@e0140200 { - compatible = "renesas,pfc-emev2"; - reg = <0xe0140200 0x100>; - }; - - gpio0: gpio@e0050000 { - compatible = "renesas,em-gio"; - reg = <0xe0050000 0x2c>, <0xe0050040 0x20>; - interrupts = , - ; - gpio-controller; - gpio-ranges = <&pfc 0 0 32>; - #gpio-cells = <2>; - ngpios = <32>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio@e0050080 { - compatible = "renesas,em-gio"; - reg = <0xe0050080 0x2c>, <0xe00500c0 0x20>; - interrupts = , - ; - gpio-controller; - gpio-ranges = <&pfc 0 32 32>; - #gpio-cells = <2>; - ngpios = <32>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@e0050100 { - compatible = "renesas,em-gio"; - reg = <0xe0050100 0x2c>, <0xe0050140 0x20>; - interrupts = , - ; - gpio-controller; - gpio-ranges = <&pfc 0 64 32>; - #gpio-cells = <2>; - ngpios = <32>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio@e0050180 { - compatible = "renesas,em-gio"; - reg = <0xe0050180 0x2c>, <0xe00501c0 0x20>; - interrupts = , - ; - gpio-controller; - gpio-ranges = <&pfc 0 96 32>; - #gpio-cells = <2>; - ngpios = <32>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio4: gpio@e0050200 { - compatible = "renesas,em-gio"; - reg = <0xe0050200 0x2c>, <0xe0050240 0x20>; - interrupts = , - ; - gpio-controller; - gpio-ranges = <&pfc 0 128 31>; - #gpio-cells = <2>; - ngpios = <31>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - iic0: i2c@e0070000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-emev2"; - reg = <0xe0070000 0x28>; - interrupts = ; - clocks = <&iic0_sclk>; - clock-names = "sclk"; - status = "disabled"; - }; - - iic1: i2c@e10a0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-emev2"; - reg = <0xe10a0000 0x28>; - interrupts = ; - clocks = <&iic1_sclk>; - clock-names = "sclk"; - status = "disabled"; - }; -}; diff --git a/sys/gnu/dts/arm/ep7209.dtsi b/sys/gnu/dts/arm/ep7209.dtsi deleted file mode 100644 index 365931f8b48..00000000000 --- a/sys/gnu/dts/arm/ep7209.dtsi +++ /dev/null @@ -1,187 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later - -/dts-v1/; - -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - model = "Cirrus Logic EP7209"; - compatible = "cirrus,ep7209"; - - aliases { - gpio0 = &porta; - gpio1 = &portb; - gpio3 = &portd; - gpio4 = &porte; - serial0 = &uart1; - serial1 = &uart2; - spi0 = &spi; - timer0 = &timer1; - timer1 = &timer2; - }; - - cpus { - #address-cells = <0>; - #size-cells = <0>; - - cpu { - device_type = "cpu"; - compatible = "arm,arm720t"; - }; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&intc>; - ranges; - - clks: clks@80000000 { - #clock-cells = <1>; - compatible = "cirrus,ep7209-clk"; - reg = <0x80000000 0xc000>; - startup-frequency = <73728000>; - }; - - intc: intc@80000000 { - compatible = "cirrus,ep7209-intc"; - reg = <0x80000000 0x4000>; - interrupt-controller; - #interrupt-cells = <1>; - }; - - porta: gpio@80000000 { - compatible = "cirrus,ep7209-gpio"; - reg = <0x80000000 0x1 0x80000040 0x1>; - gpio-controller; - #gpio-cells = <2>; - }; - - portb: gpio@80000001 { - compatible = "cirrus,ep7209-gpio"; - reg = <0x80000001 0x1 0x80000041 0x1>; - gpio-controller; - #gpio-cells = <2>; - }; - - portd: gpio@80000003 { - compatible = "cirrus,ep7209-gpio"; - reg = <0x80000003 0x1 0x80000043 0x1>; - gpio-controller; - #gpio-cells = <2>; - }; - - porte: gpio@80000083 { - compatible = "cirrus,ep7209-gpio"; - reg = <0x80000083 0x1 0x800000c3 0x1>; - gpio-controller; - #gpio-cells = <2>; - }; - - syscon1: syscon@80000100 { - compatible = "cirrus,ep7209-syscon1", "syscon"; - reg = <0x80000100 0x80>; - }; - - bus: bus@80000180 { - #address-cells = <2>; - #size-cells = <1>; - compatible = "cirrus,ep7209-bus", "simple-bus"; - clocks = <&clks CLPS711X_CLK_BUS>; - reg = <0x80000180 0x80>; - ranges = < - 0 0 0x00000000 0x10000000 - 1 0 0x10000000 0x10000000 - 2 0 0x20000000 0x10000000 - 3 0 0x30000000 0x10000000 - 4 0 0x40000000 0x10000000 - 5 0 0x50000000 0x10000000 - 6 0 0x60000000 0x0000c000 - 7 0 0x70000000 0x00000080 - >; - }; - - fb: fb@800002c0 { - compatible = "cirrus,ep7209-fb"; - reg = <0x800002c0 0xd44>, <0x60000000 0xc000>; - clocks = <&clks CLPS711X_CLK_BUS>; - status = "disabled"; - }; - - timer1: timer@80000300 { - compatible = "cirrus,ep7209-timer"; - reg = <0x80000300 0x4>; - clocks = <&clks CLPS711X_CLK_TIMER1>; - interrupts = <8>; - }; - - timer2: timer@80000340 { - compatible = "cirrus,ep7209-timer"; - reg = <0x80000340 0x4>; - clocks = <&clks CLPS711X_CLK_TIMER2>; - interrupts = <9>; - }; - - pwm: pwm@80000400 { - compatible = "cirrus,ep7209-pwm"; - reg = <0x80000400 0x4>; - clocks = <&clks CLPS711X_CLK_PWM>; - #pwm-cells = <1>; - }; - - uart1: uart@80000480 { - compatible = "cirrus,ep7209-uart"; - reg = <0x80000480 0x80>; - interrupts = <12 13>; - clocks = <&clks CLPS711X_CLK_UART>; - syscon = <&syscon1>; - }; - - spi: spi@80000500 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "cirrus,ep7209-spi"; - reg = <0x80000500 0x4>; - interrupts = <15>; - clocks = <&clks CLPS711X_CLK_SPI>; - status = "disabled"; - }; - - syscon2: syscon@80001100 { - compatible = "cirrus,ep7209-syscon2", "syscon"; - reg = <0x80001100 0x80>; - }; - - uart2: uart@80001480 { - compatible = "cirrus,ep7209-uart"; - reg = <0x80001480 0x80>; - interrupts = <28 29>; - clocks = <&clks CLPS711X_CLK_UART>; - syscon = <&syscon2>; - }; - - dai: dai@80002000 { - #sound-dai-cells = <0>; - compatible = "cirrus,ep7209-dai"; - reg = <0x80002000 0x604>; - clocks = <&clks CLPS711X_CLK_PLL>; - clock-names = "pll"; - interrupts = <32>; - status = "disabled"; - }; - - syscon3: syscon@80002200 { - compatible = "cirrus,ep7209-syscon3", "syscon"; - reg = <0x80002200 0x40>; - }; - }; - - mctrl: mctrl { - compatible = "cirrus,ep7209-mctrl-gpio"; - gpio-controller; - #gpio-cells = <2>; - }; -}; diff --git a/sys/gnu/dts/arm/ep7211-edb7211.dts b/sys/gnu/dts/arm/ep7211-edb7211.dts deleted file mode 100644 index da076479c8e..00000000000 --- a/sys/gnu/dts/arm/ep7211-edb7211.dts +++ /dev/null @@ -1,97 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later - -#include "ep7211.dtsi" -#include - -/ { - model = "Cirrus Logic EP7211 Development Board"; - compatible = "cirrus,edb7211", "cirrus,ep7211", "cirrus,ep7209"; - - memory { - device_type = "memory"; - reg = <0xc0000000 0x02000000>; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 0>; - brightness-levels = < - 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 - 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf - >; - default-brightness-level = <0x0>; - power-supply = <&blen>; - }; - - display: display { - model = "320x240x4"; - bits-per-pixel = <4>; - ac-prescale = <17>; - - display-timings { - native-mode = <&timing0>; - timing0: 320x240 { - hactive = <320>; - hback-porch = <0>; - hfront-porch = <0>; - hsync-len = <0>; - vactive = <240>; - vback-porch = <0>; - vfront-porch = <0>; - vsync-len = <0>; - clock-frequency = <6500000>; - }; - }; - }; - - i2c: i2c { - compatible = "i2c-gpio"; - gpios = <&portd 4 GPIO_ACTIVE_HIGH>, - <&portd 5 GPIO_ACTIVE_HIGH>; - i2c-gpio,delay-us = <2>; - i2c-gpio,scl-output-only; - #address-cells = <1>; - #size-cells = <0>; - }; - - lcddc: lcddc { - compatible = "regulator-fixed"; - regulator-name = "BACKLIGHT ENABLE"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&portd 1 GPIO_ACTIVE_HIGH>; - }; - - blen: blen { - compatible = "regulator-fixed"; - regulator-name = "BACKLIGHT ENABLE"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&portd 3 GPIO_ACTIVE_HIGH>; - }; -}; - -&bus { - flash: nor@0 { - compatible = "cfi-flash"; - reg = <0 0x00000000 0x02000000>; - bank-width = <2>; - #address-cells = <1>; - #size-cells = <1>; - }; -}; - -&fb { - display = <&display>; - lcd-supply = <&lcddc>; - status = "okay"; -}; - -&portd { - lcden { - gpio-hog; - gpios = <2 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "LCD ENABLE"; - }; -}; diff --git a/sys/gnu/dts/arm/ep7211.dtsi b/sys/gnu/dts/arm/ep7211.dtsi deleted file mode 100644 index 32a4e123714..00000000000 --- a/sys/gnu/dts/arm/ep7211.dtsi +++ /dev/null @@ -1,8 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later - -#include "ep7209.dtsi" - -/ { - model = "Cirrus Logic EP7211"; - compatible = "cirrus,ep7211", "cirrus,ep7209"; -}; diff --git a/sys/gnu/dts/arm/ethernut5.dts b/sys/gnu/dts/arm/ethernut5.dts deleted file mode 100644 index 052a52f947c..00000000000 --- a/sys/gnu/dts/arm/ethernut5.dts +++ /dev/null @@ -1,118 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * ethernut5.dts - Device Tree file for Ethernut 5 board - * - * Copyright (C) 2012 egnite GmbH - */ -/dts-v1/; -#include "at91sam9xe.dtsi" - -/ { - model = "Ethernut 5"; - compatible = "egnite,ethernut5", "atmel,at91sam9260", "atmel,at91sam9"; - - chosen { - bootargs = "console=ttyS0,115200 root=/dev/mtdblock0 rw rootfstype=jffs2"; - }; - - memory { - reg = <0x20000000 0x08000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <18432000>; - }; - }; - - ahb { - apb { - dbgu: serial@fffff200 { - status = "okay"; - }; - - tcb0: timer@fffa0000 { - timer@0 { - compatible = "atmel,tcb-timer"; - reg = <0>, <1>; - }; - - timer@2 { - compatible = "atmel,tcb-timer"; - reg = <2>; - }; - }; - - usart0: serial@fffb0000 { - status = "okay"; - }; - - usart1: serial@fffb4000 { - status = "okay"; - }; - - macb0: ethernet@fffc4000 { - phy-mode = "rmii"; - status = "okay"; - }; - - usb1: gadget@fffa4000 { - atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - }; - - ebi: ebi@10000000 { - status = "okay"; - - nand_controller: nand-controller { - status = "okay"; - pinctrl-0 = <&pinctrl_nand_cs>; - pinctrl-names = "default"; - - nand: nand@3 { - reg = <0x3 0x0 0x800000>; - cs-gpios = <&pioC 14 GPIO_ACTIVE_HIGH>; - nand-bus-width = <8>; - nand-ecc-mode = "soft"; - nand-on-flash-bbt; - label = "atmel_nand"; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - root@0 { - label = "root"; - reg = <0x0 0x08000000>; - }; - - data@20000 { - label = "data"; - reg = <0x08000000 0x38000000>; - }; - }; - }; - }; - }; - - usb0: ohci@500000 { - num-ports = <2>; - status = "okay"; - }; - }; - - i2c-gpio-0 { - status = "okay"; - - pcf8563@50 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/evk-pro3.dts b/sys/gnu/dts/arm/evk-pro3.dts deleted file mode 100644 index 6d519d02d19..00000000000 --- a/sys/gnu/dts/arm/evk-pro3.dts +++ /dev/null @@ -1,58 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * evk-pro3.dts - Device Tree file for Telit EVK-PRO3 with Telit GE863-PRO3 - * - * Copyright (C) 2012 Telit, - * 2012 Fabio Porcedda - */ - -/dts-v1/; - -#include "ge863-pro3.dtsi" - -/ { - model = "Telit EVK-PRO3 for Telit GE863-PRO3"; - compatible = "telit,evk-pro3", "atmel,at91sam9260", "atmel,at91sam9"; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - }; - - ahb { - apb { - macb0: ethernet@fffc4000 { - phy-mode = "rmii"; - status = "okay"; - }; - - usart0: serial@fffb0000 { - status = "okay"; - }; - - usart2: serial@fffb8000 { - status = "okay"; - }; - - usb1: gadget@fffa4000 { - atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - watchdog@fffffd40 { - status = "okay"; - }; - }; - - usb0: ohci@500000 { - num-ports = <2>; - status = "okay"; - }; - }; - - i2c-gpio-0 { - status = "okay"; - }; - -}; diff --git a/sys/gnu/dts/arm/exynos-mfc-reserved-memory.dtsi b/sys/gnu/dts/arm/exynos-mfc-reserved-memory.dtsi deleted file mode 100644 index 1dbf3bbff8d..00000000000 --- a/sys/gnu/dts/arm/exynos-mfc-reserved-memory.dtsi +++ /dev/null @@ -1,32 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's Exynos SoC MFC (Video Codec) reserved memory common definition. - * - * Copyright (c) 2016 Samsung Electronics Co., Ltd - */ - -/ { - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - mfc_left: region_mfc_left { - compatible = "shared-dma-pool"; - no-map; - size = <0x2400000>; - alignment = <0x100000>; - }; - - mfc_right: region_mfc_right { - compatible = "shared-dma-pool"; - no-map; - size = <0x800000>; - alignment = <0x100000>; - }; - }; -}; - -&mfc { - memory-region = <&mfc_left>, <&mfc_right>; -}; diff --git a/sys/gnu/dts/arm/exynos-syscon-restart.dtsi b/sys/gnu/dts/arm/exynos-syscon-restart.dtsi deleted file mode 100644 index ecf416690a1..00000000000 --- a/sys/gnu/dts/arm/exynos-syscon-restart.dtsi +++ /dev/null @@ -1,20 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's Exynos SoC syscon reboot/poweroff nodes common definition. - */ - -&pmu_system_controller { - poweroff: syscon-poweroff { - compatible = "syscon-poweroff"; - regmap = <&pmu_system_controller>; - offset = <0x330C>; /* PS_HOLD_CONTROL */ - mask = <0x5200>; /* reset value */ - }; - - reboot: syscon-reboot { - compatible = "syscon-reboot"; - regmap = <&pmu_system_controller>; - offset = <0x0400>; /* SWRESET */ - mask = <0x1>; - }; -}; diff --git a/sys/gnu/dts/arm/exynos3250-artik5-eval.dts b/sys/gnu/dts/arm/exynos3250-artik5-eval.dts deleted file mode 100644 index 20446a846a9..00000000000 --- a/sys/gnu/dts/arm/exynos3250-artik5-eval.dts +++ /dev/null @@ -1,39 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's Exynos3250 based ARTIK5 evaluation board device tree source - * - * Copyright (c) 2016 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Device tree source file for Samsung's ARTIK5 evaluation board - * which is based on Samsung Exynos3250 SoC. - */ - -/dts-v1/; -#include "exynos3250-artik5.dtsi" - -/ { - model = "Samsung ARTIK5 evaluation board"; - compatible = "samsung,artik5-eval", "samsung,artik5", - "samsung,exynos3250", "samsung,exynos3"; -}; - -&mshc_2 { - cap-sd-highspeed; - disable-wp; - vqmmc-supply = <&ldo3_reg>; - card-detect-delay = <200>; - clock-frequency = <100000000>; - max-frequency = <100000000>; - samsung,dw-mshc-ciu-div = <1>; - samsung,dw-mshc-sdr-timing = <0 1>; - samsung,dw-mshc-ddr-timing = <1 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd2_cmd &sd2_clk &sd2_cd &sd2_bus1 &sd2_bus4>; - bus-width = <4>; - status = "okay"; -}; - -&serial_2 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/exynos3250-artik5.dtsi b/sys/gnu/dts/arm/exynos3250-artik5.dtsi deleted file mode 100644 index dee35e3a5c4..00000000000 --- a/sys/gnu/dts/arm/exynos3250-artik5.dtsi +++ /dev/null @@ -1,381 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's Exynos3250 based ARTIK5 module device tree source - * - * Copyright (c) 2016 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Device tree source file for Samsung's ARTIK5 module which is based on - * Samsung Exynos3250 SoC. - */ - -#include "exynos3250.dtsi" -#include -#include -#include - -/ { - compatible = "samsung,artik5", "samsung,exynos3250", "samsung,exynos3"; - - chosen { - stdout-path = &serial_2; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x1ff00000>; - }; - - firmware@205f000 { - compatible = "samsung,secure-firmware"; - reg = <0x0205f000 0x1000>; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - cooling-maps { - map0 { - /* Corresponds to 500MHz */ - cooling-device = <&cpu0 5 5>, - <&cpu1 5 5>; - }; - map1 { - /* Corresponds to 200MHz */ - cooling-device = <&cpu0 8 8>, - <&cpu1 8 8>; - }; - }; - }; - }; -}; - -&adc { - vdd-supply = <&ldo7_reg>; - assigned-clocks = <&cmu CLK_SCLK_TSADC>; - assigned-clock-rates = <6000000>; -}; - -&cpu0 { - cpu0-supply = <&buck2_reg>; -}; - -&gpu { - mali-supply = <&buck3_reg>; - status = "okay"; -}; - -&i2c_0 { - #address-cells = <1>; - #size-cells = <0>; - samsung,i2c-sda-delay = <100>; - samsung,i2c-slave-addr = <0x10>; - samsung,i2c-max-bus-freq = <100000>; - status = "okay"; - - s2mps14_pmic@66 { - compatible = "samsung,s2mps14-pmic"; - interrupt-parent = <&gpx3>; - interrupts = <5 IRQ_TYPE_NONE>; - pinctrl-names = "default"; - pinctrl-0 = <&s2mps14_irq>; - reg = <0x66>; - - s2mps14_osc: clocks { - compatible = "samsung,s2mps14-clk"; - #clock-cells = <1>; - clock-output-names = "s2mps14_ap", "unused", - "s2mps14_bt"; - }; - - regulators { - ldo1_reg: LDO1 { - /* VDD_ALIVE15x */ - regulator-name = "VLDO1_1.0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo2_reg: LDO2 { - /* VDDQM176 ~ VDDQM185 */ - regulator-name = "VLDO2_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - ldo3_reg: LDO3 { - /* - * VDD1_E106 ~ VDD1_E111 - * DVDD_RTC_AP, DVDD_MMC2_AP - */ - regulator-name = "VLDO3_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo4_reg: LDO4 { - /* AVDD_PLL1120 ~ AVDD_PLL11201 */ - regulator-name = "VLDO4_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo5_reg: LDO5 { - /* VDDI_PLL_ISO141 ~ VDDI_PLL_ISO142 */ - regulator-name = "VLDO5_1.0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo6_reg: LDO6 { - /* VDD_USB, VDD10_HSIC */ - regulator-name = "VLDO6_1.0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo7_reg: LDO7 { - /* - * VDD18P, AVDD18_TS, AVDD18_HSIC, AVDD_PLL2, - * AVDD_ADC, AVDD_ABB_0, M4S_VDD18 - */ - regulator-name = "VLDO7_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo8_reg: LDO8 { - /* AVDD33_UOTG */ - regulator-name = "VLDO8_3.0V"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - }; - - ldo9_reg: LDO9 { - /* VDDQ_E86 ~ VDDQ_E105*/ - regulator-name = "VLDO9_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - ldo10_reg: LDO10 { - regulator-name = "VLDO10_1.0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - }; - - ldo11_reg: LDO11 { - /* VDD74 ~ VDD75 */ - regulator-name = "VLDO11_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - samsung,ext-control-gpios = <&gpk0 2 GPIO_ACTIVE_HIGH>; - }; - - ldo12_reg: LDO12 { - /* VDD72 ~ VDD73 */ - regulator-name = "VLDO12_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - samsung,ext-control-gpios = <&gpk0 2 GPIO_ACTIVE_HIGH>; - }; - - ldo13_reg: LDO13 { - regulator-name = "VLDO13_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo14_reg: LDO14 { - regulator-name = "VLDO14_2.7V"; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; - - ldo15_reg: LDO15 { - regulator-name = "VLDO_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo16_reg: LDO16 { - regulator-name = "VLDO16_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo17_reg: LDO17 { - regulator-name = "VLDO17_3.0V"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - ldo18_reg: LDO18 { - /* DVDD_MMC2_AP */ - regulator-name = "VLDO18_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo19_reg: LDO19 { - regulator-name = "VLDO19_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo20_reg: LDO20 { - regulator-name = "VLDO20_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo21_reg: LDO21 { - regulator-name = "VLDO21_1.25V"; - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1250000>; - }; - - ldo22_reg: LDO22 { - regulator-name = "VLDO22_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - ldo23_reg: LDO23 { - /* Xi2c3_SDA/SCL, Xi2c7_SDA/SCL, WLAN_SDIO */ - regulator-name = "VLDO23_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo24_reg: LDO24 { - regulator-name = "VLDO24_3.0V"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - ldo25_reg: LDO25 { - regulator-name = "VLDO25_3.0V"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - buck1_reg: BUCK1 { - /* VDD_MIF */ - regulator-name = "VBUCK1_1.0V"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - buck2_reg: BUCK2 { - /* VDD_CPU */ - regulator-name = "VBUCK2_1.2V"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - buck3_reg: BUCK3 { - /* VDD_G3D */ - regulator-name = "VBUCK3_1.0V"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - buck4_reg: BUCK4 { - regulator-name = "VBUCK4_1.95V"; - regulator-min-microvolt = <1950000>; - regulator-max-microvolt = <1950000>; - regulator-always-on; - }; - - buck5_reg: BUCK5 { - regulator-name = "VBUCK5_1.35V"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - }; - }; - }; -}; - -&mshc_0 { - non-removable; - cap-mmc-highspeed; - card-detect-delay = <200>; - vmmc-supply = <&ldo12_reg>; - clock-frequency = <100000000>; - max-frequency = <100000000>; - samsung,dw-mshc-ciu-div = <1>; - samsung,dw-mshc-sdr-timing = <0 1>; - samsung,dw-mshc-ddr-timing = <1 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>; - bus-width = <8>; - status = "okay"; -}; - -&mshc_1 { - cap-sd-highspeed; - cap-sdio-irq; - disable-wp; - non-removable; - keep-power-in-suspend; - fifo-depth = <0x40>; - vqmmc-supply = <&ldo11_reg>; - /* - * Voltage negotiation is broken for the SDIO periph so we - * can't actually set the voltage here. - * vmmc-supply = <&ldo23_reg>; - */ - card-detect-delay = <500>; - clock-frequency = <100000000>; - max-frequency = <100000000>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <0 1>; - samsung,dw-mshc-ddr-timing = <1 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd1_cmd &sd1_clk &sd1_bus1 &sd1_bus4 &wlanen>; - bus-width = <4>; - status = "okay"; -}; - -&pinctrl_1 { - wlanen: wlanen { - samsung,pins = "gpx2-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - samsung,pin-val = <1>; - }; - - s2mps14_irq: s2mps14-irq { - samsung,pins = "gpx3-5"; - samsung,pin-pud = ; - }; -}; - -&rtc { - clocks = <&cmu CLK_RTC>, <&s2mps14_osc S2MPS11_CLK_AP>; - clock-names = "rtc", "rtc_src"; - status = "okay"; -}; - -&tmu { - status = "okay"; -}; - -&xusbxti { - clock-frequency = <24000000>; -}; diff --git a/sys/gnu/dts/arm/exynos3250-monk.dts b/sys/gnu/dts/arm/exynos3250-monk.dts deleted file mode 100644 index 248bd372fe7..00000000000 --- a/sys/gnu/dts/arm/exynos3250-monk.dts +++ /dev/null @@ -1,638 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's Exynos3250 based Monk board device tree source - * - * Copyright (c) 2014 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Device tree source file for Samsung's Monk board which is based on - * Samsung Exynos3250 SoC. - */ - -/dts-v1/; -#include "exynos3250.dtsi" -#include "exynos4412-ppmu-common.dtsi" -#include -#include -#include - -/ { - model = "Samsung Monk board"; - compatible = "samsung,monk", "samsung,exynos3250", "samsung,exynos3"; - - aliases { - i2c7 = &i2c_max77836; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x1ff00000>; - }; - - firmware@205f000 { - compatible = "samsung,secure-firmware"; - reg = <0x0205F000 0x1000>; - }; - - gpio_keys { - compatible = "gpio-keys"; - - power_key { - gpios = <&gpx2 7 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "power key"; - debounce-interval = <10>; - wakeup-source; - }; - }; - - vemmc_reg: voltage-regulator-0 { - compatible = "regulator-fixed"; - regulator-name = "V_EMMC_2.8V-fixed"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpk0 2 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - i2c_max77836: i2c-gpio-0 { - compatible = "i2c-gpio"; - gpios = <&gpd0 2 GPIO_ACTIVE_HIGH>, <&gpd0 3 GPIO_ACTIVE_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - - max77836: subpmic@25 { - compatible = "maxim,max77836"; - interrupt-parent = <&gpx1>; - interrupts = <5 IRQ_TYPE_NONE>; - reg = <0x25>; - wakeup-source; - - muic: max77836-muic { - compatible = "maxim,max77836-muic"; - }; - - regulators { - compatible = "maxim,max77836-regulator"; - safeout_reg: SAFEOUT { - regulator-name = "SAFEOUT"; - }; - - charger_reg: CHARGER { - regulator-name = "CHARGER"; - regulator-min-microamp = <45000>; - regulator-max-microamp = <475000>; - regulator-boot-on; - }; - - motor_reg: LDO1 { - regulator-name = "MOT_2.7V"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <2700000>; - }; - - LDO2 { - regulator-name = "UNUSED_LDO2"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3950000>; - }; - }; - - charger { - compatible = "maxim,max77836-charger"; - - maxim,constant-uvolt = <4350000>; - maxim,fast-charge-uamp = <225000>; - maxim,eoc-uamp = <7500>; - maxim,ovp-uvolt = <6500000>; - }; - }; - }; - - haptics { - compatible = "regulator-haptic"; - haptic-supply = <&motor_reg>; - min-microvolt = <1100000>; - max-microvolt = <2700000>; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - cooling-maps { - map0 { - /* Correspond to 500MHz at freq_table */ - cooling-device = <&cpu0 5 5>, - <&cpu1 5 5>; - }; - map1 { - /* Correspond to 200MHz at freq_table */ - cooling-device = <&cpu0 8 8>, - <&cpu1 8 8>; - }; - }; - }; - }; -}; - -&adc { - vdd-supply = <&ldo3_reg>; - status = "okay"; - assigned-clocks = <&cmu CLK_SCLK_TSADC>; - assigned-clock-rates = <6000000>; - - thermistor-ap { - compatible = "ntc,ncp15wb473"; - pullup-uv = <1800000>; - pullup-ohm = <100000>; - pulldown-ohm = <100000>; - io-channels = <&adc 0>; - }; - - thermistor-battery { - compatible = "ntc,ncp15wb473"; - pullup-uv = <1800000>; - pullup-ohm = <100000>; - pulldown-ohm = <100000>; - io-channels = <&adc 1>; - }; -}; - -&bus_dmc { - devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>; - vdd-supply = <&buck1_reg>; - status = "okay"; -}; - -&cpu0 { - cpu0-supply = <&buck2_reg>; -}; - -&exynos_usbphy { - vbus-supply = <&safeout_reg>; - status = "okay"; -}; - -&gpu { - mali-supply = <&buck3_reg>; - status = "okay"; -}; - -&hsotg { - vusb_d-supply = <&ldo15_reg>; - vusb_a-supply = <&ldo12_reg>; - dr_mode = "peripheral"; - status = "okay"; -}; - -&i2c_0 { - #address-cells = <1>; - #size-cells = <0>; - samsung,i2c-sda-delay = <100>; - samsung,i2c-slave-addr = <0x10>; - samsung,i2c-max-bus-freq = <100000>; - status = "okay"; - - s2mps14_pmic@66 { - compatible = "samsung,s2mps14-pmic"; - interrupt-parent = <&gpx0>; - interrupts = <7 IRQ_TYPE_NONE>; - reg = <0x66>; - wakeup-source; - - s2mps14_osc: clocks { - compatible = "samsung,s2mps14-clk"; - #clock-cells = <1>; - clock-output-names = "s2mps14_ap", "unused", - "s2mps14_bt"; - }; - - regulators { - ldo1_reg: LDO1 { - regulator-name = "VAP_ALIVE_1.0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo2_reg: LDO2 { - regulator-name = "VAP_M1_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - ldo3_reg: LDO3 { - regulator-name = "VCC_AP_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo4_reg: LDO4 { - regulator-name = "VAP_AVDD_PLL1"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo5_reg: LDO5 { - regulator-name = "VAP_PLL_ISO_1.0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo6_reg: LDO6 { - regulator-name = "VAP_MIPI_1.0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - }; - - ldo7_reg: LDO7 { - regulator-name = "VAP_AVDD_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo8_reg: LDO8 { - regulator-name = "VAP_USB_3.0V"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - }; - - ldo9_reg: LDO9 { - regulator-name = "V_LPDDR_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - ldo10_reg: LDO10 { - regulator-name = "UNUSED_LDO10"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - }; - - ldo11_reg: LDO11 { - regulator-name = "V_EMMC_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - samsung,ext-control-gpios = <&gpk0 2 GPIO_ACTIVE_HIGH>; - }; - - ldo12_reg: LDO12 { - regulator-name = "V_EMMC_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - samsung,ext-control-gpios = <&gpk0 2 GPIO_ACTIVE_HIGH>; - }; - - ldo13_reg: LDO13 { - regulator-name = "VSENSOR_2.85V"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - regulator-always-on; - }; - - ldo14_reg: LDO14 { - regulator-name = "UNUSED_LDO14"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo15_reg: LDO15 { - regulator-name = "TSP_AVDD_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo16_reg: LDO16 { - regulator-name = "LCD_VDD_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo17_reg: LDO17 { - regulator-name = "UNUSED_LDO17"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo18_reg: LDO18 { - regulator-name = "UNUSED_LDO18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo19_reg: LDO19 { - regulator-name = "TSP_VDD_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo20_reg: LDO20 { - regulator-name = "LCD_VDD_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo21_reg: LDO21 { - regulator-name = "UNUSED_LDO21"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - }; - - ldo22_reg: LDO22 { - regulator-name = "UNUSED_LDO22"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - }; - - ldo23_reg: LDO23 { - regulator-name = "UNUSED_LDO23"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo24_reg: LDO24 { - regulator-name = "UNUSED_LDO24"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo25_reg: LDO25 { - regulator-name = "UNUSED_LDO25"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - buck1_reg: BUCK1 { - regulator-name = "VAP_MIF_1.0V"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <900000>; - regulator-always-on; - }; - - buck2_reg: BUCK2 { - regulator-name = "VAP_ARM_1.0V"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1150000>; - regulator-always-on; - }; - - buck3_reg: BUCK3 { - regulator-name = "VAP_INT3D_1.0V"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - buck4_reg: BUCK4 { - regulator-name = "VCC_SUB_1.95V"; - regulator-min-microvolt = <1950000>; - regulator-max-microvolt = <1950000>; - regulator-always-on; - }; - - buck5_reg: BUCK5 { - regulator-name = "VCC_SUB_1.35V"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - }; - }; - }; -}; - -&i2c_1 { - #address-cells = <1>; - #size-cells = <0>; - samsung,i2c-sda-delay = <100>; - samsung,i2c-slave-addr = <0x10>; - samsung,i2c-max-bus-freq = <400000>; - status = "okay"; - - fuelgauge@36 { - compatible = "maxim,max77836-battery"; - interrupt-parent = <&gpx1>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - reg = <0x36>; - }; -}; - -&i2s2 { - status = "okay"; -}; - -&mshc_0 { - #address-cells = <1>; - #size-cells = <0>; - broken-cd; - non-removable; - cap-mmc-highspeed; - desc-num = <4>; - mmc-hs200-1_8v; - card-detect-delay = <200>; - vmmc-supply = <&vemmc_reg>; - clock-frequency = <100000000>; - max-frequency = <100000000>; - samsung,dw-mshc-ciu-div = <1>; - samsung,dw-mshc-sdr-timing = <0 1>; - samsung,dw-mshc-ddr-timing = <1 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>; - bus-width = <8>; - status = "okay"; -}; - -&serial_0 { - assigned-clocks = <&cmu CLK_SCLK_UART0>; - assigned-clock-rates = <100000000>; - status = "okay"; -}; - -&serial_1 { - status = "okay"; -}; - -&tmu { - vtmu-supply = <&ldo7_reg>; - status = "okay"; -}; - -&rtc { - clocks = <&cmu CLK_RTC>, <&s2mps14_osc S2MPS11_CLK_AP>; - clock-names = "rtc", "rtc_src"; - status = "okay"; -}; - -&xusbxti { - clock-frequency = <24000000>; -}; - -&pinctrl_0 { - pinctrl-names = "default"; - pinctrl-0 = <&sleep0>; - - sleep0: sleep-state { - PIN_SLP(gpa0-0, INPUT, DOWN); - PIN_SLP(gpa0-1, INPUT, DOWN); - PIN_SLP(gpa0-2, INPUT, DOWN); - PIN_SLP(gpa0-3, INPUT, DOWN); - PIN_SLP(gpa0-4, INPUT, DOWN); - PIN_SLP(gpa0-5, INPUT, DOWN); - PIN_SLP(gpa0-6, INPUT, DOWN); - PIN_SLP(gpa0-7, INPUT, DOWN); - - PIN_SLP(gpa1-0, INPUT, DOWN); - PIN_SLP(gpa1-1, INPUT, DOWN); - PIN_SLP(gpa1-2, INPUT, DOWN); - PIN_SLP(gpa1-3, INPUT, DOWN); - PIN_SLP(gpa1-4, INPUT, DOWN); - PIN_SLP(gpa1-5, INPUT, DOWN); - - PIN_SLP(gpb-0, PREV, NONE); - PIN_SLP(gpb-1, PREV, NONE); - PIN_SLP(gpb-2, PREV, NONE); - PIN_SLP(gpb-3, PREV, NONE); - PIN_SLP(gpb-4, INPUT, DOWN); - PIN_SLP(gpb-5, INPUT, DOWN); - PIN_SLP(gpb-6, INPUT, DOWN); - PIN_SLP(gpb-7, INPUT, DOWN); - - PIN_SLP(gpc0-0, INPUT, DOWN); - PIN_SLP(gpc0-1, INPUT, DOWN); - PIN_SLP(gpc0-2, INPUT, DOWN); - PIN_SLP(gpc0-3, INPUT, DOWN); - PIN_SLP(gpc0-4, INPUT, DOWN); - - PIN_SLP(gpc1-0, INPUT, DOWN); - PIN_SLP(gpc1-1, INPUT, DOWN); - PIN_SLP(gpc1-2, INPUT, DOWN); - PIN_SLP(gpc1-3, INPUT, DOWN); - PIN_SLP(gpc1-4, INPUT, DOWN); - - PIN_SLP(gpd0-0, INPUT, DOWN); - PIN_SLP(gpd0-1, INPUT, DOWN); - PIN_SLP(gpd0-2, INPUT, NONE); - PIN_SLP(gpd0-3, INPUT, NONE); - - PIN_SLP(gpd1-0, INPUT, NONE); - PIN_SLP(gpd1-1, INPUT, NONE); - PIN_SLP(gpd1-2, INPUT, NONE); - PIN_SLP(gpd1-3, INPUT, NONE); - }; -}; - -&pinctrl_1 { - pinctrl-names = "default"; - pinctrl-0 = <&initial1 &sleep1>; - - initial1: initial-state { - PIN_IN(gpk2-0, DOWN, LV1); - PIN_IN(gpk2-1, DOWN, LV1); - PIN_IN(gpk2-2, DOWN, LV1); - PIN_IN(gpk2-3, DOWN, LV1); - PIN_IN(gpk2-4, DOWN, LV1); - PIN_IN(gpk2-5, DOWN, LV1); - PIN_IN(gpk2-6, DOWN, LV1); - }; - - sleep1: sleep-state { - PIN_SLP(gpe0-0, PREV, NONE); - PIN_SLP(gpe0-1, PREV, NONE); - PIN_SLP(gpe0-2, INPUT, DOWN); - PIN_SLP(gpe0-3, INPUT, DOWN); - PIN_SLP(gpe0-4, PREV, NONE); - PIN_SLP(gpe0-5, INPUT, DOWN); - PIN_SLP(gpe0-6, INPUT, DOWN); - PIN_SLP(gpe0-7, INPUT, DOWN); - - PIN_SLP(gpe1-0, INPUT, DOWN); - PIN_SLP(gpe1-1, PREV, NONE); - PIN_SLP(gpe1-2, INPUT, DOWN); - PIN_SLP(gpe1-3, INPUT, DOWN); - PIN_SLP(gpe1-4, INPUT, DOWN); - PIN_SLP(gpe1-5, INPUT, DOWN); - PIN_SLP(gpe1-6, INPUT, DOWN); - PIN_SLP(gpe1-7, INPUT, NONE); - - PIN_SLP(gpe2-0, INPUT, NONE); - PIN_SLP(gpe2-1, INPUT, NONE); - PIN_SLP(gpe2-2, INPUT, NONE); - - PIN_SLP(gpk0-0, INPUT, DOWN); - PIN_SLP(gpk0-1, INPUT, DOWN); - PIN_SLP(gpk0-2, OUT0, NONE); - PIN_SLP(gpk0-3, INPUT, DOWN); - PIN_SLP(gpk0-4, INPUT, DOWN); - PIN_SLP(gpk0-5, INPUT, DOWN); - PIN_SLP(gpk0-6, INPUT, DOWN); - PIN_SLP(gpk0-7, INPUT, DOWN); - - PIN_SLP(gpk1-0, PREV, NONE); - PIN_SLP(gpk1-1, PREV, NONE); - PIN_SLP(gpk1-2, INPUT, DOWN); - PIN_SLP(gpk1-3, PREV, NONE); - PIN_SLP(gpk1-4, PREV, NONE); - PIN_SLP(gpk1-5, PREV, NONE); - PIN_SLP(gpk1-6, PREV, NONE); - - PIN_SLP(gpk2-0, INPUT, DOWN); - PIN_SLP(gpk2-1, INPUT, DOWN); - PIN_SLP(gpk2-2, INPUT, DOWN); - PIN_SLP(gpk2-3, INPUT, DOWN); - PIN_SLP(gpk2-4, INPUT, DOWN); - PIN_SLP(gpk2-5, INPUT, DOWN); - PIN_SLP(gpk2-6, INPUT, DOWN); - - PIN_SLP(gpl0-0, INPUT, DOWN); - PIN_SLP(gpl0-1, INPUT, DOWN); - PIN_SLP(gpl0-2, INPUT, DOWN); - PIN_SLP(gpl0-3, INPUT, DOWN); - - PIN_SLP(gpm0-0, INPUT, DOWN); - PIN_SLP(gpm0-1, INPUT, DOWN); - PIN_SLP(gpm0-2, INPUT, DOWN); - PIN_SLP(gpm0-3, INPUT, DOWN); - PIN_SLP(gpm0-4, INPUT, DOWN); - PIN_SLP(gpm0-5, INPUT, DOWN); - PIN_SLP(gpm0-6, INPUT, DOWN); - PIN_SLP(gpm0-7, INPUT, DOWN); - - PIN_SLP(gpm1-0, INPUT, DOWN); - PIN_SLP(gpm1-1, INPUT, DOWN); - PIN_SLP(gpm1-2, INPUT, DOWN); - PIN_SLP(gpm1-3, INPUT, DOWN); - PIN_SLP(gpm1-4, INPUT, DOWN); - PIN_SLP(gpm1-5, INPUT, DOWN); - PIN_SLP(gpm1-6, INPUT, DOWN); - - PIN_SLP(gpm2-0, INPUT, DOWN); - PIN_SLP(gpm2-1, INPUT, DOWN); - PIN_SLP(gpm2-2, INPUT, DOWN); - PIN_SLP(gpm2-3, INPUT, DOWN); - PIN_SLP(gpm2-4, INPUT, DOWN); - - PIN_SLP(gpm3-0, INPUT, DOWN); - PIN_SLP(gpm3-1, INPUT, DOWN); - PIN_SLP(gpm3-2, INPUT, DOWN); - PIN_SLP(gpm3-3, INPUT, DOWN); - PIN_SLP(gpm3-4, INPUT, DOWN); - PIN_SLP(gpm3-5, INPUT, DOWN); - PIN_SLP(gpm3-6, INPUT, DOWN); - PIN_SLP(gpm3-7, INPUT, DOWN); - - PIN_SLP(gpm4-0, INPUT, DOWN); - PIN_SLP(gpm4-1, INPUT, DOWN); - PIN_SLP(gpm4-2, INPUT, DOWN); - PIN_SLP(gpm4-3, INPUT, DOWN); - PIN_SLP(gpm4-4, INPUT, DOWN); - PIN_SLP(gpm4-5, INPUT, DOWN); - PIN_SLP(gpm4-6, INPUT, DOWN); - PIN_SLP(gpm4-7, INPUT, DOWN); - }; -}; diff --git a/sys/gnu/dts/arm/exynos3250-pinctrl.dtsi b/sys/gnu/dts/arm/exynos3250-pinctrl.dtsi deleted file mode 100644 index dff3c6e3aa1..00000000000 --- a/sys/gnu/dts/arm/exynos3250-pinctrl.dtsi +++ /dev/null @@ -1,568 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's Exynos3250 SoCs pin-mux and pin-config device tree source - * - * Copyright (c) 2014 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Samsung's Exynos3250 SoCs pin-mux and pin-config optiosn are listed as device - * tree nodes are listed in this file. - */ - -#include - -#define PIN_IN(_pin, _pull, _drv) \ - _pin { \ - samsung,pins = #_pin; \ - samsung,pin-function = ; \ - samsung,pin-pud = ; \ - samsung,pin-drv = ; \ - } - -#define PIN_OUT(_pin, _drv) \ - _pin { \ - samsung,pins = #_pin; \ - samsung,pin-function = ; \ - samsung,pin-pud = ; \ - samsung,pin-drv = ; \ - } - -#define PIN_OUT_SET(_pin, _val, _drv) \ - _pin { \ - samsung,pins = #_pin; \ - samsung,pin-function = ; \ - samsung,pin-pud = ; \ - samsung,pin-drv = ; \ - samsung,pin-val = <_val>; \ - } - -#define PIN_CFG(_pin, _sel, _pull, _drv) \ - _pin { \ - samsung,pins = #_pin; \ - samsung,pin-function = <_sel>; \ - samsung,pin-pud = ; \ - samsung,pin-drv = ; \ - } - -#define PIN_SLP(_pin, _mode, _pull) \ - _pin { \ - samsung,pins = #_pin; \ - samsung,pin-con-pdn = ; \ - samsung,pin-pud-pdn = ; \ - } - -&pinctrl_0 { - gpa0: gpa0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpa1: gpa1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpb: gpb { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc0: gpc0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc1: gpc1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpd0: gpd0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpd1: gpd1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - uart0_data: uart0-data { - samsung,pins = "gpa0-0", "gpa0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart0_fctl: uart0-fctl { - samsung,pins = "gpa0-2", "gpa0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart1_data: uart1-data { - samsung,pins = "gpa0-4", "gpa0-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart1_fctl: uart1-fctl { - samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c2_bus: i2c2-bus { - samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart2_data: uart2-data { - samsung,pins = "gpa1-0", "gpa1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c3_bus: i2c3-bus { - samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spi0_bus: spi0-bus { - samsung,pins = "gpb-0", "gpb-2", "gpb-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c4_bus: i2c4-bus { - samsung,pins = "gpb-0", "gpb-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spi1_bus: spi1-bus { - samsung,pins = "gpb-4", "gpb-6", "gpb-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c5_bus: i2c5-bus { - samsung,pins = "gpb-2", "gpb-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2s2_bus: i2s2-bus { - samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", - "gpc1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pcm2_bus: pcm2-bus { - samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", - "gpc1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c6_bus: i2c6-bus { - samsung,pins = "gpc1-3", "gpc1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm0_out: pwm0-out { - samsung,pins = "gpd0-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm1_out: pwm1-out { - samsung,pins = "gpd0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c7_bus: i2c7-bus { - samsung,pins = "gpd0-2", "gpd0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm2_out: pwm2-out { - samsung,pins = "gpd0-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm3_out: pwm3-out { - samsung,pins = "gpd0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c0_bus: i2c0-bus { - samsung,pins = "gpd1-0", "gpd1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - mipi0_clk: mipi0-clk { - samsung,pins = "gpd1-0", "gpd1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c1_bus: i2c1-bus { - samsung,pins = "gpd1-2", "gpd1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pinctrl_1 { - gpe0: gpe0 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpe1: gpe1 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpe2: gpe2 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpk0: gpk0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpk1: gpk1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpk2: gpk2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpl0: gpl0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpm0: gpm0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpm1: gpm1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpm2: gpm2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpm3: gpm3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpm4: gpm4 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpx0: gpx0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - interrupt-parent = <&gic>; - interrupts = , - , - , - , - , - , - , - ; - #interrupt-cells = <2>; - }; - - gpx1: gpx1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - interrupt-parent = <&gic>; - interrupts = , - , - , - , - , - , - , - ; - #interrupt-cells = <2>; - }; - - gpx2: gpx2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpx3: gpx3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - sd0_clk: sd0-clk { - samsung,pins = "gpk0-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_cmd: sd0-cmd { - samsung,pins = "gpk0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_cd: sd0-cd { - samsung,pins = "gpk0-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_rdqs: sd0-rdqs { - samsung,pins = "gpk0-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus1: sd0-bus-width1 { - samsung,pins = "gpk0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus4: sd0-bus-width4 { - samsung,pins = "gpk0-4", "gpk0-5", "gpk0-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus8: sd0-bus-width8 { - samsung,pins = "gpl0-0", "gpl0-1", "gpl0-2", "gpl0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_clk: sd1-clk { - samsung,pins = "gpk1-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_cmd: sd1-cmd { - samsung,pins = "gpk1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_cd: sd1-cd { - samsung,pins = "gpk1-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_bus1: sd1-bus-width1 { - samsung,pins = "gpk1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_bus4: sd1-bus-width4 { - samsung,pins = "gpk1-4", "gpk1-5", "gpk1-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_clk: sd2-clk { - samsung,pins = "gpk2-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_cmd: sd2-cmd { - samsung,pins = "gpk2-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_cd: sd2-cd { - samsung,pins = "gpk2-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_bus1: sd2-bus-width1 { - samsung,pins = "gpk2-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_bus4: sd2-bus-width4 { - samsung,pins = "gpk2-4", "gpk2-5", "gpk2-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_port_b_io: cam-port-b-io { - samsung,pins = "gpm0-0", "gpm0-1", "gpm0-2", "gpm0-3", - "gpm0-4", "gpm0-5", "gpm0-6", "gpm0-7", - "gpm1-0", "gpm1-1", "gpm2-0", "gpm2-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_port_b_clk_active: cam-port-b-clk-active { - samsung,pins = "gpm2-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_port_b_clk_idle: cam-port-b-clk-idle { - samsung,pins = "gpm2-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - fimc_is_i2c0: fimc-is-i2c0 { - samsung,pins = "gpm4-0", "gpm4-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - fimc_is_i2c1: fimc-is-i2c1 { - samsung,pins = "gpm4-2", "gpm4-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - fimc_is_uart: fimc-is-uart { - samsung,pins = "gpm3-5", "gpm3-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; diff --git a/sys/gnu/dts/arm/exynos3250-rinato.dts b/sys/gnu/dts/arm/exynos3250-rinato.dts deleted file mode 100644 index 86c26a4edfd..00000000000 --- a/sys/gnu/dts/arm/exynos3250-rinato.dts +++ /dev/null @@ -1,872 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's Exynos3250 based Rinato board device tree source - * - * Copyright (c) 2014 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Device tree source file for Samsung's Rinato board which is based on - * Samsung Exynos3250 SoC. - */ - -/dts-v1/; -#include "exynos3250.dtsi" -#include "exynos4412-ppmu-common.dtsi" -#include -#include -#include - -/ { - model = "Samsung Rinato board"; - compatible = "samsung,rinato", "samsung,exynos3250", "samsung,exynos3"; - - aliases { - i2c7 = &i2c_max77836; - }; - - chosen { - stdout-path = &serial_1; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x1ff00000>; - }; - - firmware@205f000 { - compatible = "samsung,secure-firmware"; - reg = <0x0205F000 0x1000>; - }; - - gpio_keys { - compatible = "gpio-keys"; - - power_key { - gpios = <&gpx2 7 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "power key"; - debounce-interval = <10>; - wakeup-source; - }; - }; - - i2c_max77836: i2c-gpio-0 { - compatible = "i2c-gpio"; - gpios = <&gpd0 2 GPIO_ACTIVE_HIGH>, <&gpd0 3 GPIO_ACTIVE_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - - max77836: subpmic@25 { - compatible = "maxim,max77836"; - interrupt-parent = <&gpx1>; - interrupts = <5 IRQ_TYPE_NONE>; - reg = <0x25>; - wakeup-source; - - muic: max77836-muic { - compatible = "maxim,max77836-muic"; - }; - - regulators { - compatible = "maxim,max77836-regulator"; - safeout_reg: SAFEOUT { - regulator-name = "SAFEOUT"; - }; - - charger_reg: CHARGER { - regulator-name = "CHARGER"; - regulator-min-microamp = <45000>; - regulator-max-microamp = <475000>; - regulator-boot-on; - }; - - motor_reg: LDO1 { - regulator-name = "MOT_2.7V"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <2700000>; - }; - - LDO2 { - regulator-name = "UNUSED_LDO2"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3950000>; - }; - }; - - charger { - compatible = "maxim,max77836-charger"; - - maxim,constant-uvolt = <4350000>; - maxim,fast-charge-uamp = <225000>; - maxim,eoc-uamp = <7500>; - maxim,ovp-uvolt = <6500000>; - }; - }; - }; - - haptics { - compatible = "regulator-haptic"; - haptic-supply = <&motor_reg>; - min-microvolt = <1100000>; - max-microvolt = <2700000>; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - cooling-maps { - map0 { - /* Corresponds to 500MHz */ - cooling-device = <&cpu0 5 5>, - <&cpu1 5 5>; - }; - map1 { - /* Corresponds to 200MHz */ - cooling-device = <&cpu0 8 8>, - <&cpu1 8 8>; - }; - }; - }; - }; -}; - -&adc { - vdd-supply = <&ldo3_reg>; - status = "okay"; - assigned-clocks = <&cmu CLK_SCLK_TSADC>; - assigned-clock-rates = <6000000>; - - thermistor-ap { - compatible = "ntc,ncp15wb473"; - pullup-uv = <1800000>; - pullup-ohm = <100000>; - pulldown-ohm = <100000>; - io-channels = <&adc 0>; - }; - - thermistor-battery { - compatible = "ntc,ncp15wb473"; - pullup-uv = <1800000>; - pullup-ohm = <100000>; - pulldown-ohm = <100000>; - io-channels = <&adc 1>; - }; -}; - -&bus_dmc { - devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>; - vdd-supply = <&buck1_reg>; - status = "okay"; -}; - -&bus_leftbus { - devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>; - vdd-supply = <&buck3_reg>; - status = "okay"; -}; - -&bus_rightbus { - devfreq = <&bus_leftbus>; - status = "okay"; -}; - -&bus_lcd0 { - devfreq = <&bus_leftbus>; - status = "okay"; -}; - -&bus_fsys { - devfreq = <&bus_leftbus>; - status = "okay"; -}; - -&bus_mcuisp { - devfreq = <&bus_leftbus>; - status = "okay"; -}; - -&bus_isp { - devfreq = <&bus_leftbus>; - status = "okay"; -}; - -&bus_peril { - devfreq = <&bus_leftbus>; - status = "okay"; -}; - -&bus_mfc { - devfreq = <&bus_leftbus>; - status = "okay"; -}; - -&cpu0 { - cpu0-supply = <&buck2_reg>; -}; - -&exynos_usbphy { - status = "okay"; - vbus-supply = <&safeout_reg>; -}; - -&hsotg { - vusb_d-supply = <&ldo15_reg>; - vusb_a-supply = <&ldo12_reg>; - dr_mode = "peripheral"; - status = "okay"; -}; - -&dsi_0 { - vddcore-supply = <&ldo6_reg>; - vddio-supply = <&ldo6_reg>; - samsung,burst-clock-frequency = <250000000>; - samsung,esc-clock-frequency = <20000000>; - samsung,pll-clock-frequency = <24000000>; - status = "okay"; - - panel@0 { - compatible = "samsung,s6e63j0x03"; - reg = <0>; - vdd3-supply = <&ldo16_reg>; - vci-supply = <&ldo20_reg>; - reset-gpios = <&gpe0 1 GPIO_ACTIVE_LOW>; - te-gpios = <&gpx0 6 GPIO_ACTIVE_HIGH>; - }; -}; - -&fimd { - status = "okay"; - - i80-if-timings { - cs-setup = <0>; - wr-setup = <0>; - wr-act = <1>; - wr-hold = <0>; - }; -}; - -&gpu { - mali-supply = <&buck3_reg>; - status = "okay"; -}; - -&i2c_0 { - #address-cells = <1>; - #size-cells = <0>; - samsung,i2c-sda-delay = <100>; - samsung,i2c-slave-addr = <0x10>; - samsung,i2c-max-bus-freq = <100000>; - status = "okay"; - - s2mps14_pmic@66 { - compatible = "samsung,s2mps14-pmic"; - interrupt-parent = <&gpx0>; - interrupts = <7 IRQ_TYPE_NONE>; - reg = <0x66>; - wakeup-source; - - s2mps14_osc: clocks { - compatible = "samsung,s2mps14-clk"; - #clock-cells = <1>; - clock-output-names = "s2mps14_ap", "unused", - "s2mps14_bt"; - }; - - regulators { - ldo1_reg: LDO1 { - regulator-name = "VAP_ALIVE_1.0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - ldo2_reg: LDO2 { - regulator-name = "VAP_M1_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo3_reg: LDO3 { - regulator-name = "VCC_AP_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo4_reg: LDO4 { - regulator-name = "VAP_AVDD_PLL1"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo5_reg: LDO5 { - regulator-name = "VAP_PLL_ISO_1.0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo6_reg: LDO6 { - regulator-name = "VAP_VMIPI_1.0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo7_reg: LDO7 { - regulator-name = "VAP_AVDD_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo8_reg: LDO8 { - regulator-name = "VAP_USB_3.0V"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo9_reg: LDO9 { - regulator-name = "V_LPDDR_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - ldo10_reg: LDO10 { - regulator-name = "UNUSED_LDO10"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo11_reg: LDO11 { - regulator-name = "V_EMMC_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - samsung,ext-control-gpios = <&gpk0 2 GPIO_ACTIVE_HIGH>; - }; - - ldo12_reg: LDO12 { - regulator-name = "V_EMMC_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - samsung,ext-control-gpios = <&gpk0 2 GPIO_ACTIVE_HIGH>; - }; - - ldo13_reg: LDO13 { - regulator-name = "CAM_AVDD_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo14_reg: LDO14 { - regulator-name = "UNUSED_LDO14"; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo15_reg: LDO15 { - regulator-name = "TSP_AVDD_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo16_reg: LDO16 { - regulator-name = "LCD_VDD_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo17_reg: LDO17 { - regulator-name = "V_IRLED_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo18_reg: LDO18 { - regulator-name = "CAM_AF_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo19_reg: LDO19 { - regulator-name = "TSP_VDD_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo20_reg: LDO20 { - regulator-name = "LCD_VDD_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo21_reg: LDO21 { - regulator-name = "CAM_IO_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo22_reg: LDO22 { - regulator-name = "CAM_DVDD_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo23_reg: LDO23 { - regulator-name = "HRM_VCC_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo24_reg: LDO24 { - regulator-name = "HRM_VCC_3.3V"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo25_reg: LDO25 { - regulator-name = "UNUSED_LDO25"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck1_reg: BUCK1 { - regulator-name = "VAP_MIF_1.0V"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <900000>; - regulator-always-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck2_reg: BUCK2 { - regulator-name = "VAP_ARM_1.0V"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1150000>; - regulator-always-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck3_reg: BUCK3 { - regulator-name = "VAP_INT3D_1.0V"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck4_reg: BUCK4 { - regulator-name = "VCC_SUB_1.95V"; - regulator-min-microvolt = <1950000>; - regulator-max-microvolt = <1950000>; - regulator-always-on; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - buck5_reg: BUCK5 { - regulator-name = "VCC_SUB_1.35V"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - }; - }; -}; - -&i2c_1 { - #address-cells = <1>; - #size-cells = <0>; - samsung,i2c-sda-delay = <100>; - samsung,i2c-slave-addr = <0x10>; - samsung,i2c-max-bus-freq = <400000>; - status = "okay"; - - fuelgauge@36 { - compatible = "maxim,max77836-battery"; - interrupt-parent = <&gpx1>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - reg = <0x36>; - }; -}; - -&i2s2 { - status = "okay"; -}; - -&jpeg { - status = "okay"; -}; - -&mshc_0 { - #address-cells = <1>; - #size-cells = <0>; - broken-cd; - non-removable; - cap-mmc-highspeed; - desc-num = <4>; - mmc-hs200-1_8v; - card-detect-delay = <200>; - vmmc-supply = <&ldo12_reg>; - clock-frequency = <100000000>; - max-frequency = <100000000>; - samsung,dw-mshc-ciu-div = <1>; - samsung,dw-mshc-sdr-timing = <0 1>; - samsung,dw-mshc-ddr-timing = <1 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>; - bus-width = <8>; - status = "okay"; -}; - -&serial_0 { - assigned-clocks = <&cmu CLK_SCLK_UART0>; - assigned-clock-rates = <100000000>; - status = "okay"; -}; - -&serial_1 { - status = "okay"; -}; - -&tmu { - vtmu-supply = <&ldo7_reg>; - status = "okay"; -}; - -&rtc { - clocks = <&cmu CLK_RTC>, <&s2mps14_osc S2MPS11_CLK_AP>; - clock-names = "rtc", "rtc_src"; - status = "okay"; -}; - -&xusbxti { - clock-frequency = <24000000>; -}; - -&pinctrl_0 { - pinctrl-names = "default"; - pinctrl-0 = <&initial0 &sleep0>; - - initial0: initial-state { - PIN_IN(gpa1-4, DOWN, LV1); - PIN_IN(gpa1-5, DOWN, LV1); - - PIN_IN(gpc0-0, DOWN, LV1); - PIN_IN(gpc0-1, DOWN, LV1); - PIN_IN(gpc0-2, DOWN, LV1); - PIN_IN(gpc0-3, DOWN, LV1); - PIN_IN(gpc0-4, DOWN, LV1); - - PIN_IN(gpd0-0, DOWN, LV1); - PIN_IN(gpd0-1, DOWN, LV1); - }; - - sleep0: sleep-state { - PIN_SLP(gpa0-0, INPUT, DOWN); - PIN_SLP(gpa0-1, INPUT, DOWN); - PIN_SLP(gpa0-2, INPUT, DOWN); - PIN_SLP(gpa0-3, INPUT, DOWN); - PIN_SLP(gpa0-4, INPUT, DOWN); - PIN_SLP(gpa0-5, INPUT, DOWN); - PIN_SLP(gpa0-6, INPUT, DOWN); - PIN_SLP(gpa0-7, INPUT, DOWN); - - PIN_SLP(gpa1-0, INPUT, DOWN); - PIN_SLP(gpa1-1, INPUT, DOWN); - PIN_SLP(gpa1-2, INPUT, DOWN); - PIN_SLP(gpa1-3, INPUT, DOWN); - PIN_SLP(gpa1-4, INPUT, DOWN); - PIN_SLP(gpa1-5, INPUT, DOWN); - - PIN_SLP(gpb-0, PREV, NONE); - PIN_SLP(gpb-1, PREV, NONE); - PIN_SLP(gpb-2, PREV, NONE); - PIN_SLP(gpb-3, PREV, NONE); - PIN_SLP(gpb-4, INPUT, DOWN); - PIN_SLP(gpb-5, INPUT, DOWN); - PIN_SLP(gpb-6, INPUT, DOWN); - PIN_SLP(gpb-7, INPUT, DOWN); - - PIN_SLP(gpc0-0, INPUT, DOWN); - PIN_SLP(gpc0-1, INPUT, DOWN); - PIN_SLP(gpc0-2, INPUT, DOWN); - PIN_SLP(gpc0-3, INPUT, DOWN); - PIN_SLP(gpc0-4, INPUT, DOWN); - - PIN_SLP(gpc1-0, INPUT, DOWN); - PIN_SLP(gpc1-1, INPUT, DOWN); - PIN_SLP(gpc1-2, INPUT, DOWN); - PIN_SLP(gpc1-3, INPUT, DOWN); - PIN_SLP(gpc1-4, INPUT, DOWN); - - PIN_SLP(gpd0-0, INPUT, DOWN); - PIN_SLP(gpd0-1, INPUT, DOWN); - PIN_SLP(gpd0-2, INPUT, NONE); - PIN_SLP(gpd0-3, INPUT, NONE); - - PIN_SLP(gpd1-0, INPUT, NONE); - PIN_SLP(gpd1-1, INPUT, NONE); - PIN_SLP(gpd1-2, INPUT, NONE); - PIN_SLP(gpd1-3, INPUT, NONE); - }; -}; - -&pinctrl_1 { - pinctrl-names = "default"; - pinctrl-0 = <&initial1 &sleep1>; - - initial1: initial-state { - PIN_IN(gpe0-6, DOWN, LV1); - PIN_IN(gpe0-7, DOWN, LV1); - - PIN_IN(gpe1-0, DOWN, LV1); - PIN_IN(gpe1-3, DOWN, LV1); - PIN_IN(gpe1-4, DOWN, LV1); - PIN_IN(gpe1-5, DOWN, LV1); - PIN_IN(gpe1-6, DOWN, LV1); - - PIN_IN(gpk2-0, DOWN, LV1); - PIN_IN(gpk2-1, DOWN, LV1); - PIN_IN(gpk2-2, DOWN, LV1); - PIN_IN(gpk2-3, DOWN, LV1); - PIN_IN(gpk2-4, DOWN, LV1); - PIN_IN(gpk2-5, DOWN, LV1); - PIN_IN(gpk2-6, DOWN, LV1); - - PIN_IN(gpm0-0, DOWN, LV1); - PIN_IN(gpm0-1, DOWN, LV1); - PIN_IN(gpm0-2, DOWN, LV1); - PIN_IN(gpm0-3, DOWN, LV1); - PIN_IN(gpm0-4, DOWN, LV1); - PIN_IN(gpm0-5, DOWN, LV1); - PIN_IN(gpm0-6, DOWN, LV1); - PIN_IN(gpm0-7, DOWN, LV1); - - PIN_IN(gpm1-0, DOWN, LV1); - PIN_IN(gpm1-1, DOWN, LV1); - PIN_IN(gpm1-2, DOWN, LV1); - PIN_IN(gpm1-3, DOWN, LV1); - PIN_IN(gpm1-4, DOWN, LV1); - PIN_IN(gpm1-5, DOWN, LV1); - PIN_IN(gpm1-6, DOWN, LV1); - - PIN_IN(gpm2-0, DOWN, LV1); - PIN_IN(gpm2-1, DOWN, LV1); - - PIN_IN(gpm3-0, DOWN, LV1); - PIN_IN(gpm3-1, DOWN, LV1); - PIN_IN(gpm3-2, DOWN, LV1); - PIN_IN(gpm3-3, DOWN, LV1); - PIN_IN(gpm3-4, DOWN, LV1); - - PIN_IN(gpm4-1, DOWN, LV1); - PIN_IN(gpm4-2, DOWN, LV1); - PIN_IN(gpm4-3, DOWN, LV1); - PIN_IN(gpm4-4, DOWN, LV1); - PIN_IN(gpm4-5, DOWN, LV1); - PIN_IN(gpm4-6, DOWN, LV1); - PIN_IN(gpm4-7, DOWN, LV1); - }; - - sleep1: sleep-state { - PIN_SLP(gpe0-0, PREV, NONE); - PIN_SLP(gpe0-1, PREV, NONE); - PIN_SLP(gpe0-2, INPUT, DOWN); - PIN_SLP(gpe0-3, INPUT, UP); - PIN_SLP(gpe0-4, INPUT, DOWN); - PIN_SLP(gpe0-5, INPUT, DOWN); - PIN_SLP(gpe0-6, INPUT, DOWN); - PIN_SLP(gpe0-7, INPUT, DOWN); - - PIN_SLP(gpe1-0, INPUT, DOWN); - PIN_SLP(gpe1-1, PREV, NONE); - PIN_SLP(gpe1-2, INPUT, DOWN); - PIN_SLP(gpe1-3, INPUT, DOWN); - PIN_SLP(gpe1-4, INPUT, DOWN); - PIN_SLP(gpe1-5, INPUT, DOWN); - PIN_SLP(gpe1-6, INPUT, DOWN); - PIN_SLP(gpe1-7, INPUT, NONE); - - PIN_SLP(gpe2-0, INPUT, NONE); - PIN_SLP(gpe2-1, INPUT, NONE); - PIN_SLP(gpe2-2, INPUT, NONE); - - PIN_SLP(gpk0-0, INPUT, DOWN); - PIN_SLP(gpk0-1, INPUT, DOWN); - PIN_SLP(gpk0-2, OUT0, NONE); - PIN_SLP(gpk0-3, INPUT, DOWN); - PIN_SLP(gpk0-4, INPUT, DOWN); - PIN_SLP(gpk0-5, INPUT, DOWN); - PIN_SLP(gpk0-6, INPUT, DOWN); - PIN_SLP(gpk0-7, INPUT, DOWN); - - PIN_SLP(gpk1-0, INPUT, DOWN); - PIN_SLP(gpk1-1, INPUT, DOWN); - PIN_SLP(gpk1-2, INPUT, DOWN); - PIN_SLP(gpk1-3, INPUT, DOWN); - PIN_SLP(gpk1-4, INPUT, DOWN); - PIN_SLP(gpk1-5, INPUT, DOWN); - PIN_SLP(gpk1-6, INPUT, DOWN); - - PIN_SLP(gpk2-0, INPUT, DOWN); - PIN_SLP(gpk2-1, INPUT, DOWN); - PIN_SLP(gpk2-2, INPUT, DOWN); - PIN_SLP(gpk2-3, INPUT, DOWN); - PIN_SLP(gpk2-4, INPUT, DOWN); - PIN_SLP(gpk2-5, INPUT, DOWN); - PIN_SLP(gpk2-6, INPUT, DOWN); - - PIN_SLP(gpl0-0, INPUT, DOWN); - PIN_SLP(gpl0-1, INPUT, DOWN); - PIN_SLP(gpl0-2, INPUT, DOWN); - PIN_SLP(gpl0-3, INPUT, DOWN); - - PIN_SLP(gpm0-0, INPUT, DOWN); - PIN_SLP(gpm0-1, INPUT, DOWN); - PIN_SLP(gpm0-2, INPUT, DOWN); - PIN_SLP(gpm0-3, INPUT, DOWN); - PIN_SLP(gpm0-4, INPUT, DOWN); - PIN_SLP(gpm0-5, INPUT, DOWN); - PIN_SLP(gpm0-6, INPUT, DOWN); - PIN_SLP(gpm0-7, INPUT, DOWN); - - PIN_SLP(gpm1-0, INPUT, DOWN); - PIN_SLP(gpm1-1, INPUT, DOWN); - PIN_SLP(gpm1-2, INPUT, DOWN); - PIN_SLP(gpm1-3, INPUT, DOWN); - PIN_SLP(gpm1-4, INPUT, DOWN); - PIN_SLP(gpm1-5, INPUT, DOWN); - PIN_SLP(gpm1-6, INPUT, DOWN); - - PIN_SLP(gpm2-0, INPUT, DOWN); - PIN_SLP(gpm2-1, INPUT, DOWN); - PIN_SLP(gpm2-2, INPUT, DOWN); - PIN_SLP(gpm2-3, INPUT, DOWN); - PIN_SLP(gpm2-4, INPUT, DOWN); - - PIN_SLP(gpm3-0, INPUT, DOWN); - PIN_SLP(gpm3-1, INPUT, DOWN); - PIN_SLP(gpm3-2, INPUT, DOWN); - PIN_SLP(gpm3-3, INPUT, DOWN); - PIN_SLP(gpm3-4, INPUT, DOWN); - PIN_SLP(gpm3-5, INPUT, DOWN); - PIN_SLP(gpm3-6, INPUT, DOWN); - PIN_SLP(gpm3-7, INPUT, DOWN); - - PIN_SLP(gpm4-0, INPUT, DOWN); - PIN_SLP(gpm4-1, INPUT, DOWN); - PIN_SLP(gpm4-2, INPUT, DOWN); - PIN_SLP(gpm4-3, INPUT, DOWN); - PIN_SLP(gpm4-4, INPUT, DOWN); - PIN_SLP(gpm4-5, INPUT, DOWN); - PIN_SLP(gpm4-6, INPUT, DOWN); - PIN_SLP(gpm4-7, INPUT, DOWN); - }; -}; diff --git a/sys/gnu/dts/arm/exynos3250.dtsi b/sys/gnu/dts/arm/exynos3250.dtsi deleted file mode 100644 index 044e5da64a7..00000000000 --- a/sys/gnu/dts/arm/exynos3250.dtsi +++ /dev/null @@ -1,967 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's Exynos3250 SoC device tree source - * - * Copyright (c) 2014 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Samsung's Exynos3250 SoC device nodes are listed in this file. Exynos3250 - * based board files can include this file and provide values for board specfic - * bindings. - * - * Note: This file does not include device nodes for all the controllers in - * Exynos3250 SoC. As device tree coverage for Exynos3250 increases, additional - * nodes can be added to this file. - */ - -#include "exynos4-cpu-thermal.dtsi" -#include -#include -#include - -/ { - compatible = "samsung,exynos3250"; - interrupt-parent = <&gic>; - #address-cells = <1>; - #size-cells = <1>; - - aliases { - pinctrl0 = &pinctrl_0; - pinctrl1 = &pinctrl_1; - mshc0 = &mshc_0; - mshc1 = &mshc_1; - mshc2 = &mshc_2; - spi0 = &spi_0; - spi1 = &spi_1; - i2c0 = &i2c_0; - i2c1 = &i2c_1; - i2c2 = &i2c_2; - i2c3 = &i2c_3; - i2c4 = &i2c_4; - i2c5 = &i2c_5; - i2c6 = &i2c_6; - i2c7 = &i2c_7; - serial0 = &serial_0; - serial1 = &serial_1; - serial2 = &serial_2; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0>; - clock-frequency = <1000000000>; - clocks = <&cmu CLK_ARM_CLK>; - clock-names = "cpu"; - #cooling-cells = <2>; - - operating-points = < - 1000000 1150000 - 900000 1112500 - 800000 1075000 - 700000 1037500 - 600000 1000000 - 500000 962500 - 400000 925000 - 300000 887500 - 200000 850000 - 100000 850000 - >; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <1>; - clock-frequency = <1000000000>; - clocks = <&cmu CLK_ARM_CLK>; - clock-names = "cpu"; - #cooling-cells = <2>; - - operating-points = < - 1000000 1150000 - 900000 1112500 - 800000 1075000 - 700000 1037500 - 600000 1000000 - 500000 962500 - 400000 925000 - 300000 887500 - 200000 850000 - 100000 850000 - >; - }; - }; - - fixed-rate-clocks { - #address-cells = <1>; - #size-cells = <0>; - - xusbxti: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - clock-frequency = <0>; - #clock-cells = <0>; - clock-output-names = "xusbxti"; - }; - - xxti: clock@1 { - compatible = "fixed-clock"; - reg = <1>; - clock-frequency = <0>; - #clock-cells = <0>; - clock-output-names = "xxti"; - }; - - xtcxo: clock@2 { - compatible = "fixed-clock"; - reg = <2>; - clock-frequency = <0>; - #clock-cells = <0>; - clock-output-names = "xtcxo"; - }; - }; - - pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts = , - ; - }; - - soc: soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - sram@2020000 { - compatible = "mmio-sram"; - reg = <0x02020000 0x40000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x02020000 0x40000>; - - smp-sram@0 { - compatible = "samsung,exynos4210-sysram"; - reg = <0x0 0x1000>; - }; - - smp-sram@3f000 { - compatible = "samsung,exynos4210-sysram-ns"; - reg = <0x3f000 0x1000>; - }; - }; - - chipid@10000000 { - compatible = "samsung,exynos4210-chipid"; - reg = <0x10000000 0x100>; - }; - - sys_reg: syscon@10010000 { - compatible = "samsung,exynos3-sysreg", "syscon"; - reg = <0x10010000 0x400>; - }; - - pmu_system_controller: system-controller@10020000 { - compatible = "samsung,exynos3250-pmu", "syscon"; - reg = <0x10020000 0x4000>; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - clock-names = "clkout8"; - clocks = <&cmu CLK_FIN_PLL>; - #clock-cells = <1>; - }; - - mipi_phy: video-phy { - compatible = "samsung,s5pv210-mipi-video-phy"; - #phy-cells = <1>; - syscon = <&pmu_system_controller>; - }; - - pd_cam: power-domain@10023c00 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10023C00 0x20>; - #power-domain-cells = <0>; - label = "CAM"; - }; - - pd_mfc: power-domain@10023c40 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10023C40 0x20>; - #power-domain-cells = <0>; - label = "MFC"; - }; - - pd_g3d: power-domain@10023c60 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10023C60 0x20>; - #power-domain-cells = <0>; - label = "G3D"; - }; - - pd_lcd0: power-domain@10023c80 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10023C80 0x20>; - #power-domain-cells = <0>; - label = "LCD0"; - }; - - pd_isp: power-domain@10023ca0 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10023CA0 0x20>; - #power-domain-cells = <0>; - label = "ISP"; - }; - - cmu: clock-controller@10030000 { - compatible = "samsung,exynos3250-cmu"; - reg = <0x10030000 0x20000>; - #clock-cells = <1>; - assigned-clocks = <&cmu CLK_MOUT_ACLK_400_MCUISP_SUB>, - <&cmu CLK_MOUT_ACLK_266_SUB>; - assigned-clock-parents = <&cmu CLK_FIN_PLL>, - <&cmu CLK_FIN_PLL>; - }; - - cmu_dmc: clock-controller@105c0000 { - compatible = "samsung,exynos3250-cmu-dmc"; - reg = <0x105C0000 0x2000>; - #clock-cells = <1>; - }; - - rtc: rtc@10070000 { - compatible = "samsung,s3c6410-rtc"; - reg = <0x10070000 0x100>; - interrupts = , - ; - interrupt-parent = <&pmu_system_controller>; - status = "disabled"; - }; - - tmu: tmu@100c0000 { - compatible = "samsung,exynos3250-tmu"; - reg = <0x100C0000 0x100>; - interrupts = ; - clocks = <&cmu CLK_TMU_APBIF>; - clock-names = "tmu_apbif"; - #thermal-sensor-cells = <0>; - status = "disabled"; - }; - - gic: interrupt-controller@10481000 { - compatible = "arm,cortex-a15-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x10481000 0x1000>, - <0x10482000 0x2000>, - <0x10484000 0x2000>, - <0x10486000 0x2000>; - interrupts = ; - }; - - timer@10050000 { - compatible = "samsung,exynos4210-mct"; - reg = <0x10050000 0x800>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>; - clock-names = "fin_pll", "mct"; - }; - - pinctrl_1: pinctrl@11000000 { - compatible = "samsung,exynos3250-pinctrl"; - reg = <0x11000000 0x1000>; - interrupts = ; - - wakeup-interrupt-controller { - compatible = "samsung,exynos4210-wakeup-eint"; - interrupts = ; - }; - }; - - pinctrl_0: pinctrl@11400000 { - compatible = "samsung,exynos3250-pinctrl"; - reg = <0x11400000 0x1000>; - interrupts = ; - }; - - jpeg: codec@11830000 { - compatible = "samsung,exynos3250-jpeg"; - reg = <0x11830000 0x1000>; - interrupts = ; - clocks = <&cmu CLK_JPEG>, <&cmu CLK_SCLK_JPEG>; - clock-names = "jpeg", "sclk"; - power-domains = <&pd_cam>; - assigned-clocks = <&cmu CLK_MOUT_CAM_BLK>, <&cmu CLK_SCLK_JPEG>; - assigned-clock-rates = <0>, <150000000>; - assigned-clock-parents = <&cmu CLK_DIV_MPLL_PRE>; - iommus = <&sysmmu_jpeg>; - status = "disabled"; - }; - - sysmmu_jpeg: sysmmu@11a60000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x11a60000 0x1000>; - interrupts = ; - clock-names = "sysmmu", "master"; - clocks = <&cmu CLK_SMMUJPEG>, <&cmu CLK_JPEG>; - power-domains = <&pd_cam>; - #iommu-cells = <0>; - }; - - fimd: fimd@11c00000 { - compatible = "samsung,exynos3250-fimd"; - reg = <0x11c00000 0x30000>; - interrupt-names = "fifo", "vsync", "lcd_sys"; - interrupts = , - , - ; - clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>; - clock-names = "sclk_fimd", "fimd"; - power-domains = <&pd_lcd0>; - iommus = <&sysmmu_fimd0>; - samsung,sysreg = <&sys_reg>; - status = "disabled"; - }; - - dsi_0: dsi@11c80000 { - compatible = "samsung,exynos3250-mipi-dsi"; - reg = <0x11C80000 0x10000>; - interrupts = ; - samsung,phy-type = <0>; - power-domains = <&pd_lcd0>; - phys = <&mipi_phy 1>; - phy-names = "dsim"; - clocks = <&cmu CLK_DSIM0>, <&cmu CLK_SCLK_MIPI0>; - clock-names = "bus_clk", "pll_clk"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - sysmmu_fimd0: sysmmu@11e20000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x11e20000 0x1000>; - interrupts = ; - clock-names = "sysmmu", "master"; - clocks = <&cmu CLK_SMMUFIMD0>, <&cmu CLK_FIMD0>; - power-domains = <&pd_lcd0>; - #iommu-cells = <0>; - }; - - hsotg: hsotg@12480000 { - compatible = "samsung,s3c6400-hsotg", "snps,dwc2"; - reg = <0x12480000 0x20000>; - interrupts = ; - clocks = <&cmu CLK_USBOTG>; - clock-names = "otg"; - phys = <&exynos_usbphy 0>; - phy-names = "usb2-phy"; - status = "disabled"; - }; - - mshc_0: mshc@12510000 { - compatible = "samsung,exynos5420-dw-mshc"; - reg = <0x12510000 0x1000>; - interrupts = ; - clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>; - clock-names = "biu", "ciu"; - fifo-depth = <0x80>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - mshc_1: mshc@12520000 { - compatible = "samsung,exynos5420-dw-mshc"; - reg = <0x12520000 0x1000>; - interrupts = ; - clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>; - clock-names = "biu", "ciu"; - fifo-depth = <0x80>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - mshc_2: mshc@12530000 { - compatible = "samsung,exynos5250-dw-mshc"; - reg = <0x12530000 0x1000>; - interrupts = ; - clocks = <&cmu CLK_SDMMC2>, <&cmu CLK_SCLK_MMC2>; - clock-names = "biu", "ciu"; - fifo-depth = <0x80>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - exynos_usbphy: exynos-usbphy@125b0000 { - compatible = "samsung,exynos3250-usb2-phy"; - reg = <0x125B0000 0x100>; - samsung,pmureg-phandle = <&pmu_system_controller>; - clocks = <&cmu CLK_USBOTG>, <&cmu CLK_SCLK_UPLL>; - clock-names = "phy", "ref"; - #phy-cells = <1>; - status = "disabled"; - }; - - amba { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - pdma0: pdma@12680000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x12680000 0x1000>; - interrupts = ; - clocks = <&cmu CLK_PDMA0>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; - }; - - pdma1: pdma@12690000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x12690000 0x1000>; - interrupts = ; - clocks = <&cmu CLK_PDMA1>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; - }; - }; - - adc: adc@126c0000 { - compatible = "samsung,exynos3250-adc"; - reg = <0x126C0000 0x100>; - interrupts = ; - clock-names = "adc", "sclk"; - clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>; - #io-channel-cells = <1>; - io-channel-ranges; - samsung,syscon-phandle = <&pmu_system_controller>; - status = "disabled"; - }; - - gpu: gpu@13000000 { - compatible = "samsung,exynos4210-mali", "arm,mali-400"; - reg = <0x13000000 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "gp", - "gpmmu", - "pp0", - "ppmmu0", - "pp1", - "ppmmu1", - "pp2", - "ppmmu2", - "pp3", - "ppmmu3", - "pmu"; - clocks = <&cmu CLK_G3D>, - <&cmu CLK_SCLK_G3D>; - clock-names = "bus", "core"; - power-domains = <&pd_g3d>; - status = "disabled"; - /* TODO: operating points for DVFS, assigned clock as 134 MHz */ - }; - - mfc: codec@13400000 { - compatible = "samsung,mfc-v7"; - reg = <0x13400000 0x10000>; - interrupts = ; - clock-names = "mfc", "sclk_mfc"; - clocks = <&cmu CLK_MFC>, <&cmu CLK_SCLK_MFC>; - power-domains = <&pd_mfc>; - iommus = <&sysmmu_mfc>; - }; - - sysmmu_mfc: sysmmu@13620000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x13620000 0x1000>; - interrupts = ; - clock-names = "sysmmu", "master"; - clocks = <&cmu CLK_SMMUMFC_L>, <&cmu CLK_MFC>; - power-domains = <&pd_mfc>; - #iommu-cells = <0>; - }; - - serial_0: serial@13800000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x13800000 0x100>; - interrupts = ; - clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>; - clock-names = "uart", "clk_uart_baud0"; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_data &uart0_fctl>; - status = "disabled"; - }; - - serial_1: serial@13810000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x13810000 0x100>; - interrupts = ; - clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>; - clock-names = "uart", "clk_uart_baud0"; - pinctrl-names = "default"; - pinctrl-0 = <&uart1_data>; - status = "disabled"; - }; - - serial_2: serial@13820000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x13820000 0x100>; - interrupts = ; - clocks = <&cmu CLK_UART2>, <&cmu CLK_SCLK_UART2>; - clock-names = "uart", "clk_uart_baud0"; - pinctrl-names = "default"; - pinctrl-0 = <&uart2_data>; - status = "disabled"; - }; - - i2c_0: i2c@13860000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x13860000 0x100>; - interrupts = ; - clocks = <&cmu CLK_I2C0>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_bus>; - status = "disabled"; - }; - - i2c_1: i2c@13870000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x13870000 0x100>; - interrupts = ; - clocks = <&cmu CLK_I2C1>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_bus>; - status = "disabled"; - }; - - i2c_2: i2c@13880000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x13880000 0x100>; - interrupts = ; - clocks = <&cmu CLK_I2C2>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_bus>; - status = "disabled"; - }; - - i2c_3: i2c@13890000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x13890000 0x100>; - interrupts = ; - clocks = <&cmu CLK_I2C3>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_bus>; - status = "disabled"; - }; - - i2c_4: i2c@138a0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x138A0000 0x100>; - interrupts = ; - clocks = <&cmu CLK_I2C4>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_bus>; - status = "disabled"; - }; - - i2c_5: i2c@138b0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x138B0000 0x100>; - interrupts = ; - clocks = <&cmu CLK_I2C5>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c5_bus>; - status = "disabled"; - }; - - i2c_6: i2c@138c0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x138C0000 0x100>; - interrupts = ; - clocks = <&cmu CLK_I2C6>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c6_bus>; - status = "disabled"; - }; - - i2c_7: i2c@138d0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x138D0000 0x100>; - interrupts = ; - clocks = <&cmu CLK_I2C7>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c7_bus>; - status = "disabled"; - }; - - spi_0: spi@13920000 { - compatible = "samsung,exynos4210-spi"; - reg = <0x13920000 0x100>; - interrupts = ; - dmas = <&pdma0 7>, <&pdma0 6>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>; - clock-names = "spi", "spi_busclk0"; - samsung,spi-src-clk = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_bus>; - status = "disabled"; - }; - - spi_1: spi@13930000 { - compatible = "samsung,exynos4210-spi"; - reg = <0x13930000 0x100>; - interrupts = ; - dmas = <&pdma1 7>, <&pdma1 6>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>; - clock-names = "spi", "spi_busclk0"; - samsung,spi-src-clk = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&spi1_bus>; - status = "disabled"; - }; - - i2s2: i2s@13970000 { - compatible = "samsung,s3c6410-i2s"; - reg = <0x13970000 0x100>; - interrupts = ; - clocks = <&cmu CLK_I2S>, <&cmu CLK_SCLK_I2S>; - clock-names = "iis", "i2s_opclk0"; - dmas = <&pdma0 14>, <&pdma0 13>; - dma-names = "tx", "rx"; - pinctrl-0 = <&i2s2_bus>; - pinctrl-names = "default"; - status = "disabled"; - }; - - pwm: pwm@139d0000 { - compatible = "samsung,exynos4210-pwm"; - reg = <0x139D0000 0x1000>; - interrupts = , - , - , - , - ; - #pwm-cells = <3>; - status = "disabled"; - }; - - ppmu_dmc0: ppmu_dmc0@106a0000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x106a0000 0x2000>; - status = "disabled"; - }; - - ppmu_dmc1: ppmu_dmc1@106b0000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x106b0000 0x2000>; - status = "disabled"; - }; - - ppmu_cpu: ppmu_cpu@106c0000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x106c0000 0x2000>; - status = "disabled"; - }; - - ppmu_rightbus: ppmu_rightbus@112a0000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x112a0000 0x2000>; - clocks = <&cmu CLK_PPMURIGHT>; - clock-names = "ppmu"; - status = "disabled"; - }; - - ppmu_leftbus: ppmu_leftbus0@116a0000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x116a0000 0x2000>; - clocks = <&cmu CLK_PPMULEFT>; - clock-names = "ppmu"; - status = "disabled"; - }; - - ppmu_camif: ppmu_camif@11ac0000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x11ac0000 0x2000>; - clocks = <&cmu CLK_PPMUCAMIF>; - clock-names = "ppmu"; - status = "disabled"; - }; - - ppmu_lcd0: ppmu_lcd0@11e40000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x11e40000 0x2000>; - clocks = <&cmu CLK_PPMULCD0>; - clock-names = "ppmu"; - status = "disabled"; - }; - - ppmu_fsys: ppmu_fsys@12630000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x12630000 0x2000>; - clocks = <&cmu CLK_PPMUFILE>; - clock-names = "ppmu"; - status = "disabled"; - }; - - ppmu_g3d: ppmu_g3d@13220000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x13220000 0x2000>; - clocks = <&cmu CLK_PPMUG3D>; - clock-names = "ppmu"; - status = "disabled"; - }; - - ppmu_mfc: ppmu_mfc@13660000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x13660000 0x2000>; - clocks = <&cmu CLK_PPMUMFC_L>; - clock-names = "ppmu"; - status = "disabled"; - }; - - bus_dmc: bus_dmc { - compatible = "samsung,exynos-bus"; - clocks = <&cmu_dmc CLK_DIV_DMC>; - clock-names = "bus"; - operating-points-v2 = <&bus_dmc_opp_table>; - status = "disabled"; - }; - - bus_dmc_opp_table: opp_table1 { - compatible = "operating-points-v2"; - opp-shared; - - opp-50000000 { - opp-hz = /bits/ 64 <50000000>; - opp-microvolt = <800000>; - }; - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - opp-microvolt = <800000>; - }; - opp-134000000 { - opp-hz = /bits/ 64 <134000000>; - opp-microvolt = <800000>; - }; - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - opp-microvolt = <825000>; - }; - opp-400000000 { - opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <875000>; - }; - }; - - bus_leftbus: bus_leftbus { - compatible = "samsung,exynos-bus"; - clocks = <&cmu CLK_DIV_GDL>; - clock-names = "bus"; - operating-points-v2 = <&bus_leftbus_opp_table>; - status = "disabled"; - }; - - bus_rightbus: bus_rightbus { - compatible = "samsung,exynos-bus"; - clocks = <&cmu CLK_DIV_GDR>; - clock-names = "bus"; - operating-points-v2 = <&bus_leftbus_opp_table>; - status = "disabled"; - }; - - bus_lcd0: bus_lcd0 { - compatible = "samsung,exynos-bus"; - clocks = <&cmu CLK_DIV_ACLK_160>; - clock-names = "bus"; - operating-points-v2 = <&bus_leftbus_opp_table>; - status = "disabled"; - }; - - bus_fsys: bus_fsys { - compatible = "samsung,exynos-bus"; - clocks = <&cmu CLK_DIV_ACLK_200>; - clock-names = "bus"; - operating-points-v2 = <&bus_leftbus_opp_table>; - status = "disabled"; - }; - - bus_mcuisp: bus_mcuisp { - compatible = "samsung,exynos-bus"; - clocks = <&cmu CLK_DIV_ACLK_400_MCUISP>; - clock-names = "bus"; - operating-points-v2 = <&bus_mcuisp_opp_table>; - status = "disabled"; - }; - - bus_isp: bus_isp { - compatible = "samsung,exynos-bus"; - clocks = <&cmu CLK_DIV_ACLK_266>; - clock-names = "bus"; - operating-points-v2 = <&bus_isp_opp_table>; - status = "disabled"; - }; - - bus_peril: bus_peril { - compatible = "samsung,exynos-bus"; - clocks = <&cmu CLK_DIV_ACLK_100>; - clock-names = "bus"; - operating-points-v2 = <&bus_peril_opp_table>; - status = "disabled"; - }; - - bus_mfc: bus_mfc { - compatible = "samsung,exynos-bus"; - clocks = <&cmu CLK_SCLK_MFC>; - clock-names = "bus"; - operating-points-v2 = <&bus_leftbus_opp_table>; - status = "disabled"; - }; - - bus_leftbus_opp_table: opp_table2 { - compatible = "operating-points-v2"; - opp-shared; - - opp-50000000 { - opp-hz = /bits/ 64 <50000000>; - opp-microvolt = <900000>; - }; - opp-80000000 { - opp-hz = /bits/ 64 <80000000>; - opp-microvolt = <900000>; - }; - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - opp-microvolt = <1000000>; - }; - opp-134000000 { - opp-hz = /bits/ 64 <134000000>; - opp-microvolt = <1000000>; - }; - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - opp-microvolt = <1000000>; - }; - }; - - bus_mcuisp_opp_table: opp_table3 { - compatible = "operating-points-v2"; - opp-shared; - - opp-50000000 { - opp-hz = /bits/ 64 <50000000>; - }; - opp-80000000 { - opp-hz = /bits/ 64 <80000000>; - }; - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - }; - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - }; - opp-400000000 { - opp-hz = /bits/ 64 <400000000>; - }; - }; - - bus_isp_opp_table: opp_table4 { - compatible = "operating-points-v2"; - opp-shared; - - opp-50000000 { - opp-hz = /bits/ 64 <50000000>; - }; - opp-80000000 { - opp-hz = /bits/ 64 <80000000>; - }; - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - }; - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - }; - opp-300000000 { - opp-hz = /bits/ 64 <300000000>; - }; - }; - - bus_peril_opp_table: opp_table5 { - compatible = "operating-points-v2"; - opp-shared; - - opp-50000000 { - opp-hz = /bits/ 64 <50000000>; - }; - opp-80000000 { - opp-hz = /bits/ 64 <80000000>; - }; - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - }; - }; - }; -}; - -#include "exynos3250-pinctrl.dtsi" -#include "exynos-syscon-restart.dtsi" diff --git a/sys/gnu/dts/arm/exynos4-cpu-thermal.dtsi b/sys/gnu/dts/arm/exynos4-cpu-thermal.dtsi deleted file mode 100644 index 021d9fc1b49..00000000000 --- a/sys/gnu/dts/arm/exynos4-cpu-thermal.dtsi +++ /dev/null @@ -1,48 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device tree sources for Exynos4 thermal zone - * - * Copyright (c) 2014 Lukasz Majewski - */ - -#include - -/ { -thermal-zones { - cpu_thermal: cpu-thermal { - thermal-sensors = <&tmu 0>; - polling-delay-passive = <0>; - polling-delay = <0>; - trips { - cpu_alert0: cpu-alert-0 { - temperature = <70000>; /* millicelsius */ - hysteresis = <10000>; /* millicelsius */ - type = "active"; - }; - cpu_alert1: cpu-alert-1 { - temperature = <95000>; /* millicelsius */ - hysteresis = <10000>; /* millicelsius */ - type = "active"; - }; - cpu_alert2: cpu-alert-2 { - temperature = <110000>; /* millicelsius */ - hysteresis = <10000>; /* millicelsius */ - type = "active"; - }; - cpu_crit0: cpu-crit-0 { - temperature = <120000>; /* millicelsius */ - hysteresis = <0>; /* millicelsius */ - type = "critical"; - }; - }; - cooling-maps { - map0 { - trip = <&cpu_alert0>; - }; - map1 { - trip = <&cpu_alert1>; - }; - }; - }; -}; -}; diff --git a/sys/gnu/dts/arm/exynos4.dtsi b/sys/gnu/dts/arm/exynos4.dtsi deleted file mode 100644 index d2779a790ce..00000000000 --- a/sys/gnu/dts/arm/exynos4.dtsi +++ /dev/null @@ -1,1022 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's Exynos4 SoC series common device tree source - * - * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * Copyright (c) 2010-2011 Linaro Ltd. - * www.linaro.org - * - * Samsung's Exynos4 SoC series device nodes are listed in this file. Particular - * SoCs from Exynos4 series can include this file and provide values for SoCs - * specfic bindings. - * - * Note: This file does not include device nodes for all the controllers in - * Exynos4 SoCs. As device tree coverage for Exynos4 increases, additional - * nodes can be added to this file. - */ - -#include -#include -#include -#include - -/ { - interrupt-parent = <&gic>; - #address-cells = <1>; - #size-cells = <1>; - - aliases { - spi0 = &spi_0; - spi1 = &spi_1; - spi2 = &spi_2; - i2c0 = &i2c_0; - i2c1 = &i2c_1; - i2c2 = &i2c_2; - i2c3 = &i2c_3; - i2c4 = &i2c_4; - i2c5 = &i2c_5; - i2c6 = &i2c_6; - i2c7 = &i2c_7; - i2c8 = &i2c_8; - csis0 = &csis_0; - csis1 = &csis_1; - fimc0 = &fimc_0; - fimc1 = &fimc_1; - fimc2 = &fimc_2; - fimc3 = &fimc_3; - serial0 = &serial_0; - serial1 = &serial_1; - serial2 = &serial_2; - serial3 = &serial_3; - }; - - pmu: pmu { - compatible = "arm,cortex-a9-pmu"; - interrupt-parent = <&combiner>; - status = "disabled"; - }; - - soc: soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - clock_audss: clock-controller@3810000 { - compatible = "samsung,exynos4210-audss-clock"; - reg = <0x03810000 0x0C>; - #clock-cells = <1>; - clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>, - <&clock CLK_SCLK_AUDIO0>, - <&clock CLK_SCLK_AUDIO0>; - clock-names = "pll_ref", "pll_in", "sclk_audio", - "sclk_pcm_in"; - }; - - i2s0: i2s@3830000 { - compatible = "samsung,s5pv210-i2s"; - reg = <0x03830000 0x100>; - clocks = <&clock_audss EXYNOS_I2S_BUS>, - <&clock_audss EXYNOS_DOUT_AUD_BUS>, - <&clock_audss EXYNOS_SCLK_I2S>; - clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; - #clock-cells = <1>; - clock-output-names = "i2s_cdclk0"; - dmas = <&pdma0 12>, <&pdma0 11>, <&pdma0 10>; - dma-names = "tx", "rx", "tx-sec"; - samsung,idma-addr = <0x03000000>; - #sound-dai-cells = <1>; - status = "disabled"; - }; - - chipid@10000000 { - compatible = "samsung,exynos4210-chipid"; - reg = <0x10000000 0x100>; - }; - - scu: snoop-control-unit@10500000 { - compatible = "arm,cortex-a9-scu"; - reg = <0x10500000 0x2000>; - }; - - memory-controller@12570000 { - compatible = "samsung,exynos4210-srom"; - reg = <0x12570000 0x14>; - }; - - mipi_phy: video-phy { - compatible = "samsung,s5pv210-mipi-video-phy"; - #phy-cells = <1>; - syscon = <&pmu_system_controller>; - }; - - pd_mfc: power-domain@10023c40 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10023C40 0x20>; - #power-domain-cells = <0>; - label = "MFC"; - }; - - pd_g3d: power-domain@10023c60 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10023C60 0x20>; - #power-domain-cells = <0>; - label = "G3D"; - }; - - pd_lcd0: power-domain@10023c80 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10023C80 0x20>; - #power-domain-cells = <0>; - label = "LCD0"; - }; - - pd_tv: power-domain@10023c20 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10023C20 0x20>; - #power-domain-cells = <0>; - power-domains = <&pd_lcd0>; - label = "TV"; - }; - - pd_cam: power-domain@10023c00 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10023C00 0x20>; - #power-domain-cells = <0>; - label = "CAM"; - }; - - pd_gps: power-domain@10023ce0 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10023CE0 0x20>; - #power-domain-cells = <0>; - label = "GPS"; - }; - - pd_gps_alive: power-domain@10023d00 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10023D00 0x20>; - #power-domain-cells = <0>; - label = "GPS alive"; - }; - - gic: interrupt-controller@10490000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x10490000 0x10000>, <0x10480000 0x10000>; - }; - - combiner: interrupt-controller@10440000 { - compatible = "samsung,exynos4210-combiner"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0x10440000 0x1000>; - }; - - sys_reg: syscon@10010000 { - compatible = "samsung,exynos4-sysreg", "syscon"; - reg = <0x10010000 0x400>; - }; - - pmu_system_controller: system-controller@10020000 { - compatible = "samsung,exynos4210-pmu", "syscon"; - reg = <0x10020000 0x4000>; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - }; - - dsi_0: dsi@11c80000 { - compatible = "samsung,exynos4210-mipi-dsi"; - reg = <0x11C80000 0x10000>; - interrupts = ; - power-domains = <&pd_lcd0>; - phys = <&mipi_phy 1>; - phy-names = "dsim"; - clocks = <&clock CLK_DSIM0>, <&clock CLK_SCLK_MIPI0>; - clock-names = "bus_clk", "sclk_mipi"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - camera: camera { - compatible = "samsung,fimc", "simple-bus"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - #clock-cells = <1>; - clock-output-names = "cam_a_clkout", "cam_b_clkout"; - ranges; - - fimc_0: fimc@11800000 { - compatible = "samsung,exynos4210-fimc"; - reg = <0x11800000 0x1000>; - interrupts = ; - clocks = <&clock CLK_FIMC0>, - <&clock CLK_SCLK_FIMC0>; - clock-names = "fimc", "sclk_fimc"; - power-domains = <&pd_cam>; - samsung,sysreg = <&sys_reg>; - iommus = <&sysmmu_fimc0>; - status = "disabled"; - }; - - fimc_1: fimc@11810000 { - compatible = "samsung,exynos4210-fimc"; - reg = <0x11810000 0x1000>; - interrupts = ; - clocks = <&clock CLK_FIMC1>, - <&clock CLK_SCLK_FIMC1>; - clock-names = "fimc", "sclk_fimc"; - power-domains = <&pd_cam>; - samsung,sysreg = <&sys_reg>; - iommus = <&sysmmu_fimc1>; - status = "disabled"; - }; - - fimc_2: fimc@11820000 { - compatible = "samsung,exynos4210-fimc"; - reg = <0x11820000 0x1000>; - interrupts = ; - clocks = <&clock CLK_FIMC2>, - <&clock CLK_SCLK_FIMC2>; - clock-names = "fimc", "sclk_fimc"; - power-domains = <&pd_cam>; - samsung,sysreg = <&sys_reg>; - iommus = <&sysmmu_fimc2>; - status = "disabled"; - }; - - fimc_3: fimc@11830000 { - compatible = "samsung,exynos4210-fimc"; - reg = <0x11830000 0x1000>; - interrupts = ; - clocks = <&clock CLK_FIMC3>, - <&clock CLK_SCLK_FIMC3>; - clock-names = "fimc", "sclk_fimc"; - power-domains = <&pd_cam>; - samsung,sysreg = <&sys_reg>; - iommus = <&sysmmu_fimc3>; - status = "disabled"; - }; - - csis_0: csis@11880000 { - compatible = "samsung,exynos4210-csis"; - reg = <0x11880000 0x4000>; - interrupts = ; - clocks = <&clock CLK_CSIS0>, - <&clock CLK_SCLK_CSIS0>; - clock-names = "csis", "sclk_csis"; - bus-width = <4>; - power-domains = <&pd_cam>; - phys = <&mipi_phy 0>; - phy-names = "csis"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - csis_1: csis@11890000 { - compatible = "samsung,exynos4210-csis"; - reg = <0x11890000 0x4000>; - interrupts = ; - clocks = <&clock CLK_CSIS1>, - <&clock CLK_SCLK_CSIS1>; - clock-names = "csis", "sclk_csis"; - bus-width = <2>; - power-domains = <&pd_cam>; - phys = <&mipi_phy 2>; - phy-names = "csis"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - rtc: rtc@10070000 { - compatible = "samsung,s3c6410-rtc"; - reg = <0x10070000 0x100>; - interrupt-parent = <&pmu_system_controller>; - interrupts = , - ; - clocks = <&clock CLK_RTC>; - clock-names = "rtc"; - status = "disabled"; - }; - - keypad: keypad@100a0000 { - compatible = "samsung,s5pv210-keypad"; - reg = <0x100A0000 0x100>; - interrupts = ; - clocks = <&clock CLK_KEYIF>; - clock-names = "keypad"; - status = "disabled"; - }; - - sdhci_0: sdhci@12510000 { - compatible = "samsung,exynos4210-sdhci"; - reg = <0x12510000 0x100>; - interrupts = ; - clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>; - clock-names = "hsmmc", "mmc_busclk.2"; - status = "disabled"; - }; - - sdhci_1: sdhci@12520000 { - compatible = "samsung,exynos4210-sdhci"; - reg = <0x12520000 0x100>; - interrupts = ; - clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>; - clock-names = "hsmmc", "mmc_busclk.2"; - status = "disabled"; - }; - - sdhci_2: sdhci@12530000 { - compatible = "samsung,exynos4210-sdhci"; - reg = <0x12530000 0x100>; - interrupts = ; - clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>; - clock-names = "hsmmc", "mmc_busclk.2"; - status = "disabled"; - }; - - sdhci_3: sdhci@12540000 { - compatible = "samsung,exynos4210-sdhci"; - reg = <0x12540000 0x100>; - interrupts = ; - clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>; - clock-names = "hsmmc", "mmc_busclk.2"; - status = "disabled"; - }; - - exynos_usbphy: exynos-usbphy@125b0000 { - compatible = "samsung,exynos4210-usb2-phy"; - reg = <0x125B0000 0x100>; - samsung,pmureg-phandle = <&pmu_system_controller>; - clocks = <&clock CLK_USB_DEVICE>, <&clock CLK_XUSBXTI>; - clock-names = "phy", "ref"; - #phy-cells = <1>; - status = "disabled"; - }; - - hsotg: hsotg@12480000 { - compatible = "samsung,s3c6400-hsotg"; - reg = <0x12480000 0x20000>; - interrupts = ; - clocks = <&clock CLK_USB_DEVICE>; - clock-names = "otg"; - phys = <&exynos_usbphy 0>; - phy-names = "usb2-phy"; - status = "disabled"; - }; - - ehci: ehci@12580000 { - compatible = "samsung,exynos4210-ehci"; - reg = <0x12580000 0x100>; - interrupts = ; - clocks = <&clock CLK_USB_HOST>; - clock-names = "usbhost"; - status = "disabled"; - phys = <&exynos_usbphy 1>, <&exynos_usbphy 2>, <&exynos_usbphy 3>; - phy-names = "host", "hsic0", "hsic1"; - }; - - ohci: ohci@12590000 { - compatible = "samsung,exynos4210-ohci"; - reg = <0x12590000 0x100>; - interrupts = ; - clocks = <&clock CLK_USB_HOST>; - clock-names = "usbhost"; - status = "disabled"; - phys = <&exynos_usbphy 1>; - phy-names = "host"; - }; - - gpu: gpu@13000000 { - compatible = "samsung,exynos4210-mali", "arm,mali-400"; - reg = <0x13000000 0x10000>; - /* - * CLK_G3D is not actually bus clock but a IP-level clock. - * The bus clock is not described in hardware manual. - */ - clocks = <&clock CLK_G3D>, - <&clock CLK_SCLK_G3D>; - clock-names = "bus", "core"; - power-domains = <&pd_g3d>; - status = "disabled"; - }; - - i2s1: i2s@13960000 { - compatible = "samsung,s3c6410-i2s"; - reg = <0x13960000 0x100>; - clocks = <&clock CLK_I2S1>; - clock-names = "iis"; - #clock-cells = <1>; - clock-output-names = "i2s_cdclk1"; - dmas = <&pdma1 12>, <&pdma1 11>; - dma-names = "tx", "rx"; - #sound-dai-cells = <1>; - status = "disabled"; - }; - - i2s2: i2s@13970000 { - compatible = "samsung,s3c6410-i2s"; - reg = <0x13970000 0x100>; - clocks = <&clock CLK_I2S2>; - clock-names = "iis"; - #clock-cells = <1>; - clock-output-names = "i2s_cdclk2"; - dmas = <&pdma0 14>, <&pdma0 13>; - dma-names = "tx", "rx"; - #sound-dai-cells = <1>; - status = "disabled"; - }; - - mfc: codec@13400000 { - compatible = "samsung,mfc-v5"; - reg = <0x13400000 0x10000>; - interrupts = ; - power-domains = <&pd_mfc>; - clocks = <&clock CLK_MFC>, <&clock CLK_SCLK_MFC>; - clock-names = "mfc", "sclk_mfc"; - iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>; - iommu-names = "left", "right"; - }; - - serial_0: serial@13800000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x13800000 0x100>; - interrupts = ; - clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; - clock-names = "uart", "clk_uart_baud0"; - dmas = <&pdma0 15>, <&pdma0 16>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - serial_1: serial@13810000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x13810000 0x100>; - interrupts = ; - clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>; - clock-names = "uart", "clk_uart_baud0"; - dmas = <&pdma1 15>, <&pdma1 16>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - serial_2: serial@13820000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x13820000 0x100>; - interrupts = ; - clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; - clock-names = "uart", "clk_uart_baud0"; - dmas = <&pdma0 17>, <&pdma0 18>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - serial_3: serial@13830000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x13830000 0x100>; - interrupts = ; - clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>; - clock-names = "uart", "clk_uart_baud0"; - dmas = <&pdma1 17>, <&pdma1 18>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c_0: i2c@13860000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x13860000 0x100>; - interrupts = ; - clocks = <&clock CLK_I2C0>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_bus>; - status = "disabled"; - }; - - i2c_1: i2c@13870000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x13870000 0x100>; - interrupts = ; - clocks = <&clock CLK_I2C1>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_bus>; - status = "disabled"; - }; - - i2c_2: i2c@13880000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x13880000 0x100>; - interrupts = ; - clocks = <&clock CLK_I2C2>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_bus>; - status = "disabled"; - }; - - i2c_3: i2c@13890000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x13890000 0x100>; - interrupts = ; - clocks = <&clock CLK_I2C3>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_bus>; - status = "disabled"; - }; - - i2c_4: i2c@138a0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x138A0000 0x100>; - interrupts = ; - clocks = <&clock CLK_I2C4>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_bus>; - status = "disabled"; - }; - - i2c_5: i2c@138b0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x138B0000 0x100>; - interrupts = ; - clocks = <&clock CLK_I2C5>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c5_bus>; - status = "disabled"; - }; - - i2c_6: i2c@138c0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x138C0000 0x100>; - interrupts = ; - clocks = <&clock CLK_I2C6>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c6_bus>; - status = "disabled"; - }; - - i2c_7: i2c@138d0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x138D0000 0x100>; - interrupts = ; - clocks = <&clock CLK_I2C7>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c7_bus>; - status = "disabled"; - }; - - i2c_8: i2c@138e0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-hdmiphy-i2c"; - reg = <0x138E0000 0x100>; - interrupts = ; - clocks = <&clock CLK_I2C_HDMI>; - clock-names = "i2c"; - status = "disabled"; - - hdmi_i2c_phy: hdmiphy@38 { - compatible = "exynos4210-hdmiphy"; - reg = <0x38>; - }; - }; - - spi_0: spi@13920000 { - compatible = "samsung,exynos4210-spi"; - reg = <0x13920000 0x100>; - interrupts = ; - dmas = <&pdma0 7>, <&pdma0 6>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>; - clock-names = "spi", "spi_busclk0"; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_bus>; - status = "disabled"; - }; - - spi_1: spi@13930000 { - compatible = "samsung,exynos4210-spi"; - reg = <0x13930000 0x100>; - interrupts = ; - dmas = <&pdma1 7>, <&pdma1 6>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>; - clock-names = "spi", "spi_busclk0"; - pinctrl-names = "default"; - pinctrl-0 = <&spi1_bus>; - status = "disabled"; - }; - - spi_2: spi@13940000 { - compatible = "samsung,exynos4210-spi"; - reg = <0x13940000 0x100>; - interrupts = ; - dmas = <&pdma0 9>, <&pdma0 8>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>; - clock-names = "spi", "spi_busclk0"; - pinctrl-names = "default"; - pinctrl-0 = <&spi2_bus>; - status = "disabled"; - }; - - pwm: pwm@139d0000 { - compatible = "samsung,exynos4210-pwm"; - reg = <0x139D0000 0x1000>; - interrupts = , - , - , - , - ; - clocks = <&clock CLK_PWM>; - clock-names = "timers"; - #pwm-cells = <3>; - status = "disabled"; - }; - - amba: amba { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&gic>; - ranges; - - pdma0: pdma@12680000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x12680000 0x1000>; - interrupts = ; - clocks = <&clock CLK_PDMA0>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; - }; - - pdma1: pdma@12690000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x12690000 0x1000>; - interrupts = ; - clocks = <&clock CLK_PDMA1>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; - }; - - mdma1: mdma@12850000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x12850000 0x1000>; - interrupts = ; - clocks = <&clock CLK_MDMA>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <1>; - }; - }; - - fimd: fimd@11c00000 { - compatible = "samsung,exynos4210-fimd"; - interrupt-parent = <&combiner>; - reg = <0x11c00000 0x20000>; - interrupt-names = "fifo", "vsync", "lcd_sys"; - interrupts = <11 0>, <11 1>, <11 2>; - clocks = <&clock CLK_SCLK_FIMD0>, <&clock CLK_FIMD0>; - clock-names = "sclk_fimd", "fimd"; - power-domains = <&pd_lcd0>; - iommus = <&sysmmu_fimd0>; - samsung,sysreg = <&sys_reg>; - status = "disabled"; - }; - - tmu: tmu@100c0000 { - interrupt-parent = <&combiner>; - reg = <0x100C0000 0x100>; - interrupts = <2 4>; - status = "disabled"; - #thermal-sensor-cells = <0>; - }; - - jpeg_codec: jpeg-codec@11840000 { - compatible = "samsung,exynos4210-jpeg"; - reg = <0x11840000 0x1000>; - interrupts = ; - clocks = <&clock CLK_JPEG>; - clock-names = "jpeg"; - power-domains = <&pd_cam>; - iommus = <&sysmmu_jpeg>; - }; - - rotator: rotator@12810000 { - compatible = "samsung,exynos4210-rotator"; - reg = <0x12810000 0x64>; - interrupts = ; - clocks = <&clock CLK_ROTATOR>; - clock-names = "rotator"; - iommus = <&sysmmu_rotator>; - }; - - hdmi: hdmi@12d00000 { - compatible = "samsung,exynos4210-hdmi"; - reg = <0x12D00000 0x70000>; - interrupts = ; - clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", - "sclk_hdmiphy", "mout_hdmi"; - clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>, - <&clock CLK_SCLK_PIXEL>, - <&clock CLK_SCLK_HDMIPHY>, - <&clock CLK_MOUT_HDMI>; - phy = <&hdmi_i2c_phy>; - power-domains = <&pd_tv>; - samsung,syscon-phandle = <&pmu_system_controller>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - hdmicec: cec@100b0000 { - compatible = "samsung,s5p-cec"; - reg = <0x100B0000 0x200>; - interrupts = ; - clocks = <&clock CLK_HDMI_CEC>; - clock-names = "hdmicec"; - samsung,syscon-phandle = <&pmu_system_controller>; - hdmi-phandle = <&hdmi>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_cec>; - status = "disabled"; - }; - - mixer: mixer@12c10000 { - compatible = "samsung,exynos4210-mixer"; - interrupts = ; - reg = <0x12C10000 0x2100>, <0x12c00000 0x300>; - power-domains = <&pd_tv>; - iommus = <&sysmmu_tv>; - status = "disabled"; - }; - - ppmu_dmc0: ppmu_dmc0@106a0000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x106a0000 0x2000>; - clocks = <&clock CLK_PPMUDMC0>; - clock-names = "ppmu"; - status = "disabled"; - }; - - ppmu_dmc1: ppmu_dmc1@106b0000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x106b0000 0x2000>; - clocks = <&clock CLK_PPMUDMC1>; - clock-names = "ppmu"; - status = "disabled"; - }; - - ppmu_cpu: ppmu_cpu@106c0000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x106c0000 0x2000>; - clocks = <&clock CLK_PPMUCPU>; - clock-names = "ppmu"; - status = "disabled"; - }; - - ppmu_rightbus: ppmu_rightbus@112a0000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x112a0000 0x2000>; - clocks = <&clock CLK_PPMURIGHT>; - clock-names = "ppmu"; - status = "disabled"; - }; - - ppmu_leftbus: ppmu_leftbus0@116a0000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x116a0000 0x2000>; - clocks = <&clock CLK_PPMULEFT>; - clock-names = "ppmu"; - status = "disabled"; - }; - - ppmu_camif: ppmu_camif@11ac0000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x11ac0000 0x2000>; - clocks = <&clock CLK_PPMUCAMIF>; - clock-names = "ppmu"; - status = "disabled"; - }; - - ppmu_lcd0: ppmu_lcd0@11e40000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x11e40000 0x2000>; - clocks = <&clock CLK_PPMULCD0>; - clock-names = "ppmu"; - status = "disabled"; - }; - - ppmu_fsys: ppmu_g3d@12630000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x12630000 0x2000>; - status = "disabled"; - }; - - ppmu_image: ppmu_image@12aa0000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x12aa0000 0x2000>; - clocks = <&clock CLK_PPMUIMAGE>; - clock-names = "ppmu"; - status = "disabled"; - }; - - ppmu_tv: ppmu_tv@12e40000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x12e40000 0x2000>; - clocks = <&clock CLK_PPMUTV>; - clock-names = "ppmu"; - status = "disabled"; - }; - - ppmu_g3d: ppmu_g3d@13220000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x13220000 0x2000>; - clocks = <&clock CLK_PPMUG3D>; - clock-names = "ppmu"; - status = "disabled"; - }; - - ppmu_mfc_left: ppmu_mfc_left@13660000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x13660000 0x2000>; - clocks = <&clock CLK_PPMUMFC_L>; - clock-names = "ppmu"; - status = "disabled"; - }; - - ppmu_mfc_right: ppmu_mfc_right@13670000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x13670000 0x2000>; - clocks = <&clock CLK_PPMUMFC_R>; - clock-names = "ppmu"; - status = "disabled"; - }; - - sysmmu_mfc_l: sysmmu@13620000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x13620000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <5 5>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>; - power-domains = <&pd_mfc>; - #iommu-cells = <0>; - }; - - sysmmu_mfc_r: sysmmu@13630000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x13630000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <5 6>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>; - power-domains = <&pd_mfc>; - #iommu-cells = <0>; - }; - - sysmmu_tv: sysmmu@12e20000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x12E20000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <5 4>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>; - power-domains = <&pd_tv>; - #iommu-cells = <0>; - }; - - sysmmu_fimc0: sysmmu@11a20000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x11A20000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <4 2>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_FIMC0>, <&clock CLK_FIMC0>; - power-domains = <&pd_cam>; - #iommu-cells = <0>; - }; - - sysmmu_fimc1: sysmmu@11a30000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x11A30000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <4 3>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_FIMC1>, <&clock CLK_FIMC1>; - power-domains = <&pd_cam>; - #iommu-cells = <0>; - }; - - sysmmu_fimc2: sysmmu@11a40000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x11A40000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <4 4>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_FIMC2>, <&clock CLK_FIMC2>; - power-domains = <&pd_cam>; - #iommu-cells = <0>; - }; - - sysmmu_fimc3: sysmmu@11a50000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x11A50000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <4 5>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_FIMC3>, <&clock CLK_FIMC3>; - power-domains = <&pd_cam>; - #iommu-cells = <0>; - }; - - sysmmu_jpeg: sysmmu@11a60000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x11A60000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <4 6>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>; - power-domains = <&pd_cam>; - #iommu-cells = <0>; - }; - - sysmmu_rotator: sysmmu@12a30000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x12A30000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <5 0>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_ROTATOR>, - <&clock CLK_ROTATOR>; - #iommu-cells = <0>; - }; - - sysmmu_fimd0: sysmmu@11e20000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x11E20000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <5 2>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_FIMD0>, <&clock CLK_FIMD0>; - power-domains = <&pd_lcd0>; - #iommu-cells = <0>; - }; - - sss: sss@10830000 { - compatible = "samsung,exynos4210-secss"; - reg = <0x10830000 0x300>; - interrupts = ; - clocks = <&clock CLK_SSS>; - clock-names = "secss"; - }; - - prng: rng@10830400 { - compatible = "samsung,exynos4-rng"; - reg = <0x10830400 0x200>; - clocks = <&clock CLK_SSS>; - clock-names = "secss"; - }; - }; -}; - -#include "exynos-syscon-restart.dtsi" diff --git a/sys/gnu/dts/arm/exynos4210-origen.dts b/sys/gnu/dts/arm/exynos4210-origen.dts deleted file mode 100644 index 0d1e1a9c2f6..00000000000 --- a/sys/gnu/dts/arm/exynos4210-origen.dts +++ /dev/null @@ -1,343 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's Exynos4210 based Origen board device tree source - * - * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * Copyright (c) 2010-2011 Linaro Ltd. - * www.linaro.org - * - * Device tree source file for Insignal's Origen board which is based on - * Samsung's Exynos4210 SoC. - */ - -/dts-v1/; -#include "exynos4210.dtsi" -#include -#include -#include "exynos-mfc-reserved-memory.dtsi" - -/ { - model = "Insignal Origen evaluation board based on Exynos4210"; - compatible = "insignal,origen", "samsung,exynos4210", "samsung,exynos4"; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x10000000 - 0x50000000 0x10000000 - 0x60000000 0x10000000 - 0x70000000 0x10000000>; - }; - - chosen { - bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M init=/linuxrc"; - stdout-path = "serial2:115200n8"; - }; - - mmc_reg: voltage-regulator { - compatible = "regulator-fixed"; - regulator-name = "VMEM_VDD_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpx1 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - gpio_keys { - compatible = "gpio-keys"; - - up { - label = "Up"; - gpios = <&gpx2 0 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - - down { - label = "Down"; - gpios = <&gpx2 1 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - - back { - label = "Back"; - gpios = <&gpx1 7 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - - home { - label = "Home"; - gpios = <&gpx1 6 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - - menu { - label = "Menu"; - gpios = <&gpx1 5 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - status { - gpios = <&gpx1 3 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - }; - }; - - fixed-rate-clocks { - xxti { - compatible = "samsung,clock-xxti"; - clock-frequency = <0>; - }; - - xusbxti { - compatible = "samsung,clock-xusbxti"; - clock-frequency = <24000000>; - }; - }; - - display-timings { - native-mode = <&timing0>; - timing0: timing { - clock-frequency = <47500000>; - hactive = <1024>; - vactive = <600>; - hfront-porch = <64>; - hback-porch = <16>; - hsync-len = <48>; - vback-porch = <64>; - vfront-porch = <16>; - vsync-len = <3>; - }; - }; -}; - -&cpu0 { - cpu0-supply = <&buck1_reg>; -}; - -&exynos_usbphy { - status = "okay"; -}; - -&fimd { - pinctrl-0 = <&lcd_en &lcd_clk &lcd_data24 &pwm0_out>; - pinctrl-names = "default"; - status = "okay"; -}; - -&gpu { - mali-supply = <&buck3_reg>; - status = "okay"; -}; - -&hsotg { - vusb_d-supply = <&ldo3_reg>; - vusb_a-supply = <&ldo8_reg>; - dr_mode = "peripheral"; - status = "okay"; -}; - -&i2c_0 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <20000>; - pinctrl-0 = <&i2c0_bus>; - pinctrl-names = "default"; - - max8997_pmic@66 { - compatible = "maxim,max8997-pmic"; - reg = <0x66>; - interrupt-parent = <&gpx0>; - interrupts = <4 IRQ_TYPE_NONE>, <3 IRQ_TYPE_NONE>; - pinctrl-names = "default"; - pinctrl-0 = <&max8997_irq>; - - max8997,pmic-buck1-dvs-voltage = <1350000>; - max8997,pmic-buck2-dvs-voltage = <1100000>; - max8997,pmic-buck5-dvs-voltage = <1200000>; - - regulators { - ldo1_reg: LDO1 { - regulator-name = "VDD_ABB_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo2_reg: LDO2 { - regulator-name = "VDD_ALIVE_1.1V"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - ldo3_reg: LDO3 { - regulator-name = "VMIPI_1.1V"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - }; - - ldo4_reg: LDO4 { - regulator-name = "VDD_RTC_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo6_reg: LDO6 { - regulator-name = "VMIPI_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo7_reg: LDO7 { - regulator-name = "VDD_AUD_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo8_reg: LDO8 { - regulator-name = "VADC_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo9_reg: LDO9 { - regulator-name = "DVDD_SWB_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - ldo10_reg: LDO10 { - regulator-name = "VDD_PLL_1.1V"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - ldo11_reg: LDO11 { - regulator-name = "VDD_AUD_3V"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - ldo14_reg: LDO14 { - regulator-name = "AVDD18_SWB_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo17_reg: LDO17 { - regulator-name = "VDD_SWB_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo21_reg: LDO21 { - regulator-name = "VDD_MIF_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - buck1_reg: BUCK1 { - /* - * HACK: The real name is VDD_ARM_1.2V, - * but exynos-cpufreq does not support - * DT-based regulator lookup yet. - */ - regulator-name = "vdd_arm"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - - buck2_reg: BUCK2 { - regulator-name = "VDD_INT_1.1V"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - regulator-boot-on; - }; - - buck3_reg: BUCK3 { - regulator-name = "VDD_G3D_1.1V"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1100000>; - }; - - buck5_reg: BUCK5 { - regulator-name = "VDDQ_M1M2_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - buck7_reg: BUCK7 { - regulator-name = "VDD_LCD_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; -}; - -&pinctrl_1 { - max8997_irq: max8997-irq { - samsung,pins = "gpx0-3", "gpx0-4"; - samsung,pin-pud = ; - }; -}; - -&sdhci_0 { - bus-width = <4>; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_cd>; - pinctrl-names = "default"; - vmmc-supply = <&mmc_reg>; - status = "okay"; -}; - -&sdhci_2 { - bus-width = <4>; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sd2_cd>; - pinctrl-names = "default"; - vmmc-supply = <&mmc_reg>; - status = "okay"; -}; - -&serial_0 { - status = "okay"; -}; - -&serial_1 { - status = "okay"; -}; - -&serial_2 { - status = "okay"; -}; - -&serial_3 { - status = "okay"; -}; - -&rtc { - status = "okay"; -}; - -&tmu { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/exynos4210-pinctrl.dtsi b/sys/gnu/dts/arm/exynos4210-pinctrl.dtsi deleted file mode 100644 index 520c5934a8d..00000000000 --- a/sys/gnu/dts/arm/exynos4210-pinctrl.dtsi +++ /dev/null @@ -1,863 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's Exynos4210 SoC pin-mux and pin-config device tree source - * - * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * Copyright (c) 2011-2012 Linaro Ltd. - * www.linaro.org - * - * Samsung's Exynos4210 SoC pin-mux and pin-config optiosn are listed as device - * tree nodes are listed in this file. - */ - -#include - -&pinctrl_0 { - gpa0: gpa0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpa1: gpa1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpb: gpb { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc0: gpc0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc1: gpc1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpd0: gpd0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpd1: gpd1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpe0: gpe0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpe1: gpe1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpe2: gpe2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpe3: gpe3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpe4: gpe4 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf0: gpf0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf1: gpf1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf2: gpf2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf3: gpf3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - uart0_data: uart0-data { - samsung,pins = "gpa0-0", "gpa0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart0_fctl: uart0-fctl { - samsung,pins = "gpa0-2", "gpa0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart1_data: uart1-data { - samsung,pins = "gpa0-4", "gpa0-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart1_fctl: uart1-fctl { - samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c2_bus: i2c2-bus { - samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart2_data: uart2-data { - samsung,pins = "gpa1-0", "gpa1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart2_fctl: uart2-fctl { - samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart_audio_a: uart-audio-a { - samsung,pins = "gpa1-0", "gpa1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c3_bus: i2c3-bus { - samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart3_data: uart3-data { - samsung,pins = "gpa1-4", "gpa1-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart_audio_b: uart-audio-b { - samsung,pins = "gpa1-4", "gpa1-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spi0_bus: spi0-bus { - samsung,pins = "gpb-0", "gpb-2", "gpb-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c4_bus: i2c4-bus { - samsung,pins = "gpb-2", "gpb-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spi1_bus: spi1-bus { - samsung,pins = "gpb-4", "gpb-6", "gpb-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c5_bus: i2c5-bus { - samsung,pins = "gpb-6", "gpb-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2s1_bus: i2s1-bus { - samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", - "gpc0-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pcm1_bus: pcm1-bus { - samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", - "gpc0-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - ac97_bus: ac97-bus { - samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", - "gpc0-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2s2_bus: i2s2-bus { - samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", - "gpc1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pcm2_bus: pcm2-bus { - samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", - "gpc1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spdif_bus: spdif-bus { - samsung,pins = "gpc1-0", "gpc1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c6_bus: i2c6-bus { - samsung,pins = "gpc1-3", "gpc1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spi2_bus: spi2-bus { - samsung,pins = "gpc1-1", "gpc1-2", "gpc1-3", "gpc1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c7_bus: i2c7-bus { - samsung,pins = "gpd0-2", "gpd0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c0_bus: i2c0-bus { - samsung,pins = "gpd1-0", "gpd1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c1_bus: i2c1-bus { - samsung,pins = "gpd1-2", "gpd1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm0_out: pwm0-out { - samsung,pins = "gpd0-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm1_out: pwm1-out { - samsung,pins = "gpd0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm2_out: pwm2-out { - samsung,pins = "gpd0-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm3_out: pwm3-out { - samsung,pins = "gpd0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - lcd_ctrl: lcd-ctrl { - samsung,pins = "gpd0-0", "gpd0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - lcd_sync: lcd-sync { - samsung,pins = "gpf0-0", "gpf0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - lcd_en: lcd-en { - samsung,pins = "gpe3-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - lcd_clk: lcd-clk { - samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - lcd_data16: lcd-data-width16 { - samsung,pins = "gpf0-7", "gpf1-0", "gpf1-1", "gpf1-2", - "gpf1-3", "gpf1-6", "gpf1-7", "gpf2-0", - "gpf2-1", "gpf2-2", "gpf2-3", "gpf2-7", - "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - lcd_data18: lcd-data-width18 { - samsung,pins = "gpf0-6", "gpf0-7", "gpf1-0", "gpf1-1", - "gpf1-2", "gpf1-3", "gpf1-6", "gpf1-7", - "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3", - "gpf2-6", "gpf2-7", "gpf3-0", "gpf3-1", - "gpf3-2", "gpf3-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - lcd_data24: lcd-data-width24 { - samsung,pins = "gpf0-4", "gpf0-5", "gpf0-6", "gpf0-7", - "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3", - "gpf1-4", "gpf1-5", "gpf1-6", "gpf1-7", - "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3", - "gpf2-4", "gpf2-5", "gpf2-6", "gpf2-7", - "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pinctrl_1 { - gpj0: gpj0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpj1: gpj1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpk0: gpk0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpk1: gpk1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpk2: gpk2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpk3: gpk3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpl0: gpl0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpl1: gpl1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpl2: gpl2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpy0: gpy0 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy1: gpy1 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy2: gpy2 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy3: gpy3 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy4: gpy4 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy5: gpy5 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy6: gpy6 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpx0: gpx0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - interrupt-parent = <&gic>; - interrupts = , - , - , - , - , - , - , - ; - #interrupt-cells = <2>; - }; - - gpx1: gpx1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - interrupt-parent = <&gic>; - interrupts = , - , - , - , - , - , - , - ; - #interrupt-cells = <2>; - }; - - gpx2: gpx2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpx3: gpx3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - sd0_clk: sd0-clk { - samsung,pins = "gpk0-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_cmd: sd0-cmd { - samsung,pins = "gpk0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_cd: sd0-cd { - samsung,pins = "gpk0-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus1: sd0-bus-width1 { - samsung,pins = "gpk0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus4: sd0-bus-width4 { - samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus8: sd0-bus-width8 { - samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd4_clk: sd4-clk { - samsung,pins = "gpk0-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd4_cmd: sd4-cmd { - samsung,pins = "gpk0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd4_cd: sd4-cd { - samsung,pins = "gpk0-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd4_bus1: sd4-bus-width1 { - samsung,pins = "gpk0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd4_bus4: sd4-bus-width4 { - samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd4_bus8: sd4-bus-width8 { - samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_clk: sd1-clk { - samsung,pins = "gpk1-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_cmd: sd1-cmd { - samsung,pins = "gpk1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_cd: sd1-cd { - samsung,pins = "gpk1-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_bus1: sd1-bus-width1 { - samsung,pins = "gpk1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_bus4: sd1-bus-width4 { - samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_clk: sd2-clk { - samsung,pins = "gpk2-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_cmd: sd2-cmd { - samsung,pins = "gpk2-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_cd: sd2-cd { - samsung,pins = "gpk2-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_bus1: sd2-bus-width1 { - samsung,pins = "gpk2-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_bus4: sd2-bus-width4 { - samsung,pins = "gpk2-3", "gpk2-4", "gpk2-5", "gpk2-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_bus8: sd2-bus-width8 { - samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd3_clk: sd3-clk { - samsung,pins = "gpk3-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd3_cmd: sd3-cmd { - samsung,pins = "gpk3-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd3_cd: sd3-cd { - samsung,pins = "gpk3-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd3_bus1: sd3-bus-width1 { - samsung,pins = "gpk3-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd3_bus4: sd3-bus-width4 { - samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - eint0: ext-int0 { - samsung,pins = "gpx0-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - eint8: ext-int8 { - samsung,pins = "gpx1-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - eint15: ext-int15 { - samsung,pins = "gpx1-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - eint16: ext-int16 { - samsung,pins = "gpx2-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - eint31: ext-int31 { - samsung,pins = "gpx3-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_port_a_io: cam-port-a-io { - samsung,pins = "gpj0-0", "gpj0-1", "gpj0-2", "gpj0-3", - "gpj0-4", "gpj0-5", "gpj0-6", "gpj0-7", - "gpj1-0", "gpj1-1", "gpj1-2", "gpj1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_port_a_clk_active: cam-port-a-clk-active { - samsung,pins = "gpj1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_port_a_clk_idle: cam-port-a-clk-idle { - samsung,pins = "gpj1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - hdmi_cec: hdmi-cec { - samsung,pins = "gpx3-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pinctrl_2 { - gpz: gpz { - gpio-controller; - #gpio-cells = <2>; - }; - - i2s0_bus: i2s0-bus { - samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", - "gpz-4", "gpz-5", "gpz-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pcm0_bus: pcm0-bus { - samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", - "gpz-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; diff --git a/sys/gnu/dts/arm/exynos4210-smdkv310.dts b/sys/gnu/dts/arm/exynos4210-smdkv310.dts deleted file mode 100644 index 77fc11e593a..00000000000 --- a/sys/gnu/dts/arm/exynos4210-smdkv310.dts +++ /dev/null @@ -1,200 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's Exynos4210 based SMDKV310 board device tree source - * - * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * Copyright (c) 2010-2011 Linaro Ltd. - * www.linaro.org - * - * Device tree source file for Samsung's SMDKV310 board which is based on - * Samsung's Exynos4210 SoC. - */ - -/dts-v1/; -#include "exynos4210.dtsi" -#include -#include "exynos-mfc-reserved-memory.dtsi" - -/ { - model = "Samsung smdkv310 evaluation board based on Exynos4210"; - compatible = "samsung,smdkv310", "samsung,exynos4210", "samsung,exynos4"; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x80000000>; - }; - - chosen { - bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M init=/linuxrc"; - stdout-path = "serial1:115200n8"; - }; - - fixed-rate-clocks { - xxti { - compatible = "samsung,clock-xxti"; - clock-frequency = <12000000>; - }; - - xusbxti { - compatible = "samsung,clock-xusbxti"; - clock-frequency = <24000000>; - }; - }; -}; - -&i2c_0 { - #address-cells = <1>; - #size-cells = <0>; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <100000>; - status = "okay"; - - eeprom@50 { - compatible = "samsung,24ad0xd1"; - reg = <0x50>; - }; - - eeprom@52 { - compatible = "samsung,24ad0xd1"; - reg = <0x52>; - }; -}; - -&keypad { - samsung,keypad-num-rows = <2>; - samsung,keypad-num-columns = <8>; - linux,keypad-no-autorepeat; - wakeup-source; - pinctrl-names = "default"; - pinctrl-0 = <&keypad_rows &keypad_cols>; - status = "okay"; - - key_1 { - keypad,row = <0>; - keypad,column = <3>; - linux,code = <2>; - }; - - key_2 { - keypad,row = <0>; - keypad,column = <4>; - linux,code = <3>; - }; - - key_3 { - keypad,row = <0>; - keypad,column = <5>; - linux,code = <4>; - }; - - key_4 { - keypad,row = <0>; - keypad,column = <6>; - linux,code = <5>; - }; - - key_5 { - keypad,row = <0>; - keypad,column = <7>; - linux,code = <6>; - }; - - key_a { - keypad,row = <1>; - keypad,column = <3>; - linux,code = <30>; - }; - - key_b { - keypad,row = <1>; - keypad,column = <4>; - linux,code = <48>; - }; - - key_c { - keypad,row = <1>; - keypad,column = <5>; - linux,code = <46>; - }; - - key_d { - keypad,row = <1>; - keypad,column = <6>; - linux,code = <32>; - }; - - key_e { - keypad,row = <1>; - keypad,column = <7>; - linux,code = <18>; - }; -}; - -&pinctrl_1 { - keypad_rows: keypad-rows { - samsung,pins = "gpx2-0", "gpx2-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - keypad_cols: keypad-cols { - samsung,pins = "gpx1-0", "gpx1-1", "gpx1-2", "gpx1-3", - "gpx1-4", "gpx1-5", "gpx1-6", "gpx1-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&sdhci_2 { - bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; - status = "okay"; -}; - -&serial_0 { - status = "okay"; -}; - -&serial_1 { - status = "okay"; -}; - -&serial_2 { - status = "okay"; -}; - -&serial_3 { - status = "okay"; -}; - -&spi_2 { - cs-gpios = <&gpc1 2 GPIO_ACTIVE_HIGH>; - status = "okay"; - - w25x80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "w25x80"; - reg = <0>; - spi-max-frequency = <1000000>; - - controller-data { - samsung,spi-feedback-delay = <0>; - }; - - partition@0 { - label = "U-Boot"; - reg = <0x0 0x40000>; - read-only; - }; - - partition@40000 { - label = "Kernel"; - reg = <0x40000 0xc0000>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/exynos4210-trats.dts b/sys/gnu/dts/arm/exynos4210-trats.dts deleted file mode 100644 index 7c39dd1c4d3..00000000000 --- a/sys/gnu/dts/arm/exynos4210-trats.dts +++ /dev/null @@ -1,492 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's Exynos4210 based Trats board device tree source - * - * Copyright (c) 2012 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Device tree source file for Samsung's Trats board which is based on - * Samsung's Exynos4210 SoC. - */ - -/dts-v1/; -#include "exynos4210.dtsi" -#include - -/ { - model = "Samsung Trats based on Exynos4210"; - compatible = "samsung,trats", "samsung,exynos4210", "samsung,exynos4"; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x10000000 - 0x50000000 0x10000000 - 0x60000000 0x10000000 - 0x70000000 0x10000000>; - }; - - chosen { - bootargs = "root=/dev/mmcblk0p5 rootwait earlyprintk panic=5"; - stdout-path = "serial2:115200n8"; - }; - - regulators { - compatible = "simple-bus"; - - vemmc_reg: regulator-0 { - compatible = "regulator-fixed"; - regulator-name = "VMEM_VDD_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpk0 2 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - tsp_reg: regulator-1 { - compatible = "regulator-fixed"; - regulator-name = "TSP_FIXED_VOLTAGES"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpl0 3 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - cam_af_28v_reg: regulator-2 { - compatible = "regulator-fixed"; - regulator-name = "8M_AF_2.8V_EN"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpk1 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - cam_io_en_reg: regulator-3 { - compatible = "regulator-fixed"; - regulator-name = "CAM_IO_EN"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpe2 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - cam_io_12v_reg: regulator-4 { - compatible = "regulator-fixed"; - regulator-name = "8M_1.2V_EN"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - gpio = <&gpe2 5 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vt_core_15v_reg: regulator-5 { - compatible = "regulator-fixed"; - regulator-name = "VT_CORE_1.5V"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - gpio = <&gpe2 2 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - vol-down-key { - gpios = <&gpx2 1 GPIO_ACTIVE_LOW>; - linux,code = <114>; - label = "volume down"; - debounce-interval = <10>; - }; - - vol-up-key { - gpios = <&gpx2 0 GPIO_ACTIVE_LOW>; - linux,code = <115>; - label = "volume up"; - debounce-interval = <10>; - }; - - power-key { - gpios = <&gpx2 7 GPIO_ACTIVE_LOW>; - linux,code = <116>; - label = "power"; - debounce-interval = <10>; - wakeup-source; - }; - - ok-key { - gpios = <&gpx3 5 GPIO_ACTIVE_LOW>; - linux,code = <352>; - label = "ok"; - debounce-interval = <10>; - }; - }; - - fixed-rate-clocks { - xxti { - compatible = "samsung,clock-xxti"; - clock-frequency = <0>; - }; - - xusbxti { - compatible = "samsung,clock-xusbxti"; - clock-frequency = <24000000>; - }; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - cooling-maps { - map0 { - /* Corresponds to 800MHz at freq_table */ - cooling-device = <&cpu0 2 2>, <&cpu1 2 2>; - }; - map1 { - /* Corresponds to 200MHz at freq_table */ - cooling-device = <&cpu0 4 4>, <&cpu1 4 4>; - }; - }; - }; - }; - -}; - -&camera { - pinctrl-names = "default"; - pinctrl-0 = <>; - status = "okay"; -}; - -&cpu0 { - cpu0-supply = <&varm_breg>; -}; - -&dsi_0 { - vddcore-supply = <&vusb_reg>; - vddio-supply = <&vmipi_reg>; - samsung,burst-clock-frequency = <500000000>; - samsung,esc-clock-frequency = <20000000>; - samsung,pll-clock-frequency = <24000000>; - status = "okay"; - - panel@0 { - reg = <0>; - compatible = "samsung,s6e8aa0"; - vdd3-supply = <&vcclcd_reg>; - vci-supply = <&vlcd_reg>; - reset-gpios = <&gpy4 5 GPIO_ACTIVE_HIGH>; - power-on-delay= <50>; - reset-delay = <100>; - init-delay = <100>; - flip-horizontal; - flip-vertical; - panel-width-mm = <58>; - panel-height-mm = <103>; - - display-timings { - timing-0 { - clock-frequency = <57153600>; - hactive = <720>; - vactive = <1280>; - hfront-porch = <5>; - hback-porch = <5>; - hsync-len = <5>; - vfront-porch = <13>; - vback-porch = <1>; - vsync-len = <2>; - }; - }; - }; -}; - -&exynos_usbphy { - status = "okay"; - vbus-supply = <&safe1_sreg>; -}; - -&fimc_0 { - status = "okay"; - assigned-clocks = <&clock CLK_MOUT_FIMC0>, - <&clock CLK_SCLK_FIMC0>; - assigned-clock-parents = <&clock CLK_SCLK_MPLL>; - assigned-clock-rates = <0>, <160000000>; -}; - -&fimc_1 { - status = "okay"; - assigned-clocks = <&clock CLK_MOUT_FIMC1>, - <&clock CLK_SCLK_FIMC1>; - assigned-clock-parents = <&clock CLK_SCLK_MPLL>; - assigned-clock-rates = <0>, <160000000>; -}; - -&fimc_2 { - status = "okay"; - assigned-clocks = <&clock CLK_MOUT_FIMC2>, - <&clock CLK_SCLK_FIMC2>; - assigned-clock-parents = <&clock CLK_SCLK_MPLL>; - assigned-clock-rates = <0>, <160000000>; -}; - -&fimc_3 { - status = "okay"; - assigned-clocks = <&clock CLK_MOUT_FIMC3>, - <&clock CLK_SCLK_FIMC3>; - assigned-clock-parents = <&clock CLK_SCLK_MPLL>; - assigned-clock-rates = <0>, <160000000>; -}; - -&fimd { - status = "okay"; -}; - -&gpu { - status = "okay"; -}; - -&hsotg { - vusb_d-supply = <&vusb_reg>; - vusb_a-supply = <&vusbdac_reg>; - dr_mode = "peripheral"; - status = "okay"; -}; - -&i2c_3 { - samsung,i2c-sda-delay = <100>; - samsung,i2c-slave-addr = <0x10>; - samsung,i2c-max-bus-freq = <400000>; - pinctrl-0 = <&i2c3_bus>; - pinctrl-names = "default"; - status = "okay"; - - mms114-touchscreen@48 { - compatible = "melfas,mms114"; - reg = <0x48>; - interrupt-parent = <&gpx0>; - interrupts = <4 IRQ_TYPE_EDGE_FALLING>; - touchscreen-size-x = <720>; - touchscreen-size-y = <1280>; - avdd-supply = <&tsp_reg>; - vdd-supply = <&tsp_reg>; - }; -}; - -&i2c_5 { - samsung,i2c-sda-delay = <100>; - samsung,i2c-slave-addr = <0x10>; - samsung,i2c-max-bus-freq = <100000>; - pinctrl-0 = <&i2c5_bus>; - pinctrl-names = "default"; - status = "okay"; - - max8997_pmic@66 { - compatible = "maxim,max8997-pmic"; - interrupts-extended = <&gpx0 7 0>, <&gpx2 3 0>; - - reg = <0x66>; - interrupt-parent = <&gpx0>; - interrupts = <7 IRQ_TYPE_NONE>; - - max8997,pmic-buck1-uses-gpio-dvs; - max8997,pmic-buck2-uses-gpio-dvs; - max8997,pmic-buck5-uses-gpio-dvs; - - max8997,pmic-ignore-gpiodvs-side-effect; - max8997,pmic-buck125-default-dvs-idx = <0>; - - max8997,pmic-buck125-dvs-gpios = <&gpx0 5 GPIO_ACTIVE_HIGH>, - <&gpx0 6 GPIO_ACTIVE_HIGH>, - <&gpl0 0 GPIO_ACTIVE_HIGH>; - - max8997,pmic-buck1-dvs-voltage = <1350000>, <1300000>, - <1250000>, <1200000>, - <1150000>, <1100000>, - <1000000>, <950000>; - - max8997,pmic-buck2-dvs-voltage = <1100000>, <1000000>, - <950000>, <900000>, - <1100000>, <1000000>, - <950000>, <900000>; - - max8997,pmic-buck5-dvs-voltage = <1200000>, <1200000>, - <1200000>, <1200000>, - <1200000>, <1200000>, - <1200000>, <1200000>; - - regulators { - valive_reg: LDO2 { - regulator-name = "VALIVE_1.1V_C210"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - vusb_reg: LDO3 { - regulator-name = "VUSB_1.1V_C210"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - }; - - vmipi_reg: LDO4 { - regulator-name = "VMIPI_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vpda_reg: LDO6 { - regulator-name = "VCC_1.8V_PDA"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vcam_reg: LDO7 { - regulator-name = "CAM_ISP_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vusbdac_reg: LDO8 { - regulator-name = "VUSB+VDAC_3.3V_C210"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vccpda_reg: LDO9 { - regulator-name = "VCC_2.8V_PDA"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - vpll_reg: LDO10 { - regulator-name = "VPLL_1.1V_C210"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - vtcam_reg: LDO12 { - regulator-name = "VT_CAM_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vcclcd_reg: LDO13 { - regulator-name = "VCC_3.3V_LCD"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vlcd_reg: LDO15 { - regulator-name = "VLCD_2.2V"; - regulator-min-microvolt = <2200000>; - regulator-max-microvolt = <2200000>; - }; - - camsensor_reg: LDO16 { - regulator-name = "CAM_SENSOR_IO_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - tflash_reg: LDO17 { - regulator-name = "VTF_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - vddq_reg: LDO21 { - regulator-name = "VDDQ_M1M2_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - varm_breg: BUCK1 { - /* - * HACK: The real name is VARM_1.2V_C210, - * but exynos-cpufreq does not support - * DT-based regulator lookup yet. - */ - regulator-name = "vdd_arm"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - }; - - vint_breg: BUCK2 { - regulator-name = "VINT_1.1V_C210"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - camisp_breg: BUCK4 { - regulator-name = "CAM_ISP_CORE_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - vmem_breg: BUCK5 { - regulator-name = "VMEM_1.2V_C210"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - vccsub_breg: BUCK7 { - regulator-name = "VCC_SUB_2.0V"; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - regulator-always-on; - }; - - safe1_sreg: ESAFEOUT1 { - regulator-name = "SAFEOUT1"; - }; - - safe2_sreg: ESAFEOUT2 { - regulator-name = "SAFEOUT2"; - regulator-boot-on; - }; - }; - }; -}; - -&sdhci_0 { - bus-width = <8>; - non-removable; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus8>; - pinctrl-names = "default"; - vmmc-supply = <&vemmc_reg>; - status = "okay"; -}; - -&sdhci_2 { - bus-width = <4>; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4>; - pinctrl-names = "default"; - vmmc-supply = <&tflash_reg>; - cd-gpios = <&gpx3 4 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&serial_0 { - status = "okay"; -}; - -&serial_1 { - status = "okay"; -}; - -&serial_2 { - status = "okay"; -}; - -&serial_3 { - status = "okay"; -}; - -&tmu { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/exynos4210-universal_c210.dts b/sys/gnu/dts/arm/exynos4210-universal_c210.dts deleted file mode 100644 index a1bdf7830a8..00000000000 --- a/sys/gnu/dts/arm/exynos4210-universal_c210.dts +++ /dev/null @@ -1,605 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's Exynos4210 based Universal C210 board device tree source - * - * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Device tree source file for Samsung's Universal C210 board which is based on - * Samsung's Exynos4210 rev0 SoC. - */ - -/dts-v1/; -#include "exynos4210.dtsi" -#include - -/ { - model = "Samsung Universal C210 based on Exynos4210 rev0"; - compatible = "samsung,universal_c210", "samsung,exynos4210", "samsung,exynos4"; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x10000000 - 0x50000000 0x10000000>; - }; - - chosen { - bootargs = "root=/dev/mmcblk0p5 rw rootwait earlyprintk panic=5 maxcpus=1"; - stdout-path = "serial2:115200n8"; - }; - - - fixed-rate-clocks { - xxti { - compatible = "samsung,clock-xxti"; - clock-frequency = <0>; - }; - - xusbxti { - compatible = "samsung,clock-xusbxti"; - clock-frequency = <24000000>; - }; - }; - - vemmc_reg: voltage-regulator { - compatible = "regulator-fixed"; - regulator-name = "VMEM_VDD_2_8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpe1 3 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - gpio-keys { - compatible = "gpio-keys"; - - vol-up-key { - gpios = <&gpx2 0 GPIO_ACTIVE_LOW>; - linux,code = <115>; - label = "volume up"; - debounce-interval = <1>; - }; - - vol-down-key { - gpios = <&gpx2 1 GPIO_ACTIVE_LOW>; - linux,code = <114>; - label = "volume down"; - debounce-interval = <1>; - }; - - config-key { - gpios = <&gpx2 2 GPIO_ACTIVE_LOW>; - linux,code = <171>; - label = "config"; - debounce-interval = <1>; - wakeup-source; - }; - - camera-key { - gpios = <&gpx2 3 GPIO_ACTIVE_LOW>; - linux,code = <212>; - label = "camera"; - debounce-interval = <1>; - }; - - power-key { - gpios = <&gpx2 7 GPIO_ACTIVE_LOW>; - linux,code = <116>; - label = "power"; - debounce-interval = <1>; - wakeup-source; - }; - - ok-key { - gpios = <&gpx3 5 GPIO_ACTIVE_LOW>; - linux,code = <352>; - label = "ok"; - debounce-interval = <1>; - }; - }; - - tsp_reg: voltage-regulator { - compatible = "regulator-fixed"; - regulator-name = "TSP_2_8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpe2 3 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - spi-lcd { - compatible = "spi-gpio"; - #address-cells = <1>; - #size-cells = <0>; - - gpio-sck = <&gpy3 1 GPIO_ACTIVE_HIGH>; - gpio-mosi = <&gpy3 3 GPIO_ACTIVE_HIGH>; - num-chipselects = <1>; - cs-gpios = <&gpy4 3 GPIO_ACTIVE_HIGH>; - - lcd@0 { - compatible = "samsung,ld9040"; - reg = <0>; - vdd3-supply = <&ldo7_reg>; - vci-supply = <&ldo17_reg>; - reset-gpios = <&gpy4 5 GPIO_ACTIVE_HIGH>; - spi-max-frequency = <1200000>; - spi-cpol; - spi-cpha; - power-on-delay = <10>; - reset-delay = <10>; - panel-width-mm = <90>; - panel-height-mm = <154>; - display-timings { - timing { - clock-frequency = <23492370>; - hactive = <480>; - vactive = <800>; - hback-porch = <16>; - hfront-porch = <16>; - vback-porch = <2>; - vfront-porch = <28>; - hsync-len = <2>; - vsync-len = <1>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - }; - }; - port { - lcd_ep: endpoint { - remote-endpoint = <&fimd_dpi_ep>; - }; - }; - }; - }; - - hdmi_en: voltage-regulator-hdmi-5v { - compatible = "regulator-fixed"; - regulator-name = "HDMI_5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpe0 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - hdmi_ddc: i2c-ddc { - compatible = "i2c-gpio"; - gpios = <&gpe4 2 GPIO_ACTIVE_HIGH &gpe4 3 GPIO_ACTIVE_HIGH>; - i2c-gpio,delay-us = <100>; - #address-cells = <1>; - #size-cells = <0>; - - pinctrl-0 = <&i2c_ddc_bus>; - pinctrl-names = "default"; - status = "okay"; - }; -}; - -&amba { - mdma0: mdma@12840000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x12840000 0x1000>; - interrupts = ; - clocks = <&clock CLK_MDMA>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <1>; - power-domains = <&pd_lcd0>; - }; -}; - -&camera { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <>; -}; - -&cpu0 { - cpu0-supply = <&vdd_arm_reg>; -}; - -&ehci { - status = "okay"; - phys = <&exynos_usbphy 1>; - phy-names = "host"; -}; - -&exynos_usbphy { - status = "okay"; - vbus-supply = <&safeout1_reg>; -}; - -&fimc_0 { - status = "okay"; - assigned-clocks = <&clock CLK_MOUT_FIMC0>, - <&clock CLK_SCLK_FIMC0>; - assigned-clock-parents = <&clock CLK_SCLK_MPLL>; - assigned-clock-rates = <0>, <160000000>; -}; - -&fimc_1 { - status = "okay"; - assigned-clocks = <&clock CLK_MOUT_FIMC1>, - <&clock CLK_SCLK_FIMC1>; - assigned-clock-parents = <&clock CLK_SCLK_MPLL>; - assigned-clock-rates = <0>, <160000000>; -}; - -&fimc_2 { - status = "okay"; - assigned-clocks = <&clock CLK_MOUT_FIMC2>, - <&clock CLK_SCLK_FIMC2>; - assigned-clock-parents = <&clock CLK_SCLK_MPLL>; - assigned-clock-rates = <0>, <160000000>; -}; - -&fimc_3 { - status = "okay"; - assigned-clocks = <&clock CLK_MOUT_FIMC3>, - <&clock CLK_SCLK_FIMC3>; - assigned-clock-parents = <&clock CLK_SCLK_MPLL>; - assigned-clock-rates = <0>, <160000000>; -}; - -&fimd { - pinctrl-0 = <&lcd_clk>, <&lcd_data24>; - pinctrl-names = "default"; - status = "okay"; - samsung,invert-vden; - samsung,invert-vclk; - #address-cells = <1>; - #size-cells = <0>; - port@3 { - reg = <3>; - fimd_dpi_ep: endpoint { - remote-endpoint = <&lcd_ep>; - }; - }; -}; - -&gpu { - mali-supply = <&buck2_reg>; - status = "okay"; -}; - -&hdmi { - hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_hpd>; - hdmi-en-supply = <&hdmi_en>; - vdd-supply = <&ldo3_reg>; - vdd_osc-supply = <&ldo4_reg>; - vdd_pll-supply = <&ldo3_reg>; - ddc = <&hdmi_ddc>; - status = "okay"; -}; - -&hsotg { - vusb_d-supply = <&ldo3_reg>; - vusb_a-supply = <&ldo8_reg>; - dr_mode = "peripheral"; - status = "okay"; -}; - -&i2c_3 { - samsung,i2c-sda-delay = <100>; - samsung,i2c-slave-addr = <0x10>; - samsung,i2c-max-bus-freq = <100000>; - pinctrl-0 = <&i2c3_bus>; - pinctrl-names = "default"; - status = "okay"; - - tsp@4a { - /* TBD: Atmel maXtouch touchscreen */ - reg = <0x4a>; - }; -}; - -&i2c_5 { - samsung,i2c-sda-delay = <100>; - samsung,i2c-slave-addr = <0x10>; - samsung,i2c-max-bus-freq = <100000>; - pinctrl-0 = <&i2c5_bus>; - pinctrl-names = "default"; - status = "okay"; - - vdd_arm_reg: pmic@60 { - compatible = "maxim,max8952"; - reg = <0x60>; - - max8952,vid-gpios = <&gpx0 3 GPIO_ACTIVE_HIGH>, - <&gpx0 4 GPIO_ACTIVE_HIGH>; - max8952,default-mode = <0>; - max8952,dvs-mode-microvolt = <1250000>, <1200000>, - <1050000>, <950000>; - max8952,sync-freq = <0>; - max8952,ramp-speed = <0>; - - regulator-name = "vdd_arm"; - regulator-min-microvolt = <770000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-boot-on; - }; - - pmic@66 { - compatible = "national,lp3974"; - interrupts-extended = <&gpx0 7 0>, <&gpx2 7 0>; - pinctrl-names = "default"; - pinctrl-0 = <&lp3974_irq>; - reg = <0x66>; - - max8998,pmic-buck1-default-dvs-idx = <0>; - max8998,pmic-buck1-dvs-gpios = <&gpx0 5 GPIO_ACTIVE_HIGH>, - <&gpx0 6 GPIO_ACTIVE_HIGH>; - max8998,pmic-buck1-dvs-voltage = <1100000>, <1000000>, - <1100000>, <1000000>; - - max8998,pmic-buck2-default-dvs-idx = <0>; - max8998,pmic-buck2-dvs-gpio = <&gpe2 0 GPIO_ACTIVE_HIGH>; - max8998,pmic-buck2-dvs-voltage = <1200000>, <1100000>; - - regulators { - ldo2_reg: LDO2 { - regulator-name = "VALIVE_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - ldo3_reg: LDO3 { - regulator-name = "VUSB+MIPI_1.1V"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - ldo4_reg: LDO4 { - regulator-name = "VADC_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo5_reg: LDO5 { - regulator-name = "VTF_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo6_reg: LDO6 { - regulator-name = "LDO6"; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - }; - - ldo7_reg: LDO7 { - regulator-name = "VLCD+VMIPI_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo8_reg: LDO8 { - regulator-name = "VUSB+VDAC_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo9_reg: LDO9 { - regulator-name = "VCC_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - ldo10_reg: LDO10 { - regulator-name = "VPLL_1.1V"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo11_reg: LDO11 { - regulator-name = "CAM_AF_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo12_reg: LDO12 { - regulator-name = "PS_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo13_reg: LDO13 { - regulator-name = "VHIC_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - ldo14_reg: LDO14 { - regulator-name = "CAM_I_HOST_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo15_reg: LDO15 { - regulator-name = "CAM_S_DIG+FM33_CORE_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - ldo16_reg: LDO16 { - regulator-name = "CAM_S_ANA_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo17_reg: LDO17 { - regulator-name = "VCC_3.0V_LCD"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - buck1_reg: BUCK1 { - regulator-name = "VINT_1.1V"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - regulator-always-on; - }; - - buck2_reg: BUCK2 { - regulator-name = "VG3D_1.1V"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - }; - - buck3_reg: BUCK3 { - regulator-name = "VCC_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - buck4_reg: BUCK4 { - regulator-name = "VMEM_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - ap32khz_reg: EN32KHz-AP { - regulator-name = "32KHz AP"; - regulator-always-on; - }; - - cp32khz_reg: EN32KHz-CP { - regulator-name = "32KHz CP"; - }; - - vichg_reg: ENVICHG { - regulator-name = "VICHG"; - }; - - safeout1_reg: ESAFEOUT1 { - regulator-name = "SAFEOUT1"; - }; - - safeout2_reg: ESAFEOUT2 { - regulator-name = "SAFEOUT2"; - regulator-boot-on; - }; - }; - }; -}; - -&i2c_8 { - status = "okay"; -}; - -&mct { - compatible = "none"; -}; - -&mdma1 { - /* Use the secure mdma0 */ - status = "disabled"; -}; - -&mixer { - status = "okay"; -}; - -&ohci { - status = "okay"; -}; - -&pinctrl_1 { - lp3974_irq: lp3974-irq { - samsung,pins = "gpx0-7", "gpx2-7"; - samsung,pin-pud = ; - }; - - hdmi_hpd: hdmi-hpd { - samsung,pins = "gpx3-7"; - samsung,pin-pud = ; - }; -}; - -&pinctrl_0 { - i2c_ddc_bus: i2c-ddc-bus { - samsung,pins = "gpe4-2", "gpe4-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pwm { - compatible = "samsung,s5p6440-pwm"; - status = "okay"; -}; - -&sdhci_0 { - bus-width = <8>; - non-removable; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus8>; - pinctrl-names = "default"; - vmmc-supply = <&vemmc_reg>; - status = "okay"; -}; - -&sdhci_2 { - bus-width = <4>; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4>; - pinctrl-names = "default"; - vmmc-supply = <&ldo5_reg>; - cd-gpios = <&gpx3 4 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&serial_0 { - status = "okay"; - /delete-property/dmas; - /delete-property/dma-names; -}; - -&serial_1 { - status = "okay"; - /delete-property/dmas; - /delete-property/dma-names; -}; - -&serial_2 { - status = "okay"; - /delete-property/dmas; - /delete-property/dma-names; -}; - -&serial_3 { - status = "okay"; - /delete-property/dmas; - /delete-property/dma-names; -}; - -&sysram { - smp-sram@0 { - status = "disabled"; - }; - - smp-sram@5000 { - compatible = "samsung,exynos4210-sysram"; - reg = <0x5000 0x1000>; - }; - - smp-sram@1f000 { - status = "disabled"; - }; -}; diff --git a/sys/gnu/dts/arm/exynos4210.dtsi b/sys/gnu/dts/arm/exynos4210.dtsi deleted file mode 100644 index b4466232f0c..00000000000 --- a/sys/gnu/dts/arm/exynos4210.dtsi +++ /dev/null @@ -1,523 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's Exynos4210 SoC device tree source - * - * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * Copyright (c) 2010-2011 Linaro Ltd. - * www.linaro.org - * - * Samsung's Exynos4210 SoC device nodes are listed in this file. Exynos4210 - * based board files can include this file and provide values for board specific - * bindings. - * - * Note: This file does not include device nodes for all the controllers in - * Exynos4210 SoC. As device tree coverage for Exynos4210 increases, additional - * nodes can be added to this file. - */ - -#include "exynos4.dtsi" -#include "exynos4-cpu-thermal.dtsi" - -/ { - compatible = "samsung,exynos4210", "samsung,exynos4"; - - aliases { - pinctrl0 = &pinctrl_0; - pinctrl1 = &pinctrl_1; - pinctrl2 = &pinctrl_2; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@900 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0x900>; - clocks = <&clock CLK_ARM_CLK>; - clock-names = "cpu"; - clock-latency = <160000>; - - operating-points = < - 1200000 1250000 - 1000000 1150000 - 800000 1075000 - 500000 975000 - 400000 975000 - 200000 950000 - >; - #cooling-cells = <2>; /* min followed by max */ - }; - - cpu1: cpu@901 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0x901>; - clocks = <&clock CLK_ARM_CLK>; - clock-names = "cpu"; - clock-latency = <160000>; - - operating-points = < - 1200000 1250000 - 1000000 1150000 - 800000 1075000 - 500000 975000 - 400000 975000 - 200000 950000 - >; - #cooling-cells = <2>; /* min followed by max */ - }; - }; - - soc: soc { - sysram: sram@2020000 { - compatible = "mmio-sram"; - reg = <0x02020000 0x20000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x02020000 0x20000>; - - smp-sram@0 { - compatible = "samsung,exynos4210-sysram"; - reg = <0x0 0x1000>; - }; - - smp-sram@1f000 { - compatible = "samsung,exynos4210-sysram-ns"; - reg = <0x1f000 0x1000>; - }; - }; - - pd_lcd1: power-domain@10023ca0 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10023CA0 0x20>; - #power-domain-cells = <0>; - label = "LCD1"; - }; - - l2c: l2-cache-controller@10502000 { - compatible = "arm,pl310-cache"; - reg = <0x10502000 0x1000>; - cache-unified; - cache-level = <2>; - arm,tag-latency = <2 2 1>; - arm,data-latency = <2 2 1>; - }; - - mct: timer@10050000 { - compatible = "samsung,exynos4210-mct"; - reg = <0x10050000 0x800>; - clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; - clock-names = "fin_pll", "mct"; - interrupts-extended = <&gic GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, - <&combiner 12 6>, - <&combiner 12 7>, - <&gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; - }; - - watchdog: watchdog@10060000 { - compatible = "samsung,s3c6410-wdt"; - reg = <0x10060000 0x100>; - interrupts = ; - clocks = <&clock CLK_WDT>; - clock-names = "watchdog"; - }; - - clock: clock-controller@10030000 { - compatible = "samsung,exynos4210-clock"; - reg = <0x10030000 0x20000>; - #clock-cells = <1>; - }; - - pinctrl_0: pinctrl@11400000 { - compatible = "samsung,exynos4210-pinctrl"; - reg = <0x11400000 0x1000>; - interrupts = ; - }; - - pinctrl_1: pinctrl@11000000 { - compatible = "samsung,exynos4210-pinctrl"; - reg = <0x11000000 0x1000>; - interrupts = ; - - wakup_eint: wakeup-interrupt-controller { - compatible = "samsung,exynos4210-wakeup-eint"; - interrupt-parent = <&gic>; - interrupts = ; - }; - }; - - pinctrl_2: pinctrl@3860000 { - compatible = "samsung,exynos4210-pinctrl"; - reg = <0x03860000 0x1000>; - }; - - g2d: g2d@12800000 { - compatible = "samsung,s5pv210-g2d"; - reg = <0x12800000 0x1000>; - interrupts = ; - clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>; - clock-names = "sclk_fimg2d", "fimg2d"; - power-domains = <&pd_lcd0>; - iommus = <&sysmmu_g2d>; - }; - - ppmu_acp: ppmu_acp@10ae0000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x10ae0000 0x2000>; - status = "disabled"; - }; - - ppmu_lcd1: ppmu_lcd1@12240000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x12240000 0x2000>; - clocks = <&clock CLK_PPMULCD1>; - clock-names = "ppmu"; - status = "disabled"; - }; - - sysmmu_g2d: sysmmu@12a20000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x12A20000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <4 7>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>; - power-domains = <&pd_lcd0>; - #iommu-cells = <0>; - }; - - sysmmu_fimd1: sysmmu@12220000 { - compatible = "samsung,exynos-sysmmu"; - interrupt-parent = <&combiner>; - reg = <0x12220000 0x1000>; - interrupts = <5 3>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>; - power-domains = <&pd_lcd1>; - #iommu-cells = <0>; - }; - - bus_dmc: bus_dmc { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DIV_DMC>; - clock-names = "bus"; - operating-points-v2 = <&bus_dmc_opp_table>; - status = "disabled"; - }; - - bus_acp: bus_acp { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DIV_ACP>; - clock-names = "bus"; - operating-points-v2 = <&bus_acp_opp_table>; - status = "disabled"; - }; - - bus_peri: bus_peri { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_ACLK100>; - clock-names = "bus"; - operating-points-v2 = <&bus_peri_opp_table>; - status = "disabled"; - }; - - bus_fsys: bus_fsys { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_ACLK133>; - clock-names = "bus"; - operating-points-v2 = <&bus_fsys_opp_table>; - status = "disabled"; - }; - - bus_display: bus_display { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_ACLK160>; - clock-names = "bus"; - operating-points-v2 = <&bus_display_opp_table>; - status = "disabled"; - }; - - bus_lcd0: bus_lcd0 { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_ACLK200>; - clock-names = "bus"; - operating-points-v2 = <&bus_leftbus_opp_table>; - status = "disabled"; - }; - - bus_leftbus: bus_leftbus { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DIV_GDL>; - clock-names = "bus"; - operating-points-v2 = <&bus_leftbus_opp_table>; - status = "disabled"; - }; - - bus_rightbus: bus_rightbus { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DIV_GDR>; - clock-names = "bus"; - operating-points-v2 = <&bus_leftbus_opp_table>; - status = "disabled"; - }; - - bus_mfc: bus_mfc { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_SCLK_MFC>; - clock-names = "bus"; - operating-points-v2 = <&bus_leftbus_opp_table>; - status = "disabled"; - }; - - bus_dmc_opp_table: opp_table1 { - compatible = "operating-points-v2"; - opp-shared; - - opp-134000000 { - opp-hz = /bits/ 64 <134000000>; - opp-microvolt = <1025000>; - }; - opp-267000000 { - opp-hz = /bits/ 64 <267000000>; - opp-microvolt = <1050000>; - }; - opp-400000000 { - opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <1150000>; - opp-suspend; - }; - }; - - bus_acp_opp_table: opp_table2 { - compatible = "operating-points-v2"; - opp-shared; - - opp-134000000 { - opp-hz = /bits/ 64 <134000000>; - }; - opp-160000000 { - opp-hz = /bits/ 64 <160000000>; - }; - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - }; - }; - - bus_peri_opp_table: opp_table3 { - compatible = "operating-points-v2"; - opp-shared; - - opp-5000000 { - opp-hz = /bits/ 64 <5000000>; - }; - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - }; - }; - - bus_fsys_opp_table: opp_table4 { - compatible = "operating-points-v2"; - opp-shared; - - opp-10000000 { - opp-hz = /bits/ 64 <10000000>; - }; - opp-134000000 { - opp-hz = /bits/ 64 <134000000>; - }; - }; - - bus_display_opp_table: opp_table5 { - compatible = "operating-points-v2"; - opp-shared; - - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - }; - opp-134000000 { - opp-hz = /bits/ 64 <134000000>; - }; - opp-160000000 { - opp-hz = /bits/ 64 <160000000>; - }; - }; - - bus_leftbus_opp_table: opp_table6 { - compatible = "operating-points-v2"; - opp-shared; - - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - }; - opp-160000000 { - opp-hz = /bits/ 64 <160000000>; - }; - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - opp-suspend; - }; - }; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tmu 0>; - - trips { - cpu_alert0: cpu-alert-0 { - temperature = <85000>; /* millicelsius */ - }; - cpu_alert1: cpu-alert-1 { - temperature = <100000>; /* millicelsius */ - }; - cpu_alert2: cpu-alert-2 { - temperature = <110000>; /* millicelsius */ - }; - }; - }; - }; -}; - -&gic { - cpu-offset = <0x8000>; -}; - -&camera { - clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>, - <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>; - clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1"; -}; - -&combiner { - samsung,combiner-nr = <16>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; -}; - -&fimc_0 { - samsung,pix-limits = <4224 8192 1920 4224>; - samsung,mainscaler-ext; - samsung,cam-if; -}; - -&fimc_1 { - samsung,pix-limits = <4224 8192 1920 4224>; - samsung,mainscaler-ext; - samsung,cam-if; -}; - -&fimc_2 { - samsung,pix-limits = <4224 8192 1920 4224>; - samsung,mainscaler-ext; - samsung,lcd-wb; -}; - -&fimc_3 { - samsung,pix-limits = <1920 8192 1366 1920>; - samsung,rotators = <0>; - samsung,mainscaler-ext; - samsung,lcd-wb; -}; - -&gpu { - interrupts = , - , - , - , - , - , - , - , - , - ; - interrupt-names = "gp", - "gpmmu", - "pp0", - "ppmmu0", - "pp1", - "ppmmu1", - "pp2", - "ppmmu2", - "pp3", - "ppmmu3"; - operating-points-v2 = <&gpu_opp_table>; - - gpu_opp_table: opp_table { - compatible = "operating-points-v2"; - - opp-160000000 { - opp-hz = /bits/ 64 <160000000>; - opp-microvolt = <950000>; - }; - opp-267000000 { - opp-hz = /bits/ 64 <267000000>; - opp-microvolt = <1050000>; - }; - }; -}; - -&mdma1 { - power-domains = <&pd_lcd0>; -}; - -&mixer { - clock-names = "mixer", "hdmi", "sclk_hdmi", "vp", "mout_mixer", - "sclk_mixer"; - clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>, - <&clock CLK_SCLK_HDMI>, <&clock CLK_VP>, - <&clock CLK_MOUT_MIXER>, <&clock CLK_SCLK_MIXER>; -}; - -&pmu { - interrupts = <2 2>, <3 2>; - interrupt-affinity = <&cpu0>, <&cpu1>; - status = "okay"; -}; - -&pmu_system_controller { - clock-names = "clkout0", "clkout1", "clkout2", "clkout3", - "clkout4", "clkout8", "clkout9"; - clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>, - <&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>, - <&clock CLK_OUT_CPU>, <&clock CLK_XXTI>, <&clock CLK_XUSBXTI>; - #clock-cells = <1>; -}; - -&rotator { - power-domains = <&pd_lcd0>; -}; - -&sysmmu_rotator { - power-domains = <&pd_lcd0>; -}; - -&tmu { - compatible = "samsung,exynos4210-tmu"; - clocks = <&clock CLK_TMU_APBIF>; - clock-names = "tmu_apbif"; - samsung,tmu_gain = <15>; - samsung,tmu_reference_voltage = <7>; -}; - -#include "exynos4210-pinctrl.dtsi" diff --git a/sys/gnu/dts/arm/exynos4212.dtsi b/sys/gnu/dts/arm/exynos4212.dtsi deleted file mode 100644 index 538901123d3..00000000000 --- a/sys/gnu/dts/arm/exynos4212.dtsi +++ /dev/null @@ -1,133 +0,0 @@ -/* - * Samsung's Exynos4212 SoC device tree source - * - * Copyright (c) 2012 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Samsung's Exynos4212 SoC device nodes are listed in this file. Exynos4212 - * based board files can include this file and provide values for board specfic - * bindings. - * - * Note: This file does not include device nodes for all the controllers in - * Exynos4212 SoC. As device tree coverage for Exynos4212 increases, additional - * nodes can be added to this file. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include "exynos4x12.dtsi" - -/ { - compatible = "samsung,exynos4212", "samsung,exynos4"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@A00 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0xA00>; - clocks = <&clock CLK_ARM_CLK>; - clock-names = "cpu"; - operating-points-v2 = <&cpu0_opp_table>; - cooling-min-level = <13>; - cooling-max-level = <7>; - #cooling-cells = <2>; /* min followed by max */ - }; - - cpu@A01 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0xA01>; - operating-points-v2 = <&cpu0_opp_table>; - }; - }; - - cpu0_opp_table: opp_table0 { - compatible = "operating-points-v2"; - opp-shared; - - opp00 { - opp-hz = /bits/ 64 <200000000>; - opp-microvolt = <900000>; - clock-latency-ns = <200000>; - }; - opp01 { - opp-hz = /bits/ 64 <300000000>; - opp-microvolt = <900000>; - clock-latency-ns = <200000>; - }; - opp02 { - opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <925000>; - clock-latency-ns = <200000>; - }; - opp03 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <950000>; - clock-latency-ns = <200000>; - }; - opp04 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <975000>; - clock-latency-ns = <200000>; - }; - opp05 { - opp-hz = /bits/ 64 <700000000>; - opp-microvolt = <987500>; - clock-latency-ns = <200000>; - }; - opp06 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <1000000>; - clock-latency-ns = <200000>; - }; - opp07 { - opp-hz = /bits/ 64 <900000000>; - opp-microvolt = <1037500>; - clock-latency-ns = <200000>; - }; - opp08 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <1087500>; - clock-latency-ns = <200000>; - }; - opp09 { - opp-hz = /bits/ 64 <1100000000>; - opp-microvolt = <1137500>; - clock-latency-ns = <200000>; - }; - opp10 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <1187500>; - clock-latency-ns = <200000>; - }; - opp11 { - opp-hz = /bits/ 64 <1300000000>; - opp-microvolt = <1250000>; - clock-latency-ns = <200000>; - }; - opp12 { - opp-hz = /bits/ 64 <1400000000>; - opp-microvolt = <1287500>; - clock-latency-ns = <200000>; - }; - opp13 { - opp-hz = /bits/ 64 <1500000000>; - opp-microvolt = <1350000>; - clock-latency-ns = <200000>; - turbo-mode; - }; - }; -}; - -&combiner { - samsung,combiner-nr = <18>; -}; - -&gic { - cpu-offset = <0x8000>; -}; diff --git a/sys/gnu/dts/arm/exynos4412-galaxy-s3.dtsi b/sys/gnu/dts/arm/exynos4412-galaxy-s3.dtsi deleted file mode 100644 index 44f97546dd0..00000000000 --- a/sys/gnu/dts/arm/exynos4412-galaxy-s3.dtsi +++ /dev/null @@ -1,175 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's Exynos4412 based Galaxy S3 board device tree source - * - * Copyright (c) 2013 Samsung Electronics Co., Ltd. - * http://www.samsung.com - */ - -/dts-v1/; -#include "exynos4412-midas.dtsi" - -/ { - aliases { - i2c9 = &i2c_ak8975; - i2c10 = &i2c_cm36651; - }; - - aat1290 { - compatible = "skyworks,aat1290"; - flen-gpios = <&gpj1 1 GPIO_ACTIVE_HIGH>; - enset-gpios = <&gpj1 2 GPIO_ACTIVE_HIGH>; - - pinctrl-names = "default", "host", "isp"; - pinctrl-0 = <&camera_flash_host>; - pinctrl-1 = <&camera_flash_host>; - pinctrl-2 = <&camera_flash_isp>; - - flash-led { - label = "flash"; - led-max-microamp = <520833>; - flash-max-microamp = <1012500>; - flash-max-timeout-us = <1940000>; - }; - }; - - lcd_vdd3_reg: voltage-regulator-7 { - compatible = "regulator-fixed"; - regulator-name = "LCD_VDD_2.2V"; - regulator-min-microvolt = <2200000>; - regulator-max-microvolt = <2200000>; - gpio = <&gpc0 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - ps_als_reg: voltage-regulator-8 { - compatible = "regulator-fixed"; - regulator-name = "LED_A_3.0V"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - gpio = <&gpj0 5 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - i2c_ak8975: i2c-gpio-0 { - compatible = "i2c-gpio"; - gpios = <&gpy2 4 GPIO_ACTIVE_HIGH>, <&gpy2 5 GPIO_ACTIVE_HIGH>; - i2c-gpio,delay-us = <2>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - ak8975@c { - compatible = "asahi-kasei,ak8975"; - reg = <0x0c>; - gpios = <&gpj0 7 GPIO_ACTIVE_HIGH>; - }; - }; - - i2c_cm36651: i2c-gpio-2 { - compatible = "i2c-gpio"; - gpios = <&gpf0 0 GPIO_ACTIVE_LOW>, <&gpf0 1 GPIO_ACTIVE_LOW>; - i2c-gpio,delay-us = <2>; - #address-cells = <1>; - #size-cells = <0>; - - cm36651@18 { - compatible = "capella,cm36651"; - reg = <0x18>; - interrupt-parent = <&gpx0>; - interrupts = <2 IRQ_TYPE_EDGE_FALLING>; - vled-supply = <&ps_als_reg>; - }; - }; -}; - -&buck9_reg { - maxim,ena-gpios = <&gpm0 3 GPIO_ACTIVE_HIGH>; -}; - -&cam_af_reg { - gpio = <&gpm0 4 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&cam_io_reg { - gpio = <&gpm0 2 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&dsi_0 { - status = "okay"; - - panel@0 { - compatible = "samsung,s6e8aa0"; - reg = <0>; - vdd3-supply = <&lcd_vdd3_reg>; - vci-supply = <&ldo25_reg>; - reset-gpios = <&gpf2 1 GPIO_ACTIVE_HIGH>; - power-on-delay= <50>; - reset-delay = <100>; - init-delay = <100>; - flip-horizontal; - flip-vertical; - panel-width-mm = <58>; - panel-height-mm = <103>; - - display-timings { - timing-0 { - clock-frequency = <57153600>; - hactive = <720>; - vactive = <1280>; - hfront-porch = <5>; - hback-porch = <5>; - hsync-len = <5>; - vfront-porch = <13>; - vback-porch = <1>; - vsync-len = <2>; - }; - }; - }; -}; - -&i2c_3 { - mms114-touchscreen@48 { - compatible = "melfas,mms114"; - reg = <0x48>; - interrupt-parent = <&gpm2>; - interrupts = <3 IRQ_TYPE_EDGE_FALLING>; - touchscreen-size-x = <720>; - touchscreen-size-y = <1280>; - avdd-supply = <&ldo23_reg>; - vdd-supply = <&ldo24_reg>; - }; -}; - -&ldo25_reg { - regulator-name = "LCD_VCC_3.3V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; -}; - -&pinctrl_0 { - camera_flash_host: camera-flash-host { - samsung,pins = "gpj1-0"; - samsung,pin-function = ; - samsung,pin-val = <0>; - }; - - camera_flash_isp: camera-flash-isp { - samsung,pins = "gpj1-0"; - samsung,pin-function = ; - samsung,pin-val = <1>; - }; -}; - -&s5c73m3 { - standby-gpios = <&gpm0 1 GPIO_ACTIVE_LOW>; /* ISP_STANDBY */ - vdda-supply = <&ldo17_reg>; - status = "okay"; -}; - -&touchkey_reg { - gpio = <&gpm0 0 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/exynos4412-i9300.dts b/sys/gnu/dts/arm/exynos4412-i9300.dts deleted file mode 100644 index f8125a945f8..00000000000 --- a/sys/gnu/dts/arm/exynos4412-i9300.dts +++ /dev/null @@ -1,22 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's Exynos4412 based M0 (GT-I9300) board device tree source - * - * Copyright (c) 2013 Samsung Electronics Co., Ltd. - * http://www.samsung.com - */ - -/dts-v1/; -#include "exynos4412-galaxy-s3.dtsi" - -/ { - model = "Samsung Galaxy S3 (GT-I9300) based on Exynos4412"; - compatible = "samsung,i9300", "samsung,midas", "samsung,exynos4412", "samsung,exynos4"; - - /* bootargs are passed in by bootloader */ - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x40000000>; - }; -}; diff --git a/sys/gnu/dts/arm/exynos4412-i9305.dts b/sys/gnu/dts/arm/exynos4412-i9305.dts deleted file mode 100644 index 54a2a55dbf7..00000000000 --- a/sys/gnu/dts/arm/exynos4412-i9305.dts +++ /dev/null @@ -1,20 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; -#include "exynos4412-galaxy-s3.dtsi" - -/ { - model = "Samsung Galaxy S3 (GT-I9305) based on Exynos4412"; - compatible = "samsung,i9305", "samsung,midas", "samsung,exynos4412", "samsung,exynos4"; - - /* bootargs are passed in by bootloader */ - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x80000000>; - }; -}; - -&i2c0_bus { - /* SCL and SDA pins are swapped */ - samsung,pins = "gpd1-1", "gpd1-0"; -}; diff --git a/sys/gnu/dts/arm/exynos4412-itop-elite.dts b/sys/gnu/dts/arm/exynos4412-itop-elite.dts deleted file mode 100644 index f6d0a5f5d33..00000000000 --- a/sys/gnu/dts/arm/exynos4412-itop-elite.dts +++ /dev/null @@ -1,227 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * TOPEET's Exynos4412 based itop board device tree source - * - * Copyright (c) 2016 SUMOMO Computer Association - * https://www.sumomo.mobi - * Randy Li - * - * Device tree source file for TOPEET iTop Exynos 4412 core board - * which is based on Samsung's Exynos4412 SoC. - */ - -/dts-v1/; -#include -#include -#include "exynos4412-itop-scp-core.dtsi" - -/ { - model = "TOPEET iTop 4412 Elite board based on Exynos4412"; - compatible = "topeet,itop4412-elite", "samsung,exynos4412", "samsung,exynos4"; - - chosen { - bootargs = "root=/dev/mmcblk0p2 rw rootfstype=ext4 rootdelay=1 rootwait"; - stdout-path = "serial2:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - led2 { - label = "red:system"; - gpios = <&gpx1 0 GPIO_ACTIVE_HIGH>; - default-state = "off"; - linux,default-trigger = "heartbeat"; - }; - - led3 { - label = "red:user"; - gpios = <&gpk1 1 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - home { - label = "GPIO Key Home"; - linux,code = ; - gpios = <&gpx1 1 GPIO_ACTIVE_LOW>; - }; - - back { - label = "GPIO Key Back"; - linux,code = ; - gpios = <&gpx1 2 GPIO_ACTIVE_LOW>; - }; - - sleep { - label = "GPIO Key Sleep"; - linux,code = ; - gpios = <&gpx3 3 GPIO_ACTIVE_LOW>; - }; - - vol-up { - label = "GPIO Key Vol+"; - linux,code = ; - gpios = <&gpx2 1 GPIO_ACTIVE_LOW>; - }; - - vol-down { - label = "GPIO Key Vol-"; - linux,code = ; - gpios = <&gpx2 0 GPIO_ACTIVE_LOW>; - }; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "wm-sound"; - - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&link0_codec>; - simple-audio-card,frame-master = <&link0_codec>; - - simple-audio-card,widgets = - "Microphone", "Mic Jack", - "Line", "Line In", - "Line", "Line Out", - "Speaker", "Speaker", - "Headphone", "Headphone Jack"; - simple-audio-card,routing = - "Headphone Jack", "HP_L", - "Headphone Jack", "HP_R", - "Speaker", "SPK_LP", - "Speaker", "SPK_LN", - "Speaker", "SPK_RP", - "Speaker", "SPK_RN", - "LINPUT1", "Mic Jack", - "LINPUT3", "Mic Jack", - "RINPUT1", "Mic Jack", - "RINPUT2", "Mic Jack"; - - simple-audio-card,cpu { - sound-dai = <&i2s0 0>; - }; - - link0_codec: simple-audio-card,codec { - sound-dai = <&codec>; - clocks = <&i2s0 CLK_I2S_CDCLK>; - system-clock-frequency = <11289600>; - }; - }; - - beep { - compatible = "pwm-beeper"; - pwms = <&pwm 0 4000000 PWM_POLARITY_INVERTED>; - }; -}; - -&adc { - vdd-supply = <&ldo3_reg>; - status = "okay"; -}; - -&camera { - pinctrl-0 = <&cam_port_a_clk_active>; - pinctrl-names = "default"; - status = "okay"; - assigned-clocks = <&clock CLK_MOUT_CAM0>; - assigned-clock-parents = <&clock CLK_XUSBXTI>; -}; - -&clock_audss { - assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>, - <&clock_audss EXYNOS_MOUT_I2S>, - <&clock_audss EXYNOS_DOUT_SRP>, - <&clock_audss EXYNOS_DOUT_AUD_BUS>; - assigned-clock-parents = <&clock CLK_FOUT_EPLL>, - <&clock_audss EXYNOS_MOUT_AUDSS>; - assigned-clock-rates = <0>, <0>, <112896000>, <11289600>; -}; - -&ehci { - status = "okay"; - /* In order to reset USB ethernet */ - samsung,vbus-gpio = <&gpc0 1 GPIO_ACTIVE_HIGH>; - - phys = <&exynos_usbphy 1>, <&exynos_usbphy 3>; - phy-names = "host", "hsic1"; -}; - -&exynos_usbphy { - status = "okay"; -}; - -&fimc_0 { - status = "okay"; - assigned-clocks = <&clock CLK_MOUT_FIMC0>, - <&clock CLK_SCLK_FIMC0>; - assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; - assigned-clock-rates = <0>, <176000000>; -}; - -&hsotg { - dr_mode = "peripheral"; - status = "okay"; -}; - -&i2c_4 { - samsung,i2c-sda-delay = <100>; - samsung,i2c-slave-addr = <0x10>; - samsung,i2c-max-bus-freq = <100000>; - pinctrl-0 = <&i2c4_bus>; - pinctrl-names = "default"; - status = "okay"; - - codec: wm8960@1a { - compatible = "wlf,wm8960"; - reg = <0x1a>; - clocks = <&pmu_system_controller 0>; - clock-names = "MCLK1"; - wlf,shared-lrclk; - #sound-dai-cells = <0>; - }; -}; - -&i2s0 { - pinctrl-0 = <&i2s0_bus>; - pinctrl-names = "default"; - status = "okay"; -}; - -&pinctrl_1 { - ether-reset { - samsung,pins = "gpc0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pwm { - status = "okay"; - pinctrl-0 = <&pwm0_out>; - pinctrl-names = "default"; - samsung,pwm-outputs = <0>; -}; - -&sdhci_2 { - bus-width = <4>; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4>; - pinctrl-names = "default"; - cd-gpio = <&gpx0 7 GPIO_ACTIVE_LOW>; - cap-sd-highspeed; - vmmc-supply = <&ldo23_reg>; - vqmmc-supply = <&ldo17_reg>; - status = "okay"; -}; - -&serial_1 { - status = "okay"; -}; - -&serial_2 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/exynos4412-itop-scp-core.dtsi b/sys/gnu/dts/arm/exynos4412-itop-scp-core.dtsi deleted file mode 100644 index dfceb155b3a..00000000000 --- a/sys/gnu/dts/arm/exynos4412-itop-scp-core.dtsi +++ /dev/null @@ -1,503 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * TOPEET's Exynos4412 based itop board device tree source - * - * Copyright (c) 2016 SUMOMO Computer Association - * https://www.sumomo.mobi - * Randy Li - * - * Device tree source file for TOPEET iTop Exynos 4412 SCP package core - * board which is based on Samsung's Exynos4412 SoC. - */ - -#include -#include -#include -#include "exynos4412.dtsi" -#include "exynos4412-ppmu-common.dtsi" -#include "exynos-mfc-reserved-memory.dtsi" - -/ { - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x40000000>; - }; - - firmware@203f000 { - compatible = "samsung,secure-firmware"; - reg = <0x0203F000 0x1000>; - }; - - fixed-rate-clocks { - xxti { - compatible = "samsung,clock-xxti"; - clock-frequency = <0>; - }; - - xusbxti { - compatible = "samsung,clock-xusbxti"; - clock-frequency = <24000000>; - }; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - cooling-maps { - map0 { - /* Corresponds to 800MHz at freq_table */ - cooling-device = <&cpu0 7 7>, <&cpu1 7 7>, - <&cpu2 7 7>, <&cpu3 7 7>; - }; - map1 { - /* Corresponds to 200MHz at freq_table */ - cooling-device = <&cpu0 13 13>, - <&cpu1 13 13>, - <&cpu2 13 13>, - <&cpu3 13 13>; - }; - }; - }; - }; - - usb-hub { - compatible = "smsc,usb3503a"; - reset-gpios = <&gpm2 4 GPIO_ACTIVE_LOW>; - connect-gpios = <&gpm3 3 GPIO_ACTIVE_HIGH>; - intn-gpios = <&gpx2 3 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&hsic_reset>; - }; -}; - -&bus_dmc { - devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>; - vdd-supply = <&buck1_reg>; - status = "okay"; -}; - -&bus_acp { - devfreq = <&bus_dmc>; - status = "okay"; -}; - -&bus_c2c { - devfreq = <&bus_dmc>; - status = "okay"; -}; - -&bus_leftbus { - devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>; - vdd-supply = <&buck3_reg>; - status = "okay"; -}; - -&bus_rightbus { - devfreq = <&bus_leftbus>; - status = "okay"; -}; - -&bus_fsys { - devfreq = <&bus_leftbus>; - status = "okay"; -}; - -&bus_peri { - devfreq = <&bus_leftbus>; - status = "okay"; -}; - -&bus_mfc { - devfreq = <&bus_leftbus>; - status = "okay"; -}; - -&cpu0 { - cpu0-supply = <&buck2_reg>; -}; - -&gpu { - mali-supply = <&buck4_reg>; - status = "okay"; -}; - -&hsotg { - vusb_d-supply = <&ldo15_reg>; - vusb_a-supply = <&ldo12_reg>; -}; - -&i2c_1 { - #address-cells = <1>; - #size-cells = <0>; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <400000>; - pinctrl-0 = <&i2c1_bus>; - pinctrl-names = "default"; - status = "okay"; - - s5m8767: s5m8767-pmic@66 { - compatible = "samsung,s5m8767-pmic"; - reg = <0x66>; - - s5m8767,pmic-buck-default-dvs-idx = <3>; - - s5m8767,pmic-buck-dvs-gpios = <&gpb 5 GPIO_ACTIVE_HIGH>, - <&gpb 6 GPIO_ACTIVE_HIGH>, - <&gpb 7 GPIO_ACTIVE_HIGH>; - - s5m8767,pmic-buck-ds-gpios = <&gpm3 5 GPIO_ACTIVE_HIGH>, - <&gpm3 6 GPIO_ACTIVE_HIGH>, - <&gpm3 7 GPIO_ACTIVE_HIGH>; - - /* VDD_ARM */ - s5m8767,pmic-buck2-dvs-voltage = <1356250>, <1300000>, - <1243750>, <1118750>, - <1068750>, <1012500>, - <956250>, <900000>; - /* VDD_INT */ - s5m8767,pmic-buck3-dvs-voltage = <1000000>, <1000000>, - <925000>, <925000>, - <887500>, <887500>, - <850000>, <850000>; - /* VDD_G3D */ - s5m8767,pmic-buck4-dvs-voltage = <1081250>, <1081250>, - <1025000>, <950000>, - <918750>, <900000>, - <875000>, <831250>; - - regulators { - ldo1_reg: LDO1 { - regulator-name = "VDD_ALIVE"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; /* Normal Mode */ - }; - - /* SCP uses 1.5v, POP uses 1.2v */ - ldo2_reg: LDO2 { - regulator-name = "VDDQ_M12"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo3_reg: LDO3 { - regulator-name = "VDDIOAP_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo4_reg: LDO4 { - regulator-name = "VDDQ_PRE"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo5_reg: LDO5 { - regulator-name = "VDD_LDO5"; - op_mode = <0>; /* Always off Mode */ - }; - - ldo6_reg: LDO6 { - regulator-name = "VDD10_MPLL"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo7_reg: LDO7 { - regulator-name = "VDD10_XPLL"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo8_reg: LDO8 { - regulator-name = "VDD10_MIPI"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - op_mode = <1>; /* Normal Mode */ - }; - - ldo9_reg: LDO9 { - regulator-name = "VDD33_LCD"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - op_mode = <1>; /* Normal Mode */ - }; - - ldo10_reg: LDO10 { - regulator-name = "VDD18_MIPI"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - op_mode = <1>; /* Normal Mode */ - }; - - ldo11_reg: LDO11 { - regulator-name = "VDD18_ABB1"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo12_reg: LDO12 { - regulator-name = "VDD33_UOTG"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo13_reg: LDO13 { - regulator-name = "VDDIOPERI_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo14_reg: LDO14 { - regulator-name = "VDD18_ABB02"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo15_reg: LDO15 { - regulator-name = "VDD10_USH"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo16_reg: LDO16 { - regulator-name = "VDD18_HSIC"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo17_reg: LDO17 { - regulator-name = "VDDIOAP_MMC012_28"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - op_mode = <1>; /* Normal Mode */ - }; - - /* Used by HSIC */ - ldo18_reg: LDO18 { - regulator-name = "VDDIOPERI_28"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo19_reg: LDO19 { - regulator-name = "VDD_LDO19"; - op_mode = <0>; /* Always off Mode */ - }; - - ldo20_reg: LDO20 { - regulator-name = "VDD28_CAM"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2800000>; - op_mode = <1>; /* Normal Mode */ - }; - - ldo21_reg: LDO21 { - regulator-name = "VDD28_AF"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2800000>; - op_mode = <1>; /* Normal Mode */ - }; - - ldo22_reg: LDO22 { - regulator-name = "VDDA28_2M"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - op_mode = <1>; /* Normal Mode */ - }; - - ldo23_reg: LDO23 { - regulator-name = "VDD28_TF"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - op_mode = <1>; /* Normal Mode */ - }; - - ldo24_reg: LDO24 { - regulator-name = "VDD33_A31"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - op_mode = <1>; /* Normal Mode */ - }; - - ldo25_reg: LDO25 { - regulator-name = "VDD18_CAM"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - op_mode = <1>; /* Normal Mode */ - }; - - ldo26_reg: LDO26 { - regulator-name = "VDD18_A31"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - op_mode = <1>; /* Normal Mode */ - }; - - ldo27_reg: LDO27 { - regulator-name = "GPS_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - op_mode = <1>; /* Normal Mode */ - }; - - ldo28_reg: LDO28 { - regulator-name = "DVDD12"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - op_mode = <1>; /* Normal Mode */ - }; - - buck1_reg: BUCK1 { - regulator-name = "vdd_mif"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; /* Normal Mode */ - }; - - buck2_reg: BUCK2 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1456250>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; /* Normal Mode */ - }; - - buck3_reg: BUCK3 { - regulator-name = "vdd_int"; - regulator-min-microvolt = <875000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; /* Normal Mode */ - }; - - buck4_reg: BUCK4 { - regulator-name = "vdd_g3d"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; /* Normal Mode */ - }; - - buck5_reg: BUCK5 { - regulator-name = "vdd_m12"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; /* Normal Mode */ - }; - - buck6_reg: BUCK6 { - regulator-name = "vdd12_5m"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; /* Normal Mode */ - }; - - buck7_reg: BUCK7 { - regulator-name = "pvdd_buck7"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <2000000>; - regulator-boot-on; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - buck8_reg: BUCK8 { - regulator-name = "pvdd_buck8"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - buck9_reg: BUCK9 { - regulator-name = "vddf28_emmc"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3000000>; - op_mode = <1>; /* Normal Mode */ - }; - }; - - s5m8767_osc: clocks { - compatible = "samsung,s5m8767-clk"; - #clock-cells = <1>; - clock-output-names = "s5m8767_ap", - "s5m8767_cp", "s5m8767_bt"; - }; - - }; -}; - -&mfc { - status = "okay"; -}; - -&mshc_0 { - pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>; - pinctrl-names = "default"; - status = "okay"; - vmmc-supply = <&buck9_reg>; - broken-cd; - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; - bus-width = <8>; - cap-mmc-highspeed; -}; - -&pinctrl_1 { - hsic_reset: hsic-reset { - samsung,pins = "gpm2-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&rtc { - status = "okay"; - clocks = <&clock CLK_RTC>, <&s5m8767_osc S2MPS11_CLK_AP>; - clock-names = "rtc", "rtc_src"; -}; - -&tmu { - vtmu-supply = <&ldo16_reg>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/exynos4412-midas.dtsi b/sys/gnu/dts/arm/exynos4412-midas.dtsi deleted file mode 100644 index 3023bc3b68c..00000000000 --- a/sys/gnu/dts/arm/exynos4412-midas.dtsi +++ /dev/null @@ -1,1372 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's Exynos4412 based Trats 2 board device tree source - * - * Copyright (c) 2013 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Device tree source file for Samsung's Trats 2 board which is based on - * Samsung's Exynos4412 SoC. - */ - -/dts-v1/; -#include "exynos4412.dtsi" -#include "exynos4412-ppmu-common.dtsi" -#include -#include -#include -#include -#include - -/ { - compatible = "samsung,midas", "samsung,exynos4412", "samsung,exynos4"; - - aliases { - i2c11 = &i2c_max77693; - i2c12 = &i2c_max77693_fuel; - }; - - chosen { - stdout-path = &serial_2; - }; - - firmware@204f000 { - compatible = "samsung,secure-firmware"; - reg = <0x0204F000 0x1000>; - }; - - fixed-rate-clocks { - xxti { - compatible = "samsung,clock-xxti", "fixed-clock"; - clock-frequency = <0>; - }; - - xusbxti { - compatible = "samsung,clock-xusbxti", "fixed-clock"; - clock-frequency = <24000000>; - }; - }; - - cam_io_reg: voltage-regulator-1 { - compatible = "regulator-fixed"; - regulator-name = "CAM_SENSOR_A"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - enable-active-high; - status = "disabled"; - }; - - cam_af_reg: voltage-regulator-2 { - compatible = "regulator-fixed"; - regulator-name = "CAM_AF"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - enable-active-high; - status = "disabled"; - }; - - vsil12: voltage-regulator-3 { - compatible = "regulator-fixed"; - regulator-name = "VSIL_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - gpio = <&gpl0 4 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&buck7_reg>; - }; - - vcc33mhl: voltage-regulator-4 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3.3_MHL"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpl0 4 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vcc18mhl: voltage-regulator-5 { - compatible = "regulator-fixed"; - regulator-name = "VCC_1.8_MHL"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpl0 4 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - touchkey_reg: voltage-regulator-6 { - compatible = "regulator-fixed"; - regulator-name = "LED_VDD_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - status = "disabled"; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&gpio_keys>; - - key-down { - gpios = <&gpx3 3 GPIO_ACTIVE_LOW>; - linux,code = <114>; - label = "volume down"; - debounce-interval = <10>; - }; - - key-up { - gpios = <&gpx2 2 GPIO_ACTIVE_LOW>; - linux,code = <115>; - label = "volume up"; - debounce-interval = <10>; - }; - - key-power { - gpios = <&gpx2 7 GPIO_ACTIVE_LOW>; - linux,code = <116>; - label = "power"; - debounce-interval = <10>; - wakeup-source; - }; - - key-ok { - gpios = <&gpx0 1 GPIO_ACTIVE_LOW>; - linux,code = <139>; - label = "ok"; - debounce-interval = <10>; - wakeup-source; - }; - }; - - i2c_max77693: i2c-gpio-1 { - compatible = "i2c-gpio"; - gpios = <&gpm2 0 GPIO_ACTIVE_HIGH>, <&gpm2 1 GPIO_ACTIVE_HIGH>; - i2c-gpio,delay-us = <2>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - max77693@66 { - compatible = "maxim,max77693"; - interrupt-parent = <&gpx1>; - interrupts = <5 IRQ_TYPE_EDGE_FALLING>; - pinctrl-names = "default"; - pinctrl-0 = <&max77693_irq>; - reg = <0x66>; - - regulators { - esafeout1_reg: ESAFEOUT1 { - regulator-name = "ESAFEOUT1"; - }; - esafeout2_reg: ESAFEOUT2 { - regulator-name = "ESAFEOUT2"; - }; - charger_reg: CHARGER { - regulator-name = "CHARGER"; - regulator-min-microamp = <60000>; - regulator-max-microamp = <2580000>; - }; - }; - - max77693_haptic { - compatible = "maxim,max77693-haptic"; - haptic-supply = <&ldo26_reg>; - pwms = <&pwm 0 38022 0>; - }; - - charger { - compatible = "maxim,max77693-charger"; - - maxim,constant-microvolt = <4350000>; - maxim,min-system-microvolt = <3600000>; - maxim,thermal-regulation-celsius = <100>; - maxim,battery-overcurrent-microamp = <3500000>; - maxim,charge-input-threshold-microvolt = <4300000>; - }; - }; - }; - - i2c_max77693_fuel: i2c-gpio-3 { - compatible = "i2c-gpio"; - gpios = <&gpf1 5 GPIO_ACTIVE_HIGH>, <&gpf1 4 GPIO_ACTIVE_HIGH>; - i2c-gpio,delay-us = <2>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - max77693-fuel-gauge@36 { - compatible = "maxim,max17047"; - interrupt-parent = <&gpx2>; - interrupts = <3 IRQ_TYPE_EDGE_FALLING>; - pinctrl-names = "default"; - pinctrl-0 = <&max77693_fuel_irq>; - reg = <0x36>; - - maxim,over-heat-temp = <700>; - maxim,over-volt = <4500>; - }; - }; - - i2c-gpio-4 { - compatible = "i2c-gpio"; - sda-gpios = <&gpl0 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpl0 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <2>; - #address-cells = <1>; - #size-cells = <0>; - - touchkey@20 { - compatible = "cypress,midas-touchkey"; - reg = <0x20>; - vdd-supply = <&touchkey_reg>; - vcc-supply = <&ldo5_reg>; - interrupt-parent = <&gpj0>; - interrupts = <3 IRQ_TYPE_EDGE_FALLING>; - linux,keycodes = ; - }; - }; - - i2c-mhl { - compatible = "i2c-gpio"; - gpios = <&gpf0 4 GPIO_ACTIVE_HIGH>, <&gpf0 6 GPIO_ACTIVE_HIGH>; - i2c-gpio,delay-us = <100>; - #address-cells = <1>; - #size-cells = <0>; - - pinctrl-0 = <&i2c_mhl_bus>; - pinctrl-names = "default"; - status = "okay"; - - sii9234: hdmi-bridge@39 { - compatible = "sil,sii9234"; - avcc33-supply = <&vcc33mhl>; - iovcc18-supply = <&vcc18mhl>; - avcc12-supply = <&vsil12>; - cvcc12-supply = <&vsil12>; - reset-gpios = <&gpf3 4 GPIO_ACTIVE_LOW>; - interrupt-parent = <&gpf3>; - interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x39>; - - port { - mhl_to_hdmi: endpoint { - remote-endpoint = <&hdmi_to_mhl>; - }; - }; - }; - }; - - wlan_pwrseq: sdhci3-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpj0 0 GPIO_ACTIVE_LOW>; - clocks = <&max77686 MAX77686_CLK_PMIC>; - clock-names = "ext_clock"; - }; - - sound { - compatible = "samsung,trats2-audio"; - samsung,i2s-controller = <&i2s0>; - samsung,model = "Trats2"; - samsung,audio-codec = <&wm1811>; - samsung,audio-routing = - "SPK", "SPKOUTLN", - "SPK", "SPKOUTLP", - "SPK", "SPKOUTRN", - "SPK", "SPKOUTRP"; - }; - - thermistor-ap { - compatible = "murata,ncp15wb473"; - pullup-uv = <1800000>; /* VCC_1.8V_AP */ - pullup-ohm = <100000>; /* 100K */ - pulldown-ohm = <100000>; /* 100K */ - io-channels = <&adc 1>; /* AP temperature */ - }; - - thermistor-battery { - compatible = "murata,ncp15wb473"; - pullup-uv = <1800000>; /* VCC_1.8V_AP */ - pullup-ohm = <100000>; /* 100K */ - pulldown-ohm = <100000>; /* 100K */ - io-channels = <&adc 2>; /* Battery temperature */ - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - cooling-maps { - map0 { - /* Corresponds to 800MHz at freq_table */ - cooling-device = <&cpu0 7 7>, <&cpu1 7 7>, - <&cpu2 7 7>, <&cpu3 7 7>; - }; - map1 { - /* Corresponds to 200MHz at freq_table */ - cooling-device = <&cpu0 13 13>, - <&cpu1 13 13>, - <&cpu2 13 13>, - <&cpu3 13 13>; - }; - }; - }; - }; -}; - -&adc { - vdd-supply = <&ldo3_reg>; - status = "okay"; -}; - -&bus_dmc { - devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>; - vdd-supply = <&buck1_reg>; - status = "okay"; -}; - -&bus_acp { - devfreq = <&bus_dmc>; - status = "okay"; -}; - -&bus_c2c { - devfreq = <&bus_dmc>; - status = "okay"; -}; - -&bus_leftbus { - devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>; - vdd-supply = <&buck3_reg>; - status = "okay"; -}; - -&bus_rightbus { - devfreq = <&bus_leftbus>; - status = "okay"; -}; - -&bus_display { - devfreq = <&bus_leftbus>; - status = "okay"; -}; - -&bus_fsys { - devfreq = <&bus_leftbus>; - status = "okay"; -}; - -&bus_peri { - devfreq = <&bus_leftbus>; - status = "okay"; -}; - -&bus_mfc { - devfreq = <&bus_leftbus>; - status = "okay"; -}; - -&camera { - pinctrl-0 = <&cam_port_a_clk_active &cam_port_b_clk_active>; - pinctrl-names = "default"; - status = "okay"; - assigned-clocks = <&clock CLK_MOUT_CAM0>, - <&clock CLK_MOUT_CAM1>; - assigned-clock-parents = <&clock CLK_XUSBXTI>, - <&clock CLK_XUSBXTI>; -}; - -&cpu0 { - cpu0-supply = <&buck2_reg>; -}; - -&csis_0 { - status = "okay"; - vddcore-supply = <&ldo8_reg>; - vddio-supply = <&ldo10_reg>; - assigned-clocks = <&clock CLK_MOUT_CSIS0>, - <&clock CLK_SCLK_CSIS0>; - assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; - assigned-clock-rates = <0>, <176000000>; - - /* Camera C (3) MIPI CSI-2 (CSIS0) */ - port@3 { - reg = <3>; - csis0_ep: endpoint { - remote-endpoint = <&s5c73m3_ep>; - data-lanes = <1 2 3 4>; - samsung,csis-hs-settle = <12>; - }; - }; -}; - -&csis_1 { - status = "okay"; - vddcore-supply = <&ldo8_reg>; - vddio-supply = <&ldo10_reg>; - assigned-clocks = <&clock CLK_MOUT_CSIS1>, - <&clock CLK_SCLK_CSIS1>; - assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; - assigned-clock-rates = <0>, <176000000>; - - /* Camera D (4) MIPI CSI-2 (CSIS1) */ - port@4 { - reg = <4>; - csis1_ep: endpoint { - remote-endpoint = <&is_s5k6a3_ep>; - data-lanes = <1>; - samsung,csis-hs-settle = <18>; - samsung,csis-wclk; - }; - }; -}; - -&dsi_0 { - vddcore-supply = <&ldo8_reg>; - vddio-supply = <&ldo10_reg>; - samsung,burst-clock-frequency = <500000000>; - samsung,esc-clock-frequency = <20000000>; - samsung,pll-clock-frequency = <24000000>; -}; - -&exynos_usbphy { - vbus-supply = <&esafeout1_reg>; - status = "okay"; -}; - -&fimc_0 { - status = "okay"; - assigned-clocks = <&clock CLK_MOUT_FIMC0>, - <&clock CLK_SCLK_FIMC0>; - assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; - assigned-clock-rates = <0>, <176000000>; -}; - -&fimc_1 { - status = "okay"; - assigned-clocks = <&clock CLK_MOUT_FIMC1>, - <&clock CLK_SCLK_FIMC1>; - assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; - assigned-clock-rates = <0>, <176000000>; -}; - -&fimc_2 { - status = "okay"; - assigned-clocks = <&clock CLK_MOUT_FIMC2>, - <&clock CLK_SCLK_FIMC2>; - assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; - assigned-clock-rates = <0>, <176000000>; -}; - -&fimc_3 { - status = "okay"; - assigned-clocks = <&clock CLK_MOUT_FIMC3>, - <&clock CLK_SCLK_FIMC3>; - assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; - assigned-clock-rates = <0>, <176000000>; -}; - -&fimc_is { - pinctrl-0 = <&fimc_is_uart>; - pinctrl-names = "default"; - status = "okay"; - - }; - -&fimc_lite_0 { - status = "okay"; -}; - -&fimc_lite_1 { - status = "okay"; -}; - -&fimd { - status = "okay"; -}; - -&gpu { - mali-supply = <&buck4_reg>; - status = "okay"; -}; - -&hdmi { - hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_hpd>; - vdd-supply = <&ldo3_reg>; - vdd_osc-supply = <&ldo4_reg>; - vdd_pll-supply = <&ldo3_reg>; - ddc = <&i2c_5>; - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - hdmi_to_mhl: endpoint { - remote-endpoint = <&mhl_to_hdmi>; - }; - }; - }; -}; - -&hsotg { - vusb_d-supply = <&ldo15_reg>; - vusb_a-supply = <&ldo12_reg>; - dr_mode = "peripheral"; - status = "okay"; -}; - -&i2c_0 { - samsung,i2c-sda-delay = <100>; - samsung,i2c-slave-addr = <0x10>; - samsung,i2c-max-bus-freq = <400000>; - pinctrl-0 = <&i2c0_bus>; - pinctrl-names = "default"; - status = "okay"; - - s5c73m3: s5c73m3@3c { - compatible = "samsung,s5c73m3"; - reg = <0x3c>; - xshutdown-gpios = <&gpf1 3 GPIO_ACTIVE_LOW>; /* ISP_RESET */ - vdd-int-supply = <&buck9_reg>; - vddio-cis-supply = <&ldo9_reg>; - vddio-host-supply = <&ldo18_reg>; - vdd-af-supply = <&cam_af_reg>; - vdd-reg-supply = <&cam_io_reg>; - clock-frequency = <24000000>; - /* CAM_A_CLKOUT */ - clocks = <&camera 0>; - clock-names = "cis_extclk"; - status = "disabled"; - port { - s5c73m3_ep: endpoint { - remote-endpoint = <&csis0_ep>; - data-lanes = <1 2 3 4>; - }; - }; - }; -}; - -&i2c1_isp { - pinctrl-0 = <&fimc_is_i2c1>; - pinctrl-names = "default"; - - s5k6a3@10 { - compatible = "samsung,s5k6a3"; - reg = <0x10>; - svdda-supply = <&cam_io_reg>; - svddio-supply = <&ldo19_reg>; - afvdd-supply = <&ldo19_reg>; - clock-frequency = <24000000>; - /* CAM_B_CLKOUT */ - clocks = <&camera 1>; - clock-names = "extclk"; - samsung,camclk-out = <1>; - gpios = <&gpm1 6 GPIO_ACTIVE_HIGH>; - - port { - is_s5k6a3_ep: endpoint { - remote-endpoint = <&csis1_ep>; - data-lanes = <1>; - }; - }; - }; -}; - -&i2c_3 { - samsung,i2c-sda-delay = <100>; - samsung,i2c-slave-addr = <0x10>; - samsung,i2c-max-bus-freq = <400000>; - pinctrl-0 = <&i2c3_bus>; - pinctrl-names = "default"; - status = "okay"; -}; - -&i2c_4 { - samsung,i2c-sda-delay = <100>; - samsung,i2c-slave-addr = <0x10>; - samsung,i2c-max-bus-freq = <100000>; - pinctrl-0 = <&i2c4_bus>; - pinctrl-names = "default"; - status = "okay"; - - wm1811: wm1811@1a { - compatible = "wlf,wm1811"; - reg = <0x1a>; - clocks = <&pmu_system_controller 0>; - clock-names = "MCLK1"; - DCVDD-supply = <&ldo3_reg>; - DBVDD1-supply = <&ldo3_reg>; - wlf,ldo1ena = <&gpj0 4 0>; - }; -}; - -&i2c_5 { - status = "okay"; -}; - -&i2c_7 { - samsung,i2c-sda-delay = <100>; - samsung,i2c-slave-addr = <0x10>; - samsung,i2c-max-bus-freq = <100000>; - pinctrl-0 = <&i2c7_bus>; - pinctrl-names = "default"; - status = "okay"; - - max77686: max77686_pmic@9 { - compatible = "maxim,max77686"; - interrupt-parent = <&gpx0>; - interrupts = <7 IRQ_TYPE_NONE>; - pinctrl-0 = <&max77686_irq>; - pinctrl-names = "default"; - reg = <0x09>; - #clock-cells = <1>; - - voltage-regulators { - ldo1_reg: LDO1 { - regulator-name = "VALIVE_1.0V_AP"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo2_reg: LDO2 { - regulator-name = "VM1M2_1.2V_AP"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - ldo3_reg: LDO3 { - regulator-name = "VCC_1.8V_AP"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo4_reg: LDO4 { - regulator-name = "VCC_2.8V_AP"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - ldo5_reg: LDO5 { - regulator-name = "VCC_1.8V_IO"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo6_reg: LDO6 { - regulator-name = "VMPLL_1.0V_AP"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - ldo7_reg: LDO7 { - regulator-name = "VPLL_1.0V_AP"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - ldo8_reg: LDO8 { - regulator-name = "VMIPI_1.0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo9_reg: LDO9 { - regulator-name = "CAM_ISP_MIPI_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - ldo10_reg: LDO10 { - regulator-name = "VMIPI_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo11_reg: LDO11 { - regulator-name = "VABB1_1.95V"; - regulator-min-microvolt = <1950000>; - regulator-max-microvolt = <1950000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo12_reg: LDO12 { - regulator-name = "VUOTG_3.0V"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo13_reg: LDO13 { - regulator-name = "NFC_AVDD_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo14_reg: LDO14 { - regulator-name = "VABB2_1.95V"; - regulator-min-microvolt = <1950000>; - regulator-max-microvolt = <1950000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo15_reg: LDO15 { - regulator-name = "VHSIC_1.0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - ldo16_reg: LDO16 { - regulator-name = "VHSIC_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - ldo17_reg: LDO17 { - regulator-name = "CAM_SENSOR_CORE_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - ldo18_reg: LDO18 { - regulator-name = "CAM_ISP_SEN_IO_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo19_reg: LDO19 { - regulator-name = "VT_CAM_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo20_reg: LDO20 { - regulator-name = "VDDQ_PRE_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo21_reg: LDO21 { - regulator-name = "VTF_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - maxim,ena-gpios = <&gpy2 0 GPIO_ACTIVE_HIGH>; - }; - - ldo22_reg: LDO22 { - regulator-name = "VMEM_VDD_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - maxim,ena-gpios = <&gpk0 2 GPIO_ACTIVE_HIGH>; - }; - - ldo23_reg: LDO23 { - regulator-name = "TSP_AVDD_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo24_reg: LDO24 { - regulator-name = "TSP_VDD_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo25_reg: LDO25 { - regulator-name = "LDO25"; - }; - - ldo26_reg: LDO26 { - regulator-name = "MOTOR_VCC_3.0V"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - buck1_reg: BUCK1 { - regulator-name = "vdd_mif"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck2_reg: BUCK2 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - buck3_reg: BUCK3 { - regulator-name = "vdd_int"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1150000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck4_reg: BUCK4 { - regulator-name = "vdd_g3d"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1150000>; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck5_reg: BUCK5 { - regulator-name = "VMEM_1.2V_AP"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - buck6_reg: BUCK6 { - regulator-name = "VCC_SUB_1.35V"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - }; - - buck7_reg: BUCK7 { - regulator-name = "VCC_SUB_2.0V"; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - regulator-always-on; - }; - - buck8_reg: BUCK8 { - regulator-name = "VMEM_VDDF_3.0V"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - maxim,ena-gpios = <&gpk0 2 GPIO_ACTIVE_HIGH>; - }; - - buck9_reg: BUCK9 { - regulator-name = "CAM_ISP_CORE_1.2V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1200000>; - }; - }; - }; -}; - -&i2c_8 { - status = "okay"; -}; - -&i2s0 { - pinctrl-0 = <&i2s0_bus>; - pinctrl-names = "default"; - status = "okay"; -}; - -&mixer { - status = "okay"; -}; - -&mshc_0 { - broken-cd; - non-removable; - card-detect-delay = <200>; - vmmc-supply = <&ldo22_reg>; - clock-frequency = <400000000>; - samsung,dw-mshc-ciu-div = <0>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; - pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>; - pinctrl-names = "default"; - status = "okay"; - bus-width = <8>; - cap-mmc-highspeed; -}; - -&pmu_system_controller { - assigned-clocks = <&pmu_system_controller 0>; - assigned-clock-parents = <&clock CLK_XUSBXTI>; -}; - -&pinctrl_0 { - pinctrl-names = "default"; - pinctrl-0 = <&sleep0>; - - mhl_int: mhl-int { - samsung,pins = "gpf3-5"; - samsung,pin-pud = ; - }; - - i2c_mhl_bus: i2c-mhl-bus { - samsung,pins = "gpf0-4", "gpf0-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sleep0: sleep-states { - PIN_SLP(gpa0-0, INPUT, NONE); - PIN_SLP(gpa0-1, OUT0, NONE); - PIN_SLP(gpa0-2, INPUT, NONE); - PIN_SLP(gpa0-3, INPUT, UP); - PIN_SLP(gpa0-4, INPUT, NONE); - PIN_SLP(gpa0-5, INPUT, DOWN); - PIN_SLP(gpa0-6, INPUT, DOWN); - PIN_SLP(gpa0-7, INPUT, UP); - - PIN_SLP(gpa1-0, INPUT, DOWN); - PIN_SLP(gpa1-1, INPUT, DOWN); - PIN_SLP(gpa1-2, INPUT, DOWN); - PIN_SLP(gpa1-3, INPUT, DOWN); - PIN_SLP(gpa1-4, INPUT, DOWN); - PIN_SLP(gpa1-5, INPUT, DOWN); - - PIN_SLP(gpb-0, INPUT, NONE); - PIN_SLP(gpb-1, INPUT, NONE); - PIN_SLP(gpb-2, INPUT, NONE); - PIN_SLP(gpb-3, INPUT, NONE); - PIN_SLP(gpb-4, INPUT, DOWN); - PIN_SLP(gpb-5, INPUT, UP); - PIN_SLP(gpb-6, INPUT, DOWN); - PIN_SLP(gpb-7, INPUT, DOWN); - - PIN_SLP(gpc0-0, INPUT, DOWN); - PIN_SLP(gpc0-1, INPUT, DOWN); - PIN_SLP(gpc0-2, INPUT, DOWN); - PIN_SLP(gpc0-3, INPUT, DOWN); - PIN_SLP(gpc0-4, INPUT, DOWN); - - PIN_SLP(gpc1-0, INPUT, NONE); - PIN_SLP(gpc1-1, PREV, NONE); - PIN_SLP(gpc1-2, INPUT, NONE); - PIN_SLP(gpc1-3, INPUT, NONE); - PIN_SLP(gpc1-4, INPUT, NONE); - - PIN_SLP(gpd0-0, INPUT, DOWN); - PIN_SLP(gpd0-1, INPUT, DOWN); - PIN_SLP(gpd0-2, INPUT, NONE); - PIN_SLP(gpd0-3, INPUT, NONE); - - PIN_SLP(gpd1-0, INPUT, DOWN); - PIN_SLP(gpd1-1, INPUT, DOWN); - PIN_SLP(gpd1-2, INPUT, NONE); - PIN_SLP(gpd1-3, INPUT, NONE); - - PIN_SLP(gpf0-0, INPUT, NONE); - PIN_SLP(gpf0-1, INPUT, NONE); - PIN_SLP(gpf0-2, INPUT, DOWN); - PIN_SLP(gpf0-3, INPUT, DOWN); - PIN_SLP(gpf0-4, INPUT, NONE); - PIN_SLP(gpf0-5, INPUT, DOWN); - PIN_SLP(gpf0-6, INPUT, NONE); - PIN_SLP(gpf0-7, INPUT, DOWN); - - PIN_SLP(gpf1-0, INPUT, DOWN); - PIN_SLP(gpf1-1, INPUT, DOWN); - PIN_SLP(gpf1-2, INPUT, DOWN); - PIN_SLP(gpf1-3, INPUT, DOWN); - PIN_SLP(gpf1-4, INPUT, NONE); - PIN_SLP(gpf1-5, INPUT, NONE); - PIN_SLP(gpf1-6, INPUT, DOWN); - PIN_SLP(gpf1-7, PREV, NONE); - - PIN_SLP(gpf2-0, PREV, NONE); - PIN_SLP(gpf2-1, INPUT, DOWN); - PIN_SLP(gpf2-2, INPUT, DOWN); - PIN_SLP(gpf2-3, INPUT, DOWN); - PIN_SLP(gpf2-4, INPUT, DOWN); - PIN_SLP(gpf2-5, INPUT, DOWN); - PIN_SLP(gpf2-6, INPUT, NONE); - PIN_SLP(gpf2-7, INPUT, NONE); - - PIN_SLP(gpf3-0, INPUT, NONE); - PIN_SLP(gpf3-1, PREV, NONE); - PIN_SLP(gpf3-2, PREV, NONE); - PIN_SLP(gpf3-3, PREV, NONE); - PIN_SLP(gpf3-4, OUT1, NONE); - PIN_SLP(gpf3-5, INPUT, DOWN); - - PIN_SLP(gpj0-0, PREV, NONE); - PIN_SLP(gpj0-1, PREV, NONE); - PIN_SLP(gpj0-2, PREV, NONE); - PIN_SLP(gpj0-3, INPUT, DOWN); - PIN_SLP(gpj0-4, PREV, NONE); - PIN_SLP(gpj0-5, PREV, NONE); - PIN_SLP(gpj0-6, INPUT, DOWN); - PIN_SLP(gpj0-7, INPUT, DOWN); - - PIN_SLP(gpj1-0, INPUT, DOWN); - PIN_SLP(gpj1-1, PREV, NONE); - PIN_SLP(gpj1-2, PREV, NONE); - PIN_SLP(gpj1-3, INPUT, DOWN); - PIN_SLP(gpj1-4, INPUT, DOWN); - }; -}; - -&pinctrl_1 { - pinctrl-names = "default"; - pinctrl-0 = <&sleep1>; - - gpio_keys: gpio-keys { - samsung,pins = "gpx0-1", "gpx2-2", "gpx2-7", "gpx3-3"; - samsung,pin-pud = ; - }; - - max77686_irq: max77686-irq { - samsung,pins = "gpx0-7"; - samsung,pin-pud = ; - }; - - max77693_irq: max77693-irq { - samsung,pins = "gpx1-5"; - samsung,pin-pud = ; - }; - - max77693_fuel_irq: max77693-fuel-irq { - samsung,pins = "gpx2-3"; - samsung,pin-pud = ; - }; - - sdhci2_cd: sdhci2-cd-irq { - samsung,pins = "gpx3-4"; - samsung,pin-pud = ; - }; - - hdmi_hpd: hdmi-hpd { - samsung,pins = "gpx3-7"; - samsung,pin-pud = ; - }; - - sleep1: sleep-states { - PIN_SLP(gpk0-0, PREV, NONE); - PIN_SLP(gpk0-1, PREV, NONE); - PIN_SLP(gpk0-2, OUT0, NONE); - PIN_SLP(gpk0-3, PREV, NONE); - PIN_SLP(gpk0-4, PREV, NONE); - PIN_SLP(gpk0-5, PREV, NONE); - PIN_SLP(gpk0-6, PREV, NONE); - - PIN_SLP(gpk1-0, INPUT, DOWN); - PIN_SLP(gpk1-1, INPUT, DOWN); - PIN_SLP(gpk1-2, INPUT, DOWN); - PIN_SLP(gpk1-3, PREV, NONE); - PIN_SLP(gpk1-4, PREV, NONE); - PIN_SLP(gpk1-5, PREV, NONE); - PIN_SLP(gpk1-6, PREV, NONE); - - PIN_SLP(gpk2-0, INPUT, DOWN); - PIN_SLP(gpk2-1, INPUT, DOWN); - PIN_SLP(gpk2-2, INPUT, DOWN); - PIN_SLP(gpk2-3, INPUT, DOWN); - PIN_SLP(gpk2-4, INPUT, DOWN); - PIN_SLP(gpk2-5, INPUT, DOWN); - PIN_SLP(gpk2-6, INPUT, DOWN); - - PIN_SLP(gpk3-0, OUT0, NONE); - PIN_SLP(gpk3-1, INPUT, NONE); - PIN_SLP(gpk3-2, INPUT, DOWN); - PIN_SLP(gpk3-3, INPUT, NONE); - PIN_SLP(gpk3-4, INPUT, NONE); - PIN_SLP(gpk3-5, INPUT, NONE); - PIN_SLP(gpk3-6, INPUT, NONE); - - PIN_SLP(gpl0-0, INPUT, DOWN); - PIN_SLP(gpl0-1, INPUT, DOWN); - PIN_SLP(gpl0-2, INPUT, DOWN); - PIN_SLP(gpl0-3, INPUT, DOWN); - PIN_SLP(gpl0-4, PREV, NONE); - PIN_SLP(gpl0-6, PREV, NONE); - - PIN_SLP(gpl1-0, INPUT, DOWN); - PIN_SLP(gpl1-1, INPUT, DOWN); - PIN_SLP(gpl2-0, INPUT, DOWN); - PIN_SLP(gpl2-1, INPUT, DOWN); - PIN_SLP(gpl2-2, INPUT, DOWN); - PIN_SLP(gpl2-3, INPUT, DOWN); - PIN_SLP(gpl2-4, INPUT, DOWN); - PIN_SLP(gpl2-5, INPUT, DOWN); - PIN_SLP(gpl2-6, PREV, NONE); - PIN_SLP(gpl2-7, INPUT, DOWN); - - PIN_SLP(gpm0-0, INPUT, DOWN); - PIN_SLP(gpm0-1, INPUT, DOWN); - PIN_SLP(gpm0-2, INPUT, DOWN); - PIN_SLP(gpm0-3, INPUT, DOWN); - PIN_SLP(gpm0-4, INPUT, DOWN); - PIN_SLP(gpm0-5, INPUT, DOWN); - PIN_SLP(gpm0-6, INPUT, DOWN); - PIN_SLP(gpm0-7, INPUT, DOWN); - - PIN_SLP(gpm1-0, INPUT, DOWN); - PIN_SLP(gpm1-1, INPUT, DOWN); - PIN_SLP(gpm1-2, INPUT, NONE); - PIN_SLP(gpm1-3, INPUT, NONE); - PIN_SLP(gpm1-4, INPUT, NONE); - PIN_SLP(gpm1-5, INPUT, NONE); - PIN_SLP(gpm1-6, INPUT, DOWN); - - PIN_SLP(gpm2-0, INPUT, NONE); - PIN_SLP(gpm2-1, INPUT, NONE); - PIN_SLP(gpm2-2, INPUT, DOWN); - PIN_SLP(gpm2-3, INPUT, DOWN); - PIN_SLP(gpm2-4, INPUT, DOWN); - - PIN_SLP(gpm3-0, PREV, NONE); - PIN_SLP(gpm3-1, PREV, NONE); - PIN_SLP(gpm3-2, PREV, NONE); - PIN_SLP(gpm3-3, OUT1, NONE); - PIN_SLP(gpm3-4, INPUT, DOWN); - PIN_SLP(gpm3-5, INPUT, DOWN); - PIN_SLP(gpm3-6, INPUT, DOWN); - PIN_SLP(gpm3-7, INPUT, DOWN); - - PIN_SLP(gpm4-0, INPUT, DOWN); - PIN_SLP(gpm4-1, INPUT, DOWN); - PIN_SLP(gpm4-2, INPUT, DOWN); - PIN_SLP(gpm4-3, INPUT, DOWN); - PIN_SLP(gpm4-4, INPUT, DOWN); - PIN_SLP(gpm4-5, INPUT, DOWN); - PIN_SLP(gpm4-6, INPUT, DOWN); - PIN_SLP(gpm4-7, INPUT, DOWN); - - PIN_SLP(gpy0-0, INPUT, DOWN); - PIN_SLP(gpy0-1, INPUT, DOWN); - PIN_SLP(gpy0-2, INPUT, DOWN); - PIN_SLP(gpy0-3, INPUT, DOWN); - PIN_SLP(gpy0-4, INPUT, DOWN); - PIN_SLP(gpy0-5, INPUT, DOWN); - - PIN_SLP(gpy1-0, INPUT, DOWN); - PIN_SLP(gpy1-1, INPUT, DOWN); - PIN_SLP(gpy1-2, INPUT, DOWN); - PIN_SLP(gpy1-3, INPUT, DOWN); - - PIN_SLP(gpy2-0, PREV, NONE); - PIN_SLP(gpy2-1, INPUT, DOWN); - PIN_SLP(gpy2-2, INPUT, NONE); - PIN_SLP(gpy2-3, INPUT, NONE); - PIN_SLP(gpy2-4, INPUT, NONE); - PIN_SLP(gpy2-5, INPUT, NONE); - - PIN_SLP(gpy3-0, INPUT, DOWN); - PIN_SLP(gpy3-1, INPUT, DOWN); - PIN_SLP(gpy3-2, INPUT, DOWN); - PIN_SLP(gpy3-3, INPUT, DOWN); - PIN_SLP(gpy3-4, INPUT, DOWN); - PIN_SLP(gpy3-5, INPUT, DOWN); - PIN_SLP(gpy3-6, INPUT, DOWN); - PIN_SLP(gpy3-7, INPUT, DOWN); - - PIN_SLP(gpy4-0, INPUT, DOWN); - PIN_SLP(gpy4-1, INPUT, DOWN); - PIN_SLP(gpy4-2, INPUT, DOWN); - PIN_SLP(gpy4-3, INPUT, DOWN); - PIN_SLP(gpy4-4, INPUT, DOWN); - PIN_SLP(gpy4-5, INPUT, DOWN); - PIN_SLP(gpy4-6, INPUT, DOWN); - PIN_SLP(gpy4-7, INPUT, DOWN); - - PIN_SLP(gpy5-0, INPUT, DOWN); - PIN_SLP(gpy5-1, INPUT, DOWN); - PIN_SLP(gpy5-2, INPUT, DOWN); - PIN_SLP(gpy5-3, INPUT, DOWN); - PIN_SLP(gpy5-4, INPUT, DOWN); - PIN_SLP(gpy5-5, INPUT, DOWN); - PIN_SLP(gpy5-6, INPUT, DOWN); - PIN_SLP(gpy5-7, INPUT, DOWN); - - PIN_SLP(gpy6-0, INPUT, DOWN); - PIN_SLP(gpy6-1, INPUT, DOWN); - PIN_SLP(gpy6-2, INPUT, DOWN); - PIN_SLP(gpy6-3, INPUT, DOWN); - PIN_SLP(gpy6-4, INPUT, DOWN); - PIN_SLP(gpy6-5, INPUT, DOWN); - PIN_SLP(gpy6-6, INPUT, DOWN); - PIN_SLP(gpy6-7, INPUT, DOWN); - }; -}; - -&pinctrl_2 { - pinctrl-names = "default"; - pinctrl-0 = <&sleep2>; - - sleep2: sleep-states { - PIN_SLP(gpz-0, INPUT, DOWN); - PIN_SLP(gpz-1, INPUT, DOWN); - PIN_SLP(gpz-2, INPUT, DOWN); - PIN_SLP(gpz-3, INPUT, DOWN); - PIN_SLP(gpz-4, INPUT, DOWN); - PIN_SLP(gpz-5, INPUT, DOWN); - PIN_SLP(gpz-6, INPUT, DOWN); - }; -}; - -&pinctrl_3 { - pinctrl-names = "default"; - pinctrl-0 = <&sleep3>; - - sleep3: sleep-states { - PIN_SLP(gpv0-0, INPUT, DOWN); - PIN_SLP(gpv0-1, INPUT, DOWN); - PIN_SLP(gpv0-2, INPUT, DOWN); - PIN_SLP(gpv0-3, INPUT, DOWN); - PIN_SLP(gpv0-4, INPUT, DOWN); - PIN_SLP(gpv0-5, INPUT, DOWN); - PIN_SLP(gpv0-6, INPUT, DOWN); - PIN_SLP(gpv0-7, INPUT, DOWN); - - PIN_SLP(gpv1-0, INPUT, DOWN); - PIN_SLP(gpv1-1, INPUT, DOWN); - PIN_SLP(gpv1-2, INPUT, DOWN); - PIN_SLP(gpv1-3, INPUT, DOWN); - PIN_SLP(gpv1-4, INPUT, DOWN); - PIN_SLP(gpv1-5, INPUT, DOWN); - PIN_SLP(gpv1-6, INPUT, DOWN); - PIN_SLP(gpv1-7, INPUT, DOWN); - - PIN_SLP(gpv2-0, INPUT, DOWN); - PIN_SLP(gpv2-1, INPUT, DOWN); - PIN_SLP(gpv2-2, INPUT, DOWN); - PIN_SLP(gpv2-3, INPUT, DOWN); - PIN_SLP(gpv2-4, INPUT, DOWN); - PIN_SLP(gpv2-5, INPUT, DOWN); - PIN_SLP(gpv2-6, INPUT, DOWN); - PIN_SLP(gpv2-7, INPUT, DOWN); - - PIN_SLP(gpv3-0, INPUT, DOWN); - PIN_SLP(gpv3-1, INPUT, DOWN); - PIN_SLP(gpv3-2, INPUT, DOWN); - PIN_SLP(gpv3-3, INPUT, DOWN); - PIN_SLP(gpv3-4, INPUT, DOWN); - PIN_SLP(gpv3-5, INPUT, DOWN); - PIN_SLP(gpv3-6, INPUT, DOWN); - PIN_SLP(gpv3-7, INPUT, DOWN); - - PIN_SLP(gpv4-0, INPUT, DOWN); - }; -}; - -&pwm { - pinctrl-0 = <&pwm0_out>; - pinctrl-names = "default"; - samsung,pwm-outputs = <0>; - status = "okay"; -}; - -&rtc { - status = "okay"; - clocks = <&clock CLK_RTC>, <&max77686 MAX77686_CLK_AP>; - clock-names = "rtc", "rtc_src"; -}; - -&sdhci_2 { - bus-width = <4>; - cd-gpios = <&gpx3 4 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sdhci2_cd>; - pinctrl-names = "default"; - vmmc-supply = <&ldo21_reg>; - status = "okay"; -}; - -&sdhci_3 { - #address-cells = <1>; - #size-cells = <0>; - non-removable; - bus-width = <4>; - - mmc-pwrseq = <&wlan_pwrseq>; - pinctrl-names = "default"; - pinctrl-0 = <&sd3_clk &sd3_cmd &sd3_bus4>; - status = "okay"; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - interrupt-parent = <&gpx2>; - interrupts = <5 IRQ_TYPE_NONE>; - interrupt-names = "host-wake"; - }; -}; - -&serial_0 { - status = "okay"; -}; - -&serial_1 { - status = "okay"; -}; - -&serial_2 { - status = "okay"; -}; - -&serial_3 { - status = "okay"; -}; - -&spi_1 { - pinctrl-names = "default"; - pinctrl-0 = <&spi1_bus>; - cs-gpios = <&gpb 5 GPIO_ACTIVE_HIGH>; - status = "okay"; - - s5c73m3_spi: s5c73m3@0 { - compatible = "samsung,s5c73m3"; - spi-max-frequency = <50000000>; - reg = <0>; - controller-data { - samsung,spi-feedback-delay = <2>; - }; - }; -}; - -&tmu { - vtmu-supply = <&ldo10_reg>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/exynos4412-n710x.dts b/sys/gnu/dts/arm/exynos4412-n710x.dts deleted file mode 100644 index 4189e1fb204..00000000000 --- a/sys/gnu/dts/arm/exynos4412-n710x.dts +++ /dev/null @@ -1,80 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; -#include "exynos4412-midas.dtsi" - -/ { - compatible = "samsung,n710x", "samsung,midas", "samsung,exynos4412", "samsung,exynos4"; - model = "Samsung Galaxy Note 2 (GT-N7100, GT-N7105) based on Exynos4412"; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x80000000>; - }; - - /* bootargs are passed in by bootloader */ - - cam_vdda_reg: voltage-regulator-7 { - compatible = "regulator-fixed"; - regulator-name = "CAM_SENSOR_CORE_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - gpio = <&gpm4 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&buck9_reg { - maxim,ena-gpios = <&gpm1 0 GPIO_ACTIVE_HIGH>; -}; - -&cam_af_reg { - gpio = <&gpm1 1 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&cam_io_reg { - gpio = <&gpm0 7 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&i2c_3 { - samsung,i2c-sda-delay = <100>; - samsung,i2c-slave-addr = <0x10>; - samsung,i2c-max-bus-freq = <400000>; - pinctrl-0 = <&i2c3_bus>; - pinctrl-names = "default"; - status = "okay"; - - mms152-touchscreen@48 { - compatible = "melfas,mms152"; - reg = <0x48>; - interrupt-parent = <&gpm2>; - interrupts = <3 IRQ_TYPE_EDGE_FALLING>; - x-size = <720>; - y-size = <1280>; - avdd-supply = <&ldo23_reg>; - vdd-supply = <&ldo24_reg>; - }; -}; - -&ldo13_reg { - regulator-name = "VCC_1.8V_LCD"; - regulator-always-on; -}; - -&ldo25_reg { - regulator-name = "VCI_3.0V_LCD"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; -}; - -&s5c73m3 { - standby-gpios = <&gpm0 6 GPIO_ACTIVE_LOW>; /* ISP_STANDBY */ - vdda-supply = <&cam_vdda_reg>; - status = "okay"; -}; - -&touchkey_reg { - gpio = <&gpm0 5 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/exynos4412-odroid-common.dtsi b/sys/gnu/dts/arm/exynos4412-odroid-common.dtsi deleted file mode 100644 index 9c39e82e4ec..00000000000 --- a/sys/gnu/dts/arm/exynos4412-odroid-common.dtsi +++ /dev/null @@ -1,564 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Common definition for Hardkernel's Exynos4412 based ODROID-X/X2/U2/U3 boards - * device tree source -*/ - -#include -#include -#include -#include "exynos4412.dtsi" -#include "exynos4412-ppmu-common.dtsi" -#include -#include "exynos-mfc-reserved-memory.dtsi" - -/ { - chosen { - stdout-path = &serial_1; - }; - - firmware@204f000 { - compatible = "samsung,secure-firmware"; - reg = <0x0204F000 0x1000>; - }; - - gpio_keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&gpio_power_key>; - - power_key { - gpios = <&gpx1 3 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "power key"; - debounce-interval = <10>; - wakeup-source; - }; - }; - - sound: sound { - compatible = "hardkernel,odroid-xu4-audio"; - - cpu { - sound-dai = <&i2s0 0>; - }; - - codec { - sound-dai = <&hdmi>, <&max98090>; - }; - }; - - emmc_pwrseq: pwrseq { - pinctrl-0 = <&emmc_rstn>; - pinctrl-names = "default"; - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpk1 2 GPIO_ACTIVE_LOW>; - }; - - fixed-rate-clocks { - xxti { - compatible = "samsung,clock-xxti"; - clock-frequency = <0>; - }; - - xusbxti { - compatible = "samsung,clock-xusbxti"; - clock-frequency = <24000000>; - }; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - cooling-maps { - cooling_map0: map0 { - /* Corresponds to 800MHz at freq_table */ - cooling-device = <&cpu0 7 7>, <&cpu1 7 7>, - <&cpu2 7 7>, <&cpu3 7 7>; - }; - cooling_map1: map1 { - /* Corresponds to 200MHz at freq_table */ - cooling-device = <&cpu0 13 13>, - <&cpu1 13 13>, - <&cpu2 13 13>, - <&cpu3 13 13>; - }; - }; - }; - }; -}; - -&bus_dmc { - devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>; - vdd-supply = <&buck1_reg>; - status = "okay"; -}; - -&bus_acp { - devfreq = <&bus_dmc>; - status = "okay"; -}; - -&bus_c2c { - devfreq = <&bus_dmc>; - status = "okay"; -}; - -&bus_leftbus { - devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>; - vdd-supply = <&buck3_reg>; - status = "okay"; -}; - -&bus_rightbus { - devfreq = <&bus_leftbus>; - status = "okay"; -}; - -&bus_display { - devfreq = <&bus_leftbus>; - status = "okay"; -}; - -&bus_fsys { - devfreq = <&bus_leftbus>; - status = "okay"; -}; - -&bus_peri { - devfreq = <&bus_leftbus>; - status = "okay"; -}; - -&bus_mfc { - devfreq = <&bus_leftbus>; - status = "okay"; -}; - -&camera { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <>; -}; - -&clock { - assigned-clocks = <&clock CLK_FOUT_EPLL>; - assigned-clock-rates = <45158401>; -}; - -&clock_audss { - assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>, - <&clock_audss EXYNOS_MOUT_I2S>, - <&clock_audss EXYNOS_DOUT_SRP>, - <&clock_audss EXYNOS_DOUT_AUD_BUS>, - <&clock_audss EXYNOS_DOUT_I2S>; - - assigned-clock-parents = <&clock CLK_FOUT_EPLL>, - <&clock_audss EXYNOS_MOUT_AUDSS>; - - assigned-clock-rates = <0>, <0>, - <196608001>, - <(196608001 / 2)>, - <(196608001 / 8)>; -}; - -&cpu0 { - cpu0-supply = <&buck2_reg>; -}; - -&pinctrl_1 { - gpio_power_key: power_key { - samsung,pins = "gpx1-3"; - samsung,pin-pud = ; - }; - - max77686_irq: max77686-irq { - samsung,pins = "gpx3-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - hdmi_hpd: hdmi-hpd { - samsung,pins = "gpx3-7"; - samsung,pin-pud = ; - }; - - emmc_rstn: emmc-rstn { - samsung,pins = "gpk1-2"; - samsung,pin-pud = ; - }; -}; - -&ehci { - status = "okay"; -}; - -&exynos_usbphy { - status = "okay"; -}; - -&fimc_0 { - status = "okay"; - assigned-clocks = <&clock CLK_MOUT_FIMC0>, - <&clock CLK_SCLK_FIMC0>; - assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; - assigned-clock-rates = <0>, <176000000>; -}; - -&fimc_1 { - status = "okay"; - assigned-clocks = <&clock CLK_MOUT_FIMC1>, - <&clock CLK_SCLK_FIMC1>; - assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; - assigned-clock-rates = <0>, <176000000>; -}; - -&fimc_2 { - status = "okay"; - assigned-clocks = <&clock CLK_MOUT_FIMC2>, - <&clock CLK_SCLK_FIMC2>; - assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; - assigned-clock-rates = <0>, <176000000>; -}; - -&fimc_3 { - status = "okay"; - assigned-clocks = <&clock CLK_MOUT_FIMC3>, - <&clock CLK_SCLK_FIMC3>; - assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; - assigned-clock-rates = <0>, <176000000>; -}; - -&gpu { - mali-supply = <&buck4_reg>; - status = "okay"; -}; - -&hdmi { - hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_hpd>; - vdd-supply = <&ldo8_reg>; - vdd_osc-supply = <&ldo10_reg>; - vdd_pll-supply = <&ldo8_reg>; - ddc = <&i2c_2>; - status = "okay"; -}; - -&hdmicec { - status = "okay"; -}; - -&hsotg { - dr_mode = "peripheral"; - status = "okay"; - vusb_d-supply = <&ldo15_reg>; - vusb_a-supply = <&ldo12_reg>; -}; - -&i2c_0 { - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <400000>; - status = "okay"; - - usb3503: usb3503@8 { - compatible = "smsc,usb3503"; - reg = <0x08>; - - intn-gpios = <&gpx3 0 GPIO_ACTIVE_HIGH>; - connect-gpios = <&gpx3 4 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpx3 5 GPIO_ACTIVE_LOW>; - initial-mode = <1>; - }; - - max77686: pmic@9 { - compatible = "maxim,max77686"; - interrupt-parent = <&gpx3>; - interrupts = <2 IRQ_TYPE_NONE>; - pinctrl-names = "default"; - pinctrl-0 = <&max77686_irq>; - reg = <0x09>; - #clock-cells = <1>; - - voltage-regulators { - ldo1_reg: LDO1 { - regulator-name = "VDD_ALIVE_1.0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo2_reg: LDO2 { - regulator-name = "VDDQ_M1_2_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo3_reg: LDO3 { - regulator-name = "VDDQ_EXT_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo4_reg: LDO4 { - regulator-name = "VDDQ_MMC2_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-boot-on; - }; - - ldo5_reg: LDO5 { - regulator-name = "VDDQ_MMC1_3_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo6_reg: LDO6 { - regulator-name = "VDD10_MPLL_1.0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo7_reg: LDO7 { - regulator-name = "VDD10_XPLL_1.0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo8_reg: LDO8 { - regulator-name = "VDD10_HDMI_1.0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - }; - - ldo10_reg: LDO10 { - regulator-name = "VDDQ_MIPIHSI_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo11_reg: LDO11 { - regulator-name = "VDD18_ABB1_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo12_reg: LDO12 { - regulator-name = "VDD33_USB_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo13_reg: LDO13 { - regulator-name = "VDDQ_C2C_W_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo14_reg: LDO14 { - regulator-name = "VDD18_ABB0_2_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo15_reg: LDO15 { - regulator-name = "VDD10_HSIC_1.0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo16_reg: LDO16 { - regulator-name = "VDD18_HSIC_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo20_reg: LDO20 { - regulator-name = "LDO20_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo21_reg: LDO21 { - regulator-name = "TFLASH_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-boot-on; - }; - - ldo22_reg: LDO22 { - /* - * Only U3 uses it, so let it define the - * constraints - */ - regulator-name = "LDO22"; - regulator-boot-on; - }; - - ldo25_reg: LDO25 { - regulator-name = "VDDQ_LCD_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - buck1_reg: BUCK1 { - regulator-name = "vdd_mif"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - regulator-boot-on; - }; - - buck2_reg: BUCK2 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - - buck3_reg: BUCK3 { - regulator-name = "vdd_int"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1050000>; - regulator-always-on; - regulator-boot-on; - }; - - buck4_reg: BUCK4 { - regulator-name = "vdd_g3d"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1100000>; - regulator-microvolt-offset = <50000>; - }; - - buck5_reg: BUCK5 { - regulator-name = "VDDQ_CKEM1_2_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - }; - - buck6_reg: BUCK6 { - regulator-name = "BUCK6_1.35V"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - - buck7_reg: BUCK7 { - regulator-name = "BUCK7_2.0V"; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - regulator-always-on; - }; - - buck8_reg: BUCK8 { - /* - * Constraints set by specific board: X, - * X2 and U3. - */ - regulator-name = "BUCK8_2.8V"; - }; - }; - }; -}; - -&i2c_1 { - status = "okay"; - max98090: max98090@10 { - compatible = "maxim,max98090"; - reg = <0x10>; - interrupt-parent = <&gpx0>; - interrupts = <0 IRQ_TYPE_NONE>; - clocks = <&i2s0 CLK_I2S_CDCLK>; - clock-names = "mclk"; - #sound-dai-cells = <0>; - }; -}; - -&i2c_2 { - status = "okay"; -}; - -&i2c_8 { - status = "okay"; -}; - -&i2s0 { - pinctrl-0 = <&i2s0_bus>; - pinctrl-names = "default"; - status = "okay"; - assigned-clocks = <&i2s0 CLK_I2S_RCLK_SRC>; - assigned-clock-parents = <&clock_audss EXYNOS_SCLK_I2S>; -}; - -&mixer { - status = "okay"; -}; - -&mshc_0 { - pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>; - pinctrl-names = "default"; - vmmc-supply = <&ldo20_reg>; - mmc-pwrseq = <&emmc_pwrseq>; - status = "okay"; - - broken-cd; - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; - bus-width = <8>; - cap-mmc-highspeed; -}; - -&rtc { - status = "okay"; - clocks = <&clock CLK_RTC>, <&max77686 MAX77686_CLK_AP>; - clock-names = "rtc", "rtc_src"; -}; - -&sdhci_2 { - bus-width = <4>; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; - pinctrl-names = "default"; - vmmc-supply = <&ldo21_reg>; - vqmmc-supply = <&ldo4_reg>; - cd-gpios = <&gpk2 2 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&serial_0 { - status = "okay"; -}; - -&serial_1 { - status = "okay"; -}; - -&tmu { - vtmu-supply = <&ldo10_reg>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/exynos4412-odroidu3.dts b/sys/gnu/dts/arm/exynos4412-odroidu3.dts deleted file mode 100644 index 8ff243ba454..00000000000 --- a/sys/gnu/dts/arm/exynos4412-odroidu3.dts +++ /dev/null @@ -1,131 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Hardkernel's Exynos4412 based ODROID-U3 board device tree source - * - * Copyright (c) 2014 Marek Szyprowski - * - * Device tree source file for Hardkernel's ODROID-U3 board which is based - * on Samsung's Exynos4412 SoC. - */ - -/dts-v1/; -#include "exynos4412-odroid-common.dtsi" -#include "exynos4412-prime.dtsi" - -/ { - model = "Hardkernel ODROID-U3 board based on Exynos4412"; - compatible = "hardkernel,odroid-u3", "samsung,exynos4412", "samsung,exynos4"; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x7FF00000>; - }; - - leds { - compatible = "gpio-leds"; - led1 { - label = "led1:heart"; - gpios = <&gpc1 0 GPIO_ACTIVE_LOW>; - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - }; - - fan0: pwm-fan { - compatible = "pwm-fan"; - pwms = <&pwm 0 10000 0>; - #cooling-cells = <2>; - cooling-levels = <0 102 170 230>; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - cooling-maps { - map0 { - trip = <&cpu_alert1>; - cooling-device = <&cpu0 9 9>, <&cpu1 9 9>, - <&cpu2 9 9>, <&cpu3 9 9>, - <&fan0 1 2>; - }; - map1 { - trip = <&cpu_alert2>; - cooling-device = <&cpu0 15 15>, - <&cpu1 15 15>, - <&cpu2 15 15>, - <&cpu3 15 15>, - <&fan0 2 3>; - }; - map2 { - trip = <&cpu_alert0>; - cooling-device = <&fan0 0 1>; - }; - }; - }; - }; -}; - -&adc { - vdd-supply = <&ldo10_reg>; - /* Nothing connected to ADC inputs, keep it disabled */ -}; - -/* Supply for LAN9730/SMSC95xx */ -&buck8_reg { - regulator-name = "BUCK8_P3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; -}; - -&hdmicec { - needs-hpd; -}; - -/* VDDQ for MSHC (eMMC card) */ -&ldo22_reg { - regulator-name = "LDO22_VDDQ_MMC4_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; -}; - -&mshc_0 { - vqmmc-supply = <&ldo22_reg>; -}; - -&pwm { - pinctrl-0 = <&pwm0_out>; - pinctrl-names = "default"; - samsung,pwm-outputs = <0>; - status = "okay"; -}; - -&usb3503 { - clock-names = "refclk"; - clocks = <&pmu_system_controller 0>; - refclk-frequency = <24000000>; -}; - -&ehci { - phys = <&exynos_usbphy 2>, <&exynos_usbphy 3>; - phy-names = "hsic0", "hsic1"; -}; - -&sound { - model = "Odroid-U3"; - samsung,audio-widgets = - "Headphone", "Headphone Jack", - "Speakers", "Speakers"; - samsung,audio-routing = - "Headphone Jack", "HPL", - "Headphone Jack", "HPR", - "Headphone Jack", "MICBIAS", - "IN1", "Headphone Jack", - "Speakers", "SPKL", - "Speakers", "SPKR"; -}; - -&spi_1 { - pinctrl-names = "default"; - pinctrl-0 = <&spi1_bus>; - cs-gpios = <&gpb 5 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/exynos4412-odroidx.dts b/sys/gnu/dts/arm/exynos4412-odroidx.dts deleted file mode 100644 index 3ea2a0101e8..00000000000 --- a/sys/gnu/dts/arm/exynos4412-odroidx.dts +++ /dev/null @@ -1,109 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Hardkernel's Exynos4412 based ODROID-X board device tree source - * - * Copyright (c) 2012 Dongjin Kim - * - * Device tree source file for Hardkernel's ODROID-X board which is based - * on Samsung's Exynos4412 SoC. - */ - -/dts-v1/; -#include "exynos4412-odroid-common.dtsi" - -/ { - model = "Hardkernel ODROID-X board based on Exynos4412"; - compatible = "hardkernel,odroid-x", "samsung,exynos4412", "samsung,exynos4"; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x3FF00000>; - }; - - leds { - compatible = "gpio-leds"; - led1 { - label = "led1:heart"; - gpios = <&gpc1 0 GPIO_ACTIVE_LOW>; - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - led2 { - label = "led2:mmc0"; - gpios = <&gpc1 2 GPIO_ACTIVE_LOW>; - default-state = "on"; - linux,default-trigger = "mmc0"; - }; - }; - - gpio_keys { - pinctrl-0 = <&gpio_power_key &gpio_home_key>; - - home_key { - gpios = <&gpx2 2 GPIO_ACTIVE_HIGH>; - linux,code = ; - label = "home key"; - debounce-interval = <10>; - wakeup-source; - }; - }; - - regulator_p3v3 { - compatible = "regulator-fixed"; - regulator-name = "p3v3_en"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpa1 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - }; -}; - -&adc { - vdd-supply = <&ldo10_reg>; - status = "okay"; -}; - -/* VDDQ for MSHC (eMMC card) */ -&buck8_reg { - regulator-name = "BUCK8_VDDQ_MMC4_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; -}; - -&ehci { - phys = <&exynos_usbphy 2>; - phy-names = "hsic0"; -}; - -&mshc_0 { - vqmmc-supply = <&buck8_reg>; -}; - -&pinctrl_1 { - gpio_home_key: home_key { - samsung,pins = "gpx2-2"; - samsung,pin-pud = ; - }; -}; - -&serial_2 { - status = "okay"; -}; - -&serial_3 { - status = "okay"; -}; - -&sound { - model = "Odroid-X"; - samsung,audio-widgets = - "Headphone", "Headphone Jack", - "Microphone", "Mic Jack", - "Microphone", "DMIC"; - samsung,audio-routing = - "Headphone Jack", "HPL", - "Headphone Jack", "HPR", - "IN1", "Mic Jack", - "Mic Jack", "MICBIAS"; -}; diff --git a/sys/gnu/dts/arm/exynos4412-odroidx2.dts b/sys/gnu/dts/arm/exynos4412-odroidx2.dts deleted file mode 100644 index f4b68c75c96..00000000000 --- a/sys/gnu/dts/arm/exynos4412-odroidx2.dts +++ /dev/null @@ -1,22 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Hardkernel's Exynos4412 based ODROID-X2 board device tree source - * - * Copyright (c) 2012 Dongjin Kim - * - * Device tree source file for Hardkernel's ODROID-X2 board which is based - * on Samsung's Exynos4412 SoC. - */ - -#include "exynos4412-odroidx.dts" -#include "exynos4412-prime.dtsi" - -/ { - model = "Hardkernel ODROID-X2 board based on Exynos4412"; - compatible = "hardkernel,odroid-x2", "samsung,exynos4412", "samsung,exynos4"; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x7FF00000>; - }; -}; diff --git a/sys/gnu/dts/arm/exynos4412-origen.dts b/sys/gnu/dts/arm/exynos4412-origen.dts deleted file mode 100644 index ecd14b283a6..00000000000 --- a/sys/gnu/dts/arm/exynos4412-origen.dts +++ /dev/null @@ -1,533 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Insignal's Exynos4412 based Origen board device tree source - * - * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Device tree source file for Insignal's Origen board which is based on - * Samsung's Exynos4412 SoC. - */ - -/dts-v1/; -#include "exynos4412.dtsi" -#include -#include -#include "exynos-mfc-reserved-memory.dtsi" - -/ { - model = "Insignal Origen evaluation board based on Exynos4412"; - compatible = "insignal,origen4412", "samsung,exynos4412", "samsung,exynos4"; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x40000000>; - }; - - chosen { - stdout-path = "serial2:115200n8"; - }; - - firmware@203f000 { - compatible = "samsung,secure-firmware"; - reg = <0x0203F000 0x1000>; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - mmc_reg: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "VMEM_VDD_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpx1 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - }; - - display-timings { - native-mode = <&timing0>; - timing0: timing { - clock-frequency = <47500000>; - hactive = <1024>; - vactive = <600>; - hfront-porch = <64>; - hback-porch = <16>; - hsync-len = <48>; - vback-porch = <64>; - vfront-porch = <16>; - vsync-len = <3>; - }; - }; - - fixed-rate-clocks { - xxti { - compatible = "samsung,clock-xxti"; - clock-frequency = <0>; - }; - - xusbxti { - compatible = "samsung,clock-xusbxti"; - clock-frequency = <24000000>; - }; - }; -}; - -&cpu0 { - cpu0-supply = <&buck2_reg>; -}; - -&exynos_usbphy { - status = "okay"; -}; - -&ehci { - samsung,vbus-gpio = <&gpx3 5 1>; - status = "okay"; - phys = <&exynos_usbphy 2>, <&exynos_usbphy 3>; - phy-names = "hsic0", "hsic1"; -}; - -&fimd { - pinctrl-0 = <&lcd_clk &lcd_data24 &pwm1_out>; - pinctrl-names = "default"; - status = "okay"; -}; - -&i2c_0 { - #address-cells = <1>; - #size-cells = <0>; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <20000>; - pinctrl-0 = <&i2c0_bus>; - pinctrl-names = "default"; - status = "okay"; - - s5m8767_pmic@66 { - compatible = "samsung,s5m8767-pmic"; - reg = <0x66>; - - s5m8767,pmic-buck-default-dvs-idx = <3>; - - s5m8767,pmic-buck-dvs-gpios = <&gpx2 3 GPIO_ACTIVE_HIGH>, - <&gpx2 4 GPIO_ACTIVE_HIGH>, - <&gpx2 5 GPIO_ACTIVE_HIGH>; - - s5m8767,pmic-buck-ds-gpios = <&gpm3 5 GPIO_ACTIVE_HIGH>, - <&gpm3 6 GPIO_ACTIVE_HIGH>, - <&gpm3 7 GPIO_ACTIVE_HIGH>; - - s5m8767,pmic-buck2-dvs-voltage = <1250000>, <1200000>, - <1200000>, <1200000>, - <1200000>, <1200000>, - <1200000>, <1200000>; - - s5m8767,pmic-buck3-dvs-voltage = <1100000>, <1100000>, - <1100000>, <1100000>, - <1100000>, <1100000>, - <1100000>, <1100000>; - - s5m8767,pmic-buck4-dvs-voltage = <1200000>, <1200000>, - <1200000>, <1200000>, - <1200000>, <1200000>, - <1200000>, <1200000>; - - regulators { - ldo1_reg: LDO1 { - regulator-name = "VDD_ALIVE"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo2_reg: LDO2 { - regulator-name = "VDDQ_M12"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo3_reg: LDO3 { - regulator-name = "VDDIOAP_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo4_reg: LDO4 { - regulator-name = "VDDQ_PRE"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo5_reg: LDO5 { - regulator-name = "VDD18_2M"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo6_reg: LDO6 { - regulator-name = "VDD10_MPLL"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo7_reg: LDO7 { - regulator-name = "VDD10_XPLL"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo8_reg: LDO8 { - regulator-name = "VDD10_MIPI"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo9_reg: LDO9 { - regulator-name = "VDD33_LCD"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo10_reg: LDO10 { - regulator-name = "VDD18_MIPI"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo11_reg: LDO11 { - regulator-name = "VDD18_ABB1"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo12_reg: LDO12 { - regulator-name = "VDD33_UOTG"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo13_reg: LDO13 { - regulator-name = "VDDIOPERI_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo14_reg: LDO14 { - regulator-name = "VDD18_ABB02"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo15_reg: LDO15 { - regulator-name = "VDD10_USH"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo16_reg: LDO16 { - regulator-name = "VDD18_HSIC"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo17_reg: LDO17 { - regulator-name = "VDDIOAP_MMC012_28"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo18_reg: LDO18 { - regulator-name = "VDDIOPERI_28"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo19_reg: LDO19 { - regulator-name = "DVDD25"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo20_reg: LDO20 { - regulator-name = "VDD28_CAM"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo21_reg: LDO21 { - regulator-name = "VDD28_AF"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo22_reg: LDO22 { - regulator-name = "VDDA28_2M"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo23_reg: LDO23 { - regulator-name = "VDD28_TF"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo24_reg: LDO24 { - regulator-name = "VDD33_A31"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo25_reg: LDO25 { - regulator-name = "VDD18_CAM"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo26_reg: LDO26 { - regulator-name = "VDD18_A31"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo27_reg: LDO27 { - regulator-name = "GPS_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo28_reg: LDO28 { - regulator-name = "DVDD12"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - buck1_reg: BUCK1 { - regulator-name = "vdd_mif"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; /* Normal Mode */ - }; - - buck2_reg: BUCK2 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; /* Normal Mode */ - }; - - buck3_reg: BUCK3 { - regulator-name = "vdd_int"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; /* Normal Mode */ - }; - - buck4_reg: BUCK4 { - regulator-name = "vdd_g3d"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; /* Normal Mode */ - }; - - buck5_reg: BUCK5 { - regulator-name = "vdd_m12"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; /* Normal Mode */ - }; - - buck6_reg: BUCK6 { - regulator-name = "vdd12_5m"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; /* Normal Mode */ - }; - - buck9_reg: BUCK9 { - regulator-name = "vddf28_emmc"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; /* Normal Mode */ - }; - }; - }; -}; - -&keypad { - samsung,keypad-num-rows = <3>; - samsung,keypad-num-columns = <2>; - linux,keypad-no-autorepeat; - wakeup-source; - pinctrl-0 = <&keypad_rows &keypad_cols>; - pinctrl-names = "default"; - status = "okay"; - - key_home { - keypad,row = <0>; - keypad,column = <0>; - linux,code = ; - }; - - key_down { - keypad,row = <0>; - keypad,column = <1>; - linux,code = ; - }; - - key_up { - keypad,row = <1>; - keypad,column = <0>; - linux,code = ; - }; - - key_menu { - keypad,row = <1>; - keypad,column = <1>; - linux,code = ; - }; - - key_back { - keypad,row = <2>; - keypad,column = <0>; - linux,code = ; - }; - - key_enter { - keypad,row = <2>; - keypad,column = <1>; - linux,code = ; - }; -}; - -&mshc_0 { - pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>; - pinctrl-names = "default"; - status = "okay"; - - broken-cd; - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; - bus-width = <8>; - cap-mmc-highspeed; -}; - -&pinctrl_1 { - keypad_rows: keypad-rows { - samsung,pins = "gpx2-0", "gpx2-1", "gpx2-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - keypad_cols: keypad-cols { - samsung,pins = "gpx1-0", "gpx1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&rtc { - status = "okay"; -}; - -&sdhci_2 { - bus-width = <4>; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sd2_cd>; - pinctrl-names = "default"; - vmmc-supply = <&mmc_reg>; - status = "okay"; -}; - -&serial_0 { - status = "okay"; -}; - -&serial_1 { - status = "okay"; -}; - -&serial_2 { - status = "okay"; -}; - -&serial_3 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/exynos4412-pinctrl.dtsi b/sys/gnu/dts/arm/exynos4412-pinctrl.dtsi deleted file mode 100644 index d7d5fdc230d..00000000000 --- a/sys/gnu/dts/arm/exynos4412-pinctrl.dtsi +++ /dev/null @@ -1,979 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's Exynos4412 SoCs pin-mux and pin-config device tree source - * - * Copyright (c) 2012 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Samsung's Exynos4412 SoCs pin-mux and pin-config optiosn are listed as device - * tree nodes are listed in this file. - */ - -#include - -#define PIN_SLP(_pin, _mode, _pull) \ - _pin { \ - samsung,pins = #_pin; \ - samsung,pin-con-pdn = ; \ - samsung,pin-pud-pdn = ; \ - } - -&pinctrl_0 { - gpa0: gpa0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpa1: gpa1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpb: gpb { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc0: gpc0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc1: gpc1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpd0: gpd0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpd1: gpd1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf0: gpf0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf1: gpf1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf2: gpf2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf3: gpf3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpj0: gpj0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpj1: gpj1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - uart0_data: uart0-data { - samsung,pins = "gpa0-0", "gpa0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart0_fctl: uart0-fctl { - samsung,pins = "gpa0-2", "gpa0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart1_data: uart1-data { - samsung,pins = "gpa0-4", "gpa0-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart1_fctl: uart1-fctl { - samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c2_bus: i2c2-bus { - samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart2_data: uart2-data { - samsung,pins = "gpa1-0", "gpa1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart2_fctl: uart2-fctl { - samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart_audio_a: uart-audio-a { - samsung,pins = "gpa1-0", "gpa1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c3_bus: i2c3-bus { - samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart3_data: uart3-data { - samsung,pins = "gpa1-4", "gpa1-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart_audio_b: uart-audio-b { - samsung,pins = "gpa1-4", "gpa1-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spi0_bus: spi0-bus { - samsung,pins = "gpb-0", "gpb-2", "gpb-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c4_bus: i2c4-bus { - samsung,pins = "gpb-0", "gpb-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spi1_bus: spi1-bus { - samsung,pins = "gpb-4", "gpb-6", "gpb-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c5_bus: i2c5-bus { - samsung,pins = "gpb-2", "gpb-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2s1_bus: i2s1-bus { - samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", - "gpc0-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pcm1_bus: pcm1-bus { - samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", - "gpc0-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - ac97_bus: ac97-bus { - samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", - "gpc0-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2s2_bus: i2s2-bus { - samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", - "gpc1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pcm2_bus: pcm2-bus { - samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", - "gpc1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spdif_bus: spdif-bus { - samsung,pins = "gpc1-0", "gpc1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c6_bus: i2c6-bus { - samsung,pins = "gpc1-3", "gpc1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spi2_bus: spi2-bus { - samsung,pins = "gpc1-1", "gpc1-3", "gpc1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm0_out: pwm0-out { - samsung,pins = "gpd0-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm1_out: pwm1-out { - samsung,pins = "gpd0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - lcd_ctrl: lcd-ctrl { - samsung,pins = "gpd0-0", "gpd0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c7_bus: i2c7-bus { - samsung,pins = "gpd0-2", "gpd0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm2_out: pwm2-out { - samsung,pins = "gpd0-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm3_out: pwm3-out { - samsung,pins = "gpd0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c0_bus: i2c0-bus { - samsung,pins = "gpd1-0", "gpd1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - mipi0_clk: mipi0-clk { - samsung,pins = "gpd1-0", "gpd1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c1_bus: i2c1-bus { - samsung,pins = "gpd1-2", "gpd1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - mipi1_clk: mipi1-clk { - samsung,pins = "gpd1-2", "gpd1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - lcd_clk: lcd-clk { - samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - lcd_data16: lcd-data-width16 { - samsung,pins = "gpf0-7", "gpf1-0", "gpf1-1", "gpf1-2", - "gpf1-3", "gpf1-6", "gpf1-7", "gpf2-0", - "gpf2-1", "gpf2-2", "gpf2-3", "gpf2-7", - "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - lcd_data18: lcd-data-width18 { - samsung,pins = "gpf0-6", "gpf0-7", "gpf1-0", "gpf1-1", - "gpf1-2", "gpf1-3", "gpf1-6", "gpf1-7", - "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3", - "gpf2-6", "gpf2-7", "gpf3-0", "gpf3-1", - "gpf3-2", "gpf3-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - lcd_data24: lcd-data-width24 { - samsung,pins = "gpf0-4", "gpf0-5", "gpf0-6", "gpf0-7", - "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3", - "gpf1-4", "gpf1-5", "gpf1-6", "gpf1-7", - "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3", - "gpf2-4", "gpf2-5", "gpf2-6", "gpf2-7", - "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - lcd_ldi: lcd-ldi { - samsung,pins = "gpf3-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_port_a_io: cam-port-a-io { - samsung,pins = "gpj0-0", "gpj0-1", "gpj0-2", "gpj0-3", - "gpj0-4", "gpj0-5", "gpj0-6", "gpj0-7", - "gpj1-0", "gpj1-1", "gpj1-2", "gpj1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_port_a_clk_active: cam-port-a-clk-active { - samsung,pins = "gpj1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_port_a_clk_idle: cam-port-a-clk-idle { - samsung,pins = "gpj1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pinctrl_1 { - gpk0: gpk0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpk1: gpk1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpk2: gpk2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpk3: gpk3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpl0: gpl0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpl1: gpl1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpl2: gpl2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpm0: gpm0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpm1: gpm1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpm2: gpm2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpm3: gpm3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpm4: gpm4 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpy0: gpy0 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy1: gpy1 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy2: gpy2 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy3: gpy3 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy4: gpy4 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy5: gpy5 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy6: gpy6 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpx0: gpx0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - interrupt-parent = <&gic>; - interrupts = , - , - , - , - , - , - , - ; - #interrupt-cells = <2>; - }; - - gpx1: gpx1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - interrupt-parent = <&gic>; - interrupts = , - , - , - , - , - , - , - ; - #interrupt-cells = <2>; - }; - - gpx2: gpx2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpx3: gpx3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - sd0_clk: sd0-clk { - samsung,pins = "gpk0-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_cmd: sd0-cmd { - samsung,pins = "gpk0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_cd: sd0-cd { - samsung,pins = "gpk0-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus1: sd0-bus-width1 { - samsung,pins = "gpk0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus4: sd0-bus-width4 { - samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus8: sd0-bus-width8 { - samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd4_clk: sd4-clk { - samsung,pins = "gpk0-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd4_cmd: sd4-cmd { - samsung,pins = "gpk0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd4_cd: sd4-cd { - samsung,pins = "gpk0-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd4_bus1: sd4-bus-width1 { - samsung,pins = "gpk0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd4_bus4: sd4-bus-width4 { - samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd4_bus8: sd4-bus-width8 { - samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_clk: sd1-clk { - samsung,pins = "gpk1-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_cmd: sd1-cmd { - samsung,pins = "gpk1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_cd: sd1-cd { - samsung,pins = "gpk1-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_bus1: sd1-bus-width1 { - samsung,pins = "gpk1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_bus4: sd1-bus-width4 { - samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_clk: sd2-clk { - samsung,pins = "gpk2-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_cmd: sd2-cmd { - samsung,pins = "gpk2-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_cd: sd2-cd { - samsung,pins = "gpk2-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_bus1: sd2-bus-width1 { - samsung,pins = "gpk2-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_bus4: sd2-bus-width4 { - samsung,pins = "gpk2-3", "gpk2-4", "gpk2-5", "gpk2-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_bus8: sd2-bus-width8 { - samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd3_clk: sd3-clk { - samsung,pins = "gpk3-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd3_cmd: sd3-cmd { - samsung,pins = "gpk3-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd3_cd: sd3-cd { - samsung,pins = "gpk3-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd3_bus1: sd3-bus-width1 { - samsung,pins = "gpk3-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd3_bus4: sd3-bus-width4 { - samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_port_b_io: cam-port-b-io { - samsung,pins = "gpm0-0", "gpm0-1", "gpm0-2", "gpm0-3", - "gpm0-4", "gpm0-5", "gpm0-6", "gpm0-7", - "gpm1-0", "gpm1-1", "gpm2-0", "gpm2-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_port_b_clk_active: cam-port-b-clk-active { - samsung,pins = "gpm2-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_port_b_clk_idle: cam-port-b-clk-idle { - samsung,pins = "gpm2-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - eint0: ext-int0 { - samsung,pins = "gpx0-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - eint8: ext-int8 { - samsung,pins = "gpx1-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - eint15: ext-int15 { - samsung,pins = "gpx1-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - eint16: ext-int16 { - samsung,pins = "gpx2-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - eint31: ext-int31 { - samsung,pins = "gpx3-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - fimc_is_i2c0: fimc-is-i2c0 { - samsung,pins = "gpm4-0", "gpm4-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - fimc_is_i2c1: fimc-is-i2c1 { - samsung,pins = "gpm4-2", "gpm4-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - fimc_is_uart: fimc-is-uart { - samsung,pins = "gpm3-5", "gpm3-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - hdmi_cec: hdmi-cec { - samsung,pins = "gpx3-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pinctrl_2 { - gpz: gpz { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - i2s0_bus: i2s0-bus { - samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", - "gpz-4", "gpz-5", "gpz-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pcm0_bus: pcm0-bus { - samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", - "gpz-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pinctrl_3 { - gpv0: gpv0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpv1: gpv1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpv2: gpv2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpv3: gpv3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpv4: gpv4 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - c2c_bus: c2c-bus { - samsung,pins = "gpv0-0", "gpv0-1", "gpv0-2", "gpv0-3", - "gpv0-4", "gpv0-5", "gpv0-6", "gpv0-7", - "gpv1-0", "gpv1-1", "gpv1-2", "gpv1-3", - "gpv1-4", "gpv1-5", "gpv1-6", "gpv1-7", - "gpv2-0", "gpv2-1", "gpv2-2", "gpv2-3", - "gpv2-4", "gpv2-5", "gpv2-6", "gpv2-7", - "gpv3-0", "gpv3-1", "gpv3-2", "gpv3-3", - "gpv3-4", "gpv3-5", "gpv3-6", "gpv3-7", - "gpv4-0", "gpv4-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; diff --git a/sys/gnu/dts/arm/exynos4412-ppmu-common.dtsi b/sys/gnu/dts/arm/exynos4412-ppmu-common.dtsi deleted file mode 100644 index 3a3b2fafefd..00000000000 --- a/sys/gnu/dts/arm/exynos4412-ppmu-common.dtsi +++ /dev/null @@ -1,47 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device tree sources for Exynos4412 PPMU common device tree - * - * Copyright (C) 2015 Samsung Electronics - * Author: Chanwoo Choi - */ - -&ppmu_dmc0 { - status = "okay"; - - events { - ppmu_dmc0_3: ppmu-event3-dmc0 { - event-name = "ppmu-event3-dmc0"; - }; - }; -}; - -&ppmu_dmc1 { - status = "okay"; - - events { - ppmu_dmc1_3: ppmu-event3-dmc1 { - event-name = "ppmu-event3-dmc1"; - }; - }; -}; - -&ppmu_leftbus { - status = "okay"; - - events { - ppmu_leftbus_3: ppmu-event3-leftbus { - event-name = "ppmu-event3-leftbus"; - }; - }; -}; - -&ppmu_rightbus { - status = "okay"; - - events { - ppmu_rightbus_3: ppmu-event3-rightbus { - event-name = "ppmu-event3-rightbus"; - }; - }; -}; diff --git a/sys/gnu/dts/arm/exynos4412-prime.dtsi b/sys/gnu/dts/arm/exynos4412-prime.dtsi deleted file mode 100644 index 3731a225f77..00000000000 --- a/sys/gnu/dts/arm/exynos4412-prime.dtsi +++ /dev/null @@ -1,47 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's Exynos4412 Prime SoC device tree source - * - * Copyright (c) 2016 Samsung Electronics Co., Ltd. - * http://www.samsung.com - */ - -/* - * Exynos4412 Prime SoC revision supports higher CPU frequencies than - * non-Prime version. Therefore we need to update OPPs table and - * thermal maps accordingly. - */ - -&cpu0_opp_1500 { - /delete-property/turbo-mode; -}; - -&cpu0_opp_table { - opp-1600000000 { - opp-hz = /bits/ 64 <1600000000>; - opp-microvolt = <1350000>; - clock-latency-ns = <200000>; - }; - opp-1704000000 { - opp-hz = /bits/ 64 <1704000000>; - opp-microvolt = <1350000>; - clock-latency-ns = <200000>; - }; -}; - -&cooling_map0 { - cooling-device = <&cpu0 9 9>, <&cpu1 9 9>, - <&cpu2 9 9>, <&cpu3 9 9>; -}; - -&cooling_map1 { - cooling-device = <&cpu0 15 15>, <&cpu1 15 15>, - <&cpu2 15 15>, <&cpu3 15 15>; -}; - -&gpu_opp_table { - opp-533000000 { - opp-hz = /bits/ 64 <533000000>; - opp-microvolt = <1075000>; - }; -}; diff --git a/sys/gnu/dts/arm/exynos4412-smdk4412.dts b/sys/gnu/dts/arm/exynos4412-smdk4412.dts deleted file mode 100644 index e70fb6e601f..00000000000 --- a/sys/gnu/dts/arm/exynos4412-smdk4412.dts +++ /dev/null @@ -1,151 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's Exynos4412 based SMDK board device tree source - * - * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Device tree source file for Samsung's SMDK4412 board which is based on - * Samsung's Exynos4412 SoC. - */ - -/dts-v1/; -#include "exynos4412.dtsi" -#include "exynos-mfc-reserved-memory.dtsi" - -/ { - model = "Samsung SMDK evaluation board based on Exynos4412"; - compatible = "samsung,smdk4412", "samsung,exynos4412", "samsung,exynos4"; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x40000000>; - }; - - chosen { - bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M init=/linuxrc"; - stdout-path = "serial1:115200n8"; - }; - - fixed-rate-clocks { - xxti { - compatible = "samsung,clock-xxti"; - clock-frequency = <0>; - }; - - xusbxti { - compatible = "samsung,clock-xusbxti"; - clock-frequency = <24000000>; - }; - }; -}; - -&keypad { - samsung,keypad-num-rows = <3>; - samsung,keypad-num-columns = <8>; - linux,keypad-no-autorepeat; - wakeup-source; - pinctrl-0 = <&keypad_rows &keypad_cols>; - pinctrl-names = "default"; - status = "okay"; - - key_1 { - keypad,row = <1>; - keypad,column = <3>; - linux,code = <2>; - }; - - key_2 { - keypad,row = <1>; - keypad,column = <4>; - linux,code = <3>; - }; - - key_3 { - keypad,row = <1>; - keypad,column = <5>; - linux,code = <4>; - }; - - key_4 { - keypad,row = <1>; - keypad,column = <6>; - linux,code = <5>; - }; - - key_5 { - keypad,row = <1>; - keypad,column = <7>; - linux,code = <6>; - }; - - key_A { - keypad,row = <2>; - keypad,column = <6>; - linux,code = <30>; - }; - - key_B { - keypad,row = <2>; - keypad,column = <7>; - linux,code = <48>; - }; - - key_C { - keypad,row = <0>; - keypad,column = <5>; - linux,code = <46>; - }; - - key_D { - keypad,row = <2>; - keypad,column = <5>; - linux,code = <32>; - }; - - key_E { - keypad,row = <0>; - keypad,column = <7>; - linux,code = <18>; - }; -}; - -&pinctrl_1 { - keypad_rows: keypad-rows { - samsung,pins = "gpx2-0", "gpx2-1", "gpx2-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - keypad_cols: keypad-cols { - samsung,pins = "gpx1-0", "gpx1-1", "gpx1-2", "gpx1-3", - "gpx1-4", "gpx1-5", "gpx1-6", "gpx1-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&sdhci_2 { - bus-width = <4>; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sd2_cd>; - pinctrl-names = "default"; - status = "okay"; -}; - -&serial_0 { - status = "okay"; -}; - -&serial_1 { - status = "okay"; -}; - -&serial_2 { - status = "okay"; -}; - -&serial_3 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/exynos4412-tiny4412.dts b/sys/gnu/dts/arm/exynos4412-tiny4412.dts deleted file mode 100644 index 3a91de8a808..00000000000 --- a/sys/gnu/dts/arm/exynos4412-tiny4412.dts +++ /dev/null @@ -1,121 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * FriendlyARM's Exynos4412 based TINY4412 board device tree source - * - * Copyright (c) 2013 Alex Ling - * - * Device tree source file for FriendlyARM's TINY4412 board which is based on - * Samsung's Exynos4412 SoC. - */ - -/dts-v1/; -#include "exynos4412.dtsi" -#include - -/ { - model = "FriendlyARM TINY4412 board based on Exynos4412"; - compatible = "friendlyarm,tiny4412", "samsung,exynos4412", "samsung,exynos4"; - - chosen { - stdout-path = &serial_0; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x40000000>; - }; - - leds { - compatible = "gpio-leds"; - - led1 { - label = "led1"; - gpios = <&gpm4 0 GPIO_ACTIVE_LOW>; - default-state = "off"; - linux,default-trigger = "heartbeat"; - }; - - led2 { - label = "led2"; - gpios = <&gpm4 1 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led3 { - label = "led3"; - gpios = <&gpm4 2 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led4 { - label = "led4"; - gpios = <&gpm4 3 GPIO_ACTIVE_LOW>; - default-state = "off"; - linux,default-trigger = "mmc0"; - }; - }; - - fixed-rate-clocks { - xxti { - compatible = "samsung,clock-xxti"; - clock-frequency = <0>; - }; - - xusbxti { - compatible = "samsung,clock-xusbxti"; - clock-frequency = <24000000>; - }; - }; - - panel { - compatible = "innolux,at070tn92"; - - port { - panel_input: endpoint { - remote-endpoint = <&lcdc_output>; - }; - }; - }; -}; - -&fimd { - pinctrl-0 = <&lcd_clk>, <&lcd_data24>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - port@3 { - reg = <3>; - lcdc_output: endpoint { - remote-endpoint = <&panel_input>; - }; - }; -}; - -&rtc { - status = "okay"; -}; - -&sdhci_2 { - bus-width = <4>; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; - pinctrl-names = "default"; - status = "okay"; -}; - -&serial_0 { - status = "okay"; -}; - -&serial_1 { - status = "okay"; -}; - -&serial_2 { - status = "okay"; -}; - -&serial_3 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/exynos4412-tmu-sensor-conf.dtsi b/sys/gnu/dts/arm/exynos4412-tmu-sensor-conf.dtsi deleted file mode 100644 index e3f7934d19d..00000000000 --- a/sys/gnu/dts/arm/exynos4412-tmu-sensor-conf.dtsi +++ /dev/null @@ -1,24 +0,0 @@ -/* - * Device tree sources for Exynos4412 TMU sensor configuration - * - * Copyright (c) 2014 Lukasz Majewski - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -#include - -#thermal-sensor-cells = <0>; -samsung,tmu_gain = <8>; -samsung,tmu_reference_voltage = <16>; -samsung,tmu_noise_cancel_mode = <4>; -samsung,tmu_efuse_value = <55>; -samsung,tmu_min_efuse_value = <40>; -samsung,tmu_max_efuse_value = <100>; -samsung,tmu_first_point_trim = <25>; -samsung,tmu_second_point_trim = <85>; -samsung,tmu_default_temp_offset = <50>; -samsung,tmu_cal_type = ; diff --git a/sys/gnu/dts/arm/exynos4412-trats2.dts b/sys/gnu/dts/arm/exynos4412-trats2.dts deleted file mode 100644 index aac533933c6..00000000000 --- a/sys/gnu/dts/arm/exynos4412-trats2.dts +++ /dev/null @@ -1,28 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's Exynos4412 based Trats 2 board device tree source - * - * Copyright (c) 2013 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Device tree source file for Samsung's Trats 2 board which is based on - * Samsung's Exynos4412 SoC. - */ - -/dts-v1/; -#include "exynos4412-galaxy-s3.dtsi" - -/ { - model = "Samsung Trats 2 based on Exynos4412"; - compatible = "samsung,trats2", "samsung,midas", "samsung,exynos4412", "samsung,exynos4"; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x40000000>; - }; - - chosen { - bootargs = "root=/dev/mmcblk0p5 rootwait earlyprintk panic=5"; - stdout-path = "serial2:115200n8"; - }; -}; diff --git a/sys/gnu/dts/arm/exynos4412.dtsi b/sys/gnu/dts/arm/exynos4412.dtsi deleted file mode 100644 index 48868947373..00000000000 --- a/sys/gnu/dts/arm/exynos4412.dtsi +++ /dev/null @@ -1,802 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's Exynos4412 SoC device tree source - * - * Copyright (c) 2012 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Samsung's Exynos4412 SoC device nodes are listed in this file. Exynos4412 - * based board files can include this file and provide values for board specfic - * bindings. - * - * Note: This file does not include device nodes for all the controllers in - * Exynos4412 SoC. As device tree coverage for Exynos4412 increases, additional - * nodes can be added to this file. - */ - -#include "exynos4.dtsi" - -#include "exynos4-cpu-thermal.dtsi" - -/ { - compatible = "samsung,exynos4412", "samsung,exynos4"; - - aliases { - pinctrl0 = &pinctrl_0; - pinctrl1 = &pinctrl_1; - pinctrl2 = &pinctrl_2; - pinctrl3 = &pinctrl_3; - fimc-lite0 = &fimc_lite_0; - fimc-lite1 = &fimc_lite_1; - mshc0 = &mshc_0; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@a00 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0xA00>; - clocks = <&clock CLK_ARM_CLK>; - clock-names = "cpu"; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - }; - - cpu1: cpu@a01 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0xA01>; - clocks = <&clock CLK_ARM_CLK>; - clock-names = "cpu"; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - }; - - cpu2: cpu@a02 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0xA02>; - clocks = <&clock CLK_ARM_CLK>; - clock-names = "cpu"; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - }; - - cpu3: cpu@a03 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0xA03>; - clocks = <&clock CLK_ARM_CLK>; - clock-names = "cpu"; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - }; - }; - - cpu0_opp_table: opp_table0 { - compatible = "operating-points-v2"; - opp-shared; - - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - opp-microvolt = <900000>; - clock-latency-ns = <200000>; - }; - opp-300000000 { - opp-hz = /bits/ 64 <300000000>; - opp-microvolt = <900000>; - clock-latency-ns = <200000>; - }; - opp-400000000 { - opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <925000>; - clock-latency-ns = <200000>; - }; - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <950000>; - clock-latency-ns = <200000>; - }; - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <975000>; - clock-latency-ns = <200000>; - }; - opp-700000000 { - opp-hz = /bits/ 64 <700000000>; - opp-microvolt = <987500>; - clock-latency-ns = <200000>; - }; - opp-800000000 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <1000000>; - clock-latency-ns = <200000>; - opp-suspend; - }; - opp-900000000 { - opp-hz = /bits/ 64 <900000000>; - opp-microvolt = <1037500>; - clock-latency-ns = <200000>; - }; - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <1087500>; - clock-latency-ns = <200000>; - }; - opp-1100000000 { - opp-hz = /bits/ 64 <1100000000>; - opp-microvolt = <1137500>; - clock-latency-ns = <200000>; - }; - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <1187500>; - clock-latency-ns = <200000>; - }; - opp-1300000000 { - opp-hz = /bits/ 64 <1300000000>; - opp-microvolt = <1250000>; - clock-latency-ns = <200000>; - }; - opp-1400000000 { - opp-hz = /bits/ 64 <1400000000>; - opp-microvolt = <1287500>; - clock-latency-ns = <200000>; - }; - cpu0_opp_1500: opp-1500000000 { - opp-hz = /bits/ 64 <1500000000>; - opp-microvolt = <1350000>; - clock-latency-ns = <200000>; - turbo-mode; - }; - }; - - - soc: soc { - - pinctrl_0: pinctrl@11400000 { - compatible = "samsung,exynos4x12-pinctrl"; - reg = <0x11400000 0x1000>; - interrupts = ; - }; - - pinctrl_1: pinctrl@11000000 { - compatible = "samsung,exynos4x12-pinctrl"; - reg = <0x11000000 0x1000>; - interrupts = ; - - wakup_eint: wakeup-interrupt-controller { - compatible = "samsung,exynos4210-wakeup-eint"; - interrupt-parent = <&gic>; - interrupts = ; - }; - }; - - pinctrl_2: pinctrl@3860000 { - compatible = "samsung,exynos4x12-pinctrl"; - reg = <0x03860000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <10 0>; - }; - - pinctrl_3: pinctrl@106e0000 { - compatible = "samsung,exynos4x12-pinctrl"; - reg = <0x106E0000 0x1000>; - interrupts = ; - }; - - sram@2020000 { - compatible = "mmio-sram"; - reg = <0x02020000 0x40000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x02020000 0x40000>; - - smp-sram@0 { - compatible = "samsung,exynos4210-sysram"; - reg = <0x0 0x1000>; - }; - - smp-sram@2f000 { - compatible = "samsung,exynos4210-sysram-ns"; - reg = <0x2f000 0x1000>; - }; - }; - - pd_isp: power-domain@10023ca0 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10023CA0 0x20>; - #power-domain-cells = <0>; - label = "ISP"; - }; - - l2c: l2-cache-controller@10502000 { - compatible = "arm,pl310-cache"; - reg = <0x10502000 0x1000>; - cache-unified; - cache-level = <2>; - arm,tag-latency = <2 2 1>; - arm,data-latency = <3 2 1>; - arm,double-linefill = <1>; - arm,double-linefill-incr = <0>; - arm,double-linefill-wrap = <1>; - arm,prefetch-drop = <1>; - arm,prefetch-offset = <7>; - }; - - clock: clock-controller@10030000 { - compatible = "samsung,exynos4412-clock"; - reg = <0x10030000 0x18000>; - #clock-cells = <1>; - }; - - isp_clock: clock-controller@10048000 { - compatible = "samsung,exynos4412-isp-clock"; - reg = <0x10048000 0x1000>; - #clock-cells = <1>; - power-domains = <&pd_isp>; - clocks = <&clock CLK_ACLK200>, - <&clock CLK_ACLK400_MCUISP>; - clock-names = "aclk200", "aclk400_mcuisp"; - }; - - timer@10050000 { - compatible = "samsung,exynos4412-mct"; - reg = <0x10050000 0x800>; - clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; - clock-names = "fin_pll", "mct"; - interrupts-extended = <&gic GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, - <&combiner 12 5>, - <&combiner 12 6>, - <&combiner 12 7>, - <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH>; - }; - - watchdog: watchdog@10060000 { - compatible = "samsung,exynos5250-wdt"; - reg = <0x10060000 0x100>; - interrupts = ; - clocks = <&clock CLK_WDT>; - clock-names = "watchdog"; - samsung,syscon-phandle = <&pmu_system_controller>; - }; - - adc: adc@126c0000 { - compatible = "samsung,exynos4212-adc"; - reg = <0x126C0000 0x100>; - interrupt-parent = <&combiner>; - interrupts = <10 3>; - clocks = <&clock CLK_TSADC>; - clock-names = "adc"; - #io-channel-cells = <1>; - io-channel-ranges; - samsung,syscon-phandle = <&pmu_system_controller>; - status = "disabled"; - }; - - g2d: g2d@10800000 { - compatible = "samsung,exynos4212-g2d"; - reg = <0x10800000 0x1000>; - interrupts = ; - clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>; - clock-names = "sclk_fimg2d", "fimg2d"; - iommus = <&sysmmu_g2d>; - }; - - mshc_0: mmc@12550000 { - compatible = "samsung,exynos4412-dw-mshc"; - reg = <0x12550000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - fifo-depth = <0x80>; - clocks = <&clock CLK_SDMMC4>, <&clock CLK_SCLK_MMC4>; - clock-names = "biu", "ciu"; - status = "disabled"; - }; - - sysmmu_g2d: sysmmu@10a40000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x10A40000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <4 7>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>; - #iommu-cells = <0>; - }; - - sysmmu_fimc_isp: sysmmu@12260000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x12260000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <16 2>; - power-domains = <&pd_isp>; - clock-names = "sysmmu"; - clocks = <&isp_clock CLK_ISP_SMMU_ISP>; - #iommu-cells = <0>; - }; - - sysmmu_fimc_drc: sysmmu@12270000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x12270000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <16 3>; - power-domains = <&pd_isp>; - clock-names = "sysmmu"; - clocks = <&isp_clock CLK_ISP_SMMU_DRC>; - #iommu-cells = <0>; - }; - - sysmmu_fimc_fd: sysmmu@122a0000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x122A0000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <16 4>; - power-domains = <&pd_isp>; - clock-names = "sysmmu"; - clocks = <&isp_clock CLK_ISP_SMMU_FD>; - #iommu-cells = <0>; - }; - - sysmmu_fimc_mcuctl: sysmmu@122b0000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x122B0000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <16 5>; - power-domains = <&pd_isp>; - clock-names = "sysmmu"; - clocks = <&isp_clock CLK_ISP_SMMU_ISPCX>; - #iommu-cells = <0>; - }; - - sysmmu_fimc_lite0: sysmmu@123b0000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x123B0000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <16 0>; - power-domains = <&pd_isp>; - clock-names = "sysmmu", "master"; - clocks = <&isp_clock CLK_ISP_SMMU_LITE0>, - <&isp_clock CLK_ISP_FIMC_LITE0>; - #iommu-cells = <0>; - }; - - sysmmu_fimc_lite1: sysmmu@123c0000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x123C0000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <16 1>; - power-domains = <&pd_isp>; - clock-names = "sysmmu", "master"; - clocks = <&isp_clock CLK_ISP_SMMU_LITE1>, - <&isp_clock CLK_ISP_FIMC_LITE1>; - #iommu-cells = <0>; - }; - - bus_dmc: bus_dmc { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DIV_DMC>; - clock-names = "bus"; - operating-points-v2 = <&bus_dmc_opp_table>; - status = "disabled"; - }; - - bus_acp: bus_acp { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DIV_ACP>; - clock-names = "bus"; - operating-points-v2 = <&bus_acp_opp_table>; - status = "disabled"; - }; - - bus_c2c: bus_c2c { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DIV_C2C>; - clock-names = "bus"; - operating-points-v2 = <&bus_dmc_opp_table>; - status = "disabled"; - }; - - bus_dmc_opp_table: opp_table1 { - compatible = "operating-points-v2"; - opp-shared; - - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - opp-microvolt = <900000>; - }; - opp-134000000 { - opp-hz = /bits/ 64 <134000000>; - opp-microvolt = <900000>; - }; - opp-160000000 { - opp-hz = /bits/ 64 <160000000>; - opp-microvolt = <900000>; - }; - opp-267000000 { - opp-hz = /bits/ 64 <267000000>; - opp-microvolt = <950000>; - }; - opp-400000000 { - opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <1050000>; - opp-suspend; - }; - }; - - bus_acp_opp_table: opp_table2 { - compatible = "operating-points-v2"; - opp-shared; - - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - }; - opp-134000000 { - opp-hz = /bits/ 64 <134000000>; - }; - opp-160000000 { - opp-hz = /bits/ 64 <160000000>; - }; - opp-267000000 { - opp-hz = /bits/ 64 <267000000>; - }; - }; - - bus_leftbus: bus_leftbus { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DIV_GDL>; - clock-names = "bus"; - operating-points-v2 = <&bus_leftbus_opp_table>; - status = "disabled"; - }; - - bus_rightbus: bus_rightbus { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DIV_GDR>; - clock-names = "bus"; - operating-points-v2 = <&bus_leftbus_opp_table>; - status = "disabled"; - }; - - bus_display: bus_display { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_ACLK160>; - clock-names = "bus"; - operating-points-v2 = <&bus_display_opp_table>; - status = "disabled"; - }; - - bus_fsys: bus_fsys { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_ACLK133>; - clock-names = "bus"; - operating-points-v2 = <&bus_fsys_opp_table>; - status = "disabled"; - }; - - bus_peri: bus_peri { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_ACLK100>; - clock-names = "bus"; - operating-points-v2 = <&bus_peri_opp_table>; - status = "disabled"; - }; - - bus_mfc: bus_mfc { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_SCLK_MFC>; - clock-names = "bus"; - operating-points-v2 = <&bus_leftbus_opp_table>; - status = "disabled"; - }; - - bus_leftbus_opp_table: opp_table3 { - compatible = "operating-points-v2"; - opp-shared; - - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - opp-microvolt = <900000>; - }; - opp-134000000 { - opp-hz = /bits/ 64 <134000000>; - opp-microvolt = <925000>; - }; - opp-160000000 { - opp-hz = /bits/ 64 <160000000>; - opp-microvolt = <950000>; - }; - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - opp-microvolt = <1000000>; - opp-suspend; - }; - }; - - bus_display_opp_table: opp_table4 { - compatible = "operating-points-v2"; - opp-shared; - - opp-160000000 { - opp-hz = /bits/ 64 <160000000>; - }; - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - }; - }; - - bus_fsys_opp_table: opp_table5 { - compatible = "operating-points-v2"; - opp-shared; - - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - }; - opp-134000000 { - opp-hz = /bits/ 64 <134000000>; - }; - }; - - bus_peri_opp_table: opp_table6 { - compatible = "operating-points-v2"; - opp-shared; - - opp-50000000 { - opp-hz = /bits/ 64 <50000000>; - }; - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - }; - }; - }; -}; - -&combiner { - samsung,combiner-nr = <20>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; -}; - -&camera { - clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>, - <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>; - clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1"; - - /* fimc_[0-3] are configured outside, under phandles */ - fimc_lite_0: fimc-lite@12390000 { - compatible = "samsung,exynos4212-fimc-lite"; - reg = <0x12390000 0x1000>; - interrupts = ; - power-domains = <&pd_isp>; - clocks = <&isp_clock CLK_ISP_FIMC_LITE0>; - clock-names = "flite"; - iommus = <&sysmmu_fimc_lite0>; - status = "disabled"; - }; - - fimc_lite_1: fimc-lite@123a0000 { - compatible = "samsung,exynos4212-fimc-lite"; - reg = <0x123A0000 0x1000>; - interrupts = ; - power-domains = <&pd_isp>; - clocks = <&isp_clock CLK_ISP_FIMC_LITE1>; - clock-names = "flite"; - iommus = <&sysmmu_fimc_lite1>; - status = "disabled"; - }; - - fimc_is: fimc-is@12000000 { - compatible = "samsung,exynos4212-fimc-is"; - reg = <0x12000000 0x260000>; - interrupts = , - ; - power-domains = <&pd_isp>; - clocks = <&isp_clock CLK_ISP_FIMC_LITE0>, - <&isp_clock CLK_ISP_FIMC_LITE1>, - <&isp_clock CLK_ISP_PPMUISPX>, - <&isp_clock CLK_ISP_PPMUISPMX>, - <&isp_clock CLK_ISP_FIMC_ISP>, - <&isp_clock CLK_ISP_FIMC_DRC>, - <&isp_clock CLK_ISP_FIMC_FD>, - <&isp_clock CLK_ISP_MCUISP>, - <&isp_clock CLK_ISP_GICISP>, - <&isp_clock CLK_ISP_MCUCTL_ISP>, - <&isp_clock CLK_ISP_PWM_ISP>, - <&isp_clock CLK_ISP_DIV_ISP0>, - <&isp_clock CLK_ISP_DIV_ISP1>, - <&isp_clock CLK_ISP_DIV_MCUISP0>, - <&isp_clock CLK_ISP_DIV_MCUISP1>, - <&clock CLK_MOUT_MPLL_USER_T>, - <&clock CLK_ACLK200>, - <&clock CLK_ACLK400_MCUISP>, - <&clock CLK_DIV_ACLK200>, - <&clock CLK_DIV_ACLK400_MCUISP>, - <&clock CLK_UART_ISP_SCLK>; - clock-names = "lite0", "lite1", "ppmuispx", - "ppmuispmx", "isp", - "drc", "fd", "mcuisp", - "gicisp", "mcuctl_isp", "pwm_isp", - "ispdiv0", "ispdiv1", "mcuispdiv0", - "mcuispdiv1", "mpll", "aclk200", - "aclk400mcuisp", "div_aclk200", - "div_aclk400mcuisp", "uart"; - iommus = <&sysmmu_fimc_isp>, <&sysmmu_fimc_drc>, - <&sysmmu_fimc_fd>, <&sysmmu_fimc_mcuctl>; - iommu-names = "isp", "drc", "fd", "mcuctl"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - status = "disabled"; - - pmu@10020000 { - reg = <0x10020000 0x3000>; - }; - - i2c1_isp: i2c-isp@12140000 { - compatible = "samsung,exynos4212-i2c-isp"; - reg = <0x12140000 0x100>; - clocks = <&isp_clock CLK_ISP_I2C1_ISP>; - clock-names = "i2c_isp"; - #address-cells = <1>; - #size-cells = <0>; - }; - }; -}; - -&exynos_usbphy { - compatible = "samsung,exynos4x12-usb2-phy"; - samsung,sysreg-phandle = <&sys_reg>; -}; - -&fimc_0 { - compatible = "samsung,exynos4212-fimc"; - samsung,pix-limits = <4224 8192 1920 4224>; - samsung,mainscaler-ext; - samsung,isp-wb; - samsung,cam-if; -}; - -&fimc_1 { - compatible = "samsung,exynos4212-fimc"; - samsung,pix-limits = <4224 8192 1920 4224>; - samsung,mainscaler-ext; - samsung,isp-wb; - samsung,cam-if; -}; - -&fimc_2 { - compatible = "samsung,exynos4212-fimc"; - samsung,pix-limits = <4224 8192 1920 4224>; - samsung,mainscaler-ext; - samsung,isp-wb; - samsung,lcd-wb; - samsung,cam-if; -}; - -&fimc_3 { - compatible = "samsung,exynos4212-fimc"; - samsung,pix-limits = <1920 8192 1366 1920>; - samsung,rotators = <0>; - samsung,mainscaler-ext; - samsung,isp-wb; - samsung,lcd-wb; -}; - -&gic { - cpu-offset = <0x4000>; -}; - -&gpu { - interrupts = , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "gp", - "gpmmu", - "pp0", - "ppmmu0", - "pp1", - "ppmmu1", - "pp2", - "ppmmu2", - "pp3", - "ppmmu3", - "pmu"; - operating-points-v2 = <&gpu_opp_table>; - - gpu_opp_table: opp_table { - compatible = "operating-points-v2"; - - opp-160000000 { - opp-hz = /bits/ 64 <160000000>; - opp-microvolt = <875000>; - }; - opp-267000000 { - opp-hz = /bits/ 64 <267000000>; - opp-microvolt = <900000>; - }; - opp-350000000 { - opp-hz = /bits/ 64 <350000000>; - opp-microvolt = <950000>; - }; - opp-440000000 { - opp-hz = /bits/ 64 <440000000>; - opp-microvolt = <1025000>; - }; - }; -}; - -&hdmi { - compatible = "samsung,exynos4212-hdmi"; -}; - -&jpeg_codec { - compatible = "samsung,exynos4212-jpeg"; -}; - -&rotator { - compatible = "samsung,exynos4212-rotator"; -}; - -&mixer { - compatible = "samsung,exynos4212-mixer"; - clock-names = "mixer", "hdmi", "sclk_hdmi", "vp"; - clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>, - <&clock CLK_SCLK_HDMI>, <&clock CLK_VP>; -}; - -&pmu { - interrupts = <2 2>, <3 2>, <18 2>, <19 2>; - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; - status = "okay"; -}; - -&pmu_system_controller { - compatible = "samsung,exynos4412-pmu", "syscon"; - clock-names = "clkout0", "clkout1", "clkout2", "clkout3", - "clkout4", "clkout8", "clkout9"; - clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>, - <&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>, - <&clock CLK_OUT_CPU>, <&clock CLK_XXTI>, <&clock CLK_XUSBXTI>; - #clock-cells = <1>; -}; - -&tmu { - compatible = "samsung,exynos4412-tmu"; - interrupt-parent = <&combiner>; - interrupts = <2 4>; - reg = <0x100C0000 0x100>; - clocks = <&clock 383>; - clock-names = "tmu_apbif"; - status = "disabled"; -}; - -#include "exynos4412-pinctrl.dtsi" diff --git a/sys/gnu/dts/arm/exynos4415-pinctrl.dtsi b/sys/gnu/dts/arm/exynos4415-pinctrl.dtsi deleted file mode 100644 index 75af9c56123..00000000000 --- a/sys/gnu/dts/arm/exynos4415-pinctrl.dtsi +++ /dev/null @@ -1,573 +0,0 @@ -/* - * Samsung's Exynos4415 SoCs pin-mux and pin-config device tree source - * - * Copyright (c) 2014 Samsung Electronics Co., Ltd. - * - * Samsung's Exynos4415 SoCs pin-mux and pin-config optiosn are listed as device - * tree nodes are listed in this file. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -&pinctrl_0 { - gpa0: gpa0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpa1: gpa1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpb: gpb { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc0: gpc0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc1: gpc1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpd0: gpd0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpd1: gpd1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf0: gpf0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf1: gpf1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf2: gpf2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - uart0_data: uart0-data { - samsung,pins = "gpa0-0", "gpa0-1"; - samsung,pin-function = <0x2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - uart0_fctl: uart0-fctl { - samsung,pins = "gpa0-2", "gpa0-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - uart1_data: uart1-data { - samsung,pins = "gpa0-4", "gpa0-5"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - uart1_fctl: uart1-fctl { - samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - uart2_data: uart2-data { - samsung,pins = "gpa1-0", "gpa1-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - uart2_fctl: uart2-fctl { - samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - uart3_data: uart3-data { - samsung,pins = "gpa1-4", "gpa1-5"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - i2c2_bus: i2c2-bus { - samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; - }; - - i2c3_bus: i2c3-bus { - samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; - }; - - spi0_bus: spi0-bus { - samsung,pins = "gpb-0", "gpb-2", "gpb-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; - }; - - i2c4_bus: i2c4-bus { - samsung,pins = "gpb-0", "gpb-1"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; - }; - - spi1_bus: spi1-bus { - samsung,pins = "gpb-4", "gpb-6", "gpb-7"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; - }; - - i2c5_bus: i2c5-bus { - samsung,pins = "gpb-2", "gpb-3"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; - }; - - i2s1_bus: i2s1-bus { - samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", - "gpc0-4"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - i2s2_bus: i2s2-bus { - samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", - "gpc1-4"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - pcm2_bus: pcm2-bus { - samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", - "gpc1-4"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - i2c6_bus: i2c6-bus { - samsung,pins = "gpc1-3", "gpc1-4"; - samsung,pin-function = <4>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; - }; - - spi2_bus: spi2-bus { - samsung,pins = "gpc1-1", "gpc1-3", "gpc1-4"; - samsung,pin-function = <5>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; - }; - - pwm0_out: pwm0-out { - samsung,pins = "gpd0-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - pwm1_out: pwm1-out { - samsung,pins = "gpd0-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - pwm2_out: pwm2-out { - samsung,pins = "gpd0-2"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - pwm3_out: pwm3-out { - samsung,pins = "gpd0-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - i2c7_bus: i2c7-bus { - samsung,pins = "gpd0-2", "gpd0-3"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; - }; - - i2c0_bus: i2c0-bus { - samsung,pins = "gpd1-0", "gpd1-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; - }; - - i2c1_bus: i2c1-bus { - samsung,pins = "gpd1-2", "gpd1-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; - }; -}; - -&pinctrl_1 { - gpk0: gpk0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpk1: gpk1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpk2: gpk2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpk3: gpk3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpl0: gpl0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpm0: gpm0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpm1: gpm1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpm2: gpm2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpm3: gpm3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpm4: gpm4 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpx0: gpx0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - interrupt-parent = <&gic>; - interrupts = <0 32 0>, <0 33 0>, <0 34 0>, <0 35 0>, - <0 36 0>, <0 37 0>, <0 38 0>, <0 39 0>; - #interrupt-cells = <2>; - }; - - gpx1: gpx1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - interrupt-parent = <&gic>; - interrupts = <0 40 0>, <0 41 0>, <0 42 0>, <0 43 0>, - <0 44 0>, <0 45 0>, <0 46 0>, <0 47 0>; - #interrupt-cells = <2>; - }; - - gpx2: gpx2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpx3: gpx3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - sd0_clk: sd0-clk { - samsung,pins = "gpk0-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; - }; - - sd0_cmd: sd0-cmd { - samsung,pins = "gpk0-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; - }; - - sd0_cd: sd0-cd { - samsung,pins = "gpk0-2"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; - }; - - sd0_rdqs: sd0-rdqs { - samsung,pins = "gpk0-7"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; - }; - - sd0_bus1: sd0-bus-width1 { - samsung,pins = "gpk0-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; - }; - - sd0_bus4: sd0-bus-width4 { - samsung,pins = "gpk0-4", "gpk0-5", "gpk0-6"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; - }; - - sd0_bus8: sd0-bus-width8 { - samsung,pins = "gpl0-0", "gpl0-1", "gpl0-2", "gpl0-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; - }; - - sd1_clk: sd1-clk { - samsung,pins = "gpk1-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; - }; - - sd1_cmd: sd1-cmd { - samsung,pins = "gpk1-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; - }; - - sd1_cd: sd1-cd { - samsung,pins = "gpk1-2"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; - }; - - sd1_bus1: sd1-bus-width1 { - samsung,pins = "gpk1-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; - }; - - sd1_bus4: sd1-bus-width4 { - samsung,pins = "gpk1-4", "gpk1-5", "gpk1-6"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; - }; - - sd2_clk: sd2-clk { - samsung,pins = "gpk2-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <4>; - }; - - sd2_cmd: sd2-cmd { - samsung,pins = "gpk2-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <4>; - }; - - sd2_cd: sd2-cd { - samsung,pins = "gpk2-2"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; - }; - - sd2_bus1: sd2-bus-width1 { - samsung,pins = "gpk2-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <4>; - }; - - sd2_bus4: sd2-bus-width4 { - samsung,pins = "gpk2-4", "gpk2-5", "gpk2-6"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <4>; - }; - - cam_port_b_io: cam-port-b-io { - samsung,pins = "gpm0-0", "gpm0-1", "gpm0-2", "gpm0-3", - "gpm0-4", "gpm0-5", "gpm0-6", "gpm0-7", - "gpm1-0", "gpm1-1", "gpm2-0", "gpm2-1"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; - }; - - cam_port_b_clk_active: cam-port-b-clk-active { - samsung,pins = "gpm2-2"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; - }; - - cam_port_b_clk_idle: cam-port-b-clk-idle { - samsung,pins = "gpm2-2"; - samsung,pin-function = <0>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - fimc_is_i2c0: fimc-is-i2c0 { - samsung,pins = "gpm4-0", "gpm4-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - fimc_is_i2c1: fimc-is-i2c1 { - samsung,pins = "gpm4-2", "gpm4-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - fimc_is_uart: fimc-is-uart { - samsung,pins = "gpm3-5", "gpm3-7"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; -}; - -&pinctrl_2 { - gpz: gpz { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - i2s0_bus: i2s0-bus { - samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", - "gpz-4", "gpz-5", "gpz-6"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; -}; diff --git a/sys/gnu/dts/arm/exynos4415.dtsi b/sys/gnu/dts/arm/exynos4415.dtsi deleted file mode 100644 index 28b04b6795c..00000000000 --- a/sys/gnu/dts/arm/exynos4415.dtsi +++ /dev/null @@ -1,649 +0,0 @@ -/* - * Samsung's Exynos4415 SoC device tree source - * - * Copyright (c) 2014 Samsung Electronics Co., Ltd. - * - * Samsung's Exynos4415 SoC device nodes are listed in this file. Exynos4415 - * based board files can include this file and provide values for board - * specific bindings. - * - * Note: This file does not include device nodes for all the controllers in - * Exynos4415 SoC. As device tree coverage for Exynos4415 increases, additional - * nodes can be added to this file. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include "skeleton.dtsi" -#include -#include - -/ { - compatible = "samsung,exynos4415"; - interrupt-parent = <&gic>; - - aliases { - pinctrl0 = &pinctrl_0; - pinctrl1 = &pinctrl_1; - pinctrl2 = &pinctrl_2; - mshc0 = &mshc_0; - mshc1 = &mshc_1; - mshc2 = &mshc_2; - spi0 = &spi_0; - spi1 = &spi_1; - spi2 = &spi_2; - i2c0 = &i2c_0; - i2c1 = &i2c_1; - i2c2 = &i2c_2; - i2c3 = &i2c_3; - i2c4 = &i2c_4; - i2c5 = &i2c_5; - i2c6 = &i2c_6; - i2c7 = &i2c_7; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@a00 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0xa00>; - clock-frequency = <1600000000>; - }; - - cpu1: cpu@a01 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0xa01>; - clock-frequency = <1600000000>; - }; - - cpu2: cpu@a02 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0xa02>; - clock-frequency = <1600000000>; - }; - - cpu3: cpu@a03 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0xa03>; - clock-frequency = <1600000000>; - }; - }; - - soc: soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - sysram@02020000 { - compatible = "mmio-sram"; - reg = <0x02020000 0x50000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x02020000 0x50000>; - - smp-sysram@0 { - compatible = "samsung,exynos4210-sysram"; - reg = <0x0 0x1000>; - }; - - smp-sysram@4f000 { - compatible = "samsung,exynos4210-sysram-ns"; - reg = <0x4f000 0x1000>; - }; - }; - - pinctrl_2: pinctrl@03860000 { - compatible = "samsung,exynos4415-pinctrl"; - reg = <0x03860000 0x1000>; - interrupts = <0 242 0>; - }; - - chipid@10000000 { - compatible = "samsung,exynos4210-chipid"; - reg = <0x10000000 0x100>; - }; - - sysreg_system_controller: syscon@10010000 { - compatible = "samsung,exynos4-sysreg", "syscon"; - reg = <0x10010000 0x400>; - }; - - pmu_system_controller: system-controller@10020000 { - compatible = "samsung,exynos4415-pmu", "syscon"; - reg = <0x10020000 0x4000>; - }; - - mipi_phy: video-phy@10020710 { - compatible = "samsung,s5pv210-mipi-video-phy"; - #phy-cells = <1>; - syscon = <&pmu_system_controller>; - }; - - pd_cam: cam-power-domain@10024000 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10024000 0x20>; - #power-domain-cells = <0>; - }; - - pd_tv: tv-power-domain@10024020 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10024020 0x20>; - #power-domain-cells = <0>; - }; - - pd_mfc: mfc-power-domain@10024040 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10024040 0x20>; - #power-domain-cells = <0>; - }; - - pd_g3d: g3d-power-domain@10024060 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10024060 0x20>; - #power-domain-cells = <0>; - }; - - pd_lcd0: lcd0-power-domain@10024080 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10024080 0x20>; - #power-domain-cells = <0>; - }; - - pd_isp0: isp0-power-domain@100240A0 { - compatible = "samsung,exynos4210-pd"; - reg = <0x100240A0 0x20>; - #power-domain-cells = <0>; - }; - - pd_isp1: isp1-power-domain@100240E0 { - compatible = "samsung,exynos4210-pd"; - reg = <0x100240E0 0x20>; - #power-domain-cells = <0>; - }; - - cmu: clock-controller@10030000 { - compatible = "samsung,exynos4415-cmu"; - reg = <0x10030000 0x18000>; - #clock-cells = <1>; - }; - - rtc: rtc@10070000 { - compatible = "samsung,s3c6410-rtc"; - reg = <0x10070000 0x100>; - interrupts = <0 73 0>, <0 74 0>; - status = "disabled"; - }; - - mct@10050000 { - compatible = "samsung,exynos4210-mct"; - reg = <0x10050000 0x800>; - interrupts = <0 218 0>, <0 219 0>, <0 220 0>, <0 221 0>, - <0 223 0>, <0 226 0>, <0 227 0>, <0 228 0>; - clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>; - clock-names = "fin_pll", "mct"; - }; - - gic: interrupt-controller@10481000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x10481000 0x1000>, - <0x10482000 0x1000>, - <0x10484000 0x2000>, - <0x10486000 0x2000>; - interrupts = <1 9 0xf04>; - }; - - l2c: l2-cache-controller@10502000 { - compatible = "arm,pl310-cache"; - reg = <0x10502000 0x1000>; - cache-unified; - cache-level = <2>; - arm,tag-latency = <2 2 1>; - arm,data-latency = <3 2 1>; - arm,double-linefill = <1>; - arm,double-linefill-incr = <0>; - arm,double-linefill-wrap = <1>; - arm,prefetch-drop = <1>; - arm,prefetch-offset = <7>; - }; - - cmu_dmc: clock-controller@105C0000 { - compatible = "samsung,exynos4415-cmu-dmc"; - reg = <0x105C0000 0x3000>; - #clock-cells = <1>; - }; - - pinctrl_1: pinctrl@11000000 { - compatible = "samsung,exynos4415-pinctrl"; - reg = <0x11000000 0x1000>; - interrupts = <0 225 0>; - - wakeup-interrupt-controller { - compatible = "samsung,exynos4210-wakeup-eint"; - interrupt-parent = <&gic>; - interrupts = <0 48 0>; - }; - }; - - pinctrl_0: pinctrl@11400000 { - compatible = "samsung,exynos4415-pinctrl"; - reg = <0x11400000 0x1000>; - interrupts = <0 240 0>; - }; - - fimd: fimd@11C00000 { - compatible = "samsung,exynos4415-fimd"; - reg = <0x11C00000 0x30000>; - interrupt-names = "fifo", "vsync", "lcd_sys"; - interrupts = <0 84 0>, <0 85 0>, <0 86 0>; - clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>; - clock-names = "sclk_fimd", "fimd"; - samsung,power-domain = <&pd_lcd0>; - iommus = <&sysmmu_fimd0>; - samsung,sysreg = <&sysreg_system_controller>; - status = "disabled"; - }; - - dsi_0: dsi@11C80000 { - compatible = "samsung,exynos4415-mipi-dsi"; - reg = <0x11C80000 0x10000>; - interrupts = <0 83 0>; - samsung,phy-type = <0>; - samsung,power-domain = <&pd_lcd0>; - phys = <&mipi_phy 1>; - phy-names = "dsim"; - clocks = <&cmu CLK_DSIM0>, <&cmu CLK_SCLK_MIPI0>; - clock-names = "bus_clk", "pll_clk"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - sysmmu_fimd0: sysmmu@11E20000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x11e20000 0x1000>; - interrupts = <0 80 0>, <0 81 0>; - clock-names = "sysmmu", "master"; - clocks = <&cmu CLK_SMMUFIMD0>, <&cmu CLK_FIMD0>; - power-domains = <&pd_lcd0>; - #iommu-cells = <0>; - }; - - hsotg: hsotg@12480000 { - compatible = "samsung,s3c6400-hsotg"; - reg = <0x12480000 0x20000>; - interrupts = <0 141 0>; - clocks = <&cmu CLK_USBDEVICE>; - clock-names = "otg"; - phys = <&exynos_usbphy 0>; - phy-names = "usb2-phy"; - status = "disabled"; - }; - - mshc_0: mshc@12510000 { - compatible = "samsung,exynos5250-dw-mshc"; - reg = <0x12510000 0x1000>; - interrupts = <0 142 0>; - clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>; - clock-names = "biu", "ciu"; - fifo-depth = <0x80>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - mshc_1: mshc@12520000 { - compatible = "samsung,exynos5250-dw-mshc"; - reg = <0x12520000 0x1000>; - interrupts = <0 143 0>; - clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>; - clock-names = "biu", "ciu"; - fifo-depth = <0x80>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - mshc_2: mshc@12530000 { - compatible = "samsung,exynos5250-dw-mshc"; - reg = <0x12530000 0x1000>; - interrupts = <0 144 0>; - clocks = <&cmu CLK_SDMMC2>, <&cmu CLK_SCLK_MMC2>; - clock-names = "biu", "ciu"; - fifo-depth = <0x80>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - ehci: ehci@12580000 { - compatible = "samsung,exynos4210-ehci"; - reg = <0x12580000 0x100>; - interrupts = <0 140 0>; - clocks = <&cmu CLK_USBHOST>; - clock-names = "usbhost"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - phys = <&exynos_usbphy 1>; - status = "disabled"; - }; - port@1 { - reg = <1>; - phys = <&exynos_usbphy 2>; - status = "disabled"; - }; - port@2 { - reg = <2>; - phys = <&exynos_usbphy 3>; - status = "disabled"; - }; - }; - - ohci: ohci@12590000 { - compatible = "samsung,exynos4210-ohci"; - reg = <0x12590000 0x100>; - interrupts = <0 140 0>; - clocks = <&cmu CLK_USBHOST>; - clock-names = "usbhost"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - phys = <&exynos_usbphy 1>; - status = "disabled"; - }; - }; - - exynos_usbphy: exynos-usbphy@125B0000 { - compatible = "samsung,exynos4x12-usb2-phy"; - reg = <0x125B0000 0x100>; - samsung,pmureg-phandle = <&pmu_system_controller>; - samsung,sysreg-phandle = <&sysreg_system_controller>; - clocks = <&cmu CLK_USBDEVICE>, <&xusbxti>; - clock-names = "phy", "ref"; - #phy-cells = <1>; - status = "disabled"; - }; - - amba { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&gic>; - ranges; - - pdma0: pdma@12680000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x12680000 0x1000>; - interrupts = <0 138 0>; - clocks = <&cmu CLK_PDMA0>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; - }; - - pdma1: pdma@12690000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x12690000 0x1000>; - interrupts = <0 139 0>; - clocks = <&cmu CLK_PDMA1>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; - }; - }; - - adc: adc@126C0000 { - compatible = "samsung,exynos3250-adc", - "samsung,exynos-adc-v2"; - reg = <0x126C0000 0x100>, <0x10020718 0x4>; - interrupts = <0 137 0>; - clock-names = "adc", "sclk"; - clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>; - #io-channel-cells = <1>; - io-channel-ranges; - status = "disabled"; - }; - - serial_0: serial@13800000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x13800000 0x100>; - interrupts = <0 109 0>; - clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>; - clock-names = "uart", "clk_uart_baud0"; - status = "disabled"; - }; - - serial_1: serial@13810000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x13810000 0x100>; - interrupts = <0 110 0>; - clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>; - clock-names = "uart", "clk_uart_baud0"; - status = "disabled"; - }; - - serial_2: serial@13820000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x13820000 0x100>; - interrupts = <0 111 0>; - clocks = <&cmu CLK_UART2>, <&cmu CLK_SCLK_UART2>; - clock-names = "uart", "clk_uart_baud0"; - status = "disabled"; - }; - - serial_3: serial@13830000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x13830000 0x100>; - interrupts = <0 112 0>; - clocks = <&cmu CLK_UART3>, <&cmu CLK_SCLK_UART3>; - clock-names = "uart", "clk_uart_baud0"; - status = "disabled"; - }; - - i2c_0: i2c@13860000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x13860000 0x100>; - interrupts = <0 113 0>; - clocks = <&cmu CLK_I2C0>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_bus>; - status = "disabled"; - }; - - i2c_1: i2c@13870000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x13870000 0x100>; - interrupts = <0 114 0>; - clocks = <&cmu CLK_I2C1>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_bus>; - status = "disabled"; - }; - - i2c_2: i2c@13880000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x13880000 0x100>; - interrupts = <0 115 0>; - clocks = <&cmu CLK_I2C2>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_bus>; - status = "disabled"; - }; - - i2c_3: i2c@13890000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x13890000 0x100>; - interrupts = <0 116 0>; - clocks = <&cmu CLK_I2C3>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_bus>; - status = "disabled"; - }; - - i2c_4: i2c@138A0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x138A0000 0x100>; - interrupts = <0 117 0>; - clocks = <&cmu CLK_I2C4>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_bus>; - status = "disabled"; - }; - - i2c_5: i2c@138B0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x138B0000 0x100>; - interrupts = <0 118 0>; - clocks = <&cmu CLK_I2C5>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c5_bus>; - status = "disabled"; - }; - - i2c_6: i2c@138C0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x138C0000 0x100>; - interrupts = <0 119 0>; - clocks = <&cmu CLK_I2C6>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c6_bus>; - status = "disabled"; - }; - - i2c_7: i2c@138D0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x138D0000 0x100>; - interrupts = <0 120 0>; - clocks = <&cmu CLK_I2C7>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c7_bus>; - status = "disabled"; - }; - - spi_0: spi@13920000 { - compatible = "samsung,exynos4210-spi"; - reg = <0x13920000 0x100>; - interrupts = <0 121 0>; - dmas = <&pdma0 7>, <&pdma0 6>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>; - clock-names = "spi", "spi_busclk0"; - samsung,spi-src-clk = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_bus>; - status = "disabled"; - }; - - spi_1: spi@13930000 { - compatible = "samsung,exynos4210-spi"; - reg = <0x13930000 0x100>; - interrupts = <0 122 0>; - dmas = <&pdma1 7>, <&pdma1 6>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>; - clock-names = "spi", "spi_busclk0"; - samsung,spi-src-clk = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&spi1_bus>; - status = "disabled"; - }; - - spi_2: spi@13940000 { - compatible = "samsung,exynos4210-spi"; - reg = <0x13940000 0x100>; - interrupts = <0 123 0>; - dmas = <&pdma0 9>, <&pdma0 8>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cmu CLK_SPI2>, <&cmu CLK_SCLK_SPI2>; - clock-names = "spi", "spi_busclk0"; - samsung,spi-src-clk = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&spi2_bus>; - status = "disabled"; - }; - - clock_audss: clock-controller@03810000 { - compatible = "samsung,exynos4210-audss-clock"; - reg = <0x03810000 0x0C>; - #clock-cells = <1>; - }; - - i2s0: i2s@3830000 { - compatible = "samsung,s5pv210-i2s"; - reg = <0x03830000 0x100>; - interrupts = <0 124 0>; - clocks = <&clock_audss EXYNOS_I2S_BUS>, - <&clock_audss EXYNOS_SCLK_I2S>; - clock-names = "iis", "i2s_opclk0"; - dmas = <&pdma1 10>, <&pdma1 9>, <&pdma1 8>; - dma-names = "tx", "rx", "tx-sec"; - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_bus>; - samsung,idma-addr = <0x03000000>; - status = "disabled"; - }; - - pwm: pwm@139D0000 { - compatible = "samsung,exynos4210-pwm"; - reg = <0x139D0000 0x1000>; - interrupts = <0 104 0>, <0 105 0>, <0 106 0>, - <0 107 0>, <0 108 0>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts = <0 18 0>, <0 19 0>, <0 20 0>, <0 21 0>; - }; - }; -}; - -#include "exynos4415-pinctrl.dtsi" diff --git a/sys/gnu/dts/arm/exynos4x12-pinctrl.dtsi b/sys/gnu/dts/arm/exynos4x12-pinctrl.dtsi deleted file mode 100644 index 2f866f6e583..00000000000 --- a/sys/gnu/dts/arm/exynos4x12-pinctrl.dtsi +++ /dev/null @@ -1,984 +0,0 @@ -/* - * Samsung's Exynos4x12 SoCs pin-mux and pin-config device tree source - * - * Copyright (c) 2012 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Samsung's Exynos4x12 SoCs pin-mux and pin-config optiosn are listed as device - * tree nodes are listed in this file. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include - -#define PIN_SLP(_pin, _mode, _pull) \ - _pin { \ - samsung,pins = #_pin; \ - samsung,pin-con-pdn = ; \ - samsung,pin-pud-pdn = ; \ - } - -/ { - pinctrl_0: pinctrl@11400000 { - gpa0: gpa0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpa1: gpa1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpb: gpb { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc0: gpc0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc1: gpc1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpd0: gpd0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpd1: gpd1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf0: gpf0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf1: gpf1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf2: gpf2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf3: gpf3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpj0: gpj0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpj1: gpj1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - uart0_data: uart0-data { - samsung,pins = "gpa0-0", "gpa0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart0_fctl: uart0-fctl { - samsung,pins = "gpa0-2", "gpa0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart1_data: uart1-data { - samsung,pins = "gpa0-4", "gpa0-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart1_fctl: uart1-fctl { - samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c2_bus: i2c2-bus { - samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart2_data: uart2-data { - samsung,pins = "gpa1-0", "gpa1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart2_fctl: uart2-fctl { - samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart_audio_a: uart-audio-a { - samsung,pins = "gpa1-0", "gpa1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c3_bus: i2c3-bus { - samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart3_data: uart3-data { - samsung,pins = "gpa1-4", "gpa1-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart_audio_b: uart-audio-b { - samsung,pins = "gpa1-4", "gpa1-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spi0_bus: spi0-bus { - samsung,pins = "gpb-0", "gpb-2", "gpb-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c4_bus: i2c4-bus { - samsung,pins = "gpb-0", "gpb-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spi1_bus: spi1-bus { - samsung,pins = "gpb-4", "gpb-6", "gpb-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c5_bus: i2c5-bus { - samsung,pins = "gpb-2", "gpb-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2s1_bus: i2s1-bus { - samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", - "gpc0-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pcm1_bus: pcm1-bus { - samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", - "gpc0-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - ac97_bus: ac97-bus { - samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", - "gpc0-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2s2_bus: i2s2-bus { - samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", - "gpc1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pcm2_bus: pcm2-bus { - samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", - "gpc1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spdif_bus: spdif-bus { - samsung,pins = "gpc1-0", "gpc1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c6_bus: i2c6-bus { - samsung,pins = "gpc1-3", "gpc1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spi2_bus: spi2-bus { - samsung,pins = "gpc1-1", "gpc1-3", "gpc1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm0_out: pwm0-out { - samsung,pins = "gpd0-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm1_out: pwm1-out { - samsung,pins = "gpd0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - lcd_ctrl: lcd-ctrl { - samsung,pins = "gpd0-0", "gpd0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c7_bus: i2c7-bus { - samsung,pins = "gpd0-2", "gpd0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm2_out: pwm2-out { - samsung,pins = "gpd0-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm3_out: pwm3-out { - samsung,pins = "gpd0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c0_bus: i2c0-bus { - samsung,pins = "gpd1-0", "gpd1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - mipi0_clk: mipi0-clk { - samsung,pins = "gpd1-0", "gpd1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c1_bus: i2c1-bus { - samsung,pins = "gpd1-2", "gpd1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - mipi1_clk: mipi1-clk { - samsung,pins = "gpd1-2", "gpd1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - lcd_clk: lcd-clk { - samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - lcd_data16: lcd-data-width16 { - samsung,pins = "gpf0-7", "gpf1-0", "gpf1-1", "gpf1-2", - "gpf1-3", "gpf1-6", "gpf1-7", "gpf2-0", - "gpf2-1", "gpf2-2", "gpf2-3", "gpf2-7", - "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - lcd_data18: lcd-data-width18 { - samsung,pins = "gpf0-6", "gpf0-7", "gpf1-0", "gpf1-1", - "gpf1-2", "gpf1-3", "gpf1-6", "gpf1-7", - "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3", - "gpf2-6", "gpf2-7", "gpf3-0", "gpf3-1", - "gpf3-2", "gpf3-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - lcd_data24: lcd-data-width24 { - samsung,pins = "gpf0-4", "gpf0-5", "gpf0-6", "gpf0-7", - "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3", - "gpf1-4", "gpf1-5", "gpf1-6", "gpf1-7", - "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3", - "gpf2-4", "gpf2-5", "gpf2-6", "gpf2-7", - "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - lcd_ldi: lcd-ldi { - samsung,pins = "gpf3-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_port_a_io: cam-port-a-io { - samsung,pins = "gpj0-0", "gpj0-1", "gpj0-2", "gpj0-3", - "gpj0-4", "gpj0-5", "gpj0-6", "gpj0-7", - "gpj1-0", "gpj1-1", "gpj1-2", "gpj1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_port_a_clk_active: cam-port-a-clk-active { - samsung,pins = "gpj1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_port_a_clk_idle: cam-port-a-clk-idle { - samsung,pins = "gpj1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - }; - - pinctrl_1: pinctrl@11000000 { - gpk0: gpk0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpk1: gpk1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpk2: gpk2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpk3: gpk3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpl0: gpl0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpl1: gpl1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpl2: gpl2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpm0: gpm0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpm1: gpm1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpm2: gpm2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpm3: gpm3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpm4: gpm4 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpy0: gpy0 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy1: gpy1 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy2: gpy2 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy3: gpy3 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy4: gpy4 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy5: gpy5 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy6: gpy6 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpx0: gpx0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - interrupt-parent = <&gic>; - interrupts = , - , - , - , - , - , - , - ; - #interrupt-cells = <2>; - }; - - gpx1: gpx1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - interrupt-parent = <&gic>; - interrupts = , - , - , - , - , - , - , - ; - #interrupt-cells = <2>; - }; - - gpx2: gpx2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpx3: gpx3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - sd0_clk: sd0-clk { - samsung,pins = "gpk0-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_cmd: sd0-cmd { - samsung,pins = "gpk0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_cd: sd0-cd { - samsung,pins = "gpk0-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus1: sd0-bus-width1 { - samsung,pins = "gpk0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus4: sd0-bus-width4 { - samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus8: sd0-bus-width8 { - samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd4_clk: sd4-clk { - samsung,pins = "gpk0-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd4_cmd: sd4-cmd { - samsung,pins = "gpk0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd4_cd: sd4-cd { - samsung,pins = "gpk0-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd4_bus1: sd4-bus-width1 { - samsung,pins = "gpk0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd4_bus4: sd4-bus-width4 { - samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd4_bus8: sd4-bus-width8 { - samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_clk: sd1-clk { - samsung,pins = "gpk1-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_cmd: sd1-cmd { - samsung,pins = "gpk1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_cd: sd1-cd { - samsung,pins = "gpk1-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_bus1: sd1-bus-width1 { - samsung,pins = "gpk1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_bus4: sd1-bus-width4 { - samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_clk: sd2-clk { - samsung,pins = "gpk2-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_cmd: sd2-cmd { - samsung,pins = "gpk2-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_cd: sd2-cd { - samsung,pins = "gpk2-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_bus1: sd2-bus-width1 { - samsung,pins = "gpk2-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_bus4: sd2-bus-width4 { - samsung,pins = "gpk2-3", "gpk2-4", "gpk2-5", "gpk2-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_bus8: sd2-bus-width8 { - samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd3_clk: sd3-clk { - samsung,pins = "gpk3-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd3_cmd: sd3-cmd { - samsung,pins = "gpk3-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd3_cd: sd3-cd { - samsung,pins = "gpk3-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd3_bus1: sd3-bus-width1 { - samsung,pins = "gpk3-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd3_bus4: sd3-bus-width4 { - samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_port_b_io: cam-port-b-io { - samsung,pins = "gpm0-0", "gpm0-1", "gpm0-2", "gpm0-3", - "gpm0-4", "gpm0-5", "gpm0-6", "gpm0-7", - "gpm1-0", "gpm1-1", "gpm2-0", "gpm2-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_port_b_clk_active: cam-port-b-clk-active { - samsung,pins = "gpm2-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_port_b_clk_idle: cam-port-b-clk-idle { - samsung,pins = "gpm2-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - eint0: ext-int0 { - samsung,pins = "gpx0-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - eint8: ext-int8 { - samsung,pins = "gpx1-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - eint15: ext-int15 { - samsung,pins = "gpx1-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - eint16: ext-int16 { - samsung,pins = "gpx2-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - eint31: ext-int31 { - samsung,pins = "gpx3-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - fimc_is_i2c0: fimc-is-i2c0 { - samsung,pins = "gpm4-0", "gpm4-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - fimc_is_i2c1: fimc-is-i2c1 { - samsung,pins = "gpm4-2", "gpm4-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - fimc_is_uart: fimc-is-uart { - samsung,pins = "gpm3-5", "gpm3-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - hdmi_cec: hdmi-cec { - samsung,pins = "gpx3-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - }; - - pinctrl_2: pinctrl@03860000 { - gpz: gpz { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - i2s0_bus: i2s0-bus { - samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", - "gpz-4", "gpz-5", "gpz-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pcm0_bus: pcm0-bus { - samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", - "gpz-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - }; - - pinctrl_3: pinctrl@106E0000 { - gpv0: gpv0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpv1: gpv1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpv2: gpv2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpv3: gpv3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpv4: gpv4 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - c2c_bus: c2c-bus { - samsung,pins = "gpv0-0", "gpv0-1", "gpv0-2", "gpv0-3", - "gpv0-4", "gpv0-5", "gpv0-6", "gpv0-7", - "gpv1-0", "gpv1-1", "gpv1-2", "gpv1-3", - "gpv1-4", "gpv1-5", "gpv1-6", "gpv1-7", - "gpv2-0", "gpv2-1", "gpv2-2", "gpv2-3", - "gpv2-4", "gpv2-5", "gpv2-6", "gpv2-7", - "gpv3-0", "gpv3-1", "gpv3-2", "gpv3-3", - "gpv3-4", "gpv3-5", "gpv3-6", "gpv3-7", - "gpv4-0", "gpv4-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - }; -}; diff --git a/sys/gnu/dts/arm/exynos4x12.dtsi b/sys/gnu/dts/arm/exynos4x12.dtsi deleted file mode 100644 index 85a7122658f..00000000000 --- a/sys/gnu/dts/arm/exynos4x12.dtsi +++ /dev/null @@ -1,594 +0,0 @@ -/* - * Samsung's Exynos4x12 SoCs device tree source - * - * Copyright (c) 2012 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Samsung's Exynos4x12 SoCs device nodes are listed in this file. Exynos4x12 - * based board files can include this file and provide values for board specfic - * bindings. - * - * Note: This file does not include device nodes for all the controllers in - * Exynos4x12 SoC. As device tree coverage for Exynos4x12 increases, additional - * nodes can be added to this file. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include "exynos4.dtsi" -#include "exynos4x12-pinctrl.dtsi" -#include "exynos4-cpu-thermal.dtsi" - -/ { - aliases { - pinctrl0 = &pinctrl_0; - pinctrl1 = &pinctrl_1; - pinctrl2 = &pinctrl_2; - pinctrl3 = &pinctrl_3; - fimc-lite0 = &fimc_lite_0; - fimc-lite1 = &fimc_lite_1; - mshc0 = &mshc_0; - }; - - sysram@02020000 { - compatible = "mmio-sram"; - reg = <0x02020000 0x40000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x02020000 0x40000>; - - smp-sysram@0 { - compatible = "samsung,exynos4210-sysram"; - reg = <0x0 0x1000>; - }; - - smp-sysram@2f000 { - compatible = "samsung,exynos4210-sysram-ns"; - reg = <0x2f000 0x1000>; - }; - }; - - pd_isp: isp-power-domain@10023CA0 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10023CA0 0x20>; - #power-domain-cells = <0>; - }; - - l2c: l2-cache-controller@10502000 { - compatible = "arm,pl310-cache"; - reg = <0x10502000 0x1000>; - cache-unified; - cache-level = <2>; - arm,tag-latency = <2 2 1>; - arm,data-latency = <3 2 1>; - arm,double-linefill = <1>; - arm,double-linefill-incr = <0>; - arm,double-linefill-wrap = <1>; - arm,prefetch-drop = <1>; - arm,prefetch-offset = <7>; - }; - - clock: clock-controller@10030000 { - compatible = "samsung,exynos4412-clock"; - reg = <0x10030000 0x20000>; - #clock-cells = <1>; - }; - - mct@10050000 { - compatible = "samsung,exynos4412-mct"; - reg = <0x10050000 0x800>; - interrupt-parent = <&mct_map>; - interrupts = <0>, <1>, <2>, <3>, <4>; - clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; - clock-names = "fin_pll", "mct"; - - mct_map: mct-map { - #interrupt-cells = <1>; - #address-cells = <0>; - #size-cells = <0>; - interrupt-map = <0 &gic 0 57 IRQ_TYPE_LEVEL_HIGH>, - <1 &combiner 12 5>, - <2 &combiner 12 6>, - <3 &combiner 12 7>, - <4 &gic 1 12 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - - adc: adc@126C0000 { - compatible = "samsung,exynos-adc-v1"; - reg = <0x126C0000 0x100>; - interrupt-parent = <&combiner>; - interrupts = <10 3>; - clocks = <&clock CLK_TSADC>; - clock-names = "adc"; - #io-channel-cells = <1>; - io-channel-ranges; - samsung,syscon-phandle = <&pmu_system_controller>; - status = "disabled"; - }; - - g2d: g2d@10800000 { - compatible = "samsung,exynos4212-g2d"; - reg = <0x10800000 0x1000>; - interrupts = ; - clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>; - clock-names = "sclk_fimg2d", "fimg2d"; - iommus = <&sysmmu_g2d>; - }; - - camera { - clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>, - <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>; - clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1"; - - /* fimc_[0-3] are configured outside, under phandles */ - fimc_lite_0: fimc-lite@12390000 { - compatible = "samsung,exynos4212-fimc-lite"; - reg = <0x12390000 0x1000>; - interrupts = ; - power-domains = <&pd_isp>; - clocks = <&clock CLK_FIMC_LITE0>; - clock-names = "flite"; - iommus = <&sysmmu_fimc_lite0>; - status = "disabled"; - }; - - fimc_lite_1: fimc-lite@123A0000 { - compatible = "samsung,exynos4212-fimc-lite"; - reg = <0x123A0000 0x1000>; - interrupts = ; - power-domains = <&pd_isp>; - clocks = <&clock CLK_FIMC_LITE1>; - clock-names = "flite"; - iommus = <&sysmmu_fimc_lite1>; - status = "disabled"; - }; - - fimc_is: fimc-is@12000000 { - compatible = "samsung,exynos4212-fimc-is"; - reg = <0x12000000 0x260000>; - interrupts = , - ; - power-domains = <&pd_isp>; - clocks = <&clock CLK_FIMC_LITE0>, - <&clock CLK_FIMC_LITE1>, <&clock CLK_PPMUISPX>, - <&clock CLK_PPMUISPMX>, - <&clock CLK_MOUT_MPLL_USER_T>, - <&clock CLK_FIMC_ISP>, <&clock CLK_FIMC_DRC>, - <&clock CLK_FIMC_FD>, <&clock CLK_MCUISP>, - <&clock CLK_GICISP>, <&clock CLK_MCUCTL_ISP>, - <&clock CLK_PWM_ISP>, - <&clock CLK_DIV_ISP0>, <&clock CLK_DIV_ISP1>, - <&clock CLK_DIV_MCUISP0>, - <&clock CLK_DIV_MCUISP1>, - <&clock CLK_UART_ISP_SCLK>, - <&clock CLK_ACLK200>, <&clock CLK_DIV_ACLK200>, - <&clock CLK_ACLK400_MCUISP>, - <&clock CLK_DIV_ACLK400_MCUISP>; - clock-names = "lite0", "lite1", "ppmuispx", - "ppmuispmx", "mpll", "isp", - "drc", "fd", "mcuisp", - "gicisp", "mcuctl_isp", "pwm_isp", - "ispdiv0", "ispdiv1", "mcuispdiv0", - "mcuispdiv1", "uart", "aclk200", - "div_aclk200", "aclk400mcuisp", - "div_aclk400mcuisp"; - iommus = <&sysmmu_fimc_isp>, <&sysmmu_fimc_drc>, - <&sysmmu_fimc_fd>, <&sysmmu_fimc_mcuctl>; - iommu-names = "isp", "drc", "fd", "mcuctl"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - status = "disabled"; - - pmu@10020000 { - reg = <0x10020000 0x3000>; - }; - - i2c1_isp: i2c-isp@12140000 { - compatible = "samsung,exynos4212-i2c-isp"; - reg = <0x12140000 0x100>; - clocks = <&clock CLK_I2C1_ISP>; - clock-names = "i2c_isp"; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - }; - - mshc_0: mmc@12550000 { - compatible = "samsung,exynos4412-dw-mshc"; - reg = <0x12550000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - fifo-depth = <0x80>; - clocks = <&clock CLK_SDMMC4>, <&clock CLK_SCLK_MMC4>; - clock-names = "biu", "ciu"; - status = "disabled"; - }; - - sysmmu_g2d: sysmmu@10A40000{ - compatible = "samsung,exynos-sysmmu"; - reg = <0x10A40000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <4 7>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>; - #iommu-cells = <0>; - }; - - sysmmu_fimc_isp: sysmmu@12260000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x12260000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <16 2>; - power-domains = <&pd_isp>; - clock-names = "sysmmu"; - clocks = <&clock CLK_SMMU_ISP>; - #iommu-cells = <0>; - }; - - sysmmu_fimc_drc: sysmmu@12270000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x12270000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <16 3>; - power-domains = <&pd_isp>; - clock-names = "sysmmu"; - clocks = <&clock CLK_SMMU_DRC>; - #iommu-cells = <0>; - }; - - sysmmu_fimc_fd: sysmmu@122A0000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x122A0000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <16 4>; - power-domains = <&pd_isp>; - clock-names = "sysmmu"; - clocks = <&clock CLK_SMMU_FD>; - #iommu-cells = <0>; - }; - - sysmmu_fimc_mcuctl: sysmmu@122B0000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x122B0000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <16 5>; - power-domains = <&pd_isp>; - clock-names = "sysmmu"; - clocks = <&clock CLK_SMMU_ISPCX>; - #iommu-cells = <0>; - }; - - sysmmu_fimc_lite0: sysmmu@123B0000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x123B0000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <16 0>; - power-domains = <&pd_isp>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_LITE0>, <&clock CLK_FIMC_LITE0>; - #iommu-cells = <0>; - }; - - sysmmu_fimc_lite1: sysmmu@123C0000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x123C0000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <16 1>; - power-domains = <&pd_isp>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_LITE1>, <&clock CLK_FIMC_LITE1>; - #iommu-cells = <0>; - }; - - bus_dmc: bus_dmc { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DIV_DMC>; - clock-names = "bus"; - operating-points-v2 = <&bus_dmc_opp_table>; - status = "disabled"; - }; - - bus_acp: bus_acp { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DIV_ACP>; - clock-names = "bus"; - operating-points-v2 = <&bus_acp_opp_table>; - status = "disabled"; - }; - - bus_c2c: bus_c2c { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DIV_C2C>; - clock-names = "bus"; - operating-points-v2 = <&bus_dmc_opp_table>; - status = "disabled"; - }; - - bus_dmc_opp_table: opp_table1 { - compatible = "operating-points-v2"; - opp-shared; - - opp@100000000 { - opp-hz = /bits/ 64 <100000000>; - opp-microvolt = <900000>; - }; - opp@134000000 { - opp-hz = /bits/ 64 <134000000>; - opp-microvolt = <900000>; - }; - opp@160000000 { - opp-hz = /bits/ 64 <160000000>; - opp-microvolt = <900000>; - }; - opp@267000000 { - opp-hz = /bits/ 64 <267000000>; - opp-microvolt = <950000>; - }; - opp@400000000 { - opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <1050000>; - }; - }; - - bus_acp_opp_table: opp_table2 { - compatible = "operating-points-v2"; - opp-shared; - - opp@100000000 { - opp-hz = /bits/ 64 <100000000>; - }; - opp@134000000 { - opp-hz = /bits/ 64 <134000000>; - }; - opp@160000000 { - opp-hz = /bits/ 64 <160000000>; - }; - opp@267000000 { - opp-hz = /bits/ 64 <267000000>; - }; - }; - - bus_leftbus: bus_leftbus { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DIV_GDL>; - clock-names = "bus"; - operating-points-v2 = <&bus_leftbus_opp_table>; - status = "disabled"; - }; - - bus_rightbus: bus_rightbus { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DIV_GDR>; - clock-names = "bus"; - operating-points-v2 = <&bus_leftbus_opp_table>; - status = "disabled"; - }; - - bus_display: bus_display { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_ACLK160>; - clock-names = "bus"; - operating-points-v2 = <&bus_display_opp_table>; - status = "disabled"; - }; - - bus_fsys: bus_fsys { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_ACLK133>; - clock-names = "bus"; - operating-points-v2 = <&bus_fsys_opp_table>; - status = "disabled"; - }; - - bus_peri: bus_peri { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_ACLK100>; - clock-names = "bus"; - operating-points-v2 = <&bus_peri_opp_table>; - status = "disabled"; - }; - - bus_mfc: bus_mfc { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_SCLK_MFC>; - clock-names = "bus"; - operating-points-v2 = <&bus_leftbus_opp_table>; - status = "disabled"; - }; - - bus_leftbus_opp_table: opp_table3 { - compatible = "operating-points-v2"; - opp-shared; - - opp@100000000 { - opp-hz = /bits/ 64 <100000000>; - opp-microvolt = <900000>; - }; - opp@134000000 { - opp-hz = /bits/ 64 <134000000>; - opp-microvolt = <925000>; - }; - opp@160000000 { - opp-hz = /bits/ 64 <160000000>; - opp-microvolt = <950000>; - }; - opp@200000000 { - opp-hz = /bits/ 64 <200000000>; - opp-microvolt = <1000000>; - }; - }; - - bus_display_opp_table: opp_table4 { - compatible = "operating-points-v2"; - opp-shared; - - opp@160000000 { - opp-hz = /bits/ 64 <160000000>; - }; - opp@200000000 { - opp-hz = /bits/ 64 <200000000>; - }; - }; - - bus_fsys_opp_table: opp_table5 { - compatible = "operating-points-v2"; - opp-shared; - - opp@100000000 { - opp-hz = /bits/ 64 <100000000>; - }; - opp@134000000 { - opp-hz = /bits/ 64 <134000000>; - }; - }; - - bus_peri_opp_table: opp_table6 { - compatible = "operating-points-v2"; - opp-shared; - - opp@50000000 { - opp-hz = /bits/ 64 <50000000>; - }; - opp@100000000 { - opp-hz = /bits/ 64 <100000000>; - }; - }; -}; - -&combiner { - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; -}; - -&exynos_usbphy { - compatible = "samsung,exynos4x12-usb2-phy"; - samsung,sysreg-phandle = <&sys_reg>; -}; - -&fimc_0 { - compatible = "samsung,exynos4212-fimc"; - samsung,pix-limits = <4224 8192 1920 4224>; - samsung,mainscaler-ext; - samsung,isp-wb; - samsung,cam-if; -}; - -&fimc_1 { - compatible = "samsung,exynos4212-fimc"; - samsung,pix-limits = <4224 8192 1920 4224>; - samsung,mainscaler-ext; - samsung,isp-wb; - samsung,cam-if; -}; - -&fimc_2 { - compatible = "samsung,exynos4212-fimc"; - samsung,pix-limits = <4224 8192 1920 4224>; - samsung,mainscaler-ext; - samsung,isp-wb; - samsung,lcd-wb; - samsung,cam-if; -}; - -&fimc_3 { - compatible = "samsung,exynos4212-fimc"; - samsung,pix-limits = <1920 8192 1366 1920>; - samsung,rotators = <0>; - samsung,mainscaler-ext; - samsung,isp-wb; - samsung,lcd-wb; -}; - -&hdmi { - compatible = "samsung,exynos4212-hdmi"; -}; - -&jpeg_codec { - compatible = "samsung,exynos4212-jpeg"; -}; - -&rotator { - compatible = "samsung,exynos4212-rotator"; -}; - -&mixer { - compatible = "samsung,exynos4212-mixer"; - clock-names = "mixer", "hdmi", "sclk_hdmi", "vp"; - clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>, - <&clock CLK_SCLK_HDMI>, <&clock CLK_VP>; -}; - -&pinctrl_0 { - compatible = "samsung,exynos4x12-pinctrl"; - reg = <0x11400000 0x1000>; - interrupts = ; -}; - -&pinctrl_1 { - compatible = "samsung,exynos4x12-pinctrl"; - reg = <0x11000000 0x1000>; - interrupts = ; - - wakup_eint: wakeup-interrupt-controller { - compatible = "samsung,exynos4210-wakeup-eint"; - interrupt-parent = <&gic>; - interrupts = ; - }; -}; - -&pinctrl_2 { - compatible = "samsung,exynos4x12-pinctrl"; - reg = <0x03860000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <10 0>; -}; - -&pinctrl_3 { - compatible = "samsung,exynos4x12-pinctrl"; - reg = <0x106E0000 0x1000>; - interrupts = ; -}; - -&pmu_system_controller { - compatible = "samsung,exynos4212-pmu", "syscon"; - clock-names = "clkout0", "clkout1", "clkout2", "clkout3", - "clkout4", "clkout8", "clkout9"; - clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>, - <&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>, - <&clock CLK_OUT_CPU>, <&clock CLK_XXTI>, <&clock CLK_XUSBXTI>; - #clock-cells = <1>; -}; - -&tmu { - compatible = "samsung,exynos4412-tmu"; - interrupt-parent = <&combiner>; - interrupts = <2 4>; - reg = <0x100C0000 0x100>; - clocks = <&clock 383>; - clock-names = "tmu_apbif"; - status = "disabled"; -}; diff --git a/sys/gnu/dts/arm/exynos5.dtsi b/sys/gnu/dts/arm/exynos5.dtsi deleted file mode 100644 index 22eb951c614..00000000000 --- a/sys/gnu/dts/arm/exynos5.dtsi +++ /dev/null @@ -1,230 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's Exynos5 SoC series common device tree source - * - * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Samsung's Exynos5 SoC series device nodes are listed in this file. Particular - * SoCs from Exynos5 series can include this file and provide values for SoCs - * specfic bindings. - */ - -#include -#include - -/ { - interrupt-parent = <&gic>; - #address-cells = <1>; - #size-cells = <1>; - - aliases { - i2c0 = &i2c_0; - i2c1 = &i2c_1; - i2c2 = &i2c_2; - i2c3 = &i2c_3; - serial0 = &serial_0; - serial1 = &serial_1; - serial2 = &serial_2; - serial3 = &serial_3; - }; - - soc: soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - chipid: chipid@10000000 { - compatible = "samsung,exynos4210-chipid"; - reg = <0x10000000 0x100>; - }; - - sromc: memory-controller@12250000 { - compatible = "samsung,exynos4210-srom"; - reg = <0x12250000 0x14>; - }; - - combiner: interrupt-controller@10440000 { - compatible = "samsung,exynos4210-combiner"; - #interrupt-cells = <2>; - interrupt-controller; - samsung,combiner-nr = <32>; - reg = <0x10440000 0x1000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - }; - - gic: interrupt-controller@10481000 { - compatible = "arm,gic-400", "arm,cortex-a15-gic", "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x10481000 0x1000>, - <0x10482000 0x2000>, - <0x10484000 0x2000>, - <0x10486000 0x2000>; - interrupts = ; - }; - - sysreg_system_controller: syscon@10050000 { - compatible = "samsung,exynos5-sysreg", "syscon"; - reg = <0x10050000 0x5000>; - }; - - serial_0: serial@12c00000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x12C00000 0x100>; - interrupts = ; - }; - - serial_1: serial@12c10000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x12C10000 0x100>; - interrupts = ; - }; - - serial_2: serial@12c20000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x12C20000 0x100>; - interrupts = ; - }; - - serial_3: serial@12c30000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x12C30000 0x100>; - interrupts = ; - }; - - i2c_0: i2c@12c60000 { - compatible = "samsung,s3c2440-i2c"; - reg = <0x12C60000 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - samsung,sysreg-phandle = <&sysreg_system_controller>; - status = "disabled"; - }; - - i2c_1: i2c@12c70000 { - compatible = "samsung,s3c2440-i2c"; - reg = <0x12C70000 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - samsung,sysreg-phandle = <&sysreg_system_controller>; - status = "disabled"; - }; - - i2c_2: i2c@12c80000 { - compatible = "samsung,s3c2440-i2c"; - reg = <0x12C80000 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - samsung,sysreg-phandle = <&sysreg_system_controller>; - status = "disabled"; - }; - - i2c_3: i2c@12c90000 { - compatible = "samsung,s3c2440-i2c"; - reg = <0x12C90000 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - samsung,sysreg-phandle = <&sysreg_system_controller>; - status = "disabled"; - }; - - pwm: pwm@12dd0000 { - compatible = "samsung,exynos4210-pwm"; - reg = <0x12DD0000 0x100>; - interrupts = , - , - , - , - ; - samsung,pwm-outputs = <0>, <1>, <2>, <3>; - #pwm-cells = <3>; - }; - - rtc: rtc@101e0000 { - compatible = "samsung,s3c6410-rtc"; - reg = <0x101E0000 0x100>; - interrupts = , - ; - status = "disabled"; - }; - - fimd: fimd@14400000 { - compatible = "samsung,exynos5250-fimd"; - interrupt-parent = <&combiner>; - reg = <0x14400000 0x40000>; - interrupt-names = "fifo", "vsync", "lcd_sys"; - interrupts = <18 4>, <18 5>, <18 6>; - samsung,sysreg = <&sysreg_system_controller>; - status = "disabled"; - }; - - dp: dp-controller@145b0000 { - compatible = "samsung,exynos5-dp"; - reg = <0x145B0000 0x1000>; - interrupts = <10 3>; - interrupt-parent = <&combiner>; - status = "disabled"; - }; - - sss: sss@10830000 { - compatible = "samsung,exynos4210-secss"; - reg = <0x10830000 0x300>; - interrupts = ; - }; - - prng: rng@10830400 { - compatible = "samsung,exynos5250-prng"; - reg = <0x10830400 0x200>; - }; - - trng: rng@10830600 { - compatible = "samsung,exynos5250-trng"; - reg = <0x10830600 0x100>; - }; - - g2d: g2d@10850000 { - compatible = "samsung,exynos5250-g2d"; - reg = <0x10850000 0x1000>; - interrupts = ; - status = "disabled"; - }; - }; -}; diff --git a/sys/gnu/dts/arm/exynos5250-arndale.dts b/sys/gnu/dts/arm/exynos5250-arndale.dts deleted file mode 100644 index f8ebc620f42..00000000000 --- a/sys/gnu/dts/arm/exynos5250-arndale.dts +++ /dev/null @@ -1,647 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's Exynos5250 based Arndale board device tree source - * - * Copyright (c) 2013 Samsung Electronics Co., Ltd. - * http://www.samsung.com - */ - -/dts-v1/; -#include -#include -#include -#include -#include -#include "exynos5250.dtsi" - -/ { - model = "Insignal Arndale evaluation board based on Exynos5250"; - compatible = "insignal,arndale", "samsung,exynos5250", "samsung,exynos5"; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x80000000>; - }; - - chosen { - stdout-path = "serial2:115200n8"; - }; - - gpio_keys { - compatible = "gpio-keys"; - - menu { - label = "SW-TACT2"; - gpios = <&gpx1 4 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - - home { - label = "SW-TACT3"; - gpios = <&gpx1 5 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - - up { - label = "SW-TACT4"; - gpios = <&gpx1 6 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - - down { - label = "SW-TACT5"; - gpios = <&gpx1 7 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - - back { - label = "SW-TACT6"; - gpios = <&gpx2 0 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - - wakeup { - label = "SW-TACT7"; - gpios = <&gpx2 1 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - }; - - panel: panel { - compatible = "boe,hv070wsa-100"; - power-supply = <&vcc_3v3_reg>; - enable-gpios = <&gpd1 3 GPIO_ACTIVE_HIGH>; - port { - panel_ep: endpoint { - remote-endpoint = <&bridge_out_ep>; - }; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - main_dc_reg: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "MAIN_DC"; - }; - - mmc_reg: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "VDD_33ON_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpx1 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_hdmi_en: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "hdmi-en"; - }; - - vcc_1v2_reg: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "VCC_1V2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - vcc_1v8_reg: regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "VCC_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vcc_3v3_reg: regulator@5 { - compatible = "regulator-fixed"; - reg = <5>; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - }; - - sound { - compatible = "samsung,arndale-wm1811"; - samsung,audio-cpu = <&i2s0>; - samsung,audio-codec = <&wm1811>; - }; - - fixed-rate-clocks { - xxti { - compatible = "samsung,clock-xxti"; - clock-frequency = <24000000>; - }; - }; - - // SMSC USB3503 connected in hardware only mode as a PHY - usb_hub: usb-hub { - compatible = "smsc,usb3503a"; - - reset-gpios = <&gpx3 5 GPIO_ACTIVE_LOW>; - connect-gpios = <&gpd1 7 GPIO_ACTIVE_HIGH>; - }; -}; - -&clock { - assigned-clocks = <&clock CLK_FOUT_EPLL>; - assigned-clock-rates = <49152000>; -}; - -&clock_audss { - assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>; - assigned-clock-parents = <&clock CLK_FOUT_EPLL>; -}; - -&cpu0 { - cpu0-supply = <&buck2_reg>; -}; - -&dsi_0 { - vddcore-supply = <&ldo8_reg>; - vddio-supply = <&ldo10_reg>; - samsung,pll-clock-frequency = <24000000>; - samsung,burst-clock-frequency = <320000000>; - samsung,esc-clock-frequency = <10000000>; - status = "okay"; - - bridge@0 { - reg = <0>; - compatible = "toshiba,tc358764"; - vddc-supply = <&vcc_1v2_reg>; - vddio-supply = <&vcc_1v8_reg>; - vddlvds-supply = <&vcc_3v3_reg>; - reset-gpios = <&gpd1 6 GPIO_ACTIVE_LOW>; - #address-cells = <1>; - #size-cells = <0>; - port@1 { - reg = <1>; - bridge_out_ep: endpoint { - remote-endpoint = <&panel_ep>; - }; - }; - }; -}; - -&fimd { - status = "okay"; -}; - -&hdmi { - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_hpd>; - status = "okay"; - ddc = <&i2c_ddc>; - hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; - vdd_osc-supply = <&ldo10_reg>; - vdd_pll-supply = <&ldo8_reg>; - vdd-supply = <&ldo8_reg>; -}; - -&i2c_0 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <20000>; - samsung,i2c-slave-addr = <0x66>; - - s5m8767_pmic@66 { - compatible = "samsung,s5m8767-pmic"; - reg = <0x66>; - interrupt-parent = <&gpx3>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&s5m8767_irq>; - - vinb1-supply = <&main_dc_reg>; - vinb2-supply = <&main_dc_reg>; - vinb3-supply = <&main_dc_reg>; - vinb4-supply = <&main_dc_reg>; - vinb5-supply = <&main_dc_reg>; - vinb6-supply = <&main_dc_reg>; - vinb7-supply = <&main_dc_reg>; - vinb8-supply = <&main_dc_reg>; - vinb9-supply = <&main_dc_reg>; - - vinl1-supply = <&buck7_reg>; - vinl2-supply = <&buck7_reg>; - vinl3-supply = <&buck7_reg>; - vinl4-supply = <&main_dc_reg>; - vinl5-supply = <&main_dc_reg>; - vinl6-supply = <&main_dc_reg>; - vinl7-supply = <&main_dc_reg>; - vinl8-supply = <&buck8_reg>; - vinl9-supply = <&buck8_reg>; - - s5m8767,pmic-buck2-dvs-voltage = <1300000>; - s5m8767,pmic-buck3-dvs-voltage = <1100000>; - s5m8767,pmic-buck4-dvs-voltage = <1200000>; - s5m8767,pmic-buck-dvs-gpios = <&gpd1 0 GPIO_ACTIVE_HIGH>, - <&gpd1 1 GPIO_ACTIVE_HIGH>, - <&gpd1 2 GPIO_ACTIVE_HIGH>; - s5m8767,pmic-buck-ds-gpios = <&gpx2 3 GPIO_ACTIVE_HIGH>, - <&gpx2 4 GPIO_ACTIVE_HIGH>, - <&gpx2 5 GPIO_ACTIVE_HIGH>; - - s5m8767_osc: clocks { - compatible = "samsung,s5m8767-clk"; - #clock-cells = <1>; - clock-output-names = "s5m8767_ap", "unused1", "unused2"; - }; - - regulators { - ldo1_reg: LDO1 { - regulator-name = "VDD_ALIVE_1.0V"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - ldo2_reg: LDO2 { - regulator-name = "VDD_28IO_DP_1.35V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - ldo3_reg: LDO3 { - regulator-name = "VDD_COMMON1_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - ldo4_reg: LDO4 { - regulator-name = "VDD_IOPERI_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - op_mode = <1>; - }; - - ldo5_reg: LDO5 { - regulator-name = "VDD_EXT_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - ldo6_reg: LDO6 { - regulator-name = "VDD_MPLL_1.1V"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - ldo7_reg: LDO7 { - regulator-name = "VDD_XPLL_1.1V"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - ldo8_reg: LDO8 { - regulator-name = "VDD_COMMON2_1.0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - ldo9_reg: LDO9 { - regulator-name = "VDD_33ON_3.0V"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - op_mode = <1>; - }; - - ldo10_reg: LDO10 { - regulator-name = "VDD_COMMON3_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - ldo11_reg: LDO11 { - regulator-name = "VDD_ABB2_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - ldo12_reg: LDO12 { - regulator-name = "VDD_USB_3.0V"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - ldo13_reg: LDO13 { - regulator-name = "VDDQ_C2C_W_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - ldo14_reg: LDO14 { - regulator-name = "VDD18_ABB0_3_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - ldo15_reg: LDO15 { - regulator-name = "VDD10_COMMON4_1.0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - ldo16_reg: LDO16 { - regulator-name = "VDD18_HSIC_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - ldo17_reg: LDO17 { - regulator-name = "VDDQ_MMC2_3_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - ldo18_reg: LDO18 { - regulator-name = "VDD_33ON_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - op_mode = <1>; - }; - - ldo22_reg: LDO22 { - regulator-name = "EXT_33_OFF"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - op_mode = <1>; - }; - - ldo23_reg: LDO23 { - regulator-name = "EXT_28_OFF"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - op_mode = <1>; - }; - - ldo25_reg: LDO25 { - regulator-name = "PVDD_LDO25"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - op_mode = <1>; - }; - - ldo26_reg: LDO26 { - regulator-name = "EXT_18_OFF"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - op_mode = <1>; - }; - - buck1_reg: BUCK1 { - regulator-name = "vdd_mif"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - buck2_reg: BUCK2 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <912500>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - buck3_reg: BUCK3 { - regulator-name = "vdd_int"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - buck4_reg: BUCK4 { - regulator-name = "vdd_g3d"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - buck5_reg: BUCK5 { - regulator-name = "VDD_MEM_1.35V"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1355000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - buck7_reg: BUCK7 { - regulator-name = "PVDD_BUCK7"; - regulator-always-on; - op_mode = <1>; - }; - - buck8_reg: BUCK8 { - regulator-name = "PVDD_BUCK8"; - regulator-always-on; - op_mode = <1>; - }; - - buck9_reg: BUCK9 { - regulator-name = "VDD_33_OFF_EXT1"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3000000>; - op_mode = <1>; - }; - }; - }; -}; - -&i2c_3 { - status = "okay"; - - wm1811: codec@1a { - compatible = "wlf,wm1811"; - reg = <0x1a>; - clocks = <&i2s0 CLK_I2S_CDCLK>; - clock-names = "MCLK1"; - - AVDD2-supply = <&main_dc_reg>; - CPVDD-supply = <&main_dc_reg>; - DBVDD1-supply = <&main_dc_reg>; - DBVDD2-supply = <&main_dc_reg>; - DBVDD3-supply = <&main_dc_reg>; - LDO1VDD-supply = <&main_dc_reg>; - SPKVDD1-supply = <&main_dc_reg>; - SPKVDD2-supply = <&main_dc_reg>; - - wlf,ldo1ena = <&gpb0 0 GPIO_ACTIVE_HIGH>; - wlf,ldo2ena = <&gpb0 1 GPIO_ACTIVE_HIGH>; - }; -}; - -&i2c_8 { - status = "okay"; - /* used by HDMI PHY */ - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <66000>; -}; - -&i2c_9 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <40000>; - samsung,i2c-slave-addr = <0x38>; - - sata_phy_i2c:sata-phy@38 { - compatible = "samsung,exynos-sataphy-i2c"; - reg = <0x38>; - }; -}; - -&i2s0 { - assigned-clocks = <&i2s0 CLK_I2S_RCLK_SRC>; - assigned-clock-parents = <&clock_audss EXYNOS_I2S_BUS>; - status = "okay"; -}; - -&i2s0_bus { - samsung,pin-drv = ; -}; - -&mali { - mali-supply = <&buck4_reg>; - status = "okay"; -}; - -&mixer { - status = "okay"; -}; - -&mmc_0 { - status = "okay"; - broken-cd; - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; - vmmc-supply = <&mmc_reg>; - pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>; - bus-width = <8>; - cap-mmc-highspeed; -}; - -&mmc_2 { - status = "okay"; - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; - vmmc-supply = <&mmc_reg>; - pinctrl-names = "default"; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; - bus-width = <4>; - disable-wp; - cap-sd-highspeed; -}; - -&pinctrl_0 { - s5m8767_irq: s5m8767-irq { - samsung,pins = "gpx3-2"; - samsung,pin-pud = ; - }; -}; - -&rtc { - clocks = <&clock CLK_RTC>, <&s5m8767_osc S2MPS11_CLK_AP>; - clock-names = "rtc", "rtc_src"; - status = "okay"; -}; - -&sata { - status = "okay"; -}; - -&sata_phy { - status = "okay"; - samsung,exynos-sataphy-i2c-phandle = <&sata_phy_i2c>; -}; - -&soc { - /* - * For unknown reasons HDMI-DDC does not work with Exynos I2C - * controllers. Lets use software I2C over GPIO pins as a workaround. - */ - i2c_ddc: i2c-gpio { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_gpio_bus>; - status = "okay"; - compatible = "i2c-gpio"; - gpios = <&gpa0 6 0 /* sda */ - &gpa0 7 0 /* scl */ - >; - i2c-gpio,delay-us = <2>; - #address-cells = <1>; - #size-cells = <0>; - }; -}; diff --git a/sys/gnu/dts/arm/exynos5250-pinctrl.dtsi b/sys/gnu/dts/arm/exynos5250-pinctrl.dtsi deleted file mode 100644 index d31a68672bf..00000000000 --- a/sys/gnu/dts/arm/exynos5250-pinctrl.dtsi +++ /dev/null @@ -1,833 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's Exynos5250 SoC pin-mux and pin-config device tree source - * - * Copyright (c) 2012 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Samsung's Exynos5250 SoC pin-mux and pin-config optiosn are listed as device - * tree nodes are listed in this file. - */ - -#include - -&pinctrl_0 { - gpa0: gpa0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpa1: gpa1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpa2: gpa2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpb0: gpb0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpb1: gpb1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpb2: gpb2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpb3: gpb3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc0: gpc0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc1: gpc1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc2: gpc2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc3: gpc3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpd0: gpd0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpd1: gpd1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpy0: gpy0 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy1: gpy1 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy2: gpy2 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy3: gpy3 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy4: gpy4 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy5: gpy5 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy6: gpy6 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpc4: gpc4 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpx0: gpx0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - interrupt-parent = <&combiner>; - #interrupt-cells = <2>; - interrupts = <23 0>, <24 0>, <25 0>, <25 1>, - <26 0>, <26 1>, <27 0>, <27 1>; - }; - - gpx1: gpx1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - interrupt-parent = <&combiner>; - #interrupt-cells = <2>; - interrupts = <28 0>, <28 1>, <29 0>, <29 1>, - <30 0>, <30 1>, <31 0>, <31 1>; - }; - - gpx2: gpx2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpx3: gpx3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - uart0_data: uart0-data { - samsung,pins = "gpa0-0", "gpa0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart0_fctl: uart0-fctl { - samsung,pins = "gpa0-2", "gpa0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c2_bus: i2c2-bus { - samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c2_hs_bus: i2c2-hs-bus { - samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c2_gpio_bus: i2c2-gpio-bus { - samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart2_data: uart2-data { - samsung,pins = "gpa1-0", "gpa1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart2_fctl: uart2-fctl { - samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c3_bus: i2c3-bus { - samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c3_hs_bus: i2c3-hs-bus { - samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart3_data: uart3-data { - samsung,pins = "gpa1-4", "gpa1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spi0_bus: spi0-bus { - samsung,pins = "gpa2-0", "gpa2-2", "gpa2-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c4_bus: i2c4-bus { - samsung,pins = "gpa2-0", "gpa2-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c5_bus: i2c5-bus { - samsung,pins = "gpa2-2", "gpa2-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spi1_bus: spi1-bus { - samsung,pins = "gpa2-4", "gpa2-6", "gpa2-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2s1_bus: i2s1-bus { - samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3", - "gpb0-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pcm1_bus: pcm1-bus { - samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3", - "gpb0-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - ac97_bus: ac97-bus { - samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3", - "gpb0-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2s2_bus: i2s2-bus { - samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3", - "gpb1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pcm2_bus: pcm2-bus { - samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3", - "gpb1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spdif_bus: spdif-bus { - samsung,pins = "gpb1-0", "gpb1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spi2_bus: spi2-bus { - samsung,pins = "gpb1-1", "gpb1-3", "gpb1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c6_bus: i2c6-bus { - samsung,pins = "gpb1-3", "gpb1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm0_out: pwm0-out { - samsung,pins = "gpb2-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm1_out: pwm1-out { - samsung,pins = "gpb2-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm2_out: pwm2-out { - samsung,pins = "gpb2-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm3_out: pwm3-out { - samsung,pins = "gpb2-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c7_bus: i2c7-bus { - samsung,pins = "gpb2-2", "gpb2-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c0_bus: i2c0-bus { - samsung,pins = "gpb3-0", "gpb3-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c1_bus: i2c1-bus { - samsung,pins = "gpb3-2", "gpb3-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c0_hs_bus: i2c0-hs-bus { - samsung,pins = "gpb3-0", "gpb3-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c1_hs_bus: i2c1-hs-bus { - samsung,pins = "gpb3-2", "gpb3-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_clk: sd0-clk { - samsung,pins = "gpc0-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_cmd: sd0-cmd { - samsung,pins = "gpc0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_cd: sd0-cd { - samsung,pins = "gpc0-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus1: sd0-bus-width1 { - samsung,pins = "gpc0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus4: sd0-bus-width4 { - samsung,pins = "gpc0-3", "gpc0-4", "gpc0-5", "gpc0-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus8: sd0-bus-width8 { - samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_clk: sd1-clk { - samsung,pins = "gpc2-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_cmd: sd1-cmd { - samsung,pins = "gpc2-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_cd: sd1-cd { - samsung,pins = "gpc2-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_bus1: sd1-bus-width1 { - samsung,pins = "gpc2-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_bus4: sd1-bus-width4 { - samsung,pins = "gpc2-3", "gpc2-4", "gpc2-5", "gpc2-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_clk: sd2-clk { - samsung,pins = "gpc3-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_cmd: sd2-cmd { - samsung,pins = "gpc3-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_cd: sd2-cd { - samsung,pins = "gpc3-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_bus1: sd2-bus-width1 { - samsung,pins = "gpc3-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_bus4: sd2-bus-width4 { - samsung,pins = "gpc3-3", "gpc3-4", "gpc3-5", "gpc3-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_bus8: sd2-bus-width8 { - samsung,pins = "gpc4-3", "gpc4-4", "gpc4-5", "gpc4-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd3_clk: sd3-clk { - samsung,pins = "gpc4-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd3_cmd: sd3-cmd { - samsung,pins = "gpc4-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd3_cd: sd3-cd { - samsung,pins = "gpc4-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd3_bus1: sd3-bus-width1 { - samsung,pins = "gpc4-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd3_bus4: sd3-bus-width4 { - samsung,pins = "gpc4-3", "gpc4-4", "gpc4-5", "gpc4-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart1_data: uart1-data { - samsung,pins = "gpd0-0", "gpd0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart1_fctl: uart1-fctl { - samsung,pins = "gpd0-2", "gpd0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - dp_hpd: dp_hpd { - samsung,pins = "gpx0-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - hdmi_cec: hdmi-cec { - samsung,pins = "gpx3-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - hdmi_hpd: hdmi-hpd { - samsung,pins = "gpx3-7"; - samsung,pin-pud = ; - }; -}; - -&pinctrl_1 { - gpe0: gpe0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpe1: gpe1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf0: gpf0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf1: gpf1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpg0: gpg0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpg1: gpg1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpg2: gpg2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gph0: gph0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gph1: gph1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - cam_gpio_a: cam-gpio-a { - samsung,pins = "gpe0-0", "gpe0-1", "gpe0-2", "gpe0-3", - "gpe0-4", "gpe0-5", "gpe0-6", "gpe0-7", - "gpe1-0", "gpe1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_gpio_b: cam-gpio-b { - samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3", - "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_i2c2_bus: cam-i2c2-bus { - samsung,pins = "gpe0-6", "gpe1-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_spi1_bus: cam-spi1-bus { - samsung,pins = "gpe0-4", "gpe0-5", "gpf0-2", "gpf0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_i2c1_bus: cam-i2c1-bus { - samsung,pins = "gpf0-2", "gpf0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_i2c0_bus: cam-i2c0-bus { - samsung,pins = "gpf0-0", "gpf0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_spi0_bus: cam-spi0-bus { - samsung,pins = "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_bayrgb_bus: cam-bayrgb-bus { - samsung,pins = "gpg0-0", "gpg0-1", "gpg0-2", "gpg0-3", - "gpg0-4", "gpg0-5", "gpg0-6", "gpg0-7", - "gpg1-0", "gpg1-1", "gpg1-2", "gpg1-3", - "gpg1-4", "gpg1-5", "gpg1-6", "gpg1-7", - "gpg2-0", "gpg2-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_port_a: cam-port-a { - samsung,pins = "gph0-0", "gph0-1", "gph0-2", "gph0-3", - "gph1-0", "gph1-1", "gph1-2", "gph1-3", - "gph1-4", "gph1-5", "gph1-6", "gph1-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pinctrl_2 { - gpv0: gpv0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpv1: gpv1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpv2: gpv2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpv3: gpv3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpv4: gpv4 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - c2c_rxd: c2c-rxd { - samsung,pins = "gpv0-0", "gpv0-1", "gpv0-2", "gpv0-3", - "gpv0-4", "gpv0-5", "gpv0-6", "gpv0-7", - "gpv1-0", "gpv1-1", "gpv1-2", "gpv1-3", - "gpv1-4", "gpv1-5", "gpv1-6", "gpv1-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - c2c_txd: c2c-txd { - samsung,pins = "gpv2-0", "gpv2-1", "gpv2-2", "gpv2-3", - "gpv2-4", "gpv2-5", "gpv2-6", "gpv2-7", - "gpv3-0", "gpv3-1", "gpv3-2", "gpv3-3", - "gpv3-4", "gpv3-5", "gpv3-6", "gpv3-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pinctrl_3 { - gpz: gpz { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - i2s0_bus: i2s0-bus { - samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", - "gpz-4", "gpz-5", "gpz-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; diff --git a/sys/gnu/dts/arm/exynos5250-smdk5250.dts b/sys/gnu/dts/arm/exynos5250-smdk5250.dts deleted file mode 100644 index 5c42df024ad..00000000000 --- a/sys/gnu/dts/arm/exynos5250-smdk5250.dts +++ /dev/null @@ -1,417 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung SMDK5250 board device tree source - * - * Copyright (c) 2012 Samsung Electronics Co., Ltd. - * http://www.samsung.com - */ - -/dts-v1/; -#include -#include -#include "exynos5250.dtsi" - -/ { - model = "Samsung SMDK5250 board based on Exynos5250"; - compatible = "samsung,smdk5250", "samsung,exynos5250", "samsung,exynos5"; - - aliases { - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x80000000>; - }; - - chosen { - bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M init=/linuxrc"; - stdout-path = "serial2:115200n8"; - }; - - vdd: fixed-regulator-vdd { - compatible = "regulator-fixed"; - regulator-name = "vdd-supply"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - dbvdd: fixed-regulator-dbvdd { - compatible = "regulator-fixed"; - regulator-name = "dbvdd-supply"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - spkvdd: fixed-regulator-spkvdd { - compatible = "regulator-fixed"; - regulator-name = "spkvdd-supply"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - sound { - compatible = "samsung,smdk-wm8994"; - - samsung,i2s-controller = <&i2s0>; - samsung,audio-codec = <&wm8994>; - }; - - fixed-rate-clocks { - xxti { - compatible = "samsung,clock-xxti"; - clock-frequency = <24000000>; - }; - - codec_mclk: codec-mclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <16934000>; - }; - }; -}; - -&cpu0 { - cpu0-supply = <&buck2_reg>; -}; - -&dp { - samsung,color-space = <0>; - samsung,color-depth = <1>; - samsung,link-rate = <0x0a>; - samsung,lane-count = <4>; - - pinctrl-names = "default"; - pinctrl-0 = <&dp_hpd>; - status = "okay"; - - display-timings { - native-mode = <&timing0>; - - timing0: timing { - /* 1280x800 */ - clock-frequency = <50000>; - hactive = <1280>; - vactive = <800>; - hfront-porch = <4>; - hback-porch = <4>; - hsync-len = <4>; - vback-porch = <4>; - vfront-porch = <4>; - vsync-len = <4>; - }; - }; -}; - -&ehci { - samsung,vbus-gpio = <&gpx2 6 GPIO_ACTIVE_HIGH>; -}; - -&fimd { - status = "okay"; -}; - -&hdmi { - status = "okay"; - ddc = <&i2c_2>; - hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; -}; - -&i2c_0 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <20000>; - - eeprom@50 { - compatible = "samsung,s524ad0xd1"; - reg = <0x50>; - }; - - max77686@9 { - compatible = "maxim,max77686"; - reg = <0x09>; - interrupt-parent = <&gpx3>; - interrupts = <2 IRQ_TYPE_NONE>; - pinctrl-names = "default"; - pinctrl-0 = <&max77686_irq>; - wakeup-source; - - voltage-regulators { - ldo1_reg: LDO1 { - regulator-name = "P1.0V_LDO_OUT1"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo2_reg: LDO2 { - regulator-name = "P1.2V_LDO_OUT2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - ldo3_reg: LDO3 { - regulator-name = "P1.8V_LDO_OUT3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo4_reg: LDO4 { - regulator-name = "P2.8V_LDO_OUT4"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo5_reg: LDO5 { - regulator-name = "P1.8V_LDO_OUT5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo6_reg: LDO6 { - regulator-name = "P1.1V_LDO_OUT6"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - ldo7_reg: LDO7 { - regulator-name = "P1.1V_LDO_OUT7"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - ldo8_reg: LDO8 { - regulator-name = "P1.0V_LDO_OUT8"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - }; - - ldo10_reg: LDO10 { - regulator-name = "P1.8V_LDO_OUT10"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo11_reg: LDO11 { - regulator-name = "P1.8V_LDO_OUT11"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo12_reg: LDO12 { - regulator-name = "P3.0V_LDO_OUT12"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - ldo13_reg: LDO13 { - regulator-name = "P1.8V_LDO_OUT13"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo14_reg: LDO14 { - regulator-name = "P1.8V_LDO_OUT14"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo15_reg: LDO15 { - regulator-name = "P1.0V_LDO_OUT15"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - }; - - ldo16_reg: LDO16 { - regulator-name = "P1.8V_LDO_OUT16"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - buck1_reg: BUCK1 { - regulator-name = "vdd_mif"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - }; - - buck2_reg: BUCK2 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - - buck3_reg: BUCK3 { - regulator-name = "vdd_int"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - }; - - buck4_reg: BUCK4 { - regulator-name = "vdd_g3d"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - }; - - buck5_reg: BUCK5 { - regulator-name = "P1.8V_BUCK_OUT5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - }; - }; -}; - -&i2c_1 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <20000>; - - eeprom@51 { - compatible = "samsung,s524ad0xd1"; - reg = <0x51>; - }; - - wm8994: wm8994@1a { - compatible = "wlf,wm8994"; - reg = <0x1a>; - - gpio-controller; - #gpio-cells = <2>; - - clocks = <&codec_mclk>; - clock-names = "MCLK1"; - - AVDD2-supply = <&vdd>; - CPVDD-supply = <&vdd>; - DBVDD-supply = <&dbvdd>; - SPKVDD1-supply = <&spkvdd>; - SPKVDD2-supply = <&spkvdd>; - }; -}; - -&i2c_2 { - status = "okay"; - /* used by HDMI DDC */ - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <66000>; -}; - -&i2c_8 { - status = "okay"; - /* used by HDMI PHY */ - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <66000>; -}; - -&i2c_9 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <40000>; - samsung,i2c-slave-addr = <0x38>; - - sata_phy_i2c: sata-phy@38 { - compatible = "samsung,exynos-sataphy-i2c"; - reg = <0x38>; - }; -}; - -&i2s0 { - status = "okay"; -}; - -&mixer { - status = "okay"; -}; - -&mmc_0 { - status = "okay"; - broken-cd; - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>; - bus-width = <8>; - cap-mmc-highspeed; -}; - -&mmc_2 { - status = "okay"; - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; - bus-width = <4>; - disable-wp; - cap-sd-highspeed; -}; - -&rtc { - status = "okay"; -}; - -&sata { - status = "okay"; -}; - -&sata_phy { - status = "okay"; - samsung,exynos-sataphy-i2c-phandle = <&sata_phy_i2c>; -}; - -&spi_1 { - status = "okay"; - cs-gpios = <&gpa2 5 GPIO_ACTIVE_HIGH>; - - w25q80bw@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "w25x80"; - reg = <0>; - spi-max-frequency = <1000000>; - - controller-data { - samsung,spi-feedback-delay = <0>; - }; - - partition@0 { - label = "U-Boot"; - reg = <0x0 0x40000>; - read-only; - }; - - partition@40000 { - label = "Kernel"; - reg = <0x40000 0xc0000>; - }; - }; -}; - -&pinctrl_0 { - max77686_irq: max77686-irq { - samsung,pins = "gpx3-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; diff --git a/sys/gnu/dts/arm/exynos5250-snow-common.dtsi b/sys/gnu/dts/arm/exynos5250-snow-common.dtsi deleted file mode 100644 index c952a615148..00000000000 --- a/sys/gnu/dts/arm/exynos5250-snow-common.dtsi +++ /dev/null @@ -1,709 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Google Snow board device tree source - * - * Copyright (c) 2012 Google, Inc - */ - -#include -#include -#include -#include -#include -#include "exynos5250.dtsi" - -/ { - aliases { - i2c104 = &i2c_104; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x80000000>; - }; - - chosen { - bootargs = "console=tty1"; - stdout-path = "serial3:115200n8"; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&power_key_irq &lid_irq>; - - power { - label = "Power"; - gpios = <&gpx1 3 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - - lid-switch { - label = "Lid"; - gpios = <&gpx3 5 GPIO_ACTIVE_LOW>; - linux,input-type = <5>; /* EV_SW */ - linux,code = <0>; /* SW_LID */ - debounce-interval = <1>; - wakeup-source; - }; - }; - - vbat: vbat-fixed-regulator { - compatible = "regulator-fixed"; - regulator-name = "vbat-supply"; - regulator-boot-on; - }; - - i2c-arbitrator { - compatible = "i2c-arb-gpio-challenge"; - #address-cells = <1>; - #size-cells = <0>; - - i2c-parent = <&i2c_4>; - - our-claim-gpio = <&gpf0 3 GPIO_ACTIVE_LOW>; - their-claim-gpios = <&gpe0 4 GPIO_ACTIVE_LOW>; - slew-delay-us = <10>; - wait-retry-us = <3000>; - wait-free-us = <50000>; - - pinctrl-names = "default"; - pinctrl-0 = <&arb_our_claim &arb_their_claim>; - - /* Use ID 104 as a hint that we're on physical bus 4 */ - i2c_104: i2c@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - battery: sbs-battery@b { - compatible = "sbs,sbs-battery"; - reg = <0xb>; - sbs,poll-retry-count = <1>; - }; - - cros_ec: embedded-controller@1e { - compatible = "google,cros-ec-i2c"; - reg = <0x1e>; - interrupts = <6 IRQ_TYPE_NONE>; - interrupt-parent = <&gpx1>; - pinctrl-names = "default"; - pinctrl-0 = <&ec_irq>; - wakeup-source; - }; - - power-regulator@48 { - compatible = "ti,tps65090"; - reg = <0x48>; - - /* - * Config irq to disable internal pulls - * even though we run in polling mode. - */ - pinctrl-names = "default"; - pinctrl-0 = <&tps65090_irq>; - - vsys1-supply = <&vbat>; - vsys2-supply = <&vbat>; - vsys3-supply = <&vbat>; - infet1-supply = <&vbat>; - infet2-supply = <&vbat>; - infet3-supply = <&vbat>; - infet4-supply = <&vbat>; - infet5-supply = <&vbat>; - infet6-supply = <&vbat>; - infet7-supply = <&vbat>; - vsys-l1-supply = <&vbat>; - vsys-l2-supply = <&vbat>; - - regulators { - dcdc1 { - ti,enable-ext-control; - }; - dcdc2 { - ti,enable-ext-control; - }; - dcdc3 { - ti,enable-ext-control; - }; - fet1: fet1 { - regulator-name = "vcd_led"; - ti,overcurrent-wait = <3>; - }; - tps65090_fet2: fet2 { - regulator-name = "video_mid"; - regulator-always-on; - ti,overcurrent-wait = <3>; - }; - fet3 { - regulator-name = "wwan_r"; - regulator-always-on; - ti,overcurrent-wait = <3>; - }; - fet4 { - regulator-name = "sdcard"; - ti,overcurrent-wait = <3>; - }; - fet5 { - regulator-name = "camout"; - regulator-always-on; - ti,overcurrent-wait = <3>; - }; - fet6: fet6 { - regulator-name = "lcd_vdd"; - ti,overcurrent-wait = <3>; - }; - tps65090_fet7: fet7 { - regulator-name = "video_mid_1a"; - regulator-always-on; - ti,overcurrent-wait = <3>; - }; - ldo1 { - }; - ldo2 { - }; - }; - - charger { - compatible = "ti,tps65090-charger"; - }; - }; - }; - }; - - sound { - samsung,i2s-controller = <&i2s0>; - }; - - usb3_vbus_reg: regulator-usb3 { - compatible = "regulator-fixed"; - regulator-name = "P5.0V_USB3CON"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpx2 7 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&usb3_vbus_en>; - enable-active-high; - }; - - fixed-rate-clocks { - xxti { - compatible = "samsung,clock-xxti"; - clock-frequency = <24000000>; - }; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 0 1000000 0>; - brightness-levels = <0 100 500 1000 1500 2000 2500 2800>; - default-brightness-level = <7>; - enable-gpios = <&gpx3 0 GPIO_ACTIVE_HIGH>; - power-supply = <&fet1>; - pinctrl-0 = <&pwm0_out>; - pinctrl-names = "default"; - }; - - panel: panel { - compatible = "auo,b116xw03"; - power-supply = <&fet6>; - backlight = <&backlight>; - - port { - panel_in: endpoint { - remote-endpoint = <&bridge_out>; - }; - }; - }; - - mmc3_pwrseq: mmc3_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpx0 2 GPIO_ACTIVE_LOW>, /* WIFI_RSTn */ - <&gpx0 1 GPIO_ACTIVE_LOW>; /* WIFI_EN */ - clocks = <&max77686 MAX77686_CLK_PMIC>; - clock-names = "ext_clock"; - }; -}; - -&clock { - assigned-clocks = <&clock CLK_FOUT_EPLL>; - assigned-clock-rates = <49152000>; -}; - -&clock_audss { - assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>; - assigned-clock-parents = <&clock CLK_FOUT_EPLL>; -}; - -&cpu0 { - cpu0-supply = <&buck2_reg>; -}; - -&dp { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&dp_hpd>; - samsung,color-space = <0>; - samsung,color-depth = <1>; - samsung,link-rate = <0x0a>; - samsung,lane-count = <2>; - hpd-gpios = <&gpx0 7 GPIO_ACTIVE_HIGH>; - - ports { - port { - dp_out: endpoint { - remote-endpoint = <&bridge_in>; - }; - }; - }; -}; - -&ehci { - samsung,vbus-gpio = <&gpx1 1 GPIO_ACTIVE_HIGH>; -}; - -&fimd { - status = "okay"; - samsung,invert-vclk; -}; - -&hdmi { - status = "okay"; - hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_hpd_irq>; - ddc = <&i2c_2>; - hdmi-en-supply = <&tps65090_fet7>; - vdd-supply = <&ldo8_reg>; - vdd_osc-supply = <&ldo10_reg>; - vdd_pll-supply = <&ldo8_reg>; -}; - -&hdmicec { - status = "okay"; -}; - -&i2c_0 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <378000>; - - max77686: max77686@9 { - compatible = "maxim,max77686"; - interrupt-parent = <&gpx3>; - interrupts = <2 IRQ_TYPE_NONE>; - pinctrl-names = "default"; - pinctrl-0 = <&max77686_irq>; - wakeup-source; - reg = <0x09>; - #clock-cells = <1>; - - voltage-regulators { - ldo1_reg: LDO1 { - regulator-name = "P1.0V_LDO_OUT1"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo2_reg: LDO2 { - regulator-name = "P1.8V_LDO_OUT2"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo3_reg: LDO3 { - regulator-name = "P1.8V_LDO_OUT3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo7_reg: LDO7 { - regulator-name = "P1.1V_LDO_OUT7"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - ldo8_reg: LDO8 { - regulator-name = "P1.0V_LDO_OUT8"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo10_reg: LDO10 { - regulator-name = "P1.8V_LDO_OUT10"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo12_reg: LDO12 { - regulator-name = "P3.0V_LDO_OUT12"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - }; - - ldo14_reg: LDO14 { - regulator-name = "P1.8V_LDO_OUT14"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo15_reg: LDO15 { - regulator-name = "P1.0V_LDO_OUT15"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo16_reg: LDO16 { - regulator-name = "P1.8V_LDO_OUT16"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - buck1_reg: BUCK1 { - regulator-name = "vdd_mif"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - }; - - buck2_reg: BUCK2 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - - buck3_reg: BUCK3 { - regulator-name = "vdd_int"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - }; - - buck4_reg: BUCK4 { - regulator-name = "vdd_g3d"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - }; - - buck5_reg: BUCK5 { - regulator-name = "P1.8V_BUCK_OUT5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - buck6_reg: BUCK6 { - regulator-name = "P1.35V_BUCK_OUT6"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - }; - - buck7_reg: BUCK7 { - regulator-name = "P2.0V_BUCK_OUT7"; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - regulator-always-on; - }; - - buck8_reg: BUCK8 { - regulator-name = "P2.85V_BUCK_OUT8"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - regulator-always-on; - }; - }; - }; -}; - -&i2c_1 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <378000>; - - trackpad@67 { - reg = <0x67>; - compatible = "cypress,cyapa"; - interrupts = <2 IRQ_TYPE_NONE>; - interrupt-parent = <&gpx1>; - wakeup-source; - }; -}; - -/* - * Disabled pullups since external part has its own pullups and - * double-pulling gets us out of spec in some cases. - */ -&i2c2_bus { - samsung,pin-pud = ; -}; - -&i2c_2 { - status = "okay"; - /* used by HDMI DDC */ - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <66000>; -}; - -&i2c_3 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <66000>; -}; - -&i2c_4 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <66000>; -}; - -&i2c_5 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <66000>; -}; - -&i2c_7 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <66000>; - - ptn3460: lvds-bridge@20 { - compatible = "nxp,ptn3460"; - reg = <0x20>; - powerdown-gpios = <&gpy2 5 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpx1 5 GPIO_ACTIVE_HIGH>; - edid-emulation = <5>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - bridge_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - - port@1 { - reg = <1>; - - bridge_in: endpoint { - remote-endpoint = <&dp_out>; - }; - }; - }; - }; -}; - -&i2c_8 { - status = "okay"; - /* used by HDMI PHY */ - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <378000>; -}; - -&i2s0 { - assigned-clocks = <&i2s0 CLK_I2S_RCLK_SRC>; - assigned-clock-parents = <&clock_audss EXYNOS_I2S_BUS>; - status = "okay"; -}; - -&mali { - mali-supply = <&buck4_reg>; - status = "okay"; -}; - -&mixer { - status = "okay"; -}; - -/* eMMC flash */ -&mmc_0 { - status = "okay"; - non-removable; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4 &sd0_bus8>; - bus-width = <8>; - cap-mmc-highspeed; -}; - -/* uSD card */ -&mmc_2 { - status = "okay"; - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; - bus-width = <4>; - wp-gpios = <&gpc2 1 GPIO_ACTIVE_HIGH>; - cap-sd-highspeed; -}; - -/* - * On Snow we've got SIP WiFi and so can keep drive strengths low to - * reduce EMI. - * - * WiFi SDIO module - */ -&mmc_3 { - status = "okay"; - non-removable; - cap-sdio-irq; - keep-power-in-suspend; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd3_clk &sd3_cmd &sd3_bus4 &wifi_en &wifi_rst>; - bus-width = <4>; - cap-sd-highspeed; - mmc-pwrseq = <&mmc3_pwrseq>; -}; - -&pinctrl_0 { - wifi_en: wifi-en { - samsung,pins = "gpx0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - wifi_rst: wifi-rst { - samsung,pins = "gpx0-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - power_key_irq: power-key-irq { - samsung,pins = "gpx1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - ec_irq: ec-irq { - samsung,pins = "gpx1-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - tps65090_irq: tps65090-irq { - samsung,pins = "gpx2-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - usb3_vbus_en: usb3-vbus-en { - samsung,pins = "gpx2-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - max77686_irq: max77686-irq { - samsung,pins = "gpx3-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - lid_irq: lid-irq { - samsung,pins = "gpx3-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - hdmi_hpd_irq: hdmi-hpd-irq { - samsung,pins = "gpx3-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pinctrl_1 { - arb_their_claim: arb-their-claim { - samsung,pins = "gpe0-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - arb_our_claim: arb-our-claim { - samsung,pins = "gpf0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pmu_system_controller { - assigned-clocks = <&pmu_system_controller 0>; - assigned-clock-parents = <&clock CLK_FIN_PLL>; -}; - -&rtc { - status = "okay"; - clocks = <&clock CLK_RTC>, <&max77686 MAX77686_CLK_AP>; - clock-names = "rtc", "rtc_src"; -}; - -&sd3_bus4 { - samsung,pin-drv = ; -}; - -&sd3_clk { - samsung,pin-drv = ; -}; - -&sd3_cmd { - samsung,pin-pud = ; - samsung,pin-drv = ; -}; - -&spi_1 { - status = "okay"; - samsung,spi-src-clk = <0>; - num-cs = <1>; - cs-gpios = <&gpa2 5 GPIO_ACTIVE_HIGH>; -}; - -&usbdrd_dwc3 { - dr_mode = "host"; -}; - -&usbdrd_phy { - vbus-supply = <&usb3_vbus_reg>; -}; - -#include "cros-ec-keyboard.dtsi" diff --git a/sys/gnu/dts/arm/exynos5250-snow-rev5.dts b/sys/gnu/dts/arm/exynos5250-snow-rev5.dts deleted file mode 100644 index 7cbfc6f1f4b..00000000000 --- a/sys/gnu/dts/arm/exynos5250-snow-rev5.dts +++ /dev/null @@ -1,55 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Google Snow Rev 5+ board device tree source - * - * Copyright (c) 2012 Google, Inc - * Copyright (c) 2015 Samsung Electronics Co., Ltd. - * http://www.samsung.com - */ - -/dts-v1/; -#include "exynos5250-snow-common.dtsi" - -/ { - model = "Google Snow Rev 5+"; - compatible = "google,snow-rev5", "samsung,exynos5250", - "samsung,exynos5"; - - sound { - compatible = "google,snow-audio-max98090"; - - samsung,model = "Snow-I2S-MAX98090"; - samsung,audio-codec = <&max98090>; - - cpu { - sound-dai = <&i2s0 0>; - }; - - codec { - sound-dai = <&max98090 0>, <&hdmi>; - }; - }; -}; - -&i2c_7 { - max98090: codec@10 { - compatible = "maxim,max98090"; - reg = <0x10>; - interrupts = <4 IRQ_TYPE_NONE>; - interrupt-parent = <&gpx0>; - pinctrl-names = "default"; - pinctrl-0 = <&max98090_irq>; - clocks = <&pmu_system_controller 0>; - clock-names = "mclk"; - #sound-dai-cells = <1>; - }; -}; - -&pinctrl_0 { - max98090_irq: max98090-irq { - samsung,pins = "gpx0-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; diff --git a/sys/gnu/dts/arm/exynos5250-snow.dts b/sys/gnu/dts/arm/exynos5250-snow.dts deleted file mode 100644 index 75fdc5e6d42..00000000000 --- a/sys/gnu/dts/arm/exynos5250-snow.dts +++ /dev/null @@ -1,51 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Google Snow board device tree source - * - * Copyright (c) 2012 Google, Inc - */ - -/dts-v1/; -#include "exynos5250-snow-common.dtsi" - -/ { - model = "Google Snow"; - compatible = "google,snow-rev4", "google,snow", "samsung,exynos5250", - "samsung,exynos5"; - - sound { - compatible = "google,snow-audio-max98095"; - - samsung,model = "Snow-I2S-MAX98095"; - samsung,audio-codec = <&max98095>; - - cpu { - sound-dai = <&i2s0 0>; - }; - - codec { - sound-dai = <&max98095 0>, <&hdmi>; - }; - }; -}; - -&i2c_7 { - max98095: codec@11 { - compatible = "maxim,max98095"; - reg = <0x11>; - pinctrl-names = "default"; - pinctrl-0 = <&max98095_en>; - clocks = <&pmu_system_controller 0>; - clock-names = "mclk"; - #sound-dai-cells = <1>; - }; -}; - -&pinctrl_0 { - max98095_en: max98095-en { - samsung,pins = "gpx1-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; diff --git a/sys/gnu/dts/arm/exynos5250-spring.dts b/sys/gnu/dts/arm/exynos5250-spring.dts deleted file mode 100644 index 3d501926c22..00000000000 --- a/sys/gnu/dts/arm/exynos5250-spring.dts +++ /dev/null @@ -1,548 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Google Spring board device tree source - * - * Copyright (c) 2013 Google, Inc - * Copyright (c) 2014 SUSE LINUX Products GmbH - */ - -/dts-v1/; -#include -#include -#include -#include "exynos5250.dtsi" - -/ { - model = "Google Spring"; - compatible = "google,spring", "samsung,exynos5250", "samsung,exynos5"; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x80000000>; - }; - - chosen { - bootargs = "console=tty1"; - stdout-path = "serial3:115200n8"; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&power_key_irq>, <&lid_irq>; - - power { - label = "Power"; - gpios = <&gpx1 3 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - - lid-switch { - label = "Lid"; - gpios = <&gpx3 5 GPIO_ACTIVE_LOW>; - linux,input-type = <5>; /* EV_SW */ - linux,code = <0>; /* SW_LID */ - debounce-interval = <1>; - wakeup-source; - }; - }; - - usb-hub { - compatible = "smsc,usb3503a"; - reset-gpios = <&gpe1 0 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&hsic_reset>; - }; - - fixed-rate-clocks { - xxti { - compatible = "samsung,clock-xxti"; - clock-frequency = <24000000>; - }; - }; -}; - -&cpu0 { - cpu0-supply = <&buck2_reg>; -}; - -&dp { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&dp_hpd_gpio>; - samsung,color-space = <0>; - samsung,color-depth = <1>; - samsung,link-rate = <0x0a>; - samsung,lane-count = <1>; - hpd-gpios = <&gpc3 0 GPIO_ACTIVE_HIGH>; -}; - -&ehci { - samsung,vbus-gpio = <&gpx1 1 GPIO_ACTIVE_HIGH>; -}; - -&fimd { - status = "okay"; - samsung,invert-vclk; -}; - -&hdmi { - status = "okay"; - hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_hpd_irq>; - ddc = <&i2c_2>; - hdmi-en-supply = <&ldo8_reg>; - vdd-supply = <&ldo8_reg>; - vdd_osc-supply = <&ldo10_reg>; - vdd_pll-supply = <&ldo8_reg>; -}; - -&i2c_0 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <378000>; - - s5m8767-pmic@66 { - compatible = "samsung,s5m8767-pmic"; - reg = <0x66>; - interrupt-parent = <&gpx3>; - interrupts = <2 IRQ_TYPE_NONE>; - pinctrl-names = "default"; - pinctrl-0 = <&s5m8767_irq &s5m8767_dvs &s5m8767_ds>; - wakeup-source; - - s5m8767,pmic-buck-dvs-gpios = <&gpd1 0 GPIO_ACTIVE_LOW>, /* DVS1 */ - <&gpd1 1 GPIO_ACTIVE_LOW>, /* DVS2 */ - <&gpd1 2 GPIO_ACTIVE_LOW>; /* DVS3 */ - - s5m8767,pmic-buck-ds-gpios = <&gpx2 3 GPIO_ACTIVE_LOW>, /* SET1 */ - <&gpx2 4 GPIO_ACTIVE_LOW>, /* SET2 */ - <&gpx2 5 GPIO_ACTIVE_LOW>; /* SET3 */ - - /* - * The following arrays of DVS voltages are not used, since we are - * not using GPIOs to control PMIC bucks, but they must be defined - * to please the driver. - */ - s5m8767,pmic-buck2-dvs-voltage = <1350000>, <1300000>, - <1250000>, <1200000>, - <1150000>, <1100000>, - <1000000>, <950000>; - - s5m8767,pmic-buck3-dvs-voltage = <1100000>, <1100000>, - <1100000>, <1100000>, - <1000000>, <1000000>, - <1000000>, <1000000>; - - s5m8767,pmic-buck4-dvs-voltage = <1200000>, <1200000>, - <1200000>, <1200000>, - <1200000>, <1200000>, - <1200000>, <1200000>; - - clocks { - compatible = "samsung,s5m8767-clk"; - #clock-cells = <1>; - clock-output-names = "en32khz_ap", - "en32khz_cp", - "en32khz_bt"; - }; - - regulators { - ldo4_reg: LDO4 { - regulator-name = "P1.0V_LDO_OUT4"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - op_mode = <0>; - }; - - ldo5_reg: LDO5 { - regulator-name = "P1.0V_LDO_OUT5"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - op_mode = <0>; - }; - - ldo6_reg: LDO6 { - regulator-name = "vdd_mydp"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - op_mode = <3>; - }; - - ldo7_reg: LDO7 { - regulator-name = "P1.1V_LDO_OUT7"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - op_mode = <3>; - }; - - ldo8_reg: LDO8 { - regulator-name = "P1.0V_LDO_OUT8"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - op_mode = <3>; - }; - - ldo10_reg: LDO10 { - regulator-name = "P1.8V_LDO_OUT10"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - op_mode = <3>; - }; - - ldo11_reg: LDO11 { - regulator-name = "P1.8V_LDO_OUT11"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - op_mode = <0>; - }; - - ldo12_reg: LDO12 { - regulator-name = "P3.0V_LDO_OUT12"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - op_mode = <3>; - }; - - ldo13_reg: LDO13 { - regulator-name = "P1.8V_LDO_OUT13"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - op_mode = <0>; - }; - - ldo14_reg: LDO14 { - regulator-name = "P1.8V_LDO_OUT14"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - op_mode = <3>; - }; - - ldo15_reg: LDO15 { - regulator-name = "P1.0V_LDO_OUT15"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - op_mode = <3>; - }; - - ldo16_reg: LDO16 { - regulator-name = "P1.8V_LDO_OUT16"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - op_mode = <3>; - }; - - ldo17_reg: LDO17 { - regulator-name = "P2.8V_LDO_OUT17"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - op_mode = <0>; - }; - - ldo25_reg: LDO25 { - regulator-name = "vdd_bridge"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - op_mode = <1>; - }; - - buck1_reg: BUCK1 { - regulator-name = "vdd_mif"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - op_mode = <3>; - }; - - buck2_reg: BUCK2 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - op_mode = <3>; - }; - - buck3_reg: BUCK3 { - regulator-name = "vdd_int"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - op_mode = <3>; - }; - - buck4_reg: BUCK4 { - regulator-name = "vdd_g3d"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - op_mode = <3>; - }; - - buck5_reg: BUCK5 { - regulator-name = "P1.8V_BUCK_OUT5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - buck6_reg: BUCK6 { - regulator-name = "P1.2V_BUCK_OUT6"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - op_mode = <0>; - }; - - buck9_reg: BUCK9 { - regulator-name = "vdd_ummc"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - regulator-boot-on; - op_mode = <3>; - }; - }; - }; -}; - -&i2c_1 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <378000>; - - trackpad@4b { - compatible = "atmel,maxtouch"; - reg = <0x4b>; - interrupt-parent = <&gpx1>; - interrupts = <2 IRQ_TYPE_EDGE_FALLING>; - pinctrl-names = "default"; - pinctrl-0 = <&trackpad_irq>; - linux,gpio-keymap = ; - wakeup-source; - }; -}; - -/* - * Disabled pullups since external part has its own pullups and - * double-pulling gets us out of spec in some cases. - */ -&i2c2_bus { - samsung,pin-pud = ; -}; - -&i2c_2 { - status = "okay"; - /* used by HDMI DDC */ - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <66000>; -}; - -&i2c_3 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <66000>; -}; - -&i2c_4 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <66000>; - - cros_ec: embedded-controller@1e { - compatible = "google,cros-ec-i2c"; - reg = <0x1e>; - interrupts = <6 IRQ_TYPE_NONE>; - interrupt-parent = <&gpx1>; - wakeup-source; - pinctrl-names = "default"; - pinctrl-0 = <&ec_irq>; - }; -}; - -&i2c_5 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <66000>; -}; - -&i2c_7 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <66000>; - - temperature-sensor@4c { - compatible = "gmt,g781"; - reg = <0x4c>; - }; -}; - -&i2c_8 { - status = "okay"; - /* used by HDMI PHY */ - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <378000>; -}; - -&i2s0 { - status = "okay"; -}; - -&mixer { - status = "okay"; -}; - -&mmc_0 { - status = "okay"; - broken-cd; - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4 &sd0_bus8>; - bus-width = <8>; - cap-mmc-highspeed; -}; - -/* - * On Spring we've got SIP WiFi and so can keep drive strengths low to - * reduce EMI. - */ -&mmc_1 { - status = "okay"; - broken-cd; - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus4>; - bus-width = <4>; - cap-sd-highspeed; -}; - -&pinctrl_0 { - s5m8767_dvs: s5m8767-dvs { - samsung,pins = "gpd1-0", "gpd1-1", "gpd1-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - dp_hpd_gpio: dp-hpd-gpio { - samsung,pins = "gpc3-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - trackpad_irq: trackpad-irq { - samsung,pins = "gpx1-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - power_key_irq: power-key-irq { - samsung,pins = "gpx1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - ec_irq: ec-irq { - samsung,pins = "gpx1-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - s5m8767_ds: s5m8767-ds { - samsung,pins = "gpx2-3", "gpx2-4", "gpx2-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - s5m8767_irq: s5m8767-irq { - samsung,pins = "gpx3-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - lid_irq: lid-irq { - samsung,pins = "gpx3-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - hdmi_hpd_irq: hdmi-hpd-irq { - samsung,pins = "gpx3-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pinctrl_1 { - hsic_reset: hsic-reset { - samsung,pins = "gpe1-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&sd1_bus4 { - samsung,pin-drv = ; -}; - -&sd1_cd { - samsung,pin-drv = ; -}; - -&sd1_clk { - samsung,pin-drv = ; -}; - -&sd1_cmd { - samsung,pin-pud = ; - samsung,pin-drv = ; -}; - -&spi_1 { - status = "okay"; - samsung,spi-src-clk = <0>; - num-cs = <1>; -}; - -#include "cros-ec-keyboard.dtsi" diff --git a/sys/gnu/dts/arm/exynos5250.dtsi b/sys/gnu/dts/arm/exynos5250.dtsi deleted file mode 100644 index b6135af7ef3..00000000000 --- a/sys/gnu/dts/arm/exynos5250.dtsi +++ /dev/null @@ -1,1237 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung Exynos5250 SoC device tree source - * - * Copyright (c) 2012 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Samsung Exynos5250 SoC device nodes are listed in this file. - * Exynos5250 based board files can include this file and provide - * values for board specfic bindings. - * - * Note: This file does not include device nodes for all the controllers in - * Exynos5250 SoC. As device tree coverage for Exynos5250 increases, - * additional nodes can be added to this file. - */ - -#include -#include "exynos5.dtsi" -#include "exynos4-cpu-thermal.dtsi" -#include - -/ { - compatible = "samsung,exynos5250", "samsung,exynos5"; - - aliases { - spi0 = &spi_0; - spi1 = &spi_1; - spi2 = &spi_2; - gsc0 = &gsc_0; - gsc1 = &gsc_1; - gsc2 = &gsc_2; - gsc3 = &gsc_3; - mshc0 = &mmc_0; - mshc1 = &mmc_1; - mshc2 = &mmc_2; - mshc3 = &mmc_3; - i2c4 = &i2c_4; - i2c5 = &i2c_5; - i2c6 = &i2c_6; - i2c7 = &i2c_7; - i2c8 = &i2c_8; - i2c9 = &i2c_9; - pinctrl0 = &pinctrl_0; - pinctrl1 = &pinctrl_1; - pinctrl2 = &pinctrl_2; - pinctrl3 = &pinctrl_3; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0>; - clocks = <&clock CLK_ARM_CLK>; - clock-names = "cpu"; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - }; - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <1>; - clocks = <&clock CLK_ARM_CLK>; - clock-names = "cpu"; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - }; - }; - - cpu0_opp_table: opp_table0 { - compatible = "operating-points-v2"; - opp-shared; - - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - opp-microvolt = <925000>; - clock-latency-ns = <140000>; - }; - opp-300000000 { - opp-hz = /bits/ 64 <300000000>; - opp-microvolt = <937500>; - clock-latency-ns = <140000>; - }; - opp-400000000 { - opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <950000>; - clock-latency-ns = <140000>; - }; - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <975000>; - clock-latency-ns = <140000>; - }; - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <1000000>; - clock-latency-ns = <140000>; - }; - opp-700000000 { - opp-hz = /bits/ 64 <700000000>; - opp-microvolt = <1012500>; - clock-latency-ns = <140000>; - }; - opp-800000000 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <1025000>; - clock-latency-ns = <140000>; - }; - opp-900000000 { - opp-hz = /bits/ 64 <900000000>; - opp-microvolt = <1050000>; - clock-latency-ns = <140000>; - }; - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <1075000>; - clock-latency-ns = <140000>; - opp-suspend; - }; - opp-1100000000 { - opp-hz = /bits/ 64 <1100000000>; - opp-microvolt = <1100000>; - clock-latency-ns = <140000>; - }; - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <1125000>; - clock-latency-ns = <140000>; - }; - opp-1300000000 { - opp-hz = /bits/ 64 <1300000000>; - opp-microvolt = <1150000>; - clock-latency-ns = <140000>; - }; - opp-1400000000 { - opp-hz = /bits/ 64 <1400000000>; - opp-microvolt = <1200000>; - clock-latency-ns = <140000>; - }; - opp-1500000000 { - opp-hz = /bits/ 64 <1500000000>; - opp-microvolt = <1225000>; - clock-latency-ns = <140000>; - }; - opp-1600000000 { - opp-hz = /bits/ 64 <1600000000>; - opp-microvolt = <1250000>; - clock-latency-ns = <140000>; - }; - opp-1700000000 { - opp-hz = /bits/ 64 <1700000000>; - opp-microvolt = <1300000>; - clock-latency-ns = <140000>; - }; - }; - - pmu { - compatible = "arm,cortex-a15-pmu"; - interrupt-parent = <&combiner>; - interrupts = <1 2>, <22 4>; - }; - - soc: soc { - sram@2020000 { - compatible = "mmio-sram"; - reg = <0x02020000 0x30000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x02020000 0x30000>; - - smp-sram@0 { - compatible = "samsung,exynos4210-sysram"; - reg = <0x0 0x1000>; - }; - - smp-sram@2f000 { - compatible = "samsung,exynos4210-sysram-ns"; - reg = <0x2f000 0x1000>; - }; - }; - - pd_gsc: power-domain@10044000 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10044000 0x20>; - #power-domain-cells = <0>; - label = "GSC"; - }; - - pd_mfc: power-domain@10044040 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10044040 0x20>; - #power-domain-cells = <0>; - label = "MFC"; - }; - - pd_g3d: power-domain@10044060 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10044060 0x20>; - #power-domain-cells = <0>; - label = "G3D"; - }; - - pd_disp1: power-domain@100440a0 { - compatible = "samsung,exynos4210-pd"; - reg = <0x100440A0 0x20>; - #power-domain-cells = <0>; - label = "DISP1"; - }; - - pd_mau: power-domain@100440c0 { - compatible = "samsung,exynos4210-pd"; - reg = <0x100440C0 0x20>; - #power-domain-cells = <0>; - label = "MAU"; - }; - - clock: clock-controller@10010000 { - compatible = "samsung,exynos5250-clock"; - reg = <0x10010000 0x30000>; - #clock-cells = <1>; - }; - - clock_audss: audss-clock-controller@3810000 { - compatible = "samsung,exynos5250-audss-clock"; - reg = <0x03810000 0x0C>; - #clock-cells = <1>; - clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>, - <&clock CLK_SCLK_AUDIO0>, <&clock CLK_DIV_PCM0>; - clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in"; - power-domains = <&pd_mau>; - }; - - timer@101c0000 { - compatible = "samsung,exynos4210-mct"; - reg = <0x101C0000 0x800>; - clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; - clock-names = "fin_pll", "mct"; - interrupts-extended = <&combiner 23 3>, - <&combiner 23 4>, - <&combiner 25 2>, - <&combiner 25 3>, - <&gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; - }; - - pinctrl_0: pinctrl@11400000 { - compatible = "samsung,exynos5250-pinctrl"; - reg = <0x11400000 0x1000>; - interrupts = ; - - wakup_eint: wakeup-interrupt-controller { - compatible = "samsung,exynos4210-wakeup-eint"; - interrupt-parent = <&gic>; - interrupts = ; - }; - }; - - pinctrl_1: pinctrl@13400000 { - compatible = "samsung,exynos5250-pinctrl"; - reg = <0x13400000 0x1000>; - interrupts = ; - }; - - pinctrl_2: pinctrl@10d10000 { - compatible = "samsung,exynos5250-pinctrl"; - reg = <0x10d10000 0x1000>; - interrupts = ; - }; - - pinctrl_3: pinctrl@3860000 { - compatible = "samsung,exynos5250-pinctrl"; - reg = <0x03860000 0x1000>; - interrupts = ; - power-domains = <&pd_mau>; - }; - - pmu_system_controller: system-controller@10040000 { - compatible = "samsung,exynos5250-pmu", "syscon"; - reg = <0x10040000 0x5000>; - clock-names = "clkout16"; - clocks = <&clock CLK_FIN_PLL>; - #clock-cells = <1>; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - }; - - watchdog@101d0000 { - compatible = "samsung,exynos5250-wdt"; - reg = <0x101D0000 0x100>; - interrupts = ; - clocks = <&clock CLK_WDT>; - clock-names = "watchdog"; - samsung,syscon-phandle = <&pmu_system_controller>; - }; - - mfc: codec@11000000 { - compatible = "samsung,mfc-v6"; - reg = <0x11000000 0x10000>; - interrupts = ; - power-domains = <&pd_mfc>; - clocks = <&clock CLK_MFC>; - clock-names = "mfc"; - iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>; - iommu-names = "left", "right"; - }; - - rotator: rotator@11c00000 { - compatible = "samsung,exynos5250-rotator"; - reg = <0x11C00000 0x64>; - interrupts = ; - clocks = <&clock CLK_ROTATOR>; - clock-names = "rotator"; - iommus = <&sysmmu_rotator>; - }; - - mali: gpu@11800000 { - compatible = "samsung,exynos5250-mali", "arm,mali-t604"; - reg = <0x11800000 0x5000>; - interrupts = , - , - ; - interrupt-names = "job", "mmu", "gpu"; - clocks = <&clock CLK_G3D>; - clock-names = "core"; - operating-points-v2 = <&gpu_opp_table>; - power-domains = <&pd_g3d>; - status = "disabled"; - - gpu_opp_table: gpu-opp-table { - compatible = "operating-points-v2"; - - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - opp-microvolt = <925000>; - }; - opp-160000000 { - opp-hz = /bits/ 64 <160000000>; - opp-microvolt = <925000>; - }; - opp-266000000 { - opp-hz = /bits/ 64 <266000000>; - opp-microvolt = <1025000>; - }; - opp-350000000 { - opp-hz = /bits/ 64 <350000000>; - opp-microvolt = <1075000>; - }; - opp-400000000 { - opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <1125000>; - }; - opp-450000000 { - opp-hz = /bits/ 64 <450000000>; - opp-microvolt = <1150000>; - }; - opp-533000000 { - opp-hz = /bits/ 64 <533000000>; - opp-microvolt = <1250000>; - }; - }; - }; - - tmu: tmu@10060000 { - compatible = "samsung,exynos5250-tmu"; - reg = <0x10060000 0x100>; - interrupts = ; - clocks = <&clock CLK_TMU>; - clock-names = "tmu_apbif"; - #thermal-sensor-cells = <0>; - }; - - sata: sata@122f0000 { - compatible = "snps,dwc-ahci"; - samsung,sata-freq = <66>; - reg = <0x122F0000 0x1ff>; - interrupts = ; - clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>; - clock-names = "sata", "sclk_sata"; - phys = <&sata_phy>; - phy-names = "sata-phy"; - ports-implemented = <0x1>; - status = "disabled"; - }; - - sata_phy: sata-phy@12170000 { - compatible = "samsung,exynos5250-sata-phy"; - reg = <0x12170000 0x1ff>; - clocks = <&clock CLK_SATA_PHYCTRL>; - clock-names = "sata_phyctrl"; - #phy-cells = <0>; - samsung,syscon-phandle = <&pmu_system_controller>; - status = "disabled"; - }; - - /* i2c_0-3 are defined in exynos5.dtsi */ - i2c_4: i2c@12ca0000 { - compatible = "samsung,s3c2440-i2c"; - reg = <0x12CA0000 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clock CLK_I2C4>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_bus>; - status = "disabled"; - }; - - i2c_5: i2c@12cb0000 { - compatible = "samsung,s3c2440-i2c"; - reg = <0x12CB0000 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clock CLK_I2C5>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c5_bus>; - status = "disabled"; - }; - - i2c_6: i2c@12cc0000 { - compatible = "samsung,s3c2440-i2c"; - reg = <0x12CC0000 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clock CLK_I2C6>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c6_bus>; - status = "disabled"; - }; - - i2c_7: i2c@12cd0000 { - compatible = "samsung,s3c2440-i2c"; - reg = <0x12CD0000 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clock CLK_I2C7>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c7_bus>; - status = "disabled"; - }; - - i2c_8: i2c@12ce0000 { - compatible = "samsung,s3c2440-hdmiphy-i2c"; - reg = <0x12CE0000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clock CLK_I2C_HDMI>; - clock-names = "i2c"; - status = "disabled"; - - hdmiphy: hdmiphy@38 { - compatible = "samsung,exynos4212-hdmiphy"; - reg = <0x38>; - }; - }; - - i2c_9: i2c@121d0000 { - compatible = "samsung,exynos5-sata-phy-i2c"; - reg = <0x121D0000 0x100>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clock CLK_SATA_PHYI2C>; - clock-names = "i2c"; - status = "disabled"; - }; - - spi_0: spi@12d20000 { - compatible = "samsung,exynos4210-spi"; - status = "disabled"; - reg = <0x12d20000 0x100>; - interrupts = ; - dmas = <&pdma0 5 - &pdma0 4>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>; - clock-names = "spi", "spi_busclk0"; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_bus>; - }; - - spi_1: spi@12d30000 { - compatible = "samsung,exynos4210-spi"; - status = "disabled"; - reg = <0x12d30000 0x100>; - interrupts = ; - dmas = <&pdma1 5 - &pdma1 4>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>; - clock-names = "spi", "spi_busclk0"; - pinctrl-names = "default"; - pinctrl-0 = <&spi1_bus>; - }; - - spi_2: spi@12d40000 { - compatible = "samsung,exynos4210-spi"; - status = "disabled"; - reg = <0x12d40000 0x100>; - interrupts = ; - dmas = <&pdma0 7 - &pdma0 6>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>; - clock-names = "spi", "spi_busclk0"; - pinctrl-names = "default"; - pinctrl-0 = <&spi2_bus>; - }; - - mmc_0: mmc@12200000 { - compatible = "samsung,exynos5250-dw-mshc"; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x12200000 0x1000>; - clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>; - clock-names = "biu", "ciu"; - fifo-depth = <0x80>; - status = "disabled"; - }; - - mmc_1: mmc@12210000 { - compatible = "samsung,exynos5250-dw-mshc"; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x12210000 0x1000>; - clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>; - clock-names = "biu", "ciu"; - fifo-depth = <0x80>; - status = "disabled"; - }; - - mmc_2: mmc@12220000 { - compatible = "samsung,exynos5250-dw-mshc"; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x12220000 0x1000>; - clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>; - clock-names = "biu", "ciu"; - fifo-depth = <0x80>; - status = "disabled"; - }; - - mmc_3: mmc@12230000 { - compatible = "samsung,exynos5250-dw-mshc"; - reg = <0x12230000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>; - clock-names = "biu", "ciu"; - fifo-depth = <0x80>; - status = "disabled"; - }; - - i2s0: i2s@3830000 { - compatible = "samsung,s5pv210-i2s"; - status = "disabled"; - reg = <0x03830000 0x100>; - dmas = <&pdma0 10>, - <&pdma0 9>, - <&pdma0 8>; - dma-names = "tx", "rx", "tx-sec"; - clocks = <&clock_audss EXYNOS_I2S_BUS>, - <&clock_audss EXYNOS_I2S_BUS>, - <&clock_audss EXYNOS_SCLK_I2S>; - clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; - samsung,idma-addr = <0x03000000>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_bus>; - power-domains = <&pd_mau>; - #clock-cells = <1>; - #sound-dai-cells = <1>; - }; - - i2s1: i2s@12d60000 { - compatible = "samsung,s3c6410-i2s"; - status = "disabled"; - reg = <0x12D60000 0x100>; - dmas = <&pdma1 12>, - <&pdma1 11>; - dma-names = "tx", "rx"; - clocks = <&clock CLK_I2S1>, <&clock CLK_DIV_I2S1>; - clock-names = "iis", "i2s_opclk0"; - pinctrl-names = "default"; - pinctrl-0 = <&i2s1_bus>; - power-domains = <&pd_mau>; - #sound-dai-cells = <1>; - }; - - i2s2: i2s@12d70000 { - compatible = "samsung,s3c6410-i2s"; - status = "disabled"; - reg = <0x12D70000 0x100>; - dmas = <&pdma0 12>, - <&pdma0 11>; - dma-names = "tx", "rx"; - clocks = <&clock CLK_I2S2>, <&clock CLK_DIV_I2S2>; - clock-names = "iis", "i2s_opclk0"; - pinctrl-names = "default"; - pinctrl-0 = <&i2s2_bus>; - power-domains = <&pd_mau>; - #sound-dai-cells = <1>; - }; - - usb_dwc3 { - compatible = "samsung,exynos5250-dwusb3"; - clocks = <&clock CLK_USB3>; - clock-names = "usbdrd30"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - usbdrd_dwc3: dwc3@12000000 { - compatible = "synopsys,dwc3"; - reg = <0x12000000 0x10000>; - interrupts = ; - phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>; - phy-names = "usb2-phy", "usb3-phy"; - }; - }; - - usbdrd_phy: phy@12100000 { - compatible = "samsung,exynos5250-usbdrd-phy"; - reg = <0x12100000 0x100>; - clocks = <&clock CLK_USB3>, <&clock CLK_FIN_PLL>; - clock-names = "phy", "ref"; - samsung,pmu-syscon = <&pmu_system_controller>; - #phy-cells = <1>; - }; - - ehci: usb@12110000 { - compatible = "samsung,exynos4210-ehci"; - reg = <0x12110000 0x100>; - interrupts = ; - - clocks = <&clock CLK_USB2>; - clock-names = "usbhost"; - phys = <&usb2_phy_gen 1>; - phy-names = "host"; - }; - - ohci: usb@12120000 { - compatible = "samsung,exynos4210-ohci"; - reg = <0x12120000 0x100>; - interrupts = ; - - clocks = <&clock CLK_USB2>; - clock-names = "usbhost"; - phys = <&usb2_phy_gen 1>; - phy-names = "host"; - }; - - usb2_phy_gen: phy@12130000 { - compatible = "samsung,exynos5250-usb2-phy"; - reg = <0x12130000 0x100>; - clocks = <&clock CLK_USB2>, <&clock CLK_FIN_PLL>; - clock-names = "phy", "ref"; - #phy-cells = <1>; - samsung,sysreg-phandle = <&sysreg_system_controller>; - samsung,pmureg-phandle = <&pmu_system_controller>; - }; - - amba { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&gic>; - ranges; - - pdma0: pdma@121a0000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x121A0000 0x1000>; - interrupts = ; - clocks = <&clock CLK_PDMA0>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; - }; - - pdma1: pdma@121b0000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x121B0000 0x1000>; - interrupts = ; - clocks = <&clock CLK_PDMA1>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; - }; - - mdma0: mdma@10800000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x10800000 0x1000>; - interrupts = ; - clocks = <&clock CLK_MDMA0>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <1>; - }; - - mdma1: mdma@11c10000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x11C10000 0x1000>; - interrupts = ; - clocks = <&clock CLK_MDMA1>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <1>; - }; - }; - - gsc_0: gsc@13e00000 { - compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc"; - reg = <0x13e00000 0x1000>; - interrupts = ; - power-domains = <&pd_gsc>; - clocks = <&clock CLK_GSCL0>; - clock-names = "gscl"; - iommus = <&sysmmu_gsc0>; - }; - - gsc_1: gsc@13e10000 { - compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc"; - reg = <0x13e10000 0x1000>; - interrupts = ; - power-domains = <&pd_gsc>; - clocks = <&clock CLK_GSCL1>; - clock-names = "gscl"; - iommus = <&sysmmu_gsc1>; - }; - - gsc_2: gsc@13e20000 { - compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc"; - reg = <0x13e20000 0x1000>; - interrupts = ; - power-domains = <&pd_gsc>; - clocks = <&clock CLK_GSCL2>; - clock-names = "gscl"; - iommus = <&sysmmu_gsc2>; - }; - - gsc_3: gsc@13e30000 { - compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc"; - reg = <0x13e30000 0x1000>; - interrupts = ; - power-domains = <&pd_gsc>; - clocks = <&clock CLK_GSCL3>; - clock-names = "gscl"; - iommus = <&sysmmu_gsc3>; - }; - - hdmi: hdmi@14530000 { - compatible = "samsung,exynos4212-hdmi"; - reg = <0x14530000 0x70000>; - power-domains = <&pd_disp1>; - interrupts = ; - clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>, - <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>, - <&clock CLK_MOUT_HDMI>; - clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", - "sclk_hdmiphy", "mout_hdmi"; - samsung,syscon-phandle = <&pmu_system_controller>; - phy = <&hdmiphy>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - hdmicec: cec@101b0000 { - compatible = "samsung,s5p-cec"; - reg = <0x101B0000 0x200>; - interrupts = ; - clocks = <&clock CLK_HDMI_CEC>; - clock-names = "hdmicec"; - samsung,syscon-phandle = <&pmu_system_controller>; - hdmi-phandle = <&hdmi>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_cec>; - status = "disabled"; - }; - - mixer: mixer@14450000 { - compatible = "samsung,exynos5250-mixer"; - reg = <0x14450000 0x10000>; - power-domains = <&pd_disp1>; - interrupts = ; - clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>, - <&clock CLK_SCLK_HDMI>; - clock-names = "mixer", "hdmi", "sclk_hdmi"; - iommus = <&sysmmu_tv>; - status = "disabled"; - }; - - dp_phy: video-phy { - compatible = "samsung,exynos5250-dp-video-phy"; - samsung,pmu-syscon = <&pmu_system_controller>; - #phy-cells = <0>; - }; - - mipi_phy: video-phy@10040710 { - compatible = "samsung,s5pv210-mipi-video-phy"; - reg = <0x10040710 0x100>; - #phy-cells = <1>; - syscon = <&pmu_system_controller>; - }; - - dsi_0: dsi@14500000 { - compatible = "samsung,exynos4210-mipi-dsi"; - reg = <0x14500000 0x10000>; - interrupts = ; - samsung,power-domain = <&pd_disp1>; - phys = <&mipi_phy 3>; - phy-names = "dsim"; - clocks = <&clock CLK_DSIM0>, <&clock CLK_SCLK_MIPI1>; - clock-names = "bus_clk", "sclk_mipi"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - adc: adc@12d10000 { - compatible = "samsung,exynos-adc-v1"; - reg = <0x12D10000 0x100>; - interrupts = ; - clocks = <&clock CLK_ADC>; - clock-names = "adc"; - #io-channel-cells = <1>; - io-channel-ranges; - samsung,syscon-phandle = <&pmu_system_controller>; - status = "disabled"; - }; - - sysmmu_g2d: sysmmu@10a60000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x10A60000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <24 5>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_2D>, <&clock CLK_G2D>; - #iommu-cells = <0>; - }; - - sysmmu_mfc_r: sysmmu@11200000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x11200000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <6 2>; - power-domains = <&pd_mfc>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>; - #iommu-cells = <0>; - }; - - sysmmu_mfc_l: sysmmu@11210000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x11210000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <8 5>; - power-domains = <&pd_mfc>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>; - #iommu-cells = <0>; - }; - - sysmmu_rotator: sysmmu@11d40000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x11D40000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <4 0>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>; - #iommu-cells = <0>; - }; - - sysmmu_jpeg: sysmmu@11f20000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x11F20000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <4 2>; - power-domains = <&pd_gsc>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>; - #iommu-cells = <0>; - }; - - sysmmu_fimc_isp: sysmmu@13260000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x13260000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <10 6>; - clock-names = "sysmmu"; - clocks = <&clock CLK_SMMU_FIMC_ISP>; - #iommu-cells = <0>; - }; - - sysmmu_fimc_drc: sysmmu@13270000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x13270000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <11 6>; - clock-names = "sysmmu"; - clocks = <&clock CLK_SMMU_FIMC_DRC>; - #iommu-cells = <0>; - }; - - sysmmu_fimc_fd: sysmmu@132a0000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x132A0000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <5 0>; - clock-names = "sysmmu"; - clocks = <&clock CLK_SMMU_FIMC_FD>; - #iommu-cells = <0>; - }; - - sysmmu_fimc_scc: sysmmu@13280000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x13280000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <5 2>; - clock-names = "sysmmu"; - clocks = <&clock CLK_SMMU_FIMC_SCC>; - #iommu-cells = <0>; - }; - - sysmmu_fimc_scp: sysmmu@13290000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x13290000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <3 6>; - clock-names = "sysmmu"; - clocks = <&clock CLK_SMMU_FIMC_SCP>; - #iommu-cells = <0>; - }; - - sysmmu_fimc_mcuctl: sysmmu@132b0000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x132B0000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <5 4>; - clock-names = "sysmmu"; - clocks = <&clock CLK_SMMU_FIMC_MCU>; - #iommu-cells = <0>; - }; - - sysmmu_fimc_odc: sysmmu@132c0000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x132C0000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <11 0>; - clock-names = "sysmmu"; - clocks = <&clock CLK_SMMU_FIMC_ODC>; - #iommu-cells = <0>; - }; - - sysmmu_fimc_dis0: sysmmu@132d0000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x132D0000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <10 4>; - clock-names = "sysmmu"; - clocks = <&clock CLK_SMMU_FIMC_DIS0>; - #iommu-cells = <0>; - }; - - sysmmu_fimc_dis1: sysmmu@132e0000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x132E0000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <9 4>; - clock-names = "sysmmu"; - clocks = <&clock CLK_SMMU_FIMC_DIS1>; - #iommu-cells = <0>; - }; - - sysmmu_fimc_3dnr: sysmmu@132f0000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x132F0000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <5 6>; - clock-names = "sysmmu"; - clocks = <&clock CLK_SMMU_FIMC_3DNR>; - #iommu-cells = <0>; - }; - - sysmmu_fimc_lite0: sysmmu@13c40000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x13C40000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <3 4>; - power-domains = <&pd_gsc>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_FIMC_LITE0>, <&clock CLK_CAMIF_TOP>; - #iommu-cells = <0>; - }; - - sysmmu_fimc_lite1: sysmmu@13c50000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x13C50000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <24 1>; - power-domains = <&pd_gsc>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_FIMC_LITE1>, <&clock CLK_CAMIF_TOP>; - #iommu-cells = <0>; - }; - - sysmmu_gsc0: sysmmu@13e80000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x13E80000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <2 0>; - power-domains = <&pd_gsc>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>; - #iommu-cells = <0>; - }; - - sysmmu_gsc1: sysmmu@13e90000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x13E90000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <2 2>; - power-domains = <&pd_gsc>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>; - #iommu-cells = <0>; - }; - - sysmmu_gsc2: sysmmu@13ea0000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x13EA0000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <2 4>; - power-domains = <&pd_gsc>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_GSCL2>, <&clock CLK_GSCL2>; - #iommu-cells = <0>; - }; - - sysmmu_gsc3: sysmmu@13eb0000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x13EB0000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <2 6>; - power-domains = <&pd_gsc>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_GSCL3>, <&clock CLK_GSCL3>; - #iommu-cells = <0>; - }; - - sysmmu_fimd1: sysmmu@14640000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x14640000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <3 2>; - power-domains = <&pd_disp1>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>; - #iommu-cells = <0>; - }; - - sysmmu_tv: sysmmu@14650000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x14650000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <7 4>; - power-domains = <&pd_disp1>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>; - #iommu-cells = <0>; - }; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tmu 0>; - - cooling-maps { - map0 { - /* Corresponds to 800MHz at freq_table */ - cooling-device = <&cpu0 9 9>, <&cpu1 9 9>; - }; - map1 { - /* Corresponds to 200MHz at freq_table */ - cooling-device = <&cpu0 15 15>, - <&cpu1 15 15>; - }; - }; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; - /* - * Unfortunately we need this since some versions - * of U-Boot on Exynos don't set the CNTFRQ register, - * so we need the value from DT. - */ - clock-frequency = <24000000>; - }; -}; - -&dp { - power-domains = <&pd_disp1>; - clocks = <&clock CLK_DP>; - clock-names = "dp"; - phys = <&dp_phy>; - phy-names = "dp"; -}; - -&fimd { - power-domains = <&pd_disp1>; - clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>; - clock-names = "sclk_fimd", "fimd"; - iommus = <&sysmmu_fimd1>; -}; - -&g2d { - iommus = <&sysmmu_g2d>; - clocks = <&clock CLK_G2D>; - clock-names = "fimg2d"; - status = "okay"; -}; - -&i2c_0 { - clocks = <&clock CLK_I2C0>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_bus>; -}; - -&i2c_1 { - clocks = <&clock CLK_I2C1>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_bus>; -}; - -&i2c_2 { - clocks = <&clock CLK_I2C2>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_bus>; -}; - -&i2c_3 { - clocks = <&clock CLK_I2C3>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_bus>; -}; - -&prng { - clocks = <&clock CLK_SSS>; - clock-names = "secss"; -}; - -&pwm { - clocks = <&clock CLK_PWM>; - clock-names = "timers"; -}; - -&rtc { - clocks = <&clock CLK_RTC>; - clock-names = "rtc"; - interrupt-parent = <&pmu_system_controller>; - status = "disabled"; -}; - -&serial_0 { - clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; - clock-names = "uart", "clk_uart_baud0"; - dmas = <&pdma0 13>, <&pdma0 14>; - dma-names = "rx", "tx"; -}; - -&serial_1 { - clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>; - clock-names = "uart", "clk_uart_baud0"; - dmas = <&pdma1 15>, <&pdma1 16>; - dma-names = "rx", "tx"; -}; - -&serial_2 { - clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; - clock-names = "uart", "clk_uart_baud0"; - dmas = <&pdma0 15>, <&pdma0 16>; - dma-names = "rx", "tx"; -}; - -&serial_3 { - clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>; - clock-names = "uart", "clk_uart_baud0"; - dmas = <&pdma1 17>, <&pdma1 18>; - dma-names = "rx", "tx"; -}; - -&sss { - clocks = <&clock CLK_SSS>; - clock-names = "secss"; -}; - -&trng { - clocks = <&clock CLK_SSS>; - clock-names = "secss"; -}; - -#include "exynos5250-pinctrl.dtsi" -#include "exynos-syscon-restart.dtsi" diff --git a/sys/gnu/dts/arm/exynos5260-pinctrl.dtsi b/sys/gnu/dts/arm/exynos5260-pinctrl.dtsi deleted file mode 100644 index 17e2f3e0d71..00000000000 --- a/sys/gnu/dts/arm/exynos5260-pinctrl.dtsi +++ /dev/null @@ -1,585 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's Exynos5260 SoC pin-mux and pin-config device tree source - * - * Copyright (c) 2013 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Samsung's Exynos5260 SoC pin-mux and pin-config options are listed as device - * tree nodes are listed in this file. - */ - -#include - -&pinctrl_0 { - gpa0: gpa0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpa1: gpa1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpa2: gpa2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpb0: gpb0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpb1: gpb1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpb2: gpb2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpb3: gpb3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpb4: gpb4 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpb5: gpb5 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpd0: gpd0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpd1: gpd1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpd2: gpd2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpe0: gpe0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpe1: gpe1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf0: gpf0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf1: gpf1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpk0: gpk0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpx0: gpx0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - interrupts = , - , - , - , - , - , - , - ; - #interrupt-cells = <2>; - }; - - gpx1: gpx1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - interrupts = , - , - , - , - , - , - , - ; - #interrupt-cells = <2>; - }; - - gpx2: gpx2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpx3: gpx3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - uart0_data: uart0-data { - samsung,pins = "gpa0-0", "gpa0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart0_fctl: uart0-fctl { - samsung,pins = "gpa0-2", "gpa0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart1_data: uart1-data { - samsung,pins = "gpa1-0", "gpa1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart1_fctl: uart1-fctl { - samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart2_data: uart2-data { - samsung,pins = "gpa1-4", "gpa1-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spi0_bus: spi0-bus { - samsung,pins = "gpa2-0", "gpa2-2", "gpa2-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spi1_bus: spi1-bus { - samsung,pins = "gpa2-4", "gpa2-6", "gpa2-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - usb3_vbus0_en: usb3-vbus0-en { - samsung,pins = "gpa2-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2s1_bus: i2s1-bus { - samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3", - "gpb0-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pcm1_bus: pcm1-bus { - samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3", - "gpb0-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spdif1_bus: spdif1-bus { - samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spi2_bus: spi2-bus { - samsung,pins = "gpb1-0", "gpb1-2", "gpb1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c0_hs_bus: i2c0-hs-bus { - samsung,pins = "gpb3-0", "gpb3-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c1_hs_bus: i2c1-hs-bus { - samsung,pins = "gpb3-2", "gpb3-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c2_hs_bus: i2c2-hs-bus { - samsung,pins = "gpb3-4", "gpb3-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c3_hs_bus: i2c3-hs-bus { - samsung,pins = "gpb3-6", "gpb3-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c4_bus: i2c4-bus { - samsung,pins = "gpb4-0", "gpb4-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c5_bus: i2c5-bus { - samsung,pins = "gpb4-2", "gpb4-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c6_bus: i2c6-bus { - samsung,pins = "gpb4-4", "gpb4-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c7_bus: i2c7-bus { - samsung,pins = "gpb4-6", "gpb4-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c8_bus: i2c8-bus { - samsung,pins = "gpb5-0", "gpb5-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c9_bus: i2c9-bus { - samsung,pins = "gpb5-2", "gpb5-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c10_bus: i2c10-bus { - samsung,pins = "gpb5-4", "gpb5-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c11_bus: i2c11-bus { - samsung,pins = "gpb5-6", "gpb5-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_gpio_a: cam-gpio-a { - samsung,pins = "gpe0-0", "gpe0-1", "gpe0-2", "gpe0-3", - "gpe0-4", "gpe0-5", "gpe0-6", "gpe0-7", - "gpe1-0", "gpe1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_gpio_b: cam-gpio-b { - samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3", - "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_i2c1_bus: cam-i2c1-bus { - samsung,pins = "gpf0-2", "gpf0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_i2c0_bus: cam-i2c0-bus { - samsung,pins = "gpf0-0", "gpf0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_spi0_bus: cam-spi0-bus { - samsung,pins = "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_spi1_bus: cam-spi1-bus { - samsung,pins = "gpf1-4", "gpf1-5", "gpf1-6", "gpf1-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pinctrl_1 { - gpc0: gpc0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc1: gpc1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc2: gpc2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc3: gpc3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc4: gpc4 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - sd0_clk: sd0-clk { - samsung,pins = "gpc0-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_cmd: sd0-cmd { - samsung,pins = "gpc0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus1: sd0-bus-width1 { - samsung,pins = "gpc0-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus4: sd0-bus-width4 { - samsung,pins = "gpc0-3", "gpc0-4", "gpc0-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus8: sd0-bus-width8 { - samsung,pins = "gpc3-0", "gpc3-1", "gpc3-2", "gpc3-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_rdqs: sd0-rdqs { - samsung,pins = "gpc0-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_clk: sd1-clk { - samsung,pins = "gpc1-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_cmd: sd1-cmd { - samsung,pins = "gpc1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_bus1: sd1-bus-width1 { - samsung,pins = "gpc1-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_bus4: sd1-bus-width4 { - samsung,pins = "gpc1-3", "gpc1-4", "gpc1-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_bus8: sd1-bus-width8 { - samsung,pins = "gpc4-0", "gpc4-1", "gpc4-2", "gpc4-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_clk: sd2-clk { - samsung,pins = "gpc2-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_cmd: sd2-cmd { - samsung,pins = "gpc2-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_cd: sd2-cd { - samsung,pins = "gpc2-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_bus1: sd2-bus-width1 { - samsung,pins = "gpc2-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_bus4: sd2-bus-width4 { - samsung,pins = "gpc2-4", "gpc2-5", "gpc2-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pinctrl_2 { - gpz0: gpz0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpz1: gpz1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; -}; diff --git a/sys/gnu/dts/arm/exynos5260-xyref5260.dts b/sys/gnu/dts/arm/exynos5260-xyref5260.dts deleted file mode 100644 index 0dc2ec16aa0..00000000000 --- a/sys/gnu/dts/arm/exynos5260-xyref5260.dts +++ /dev/null @@ -1,90 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung XYREF5260 board device tree source - * - * Copyright (c) 2013 Samsung Electronics Co., Ltd. - * http://www.samsung.com - */ - -/dts-v1/; -#include "exynos5260.dtsi" - -/ { - model = "Samsung XYREF5260 board based on Exynos5260"; - compatible = "samsung,xyref5260", "samsung,exynos5260", "samsung,exynos5"; - - memory@20000000 { - device_type = "memory"; - reg = <0x20000000 0x80000000>; - }; - - chosen { - stdout-path = "serial2:115200n8"; - }; - - fin_pll: xxti { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "fin_pll"; - #clock-cells = <0>; - }; - - xrtcxti: xrtcxti { - compatible = "fixed-clock"; - clock-frequency = <32768>; - clock-output-names = "xrtcxti"; - #clock-cells = <0>; - }; -}; - -&pinctrl_0 { - hdmi_hpd_irq: hdmi-hpd-irq { - samsung,pins = "gpx3-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&mmc_0 { - status = "okay"; - broken-cd; - cap-mmc-highspeed; - supports-hs200-mode; /* 200 MHz */ - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <0 4>; - samsung,dw-mshc-ddr-timing = <0 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd0_rdqs &sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>; - bus-width = <8>; -}; - -&mmc_2 { - status = "okay"; - cap-sd-highspeed; - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>; - bus-width = <4>; - disable-wp; -}; diff --git a/sys/gnu/dts/arm/exynos5260.dtsi b/sys/gnu/dts/arm/exynos5260.dtsi deleted file mode 100644 index 154df70128f..00000000000 --- a/sys/gnu/dts/arm/exynos5260.dtsi +++ /dev/null @@ -1,401 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung Exynos5260 SoC device tree source - * - * Copyright (c) 2013 Samsung Electronics Co., Ltd. - * http://www.samsung.com - */ - -#include -#include -#include - -/ { - compatible = "samsung,exynos5260", "samsung,exynos5"; - interrupt-parent = <&gic>; - #address-cells = <1>; - #size-cells = <1>; - - aliases { - i2c0 = &hsi2c_0; - i2c1 = &hsi2c_1; - i2c2 = &hsi2c_2; - i2c3 = &hsi2c_3; - pinctrl0 = &pinctrl_0; - pinctrl1 = &pinctrl_1; - pinctrl2 = &pinctrl_2; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x0>; - cci-control-port = <&cci_control1>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x1>; - cci-control-port = <&cci_control1>; - }; - - cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x100>; - cci-control-port = <&cci_control0>; - }; - - cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x101>; - cci-control-port = <&cci_control0>; - }; - - cpu@102 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x102>; - cci-control-port = <&cci_control0>; - }; - - cpu@103 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x103>; - cci-control-port = <&cci_control0>; - }; - }; - - soc: soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - clock_top: clock-controller@10010000 { - compatible = "samsung,exynos5260-clock-top"; - reg = <0x10010000 0x10000>; - #clock-cells = <1>; - }; - - clock_peri: clock-controller@10200000 { - compatible = "samsung,exynos5260-clock-peri"; - reg = <0x10200000 0x10000>; - #clock-cells = <1>; - }; - - clock_egl: clock-controller@10600000 { - compatible = "samsung,exynos5260-clock-egl"; - reg = <0x10600000 0x10000>; - #clock-cells = <1>; - }; - - clock_kfc: clock-controller@10700000 { - compatible = "samsung,exynos5260-clock-kfc"; - reg = <0x10700000 0x10000>; - #clock-cells = <1>; - }; - - clock_g2d: clock-controller@10a00000 { - compatible = "samsung,exynos5260-clock-g2d"; - reg = <0x10A00000 0x10000>; - #clock-cells = <1>; - }; - - clock_mif: clock-controller@10ce0000 { - compatible = "samsung,exynos5260-clock-mif"; - reg = <0x10CE0000 0x10000>; - #clock-cells = <1>; - }; - - clock_mfc: clock-controller@11090000 { - compatible = "samsung,exynos5260-clock-mfc"; - reg = <0x11090000 0x10000>; - #clock-cells = <1>; - }; - - clock_g3d: clock-controller@11830000 { - compatible = "samsung,exynos5260-clock-g3d"; - reg = <0x11830000 0x10000>; - #clock-cells = <1>; - }; - - clock_fsys: clock-controller@122e0000 { - compatible = "samsung,exynos5260-clock-fsys"; - reg = <0x122E0000 0x10000>; - #clock-cells = <1>; - }; - - clock_aud: clock-controller@128c0000 { - compatible = "samsung,exynos5260-clock-aud"; - reg = <0x128C0000 0x10000>; - #clock-cells = <1>; - }; - - clock_isp: clock-controller@133c0000 { - compatible = "samsung,exynos5260-clock-isp"; - reg = <0x133C0000 0x10000>; - #clock-cells = <1>; - }; - - clock_gscl: clock-controller@13f00000 { - compatible = "samsung,exynos5260-clock-gscl"; - reg = <0x13F00000 0x10000>; - #clock-cells = <1>; - }; - - clock_disp: clock-controller@14550000 { - compatible = "samsung,exynos5260-clock-disp"; - reg = <0x14550000 0x10000>; - #clock-cells = <1>; - }; - - gic: interrupt-controller@10481000 { - compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - #size-cells = <0>; - interrupt-controller; - reg = <0x10481000 0x1000>, - <0x10482000 0x2000>, - <0x10484000 0x2000>, - <0x10486000 0x2000>; - interrupts = ; - }; - - chipid: chipid@10000000 { - compatible = "samsung,exynos4210-chipid"; - reg = <0x10000000 0x100>; - }; - - mct: timer@100b0000 { - compatible = "samsung,exynos4210-mct"; - reg = <0x100B0000 0x1000>; - clocks = <&fin_pll>, <&clock_peri PERI_CLK_MCT>; - clock-names = "fin_pll", "mct"; - interrupts = , - , - , - , - , - , - , - , - , - , - , - ; - }; - - cci: cci@10f00000 { - compatible = "arm,cci-400"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x10F00000 0x1000>; - ranges = <0x0 0x10F00000 0x6000>; - - cci_control0: slave-if@4000 { - compatible = "arm,cci-400-ctrl-if"; - interface-type = "ace"; - reg = <0x4000 0x1000>; - }; - - cci_control1: slave-if@5000 { - compatible = "arm,cci-400-ctrl-if"; - interface-type = "ace"; - reg = <0x5000 0x1000>; - }; - }; - - pinctrl_0: pinctrl@11600000 { - compatible = "samsung,exynos5260-pinctrl"; - reg = <0x11600000 0x1000>; - interrupts = ; - - wakeup-interrupt-controller { - compatible = "samsung,exynos4210-wakeup-eint"; - interrupt-parent = <&gic>; - interrupts = ; - }; - }; - - pinctrl_1: pinctrl@12290000 { - compatible = "samsung,exynos5260-pinctrl"; - reg = <0x12290000 0x1000>; - interrupts = ; - }; - - pinctrl_2: pinctrl@128b0000 { - compatible = "samsung,exynos5260-pinctrl"; - reg = <0x128B0000 0x1000>; - interrupts = ; - }; - - pmu_system_controller: system-controller@10d50000 { - compatible = "samsung,exynos5260-pmu", "syscon"; - reg = <0x10D50000 0x10000>; - }; - - uart0: serial@12c00000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x12C00000 0x100>; - interrupts = ; - clocks = <&clock_peri PERI_CLK_UART0>, <&clock_peri PERI_SCLK_UART0>; - clock-names = "uart", "clk_uart_baud0"; - status = "disabled"; - }; - - uart1: serial@12c10000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x12C10000 0x100>; - interrupts = ; - clocks = <&clock_peri PERI_CLK_UART1>, <&clock_peri PERI_SCLK_UART1>; - clock-names = "uart", "clk_uart_baud0"; - status = "disabled"; - }; - - uart2: serial@12c20000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x12C20000 0x100>; - interrupts = ; - clocks = <&clock_peri PERI_CLK_UART2>, <&clock_peri PERI_SCLK_UART2>; - clock-names = "uart", "clk_uart_baud0"; - status = "disabled"; - }; - - uart3: serial@12860000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x12860000 0x100>; - interrupts = ; - clocks = <&clock_aud AUD_CLK_AUD_UART>, <&clock_aud AUD_SCLK_AUD_UART>; - clock-names = "uart", "clk_uart_baud0"; - status = "disabled"; - }; - - mmc_0: mmc@12140000 { - compatible = "samsung,exynos5250-dw-mshc"; - reg = <0x12140000 0x2000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clock_fsys FSYS_CLK_MMC0>, <&clock_top TOP_SCLK_MMC0>; - clock-names = "biu", "ciu"; - assigned-clocks = - <&clock_top TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_A>, - <&clock_top TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_B>, - <&clock_top TOP_SCLK_MMC0>; - assigned-clock-parents = - <&clock_top TOP_MOUT_BUSTOP_PLL_USER>, - <&clock_top TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_A>; - assigned-clock-rates = <0>, <0>, <800000000>; - fifo-depth = <64>; - status = "disabled"; - }; - - mmc_1: mmc@12150000 { - compatible = "samsung,exynos5250-dw-mshc"; - reg = <0x12150000 0x2000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clock_fsys FSYS_CLK_MMC1>, <&clock_top TOP_SCLK_MMC1>; - clock-names = "biu", "ciu"; - assigned-clocks = - <&clock_top TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_A>, - <&clock_top TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_B>, - <&clock_top TOP_SCLK_MMC1>; - assigned-clock-parents = - <&clock_top TOP_MOUT_BUSTOP_PLL_USER>, - <&clock_top TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_A>; - assigned-clock-rates = <0>, <0>, <800000000>; - fifo-depth = <64>; - status = "disabled"; - }; - - mmc_2: mmc@12160000 { - compatible = "samsung,exynos5250-dw-mshc"; - reg = <0x12160000 0x2000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clock_fsys FSYS_CLK_MMC2>, <&clock_top TOP_SCLK_MMC2>; - clock-names = "biu", "ciu"; - assigned-clocks = - <&clock_top TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_A>, - <&clock_top TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_B>, - <&clock_top TOP_SCLK_MMC2>; - assigned-clock-parents = - <&clock_top TOP_MOUT_BUSTOP_PLL_USER>, - <&clock_top TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_A>; - assigned-clock-rates = <0>, <0>, <800000000>; - fifo-depth = <64>; - status = "disabled"; - }; - - hsi2c_0: hsi2c@12da0000 { - compatible = "samsung,exynos5260-hsi2c"; - reg = <0x12DA0000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_hs_bus>; - clocks = <&clock_peri PERI_CLK_HSIC0>; - clock-names = "hsi2c"; - status = "disabled"; - }; - - hsi2c_1: hsi2c@12db0000 { - compatible = "samsung,exynos5260-hsi2c"; - reg = <0x12DB0000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_hs_bus>; - clocks = <&clock_peri PERI_CLK_HSIC1>; - clock-names = "hsi2c"; - status = "disabled"; - }; - - hsi2c_2: hsi2c@12dc0000 { - compatible = "samsung,exynos5260-hsi2c"; - reg = <0x12DC0000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_hs_bus>; - clocks = <&clock_peri PERI_CLK_HSIC2>; - clock-names = "hsi2c"; - status = "disabled"; - }; - - hsi2c_3: hsi2c@12dd0000 { - compatible = "samsung,exynos5260-hsi2c"; - reg = <0x12DD0000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_hs_bus>; - clocks = <&clock_peri PERI_CLK_HSIC3>; - clock-names = "hsi2c"; - status = "disabled"; - }; - }; -}; - -#include "exynos5260-pinctrl.dtsi" diff --git a/sys/gnu/dts/arm/exynos5410-odroidxu.dts b/sys/gnu/dts/arm/exynos5410-odroidxu.dts deleted file mode 100644 index 4f9297ae076..00000000000 --- a/sys/gnu/dts/arm/exynos5410-odroidxu.dts +++ /dev/null @@ -1,655 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Hardkernel Odroid XU board device tree source - * - * Copyright (c) 2013 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * Copyright (c) 2016 Krzysztof Kozlowski - */ - -/dts-v1/; -#include "exynos5410.dtsi" -#include -#include -#include -#include -#include "exynos54xx-odroidxu-leds.dtsi" - -/ { - model = "Hardkernel Odroid XU"; - compatible = "hardkernel,odroid-xu", "samsung,exynos5410", "samsung,exynos5"; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x7ea00000>; - }; - - chosen { - stdout-path = "serial2:115200n8"; - }; - - emmc_pwrseq: pwrseq { - pinctrl-0 = <&emmc_nrst_pin>; - pinctrl-names = "default"; - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpd1 0 GPIO_ACTIVE_LOW>; - }; - - fan0: pwm-fan { - compatible = "pwm-fan"; - pwms = <&pwm 0 20972 0>; - #cooling-cells = <2>; - cooling-levels = <0 130 170 230>; - }; - - fin_pll: xxti { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "fin_pll"; - #clock-cells = <0>; - }; - - firmware@2073000 { - compatible = "samsung,secure-firmware"; - reg = <0x02073000 0x1000>; - }; - - sound: sound { - compatible = "simple-audio-card"; - - simple-audio-card,name = "Odroid-XU"; - simple-audio-card,widgets = - "Headphone", "Headphone Jack", - "Speakers", "Speakers"; - simple-audio-card,routing = - "Headphone Jack", "HPL", - "Headphone Jack", "HPR", - "Headphone Jack", "MICBIAS", - "IN1", "Headphone Jack", - "Speakers", "SPKL", - "Speakers", "SPKR"; - - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&link0_codec>; - simple-audio-card,frame-master = <&link0_codec>; - - simple-audio-card,cpu { - sound-dai = <&audi2s0 0>; - system-clock-frequency = <19200000>; - }; - - link0_codec: simple-audio-card,codec { - sound-dai = <&max98090>; - clocks = <&audi2s0 CLK_I2S_CDCLK>; - }; - }; -}; - -&adc { - vdd-supply = <&ldo10_reg>; - status = "okay"; -}; - -&audi2s0 { - status = "okay"; -}; - -&clock { - clocks = <&fin_pll>; - assigned-clocks = <&clock CLK_FOUT_EPLL>; - assigned-clock-rates = <192000000>; -}; - -&clock_audss { - assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>, - <&clock_audss EXYNOS_MOUT_I2S>, - <&clock_audss EXYNOS_DOUT_SRP>, - <&clock_audss EXYNOS_DOUT_AUD_BUS>; - - assigned-clock-parents = <&clock CLK_FOUT_EPLL>, - <&clock_audss EXYNOS_MOUT_AUDSS>; - - assigned-clock-rates = <0>, - <0>, - <96000000>, - <19200000>; -}; - -&cpu0_thermal { - thermal-sensors = <&tmu_cpu0 0>; - polling-delay-passive = <0>; - polling-delay = <0>; - - trips { - cpu_alert0: cpu-alert-0 { - temperature = <50000>; /* millicelsius */ - hysteresis = <5000>; /* millicelsius */ - type = "active"; - }; - cpu_alert1: cpu-alert-1 { - temperature = <60000>; /* millicelsius */ - hysteresis = <5000>; /* millicelsius */ - type = "active"; - }; - cpu_alert2: cpu-alert-2 { - temperature = <70000>; /* millicelsius */ - hysteresis = <5000>; /* millicelsius */ - type = "active"; - }; - cpu_crit0: cpu-crit-0 { - temperature = <120000>; /* millicelsius */ - hysteresis = <0>; /* millicelsius */ - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu_alert0>; - cooling-device = <&fan0 0 1>; - }; - map1 { - trip = <&cpu_alert1>; - cooling-device = <&fan0 1 2>; - }; - map2 { - trip = <&cpu_alert2>; - cooling-device = <&fan0 2 3>; - }; - }; -}; - -&hsi2c_4 { - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <400000>; - status = "okay"; - - usb3503: usb-hub@8 { - compatible = "smsc,usb3503"; - reg = <0x08>; - - intn-gpios = <&gpx0 7 GPIO_ACTIVE_HIGH>; - connect-gpios = <&gpx0 6 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpx1 4 GPIO_ACTIVE_LOW>; - initial-mode = <1>; - - clock-names = "refclk"; - clocks = <&pmu_system_controller 0>; - refclk-frequency = <24000000>; - }; - - max77802: pmic@9 { - compatible = "maxim,max77802"; - reg = <0x9>; - interrupt-parent = <&gpx0>; - interrupts = <4 IRQ_TYPE_NONE>; - pinctrl-names = "default"; - pinctrl-0 = <&max77802_irq>, <&pmic_dvs_1>, <&pmic_dvs_2>, - <&pmic_dvs_3>; - #clock-cells = <1>; - - inl1-supply = <&buck5_reg>; - inl2-supply = <&buck7_reg>; - inl3-supply = <&buck9_reg>; - inl4-supply = <&buck9_reg>; - inl5-supply = <&buck9_reg>; - inl6-supply = <&buck10_reg>; - inl7-supply = <&buck9_reg>; - /* inl9 supply is BOOST, not configured here */ - inl10-supply = <&buck7_reg>; - - regulators { - buck1_reg: BUCK1 { - regulator-name = "vdd_mif"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - }; - - buck2_reg: BUCK2 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - }; - - buck3_reg: BUCK3 { - regulator-name = "vdd_int"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-boot-on; - }; - - buck4_reg: BUCK4 { - regulator-name = "vdd_g3d"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-boot-on; - }; - - buck5_reg: BUCK5 { - regulator-name = "vdd_mem"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - }; - - buck6_reg: BUCK6 { - regulator-name = "vdd_kfc"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - }; - - buck7_reg: BUCK7 { - regulator-name = "buck7"; - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - }; - - buck8_reg: BUCK8 { - /* vdd_mmc0 */ - regulator-name = "vddf_2v85"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - regulator-always-on; - regulator-boot-on; - }; - - buck9_reg: BUCK9 { - regulator-name = "buck9"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - regulator-boot-on; - }; - - buck10_reg: BUCK10 { - regulator-name = "buck10"; - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo1_reg: LDO1 { - regulator-name = "vdd_alive"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo2_reg: LDO2 { - regulator-name = "vddq_m1_m2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - ldo3_reg: LDO3 { - regulator-name = "vddq_gpio"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo4_reg: LDO4 { - regulator-name = "vddq_mmc2"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3000000>; - /* Having it off prevents reboot */ - regulator-always-on; - }; - - ldo5_reg: LDO5 { - regulator-name = "vdd18_hsic"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo6_reg: LDO6 { - regulator-name = "vdd18_bpll"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo7_reg: LDO7 { - regulator-name = "vddq_lcd"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo8_reg: LDO8 { - regulator-name = "vdd10_hdmi"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo9_reg: LDO9 { - regulator-name = "ldo9"; - }; - - ldo10_reg: LDO10 { - regulator-name = "vdd18_mipi"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo11_reg: LDO11 { - regulator-name = "vddq_mmc01"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - /* - * Having it off prevents accessing MMC after - * reboot with error: - * MMC Device 1: Clock OFF has been failed. - */ - regulator-always-on; - }; - - ldo12_reg: LDO12 { - regulator-name = "vdd33_usb3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo13_reg: LDO13 { - regulator-name = "vddq_abbg0"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo14_reg: LDO14 { - regulator-name = "vddq_abbg1"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo15_reg: LDO15 { - regulator-name = "vdd10_usb3"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo16_reg: LDO16 { - regulator-name = "ldo16"; - }; - - ldo17_reg: LDO17 { - regulator-name = "cam_sensor_core"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - ldo18_reg: LDO18 { - regulator-name = "ldo18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo19_reg: LDO19 { - regulator-name = "ldo19"; - }; - - ldo20_reg: LDO20 { - regulator-name = "vdd_mmc0"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo21_reg: LDO21 { - /* vdd_mmc2 */ - regulator-name = "vddf_2v8"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - ldo22_reg: LDO22 { - regulator-name = "ldo22"; - }; - - ldo23_reg: LDO23 { - regulator-name = "dp_p3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo24_reg: LDO24 { - regulator-name = "cam_af"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo25_reg: LDO25 { - regulator-name = "eth_p3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo26_reg: LDO26 { - regulator-name = "usb30_extclk"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo27_reg: LDO27 { - regulator-name = "ldo27"; - }; - - ldo28_reg: LDO28 { - regulator-name = "ldo28"; - }; - - ldo29_reg: LDO29 { - regulator-name = "ldo29"; - }; - - ldo30_reg: LDO30 { - regulator-name = "vddq_e1_e2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - ldo31_reg: LDO31 { - regulator-name = "ldo31"; - }; - - /* On revisions with ti,ina231 this is sensor VS */ - ldo32_reg: LDO32 { - regulator-name = "vs_power_meter"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo33_reg: LDO33 { - regulator-name = "ldo33"; - }; - - ldo34_reg: LDO34 { - regulator-name = "ldo34"; - }; - - ldo35_reg: LDO35 { - regulator-name = "ldo35"; - }; - }; - }; -}; - -&i2c_1 { - status = "okay"; - max98090: max98090@10 { - compatible = "maxim,max98090"; - reg = <0x10>; - interrupt-parent = <&gpj3>; - interrupts = <0 IRQ_TYPE_NONE>; - clocks = <&audi2s0 CLK_I2S_CDCLK>; - clock-names = "mclk"; - #sound-dai-cells = <0>; - }; -}; - -&mmc_0 { - status = "okay"; - mmc-pwrseq = <&emmc_pwrseq>; - cd-gpios = <&gpc0 2 GPIO_ACTIVE_LOW>; - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <0 4>; - samsung,dw-mshc-ddr-timing = <0 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8 &sd0_cd>; - bus-width = <8>; - cap-mmc-highspeed; - mmc-hs200-1_8v; - vmmc-supply = <&ldo20_reg>; - vqmmc-supply = <&ldo11_reg>; -}; - -&mmc_2 { - status = "okay"; - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <0 4>; - samsung,dw-mshc-ddr-timing = <0 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4 &sd2_wp>; - bus-width = <4>; - cap-sd-highspeed; - vmmc-supply = <&ldo21_reg>; - vqmmc-supply = <&ldo4_reg>; -}; - -&pinctrl_0 { - emmc_nrst_pin: emmc-nrst { - samsung,pins = "gpd1-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_wp: sd2-wp { - samsung,pins = "gpm5-0"; - samsung,pin-function = ; - /* Pin is floating so be sure to disable write-protect */ - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pmic_dvs_3: pmic-dvs-3 { - samsung,pins = "gpx0-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pmic_dvs_2: pmic-dvs-2 { - samsung,pins = "gpx0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pmic_dvs_1: pmic-dvs-1 { - samsung,pins = "gpx0-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - samsung,pin-val = <1>; - }; - - max77802_irq: max77802-irq { - samsung,pins = "gpx0-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pwm { - /* - * PWM 0 -- fan - * PWM 1 -- Green LED - * PWM 2 -- Blue LED - * PWM 3 -- on MIPI connector for backlight - */ - pinctrl-0 = <&pwm0_out &pwm1_out &pwm2_out &pwm3_out>; - pinctrl-names = "default"; - status = "okay"; -}; - -&rtc { - status = "okay"; - clocks = <&clock CLK_RTC>, <&max77802 MAX77802_CLK_32K_AP>; - clock-names = "rtc", "rtc_src"; -}; - -&serial_0 { - status = "okay"; -}; - -&serial_1 { - status = "okay"; -}; - -&serial_2 { - status = "okay"; -}; - -&serial_3 { - status = "okay"; -}; - -&tmu_cpu0 { - vtmu-supply = <&ldo10_reg>; -}; - -&tmu_cpu1 { - vtmu-supply = <&ldo10_reg>; -}; - -&tmu_cpu2 { - vtmu-supply = <&ldo10_reg>; -}; - -&tmu_cpu3 { - vtmu-supply = <&ldo10_reg>; -}; - -&usbdrd_dwc3_0 { - dr_mode = "host"; -}; - -&usbdrd_dwc3_1 { - dr_mode = "peripheral"; -}; - -&usbdrd3_0 { - vdd33-supply = <&ldo12_reg>; - vdd10-supply = <&ldo15_reg>; -}; - -&usbdrd3_1 { - vdd33-supply = <&ldo12_reg>; - vdd10-supply = <&ldo15_reg>; -}; diff --git a/sys/gnu/dts/arm/exynos5410-pinctrl.dtsi b/sys/gnu/dts/arm/exynos5410-pinctrl.dtsi deleted file mode 100644 index 369a8a7f210..00000000000 --- a/sys/gnu/dts/arm/exynos5410-pinctrl.dtsi +++ /dev/null @@ -1,624 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Exynos5410 SoC pin-mux and pin-config device tree source - * - * Copyright (c) 2013 Hardkernel Co., Ltd. - * http://www.hardkernel.com - */ - -#include - -&pinctrl_0 { - gpa0: gpa0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpa1: gpa1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpa2: gpa2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpb0: gpb0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpb1: gpb1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpb2: gpb2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpb3: gpb3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc0: gpc0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc3: gpc3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc1: gpc1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc2: gpc2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpm5: gpm5 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpd1: gpd1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpe0: gpe0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpe1: gpe1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf0: gpf0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf1: gpf1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpg0: gpg0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpg1: gpg1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpg2: gpg2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gph0: gph0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gph1: gph1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpm7: gpm7 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy0: gpy0 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy1: gpy1 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy2: gpy2 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy3: gpy3 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy4: gpy4 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy5: gpy5 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy6: gpy6 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy7: gpy7 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpx0: gpx0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - interrupt-parent = <&combiner>; - #interrupt-cells = <2>; - interrupts = <23 0>, - <24 0>, - <25 0>, - <25 1>, - <26 0>, - <26 1>, - <27 0>, - <27 1>; - }; - - gpx1: gpx1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - interrupt-parent = <&combiner>; - #interrupt-cells = <2>; - interrupts = <28 0>, - <28 1>, - <29 0>, - <29 1>, - <30 0>, - <30 1>, - <31 0>, - <31 1>; - }; - - gpx2: gpx2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpx3: gpx3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - uart0_data: uart0-data { - samsung,pins = "gpa0-0", "gpa0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart0_fctl: uart0-fctl { - samsung,pins = "gpa0-2", "gpa0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart1_data: uart1-data { - samsung,pins = "gpa0-4", "gpa0-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart1_fctl: uart1-fctl { - samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c2_bus: i2c2-bus { - samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart2_data: uart2-data { - samsung,pins = "gpa1-0", "gpa1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart2_fctl: uart2-fctl { - samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c3_bus: i2c3-bus { - samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart3_data: uart3-data { - samsung,pins = "gpa1-4", "gpa1-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c4_hs_bus: i2c4-hs-bus { - samsung,pins = "gpa2-0", "gpa2-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c5_hs_bus: i2c5-hs-bus { - samsung,pins = "gpa2-2", "gpa2-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c6_hs_bus: i2c6-hs-bus { - samsung,pins = "gpb1-3", "gpb1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm0_out: pwm0-out { - samsung,pins = "gpb2-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm1_out: pwm1-out { - samsung,pins = "gpb2-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm2_out: pwm2-out { - samsung,pins = "gpb2-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm3_out: pwm3-out { - samsung,pins = "gpb2-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c7_hs_bus: i2c7-hs-bus { - samsung,pins = "gpb2-2", "gpb2-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c0_bus: i2c0-bus { - samsung,pins = "gpb3-0", "gpb3-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c1_bus: i2c1-bus { - samsung,pins = "gpb3-2", "gpb3-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_clk: sd0-clk { - samsung,pins = "gpc0-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_cmd: sd0-cmd { - samsung,pins = "gpc0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_cd: sd0-cd { - samsung,pins = "gpc0-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus1: sd0-bus-width1 { - samsung,pins = "gpc0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus4: sd0-bus-width4 { - samsung,pins = "gpc0-4", "gpc0-5", "gpc0-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_clk: sd2-clk { - samsung,pins = "gpc2-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_cmd: sd2-cmd { - samsung,pins = "gpc2-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_cd: sd2-cd { - samsung,pins = "gpc2-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_bus1: sd2-bus-width1 { - samsung,pins = "gpc2-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_bus4: sd2-bus-width4 { - samsung,pins = "gpc2-4", "gpc2-5", "gpc2-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus8: sd0-bus-width8 { - samsung,pins = "gpc3-0", "gpc3-1", "gpc3-2", "gpc3-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pinctrl_1 { - gpj0: gpj0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpj1: gpj1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpj2: gpj2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpj3: gpj3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpj4: gpj4 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpk0: gpk0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpk1: gpk1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpk2: gpk2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpk3: gpk3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; -}; - -&pinctrl_2 { - gpv0: gpv0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpv1: gpv1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpv2: gpv2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpv3: gpv3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpv4: gpv4 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; -}; - -&pinctrl_3 { - gpz: gpz { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - audi2s0_bus: audi2s0-bus { - samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", - "gpz-4"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - -}; diff --git a/sys/gnu/dts/arm/exynos5410-smdk5410.dts b/sys/gnu/dts/arm/exynos5410-smdk5410.dts deleted file mode 100644 index 5282b5deca8..00000000000 --- a/sys/gnu/dts/arm/exynos5410-smdk5410.dts +++ /dev/null @@ -1,111 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung SMDK5410 board device tree source - * - * Copyright (c) 2013 Samsung Electronics Co., Ltd. - * http://www.samsung.com - */ - -/dts-v1/; -#include "exynos5410.dtsi" -#include -/ { - model = "Samsung SMDK5410 board based on Exynos5410"; - compatible = "samsung,smdk5410", "samsung,exynos5410", "samsung,exynos5"; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x80000000>; - }; - - chosen { - stdout-path = "serial2:115200n8"; - }; - - fin_pll: xxti { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "fin_pll"; - #clock-cells = <0>; - }; - - firmware@2037000 { - compatible = "samsung,secure-firmware"; - reg = <0x02037000 0x1000>; - }; - -}; - -&mmc_0 { - status = "okay"; - cap-mmc-highspeed; - broken-cd; - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; - bus-width = <8>; -}; - -&mmc_2 { - status = "okay"; - cap-sd-highspeed; - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; - bus-width = <4>; - disable-wp; -}; - -&pinctrl_0 { - srom_ctl: srom-ctl { - samsung,pins = "gpy0-3", "gpy0-4", "gpy0-5", - "gpy1-0", "gpy1-1", "gpy1-2", "gpy1-3"; - samsung,pin-function = ; - samsung,pin-drv = ; - }; - - srom_ebi: srom-ebi { - samsung,pins = "gpy3-0", "gpy3-1", "gpy3-2", "gpy3-3", - "gpy3-4", "gpy3-5", "gpy3-6", "gpy3-7", - "gpy5-0", "gpy5-1", "gpy5-2", "gpy5-3", - "gpy5-4", "gpy5-5", "gpy5-6", "gpy5-7", - "gpy6-0", "gpy6-1", "gpy6-2", "gpy6-3", - "gpy6-4", "gpy6-5", "gpy6-6", "gpy6-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&sromc { - pinctrl-names = "default"; - pinctrl-0 = <&srom_ctl>, <&srom_ebi>; - - ethernet@3,0 { - compatible = "smsc,lan9115"; - reg = <3 0 0x10000>; - phy-mode = "mii"; - interrupt-parent = <&gpx0>; - interrupts = <5 IRQ_TYPE_LEVEL_LOW>; - reg-io-width = <2>; - smsc,irq-push-pull; - smsc,force-internal-phy; - - samsung,srom-page-mode; - samsung,srom-timing = <9 12 1 9 1 1>; - }; -}; - -&serial_0 { - status = "okay"; -}; - -&serial_1 { - status = "okay"; -}; - -&serial_2 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/exynos5410.dtsi b/sys/gnu/dts/arm/exynos5410.dtsi deleted file mode 100644 index 2eab80bf5f3..00000000000 --- a/sys/gnu/dts/arm/exynos5410.dtsi +++ /dev/null @@ -1,448 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung Exynos5410 SoC device tree source - * - * Copyright (c) 2013 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Samsung Exynos5410 SoC device nodes are listed in this file. - * Exynos5410 based board files can include this file and provide - * values for board specfic bindings. - */ - -#include "exynos54xx.dtsi" -#include -#include -#include - -/ { - compatible = "samsung,exynos5410", "samsung,exynos5"; - interrupt-parent = <&gic>; - - aliases { - pinctrl0 = &pinctrl_0; - pinctrl1 = &pinctrl_1; - pinctrl2 = &pinctrl_2; - pinctrl3 = &pinctrl_3; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x0>; - clock-frequency = <1600000000>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x1>; - clock-frequency = <1600000000>; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x2>; - clock-frequency = <1600000000>; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x3>; - clock-frequency = <1600000000>; - }; - }; - - soc: soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - pmu_system_controller: system-controller@10040000 { - compatible = "samsung,exynos5410-pmu", "syscon"; - reg = <0x10040000 0x5000>; - clock-names = "clkout16"; - clocks = <&fin_pll>; - #clock-cells = <1>; - }; - - clock: clock-controller@10010000 { - compatible = "samsung,exynos5410-clock"; - reg = <0x10010000 0x30000>; - #clock-cells = <1>; - }; - - clock_audss: audss-clock-controller@3810000 { - compatible = "samsung,exynos5410-audss-clock"; - reg = <0x03810000 0x0C>; - #clock-cells = <1>; - clocks = <&fin_pll>, <&clock CLK_FOUT_EPLL>; - clock-names = "pll_ref", "pll_in"; - }; - - tmu_cpu0: tmu@10060000 { - compatible = "samsung,exynos5420-tmu"; - reg = <0x10060000 0x100>; - interrupts = ; - clocks = <&clock CLK_TMU>; - clock-names = "tmu_apbif"; - #thermal-sensor-cells = <0>; - }; - - tmu_cpu1: tmu@10064000 { - compatible = "samsung,exynos5420-tmu"; - reg = <0x10064000 0x100>; - interrupts = ; - clocks = <&clock CLK_TMU>; - clock-names = "tmu_apbif"; - #thermal-sensor-cells = <0>; - }; - - tmu_cpu2: tmu@10068000 { - compatible = "samsung,exynos5420-tmu"; - reg = <0x10068000 0x100>; - interrupts = ; - clocks = <&clock CLK_TMU>; - clock-names = "tmu_apbif"; - #thermal-sensor-cells = <0>; - }; - - tmu_cpu3: tmu@1006c000 { - compatible = "samsung,exynos5420-tmu"; - reg = <0x1006c000 0x100>; - interrupts = ; - clocks = <&clock CLK_TMU>; - clock-names = "tmu_apbif"; - #thermal-sensor-cells = <0>; - }; - - mmc_0: mmc@12200000 { - compatible = "samsung,exynos5250-dw-mshc"; - reg = <0x12200000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>; - clock-names = "biu", "ciu"; - fifo-depth = <0x80>; - status = "disabled"; - }; - - mmc_1: mmc@12210000 { - compatible = "samsung,exynos5250-dw-mshc"; - reg = <0x12210000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>; - clock-names = "biu", "ciu"; - fifo-depth = <0x80>; - status = "disabled"; - }; - - mmc_2: mmc@12220000 { - compatible = "samsung,exynos5250-dw-mshc"; - reg = <0x12220000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>; - clock-names = "biu", "ciu"; - fifo-depth = <0x80>; - status = "disabled"; - }; - - pinctrl_0: pinctrl@13400000 { - compatible = "samsung,exynos5410-pinctrl"; - reg = <0x13400000 0x1000>; - interrupts = ; - - wakeup-interrupt-controller { - compatible = "samsung,exynos4210-wakeup-eint"; - interrupt-parent = <&gic>; - interrupts = ; - }; - }; - - pinctrl_1: pinctrl@14000000 { - compatible = "samsung,exynos5410-pinctrl"; - reg = <0x14000000 0x1000>; - interrupts = ; - }; - - pinctrl_2: pinctrl@10d10000 { - compatible = "samsung,exynos5410-pinctrl"; - reg = <0x10d10000 0x1000>; - interrupts = ; - }; - - pinctrl_3: pinctrl@3860000 { - compatible = "samsung,exynos5410-pinctrl"; - reg = <0x03860000 0x1000>; - interrupts = ; - }; - - amba { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&gic>; - ranges; - - pdma0: pdma@121a0000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x121a0000 0x1000>; - interrupts = ; - clocks = <&clock CLK_PDMA0>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; - }; - - pdma1: pdma@121b0000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x121b0000 0x1000>; - interrupts = ; - clocks = <&clock CLK_PDMA1>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; - }; - }; - - audi2s0: i2s@3830000 { - compatible = "samsung,exynos5420-i2s"; - reg = <0x03830000 0x100>; - dmas = <&pdma0 10>, - <&pdma0 9>, - <&pdma0 8>; - dma-names = "tx", "rx", "tx-sec"; - clocks = <&clock_audss EXYNOS_I2S_BUS>, - <&clock_audss EXYNOS_I2S_BUS>, - <&clock_audss EXYNOS_SCLK_I2S>; - clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; - #clock-cells = <1>; - clock-output-names = "i2s_cdclk0"; - #sound-dai-cells = <1>; - samsung,idma-addr = <0x03000000>; - pinctrl-names = "default"; - pinctrl-0 = <&audi2s0_bus>; - status = "disabled"; - }; - }; - - thermal-zones { - cpu0_thermal: cpu0-thermal { - thermal-sensors = <&tmu_cpu0>; - #include "exynos5420-trip-points.dtsi" - }; - cpu1_thermal: cpu1-thermal { - thermal-sensors = <&tmu_cpu1>; - #include "exynos5420-trip-points.dtsi" - }; - cpu2_thermal: cpu2-thermal { - thermal-sensors = <&tmu_cpu2>; - #include "exynos5420-trip-points.dtsi" - }; - cpu3_thermal: cpu3-thermal { - thermal-sensors = <&tmu_cpu3>; - #include "exynos5420-trip-points.dtsi" - }; - }; -}; - -&adc { - clocks = <&clock CLK_TSADC>; - clock-names = "adc"; - samsung,syscon-phandle = <&pmu_system_controller>; -}; - -&arm_a15_pmu { - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; - status = "okay"; -}; - -&i2c_0 { - clocks = <&clock CLK_I2C0>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_bus>; -}; - -&i2c_1 { - clocks = <&clock CLK_I2C1>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_bus>; -}; - -&i2c_2 { - clocks = <&clock CLK_I2C2>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_bus>; -}; - -&i2c_3 { - clocks = <&clock CLK_I2C3>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_bus>; -}; - -&hsi2c_4 { - clocks = <&clock CLK_USI0>; - clock-names = "hsi2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_hs_bus>; -}; - -&hsi2c_5 { - clocks = <&clock CLK_USI1>; - clock-names = "hsi2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c5_hs_bus>; -}; - -&hsi2c_6 { - clocks = <&clock CLK_USI2>; - clock-names = "hsi2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c6_hs_bus>; -}; - -&hsi2c_7 { - clocks = <&clock CLK_USI3>; - clock-names = "hsi2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c7_hs_bus>; -}; - -&mct { - clocks = <&fin_pll>, <&clock CLK_MCT>; - clock-names = "fin_pll", "mct"; -}; - -&prng { - clocks = <&clock CLK_SSS>; - clock-names = "secss"; -}; - -&pwm { - clocks = <&clock CLK_PWM>; - clock-names = "timers"; -}; - -&rtc { - clocks = <&clock CLK_RTC>; - clock-names = "rtc"; - status = "disabled"; -}; - -&serial_0 { - clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; - clock-names = "uart", "clk_uart_baud0"; - dmas = <&pdma0 13>, <&pdma0 14>; - dma-names = "rx", "tx"; -}; - -&serial_1 { - clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>; - clock-names = "uart", "clk_uart_baud0"; - dmas = <&pdma1 15>, <&pdma1 16>; - dma-names = "rx", "tx"; -}; - -&serial_2 { - clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; - clock-names = "uart", "clk_uart_baud0"; - dmas = <&pdma0 15>, <&pdma0 16>; - dma-names = "rx", "tx"; -}; - -&serial_3 { - clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>; - clock-names = "uart", "clk_uart_baud0"; - dmas = <&pdma1 17>, <&pdma1 18>; - dma-names = "rx", "tx"; -}; - -&sss { - clocks = <&clock CLK_SSS>; - clock-names = "secss"; -}; - -&sromc { - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0x04000000 0x20000 - 1 0 0x05000000 0x20000 - 2 0 0x06000000 0x20000 - 3 0 0x07000000 0x20000>; -}; - -&trng { - clocks = <&clock CLK_SSS>; - clock-names = "secss"; -}; - -&usbdrd3_0 { - clocks = <&clock CLK_USBD300>; - clock-names = "usbdrd30"; -}; - -&usbdrd_phy0 { - clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>; - clock-names = "phy", "ref"; - samsung,pmu-syscon = <&pmu_system_controller>; -}; - -&usbdrd3_1 { - clocks = <&clock CLK_USBD301>; - clock-names = "usbdrd30"; -}; - -&usbdrd_dwc3_1 { - interrupts = ; -}; - -&usbdrd_phy1 { - clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>; - clock-names = "phy", "ref"; - samsung,pmu-syscon = <&pmu_system_controller>; -}; - -&usbhost1 { - clocks = <&clock CLK_USBH20>; - clock-names = "usbhost"; -}; - -&usbhost2 { - clocks = <&clock CLK_USBH20>; - clock-names = "usbhost"; -}; - -&usb2_phy { - clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>; - clock-names = "phy", "ref"; - samsung,sysreg-phandle = <&sysreg_system_controller>; - samsung,pmureg-phandle = <&pmu_system_controller>; -}; - -&watchdog { - clocks = <&clock CLK_WDT>; - clock-names = "watchdog"; - samsung,syscon-phandle = <&pmu_system_controller>; -}; - -#include "exynos5410-pinctrl.dtsi" -#include "exynos-syscon-restart.dtsi" diff --git a/sys/gnu/dts/arm/exynos5420-arndale-octa.dts b/sys/gnu/dts/arm/exynos5420-arndale-octa.dts deleted file mode 100644 index ee28d30f547..00000000000 --- a/sys/gnu/dts/arm/exynos5420-arndale-octa.dts +++ /dev/null @@ -1,824 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's Exynos5420 based Arndale Octa board device tree source - * - * Copyright (c) 2013 Samsung Electronics Co., Ltd. - * http://www.samsung.com - */ - -/dts-v1/; -#include "exynos5420.dtsi" -#include "exynos5420-cpus.dtsi" -#include -#include -#include -#include - -/ { - model = "Insignal Arndale Octa evaluation board based on Exynos5420"; - compatible = "insignal,arndale-octa", "samsung,exynos5420", "samsung,exynos5"; - - memory@20000000 { - device_type = "memory"; - reg = <0x20000000 0x80000000>; - }; - - chosen { - stdout-path = "serial3:115200n8"; - }; - - firmware@2073000 { - compatible = "samsung,secure-firmware"; - reg = <0x02073000 0x1000>; - }; - - fixed-rate-clocks { - oscclk { - compatible = "samsung,exynos5420-oscclk"; - clock-frequency = <24000000>; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - - wakeup { - label = "SW-TACT1"; - gpios = <&gpx2 7 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - }; -}; - -&adc { - vdd-supply = <&ldo4_reg>; - status = "okay"; -}; - -&cci { - status = "disabled"; -}; - -&cpu0 { - cpu-supply = <&buck2_reg>; -}; - -&cpu4 { - cpu-supply = <&buck6_reg>; -}; - -&cpu0_thermal { - trips { - cpu0_alert0: cpu-alert-0 { - temperature = <60000>; /* millicelsius */ - hysteresis = <5000>; /* millicelsius */ - type = "passive"; - }; - cpu0_alert1: cpu-alert-1 { - temperature = <80000>; /* millicelsius */ - hysteresis = <10000>; /* millicelsius */ - type = "passive"; - }; - cpu0_alert2: cpu-alert-2 { - temperature = <110000>; /* millicelsius */ - hysteresis = <10000>; /* millicelsius */ - type = "passive"; - }; - cpu0_crit0: cpu-crit-0 { - temperature = <120000>; /* millicelsius */ - hysteresis = <0>; /* millicelsius */ - type = "critical"; - }; - }; - - cooling-maps { - /* - * Reduce the CPU speed by 2 steps, down to: 1600 MHz - * and 1100 MHz. - */ - map0 { - trip = <&cpu0_alert0>; - cooling-device = <&cpu0 0 2>, - <&cpu1 0 2>, - <&cpu2 0 2>, - <&cpu3 0 2>, - <&cpu4 0 2>, - <&cpu5 0 2>, - <&cpu6 0 2>, - <&cpu7 0 2>; - }; - - /* - * Reduce the CPU speed down to 1200 MHz big (6 steps) - * and 800 MHz LITTLE (5 steps). - */ - map1 { - trip = <&cpu0_alert1>; - cooling-device = <&cpu0 3 6>, - <&cpu1 3 6>, - <&cpu2 3 6>, - <&cpu3 3 6>, - <&cpu4 3 5>, - <&cpu5 3 5>, - <&cpu6 3 5>, - <&cpu7 3 5>; - }; - - /* - * Reduce the CPU speed as much as possible, down to 700 MHz - * big (11 steps) and 600 MHz LITTLE (7 steps). - */ - map2 { - trip = <&cpu0_alert2>; - cooling-device = <&cpu0 6 11>, - <&cpu1 6 11>, - <&cpu2 6 11>, - <&cpu3 6 11>, - <&cpu4 5 7>, - <&cpu5 5 7>, - <&cpu6 5 7>, - <&cpu7 5 7>; - }; - }; -}; - -&cpu1_thermal { - trips { - cpu1_alert0: cpu-alert-0 { - temperature = <60000>; /* millicelsius */ - hysteresis = <5000>; /* millicelsius */ - type = "passive"; - }; - cpu1_alert1: cpu-alert-1 { - temperature = <80000>; /* millicelsius */ - hysteresis = <10000>; /* millicelsius */ - type = "passive"; - }; - cpu1_alert2: cpu-alert-2 { - temperature = <110000>; /* millicelsius */ - hysteresis = <10000>; /* millicelsius */ - type = "passive"; - }; - cpu1_crit0: cpu-crit-0 { - temperature = <120000>; /* millicelsius */ - hysteresis = <0>; /* millicelsius */ - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu1_alert0>; - cooling-device = <&cpu0 0 2>, - <&cpu1 0 2>, - <&cpu2 0 2>, - <&cpu3 0 2>, - <&cpu4 0 2>, - <&cpu5 0 2>, - <&cpu6 0 2>, - <&cpu7 0 2>; - }; - - map1 { - trip = <&cpu1_alert1>; - cooling-device = <&cpu0 3 6>, - <&cpu1 3 6>, - <&cpu2 3 6>, - <&cpu3 3 6>, - <&cpu4 3 5>, - <&cpu5 3 5>, - <&cpu6 3 5>, - <&cpu7 3 5>; - }; - - map2 { - trip = <&cpu1_alert2>; - cooling-device = <&cpu0 6 11>, - <&cpu1 6 11>, - <&cpu2 6 11>, - <&cpu3 6 11>, - <&cpu4 5 7>, - <&cpu5 5 7>, - <&cpu6 5 7>, - <&cpu7 5 7>; - }; - }; -}; - -&cpu2_thermal { - trips { - cpu2_alert0: cpu-alert-0 { - temperature = <60000>; /* millicelsius */ - hysteresis = <5000>; /* millicelsius */ - type = "passive"; - }; - cpu2_alert1: cpu-alert-1 { - temperature = <80000>; /* millicelsius */ - hysteresis = <10000>; /* millicelsius */ - type = "passive"; - }; - cpu2_alert2: cpu-alert-2 { - temperature = <110000>; /* millicelsius */ - hysteresis = <10000>; /* millicelsius */ - type = "passive"; - }; - cpu2_crit0: cpu-crit-0 { - temperature = <120000>; /* millicelsius */ - hysteresis = <0>; /* millicelsius */ - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu2_alert0>; - cooling-device = <&cpu0 0 2>, - <&cpu1 0 2>, - <&cpu2 0 2>, - <&cpu3 0 2>, - <&cpu4 0 2>, - <&cpu5 0 2>, - <&cpu6 0 2>, - <&cpu7 0 2>; - }; - - map1 { - trip = <&cpu2_alert1>; - cooling-device = <&cpu0 3 6>, - <&cpu1 3 6>, - <&cpu2 3 6>, - <&cpu3 3 6>, - <&cpu4 3 5>, - <&cpu5 3 5>, - <&cpu6 3 5>, - <&cpu7 3 5>; - }; - - map2 { - trip = <&cpu2_alert2>; - cooling-device = <&cpu0 6 11>, - <&cpu1 6 11>, - <&cpu2 6 11>, - <&cpu3 6 11>, - <&cpu4 6 7>, - <&cpu5 6 7>, - <&cpu6 6 7>, - <&cpu7 6 7>; - }; - }; -}; - -&cpu3_thermal { - trips { - cpu3_alert0: cpu-alert-0 { - temperature = <60000>; /* millicelsius */ - hysteresis = <5000>; /* millicelsius */ - type = "passive"; - }; - cpu3_alert1: cpu-alert-1 { - temperature = <80000>; /* millicelsius */ - hysteresis = <10000>; /* millicelsius */ - type = "passive"; - }; - cpu3_alert2: cpu-alert-2 { - temperature = <110000>; /* millicelsius */ - hysteresis = <10000>; /* millicelsius */ - type = "passive"; - }; - cpu3_crit0: cpu-crit-0 { - temperature = <120000>; /* millicelsius */ - hysteresis = <0>; /* millicelsius */ - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu3_alert0>; - cooling-device = <&cpu0 0 2>, - <&cpu1 0 2>, - <&cpu2 0 2>, - <&cpu3 0 2>, - <&cpu4 0 2>, - <&cpu5 0 2>, - <&cpu6 0 2>, - <&cpu7 0 2>; - }; - - map1 { - trip = <&cpu3_alert1>; - cooling-device = <&cpu0 3 6>, - <&cpu1 3 6>, - <&cpu2 3 6>, - <&cpu3 3 6>, - <&cpu4 3 5>, - <&cpu5 3 5>, - <&cpu6 3 5>, - <&cpu7 3 5>; - }; - - map2 { - trip = <&cpu3_alert2>; - cooling-device = <&cpu0 6 11>, - <&cpu1 6 11>, - <&cpu2 6 11>, - <&cpu3 6 11>, - <&cpu4 5 7>, - <&cpu5 5 7>, - <&cpu6 5 7>, - <&cpu7 5 7>; - }; - }; -}; - -&hdmi { - hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; - vdd_osc-supply = <&ldo7_reg>; - vdd_pll-supply = <&ldo6_reg>; - vdd-supply = <&ldo6_reg>; - ddc = <&i2c_2>; - status = "okay"; -}; - -&hsi2c_4 { - status = "okay"; - - s2mps11_pmic@66 { - compatible = "samsung,s2mps11-pmic"; - reg = <0x66>; - - interrupt-parent = <&gpx3>; - interrupts = <2 IRQ_TYPE_EDGE_FALLING>; - pinctrl-names = "default"; - pinctrl-0 = <&s2mps11_irq>; - - s2mps11_osc: clocks { - compatible = "samsung,s2mps11-clk"; - #clock-cells = <1>; - clock-output-names = "s2mps11_ap", - "s2mps11_cp", "s2mps11_bt"; - }; - - regulators { - ldo1_reg: LDO1 { - regulator-name = "PVDD_ALIVE_1V0"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo2_reg: LDO2 { - regulator-name = "PVDD_APIO_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo3_reg: LDO3 { - regulator-name = "PVDD_APIO_MMCON_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - /* - * Must be always on, even though there is - * a consumer (mmc_0). Otherwise the board - * does not reboot with vendor U-Boot - * (Linaro for Arndale Octa, v2012.07). - */ - regulator-always-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo4_reg: LDO4 { - regulator-name = "PVDD_ADC_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo5_reg: LDO5 { - regulator-name = "PVDD_PLL_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo6_reg: LDO6 { - regulator-name = "PVDD_ANAIP_1V0"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - }; - - ldo7_reg: LDO7 { - regulator-name = "PVDD_ANAIP_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo8_reg: LDO8 { - regulator-name = "PVDD_ABB_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo9_reg: LDO9 { - regulator-name = "PVDD_USB_3V3"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - }; - - ldo10_reg: LDO10 { - regulator-name = "PVDD_PRE_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo11_reg: LDO11 { - regulator-name = "PVDD_USB_1V0"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo12_reg: LDO12 { - regulator-name = "PVDD_HSIC_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo13_reg: LDO13 { - regulator-name = "PVDD_APIO_MMCOFF_2V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo14_reg: LDO14 { - /* Unused */ - regulator-name = "PVDD_LDO14"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3950000>; - }; - - ldo15_reg: LDO15 { - regulator-name = "PVDD_PERI_2V8"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - ldo16_reg: LDO16 { - regulator-name = "PVDD_PERI_3V3"; - regulator-min-microvolt = <2200000>; - regulator-max-microvolt = <2200000>; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - ldo17_reg: LDO17 { - /* Unused */ - regulator-name = "PVDD_LDO17"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3950000>; - }; - - ldo18_reg: LDO18 { - regulator-name = "PVDD_EMMC_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - /* - * Must stay in "off" mode during shutdown for - * proper eMMC reset. The "off" mode is in - * fact controlled by LDO18EN. The eMMC does - * not have reset pin connected so the reset - * will be triggered by falling edge of - * LDO18EN. - */ - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo19_reg: LDO19 { - regulator-name = "PVDD_TFLASH_2V8"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo20_reg: LDO20 { - regulator-name = "PVDD_BTWIFI_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo21_reg: LDO21 { - regulator-name = "PVDD_CAM1IO_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo22_reg: LDO22 { - /* Unused */ - regulator-name = "PVDD_LDO22"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <2375000>; - }; - - ldo23_reg: LDO23 { - regulator-name = "PVDD_MIFS_1V1"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - ldo24_reg: LDO24 { - regulator-name = "PVDD_CAM1_AVDD_2V8"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - ldo25_reg: LDO25 { - /* Unused */ - regulator-name = "PVDD_LDO25"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3950000>; - }; - - ldo26_reg: LDO26 { - regulator-name = "PVDD_CAM0_AF_2V8"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - ldo27_reg: LDO27 { - regulator-name = "PVDD_G3DS_1V0"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1100000>; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - ldo28_reg: LDO28 { - regulator-name = "PVDD_TSP_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo29_reg: LDO29 { - regulator-name = "PVDD_AUDIO_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo30_reg: LDO30 { - /* Unused */ - regulator-name = "PVDD_LDO30"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3950000>; - }; - - ldo31_reg: LDO31 { - regulator-name = "PVDD_PERI_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo32_reg: LDO32 { - regulator-name = "PVDD_LCD_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo33_reg: LDO33 { - regulator-name = "PVDD_CAM0IO_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo34_reg: LDO34 { - /* Unused */ - regulator-name = "PVDD_LDO34"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3950000>; - }; - - ldo35_reg: LDO35 { - regulator-name = "PVDD_CAM0_DVDD_1V2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - ldo36_reg: LDO36 { - /* Unused */ - regulator-name = "PVDD_LDO36"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3950000>; - }; - - ldo37_reg: LDO37 { - /* Unused */ - regulator-name = "PVDD_LDO37"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3950000>; - }; - - ldo38_reg: LDO38 { - regulator-name = "PVDD_CAM0_AVDD_2V8"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - buck1_reg: BUCK1 { - regulator-name = "PVDD_MIF_1V1"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck2_reg: BUCK2 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck3_reg: BUCK3 { - regulator-name = "PVDD_INT_1V0"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck4_reg: BUCK4 { - regulator-name = "PVDD_G3D_1V0"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck5_reg: BUCK5 { - regulator-name = "PVDD_LPDDR3_1V2"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - }; - - buck6_reg: BUCK6 { - regulator-name = "PVDD_KFC_1V0"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck7_reg: BUCK7 { - regulator-name = "VIN_LLDO_1V4"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - }; - - buck8_reg: BUCK8 { - regulator-name = "VIN_MLDO_2V0"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2100000>; - regulator-always-on; - }; - - buck9_reg: BUCK9 { - regulator-name = "VIN_HLDO_3V5"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3500000>; - regulator-always-on; - }; - - buck10_reg: BUCK10 { - regulator-name = "PVDD_EMMCF_2V8"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - /* - * Must stay in "off" mode during shutdown for - * proper eMMC reset. The "off" mode is in - * fact controlled by BUCK10EN. The eMMC does - * not have reset pin connected so the reset - * will be triggered by falling edge of - * BUCK10EN. - */ - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; -}; - -&i2c_2 { - status = "okay"; -}; - -&mixer { - status = "okay"; -}; - -&mmc_0 { - status = "okay"; - non-removable; - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <0 4>; - samsung,dw-mshc-ddr-timing = <0 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>; - vmmc-supply = <&ldo18_reg>; - vqmmc-supply = <&ldo3_reg>; - bus-width = <8>; - cap-mmc-highspeed; - mmc-hs200-1_8v; -}; - -&mmc_2 { - status = "okay"; - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <0 4>; - samsung,dw-mshc-ddr-timing = <0 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>; - vmmc-supply = <&ldo19_reg>; - vqmmc-supply = <&ldo13_reg>; - bus-width = <4>; - cap-sd-highspeed; - sd-uhs-sdr50; - sd-uhs-sdr104; - sd-uhs-ddr50; -}; - -&pinctrl_0 { - s2mps11_irq: s2mps11-irq { - samsung,pins = "gpx3-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&rtc { - status = "okay"; - clocks = <&clock CLK_RTC>, <&s2mps11_osc S2MPS11_CLK_AP>; - clock-names = "rtc", "rtc_src"; -}; - -&usbdrd_dwc3_1 { - dr_mode = "host"; -}; diff --git a/sys/gnu/dts/arm/exynos5420-cpus.dtsi b/sys/gnu/dts/arm/exynos5420-cpus.dtsi deleted file mode 100644 index 58d1c54cf92..00000000000 --- a/sys/gnu/dts/arm/exynos5420-cpus.dtsi +++ /dev/null @@ -1,131 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung Exynos5420 SoC cpu device tree source - * - * Copyright (c) 2015 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * This file provides desired ordering for Exynos5420 and Exynos5800 - * boards: CPU[0123] being the A15. - * - * The Exynos5420, 5422 and 5800 actually share the same CPU configuration - * but particular boards choose different booting order. - * - * Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422 - * booting cluster (big or LITTLE) is chosen by IROM code by reading - * the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting - * from the LITTLE: Cortex-A7. - */ - -/ { - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x0>; - clocks = <&clock CLK_ARM_CLK>; - clock-frequency = <1800000000>; - cci-control-port = <&cci_control1>; - operating-points-v2 = <&cluster_a15_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - capacity-dmips-mhz = <1024>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x1>; - clocks = <&clock CLK_ARM_CLK>; - clock-frequency = <1800000000>; - cci-control-port = <&cci_control1>; - operating-points-v2 = <&cluster_a15_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - capacity-dmips-mhz = <1024>; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x2>; - clocks = <&clock CLK_ARM_CLK>; - clock-frequency = <1800000000>; - cci-control-port = <&cci_control1>; - operating-points-v2 = <&cluster_a15_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - capacity-dmips-mhz = <1024>; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x3>; - clocks = <&clock CLK_ARM_CLK>; - clock-frequency = <1800000000>; - cci-control-port = <&cci_control1>; - operating-points-v2 = <&cluster_a15_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - capacity-dmips-mhz = <1024>; - }; - - cpu4: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x100>; - clocks = <&clock CLK_KFC_CLK>; - clock-frequency = <1000000000>; - cci-control-port = <&cci_control0>; - operating-points-v2 = <&cluster_a7_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - capacity-dmips-mhz = <539>; - }; - - cpu5: cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x101>; - clocks = <&clock CLK_KFC_CLK>; - clock-frequency = <1000000000>; - cci-control-port = <&cci_control0>; - operating-points-v2 = <&cluster_a7_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - capacity-dmips-mhz = <539>; - }; - - cpu6: cpu@102 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x102>; - clocks = <&clock CLK_KFC_CLK>; - clock-frequency = <1000000000>; - cci-control-port = <&cci_control0>; - operating-points-v2 = <&cluster_a7_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - capacity-dmips-mhz = <539>; - }; - - cpu7: cpu@103 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x103>; - clocks = <&clock CLK_KFC_CLK>; - clock-frequency = <1000000000>; - cci-control-port = <&cci_control0>; - operating-points-v2 = <&cluster_a7_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - capacity-dmips-mhz = <539>; - }; - }; -}; - -&arm_a7_pmu { - interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; - status = "okay"; -}; - -&arm_a15_pmu { - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/exynos5420-peach-pit.dts b/sys/gnu/dts/arm/exynos5420-peach-pit.dts deleted file mode 100644 index 2bcbdf8a39b..00000000000 --- a/sys/gnu/dts/arm/exynos5420-peach-pit.dts +++ /dev/null @@ -1,1118 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Google Peach Pit Rev 6+ board device tree source - * - * Copyright (c) 2014 Google, Inc - */ - -/dts-v1/; -#include -#include -#include -#include -#include -#include -#include "exynos5420.dtsi" -#include "exynos5420-cpus.dtsi" - -/ { - model = "Google Peach Pit Rev 6+"; - - compatible = "google,pit-rev16", - "google,pit-rev15", "google,pit-rev14", - "google,pit-rev13", "google,pit-rev12", - "google,pit-rev11", "google,pit-rev10", - "google,pit-rev9", "google,pit-rev8", - "google,pit-rev7", "google,pit-rev6", - "google,pit", "google,peach","samsung,exynos5420", - "samsung,exynos5"; - - aliases { - /* Assign 20 so we don't get confused w/ builtin ones */ - i2c20 = &i2c_tunnel; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 0 1000000 0>; - brightness-levels = <0 100 500 1000 1500 2000 2500 2800>; - default-brightness-level = <7>; - power-supply = <&tps65090_fet1>; - pinctrl-0 = <&pwm0_out>; - pinctrl-names = "default"; - }; - - chosen { - stdout-path = "serial3:115200n8"; - }; - - fixed-rate-clocks { - oscclk { - compatible = "samsung,exynos5420-oscclk"; - clock-frequency = <24000000>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - pinctrl-names = "default"; - pinctrl-0 = <&power_key_irq &lid_irq>; - - power { - label = "Power"; - gpios = <&gpx1 2 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - - lid-switch { - label = "Lid"; - gpios = <&gpx3 4 GPIO_ACTIVE_LOW>; - linux,input-type = <5>; /* EV_SW */ - linux,code = <0>; /* SW_LID */ - debounce-interval = <1>; - wakeup-source; - }; - }; - - memory@20000000 { - device_type = "memory"; - reg = <0x20000000 0x80000000>; - }; - - sound { - compatible = "google,snow-audio-max98090"; - - samsung,model = "Peach-Pit-I2S-MAX98090"; - samsung,i2s-controller = <&i2s0>; - samsung,audio-codec = <&max98090>; - - cpu { - sound-dai = <&i2s0 0>; - }; - - codec { - sound-dai = <&max98090>, <&hdmi>; - }; - }; - - usb300_vbus_reg: regulator-usb300 { - compatible = "regulator-fixed"; - regulator-name = "P5.0V_USB3CON0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gph0 0 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&usb300_vbus_en>; - enable-active-high; - }; - - usb301_vbus_reg: regulator-usb301 { - compatible = "regulator-fixed"; - regulator-name = "P5.0V_USB3CON1"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gph0 1 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&usb301_vbus_en>; - enable-active-high; - }; - - vbat: fixed-regulator { - compatible = "regulator-fixed"; - regulator-name = "vbat-supply"; - regulator-boot-on; - regulator-always-on; - }; - - panel: panel { - compatible = "auo,b116xw03"; - power-supply = <&tps65090_fet6>; - backlight = <&backlight>; - - port { - panel_in: endpoint { - remote-endpoint = <&bridge_out>; - }; - }; - }; - - mmc1_pwrseq: mmc1_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpx0 0 GPIO_ACTIVE_LOW>; /* WIFI_EN */ - clocks = <&max77802 MAX77802_CLK_32K_CP>; - clock-names = "ext_clock"; - }; -}; - -&adc { - status = "okay"; - vdd-supply = <&ldo9_reg>; -}; - -&clock_audss { - assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>; - assigned-clock-parents = <&clock CLK_MAU_EPLL>; -}; - -&cpu0 { - cpu-supply = <&buck2_reg>; -}; - -&cpu4 { - cpu-supply = <&buck6_reg>; -}; - -&dp { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&dp_hpd_gpio>; - samsung,color-space = <0>; - samsung,color-depth = <1>; - samsung,link-rate = <0x06>; - samsung,lane-count = <2>; - hpd-gpios = <&gpx2 6 GPIO_ACTIVE_HIGH>; - - ports { - port { - dp_out: endpoint { - remote-endpoint = <&bridge_in>; - }; - }; - }; -}; - -&fimd { - status = "okay"; - samsung,invert-vclk; -}; - -&hdmi { - status = "okay"; - hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_hpd_irq>; - ddc = <&i2c_2>; - - hdmi-en-supply = <&tps65090_fet7>; - vdd-supply = <&ldo8_reg>; - vdd_osc-supply = <&ldo10_reg>; - vdd_pll-supply = <&ldo8_reg>; -}; - -&hsi2c_4 { - status = "okay"; - clock-frequency = <400000>; - - max77802: max77802-pmic@9 { - compatible = "maxim,max77802"; - interrupt-parent = <&gpx3>; - interrupts = <1 IRQ_TYPE_NONE>; - pinctrl-names = "default"; - pinctrl-0 = <&max77802_irq>, <&pmic_selb>, - <&pmic_dvs_1>, <&pmic_dvs_2>, <&pmic_dvs_3>; - wakeup-source; - reg = <0x9>; - #clock-cells = <1>; - - inb1-supply = <&tps65090_dcdc2>; - inb2-supply = <&tps65090_dcdc1>; - inb3-supply = <&tps65090_dcdc2>; - inb4-supply = <&tps65090_dcdc2>; - inb5-supply = <&tps65090_dcdc1>; - inb6-supply = <&tps65090_dcdc2>; - inb7-supply = <&tps65090_dcdc1>; - inb8-supply = <&tps65090_dcdc1>; - inb9-supply = <&tps65090_dcdc1>; - inb10-supply = <&tps65090_dcdc1>; - - inl1-supply = <&buck5_reg>; - inl2-supply = <&buck7_reg>; - inl3-supply = <&buck9_reg>; - inl4-supply = <&buck9_reg>; - inl5-supply = <&buck9_reg>; - inl6-supply = <&tps65090_dcdc2>; - inl7-supply = <&buck9_reg>; - inl9-supply = <&tps65090_dcdc2>; - inl10-supply = <&buck7_reg>; - - regulators { - buck1_reg: BUCK1 { - regulator-name = "vdd_mif"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - regulator-ramp-delay = <12500>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck2_reg: BUCK2 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - regulator-ramp-delay = <12500>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck3_reg: BUCK3 { - regulator-name = "vdd_int"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-boot-on; - regulator-ramp-delay = <12500>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck4_reg: BUCK4 { - regulator-name = "vdd_g3d"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-boot-on; - regulator-ramp-delay = <12500>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck5_reg: BUCK5 { - regulator-name = "vdd_1v2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck6_reg: BUCK6 { - regulator-name = "vdd_kfc"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - regulator-ramp-delay = <12500>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck7_reg: BUCK7 { - regulator-name = "vdd_1v35"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - buck8_reg: BUCK8 { - regulator-name = "vdd_emmc"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck9_reg: BUCK9 { - regulator-name = "vdd_2v"; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - buck10_reg: BUCK10 { - regulator-name = "vdd_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - ldo1_reg: LDO1 { - regulator-name = "vdd_1v0"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-mode = ; - }; - }; - - ldo2_reg: LDO2 { - regulator-name = "vdd_1v2_2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - ldo3_reg: LDO3 { - regulator-name = "vdd_1v8_3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-mode = ; - }; - }; - - vqmmc_sdcard: ldo4_reg: LDO4 { - regulator-name = "vdd_sd"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo5_reg: LDO5 { - regulator-name = "vdd_1v8_5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo6_reg: LDO6 { - regulator-name = "vdd_1v8_6"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo7_reg: LDO7 { - regulator-name = "vdd_1v8_7"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo8_reg: LDO8 { - regulator-name = "vdd_ldo8"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo9_reg: LDO9 { - regulator-name = "vdd_ldo9"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-mode = ; - }; - }; - - ldo10_reg: LDO10 { - regulator-name = "vdd_ldo10"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo11_reg: LDO11 { - regulator-name = "vdd_ldo11"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-mode = ; - }; - }; - - ldo12_reg: LDO12 { - regulator-name = "vdd_ldo12"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo13_reg: LDO13 { - regulator-name = "vdd_ldo13"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-mode = ; - }; - }; - - ldo14_reg: LDO14 { - regulator-name = "vdd_ldo14"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo15_reg: LDO15 { - regulator-name = "vdd_ldo15"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo17_reg: LDO17 { - regulator-name = "vdd_g3ds"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo18_reg: LDO18 { - regulator-name = "ldo_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo19_reg: LDO19 { - regulator-name = "ldo_19"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo20_reg: LDO20 { - regulator-name = "ldo_20"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo21_reg: LDO21 { - regulator-name = "ldo_21"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo23_reg: LDO23 { - regulator-name = "ldo_23"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - ldo24_reg: LDO24 { - regulator-name = "ldo_24"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo25_reg: LDO25 { - regulator-name = "ldo_25"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo26_reg: LDO26 { - regulator-name = "ldo_26"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - ldo27_reg: LDO27 { - regulator-name = "ldo_27"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - ldo28_reg: LDO28 { - regulator-name = "ldo_28"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo29_reg: LDO29 { - regulator-name = "ldo_29"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo30_reg: LDO30 { - regulator-name = "vdd_mifs"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo32_reg: LDO32 { - regulator-name = "ldo_32"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - ldo33_reg: LDO33 { - regulator-name = "ldo_33"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo34_reg: LDO34 { - regulator-name = "ldo_34"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - ldo35_reg: LDO35 { - regulator-name = "ldo_35"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - }; - }; -}; - -&hsi2c_7 { - status = "okay"; - clock-frequency = <400000>; - - max98090: codec@10 { - compatible = "maxim,max98090"; - reg = <0x10>; - interrupts = <2 IRQ_TYPE_NONE>; - interrupt-parent = <&gpx0>; - pinctrl-names = "default"; - pinctrl-0 = <&max98090_irq>; - clocks = <&pmu_system_controller 0>; - clock-names = "mclk"; - #sound-dai-cells = <0>; - }; - - light-sensor@44 { - compatible = "isil,isl29018"; - reg = <0x44>; - vcc-supply = <&tps65090_fet5>; - }; - - ps8625: lvds-bridge@48 { - compatible = "parade,ps8625"; - reg = <0x48>; - sleep-gpios = <&gpx3 5 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpy7 7 GPIO_ACTIVE_HIGH>; - lane-count = <2>; - use-external-pwm; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - bridge_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - - port@1 { - reg = <1>; - - bridge_in: endpoint { - remote-endpoint = <&dp_out>; - }; - }; - }; - - }; -}; - -&hsi2c_8 { - status = "okay"; - clock-frequency = <333000>; - - /* Atmel mXT336S */ - trackpad@4b { - compatible = "atmel,maxtouch"; - reg = <0x4b>; - interrupt-parent = <&gpx1>; - interrupts = <1 IRQ_TYPE_EDGE_FALLING>; - wakeup-source; - pinctrl-names = "default"; - pinctrl-0 = <&trackpad_irq>; - linux,gpio-keymap = ; /* GPIO3 */ - }; -}; - -&hsi2c_9 { - status = "okay"; - clock-frequency = <400000>; - - tpm@20 { - compatible = "infineon,slb9645tt"; - reg = <0x20>; - - /* Unused irq; but still need to configure the pins */ - pinctrl-names = "default"; - pinctrl-0 = <&tpm_irq>; - }; -}; - -&i2c_2 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <66000>; - samsung,i2c-slave-addr = <0x50>; -}; - -&i2s0 { - assigned-clocks = <&i2s0 CLK_I2S_RCLK_SRC>; - assigned-clock-parents = <&clock_audss EXYNOS_I2S_BUS>; - status = "okay"; -}; - -&mixer { - status = "okay"; -}; - -/* eMMC flash */ -&mmc_0 { - status = "okay"; - mmc-hs200-1_8v; - cap-mmc-highspeed; - non-removable; - clock-frequency = <400000000>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <0 4>; - samsung,dw-mshc-ddr-timing = <0 2>; - samsung,dw-mshc-hs400-timing = <0 2>; - samsung,read-strobe-delay = <90>; - pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8 &sd0_rclk>; - bus-width = <8>; -}; - -/* WiFi SDIO module */ -&mmc_1 { - status = "okay"; - non-removable; - cap-sdio-irq; - keep-power-in-suspend; - clock-frequency = <400000000>; - samsung,dw-mshc-ciu-div = <1>; - samsung,dw-mshc-sdr-timing = <0 1>; - samsung,dw-mshc-ddr-timing = <0 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd1_clk>, <&sd1_cmd>, <&sd1_int>, <&sd1_bus1>, - <&sd1_bus4>, <&sd1_bus8>, <&wifi_en>; - bus-width = <4>; - cap-sd-highspeed; - mmc-pwrseq = <&mmc1_pwrseq>; - vqmmc-supply = <&buck10_reg>; -}; - -/* uSD card */ -&mmc_2 { - status = "okay"; - cap-sd-highspeed; - card-detect-delay = <200>; - clock-frequency = <400000000>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>; - bus-width = <4>; -}; - - -&pinctrl_0 { - pinctrl-names = "default"; - pinctrl-0 = <&mask_tpm_reset>; - - wifi_en: wifi-en { - samsung,pins = "gpx0-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - max98090_irq: max98090-irq { - samsung,pins = "gpx0-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - /* We need GPX0_6 to be low at sleep time; just keep it low always */ - mask_tpm_reset: mask-tpm-reset { - samsung,pins = "gpx0-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - samsung,pin-val = <0>; - }; - - tpm_irq: tpm-irq { - samsung,pins = "gpx1-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - trackpad_irq: trackpad-irq { - samsung,pins = "gpx1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - power_key_irq: power-key-irq { - samsung,pins = "gpx1-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - ec_irq: ec-irq { - samsung,pins = "gpx1-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - tps65090_irq: tps65090-irq { - samsung,pins = "gpx2-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - dp_hpd_gpio: dp_hpd_gpio { - samsung,pins = "gpx2-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - max77802_irq: max77802-irq { - samsung,pins = "gpx3-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - lid_irq: lid-irq { - samsung,pins = "gpx3-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - hdmi_hpd_irq: hdmi-hpd-irq { - samsung,pins = "gpx3-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pmic_dvs_1: pmic-dvs-1 { - samsung,pins = "gpy7-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pinctrl_1 { - /* Adjust WiFi drive strengths lower for EMI */ - sd1_clk: sd1-clk { - samsung,pin-drv = ; - }; - - sd1_cmd: sd1-cmd { - samsung,pin-drv = ; - }; - - sd1_bus1: sd1-bus-width1 { - samsung,pin-drv = ; - }; - - sd1_bus4: sd1-bus-width4 { - samsung,pin-drv = ; - }; - - sd1_bus8: sd1-bus-width8 { - samsung,pin-drv = ; - }; -}; - -&pinctrl_2 { - pmic_dvs_2: pmic-dvs-2 { - samsung,pins = "gpj4-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pmic_dvs_3: pmic-dvs-3 { - samsung,pins = "gpj4-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pinctrl_3 { - /* Drive SPI lines at x2 for better integrity */ - spi2-bus { - samsung,pin-drv = ; - }; - - /* Drive SPI chip select at x2 for better integrity */ - ec_spi_cs: ec-spi-cs { - samsung,pins = "gpb1-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - usb300_vbus_en: usb300-vbus-en { - samsung,pins = "gph0-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - usb301_vbus_en: usb301-vbus-en { - samsung,pins = "gph0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pmic_selb: pmic-selb { - samsung,pins = "gph0-2", "gph0-3", "gph0-4", "gph0-5", - "gph0-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pmu_system_controller { - assigned-clocks = <&pmu_system_controller 0>; - assigned-clock-parents = <&clock CLK_FIN_PLL>; -}; - -&rtc { - status = "okay"; - clocks = <&clock CLK_RTC>, <&max77802 MAX77802_CLK_32K_AP>; - clock-names = "rtc", "rtc_src"; -}; - -&spi_2 { - status = "okay"; - num-cs = <1>; - samsung,spi-src-clk = <0>; - cs-gpios = <&gpb1 2 GPIO_ACTIVE_HIGH>; - - cros_ec: cros-ec@0 { - compatible = "google,cros-ec-spi"; - interrupt-parent = <&gpx1>; - interrupts = <5 IRQ_TYPE_NONE>; - pinctrl-names = "default"; - pinctrl-0 = <&ec_spi_cs &ec_irq>; - reg = <0>; - spi-max-frequency = <3125000>; - google,has-vbc-nvram; - - controller-data { - samsung,spi-feedback-delay = <1>; - }; - - i2c_tunnel: i2c-tunnel { - compatible = "google,cros-ec-i2c-tunnel"; - #address-cells = <1>; - #size-cells = <0>; - google,remote-bus = <0>; - - battery: sbs-battery@b { - compatible = "sbs,sbs-battery"; - reg = <0xb>; - sbs,poll-retry-count = <1>; - sbs,i2c-retry-count = <2>; - }; - - power-regulator@48 { - compatible = "ti,tps65090"; - reg = <0x48>; - - /* - * Config irq to disable internal pulls - * even though we run in polling mode. - */ - pinctrl-names = "default"; - pinctrl-0 = <&tps65090_irq>; - - vsys1-supply = <&vbat>; - vsys2-supply = <&vbat>; - vsys3-supply = <&vbat>; - infet1-supply = <&vbat>; - infet2-supply = <&tps65090_dcdc1>; - infet3-supply = <&tps65090_dcdc2>; - infet4-supply = <&tps65090_dcdc2>; - infet5-supply = <&tps65090_dcdc2>; - infet6-supply = <&tps65090_dcdc2>; - infet7-supply = <&tps65090_dcdc1>; - vsys-l1-supply = <&vbat>; - vsys-l2-supply = <&vbat>; - - regulators { - tps65090_dcdc1: dcdc1 { - ti,enable-ext-control; - }; - tps65090_dcdc2: dcdc2 { - ti,enable-ext-control; - }; - tps65090_dcdc3: dcdc3 { - ti,enable-ext-control; - }; - tps65090_fet1: fet1 { - regulator-name = "vcd_led"; - }; - tps65090_fet2: fet2 { - regulator-name = "video_mid"; - regulator-always-on; - }; - tps65090_fet3: fet3 { - regulator-name = "wwan_r"; - regulator-always-on; - }; - tps65090_fet4: fet4 { - regulator-name = "sdcard"; - regulator-always-on; - }; - tps65090_fet5: fet5 { - regulator-name = "camout"; - regulator-always-on; - }; - tps65090_fet6: fet6 { - regulator-name = "lcd_vdd"; - }; - tps65090_fet7: fet7 { - regulator-name = "video_mid_1a"; - regulator-always-on; - }; - tps65090_ldo1: ldo1 { - }; - tps65090_ldo2: ldo2 { - }; - }; - - charger { - compatible = "ti,tps65090-charger"; - }; - }; - }; - }; -}; - -&serial_3 { - status = "okay"; -}; - -&timer { - arm,cpu-registers-not-fw-configured; -}; - -&tmu_cpu0 { - vtmu-supply = <&ldo10_reg>; -}; - -&tmu_cpu1 { - vtmu-supply = <&ldo10_reg>; -}; - -&tmu_cpu2 { - vtmu-supply = <&ldo10_reg>; -}; - -&tmu_cpu3 { - vtmu-supply = <&ldo10_reg>; -}; - -&tmu_gpu { - vtmu-supply = <&ldo10_reg>; -}; - -&usbdrd_dwc3_0 { - dr_mode = "host"; -}; - -&usbdrd_dwc3_1 { - dr_mode = "host"; -}; - -&usbdrd_phy0 { - vbus-supply = <&usb300_vbus_reg>; -}; - -&usbdrd_phy1 { - vbus-supply = <&usb301_vbus_reg>; -}; - -/* - * Use longest HW watchdog in SoC (32 seconds) since the hardware - * watchdog provides no debugging information (compared to soft/hard - * lockup detectors) and so should be last resort. - */ -&watchdog { - timeout-sec = <32>; -}; - -#include "cros-ec-keyboard.dtsi" -#include "cros-adc-thermistors.dtsi" diff --git a/sys/gnu/dts/arm/exynos5420-pinctrl.dtsi b/sys/gnu/dts/arm/exynos5420-pinctrl.dtsi deleted file mode 100644 index b82af7c8965..00000000000 --- a/sys/gnu/dts/arm/exynos5420-pinctrl.dtsi +++ /dev/null @@ -1,734 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's Exynos5420 SoC pin-mux and pin-config device tree source - * - * Copyright (c) 2013 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Samsung's Exynos5420 SoC pin-mux and pin-config options are listed as device - * tree nodes are listed in this file. - */ - -#include - -&pinctrl_0 { - gpy7: gpy7 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpx0: gpx0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - interrupt-parent = <&combiner>; - #interrupt-cells = <2>; - interrupts = <23 0>, <24 0>, <25 0>, <25 1>, - <26 0>, <26 1>, <27 0>, <27 1>; - }; - - gpx1: gpx1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - interrupt-parent = <&combiner>; - #interrupt-cells = <2>; - interrupts = <28 0>, <28 1>, <29 0>, <29 1>, - <30 0>, <30 1>, <31 0>, <31 1>; - }; - - gpx2: gpx2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpx3: gpx3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - dp_hpd: dp_hpd { - samsung,pins = "gpx0-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - hdmi_cec: hdmi-cec { - samsung,pins = "gpx3-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pinctrl_1 { - gpc0: gpc0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc1: gpc1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc2: gpc2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc3: gpc3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc4: gpc4 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpd1: gpd1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpy0: gpy0 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy1: gpy1 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy2: gpy2 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy3: gpy3 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy4: gpy4 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy5: gpy5 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy6: gpy6 { - gpio-controller; - #gpio-cells = <2>; - }; - - sd0_clk: sd0-clk { - samsung,pins = "gpc0-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_cmd: sd0-cmd { - samsung,pins = "gpc0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_cd: sd0-cd { - samsung,pins = "gpc0-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus1: sd0-bus-width1 { - samsung,pins = "gpc0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus4: sd0-bus-width4 { - samsung,pins = "gpc0-4", "gpc0-5", "gpc0-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus8: sd0-bus-width8 { - samsung,pins = "gpc3-0", "gpc3-1", "gpc3-2", "gpc3-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_rclk: sd0-rclk { - samsung,pins = "gpc0-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_clk: sd1-clk { - samsung,pins = "gpc1-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_cmd: sd1-cmd { - samsung,pins = "gpc1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_cd: sd1-cd { - samsung,pins = "gpc1-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_int: sd1-int { - samsung,pins = "gpd1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_bus1: sd1-bus-width1 { - samsung,pins = "gpc1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_bus4: sd1-bus-width4 { - samsung,pins = "gpc1-4", "gpc1-5", "gpc1-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_bus8: sd1-bus-width8 { - samsung,pins = "gpd1-4", "gpd1-5", "gpd1-6", "gpd1-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_clk: sd2-clk { - samsung,pins = "gpc2-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_cmd: sd2-cmd { - samsung,pins = "gpc2-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_cd: sd2-cd { - samsung,pins = "gpc2-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_bus1: sd2-bus-width1 { - samsung,pins = "gpc2-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_bus4: sd2-bus-width4 { - samsung,pins = "gpc2-4", "gpc2-5", "gpc2-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_wp: sd2-wp { - samsung,pins = "gpc4-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pinctrl_2 { - gpe0: gpe0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpe1: gpe1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf0: gpf0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf1: gpf1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpg0: gpg0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpg1: gpg1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpg2: gpg2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpj4: gpj4 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - cam_gpio_a: cam-gpio-a { - samsung,pins = "gpe0-0", "gpe0-1", "gpe0-2", "gpe0-3", - "gpe0-4", "gpe0-5", "gpe0-6", "gpe0-7", - "gpe1-0", "gpe1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_gpio_b: cam-gpio-b { - samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3", - "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_i2c2_bus: cam-i2c2-bus { - samsung,pins = "gpf0-4", "gpf0-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_spi1_bus: cam-spi1-bus { - samsung,pins = "gpe0-4", "gpe0-5", "gpf0-2", "gpf0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_i2c1_bus: cam-i2c1-bus { - samsung,pins = "gpf0-2", "gpf0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_i2c0_bus: cam-i2c0-bus { - samsung,pins = "gpf0-0", "gpf0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_spi0_bus: cam-spi0-bus { - samsung,pins = "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_bayrgb_bus: cam-bayrgb-bus { - samsung,pins = "gpg0-0", "gpg0-1", "gpg0-2", "gpg0-3", - "gpg0-4", "gpg0-5", "gpg0-6", "gpg0-7", - "gpg1-0", "gpg1-1", "gpg1-2", "gpg1-3", - "gpg1-4", "gpg1-5", "gpg1-6", "gpg1-7", - "gpg2-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pinctrl_3 { - gpa0: gpa0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpa1: gpa1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpa2: gpa2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpb0: gpb0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpb1: gpb1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpb2: gpb2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpb3: gpb3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpb4: gpb4 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gph0: gph0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - uart0_data: uart0-data { - samsung,pins = "gpa0-0", "gpa0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart0_fctl: uart0-fctl { - samsung,pins = "gpa0-2", "gpa0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart1_data: uart1-data { - samsung,pins = "gpa0-4", "gpa0-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart1_fctl: uart1-fctl { - samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c2_bus: i2c2-bus { - samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart2_data: uart2-data { - samsung,pins = "gpa1-0", "gpa1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart2_fctl: uart2-fctl { - samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c3_bus: i2c3-bus { - samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart3_data: uart3-data { - samsung,pins = "gpa1-4", "gpa1-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spi0_bus: spi0-bus { - samsung,pins = "gpa2-0", "gpa2-1", "gpa2-2", "gpa2-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spi1_bus: spi1-bus { - samsung,pins = "gpa2-4", "gpa2-6", "gpa2-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c4_hs_bus: i2c4-hs-bus { - samsung,pins = "gpa2-0", "gpa2-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c5_hs_bus: i2c5-hs-bus { - samsung,pins = "gpa2-2", "gpa2-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2s1_bus: i2s1-bus { - samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3", - "gpb0-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pcm1_bus: pcm1-bus { - samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3", - "gpb0-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2s2_bus: i2s2-bus { - samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3", - "gpb1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pcm2_bus: pcm2-bus { - samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3", - "gpb1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spdif_bus: spdif-bus { - samsung,pins = "gpb1-0", "gpb1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spi2_bus: spi2-bus { - samsung,pins = "gpb1-1", "gpb1-3", "gpb1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c6_hs_bus: i2c6-hs-bus { - samsung,pins = "gpb1-3", "gpb1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm0_out: pwm0-out { - samsung,pins = "gpb2-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm1_out: pwm1-out { - samsung,pins = "gpb2-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm2_out: pwm2-out { - samsung,pins = "gpb2-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm3_out: pwm3-out { - samsung,pins = "gpb2-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c7_hs_bus: i2c7-hs-bus { - samsung,pins = "gpb2-2", "gpb2-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c0_bus: i2c0-bus { - samsung,pins = "gpb3-0", "gpb3-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c1_bus: i2c1-bus { - samsung,pins = "gpb3-2", "gpb3-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c8_hs_bus: i2c8-hs-bus { - samsung,pins = "gpb3-4", "gpb3-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c9_hs_bus: i2c9-hs-bus { - samsung,pins = "gpb3-6", "gpb3-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c10_hs_bus: i2c10-hs-bus { - samsung,pins = "gpb4-0", "gpb4-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pinctrl_4 { - gpz: gpz { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - i2s0_bus: i2s0-bus { - samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", - "gpz-4", "gpz-5", "gpz-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; diff --git a/sys/gnu/dts/arm/exynos5420-smdk5420.dts b/sys/gnu/dts/arm/exynos5420-smdk5420.dts deleted file mode 100644 index e3f2afe8359..00000000000 --- a/sys/gnu/dts/arm/exynos5420-smdk5420.dts +++ /dev/null @@ -1,421 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung SMDK5420 board device tree source - * - * Copyright (c) 2013 Samsung Electronics Co., Ltd. - * http://www.samsung.com - */ - -/dts-v1/; -#include "exynos5420.dtsi" -#include "exynos5420-cpus.dtsi" -#include - -/ { - model = "Samsung SMDK5420 board based on Exynos5420"; - compatible = "samsung,smdk5420", "samsung,exynos5420", "samsung,exynos5"; - - memory@20000000 { - device_type = "memory"; - reg = <0x20000000 0x80000000>; - }; - - chosen { - bootargs = "init=/linuxrc"; - stdout-path = "serial2:115200n8"; - }; - - fixed-rate-clocks { - oscclk { - compatible = "samsung,exynos5420-oscclk"; - clock-frequency = <24000000>; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - vdd: fixed-regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "vdd-supply"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - dbvdd: fixed-regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "dbvdd-supply"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - spkvdd: fixed-regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "spkvdd-supply"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - }; - - usb300_vbus_reg: regulator-usb300 { - compatible = "regulator-fixed"; - regulator-name = "VBUS0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpg0 5 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&usb300_vbus_en>; - enable-active-high; - }; - - usb301_vbus_reg: regulator-usb301 { - compatible = "regulator-fixed"; - regulator-name = "VBUS1"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpg1 4 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&usb301_vbus_en>; - enable-active-high; - }; - -}; - -&cpu0 { - cpu-supply = <&buck2_reg>; -}; - -&cpu4 { - cpu-supply = <&buck6_reg>; -}; - -&dp { - pinctrl-names = "default"; - pinctrl-0 = <&dp_hpd>; - samsung,color-space = <0>; - samsung,color-depth = <1>; - samsung,link-rate = <0x0a>; - samsung,lane-count = <4>; - status = "okay"; - - display-timings { - native-mode = <&timing0>; - timing0: timing { - clock-frequency = <50000>; - hactive = <2560>; - vactive = <1600>; - hfront-porch = <48>; - hback-porch = <80>; - hsync-len = <32>; - vback-porch = <16>; - vfront-porch = <8>; - vsync-len = <6>; - }; - }; -}; - -&fimd { - status = "okay"; -}; - -&hdmi { - status = "okay"; - ddc = <&i2c_2>; - hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_hpd_irq>; -}; - -&hsi2c_4 { - status = "okay"; - - s2mps11_pmic@66 { - compatible = "samsung,s2mps11-pmic"; - reg = <0x66>; - - s2mps11_osc: clocks { - compatible = "samsung,s2mps11-clk"; - #clock-cells = <1>; - clock-output-names = "s2mps11_ap", - "s2mps11_cp", "s2mps11_bt"; - }; - - regulators { - ldo1_reg: LDO1 { - regulator-name = "vdd_ldo1"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo3_reg: LDO3 { - regulator-name = "vdd_ldo3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo5_reg: LDO5 { - regulator-name = "vdd_ldo5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo6_reg: LDO6 { - regulator-name = "vdd_ldo6"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo7_reg: LDO7 { - regulator-name = "vdd_ldo7"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo8_reg: LDO8 { - regulator-name = "vdd_ldo8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo9_reg: LDO9 { - regulator-name = "vdd_ldo9"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - }; - - ldo10_reg: LDO10 { - regulator-name = "vdd_ldo10"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo11_reg: LDO11 { - regulator-name = "vdd_ldo11"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo12_reg: LDO12 { - regulator-name = "vdd_ldo12"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo13_reg: LDO13 { - regulator-name = "vdd_ldo13"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - ldo15_reg: LDO15 { - regulator-name = "vdd_ldo15"; - regulator-min-microvolt = <3100000>; - regulator-max-microvolt = <3100000>; - regulator-always-on; - }; - - ldo16_reg: LDO16 { - regulator-name = "vdd_ldo16"; - regulator-min-microvolt = <2200000>; - regulator-max-microvolt = <2200000>; - regulator-always-on; - }; - - ldo17_reg: LDO17 { - regulator-name = "tsp_avdd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo19_reg: LDO19 { - regulator-name = "vdd_sd"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - ldo24_reg: LDO24 { - regulator-name = "tsp_io"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - buck1_reg: BUCK1 { - regulator-name = "vdd_mif"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - }; - - buck2_reg: BUCK2 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - }; - - buck3_reg: BUCK3 { - regulator-name = "vdd_int"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-boot-on; - }; - - buck4_reg: BUCK4 { - regulator-name = "vdd_g3d"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-boot-on; - }; - - buck5_reg: BUCK5 { - regulator-name = "vdd_mem"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-boot-on; - }; - - buck6_reg: BUCK6 { - regulator-name = "vdd_kfc"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - }; - - buck7_reg: BUCK7 { - regulator-name = "vdd_1.0v_ldo"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - }; - - buck8_reg: BUCK8 { - regulator-name = "vdd_1.8v_ldo"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - }; - - buck9_reg: BUCK9 { - regulator-name = "vdd_2.8v_ldo"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3750000>; - regulator-always-on; - regulator-boot-on; - }; - - buck10_reg: BUCK10 { - regulator-name = "vdd_vmem"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - regulator-always-on; - regulator-boot-on; - }; - }; - }; -}; - -&i2c_2 { - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <66000>; - /* used by HDMI DDC */ - status = "okay"; -}; - -&mixer { - status = "okay"; -}; - -&mmc_0 { - status = "okay"; - broken-cd; - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <0 4>; - samsung,dw-mshc-ddr-timing = <0 2>; - samsung,dw-mshc-hs400-timing = <0 2>; - samsung,read-strobe-delay = <90>; - pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8 - &sd0_rclk>; - bus-width = <8>; - cap-mmc-highspeed; -}; - -&mmc_2 { - status = "okay"; - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>; - bus-width = <4>; - cap-sd-highspeed; -}; - -&pinctrl_0 { - hdmi_hpd_irq: hdmi-hpd-irq { - samsung,pins = "gpx3-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pinctrl_2 { - usb300_vbus_en: usb300-vbus-en { - samsung,pins = "gpg0-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - usb301_vbus_en: usb301-vbus-en { - samsung,pins = "gpg1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&rtc { - status = "okay"; -}; - -&usbdrd_phy0 { - vbus-supply = <&usb300_vbus_reg>; -}; - -&usbdrd_phy1 { - vbus-supply = <&usb301_vbus_reg>; -}; diff --git a/sys/gnu/dts/arm/exynos5420-trip-points.dtsi b/sys/gnu/dts/arm/exynos5420-trip-points.dtsi deleted file mode 100644 index a67a380717e..00000000000 --- a/sys/gnu/dts/arm/exynos5420-trip-points.dtsi +++ /dev/null @@ -1,31 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device tree sources for default Exynos5420 thermal zone definition - * - * Copyright (c) 2014 Lukasz Majewski - */ - -polling-delay-passive = <0>; -polling-delay = <0>; -trips { - cpu-alert-0 { - temperature = <85000>; /* millicelsius */ - hysteresis = <10000>; /* millicelsius */ - type = "active"; - }; - cpu-alert-1 { - temperature = <103000>; /* millicelsius */ - hysteresis = <10000>; /* millicelsius */ - type = "active"; - }; - cpu-alert-2 { - temperature = <110000>; /* millicelsius */ - hysteresis = <10000>; /* millicelsius */ - type = "active"; - }; - cpu-crit-0 { - temperature = <120000>; /* millicelsius */ - hysteresis = <0>; /* millicelsius */ - type = "critical"; - }; -}; diff --git a/sys/gnu/dts/arm/exynos5420.dtsi b/sys/gnu/dts/arm/exynos5420.dtsi deleted file mode 100644 index b672080e746..00000000000 --- a/sys/gnu/dts/arm/exynos5420.dtsi +++ /dev/null @@ -1,1424 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung Exynos5420 SoC device tree source - * - * Copyright (c) 2013 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Samsung Exynos5420 SoC device nodes are listed in this file. - * Exynos5420 based board files can include this file and provide - * values for board specfic bindings. - */ - -#include "exynos54xx.dtsi" -#include -#include -#include - -/ { - compatible = "samsung,exynos5420", "samsung,exynos5"; - - aliases { - mshc0 = &mmc_0; - mshc1 = &mmc_1; - mshc2 = &mmc_2; - pinctrl0 = &pinctrl_0; - pinctrl1 = &pinctrl_1; - pinctrl2 = &pinctrl_2; - pinctrl3 = &pinctrl_3; - pinctrl4 = &pinctrl_4; - i2c8 = &hsi2c_8; - i2c9 = &hsi2c_9; - i2c10 = &hsi2c_10; - gsc0 = &gsc_0; - gsc1 = &gsc_1; - spi0 = &spi_0; - spi1 = &spi_1; - spi2 = &spi_2; - }; - - /* - * The 'cpus' node is not present here but instead it is provided - * by exynos5420-cpus.dtsi or exynos5422-cpus.dtsi. - */ - - cluster_a15_opp_table: opp_table0 { - compatible = "operating-points-v2"; - opp-shared; - - opp-1800000000 { - opp-hz = /bits/ 64 <1800000000>; - opp-microvolt = <1250000 1250000 1500000>; - clock-latency-ns = <140000>; - }; - opp-1700000000 { - opp-hz = /bits/ 64 <1700000000>; - opp-microvolt = <1212500 1212500 1500000>; - clock-latency-ns = <140000>; - }; - opp-1600000000 { - opp-hz = /bits/ 64 <1600000000>; - opp-microvolt = <1175000 1175000 1500000>; - clock-latency-ns = <140000>; - }; - opp-1500000000 { - opp-hz = /bits/ 64 <1500000000>; - opp-microvolt = <1137500 1137500 1500000>; - clock-latency-ns = <140000>; - }; - opp-1400000000 { - opp-hz = /bits/ 64 <1400000000>; - opp-microvolt = <1112500 1112500 1500000>; - clock-latency-ns = <140000>; - }; - opp-1300000000 { - opp-hz = /bits/ 64 <1300000000>; - opp-microvolt = <1062500 1062500 1500000>; - clock-latency-ns = <140000>; - }; - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <1037500 1037500 1500000>; - clock-latency-ns = <140000>; - }; - opp-1100000000 { - opp-hz = /bits/ 64 <1100000000>; - opp-microvolt = <1012500 1012500 1500000>; - clock-latency-ns = <140000>; - }; - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = < 987500 987500 1500000>; - clock-latency-ns = <140000>; - }; - opp-900000000 { - opp-hz = /bits/ 64 <900000000>; - opp-microvolt = < 962500 962500 1500000>; - clock-latency-ns = <140000>; - }; - opp-800000000 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = < 937500 937500 1500000>; - clock-latency-ns = <140000>; - }; - opp-700000000 { - opp-hz = /bits/ 64 <700000000>; - opp-microvolt = < 912500 912500 1500000>; - clock-latency-ns = <140000>; - }; - }; - - cluster_a7_opp_table: opp_table1 { - compatible = "operating-points-v2"; - opp-shared; - - opp-1300000000 { - opp-hz = /bits/ 64 <1300000000>; - opp-microvolt = <1275000>; - clock-latency-ns = <140000>; - }; - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <1212500>; - clock-latency-ns = <140000>; - }; - opp-1100000000 { - opp-hz = /bits/ 64 <1100000000>; - opp-microvolt = <1162500>; - clock-latency-ns = <140000>; - }; - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <1112500>; - clock-latency-ns = <140000>; - }; - opp-900000000 { - opp-hz = /bits/ 64 <900000000>; - opp-microvolt = <1062500>; - clock-latency-ns = <140000>; - }; - opp-800000000 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <1025000>; - clock-latency-ns = <140000>; - }; - opp-700000000 { - opp-hz = /bits/ 64 <700000000>; - opp-microvolt = <975000>; - clock-latency-ns = <140000>; - }; - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <937500>; - clock-latency-ns = <140000>; - }; - }; - - soc: soc { - cci: cci@10d20000 { - compatible = "arm,cci-400"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x10d20000 0x1000>; - ranges = <0x0 0x10d20000 0x6000>; - - cci_control0: slave-if@4000 { - compatible = "arm,cci-400-ctrl-if"; - interface-type = "ace"; - reg = <0x4000 0x1000>; - }; - cci_control1: slave-if@5000 { - compatible = "arm,cci-400-ctrl-if"; - interface-type = "ace"; - reg = <0x5000 0x1000>; - }; - }; - - clock: clock-controller@10010000 { - compatible = "samsung,exynos5420-clock", "syscon"; - reg = <0x10010000 0x30000>; - #clock-cells = <1>; - }; - - clock_audss: audss-clock-controller@3810000 { - compatible = "samsung,exynos5420-audss-clock"; - reg = <0x03810000 0x0C>; - #clock-cells = <1>; - clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MAU_EPLL>, - <&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>; - clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in"; - power-domains = <&mau_pd>; - }; - - mfc: codec@11000000 { - compatible = "samsung,mfc-v7"; - reg = <0x11000000 0x10000>; - interrupts = ; - clocks = <&clock CLK_MFC>; - clock-names = "mfc"; - power-domains = <&mfc_pd>; - iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>; - iommu-names = "left", "right"; - }; - - mmc_0: mmc@12200000 { - compatible = "samsung,exynos5420-dw-mshc-smu"; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x12200000 0x2000>; - clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>; - clock-names = "biu", "ciu"; - fifo-depth = <0x40>; - status = "disabled"; - }; - - mmc_1: mmc@12210000 { - compatible = "samsung,exynos5420-dw-mshc-smu"; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x12210000 0x2000>; - clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>; - clock-names = "biu", "ciu"; - fifo-depth = <0x40>; - status = "disabled"; - }; - - mmc_2: mmc@12220000 { - compatible = "samsung,exynos5420-dw-mshc"; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x12220000 0x1000>; - clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>; - clock-names = "biu", "ciu"; - fifo-depth = <0x40>; - status = "disabled"; - }; - - dmc: memory-controller@10c20000 { - compatible = "samsung,exynos5422-dmc"; - reg = <0x10c20000 0x10000>, <0x10c30000 0x10000>; - interrupt-parent = <&combiner>; - interrupts = <16 0>, <16 1>; - interrupt-names = "drex_0", "drex_1"; - clocks = <&clock CLK_FOUT_SPLL>, - <&clock CLK_MOUT_SCLK_SPLL>, - <&clock CLK_FF_DOUT_SPLL2>, - <&clock CLK_FOUT_BPLL>, - <&clock CLK_MOUT_BPLL>, - <&clock CLK_SCLK_BPLL>, - <&clock CLK_MOUT_MX_MSPLL_CCORE>, - <&clock CLK_MOUT_MCLK_CDREX>; - clock-names = "fout_spll", - "mout_sclk_spll", - "ff_dout_spll2", - "fout_bpll", - "mout_bpll", - "sclk_bpll", - "mout_mx_mspll_ccore", - "mout_mclk_cdrex"; - samsung,syscon-clk = <&clock>; - status = "disabled"; - }; - - nocp_mem0_0: nocp@10ca1000 { - compatible = "samsung,exynos5420-nocp"; - reg = <0x10CA1000 0x200>; - status = "disabled"; - }; - - nocp_mem0_1: nocp@10ca1400 { - compatible = "samsung,exynos5420-nocp"; - reg = <0x10CA1400 0x200>; - status = "disabled"; - }; - - nocp_mem1_0: nocp@10ca1800 { - compatible = "samsung,exynos5420-nocp"; - reg = <0x10CA1800 0x200>; - status = "disabled"; - }; - - nocp_mem1_1: nocp@10ca1c00 { - compatible = "samsung,exynos5420-nocp"; - reg = <0x10CA1C00 0x200>; - status = "disabled"; - }; - - nocp_g3d_0: nocp@11a51000 { - compatible = "samsung,exynos5420-nocp"; - reg = <0x11A51000 0x200>; - status = "disabled"; - }; - - nocp_g3d_1: nocp@11a51400 { - compatible = "samsung,exynos5420-nocp"; - reg = <0x11A51400 0x200>; - status = "disabled"; - }; - - ppmu_dmc0_0: ppmu@10d00000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x10d00000 0x2000>; - clocks = <&clock CLK_PCLK_PPMU_DREX0_0>; - clock-names = "ppmu"; - events { - ppmu_event3_dmc0_0: ppmu-event3-dmc0_0 { - event-name = "ppmu-event3-dmc0_0"; - }; - }; - }; - - ppmu_dmc0_1: ppmu@10d10000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x10d10000 0x2000>; - clocks = <&clock CLK_PCLK_PPMU_DREX0_1>; - clock-names = "ppmu"; - events { - ppmu_event3_dmc0_1: ppmu-event3-dmc0_1 { - event-name = "ppmu-event3-dmc0_1"; - }; - }; - }; - - ppmu_dmc1_0: ppmu@10d60000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x10d60000 0x2000>; - clocks = <&clock CLK_PCLK_PPMU_DREX1_0>; - clock-names = "ppmu"; - events { - ppmu_event3_dmc1_0: ppmu-event3-dmc1_0 { - event-name = "ppmu-event3-dmc1_0"; - }; - }; - }; - - ppmu_dmc1_1: ppmu@10d70000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x10d70000 0x2000>; - clocks = <&clock CLK_PCLK_PPMU_DREX1_1>; - clock-names = "ppmu"; - events { - ppmu_event3_dmc1_1: ppmu-event3-dmc1_1 { - event-name = "ppmu-event3-dmc1_1"; - }; - }; - }; - - gsc_pd: power-domain@10044000 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10044000 0x20>; - #power-domain-cells = <0>; - label = "GSC"; - }; - - isp_pd: power-domain@10044020 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10044020 0x20>; - #power-domain-cells = <0>; - label = "ISP"; - }; - - mfc_pd: power-domain@10044060 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10044060 0x20>; - #power-domain-cells = <0>; - label = "MFC"; - }; - - g3d_pd: power-domain@10044080 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10044080 0x20>; - #power-domain-cells = <0>; - label = "G3D"; - }; - - disp_pd: power-domain@100440c0 { - compatible = "samsung,exynos4210-pd"; - reg = <0x100440C0 0x20>; - #power-domain-cells = <0>; - label = "DISP"; - }; - - mau_pd: power-domain@100440e0 { - compatible = "samsung,exynos4210-pd"; - reg = <0x100440E0 0x20>; - #power-domain-cells = <0>; - label = "MAU"; - }; - - msc_pd: power-domain@10044120 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10044120 0x20>; - #power-domain-cells = <0>; - label = "MSC"; - }; - - pinctrl_0: pinctrl@13400000 { - compatible = "samsung,exynos5420-pinctrl"; - reg = <0x13400000 0x1000>; - interrupts = ; - - wakeup-interrupt-controller { - compatible = "samsung,exynos4210-wakeup-eint"; - interrupt-parent = <&gic>; - interrupts = ; - }; - }; - - pinctrl_1: pinctrl@13410000 { - compatible = "samsung,exynos5420-pinctrl"; - reg = <0x13410000 0x1000>; - interrupts = ; - }; - - pinctrl_2: pinctrl@14000000 { - compatible = "samsung,exynos5420-pinctrl"; - reg = <0x14000000 0x1000>; - interrupts = ; - }; - - pinctrl_3: pinctrl@14010000 { - compatible = "samsung,exynos5420-pinctrl"; - reg = <0x14010000 0x1000>; - interrupts = ; - }; - - pinctrl_4: pinctrl@3860000 { - compatible = "samsung,exynos5420-pinctrl"; - reg = <0x03860000 0x1000>; - interrupts = ; - power-domains = <&mau_pd>; - }; - - amba { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&gic>; - ranges; - - adma: adma@3880000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x03880000 0x1000>; - interrupts = ; - clocks = <&clock_audss EXYNOS_ADMA>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <6>; - #dma-requests = <16>; - power-domains = <&mau_pd>; - }; - - pdma0: pdma@121a0000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x121A0000 0x1000>; - interrupts = ; - clocks = <&clock CLK_PDMA0>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; - }; - - pdma1: pdma@121b0000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x121B0000 0x1000>; - interrupts = ; - clocks = <&clock CLK_PDMA1>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; - }; - - mdma0: mdma@10800000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x10800000 0x1000>; - interrupts = ; - clocks = <&clock CLK_MDMA0>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <1>; - }; - - mdma1: mdma@11c10000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x11C10000 0x1000>; - interrupts = ; - clocks = <&clock CLK_MDMA1>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <1>; - /* - * MDMA1 can support both secure and non-secure - * AXI transactions. When this is enabled in - * the kernel for boards that run in secure - * mode, we are getting imprecise external - * aborts causing the kernel to oops. - */ - status = "disabled"; - }; - }; - - i2s0: i2s@3830000 { - compatible = "samsung,exynos5420-i2s"; - reg = <0x03830000 0x100>; - dmas = <&adma 0>, - <&adma 2>, - <&adma 1>; - dma-names = "tx", "rx", "tx-sec"; - clocks = <&clock_audss EXYNOS_I2S_BUS>, - <&clock_audss EXYNOS_I2S_BUS>, - <&clock_audss EXYNOS_SCLK_I2S>; - clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; - #clock-cells = <1>; - clock-output-names = "i2s_cdclk0"; - #sound-dai-cells = <1>; - samsung,idma-addr = <0x03000000>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_bus>; - power-domains = <&mau_pd>; - status = "disabled"; - }; - - i2s1: i2s@12d60000 { - compatible = "samsung,exynos5420-i2s"; - reg = <0x12D60000 0x100>; - dmas = <&pdma1 12>, - <&pdma1 11>; - dma-names = "tx", "rx"; - clocks = <&clock CLK_I2S1>, <&clock CLK_SCLK_I2S1>; - clock-names = "iis", "i2s_opclk0"; - #clock-cells = <1>; - clock-output-names = "i2s_cdclk1"; - #sound-dai-cells = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s1_bus>; - status = "disabled"; - }; - - i2s2: i2s@12d70000 { - compatible = "samsung,exynos5420-i2s"; - reg = <0x12D70000 0x100>; - dmas = <&pdma0 12>, - <&pdma0 11>; - dma-names = "tx", "rx"; - clocks = <&clock CLK_I2S2>, <&clock CLK_SCLK_I2S2>; - clock-names = "iis", "i2s_opclk0"; - #clock-cells = <1>; - clock-output-names = "i2s_cdclk2"; - #sound-dai-cells = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s2_bus>; - status = "disabled"; - }; - - spi_0: spi@12d20000 { - compatible = "samsung,exynos4210-spi"; - reg = <0x12d20000 0x100>; - interrupts = ; - dmas = <&pdma0 5 - &pdma0 4>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_bus>; - clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>; - clock-names = "spi", "spi_busclk0"; - status = "disabled"; - }; - - spi_1: spi@12d30000 { - compatible = "samsung,exynos4210-spi"; - reg = <0x12d30000 0x100>; - interrupts = ; - dmas = <&pdma1 5 - &pdma1 4>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&spi1_bus>; - clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>; - clock-names = "spi", "spi_busclk0"; - status = "disabled"; - }; - - spi_2: spi@12d40000 { - compatible = "samsung,exynos4210-spi"; - reg = <0x12d40000 0x100>; - interrupts = ; - dmas = <&pdma0 7 - &pdma0 6>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&spi2_bus>; - clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>; - clock-names = "spi", "spi_busclk0"; - status = "disabled"; - }; - - dp_phy: dp-video-phy { - compatible = "samsung,exynos5420-dp-video-phy"; - samsung,pmu-syscon = <&pmu_system_controller>; - #phy-cells = <0>; - }; - - mipi_phy: mipi-video-phy { - compatible = "samsung,s5pv210-mipi-video-phy"; - syscon = <&pmu_system_controller>; - #phy-cells = <1>; - }; - - dsi@14500000 { - compatible = "samsung,exynos5410-mipi-dsi"; - reg = <0x14500000 0x10000>; - interrupts = ; - phys = <&mipi_phy 1>; - phy-names = "dsim"; - clocks = <&clock CLK_DSIM1>, <&clock CLK_SCLK_MIPI1>; - clock-names = "bus_clk", "pll_clk"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - hsi2c_8: i2c@12e00000 { - compatible = "samsung,exynos5250-hsi2c"; - reg = <0x12E00000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c8_hs_bus>; - clocks = <&clock CLK_USI4>; - clock-names = "hsi2c"; - status = "disabled"; - }; - - hsi2c_9: i2c@12e10000 { - compatible = "samsung,exynos5250-hsi2c"; - reg = <0x12E10000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c9_hs_bus>; - clocks = <&clock CLK_USI5>; - clock-names = "hsi2c"; - status = "disabled"; - }; - - hsi2c_10: i2c@12e20000 { - compatible = "samsung,exynos5250-hsi2c"; - reg = <0x12E20000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c10_hs_bus>; - clocks = <&clock CLK_USI6>; - clock-names = "hsi2c"; - status = "disabled"; - }; - - hdmi: hdmi@14530000 { - compatible = "samsung,exynos5420-hdmi"; - reg = <0x14530000 0x70000>; - interrupts = ; - clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>, - <&clock CLK_DOUT_PIXEL>, <&clock CLK_SCLK_HDMIPHY>, - <&clock CLK_MOUT_HDMI>; - clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", - "sclk_hdmiphy", "mout_hdmi"; - phy = <&hdmiphy>; - samsung,syscon-phandle = <&pmu_system_controller>; - status = "disabled"; - power-domains = <&disp_pd>; - #sound-dai-cells = <0>; - }; - - hdmiphy: hdmiphy@145d0000 { - reg = <0x145D0000 0x20>; - }; - - hdmicec: cec@101b0000 { - compatible = "samsung,s5p-cec"; - reg = <0x101B0000 0x200>; - interrupts = ; - clocks = <&clock CLK_HDMI_CEC>; - clock-names = "hdmicec"; - samsung,syscon-phandle = <&pmu_system_controller>; - hdmi-phandle = <&hdmi>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_cec>; - status = "disabled"; - }; - - mixer: mixer@14450000 { - compatible = "samsung,exynos5420-mixer"; - reg = <0x14450000 0x10000>; - interrupts = ; - clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>, - <&clock CLK_SCLK_HDMI>; - clock-names = "mixer", "hdmi", "sclk_hdmi"; - power-domains = <&disp_pd>; - iommus = <&sysmmu_tv>; - status = "disabled"; - }; - - rotator: rotator@11c00000 { - compatible = "samsung,exynos5250-rotator"; - reg = <0x11C00000 0x64>; - interrupts = ; - clocks = <&clock CLK_ROTATOR>; - clock-names = "rotator"; - iommus = <&sysmmu_rotator>; - }; - - gsc_0: video-scaler@13e00000 { - compatible = "samsung,exynos5420-gsc", "samsung,exynos5-gsc"; - reg = <0x13e00000 0x1000>; - interrupts = ; - clocks = <&clock CLK_GSCL0>; - clock-names = "gscl"; - power-domains = <&gsc_pd>; - iommus = <&sysmmu_gscl0>; - }; - - gsc_1: video-scaler@13e10000 { - compatible = "samsung,exynos5420-gsc", "samsung,exynos5-gsc"; - reg = <0x13e10000 0x1000>; - interrupts = ; - clocks = <&clock CLK_GSCL1>; - clock-names = "gscl"; - power-domains = <&gsc_pd>; - iommus = <&sysmmu_gscl1>; - }; - - gpu: gpu@11800000 { - compatible = "samsung,exynos5420-mali", "arm,mali-t628"; - reg = <0x11800000 0x5000>; - interrupts = , - , - ; - interrupt-names = "job", "mmu", "gpu"; - - clocks = <&clock CLK_G3D>; - clock-names = "core"; - power-domains = <&g3d_pd>; - operating-points-v2 = <&gpu_opp_table>; - - status = "disabled"; - #cooling-cells = <2>; - - gpu_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-177000000 { - opp-hz = /bits/ 64 <177000000>; - opp-microvolt = <812500>; - }; - opp-266000000 { - opp-hz = /bits/ 64 <266000000>; - opp-microvolt = <862500>; - }; - opp-350000000 { - opp-hz = /bits/ 64 <350000000>; - opp-microvolt = <912500>; - }; - opp-420000000 { - opp-hz = /bits/ 64 <420000000>; - opp-microvolt = <962500>; - }; - opp-480000000 { - opp-hz = /bits/ 64 <480000000>; - opp-microvolt = <1000000>; - }; - opp-543000000 { - opp-hz = /bits/ 64 <543000000>; - opp-microvolt = <1037500>; - }; - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <1150000>; - }; - }; - }; - - scaler_0: scaler@12800000 { - compatible = "samsung,exynos5420-scaler"; - reg = <0x12800000 0x1294>; - interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clock CLK_MSCL0>; - clock-names = "mscl"; - power-domains = <&msc_pd>; - iommus = <&sysmmu_scaler0r>, <&sysmmu_scaler0w>; - }; - - scaler_1: scaler@12810000 { - compatible = "samsung,exynos5420-scaler"; - reg = <0x12810000 0x1294>; - interrupts = <0 221 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clock CLK_MSCL1>; - clock-names = "mscl"; - power-domains = <&msc_pd>; - iommus = <&sysmmu_scaler1r>, <&sysmmu_scaler1w>; - }; - - scaler_2: scaler@12820000 { - compatible = "samsung,exynos5420-scaler"; - reg = <0x12820000 0x1294>; - interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clock CLK_MSCL2>; - clock-names = "mscl"; - power-domains = <&msc_pd>; - iommus = <&sysmmu_scaler2r>, <&sysmmu_scaler2w>; - }; - - jpeg_0: jpeg@11f50000 { - compatible = "samsung,exynos5420-jpeg"; - reg = <0x11F50000 0x1000>; - interrupts = ; - clock-names = "jpeg"; - clocks = <&clock CLK_JPEG>; - iommus = <&sysmmu_jpeg0>; - }; - - jpeg_1: jpeg@11f60000 { - compatible = "samsung,exynos5420-jpeg"; - reg = <0x11F60000 0x1000>; - interrupts = ; - clock-names = "jpeg"; - clocks = <&clock CLK_JPEG2>; - iommus = <&sysmmu_jpeg1>; - }; - - pmu_system_controller: system-controller@10040000 { - compatible = "samsung,exynos5420-pmu", "syscon"; - reg = <0x10040000 0x5000>; - clock-names = "clkout16"; - clocks = <&clock CLK_FIN_PLL>; - #clock-cells = <1>; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - }; - - tmu_cpu0: tmu@10060000 { - compatible = "samsung,exynos5420-tmu"; - reg = <0x10060000 0x100>; - interrupts = ; - clocks = <&clock CLK_TMU>; - clock-names = "tmu_apbif"; - #thermal-sensor-cells = <0>; - }; - - tmu_cpu1: tmu@10064000 { - compatible = "samsung,exynos5420-tmu"; - reg = <0x10064000 0x100>; - interrupts = ; - clocks = <&clock CLK_TMU>; - clock-names = "tmu_apbif"; - #thermal-sensor-cells = <0>; - }; - - tmu_cpu2: tmu@10068000 { - compatible = "samsung,exynos5420-tmu-ext-triminfo"; - reg = <0x10068000 0x100>, <0x1006c000 0x4>; - interrupts = ; - clocks = <&clock CLK_TMU>, <&clock CLK_TMU>; - clock-names = "tmu_apbif", "tmu_triminfo_apbif"; - #thermal-sensor-cells = <0>; - }; - - tmu_cpu3: tmu@1006c000 { - compatible = "samsung,exynos5420-tmu-ext-triminfo"; - reg = <0x1006c000 0x100>, <0x100a0000 0x4>; - interrupts = ; - clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>; - clock-names = "tmu_apbif", "tmu_triminfo_apbif"; - #thermal-sensor-cells = <0>; - }; - - tmu_gpu: tmu@100a0000 { - compatible = "samsung,exynos5420-tmu-ext-triminfo"; - reg = <0x100a0000 0x100>, <0x10068000 0x4>; - interrupts = ; - clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>; - clock-names = "tmu_apbif", "tmu_triminfo_apbif"; - #thermal-sensor-cells = <0>; - }; - - sysmmu_g2dr: sysmmu@10a60000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x10A60000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <24 5>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>; - #iommu-cells = <0>; - }; - - sysmmu_g2dw: sysmmu@10a70000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x10A70000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <22 2>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>; - #iommu-cells = <0>; - }; - - sysmmu_tv: sysmmu@14650000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x14650000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <7 4>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_MIXER>, <&clock CLK_MIXER>; - power-domains = <&disp_pd>; - #iommu-cells = <0>; - }; - - sysmmu_gscl0: sysmmu@13e80000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x13E80000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <2 0>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>; - power-domains = <&gsc_pd>; - #iommu-cells = <0>; - }; - - sysmmu_gscl1: sysmmu@13e90000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x13E90000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <2 2>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>; - power-domains = <&gsc_pd>; - #iommu-cells = <0>; - }; - - sysmmu_scaler0r: sysmmu@12880000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x12880000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <22 4>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>; - power-domains = <&msc_pd>; - #iommu-cells = <0>; - }; - - sysmmu_scaler1r: sysmmu@12890000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x12890000 0x1000>; - interrupts = ; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>; - power-domains = <&msc_pd>; - #iommu-cells = <0>; - }; - - sysmmu_scaler2r: sysmmu@128a0000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x128A0000 0x1000>; - interrupts = ; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>; - power-domains = <&msc_pd>; - #iommu-cells = <0>; - }; - - sysmmu_scaler0w: sysmmu@128c0000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x128C0000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <27 2>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>; - power-domains = <&msc_pd>; - #iommu-cells = <0>; - }; - - sysmmu_scaler1w: sysmmu@128d0000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x128D0000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <22 6>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>; - power-domains = <&msc_pd>; - #iommu-cells = <0>; - }; - - sysmmu_scaler2w: sysmmu@128e0000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x128E0000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <19 6>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>; - power-domains = <&msc_pd>; - #iommu-cells = <0>; - }; - - sysmmu_rotator: sysmmu@11d40000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x11D40000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <4 0>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>; - #iommu-cells = <0>; - }; - - sysmmu_jpeg0: sysmmu@11f10000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x11F10000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <4 2>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>; - #iommu-cells = <0>; - }; - - sysmmu_jpeg1: sysmmu@11f20000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x11F20000 0x1000>; - interrupts = ; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_JPEG2>, <&clock CLK_JPEG2>; - #iommu-cells = <0>; - }; - - sysmmu_mfc_l: sysmmu@11200000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x11200000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <6 2>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>; - power-domains = <&mfc_pd>; - #iommu-cells = <0>; - }; - - sysmmu_mfc_r: sysmmu@11210000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x11210000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <8 5>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>; - power-domains = <&mfc_pd>; - #iommu-cells = <0>; - }; - - sysmmu_fimd1_0: sysmmu@14640000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x14640000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <3 2>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_FIMD1M0>, <&clock CLK_FIMD1>; - power-domains = <&disp_pd>; - #iommu-cells = <0>; - }; - - sysmmu_fimd1_1: sysmmu@14680000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x14680000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <3 0>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_FIMD1M1>, <&clock CLK_FIMD1>; - power-domains = <&disp_pd>; - #iommu-cells = <0>; - }; - - bus_wcore: bus_wcore { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK400_WCORE>; - clock-names = "bus"; - status = "disabled"; - }; - - bus_noc: bus_noc { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK100_NOC>; - clock-names = "bus"; - status = "disabled"; - }; - - bus_fsys_apb: bus_fsys_apb { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_PCLK200_FSYS>; - clock-names = "bus"; - status = "disabled"; - }; - - bus_fsys: bus_fsys { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK200_FSYS>; - clock-names = "bus"; - status = "disabled"; - }; - - bus_fsys2: bus_fsys2 { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK200_FSYS2>; - clock-names = "bus"; - status = "disabled"; - }; - - bus_mfc: bus_mfc { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK333>; - clock-names = "bus"; - status = "disabled"; - }; - - bus_gen: bus_gen { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK266>; - clock-names = "bus"; - status = "disabled"; - }; - - bus_peri: bus_peri { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK66>; - clock-names = "bus"; - status = "disabled"; - }; - - bus_g2d: bus_g2d { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK333_G2D>; - clock-names = "bus"; - status = "disabled"; - }; - - bus_g2d_acp: bus_g2d_acp { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK266_G2D>; - clock-names = "bus"; - status = "disabled"; - }; - - bus_jpeg: bus_jpeg { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK300_JPEG>; - clock-names = "bus"; - status = "disabled"; - }; - - bus_jpeg_apb: bus_jpeg_apb { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK166>; - clock-names = "bus"; - status = "disabled"; - }; - - bus_disp1_fimd: bus_disp1_fimd { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK300_DISP1>; - clock-names = "bus"; - status = "disabled"; - }; - - bus_disp1: bus_disp1 { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK400_DISP1>; - clock-names = "bus"; - status = "disabled"; - }; - - bus_gscl_scaler: bus_gscl_scaler { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK300_GSCL>; - clock-names = "bus"; - status = "disabled"; - }; - - bus_mscl: bus_mscl { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK400_MSCL>; - clock-names = "bus"; - status = "disabled"; - }; - }; - - thermal-zones { - cpu0_thermal: cpu0-thermal { - thermal-sensors = <&tmu_cpu0>; - #include "exynos5420-trip-points.dtsi" - }; - cpu1_thermal: cpu1-thermal { - thermal-sensors = <&tmu_cpu1>; - #include "exynos5420-trip-points.dtsi" - }; - cpu2_thermal: cpu2-thermal { - thermal-sensors = <&tmu_cpu2>; - #include "exynos5420-trip-points.dtsi" - }; - cpu3_thermal: cpu3-thermal { - thermal-sensors = <&tmu_cpu3>; - #include "exynos5420-trip-points.dtsi" - }; - gpu_thermal: gpu-thermal { - thermal-sensors = <&tmu_gpu>; - #include "exynos5420-trip-points.dtsi" - }; - }; -}; - -&adc { - clocks = <&clock CLK_TSADC>; - clock-names = "adc"; - samsung,syscon-phandle = <&pmu_system_controller>; -}; - -&dp { - clocks = <&clock CLK_DP1>; - clock-names = "dp"; - phys = <&dp_phy>; - phy-names = "dp"; - power-domains = <&disp_pd>; -}; - -&fimd { - compatible = "samsung,exynos5420-fimd"; - clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>; - clock-names = "sclk_fimd", "fimd"; - power-domains = <&disp_pd>; - iommus = <&sysmmu_fimd1_0>, <&sysmmu_fimd1_1>; - iommu-names = "m0", "m1"; -}; - -&g2d { - iommus = <&sysmmu_g2dr>, <&sysmmu_g2dw>; - clocks = <&clock CLK_G2D>; - clock-names = "fimg2d"; - status = "okay"; -}; - -&i2c_0 { - clocks = <&clock CLK_I2C0>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_bus>; -}; - -&i2c_1 { - clocks = <&clock CLK_I2C1>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_bus>; -}; - -&i2c_2 { - clocks = <&clock CLK_I2C2>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_bus>; -}; - -&i2c_3 { - clocks = <&clock CLK_I2C3>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_bus>; -}; - -&hsi2c_4 { - clocks = <&clock CLK_USI0>; - clock-names = "hsi2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_hs_bus>; -}; - -&hsi2c_5 { - clocks = <&clock CLK_USI1>; - clock-names = "hsi2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c5_hs_bus>; -}; - -&hsi2c_6 { - clocks = <&clock CLK_USI2>; - clock-names = "hsi2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c6_hs_bus>; -}; - -&hsi2c_7 { - clocks = <&clock CLK_USI3>; - clock-names = "hsi2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c7_hs_bus>; -}; - -&mct { - clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; - clock-names = "fin_pll", "mct"; -}; - -&prng { - clocks = <&clock CLK_SSS>; - clock-names = "secss"; -}; - -&pwm { - clocks = <&clock CLK_PWM>; - clock-names = "timers"; -}; - -&rtc { - clocks = <&clock CLK_RTC>; - clock-names = "rtc"; - interrupt-parent = <&pmu_system_controller>; - status = "disabled"; -}; - -&serial_0 { - clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; - clock-names = "uart", "clk_uart_baud0"; - dmas = <&pdma0 13>, <&pdma0 14>; - dma-names = "rx", "tx"; -}; - -&serial_1 { - clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>; - clock-names = "uart", "clk_uart_baud0"; - dmas = <&pdma1 15>, <&pdma1 16>; - dma-names = "rx", "tx"; -}; - -&serial_2 { - clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; - clock-names = "uart", "clk_uart_baud0"; - dmas = <&pdma0 15>, <&pdma0 16>; - dma-names = "rx", "tx"; -}; - -&serial_3 { - clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>; - clock-names = "uart", "clk_uart_baud0"; - dmas = <&pdma1 17>, <&pdma1 18>; - dma-names = "rx", "tx"; -}; - -&sss { - clocks = <&clock CLK_SSS>; - clock-names = "secss"; -}; - -&trng { - clocks = <&clock CLK_SSS>; - clock-names = "secss"; -}; - -&usbdrd3_0 { - clocks = <&clock CLK_USBD300>; - clock-names = "usbdrd30"; -}; - -&usbdrd_phy0 { - clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>; - clock-names = "phy", "ref"; - samsung,pmu-syscon = <&pmu_system_controller>; -}; - -&usbdrd3_1 { - clocks = <&clock CLK_USBD301>; - clock-names = "usbdrd30"; -}; - -&usbdrd_dwc3_1 { - interrupts = ; -}; - -&usbdrd_phy1 { - clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>; - clock-names = "phy", "ref"; - samsung,pmu-syscon = <&pmu_system_controller>; -}; - -&usbhost1 { - clocks = <&clock CLK_USBH20>; - clock-names = "usbhost"; -}; - -&usbhost2 { - clocks = <&clock CLK_USBH20>; - clock-names = "usbhost"; -}; - -&usb2_phy { - clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>; - clock-names = "phy", "ref"; - samsung,sysreg-phandle = <&sysreg_system_controller>; - samsung,pmureg-phandle = <&pmu_system_controller>; -}; - -&watchdog { - clocks = <&clock CLK_WDT>; - clock-names = "watchdog"; - samsung,syscon-phandle = <&pmu_system_controller>; -}; - -#include "exynos5420-pinctrl.dtsi" -#include "exynos-syscon-restart.dtsi" diff --git a/sys/gnu/dts/arm/exynos5422-cpu-thermal.dtsi b/sys/gnu/dts/arm/exynos5422-cpu-thermal.dtsi deleted file mode 100644 index 3e4c4ad96d6..00000000000 --- a/sys/gnu/dts/arm/exynos5422-cpu-thermal.dtsi +++ /dev/null @@ -1,103 +0,0 @@ -/* - * Device tree sources for Exynos5422 thermal zone - * - * Copyright (c) 2015 Lukasz Majewski - * Anand Moon - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -#include - -/ { - thermal-zones { - cpu0_thermal: cpu0-thermal { - thermal-sensors = <&tmu_cpu0 0>; - polling-delay-passive = <250>; - polling-delay = <0>; - trips { - cpu_alert0: cpu-alert-0 { - temperature = <50000>; /* millicelsius */ - hysteresis = <5000>; /* millicelsius */ - type = "active"; - }; - cpu_alert1: cpu-alert-1 { - temperature = <60000>; /* millicelsius */ - hysteresis = <5000>; /* millicelsius */ - type = "active"; - }; - cpu_alert2: cpu-alert-2 { - temperature = <70000>; /* millicelsius */ - hysteresis = <5000>; /* millicelsius */ - type = "active"; - }; - cpu_crit0: cpu-crit-0 { - temperature = <120000>; /* millicelsius */ - hysteresis = <0>; /* millicelsius */ - type = "critical"; - }; - /* - * Exyunos542x support only 4 trip-points - * so for these polling mode is required. - * Start polling at temperature level of last - * interrupt-driven trip: cpu_alert2 - */ - cpu_alert3: cpu-alert-3 { - temperature = <70000>; /* millicelsius */ - hysteresis = <10000>; /* millicelsius */ - type = "passive"; - }; - cpu_alert4: cpu-alert-4 { - temperature = <85000>; /* millicelsius */ - hysteresis = <10000>; /* millicelsius */ - type = "passive"; - }; - - }; - cooling-maps { - map0 { - trip = <&cpu_alert0>; - cooling-device = <&fan0 0 1>; - }; - map1 { - trip = <&cpu_alert1>; - cooling-device = <&fan0 1 2>; - }; - map2 { - trip = <&cpu_alert2>; - cooling-device = <&fan0 2 3>; - }; - /* - * When reaching cpu_alert3, reduce CPU - * by 2 steps. On Exynos5422/5800 that would - * be: 1500 MHz and 1100 MHz. - */ - map3 { - trip = <&cpu_alert3>; - cooling-device = <&cpu0 0 2>; - }; - map4 { - trip = <&cpu_alert3>; - cooling-device = <&cpu4 0 2>; - }; - - /* - * When reaching cpu_alert4, reduce CPU - * further, down to 600 MHz (11 steps for big, - * 7 steps for LITTLE). - */ - map5 { - trip = <&cpu_alert4>; - cooling-device = <&cpu0 3 7>; - }; - map6 { - trip = <&cpu_alert4>; - cooling-device = <&cpu4 3 11>; - }; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/exynos5422-cpus.dtsi b/sys/gnu/dts/arm/exynos5422-cpus.dtsi deleted file mode 100644 index 1b8605cf240..00000000000 --- a/sys/gnu/dts/arm/exynos5422-cpus.dtsi +++ /dev/null @@ -1,130 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung Exynos5422 SoC cpu device tree source - * - * Copyright (c) 2015 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * This file provides desired ordering for Exynos5422: CPU[0123] being the A7. - * - * The Exynos5420, 5422 and 5800 actually share the same CPU configuration - * but particular boards choose different booting order. - * - * Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422 - * booting cluster (big or LITTLE) is chosen by IROM code by reading - * the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting - * from the LITTLE: Cortex-A7. - */ - -/ { - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x100>; - clocks = <&clock CLK_KFC_CLK>; - clock-frequency = <1000000000>; - cci-control-port = <&cci_control0>; - operating-points-v2 = <&cluster_a7_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - capacity-dmips-mhz = <539>; - }; - - cpu1: cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x101>; - clocks = <&clock CLK_KFC_CLK>; - clock-frequency = <1000000000>; - cci-control-port = <&cci_control0>; - operating-points-v2 = <&cluster_a7_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - capacity-dmips-mhz = <539>; - }; - - cpu2: cpu@102 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x102>; - clocks = <&clock CLK_KFC_CLK>; - clock-frequency = <1000000000>; - cci-control-port = <&cci_control0>; - operating-points-v2 = <&cluster_a7_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - capacity-dmips-mhz = <539>; - }; - - cpu3: cpu@103 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x103>; - clocks = <&clock CLK_KFC_CLK>; - clock-frequency = <1000000000>; - cci-control-port = <&cci_control0>; - operating-points-v2 = <&cluster_a7_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - capacity-dmips-mhz = <539>; - }; - - cpu4: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x0>; - clocks = <&clock CLK_ARM_CLK>; - clock-frequency = <1800000000>; - cci-control-port = <&cci_control1>; - operating-points-v2 = <&cluster_a15_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - capacity-dmips-mhz = <1024>; - }; - - cpu5: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x1>; - clocks = <&clock CLK_ARM_CLK>; - clock-frequency = <1800000000>; - cci-control-port = <&cci_control1>; - operating-points-v2 = <&cluster_a15_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - capacity-dmips-mhz = <1024>; - }; - - cpu6: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x2>; - clocks = <&clock CLK_ARM_CLK>; - clock-frequency = <1800000000>; - cci-control-port = <&cci_control1>; - operating-points-v2 = <&cluster_a15_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - capacity-dmips-mhz = <1024>; - }; - - cpu7: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x3>; - clocks = <&clock CLK_ARM_CLK>; - clock-frequency = <1800000000>; - cci-control-port = <&cci_control1>; - operating-points-v2 = <&cluster_a15_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - capacity-dmips-mhz = <1024>; - }; - }; -}; - -&arm_a7_pmu { - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; - status = "okay"; -}; - -&arm_a15_pmu { - interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/exynos5422-odroid-core.dtsi b/sys/gnu/dts/arm/exynos5422-odroid-core.dtsi deleted file mode 100644 index 5cf1aed2049..00000000000 --- a/sys/gnu/dts/arm/exynos5422-odroid-core.dtsi +++ /dev/null @@ -1,1075 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Hardkernel Odroid XU3/XU3-Lite/XU4/HC1 boards core device tree source - * - * Copyright (c) 2017 Marek Szyprowski - * Copyright (c) 2013-2017 Samsung Electronics Co., Ltd. - * http://www.samsung.com - */ - -#include -#include -#include -#include "exynos5800.dtsi" -#include "exynos5422-cpus.dtsi" - -/ { - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x7EA00000>; - }; - - chosen { - stdout-path = "serial2:115200n8"; - }; - - firmware@2073000 { - compatible = "samsung,secure-firmware"; - reg = <0x02073000 0x1000>; - }; - - fixed-rate-clocks { - oscclk { - compatible = "samsung,exynos5420-oscclk"; - clock-frequency = <24000000>; - }; - }; - - bus_wcore_opp_table: opp_table2 { - compatible = "operating-points-v2"; - - /* derived from 532MHz MPLL */ - opp00 { - opp-hz = /bits/ 64 <88700000>; - opp-microvolt = <925000 925000 1400000>; - }; - opp01 { - opp-hz = /bits/ 64 <133000000>; - opp-microvolt = <950000 950000 1400000>; - }; - opp02 { - opp-hz = /bits/ 64 <177400000>; - opp-microvolt = <950000 950000 1400000>; - }; - opp03 { - opp-hz = /bits/ 64 <266000000>; - opp-microvolt = <950000 950000 1400000>; - }; - opp04 { - opp-hz = /bits/ 64 <532000000>; - opp-microvolt = <1000000 1000000 1400000>; - }; - }; - - bus_noc_opp_table: opp_table3 { - compatible = "operating-points-v2"; - - /* derived from 666MHz CPLL */ - opp00 { - opp-hz = /bits/ 64 <66600000>; - }; - opp01 { - opp-hz = /bits/ 64 <74000000>; - }; - opp02 { - opp-hz = /bits/ 64 <83250000>; - }; - opp03 { - opp-hz = /bits/ 64 <111000000>; - }; - }; - - bus_fsys_apb_opp_table: opp_table4 { - compatible = "operating-points-v2"; - - /* derived from 666MHz CPLL */ - opp00 { - opp-hz = /bits/ 64 <111000000>; - }; - opp01 { - opp-hz = /bits/ 64 <222000000>; - }; - }; - - bus_fsys2_opp_table: opp_table5 { - compatible = "operating-points-v2"; - - /* derived from 600MHz DPLL */ - opp00 { - opp-hz = /bits/ 64 <75000000>; - }; - opp01 { - opp-hz = /bits/ 64 <120000000>; - }; - opp02 { - opp-hz = /bits/ 64 <200000000>; - }; - }; - - bus_mfc_opp_table: opp_table6 { - compatible = "operating-points-v2"; - - /* derived from 666MHz CPLL */ - opp00 { - opp-hz = /bits/ 64 <83250000>; - }; - opp01 { - opp-hz = /bits/ 64 <111000000>; - }; - opp02 { - opp-hz = /bits/ 64 <166500000>; - }; - opp03 { - opp-hz = /bits/ 64 <222000000>; - }; - opp04 { - opp-hz = /bits/ 64 <333000000>; - }; - }; - - bus_gen_opp_table: opp_table7 { - compatible = "operating-points-v2"; - - /* derived from 532MHz MPLL */ - opp00 { - opp-hz = /bits/ 64 <88700000>; - }; - opp01 { - opp-hz = /bits/ 64 <133000000>; - }; - opp02 { - opp-hz = /bits/ 64 <178000000>; - }; - opp03 { - opp-hz = /bits/ 64 <266000000>; - }; - }; - - bus_peri_opp_table: opp_table8 { - compatible = "operating-points-v2"; - - /* derived from 666MHz CPLL */ - opp00 { - opp-hz = /bits/ 64 <66600000>; - }; - }; - - bus_g2d_opp_table: opp_table9 { - compatible = "operating-points-v2"; - - /* derived from 666MHz CPLL */ - opp00 { - opp-hz = /bits/ 64 <83250000>; - }; - opp01 { - opp-hz = /bits/ 64 <111000000>; - }; - opp02 { - opp-hz = /bits/ 64 <166500000>; - }; - opp03 { - opp-hz = /bits/ 64 <222000000>; - }; - opp04 { - opp-hz = /bits/ 64 <333000000>; - }; - }; - - bus_g2d_acp_opp_table: opp_table10 { - compatible = "operating-points-v2"; - - /* derived from 532MHz MPLL */ - opp00 { - opp-hz = /bits/ 64 <66500000>; - }; - opp01 { - opp-hz = /bits/ 64 <133000000>; - }; - opp02 { - opp-hz = /bits/ 64 <178000000>; - }; - opp03 { - opp-hz = /bits/ 64 <266000000>; - }; - }; - - bus_jpeg_opp_table: opp_table11 { - compatible = "operating-points-v2"; - - /* derived from 600MHz DPLL */ - opp00 { - opp-hz = /bits/ 64 <75000000>; - }; - opp01 { - opp-hz = /bits/ 64 <150000000>; - }; - opp02 { - opp-hz = /bits/ 64 <200000000>; - }; - opp03 { - opp-hz = /bits/ 64 <300000000>; - }; - }; - - bus_jpeg_apb_opp_table: opp_table12 { - compatible = "operating-points-v2"; - - /* derived from 666MHz CPLL */ - opp00 { - opp-hz = /bits/ 64 <83250000>; - }; - opp01 { - opp-hz = /bits/ 64 <111000000>; - }; - opp02 { - opp-hz = /bits/ 64 <133000000>; - }; - opp03 { - opp-hz = /bits/ 64 <166500000>; - }; - }; - - bus_disp1_fimd_opp_table: opp_table13 { - compatible = "operating-points-v2"; - - /* derived from 600MHz DPLL */ - opp00 { - opp-hz = /bits/ 64 <120000000>; - }; - opp01 { - opp-hz = /bits/ 64 <200000000>; - }; - }; - - bus_disp1_opp_table: opp_table14 { - compatible = "operating-points-v2"; - - /* derived from 600MHz DPLL */ - opp00 { - opp-hz = /bits/ 64 <120000000>; - }; - opp01 { - opp-hz = /bits/ 64 <200000000>; - }; - opp02 { - opp-hz = /bits/ 64 <300000000>; - }; - }; - - bus_gscl_opp_table: opp_table15 { - compatible = "operating-points-v2"; - - /* derived from 600MHz DPLL */ - opp00 { - opp-hz = /bits/ 64 <150000000>; - }; - opp01 { - opp-hz = /bits/ 64 <200000000>; - }; - opp02 { - opp-hz = /bits/ 64 <300000000>; - }; - }; - - bus_mscl_opp_table: opp_table16 { - compatible = "operating-points-v2"; - - /* derived from 666MHz CPLL */ - opp00 { - opp-hz = /bits/ 64 <84000000>; - }; - opp01 { - opp-hz = /bits/ 64 <167000000>; - }; - opp02 { - opp-hz = /bits/ 64 <222000000>; - }; - opp03 { - opp-hz = /bits/ 64 <333000000>; - }; - opp04 { - opp-hz = /bits/ 64 <666000000>; - }; - }; - - dmc_opp_table: opp_table17 { - compatible = "operating-points-v2"; - - opp00 { - opp-hz = /bits/ 64 <165000000>; - opp-microvolt = <875000>; - }; - opp01 { - opp-hz = /bits/ 64 <206000000>; - opp-microvolt = <875000>; - }; - opp02 { - opp-hz = /bits/ 64 <275000000>; - opp-microvolt = <875000>; - }; - opp03 { - opp-hz = /bits/ 64 <413000000>; - opp-microvolt = <887500>; - }; - opp04 { - opp-hz = /bits/ 64 <543000000>; - opp-microvolt = <937500>; - }; - opp05 { - opp-hz = /bits/ 64 <633000000>; - opp-microvolt = <1012500>; - }; - opp06 { - opp-hz = /bits/ 64 <728000000>; - opp-microvolt = <1037500>; - }; - opp07 { - opp-hz = /bits/ 64 <825000000>; - opp-microvolt = <1050000>; - }; - }; - - samsung_K3QF2F20DB: lpddr3 { - compatible = "samsung,K3QF2F20DB", "jedec,lpddr3"; - density = <16384>; - io-width = <32>; - #address-cells = <1>; - #size-cells = <0>; - - tRFC-min-tck = <17>; - tRRD-min-tck = <2>; - tRPab-min-tck = <2>; - tRPpb-min-tck = <2>; - tRCD-min-tck = <3>; - tRC-min-tck = <6>; - tRAS-min-tck = <5>; - tWTR-min-tck = <2>; - tWR-min-tck = <7>; - tRTP-min-tck = <2>; - tW2W-C2C-min-tck = <0>; - tR2R-C2C-min-tck = <0>; - tWL-min-tck = <8>; - tDQSCK-min-tck = <5>; - tRL-min-tck = <14>; - tFAW-min-tck = <5>; - tXSR-min-tck = <12>; - tXP-min-tck = <2>; - tCKE-min-tck = <2>; - tCKESR-min-tck = <2>; - tMRD-min-tck = <5>; - - timings_samsung_K3QF2F20DB_800mhz: lpddr3-timings@800000000 { - compatible = "jedec,lpddr3-timings"; - /* workaround: 'reg' shows max-freq */ - reg = <800000000>; - min-freq = <100000000>; - tRFC = <65000>; - tRRD = <6000>; - tRPab = <12000>; - tRPpb = <12000>; - tRCD = <10000>; - tRC = <33750>; - tRAS = <23000>; - tWTR = <3750>; - tWR = <7500>; - tRTP = <3750>; - tW2W-C2C = <0>; - tR2R-C2C = <0>; - tFAW = <25000>; - tXSR = <70000>; - tXP = <3750>; - tCKE = <3750>; - tCKESR = <3750>; - tMRD = <7000>; - }; - }; -}; - -&adc { - vdd-supply = <&ldo4_reg>; - status = "okay"; -}; - -&bus_wcore { - operating-points-v2 = <&bus_wcore_opp_table>; - devfreq-events = <&nocp_mem0_0>, <&nocp_mem0_1>, - <&nocp_mem1_0>, <&nocp_mem1_1>; - vdd-supply = <&buck3_reg>; - exynos,saturation-ratio = <100>; - status = "okay"; -}; - -&bus_noc { - operating-points-v2 = <&bus_noc_opp_table>; - devfreq = <&bus_wcore>; - status = "okay"; -}; - -&bus_fsys_apb { - operating-points-v2 = <&bus_fsys_apb_opp_table>; - devfreq = <&bus_wcore>; - status = "okay"; -}; - -&bus_fsys { - operating-points-v2 = <&bus_fsys2_opp_table>; - devfreq = <&bus_wcore>; - status = "okay"; -}; - -&bus_fsys2 { - operating-points-v2 = <&bus_fsys2_opp_table>; - devfreq = <&bus_wcore>; - status = "okay"; -}; - -&bus_mfc { - operating-points-v2 = <&bus_mfc_opp_table>; - devfreq = <&bus_wcore>; - status = "okay"; -}; - -&bus_gen { - operating-points-v2 = <&bus_gen_opp_table>; - devfreq = <&bus_wcore>; - status = "okay"; -}; - -&bus_peri { - operating-points-v2 = <&bus_peri_opp_table>; - devfreq = <&bus_wcore>; - status = "okay"; -}; - -&bus_g2d { - operating-points-v2 = <&bus_g2d_opp_table>; - devfreq = <&bus_wcore>; - status = "okay"; -}; - -&bus_g2d_acp { - operating-points-v2 = <&bus_g2d_acp_opp_table>; - devfreq = <&bus_wcore>; - status = "okay"; -}; - -&bus_jpeg { - operating-points-v2 = <&bus_jpeg_opp_table>; - devfreq = <&bus_wcore>; - status = "okay"; -}; - -&bus_jpeg_apb { - operating-points-v2 = <&bus_jpeg_apb_opp_table>; - devfreq = <&bus_wcore>; - status = "okay"; -}; - -&bus_disp1_fimd { - operating-points-v2 = <&bus_disp1_fimd_opp_table>; - devfreq = <&bus_wcore>; - status = "okay"; -}; - -&bus_disp1 { - operating-points-v2 = <&bus_disp1_opp_table>; - devfreq = <&bus_wcore>; - status = "okay"; -}; - -&bus_gscl_scaler { - operating-points-v2 = <&bus_gscl_opp_table>; - devfreq = <&bus_wcore>; - status = "okay"; -}; - -&bus_mscl { - operating-points-v2 = <&bus_mscl_opp_table>; - devfreq = <&bus_wcore>; - status = "okay"; -}; - -&cpu0 { - cpu-supply = <&buck6_reg>; -}; - -&cpu4 { - cpu-supply = <&buck2_reg>; -}; - -&dmc { - devfreq-events = <&ppmu_event3_dmc0_0>, <&ppmu_event3_dmc0_1>, - <&ppmu_event3_dmc1_0>, <&ppmu_event3_dmc1_1>; - device-handle = <&samsung_K3QF2F20DB>; - operating-points-v2 = <&dmc_opp_table>; - vdd-supply = <&buck1_reg>; - status = "okay"; -}; - -&hsi2c_4 { - status = "okay"; - - s2mps11_pmic@66 { - compatible = "samsung,s2mps11-pmic"; - reg = <0x66>; - samsung,s2mps11-acokb-ground; - - interrupt-parent = <&gpx0>; - interrupts = <4 IRQ_TYPE_EDGE_FALLING>; - pinctrl-names = "default"; - pinctrl-0 = <&s2mps11_irq>; - - s2mps11_osc: clocks { - compatible = "samsung,s2mps11-clk"; - #clock-cells = <1>; - clock-output-names = "s2mps11_ap", - "s2mps11_cp", "s2mps11_bt"; - }; - - regulators { - ldo1_reg: LDO1 { - regulator-name = "vdd_ldo1"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo2_reg: LDO2 { - regulator-name = "vdd_ldo2"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo3_reg: LDO3 { - regulator-name = "vddq_mmc0"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo4_reg: LDO4 { - regulator-name = "vdd_adc"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo5_reg: LDO5 { - regulator-name = "vdd_ldo5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo6_reg: LDO6 { - regulator-name = "vdd_ldo6"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo7_reg: LDO7 { - regulator-name = "vdd_ldo7"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo8_reg: LDO8 { - regulator-name = "vdd_ldo8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo9_reg: LDO9 { - regulator-name = "vdd_ldo9"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo10_reg: LDO10 { - regulator-name = "vdd_ldo10"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo11_reg: LDO11 { - regulator-name = "vdd_ldo11"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo12_reg: LDO12 { - /* Unused */ - regulator-name = "vdd_ldo12"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <2375000>; - }; - - ldo13_reg: LDO13 { - regulator-name = "vddq_mmc2"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo14_reg: LDO14 { - /* Unused */ - regulator-name = "vdd_ldo14"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3950000>; - }; - - ldo15_reg: LDO15 { - regulator-name = "vdd_ldo15"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo16_reg: LDO16 { - /* Unused */ - regulator-name = "vdd_ldo16"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3950000>; - }; - - ldo17_reg: LDO17 { - regulator-name = "vdd_ldo17"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo18_reg: LDO18 { - regulator-name = "vdd_emmc_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo19_reg: LDO19 { - regulator-name = "vdd_sd"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo20_reg: LDO20 { - /* Unused */ - regulator-name = "vdd_ldo20"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3950000>; - }; - - ldo21_reg: LDO21 { - /* Unused */ - regulator-name = "vdd_ldo21"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3950000>; - }; - - ldo22_reg: LDO22 { - /* Unused */ - regulator-name = "vdd_ldo22"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <2375000>; - }; - - ldo23_reg: LDO23 { - regulator-name = "vdd_mifs"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo24_reg: LDO24 { - /* Unused */ - regulator-name = "vdd_ldo24"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3950000>; - }; - - ldo25_reg: LDO25 { - /* Unused */ - regulator-name = "vdd_ldo25"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3950000>; - }; - - ldo26_reg: LDO26 { - /* Used on XU3, XU3-Lite and XU4 */ - regulator-name = "vdd_ldo26"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3950000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo27_reg: LDO27 { - regulator-name = "vdd_g3ds"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo28_reg: LDO28 { - /* Used on XU3 */ - regulator-name = "vdd_ldo28"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3950000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo29_reg: LDO29 { - /* Unused */ - regulator-name = "vdd_ldo29"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3950000>; - }; - - ldo30_reg: LDO30 { - /* Unused */ - regulator-name = "vdd_ldo30"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3950000>; - }; - - ldo31_reg: LDO31 { - /* Unused */ - regulator-name = "vdd_ldo31"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3950000>; - }; - - ldo32_reg: LDO32 { - /* Unused */ - regulator-name = "vdd_ldo32"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3950000>; - }; - - ldo33_reg: LDO33 { - /* Unused */ - regulator-name = "vdd_ldo33"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3950000>; - }; - - ldo34_reg: LDO34 { - /* Unused */ - regulator-name = "vdd_ldo34"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3950000>; - }; - - ldo35_reg: LDO35 { - /* Unused */ - regulator-name = "vdd_ldo35"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <2375000>; - }; - - ldo36_reg: LDO36 { - /* Unused */ - regulator-name = "vdd_ldo36"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3950000>; - }; - - ldo37_reg: LDO37 { - /* Unused */ - regulator-name = "vdd_ldo37"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3950000>; - }; - - ldo38_reg: LDO38 { - /* Unused */ - regulator-name = "vdd_ldo38"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3950000>; - }; - - buck1_reg: BUCK1 { - regulator-name = "vdd_mif"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck2_reg: BUCK2 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - regulator-coupled-with = <&buck3_reg>; - regulator-coupled-max-spread = <300000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck3_reg: BUCK3 { - regulator-name = "vdd_int"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-boot-on; - regulator-coupled-with = <&buck2_reg>; - regulator-coupled-max-spread = <300000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck4_reg: BUCK4 { - regulator-name = "vdd_g3d"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck5_reg: BUCK5 { - regulator-name = "vdd_mem"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-boot-on; - }; - - buck6_reg: BUCK6 { - regulator-name = "vdd_kfc"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck7_reg: BUCK7 { - regulator-name = "vdd_1.35v_ldo"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - }; - - buck8_reg: BUCK8 { - regulator-name = "vdd_2.0v_ldo"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2100000>; - regulator-always-on; - regulator-boot-on; - }; - - buck9_reg: BUCK9 { - regulator-name = "vdd_2.8v_ldo"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3750000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck10_reg: BUCK10 { - regulator-name = "vdd_vmem"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; -}; - -&mmc_2 { - status = "okay"; - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <0 4>; - samsung,dw-mshc-ddr-timing = <0 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_wp &sd2_bus1 &sd2_bus4>; - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <200000000>; - vmmc-supply = <&ldo19_reg>; - vqmmc-supply = <&ldo13_reg>; - sd-uhs-sdr50; - sd-uhs-sdr104; - sd-uhs-ddr50; -}; - -&nocp_mem0_0 { - status = "okay"; -}; - -&nocp_mem0_1 { - status = "okay"; -}; - -&nocp_mem1_0 { - status = "okay"; -}; - -&nocp_mem1_1 { - status = "okay"; -}; - -&pinctrl_0 { - s2mps11_irq: s2mps11-irq { - samsung,pins = "gpx0-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&ppmu_dmc0_0 { - status = "okay"; -}; - -&ppmu_dmc0_1 { - status = "okay"; -}; - -&ppmu_dmc1_0 { - status = "okay"; -}; - -&ppmu_dmc1_1 { - status = "okay"; -}; - -&tmu_cpu0 { - vtmu-supply = <&ldo7_reg>; -}; - -&tmu_cpu1 { - vtmu-supply = <&ldo7_reg>; -}; - -&tmu_cpu2 { - vtmu-supply = <&ldo7_reg>; -}; - -&tmu_cpu3 { - vtmu-supply = <&ldo7_reg>; -}; - -&tmu_gpu { - vtmu-supply = <&ldo7_reg>; -}; - -&gpu { - mali-supply = <&buck4_reg>; - status = "okay"; -}; - -&rtc { - status = "okay"; - clocks = <&clock CLK_RTC>, <&s2mps11_osc S2MPS11_CLK_AP>; - clock-names = "rtc", "rtc_src"; -}; - -&usbdrd_dwc3_0 { - dr_mode = "host"; -}; - -/* usbdrd_dwc3_1 mode customized in each board */ - -&usbdrd3_0 { - vdd33-supply = <&ldo9_reg>; - vdd10-supply = <&ldo11_reg>; -}; - -&usbdrd3_1 { - vdd33-supply = <&ldo9_reg>; - vdd10-supply = <&ldo11_reg>; -}; diff --git a/sys/gnu/dts/arm/exynos5422-odroidhc1.dts b/sys/gnu/dts/arm/exynos5422-odroidhc1.dts deleted file mode 100644 index f163206265b..00000000000 --- a/sys/gnu/dts/arm/exynos5422-odroidhc1.dts +++ /dev/null @@ -1,234 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Hardkernel Odroid HC1 board device tree source - * - * Copyright (c) 2017 Marek Szyprowski - * Copyright (c) 2017 Samsung Electronics Co., Ltd. - * http://www.samsung.com - */ - -/dts-v1/; -#include "exynos5422-odroid-core.dtsi" - -/ { - model = "Hardkernel Odroid HC1"; - compatible = "hardkernel,odroid-hc1", "samsung,exynos5800", \ - "samsung,exynos5"; - - pwmleds { - compatible = "pwm-leds"; - - blueled { - label = "blue:heartbeat"; - pwms = <&pwm 2 2000000 0>; - pwm-names = "pwm2"; - max_brightness = <255>; - linux,default-trigger = "heartbeat"; - }; - }; - - thermal-zones { - cpu0_thermal: cpu0-thermal { - thermal-sensors = <&tmu_cpu0 0>; - trips { - cpu0_alert0: cpu-alert-0 { - temperature = <70000>; /* millicelsius */ - hysteresis = <10000>; /* millicelsius */ - type = "active"; - }; - cpu0_alert1: cpu-alert-1 { - temperature = <85000>; /* millicelsius */ - hysteresis = <10000>; /* millicelsius */ - type = "active"; - }; - cpu0_crit0: cpu-crit-0 { - temperature = <120000>; /* millicelsius */ - hysteresis = <0>; /* millicelsius */ - type = "critical"; - }; - }; - - cooling-maps { - /* - * When reaching cpu0_alert0, reduce CPU - * by 2 steps. On Exynos5422/5800 that would - * be: 1600 MHz and 1100 MHz. - */ - map0 { - trip = <&cpu0_alert0>; - cooling-device = <&cpu0 0 2>, - <&cpu1 0 2>, - <&cpu2 0 2>, - <&cpu3 0 2>, - <&cpu4 0 2>, - <&cpu5 0 2>, - <&cpu6 0 2>, - <&cpu7 0 2>; - }; - /* - * When reaching cpu0_alert1, reduce CPU - * further, down to 600 MHz (12 steps for big, - * 7 steps for LITTLE). - */ - map1 { - trip = <&cpu0_alert1>; - cooling-device = <&cpu0 3 8>, - <&cpu1 3 8>, - <&cpu2 3 8>, - <&cpu3 3 8>, - <&cpu4 3 14>, - <&cpu5 3 14>, - <&cpu6 3 14>, - <&cpu7 3 14>; - }; - }; - }; - cpu1_thermal: cpu1-thermal { - thermal-sensors = <&tmu_cpu1 0>; - trips { - cpu1_alert0: cpu-alert-0 { - temperature = <70000>; - hysteresis = <10000>; - type = "active"; - }; - cpu1_alert1: cpu-alert-1 { - temperature = <85000>; - hysteresis = <10000>; - type = "active"; - }; - cpu1_crit0: cpu-crit-0 { - temperature = <120000>; - hysteresis = <0>; - type = "critical"; - }; - }; - cooling-maps { - map0 { - trip = <&cpu1_alert0>; - cooling-device = <&cpu0 0 2>, - <&cpu1 0 2>, - <&cpu2 0 2>, - <&cpu3 0 2>, - <&cpu4 0 2>, - <&cpu5 0 2>, - <&cpu6 0 2>, - <&cpu7 0 2>; - }; - map1 { - trip = <&cpu1_alert1>; - cooling-device = <&cpu0 3 8>, - <&cpu1 3 8>, - <&cpu2 3 8>, - <&cpu3 3 8>, - <&cpu4 3 14>, - <&cpu5 3 14>, - <&cpu6 3 14>, - <&cpu7 3 14>; - }; - }; - }; - cpu2_thermal: cpu2-thermal { - thermal-sensors = <&tmu_cpu2 0>; - trips { - cpu2_alert0: cpu-alert-0 { - temperature = <70000>; - hysteresis = <10000>; - type = "active"; - }; - cpu2_alert1: cpu-alert-1 { - temperature = <85000>; - hysteresis = <10000>; - type = "active"; - }; - cpu2_crit0: cpu-crit-0 { - temperature = <120000>; - hysteresis = <0>; - type = "critical"; - }; - }; - cooling-maps { - map0 { - trip = <&cpu2_alert0>; - cooling-device = <&cpu0 0 2>, - <&cpu1 0 2>, - <&cpu2 0 2>, - <&cpu3 0 2>, - <&cpu4 0 2>, - <&cpu5 0 2>, - <&cpu6 0 2>, - <&cpu7 0 2>; - }; - map1 { - trip = <&cpu2_alert1>; - cooling-device = <&cpu0 3 8>, - <&cpu1 3 8>, - <&cpu2 3 8>, - <&cpu3 3 8>, - <&cpu4 3 14>, - <&cpu5 3 14>, - <&cpu6 3 14>, - <&cpu7 3 14>; - }; - }; - }; - cpu3_thermal: cpu3-thermal { - thermal-sensors = <&tmu_cpu3 0>; - trips { - cpu3_alert0: cpu-alert-0 { - temperature = <70000>; - hysteresis = <10000>; - type = "active"; - }; - cpu3_alert1: cpu-alert-1 { - temperature = <85000>; - hysteresis = <10000>; - type = "active"; - }; - cpu3_crit0: cpu-crit-0 { - temperature = <120000>; - hysteresis = <0>; - type = "critical"; - }; - }; - cooling-maps { - map0 { - trip = <&cpu3_alert0>; - cooling-device = <&cpu0 0 2>, - <&cpu1 0 2>, - <&cpu2 0 2>, - <&cpu3 0 2>, - <&cpu4 0 2>, - <&cpu5 0 2>, - <&cpu6 0 2>, - <&cpu7 0 2>; - }; - map1 { - trip = <&cpu3_alert1>; - cooling-device = <&cpu0 3 8>, - <&cpu1 3 8>, - <&cpu2 3 8>, - <&cpu3 3 8>, - <&cpu4 3 14>, - <&cpu5 3 14>, - <&cpu6 3 14>, - <&cpu7 3 14>; - }; - }; - }; - }; - -}; - -&pwm { - /* - * PWM 2 -- Blue LED - */ - pinctrl-0 = <&pwm2_out>; - pinctrl-names = "default"; - samsung,pwm-outputs = <2>; - status = "okay"; -}; - -&usbdrd_dwc3_1 { - dr_mode = "host"; -}; diff --git a/sys/gnu/dts/arm/exynos5422-odroidxu3-audio.dtsi b/sys/gnu/dts/arm/exynos5422-odroidxu3-audio.dtsi deleted file mode 100644 index c3c2d85267d..00000000000 --- a/sys/gnu/dts/arm/exynos5422-odroidxu3-audio.dtsi +++ /dev/null @@ -1,89 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Hardkernel Odroid XU3 audio subsystem device tree source - * - * Copyright (c) 2015 Krzysztof Kozlowski - * Copyright (c) 2014 Collabora Ltd. - * Copyright (c) 2013 Samsung Electronics Co., Ltd. - * http://www.samsung.com - */ - -#include - -/ { - sound: sound { - compatible = "samsung,odroid-xu3-audio"; - model = "Odroid-XU3"; - - samsung,audio-widgets = - "Headphone", "Headphone Jack", - "Speakers", "Speakers"; - samsung,audio-routing = - "Headphone Jack", "HPL", - "Headphone Jack", "HPR", - "Headphone Jack", "MICBIAS", - "IN12", "Headphone Jack", - "Speakers", "SPKL", - "Speakers", "SPKR", - "I2S Playback", "Mixer DAI TX", - "HiFi Playback", "Mixer DAI TX", - "Mixer DAI RX", "HiFi Capture"; - - assigned-clocks = <&clock CLK_MOUT_EPLL>, - <&clock CLK_MOUT_MAU_EPLL>, - <&clock CLK_MOUT_USER_MAU_EPLL>, - <&clock_audss EXYNOS_MOUT_AUDSS>, - <&clock_audss EXYNOS_MOUT_I2S>, - <&clock_audss EXYNOS_DOUT_SRP>, - <&clock_audss EXYNOS_DOUT_AUD_BUS>, - <&clock_audss EXYNOS_DOUT_I2S>; - - assigned-clock-parents = <&clock CLK_FOUT_EPLL>, - <&clock CLK_MOUT_EPLL>, - <&clock CLK_MOUT_MAU_EPLL>, - <&clock CLK_MAU_EPLL>, - <&clock_audss EXYNOS_MOUT_AUDSS>; - - assigned-clock-rates = <0>, - <0>, - <0>, - <0>, - <0>, - <196608001>, - <(196608002 / 2)>, - <196608000>; - - cpu { - sound-dai = <&i2s0 0>, <&i2s0 1>; - }; - codec { - sound-dai = <&hdmi>, <&max98090>; - }; - }; -}; - -&clock_audss { - assigned-clocks = <&clock_audss EXYNOS_DOUT_SRP>, - <&clock CLK_FOUT_EPLL>; - assigned-clock-rates = <(196608000 / 256)>, - <196608000>; -}; - -&hsi2c_5 { - status = "okay"; - max98090: max98090@10 { - compatible = "maxim,max98090"; - reg = <0x10>; - interrupt-parent = <&gpx3>; - interrupts = <2 IRQ_TYPE_NONE>; - clocks = <&i2s0 CLK_I2S_CDCLK>; - clock-names = "mclk"; - #sound-dai-cells = <0>; - }; -}; - -&i2s0 { - status = "okay"; - assigned-clocks = <&i2s0 CLK_I2S_RCLK_SRC>; - assigned-clock-parents = <&clock_audss EXYNOS_SCLK_I2S>; -}; diff --git a/sys/gnu/dts/arm/exynos5422-odroidxu3-common.dtsi b/sys/gnu/dts/arm/exynos5422-odroidxu3-common.dtsi deleted file mode 100644 index 1865a708b49..00000000000 --- a/sys/gnu/dts/arm/exynos5422-odroidxu3-common.dtsi +++ /dev/null @@ -1,446 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Hardkernel Odroid XU3/XU3-Lite/XU4 boards common device tree source - * - * Copyright (c) 2013 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * Copyright (c) 2014 Collabora Ltd. - * Copyright (c) 2015 Lukasz Majewski - * Anand Moon - */ - -#include -#include "exynos5422-odroid-core.dtsi" - -/ { - gpio_keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&power_key>; - - power_key { - /* - * The power button (SW2) is connected to the PWRON - * pin (active high) of the S2MPS11 PMIC, which acts - * as a 16ms debouce filter and signal inverter with - * output on ONOB pin (active low). ONOB PMIC pin is - * then connected to XEINT3 SoC pin. - */ - gpios = <&gpx0 3 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "power key"; - debounce-interval = <0>; - wakeup-source; - }; - }; - - emmc_pwrseq: pwrseq { - pinctrl-0 = <&emmc_nrst_pin>; - pinctrl-names = "default"; - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpd1 0 GPIO_ACTIVE_LOW>; - }; - - fan0: pwm-fan { - compatible = "pwm-fan"; - pwms = <&pwm 0 20972 0>; - #cooling-cells = <2>; - cooling-levels = <0 130 170 230>; - }; - - thermal-zones { - cpu0_thermal: cpu0-thermal { - thermal-sensors = <&tmu_cpu0 0>; - polling-delay-passive = <250>; - polling-delay = <0>; - trips { - cpu0_alert0: cpu-alert-0 { - temperature = <50000>; /* millicelsius */ - hysteresis = <5000>; /* millicelsius */ - type = "active"; - }; - cpu0_alert1: cpu-alert-1 { - temperature = <60000>; /* millicelsius */ - hysteresis = <5000>; /* millicelsius */ - type = "active"; - }; - cpu0_alert2: cpu-alert-2 { - temperature = <70000>; /* millicelsius */ - hysteresis = <5000>; /* millicelsius */ - type = "active"; - }; - cpu0_crit0: cpu-crit-0 { - temperature = <120000>; /* millicelsius */ - hysteresis = <0>; /* millicelsius */ - type = "critical"; - }; - /* - * Exynos542x supports only 4 trip-points - * so for these polling mode is required. - * Start polling at temperature level of last - * interrupt-driven trip: cpu0_alert2 - */ - cpu0_alert3: cpu-alert-3 { - temperature = <70000>; /* millicelsius */ - hysteresis = <10000>; /* millicelsius */ - type = "passive"; - }; - cpu0_alert4: cpu-alert-4 { - temperature = <85000>; /* millicelsius */ - hysteresis = <10000>; /* millicelsius */ - type = "passive"; - }; - }; - cooling-maps { - map0 { - trip = <&cpu0_alert0>; - cooling-device = <&fan0 0 1>; - }; - map1 { - trip = <&cpu0_alert1>; - cooling-device = <&fan0 1 2>; - }; - map2 { - trip = <&cpu0_alert2>; - cooling-device = <&fan0 2 3>; - }; - /* - * When reaching cpu0_alert3, reduce CPU - * by 2 steps. On Exynos5422/5800 that would - * (usually) be: 1800 MHz and 1200 MHz. - */ - map3 { - trip = <&cpu0_alert3>; - cooling-device = <&cpu0 0 2>, - <&cpu1 0 2>, - <&cpu2 0 2>, - <&cpu3 0 2>, - <&cpu4 0 2>, - <&cpu5 0 2>, - <&cpu6 0 2>, - <&cpu7 0 2>; - }; - /* - * When reaching cpu0_alert4, reduce CPU - * further, down to 600 MHz (14 steps for big, - * 8 steps for LITTLE). - */ - cpu0_cooling_map4: map4 { - trip = <&cpu0_alert4>; - cooling-device = <&cpu0 3 8>, - <&cpu1 3 8>, - <&cpu2 3 8>, - <&cpu3 3 8>, - <&cpu4 3 14>, - <&cpu5 3 14>, - <&cpu6 3 14>, - <&cpu7 3 14>; - }; - }; - }; - cpu1_thermal: cpu1-thermal { - thermal-sensors = <&tmu_cpu1 0>; - polling-delay-passive = <250>; - polling-delay = <0>; - trips { - cpu1_alert0: cpu-alert-0 { - temperature = <50000>; - hysteresis = <5000>; - type = "active"; - }; - cpu1_alert1: cpu-alert-1 { - temperature = <60000>; - hysteresis = <5000>; - type = "active"; - }; - cpu1_alert2: cpu-alert-2 { - temperature = <70000>; - hysteresis = <5000>; - type = "active"; - }; - cpu1_crit0: cpu-crit-0 { - temperature = <120000>; - hysteresis = <0>; - type = "critical"; - }; - cpu1_alert3: cpu-alert-3 { - temperature = <70000>; - hysteresis = <10000>; - type = "passive"; - }; - cpu1_alert4: cpu-alert-4 { - temperature = <85000>; - hysteresis = <10000>; - type = "passive"; - }; - }; - cooling-maps { - map0 { - trip = <&cpu1_alert0>; - cooling-device = <&fan0 0 1>; - }; - map1 { - trip = <&cpu1_alert1>; - cooling-device = <&fan0 1 2>; - }; - map2 { - trip = <&cpu1_alert2>; - cooling-device = <&fan0 2 3>; - }; - map3 { - trip = <&cpu1_alert3>; - cooling-device = <&cpu0 0 2>, - <&cpu1 0 2>, - <&cpu2 0 2>, - <&cpu3 0 2>, - <&cpu4 0 2>, - <&cpu5 0 2>, - <&cpu6 0 2>, - <&cpu7 0 2>; - }; - cpu1_cooling_map4: map4 { - trip = <&cpu1_alert4>; - cooling-device = <&cpu0 3 8>, - <&cpu1 3 8>, - <&cpu2 3 8>, - <&cpu3 3 8>, - <&cpu4 3 14>, - <&cpu5 3 14>, - <&cpu6 3 14>, - <&cpu7 3 14>; - }; - }; - }; - cpu2_thermal: cpu2-thermal { - thermal-sensors = <&tmu_cpu2 0>; - polling-delay-passive = <250>; - polling-delay = <0>; - trips { - cpu2_alert0: cpu-alert-0 { - temperature = <50000>; - hysteresis = <5000>; - type = "active"; - }; - cpu2_alert1: cpu-alert-1 { - temperature = <60000>; - hysteresis = <5000>; - type = "active"; - }; - cpu2_alert2: cpu-alert-2 { - temperature = <70000>; - hysteresis = <5000>; - type = "active"; - }; - cpu2_crit0: cpu-crit-0 { - temperature = <120000>; - hysteresis = <0>; - type = "critical"; - }; - cpu2_alert3: cpu-alert-3 { - temperature = <70000>; - hysteresis = <10000>; - type = "passive"; - }; - cpu2_alert4: cpu-alert-4 { - temperature = <85000>; - hysteresis = <10000>; - type = "passive"; - }; - }; - cooling-maps { - map0 { - trip = <&cpu2_alert0>; - cooling-device = <&fan0 0 1>; - }; - map1 { - trip = <&cpu2_alert1>; - cooling-device = <&fan0 1 2>; - }; - map2 { - trip = <&cpu2_alert2>; - cooling-device = <&fan0 2 3>; - }; - map3 { - trip = <&cpu2_alert3>; - cooling-device = <&cpu0 0 2>, - <&cpu1 0 2>, - <&cpu2 0 2>, - <&cpu3 0 2>, - <&cpu4 0 2>, - <&cpu5 0 2>, - <&cpu6 0 2>, - <&cpu7 0 2>; - }; - cpu2_cooling_map4: map4 { - trip = <&cpu2_alert4>; - cooling-device = <&cpu0 3 8>, - <&cpu1 3 8>, - <&cpu2 3 8>, - <&cpu3 3 8>, - <&cpu4 3 14>, - <&cpu5 3 14>, - <&cpu6 3 14>, - <&cpu7 3 14>; - }; - }; - }; - cpu3_thermal: cpu3-thermal { - thermal-sensors = <&tmu_cpu3 0>; - polling-delay-passive = <250>; - polling-delay = <0>; - trips { - cpu3_alert0: cpu-alert-0 { - temperature = <50000>; - hysteresis = <5000>; - type = "active"; - }; - cpu3_alert1: cpu-alert-1 { - temperature = <60000>; - hysteresis = <5000>; - type = "active"; - }; - cpu3_alert2: cpu-alert-2 { - temperature = <70000>; - hysteresis = <5000>; - type = "active"; - }; - cpu3_crit0: cpu-crit-0 { - temperature = <120000>; - hysteresis = <0>; - type = "critical"; - }; - cpu3_alert3: cpu-alert-3 { - temperature = <70000>; - hysteresis = <10000>; - type = "passive"; - }; - cpu3_alert4: cpu-alert-4 { - temperature = <85000>; - hysteresis = <10000>; - type = "passive"; - }; - }; - cooling-maps { - map0 { - trip = <&cpu3_alert0>; - cooling-device = <&fan0 0 1>; - }; - map1 { - trip = <&cpu3_alert1>; - cooling-device = <&fan0 1 2>; - }; - map2 { - trip = <&cpu3_alert2>; - cooling-device = <&fan0 2 3>; - }; - map3 { - trip = <&cpu3_alert3>; - cooling-device = <&cpu0 0 2>, - <&cpu1 0 2>, - <&cpu2 0 2>, - <&cpu3 0 2>, - <&cpu4 0 2>, - <&cpu5 0 2>, - <&cpu6 0 2>, - <&cpu7 0 2>; - }; - cpu3_cooling_map4: map4 { - trip = <&cpu3_alert4>; - cooling-device = <&cpu0 3 8>, - <&cpu1 3 8>, - <&cpu2 3 8>, - <&cpu3 3 8>, - <&cpu4 3 14>, - <&cpu5 3 14>, - <&cpu6 3 14>, - <&cpu7 3 14>; - }; - }; - }; - }; -}; - -&buck10_reg { - /* Supplies vmmc-supply of mmc_0 */ - regulator-always-on; - regulator-boot-on; -}; - -&hdmi { - status = "okay"; - ddc = <&i2c_2>; - hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_hpd_irq>; - - vdd_osc-supply = <&ldo7_reg>; - vdd_pll-supply = <&ldo6_reg>; - vdd-supply = <&ldo6_reg>; -}; - -&hdmicec { - status = "okay"; - needs-hpd; -}; - -&i2c_2 { - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <66000>; - /* used by HDMI DDC */ - status = "okay"; -}; - -&ldo26_reg { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; -}; - -&mixer { - status = "okay"; -}; - -&mmc_0 { - status = "okay"; - mmc-pwrseq = <&emmc_pwrseq>; - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <0 4>; - samsung,dw-mshc-ddr-timing = <0 2>; - samsung,dw-mshc-hs400-timing = <0 2>; - samsung,read-strobe-delay = <90>; - pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8 &sd0_cd &sd0_rclk>; - bus-width = <8>; - cap-mmc-highspeed; - mmc-hs200-1_8v; - mmc-hs400-1_8v; - max-frequency = <200000000>; - vmmc-supply = <&ldo18_reg>; - vqmmc-supply = <&ldo3_reg>; -}; - -&pinctrl_0 { - power_key: power-key { - samsung,pins = "gpx0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - hdmi_hpd_irq: hdmi-hpd-irq { - samsung,pins = "gpx3-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pinctrl_1 { - emmc_nrst_pin: emmc-nrst { - samsung,pins = "gpd1-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; diff --git a/sys/gnu/dts/arm/exynos5422-odroidxu3-lite.dts b/sys/gnu/dts/arm/exynos5422-odroidxu3-lite.dts deleted file mode 100644 index 98feecad548..00000000000 --- a/sys/gnu/dts/arm/exynos5422-odroidxu3-lite.dts +++ /dev/null @@ -1,105 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Hardkernel Odroid XU3-Lite board device tree source - * - * Copyright (c) 2015 Krzysztof Kozlowski - * Copyright (c) 2014 Collabora Ltd. - * Copyright (c) 2013 Samsung Electronics Co., Ltd. - * http://www.samsung.com - */ - -/dts-v1/; -#include "exynos5422-odroidxu3-common.dtsi" -#include "exynos5422-odroidxu3-audio.dtsi" -#include "exynos54xx-odroidxu-leds.dtsi" - -/ { - model = "Hardkernel Odroid XU3 Lite"; - compatible = "hardkernel,odroid-xu3-lite", "samsung,exynos5800", "samsung,exynos5"; -}; - -&arm_a7_pmu { - status = "disabled"; -}; - -&arm_a15_pmu { - status = "disabled"; -}; - -&chipid { - samsung,asv-bin = <2>; -}; - -/* - * Odroid XU3-Lite board uses SoC revision with lower maximum frequencies - * than Odroid XU3/XU4 boards: 1.8 GHz for A15 cores & 1.3 GHz for A7 cores. - * Therefore we need to update OPPs tables and thermal maps accordingly. - */ -&cluster_a15_opp_table { - /delete-node/opp-2000000000; - /delete-node/opp-1900000000; -}; - -&cluster_a7_opp_table { - /delete-node/opp-1400000000; -}; - -&cpu0_cooling_map4 { - cooling-device = <&cpu0 3 7>, - <&cpu1 3 7>, - <&cpu2 3 7>, - <&cpu3 3 7>, - <&cpu4 3 12>, - <&cpu5 3 12>, - <&cpu6 3 12>, - <&cpu7 3 12>; -}; - -&cpu1_cooling_map4 { - cooling-device = <&cpu0 3 7>, - <&cpu1 3 7>, - <&cpu2 3 7>, - <&cpu3 3 7>, - <&cpu4 3 12>, - <&cpu5 3 12>, - <&cpu6 3 12>, - <&cpu7 3 12>; -}; - -&cpu2_cooling_map4 { - cooling-device = <&cpu0 3 7>, - <&cpu1 3 7>, - <&cpu2 3 7>, - <&cpu3 3 7>, - <&cpu4 3 12>, - <&cpu5 3 12>, - <&cpu6 3 12>, - <&cpu7 3 12>; -}; - -&cpu3_cooling_map4 { - cooling-device = <&cpu0 3 7>, - <&cpu1 3 7>, - <&cpu2 3 7>, - <&cpu3 3 7>, - <&cpu4 3 12>, - <&cpu5 3 12>, - <&cpu6 3 12>, - <&cpu7 3 12>; -}; - -&pwm { - /* - * PWM 0 -- fan - * PWM 1 -- Green LED - * PWM 2 -- Blue LED - * PWM 3 -- on MIPI connector for backlight - */ - pinctrl-0 = <&pwm0_out &pwm1_out &pwm2_out &pwm3_out>; - pinctrl-names = "default"; - status = "okay"; -}; - -&usbdrd_dwc3_1 { - dr_mode = "peripheral"; -}; diff --git a/sys/gnu/dts/arm/exynos5422-odroidxu3.dts b/sys/gnu/dts/arm/exynos5422-odroidxu3.dts deleted file mode 100644 index db0bc17a667..00000000000 --- a/sys/gnu/dts/arm/exynos5422-odroidxu3.dts +++ /dev/null @@ -1,72 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Hardkernel Odroid XU3 board device tree source - * - * Copyright (c) 2014 Collabora Ltd. - * Copyright (c) 2013 Samsung Electronics Co., Ltd. - * http://www.samsung.com - */ - -/dts-v1/; -#include "exynos5422-odroidxu3-common.dtsi" -#include "exynos5422-odroidxu3-audio.dtsi" -#include "exynos54xx-odroidxu-leds.dtsi" - -/ { - model = "Hardkernel Odroid XU3"; - compatible = "hardkernel,odroid-xu3", "samsung,exynos5800", "samsung,exynos5"; -}; - -&i2c_0 { - status = "okay"; - - /* A15 cluster: VDD_ARM */ - ina231@40 { - compatible = "ti,ina231"; - reg = <0x40>; - shunt-resistor = <10000>; - }; - - /* memory: VDD_MEM */ - ina231@41 { - compatible = "ti,ina231"; - reg = <0x41>; - shunt-resistor = <10000>; - }; - - /* GPU: VDD_G3D */ - ina231@44 { - compatible = "ti,ina231"; - reg = <0x44>; - shunt-resistor = <10000>; - }; - - /* A7 cluster: VDD_KFC */ - ina231@45 { - compatible = "ti,ina231"; - reg = <0x45>; - shunt-resistor = <10000>; - }; -}; - -&ldo28_reg { - regulator-name = "dp_p3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; -}; - -&pwm { - /* - * PWM 0 -- fan - * PWM 1 -- Green LED - * PWM 2 -- Blue LED - * PWM 3 -- on MIPI connector for backlight - */ - pinctrl-0 = <&pwm0_out &pwm1_out &pwm2_out &pwm3_out>; - pinctrl-names = "default"; - status = "okay"; -}; - -&usbdrd_dwc3_1 { - dr_mode = "peripheral"; -}; diff --git a/sys/gnu/dts/arm/exynos5422-odroidxu4.dts b/sys/gnu/dts/arm/exynos5422-odroidxu4.dts deleted file mode 100644 index 892d389d6d0..00000000000 --- a/sys/gnu/dts/arm/exynos5422-odroidxu4.dts +++ /dev/null @@ -1,98 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Hardkernel Odroid XU4 board device tree source - * - * Copyright (c) 2015 Krzysztof Kozlowski - * Copyright (c) 2014 Collabora Ltd. - * Copyright (c) 2013-2015 Samsung Electronics Co., Ltd. - * http://www.samsung.com - */ - -/dts-v1/; -#include -#include "exynos5422-odroidxu3-common.dtsi" - -/ { - model = "Hardkernel Odroid XU4"; - compatible = "hardkernel,odroid-xu4", "samsung,exynos5800", \ - "samsung,exynos5"; - - pwmleds { - compatible = "pwm-leds"; - - blueled { - label = "blue:heartbeat"; - pwms = <&pwm 2 2000000 0>; - pwm-names = "pwm2"; - max_brightness = <255>; - linux,default-trigger = "heartbeat"; - }; - }; - - sound: sound { - compatible = "samsung,odroid-xu3-audio"; - model = "Odroid-XU4"; - - samsung,audio-routing = "I2S Playback", "Mixer DAI TX"; - - assigned-clocks = <&clock CLK_MOUT_EPLL>, - <&clock CLK_MOUT_MAU_EPLL>, - <&clock CLK_MOUT_USER_MAU_EPLL>, - <&clock_audss EXYNOS_MOUT_AUDSS>, - <&clock_audss EXYNOS_MOUT_I2S>, - <&clock_audss EXYNOS_DOUT_SRP>, - <&clock_audss EXYNOS_DOUT_AUD_BUS>, - <&clock_audss EXYNOS_DOUT_I2S>; - - assigned-clock-parents = <&clock CLK_FOUT_EPLL>, - <&clock CLK_MOUT_EPLL>, - <&clock CLK_MOUT_MAU_EPLL>, - <&clock CLK_MAU_EPLL>, - <&clock_audss EXYNOS_MOUT_AUDSS>; - - assigned-clock-rates = <0>, - <0>, - <0>, - <0>, - <0>, - <196608001>, - <(196608002 / 2)>, - <196608000>; - - cpu { - sound-dai = <&i2s0 0>, <&i2s0 1>; - }; - - codec { - sound-dai = <&hdmi>; - }; - }; -}; - -&clock_audss { - assigned-clocks = <&clock_audss EXYNOS_DOUT_SRP>, - <&clock CLK_FOUT_EPLL>; - assigned-clock-rates = <(196608000 / 256)>, - <196608000>; -}; - -&i2s0 { - status = "okay"; - assigned-clocks = <&i2s0 CLK_I2S_RCLK_SRC>; - assigned-clock-parents = <&clock_audss EXYNOS_SCLK_I2S>; -}; - -&pwm { - /* - * PWM 0 -- fan - * PWM 2 -- Blue LED - */ - pinctrl-0 = <&pwm0_out &pwm2_out>; - pinctrl-names = "default"; - samsung,pwm-outputs = <0>, <2>; - status = "okay"; -}; - -&usbdrd_dwc3_1 { - dr_mode = "host"; -}; diff --git a/sys/gnu/dts/arm/exynos5440-sd5v1.dts b/sys/gnu/dts/arm/exynos5440-sd5v1.dts deleted file mode 100644 index a98501bab6f..00000000000 --- a/sys/gnu/dts/arm/exynos5440-sd5v1.dts +++ /dev/null @@ -1,39 +0,0 @@ -/* - * SAMSUNG SD5v1 board device tree source - * - * Copyright (c) 2013 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -/dts-v1/; -#include "exynos5440.dtsi" - -/ { - model = "SAMSUNG SD5v1 board based on EXYNOS5440"; - compatible = "samsung,sd5v1", "samsung,exynos5440", "samsung,exynos5"; - - chosen { - bootargs = "root=/dev/sda2 rw rootwait ignore_loglevel earlyprintk no_console_suspend mem=2048M@0x80000000 mem=6144M@0x100000000 console=ttySAC0,115200"; - }; - - fixed-rate-clocks { - xtal { - compatible = "samsung,clock-xtal"; - clock-frequency = <50000000>; - }; - }; - - spi { - status = "disabled"; - }; - -}; - -&gmac { - fixed_phy; - phy_addr = <1>; -}; diff --git a/sys/gnu/dts/arm/exynos5440-ssdk5440.dts b/sys/gnu/dts/arm/exynos5440-ssdk5440.dts deleted file mode 100644 index 6a0d802e87c..00000000000 --- a/sys/gnu/dts/arm/exynos5440-ssdk5440.dts +++ /dev/null @@ -1,78 +0,0 @@ -/* - * SAMSUNG SSDK5440 board device tree source - * - * Copyright (c) 2012 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -/dts-v1/; -#include "exynos5440.dtsi" -#include - -/ { - model = "SAMSUNG SSDK5440 board based on EXYNOS5440"; - compatible = "samsung,ssdk5440", "samsung,exynos5440", "samsung,exynos5"; - - chosen { - bootargs = "root=/dev/sda2 rw rootwait ignore_loglevel earlyprintk no_console_suspend mem=2048M@0x80000000 mem=6144M@0x100000000 console=ttySAC0,115200"; - }; - - fixed-rate-clocks { - xtal { - compatible = "samsung,clock-xtal"; - clock-frequency = <50000000>; - }; - }; -}; - -&pcie_0 { - reset-gpio = <&pin_ctrl 5 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&pcie_1 { - reset-gpio = <&pin_ctrl 22 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&spi_0 { - flash: w25q128@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "winbond,w25q128"; - spi-max-frequency = <15625000>; - reg = <0>; - controller-data { - samsung,spi-feedback-delay = <0>; - }; - - partition@00000 { - label = "BootLoader"; - reg = <0x60000 0x80000>; - read-only; - }; - - partition@e0000 { - label = "Recovery-Kernel"; - reg = <0xe0000 0x300000>; - read-only; - }; - - partition@3e0000 { - label = "CRAM-FS"; - reg = <0x3e0000 0x700000>; - read-only; - }; - - partition@ae0000 { - label = "User-Data"; - reg = <0xae0000 0x520000>; - }; - - }; - -}; diff --git a/sys/gnu/dts/arm/exynos5440-tmu-sensor-conf.dtsi b/sys/gnu/dts/arm/exynos5440-tmu-sensor-conf.dtsi deleted file mode 100644 index 7b2fba0ae92..00000000000 --- a/sys/gnu/dts/arm/exynos5440-tmu-sensor-conf.dtsi +++ /dev/null @@ -1,24 +0,0 @@ -/* - * Device tree sources for Exynos5440 TMU sensor configuration - * - * Copyright (c) 2014 Lukasz Majewski - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -#include - -#thermal-sensor-cells = <0>; -samsung,tmu_gain = <5>; -samsung,tmu_reference_voltage = <16>; -samsung,tmu_noise_cancel_mode = <4>; -samsung,tmu_efuse_value = <0x5d2d>; -samsung,tmu_min_efuse_value = <16>; -samsung,tmu_max_efuse_value = <76>; -samsung,tmu_first_point_trim = <25>; -samsung,tmu_second_point_trim = <70>; -samsung,tmu_default_temp_offset = <25>; -samsung,tmu_cal_type = ; diff --git a/sys/gnu/dts/arm/exynos5440-trip-points.dtsi b/sys/gnu/dts/arm/exynos5440-trip-points.dtsi deleted file mode 100644 index 356e963edf1..00000000000 --- a/sys/gnu/dts/arm/exynos5440-trip-points.dtsi +++ /dev/null @@ -1,25 +0,0 @@ -/* - * Device tree sources for default Exynos5440 thermal zone definition - * - * Copyright (c) 2014 Lukasz Majewski - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -polling-delay-passive = <0>; -polling-delay = <0>; -trips { - cpu-alert-0 { - temperature = <100000>; /* millicelsius */ - hysteresis = <0>; /* millicelsius */ - type = "active"; - }; - cpu-crit-0 { - temperature = <105000>; /* millicelsius */ - hysteresis = <0>; /* millicelsius */ - type = "critical"; - }; -}; diff --git a/sys/gnu/dts/arm/exynos5440.dtsi b/sys/gnu/dts/arm/exynos5440.dtsi deleted file mode 100644 index f18b51f2eea..00000000000 --- a/sys/gnu/dts/arm/exynos5440.dtsi +++ /dev/null @@ -1,323 +0,0 @@ -/* - * SAMSUNG EXYNOS5440 SoC device tree source - * - * Copyright (c) 2012 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include -#include "skeleton.dtsi" - -/ { - compatible = "samsung,exynos5440", "samsung,exynos5"; - - interrupt-parent = <&gic>; - - aliases { - serial0 = &serial_0; - serial1 = &serial_1; - spi0 = &spi_0; - tmuctrl0 = &tmuctrl_0; - tmuctrl1 = &tmuctrl_1; - tmuctrl2 = &tmuctrl_2; - }; - - clock: clock-controller@160000 { - compatible = "samsung,exynos5440-clock"; - reg = <0x160000 0x1000>; - #clock-cells = <1>; - }; - - gic: interrupt-controller@2E0000 { - compatible = "arm,cortex-a15-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x2E1000 0x1000>, - <0x2E2000 0x1000>, - <0x2E4000 0x2000>, - <0x2E6000 0x2000>; - interrupts = <1 9 0xf04>; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0>; - }; - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <1>; - }; - cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <2>; - }; - cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <3>; - }; - }; - - arm-pmu { - compatible = "arm,cortex-a15-pmu", "arm,cortex-a9-pmu"; - interrupts = <0 52 4>, - <0 53 4>, - <0 54 4>, - <0 55 4>; - }; - - timer { - compatible = "arm,cortex-a15-timer", - "arm,armv7-timer"; - interrupts = <1 13 0xf08>, - <1 14 0xf08>, - <1 11 0xf08>, - <1 10 0xf08>; - clock-frequency = <50000000>; - }; - - cpufreq@160000 { - compatible = "samsung,exynos5440-cpufreq"; - reg = <0x160000 0x1000>; - interrupts = <0 57 0>; - operating-points = < - /* KHz uV */ - 1500000 1100000 - 1400000 1075000 - 1300000 1050000 - 1200000 1025000 - 1100000 1000000 - 1000000 975000 - 900000 950000 - 800000 925000 - >; - }; - - serial_0: serial@B0000 { - compatible = "samsung,exynos4210-uart"; - reg = <0xB0000 0x1000>; - interrupts = <0 2 0>; - clocks = <&clock CLK_B_125>, <&clock CLK_B_125>; - clock-names = "uart", "clk_uart_baud0"; - }; - - serial_1: serial@C0000 { - compatible = "samsung,exynos4210-uart"; - reg = <0xC0000 0x1000>; - interrupts = <0 3 0>; - clocks = <&clock CLK_B_125>, <&clock CLK_B_125>; - clock-names = "uart", "clk_uart_baud0"; - }; - - spi_0: spi@D0000 { - compatible = "samsung,exynos5440-spi"; - reg = <0xD0000 0x100>; - interrupts = <0 4 0>; - #address-cells = <1>; - #size-cells = <0>; - samsung,spi-src-clk = <0>; - num-cs = <1>; - clocks = <&clock CLK_B_125>, <&clock CLK_SPI_BAUD>; - clock-names = "spi", "spi_busclk0"; - }; - - pin_ctrl: pinctrl { - compatible = "samsung,exynos5440-pinctrl"; - reg = <0xE0000 0x1000>; - interrupts = <0 37 0>, <0 38 0>, <0 39 0>, <0 40 0>, - <0 41 0>, <0 42 0>, <0 43 0>, <0 44 0>; - interrupt-controller; - #interrupt-cells = <2>; - #gpio-cells = <2>; - - fan: fan { - samsung,exynos5440-pin-function = <1>; - }; - - hdd_led0: hdd_led0 { - samsung,exynos5440-pin-function = <2>; - }; - - hdd_led1: hdd_led1 { - samsung,exynos5440-pin-function = <3>; - }; - - uart1: uart1 { - samsung,exynos5440-pin-function = <4>; - }; - }; - - i2c@F0000 { - compatible = "samsung,exynos5440-i2c"; - reg = <0xF0000 0x1000>; - interrupts = <0 5 0>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clock CLK_B_125>; - clock-names = "i2c"; - }; - - i2c@100000 { - compatible = "samsung,exynos5440-i2c"; - reg = <0x100000 0x1000>; - interrupts = <0 6 0>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clock CLK_B_125>; - clock-names = "i2c"; - }; - - watchdog@110000 { - compatible = "samsung,s3c2410-wdt"; - reg = <0x110000 0x1000>; - interrupts = <0 1 0>; - clocks = <&clock CLK_B_125>; - clock-names = "watchdog"; - }; - - gmac: ethernet@00230000 { - compatible = "snps,dwmac-3.70a"; - reg = <0x00230000 0x8000>; - interrupt-parent = <&gic>; - interrupts = <0 31 4>; - interrupt-names = "macirq"; - phy-mode = "sgmii"; - clocks = <&clock CLK_GMAC0>; - clock-names = "stmmaceth"; - }; - - amba { - #address-cells = <1>; - #size-cells = <1>; - compatible = "arm,amba-bus"; - interrupt-parent = <&gic>; - ranges; - }; - - rtc { - compatible = "samsung,s3c6410-rtc"; - reg = <0x130000 0x1000>; - interrupts = <0 17 0>, <0 16 0>; - clocks = <&clock CLK_B_125>; - clock-names = "rtc"; - }; - - tmuctrl_0: tmuctrl@160118 { - compatible = "samsung,exynos5440-tmu"; - reg = <0x160118 0x230>, <0x160368 0x10>; - interrupts = <0 58 0>; - clocks = <&clock CLK_B_125>; - clock-names = "tmu_apbif"; - #include "exynos5440-tmu-sensor-conf.dtsi" - }; - - tmuctrl_1: tmuctrl@16011C { - compatible = "samsung,exynos5440-tmu"; - reg = <0x16011C 0x230>, <0x160368 0x10>; - interrupts = <0 58 0>; - clocks = <&clock CLK_B_125>; - clock-names = "tmu_apbif"; - #include "exynos5440-tmu-sensor-conf.dtsi" - }; - - tmuctrl_2: tmuctrl@160120 { - compatible = "samsung,exynos5440-tmu"; - reg = <0x160120 0x230>, <0x160368 0x10>; - interrupts = <0 58 0>; - clocks = <&clock CLK_B_125>; - clock-names = "tmu_apbif"; - #include "exynos5440-tmu-sensor-conf.dtsi" - }; - - thermal-zones { - cpu0_thermal: cpu0-thermal { - thermal-sensors = <&tmuctrl_0>; - #include "exynos5440-trip-points.dtsi" - }; - cpu1_thermal: cpu1-thermal { - thermal-sensors = <&tmuctrl_1>; - #include "exynos5440-trip-points.dtsi" - }; - cpu2_thermal: cpu2-thermal { - thermal-sensors = <&tmuctrl_2>; - #include "exynos5440-trip-points.dtsi" - }; - }; - - sata@210000 { - compatible = "snps,exynos5440-ahci"; - reg = <0x210000 0x10000>; - interrupts = <0 30 0>; - clocks = <&clock CLK_SATA>; - clock-names = "sata"; - }; - - ohci@220000 { - compatible = "samsung,exynos5440-ohci"; - reg = <0x220000 0x1000>; - interrupts = <0 29 0>; - clocks = <&clock CLK_USB>; - clock-names = "usbhost"; - }; - - ehci@221000 { - compatible = "samsung,exynos5440-ehci"; - reg = <0x221000 0x1000>; - interrupts = <0 29 0>; - clocks = <&clock CLK_USB>; - clock-names = "usbhost"; - }; - - pcie_0: pcie@290000 { - compatible = "samsung,exynos5440-pcie", "snps,dw-pcie"; - reg = <0x290000 0x1000 - 0x270000 0x1000 - 0x271000 0x40>; - interrupts = <0 20 0>, <0 21 0>, <0 22 0>; - clocks = <&clock CLK_PR0_250_O>, <&clock CLK_PB0_250_O>; - clock-names = "pcie", "pcie_bus"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges = <0x00000800 0 0x40000000 0x40000000 0 0x00001000 /* configuration space */ - 0x81000000 0 0 0x40001000 0 0x00010000 /* downstream I/O */ - 0x82000000 0 0x40011000 0x40011000 0 0x1ffef000>; /* non-prefetchable memory */ - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0x0 0 &gic 53>; - num-lanes = <4>; - status = "disabled"; - }; - - pcie_1: pcie@2a0000 { - compatible = "samsung,exynos5440-pcie", "snps,dw-pcie"; - reg = <0x2a0000 0x1000 - 0x272000 0x1000 - 0x271040 0x40>; - interrupts = <0 23 0>, <0 24 0>, <0 25 0>; - clocks = <&clock CLK_PR1_250_O>, <&clock CLK_PB0_250_O>; - clock-names = "pcie", "pcie_bus"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges = <0x00000800 0 0x60000000 0x60000000 0 0x00001000 /* configuration space */ - 0x81000000 0 0 0x60001000 0 0x00010000 /* downstream I/O */ - 0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>; /* non-prefetchable memory */ - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0x0 0 &gic 56>; - num-lanes = <4>; - status = "disabled"; - }; -}; diff --git a/sys/gnu/dts/arm/exynos54xx-odroidxu-leds.dtsi b/sys/gnu/dts/arm/exynos54xx-odroidxu-leds.dtsi deleted file mode 100644 index 56acd832f0b..00000000000 --- a/sys/gnu/dts/arm/exynos54xx-odroidxu-leds.dtsi +++ /dev/null @@ -1,47 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Hardkernel Odroid XU/XU3 LED device tree source - * - * Copyright (c) 2015,2016 Krzysztof Kozlowski - * Copyright (c) 2014 Collabora Ltd. - * Copyright (c) 2013 Samsung Electronics Co., Ltd. - * http://www.samsung.com - */ - -#include - -/ { - pwmleds { - compatible = "pwm-leds"; - - greenled { - label = "green:mmc0"; - pwms = <&pwm 1 2000000 0>; - pwm-names = "pwm1"; - /* - * Green LED is much brighter than the others - * so limit its max brightness - */ - max_brightness = <127>; - linux,default-trigger = "mmc0"; - }; - - blueled { - label = "blue:heartbeat"; - pwms = <&pwm 2 2000000 0>; - pwm-names = "pwm2"; - max_brightness = <255>; - linux,default-trigger = "heartbeat"; - }; - }; - - gpioleds { - compatible = "gpio-leds"; - redled { - label = "red:microSD"; - gpios = <&gpx2 3 GPIO_ACTIVE_HIGH>; - default-state = "off"; - linux,default-trigger = "mmc1"; - }; - }; -}; diff --git a/sys/gnu/dts/arm/exynos54xx.dtsi b/sys/gnu/dts/arm/exynos54xx.dtsi deleted file mode 100644 index 8aa5117e58c..00000000000 --- a/sys/gnu/dts/arm/exynos54xx.dtsi +++ /dev/null @@ -1,210 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's Exynos54xx SoC series common device tree source - * - * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * Copyright (c) 2016 Krzysztof Kozlowski - * - * Device nodes common for Samsung Exynos5410/5420/5422/5800. Specific - * Exynos 54xx SoCs should include this file and customize it further - * (e.g. with clocks). - */ - -#include "exynos5.dtsi" - -/ { - compatible = "samsung,exynos5"; - - aliases { - i2c4 = &hsi2c_4; - i2c5 = &hsi2c_5; - i2c6 = &hsi2c_6; - i2c7 = &hsi2c_7; - usbdrdphy0 = &usbdrd_phy0; - usbdrdphy1 = &usbdrd_phy1; - }; - - arm_a7_pmu: arm-a7-pmu { - compatible = "arm,cortex-a7-pmu"; - interrupt-parent = <&gic>; - interrupts = , - , - , - ; - status = "disabled"; - }; - - arm_a15_pmu: arm-a15-pmu { - compatible = "arm,cortex-a15-pmu"; - interrupt-parent = <&combiner>; - interrupts = <1 2>, - <7 0>, - <16 6>, - <19 2>; - status = "disabled"; - }; - - timer: timer { - compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; - clock-frequency = <24000000>; - }; - - soc: soc { - sram@2020000 { - compatible = "mmio-sram"; - reg = <0x02020000 0x54000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x02020000 0x54000>; - - smp-sram@0 { - compatible = "samsung,exynos4210-sysram"; - reg = <0x0 0x1000>; - }; - - smp-sram@53000 { - compatible = "samsung,exynos4210-sysram-ns"; - reg = <0x53000 0x1000>; - }; - }; - - mct: timer@101c0000 { - compatible = "samsung,exynos4210-mct"; - reg = <0x101c0000 0xb00>; - interrupts-extended = <&combiner 23 3>, - <&combiner 23 4>, - <&combiner 25 2>, - <&combiner 25 3>, - <&gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; - }; - - watchdog: watchdog@101d0000 { - compatible = "samsung,exynos5420-wdt"; - reg = <0x101d0000 0x100>; - interrupts = ; - }; - - adc: adc@12d10000 { - compatible = "samsung,exynos-adc-v2"; - reg = <0x12d10000 0x100>; - interrupts = ; - #io-channel-cells = <1>; - io-channel-ranges; - status = "disabled"; - }; - - /* i2c_0-3 are defined in exynos5.dtsi */ - hsi2c_4: i2c@12ca0000 { - compatible = "samsung,exynos5250-hsi2c"; - reg = <0x12ca0000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - hsi2c_5: i2c@12cb0000 { - compatible = "samsung,exynos5250-hsi2c"; - reg = <0x12cb0000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - hsi2c_6: i2c@12cc0000 { - compatible = "samsung,exynos5250-hsi2c"; - reg = <0x12cc0000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - hsi2c_7: i2c@12cd0000 { - compatible = "samsung,exynos5250-hsi2c"; - reg = <0x12cd0000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - usbdrd3_0: usb3-0 { - compatible = "samsung,exynos5250-dwusb3"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - usbdrd_dwc3_0: dwc3@12000000 { - compatible = "snps,dwc3"; - reg = <0x12000000 0x10000>; - interrupts = ; - phys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>; - phy-names = "usb2-phy", "usb3-phy"; - snps,dis_u3_susphy_quirk; - }; - }; - - usbdrd_phy0: phy@12100000 { - compatible = "samsung,exynos5420-usbdrd-phy"; - reg = <0x12100000 0x100>; - #phy-cells = <1>; - }; - - usbdrd3_1: usb3-1 { - compatible = "samsung,exynos5250-dwusb3"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - usbdrd_dwc3_1: dwc3@12400000 { - compatible = "snps,dwc3"; - reg = <0x12400000 0x10000>; - phys = <&usbdrd_phy1 0>, <&usbdrd_phy1 1>; - phy-names = "usb2-phy", "usb3-phy"; - snps,dis_u3_susphy_quirk; - }; - }; - - usbdrd_phy1: phy@12500000 { - compatible = "samsung,exynos5420-usbdrd-phy"; - reg = <0x12500000 0x100>; - #phy-cells = <1>; - }; - - usbhost2: usb@12110000 { - compatible = "samsung,exynos4210-ehci"; - reg = <0x12110000 0x100>; - interrupts = ; - phys = <&usb2_phy 1>; - phy-names = "host"; - }; - - usbhost1: usb@12120000 { - compatible = "samsung,exynos4210-ohci"; - reg = <0x12120000 0x100>; - interrupts = ; - phys = <&usb2_phy 1>; - phy-names = "host"; - }; - - usb2_phy: phy@12130000 { - compatible = "samsung,exynos5250-usb2-phy"; - reg = <0x12130000 0x100>; - #phy-cells = <1>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/exynos5800-peach-pi.dts b/sys/gnu/dts/arm/exynos5800-peach-pi.dts deleted file mode 100644 index 60ab0effe47..00000000000 --- a/sys/gnu/dts/arm/exynos5800-peach-pi.dts +++ /dev/null @@ -1,1100 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Google Peach Pi Rev 10+ board device tree source - * - * Copyright (c) 2014 Google, Inc - */ - -/dts-v1/; -#include -#include -#include -#include -#include -#include -#include "exynos5800.dtsi" -#include "exynos5420-cpus.dtsi" - -/ { - model = "Google Peach Pi Rev 10+"; - - compatible = "google,pi-rev16", - "google,pi-rev15", "google,pi-rev14", - "google,pi-rev13", "google,pi-rev12", - "google,pi-rev11", "google,pi-rev10", - "google,pi", "google,peach", "samsung,exynos5800", - "samsung,exynos5"; - - aliases { - /* Assign 20 so we don't get confused w/ builtin ones */ - i2c20 = &i2c_tunnel; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 0 1000000 0>; - brightness-levels = <0 100 500 1000 1500 2000 2500 2800>; - default-brightness-level = <7>; - enable-gpios = <&gpx2 2 GPIO_ACTIVE_HIGH>; - power-supply = <&tps65090_fet1>; - pinctrl-0 = <&pwm0_out>; - pinctrl-names = "default"; - }; - - chosen { - stdout-path = "serial3:115200n8"; - }; - - fixed-rate-clocks { - oscclk { - compatible = "samsung,exynos5420-oscclk"; - clock-frequency = <24000000>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - pinctrl-names = "default"; - pinctrl-0 = <&power_key_irq &lid_irq>; - - power { - label = "Power"; - gpios = <&gpx1 2 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - - lid-switch { - label = "Lid"; - gpios = <&gpx3 4 GPIO_ACTIVE_LOW>; - linux,input-type = <5>; /* EV_SW */ - linux,code = <0>; /* SW_LID */ - debounce-interval = <1>; - wakeup-source; - }; - - }; - - memory@20000000 { - device_type = "memory"; - reg = <0x20000000 0x80000000>; - }; - - sound { - compatible = "google,snow-audio-max98091"; - - samsung,model = "Peach-Pi-I2S-MAX98091"; - samsung,i2s-controller = <&i2s0>; - samsung,audio-codec = <&max98091>; - - cpu { - sound-dai = <&i2s0 0>; - }; - - codec { - sound-dai = <&max98091>, <&hdmi>; - }; - }; - - usb300_vbus_reg: regulator-usb300 { - compatible = "regulator-fixed"; - regulator-name = "P5.0V_USB3CON0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gph0 0 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&usb300_vbus_en>; - enable-active-high; - }; - - usb301_vbus_reg: regulator-usb301 { - compatible = "regulator-fixed"; - regulator-name = "P5.0V_USB3CON1"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gph0 1 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&usb301_vbus_en>; - enable-active-high; - }; - - vbat: fixed-regulator { - compatible = "regulator-fixed"; - regulator-name = "vbat-supply"; - regulator-boot-on; - regulator-always-on; - }; - - panel: panel { - compatible = "auo,b133htn01"; - power-supply = <&tps65090_fet6>; - backlight = <&backlight>; - - port { - panel_in: endpoint { - remote-endpoint = <&dp_out>; - }; - }; - }; - - mmc1_pwrseq: mmc1_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpx0 0 GPIO_ACTIVE_LOW>; /* WIFI_EN */ - clocks = <&max77802 MAX77802_CLK_32K_CP>; - clock-names = "ext_clock"; - }; -}; - -&adc { - status = "okay"; - vdd-supply = <&ldo9_reg>; -}; - -&clock_audss { - assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>; - assigned-clock-parents = <&clock CLK_MAU_EPLL>; -}; - -/* - * Peach Pi board uses SoC revision with lower maximum frequency for A7 cores - * (1.3 GHz instead of 1.4 GHz) than Odroid XU3/XU4 boards. Thus we need to - * update A7 OPPs table accordingly. - */ -&cluster_a7_opp_table { - /delete-node/opp-1400000000; -}; - -&cpu0 { - cpu-supply = <&buck2_reg>; -}; - -&cpu4 { - cpu-supply = <&buck6_reg>; -}; - -&dp { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&dp_hpd_gpio>; - samsung,color-space = <0>; - samsung,color-depth = <1>; - samsung,link-rate = <0x0a>; - samsung,lane-count = <2>; - samsung,hpd-gpio = <&gpx2 6 GPIO_ACTIVE_HIGH>; - - ports { - port { - dp_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; -}; - -&fimd { - status = "okay"; - samsung,invert-vclk; -}; - -&hdmi { - status = "okay"; - hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_hpd_irq>; - ddc = <&i2c_2>; - - hdmi-en-supply = <&tps65090_fet7>; - vdd-supply = <&ldo8_reg>; - vdd_osc-supply = <&ldo10_reg>; - vdd_pll-supply = <&ldo8_reg>; -}; - -&hsi2c_4 { - status = "okay"; - clock-frequency = <400000>; - - max77802: max77802-pmic@9 { - compatible = "maxim,max77802"; - interrupt-parent = <&gpx3>; - interrupts = <1 IRQ_TYPE_NONE>; - pinctrl-names = "default"; - pinctrl-0 = <&max77802_irq>, <&pmic_selb>, - <&pmic_dvs_1>, <&pmic_dvs_2>, <&pmic_dvs_3>; - wakeup-source; - reg = <0x9>; - #clock-cells = <1>; - - inb1-supply = <&tps65090_dcdc2>; - inb2-supply = <&tps65090_dcdc1>; - inb3-supply = <&tps65090_dcdc2>; - inb4-supply = <&tps65090_dcdc2>; - inb5-supply = <&tps65090_dcdc1>; - inb6-supply = <&tps65090_dcdc2>; - inb7-supply = <&tps65090_dcdc1>; - inb8-supply = <&tps65090_dcdc1>; - inb9-supply = <&tps65090_dcdc1>; - inb10-supply = <&tps65090_dcdc1>; - - inl1-supply = <&buck5_reg>; - inl2-supply = <&buck7_reg>; - inl3-supply = <&buck9_reg>; - inl4-supply = <&buck9_reg>; - inl5-supply = <&buck9_reg>; - inl6-supply = <&tps65090_dcdc2>; - inl7-supply = <&buck9_reg>; - inl9-supply = <&tps65090_dcdc2>; - inl10-supply = <&buck7_reg>; - - regulators { - buck1_reg: BUCK1 { - regulator-name = "vdd_mif"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - regulator-ramp-delay = <12500>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck2_reg: BUCK2 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - regulator-ramp-delay = <12500>; - regulator-coupled-with = <&buck3_reg>; - regulator-coupled-max-spread = <300000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck3_reg: BUCK3 { - regulator-name = "vdd_int"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-boot-on; - regulator-ramp-delay = <12500>; - regulator-coupled-with = <&buck2_reg>; - regulator-coupled-max-spread = <300000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck4_reg: BUCK4 { - regulator-name = "vdd_g3d"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-boot-on; - regulator-ramp-delay = <12500>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck5_reg: BUCK5 { - regulator-name = "vdd_1v2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck6_reg: BUCK6 { - regulator-name = "vdd_kfc"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - regulator-ramp-delay = <12500>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck7_reg: BUCK7 { - regulator-name = "vdd_1v35"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - buck8_reg: BUCK8 { - regulator-name = "vdd_emmc"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck9_reg: BUCK9 { - regulator-name = "vdd_2v"; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - buck10_reg: BUCK10 { - regulator-name = "vdd_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - ldo1_reg: LDO1 { - regulator-name = "vdd_1v0"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-mode = ; - }; - }; - - ldo2_reg: LDO2 { - regulator-name = "vdd_1v2_2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - ldo3_reg: LDO3 { - regulator-name = "vdd_1v8_3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-mode = ; - }; - }; - - vqmmc_sdcard: ldo4_reg: LDO4 { - regulator-name = "vdd_sd"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo5_reg: LDO5 { - regulator-name = "vdd_1v8_5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo6_reg: LDO6 { - regulator-name = "vdd_1v8_6"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo7_reg: LDO7 { - regulator-name = "vdd_1v8_7"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo8_reg: LDO8 { - regulator-name = "vdd_ldo8"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo9_reg: LDO9 { - regulator-name = "vdd_ldo9"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-mode = ; - }; - }; - - ldo10_reg: LDO10 { - regulator-name = "vdd_ldo10"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo11_reg: LDO11 { - regulator-name = "vdd_ldo11"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-mode = ; - }; - }; - - ldo12_reg: LDO12 { - regulator-name = "vdd_ldo12"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo13_reg: LDO13 { - regulator-name = "vdd_ldo13"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-mode = ; - }; - }; - - ldo14_reg: LDO14 { - regulator-name = "vdd_ldo14"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo15_reg: LDO15 { - regulator-name = "vdd_ldo15"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo17_reg: LDO17 { - regulator-name = "vdd_g3ds"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo18_reg: LDO18 { - regulator-name = "ldo_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo19_reg: LDO19 { - regulator-name = "ldo_19"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo20_reg: LDO20 { - regulator-name = "ldo_20"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo21_reg: LDO21 { - regulator-name = "ldo_21"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo23_reg: LDO23 { - regulator-name = "ldo_23"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - ldo24_reg: LDO24 { - regulator-name = "ldo_24"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo25_reg: LDO25 { - regulator-name = "ldo_25"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo26_reg: LDO26 { - regulator-name = "ldo_26"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - ldo27_reg: LDO27 { - regulator-name = "ldo_27"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - ldo28_reg: LDO28 { - regulator-name = "ldo_28"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo29_reg: LDO29 { - regulator-name = "ldo_29"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo30_reg: LDO30 { - regulator-name = "vdd_mifs"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo32_reg: LDO32 { - regulator-name = "ldo_32"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - ldo33_reg: LDO33 { - regulator-name = "ldo_33"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo34_reg: LDO34 { - regulator-name = "ldo_34"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - ldo35_reg: LDO35 { - regulator-name = "ldo_35"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - }; - }; -}; - -&hsi2c_7 { - status = "okay"; - clock-frequency = <400000>; - - max98091: codec@10 { - compatible = "maxim,max98091"; - reg = <0x10>; - interrupts = <2 IRQ_TYPE_NONE>; - interrupt-parent = <&gpx0>; - pinctrl-names = "default"; - pinctrl-0 = <&max98091_irq>; - clocks = <&pmu_system_controller 0>; - clock-names = "mclk"; - #sound-dai-cells = <0>; - }; - - light-sensor@44 { - compatible = "isil,isl29018"; - reg = <0x44>; - vcc-supply = <&tps65090_fet5>; - }; -}; - -&hsi2c_8 { - status = "okay"; - clock-frequency = <333000>; - /* Atmel mXT540S */ - trackpad@4b { - compatible = "atmel,maxtouch"; - reg = <0x4b>; - interrupt-parent = <&gpx1>; - interrupts = <1 IRQ_TYPE_EDGE_FALLING>; - wakeup-source; - pinctrl-names = "default"; - pinctrl-0 = <&trackpad_irq>; - linux,gpio-keymap = ; /* GPIO 3 */ - }; -}; - -&hsi2c_9 { - status = "okay"; - clock-frequency = <400000>; - - tpm@20 { - compatible = "infineon,slb9645tt"; - reg = <0x20>; - - /* Unused irq; but still need to configure the pins */ - pinctrl-names = "default"; - pinctrl-0 = <&tpm_irq>; - }; -}; - -&i2c_2 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <66000>; - samsung,i2c-slave-addr = <0x50>; -}; - -&i2s0 { - assigned-clocks = <&i2s0 CLK_I2S_RCLK_SRC>; - assigned-clock-parents = <&clock_audss EXYNOS_I2S_BUS>; - status = "okay"; -}; - -&mixer { - status = "okay"; -}; - -/* eMMC flash */ -&mmc_0 { - status = "okay"; - mmc-hs200-1_8v; - mmc-hs400-1_8v; - cap-mmc-highspeed; - non-removable; - clock-frequency = <800000000>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <0 4>; - samsung,dw-mshc-ddr-timing = <0 2>; - samsung,dw-mshc-hs400-timing = <0 2>; - samsung,read-strobe-delay = <90>; - pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8 &sd0_rclk>; - bus-width = <8>; -}; - -/* WiFi SDIO module */ -&mmc_1 { - status = "okay"; - non-removable; - cap-sdio-irq; - keep-power-in-suspend; - clock-frequency = <400000000>; - samsung,dw-mshc-ciu-div = <1>; - samsung,dw-mshc-sdr-timing = <0 1>; - samsung,dw-mshc-ddr-timing = <0 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd1_clk>, <&sd1_cmd>, <&sd1_int>, <&sd1_bus1>, - <&sd1_bus4>, <&sd1_bus8>, <&wifi_en>; - bus-width = <4>; - cap-sd-highspeed; - mmc-pwrseq = <&mmc1_pwrseq>; - vqmmc-supply = <&buck10_reg>; -}; - -/* uSD card */ -&mmc_2 { - status = "okay"; - cap-sd-highspeed; - card-detect-delay = <200>; - clock-frequency = <400000000>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>; - bus-width = <4>; -}; - - -&pinctrl_0 { - pinctrl-names = "default"; - pinctrl-0 = <&mask_tpm_reset>; - - wifi_en: wifi-en { - samsung,pins = "gpx0-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - max98091_irq: max98091-irq { - samsung,pins = "gpx0-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - /* We need GPX0_6 to be low at sleep time; just keep it low always */ - mask_tpm_reset: mask-tpm-reset { - samsung,pins = "gpx0-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - samsung,pin-val = <0>; - }; - - tpm_irq: tpm-irq { - samsung,pins = "gpx1-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - trackpad_irq: trackpad-irq { - samsung,pins = "gpx1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - power_key_irq: power-key-irq { - samsung,pins = "gpx1-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - ec_irq: ec-irq { - samsung,pins = "gpx1-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - tps65090_irq: tps65090-irq { - samsung,pins = "gpx2-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - dp_hpd_gpio: dp_hpd_gpio { - samsung,pins = "gpx2-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - max77802_irq: max77802-irq { - samsung,pins = "gpx3-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - lid_irq: lid-irq { - samsung,pins = "gpx3-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - hdmi_hpd_irq: hdmi-hpd-irq { - samsung,pins = "gpx3-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pmic_dvs_1: pmic-dvs-1 { - samsung,pins = "gpy7-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pinctrl_1 { - /* Adjust WiFi drive strengths lower for EMI */ - sd1_clk: sd1-clk { - samsung,pin-drv = ; - }; - - sd1_cmd: sd1-cmd { - samsung,pin-drv = ; - }; - - sd1_bus1: sd1-bus-width1 { - samsung,pin-drv = ; - }; - - sd1_bus4: sd1-bus-width4 { - samsung,pin-drv = ; - }; - - sd1_bus8: sd1-bus-width8 { - samsung,pin-drv = ; - }; -}; - -&pinctrl_2 { - pmic_dvs_2: pmic-dvs-2 { - samsung,pins = "gpj4-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pmic_dvs_3: pmic-dvs-3 { - samsung,pins = "gpj4-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pinctrl_3 { - /* Drive SPI lines at x2 for better integrity */ - spi2-bus { - samsung,pin-drv = ; - }; - - /* Drive SPI chip select at x2 for better integrity */ - ec_spi_cs: ec-spi-cs { - samsung,pins = "gpb1-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - usb300_vbus_en: usb300-vbus-en { - samsung,pins = "gph0-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - usb301_vbus_en: usb301-vbus-en { - samsung,pins = "gph0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pmic_selb: pmic-selb { - samsung,pins = "gph0-2", "gph0-3", "gph0-4", "gph0-5", - "gph0-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pmu_system_controller { - assigned-clocks = <&pmu_system_controller 0>; - assigned-clock-parents = <&clock CLK_FIN_PLL>; -}; - -&rtc { - status = "okay"; - clocks = <&clock CLK_RTC>, <&max77802 MAX77802_CLK_32K_AP>; - clock-names = "rtc", "rtc_src"; -}; - -&spi_2 { - status = "okay"; - num-cs = <1>; - samsung,spi-src-clk = <0>; - cs-gpios = <&gpb1 2 GPIO_ACTIVE_HIGH>; - - cros_ec: cros-ec@0 { - compatible = "google,cros-ec-spi"; - interrupt-parent = <&gpx1>; - interrupts = <5 IRQ_TYPE_NONE>; - pinctrl-names = "default"; - pinctrl-0 = <&ec_spi_cs &ec_irq>; - reg = <0>; - spi-max-frequency = <3125000>; - google,has-vbc-nvram; - - controller-data { - samsung,spi-feedback-delay = <1>; - }; - - i2c_tunnel: i2c-tunnel { - compatible = "google,cros-ec-i2c-tunnel"; - #address-cells = <1>; - #size-cells = <0>; - google,remote-bus = <0>; - - battery: sbs-battery@b { - compatible = "sbs,sbs-battery"; - reg = <0xb>; - sbs,poll-retry-count = <1>; - sbs,i2c-retry-count = <2>; - }; - - power-regulator@48 { - compatible = "ti,tps65090"; - reg = <0x48>; - - /* - * Config irq to disable internal pulls - * even though we run in polling mode. - */ - pinctrl-names = "default"; - pinctrl-0 = <&tps65090_irq>; - - vsys1-supply = <&vbat>; - vsys2-supply = <&vbat>; - vsys3-supply = <&vbat>; - infet1-supply = <&vbat>; - infet2-supply = <&tps65090_dcdc1>; - infet3-supply = <&tps65090_dcdc2>; - infet4-supply = <&tps65090_dcdc2>; - infet5-supply = <&tps65090_dcdc2>; - infet6-supply = <&tps65090_dcdc2>; - infet7-supply = <&tps65090_dcdc1>; - vsys-l1-supply = <&vbat>; - vsys-l2-supply = <&vbat>; - - regulators { - tps65090_dcdc1: dcdc1 { - ti,enable-ext-control; - }; - tps65090_dcdc2: dcdc2 { - ti,enable-ext-control; - }; - tps65090_dcdc3: dcdc3 { - ti,enable-ext-control; - }; - tps65090_fet1: fet1 { - regulator-name = "vcd_led"; - }; - tps65090_fet2: fet2 { - regulator-name = "video_mid"; - regulator-always-on; - }; - tps65090_fet3: fet3 { - regulator-name = "wwan_r"; - regulator-always-on; - }; - tps65090_fet4: fet4 { - regulator-name = "sdcard"; - regulator-always-on; - }; - tps65090_fet5: fet5 { - regulator-name = "camout"; - regulator-always-on; - }; - tps65090_fet6: fet6 { - regulator-name = "lcd_vdd"; - }; - tps65090_fet7: fet7 { - regulator-name = "video_mid_1a"; - regulator-always-on; - }; - tps65090_ldo1: ldo1 { - }; - tps65090_ldo2: ldo2 { - }; - }; - - charger { - compatible = "ti,tps65090-charger"; - }; - }; - }; - }; -}; - -&serial_3 { - status = "okay"; -}; - -&timer { - arm,cpu-registers-not-fw-configured; -}; - -&tmu_cpu0 { - vtmu-supply = <&ldo10_reg>; -}; - -&tmu_cpu1 { - vtmu-supply = <&ldo10_reg>; -}; - -&tmu_cpu2 { - vtmu-supply = <&ldo10_reg>; -}; - -&tmu_cpu3 { - vtmu-supply = <&ldo10_reg>; -}; - -&tmu_gpu { - vtmu-supply = <&ldo10_reg>; -}; - -&usbdrd_dwc3_0 { - dr_mode = "host"; -}; - -&usbdrd_dwc3_1 { - dr_mode = "host"; -}; - -&usbdrd_phy0 { - vbus-supply = <&usb300_vbus_reg>; -}; - -&usbdrd_phy1 { - vbus-supply = <&usb301_vbus_reg>; -}; - -/* - * Use longest HW watchdog in SoC (32 seconds) since the hardware - * watchdog provides no debugging information (compared to soft/hard - * lockup detectors) and so should be last resort. - */ -&watchdog { - timeout-sec = <32>; -}; - -#include "cros-ec-keyboard.dtsi" -#include "cros-adc-thermistors.dtsi" diff --git a/sys/gnu/dts/arm/exynos5800.dtsi b/sys/gnu/dts/arm/exynos5800.dtsi deleted file mode 100644 index dfb99ab53c3..00000000000 --- a/sys/gnu/dts/arm/exynos5800.dtsi +++ /dev/null @@ -1,162 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung Exynos5800 SoC device tree source - * - * Copyright (c) 2014 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Samsung Exynos5800 SoC device nodes are listed in this file. - * Exynos5800 based board files can include this file and provide - * values for board specfic bindings. - */ - -#include "exynos5420.dtsi" - -/ { - compatible = "samsung,exynos5800", "samsung,exynos5"; -}; - -&clock { - compatible = "samsung,exynos5800-clock", "syscon"; -}; - -&cluster_a15_opp_table { - opp-2000000000 { - opp-hz = /bits/ 64 <2000000000>; - opp-microvolt = <1312500>; - clock-latency-ns = <140000>; - }; - opp-1900000000 { - opp-hz = /bits/ 64 <1900000000>; - opp-microvolt = <1262500>; - clock-latency-ns = <140000>; - }; - opp-1800000000 { - opp-hz = /bits/ 64 <1800000000>; - opp-microvolt = <1237500>; - clock-latency-ns = <140000>; - }; - opp-1700000000 { - opp-microvolt = <1250000 1250000 1500000>; - }; - opp-1600000000 { - opp-microvolt = <1250000 1250000 1500000>; - }; - opp-1500000000 { - opp-microvolt = <1100000 1100000 1500000>; - }; - opp-1400000000 { - opp-microvolt = <1100000 1100000 1500000>; - }; - opp-1300000000 { - opp-microvolt = <1100000 1100000 1500000>; - }; - opp-1200000000 { - opp-microvolt = <1000000 1000000 1500000>; - }; - opp-1100000000 { - opp-microvolt = <1000000 1000000 1500000>; - }; - opp-1000000000 { - opp-microvolt = <1000000 1000000 1500000>; - }; - opp-900000000 { - opp-microvolt = <1000000 1000000 1500000>; - }; - opp-800000000 { - opp-microvolt = <900000 900000 1500000>; - }; - opp-700000000 { - opp-microvolt = <900000 900000 1500000>; - }; - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <900000 900000 1500000>; - clock-latency-ns = <140000>; - }; - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <900000 900000 1500000>; - clock-latency-ns = <140000>; - }; - opp-400000000 { - opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <900000 900000 1500000>; - clock-latency-ns = <140000>; - }; - opp-300000000 { - opp-hz = /bits/ 64 <300000000>; - opp-microvolt = <900000 900000 1500000>; - clock-latency-ns = <140000>; - }; - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - opp-microvolt = <900000 900000 1500000>; - clock-latency-ns = <140000>; - }; -}; - -&cluster_a7_opp_table { - opp-1400000000 { - opp-hz = /bits/ 64 <1400000000>; - opp-microvolt = <1275000>; - clock-latency-ns = <140000>; - }; - opp-1300000000 { - opp-microvolt = <1250000>; - }; - opp-1200000000 { - opp-microvolt = <1250000>; - }; - opp-1100000000 { - opp-microvolt = <1250000>; - }; - opp-1000000000 { - opp-microvolt = <1100000>; - }; - opp-900000000 { - opp-microvolt = <1100000>; - }; - opp-800000000 { - opp-microvolt = <1100000>; - }; - opp-700000000 { - opp-microvolt = <1000000>; - }; - opp-600000000 { - opp-microvolt = <1000000>; - }; - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <1000000>; - clock-latency-ns = <140000>; - }; - opp-400000000 { - opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <1000000>; - clock-latency-ns = <140000>; - }; - opp-300000000 { - opp-hz = /bits/ 64 <300000000>; - opp-microvolt = <900000>; - clock-latency-ns = <140000>; - }; - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - opp-microvolt = <900000>; - clock-latency-ns = <140000>; - }; -}; - -&mfc { - compatible = "samsung,mfc-v8"; -}; - -&soc { - cam_pd: power-domain@10045100 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10045100 0x20>; - #power-domain-cells = <0>; - label = "CAM"; - }; -}; diff --git a/sys/gnu/dts/arm/facebook-bmc-flash-layout.dtsi b/sys/gnu/dts/arm/facebook-bmc-flash-layout.dtsi deleted file mode 100644 index 87bb8b57625..00000000000 --- a/sys/gnu/dts/arm/facebook-bmc-flash-layout.dtsi +++ /dev/null @@ -1,42 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// Copyright (c) 2018 Facebook Inc. - -partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - u-boot@0 { - reg = <0x0 0x60000>; - label = "u-boot"; - }; - - u-boot-env@60000 { - reg = <0x60000 0x20000>; - label = "env"; - }; - - fit@80000 { - reg = <0x80000 0x1b80000>; - label = "fit"; - }; - - /* - * "data0" partition is used by several Facebook BMC platforms - * as persistent data store. - */ - data0@1c00000 { - reg = <0x1c00000 0x400000>; - label = "data0"; - }; - - /* - * Although the master partition can be created by enabling - * MTD_PARTITIONED_MASTER option, below "flash0" partition is - * explicitly created to avoid breaking legacy applications. - */ - flash0@0 { - reg = <0x0 0x2000000>; - label = "flash0"; - }; -}; diff --git a/sys/gnu/dts/arm/ge863-pro3.dtsi b/sys/gnu/dts/arm/ge863-pro3.dtsi deleted file mode 100644 index dbba33e5a06..00000000000 --- a/sys/gnu/dts/arm/ge863-pro3.dtsi +++ /dev/null @@ -1,77 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * ge863_pro3.dtsi - Device Tree file for Telit GE863-PRO3 - * - * Copyright (C) 2012 Telit, - * 2012 Fabio Porcedda - */ - -#include "at91sam9260.dtsi" - -/ { - clocks { - main_xtal { - clock-frequency = <6000000>; - }; - }; - - ahb { - apb { - tcb0: timer@fffa0000 { - timer@0 { - compatible = "atmel,tcb-timer"; - reg = <0>, <1>; - }; - - timer@2 { - compatible = "atmel,tcb-timer"; - reg = <2>; - }; - }; - - dbgu: serial@fffff200 { - status = "okay"; - }; - }; - - ebi: ebi@10000000 { - status = "okay"; - - nand_controller: nand-controller { - status = "okay"; - pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>; - pinctrl-names = "default"; - - nand@3 { - reg = <0x3 0x0 0x800000>; - rb-gpios = <&pioC 13 GPIO_ACTIVE_HIGH>; - cs-gpios = <&pioC 14 GPIO_ACTIVE_HIGH>; - nand-bus-width = <8>; - nand-ecc-mode = "soft"; - nand-on-flash-bbt; - label = "atmel_nand"; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot@0 { - label = "boot"; - reg = <0x0 0x7c0000>; - }; - - root@7c0000 { - label = "root"; - reg = <0x7c0000 0x7840000>; - }; - }; - }; - }; - }; - }; - - chosen { - bootargs = "console=ttyS0,115200 root=ubi0:rootfs ubi.mtd=1 rootfstype=ubifs"; - }; -}; diff --git a/sys/gnu/dts/arm/gemini-dlink-dir-685.dts b/sys/gnu/dts/arm/gemini-dlink-dir-685.dts deleted file mode 100644 index e2030ba1651..00000000000 --- a/sys/gnu/dts/arm/gemini-dlink-dir-685.dts +++ /dev/null @@ -1,469 +0,0 @@ -/* - * Device Tree file for D-Link DIR-685 Xtreme N Storage Router - */ - -/dts-v1/; - -#include "gemini.dtsi" -#include - -/ { - model = "D-Link DIR-685 Xtreme N Storage Router"; - compatible = "dlink,dir-685", "cortina,gemini"; - #address-cells = <1>; - #size-cells = <1>; - - memory@0 { - /* 128 MB SDRAM in 2 x Hynix HY5DU121622DTP-D43 */ - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - chosen { - bootargs = "console=ttyS0,19200n8 root=/dev/sda1 rw rootwait consoleblank=300"; - stdout-path = "uart0:19200n8"; - }; - - gpio_keys { - compatible = "gpio-keys"; - - button-esc { - debounce-interval = <100>; - wakeup-source; - linux,code = ; - label = "reset"; - /* Collides with LPC_LAD[0], UART DCD, SSP 97RST */ - gpios = <&gpio0 8 GPIO_ACTIVE_LOW>; - }; - button-eject { - debounce-interval = <100>; - wakeup-source; - linux,code = ; - label = "unmount"; - /* Collides with LPC LFRAME, UART RTS, SSP TXD */ - gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; - }; - }; - - vdisp: regulator { - compatible = "regulator-fixed"; - regulator-name = "display-power"; - regulator-min-microvolt = <3600000>; - regulator-max-microvolt = <3600000>; - /* Collides with LCD E */ - gpio = <&gpio0 16 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - spi { - compatible = "spi-gpio"; - #address-cells = <1>; - #size-cells = <0>; - - /* Collides with IDE pins, that's cool (we do not use them) */ - gpio-sck = <&gpio1 5 GPIO_ACTIVE_HIGH>; - gpio-miso = <&gpio1 8 GPIO_ACTIVE_HIGH>; - gpio-mosi = <&gpio1 7 GPIO_ACTIVE_HIGH>; - cs-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; - num-chipselects = <1>; - - panel: display@0 { - compatible = "dlink,dir-685-panel", "ilitek,ili9322"; - reg = <0>; - /* 50 ns min period = 20 MHz */ - spi-max-frequency = <20000000>; - vcc-supply = <&vdisp>; - iovcc-supply = <&vdisp>; - vci-supply = <&vdisp>; - - port { - panel_in: endpoint { - remote-endpoint = <&display_out>; - }; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - led-wps { - label = "dir685:blue:WPS"; - /* Collides with ICE */ - gpios = <&gpio0 7 GPIO_ACTIVE_LOW>; - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - /* - * These two LEDs are on the side of the device. - * For electrical reasons, both LEDs cannot be active - * at the same time so only blue or orange can be on at - * one time. Enabling both makes the LED go dark. - * The LEDs both sit inside the unmount button and the - * label on the case says "unmount". - */ - led-blue-hd { - label = "dir685:blue:HD"; - /* Collides with LPC_SERIRQ, UART DTR, SSP FSC pins */ - gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>; - default-state = "off"; - linux,default-trigger = "disk-read"; - }; - led-orange-hd { - label = "dir685:orange:HD"; - /* Collides with LPC_LAD[2], UART DSR, SSP ECLK pins */ - gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; - default-state = "off"; - linux,default-trigger = "disk-write"; - }; - }; - - /* - * This is a Sunon Maglev GM0502PFV2-8 cooling fan @10000 RPM. - * Since the platform has no temperature sensor, this is controlled - * from userspace by using the hard disks S.M.A.R.T. temperature - * sensor. It is turned on when the temperature exceeds 46 degrees - * and turned off when the temperatures goes below 41 degrees - * (celsius). - */ - gpio-fan { - compatible = "gpio-fan"; - /* Collides with IDE */ - gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; - gpio-fan,speed-map = <0 0>, <10000 1>; - #cooling-cells = <2>; - }; - - /* - * The touchpad input is connected to a GPIO bit-banged - * I2C bus. - */ - gpio-i2c { - compatible = "i2c-gpio"; - /* Collides with ICE */ - sda-gpios = <&gpio0 5 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpio0 6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - #address-cells = <1>; - #size-cells = <0>; - - touchkeys@26 { - compatible = "dlink,dir685-touchkeys"; - reg = <0x26>; - interrupt-parent = <&gpio0>; - /* Collides with NAND flash */ - interrupts = <17 IRQ_TYPE_EDGE_FALLING>; - }; - }; - - /* This is a RealTek RTL8366RB switch and PHY using SMI over GPIO */ - switch { - compatible = "realtek,rtl8366rb"; - /* 22 = MDIO (has input reads), 21 = MDC (clock, output only) */ - mdc-gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>; - mdio-gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; - realtek,disable-leds; - - switch_intc: interrupt-controller { - /* GPIO 15 provides the interrupt */ - interrupt-parent = <&gpio0>; - interrupts = <15 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "lan0"; - phy-handle = <&phy0>; - }; - port@1 { - reg = <1>; - label = "lan1"; - phy-handle = <&phy1>; - }; - port@2 { - reg = <2>; - label = "lan2"; - phy-handle = <&phy2>; - }; - port@3 { - reg = <3>; - label = "lan3"; - phy-handle = <&phy3>; - }; - port@4 { - reg = <4>; - label = "wan"; - phy-handle = <&phy4>; - }; - rtl8366rb_cpu_port: port@5 { - reg = <5>; - label = "cpu"; - ethernet = <&gmac0>; - phy-mode = "rgmii"; - fixed-link { - speed = <1000>; - full-duplex; - pause; - }; - }; - - }; - - mdio { - compatible = "realtek,smi-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - phy0: phy@0 { - reg = <0>; - interrupt-parent = <&switch_intc>; - interrupts = <0>; - }; - phy1: phy@1 { - reg = <1>; - interrupt-parent = <&switch_intc>; - interrupts = <1>; - }; - phy2: phy@2 { - reg = <2>; - interrupt-parent = <&switch_intc>; - interrupts = <2>; - }; - phy3: phy@3 { - reg = <3>; - interrupt-parent = <&switch_intc>; - interrupts = <3>; - }; - phy4: phy@4 { - reg = <4>; - interrupt-parent = <&switch_intc>; - interrupts = <12>; - }; - }; - }; - - soc { - flash@30000000 { - /* - * Flash access collides with the Chip Enable signal for - * the display panel, that reuse the parallel flash Chip - * Select 1 (CS1). We switch the pin control state so we - * enable these pins for flash access only when we need - * then, and when disabled they can be used for GPIO which - * is what the display panel needs. - */ - status = "okay"; - pinctrl-names = "enabled", "disabled"; - pinctrl-0 = <&pflash_default_pins>; - pinctrl-1 = <&pflash_disabled_pins>; - - /* 32MB of flash */ - reg = <0x30000000 0x02000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* - * This "RedBoot" is the Storlink derivative. - */ - partition@0 { - label = "RedBoot"; - reg = <0x00000000 0x00040000>; - read-only; - }; - /* - * This firmware image contains the kernel catenated - * with the squashfs root filesystem. For some reason - * this is called "upgrade" on the vendor system. - */ - partition@40000 { - label = "upgrade"; - reg = <0x00040000 0x01f40000>; - read-only; - }; - /* RGDB, Residental Gateway Database? */ - partition@1f80000 { - label = "rgdb"; - reg = <0x01f80000 0x00040000>; - read-only; - }; - /* - * This partition contains MAC addresses for WAN, - * WLAN and LAN, and the country code (for wireless - * I guess). - */ - partition@1fc0000 { - label = "nvram"; - reg = <0x01fc0000 0x00020000>; - read-only; - }; - partition@1fe0000 { - label = "LangPack"; - reg = <0x01fe0000 0x00020000>; - read-only; - }; - }; - }; - - syscon: syscon@40000000 { - pinctrl { - /* - * gpio0bgrp cover line 5, 6 used by TK I2C - * gpio0bgrp cover line 7 used by WPS LED - * gpio0cgrp cover line 8, 13 used by keys - * and 11, 12 used by the HD LEDs - * and line 14, 15 used by RTL8366 - * RESET and phy ready - * gpio0egrp cover line 16 used by VDISP - * gpio0fgrp cover line 17 used by TK IRQ - * gpio0ggrp cover line 20 used by panel CS - * gpio0hgrp cover line 21,22 used by RTL8366RB MDIO - */ - gpio0_default_pins: pinctrl-gpio0 { - mux { - function = "gpio0"; - groups = "gpio0bgrp", - "gpio0cgrp", - "gpio0egrp", - "gpio0fgrp", - "gpio0hgrp"; - }; - }; - /* - * gpio1bgrp cover line 5,8,7 used by panel SPI - * also line 6 used by the fan - * - */ - gpio1_default_pins: pinctrl-gpio1 { - mux { - function = "gpio1"; - groups = "gpio1bgrp"; - }; - }; - /* - * These GPIO groups will be mapped in over some - * of the flash pins when the flash is not in - * active use. - */ - pflash_disabled_pins: pinctrl-pflash-disabled { - mux { - function = "gpio0"; - groups = "gpio0ggrp", "gpio0igrp", "gpio0jgrp", - "gpio0kgrp"; - }; - }; - pinctrl-gmii { - mux { - function = "gmii"; - groups = "gmii_gmac0_grp"; - }; - conf0 { - pins = "V8 GMAC0 RXDV", "T10 GMAC1 RXDV", - "Y7 GMAC0 RXC", "Y11 GMAC1 RXC", - "T8 GMAC0 TXEN", "W11 GMAC1 TXEN", - "U8 GMAC0 TXC", "V11 GMAC1 TXC", - "W8 GMAC0 RXD0", "V9 GMAC0 RXD1", - "Y8 GMAC0 RXD2", "U9 GMAC0 RXD3", - "T7 GMAC0 TXD0", "U6 GMAC0 TXD1", - "V7 GMAC0 TXD2", "U7 GMAC0 TXD3", - "Y12 GMAC1 RXD0", "V12 GMAC1 RXD1", - "T11 GMAC1 RXD2", "W12 GMAC1 RXD3", - "U10 GMAC1 TXD0", "Y10 GMAC1 TXD1", - "W10 GMAC1 TXD2", "T9 GMAC1 TXD3"; - skew-delay = <7>; - }; - /* Set up drive strength on GMAC0 to 16 mA */ - conf1 { - groups = "gmii_gmac0_grp"; - drive-strength = <16>; - }; - }; - }; - }; - - sata: sata@46000000 { - cortina,gemini-ata-muxmode = <0>; - cortina,gemini-enable-sata-bridge; - status = "okay"; - }; - - gpio0: gpio@4d000000 { - pinctrl-names = "default"; - pinctrl-0 = <&gpio0_default_pins>; - }; - - gpio1: gpio@4e000000 { - pinctrl-names = "default"; - pinctrl-0 = <&gpio1_default_pins>; - }; - - pci@50000000 { - status = "okay"; - interrupt-map-mask = <0xf800 0 0 7>; - interrupt-map = - <0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */ - <0x4800 0 0 2 &pci_intc 1>, - <0x4800 0 0 3 &pci_intc 2>, - <0x4800 0 0 4 &pci_intc 3>, - <0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */ - <0x5000 0 0 2 &pci_intc 2>, - <0x5000 0 0 3 &pci_intc 3>, - <0x5000 0 0 4 &pci_intc 0>, - <0x5800 0 0 1 &pci_intc 2>, /* Slot 11 */ - <0x5800 0 0 2 &pci_intc 3>, - <0x5800 0 0 3 &pci_intc 0>, - <0x5800 0 0 4 &pci_intc 1>, - <0x6000 0 0 1 &pci_intc 3>, /* Slot 12 */ - <0x6000 0 0 2 &pci_intc 0>, - <0x6000 0 0 3 &pci_intc 1>, - <0x6000 0 0 4 &pci_intc 2>; - }; - - ethernet@60000000 { - status = "okay"; - - ethernet-port@0 { - phy-mode = "rgmii"; - fixed-link { - speed = <1000>; - full-duplex; - pause; - }; - }; - ethernet-port@1 { - /* Not used in this platform */ - }; - }; - - ata@63000000 { - status = "okay"; - }; - - display-controller@6a000000 { - status = "okay"; - - port@0 { - reg = <0>; - display_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; - - usb@68000000 { - status = "okay"; - }; - - usb@69000000 { - status = "okay"; - }; - }; -}; diff --git a/sys/gnu/dts/arm/gemini-dlink-dns-313.dts b/sys/gnu/dts/arm/gemini-dlink-dns-313.dts deleted file mode 100644 index 360642a02a4..00000000000 --- a/sys/gnu/dts/arm/gemini-dlink-dns-313.dts +++ /dev/null @@ -1,304 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree file for D-Link DNS-313 1-Bay Network Storage Enclosure - */ - -/dts-v1/; - -#include "gemini.dtsi" -#include -#include - -/ { - model = "D-Link DNS-313 1-Bay Network Storage Enclosure"; - compatible = "dlink,dns-313", "cortina,gemini"; - #address-cells = <1>; - #size-cells = <1>; - - memory@0 { - /* 64 MB SDRAM in a Nanya NT5DS32M16BS-6K package */ - device_type = "memory"; - reg = <0x00000000 0x4000000>; - }; - - aliases { - mdio-gpio0 = &mdio0; - }; - - chosen { - bootargs = "console=ttyS0,19200n8 root=/dev/sda4 rw rootwait"; - stdout-path = "uart0:19200n8"; - }; - - gpio_keys { - compatible = "gpio-keys"; - - button-esc { - debounce-interval = <100>; - wakeup-source; - linux,code = ; - label = "reset"; - gpios = <&gpio1 31 GPIO_ACTIVE_LOW>; - }; - }; - - leds { - compatible = "gpio-leds"; - led-power { - label = "dns313:blue:power"; - gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - led-disk-blue { - label = "dns313:blue:disk"; - gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - led-disk-green { - label = "dns313:green:disk"; - gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>; - default-state = "off"; - linux,default-trigger = "disk-read"; - }; - led-disk-red { - label = "dns313:red:disk"; - gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>; - default-state = "off"; - linux,default-trigger = "disk-write"; - }; - }; - - /* - * This is a ADDA AD0405GB-G73 fan @3000 and 6000 RPM. - */ - fan0: gpio-fan { - compatible = "gpio-fan"; - gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>, - <&gpio0 12 GPIO_ACTIVE_HIGH>; - gpio-fan,speed-map = <0 0>, <3000 1>, <6000 2>; - #cooling-cells = <2>; - }; - - - /* Global Mixed-Mode Technology G751 mounted on GPIO I2C */ - gpio-i2c { - compatible = "i2c-gpio"; - sda-gpios = <&gpio0 15 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpio0 16 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - #address-cells = <1>; - #size-cells = <0>; - - g751: temperature-sensor@48 { - compatible = "gmt,g751"; - reg = <0x48>; - #thermal-sensor-cells = <0>; - }; - }; - - thermal-zones { - chassis-thermal { - /* Poll every 20 seconds */ - polling-delay = <20000>; - /* Poll every 2nd second when cooling */ - polling-delay-passive = <2000>; - - thermal-sensors = <&g751>; - - /* Tripping points from the fan.script in the rootfs */ - trips { - chassis_alert0: chassis-alert0 { - /* At 43 degrees turn on low speed */ - temperature = <43000>; - hysteresis = <3000>; - type = "active"; - }; - chassis_alert1: chassis-alert1 { - /* At 47 degrees turn on high speed */ - temperature = <47000>; - hysteresis = <3000>; - type = "active"; - }; - chassis_crit: chassis-crit { - /* Just shut down at 60 degrees */ - temperature = <60000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&chassis_alert0>; - cooling-device = <&fan0 1 1>; - }; - map1 { - trip = <&chassis_alert1>; - cooling-device = <&fan0 2 2>; - }; - }; - }; - }; - - mdio0: ethernet-phy { - compatible = "virtual,mdio-gpio"; - /* Uses MDC and MDIO */ - gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */ - <&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */ - #address-cells = <1>; - #size-cells = <0>; - - /* This is a Realtek RTL8211B Gigabit ethernet transceiver */ - phy0: ethernet-phy@1 { - reg = <1>; - device_type = "ethernet-phy"; - }; - }; - - soc { - flash@30000000 { - /* - * This is a Eon EN29LV400AB 512 KiB flash with - * three partitions. - */ - compatible = "cortina,gemini-flash", "jedec-flash"; - status = "okay"; - reg = <0x30000000 0x00080000>; - - /* - * This "RedBoot" is the Storlink derivative. - */ - partition@0 { - label = "RedBoot"; - reg = <0x00000000 0x00040000>; - read-only; - }; - partition@40000 { - label = "MTD1"; - reg = <0x00040000 0x00020000>; - read-only; - }; - partition@60000 { - label = "MTD2"; - reg = <0x00060000 0x00020000>; - read-only; - }; - }; - - syscon: syscon@40000000 { - pinctrl { - /* - */ - gpio0_default_pins: pinctrl-gpio0 { - mux { - function = "gpio0"; - groups = - /* Used by LEDs conflicts ICE */ - "gpio0bgrp", - /* Used by ? conflicts ICE */ - "gpio0cgrp", - /* - * Used by fan & G751, conflicts LPC, - * UART modem lines, SSP - */ - "gpio0egrp", - /* Used by G751 */ - "gpio0fgrp", - /* Used by MDIO */ - "gpio0igrp"; - }; - }; - gpio1_default_pins: pinctrl-gpio1 { - mux { - function = "gpio1"; - /* Used by "reset" button */ - groups = "gpio1dgrp"; - }; - }; - pinctrl-gmii { - mux { - function = "gmii"; - groups = "gmii_gmac0_grp"; - }; - /* - * In the vendor Linux tree, these values are set for the C3 - * version of the SL3512 ASIC with the comment "benson suggest" - */ - conf0 { - pins = "R8 GMAC0 RXDV", "U11 GMAC1 RXDV"; - skew-delay = <0>; - }; - conf1 { - pins = "T8 GMAC0 RXC"; - skew-delay = <10>; - }; - conf2 { - pins = "T11 GMAC1 RXC"; - skew-delay = <15>; - }; - conf3 { - pins = "P8 GMAC0 TXEN", "V11 GMAC1 TXEN"; - skew-delay = <7>; - }; - conf4 { - pins = "V7 GMAC0 TXC", "P10 GMAC1 TXC"; - skew-delay = <10>; - }; - conf5 { - /* The data lines all have default skew */ - pins = "U8 GMAC0 RXD0", "V8 GMAC0 RXD1", - "P9 GMAC0 RXD2", "R9 GMAC0 RXD3", - "R11 GMAC1 RXD0", "P11 GMAC1 RXD1", - "V12 GMAC1 RXD2", "U12 GMAC1 RXD3", - "R10 GMAC1 TXD0", "T10 GMAC1 TXD1", - "U10 GMAC1 TXD2", "V10 GMAC1 TXD3"; - skew-delay = <7>; - }; - conf6 { - pins = "U7 GMAC0 TXD0", "T7 GMAC0 TXD1", - "R7 GMAC0 TXD2", "P7 GMAC0 TXD3"; - skew-delay = <5>; - }; - /* Set up drive strength on GMAC0 to 16 mA */ - conf7 { - groups = "gmii_gmac0_grp"; - drive-strength = <16>; - }; - }; - }; - }; - - sata: sata@46000000 { - /* The ROM uses this muxmode */ - cortina,gemini-ata-muxmode = <0>; - cortina,gemini-enable-sata-bridge; - status = "okay"; - }; - - gpio0: gpio@4d000000 { - pinctrl-names = "default"; - pinctrl-0 = <&gpio0_default_pins>; - }; - - gpio1: gpio@4e000000 { - pinctrl-names = "default"; - pinctrl-0 = <&gpio1_default_pins>; - }; - - ethernet@60000000 { - status = "okay"; - - ethernet-port@0 { - phy-mode = "rgmii"; - phy-handle = <&phy0>; - }; - ethernet-port@1 { - /* Not used in this platform */ - }; - }; - - ata@63000000 { - status = "okay"; - }; - }; -}; diff --git a/sys/gnu/dts/arm/gemini-nas4220b.dts b/sys/gnu/dts/arm/gemini-nas4220b.dts deleted file mode 100644 index 521714f38ee..00000000000 --- a/sys/gnu/dts/arm/gemini-nas4220b.dts +++ /dev/null @@ -1,189 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree file for the Gemini-based Raidsonic NAS IB-4220-B - */ - -/dts-v1/; - -#include "gemini.dtsi" -#include - -/ { - model = "Raidsonic NAS IB-4220-B"; - compatible = "raidsonic,ib-4220-b", "cortina,gemini"; - #address-cells = <1>; - #size-cells = <1>; - - memory@0 { /* 128 MB */ - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - chosen { - bootargs = "console=ttyS0,19200n8 root=/dev/mtdblock3 rw rootfstype=squashfs,jffs2 rootwait"; - stdout-path = &uart0; - }; - - gpio_keys { - compatible = "gpio-keys"; - - button-setup { - debounce-interval = <100>; - wakeup-source; - linux,code = ; - label = "Backup button"; - /* Conflict with TVC */ - gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; - }; - button-restart { - debounce-interval = <100>; - wakeup-source; - linux,code = ; - label = "Softreset button"; - /* Conflict with TVC */ - gpios = <&gpio1 31 GPIO_ACTIVE_LOW>; - }; - }; - - leds { - compatible = "gpio-leds"; - led-orange-hdd { - label = "nas4220b:orange:hdd"; - /* Conflict with TVC */ - gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - led-green-os { - label = "nas4220b:green:os"; - /* Conflict with TVC */ - gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - }; - - mdio0: ethernet-phy { - compatible = "virtual,mdio-gpio"; - gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */ - <&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */ - #address-cells = <1>; - #size-cells = <0>; - - phy0: ethernet-phy@1 { - reg = <1>; - device_type = "ethernet-phy"; - }; - }; - - soc { - flash@30000000 { - status = "okay"; - /* 16MB of flash */ - reg = <0x30000000 0x01000000>; - - partitions { - compatible = "redboot-fis"; - /* Eraseblock at 0xfe0000 */ - fis-index-block = <0x1fc>; - }; - }; - - syscon: syscon@40000000 { - pinctrl { - /* - * gpio1dgrp cover line 28-31 otherwise used - * by TVC. - */ - gpio1_default_pins: pinctrl-gpio1 { - mux { - function = "gpio1"; - groups = "gpio1dgrp"; - }; - }; - pinctrl-gmii { - mux { - function = "gmii"; - groups = "gmii_gmac0_grp"; - }; - /* Settings come from OpenWRT, pins on SL3516 */ - conf0 { - pins = "V8 GMAC0 RXDV", "T10 GMAC1 RXDV"; - skew-delay = <0>; - }; - conf1 { - pins = "Y7 GMAC0 RXC", "Y11 GMAC1 RXC"; - skew-delay = <15>; - }; - conf2 { - pins = "T8 GMAC0 TXEN", "W11 GMAC1 TXEN"; - skew-delay = <7>; - }; - conf3 { - pins = "U8 GMAC0 TXC"; - skew-delay = <11>; - }; - conf4 { - pins = "V11 GMAC1 TXC"; - skew-delay = <10>; - }; - conf5 { - /* The data lines all have default skew */ - pins = "W8 GMAC0 RXD0", "V9 GMAC0 RXD1", - "Y8 GMAC0 RXD2", "U9 GMAC0 RXD3", - "T7 GMAC0 TXD0", "U6 GMAC0 TXD1", - "V7 GMAC0 TXD2", "U7 GMAC0 TXD3", - "Y12 GMAC1 RXD0", "V12 GMAC1 RXD1", - "T11 GMAC1 RXD2", "W12 GMAC1 RXD3", - "U10 GMAC1 TXD0", "Y10 GMAC1 TXD1", - "W10 GMAC1 TXD2", "T9 GMAC1 TXD3"; - skew-delay = <7>; - }; - /* Set up drive strength on GMAC0 to 16 mA */ - conf6 { - groups = "gmii_gmac0_grp"; - drive-strength = <16>; - }; - }; - }; - }; - - sata: sata@46000000 { - cortina,gemini-ata-muxmode = <0>; - cortina,gemini-enable-sata-bridge; - status = "okay"; - }; - - gpio1: gpio@4e000000 { - pinctrl-names = "default"; - pinctrl-0 = <&gpio1_default_pins>; - }; - - ethernet@60000000 { - status = "okay"; - - ethernet-port@0 { - phy-mode = "rgmii"; - phy-handle = <&phy0>; - }; - ethernet-port@1 { - /* Not used in this platform */ - }; - }; - - ata@63000000 { - status = "okay"; - }; - - ata@63400000 { - status = "okay"; - }; - - usb@68000000 { - status = "okay"; - }; - - usb@69000000 { - status = "okay"; - }; - }; -}; diff --git a/sys/gnu/dts/arm/gemini-rut1xx.dts b/sys/gnu/dts/arm/gemini-rut1xx.dts deleted file mode 100644 index 9611ddf0679..00000000000 --- a/sys/gnu/dts/arm/gemini-rut1xx.dts +++ /dev/null @@ -1,148 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree file for Teltonika RUT1xx - */ - -/dts-v1/; - -#include "gemini.dtsi" -#include - -/ { - model = "Teltonika RUT1xx"; - compatible = "teltonika,rut1xx", "cortina,gemini"; - #address-cells = <1>; - #size-cells = <1>; - - memory@0 { /* 128 MB */ - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - gpio_keys { - compatible = "gpio-keys"; - - button-setup { - debounce-interval = <100>; - wakeup-source; - linux,code = ; - label = "Reset to defaults"; - /* Conflict with TVC */ - gpios = <&gpio1 28 GPIO_ACTIVE_LOW>; - }; - }; - - leds { - compatible = "gpio-leds"; - led-gsm { - /* FIXME: add the LED color */ - label = "rut1xx::gsm"; - /* Conflict with ICE */ - gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - led-power { - /* FIXME: add the LED color */ - label = "rut1xx::power"; - /* Conflict with NAND CE0 */ - gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>; - default-state = "off"; - linux,default-trigger = "heartbeat"; - }; - }; - - mdio0: ethernet-phy { - compatible = "virtual,mdio-gpio"; - gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */ - <&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */ - #address-cells = <1>; - #size-cells = <0>; - - phy0: ethernet-phy@1 { - reg = <1>; - device_type = "ethernet-phy"; - }; - }; - - soc { - flash@30000000 { - status = "okay"; - /* 8MB of flash */ - reg = <0x30000000 0x00800000>; - /* TODO: add flash partitions here */ - }; - - syscon: syscon@40000000 { - pinctrl { - /* - * gpio0bgrp cover line 7 used by GSM LED - * gpio0fgrp cover line 17 used by power LED - */ - gpio0_default_pins: pinctrl-gpio0 { - mux { - function = "gpio0"; - groups = "gpio0bgrp", - "gpio0fgrp"; - }; - }; - /* - * gpio1dgrp cover line 28-31 otherwise used - * by TVC. - */ - gpio1_default_pins: pinctrl-gpio1 { - mux { - function = "gpio1"; - groups = "gpio1dgrp"; - }; - }; - }; - }; - - gpio0: gpio@4d000000 { - pinctrl-names = "default"; - pinctrl-0 = <&gpio0_default_pins>; - }; - - gpio1: gpio@4e000000 { - pinctrl-names = "default"; - pinctrl-0 = <&gpio1_default_pins>; - }; - - ethernet@60000000 { - status = "okay"; - - ethernet-port@0 { - phy-mode = "rgmii"; - phy-handle = <&phy0>; - }; - ethernet-port@1 { - /* Not used in this platform */ - }; - }; - - ethernet@60000000 { - status = "okay"; - - ethernet-port@0 { - phy-mode = "rgmii"; - phy-handle = <&phy0>; - }; - ethernet-port@1 { - /* Not used in this platform */ - }; - }; - - usb@68000000 { - status = "okay"; - }; - - usb@69000000 { - status = "okay"; - }; - }; -}; diff --git a/sys/gnu/dts/arm/gemini-sl93512r.dts b/sys/gnu/dts/arm/gemini-sl93512r.dts deleted file mode 100644 index a98af035190..00000000000 --- a/sys/gnu/dts/arm/gemini-sl93512r.dts +++ /dev/null @@ -1,312 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree file for the Storm Semiconductor SL93512R_BRD - * Gemini reference design, also initially called - * "Gemini324 EV-Board" before Storm acquired Storlink Semiconductor. - * The series were later acquired by Cortina Systems. - */ - -/dts-v1/; - -#include "gemini.dtsi" -#include - -/ { - model = "Storlink Semiconductor Gemini324 EV-Board / Storm Semiconductor SL93512R_BRD"; - compatible = "storlink,gemini324", "storm,sl93512r", "cortina,gemini"; - #address-cells = <1>; - #size-cells = <1>; - - memory@0 { - /* 64 MB Samsung K4H511638B */ - device_type = "memory"; - reg = <0x00000000 0x4000000>; - }; - - chosen { - bootargs = "console=ttyS0,19200n8 root=/dev/mtdblock3 rw rootfstype=squashfs,jffs2 rootwait"; - stdout-path = &uart0; - }; - - gpio_keys { - compatible = "gpio-keys"; - - button-wps { - debounce-interval = <50>; - wakeup-source; - linux,code = ; - label = "WPS"; - /* Conflicts with TVC and extended flash */ - gpios = <&gpio0 0 GPIO_ACTIVE_LOW>; - }; - - button-setup { - debounce-interval = <50>; - wakeup-source; - linux,code = ; - label = "factory reset"; - /* Conflict with NAND flash */ - gpios = <&gpio0 18 GPIO_ACTIVE_LOW>; - }; - }; - - leds { - compatible = "gpio-leds"; - led-green-harddisk { - label = "sq201:green:harddisk"; - /* Conflict with LCD (no problem) */ - gpios = <&gpio0 16 GPIO_ACTIVE_LOW>; - default-state = "off"; - linux,default-trigger = "disk-activity"; - }; - led-green-wireless { - label = "sq201:green:wireless"; - /* Conflict with NAND flash CE0 (no problem) */ - gpios = <&gpio0 17 GPIO_ACTIVE_LOW>; - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - }; - - mdio0: mdio { - compatible = "virtual,mdio-gpio"; - /* Uses MDC and MDIO */ - gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */ - <&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */ - #address-cells = <1>; - #size-cells = <0>; - - /* This is a Marvell 88E1111 ethernet transciever */ - phy0: ethernet-phy@1 { - reg = <1>; - }; - }; - - spi { - compatible = "spi-gpio"; - #address-cells = <1>; - #size-cells = <0>; - /* Check pin collisions */ - gpio-sck = <&gpio1 28 GPIO_ACTIVE_HIGH>; - gpio-miso = <&gpio1 30 GPIO_ACTIVE_HIGH>; - gpio-mosi = <&gpio1 29 GPIO_ACTIVE_HIGH>; - cs-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>; - num-chipselects = <1>; - - switch@0 { - compatible = "vitesse,vsc7385"; - reg = <0>; - /* Specified for 2.5 MHz or below */ - spi-max-frequency = <2500000>; - gpio-controller; - #gpio-cells = <2>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "lan1"; - }; - port@1 { - reg = <1>; - label = "lan2"; - }; - port@2 { - reg = <2>; - label = "lan3"; - }; - port@3 { - reg = <3>; - label = "lan4"; - }; - vsc: port@6 { - reg = <6>; - label = "cpu"; - ethernet = <&gmac1>; - phy-mode = "rgmii"; - fixed-link { - speed = <1000>; - full-duplex; - pause; - }; - }; - }; - }; - }; - - - soc { - flash@30000000 { - status = "okay"; - /* 16MB of flash */ - reg = <0x30000000 0x01000000>; - - partitions { - compatible = "redboot-fis"; - /* Eraseblock at 0xfe0000 */ - fis-index-block = <0x1fc>; - }; - }; - - syscon: syscon@40000000 { - pinctrl { - /* - * gpio0agrp cover line 0, used by WPS button - * gpio0fgrp cover line 16 used by HD LED - * gpio0ggrp cover line 17, 18 used by wireless LAN LED and - * reset button OR USB ID select on 17 and USB VBUS select - * on 18. (Confusing.) - * gpio0igrp cover line 21, 22 used by MDIO for Marvell PHY - */ - gpio0_default_pins: pinctrl-gpio0 { - mux { - function = "gpio0"; - groups = "gpio0agrp", - "gpio0fgrp", - "gpio0ggrp", - "gpio0igrp"; - }; - }; - /* - * gpio1dgrp cover lines used by SPI for - * the Vitesse chip (28-31) - */ - gpio1_default_pins: pinctrl-gpio1 { - mux { - function = "gpio1"; - groups = "gpio1dgrp"; - }; - }; - pinctrl-gmii { - mux { - function = "gmii"; - groups = "gmii_gmac0_grp", "gmii_gmac1_grp"; - }; - /* Control pad skew comes from sl_switch.c in the vendor code */ - conf0 { - pins = "P10 GMAC1 TXC"; - skew-delay = <5>; - }; - conf1 { - pins = "V11 GMAC1 TXEN"; - skew-delay = <7>; - }; - conf2 { - pins = "T11 GMAC1 RXC"; - skew-delay = <8>; - }; - conf3 { - pins = "U11 GMAC1 RXDV"; - skew-delay = <7>; - }; - conf4 { - pins = "V7 GMAC0 TXC"; - skew-delay = <10>; - }; - conf5 { - pins = "P8 GMAC0 TXEN"; - skew-delay = <7>; /* 5 at another place? */ - }; - conf6 { - pins = "T8 GMAC0 RXC"; - skew-delay = <15>; - }; - conf7 { - pins = "R8 GMAC0 RXDV"; - skew-delay = <0>; - }; - conf8 { - /* The data lines all have default skew */ - pins = "U8 GMAC0 RXD0", "V8 GMAC0 RXD1", - "P9 GMAC0 RXD2", "R9 GMAC0 RXD3", - "R11 GMAC1 RXD0", "P11 GMAC1 RXD1", - "V12 GMAC1 RXD2", "U12 GMAC1 RXD3", - "R10 GMAC1 TXD0", "T10 GMAC1 TXD1", - "U10 GMAC1 TXD2", "V10 GMAC1 TXD3"; - skew-delay = <7>; - }; - /* Appears in sl351x_gmac.c in the vendor code */ - conf9 { - pins = "U7 GMAC0 TXD0", "T7 GMAC0 TXD1", - "R7 GMAC0 TXD2", "P7 GMAC0 TXD3"; - skew-delay = <5>; - }; - }; - }; - }; - - /* Both interfaces brought out on SATA connectors */ - sata: sata@46000000 { - cortina,gemini-ata-muxmode = <0>; - cortina,gemini-enable-sata-bridge; - status = "okay"; - }; - - gpio0: gpio@4d000000 { - pinctrl-names = "default"; - pinctrl-0 = <&gpio0_default_pins>; - }; - - gpio1: gpio@4e000000 { - pinctrl-names = "default"; - pinctrl-0 = <&gpio1_default_pins>; - }; - - pci@50000000 { - status = "okay"; - interrupt-map-mask = <0xf800 0 0 7>; - interrupt-map = - <0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */ - <0x4800 0 0 2 &pci_intc 1>, - <0x4800 0 0 3 &pci_intc 2>, - <0x4800 0 0 4 &pci_intc 3>, - <0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */ - <0x5000 0 0 2 &pci_intc 2>, - <0x5000 0 0 3 &pci_intc 3>, - <0x5000 0 0 4 &pci_intc 0>, - <0x5800 0 0 1 &pci_intc 2>, /* Slot 11 */ - <0x5800 0 0 2 &pci_intc 3>, - <0x5800 0 0 3 &pci_intc 0>, - <0x5800 0 0 4 &pci_intc 1>, - <0x6000 0 0 1 &pci_intc 3>, /* Slot 12 */ - <0x6000 0 0 2 &pci_intc 0>, - <0x6000 0 0 3 &pci_intc 1>, - <0x6000 0 0 4 &pci_intc 2>; - }; - - ethernet@60000000 { - status = "okay"; - - ethernet-port@0 { - phy-mode = "rgmii"; - phy-handle = <&phy0>; - }; - ethernet-port@1 { - phy-mode = "rgmii"; - fixed-link { - speed = <1000>; - full-duplex; - pause; - }; - }; - }; - - ata@63000000 { - status = "okay"; - }; - - ata@63400000 { - status = "okay"; - }; - - usb@68000000 { - status = "okay"; - }; - - usb@69000000 { - status = "okay"; - }; - }; -}; diff --git a/sys/gnu/dts/arm/gemini-sq201.dts b/sys/gnu/dts/arm/gemini-sq201.dts deleted file mode 100644 index 239dfacaae4..00000000000 --- a/sys/gnu/dts/arm/gemini-sq201.dts +++ /dev/null @@ -1,304 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree file for ITian Square One SQ201 NAS - */ - -/dts-v1/; - -#include "gemini.dtsi" -#include - -/ { - model = "ITian Square One SQ201"; - compatible = "itian,sq201", "cortina,gemini"; - #address-cells = <1>; - #size-cells = <1>; - - memory@0 { /* 128 MB */ - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8 root=/dev/mtdblock2 rw rootfstype=squashfs,jffs2 rootwait"; - stdout-path = &uart0; - }; - - gpio_keys { - compatible = "gpio-keys"; - - button-setup { - debounce-interval = <100>; - wakeup-source; - linux,code = ; - label = "factory reset"; - /* Conflict with NAND flash */ - gpios = <&gpio0 18 GPIO_ACTIVE_LOW>; - }; - }; - - leds { - compatible = "gpio-leds"; - led-green-info { - label = "sq201:green:info"; - gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>; - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - led-green-usb { - label = "sq201:green:usb"; - gpios = <&gpio0 31 GPIO_ACTIVE_HIGH>; - default-state = "off"; - linux,default-trigger = "usb-host"; - }; - }; - - mdio0: mdio { - compatible = "virtual,mdio-gpio"; - /* Uses MDC and MDIO */ - gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */ - <&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */ - #address-cells = <1>; - #size-cells = <0>; - - /* This is a Marvell 88E1111 ethernet transciever */ - phy0: ethernet-phy@1 { - reg = <1>; - }; - }; - - spi { - compatible = "spi-gpio"; - #address-cells = <1>; - #size-cells = <0>; - /* Check pin collisions */ - gpio-sck = <&gpio1 28 GPIO_ACTIVE_HIGH>; - gpio-miso = <&gpio1 30 GPIO_ACTIVE_HIGH>; - gpio-mosi = <&gpio1 29 GPIO_ACTIVE_HIGH>; - cs-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>; - num-chipselects = <1>; - - switch@0 { - compatible = "vitesse,vsc7395"; - reg = <0>; - /* Specified for 2.5 MHz or below */ - spi-max-frequency = <2500000>; - gpio-controller; - #gpio-cells = <2>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "lan1"; - }; - port@1 { - reg = <1>; - label = "lan2"; - }; - port@2 { - reg = <2>; - label = "lan3"; - }; - port@3 { - reg = <3>; - label = "lan4"; - }; - vsc: port@6 { - reg = <6>; - label = "cpu"; - ethernet = <&gmac1>; - phy-mode = "rgmii"; - fixed-link { - speed = <1000>; - full-duplex; - pause; - }; - }; - }; - }; - }; - - - soc { - flash@30000000 { - status = "okay"; - pinctrl-names = "enabled", "disabled"; - pinctrl-0 = <&pflash_default_pins>; - pinctrl-1 = <&pflash_disabled_pins>; - /* 16MB of flash */ - reg = <0x30000000 0x01000000>; - - partitions { - compatible = "redboot-fis"; - /* Eraseblock at 0xfe0000 */ - fis-index-block = <0x1fc>; - }; - }; - - syscon: syscon@40000000 { - pinctrl { - /* - * gpio0fgrp cover line 18 used by reset button - * gpio0ggrp cover line 20 used by info LED - * gpio0hgrp cover line 21, 22 used by MDIO for Marvell PHY - * gpio0kgrp cover line 31 used by USB LED - */ - gpio0_default_pins: pinctrl-gpio0 { - mux { - function = "gpio0"; - groups = "gpio0fgrp", - "gpio0hgrp"; - }; - }; - /* - * gpio0dgrp cover lines used by the SPI - * to the Vitesse G5x chip. - */ - gpio1_default_pins: pinctrl-gpio1 { - mux { - function = "gpio1"; - groups = "gpio1dgrp"; - }; - }; - /* - * These GPIO groups will be mapped in over some - * of the flash pins when the flash is not in - * active use. - */ - pflash_disabled_pins: pinctrl-pflash-disabled { - mux { - function = "gpio0"; - groups = "gpio0ggrp", "gpio0igrp", "gpio0jgrp", - "gpio0kgrp"; - }; - }; - pinctrl-gmii { - mux { - function = "gmii"; - groups = "gmii_gmac0_grp", "gmii_gmac1_grp"; - }; - /* Settings come from memory dump in PLATO */ - conf0 { - pins = "V8 GMAC0 RXDV"; - skew-delay = <0>; - }; - conf1 { - pins = "Y7 GMAC0 RXC"; - skew-delay = <15>; - }; - conf2 { - pins = "T8 GMAC0 TXEN"; - skew-delay = <7>; - }; - conf3 { - pins = "U8 GMAC0 TXC"; - skew-delay = <10>; - }; - conf4 { - pins = "T10 GMAC1 RXDV"; - skew-delay = <7>; - }; - conf5 { - pins = "Y11 GMAC1 RXC"; - skew-delay = <8>; - }; - conf6 { - pins = "W11 GMAC1 TXEN"; - skew-delay = <7>; - }; - conf7 { - pins = "V11 GMAC1 TXC"; - skew-delay = <5>; - }; - conf8 { - /* The data lines all have default skew */ - pins = "W8 GMAC0 RXD0", "V9 GMAC0 RXD1", - "Y8 GMAC0 RXD2", "U9 GMAC0 RXD3", - "T7 GMAC0 TXD0", "U6 GMAC0 TXD1", - "V7 GMAC0 TXD2", "U7 GMAC0 TXD3", - "Y12 GMAC1 RXD0", "V12 GMAC1 RXD1", - "T11 GMAC1 RXD2", "W12 GMAC1 RXD3", - "U10 GMAC1 TXD0", "Y10 GMAC1 TXD1", - "W10 GMAC1 TXD2", "T9 GMAC1 TXD3"; - skew-delay = <7>; - }; - /* Set up drive strength on GMAC0 and GMAC1 to 16 mA */ - conf9 { - groups = "gmii_gmac0_grp", "gmii_gmac1_grp"; - drive-strength = <16>; - }; - }; - }; - }; - - sata: sata@46000000 { - cortina,gemini-ata-muxmode = <0>; - cortina,gemini-enable-sata-bridge; - status = "okay"; - }; - - gpio0: gpio@4d000000 { - pinctrl-names = "default"; - pinctrl-0 = <&gpio0_default_pins>; - }; - - gpio1: gpio@4e000000 { - pinctrl-names = "default"; - pinctrl-0 = <&gpio1_default_pins>; - }; - - pci@50000000 { - status = "okay"; - interrupt-map-mask = <0xf800 0 0 7>; - interrupt-map = - <0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */ - <0x4800 0 0 2 &pci_intc 1>, - <0x4800 0 0 3 &pci_intc 2>, - <0x4800 0 0 4 &pci_intc 3>, - <0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */ - <0x5000 0 0 2 &pci_intc 2>, - <0x5000 0 0 3 &pci_intc 3>, - <0x5000 0 0 4 &pci_intc 0>, - <0x5800 0 0 1 &pci_intc 2>, /* Slot 11 */ - <0x5800 0 0 2 &pci_intc 3>, - <0x5800 0 0 3 &pci_intc 0>, - <0x5800 0 0 4 &pci_intc 1>, - <0x6000 0 0 1 &pci_intc 3>, /* Slot 12 */ - <0x6000 0 0 2 &pci_intc 0>, - <0x6000 0 0 3 &pci_intc 1>, - <0x6000 0 0 4 &pci_intc 2>; - }; - - ethernet@60000000 { - status = "okay"; - - ethernet-port@0 { - phy-mode = "rgmii"; - phy-handle = <&phy0>; - }; - ethernet-port@1 { - phy-mode = "rgmii"; - fixed-link { - speed = <1000>; - full-duplex; - pause; - }; - }; - }; - - ata@63000000 { - status = "okay"; - }; - - usb@68000000 { - status = "okay"; - }; - - usb@69000000 { - status = "okay"; - }; - }; -}; diff --git a/sys/gnu/dts/arm/gemini-wbd111.dts b/sys/gnu/dts/arm/gemini-wbd111.dts deleted file mode 100644 index 3a2761dd460..00000000000 --- a/sys/gnu/dts/arm/gemini-wbd111.dts +++ /dev/null @@ -1,183 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree file for Wiliboard WBD-111 - */ - -/dts-v1/; - -#include "gemini.dtsi" -#include - -/ { - model = "Wiliboard WBD-111"; - compatible = "wiliboard,wbd111", "cortina,gemini"; - #address-cells = <1>; - #size-cells = <1>; - - memory@0 { - /* 128 MB */ - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - gpio_keys { - compatible = "gpio-keys"; - - button-setup { - debounce-interval = <100>; - wakeup-source; - linux,code = ; - label = "reset"; - /* Conflict with ICE */ - gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; - }; - }; - - leds { - compatible = "gpio-leds"; - - led-red-l3 { - label = "wbd111:red:L3"; - /* Conflict with TVC and extended parallel flash */ - gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - led-green-l4 { - label = "wbd111:green:L4"; - /* Conflict with TVC and extended parallel flash */ - gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - led-red-l4 { - label = "wbd111:red:L4"; - /* Conflict with TVC and extended parallel flash */ - gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - led-greeb-l3 { - label = "wbd111:green:L3"; - /* Conflict with TVC and extended parallel flash */ - gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>; - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - }; - - mdio0: ethernet-phy { - compatible = "virtual,mdio-gpio"; - gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */ - <&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */ - #address-cells = <1>; - #size-cells = <0>; - - phy0: ethernet-phy@1 { - reg = <1>; - device_type = "ethernet-phy"; - }; - }; - - soc { - flash@30000000 { - status = "okay"; - /* 8MB of flash */ - reg = <0x30000000 0x00800000>; - - partition@0 { - label = "RedBoot"; - reg = <0x00000000 0x00020000>; - read-only; - }; - partition@20000 { - label = "kernel"; - reg = <0x00020000 0x00100000>; - }; - partition@120000 { - label = "rootfs"; - reg = <0x00120000 0x006a0000>; - }; - partition@7c0000 { - label = "VCTL"; - reg = <0x007c0000 0x00010000>; - read-only; - }; - partition@7d0000 { - label = "cfg"; - reg = <0x007d0000 0x00010000>; - read-only; - }; - partition@7e0000 { - label = "FIS"; - reg = <0x007e0000 0x00010000>; - read-only; - }; - }; - - syscon: syscon@40000000 { - pinctrl { - /* - * gpio0agrp cover line 0-4 - * gpio0bgrp cover line 5 - */ - gpio0_default_pins: pinctrl-gpio0 { - mux { - function = "gpio0"; - groups = "gpio0agrp", - "gpio0bgrp"; - }; - }; - }; - }; - - gpio0: gpio@4d000000 { - pinctrl-names = "default"; - pinctrl-0 = <&gpio0_default_pins>; - }; - - pci@50000000 { - status = "okay"; - interrupt-map-mask = <0xf800 0 0 7>; - interrupt-map = - <0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */ - <0x4800 0 0 2 &pci_intc 1>, - <0x4800 0 0 3 &pci_intc 2>, - <0x4800 0 0 4 &pci_intc 3>, - <0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */ - <0x5000 0 0 2 &pci_intc 2>, - <0x5000 0 0 3 &pci_intc 3>, - <0x5000 0 0 4 &pci_intc 0>, - <0x5800 0 0 1 &pci_intc 2>, /* Slot 11 */ - <0x5800 0 0 2 &pci_intc 3>, - <0x5800 0 0 3 &pci_intc 0>, - <0x5800 0 0 4 &pci_intc 1>, - <0x6000 0 0 1 &pci_intc 3>, /* Slot 12 */ - <0x6000 0 0 2 &pci_intc 0>, - <0x6000 0 0 3 &pci_intc 1>, - <0x6000 0 0 4 &pci_intc 2>; - }; - - ethernet@60000000 { - status = "okay"; - - ethernet-port@0 { - phy-mode = "rgmii"; - phy-handle = <&phy0>; - }; - ethernet-port@1 { - /* Not used in this platform */ - }; - }; - - usb@68000000 { - status = "okay"; - }; - - usb@69000000 { - status = "okay"; - }; - }; -}; diff --git a/sys/gnu/dts/arm/gemini-wbd222.dts b/sys/gnu/dts/arm/gemini-wbd222.dts deleted file mode 100644 index 52b4dbc0c07..00000000000 --- a/sys/gnu/dts/arm/gemini-wbd222.dts +++ /dev/null @@ -1,195 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree file for Wiliboard WBD-222 - */ - -/dts-v1/; - -#include "gemini.dtsi" -#include - -/ { - model = "Wiliboard WBD-222"; - compatible = "wiliboard,wbd222", "cortina,gemini"; - #address-cells = <1>; - #size-cells = <1>; - - memory@0 { /* 128 MB */ - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - gpio_keys { - compatible = "gpio-keys"; - - button-setup { - debounce-interval = <100>; - wakeup-source; - linux,code = ; - label = "reset"; - /* Conflict with ICE */ - gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; - }; - }; - - leds { - compatible = "gpio-leds"; - - led-red-l3 { - label = "wbd111:red:L3"; - /* Conflict with TVC and extended parallel flash */ - gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - led-green-l4 { - label = "wbd111:green:L4"; - /* Conflict with TVC and extended parallel flash */ - gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - led-red-l4 { - label = "wbd111:red:L4"; - /* Conflict with TVC and extended parallel flash */ - gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - led-green-l3 { - label = "wbd111:green:L3"; - /* Conflict with TVC and extended parallel flash */ - gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>; - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - }; - - mdio0: ethernet-phy { - compatible = "virtual,mdio-gpio"; - gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */ - <&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */ - #address-cells = <1>; - #size-cells = <0>; - - phy0: ethernet-phy@1 { - reg = <1>; - device_type = "ethernet-phy"; - }; - - phy1: ethernet-phy@3 { - reg = <3>; - device_type = "ethernet-phy"; - }; - }; - - soc { - flash@30000000 { - status = "okay"; - /* 8MB of flash */ - reg = <0x30000000 0x00800000>; - - partition@0 { - label = "RedBoot"; - reg = <0x00000000 0x00020000>; - read-only; - }; - partition@20000 { - label = "kernel"; - reg = <0x00020000 0x00100000>; - }; - partition@120000 { - label = "rootfs"; - reg = <0x00120000 0x006a0000>; - }; - partition@7c0000 { - label = "VCTL"; - reg = <0x007c0000 0x00010000>; - read-only; - }; - partition@7d0000 { - label = "cfg"; - reg = <0x007d0000 0x00010000>; - read-only; - }; - partition@7e0000 { - label = "FIS"; - reg = <0x007e0000 0x00010000>; - read-only; - }; - }; - - syscon: syscon@40000000 { - pinctrl { - /* - * gpio0agrp cover line 0-4 - * gpio0bgrp cover line 5 - */ - gpio0_default_pins: pinctrl-gpio0 { - mux { - function = "gpio0"; - groups = "gpio0agrp", - "gpio0bgrp"; - }; - }; - pinctrl-gmii { - /* This platform use both the ethernet ports */ - mux { - function = "gmii"; - groups = "gmii_gmac0_grp", "gmii_gmac1_grp"; - }; - }; - }; - }; - - gpio0: gpio@4d000000 { - pinctrl-names = "default"; - pinctrl-0 = <&gpio0_default_pins>; - }; - - pci@50000000 { - status = "okay"; - interrupt-map-mask = <0xf800 0 0 7>; - interrupt-map = - <0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */ - <0x4800 0 0 2 &pci_intc 1>, - <0x4800 0 0 3 &pci_intc 2>, - <0x4800 0 0 4 &pci_intc 3>, - <0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */ - <0x5000 0 0 2 &pci_intc 2>, - <0x5000 0 0 3 &pci_intc 3>, - <0x5000 0 0 4 &pci_intc 0>, - <0x5800 0 0 1 &pci_intc 2>, /* Slot 11 */ - <0x5800 0 0 2 &pci_intc 3>, - <0x5800 0 0 3 &pci_intc 0>, - <0x5800 0 0 4 &pci_intc 1>, - <0x6000 0 0 1 &pci_intc 3>, /* Slot 12 */ - <0x6000 0 0 2 &pci_intc 0>, - <0x6000 0 0 3 &pci_intc 1>, - <0x6000 0 0 4 &pci_intc 2>; - }; - - ethernet@60000000 { - status = "okay"; - - ethernet-port@0 { - phy-mode = "rgmii"; - phy-handle = <&phy0>; - }; - ethernet-port@1 { - phy-mode = "rgmii"; - phy-handle = <&phy1>; - }; - }; - - usb@68000000 { - status = "okay"; - }; - - usb@69000000 { - status = "okay"; - }; - }; -}; diff --git a/sys/gnu/dts/arm/gemini.dtsi b/sys/gnu/dts/arm/gemini.dtsi deleted file mode 100644 index 8cf67b11751..00000000000 --- a/sys/gnu/dts/arm/gemini.dtsi +++ /dev/null @@ -1,445 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree file for Cortina systems Gemini SoC - */ - -#include -#include -#include -#include - -/ { - soc { - #address-cells = <1>; - #size-cells = <1>; - ranges; - compatible = "simple-bus"; - interrupt-parent = <&intcon>; - - flash@30000000 { - compatible = "cortina,gemini-flash", "cfi-flash"; - syscon = <&syscon>; - pinctrl-names = "default"; - pinctrl-0 = <&pflash_default_pins>; - bank-width = <2>; - #address-cells = <1>; - #size-cells = <1>; - status = "disabled"; - }; - - syscon: syscon@40000000 { - compatible = "cortina,gemini-syscon", - "syscon", "simple-mfd"; - reg = <0x40000000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - - syscon-reboot { - compatible = "syscon-reboot"; - regmap = <&syscon>; - /* GLOBAL_RESET register */ - offset = <0x0c>; - /* RESET_GLOBAL | RESET_CPU1 */ - mask = <0xC0000000>; - }; - - pinctrl { - compatible = "cortina,gemini-pinctrl"; - regmap = <&syscon>; - /* Hog the DRAM pins */ - pinctrl-names = "default"; - pinctrl-0 = <&dram_default_pins>, <&system_default_pins>, - <&vcontrol_default_pins>; - - dram_default_pins: pinctrl-dram { - mux { - function = "dram"; - groups = "dramgrp"; - }; - }; - rtc_default_pins: pinctrl-rtc { - mux { - function = "rtc"; - groups = "rtcgrp"; - }; - }; - power_default_pins: pinctrl-power { - mux { - function = "power"; - groups = "powergrp"; - }; - }; - cir_default_pins: pinctrl-cir { - mux { - function = "cir"; - groups = "cirgrp"; - }; - }; - system_default_pins: pinctrl-system { - mux { - function = "system"; - groups = "systemgrp"; - }; - }; - vcontrol_default_pins: pinctrl-vcontrol { - mux { - function = "vcontrol"; - groups = "vcontrolgrp"; - }; - }; - ice_default_pins: pinctrl-ice { - mux { - function = "ice"; - groups = "icegrp"; - }; - }; - uart_default_pins: pinctrl-uart { - mux { - function = "uart"; - groups = "uartrxtxgrp"; - }; - }; - pflash_default_pins: pinctrl-pflash { - mux { - function = "pflash"; - groups = "pflashgrp"; - }; - }; - usb_default_pins: pinctrl-usb { - mux { - function = "usb"; - groups = "usbgrp"; - }; - }; - gmii_default_pins: pinctrl-gmii { - /* - * Only activate GMAC0 by default since - * GMAC1 will overlap with 8 GPIO lines - * gpio2a, gpio2b. Overlay groups with - * "gmii_gmac0_grp", "gmii_gmac1_grp" for - * both ethernet interfaces. - */ - mux { - function = "gmii"; - groups = "gmii_gmac0_grp"; - }; - }; - pci_default_pins: pinctrl-pci { - mux { - function = "pci"; - groups = "pcigrp"; - }; - }; - sata_default_pins: pinctrl-sata { - mux { - function = "sata"; - groups = "satagrp"; - }; - }; - /* Activate both groups of pins for this state */ - sata_and_ide_pins: pinctrl-sata-ide { - mux0 { - function = "sata"; - groups = "satagrp"; - }; - mux1 { - function = "ide"; - groups = "idegrp"; - }; - }; - tvc_default_pins: pinctrl-tvc { - mux { - function = "tvc"; - groups = "tvcgrp"; - }; - }; - }; - }; - - watchdog@41000000 { - compatible = "cortina,gemini-watchdog", "faraday,ftwdt010"; - reg = <0x41000000 0x1000>; - interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; - resets = <&syscon GEMINI_RESET_WDOG>; - clocks = <&syscon GEMINI_CLK_APB>; - clock-names = "PCLK"; - }; - - uart0: serial@42000000 { - compatible = "ns16550a"; - reg = <0x42000000 0x100>; - resets = <&syscon GEMINI_RESET_UART>; - clocks = <&syscon GEMINI_CLK_UART>; - interrupts = <18 IRQ_TYPE_LEVEL_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&uart_default_pins>; - reg-shift = <2>; - }; - - timer@43000000 { - compatible = "faraday,fttmr010"; - reg = <0x43000000 0x1000>; - interrupt-parent = <&intcon>; - interrupts = <14 IRQ_TYPE_EDGE_FALLING>, /* Timer 1 */ - <15 IRQ_TYPE_EDGE_FALLING>, /* Timer 2 */ - <16 IRQ_TYPE_EDGE_FALLING>; /* Timer 3 */ - resets = <&syscon GEMINI_RESET_TIMER>; - /* APB clock or RTC clock */ - clocks = <&syscon GEMINI_CLK_APB>, <&syscon GEMINI_CLK_RTC>; - clock-names = "PCLK", "EXTCLK"; - syscon = <&syscon>; - }; - - rtc@45000000 { - compatible = "cortina,gemini-rtc"; - reg = <0x45000000 0x100>; - interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; - resets = <&syscon GEMINI_RESET_RTC>; - clocks = <&syscon GEMINI_CLK_APB>, <&syscon GEMINI_CLK_RTC>; - clock-names = "PCLK", "EXTCLK"; - pinctrl-names = "default"; - pinctrl-0 = <&rtc_default_pins>; - }; - - sata: sata@46000000 { - compatible = "cortina,gemini-sata-bridge"; - reg = <0x46000000 0x100>; - resets = <&syscon GEMINI_RESET_SATA0>, - <&syscon GEMINI_RESET_SATA1>; - reset-names = "sata0", "sata1"; - clocks = <&syscon GEMINI_CLK_GATE_SATA0>, - <&syscon GEMINI_CLK_GATE_SATA1>; - clock-names = "SATA0_PCLK", "SATA1_PCLK"; - /* - * This defines the special "ide" state that needs - * to be explicitly enabled to enable the IDE pins, - * as these pins are normally used for other things. - */ - pinctrl-names = "default", "ide"; - pinctrl-0 = <&sata_default_pins>; - pinctrl-1 = <&sata_and_ide_pins>; - syscon = <&syscon>; - status = "disabled"; - }; - - intcon: interrupt-controller@48000000 { - compatible = "faraday,ftintc010"; - reg = <0x48000000 0x1000>; - resets = <&syscon GEMINI_RESET_INTCON0>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - power-controller@4b000000 { - compatible = "cortina,gemini-power-controller"; - reg = <0x4b000000 0x100>; - interrupts = <26 IRQ_TYPE_EDGE_RISING>; - pinctrl-names = "default"; - pinctrl-0 = <&power_default_pins>; - }; - - gpio0: gpio@4d000000 { - compatible = "cortina,gemini-gpio", "faraday,ftgpio010"; - reg = <0x4d000000 0x100>; - interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; - resets = <&syscon GEMINI_RESET_GPIO0>; - clocks = <&syscon GEMINI_CLK_APB>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio@4e000000 { - compatible = "cortina,gemini-gpio", "faraday,ftgpio010"; - reg = <0x4e000000 0x100>; - interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; - resets = <&syscon GEMINI_RESET_GPIO1>; - clocks = <&syscon GEMINI_CLK_APB>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@4f000000 { - compatible = "cortina,gemini-gpio", "faraday,ftgpio010"; - reg = <0x4f000000 0x100>; - interrupts = <24 IRQ_TYPE_LEVEL_HIGH>; - resets = <&syscon GEMINI_RESET_GPIO2>; - clocks = <&syscon GEMINI_CLK_APB>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - pci@50000000 { - compatible = "cortina,gemini-pci", "faraday,ftpci100"; - /* - * The first 256 bytes in the IO range is actually used - * to configure the host bridge. - */ - reg = <0x50000000 0x100>; - resets = <&syscon GEMINI_RESET_PCI>; - clocks = <&syscon GEMINI_CLK_GATE_PCI>, <&syscon GEMINI_CLK_PCI>; - clock-names = "PCLK", "PCICLK"; - pinctrl-names = "default"; - pinctrl-0 = <&pci_default_pins>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - status = "disabled"; - - bus-range = <0x00 0xff>; - /* PCI ranges mappings */ - ranges = - /* 1MiB I/O space 0x50000000-0x500fffff */ - <0x01000000 0 0 0x50000000 0 0x00100000>, - /* 128MiB non-prefetchable memory 0x58000000-0x5fffffff */ - <0x02000000 0 0x58000000 0x58000000 0 0x08000000>; - - /* DMA ranges */ - dma-ranges = - /* 128MiB at 0x00000000-0x07ffffff */ - <0x02000000 0 0x00000000 0x00000000 0 0x08000000>, - /* 64MiB at 0x00000000-0x03ffffff */ - <0x02000000 0 0x00000000 0x00000000 0 0x04000000>, - /* 64MiB at 0x00000000-0x03ffffff */ - <0x02000000 0 0x00000000 0x00000000 0 0x04000000>; - - /* - * This PCI host bridge variant has a cascaded interrupt - * controller embedded in the host bridge. - */ - pci_intc: interrupt-controller { - interrupt-parent = <&intcon>; - interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - }; - }; - - ethernet@60000000 { - compatible = "cortina,gemini-ethernet"; - reg = <0x60000000 0x4000>, /* Global registers, queue */ - <0x60004000 0x2000>, /* V-bit */ - <0x60006000 0x2000>; /* A-bit */ - pinctrl-names = "default"; - pinctrl-0 = <&gmii_default_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gmac0: ethernet-port@0 { - compatible = "cortina,gemini-ethernet-port"; - reg = <0x60008000 0x2000>, /* Port 0 DMA/TOE */ - <0x6000a000 0x2000>; /* Port 0 GMAC */ - interrupt-parent = <&intcon>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; - resets = <&syscon GEMINI_RESET_GMAC0>; - clocks = <&syscon GEMINI_CLK_GATE_GMAC0>; - clock-names = "PCLK"; - }; - - gmac1: ethernet-port@1 { - compatible = "cortina,gemini-ethernet-port"; - reg = <0x6000c000 0x2000>, /* Port 1 DMA/TOE */ - <0x6000e000 0x2000>; /* Port 1 GMAC */ - interrupt-parent = <&intcon>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; - resets = <&syscon GEMINI_RESET_GMAC1>; - clocks = <&syscon GEMINI_CLK_GATE_GMAC1>; - clock-names = "PCLK"; - }; - }; - - ata@63000000 { - compatible = "cortina,gemini-pata", "faraday,ftide010"; - reg = <0x63000000 0x1000>; - interrupts = <4 IRQ_TYPE_EDGE_RISING>; - resets = <&syscon GEMINI_RESET_IDE>; - clocks = <&syscon GEMINI_CLK_GATE_IDE>; - clock-names = "PCLK"; - sata = <&sata>; - status = "disabled"; - }; - - ata@63400000 { - compatible = "cortina,gemini-pata", "faraday,ftide010"; - reg = <0x63400000 0x1000>; - interrupts = <5 IRQ_TYPE_EDGE_RISING>; - resets = <&syscon GEMINI_RESET_IDE>; - clocks = <&syscon GEMINI_CLK_GATE_IDE>; - clock-names = "PCLK"; - sata = <&sata>; - status = "disabled"; - }; - - dma-controller@67000000 { - compatible = "faraday,ftdma020", "arm,pl080", "arm,primecell"; - /* Faraday Technology FTDMAC020 variant */ - arm,primecell-periphid = <0x0003b080>; - reg = <0x67000000 0x1000>; - interrupts = <9 IRQ_TYPE_EDGE_RISING>; - resets = <&syscon GEMINI_RESET_DMAC>; - clocks = <&syscon GEMINI_CLK_AHB>; - clock-names = "apb_pclk"; - /* Bus interface AHB1 (AHB0) is totally tilted */ - lli-bus-interface-ahb2; - mem-bus-interface-ahb2; - memcpy-burst-size = <256>; - memcpy-bus-width = <32>; - #dma-cells = <2>; - }; - - display-controller@6a000000 { - compatible = "cortina,gemini-tvc", "faraday,tve200"; - reg = <0x6a000000 0x1000>; - interrupts = <13 IRQ_TYPE_EDGE_RISING>; - resets = <&syscon GEMINI_RESET_TVC>; - clocks = <&syscon GEMINI_CLK_GATE_TVC>, - <&syscon GEMINI_CLK_TVC>; - clock-names = "PCLK", "TVE"; - pinctrl-names = "default"; - pinctrl-0 = <&tvc_default_pins>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - usb@68000000 { - compatible = "cortina,gemini-usb", "faraday,fotg210"; - reg = <0x68000000 0x1000>; - interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; - resets = <&syscon GEMINI_RESET_USB0>; - clocks = <&syscon GEMINI_CLK_GATE_USB0>; - clock-names = "PCLK"; - /* - * This will claim pins for USB0 and USB1 at the same - * time as they are using some common pins. If you for - * some reason have a system using USB1 at 96000000 but - * NOT using USB0 at 68000000 you wll have to add the - * usb_default_pins to the USB controller at 96000000 - * in your .dts for the board. - */ - pinctrl-names = "default"; - pinctrl-0 = <&usb_default_pins>; - syscon = <&syscon>; - status = "disabled"; - }; - - usb@69000000 { - compatible = "cortina,gemini-usb", "faraday,fotg210"; - reg = <0x69000000 0x1000>; - interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; - resets = <&syscon GEMINI_RESET_USB1>; - clocks = <&syscon GEMINI_CLK_GATE_USB1>; - clock-names = "PCLK"; - syscon = <&syscon>; - status = "disabled"; - }; - }; -}; diff --git a/sys/gnu/dts/arm/gr-peach-audiocamerashield.dtsi b/sys/gnu/dts/arm/gr-peach-audiocamerashield.dtsi deleted file mode 100644 index 8d77579807e..00000000000 --- a/sys/gnu/dts/arm/gr-peach-audiocamerashield.dtsi +++ /dev/null @@ -1,75 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the GR-Peach audiocamera shield expansion board - * - * Copyright (C) 2017 Jacopo Mondi - */ - -#include "r7s72100.dtsi" -#include -#include - -/ { - /* On-board camera clock. */ - camera_clk: camera_clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <27000000>; - }; -}; - -&pinctrl { - i2c1_pins: i2c1 { - /* P1_2 as SCL; P1_3 as SDA */ - pinmux = , ; - }; - - vio_pins: vio { - /* CEU pins: VIO_D[0-10], VIO_VD, VIO_HD, VIO_CLK */ - pinmux = , /* VIO_VD */ - , /* VIO_HD */ - , /* VIO_D0 */ - , /* VIO_D1 */ - , /* VIO_D2 */ - , /* VIO_D3 */ - , /* VIO_D4 */ - , /* VIO_D5 */ - , /* VIO_D6 */ - , /* VIO_D7 */ - ; /* VIO_CLK */ - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - - status = "okay"; - clock-frequency = <100000>; - - camera@48 { - compatible = "aptina,mt9v111"; - reg = <0x48>; - - clocks = <&camera_clk>; - - port { - mt9v111_out: endpoint { - remote-endpoint = <&ceu_in>; - }; - }; - }; -}; - -&ceu { - pinctrl-names = "default"; - pinctrl-0 = <&vio_pins>; - - status = "okay"; - - port { - ceu_in: endpoint { - remote-endpoint = <&mt9v111_out>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/hi3519-demb.dts b/sys/gnu/dts/arm/hi3519-demb.dts deleted file mode 100644 index 64f8ed12693..00000000000 --- a/sys/gnu/dts/arm/hi3519-demb.dts +++ /dev/null @@ -1,29 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (c) 2015 HiSilicon Technologies Co., Ltd. - */ - -/dts-v1/; -#include "hi3519.dtsi" - -/ { - model = "HiSilicon HI3519 DEMO Board"; - compatible = "hisilicon,hi3519"; - - aliases { - serial0 = &uart0; - }; - - memory { - device_type = "memory"; - reg = <0x80000000 0x40000000>; - }; -}; - -&uart0 { - status = "okay"; -}; - -&dual_timer0 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/hi3519.dtsi b/sys/gnu/dts/arm/hi3519.dtsi deleted file mode 100644 index 410409a0ed6..00000000000 --- a/sys/gnu/dts/arm/hi3519.dtsi +++ /dev/null @@ -1,174 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (c) 2015 HiSilicon Technologies Co., Ltd. - */ - -#include -#include -/ { - #address-cells = <1>; - #size-cells = <1>; - chosen { }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0>; - }; - }; - - gic: interrupt-controller@10300000 { - compatible = "arm,cortex-a7-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x10301000 0x1000>, <0x10302000 0x1000>; - }; - - clk_3m: clk_3m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <3000000>; - }; - - crg: clock-reset-controller@12010000 { - compatible = "hisilicon,hi3519-crg"; - #clock-cells = <1>; - #reset-cells = <2>; - reg = <0x12010000 0x10000>; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&gic>; - ranges; - - uart0: serial@12100000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x12100000 0x1000>; - interrupts = ; - clocks = <&crg HI3519_UART0_CLK>; - clock-names = "apb_pclk"; - status = "disable"; - }; - - uart1: serial@12101000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x12101000 0x1000>; - interrupts = ; - clocks = <&crg HI3519_UART1_CLK>; - clock-names = "apb_pclk"; - status = "disable"; - }; - - uart2: serial@12102000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x12102000 0x1000>; - interrupts = ; - clocks = <&crg HI3519_UART2_CLK>; - clock-names = "apb_pclk"; - status = "disable"; - }; - - uart3: serial@12103000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x12103000 0x1000>; - interrupts = ; - clocks = <&crg HI3519_UART3_CLK>; - clock-names = "apb_pclk"; - status = "disable"; - }; - - uart4: serial@12104000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x12104000 0x1000>; - interrupts = ; - clocks = <&crg HI3519_UART4_CLK>; - clock-names = "apb_pclk"; - status = "disable"; - }; - - dual_timer0: timer@12000000 { - compatible = "arm,sp804", "arm,primecell"; - interrupts = , - ; - reg = <0x12000000 0x1000>; - clocks = <&clk_3m>; - clock-names = "apb_pclk"; - status = "disable"; - }; - - dual_timer1: timer@12001000 { - compatible = "arm,sp804", "arm,primecell"; - interrupts = , - ; - reg = <0x12001000 0x1000>; - clocks = <&clk_3m>; - clock-names = "apb_pclk"; - status = "disable"; - }; - - dual_timer2: timer@12002000 { - compatible = "arm,sp804", "arm,primecell"; - interrupts = , - ; - reg = <0x12002000 0x1000>; - clocks = <&clk_3m>; - clock-names = "apb_pclk"; - status = "disable"; - }; - - spi_bus0: spi@12120000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x12120000 0x1000>; - interrupts = ; - clocks = <&crg HI3519_SPI0_CLK>; - clock-names = "apb_pclk"; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disable"; - }; - - spi_bus1: spi@12121000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x12121000 0x1000>; - interrupts = ; - clocks = <&crg HI3519_SPI1_CLK>; - clock-names = "apb_pclk"; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disable"; - }; - - spi_bus2: spi@12122000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x12122000 0x1000>; - interrupts = ; - clocks = <&crg HI3519_SPI2_CLK>; - clock-names = "apb_pclk"; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disable"; - }; - - sysctrl: system-controller@12020000 { - compatible = "hisilicon,hi3519-sysctrl", "syscon"; - reg = <0x12020000 0x1000>; - }; - - reboot { - compatible = "syscon-reboot"; - regmap = <&sysctrl>; - offset = <0x4>; - mask = <0xdeadbeef>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/hi3620-hi4511.dts b/sys/gnu/dts/arm/hi3620-hi4511.dts deleted file mode 100644 index 8c703c3f2fe..00000000000 --- a/sys/gnu/dts/arm/hi3620-hi4511.dts +++ /dev/null @@ -1,647 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012-2013 Linaro Ltd. - * Author: Haojian Zhuang - */ - -/dts-v1/; - -#include "hi3620.dtsi" - -/ { - model = "Hisilicon Hi4511 Development Board"; - compatible = "hisilicon,hi3620-hi4511"; - - chosen { - bootargs = "root=/dev/ram0"; - stdout-path = "serial0:115200n8"; - }; - - memory { - device_type = "memory"; - reg = <0x40000000 0x20000000>; - }; - - amba { - dual_timer0: dual_timer@800000 { - status = "ok"; - }; - - uart0: uart@b00000 { /* console */ - pinctrl-names = "default", "idle"; - pinctrl-0 = <&uart0_pmx_func &uart0_cfg_func>; - pinctrl-1 = <&uart0_pmx_idle &uart0_cfg_idle>; - status = "ok"; - }; - - uart1: uart@b01000 { /* modem */ - pinctrl-names = "default", "idle"; - pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func>; - pinctrl-1 = <&uart1_pmx_idle &uart1_cfg_idle>; - status = "ok"; - }; - - uart2: uart@b02000 { /* audience */ - pinctrl-names = "default", "idle"; - pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>; - pinctrl-1 = <&uart2_pmx_idle &uart2_cfg_idle>; - status = "ok"; - }; - - uart3: uart@b03000 { - pinctrl-names = "default", "idle"; - pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>; - pinctrl-1 = <&uart3_pmx_idle &uart3_cfg_idle>; - status = "ok"; - }; - - uart4: uart@b04000 { - pinctrl-names = "default", "idle"; - pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>; - pinctrl-1 = <&uart4_pmx_idle &uart4_cfg_func>; - status = "ok"; - }; - - pmx0: pinmux@803000 { - pinctrl-names = "default"; - pinctrl-0 = <&board_pmx_pins>; - - board_pmx_pins: board_pmx_pins { - pinctrl-single,pins = < - 0x008 0x0 /* GPIO -- eFUSE_DOUT */ - 0x100 0x0 /* USIM_CLK & USIM_DATA (IOMG63) */ - >; - }; - uart0_pmx_func: uart0_pmx_func { - pinctrl-single,pins = < - 0x0f0 0x0 - 0x0f4 0x0 /* UART0_RX & UART0_TX */ - >; - }; - uart0_pmx_idle: uart0_pmx_idle { - pinctrl-single,pins = < - /*0x0f0 0x1*/ /* UART0_CTS & UART0_RTS */ - 0x0f4 0x1 /* UART0_RX & UART0_TX */ - >; - }; - uart1_pmx_func: uart1_pmx_func { - pinctrl-single,pins = < - 0x0f8 0x0 /* UART1_CTS & UART1_RTS (IOMG61) */ - 0x0fc 0x0 /* UART1_RX & UART1_TX (IOMG62) */ - >; - }; - uart1_pmx_idle: uart1_pmx_idle { - pinctrl-single,pins = < - 0x0f8 0x1 /* GPIO (IOMG61) */ - 0x0fc 0x1 /* GPIO (IOMG62) */ - >; - }; - uart2_pmx_func: uart2_pmx_func { - pinctrl-single,pins = < - 0x104 0x2 /* UART2_RXD (IOMG96) */ - 0x108 0x2 /* UART2_TXD (IOMG64) */ - >; - }; - uart2_pmx_idle: uart2_pmx_idle { - pinctrl-single,pins = < - 0x104 0x1 /* GPIO (IOMG96) */ - 0x108 0x1 /* GPIO (IOMG64) */ - >; - }; - uart3_pmx_func: uart3_pmx_func { - pinctrl-single,pins = < - 0x160 0x2 /* UART3_CTS & UART3_RTS (IOMG85) */ - 0x164 0x2 /* UART3_RXD & UART3_TXD (IOMG86) */ - >; - }; - uart3_pmx_idle: uart3_pmx_idle { - pinctrl-single,pins = < - 0x160 0x1 /* GPIO (IOMG85) */ - 0x164 0x1 /* GPIO (IOMG86) */ - >; - }; - uart4_pmx_func: uart4_pmx_func { - pinctrl-single,pins = < - 0x168 0x0 /* UART4_CTS & UART4_RTS (IOMG87) */ - 0x16c 0x0 /* UART4_RXD (IOMG88) */ - 0x170 0x0 /* UART4_TXD (IOMG93) */ - >; - }; - uart4_pmx_idle: uart4_pmx_idle { - pinctrl-single,pins = < - 0x168 0x1 /* GPIO (IOMG87) */ - 0x16c 0x1 /* GPIO (IOMG88) */ - 0x170 0x1 /* GPIO (IOMG93) */ - >; - }; - i2c0_pmx_func: i2c0_pmx_func { - pinctrl-single,pins = < - 0x0b4 0x0 /* I2C0_SCL & I2C0_SDA (IOMG45) */ - >; - }; - i2c0_pmx_idle: i2c0_pmx_idle { - pinctrl-single,pins = < - 0x0b4 0x1 /* GPIO (IOMG45) */ - >; - }; - i2c1_pmx_func: i2c1_pmx_func { - pinctrl-single,pins = < - 0x0b8 0x0 /* I2C1_SCL & I2C1_SDA (IOMG46) */ - >; - }; - i2c1_pmx_idle: i2c1_pmx_idle { - pinctrl-single,pins = < - 0x0b8 0x1 /* GPIO (IOMG46) */ - >; - }; - i2c2_pmx_func: i2c2_pmx_func { - pinctrl-single,pins = < - 0x068 0x0 /* I2C2_SCL (IOMG26) */ - 0x06c 0x0 /* I2C2_SDA (IOMG27) */ - >; - }; - i2c2_pmx_idle: i2c2_pmx_idle { - pinctrl-single,pins = < - 0x068 0x1 /* GPIO (IOMG26) */ - 0x06c 0x1 /* GPIO (IOMG27) */ - >; - }; - i2c3_pmx_func: i2c3_pmx_func { - pinctrl-single,pins = < - 0x050 0x2 /* I2C3_SCL (IOMG20) */ - 0x054 0x2 /* I2C3_SDA (IOMG21) */ - >; - }; - i2c3_pmx_idle: i2c3_pmx_idle { - pinctrl-single,pins = < - 0x050 0x1 /* GPIO (IOMG20) */ - 0x054 0x1 /* GPIO (IOMG21) */ - >; - }; - spi0_pmx_func: spi0_pmx_func { - pinctrl-single,pins = < - 0x0d4 0x0 /* SPI0_CLK/SPI0_DI/SPI0_DO (IOMG53) */ - 0x0d8 0x0 /* SPI0_CS0 (IOMG54) */ - 0x0dc 0x0 /* SPI0_CS1 (IOMG55) */ - 0x0e0 0x0 /* SPI0_CS2 (IOMG56) */ - 0x0e4 0x0 /* SPI0_CS3 (IOMG57) */ - >; - }; - spi0_pmx_idle: spi0_pmx_idle { - pinctrl-single,pins = < - 0x0d4 0x1 /* GPIO (IOMG53) */ - 0x0d8 0x1 /* GPIO (IOMG54) */ - 0x0dc 0x1 /* GPIO (IOMG55) */ - 0x0e0 0x1 /* GPIO (IOMG56) */ - 0x0e4 0x1 /* GPIO (IOMG57) */ - >; - }; - spi1_pmx_func: spi1_pmx_func { - pinctrl-single,pins = < - 0x184 0x0 /* SPI1_CLK/SPI1_DI (IOMG98) */ - 0x0e8 0x0 /* SPI1_DO (IOMG58) */ - 0x0ec 0x0 /* SPI1_CS (IOMG95) */ - >; - }; - spi1_pmx_idle: spi1_pmx_idle { - pinctrl-single,pins = < - 0x184 0x1 /* GPIO (IOMG98) */ - 0x0e8 0x1 /* GPIO (IOMG58) */ - 0x0ec 0x1 /* GPIO (IOMG95) */ - >; - }; - kpc_pmx_func: kpc_pmx_func { - pinctrl-single,pins = < - 0x12c 0x0 /* KEY_IN0 (IOMG73) */ - 0x130 0x0 /* KEY_IN1 (IOMG74) */ - 0x134 0x0 /* KEY_IN2 (IOMG75) */ - 0x10c 0x0 /* KEY_OUT0 (IOMG65) */ - 0x110 0x0 /* KEY_OUT1 (IOMG66) */ - 0x114 0x0 /* KEY_OUT2 (IOMG67) */ - >; - }; - kpc_pmx_idle: kpc_pmx_idle { - pinctrl-single,pins = < - 0x12c 0x1 /* GPIO (IOMG73) */ - 0x130 0x1 /* GPIO (IOMG74) */ - 0x134 0x1 /* GPIO (IOMG75) */ - 0x10c 0x1 /* GPIO (IOMG65) */ - 0x110 0x1 /* GPIO (IOMG66) */ - 0x114 0x1 /* GPIO (IOMG67) */ - >; - }; - gpio_key_func: gpio_key_func { - pinctrl-single,pins = < - 0x10c 0x1 /* KEY_OUT0/GPIO (IOMG65) */ - 0x130 0x1 /* KEY_IN1/GPIO (IOMG74) */ - >; - }; - emmc_pmx_func: emmc_pmx_func { - pinctrl-single,pins = < - 0x030 0x2 /* eMMC_CMD/eMMC_CLK (IOMG12) */ - 0x018 0x0 /* NAND_CS3_N (IOMG6) */ - 0x024 0x0 /* NAND_BUSY2_N (IOMG8) */ - 0x028 0x0 /* NAND_BUSY3_N (IOMG9) */ - 0x02c 0x2 /* eMMC_DATA[0:7] (IOMG10) */ - >; - }; - emmc_pmx_idle: emmc_pmx_idle { - pinctrl-single,pins = < - 0x030 0x0 /* GPIO (IOMG12) */ - 0x018 0x1 /* GPIO (IOMG6) */ - 0x024 0x1 /* GPIO (IOMG8) */ - 0x028 0x1 /* GPIO (IOMG9) */ - 0x02c 0x1 /* GPIO (IOMG10) */ - >; - }; - sd_pmx_func: sd_pmx_func { - pinctrl-single,pins = < - 0x0bc 0x0 /* SD_CLK/SD_CMD/SD_DATA0/SD_DATA1/SD_DATA2 (IOMG47) */ - 0x0c0 0x0 /* SD_DATA3 (IOMG48) */ - >; - }; - sd_pmx_idle: sd_pmx_idle { - pinctrl-single,pins = < - 0x0bc 0x1 /* GPIO (IOMG47) */ - 0x0c0 0x1 /* GPIO (IOMG48) */ - >; - }; - nand_pmx_func: nand_pmx_func { - pinctrl-single,pins = < - 0x00c 0x0 /* NAND_ALE/NAND_CLE/.../NAND_DATA[0:7] (IOMG3) */ - 0x010 0x0 /* NAND_CS1_N (IOMG4) */ - 0x014 0x0 /* NAND_CS2_N (IOMG5) */ - 0x018 0x0 /* NAND_CS3_N (IOMG6) */ - 0x01c 0x0 /* NAND_BUSY0_N (IOMG94) */ - 0x020 0x0 /* NAND_BUSY1_N (IOMG7) */ - 0x024 0x0 /* NAND_BUSY2_N (IOMG8) */ - 0x028 0x0 /* NAND_BUSY3_N (IOMG9) */ - 0x02c 0x0 /* NAND_DATA[8:15] (IOMG10) */ - >; - }; - nand_pmx_idle: nand_pmx_idle { - pinctrl-single,pins = < - 0x00c 0x1 /* GPIO (IOMG3) */ - 0x010 0x1 /* GPIO (IOMG4) */ - 0x014 0x1 /* GPIO (IOMG5) */ - 0x018 0x1 /* GPIO (IOMG6) */ - 0x01c 0x1 /* GPIO (IOMG94) */ - 0x020 0x1 /* GPIO (IOMG7) */ - 0x024 0x1 /* GPIO (IOMG8) */ - 0x028 0x1 /* GPIO (IOMG9) */ - 0x02c 0x1 /* GPIO (IOMG10) */ - >; - }; - sdio_pmx_func: sdio_pmx_func { - pinctrl-single,pins = < - 0x0c4 0x0 /* SDIO_CLK/SDIO_CMD/SDIO_DATA[0:3] (IOMG49) */ - >; - }; - sdio_pmx_idle: sdio_pmx_idle { - pinctrl-single,pins = < - 0x0c4 0x1 /* GPIO (IOMG49) */ - >; - }; - audio_out_pmx_func: audio_out_pmx_func { - pinctrl-single,pins = < - 0x0f0 0x1 /* GPIO (IOMG59), audio spk & earphone */ - >; - }; - }; - - pmx1: pinmux@803800 { - pinctrl-names = "default"; - pinctrl-0 = < &board_pu_pins &board_pd_pins &board_pd_ps_pins - &board_np_pins &board_ps_pins &kpc_cfg_func - &audio_out_cfg_func>; - board_pu_pins: board_pu_pins { - pinctrl-single,pins = < - 0x014 0 /* GPIO_158 (IOCFG2) */ - 0x018 0 /* GPIO_159 (IOCFG3) */ - 0x01c 0 /* BOOT_MODE0 (IOCFG4) */ - 0x020 0 /* BOOT_MODE1 (IOCFG5) */ - >; - pinctrl-single,bias-pulldown = <0 2 0 2>; - pinctrl-single,bias-pullup = <1 1 0 1>; - }; - board_pd_pins: board_pd_pins { - pinctrl-single,pins = < - 0x038 0 /* eFUSE_DOUT (IOCFG11) */ - 0x150 0 /* ISP_GPIO8 (IOCFG93) */ - 0x154 0 /* ISP_GPIO9 (IOCFG94) */ - >; - pinctrl-single,bias-pulldown = <2 2 0 2>; - pinctrl-single,bias-pullup = <0 1 0 1>; - }; - board_pd_ps_pins: board_pd_ps_pins { - pinctrl-single,pins = < - 0x2d8 0 /* CLK_OUT0 (IOCFG190) */ - 0x004 0 /* PMU_SPI_DATA (IOCFG192) */ - >; - pinctrl-single,bias-pulldown = <2 2 0 2>; - pinctrl-single,bias-pullup = <0 1 0 1>; - pinctrl-single,drive-strength = <0x30 0xf0>; - }; - board_np_pins: board_np_pins { - pinctrl-single,pins = < - 0x24c 0 /* KEYPAD_OUT7 (IOCFG155) */ - >; - pinctrl-single,bias-pulldown = <0 2 0 2>; - pinctrl-single,bias-pullup = <0 1 0 1>; - }; - board_ps_pins: board_ps_pins { - pinctrl-single,pins = < - 0x000 0 /* PMU_SPI_CLK (IOCFG191) */ - 0x008 0 /* PMU_SPI_CS_N (IOCFG193) */ - >; - pinctrl-single,drive-strength = <0x30 0xf0>; - }; - uart0_cfg_func: uart0_cfg_func { - pinctrl-single,pins = < - 0x208 0 /* UART0_RXD (IOCFG138) */ - 0x20c 0 /* UART0_TXD (IOCFG139) */ - >; - pinctrl-single,bias-pulldown = <0 2 0 2>; - pinctrl-single,bias-pullup = <0 1 0 1>; - }; - uart0_cfg_idle: uart0_cfg_idle { - pinctrl-single,pins = < - 0x208 0 /* UART0_RXD (IOCFG138) */ - 0x20c 0 /* UART0_TXD (IOCFG139) */ - >; - pinctrl-single,bias-pulldown = <2 2 0 2>; - pinctrl-single,bias-pullup = <0 1 0 1>; - }; - uart1_cfg_func: uart1_cfg_func { - pinctrl-single,pins = < - 0x210 0 /* UART1_CTS (IOCFG140) */ - 0x214 0 /* UART1_RTS (IOCFG141) */ - 0x218 0 /* UART1_RXD (IOCFG142) */ - 0x21c 0 /* UART1_TXD (IOCFG143) */ - >; - pinctrl-single,bias-pulldown = <0 2 0 2>; - pinctrl-single,bias-pullup = <0 1 0 1>; - }; - uart1_cfg_idle: uart1_cfg_idle { - pinctrl-single,pins = < - 0x210 0 /* UART1_CTS (IOCFG140) */ - 0x214 0 /* UART1_RTS (IOCFG141) */ - 0x218 0 /* UART1_RXD (IOCFG142) */ - 0x21c 0 /* UART1_TXD (IOCFG143) */ - >; - pinctrl-single,bias-pulldown = <2 2 0 2>; - pinctrl-single,bias-pullup = <0 1 0 1>; - }; - uart2_cfg_func: uart2_cfg_func { - pinctrl-single,pins = < - 0x220 0 /* UART2_CTS (IOCFG144) */ - 0x224 0 /* UART2_RTS (IOCFG145) */ - 0x228 0 /* UART2_RXD (IOCFG146) */ - 0x22c 0 /* UART2_TXD (IOCFG147) */ - >; - pinctrl-single,bias-pulldown = <0 2 0 2>; - pinctrl-single,bias-pullup = <0 1 0 1>; - }; - uart2_cfg_idle: uart2_cfg_idle { - pinctrl-single,pins = < - 0x220 0 /* GPIO (IOCFG144) */ - 0x224 0 /* GPIO (IOCFG145) */ - 0x228 0 /* GPIO (IOCFG146) */ - 0x22c 0 /* GPIO (IOCFG147) */ - >; - pinctrl-single,bias-pulldown = <2 2 0 2>; - pinctrl-single,bias-pullup = <0 1 0 1>; - }; - uart3_cfg_func: uart3_cfg_func { - pinctrl-single,pins = < - 0x294 0 /* UART3_CTS (IOCFG173) */ - 0x298 0 /* UART3_RTS (IOCFG174) */ - 0x29c 0 /* UART3_RXD (IOCFG175) */ - 0x2a0 0 /* UART3_TXD (IOCFG176) */ - >; - pinctrl-single,bias-pulldown = <0 2 0 2>; - pinctrl-single,bias-pullup = <0 1 0 1>; - }; - uart3_cfg_idle: uart3_cfg_idle { - pinctrl-single,pins = < - 0x294 0 /* UART3_CTS (IOCFG173) */ - 0x298 0 /* UART3_RTS (IOCFG174) */ - 0x29c 0 /* UART3_RXD (IOCFG175) */ - 0x2a0 0 /* UART3_TXD (IOCFG176) */ - >; - pinctrl-single,bias-pulldown = <2 2 0 2>; - pinctrl-single,bias-pullup = <0 1 0 1>; - }; - uart4_cfg_func: uart4_cfg_func { - pinctrl-single,pins = < - 0x2a4 0 /* UART4_CTS (IOCFG177) */ - 0x2a8 0 /* UART4_RTS (IOCFG178) */ - 0x2ac 0 /* UART4_RXD (IOCFG179) */ - 0x2b0 0 /* UART4_TXD (IOCFG180) */ - >; - pinctrl-single,bias-pulldown = <0 2 0 2>; - pinctrl-single,bias-pullup = <0 1 0 1>; - }; - i2c0_cfg_func: i2c0_cfg_func { - pinctrl-single,pins = < - 0x17c 0 /* I2C0_SCL (IOCFG103) */ - 0x180 0 /* I2C0_SDA (IOCFG104) */ - >; - pinctrl-single,bias-pulldown = <0 2 0 2>; - pinctrl-single,bias-pullup = <0 1 0 1>; - pinctrl-single,drive-strength = <0x30 0xf0>; - }; - i2c1_cfg_func: i2c1_cfg_func { - pinctrl-single,pins = < - 0x184 0 /* I2C1_SCL (IOCFG105) */ - 0x188 0 /* I2C1_SDA (IOCFG106) */ - >; - pinctrl-single,bias-pulldown = <0 2 0 2>; - pinctrl-single,bias-pullup = <0 1 0 1>; - pinctrl-single,drive-strength = <0x30 0xf0>; - }; - i2c2_cfg_func: i2c2_cfg_func { - pinctrl-single,pins = < - 0x118 0 /* I2C2_SCL (IOCFG79) */ - 0x11c 0 /* I2C2_SDA (IOCFG80) */ - >; - pinctrl-single,bias-pulldown = <0 2 0 2>; - pinctrl-single,bias-pullup = <0 1 0 1>; - pinctrl-single,drive-strength = <0x30 0xf0>; - }; - i2c3_cfg_func: i2c3_cfg_func { - pinctrl-single,pins = < - 0x100 0 /* I2C3_SCL (IOCFG73) */ - 0x104 0 /* I2C3_SDA (IOCFG74) */ - >; - pinctrl-single,bias-pulldown = <0 2 0 2>; - pinctrl-single,bias-pullup = <0 1 0 1>; - pinctrl-single,drive-strength = <0x30 0xf0>; - }; - spi0_cfg_func1: spi0_cfg_func1 { - pinctrl-single,pins = < - 0x1d4 0 /* SPI0_CLK (IOCFG125) */ - 0x1d8 0 /* SPI0_DI (IOCFG126) */ - 0x1dc 0 /* SPI0_DO (IOCFG127) */ - >; - pinctrl-single,bias-pulldown = <2 2 0 2>; - pinctrl-single,bias-pullup = <0 1 0 1>; - pinctrl-single,drive-strength = <0x30 0xf0>; - }; - spi0_cfg_func2: spi0_cfg_func2 { - pinctrl-single,pins = < - 0x1e0 0 /* SPI0_CS0 (IOCFG128) */ - 0x1e4 0 /* SPI0_CS1 (IOCFG129) */ - 0x1e8 0 /* SPI0_CS2 (IOCFG130 */ - 0x1ec 0 /* SPI0_CS3 (IOCFG131) */ - >; - pinctrl-single,bias-pulldown = <0 2 0 2>; - pinctrl-single,bias-pullup = <1 1 0 1>; - pinctrl-single,drive-strength = <0x30 0xf0>; - }; - spi1_cfg_func1: spi1_cfg_func1 { - pinctrl-single,pins = < - 0x1f0 0 /* SPI1_CLK (IOCFG132) */ - 0x1f4 0 /* SPI1_DI (IOCFG133) */ - 0x1f8 0 /* SPI1_DO (IOCFG134) */ - >; - pinctrl-single,bias-pulldown = <2 2 0 2>; - pinctrl-single,bias-pullup = <0 1 0 1>; - pinctrl-single,drive-strength = <0x30 0xf0>; - }; - spi1_cfg_func2: spi1_cfg_func2 { - pinctrl-single,pins = < - 0x1fc 0 /* SPI1_CS (IOCFG135) */ - >; - pinctrl-single,bias-pulldown = <0 2 0 2>; - pinctrl-single,bias-pullup = <1 1 0 1>; - pinctrl-single,drive-strength = <0x30 0xf0>; - }; - kpc_cfg_func: kpc_cfg_func { - pinctrl-single,pins = < - 0x250 0 /* KEY_IN0 (IOCFG156) */ - 0x254 0 /* KEY_IN1 (IOCFG157) */ - 0x258 0 /* KEY_IN2 (IOCFG158) */ - 0x230 0 /* KEY_OUT0 (IOCFG148) */ - 0x234 0 /* KEY_OUT1 (IOCFG149) */ - 0x238 0 /* KEY_OUT2 (IOCFG150) */ - >; - pinctrl-single,bias-pulldown = <2 2 0 2>; - pinctrl-single,bias-pullup = <0 1 0 1>; - }; - emmc_cfg_func: emmc_cfg_func { - pinctrl-single,pins = < - 0x0ac 0 /* eMMC_CMD (IOCFG40) */ - 0x0b0 0 /* eMMC_CLK (IOCFG41) */ - 0x058 0 /* NAND_CS3_N (IOCFG19) */ - 0x064 0 /* NAND_BUSY2_N (IOCFG22) */ - 0x068 0 /* NAND_BUSY3_N (IOCFG23) */ - 0x08c 0 /* NAND_DATA8 (IOCFG32) */ - 0x090 0 /* NAND_DATA9 (IOCFG33) */ - 0x094 0 /* NAND_DATA10 (IOCFG34) */ - 0x098 0 /* NAND_DATA11 (IOCFG35) */ - 0x09c 0 /* NAND_DATA12 (IOCFG36) */ - 0x0a0 0 /* NAND_DATA13 (IOCFG37) */ - 0x0a4 0 /* NAND_DATA14 (IOCFG38) */ - 0x0a8 0 /* NAND_DATA15 (IOCFG39) */ - >; - pinctrl-single,bias-pulldown = <0 2 0 2>; - pinctrl-single,bias-pullup = <1 1 0 1>; - pinctrl-single,drive-strength = <0x30 0xf0>; - }; - sd_cfg_func1: sd_cfg_func1 { - pinctrl-single,pins = < - 0x18c 0 /* SD_CLK (IOCFG107) */ - 0x190 0 /* SD_CMD (IOCFG108) */ - >; - pinctrl-single,bias-pulldown = <2 2 0 2>; - pinctrl-single,bias-pullup = <0 1 0 1>; - pinctrl-single,drive-strength = <0x30 0xf0>; - }; - sd_cfg_func2: sd_cfg_func2 { - pinctrl-single,pins = < - 0x194 0 /* SD_DATA0 (IOCFG109) */ - 0x198 0 /* SD_DATA1 (IOCFG110) */ - 0x19c 0 /* SD_DATA2 (IOCFG111) */ - 0x1a0 0 /* SD_DATA3 (IOCFG112) */ - >; - pinctrl-single,bias-pulldown = <2 2 0 2>; - pinctrl-single,bias-pullup = <0 1 0 1>; - pinctrl-single,drive-strength = <0x70 0xf0>; - }; - nand_cfg_func1: nand_cfg_func1 { - pinctrl-single,pins = < - 0x03c 0 /* NAND_ALE (IOCFG12) */ - 0x040 0 /* NAND_CLE (IOCFG13) */ - 0x06c 0 /* NAND_DATA0 (IOCFG24) */ - 0x070 0 /* NAND_DATA1 (IOCFG25) */ - 0x074 0 /* NAND_DATA2 (IOCFG26) */ - 0x078 0 /* NAND_DATA3 (IOCFG27) */ - 0x07c 0 /* NAND_DATA4 (IOCFG28) */ - 0x080 0 /* NAND_DATA5 (IOCFG29) */ - 0x084 0 /* NAND_DATA6 (IOCFG30) */ - 0x088 0 /* NAND_DATA7 (IOCFG31) */ - 0x08c 0 /* NAND_DATA8 (IOCFG32) */ - 0x090 0 /* NAND_DATA9 (IOCFG33) */ - 0x094 0 /* NAND_DATA10 (IOCFG34) */ - 0x098 0 /* NAND_DATA11 (IOCFG35) */ - 0x09c 0 /* NAND_DATA12 (IOCFG36) */ - 0x0a0 0 /* NAND_DATA13 (IOCFG37) */ - 0x0a4 0 /* NAND_DATA14 (IOCFG38) */ - 0x0a8 0 /* NAND_DATA15 (IOCFG39) */ - >; - pinctrl-single,bias-pulldown = <2 2 0 2>; - pinctrl-single,bias-pullup = <0 1 0 1>; - pinctrl-single,drive-strength = <0x30 0xf0>; - }; - nand_cfg_func2: nand_cfg_func2 { - pinctrl-single,pins = < - 0x044 0 /* NAND_RE_N (IOCFG14) */ - 0x048 0 /* NAND_WE_N (IOCFG15) */ - 0x04c 0 /* NAND_CS0_N (IOCFG16) */ - 0x050 0 /* NAND_CS1_N (IOCFG17) */ - 0x054 0 /* NAND_CS2_N (IOCFG18) */ - 0x058 0 /* NAND_CS3_N (IOCFG19) */ - 0x05c 0 /* NAND_BUSY0_N (IOCFG20) */ - 0x060 0 /* NAND_BUSY1_N (IOCFG21) */ - 0x064 0 /* NAND_BUSY2_N (IOCFG22) */ - 0x068 0 /* NAND_BUSY3_N (IOCFG23) */ - >; - pinctrl-single,bias-pulldown = <0 2 0 2>; - pinctrl-single,bias-pullup = <1 1 0 1>; - pinctrl-single,drive-strength = <0x30 0xf0>; - }; - sdio_cfg_func: sdio_cfg_func { - pinctrl-single,pins = < - 0x1a4 0 /* SDIO0_CLK (IOCG113) */ - 0x1a8 0 /* SDIO0_CMD (IOCG114) */ - 0x1ac 0 /* SDIO0_DATA0 (IOCG115) */ - 0x1b0 0 /* SDIO0_DATA1 (IOCG116) */ - 0x1b4 0 /* SDIO0_DATA2 (IOCG117) */ - 0x1b8 0 /* SDIO0_DATA3 (IOCG118) */ - >; - pinctrl-single,bias-pulldown = <2 2 0 2>; - pinctrl-single,bias-pullup = <0 1 0 1>; - pinctrl-single,drive-strength = <0x30 0xf0>; - }; - audio_out_cfg_func: audio_out_cfg_func { - pinctrl-single,pins = < - 0x200 0 /* GPIO (IOCFG136) */ - 0x204 0 /* GPIO (IOCFG137) */ - >; - pinctrl-single,bias-pulldown = <2 2 0 2>; - pinctrl-single,bias-pullup = <0 1 0 1>; - }; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - call { - label = "call"; - gpios = <&gpio17 2 0>; - linux,code = <169>; /* KEY_PHONE */ - }; - }; -}; diff --git a/sys/gnu/dts/arm/hi3620.dtsi b/sys/gnu/dts/arm/hi3620.dtsi deleted file mode 100644 index 9c207a690df..00000000000 --- a/sys/gnu/dts/arm/hi3620.dtsi +++ /dev/null @@ -1,567 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Hisilicon Ltd. Hi3620 SoC - * - * Copyright (C) 2012-2013 Hisilicon Ltd. - * Copyright (C) 2012-2013 Linaro Ltd. - * - * Author: Haojian Zhuang - */ - -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - serial4 = &uart4; - }; - - pclk: clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <26000000>; - clock-output-names = "apb_pclk"; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "hisilicon,hi3620-smp"; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0x0>; - next-level-cache = <&L2>; - }; - - cpu@1 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - reg = <1>; - next-level-cache = <&L2>; - }; - - cpu@2 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - reg = <2>; - next-level-cache = <&L2>; - }; - - cpu@3 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - reg = <3>; - next-level-cache = <&L2>; - }; - }; - - amba { - - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&gic>; - ranges = <0 0xfc000000 0x2000000>; - - L2: l2-cache { - compatible = "arm,pl310-cache"; - reg = <0x100000 0x100000>; - interrupts = <0 15 4>; - cache-unified; - cache-level = <2>; - }; - - gic: interrupt-controller@1000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - /* gic dist base, gic cpu base */ - reg = <0x1000 0x1000>, <0x100 0x100>; - }; - - sysctrl: system-controller@802000 { - compatible = "hisilicon,sysctrl"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x802000 0x1000>; - reg = <0x802000 0x1000>; - - smp-offset = <0x31c>; - resume-offset = <0x308>; - reboot-offset = <0x4>; - - clock: clock@0 { - compatible = "hisilicon,hi3620-clock"; - reg = <0 0x10000>; - #clock-cells = <1>; - }; - }; - - dual_timer0: dual_timer@800000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x800000 0x1000>; - /* timer00 & timer01 */ - interrupts = <0 0 4>, <0 1 4>; - clocks = <&clock HI3620_TIMER0_MUX>, <&clock HI3620_TIMER1_MUX>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - dual_timer1: dual_timer@801000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x801000 0x1000>; - /* timer10 & timer11 */ - interrupts = <0 2 4>, <0 3 4>; - clocks = <&clock HI3620_TIMER2_MUX>, <&clock HI3620_TIMER3_MUX>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - dual_timer2: dual_timer@a01000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0xa01000 0x1000>; - /* timer20 & timer21 */ - interrupts = <0 4 4>, <0 5 4>; - clocks = <&clock HI3620_TIMER4_MUX>, <&clock HI3620_TIMER5_MUX>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - dual_timer3: dual_timer@a02000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0xa02000 0x1000>; - /* timer30 & timer31 */ - interrupts = <0 6 4>, <0 7 4>; - clocks = <&clock HI3620_TIMER6_MUX>, <&clock HI3620_TIMER7_MUX>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - dual_timer4: dual_timer@a03000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0xa03000 0x1000>; - /* timer40 & timer41 */ - interrupts = <0 96 4>, <0 97 4>; - clocks = <&clock HI3620_TIMER8_MUX>, <&clock HI3620_TIMER9_MUX>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - timer5: timer@600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0x600 0x20>; - interrupts = <1 13 0xf01>; - }; - - uart0: uart@b00000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0xb00000 0x1000>; - interrupts = <0 20 4>; - clocks = <&clock HI3620_UARTCLK0>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - uart1: uart@b01000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0xb01000 0x1000>; - interrupts = <0 21 4>; - clocks = <&clock HI3620_UARTCLK1>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - uart2: uart@b02000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0xb02000 0x1000>; - interrupts = <0 22 4>; - clocks = <&clock HI3620_UARTCLK2>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - uart3: uart@b03000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0xb03000 0x1000>; - interrupts = <0 23 4>; - clocks = <&clock HI3620_UARTCLK3>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - uart4: uart@b04000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0xb04000 0x1000>; - interrupts = <0 24 4>; - clocks = <&clock HI3620_UARTCLK4>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - gpio0: gpio@806000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x806000 0x1000>; - interrupts = <0 64 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = < &pmx0 2 0 1 &pmx0 3 0 1 &pmx0 4 0 1 - &pmx0 5 0 1 &pmx0 6 1 1 &pmx0 7 2 1>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&clock HI3620_GPIOCLK0>; - clock-names = "apb_pclk"; - }; - - gpio1: gpio@807000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x807000 0x1000>; - interrupts = <0 65 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = < &pmx0 0 3 1 &pmx0 1 3 1 &pmx0 2 3 1 - &pmx0 3 3 1 &pmx0 4 3 1 &pmx0 5 4 1 - &pmx0 6 5 1 &pmx0 7 6 1>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&clock HI3620_GPIOCLK1>; - clock-names = "apb_pclk"; - }; - - gpio2: gpio@808000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x808000 0x1000>; - interrupts = <0 66 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = < &pmx0 0 7 1 &pmx0 1 8 1 &pmx0 2 9 1 - &pmx0 3 10 1 &pmx0 4 3 1 &pmx0 5 3 1 - &pmx0 6 3 1 &pmx0 7 3 1>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&clock HI3620_GPIOCLK2>; - clock-names = "apb_pclk"; - }; - - gpio3: gpio@809000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x809000 0x1000>; - interrupts = <0 67 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = < &pmx0 0 3 1 &pmx0 1 3 1 &pmx0 2 3 1 - &pmx0 3 3 1 &pmx0 4 11 1 &pmx0 5 11 1 - &pmx0 6 11 1 &pmx0 7 11 1>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&clock HI3620_GPIOCLK3>; - clock-names = "apb_pclk"; - }; - - gpio4: gpio@80a000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x80a000 0x1000>; - interrupts = <0 68 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = < &pmx0 0 11 1 &pmx0 1 11 1 &pmx0 2 11 1 - &pmx0 3 11 1 &pmx0 4 12 1 &pmx0 5 12 1 - &pmx0 6 13 1 &pmx0 7 13 1>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&clock HI3620_GPIOCLK4>; - clock-names = "apb_pclk"; - }; - - gpio5: gpio@80b000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x80b000 0x1000>; - interrupts = <0 69 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = < &pmx0 0 14 1 &pmx0 1 15 1 &pmx0 2 16 1 - &pmx0 3 16 1 &pmx0 4 16 1 &pmx0 5 16 1 - &pmx0 6 16 1 &pmx0 7 16 1>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&clock HI3620_GPIOCLK5>; - clock-names = "apb_pclk"; - }; - - gpio6: gpio@80c000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x80c000 0x1000>; - interrupts = <0 70 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = < &pmx0 0 16 1 &pmx0 1 16 1 &pmx0 2 17 1 - &pmx0 3 17 1 &pmx0 4 18 1 &pmx0 5 18 1 - &pmx0 6 18 1 &pmx0 7 19 1>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&clock HI3620_GPIOCLK6>; - clock-names = "apb_pclk"; - }; - - gpio7: gpio@80d000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x80d000 0x1000>; - interrupts = <0 71 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = < &pmx0 0 19 1 &pmx0 1 20 1 &pmx0 2 21 1 - &pmx0 3 22 1 &pmx0 4 23 1 &pmx0 5 24 1 - &pmx0 6 25 1 &pmx0 7 26 1>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&clock HI3620_GPIOCLK7>; - clock-names = "apb_pclk"; - }; - - gpio8: gpio@80e000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x80e000 0x1000>; - interrupts = <0 72 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = < &pmx0 0 27 1 &pmx0 1 28 1 &pmx0 2 29 1 - &pmx0 3 30 1 &pmx0 4 31 1 &pmx0 5 32 1 - &pmx0 6 33 1 &pmx0 7 34 1>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&clock HI3620_GPIOCLK8>; - clock-names = "apb_pclk"; - }; - - gpio9: gpio@80f000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x80f000 0x1000>; - interrupts = <0 73 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = < &pmx0 0 35 1 &pmx0 1 36 1 &pmx0 2 37 1 - &pmx0 3 38 1 &pmx0 4 39 1 &pmx0 5 40 1 - &pmx0 6 41 1>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&clock HI3620_GPIOCLK9>; - clock-names = "apb_pclk"; - }; - - gpio10: gpio@810000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x810000 0x1000>; - interrupts = <0 74 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = < &pmx0 2 43 1 &pmx0 3 44 1 &pmx0 4 45 1 - &pmx0 5 45 1 &pmx0 6 46 1 &pmx0 7 46 1>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&clock HI3620_GPIOCLK10>; - clock-names = "apb_pclk"; - }; - - gpio11: gpio@811000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x811000 0x1000>; - interrupts = <0 75 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = < &pmx0 0 47 1 &pmx0 1 47 1 &pmx0 2 47 1 - &pmx0 3 47 1 &pmx0 4 47 1 &pmx0 5 48 1 - &pmx0 6 49 1 &pmx0 7 49 1>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&clock HI3620_GPIOCLK11>; - clock-names = "apb_pclk"; - }; - - gpio12: gpio@812000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x812000 0x1000>; - interrupts = <0 76 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = < &pmx0 0 49 1 &pmx0 1 50 1 &pmx0 2 49 1 - &pmx0 3 49 1 &pmx0 4 51 1 &pmx0 5 51 1 - &pmx0 6 51 1 &pmx0 7 52 1>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&clock HI3620_GPIOCLK12>; - clock-names = "apb_pclk"; - }; - - gpio13: gpio@813000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x813000 0x1000>; - interrupts = <0 77 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = < &pmx0 0 51 1 &pmx0 1 51 1 &pmx0 2 53 1 - &pmx0 3 53 1 &pmx0 4 53 1 &pmx0 5 54 1 - &pmx0 6 55 1 &pmx0 7 56 1>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&clock HI3620_GPIOCLK13>; - clock-names = "apb_pclk"; - }; - - gpio14: gpio@814000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x814000 0x1000>; - interrupts = <0 78 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = < &pmx0 0 57 1 &pmx0 1 97 1 &pmx0 2 97 1 - &pmx0 3 58 1 &pmx0 4 59 1 &pmx0 5 60 1 - &pmx0 6 60 1 &pmx0 7 61 1>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&clock HI3620_GPIOCLK14>; - clock-names = "apb_pclk"; - }; - - gpio15: gpio@815000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x815000 0x1000>; - interrupts = <0 79 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = < &pmx0 0 61 1 &pmx0 1 62 1 &pmx0 2 62 1 - &pmx0 3 63 1 &pmx0 4 63 1 &pmx0 5 64 1 - &pmx0 6 64 1 &pmx0 7 65 1>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&clock HI3620_GPIOCLK15>; - clock-names = "apb_pclk"; - }; - - gpio16: gpio@816000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x816000 0x1000>; - interrupts = <0 80 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = < &pmx0 0 66 1 &pmx0 1 67 1 &pmx0 2 68 1 - &pmx0 3 69 1 &pmx0 4 70 1 &pmx0 5 71 1 - &pmx0 6 72 1 &pmx0 7 73 1>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&clock HI3620_GPIOCLK16>; - clock-names = "apb_pclk"; - }; - - gpio17: gpio@817000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x817000 0x1000>; - interrupts = <0 81 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = < &pmx0 0 74 1 &pmx0 1 75 1 &pmx0 2 76 1 - &pmx0 3 77 1 &pmx0 4 78 1 &pmx0 5 79 1 - &pmx0 6 80 1 &pmx0 7 81 1>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&clock HI3620_GPIOCLK17>; - clock-names = "apb_pclk"; - }; - - gpio18: gpio@818000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x818000 0x1000>; - interrupts = <0 82 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = < &pmx0 0 82 1 &pmx0 1 83 1 &pmx0 2 83 1 - &pmx0 3 84 1 &pmx0 4 84 1 &pmx0 5 85 1 - &pmx0 6 86 1 &pmx0 7 87 1>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&clock HI3620_GPIOCLK18>; - clock-names = "apb_pclk"; - }; - - gpio19: gpio@819000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x819000 0x1000>; - interrupts = <0 83 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = < &pmx0 0 87 1 &pmx0 1 87 1 &pmx0 2 88 1 - &pmx0 3 88 1>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&clock HI3620_GPIOCLK19>; - clock-names = "apb_pclk"; - }; - - gpio20: gpio@81a000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x81a000 0x1000>; - interrupts = <0 84 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = < &pmx0 0 89 1 &pmx0 1 89 1 &pmx0 2 90 1 - &pmx0 3 90 1 &pmx0 4 91 1 &pmx0 5 92 1>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&clock HI3620_GPIOCLK20>; - clock-names = "apb_pclk"; - }; - - gpio21: gpio@81b000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x81b000 0x1000>; - interrupts = <0 85 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = < &pmx0 3 94 1 &pmx0 7 96 1>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&clock HI3620_GPIOCLK21>; - clock-names = "apb_pclk"; - }; - - pmx0: pinmux@803000 { - compatible = "pinctrl-single"; - reg = <0x803000 0x188>; - #address-cells = <1>; - #size-cells = <1>; - #pinctrl-cells = <1>; - #gpio-range-cells = <3>; - ranges; - - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <7>; - /* pin base, nr pins & gpio function */ - pinctrl-single,gpio-range = <&range 0 3 0 &range 3 9 1 - &range 12 1 0 &range 13 29 1 - &range 43 1 0 &range 44 49 1 - &range 94 1 1 &range 96 2 1>; - - range: gpio-range { - #pinctrl-single,gpio-range-cells = <3>; - }; - }; - - pmx1: pinmux@803800 { - compatible = "pinconf-single"; - reg = <0x803800 0x2dc>; - #address-cells = <1>; - #size-cells = <1>; - #pinctrl-cells = <1>; - ranges; - - pinctrl-single,register-width = <32>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/highbank.dts b/sys/gnu/dts/arm/highbank.dts deleted file mode 100644 index f4e4dca6f7e..00000000000 --- a/sys/gnu/dts/arm/highbank.dts +++ /dev/null @@ -1,161 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright 2011-2012 Calxeda, Inc. - */ - -/dts-v1/; - -/* First 4KB has pen for secondary cores. */ -/memreserve/ 0x00000000 0x0001000; - -/ { - model = "Calxeda Highbank"; - compatible = "calxeda,highbank"; - #address-cells = <1>; - #size-cells = <1>; - clock-ranges; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@900 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - reg = <0x900>; - next-level-cache = <&L2>; - clocks = <&a9pll>; - clock-names = "cpu"; - operating-points = < - /* kHz ignored */ - 1300000 1000000 - 1200000 1000000 - 1100000 1000000 - 800000 1000000 - 400000 1000000 - 200000 1000000 - >; - clock-latency = <100000>; - }; - - cpu@901 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - reg = <0x901>; - next-level-cache = <&L2>; - clocks = <&a9pll>; - clock-names = "cpu"; - operating-points = < - /* kHz ignored */ - 1300000 1000000 - 1200000 1000000 - 1100000 1000000 - 800000 1000000 - 400000 1000000 - 200000 1000000 - >; - clock-latency = <100000>; - }; - - cpu@902 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - reg = <0x902>; - next-level-cache = <&L2>; - clocks = <&a9pll>; - clock-names = "cpu"; - operating-points = < - /* kHz ignored */ - 1300000 1000000 - 1200000 1000000 - 1100000 1000000 - 800000 1000000 - 400000 1000000 - 200000 1000000 - >; - clock-latency = <100000>; - }; - - cpu@903 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - reg = <0x903>; - next-level-cache = <&L2>; - clocks = <&a9pll>; - clock-names = "cpu"; - operating-points = < - /* kHz ignored */ - 1300000 1000000 - 1200000 1000000 - 1100000 1000000 - 800000 1000000 - 400000 1000000 - 200000 1000000 - >; - clock-latency = <100000>; - }; - }; - - memory { - name = "memory"; - device_type = "memory"; - reg = <0x00000000 0xff900000>; - }; - - soc { - ranges = <0x00000000 0x00000000 0xffffffff>; - - memory-controller@fff00000 { - compatible = "calxeda,hb-ddr-ctrl"; - reg = <0xfff00000 0x1000>; - interrupts = <0 91 4>; - }; - - timer@fff10600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0xfff10600 0x20>; - interrupts = <1 13 0xf01>; - clocks = <&a9periphclk>; - }; - - watchdog@fff10620 { - compatible = "arm,cortex-a9-twd-wdt"; - reg = <0xfff10620 0x20>; - interrupts = <1 14 0xf01>; - clocks = <&a9periphclk>; - }; - - intc: interrupt-controller@fff11000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #size-cells = <0>; - #address-cells = <1>; - interrupt-controller; - reg = <0xfff11000 0x1000>, - <0xfff10100 0x100>; - }; - - L2: l2-cache { - compatible = "arm,pl310-cache"; - reg = <0xfff12000 0x1000>; - interrupts = <0 70 4>; - cache-unified; - cache-level = <2>; - }; - - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts = <0 76 4 0 75 4 0 74 4 0 73 4>; - }; - - - sregs@fff3c200 { - compatible = "calxeda,hb-sregs-l2-ecc"; - reg = <0xfff3c200 0x100>; - interrupts = <0 71 4 0 72 4>; - }; - - }; -}; - -/include/ "ecx-common.dtsi" diff --git a/sys/gnu/dts/arm/hip01-ca9x2.dts b/sys/gnu/dts/arm/hip01-ca9x2.dts deleted file mode 100644 index f05e74eacfe..00000000000 --- a/sys/gnu/dts/arm/hip01-ca9x2.dts +++ /dev/null @@ -1,48 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Hisilicon Ltd. HiP01 SoC - * - * Copyright (C) 2014 Hisilicon Ltd. - * Copyright (C) 2014 Huawei Ltd. - * - * Author: Wang Long - */ - -/dts-v1/; - -/* First 8KB reserved for secondary core boot */ -/memreserve/ 0x80000000 0x00002000; - -#include "hip01.dtsi" - -/ { - model = "Hisilicon HIP01 Development Board"; - compatible = "hisilicon,hip01-ca9x2", "hisilicon,hip01"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "hisilicon,hip01-smp"; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <1>; - }; - }; - - memory { - device_type = "memory"; - reg = <0x80000000 0x80000000>; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/hip01.dtsi b/sys/gnu/dts/arm/hip01.dtsi deleted file mode 100644 index 975d3982840..00000000000 --- a/sys/gnu/dts/arm/hip01.dtsi +++ /dev/null @@ -1,105 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Hisilicon Ltd. HiP01 SoC - * - * Copyright (c) 2014 Hisilicon Ltd. - * Copyright (c) 2014 Huawei Ltd. - * - * Author: Wang Long - */ - -/ { - interrupt-parent = <&gic>; - #address-cells = <1>; - #size-cells = <1>; - - gic: interrupt-controller@1e001000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x1a001000 0x1000>, <0x1a000100 0x1000>; - }; - - hisi_refclk144mhz: refclk144mkhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <144000000>; - clock-output-names = "hisi:refclk144khz"; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&gic>; - ranges = <0 0x10000000 0x20000000>; - - amba { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges; - - uart0: uart@10001000 { - compatible = "snps,dw-apb-uart"; - reg = <0x10001000 0x1000>; - clocks = <&hisi_refclk144mhz>; - clock-names = "apb_pclk"; - reg-shift = <2>; - interrupts = <0 32 4>; - status = "disabled"; - }; - - uart1: uart@10002000 { - compatible = "snps,dw-apb-uart"; - reg = <0x10002000 0x1000>; - clocks = <&hisi_refclk144mhz>; - clock-names = "apb_pclk"; - reg-shift = <2>; - interrupts = <0 33 4>; - status = "disabled"; - }; - - uart2: uart@10003000 { - compatible = "snps,dw-apb-uart"; - reg = <0x10003000 0x1000>; - clocks = <&hisi_refclk144mhz>; - clock-names = "apb_pclk"; - reg-shift = <2>; - interrupts = <0 34 4>; - status = "disabled"; - }; - - uart3: uart@10006000 { - compatible = "snps,dw-apb-uart"; - reg = <0x10006000 0x1000>; - clocks = <&hisi_refclk144mhz>; - clock-names = "apb_pclk"; - reg-shift = <2>; - interrupts = <0 4 4>; - status = "disabled"; - }; - }; - - system-controller@10000000 { - compatible = "hisilicon,hip01-sysctrl", "hisilicon,sysctrl"; - reg = <0x10000000 0x1000>; - reboot-offset = <0x4>; - }; - - global_timer@a000200 { - compatible = "arm,cortex-a9-global-timer"; - reg = <0x0a000200 0x100>; - interrupts = <1 11 0xf04>; - clocks = <&hisi_refclk144mhz>; - }; - - local_timer@a000600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0x0a000600 0x100>; - interrupts = <1 13 0xf04>; - clocks = <&hisi_refclk144mhz>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/hip04-d01.dts b/sys/gnu/dts/arm/hip04-d01.dts deleted file mode 100644 index 9019e0d2ef6..00000000000 --- a/sys/gnu/dts/arm/hip04-d01.dts +++ /dev/null @@ -1,29 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2013-2014 Linaro Ltd. - * Author: Haojian Zhuang - */ - -/dts-v1/; - -#include "hip04.dtsi" - -/ { - /* memory bus is 64-bit */ - #address-cells = <2>; - #size-cells = <2>; - model = "Hisilicon D01 Development Board"; - compatible = "hisilicon,hip04-d01"; - - memory@0,10000000 { - device_type = "memory"; - reg = <0x00000000 0x10000000 0x00000000 0xc0000000>, - <0x00000004 0xc0000000 0x00000003 0x40000000>; - }; - - soc { - uart0: uart@4007000 { - status = "ok"; - }; - }; -}; diff --git a/sys/gnu/dts/arm/hip04.dtsi b/sys/gnu/dts/arm/hip04.dtsi deleted file mode 100644 index 4263a9339c2..00000000000 --- a/sys/gnu/dts/arm/hip04.dtsi +++ /dev/null @@ -1,986 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Hisilicon Ltd. HiP04 SoC - * - * Copyright (C) 2013-2014 Hisilicon Ltd. - * Copyright (C) 2013-2014 Linaro Ltd. - * - * Author: Haojian Zhuang - */ - -/ { - /* memory bus is 64-bit */ - #address-cells = <2>; - #size-cells = <2>; - - aliases { - serial0 = &uart0; - }; - - bootwrapper { - compatible = "hisilicon,hip04-bootwrapper"; - boot-method = <0x10c00000 0x10000>, <0xe0000100 0x1000>; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu-map { - cluster0 { - core0 { - cpu = <&CPU0>; - }; - core1 { - cpu = <&CPU1>; - }; - core2 { - cpu = <&CPU2>; - }; - core3 { - cpu = <&CPU3>; - }; - }; - cluster1 { - core0 { - cpu = <&CPU4>; - }; - core1 { - cpu = <&CPU5>; - }; - core2 { - cpu = <&CPU6>; - }; - core3 { - cpu = <&CPU7>; - }; - }; - cluster2 { - core0 { - cpu = <&CPU8>; - }; - core1 { - cpu = <&CPU9>; - }; - core2 { - cpu = <&CPU10>; - }; - core3 { - cpu = <&CPU11>; - }; - }; - cluster3 { - core0 { - cpu = <&CPU12>; - }; - core1 { - cpu = <&CPU13>; - }; - core2 { - cpu = <&CPU14>; - }; - core3 { - cpu = <&CPU15>; - }; - }; - }; - CPU0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0>; - }; - CPU1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <1>; - }; - CPU2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <2>; - }; - CPU3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <3>; - }; - CPU4: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x100>; - }; - CPU5: cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x101>; - }; - CPU6: cpu@102 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x102>; - }; - CPU7: cpu@103 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x103>; - }; - CPU8: cpu@200 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x200>; - }; - CPU9: cpu@201 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x201>; - }; - CPU10: cpu@202 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x202>; - }; - CPU11: cpu@203 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x203>; - }; - CPU12: cpu@300 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x300>; - }; - CPU13: cpu@301 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x301>; - }; - CPU14: cpu@302 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x302>; - }; - CPU15: cpu@303 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x303>; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupt-parent = <&gic>; - interrupts = <1 13 0xf08>, - <1 14 0xf08>, - <1 11 0xf08>, - <1 10 0xf08>; - }; - - clk_50m: clk_50m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <50000000>; - }; - - clk_168m: clk_168m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <168000000>; - }; - - clk_375m: clk_375m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <375000000>; - }; - - soc { - /* It's a 32-bit SoC. */ - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&gic>; - ranges = <0 0 0xe0000000 0x10000000>; - - gic: interrupt-controller@c01000 { - compatible = "hisilicon,hip04-intc"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - interrupts = <1 9 0xf04>; - - reg = <0xc01000 0x1000>, <0xc02000 0x1000>, - <0xc04000 0x2000>, <0xc06000 0x2000>; - }; - - sysctrl: sysctrl { - compatible = "hisilicon,sysctrl"; - reg = <0x3e00000 0x00100000>; - }; - - fabric: fabric { - compatible = "hisilicon,hip04-fabric"; - reg = <0x302a000 0x1000>; - }; - - dual_timer0: dual_timer@3000000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x3000000 0x1000>; - interrupts = <0 224 4>; - clocks = <&clk_50m>, <&clk_50m>; - clock-names = "apb_pclk"; - }; - - arm-pmu { - compatible = "arm,cortex-a15-pmu"; - interrupts = <0 64 4>, - <0 65 4>, - <0 66 4>, - <0 67 4>, - <0 68 4>, - <0 69 4>, - <0 70 4>, - <0 71 4>, - <0 72 4>, - <0 73 4>, - <0 74 4>, - <0 75 4>, - <0 76 4>, - <0 77 4>, - <0 78 4>, - <0 79 4>; - }; - - uart0: uart@4007000 { - compatible = "snps,dw-apb-uart"; - reg = <0x4007000 0x1000>; - interrupts = <0 381 4>; - clocks = <&clk_168m>; - clock-names = "uartclk"; - reg-shift = <2>; - status = "disabled"; - }; - - sata0: sata@a000000 { - compatible = "hisilicon,hisi-ahci"; - reg = <0xa000000 0x1000000>; - interrupts = <0 372 4>; - }; - - }; - - etb@0,e3c42000 { - compatible = "arm,coresight-etb10", "arm,primecell"; - reg = <0 0xe3c42000 0 0x1000>; - - clocks = <&clk_375m>; - clock-names = "apb_pclk"; - in-ports { - port { - etb0_in_port: endpoint@0 { - remote-endpoint = <&replicator0_out_port0>; - }; - }; - }; - }; - - etb@0,e3c82000 { - compatible = "arm,coresight-etb10", "arm,primecell"; - reg = <0 0xe3c82000 0 0x1000>; - - clocks = <&clk_375m>; - clock-names = "apb_pclk"; - in-ports { - port { - etb1_in_port: endpoint@0 { - remote-endpoint = <&replicator1_out_port0>; - }; - }; - }; - }; - - etb@0,e3cc2000 { - compatible = "arm,coresight-etb10", "arm,primecell"; - reg = <0 0xe3cc2000 0 0x1000>; - - clocks = <&clk_375m>; - clock-names = "apb_pclk"; - in-ports { - port { - etb2_in_port: endpoint@0 { - remote-endpoint = <&replicator2_out_port0>; - }; - }; - }; - }; - - etb@0,e3d02000 { - compatible = "arm,coresight-etb10", "arm,primecell"; - reg = <0 0xe3d02000 0 0x1000>; - - clocks = <&clk_375m>; - clock-names = "apb_pclk"; - in-ports { - port { - etb3_in_port: endpoint@0 { - remote-endpoint = <&replicator3_out_port0>; - }; - }; - }; - }; - - tpiu@0,e3c05000 { - compatible = "arm,coresight-tpiu", "arm,primecell"; - reg = <0 0xe3c05000 0 0x1000>; - - clocks = <&clk_375m>; - clock-names = "apb_pclk"; - in-ports { - port { - tpiu_in_port: endpoint@0 { - remote-endpoint = <&funnel4_out_port0>; - }; - }; - }; - }; - - replicator0 { - /* non-configurable replicators don't show up on the - * AMBA bus. As such no need to add "arm,primecell". - */ - compatible = "arm,coresight-static-replicator"; - - out-ports { - #address-cells = <1>; - #size-cells = <0>; - - /* replicator output ports */ - port@0 { - reg = <0>; - replicator0_out_port0: endpoint { - remote-endpoint = <&etb0_in_port>; - }; - }; - - port@1 { - reg = <1>; - replicator0_out_port1: endpoint { - remote-endpoint = <&funnel4_in_port0>; - }; - }; - }; - - in-ports { - port { - replicator0_in_port0: endpoint { - remote-endpoint = <&funnel0_out_port0>; - }; - }; - }; - }; - - replicator1 { - /* non-configurable replicators don't show up on the - * AMBA bus. As such no need to add "arm,primecell". - */ - compatible = "arm,coresight-static-replicator"; - - out-ports { - #address-cells = <1>; - #size-cells = <0>; - - /* replicator output ports */ - port@0 { - reg = <0>; - replicator1_out_port0: endpoint { - remote-endpoint = <&etb1_in_port>; - }; - }; - - port@1 { - reg = <1>; - replicator1_out_port1: endpoint { - remote-endpoint = <&funnel4_in_port1>; - }; - }; - }; - - in-ports { - port { - replicator1_in_port0: endpoint { - remote-endpoint = <&funnel1_out_port0>; - }; - }; - }; - }; - - replicator2 { - /* non-configurable replicators don't show up on the - * AMBA bus. As such no need to add "arm,primecell". - */ - compatible = "arm,coresight-static-replicator"; - - out-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - replicator2_out_port0: endpoint { - remote-endpoint = <&etb2_in_port>; - }; - }; - - port@1 { - reg = <1>; - replicator2_out_port1: endpoint { - remote-endpoint = <&funnel4_in_port2>; - }; - }; - }; - - in-ports { - port { - replicator2_in_port0: endpoint { - remote-endpoint = <&funnel2_out_port0>; - }; - }; - }; - }; - - replicator3 { - /* non-configurable replicators don't show up on the - * AMBA bus. As such no need to add "arm,primecell". - */ - compatible = "arm,coresight-static-replicator"; - - out-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - replicator3_out_port0: endpoint { - remote-endpoint = <&etb3_in_port>; - }; - }; - - port@1 { - reg = <1>; - replicator3_out_port1: endpoint { - remote-endpoint = <&funnel4_in_port3>; - }; - }; - }; - - in-ports { - port { - replicator3_in_port0: endpoint { - remote-endpoint = <&funnel3_out_port0>; - }; - }; - }; - }; - - funnel@0,e3c41000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0xe3c41000 0 0x1000>; - - clocks = <&clk_375m>; - clock-names = "apb_pclk"; - out-ports { - port { - funnel0_out_port0: endpoint { - remote-endpoint = - <&replicator0_in_port0>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - funnel0_in_port0: endpoint { - remote-endpoint = <&ptm0_out_port>; - }; - }; - - port@1 { - reg = <1>; - funnel0_in_port1: endpoint { - remote-endpoint = <&ptm1_out_port>; - }; - }; - - port@2 { - reg = <2>; - funnel0_in_port2: endpoint { - remote-endpoint = <&ptm2_out_port>; - }; - }; - - port@3 { - reg = <3>; - funnel0_in_port3: endpoint { - remote-endpoint = <&ptm3_out_port>; - }; - }; - }; - }; - - funnel@0,e3c81000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0xe3c81000 0 0x1000>; - - clocks = <&clk_375m>; - clock-names = "apb_pclk"; - out-ports { - port { - funnel1_out_port0: endpoint { - remote-endpoint = - <&replicator1_in_port0>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - funnel1_in_port0: endpoint { - remote-endpoint = <&ptm4_out_port>; - }; - }; - - port@1 { - reg = <1>; - funnel1_in_port1: endpoint { - remote-endpoint = <&ptm5_out_port>; - }; - }; - - port@2 { - reg = <2>; - funnel1_in_port2: endpoint { - remote-endpoint = <&ptm6_out_port>; - }; - }; - - port@3 { - reg = <3>; - funnel1_in_port3: endpoint { - remote-endpoint = <&ptm7_out_port>; - }; - }; - }; - }; - - funnel@0,e3cc1000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0xe3cc1000 0 0x1000>; - - clocks = <&clk_375m>; - clock-names = "apb_pclk"; - out-ports { - port { - funnel2_out_port0: endpoint { - remote-endpoint = - <&replicator2_in_port0>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - funnel2_in_port0: endpoint { - remote-endpoint = <&ptm8_out_port>; - }; - }; - - port@1 { - reg = <1>; - funnel2_in_port1: endpoint { - remote-endpoint = <&ptm9_out_port>; - }; - }; - - port@2 { - reg = <2>; - funnel2_in_port2: endpoint { - remote-endpoint = <&ptm10_out_port>; - }; - }; - - port@3 { - reg = <3>; - funnel2_in_port3: endpoint { - remote-endpoint = <&ptm11_out_port>; - }; - }; - }; - }; - - funnel@0,e3d01000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0xe3d01000 0 0x1000>; - - clocks = <&clk_375m>; - clock-names = "apb_pclk"; - out-ports { - port { - funnel3_out_port0: endpoint { - remote-endpoint = - <&replicator3_in_port0>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - funnel3_in_port0: endpoint { - remote-endpoint = <&ptm12_out_port>; - }; - }; - - port@1 { - reg = <1>; - funnel3_in_port1: endpoint { - remote-endpoint = <&ptm13_out_port>; - }; - }; - - port@2 { - reg = <2>; - funnel3_in_port2: endpoint { - remote-endpoint = <&ptm14_out_port>; - }; - }; - - port@3 { - reg = <3>; - funnel3_in_port3: endpoint { - remote-endpoint = <&ptm15_out_port>; - }; - }; - }; - }; - - funnel@0,e3c04000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0xe3c04000 0 0x1000>; - - clocks = <&clk_375m>; - clock-names = "apb_pclk"; - out-ports { - port { - funnel4_out_port0: endpoint { - remote-endpoint = <&tpiu_in_port>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - funnel4_in_port0: endpoint { - remote-endpoint = - <&replicator0_out_port1>; - }; - }; - - port@1 { - reg = <1>; - funnel4_in_port1: endpoint { - remote-endpoint = - <&replicator1_out_port1>; - }; - }; - - port@2 { - reg = <2>; - funnel4_in_port2: endpoint { - remote-endpoint = - <&replicator2_out_port1>; - }; - }; - - port@3 { - reg = <3>; - funnel4_in_port3: endpoint { - remote-endpoint = - <&replicator3_out_port1>; - }; - }; - }; - }; - - ptm@0,e3c7c000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0 0xe3c7c000 0 0x1000>; - - clocks = <&clk_375m>; - clock-names = "apb_pclk"; - cpu = <&CPU0>; - out-ports { - port { - ptm0_out_port: endpoint { - remote-endpoint = <&funnel0_in_port0>; - }; - }; - }; - }; - - ptm@0,e3c7d000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0 0xe3c7d000 0 0x1000>; - - clocks = <&clk_375m>; - clock-names = "apb_pclk"; - cpu = <&CPU1>; - out-ports { - port { - ptm1_out_port: endpoint { - remote-endpoint = <&funnel0_in_port1>; - }; - }; - }; - }; - - ptm@0,e3c7e000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0 0xe3c7e000 0 0x1000>; - - clocks = <&clk_375m>; - clock-names = "apb_pclk"; - cpu = <&CPU2>; - out-ports { - port { - ptm2_out_port: endpoint { - remote-endpoint = <&funnel0_in_port2>; - }; - }; - }; - }; - - ptm@0,e3c7f000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0 0xe3c7f000 0 0x1000>; - - clocks = <&clk_375m>; - clock-names = "apb_pclk"; - cpu = <&CPU3>; - out-ports { - port { - ptm3_out_port: endpoint { - remote-endpoint = <&funnel0_in_port3>; - }; - }; - }; - }; - - ptm@0,e3cbc000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0 0xe3cbc000 0 0x1000>; - - clocks = <&clk_375m>; - clock-names = "apb_pclk"; - cpu = <&CPU4>; - out-ports { - port { - ptm4_out_port: endpoint { - remote-endpoint = <&funnel1_in_port0>; - }; - }; - }; - }; - - ptm@0,e3cbd000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0 0xe3cbd000 0 0x1000>; - - clocks = <&clk_375m>; - clock-names = "apb_pclk"; - cpu = <&CPU5>; - out-ports { - port { - ptm5_out_port: endpoint { - remote-endpoint = <&funnel1_in_port1>; - }; - }; - }; - }; - - ptm@0,e3cbe000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0 0xe3cbe000 0 0x1000>; - - clocks = <&clk_375m>; - clock-names = "apb_pclk"; - cpu = <&CPU6>; - out-ports { - port { - ptm6_out_port: endpoint { - remote-endpoint = <&funnel1_in_port2>; - }; - }; - }; - }; - - ptm@0,e3cbf000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0 0xe3cbf000 0 0x1000>; - - clocks = <&clk_375m>; - clock-names = "apb_pclk"; - cpu = <&CPU7>; - out-ports { - port { - ptm7_out_port: endpoint { - remote-endpoint = <&funnel1_in_port3>; - }; - }; - }; - }; - - ptm@0,e3cfc000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0 0xe3cfc000 0 0x1000>; - - clocks = <&clk_375m>; - clock-names = "apb_pclk"; - cpu = <&CPU8>; - out-ports { - port { - ptm8_out_port: endpoint { - remote-endpoint = <&funnel2_in_port0>; - }; - }; - }; - }; - - ptm@0,e3cfd000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0 0xe3cfd000 0 0x1000>; - clocks = <&clk_375m>; - clock-names = "apb_pclk"; - cpu = <&CPU9>; - out-ports { - port { - ptm9_out_port: endpoint { - remote-endpoint = <&funnel2_in_port1>; - }; - }; - }; - }; - - ptm@0,e3cfe000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0 0xe3cfe000 0 0x1000>; - - clocks = <&clk_375m>; - clock-names = "apb_pclk"; - cpu = <&CPU10>; - out-ports { - port { - ptm10_out_port: endpoint { - remote-endpoint = <&funnel2_in_port2>; - }; - }; - }; - }; - - ptm@0,e3cff000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0 0xe3cff000 0 0x1000>; - - clocks = <&clk_375m>; - clock-names = "apb_pclk"; - cpu = <&CPU11>; - out-ports { - port { - ptm11_out_port: endpoint { - remote-endpoint = <&funnel2_in_port3>; - }; - }; - }; - }; - - ptm@0,e3d3c000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0 0xe3d3c000 0 0x1000>; - - clocks = <&clk_375m>; - clock-names = "apb_pclk"; - cpu = <&CPU12>; - out-ports { - port { - ptm12_out_port: endpoint { - remote-endpoint = <&funnel3_in_port0>; - }; - }; - }; - }; - - ptm@0,e3d3d000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0 0xe3d3d000 0 0x1000>; - - clocks = <&clk_375m>; - clock-names = "apb_pclk"; - cpu = <&CPU13>; - out-ports { - port { - ptm13_out_port: endpoint { - remote-endpoint = <&funnel3_in_port1>; - }; - }; - }; - }; - - ptm@0,e3d3e000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0 0xe3d3e000 0 0x1000>; - - clocks = <&clk_375m>; - clock-names = "apb_pclk"; - cpu = <&CPU14>; - out-ports { - port { - ptm14_out_port: endpoint { - remote-endpoint = <&funnel3_in_port2>; - }; - }; - }; - }; - - ptm@0,e3d3f000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0 0xe3d3f000 0 0x1000>; - - clocks = <&clk_375m>; - clock-names = "apb_pclk"; - cpu = <&CPU15>; - out-ports { - port { - ptm15_out_port: endpoint { - remote-endpoint = <&funnel3_in_port3>; - }; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/hisi-x5hd2-dkb.dts b/sys/gnu/dts/arm/hisi-x5hd2-dkb.dts deleted file mode 100644 index d55e9cd3b12..00000000000 --- a/sys/gnu/dts/arm/hisi-x5hd2-dkb.dts +++ /dev/null @@ -1,83 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2013-2014 Linaro Ltd. - * Copyright (c) 2013-2014 Hisilicon Limited. - */ - -/dts-v1/; -#include "hisi-x5hd2.dtsi" - -/ { - model = "Hisilicon HIX5HD2 Development Board"; - compatible = "hisilicon,hix5hd2"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "hisilicon,hix5hd2-smp"; - - cpu@0 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - reg = <0>; - next-level-cache = <&l2>; - }; - - cpu@1 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - reg = <1>; - next-level-cache = <&l2>; - }; - }; - - memory { - device_type = "memory"; - reg = <0x00000000 0x80000000>; - }; -}; - -&timer0 { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&gmac0 { - #address-cells = <1>; - #size-cells = <0>; - phy-handle = <&phy2>; - phy-mode = "mii"; - /* Placeholder, overwritten by bootloader */ - mac-address = [00 00 00 00 00 00]; - status = "okay"; - - phy2: ethernet-phy@2 { - reg = <2>; - }; -}; - -&gmac1 { - #address-cells = <1>; - #size-cells = <0>; - phy-handle = <&phy1>; - phy-mode = "rgmii"; - /* Placeholder, overwritten by bootloader */ - mac-address = [00 00 00 00 00 00]; - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&ahci { - phys = <&sata_phy>; - phy-names = "sata-phy"; -}; diff --git a/sys/gnu/dts/arm/hisi-x5hd2.dtsi b/sys/gnu/dts/arm/hisi-x5hd2.dtsi deleted file mode 100644 index 696e6982a68..00000000000 --- a/sys/gnu/dts/arm/hisi-x5hd2.dtsi +++ /dev/null @@ -1,557 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2013-2014 Linaro Ltd. - * Copyright (c) 2013-2014 Hisilicon Limited. - */ - -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - - aliases { - serial0 = &uart0; - }; - - gic: interrupt-controller@f8a01000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - /* gic dist base, gic cpu base */ - reg = <0xf8a01000 0x1000>, <0xf8a00100 0x100>; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&gic>; - ranges = <0 0xf8000000 0x8000000>; - - amba { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges; - - timer0: timer@2000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x00002000 0x1000>; - /* timer00 & timer01 */ - interrupts = <0 24 4>; - clocks = <&clock HIX5HD2_FIXED_24M>; - status = "disabled"; - }; - - timer1: timer@a29000 { - /* - * Only used in NORMAL state, not available ins - * SLOW or DOZE state. - * The rate is fixed in 24MHz. - */ - compatible = "arm,sp804", "arm,primecell"; - reg = <0x00a29000 0x1000>; - /* timer10 & timer11 */ - interrupts = <0 25 4>; - clocks = <&clock HIX5HD2_FIXED_24M>; - status = "disabled"; - }; - - timer2: timer@a2a000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x00a2a000 0x1000>; - /* timer20 & timer21 */ - interrupts = <0 26 4>; - clocks = <&clock HIX5HD2_FIXED_24M>; - status = "disabled"; - }; - - timer3: timer@a2b000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x00a2b000 0x1000>; - /* timer30 & timer31 */ - interrupts = <0 27 4>; - clocks = <&clock HIX5HD2_FIXED_24M>; - status = "disabled"; - }; - - timer4: timer@a81000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x00a81000 0x1000>; - /* timer30 & timer31 */ - interrupts = <0 28 4>; - clocks = <&clock HIX5HD2_FIXED_24M>; - status = "disabled"; - }; - - uart0: uart@b00000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x00b00000 0x1000>; - interrupts = <0 49 4>; - clocks = <&clock HIX5HD2_FIXED_83M>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - uart1: uart@6000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x00006000 0x1000>; - interrupts = <0 50 4>; - clocks = <&clock HIX5HD2_FIXED_83M>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - uart2: uart@b02000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x00b02000 0x1000>; - interrupts = <0 51 4>; - clocks = <&clock HIX5HD2_FIXED_83M>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - uart3: uart@b03000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x00b03000 0x1000>; - interrupts = <0 52 4>; - clocks = <&clock HIX5HD2_FIXED_83M>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - uart4: uart@b04000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0xb04000 0x1000>; - interrupts = <0 53 4>; - clocks = <&clock HIX5HD2_FIXED_83M>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - gpio0: gpio@b20000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0xb20000 0x1000>; - interrupts = <0 108 0x4>; - gpio-controller; - #gpio-cells = <2>; - clocks = <&clock HIX5HD2_FIXED_100M>; - clock-names = "apb_pclk"; - interrupt-controller; - #interrupt-cells = <2>; - status = "disabled"; - }; - - gpio1: gpio@b21000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0xb21000 0x1000>; - interrupts = <0 109 0x4>; - gpio-controller; - #gpio-cells = <2>; - clocks = <&clock HIX5HD2_FIXED_100M>; - clock-names = "apb_pclk"; - interrupt-controller; - #interrupt-cells = <2>; - status = "disabled"; - }; - - gpio2: gpio@b22000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0xb22000 0x1000>; - interrupts = <0 110 0x4>; - gpio-controller; - #gpio-cells = <2>; - clocks = <&clock HIX5HD2_FIXED_100M>; - clock-names = "apb_pclk"; - interrupt-controller; - #interrupt-cells = <2>; - status = "disabled"; - }; - - gpio3: gpio@b23000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0xb23000 0x1000>; - interrupts = <0 111 0x4>; - gpio-controller; - #gpio-cells = <2>; - clocks = <&clock HIX5HD2_FIXED_100M>; - clock-names = "apb_pclk"; - interrupt-controller; - #interrupt-cells = <2>; - status = "disabled"; - }; - - gpio4: gpio@b24000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0xb24000 0x1000>; - interrupts = <0 112 0x4>; - gpio-controller; - #gpio-cells = <2>; - clocks = <&clock HIX5HD2_FIXED_100M>; - clock-names = "apb_pclk"; - interrupt-controller; - #interrupt-cells = <2>; - status = "disabled"; - }; - - gpio5: gpio@4000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x004000 0x1000>; - interrupts = <0 113 0x4>; - gpio-controller; - #gpio-cells = <2>; - clocks = <&clock HIX5HD2_FIXED_100M>; - clock-names = "apb_pclk"; - interrupt-controller; - #interrupt-cells = <2>; - status = "disabled"; - }; - - gpio6: gpio@b26000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0xb26000 0x1000>; - interrupts = <0 114 0x4>; - gpio-controller; - #gpio-cells = <2>; - clocks = <&clock HIX5HD2_FIXED_100M>; - clock-names = "apb_pclk"; - interrupt-controller; - #interrupt-cells = <2>; - status = "disabled"; - }; - - gpio7: gpio@b27000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0xb27000 0x1000>; - interrupts = <0 115 0x4>; - gpio-controller; - #gpio-cells = <2>; - clocks = <&clock HIX5HD2_FIXED_100M>; - clock-names = "apb_pclk"; - interrupt-controller; - #interrupt-cells = <2>; - status = "disabled"; - }; - - gpio8: gpio@b28000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0xb28000 0x1000>; - interrupts = <0 116 0x4>; - gpio-controller; - #gpio-cells = <2>; - clocks = <&clock HIX5HD2_FIXED_100M>; - clock-names = "apb_pclk"; - interrupt-controller; - #interrupt-cells = <2>; - status = "disabled"; - }; - - gpio9: gpio@b29000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0xb29000 0x1000>; - interrupts = <0 117 0x4>; - gpio-controller; - #gpio-cells = <2>; - clocks = <&clock HIX5HD2_FIXED_100M>; - clock-names = "apb_pclk"; - interrupt-controller; - #interrupt-cells = <2>; - status = "disabled"; - }; - - gpio10: gpio@b2a000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0xb2a000 0x1000>; - interrupts = <0 118 0x4>; - gpio-controller; - #gpio-cells = <2>; - clocks = <&clock HIX5HD2_FIXED_100M>; - clock-names = "apb_pclk"; - interrupt-controller; - #interrupt-cells = <2>; - status = "disabled"; - }; - - gpio11: gpio@b2b000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0xb2b000 0x1000>; - interrupts = <0 119 0x4>; - gpio-controller; - #gpio-cells = <2>; - clocks = <&clock HIX5HD2_FIXED_100M>; - clock-names = "apb_pclk"; - interrupt-controller; - #interrupt-cells = <2>; - status = "disabled"; - }; - - gpio12: gpio@b2c000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0xb2c000 0x1000>; - interrupts = <0 120 0x4>; - gpio-controller; - #gpio-cells = <2>; - clocks = <&clock HIX5HD2_FIXED_100M>; - clock-names = "apb_pclk"; - interrupt-controller; - #interrupt-cells = <2>; - status = "disabled"; - }; - - gpio13: gpio@b2d000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0xb2d000 0x1000>; - interrupts = <0 121 0x4>; - gpio-controller; - #gpio-cells = <2>; - clocks = <&clock HIX5HD2_FIXED_100M>; - clock-names = "apb_pclk"; - interrupt-controller; - #interrupt-cells = <2>; - status = "disabled"; - }; - - gpio14: gpio@b2e000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0xb2e000 0x1000>; - interrupts = <0 122 0x4>; - gpio-controller; - #gpio-cells = <2>; - clocks = <&clock HIX5HD2_FIXED_100M>; - clock-names = "apb_pclk"; - interrupt-controller; - #interrupt-cells = <2>; - status = "disabled"; - }; - - gpio15: gpio@b2f000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0xb2f000 0x1000>; - interrupts = <0 123 0x4>; - gpio-controller; - #gpio-cells = <2>; - clocks = <&clock HIX5HD2_FIXED_100M>; - clock-names = "apb_pclk"; - interrupt-controller; - #interrupt-cells = <2>; - status = "disabled"; - }; - - gpio16: gpio@b30000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0xb30000 0x1000>; - interrupts = <0 124 0x4>; - gpio-controller; - #gpio-cells = <2>; - clocks = <&clock HIX5HD2_FIXED_100M>; - clock-names = "apb_pclk"; - interrupt-controller; - #interrupt-cells = <2>; - status = "disabled"; - }; - - gpio17: gpio@b31000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0xb31000 0x1000>; - interrupts = <0 125 0x4>; - gpio-controller; - #gpio-cells = <2>; - clocks = <&clock HIX5HD2_FIXED_100M>; - clock-names = "apb_pclk"; - interrupt-controller; - #interrupt-cells = <2>; - status = "disabled"; - }; - - wdt0: watchdog@a2c000 { - compatible = "arm,sp805", "arm,primecell"; - arm,primecell-periphid = <0x00141805>; - reg = <0xa2c000 0x1000>; - interrupts = <0 29 4>; - clocks = <&clock HIX5HD2_WDG0_RST>; - clock-names = "apb_pclk"; - }; - }; - - local_timer@a00600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0x00a00600 0x20>; - interrupts = <1 13 0xf01>; - }; - - l2: l2-cache { - compatible = "arm,pl310-cache"; - reg = <0x00a10000 0x100000>; - interrupts = <0 15 4>; - cache-unified; - cache-level = <2>; - }; - - sysctrl: system-controller@0 { - compatible = "hisilicon,sysctrl", "syscon"; - reg = <0x00000000 0x1000>; - }; - - reboot { - compatible = "syscon-reboot"; - regmap = <&sysctrl>; - offset = <0x4>; - mask = <0xdeadbeef>; - }; - - cpuctrl@a22000 { - compatible = "hisilicon,cpuctrl"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x00a22000 0x2000>; - ranges = <0 0x00a22000 0x2000>; - - clock: clock@0 { - compatible = "hisilicon,hix5hd2-clock"; - reg = <0 0x2000>; - #clock-cells = <1>; - }; - }; - - /* unremovable emmc as mmcblk0 */ - mmc: mmc@1830000 { - compatible = "snps,dw-mshc"; - reg = <0x1830000 0x1000>; - interrupts = <0 35 4>; - clocks = <&clock HIX5HD2_MMC_CIU_RST>, - <&clock HIX5HD2_MMC_BIU_CLK>; - clock-names = "ciu", "biu"; - }; - - sd: mmc@1820000 { - compatible = "snps,dw-mshc"; - reg = <0x1820000 0x1000>; - interrupts = <0 34 4>; - clocks = <&clock HIX5HD2_SD_CIU_RST>, - <&clock HIX5HD2_SD_BIU_CLK>; - clock-names = "ciu","biu"; - }; - - gmac0: ethernet@1840000 { - compatible = "hisilicon,hix5hd2-gmac", "hisilicon,hisi-gmac-v1"; - reg = <0x1840000 0x1000>,<0x184300c 0x4>; - interrupts = <0 71 4>; - clocks = <&clock HIX5HD2_MAC0_CLK>; - clock-names = "mac_core"; - status = "disabled"; - }; - - gmac1: ethernet@1841000 { - compatible = "hisilicon,hix5hd2-gmac", "hisilicon,hisi-gmac-v1"; - reg = <0x1841000 0x1000>,<0x1843010 0x4>; - interrupts = <0 72 4>; - clocks = <&clock HIX5HD2_MAC1_CLK>; - clock-names = "mac_core"; - status = "disabled"; - }; - - usb0: ehci@1890000 { - compatible = "generic-ehci"; - reg = <0x1890000 0x1000>; - interrupts = <0 66 4>; - clocks = <&clock HIX5HD2_USB_CLK>; - }; - - usb1: ohci@1880000 { - compatible = "generic-ohci"; - reg = <0x1880000 0x1000>; - interrupts = <0 67 4>; - clocks = <&clock HIX5HD2_USB_CLK>; - }; - - peripheral_ctrl: syscon@a20000 { - compatible = "syscon"; - reg = <0xa20000 0x1000>; - }; - - sata_phy: phy@1900000 { - compatible = "hisilicon,hix5hd2-sata-phy"; - reg = <0x1900000 0x10000>; - #phy-cells = <0>; - hisilicon,peripheral-syscon = <&peripheral_ctrl>; - hisilicon,power-reg = <0x8 10>; - }; - - ahci: sata@1900000 { - compatible = "hisilicon,hisi-ahci"; - reg = <0x1900000 0x10000>; - interrupts = <0 70 4>; - clocks = <&clock HIX5HD2_SATA_CLK>; - }; - - ir: ir@1000 { - compatible = "hisilicon,hix5hd2-ir"; - reg = <0x001000 0x1000>; - interrupts = <0 47 4>; - clocks = <&clock HIX5HD2_FIXED_24M>; - hisilicon,power-syscon = <&sysctrl>; - }; - - i2c0: i2c@b10000 { - compatible = "hisilicon,hix5hd2-i2c"; - reg = <0xb10000 0x1000>; - interrupts = <0 38 4>; - clocks = <&clock HIX5HD2_I2C0_RST>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c1: i2c@b11000 { - compatible = "hisilicon,hix5hd2-i2c"; - reg = <0xb11000 0x1000>; - interrupts = <0 39 4>; - clocks = <&clock HIX5HD2_I2C1_RST>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@b12000 { - compatible = "hisilicon,hix5hd2-i2c"; - reg = <0xb12000 0x1000>; - interrupts = <0 40 4>; - clocks = <&clock HIX5HD2_I2C2_RST>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c3: i2c@b13000 { - compatible = "hisilicon,hix5hd2-i2c"; - reg = <0xb13000 0x1000>; - interrupts = <0 41 4>; - clocks = <&clock HIX5HD2_I2C3_RST>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c4: i2c@b16000 { - compatible = "hisilicon,hix5hd2-i2c"; - reg = <0xb16000 0x1000>; - interrupts = <0 43 4>; - clocks = <&clock HIX5HD2_I2C4_RST>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c5: i2c@b17000 { - compatible = "hisilicon,hix5hd2-i2c"; - reg = <0xb17000 0x1000>; - interrupts = <0 44 4>; - clocks = <&clock HIX5HD2_I2C5_RST>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; -}; diff --git a/sys/gnu/dts/arm/ibm-power9-dual.dtsi b/sys/gnu/dts/arm/ibm-power9-dual.dtsi deleted file mode 100644 index a0fa65b44b0..00000000000 --- a/sys/gnu/dts/arm/ibm-power9-dual.dtsi +++ /dev/null @@ -1,248 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// Copyright 2018 IBM Corp - -&fsi { - cfam@0,0 { - reg = <0 0>; - #address-cells = <1>; - #size-cells = <1>; - chip-id = <0>; - - scom@1000 { - compatible = "ibm,fsi2pib"; - reg = <0x1000 0x400>; - }; - - i2c@1800 { - compatible = "ibm,fsi-i2c-master"; - reg = <0x1800 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - cfam0_i2c0: i2c-bus@0 { - reg = <0>; - }; - - cfam0_i2c1: i2c-bus@1 { - reg = <1>; - }; - - cfam0_i2c2: i2c-bus@2 { - reg = <2>; - }; - - cfam0_i2c3: i2c-bus@3 { - reg = <3>; - }; - - cfam0_i2c4: i2c-bus@4 { - reg = <4>; - }; - - cfam0_i2c5: i2c-bus@5 { - reg = <5>; - }; - - cfam0_i2c6: i2c-bus@6 { - reg = <6>; - }; - - cfam0_i2c7: i2c-bus@7 { - reg = <7>; - }; - - cfam0_i2c8: i2c-bus@8 { - reg = <8>; - }; - - cfam0_i2c9: i2c-bus@9 { - reg = <9>; - }; - - cfam0_i2c10: i2c-bus@a { - reg = <10>; - }; - - cfam0_i2c11: i2c-bus@b { - reg = <11>; - }; - - cfam0_i2c12: i2c-bus@c { - reg = <12>; - }; - - cfam0_i2c13: i2c-bus@d { - reg = <13>; - }; - - cfam0_i2c14: i2c-bus@e { - reg = <14>; - }; - }; - - sbefifo@2400 { - compatible = "ibm,p9-sbefifo"; - reg = <0x2400 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - fsi_occ0: occ@1 { - compatible = "ibm,p9-occ"; - }; - }; - - fsi_hub0: hub@3400 { - compatible = "fsi-master-hub"; - reg = <0x3400 0x400>; - #address-cells = <2>; - #size-cells = <0>; - - no-scan-on-init; - }; - }; -}; - -&fsi_hub0 { - cfam@1,0 { - reg = <1 0>; - #address-cells = <1>; - #size-cells = <1>; - chip-id = <1>; - - scom@1000 { - compatible = "ibm,fsi2pib"; - reg = <0x1000 0x400>; - }; - - i2c@1800 { - compatible = "ibm,fsi-i2c-master"; - reg = <0x1800 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - cfam1_i2c0: i2c-bus@0 { - reg = <0>; - }; - - cfam1_i2c1: i2c-bus@1 { - reg = <1>; - }; - - cfam1_i2c2: i2c-bus@2 { - reg = <2>; - }; - - cfam1_i2c3: i2c-bus@3 { - reg = <3>; - }; - - cfam1_i2c4: i2c-bus@4 { - reg = <4>; - }; - - cfam1_i2c5: i2c-bus@5 { - reg = <5>; - }; - - cfam1_i2c6: i2c-bus@6 { - reg = <6>; - }; - - cfam1_i2c7: i2c-bus@7 { - reg = <7>; - }; - - cfam1_i2c8: i2c-bus@8 { - reg = <8>; - }; - - cfam1_i2c9: i2c-bus@9 { - reg = <9>; - }; - - cfam1_i2c10: i2c-bus@a { - reg = <10>; - }; - - cfam1_i2c11: i2c-bus@b { - reg = <11>; - }; - - cfam1_i2c12: i2c-bus@c { - reg = <12>; - }; - - cfam1_i2c13: i2c-bus@d { - reg = <13>; - }; - - cfam1_i2c14: i2c-bus@e { - reg = <14>; - }; - }; - - sbefifo@2400 { - compatible = "ibm,p9-sbefifo"; - reg = <0x2400 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - fsi_occ1: occ@2 { - compatible = "ibm,p9-occ"; - }; - }; - - fsi_hub1: hub@3400 { - compatible = "fsi-master-hub"; - reg = <0x3400 0x400>; - #address-cells = <2>; - #size-cells = <0>; - - no-scan-on-init; - }; - }; -}; - -/* Legacy OCC numbering (to get rid of when userspace is fixed) */ -&fsi_occ0 { - reg = <1>; -}; - -&fsi_occ1 { - reg = <2>; -}; - -/ { - aliases { - i2c100 = &cfam0_i2c0; - i2c101 = &cfam0_i2c1; - i2c102 = &cfam0_i2c2; - i2c103 = &cfam0_i2c3; - i2c104 = &cfam0_i2c4; - i2c105 = &cfam0_i2c5; - i2c106 = &cfam0_i2c6; - i2c107 = &cfam0_i2c7; - i2c108 = &cfam0_i2c8; - i2c109 = &cfam0_i2c9; - i2c110 = &cfam0_i2c10; - i2c111 = &cfam0_i2c11; - i2c112 = &cfam0_i2c12; - i2c113 = &cfam0_i2c13; - i2c114 = &cfam0_i2c14; - i2c200 = &cfam1_i2c0; - i2c201 = &cfam1_i2c1; - i2c202 = &cfam1_i2c2; - i2c203 = &cfam1_i2c3; - i2c204 = &cfam1_i2c4; - i2c205 = &cfam1_i2c5; - i2c206 = &cfam1_i2c6; - i2c207 = &cfam1_i2c7; - i2c208 = &cfam1_i2c8; - i2c209 = &cfam1_i2c9; - i2c210 = &cfam1_i2c10; - i2c211 = &cfam1_i2c11; - i2c212 = &cfam1_i2c12; - i2c213 = &cfam1_i2c13; - i2c214 = &cfam1_i2c14; - }; -}; diff --git a/sys/gnu/dts/arm/imx1-ads.dts b/sys/gnu/dts/arm/imx1-ads.dts deleted file mode 100644 index 5833fb6f15d..00000000000 --- a/sys/gnu/dts/arm/imx1-ads.dts +++ /dev/null @@ -1,135 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (C) 2014 Alexander Shiyan - */ - -/dts-v1/; -#include "imx1.dtsi" - -/ { - model = "Freescale MX1 ADS"; - compatible = "fsl,imx1ads", "fsl,imx1"; - - chosen { - stdout-path = &uart1; - }; - - memory@8000000 { - device_type = "memory"; - reg = <0x08000000 0x04000000>; - }; -}; - -&cspi1 { - pinctrl-0 = <&pinctrl_cspi1>; - cs-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&i2c { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c>; - status = "okay"; - - extgpio0: pcf8575@22 { - compatible = "nxp,pcf8575"; - reg = <0x22>; - gpio-controller; - #gpio-cells = <2>; - }; - - extgpio1: pcf8575@24 { - compatible = "nxp,pcf8575"; - reg = <0x24>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - uart-has-rtscts; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - uart-has-rtscts; - status = "okay"; -}; - -&weim { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_weim>; - status = "okay"; - - nor: nor@0,0 { - compatible = "cfi-flash"; - reg = <0 0x00000000 0x02000000>; - bank-width = <4>; - fsl,weim-cs-timing = <0x00003e00 0x00000801>; - #address-cells = <1>; - #size-cells = <1>; - }; -}; - -&iomuxc { - imx1-ads { - pinctrl_cspi1: cspi1grp { - fsl,pins = < - MX1_PAD_SPI1_MISO__SPI1_MISO 0x0 - MX1_PAD_SPI1_MOSI__SPI1_MOSI 0x0 - MX1_PAD_SPI1_RDY__SPI1_RDY 0x0 - MX1_PAD_SPI1_SCLK__SPI1_SCLK 0x0 - MX1_PAD_SPI1_SS__GPIO3_15 0x0 - >; - }; - - pinctrl_i2c: i2cgrp { - fsl,pins = < - MX1_PAD_I2C_SCL__I2C_SCL 0x0 - MX1_PAD_I2C_SDA__I2C_SDA 0x0 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX1_PAD_UART1_TXD__UART1_TXD 0x0 - MX1_PAD_UART1_RXD__UART1_RXD 0x0 - MX1_PAD_UART1_CTS__UART1_CTS 0x0 - MX1_PAD_UART1_RTS__UART1_RTS 0x0 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX1_PAD_UART2_TXD__UART2_TXD 0x0 - MX1_PAD_UART2_RXD__UART2_RXD 0x0 - MX1_PAD_UART2_CTS__UART2_CTS 0x0 - MX1_PAD_UART2_RTS__UART2_RTS 0x0 - >; - }; - - pinctrl_weim: weimgrp { - fsl,pins = < - MX1_PAD_A0__A0 0x0 - MX1_PAD_A16__A16 0x0 - MX1_PAD_A17__A17 0x0 - MX1_PAD_A18__A18 0x0 - MX1_PAD_A19__A19 0x0 - MX1_PAD_A20__A20 0x0 - MX1_PAD_A21__A21 0x0 - MX1_PAD_A22__A22 0x0 - MX1_PAD_A23__A23 0x0 - MX1_PAD_A24__A24 0x0 - MX1_PAD_BCLK__BCLK 0x0 - MX1_PAD_CS4__CS4 0x0 - MX1_PAD_DTACK__DTACK 0x0 - MX1_PAD_ECB__ECB 0x0 - MX1_PAD_LBA__LBA 0x0 - >; - }; - }; -}; diff --git a/sys/gnu/dts/arm/imx1-apf9328.dts b/sys/gnu/dts/arm/imx1-apf9328.dts deleted file mode 100644 index 77b21aa7a14..00000000000 --- a/sys/gnu/dts/arm/imx1-apf9328.dts +++ /dev/null @@ -1,124 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (C) 2014 Alexander Shiyan - */ - -/dts-v1/; -#include "imx1.dtsi" - -/ { - model = "Armadeus APF9328"; - compatible = "armadeus,imx1-apf9328", "fsl,imx1"; - - chosen { - stdout-path = &uart1; - }; - - memory@8000000 { - device_type = "memory"; - reg = <0x08000000 0x00800000>; - }; -}; - -&i2c { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - uart-has-rtscts; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - uart-has-rtscts; - status = "okay"; -}; - -&weim { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_weim>; - status = "okay"; - - nor: nor@0,0 { - compatible = "cfi-flash"; - reg = <0 0x00000000 0x02000000>; - bank-width = <2>; - fsl,weim-cs-timing = <0x00330e04 0x00000d01>; - #address-cells = <1>; - #size-cells = <1>; - }; - - eth: eth@4,c00000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_eth>; - compatible = "davicom,dm9000"; - reg = < - 4 0x00c00000 0x2 - 4 0x00c00002 0x2 - >; - interrupt-parent = <&gpio2>; - interrupts = <14 IRQ_TYPE_LEVEL_LOW>; - fsl,weim-cs-timing = <0x0000c700 0x19190d01>; - }; -}; - -&iomuxc { - imx1-apf9328 { - pinctrl_eth: ethgrp { - fsl,pins = < - MX1_PAD_SIM_SVEN__GPIO2_14 0x0 - >; - }; - - pinctrl_i2c: i2cgrp { - fsl,pins = < - MX1_PAD_I2C_SCL__I2C_SCL 0x0 - MX1_PAD_I2C_SDA__I2C_SDA 0x0 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX1_PAD_UART1_TXD__UART1_TXD 0x0 - MX1_PAD_UART1_RXD__UART1_RXD 0x0 - MX1_PAD_UART1_CTS__UART1_CTS 0x0 - MX1_PAD_UART1_RTS__UART1_RTS 0x0 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX1_PAD_UART2_TXD__UART2_TXD 0x0 - MX1_PAD_UART2_RXD__UART2_RXD 0x0 - MX1_PAD_UART2_CTS__UART2_CTS 0x0 - MX1_PAD_UART2_RTS__UART2_RTS 0x0 - >; - }; - - pinctrl_weim: weimgrp { - fsl,pins = < - MX1_PAD_A0__A0 0x0 - MX1_PAD_A16__A16 0x0 - MX1_PAD_A17__A17 0x0 - MX1_PAD_A18__A18 0x0 - MX1_PAD_A19__A19 0x0 - MX1_PAD_A20__A20 0x0 - MX1_PAD_A21__A21 0x0 - MX1_PAD_A22__A22 0x0 - MX1_PAD_A23__A23 0x0 - MX1_PAD_A24__A24 0x0 - MX1_PAD_BCLK__BCLK 0x0 - MX1_PAD_CS4__CS4 0x0 - MX1_PAD_DTACK__DTACK 0x0 - MX1_PAD_ECB__ECB 0x0 - MX1_PAD_LBA__LBA 0x0 - >; - }; - }; -}; diff --git a/sys/gnu/dts/arm/imx1-pinfunc.h b/sys/gnu/dts/arm/imx1-pinfunc.h deleted file mode 100644 index 050a1fc46a7..00000000000 --- a/sys/gnu/dts/arm/imx1-pinfunc.h +++ /dev/null @@ -1,296 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright (C) 2014 Alexander Shiyan - */ - -#ifndef __DTS_IMX1_PINFUNC_H -#define __DTS_IMX1_PINFUNC_H - -/* - * The pin function ID is a tuple of - * - * mux_id consists of - * function + (direction << 2) + (gpio_oconf << 4) + (gpio_iconfa << 8) + (gpio_iconfb << 10) - * - * function: 0 - Primary function - * 1 - Alternate function - * 2 - GPIO - * direction: 0 - Input - * 1 - Output - * gpio_oconf: 0 - A_IN - * 1 - B_IN - * 2 - A_OUT - * 3 - Data Register - * gpio_iconfa/b: 0 - GPIO_IN - * 1 - Interrupt Status Register - * 2 - 0 - * 3 - 1 - * - * 'pin' is an integer between 0 and 0xbf. i.MX1 has 4 ports with 32 configurable - * configurable pins each. 'pin' is PORT * 32 + PORT_PIN, PORT_PIN is the pin - * number on the specific port (between 0 and 31). - */ - -#define MX1_PAD_A24__A24 0x00 0x004 -#define MX1_PAD_A24__GPIO1_0 0x00 0x032 -#define MX1_PAD_A24__SPI2_CLK 0x00 0x006 -#define MX1_PAD_TIN__TIN 0x01 0x000 -#define MX1_PAD_TIN__GPIO1_1 0x01 0x032 -#define MX1_PAD_TIN__SPI2_RXD 0x01 0x022 -#define MX1_PAD_PWMO__PWMO 0x02 0x004 -#define MX1_PAD_PWMO__GPIO1_2 0x02 0x032 -#define MX1_PAD_CSI_MCLK__CSI_MCLK 0x03 0x004 -#define MX1_PAD_CSI_MCLK__GPIO1_3 0x03 0x032 -#define MX1_PAD_CSI_D0__CSI_D0 0x04 0x000 -#define MX1_PAD_CSI_D0__GPIO1_4 0x04 0x032 -#define MX1_PAD_CSI_D1__CSI_D1 0x05 0x000 -#define MX1_PAD_CSI_D1__GPIO1_5 0x05 0x032 -#define MX1_PAD_CSI_D2__CSI_D2 0x06 0x000 -#define MX1_PAD_CSI_D2__GPIO1_6 0x06 0x032 -#define MX1_PAD_CSI_D3__CSI_D3 0x07 0x000 -#define MX1_PAD_CSI_D3__GPIO1_7 0x07 0x032 -#define MX1_PAD_CSI_D4__CSI_D4 0x08 0x000 -#define MX1_PAD_CSI_D4__GPIO1_8 0x08 0x032 -#define MX1_PAD_CSI_D5__CSI_D5 0x09 0x000 -#define MX1_PAD_CSI_D5__GPIO1_9 0x09 0x032 -#define MX1_PAD_CSI_D6__CSI_D6 0x0a 0x000 -#define MX1_PAD_CSI_D6__GPIO1_10 0x0a 0x032 -#define MX1_PAD_CSI_D7__CSI_D7 0x0b 0x000 -#define MX1_PAD_CSI_D7__GPIO1_11 0x0b 0x032 -#define MX1_PAD_CSI_VSYNC__CSI_VSYNC 0x0c 0x000 -#define MX1_PAD_CSI_VSYNC__GPIO1_12 0x0c 0x032 -#define MX1_PAD_CSI_HSYNC__CSI_HSYNC 0x0d 0x000 -#define MX1_PAD_CSI_HSYNC__GPIO1_13 0x0d 0x032 -#define MX1_PAD_CSI_PIXCLK__CSI_PIXCLK 0x0e 0x000 -#define MX1_PAD_CSI_PIXCLK__GPIO1_14 0x0e 0x032 -#define MX1_PAD_I2C_SDA__I2C_SDA 0x0f 0x000 -#define MX1_PAD_I2C_SDA__GPIO1_15 0x0f 0x032 -#define MX1_PAD_I2C_SCL__I2C_SCL 0x10 0x004 -#define MX1_PAD_I2C_SCL__GPIO1_16 0x10 0x032 -#define MX1_PAD_DTACK__DTACK 0x11 0x000 -#define MX1_PAD_DTACK__GPIO1_17 0x11 0x032 -#define MX1_PAD_DTACK__SPI2_SS 0x11 0x002 -#define MX1_PAD_DTACK__A25 0x11 0x016 -#define MX1_PAD_BCLK__BCLK 0x12 0x004 -#define MX1_PAD_BCLK__GPIO1_18 0x12 0x032 -#define MX1_PAD_LBA__LBA 0x13 0x004 -#define MX1_PAD_LBA__GPIO1_19 0x13 0x032 -#define MX1_PAD_ECB__ECB 0x14 0x000 -#define MX1_PAD_ECB__GPIO1_20 0x14 0x032 -#define MX1_PAD_A0__A0 0x15 0x004 -#define MX1_PAD_A0__GPIO1_21 0x15 0x032 -#define MX1_PAD_CS4__CS4 0x16 0x004 -#define MX1_PAD_CS4__GPIO1_22 0x16 0x032 -#define MX1_PAD_CS5__CS5 0x17 0x004 -#define MX1_PAD_CS5__GPIO1_23 0x17 0x032 -#define MX1_PAD_A16__A16 0x18 0x004 -#define MX1_PAD_A16__GPIO1_24 0x18 0x032 -#define MX1_PAD_A17__A17 0x19 0x004 -#define MX1_PAD_A17__GPIO1_25 0x19 0x032 -#define MX1_PAD_A18__A18 0x1a 0x004 -#define MX1_PAD_A18__GPIO1_26 0x1a 0x032 -#define MX1_PAD_A19__A19 0x1b 0x004 -#define MX1_PAD_A19__GPIO1_27 0x1b 0x032 -#define MX1_PAD_A20__A20 0x1c 0x004 -#define MX1_PAD_A20__GPIO1_28 0x1c 0x032 -#define MX1_PAD_A21__A21 0x1d 0x004 -#define MX1_PAD_A21__GPIO1_29 0x1d 0x032 -#define MX1_PAD_A22__A22 0x1e 0x004 -#define MX1_PAD_A22__GPIO1_30 0x1e 0x032 -#define MX1_PAD_A23__A23 0x1f 0x004 -#define MX1_PAD_A23__GPIO1_31 0x1f 0x032 -#define MX1_PAD_SD_DAT0__SD_DAT0 0x28 0x000 -#define MX1_PAD_SD_DAT0__MS_PI0 0x28 0x001 -#define MX1_PAD_SD_DAT0__GPIO2_8 0x28 0x032 -#define MX1_PAD_SD_DAT1__SD_DAT1 0x29 0x000 -#define MX1_PAD_SD_DAT1__MS_PI1 0x29 0x001 -#define MX1_PAD_SD_DAT1__GPIO2_9 0x29 0x032 -#define MX1_PAD_SD_DAT2__SD_DAT2 0x2a 0x000 -#define MX1_PAD_SD_DAT2__MS_SCLKI 0x2a 0x001 -#define MX1_PAD_SD_DAT2__GPIO2_10 0x2a 0x032 -#define MX1_PAD_SD_DAT3__SD_DAT3 0x2b 0x000 -#define MX1_PAD_SD_DAT3__MS_SDIO 0x2b 0x001 -#define MX1_PAD_SD_DAT3__GPIO2_11 0x2b 0x032 -#define MX1_PAD_SD_SCLK__SD_SCLK 0x2c 0x004 -#define MX1_PAD_SD_SCLK__MS_SCLKO 0x2c 0x005 -#define MX1_PAD_SD_SCLK__GPIO2_12 0x2c 0x032 -#define MX1_PAD_SD_CMD__SD_CMD 0x2d 0x000 -#define MX1_PAD_SD_CMD__MS_BS 0x2d 0x005 -#define MX1_PAD_SD_CMD__GPIO2_13 0x2d 0x032 -#define MX1_PAD_SIM_SVEN__SIM_SVEN 0x2e 0x004 -#define MX1_PAD_SIM_SVEN__SSI_RXFS 0x2e 0x001 -#define MX1_PAD_SIM_SVEN__GPIO2_14 0x2e 0x032 -#define MX1_PAD_SIM_PD__SIM_PD 0x2f 0x000 -#define MX1_PAD_SIM_PD__SSI_RXCLK 0x2f 0x001 -#define MX1_PAD_SIM_PD__GPIO2_15 0x2f 0x032 -#define MX1_PAD_SIM_TX__SIM_TX 0x30 0x000 -#define MX1_PAD_SIM_TX__SSI_RXDAT 0x30 0x001 -#define MX1_PAD_SIM_TX__GPIO2_16 0x30 0x032 -#define MX1_PAD_SIM_RX__SIM_RX 0x31 0x000 -#define MX1_PAD_SIM_RX__SSI_TXDAT 0x31 0x005 -#define MX1_PAD_SIM_RX__GPIO2_17 0x31 0x032 -#define MX1_PAD_SIM_RST__SIM_RST 0x32 0x004 -#define MX1_PAD_SIM_RST__SSI_TXFS 0x32 0x001 -#define MX1_PAD_SIM_RST__GPIO2_18 0x32 0x032 -#define MX1_PAD_SIM_CLK__SIM_CLK 0x33 0x004 -#define MX1_PAD_SIM_CLK__SSI_TXCLK 0x33 0x001 -#define MX1_PAD_SIM_CLK__GPIO2_19 0x33 0x032 -#define MX1_PAD_USBD_AFE__USBD_AFE 0x34 0x004 -#define MX1_PAD_USBD_AFE__GPIO2_20 0x34 0x032 -#define MX1_PAD_USBD_OE__USBD_OE 0x35 0x004 -#define MX1_PAD_USBD_OE__GPIO2_21 0x35 0x032 -#define MX1_PAD_USBD_RCV__USBD_RCV 0x36 0x000 -#define MX1_PAD_USBD_RCV__GPIO2_22 0x36 0x032 -#define MX1_PAD_USBD_SUSPND__USBD_SUSPND 0x37 0x004 -#define MX1_PAD_USBD_SUSPND__GPIO2_23 0x37 0x032 -#define MX1_PAD_USBD_VP__USBD_VP 0x38 0x000 -#define MX1_PAD_USBD_VP__GPIO2_24 0x38 0x032 -#define MX1_PAD_USBD_VM__USBD_VM 0x39 0x000 -#define MX1_PAD_USBD_VM__GPIO2_25 0x39 0x032 -#define MX1_PAD_USBD_VPO__USBD_VPO 0x3a 0x004 -#define MX1_PAD_USBD_VPO__GPIO2_26 0x3a 0x032 -#define MX1_PAD_USBD_VMO__USBD_VMO 0x3b 0x004 -#define MX1_PAD_USBD_VMO__GPIO2_27 0x3b 0x032 -#define MX1_PAD_UART2_CTS__UART2_CTS 0x3c 0x004 -#define MX1_PAD_UART2_CTS__GPIO2_28 0x3c 0x032 -#define MX1_PAD_UART2_RTS__UART2_RTS 0x3d 0x000 -#define MX1_PAD_UART2_RTS__GPIO2_29 0x3d 0x032 -#define MX1_PAD_UART2_TXD__UART2_TXD 0x3e 0x004 -#define MX1_PAD_UART2_TXD__GPIO2_30 0x3e 0x032 -#define MX1_PAD_UART2_RXD__UART2_RXD 0x3f 0x000 -#define MX1_PAD_UART2_RXD__GPIO2_31 0x3f 0x032 -#define MX1_PAD_SSI_RXFS__SSI_RXFS 0x43 0x000 -#define MX1_PAD_SSI_RXFS__GPIO3_3 0x43 0x032 -#define MX1_PAD_SSI_RXCLK__SSI_RXCLK 0x44 0x000 -#define MX1_PAD_SSI_RXCLK__GPIO3_4 0x44 0x032 -#define MX1_PAD_SSI_RXDAT__SSI_RXDAT 0x45 0x000 -#define MX1_PAD_SSI_RXDAT__GPIO3_5 0x45 0x032 -#define MX1_PAD_SSI_TXDAT__SSI_TXDAT 0x46 0x004 -#define MX1_PAD_SSI_TXDAT__GPIO3_6 0x46 0x032 -#define MX1_PAD_SSI_TXFS__SSI_TXFS 0x47 0x000 -#define MX1_PAD_SSI_TXFS__GPIO3_7 0x47 0x032 -#define MX1_PAD_SSI_TXCLK__SSI_TXCLK 0x48 0x000 -#define MX1_PAD_SSI_TXCLK__GPIO3_8 0x48 0x032 -#define MX1_PAD_UART1_CTS__UART1_CTS 0x49 0x004 -#define MX1_PAD_UART1_CTS__GPIO3_9 0x49 0x032 -#define MX1_PAD_UART1_RTS__UART1_RTS 0x4a 0x000 -#define MX1_PAD_UART1_RTS__GPIO3_10 0x4a 0x032 -#define MX1_PAD_UART1_TXD__UART1_TXD 0x4b 0x004 -#define MX1_PAD_UART1_TXD__GPIO3_11 0x4b 0x032 -#define MX1_PAD_UART1_RXD__UART1_RXD 0x4c 0x000 -#define MX1_PAD_UART1_RXD__GPIO3_12 0x4c 0x032 -#define MX1_PAD_SPI1_RDY__SPI1_RDY 0x4d 0x000 -#define MX1_PAD_SPI1_RDY__GPIO3_13 0x4d 0x032 -#define MX1_PAD_SPI1_SCLK__SPI1_SCLK 0x4e 0x004 -#define MX1_PAD_SPI1_SCLK__GPIO3_14 0x4e 0x032 -#define MX1_PAD_SPI1_SS__SPI1_SS 0x4f 0x000 -#define MX1_PAD_SPI1_SS__GPIO3_15 0x4f 0x032 -#define MX1_PAD_SPI1_MISO__SPI1_MISO 0x50 0x000 -#define MX1_PAD_SPI1_MISO__GPIO3_16 0x50 0x032 -#define MX1_PAD_SPI1_MOSI__SPI1_MOSI 0x51 0x004 -#define MX1_PAD_SPI1_MOSI__GPIO3_17 0x51 0x032 -#define MX1_PAD_BT13__BT13 0x53 0x004 -#define MX1_PAD_BT13__SSI2_RXCLK 0x53 0x001 -#define MX1_PAD_BT13__GPIO3_19 0x53 0x032 -#define MX1_PAD_BT12__BT12 0x54 0x004 -#define MX1_PAD_BT12__SSI2_TXFS 0x54 0x001 -#define MX1_PAD_BT12__GPIO3_20 0x54 0x032 -#define MX1_PAD_BT11__BT11 0x55 0x004 -#define MX1_PAD_BT11__SSI2_TXCLK 0x55 0x001 -#define MX1_PAD_BT11__GPIO3_21 0x55 0x032 -#define MX1_PAD_BT10__BT10 0x56 0x004 -#define MX1_PAD_BT10__SSI2_TX 0x56 0x001 -#define MX1_PAD_BT10__GPIO3_22 0x56 0x032 -#define MX1_PAD_BT9__BT9 0x57 0x004 -#define MX1_PAD_BT9__SSI2_RX 0x57 0x001 -#define MX1_PAD_BT9__GPIO3_23 0x57 0x032 -#define MX1_PAD_BT8__BT8 0x58 0x004 -#define MX1_PAD_BT8__SSI2_RXFS 0x58 0x001 -#define MX1_PAD_BT8__GPIO3_24 0x58 0x032 -#define MX1_PAD_BT8__UART3_RI 0x58 0x016 -#define MX1_PAD_BT7__BT7 0x59 0x004 -#define MX1_PAD_BT7__GPIO3_25 0x59 0x032 -#define MX1_PAD_BT7__UART3_DSR 0x59 0x016 -#define MX1_PAD_BT6__BT6 0x5a 0x004 -#define MX1_PAD_BT6__GPIO3_26 0x5a 0x032 -#define MX1_PAD_BT6__SPI2_SS3 0x5a 0x016 -#define MX1_PAD_BT6__UART3_DTR 0x5a 0x022 -#define MX1_PAD_BT5__BT5 0x5b 0x000 -#define MX1_PAD_BT5__GPIO3_27 0x5b 0x032 -#define MX1_PAD_BT5__UART3_DCD 0x5b 0x016 -#define MX1_PAD_BT4__BT4 0x5c 0x000 -#define MX1_PAD_BT4__GPIO3_28 0x5c 0x032 -#define MX1_PAD_BT4__UART3_CTS 0x5c 0x016 -#define MX1_PAD_BT3__BT3 0x5d 0x000 -#define MX1_PAD_BT3__GPIO3_29 0x5d 0x032 -#define MX1_PAD_BT3__UART3_RTS 0x5d 0x022 -#define MX1_PAD_BT2__BT2 0x5e 0x004 -#define MX1_PAD_BT2__GPIO3_30 0x5e 0x032 -#define MX1_PAD_BT2__UART3_TX 0x5e 0x016 -#define MX1_PAD_BT1__BT1 0x5f 0x000 -#define MX1_PAD_BT1__GPIO3_31 0x5f 0x032 -#define MX1_PAD_BT1__UART3_RX 0x5f 0x022 -#define MX1_PAD_LSCLK__LSCLK 0x66 0x004 -#define MX1_PAD_LSCLK__GPIO4_6 0x66 0x032 -#define MX1_PAD_REV__REV 0x67 0x004 -#define MX1_PAD_REV__UART2_DTR 0x67 0x001 -#define MX1_PAD_REV__GPIO4_7 0x67 0x032 -#define MX1_PAD_REV__SPI2_CLK 0x67 0x006 -#define MX1_PAD_CLS__CLS 0x68 0x004 -#define MX1_PAD_CLS__UART2_DCD 0x68 0x005 -#define MX1_PAD_CLS__GPIO4_8 0x68 0x032 -#define MX1_PAD_CLS__SPI2_SS 0x68 0x002 -#define MX1_PAD_PS__PS 0x69 0x004 -#define MX1_PAD_PS__UART2_RI 0x69 0x005 -#define MX1_PAD_PS__GPIO4_9 0x69 0x032 -#define MX1_PAD_PS__SPI2_RXD 0x69 0x022 -#define MX1_PAD_SPL_SPR__SPL_SPR 0x6a 0x004 -#define MX1_PAD_SPL_SPR__UART2_DSR 0x6a 0x005 -#define MX1_PAD_SPL_SPR__GPIO4_10 0x6a 0x032 -#define MX1_PAD_SPL_SPR__SPI2_TXD 0x6a 0x006 -#define MX1_PAD_CONTRAST__CONTRAST 0x6b 0x004 -#define MX1_PAD_CONTRAST__GPIO4_11 0x6b 0x032 -#define MX1_PAD_CONTRAST__SPI2_SS2 0x6b 0x012 -#define MX1_PAD_ACD_OE__ACD_OE 0x6c 0x004 -#define MX1_PAD_ACD_OE__GPIO4_12 0x6c 0x032 -#define MX1_PAD_LP_HSYNC__LP_HSYNC 0x6d 0x004 -#define MX1_PAD_LP_HSYNC__GPIO4_13 0x6d 0x032 -#define MX1_PAD_FLM_VSYNC__FLM_VSYNC 0x6e 0x004 -#define MX1_PAD_FLM_VSYNC__GPIO4_14 0x6e 0x032 -#define MX1_PAD_LD0__LD0 0x6f 0x004 -#define MX1_PAD_LD0__GPIO4_15 0x6f 0x032 -#define MX1_PAD_LD1__LD1 0x70 0x004 -#define MX1_PAD_LD1__GPIO4_16 0x70 0x032 -#define MX1_PAD_LD2__LD2 0x71 0x004 -#define MX1_PAD_LD2__GPIO4_17 0x71 0x032 -#define MX1_PAD_LD3__LD3 0x72 0x004 -#define MX1_PAD_LD3__GPIO4_18 0x72 0x032 -#define MX1_PAD_LD4__LD4 0x73 0x004 -#define MX1_PAD_LD4__GPIO4_19 0x73 0x032 -#define MX1_PAD_LD5__LD5 0x74 0x004 -#define MX1_PAD_LD5__GPIO4_20 0x74 0x032 -#define MX1_PAD_LD6__LD6 0x75 0x004 -#define MX1_PAD_LD6__GPIO4_21 0x75 0x032 -#define MX1_PAD_LD7__LD7 0x76 0x004 -#define MX1_PAD_LD7__GPIO4_22 0x76 0x032 -#define MX1_PAD_LD8__LD8 0x77 0x004 -#define MX1_PAD_LD8__GPIO4_23 0x77 0x032 -#define MX1_PAD_LD9__LD9 0x78 0x004 -#define MX1_PAD_LD9__GPIO4_24 0x78 0x032 -#define MX1_PAD_LD10__LD10 0x79 0x004 -#define MX1_PAD_LD10__GPIO4_25 0x79 0x032 -#define MX1_PAD_LD11__LD11 0x7a 0x004 -#define MX1_PAD_LD11__GPIO4_26 0x7a 0x032 -#define MX1_PAD_LD12__LD12 0x7b 0x004 -#define MX1_PAD_LD12__GPIO4_27 0x7b 0x032 -#define MX1_PAD_LD13__LD13 0x7c 0x004 -#define MX1_PAD_LD13__GPIO4_28 0x7c 0x032 -#define MX1_PAD_LD14__LD14 0x7d 0x004 -#define MX1_PAD_LD14__GPIO4_29 0x7d 0x032 -#define MX1_PAD_LD15__LD15 0x7e 0x004 -#define MX1_PAD_LD15__GPIO4_30 0x7e 0x032 -#define MX1_PAD_TMR2OUT__TMR2OUT 0x7f 0x000 -#define MX1_PAD_TMR2OUT__GPIO4_31 0x7f 0x032 -#define MX1_PAD_TMR2OUT__SPI2_TXD 0x7f 0x006 - -#endif diff --git a/sys/gnu/dts/arm/imx1.dtsi b/sys/gnu/dts/arm/imx1.dtsi deleted file mode 100644 index b30448cde58..00000000000 --- a/sys/gnu/dts/arm/imx1.dtsi +++ /dev/null @@ -1,276 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// -// Copyright (C) 2014 Alexander Shiyan - -#include "imx1-pinfunc.h" - -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - /* - * The decompressor and also some bootloaders rely on a - * pre-existing /chosen node to be available to insert the - * command line and merge other ATAGS info. - */ - chosen {}; - - aliases { - gpio0 = &gpio1; - gpio1 = &gpio2; - gpio2 = &gpio3; - gpio3 = &gpio4; - i2c0 = &i2c; - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - spi0 = &cspi1; - spi1 = &cspi2; - }; - - aitc: aitc-interrupt-controller@223000 { - compatible = "fsl,imx1-aitc", "fsl,avic"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x00223000 0x1000>; - }; - - cpus { - #size-cells = <0>; - #address-cells = <1>; - - cpu@0 { - device_type = "cpu"; - reg = <0>; - compatible = "arm,arm920t"; - operating-points = <200000 1900000>; - clock-latency = <62500>; - clocks = <&clks IMX1_CLK_MCU>; - voltage-tolerance = <5>; - }; - }; - - clocks { - clk32 { - compatible = "fsl,imx-clk32", "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32000>; - }; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&aitc>; - ranges; - - aipi@200000 { - compatible = "fsl,aipi-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x00200000 0x10000>; - ranges; - - gpt1: timer@202000 { - compatible = "fsl,imx1-gpt"; - reg = <0x00202000 0x1000>; - interrupts = <59>; - clocks = <&clks IMX1_CLK_HCLK>, - <&clks IMX1_CLK_PER1>; - clock-names = "ipg", "per"; - }; - - gpt2: timer@203000 { - compatible = "fsl,imx1-gpt"; - reg = <0x00203000 0x1000>; - interrupts = <58>; - clocks = <&clks IMX1_CLK_HCLK>, - <&clks IMX1_CLK_PER1>; - clock-names = "ipg", "per"; - }; - - fb: fb@205000 { - compatible = "fsl,imx1-fb"; - reg = <0x00205000 0x1000>; - interrupts = <14>; - clocks = <&clks IMX1_CLK_DUMMY>, - <&clks IMX1_CLK_DUMMY>, - <&clks IMX1_CLK_PER2>; - clock-names = "ipg", "ahb", "per"; - status = "disabled"; - }; - - uart1: serial@206000 { - compatible = "fsl,imx1-uart"; - reg = <0x00206000 0x1000>; - interrupts = <30 29 26>; - clocks = <&clks IMX1_CLK_HCLK>, - <&clks IMX1_CLK_PER1>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart2: serial@207000 { - compatible = "fsl,imx1-uart"; - reg = <0x00207000 0x1000>; - interrupts = <24 23 20>; - clocks = <&clks IMX1_CLK_HCLK>, - <&clks IMX1_CLK_PER1>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - pwm: pwm@208000 { - #pwm-cells = <2>; - compatible = "fsl,imx1-pwm"; - reg = <0x00208000 0x1000>; - interrupts = <34>; - clocks = <&clks IMX1_CLK_DUMMY>, - <&clks IMX1_CLK_PER1>; - clock-names = "ipg", "per"; - }; - - dma: dma@209000 { - compatible = "fsl,imx1-dma"; - reg = <0x00209000 0x1000>; - interrupts = <61 60>; - clocks = <&clks IMX1_CLK_HCLK>, - <&clks IMX1_CLK_DMA_GATE>; - clock-names = "ipg", "ahb"; - #dma-cells = <1>; - }; - - uart3: serial@20a000 { - compatible = "fsl,imx1-uart"; - reg = <0x0020a000 0x1000>; - interrupts = <54 4 1>; - clocks = <&clks IMX1_CLK_UART3_GATE>, - <&clks IMX1_CLK_PER1>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - }; - - aipi@210000 { - compatible = "fsl,aipi-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x00210000 0x10000>; - ranges; - - cspi1: spi@213000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx1-cspi"; - reg = <0x00213000 0x1000>; - interrupts = <41>; - clocks = <&clks IMX1_CLK_DUMMY>, - <&clks IMX1_CLK_PER1>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - i2c: i2c@217000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx1-i2c"; - reg = <0x00217000 0x1000>; - interrupts = <39>; - clocks = <&clks IMX1_CLK_HCLK>; - status = "disabled"; - }; - - cspi2: spi@219000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx1-cspi"; - reg = <0x00219000 0x1000>; - interrupts = <40>; - clocks = <&clks IMX1_CLK_DUMMY>, - <&clks IMX1_CLK_PER1>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - clks: ccm@21b000 { - compatible = "fsl,imx1-ccm"; - reg = <0x0021b000 0x1000>; - #clock-cells = <1>; - }; - - iomuxc: iomuxc@21c000 { - compatible = "fsl,imx1-iomuxc"; - reg = <0x0021c000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gpio1: gpio@21c000 { - compatible = "fsl,imx1-gpio"; - reg = <0x0021c000 0x100>; - interrupts = <11>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@21c100 { - compatible = "fsl,imx1-gpio"; - reg = <0x0021c100 0x100>; - interrupts = <12>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio@21c200 { - compatible = "fsl,imx1-gpio"; - reg = <0x0021c200 0x100>; - interrupts = <13>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio4: gpio@21c300 { - compatible = "fsl,imx1-gpio"; - reg = <0x0021c300 0x100>; - interrupts = <62>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - }; - - weim: weim@220000 { - #address-cells = <2>; - #size-cells = <1>; - compatible = "fsl,imx1-weim"; - reg = <0x00220000 0x1000>; - clocks = <&clks IMX1_CLK_DUMMY>; - ranges = < - 0 0 0x10000000 0x02000000 - 1 0 0x12000000 0x01000000 - 2 0 0x13000000 0x01000000 - 3 0 0x14000000 0x01000000 - 4 0 0x15000000 0x01000000 - 5 0 0x16000000 0x01000000 - >; - status = "disabled"; - }; - - esram: esram@300000 { - compatible = "mmio-sram"; - reg = <0x00300000 0x20000>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/imx23-evk.dts b/sys/gnu/dts/arm/imx23-evk.dts deleted file mode 100644 index 0b2701ca292..00000000000 --- a/sys/gnu/dts/arm/imx23-evk.dts +++ /dev/null @@ -1,145 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// -// Copyright 2012 Freescale Semiconductor, Inc. - -/dts-v1/; -#include "imx23.dtsi" - -/ { - model = "Freescale i.MX23 Evaluation Kit"; - compatible = "fsl,imx23-evk", "fsl,imx23"; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x08000000>; - }; - - reg_vddio_sd0: regulator-vddio-sd0 { - compatible = "regulator-fixed"; - regulator-name = "vddio-sd0"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio1 29 0>; - }; - - reg_lcd_3v3: regulator-lcd-3v3 { - compatible = "regulator-fixed"; - regulator-name = "lcd-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio1 18 0>; - enable-active-high; - }; - - reg_lcd_5v: regulator-lcd-5v { - compatible = "regulator-fixed"; - regulator-name = "lcd-5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - panel { - compatible = "sii,43wvf1g"; - backlight = <&backlight_display>; - dvdd-supply = <®_lcd_3v3>; - avdd-supply = <®_lcd_5v>; - - port { - panel_in: endpoint { - remote-endpoint = <&display_out>; - }; - }; - }; - - apb@80000000 { - apbh@80000000 { - gpmi-nand@8000c000 { - pinctrl-names = "default"; - pinctrl-0 = <&gpmi_pins_a &gpmi_pins_fixup>; - status = "okay"; - }; - - ssp0: spi@80010000 { - compatible = "fsl,imx23-mmc"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_pins_fixup>; - bus-width = <4>; - wp-gpios = <&gpio1 30 0>; - vmmc-supply = <®_vddio_sd0>; - status = "okay"; - }; - - pinctrl@80018000 { - pinctrl-names = "default"; - pinctrl-0 = <&hog_pins_a>; - - hog_pins_a: hog@0 { - reg = <0>; - fsl,pinmux-ids = < - MX23_PAD_LCD_RESET__GPIO_1_18 - MX23_PAD_PWM3__GPIO_1_29 - MX23_PAD_PWM4__GPIO_1_30 - MX23_PAD_SSP1_DETECT__SSP1_DETECT - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - }; - - lcdif@80030000 { - pinctrl-names = "default"; - pinctrl-0 = <&lcdif_24bit_pins_a>; - status = "okay"; - - port { - display_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; - }; - - apbx@80040000 { - lradc@80050000 { - status = "okay"; - fsl,lradc-touchscreen-wires = <4>; - }; - - pwm: pwm@80064000 { - pinctrl-names = "default"; - pinctrl-0 = <&pwm2_pins_a>; - status = "okay"; - }; - - auart0: serial@8006c000 { - pinctrl-names = "default"; - pinctrl-0 = <&auart0_pins_a>; - status = "okay"; - }; - - duart: serial@80070000 { - pinctrl-names = "default"; - pinctrl-0 = <&duart_pins_a>; - status = "okay"; - }; - - usbphy0: usbphy@8007c000 { - status = "okay"; - }; - }; - }; - - ahb@80080000 { - usb0: usb@80080000 { - status = "okay"; - }; - }; - - backlight_display: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 2 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - }; -}; diff --git a/sys/gnu/dts/arm/imx23-olinuxino.dts b/sys/gnu/dts/arm/imx23-olinuxino.dts deleted file mode 100644 index 4c9aafe00b5..00000000000 --- a/sys/gnu/dts/arm/imx23-olinuxino.dts +++ /dev/null @@ -1,131 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2012 Freescale Semiconductor, Inc. - * - * Author: Fabio Estevam - */ - -/dts-v1/; -#include -#include "imx23.dtsi" - -/ { - model = "i.MX23 Olinuxino Low Cost Board"; - compatible = "olimex,imx23-olinuxino", "fsl,imx23"; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x04000000>; - }; - - apb@80000000 { - apbh@80000000 { - ssp0: spi@80010000 { - compatible = "fsl,imx23-mmc"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_pins_fixup>; - bus-width = <4>; - broken-cd; - status = "okay"; - }; - - pinctrl@80018000 { - pinctrl-names = "default"; - pinctrl-0 = <&hog_pins_a>; - - hog_pins_a: hog@0 { - reg = <0>; - fsl,pinmux-ids = < - MX23_PAD_GPMI_ALE__GPIO_0_17 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - led_pin_gpio2_1: led_gpio2_1@0 { - reg = <0>; - fsl,pinmux-ids = < - MX23_PAD_SSP1_DETECT__GPIO_2_1 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - }; - - ssp1: spi@80034000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx23-spi"; - pinctrl-names = "default"; - pinctrl-0 = <&spi2_pins_a>; - status = "okay"; - }; - }; - - apbx@80040000 { - lradc@80050000 { - status = "okay"; - }; - - i2c: i2c@80058000 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c_pins_b>; - status = "okay"; - }; - - duart: serial@80070000 { - pinctrl-names = "default"; - pinctrl-0 = <&duart_pins_a>; - status = "okay"; - }; - - auart0: serial@8006c000 { - pinctrl-names = "default"; - pinctrl-0 = <&auart0_2pins_a>; - status = "okay"; - }; - - usbphy0: usbphy@8007c000 { - status = "okay"; - }; - }; - }; - - ahb@80080000 { - usb0: usb@80080000 { - dr_mode = "host"; - vbus-supply = <®_usb0_vbus>; - status = "okay"; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_usb0_vbus: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "usb0_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - startup-delay-us = <300>; /* LAN9215 requires a POR of 200us minimum */ - gpio = <&gpio0 17 0>; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pin_gpio2_1>; - - user { - label = "green"; - gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/imx23-pinfunc.h b/sys/gnu/dts/arm/imx23-pinfunc.h deleted file mode 100644 index 5c0f32ca3a9..00000000000 --- a/sys/gnu/dts/arm/imx23-pinfunc.h +++ /dev/null @@ -1,333 +0,0 @@ -/* - * Header providing constants for i.MX23 pinctrl bindings. - * - * Copyright (C) 2013 Lothar Waßmann - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#ifndef __DT_BINDINGS_MX23_PINCTRL_H__ -#define __DT_BINDINGS_MX23_PINCTRL_H__ - -#include "mxs-pinfunc.h" - -#define MX23_PAD_GPMI_D00__GPMI_D00 0x0000 -#define MX23_PAD_GPMI_D01__GPMI_D01 0x0010 -#define MX23_PAD_GPMI_D02__GPMI_D02 0x0020 -#define MX23_PAD_GPMI_D03__GPMI_D03 0x0030 -#define MX23_PAD_GPMI_D04__GPMI_D04 0x0040 -#define MX23_PAD_GPMI_D05__GPMI_D05 0x0050 -#define MX23_PAD_GPMI_D06__GPMI_D06 0x0060 -#define MX23_PAD_GPMI_D07__GPMI_D07 0x0070 -#define MX23_PAD_GPMI_D08__GPMI_D08 0x0080 -#define MX23_PAD_GPMI_D09__GPMI_D09 0x0090 -#define MX23_PAD_GPMI_D10__GPMI_D10 0x00a0 -#define MX23_PAD_GPMI_D11__GPMI_D11 0x00b0 -#define MX23_PAD_GPMI_D12__GPMI_D12 0x00c0 -#define MX23_PAD_GPMI_D13__GPMI_D13 0x00d0 -#define MX23_PAD_GPMI_D14__GPMI_D14 0x00e0 -#define MX23_PAD_GPMI_D15__GPMI_D15 0x00f0 -#define MX23_PAD_GPMI_CLE__GPMI_CLE 0x0100 -#define MX23_PAD_GPMI_ALE__GPMI_ALE 0x0110 -#define MX23_PAD_GPMI_CE2N__GPMI_CE2N 0x0120 -#define MX23_PAD_GPMI_RDY0__GPMI_RDY0 0x0130 -#define MX23_PAD_GPMI_RDY1__GPMI_RDY1 0x0140 -#define MX23_PAD_GPMI_RDY2__GPMI_RDY2 0x0150 -#define MX23_PAD_GPMI_RDY3__GPMI_RDY3 0x0160 -#define MX23_PAD_GPMI_WPN__GPMI_WPN 0x0170 -#define MX23_PAD_GPMI_WRN__GPMI_WRN 0x0180 -#define MX23_PAD_GPMI_RDN__GPMI_RDN 0x0190 -#define MX23_PAD_AUART1_CTS__AUART1_CTS 0x01a0 -#define MX23_PAD_AUART1_RTS__AUART1_RTS 0x01b0 -#define MX23_PAD_AUART1_RX__AUART1_RX 0x01c0 -#define MX23_PAD_AUART1_TX__AUART1_TX 0x01d0 -#define MX23_PAD_I2C_SCL__I2C_SCL 0x01e0 -#define MX23_PAD_I2C_SDA__I2C_SDA 0x01f0 -#define MX23_PAD_LCD_D00__LCD_D00 0x1000 -#define MX23_PAD_LCD_D01__LCD_D01 0x1010 -#define MX23_PAD_LCD_D02__LCD_D02 0x1020 -#define MX23_PAD_LCD_D03__LCD_D03 0x1030 -#define MX23_PAD_LCD_D04__LCD_D04 0x1040 -#define MX23_PAD_LCD_D05__LCD_D05 0x1050 -#define MX23_PAD_LCD_D06__LCD_D06 0x1060 -#define MX23_PAD_LCD_D07__LCD_D07 0x1070 -#define MX23_PAD_LCD_D08__LCD_D08 0x1080 -#define MX23_PAD_LCD_D09__LCD_D09 0x1090 -#define MX23_PAD_LCD_D10__LCD_D10 0x10a0 -#define MX23_PAD_LCD_D11__LCD_D11 0x10b0 -#define MX23_PAD_LCD_D12__LCD_D12 0x10c0 -#define MX23_PAD_LCD_D13__LCD_D13 0x10d0 -#define MX23_PAD_LCD_D14__LCD_D14 0x10e0 -#define MX23_PAD_LCD_D15__LCD_D15 0x10f0 -#define MX23_PAD_LCD_D16__LCD_D16 0x1100 -#define MX23_PAD_LCD_D17__LCD_D17 0x1110 -#define MX23_PAD_LCD_RESET__LCD_RESET 0x1120 -#define MX23_PAD_LCD_RS__LCD_RS 0x1130 -#define MX23_PAD_LCD_WR__LCD_WR 0x1140 -#define MX23_PAD_LCD_CS__LCD_CS 0x1150 -#define MX23_PAD_LCD_DOTCK__LCD_DOTCK 0x1160 -#define MX23_PAD_LCD_ENABLE__LCD_ENABLE 0x1170 -#define MX23_PAD_LCD_HSYNC__LCD_HSYNC 0x1180 -#define MX23_PAD_LCD_VSYNC__LCD_VSYNC 0x1190 -#define MX23_PAD_PWM0__PWM0 0x11a0 -#define MX23_PAD_PWM1__PWM1 0x11b0 -#define MX23_PAD_PWM2__PWM2 0x11c0 -#define MX23_PAD_PWM3__PWM3 0x11d0 -#define MX23_PAD_PWM4__PWM4 0x11e0 -#define MX23_PAD_SSP1_CMD__SSP1_CMD 0x2000 -#define MX23_PAD_SSP1_DETECT__SSP1_DETECT 0x2010 -#define MX23_PAD_SSP1_DATA0__SSP1_DATA0 0x2020 -#define MX23_PAD_SSP1_DATA1__SSP1_DATA1 0x2030 -#define MX23_PAD_SSP1_DATA2__SSP1_DATA2 0x2040 -#define MX23_PAD_SSP1_DATA3__SSP1_DATA3 0x2050 -#define MX23_PAD_SSP1_SCK__SSP1_SCK 0x2060 -#define MX23_PAD_ROTARYA__ROTARYA 0x2070 -#define MX23_PAD_ROTARYB__ROTARYB 0x2080 -#define MX23_PAD_EMI_A00__EMI_A00 0x2090 -#define MX23_PAD_EMI_A01__EMI_A01 0x20a0 -#define MX23_PAD_EMI_A02__EMI_A02 0x20b0 -#define MX23_PAD_EMI_A03__EMI_A03 0x20c0 -#define MX23_PAD_EMI_A04__EMI_A04 0x20d0 -#define MX23_PAD_EMI_A05__EMI_A05 0x20e0 -#define MX23_PAD_EMI_A06__EMI_A06 0x20f0 -#define MX23_PAD_EMI_A07__EMI_A07 0x2100 -#define MX23_PAD_EMI_A08__EMI_A08 0x2110 -#define MX23_PAD_EMI_A09__EMI_A09 0x2120 -#define MX23_PAD_EMI_A10__EMI_A10 0x2130 -#define MX23_PAD_EMI_A11__EMI_A11 0x2140 -#define MX23_PAD_EMI_A12__EMI_A12 0x2150 -#define MX23_PAD_EMI_BA0__EMI_BA0 0x2160 -#define MX23_PAD_EMI_BA1__EMI_BA1 0x2170 -#define MX23_PAD_EMI_CASN__EMI_CASN 0x2180 -#define MX23_PAD_EMI_CE0N__EMI_CE0N 0x2190 -#define MX23_PAD_EMI_CE1N__EMI_CE1N 0x21a0 -#define MX23_PAD_GPMI_CE1N__GPMI_CE1N 0x21b0 -#define MX23_PAD_GPMI_CE0N__GPMI_CE0N 0x21c0 -#define MX23_PAD_EMI_CKE__EMI_CKE 0x21d0 -#define MX23_PAD_EMI_RASN__EMI_RASN 0x21e0 -#define MX23_PAD_EMI_WEN__EMI_WEN 0x21f0 -#define MX23_PAD_EMI_D00__EMI_D00 0x3000 -#define MX23_PAD_EMI_D01__EMI_D01 0x3010 -#define MX23_PAD_EMI_D02__EMI_D02 0x3020 -#define MX23_PAD_EMI_D03__EMI_D03 0x3030 -#define MX23_PAD_EMI_D04__EMI_D04 0x3040 -#define MX23_PAD_EMI_D05__EMI_D05 0x3050 -#define MX23_PAD_EMI_D06__EMI_D06 0x3060 -#define MX23_PAD_EMI_D07__EMI_D07 0x3070 -#define MX23_PAD_EMI_D08__EMI_D08 0x3080 -#define MX23_PAD_EMI_D09__EMI_D09 0x3090 -#define MX23_PAD_EMI_D10__EMI_D10 0x30a0 -#define MX23_PAD_EMI_D11__EMI_D11 0x30b0 -#define MX23_PAD_EMI_D12__EMI_D12 0x30c0 -#define MX23_PAD_EMI_D13__EMI_D13 0x30d0 -#define MX23_PAD_EMI_D14__EMI_D14 0x30e0 -#define MX23_PAD_EMI_D15__EMI_D15 0x30f0 -#define MX23_PAD_EMI_DQM0__EMI_DQM0 0x3100 -#define MX23_PAD_EMI_DQM1__EMI_DQM1 0x3110 -#define MX23_PAD_EMI_DQS0__EMI_DQS0 0x3120 -#define MX23_PAD_EMI_DQS1__EMI_DQS1 0x3130 -#define MX23_PAD_EMI_CLK__EMI_CLK 0x3140 -#define MX23_PAD_EMI_CLKN__EMI_CLKN 0x3150 -#define MX23_PAD_GPMI_D00__LCD_D8 0x0001 -#define MX23_PAD_GPMI_D01__LCD_D9 0x0011 -#define MX23_PAD_GPMI_D02__LCD_D10 0x0021 -#define MX23_PAD_GPMI_D03__LCD_D11 0x0031 -#define MX23_PAD_GPMI_D04__LCD_D12 0x0041 -#define MX23_PAD_GPMI_D05__LCD_D13 0x0051 -#define MX23_PAD_GPMI_D06__LCD_D14 0x0061 -#define MX23_PAD_GPMI_D07__LCD_D15 0x0071 -#define MX23_PAD_GPMI_D08__LCD_D18 0x0081 -#define MX23_PAD_GPMI_D09__LCD_D19 0x0091 -#define MX23_PAD_GPMI_D10__LCD_D20 0x00a1 -#define MX23_PAD_GPMI_D11__LCD_D21 0x00b1 -#define MX23_PAD_GPMI_D12__LCD_D22 0x00c1 -#define MX23_PAD_GPMI_D13__LCD_D23 0x00d1 -#define MX23_PAD_GPMI_D14__AUART2_RX 0x00e1 -#define MX23_PAD_GPMI_D15__AUART2_TX 0x00f1 -#define MX23_PAD_GPMI_CLE__LCD_D16 0x0101 -#define MX23_PAD_GPMI_ALE__LCD_D17 0x0111 -#define MX23_PAD_GPMI_CE2N__ATA_A2 0x0121 -#define MX23_PAD_AUART1_RTS__IR_CLK 0x01b1 -#define MX23_PAD_AUART1_RX__IR_RX 0x01c1 -#define MX23_PAD_AUART1_TX__IR_TX 0x01d1 -#define MX23_PAD_I2C_SCL__GPMI_RDY2 0x01e1 -#define MX23_PAD_I2C_SDA__GPMI_CE2N 0x01f1 -#define MX23_PAD_LCD_D00__ETM_DA8 0x1001 -#define MX23_PAD_LCD_D01__ETM_DA9 0x1011 -#define MX23_PAD_LCD_D02__ETM_DA10 0x1021 -#define MX23_PAD_LCD_D03__ETM_DA11 0x1031 -#define MX23_PAD_LCD_D04__ETM_DA12 0x1041 -#define MX23_PAD_LCD_D05__ETM_DA13 0x1051 -#define MX23_PAD_LCD_D06__ETM_DA14 0x1061 -#define MX23_PAD_LCD_D07__ETM_DA15 0x1071 -#define MX23_PAD_LCD_D08__ETM_DA0 0x1081 -#define MX23_PAD_LCD_D09__ETM_DA1 0x1091 -#define MX23_PAD_LCD_D10__ETM_DA2 0x10a1 -#define MX23_PAD_LCD_D11__ETM_DA3 0x10b1 -#define MX23_PAD_LCD_D12__ETM_DA4 0x10c1 -#define MX23_PAD_LCD_D13__ETM_DA5 0x10d1 -#define MX23_PAD_LCD_D14__ETM_DA6 0x10e1 -#define MX23_PAD_LCD_D15__ETM_DA7 0x10f1 -#define MX23_PAD_LCD_RESET__ETM_TCTL 0x1121 -#define MX23_PAD_LCD_RS__ETM_TCLK 0x1131 -#define MX23_PAD_LCD_DOTCK__GPMI_RDY3 0x1161 -#define MX23_PAD_LCD_ENABLE__I2C_SCL 0x1171 -#define MX23_PAD_LCD_HSYNC__I2C_SDA 0x1181 -#define MX23_PAD_LCD_VSYNC__LCD_BUSY 0x1191 -#define MX23_PAD_PWM0__ROTARYA 0x11a1 -#define MX23_PAD_PWM1__ROTARYB 0x11b1 -#define MX23_PAD_PWM2__GPMI_RDY3 0x11c1 -#define MX23_PAD_PWM3__ETM_TCTL 0x11d1 -#define MX23_PAD_PWM4__ETM_TCLK 0x11e1 -#define MX23_PAD_SSP1_DETECT__GPMI_CE3N 0x2011 -#define MX23_PAD_SSP1_DATA1__I2C_SCL 0x2031 -#define MX23_PAD_SSP1_DATA2__I2C_SDA 0x2041 -#define MX23_PAD_ROTARYA__AUART2_RTS 0x2071 -#define MX23_PAD_ROTARYB__AUART2_CTS 0x2081 -#define MX23_PAD_GPMI_D00__SSP2_DATA0 0x0002 -#define MX23_PAD_GPMI_D01__SSP2_DATA1 0x0012 -#define MX23_PAD_GPMI_D02__SSP2_DATA2 0x0022 -#define MX23_PAD_GPMI_D03__SSP2_DATA3 0x0032 -#define MX23_PAD_GPMI_D04__SSP2_DATA4 0x0042 -#define MX23_PAD_GPMI_D05__SSP2_DATA5 0x0052 -#define MX23_PAD_GPMI_D06__SSP2_DATA6 0x0062 -#define MX23_PAD_GPMI_D07__SSP2_DATA7 0x0072 -#define MX23_PAD_GPMI_D08__SSP1_DATA4 0x0082 -#define MX23_PAD_GPMI_D09__SSP1_DATA5 0x0092 -#define MX23_PAD_GPMI_D10__SSP1_DATA6 0x00a2 -#define MX23_PAD_GPMI_D11__SSP1_DATA7 0x00b2 -#define MX23_PAD_GPMI_D15__GPMI_CE3N 0x00f2 -#define MX23_PAD_GPMI_RDY0__SSP2_DETECT 0x0132 -#define MX23_PAD_GPMI_RDY1__SSP2_CMD 0x0142 -#define MX23_PAD_GPMI_WRN__SSP2_SCK 0x0182 -#define MX23_PAD_AUART1_CTS__SSP1_DATA4 0x01a2 -#define MX23_PAD_AUART1_RTS__SSP1_DATA5 0x01b2 -#define MX23_PAD_AUART1_RX__SSP1_DATA6 0x01c2 -#define MX23_PAD_AUART1_TX__SSP1_DATA7 0x01d2 -#define MX23_PAD_I2C_SCL__AUART1_TX 0x01e2 -#define MX23_PAD_I2C_SDA__AUART1_RX 0x01f2 -#define MX23_PAD_LCD_D08__SAIF2_SDATA0 0x1082 -#define MX23_PAD_LCD_D09__SAIF1_SDATA0 0x1092 -#define MX23_PAD_LCD_D10__SAIF_MCLK_BITCLK 0x10a2 -#define MX23_PAD_LCD_D11__SAIF_LRCLK 0x10b2 -#define MX23_PAD_LCD_D12__SAIF2_SDATA1 0x10c2 -#define MX23_PAD_LCD_D13__SAIF2_SDATA2 0x10d2 -#define MX23_PAD_LCD_D14__SAIF1_SDATA2 0x10e2 -#define MX23_PAD_LCD_D15__SAIF1_SDATA1 0x10f2 -#define MX23_PAD_LCD_D16__SAIF_ALT_BITCLK 0x1102 -#define MX23_PAD_LCD_RESET__GPMI_CE3N 0x1122 -#define MX23_PAD_PWM0__DUART_RX 0x11a2 -#define MX23_PAD_PWM1__DUART_TX 0x11b2 -#define MX23_PAD_PWM3__AUART1_CTS 0x11d2 -#define MX23_PAD_PWM4__AUART1_RTS 0x11e2 -#define MX23_PAD_SSP1_CMD__JTAG_TDO 0x2002 -#define MX23_PAD_SSP1_DETECT__USB_OTG_ID 0x2012 -#define MX23_PAD_SSP1_DATA0__JTAG_TDI 0x2022 -#define MX23_PAD_SSP1_DATA1__JTAG_TCLK 0x2032 -#define MX23_PAD_SSP1_DATA2__JTAG_RTCK 0x2042 -#define MX23_PAD_SSP1_DATA3__JTAG_TMS 0x2052 -#define MX23_PAD_SSP1_SCK__JTAG_TRST 0x2062 -#define MX23_PAD_ROTARYA__SPDIF 0x2072 -#define MX23_PAD_ROTARYB__GPMI_CE3N 0x2082 -#define MX23_PAD_GPMI_D00__GPIO_0_0 0x0003 -#define MX23_PAD_GPMI_D01__GPIO_0_1 0x0013 -#define MX23_PAD_GPMI_D02__GPIO_0_2 0x0023 -#define MX23_PAD_GPMI_D03__GPIO_0_3 0x0033 -#define MX23_PAD_GPMI_D04__GPIO_0_4 0x0043 -#define MX23_PAD_GPMI_D05__GPIO_0_5 0x0053 -#define MX23_PAD_GPMI_D06__GPIO_0_6 0x0063 -#define MX23_PAD_GPMI_D07__GPIO_0_7 0x0073 -#define MX23_PAD_GPMI_D08__GPIO_0_8 0x0083 -#define MX23_PAD_GPMI_D09__GPIO_0_9 0x0093 -#define MX23_PAD_GPMI_D10__GPIO_0_10 0x00a3 -#define MX23_PAD_GPMI_D11__GPIO_0_11 0x00b3 -#define MX23_PAD_GPMI_D12__GPIO_0_12 0x00c3 -#define MX23_PAD_GPMI_D13__GPIO_0_13 0x00d3 -#define MX23_PAD_GPMI_D14__GPIO_0_14 0x00e3 -#define MX23_PAD_GPMI_D15__GPIO_0_15 0x00f3 -#define MX23_PAD_GPMI_CLE__GPIO_0_16 0x0103 -#define MX23_PAD_GPMI_ALE__GPIO_0_17 0x0113 -#define MX23_PAD_GPMI_CE2N__GPIO_0_18 0x0123 -#define MX23_PAD_GPMI_RDY0__GPIO_0_19 0x0133 -#define MX23_PAD_GPMI_RDY1__GPIO_0_20 0x0143 -#define MX23_PAD_GPMI_RDY2__GPIO_0_21 0x0153 -#define MX23_PAD_GPMI_RDY3__GPIO_0_22 0x0163 -#define MX23_PAD_GPMI_WPN__GPIO_0_23 0x0173 -#define MX23_PAD_GPMI_WRN__GPIO_0_24 0x0183 -#define MX23_PAD_GPMI_RDN__GPIO_0_25 0x0193 -#define MX23_PAD_AUART1_CTS__GPIO_0_26 0x01a3 -#define MX23_PAD_AUART1_RTS__GPIO_0_27 0x01b3 -#define MX23_PAD_AUART1_RX__GPIO_0_28 0x01c3 -#define MX23_PAD_AUART1_TX__GPIO_0_29 0x01d3 -#define MX23_PAD_I2C_SCL__GPIO_0_30 0x01e3 -#define MX23_PAD_I2C_SDA__GPIO_0_31 0x01f3 -#define MX23_PAD_LCD_D00__GPIO_1_0 0x1003 -#define MX23_PAD_LCD_D01__GPIO_1_1 0x1013 -#define MX23_PAD_LCD_D02__GPIO_1_2 0x1023 -#define MX23_PAD_LCD_D03__GPIO_1_3 0x1033 -#define MX23_PAD_LCD_D04__GPIO_1_4 0x1043 -#define MX23_PAD_LCD_D05__GPIO_1_5 0x1053 -#define MX23_PAD_LCD_D06__GPIO_1_6 0x1063 -#define MX23_PAD_LCD_D07__GPIO_1_7 0x1073 -#define MX23_PAD_LCD_D08__GPIO_1_8 0x1083 -#define MX23_PAD_LCD_D09__GPIO_1_9 0x1093 -#define MX23_PAD_LCD_D10__GPIO_1_10 0x10a3 -#define MX23_PAD_LCD_D11__GPIO_1_11 0x10b3 -#define MX23_PAD_LCD_D12__GPIO_1_12 0x10c3 -#define MX23_PAD_LCD_D13__GPIO_1_13 0x10d3 -#define MX23_PAD_LCD_D14__GPIO_1_14 0x10e3 -#define MX23_PAD_LCD_D15__GPIO_1_15 0x10f3 -#define MX23_PAD_LCD_D16__GPIO_1_16 0x1103 -#define MX23_PAD_LCD_D17__GPIO_1_17 0x1113 -#define MX23_PAD_LCD_RESET__GPIO_1_18 0x1123 -#define MX23_PAD_LCD_RS__GPIO_1_19 0x1133 -#define MX23_PAD_LCD_WR__GPIO_1_20 0x1143 -#define MX23_PAD_LCD_CS__GPIO_1_21 0x1153 -#define MX23_PAD_LCD_DOTCK__GPIO_1_22 0x1163 -#define MX23_PAD_LCD_ENABLE__GPIO_1_23 0x1173 -#define MX23_PAD_LCD_HSYNC__GPIO_1_24 0x1183 -#define MX23_PAD_LCD_VSYNC__GPIO_1_25 0x1193 -#define MX23_PAD_PWM0__GPIO_1_26 0x11a3 -#define MX23_PAD_PWM1__GPIO_1_27 0x11b3 -#define MX23_PAD_PWM2__GPIO_1_28 0x11c3 -#define MX23_PAD_PWM3__GPIO_1_29 0x11d3 -#define MX23_PAD_PWM4__GPIO_1_30 0x11e3 -#define MX23_PAD_SSP1_CMD__GPIO_2_0 0x2003 -#define MX23_PAD_SSP1_DETECT__GPIO_2_1 0x2013 -#define MX23_PAD_SSP1_DATA0__GPIO_2_2 0x2023 -#define MX23_PAD_SSP1_DATA1__GPIO_2_3 0x2033 -#define MX23_PAD_SSP1_DATA2__GPIO_2_4 0x2043 -#define MX23_PAD_SSP1_DATA3__GPIO_2_5 0x2053 -#define MX23_PAD_SSP1_SCK__GPIO_2_6 0x2063 -#define MX23_PAD_ROTARYA__GPIO_2_7 0x2073 -#define MX23_PAD_ROTARYB__GPIO_2_8 0x2083 -#define MX23_PAD_EMI_A00__GPIO_2_9 0x2093 -#define MX23_PAD_EMI_A01__GPIO_2_10 0x20a3 -#define MX23_PAD_EMI_A02__GPIO_2_11 0x20b3 -#define MX23_PAD_EMI_A03__GPIO_2_12 0x20c3 -#define MX23_PAD_EMI_A04__GPIO_2_13 0x20d3 -#define MX23_PAD_EMI_A05__GPIO_2_14 0x20e3 -#define MX23_PAD_EMI_A06__GPIO_2_15 0x20f3 -#define MX23_PAD_EMI_A07__GPIO_2_16 0x2103 -#define MX23_PAD_EMI_A08__GPIO_2_17 0x2113 -#define MX23_PAD_EMI_A09__GPIO_2_18 0x2123 -#define MX23_PAD_EMI_A10__GPIO_2_19 0x2133 -#define MX23_PAD_EMI_A11__GPIO_2_20 0x2143 -#define MX23_PAD_EMI_A12__GPIO_2_21 0x2153 -#define MX23_PAD_EMI_BA0__GPIO_2_22 0x2163 -#define MX23_PAD_EMI_BA1__GPIO_2_23 0x2173 -#define MX23_PAD_EMI_CASN__GPIO_2_24 0x2183 -#define MX23_PAD_EMI_CE0N__GPIO_2_25 0x2193 -#define MX23_PAD_EMI_CE1N__GPIO_2_26 0x21a3 -#define MX23_PAD_GPMI_CE1N__GPIO_2_27 0x21b3 -#define MX23_PAD_GPMI_CE0N__GPIO_2_28 0x21c3 -#define MX23_PAD_EMI_CKE__GPIO_2_29 0x21d3 -#define MX23_PAD_EMI_RASN__GPIO_2_30 0x21e3 -#define MX23_PAD_EMI_WEN__GPIO_2_31 0x21f3 - -#endif /* __DT_BINDINGS_MX23_PINCTRL_H__ */ diff --git a/sys/gnu/dts/arm/imx23-sansa.dts b/sys/gnu/dts/arm/imx23-sansa.dts deleted file mode 100644 index 46057d9bf55..00000000000 --- a/sys/gnu/dts/arm/imx23-sansa.dts +++ /dev/null @@ -1,207 +0,0 @@ -/* - * Copyright (C) 2013-2016 Marek Vasut - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - -/dts-v1/; -#include -#include "imx23.dtsi" - -/ { - model = "SanDisk Sansa Fuze+"; - compatible = "sandisk,sansa_fuze_plus", "fsl,imx23"; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x04000000>; - }; - - apb@80000000 { - apbh@80000000 { - ssp0: spi@80010000 { - compatible = "fsl,imx23-mmc"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_pins_fixup>; - bus-width = <4>; - vmmc-supply = <®_vddio_sd0>; - cd-inverted; - status = "okay"; - }; - - ssp1: spi@80034000 { - compatible = "fsl,imx23-mmc"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_8bit_pins_a>; - bus-width = <8>; - vmmc-supply = <®_vddio_sd1>; - non-removable; - status = "okay"; - }; - - pinctrl@80018000 { - pinctrl-names = "default"; - pinctrl-0 = <&hog_pins_a>; - - hog_pins_a: hog@0 { - reg = <0>; - fsl,pinmux-ids = < - MX23_PAD_GPMI_D08__GPIO_0_8 - MX23_PAD_PWM3__GPIO_1_29 - MX23_PAD_AUART1_RTS__GPIO_0_27 - MX23_PAD_AUART1_CTS__GPIO_0_26 - MX23_PAD_I2C_SCL__I2C_SCL - MX23_PAD_I2C_SDA__I2C_SDA - MX23_PAD_LCD_DOTCK__GPIO_1_22 - MX23_PAD_LCD_HSYNC__GPIO_1_24 - MX23_PAD_PWM3__GPIO_1_29 - >; - fsl,drive-strength = <0>; - fsl,voltage = <1>; - fsl,pull-up = <0>; - }; - }; - }; - - apbx@80040000 { - pwm: pwm@80064000 { - pinctrl-names = "default"; - pinctrl-0 = <&pwm2_pins_a>; - status = "okay"; - }; - - duart: serial@80070000 { - pinctrl-names = "default"; - pinctrl-0 = <&duart_pins_a>; - status = "okay"; - }; - - usbphy0: usbphy@8007c000 { - status = "okay"; - }; - - lradc@80050000 { - status = "okay"; - }; - }; - }; - - ahb@80080000 { - usb0: usb@80080000 { - dr_mode = "peripheral"; - status = "okay"; - }; - }; - - reg_vddio_sd0: regulator-vddio-sd0 { - compatible = "regulator-fixed"; - regulator-name = "vddio-sd0"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio0 8 0>; - }; - - reg_vddio_sd1: regulator-vddio-sd1 { - compatible = "regulator-fixed"; - regulator-name = "vddio-sd1"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio1 29 0>; - }; - - reg_vdd_touchpad: regulator-vdd-touchpad0 { - compatible = "regulator-fixed"; - regulator-name = "vdd-touchpad0"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio0 26 GPIO_ACTIVE_LOW>; - regulator-always-on; - }; - - reg_vdd_tuner: regulator-vdd-tuner0 { - compatible = "regulator-fixed"; - regulator-name = "vdd-tuner0"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio0 29 GPIO_ACTIVE_LOW>; - regulator-always-on; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 2 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - }; - - i2c-0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "i2c-gpio"; - gpios = < - &gpio1 24 0 /* SDA */ - &gpio1 22 0 /* SCL */ - >; - i2c-gpio,delay-us = <2>; /* ~100 kHz */ - }; - - i2c-1 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "i2c-gpio"; - gpios = < - &gpio0 31 0 /* SDA */ - &gpio0 30 0 /* SCL */ - >; - i2c-gpio,delay-us = <2>; /* ~100 kHz */ - - touch: touch@20 { - compatible = "synaptics,synaptics_i2c"; - reg = <0x20>; - }; - - eeprom: eeprom@50 { - compatible = "atmel,24c64"; - reg = <0x50>; - pagesize = <32>; - }; - }; - -}; diff --git a/sys/gnu/dts/arm/imx23-stmp378x_devb.dts b/sys/gnu/dts/arm/imx23-stmp378x_devb.dts deleted file mode 100644 index da4b88f32ea..00000000000 --- a/sys/gnu/dts/arm/imx23-stmp378x_devb.dts +++ /dev/null @@ -1,76 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2012 Freescale Semiconductor, Inc. - */ - -/dts-v1/; -#include "imx23.dtsi" - -/ { - model = "Freescale STMP378x Development Board"; - compatible = "fsl,stmp378x-devb", "fsl,imx23"; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x04000000>; - }; - - apb@80000000 { - apbh@80000000 { - ssp0: spi@80010000 { - compatible = "fsl,imx23-mmc"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_pins_fixup>; - bus-width = <4>; - wp-gpios = <&gpio1 30 0>; - vmmc-supply = <®_vddio_sd0>; - status = "okay"; - }; - - pinctrl@80018000 { - pinctrl-names = "default"; - pinctrl-0 = <&hog_pins_a>; - - hog_pins_a: hog@0 { - reg = <0>; - fsl,pinmux-ids = < - MX23_PAD_PWM3__GPIO_1_29 - MX23_PAD_PWM4__GPIO_1_30 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - }; - }; - - apbx@80040000 { - auart0: serial@8006c000 { - pinctrl-names = "default"; - pinctrl-0 = <&auart0_pins_a>; - status = "okay"; - }; - - duart: serial@80070000 { - pinctrl-names = "default"; - pinctrl-0 = <&duart_pins_a>; - status = "okay"; - }; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_vddio_sd0: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "vddio-sd0"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio1 29 0>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/imx23-xfi3.dts b/sys/gnu/dts/arm/imx23-xfi3.dts deleted file mode 100644 index a6213c590f9..00000000000 --- a/sys/gnu/dts/arm/imx23-xfi3.dts +++ /dev/null @@ -1,180 +0,0 @@ -/* - * Copyright (C) 2013-2016 Marek Vasut - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - -/dts-v1/; -#include "imx23.dtsi" - -/ { - model = "Creative ZEN X-Fi3"; - compatible = "creative,x-fi3", "fsl,imx23"; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x04000000>; - }; - - apb@80000000 { - apbh@80000000 { - ssp0: spi@80010000 { - compatible = "fsl,imx23-mmc"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_pins_fixup>; - bus-width = <4>; - vmmc-supply = <®_vddio_sd0>; - cd-inverted; - status = "okay"; - }; - - ssp1: spi@80034000 { - compatible = "fsl,imx23-mmc"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_4bit_pins_a>; - bus-width = <4>; - non-removable; - status = "okay"; - }; - - pinctrl@80018000 { - pinctrl-names = "default"; - pinctrl-0 = <&hog_pins_a>; - - hog_pins_a: hog@0 { - reg = <0>; - fsl,pinmux-ids = < - MX23_PAD_GPMI_D07__GPIO_0_7 - >; - fsl,drive-strength = <0>; - fsl,voltage = <1>; - fsl,pull-up = <0>; - }; - - key_pins_a: keys@0 { - reg = <0>; - fsl,pinmux-ids = < - MX23_PAD_ROTARYA__GPIO_2_7 - MX23_PAD_ROTARYB__GPIO_2_8 - >; - fsl,drive-strength = <0>; - fsl,voltage = <1>; - fsl,pull-up = <1>; - }; - }; - }; - - apbx@80040000 { - i2c: i2c@80058000 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c_pins_a>; - status = "okay"; - }; - - pwm: pwm@80064000 { - pinctrl-names = "default"; - pinctrl-0 = <&pwm2_pins_a>; - status = "okay"; - }; - - duart: serial@80070000 { - pinctrl-names = "default"; - pinctrl-0 = <&duart_pins_a>; - status = "okay"; - }; - - auart1: serial@8006e000 { - pinctrl-names = "default"; - pinctrl-0 = <&auart1_2pins_a>; - status = "okay"; - }; - - usbphy0: usbphy@8007c000 { - status = "okay"; - }; - - lradc@80050000 { - status = "okay"; - }; - }; - }; - - ahb@80080000 { - usb0: usb@80080000 { - dr_mode = "peripheral"; - status = "okay"; - }; - }; - - reg_vddio_sd0: regulator-vddio-sd0 { - compatible = "regulator-fixed"; - regulator-name = "vddio-sd0"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio0 7 0>; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 2 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - }; - - gpio_keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&key_pins_a>; - - voldown { - label = "volume-down"; - linux,code = <114>; - gpios = <&gpio2 7 0>; - debounce-interval = <20>; - }; - - volup { - label = "volume-up"; - linux,code = <115>; - gpios = <&gpio2 8 0>; - debounce-interval = <20>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/imx23.dtsi b/sys/gnu/dts/arm/imx23.dtsi deleted file mode 100644 index 8257630f7a4..00000000000 --- a/sys/gnu/dts/arm/imx23.dtsi +++ /dev/null @@ -1,628 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// -// Copyright 2012 Freescale Semiconductor, Inc. - -#include "imx23-pinfunc.h" - -/ { - #address-cells = <1>; - #size-cells = <1>; - - interrupt-parent = <&icoll>; - /* - * The decompressor and also some bootloaders rely on a - * pre-existing /chosen node to be available to insert the - * command line and merge other ATAGS info. - */ - chosen {}; - - aliases { - gpio0 = &gpio0; - gpio1 = &gpio1; - gpio2 = &gpio2; - serial0 = &auart0; - serial1 = &auart1; - spi0 = &ssp0; - spi1 = &ssp1; - usbphy0 = &usbphy0; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "arm,arm926ej-s"; - device_type = "cpu"; - reg = <0>; - }; - }; - - apb@80000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x80000000 0x80000>; - ranges; - - apbh@80000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x80000000 0x40000>; - ranges; - - icoll: interrupt-controller@80000000 { - compatible = "fsl,imx23-icoll", "fsl,icoll"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x80000000 0x2000>; - }; - - dma_apbh: dma-apbh@80004000 { - compatible = "fsl,imx23-dma-apbh"; - reg = <0x80004000 0x2000>; - interrupts = <0 14 20 0 - 13 13 13 13>; - interrupt-names = "empty", "ssp0", "ssp1", "empty", - "gpmi0", "gpmi1", "gpmi2", "gpmi3"; - #dma-cells = <1>; - dma-channels = <8>; - clocks = <&clks 15>; - }; - - ecc@80008000 { - reg = <0x80008000 0x2000>; - status = "disabled"; - }; - - gpmi-nand@8000c000 { - compatible = "fsl,imx23-gpmi-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>; - reg-names = "gpmi-nand", "bch"; - interrupts = <56>; - interrupt-names = "bch"; - clocks = <&clks 34>; - clock-names = "gpmi_io"; - dmas = <&dma_apbh 4>; - dma-names = "rx-tx"; - status = "disabled"; - }; - - ssp0: spi@80010000 { - reg = <0x80010000 0x2000>; - interrupts = <15>; - clocks = <&clks 33>; - dmas = <&dma_apbh 1>; - dma-names = "rx-tx"; - status = "disabled"; - }; - - etm@80014000 { - reg = <0x80014000 0x2000>; - status = "disabled"; - }; - - pinctrl@80018000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx23-pinctrl", "simple-bus"; - reg = <0x80018000 0x2000>; - - gpio0: gpio@0 { - compatible = "fsl,imx23-gpio", "fsl,mxs-gpio"; - reg = <0>; - interrupts = <16>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio@1 { - compatible = "fsl,imx23-gpio", "fsl,mxs-gpio"; - reg = <1>; - interrupts = <17>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@2 { - compatible = "fsl,imx23-gpio", "fsl,mxs-gpio"; - reg = <2>; - interrupts = <18>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - duart_pins_a: duart@0 { - reg = <0>; - fsl,pinmux-ids = < - MX23_PAD_PWM0__DUART_RX - MX23_PAD_PWM1__DUART_TX - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - auart0_pins_a: auart0@0 { - reg = <0>; - fsl,pinmux-ids = < - MX23_PAD_AUART1_RX__AUART1_RX - MX23_PAD_AUART1_TX__AUART1_TX - MX23_PAD_AUART1_CTS__AUART1_CTS - MX23_PAD_AUART1_RTS__AUART1_RTS - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - auart0_2pins_a: auart0-2pins@0 { - reg = <0>; - fsl,pinmux-ids = < - MX23_PAD_I2C_SCL__AUART1_TX - MX23_PAD_I2C_SDA__AUART1_RX - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - auart1_2pins_a: auart1-2pins@0 { - reg = <0>; - fsl,pinmux-ids = < - MX23_PAD_GPMI_D14__AUART2_RX - MX23_PAD_GPMI_D15__AUART2_TX - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - gpmi_pins_a: gpmi-nand@0 { - reg = <0>; - fsl,pinmux-ids = < - MX23_PAD_GPMI_D00__GPMI_D00 - MX23_PAD_GPMI_D01__GPMI_D01 - MX23_PAD_GPMI_D02__GPMI_D02 - MX23_PAD_GPMI_D03__GPMI_D03 - MX23_PAD_GPMI_D04__GPMI_D04 - MX23_PAD_GPMI_D05__GPMI_D05 - MX23_PAD_GPMI_D06__GPMI_D06 - MX23_PAD_GPMI_D07__GPMI_D07 - MX23_PAD_GPMI_CLE__GPMI_CLE - MX23_PAD_GPMI_ALE__GPMI_ALE - MX23_PAD_GPMI_RDY0__GPMI_RDY0 - MX23_PAD_GPMI_RDY1__GPMI_RDY1 - MX23_PAD_GPMI_WPN__GPMI_WPN - MX23_PAD_GPMI_WRN__GPMI_WRN - MX23_PAD_GPMI_RDN__GPMI_RDN - MX23_PAD_GPMI_CE1N__GPMI_CE1N - MX23_PAD_GPMI_CE0N__GPMI_CE0N - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - gpmi_pins_fixup: gpmi-pins-fixup@0 { - reg = <0>; - fsl,pinmux-ids = < - MX23_PAD_GPMI_WPN__GPMI_WPN - MX23_PAD_GPMI_WRN__GPMI_WRN - MX23_PAD_GPMI_RDN__GPMI_RDN - >; - fsl,drive-strength = ; - }; - - mmc0_4bit_pins_a: mmc0-4bit@0 { - reg = <0>; - fsl,pinmux-ids = < - MX23_PAD_SSP1_DATA0__SSP1_DATA0 - MX23_PAD_SSP1_DATA1__SSP1_DATA1 - MX23_PAD_SSP1_DATA2__SSP1_DATA2 - MX23_PAD_SSP1_DATA3__SSP1_DATA3 - MX23_PAD_SSP1_CMD__SSP1_CMD - MX23_PAD_SSP1_SCK__SSP1_SCK - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - mmc0_8bit_pins_a: mmc0-8bit@0 { - reg = <0>; - fsl,pinmux-ids = < - MX23_PAD_SSP1_DATA0__SSP1_DATA0 - MX23_PAD_SSP1_DATA1__SSP1_DATA1 - MX23_PAD_SSP1_DATA2__SSP1_DATA2 - MX23_PAD_SSP1_DATA3__SSP1_DATA3 - MX23_PAD_GPMI_D08__SSP1_DATA4 - MX23_PAD_GPMI_D09__SSP1_DATA5 - MX23_PAD_GPMI_D10__SSP1_DATA6 - MX23_PAD_GPMI_D11__SSP1_DATA7 - MX23_PAD_SSP1_CMD__SSP1_CMD - MX23_PAD_SSP1_DETECT__SSP1_DETECT - MX23_PAD_SSP1_SCK__SSP1_SCK - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - mmc0_pins_fixup: mmc0-pins-fixup@0 { - reg = <0>; - fsl,pinmux-ids = < - MX23_PAD_SSP1_DETECT__SSP1_DETECT - MX23_PAD_SSP1_SCK__SSP1_SCK - >; - fsl,pull-up = ; - }; - - mmc1_4bit_pins_a: mmc1-4bit@0 { - reg = <0>; - fsl,pinmux-ids = < - MX23_PAD_GPMI_D00__SSP2_DATA0 - MX23_PAD_GPMI_D01__SSP2_DATA1 - MX23_PAD_GPMI_D02__SSP2_DATA2 - MX23_PAD_GPMI_D03__SSP2_DATA3 - MX23_PAD_GPMI_RDY1__SSP2_CMD - MX23_PAD_GPMI_WRN__SSP2_SCK - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - mmc1_8bit_pins_a: mmc1-8bit@0 { - reg = <0>; - fsl,pinmux-ids = < - MX23_PAD_GPMI_D00__SSP2_DATA0 - MX23_PAD_GPMI_D01__SSP2_DATA1 - MX23_PAD_GPMI_D02__SSP2_DATA2 - MX23_PAD_GPMI_D03__SSP2_DATA3 - MX23_PAD_GPMI_D04__SSP2_DATA4 - MX23_PAD_GPMI_D05__SSP2_DATA5 - MX23_PAD_GPMI_D06__SSP2_DATA6 - MX23_PAD_GPMI_D07__SSP2_DATA7 - MX23_PAD_GPMI_RDY1__SSP2_CMD - MX23_PAD_GPMI_WRN__SSP2_SCK - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - pwm2_pins_a: pwm2@0 { - reg = <0>; - fsl,pinmux-ids = < - MX23_PAD_PWM2__PWM2 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - lcdif_24bit_pins_a: lcdif-24bit@0 { - reg = <0>; - fsl,pinmux-ids = < - MX23_PAD_LCD_D00__LCD_D00 - MX23_PAD_LCD_D01__LCD_D01 - MX23_PAD_LCD_D02__LCD_D02 - MX23_PAD_LCD_D03__LCD_D03 - MX23_PAD_LCD_D04__LCD_D04 - MX23_PAD_LCD_D05__LCD_D05 - MX23_PAD_LCD_D06__LCD_D06 - MX23_PAD_LCD_D07__LCD_D07 - MX23_PAD_LCD_D08__LCD_D08 - MX23_PAD_LCD_D09__LCD_D09 - MX23_PAD_LCD_D10__LCD_D10 - MX23_PAD_LCD_D11__LCD_D11 - MX23_PAD_LCD_D12__LCD_D12 - MX23_PAD_LCD_D13__LCD_D13 - MX23_PAD_LCD_D14__LCD_D14 - MX23_PAD_LCD_D15__LCD_D15 - MX23_PAD_LCD_D16__LCD_D16 - MX23_PAD_LCD_D17__LCD_D17 - MX23_PAD_GPMI_D08__LCD_D18 - MX23_PAD_GPMI_D09__LCD_D19 - MX23_PAD_GPMI_D10__LCD_D20 - MX23_PAD_GPMI_D11__LCD_D21 - MX23_PAD_GPMI_D12__LCD_D22 - MX23_PAD_GPMI_D13__LCD_D23 - MX23_PAD_LCD_DOTCK__LCD_DOTCK - MX23_PAD_LCD_ENABLE__LCD_ENABLE - MX23_PAD_LCD_HSYNC__LCD_HSYNC - MX23_PAD_LCD_VSYNC__LCD_VSYNC - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - spi2_pins_a: spi2@0 { - reg = <0>; - fsl,pinmux-ids = < - MX23_PAD_GPMI_WRN__SSP2_SCK - MX23_PAD_GPMI_RDY1__SSP2_CMD - MX23_PAD_GPMI_D00__SSP2_DATA0 - MX23_PAD_GPMI_D03__SSP2_DATA3 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - i2c_pins_a: i2c@0 { - reg = <0>; - fsl,pinmux-ids = < - MX23_PAD_I2C_SCL__I2C_SCL - MX23_PAD_I2C_SDA__I2C_SDA - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - i2c_pins_b: i2c@1 { - reg = <1>; - fsl,pinmux-ids = < - MX23_PAD_LCD_ENABLE__I2C_SCL - MX23_PAD_LCD_HSYNC__I2C_SDA - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - i2c_pins_c: i2c@2 { - reg = <2>; - fsl,pinmux-ids = < - MX23_PAD_SSP1_DATA1__I2C_SCL - MX23_PAD_SSP1_DATA2__I2C_SDA - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - }; - - digctl@8001c000 { - compatible = "fsl,imx23-digctl"; - reg = <0x8001c000 2000>; - status = "disabled"; - }; - - emi@80020000 { - reg = <0x80020000 0x2000>; - status = "disabled"; - }; - - dma_apbx: dma-apbx@80024000 { - compatible = "fsl,imx23-dma-apbx"; - reg = <0x80024000 0x2000>; - interrupts = <7 5 9 26 - 19 0 25 23 - 60 58 9 0 - 0 0 0 0>; - interrupt-names = "audio-adc", "audio-dac", "spdif-tx", "i2c", - "saif0", "empty", "auart0-rx", "auart0-tx", - "auart1-rx", "auart1-tx", "saif1", "empty", - "empty", "empty", "empty", "empty"; - #dma-cells = <1>; - dma-channels = <16>; - clocks = <&clks 16>; - }; - - dcp@80028000 { - compatible = "fsl,imx23-dcp"; - reg = <0x80028000 0x2000>; - interrupts = <53 54>; - status = "okay"; - }; - - pxp@8002a000 { - reg = <0x8002a000 0x2000>; - status = "disabled"; - }; - - ocotp@8002c000 { - compatible = "fsl,imx23-ocotp", "fsl,ocotp"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x8002c000 0x2000>; - clocks = <&clks 15>; - }; - - axi-ahb@8002e000 { - reg = <0x8002e000 0x2000>; - status = "disabled"; - }; - - lcdif@80030000 { - compatible = "fsl,imx23-lcdif"; - reg = <0x80030000 2000>; - interrupts = <46 45>; - clocks = <&clks 38>; - status = "disabled"; - }; - - ssp1: spi@80034000 { - reg = <0x80034000 0x2000>; - interrupts = <2>; - clocks = <&clks 33>; - dmas = <&dma_apbh 2>; - dma-names = "rx-tx"; - status = "disabled"; - }; - - tvenc@80038000 { - reg = <0x80038000 0x2000>; - status = "disabled"; - }; - }; - - apbx@80040000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x80040000 0x40000>; - ranges; - - clks: clkctrl@80040000 { - compatible = "fsl,imx23-clkctrl", "fsl,clkctrl"; - reg = <0x80040000 0x2000>; - #clock-cells = <1>; - }; - - saif0: saif@80042000 { - reg = <0x80042000 0x2000>; - dmas = <&dma_apbx 4>; - dma-names = "rx-tx"; - status = "disabled"; - }; - - power@80044000 { - reg = <0x80044000 0x2000>; - status = "disabled"; - }; - - saif1: saif@80046000 { - reg = <0x80046000 0x2000>; - dmas = <&dma_apbx 10>; - dma-names = "rx-tx"; - status = "disabled"; - }; - - audio-out@80048000 { - reg = <0x80048000 0x2000>; - dmas = <&dma_apbx 1>; - dma-names = "tx"; - status = "disabled"; - }; - - audio-in@8004c000 { - reg = <0x8004c000 0x2000>; - dmas = <&dma_apbx 0>; - dma-names = "rx"; - status = "disabled"; - }; - - lradc: lradc@80050000 { - compatible = "fsl,imx23-lradc"; - reg = <0x80050000 0x2000>; - interrupts = <36 37 38 39 40 41 42 43 44>; - status = "disabled"; - clocks = <&clks 26>; - #io-channel-cells = <1>; - }; - - spdif@80054000 { - reg = <0x80054000 2000>; - dmas = <&dma_apbx 2>; - dma-names = "tx"; - status = "disabled"; - }; - - i2c: i2c@80058000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx23-i2c"; - reg = <0x80058000 0x2000>; - interrupts = <27>; - clock-frequency = <100000>; - dmas = <&dma_apbx 3>; - dma-names = "rx-tx"; - status = "disabled"; - }; - - rtc@8005c000 { - compatible = "fsl,imx23-rtc", "fsl,stmp3xxx-rtc"; - reg = <0x8005c000 0x2000>; - interrupts = <22>; - }; - - pwm: pwm@80064000 { - compatible = "fsl,imx23-pwm"; - reg = <0x80064000 0x2000>; - clocks = <&clks 30>; - #pwm-cells = <2>; - fsl,pwm-number = <5>; - status = "disabled"; - }; - - timrot@80068000 { - compatible = "fsl,imx23-timrot", "fsl,timrot"; - reg = <0x80068000 0x2000>; - interrupts = <28 29 30 31>; - clocks = <&clks 28>; - }; - - auart0: serial@8006c000 { - compatible = "fsl,imx23-auart"; - reg = <0x8006c000 0x2000>; - interrupts = <24>; - clocks = <&clks 32>; - dmas = <&dma_apbx 6>, <&dma_apbx 7>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - auart1: serial@8006e000 { - compatible = "fsl,imx23-auart"; - reg = <0x8006e000 0x2000>; - interrupts = <59>; - clocks = <&clks 32>; - dmas = <&dma_apbx 8>, <&dma_apbx 9>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - duart: serial@80070000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x80070000 0x2000>; - interrupts = <0>; - clocks = <&clks 32>, <&clks 16>; - clock-names = "uart", "apb_pclk"; - status = "disabled"; - }; - - usbphy0: usbphy@8007c000 { - compatible = "fsl,imx23-usbphy"; - reg = <0x8007c000 0x2000>; - clocks = <&clks 41>; - status = "disabled"; - }; - }; - }; - - ahb@80080000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x80080000 0x80000>; - ranges; - - usb0: usb@80080000 { - compatible = "fsl,imx23-usb", "fsl,imx27-usb"; - reg = <0x80080000 0x40000>; - interrupts = <11>; - fsl,usbphy = <&usbphy0>; - clocks = <&clks 40>; - status = "disabled"; - }; - }; - - iio-hwmon { - compatible = "iio-hwmon"; - io-channels = <&lradc 8>; - }; -}; diff --git a/sys/gnu/dts/arm/imx25-eukrea-cpuimx25.dtsi b/sys/gnu/dts/arm/imx25-eukrea-cpuimx25.dtsi deleted file mode 100644 index 0703f62d10d..00000000000 --- a/sys/gnu/dts/arm/imx25-eukrea-cpuimx25.dtsi +++ /dev/null @@ -1,66 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Eukréa Electromatique - */ - -#include "imx25.dtsi" - -/ { - model = "Eukrea CPUIMX25"; - compatible = "eukrea,cpuimx25", "fsl,imx25"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x4000000>; /* 64M */ - }; -}; - -&fec { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec>; - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pcf8563@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; -}; - -&iomuxc { - imx25-eukrea-cpuimx25 { - pinctrl_fec: fecgrp { - fsl,pins = < - MX25_PAD_FEC_MDC__FEC_MDC 0x80000000 - MX25_PAD_FEC_MDIO__FEC_MDIO 0x400001e0 - MX25_PAD_FEC_TDATA0__FEC_TDATA0 0x80000000 - MX25_PAD_FEC_TDATA1__FEC_TDATA1 0x80000000 - MX25_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 - MX25_PAD_FEC_RDATA0__FEC_RDATA0 0x80000000 - MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x80000000 - MX25_PAD_FEC_RX_DV__FEC_RX_DV 0x80000000 - MX25_PAD_FEC_TX_CLK__FEC_TX_CLK 0x1c0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX25_PAD_I2C1_CLK__I2C1_CLK 0x80000000 - MX25_PAD_I2C1_DAT__I2C1_DAT 0x80000000 - >; - }; - }; -}; - -&nfc { - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - nand-on-flash-bbt; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dts b/sys/gnu/dts/arm/imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dts deleted file mode 100644 index 7d4301b22b9..00000000000 --- a/sys/gnu/dts/arm/imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dts +++ /dev/null @@ -1,65 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Eukréa Electromatique - */ - -#include "imx25-eukrea-mbimxsd25-baseboard.dts" - -/ { - model = "Eukrea MBIMXSD25 with the CMO-QVGA Display"; - compatible = "eukrea,mbimxsd25-baseboard-cmo-qvga", "eukrea,mbimxsd25-baseboard", "eukrea,cpuimx25", "fsl,imx25"; - - cmo_qvga: display { - model = "CMO-QVGA"; - bits-per-pixel = <16>; - fsl,pcr = <0xcad08b80>; - bus-width = <18>; - display-timings { - native-mode = <&qvga_timings>; - qvga_timings: 320x240 { - clock-frequency = <6500000>; - hactive = <320>; - vactive = <240>; - hback-porch = <30>; - hfront-porch = <38>; - vback-porch = <20>; - vfront-porch = <3>; - hsync-len = <15>; - vsync-len = <4>; - }; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_lcd_3v3: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_lcd_3v3>; - regulator-name = "lcd-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - }; -}; - -&iomuxc { - imx25-eukrea-mbimxsd25-baseboard-cmo-qvga { - pinctrl_reg_lcd_3v3: reg_lcd_3v3 { - fsl,pins = ; - }; - }; -}; - -&lcdc { - display = <&cmo_qvga>; - fsl,lpccr = <0x00a903ff>; - lcd-supply = <®_lcd_3v3>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx25-eukrea-mbimxsd25-baseboard-dvi-svga.dts b/sys/gnu/dts/arm/imx25-eukrea-mbimxsd25-baseboard-dvi-svga.dts deleted file mode 100644 index 80a7f96de4c..00000000000 --- a/sys/gnu/dts/arm/imx25-eukrea-mbimxsd25-baseboard-dvi-svga.dts +++ /dev/null @@ -1,37 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Eukréa Electromatique - */ - -#include "imx25-eukrea-mbimxsd25-baseboard.dts" - -/ { - model = "Eukrea MBIMXSD25 with the DVI-SVGA Display"; - compatible = "eukrea,mbimxsd25-baseboard-dvi-svga", "eukrea,mbimxsd25-baseboard", "eukrea,cpuimx25", "fsl,imx25"; - - dvi_svga: display { - model = "DVI-SVGA"; - bits-per-pixel = <16>; - fsl,pcr = <0xfa208b80>; - bus-width = <18>; - display-timings { - native-mode = <&dvi_svga_timings>; - dvi_svga_timings: 800x600 { - clock-frequency = <40000000>; - hactive = <800>; - vactive = <600>; - hback-porch = <75>; - hfront-porch = <75>; - vback-porch = <7>; - vfront-porch = <75>; - hsync-len = <7>; - vsync-len = <7>; - }; - }; - }; -}; - -&lcdc { - display = <&dvi_svga>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx25-eukrea-mbimxsd25-baseboard-dvi-vga.dts b/sys/gnu/dts/arm/imx25-eukrea-mbimxsd25-baseboard-dvi-vga.dts deleted file mode 100644 index 24027a1fb46..00000000000 --- a/sys/gnu/dts/arm/imx25-eukrea-mbimxsd25-baseboard-dvi-vga.dts +++ /dev/null @@ -1,37 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Eukréa Electromatique - */ - -#include "imx25-eukrea-mbimxsd25-baseboard.dts" - -/ { - model = "Eukrea MBIMXSD25 with the DVI-VGA Display"; - compatible = "eukrea,mbimxsd25-baseboard-dvi-vga", "eukrea,mbimxsd25-baseboard", "eukrea,cpuimx25", "fsl,imx25"; - - dvi_vga: display { - model = "DVI-VGA"; - bits-per-pixel = <16>; - fsl,pcr = <0xfa208b80>; - bus-width = <18>; - display-timings { - native-mode = <&dvi_vga_timings>; - dvi_vga_timings: 640x480 { - clock-frequency = <31250000>; - hactive = <640>; - vactive = <480>; - hback-porch = <100>; - hfront-porch = <100>; - vback-porch = <7>; - vfront-porch = <100>; - hsync-len = <7>; - vsync-len = <7>; - }; - }; - }; -}; - -&lcdc { - display = <&dvi_vga>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx25-eukrea-mbimxsd25-baseboard.dts b/sys/gnu/dts/arm/imx25-eukrea-mbimxsd25-baseboard.dts deleted file mode 100644 index 3f38c2e60a7..00000000000 --- a/sys/gnu/dts/arm/imx25-eukrea-mbimxsd25-baseboard.dts +++ /dev/null @@ -1,174 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Eukréa Electromatique - */ - -/dts-v1/; - -#include -#include -#include "imx25-eukrea-cpuimx25.dtsi" - -/ { - model = "Eukrea MBIMXSD25"; - compatible = "eukrea,mbimxsd25-baseboard", "eukrea,cpuimx25", "fsl,imx25"; - - gpio_keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpiokeys>; - - bp1 { - label = "BP1"; - gpios = <&gpio3 18 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpioled>; - - led1 { - label = "led1"; - gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - }; - }; - - sound { - compatible = "eukrea,asoc-tlv320"; - eukrea,model = "imx25-eukrea-tlv320aic23"; - ssi-controller = <&ssi1>; - fsl,mux-int-port = <1>; - fsl,mux-ext-port = <5>; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; - -&esdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc1>; - cd-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&i2c1 { - tlv320aic23: codec@1a { - compatible = "ti,tlv320aic23"; - reg = <0x1a>; - }; -}; - -&iomuxc { - imx25-eukrea-mbimxsd25-baseboard { - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX25_PAD_KPP_COL3__AUD5_TXFS 0xe0 - MX25_PAD_KPP_COL2__AUD5_TXC 0xe0 - MX25_PAD_KPP_COL1__AUD5_RXD 0xe0 - MX25_PAD_KPP_COL0__AUD5_TXD 0xe0 - >; - }; - - pinctrl_esdhc1: esdhc1grp { - fsl,pins = < - MX25_PAD_SD1_CMD__ESDHC1_CMD 0x400000c0 - MX25_PAD_SD1_CLK__ESDHC1_CLK 0x400000c0 - MX25_PAD_SD1_DATA0__ESDHC1_DAT0 0x400000c0 - MX25_PAD_SD1_DATA1__ESDHC1_DAT1 0x400000c0 - MX25_PAD_SD1_DATA2__ESDHC1_DAT2 0x400000c0 - MX25_PAD_SD1_DATA3__ESDHC1_DAT3 0x400000c0 - >; - }; - - pinctrl_gpiokeys: gpiokeysgrp { - fsl,pins = ; - }; - - pinctrl_gpioled: gpioledgrp { - fsl,pins = ; - }; - - pinctrl_lcdc: lcdcgrp { - fsl,pins = < - MX25_PAD_LD0__LD0 0x1 - MX25_PAD_LD1__LD1 0x1 - MX25_PAD_LD2__LD2 0x1 - MX25_PAD_LD3__LD3 0x1 - MX25_PAD_LD4__LD4 0x1 - MX25_PAD_LD5__LD5 0x1 - MX25_PAD_LD6__LD6 0x1 - MX25_PAD_LD7__LD7 0x1 - MX25_PAD_LD8__LD8 0x1 - MX25_PAD_LD9__LD9 0x1 - MX25_PAD_LD10__LD10 0x1 - MX25_PAD_LD11__LD11 0x1 - MX25_PAD_LD12__LD12 0x1 - MX25_PAD_LD13__LD13 0x1 - MX25_PAD_LD14__LD14 0x1 - MX25_PAD_LD15__LD15 0x1 - MX25_PAD_GPIO_E__LD16 0x1 - MX25_PAD_GPIO_F__LD17 0x1 - MX25_PAD_HSYNC__HSYNC 0x80000000 - MX25_PAD_VSYNC__VSYNC 0x80000000 - MX25_PAD_LSCLK__LSCLK 0x80000000 - MX25_PAD_OE_ACD__OE_ACD 0x80000000 - MX25_PAD_CONTRAST__CONTRAST 0x80000000 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX25_PAD_UART1_RTS__UART1_RTS 0xe0 - MX25_PAD_UART1_CTS__UART1_CTS 0xe0 - MX25_PAD_UART1_TXD__UART1_TXD 0x80000000 - MX25_PAD_UART1_RXD__UART1_RXD 0xc0 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX25_PAD_UART2_RXD__UART2_RXD 0x80000000 - MX25_PAD_UART2_TXD__UART2_TXD 0x80000000 - MX25_PAD_UART2_RTS__UART2_RTS 0x80000000 - MX25_PAD_UART2_CTS__UART2_CTS 0x80000000 - >; - }; - }; -}; - -&ssi1 { - codec-handle = <&tlv320aic23>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - uart-has-rtscts; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - uart-has-rtscts; - status = "okay"; -}; - -&usbhost1 { - status = "okay"; -}; - -&usbotg { - external-vbus-divider; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx25-karo-tx25.dts b/sys/gnu/dts/arm/imx25-karo-tx25.dts deleted file mode 100644 index 0950eb66d3d..00000000000 --- a/sys/gnu/dts/arm/imx25-karo-tx25.dts +++ /dev/null @@ -1,108 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2012 Sascha Hauer, Pengutronix - */ - -/dts-v1/; -#include "imx25.dtsi" - -/ { - model = "Ka-Ro TX25"; - compatible = "karo,imx25-tx25", "fsl,imx25"; - - chosen { - stdout-path = &uart1; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_fec_phy: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "fec-phy"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio4 9 0>; - enable-active-high; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x02000000 0x90000000 0x02000000>; - }; -}; - -&iomuxc { - pinctrl_uart1: uart1grp { - fsl,pins = < - MX25_PAD_UART1_TXD__UART1_TXD 0x80000000 - MX25_PAD_UART1_RXD__UART1_RXD 0x80000000 - MX25_PAD_UART1_CTS__UART1_CTS 0x80000000 - MX25_PAD_UART1_RTS__UART1_RTS 0x80000000 - >; - }; - - pinctrl_fec: fecgrp { - fsl,pins = < - MX25_PAD_D11__GPIO_4_9 0x80000000 /* FEC PHY power on pin */ - MX25_PAD_D13__GPIO_4_7 0x80000000 /* FEC reset */ - MX25_PAD_FEC_MDC__FEC_MDC 0x80000000 - MX25_PAD_FEC_MDIO__FEC_MDIO 0x80000000 - MX25_PAD_FEC_TDATA0__FEC_TDATA0 0x80000000 - MX25_PAD_FEC_TDATA1__FEC_TDATA1 0x80000000 - MX25_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 - MX25_PAD_FEC_RDATA0__FEC_RDATA0 0x80000000 - MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x80000000 - MX25_PAD_FEC_RX_DV__FEC_RX_DV 0x80000000 - MX25_PAD_FEC_TX_CLK__FEC_TX_CLK 0x80000000 - >; - }; - - pinctrl_nfc: nfcgrp { - fsl,pins = < - MX25_PAD_NF_CE0__NF_CE0 0x80000000 - MX25_PAD_NFWE_B__NFWE_B 0x80000000 - MX25_PAD_NFRE_B__NFRE_B 0x80000000 - MX25_PAD_NFALE__NFALE 0x80000000 - MX25_PAD_NFCLE__NFCLE 0x80000000 - MX25_PAD_NFWP_B__NFWP_B 0x80000000 - MX25_PAD_NFRB__NFRB 0x80000000 - MX25_PAD_D7__D7 0x80000000 - MX25_PAD_D6__D6 0x80000000 - MX25_PAD_D5__D5 0x80000000 - MX25_PAD_D4__D4 0x80000000 - MX25_PAD_D3__D3 0x80000000 - MX25_PAD_D2__D2 0x80000000 - MX25_PAD_D1__D1 0x80000000 - MX25_PAD_D0__D0 0x80000000 - >; - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec>; - phy-reset-gpios = <&gpio3 7 GPIO_ACTIVE_LOW>; - phy-mode = "rmii"; - phy-supply = <®_fec_phy>; - status = "okay"; -}; - -&nfc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nfc>; - nand-on-flash-bbt; - nand-ecc-mode = "hw"; - nand-bus-width = <8>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx25-pdk.dts b/sys/gnu/dts/arm/imx25-pdk.dts deleted file mode 100644 index fb66884d8a2..00000000000 --- a/sys/gnu/dts/arm/imx25-pdk.dts +++ /dev/null @@ -1,313 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// -// Copyright 2013 Freescale Semiconductor, Inc. - -/dts-v1/; -#include -#include -#include "imx25.dtsi" - -/ { - model = "Freescale i.MX25 Product Development Kit"; - compatible = "fsl,imx25-pdk", "fsl,imx25"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x4000000>; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_fec_3v3: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "fec-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 3 0>; - enable-active-high; - }; - - reg_2p5v: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "2P5V"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - }; - - reg_3p3v: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_can_3v3: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "can-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio4 6 0>; - }; - }; - - sound { - compatible = "fsl,imx25-pdk-sgtl5000", - "fsl,imx-audio-sgtl5000"; - model = "imx25-pdk-sgtl5000"; - ssi-controller = <&ssi1>; - audio-codec = <&codec>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - mux-int-port = <1>; - mux-ext-port = <4>; - }; - - wvga: display { - model = "CLAA057VC01CW"; - bits-per-pixel = <16>; - fsl,pcr = <0xfa208b80>; - bus-width = <18>; - display-timings { - native-mode = <&wvga_timings>; - wvga_timings: 640x480 { - hactive = <640>; - vactive = <480>; - hback-porch = <45>; - hfront-porch = <114>; - hsync-len = <1>; - vback-porch = <33>; - vfront-porch = <11>; - vsync-len = <1>; - clock-frequency = <25200000>; - }; - }; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can1>; - xceiver-supply = <®_can_3v3>; - status = "okay"; -}; - -&esdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc1>; - cd-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio2 0 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&fec { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec>; - phy-supply = <®_fec_3v3>; - phy-reset-gpios = <&gpio4 8 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - codec: sgtl5000@a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - clocks = <&clks 129>; - VDDA-supply = <®_2p5v>; - VDDIO-supply = <®_3p3v>; - }; -}; - -&iomuxc { - imx25-pdk { - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX25_PAD_RW__AUD4_TXFS 0xe0 - MX25_PAD_OE__AUD4_TXC 0xe0 - MX25_PAD_EB0__AUD4_TXD 0xe0 - MX25_PAD_EB1__AUD4_RXD 0xe0 - >; - }; - - pinctrl_can1: can1grp { - fsl,pins = < - MX25_PAD_GPIO_A__CAN1_TX 0x0 - MX25_PAD_GPIO_B__CAN1_RX 0x0 - MX25_PAD_D14__GPIO_4_6 0x80000000 - >; - }; - - pinctrl_esdhc1: esdhc1grp { - fsl,pins = < - MX25_PAD_SD1_CMD__ESDHC1_CMD 0x80000000 - MX25_PAD_SD1_CLK__ESDHC1_CLK 0x80000000 - MX25_PAD_SD1_DATA0__ESDHC1_DAT0 0x80000000 - MX25_PAD_SD1_DATA1__ESDHC1_DAT1 0x80000000 - MX25_PAD_SD1_DATA2__ESDHC1_DAT2 0x80000000 - MX25_PAD_SD1_DATA3__ESDHC1_DAT3 0x80000000 - MX25_PAD_A14__GPIO_2_0 0x80000000 - MX25_PAD_A15__GPIO_2_1 0x80000000 - >; - }; - - pinctrl_fec: fecgrp { - fsl,pins = < - MX25_PAD_FEC_MDC__FEC_MDC 0x80000000 - MX25_PAD_FEC_MDIO__FEC_MDIO 0x400001e0 - MX25_PAD_FEC_TDATA0__FEC_TDATA0 0x80000000 - MX25_PAD_FEC_TDATA1__FEC_TDATA1 0x80000000 - MX25_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 - MX25_PAD_FEC_RDATA0__FEC_RDATA0 0x80000000 - MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x80000000 - MX25_PAD_FEC_RX_DV__FEC_RX_DV 0x80000000 - MX25_PAD_FEC_TX_CLK__FEC_TX_CLK 0x1c0 - MX25_PAD_A17__GPIO_2_3 0x80000000 - MX25_PAD_D12__GPIO_4_8 0x80000000 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX25_PAD_I2C1_CLK__I2C1_CLK 0x80000000 - MX25_PAD_I2C1_DAT__I2C1_DAT 0x80000000 - >; - }; - - pinctrl_kpp: kppgrp { - fsl,pins = < - MX25_PAD_KPP_ROW0__KPP_ROW0 0x80000000 - MX25_PAD_KPP_ROW1__KPP_ROW1 0x80000000 - MX25_PAD_KPP_ROW2__KPP_ROW2 0x80000000 - MX25_PAD_KPP_ROW3__KPP_ROW3 0x80000000 - MX25_PAD_KPP_COL0__KPP_COL0 0x80000000 - MX25_PAD_KPP_COL1__KPP_COL1 0x80000000 - MX25_PAD_KPP_COL2__KPP_COL2 0x80000000 - MX25_PAD_KPP_COL3__KPP_COL3 0x80000000 - >; - }; - - pinctrl_lcd: lcdgrp { - fsl,pins = < - MX25_PAD_LD0__LD0 0xe0 - MX25_PAD_LD1__LD1 0xe0 - MX25_PAD_LD2__LD2 0xe0 - MX25_PAD_LD3__LD3 0xe0 - MX25_PAD_LD4__LD4 0xe0 - MX25_PAD_LD5__LD5 0xe0 - MX25_PAD_LD6__LD6 0xe0 - MX25_PAD_LD7__LD7 0xe0 - MX25_PAD_LD8__LD8 0xe0 - MX25_PAD_LD9__LD9 0xe0 - MX25_PAD_LD10__LD10 0xe0 - MX25_PAD_LD11__LD11 0xe0 - MX25_PAD_LD12__LD12 0xe0 - MX25_PAD_LD13__LD13 0xe0 - MX25_PAD_LD14__LD14 0xe0 - MX25_PAD_LD15__LD15 0xe0 - MX25_PAD_GPIO_E__LD16 0xe0 - MX25_PAD_GPIO_F__LD17 0xe0 - MX25_PAD_HSYNC__HSYNC 0xe0 - MX25_PAD_VSYNC__VSYNC 0xe0 - MX25_PAD_LSCLK__LSCLK 0xe0 - MX25_PAD_OE_ACD__OE_ACD 0xe0 - MX25_PAD_CONTRAST__CONTRAST 0xe0 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX25_PAD_UART1_RTS__UART1_RTS 0xe0 - MX25_PAD_UART1_CTS__UART1_CTS 0xe0 - MX25_PAD_UART1_TXD__UART1_TXD 0x80000000 - MX25_PAD_UART1_RXD__UART1_RXD 0xc0 - >; - }; - }; -}; - -&lcdc { - display = <&wvga>; - fsl,lpccr = <0x00a903ff>; - fsl,lscr1 = <0x00120300>; - fsl,dmacr = <0x00020010>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd>; - status = "okay"; -}; - -&nfc { - nand-on-flash-bbt; - status = "okay"; -}; - -&kpp { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_kpp>; - linux,keymap = < - MATRIX_KEY(0x0, 0x0, KEY_UP) - MATRIX_KEY(0x0, 0x1, KEY_DOWN) - MATRIX_KEY(0x0, 0x2, KEY_VOLUMEDOWN) - MATRIX_KEY(0x0, 0x3, KEY_HOME) - MATRIX_KEY(0x1, 0x0, KEY_RIGHT) - MATRIX_KEY(0x1, 0x1, KEY_LEFT) - MATRIX_KEY(0x1, 0x2, KEY_ENTER) - MATRIX_KEY(0x1, 0x3, KEY_VOLUMEUP) - MATRIX_KEY(0x2, 0x0, KEY_F6) - MATRIX_KEY(0x2, 0x1, KEY_F8) - MATRIX_KEY(0x2, 0x2, KEY_F9) - MATRIX_KEY(0x2, 0x3, KEY_F10) - MATRIX_KEY(0x3, 0x0, KEY_F1) - MATRIX_KEY(0x3, 0x1, KEY_F2) - MATRIX_KEY(0x3, 0x2, KEY_F3) - MATRIX_KEY(0x3, 0x2, KEY_POWER) - >; - status = "okay"; -}; - -&ssi1 { - status = "okay"; -}; - -&tsc { - status = "okay"; -}; - -&tscadc { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - uart-has-rtscts; - status = "okay"; -}; - -&usbhost1 { - status = "okay"; -}; - -&usbotg { - external-vbus-divider; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx25-pinfunc.h b/sys/gnu/dts/arm/imx25-pinfunc.h deleted file mode 100644 index f4516ccf2c1..00000000000 --- a/sys/gnu/dts/arm/imx25-pinfunc.h +++ /dev/null @@ -1,628 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2013 Eukréa Electromatique - * Based on imx35-pinfunc.h in the same directory Which is: - * Copyright 2013 Freescale Semiconductor, Inc. - */ - -#ifndef __DTS_IMX25_PINFUNC_H -#define __DTS_IMX25_PINFUNC_H - -/* - * The pin function ID is a tuple of - * - */ - -#define MX25_PAD_A10__A10 0x008 0x000 0x000 0x00 0x000 -#define MX25_PAD_A10__GPIO_4_0 0x008 0x000 0x000 0x05 0x000 - -#define MX25_PAD_A13__A13 0x00c 0x22C 0x000 0x00 0x000 -#define MX25_PAD_A13__GPIO_4_1 0x00c 0x22C 0x000 0x05 0x000 -#define MX25_PAD_A13__LCDC_CLS 0x00c 0x22C 0x000 0x07 0x000 - -#define MX25_PAD_A14__A14 0x010 0x230 0x000 0x00 0x000 -#define MX25_PAD_A14__GPIO_2_0 0x010 0x230 0x000 0x05 0x000 -#define MX25_PAD_A14__SIM1_CLK1 0x010 0x230 0x000 0x06 0x000 -#define MX25_PAD_A14__LCDC_SPL 0x010 0x230 0x000 0x07 0x000 - -#define MX25_PAD_A15__A15 0x014 0x234 0x000 0x00 0x000 -#define MX25_PAD_A15__GPIO_2_1 0x014 0x234 0x000 0x05 0x000 -#define MX25_PAD_A15__SIM1_RST1 0x014 0x234 0x000 0x06 0x000 -#define MX25_PAD_A15__LCDC_PS 0x014 0x234 0x000 0x07 0x000 - -#define MX25_PAD_A16__A16 0x018 0x000 0x000 0x00 0x000 -#define MX25_PAD_A16__GPIO_2_2 0x018 0x000 0x000 0x05 0x000 -#define MX25_PAD_A16__SIM1_VEN1 0x018 0x000 0x000 0x06 0x000 -#define MX25_PAD_A16__LCDC_REV 0x018 0x000 0x000 0x07 0x000 - -#define MX25_PAD_A17__A17 0x01c 0x238 0x000 0x00 0x000 -#define MX25_PAD_A17__GPIO_2_3 0x01c 0x238 0x000 0x05 0x000 -#define MX25_PAD_A17__SIM1_TX 0x01c 0x238 0x554 0x06 0x000 -#define MX25_PAD_A17__FEC_TX_ERR 0x01c 0x238 0x000 0x07 0x000 - -#define MX25_PAD_A18__A18 0x020 0x23c 0x000 0x00 0x000 -#define MX25_PAD_A18__GPIO_2_4 0x020 0x23c 0x000 0x05 0x000 -#define MX25_PAD_A18__SIM1_PD1 0x020 0x23c 0x550 0x06 0x000 -#define MX25_PAD_A18__FEC_COL 0x020 0x23c 0x504 0x07 0x000 - -#define MX25_PAD_A19__A19 0x024 0x240 0x000 0x00 0x000 -#define MX25_PAD_A19__GPIO_2_5 0x024 0x240 0x000 0x05 0x000 -#define MX25_PAD_A19__SIM1_RX1 0x024 0x240 0x54c 0x06 0x000 -#define MX25_PAD_A19__FEC_RX_ERR 0x024 0x240 0x518 0x07 0x000 - -#define MX25_PAD_A20__A20 0x028 0x244 0x000 0x00 0x000 -#define MX25_PAD_A20__GPIO_2_6 0x028 0x244 0x000 0x05 0x000 -#define MX25_PAD_A20__SIM2_CLK1 0x028 0x244 0x000 0x06 0x000 -#define MX25_PAD_A20__FEC_RDATA2 0x028 0x244 0x50c 0x07 0x000 - -#define MX25_PAD_A21__A21 0x02c 0x248 0x000 0x00 0x000 -#define MX25_PAD_A21__GPIO_2_7 0x02c 0x248 0x000 0x05 0x000 -#define MX25_PAD_A21__SIM2_RST1 0x02c 0x248 0x000 0x06 0x000 -#define MX25_PAD_A21__FEC_RDATA3 0x02c 0x248 0x510 0x07 0x000 - -#define MX25_PAD_A22__A22 0x030 0x000 0x000 0x00 0x000 -#define MX25_PAD_A22__GPIO_2_8 0x030 0x000 0x000 0x05 0x000 -#define MX25_PAD_A22__SIM2_VEN1 0x030 0x000 0x000 0x06 0x000 -#define MX25_PAD_A22__FEC_TDATA2 0x030 0x000 0x000 0x07 0x000 - -#define MX25_PAD_A23__A23 0x034 0x24c 0x000 0x00 0x000 -#define MX25_PAD_A23__GPIO_2_9 0x034 0x24c 0x000 0x05 0x000 -#define MX25_PAD_A23__SIM2_TX1 0x034 0x24c 0x560 0x06 0x000 -#define MX25_PAD_A23__FEC_TDATA3 0x034 0x24c 0x000 0x07 0x000 - -#define MX25_PAD_A24__A24 0x038 0x250 0x000 0x00 0x000 -#define MX25_PAD_A24__GPIO_2_10 0x038 0x250 0x000 0x05 0x000 -#define MX25_PAD_A24__SIM2_PD1 0x038 0x250 0x55c 0x06 0x000 -#define MX25_PAD_A24__FEC_RX_CLK 0x038 0x250 0x514 0x07 0x000 - -#define MX25_PAD_A25__A25 0x03c 0x254 0x000 0x00 0x000 -#define MX25_PAD_A25__GPIO_2_11 0x03c 0x254 0x000 0x05 0x000 -#define MX25_PAD_A25__FEC_CRS 0x03c 0x254 0x508 0x07 0x000 - -#define MX25_PAD_EB0__EB0 0x040 0x258 0x000 0x00 0x000 -#define MX25_PAD_EB0__AUD4_TXD 0x040 0x258 0x464 0x04 0x000 -#define MX25_PAD_EB0__GPIO_2_12 0x040 0x258 0x000 0x05 0x000 - -#define MX25_PAD_EB1__EB1 0x044 0x25c 0x000 0x00 0x000 -#define MX25_PAD_EB1__AUD4_RXD 0x044 0x25c 0x460 0x04 0x000 -#define MX25_PAD_EB1__GPIO_2_13 0x044 0x25c 0x000 0x05 0x000 - -#define MX25_PAD_OE__OE 0x048 0x260 0x000 0x00 0x000 -#define MX25_PAD_OE__AUD4_TXC 0x048 0x260 0x000 0x04 0x000 -#define MX25_PAD_OE__GPIO_2_14 0x048 0x260 0x000 0x05 0x000 - -#define MX25_PAD_CS0__CS0 0x04c 0x000 0x000 0x00 0x000 -#define MX25_PAD_CS0__GPIO_4_2 0x04c 0x000 0x000 0x05 0x000 - -#define MX25_PAD_CS1__CS1 0x050 0x000 0x000 0x00 0x000 -#define MX25_PAD_CS1__NF_CE3 0x050 0x000 0x000 0x01 0x000 -#define MX25_PAD_CS1__GPIO_4_3 0x050 0x000 0x000 0x05 0x000 - -#define MX25_PAD_CS4__CS4 0x054 0x264 0x000 0x00 0x000 -#define MX25_PAD_CS4__NF_CE1 0x054 0x264 0x000 0x01 0x000 -#define MX25_PAD_CS4__UART5_CTS 0x054 0x264 0x000 0x03 0x000 -#define MX25_PAD_CS4__GPIO_3_20 0x054 0x264 0x000 0x05 0x000 - -#define MX25_PAD_CS5__CS5 0x058 0x268 0x000 0x00 0x000 -#define MX25_PAD_CS5__NF_CE2 0x058 0x268 0x000 0x01 0x000 -#define MX25_PAD_CS5__UART5_RTS 0x058 0x268 0x574 0x03 0x000 -#define MX25_PAD_CS5__GPIO_3_21 0x058 0x268 0x000 0x05 0x000 - -#define MX25_PAD_NF_CE0__NF_CE0 0x05c 0x26c 0x000 0x00 0x000 -#define MX25_PAD_NF_CE0__GPIO_3_22 0x05c 0x26c 0x000 0x05 0x000 - -#define MX25_PAD_ECB__ECB 0x060 0x270 0x000 0x00 0x000 -#define MX25_PAD_ECB__UART5_TXD 0x060 0x270 0x000 0x03 0x000 -#define MX25_PAD_ECB__GPIO_3_23 0x060 0x270 0x000 0x05 0x000 - -#define MX25_PAD_LBA__LBA 0x064 0x274 0x000 0x00 0x000 -#define MX25_PAD_LBA__UART5_RXD 0x064 0x274 0x578 0x03 0x000 -#define MX25_PAD_LBA__GPIO_3_24 0x064 0x274 0x000 0x05 0x000 - -#define MX25_PAD_BCLK__BCLK 0x068 0x000 0x000 0x00 0x000 -#define MX25_PAD_BCLK__GPIO_4_4 0x068 0x000 0x000 0x05 0x000 - -#define MX25_PAD_RW__RW 0x06c 0x278 0x000 0x00 0x000 -#define MX25_PAD_RW__AUD4_TXFS 0x06c 0x278 0x474 0x04 0x000 -#define MX25_PAD_RW__GPIO_3_25 0x06c 0x278 0x000 0x05 0x000 - -#define MX25_PAD_NFWE_B__NFWE_B 0x070 0x000 0x000 0x00 0x000 -#define MX25_PAD_NFWE_B__GPIO_3_26 0x070 0x000 0x000 0x05 0x000 - -#define MX25_PAD_NFRE_B__NFRE_B 0x074 0x000 0x000 0x00 0x000 -#define MX25_PAD_NFRE_B__GPIO_3_27 0x074 0x000 0x000 0x05 0x000 - -#define MX25_PAD_NFALE__NFALE 0x078 0x000 0x000 0x00 0x000 -#define MX25_PAD_NFALE__GPIO_3_28 0x078 0x000 0x000 0x05 0x000 - -#define MX25_PAD_NFCLE__NFCLE 0x07c 0x000 0x000 0x00 0x000 -#define MX25_PAD_NFCLE__GPIO_3_29 0x07c 0x000 0x000 0x05 0x000 - -#define MX25_PAD_NFWP_B__NFWP_B 0x080 0x000 0x000 0x00 0x000 -#define MX25_PAD_NFWP_B__GPIO_3_30 0x080 0x000 0x000 0x05 0x000 - -#define MX25_PAD_NFRB__NFRB 0x084 0x27c 0x000 0x00 0x000 -#define MX25_PAD_NFRB__GPIO_3_31 0x084 0x27c 0x000 0x05 0x000 - -#define MX25_PAD_D15__D15 0x088 0x280 0x000 0x00 0x000 -#define MX25_PAD_D15__LD16 0x088 0x280 0x000 0x01 0x000 -#define MX25_PAD_D15__GPIO_4_5 0x088 0x280 0x000 0x05 0x000 -#define MX25_PAD_D15__ESDHC1_DAT7 0x088 0x280 0x4d8 0x06 0x000 - -#define MX25_PAD_D14__D14 0x08c 0x284 0x000 0x00 0x000 -#define MX25_PAD_D14__LD17 0x08c 0x284 0x000 0x01 0x000 -#define MX25_PAD_D14__GPIO_4_6 0x08c 0x284 0x000 0x05 0x000 -#define MX25_PAD_D14__ESDHC1_DAT6 0x08c 0x284 0x4d4 0x06 0x000 - -#define MX25_PAD_D13__D13 0x090 0x288 0x000 0x00 0x000 -#define MX25_PAD_D13__LD18 0x090 0x288 0x000 0x01 0x000 -#define MX25_PAD_D13__GPIO_4_7 0x090 0x288 0x000 0x05 0x000 -#define MX25_PAD_D13__ESDHC1_DAT5 0x090 0x288 0x4d0 0x06 0x000 - -#define MX25_PAD_D12__D12 0x094 0x28c 0x000 0x00 0x000 -#define MX25_PAD_D12__GPIO_4_8 0x094 0x28c 0x000 0x05 0x000 -#define MX25_PAD_D12__ESDHC1_DAT4 0x094 0x28c 0x4cc 0x06 0x000 - -#define MX25_PAD_D11__D11 0x098 0x290 0x000 0x00 0x000 -#define MX25_PAD_D11__GPIO_4_9 0x098 0x290 0x000 0x05 0x000 -#define MX25_PAD_D11__USBOTG_PWR 0x098 0x290 0x000 0x06 0x000 - -#define MX25_PAD_D10__D10 0x09c 0x294 0x000 0x00 0x000 -#define MX25_PAD_D10__GPIO_4_10 0x09c 0x294 0x000 0x05 0x000 -#define MX25_PAD_D10__USBOTG_OC 0x09c 0x294 0x57c 0x06 0x000 - -#define MX25_PAD_D9__D9 0x0a0 0x298 0x000 0x00 0x000 -#define MX25_PAD_D9__GPIO_4_11 0x0a0 0x298 0x000 0x05 0x000 -#define MX25_PAD_D9__USBH2_PWR 0x0a0 0x298 0x000 0x06 0x000 - -#define MX25_PAD_D8__D8 0x0a4 0x29c 0x000 0x00 0x000 -#define MX25_PAD_D8__GPIO_4_12 0x0a4 0x29c 0x000 0x05 0x000 -#define MX25_PAD_D8__USBH2_OC 0x0a4 0x29c 0x580 0x06 0x000 - -#define MX25_PAD_D7__D7 0x0a8 0x2a0 0x000 0x00 0x000 -#define MX25_PAD_D7__GPIO_4_13 0x0a8 0x2a0 0x000 0x05 0x000 - -#define MX25_PAD_D6__D6 0x0ac 0x2a4 0x000 0x00 0x000 -#define MX25_PAD_D6__GPIO_4_14 0x0ac 0x2a4 0x000 0x05 0x000 - -#define MX25_PAD_D5__D5 0x0b0 0x2a8 0x000 0x00 0x000 -#define MX25_PAD_D5__GPIO_4_15 0x0b0 0x2a8 0x000 0x05 0x000 - -#define MX25_PAD_D4__D4 0x0b4 0x2ac 0x000 0x00 0x000 -#define MX25_PAD_D4__GPIO_4_16 0x0b4 0x2ac 0x000 0x05 0x000 - -#define MX25_PAD_D3__D3 0x0b8 0x2b0 0x000 0x00 0x000 -#define MX25_PAD_D3__GPIO_4_17 0x0b8 0x2b0 0x000 0x05 0x000 - -#define MX25_PAD_D2__D2 0x0bc 0x2b4 0x000 0x00 0x000 -#define MX25_PAD_D2__GPIO_4_18 0x0bc 0x2b4 0x000 0x05 0x000 - -#define MX25_PAD_D1__D1 0x0c0 0x2b8 0x000 0x00 0x000 -#define MX25_PAD_D1__GPIO_4_19 0x0c0 0x2b8 0x000 0x05 0x000 - -#define MX25_PAD_D0__D0 0x0c4 0x2bc 0x000 0x00 0x000 -#define MX25_PAD_D0__GPIO_4_20 0x0c4 0x2bc 0x000 0x05 0x000 - -#define MX25_PAD_LD0__LD0 0x0c8 0x2c0 0x000 0x00 0x000 -#define MX25_PAD_LD0__CSI_D0 0x0c8 0x2c0 0x488 0x02 0x000 -#define MX25_PAD_LD0__GPIO_2_15 0x0c8 0x2c0 0x000 0x05 0x000 - -#define MX25_PAD_LD1__LD1 0x0cc 0x2c4 0x000 0x00 0x000 -#define MX25_PAD_LD1__CSI_D1 0x0cc 0x2c4 0x48c 0x02 0x000 -#define MX25_PAD_LD1__GPIO_2_16 0x0cc 0x2c4 0x000 0x05 0x000 - -#define MX25_PAD_LD2__LD2 0x0d0 0x2c8 0x000 0x00 0x000 -#define MX25_PAD_LD2__GPIO_2_17 0x0d0 0x2c8 0x000 0x05 0x000 - -#define MX25_PAD_LD3__LD3 0x0d4 0x2cc 0x000 0x00 0x000 -#define MX25_PAD_LD3__GPIO_2_18 0x0d4 0x2cc 0x000 0x05 0x000 - -#define MX25_PAD_LD4__LD4 0x0d8 0x2d0 0x000 0x00 0x000 -#define MX25_PAD_LD4__GPIO_2_19 0x0d8 0x2d0 0x000 0x05 0x000 - -#define MX25_PAD_LD5__LD5 0x0dc 0x2d4 0x000 0x00 0x000 -#define MX25_PAD_LD5__GPIO_1_19 0x0dc 0x2d4 0x000 0x05 0x000 - -#define MX25_PAD_LD6__LD6 0x0e0 0x2d8 0x000 0x00 0x000 -#define MX25_PAD_LD6__GPIO_1_20 0x0e0 0x2d8 0x000 0x05 0x000 - -#define MX25_PAD_LD7__LD7 0x0e4 0x2dc 0x000 0x00 0x000 -#define MX25_PAD_LD7__GPIO_1_21 0x0e4 0x2dc 0x000 0x05 0x000 - -#define MX25_PAD_LD8__LD8 0x0e8 0x2e0 0x000 0x00 0x000 -#define MX25_PAD_LD8__UART4_RXD 0x0e8 0x2e0 0x570 0x02 0x000 -#define MX25_PAD_LD8__FEC_TX_ERR 0x0e8 0x2e0 0x000 0x05 0x000 -/* SION must be set; see the comment for MX25_PAD_SD1_CMD__ESDHC1_CMD. */ -#define MX25_PAD_LD8__ESDHC2_CMD 0x0e8 0x2e0 0x4e0 0x16 0x000 - -#define MX25_PAD_LD9__LD9 0x0ec 0x2e4 0x000 0x00 0x000 -#define MX25_PAD_LD9__UART4_TXD 0x0ec 0x2e4 0x000 0x02 0x000 -#define MX25_PAD_LD9__FEC_COL 0x0ec 0x2e4 0x504 0x05 0x001 -#define MX25_PAD_LD9__ESDHC2_CLK 0x0ec 0x2e4 0x4dc 0x06 0x000 - -#define MX25_PAD_LD10__LD10 0x0f0 0x2e8 0x000 0x00 0x000 -#define MX25_PAD_LD10__UART4_RTS 0x0f0 0x2e8 0x56c 0x02 0x000 -#define MX25_PAD_LD10__FEC_RX_ERR 0x0f0 0x2e8 0x518 0x05 0x001 - -#define MX25_PAD_LD11__LD11 0x0f4 0x2ec 0x000 0x00 0x000 -#define MX25_PAD_LD11__UART4_CTS 0x0f4 0x2ec 0x000 0x02 0x000 -#define MX25_PAD_LD11__FEC_RDATA2 0x0f4 0x2ec 0x50c 0x05 0x001 -#define MX25_PAD_LD11__ESDHC2_DAT1 0x0f4 0x2ec 0x4e8 0x06 0x000 - -#define MX25_PAD_LD12__LD12 0x0f8 0x2f0 0x000 0x00 0x000 -#define MX25_PAD_LD12__CSPI2_MOSI 0x0f8 0x2f0 0x4a0 0x02 0x000 -#define MX25_PAD_LD12__FEC_RDATA3 0x0f8 0x2f0 0x510 0x05 0x001 - -#define MX25_PAD_LD13__LD13 0x0fc 0x2f4 0x000 0x00 0x000 -#define MX25_PAD_LD13__CSPI2_MISO 0x0fc 0x2f4 0x49c 0x02 0x000 -#define MX25_PAD_LD13__FEC_TDATA2 0x0fc 0x2f4 0x000 0x05 0x000 - -#define MX25_PAD_LD14__LD14 0x100 0x2f8 0x000 0x00 0x000 -#define MX25_PAD_LD14__CSPI2_SCLK 0x100 0x2f8 0x494 0x02 0x000 -#define MX25_PAD_LD14__FEC_TDATA3 0x100 0x2f8 0x000 0x05 0x000 - -#define MX25_PAD_LD15__LD15 0x104 0x2fc 0x000 0x00 0x000 -#define MX25_PAD_LD15__CSPI2_RDY 0x104 0x2fc 0x498 0x02 0x000 -#define MX25_PAD_LD15__FEC_RX_CLK 0x104 0x2fc 0x514 0x05 0x001 - -#define MX25_PAD_HSYNC__HSYNC 0x108 0x300 0x000 0x00 0x000 -#define MX25_PAD_HSYNC__GPIO_1_22 0x108 0x300 0x000 0x05 0x000 - -#define MX25_PAD_VSYNC__VSYNC 0x10c 0x304 0x000 0x00 0x000 -#define MX25_PAD_VSYNC__GPIO_1_23 0x10c 0x304 0x000 0x05 0x000 - -#define MX25_PAD_LSCLK__LSCLK 0x110 0x308 0x000 0x00 0x000 -#define MX25_PAD_LSCLK__GPIO_1_24 0x110 0x308 0x000 0x05 0x000 - -#define MX25_PAD_OE_ACD__OE_ACD 0x114 0x30c 0x000 0x00 0x000 -#define MX25_PAD_OE_ACD__CSPI2_SS0 0x114 0x30c 0x4a4 0x02 0x000 -#define MX25_PAD_OE_ACD__GPIO_1_25 0x114 0x30c 0x000 0x05 0x000 - -#define MX25_PAD_CONTRAST__CONTRAST 0x118 0x310 0x000 0x00 0x000 -#define MX25_PAD_CONTRAST__CC4 0x118 0x310 0x000 0x01 0x000 -#define MX25_PAD_CONTRAST__PWM4_PWMO 0x118 0x310 0x000 0x04 0x000 -#define MX25_PAD_CONTRAST__FEC_CRS 0x118 0x310 0x508 0x05 0x001 -#define MX25_PAD_CONTRAST__USBH2_PWR 0x118 0x310 0x000 0x06 0x000 - -#define MX25_PAD_PWM__PWM 0x11c 0x314 0x000 0x00 0x000 -#define MX25_PAD_PWM__GPIO_1_26 0x11c 0x314 0x000 0x05 0x000 -#define MX25_PAD_PWM__USBH2_OC 0x11c 0x314 0x580 0x06 0x001 - -#define MX25_PAD_CSI_D2__CSI_D2 0x120 0x318 0x000 0x00 0x000 -#define MX25_PAD_CSI_D2__UART5_RXD 0x120 0x318 0x578 0x01 0x001 -#define MX25_PAD_CSI_D2__SIM1_CLK0 0x120 0x318 0x000 0x04 0x000 -#define MX25_PAD_CSI_D2__GPIO_1_27 0x120 0x318 0x000 0x05 0x000 -#define MX25_PAD_CSI_D2__CSPI3_MOSI 0x120 0x318 0x000 0x07 0x000 - -#define MX25_PAD_CSI_D3__CSI_D3 0x124 0x31c 0x000 0x00 0x000 -#define MX25_PAD_CSI_D3__UART5_TXD 0x124 0x31c 0x000 0x01 0x000 -#define MX25_PAD_CSI_D3__SIM1_RST0 0x124 0x31c 0x000 0x04 0x000 -#define MX25_PAD_CSI_D3__GPIO_1_28 0x124 0x31c 0x000 0x05 0x000 -#define MX25_PAD_CSI_D3__CSPI3_MISO 0x124 0x31c 0x4b4 0x07 0x001 - -#define MX25_PAD_CSI_D4__CSI_D4 0x128 0x320 0x000 0x00 0x000 -#define MX25_PAD_CSI_D4__UART5_RTS 0x128 0x320 0x574 0x01 0x001 -#define MX25_PAD_CSI_D4__SIM1_VEN0 0x128 0x320 0x000 0x04 0x000 -#define MX25_PAD_CSI_D4__GPIO_1_29 0x128 0x320 0x000 0x05 0x000 -#define MX25_PAD_CSI_D4__CSPI3_SCLK 0x128 0x320 0x000 0x07 0x000 - -#define MX25_PAD_CSI_D5__CSI_D5 0x12c 0x324 0x000 0x00 0x000 -#define MX25_PAD_CSI_D5__UART5_CTS 0x12c 0x324 0x000 0x01 0x000 -#define MX25_PAD_CSI_D5__SIM1_TX0 0x12c 0x324 0x000 0x04 0x000 -#define MX25_PAD_CSI_D5__GPIO_1_30 0x12c 0x324 0x000 0x05 0x000 -#define MX25_PAD_CSI_D5__CSPI3_RDY 0x12c 0x324 0x000 0x07 0x000 - -#define MX25_PAD_CSI_D6__CSI_D6 0x130 0x328 0x000 0x00 0x000 -/* SION must be set; see the comment for MX25_PAD_SD1_CMD__ESDHC1_CMD. */ -#define MX25_PAD_CSI_D6__ESDHC2_CMD 0x130 0x328 0x4e0 0x12 0x001 -#define MX25_PAD_CSI_D6__SIM1_PD0 0x130 0x328 0x000 0x04 0x000 -#define MX25_PAD_CSI_D6__GPIO_1_31 0x130 0x328 0x000 0x05 0x000 - -#define MX25_PAD_CSI_D7__CSI_D7 0x134 0x32c 0x000 0x00 0x000 -#define MX25_PAD_CSI_D7__ESDHC2_CLK 0x134 0x32C 0x4dc 0x02 0x001 -#define MX25_PAD_CSI_D7__GPIO_1_6 0x134 0x32c 0x000 0x05 0x000 - -#define MX25_PAD_CSI_D8__CSI_D8 0x138 0x330 0x000 0x00 0x000 -#define MX25_PAD_CSI_D8__AUD6_RXC 0x138 0x330 0x000 0x02 0x000 -#define MX25_PAD_CSI_D8__GPIO_1_7 0x138 0x330 0x000 0x05 0x000 -#define MX25_PAD_CSI_D8__CSPI3_SS2 0x138 0x330 0x4c4 0x07 0x000 - -#define MX25_PAD_CSI_D9__CSI_D9 0x13c 0x334 0x000 0x00 0x000 -#define MX25_PAD_CSI_D9__AUD6_RXFS 0x13c 0x334 0x000 0x02 0x000 -#define MX25_PAD_CSI_D9__GPIO_4_21 0x13c 0x334 0x000 0x05 0x000 -#define MX25_PAD_CSI_D9__CSPI3_SS3 0x13c 0x334 0x4c8 0x07 0x000 - -#define MX25_PAD_CSI_MCLK__CSI_MCLK 0x140 0x338 0x000 0x00 0x000 -#define MX25_PAD_CSI_MCLK__AUD6_TXD 0x140 0x338 0x000 0x01 0x000 -#define MX25_PAD_CSI_MCLK__ESDHC2_DAT0 0x140 0x338 0x4e4 0x02 0x001 -#define MX25_PAD_CSI_MCLK__GPIO_1_8 0x140 0x338 0x000 0x05 0x000 - -#define MX25_PAD_CSI_VSYNC__CSI_VSYNC 0x144 0x33c 0x000 0x00 0x000 -#define MX25_PAD_CSI_VSYNC__AUD6_RXD 0x144 0x33c 0x000 0x01 0x000 -#define MX25_PAD_CSI_VSYNC__ESDHC2_DAT1 0x144 0x33c 0x4e8 0x02 0x001 -#define MX25_PAD_CSI_VSYNC__GPIO_1_9 0x144 0x33c 0x000 0x05 0x000 - -#define MX25_PAD_CSI_HSYNC__CSI_HSYNC 0x148 0x340 0x000 0x00 0x000 -#define MX25_PAD_CSI_HSYNC__AUD6_TXC 0x148 0x340 0x000 0x01 0x000 -#define MX25_PAD_CSI_HSYNC__ESDHC2_DAT2 0x148 0x340 0x4ec 0x02 0x001 -#define MX25_PAD_CSI_HSYNC__GPIO_1_10 0x148 0x340 0x000 0x05 0x000 - -#define MX25_PAD_CSI_PIXCLK__CSI_PIXCLK 0x14c 0x344 0x000 0x00 0x000 -#define MX25_PAD_CSI_PIXCLK__AUD6_TXFS 0x14c 0x344 0x000 0x01 0x000 -#define MX25_PAD_CSI_PIXCLK__ESDHC2_DAT3 0x14c 0x344 0x4f0 0x02 0x001 -#define MX25_PAD_CSI_PIXCLK__GPIO_1_11 0x14c 0x344 0x000 0x05 0x000 - -#define MX25_PAD_I2C1_CLK__I2C1_CLK 0x150 0x348 0x000 0x00 0x000 -#define MX25_PAD_I2C1_CLK__GPIO_1_12 0x150 0x348 0x000 0x05 0x000 - -#define MX25_PAD_I2C1_DAT__I2C1_DAT 0x154 0x34c 0x000 0x00 0x000 -#define MX25_PAD_I2C1_DAT__GPIO_1_13 0x154 0x34c 0x000 0x05 0x000 - -#define MX25_PAD_CSPI1_MOSI__CSPI1_MOSI 0x158 0x350 0x000 0x00 0x000 -#define MX25_PAD_CSPI1_MOSI__UART3_RXD 0x158 0x350 0x568 0x02 0x000 -#define MX25_PAD_CSPI1_MOSI__GPIO_1_14 0x158 0x350 0x000 0x05 0x000 - -#define MX25_PAD_CSPI1_MISO__CSPI1_MISO 0x15c 0x354 0x000 0x00 0x000 -#define MX25_PAD_CSPI1_MISO__UART3_TXD 0x15c 0x354 0x000 0x02 0x000 -#define MX25_PAD_CSPI1_MISO__GPIO_1_15 0x15c 0x354 0x000 0x05 0x000 - -#define MX25_PAD_CSPI1_SS0__CSPI1_SS0 0x160 0x358 0x000 0x00 0x000 -#define MX25_PAD_CSPI1_SS0__PWM2_PWMO 0x160 0x358 0x000 0x02 0x000 -#define MX25_PAD_CSPI1_SS0__GPIO_1_16 0x160 0x358 0x000 0x05 0x000 - -#define MX25_PAD_CSPI1_SS1__CSPI1_SS1 0x164 0x35c 0x000 0x00 0x000 -#define MX25_PAD_CSPI1_SS1__I2C3_DAT 0x164 0x35C 0x528 0x01 0x001 -#define MX25_PAD_CSPI1_SS1__UART3_RTS 0x164 0x35c 0x000 0x02 0x000 -#define MX25_PAD_CSPI1_SS1__GPIO_1_17 0x164 0x35c 0x000 0x05 0x000 - -#define MX25_PAD_CSPI1_SCLK__CSPI1_SCLK 0x168 0x360 0x000 0x00 0x000 -#define MX25_PAD_CSPI1_SCLK__UART3_CTS 0x168 0x360 0x000 0x02 0x000 -#define MX25_PAD_CSPI1_SCLK__GPIO_1_18 0x168 0x360 0x000 0x05 0x000 - -#define MX25_PAD_CSPI1_RDY__CSPI1_RDY 0x16c 0x364 0x000 0x00 0x000 -#define MX25_PAD_CSPI1_RDY__GPIO_2_22 0x16c 0x364 0x000 0x05 0x000 - -#define MX25_PAD_UART1_RXD__UART1_RXD 0x170 0x368 0x000 0x00 0x000 -#define MX25_PAD_UART1_RXD__UART2_DTR 0x170 0x368 0x000 0x03 0x000 -#define MX25_PAD_UART1_RXD__GPIO_4_22 0x170 0x368 0x000 0x05 0x000 - -#define MX25_PAD_UART1_TXD__UART1_TXD 0x174 0x36c 0x000 0x00 0x000 -#define MX25_PAD_UART1_TXD__UART2_DSR 0x174 0x36c 0x000 0x03 0x000 -#define MX25_PAD_UART1_TXD__GPIO_4_23 0x174 0x36c 0x000 0x05 0x000 - -#define MX25_PAD_UART1_RTS__UART1_RTS 0x178 0x370 0x000 0x00 0x000 -#define MX25_PAD_UART1_RTS__CSI_D0 0x178 0x370 0x488 0x01 0x001 -#define MX25_PAD_UART1_RTS__CC3 0x178 0x370 0x000 0x02 0x000 -#define MX25_PAD_UART1_RTS__UART2_DCD 0x178 0x370 0x000 0x03 0x000 -#define MX25_PAD_UART1_RTS__GPIO_4_24 0x178 0x370 0x000 0x05 0x000 - -#define MX25_PAD_UART1_CTS__UART1_CTS 0x17c 0x374 0x000 0x00 0x000 -#define MX25_PAD_UART1_CTS__CSI_D1 0x17c 0x374 0x48c 0x01 0x001 -#define MX25_PAD_UART1_CTS__UART2_RI 0x17c 0x374 0x000 0x03 0x001 -#define MX25_PAD_UART1_CTS__GPIO_4_25 0x17c 0x374 0x000 0x05 0x000 - -#define MX25_PAD_UART2_RXD__UART2_RXD 0x180 0x378 0x000 0x00 0x000 -#define MX25_PAD_UART2_RXD__GPIO_4_26 0x180 0x378 0x000 0x05 0x000 - -#define MX25_PAD_UART2_TXD__UART2_TXD 0x184 0x37c 0x000 0x00 0x000 -#define MX25_PAD_UART2_TXD__GPIO_4_27 0x184 0x37c 0x000 0x05 0x000 - -#define MX25_PAD_UART2_RTS__UART2_RTS 0x188 0x380 0x000 0x00 0x000 -#define MX25_PAD_UART2_RTS__FEC_COL 0x188 0x380 0x504 0x02 0x002 -#define MX25_PAD_UART2_RTS__CC1 0x188 0x380 0x000 0x03 0x000 -#define MX25_PAD_UART2_RTS__GPIO_4_28 0x188 0x380 0x000 0x05 0x000 - -#define MX25_PAD_UART2_CTS__UART2_CTS 0x18c 0x384 0x000 0x00 0x000 -#define MX25_PAD_UART2_CTS__FEC_RX_ERR 0x18c 0x384 0x518 0x02 0x002 -#define MX25_PAD_UART2_CTS__GPIO_4_29 0x18c 0x384 0x000 0x05 0x000 - -/* - * Removing the SION bit from MX25_PAD_*__ESDHCn_CMD breaks detecting an SD - * card. According to the i.MX25 reference manual (e.g. Figure 23-2 in IMX25RM - * Rev. 2 from 01/2011) this pin is bidirectional. So it seems to be a silicon - * bug that configuring the ESDHCn_CMD function doesn't enable the input path - * for this pin. - * This might have side effects for other hardware units that are connected to - * that pin and use the respective function as input. - */ -#define MX25_PAD_SD1_CMD__ESDHC1_CMD 0x190 0x388 0x000 0x10 0x000 -#define MX25_PAD_SD1_CMD__CSPI2_MOSI 0x190 0x388 0x4a0 0x01 0x001 -#define MX25_PAD_SD1_CMD__FEC_RDATA2 0x190 0x388 0x50c 0x02 0x002 -#define MX25_PAD_SD1_CMD__GPIO_2_23 0x190 0x388 0x000 0x05 0x000 - -#define MX25_PAD_SD1_CLK__ESDHC1_CLK 0x194 0x38c 0x000 0x00 0x000 -#define MX25_PAD_SD1_CLK__CSPI2_MISO 0x194 0x38c 0x49c 0x01 0x001 -#define MX25_PAD_SD1_CLK__FEC_RDATA3 0x194 0x38c 0x510 0x02 0x002 -#define MX25_PAD_SD1_CLK__GPIO_2_24 0x194 0x38c 0x000 0x05 0x000 - -#define MX25_PAD_SD1_DATA0__ESDHC1_DAT0 0x198 0x390 0x000 0x00 0x000 -#define MX25_PAD_SD1_DATA0__CSPI2_SCLK 0x198 0x390 0x494 0x01 0x001 -#define MX25_PAD_SD1_DATA0__GPIO_2_25 0x198 0x390 0x000 0x05 0x000 - -#define MX25_PAD_SD1_DATA1__ESDHC1_DAT1 0x19c 0x394 0x000 0x00 0x000 -#define MX25_PAD_SD1_DATA1__AUD7_RXD 0x19c 0x394 0x478 0x03 0x000 -#define MX25_PAD_SD1_DATA1__GPIO_2_26 0x19c 0x394 0x000 0x05 0x000 - -#define MX25_PAD_SD1_DATA2__ESDHC1_DAT2 0x1a0 0x398 0x000 0x00 0x000 -#define MX25_PAD_SD1_DATA2__FEC_RX_CLK 0x1a0 0x398 0x514 0x02 0x002 -#define MX25_PAD_SD1_DATA2__GPIO_2_27 0x1a0 0x398 0x000 0x05 0x000 - -#define MX25_PAD_SD1_DATA3__ESDHC1_DAT3 0x1a4 0x39c 0x000 0x00 0x000 -#define MX25_PAD_SD1_DATA3__FEC_CRS 0x1a4 0x39c 0x508 0x02 0x002 -#define MX25_PAD_SD1_DATA3__GPIO_2_28 0x1a4 0x39c 0x000 0x05 0x000 - -#define MX25_PAD_KPP_ROW0__KPP_ROW0 0x1a8 0x3a0 0x000 0x00 0x000 -#define MX25_PAD_KPP_ROW0__UART3_RXD 0x1a8 0x3a0 0x568 0x01 0x001 -#define MX25_PAD_KPP_ROW0__UART1_DTR 0x1a8 0x3a0 0x000 0x04 0x000 -#define MX25_PAD_KPP_ROW0__GPIO_2_29 0x1a8 0x3a0 0x000 0x05 0x000 - -#define MX25_PAD_KPP_ROW1__KPP_ROW1 0x1ac 0x3a4 0x000 0x00 0x000 -#define MX25_PAD_KPP_ROW1__UART3_TXD 0x1ac 0x3a4 0x000 0x01 0x000 -#define MX25_PAD_KPP_ROW1__UART1_DSR 0x1ac 0x3a4 0x000 0x04 0x000 -#define MX25_PAD_KPP_ROW1__GPIO_2_30 0x1ac 0x3a4 0x000 0x05 0x000 - -#define MX25_PAD_KPP_ROW2__KPP_ROW2 0x1b0 0x3a8 0x000 0x00 0x000 -#define MX25_PAD_KPP_ROW2__UART3_RTS 0x1b0 0x3a8 0x000 0x01 0x000 -#define MX25_PAD_KPP_ROW2__CSI_D0 0x1b0 0x3a8 0x488 0x03 0x002 -#define MX25_PAD_KPP_ROW2__UART1_DCD 0x1b0 0x3a8 0x000 0x04 0x000 -#define MX25_PAD_KPP_ROW2__GPIO_2_31 0x1b0 0x3a8 0x000 0x05 0x000 - -#define MX25_PAD_KPP_ROW3__KPP_ROW3 0x1b4 0x3ac 0x000 0x00 0x000 -#define MX25_PAD_KPP_ROW3__UART3_CTS 0x1b4 0x3ac 0x000 0x01 0x000 -#define MX25_PAD_KPP_ROW3__CSI_D1 0x1b4 0x3ac 0x48c 0x03 0x002 -#define MX25_PAD_KPP_ROW3__UART1_RI 0x1b4 0x3ac 0x000 0x04 0x000 -#define MX25_PAD_KPP_ROW3__GPIO_3_0 0x1b4 0x3ac 0x000 0x05 0x000 - -#define MX25_PAD_KPP_COL0__KPP_COL0 0x1b8 0x3b0 0x000 0x00 0x000 -#define MX25_PAD_KPP_COL0__UART4_RXD 0x1b8 0x3b0 0x570 0x01 0x001 -#define MX25_PAD_KPP_COL0__AUD5_TXD 0x1b8 0x3b0 0x000 0x02 0x000 -#define MX25_PAD_KPP_COL0__GPIO_3_1 0x1b8 0x3b0 0x000 0x05 0x000 - -#define MX25_PAD_KPP_COL1__KPP_COL1 0x1bc 0x3b4 0x000 0x00 0x000 -#define MX25_PAD_KPP_COL1__UART4_TXD 0x1bc 0x3b4 0x000 0x01 0x000 -#define MX25_PAD_KPP_COL1__AUD5_RXD 0x1bc 0x3b4 0x000 0x02 0x000 -#define MX25_PAD_KPP_COL1__GPIO_3_2 0x1bc 0x3b4 0x000 0x05 0x000 - -#define MX25_PAD_KPP_COL2__KPP_COL2 0x1c0 0x3b8 0x000 0x00 0x000 -#define MX25_PAD_KPP_COL2__UART4_RTS 0x1c0 0x3b8 0x56c 0x01 0x001 -#define MX25_PAD_KPP_COL2__AUD5_TXC 0x1c0 0x3b8 0x000 0x02 0x000 -#define MX25_PAD_KPP_COL2__GPIO_3_3 0x1c0 0x3b8 0x000 0x05 0x000 - -#define MX25_PAD_KPP_COL3__KPP_COL3 0x1c4 0x3bc 0x000 0x00 0x000 -#define MX25_PAD_KPP_COL3__UART4_CTS 0x1c4 0x3bc 0x000 0x01 0x000 -#define MX25_PAD_KPP_COL3__AUD5_TXFS 0x1c4 0x3bc 0x000 0x02 0x000 -#define MX25_PAD_KPP_COL3__GPIO_3_4 0x1c4 0x3bc 0x000 0x05 0x000 - -#define MX25_PAD_FEC_MDC__FEC_MDC 0x1c8 0x3c0 0x000 0x00 0x000 -/* SION must be set; see the comment for MX25_PAD_SD1_CMD__ESDHC1_CMD. */ -#define MX25_PAD_FEC_MDC__ESDHC2_CMD 0x1c8 0x3c0 0x4e0 0x11 0x002 -#define MX25_PAD_FEC_MDC__AUD4_TXD 0x1c8 0x3c0 0x464 0x02 0x001 -#define MX25_PAD_FEC_MDC__GPIO_3_5 0x1c8 0x3c0 0x000 0x05 0x000 - -#define MX25_PAD_FEC_MDIO__FEC_MDIO 0x1cc 0x3c4 0x000 0x00 0x000 -#define MX25_PAD_FEC_MDIO__AUD4_RXD 0x1cc 0x3c4 0x460 0x02 0x001 -#define MX25_PAD_FEC_MDIO__GPIO_3_6 0x1cc 0x3c4 0x000 0x05 0x000 - -#define MX25_PAD_FEC_TDATA0__FEC_TDATA0 0x1d0 0x3c8 0x000 0x00 0x000 -#define MX25_PAD_FEC_TDATA0__GPIO_3_7 0x1d0 0x3c8 0x000 0x05 0x000 - -#define MX25_PAD_FEC_TDATA1__FEC_TDATA1 0x1d4 0x3cc 0x000 0x00 0x000 -#define MX25_PAD_FEC_TDATA1__AUD4_TXFS 0x1d4 0x3cc 0x474 0x02 0x001 -#define MX25_PAD_FEC_TDATA1__GPIO_3_8 0x1d4 0x3cc 0x000 0x05 0x000 - -#define MX25_PAD_FEC_TX_EN__FEC_TX_EN 0x1d8 0x3d0 0x000 0x00 0x000 -#define MX25_PAD_FEC_TX_EN__GPIO_3_9 0x1d8 0x3d0 0x000 0x05 0x000 - -#define MX25_PAD_FEC_RDATA0__FEC_RDATA0 0x1dc 0x3d4 0x000 0x00 0x000 -#define MX25_PAD_FEC_RDATA0__GPIO_3_10 0x1dc 0x3d4 0x000 0x05 0x000 - -#define MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x1e0 0x3d8 0x000 0x00 0x000 -/* - * According to the i.MX25 Reference manual (IMX25RM, Rev. 2, - * 01/2011) this is CAN1_TX but that's wrong. - */ -#define MX25_PAD_FEC_RDATA1__CAN2_TX 0x1e0 0x3d8 0x000 0x04 0x000 -#define MX25_PAD_FEC_RDATA1__GPIO_3_11 0x1e0 0x3d8 0x000 0x05 0x000 - -#define MX25_PAD_FEC_RX_DV__FEC_RX_DV 0x1e4 0x3dc 0x000 0x00 0x000 -/* - * According to the i.MX25 Reference manual (IMX25RM, Rev. 2, - * 01/2011) this is CAN1_RX but that's wrong. - */ -#define MX25_PAD_FEC_RX_DV__CAN2_RX 0x1e4 0x3dc 0x484 0x04 0x000 -#define MX25_PAD_FEC_RX_DV__GPIO_3_12 0x1e4 0x3dc 0x000 0x05 0x000 - -#define MX25_PAD_FEC_TX_CLK__FEC_TX_CLK 0x1e8 0x3e0 0x000 0x00 0x000 -#define MX25_PAD_FEC_TX_CLK__GPIO_3_13 0x1e8 0x3e0 0x000 0x05 0x000 - -#define MX25_PAD_RTCK__RTCK 0x1ec 0x3e4 0x000 0x00 0x000 -#define MX25_PAD_RTCK__OWIRE 0x1ec 0x3e4 0x000 0x01 0x000 -#define MX25_PAD_RTCK__GPIO_3_14 0x1ec 0x3e4 0x000 0x05 0x000 - -#define MX25_PAD_TDO__TDO 0x000 0x3e8 0x000 0x00 0x000 - -#define MX25_PAD_DE_B__DE_B 0x1f0 0x3ec 0x000 0x00 0x000 -#define MX25_PAD_DE_B__GPIO_2_20 0x1f0 0x3ec 0x000 0x05 0x000 - -#define MX25_PAD_GPIO_A__GPIO_A 0x1f4 0x3f0 0x000 0x00 0x000 -#define MX25_PAD_GPIO_A__CAN1_TX 0x1f4 0x3f0 0x000 0x06 0x000 -#define MX25_PAD_GPIO_A__USBOTG_PWR 0x1f4 0x3f0 0x000 0x02 0x000 - -#define MX25_PAD_GPIO_B__GPIO_B 0x1f8 0x3f4 0x000 0x00 0x000 -#define MX25_PAD_GPIO_B__USBOTG_OC 0x1f8 0x3f4 0x57c 0x02 0x001 -#define MX25_PAD_GPIO_B__CAN1_RX 0x1f8 0x3f4 0x480 0x06 0x001 - -#define MX25_PAD_GPIO_C__GPIO_C 0x1fc 0x3f8 0x000 0x00 0x000 -#define MX25_PAD_GPIO_C__PWM4_PWMO 0x1fc 0x3f8 0x000 0x01 0x000 -#define MX25_PAD_GPIO_C__I2C2_SCL 0x1fc 0x3f8 0x51c 0x02 0x001 -#define MX25_PAD_GPIO_C__KPP_COL4 0x1fc 0x3f8 0x52c 0x03 0x001 -#define MX25_PAD_GPIO_C__CAN2_TX 0x1fc 0x3f8 0x000 0x06 0x000 - -#define MX25_PAD_GPIO_D__GPIO_D 0x200 0x3fc 0x000 0x00 0x000 -#define MX25_PAD_GPIO_D__I2C2_SDA 0x200 0x3fc 0x520 0x02 0x001 -#define MX25_PAD_GPIO_D__CAN2_RX 0x200 0x3fc 0x484 0x06 0x001 - -#define MX25_PAD_GPIO_E__GPIO_E 0x204 0x400 0x000 0x00 0x000 -#define MX25_PAD_GPIO_E__I2C3_CLK 0x204 0x400 0x524 0x01 0x002 -#define MX25_PAD_GPIO_E__LD16 0x204 0x400 0x000 0x02 0x000 -#define MX25_PAD_GPIO_E__AUD7_TXD 0x204 0x400 0x000 0x04 0x000 -#define MX25_PAD_GPIO_E__UART4_RXD 0x204 0x400 0x570 0x06 0x002 - -#define MX25_PAD_GPIO_F__GPIO_F 0x208 0x404 0x000 0x00 0x000 -#define MX25_PAD_GPIO_F__LD17 0x208 0x404 0x000 0x02 0x000 -#define MX25_PAD_GPIO_F__AUD7_TXC 0x208 0x404 0x000 0x04 0x000 -#define MX25_PAD_GPIO_F__UART4_TXD 0x208 0x404 0x000 0x06 0x000 - -#define MX25_PAD_EXT_ARMCLK__EXT_ARMCLK 0x20c 0x000 0x000 0x00 0x000 -#define MX25_PAD_EXT_ARMCLK__GPIO_3_15 0x20c 0x000 0x000 0x05 0x000 - -#define MX25_PAD_UPLL_BYPCLK__UPLL_BYPCLK 0x210 0x000 0x000 0x00 0x000 -#define MX25_PAD_UPLL_BYPCLK__GPIO_3_16 0x210 0x000 0x000 0x05 0x000 - -#define MX25_PAD_VSTBY_REQ__VSTBY_REQ 0x214 0x408 0x000 0x00 0x000 -#define MX25_PAD_VSTBY_REQ__AUD7_TXFS 0x214 0x408 0x000 0x04 0x000 -#define MX25_PAD_VSTBY_REQ__GPIO_3_17 0x214 0x408 0x000 0x05 0x000 -#define MX25_PAD_VSTBY_REQ__UART4_RTS 0x214 0x408 0x56c 0x06 0x002 - -#define MX25_PAD_VSTBY_ACK__VSTBY_ACK 0x218 0x40c 0x000 0x00 0x000 -#define MX25_PAD_VSTBY_ACK__GPIO_3_18 0x218 0x40c 0x000 0x05 0x000 - -#define MX25_PAD_POWER_FAIL__POWER_FAIL 0x21c 0x410 0x000 0x00 0x000 -#define MX25_PAD_POWER_FAIL__AUD7_RXD 0x21c 0x410 0x478 0x04 0x001 -#define MX25_PAD_POWER_FAIL__GPIO_3_19 0x21c 0x410 0x000 0x05 0x000 -#define MX25_PAD_POWER_FAIL__UART4_CTS 0x21c 0x410 0x000 0x06 0x000 - -#define MX25_PAD_CLKO__CLKO 0x220 0x414 0x000 0x00 0x000 -#define MX25_PAD_CLKO__GPIO_2_21 0x220 0x414 0x000 0x05 0x000 - -#define MX25_PAD_BOOT_MODE0__BOOT_MODE0 0x224 0x000 0x000 0x00 0x000 -#define MX25_PAD_BOOT_MODE0__GPIO_4_30 0x224 0x000 0x000 0x05 0x000 - -#define MX25_PAD_BOOT_MODE1__BOOT_MODE1 0x228 0x000 0x000 0x00 0x000 -#define MX25_PAD_BOOT_MODE1__GPIO_4_31 0x228 0x000 0x000 0x05 0x000 - -/* - * Compatibility defines for out-of-tree users. You should update if you make - * use of one of them. - */ -#define MX25_PAD_D15__SDHC1_DAT7 MX25_PAD_D15__ESDHC1_DAT7 -#define MX25_PAD_D14__SDHC1_DAT6 MX25_PAD_D14__ESDHC1_DAT6 -#define MX25_PAD_D13__SDHC1_DAT5 MX25_PAD_D13__ESDHC1_DAT5 -#define MX25_PAD_D12__SDHC1_DAT4 MX25_PAD_D12__ESDHC1_DAT4 -#define MX25_PAD_LD8__SDHC2_CMD MX25_PAD_LD8__ESDHC2_CMD -#define MX25_PAD_LD9__SDHC2_CLK MX25_PAD_LD9__ESDHC2_CLK -#define MX25_PAD_LD11__SDHC2_DAT1 MX25_PAD_LD11__ESDHC2_DAT1 -#define MX25_PAD_CSI_D6__SDHC2_CMD MX25_PAD_CSI_D6__ESDHC2_CMD -#define MX25_PAD_CSI_D7__SDHC2_DAT_CLK MX25_PAD_CSI_D7__ESDHC2_CLK -#define MX25_PAD_CSI_MCLK__SDHC2_DAT0 MX25_PAD_CSI_MCLK__ESDHC2_DAT0 -#define MX25_PAD_CSI_VSYNC__SDHC2_DAT1 MX25_PAD_CSI_VSYNC__ESDHC2_DAT1 -#define MX25_PAD_CSI_HSYNC__SDHC2_DAT2 MX25_PAD_CSI_HSYNC__ESDHC2_DAT2 -#define MX25_PAD_CSI_PIXCLK__SDHC2_DAT3 MX25_PAD_CSI_PIXCLK__ESDHC2_DAT3 -#define MX25_PAD_SD1_CMD__SD1_CMD MX25_PAD_SD1_CMD__ESDHC1_CMD -#define MX25_PAD_SD1_CLK__SD1_CLK MX25_PAD_SD1_CLK__ESDHC1_CLK -#define MX25_PAD_SD1_DATA0__SD1_DATA0 MX25_PAD_SD1_DATA0__ESDHC1_DAT0 -#define MX25_PAD_SD1_DATA1__SD1_DATA1 MX25_PAD_SD1_DATA1__ESDHC1_DAT1 -#define MX25_PAD_SD1_DATA2__SD1_DATA2 MX25_PAD_SD1_DATA2__ESDHC1_DAT2 -#define MX25_PAD_SD1_DATA3__SD1_DATA3 MX25_PAD_SD1_DATA3__ESDHC1_DAT3 - -#endif /* __DTS_IMX25_PINFUNC_H */ diff --git a/sys/gnu/dts/arm/imx25.dtsi b/sys/gnu/dts/arm/imx25.dtsi deleted file mode 100644 index 40b95a290bd..00000000000 --- a/sys/gnu/dts/arm/imx25.dtsi +++ /dev/null @@ -1,637 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// -// Copyright 2012 Sascha Hauer, Pengutronix - -#include -#include "imx25-pinfunc.h" - -/ { - #address-cells = <1>; - #size-cells = <1>; - /* - * The decompressor and also some bootloaders rely on a - * pre-existing /chosen node to be available to insert the - * command line and merge other ATAGS info. - */ - chosen {}; - - aliases { - ethernet0 = &fec; - gpio0 = &gpio1; - gpio1 = &gpio2; - gpio2 = &gpio3; - gpio3 = &gpio4; - i2c0 = &i2c1; - i2c1 = &i2c2; - i2c2 = &i2c3; - mmc0 = &esdhc1; - mmc1 = &esdhc2; - pwm0 = &pwm1; - pwm1 = &pwm2; - pwm2 = &pwm3; - pwm3 = &pwm4; - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - serial3 = &uart4; - serial4 = &uart5; - spi0 = &spi1; - spi1 = &spi2; - spi2 = &spi3; - usb0 = &usbotg; - usb1 = &usbhost1; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "arm,arm926ej-s"; - device_type = "cpu"; - reg = <0>; - }; - }; - - asic: asic-interrupt-controller@68000000 { - compatible = "fsl,imx25-asic", "fsl,avic"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x68000000 0x8000000>; - }; - - clocks { - osc { - compatible = "fsl,imx-osc", "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - }; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&asic>; - ranges; - - aips@43f00000 { /* AIPS1 */ - compatible = "fsl,aips-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x43f00000 0x100000>; - ranges; - - aips1: bridge@43f00000 { - compatible = "fsl,imx25-aips"; - reg = <0x43f00000 0x4000>; - }; - - i2c1: i2c@43f80000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx25-i2c", "fsl,imx21-i2c"; - reg = <0x43f80000 0x4000>; - clocks = <&clks 48>; - clock-names = ""; - interrupts = <3>; - status = "disabled"; - }; - - i2c3: i2c@43f84000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx25-i2c", "fsl,imx21-i2c"; - reg = <0x43f84000 0x4000>; - clocks = <&clks 48>; - clock-names = ""; - interrupts = <10>; - status = "disabled"; - }; - - can1: can@43f88000 { - compatible = "fsl,imx25-flexcan"; - reg = <0x43f88000 0x4000>; - interrupts = <43>; - clocks = <&clks 75>, <&clks 75>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - can2: can@43f8c000 { - compatible = "fsl,imx25-flexcan"; - reg = <0x43f8c000 0x4000>; - interrupts = <44>; - clocks = <&clks 76>, <&clks 76>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart1: serial@43f90000 { - compatible = "fsl,imx25-uart", "fsl,imx21-uart"; - reg = <0x43f90000 0x4000>; - interrupts = <45>; - clocks = <&clks 120>, <&clks 57>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart2: serial@43f94000 { - compatible = "fsl,imx25-uart", "fsl,imx21-uart"; - reg = <0x43f94000 0x4000>; - interrupts = <32>; - clocks = <&clks 121>, <&clks 57>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - i2c2: i2c@43f98000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx25-i2c", "fsl,imx21-i2c"; - reg = <0x43f98000 0x4000>; - clocks = <&clks 48>; - clock-names = ""; - interrupts = <4>; - status = "disabled"; - }; - - owire@43f9c000 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x43f9c000 0x4000>; - clocks = <&clks 51>; - clock-names = ""; - interrupts = <2>; - status = "disabled"; - }; - - spi1: spi@43fa4000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx25-cspi", "fsl,imx35-cspi"; - reg = <0x43fa4000 0x4000>; - clocks = <&clks 78>, <&clks 78>; - clock-names = "ipg", "per"; - interrupts = <14>; - status = "disabled"; - }; - - kpp: kpp@43fa8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx25-kpp", "fsl,imx21-kpp"; - reg = <0x43fa8000 0x4000>; - clocks = <&clks 102>; - clock-names = ""; - interrupts = <24>; - status = "disabled"; - }; - - iomuxc: iomuxc@43fac000 { - compatible = "fsl,imx25-iomuxc"; - reg = <0x43fac000 0x4000>; - }; - - audmux: audmux@43fb0000 { - compatible = "fsl,imx25-audmux", "fsl,imx31-audmux"; - reg = <0x43fb0000 0x4000>; - status = "disabled"; - }; - }; - - spba@50000000 { - compatible = "fsl,spba-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x50000000 0x40000>; - ranges; - - spi3: spi@50004000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx25-cspi", "fsl,imx35-cspi"; - reg = <0x50004000 0x4000>; - interrupts = <0>; - clocks = <&clks 80>, <&clks 80>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart4: serial@50008000 { - compatible = "fsl,imx25-uart", "fsl,imx21-uart"; - reg = <0x50008000 0x4000>; - interrupts = <5>; - clocks = <&clks 123>, <&clks 57>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart3: serial@5000c000 { - compatible = "fsl,imx25-uart", "fsl,imx21-uart"; - reg = <0x5000c000 0x4000>; - interrupts = <18>; - clocks = <&clks 122>, <&clks 57>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - spi2: spi@50010000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx25-cspi", "fsl,imx35-cspi"; - reg = <0x50010000 0x4000>; - clocks = <&clks 79>, <&clks 79>; - clock-names = "ipg", "per"; - interrupts = <13>; - status = "disabled"; - }; - - ssi2: ssi@50014000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx25-ssi", "fsl,imx21-ssi"; - reg = <0x50014000 0x4000>; - interrupts = <11>; - clocks = <&clks 118>; - clock-names = "ipg"; - dmas = <&sdma 24 1 0>, - <&sdma 25 1 0>; - dma-names = "rx", "tx"; - fsl,fifo-depth = <15>; - status = "disabled"; - }; - - esai@50018000 { - reg = <0x50018000 0x4000>; - interrupts = <7>; - }; - - uart5: serial@5002c000 { - compatible = "fsl,imx25-uart", "fsl,imx21-uart"; - reg = <0x5002c000 0x4000>; - interrupts = <40>; - clocks = <&clks 124>, <&clks 57>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - tscadc: tscadc@50030000 { - compatible = "fsl,imx25-tsadc"; - reg = <0x50030000 0xc>; - interrupts = <46>; - clocks = <&clks 119>; - clock-names = "ipg"; - interrupt-controller; - #interrupt-cells = <1>; - #address-cells = <1>; - #size-cells = <1>; - status = "disabled"; - ranges; - - adc: adc@50030800 { - compatible = "fsl,imx25-gcq"; - reg = <0x50030800 0x60>; - interrupt-parent = <&tscadc>; - interrupts = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - tsc: tcq@50030400 { - compatible = "fsl,imx25-tcq"; - reg = <0x50030400 0x60>; - interrupt-parent = <&tscadc>; - interrupts = <0>; - fsl,wires = <4>; - status = "disabled"; - }; - }; - - ssi1: ssi@50034000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx25-ssi", "fsl,imx21-ssi"; - reg = <0x50034000 0x4000>; - interrupts = <12>; - clocks = <&clks 117>; - clock-names = "ipg"; - dmas = <&sdma 28 1 0>, - <&sdma 29 1 0>; - dma-names = "rx", "tx"; - fsl,fifo-depth = <15>; - status = "disabled"; - }; - - fec: ethernet@50038000 { - compatible = "fsl,imx25-fec"; - reg = <0x50038000 0x4000>; - interrupts = <57>; - clocks = <&clks 88>, <&clks 65>; - clock-names = "ipg", "ahb"; - status = "disabled"; - }; - }; - - aips@53f00000 { /* AIPS2 */ - compatible = "fsl,aips-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x53f00000 0x100000>; - ranges; - - aips2: bridge@53f00000 { - compatible = "fsl,imx25-aips"; - reg = <0x53f00000 0x4000>; - }; - - clks: ccm@53f80000 { - compatible = "fsl,imx25-ccm"; - reg = <0x53f80000 0x4000>; - interrupts = <31>; - #clock-cells = <1>; - }; - - gpt4: timer@53f84000 { - compatible = "fsl,imx25-gpt", "fsl,imx31-gpt"; - reg = <0x53f84000 0x4000>; - clocks = <&clks 95>, <&clks 47>; - clock-names = "ipg", "per"; - interrupts = <1>; - }; - - gpt3: timer@53f88000 { - compatible = "fsl,imx25-gpt", "fsl,imx31-gpt"; - reg = <0x53f88000 0x4000>; - clocks = <&clks 94>, <&clks 47>; - clock-names = "ipg", "per"; - interrupts = <29>; - }; - - gpt2: timer@53f8c000 { - compatible = "fsl,imx25-gpt", "fsl,imx31-gpt"; - reg = <0x53f8c000 0x4000>; - clocks = <&clks 93>, <&clks 47>; - clock-names = "ipg", "per"; - interrupts = <53>; - }; - - gpt1: timer@53f90000 { - compatible = "fsl,imx25-gpt", "fsl,imx31-gpt"; - reg = <0x53f90000 0x4000>; - clocks = <&clks 92>, <&clks 47>; - clock-names = "ipg", "per"; - interrupts = <54>; - }; - - epit1: timer@53f94000 { - compatible = "fsl,imx25-epit"; - reg = <0x53f94000 0x4000>; - clocks = <&clks 83>, <&clks 43>; - clock-names = "ipg", "per"; - interrupts = <28>; - }; - - epit2: timer@53f98000 { - compatible = "fsl,imx25-epit"; - reg = <0x53f98000 0x4000>; - clocks = <&clks 84>, <&clks 43>; - clock-names = "ipg", "per"; - interrupts = <27>; - }; - - gpio4: gpio@53f9c000 { - compatible = "fsl,imx25-gpio", "fsl,imx35-gpio"; - reg = <0x53f9c000 0x4000>; - interrupts = <23>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - pwm2: pwm@53fa0000 { - compatible = "fsl,imx25-pwm", "fsl,imx27-pwm"; - #pwm-cells = <2>; - reg = <0x53fa0000 0x4000>; - clocks = <&clks 106>, <&clks 52>; - clock-names = "ipg", "per"; - interrupts = <36>; - }; - - gpio3: gpio@53fa4000 { - compatible = "fsl,imx25-gpio", "fsl,imx35-gpio"; - reg = <0x53fa4000 0x4000>; - interrupts = <16>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - pwm3: pwm@53fa8000 { - compatible = "fsl,imx25-pwm", "fsl,imx27-pwm"; - #pwm-cells = <2>; - reg = <0x53fa8000 0x4000>; - clocks = <&clks 107>, <&clks 52>; - clock-names = "ipg", "per"; - interrupts = <41>; - }; - - scc: crypto@53fac000 { - compatible = "fsl,imx25-scc"; - reg = <0x53fac000 0x4000>; - clocks = <&clks 111>; - clock-names = "ipg"; - interrupts = <49>, <50>; - interrupt-names = "scm", "smn"; - }; - - rngb: rngb@53fb0000 { - compatible = "fsl,imx25-rngb"; - reg = <0x53fb0000 0x4000>; - clocks = <&clks 109>; - interrupts = <22>; - }; - - esdhc1: esdhc@53fb4000 { - compatible = "fsl,imx25-esdhc"; - reg = <0x53fb4000 0x4000>; - interrupts = <9>; - clocks = <&clks 86>, <&clks 63>, <&clks 45>; - clock-names = "ipg", "ahb", "per"; - status = "disabled"; - }; - - esdhc2: esdhc@53fb8000 { - compatible = "fsl,imx25-esdhc"; - reg = <0x53fb8000 0x4000>; - interrupts = <8>; - clocks = <&clks 87>, <&clks 64>, <&clks 46>; - clock-names = "ipg", "ahb", "per"; - status = "disabled"; - }; - - lcdc: lcdc@53fbc000 { - compatible = "fsl,imx25-fb", "fsl,imx21-fb"; - reg = <0x53fbc000 0x4000>; - interrupts = <39>; - clocks = <&clks 103>, <&clks 66>, <&clks 49>; - clock-names = "ipg", "ahb", "per"; - status = "disabled"; - }; - - slcdc@53fc0000 { - reg = <0x53fc0000 0x4000>; - interrupts = <38>; - status = "disabled"; - }; - - pwm4: pwm@53fc8000 { - compatible = "fsl,imx25-pwm", "fsl,imx27-pwm"; - #pwm-cells = <2>; - reg = <0x53fc8000 0x4000>; - clocks = <&clks 108>, <&clks 52>; - clock-names = "ipg", "per"; - interrupts = <42>; - }; - - gpio1: gpio@53fcc000 { - compatible = "fsl,imx25-gpio", "fsl,imx35-gpio"; - reg = <0x53fcc000 0x4000>; - interrupts = <52>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@53fd0000 { - compatible = "fsl,imx25-gpio", "fsl,imx35-gpio"; - reg = <0x53fd0000 0x4000>; - interrupts = <51>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - sdma: sdma@53fd4000 { - compatible = "fsl,imx25-sdma"; - reg = <0x53fd4000 0x4000>; - clocks = <&clks 112>, <&clks 68>; - clock-names = "ipg", "ahb"; - #dma-cells = <3>; - interrupts = <34>; - fsl,sdma-ram-script-name = "imx/sdma/sdma-imx25.bin"; - }; - - wdog@53fdc000 { - compatible = "fsl,imx25-wdt", "fsl,imx21-wdt"; - reg = <0x53fdc000 0x4000>; - clocks = <&clks 126>; - clock-names = ""; - interrupts = <55>; - }; - - pwm1: pwm@53fe0000 { - compatible = "fsl,imx25-pwm", "fsl,imx27-pwm"; - #pwm-cells = <2>; - reg = <0x53fe0000 0x4000>; - clocks = <&clks 105>, <&clks 52>; - clock-names = "ipg", "per"; - interrupts = <26>; - }; - - iim: iim@53ff0000 { - compatible = "fsl,imx25-iim", "fsl,imx27-iim"; - reg = <0x53ff0000 0x4000>; - interrupts = <19>; - clocks = <&clks 99>; - }; - - usbotg: usb@53ff4000 { - compatible = "fsl,imx25-usb", "fsl,imx27-usb"; - reg = <0x53ff4000 0x0200>; - interrupts = <37>; - clocks = <&clks 9>, <&clks 70>, <&clks 8>; - clock-names = "ipg", "ahb", "per"; - fsl,usbmisc = <&usbmisc 0>; - fsl,usbphy = <&usbphy0>; - phy_type = "utmi"; - dr_mode = "otg"; - status = "disabled"; - }; - - usbhost1: usb@53ff4400 { - compatible = "fsl,imx25-usb", "fsl,imx27-usb"; - reg = <0x53ff4400 0x0200>; - interrupts = <35>; - clocks = <&clks 9>, <&clks 70>, <&clks 8>; - clock-names = "ipg", "ahb", "per"; - fsl,usbmisc = <&usbmisc 1>; - fsl,usbphy = <&usbphy1>; - maximum-speed = "full-speed"; - phy_type = "serial"; - dr_mode = "host"; - status = "disabled"; - }; - - usbmisc: usbmisc@53ff4600 { - #index-cells = <1>; - compatible = "fsl,imx25-usbmisc"; - reg = <0x53ff4600 0x00f>; - }; - - dryice@53ffc000 { - compatible = "fsl,imx25-dryice", "fsl,imx25-rtc"; - reg = <0x53ffc000 0x4000>; - clocks = <&clks 81>; - clock-names = "ipg"; - interrupts = <25 56>; - }; - }; - - iram: sram@78000000 { - compatible = "mmio-sram"; - reg = <0x78000000 0x20000>; - }; - - emi@80000000 { - compatible = "fsl,emi-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x80000000 0x3b002000>; - ranges; - - nfc: nand@bb000000 { - #address-cells = <1>; - #size-cells = <1>; - - compatible = "fsl,imx25-nand"; - reg = <0xbb000000 0x2000>; - clocks = <&clks 50>; - clock-names = ""; - interrupts = <33>; - status = "disabled"; - }; - }; - }; - - usbphy { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - usbphy0: usb-phy@0 { - reg = <0>; - compatible = "usb-nop-xceiv"; - #phy-cells = <0>; - }; - - usbphy1: usb-phy@1 { - reg = <1>; - compatible = "usb-nop-xceiv"; - #phy-cells = <0>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/imx27-apf27.dts b/sys/gnu/dts/arm/imx27-apf27.dts deleted file mode 100644 index 745d5d40995..00000000000 --- a/sys/gnu/dts/arm/imx27-apf27.dts +++ /dev/null @@ -1,112 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2012 Philippe Reynes - * Copyright 2012 Armadeus Systems - * - * Based on code which is: Copyright 2012 Sascha Hauer, Pengutronix - */ - -/dts-v1/; -#include "imx27.dtsi" - -/ { - model = "Armadeus Systems APF27 module"; - compatible = "armadeus,imx27-apf27", "fsl,imx27"; - - memory@a0000000 { - device_type = "memory"; - reg = <0xa0000000 0x04000000>; - }; -}; - -&clk_osc26m { - clock-frequency = <0>; -}; - -&iomuxc { - imx27-apf27 { - pinctrl_fec1: fec1grp { - fsl,pins = < - MX27_PAD_SD3_CMD__FEC_TXD0 0x0 - MX27_PAD_SD3_CLK__FEC_TXD1 0x0 - MX27_PAD_ATA_DATA0__FEC_TXD2 0x0 - MX27_PAD_ATA_DATA1__FEC_TXD3 0x0 - MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0 - MX27_PAD_ATA_DATA3__FEC_RXD1 0x0 - MX27_PAD_ATA_DATA4__FEC_RXD2 0x0 - MX27_PAD_ATA_DATA5__FEC_RXD3 0x0 - MX27_PAD_ATA_DATA6__FEC_MDIO 0x0 - MX27_PAD_ATA_DATA7__FEC_MDC 0x0 - MX27_PAD_ATA_DATA8__FEC_CRS 0x0 - MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0 - MX27_PAD_ATA_DATA10__FEC_RXD0 0x0 - MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0 - MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0 - MX27_PAD_ATA_DATA13__FEC_COL 0x0 - MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0 - MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX27_PAD_UART1_TXD__UART1_TXD 0x0 - MX27_PAD_UART1_RXD__UART1_RXD 0x0 - >; - }; - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - status = "okay"; -}; - -&nfc { - status = "okay"; - nand-bus-width = <16>; - nand-ecc-mode = "hw"; - nand-on-flash-bbt; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x100000>; - }; - - partition@100000 { - label = "env"; - reg = <0x100000 0x80000>; - }; - - partition@180000 { - label = "env2"; - reg = <0x180000 0x80000>; - }; - - partition@200000 { - label = "firmware"; - reg = <0x200000 0x80000>; - }; - - partition@280000 { - label = "dtb"; - reg = <0x280000 0x80000>; - }; - - partition@300000 { - label = "kernel"; - reg = <0x300000 0x500000>; - }; - - partition@800000 { - label = "rootfs"; - reg = <0x800000 0xf800000>; - }; -}; diff --git a/sys/gnu/dts/arm/imx27-apf27dev.dts b/sys/gnu/dts/arm/imx27-apf27dev.dts deleted file mode 100644 index 6f1e8ce9e76..00000000000 --- a/sys/gnu/dts/arm/imx27-apf27dev.dts +++ /dev/null @@ -1,256 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Armadeus Systems - - */ - -/* APF27Dev is a docking board for the APF27 SOM */ -#include "imx27-apf27.dts" - -/ { - model = "Armadeus Systems APF27Dev docking/development board"; - compatible = "armadeus,imx27-apf27dev", "armadeus,imx27-apf27", "fsl,imx27"; - - display: display { - model = "Chimei-LW700AT9003"; - bits-per-pixel = <16>; /* non-standard but required */ - fsl,pcr = <0xfae80083>; /* non-standard but required */ - display-timings { - native-mode = <&timing0>; - timing0: 800x480 { - clock-frequency = <33000033>; - hactive = <800>; - vactive = <480>; - hback-porch = <96>; - hfront-porch = <96>; - vback-porch = <20>; - vfront-porch = <21>; - hsync-len = <64>; - vsync-len = <4>; - }; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_keys>; - - user-key { - label = "user"; - gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>; - linux,code = <276>; /* BTN_EXTRA */ - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - user { - label = "Heartbeat"; - gpios = <&gpio6 14 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_max5821: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "max5821-reg"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - }; -}; - -&cspi1 { - cs-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_cspi1 &pinctrl_cspi1_cs>; - status = "okay"; - - adc@0 { - compatible = "maxim,max1027"; - reg = <0>; - interrupt-parent = <&gpio5>; - interrupts = <15 IRQ_TYPE_EDGE_FALLING>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_max1027>; - spi-max-frequency = <10000000>; - }; -}; - -&cspi2 { - cs-gpios = <&gpio4 21 GPIO_ACTIVE_LOW>, - <&gpio4 27 GPIO_ACTIVE_LOW>, - <&gpio2 17 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_cspi2 &pinctrl_cspi2_cs>; - status = "okay"; -}; - -&fb { - display = <&display>; - fsl,dmacr = <0x00020010>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_imxfb1>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - rtc@68 { - compatible = "dallas,ds1374"; - reg = <0x68>; - }; - - max5821@38 { - compatible = "maxim,max5821"; - reg = <0x38>; - vref-supply = <®_max5821>; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&iomuxc { - imx27-apf27dev { - pinctrl_cspi1: cspi1grp { - fsl,pins = < - MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x0 - MX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x0 - MX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x0 - >; - }; - - pinctrl_cspi1_cs: cspi1csgrp { - fsl,pins = ; - }; - - pinctrl_cspi2: cspi2grp { - fsl,pins = < - MX27_PAD_CSPI2_MISO__CSPI2_MISO 0x0 - MX27_PAD_CSPI2_MOSI__CSPI2_MOSI 0x0 - MX27_PAD_CSPI2_SCLK__CSPI2_SCLK 0x0 - >; - }; - - pinctrl_cspi2_cs: cspi2csgrp { - fsl,pins = < - MX27_PAD_CSI_D5__GPIO2_17 0x0 - MX27_PAD_CSPI2_SS0__GPIO4_21 0x0 - MX27_PAD_CSPI1_SS1__GPIO4_27 0x0 - >; - }; - - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = ; - }; - - pinctrl_gpio_keys: gpiokeysgrp { - fsl,pins = ; - }; - - pinctrl_imxfb1: imxfbgrp { - fsl,pins = < - MX27_PAD_CLS__CLS 0x0 - MX27_PAD_CONTRAST__CONTRAST 0x0 - MX27_PAD_LD0__LD0 0x0 - MX27_PAD_LD1__LD1 0x0 - MX27_PAD_LD2__LD2 0x0 - MX27_PAD_LD3__LD3 0x0 - MX27_PAD_LD4__LD4 0x0 - MX27_PAD_LD5__LD5 0x0 - MX27_PAD_LD6__LD6 0x0 - MX27_PAD_LD7__LD7 0x0 - MX27_PAD_LD8__LD8 0x0 - MX27_PAD_LD9__LD9 0x0 - MX27_PAD_LD10__LD10 0x0 - MX27_PAD_LD11__LD11 0x0 - MX27_PAD_LD12__LD12 0x0 - MX27_PAD_LD13__LD13 0x0 - MX27_PAD_LD14__LD14 0x0 - MX27_PAD_LD15__LD15 0x0 - MX27_PAD_LD16__LD16 0x0 - MX27_PAD_LD17__LD17 0x0 - MX27_PAD_LSCLK__LSCLK 0x0 - MX27_PAD_OE_ACD__OE_ACD 0x0 - MX27_PAD_PS__PS 0x0 - MX27_PAD_REV__REV 0x0 - MX27_PAD_SPL_SPR__SPL_SPR 0x0 - MX27_PAD_HSYNC__HSYNC 0x0 - MX27_PAD_VSYNC__VSYNC 0x0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX27_PAD_I2C_DATA__I2C_DATA 0x0 - MX27_PAD_I2C_CLK__I2C_CLK 0x0 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX27_PAD_I2C2_SDA__I2C2_SDA 0x0 - MX27_PAD_I2C2_SCL__I2C2_SCL 0x0 - >; - }; - - pinctrl_max1027: max1027 { - fsl,pins = < - MX27_PAD_UART1_CTS__GPIO5_14 0x0 /* CNVST */ - MX27_PAD_UART1_RTS__GPIO5_15 0x0 /* EOC */ - >; - }; - - pinctrl_pwm: pwmgrp { - fsl,pins = < - MX27_PAD_PWMO__PWMO 0x0 - >; - }; - - pinctrl_sdhc2: sdhc2grp { - fsl,pins = < - MX27_PAD_SD2_CLK__SD2_CLK 0x0 - MX27_PAD_SD2_CMD__SD2_CMD 0x0 - MX27_PAD_SD2_D0__SD2_D0 0x0 - MX27_PAD_SD2_D1__SD2_D1 0x0 - MX27_PAD_SD2_D2__SD2_D2 0x0 - MX27_PAD_SD2_D3__SD2_D3 0x0 - >; - }; - - pinctrl_sdhc2_cd: sdhc2cdgrp { - fsl,pins = ; - }; - }; -}; - -&sdhci2 { - bus-width = <4>; - cd-gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sdhc2 &pinctrl_sdhc2_cd>; - status = "okay"; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm>; -}; diff --git a/sys/gnu/dts/arm/imx27-eukrea-cpuimx27.dtsi b/sys/gnu/dts/arm/imx27-eukrea-cpuimx27.dtsi deleted file mode 100644 index 74110bbcd9d..00000000000 --- a/sys/gnu/dts/arm/imx27-eukrea-cpuimx27.dtsi +++ /dev/null @@ -1,284 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (C) 2014 Alexander Shiyan - */ - -/dts-v1/; -#include "imx27.dtsi" - -/ { - model = "Eukrea CPUIMX27"; - compatible = "eukrea,cpuimx27", "fsl,imx27"; - - memory@a0000000 { - device_type = "memory"; - reg = <0xa0000000 0x04000000>; - }; - - clk14745600: clk-uart { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <14745600>; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec>; - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pcf8563@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; -}; - -&nfc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nfc>; - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - nand-on-flash-bbt; - status = "okay"; -}; - -&owire { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_owire>; - status = "okay"; -}; - -&sdhci2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sdhc2>; - bus-width = <4>; - non-removable; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - uart-has-rtscts; - status = "okay"; -}; - -&usbh2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh2>; - dr_mode = "host"; - phy_type = "ulpi"; - disable-over-current; - status = "okay"; -}; - -&usbotg { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - dr_mode = "otg"; - phy_type = "ulpi"; - disable-over-current; - status = "okay"; -}; - -&weim { - status = "okay"; - - nor: nor@0,0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "cfi-flash"; - reg = <0 0x00000000 0x04000000>; - bank-width = <2>; - linux,mtd-name = "physmap-flash.0"; - fsl,weim-cs-timing = <0x00008f03 0xa0330d01 0x002208c0>; - }; - - uart8250@3,200000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart8250_1>; - compatible = "ns8250"; - clocks = <&clk14745600>; - fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>; - interrupts = <&gpio2 23 IRQ_TYPE_LEVEL_LOW>; - reg = <3 0x200000 0x1000>; - reg-shift = <1>; - reg-io-width = <1>; - no-loopback-test; - }; - - uart8250@3,400000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart8250_2>; - compatible = "ns8250"; - clocks = <&clk14745600>; - fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>; - interrupts = <&gpio2 22 IRQ_TYPE_LEVEL_LOW>; - reg = <3 0x400000 0x1000>; - reg-shift = <1>; - reg-io-width = <1>; - no-loopback-test; - }; - - uart8250@3,800000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart8250_3>; - compatible = "ns8250"; - clocks = <&clk14745600>; - fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>; - interrupts = <&gpio2 27 IRQ_TYPE_LEVEL_LOW>; - reg = <3 0x800000 0x1000>; - reg-shift = <1>; - reg-io-width = <1>; - no-loopback-test; - }; - - uart8250@3,1000000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart8250_4>; - compatible = "ns8250"; - clocks = <&clk14745600>; - fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>; - interrupts = <&gpio2 30 IRQ_TYPE_LEVEL_LOW>; - reg = <3 0x1000000 0x1000>; - reg-shift = <1>; - reg-io-width = <1>; - no-loopback-test; - }; -}; - -&iomuxc { - imx27-eukrea-cpuimx27 { - pinctrl_fec: fecgrp { - fsl,pins = < - MX27_PAD_SD3_CMD__FEC_TXD0 0x0 - MX27_PAD_SD3_CLK__FEC_TXD1 0x0 - MX27_PAD_ATA_DATA0__FEC_TXD2 0x0 - MX27_PAD_ATA_DATA1__FEC_TXD3 0x0 - MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0 - MX27_PAD_ATA_DATA3__FEC_RXD1 0x0 - MX27_PAD_ATA_DATA4__FEC_RXD2 0x0 - MX27_PAD_ATA_DATA5__FEC_RXD3 0x0 - MX27_PAD_ATA_DATA6__FEC_MDIO 0x0 - MX27_PAD_ATA_DATA7__FEC_MDC 0x0 - MX27_PAD_ATA_DATA8__FEC_CRS 0x0 - MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0 - MX27_PAD_ATA_DATA10__FEC_RXD0 0x0 - MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0 - MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0 - MX27_PAD_ATA_DATA13__FEC_COL 0x0 - MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0 - MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX27_PAD_I2C_DATA__I2C_DATA 0x0 - MX27_PAD_I2C_CLK__I2C_CLK 0x0 - >; - }; - - pinctrl_nfc: nfcgrp { - fsl,pins = < - MX27_PAD_NFRB__NFRB 0x0 - MX27_PAD_NFCLE__NFCLE 0x0 - MX27_PAD_NFWP_B__NFWP_B 0x0 - MX27_PAD_NFCE_B__NFCE_B 0x0 - MX27_PAD_NFALE__NFALE 0x0 - MX27_PAD_NFRE_B__NFRE_B 0x0 - MX27_PAD_NFWE_B__NFWE_B 0x0 - >; - }; - - pinctrl_owire: owiregrp { - fsl,pins = < - MX27_PAD_RTCK__OWIRE 0x0 - >; - }; - - pinctrl_sdhc2: sdhc2grp { - fsl,pins = < - MX27_PAD_SD2_CLK__SD2_CLK 0x0 - MX27_PAD_SD2_CMD__SD2_CMD 0x0 - MX27_PAD_SD2_D0__SD2_D0 0x0 - MX27_PAD_SD2_D1__SD2_D1 0x0 - MX27_PAD_SD2_D2__SD2_D2 0x0 - MX27_PAD_SD2_D3__SD2_D3 0x0 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX27_PAD_USBH1_TXDM__UART4_TXD 0x0 - MX27_PAD_USBH1_RXDP__UART4_RXD 0x0 - MX27_PAD_USBH1_TXDP__UART4_CTS 0x0 - MX27_PAD_USBH1_FS__UART4_RTS 0x0 - >; - }; - - pinctrl_uart8250_1: uart82501grp { - fsl,pins = < - MX27_PAD_USB_PWR__GPIO2_23 0x0 - >; - }; - - pinctrl_uart8250_2: uart82502grp { - fsl,pins = < - MX27_PAD_USBH1_SUSP__GPIO2_22 0x0 - >; - }; - - pinctrl_uart8250_3: uart82503grp { - fsl,pins = < - MX27_PAD_USBH1_OE_B__GPIO2_27 0x0 - >; - }; - - pinctrl_uart8250_4: uart82504grp { - fsl,pins = < - MX27_PAD_USBH1_RXDM__GPIO2_30 0x0 - >; - }; - - pinctrl_usbh2: usbh2grp { - fsl,pins = < - MX27_PAD_USBH2_CLK__USBH2_CLK 0x0 - MX27_PAD_USBH2_DIR__USBH2_DIR 0x0 - MX27_PAD_USBH2_NXT__USBH2_NXT 0x0 - MX27_PAD_USBH2_STP__USBH2_STP 0x0 - MX27_PAD_CSPI2_SCLK__USBH2_DATA0 0x0 - MX27_PAD_CSPI2_MOSI__USBH2_DATA1 0x0 - MX27_PAD_CSPI2_MISO__USBH2_DATA2 0x0 - MX27_PAD_CSPI2_SS1__USBH2_DATA3 0x0 - MX27_PAD_CSPI2_SS2__USBH2_DATA4 0x0 - MX27_PAD_CSPI1_SS2__USBH2_DATA5 0x0 - MX27_PAD_CSPI2_SS0__USBH2_DATA6 0x0 - MX27_PAD_USBH2_DATA7__USBH2_DATA7 0x0 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX27_PAD_USBOTG_CLK__USBOTG_CLK 0x0 - MX27_PAD_USBOTG_DIR__USBOTG_DIR 0x0 - MX27_PAD_USBOTG_NXT__USBOTG_NXT 0x0 - MX27_PAD_USBOTG_STP__USBOTG_STP 0x0 - MX27_PAD_USBOTG_DATA0__USBOTG_DATA0 0x0 - MX27_PAD_USBOTG_DATA1__USBOTG_DATA1 0x0 - MX27_PAD_USBOTG_DATA2__USBOTG_DATA2 0x0 - MX27_PAD_USBOTG_DATA3__USBOTG_DATA3 0x0 - MX27_PAD_USBOTG_DATA4__USBOTG_DATA4 0x0 - MX27_PAD_USBOTG_DATA5__USBOTG_DATA5 0x0 - MX27_PAD_USBOTG_DATA6__USBOTG_DATA6 0x0 - MX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x0 - >; - }; - }; -}; diff --git a/sys/gnu/dts/arm/imx27-eukrea-mbimxsd27-baseboard.dts b/sys/gnu/dts/arm/imx27-eukrea-mbimxsd27-baseboard.dts deleted file mode 100644 index 9c3ec82ec7e..00000000000 --- a/sys/gnu/dts/arm/imx27-eukrea-mbimxsd27-baseboard.dts +++ /dev/null @@ -1,266 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (C) 2014 Alexander Shiyan - */ - -#include "imx27-eukrea-cpuimx27.dtsi" - -/ { - model = "Eukrea MBIMXSD27"; - compatible = "eukrea,mbimxsd27-baseboard", "eukrea,cpuimx27", "fsl,imx27"; - - display0: CMO-QVGA { - model = "CMO-QVGA"; - bits-per-pixel = <16>; - fsl,pcr = <0xfad08b80>; - - display-timings { - native-mode = <&timing0>; - timing0: 320x240 { - clock-frequency = <6500000>; - hactive = <320>; - vactive = <240>; - hback-porch = <20>; - hsync-len = <30>; - hfront-porch = <38>; - vback-porch = <4>; - vsync-len = <3>; - vfront-porch = <15>; - }; - }; - }; - - backlight { - compatible = "gpio-backlight"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_backlight>; - gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpioleds>; - - led1 { - label = "system::live"; - gpios = <&gpio6 16 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - }; - - led2 { - label = "system::user"; - gpios = <&gpio6 19 GPIO_ACTIVE_LOW>; - }; - }; - - regulators { - #address-cells = <1>; - #size-cells = <0>; - compatible = "simple-bus"; - - reg_lcd: regulator@0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcdreg>; - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "LCD"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 25 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - }; -}; - -&cspi1 { - pinctrl-0 = <&pinctrl_cspi1>; - cs-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; - status = "okay"; - - ads7846@0 { - compatible = "ti,ads7846"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_touch>; - reg = <0>; - interrupts = <&gpio4 25 IRQ_TYPE_LEVEL_LOW>; - spi-cpol; - spi-max-frequency = <1500000>; - ti,keep-vref-on; - }; -}; - -&fb { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_imxfb>; - display = <&display0>; - lcd-supply = <®_lcd>; - fsl,dmacr = <0x00040060>; - fsl,lscr1 = <0x00120300>; - fsl,lpccr = <0x00a903ff>; - status = "okay"; -}; - -&i2c1 { - codec: codec@1a { - compatible = "ti,tlv320aic23"; - reg = <0x1a>; - }; -}; - -&kpp { - linux,keymap = < - MATRIX_KEY(0, 0, KEY_UP) - MATRIX_KEY(0, 1, KEY_DOWN) - MATRIX_KEY(1, 0, KEY_RIGHT) - MATRIX_KEY(1, 1, KEY_LEFT) - >; - status = "okay"; -}; - -&sdhci1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sdhc1>; - bus-width = <4>; - status = "okay"; -}; - -&ssi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ssi1>; - codec-handle = <&codec>; - status = "okay"; -}; - -&uart1 { - uart-has-rtscts; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - uart-has-rtscts; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart3 { - uart-has-rtscts; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -&iomuxc { - imx27-eukrea-cpuimx27-baseboard { - pinctrl_cspi1: cspi1grp { - fsl,pins = < - MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x0 - MX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x0 - MX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x0 - MX27_PAD_CSPI1_SS0__GPIO4_28 0x0 /* CS0 */ - >; - }; - - pinctrl_backlight: backlightgrp { - fsl,pins = < - MX27_PAD_PWMO__GPIO5_5 0x0 - >; - }; - - pinctrl_gpioleds: gpioledsgrp { - fsl,pins = < - MX27_PAD_PC_PWRON__GPIO6_16 0x0 - MX27_PAD_PC_CD2_B__GPIO6_19 0x0 - >; - }; - - pinctrl_imxfb: imxfbgrp { - fsl,pins = < - MX27_PAD_LD0__LD0 0x0 - MX27_PAD_LD1__LD1 0x0 - MX27_PAD_LD2__LD2 0x0 - MX27_PAD_LD3__LD3 0x0 - MX27_PAD_LD4__LD4 0x0 - MX27_PAD_LD5__LD5 0x0 - MX27_PAD_LD6__LD6 0x0 - MX27_PAD_LD7__LD7 0x0 - MX27_PAD_LD8__LD8 0x0 - MX27_PAD_LD9__LD9 0x0 - MX27_PAD_LD10__LD10 0x0 - MX27_PAD_LD11__LD11 0x0 - MX27_PAD_LD12__LD12 0x0 - MX27_PAD_LD13__LD13 0x0 - MX27_PAD_LD14__LD14 0x0 - MX27_PAD_LD15__LD15 0x0 - MX27_PAD_LD16__LD16 0x0 - MX27_PAD_LD17__LD17 0x0 - MX27_PAD_CONTRAST__CONTRAST 0x0 - MX27_PAD_OE_ACD__OE_ACD 0x0 - MX27_PAD_HSYNC__HSYNC 0x0 - MX27_PAD_VSYNC__VSYNC 0x0 - >; - }; - - pinctrl_lcdreg: lcdreggrp { - fsl,pins = < - MX27_PAD_CLS__GPIO1_25 0x0 - >; - }; - - pinctrl_sdhc1: sdhc1grp { - fsl,pins = < - MX27_PAD_SD1_CLK__SD1_CLK 0x0 - MX27_PAD_SD1_CMD__SD1_CMD 0x0 - MX27_PAD_SD1_D0__SD1_D0 0x0 - MX27_PAD_SD1_D1__SD1_D1 0x0 - MX27_PAD_SD1_D2__SD1_D2 0x0 - MX27_PAD_SD1_D3__SD1_D3 0x0 - >; - }; - - pinctrl_ssi1: ssi1grp { - fsl,pins = < - MX27_PAD_SSI4_CLK__SSI4_CLK 0x0 - MX27_PAD_SSI4_FS__SSI4_FS 0x0 - MX27_PAD_SSI4_RXDAT__SSI4_RXDAT 0x1 - MX27_PAD_SSI4_TXDAT__SSI4_TXDAT 0x1 - >; - }; - - pinctrl_touch: touchgrp { - fsl,pins = < - MX27_PAD_CSPI1_RDY__GPIO4_25 0x0 /* IRQ */ - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX27_PAD_UART1_TXD__UART1_TXD 0x0 - MX27_PAD_UART1_RXD__UART1_RXD 0x0 - MX27_PAD_UART1_CTS__UART1_CTS 0x0 - MX27_PAD_UART1_RTS__UART1_RTS 0x0 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX27_PAD_UART2_TXD__UART2_TXD 0x0 - MX27_PAD_UART2_RXD__UART2_RXD 0x0 - MX27_PAD_UART2_CTS__UART2_CTS 0x0 - MX27_PAD_UART2_RTS__UART2_RTS 0x0 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX27_PAD_UART3_TXD__UART3_TXD 0x0 - MX27_PAD_UART3_RXD__UART3_RXD 0x0 - MX27_PAD_UART3_CTS__UART3_CTS 0x0 - MX27_PAD_UART3_RTS__UART3_RTS 0x0 - >; - }; - }; -}; diff --git a/sys/gnu/dts/arm/imx27-pdk.dts b/sys/gnu/dts/arm/imx27-pdk.dts deleted file mode 100644 index 35123b7cb6b..00000000000 --- a/sys/gnu/dts/arm/imx27-pdk.dts +++ /dev/null @@ -1,191 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// -// Copyright 2012 Sascha Hauer, Pengutronix - -/dts-v1/; -#include "imx27.dtsi" - -/ { - model = "Freescale i.MX27 Product Development Kit"; - compatible = "fsl,imx27-pdk", "fsl,imx27"; - - memory@a0000000 { - device_type = "memory"; - reg = <0xa0000000 0x08000000>; - }; - - usbphy { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - usbphy0: usbphy@0 { - compatible = "usb-nop-xceiv"; - reg = <0>; - clocks = <&clks IMX27_CLK_DUMMY>; - clock-names = "main_clk"; - #phy-cells = <0>; - }; - }; -}; - -&cspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_cspi2>; - cs-gpios = <&gpio4 21 GPIO_ACTIVE_HIGH>; - status = "okay"; - - pmic: mc13783@0 { - compatible = "fsl,mc13783"; - reg = <0>; - spi-cs-high; - spi-max-frequency = <1000000>; - interrupt-parent = <&gpio3>; - interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; - - regulators { - vgen_reg: vgen { - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - }; - - vmmc1_reg: vmmc1 { - regulator-min-microvolt = <1600000>; - regulator-max-microvolt = <3000000>; - }; - - gpo1_reg: gpo1 { - regulator-always-on; - regulator-boot-on; - }; - - gpo3_reg: gpo3 { - regulator-always-on; - regulator-boot-on; - }; - }; - }; -}; - -&fec { - phy-mode = "mii"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec>; - status = "okay"; -}; - -&kpp { - linux,keymap = < - MATRIX_KEY(0, 0, KEY_UP) - MATRIX_KEY(0, 1, KEY_DOWN) - MATRIX_KEY(1, 0, KEY_RIGHT) - MATRIX_KEY(1, 1, KEY_LEFT) - MATRIX_KEY(1, 2, KEY_ENTER) - MATRIX_KEY(2, 0, KEY_F6) - MATRIX_KEY(2, 1, KEY_F8) - MATRIX_KEY(2, 2, KEY_F9) - MATRIX_KEY(2, 3, KEY_F10) - >; - status = "okay"; -}; - -&nfc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nand>; - nand-ecc-mode = "hw"; - nand-on-flash-bbt; - status = "okay"; -}; - -&uart1 { - uart-has-rtscts; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&usbotg { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - dr_mode = "otg"; - fsl,usbphy = <&usbphy0>; - phy_type = "ulpi"; - status = "okay"; -}; - -&iomuxc { - imx27-pdk { - pinctrl_cspi2: cspi2grp { - fsl,pins = < - MX27_PAD_CSPI2_MISO__CSPI2_MISO 0x0 - MX27_PAD_CSPI2_MOSI__CSPI2_MOSI 0x0 - MX27_PAD_CSPI2_SCLK__CSPI2_SCLK 0x0 - MX27_PAD_CSPI2_SS0__GPIO4_21 0x0 /* SPI2 CS0 */ - MX27_PAD_TOUT__GPIO3_14 0x0 /* PMIC IRQ */ - >; - }; - - pinctrl_fec: fecgrp { - fsl,pins = < - MX27_PAD_SD3_CMD__FEC_TXD0 0x0 - MX27_PAD_SD3_CLK__FEC_TXD1 0x0 - MX27_PAD_ATA_DATA0__FEC_TXD2 0x0 - MX27_PAD_ATA_DATA1__FEC_TXD3 0x0 - MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0 - MX27_PAD_ATA_DATA3__FEC_RXD1 0x0 - MX27_PAD_ATA_DATA4__FEC_RXD2 0x0 - MX27_PAD_ATA_DATA5__FEC_RXD3 0x0 - MX27_PAD_ATA_DATA6__FEC_MDIO 0x0 - MX27_PAD_ATA_DATA7__FEC_MDC 0x0 - MX27_PAD_ATA_DATA8__FEC_CRS 0x0 - MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0 - MX27_PAD_ATA_DATA10__FEC_RXD0 0x0 - MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0 - MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0 - MX27_PAD_ATA_DATA13__FEC_COL 0x0 - MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0 - MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0 - >; - }; - - pinctrl_nand: nandgrp { - fsl,pins = < - MX27_PAD_NFRB__NFRB 0x0 - MX27_PAD_NFCLE__NFCLE 0x0 - MX27_PAD_NFWP_B__NFWP_B 0x0 - MX27_PAD_NFCE_B__NFCE_B 0x0 - MX27_PAD_NFALE__NFALE 0x0 - MX27_PAD_NFRE_B__NFRE_B 0x0 - MX27_PAD_NFWE_B__NFWE_B 0x0 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX27_PAD_UART1_TXD__UART1_TXD 0x0 - MX27_PAD_UART1_RXD__UART1_RXD 0x0 - MX27_PAD_UART1_CTS__UART1_CTS 0x0 - MX27_PAD_UART1_RTS__UART1_RTS 0x0 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX27_PAD_USBOTG_NXT__USBOTG_NXT 0x0 - MX27_PAD_USBOTG_STP__USBOTG_STP 0x0 - MX27_PAD_USBOTG_DIR__USBOTG_DIR 0x0 - MX27_PAD_USBOTG_CLK__USBOTG_CLK 0x0 - MX27_PAD_USBOTG_DATA0__USBOTG_DATA0 0x0 - MX27_PAD_USBOTG_DATA1__USBOTG_DATA1 0x0 - MX27_PAD_USBOTG_DATA2__USBOTG_DATA2 0x0 - MX27_PAD_USBOTG_DATA3__USBOTG_DATA3 0x0 - MX27_PAD_USBOTG_DATA4__USBOTG_DATA4 0x0 - MX27_PAD_USBOTG_DATA5__USBOTG_DATA5 0x0 - MX27_PAD_USBOTG_DATA6__USBOTG_DATA6 0x0 - MX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x0 - >; - }; - }; -}; diff --git a/sys/gnu/dts/arm/imx27-phytec-phycard-s-rdk.dts b/sys/gnu/dts/arm/imx27-phytec-phycard-s-rdk.dts deleted file mode 100644 index 0cd75dadf29..00000000000 --- a/sys/gnu/dts/arm/imx27-phytec-phycard-s-rdk.dts +++ /dev/null @@ -1,162 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2012 Markus Pargmann, Pengutronix - */ - -#include "imx27-phytec-phycard-s-som.dtsi" - -/ { - model = "Phytec pca100 rapid development kit"; - compatible = "phytec,imx27-pca100-rdk", "phytec,imx27-pca100", "fsl,imx27"; - - chosen { - stdout-path = &uart1; - }; - - display: display { - model = "Primeview-PD050VL1"; - bits-per-pixel = <16>; /* non-standard but required */ - fsl,pcr = <0xf0c88080>; /* non-standard but required */ - display-timings { - native-mode = <&timing0>; - timing0: 640x480 { - hactive = <640>; - vactive = <480>; - hback-porch = <112>; - hfront-porch = <36>; - hsync-len = <32>; - vback-porch = <33>; - vfront-porch = <33>; - vsync-len = <2>; - clock-frequency = <25000000>; - }; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_3v3: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; -}; - -&fb { - display = <&display>; - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; - - adc@64 { - compatible = "maxim,max1037"; - vcc-supply = <®_3v3>; - reg = <0x64>; - }; -}; - -&iomuxc { - imx27-phycard-s-rdk { - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX27_PAD_I2C2_SDA__I2C2_SDA 0x0 - MX27_PAD_I2C2_SCL__I2C2_SCL 0x0 - >; - }; - - pinctrl_owire1: owire1grp { - fsl,pins = < - MX27_PAD_RTCK__OWIRE 0x0 - >; - }; - - pinctrl_sdhc2: sdhc2grp { - fsl,pins = < - MX27_PAD_SD2_CLK__SD2_CLK 0x0 - MX27_PAD_SD2_CMD__SD2_CMD 0x0 - MX27_PAD_SD2_D0__SD2_D0 0x0 - MX27_PAD_SD2_D1__SD2_D1 0x0 - MX27_PAD_SD2_D2__SD2_D2 0x0 - MX27_PAD_SD2_D3__SD2_D3 0x0 - MX27_PAD_SSI3_RXDAT__GPIO3_29 0x0 /* CD */ - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX27_PAD_UART1_TXD__UART1_TXD 0x0 - MX27_PAD_UART1_RXD__UART1_RXD 0x0 - MX27_PAD_UART1_CTS__UART1_CTS 0x0 - MX27_PAD_UART1_RTS__UART1_RTS 0x0 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX27_PAD_UART2_TXD__UART2_TXD 0x0 - MX27_PAD_UART2_RXD__UART2_RXD 0x0 - MX27_PAD_UART2_CTS__UART2_CTS 0x0 - MX27_PAD_UART2_RTS__UART2_RTS 0x0 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX27_PAD_UART3_TXD__UART3_TXD 0x0 - MX27_PAD_UART3_RXD__UART3_RXD 0x0 - MX27_PAD_UART3_CTS__UART3_CTS 0x0 - MX27_PAD_UART3_RTS__UART3_RTS 0x0 - >; - }; - }; -}; - -&owire { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_owire1>; - status = "okay"; -}; - -&sdhci2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sdhc2>; - cd-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&uart1 { - uart-has-rtscts; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - uart-has-rtscts; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart3 { - uart-has-rtscts; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx27-phytec-phycard-s-som.dtsi b/sys/gnu/dts/arm/imx27-phytec-phycard-s-som.dtsi deleted file mode 100644 index 52c95248e25..00000000000 --- a/sys/gnu/dts/arm/imx27-phytec-phycard-s-som.dtsi +++ /dev/null @@ -1,97 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2012 Sascha Hauer, Uwe Kleine-König, Steffen Trumtrar - * and Markus Pargmann, Pengutronix - */ - -/dts-v1/; -#include "imx27.dtsi" - -/ { - model = "Phytec pca100"; - compatible = "phytec,imx27-pca100", "fsl,imx27"; - - memory@a0000000 { - device_type = "memory"; - reg = <0xa0000000 0x08000000>; /* 128MB */ - }; -}; - -&cspi1 { - cs-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>, - <&gpio4 27 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - status = "okay"; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - at24@52 { - compatible = "atmel,24c32"; - pagesize = <32>; - reg = <0x52>; - }; -}; - -&iomuxc { - imx27-phycard-s-som { - pinctrl_fec1: fec1grp { - fsl,pins = < - MX27_PAD_SD3_CMD__FEC_TXD0 0x0 - MX27_PAD_SD3_CLK__FEC_TXD1 0x0 - MX27_PAD_ATA_DATA0__FEC_TXD2 0x0 - MX27_PAD_ATA_DATA1__FEC_TXD3 0x0 - MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0 - MX27_PAD_ATA_DATA3__FEC_RXD1 0x0 - MX27_PAD_ATA_DATA4__FEC_RXD2 0x0 - MX27_PAD_ATA_DATA5__FEC_RXD3 0x0 - MX27_PAD_ATA_DATA6__FEC_MDIO 0x0 - MX27_PAD_ATA_DATA7__FEC_MDC 0x0 - MX27_PAD_ATA_DATA8__FEC_CRS 0x0 - MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0 - MX27_PAD_ATA_DATA10__FEC_RXD0 0x0 - MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0 - MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0 - MX27_PAD_ATA_DATA13__FEC_COL 0x0 - MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0 - MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX27_PAD_I2C2_SDA__I2C2_SDA 0x0 - MX27_PAD_I2C2_SCL__I2C2_SCL 0x0 - >; - }; - - pinctrl_nfc: nfcgrp { - fsl,pins = < - MX27_PAD_NFRB__NFRB 0x0 - MX27_PAD_NFCLE__NFCLE 0x0 - MX27_PAD_NFWP_B__NFWP_B 0x0 - MX27_PAD_NFCE_B__NFCE_B 0x0 - MX27_PAD_NFALE__NFALE 0x0 - MX27_PAD_NFRE_B__NFRE_B 0x0 - MX27_PAD_NFWE_B__NFWE_B 0x0 - >; - }; - }; -}; - -&nfc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nfc>; - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - nand-on-flash-bbt; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx27-phytec-phycore-rdk.dts b/sys/gnu/dts/arm/imx27-phytec-phycore-rdk.dts deleted file mode 100644 index bf883e45576..00000000000 --- a/sys/gnu/dts/arm/imx27-phytec-phycore-rdk.dts +++ /dev/null @@ -1,319 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - */ - -#include "imx27-phytec-phycore-som.dtsi" - -/ { - model = "Phytec pcm970"; - compatible = "phytec,imx27-pcm970", "phytec,imx27-pcm038", "fsl,imx27"; - - chosen { - stdout-path = &uart1; - }; - - display0: LQ035Q7 { - model = "Sharp-LQ035Q7"; - bits-per-pixel = <16>; - fsl,pcr = <0xf00080c0>; - - display-timings { - native-mode = <&timing0>; - timing0: 240x320 { - clock-frequency = <5500000>; - hactive = <240>; - vactive = <320>; - hback-porch = <5>; - hsync-len = <7>; - hfront-porch = <16>; - vback-porch = <7>; - vsync-len = <1>; - vfront-porch = <9>; - pixelclk-active = <1>; - hsync-active = <1>; - vsync-active = <1>; - de-active = <0>; - }; - }; - }; - - regulators { - regulator@2 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_csien>; - reg = <2>; - regulator-name = "CSI_EN"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 24 GPIO_ACTIVE_LOW>; - regulator-always-on; - }; - }; - - usbphy { - usbphy2: usbphy@2 { - compatible = "usb-nop-xceiv"; - reg = <2>; - vcc-supply = <®_5v0>; - clocks = <&clks IMX27_CLK_DUMMY>; - clock-names = "main_clk"; - #phy-cells = <0>; - }; - }; -}; - -&cspi1 { - pinctrl-0 = <&pinctrl_cspi1>, <&pinctrl_cspi1cs1>; - cs-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>, - <&gpio4 27 GPIO_ACTIVE_LOW>; -}; - -&fb { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_imxfb1>; - display = <&display0>; - lcd-supply = <®_5v0>; - fsl,dmacr = <0x00020010>; - fsl,lscr1 = <0x00120300>; - fsl,lpccr = <0x00a903ff>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - camgpio: pca9536@41 { - compatible = "nxp,pca9536"; - reg = <0x41>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -&iomuxc { - imx27_phycore_rdk { - pinctrl_csien: csiengrp { - fsl,pins = < - MX27_PAD_USB_OC_B__GPIO2_24 0x0 - >; - }; - - pinctrl_cspi1cs1: cspi1cs1grp { - fsl,pins = < - MX27_PAD_CSPI1_SS1__GPIO4_27 0x0 - >; - }; - - pinctrl_imxfb1: imxfbgrp { - fsl,pins = < - MX27_PAD_LD0__LD0 0x0 - MX27_PAD_LD1__LD1 0x0 - MX27_PAD_LD2__LD2 0x0 - MX27_PAD_LD3__LD3 0x0 - MX27_PAD_LD4__LD4 0x0 - MX27_PAD_LD5__LD5 0x0 - MX27_PAD_LD6__LD6 0x0 - MX27_PAD_LD7__LD7 0x0 - MX27_PAD_LD8__LD8 0x0 - MX27_PAD_LD9__LD9 0x0 - MX27_PAD_LD10__LD10 0x0 - MX27_PAD_LD11__LD11 0x0 - MX27_PAD_LD12__LD12 0x0 - MX27_PAD_LD13__LD13 0x0 - MX27_PAD_LD14__LD14 0x0 - MX27_PAD_LD15__LD15 0x0 - MX27_PAD_LD16__LD16 0x0 - MX27_PAD_LD17__LD17 0x0 - MX27_PAD_CLS__CLS 0x0 - MX27_PAD_CONTRAST__CONTRAST 0x0 - MX27_PAD_LSCLK__LSCLK 0x0 - MX27_PAD_OE_ACD__OE_ACD 0x0 - MX27_PAD_PS__PS 0x0 - MX27_PAD_REV__REV 0x0 - MX27_PAD_SPL_SPR__SPL_SPR 0x0 - MX27_PAD_HSYNC__HSYNC 0x0 - MX27_PAD_VSYNC__VSYNC 0x0 - >; - }; - - pinctrl_i2c1: i2c1grp { - /* Add pullup to DATA line */ - fsl,pins = < - MX27_PAD_I2C_DATA__I2C_DATA 0x1 - MX27_PAD_I2C_CLK__I2C_CLK 0x0 - >; - }; - - pinctrl_owire1: owire1grp { - fsl,pins = < - MX27_PAD_RTCK__OWIRE 0x0 - >; - }; - - pinctrl_sdhc2: sdhc2grp { - fsl,pins = < - MX27_PAD_SD2_CLK__SD2_CLK 0x0 - MX27_PAD_SD2_CMD__SD2_CMD 0x0 - MX27_PAD_SD2_D0__SD2_D0 0x0 - MX27_PAD_SD2_D1__SD2_D1 0x0 - MX27_PAD_SD2_D2__SD2_D2 0x0 - MX27_PAD_SD2_D3__SD2_D3 0x0 - MX27_PAD_SSI3_FS__GPIO3_28 0x0 /* WP */ - MX27_PAD_SSI3_RXDAT__GPIO3_29 0x0 /* CD */ - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX27_PAD_UART1_TXD__UART1_TXD 0x0 - MX27_PAD_UART1_RXD__UART1_RXD 0x0 - MX27_PAD_UART1_CTS__UART1_CTS 0x0 - MX27_PAD_UART1_RTS__UART1_RTS 0x0 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX27_PAD_UART2_TXD__UART2_TXD 0x0 - MX27_PAD_UART2_RXD__UART2_RXD 0x0 - MX27_PAD_UART2_CTS__UART2_CTS 0x0 - MX27_PAD_UART2_RTS__UART2_RTS 0x0 - >; - }; - - pinctrl_usbh2: usbh2grp { - fsl,pins = < - MX27_PAD_USBH2_CLK__USBH2_CLK 0x0 - MX27_PAD_USBH2_DIR__USBH2_DIR 0x0 - MX27_PAD_USBH2_NXT__USBH2_NXT 0x0 - MX27_PAD_USBH2_STP__USBH2_STP 0x0 - MX27_PAD_CSPI2_SCLK__USBH2_DATA0 0x0 - MX27_PAD_CSPI2_MOSI__USBH2_DATA1 0x0 - MX27_PAD_CSPI2_MISO__USBH2_DATA2 0x0 - MX27_PAD_CSPI2_SS1__USBH2_DATA3 0x0 - MX27_PAD_CSPI2_SS2__USBH2_DATA4 0x0 - MX27_PAD_CSPI1_SS2__USBH2_DATA5 0x0 - MX27_PAD_CSPI2_SS0__USBH2_DATA6 0x0 - MX27_PAD_USBH2_DATA7__USBH2_DATA7 0x0 - >; - }; - - pinctrl_weim: weimgrp { - fsl,pins = < - MX27_PAD_CS4_B__CS4_B 0x0 /* CS4 */ - MX27_PAD_SD1_D1__GPIO5_19 0x0 /* CAN IRQ */ - >; - }; - }; -}; - -&owire { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_owire1>; - status = "okay"; -}; - -&pmicleds { - ledr1: led@3 { - reg = <3>; - label = "system:red1:user"; - }; - - ledg1: led@4 { - reg = <4>; - label = "system:green1:user"; - }; - - ledb1: led@5 { - reg = <5>; - label = "system:blue1:user"; - }; - - ledr2: led@6 { - reg = <6>; - label = "system:red2:user"; - }; - - ledg2: led@7 { - reg = <7>; - label = "system:green2:user"; - }; - - ledb2: led@8 { - reg = <8>; - label = "system:blue2:user"; - }; - - ledr3: led@9 { - reg = <9>; - label = "system:red3:nand"; - linux,default-trigger = "nand-disk"; - }; - - ledg3: led@10 { - reg = <10>; - label = "system:green3:live"; - linux,default-trigger = "heartbeat"; - }; - - ledb3: led@11 { - reg = <11>; - label = "system:blue3:cpu"; - linux,default-trigger = "cpu0"; - }; -}; - -&sdhci2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sdhc2>; - bus-width = <4>; - cd-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>; - wp-gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>; - vmmc-supply = <&vmmc1_reg>; - status = "okay"; -}; - -&uart1 { - uart-has-rtscts; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - uart-has-rtscts; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&usbh2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh2>; - dr_mode = "host"; - phy_type = "ulpi"; - vbus-supply = <®_5v0>; - fsl,usbphy = <&usbphy2>; - disable-over-current; - status = "okay"; -}; - -&weim { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_weim>; - - can@4,0 { - compatible = "nxp,sja1000"; - reg = <4 0x00000000 0x00000100>; - interrupt-parent = <&gpio5>; - interrupts = <19 IRQ_TYPE_EDGE_FALLING>; - nxp,external-clock-frequency = <16000000>; - nxp,tx-output-config = <0x16>; - nxp,no-comparator-bypass; - fsl,weim-cs-timing = <0x0000dcf6 0x444a0301 0x44443302>; - }; -}; diff --git a/sys/gnu/dts/arm/imx27-phytec-phycore-som.dtsi b/sys/gnu/dts/arm/imx27-phytec-phycore-som.dtsi deleted file mode 100644 index 3d10273177e..00000000000 --- a/sys/gnu/dts/arm/imx27-phytec-phycore-som.dtsi +++ /dev/null @@ -1,344 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2012 Sascha Hauer, Pengutronix - */ - -/dts-v1/; -#include "imx27.dtsi" - -/ { - model = "Phytec pcm038"; - compatible = "phytec,imx27-pcm038", "fsl,imx27"; - - memory@a0000000 { - device_type = "memory"; - reg = <0xa0000000 0x08000000>; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_3v3: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_5v0: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "5V0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - }; - - usbphy { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - usbphy0: usbphy@0 { - compatible = "usb-nop-xceiv"; - reg = <0>; - vcc-supply = <&sw3_reg>; - clocks = <&clks IMX27_CLK_DUMMY>; - clock-names = "main_clk"; - #phy-cells = <0>; - }; - }; -}; - -&audmux { - status = "okay"; - - /* SSI0 <=> PINS_4 (MC13783 Audio) */ - ssi0 { - fsl,audmux-port = <0>; - fsl,port-config = <0xcb205000>; - }; - - pins4 { - fsl,audmux-port = <2>; - fsl,port-config = <0x00001000>; - }; -}; - -&cspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_cspi1>; - cs-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; - status = "okay"; - - pmic: mc13783@0 { - compatible = "fsl,mc13783"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - reg = <0>; - spi-cs-high; - spi-max-frequency = <20000000>; - interrupt-parent = <&gpio2>; - interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; - fsl,mc13xxx-uses-adc; - fsl,mc13xxx-uses-rtc; - - pmicleds: leds { - #address-cells = <1>; - #size-cells = <0>; - led-control = <0x001 0x000 0x000 0x000 0x000 0x000>; - }; - - regulators { - /* SW1A and SW1B joined operation */ - sw1_reg: sw1a { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1520000>; - regulator-always-on; - regulator-boot-on; - }; - - /* SW2A and SW2B joined operation */ - sw2_reg: sw2a { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - sw3_reg: sw3 { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - vaudio_reg: vaudio { - regulator-always-on; - regulator-boot-on; - }; - - violo_reg: violo { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - viohi_reg: viohi { - regulator-always-on; - regulator-boot-on; - }; - - vgen_reg: vgen { - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - }; - - vcam_reg: vcam { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - vrf1_reg: vrf1 { - regulator-min-microvolt = <2775000>; - regulator-max-microvolt = <2775000>; - regulator-always-on; - regulator-boot-on; - }; - - vrf2_reg: vrf2 { - regulator-min-microvolt = <2775000>; - regulator-max-microvolt = <2775000>; - regulator-always-on; - regulator-boot-on; - }; - - vmmc1_reg: vmmc1 { - regulator-min-microvolt = <1600000>; - regulator-max-microvolt = <3000000>; - }; - - gpo1_reg: gpo1 { }; - - pwgt1spi_reg: pwgt1spi { - regulator-always-on; - }; - }; - }; -}; - -&fec { - phy-mode = "mii"; - phy-reset-gpios = <&gpio3 30 GPIO_ACTIVE_LOW>; - phy-supply = <®_3v3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - status = "okay"; -}; - -&i2c2 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - at24@52 { - compatible = "atmel,24c32"; - pagesize = <32>; - reg = <0x52>; - }; - - pcf8563@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; - - lm75@4a { - compatible = "national,lm75"; - reg = <0x4a>; - }; -}; - -&iomuxc { - imx27_phycore_som { - pinctrl_cspi1: cspi1grp { - fsl,pins = < - MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x0 - MX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x0 - MX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x0 - MX27_PAD_CSPI1_SS0__GPIO4_28 0x0 /* SPI1 CS0 */ - >; - }; - - pinctrl_fec1: fec1grp { - fsl,pins = < - MX27_PAD_SD3_CMD__FEC_TXD0 0x0 - MX27_PAD_SD3_CLK__FEC_TXD1 0x0 - MX27_PAD_ATA_DATA0__FEC_TXD2 0x0 - MX27_PAD_ATA_DATA1__FEC_TXD3 0x0 - MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0 - MX27_PAD_ATA_DATA3__FEC_RXD1 0x0 - MX27_PAD_ATA_DATA4__FEC_RXD2 0x0 - MX27_PAD_ATA_DATA5__FEC_RXD3 0x0 - MX27_PAD_ATA_DATA6__FEC_MDIO 0x0 - MX27_PAD_ATA_DATA7__FEC_MDC 0x0 - MX27_PAD_ATA_DATA8__FEC_CRS 0x0 - MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0 - MX27_PAD_ATA_DATA10__FEC_RXD0 0x0 - MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0 - MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0 - MX27_PAD_ATA_DATA13__FEC_COL 0x0 - MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0 - MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0 - MX27_PAD_SSI3_TXDAT__GPIO3_30 0x0 /* FEC RST */ - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX27_PAD_I2C2_SDA__I2C2_SDA 0x0 - MX27_PAD_I2C2_SCL__I2C2_SCL 0x0 - >; - }; - - pinctrl_nfc: nfcgrp { - fsl,pins = < - MX27_PAD_NFRB__NFRB 0x0 - MX27_PAD_NFCLE__NFCLE 0x0 - MX27_PAD_NFWP_B__NFWP_B 0x0 - MX27_PAD_NFCE_B__NFCE_B 0x0 - MX27_PAD_NFALE__NFALE 0x0 - MX27_PAD_NFRE_B__NFRE_B 0x0 - MX27_PAD_NFWE_B__NFWE_B 0x0 - >; - }; - - pinctrl_pmic: pmicgrp { - fsl,pins = < - MX27_PAD_USB_PWR__GPIO2_23 0x0 /* PMIC IRQ */ - >; - }; - - pinctrl_ssi1: ssi1grp { - fsl,pins = < - MX27_PAD_SSI1_FS__SSI1_FS 0x0 - MX27_PAD_SSI1_RXDAT__SSI1_RXDAT 0x0 - MX27_PAD_SSI1_TXDAT__SSI1_TXDAT 0x0 - MX27_PAD_SSI1_CLK__SSI1_CLK 0x0 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX27_PAD_USBOTG_CLK__USBOTG_CLK 0x0 - MX27_PAD_USBOTG_DIR__USBOTG_DIR 0x0 - MX27_PAD_USBOTG_NXT__USBOTG_NXT 0x0 - MX27_PAD_USBOTG_STP__USBOTG_STP 0x0 - MX27_PAD_USBOTG_DATA0__USBOTG_DATA0 0x0 - MX27_PAD_USBOTG_DATA1__USBOTG_DATA1 0x0 - MX27_PAD_USBOTG_DATA2__USBOTG_DATA2 0x0 - MX27_PAD_USBOTG_DATA3__USBOTG_DATA3 0x0 - MX27_PAD_USBOTG_DATA4__USBOTG_DATA4 0x0 - MX27_PAD_USBOTG_DATA5__USBOTG_DATA5 0x0 - MX27_PAD_USBOTG_DATA6__USBOTG_DATA6 0x0 - MX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x0 - >; - }; - }; -}; - -&nfc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nfc>; - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - nand-on-flash-bbt; - status = "okay"; -}; - -&ssi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ssi1>; - status = "okay"; -}; - -&usbotg { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - dr_mode = "otg"; - phy_type = "ulpi"; - fsl,usbphy = <&usbphy0>; - vbus-supply = <&sw3_reg>; - disable-over-current; - status = "okay"; -}; - -&weim { - status = "okay"; - - nor: nor@0,0 { - compatible = "cfi-flash"; - reg = <0 0x00000000 0x02000000>; - bank-width = <2>; - linux,mtd-name = "physmap-flash.0"; - fsl,weim-cs-timing = <0x22c2cf00 0x75000d01 0x00000900>; - #address-cells = <1>; - #size-cells = <1>; - }; - - sram: sram@1,0 { - compatible = "mtd-ram"; - reg = <1 0x00000000 0x00800000>; - bank-width = <2>; - linux,mtd-name = "mtd-ram.0"; - fsl,weim-cs-timing = <0x0000d843 0x22252521 0x22220a00>; - #address-cells = <1>; - #size-cells = <1>; - }; -}; diff --git a/sys/gnu/dts/arm/imx27-pinfunc.h b/sys/gnu/dts/arm/imx27-pinfunc.h deleted file mode 100644 index 1514d80a311..00000000000 --- a/sys/gnu/dts/arm/imx27-pinfunc.h +++ /dev/null @@ -1,474 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright 2013 Markus Pargmann , Pengutronix - */ - -#ifndef __DTS_IMX27_PINFUNC_H -#define __DTS_IMX27_PINFUNC_H - -/* - * The pin function ID is a tuple of - * - * mux_id consists of - * function + (direction << 2) + (gpio_oconf << 4) + (gpio_iconfa << 8) + (gpio_iconfb << 10) - * - * function: 0 - Primary function - * 1 - Alternate function - * 2 - GPIO - * direction: 0 - Input - * 1 - Output - * gpio_oconf: 0 - A_IN - * 1 - B_IN - * 2 - C_IN - * 3 - Data Register - * gpio_iconfa/b: 0 - GPIO_IN - * 1 - Interrupt Status Register - * 2 - 0 - * 3 - 1 - * - * 'pin' is an integer between 0 and 0xbf. imx27 has 6 ports with 32 configurable - * configurable pins each. 'pin' is PORT * 32 + PORT_PIN, PORT_PIN is the pin - * number on the specific port (between 0 and 31). - */ - -#define MX27_PAD_USBH2_CLK__USBH2_CLK 0x00 0x000 -#define MX27_PAD_USBH2_CLK__GPIO1_0 0x00 0x032 -#define MX27_PAD_USBH2_DIR__USBH2_DIR 0x01 0x000 -#define MX27_PAD_USBH2_DIR__GPIO1_1 0x01 0x032 -#define MX27_PAD_USBH2_DATA7__USBH2_DATA7 0x02 0x004 -#define MX27_PAD_USBH2_DATA7__GPIO1_2 0x02 0x032 -#define MX27_PAD_USBH2_NXT__USBH2_NXT 0x03 0x000 -#define MX27_PAD_USBH2_NXT__GPIO1_3 0x03 0x032 -#define MX27_PAD_USBH2_STP__USBH2_STP 0x04 0x004 -#define MX27_PAD_USBH2_STP__GPIO1_4 0x04 0x032 -#define MX27_PAD_LSCLK__LSCLK 0x05 0x004 -#define MX27_PAD_LSCLK__GPIO1_5 0x05 0x032 -#define MX27_PAD_LD0__LD0 0x06 0x004 -#define MX27_PAD_LD0__GPIO1_6 0x06 0x032 -#define MX27_PAD_LD1__LD1 0x07 0x004 -#define MX27_PAD_LD1__GPIO1_7 0x07 0x032 -#define MX27_PAD_LD2__LD2 0x08 0x004 -#define MX27_PAD_LD2__GPIO1_8 0x08 0x032 -#define MX27_PAD_LD3__LD3 0x09 0x004 -#define MX27_PAD_LD3__GPIO1_9 0x09 0x032 -#define MX27_PAD_LD4__LD4 0x0a 0x004 -#define MX27_PAD_LD4__GPIO1_10 0x0a 0x032 -#define MX27_PAD_LD5__LD5 0x0b 0x004 -#define MX27_PAD_LD5__GPIO1_11 0x0b 0x032 -#define MX27_PAD_LD6__LD6 0x0c 0x004 -#define MX27_PAD_LD6__GPIO1_12 0x0c 0x032 -#define MX27_PAD_LD7__LD7 0x0d 0x004 -#define MX27_PAD_LD7__GPIO1_13 0x0d 0x032 -#define MX27_PAD_LD8__LD8 0x0e 0x004 -#define MX27_PAD_LD8__GPIO1_14 0x0e 0x032 -#define MX27_PAD_LD9__LD9 0x0f 0x004 -#define MX27_PAD_LD9__GPIO1_15 0x0f 0x032 -#define MX27_PAD_LD10__LD10 0x10 0x004 -#define MX27_PAD_LD10__GPIO1_16 0x10 0x032 -#define MX27_PAD_LD11__LD11 0x11 0x004 -#define MX27_PAD_LD11__GPIO1_17 0x11 0x032 -#define MX27_PAD_LD12__LD12 0x12 0x004 -#define MX27_PAD_LD12__GPIO1_18 0x12 0x032 -#define MX27_PAD_LD13__LD13 0x13 0x004 -#define MX27_PAD_LD13__GPIO1_19 0x13 0x032 -#define MX27_PAD_LD14__LD14 0x14 0x004 -#define MX27_PAD_LD14__GPIO1_20 0x14 0x032 -#define MX27_PAD_LD15__LD15 0x15 0x004 -#define MX27_PAD_LD15__GPIO1_21 0x15 0x032 -#define MX27_PAD_LD16__LD16 0x16 0x004 -#define MX27_PAD_LD16__GPIO1_22 0x16 0x032 -#define MX27_PAD_LD17__LD17 0x17 0x004 -#define MX27_PAD_LD17__GPIO1_23 0x17 0x032 -#define MX27_PAD_REV__REV 0x18 0x004 -#define MX27_PAD_REV__GPIO1_24 0x18 0x032 -#define MX27_PAD_CLS__CLS 0x19 0x004 -#define MX27_PAD_CLS__GPIO1_25 0x19 0x032 -#define MX27_PAD_PS__PS 0x1a 0x004 -#define MX27_PAD_PS__GPIO1_26 0x1a 0x032 -#define MX27_PAD_SPL_SPR__SPL_SPR 0x1b 0x004 -#define MX27_PAD_SPL_SPR__GPIO1_27 0x1b 0x032 -#define MX27_PAD_HSYNC__HSYNC 0x1c 0x004 -#define MX27_PAD_HSYNC__GPIO1_28 0x1c 0x032 -#define MX27_PAD_VSYNC__VSYNC 0x1d 0x004 -#define MX27_PAD_VSYNC__GPIO1_29 0x1d 0x032 -#define MX27_PAD_CONTRAST__CONTRAST 0x1e 0x004 -#define MX27_PAD_CONTRAST__GPIO1_30 0x1e 0x032 -#define MX27_PAD_OE_ACD__OE_ACD 0x1f 0x004 -#define MX27_PAD_OE_ACD__GPIO1_31 0x1f 0x032 -#define MX27_PAD_SD2_D0__SD2_D0 0x24 0x004 -#define MX27_PAD_SD2_D0__MSHC_DATA0 0x24 0x005 -#define MX27_PAD_SD2_D0__GPIO2_4 0x24 0x032 -#define MX27_PAD_SD2_D1__SD2_D1 0x25 0x004 -#define MX27_PAD_SD2_D1__MSHC_DATA1 0x25 0x005 -#define MX27_PAD_SD2_D1__GPIO2_5 0x25 0x032 -#define MX27_PAD_SD2_D2__SD2_D2 0x26 0x004 -#define MX27_PAD_SD2_D2__MSHC_DATA2 0x26 0x005 -#define MX27_PAD_SD2_D2__GPIO2_6 0x26 0x032 -#define MX27_PAD_SD2_D3__SD2_D3 0x27 0x004 -#define MX27_PAD_SD2_D3__MSHC_DATA3 0x27 0x005 -#define MX27_PAD_SD2_D3__GPIO2_7 0x27 0x032 -#define MX27_PAD_SD2_CMD__SD2_CMD 0x28 0x004 -#define MX27_PAD_SD2_CMD__MSHC_BS 0x28 0x005 -#define MX27_PAD_SD2_CMD__GPIO2_8 0x28 0x032 -#define MX27_PAD_SD2_CLK__SD2_CLK 0x29 0x004 -#define MX27_PAD_SD2_CLK__MSHC_SCLK 0x29 0x005 -#define MX27_PAD_SD2_CLK__GPIO2_9 0x29 0x032 -#define MX27_PAD_CSI_D0__CSI_D0 0x2a 0x000 -#define MX27_PAD_CSI_D0__UART6_TXD 0x2a 0x005 -#define MX27_PAD_CSI_D0__GPIO2_10 0x2a 0x032 -#define MX27_PAD_CSI_D1__CSI_D1 0x2b 0x000 -#define MX27_PAD_CSI_D1__UART6_RXD 0x2b 0x001 -#define MX27_PAD_CSI_D1__GPIO2_11 0x2b 0x032 -#define MX27_PAD_CSI_D2__CSI_D2 0x2c 0x000 -#define MX27_PAD_CSI_D2__UART6_CTS 0x2c 0x005 -#define MX27_PAD_CSI_D2__GPIO2_12 0x2c 0x032 -#define MX27_PAD_CSI_D3__CSI_D3 0x2d 0x000 -#define MX27_PAD_CSI_D3__UART6_RTS 0x2d 0x001 -#define MX27_PAD_CSI_D3__GPIO2_13 0x2d 0x032 -#define MX27_PAD_CSI_D4__CSI_D4 0x2e 0x000 -#define MX27_PAD_CSI_D4__GPIO2_14 0x2e 0x032 -#define MX27_PAD_CSI_MCLK__CSI_MCLK 0x2f 0x004 -#define MX27_PAD_CSI_MCLK__GPIO2_15 0x2f 0x032 -#define MX27_PAD_CSI_PIXCLK__CSI_PIXCLK 0x30 0x000 -#define MX27_PAD_CSI_PIXCLK__GPIO2_16 0x30 0x032 -#define MX27_PAD_CSI_D5__CSI_D5 0x31 0x000 -#define MX27_PAD_CSI_D5__GPIO2_17 0x31 0x032 -#define MX27_PAD_CSI_D6__CSI_D6 0x32 0x000 -#define MX27_PAD_CSI_D6__UART5_TXD 0x32 0x005 -#define MX27_PAD_CSI_D6__GPIO2_18 0x32 0x032 -#define MX27_PAD_CSI_D7__CSI_D7 0x33 0x000 -#define MX27_PAD_CSI_D7__UART5_RXD 0x33 0x001 -#define MX27_PAD_CSI_D7__GPIO2_19 0x33 0x032 -#define MX27_PAD_CSI_VSYNC__CSI_VSYNC 0x34 0x000 -#define MX27_PAD_CSI_VSYNC__UART5_CTS 0x34 0x005 -#define MX27_PAD_CSI_VSYNC__GPIO2_20 0x34 0x032 -#define MX27_PAD_CSI_HSYNC__CSI_HSYNC 0x35 0x000 -#define MX27_PAD_CSI_HSYNC__UART5_RTS 0x35 0x001 -#define MX27_PAD_CSI_HSYNC__GPIO2_21 0x35 0x032 -#define MX27_PAD_USBH1_SUSP__USBH1_SUSP 0x36 0x004 -#define MX27_PAD_USBH1_SUSP__GPIO2_22 0x36 0x032 -#define MX27_PAD_USB_PWR__USB_PWR 0x37 0x004 -#define MX27_PAD_USB_PWR__GPIO2_23 0x37 0x032 -#define MX27_PAD_USB_OC_B__USB_OC_B 0x38 0x000 -#define MX27_PAD_USB_OC_B__GPIO2_24 0x38 0x032 -#define MX27_PAD_USBH1_RCV__USBH1_RCV 0x39 0x004 -#define MX27_PAD_USBH1_RCV__GPIO2_25 0x39 0x032 -#define MX27_PAD_USBH1_FS__USBH1_FS 0x3a 0x004 -#define MX27_PAD_USBH1_FS__UART4_RTS 0x3a 0x001 -#define MX27_PAD_USBH1_FS__GPIO2_26 0x3a 0x032 -#define MX27_PAD_USBH1_OE_B__USBH1_OE_B 0x3b 0x004 -#define MX27_PAD_USBH1_OE_B__GPIO2_27 0x3b 0x032 -#define MX27_PAD_USBH1_TXDM__USBH1_TXDM 0x3c 0x004 -#define MX27_PAD_USBH1_TXDM__UART4_TXD 0x3c 0x005 -#define MX27_PAD_USBH1_TXDM__GPIO2_28 0x3c 0x032 -#define MX27_PAD_USBH1_TXDP__USBH1_TXDP 0x3d 0x004 -#define MX27_PAD_USBH1_TXDP__UART4_CTS 0x3d 0x005 -#define MX27_PAD_USBH1_TXDP__GPIO2_29 0x3d 0x032 -#define MX27_PAD_USBH1_RXDM__USBH1_RXDM 0x3e 0x004 -#define MX27_PAD_USBH1_RXDM__GPIO2_30 0x3e 0x032 -#define MX27_PAD_USBH1_RXDP__USBH1_RXDP 0x3f 0x004 -#define MX27_PAD_USBH1_RXDP__UART4_RXD 0x3f 0x001 -#define MX27_PAD_USBH1_RXDP__GPIO2_31 0x3f 0x032 -#define MX27_PAD_I2C2_SDA__I2C2_SDA 0x45 0x004 -#define MX27_PAD_I2C2_SDA__GPIO3_5 0x45 0x032 -#define MX27_PAD_I2C2_SCL__I2C2_SCL 0x46 0x004 -#define MX27_PAD_I2C2_SCL__GPIO3_6 0x46 0x032 -#define MX27_PAD_USBOTG_DATA5__USBOTG_DATA5 0x47 0x004 -#define MX27_PAD_USBOTG_DATA5__GPIO3_7 0x47 0x032 -#define MX27_PAD_USBOTG_DATA6__USBOTG_DATA6 0x48 0x004 -#define MX27_PAD_USBOTG_DATA6__GPIO3_8 0x48 0x032 -#define MX27_PAD_USBOTG_DATA0__USBOTG_DATA0 0x49 0x004 -#define MX27_PAD_USBOTG_DATA0__GPIO3_9 0x49 0x032 -#define MX27_PAD_USBOTG_DATA2__USBOTG_DATA2 0x4a 0x004 -#define MX27_PAD_USBOTG_DATA2__GPIO3_10 0x4a 0x032 -#define MX27_PAD_USBOTG_DATA1__USBOTG_DATA1 0x4b 0x004 -#define MX27_PAD_USBOTG_DATA1__GPIO3_11 0x4b 0x032 -#define MX27_PAD_USBOTG_DATA4__USBOTG_DATA4 0x4c 0x004 -#define MX27_PAD_USBOTG_DATA4__GPIO3_12 0x4c 0x032 -#define MX27_PAD_USBOTG_DATA3__USBOTG_DATA3 0x4d 0x004 -#define MX27_PAD_USBOTG_DATA3__GPIO3_13 0x4d 0x032 -#define MX27_PAD_TOUT__TOUT 0x4e 0x004 -#define MX27_PAD_TOUT__GPIO3_14 0x4e 0x032 -#define MX27_PAD_TIN__TIN 0x4f 0x000 -#define MX27_PAD_TIN__GPIO3_15 0x4f 0x032 -#define MX27_PAD_SSI4_FS__SSI4_FS 0x50 0x004 -#define MX27_PAD_SSI4_FS__GPIO3_16 0x50 0x032 -#define MX27_PAD_SSI4_RXDAT__SSI4_RXDAT 0x51 0x004 -#define MX27_PAD_SSI4_RXDAT__GPIO3_17 0x51 0x032 -#define MX27_PAD_SSI4_TXDAT__SSI4_TXDAT 0x52 0x004 -#define MX27_PAD_SSI4_TXDAT__GPIO3_18 0x52 0x032 -#define MX27_PAD_SSI4_CLK__SSI4_CLK 0x53 0x004 -#define MX27_PAD_SSI4_CLK__GPIO3_19 0x53 0x032 -#define MX27_PAD_SSI1_FS__SSI1_FS 0x54 0x004 -#define MX27_PAD_SSI1_FS__GPIO3_20 0x54 0x032 -#define MX27_PAD_SSI1_RXDAT__SSI1_RXDAT 0x55 0x004 -#define MX27_PAD_SSI1_RXDAT__GPIO3_21 0x55 0x032 -#define MX27_PAD_SSI1_TXDAT__SSI1_TXDAT 0x56 0x004 -#define MX27_PAD_SSI1_TXDAT__GPIO3_22 0x56 0x032 -#define MX27_PAD_SSI1_CLK__SSI1_CLK 0x57 0x004 -#define MX27_PAD_SSI1_CLK__GPIO3_23 0x57 0x032 -#define MX27_PAD_SSI2_FS__SSI2_FS 0x58 0x004 -#define MX27_PAD_SSI2_FS__GPT5_TOUT 0x58 0x005 -#define MX27_PAD_SSI2_FS__GPIO3_24 0x58 0x032 -#define MX27_PAD_SSI2_RXDAT__SSI2_RXDAT 0x59 0x004 -#define MX27_PAD_SSI2_RXDAT__GPTS_TIN 0x59 0x001 -#define MX27_PAD_SSI2_RXDAT__GPIO3_25 0x59 0x032 -#define MX27_PAD_SSI2_TXDAT__SSI2_TXDAT 0x5a 0x004 -#define MX27_PAD_SSI2_TXDAT__GPT4_TOUT 0x5a 0x005 -#define MX27_PAD_SSI2_TXDAT__GPIO3_26 0x5a 0x032 -#define MX27_PAD_SSI2_CLK__SSI2_CLK 0x5b 0x004 -#define MX27_PAD_SSI2_CLK__GPT4_TIN 0x5b 0x001 -#define MX27_PAD_SSI2_CLK__GPIO3_27 0x5b 0x032 -#define MX27_PAD_SSI3_FS__SSI3_FS 0x5c 0x004 -#define MX27_PAD_SSI3_FS__SLCDC2_D0 0x5c 0x001 -#define MX27_PAD_SSI3_FS__GPIO3_28 0x5c 0x032 -#define MX27_PAD_SSI3_RXDAT__SSI3_RXDAT 0x5d 0x004 -#define MX27_PAD_SSI3_RXDAT__SLCDC2_RS 0x5d 0x001 -#define MX27_PAD_SSI3_RXDAT__GPIO3_29 0x5d 0x032 -#define MX27_PAD_SSI3_TXDAT__SSI3_TXDAT 0x5e 0x004 -#define MX27_PAD_SSI3_TXDAT__SLCDC2_CS 0x5e 0x001 -#define MX27_PAD_SSI3_TXDAT__GPIO3_30 0x5e 0x032 -#define MX27_PAD_SSI3_CLK__SSI3_CLK 0x5f 0x004 -#define MX27_PAD_SSI3_CLK__SLCDC2_CLK 0x5f 0x001 -#define MX27_PAD_SSI3_CLK__GPIO3_31 0x5f 0x032 -#define MX27_PAD_SD3_CMD__SD3_CMD 0x60 0x004 -#define MX27_PAD_SD3_CMD__FEC_TXD0 0x60 0x006 -#define MX27_PAD_SD3_CMD__GPIO4_0 0x60 0x032 -#define MX27_PAD_SD3_CLK__SD3_CLK 0x61 0x004 -#define MX27_PAD_SD3_CLK__ETMTRACEPKT15 0x61 0x005 -#define MX27_PAD_SD3_CLK__FEC_TXD1 0x61 0x006 -#define MX27_PAD_SD3_CLK__GPIO4_1 0x61 0x032 -#define MX27_PAD_ATA_DATA0__ATA_DATA0 0x62 0x004 -#define MX27_PAD_ATA_DATA0__SD3_D0 0x62 0x005 -#define MX27_PAD_ATA_DATA0__FEC_TXD2 0x62 0x006 -#define MX27_PAD_ATA_DATA0__GPIO4_2 0x62 0x032 -#define MX27_PAD_ATA_DATA1__ATA_DATA1 0x63 0x004 -#define MX27_PAD_ATA_DATA1__SD3_D1 0x63 0x005 -#define MX27_PAD_ATA_DATA1__FEC_TXD3 0x63 0x006 -#define MX27_PAD_ATA_DATA1__GPIO4_3 0x63 0x032 -#define MX27_PAD_ATA_DATA2__ATA_DATA2 0x64 0x004 -#define MX27_PAD_ATA_DATA2__SD3_D2 0x64 0x005 -#define MX27_PAD_ATA_DATA2__FEC_RX_ER 0x64 0x002 -#define MX27_PAD_ATA_DATA2__GPIO4_4 0x64 0x032 -#define MX27_PAD_ATA_DATA3__ATA_DATA3 0x65 0x004 -#define MX27_PAD_ATA_DATA3__SD3_D3 0x65 0x005 -#define MX27_PAD_ATA_DATA3__FEC_RXD1 0x65 0x002 -#define MX27_PAD_ATA_DATA3__GPIO4_5 0x65 0x032 -#define MX27_PAD_ATA_DATA4__ATA_DATA4 0x66 0x004 -#define MX27_PAD_ATA_DATA4__ETMTRACEPKT14 0x66 0x005 -#define MX27_PAD_ATA_DATA4__FEC_RXD2 0x66 0x002 -#define MX27_PAD_ATA_DATA4__GPIO4_6 0x66 0x032 -#define MX27_PAD_ATA_DATA5__ATA_DATA5 0x67 0x004 -#define MX27_PAD_ATA_DATA5__ETMTRACEPKT13 0x67 0x005 -#define MX27_PAD_ATA_DATA5__FEC_RXD3 0x67 0x002 -#define MX27_PAD_ATA_DATA5__GPIO4_7 0x67 0x032 -#define MX27_PAD_ATA_DATA6__ATA_DATA6 0x68 0x004 -#define MX27_PAD_ATA_DATA6__FEC_MDIO 0x68 0x005 -#define MX27_PAD_ATA_DATA6__GPIO4_8 0x68 0x032 -#define MX27_PAD_ATA_DATA7__ATA_DATA7 0x69 0x004 -#define MX27_PAD_ATA_DATA7__ETMTRACEPKT12 0x69 0x005 -#define MX27_PAD_ATA_DATA7__FEC_MDC 0x69 0x006 -#define MX27_PAD_ATA_DATA7__GPIO4_9 0x69 0x032 -#define MX27_PAD_ATA_DATA8__ATA_DATA8 0x6a 0x004 -#define MX27_PAD_ATA_DATA8__ETMTRACEPKT11 0x6a 0x005 -#define MX27_PAD_ATA_DATA8__FEC_CRS 0x6a 0x002 -#define MX27_PAD_ATA_DATA8__GPIO4_10 0x6a 0x032 -#define MX27_PAD_ATA_DATA9__ATA_DATA9 0x6b 0x004 -#define MX27_PAD_ATA_DATA9__ETMTRACEPKT10 0x6b 0x005 -#define MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x6b 0x002 -#define MX27_PAD_ATA_DATA9__GPIO4_11 0x6b 0x032 -#define MX27_PAD_ATA_DATA10__ATA_DATA10 0x6c 0x004 -#define MX27_PAD_ATA_DATA10__ETMTRACEPKT9 0x6c 0x005 -#define MX27_PAD_ATA_DATA10__FEC_RXD0 0x6c 0x002 -#define MX27_PAD_ATA_DATA10__GPIO4_12 0x6c 0x032 -#define MX27_PAD_ATA_DATA11__ATA_DATA11 0x6d 0x004 -#define MX27_PAD_ATA_DATA11__ETMTRACEPKT8 0x6d 0x005 -#define MX27_PAD_ATA_DATA11__FEC_RX_DV 0x6d 0x002 -#define MX27_PAD_ATA_DATA11__GPIO4_13 0x6d 0x032 -#define MX27_PAD_ATA_DATA12__ATA_DATA12 0x6e 0x004 -#define MX27_PAD_ATA_DATA12__ETMTRACEPKT7 0x6e 0x005 -#define MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x6e 0x002 -#define MX27_PAD_ATA_DATA12__GPIO4_14 0x6e 0x032 -#define MX27_PAD_ATA_DATA13__ATA_DATA13 0x6f 0x004 -#define MX27_PAD_ATA_DATA13__ETMTRACEPKT6 0x6f 0x005 -#define MX27_PAD_ATA_DATA13__FEC_COL 0x6f 0x002 -#define MX27_PAD_ATA_DATA13__GPIO4_15 0x6f 0x032 -#define MX27_PAD_ATA_DATA14__ATA_DATA14 0x70 0x004 -#define MX27_PAD_ATA_DATA14__ETMTRACEPKT5 0x70 0x005 -#define MX27_PAD_ATA_DATA14__FEC_TX_ER 0x70 0x006 -#define MX27_PAD_ATA_DATA14__GPIO4_16 0x70 0x032 -#define MX27_PAD_I2C_DATA__I2C_DATA 0x71 0x004 -#define MX27_PAD_I2C_DATA__GPIO4_17 0x71 0x032 -#define MX27_PAD_I2C_CLK__I2C_CLK 0x72 0x004 -#define MX27_PAD_I2C_CLK__GPIO4_18 0x72 0x032 -#define MX27_PAD_CSPI2_SS2__CSPI2_SS2 0x73 0x004 -#define MX27_PAD_CSPI2_SS2__USBH2_DATA4 0x73 0x005 -#define MX27_PAD_CSPI2_SS2__GPIO4_19 0x73 0x032 -#define MX27_PAD_CSPI2_SS1__CSPI2_SS1 0x74 0x004 -#define MX27_PAD_CSPI2_SS1__USBH2_DATA3 0x74 0x005 -#define MX27_PAD_CSPI2_SS1__GPIO4_20 0x74 0x032 -#define MX27_PAD_CSPI2_SS0__CSPI2_SS0 0x75 0x004 -#define MX27_PAD_CSPI2_SS0__USBH2_DATA6 0x75 0x005 -#define MX27_PAD_CSPI2_SS0__GPIO4_21 0x75 0x032 -#define MX27_PAD_CSPI2_SCLK__CSPI2_SCLK 0x76 0x004 -#define MX27_PAD_CSPI2_SCLK__USBH2_DATA0 0x76 0x005 -#define MX27_PAD_CSPI2_SCLK__GPIO4_22 0x76 0x032 -#define MX27_PAD_CSPI2_MISO__CSPI2_MISO 0x77 0x004 -#define MX27_PAD_CSPI2_MISO__USBH2_DATA2 0x77 0x005 -#define MX27_PAD_CSPI2_MISO__GPIO4_23 0x77 0x032 -#define MX27_PAD_CSPI2_MOSI__CSPI2_MOSI 0x78 0x004 -#define MX27_PAD_CSPI2_MOSI__USBH2_DATA1 0x78 0x005 -#define MX27_PAD_CSPI2_MOSI__GPIO4_24 0x78 0x032 -#define MX27_PAD_CSPI1_RDY__CSPI1_RDY 0x79 0x000 -#define MX27_PAD_CSPI1_RDY__GPIO4_25 0x79 0x032 -#define MX27_PAD_CSPI1_SS2__CSPI1_SS2 0x7a 0x004 -#define MX27_PAD_CSPI1_SS2__USBH2_DATA5 0x7a 0x005 -#define MX27_PAD_CSPI1_SS2__GPIO4_26 0x7a 0x032 -#define MX27_PAD_CSPI1_SS1__CSPI1_SS1 0x7b 0x004 -#define MX27_PAD_CSPI1_SS1__GPIO4_27 0x7b 0x032 -#define MX27_PAD_CSPI1_SS0__CSPI1_SS0 0x7c 0x004 -#define MX27_PAD_CSPI1_SS0__GPIO4_28 0x7c 0x032 -#define MX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x7d 0x004 -#define MX27_PAD_CSPI1_SCLK__GPIO4_29 0x7d 0x032 -#define MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x7e 0x004 -#define MX27_PAD_CSPI1_MISO__GPIO4_30 0x7e 0x032 -#define MX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x7f 0x004 -#define MX27_PAD_CSPI1_MOSI__GPIO4_31 0x7f 0x032 -#define MX27_PAD_USBOTG_NXT__USBOTG_NXT 0x80 0x000 -#define MX27_PAD_USBOTG_NXT__KP_COL6A 0x80 0x005 -#define MX27_PAD_USBOTG_NXT__GPIO5_0 0x80 0x032 -#define MX27_PAD_USBOTG_STP__USBOTG_STP 0x81 0x004 -#define MX27_PAD_USBOTG_STP__KP_ROW6A 0x81 0x005 -#define MX27_PAD_USBOTG_STP__GPIO5_1 0x81 0x032 -#define MX27_PAD_USBOTG_DIR__USBOTG_DIR 0x82 0x000 -#define MX27_PAD_USBOTG_DIR__KP_ROW7A 0x82 0x005 -#define MX27_PAD_USBOTG_DIR__GPIO5_2 0x82 0x032 -#define MX27_PAD_UART2_CTS__UART2_CTS 0x83 0x004 -#define MX27_PAD_UART2_CTS__KP_COL7 0x83 0x005 -#define MX27_PAD_UART2_CTS__GPIO5_3 0x83 0x032 -#define MX27_PAD_UART2_RTS__UART2_RTS 0x84 0x000 -#define MX27_PAD_UART2_RTS__KP_ROW7 0x84 0x005 -#define MX27_PAD_UART2_RTS__GPIO5_4 0x84 0x032 -#define MX27_PAD_PWMO__PWMO 0x85 0x004 -#define MX27_PAD_PWMO__GPIO5_5 0x85 0x032 -#define MX27_PAD_UART2_TXD__UART2_TXD 0x86 0x004 -#define MX27_PAD_UART2_TXD__KP_COL6 0x86 0x005 -#define MX27_PAD_UART2_TXD__GPIO5_6 0x86 0x032 -#define MX27_PAD_UART2_RXD__UART2_RXD 0x87 0x000 -#define MX27_PAD_UART2_RXD__KP_ROW6 0x87 0x005 -#define MX27_PAD_UART2_RXD__GPIO5_7 0x87 0x032 -#define MX27_PAD_UART3_TXD__UART3_TXD 0x88 0x004 -#define MX27_PAD_UART3_TXD__GPIO5_8 0x88 0x032 -#define MX27_PAD_UART3_RXD__UART3_RXD 0x89 0x000 -#define MX27_PAD_UART3_RXD__GPIO5_9 0x89 0x032 -#define MX27_PAD_UART3_CTS__UART3_CTS 0x8a 0x004 -#define MX27_PAD_UART3_CTS__GPIO5_10 0x8a 0x032 -#define MX27_PAD_UART3_RTS__UART3_RTS 0x8b 0x000 -#define MX27_PAD_UART3_RTS__GPIO5_11 0x8b 0x032 -#define MX27_PAD_UART1_TXD__UART1_TXD 0x8c 0x004 -#define MX27_PAD_UART1_TXD__GPIO5_12 0x8c 0x032 -#define MX27_PAD_UART1_RXD__UART1_RXD 0x8d 0x000 -#define MX27_PAD_UART1_RXD__GPIO5_13 0x8d 0x032 -#define MX27_PAD_UART1_CTS__UART1_CTS 0x8e 0x004 -#define MX27_PAD_UART1_CTS__GPIO5_14 0x8e 0x032 -#define MX27_PAD_UART1_RTS__UART1_RTS 0x8f 0x000 -#define MX27_PAD_UART1_RTS__GPIO5_15 0x8f 0x032 -#define MX27_PAD_RTCK__RTCK 0x90 0x004 -#define MX27_PAD_RTCK__OWIRE 0x90 0x005 -#define MX27_PAD_RTCK__GPIO5_16 0x90 0x032 -#define MX27_PAD_RESET_OUT_B__RESET_OUT_B 0x91 0x004 -#define MX27_PAD_RESET_OUT_B__GPIO5_17 0x91 0x032 -#define MX27_PAD_SD1_D0__SD1_D0 0x92 0x004 -#define MX27_PAD_SD1_D0__CSPI3_MISO 0x92 0x001 -#define MX27_PAD_SD1_D0__GPIO5_18 0x92 0x032 -#define MX27_PAD_SD1_D1__SD1_D1 0x93 0x004 -#define MX27_PAD_SD1_D1__GPIO5_19 0x93 0x032 -#define MX27_PAD_SD1_D2__SD1_D2 0x94 0x004 -#define MX27_PAD_SD1_D2__GPIO5_20 0x94 0x032 -#define MX27_PAD_SD1_D3__SD1_D3 0x95 0x004 -#define MX27_PAD_SD1_D3__CSPI3_SS 0x95 0x005 -#define MX27_PAD_SD1_D3__GPIO5_21 0x95 0x032 -#define MX27_PAD_SD1_CMD__SD1_CMD 0x96 0x004 -#define MX27_PAD_SD1_CMD__CSPI3_MOSI 0x96 0x005 -#define MX27_PAD_SD1_CMD__GPIO5_22 0x96 0x032 -#define MX27_PAD_SD1_CLK__SD1_CLK 0x97 0x004 -#define MX27_PAD_SD1_CLK__CSPI3_SCLK 0x97 0x005 -#define MX27_PAD_SD1_CLK__GPIO5_23 0x97 0x032 -#define MX27_PAD_USBOTG_CLK__USBOTG_CLK 0x98 0x000 -#define MX27_PAD_USBOTG_CLK__GPIO5_24 0x98 0x032 -#define MX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x99 0x004 -#define MX27_PAD_USBOTG_DATA7__GPIO5_25 0x99 0x032 -#define MX27_PAD_NFRB__NFRB 0xa0 0x000 -#define MX27_PAD_NFRB__ETMTRACEPKT3 0xa0 0x005 -#define MX27_PAD_NFRB__GPIO6_0 0xa0 0x032 -#define MX27_PAD_NFCLE__NFCLE 0xa1 0x004 -#define MX27_PAD_NFCLE__ETMTRACEPKT0 0xa1 0x005 -#define MX27_PAD_NFCLE__GPIO6_1 0xa1 0x032 -#define MX27_PAD_NFWP_B__NFWP_B 0xa2 0x004 -#define MX27_PAD_NFWP_B__ETMTRACEPKT1 0xa2 0x005 -#define MX27_PAD_NFWP_B__GPIO6_2 0xa2 0x032 -#define MX27_PAD_NFCE_B__NFCE_B 0xa3 0x004 -#define MX27_PAD_NFCE_B__ETMTRACEPKT2 0xa3 0x005 -#define MX27_PAD_NFCE_B__GPIO6_3 0xa3 0x032 -#define MX27_PAD_NFALE__NFALE 0xa4 0x004 -#define MX27_PAD_NFALE__ETMPIPESTAT0 0xa4 0x005 -#define MX27_PAD_NFALE__GPIO6_4 0xa4 0x032 -#define MX27_PAD_NFRE_B__NFRE_B 0xa5 0x004 -#define MX27_PAD_NFRE_B__ETMPIPESTAT1 0xa5 0x005 -#define MX27_PAD_NFRE_B__GPIO6_5 0xa5 0x032 -#define MX27_PAD_NFWE_B__NFWE_B 0xa6 0x004 -#define MX27_PAD_NFWE_B__ETMPIPESTAT2 0xa6 0x005 -#define MX27_PAD_NFWE_B__GPIO6_6 0xa6 0x032 -#define MX27_PAD_PC_POE__PC_POE 0xa7 0x004 -#define MX27_PAD_PC_POE__ATA_BUFFER_EN 0xa7 0x005 -#define MX27_PAD_PC_POE__GPIO6_7 0xa7 0x032 -#define MX27_PAD_PC_RW_B__PC_RW_B 0xa8 0x004 -#define MX27_PAD_PC_RW_B__ATA_IORDY 0xa8 0x001 -#define MX27_PAD_PC_RW_B__GPIO6_8 0xa8 0x032 -#define MX27_PAD_IOIS16__IOIS16 0xa9 0x000 -#define MX27_PAD_IOIS16__ATA_INTRQ 0xa9 0x001 -#define MX27_PAD_IOIS16__GPIO6_9 0xa9 0x032 -#define MX27_PAD_PC_RST__PC_RST 0xaa 0x004 -#define MX27_PAD_PC_RST__ATA_RESET_B 0xaa 0x005 -#define MX27_PAD_PC_RST__GPIO6_10 0xaa 0x032 -#define MX27_PAD_PC_BVD2__PC_BVD2 0xab 0x000 -#define MX27_PAD_PC_BVD2__ATA_DMACK 0xab 0x005 -#define MX27_PAD_PC_BVD2__GPIO6_11 0xab 0x032 -#define MX27_PAD_PC_BVD1__PC_BVD1 0xac 0x000 -#define MX27_PAD_PC_BVD1__ATA_DMARQ 0xac 0x001 -#define MX27_PAD_PC_BVD1__GPIO6_12 0xac 0x032 -#define MX27_PAD_PC_VS2__PC_VS2 0xad 0x000 -#define MX27_PAD_PC_VS2__ATA_DA0 0xad 0x005 -#define MX27_PAD_PC_VS2__GPIO6_13 0xad 0x032 -#define MX27_PAD_PC_VS1__PC_VS1 0xae 0x000 -#define MX27_PAD_PC_VS1__ATA_DA1 0xae 0x005 -#define MX27_PAD_PC_VS1__GPIO6_14 0xae 0x032 -#define MX27_PAD_CLKO__CLKO 0xaf 0x004 -#define MX27_PAD_CLKO__GPIO6_15 0xaf 0x032 -#define MX27_PAD_PC_PWRON__PC_PWRON 0xb0 0x000 -#define MX27_PAD_PC_PWRON__ATA_DA2 0xb0 0x005 -#define MX27_PAD_PC_PWRON__GPIO6_16 0xb0 0x032 -#define MX27_PAD_PC_READY__PC_READY 0xb1 0x000 -#define MX27_PAD_PC_READY__ATA_CS0 0xb1 0x005 -#define MX27_PAD_PC_READY__GPIO6_17 0xb1 0x032 -#define MX27_PAD_PC_WAIT_B__PC_WAIT_B 0xb2 0x000 -#define MX27_PAD_PC_WAIT_B__ATA_CS1 0xb2 0x005 -#define MX27_PAD_PC_WAIT_B__GPIO6_18 0xb2 0x032 -#define MX27_PAD_PC_CD2_B__PC_CD2_B 0xb3 0x000 -#define MX27_PAD_PC_CD2_B__ATA_DIOW 0xb3 0x005 -#define MX27_PAD_PC_CD2_B__GPIO6_19 0xb3 0x032 -#define MX27_PAD_PC_CD1_B__PC_CD1_B 0xb4 0x000 -#define MX27_PAD_PC_CD1_B__ATA_DIOR 0xb4 0x005 -#define MX27_PAD_PC_CD1_B__GPIO6_20 0xb4 0x032 -#define MX27_PAD_CS4_B__CS4_B 0xb5 0x004 -#define MX27_PAD_CS4_B__ETMTRACESYNC 0xb5 0x005 -#define MX27_PAD_CS4_B__GPIO6_21 0xb5 0x032 -#define MX27_PAD_CS5_B__CS5_B 0xb6 0x004 -#define MX27_PAD_CS5_B__ETMTRACECLK 0xb6 0x005 -#define MX27_PAD_CS5_B__GPIO6_22 0xb6 0x032 -#define MX27_PAD_ATA_DATA15__ATA_DATA15 0xb7 0x004 -#define MX27_PAD_ATA_DATA15__ETMTRACEPKT4 0xb7 0x005 -#define MX27_PAD_ATA_DATA15__FEC_TX_EN 0xb7 0x006 -#define MX27_PAD_ATA_DATA15__GPIO6_23 0xb7 0x032 - -#endif /* __DTS_IMX27_PINFUNC_H */ diff --git a/sys/gnu/dts/arm/imx27.dtsi b/sys/gnu/dts/arm/imx27.dtsi deleted file mode 100644 index f3464cf52e4..00000000000 --- a/sys/gnu/dts/arm/imx27.dtsi +++ /dev/null @@ -1,593 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// -// Copyright 2012 Sascha Hauer, Pengutronix - -#include "imx27-pinfunc.h" - -#include -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - /* - * The decompressor and also some bootloaders rely on a - * pre-existing /chosen node to be available to insert the - * command line and merge other ATAGS info. - */ - chosen {}; - - aliases { - ethernet0 = &fec; - gpio0 = &gpio1; - gpio1 = &gpio2; - gpio2 = &gpio3; - gpio3 = &gpio4; - gpio4 = &gpio5; - gpio5 = &gpio6; - i2c0 = &i2c1; - i2c1 = &i2c2; - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - serial3 = &uart4; - serial4 = &uart5; - serial5 = &uart6; - spi0 = &cspi1; - spi1 = &cspi2; - spi2 = &cspi3; - }; - - aitc: aitc-interrupt-controller@10040000 { - compatible = "fsl,imx27-aitc", "fsl,avic"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x10040000 0x1000>; - }; - - clocks { - clk_osc26m: osc26m { - compatible = "fsl,imx-osc26m", "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <26000000>; - }; - }; - - cpus { - #size-cells = <0>; - #address-cells = <1>; - - cpu: cpu@0 { - device_type = "cpu"; - reg = <0>; - compatible = "arm,arm926ej-s"; - operating-points = < - /* kHz uV */ - 266000 1300000 - 399000 1450000 - >; - clock-latency = <62500>; - clocks = <&clks IMX27_CLK_CPU_DIV>; - voltage-tolerance = <5>; - }; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&aitc>; - ranges; - - aipi@10000000 { /* AIPI1 */ - compatible = "fsl,aipi-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x10000000 0x20000>; - ranges; - - dma: dma@10001000 { - compatible = "fsl,imx27-dma"; - reg = <0x10001000 0x1000>; - interrupts = <32>; - clocks = <&clks IMX27_CLK_DMA_IPG_GATE>, - <&clks IMX27_CLK_DMA_AHB_GATE>; - clock-names = "ipg", "ahb"; - #dma-cells = <1>; - #dma-channels = <16>; - }; - - wdog: wdog@10002000 { - compatible = "fsl,imx27-wdt", "fsl,imx21-wdt"; - reg = <0x10002000 0x1000>; - interrupts = <27>; - clocks = <&clks IMX27_CLK_WDOG_IPG_GATE>; - }; - - gpt1: timer@10003000 { - compatible = "fsl,imx27-gpt", "fsl,imx21-gpt"; - reg = <0x10003000 0x1000>; - interrupts = <26>; - clocks = <&clks IMX27_CLK_GPT1_IPG_GATE>, - <&clks IMX27_CLK_PER1_GATE>; - clock-names = "ipg", "per"; - }; - - gpt2: timer@10004000 { - compatible = "fsl,imx27-gpt", "fsl,imx21-gpt"; - reg = <0x10004000 0x1000>; - interrupts = <25>; - clocks = <&clks IMX27_CLK_GPT2_IPG_GATE>, - <&clks IMX27_CLK_PER1_GATE>; - clock-names = "ipg", "per"; - }; - - gpt3: timer@10005000 { - compatible = "fsl,imx27-gpt", "fsl,imx21-gpt"; - reg = <0x10005000 0x1000>; - interrupts = <24>; - clocks = <&clks IMX27_CLK_GPT3_IPG_GATE>, - <&clks IMX27_CLK_PER1_GATE>; - clock-names = "ipg", "per"; - }; - - pwm: pwm@10006000 { - #pwm-cells = <2>; - compatible = "fsl,imx27-pwm"; - reg = <0x10006000 0x1000>; - interrupts = <23>; - clocks = <&clks IMX27_CLK_PWM_IPG_GATE>, - <&clks IMX27_CLK_PER1_GATE>; - clock-names = "ipg", "per"; - }; - - rtc: rtc@10007000 { - compatible = "fsl,imx21-rtc"; - reg = <0x10007000 0x1000>; - interrupts = <22>; - clocks = <&clks IMX27_CLK_CKIL>, - <&clks IMX27_CLK_RTC_IPG_GATE>; - clock-names = "ref", "ipg"; - }; - - kpp: kpp@10008000 { - compatible = "fsl,imx27-kpp", "fsl,imx21-kpp"; - reg = <0x10008000 0x1000>; - interrupts = <21>; - clocks = <&clks IMX27_CLK_KPP_IPG_GATE>; - status = "disabled"; - }; - - owire: owire@10009000 { - compatible = "fsl,imx27-owire", "fsl,imx21-owire"; - reg = <0x10009000 0x1000>; - clocks = <&clks IMX27_CLK_OWIRE_IPG_GATE>; - status = "disabled"; - }; - - uart1: serial@1000a000 { - compatible = "fsl,imx27-uart", "fsl,imx21-uart"; - reg = <0x1000a000 0x1000>; - interrupts = <20>; - clocks = <&clks IMX27_CLK_UART1_IPG_GATE>, - <&clks IMX27_CLK_PER1_GATE>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart2: serial@1000b000 { - compatible = "fsl,imx27-uart", "fsl,imx21-uart"; - reg = <0x1000b000 0x1000>; - interrupts = <19>; - clocks = <&clks IMX27_CLK_UART2_IPG_GATE>, - <&clks IMX27_CLK_PER1_GATE>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart3: serial@1000c000 { - compatible = "fsl,imx27-uart", "fsl,imx21-uart"; - reg = <0x1000c000 0x1000>; - interrupts = <18>; - clocks = <&clks IMX27_CLK_UART3_IPG_GATE>, - <&clks IMX27_CLK_PER1_GATE>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart4: serial@1000d000 { - compatible = "fsl,imx27-uart", "fsl,imx21-uart"; - reg = <0x1000d000 0x1000>; - interrupts = <17>; - clocks = <&clks IMX27_CLK_UART4_IPG_GATE>, - <&clks IMX27_CLK_PER1_GATE>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - cspi1: spi@1000e000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx27-cspi"; - reg = <0x1000e000 0x1000>; - interrupts = <16>; - clocks = <&clks IMX27_CLK_CSPI1_IPG_GATE>, - <&clks IMX27_CLK_PER2_GATE>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - cspi2: spi@1000f000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx27-cspi"; - reg = <0x1000f000 0x1000>; - interrupts = <15>; - clocks = <&clks IMX27_CLK_CSPI2_IPG_GATE>, - <&clks IMX27_CLK_PER2_GATE>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - ssi1: ssi@10010000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx27-ssi", "fsl,imx21-ssi"; - reg = <0x10010000 0x1000>; - interrupts = <14>; - clocks = <&clks IMX27_CLK_SSI1_IPG_GATE>; - dmas = <&dma 12>, <&dma 13>, <&dma 14>, <&dma 15>; - dma-names = "rx0", "tx0", "rx1", "tx1"; - fsl,fifo-depth = <8>; - status = "disabled"; - }; - - ssi2: ssi@10011000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx27-ssi", "fsl,imx21-ssi"; - reg = <0x10011000 0x1000>; - interrupts = <13>; - clocks = <&clks IMX27_CLK_SSI2_IPG_GATE>; - dmas = <&dma 8>, <&dma 9>, <&dma 10>, <&dma 11>; - dma-names = "rx0", "tx0", "rx1", "tx1"; - fsl,fifo-depth = <8>; - status = "disabled"; - }; - - i2c1: i2c@10012000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx27-i2c", "fsl,imx21-i2c"; - reg = <0x10012000 0x1000>; - interrupts = <12>; - clocks = <&clks IMX27_CLK_I2C1_IPG_GATE>; - status = "disabled"; - }; - - sdhci1: sdhci@10013000 { - compatible = "fsl,imx27-mmc", "fsl,imx21-mmc"; - reg = <0x10013000 0x1000>; - interrupts = <11>; - clocks = <&clks IMX27_CLK_SDHC1_IPG_GATE>, - <&clks IMX27_CLK_PER2_GATE>; - clock-names = "ipg", "per"; - dmas = <&dma 7>; - dma-names = "rx-tx"; - status = "disabled"; - }; - - sdhci2: sdhci@10014000 { - compatible = "fsl,imx27-mmc", "fsl,imx21-mmc"; - reg = <0x10014000 0x1000>; - interrupts = <10>; - clocks = <&clks IMX27_CLK_SDHC2_IPG_GATE>, - <&clks IMX27_CLK_PER2_GATE>; - clock-names = "ipg", "per"; - dmas = <&dma 6>; - dma-names = "rx-tx"; - status = "disabled"; - }; - - iomuxc: iomuxc@10015000 { - compatible = "fsl,imx27-iomuxc"; - reg = <0x10015000 0x600>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gpio1: gpio@10015000 { - compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; - reg = <0x10015000 0x100>; - clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>; - interrupts = <8>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@10015100 { - compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; - reg = <0x10015100 0x100>; - clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>; - interrupts = <8>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio@10015200 { - compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; - reg = <0x10015200 0x100>; - clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>; - interrupts = <8>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio4: gpio@10015300 { - compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; - reg = <0x10015300 0x100>; - clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>; - interrupts = <8>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio5: gpio@10015400 { - compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; - reg = <0x10015400 0x100>; - clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>; - interrupts = <8>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio6: gpio@10015500 { - compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; - reg = <0x10015500 0x100>; - clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>; - interrupts = <8>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - audmux: audmux@10016000 { - compatible = "fsl,imx27-audmux", "fsl,imx21-audmux"; - reg = <0x10016000 0x1000>; - clocks = <&clks IMX27_CLK_DUMMY>; - clock-names = "audmux"; - status = "disabled"; - }; - - cspi3: spi@10017000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx27-cspi"; - reg = <0x10017000 0x1000>; - interrupts = <6>; - clocks = <&clks IMX27_CLK_CSPI3_IPG_GATE>, - <&clks IMX27_CLK_PER2_GATE>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - gpt4: timer@10019000 { - compatible = "fsl,imx27-gpt", "fsl,imx21-gpt"; - reg = <0x10019000 0x1000>; - interrupts = <4>; - clocks = <&clks IMX27_CLK_GPT4_IPG_GATE>, - <&clks IMX27_CLK_PER1_GATE>; - clock-names = "ipg", "per"; - }; - - gpt5: timer@1001a000 { - compatible = "fsl,imx27-gpt", "fsl,imx21-gpt"; - reg = <0x1001a000 0x1000>; - interrupts = <3>; - clocks = <&clks IMX27_CLK_GPT5_IPG_GATE>, - <&clks IMX27_CLK_PER1_GATE>; - clock-names = "ipg", "per"; - }; - - uart5: serial@1001b000 { - compatible = "fsl,imx27-uart", "fsl,imx21-uart"; - reg = <0x1001b000 0x1000>; - interrupts = <49>; - clocks = <&clks IMX27_CLK_UART5_IPG_GATE>, - <&clks IMX27_CLK_PER1_GATE>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart6: serial@1001c000 { - compatible = "fsl,imx27-uart", "fsl,imx21-uart"; - reg = <0x1001c000 0x1000>; - interrupts = <48>; - clocks = <&clks IMX27_CLK_UART6_IPG_GATE>, - <&clks IMX27_CLK_PER1_GATE>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - i2c2: i2c@1001d000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx27-i2c", "fsl,imx21-i2c"; - reg = <0x1001d000 0x1000>; - interrupts = <1>; - clocks = <&clks IMX27_CLK_I2C2_IPG_GATE>; - status = "disabled"; - }; - - sdhci3: sdhci@1001e000 { - compatible = "fsl,imx27-mmc", "fsl,imx21-mmc"; - reg = <0x1001e000 0x1000>; - interrupts = <9>; - clocks = <&clks IMX27_CLK_SDHC3_IPG_GATE>, - <&clks IMX27_CLK_PER2_GATE>; - clock-names = "ipg", "per"; - dmas = <&dma 36>; - dma-names = "rx-tx"; - status = "disabled"; - }; - - gpt6: timer@1001f000 { - compatible = "fsl,imx27-gpt", "fsl,imx21-gpt"; - reg = <0x1001f000 0x1000>; - interrupts = <2>; - clocks = <&clks IMX27_CLK_GPT6_IPG_GATE>, - <&clks IMX27_CLK_PER1_GATE>; - clock-names = "ipg", "per"; - }; - }; - - aipi@10020000 { /* AIPI2 */ - compatible = "fsl,aipi-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x10020000 0x20000>; - ranges; - - fb: fb@10021000 { - compatible = "fsl,imx27-fb", "fsl,imx21-fb"; - interrupts = <61>; - reg = <0x10021000 0x1000>; - clocks = <&clks IMX27_CLK_LCDC_IPG_GATE>, - <&clks IMX27_CLK_LCDC_AHB_GATE>, - <&clks IMX27_CLK_PER3_GATE>; - clock-names = "ipg", "ahb", "per"; - status = "disabled"; - }; - - coda: coda@10023000 { - compatible = "fsl,imx27-vpu", "cnm,codadx6"; - reg = <0x10023000 0x0200>; - interrupts = <53>; - clocks = <&clks IMX27_CLK_VPU_BAUD_GATE>, - <&clks IMX27_CLK_VPU_AHB_GATE>; - clock-names = "per", "ahb"; - iram = <&iram>; - }; - - usbotg: usb@10024000 { - compatible = "fsl,imx27-usb"; - reg = <0x10024000 0x200>; - interrupts = <56>; - clocks = <&clks IMX27_CLK_USB_IPG_GATE>, - <&clks IMX27_CLK_USB_AHB_GATE>, - <&clks IMX27_CLK_USB_DIV>; - clock-names = "ipg", "ahb", "per"; - fsl,usbmisc = <&usbmisc 0>; - status = "disabled"; - }; - - usbh1: usb@10024200 { - compatible = "fsl,imx27-usb"; - reg = <0x10024200 0x200>; - interrupts = <54>; - clocks = <&clks IMX27_CLK_USB_IPG_GATE>, - <&clks IMX27_CLK_USB_AHB_GATE>, - <&clks IMX27_CLK_USB_DIV>; - clock-names = "ipg", "ahb", "per"; - fsl,usbmisc = <&usbmisc 1>; - dr_mode = "host"; - status = "disabled"; - }; - - usbh2: usb@10024400 { - compatible = "fsl,imx27-usb"; - reg = <0x10024400 0x200>; - interrupts = <55>; - clocks = <&clks IMX27_CLK_USB_IPG_GATE>, - <&clks IMX27_CLK_USB_AHB_GATE>, - <&clks IMX27_CLK_USB_DIV>; - clock-names = "ipg", "ahb", "per"; - fsl,usbmisc = <&usbmisc 2>; - dr_mode = "host"; - status = "disabled"; - }; - - usbmisc: usbmisc@10024600 { - #index-cells = <1>; - compatible = "fsl,imx27-usbmisc"; - reg = <0x10024600 0x200>; - }; - - sahara2: sahara@10025000 { - compatible = "fsl,imx27-sahara"; - reg = <0x10025000 0x1000>; - interrupts = <59>; - clocks = <&clks IMX27_CLK_SAHARA_IPG_GATE>, - <&clks IMX27_CLK_SAHARA_AHB_GATE>; - clock-names = "ipg", "ahb"; - }; - - clks: ccm@10027000{ - compatible = "fsl,imx27-ccm"; - reg = <0x10027000 0x1000>; - #clock-cells = <1>; - }; - - iim: iim@10028000 { - compatible = "fsl,imx27-iim"; - reg = <0x10028000 0x1000>; - interrupts = <62>; - clocks = <&clks IMX27_CLK_IIM_IPG_GATE>; - }; - - fec: ethernet@1002b000 { - compatible = "fsl,imx27-fec"; - reg = <0x1002b000 0x1000>; - interrupts = <50>; - clocks = <&clks IMX27_CLK_FEC_IPG_GATE>, - <&clks IMX27_CLK_FEC_AHB_GATE>; - clock-names = "ipg", "ahb"; - status = "disabled"; - }; - }; - - nfc: nand@d8000000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "fsl,imx27-nand"; - reg = <0xd8000000 0x1000>; - interrupts = <29>; - clocks = <&clks IMX27_CLK_NFC_BAUD_GATE>; - status = "disabled"; - }; - - weim: weim@d8002000 { - #address-cells = <2>; - #size-cells = <1>; - compatible = "fsl,imx27-weim"; - reg = <0xd8002000 0x1000>; - clocks = <&clks IMX27_CLK_EMI_AHB_GATE>; - ranges = < - 0 0 0xc0000000 0x08000000 - 1 0 0xc8000000 0x08000000 - 2 0 0xd0000000 0x02000000 - 3 0 0xd2000000 0x02000000 - 4 0 0xd4000000 0x02000000 - 5 0 0xd6000000 0x02000000 - >; - status = "disabled"; - }; - - iram: sram@ffff4c00 { - compatible = "mmio-sram"; - reg = <0xffff4c00 0xb400>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/imx28-apf28.dts b/sys/gnu/dts/arm/imx28-apf28.dts deleted file mode 100644 index 3ed2b328f7e..00000000000 --- a/sys/gnu/dts/arm/imx28-apf28.dts +++ /dev/null @@ -1,80 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2012 Armadeus Systems - - */ - -/dts-v1/; -#include "imx28.dtsi" - -/ { - model = "Armadeus Systems APF28 module"; - compatible = "armadeus,imx28-apf28", "fsl,imx28"; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x08000000>; - }; - - apb@80000000 { - apbh@80000000 { - gpmi-nand@8000c000 { - pinctrl-names = "default"; - pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>; - status = "okay"; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x300000>; - }; - - partition@300000 { - label = "env"; - reg = <0x300000 0x80000>; - }; - - partition@380000 { - label = "env2"; - reg = <0x380000 0x80000>; - }; - - partition@400000 { - label = "dtb"; - reg = <0x400000 0x80000>; - }; - - partition@480000 { - label = "splash"; - reg = <0x480000 0x80000>; - }; - - partition@500000 { - label = "kernel"; - reg = <0x500000 0x800000>; - }; - - partition@d00000 { - label = "rootfs"; - reg = <0xd00000 0xf300000>; - }; - }; - }; - - apbx@80040000 { - duart: serial@80074000 { - pinctrl-names = "default"; - pinctrl-0 = <&duart_pins_a>; - status = "okay"; - }; - }; - }; - - ahb@80080000 { - mac0: ethernet@800f0000 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&mac0_pins_a>; - phy-reset-gpios = <&gpio4 13 GPIO_ACTIVE_LOW>; - status = "okay"; - }; - }; -}; diff --git a/sys/gnu/dts/arm/imx28-apf28dev.dts b/sys/gnu/dts/arm/imx28-apf28dev.dts deleted file mode 100644 index 1b253b47006..00000000000 --- a/sys/gnu/dts/arm/imx28-apf28dev.dts +++ /dev/null @@ -1,225 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2012 Armadeus Systems - - */ - -/* APF28Dev is a docking board for the APF28 SOM */ -#include "imx28-apf28.dts" - -/ { - model = "Armadeus Systems APF28Dev docking/development board"; - compatible = "armadeus,imx28-apf28dev", "armadeus,imx28-apf28", "fsl,imx28"; - - apb@80000000 { - apbh@80000000 { - ssp0: spi@80010000 { - compatible = "fsl,imx28-mmc"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_4bit_pins_a - &mmc0_cd_cfg &mmc0_sck_cfg>; - bus-width = <4>; - status = "okay"; - }; - - ssp2: spi@80014000 { - compatible = "fsl,imx28-spi"; - pinctrl-names = "default"; - pinctrl-0 = <&spi2_pins_a>; - status = "okay"; - }; - - pinctrl@80018000 { - pinctrl-names = "default"; - pinctrl-0 = <&hog_pins_apf28dev>; - - hog_pins_apf28dev: hog@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_D16__GPIO_1_16 - MX28_PAD_LCD_D17__GPIO_1_17 - MX28_PAD_LCD_D18__GPIO_1_18 - MX28_PAD_LCD_D19__GPIO_1_19 - MX28_PAD_LCD_D20__GPIO_1_20 - MX28_PAD_LCD_D21__GPIO_1_21 - MX28_PAD_LCD_D22__GPIO_1_22 - MX28_PAD_GPMI_CE1N__GPIO_0_17 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - lcdif_pins_apf28dev: lcdif-apf28dev@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_RD_E__LCD_VSYNC - MX28_PAD_LCD_WR_RWN__LCD_HSYNC - MX28_PAD_LCD_RS__LCD_DOTCLK - MX28_PAD_LCD_CS__LCD_ENABLE - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - usb0_otg_apf28dev: otg-apf28dev@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_D23__GPIO_1_23 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - }; - - lcdif@80030000 { - pinctrl-names = "default"; - pinctrl-0 = <&lcdif_16bit_pins_a - &lcdif_pins_apf28dev>; - display = <&display0>; - status = "okay"; - - display0: display0 { - bits-per-pixel = <16>; - bus-width = <16>; - - display-timings { - native-mode = <&timing0>; - timing0: timing0 { - clock-frequency = <33000033>; - hactive = <800>; - vactive = <480>; - hback-porch = <96>; - hfront-porch = <96>; - vback-porch = <20>; - vfront-porch = <21>; - hsync-len = <64>; - vsync-len = <4>; - hsync-active = <1>; - vsync-active = <1>; - de-active = <1>; - pixelclk-active = <0>; - }; - }; - }; - }; - - can0: can@80032000 { - pinctrl-names = "default"; - pinctrl-0 = <&can0_pins_a>; - xceiver-supply = <®_can0_vcc>; - status = "okay"; - }; - }; - - apbx@80040000 { - lradc@80050000 { - fsl,lradc-touchscreen-wires = <4>; - status = "okay"; - }; - - i2c0: i2c@80058000 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - }; - - pwm: pwm@80064000 { - pinctrl-names = "default"; - pinctrl-0 = <&pwm3_pins_a &pwm4_pins_a>; - status = "okay"; - }; - - auart0: serial@8006a000 { - pinctrl-names = "default"; - pinctrl-0 = <&auart0_pins_a>; - uart-has-rtscts; - status = "okay"; - }; - - usbphy0: usbphy@8007c000 { - status = "okay"; - }; - - usbphy1: usbphy@8007e000 { - status = "okay"; - }; - }; - }; - - ahb@80080000 { - usb0: usb@80080000 { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_otg_apf28dev - &usb0_id_pins_b>; - vbus-supply = <®_usb0_vbus>; - status = "okay"; - }; - - usb1: usb@80090000 { - status = "okay"; - }; - - mac1: ethernet@800f4000 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&mac1_pins_a>; - phy-reset-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; - status = "okay"; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_usb0_vbus: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "usb0_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 23 1>; - enable-active-high; - }; - - reg_can0_vcc: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "can0_vcc"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - }; - - leds { - compatible = "gpio-leds"; - - user { - label = "Heartbeat"; - gpios = <&gpio0 21 0>; - linux,default-trigger = "heartbeat"; - }; - }; - - backlight { - compatible = "pwm-backlight"; - - pwms = <&pwm 3 191000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - user-button { - label = "User button"; - gpios = <&gpio0 17 GPIO_ACTIVE_LOW>; - linux,code = <0x100>; - wakeup-source; - }; - }; -}; diff --git a/sys/gnu/dts/arm/imx28-apx4devkit.dts b/sys/gnu/dts/arm/imx28-apx4devkit.dts deleted file mode 100644 index 3a184d13887..00000000000 --- a/sys/gnu/dts/arm/imx28-apx4devkit.dts +++ /dev/null @@ -1,230 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; -#include "imx28.dtsi" - -/ { - model = "Bluegiga APX4 Development Kit"; - compatible = "bluegiga,apx4devkit", "fsl,imx28"; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x04000000>; - }; - - apb@80000000 { - apbh@80000000 { - gpmi-nand@8000c000 { - pinctrl-names = "default"; - pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>; - status = "okay"; - }; - - ssp0: spi@80010000 { - compatible = "fsl,imx28-mmc"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_sck_cfg>; - bus-width = <4>; - status = "okay"; - }; - - ssp2: spi@80014000 { - compatible = "fsl,imx28-mmc"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_4bit_pins_apx4 &mmc2_sck_cfg_apx4>; - bus-width = <4>; - status = "okay"; - }; - - pinctrl@80018000 { - pinctrl-names = "default"; - pinctrl-0 = <&hog_pins_a>; - - hog_pins_a: hog@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_GPMI_CE1N__GPIO_0_17 - MX28_PAD_GPMI_RDY1__GPIO_0_21 - MX28_PAD_SSP2_MISO__GPIO_2_18 - MX28_PAD_SSP2_SS0__AUART3_TX /* was: 0x2131 - MX28_PAD_SSP2_SS0__GPIO_2_19 */ - MX28_PAD_PWM3__GPIO_3_28 - MX28_PAD_LCD_RESET__GPIO_3_30 - MX28_PAD_JTAG_RTCK__GPIO_4_20 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - lcdif_pins_apx4: lcdif-apx4@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_RD_E__LCD_VSYNC - MX28_PAD_LCD_WR_RWN__LCD_HSYNC - MX28_PAD_LCD_RS__LCD_DOTCLK - MX28_PAD_LCD_CS__LCD_ENABLE - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - mmc2_4bit_pins_apx4: mmc2-4bit-apx4@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SSP0_DATA4__SSP2_D0 - MX28_PAD_SSP0_DATA5__SSP2_D3 - MX28_PAD_SSP0_DATA6__SSP2_CMD - MX28_PAD_SSP0_DATA7__SSP2_SCK - MX28_PAD_SSP2_SS1__SSP2_D1 - MX28_PAD_SSP2_SS2__SSP2_D2 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - mmc2_sck_cfg_apx4: mmc2-sck-cfg-apx4@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SSP0_DATA7__SSP2_SCK - >; - fsl,drive-strength = ; - fsl,pull-up = ; - }; - }; - - lcdif@80030000 { - pinctrl-names = "default"; - pinctrl-0 = <&lcdif_24bit_pins_a - &lcdif_pins_apx4>; - display = <&display0>; - status = "okay"; - - display0: display0 { - bits-per-pixel = <32>; - bus-width = <24>; - - display-timings { - native-mode = <&timing0>; - timing0: timing0 { - clock-frequency = <30000000>; - hactive = <800>; - vactive = <480>; - hback-porch = <88>; - hfront-porch = <40>; - vback-porch = <32>; - vfront-porch = <13>; - hsync-len = <48>; - vsync-len = <3>; - hsync-active = <1>; - vsync-active = <1>; - de-active = <1>; - pixelclk-active = <0>; - }; - }; - }; - }; - }; - - apbx@80040000 { - saif0: saif@80042000 { - pinctrl-names = "default"; - pinctrl-0 = <&saif0_pins_a>; - status = "okay"; - }; - - saif1: saif@80046000 { - pinctrl-names = "default"; - pinctrl-0 = <&saif1_pins_a>; - fsl,saif-master = <&saif0>; - status = "okay"; - }; - - i2c0: i2c@80058000 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - - sgtl5000: codec@a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - #sound-dai-cells = <0>; - VDDA-supply = <®_3p3v>; - VDDIO-supply = <®_3p3v>; - clocks = <&saif0>; - }; - - pcf8563: rtc@51 { - compatible = "phg,pcf8563"; - reg = <0x51>; - }; - }; - - duart: serial@80074000 { - pinctrl-names = "default"; - pinctrl-0 = <&duart_pins_a>; - status = "okay"; - }; - - auart0: serial@8006a000 { - pinctrl-names = "default"; - pinctrl-0 = <&auart0_pins_a>; - status = "okay"; - }; - - auart1: serial@8006c000 { - pinctrl-names = "default"; - pinctrl-0 = <&auart1_2pins_a>; - status = "okay"; - }; - - auart2: serial@8006e000 { - pinctrl-names = "default"; - pinctrl-0 = <&auart2_2pins_a>; - status = "okay"; - }; - }; - }; - - ahb@80080000 { - mac0: ethernet@800f0000 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&mac0_pins_a>; - status = "okay"; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_3p3v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - - sound { - compatible = "bluegiga,apx4devkit-sgtl5000", - "fsl,mxs-audio-sgtl5000"; - model = "apx4devkit-sgtl5000"; - saif-controllers = <&saif0 &saif1>; - audio-codec = <&sgtl5000>; - }; - - leds { - compatible = "gpio-leds"; - - user { - label = "Heartbeat"; - gpios = <&gpio3 28 0>; - linux,default-trigger = "heartbeat"; - }; - }; -}; diff --git a/sys/gnu/dts/arm/imx28-cfa10036.dts b/sys/gnu/dts/arm/imx28-cfa10036.dts deleted file mode 100644 index 85aa1cc3ff6..00000000000 --- a/sys/gnu/dts/arm/imx28-cfa10036.dts +++ /dev/null @@ -1,140 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2012 Free Electrons - */ - -/dts-v1/; -#include "imx28.dtsi" -#include - -/ { - model = "Crystalfontz CFA-10036 Board"; - compatible = "crystalfontz,cfa10036", "fsl,imx28"; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x08000000>; - }; - - apb@80000000 { - apbh@80000000 { - pinctrl@80018000 { - ssd1306_cfa10036: ssd1306-10036@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SSP0_DATA7__GPIO_2_7 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - led_pins_cfa10036: leds-10036@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_AUART1_RX__GPIO_3_4 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - usb0_otg_cfa10036: otg-10036@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_GPMI_RDY0__USB0_ID - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - mmc_pwr_cfa10036: mmc_pwr_cfa10036@0 { - reg = <0>; - fsl,pinmux-ids = < - 0x31c3 /* - MX28_PAD_PWM3__GPIO_3_28 */ - >; - fsl,drive-strength = <0>; - fsl,voltage = <1>; - fsl,pull-up = <0>; - }; - - }; - - ssp0: spi@80010000 { - compatible = "fsl,imx28-mmc"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_4bit_pins_a - &mmc0_cd_cfg &mmc0_sck_cfg>; - vmmc-supply = <®_vddio_sd0>; - bus-width = <4>; - status = "okay"; - }; - }; - - apbx@80040000 { - duart: serial@80074000 { - pinctrl-names = "default"; - pinctrl-0 = <&duart_pins_b>; - status = "okay"; - }; - - i2c0: i2c@80058000 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_b>; - clock-frequency = <400000>; - status = "okay"; - - ssd1306: oled@3c { - compatible = "solomon,ssd1306fb-i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&ssd1306_cfa10036>; - reg = <0x3c>; - reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>; - solomon,height = <32>; - solomon,width = <128>; - solomon,page-offset = <0>; - solomon,com-lrremap; - solomon,com-invdir; - solomon,com-offset = <32>; - }; - }; - - usbphy0: usbphy@8007c000 { - status = "okay"; - }; - }; - }; - - ahb@80080000 { - usb0: usb@80080000 { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_otg_cfa10036>; - dr_mode = "peripheral"; - phy_type = "utmi"; - status = "okay"; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_cfa10036>; - - power { - gpios = <&gpio3 4 1>; - default-state = "on"; - }; - }; - - reg_vddio_sd0: vddio-sd0 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc_pwr_cfa10036>; - regulator-name = "vddio-sd0"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio3 28 0>; - }; -}; diff --git a/sys/gnu/dts/arm/imx28-cfa10037.dts b/sys/gnu/dts/arm/imx28-cfa10037.dts deleted file mode 100644 index d3e9a731525..00000000000 --- a/sys/gnu/dts/arm/imx28-cfa10037.dts +++ /dev/null @@ -1,83 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2012 Free Electrons - */ - -/* - * The CFA-10049 is an expansion board for the CFA-10036 module, thus we - * need to include the CFA-10036 DTS. - */ -#include "imx28-cfa10036.dts" - -/ { - model = "Crystalfontz CFA-10037 Board"; - compatible = "crystalfontz,cfa10037", "crystalfontz,cfa10036", "fsl,imx28"; - - apb@80000000 { - apbh@80000000 { - pinctrl@80018000 { - usb_pins_cfa10037: usb-10037@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_GPMI_D07__GPIO_0_7 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - mac0_pins_cfa10037: mac0-10037@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SSP2_SS2__GPIO_2_21 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - }; - }; - - apbx@80040000 { - usbphy1: usbphy@8007e000 { - status = "okay"; - }; - }; - }; - - ahb@80080000 { - usb1: usb@80090000 { - vbus-supply = <®_usb1_vbus>; - pinctrl-0 = <&usb1_pins_a>; - pinctrl-names = "default"; - status = "okay"; - }; - - mac0: ethernet@800f0000 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&mac0_pins_a - &mac0_pins_cfa10037>; - phy-reset-gpios = <&gpio2 21 GPIO_ACTIVE_LOW>; - phy-reset-duration = <100>; - status = "okay"; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_usb1_vbus: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&usb_pins_cfa10037>; - regulator-name = "usb1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio0 7 1>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/imx28-cfa10049.dts b/sys/gnu/dts/arm/imx28-cfa10049.dts deleted file mode 100644 index a92b05ef390..00000000000 --- a/sys/gnu/dts/arm/imx28-cfa10049.dts +++ /dev/null @@ -1,428 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2012 Free Electrons - */ - -/* - * The CFA-10049 is an expansion board for the CFA-10036 module, thus we - * need to include the CFA-10036 DTS. - */ -#include "imx28-cfa10036.dts" - -/ { - model = "Crystalfontz CFA-10049 Board"; - compatible = "crystalfontz,cfa10049", "crystalfontz,cfa10036", "fsl,imx28"; - - i2cmux { - compatible = "i2c-mux-gpio"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2cmux_pins_cfa10049>; - mux-gpios = <&gpio1 22 0 &gpio1 23 0>; - i2c-parent = <&i2c1>; - - i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - adc0: nau7802@2a { - compatible = "nuvoton,nau7802"; - reg = <0x2a>; - nuvoton,vldo = <3000>; - }; - }; - - i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - adc1: nau7802@2a { - compatible = "nuvoton,nau7802"; - reg = <0x2a>; - nuvoton,vldo = <3000>; - }; - }; - - i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - - adc2: nau7802@2a { - compatible = "nuvoton,nau7802"; - reg = <0x2a>; - nuvoton,vldo = <3000>; - }; - }; - - i2c@3 { - reg = <3>; - #address-cells = <1>; - #size-cells = <0>; - - pca9555: pca9555@20 { - compatible = "nxp,pca9555"; - pinctrl-names = "default"; - pinctrl-0 = <&pca_pins_cfa10049>; - interrupt-parent = <&gpio2>; - interrupts = <19 0x2>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x20>; - }; - }; - }; - - apb@80000000 { - apbh@80000000 { - pinctrl@80018000 { - usb_pins_cfa10049: usb-10049@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_GPMI_D07__GPIO_0_7 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - i2cmux_pins_cfa10049: i2cmux-10049@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_D22__GPIO_1_22 - MX28_PAD_LCD_D23__GPIO_1_23 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - mac0_pins_cfa10049: mac0-10049@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SSP2_SS2__GPIO_2_21 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - pca_pins_cfa10049: pca-10049@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SSP2_SS0__GPIO_2_19 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - rotary_pins_cfa10049: rotary-10049@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_I2C0_SCL__GPIO_3_24 - MX28_PAD_I2C0_SDA__GPIO_3_25 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - rotary_btn_pins_cfa10049: rotary-btn-10049@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SAIF1_SDATA0__GPIO_3_26 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - spi2_pins_cfa10049: spi2-cfa10049@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SSP2_SCK__GPIO_2_16 - MX28_PAD_SSP2_MOSI__GPIO_2_17 - MX28_PAD_SSP2_MISO__GPIO_2_18 - MX28_PAD_AUART1_TX__GPIO_3_5 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - spi3_pins_cfa10049: spi3-cfa10049@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_GPMI_RDN__GPIO_0_24 - MX28_PAD_GPMI_RESETN__GPIO_0_28 - MX28_PAD_GPMI_CE1N__GPIO_0_17 - MX28_PAD_GPMI_ALE__GPIO_0_26 - MX28_PAD_GPMI_CLE__GPIO_0_27 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - lcdif_18bit_pins_cfa10049: lcdif-18bit@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_D00__LCD_D0 - MX28_PAD_LCD_D01__LCD_D1 - MX28_PAD_LCD_D02__LCD_D2 - MX28_PAD_LCD_D03__LCD_D3 - MX28_PAD_LCD_D04__LCD_D4 - MX28_PAD_LCD_D05__LCD_D5 - MX28_PAD_LCD_D06__LCD_D6 - MX28_PAD_LCD_D07__LCD_D7 - MX28_PAD_LCD_D08__LCD_D8 - MX28_PAD_LCD_D09__LCD_D9 - MX28_PAD_LCD_D10__LCD_D10 - MX28_PAD_LCD_D11__LCD_D11 - MX28_PAD_LCD_D12__LCD_D12 - MX28_PAD_LCD_D13__LCD_D13 - MX28_PAD_LCD_D14__LCD_D14 - MX28_PAD_LCD_D15__LCD_D15 - MX28_PAD_LCD_D16__LCD_D16 - MX28_PAD_LCD_D17__LCD_D17 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - lcdif_pins_cfa10049: lcdif-evk@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_RD_E__LCD_VSYNC - MX28_PAD_LCD_WR_RWN__LCD_HSYNC - MX28_PAD_LCD_RS__LCD_DOTCLK - MX28_PAD_LCD_CS__LCD_ENABLE - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - lcdif_pins_cfa10049_pullup: lcdif-10049-pullup@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_RESET__GPIO_3_30 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - w1_gpio_pins: w1-gpio@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_D21__GPIO_1_21 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; /* 0 will enable the keeper */ - }; - }; - - lcdif@80030000 { - pinctrl-names = "default"; - pinctrl-0 = <&lcdif_18bit_pins_cfa10049 - &lcdif_pins_cfa10049 - &lcdif_pins_cfa10049_pullup>; - display = <&display0>; - status = "okay"; - - display0: display0 { - bits-per-pixel = <32>; - bus-width = <18>; - - display-timings { - native-mode = <&timing0>; - timing0: timing0 { - clock-frequency = <9216000>; - hactive = <320>; - vactive = <480>; - hback-porch = <2>; - hfront-porch = <2>; - vback-porch = <2>; - vfront-porch = <2>; - hsync-len = <15>; - vsync-len = <15>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - }; - }; - }; - - apbx@80040000 { - pwm: pwm@80064000 { - pinctrl-names = "default"; - pinctrl-0 = <&pwm3_pins_b>; - status = "okay"; - }; - - i2c1: i2c@8005a000 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; - status = "okay"; - }; - - usbphy1: usbphy@8007e000 { - status = "okay"; - }; - - lradc@80050000 { - status = "okay"; - fsl,lradc-touchscreen-wires = <4>; - }; - }; - }; - - ahb@80080000 { - usb1: usb@80090000 { - vbus-supply = <®_usb1_vbus>; - pinctrl-0 = <&usb1_pins_a>; - pinctrl-names = "default"; - status = "okay"; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_usb1_vbus: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&usb_pins_cfa10049>; - regulator-name = "usb1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio0 7 1>; - }; - }; - - ahb@80080000 { - mac0: ethernet@800f0000 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&mac0_pins_a - &mac0_pins_cfa10049>; - phy-reset-gpios = <&gpio2 21 GPIO_ACTIVE_LOW>; - phy-reset-duration = <100>; - status = "okay"; - }; - }; - - spi2 { - compatible = "spi-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&spi2_pins_cfa10049>; - status = "okay"; - gpio-sck = <&gpio2 16 0>; - gpio-mosi = <&gpio2 17 0>; - gpio-miso = <&gpio2 18 0>; - cs-gpios = <&gpio3 5 0>; - num-chipselects = <1>; - #address-cells = <1>; - #size-cells = <0>; - - hx8357: hx8357@0 { - compatible = "himax,hx8357b", "himax,hx8357"; - reg = <0>; - spi-max-frequency = <100000>; - spi-cpol; - spi-cpha; - gpios-reset = <&gpio3 30 0>; - im-gpios = <&gpio5 4 0 &gpio5 5 0 &gpio5 6 0>; - }; - }; - - spi3 { - compatible = "spi-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&spi3_pins_cfa10049>; - status = "okay"; - gpio-sck = <&gpio0 24 0>; - gpio-mosi = <&gpio0 28 0>; - cs-gpios = <&gpio0 17 0 &gpio0 26 0 &gpio0 27 0>; - num-chipselects = <3>; - #address-cells = <1>; - #size-cells = <0>; - - gpio5: gpio5@0 { - compatible = "fairchild,74hc595"; - gpio-controller; - #gpio-cells = <2>; - reg = <0>; - registers-number = <2>; - spi-max-frequency = <100000>; - }; - - gpio6: gpio6@1 { - compatible = "fairchild,74hc595"; - gpio-controller; - #gpio-cells = <2>; - reg = <1>; - registers-number = <4>; - spi-max-frequency = <100000>; - }; - - dac0: dh2228@2 { - compatible = "rohm,dh2228fv"; - reg = <2>; - spi-max-frequency = <100000>; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&rotary_btn_pins_cfa10049>; - - rotary_button { - label = "rotary_button"; - gpios = <&gpio3 26 1>; - debounce-interval = <10>; - linux,code = <28>; - }; - }; - - rotary { - compatible = "rotary-encoder"; - pinctrl-names = "default"; - pinctrl-0 = <&rotary_pins_cfa10049>; - gpios = <&gpio3 24 1>, <&gpio3 25 1>; - linux,axis = <1>; /* REL_Y */ - rotary-encoder,relative-axis; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 3 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - - }; - - onewire { - compatible = "w1-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&w1_gpio_pins>; - status = "okay"; - gpios = <&gpio1 21 0>; - }; -}; diff --git a/sys/gnu/dts/arm/imx28-cfa10055.dts b/sys/gnu/dts/arm/imx28-cfa10055.dts deleted file mode 100644 index d05c370dfc1..00000000000 --- a/sys/gnu/dts/arm/imx28-cfa10055.dts +++ /dev/null @@ -1,161 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Crystalfontz America, Inc. - * Free Electrons - */ - -/* - * The CFA-10055 is an expansion board for the CFA-10036 module and - * CFA-10037, thus we need to include the CFA-10037 DTS. - */ -#include "imx28-cfa10037.dts" - -/ { - model = "Crystalfontz CFA-10055 Board"; - compatible = "crystalfontz,cfa10055", "crystalfontz,cfa10037", "crystalfontz,cfa10036", "fsl,imx28"; - - apb@80000000 { - apbh@80000000 { - pinctrl@80018000 { - spi2_pins_cfa10055: spi2-cfa10055@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SSP2_SCK__GPIO_2_16 - MX28_PAD_SSP2_MOSI__GPIO_2_17 - MX28_PAD_SSP2_MISO__GPIO_2_18 - MX28_PAD_AUART1_TX__GPIO_3_5 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - lcdif_18bit_pins_cfa10055: lcdif-18bit@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_D00__LCD_D0 - MX28_PAD_LCD_D01__LCD_D1 - MX28_PAD_LCD_D02__LCD_D2 - MX28_PAD_LCD_D03__LCD_D3 - MX28_PAD_LCD_D04__LCD_D4 - MX28_PAD_LCD_D05__LCD_D5 - MX28_PAD_LCD_D06__LCD_D6 - MX28_PAD_LCD_D07__LCD_D7 - MX28_PAD_LCD_D08__LCD_D8 - MX28_PAD_LCD_D09__LCD_D9 - MX28_PAD_LCD_D10__LCD_D10 - MX28_PAD_LCD_D11__LCD_D11 - MX28_PAD_LCD_D12__LCD_D12 - MX28_PAD_LCD_D13__LCD_D13 - MX28_PAD_LCD_D14__LCD_D14 - MX28_PAD_LCD_D15__LCD_D15 - MX28_PAD_LCD_D16__LCD_D16 - MX28_PAD_LCD_D17__LCD_D17 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - lcdif_pins_cfa10055: lcdif-evk@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_RD_E__LCD_VSYNC - MX28_PAD_LCD_WR_RWN__LCD_HSYNC - MX28_PAD_LCD_RS__LCD_DOTCLK - MX28_PAD_LCD_CS__LCD_ENABLE - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - lcdif_pins_cfa10055_pullup: lcdif-10055-pullup@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_RESET__GPIO_3_30 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - }; - - lcdif@80030000 { - pinctrl-names = "default"; - pinctrl-0 = <&lcdif_18bit_pins_cfa10055 - &lcdif_pins_cfa10055 - &lcdif_pins_cfa10055_pullup>; - display = <&display0>; - status = "okay"; - - display0: display0 { - bits-per-pixel = <32>; - bus-width = <18>; - - display-timings { - native-mode = <&timing0>; - timing0: timing0 { - clock-frequency = <9216000>; - hactive = <320>; - vactive = <480>; - hback-porch = <2>; - hfront-porch = <2>; - vback-porch = <2>; - vfront-porch = <2>; - hsync-len = <15>; - vsync-len = <15>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - }; - }; - }; - - apbx@80040000 { - lradc@80050000 { - fsl,lradc-touchscreen-wires = <4>; - status = "okay"; - }; - - pwm: pwm@80064000 { - pinctrl-names = "default"; - pinctrl-0 = <&pwm3_pins_b>; - status = "okay"; - }; - }; - }; - - spi2 { - compatible = "spi-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&spi2_pins_cfa10055>; - status = "okay"; - gpio-sck = <&gpio2 16 0>; - gpio-mosi = <&gpio2 17 0>; - gpio-miso = <&gpio2 18 0>; - cs-gpios = <&gpio3 5 0>; - num-chipselects = <1>; - #address-cells = <1>; - #size-cells = <0>; - - hx8357: hx8357@0 { - compatible = "himax,hx8357b", "himax,hx8357"; - reg = <0>; - spi-max-frequency = <100000>; - spi-cpol; - spi-cpha; - gpios-reset = <&gpio3 30 0>; - }; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 3 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - }; -}; diff --git a/sys/gnu/dts/arm/imx28-cfa10056.dts b/sys/gnu/dts/arm/imx28-cfa10056.dts deleted file mode 100644 index c1060bd5f17..00000000000 --- a/sys/gnu/dts/arm/imx28-cfa10056.dts +++ /dev/null @@ -1,113 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Free Electrons - */ - -/* - * The CFA-10055 is an expansion board for the CFA-10036 module and - * CFA-10037, thus we need to include the CFA-10037 DTS. - */ -#include "imx28-cfa10037.dts" - -/ { - model = "Crystalfontz CFA-10056 Board"; - compatible = "crystalfontz,cfa10056", "crystalfontz,cfa10037", "crystalfontz,cfa10036", "fsl,imx28"; - - apb@80000000 { - apbh@80000000 { - pinctrl@80018000 { - spi2_pins_cfa10056: spi2-cfa10056@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SSP2_SCK__GPIO_2_16 - MX28_PAD_SSP2_MOSI__GPIO_2_17 - MX28_PAD_SSP2_MISO__GPIO_2_18 - MX28_PAD_AUART1_TX__GPIO_3_5 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - lcdif_pins_cfa10056: lcdif-10056@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_RD_E__LCD_VSYNC - MX28_PAD_LCD_WR_RWN__LCD_HSYNC - MX28_PAD_LCD_RS__LCD_DOTCLK - MX28_PAD_LCD_CS__LCD_ENABLE - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - lcdif_pins_cfa10056_pullup: lcdif-10056-pullup@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_RESET__GPIO_3_30 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - }; - - lcdif@80030000 { - pinctrl-names = "default"; - pinctrl-0 = <&lcdif_24bit_pins_a - &lcdif_pins_cfa10056 - &lcdif_pins_cfa10056_pullup >; - display = <&display0>; - status = "okay"; - - display0: display0 { - bits-per-pixel = <32>; - bus-width = <24>; - - display-timings { - native-mode = <&timing0>; - timing0: timing0 { - clock-frequency = <32000000>; - hactive = <480>; - vactive = <800>; - hback-porch = <2>; - hfront-porch = <2>; - vback-porch = <2>; - vfront-porch = <2>; - hsync-len = <5>; - vsync-len = <5>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - }; - }; - }; - }; - - spi2 { - compatible = "spi-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&spi2_pins_cfa10056>; - status = "okay"; - gpio-sck = <&gpio2 16 0>; - gpio-mosi = <&gpio2 17 0>; - gpio-miso = <&gpio2 18 0>; - cs-gpios = <&gpio3 5 0>; - num-chipselects = <1>; - #address-cells = <1>; - #size-cells = <0>; - - hx8369: hx8369@0 { - compatible = "himax,hx8369a", "himax,hx8369"; - reg = <0>; - spi-max-frequency = <100000>; - spi-cpol; - spi-cpha; - gpios-reset = <&gpio3 30 0>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/imx28-cfa10057.dts b/sys/gnu/dts/arm/imx28-cfa10057.dts deleted file mode 100644 index 2f7e479dbc7..00000000000 --- a/sys/gnu/dts/arm/imx28-cfa10057.dts +++ /dev/null @@ -1,171 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Crystalfontz America, Inc. - * Copyright 2012 Free Electrons - */ - -/* - * The CFA-10057 is an expansion board for the CFA-10036 module, thus we - * need to include the CFA-10036 DTS. - */ -#include "imx28-cfa10036.dts" - -/ { - model = "Crystalfontz CFA-10057 Board"; - compatible = "crystalfontz,cfa10057", "crystalfontz,cfa10036", "fsl,imx28"; - - apb@80000000 { - apbh@80000000 { - pinctrl@80018000 { - usb_pins_cfa10057: usb-10057@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_GPMI_D07__GPIO_0_7 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - lcdif_18bit_pins_cfa10057: lcdif-18bit@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_D00__LCD_D0 - MX28_PAD_LCD_D01__LCD_D1 - MX28_PAD_LCD_D02__LCD_D2 - MX28_PAD_LCD_D03__LCD_D3 - MX28_PAD_LCD_D04__LCD_D4 - MX28_PAD_LCD_D05__LCD_D5 - MX28_PAD_LCD_D06__LCD_D6 - MX28_PAD_LCD_D07__LCD_D7 - MX28_PAD_LCD_D08__LCD_D8 - MX28_PAD_LCD_D09__LCD_D9 - MX28_PAD_LCD_D10__LCD_D10 - MX28_PAD_LCD_D11__LCD_D11 - MX28_PAD_LCD_D12__LCD_D12 - MX28_PAD_LCD_D13__LCD_D13 - MX28_PAD_LCD_D14__LCD_D14 - MX28_PAD_LCD_D15__LCD_D15 - MX28_PAD_LCD_D16__LCD_D16 - MX28_PAD_LCD_D17__LCD_D17 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - lcdif_pins_cfa10057: lcdif-evk@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_RD_E__LCD_VSYNC - MX28_PAD_LCD_WR_RWN__LCD_HSYNC - MX28_PAD_LCD_RS__LCD_DOTCLK - MX28_PAD_LCD_CS__LCD_ENABLE - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - }; - - lcdif@80030000 { - pinctrl-names = "default"; - pinctrl-0 = <&lcdif_18bit_pins_cfa10057 - &lcdif_pins_cfa10057>; - display = <&display0>; - status = "okay"; - - display0: display0 { - bits-per-pixel = <32>; - bus-width = <18>; - - display-timings { - native-mode = <&timing0>; - timing0: timing0 { - clock-frequency = <30000000>; - hactive = <480>; - vactive = <800>; - hfront-porch = <12>; - hback-porch = <2>; - vfront-porch = <5>; - vback-porch = <3>; - hsync-len = <2>; - vsync-len = <2>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - }; - }; - }; - - apbx@80040000 { - lradc@80050000 { - fsl,lradc-touchscreen-wires = <4>; - status = "okay"; - }; - - pwm: pwm@80064000 { - pinctrl-names = "default"; - pinctrl-0 = <&pwm4_pins_a>; - status = "okay"; - }; - - i2c1: i2c@8005a000 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; - status = "okay"; - }; - - usbphy1: usbphy@8007e000 { - status = "okay"; - }; - }; - }; - - ahb@80080000 { - usb1: usb@80090000 { - vbus-supply = <®_usb1_vbus>; - pinctrl-0 = <&usb1_pins_a>; - pinctrl-names = "default"; - status = "okay"; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_usb1_vbus: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&usb_pins_cfa10057>; - regulator-name = "usb1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio0 7 1>; - }; - }; - - ahb@80080000 { - mac0: ethernet@800f0000 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&mac0_pins_a>; - phy-reset-gpios = <&gpio2 21 GPIO_ACTIVE_LOW>; - phy-reset-duration = <100>; - status = "okay"; - }; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 4 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <7>; - }; -}; diff --git a/sys/gnu/dts/arm/imx28-cfa10058.dts b/sys/gnu/dts/arm/imx28-cfa10058.dts deleted file mode 100644 index 4465fd86785..00000000000 --- a/sys/gnu/dts/arm/imx28-cfa10058.dts +++ /dev/null @@ -1,138 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Crystalfontz America, Inc. - * Copyright 2013 Free Electrons - */ - -/* - * The CFA-10058 is an expansion board for the CFA-10036 module, thus we - * need to include the CFA-10036 DTS. - */ -#include "imx28-cfa10036.dts" - -/ { - model = "Crystalfontz CFA-10058 Board"; - compatible = "crystalfontz,cfa10058", "crystalfontz,cfa10036", "fsl,imx28"; - - apb@80000000 { - apbh@80000000 { - pinctrl@80018000 { - usb_pins_cfa10058: usb-10058@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_GPMI_D07__GPIO_0_7 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - lcdif_pins_cfa10058: lcdif-10058@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_RD_E__LCD_VSYNC - MX28_PAD_LCD_WR_RWN__LCD_HSYNC - MX28_PAD_LCD_RS__LCD_DOTCLK - MX28_PAD_LCD_CS__LCD_ENABLE - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - }; - - lcdif@80030000 { - pinctrl-names = "default"; - pinctrl-0 = <&lcdif_24bit_pins_a - &lcdif_pins_cfa10058>; - display = <&display0>; - status = "okay"; - - display0: display0 { - bits-per-pixel = <32>; - bus-width = <24>; - - display-timings { - native-mode = <&timing0>; - timing0: timing0 { - clock-frequency = <30000000>; - hactive = <800>; - vactive = <480>; - hback-porch = <40>; - hfront-porch = <40>; - vback-porch = <13>; - vfront-porch = <29>; - hsync-len = <8>; - vsync-len = <8>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - }; - }; - }; - - apbx@80040000 { - lradc@80050000 { - fsl,lradc-touchscreen-wires = <4>; - status = "okay"; - }; - - pwm: pwm@80064000 { - pinctrl-names = "default"; - pinctrl-0 = <&pwm3_pins_b>; - status = "okay"; - }; - - usbphy1: usbphy@8007e000 { - status = "okay"; - }; - }; - }; - - ahb@80080000 { - usb1: usb@80090000 { - vbus-supply = <®_usb1_vbus>; - pinctrl-0 = <&usb1_pins_a>; - pinctrl-names = "default"; - status = "okay"; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_usb1_vbus: regulator@0 { - pinctrl-names = "default"; - pinctrl-0 = <&usb_pins_cfa10058>; - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "usb1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio0 7 1>; - }; - }; - - ahb@80080000 { - mac0: ethernet@800f0000 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&mac0_pins_a>; - phy-reset-gpios = <&gpio2 21 GPIO_ACTIVE_LOW>; - phy-reset-duration = <100>; - status = "okay"; - }; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 3 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - }; -}; diff --git a/sys/gnu/dts/arm/imx28-duckbill-2-485.dts b/sys/gnu/dts/arm/imx28-duckbill-2-485.dts deleted file mode 100644 index d451fa018d8..00000000000 --- a/sys/gnu/dts/arm/imx28-duckbill-2-485.dts +++ /dev/null @@ -1,184 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (C) 2015-2017 I2SE GmbH - * Copyright (C) 2016 Michael Heimpold - */ - -/dts-v1/; -#include -#include -#include "imx28.dtsi" - -/ { - model = "I2SE Duckbill 2 485"; - compatible = "i2se,duckbill-2-485", "i2se,duckbill-2", "fsl,imx28"; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x08000000>; - }; - - apb@80000000 { - apbh@80000000 { - ssp0: spi@80010000 { - compatible = "fsl,imx28-mmc"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_8bit_pins_a - &mmc0_cd_cfg &mmc0_sck_cfg>; - bus-width = <8>; - vmmc-supply = <®_3p3v>; - status = "okay"; - non-removable; - }; - - ssp2: spi@80014000 { - compatible = "fsl,imx28-mmc"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_4bit_pins_b - &mmc2_cd_cfg &mmc2_sck_cfg_b>; - bus-width = <4>; - vmmc-supply = <®_3p3v>; - status = "okay"; - }; - - pinctrl@80018000 { - pinctrl-names = "default"; - pinctrl-0 = <&hog_pins_a>; - - hog_pins_a: hog@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_D17__GPIO_1_17 /* Revision detection */ - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - mac0_phy_reset_pin: mac0-phy-reset@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_GPMI_ALE__GPIO_0_26 /* PHY Reset */ - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - mac0_phy_int_pin: mac0-phy-int@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_GPMI_D07__GPIO_0_7 /* PHY Interrupt */ - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - led_pins: leds@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SAIF0_MCLK__GPIO_3_20 - MX28_PAD_SAIF0_LRCLK__GPIO_3_21 - MX28_PAD_I2C0_SCL__GPIO_3_24 - MX28_PAD_I2C0_SDA__GPIO_3_25 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - }; - }; - - apbx@80040000 { - lradc@80050000 { - status = "okay"; - }; - - auart0: serial@8006a000 { - pinctrl-names = "default"; - pinctrl-0 = <&auart0_2pins_a>; - status = "okay"; - }; - - duart: serial@80074000 { - pinctrl-names = "default"; - pinctrl-0 = <&duart_pins_a>; - status = "okay"; - }; - - usbphy0: usbphy@8007c000 { - status = "okay"; - }; - }; - }; - - ahb@80080000 { - usb0: usb@80080000 { - status = "okay"; - dr_mode = "peripheral"; - }; - - mac0: ethernet@800f0000 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&mac0_pins_a>, <&mac0_phy_reset_pin>; - phy-supply = <®_3p3v>; - phy-reset-gpios = <&gpio0 26 GPIO_ACTIVE_LOW>; - phy-reset-duration = <25>; - phy-handle = <ðphy>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&mac0_phy_int_pin>; - interrupt-parent = <&gpio0>; - interrupts = <7 IRQ_TYPE_EDGE_FALLING>; - max-speed = <100>; - }; - }; - }; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins>; - - status-red { - label = "duckbill:red:status"; - gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - }; - - status-green { - label = "duckbill:green:status"; - gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - - rs485-red { - label = "duckbill:red:rs485"; - gpios = <&gpio3 24 GPIO_ACTIVE_LOW>; - }; - - rs485-green { - label = "duckbill:green:rs485"; - gpios = <&gpio3 25 GPIO_ACTIVE_LOW>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/imx28-duckbill-2-enocean.dts b/sys/gnu/dts/arm/imx28-duckbill-2-enocean.dts deleted file mode 100644 index bacb846f99e..00000000000 --- a/sys/gnu/dts/arm/imx28-duckbill-2-enocean.dts +++ /dev/null @@ -1,213 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (C) 2015-2017 I2SE GmbH - * Copyright (C) 2016 Michael Heimpold - */ - -/dts-v1/; -#include -#include -#include -#include "imx28.dtsi" - -/ { - model = "I2SE Duckbill 2 EnOcean"; - compatible = "i2se,duckbill-2-enocean", "i2se,duckbill-2", "fsl,imx28"; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x08000000>; - }; - - apb@80000000 { - apbh@80000000 { - ssp0: spi@80010000 { - compatible = "fsl,imx28-mmc"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_8bit_pins_a - &mmc0_cd_cfg &mmc0_sck_cfg>; - bus-width = <8>; - vmmc-supply = <®_3p3v>; - status = "okay"; - non-removable; - }; - - ssp2: spi@80014000 { - compatible = "fsl,imx28-mmc"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_4bit_pins_b - &mmc2_cd_cfg &mmc2_sck_cfg_b>; - bus-width = <4>; - vmmc-supply = <®_3p3v>; - status = "okay"; - }; - - pinctrl@80018000 { - pinctrl-names = "default"; - pinctrl-0 = <&hog_pins_a>; - - hog_pins_a: hog@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_D17__GPIO_1_17 /* Revision detection */ - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - mac0_phy_reset_pin: mac0-phy-reset@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_GPMI_ALE__GPIO_0_26 /* PHY Reset */ - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - mac0_phy_int_pin: mac0-phy-int@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_GPMI_D07__GPIO_0_7 /* PHY Interrupt */ - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - led_pins: leds@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SAIF0_MCLK__GPIO_3_20 - MX28_PAD_SAIF0_LRCLK__GPIO_3_21 - MX28_PAD_AUART0_CTS__GPIO_3_2 - MX28_PAD_I2C0_SCL__GPIO_3_24 - MX28_PAD_I2C0_SDA__GPIO_3_25 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - enocean_button: enocean-button@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_AUART0_RTS__GPIO_3_3 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - }; - }; - - apbx@80040000 { - lradc@80050000 { - status = "okay"; - }; - - auart0: serial@8006a000 { - pinctrl-names = "default"; - pinctrl-0 = <&auart0_2pins_a>; - status = "okay"; - }; - - duart: serial@80074000 { - pinctrl-names = "default"; - pinctrl-0 = <&duart_pins_a>; - status = "okay"; - }; - - usbphy0: usbphy@8007c000 { - status = "okay"; - }; - }; - }; - - ahb@80080000 { - usb0: usb@80080000 { - status = "okay"; - dr_mode = "peripheral"; - }; - - mac0: ethernet@800f0000 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&mac0_pins_a>, <&mac0_phy_reset_pin>; - phy-supply = <®_3p3v>; - phy-reset-gpios = <&gpio0 26 GPIO_ACTIVE_LOW>; - phy-reset-duration = <25>; - phy-handle = <ðphy>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&mac0_phy_int_pin>; - interrupt-parent = <&gpio0>; - interrupts = <7 IRQ_TYPE_EDGE_FALLING>; - max-speed = <100>; - }; - }; - }; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins>; - - status-red { - label = "duckbill:red:status"; - gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - }; - - status-green { - label = "duckbill:green:status"; - gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - - enocean-blue { - label = "duckbill:blue:enocean"; - gpios = <&gpio3 24 GPIO_ACTIVE_LOW>; - }; - - enocean-red { - label = "duckbill:red:enocean"; - gpios = <&gpio3 25 GPIO_ACTIVE_LOW>; - }; - - enocean-green { - label = "duckbill:green:enocean"; - gpios = <&gpio3 2 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&enocean_button>; - - enocean { - label = "EnOcean"; - linux,code = ; - gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/imx28-duckbill-2-spi.dts b/sys/gnu/dts/arm/imx28-duckbill-2-spi.dts deleted file mode 100644 index 0e8be597570..00000000000 --- a/sys/gnu/dts/arm/imx28-duckbill-2-spi.dts +++ /dev/null @@ -1,194 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (C) 2015-2017 I2SE GmbH - * Copyright (C) 2016 Michael Heimpold - */ - -/dts-v1/; -#include -#include -#include "imx28.dtsi" - -/ { - model = "I2SE Duckbill 2 SPI"; - compatible = "i2se,duckbill-2-spi", "i2se,duckbill-2", "fsl,imx28"; - - aliases { - ethernet1 = &qca7000; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x08000000>; - }; - - apb@80000000 { - apbh@80000000 { - ssp0: spi@80010000 { - compatible = "fsl,imx28-mmc"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_8bit_pins_a - &mmc0_cd_cfg &mmc0_sck_cfg>; - bus-width = <8>; - vmmc-supply = <®_3p3v>; - status = "okay"; - non-removable; - }; - - ssp2: spi@80014000 { - compatible = "fsl,imx28-spi"; - pinctrl-names = "default"; - pinctrl-0 = <&spi2_pins_a>; - status = "okay"; - - qca7000: ethernet@0 { - reg = <0>; - compatible = "qca,qca7000"; - pinctrl-names = "default"; - pinctrl-0 = <&qca7000_pins>; - interrupt-parent = <&gpio3>; - interrupts = <3 IRQ_TYPE_EDGE_RISING>; - spi-cpha; - spi-cpol; - spi-max-frequency = <8000000>; - }; - }; - - pinctrl@80018000 { - pinctrl-names = "default"; - pinctrl-0 = <&hog_pins_a>; - - hog_pins_a: hog@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_D17__GPIO_1_17 /* Revision detection */ - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - mac0_phy_reset_pin: mac0-phy-reset@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_GPMI_ALE__GPIO_0_26 /* PHY Reset */ - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - mac0_phy_int_pin: mac0-phy-int@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_GPMI_D07__GPIO_0_7 /* PHY Interrupt */ - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - led_pins: led@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SAIF0_MCLK__GPIO_3_20 - MX28_PAD_SAIF0_LRCLK__GPIO_3_21 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - qca7000_pins: qca7000@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_AUART0_RTS__GPIO_3_3 /* Interrupt */ - MX28_PAD_LCD_D13__GPIO_1_13 /* QCA7K reset */ - MX28_PAD_LCD_D14__GPIO_1_14 /* GPIO 0 */ - MX28_PAD_LCD_D15__GPIO_1_15 /* GPIO 1 */ - MX28_PAD_LCD_D18__GPIO_1_18 /* GPIO 2 */ - MX28_PAD_LCD_D21__GPIO_1_21 /* GPIO 3 */ - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - }; - }; - - apbx@80040000 { - lradc@80050000 { - status = "okay"; - }; - - duart: serial@80074000 { - pinctrl-names = "default"; - pinctrl-0 = <&duart_pins_a>; - status = "okay"; - }; - - usbphy0: usbphy@8007c000 { - status = "okay"; - }; - }; - }; - - ahb@80080000 { - usb0: usb@80080000 { - status = "okay"; - dr_mode = "peripheral"; - }; - - mac0: ethernet@800f0000 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&mac0_pins_a>, <&mac0_phy_reset_pin>; - phy-supply = <®_3p3v>; - phy-reset-gpios = <&gpio0 26 GPIO_ACTIVE_LOW>; - phy-reset-duration = <25>; - phy-handle = <ðphy>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&mac0_phy_int_pin>; - interrupt-parent = <&gpio0>; - interrupts = <7 IRQ_TYPE_EDGE_FALLING>; - max-speed = <100>; - }; - }; - }; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins>; - - status-red { - label = "duckbill:red:status"; - gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - }; - - status-green { - label = "duckbill:green:status"; - gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; -}; diff --git a/sys/gnu/dts/arm/imx28-duckbill-2.dts b/sys/gnu/dts/arm/imx28-duckbill-2.dts deleted file mode 100644 index 23fd3036404..00000000000 --- a/sys/gnu/dts/arm/imx28-duckbill-2.dts +++ /dev/null @@ -1,178 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (C) 2015-2017 I2SE GmbH - * Copyright (C) 2016 Michael Heimpold - */ - -/dts-v1/; -#include -#include -#include "imx28.dtsi" - -/ { - model = "I2SE Duckbill 2"; - compatible = "i2se,duckbill-2", "fsl,imx28"; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x08000000>; - }; - - apb@80000000 { - apbh@80000000 { - ssp0: spi@80010000 { - compatible = "fsl,imx28-mmc"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_8bit_pins_a - &mmc0_cd_cfg &mmc0_sck_cfg>; - bus-width = <8>; - vmmc-supply = <®_3p3v>; - status = "okay"; - non-removable; - }; - - ssp2: spi@80014000 { - compatible = "fsl,imx28-mmc"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_4bit_pins_b - &mmc2_cd_cfg &mmc2_sck_cfg_b>; - bus-width = <4>; - vmmc-supply = <®_3p3v>; - status = "okay"; - }; - - pinctrl@80018000 { - pinctrl-names = "default"; - pinctrl-0 = <&hog_pins_a>; - - hog_pins_a: hog@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_D17__GPIO_1_17 /* Revision detection */ - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - mac0_phy_reset_pin: mac0-phy-reset@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_GPMI_ALE__GPIO_0_26 /* PHY Reset */ - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - mac0_phy_int_pin: mac0-phy-int@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_GPMI_D07__GPIO_0_7 /* PHY Interrupt */ - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - led_pins: leds@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SAIF0_MCLK__GPIO_3_20 - MX28_PAD_SAIF0_LRCLK__GPIO_3_21 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - }; - }; - - apbx@80040000 { - lradc@80050000 { - status = "okay"; - }; - - i2c0: i2c@80058000 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - }; - - auart0: serial@8006a000 { - pinctrl-names = "default"; - pinctrl-0 = <&auart0_2pins_a>; - status = "okay"; - }; - - duart: serial@80074000 { - pinctrl-names = "default"; - pinctrl-0 = <&duart_pins_a>; - status = "okay"; - }; - - usbphy0: usbphy@8007c000 { - status = "okay"; - }; - }; - }; - - ahb@80080000 { - usb0: usb@80080000 { - status = "okay"; - dr_mode = "peripheral"; - }; - - mac0: ethernet@800f0000 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&mac0_pins_a>, <&mac0_phy_reset_pin>; - phy-supply = <®_3p3v>; - phy-reset-gpios = <&gpio0 26 GPIO_ACTIVE_LOW>; - phy-reset-duration = <25>; - phy-handle = <ðphy>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&mac0_phy_int_pin>; - interrupt-parent = <&gpio0>; - interrupts = <7 IRQ_TYPE_EDGE_FALLING>; - max-speed = <100>; - }; - }; - }; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins>; - - status-red { - label = "duckbill:red:status"; - gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - }; - - status-green { - label = "duckbill:green:status"; - gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; -}; diff --git a/sys/gnu/dts/arm/imx28-duckbill.dts b/sys/gnu/dts/arm/imx28-duckbill.dts deleted file mode 100644 index c666afb1244..00000000000 --- a/sys/gnu/dts/arm/imx28-duckbill.dts +++ /dev/null @@ -1,147 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (C) 2013-2014,2016 Michael Heimpold - * Copyright (C) 2015-2017 I2SE GmbH - */ - -/dts-v1/; -#include -#include "imx28.dtsi" - -/ { - model = "I2SE Duckbill"; - compatible = "i2se,duckbill", "fsl,imx28"; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x08000000>; - }; - - apb@80000000 { - apbh@80000000 { - ssp0: spi@80010000 { - compatible = "fsl,imx28-mmc"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_4bit_pins_a - &mmc0_cd_cfg &mmc0_sck_cfg>; - bus-width = <4>; - vmmc-supply = <®_3p3v>; - status = "okay"; - }; - - ssp2: spi@80014000 { - compatible = "fsl,imx28-spi"; - pinctrl-names = "default"; - pinctrl-0 = <&spi2_pins_a>; - status = "okay"; - }; - - pinctrl@80018000 { - pinctrl-names = "default"; - pinctrl-0 = <&hog_pins_a>; - - hog_pins_a: hog@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_D17__GPIO_1_17 /* Revision detection */ - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - mac0_phy_reset_pin: mac0-phy-reset@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SSP0_DATA7__GPIO_2_7 /* PHY Reset */ - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - led_pins: leds@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_AUART1_RX__GPIO_3_4 - MX28_PAD_AUART1_TX__GPIO_3_5 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - }; - }; - - apbx@80040000 { - lradc@80050000 { - status = "okay"; - }; - - i2c0: i2c@80058000 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - }; - - auart0: serial@8006a000 { - pinctrl-names = "default"; - pinctrl-0 = <&auart0_2pins_a>; - status = "okay"; - }; - - duart: serial@80074000 { - pinctrl-names = "default"; - pinctrl-0 = <&duart_pins_a>; - status = "okay"; - }; - - usbphy0: usbphy@8007c000 { - status = "okay"; - }; - }; - }; - - ahb@80080000 { - usb0: usb@80080000 { - status = "okay"; - dr_mode = "peripheral"; - }; - - mac0: ethernet@800f0000 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&mac0_pins_a>, <&mac0_phy_reset_pin>; - phy-supply = <®_3p3v>; - phy-reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>; - phy-reset-duration = <25>; - status = "okay"; - }; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins>; - - status-red { - label = "duckbill:red:status"; - gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - }; - - status-green { - label = "duckbill:green:status"; - gpios = <&gpio3 5 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; -}; diff --git a/sys/gnu/dts/arm/imx28-eukrea-mbmx283lc.dts b/sys/gnu/dts/arm/imx28-eukrea-mbmx283lc.dts deleted file mode 100644 index 29f8a3a245d..00000000000 --- a/sys/gnu/dts/arm/imx28-eukrea-mbmx283lc.dts +++ /dev/null @@ -1,64 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Eukréa Electromatique - * Copyright 2013 Eukréa Electromatique - */ - -/* - * Module contains : i.MX282 + 64MB DDR2 + NAND + Ethernet PHY + RTC - */ - -/dts-v1/; -#include "imx28-eukrea-mbmx28lc.dtsi" - -/ { - model = "Eukrea Electromatique MBMX283LC"; - compatible = "eukrea,mbmx283lc", "eukrea,mbmx28lc", "fsl,imx28"; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x04000000>; - }; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&gpmi_pins_a>; - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - - pcf8563: rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; -}; - - -&mac0 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&mac0_pins_a>; - phy-reset-gpios = <&gpio4 13 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&pinctrl{ - pinctrl-names = "default"; - pinctrl-0 = <&hog_pins_cpuimx283>; - - hog_pins_cpuimx283: hog-cpuimx283@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_ENET0_RX_CLK__GPIO_4_13 - MX28_PAD_ENET0_TX_CLK__GPIO_4_5 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; -}; diff --git a/sys/gnu/dts/arm/imx28-eukrea-mbmx287lc.dts b/sys/gnu/dts/arm/imx28-eukrea-mbmx287lc.dts deleted file mode 100644 index cd875ace168..00000000000 --- a/sys/gnu/dts/arm/imx28-eukrea-mbmx287lc.dts +++ /dev/null @@ -1,43 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Eukréa Electromatique - * Copyright 2013 Eukréa Electromatique - */ - -/* - * Module contains : i.MX287 + 128MB DDR2 + NAND + 2 x Ethernet PHY + RTC - */ - -#include "imx28-eukrea-mbmx283lc.dts" - -/ { - model = "Eukrea Electromatique MBMX287LC"; - compatible = "eukrea,mbmx287lc", "eukrea,mbmx283lc", "eukrea,mbmx28lc", "fsl,imx28"; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x08000000>; - }; -}; - -&mac1 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&mac1_pins_a>; - phy-reset-gpios = <&gpio3 27 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&pinctrl { - pinctrl-names = "default"; - pinctrl-0 = <&hog_pins_cpuimx283 &hog_pins_cpuimx287>; - hog_pins_cpuimx287: hog-cpuimx287@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SPDIF__GPIO_3_27 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; -}; diff --git a/sys/gnu/dts/arm/imx28-eukrea-mbmx28lc.dtsi b/sys/gnu/dts/arm/imx28-eukrea-mbmx28lc.dtsi deleted file mode 100644 index 3280fddaaf0..00000000000 --- a/sys/gnu/dts/arm/imx28-eukrea-mbmx28lc.dtsi +++ /dev/null @@ -1,323 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Eukréa Electromatique - * Copyright 2013 Eukréa Electromatique - */ - -#include -#include -#include "imx28.dtsi" - -/ { - model = "Eukrea Electromatique MBMX28LC"; - compatible = "eukrea,mbmx28lc", "fsl,imx28"; - - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 4 1000000>; - brightness-levels = <0 25 50 75 100 125 150 175 200 225 255>; - default-brightness-level = <10>; - }; - - button-sw3 { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&gpio_button_sw3_pins_mbmx28lc>; - - sw3 { - label = "SW3"; - gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - }; - - button-sw4 { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&gpio_button_sw4_pins_mbmx28lc>; - - sw4 { - label = "SW4"; - gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - }; - - led-d6 { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_d6_pins_mbmx28lc>; - - led1 { - label = "d6"; - gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - }; - }; - - led-d7 { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_d7_pins_mbmx28lc>; - - led1 { - label = "d7"; - gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-on"; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_3p3v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_lcd_3v3: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - pinctrl-names = "default"; - pinctrl-0 = <®_lcd_3v3_pins_mbmx28lc>; - regulator-name = "lcd-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usb0_vbus: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - pinctrl-names = "default"; - pinctrl-0 = <®_usb0_vbus_pins_mbmx28lc>; - regulator-name = "usb0_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 18 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usb1_vbus: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - pinctrl-names = "default"; - pinctrl-0 = <®_usb1_vbus_pins_mbmx28lc>; - regulator-name = "usb1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 19 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - }; - - sound { - compatible = "fsl,imx28-mbmx28lc-sgtl5000", - "fsl,mxs-audio-sgtl5000"; - model = "imx28-mbmx28lc-sgtl5000"; - saif-controllers = <&saif0 &saif1>; - audio-codec = <&sgtl5000>; - }; -}; - -&duart { - pinctrl-names = "default"; - pinctrl-0 = <&duart_4pins_a>; - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - - sgtl5000: codec@a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - #sound-dai-cells = <0>; - VDDA-supply = <®_3p3v>; - VDDIO-supply = <®_3p3v>; - clocks = <&saif0>; - }; -}; - -&lcdif { - pinctrl-names = "default"; - pinctrl-0 = <&lcdif_18bit_pins_a &lcdif_pins_mbmx28lc>; - lcd-supply = <®_lcd_3v3>; - display = <&display0>; - status = "okay"; - - display0: display0 { - model = "43WVF1G-0"; - bits-per-pixel = <16>; - bus-width = <18>; - - display-timings { - native-mode = <&timing0>; - timing0: timing0 { - clock-frequency = <9072000>; - hactive = <480>; - vactive = <272>; - hback-porch = <10>; - hfront-porch = <5>; - vback-porch = <8>; - vfront-porch = <8>; - hsync-len = <40>; - vsync-len = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - }; -}; - -&lradc { - fsl,lradc-touchscreen-wires = <4>; - status = "okay"; -}; - -&pinctrl { - gpio_button_sw3_pins_mbmx28lc: gpio-button-sw3-mbmx28lc@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_D21__GPIO_1_21 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - gpio_button_sw4_pins_mbmx28lc: gpio-button-sw4-mbmx28lc@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_D20__GPIO_1_20 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - lcdif_pins_mbmx28lc: lcdif-mbmx28lc@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_VSYNC__LCD_VSYNC - MX28_PAD_LCD_HSYNC__LCD_HSYNC - MX28_PAD_LCD_DOTCLK__LCD_DOTCLK - MX28_PAD_LCD_ENABLE__LCD_ENABLE - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - led_d6_pins_mbmx28lc: led-d6-mbmx28lc@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_D23__GPIO_1_23 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - led_d7_pins_mbmx28lc: led-d7-mbmx28lc@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_D22__GPIO_1_22 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - reg_lcd_3v3_pins_mbmx28lc: lcd-3v3-mbmx28lc@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_RESET__GPIO_3_30 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - reg_usb0_vbus_pins_mbmx28lc: reg-usb0-vbus-mbmx28lc@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_D18__GPIO_1_18 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - reg_usb1_vbus_pins_mbmx28lc: reg-usb1-vbus-mbmx28lc@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_D19__GPIO_1_19 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm4_pins_a>; - status = "okay"; -}; - -&saif0 { - pinctrl-names = "default"; - pinctrl-0 = <&saif0_pins_a>; - status = "okay"; -}; - -&saif1 { - pinctrl-names = "default"; - pinctrl-0 = <&saif1_pins_a>; - fsl,saif-master = <&saif0>; - status = "okay"; -}; - -&ssp0 { - compatible = "fsl,imx28-mmc"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_cd_cfg &mmc0_sck_cfg>; - bus-width = <4>; - cd-inverted; - status = "okay"; -}; - -&usb0 { - disable-over-current; - vbus-supply = <®_usb0_vbus>; - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_pins_b>; -}; - -&usb1 { - vbus-supply = <®_usb1_vbus>; - status = "okay"; -}; - -&usbphy0 { - status = "okay"; -}; - -&usbphy1 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx28-evk.dts b/sys/gnu/dts/arm/imx28-evk.dts deleted file mode 100644 index 96c1d106bc6..00000000000 --- a/sys/gnu/dts/arm/imx28-evk.dts +++ /dev/null @@ -1,360 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// -// Copyright 2012 Freescale Semiconductor, Inc. - -/dts-v1/; -#include "imx28.dtsi" - -/ { - model = "Freescale i.MX28 Evaluation Kit"; - compatible = "fsl,imx28-evk", "fsl,imx28"; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x08000000>; - }; - - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_vddio_sd0: regulator-vddio-sd0 { - compatible = "regulator-fixed"; - regulator-name = "vddio-sd0"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio3 28 0>; - }; - - reg_fec_3v3: regulator-fec-3v3 { - compatible = "regulator-fixed"; - regulator-name = "fec-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 15 0>; - }; - - reg_usb0_vbus: regulator-usb0-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb0_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 9 0>; - enable-active-high; - }; - - reg_usb1_vbus: regulator-usb1-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 8 0>; - enable-active-high; - }; - - reg_lcd_3v3: regulator-lcd-3v3 { - compatible = "regulator-fixed"; - regulator-name = "lcd-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio3 30 0>; - enable-active-high; - }; - - reg_can_3v3: regulator-can-3v3 { - compatible = "regulator-fixed"; - regulator-name = "can-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 13 0>; - enable-active-high; - }; - - reg_lcd_5v: regulator-lcd-5v { - compatible = "regulator-fixed"; - regulator-name = "lcd-5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - panel { - compatible = "sii,43wvf1g"; - backlight = <&backlight_display>; - dvdd-supply = <®_lcd_3v3>; - avdd-supply = <®_lcd_5v>; - - port { - panel_in: endpoint { - remote-endpoint = <&display_out>; - }; - }; - }; - - apb@80000000 { - apbh@80000000 { - gpmi-nand@8000c000 { - pinctrl-names = "default"; - pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg - &gpmi_pins_evk>; - status = "okay"; - }; - - ssp0: spi@80010000 { - compatible = "fsl,imx28-mmc"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_8bit_pins_a - &mmc0_cd_cfg &mmc0_sck_cfg>; - bus-width = <8>; - wp-gpios = <&gpio2 12 0>; - vmmc-supply = <®_vddio_sd0>; - status = "okay"; - }; - - ssp1: spi@80012000 { - compatible = "fsl,imx28-mmc"; - bus-width = <8>; - wp-gpios = <&gpio0 28 0>; - }; - - ssp2: spi@80014000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx28-spi"; - pinctrl-names = "default"; - pinctrl-0 = <&spi2_pins_a>; - status = "okay"; - - flash: m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "sst,sst25vf016b", "jedec,spi-nor"; - spi-max-frequency = <40000000>; - reg = <0>; - }; - }; - - pinctrl@80018000 { - pinctrl-names = "default"; - pinctrl-0 = <&hog_pins_a>; - - hog_pins_a: hog@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SSP1_CMD__GPIO_2_13 - MX28_PAD_SSP1_DATA3__GPIO_2_15 - MX28_PAD_ENET0_RX_CLK__GPIO_4_13 - MX28_PAD_SSP1_SCK__GPIO_2_12 - MX28_PAD_PWM3__GPIO_3_28 - MX28_PAD_LCD_RESET__GPIO_3_30 - MX28_PAD_AUART2_RX__GPIO_3_8 - MX28_PAD_AUART2_TX__GPIO_3_9 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - led_pin_gpio3_5: led_gpio3_5@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_AUART1_TX__GPIO_3_5 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - gpmi_pins_evk: gpmi-nand-evk@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_GPMI_CE1N__GPMI_CE1N - MX28_PAD_GPMI_RDY1__GPMI_READY1 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - lcdif_pins_evk: lcdif-evk@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_RD_E__LCD_VSYNC - MX28_PAD_LCD_WR_RWN__LCD_HSYNC - MX28_PAD_LCD_RS__LCD_DOTCLK - MX28_PAD_LCD_CS__LCD_ENABLE - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - }; - - lcdif@80030000 { - pinctrl-names = "default"; - pinctrl-0 = <&lcdif_24bit_pins_a - &lcdif_pins_evk>; - status = "okay"; - - port { - display_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; - - can0: can@80032000 { - pinctrl-names = "default"; - pinctrl-0 = <&can0_pins_a>; - xceiver-supply = <®_can_3v3>; - status = "okay"; - }; - - can1: can@80034000 { - pinctrl-names = "default"; - pinctrl-0 = <&can1_pins_a>; - xceiver-supply = <®_can_3v3>; - status = "okay"; - }; - }; - - apbx@80040000 { - saif0: saif@80042000 { - pinctrl-names = "default"; - pinctrl-0 = <&saif0_pins_a>; - status = "okay"; - }; - - saif1: saif@80046000 { - pinctrl-names = "default"; - pinctrl-0 = <&saif1_pins_a>; - fsl,saif-master = <&saif0>; - status = "okay"; - }; - - lradc@80050000 { - status = "okay"; - fsl,lradc-touchscreen-wires = <4>; - fsl,ave-ctrl = <4>; - fsl,ave-delay = <2>; - fsl,settling = <10>; - }; - - i2c0: i2c@80058000 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - - sgtl5000: codec@a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - #sound-dai-cells = <0>; - VDDA-supply = <®_3p3v>; - VDDIO-supply = <®_3p3v>; - clocks = <&saif0>; - }; - - at24@51 { - compatible = "atmel,24c32"; - pagesize = <32>; - reg = <0x51>; - }; - }; - - pwm: pwm@80064000 { - pinctrl-names = "default"; - pinctrl-0 = <&pwm2_pins_a>; - status = "okay"; - }; - - duart: serial@80074000 { - pinctrl-names = "default"; - pinctrl-0 = <&duart_pins_a>; - status = "okay"; - }; - - auart0: serial@8006a000 { - pinctrl-names = "default"; - pinctrl-0 = <&auart0_pins_a>; - uart-has-rtscts; - status = "okay"; - }; - - auart3: serial@80070000 { - pinctrl-names = "default"; - pinctrl-0 = <&auart3_pins_a>; - status = "okay"; - }; - - usbphy0: usbphy@8007c000 { - status = "okay"; - }; - - usbphy1: usbphy@8007e000 { - status = "okay"; - }; - }; - }; - - ahb@80080000 { - usb0: usb@80080000 { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_pins_a>; - vbus-supply = <®_usb0_vbus>; - status = "okay"; - }; - - usb1: usb@80090000 { - vbus-supply = <®_usb1_vbus>; - status = "okay"; - }; - - mac0: ethernet@800f0000 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&mac0_pins_a>; - phy-supply = <®_fec_3v3>; - phy-reset-gpios = <&gpio4 13 GPIO_ACTIVE_LOW>; - phy-reset-duration = <100>; - status = "okay"; - }; - - mac1: ethernet@800f4000 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&mac1_pins_a>; - status = "okay"; - }; - }; - - sound { - compatible = "fsl,imx28-evk-sgtl5000", - "fsl,mxs-audio-sgtl5000"; - model = "imx28-evk-sgtl5000"; - saif-controllers = <&saif0 &saif1>; - audio-codec = <&sgtl5000>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pin_gpio3_5>; - - user { - label = "Heartbeat"; - gpios = <&gpio3 5 0>; - linux,default-trigger = "heartbeat"; - }; - }; - - backlight_display: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 2 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - }; -}; diff --git a/sys/gnu/dts/arm/imx28-m28.dtsi b/sys/gnu/dts/arm/imx28-m28.dtsi deleted file mode 100644 index 0bac72d5351..00000000000 --- a/sys/gnu/dts/arm/imx28-m28.dtsi +++ /dev/null @@ -1,56 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (C) 2014 Marek Vasut - */ - -#include "imx28.dtsi" - -/ { - model = "Aries/DENX M28"; - compatible = "aries,m28", "denx,m28", "fsl,imx28"; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x08000000>; - }; - - apb@80000000 { - apbh@80000000 { - gpmi-nand@8000c000 { - #address-cells = <1>; - #size-cells = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>; - status = "okay"; - }; - }; - - apbx@80040000 { - i2c0: i2c@80058000 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - - rtc: rtc@68 { - compatible = "st,m41t62"; - reg = <0x68>; - }; - }; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_3p3v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; -}; diff --git a/sys/gnu/dts/arm/imx28-m28cu3.dts b/sys/gnu/dts/arm/imx28-m28cu3.dts deleted file mode 100644 index 91bd6deffee..00000000000 --- a/sys/gnu/dts/arm/imx28-m28cu3.dts +++ /dev/null @@ -1,266 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (C) 2013 Marek Vasut - */ - -/dts-v1/; -#include "imx28.dtsi" - -/ { - model = "MSR M28CU3"; - compatible = "msr,m28cu3", "fsl,imx28"; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x08000000>; - }; - - apb@80000000 { - apbh@80000000 { - gpmi-nand@8000c000 { - #address-cells = <1>; - #size-cells = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>; - status = "okay"; - - partition@0 { - label = "gpmi-nfc-0-boot"; - reg = <0x00000000 0x01400000>; - read-only; - }; - - partition@1 { - label = "gpmi-nfc-general-use"; - reg = <0x01400000 0x0ec00000>; - }; - }; - - ssp0: spi@80010000 { - compatible = "fsl,imx28-mmc"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_4bit_pins_a - &mmc0_cd_cfg - &mmc0_sck_cfg>; - bus-width = <4>; - vmmc-supply = <®_vddio_sd0>; - status = "okay"; - }; - - ssp2: spi@80014000 { - compatible = "fsl,imx28-mmc"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_4bit_pins_a - &mmc2_cd_cfg - &mmc2_sck_cfg_a>; - bus-width = <4>; - vmmc-supply = <®_vddio_sd1>; - status = "okay"; - }; - - pinctrl@80018000 { - pinctrl-names = "default"; - pinctrl-0 = <&hog_pins_a>; - - hog_pins_a: hog@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SSP2_SS0__GPIO_2_19 - MX28_PAD_PWM4__GPIO_3_29 - MX28_PAD_AUART2_RX__GPIO_3_8 - MX28_PAD_ENET0_RX_CLK__GPIO_4_13 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - lcdif_pins_m28: lcdif-m28@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_VSYNC__LCD_VSYNC - MX28_PAD_LCD_HSYNC__LCD_HSYNC - MX28_PAD_LCD_DOTCLK__LCD_DOTCLK - MX28_PAD_LCD_RESET__LCD_RESET - MX28_PAD_LCD_CS__LCD_ENABLE - MX28_PAD_AUART1_TX__GPIO_3_5 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - led_pins_gpio: leds-m28@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SSP3_MISO__GPIO_2_26 - MX28_PAD_SSP3_SCK__GPIO_2_24 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - }; - - ocotp@8002c000 { - status = "okay"; - }; - - lcdif@80030000 { - pinctrl-names = "default"; - pinctrl-0 = <&lcdif_24bit_pins_a - &lcdif_pins_m28>; - display = <&display0>; - status = "okay"; - - display0: display0 { - bits-per-pixel = <32>; - bus-width = <24>; - - display-timings { - native-mode = <&timing0>; - timing0: timing0 { - clock-frequency = <6410256>; - hactive = <320>; - vactive = <240>; - hback-porch = <38>; - hfront-porch = <20>; - vback-porch = <15>; - vfront-porch = <5>; - hsync-len = <30>; - vsync-len = <3>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - }; - }; - }; - - apbx@80040000 { - duart: serial@80074000 { - pinctrl-names = "default"; - pinctrl-0 = <&duart_pins_b>; - status = "okay"; - }; - - usbphy1: usbphy@8007e000 { - status = "okay"; - }; - - auart0: serial@8006a000 { - pinctrl-names = "default"; - pinctrl-0 = <&auart0_2pins_a>; - status = "okay"; - }; - - auart3: serial@80070000 { - pinctrl-names = "default"; - pinctrl-0 = <&auart3_2pins_b>; - status = "okay"; - }; - - pwm: pwm@80064000 { - pinctrl-names = "default"; - pinctrl-0 = <&pwm3_pins_a>; - status = "okay"; - }; - }; - }; - - ahb@80080000 { - usb1: usb@80090000 { - vbus-supply = <®_usb1_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&usb1_pins_a>; - disable-over-current; - status = "okay"; - }; - - mac0: ethernet@800f0000 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&mac0_pins_a>; - phy-reset-gpios = <&gpio4 13 GPIO_ACTIVE_LOW>; - phy-reset-duration = <100>; - status = "okay"; - }; - - mac1: ethernet@800f4000 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&mac1_pins_a>; - status = "okay"; - }; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 3 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_gpio>; - - user1 { - label = "sd0-led"; - gpios = <&gpio2 26 0>; - linux,default-trigger = "mmc0"; - }; - - user2 { - label = "sd1-led"; - gpios = <&gpio2 24 0>; - linux,default-trigger = "mmc2"; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_3p3v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_vddio_sd0: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "vddio-sd0"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio3 29 0>; - }; - - reg_vddio_sd1: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "vddio-sd1"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 19 0>; - }; - - reg_usb1_vbus: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "usb1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 8 0>; - enable-active-high; - }; - }; -}; diff --git a/sys/gnu/dts/arm/imx28-m28evk.dts b/sys/gnu/dts/arm/imx28-m28evk.dts deleted file mode 100644 index f3bddc5ada4..00000000000 --- a/sys/gnu/dts/arm/imx28-m28evk.dts +++ /dev/null @@ -1,271 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - - * Copyright (C) 2012 Marek Vasut - */ - -/dts-v1/; -#include "imx28-m28.dtsi" - -/ { - model = "Aries/DENX M28EVK"; - compatible = "aries,m28evk", "denx,m28evk", "fsl,imx28"; - - apb@80000000 { - apbh@80000000 { - ssp0: spi@80010000 { - compatible = "fsl,imx28-mmc"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_8bit_pins_a - &mmc0_cd_cfg - &mmc0_sck_cfg>; - bus-width = <8>; - wp-gpios = <&gpio3 10 0>; - vmmc-supply = <®_vddio_sd0>; - status = "okay"; - }; - - ssp2: spi@80014000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx28-spi"; - pinctrl-names = "default"; - pinctrl-0 = <&spi2_pins_a>; - status = "okay"; - - flash: m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "m25p80", "jedec,spi-nor"; - spi-max-frequency = <40000000>; - reg = <0>; - }; - }; - - pinctrl@80018000 { - pinctrl-names = "default"; - pinctrl-0 = <&hog_pins_a>; - - hog_pins_a: hog@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_PWM3__GPIO_3_28 - MX28_PAD_AUART2_CTS__GPIO_3_10 - MX28_PAD_AUART2_RTS__GPIO_3_11 - MX28_PAD_AUART3_RX__GPIO_3_12 - MX28_PAD_AUART3_TX__GPIO_3_13 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - lcdif_pins_m28: lcdif-m28@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_DOTCLK__LCD_DOTCLK - MX28_PAD_LCD_ENABLE__LCD_ENABLE - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - }; - - lcdif@80030000 { - pinctrl-names = "default"; - pinctrl-0 = <&lcdif_24bit_pins_a - &lcdif_pins_m28>; - display = <&display0>; - status = "okay"; - - display0: display0 { - bits-per-pixel = <16>; - bus-width = <18>; - - display-timings { - native-mode = <&timing0>; - timing0: timing0 { - clock-frequency = <33260000>; - hactive = <800>; - vactive = <480>; - hback-porch = <0>; - hfront-porch = <256>; - vback-porch = <0>; - vfront-porch = <45>; - hsync-len = <1>; - vsync-len = <1>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - }; - }; - - can0: can@80032000 { - pinctrl-names = "default"; - pinctrl-0 = <&can0_pins_a>; - status = "okay"; - }; - - can1: can@80034000 { - pinctrl-names = "default"; - pinctrl-0 = <&can1_pins_a>; - status = "okay"; - }; - }; - - apbx@80040000 { - saif0: saif@80042000 { - pinctrl-names = "default"; - pinctrl-0 = <&saif0_pins_a>; - status = "okay"; - }; - - saif1: saif@80046000 { - pinctrl-names = "default"; - pinctrl-0 = <&saif1_pins_a>; - fsl,saif-master = <&saif0>; - status = "okay"; - }; - - i2c0: i2c@80058000 { - sgtl5000: codec@a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - #sound-dai-cells = <0>; - VDDA-supply = <®_3p3v>; - VDDIO-supply = <®_3p3v>; - clocks = <&saif0>; - }; - - eeprom: eeprom@51 { - compatible = "atmel,24c128"; - reg = <0x51>; - pagesize = <32>; - }; - }; - - lradc@80050000 { - status = "okay"; - fsl,lradc-touchscreen-wires = <4>; - }; - - duart: serial@80074000 { - pinctrl-names = "default"; - pinctrl-0 = <&duart_pins_a>; - status = "okay"; - }; - - usbphy0: usbphy@8007c000 { - status = "okay"; - }; - - usbphy1: usbphy@8007e000 { - status = "okay"; - }; - - auart0: serial@8006a000 { - pinctrl-names = "default"; - pinctrl-0 = <&auart0_pins_a>; - status = "okay"; - }; - - auart1: serial@8006c000 { - pinctrl-names = "default"; - pinctrl-0 = <&auart1_pins_a>; - status = "okay"; - }; - - auart2: serial@8006e000 { - pinctrl-names = "default"; - pinctrl-0 = <&auart2_2pins_b>; - status = "okay"; - }; - - pwm: pwm@80064000 { - pinctrl-names = "default"; - pinctrl-0 = <&pwm4_pins_a>; - status = "okay"; - }; - }; - }; - - ahb@80080000 { - usb0: usb@80080000 { - vbus-supply = <®_usb0_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&usb0_pins_a>; - status = "okay"; - }; - - usb1: usb@80090000 { - vbus-supply = <®_usb1_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&usb1_pins_a>; - status = "okay"; - }; - - mac0: ethernet@800f0000 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&mac0_pins_a>; - clocks = <&clks 57>, <&clks 57>; - clock-names = "ipg", "ahb"; - status = "okay"; - }; - - mac1: ethernet@800f4000 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&mac1_pins_a>; - status = "okay"; - }; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 4 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - }; - - regulators { - reg_vddio_sd0: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "vddio-sd0"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio3 28 0>; - }; - - reg_usb0_vbus: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "usb0_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 12 0>; - }; - - reg_usb1_vbus: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "usb1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 13 0>; - }; - }; - - sound { - compatible = "denx,m28evk-sgtl5000", - "fsl,mxs-audio-sgtl5000"; - model = "m28evk-sgtl5000"; - saif-controllers = <&saif0 &saif1>; - audio-codec = <&sgtl5000>; - }; -}; diff --git a/sys/gnu/dts/arm/imx28-pinfunc.h b/sys/gnu/dts/arm/imx28-pinfunc.h deleted file mode 100644 index e11f69ba0fe..00000000000 --- a/sys/gnu/dts/arm/imx28-pinfunc.h +++ /dev/null @@ -1,506 +0,0 @@ -/* - * Header providing constants for i.MX28 pinctrl bindings. - * - * Copyright (C) 2013 Lothar Waßmann - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#ifndef __DT_BINDINGS_MX28_PINCTRL_H__ -#define __DT_BINDINGS_MX28_PINCTRL_H__ - -#include "mxs-pinfunc.h" - -#define MX28_PAD_GPMI_D00__GPMI_D0 0x0000 -#define MX28_PAD_GPMI_D01__GPMI_D1 0x0010 -#define MX28_PAD_GPMI_D02__GPMI_D2 0x0020 -#define MX28_PAD_GPMI_D03__GPMI_D3 0x0030 -#define MX28_PAD_GPMI_D04__GPMI_D4 0x0040 -#define MX28_PAD_GPMI_D05__GPMI_D5 0x0050 -#define MX28_PAD_GPMI_D06__GPMI_D6 0x0060 -#define MX28_PAD_GPMI_D07__GPMI_D7 0x0070 -#define MX28_PAD_GPMI_CE0N__GPMI_CE0N 0x0100 -#define MX28_PAD_GPMI_CE1N__GPMI_CE1N 0x0110 -#define MX28_PAD_GPMI_CE2N__GPMI_CE2N 0x0120 -#define MX28_PAD_GPMI_CE3N__GPMI_CE3N 0x0130 -#define MX28_PAD_GPMI_RDY0__GPMI_READY0 0x0140 -#define MX28_PAD_GPMI_RDY1__GPMI_READY1 0x0150 -#define MX28_PAD_GPMI_RDY2__GPMI_READY2 0x0160 -#define MX28_PAD_GPMI_RDY3__GPMI_READY3 0x0170 -#define MX28_PAD_GPMI_RDN__GPMI_RDN 0x0180 -#define MX28_PAD_GPMI_WRN__GPMI_WRN 0x0190 -#define MX28_PAD_GPMI_ALE__GPMI_ALE 0x01a0 -#define MX28_PAD_GPMI_CLE__GPMI_CLE 0x01b0 -#define MX28_PAD_GPMI_RESETN__GPMI_RESETN 0x01c0 -#define MX28_PAD_LCD_D00__LCD_D0 0x1000 -#define MX28_PAD_LCD_D01__LCD_D1 0x1010 -#define MX28_PAD_LCD_D02__LCD_D2 0x1020 -#define MX28_PAD_LCD_D03__LCD_D3 0x1030 -#define MX28_PAD_LCD_D04__LCD_D4 0x1040 -#define MX28_PAD_LCD_D05__LCD_D5 0x1050 -#define MX28_PAD_LCD_D06__LCD_D6 0x1060 -#define MX28_PAD_LCD_D07__LCD_D7 0x1070 -#define MX28_PAD_LCD_D08__LCD_D8 0x1080 -#define MX28_PAD_LCD_D09__LCD_D9 0x1090 -#define MX28_PAD_LCD_D10__LCD_D10 0x10a0 -#define MX28_PAD_LCD_D11__LCD_D11 0x10b0 -#define MX28_PAD_LCD_D12__LCD_D12 0x10c0 -#define MX28_PAD_LCD_D13__LCD_D13 0x10d0 -#define MX28_PAD_LCD_D14__LCD_D14 0x10e0 -#define MX28_PAD_LCD_D15__LCD_D15 0x10f0 -#define MX28_PAD_LCD_D16__LCD_D16 0x1100 -#define MX28_PAD_LCD_D17__LCD_D17 0x1110 -#define MX28_PAD_LCD_D18__LCD_D18 0x1120 -#define MX28_PAD_LCD_D19__LCD_D19 0x1130 -#define MX28_PAD_LCD_D20__LCD_D20 0x1140 -#define MX28_PAD_LCD_D21__LCD_D21 0x1150 -#define MX28_PAD_LCD_D22__LCD_D22 0x1160 -#define MX28_PAD_LCD_D23__LCD_D23 0x1170 -#define MX28_PAD_LCD_RD_E__LCD_RD_E 0x1180 -#define MX28_PAD_LCD_WR_RWN__LCD_WR_RWN 0x1190 -#define MX28_PAD_LCD_RS__LCD_RS 0x11a0 -#define MX28_PAD_LCD_CS__LCD_CS 0x11b0 -#define MX28_PAD_LCD_VSYNC__LCD_VSYNC 0x11c0 -#define MX28_PAD_LCD_HSYNC__LCD_HSYNC 0x11d0 -#define MX28_PAD_LCD_DOTCLK__LCD_DOTCLK 0x11e0 -#define MX28_PAD_LCD_ENABLE__LCD_ENABLE 0x11f0 -#define MX28_PAD_SSP0_DATA0__SSP0_D0 0x2000 -#define MX28_PAD_SSP0_DATA1__SSP0_D1 0x2010 -#define MX28_PAD_SSP0_DATA2__SSP0_D2 0x2020 -#define MX28_PAD_SSP0_DATA3__SSP0_D3 0x2030 -#define MX28_PAD_SSP0_DATA4__SSP0_D4 0x2040 -#define MX28_PAD_SSP0_DATA5__SSP0_D5 0x2050 -#define MX28_PAD_SSP0_DATA6__SSP0_D6 0x2060 -#define MX28_PAD_SSP0_DATA7__SSP0_D7 0x2070 -#define MX28_PAD_SSP0_CMD__SSP0_CMD 0x2080 -#define MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT 0x2090 -#define MX28_PAD_SSP0_SCK__SSP0_SCK 0x20a0 -#define MX28_PAD_SSP1_SCK__SSP1_SCK 0x20c0 -#define MX28_PAD_SSP1_CMD__SSP1_CMD 0x20d0 -#define MX28_PAD_SSP1_DATA0__SSP1_D0 0x20e0 -#define MX28_PAD_SSP1_DATA3__SSP1_D3 0x20f0 -#define MX28_PAD_SSP2_SCK__SSP2_SCK 0x2100 -#define MX28_PAD_SSP2_MOSI__SSP2_CMD 0x2110 -#define MX28_PAD_SSP2_MISO__SSP2_D0 0x2120 -#define MX28_PAD_SSP2_SS0__SSP2_D3 0x2130 -#define MX28_PAD_SSP2_SS1__SSP2_D4 0x2140 -#define MX28_PAD_SSP2_SS2__SSP2_D5 0x2150 -#define MX28_PAD_SSP3_SCK__SSP3_SCK 0x2180 -#define MX28_PAD_SSP3_MOSI__SSP3_CMD 0x2190 -#define MX28_PAD_SSP3_MISO__SSP3_D0 0x21a0 -#define MX28_PAD_SSP3_SS0__SSP3_D3 0x21b0 -#define MX28_PAD_AUART0_RX__AUART0_RX 0x3000 -#define MX28_PAD_AUART0_TX__AUART0_TX 0x3010 -#define MX28_PAD_AUART0_CTS__AUART0_CTS 0x3020 -#define MX28_PAD_AUART0_RTS__AUART0_RTS 0x3030 -#define MX28_PAD_AUART1_RX__AUART1_RX 0x3040 -#define MX28_PAD_AUART1_TX__AUART1_TX 0x3050 -#define MX28_PAD_AUART1_CTS__AUART1_CTS 0x3060 -#define MX28_PAD_AUART1_RTS__AUART1_RTS 0x3070 -#define MX28_PAD_AUART2_RX__AUART2_RX 0x3080 -#define MX28_PAD_AUART2_TX__AUART2_TX 0x3090 -#define MX28_PAD_AUART2_CTS__AUART2_CTS 0x30a0 -#define MX28_PAD_AUART2_RTS__AUART2_RTS 0x30b0 -#define MX28_PAD_AUART3_RX__AUART3_RX 0x30c0 -#define MX28_PAD_AUART3_TX__AUART3_TX 0x30d0 -#define MX28_PAD_AUART3_CTS__AUART3_CTS 0x30e0 -#define MX28_PAD_AUART3_RTS__AUART3_RTS 0x30f0 -#define MX28_PAD_PWM0__PWM_0 0x3100 -#define MX28_PAD_PWM1__PWM_1 0x3110 -#define MX28_PAD_PWM2__PWM_2 0x3120 -#define MX28_PAD_SAIF0_MCLK__SAIF0_MCLK 0x3140 -#define MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK 0x3150 -#define MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK 0x3160 -#define MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 0x3170 -#define MX28_PAD_I2C0_SCL__I2C0_SCL 0x3180 -#define MX28_PAD_I2C0_SDA__I2C0_SDA 0x3190 -#define MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 0x31a0 -#define MX28_PAD_SPDIF__SPDIF_TX 0x31b0 -#define MX28_PAD_PWM3__PWM_3 0x31c0 -#define MX28_PAD_PWM4__PWM_4 0x31d0 -#define MX28_PAD_LCD_RESET__LCD_RESET 0x31e0 -#define MX28_PAD_ENET0_MDC__ENET0_MDC 0x4000 -#define MX28_PAD_ENET0_MDIO__ENET0_MDIO 0x4010 -#define MX28_PAD_ENET0_RX_EN__ENET0_RX_EN 0x4020 -#define MX28_PAD_ENET0_RXD0__ENET0_RXD0 0x4030 -#define MX28_PAD_ENET0_RXD1__ENET0_RXD1 0x4040 -#define MX28_PAD_ENET0_TX_CLK__ENET0_TX_CLK 0x4050 -#define MX28_PAD_ENET0_TX_EN__ENET0_TX_EN 0x4060 -#define MX28_PAD_ENET0_TXD0__ENET0_TXD0 0x4070 -#define MX28_PAD_ENET0_TXD1__ENET0_TXD1 0x4080 -#define MX28_PAD_ENET0_RXD2__ENET0_RXD2 0x4090 -#define MX28_PAD_ENET0_RXD3__ENET0_RXD3 0x40a0 -#define MX28_PAD_ENET0_TXD2__ENET0_TXD2 0x40b0 -#define MX28_PAD_ENET0_TXD3__ENET0_TXD3 0x40c0 -#define MX28_PAD_ENET0_RX_CLK__ENET0_RX_CLK 0x40d0 -#define MX28_PAD_ENET0_COL__ENET0_COL 0x40e0 -#define MX28_PAD_ENET0_CRS__ENET0_CRS 0x40f0 -#define MX28_PAD_ENET_CLK__CLKCTRL_ENET 0x4100 -#define MX28_PAD_JTAG_RTCK__JTAG_RTCK 0x4140 -#define MX28_PAD_EMI_D00__EMI_DATA0 0x5000 -#define MX28_PAD_EMI_D01__EMI_DATA1 0x5010 -#define MX28_PAD_EMI_D02__EMI_DATA2 0x5020 -#define MX28_PAD_EMI_D03__EMI_DATA3 0x5030 -#define MX28_PAD_EMI_D04__EMI_DATA4 0x5040 -#define MX28_PAD_EMI_D05__EMI_DATA5 0x5050 -#define MX28_PAD_EMI_D06__EMI_DATA6 0x5060 -#define MX28_PAD_EMI_D07__EMI_DATA7 0x5070 -#define MX28_PAD_EMI_D08__EMI_DATA8 0x5080 -#define MX28_PAD_EMI_D09__EMI_DATA9 0x5090 -#define MX28_PAD_EMI_D10__EMI_DATA10 0x50a0 -#define MX28_PAD_EMI_D11__EMI_DATA11 0x50b0 -#define MX28_PAD_EMI_D12__EMI_DATA12 0x50c0 -#define MX28_PAD_EMI_D13__EMI_DATA13 0x50d0 -#define MX28_PAD_EMI_D14__EMI_DATA14 0x50e0 -#define MX28_PAD_EMI_D15__EMI_DATA15 0x50f0 -#define MX28_PAD_EMI_ODT0__EMI_ODT0 0x5100 -#define MX28_PAD_EMI_DQM0__EMI_DQM0 0x5110 -#define MX28_PAD_EMI_ODT1__EMI_ODT1 0x5120 -#define MX28_PAD_EMI_DQM1__EMI_DQM1 0x5130 -#define MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK 0x5140 -#define MX28_PAD_EMI_CLK__EMI_CLK 0x5150 -#define MX28_PAD_EMI_DQS0__EMI_DQS0 0x5160 -#define MX28_PAD_EMI_DQS1__EMI_DQS1 0x5170 -#define MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN 0x51a0 -#define MX28_PAD_EMI_A00__EMI_ADDR0 0x6000 -#define MX28_PAD_EMI_A01__EMI_ADDR1 0x6010 -#define MX28_PAD_EMI_A02__EMI_ADDR2 0x6020 -#define MX28_PAD_EMI_A03__EMI_ADDR3 0x6030 -#define MX28_PAD_EMI_A04__EMI_ADDR4 0x6040 -#define MX28_PAD_EMI_A05__EMI_ADDR5 0x6050 -#define MX28_PAD_EMI_A06__EMI_ADDR6 0x6060 -#define MX28_PAD_EMI_A07__EMI_ADDR7 0x6070 -#define MX28_PAD_EMI_A08__EMI_ADDR8 0x6080 -#define MX28_PAD_EMI_A09__EMI_ADDR9 0x6090 -#define MX28_PAD_EMI_A10__EMI_ADDR10 0x60a0 -#define MX28_PAD_EMI_A11__EMI_ADDR11 0x60b0 -#define MX28_PAD_EMI_A12__EMI_ADDR12 0x60c0 -#define MX28_PAD_EMI_A13__EMI_ADDR13 0x60d0 -#define MX28_PAD_EMI_A14__EMI_ADDR14 0x60e0 -#define MX28_PAD_EMI_BA0__EMI_BA0 0x6100 -#define MX28_PAD_EMI_BA1__EMI_BA1 0x6110 -#define MX28_PAD_EMI_BA2__EMI_BA2 0x6120 -#define MX28_PAD_EMI_CASN__EMI_CASN 0x6130 -#define MX28_PAD_EMI_RASN__EMI_RASN 0x6140 -#define MX28_PAD_EMI_WEN__EMI_WEN 0x6150 -#define MX28_PAD_EMI_CE0N__EMI_CE0N 0x6160 -#define MX28_PAD_EMI_CE1N__EMI_CE1N 0x6170 -#define MX28_PAD_EMI_CKE__EMI_CKE 0x6180 -#define MX28_PAD_GPMI_D00__SSP1_D0 0x0001 -#define MX28_PAD_GPMI_D01__SSP1_D1 0x0011 -#define MX28_PAD_GPMI_D02__SSP1_D2 0x0021 -#define MX28_PAD_GPMI_D03__SSP1_D3 0x0031 -#define MX28_PAD_GPMI_D04__SSP1_D4 0x0041 -#define MX28_PAD_GPMI_D05__SSP1_D5 0x0051 -#define MX28_PAD_GPMI_D06__SSP1_D6 0x0061 -#define MX28_PAD_GPMI_D07__SSP1_D7 0x0071 -#define MX28_PAD_GPMI_CE0N__SSP3_D0 0x0101 -#define MX28_PAD_GPMI_CE1N__SSP3_D3 0x0111 -#define MX28_PAD_GPMI_CE2N__CAN1_TX 0x0121 -#define MX28_PAD_GPMI_CE3N__CAN1_RX 0x0131 -#define MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT 0x0141 -#define MX28_PAD_GPMI_RDY1__SSP1_CMD 0x0151 -#define MX28_PAD_GPMI_RDY2__CAN0_TX 0x0161 -#define MX28_PAD_GPMI_RDY3__CAN0_RX 0x0171 -#define MX28_PAD_GPMI_RDN__SSP3_SCK 0x0181 -#define MX28_PAD_GPMI_WRN__SSP1_SCK 0x0191 -#define MX28_PAD_GPMI_ALE__SSP3_D1 0x01a1 -#define MX28_PAD_GPMI_CLE__SSP3_D2 0x01b1 -#define MX28_PAD_GPMI_RESETN__SSP3_CMD 0x01c1 -#define MX28_PAD_LCD_D03__ETM_DA8 0x1031 -#define MX28_PAD_LCD_D04__ETM_DA9 0x1041 -#define MX28_PAD_LCD_D08__ETM_DA3 0x1081 -#define MX28_PAD_LCD_D09__ETM_DA4 0x1091 -#define MX28_PAD_LCD_D20__ENET1_1588_EVENT2_OUT 0x1141 -#define MX28_PAD_LCD_D21__ENET1_1588_EVENT2_IN 0x1151 -#define MX28_PAD_LCD_D22__ENET1_1588_EVENT3_OUT 0x1161 -#define MX28_PAD_LCD_D23__ENET1_1588_EVENT3_IN 0x1171 -#define MX28_PAD_LCD_RD_E__LCD_VSYNC 0x1181 -#define MX28_PAD_LCD_WR_RWN__LCD_HSYNC 0x1191 -#define MX28_PAD_LCD_RS__LCD_DOTCLK 0x11a1 -#define MX28_PAD_LCD_CS__LCD_ENABLE 0x11b1 -#define MX28_PAD_LCD_VSYNC__SAIF1_SDATA0 0x11c1 -#define MX28_PAD_LCD_HSYNC__SAIF1_SDATA1 0x11d1 -#define MX28_PAD_LCD_DOTCLK__SAIF1_MCLK 0x11e1 -#define MX28_PAD_SSP0_DATA4__SSP2_D0 0x2041 -#define MX28_PAD_SSP0_DATA5__SSP2_D3 0x2051 -#define MX28_PAD_SSP0_DATA6__SSP2_CMD 0x2061 -#define MX28_PAD_SSP0_DATA7__SSP2_SCK 0x2071 -#define MX28_PAD_SSP1_SCK__SSP2_D1 0x20c1 -#define MX28_PAD_SSP1_CMD__SSP2_D2 0x20d1 -#define MX28_PAD_SSP1_DATA0__SSP2_D6 0x20e1 -#define MX28_PAD_SSP1_DATA3__SSP2_D7 0x20f1 -#define MX28_PAD_SSP2_SCK__AUART2_RX 0x2101 -#define MX28_PAD_SSP2_MOSI__AUART2_TX 0x2111 -#define MX28_PAD_SSP2_MISO__AUART3_RX 0x2121 -#define MX28_PAD_SSP2_SS0__AUART3_TX 0x2131 -#define MX28_PAD_SSP2_SS1__SSP2_D1 0x2141 -#define MX28_PAD_SSP2_SS2__SSP2_D2 0x2151 -#define MX28_PAD_SSP3_SCK__AUART4_TX 0x2181 -#define MX28_PAD_SSP3_MOSI__AUART4_RX 0x2191 -#define MX28_PAD_SSP3_MISO__AUART4_RTS 0x21a1 -#define MX28_PAD_SSP3_SS0__AUART4_CTS 0x21b1 -#define MX28_PAD_AUART0_RX__I2C0_SCL 0x3001 -#define MX28_PAD_AUART0_TX__I2C0_SDA 0x3011 -#define MX28_PAD_AUART0_CTS__AUART4_RX 0x3021 -#define MX28_PAD_AUART0_RTS__AUART4_TX 0x3031 -#define MX28_PAD_AUART1_RX__SSP2_CARD_DETECT 0x3041 -#define MX28_PAD_AUART1_TX__SSP3_CARD_DETECT 0x3051 -#define MX28_PAD_AUART1_CTS__USB0_OVERCURRENT 0x3061 -#define MX28_PAD_AUART1_RTS__USB0_ID 0x3071 -#define MX28_PAD_AUART2_RX__SSP3_D1 0x3081 -#define MX28_PAD_AUART2_TX__SSP3_D2 0x3091 -#define MX28_PAD_AUART2_CTS__I2C1_SCL 0x30a1 -#define MX28_PAD_AUART2_RTS__I2C1_SDA 0x30b1 -#define MX28_PAD_AUART3_RX__CAN0_TX 0x30c1 -#define MX28_PAD_AUART3_TX__CAN0_RX 0x30d1 -#define MX28_PAD_AUART3_CTS__CAN1_TX 0x30e1 -#define MX28_PAD_AUART3_RTS__CAN1_RX 0x30f1 -#define MX28_PAD_PWM0__I2C1_SCL 0x3101 -#define MX28_PAD_PWM1__I2C1_SDA 0x3111 -#define MX28_PAD_PWM2__USB0_ID 0x3121 -#define MX28_PAD_SAIF0_MCLK__PWM_3 0x3141 -#define MX28_PAD_SAIF0_LRCLK__PWM_4 0x3151 -#define MX28_PAD_SAIF0_BITCLK__PWM_5 0x3161 -#define MX28_PAD_SAIF0_SDATA0__PWM_6 0x3171 -#define MX28_PAD_I2C0_SCL__TIMROT_ROTARYA 0x3181 -#define MX28_PAD_I2C0_SDA__TIMROT_ROTARYB 0x3191 -#define MX28_PAD_SAIF1_SDATA0__PWM_7 0x31a1 -#define MX28_PAD_LCD_RESET__LCD_VSYNC 0x31e1 -#define MX28_PAD_ENET0_MDC__GPMI_CE4N 0x4001 -#define MX28_PAD_ENET0_MDIO__GPMI_CE5N 0x4011 -#define MX28_PAD_ENET0_RX_EN__GPMI_CE6N 0x4021 -#define MX28_PAD_ENET0_RXD0__GPMI_CE7N 0x4031 -#define MX28_PAD_ENET0_RXD1__GPMI_READY4 0x4041 -#define MX28_PAD_ENET0_TX_CLK__HSADC_TRIGGER 0x4051 -#define MX28_PAD_ENET0_TX_EN__GPMI_READY5 0x4061 -#define MX28_PAD_ENET0_TXD0__GPMI_READY6 0x4071 -#define MX28_PAD_ENET0_TXD1__GPMI_READY7 0x4081 -#define MX28_PAD_ENET0_RXD2__ENET1_RXD0 0x4091 -#define MX28_PAD_ENET0_RXD3__ENET1_RXD1 0x40a1 -#define MX28_PAD_ENET0_TXD2__ENET1_TXD0 0x40b1 -#define MX28_PAD_ENET0_TXD3__ENET1_TXD1 0x40c1 -#define MX28_PAD_ENET0_RX_CLK__ENET0_RX_ER 0x40d1 -#define MX28_PAD_ENET0_COL__ENET1_TX_EN 0x40e1 -#define MX28_PAD_ENET0_CRS__ENET1_RX_EN 0x40f1 -#define MX28_PAD_GPMI_CE2N__ENET0_RX_ER 0x0122 -#define MX28_PAD_GPMI_CE3N__SAIF1_MCLK 0x0132 -#define MX28_PAD_GPMI_RDY0__USB0_ID 0x0142 -#define MX28_PAD_GPMI_RDY2__ENET0_TX_ER 0x0162 -#define MX28_PAD_GPMI_RDY3__HSADC_TRIGGER 0x0172 -#define MX28_PAD_GPMI_ALE__SSP3_D4 0x01a2 -#define MX28_PAD_GPMI_CLE__SSP3_D5 0x01b2 -#define MX28_PAD_LCD_D00__ETM_DA0 0x1002 -#define MX28_PAD_LCD_D01__ETM_DA1 0x1012 -#define MX28_PAD_LCD_D02__ETM_DA2 0x1022 -#define MX28_PAD_LCD_D03__ETM_DA3 0x1032 -#define MX28_PAD_LCD_D04__ETM_DA4 0x1042 -#define MX28_PAD_LCD_D05__ETM_DA5 0x1052 -#define MX28_PAD_LCD_D06__ETM_DA6 0x1062 -#define MX28_PAD_LCD_D07__ETM_DA7 0x1072 -#define MX28_PAD_LCD_D08__ETM_DA8 0x1082 -#define MX28_PAD_LCD_D09__ETM_DA9 0x1092 -#define MX28_PAD_LCD_D10__ETM_DA10 0x10a2 -#define MX28_PAD_LCD_D11__ETM_DA11 0x10b2 -#define MX28_PAD_LCD_D12__ETM_DA12 0x10c2 -#define MX28_PAD_LCD_D13__ETM_DA13 0x10d2 -#define MX28_PAD_LCD_D14__ETM_DA14 0x10e2 -#define MX28_PAD_LCD_D15__ETM_DA15 0x10f2 -#define MX28_PAD_LCD_D16__ETM_DA7 0x1102 -#define MX28_PAD_LCD_D17__ETM_DA6 0x1112 -#define MX28_PAD_LCD_D18__ETM_DA5 0x1122 -#define MX28_PAD_LCD_D19__ETM_DA4 0x1132 -#define MX28_PAD_LCD_D20__ETM_DA3 0x1142 -#define MX28_PAD_LCD_D21__ETM_DA2 0x1152 -#define MX28_PAD_LCD_D22__ETM_DA1 0x1162 -#define MX28_PAD_LCD_D23__ETM_DA0 0x1172 -#define MX28_PAD_LCD_RD_E__ETM_TCTL 0x1182 -#define MX28_PAD_LCD_WR_RWN__ETM_TCLK 0x1192 -#define MX28_PAD_LCD_HSYNC__ETM_TCTL 0x11d2 -#define MX28_PAD_LCD_DOTCLK__ETM_TCLK 0x11e2 -#define MX28_PAD_SSP1_SCK__ENET0_1588_EVENT2_OUT 0x20c2 -#define MX28_PAD_SSP1_CMD__ENET0_1588_EVENT2_IN 0x20d2 -#define MX28_PAD_SSP1_DATA0__ENET0_1588_EVENT3_OUT 0x20e2 -#define MX28_PAD_SSP1_DATA3__ENET0_1588_EVENT3_IN 0x20f2 -#define MX28_PAD_SSP2_SCK__SAIF0_SDATA1 0x2102 -#define MX28_PAD_SSP2_MOSI__SAIF0_SDATA2 0x2112 -#define MX28_PAD_SSP2_MISO__SAIF1_SDATA1 0x2122 -#define MX28_PAD_SSP2_SS0__SAIF1_SDATA2 0x2132 -#define MX28_PAD_SSP2_SS1__USB1_OVERCURRENT 0x2142 -#define MX28_PAD_SSP2_SS2__USB0_OVERCURRENT 0x2152 -#define MX28_PAD_SSP3_SCK__ENET1_1588_EVENT0_OUT 0x2182 -#define MX28_PAD_SSP3_MOSI__ENET1_1588_EVENT0_IN 0x2192 -#define MX28_PAD_SSP3_MISO__ENET1_1588_EVENT1_OUT 0x21a2 -#define MX28_PAD_SSP3_SS0__ENET1_1588_EVENT1_IN 0x21b2 -#define MX28_PAD_AUART0_RX__DUART_CTS 0x3002 -#define MX28_PAD_AUART0_TX__DUART_RTS 0x3012 -#define MX28_PAD_AUART0_CTS__DUART_RX 0x3022 -#define MX28_PAD_AUART0_RTS__DUART_TX 0x3032 -#define MX28_PAD_AUART1_RX__PWM_0 0x3042 -#define MX28_PAD_AUART1_TX__PWM_1 0x3052 -#define MX28_PAD_AUART1_CTS__TIMROT_ROTARYA 0x3062 -#define MX28_PAD_AUART1_RTS__TIMROT_ROTARYB 0x3072 -#define MX28_PAD_AUART2_RX__SSP3_D4 0x3082 -#define MX28_PAD_AUART2_TX__SSP3_D5 0x3092 -#define MX28_PAD_AUART2_CTS__SAIF1_BITCLK 0x30a2 -#define MX28_PAD_AUART2_RTS__SAIF1_LRCLK 0x30b2 -#define MX28_PAD_AUART3_RX__ENET0_1588_EVENT0_OUT 0x30c2 -#define MX28_PAD_AUART3_TX__ENET0_1588_EVENT0_IN 0x30d2 -#define MX28_PAD_AUART3_CTS__ENET0_1588_EVENT1_OUT 0x30e2 -#define MX28_PAD_AUART3_RTS__ENET0_1588_EVENT1_IN 0x30f2 -#define MX28_PAD_PWM0__DUART_RX 0x3102 -#define MX28_PAD_PWM1__DUART_TX 0x3112 -#define MX28_PAD_PWM2__USB1_OVERCURRENT 0x3122 -#define MX28_PAD_SAIF0_MCLK__AUART4_CTS 0x3142 -#define MX28_PAD_SAIF0_LRCLK__AUART4_RTS 0x3152 -#define MX28_PAD_SAIF0_BITCLK__AUART4_RX 0x3162 -#define MX28_PAD_SAIF0_SDATA0__AUART4_TX 0x3172 -#define MX28_PAD_I2C0_SCL__DUART_RX 0x3182 -#define MX28_PAD_I2C0_SDA__DUART_TX 0x3192 -#define MX28_PAD_SAIF1_SDATA0__SAIF0_SDATA1 0x31a2 -#define MX28_PAD_SPDIF__ENET1_RX_ER 0x31b2 -#define MX28_PAD_ENET0_MDC__SAIF0_SDATA1 0x4002 -#define MX28_PAD_ENET0_MDIO__SAIF0_SDATA2 0x4012 -#define MX28_PAD_ENET0_RX_EN__SAIF1_SDATA1 0x4022 -#define MX28_PAD_ENET0_RXD0__SAIF1_SDATA2 0x4032 -#define MX28_PAD_ENET0_TX_CLK__ENET0_1588_EVENT2_OUT 0x4052 -#define MX28_PAD_ENET0_RXD2__ENET0_1588_EVENT0_OUT 0x4092 -#define MX28_PAD_ENET0_RXD3__ENET0_1588_EVENT0_IN 0x40a2 -#define MX28_PAD_ENET0_TXD2__ENET0_1588_EVENT1_OUT 0x40b2 -#define MX28_PAD_ENET0_TXD3__ENET0_1588_EVENT1_IN 0x40c2 -#define MX28_PAD_ENET0_RX_CLK__ENET0_1588_EVENT2_IN 0x40d2 -#define MX28_PAD_ENET0_COL__ENET0_1588_EVENT3_OUT 0x40e2 -#define MX28_PAD_ENET0_CRS__ENET0_1588_EVENT3_IN 0x40f2 -#define MX28_PAD_GPMI_D00__GPIO_0_0 0x0003 -#define MX28_PAD_GPMI_D01__GPIO_0_1 0x0013 -#define MX28_PAD_GPMI_D02__GPIO_0_2 0x0023 -#define MX28_PAD_GPMI_D03__GPIO_0_3 0x0033 -#define MX28_PAD_GPMI_D04__GPIO_0_4 0x0043 -#define MX28_PAD_GPMI_D05__GPIO_0_5 0x0053 -#define MX28_PAD_GPMI_D06__GPIO_0_6 0x0063 -#define MX28_PAD_GPMI_D07__GPIO_0_7 0x0073 -#define MX28_PAD_GPMI_CE0N__GPIO_0_16 0x0103 -#define MX28_PAD_GPMI_CE1N__GPIO_0_17 0x0113 -#define MX28_PAD_GPMI_CE2N__GPIO_0_18 0x0123 -#define MX28_PAD_GPMI_CE3N__GPIO_0_19 0x0133 -#define MX28_PAD_GPMI_RDY0__GPIO_0_20 0x0143 -#define MX28_PAD_GPMI_RDY1__GPIO_0_21 0x0153 -#define MX28_PAD_GPMI_RDY2__GPIO_0_22 0x0163 -#define MX28_PAD_GPMI_RDY3__GPIO_0_23 0x0173 -#define MX28_PAD_GPMI_RDN__GPIO_0_24 0x0183 -#define MX28_PAD_GPMI_WRN__GPIO_0_25 0x0193 -#define MX28_PAD_GPMI_ALE__GPIO_0_26 0x01a3 -#define MX28_PAD_GPMI_CLE__GPIO_0_27 0x01b3 -#define MX28_PAD_GPMI_RESETN__GPIO_0_28 0x01c3 -#define MX28_PAD_LCD_D00__GPIO_1_0 0x1003 -#define MX28_PAD_LCD_D01__GPIO_1_1 0x1013 -#define MX28_PAD_LCD_D02__GPIO_1_2 0x1023 -#define MX28_PAD_LCD_D03__GPIO_1_3 0x1033 -#define MX28_PAD_LCD_D04__GPIO_1_4 0x1043 -#define MX28_PAD_LCD_D05__GPIO_1_5 0x1053 -#define MX28_PAD_LCD_D06__GPIO_1_6 0x1063 -#define MX28_PAD_LCD_D07__GPIO_1_7 0x1073 -#define MX28_PAD_LCD_D08__GPIO_1_8 0x1083 -#define MX28_PAD_LCD_D09__GPIO_1_9 0x1093 -#define MX28_PAD_LCD_D10__GPIO_1_10 0x10a3 -#define MX28_PAD_LCD_D11__GPIO_1_11 0x10b3 -#define MX28_PAD_LCD_D12__GPIO_1_12 0x10c3 -#define MX28_PAD_LCD_D13__GPIO_1_13 0x10d3 -#define MX28_PAD_LCD_D14__GPIO_1_14 0x10e3 -#define MX28_PAD_LCD_D15__GPIO_1_15 0x10f3 -#define MX28_PAD_LCD_D16__GPIO_1_16 0x1103 -#define MX28_PAD_LCD_D17__GPIO_1_17 0x1113 -#define MX28_PAD_LCD_D18__GPIO_1_18 0x1123 -#define MX28_PAD_LCD_D19__GPIO_1_19 0x1133 -#define MX28_PAD_LCD_D20__GPIO_1_20 0x1143 -#define MX28_PAD_LCD_D21__GPIO_1_21 0x1153 -#define MX28_PAD_LCD_D22__GPIO_1_22 0x1163 -#define MX28_PAD_LCD_D23__GPIO_1_23 0x1173 -#define MX28_PAD_LCD_RD_E__GPIO_1_24 0x1183 -#define MX28_PAD_LCD_WR_RWN__GPIO_1_25 0x1193 -#define MX28_PAD_LCD_RS__GPIO_1_26 0x11a3 -#define MX28_PAD_LCD_CS__GPIO_1_27 0x11b3 -#define MX28_PAD_LCD_VSYNC__GPIO_1_28 0x11c3 -#define MX28_PAD_LCD_HSYNC__GPIO_1_29 0x11d3 -#define MX28_PAD_LCD_DOTCLK__GPIO_1_30 0x11e3 -#define MX28_PAD_LCD_ENABLE__GPIO_1_31 0x11f3 -#define MX28_PAD_SSP0_DATA0__GPIO_2_0 0x2003 -#define MX28_PAD_SSP0_DATA1__GPIO_2_1 0x2013 -#define MX28_PAD_SSP0_DATA2__GPIO_2_2 0x2023 -#define MX28_PAD_SSP0_DATA3__GPIO_2_3 0x2033 -#define MX28_PAD_SSP0_DATA4__GPIO_2_4 0x2043 -#define MX28_PAD_SSP0_DATA5__GPIO_2_5 0x2053 -#define MX28_PAD_SSP0_DATA6__GPIO_2_6 0x2063 -#define MX28_PAD_SSP0_DATA7__GPIO_2_7 0x2073 -#define MX28_PAD_SSP0_CMD__GPIO_2_8 0x2083 -#define MX28_PAD_SSP0_DETECT__GPIO_2_9 0x2093 -#define MX28_PAD_SSP0_SCK__GPIO_2_10 0x20a3 -#define MX28_PAD_SSP1_SCK__GPIO_2_12 0x20c3 -#define MX28_PAD_SSP1_CMD__GPIO_2_13 0x20d3 -#define MX28_PAD_SSP1_DATA0__GPIO_2_14 0x20e3 -#define MX28_PAD_SSP1_DATA3__GPIO_2_15 0x20f3 -#define MX28_PAD_SSP2_SCK__GPIO_2_16 0x2103 -#define MX28_PAD_SSP2_MOSI__GPIO_2_17 0x2113 -#define MX28_PAD_SSP2_MISO__GPIO_2_18 0x2123 -#define MX28_PAD_SSP2_SS0__GPIO_2_19 0x2133 -#define MX28_PAD_SSP2_SS1__GPIO_2_20 0x2143 -#define MX28_PAD_SSP2_SS2__GPIO_2_21 0x2153 -#define MX28_PAD_SSP3_SCK__GPIO_2_24 0x2183 -#define MX28_PAD_SSP3_MOSI__GPIO_2_25 0x2193 -#define MX28_PAD_SSP3_MISO__GPIO_2_26 0x21a3 -#define MX28_PAD_SSP3_SS0__GPIO_2_27 0x21b3 -#define MX28_PAD_AUART0_RX__GPIO_3_0 0x3003 -#define MX28_PAD_AUART0_TX__GPIO_3_1 0x3013 -#define MX28_PAD_AUART0_CTS__GPIO_3_2 0x3023 -#define MX28_PAD_AUART0_RTS__GPIO_3_3 0x3033 -#define MX28_PAD_AUART1_RX__GPIO_3_4 0x3043 -#define MX28_PAD_AUART1_TX__GPIO_3_5 0x3053 -#define MX28_PAD_AUART1_CTS__GPIO_3_6 0x3063 -#define MX28_PAD_AUART1_RTS__GPIO_3_7 0x3073 -#define MX28_PAD_AUART2_RX__GPIO_3_8 0x3083 -#define MX28_PAD_AUART2_TX__GPIO_3_9 0x3093 -#define MX28_PAD_AUART2_CTS__GPIO_3_10 0x30a3 -#define MX28_PAD_AUART2_RTS__GPIO_3_11 0x30b3 -#define MX28_PAD_AUART3_RX__GPIO_3_12 0x30c3 -#define MX28_PAD_AUART3_TX__GPIO_3_13 0x30d3 -#define MX28_PAD_AUART3_CTS__GPIO_3_14 0x30e3 -#define MX28_PAD_AUART3_RTS__GPIO_3_15 0x30f3 -#define MX28_PAD_PWM0__GPIO_3_16 0x3103 -#define MX28_PAD_PWM1__GPIO_3_17 0x3113 -#define MX28_PAD_PWM2__GPIO_3_18 0x3123 -#define MX28_PAD_SAIF0_MCLK__GPIO_3_20 0x3143 -#define MX28_PAD_SAIF0_LRCLK__GPIO_3_21 0x3153 -#define MX28_PAD_SAIF0_BITCLK__GPIO_3_22 0x3163 -#define MX28_PAD_SAIF0_SDATA0__GPIO_3_23 0x3173 -#define MX28_PAD_I2C0_SCL__GPIO_3_24 0x3183 -#define MX28_PAD_I2C0_SDA__GPIO_3_25 0x3193 -#define MX28_PAD_SAIF1_SDATA0__GPIO_3_26 0x31a3 -#define MX28_PAD_SPDIF__GPIO_3_27 0x31b3 -#define MX28_PAD_PWM3__GPIO_3_28 0x31c3 -#define MX28_PAD_PWM4__GPIO_3_29 0x31d3 -#define MX28_PAD_LCD_RESET__GPIO_3_30 0x31e3 -#define MX28_PAD_ENET0_MDC__GPIO_4_0 0x4003 -#define MX28_PAD_ENET0_MDIO__GPIO_4_1 0x4013 -#define MX28_PAD_ENET0_RX_EN__GPIO_4_2 0x4023 -#define MX28_PAD_ENET0_RXD0__GPIO_4_3 0x4033 -#define MX28_PAD_ENET0_RXD1__GPIO_4_4 0x4043 -#define MX28_PAD_ENET0_TX_CLK__GPIO_4_5 0x4053 -#define MX28_PAD_ENET0_TX_EN__GPIO_4_6 0x4063 -#define MX28_PAD_ENET0_TXD0__GPIO_4_7 0x4073 -#define MX28_PAD_ENET0_TXD1__GPIO_4_8 0x4083 -#define MX28_PAD_ENET0_RXD2__GPIO_4_9 0x4093 -#define MX28_PAD_ENET0_RXD3__GPIO_4_10 0x40a3 -#define MX28_PAD_ENET0_TXD2__GPIO_4_11 0x40b3 -#define MX28_PAD_ENET0_TXD3__GPIO_4_12 0x40c3 -#define MX28_PAD_ENET0_RX_CLK__GPIO_4_13 0x40d3 -#define MX28_PAD_ENET0_COL__GPIO_4_14 0x40e3 -#define MX28_PAD_ENET0_CRS__GPIO_4_15 0x40f3 -#define MX28_PAD_ENET_CLK__GPIO_4_16 0x4103 -#define MX28_PAD_JTAG_RTCK__GPIO_4_20 0x4143 - -#endif /* __DT_BINDINGS_MX28_PINCTRL_H__ */ diff --git a/sys/gnu/dts/arm/imx28-sps1.dts b/sys/gnu/dts/arm/imx28-sps1.dts deleted file mode 100644 index 43be7a6a769..00000000000 --- a/sys/gnu/dts/arm/imx28-sps1.dts +++ /dev/null @@ -1,166 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (C) 2012 Marek Vasut - */ - -/dts-v1/; -#include "imx28.dtsi" - -/ { - model = "SchulerControl GmbH, SC SPS 1"; - compatible = "schulercontrol,imx28-sps1", "fsl,imx28"; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x08000000>; - }; - - apb@80000000 { - apbh@80000000 { - pinctrl@80018000 { - pinctrl-names = "default"; - pinctrl-0 = <&hog_pins_a>; - - hog_pins_a: hog-gpios@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_GPMI_D00__GPIO_0_0 - MX28_PAD_GPMI_D03__GPIO_0_3 - MX28_PAD_GPMI_D06__GPIO_0_6 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - }; - - ssp0: spi@80010000 { - compatible = "fsl,imx28-mmc"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_4bit_pins_a>; - bus-width = <4>; - status = "okay"; - }; - - ssp2: spi@80014000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx28-spi"; - pinctrl-names = "default"; - pinctrl-0 = <&spi2_pins_a>; - status = "okay"; - - flash: m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "everspin,mr25h256", "mr25h256"; - spi-max-frequency = <40000000>; - reg = <0>; - }; - }; - }; - - apbx@80040000 { - i2c0: i2c@80058000 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - - rtc: rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; - - eeprom: eeprom@52 { - compatible = "atmel,24c64"; - reg = <0x52>; - pagesize = <32>; - }; - }; - - duart: serial@80074000 { - pinctrl-names = "default"; - pinctrl-0 = <&duart_pins_a>; - status = "okay"; - }; - - usbphy0: usbphy@8007c000 { - status = "okay"; - }; - - auart0: serial@8006a000 { - pinctrl-names = "default"; - pinctrl-0 = <&auart0_pins_a>; - status = "okay"; - }; - }; - }; - - ahb@80080000 { - usb0: usb@80080000 { - vbus-supply = <®_usb0_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&usb0_pins_b>; - status = "okay"; - }; - - mac0: ethernet@800f0000 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&mac0_pins_a>; - status = "okay"; - }; - - mac1: ethernet@800f4000 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&mac1_pins_a>; - status = "okay"; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_usb0_vbus: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "usb0_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 9 0>; - }; - }; - - leds { - #address-cells = <1>; - #size-cells = <0>; - compatible = "gpio-leds"; - status = "okay"; - - led@1 { - label = "sps1-1:yellow:user"; - gpios = <&gpio0 6 0>; - linux,default-trigger = "heartbeat"; - reg = <0>; - }; - - led@2 { - label = "sps1-2:red:user"; - gpios = <&gpio0 3 0>; - linux,default-trigger = "heartbeat"; - reg = <1>; - }; - - led@3 { - label = "sps1-3:red:user"; - gpios = <&gpio0 0 0>; - default-trigger = "heartbeat"; - reg = <2>; - }; - - }; -}; diff --git a/sys/gnu/dts/arm/imx28-ts4600.dts b/sys/gnu/dts/arm/imx28-ts4600.dts deleted file mode 100644 index 097ec35c62d..00000000000 --- a/sys/gnu/dts/arm/imx28-ts4600.dts +++ /dev/null @@ -1,74 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (C) 2016 Savoir-Faire Linux - * Author: Sebastien Bourdelin - */ - -/dts-v1/; -#include "imx28.dtsi" -#include "dt-bindings/gpio/gpio.h" - -/ { - - model = "Technologic Systems i.MX28 TS-4600"; - compatible = "technologic,imx28-ts4600", "fsl,imx28"; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x10000000>; /* 256MB */ - }; - - apb@80000000 { - apbh@80000000 { - ssp0: spi@80010000 { - compatible = "fsl,imx28-mmc"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_4bit_pins_a - &mmc0_sck_cfg - &en_sd_pwr>; - broken-cd = <1>; - bus-width = <4>; - vmmc-supply = <®_vddio_sd0>; - status = "okay"; - }; - - pinctrl@80018000 { - - en_sd_pwr: en-sd-pwr@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_PWM3__GPIO_3_28 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - }; - }; - - apbx@80040000 { - pwm: pwm@80064000 { - pinctrl-names = "default"; - pinctrl-0 = <&pwm2_pins_a>; - status = "okay"; - }; - - duart: serial@80074000 { - pinctrl-names = "default"; - pinctrl-0 = <&duart_pins_a>; - status = "okay"; - }; - }; - }; - - reg_vddio_sd0: regulator-vddio-sd0 { - compatible = "regulator-fixed"; - regulator-name = "vddio-sd0"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - gpio = <&gpio3 28 GPIO_ACTIVE_LOW>; - }; - -}; diff --git a/sys/gnu/dts/arm/imx28-tx28.dts b/sys/gnu/dts/arm/imx28-tx28.dts deleted file mode 100644 index 164254c28f8..00000000000 --- a/sys/gnu/dts/arm/imx28-tx28.dts +++ /dev/null @@ -1,749 +0,0 @@ -/* - * Copyright 2012 Shawn Guo - * Copyright 2013-2017 Lothar Waßmann - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx28.dtsi" -#include -#include - -/ { - model = "Ka-Ro electronics TX28 module"; - compatible = "karo,tx28", "fsl,imx28"; - - aliases { - can0 = &can0; - can1 = &can1; - display = &display0; - ds1339 = &ds1339; - gpio5 = &gpio5; - lcdif = &lcdif; - lcdif_23bit_pins = &tx28_lcdif_23bit_pins; - lcdif_24bit_pins = &lcdif_24bit_pins_a; - reg_can_xcvr = ®_can_xcvr; - spi_gpio = &spi_gpio; - spi_mxs = &ssp3; - stk5led = &user_led; - usbotg = &usb0; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0>; /* will be filled in by U-Boot */ - }; - - onewire { - compatible = "w1-gpio"; - gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>; - status = "disabled"; - }; - - reg_usb0_vbus: regulator-usb0-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb0_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio0 18 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usb1_vbus: regulator-usb1-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 27 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_2p5v: regulator-2p5v { - compatible = "regulator-fixed"; - regulator-name = "2P5V"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_can_xcvr: regulator-can-xcvr { - compatible = "regulator-fixed"; - regulator-name = "CAN XCVR"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&tx28_flexcan_xcvr_pins>; - }; - - reg_lcd: regulator-lcd-power { - compatible = "regulator-fixed"; - regulator-name = "LCD POWER"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio1 31 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_lcd_reset: regulator-lcd-reset { - compatible = "regulator-fixed"; - regulator-name = "LCD RESET"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>; - startup-delay-us = <300000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - }; - - mclk: clock-mclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <26000000>; - }; - - sound { - compatible = "fsl,imx28-tx28-sgtl5000", - "fsl,mxs-audio-sgtl5000"; - model = "imx28-tx28-sgtl5000"; - saif-controllers = <&saif0 &saif1>; - audio-codec = <&sgtl5000>; - }; - - leds { - compatible = "gpio-leds"; - - user_led: user { - label = "Heartbeat"; - gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 0 500000>; - /* - * a silly way to create a 1:1 relationship between the - * PWM value and the actual duty cycle - */ - brightness-levels = < 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100>; - default-brightness-level = <50>; - }; - - matrix_keypad: matrix-keypad { - compatible = "gpio-matrix-keypad"; - col-gpios = < - &gpio5 0 GPIO_ACTIVE_HIGH - &gpio5 1 GPIO_ACTIVE_HIGH - &gpio5 2 GPIO_ACTIVE_HIGH - &gpio5 3 GPIO_ACTIVE_HIGH - >; - row-gpios = < - &gpio5 4 GPIO_ACTIVE_HIGH - &gpio5 5 GPIO_ACTIVE_HIGH - &gpio5 6 GPIO_ACTIVE_HIGH - &gpio5 7 GPIO_ACTIVE_HIGH - >; - /* sample keymap */ - linux,keymap = < - 0x00000074 /* row 0, col 0, KEY_POWER */ - 0x00010052 /* row 0, col 1, KEY_KP0 */ - 0x0002004f /* row 0, col 2, KEY_KP1 */ - 0x00030050 /* row 0, col 3, KEY_KP2 */ - 0x01000051 /* row 1, col 0, KEY_KP3 */ - 0x0101004b /* row 1, col 1, KEY_KP4 */ - 0x0102004c /* row 1, col 2, KEY_KP5 */ - 0x0103004d /* row 1, col 3, KEY_KP6 */ - 0x02000047 /* row 2, col 0, KEY_KP7 */ - 0x02010048 /* row 2, col 1, KEY_KP8 */ - 0x02020049 /* row 2, col 2, KEY_KP9 */ - >; - gpio-activelow; - wakeup-source; - debounce-delay-ms = <100>; - col-scan-delay-us = <5000>; - linux,no-autorepeat; - }; - - spi_gpio: spi-gpio { - compatible = "spi-gpio"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&tx28_spi_gpio_pins>; - - gpio-sck = <&gpio2 24 GPIO_ACTIVE_HIGH>; - gpio-mosi = <&gpio2 25 GPIO_ACTIVE_HIGH>; - gpio-miso = <&gpio2 26 GPIO_ACTIVE_HIGH>; - num-chipselects = <3>; - cs-gpios = < - &gpio2 27 GPIO_ACTIVE_LOW - &gpio3 8 GPIO_ACTIVE_LOW - &gpio3 9 GPIO_ACTIVE_LOW - >; - /* enable this and disable ssp3 below, if you need full duplex SPI transfer */ - status = "disabled"; - - spi@0 { - compatible = "spidev"; - reg = <0>; - spi-max-frequency = <57600000>; - }; - - spi@1 { - compatible = "spidev"; - reg = <1>; - spi-max-frequency = <57600000>; - }; - - spi@2 { - compatible = "spidev"; - reg = <2>; - spi-max-frequency = <57600000>; - }; - }; -}; - -/* 2nd TX-Std UART - (A)UART1 */ -&auart1 { - pinctrl-names = "default"; - pinctrl-0 = <&auart1_pins_a>; - status = "okay"; -}; - -/* 3rd TX-Std UART - (A)UART3 */ -&auart3 { - pinctrl-names = "default"; - pinctrl-0 = <&auart3_pins_a>; - status = "okay"; -}; - -&can0 { - pinctrl-names = "default"; - pinctrl-0 = <&can0_pins_a>; - xceiver-supply = <®_can_xcvr>; - status = "okay"; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&can1_pins_a>; - xceiver-supply = <®_can_xcvr>; - status = "okay"; -}; - -&digctl { - status = "okay"; -}; - -/* 1st TX-Std UART - (D)UART */ -&duart { - pinctrl-names = "default"; - pinctrl-0 = <&duart_4pins_a>; - status = "okay"; -}; - -&gpmi { - pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>; - nand-on-flash-bbt; - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - clock-frequency = <400000>; - status = "okay"; - - sgtl5000: sgtl5000@a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - VDDA-supply = <®_2p5v>; - VDDIO-supply = <®_3p3v>; - clocks = <&mclk>; - }; - - gpio5: pca953x@20 { - compatible = "nxp,pca9554"; - reg = <0x20>; - pinctrl-names = "default"; - pinctrl-0 = <&tx28_pca9554_pins>; - interrupt-parent = <&gpio3>; - interrupts = <28 IRQ_TYPE_NONE>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - polytouch: edt-ft5x06@38 { - compatible = "edt,edt-ft5x06"; - reg = <0x38>; - pinctrl-names = "default"; - pinctrl-0 = <&tx28_edt_ft5x06_pins>; - interrupt-parent = <&gpio2>; - interrupts = <5 IRQ_TYPE_EDGE_FALLING>; - reset-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>; - wake-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH>; - wakeup-source; - }; - - touchscreen: tsc2007@48 { - compatible = "ti,tsc2007"; - reg = <0x48>; - pinctrl-names = "default"; - pinctrl-0 = <&tx28_tsc2007_pins>; - interrupt-parent = <&gpio3>; - interrupts = <20 IRQ_TYPE_EDGE_FALLING>; - pendown-gpio = <&gpio3 20 GPIO_ACTIVE_LOW>; - ti,x-plate-ohms = /bits/ 16 <660>; - }; - - ds1339: rtc@68 { - compatible = "mxim,ds1339"; - reg = <0x68>; - trickle-resistor-ohms = <250>; - trickle-diode-disable; - }; -}; - -&lcdif { - pinctrl-names = "default"; - pinctrl-0 = <&lcdif_24bit_pins_a &lcdif_sync_pins_a &tx28_lcdif_ctrl_pins>; - lcd-supply = <®_lcd>; - display = <&display0>; - status = "okay"; - - display0: display0 { - bits-per-pixel = <32>; - bus-width = <24>; - display-timings { - native-mode = <&timing5>; - timing0: timing0 { - panel-name = "VGA"; - clock-frequency = <25175000>; - hactive = <640>; - vactive = <480>; - hback-porch = <48>; - hsync-len = <96>; - hfront-porch = <16>; - vback-porch = <33>; - vsync-len = <2>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - - timing1: timing1 { - panel-name = "ETV570"; - clock-frequency = <25175000>; - hactive = <640>; - vactive = <480>; - hback-porch = <114>; - hsync-len = <30>; - hfront-porch = <16>; - vback-porch = <32>; - vsync-len = <3>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - - timing2: timing2 { - panel-name = "ET0350"; - clock-frequency = <6500000>; - hactive = <320>; - vactive = <240>; - hback-porch = <34>; - hsync-len = <34>; - hfront-porch = <20>; - vback-porch = <15>; - vsync-len = <3>; - vfront-porch = <4>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - - timing3: timing3 { - panel-name = "ET0430"; - clock-frequency = <9000000>; - hactive = <480>; - vactive = <272>; - hback-porch = <2>; - hsync-len = <41>; - hfront-porch = <2>; - vback-porch = <2>; - vsync-len = <10>; - vfront-porch = <2>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - - timing4: timing4 { - panel-name = "ET0500", "ET0700"; - clock-frequency = <33260000>; - hactive = <800>; - vactive = <480>; - hback-porch = <88>; - hsync-len = <128>; - hfront-porch = <40>; - vback-porch = <33>; - vsync-len = <2>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - - timing5: timing5 { - panel-name = "ETQ570"; - clock-frequency = <6400000>; - hactive = <320>; - vactive = <240>; - hback-porch = <38>; - hsync-len = <30>; - hfront-porch = <30>; - vback-porch = <16>; - vsync-len = <3>; - vfront-porch = <4>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - }; -}; - -&lradc { - fsl,lradc-touchscreen-wires = <4>; - status = "okay"; -}; - -&mac0 { - phy-mode = "rmii"; - pinctrl-names = "default", "gpio_mode"; - pinctrl-0 = <&mac0_pins_a>; - pinctrl-1 = <&tx28_mac0_pins_gpio>; - status = "okay"; -}; - -&mac1 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&mac1_pins_a>; - /* not enabled by default */ -}; - -&mxs_rtc { - status = "okay"; -}; - -&ocotp { - status = "okay"; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pins_a>; - status = "okay"; -}; - -&pinctrl { - pinctrl-names = "default"; - pinctrl-0 = <&hog_pins_a>; - - hog_pins_a: hog@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_ENET0_RXD3__GPIO_4_10 /* module LED */ - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - tx28_edt_ft5x06_pins: tx28-edt-ft5x06-pins@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SSP0_DATA6__GPIO_2_6 /* RESET */ - MX28_PAD_SSP0_DATA5__GPIO_2_5 /* IRQ */ - MX28_PAD_ENET0_RXD2__GPIO_4_9 /* WAKE */ - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - tx28_flexcan_xcvr_pins: tx28-flexcan-xcvr-pins@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_D00__GPIO_1_0 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - tx28_lcdif_23bit_pins: tx28-lcdif-23bit@0 { - reg = <0>; - fsl,pinmux-ids = < - /* LCD_D00 may be used as Flexcan Transceiver Enable on STK5-V5 */ - MX28_PAD_LCD_D01__LCD_D1 - MX28_PAD_LCD_D02__LCD_D2 - MX28_PAD_LCD_D03__LCD_D3 - MX28_PAD_LCD_D04__LCD_D4 - MX28_PAD_LCD_D05__LCD_D5 - MX28_PAD_LCD_D06__LCD_D6 - MX28_PAD_LCD_D07__LCD_D7 - MX28_PAD_LCD_D08__LCD_D8 - MX28_PAD_LCD_D09__LCD_D9 - MX28_PAD_LCD_D10__LCD_D10 - MX28_PAD_LCD_D11__LCD_D11 - MX28_PAD_LCD_D12__LCD_D12 - MX28_PAD_LCD_D13__LCD_D13 - MX28_PAD_LCD_D14__LCD_D14 - MX28_PAD_LCD_D15__LCD_D15 - MX28_PAD_LCD_D16__LCD_D16 - MX28_PAD_LCD_D17__LCD_D17 - MX28_PAD_LCD_D18__LCD_D18 - MX28_PAD_LCD_D19__LCD_D19 - MX28_PAD_LCD_D20__LCD_D20 - MX28_PAD_LCD_D21__LCD_D21 - MX28_PAD_LCD_D22__LCD_D22 - MX28_PAD_LCD_D23__LCD_D23 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - tx28_lcdif_ctrl_pins: tx28-lcdif-ctrl@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_ENABLE__GPIO_1_31 /* Enable */ - MX28_PAD_LCD_RESET__GPIO_3_30 /* Reset */ - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - tx28_mac0_pins_gpio: tx28-mac0-gpio-pins@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_ENET0_MDC__GPIO_4_0 - MX28_PAD_ENET0_MDIO__GPIO_4_1 - MX28_PAD_ENET0_RX_EN__GPIO_4_2 - MX28_PAD_ENET0_RXD0__GPIO_4_3 - MX28_PAD_ENET0_RXD1__GPIO_4_4 - MX28_PAD_ENET0_TX_EN__GPIO_4_6 - MX28_PAD_ENET0_TXD0__GPIO_4_7 - MX28_PAD_ENET0_TXD1__GPIO_4_8 - MX28_PAD_ENET_CLK__GPIO_4_16 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - tx28_pca9554_pins: tx28-pca9554-pins@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_PWM3__GPIO_3_28 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - tx28_spi_gpio_pins: spi-gpiogrp@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_AUART2_RX__GPIO_3_8 - MX28_PAD_AUART2_TX__GPIO_3_9 - MX28_PAD_SSP3_SCK__GPIO_2_24 - MX28_PAD_SSP3_MOSI__GPIO_2_25 - MX28_PAD_SSP3_MISO__GPIO_2_26 - MX28_PAD_SSP3_SS0__GPIO_2_27 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - tx28_tsc2007_pins: tx28-tsc2007-pins@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SAIF0_MCLK__GPIO_3_20 /* TSC2007 IRQ */ - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - - tx28_usbphy0_pins: tx28-usbphy0-pins@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_GPMI_CE2N__GPIO_0_18 /* USBOTG_VBUSEN */ - MX28_PAD_GPMI_CE3N__GPIO_0_19 /* USBOTH_OC */ - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - tx28_usbphy1_pins: tx28-usbphy1-pins@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SPDIF__GPIO_3_27 /* USBH_VBUSEN */ - MX28_PAD_JTAG_RTCK__GPIO_4_20 /* USBH_OC */ - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; -}; - -&saif0 { - pinctrl-names = "default"; - pinctrl-0 = <&saif0_pins_b>; - fsl,saif-master; - status = "okay"; -}; - -&saif1 { - pinctrl-names = "default"; - pinctrl-0 = <&saif1_pins_a>; - status = "okay"; -}; - -&ssp0 { - compatible = "fsl,imx28-mmc"; - pinctrl-names = "default", "special"; - pinctrl-0 = <&mmc0_4bit_pins_a - &mmc0_cd_cfg - &mmc0_sck_cfg>; - bus-width = <4>; - status = "okay"; -}; - -&ssp3 { - compatible = "fsl,imx28-spi"; - pinctrl-names = "default"; - pinctrl-0 = <&spi3_pins_a>; - clock-frequency = <57600000>; - status = "okay"; - - spi@0 { - compatible = "spidev"; - reg = <0>; - spi-max-frequency = <57600000>; - }; - - spi@1 { - compatible = "spidev"; - reg = <1>; - spi-max-frequency = <57600000>; - }; - - spi@2 { - compatible = "spidev"; - reg = <2>; - spi-max-frequency = <57600000>; - }; -}; - -&usb0 { - vbus-supply = <®_usb0_vbus>; - disable-over-current; - dr_mode = "peripheral"; - status = "okay"; -}; - -&usb1 { - vbus-supply = <®_usb1_vbus>; - disable-over-current; - dr_mode = "host"; - status = "okay"; -}; - -&usbphy0 { - pinctrl-names = "default"; - pinctrl-0 = <&tx28_usbphy0_pins>; - phy_type = "utmi"; - status = "okay"; -}; - -&usbphy1 { - pinctrl-names = "default"; - pinctrl-0 = <&tx28_usbphy1_pins>; - phy_type = "utmi"; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx28.dtsi b/sys/gnu/dts/arm/imx28.dtsi deleted file mode 100644 index e14d8ef0158..00000000000 --- a/sys/gnu/dts/arm/imx28.dtsi +++ /dev/null @@ -1,1330 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// -// Copyright 2012 Freescale Semiconductor, Inc. - -#include -#include "imx28-pinfunc.h" - -/ { - #address-cells = <1>; - #size-cells = <1>; - - interrupt-parent = <&icoll>; - /* - * The decompressor and also some bootloaders rely on a - * pre-existing /chosen node to be available to insert the - * command line and merge other ATAGS info. - */ - chosen {}; - - aliases { - ethernet0 = &mac0; - ethernet1 = &mac1; - gpio0 = &gpio0; - gpio1 = &gpio1; - gpio2 = &gpio2; - gpio3 = &gpio3; - gpio4 = &gpio4; - saif0 = &saif0; - saif1 = &saif1; - serial0 = &auart0; - serial1 = &auart1; - serial2 = &auart2; - serial3 = &auart3; - serial4 = &auart4; - spi0 = &ssp1; - spi1 = &ssp2; - usbphy0 = &usbphy0; - usbphy1 = &usbphy1; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "arm,arm926ej-s"; - device_type = "cpu"; - reg = <0>; - }; - }; - - apb@80000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x80000000 0x80000>; - ranges; - - apbh@80000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x80000000 0x3c900>; - ranges; - - icoll: interrupt-controller@80000000 { - compatible = "fsl,imx28-icoll", "fsl,icoll"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x80000000 0x2000>; - }; - - hsadc: hsadc@80002000 { - reg = <0x80002000 0x2000>; - interrupts = <13>; - dmas = <&dma_apbh 12>; - dma-names = "rx"; - status = "disabled"; - }; - - dma_apbh: dma-apbh@80004000 { - compatible = "fsl,imx28-dma-apbh"; - reg = <0x80004000 0x2000>; - interrupts = <82 83 84 85 - 88 88 88 88 - 88 88 88 88 - 87 86 0 0>; - interrupt-names = "ssp0", "ssp1", "ssp2", "ssp3", - "gpmi0", "gmpi1", "gpmi2", "gmpi3", - "gpmi4", "gmpi5", "gpmi6", "gmpi7", - "hsadc", "lcdif", "empty", "empty"; - #dma-cells = <1>; - dma-channels = <16>; - clocks = <&clks 25>; - }; - - perfmon: perfmon@80006000 { - reg = <0x80006000 0x800>; - interrupts = <27>; - status = "disabled"; - }; - - gpmi: gpmi-nand@8000c000 { - compatible = "fsl,imx28-gpmi-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>; - reg-names = "gpmi-nand", "bch"; - interrupts = <41>; - interrupt-names = "bch"; - clocks = <&clks 50>; - clock-names = "gpmi_io"; - dmas = <&dma_apbh 4>; - dma-names = "rx-tx"; - status = "disabled"; - }; - - ssp0: spi@80010000 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x80010000 0x2000>; - interrupts = <96>; - clocks = <&clks 46>; - dmas = <&dma_apbh 0>; - dma-names = "rx-tx"; - status = "disabled"; - }; - - ssp1: spi@80012000 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x80012000 0x2000>; - interrupts = <97>; - clocks = <&clks 47>; - dmas = <&dma_apbh 1>; - dma-names = "rx-tx"; - status = "disabled"; - }; - - ssp2: spi@80014000 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x80014000 0x2000>; - interrupts = <98>; - clocks = <&clks 48>; - dmas = <&dma_apbh 2>; - dma-names = "rx-tx"; - status = "disabled"; - }; - - ssp3: spi@80016000 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x80016000 0x2000>; - interrupts = <99>; - clocks = <&clks 49>; - dmas = <&dma_apbh 3>; - dma-names = "rx-tx"; - status = "disabled"; - }; - - pinctrl: pinctrl@80018000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx28-pinctrl", "simple-bus"; - reg = <0x80018000 0x2000>; - - gpio0: gpio@0 { - compatible = "fsl,imx28-gpio", "fsl,mxs-gpio"; - reg = <0>; - interrupts = <127>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio@1 { - compatible = "fsl,imx28-gpio", "fsl,mxs-gpio"; - reg = <1>; - interrupts = <126>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@2 { - compatible = "fsl,imx28-gpio", "fsl,mxs-gpio"; - reg = <2>; - interrupts = <125>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio@3 { - compatible = "fsl,imx28-gpio", "fsl,mxs-gpio"; - reg = <3>; - interrupts = <124>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio4: gpio@4 { - compatible = "fsl,imx28-gpio", "fsl,mxs-gpio"; - reg = <4>; - interrupts = <123>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - duart_pins_a: duart@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_PWM0__DUART_RX - MX28_PAD_PWM1__DUART_TX - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - duart_pins_b: duart@1 { - reg = <1>; - fsl,pinmux-ids = < - MX28_PAD_AUART0_CTS__DUART_RX - MX28_PAD_AUART0_RTS__DUART_TX - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - duart_4pins_a: duart-4pins@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_AUART0_CTS__DUART_RX - MX28_PAD_AUART0_RTS__DUART_TX - MX28_PAD_AUART0_RX__DUART_CTS - MX28_PAD_AUART0_TX__DUART_RTS - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - gpmi_pins_a: gpmi-nand@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_GPMI_D00__GPMI_D0 - MX28_PAD_GPMI_D01__GPMI_D1 - MX28_PAD_GPMI_D02__GPMI_D2 - MX28_PAD_GPMI_D03__GPMI_D3 - MX28_PAD_GPMI_D04__GPMI_D4 - MX28_PAD_GPMI_D05__GPMI_D5 - MX28_PAD_GPMI_D06__GPMI_D6 - MX28_PAD_GPMI_D07__GPMI_D7 - MX28_PAD_GPMI_CE0N__GPMI_CE0N - MX28_PAD_GPMI_RDY0__GPMI_READY0 - MX28_PAD_GPMI_RDN__GPMI_RDN - MX28_PAD_GPMI_WRN__GPMI_WRN - MX28_PAD_GPMI_ALE__GPMI_ALE - MX28_PAD_GPMI_CLE__GPMI_CLE - MX28_PAD_GPMI_RESETN__GPMI_RESETN - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - gpmi_status_cfg: gpmi-status-cfg@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_GPMI_RDN__GPMI_RDN - MX28_PAD_GPMI_WRN__GPMI_WRN - MX28_PAD_GPMI_RESETN__GPMI_RESETN - >; - fsl,drive-strength = ; - }; - - auart0_pins_a: auart0@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_AUART0_RX__AUART0_RX - MX28_PAD_AUART0_TX__AUART0_TX - MX28_PAD_AUART0_CTS__AUART0_CTS - MX28_PAD_AUART0_RTS__AUART0_RTS - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - auart0_2pins_a: auart0-2pins@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_AUART0_RX__AUART0_RX - MX28_PAD_AUART0_TX__AUART0_TX - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - auart1_pins_a: auart1@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_AUART1_RX__AUART1_RX - MX28_PAD_AUART1_TX__AUART1_TX - MX28_PAD_AUART1_CTS__AUART1_CTS - MX28_PAD_AUART1_RTS__AUART1_RTS - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - auart1_2pins_a: auart1-2pins@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_AUART1_RX__AUART1_RX - MX28_PAD_AUART1_TX__AUART1_TX - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - auart2_2pins_a: auart2-2pins@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SSP2_SCK__AUART2_RX - MX28_PAD_SSP2_MOSI__AUART2_TX - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - auart2_2pins_b: auart2-2pins@1 { - reg = <1>; - fsl,pinmux-ids = < - MX28_PAD_AUART2_RX__AUART2_RX - MX28_PAD_AUART2_TX__AUART2_TX - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - auart2_pins_a: auart2-pins@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_AUART2_RX__AUART2_RX - MX28_PAD_AUART2_TX__AUART2_TX - MX28_PAD_AUART2_CTS__AUART2_CTS - MX28_PAD_AUART2_RTS__AUART2_RTS - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - auart3_pins_a: auart3@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_AUART3_RX__AUART3_RX - MX28_PAD_AUART3_TX__AUART3_TX - MX28_PAD_AUART3_CTS__AUART3_CTS - MX28_PAD_AUART3_RTS__AUART3_RTS - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - auart3_2pins_a: auart3-2pins@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SSP2_MISO__AUART3_RX - MX28_PAD_SSP2_SS0__AUART3_TX - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - auart3_2pins_b: auart3-2pins@1 { - reg = <1>; - fsl,pinmux-ids = < - MX28_PAD_AUART3_RX__AUART3_RX - MX28_PAD_AUART3_TX__AUART3_TX - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - auart4_2pins_a: auart4@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SSP3_SCK__AUART4_TX - MX28_PAD_SSP3_MOSI__AUART4_RX - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - auart4_2pins_b: auart4@1 { - reg = <1>; - fsl,pinmux-ids = < - MX28_PAD_AUART0_CTS__AUART4_RX - MX28_PAD_AUART0_RTS__AUART4_TX - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - mac0_pins_a: mac0@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_ENET0_MDC__ENET0_MDC - MX28_PAD_ENET0_MDIO__ENET0_MDIO - MX28_PAD_ENET0_RX_EN__ENET0_RX_EN - MX28_PAD_ENET0_RXD0__ENET0_RXD0 - MX28_PAD_ENET0_RXD1__ENET0_RXD1 - MX28_PAD_ENET0_TX_EN__ENET0_TX_EN - MX28_PAD_ENET0_TXD0__ENET0_TXD0 - MX28_PAD_ENET0_TXD1__ENET0_TXD1 - MX28_PAD_ENET_CLK__CLKCTRL_ENET - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - mac0_pins_b: mac0@1 { - reg = <1>; - fsl,pinmux-ids = < - MX28_PAD_ENET0_MDC__ENET0_MDC - MX28_PAD_ENET0_MDIO__ENET0_MDIO - MX28_PAD_ENET0_RX_EN__ENET0_RX_EN - MX28_PAD_ENET0_RXD0__ENET0_RXD0 - MX28_PAD_ENET0_RXD1__ENET0_RXD1 - MX28_PAD_ENET0_RXD2__ENET0_RXD2 - MX28_PAD_ENET0_RXD3__ENET0_RXD3 - MX28_PAD_ENET0_TX_EN__ENET0_TX_EN - MX28_PAD_ENET0_TXD0__ENET0_TXD0 - MX28_PAD_ENET0_TXD1__ENET0_TXD1 - MX28_PAD_ENET0_TXD2__ENET0_TXD2 - MX28_PAD_ENET0_TXD3__ENET0_TXD3 - MX28_PAD_ENET_CLK__CLKCTRL_ENET - MX28_PAD_ENET0_COL__ENET0_COL - MX28_PAD_ENET0_CRS__ENET0_CRS - MX28_PAD_ENET0_TX_CLK__ENET0_TX_CLK - MX28_PAD_ENET0_RX_CLK__ENET0_RX_CLK - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - mac1_pins_a: mac1@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_ENET0_CRS__ENET1_RX_EN - MX28_PAD_ENET0_RXD2__ENET1_RXD0 - MX28_PAD_ENET0_RXD3__ENET1_RXD1 - MX28_PAD_ENET0_COL__ENET1_TX_EN - MX28_PAD_ENET0_TXD2__ENET1_TXD0 - MX28_PAD_ENET0_TXD3__ENET1_TXD1 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - mmc0_8bit_pins_a: mmc0-8bit@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SSP0_DATA0__SSP0_D0 - MX28_PAD_SSP0_DATA1__SSP0_D1 - MX28_PAD_SSP0_DATA2__SSP0_D2 - MX28_PAD_SSP0_DATA3__SSP0_D3 - MX28_PAD_SSP0_DATA4__SSP0_D4 - MX28_PAD_SSP0_DATA5__SSP0_D5 - MX28_PAD_SSP0_DATA6__SSP0_D6 - MX28_PAD_SSP0_DATA7__SSP0_D7 - MX28_PAD_SSP0_CMD__SSP0_CMD - MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT - MX28_PAD_SSP0_SCK__SSP0_SCK - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - mmc0_4bit_pins_a: mmc0-4bit@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SSP0_DATA0__SSP0_D0 - MX28_PAD_SSP0_DATA1__SSP0_D1 - MX28_PAD_SSP0_DATA2__SSP0_D2 - MX28_PAD_SSP0_DATA3__SSP0_D3 - MX28_PAD_SSP0_CMD__SSP0_CMD - MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT - MX28_PAD_SSP0_SCK__SSP0_SCK - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - mmc0_cd_cfg: mmc0-cd-cfg@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT - >; - fsl,pull-up = ; - }; - - mmc0_sck_cfg: mmc0-sck-cfg@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SSP0_SCK__SSP0_SCK - >; - fsl,drive-strength = ; - fsl,pull-up = ; - }; - - mmc1_4bit_pins_a: mmc1-4bit@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_GPMI_D00__SSP1_D0 - MX28_PAD_GPMI_D01__SSP1_D1 - MX28_PAD_GPMI_D02__SSP1_D2 - MX28_PAD_GPMI_D03__SSP1_D3 - MX28_PAD_GPMI_RDY1__SSP1_CMD - MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT - MX28_PAD_GPMI_WRN__SSP1_SCK - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - mmc1_cd_cfg: mmc1-cd-cfg@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT - >; - fsl,pull-up = ; - }; - - mmc1_sck_cfg: mmc1-sck-cfg@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_GPMI_WRN__SSP1_SCK - >; - fsl,drive-strength = ; - fsl,pull-up = ; - }; - - - mmc2_4bit_pins_a: mmc2-4bit@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SSP0_DATA4__SSP2_D0 - MX28_PAD_SSP1_SCK__SSP2_D1 - MX28_PAD_SSP1_CMD__SSP2_D2 - MX28_PAD_SSP0_DATA5__SSP2_D3 - MX28_PAD_SSP0_DATA6__SSP2_CMD - MX28_PAD_AUART1_RX__SSP2_CARD_DETECT - MX28_PAD_SSP0_DATA7__SSP2_SCK - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - mmc2_4bit_pins_b: mmc2-4bit@1 { - reg = <1>; - fsl,pinmux-ids = < - MX28_PAD_SSP2_SCK__SSP2_SCK - MX28_PAD_SSP2_MOSI__SSP2_CMD - MX28_PAD_SSP2_MISO__SSP2_D0 - MX28_PAD_SSP2_SS0__SSP2_D3 - MX28_PAD_SSP2_SS1__SSP2_D1 - MX28_PAD_SSP2_SS2__SSP2_D2 - MX28_PAD_AUART1_RX__SSP2_CARD_DETECT - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - mmc2_cd_cfg: mmc2-cd-cfg@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_AUART1_RX__SSP2_CARD_DETECT - >; - fsl,pull-up = ; - }; - - mmc2_sck_cfg_a: mmc2-sck-cfg@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SSP0_DATA7__SSP2_SCK - >; - fsl,drive-strength = ; - fsl,pull-up = ; - }; - - mmc2_sck_cfg_b: mmc2-sck-cfg@1 { - reg = <1>; - fsl,pinmux-ids = < - MX28_PAD_SSP2_SCK__SSP2_SCK - >; - fsl,drive-strength = ; - fsl,pull-up = ; - }; - - i2c0_pins_a: i2c0@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_I2C0_SCL__I2C0_SCL - MX28_PAD_I2C0_SDA__I2C0_SDA - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - i2c0_pins_b: i2c0@1 { - reg = <1>; - fsl,pinmux-ids = < - MX28_PAD_AUART0_RX__I2C0_SCL - MX28_PAD_AUART0_TX__I2C0_SDA - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - i2c1_pins_a: i2c1@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_PWM0__I2C1_SCL - MX28_PAD_PWM1__I2C1_SDA - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - i2c1_pins_b: i2c1@1 { - reg = <1>; - fsl,pinmux-ids = < - MX28_PAD_AUART2_CTS__I2C1_SCL - MX28_PAD_AUART2_RTS__I2C1_SDA - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - saif0_pins_a: saif0@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SAIF0_MCLK__SAIF0_MCLK - MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK - MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK - MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - saif0_pins_b: saif0@1 { - reg = <1>; - fsl,pinmux-ids = < - MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK - MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK - MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - saif1_pins_a: saif1@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - pwm0_pins_a: pwm0@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_PWM0__PWM_0 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - pwm2_pins_a: pwm2@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_PWM2__PWM_2 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - pwm3_pins_a: pwm3@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_PWM3__PWM_3 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - pwm3_pins_b: pwm3@1 { - reg = <1>; - fsl,pinmux-ids = < - MX28_PAD_SAIF0_MCLK__PWM_3 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - pwm4_pins_a: pwm4@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_PWM4__PWM_4 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - lcdif_24bit_pins_a: lcdif-24bit@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_D00__LCD_D0 - MX28_PAD_LCD_D01__LCD_D1 - MX28_PAD_LCD_D02__LCD_D2 - MX28_PAD_LCD_D03__LCD_D3 - MX28_PAD_LCD_D04__LCD_D4 - MX28_PAD_LCD_D05__LCD_D5 - MX28_PAD_LCD_D06__LCD_D6 - MX28_PAD_LCD_D07__LCD_D7 - MX28_PAD_LCD_D08__LCD_D8 - MX28_PAD_LCD_D09__LCD_D9 - MX28_PAD_LCD_D10__LCD_D10 - MX28_PAD_LCD_D11__LCD_D11 - MX28_PAD_LCD_D12__LCD_D12 - MX28_PAD_LCD_D13__LCD_D13 - MX28_PAD_LCD_D14__LCD_D14 - MX28_PAD_LCD_D15__LCD_D15 - MX28_PAD_LCD_D16__LCD_D16 - MX28_PAD_LCD_D17__LCD_D17 - MX28_PAD_LCD_D18__LCD_D18 - MX28_PAD_LCD_D19__LCD_D19 - MX28_PAD_LCD_D20__LCD_D20 - MX28_PAD_LCD_D21__LCD_D21 - MX28_PAD_LCD_D22__LCD_D22 - MX28_PAD_LCD_D23__LCD_D23 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - lcdif_18bit_pins_a: lcdif-18bit@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_D00__LCD_D0 - MX28_PAD_LCD_D01__LCD_D1 - MX28_PAD_LCD_D02__LCD_D2 - MX28_PAD_LCD_D03__LCD_D3 - MX28_PAD_LCD_D04__LCD_D4 - MX28_PAD_LCD_D05__LCD_D5 - MX28_PAD_LCD_D06__LCD_D6 - MX28_PAD_LCD_D07__LCD_D7 - MX28_PAD_LCD_D08__LCD_D8 - MX28_PAD_LCD_D09__LCD_D9 - MX28_PAD_LCD_D10__LCD_D10 - MX28_PAD_LCD_D11__LCD_D11 - MX28_PAD_LCD_D12__LCD_D12 - MX28_PAD_LCD_D13__LCD_D13 - MX28_PAD_LCD_D14__LCD_D14 - MX28_PAD_LCD_D15__LCD_D15 - MX28_PAD_LCD_D16__LCD_D16 - MX28_PAD_LCD_D17__LCD_D17 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - lcdif_16bit_pins_a: lcdif-16bit@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_D00__LCD_D0 - MX28_PAD_LCD_D01__LCD_D1 - MX28_PAD_LCD_D02__LCD_D2 - MX28_PAD_LCD_D03__LCD_D3 - MX28_PAD_LCD_D04__LCD_D4 - MX28_PAD_LCD_D05__LCD_D5 - MX28_PAD_LCD_D06__LCD_D6 - MX28_PAD_LCD_D07__LCD_D7 - MX28_PAD_LCD_D08__LCD_D8 - MX28_PAD_LCD_D09__LCD_D9 - MX28_PAD_LCD_D10__LCD_D10 - MX28_PAD_LCD_D11__LCD_D11 - MX28_PAD_LCD_D12__LCD_D12 - MX28_PAD_LCD_D13__LCD_D13 - MX28_PAD_LCD_D14__LCD_D14 - MX28_PAD_LCD_D15__LCD_D15 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - lcdif_sync_pins_a: lcdif-sync@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_RS__LCD_DOTCLK - MX28_PAD_LCD_CS__LCD_ENABLE - MX28_PAD_LCD_RD_E__LCD_VSYNC - MX28_PAD_LCD_WR_RWN__LCD_HSYNC - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - can0_pins_a: can0@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_GPMI_RDY2__CAN0_TX - MX28_PAD_GPMI_RDY3__CAN0_RX - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - can1_pins_a: can1@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_GPMI_CE2N__CAN1_TX - MX28_PAD_GPMI_CE3N__CAN1_RX - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - spi2_pins_a: spi2@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SSP2_SCK__SSP2_SCK - MX28_PAD_SSP2_MOSI__SSP2_CMD - MX28_PAD_SSP2_MISO__SSP2_D0 - MX28_PAD_SSP2_SS0__SSP2_D3 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - spi3_pins_a: spi3@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_AUART2_RX__SSP3_D4 - MX28_PAD_AUART2_TX__SSP3_D5 - MX28_PAD_SSP3_SCK__SSP3_SCK - MX28_PAD_SSP3_MOSI__SSP3_CMD - MX28_PAD_SSP3_MISO__SSP3_D0 - MX28_PAD_SSP3_SS0__SSP3_D3 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - spi3_pins_b: spi3@1 { - reg = <1>; - fsl,pinmux-ids = < - MX28_PAD_SSP3_SCK__SSP3_SCK - MX28_PAD_SSP3_MOSI__SSP3_CMD - MX28_PAD_SSP3_MISO__SSP3_D0 - MX28_PAD_SSP3_SS0__SSP3_D3 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - usb0_pins_a: usb0@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SSP2_SS2__USB0_OVERCURRENT - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - usb0_pins_b: usb0@1 { - reg = <1>; - fsl,pinmux-ids = < - MX28_PAD_AUART1_CTS__USB0_OVERCURRENT - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - usb1_pins_a: usb1@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SSP2_SS1__USB1_OVERCURRENT - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - usb0_id_pins_a: usb0id@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_AUART1_RTS__USB0_ID - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - usb0_id_pins_b: usb0id1@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_PWM2__USB0_ID - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - }; - - digctl: digctl@8001c000 { - compatible = "fsl,imx28-digctl", "fsl,imx23-digctl"; - reg = <0x8001c000 0x2000>; - interrupts = <89>; - status = "disabled"; - }; - - etm: etm@80022000 { - reg = <0x80022000 0x2000>; - status = "disabled"; - }; - - dma_apbx: dma-apbx@80024000 { - compatible = "fsl,imx28-dma-apbx"; - reg = <0x80024000 0x2000>; - interrupts = <78 79 66 0 - 80 81 68 69 - 70 71 72 73 - 74 75 76 77>; - interrupt-names = "auart4-rx", "auart4-tx", "spdif-tx", "empty", - "saif0", "saif1", "i2c0", "i2c1", - "auart0-rx", "auart0-tx", "auart1-rx", "auart1-tx", - "auart2-rx", "auart2-tx", "auart3-rx", "auart3-tx"; - #dma-cells = <1>; - dma-channels = <16>; - clocks = <&clks 26>; - }; - - dcp: dcp@80028000 { - compatible = "fsl,imx28-dcp", "fsl,imx23-dcp"; - reg = <0x80028000 0x2000>; - interrupts = <52 53 54>; - status = "okay"; - }; - - pxp: pxp@8002a000 { - reg = <0x8002a000 0x2000>; - interrupts = <39>; - status = "disabled"; - }; - - ocotp: ocotp@8002c000 { - compatible = "fsl,imx28-ocotp", "fsl,ocotp"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x8002c000 0x2000>; - clocks = <&clks 25>; - }; - - axi-ahb@8002e000 { - reg = <0x8002e000 0x2000>; - status = "disabled"; - }; - - lcdif: lcdif@80030000 { - compatible = "fsl,imx28-lcdif"; - reg = <0x80030000 0x2000>; - interrupts = <38>; - clocks = <&clks 55>; - dmas = <&dma_apbh 13>; - dma-names = "rx"; - status = "disabled"; - }; - - can0: can@80032000 { - compatible = "fsl,imx28-flexcan"; - reg = <0x80032000 0x2000>; - interrupts = <8>; - clocks = <&clks 58>, <&clks 58>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - can1: can@80034000 { - compatible = "fsl,imx28-flexcan"; - reg = <0x80034000 0x2000>; - interrupts = <9>; - clocks = <&clks 59>, <&clks 59>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - simdbg: simdbg@8003c000 { - reg = <0x8003c000 0x200>; - status = "disabled"; - }; - - simgpmisel: simgpmisel@8003c200 { - reg = <0x8003c200 0x100>; - status = "disabled"; - }; - - simsspsel: simsspsel@8003c300 { - reg = <0x8003c300 0x100>; - status = "disabled"; - }; - - simmemsel: simmemsel@8003c400 { - reg = <0x8003c400 0x100>; - status = "disabled"; - }; - - gpiomon: gpiomon@8003c500 { - reg = <0x8003c500 0x100>; - status = "disabled"; - }; - - simenet: simenet@8003c700 { - reg = <0x8003c700 0x100>; - status = "disabled"; - }; - - armjtag: armjtag@8003c800 { - reg = <0x8003c800 0x100>; - status = "disabled"; - }; - }; - - apbx@80040000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x80040000 0x40000>; - ranges; - - clks: clkctrl@80040000 { - compatible = "fsl,imx28-clkctrl", "fsl,clkctrl"; - reg = <0x80040000 0x2000>; - #clock-cells = <1>; - }; - - saif0: saif@80042000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx28-saif"; - reg = <0x80042000 0x2000>; - interrupts = <59>; - #clock-cells = <0>; - clocks = <&clks 53>; - dmas = <&dma_apbx 4>; - dma-names = "rx-tx"; - status = "disabled"; - }; - - power: power@80044000 { - reg = <0x80044000 0x2000>; - status = "disabled"; - }; - - saif1: saif@80046000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx28-saif"; - reg = <0x80046000 0x2000>; - interrupts = <58>; - clocks = <&clks 54>; - dmas = <&dma_apbx 5>; - dma-names = "rx-tx"; - status = "disabled"; - }; - - lradc: lradc@80050000 { - compatible = "fsl,imx28-lradc"; - reg = <0x80050000 0x2000>; - interrupts = <10 14 15 16 17 18 19 - 20 21 22 23 24 25>; - status = "disabled"; - clocks = <&clks 41>; - #io-channel-cells = <1>; - }; - - spdif: spdif@80054000 { - reg = <0x80054000 0x2000>; - interrupts = <45>; - dmas = <&dma_apbx 2>; - dma-names = "tx"; - status = "disabled"; - }; - - mxs_rtc: rtc@80056000 { - compatible = "fsl,imx28-rtc", "fsl,stmp3xxx-rtc"; - reg = <0x80056000 0x2000>; - interrupts = <29>; - }; - - i2c0: i2c@80058000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx28-i2c"; - reg = <0x80058000 0x2000>; - interrupts = <111>; - clock-frequency = <100000>; - dmas = <&dma_apbx 6>; - dma-names = "rx-tx"; - status = "disabled"; - }; - - i2c1: i2c@8005a000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx28-i2c"; - reg = <0x8005a000 0x2000>; - interrupts = <110>; - clock-frequency = <100000>; - dmas = <&dma_apbx 7>; - dma-names = "rx-tx"; - status = "disabled"; - }; - - pwm: pwm@80064000 { - compatible = "fsl,imx28-pwm", "fsl,imx23-pwm"; - reg = <0x80064000 0x2000>; - clocks = <&clks 44>; - #pwm-cells = <2>; - fsl,pwm-number = <8>; - status = "disabled"; - }; - - timer: timrot@80068000 { - compatible = "fsl,imx28-timrot", "fsl,timrot"; - reg = <0x80068000 0x2000>; - interrupts = <48 49 50 51>; - clocks = <&clks 26>; - }; - - auart0: serial@8006a000 { - compatible = "fsl,imx28-auart", "fsl,imx23-auart"; - reg = <0x8006a000 0x2000>; - interrupts = <112>; - dmas = <&dma_apbx 8>, <&dma_apbx 9>; - dma-names = "rx", "tx"; - clocks = <&clks 45>; - status = "disabled"; - }; - - auart1: serial@8006c000 { - compatible = "fsl,imx28-auart", "fsl,imx23-auart"; - reg = <0x8006c000 0x2000>; - interrupts = <113>; - dmas = <&dma_apbx 10>, <&dma_apbx 11>; - dma-names = "rx", "tx"; - clocks = <&clks 45>; - status = "disabled"; - }; - - auart2: serial@8006e000 { - compatible = "fsl,imx28-auart", "fsl,imx23-auart"; - reg = <0x8006e000 0x2000>; - interrupts = <114>; - dmas = <&dma_apbx 12>, <&dma_apbx 13>; - dma-names = "rx", "tx"; - clocks = <&clks 45>; - status = "disabled"; - }; - - auart3: serial@80070000 { - compatible = "fsl,imx28-auart", "fsl,imx23-auart"; - reg = <0x80070000 0x2000>; - interrupts = <115>; - dmas = <&dma_apbx 14>, <&dma_apbx 15>; - dma-names = "rx", "tx"; - clocks = <&clks 45>; - status = "disabled"; - }; - - auart4: serial@80072000 { - compatible = "fsl,imx28-auart", "fsl,imx23-auart"; - reg = <0x80072000 0x2000>; - interrupts = <116>; - dmas = <&dma_apbx 0>, <&dma_apbx 1>; - dma-names = "rx", "tx"; - clocks = <&clks 45>; - status = "disabled"; - }; - - duart: serial@80074000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x80074000 0x1000>; - interrupts = <47>; - clocks = <&clks 45>, <&clks 26>; - clock-names = "uart", "apb_pclk"; - status = "disabled"; - }; - - usbphy0: usbphy@8007c000 { - compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy"; - reg = <0x8007c000 0x2000>; - clocks = <&clks 62>; - status = "disabled"; - }; - - usbphy1: usbphy@8007e000 { - compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy"; - reg = <0x8007e000 0x2000>; - clocks = <&clks 63>; - status = "disabled"; - }; - }; - }; - - ahb@80080000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x80080000 0x80000>; - ranges; - - usb0: usb@80080000 { - compatible = "fsl,imx28-usb", "fsl,imx27-usb"; - reg = <0x80080000 0x10000>; - interrupts = <93>; - clocks = <&clks 60>; - fsl,usbphy = <&usbphy0>; - status = "disabled"; - }; - - usb1: usb@80090000 { - compatible = "fsl,imx28-usb", "fsl,imx27-usb"; - reg = <0x80090000 0x10000>; - interrupts = <92>; - clocks = <&clks 61>; - fsl,usbphy = <&usbphy1>; - dr_mode = "host"; - status = "disabled"; - }; - - dflpt: dflpt@800c0000 { - reg = <0x800c0000 0x10000>; - status = "disabled"; - }; - - mac0: ethernet@800f0000 { - compatible = "fsl,imx28-fec"; - reg = <0x800f0000 0x4000>; - interrupts = <101>; - clocks = <&clks 57>, <&clks 57>, <&clks 64>; - clock-names = "ipg", "ahb", "enet_out"; - status = "disabled"; - }; - - mac1: ethernet@800f4000 { - compatible = "fsl,imx28-fec"; - reg = <0x800f4000 0x4000>; - interrupts = <102>; - clocks = <&clks 57>, <&clks 57>; - clock-names = "ipg", "ahb"; - status = "disabled"; - }; - - etn_switch: switch@800f8000 { - reg = <0x800f8000 0x8000>; - status = "disabled"; - }; - }; - - iio-hwmon { - compatible = "iio-hwmon"; - io-channels = <&lradc 8>; - }; -}; diff --git a/sys/gnu/dts/arm/imx31-bug.dts b/sys/gnu/dts/arm/imx31-bug.dts deleted file mode 100644 index d87eee3f9b3..00000000000 --- a/sys/gnu/dts/arm/imx31-bug.dts +++ /dev/null @@ -1,22 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2012 Denis 'GNUtoo' Carikli - */ - -/dts-v1/; -#include "imx31.dtsi" - -/ { - model = "Buglabs i.MX31 Bug 1.x"; - compatible = "buglabs,imx31-bug", "fsl,imx31"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x8000000>; /* 128M */ - }; -}; - -&uart5 { - uart-has-rtscts; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx31-lite.dts b/sys/gnu/dts/arm/imx31-lite.dts deleted file mode 100644 index d17abdfb633..00000000000 --- a/sys/gnu/dts/arm/imx31-lite.dts +++ /dev/null @@ -1,178 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// -// Copyright (C) 2016-2018 Vladimir Zapolskiy - -/dts-v1/; - -#include "imx31.dtsi" - -#include -#include - -/ { - model = "LogicPD i.MX31 Lite"; - compatible = "logicpd,imx31-lite", "fsl,imx31"; - - chosen { - stdout-path = &uart1; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x8000000>; - }; - - leds { - compatible = "gpio-leds"; - - led0 { - gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; - }; - - led1 { - gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&ata { - status = "okay"; -}; - -&nfc { - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - nand-on-flash-bbt; - status = "okay"; -}; - -&sdhci1 { - bus-width = <4>; - cd-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>; - wp-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&spi2 { - status = "okay"; - - pmic@0 { - compatible = "fsl,mc13783"; - reg = <0>; - spi-cs-high; - spi-max-frequency = <1000000>; - interrupt-parent = <&gpio1>; - interrupts = <3 IRQ_TYPE_EDGE_RISING>; - - fsl,mc13xxx-uses-adc; - fsl,mc13xxx-uses-rtc; - - regulators { - sw1a { /* QVCC */ - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - }; - - sw1b { /* QVCC */ - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - }; - - sw2a { /* 1.8V_DDR, NVCC2, NVCC21 and NVCC22 */ - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - sw2b { /* NVCC10 */ - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - violo { /* NVCC1 and NVCC7 */ - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - viohi { /* VIOHI */ - regulator-min-microvolt = <2775000>; - regulator-max-microvolt = <2775000>; - regulator-always-on; - regulator-boot-on; - }; - - vaudio { /* VAUDIO */ - regulator-min-microvolt = <2775000>; - regulator-max-microvolt = <2775000>; - }; - - vcam { /* NVCC4 */ - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - vgen { /* NVCC5 / NVCC8 and NVCC6 / NVCC9 */ - regulator-min-microvolt = <2775000>; - regulator-max-microvolt = <2775000>; - regulator-always-on; - regulator-boot-on; - }; - - vmmc2 { /* NVCC3 */ - regulator-min-microvolt = <1600000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - regulator-boot-on; - }; - }; - }; -}; - -&uart1 { - uart-has-rtscts; - status = "okay"; -}; - -/* Routed to the extension board */ -&uart2 { - uart-has-rtscts; - status = "okay"; -}; - -/* Routed to the extension board */ -&uart3 { - uart-has-rtscts; - status = "okay"; -}; - -&weim { - status = "okay"; - - nor@0,0 { - compatible = "cfi-flash"; - reg = <0 0x0 0x200000>; - bank-width = <2>; - linux,mtd-name = "physmap-flash.0"; - fsl,weim-cs-timing = <0x0000cf03 0xa0330d01 0x00220800>; - }; - - ethernet@4,0 { - compatible = "smsc,lan9117", "smsc,lan9115"; - reg = <4 0x0 0x100>; - interrupt-parent = <&gpio1>; - interrupts = <26 IRQ_TYPE_EDGE_FALLING>; - phy-mode = "mii"; - reg-io-width = <2>; - smsc,irq-push-pull; - fsl,weim-cs-timing = <0x00008701 0x04000541 0x00010000>; - }; -}; diff --git a/sys/gnu/dts/arm/imx31.dtsi b/sys/gnu/dts/arm/imx31.dtsi deleted file mode 100644 index 6b62f0745b8..00000000000 --- a/sys/gnu/dts/arm/imx31.dtsi +++ /dev/null @@ -1,370 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// -// Copyright 2016-2018 Vladimir Zapolskiy -// Copyright 2012 Denis 'GNUtoo' Carikli - -/ { - #address-cells = <1>; - #size-cells = <1>; - /* - * The decompressor and also some bootloaders rely on a - * pre-existing /chosen node to be available to insert the - * command line and merge other ATAGS info. - */ - chosen {}; - - aliases { - gpio0 = &gpio1; - gpio1 = &gpio2; - gpio2 = &gpio3; - i2c0 = &i2c1; - i2c1 = &i2c2; - i2c2 = &i2c3; - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - serial3 = &uart4; - serial4 = &uart5; - spi0 = &spi1; - spi1 = &spi2; - spi2 = &spi3; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "arm,arm1136jf-s"; - device_type = "cpu"; - reg = <0>; - }; - }; - - avic: interrupt-controller@68000000 { - compatible = "fsl,imx31-avic", "fsl,avic"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x68000000 0x100000>; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&avic>; - ranges; - - iram: sram@1fffc000 { - compatible = "mmio-sram"; - reg = <0x1fffc000 0x4000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1fffc000 0x4000>; - }; - - aips@43f00000 { /* AIPS1 */ - compatible = "fsl,aips-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x43f00000 0x100000>; - ranges; - - i2c1: i2c@43f80000 { - compatible = "fsl,imx31-i2c", "fsl,imx21-i2c"; - reg = <0x43f80000 0x4000>; - interrupts = <10>; - clocks = <&clks 33>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c3: i2c@43f84000 { - compatible = "fsl,imx31-i2c", "fsl,imx21-i2c"; - reg = <0x43f84000 0x4000>; - interrupts = <3>; - clocks = <&clks 35>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - ata: ata@43f8c000 { - compatible = "fsl,imx31-pata", "fsl,imx27-pata"; - reg = <0x43f8c000 0x4000>; - interrupts = <15>; - clocks = <&clks 26>; - status = "disabled"; - }; - - uart1: serial@43f90000 { - compatible = "fsl,imx31-uart", "fsl,imx21-uart"; - reg = <0x43f90000 0x4000>; - interrupts = <45>; - clocks = <&clks 10>, <&clks 30>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart2: serial@43f94000 { - compatible = "fsl,imx31-uart", "fsl,imx21-uart"; - reg = <0x43f94000 0x4000>; - interrupts = <32>; - clocks = <&clks 10>, <&clks 31>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - i2c2: i2c@43f98000 { - compatible = "fsl,imx31-i2c", "fsl,imx21-i2c"; - reg = <0x43f98000 0x4000>; - interrupts = <4>; - clocks = <&clks 34>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi1: spi@43fa4000 { - compatible = "fsl,imx31-cspi"; - reg = <0x43fa4000 0x4000>; - interrupts = <14>; - clocks = <&clks 10>, <&clks 53>; - clock-names = "ipg", "per"; - dmas = <&sdma 8 8 0>, <&sdma 9 8 0>; - dma-names = "rx", "tx"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - kpp: kpp@43fa8000 { - compatible = "fsl,imx31-kpp", "fsl,imx21-kpp"; - reg = <0x43fa8000 0x4000>; - interrupts = <24>; - clocks = <&clks 46>; - status = "disabled"; - }; - - uart4: serial@43fb0000 { - compatible = "fsl,imx31-uart", "fsl,imx21-uart"; - reg = <0x43fb0000 0x4000>; - clocks = <&clks 10>, <&clks 49>; - clock-names = "ipg", "per"; - interrupts = <46>; - status = "disabled"; - }; - - uart5: serial@43fb4000 { - compatible = "fsl,imx31-uart", "fsl,imx21-uart"; - reg = <0x43fb4000 0x4000>; - interrupts = <47>; - clocks = <&clks 10>, <&clks 50>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - }; - - spba@50000000 { - compatible = "fsl,spba-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x50000000 0x100000>; - ranges; - - sdhci1: sdhci@50004000 { - compatible = "fsl,imx31-mmc"; - reg = <0x50004000 0x4000>; - interrupts = <9>; - clocks = <&clks 10>, <&clks 20>; - clock-names = "ipg", "per"; - dmas = <&sdma 20 3 0>; - dma-names = "rx-tx"; - status = "disabled"; - }; - - sdhci2: sdhci@50008000 { - compatible = "fsl,imx31-mmc"; - reg = <0x50008000 0x4000>; - interrupts = <8>; - clocks = <&clks 10>, <&clks 21>; - clock-names = "ipg", "per"; - dmas = <&sdma 21 3 0>; - dma-names = "rx-tx"; - status = "disabled"; - }; - - uart3: serial@5000c000 { - compatible = "fsl,imx31-uart", "fsl,imx21-uart"; - reg = <0x5000c000 0x4000>; - interrupts = <18>; - clocks = <&clks 10>, <&clks 48>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - spi2: spi@50010000 { - compatible = "fsl,imx31-cspi"; - reg = <0x50010000 0x4000>; - interrupts = <13>; - clocks = <&clks 10>, <&clks 54>; - clock-names = "ipg", "per"; - dmas = <&sdma 6 8 0>, <&sdma 7 8 0>; - dma-names = "rx", "tx"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - iim: iim@5001c000 { - compatible = "fsl,imx31-iim", "fsl,imx27-iim"; - reg = <0x5001c000 0x1000>; - interrupts = <19>; - clocks = <&clks 25>; - }; - }; - - aips@53f00000 { /* AIPS2 */ - compatible = "fsl,aips-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x53f00000 0x100000>; - ranges; - - clks: ccm@53f80000{ - compatible = "fsl,imx31-ccm"; - reg = <0x53f80000 0x4000>; - interrupts = <31>, <53>; - #clock-cells = <1>; - }; - - spi3: spi@53f84000 { - compatible = "fsl,imx31-cspi"; - reg = <0x53f84000 0x4000>; - interrupts = <17>; - clocks = <&clks 10>, <&clks 28>; - clock-names = "ipg", "per"; - dmas = <&sdma 10 8 0>, <&sdma 11 8 0>; - dma-names = "rx", "tx"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - gpt: timer@53f90000 { - compatible = "fsl,imx31-gpt"; - reg = <0x53f90000 0x4000>; - interrupts = <29>; - clocks = <&clks 10>, <&clks 22>; - clock-names = "ipg", "per"; - }; - - gpio3: gpio@53fa4000 { - compatible = "fsl,imx31-gpio"; - reg = <0x53fa4000 0x4000>; - interrupts = <56>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - rng@53fb0000 { - compatible = "fsl,imx31-rnga"; - reg = <0x53fb0000 0x4000>; - interrupts = <22>; - clocks = <&clks 29>; - }; - - gpio1: gpio@53fcc000 { - compatible = "fsl,imx31-gpio"; - reg = <0x53fcc000 0x4000>; - interrupts = <52>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@53fd0000 { - compatible = "fsl,imx31-gpio"; - reg = <0x53fd0000 0x4000>; - interrupts = <51>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - sdma: sdma@53fd4000 { - compatible = "fsl,imx31-sdma"; - reg = <0x53fd4000 0x4000>; - interrupts = <34>; - clocks = <&clks 10>, <&clks 27>; - clock-names = "ipg", "ahb"; - #dma-cells = <3>; - fsl,sdma-ram-script-name = "imx/sdma/sdma-imx31.bin"; - }; - - rtc: rtc@53fd8000 { - compatible = "fsl,imx31-rtc", "fsl,imx21-rtc"; - reg = <0x53fd8000 0x4000>; - interrupts = <25>; - clocks = <&clks 2>, <&clks 40>; - clock-names = "ref", "ipg"; - }; - - wdog: wdog@53fdc000 { - compatible = "fsl,imx31-wdt", "fsl,imx21-wdt"; - reg = <0x53fdc000 0x4000>; - clocks = <&clks 41>; - }; - - pwm: pwm@53fe0000 { - compatible = "fsl,imx31-pwm", "fsl,imx27-pwm"; - reg = <0x53fe0000 0x4000>; - interrupts = <26>; - clocks = <&clks 10>, <&clks 42>; - clock-names = "ipg", "per"; - #pwm-cells = <2>; - status = "disabled"; - }; - }; - - emi@b8000000 { /* External Memory Interface */ - compatible = "simple-bus"; - reg = <0xb8000000 0x5000>; - ranges; - #address-cells = <1>; - #size-cells = <1>; - - nfc: nand@b8000000 { - compatible = "fsl,imx31-nand", "fsl,imx27-nand"; - reg = <0xb8000000 0x1000>; - interrupts = <33>; - clocks = <&clks 9>; - dmas = <&sdma 30 17 0>; - dma-names = "rx-tx"; - #address-cells = <1>; - #size-cells = <1>; - status = "disabled"; - }; - - weim: weim@b8002000 { - compatible = "fsl,imx31-weim", "fsl,imx27-weim"; - reg = <0xb8002000 0x1000>; - clocks = <&clks 56>; - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0xa0000000 0x08000000 - 1 0 0xa8000000 0x08000000 - 2 0 0xb0000000 0x02000000 - 3 0 0xb2000000 0x02000000 - 4 0 0xb4000000 0x02000000 - 5 0 0xb6000000 0x02000000>; - status = "disabled"; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/imx35-eukrea-cpuimx35.dtsi b/sys/gnu/dts/arm/imx35-eukrea-cpuimx35.dtsi deleted file mode 100644 index 17bd2a97609..00000000000 --- a/sys/gnu/dts/arm/imx35-eukrea-cpuimx35.dtsi +++ /dev/null @@ -1,89 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Eukréa Electromatique - */ - -#include "imx35.dtsi" - -/ { - model = "Eukrea CPUIMX35"; - compatible = "eukrea,cpuimx35", "fsl,imx35"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x8000000>; /* 128M */ - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec>; - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pcf8563@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; - - tsc2007: tsc2007@48 { - compatible = "ti,tsc2007"; - gpios = <&gpio3 2 0>; - interrupt-parent = <&gpio3>; - interrupts = <0x2 0x8>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_tsc2007_1>; - reg = <0x48>; - ti,x-plate-ohms = <180>; - }; -}; - -&iomuxc { - imx35-eukrea { - pinctrl_fec: fecgrp { - fsl,pins = < - MX35_PAD_FEC_TX_CLK__FEC_TX_CLK 0x80000000 - MX35_PAD_FEC_RX_CLK__FEC_RX_CLK 0x80000000 - MX35_PAD_FEC_RX_DV__FEC_RX_DV 0x80000000 - MX35_PAD_FEC_COL__FEC_COL 0x80000000 - MX35_PAD_FEC_RDATA0__FEC_RDATA_0 0x80000000 - MX35_PAD_FEC_TDATA0__FEC_TDATA_0 0x80000000 - MX35_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 - MX35_PAD_FEC_MDC__FEC_MDC 0x80000000 - MX35_PAD_FEC_MDIO__FEC_MDIO 0x80000000 - MX35_PAD_FEC_TX_ERR__FEC_TX_ERR 0x80000000 - MX35_PAD_FEC_RX_ERR__FEC_RX_ERR 0x80000000 - MX35_PAD_FEC_CRS__FEC_CRS 0x80000000 - MX35_PAD_FEC_RDATA1__FEC_RDATA_1 0x80000000 - MX35_PAD_FEC_TDATA1__FEC_TDATA_1 0x80000000 - MX35_PAD_FEC_RDATA2__FEC_RDATA_2 0x80000000 - MX35_PAD_FEC_TDATA2__FEC_TDATA_2 0x80000000 - MX35_PAD_FEC_RDATA3__FEC_RDATA_3 0x80000000 - MX35_PAD_FEC_TDATA3__FEC_TDATA_3 0x80000000 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX35_PAD_I2C1_CLK__I2C1_SCL 0x80000000 - MX35_PAD_I2C1_DAT__I2C1_SDA 0x80000000 - >; - }; - - pinctrl_tsc2007_1: tsc2007grp-1 { - fsl,pins = ; - }; - }; -}; - -&nfc { - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - nand-on-flash-bbt; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx35-eukrea-mbimxsd35-baseboard.dts b/sys/gnu/dts/arm/imx35-eukrea-mbimxsd35-baseboard.dts deleted file mode 100644 index b1c11170ac2..00000000000 --- a/sys/gnu/dts/arm/imx35-eukrea-mbimxsd35-baseboard.dts +++ /dev/null @@ -1,156 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Eukréa Electromatique - */ - -/dts-v1/; - -#include -#include -#include "imx35-eukrea-cpuimx35.dtsi" - -/ { - model = "Eukrea CPUIMX35"; - compatible = "eukrea,mbimxsd35-baseboard", "eukrea,cpuimx35", "fsl,imx35"; - - gpio_keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_bp1>; - - bp1 { - label = "BP1"; - gpios = <&gpio3 25 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - linux,input-type = <1>; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_led1>; - - led1 { - label = "led1"; - gpios = <&gpio3 29 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - }; - }; - - sound { - compatible = "eukrea,asoc-tlv320"; - eukrea,model = "imx35-eukrea-tlv320aic23"; - ssi-controller = <&ssi1>; - fsl,mux-int-port = <1>; - fsl,mux-ext-port = <4>; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; - -&esdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc1>; - cd-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&i2c1 { - tlv320aic23: codec@1a { - compatible = "ti,tlv320aic23"; - reg = <0x1a>; - }; -}; - -&iomuxc { - imx35-eukrea { - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS 0x80000000 - MX35_PAD_STXD4__AUDMUX_AUD4_TXD 0x80000000 - MX35_PAD_SRXD4__AUDMUX_AUD4_RXD 0x80000000 - MX35_PAD_SCK4__AUDMUX_AUD4_TXC 0x80000000 - >; - }; - - pinctrl_bp1: bp1grp { - fsl,pins = ; - }; - - pinctrl_esdhc1: esdhc1grp { - fsl,pins = < - MX35_PAD_SD1_CMD__ESDHC1_CMD 0x80000000 - MX35_PAD_SD1_CLK__ESDHC1_CLK 0x80000000 - MX35_PAD_SD1_DATA0__ESDHC1_DAT0 0x80000000 - MX35_PAD_SD1_DATA1__ESDHC1_DAT1 0x80000000 - MX35_PAD_SD1_DATA2__ESDHC1_DAT2 0x80000000 - MX35_PAD_SD1_DATA3__ESDHC1_DAT3 0x80000000 - MX35_PAD_LD18__GPIO3_24 0x80000000 /* CD */ - >; - }; - - pinctrl_led1: led1grp { - fsl,pins = ; - }; - - pinctrl_reg_lcd_3v3: reg-lcd-3v3 { - fsl,pins = ; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX35_PAD_TXD1__UART1_TXD_MUX 0x1c5 - MX35_PAD_RXD1__UART1_RXD_MUX 0x1c5 - MX35_PAD_CTS1__UART1_CTS 0x1c5 - MX35_PAD_RTS1__UART1_RTS 0x1c5 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX35_PAD_RXD2__UART2_RXD_MUX 0x1c5 - MX35_PAD_TXD2__UART2_TXD_MUX 0x1c5 - MX35_PAD_RTS2__UART2_RTS 0x1c5 - MX35_PAD_CTS2__UART2_CTS 0x1c5 - >; - }; - }; -}; - -&ssi1 { - codec-handle = <&tlv320aic23>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - uart-has-rtscts; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - uart-has-rtscts; - status = "okay"; -}; - -&usbhost1 { - phy_type = "serial"; - dr_mode = "host"; - status = "okay"; -}; - -&usbotg { - phy_type = "utmi"; - dr_mode = "otg"; - external-vbus-divider; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx35-pdk.dts b/sys/gnu/dts/arm/imx35-pdk.dts deleted file mode 100644 index ddce0a84475..00000000000 --- a/sys/gnu/dts/arm/imx35-pdk.dts +++ /dev/null @@ -1,62 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// -// Copyright 2013 Eukréa Electromatique -// Copyright 2014 Freescale Semiconductor, Inc. - -/dts-v1/; -#include "imx35.dtsi" - -/ { - model = "Freescale i.MX35 Product Development Kit"; - compatible = "fsl,imx35-pdk", "fsl,imx35"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x8000000>, - <0x90000000 0x8000000>; - }; -}; - -&esdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc1>; - status = "okay"; -}; - -&iomuxc { - imx35-pdk { - pinctrl_esdhc1: esdhc1grp { - fsl,pins = < - MX35_PAD_SD1_CMD__ESDHC1_CMD 0x80000000 - MX35_PAD_SD1_CLK__ESDHC1_CLK 0x80000000 - MX35_PAD_SD1_DATA0__ESDHC1_DAT0 0x80000000 - MX35_PAD_SD1_DATA1__ESDHC1_DAT1 0x80000000 - MX35_PAD_SD1_DATA2__ESDHC1_DAT2 0x80000000 - MX35_PAD_SD1_DATA3__ESDHC1_DAT3 0x80000000 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX35_PAD_TXD1__UART1_TXD_MUX 0x1c5 - MX35_PAD_RXD1__UART1_RXD_MUX 0x1c5 - MX35_PAD_CTS1__UART1_CTS 0x1c5 - MX35_PAD_RTS1__UART1_RTS 0x1c5 - >; - }; - }; -}; - -&nfc { - nand-bus-width = <16>; - nand-ecc-mode = "hw"; - nand-on-flash-bbt; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - uart-has-rtscts; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx35-pinfunc.h b/sys/gnu/dts/arm/imx35-pinfunc.h deleted file mode 100644 index 9d6cc9564b7..00000000000 --- a/sys/gnu/dts/arm/imx35-pinfunc.h +++ /dev/null @@ -1,966 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - */ - -#ifndef __DTS_IMX35_PINFUNC_H -#define __DTS_IMX35_PINFUNC_H - -/* - * The pin function ID is a tuple of - * - */ -#define MX35_PAD_CAPTURE__GPT_CAPIN1 0x004 0x328 0x000 0x0 0x0 -#define MX35_PAD_CAPTURE__GPT_CMPOUT2 0x004 0x328 0x000 0x1 0x0 -#define MX35_PAD_CAPTURE__CSPI2_SS1 0x004 0x328 0x7f4 0x2 0x0 -#define MX35_PAD_CAPTURE__EPIT1_EPITO 0x004 0x328 0x000 0x3 0x0 -#define MX35_PAD_CAPTURE__CCM_CLK32K 0x004 0x328 0x7d0 0x4 0x0 -#define MX35_PAD_CAPTURE__GPIO1_4 0x004 0x328 0x850 0x5 0x0 -#define MX35_PAD_COMPARE__GPT_CMPOUT1 0x008 0x32c 0x000 0x0 0x0 -#define MX35_PAD_COMPARE__GPT_CAPIN2 0x008 0x32c 0x000 0x1 0x0 -#define MX35_PAD_COMPARE__GPT_CMPOUT3 0x008 0x32c 0x000 0x2 0x0 -#define MX35_PAD_COMPARE__EPIT2_EPITO 0x008 0x32c 0x000 0x3 0x0 -#define MX35_PAD_COMPARE__GPIO1_5 0x008 0x32c 0x854 0x5 0x0 -#define MX35_PAD_COMPARE__SDMA_EXTDMA_2 0x008 0x32c 0x000 0x7 0x0 -#define MX35_PAD_WDOG_RST__WDOG_WDOG_B 0x00c 0x330 0x000 0x0 0x0 -#define MX35_PAD_WDOG_RST__IPU_FLASH_STROBE 0x00c 0x330 0x000 0x3 0x0 -#define MX35_PAD_WDOG_RST__GPIO1_6 0x00c 0x330 0x858 0x5 0x0 -#define MX35_PAD_GPIO1_0__GPIO1_0 0x010 0x334 0x82c 0x0 0x0 -#define MX35_PAD_GPIO1_0__CCM_PMIC_RDY 0x010 0x334 0x7d4 0x1 0x0 -#define MX35_PAD_GPIO1_0__OWIRE_LINE 0x010 0x334 0x990 0x2 0x0 -#define MX35_PAD_GPIO1_0__SDMA_EXTDMA_0 0x010 0x334 0x000 0x7 0x0 -#define MX35_PAD_GPIO1_1__GPIO1_1 0x014 0x338 0x838 0x0 0x0 -#define MX35_PAD_GPIO1_1__PWM_PWMO 0x014 0x338 0x000 0x2 0x0 -#define MX35_PAD_GPIO1_1__CSPI1_SS2 0x014 0x338 0x7d8 0x3 0x0 -#define MX35_PAD_GPIO1_1__SCC_TAMPER_DETECT 0x014 0x338 0x000 0x6 0x0 -#define MX35_PAD_GPIO1_1__SDMA_EXTDMA_1 0x014 0x338 0x000 0x7 0x0 -#define MX35_PAD_GPIO2_0__GPIO2_0 0x018 0x33c 0x868 0x0 0x0 -#define MX35_PAD_GPIO2_0__USB_TOP_USBOTG_CLK 0x018 0x33c 0x000 0x1 0x0 -#define MX35_PAD_GPIO3_0__GPIO3_0 0x01c 0x340 0x8e8 0x0 0x0 -#define MX35_PAD_GPIO3_0__USB_TOP_USBH2_CLK 0x01c 0x340 0x000 0x1 0x0 -#define MX35_PAD_RESET_IN_B__CCM_RESET_IN_B 0x000 0x344 0x000 0x0 0x0 -#define MX35_PAD_POR_B__CCM_POR_B 0x000 0x348 0x000 0x0 0x0 -#define MX35_PAD_CLKO__CCM_CLKO 0x020 0x34c 0x000 0x0 0x0 -#define MX35_PAD_CLKO__GPIO1_8 0x020 0x34c 0x860 0x5 0x0 -#define MX35_PAD_BOOT_MODE0__CCM_BOOT_MODE_0 0x000 0x350 0x000 0x0 0x0 -#define MX35_PAD_BOOT_MODE1__CCM_BOOT_MODE_1 0x000 0x354 0x000 0x0 0x0 -#define MX35_PAD_CLK_MODE0__CCM_CLK_MODE_0 0x000 0x358 0x000 0x0 0x0 -#define MX35_PAD_CLK_MODE1__CCM_CLK_MODE_1 0x000 0x35c 0x000 0x0 0x0 -#define MX35_PAD_POWER_FAIL__CCM_DSM_WAKEUP_INT_26 0x000 0x360 0x000 0x0 0x0 -#define MX35_PAD_VSTBY__CCM_VSTBY 0x024 0x364 0x000 0x0 0x0 -#define MX35_PAD_VSTBY__GPIO1_7 0x024 0x364 0x85c 0x5 0x0 -#define MX35_PAD_A0__EMI_EIM_DA_L_0 0x028 0x368 0x000 0x0 0x0 -#define MX35_PAD_A1__EMI_EIM_DA_L_1 0x02c 0x36c 0x000 0x0 0x0 -#define MX35_PAD_A2__EMI_EIM_DA_L_2 0x030 0x370 0x000 0x0 0x0 -#define MX35_PAD_A3__EMI_EIM_DA_L_3 0x034 0x374 0x000 0x0 0x0 -#define MX35_PAD_A4__EMI_EIM_DA_L_4 0x038 0x378 0x000 0x0 0x0 -#define MX35_PAD_A5__EMI_EIM_DA_L_5 0x03c 0x37c 0x000 0x0 0x0 -#define MX35_PAD_A6__EMI_EIM_DA_L_6 0x040 0x380 0x000 0x0 0x0 -#define MX35_PAD_A7__EMI_EIM_DA_L_7 0x044 0x384 0x000 0x0 0x0 -#define MX35_PAD_A8__EMI_EIM_DA_H_8 0x048 0x388 0x000 0x0 0x0 -#define MX35_PAD_A9__EMI_EIM_DA_H_9 0x04c 0x38c 0x000 0x0 0x0 -#define MX35_PAD_A10__EMI_EIM_DA_H_10 0x050 0x390 0x000 0x0 0x0 -#define MX35_PAD_MA10__EMI_MA10 0x054 0x394 0x000 0x0 0x0 -#define MX35_PAD_A11__EMI_EIM_DA_H_11 0x058 0x398 0x000 0x0 0x0 -#define MX35_PAD_A12__EMI_EIM_DA_H_12 0x05c 0x39c 0x000 0x0 0x0 -#define MX35_PAD_A13__EMI_EIM_DA_H_13 0x060 0x3a0 0x000 0x0 0x0 -#define MX35_PAD_A14__EMI_EIM_DA_H2_14 0x064 0x3a4 0x000 0x0 0x0 -#define MX35_PAD_A15__EMI_EIM_DA_H2_15 0x068 0x3a8 0x000 0x0 0x0 -#define MX35_PAD_A16__EMI_EIM_A_16 0x06c 0x3ac 0x000 0x0 0x0 -#define MX35_PAD_A17__EMI_EIM_A_17 0x070 0x3b0 0x000 0x0 0x0 -#define MX35_PAD_A18__EMI_EIM_A_18 0x074 0x3b4 0x000 0x0 0x0 -#define MX35_PAD_A19__EMI_EIM_A_19 0x078 0x3b8 0x000 0x0 0x0 -#define MX35_PAD_A20__EMI_EIM_A_20 0x07c 0x3bc 0x000 0x0 0x0 -#define MX35_PAD_A21__EMI_EIM_A_21 0x080 0x3c0 0x000 0x0 0x0 -#define MX35_PAD_A22__EMI_EIM_A_22 0x084 0x3c4 0x000 0x0 0x0 -#define MX35_PAD_A23__EMI_EIM_A_23 0x088 0x3c8 0x000 0x0 0x0 -#define MX35_PAD_A24__EMI_EIM_A_24 0x08c 0x3cc 0x000 0x0 0x0 -#define MX35_PAD_A25__EMI_EIM_A_25 0x090 0x3d0 0x000 0x0 0x0 -#define MX35_PAD_SDBA1__EMI_EIM_SDBA1 0x000 0x3d4 0x000 0x0 0x0 -#define MX35_PAD_SDBA0__EMI_EIM_SDBA0 0x000 0x3d8 0x000 0x0 0x0 -#define MX35_PAD_SD0__EMI_DRAM_D_0 0x000 0x3dc 0x000 0x0 0x0 -#define MX35_PAD_SD1__EMI_DRAM_D_1 0x000 0x3e0 0x000 0x0 0x0 -#define MX35_PAD_SD2__EMI_DRAM_D_2 0x000 0x3e4 0x000 0x0 0x0 -#define MX35_PAD_SD3__EMI_DRAM_D_3 0x000 0x3e8 0x000 0x0 0x0 -#define MX35_PAD_SD4__EMI_DRAM_D_4 0x000 0x3ec 0x000 0x0 0x0 -#define MX35_PAD_SD5__EMI_DRAM_D_5 0x000 0x3f0 0x000 0x0 0x0 -#define MX35_PAD_SD6__EMI_DRAM_D_6 0x000 0x3f4 0x000 0x0 0x0 -#define MX35_PAD_SD7__EMI_DRAM_D_7 0x000 0x3f8 0x000 0x0 0x0 -#define MX35_PAD_SD8__EMI_DRAM_D_8 0x000 0x3fc 0x000 0x0 0x0 -#define MX35_PAD_SD9__EMI_DRAM_D_9 0x000 0x400 0x000 0x0 0x0 -#define MX35_PAD_SD10__EMI_DRAM_D_10 0x000 0x404 0x000 0x0 0x0 -#define MX35_PAD_SD11__EMI_DRAM_D_11 0x000 0x408 0x000 0x0 0x0 -#define MX35_PAD_SD12__EMI_DRAM_D_12 0x000 0x40c 0x000 0x0 0x0 -#define MX35_PAD_SD13__EMI_DRAM_D_13 0x000 0x410 0x000 0x0 0x0 -#define MX35_PAD_SD14__EMI_DRAM_D_14 0x000 0x414 0x000 0x0 0x0 -#define MX35_PAD_SD15__EMI_DRAM_D_15 0x000 0x418 0x000 0x0 0x0 -#define MX35_PAD_SD16__EMI_DRAM_D_16 0x000 0x41c 0x000 0x0 0x0 -#define MX35_PAD_SD17__EMI_DRAM_D_17 0x000 0x420 0x000 0x0 0x0 -#define MX35_PAD_SD18__EMI_DRAM_D_18 0x000 0x424 0x000 0x0 0x0 -#define MX35_PAD_SD19__EMI_DRAM_D_19 0x000 0x428 0x000 0x0 0x0 -#define MX35_PAD_SD20__EMI_DRAM_D_20 0x000 0x42c 0x000 0x0 0x0 -#define MX35_PAD_SD21__EMI_DRAM_D_21 0x000 0x430 0x000 0x0 0x0 -#define MX35_PAD_SD22__EMI_DRAM_D_22 0x000 0x434 0x000 0x0 0x0 -#define MX35_PAD_SD23__EMI_DRAM_D_23 0x000 0x438 0x000 0x0 0x0 -#define MX35_PAD_SD24__EMI_DRAM_D_24 0x000 0x43c 0x000 0x0 0x0 -#define MX35_PAD_SD25__EMI_DRAM_D_25 0x000 0x440 0x000 0x0 0x0 -#define MX35_PAD_SD26__EMI_DRAM_D_26 0x000 0x444 0x000 0x0 0x0 -#define MX35_PAD_SD27__EMI_DRAM_D_27 0x000 0x448 0x000 0x0 0x0 -#define MX35_PAD_SD28__EMI_DRAM_D_28 0x000 0x44c 0x000 0x0 0x0 -#define MX35_PAD_SD29__EMI_DRAM_D_29 0x000 0x450 0x000 0x0 0x0 -#define MX35_PAD_SD30__EMI_DRAM_D_30 0x000 0x454 0x000 0x0 0x0 -#define MX35_PAD_SD31__EMI_DRAM_D_31 0x000 0x458 0x000 0x0 0x0 -#define MX35_PAD_DQM0__EMI_DRAM_DQM_0 0x000 0x45c 0x000 0x0 0x0 -#define MX35_PAD_DQM1__EMI_DRAM_DQM_1 0x000 0x460 0x000 0x0 0x0 -#define MX35_PAD_DQM2__EMI_DRAM_DQM_2 0x000 0x464 0x000 0x0 0x0 -#define MX35_PAD_DQM3__EMI_DRAM_DQM_3 0x000 0x468 0x000 0x0 0x0 -#define MX35_PAD_EB0__EMI_EIM_EB0_B 0x094 0x46c 0x000 0x0 0x0 -#define MX35_PAD_EB1__EMI_EIM_EB1_B 0x098 0x470 0x000 0x0 0x0 -#define MX35_PAD_OE__EMI_EIM_OE 0x09c 0x474 0x000 0x0 0x0 -#define MX35_PAD_CS0__EMI_EIM_CS0 0x0a0 0x478 0x000 0x0 0x0 -#define MX35_PAD_CS1__EMI_EIM_CS1 0x0a4 0x47c 0x000 0x0 0x0 -#define MX35_PAD_CS1__EMI_NANDF_CE3 0x0a4 0x47c 0x000 0x3 0x0 -#define MX35_PAD_CS2__EMI_EIM_CS2 0x0a8 0x480 0x000 0x0 0x0 -#define MX35_PAD_CS3__EMI_EIM_CS3 0x0ac 0x484 0x000 0x0 0x0 -#define MX35_PAD_CS4__EMI_EIM_CS4 0x0b0 0x488 0x000 0x0 0x0 -#define MX35_PAD_CS4__EMI_DTACK_B 0x0b0 0x488 0x800 0x1 0x0 -#define MX35_PAD_CS4__EMI_NANDF_CE1 0x0b0 0x488 0x000 0x3 0x0 -#define MX35_PAD_CS4__GPIO1_20 0x0b0 0x488 0x83c 0x5 0x0 -#define MX35_PAD_CS5__EMI_EIM_CS5 0x0b4 0x48c 0x000 0x0 0x0 -#define MX35_PAD_CS5__CSPI2_SS2 0x0b4 0x48c 0x7f8 0x1 0x0 -#define MX35_PAD_CS5__CSPI1_SS2 0x0b4 0x48c 0x7d8 0x2 0x1 -#define MX35_PAD_CS5__EMI_NANDF_CE2 0x0b4 0x48c 0x000 0x3 0x0 -#define MX35_PAD_CS5__GPIO1_21 0x0b4 0x48c 0x840 0x5 0x0 -#define MX35_PAD_NF_CE0__EMI_NANDF_CE0 0x0b8 0x490 0x000 0x0 0x0 -#define MX35_PAD_NF_CE0__GPIO1_22 0x0b8 0x490 0x844 0x5 0x0 -#define MX35_PAD_ECB__EMI_EIM_ECB 0x000 0x494 0x000 0x0 0x0 -#define MX35_PAD_LBA__EMI_EIM_LBA 0x0bc 0x498 0x000 0x0 0x0 -#define MX35_PAD_BCLK__EMI_EIM_BCLK 0x0c0 0x49c 0x000 0x0 0x0 -#define MX35_PAD_RW__EMI_EIM_RW 0x0c4 0x4a0 0x000 0x0 0x0 -#define MX35_PAD_RAS__EMI_DRAM_RAS 0x000 0x4a4 0x000 0x0 0x0 -#define MX35_PAD_CAS__EMI_DRAM_CAS 0x000 0x4a8 0x000 0x0 0x0 -#define MX35_PAD_SDWE__EMI_DRAM_SDWE 0x000 0x4ac 0x000 0x0 0x0 -#define MX35_PAD_SDCKE0__EMI_DRAM_SDCKE_0 0x000 0x4b0 0x000 0x0 0x0 -#define MX35_PAD_SDCKE1__EMI_DRAM_SDCKE_1 0x000 0x4b4 0x000 0x0 0x0 -#define MX35_PAD_SDCLK__EMI_DRAM_SDCLK 0x000 0x4b8 0x000 0x0 0x0 -#define MX35_PAD_SDQS0__EMI_DRAM_SDQS_0 0x000 0x4bc 0x000 0x0 0x0 -#define MX35_PAD_SDQS1__EMI_DRAM_SDQS_1 0x000 0x4c0 0x000 0x0 0x0 -#define MX35_PAD_SDQS2__EMI_DRAM_SDQS_2 0x000 0x4c4 0x000 0x0 0x0 -#define MX35_PAD_SDQS3__EMI_DRAM_SDQS_3 0x000 0x4c8 0x000 0x0 0x0 -#define MX35_PAD_NFWE_B__EMI_NANDF_WE_B 0x0c8 0x4cc 0x000 0x0 0x0 -#define MX35_PAD_NFWE_B__USB_TOP_USBH2_DATA_3 0x0c8 0x4cc 0x9d8 0x1 0x0 -#define MX35_PAD_NFWE_B__IPU_DISPB_D0_VSYNC 0x0c8 0x4cc 0x924 0x2 0x0 -#define MX35_PAD_NFWE_B__GPIO2_18 0x0c8 0x4cc 0x88c 0x5 0x0 -#define MX35_PAD_NFWE_B__ARM11P_TOP_TRACE_0 0x0c8 0x4cc 0x000 0x7 0x0 -#define MX35_PAD_NFRE_B__EMI_NANDF_RE_B 0x0cc 0x4d0 0x000 0x0 0x0 -#define MX35_PAD_NFRE_B__USB_TOP_USBH2_DIR 0x0cc 0x4d0 0x9ec 0x1 0x0 -#define MX35_PAD_NFRE_B__IPU_DISPB_BCLK 0x0cc 0x4d0 0x000 0x2 0x0 -#define MX35_PAD_NFRE_B__GPIO2_19 0x0cc 0x4d0 0x890 0x5 0x0 -#define MX35_PAD_NFRE_B__ARM11P_TOP_TRACE_1 0x0cc 0x4d0 0x000 0x7 0x0 -#define MX35_PAD_NFALE__EMI_NANDF_ALE 0x0d0 0x4d4 0x000 0x0 0x0 -#define MX35_PAD_NFALE__USB_TOP_USBH2_STP 0x0d0 0x4d4 0x000 0x1 0x0 -#define MX35_PAD_NFALE__IPU_DISPB_CS0 0x0d0 0x4d4 0x000 0x2 0x0 -#define MX35_PAD_NFALE__GPIO2_20 0x0d0 0x4d4 0x898 0x5 0x0 -#define MX35_PAD_NFALE__ARM11P_TOP_TRACE_2 0x0d0 0x4d4 0x000 0x7 0x0 -#define MX35_PAD_NFCLE__EMI_NANDF_CLE 0x0d4 0x4d8 0x000 0x0 0x0 -#define MX35_PAD_NFCLE__USB_TOP_USBH2_NXT 0x0d4 0x4d8 0x9f0 0x1 0x0 -#define MX35_PAD_NFCLE__IPU_DISPB_PAR_RS 0x0d4 0x4d8 0x000 0x2 0x0 -#define MX35_PAD_NFCLE__GPIO2_21 0x0d4 0x4d8 0x89c 0x5 0x0 -#define MX35_PAD_NFCLE__ARM11P_TOP_TRACE_3 0x0d4 0x4d8 0x000 0x7 0x0 -#define MX35_PAD_NFWP_B__EMI_NANDF_WP_B 0x0d8 0x4dc 0x000 0x0 0x0 -#define MX35_PAD_NFWP_B__USB_TOP_USBH2_DATA_7 0x0d8 0x4dc 0x9e8 0x1 0x0 -#define MX35_PAD_NFWP_B__IPU_DISPB_WR 0x0d8 0x4dc 0x000 0x2 0x0 -#define MX35_PAD_NFWP_B__GPIO2_22 0x0d8 0x4dc 0x8a0 0x5 0x0 -#define MX35_PAD_NFWP_B__ARM11P_TOP_TRCTL 0x0d8 0x4dc 0x000 0x7 0x0 -#define MX35_PAD_NFRB__EMI_NANDF_RB 0x0dc 0x4e0 0x000 0x0 0x0 -#define MX35_PAD_NFRB__IPU_DISPB_RD 0x0dc 0x4e0 0x000 0x2 0x0 -#define MX35_PAD_NFRB__GPIO2_23 0x0dc 0x4e0 0x8a4 0x5 0x0 -#define MX35_PAD_NFRB__ARM11P_TOP_TRCLK 0x0dc 0x4e0 0x000 0x7 0x0 -#define MX35_PAD_D15__EMI_EIM_D_15 0x000 0x4e4 0x000 0x0 0x0 -#define MX35_PAD_D14__EMI_EIM_D_14 0x000 0x4e8 0x000 0x0 0x0 -#define MX35_PAD_D13__EMI_EIM_D_13 0x000 0x4ec 0x000 0x0 0x0 -#define MX35_PAD_D12__EMI_EIM_D_12 0x000 0x4f0 0x000 0x0 0x0 -#define MX35_PAD_D11__EMI_EIM_D_11 0x000 0x4f4 0x000 0x0 0x0 -#define MX35_PAD_D10__EMI_EIM_D_10 0x000 0x4f8 0x000 0x0 0x0 -#define MX35_PAD_D9__EMI_EIM_D_9 0x000 0x4fc 0x000 0x0 0x0 -#define MX35_PAD_D8__EMI_EIM_D_8 0x000 0x500 0x000 0x0 0x0 -#define MX35_PAD_D7__EMI_EIM_D_7 0x000 0x504 0x000 0x0 0x0 -#define MX35_PAD_D6__EMI_EIM_D_6 0x000 0x508 0x000 0x0 0x0 -#define MX35_PAD_D5__EMI_EIM_D_5 0x000 0x50c 0x000 0x0 0x0 -#define MX35_PAD_D4__EMI_EIM_D_4 0x000 0x510 0x000 0x0 0x0 -#define MX35_PAD_D3__EMI_EIM_D_3 0x000 0x514 0x000 0x0 0x0 -#define MX35_PAD_D2__EMI_EIM_D_2 0x000 0x518 0x000 0x0 0x0 -#define MX35_PAD_D1__EMI_EIM_D_1 0x000 0x51c 0x000 0x0 0x0 -#define MX35_PAD_D0__EMI_EIM_D_0 0x000 0x520 0x000 0x0 0x0 -#define MX35_PAD_CSI_D8__IPU_CSI_D_8 0x0e0 0x524 0x000 0x0 0x0 -#define MX35_PAD_CSI_D8__KPP_COL_0 0x0e0 0x524 0x950 0x1 0x0 -#define MX35_PAD_CSI_D8__GPIO1_20 0x0e0 0x524 0x83c 0x5 0x1 -#define MX35_PAD_CSI_D8__ARM11P_TOP_EVNTBUS_13 0x0e0 0x524 0x000 0x7 0x0 -#define MX35_PAD_CSI_D9__IPU_CSI_D_9 0x0e4 0x528 0x000 0x0 0x0 -#define MX35_PAD_CSI_D9__KPP_COL_1 0x0e4 0x528 0x954 0x1 0x0 -#define MX35_PAD_CSI_D9__GPIO1_21 0x0e4 0x528 0x840 0x5 0x1 -#define MX35_PAD_CSI_D9__ARM11P_TOP_EVNTBUS_14 0x0e4 0x528 0x000 0x7 0x0 -#define MX35_PAD_CSI_D10__IPU_CSI_D_10 0x0e8 0x52c 0x000 0x0 0x0 -#define MX35_PAD_CSI_D10__KPP_COL_2 0x0e8 0x52c 0x958 0x1 0x0 -#define MX35_PAD_CSI_D10__GPIO1_22 0x0e8 0x52c 0x844 0x5 0x1 -#define MX35_PAD_CSI_D10__ARM11P_TOP_EVNTBUS_15 0x0e8 0x52c 0x000 0x7 0x0 -#define MX35_PAD_CSI_D11__IPU_CSI_D_11 0x0ec 0x530 0x000 0x0 0x0 -#define MX35_PAD_CSI_D11__KPP_COL_3 0x0ec 0x530 0x95c 0x1 0x0 -#define MX35_PAD_CSI_D11__GPIO1_23 0x0ec 0x530 0x000 0x5 0x0 -#define MX35_PAD_CSI_D12__IPU_CSI_D_12 0x0f0 0x534 0x000 0x0 0x0 -#define MX35_PAD_CSI_D12__KPP_ROW_0 0x0f0 0x534 0x970 0x1 0x0 -#define MX35_PAD_CSI_D12__GPIO1_24 0x0f0 0x534 0x000 0x5 0x0 -#define MX35_PAD_CSI_D13__IPU_CSI_D_13 0x0f4 0x538 0x000 0x0 0x0 -#define MX35_PAD_CSI_D13__KPP_ROW_1 0x0f4 0x538 0x974 0x1 0x0 -#define MX35_PAD_CSI_D13__GPIO1_25 0x0f4 0x538 0x000 0x5 0x0 -#define MX35_PAD_CSI_D14__IPU_CSI_D_14 0x0f8 0x53c 0x000 0x0 0x0 -#define MX35_PAD_CSI_D14__KPP_ROW_2 0x0f8 0x53c 0x978 0x1 0x0 -#define MX35_PAD_CSI_D14__GPIO1_26 0x0f8 0x53c 0x000 0x5 0x0 -#define MX35_PAD_CSI_D15__IPU_CSI_D_15 0x0fc 0x540 0x97c 0x0 0x0 -#define MX35_PAD_CSI_D15__KPP_ROW_3 0x0fc 0x540 0x000 0x1 0x0 -#define MX35_PAD_CSI_D15__GPIO1_27 0x0fc 0x540 0x000 0x5 0x0 -#define MX35_PAD_CSI_MCLK__IPU_CSI_MCLK 0x100 0x544 0x000 0x0 0x0 -#define MX35_PAD_CSI_MCLK__GPIO1_28 0x100 0x544 0x000 0x5 0x0 -#define MX35_PAD_CSI_VSYNC__IPU_CSI_VSYNC 0x104 0x548 0x000 0x0 0x0 -#define MX35_PAD_CSI_VSYNC__GPIO1_29 0x104 0x548 0x000 0x5 0x0 -#define MX35_PAD_CSI_HSYNC__IPU_CSI_HSYNC 0x108 0x54c 0x000 0x0 0x0 -#define MX35_PAD_CSI_HSYNC__GPIO1_30 0x108 0x54c 0x000 0x5 0x0 -#define MX35_PAD_CSI_PIXCLK__IPU_CSI_PIXCLK 0x10c 0x550 0x000 0x0 0x0 -#define MX35_PAD_CSI_PIXCLK__GPIO1_31 0x10c 0x550 0x000 0x5 0x0 -#define MX35_PAD_I2C1_CLK__I2C1_SCL 0x110 0x554 0x000 0x0 0x0 -#define MX35_PAD_I2C1_CLK__GPIO2_24 0x110 0x554 0x8a8 0x5 0x0 -#define MX35_PAD_I2C1_CLK__CCM_USB_BYP_CLK 0x110 0x554 0x000 0x6 0x0 -#define MX35_PAD_I2C1_DAT__I2C1_SDA 0x114 0x558 0x000 0x0 0x0 -#define MX35_PAD_I2C1_DAT__GPIO2_25 0x114 0x558 0x8ac 0x5 0x0 -#define MX35_PAD_I2C2_CLK__I2C2_SCL 0x118 0x55c 0x000 0x0 0x0 -#define MX35_PAD_I2C2_CLK__CAN1_TXCAN 0x118 0x55c 0x000 0x1 0x0 -#define MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR 0x118 0x55c 0x000 0x2 0x0 -#define MX35_PAD_I2C2_CLK__GPIO2_26 0x118 0x55c 0x8b0 0x5 0x0 -#define MX35_PAD_I2C2_CLK__SDMA_DEBUG_BUS_DEVICE_2 0x118 0x55c 0x000 0x6 0x0 -#define MX35_PAD_I2C2_DAT__I2C2_SDA 0x11c 0x560 0x000 0x0 0x0 -#define MX35_PAD_I2C2_DAT__CAN1_RXCAN 0x11c 0x560 0x7c8 0x1 0x0 -#define MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC 0x11c 0x560 0x9f4 0x2 0x0 -#define MX35_PAD_I2C2_DAT__GPIO2_27 0x11c 0x560 0x8b4 0x5 0x0 -#define MX35_PAD_I2C2_DAT__SDMA_DEBUG_BUS_DEVICE_3 0x11c 0x560 0x000 0x6 0x0 -#define MX35_PAD_STXD4__AUDMUX_AUD4_TXD 0x120 0x564 0x000 0x0 0x0 -#define MX35_PAD_STXD4__GPIO2_28 0x120 0x564 0x8b8 0x5 0x0 -#define MX35_PAD_STXD4__ARM11P_TOP_ARM_COREASID0 0x120 0x564 0x000 0x7 0x0 -#define MX35_PAD_SRXD4__AUDMUX_AUD4_RXD 0x124 0x568 0x000 0x0 0x0 -#define MX35_PAD_SRXD4__GPIO2_29 0x124 0x568 0x8bc 0x5 0x0 -#define MX35_PAD_SRXD4__ARM11P_TOP_ARM_COREASID1 0x124 0x568 0x000 0x7 0x0 -#define MX35_PAD_SCK4__AUDMUX_AUD4_TXC 0x128 0x56c 0x000 0x0 0x0 -#define MX35_PAD_SCK4__GPIO2_30 0x128 0x56c 0x8c4 0x5 0x0 -#define MX35_PAD_SCK4__ARM11P_TOP_ARM_COREASID2 0x128 0x56c 0x000 0x7 0x0 -#define MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS 0x12c 0x570 0x000 0x0 0x0 -#define MX35_PAD_STXFS4__GPIO2_31 0x12c 0x570 0x8c8 0x5 0x0 -#define MX35_PAD_STXFS4__ARM11P_TOP_ARM_COREASID3 0x12c 0x570 0x000 0x7 0x0 -#define MX35_PAD_STXD5__AUDMUX_AUD5_TXD 0x130 0x574 0x000 0x0 0x0 -#define MX35_PAD_STXD5__SPDIF_SPDIF_OUT1 0x130 0x574 0x000 0x1 0x0 -#define MX35_PAD_STXD5__CSPI2_MOSI 0x130 0x574 0x7ec 0x2 0x0 -#define MX35_PAD_STXD5__GPIO1_0 0x130 0x574 0x82c 0x5 0x1 -#define MX35_PAD_STXD5__ARM11P_TOP_ARM_COREASID4 0x130 0x574 0x000 0x7 0x0 -#define MX35_PAD_SRXD5__AUDMUX_AUD5_RXD 0x134 0x578 0x000 0x0 0x0 -#define MX35_PAD_SRXD5__SPDIF_SPDIF_IN1 0x134 0x578 0x998 0x1 0x0 -#define MX35_PAD_SRXD5__CSPI2_MISO 0x134 0x578 0x7e8 0x2 0x0 -#define MX35_PAD_SRXD5__GPIO1_1 0x134 0x578 0x838 0x5 0x1 -#define MX35_PAD_SRXD5__ARM11P_TOP_ARM_COREASID5 0x134 0x578 0x000 0x7 0x0 -#define MX35_PAD_SCK5__AUDMUX_AUD5_TXC 0x138 0x57c 0x000 0x0 0x0 -#define MX35_PAD_SCK5__SPDIF_SPDIF_EXTCLK 0x138 0x57c 0x994 0x1 0x0 -#define MX35_PAD_SCK5__CSPI2_SCLK 0x138 0x57c 0x7e0 0x2 0x0 -#define MX35_PAD_SCK5__GPIO1_2 0x138 0x57c 0x848 0x5 0x0 -#define MX35_PAD_SCK5__ARM11P_TOP_ARM_COREASID6 0x138 0x57c 0x000 0x7 0x0 -#define MX35_PAD_STXFS5__AUDMUX_AUD5_TXFS 0x13c 0x580 0x000 0x0 0x0 -#define MX35_PAD_STXFS5__CSPI2_RDY 0x13c 0x580 0x7e4 0x2 0x0 -#define MX35_PAD_STXFS5__GPIO1_3 0x13c 0x580 0x84c 0x5 0x0 -#define MX35_PAD_STXFS5__ARM11P_TOP_ARM_COREASID7 0x13c 0x580 0x000 0x7 0x0 -#define MX35_PAD_SCKR__ESAI_SCKR 0x140 0x584 0x000 0x0 0x0 -#define MX35_PAD_SCKR__GPIO1_4 0x140 0x584 0x850 0x5 0x1 -#define MX35_PAD_SCKR__ARM11P_TOP_EVNTBUS_10 0x140 0x584 0x000 0x7 0x0 -#define MX35_PAD_FSR__ESAI_FSR 0x144 0x588 0x000 0x0 0x0 -#define MX35_PAD_FSR__GPIO1_5 0x144 0x588 0x854 0x5 0x1 -#define MX35_PAD_FSR__ARM11P_TOP_EVNTBUS_11 0x144 0x588 0x000 0x7 0x0 -#define MX35_PAD_HCKR__ESAI_HCKR 0x148 0x58c 0x000 0x0 0x0 -#define MX35_PAD_HCKR__AUDMUX_AUD5_RXFS 0x148 0x58c 0x000 0x1 0x0 -#define MX35_PAD_HCKR__CSPI2_SS0 0x148 0x58c 0x7f0 0x2 0x0 -#define MX35_PAD_HCKR__IPU_FLASH_STROBE 0x148 0x58c 0x000 0x3 0x0 -#define MX35_PAD_HCKR__GPIO1_6 0x148 0x58c 0x858 0x5 0x1 -#define MX35_PAD_HCKR__ARM11P_TOP_EVNTBUS_12 0x148 0x58c 0x000 0x7 0x0 -#define MX35_PAD_SCKT__ESAI_SCKT 0x14c 0x590 0x000 0x0 0x0 -#define MX35_PAD_SCKT__GPIO1_7 0x14c 0x590 0x85c 0x5 0x1 -#define MX35_PAD_SCKT__IPU_CSI_D_0 0x14c 0x590 0x930 0x6 0x0 -#define MX35_PAD_SCKT__KPP_ROW_2 0x14c 0x590 0x978 0x7 0x1 -#define MX35_PAD_FST__ESAI_FST 0x150 0x594 0x000 0x0 0x0 -#define MX35_PAD_FST__GPIO1_8 0x150 0x594 0x860 0x5 0x1 -#define MX35_PAD_FST__IPU_CSI_D_1 0x150 0x594 0x934 0x6 0x0 -#define MX35_PAD_FST__KPP_ROW_3 0x150 0x594 0x97c 0x7 0x1 -#define MX35_PAD_HCKT__ESAI_HCKT 0x154 0x598 0x000 0x0 0x0 -#define MX35_PAD_HCKT__AUDMUX_AUD5_RXC 0x154 0x598 0x7a8 0x1 0x0 -#define MX35_PAD_HCKT__GPIO1_9 0x154 0x598 0x864 0x5 0x0 -#define MX35_PAD_HCKT__IPU_CSI_D_2 0x154 0x598 0x938 0x6 0x0 -#define MX35_PAD_HCKT__KPP_COL_3 0x154 0x598 0x95c 0x7 0x1 -#define MX35_PAD_TX5_RX0__ESAI_TX5_RX0 0x158 0x59c 0x000 0x0 0x0 -#define MX35_PAD_TX5_RX0__AUDMUX_AUD4_RXC 0x158 0x59c 0x000 0x1 0x0 -#define MX35_PAD_TX5_RX0__CSPI2_SS2 0x158 0x59c 0x7f8 0x2 0x1 -#define MX35_PAD_TX5_RX0__CAN2_TXCAN 0x158 0x59c 0x000 0x3 0x0 -#define MX35_PAD_TX5_RX0__UART2_DTR 0x158 0x59c 0x000 0x4 0x0 -#define MX35_PAD_TX5_RX0__GPIO1_10 0x158 0x59c 0x830 0x5 0x0 -#define MX35_PAD_TX5_RX0__EMI_M3IF_CHOSEN_MASTER_0 0x158 0x59c 0x000 0x7 0x0 -#define MX35_PAD_TX4_RX1__ESAI_TX4_RX1 0x15c 0x5a0 0x000 0x0 0x0 -#define MX35_PAD_TX4_RX1__AUDMUX_AUD4_RXFS 0x15c 0x5a0 0x000 0x1 0x0 -#define MX35_PAD_TX4_RX1__CSPI2_SS3 0x15c 0x5a0 0x7fc 0x2 0x0 -#define MX35_PAD_TX4_RX1__CAN2_RXCAN 0x15c 0x5a0 0x7cc 0x3 0x0 -#define MX35_PAD_TX4_RX1__UART2_DSR 0x15c 0x5a0 0x000 0x4 0x0 -#define MX35_PAD_TX4_RX1__GPIO1_11 0x15c 0x5a0 0x834 0x5 0x0 -#define MX35_PAD_TX4_RX1__IPU_CSI_D_3 0x15c 0x5a0 0x93c 0x6 0x0 -#define MX35_PAD_TX4_RX1__KPP_ROW_0 0x15c 0x5a0 0x970 0x7 0x1 -#define MX35_PAD_TX3_RX2__ESAI_TX3_RX2 0x160 0x5a4 0x000 0x0 0x0 -#define MX35_PAD_TX3_RX2__I2C3_SCL 0x160 0x5a4 0x91c 0x1 0x0 -#define MX35_PAD_TX3_RX2__EMI_NANDF_CE1 0x160 0x5a4 0x000 0x3 0x0 -#define MX35_PAD_TX3_RX2__GPIO1_12 0x160 0x5a4 0x000 0x5 0x0 -#define MX35_PAD_TX3_RX2__IPU_CSI_D_4 0x160 0x5a4 0x940 0x6 0x0 -#define MX35_PAD_TX3_RX2__KPP_ROW_1 0x160 0x5a4 0x974 0x7 0x1 -#define MX35_PAD_TX2_RX3__ESAI_TX2_RX3 0x164 0x5a8 0x000 0x0 0x0 -#define MX35_PAD_TX2_RX3__I2C3_SDA 0x164 0x5a8 0x920 0x1 0x0 -#define MX35_PAD_TX2_RX3__EMI_NANDF_CE2 0x164 0x5a8 0x000 0x3 0x0 -#define MX35_PAD_TX2_RX3__GPIO1_13 0x164 0x5a8 0x000 0x5 0x0 -#define MX35_PAD_TX2_RX3__IPU_CSI_D_5 0x164 0x5a8 0x944 0x6 0x0 -#define MX35_PAD_TX2_RX3__KPP_COL_0 0x164 0x5a8 0x950 0x7 0x1 -#define MX35_PAD_TX1__ESAI_TX1 0x168 0x5ac 0x000 0x0 0x0 -#define MX35_PAD_TX1__CCM_PMIC_RDY 0x168 0x5ac 0x7d4 0x1 0x1 -#define MX35_PAD_TX1__CSPI1_SS2 0x168 0x5ac 0x7d8 0x2 0x2 -#define MX35_PAD_TX1__EMI_NANDF_CE3 0x168 0x5ac 0x000 0x3 0x0 -#define MX35_PAD_TX1__UART2_RI 0x168 0x5ac 0x000 0x4 0x0 -#define MX35_PAD_TX1__GPIO1_14 0x168 0x5ac 0x000 0x5 0x0 -#define MX35_PAD_TX1__IPU_CSI_D_6 0x168 0x5ac 0x948 0x6 0x0 -#define MX35_PAD_TX1__KPP_COL_1 0x168 0x5ac 0x954 0x7 0x1 -#define MX35_PAD_TX0__ESAI_TX0 0x16c 0x5b0 0x000 0x0 0x0 -#define MX35_PAD_TX0__SPDIF_SPDIF_EXTCLK 0x16c 0x5b0 0x994 0x1 0x1 -#define MX35_PAD_TX0__CSPI1_SS3 0x16c 0x5b0 0x7dc 0x2 0x0 -#define MX35_PAD_TX0__EMI_DTACK_B 0x16c 0x5b0 0x800 0x3 0x1 -#define MX35_PAD_TX0__UART2_DCD 0x16c 0x5b0 0x000 0x4 0x0 -#define MX35_PAD_TX0__GPIO1_15 0x16c 0x5b0 0x000 0x5 0x0 -#define MX35_PAD_TX0__IPU_CSI_D_7 0x16c 0x5b0 0x94c 0x6 0x0 -#define MX35_PAD_TX0__KPP_COL_2 0x16c 0x5b0 0x958 0x7 0x1 -#define MX35_PAD_CSPI1_MOSI__CSPI1_MOSI 0x170 0x5b4 0x000 0x0 0x0 -#define MX35_PAD_CSPI1_MOSI__GPIO1_16 0x170 0x5b4 0x000 0x5 0x0 -#define MX35_PAD_CSPI1_MOSI__ECT_CTI_TRIG_OUT1_2 0x170 0x5b4 0x000 0x7 0x0 -#define MX35_PAD_CSPI1_MISO__CSPI1_MISO 0x174 0x5b8 0x000 0x0 0x0 -#define MX35_PAD_CSPI1_MISO__GPIO1_17 0x174 0x5b8 0x000 0x5 0x0 -#define MX35_PAD_CSPI1_MISO__ECT_CTI_TRIG_OUT1_3 0x174 0x5b8 0x000 0x7 0x0 -#define MX35_PAD_CSPI1_SS0__CSPI1_SS0 0x178 0x5bc 0x000 0x0 0x0 -#define MX35_PAD_CSPI1_SS0__OWIRE_LINE 0x178 0x5bc 0x990 0x1 0x1 -#define MX35_PAD_CSPI1_SS0__CSPI2_SS3 0x178 0x5bc 0x7fc 0x2 0x1 -#define MX35_PAD_CSPI1_SS0__GPIO1_18 0x178 0x5bc 0x000 0x5 0x0 -#define MX35_PAD_CSPI1_SS0__ECT_CTI_TRIG_OUT1_4 0x178 0x5bc 0x000 0x7 0x0 -#define MX35_PAD_CSPI1_SS1__CSPI1_SS1 0x17c 0x5c0 0x000 0x0 0x0 -#define MX35_PAD_CSPI1_SS1__PWM_PWMO 0x17c 0x5c0 0x000 0x1 0x0 -#define MX35_PAD_CSPI1_SS1__CCM_CLK32K 0x17c 0x5c0 0x7d0 0x2 0x1 -#define MX35_PAD_CSPI1_SS1__GPIO1_19 0x17c 0x5c0 0x000 0x5 0x0 -#define MX35_PAD_CSPI1_SS1__IPU_DIAGB_29 0x17c 0x5c0 0x000 0x6 0x0 -#define MX35_PAD_CSPI1_SS1__ECT_CTI_TRIG_OUT1_5 0x17c 0x5c0 0x000 0x7 0x0 -#define MX35_PAD_CSPI1_SCLK__CSPI1_SCLK 0x180 0x5c4 0x000 0x0 0x0 -#define MX35_PAD_CSPI1_SCLK__GPIO3_4 0x180 0x5c4 0x904 0x5 0x0 -#define MX35_PAD_CSPI1_SCLK__IPU_DIAGB_30 0x180 0x5c4 0x000 0x6 0x0 -#define MX35_PAD_CSPI1_SCLK__EMI_M3IF_CHOSEN_MASTER_1 0x180 0x5c4 0x000 0x7 0x0 -#define MX35_PAD_CSPI1_SPI_RDY__CSPI1_RDY 0x184 0x5c8 0x000 0x0 0x0 -#define MX35_PAD_CSPI1_SPI_RDY__GPIO3_5 0x184 0x5c8 0x908 0x5 0x0 -#define MX35_PAD_CSPI1_SPI_RDY__IPU_DIAGB_31 0x184 0x5c8 0x000 0x6 0x0 -#define MX35_PAD_CSPI1_SPI_RDY__EMI_M3IF_CHOSEN_MASTER_2 0x184 0x5c8 0x000 0x7 0x0 -#define MX35_PAD_RXD1__UART1_RXD_MUX 0x188 0x5cc 0x000 0x0 0x0 -#define MX35_PAD_RXD1__CSPI2_MOSI 0x188 0x5cc 0x7ec 0x1 0x1 -#define MX35_PAD_RXD1__KPP_COL_4 0x188 0x5cc 0x960 0x4 0x0 -#define MX35_PAD_RXD1__GPIO3_6 0x188 0x5cc 0x90c 0x5 0x0 -#define MX35_PAD_RXD1__ARM11P_TOP_EVNTBUS_16 0x188 0x5cc 0x000 0x7 0x0 -#define MX35_PAD_TXD1__UART1_TXD_MUX 0x18c 0x5d0 0x000 0x0 0x0 -#define MX35_PAD_TXD1__CSPI2_MISO 0x18c 0x5d0 0x7e8 0x1 0x1 -#define MX35_PAD_TXD1__KPP_COL_5 0x18c 0x5d0 0x964 0x4 0x0 -#define MX35_PAD_TXD1__GPIO3_7 0x18c 0x5d0 0x910 0x5 0x0 -#define MX35_PAD_TXD1__ARM11P_TOP_EVNTBUS_17 0x18c 0x5d0 0x000 0x7 0x0 -#define MX35_PAD_RTS1__UART1_RTS 0x190 0x5d4 0x000 0x0 0x0 -#define MX35_PAD_RTS1__CSPI2_SCLK 0x190 0x5d4 0x7e0 0x1 0x1 -#define MX35_PAD_RTS1__I2C3_SCL 0x190 0x5d4 0x91c 0x2 0x1 -#define MX35_PAD_RTS1__IPU_CSI_D_0 0x190 0x5d4 0x930 0x3 0x1 -#define MX35_PAD_RTS1__KPP_COL_6 0x190 0x5d4 0x968 0x4 0x0 -#define MX35_PAD_RTS1__GPIO3_8 0x190 0x5d4 0x914 0x5 0x0 -#define MX35_PAD_RTS1__EMI_NANDF_CE1 0x190 0x5d4 0x000 0x6 0x0 -#define MX35_PAD_RTS1__ARM11P_TOP_EVNTBUS_18 0x190 0x5d4 0x000 0x7 0x0 -#define MX35_PAD_CTS1__UART1_CTS 0x194 0x5d8 0x000 0x0 0x0 -#define MX35_PAD_CTS1__CSPI2_RDY 0x194 0x5d8 0x7e4 0x1 0x1 -#define MX35_PAD_CTS1__I2C3_SDA 0x194 0x5d8 0x920 0x2 0x1 -#define MX35_PAD_CTS1__IPU_CSI_D_1 0x194 0x5d8 0x934 0x3 0x1 -#define MX35_PAD_CTS1__KPP_COL_7 0x194 0x5d8 0x96c 0x4 0x0 -#define MX35_PAD_CTS1__GPIO3_9 0x194 0x5d8 0x918 0x5 0x0 -#define MX35_PAD_CTS1__EMI_NANDF_CE2 0x194 0x5d8 0x000 0x6 0x0 -#define MX35_PAD_CTS1__ARM11P_TOP_EVNTBUS_19 0x194 0x5d8 0x000 0x7 0x0 -#define MX35_PAD_RXD2__UART2_RXD_MUX 0x198 0x5dc 0x000 0x0 0x0 -#define MX35_PAD_RXD2__KPP_ROW_4 0x198 0x5dc 0x980 0x4 0x0 -#define MX35_PAD_RXD2__GPIO3_10 0x198 0x5dc 0x8ec 0x5 0x0 -#define MX35_PAD_TXD2__UART2_TXD_MUX 0x19c 0x5e0 0x000 0x0 0x0 -#define MX35_PAD_TXD2__SPDIF_SPDIF_EXTCLK 0x19c 0x5e0 0x994 0x1 0x2 -#define MX35_PAD_TXD2__KPP_ROW_5 0x19c 0x5e0 0x984 0x4 0x0 -#define MX35_PAD_TXD2__GPIO3_11 0x19c 0x5e0 0x8f0 0x5 0x0 -#define MX35_PAD_RTS2__UART2_RTS 0x1a0 0x5e4 0x000 0x0 0x0 -#define MX35_PAD_RTS2__SPDIF_SPDIF_IN1 0x1a0 0x5e4 0x998 0x1 0x1 -#define MX35_PAD_RTS2__CAN2_RXCAN 0x1a0 0x5e4 0x7cc 0x2 0x1 -#define MX35_PAD_RTS2__IPU_CSI_D_2 0x1a0 0x5e4 0x938 0x3 0x1 -#define MX35_PAD_RTS2__KPP_ROW_6 0x1a0 0x5e4 0x988 0x4 0x0 -#define MX35_PAD_RTS2__GPIO3_12 0x1a0 0x5e4 0x8f4 0x5 0x0 -#define MX35_PAD_RTS2__AUDMUX_AUD5_RXC 0x1a0 0x5e4 0x000 0x6 0x0 -#define MX35_PAD_RTS2__UART3_RXD_MUX 0x1a0 0x5e4 0x9a0 0x7 0x0 -#define MX35_PAD_CTS2__UART2_CTS 0x1a4 0x5e8 0x000 0x0 0x0 -#define MX35_PAD_CTS2__SPDIF_SPDIF_OUT1 0x1a4 0x5e8 0x000 0x1 0x0 -#define MX35_PAD_CTS2__CAN2_TXCAN 0x1a4 0x5e8 0x000 0x2 0x0 -#define MX35_PAD_CTS2__IPU_CSI_D_3 0x1a4 0x5e8 0x93c 0x3 0x1 -#define MX35_PAD_CTS2__KPP_ROW_7 0x1a4 0x5e8 0x98c 0x4 0x0 -#define MX35_PAD_CTS2__GPIO3_13 0x1a4 0x5e8 0x8f8 0x5 0x0 -#define MX35_PAD_CTS2__AUDMUX_AUD5_RXFS 0x1a4 0x5e8 0x000 0x6 0x0 -#define MX35_PAD_CTS2__UART3_TXD_MUX 0x1a4 0x5e8 0x000 0x7 0x0 -#define MX35_PAD_RTCK__ARM11P_TOP_RTCK 0x000 0x5ec 0x000 0x0 0x0 -#define MX35_PAD_TCK__SJC_TCK 0x000 0x5f0 0x000 0x0 0x0 -#define MX35_PAD_TMS__SJC_TMS 0x000 0x5f4 0x000 0x0 0x0 -#define MX35_PAD_TDI__SJC_TDI 0x000 0x5f8 0x000 0x0 0x0 -#define MX35_PAD_TDO__SJC_TDO 0x000 0x5fc 0x000 0x0 0x0 -#define MX35_PAD_TRSTB__SJC_TRSTB 0x000 0x600 0x000 0x0 0x0 -#define MX35_PAD_DE_B__SJC_DE_B 0x000 0x604 0x000 0x0 0x0 -#define MX35_PAD_SJC_MOD__SJC_MOD 0x000 0x608 0x000 0x0 0x0 -#define MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR 0x1a8 0x60c 0x000 0x0 0x0 -#define MX35_PAD_USBOTG_PWR__USB_TOP_USBH2_PWR 0x1a8 0x60c 0x000 0x1 0x0 -#define MX35_PAD_USBOTG_PWR__GPIO3_14 0x1a8 0x60c 0x8fc 0x5 0x0 -#define MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC 0x1ac 0x610 0x000 0x0 0x0 -#define MX35_PAD_USBOTG_OC__USB_TOP_USBH2_OC 0x1ac 0x610 0x9f4 0x1 0x1 -#define MX35_PAD_USBOTG_OC__GPIO3_15 0x1ac 0x610 0x900 0x5 0x0 -#define MX35_PAD_LD0__IPU_DISPB_DAT_0 0x1b0 0x614 0x000 0x0 0x0 -#define MX35_PAD_LD0__GPIO2_0 0x1b0 0x614 0x868 0x5 0x1 -#define MX35_PAD_LD0__SDMA_SDMA_DEBUG_PC_0 0x1b0 0x614 0x000 0x6 0x0 -#define MX35_PAD_LD1__IPU_DISPB_DAT_1 0x1b4 0x618 0x000 0x0 0x0 -#define MX35_PAD_LD1__GPIO2_1 0x1b4 0x618 0x894 0x5 0x0 -#define MX35_PAD_LD1__SDMA_SDMA_DEBUG_PC_1 0x1b4 0x618 0x000 0x6 0x0 -#define MX35_PAD_LD2__IPU_DISPB_DAT_2 0x1b8 0x61c 0x000 0x0 0x0 -#define MX35_PAD_LD2__GPIO2_2 0x1b8 0x61c 0x8c0 0x5 0x0 -#define MX35_PAD_LD2__SDMA_SDMA_DEBUG_PC_2 0x1b8 0x61c 0x000 0x6 0x0 -#define MX35_PAD_LD3__IPU_DISPB_DAT_3 0x1bc 0x620 0x000 0x0 0x0 -#define MX35_PAD_LD3__GPIO2_3 0x1bc 0x620 0x8cc 0x5 0x0 -#define MX35_PAD_LD3__SDMA_SDMA_DEBUG_PC_3 0x1bc 0x620 0x000 0x6 0x0 -#define MX35_PAD_LD4__IPU_DISPB_DAT_4 0x1c0 0x624 0x000 0x0 0x0 -#define MX35_PAD_LD4__GPIO2_4 0x1c0 0x624 0x8d0 0x5 0x0 -#define MX35_PAD_LD4__SDMA_SDMA_DEBUG_PC_4 0x1c0 0x624 0x000 0x6 0x0 -#define MX35_PAD_LD5__IPU_DISPB_DAT_5 0x1c4 0x628 0x000 0x0 0x0 -#define MX35_PAD_LD5__GPIO2_5 0x1c4 0x628 0x8d4 0x5 0x0 -#define MX35_PAD_LD5__SDMA_SDMA_DEBUG_PC_5 0x1c4 0x628 0x000 0x6 0x0 -#define MX35_PAD_LD6__IPU_DISPB_DAT_6 0x1c8 0x62c 0x000 0x0 0x0 -#define MX35_PAD_LD6__GPIO2_6 0x1c8 0x62c 0x8d8 0x5 0x0 -#define MX35_PAD_LD6__SDMA_SDMA_DEBUG_PC_6 0x1c8 0x62c 0x000 0x6 0x0 -#define MX35_PAD_LD7__IPU_DISPB_DAT_7 0x1cc 0x630 0x000 0x0 0x0 -#define MX35_PAD_LD7__GPIO2_7 0x1cc 0x630 0x8dc 0x5 0x0 -#define MX35_PAD_LD7__SDMA_SDMA_DEBUG_PC_7 0x1cc 0x630 0x000 0x6 0x0 -#define MX35_PAD_LD8__IPU_DISPB_DAT_8 0x1d0 0x634 0x000 0x0 0x0 -#define MX35_PAD_LD8__GPIO2_8 0x1d0 0x634 0x8e0 0x5 0x0 -#define MX35_PAD_LD8__SDMA_SDMA_DEBUG_PC_8 0x1d0 0x634 0x000 0x6 0x0 -#define MX35_PAD_LD9__IPU_DISPB_DAT_9 0x1d4 0x638 0x000 0x0 0x0 -#define MX35_PAD_LD9__GPIO2_9 0x1d4 0x638 0x8e4 0x5 0x0 -#define MX35_PAD_LD9__SDMA_SDMA_DEBUG_PC_9 0x1d4 0x638 0x000 0x6 0x0 -#define MX35_PAD_LD10__IPU_DISPB_DAT_10 0x1d8 0x63c 0x000 0x0 0x0 -#define MX35_PAD_LD10__GPIO2_10 0x1d8 0x63c 0x86c 0x5 0x0 -#define MX35_PAD_LD10__SDMA_SDMA_DEBUG_PC_10 0x1d8 0x63c 0x000 0x6 0x0 -#define MX35_PAD_LD11__IPU_DISPB_DAT_11 0x1dc 0x640 0x000 0x0 0x0 -#define MX35_PAD_LD11__GPIO2_11 0x1dc 0x640 0x870 0x5 0x0 -#define MX35_PAD_LD11__SDMA_SDMA_DEBUG_PC_11 0x1dc 0x640 0x000 0x6 0x0 -#define MX35_PAD_LD11__ARM11P_TOP_TRACE_4 0x1dc 0x640 0x000 0x7 0x0 -#define MX35_PAD_LD12__IPU_DISPB_DAT_12 0x1e0 0x644 0x000 0x0 0x0 -#define MX35_PAD_LD12__GPIO2_12 0x1e0 0x644 0x874 0x5 0x0 -#define MX35_PAD_LD12__SDMA_SDMA_DEBUG_PC_12 0x1e0 0x644 0x000 0x6 0x0 -#define MX35_PAD_LD12__ARM11P_TOP_TRACE_5 0x1e0 0x644 0x000 0x7 0x0 -#define MX35_PAD_LD13__IPU_DISPB_DAT_13 0x1e4 0x648 0x000 0x0 0x0 -#define MX35_PAD_LD13__GPIO2_13 0x1e4 0x648 0x878 0x5 0x0 -#define MX35_PAD_LD13__SDMA_SDMA_DEBUG_PC_13 0x1e4 0x648 0x000 0x6 0x0 -#define MX35_PAD_LD13__ARM11P_TOP_TRACE_6 0x1e4 0x648 0x000 0x7 0x0 -#define MX35_PAD_LD14__IPU_DISPB_DAT_14 0x1e8 0x64c 0x000 0x0 0x0 -#define MX35_PAD_LD14__GPIO2_14 0x1e8 0x64c 0x87c 0x5 0x0 -#define MX35_PAD_LD14__SDMA_SDMA_DEBUG_EVENT_CHANNEL_0 0x1e8 0x64c 0x000 0x6 0x0 -#define MX35_PAD_LD14__ARM11P_TOP_TRACE_7 0x1e8 0x64c 0x000 0x7 0x0 -#define MX35_PAD_LD15__IPU_DISPB_DAT_15 0x1ec 0x650 0x000 0x0 0x0 -#define MX35_PAD_LD15__GPIO2_15 0x1ec 0x650 0x880 0x5 0x0 -#define MX35_PAD_LD15__SDMA_SDMA_DEBUG_EVENT_CHANNEL_1 0x1ec 0x650 0x000 0x6 0x0 -#define MX35_PAD_LD15__ARM11P_TOP_TRACE_8 0x1ec 0x650 0x000 0x7 0x0 -#define MX35_PAD_LD16__IPU_DISPB_DAT_16 0x1f0 0x654 0x000 0x0 0x0 -#define MX35_PAD_LD16__IPU_DISPB_D12_VSYNC 0x1f0 0x654 0x928 0x2 0x0 -#define MX35_PAD_LD16__GPIO2_16 0x1f0 0x654 0x884 0x5 0x0 -#define MX35_PAD_LD16__SDMA_SDMA_DEBUG_EVENT_CHANNEL_2 0x1f0 0x654 0x000 0x6 0x0 -#define MX35_PAD_LD16__ARM11P_TOP_TRACE_9 0x1f0 0x654 0x000 0x7 0x0 -#define MX35_PAD_LD17__IPU_DISPB_DAT_17 0x1f4 0x658 0x000 0x0 0x0 -#define MX35_PAD_LD17__IPU_DISPB_CS2 0x1f4 0x658 0x000 0x2 0x0 -#define MX35_PAD_LD17__GPIO2_17 0x1f4 0x658 0x888 0x5 0x0 -#define MX35_PAD_LD17__SDMA_SDMA_DEBUG_EVENT_CHANNEL_3 0x1f4 0x658 0x000 0x6 0x0 -#define MX35_PAD_LD17__ARM11P_TOP_TRACE_10 0x1f4 0x658 0x000 0x7 0x0 -#define MX35_PAD_LD18__IPU_DISPB_DAT_18 0x1f8 0x65c 0x000 0x0 0x0 -#define MX35_PAD_LD18__IPU_DISPB_D0_VSYNC 0x1f8 0x65c 0x924 0x1 0x1 -#define MX35_PAD_LD18__IPU_DISPB_D12_VSYNC 0x1f8 0x65c 0x928 0x2 0x1 -#define MX35_PAD_LD18__ESDHC3_CMD 0x1f8 0x65c 0x818 0x3 0x0 -#define MX35_PAD_LD18__USB_TOP_USBOTG_DATA_3 0x1f8 0x65c 0x9b0 0x4 0x0 -#define MX35_PAD_LD18__GPIO3_24 0x1f8 0x65c 0x000 0x5 0x0 -#define MX35_PAD_LD18__SDMA_SDMA_DEBUG_EVENT_CHANNEL_4 0x1f8 0x65c 0x000 0x6 0x0 -#define MX35_PAD_LD18__ARM11P_TOP_TRACE_11 0x1f8 0x65c 0x000 0x7 0x0 -#define MX35_PAD_LD19__IPU_DISPB_DAT_19 0x1fc 0x660 0x000 0x0 0x0 -#define MX35_PAD_LD19__IPU_DISPB_BCLK 0x1fc 0x660 0x000 0x1 0x0 -#define MX35_PAD_LD19__IPU_DISPB_CS1 0x1fc 0x660 0x000 0x2 0x0 -#define MX35_PAD_LD19__ESDHC3_CLK 0x1fc 0x660 0x814 0x3 0x0 -#define MX35_PAD_LD19__USB_TOP_USBOTG_DIR 0x1fc 0x660 0x9c4 0x4 0x0 -#define MX35_PAD_LD19__GPIO3_25 0x1fc 0x660 0x000 0x5 0x0 -#define MX35_PAD_LD19__SDMA_SDMA_DEBUG_EVENT_CHANNEL_5 0x1fc 0x660 0x000 0x6 0x0 -#define MX35_PAD_LD19__ARM11P_TOP_TRACE_12 0x1fc 0x660 0x000 0x7 0x0 -#define MX35_PAD_LD20__IPU_DISPB_DAT_20 0x200 0x664 0x000 0x0 0x0 -#define MX35_PAD_LD20__IPU_DISPB_CS0 0x200 0x664 0x000 0x1 0x0 -#define MX35_PAD_LD20__IPU_DISPB_SD_CLK 0x200 0x664 0x000 0x2 0x0 -#define MX35_PAD_LD20__ESDHC3_DAT0 0x200 0x664 0x81c 0x3 0x0 -#define MX35_PAD_LD20__GPIO3_26 0x200 0x664 0x000 0x5 0x0 -#define MX35_PAD_LD20__SDMA_SDMA_DEBUG_CORE_STATUS_3 0x200 0x664 0x000 0x6 0x0 -#define MX35_PAD_LD20__ARM11P_TOP_TRACE_13 0x200 0x664 0x000 0x7 0x0 -#define MX35_PAD_LD21__IPU_DISPB_DAT_21 0x204 0x668 0x000 0x0 0x0 -#define MX35_PAD_LD21__IPU_DISPB_PAR_RS 0x204 0x668 0x000 0x1 0x0 -#define MX35_PAD_LD21__IPU_DISPB_SER_RS 0x204 0x668 0x000 0x2 0x0 -#define MX35_PAD_LD21__ESDHC3_DAT1 0x204 0x668 0x820 0x3 0x0 -#define MX35_PAD_LD21__USB_TOP_USBOTG_STP 0x204 0x668 0x000 0x4 0x0 -#define MX35_PAD_LD21__GPIO3_27 0x204 0x668 0x000 0x5 0x0 -#define MX35_PAD_LD21__SDMA_DEBUG_EVENT_CHANNEL_SEL 0x204 0x668 0x000 0x6 0x0 -#define MX35_PAD_LD21__ARM11P_TOP_TRACE_14 0x204 0x668 0x000 0x7 0x0 -#define MX35_PAD_LD22__IPU_DISPB_DAT_22 0x208 0x66c 0x000 0x0 0x0 -#define MX35_PAD_LD22__IPU_DISPB_WR 0x208 0x66c 0x000 0x1 0x0 -#define MX35_PAD_LD22__IPU_DISPB_SD_D_I 0x208 0x66c 0x92c 0x2 0x0 -#define MX35_PAD_LD22__ESDHC3_DAT2 0x208 0x66c 0x824 0x3 0x0 -#define MX35_PAD_LD22__USB_TOP_USBOTG_NXT 0x208 0x66c 0x9c8 0x4 0x0 -#define MX35_PAD_LD22__GPIO3_28 0x208 0x66c 0x000 0x5 0x0 -#define MX35_PAD_LD22__SDMA_DEBUG_BUS_ERROR 0x208 0x66c 0x000 0x6 0x0 -#define MX35_PAD_LD22__ARM11P_TOP_TRCTL 0x208 0x66c 0x000 0x7 0x0 -#define MX35_PAD_LD23__IPU_DISPB_DAT_23 0x20c 0x670 0x000 0x0 0x0 -#define MX35_PAD_LD23__IPU_DISPB_RD 0x20c 0x670 0x000 0x1 0x0 -#define MX35_PAD_LD23__IPU_DISPB_SD_D_IO 0x20c 0x670 0x92c 0x2 0x1 -#define MX35_PAD_LD23__ESDHC3_DAT3 0x20c 0x670 0x828 0x3 0x0 -#define MX35_PAD_LD23__USB_TOP_USBOTG_DATA_7 0x20c 0x670 0x9c0 0x4 0x0 -#define MX35_PAD_LD23__GPIO3_29 0x20c 0x670 0x000 0x5 0x0 -#define MX35_PAD_LD23__SDMA_DEBUG_MATCHED_DMBUS 0x20c 0x670 0x000 0x6 0x0 -#define MX35_PAD_LD23__ARM11P_TOP_TRCLK 0x20c 0x670 0x000 0x7 0x0 -#define MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC 0x210 0x674 0x000 0x0 0x0 -#define MX35_PAD_D3_HSYNC__IPU_DISPB_SD_D_IO 0x210 0x674 0x92c 0x2 0x2 -#define MX35_PAD_D3_HSYNC__GPIO3_30 0x210 0x674 0x000 0x5 0x0 -#define MX35_PAD_D3_HSYNC__SDMA_DEBUG_RTBUFFER_WRITE 0x210 0x674 0x000 0x6 0x0 -#define MX35_PAD_D3_HSYNC__ARM11P_TOP_TRACE_15 0x210 0x674 0x000 0x7 0x0 -#define MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK 0x214 0x678 0x000 0x0 0x0 -#define MX35_PAD_D3_FPSHIFT__IPU_DISPB_SD_CLK 0x214 0x678 0x000 0x2 0x0 -#define MX35_PAD_D3_FPSHIFT__GPIO3_31 0x214 0x678 0x000 0x5 0x0 -#define MX35_PAD_D3_FPSHIFT__SDMA_SDMA_DEBUG_CORE_STATUS_0 0x214 0x678 0x000 0x6 0x0 -#define MX35_PAD_D3_FPSHIFT__ARM11P_TOP_TRACE_16 0x214 0x678 0x000 0x7 0x0 -#define MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY 0x218 0x67c 0x000 0x0 0x0 -#define MX35_PAD_D3_DRDY__IPU_DISPB_SD_D_O 0x218 0x67c 0x000 0x2 0x0 -#define MX35_PAD_D3_DRDY__GPIO1_0 0x218 0x67c 0x82c 0x5 0x2 -#define MX35_PAD_D3_DRDY__SDMA_SDMA_DEBUG_CORE_STATUS_1 0x218 0x67c 0x000 0x6 0x0 -#define MX35_PAD_D3_DRDY__ARM11P_TOP_TRACE_17 0x218 0x67c 0x000 0x7 0x0 -#define MX35_PAD_CONTRAST__IPU_DISPB_CONTR 0x21c 0x680 0x000 0x0 0x0 -#define MX35_PAD_CONTRAST__GPIO1_1 0x21c 0x680 0x838 0x5 0x2 -#define MX35_PAD_CONTRAST__SDMA_SDMA_DEBUG_CORE_STATUS_2 0x21c 0x680 0x000 0x6 0x0 -#define MX35_PAD_CONTRAST__ARM11P_TOP_TRACE_18 0x21c 0x680 0x000 0x7 0x0 -#define MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC 0x220 0x684 0x000 0x0 0x0 -#define MX35_PAD_D3_VSYNC__IPU_DISPB_CS1 0x220 0x684 0x000 0x2 0x0 -#define MX35_PAD_D3_VSYNC__GPIO1_2 0x220 0x684 0x848 0x5 0x1 -#define MX35_PAD_D3_VSYNC__SDMA_DEBUG_YIELD 0x220 0x684 0x000 0x6 0x0 -#define MX35_PAD_D3_VSYNC__ARM11P_TOP_TRACE_19 0x220 0x684 0x000 0x7 0x0 -#define MX35_PAD_D3_REV__IPU_DISPB_D3_REV 0x224 0x688 0x000 0x0 0x0 -#define MX35_PAD_D3_REV__IPU_DISPB_SER_RS 0x224 0x688 0x000 0x2 0x0 -#define MX35_PAD_D3_REV__GPIO1_3 0x224 0x688 0x84c 0x5 0x1 -#define MX35_PAD_D3_REV__SDMA_DEBUG_BUS_RWB 0x224 0x688 0x000 0x6 0x0 -#define MX35_PAD_D3_REV__ARM11P_TOP_TRACE_20 0x224 0x688 0x000 0x7 0x0 -#define MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS 0x228 0x68c 0x000 0x0 0x0 -#define MX35_PAD_D3_CLS__IPU_DISPB_CS2 0x228 0x68c 0x000 0x2 0x0 -#define MX35_PAD_D3_CLS__GPIO1_4 0x228 0x68c 0x850 0x5 0x2 -#define MX35_PAD_D3_CLS__SDMA_DEBUG_BUS_DEVICE_0 0x228 0x68c 0x000 0x6 0x0 -#define MX35_PAD_D3_CLS__ARM11P_TOP_TRACE_21 0x228 0x68c 0x000 0x7 0x0 -#define MX35_PAD_D3_SPL__IPU_DISPB_D3_SPL 0x22c 0x690 0x000 0x0 0x0 -#define MX35_PAD_D3_SPL__IPU_DISPB_D12_VSYNC 0x22c 0x690 0x928 0x2 0x2 -#define MX35_PAD_D3_SPL__GPIO1_5 0x22c 0x690 0x854 0x5 0x2 -#define MX35_PAD_D3_SPL__SDMA_DEBUG_BUS_DEVICE_1 0x22c 0x690 0x000 0x6 0x0 -#define MX35_PAD_D3_SPL__ARM11P_TOP_TRACE_22 0x22c 0x690 0x000 0x7 0x0 -#define MX35_PAD_SD1_CMD__ESDHC1_CMD 0x230 0x694 0x000 0x0 0x0 -#define MX35_PAD_SD1_CMD__MSHC_SCLK 0x230 0x694 0x000 0x1 0x0 -#define MX35_PAD_SD1_CMD__IPU_DISPB_D0_VSYNC 0x230 0x694 0x924 0x3 0x2 -#define MX35_PAD_SD1_CMD__USB_TOP_USBOTG_DATA_4 0x230 0x694 0x9b4 0x4 0x0 -#define MX35_PAD_SD1_CMD__GPIO1_6 0x230 0x694 0x858 0x5 0x2 -#define MX35_PAD_SD1_CMD__ARM11P_TOP_TRCTL 0x230 0x694 0x000 0x7 0x0 -#define MX35_PAD_SD1_CLK__ESDHC1_CLK 0x234 0x698 0x000 0x0 0x0 -#define MX35_PAD_SD1_CLK__MSHC_BS 0x234 0x698 0x000 0x1 0x0 -#define MX35_PAD_SD1_CLK__IPU_DISPB_BCLK 0x234 0x698 0x000 0x3 0x0 -#define MX35_PAD_SD1_CLK__USB_TOP_USBOTG_DATA_5 0x234 0x698 0x9b8 0x4 0x0 -#define MX35_PAD_SD1_CLK__GPIO1_7 0x234 0x698 0x85c 0x5 0x2 -#define MX35_PAD_SD1_CLK__ARM11P_TOP_TRCLK 0x234 0x698 0x000 0x7 0x0 -#define MX35_PAD_SD1_DATA0__ESDHC1_DAT0 0x238 0x69c 0x000 0x0 0x0 -#define MX35_PAD_SD1_DATA0__MSHC_DATA_0 0x238 0x69c 0x000 0x1 0x0 -#define MX35_PAD_SD1_DATA0__IPU_DISPB_CS0 0x238 0x69c 0x000 0x3 0x0 -#define MX35_PAD_SD1_DATA0__USB_TOP_USBOTG_DATA_6 0x238 0x69c 0x9bc 0x4 0x0 -#define MX35_PAD_SD1_DATA0__GPIO1_8 0x238 0x69c 0x860 0x5 0x2 -#define MX35_PAD_SD1_DATA0__ARM11P_TOP_TRACE_23 0x238 0x69c 0x000 0x7 0x0 -#define MX35_PAD_SD1_DATA1__ESDHC1_DAT1 0x23c 0x6a0 0x000 0x0 0x0 -#define MX35_PAD_SD1_DATA1__MSHC_DATA_1 0x23c 0x6a0 0x000 0x1 0x0 -#define MX35_PAD_SD1_DATA1__IPU_DISPB_PAR_RS 0x23c 0x6a0 0x000 0x3 0x0 -#define MX35_PAD_SD1_DATA1__USB_TOP_USBOTG_DATA_0 0x23c 0x6a0 0x9a4 0x4 0x0 -#define MX35_PAD_SD1_DATA1__GPIO1_9 0x23c 0x6a0 0x864 0x5 0x1 -#define MX35_PAD_SD1_DATA1__ARM11P_TOP_TRACE_24 0x23c 0x6a0 0x000 0x7 0x0 -#define MX35_PAD_SD1_DATA2__ESDHC1_DAT2 0x240 0x6a4 0x000 0x0 0x0 -#define MX35_PAD_SD1_DATA2__MSHC_DATA_2 0x240 0x6a4 0x000 0x1 0x0 -#define MX35_PAD_SD1_DATA2__IPU_DISPB_WR 0x240 0x6a4 0x000 0x3 0x0 -#define MX35_PAD_SD1_DATA2__USB_TOP_USBOTG_DATA_1 0x240 0x6a4 0x9a8 0x4 0x0 -#define MX35_PAD_SD1_DATA2__GPIO1_10 0x240 0x6a4 0x830 0x5 0x1 -#define MX35_PAD_SD1_DATA2__ARM11P_TOP_TRACE_25 0x240 0x6a4 0x000 0x7 0x0 -#define MX35_PAD_SD1_DATA3__ESDHC1_DAT3 0x244 0x6a8 0x000 0x0 0x0 -#define MX35_PAD_SD1_DATA3__MSHC_DATA_3 0x244 0x6a8 0x000 0x1 0x0 -#define MX35_PAD_SD1_DATA3__IPU_DISPB_RD 0x244 0x6a8 0x000 0x3 0x0 -#define MX35_PAD_SD1_DATA3__USB_TOP_USBOTG_DATA_2 0x244 0x6a8 0x9ac 0x4 0x0 -#define MX35_PAD_SD1_DATA3__GPIO1_11 0x244 0x6a8 0x834 0x5 0x1 -#define MX35_PAD_SD1_DATA3__ARM11P_TOP_TRACE_26 0x244 0x6a8 0x000 0x7 0x0 -#define MX35_PAD_SD2_CMD__ESDHC2_CMD 0x248 0x6ac 0x000 0x0 0x0 -#define MX35_PAD_SD2_CMD__I2C3_SCL 0x248 0x6ac 0x91c 0x1 0x2 -#define MX35_PAD_SD2_CMD__ESDHC1_DAT4 0x248 0x6ac 0x804 0x2 0x0 -#define MX35_PAD_SD2_CMD__IPU_CSI_D_2 0x248 0x6ac 0x938 0x3 0x2 -#define MX35_PAD_SD2_CMD__USB_TOP_USBH2_DATA_4 0x248 0x6ac 0x9dc 0x4 0x0 -#define MX35_PAD_SD2_CMD__GPIO2_0 0x248 0x6ac 0x868 0x5 0x2 -#define MX35_PAD_SD2_CMD__SPDIF_SPDIF_OUT1 0x248 0x6ac 0x000 0x6 0x0 -#define MX35_PAD_SD2_CMD__IPU_DISPB_D12_VSYNC 0x248 0x6ac 0x928 0x7 0x3 -#define MX35_PAD_SD2_CLK__ESDHC2_CLK 0x24c 0x6b0 0x000 0x0 0x0 -#define MX35_PAD_SD2_CLK__I2C3_SDA 0x24c 0x6b0 0x920 0x1 0x2 -#define MX35_PAD_SD2_CLK__ESDHC1_DAT5 0x24c 0x6b0 0x808 0x2 0x0 -#define MX35_PAD_SD2_CLK__IPU_CSI_D_3 0x24c 0x6b0 0x93c 0x3 0x2 -#define MX35_PAD_SD2_CLK__USB_TOP_USBH2_DATA_5 0x24c 0x6b0 0x9e0 0x4 0x0 -#define MX35_PAD_SD2_CLK__GPIO2_1 0x24c 0x6b0 0x894 0x5 0x1 -#define MX35_PAD_SD2_CLK__SPDIF_SPDIF_IN1 0x24c 0x6b0 0x998 0x6 0x2 -#define MX35_PAD_SD2_CLK__IPU_DISPB_CS2 0x24c 0x6b0 0x000 0x7 0x0 -#define MX35_PAD_SD2_DATA0__ESDHC2_DAT0 0x250 0x6b4 0x000 0x0 0x0 -#define MX35_PAD_SD2_DATA0__UART3_RXD_MUX 0x250 0x6b4 0x9a0 0x1 0x1 -#define MX35_PAD_SD2_DATA0__ESDHC1_DAT6 0x250 0x6b4 0x80c 0x2 0x0 -#define MX35_PAD_SD2_DATA0__IPU_CSI_D_4 0x250 0x6b4 0x940 0x3 0x1 -#define MX35_PAD_SD2_DATA0__USB_TOP_USBH2_DATA_6 0x250 0x6b4 0x9e4 0x4 0x0 -#define MX35_PAD_SD2_DATA0__GPIO2_2 0x250 0x6b4 0x8c0 0x5 0x1 -#define MX35_PAD_SD2_DATA0__SPDIF_SPDIF_EXTCLK 0x250 0x6b4 0x994 0x6 0x3 -#define MX35_PAD_SD2_DATA1__ESDHC2_DAT1 0x254 0x6b8 0x000 0x0 0x0 -#define MX35_PAD_SD2_DATA1__UART3_TXD_MUX 0x254 0x6b8 0x000 0x1 0x0 -#define MX35_PAD_SD2_DATA1__ESDHC1_DAT7 0x254 0x6b8 0x810 0x2 0x0 -#define MX35_PAD_SD2_DATA1__IPU_CSI_D_5 0x254 0x6b8 0x944 0x3 0x1 -#define MX35_PAD_SD2_DATA1__USB_TOP_USBH2_DATA_0 0x254 0x6b8 0x9cc 0x4 0x0 -#define MX35_PAD_SD2_DATA1__GPIO2_3 0x254 0x6b8 0x8cc 0x5 0x1 -#define MX35_PAD_SD2_DATA2__ESDHC2_DAT2 0x258 0x6bc 0x000 0x0 0x0 -#define MX35_PAD_SD2_DATA2__UART3_RTS 0x258 0x6bc 0x99c 0x1 0x0 -#define MX35_PAD_SD2_DATA2__CAN1_RXCAN 0x258 0x6bc 0x7c8 0x2 0x1 -#define MX35_PAD_SD2_DATA2__IPU_CSI_D_6 0x258 0x6bc 0x948 0x3 0x1 -#define MX35_PAD_SD2_DATA2__USB_TOP_USBH2_DATA_1 0x258 0x6bc 0x9d0 0x4 0x0 -#define MX35_PAD_SD2_DATA2__GPIO2_4 0x258 0x6bc 0x8d0 0x5 0x1 -#define MX35_PAD_SD2_DATA3__ESDHC2_DAT3 0x25c 0x6c0 0x000 0x0 0x0 -#define MX35_PAD_SD2_DATA3__UART3_CTS 0x25c 0x6c0 0x000 0x1 0x0 -#define MX35_PAD_SD2_DATA3__CAN1_TXCAN 0x25c 0x6c0 0x000 0x2 0x0 -#define MX35_PAD_SD2_DATA3__IPU_CSI_D_7 0x25c 0x6c0 0x94c 0x3 0x1 -#define MX35_PAD_SD2_DATA3__USB_TOP_USBH2_DATA_2 0x25c 0x6c0 0x9d4 0x4 0x0 -#define MX35_PAD_SD2_DATA3__GPIO2_5 0x25c 0x6c0 0x8d4 0x5 0x1 -#define MX35_PAD_ATA_CS0__ATA_CS0 0x260 0x6c4 0x000 0x0 0x0 -#define MX35_PAD_ATA_CS0__CSPI1_SS3 0x260 0x6c4 0x7dc 0x1 0x1 -#define MX35_PAD_ATA_CS0__IPU_DISPB_CS1 0x260 0x6c4 0x000 0x3 0x0 -#define MX35_PAD_ATA_CS0__GPIO2_6 0x260 0x6c4 0x8d8 0x5 0x1 -#define MX35_PAD_ATA_CS0__IPU_DIAGB_0 0x260 0x6c4 0x000 0x6 0x0 -#define MX35_PAD_ATA_CS0__ARM11P_TOP_MAX1_HMASTER_0 0x260 0x6c4 0x000 0x7 0x0 -#define MX35_PAD_ATA_CS1__ATA_CS1 0x264 0x6c8 0x000 0x0 0x0 -#define MX35_PAD_ATA_CS1__IPU_DISPB_CS2 0x264 0x6c8 0x000 0x3 0x0 -#define MX35_PAD_ATA_CS1__CSPI2_SS0 0x264 0x6c8 0x7f0 0x4 0x1 -#define MX35_PAD_ATA_CS1__GPIO2_7 0x264 0x6c8 0x8dc 0x5 0x1 -#define MX35_PAD_ATA_CS1__IPU_DIAGB_1 0x264 0x6c8 0x000 0x6 0x0 -#define MX35_PAD_ATA_CS1__ARM11P_TOP_MAX1_HMASTER_1 0x264 0x6c8 0x000 0x7 0x0 -#define MX35_PAD_ATA_DIOR__ATA_DIOR 0x268 0x6cc 0x000 0x0 0x0 -#define MX35_PAD_ATA_DIOR__ESDHC3_DAT0 0x268 0x6cc 0x81c 0x1 0x1 -#define MX35_PAD_ATA_DIOR__USB_TOP_USBOTG_DIR 0x268 0x6cc 0x9c4 0x2 0x1 -#define MX35_PAD_ATA_DIOR__IPU_DISPB_BE0 0x268 0x6cc 0x000 0x3 0x0 -#define MX35_PAD_ATA_DIOR__CSPI2_SS1 0x268 0x6cc 0x7f4 0x4 0x1 -#define MX35_PAD_ATA_DIOR__GPIO2_8 0x268 0x6cc 0x8e0 0x5 0x1 -#define MX35_PAD_ATA_DIOR__IPU_DIAGB_2 0x268 0x6cc 0x000 0x6 0x0 -#define MX35_PAD_ATA_DIOR__ARM11P_TOP_MAX1_HMASTER_2 0x268 0x6cc 0x000 0x7 0x0 -#define MX35_PAD_ATA_DIOW__ATA_DIOW 0x26c 0x6d0 0x000 0x0 0x0 -#define MX35_PAD_ATA_DIOW__ESDHC3_DAT1 0x26c 0x6d0 0x820 0x1 0x1 -#define MX35_PAD_ATA_DIOW__USB_TOP_USBOTG_STP 0x26c 0x6d0 0x000 0x2 0x0 -#define MX35_PAD_ATA_DIOW__IPU_DISPB_BE1 0x26c 0x6d0 0x000 0x3 0x0 -#define MX35_PAD_ATA_DIOW__CSPI2_MOSI 0x26c 0x6d0 0x7ec 0x4 0x2 -#define MX35_PAD_ATA_DIOW__GPIO2_9 0x26c 0x6d0 0x8e4 0x5 0x1 -#define MX35_PAD_ATA_DIOW__IPU_DIAGB_3 0x26c 0x6d0 0x000 0x6 0x0 -#define MX35_PAD_ATA_DIOW__ARM11P_TOP_MAX1_HMASTER_3 0x26c 0x6d0 0x000 0x7 0x0 -#define MX35_PAD_ATA_DMACK__ATA_DMACK 0x270 0x6d4 0x000 0x0 0x0 -#define MX35_PAD_ATA_DMACK__ESDHC3_DAT2 0x270 0x6d4 0x824 0x1 0x1 -#define MX35_PAD_ATA_DMACK__USB_TOP_USBOTG_NXT 0x270 0x6d4 0x9c8 0x2 0x1 -#define MX35_PAD_ATA_DMACK__CSPI2_MISO 0x270 0x6d4 0x7e8 0x4 0x2 -#define MX35_PAD_ATA_DMACK__GPIO2_10 0x270 0x6d4 0x86c 0x5 0x1 -#define MX35_PAD_ATA_DMACK__IPU_DIAGB_4 0x270 0x6d4 0x000 0x6 0x0 -#define MX35_PAD_ATA_DMACK__ARM11P_TOP_MAX0_HMASTER_0 0x270 0x6d4 0x000 0x7 0x0 -#define MX35_PAD_ATA_RESET_B__ATA_RESET_B 0x274 0x6d8 0x000 0x0 0x0 -#define MX35_PAD_ATA_RESET_B__ESDHC3_DAT3 0x274 0x6d8 0x828 0x1 0x1 -#define MX35_PAD_ATA_RESET_B__USB_TOP_USBOTG_DATA_0 0x274 0x6d8 0x9a4 0x2 0x1 -#define MX35_PAD_ATA_RESET_B__IPU_DISPB_SD_D_O 0x274 0x6d8 0x000 0x3 0x0 -#define MX35_PAD_ATA_RESET_B__CSPI2_RDY 0x274 0x6d8 0x7e4 0x4 0x2 -#define MX35_PAD_ATA_RESET_B__GPIO2_11 0x274 0x6d8 0x870 0x5 0x1 -#define MX35_PAD_ATA_RESET_B__IPU_DIAGB_5 0x274 0x6d8 0x000 0x6 0x0 -#define MX35_PAD_ATA_RESET_B__ARM11P_TOP_MAX0_HMASTER_1 0x274 0x6d8 0x000 0x7 0x0 -#define MX35_PAD_ATA_IORDY__ATA_IORDY 0x278 0x6dc 0x000 0x0 0x0 -#define MX35_PAD_ATA_IORDY__ESDHC3_DAT4 0x278 0x6dc 0x000 0x1 0x0 -#define MX35_PAD_ATA_IORDY__USB_TOP_USBOTG_DATA_1 0x278 0x6dc 0x9a8 0x2 0x1 -#define MX35_PAD_ATA_IORDY__IPU_DISPB_SD_D_IO 0x278 0x6dc 0x92c 0x3 0x3 -#define MX35_PAD_ATA_IORDY__ESDHC2_DAT4 0x278 0x6dc 0x000 0x4 0x0 -#define MX35_PAD_ATA_IORDY__GPIO2_12 0x278 0x6dc 0x874 0x5 0x1 -#define MX35_PAD_ATA_IORDY__IPU_DIAGB_6 0x278 0x6dc 0x000 0x6 0x0 -#define MX35_PAD_ATA_IORDY__ARM11P_TOP_MAX0_HMASTER_2 0x278 0x6dc 0x000 0x7 0x0 -#define MX35_PAD_ATA_DATA0__ATA_DATA_0 0x27c 0x6e0 0x000 0x0 0x0 -#define MX35_PAD_ATA_DATA0__ESDHC3_DAT5 0x27c 0x6e0 0x000 0x1 0x0 -#define MX35_PAD_ATA_DATA0__USB_TOP_USBOTG_DATA_2 0x27c 0x6e0 0x9ac 0x2 0x1 -#define MX35_PAD_ATA_DATA0__IPU_DISPB_D12_VSYNC 0x27c 0x6e0 0x928 0x3 0x4 -#define MX35_PAD_ATA_DATA0__ESDHC2_DAT5 0x27c 0x6e0 0x000 0x4 0x0 -#define MX35_PAD_ATA_DATA0__GPIO2_13 0x27c 0x6e0 0x878 0x5 0x1 -#define MX35_PAD_ATA_DATA0__IPU_DIAGB_7 0x27c 0x6e0 0x000 0x6 0x0 -#define MX35_PAD_ATA_DATA0__ARM11P_TOP_MAX0_HMASTER_3 0x27c 0x6e0 0x000 0x7 0x0 -#define MX35_PAD_ATA_DATA1__ATA_DATA_1 0x280 0x6e4 0x000 0x0 0x0 -#define MX35_PAD_ATA_DATA1__ESDHC3_DAT6 0x280 0x6e4 0x000 0x1 0x0 -#define MX35_PAD_ATA_DATA1__USB_TOP_USBOTG_DATA_3 0x280 0x6e4 0x9b0 0x2 0x1 -#define MX35_PAD_ATA_DATA1__IPU_DISPB_SD_CLK 0x280 0x6e4 0x000 0x3 0x0 -#define MX35_PAD_ATA_DATA1__ESDHC2_DAT6 0x280 0x6e4 0x000 0x4 0x0 -#define MX35_PAD_ATA_DATA1__GPIO2_14 0x280 0x6e4 0x87c 0x5 0x1 -#define MX35_PAD_ATA_DATA1__IPU_DIAGB_8 0x280 0x6e4 0x000 0x6 0x0 -#define MX35_PAD_ATA_DATA1__ARM11P_TOP_TRACE_27 0x280 0x6e4 0x000 0x7 0x0 -#define MX35_PAD_ATA_DATA2__ATA_DATA_2 0x284 0x6e8 0x000 0x0 0x0 -#define MX35_PAD_ATA_DATA2__ESDHC3_DAT7 0x284 0x6e8 0x000 0x1 0x0 -#define MX35_PAD_ATA_DATA2__USB_TOP_USBOTG_DATA_4 0x284 0x6e8 0x9b4 0x2 0x1 -#define MX35_PAD_ATA_DATA2__IPU_DISPB_SER_RS 0x284 0x6e8 0x000 0x3 0x0 -#define MX35_PAD_ATA_DATA2__ESDHC2_DAT7 0x284 0x6e8 0x000 0x4 0x0 -#define MX35_PAD_ATA_DATA2__GPIO2_15 0x284 0x6e8 0x880 0x5 0x1 -#define MX35_PAD_ATA_DATA2__IPU_DIAGB_9 0x284 0x6e8 0x000 0x6 0x0 -#define MX35_PAD_ATA_DATA2__ARM11P_TOP_TRACE_28 0x284 0x6e8 0x000 0x7 0x0 -#define MX35_PAD_ATA_DATA3__ATA_DATA_3 0x288 0x6ec 0x000 0x0 0x0 -#define MX35_PAD_ATA_DATA3__ESDHC3_CLK 0x288 0x6ec 0x814 0x1 0x1 -#define MX35_PAD_ATA_DATA3__USB_TOP_USBOTG_DATA_5 0x288 0x6ec 0x9b8 0x2 0x1 -#define MX35_PAD_ATA_DATA3__CSPI2_SCLK 0x288 0x6ec 0x7e0 0x4 0x2 -#define MX35_PAD_ATA_DATA3__GPIO2_16 0x288 0x6ec 0x884 0x5 0x1 -#define MX35_PAD_ATA_DATA3__IPU_DIAGB_10 0x288 0x6ec 0x000 0x6 0x0 -#define MX35_PAD_ATA_DATA3__ARM11P_TOP_TRACE_29 0x288 0x6ec 0x000 0x7 0x0 -#define MX35_PAD_ATA_DATA4__ATA_DATA_4 0x28c 0x6f0 0x000 0x0 0x0 -#define MX35_PAD_ATA_DATA4__ESDHC3_CMD 0x28c 0x6f0 0x818 0x1 0x1 -#define MX35_PAD_ATA_DATA4__USB_TOP_USBOTG_DATA_6 0x28c 0x6f0 0x9bc 0x2 0x1 -#define MX35_PAD_ATA_DATA4__GPIO2_17 0x28c 0x6f0 0x888 0x5 0x1 -#define MX35_PAD_ATA_DATA4__IPU_DIAGB_11 0x28c 0x6f0 0x000 0x6 0x0 -#define MX35_PAD_ATA_DATA4__ARM11P_TOP_TRACE_30 0x28c 0x6f0 0x000 0x7 0x0 -#define MX35_PAD_ATA_DATA5__ATA_DATA_5 0x290 0x6f4 0x000 0x0 0x0 -#define MX35_PAD_ATA_DATA5__USB_TOP_USBOTG_DATA_7 0x290 0x6f4 0x9c0 0x2 0x1 -#define MX35_PAD_ATA_DATA5__GPIO2_18 0x290 0x6f4 0x88c 0x5 0x1 -#define MX35_PAD_ATA_DATA5__IPU_DIAGB_12 0x290 0x6f4 0x000 0x6 0x0 -#define MX35_PAD_ATA_DATA5__ARM11P_TOP_TRACE_31 0x290 0x6f4 0x000 0x7 0x0 -#define MX35_PAD_ATA_DATA6__ATA_DATA_6 0x294 0x6f8 0x000 0x0 0x0 -#define MX35_PAD_ATA_DATA6__CAN1_TXCAN 0x294 0x6f8 0x000 0x1 0x0 -#define MX35_PAD_ATA_DATA6__UART1_DTR 0x294 0x6f8 0x000 0x2 0x0 -#define MX35_PAD_ATA_DATA6__AUDMUX_AUD6_TXD 0x294 0x6f8 0x7b4 0x3 0x0 -#define MX35_PAD_ATA_DATA6__GPIO2_19 0x294 0x6f8 0x890 0x5 0x1 -#define MX35_PAD_ATA_DATA6__IPU_DIAGB_13 0x294 0x6f8 0x000 0x6 0x0 -#define MX35_PAD_ATA_DATA7__ATA_DATA_7 0x298 0x6fc 0x000 0x0 0x0 -#define MX35_PAD_ATA_DATA7__CAN1_RXCAN 0x298 0x6fc 0x7c8 0x1 0x2 -#define MX35_PAD_ATA_DATA7__UART1_DSR 0x298 0x6fc 0x000 0x2 0x0 -#define MX35_PAD_ATA_DATA7__AUDMUX_AUD6_RXD 0x298 0x6fc 0x7b0 0x3 0x0 -#define MX35_PAD_ATA_DATA7__GPIO2_20 0x298 0x6fc 0x898 0x5 0x1 -#define MX35_PAD_ATA_DATA7__IPU_DIAGB_14 0x298 0x6fc 0x000 0x6 0x0 -#define MX35_PAD_ATA_DATA8__ATA_DATA_8 0x29c 0x700 0x000 0x0 0x0 -#define MX35_PAD_ATA_DATA8__UART3_RTS 0x29c 0x700 0x99c 0x1 0x1 -#define MX35_PAD_ATA_DATA8__UART1_RI 0x29c 0x700 0x000 0x2 0x0 -#define MX35_PAD_ATA_DATA8__AUDMUX_AUD6_TXC 0x29c 0x700 0x7c0 0x3 0x0 -#define MX35_PAD_ATA_DATA8__GPIO2_21 0x29c 0x700 0x89c 0x5 0x1 -#define MX35_PAD_ATA_DATA8__IPU_DIAGB_15 0x29c 0x700 0x000 0x6 0x0 -#define MX35_PAD_ATA_DATA9__ATA_DATA_9 0x2a0 0x704 0x000 0x0 0x0 -#define MX35_PAD_ATA_DATA9__UART3_CTS 0x2a0 0x704 0x000 0x1 0x0 -#define MX35_PAD_ATA_DATA9__UART1_DCD 0x2a0 0x704 0x000 0x2 0x0 -#define MX35_PAD_ATA_DATA9__AUDMUX_AUD6_TXFS 0x2a0 0x704 0x7c4 0x3 0x0 -#define MX35_PAD_ATA_DATA9__GPIO2_22 0x2a0 0x704 0x8a0 0x5 0x1 -#define MX35_PAD_ATA_DATA9__IPU_DIAGB_16 0x2a0 0x704 0x000 0x6 0x0 -#define MX35_PAD_ATA_DATA10__ATA_DATA_10 0x2a4 0x708 0x000 0x0 0x0 -#define MX35_PAD_ATA_DATA10__UART3_RXD_MUX 0x2a4 0x708 0x9a0 0x1 0x2 -#define MX35_PAD_ATA_DATA10__AUDMUX_AUD6_RXC 0x2a4 0x708 0x7b8 0x3 0x0 -#define MX35_PAD_ATA_DATA10__GPIO2_23 0x2a4 0x708 0x8a4 0x5 0x1 -#define MX35_PAD_ATA_DATA10__IPU_DIAGB_17 0x2a4 0x708 0x000 0x6 0x0 -#define MX35_PAD_ATA_DATA11__ATA_DATA_11 0x2a8 0x70c 0x000 0x0 0x0 -#define MX35_PAD_ATA_DATA11__UART3_TXD_MUX 0x2a8 0x70c 0x000 0x1 0x0 -#define MX35_PAD_ATA_DATA11__AUDMUX_AUD6_RXFS 0x2a8 0x70c 0x7bc 0x3 0x0 -#define MX35_PAD_ATA_DATA11__GPIO2_24 0x2a8 0x70c 0x8a8 0x5 0x1 -#define MX35_PAD_ATA_DATA11__IPU_DIAGB_18 0x2a8 0x70c 0x000 0x6 0x0 -#define MX35_PAD_ATA_DATA12__ATA_DATA_12 0x2ac 0x710 0x000 0x0 0x0 -#define MX35_PAD_ATA_DATA12__I2C3_SCL 0x2ac 0x710 0x91c 0x1 0x3 -#define MX35_PAD_ATA_DATA12__GPIO2_25 0x2ac 0x710 0x8ac 0x5 0x1 -#define MX35_PAD_ATA_DATA12__IPU_DIAGB_19 0x2ac 0x710 0x000 0x6 0x0 -#define MX35_PAD_ATA_DATA13__ATA_DATA_13 0x2b0 0x714 0x000 0x0 0x0 -#define MX35_PAD_ATA_DATA13__I2C3_SDA 0x2b0 0x714 0x920 0x1 0x3 -#define MX35_PAD_ATA_DATA13__GPIO2_26 0x2b0 0x714 0x8b0 0x5 0x1 -#define MX35_PAD_ATA_DATA13__IPU_DIAGB_20 0x2b0 0x714 0x000 0x6 0x0 -#define MX35_PAD_ATA_DATA14__ATA_DATA_14 0x2b4 0x718 0x000 0x0 0x0 -#define MX35_PAD_ATA_DATA14__IPU_CSI_D_0 0x2b4 0x718 0x930 0x1 0x2 -#define MX35_PAD_ATA_DATA14__KPP_ROW_0 0x2b4 0x718 0x970 0x3 0x2 -#define MX35_PAD_ATA_DATA14__GPIO2_27 0x2b4 0x718 0x8b4 0x5 0x1 -#define MX35_PAD_ATA_DATA14__IPU_DIAGB_21 0x2b4 0x718 0x000 0x6 0x0 -#define MX35_PAD_ATA_DATA15__ATA_DATA_15 0x2b8 0x71c 0x000 0x0 0x0 -#define MX35_PAD_ATA_DATA15__IPU_CSI_D_1 0x2b8 0x71c 0x934 0x1 0x2 -#define MX35_PAD_ATA_DATA15__KPP_ROW_1 0x2b8 0x71c 0x974 0x3 0x2 -#define MX35_PAD_ATA_DATA15__GPIO2_28 0x2b8 0x71c 0x8b8 0x5 0x1 -#define MX35_PAD_ATA_DATA15__IPU_DIAGB_22 0x2b8 0x71c 0x000 0x6 0x0 -#define MX35_PAD_ATA_INTRQ__ATA_INTRQ 0x2bc 0x720 0x000 0x0 0x0 -#define MX35_PAD_ATA_INTRQ__IPU_CSI_D_2 0x2bc 0x720 0x938 0x1 0x3 -#define MX35_PAD_ATA_INTRQ__KPP_ROW_2 0x2bc 0x720 0x978 0x3 0x2 -#define MX35_PAD_ATA_INTRQ__GPIO2_29 0x2bc 0x720 0x8bc 0x5 0x1 -#define MX35_PAD_ATA_INTRQ__IPU_DIAGB_23 0x2bc 0x720 0x000 0x6 0x0 -#define MX35_PAD_ATA_BUFF_EN__ATA_BUFFER_EN 0x2c0 0x724 0x000 0x0 0x0 -#define MX35_PAD_ATA_BUFF_EN__IPU_CSI_D_3 0x2c0 0x724 0x93c 0x1 0x3 -#define MX35_PAD_ATA_BUFF_EN__KPP_ROW_3 0x2c0 0x724 0x97c 0x3 0x2 -#define MX35_PAD_ATA_BUFF_EN__GPIO2_30 0x2c0 0x724 0x8c4 0x5 0x1 -#define MX35_PAD_ATA_BUFF_EN__IPU_DIAGB_24 0x2c0 0x724 0x000 0x6 0x0 -#define MX35_PAD_ATA_DMARQ__ATA_DMARQ 0x2c4 0x728 0x000 0x0 0x0 -#define MX35_PAD_ATA_DMARQ__IPU_CSI_D_4 0x2c4 0x728 0x940 0x1 0x2 -#define MX35_PAD_ATA_DMARQ__KPP_COL_0 0x2c4 0x728 0x950 0x3 0x2 -#define MX35_PAD_ATA_DMARQ__GPIO2_31 0x2c4 0x728 0x8c8 0x5 0x1 -#define MX35_PAD_ATA_DMARQ__IPU_DIAGB_25 0x2c4 0x728 0x000 0x6 0x0 -#define MX35_PAD_ATA_DMARQ__ECT_CTI_TRIG_IN1_4 0x2c4 0x728 0x000 0x7 0x0 -#define MX35_PAD_ATA_DA0__ATA_DA_0 0x2c8 0x72c 0x000 0x0 0x0 -#define MX35_PAD_ATA_DA0__IPU_CSI_D_5 0x2c8 0x72c 0x944 0x1 0x2 -#define MX35_PAD_ATA_DA0__KPP_COL_1 0x2c8 0x72c 0x954 0x3 0x2 -#define MX35_PAD_ATA_DA0__GPIO3_0 0x2c8 0x72c 0x8e8 0x5 0x1 -#define MX35_PAD_ATA_DA0__IPU_DIAGB_26 0x2c8 0x72c 0x000 0x6 0x0 -#define MX35_PAD_ATA_DA0__ECT_CTI_TRIG_IN1_5 0x2c8 0x72c 0x000 0x7 0x0 -#define MX35_PAD_ATA_DA1__ATA_DA_1 0x2cc 0x730 0x000 0x0 0x0 -#define MX35_PAD_ATA_DA1__IPU_CSI_D_6 0x2cc 0x730 0x948 0x1 0x2 -#define MX35_PAD_ATA_DA1__KPP_COL_2 0x2cc 0x730 0x958 0x3 0x2 -#define MX35_PAD_ATA_DA1__GPIO3_1 0x2cc 0x730 0x000 0x5 0x0 -#define MX35_PAD_ATA_DA1__IPU_DIAGB_27 0x2cc 0x730 0x000 0x6 0x0 -#define MX35_PAD_ATA_DA1__ECT_CTI_TRIG_IN1_6 0x2cc 0x730 0x000 0x7 0x0 -#define MX35_PAD_ATA_DA2__ATA_DA_2 0x2d0 0x734 0x000 0x0 0x0 -#define MX35_PAD_ATA_DA2__IPU_CSI_D_7 0x2d0 0x734 0x94c 0x1 0x2 -#define MX35_PAD_ATA_DA2__KPP_COL_3 0x2d0 0x734 0x95c 0x3 0x2 -#define MX35_PAD_ATA_DA2__GPIO3_2 0x2d0 0x734 0x000 0x5 0x0 -#define MX35_PAD_ATA_DA2__IPU_DIAGB_28 0x2d0 0x734 0x000 0x6 0x0 -#define MX35_PAD_ATA_DA2__ECT_CTI_TRIG_IN1_7 0x2d0 0x734 0x000 0x7 0x0 -#define MX35_PAD_MLB_CLK__MLB_MLBCLK 0x2d4 0x738 0x000 0x0 0x0 -#define MX35_PAD_MLB_CLK__GPIO3_3 0x2d4 0x738 0x000 0x5 0x0 -#define MX35_PAD_MLB_DAT__MLB_MLBDAT 0x2d8 0x73c 0x000 0x0 0x0 -#define MX35_PAD_MLB_DAT__GPIO3_4 0x2d8 0x73c 0x904 0x5 0x1 -#define MX35_PAD_MLB_SIG__MLB_MLBSIG 0x2dc 0x740 0x000 0x0 0x0 -#define MX35_PAD_MLB_SIG__GPIO3_5 0x2dc 0x740 0x908 0x5 0x1 -#define MX35_PAD_FEC_TX_CLK__FEC_TX_CLK 0x2e0 0x744 0x000 0x0 0x0 -#define MX35_PAD_FEC_TX_CLK__ESDHC1_DAT4 0x2e0 0x744 0x804 0x1 0x1 -#define MX35_PAD_FEC_TX_CLK__UART3_RXD_MUX 0x2e0 0x744 0x9a0 0x2 0x3 -#define MX35_PAD_FEC_TX_CLK__USB_TOP_USBH2_DIR 0x2e0 0x744 0x9ec 0x3 0x1 -#define MX35_PAD_FEC_TX_CLK__CSPI2_MOSI 0x2e0 0x744 0x7ec 0x4 0x3 -#define MX35_PAD_FEC_TX_CLK__GPIO3_6 0x2e0 0x744 0x90c 0x5 0x1 -#define MX35_PAD_FEC_TX_CLK__IPU_DISPB_D12_VSYNC 0x2e0 0x744 0x928 0x6 0x5 -#define MX35_PAD_FEC_TX_CLK__ARM11P_TOP_EVNTBUS_0 0x2e0 0x744 0x000 0x7 0x0 -#define MX35_PAD_FEC_RX_CLK__FEC_RX_CLK 0x2e4 0x748 0x000 0x0 0x0 -#define MX35_PAD_FEC_RX_CLK__ESDHC1_DAT5 0x2e4 0x748 0x808 0x1 0x1 -#define MX35_PAD_FEC_RX_CLK__UART3_TXD_MUX 0x2e4 0x748 0x000 0x2 0x0 -#define MX35_PAD_FEC_RX_CLK__USB_TOP_USBH2_STP 0x2e4 0x748 0x000 0x3 0x0 -#define MX35_PAD_FEC_RX_CLK__CSPI2_MISO 0x2e4 0x748 0x7e8 0x4 0x3 -#define MX35_PAD_FEC_RX_CLK__GPIO3_7 0x2e4 0x748 0x910 0x5 0x1 -#define MX35_PAD_FEC_RX_CLK__IPU_DISPB_SD_D_I 0x2e4 0x748 0x92c 0x6 0x4 -#define MX35_PAD_FEC_RX_CLK__ARM11P_TOP_EVNTBUS_1 0x2e4 0x748 0x000 0x7 0x0 -#define MX35_PAD_FEC_RX_DV__FEC_RX_DV 0x2e8 0x74c 0x000 0x0 0x0 -#define MX35_PAD_FEC_RX_DV__ESDHC1_DAT6 0x2e8 0x74c 0x80c 0x1 0x1 -#define MX35_PAD_FEC_RX_DV__UART3_RTS 0x2e8 0x74c 0x99c 0x2 0x2 -#define MX35_PAD_FEC_RX_DV__USB_TOP_USBH2_NXT 0x2e8 0x74c 0x9f0 0x3 0x1 -#define MX35_PAD_FEC_RX_DV__CSPI2_SCLK 0x2e8 0x74c 0x7e0 0x4 0x3 -#define MX35_PAD_FEC_RX_DV__GPIO3_8 0x2e8 0x74c 0x914 0x5 0x1 -#define MX35_PAD_FEC_RX_DV__IPU_DISPB_SD_CLK 0x2e8 0x74c 0x000 0x6 0x0 -#define MX35_PAD_FEC_RX_DV__ARM11P_TOP_EVNTBUS_2 0x2e8 0x74c 0x000 0x7 0x0 -#define MX35_PAD_FEC_COL__FEC_COL 0x2ec 0x750 0x000 0x0 0x0 -#define MX35_PAD_FEC_COL__ESDHC1_DAT7 0x2ec 0x750 0x810 0x1 0x1 -#define MX35_PAD_FEC_COL__UART3_CTS 0x2ec 0x750 0x000 0x2 0x0 -#define MX35_PAD_FEC_COL__USB_TOP_USBH2_DATA_0 0x2ec 0x750 0x9cc 0x3 0x1 -#define MX35_PAD_FEC_COL__CSPI2_RDY 0x2ec 0x750 0x7e4 0x4 0x3 -#define MX35_PAD_FEC_COL__GPIO3_9 0x2ec 0x750 0x918 0x5 0x1 -#define MX35_PAD_FEC_COL__IPU_DISPB_SER_RS 0x2ec 0x750 0x000 0x6 0x0 -#define MX35_PAD_FEC_COL__ARM11P_TOP_EVNTBUS_3 0x2ec 0x750 0x000 0x7 0x0 -#define MX35_PAD_FEC_RDATA0__FEC_RDATA_0 0x2f0 0x754 0x000 0x0 0x0 -#define MX35_PAD_FEC_RDATA0__PWM_PWMO 0x2f0 0x754 0x000 0x1 0x0 -#define MX35_PAD_FEC_RDATA0__UART3_DTR 0x2f0 0x754 0x000 0x2 0x0 -#define MX35_PAD_FEC_RDATA0__USB_TOP_USBH2_DATA_1 0x2f0 0x754 0x9d0 0x3 0x1 -#define MX35_PAD_FEC_RDATA0__CSPI2_SS0 0x2f0 0x754 0x7f0 0x4 0x2 -#define MX35_PAD_FEC_RDATA0__GPIO3_10 0x2f0 0x754 0x8ec 0x5 0x1 -#define MX35_PAD_FEC_RDATA0__IPU_DISPB_CS1 0x2f0 0x754 0x000 0x6 0x0 -#define MX35_PAD_FEC_RDATA0__ARM11P_TOP_EVNTBUS_4 0x2f0 0x754 0x000 0x7 0x0 -#define MX35_PAD_FEC_TDATA0__FEC_TDATA_0 0x2f4 0x758 0x000 0x0 0x0 -#define MX35_PAD_FEC_TDATA0__SPDIF_SPDIF_OUT1 0x2f4 0x758 0x000 0x1 0x0 -#define MX35_PAD_FEC_TDATA0__UART3_DSR 0x2f4 0x758 0x000 0x2 0x0 -#define MX35_PAD_FEC_TDATA0__USB_TOP_USBH2_DATA_2 0x2f4 0x758 0x9d4 0x3 0x1 -#define MX35_PAD_FEC_TDATA0__CSPI2_SS1 0x2f4 0x758 0x7f4 0x4 0x2 -#define MX35_PAD_FEC_TDATA0__GPIO3_11 0x2f4 0x758 0x8f0 0x5 0x1 -#define MX35_PAD_FEC_TDATA0__IPU_DISPB_CS0 0x2f4 0x758 0x000 0x6 0x0 -#define MX35_PAD_FEC_TDATA0__ARM11P_TOP_EVNTBUS_5 0x2f4 0x758 0x000 0x7 0x0 -#define MX35_PAD_FEC_TX_EN__FEC_TX_EN 0x2f8 0x75c 0x000 0x0 0x0 -#define MX35_PAD_FEC_TX_EN__SPDIF_SPDIF_IN1 0x2f8 0x75c 0x998 0x1 0x3 -#define MX35_PAD_FEC_TX_EN__UART3_RI 0x2f8 0x75c 0x000 0x2 0x0 -#define MX35_PAD_FEC_TX_EN__USB_TOP_USBH2_DATA_3 0x2f8 0x75c 0x9d8 0x3 0x1 -#define MX35_PAD_FEC_TX_EN__GPIO3_12 0x2f8 0x75c 0x8f4 0x5 0x1 -#define MX35_PAD_FEC_TX_EN__IPU_DISPB_PAR_RS 0x2f8 0x75c 0x000 0x6 0x0 -#define MX35_PAD_FEC_TX_EN__ARM11P_TOP_EVNTBUS_6 0x2f8 0x75c 0x000 0x7 0x0 -#define MX35_PAD_FEC_MDC__FEC_MDC 0x2fc 0x760 0x000 0x0 0x0 -#define MX35_PAD_FEC_MDC__CAN2_TXCAN 0x2fc 0x760 0x000 0x1 0x0 -#define MX35_PAD_FEC_MDC__UART3_DCD 0x2fc 0x760 0x000 0x2 0x0 -#define MX35_PAD_FEC_MDC__USB_TOP_USBH2_DATA_4 0x2fc 0x760 0x9dc 0x3 0x1 -#define MX35_PAD_FEC_MDC__GPIO3_13 0x2fc 0x760 0x8f8 0x5 0x1 -#define MX35_PAD_FEC_MDC__IPU_DISPB_WR 0x2fc 0x760 0x000 0x6 0x0 -#define MX35_PAD_FEC_MDC__ARM11P_TOP_EVNTBUS_7 0x2fc 0x760 0x000 0x7 0x0 -#define MX35_PAD_FEC_MDIO__FEC_MDIO 0x300 0x764 0x000 0x0 0x0 -#define MX35_PAD_FEC_MDIO__CAN2_RXCAN 0x300 0x764 0x7cc 0x1 0x2 -#define MX35_PAD_FEC_MDIO__USB_TOP_USBH2_DATA_5 0x300 0x764 0x9e0 0x3 0x1 -#define MX35_PAD_FEC_MDIO__GPIO3_14 0x300 0x764 0x8fc 0x5 0x1 -#define MX35_PAD_FEC_MDIO__IPU_DISPB_RD 0x300 0x764 0x000 0x6 0x0 -#define MX35_PAD_FEC_MDIO__ARM11P_TOP_EVNTBUS_8 0x300 0x764 0x000 0x7 0x0 -#define MX35_PAD_FEC_TX_ERR__FEC_TX_ERR 0x304 0x768 0x000 0x0 0x0 -#define MX35_PAD_FEC_TX_ERR__OWIRE_LINE 0x304 0x768 0x990 0x1 0x2 -#define MX35_PAD_FEC_TX_ERR__SPDIF_SPDIF_EXTCLK 0x304 0x768 0x994 0x2 0x4 -#define MX35_PAD_FEC_TX_ERR__USB_TOP_USBH2_DATA_6 0x304 0x768 0x9e4 0x3 0x1 -#define MX35_PAD_FEC_TX_ERR__GPIO3_15 0x304 0x768 0x900 0x5 0x1 -#define MX35_PAD_FEC_TX_ERR__IPU_DISPB_D0_VSYNC 0x304 0x768 0x924 0x6 0x3 -#define MX35_PAD_FEC_TX_ERR__ARM11P_TOP_EVNTBUS_9 0x304 0x768 0x000 0x7 0x0 -#define MX35_PAD_FEC_RX_ERR__FEC_RX_ERR 0x308 0x76c 0x000 0x0 0x0 -#define MX35_PAD_FEC_RX_ERR__IPU_CSI_D_0 0x308 0x76c 0x930 0x1 0x3 -#define MX35_PAD_FEC_RX_ERR__USB_TOP_USBH2_DATA_7 0x308 0x76c 0x9e8 0x3 0x1 -#define MX35_PAD_FEC_RX_ERR__KPP_COL_4 0x308 0x76c 0x960 0x4 0x1 -#define MX35_PAD_FEC_RX_ERR__GPIO3_16 0x308 0x76c 0x000 0x5 0x0 -#define MX35_PAD_FEC_RX_ERR__IPU_DISPB_SD_D_IO 0x308 0x76c 0x92c 0x6 0x5 -#define MX35_PAD_FEC_CRS__FEC_CRS 0x30c 0x770 0x000 0x0 0x0 -#define MX35_PAD_FEC_CRS__IPU_CSI_D_1 0x30c 0x770 0x934 0x1 0x3 -#define MX35_PAD_FEC_CRS__USB_TOP_USBH2_PWR 0x30c 0x770 0x000 0x3 0x0 -#define MX35_PAD_FEC_CRS__KPP_COL_5 0x30c 0x770 0x964 0x4 0x1 -#define MX35_PAD_FEC_CRS__GPIO3_17 0x30c 0x770 0x000 0x5 0x0 -#define MX35_PAD_FEC_CRS__IPU_FLASH_STROBE 0x30c 0x770 0x000 0x6 0x0 -#define MX35_PAD_FEC_RDATA1__FEC_RDATA_1 0x310 0x774 0x000 0x0 0x0 -#define MX35_PAD_FEC_RDATA1__IPU_CSI_D_2 0x310 0x774 0x938 0x1 0x4 -#define MX35_PAD_FEC_RDATA1__AUDMUX_AUD6_RXC 0x310 0x774 0x000 0x2 0x0 -#define MX35_PAD_FEC_RDATA1__USB_TOP_USBH2_OC 0x310 0x774 0x9f4 0x3 0x2 -#define MX35_PAD_FEC_RDATA1__KPP_COL_6 0x310 0x774 0x968 0x4 0x1 -#define MX35_PAD_FEC_RDATA1__GPIO3_18 0x310 0x774 0x000 0x5 0x0 -#define MX35_PAD_FEC_RDATA1__IPU_DISPB_BE0 0x310 0x774 0x000 0x6 0x0 -#define MX35_PAD_FEC_TDATA1__FEC_TDATA_1 0x314 0x778 0x000 0x0 0x0 -#define MX35_PAD_FEC_TDATA1__IPU_CSI_D_3 0x314 0x778 0x93c 0x1 0x4 -#define MX35_PAD_FEC_TDATA1__AUDMUX_AUD6_RXFS 0x314 0x778 0x7bc 0x2 0x1 -#define MX35_PAD_FEC_TDATA1__KPP_COL_7 0x314 0x778 0x96c 0x4 0x1 -#define MX35_PAD_FEC_TDATA1__GPIO3_19 0x314 0x778 0x000 0x5 0x0 -#define MX35_PAD_FEC_TDATA1__IPU_DISPB_BE1 0x314 0x778 0x000 0x6 0x0 -#define MX35_PAD_FEC_RDATA2__FEC_RDATA_2 0x318 0x77c 0x000 0x0 0x0 -#define MX35_PAD_FEC_RDATA2__IPU_CSI_D_4 0x318 0x77c 0x940 0x1 0x3 -#define MX35_PAD_FEC_RDATA2__AUDMUX_AUD6_TXD 0x318 0x77c 0x7b4 0x2 0x1 -#define MX35_PAD_FEC_RDATA2__KPP_ROW_4 0x318 0x77c 0x980 0x4 0x1 -#define MX35_PAD_FEC_RDATA2__GPIO3_20 0x318 0x77c 0x000 0x5 0x0 -#define MX35_PAD_FEC_TDATA2__FEC_TDATA_2 0x31c 0x780 0x000 0x0 0x0 -#define MX35_PAD_FEC_TDATA2__IPU_CSI_D_5 0x31c 0x780 0x944 0x1 0x3 -#define MX35_PAD_FEC_TDATA2__AUDMUX_AUD6_RXD 0x31c 0x780 0x7b0 0x2 0x1 -#define MX35_PAD_FEC_TDATA2__KPP_ROW_5 0x31c 0x780 0x984 0x4 0x1 -#define MX35_PAD_FEC_TDATA2__GPIO3_21 0x31c 0x780 0x000 0x5 0x0 -#define MX35_PAD_FEC_RDATA3__FEC_RDATA_3 0x320 0x784 0x000 0x0 0x0 -#define MX35_PAD_FEC_RDATA3__IPU_CSI_D_6 0x320 0x784 0x948 0x1 0x3 -#define MX35_PAD_FEC_RDATA3__AUDMUX_AUD6_TXC 0x320 0x784 0x7c0 0x2 0x1 -#define MX35_PAD_FEC_RDATA3__KPP_ROW_6 0x320 0x784 0x988 0x4 0x1 -#define MX35_PAD_FEC_RDATA3__GPIO3_22 0x320 0x784 0x000 0x6 0x0 -#define MX35_PAD_FEC_TDATA3__FEC_TDATA_3 0x324 0x788 0x000 0x0 0x0 -#define MX35_PAD_FEC_TDATA3__IPU_CSI_D_7 0x324 0x788 0x94c 0x1 0x3 -#define MX35_PAD_FEC_TDATA3__AUDMUX_AUD6_TXFS 0x324 0x788 0x7c4 0x2 0x1 -#define MX35_PAD_FEC_TDATA3__KPP_ROW_7 0x324 0x788 0x98c 0x4 0x1 -#define MX35_PAD_FEC_TDATA3__GPIO3_23 0x324 0x788 0x000 0x5 0x0 -#define MX35_PAD_EXT_ARMCLK__CCM_EXT_ARMCLK 0x000 0x78c 0x000 0x0 0x0 -#define MX35_PAD_TEST_MODE__TCU_TEST_MODE 0x000 0x790 0x000 0x0 0x0 - -#endif /* __DTS_IMX35_PINFUNC_H */ diff --git a/sys/gnu/dts/arm/imx35.dtsi b/sys/gnu/dts/arm/imx35.dtsi deleted file mode 100644 index 9cbdc1a15cd..00000000000 --- a/sys/gnu/dts/arm/imx35.dtsi +++ /dev/null @@ -1,414 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// -// Copyright 2012 Steffen Trumtrar, Pengutronix -// -// based on imx27.dtsi - -#include "imx35-pinfunc.h" - -/ { - #address-cells = <1>; - #size-cells = <1>; - /* - * The decompressor and also some bootloaders rely on a - * pre-existing /chosen node to be available to insert the - * command line and merge other ATAGS info. - */ - chosen {}; - - aliases { - ethernet0 = &fec; - gpio0 = &gpio1; - gpio1 = &gpio2; - gpio2 = &gpio3; - i2c0 = &i2c1; - i2c1 = &i2c2; - i2c2 = &i2c3; - mmc0 = &esdhc1; - mmc1 = &esdhc2; - mmc2 = &esdhc3; - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - spi0 = &spi1; - spi1 = &spi2; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "arm,arm1136jf-s"; - device_type = "cpu"; - reg = <0>; - }; - }; - - avic: avic-interrupt-controller@68000000 { - compatible = "fsl,imx35-avic", "fsl,avic"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x68000000 0x10000000>; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&avic>; - ranges; - - L2: l2-cache@30000000 { - compatible = "arm,l210-cache"; - reg = <0x30000000 0x1000>; - cache-unified; - cache-level = <2>; - }; - - aips1: aips@43f00000 { - compatible = "fsl,aips", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x43f00000 0x100000>; - ranges; - - i2c1: i2c@43f80000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx35-i2c", "fsl,imx1-i2c"; - reg = <0x43f80000 0x4000>; - clocks = <&clks 51>; - clock-names = "ipg_per"; - interrupts = <10>; - status = "disabled"; - }; - - i2c3: i2c@43f84000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx35-i2c", "fsl,imx1-i2c"; - reg = <0x43f84000 0x4000>; - clocks = <&clks 53>; - clock-names = "ipg_per"; - interrupts = <3>; - status = "disabled"; - }; - - uart1: serial@43f90000 { - compatible = "fsl,imx35-uart", "fsl,imx21-uart"; - reg = <0x43f90000 0x4000>; - clocks = <&clks 9>, <&clks 70>; - clock-names = "ipg", "per"; - interrupts = <45>; - status = "disabled"; - }; - - uart2: serial@43f94000 { - compatible = "fsl,imx35-uart", "fsl,imx21-uart"; - reg = <0x43f94000 0x4000>; - clocks = <&clks 9>, <&clks 71>; - clock-names = "ipg", "per"; - interrupts = <32>; - status = "disabled"; - }; - - i2c2: i2c@43f98000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx35-i2c", "fsl,imx1-i2c"; - reg = <0x43f98000 0x4000>; - clocks = <&clks 52>; - clock-names = "ipg_per"; - interrupts = <4>; - status = "disabled"; - }; - - ssi1: ssi@43fa0000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx35-ssi", "fsl,imx21-ssi"; - reg = <0x43fa0000 0x4000>; - interrupts = <11>; - clocks = <&clks 68>; - dmas = <&sdma 28 0 0>, - <&sdma 29 0 0>; - dma-names = "rx", "tx"; - fsl,fifo-depth = <15>; - status = "disabled"; - }; - - spi1: spi@43fa4000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx35-cspi"; - reg = <0x43fa4000 0x4000>; - clocks = <&clks 35 &clks 35>; - clock-names = "ipg", "per"; - interrupts = <14>; - status = "disabled"; - }; - - kpp: kpp@43fa8000 { - compatible = "fsl,imx35-kpp", "fsl,imx21-kpp"; - reg = <0x43fa8000 0x4000>; - interrupts = <24>; - clocks = <&clks 56>; - status = "disabled"; - }; - - iomuxc: iomuxc@43fac000 { - compatible = "fsl,imx35-iomuxc"; - reg = <0x43fac000 0x4000>; - }; - }; - - spba: spba-bus@50000000 { - compatible = "fsl,spba-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x50000000 0x100000>; - ranges; - - uart3: serial@5000c000 { - compatible = "fsl,imx35-uart", "fsl,imx21-uart"; - reg = <0x5000c000 0x4000>; - clocks = <&clks 9>, <&clks 72>; - clock-names = "ipg", "per"; - interrupts = <18>; - status = "disabled"; - }; - - spi2: spi@50010000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx35-cspi"; - reg = <0x50010000 0x4000>; - interrupts = <13>; - clocks = <&clks 36 &clks 36>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - fec: fec@50038000 { - compatible = "fsl,imx35-fec", "fsl,imx27-fec"; - reg = <0x50038000 0x4000>; - clocks = <&clks 46>, <&clks 8>; - clock-names = "ipg", "ahb"; - interrupts = <57>; - status = "disabled"; - }; - }; - - aips2: aips@53f00000 { - compatible = "fsl,aips", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x53f00000 0x100000>; - ranges; - - clks: ccm@53f80000 { - compatible = "fsl,imx35-ccm"; - reg = <0x53f80000 0x4000>; - interrupts = <31>; - #clock-cells = <1>; - }; - - gpt: timer@53f90000 { - compatible = "fsl,imx35-gpt", "fsl,imx31-gpt"; - reg = <0x53f90000 0x4000>; - interrupts = <29>; - clocks = <&clks 9>, <&clks 50>; - clock-names = "ipg", "per"; - }; - - gpio3: gpio@53fa4000 { - compatible = "fsl,imx35-gpio", "fsl,imx31-gpio"; - reg = <0x53fa4000 0x4000>; - interrupts = <56>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - esdhc1: esdhc@53fb4000 { - compatible = "fsl,imx35-esdhc"; - reg = <0x53fb4000 0x4000>; - interrupts = <7>; - clocks = <&clks 9>, <&clks 8>, <&clks 43>; - clock-names = "ipg", "ahb", "per"; - status = "disabled"; - }; - - esdhc2: esdhc@53fb8000 { - compatible = "fsl,imx35-esdhc"; - reg = <0x53fb8000 0x4000>; - interrupts = <8>; - clocks = <&clks 9>, <&clks 8>, <&clks 44>; - clock-names = "ipg", "ahb", "per"; - status = "disabled"; - }; - - esdhc3: esdhc@53fbc000 { - compatible = "fsl,imx35-esdhc"; - reg = <0x53fbc000 0x4000>; - interrupts = <9>; - clocks = <&clks 9>, <&clks 8>, <&clks 45>; - clock-names = "ipg", "ahb", "per"; - status = "disabled"; - }; - - audmux: audmux@53fc4000 { - compatible = "fsl,imx35-audmux", "fsl,imx31-audmux"; - reg = <0x53fc4000 0x4000>; - status = "disabled"; - }; - - gpio1: gpio@53fcc000 { - compatible = "fsl,imx35-gpio", "fsl,imx31-gpio"; - reg = <0x53fcc000 0x4000>; - interrupts = <52>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@53fd0000 { - compatible = "fsl,imx35-gpio", "fsl,imx31-gpio"; - reg = <0x53fd0000 0x4000>; - interrupts = <51>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - sdma: sdma@53fd4000 { - compatible = "fsl,imx35-sdma"; - reg = <0x53fd4000 0x4000>; - clocks = <&clks 9>, <&clks 65>; - clock-names = "ipg", "ahb"; - #dma-cells = <3>; - interrupts = <34>; - fsl,sdma-ram-script-name = "imx/sdma/sdma-imx35.bin"; - }; - - wdog: wdog@53fdc000 { - compatible = "fsl,imx35-wdt", "fsl,imx21-wdt"; - reg = <0x53fdc000 0x4000>; - clocks = <&clks 74>; - clock-names = ""; - interrupts = <55>; - }; - - can1: can@53fe4000 { - compatible = "fsl,imx35-flexcan", "fsl,imx25-flexcan"; - reg = <0x53fe4000 0x1000>; - clocks = <&clks 33>, <&clks 33>; - clock-names = "ipg", "per"; - interrupts = <43>; - status = "disabled"; - }; - - can2: can@53fe8000 { - compatible = "fsl,imx35-flexcan", "fsl,imx25-flexcan"; - reg = <0x53fe8000 0x1000>; - clocks = <&clks 34>, <&clks 34>; - clock-names = "ipg", "per"; - interrupts = <44>; - status = "disabled"; - }; - - iim@53ff0000 { - compatible = "fsl,imx35-iim"; - reg = <0x53ff0000 0x4000>; - interrupts = <19>; - clocks = <&clks 80>; - }; - - usbotg: usb@53ff4000 { - compatible = "fsl,imx35-usb", "fsl,imx27-usb"; - reg = <0x53ff4000 0x0200>; - interrupts = <37>; - clocks = <&clks 9>, <&clks 73>, <&clks 28>; - clock-names = "ipg", "ahb", "per"; - fsl,usbmisc = <&usbmisc 0>; - fsl,usbphy = <&usbphy0>; - status = "disabled"; - }; - - usbhost1: usb@53ff4400 { - compatible = "fsl,imx35-usb", "fsl,imx27-usb"; - reg = <0x53ff4400 0x0200>; - interrupts = <35>; - clocks = <&clks 9>, <&clks 73>, <&clks 28>; - clock-names = "ipg", "ahb", "per"; - fsl,usbmisc = <&usbmisc 1>; - fsl,usbphy = <&usbphy1>; - dr_mode = "host"; - status = "disabled"; - }; - - usbmisc: usbmisc@53ff4600 { - #index-cells = <1>; - compatible = "fsl,imx35-usbmisc"; - reg = <0x53ff4600 0x00f>; - }; - }; - - emi@80000000 { /* External Memory Interface */ - compatible = "fsl,emi", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x80000000 0x40000000>; - ranges; - - nfc: nand@bb000000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "fsl,imx35-nand", "fsl,imx25-nand"; - reg = <0xbb000000 0x2000>; - clocks = <&clks 29>; - clock-names = ""; - interrupts = <33>; - status = "disabled"; - }; - - weim: weim@b8002000 { - #address-cells = <2>; - #size-cells = <1>; - clocks = <&clks 0>; - compatible = "fsl,imx35-weim", "fsl,imx27-weim"; - reg = <0xb8002000 0x1000>; - ranges = < - 0 0 0xa0000000 0x8000000 - 1 0 0xa8000000 0x8000000 - 2 0 0xb0000000 0x2000000 - 3 0 0xb2000000 0x2000000 - 4 0 0xb4000000 0x2000000 - 5 0 0xb6000000 0x2000000 - >; - status = "disabled"; - }; - }; - }; - - usbphy { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - usbphy0: usb-phy@0 { - reg = <0>; - compatible = "usb-nop-xceiv"; - #phy-cells = <0>; - }; - - usbphy1: usb-phy@1 { - reg = <1>; - compatible = "usb-nop-xceiv"; - #phy-cells = <0>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/imx50-evk.dts b/sys/gnu/dts/arm/imx50-evk.dts deleted file mode 100644 index a25da415cb0..00000000000 --- a/sys/gnu/dts/arm/imx50-evk.dts +++ /dev/null @@ -1,104 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// -// Copyright 2013 Greg Ungerer -// Copyright 2011 Freescale Semiconductor, Inc. -// Copyright 2011 Linaro Ltd. - -/dts-v1/; -#include "imx50.dtsi" - -/ { - model = "Freescale i.MX50 Evaluation Kit"; - compatible = "fsl,imx50-evk", "fsl,imx50"; - - memory@70000000 { - device_type = "memory"; - reg = <0x70000000 0x80000000>; - }; -}; - -&cspi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_cspi>; - cs-gpios = <&gpio4 11 0>, <&gpio4 13 0>; - status = "okay"; - - flash: m25p32@1 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "m25p32", "jedec,spi-nor"; - spi-max-frequency = <25000000>; - reg = <1>; - - partition@0 { - label = "bootloader"; - reg = <0x0 0x100000>; - read-only; - }; - - partition@100000 { - label = "kernel"; - reg = <0x100000 0x300000>; - }; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec>; - phy-mode = "rmii"; - phy-reset-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&iomuxc { - imx50-evk { - pinctrl_cspi: cspigrp { - fsl,pins = < - MX50_PAD_CSPI_SCLK__CSPI_SCLK 0x00 - MX50_PAD_CSPI_MISO__CSPI_MISO 0x00 - MX50_PAD_CSPI_MOSI__CSPI_MOSI 0x00 - MX50_PAD_CSPI_SS0__GPIO4_11 0xc4 - MX50_PAD_ECSPI1_MOSI__CSPI_SS1 0xf4 - >; - }; - - pinctrl_fec: fecgrp { - fsl,pins = < - MX50_PAD_SSI_RXFS__FEC_MDC 0x80 - MX50_PAD_SSI_RXC__FEC_MDIO 0x80 - MX50_PAD_DISP_D0__FEC_TX_CLK 0x80 - MX50_PAD_DISP_D1__FEC_RX_ERR 0x80 - MX50_PAD_DISP_D2__FEC_RX_DV 0x80 - MX50_PAD_DISP_D3__FEC_RDATA_1 0x80 - MX50_PAD_DISP_D4__FEC_RDATA_0 0x80 - MX50_PAD_DISP_D5__FEC_TX_EN 0x80 - MX50_PAD_DISP_D6__FEC_TDATA_1 0x80 - MX50_PAD_DISP_D7__FEC_TDATA_0 0x80 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX50_PAD_UART1_TXD__UART1_TXD_MUX 0x1e4 - MX50_PAD_UART1_RXD__UART1_RXD_MUX 0x1e4 - MX50_PAD_UART1_RTS__UART1_RTS 0x1e4 - MX50_PAD_UART1_CTS__UART1_CTS 0x1e4 - >; - }; - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&usbh1 { - status = "okay"; -}; - -&usbotg { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx50-kobo-aura.dts b/sys/gnu/dts/arm/imx50-kobo-aura.dts deleted file mode 100644 index a0eaf869b91..00000000000 --- a/sys/gnu/dts/arm/imx50-kobo-aura.dts +++ /dev/null @@ -1,258 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// Copyright 2019 Jonathan Neuschäfer -// -// The Kobo Aura e-book reader, model N514. The mainboard is marked as E606F0B. - -/dts-v1/; -#include "imx50.dtsi" -#include - -/ { - model = "Kobo Aura (N514)"; - compatible = "kobo,aura", "fsl,imx50"; - - chosen { - stdout-path = "serial1:115200n8"; - }; - - memory@70000000 { - device_type = "memory"; - reg = <0x70000000 0x10000000>; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_leds>; - - on { - label = "kobo_aura:orange:on"; - gpios = <&gpio6 24 GPIO_ACTIVE_LOW>; - panic-indicator; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpiokeys>; - - power { - label = "Power Button"; - gpios = <&gpio4 10 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - hallsensor { - label = "Hallsensor"; - gpios = <&gpio5 15 GPIO_ACTIVE_LOW>; - linux,code = ; - linux,input-type = ; - }; - - frontlight { - label = "Frontlight"; - gpios = <&gpio4 1 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - sd2_pwrseq: pwrseq { - compatible = "mmc-pwrseq-simple"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sd2_reset>; - reset-gpios = <&gpio4 17 GPIO_ACTIVE_LOW>; - }; - - sd2_vmmc: gpio-regulator { - compatible = "regulator-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sd2_vmmc>; - regulator-name = "vmmc"; - states = <3300000 0>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-gpio = <&gpio4 12 GPIO_ACTIVE_LOW>; - startup-delay-us = <100000>; - }; -}; - -&esdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sd1>; - max-frequency = <50000000>; - bus-width = <4>; - cd-gpios = <&gpio5 17 GPIO_ACTIVE_LOW>; - disable-wp; - status = "okay"; - - /* External µSD card */ -}; - -&esdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sd2>; - bus-width = <4>; - max-frequency = <50000000>; - disable-wp; - mmc-pwrseq = <&sd2_pwrseq>; - vmmc-supply = <&sd2_vmmc>; - status = "okay"; - - /* CyberTan WC121 SDIO WiFi (BCM43362) */ -}; - -&esdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sd3>; - bus-width = <8>; - non-removable; - max-frequency = <50000000>; - disable-wp; - status = "okay"; - - /* Internal eMMC */ -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - /* TODO: ektf2132 touch controller at 0x15 */ -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - /* TODO: TPS65185 PMIC for E Ink at 0x68 */ -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - /* TODO: embedded controller at 0x43 */ -}; - -&iomuxc { - pinctrl_gpiokeys: gpiokeys { - fsl,pins = < - MX50_PAD_CSPI_MISO__GPIO4_10 0x0 - MX50_PAD_SD2_D7__GPIO5_15 0x0 - MX50_PAD_KEY_ROW0__GPIO4_1 0x0 - >; - }; - - pinctrl_i2c1: i2c1 { - fsl,pins = < - MX50_PAD_I2C1_SCL__I2C1_SCL 0x400001fd - MX50_PAD_I2C1_SDA__I2C1_SDA 0x400001fd - >; - }; - - pinctrl_i2c2: i2c2 { - fsl,pins = < - MX50_PAD_I2C2_SCL__I2C2_SCL 0x400001fd - MX50_PAD_I2C2_SDA__I2C2_SDA 0x400001fd - >; - }; - - pinctrl_i2c3: i2c3 { - fsl,pins = < - MX50_PAD_I2C3_SCL__I2C3_SCL 0x400001fd - MX50_PAD_I2C3_SDA__I2C3_SDA 0x400001fd - >; - }; - - pinctrl_leds: leds { - fsl,pins = < - MX50_PAD_PWM1__GPIO6_24 0x0 - >; - }; - - pinctrl_sd1: sd1 { - fsl,pins = < - MX50_PAD_SD1_CMD__ESDHC1_CMD 0x1e4 - MX50_PAD_SD1_CLK__ESDHC1_CLK 0xd4 - MX50_PAD_SD1_D0__ESDHC1_DAT0 0x1d4 - MX50_PAD_SD1_D1__ESDHC1_DAT1 0x1d4 - MX50_PAD_SD1_D2__ESDHC1_DAT2 0x1d4 - MX50_PAD_SD1_D3__ESDHC1_DAT3 0x1d4 - - MX50_PAD_SD2_CD__GPIO5_17 0x0 - >; - }; - - pinctrl_sd2: sd2 { - fsl,pins = < - MX50_PAD_SD2_CMD__ESDHC2_CMD 0x1e4 - MX50_PAD_SD2_CLK__ESDHC2_CLK 0xd4 - MX50_PAD_SD2_D0__ESDHC2_DAT0 0x1d4 - MX50_PAD_SD2_D1__ESDHC2_DAT1 0x1d4 - MX50_PAD_SD2_D2__ESDHC2_DAT2 0x1d4 - MX50_PAD_SD2_D3__ESDHC2_DAT3 0x1d4 - >; - }; - - pinctrl_sd2_reset: sd2-reset { - fsl,pins = < - MX50_PAD_ECSPI2_MOSI__GPIO4_17 0x0 - >; - }; - - pinctrl_sd2_vmmc: sd2-vmmc { - fsl,pins = < - MX50_PAD_ECSPI1_SCLK__GPIO4_12 0x0 - >; - }; - - pinctrl_sd3: sd3 { - fsl,pins = < - MX50_PAD_SD3_CMD__ESDHC3_CMD 0x1e4 - MX50_PAD_SD3_CLK__ESDHC3_CLK 0xd4 - MX50_PAD_SD3_D0__ESDHC3_DAT0 0x1d4 - MX50_PAD_SD3_D1__ESDHC3_DAT1 0x1d4 - MX50_PAD_SD3_D2__ESDHC3_DAT2 0x1d4 - MX50_PAD_SD3_D3__ESDHC3_DAT3 0x1d4 - MX50_PAD_SD3_D4__ESDHC3_DAT4 0x1d4 - MX50_PAD_SD3_D5__ESDHC3_DAT5 0x1d4 - MX50_PAD_SD3_D6__ESDHC3_DAT6 0x1d4 - MX50_PAD_SD3_D7__ESDHC3_DAT7 0x1d4 - >; - }; - - pinctrl_uart2: uart2 { - fsl,pins = < - MX50_PAD_UART2_TXD__UART2_TXD_MUX 0x1e4 - MX50_PAD_UART2_RXD__UART2_RXD_MUX 0x1e4 - >; - }; - - pinctrl_usbphy: usbphy { - fsl,pins = < - MX50_PAD_ECSPI2_SS0__GPIO4_19 0x0 - >; - }; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&usbotg { - phy_type = "utmi_wide"; - dr_mode = "peripheral"; - status = "okay"; -}; - -&usbphy0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbphy>; - vbus-detect-gpio = <&gpio4 19 GPIO_ACTIVE_LOW>; -}; diff --git a/sys/gnu/dts/arm/imx50-pinfunc.h b/sys/gnu/dts/arm/imx50-pinfunc.h deleted file mode 100644 index 5e6b3024754..00000000000 --- a/sys/gnu/dts/arm/imx50-pinfunc.h +++ /dev/null @@ -1,919 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2013 Greg Ungerer - */ - -#ifndef __DTS_IMX50_PINFUNC_H -#define __DTS_IMX50_PINFUNC_H - -/* - * The pin function ID is a tuple of - * - */ -#define MX50_PAD_KEY_COL0__KPP_COL_0 0x020 0x2cc 0x000 0x0 0x0 -#define MX50_PAD_KEY_COL0__GPIO4_0 0x020 0x2cc 0x000 0x1 0x0 -#define MX50_PAD_KEY_COL0__EIM_NANDF_CLE 0x020 0x2cc 0x000 0x2 0x0 -#define MX50_PAD_KEY_COL0__CTI_TRIGIN7 0x020 0x2cc 0x000 0x6 0x0 -#define MX50_PAD_KEY_COL0__USBPHY1_TXREADY 0x020 0x2cc 0x000 0x7 0x0 -#define MX50_PAD_KEY_ROW0__KPP_ROW_0 0x024 0x2d0 0x000 0x0 0x0 -#define MX50_PAD_KEY_ROW0__GPIO4_1 0x024 0x2d0 0x000 0x1 0x0 -#define MX50_PAD_KEY_ROW0__EIM_NANDF_ALE 0x024 0x2d0 0x000 0x2 0x0 -#define MX50_PAD_KEY_ROW0__CTI_TRIGIN_ACK7 0x024 0x2d0 0x000 0x6 0x0 -#define MX50_PAD_KEY_ROW0__USBPHY1_RXVALID 0x024 0x2d0 0x000 0x7 0x0 -#define MX50_PAD_KEY_COL1__KPP_COL_1 0x028 0x2d4 0x000 0x0 0x0 -#define MX50_PAD_KEY_COL1__GPIO4_2 0x028 0x2d4 0x000 0x1 0x0 -#define MX50_PAD_KEY_COL1__EIM_NANDF_CEN_0 0x028 0x2d4 0x000 0x2 0x0 -#define MX50_PAD_KEY_COL1__CTI_TRIGOUT_ACK6 0x028 0x2d4 0x000 0x6 0x0 -#define MX50_PAD_KEY_COL1__USBPHY1_RXACTIVE 0x028 0x2d4 0x000 0x7 0x0 -#define MX50_PAD_KEY_ROW1__KPP_ROW_1 0x02c 0x2d8 0x000 0x0 0x0 -#define MX50_PAD_KEY_ROW1__GPIO4_3 0x02c 0x2d8 0x000 0x1 0x0 -#define MX50_PAD_KEY_ROW1__EIM_NANDF_CEN_1 0x02c 0x2d8 0x000 0x2 0x0 -#define MX50_PAD_KEY_ROW1__CTI_TRIGOUT_ACK7 0x02c 0x2d8 0x000 0x6 0x0 -#define MX50_PAD_KEY_ROW1__USBPHY1_RXERROR 0x02c 0x2d8 0x000 0x7 0x0 -#define MX50_PAD_KEY_COL2__KPP_COL_2 0x030 0x2dc 0x000 0x0 0x0 -#define MX50_PAD_KEY_COL2__GPIO4_4 0x030 0x2dc 0x000 0x1 0x0 -#define MX50_PAD_KEY_COL2__EIM_NANDF_CEN_2 0x030 0x2dc 0x000 0x2 0x0 -#define MX50_PAD_KEY_COL2__CTI_TRIGOUT6 0x030 0x2dc 0x000 0x6 0x0 -#define MX50_PAD_KEY_COL2__USBPHY1_SIECLOCK 0x030 0x2dc 0x000 0x7 0x0 -#define MX50_PAD_KEY_ROW2__KPP_ROW_2 0x034 0x2e0 0x000 0x0 0x0 -#define MX50_PAD_KEY_ROW2__GPIO4_5 0x034 0x2e0 0x000 0x1 0x0 -#define MX50_PAD_KEY_ROW2__EIM_NANDF_CEN_3 0x034 0x2e0 0x000 0x2 0x0 -#define MX50_PAD_KEY_ROW2__CTI_TRIGOUT7 0x034 0x2e0 0x000 0x6 0x0 -#define MX50_PAD_KEY_ROW2__USBPHY1_LINESTATE_0 0x034 0x2e0 0x000 0x7 0x0 -#define MX50_PAD_KEY_COL3__KPP_COL_3 0x038 0x2e4 0x000 0x0 0x0 -#define MX50_PAD_KEY_COL3__GPIO4_6 0x038 0x2e4 0x000 0x1 0x0 -#define MX50_PAD_KEY_COL3__EIM_NANDF_READY0 0x038 0x2e4 0x7b4 0x2 0x0 -#define MX50_PAD_KEY_COL3__SDMA_EXT_EVENT_0 0x038 0x2e4 0x7b8 0x6 0x0 -#define MX50_PAD_KEY_COL3__USBPHY1_LINESTATE_1 0x038 0x2e4 0x000 0x7 0x0 -#define MX50_PAD_KEY_ROW3__KPP_ROW_3 0x03c 0x2e8 0x000 0x0 0x0 -#define MX50_PAD_KEY_ROW3__GPIO4_7 0x03c 0x2e8 0x000 0x1 0x0 -#define MX50_PAD_KEY_ROW3__EIM_NANDF_DQS 0x03c 0x2e8 0x7b0 0x2 0x0 -#define MX50_PAD_KEY_ROW3__SDMA_EXT_EVENT_1 0x03c 0x2e8 0x7bc 0x6 0x0 -#define MX50_PAD_KEY_ROW3__USBPHY1_VBUSVALID 0x03c 0x2e8 0x000 0x7 0x0 -#define MX50_PAD_I2C1_SCL__I2C1_SCL 0x040 0x2ec 0x000 0x0 0x0 -#define MX50_PAD_I2C1_SCL__GPIO6_18 0x040 0x2ec 0x000 0x1 0x0 -#define MX50_PAD_I2C1_SCL__UART2_TXD_MUX 0x040 0x2ec 0x7cc 0x2 0x0 -#define MX50_PAD_I2C1_SDA__I2C1_SDA 0x044 0x2f0 0x000 0x0 0x0 -#define MX50_PAD_I2C1_SDA__GPIO6_19 0x044 0x2f0 0x000 0x1 0x0 -#define MX50_PAD_I2C1_SDA__UART2_RXD_MUX 0x044 0x2f0 0x7cc 0x2 0x1 -#define MX50_PAD_I2C2_SCL__I2C2_SCL 0x048 0x2f4 0x000 0x0 0x0 -#define MX50_PAD_I2C2_SCL__GPIO6_20 0x048 0x2f4 0x000 0x1 0x0 -#define MX50_PAD_I2C2_SCL__UART2_CTS 0x048 0x2f4 0x000 0x2 0x0 -#define MX50_PAD_I2C2_SDA__I2C2_SDA 0x04c 0x2f8 0x000 0x0 0x0 -#define MX50_PAD_I2C2_SDA__GPIO6_21 0x04c 0x2f8 0x000 0x1 0x0 -#define MX50_PAD_I2C2_SDA__UART2_RTS 0x04c 0x2f8 0x7c8 0x2 0x1 -#define MX50_PAD_I2C3_SCL__I2C3_SCL 0x050 0x2fc 0x000 0x0 0x0 -#define MX50_PAD_I2C3_SCL__GPIO6_22 0x050 0x2fc 0x000 0x1 0x0 -#define MX50_PAD_I2C3_SCL__FEC_MDC 0x050 0x2fc 0x000 0x2 0x0 -#define MX50_PAD_I2C3_SCL__GPC_PMIC_RDY 0x050 0x2fc 0x000 0x3 0x0 -#define MX50_PAD_I2C3_SCL__GPT_CAPIN1 0x050 0x2fc 0x000 0x5 0x0 -#define MX50_PAD_I2C3_SCL__OBSERVE_MUX_OBSRV_INT_OUT0 0x050 0x2fc 0x000 0x6 0x0 -#define MX50_PAD_I2C3_SCL__USBOH1_USBOTG_OC 0x050 0x2fc 0x7e8 0x7 0x0 -#define MX50_PAD_I2C3_SDA__I2C3_SDA 0x054 0x300 0x000 0x0 0x0 -#define MX50_PAD_I2C3_SDA__GPIO6_23 0x054 0x300 0x000 0x1 0x0 -#define MX50_PAD_I2C3_SDA__FEC_MDIO 0x054 0x300 0x774 0x2 0x0 -#define MX50_PAD_I2C3_SDA__TZIC_PWRFAIL_INT 0x054 0x300 0x000 0x3 0x0 -#define MX50_PAD_I2C3_SDA__SRTC_ALARM_DEB 0x054 0x300 0x000 0x4 0x0 -#define MX50_PAD_I2C3_SDA__GPT_CAPIN2 0x054 0x300 0x000 0x5 0x0 -#define MX50_PAD_I2C3_SDA__OBSERVE_MUX_OBSRV_INT_OUT1 0x054 0x300 0x000 0x6 0x0 -#define MX50_PAD_I2C3_SDA__USBOH1_USBOTG_PWR 0x054 0x300 0x000 0x7 0x0 -#define MX50_PAD_PWM1__PWM1_PWMO 0x058 0x304 0x000 0x0 0x0 -#define MX50_PAD_PWM1__GPIO6_24 0x058 0x304 0x000 0x1 0x0 -#define MX50_PAD_PWM1__USBOH1_USBOTG_OC 0x058 0x304 0x7e8 0x2 0x1 -#define MX50_PAD_PWM1__GPT_CMPOUT1 0x058 0x304 0x000 0x5 0x0 -#define MX50_PAD_PWM1__OBSERVE_MUX_OBSRV_INT_OUT2 0x058 0x304 0x000 0x6 0x0 -#define MX50_PAD_PWM1__SJC_FAIL 0x058 0x304 0x000 0x7 0x0 -#define MX50_PAD_PWM2__PWM2_PWMO 0x05c 0x308 0x000 0x0 0x0 -#define MX50_PAD_PWM2__GPIO6_25 0x05c 0x308 0x000 0x1 0x0 -#define MX50_PAD_PWM2__USBOH1_USBOTG_PWR 0x05c 0x308 0x000 0x2 0x0 -#define MX50_PAD_PWM2__GPT_CMPOUT2 0x05c 0x308 0x000 0x5 0x0 -#define MX50_PAD_PWM2__OBSERVE_MUX_OBSRV_INT_OUT3 0x05c 0x308 0x000 0x6 0x0 -#define MX50_PAD_PWM2__SRC_ANY_PU_RST 0x05c 0x308 0x000 0x7 0x0 -#define MX50_PAD_OWIRE__OWIRE_LINE 0x060 0x30c 0x000 0x0 0x0 -#define MX50_PAD_OWIRE__GPIO6_26 0x060 0x30c 0x000 0x1 0x0 -#define MX50_PAD_OWIRE__USBOH1_USBH1_OC 0x060 0x30c 0x000 0x2 0x0 -#define MX50_PAD_OWIRE__CCM_SSI_EXT1_CLK 0x060 0x30c 0x000 0x3 0x0 -#define MX50_PAD_OWIRE__EPDC_PWRIRQ 0x060 0x30c 0x000 0x4 0x0 -#define MX50_PAD_OWIRE__GPT_CMPOUT3 0x060 0x30c 0x000 0x5 0x0 -#define MX50_PAD_OWIRE__OBSERVE_MUX_OBSRV_INT_OUT4 0x060 0x30c 0x000 0x6 0x0 -#define MX50_PAD_OWIRE__SJC_JTAG_ACT 0x060 0x30c 0x000 0x7 0x0 -#define MX50_PAD_EPITO__EPIT1_EPITO 0x064 0x310 0x000 0x0 0x0 -#define MX50_PAD_EPITO__GPIO6_27 0x064 0x310 0x000 0x1 0x0 -#define MX50_PAD_EPITO__USBOH1_USBH1_PWR 0x064 0x310 0x000 0x2 0x0 -#define MX50_PAD_EPITO__CCM_SSI_EXT2_CLK 0x064 0x310 0x000 0x3 0x0 -#define MX50_PAD_EPITO__DPLLIP1_TOG_EN 0x064 0x310 0x000 0x4 0x0 -#define MX50_PAD_EPITO__GPT_CLK_IN 0x064 0x310 0x000 0x5 0x0 -#define MX50_PAD_EPITO__PMU_IRQ_B 0x064 0x310 0x000 0x6 0x0 -#define MX50_PAD_EPITO__SJC_DE_B 0x064 0x310 0x000 0x7 0x0 -#define MX50_PAD_WDOG__WDOG1_WDOG_B 0x068 0x314 0x000 0x0 0x0 -#define MX50_PAD_WDOG__GPIO6_28 0x068 0x314 0x000 0x1 0x0 -#define MX50_PAD_WDOG__WDOG1_WDOG_RST_B_DEB 0x068 0x314 0x000 0x2 0x0 -#define MX50_PAD_WDOG__CCM_XTAL32K 0x068 0x314 0x000 0x6 0x0 -#define MX50_PAD_WDOG__SJC_DONE 0x068 0x314 0x000 0x7 0x0 -#define MX50_PAD_SSI_TXFS__AUDMUX_AUD3_TXFS 0x06c 0x318 0x000 0x0 0x0 -#define MX50_PAD_SSI_TXFS__GPIO6_0 0x06c 0x318 0x000 0x1 0x0 -#define MX50_PAD_SSI_TXFS__SRC_BT_FUSE_RSV_1 0x06c 0x318 0x000 0x6 0x0 -#define MX50_PAD_SSI_TXFS__USBPHY1_DATAOUT_8 0x06c 0x318 0x000 0x7 0x0 -#define MX50_PAD_SSI_TXC__AUDMUX_AUD3_TXC 0x070 0x31c 0x000 0x0 0x0 -#define MX50_PAD_SSI_TXC__GPIO6_1 0x070 0x31c 0x000 0x1 0x0 -#define MX50_PAD_SSI_TXC__SRC_BT_FUSE_RSV_0 0x070 0x31c 0x000 0x6 0x0 -#define MX50_PAD_SSI_TXC__USBPHY1_DATAOUT_9 0x070 0x31c 0x000 0x7 0x0 -#define MX50_PAD_SSI_TXD__AUDMUX_AUD3_TXD 0x074 0x320 0x000 0x0 0x0 -#define MX50_PAD_SSI_TXD__GPIO6_2 0x074 0x320 0x000 0x1 0x0 -#define MX50_PAD_SSI_TXD__CSPI_RDY 0x074 0x320 0x6e8 0x4 0x0 -#define MX50_PAD_SSI_TXD__USBPHY1_DATAOUT_10 0x074 0x320 0x000 0x7 0x0 -#define MX50_PAD_SSI_RXD__AUDMUX_AUD3_RXD 0x078 0x324 0x000 0x0 0x0 -#define MX50_PAD_SSI_RXD__GPIO6_3 0x078 0x324 0x000 0x1 0x0 -#define MX50_PAD_SSI_RXD__CSPI_SS3 0x078 0x324 0x6f4 0x4 0x0 -#define MX50_PAD_SSI_RXD__USBPHY1_DATAOUT_11 0x078 0x324 0x000 0x7 0x0 -#define MX50_PAD_SSI_RXFS__AUDMUX_AUD3_RXFS 0x07c 0x328 0x000 0x0 0x0 -#define MX50_PAD_SSI_RXFS__GPIO6_4 0x07c 0x328 0x000 0x1 0x0 -#define MX50_PAD_SSI_RXFS__UART5_TXD_MUX 0x07c 0x328 0x7e4 0x2 0x0 -#define MX50_PAD_SSI_RXFS__EIM_WEIM_D_6 0x07c 0x328 0x804 0x3 0x0 -#define MX50_PAD_SSI_RXFS__CSPI_SS2 0x07c 0x328 0x6f0 0x4 0x0 -#define MX50_PAD_SSI_RXFS__FEC_COL 0x07c 0x328 0x770 0x5 0x0 -#define MX50_PAD_SSI_RXFS__FEC_MDC 0x07c 0x328 0x000 0x6 0x0 -#define MX50_PAD_SSI_RXFS__USBPHY1_DATAOUT_12 0x07c 0x328 0x000 0x7 0x0 -#define MX50_PAD_SSI_RXC__AUDMUX_AUD3_RXC 0x080 0x32c 0x000 0x0 0x0 -#define MX50_PAD_SSI_RXC__GPIO6_5 0x080 0x32c 0x000 0x1 0x0 -#define MX50_PAD_SSI_RXC__UART5_RXD_MUX 0x080 0x32c 0x7e4 0x2 0x1 -#define MX50_PAD_SSI_RXC__EIM_WEIM_D_7 0x080 0x32c 0x808 0x3 0x0 -#define MX50_PAD_SSI_RXC__CSPI_SS1 0x080 0x32c 0x6ec 0x4 0x0 -#define MX50_PAD_SSI_RXC__FEC_RX_CLK 0x080 0x32c 0x780 0x5 0x0 -#define MX50_PAD_SSI_RXC__FEC_MDIO 0x080 0x32c 0x774 0x6 0x1 -#define MX50_PAD_SSI_RXC__USBPHY1_DATAOUT_13 0x080 0x32c 0x000 0x7 0x0 -#define MX50_PAD_UART1_TXD__UART1_TXD_MUX 0x084 0x330 0x7c4 0x0 0x0 -#define MX50_PAD_UART1_TXD__GPIO6_6 0x084 0x330 0x000 0x1 0x0 -#define MX50_PAD_UART1_TXD__USBPHY1_DATAOUT_14 0x084 0x330 0x000 0x7 0x0 -#define MX50_PAD_UART1_RXD__UART1_RXD_MUX 0x088 0x334 0x7c4 0x0 0x1 -#define MX50_PAD_UART1_RXD__GPIO6_7 0x088 0x334 0x000 0x1 0x0 -#define MX50_PAD_UART1_RXD__USBPHY1_DATAOUT_15 0x088 0x334 0x000 0x7 0x0 -#define MX50_PAD_UART1_CTS__UART1_CTS 0x08c 0x338 0x000 0x0 0x0 -#define MX50_PAD_UART1_CTS__GPIO6_8 0x08c 0x338 0x000 0x1 0x0 -#define MX50_PAD_UART1_CTS__UART5_TXD_MUX 0x08c 0x338 0x7e4 0x2 0x2 -#define MX50_PAD_UART1_CTS__ESDHC4_DAT4 0x08c 0x338 0x760 0x4 0x0 -#define MX50_PAD_UART1_CTS__ESDHC4_CMD 0x08c 0x338 0x74c 0x5 0x0 -#define MX50_PAD_UART1_CTS__USBPHY2_DATAOUT_8 0x08c 0x338 0x000 0x7 0x0 -#define MX50_PAD_UART1_RTS__UART1_RTS 0x090 0x33c 0x7c0 0x0 0x3 -#define MX50_PAD_UART1_RTS__GPIO6_9 0x090 0x33c 0x000 0x1 0x0 -#define MX50_PAD_UART1_RTS__UART5_RXD_MUX 0x090 0x33c 0x7e4 0x2 0x3 -#define MX50_PAD_UART1_RTS__ESDHC4_DAT5 0x090 0x33c 0x764 0x4 0x0 -#define MX50_PAD_UART1_RTS__ESDHC4_CLK 0x090 0x33c 0x748 0x5 0x0 -#define MX50_PAD_UART1_RTS__USBPHY2_DATAOUT_9 0x090 0x33c 0x000 0x7 0x0 -#define MX50_PAD_UART2_TXD__UART2_TXD_MUX 0x094 0x340 0x7cc 0x0 0x2 -#define MX50_PAD_UART2_TXD__GPIO6_10 0x094 0x340 0x000 0x1 0x0 -#define MX50_PAD_UART2_TXD__ESDHC4_DAT6 0x094 0x340 0x768 0x4 0x0 -#define MX50_PAD_UART2_TXD__ESDHC4_DAT4 0x094 0x340 0x760 0x5 0x1 -#define MX50_PAD_UART2_TXD__USBPHY2_DATAOUT_10 0x094 0x340 0x000 0x7 0x0 -#define MX50_PAD_UART2_RXD__UART2_RXD_MUX 0x098 0x344 0x7cc 0x0 0x3 -#define MX50_PAD_UART2_RXD__GPIO6_11 0x098 0x344 0x000 0x1 0x0 -#define MX50_PAD_UART2_RXD__ESDHC4_DAT7 0x098 0x344 0x76c 0x4 0x0 -#define MX50_PAD_UART2_RXD__ESDHC4_DAT5 0x098 0x344 0x764 0x5 0x1 -#define MX50_PAD_UART2_RXD__USBPHY2_DATAOUT_11 0x098 0x344 0x000 0x7 0x0 -#define MX50_PAD_UART2_CTS__UART2_CTS 0x09c 0x348 0x000 0x0 0x0 -#define MX50_PAD_UART2_CTS__GPIO6_12 0x09c 0x348 0x000 0x1 0x0 -#define MX50_PAD_UART2_CTS__ESDHC4_CMD 0x09c 0x348 0x74c 0x4 0x1 -#define MX50_PAD_UART2_CTS__ESDHC4_DAT6 0x09c 0x348 0x768 0x5 0x1 -#define MX50_PAD_UART2_CTS__USBPHY2_DATAOUT_12 0x09c 0x348 0x000 0x7 0x0 -#define MX50_PAD_UART2_RTS__UART2_RTS 0x0a0 0x34c 0x7c8 0x0 0x2 -#define MX50_PAD_UART2_RTS__GPIO6_13 0x0a0 0x34c 0x000 0x1 0x0 -#define MX50_PAD_UART2_RTS__ESDHC4_CLK 0x0a0 0x34c 0x748 0x4 0x1 -#define MX50_PAD_UART2_RTS__ESDHC4_DAT7 0x0a0 0x34c 0x76c 0x5 0x1 -#define MX50_PAD_UART2_RTS__USBPHY2_DATAOUT_13 0x0a0 0x34c 0x000 0x7 0x0 -#define MX50_PAD_UART3_TXD__UART3_TXD_MUX 0x0a4 0x350 0x7d4 0x0 0x0 -#define MX50_PAD_UART3_TXD__GPIO6_14 0x0a4 0x350 0x000 0x1 0x0 -#define MX50_PAD_UART3_TXD__ESDHC1_DAT4 0x0a4 0x350 0x000 0x3 0x0 -#define MX50_PAD_UART3_TXD__ESDHC4_DAT0 0x0a4 0x350 0x000 0x4 0x0 -#define MX50_PAD_UART3_TXD__ESDHC2_WP 0x0a4 0x350 0x744 0x5 0x0 -#define MX50_PAD_UART3_TXD__EIM_WEIM_D_12 0x0a4 0x350 0x81c 0x6 0x0 -#define MX50_PAD_UART3_TXD__USBPHY2_DATAOUT_14 0x0a4 0x350 0x000 0x7 0x0 -#define MX50_PAD_UART3_RXD__UART3_RXD_MUX 0x0a8 0x354 0x7d4 0x0 0x1 -#define MX50_PAD_UART3_RXD__GPIO6_15 0x0a8 0x354 0x000 0x1 0x0 -#define MX50_PAD_UART3_RXD__ESDHC1_DAT5 0x0a8 0x354 0x000 0x3 0x0 -#define MX50_PAD_UART3_RXD__ESDHC4_DAT1 0x0a8 0x354 0x754 0x4 0x0 -#define MX50_PAD_UART3_RXD__ESDHC2_CD 0x0a8 0x354 0x740 0x5 0x0 -#define MX50_PAD_UART3_RXD__EIM_WEIM_D_13 0x0a8 0x354 0x820 0x6 0x0 -#define MX50_PAD_UART3_RXD__USBPHY2_DATAOUT_15 0x0a8 0x354 0x000 0x7 0x0 -#define MX50_PAD_UART4_TXD__UART4_TXD_MUX 0x0ac 0x358 0x7dc 0x0 0x0 -#define MX50_PAD_UART4_TXD__GPIO6_16 0x0ac 0x358 0x000 0x1 0x0 -#define MX50_PAD_UART4_TXD__UART3_CTS 0x0ac 0x358 0x7d0 0x2 0x0 -#define MX50_PAD_UART4_TXD__ESDHC1_DAT6 0x0ac 0x358 0x000 0x3 0x0 -#define MX50_PAD_UART4_TXD__ESDHC4_DAT2 0x0ac 0x358 0x758 0x4 0x0 -#define MX50_PAD_UART4_TXD__ESDHC2_LCTL 0x0ac 0x358 0x000 0x5 0x0 -#define MX50_PAD_UART4_TXD__EIM_WEIM_D_14 0x0ac 0x358 0x824 0x6 0x0 -#define MX50_PAD_UART4_RXD__UART4_RXD_MUX 0x0b0 0x35c 0x7dc 0x0 0x1 -#define MX50_PAD_UART4_RXD__GPIO6_17 0x0b0 0x35c 0x000 0x1 0x0 -#define MX50_PAD_UART4_RXD__UART3_RTS 0x0b0 0x35c 0x7d0 0x2 0x1 -#define MX50_PAD_UART4_RXD__ESDHC1_DAT7 0x0b0 0x35c 0x000 0x3 0x0 -#define MX50_PAD_UART4_RXD__ESDHC4_DAT3 0x0b0 0x35c 0x75c 0x4 0x0 -#define MX50_PAD_UART4_RXD__ESDHC1_LCTL 0x0b0 0x35c 0x000 0x5 0x0 -#define MX50_PAD_UART4_RXD__EIM_WEIM_D_15 0x0b0 0x35c 0x828 0x6 0x0 -#define MX50_PAD_CSPI_SCLK__CSPI_SCLK 0x0b4 0x360 0x000 0x0 0x0 -#define MX50_PAD_CSPI_SCLK__GPIO4_8 0x0b4 0x360 0x000 0x1 0x0 -#define MX50_PAD_CSPI_MOSI__CSPI_MOSI 0x0b8 0x364 0x000 0x0 0x0 -#define MX50_PAD_CSPI_MOSI__GPIO4_9 0x0b8 0x364 0x000 0x1 0x0 -#define MX50_PAD_CSPI_MISO__CSPI_MISO 0x0bc 0x368 0x000 0x0 0x0 -#define MX50_PAD_CSPI_MISO__GPIO4_10 0x0bc 0x368 0x000 0x1 0x0 -#define MX50_PAD_CSPI_SS0__CSPI_SS0 0x0c0 0x36c 0x000 0x0 0x0 -#define MX50_PAD_CSPI_SS0__GPIO4_11 0x0c0 0x36c 0x000 0x1 0x0 -#define MX50_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x0c4 0x370 0x000 0x0 0x0 -#define MX50_PAD_ECSPI1_SCLK__GPIO4_12 0x0c4 0x370 0x000 0x1 0x0 -#define MX50_PAD_ECSPI1_SCLK__CSPI_RDY 0x0c4 0x370 0x6e8 0x2 0x1 -#define MX50_PAD_ECSPI1_SCLK__ECSPI2_RDY 0x0c4 0x370 0x000 0x3 0x0 -#define MX50_PAD_ECSPI1_SCLK__UART3_RTS 0x0c4 0x370 0x7d0 0x4 0x2 -#define MX50_PAD_ECSPI1_SCLK__EPDC_SDCE_6 0x0c4 0x370 0x000 0x5 0x0 -#define MX50_PAD_ECSPI1_SCLK__EIM_WEIM_D_8 0x0c4 0x370 0x80c 0x7 0x0 -#define MX50_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x0c8 0x374 0x000 0x0 0x0 -#define MX50_PAD_ECSPI1_MOSI__GPIO4_13 0x0c8 0x374 0x000 0x1 0x0 -#define MX50_PAD_ECSPI1_MOSI__CSPI_SS1 0x0c8 0x374 0x6ec 0x2 0x1 -#define MX50_PAD_ECSPI1_MOSI__ECSPI2_SS1 0x0c8 0x374 0x000 0x3 0x0 -#define MX50_PAD_ECSPI1_MOSI__UART3_CTS 0x0c8 0x374 0x000 0x4 0x0 -#define MX50_PAD_ECSPI1_MOSI__EPDC_SDCE_7 0x0c8 0x374 0x000 0x5 0x0 -#define MX50_PAD_ECSPI1_MOSI__EIM_WEIM_D_9 0x0c8 0x374 0x810 0x7 0x0 -#define MX50_PAD_ECSPI1_MISO__ECSPI1_MISO 0x0cc 0x378 0x000 0x0 0x0 -#define MX50_PAD_ECSPI1_MISO__GPIO4_14 0x0cc 0x378 0x000 0x1 0x0 -#define MX50_PAD_ECSPI1_MISO__CSPI_SS2 0x0cc 0x378 0x6f0 0x2 0x1 -#define MX50_PAD_ECSPI1_MISO__ECSPI2_SS2 0x0cc 0x378 0x000 0x3 0x0 -#define MX50_PAD_ECSPI1_MISO__UART4_RTS 0x0cc 0x378 0x7d8 0x4 0x0 -#define MX50_PAD_ECSPI1_MISO__EPDC_SDCE_8 0x0cc 0x378 0x000 0x5 0x0 -#define MX50_PAD_ECSPI1_MISO__EIM_WEIM_D_10 0x0cc 0x378 0x814 0x7 0x0 -#define MX50_PAD_ECSPI1_SS0__ECSPI1_SS0 0x0d0 0x37c 0x000 0x0 0x0 -#define MX50_PAD_ECSPI1_SS0__GPIO4_15 0x0d0 0x37c 0x000 0x1 0x0 -#define MX50_PAD_ECSPI1_SS0__CSPI_SS3 0x0d0 0x37c 0x6f4 0x2 0x1 -#define MX50_PAD_ECSPI1_SS0__ECSPI2_SS3 0x0d0 0x37c 0x000 0x3 0x0 -#define MX50_PAD_ECSPI1_SS0__UART4_CTS 0x0d0 0x37c 0x000 0x4 0x0 -#define MX50_PAD_ECSPI1_SS0__EPDC_SDCE_9 0x0d0 0x37c 0x000 0x5 0x0 -#define MX50_PAD_ECSPI1_SS0__EIM_WEIM_D_11 0x0d0 0x37c 0x818 0x7 0x0 -#define MX50_PAD_ECSPI2_SCLK__ECSPI2_SCLK 0x0d4 0x380 0x000 0x0 0x0 -#define MX50_PAD_ECSPI2_SCLK__GPIO4_16 0x0d4 0x380 0x000 0x1 0x0 -#define MX50_PAD_ECSPI2_SCLK__ELCDIF_WR_RWN 0x0d4 0x380 0x000 0x2 0x0 -#define MX50_PAD_ECSPI2_SCLK__ECSPI1_RDY 0x0d4 0x380 0x000 0x3 0x0 -#define MX50_PAD_ECSPI2_SCLK__UART5_RTS 0x0d4 0x380 0x7e0 0x4 0x0 -#define MX50_PAD_ECSPI2_SCLK__ELCDIF_DOTCLK 0x0d4 0x380 0x000 0x5 0x0 -#define MX50_PAD_ECSPI2_SCLK__EIM_NANDF_CEN_4 0x0d4 0x380 0x000 0x6 0x0 -#define MX50_PAD_ECSPI2_SCLK__EIM_WEIM_D_8 0x0d4 0x380 0x80c 0x7 0x1 -#define MX50_PAD_ECSPI2_MOSI__ECSPI2_MOSI 0x0d8 0x384 0x000 0x0 0x0 -#define MX50_PAD_ECSPI2_MOSI__GPIO4_17 0x0d8 0x384 0x000 0x1 0x0 -#define MX50_PAD_ECSPI2_MOSI__ELCDIF_RE_E 0x0d8 0x384 0x000 0x2 0x0 -#define MX50_PAD_ECSPI2_MOSI__ECSPI1_SS1 0x0d8 0x384 0x000 0x3 0x0 -#define MX50_PAD_ECSPI2_MOSI__UART5_CTS 0x0d8 0x384 0x7e0 0x4 0x1 -#define MX50_PAD_ECSPI2_MOSI__ELCDIF_ENABLE 0x0d8 0x384 0x000 0x5 0x0 -#define MX50_PAD_ECSPI2_MOSI__EIM_NANDF_CEN_5 0x0d8 0x384 0x000 0x6 0x0 -#define MX50_PAD_ECSPI2_MOSI__EIM_WEIM_D_9 0x0d8 0x384 0x810 0x7 0x1 -#define MX50_PAD_ECSPI2_MISO__ECSPI2_MISO 0x0dc 0x388 0x000 0x0 0x0 -#define MX50_PAD_ECSPI2_MISO__GPIO4_18 0x0dc 0x388 0x000 0x1 0x0 -#define MX50_PAD_ECSPI2_MISO__ELCDIF_RS 0x0dc 0x388 0x000 0x2 0x0 -#define MX50_PAD_ECSPI2_MISO__ECSPI1_SS2 0x0dc 0x388 0x000 0x3 0x0 -#define MX50_PAD_ECSPI2_MISO__UART5_TXD_MUX 0x0dc 0x388 0x7e4 0x4 0x4 -#define MX50_PAD_ECSPI2_MISO__ELCDIF_VSYNC 0x0dc 0x388 0x73c 0x5 0x0 -#define MX50_PAD_ECSPI2_MISO__EIM_NANDF_CEN_6 0x0dc 0x388 0x000 0x6 0x0 -#define MX50_PAD_ECSPI2_MISO__EIM_WEIM_D_10 0x0dc 0x388 0x814 0x7 0x1 -#define MX50_PAD_ECSPI2_SS0__ECSPI2_SS0 0x0e0 0x38c 0x000 0x0 0x0 -#define MX50_PAD_ECSPI2_SS0__GPIO4_19 0x0e0 0x38c 0x000 0x1 0x0 -#define MX50_PAD_ECSPI2_SS0__ELCDIF_CS 0x0e0 0x38c 0x000 0x2 0x0 -#define MX50_PAD_ECSPI2_SS0__ECSPI2_SS3 0x0e0 0x38c 0x000 0x3 0x0 -#define MX50_PAD_ECSPI2_SS0__UART5_RXD_MUX 0x0e0 0x38c 0x7e4 0x4 0x5 -#define MX50_PAD_ECSPI2_SS0__ELCDIF_HSYNC 0x0e0 0x38c 0x6f8 0x5 0x0 -#define MX50_PAD_ECSPI2_SS0__EIM_NANDF_CEN_7 0x0e0 0x38c 0x000 0x6 0x0 -#define MX50_PAD_ECSPI2_SS0__EIM_WEIM_D_11 0x0e0 0x38c 0x818 0x7 0x1 -#define MX50_PAD_SD1_CLK__ESDHC1_CLK 0x0e4 0x390 0x000 0x0 0x0 -#define MX50_PAD_SD1_CLK__GPIO5_0 0x0e4 0x390 0x000 0x1 0x0 -#define MX50_PAD_SD1_CLK__CCM_CLKO 0x0e4 0x390 0x000 0x7 0x0 -#define MX50_PAD_SD1_CMD__ESDHC1_CMD 0x0e8 0x394 0x000 0x0 0x0 -#define MX50_PAD_SD1_CMD__GPIO5_1 0x0e8 0x394 0x000 0x1 0x0 -#define MX50_PAD_SD1_CMD__CCM_CLKO2 0x0e8 0x394 0x000 0x7 0x0 -#define MX50_PAD_SD1_D0__ESDHC1_DAT0 0x0ec 0x398 0x000 0x0 0x0 -#define MX50_PAD_SD1_D0__GPIO5_2 0x0ec 0x398 0x000 0x1 0x0 -#define MX50_PAD_SD1_D0__CCM_PLL1_BYP 0x0ec 0x398 0x6dc 0x7 0x0 -#define MX50_PAD_SD1_D1__ESDHC1_DAT1 0x0f0 0x39c 0x000 0x0 0x0 -#define MX50_PAD_SD1_D1__GPIO5_3 0x0f0 0x39c 0x000 0x1 0x0 -#define MX50_PAD_SD1_D1__CCM_PLL2_BYP 0x0f0 0x39c 0x000 0x7 0x0 -#define MX50_PAD_SD1_D2__ESDHC1_DAT2 0x0f4 0x3a0 0x000 0x0 0x0 -#define MX50_PAD_SD1_D2__GPIO5_4 0x0f4 0x3a0 0x000 0x1 0x0 -#define MX50_PAD_SD1_D2__CCM_PLL3_BYP 0x0f4 0x3a0 0x6e4 0x7 0x0 -#define MX50_PAD_SD1_D3__ESDHC1_DAT3 0x0f8 0x3a4 0x000 0x0 0x0 -#define MX50_PAD_SD1_D3__GPIO5_5 0x0f8 0x3a4 0x000 0x1 0x0 -#define MX50_PAD_SD2_CLK__ESDHC2_CLK 0x0fc 0x3a8 0x000 0x0 0x0 -#define MX50_PAD_SD2_CLK__GPIO5_6 0x0fc 0x3a8 0x000 0x1 0x0 -#define MX50_PAD_SD2_CLK__MSHC_SCLK 0x0fc 0x3a8 0x000 0x2 0x0 -#define MX50_PAD_SD2_CMD__ESDHC2_CMD 0x100 0x3ac 0x000 0x0 0x0 -#define MX50_PAD_SD2_CMD__GPIO5_7 0x100 0x3ac 0x000 0x1 0x0 -#define MX50_PAD_SD2_CMD__MSHC_BS 0x100 0x3ac 0x000 0x2 0x0 -#define MX50_PAD_SD2_D0__ESDHC2_DAT0 0x104 0x3b0 0x000 0x0 0x0 -#define MX50_PAD_SD2_D0__GPIO5_8 0x104 0x3b0 0x000 0x1 0x0 -#define MX50_PAD_SD2_D0__MSHC_DATA_0 0x104 0x3b0 0x000 0x2 0x0 -#define MX50_PAD_SD2_D0__KPP_COL_4 0x104 0x3b0 0x790 0x3 0x0 -#define MX50_PAD_SD2_D1__ESDHC2_DAT1 0x108 0x3b4 0x000 0x0 0x0 -#define MX50_PAD_SD2_D1__GPIO5_9 0x108 0x3b4 0x000 0x1 0x0 -#define MX50_PAD_SD2_D1__MSHC_DATA_1 0x108 0x3b4 0x000 0x2 0x0 -#define MX50_PAD_SD2_D1__KPP_ROW_4 0x108 0x3b4 0x7a0 0x3 0x0 -#define MX50_PAD_SD2_D2__ESDHC2_DAT2 0x10c 0x3b8 0x000 0x0 0x0 -#define MX50_PAD_SD2_D2__GPIO5_10 0x10c 0x3b8 0x000 0x1 0x0 -#define MX50_PAD_SD2_D2__MSHC_DATA_2 0x10c 0x3b8 0x000 0x2 0x0 -#define MX50_PAD_SD2_D2__KPP_COL_5 0x10c 0x3b8 0x794 0x3 0x0 -#define MX50_PAD_SD2_D3__ESDHC2_DAT3 0x110 0x3bc 0x000 0x0 0x0 -#define MX50_PAD_SD2_D3__GPIO5_11 0x110 0x3bc 0x000 0x1 0x0 -#define MX50_PAD_SD2_D3__MSHC_DATA_3 0x110 0x3bc 0x000 0x2 0x0 -#define MX50_PAD_SD2_D3__KPP_ROW_5 0x110 0x3bc 0x7a4 0x3 0x0 -#define MX50_PAD_SD2_D4__ESDHC2_DAT4 0x114 0x3c0 0x000 0x0 0x0 -#define MX50_PAD_SD2_D4__GPIO5_12 0x114 0x3c0 0x000 0x1 0x0 -#define MX50_PAD_SD2_D4__AUDMUX_AUD4_RXFS 0x114 0x3c0 0x6d0 0x2 0x0 -#define MX50_PAD_SD2_D4__KPP_COL_6 0x114 0x3c0 0x798 0x3 0x0 -#define MX50_PAD_SD2_D4__EIM_WEIM_D_0 0x114 0x3c0 0x7ec 0x4 0x0 -#define MX50_PAD_SD2_D4__CCM_CCM_OUT_0 0x114 0x3c0 0x000 0x7 0x0 -#define MX50_PAD_SD2_D5__ESDHC2_DAT5 0x118 0x3c4 0x000 0x0 0x0 -#define MX50_PAD_SD2_D5__GPIO5_13 0x118 0x3c4 0x000 0x1 0x0 -#define MX50_PAD_SD2_D5__AUDMUX_AUD4_RXC 0x118 0x3c4 0x6cc 0x2 0x0 -#define MX50_PAD_SD2_D5__KPP_ROW_6 0x118 0x3c4 0x7a8 0x3 0x0 -#define MX50_PAD_SD2_D5__EIM_WEIM_D_1 0x118 0x3c4 0x7f0 0x4 0x0 -#define MX50_PAD_SD2_D5__CCM_CCM_OUT_1 0x118 0x3c4 0x000 0x7 0x0 -#define MX50_PAD_SD2_D6__ESDHC2_DAT6 0x11c 0x3c8 0x000 0x0 0x0 -#define MX50_PAD_SD2_D6__GPIO5_14 0x11c 0x3c8 0x000 0x1 0x0 -#define MX50_PAD_SD2_D6__AUDMUX_AUD4_RXD 0x11c 0x3c8 0x6c4 0x2 0x0 -#define MX50_PAD_SD2_D6__KPP_COL_7 0x11c 0x3c8 0x79c 0x3 0x0 -#define MX50_PAD_SD2_D6__EIM_WEIM_D_2 0x11c 0x3c8 0x7f4 0x4 0x0 -#define MX50_PAD_SD2_D6__CCM_CCM_OUT_2 0x11c 0x3c8 0x000 0x7 0x0 -#define MX50_PAD_SD2_D7__ESDHC2_DAT7 0x120 0x3cc 0x000 0x0 0x0 -#define MX50_PAD_SD2_D7__GPIO5_15 0x120 0x3cc 0x000 0x1 0x0 -#define MX50_PAD_SD2_D7__AUDMUX_AUD4_TXFS 0x120 0x3cc 0x6d8 0x2 0x0 -#define MX50_PAD_SD2_D7__KPP_ROW_7 0x120 0x3cc 0x7ac 0x3 0x0 -#define MX50_PAD_SD2_D7__EIM_WEIM_D_3 0x120 0x3cc 0x7f8 0x4 0x0 -#define MX50_PAD_SD2_D7__CCM_STOP 0x120 0x3cc 0x000 0x7 0x0 -#define MX50_PAD_SD2_WP__ESDHC2_WP 0x124 0x3d0 0x744 0x0 0x1 -#define MX50_PAD_SD2_WP__GPIO5_16 0x124 0x3d0 0x000 0x1 0x0 -#define MX50_PAD_SD2_WP__AUDMUX_AUD4_TXD 0x124 0x3d0 0x6c8 0x2 0x0 -#define MX50_PAD_SD2_WP__EIM_WEIM_D_4 0x124 0x3d0 0x7fc 0x4 0x0 -#define MX50_PAD_SD2_WP__CCM_WAIT 0x124 0x3d0 0x000 0x7 0x0 -#define MX50_PAD_SD2_CD__ESDHC2_CD 0x128 0x3d4 0x740 0x0 0x1 -#define MX50_PAD_SD2_CD__GPIO5_17 0x128 0x3d4 0x000 0x1 0x0 -#define MX50_PAD_SD2_CD__AUDMUX_AUD4_TXC 0x128 0x3d4 0x6d4 0x2 0x0 -#define MX50_PAD_SD2_CD__EIM_WEIM_D_5 0x128 0x3d4 0x800 0x4 0x0 -#define MX50_PAD_SD2_CD__CCM_REF_EN_B 0x128 0x3d4 0x000 0x7 0x0 -#define MX50_PAD_DISP_D0__ELCDIF_DAT_0 0x12c 0x40c 0x6fc 0x0 0x0 -#define MX50_PAD_DISP_D0__GPIO2_0 0x12c 0x40c 0x000 0x1 0x0 -#define MX50_PAD_DISP_D0__FEC_TX_CLK 0x12c 0x40c 0x78c 0x2 0x0 -#define MX50_PAD_DISP_D0__EIM_WEIM_A_16 0x12c 0x40c 0x000 0x3 0x0 -#define MX50_PAD_DISP_D0__SDMA_DEBUG_PC_0 0x12c 0x40c 0x000 0x6 0x0 -#define MX50_PAD_DISP_D0__USBPHY1_VSTATUS_0 0x12c 0x40c 0x000 0x7 0x0 -#define MX50_PAD_DISP_D1__ELCDIF_DAT_1 0x130 0x410 0x700 0x0 0x0 -#define MX50_PAD_DISP_D1__GPIO2_1 0x130 0x410 0x000 0x1 0x0 -#define MX50_PAD_DISP_D1__FEC_RX_ERR 0x130 0x410 0x788 0x2 0x0 -#define MX50_PAD_DISP_D1__EIM_WEIM_A_17 0x130 0x410 0x000 0x3 0x0 -#define MX50_PAD_DISP_D1__SDMA_DEBUG_PC_1 0x130 0x410 0x000 0x6 0x0 -#define MX50_PAD_DISP_D1__USBPHY1_VSTATUS_1 0x130 0x410 0x000 0x7 0x0 -#define MX50_PAD_DISP_D2__ELCDIF_DAT_2 0x134 0x414 0x704 0x0 0x0 -#define MX50_PAD_DISP_D2__GPIO2_2 0x134 0x414 0x000 0x1 0x0 -#define MX50_PAD_DISP_D2__FEC_RX_DV 0x134 0x414 0x784 0x2 0x0 -#define MX50_PAD_DISP_D2__EIM_WEIM_A_18 0x134 0x414 0x000 0x3 0x0 -#define MX50_PAD_DISP_D2__SDMA_DEBUG_PC_2 0x134 0x414 0x000 0x6 0x0 -#define MX50_PAD_DISP_D2__USBPHY1_VSTATUS_2 0x134 0x414 0x000 0x7 0x0 -#define MX50_PAD_DISP_D3__ELCDIF_DAT_3 0x138 0x418 0x708 0x0 0x0 -#define MX50_PAD_DISP_D3__GPIO2_3 0x138 0x418 0x000 0x1 0x0 -#define MX50_PAD_DISP_D3__FEC_RDATA_1 0x138 0x418 0x77c 0x2 0x0 -#define MX50_PAD_DISP_D3__EIM_WEIM_A_19 0x138 0x418 0x000 0x3 0x0 -#define MX50_PAD_DISP_D3__FEC_COL 0x138 0x418 0x770 0x4 0x1 -#define MX50_PAD_DISP_D3__SDMA_DEBUG_PC_3 0x138 0x418 0x000 0x6 0x0 -#define MX50_PAD_DISP_D3__USBPHY1_VSTATUS_3 0x138 0x418 0x000 0x7 0x0 -#define MX50_PAD_DISP_D4__ELCDIF_DAT_4 0x13c 0x41c 0x70c 0x0 0x0 -#define MX50_PAD_DISP_D4__GPIO2_4 0x13c 0x41c 0x000 0x1 0x0 -#define MX50_PAD_DISP_D4__FEC_RDATA_0 0x13c 0x41c 0x778 0x2 0x0 -#define MX50_PAD_DISP_D4__EIM_WEIM_A_20 0x13c 0x41c 0x000 0x3 0x0 -#define MX50_PAD_DISP_D4__SDMA_DEBUG_PC_4 0x13c 0x41c 0x000 0x6 0x0 -#define MX50_PAD_DISP_D4__USBPHY1_VSTATUS_4 0x13c 0x41c 0x000 0x7 0x0 -#define MX50_PAD_DISP_D5__ELCDIF_DAT_5 0x140 0x420 0x710 0x0 0x0 -#define MX50_PAD_DISP_D5__GPIO2_5 0x140 0x420 0x000 0x1 0x0 -#define MX50_PAD_DISP_D5__FEC_TX_EN 0x140 0x420 0x000 0x2 0x0 -#define MX50_PAD_DISP_D5__EIM_WEIM_A_21 0x140 0x420 0x000 0x3 0x0 -#define MX50_PAD_DISP_D5__SDMA_DEBUG_PC_5 0x140 0x420 0x000 0x6 0x0 -#define MX50_PAD_DISP_D5__USBPHY1_VSTATUS_5 0x140 0x420 0x000 0x7 0x0 -#define MX50_PAD_DISP_D6__ELCDIF_DAT_6 0x144 0x424 0x714 0x0 0x0 -#define MX50_PAD_DISP_D6__GPIO2_6 0x144 0x424 0x000 0x1 0x0 -#define MX50_PAD_DISP_D6__FEC_TDATA_1 0x144 0x424 0x000 0x2 0x0 -#define MX50_PAD_DISP_D6__EIM_WEIM_A_22 0x144 0x424 0x000 0x3 0x0 -#define MX50_PAD_DISP_D6__FEC_RX_CLK 0x144 0x424 0x780 0x4 0x1 -#define MX50_PAD_DISP_D6__SDMA_DEBUG_PC_6 0x144 0x424 0x000 0x6 0x0 -#define MX50_PAD_DISP_D6__USBPHY1_VSTATUS_6 0x144 0x424 0x000 0x7 0x0 -#define MX50_PAD_DISP_D7__ELCDIF_DAT_7 0x148 0x428 0x718 0x0 0x0 -#define MX50_PAD_DISP_D7__GPIO2_7 0x148 0x428 0x000 0x1 0x0 -#define MX50_PAD_DISP_D7__FEC_TDATA_0 0x148 0x428 0x000 0x2 0x0 -#define MX50_PAD_DISP_D7__EIM_WEIM_A_23 0x148 0x428 0x000 0x3 0x0 -#define MX50_PAD_DISP_D7__SDMA_DEBUG_PC_7 0x148 0x428 0x000 0x6 0x0 -#define MX50_PAD_DISP_D7__USBPHY1_VSTATUS_7 0x148 0x428 0x000 0x7 0x0 -#define MX50_PAD_DISP_WR__ELCDIF_WR_RWN 0x14c 0x42c 0x000 0x0 0x0 -#define MX50_PAD_DISP_WR__GPIO2_16 0x14c 0x42c 0x000 0x1 0x0 -#define MX50_PAD_DISP_WR__ELCDIF_DOTCLK 0x14c 0x42c 0x000 0x2 0x0 -#define MX50_PAD_DISP_WR__EIM_WEIM_A_24 0x14c 0x42c 0x000 0x3 0x0 -#define MX50_PAD_DISP_WR__SDMA_DEBUG_PC_8 0x14c 0x42c 0x000 0x6 0x0 -#define MX50_PAD_DISP_WR__USBPHY1_AVALID 0x14c 0x42c 0x000 0x7 0x0 -#define MX50_PAD_DISP_RD__ELCDIF_RD_E 0x150 0x430 0x000 0x0 0x0 -#define MX50_PAD_DISP_RD__GPIO2_19 0x150 0x430 0x000 0x1 0x0 -#define MX50_PAD_DISP_RD__ELCDIF_ENABLE 0x150 0x430 0x000 0x2 0x0 -#define MX50_PAD_DISP_RD__EIM_WEIM_A_25 0x150 0x430 0x000 0x3 0x0 -#define MX50_PAD_DISP_RD__SDMA_DEBUG_PC_9 0x150 0x430 0x000 0x6 0x0 -#define MX50_PAD_DISP_RD__USBPHY1_BVALID 0x150 0x430 0x000 0x7 0x0 -#define MX50_PAD_DISP_RS__ELCDIF_RS 0x154 0x434 0x000 0x0 0x0 -#define MX50_PAD_DISP_RS__GPIO2_17 0x154 0x434 0x000 0x1 0x0 -#define MX50_PAD_DISP_RS__ELCDIF_VSYNC 0x154 0x434 0x73c 0x2 0x1 -#define MX50_PAD_DISP_RS__EIM_WEIM_A_26 0x154 0x434 0x000 0x3 0x0 -#define MX50_PAD_DISP_RS__SDMA_DEBUG_PC_10 0x154 0x434 0x000 0x6 0x0 -#define MX50_PAD_DISP_RS__USBPHY1_ENDSESSION 0x154 0x434 0x000 0x7 0x0 -#define MX50_PAD_DISP_CS__ELCDIF_CS 0x158 0x438 0x000 0x0 0x0 -#define MX50_PAD_DISP_CS__GPIO2_21 0x158 0x438 0x000 0x1 0x0 -#define MX50_PAD_DISP_CS__ELCDIF_HSYNC 0x158 0x438 0x6f8 0x2 0x1 -#define MX50_PAD_DISP_CS__EIM_WEIM_A_27 0x158 0x438 0x000 0x3 0x0 -#define MX50_PAD_DISP_CS__EIM_WEIM_CS_3 0x158 0x438 0x000 0x4 0x0 -#define MX50_PAD_DISP_CS__SDMA_DEBUG_PC_11 0x158 0x438 0x000 0x6 0x0 -#define MX50_PAD_DISP_CS__USBPHY1_IDDIG 0x158 0x438 0x000 0x7 0x0 -#define MX50_PAD_DISP_BUSY__ELCDIF_BUSY 0x15c 0x43c 0x6f8 0x0 0x2 -#define MX50_PAD_DISP_BUSY__GPIO2_18 0x15c 0x43c 0x000 0x1 0x0 -#define MX50_PAD_DISP_BUSY__EIM_WEIM_CS_3 0x15c 0x43c 0x000 0x4 0x0 -#define MX50_PAD_DISP_BUSY__SDMA_DEBUG_PC_12 0x15c 0x43c 0x000 0x6 0x0 -#define MX50_PAD_DISP_BUSY__USBPHY2_HOSTDISCONNECT 0x15c 0x43c 0x000 0x7 0x0 -#define MX50_PAD_DISP_RESET__ELCDIF_RESET 0x160 0x440 0x000 0x0 0x0 -#define MX50_PAD_DISP_RESET__GPIO2_20 0x160 0x440 0x000 0x1 0x0 -#define MX50_PAD_DISP_RESET__EIM_WEIM_CS_3 0x160 0x440 0x000 0x4 0x0 -#define MX50_PAD_DISP_RESET__SDMA_DEBUG_PC_13 0x160 0x440 0x000 0x6 0x0 -#define MX50_PAD_DISP_RESET__USBPHY2_BISTOK 0x160 0x440 0x000 0x7 0x0 -#define MX50_PAD_SD3_CMD__ESDHC3_CMD 0x164 0x444 0x000 0x0 0x0 -#define MX50_PAD_SD3_CMD__GPIO5_18 0x164 0x444 0x000 0x1 0x0 -#define MX50_PAD_SD3_CMD__EIM_NANDF_WRN 0x164 0x444 0x000 0x2 0x0 -#define MX50_PAD_SD3_CMD__SSP_CMD 0x164 0x444 0x000 0x3 0x0 -#define MX50_PAD_SD3_CLK__ESDHC3_CLK 0x168 0x448 0x000 0x0 0x0 -#define MX50_PAD_SD3_CLK__GPIO5_19 0x168 0x448 0x000 0x1 0x0 -#define MX50_PAD_SD3_CLK__EIM_NANDF_RDN 0x168 0x448 0x000 0x2 0x0 -#define MX50_PAD_SD3_CLK__SSP_CLK 0x168 0x448 0x000 0x3 0x0 -#define MX50_PAD_SD3_D0__ESDHC3_DAT0 0x16c 0x44c 0x000 0x0 0x0 -#define MX50_PAD_SD3_D0__GPIO5_20 0x16c 0x44c 0x000 0x1 0x0 -#define MX50_PAD_SD3_D0__EIM_NANDF_D_4 0x16c 0x44c 0x000 0x2 0x0 -#define MX50_PAD_SD3_D0__SSP_D0 0x16c 0x44c 0x000 0x3 0x0 -#define MX50_PAD_SD3_D0__CCM_PLL1_BYP 0x16c 0x44c 0x6dc 0x7 0x1 -#define MX50_PAD_SD3_D1__ESDHC3_DAT1 0x170 0x450 0x000 0x0 0x0 -#define MX50_PAD_SD3_D1__GPIO5_21 0x170 0x450 0x000 0x1 0x0 -#define MX50_PAD_SD3_D1__EIM_NANDF_D_5 0x170 0x450 0x000 0x2 0x0 -#define MX50_PAD_SD3_D1__SSP_D1 0x170 0x450 0x000 0x3 0x0 -#define MX50_PAD_SD3_D1__CCM_PLL2_BYP 0x170 0x450 0x000 0x7 0x0 -#define MX50_PAD_SD3_D2__ESDHC3_DAT2 0x174 0x454 0x000 0x0 0x0 -#define MX50_PAD_SD3_D2__GPIO5_22 0x174 0x454 0x000 0x1 0x0 -#define MX50_PAD_SD3_D2__EIM_NANDF_D_6 0x174 0x454 0x000 0x2 0x0 -#define MX50_PAD_SD3_D2__SSP_D2 0x174 0x454 0x000 0x3 0x0 -#define MX50_PAD_SD3_D2__CCM_PLL3_BYP 0x174 0x454 0x6e4 0x7 0x1 -#define MX50_PAD_SD3_D3__ESDHC3_DAT3 0x178 0x458 0x000 0x0 0x0 -#define MX50_PAD_SD3_D3__GPIO5_23 0x178 0x458 0x000 0x1 0x0 -#define MX50_PAD_SD3_D3__EIM_NANDF_D_7 0x178 0x458 0x000 0x2 0x0 -#define MX50_PAD_SD3_D3__SSP_D3 0x178 0x458 0x000 0x3 0x0 -#define MX50_PAD_SD3_D4__ESDHC3_DAT4 0x17c 0x45c 0x000 0x0 0x0 -#define MX50_PAD_SD3_D4__GPIO5_24 0x17c 0x45c 0x000 0x1 0x0 -#define MX50_PAD_SD3_D4__EIM_NANDF_D_0 0x17c 0x45c 0x000 0x2 0x0 -#define MX50_PAD_SD3_D4__SSP_D4 0x17c 0x45c 0x000 0x3 0x0 -#define MX50_PAD_SD3_D5__ESDHC3_DAT5 0x180 0x460 0x000 0x0 0x0 -#define MX50_PAD_SD3_D5__GPIO5_25 0x180 0x460 0x000 0x1 0x0 -#define MX50_PAD_SD3_D5__EIM_NANDF_D_1 0x180 0x460 0x000 0x2 0x0 -#define MX50_PAD_SD3_D5__SSP_D5 0x180 0x460 0x000 0x3 0x0 -#define MX50_PAD_SD3_D6__ESDHC3_DAT6 0x184 0x464 0x000 0x0 0x0 -#define MX50_PAD_SD3_D6__GPIO5_26 0x184 0x464 0x000 0x1 0x0 -#define MX50_PAD_SD3_D6__EIM_NANDF_D_2 0x184 0x464 0x000 0x2 0x0 -#define MX50_PAD_SD3_D6__SSP_D6 0x184 0x464 0x000 0x3 0x0 -#define MX50_PAD_SD3_D7__ESDHC3_DAT7 0x188 0x468 0x000 0x0 0x0 -#define MX50_PAD_SD3_D7__GPIO5_27 0x188 0x468 0x000 0x1 0x0 -#define MX50_PAD_SD3_D7__EIM_NANDF_D_3 0x188 0x468 0x000 0x2 0x0 -#define MX50_PAD_SD3_D7__SSP_D7 0x188 0x468 0x000 0x3 0x0 -#define MX50_PAD_SD3_WP__ESDHC3_WP 0x18c 0x46C 0x000 0x0 0x0 -#define MX50_PAD_SD3_WP__GPIO5_28 0x18c 0x46C 0x000 0x1 0x0 -#define MX50_PAD_SD3_WP__EIM_NANDF_RESETN 0x18c 0x46C 0x000 0x2 0x0 -#define MX50_PAD_SD3_WP__SSP_CD 0x18c 0x46C 0x000 0x3 0x0 -#define MX50_PAD_SD3_WP__ESDHC4_LCTL 0x18c 0x46C 0x000 0x4 0x0 -#define MX50_PAD_SD3_WP__EIM_WEIM_CS_3 0x18c 0x46C 0x000 0x5 0x0 -#define MX50_PAD_DISP_D8__ELCDIF_DAT_8 0x190 0x470 0x71c 0x0 0x0 -#define MX50_PAD_DISP_D8__GPIO2_8 0x190 0x470 0x000 0x1 0x0 -#define MX50_PAD_DISP_D8__EIM_NANDF_CLE 0x190 0x470 0x000 0x2 0x0 -#define MX50_PAD_DISP_D8__ESDHC1_LCTL 0x190 0x470 0x000 0x3 0x0 -#define MX50_PAD_DISP_D8__ESDHC4_CMD 0x190 0x470 0x74c 0x4 0x2 -#define MX50_PAD_DISP_D8__KPP_COL_4 0x190 0x470 0x790 0x5 0x1 -#define MX50_PAD_DISP_D8__FEC_TX_CLK 0x190 0x470 0x78c 0x6 0x1 -#define MX50_PAD_DISP_D8__USBPHY1_DATAOUT_0 0x190 0x470 0x000 0x7 0x0 -#define MX50_PAD_DISP_D9__ELCDIF_DAT_9 0x194 0x474 0x720 0x0 0x0 -#define MX50_PAD_DISP_D9__GPIO2_9 0x194 0x474 0x000 0x1 0x0 -#define MX50_PAD_DISP_D9__EIM_NANDF_ALE 0x194 0x474 0x000 0x2 0x0 -#define MX50_PAD_DISP_D9__ESDHC2_LCTL 0x194 0x474 0x000 0x3 0x0 -#define MX50_PAD_DISP_D9__ESDHC4_CLK 0x194 0x474 0x748 0x4 0x2 -#define MX50_PAD_DISP_D9__KPP_ROW_4 0x194 0x474 0x7a0 0x5 0x1 -#define MX50_PAD_DISP_D9__FEC_RX_ER 0x194 0x474 0x788 0x6 0x1 -#define MX50_PAD_DISP_D9__USBPHY1_DATAOUT_1 0x194 0x474 0x000 0x7 0x0 -#define MX50_PAD_DISP_D10__ELCDIF_DAT_10 0x198 0x478 0x724 0x0 0x0 -#define MX50_PAD_DISP_D10__GPIO2_10 0x198 0x478 0x000 0x1 0x0 -#define MX50_PAD_DISP_D10__EIM_NANDF_CEN_0 0x198 0x478 0x000 0x2 0x0 -#define MX50_PAD_DISP_D10__ESDHC3_LCTL 0x198 0x478 0x000 0x3 0x0 -#define MX50_PAD_DISP_D10__ESDHC4_DAT0 0x198 0x478 0x000 0x4 0x0 -#define MX50_PAD_DISP_D10__KPP_COL_5 0x198 0x478 0x794 0x5 0x1 -#define MX50_PAD_DISP_D10__FEC_RX_DV 0x198 0x478 0x784 0x6 0x1 -#define MX50_PAD_DISP_D10__USBPHY1_DATAOUT_2 0x198 0x478 0x000 0x7 0x0 -#define MX50_PAD_DISP_D11__ELCDIF_DAT_11 0x19c 0x47c 0x728 0x0 0x0 -#define MX50_PAD_DISP_D11__GPIO2_11 0x19c 0x47c 0x000 0x1 0x0 -#define MX50_PAD_DISP_D11__EIM_NANDF_CEN_1 0x19c 0x47c 0x000 0x2 0x0 -#define MX50_PAD_DISP_D11__ESDHC4_DAT1 0x19c 0x47c 0x754 0x4 0x1 -#define MX50_PAD_DISP_D11__KPP_ROW_5 0x19c 0x47c 0x7a4 0x5 0x1 -#define MX50_PAD_DISP_D11__FEC_RDATA_1 0x19c 0x47c 0x77c 0x6 0x1 -#define MX50_PAD_DISP_D11__USBPHY1_DATAOUT_3 0x19c 0x47c 0x000 0x7 0x0 -#define MX50_PAD_DISP_D12__ELCDIF_DAT_12 0x1a0 0x480 0x72c 0x0 0x0 -#define MX50_PAD_DISP_D12__GPIO2_12 0x1a0 0x480 0x000 0x1 0x0 -#define MX50_PAD_DISP_D12__EIM_NANDF_CEN_2 0x1a0 0x480 0x000 0x2 0x0 -#define MX50_PAD_DISP_D12__ESDHC1_CD 0x1a0 0x480 0x000 0x3 0x0 -#define MX50_PAD_DISP_D12__ESDHC4_DAT2 0x1a0 0x480 0x758 0x4 0x1 -#define MX50_PAD_DISP_D12__KPP_COL_6 0x1a0 0x480 0x798 0x5 0x1 -#define MX50_PAD_DISP_D12__FEC_RDATA_0 0x1a0 0x480 0x778 0x6 0x1 -#define MX50_PAD_DISP_D12__USBPHY1_DATAOUT_4 0x1a0 0x480 0x000 0x7 0x0 -#define MX50_PAD_DISP_D13__ELCDIF_DAT_13 0x1a4 0x484 0x730 0x0 0x0 -#define MX50_PAD_DISP_D13__GPIO2_13 0x1a4 0x484 0x000 0x1 0x0 -#define MX50_PAD_DISP_D13__EIM_NANDF_CEN_3 0x1a4 0x484 0x000 0x2 0x0 -#define MX50_PAD_DISP_D13__ESDHC3_CD 0x1a4 0x484 0x000 0x3 0x0 -#define MX50_PAD_DISP_D13__ESDHC4_DAT3 0x1a4 0x484 0x75c 0x4 0x1 -#define MX50_PAD_DISP_D13__KPP_ROW_6 0x1a4 0x484 0x7a8 0x5 0x1 -#define MX50_PAD_DISP_D13__FEC_TX_EN 0x1a4 0x484 0x000 0x6 0x0 -#define MX50_PAD_DISP_D13__USBPHY1_DATAOUT_5 0x1a4 0x484 0x000 0x7 0x0 -#define MX50_PAD_DISP_D14__ELCDIF_DAT_14 0x1a8 0x488 0x734 0x0 0x0 -#define MX50_PAD_DISP_D14__GPIO2_14 0x1a8 0x488 0x000 0x1 0x0 -#define MX50_PAD_DISP_D14__EIM_NANDF_READY0 0x1a8 0x488 0x7b4 0x2 0x1 -#define MX50_PAD_DISP_D14__ESDHC1_WP 0x1a8 0x488 0x000 0x3 0x0 -#define MX50_PAD_DISP_D14__ESDHC4_WP 0x1a8 0x488 0x000 0x4 0x0 -#define MX50_PAD_DISP_D14__KPP_COL_7 0x1a8 0x488 0x79c 0x5 0x1 -#define MX50_PAD_DISP_D14__FEC_TDATA_1 0x1a8 0x488 0x000 0x6 0x0 -#define MX50_PAD_DISP_D14__USBPHY1_DATAOUT_6 0x1a8 0x488 0x000 0x7 0x0 -#define MX50_PAD_DISP_D15__ELCDIF_DAT_15 0x1ac 0x48c 0x738 0x0 0x0 -#define MX50_PAD_DISP_D15__GPIO2_15 0x1ac 0x48c 0x000 0x1 0x0 -#define MX50_PAD_DISP_D15__EIM_NANDF_DQS 0x1ac 0x48c 0x7b0 0x2 0x1 -#define MX50_PAD_DISP_D15__ESDHC3_RST 0x1ac 0x48c 0x000 0x3 0x0 -#define MX50_PAD_DISP_D15__ESDHC4_CD 0x1ac 0x48c 0x000 0x4 0x0 -#define MX50_PAD_DISP_D15__KPP_ROW_7 0x1ac 0x48c 0x7ac 0x5 0x1 -#define MX50_PAD_DISP_D15__FEC_TDATA_0 0x1ac 0x48c 0x000 0x6 0x0 -#define MX50_PAD_DISP_D15__USBPHY1_DATAOUT_7 0x1ac 0x48c 0x000 0x7 0x0 -#define MX50_PAD_EPDC_D0__EPDC_SDDO_0 0x1b0 0x54c 0x000 0x0 0x0 -#define MX50_PAD_EPDC_D0__GPIO3_0 0x1b0 0x54c 0x000 0x1 0x0 -#define MX50_PAD_EPDC_D0__EIM_WEIM_D_0 0x1b0 0x54c 0x7ec 0x2 0x1 -#define MX50_PAD_EPDC_D0__ELCDIF_RS 0x1b0 0x54c 0x000 0x3 0x0 -#define MX50_PAD_EPDC_D0__ELCDIF_DOTCLK 0x1b0 0x54c 0x000 0x4 0x0 -#define MX50_PAD_EPDC_D0__SDMA_DEBUG_EVT_CHN_LINES_0 0x1b0 0x54c 0x000 0x6 0x0 -#define MX50_PAD_EPDC_D0__USBPHY2_DATAOUT_0 0x1b0 0x54c 0x000 0x7 0x0 -#define MX50_PAD_EPDC_D1__EPDC_SDDO_1 0x1b4 0x550 0x000 0x0 0x0 -#define MX50_PAD_EPDC_D1__GPIO3_1 0x1b4 0x550 0x000 0x1 0x0 -#define MX50_PAD_EPDC_D1__EIM_WEIM_D_1 0x1b4 0x550 0x7f0 0x2 0x1 -#define MX50_PAD_EPDC_D1__ELCDIF_CS 0x1b4 0x550 0x000 0x3 0x0 -#define MX50_PAD_EPDC_D1__ELCDIF_ENABLE 0x1b4 0x550 0x000 0x4 0x0 -#define MX50_PAD_EPDC_D1__SDMA_DEBUG_EVT_CHN_LINES_1 0x1b4 0x550 0x000 0x6 0x0 -#define MX50_PAD_EPDC_D1__USBPHY2_DATAOUT_1 0x1b4 0x550 0x000 0x7 0x0 -#define MX50_PAD_EPDC_D2__EPDC_SDDO_2 0x1b8 0x554 0x000 0x0 0x0 -#define MX50_PAD_EPDC_D2__GPIO3_2 0x1b8 0x554 0x000 0x1 0x0 -#define MX50_PAD_EPDC_D2__EIM_WEIM_D_2 0x1b8 0x554 0x7f4 0x2 0x1 -#define MX50_PAD_EPDC_D2__ELCDIF_WR_RWN 0x1b8 0x554 0x000 0x3 0x0 -#define MX50_PAD_EPDC_D2__ELCDIF_VSYNC 0x1b8 0x554 0x73c 0x4 0x2 -#define MX50_PAD_EPDC_D2__SDMA_DEBUG_EVT_CHN_LINES_2 0x1b8 0x554 0x000 0x6 0x0 -#define MX50_PAD_EPDC_D2__USBPHY2_DATAOUT_2 0x1b8 0x554 0x000 0x7 0x0 -#define MX50_PAD_EPDC_D3__EPDC_SDDO_3 0x1bc 0x558 0x000 0x0 0x0 -#define MX50_PAD_EPDC_D3__GPIO3_3 0x1bc 0x558 0x000 0x1 0x0 -#define MX50_PAD_EPDC_D3__EIM_WEIM_D_3 0x1bc 0x558 0x7f8 0x2 0x1 -#define MX50_PAD_EPDC_D3__ELCDIF_RD_E 0x1bc 0x558 0x000 0x3 0x0 -#define MX50_PAD_EPDC_D3__ELCDIF_HSYNC 0x1bc 0x558 0x6f8 0x4 0x3 -#define MX50_PAD_EPDC_D3__SDMA_DEBUG_EVT_CHN_LINES_3 0x1bc 0x558 0x000 0x6 0x0 -#define MX50_PAD_EPDC_D3__USBPHY2_DATAOUT_3 0x1bc 0x558 0x000 0x7 0x0 -#define MX50_PAD_EPDC_D4__EPDC_SDDO_4 0x1c0 0x55c 0x000 0x0 0x0 -#define MX50_PAD_EPDC_D4__GPIO3_4 0x1c0 0x55c 0x000 0x1 0x0 -#define MX50_PAD_EPDC_D4__EIM_WEIM_D_4 0x1c0 0x55c 0x7fc 0x2 0x1 -#define MX50_PAD_EPDC_D4__SDMA_DEBUG_EVT_CHN_LINES_4 0x1c0 0x55c 0x000 0x6 0x0 -#define MX50_PAD_EPDC_D4__USBPHY2_DATAOUT_4 0x1c0 0x55c 0x000 0x7 0x0 -#define MX50_PAD_EPDC_D5__EPDC_SDDO_5 0x1c4 0x560 0x000 0x0 0x0 -#define MX50_PAD_EPDC_D5__GPIO3_5 0x1c4 0x560 0x000 0x1 0x0 -#define MX50_PAD_EPDC_D5__EIM_WEIM_D_5 0x1c4 0x560 0x800 0x2 0x1 -#define MX50_PAD_EPDC_D5__SDMA_DEBUG_EVT_CHN_LINES_5 0x1c4 0x560 0x000 0x6 0x0 -#define MX50_PAD_EPDC_D5__USBPHY2_DATAOUT_5 0x1c4 0x560 0x000 0x7 0x0 -#define MX50_PAD_EPDC_D6__EPDC_SDDO_6 0x1c8 0x564 0x000 0x0 0x0 -#define MX50_PAD_EPDC_D6__GPIO3_6 0x1c8 0x564 0x000 0x1 0x0 -#define MX50_PAD_EPDC_D6__EIM_WEIM_D_6 0x1c8 0x564 0x804 0x2 0x1 -#define MX50_PAD_EPDC_D6__SDMA_DEBUG_EVT_CHN_LINES_6 0x1c8 0x564 0x000 0x6 0x0 -#define MX50_PAD_EPDC_D6__USBPHY2_DATAOUT_6 0x1c8 0x564 0x000 0x7 0x0 -#define MX50_PAD_EPDC_D7__EPDC_SDDO_7 0x1cc 0x568 0x000 0x0 0x0 -#define MX50_PAD_EPDC_D7__GPIO3_7 0x1cc 0x568 0x000 0x1 0x0 -#define MX50_PAD_EPDC_D7__EIM_WEIM_D_7 0x1cc 0x568 0x808 0x2 0x1 -#define MX50_PAD_EPDC_D7__SDMA_DEBUG_EVT_CHN_LINES_7 0x1cc 0x568 0x000 0x6 0x0 -#define MX50_PAD_EPDC_D7__USBPHY2_DATAOUT_7 0x1cc 0x568 0x000 0x7 0x0 -#define MX50_PAD_EPDC_D8__EPDC_SDDO_8 0x1d0 0x56c 0x000 0x0 0x0 -#define MX50_PAD_EPDC_D8__GPIO3_8 0x1d0 0x56c 0x000 0x1 0x0 -#define MX50_PAD_EPDC_D8__EIM_WEIM_D_8 0x1d0 0x56c 0x80c 0x2 0x2 -#define MX50_PAD_EPDC_D8__ELCDIF_DAT_24 0x1d0 0x56c 0x000 0x3 0x0 -#define MX50_PAD_EPDC_D8__SDMA_DEBUG_MATCHED_DMBUS 0x1d0 0x56c 0x000 0x6 0x0 -#define MX50_PAD_EPDC_D8__USBPHY2_VSTATUS_0 0x1d0 0x56c 0x000 0x7 0x0 -#define MX50_PAD_EPDC_D9__EPDC_SDDO_9 0x1d4 0x570 0x000 0x0 0x0 -#define MX50_PAD_EPDC_D9__GPIO3_9 0x1d4 0x570 0x000 0x1 0x0 -#define MX50_PAD_EPDC_D9__EIM_WEIM_D_9 0x1d4 0x570 0x810 0x2 0x2 -#define MX50_PAD_EPDC_D9__ELCDIF_DAT_25 0x1d4 0x570 0x000 0x3 0x0 -#define MX50_PAD_EPDC_D9__SDMA_DEBUG_EVENT_CHANNEL_SEL 0x1d4 0x570 0x000 0x6 0x0 -#define MX50_PAD_EPDC_D9__USBPHY2_VSTATUS_1 0x1d4 0x570 0x000 0x7 0x0 -#define MX50_PAD_EPDC_D10__EPDC_SDDO_10 0x1d8 0x574 0x000 0x0 0x0 -#define MX50_PAD_EPDC_D10__GPIO3_10 0x1d8 0x574 0x000 0x1 0x0 -#define MX50_PAD_EPDC_D10__EIM_WEIM_D_10 0x1d8 0x574 0x814 0x2 0x2 -#define MX50_PAD_EPDC_D10__ELCDIF_DAT_26 0x1d8 0x574 0x000 0x3 0x0 -#define MX50_PAD_EPDC_D10__SDMA_DEBUG_EVENT_CHANNEL_0 0x1d8 0x574 0x000 0x6 0x0 -#define MX50_PAD_EPDC_D10__USBPHY2_VSTATUS_2 0x1d8 0x574 0x000 0x7 0x0 -#define MX50_PAD_EPDC_D11__EPDC_SDDO_11 0x1dc 0x578 0x000 0x0 0x0 -#define MX50_PAD_EPDC_D11__GPIO3_11 0x1dc 0x578 0x000 0x1 0x0 -#define MX50_PAD_EPDC_D11__EIM_WEIM_D_11 0x1dc 0x578 0x818 0x2 0x2 -#define MX50_PAD_EPDC_D11__ELCDIF_DAT_27 0x1dc 0x578 0x000 0x3 0x0 -#define MX50_PAD_EPDC_D11__SDMA_DEBUG_EVENT_CHANNEL_1 0x1dc 0x578 0x000 0x6 0x0 -#define MX50_PAD_EPDC_D11__USBPHY2_VSTATUS_3 0x1dc 0x578 0x000 0x7 0x0 -#define MX50_PAD_EPDC_D12__EPDC_SDDO_12 0x1e0 0x57c 0x000 0x0 0x0 -#define MX50_PAD_EPDC_D12__GPIO3_12 0x1e0 0x57c 0x000 0x1 0x0 -#define MX50_PAD_EPDC_D12__EIM_WEIM_D_12 0x1e0 0x57c 0x81c 0x2 0x1 -#define MX50_PAD_EPDC_D12__ELCDIF_DAT_28 0x1e0 0x57c 0x000 0x3 0x0 -#define MX50_PAD_EPDC_D12__SDMA_DEBUG_EVENT_CHANNEL_2 0x1e0 0x57c 0x000 0x6 0x0 -#define MX50_PAD_EPDC_D12__USBPHY2_VSTATUS_4 0x1e0 0x57c 0x000 0x7 0x0 -#define MX50_PAD_EPDC_D13__EPDC_SDDO_13 0x1e4 0x580 0x000 0x0 0x0 -#define MX50_PAD_EPDC_D13__GPIO3_13 0x1e4 0x580 0x000 0x1 0x0 -#define MX50_PAD_EPDC_D13__EIM_WEIM_D_13 0x1e4 0x580 0x820 0x2 0x1 -#define MX50_PAD_EPDC_D13__ELCDIF_DAT_29 0x1e4 0x580 0x000 0x3 0x0 -#define MX50_PAD_EPDC_D13__SDMA_DEBUG_EVENT_CHANNEL_3 0x1e4 0x580 0x000 0x6 0x0 -#define MX50_PAD_EPDC_D13__USBPHY2_VSTATUS_5 0x1e4 0x580 0x000 0x7 0x0 -#define MX50_PAD_EPDC_D14__EPDC_SDDO_14 0x1e8 0x584 0x000 0x0 0x0 -#define MX50_PAD_EPDC_D14__GPIO3_14 0x1e8 0x584 0x000 0x1 0x0 -#define MX50_PAD_EPDC_D14__EIM_WEIM_D_14 0x1e8 0x584 0x824 0x2 0x1 -#define MX50_PAD_EPDC_D14__ELCDIF_DAT_30 0x1e8 0x584 0x000 0x3 0x0 -#define MX50_PAD_EPDC_D14__AUDMUX_AUD6_TXD 0x1e8 0x584 0x000 0x4 0x0 -#define MX50_PAD_EPDC_D14__SDMA_DEBUG_EVENT_CHANNEL_4 0x1e8 0x584 0x000 0x6 0x0 -#define MX50_PAD_EPDC_D14__USBPHY2_VSTATUS_6 0x1e8 0x584 0x000 0x7 0x0 -#define MX50_PAD_EPDC_D15__EPDC_SDDO_15 0x1ec 0x588 0x000 0x0 0x0 -#define MX50_PAD_EPDC_D15__GPIO3_15 0x1ec 0x588 0x000 0x1 0x0 -#define MX50_PAD_EPDC_D15__EIM_WEIM_D_15 0x1ec 0x588 0x828 0x2 0x1 -#define MX50_PAD_EPDC_D15__ELCDIF_DAT_31 0x1ec 0x588 0x000 0x3 0x0 -#define MX50_PAD_EPDC_D15__AUDMUX_AUD6_TXC 0x1ec 0x588 0x000 0x4 0x0 -#define MX50_PAD_EPDC_D15__SDMA_DEBUG_EVENT_CHANNEL_5 0x1ec 0x588 0x000 0x6 0x0 -#define MX50_PAD_EPDC_D15__USBPHY2_VSTATUS_7 0x1ec 0x588 0x000 0x7 0x0 -#define MX50_PAD_EPDC_GDCLK__EPDC_GDCLK 0x1f0 0x58c 0x000 0x0 0x0 -#define MX50_PAD_EPDC_GDCLK__GPIO3_16 0x1f0 0x58c 0x000 0x1 0x0 -#define MX50_PAD_EPDC_GDCLK__EIM_WEIM_D_16 0x1f0 0x58c 0x000 0x2 0x0 -#define MX50_PAD_EPDC_GDCLK__ELCDIF_DAT_16 0x1f0 0x58c 0x000 0x3 0x0 -#define MX50_PAD_EPDC_GDCLK__AUDMUX_AUD6_TXFS 0x1f0 0x58c 0x000 0x4 0x0 -#define MX50_PAD_EPDC_GDCLK__SDMA_DEBUG_CORE_STATE_0 0x1f0 0x58c 0x000 0x6 0x0 -#define MX50_PAD_EPDC_GDCLK__USBPHY2_BISTOK 0x1f0 0x58c 0x000 0x7 0x0 -#define MX50_PAD_EPDC_GDSP__EPCD_GDSP 0x1f4 0x590 0x000 0x0 0x0 -#define MX50_PAD_EPDC_GDSP__GPIO3_17 0x1f4 0x590 0x000 0x1 0x0 -#define MX50_PAD_EPDC_GDSP__EIM_WEIM_D_17 0x1f4 0x590 0x000 0x2 0x0 -#define MX50_PAD_EPDC_GDSP__ELCDIF_DAT_17 0x1f4 0x590 0x000 0x3 0x0 -#define MX50_PAD_EPDC_GDSP__AUDMUX_AUD6_RXD 0x1f4 0x590 0x000 0x4 0x0 -#define MX50_PAD_EPDC_GDSP__SDMA_DEBUG_CORE_STATE_1 0x1f4 0x590 0x000 0x6 0x0 -#define MX50_PAD_EPDC_GDSP__USBPHY2_BVALID 0x1f4 0x590 0x000 0x7 0x0 -#define MX50_PAD_EPDC_GDOE__EPCD_GDOE 0x1f8 0x594 0x000 0x0 0x0 -#define MX50_PAD_EPDC_GDOE__GPIO3_18 0x1f8 0x594 0x000 0x1 0x0 -#define MX50_PAD_EPDC_GDOE__EIM_WEIM_D_18 0x1f8 0x594 0x000 0x2 0x0 -#define MX50_PAD_EPDC_GDOE__ELCDIF_DAT_18 0x1f8 0x594 0x000 0x3 0x0 -#define MX50_PAD_EPDC_GDOE__AUDMUX_AUD6_RXC 0x1f8 0x594 0x000 0x4 0x0 -#define MX50_PAD_EPDC_GDOE__SDMA_DEBUG_CORE_STATE_2 0x1f8 0x594 0x000 0x6 0x0 -#define MX50_PAD_EPDC_GDOE__USBPHY2_ENDSESSION 0x1f8 0x594 0x000 0x7 0x0 -#define MX50_PAD_EPDC_GDRL__EPCD_GDRL 0x1fc 0x598 0x000 0x0 0x0 -#define MX50_PAD_EPDC_GDRL__GPIO3_19 0x1fc 0x598 0x000 0x1 0x0 -#define MX50_PAD_EPDC_GDRL__EIM_WEIM_D_19 0x1f8 0x598 0x000 0x2 0x0 -#define MX50_PAD_EPDC_GDRL__ELCDIF_DAT_19 0x1fc 0x598 0x000 0x3 0x0 -#define MX50_PAD_EPDC_GDRL__AUDMUX_AUD6_RXFS 0x1fc 0x598 0x000 0x4 0x0 -#define MX50_PAD_EPDC_GDRL__SDMA_DEBUG_CORE_STATE_3 0x1fc 0x598 0x000 0x6 0x0 -#define MX50_PAD_EPDC_GDRL__USBPHY2_IDDIG 0x1fc 0x598 0x000 0x7 0x0 -#define MX50_PAD_EPDC_SDCLK__EPCD_SDCLK 0x200 0x59c 0x000 0x0 0x0 -#define MX50_PAD_EPDC_SDCLK__GPIO3_20 0x200 0x59c 0x000 0x1 0x0 -#define MX50_PAD_EPDC_SDCLK__EIM_WEIM_D_20 0x200 0x59c 0x000 0x2 0x0 -#define MX50_PAD_EPDC_SDCLK__ELCDIF_DAT_20 0x200 0x59c 0x000 0x3 0x0 -#define MX50_PAD_EPDC_SDCLK__AUDMUX_AUD5_TXD 0x200 0x59c 0x000 0x4 0x0 -#define MX50_PAD_EPDC_SDCLK__SDMA_DEBUG_BUS_DEVICE_0 0x200 0x59c 0x000 0x6 0x0 -#define MX50_PAD_EPDC_SDCLK__USBPHY2_HOSTDISCONNECT 0x200 0x59c 0x000 0x7 0x0 -#define MX50_PAD_EPDC_SDOEZ__EPCD_SDOEZ 0x204 0x5a0 0x000 0x0 0x0 -#define MX50_PAD_EPDC_SDOEZ__GPIO3_21 0x204 0x5a0 0x000 0x1 0x0 -#define MX50_PAD_EPDC_SDOEZ__EIM_WEIM_D_21 0x204 0x5a0 0x000 0x2 0x0 -#define MX50_PAD_EPDC_SDOEZ__ELCDIF_DAT_21 0x204 0x5a0 0x000 0x3 0x0 -#define MX50_PAD_EPDC_SDOEZ__AUDMUX_AUD5_TXC 0x204 0x5a0 0x000 0x4 0x0 -#define MX50_PAD_EPDC_SDOEZ__SDMA_DEBUG_BUS_DEVICE_1 0x204 0x5a0 0x000 0x6 0x0 -#define MX50_PAD_EPDC_SDOEZ__USBPHY2_TXREADY 0x204 0x5a0 0x000 0x7 0x0 -#define MX50_PAD_EPDC_SDOED__EPCD_SDOED 0x208 0x5a4 0x000 0x0 0x0 -#define MX50_PAD_EPDC_SDOED__GPIO3_22 0x208 0x5a4 0x000 0x1 0x0 -#define MX50_PAD_EPDC_SDOED__EIM_WEIM_D_22 0x208 0x5a4 0x000 0x2 0x0 -#define MX50_PAD_EPDC_SDOED__ELCDIF_DAT_22 0x208 0x5a4 0x000 0x3 0x0 -#define MX50_PAD_EPDC_SDOED__AUDMUX_AUD5_TXFS 0x208 0x5a4 0x000 0x4 0x0 -#define MX50_PAD_EPDC_SDOED__SDMA_DEBUG_BUS_DEVICE_2 0x208 0x5a4 0x000 0x6 0x0 -#define MX50_PAD_EPDC_SDOED__USBPHY2_RXVALID 0x208 0x5a4 0x000 0x7 0x0 -#define MX50_PAD_EPDC_SDOE__EPCD_SDOE 0x20c 0x5a8 0x000 0x0 0x0 -#define MX50_PAD_EPDC_SDOE__GPIO3_23 0x20c 0x5a8 0x000 0x1 0x0 -#define MX50_PAD_EPDC_SDOE__EIM_WEIM_D_23 0x20c 0x5a8 0x000 0x2 0x0 -#define MX50_PAD_EPDC_SDOE__ELCDIF_DAT_23 0x20c 0x5a8 0x000 0x3 0x0 -#define MX50_PAD_EPDC_SDOE__AUDMUX_AUD5_RXD 0x20c 0x5a8 0x000 0x4 0x0 -#define MX50_PAD_EPDC_SDOE__SDMA_DEBUG_BUS_DEVICE_3 0x20c 0x5a8 0x000 0x6 0x0 -#define MX50_PAD_EPDC_SDOE__USBPHY2_RXACTIVE 0x20c 0x5a8 0x000 0x7 0x0 -#define MX50_PAD_EPDC_SDLE__EPCD_SDLE 0x210 0x5ac 0x000 0x0 0x0 -#define MX50_PAD_EPDC_SDLE__GPIO3_24 0x210 0x5ac 0x000 0x1 0x0 -#define MX50_PAD_EPDC_SDLE__EIM_WEIM_D_24 0x210 0x5ac 0x000 0x2 0x0 -#define MX50_PAD_EPDC_SDLE__ELCDIF_DAT_8 0x210 0x5ac 0x71c 0x3 0x1 -#define MX50_PAD_EPDC_SDLE__AUDMUX_AUD5_RXC 0x210 0x5ac 0x000 0x4 0x0 -#define MX50_PAD_EPDC_SDLE__SDMA_DEBUG_BUS_DEVICE_4 0x210 0x5ac 0x000 0x6 0x0 -#define MX50_PAD_EPDC_SDLE__USBPHY2_RXERROR 0x210 0x5ac 0x000 0x7 0x0 -#define MX50_PAD_EPDC_SDCLKN__EPCD_SDCLKN 0x214 0x5b0 0x000 0x0 0x0 -#define MX50_PAD_EPDC_SDCLKN__GPIO3_25 0x214 0x5b0 0x000 0x1 0x0 -#define MX50_PAD_EPDC_SDCLKN__EIM_WEIM_D_25 0x214 0x5b0 0x000 0x2 0x0 -#define MX50_PAD_EPDC_SDCLKN__ELCDIF_DAT_9 0x214 0x5b0 0x720 0x3 0x1 -#define MX50_PAD_EPDC_SDCLKN__AUDMUX_AUD5_RXFS 0x214 0x5b0 0x000 0x4 0x0 -#define MX50_PAD_EPDC_SDCLKN__SDMA_DEBUG_BUS_ERROR 0x214 0x5b0 0x000 0x6 0x0 -#define MX50_PAD_EPDC_SDCLKN__USBPHY2_SIECLOCK 0x214 0x5b0 0x000 0x7 0x0 -#define MX50_PAD_EPDC_SDSHR__EPCD_SDSHR 0x218 0x5b4 0x000 0x0 0x0 -#define MX50_PAD_EPDC_SDSHR__GPIO3_26 0x218 0x5b4 0x000 0x1 0x0 -#define MX50_PAD_EPDC_SDSHR__EIM_WEIM_D_26 0x218 0x5b4 0x000 0x2 0x0 -#define MX50_PAD_EPDC_SDSHR__ELCDIF_DAT_10 0x218 0x5b4 0x724 0x3 0x1 -#define MX50_PAD_EPDC_SDSHR__AUDMUX_AUD4_TXD 0x218 0x5b4 0x6c8 0x4 0x1 -#define MX50_PAD_EPDC_SDSHR__SDMA_DEBUG_BUS_RWB 0x218 0x5b4 0x000 0x6 0x0 -#define MX50_PAD_EPDC_SDSHR__USBPHY2_LINESTATE_0 0x218 0x5b4 0x000 0x7 0x0 -#define MX50_PAD_EPDC_PWRCOM__EPCD_PWRCOM 0x21c 0x5b8 0x000 0x0 0x0 -#define MX50_PAD_EPDC_PWRCOM__GPIO3_27 0x21c 0x5b8 0x000 0x1 0x0 -#define MX50_PAD_EPDC_PWRCOM__EIM_WEIM_D_27 0x21c 0x5b8 0x000 0x2 0x0 -#define MX50_PAD_EPDC_PWRCOM__ELCDIF_DAT_11 0x21c 0x5b8 0x728 0x3 0x1 -#define MX50_PAD_EPDC_PWRCOM__AUDMUX_AUD4_TXC 0x21c 0x5b8 0x6d4 0x4 0x1 -#define MX50_PAD_EPDC_PWRCOM__SDMA_DEBUG_CORE_RUN 0x21c 0x5b8 0x000 0x6 0x0 -#define MX50_PAD_EPDC_PWRCOM__USBPHY2_LINESTATE_1 0x21c 0x5b8 0x000 0x7 0x0 -#define MX50_PAD_EPDC_PWRSTAT__EPCD_PWRSTAT 0x220 0x5bc 0x000 0x0 0x0 -#define MX50_PAD_EPDC_PWRSTAT__GPIO3_28 0x220 0x5bc 0x000 0x1 0x0 -#define MX50_PAD_EPDC_PWRSTAT__EIM_WEIM_D_28 0x220 0x5bc 0x000 0x2 0x0 -#define MX50_PAD_EPDC_PWRSTAT__ELCDIF_DAT_12 0x220 0x5bc 0x72c 0x3 0x1 -#define MX50_PAD_EPDC_PWRSTAT__AUDMUX_AUD4_TXFS 0x220 0x5bc 0x6d8 0x4 0x1 -#define MX50_PAD_EPDC_PWRSTAT__SDMA_DEBUG_MODE 0x220 0x5bc 0x000 0x6 0x0 -#define MX50_PAD_EPDC_PWRSTAT__USBPHY2_VBUSVALID 0x220 0x5bc 0x000 0x7 0x0 -#define MX50_PAD_EPDC_PWRCTRL0__EPCD_PWRCTRL0 0x224 0x5c0 0x000 0x0 0x0 -#define MX50_PAD_EPDC_PWRCTRL0__GPIO3_29 0x224 0x5c0 0x000 0x1 0x0 -#define MX50_PAD_EPDC_PWRCTRL0__EIM_WEIM_D_29 0x224 0x5c0 0x000 0x2 0x0 -#define MX50_PAD_EPDC_PWRCTRL0__ELCDIF_DAT_13 0x224 0x5c0 0x730 0x3 0x1 -#define MX50_PAD_EPDC_PWRCTRL0__AUDMUX_AUD4_RXD 0x224 0x5c0 0x6c4 0x4 0x1 -#define MX50_PAD_EPDC_PWRCTRL0__SDMA_DEBUG_RTBUFFER_WRITE 0x224 0x5c0 0x000 0x6 0x0 -#define MX50_PAD_EPDC_PWRCTRL0__USBPHY2_AVALID 0x224 0x5c0 0x000 0x7 0x0 -#define MX50_PAD_EPDC_PWRCTRL1__EPCD_PWRCTRL1 0x228 0x5c4 0x000 0x0 0x0 -#define MX50_PAD_EPDC_PWRCTRL1__GPIO3_30 0x228 0x5c4 0x000 0x1 0x0 -#define MX50_PAD_EPDC_PWRCTRL1__EIM_WEIM_D_30 0x228 0x5c4 0x000 0x2 0x0 -#define MX50_PAD_EPDC_PWRCTRL1__ELCDIF_DAT_14 0x228 0x5c4 0x734 0x3 0x1 -#define MX50_PAD_EPDC_PWRCTRL1__AUDMUX_AUD4_RXC 0x228 0x5c4 0x6cc 0x4 0x1 -#define MX50_PAD_EPDC_PWRCTRL1__SDMA_DEBUG_YIELD 0x228 0x5c4 0x000 0x6 0x0 -#define MX50_PAD_EPDC_PWRCTRL1__USBPHY1_ONBIST 0x228 0x5c4 0x000 0x7 0x0 -#define MX50_PAD_EPDC_PWRCTRL2__EPCD_PWRCTRL2 0x22c 0x5c8 0x000 0x0 0x0 -#define MX50_PAD_EPDC_PWRCTRL2__GPIO3_31 0x22c 0x5c8 0x000 0x1 0x0 -#define MX50_PAD_EPDC_PWRCTRL2__EIM_WEIM_D_31 0x22c 0x5c8 0x000 0x2 0x0 -#define MX50_PAD_EPDC_PWRCTRL2__ELCDIF_DAT_15 0x22c 0x5c8 0x738 0x3 0x1 -#define MX50_PAD_EPDC_PWRCTRL2__AUDMUX_AUD4_RXFS 0x22c 0x5c8 0x6d0 0x4 0x1 -#define MX50_PAD_EPDC_PWRCTRL2__SDMA_EXT_EVENT_0 0x22c 0x5c8 0x7b8 0x6 0x1 -#define MX50_PAD_EPDC_PWRCTRL2__USBPHY2_ONBIST 0x22c 0x5c8 0x000 0x7 0x0 -#define MX50_PAD_EPDC_PWRCTRL3__EPCD_PWRCTRL3 0x230 0x5cc 0x000 0x0 0x0 -#define MX50_PAD_EPDC_PWRCTRL3__GPIO4_20 0x230 0x5cc 0x000 0x1 0x0 -#define MX50_PAD_EPDC_PWRCTRL3__EIM_WEIM_EB_2 0x230 0x5cc 0x000 0x2 0x0 -#define MX50_PAD_EPDC_PWRCTRL3__SDMA_EXT_EVENT_1 0x230 0x5cc 0x7bc 0x6 0x1 -#define MX50_PAD_EPDC_PWRCTRL3__USBPHY1_BISTOK 0x230 0x5cc 0x000 0x7 0x0 -#define MX50_PAD_EPDC_VCOM0__EPCD_VCOM_0 0x234 0x5d0 0x000 0x0 0x0 -#define MX50_PAD_EPDC_VCOM0__GPIO4_21 0x234 0x5d0 0x000 0x1 0x0 -#define MX50_PAD_EPDC_VCOM0__EIM_WEIM_EB_3 0x234 0x5d0 0x000 0x2 0x0 -#define MX50_PAD_EPDC_VCOM0__USBPHY2_BISTOK 0x234 0x5d0 0x000 0x7 0x0 -#define MX50_PAD_EPDC_VCOM1__EPCD_VCOM_1 0x238 0x5d4 0x000 0x0 0x0 -#define MX50_PAD_EPDC_VCOM1__GPIO4_22 0x238 0x5d4 0x000 0x1 0x0 -#define MX50_PAD_EPDC_VCOM1__EIM_WEIM_CS_3 0x238 0x5d4 0x000 0x2 0x0 -#define MX50_PAD_EPDC_BDR0__EPCD_BDR_0 0x23c 0x5d8 0x000 0x0 0x0 -#define MX50_PAD_EPDC_BDR0__GPIO4_23 0x23c 0x5d8 0x000 0x1 0x0 -#define MX50_PAD_EPDC_BDR0__ELCDIF_DAT_7 0x23c 0x5d8 0x718 0x3 0x1 -#define MX50_PAD_EPDC_BDR1__EPCD_BDR_1 0x240 0x5dc 0x000 0x0 0x0 -#define MX50_PAD_EPDC_BDR1__GPIO4_24 0x240 0x5dc 0x000 0x1 0x0 -#define MX50_PAD_EPDC_BDR1__ELCDIF_DAT_6 0x240 0x5dc 0x714 0x3 0x1 -#define MX50_PAD_EPDC_SDCE0__EPCD_SDCE_0 0x244 0x5e0 0x000 0x0 0x0 -#define MX50_PAD_EPDC_SDCE0__GPIO4_25 0x244 0x5e0 0x000 0x1 0x0 -#define MX50_PAD_EPDC_SDCE0__ELCDIF_DAT_5 0x244 0x5e0 0x710 0x3 0x1 -#define MX50_PAD_EPDC_SDCE1__EPCD_SDCE_1 0x248 0x5e4 0x000 0x0 0x0 -#define MX50_PAD_EPDC_SDCE1__GPIO4_26 0x248 0x5e4 0x000 0x1 0x0 -#define MX50_PAD_EPDC_SDCE1__ELCDIF_DAT_4 0x248 0x5e4 0x70c 0x3 0x0 -#define MX50_PAD_EPDC_SDCE2__EPCD_SDCE_2 0x24c 0x5e8 0x000 0x0 0x0 -#define MX50_PAD_EPDC_SDCE2__GPIO4_27 0x24c 0x5e8 0x000 0x1 0x0 -#define MX50_PAD_EPDC_SDCE2__ELCDIF_DAT_3 0x24c 0x5e8 0x708 0x3 0x1 -#define MX50_PAD_EPDC_SDCE3__EPCD_SDCE_3 0x250 0x5ec 0x000 0x0 0x0 -#define MX50_PAD_EPDC_SDCE3__GPIO4_28 0x250 0x5ec 0x000 0x1 0x0 -#define MX50_PAD_EPDC_SDCE3__ELCDIF_DAT_2 0x250 0x5ec 0x704 0x3 0x1 -#define MX50_PAD_EPDC_SDCE4__EPCD_SDCE_4 0x254 0x5f0 0x000 0x0 0x0 -#define MX50_PAD_EPDC_SDCE4__GPIO4_29 0x254 0x5f0 0x000 0x1 0x0 -#define MX50_PAD_EPDC_SDCE4__ELCDIF_DAT_1 0x254 0x5f0 0x700 0x3 0x1 -#define MX50_PAD_EPDC_SDCE5__EPCD_SDCE_5 0x258 0x5f4 0x000 0x0 0x0 -#define MX50_PAD_EPDC_SDCE5__GPIO4_30 0x258 0x5f4 0x000 0x1 0x0 -#define MX50_PAD_EPDC_SDCE5__ELCDIF_DAT_0 0x258 0x5f4 0x6fc 0x3 0x1 -#define MX50_PAD_EIM_DA0__EIM_WEIM_A_0 0x25c 0x5f8 0x000 0x0 0x0 -#define MX50_PAD_EIM_DA0__GPIO1_0 0x25c 0x5f8 0x000 0x1 0x0 -#define MX50_PAD_EIM_DA0__KPP_COL_4 0x25c 0x5f8 0x790 0x3 0x2 -#define MX50_PAD_EIM_DA0__TPIU_TRACE_0 0x25c 0x5f8 0x000 0x6 0x0 -#define MX50_PAD_EIM_DA0__SRC_BT_CFG1_0 0x25c 0x5f8 0x000 0x7 0x0 -#define MX50_PAD_EIM_DA1__EIM_WEIM_A_1 0x260 0x5fc 0x000 0x0 0x0 -#define MX50_PAD_EIM_DA1__GPIO1_1 0x260 0x5fc 0x000 0x1 0x0 -#define MX50_PAD_EIM_DA1__KPP_ROW_4 0x260 0x5fc 0x7a0 0x3 0x2 -#define MX50_PAD_EIM_DA1__TPIU_TRACE_1 0x260 0x5fc 0x000 0x6 0x0 -#define MX50_PAD_EIM_DA1__SRC_BT_CFG1_1 0x260 0x5fc 0x000 0x7 0x0 -#define MX50_PAD_EIM_DA2__EIM_WEIM_A_2 0x264 0x600 0x000 0x0 0x0 -#define MX50_PAD_EIM_DA2__GPIO1_2 0x264 0x600 0x000 0x1 0x0 -#define MX50_PAD_EIM_DA2__KPP_COL_5 0x264 0x600 0x794 0x3 0x2 -#define MX50_PAD_EIM_DA2__TPIU_TRACE_2 0x264 0x600 0x000 0x6 0x0 -#define MX50_PAD_EIM_DA2__SRC_BT_CFG1_2 0x264 0x600 0x000 0x7 0x0 -#define MX50_PAD_EIM_DA3__EIM_WEIM_A_3 0x268 0x604 0x000 0x0 0x0 -#define MX50_PAD_EIM_DA3__GPIO1_3 0x268 0x604 0x000 0x1 0x0 -#define MX50_PAD_EIM_DA3__KPP_ROW_5 0x268 0x604 0x7a4 0x3 0x2 -#define MX50_PAD_EIM_DA3__TPIU_TRACE_3 0x268 0x604 0x000 0x6 0x0 -#define MX50_PAD_EIM_DA3__SRC_BT_CFG1_3 0x268 0x604 0x000 0x7 0x0 -#define MX50_PAD_EIM_DA4__EIM_WEIM_A_4 0x26c 0x608 0x000 0x0 0x0 -#define MX50_PAD_EIM_DA4__GPIO1_4 0x26c 0x608 0x000 0x1 0x0 -#define MX50_PAD_EIM_DA4__KPP_COL_6 0x26c 0x608 0x798 0x3 0x2 -#define MX50_PAD_EIM_DA4__TPIU_TRACE_4 0x26c 0x608 0x000 0x6 0x0 -#define MX50_PAD_EIM_DA4__SRC_BT_CFG1_4 0x26c 0x608 0x000 0x7 0x0 -#define MX50_PAD_EIM_DA5__EIM_WEIM_A_5 0x270 0x60c 0x000 0x0 0x0 -#define MX50_PAD_EIM_DA5__GPIO1_5 0x270 0x60c 0x000 0x1 0x0 -#define MX50_PAD_EIM_DA5__KPP_ROW_6 0x270 0x60c 0x7a8 0x3 0x2 -#define MX50_PAD_EIM_DA5__TPIU_TRACE_5 0x270 0x60c 0x000 0x6 0x0 -#define MX50_PAD_EIM_DA5__SRC_BT_CFG1_5 0x270 0x60c 0x000 0x7 0x0 -#define MX50_PAD_EIM_DA6__EIM_WEIM_A_6 0x274 0x610 0x000 0x0 0x0 -#define MX50_PAD_EIM_DA6__GPIO1_6 0x274 0x610 0x000 0x1 0x0 -#define MX50_PAD_EIM_DA6__KPP_COL_7 0x274 0x610 0x79c 0x3 0x2 -#define MX50_PAD_EIM_DA6__TPIU_TRACE_6 0x274 0x610 0x000 0x6 0x0 -#define MX50_PAD_EIM_DA6__SRC_BT_CFG1_6 0x274 0x610 0x000 0x7 0x0 -#define MX50_PAD_EIM_DA7__EIM_WEIM_A_7 0x278 0x614 0x000 0x0 0x0 -#define MX50_PAD_EIM_DA7__GPIO1_7 0x278 0x614 0x000 0x1 0x0 -#define MX50_PAD_EIM_DA7__KPP_ROW_7 0x278 0x614 0x7ac 0x3 0x2 -#define MX50_PAD_EIM_DA7__TPIU_TRACE_7 0x278 0x614 0x000 0x6 0x0 -#define MX50_PAD_EIM_DA7__SRC_BT_CFG1_7 0x278 0x614 0x000 0x7 0x0 -#define MX50_PAD_EIM_DA8__EIM_WEIM_A_8 0x27c 0x618 0x000 0x0 0x0 -#define MX50_PAD_EIM_DA8__GPIO1_8 0x27c 0x618 0x000 0x1 0x0 -#define MX50_PAD_EIM_DA8__EIM_NANDF_CLE 0x27c 0x618 0x000 0x2 0x0 -#define MX50_PAD_EIM_DA8__TPIU_TRACE_8 0x27c 0x618 0x000 0x6 0x0 -#define MX50_PAD_EIM_DA8__SRC_BT_CFG2_0 0x27c 0x618 0x000 0x7 0x0 -#define MX50_PAD_EIM_DA9__EIM_WEIM_A_9 0x280 0x61c 0x000 0x0 0x0 -#define MX50_PAD_EIM_DA9__GPIO1_9 0x280 0x61c 0x000 0x1 0x0 -#define MX50_PAD_EIM_DA9__EIM_NANDF_ALE 0x280 0x61c 0x000 0x2 0x0 -#define MX50_PAD_EIM_DA9__TPIU_TRACE_9 0x280 0x61c 0x000 0x6 0x0 -#define MX50_PAD_EIM_DA9__SRC_BT_CFG2_1 0x280 0x61c 0x000 0x7 0x0 -#define MX50_PAD_EIM_DA10__EIM_WEIM_A_10 0x284 0x620 0x000 0x0 0x0 -#define MX50_PAD_EIM_DA10__GPIO1_10 0x284 0x620 0x000 0x1 0x0 -#define MX50_PAD_EIM_DA10__EIM_NANDF_CEN_0 0x284 0x620 0x000 0x2 0x0 -#define MX50_PAD_EIM_DA10__TPIU_TRACE_10 0x284 0x620 0x000 0x6 0x0 -#define MX50_PAD_EIM_DA10__SRC_BT_CFG2_2 0x284 0x620 0x000 0x7 0x0 -#define MX50_PAD_EIM_DA11__EIM_WEIM_A_11 0x288 0x624 0x000 0x0 0x0 -#define MX50_PAD_EIM_DA11__GPIO1_11 0x288 0x624 0x000 0x1 0x0 -#define MX50_PAD_EIM_DA11__EIM_NANDF_CEN_1 0x288 0x624 0x000 0x2 0x0 -#define MX50_PAD_EIM_DA11__TPIU_TRACE_11 0x288 0x624 0x000 0x6 0x0 -#define MX50_PAD_EIM_DA11__SRC_BT_CFG2_3 0x288 0x624 0x000 0x7 0x0 -#define MX50_PAD_EIM_DA12__EIM_WEIM_A_12 0x28c 0x628 0x000 0x0 0x0 -#define MX50_PAD_EIM_DA12__GPIO1_12 0x28c 0x628 0x000 0x1 0x0 -#define MX50_PAD_EIM_DA12__EIM_NANDF_CEN_2 0x28c 0x628 0x000 0x2 0x0 -#define MX50_PAD_EIM_DA12__EPDC_SDCE_6 0x28c 0x628 0x000 0x3 0x0 -#define MX50_PAD_EIM_DA12__TPIU_TRACE_12 0x28c 0x628 0x000 0x6 0x0 -#define MX50_PAD_EIM_DA12__SRC_BT_CFG2_4 0x28c 0x628 0x000 0x7 0x0 -#define MX50_PAD_EIM_DA13__EIM_WEIM_A_13 0x290 0x62c 0x000 0x0 0x0 -#define MX50_PAD_EIM_DA13__GPIO1_13 0x290 0x62c 0x000 0x1 0x0 -#define MX50_PAD_EIM_DA13__EIM_NANDF_CEN_3 0x290 0x62c 0x000 0x2 0x0 -#define MX50_PAD_EIM_DA13__EPDC_SDCE_7 0x290 0x62c 0x000 0x3 0x0 -#define MX50_PAD_EIM_DA13__TPIU_TRACE_13 0x290 0x62c 0x000 0x6 0x0 -#define MX50_PAD_EIM_DA13__SRC_BT_CFG2_5 0x290 0x62c 0x000 0x7 0x0 -#define MX50_PAD_EIM_DA14__EIM_WEIM_A_14 0x294 0x630 0x000 0x0 0x0 -#define MX50_PAD_EIM_DA14__GPIO1_14 0x294 0x630 0x000 0x1 0x0 -#define MX50_PAD_EIM_DA14__EIM_NANDF_READY0 0x294 0x630 0x7b4 0x2 0x2 -#define MX50_PAD_EIM_DA14__EPDC_SDCE_8 0x294 0x630 0x000 0x3 0x0 -#define MX50_PAD_EIM_DA14__TPIU_TRACE_14 0x294 0x630 0x000 0x6 0x0 -#define MX50_PAD_EIM_DA14__SRC_BT_CFG2_6 0x294 0x630 0x000 0x7 0x0 -#define MX50_PAD_EIM_DA15__EIM_WEIM_A_15 0x298 0x634 0x000 0x0 0x0 -#define MX50_PAD_EIM_DA15__GPIO1_15 0x298 0x634 0x000 0x1 0x0 -#define MX50_PAD_EIM_DA15__EIM_NANDF_DQS 0x298 0x634 0x7b0 0x2 0x2 -#define MX50_PAD_EIM_DA15__EPDC_SDCE_9 0x298 0x634 0x000 0x3 0x0 -#define MX50_PAD_EIM_DA15__TPIU_TRACE_15 0x298 0x634 0x000 0x6 0x0 -#define MX50_PAD_EIM_DA15__SRC_BT_CFG2_7 0x298 0x634 0x000 0x7 0x0 -#define MX50_PAD_EIM_CS2__EIM_WEIM_CS_2 0x29c 0x638 0x000 0x0 0x0 -#define MX50_PAD_EIM_CS2__GPIO1_16 0x29c 0x638 0x000 0x1 0x0 -#define MX50_PAD_EIM_CS2__EIM_WEIM_A_27 0x29c 0x638 0x000 0x2 0x0 -#define MX50_PAD_EIM_CS2__TPIU_TRCLK 0x29c 0x638 0x000 0x6 0x0 -#define MX50_PAD_EIM_CS2__SRC_BT_CFG3_0 0x29c 0x638 0x000 0x7 0x0 -#define MX50_PAD_EIM_CS1__EIM_WEIM_CS_1 0x2a0 0x63c 0x000 0x0 0x0 -#define MX50_PAD_EIM_CS1__GPIO1_17 0x2a0 0x63c 0x000 0x1 0x0 -#define MX50_PAD_EIM_CS1__TPIU_TRCTL 0x2a0 0x63c 0x000 0x6 0x0 -#define MX50_PAD_EIM_CS1__SRC_BT_CFG3_1 0x2a0 0x63c 0x000 0x7 0x0 -#define MX50_PAD_EIM_CS0__EIM_WEIM_CS_0 0x2a4 0x640 0x000 0x0 0x0 -#define MX50_PAD_EIM_CS0__GPIO1_18 0x2a4 0x640 0x000 0x1 0x0 -#define MX50_PAD_EIM_CS0__SRC_BT_CFG3_2 0x2a4 0x640 0x000 0x7 0x0 -#define MX50_PAD_EIM_EB0__EIM_WEIM_EB_0 0x2a8 0x644 0x000 0x0 0x0 -#define MX50_PAD_EIM_EB0__GPIO1_19 0x2a8 0x644 0x000 0x1 0x0 -#define MX50_PAD_EIM_EB0__SRC_BT_CFG3_3 0x2a8 0x644 0x000 0x7 0x0 -#define MX50_PAD_EIM_EB1__EIM_WEIM_EB_1 0x2ac 0x648 0x000 0x0 0x0 -#define MX50_PAD_EIM_EB1__GPIO1_20 0x2ac 0x648 0x000 0x1 0x0 -#define MX50_PAD_EIM_EB1__SRC_BT_CFG3_4 0x2ac 0x648 0x000 0x7 0x0 -#define MX50_PAD_EIM_WAIT__EIM_WEIM_WAIT 0x2b0 0x64c 0x000 0x0 0x0 -#define MX50_PAD_EIM_WAIT__GPIO1_21 0x2b0 0x64c 0x000 0x1 0x0 -#define MX50_PAD_EIM_WAIT__EIM_WEIM_DTACK_B 0x2b0 0x64c 0x000 0x2 0x0 -#define MX50_PAD_EIM_WAIT__SRC_BT_CFG3_5 0x2b0 0x64c 0x000 0x7 0x0 -#define MX50_PAD_EIM_BCLK__EIM_WEIM_BCLK 0x2b4 0x650 0x000 0x0 0x0 -#define MX50_PAD_EIM_BCLK__GPIO1_22 0x2b4 0x650 0x000 0x1 0x0 -#define MX50_PAD_EIM_BCLK__SRC_BT_CFG3_6 0x2b4 0x650 0x000 0x7 0x0 -#define MX50_PAD_EIM_RDY__EIM_WEIM_RDY 0x2b8 0x654 0x000 0x0 0x0 -#define MX50_PAD_EIM_RDY__GPIO1_23 0x2b8 0x654 0x000 0x1 0x0 -#define MX50_PAD_EIM_RDY__SRC_BT_CFG3_7 0x2b8 0x654 0x000 0x7 0x0 -#define MX50_PAD_EIM_OE__EIM_WEIM_OE 0x2bc 0x658 0x000 0x0 0x0 -#define MX50_PAD_EIM_OE__GPIO1_24 0x2bc 0x658 0x000 0x1 0x0 -#define MX50_PAD_EIM_OE__INT_BOOT 0x2bc 0x658 0x000 0x7 0x0 -#define MX50_PAD_EIM_RW__EIM_WEIM_RW 0x2c0 0x65c 0x000 0x0 0x0 -#define MX50_PAD_EIM_RW__GPIO1_25 0x2c0 0x65c 0x000 0x1 0x0 -#define MX50_PAD_EIM_RW__SYSTEM_RST 0x2c0 0x65c 0x000 0x7 0x0 -#define MX50_PAD_EIM_LBA__EIM_WEIM_LBA 0x2c4 0x660 0x000 0x0 0x0 -#define MX50_PAD_EIM_LBA__GPIO1_26 0x2c4 0x660 0x000 0x1 0x0 -#define MX50_PAD_EIM_LBA__TESTER_ACK 0x2c4 0x660 0x000 0x7 0x0 -#define MX50_PAD_EIM_CRE__EIM_WEIM_CRE 0x2c8 0x664 0x000 0x0 0x0 -#define MX50_PAD_EIM_CRE__GPIO1_27 0x2c8 0x664 0x000 0x1 0x0 - -#endif /* __DTS_IMX50_PINFUNC_H */ diff --git a/sys/gnu/dts/arm/imx50.dtsi b/sys/gnu/dts/arm/imx50.dtsi deleted file mode 100644 index 0bfe7c91d0e..00000000000 --- a/sys/gnu/dts/arm/imx50.dtsi +++ /dev/null @@ -1,503 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// -// Copyright 2013 Greg Ungerer -// Copyright 2011 Freescale Semiconductor, Inc. -// Copyright 2011 Linaro Ltd. - -#include "imx50-pinfunc.h" -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - /* - * The decompressor and also some bootloaders rely on a - * pre-existing /chosen node to be available to insert the - * command line and merge other ATAGS info. - */ - chosen {}; - - aliases { - ethernet0 = &fec; - gpio0 = &gpio1; - gpio1 = &gpio2; - gpio2 = &gpio3; - gpio3 = &gpio4; - gpio4 = &gpio5; - gpio5 = &gpio6; - i2c0 = &i2c1; - i2c1 = &i2c2; - i2c2 = &i2c3; - mmc0 = &esdhc1; - mmc1 = &esdhc2; - mmc2 = &esdhc3; - mmc3 = &esdhc4; - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - serial3 = &uart4; - serial4 = &uart5; - spi0 = &ecspi1; - spi1 = &ecspi2; - spi2 = &cspi; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a8"; - reg = <0x0>; - }; - }; - - tzic: tz-interrupt-controller@fffc000 { - compatible = "fsl,imx50-tzic", "fsl,imx53-tzic", "fsl,tzic"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x0fffc000 0x4000>; - }; - - clocks { - ckil { - compatible = "fsl,imx-ckil", "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - - ckih1 { - compatible = "fsl,imx-ckih1", "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <22579200>; - }; - - ckih2 { - compatible = "fsl,imx-ckih2", "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - osc { - compatible = "fsl,imx-osc", "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - }; - }; - - usbphy0: usbphy-0 { - compatible = "usb-nop-xceiv"; - clocks = <&clks IMX5_CLK_USB_PHY1_GATE>; - clock-names = "main_clk"; - #phy-cells = <0>; - status = "okay"; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&tzic>; - ranges; - - aips@50000000 { /* AIPS1 */ - compatible = "fsl,aips-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x50000000 0x10000000>; - ranges; - - spba@50000000 { - compatible = "fsl,spba-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x50000000 0x40000>; - ranges; - - esdhc1: esdhc@50004000 { - compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc"; - reg = <0x50004000 0x4000>; - interrupts = <1>; - clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>, - <&clks IMX5_CLK_DUMMY>, - <&clks IMX5_CLK_ESDHC1_PER_GATE>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - status = "disabled"; - }; - - esdhc2: esdhc@50008000 { - compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc"; - reg = <0x50008000 0x4000>; - interrupts = <2>; - clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>, - <&clks IMX5_CLK_DUMMY>, - <&clks IMX5_CLK_ESDHC2_PER_GATE>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - status = "disabled"; - }; - - uart3: serial@5000c000 { - compatible = "fsl,imx50-uart", "fsl,imx21-uart"; - reg = <0x5000c000 0x4000>; - interrupts = <33>; - clocks = <&clks IMX5_CLK_UART3_IPG_GATE>, - <&clks IMX5_CLK_UART3_PER_GATE>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - ecspi1: spi@50010000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx50-ecspi", "fsl,imx51-ecspi"; - reg = <0x50010000 0x4000>; - interrupts = <36>; - clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>, - <&clks IMX5_CLK_ECSPI1_PER_GATE>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - ssi2: ssi@50014000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx50-ssi", - "fsl,imx51-ssi", - "fsl,imx21-ssi"; - reg = <0x50014000 0x4000>; - interrupts = <30>; - clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>; - dmas = <&sdma 24 1 0>, - <&sdma 25 1 0>; - dma-names = "rx", "tx"; - fsl,fifo-depth = <15>; - status = "disabled"; - }; - - esdhc3: esdhc@50020000 { - compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc"; - reg = <0x50020000 0x4000>; - interrupts = <3>; - clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>, - <&clks IMX5_CLK_DUMMY>, - <&clks IMX5_CLK_ESDHC3_PER_GATE>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - status = "disabled"; - }; - - esdhc4: esdhc@50024000 { - compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc"; - reg = <0x50024000 0x4000>; - interrupts = <4>; - clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>, - <&clks IMX5_CLK_DUMMY>, - <&clks IMX5_CLK_ESDHC4_PER_GATE>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - status = "disabled"; - }; - }; - - usbotg: usb@53f80000 { - compatible = "fsl,imx50-usb", "fsl,imx27-usb"; - reg = <0x53f80000 0x0200>; - interrupts = <18>; - clocks = <&clks IMX5_CLK_USBOH3_GATE>; - fsl,usbphy = <&usbphy0>; - status = "disabled"; - }; - - usbh1: usb@53f80200 { - compatible = "fsl,imx50-usb", "fsl,imx27-usb"; - reg = <0x53f80200 0x0200>; - interrupts = <14>; - clocks = <&clks IMX5_CLK_USB_PHY2_GATE>; - dr_mode = "host"; - status = "disabled"; - }; - - gpio1: gpio@53f84000 { - compatible = "fsl,imx50-gpio", "fsl,imx35-gpio"; - reg = <0x53f84000 0x4000>; - interrupts = <50 51>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 151 28>; - }; - - gpio2: gpio@53f88000 { - compatible = "fsl,imx50-gpio", "fsl,imx35-gpio"; - reg = <0x53f88000 0x4000>; - interrupts = <52 53>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 75 8>, <&iomuxc 8 100 8>, - <&iomuxc 16 83 1>, <&iomuxc 17 85 1>, - <&iomuxc 18 87 1>, <&iomuxc 19 84 1>, - <&iomuxc 20 88 1>, <&iomuxc 21 86 1>; - }; - - gpio3: gpio@53f8c000 { - compatible = "fsl,imx50-gpio", "fsl,imx35-gpio"; - reg = <0x53f8c000 0x4000>; - interrupts = <54 55>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 108 32>; - }; - - gpio4: gpio@53f90000 { - compatible = "fsl,imx50-gpio", "fsl,imx35-gpio"; - reg = <0x53f90000 0x4000>; - interrupts = <56 57>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 8 8>, <&iomuxc 8 45 12>, - <&iomuxc 20 140 11>; - }; - - wdog1: wdog@53f98000 { - compatible = "fsl,imx50-wdt", "fsl,imx21-wdt"; - reg = <0x53f98000 0x4000>; - interrupts = <58>; - clocks = <&clks IMX5_CLK_DUMMY>; - }; - - gpt: timer@53fa0000 { - compatible = "fsl,imx50-gpt", "fsl,imx31-gpt"; - reg = <0x53fa0000 0x4000>; - interrupts = <39>; - clocks = <&clks IMX5_CLK_GPT_IPG_GATE>, - <&clks IMX5_CLK_GPT_HF_GATE>; - clock-names = "ipg", "per"; - }; - - iomuxc: iomuxc@53fa8000 { - compatible = "fsl,imx50-iomuxc", "fsl,imx53-iomuxc"; - reg = <0x53fa8000 0x4000>; - }; - - gpr: iomuxc-gpr@53fa8000 { - compatible = "fsl,imx50-iomuxc-gpr", "syscon"; - reg = <0x53fa8000 0xc>; - }; - - pwm1: pwm@53fb4000 { - #pwm-cells = <2>; - compatible = "fsl,imx50-pwm", "fsl,imx27-pwm"; - reg = <0x53fb4000 0x4000>; - clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>, - <&clks IMX5_CLK_PWM1_HF_GATE>; - clock-names = "ipg", "per"; - interrupts = <61>; - }; - - pwm2: pwm@53fb8000 { - #pwm-cells = <2>; - compatible = "fsl,imx50-pwm", "fsl,imx27-pwm"; - reg = <0x53fb8000 0x4000>; - clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>, - <&clks IMX5_CLK_PWM2_HF_GATE>; - clock-names = "ipg", "per"; - interrupts = <94>; - }; - - uart1: serial@53fbc000 { - compatible = "fsl,imx50-uart", "fsl,imx21-uart"; - reg = <0x53fbc000 0x4000>; - interrupts = <31>; - clocks = <&clks IMX5_CLK_UART1_IPG_GATE>, - <&clks IMX5_CLK_UART1_PER_GATE>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart2: serial@53fc0000 { - compatible = "fsl,imx50-uart", "fsl,imx21-uart"; - reg = <0x53fc0000 0x4000>; - interrupts = <32>; - clocks = <&clks IMX5_CLK_UART2_IPG_GATE>, - <&clks IMX5_CLK_UART2_PER_GATE>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - src: src@53fd0000 { - compatible = "fsl,imx50-src", "fsl,imx51-src"; - reg = <0x53fd0000 0x4000>; - #reset-cells = <1>; - }; - - clks: ccm@53fd4000{ - compatible = "fsl,imx50-ccm"; - reg = <0x53fd4000 0x4000>; - interrupts = <0 71 0x04 0 72 0x04>; - #clock-cells = <1>; - }; - - gpio5: gpio@53fdc000 { - compatible = "fsl,imx50-gpio", "fsl,imx35-gpio"; - reg = <0x53fdc000 0x4000>; - interrupts = <103 104>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 57 18>, <&iomuxc 18 89 11>; - }; - - gpio6: gpio@53fe0000 { - compatible = "fsl,imx50-gpio", "fsl,imx35-gpio"; - reg = <0x53fe0000 0x4000>; - interrupts = <105 106>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 27 18>, <&iomuxc 18 16 11>; - }; - - i2c3: i2c@53fec000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx50-i2c", "fsl,imx21-i2c"; - reg = <0x53fec000 0x4000>; - interrupts = <64>; - clocks = <&clks IMX5_CLK_I2C3_GATE>; - status = "disabled"; - }; - - uart4: serial@53ff0000 { - compatible = "fsl,imx50-uart", "fsl,imx21-uart"; - reg = <0x53ff0000 0x4000>; - interrupts = <13>; - clocks = <&clks IMX5_CLK_UART4_IPG_GATE>, - <&clks IMX5_CLK_UART4_PER_GATE>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - }; - - aips@60000000 { /* AIPS2 */ - compatible = "fsl,aips-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x60000000 0x10000000>; - ranges; - - uart5: serial@63f90000 { - compatible = "fsl,imx50-uart", "fsl,imx21-uart"; - reg = <0x63f90000 0x4000>; - interrupts = <86>; - clocks = <&clks IMX5_CLK_UART5_IPG_GATE>, - <&clks IMX5_CLK_UART5_PER_GATE>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - owire: owire@63fa4000 { - compatible = "fsl,imx50-owire", "fsl,imx21-owire"; - reg = <0x63fa4000 0x4000>; - clocks = <&clks IMX5_CLK_OWIRE_GATE>; - status = "disabled"; - }; - - ecspi2: spi@63fac000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx50-ecspi", "fsl,imx51-ecspi"; - reg = <0x63fac000 0x4000>; - interrupts = <37>; - clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>, - <&clks IMX5_CLK_ECSPI2_PER_GATE>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - sdma: sdma@63fb0000 { - compatible = "fsl,imx50-sdma", "fsl,imx35-sdma"; - reg = <0x63fb0000 0x4000>; - interrupts = <6>; - clocks = <&clks IMX5_CLK_SDMA_GATE>, - <&clks IMX5_CLK_AHB>; - clock-names = "ipg", "ahb"; - #dma-cells = <3>; - fsl,sdma-ram-script-name = "imx/sdma/sdma-imx50.bin"; - }; - - cspi: spi@63fc0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx50-cspi", "fsl,imx35-cspi"; - reg = <0x63fc0000 0x4000>; - interrupts = <38>; - clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>, - <&clks IMX5_CLK_CSPI_IPG_GATE>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - i2c2: i2c@63fc4000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx50-i2c", "fsl,imx21-i2c"; - reg = <0x63fc4000 0x4000>; - interrupts = <63>; - clocks = <&clks IMX5_CLK_I2C2_GATE>; - status = "disabled"; - }; - - i2c1: i2c@63fc8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx50-i2c", "fsl,imx21-i2c"; - reg = <0x63fc8000 0x4000>; - interrupts = <62>; - clocks = <&clks IMX5_CLK_I2C1_GATE>; - status = "disabled"; - }; - - ssi1: ssi@63fcc000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx50-ssi", "fsl,imx51-ssi", - "fsl,imx21-ssi"; - reg = <0x63fcc000 0x4000>; - interrupts = <29>; - clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>; - dmas = <&sdma 28 0 0>, - <&sdma 29 0 0>; - dma-names = "rx", "tx"; - fsl,fifo-depth = <15>; - status = "disabled"; - }; - - audmux: audmux@63fd0000 { - compatible = "fsl,imx50-audmux", "fsl,imx31-audmux"; - reg = <0x63fd0000 0x4000>; - status = "disabled"; - }; - - fec: ethernet@63fec000 { - compatible = "fsl,imx53-fec", "fsl,imx25-fec"; - reg = <0x63fec000 0x4000>; - interrupts = <87>; - clocks = <&clks IMX5_CLK_FEC_GATE>, - <&clks IMX5_CLK_FEC_GATE>, - <&clks IMX5_CLK_FEC_GATE>; - clock-names = "ipg", "ahb", "ptp"; - status = "disabled"; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/imx51-apf51.dts b/sys/gnu/dts/arm/imx51-apf51.dts deleted file mode 100644 index ba28ffe06fe..00000000000 --- a/sys/gnu/dts/arm/imx51-apf51.dts +++ /dev/null @@ -1,84 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2012 Armadeus Systems - - * Copyright 2012 Laurent Cans - * - * Based on mx51-babbage.dts - * Copyright 2011 Freescale Semiconductor, Inc. - * Copyright 2011 Linaro Ltd. - */ - -/dts-v1/; -#include "imx51.dtsi" - -/ { - model = "Armadeus Systems APF51 module"; - compatible = "armadeus,imx51-apf51", "fsl,imx51"; - - memory@90000000 { - device_type = "memory"; - reg = <0x90000000 0x20000000>; - }; - - clocks { - osc { - clock-frequency = <33554432>; - }; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec>; - phy-mode = "mii"; - phy-reset-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; - phy-reset-duration = <1>; - status = "okay"; -}; - -&iomuxc { - imx51-apf51 { - pinctrl_fec: fecgrp { - fsl,pins = < - MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000 - MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000 - MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000 - MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000 - MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000 - MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000 - MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000 - MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000 - MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000 - MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000 - MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000 - MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000 - MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000 - MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000 - MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000 - MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000 - MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000 - MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX51_PAD_UART3_RXD__UART3_RXD 0x1c5 - MX51_PAD_UART3_TXD__UART3_TXD 0x1c5 - >; - }; - }; -}; - -&nfc { - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - nand-on-flash-bbt; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx51-apf51dev.dts b/sys/gnu/dts/arm/imx51-apf51dev.dts deleted file mode 100644 index 563c1aae8c0..00000000000 --- a/sys/gnu/dts/arm/imx51-apf51dev.dts +++ /dev/null @@ -1,217 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Armadeus Systems - - */ - -/* APF51Dev is a docking board for the APF51 SOM */ -#include "imx51-apf51.dts" - -/ { - model = "Armadeus Systems APF51Dev docking/development board"; - compatible = "armadeus,imx51-apf51dev", "armadeus,imx51-apf51", "fsl,imx51"; - - backlight { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_backlight>; - compatible = "gpio-backlight"; - gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>; - default-on; - }; - - disp1 { - compatible = "fsl,imx-parallel-display"; - interface-pix-fmt = "bgr666"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu_disp1>; - - display-timings { - lw700 { - native-mode; - clock-frequency = <33000033>; - hactive = <800>; - vactive = <480>; - hback-porch = <96>; - hfront-porch = <96>; - vback-porch = <20>; - vfront-porch = <21>; - hsync-len = <64>; - vsync-len = <4>; - hsync-active = <1>; - vsync-active = <1>; - de-active = <1>; - pixelclk-active = <0>; - }; - }; - - port { - display_in: endpoint { - remote-endpoint = <&ipu_di0_disp1>; - }; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - user-key { - label = "user"; - gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; - linux,code = <256>; /* BTN_0 */ - }; - }; - - leds { - compatible = "gpio-leds"; - - user { - label = "Heartbeat"; - gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; -}; - -&ecspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>, - <&gpio4 25 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&ecspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi2>; - cs-gpios = <&gpio3 28 GPIO_ACTIVE_LOW>, - <&gpio3 27 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&esdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc1>; - cd-gpios = <&gpio2 29 GPIO_ACTIVE_LOW>; - bus-width = <4>; - status = "okay"; -}; - -&esdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc2>; - bus-width = <4>; - non-removable; - status = "okay"; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - imx51-apf51dev { - pinctrl_backlight: backlightgrp { - fsl,pins = < - MX51_PAD_DI1_D1_CS__GPIO3_4 0x1F5 - >; - }; - - pinctrl_hog: hoggrp { - fsl,pins = < - MX51_PAD_EIM_EB2__GPIO2_22 0x0C5 - MX51_PAD_EIM_EB3__GPIO2_23 0x0C5 - MX51_PAD_EIM_CS4__GPIO2_29 0x100 - MX51_PAD_NANDF_D13__GPIO3_27 0x0C5 - MX51_PAD_NANDF_D12__GPIO3_28 0x0C5 - MX51_PAD_CSPI1_SS0__GPIO4_24 0x0C5 - MX51_PAD_CSPI1_SS1__GPIO4_25 0x0C5 - MX51_PAD_GPIO1_2__GPIO1_2 0x0C5 - MX51_PAD_GPIO1_3__GPIO1_3 0x0C5 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185 - MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185 - MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185 - >; - }; - - pinctrl_ecspi2: ecspi2grp { - fsl,pins = < - MX51_PAD_NANDF_RB3__ECSPI2_MISO 0x185 - MX51_PAD_NANDF_D15__ECSPI2_MOSI 0x185 - MX51_PAD_NANDF_RB2__ECSPI2_SCLK 0x185 - >; - }; - - pinctrl_esdhc1: esdhc1grp { - fsl,pins = < - MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5 - MX51_PAD_SD1_CLK__SD1_CLK 0x20d5 - MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5 - MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5 - MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5 - MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5 - >; - }; - - pinctrl_esdhc2: esdhc2grp { - fsl,pins = < - MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5 - MX51_PAD_SD2_CLK__SD2_CLK 0x20d5 - MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5 - MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5 - MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5 - MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX51_PAD_EIM_D27__I2C2_SCL 0x400001ed - MX51_PAD_EIM_D24__I2C2_SDA 0x400001ed - >; - }; - - pinctrl_ipu_disp1: ipudisp1grp { - fsl,pins = < - MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5 - MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5 - MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5 - MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5 - MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5 - MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5 - MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5 - MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5 - MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5 - MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5 - MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5 - MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5 - MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5 - MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5 - MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5 - MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5 - MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5 - MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5 - MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5 - MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5 - MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5 - MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5 - MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5 - MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5 - MX51_PAD_DI1_PIN2__DI1_PIN2 0x5 - MX51_PAD_DI1_PIN3__DI1_PIN3 0x5 - >; - }; - }; -}; - -&ipu_di0_disp1 { - remote-endpoint = <&display_in>; -}; diff --git a/sys/gnu/dts/arm/imx51-babbage.dts b/sys/gnu/dts/arm/imx51-babbage.dts deleted file mode 100644 index 552196d8a60..00000000000 --- a/sys/gnu/dts/arm/imx51-babbage.dts +++ /dev/null @@ -1,726 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// -// Copyright 2011 Freescale Semiconductor, Inc. -// Copyright 2011 Linaro Ltd. - -/dts-v1/; -#include "imx51.dtsi" - -/ { - model = "Freescale i.MX51 Babbage Board"; - compatible = "fsl,imx51-babbage", "fsl,imx51"; - - chosen { - stdout-path = &uart1; - }; - - memory@90000000 { - device_type = "memory"; - reg = <0x90000000 0x20000000>; - }; - - ckih1 { - clock-frequency = <22579200>; - }; - - clk_osc: clk-osc { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <26000000>; - }; - - clk_osc_gate: clk-osc-gate { - compatible = "gpio-gate-clock"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_clk26mhz_osc>; - clocks = <&clk_osc>; - #clock-cells = <0>; - enable-gpios = <&gpio3 1 GPIO_ACTIVE_HIGH>; - }; - - clk_audio: clk-audio { - compatible = "gpio-gate-clock"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_clk26mhz_audio>; - clocks = <&clk_osc_gate>; - #clock-cells = <0>; - enable-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; - }; - - clk_usb: clk-usb { - compatible = "gpio-gate-clock"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_clk26mhz_usb>; - clocks = <&clk_osc_gate>; - #clock-cells = <0>; - enable-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; - }; - - display1: disp1 { - compatible = "fsl,imx-parallel-display"; - #address-cells = <1>; - #size-cells = <0>; - interface-pix-fmt = "rgb24"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu_disp1>; - - port@0 { - reg = <0>; - - display0_in: endpoint { - remote-endpoint = <&ipu_di0_disp1>; - }; - }; - - port@1 { - reg = <1>; - - parallel_display_out: endpoint { - remote-endpoint = <&tfp410_in>; - }; - }; - }; - - display2: disp2 { - compatible = "fsl,imx-parallel-display"; - interface-pix-fmt = "rgb565"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu_disp2>; - status = "disabled"; - display-timings { - native-mode = <&timing1>; - timing1: claawvga { - clock-frequency = <27000000>; - hactive = <800>; - vactive = <480>; - hback-porch = <40>; - hfront-porch = <60>; - vback-porch = <10>; - vfront-porch = <10>; - hsync-len = <20>; - vsync-len = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - }; - - port { - display1_in: endpoint { - remote-endpoint = <&ipu_di1_disp2>; - }; - }; - }; - - dvi-connector { - compatible = "dvi-connector"; - digital; - - port { - dvi_connector_in: endpoint { - remote-endpoint = <&tfp410_out>; - }; - }; - }; - - dvi-encoder { - compatible = "ti,tfp410"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - tfp410_in: endpoint { - remote-endpoint = <¶llel_display_out>; - }; - }; - - port@1 { - reg = <1>; - - tfp410_out: endpoint { - remote-endpoint = <&dvi_connector_in>; - }; - }; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_keys>; - - power { - label = "Power Button"; - gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>; - linux,code = ; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led-diagnostic { - label = "diagnostic"; - gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_hub_reset: regulator@0 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotgreg>; - reg = <0>; - regulator-name = "hub_reset"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - }; - - sound { - compatible = "fsl,imx51-babbage-sgtl5000", - "fsl,imx-audio-sgtl5000"; - model = "imx51-babbage-sgtl5000"; - ssi-controller = <&ssi2>; - audio-codec = <&sgtl5000>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - mux-int-port = <2>; - mux-ext-port = <3>; - }; - - usbphy1: usbphy1 { - compatible = "usb-nop-xceiv"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh1reg>; - clocks = <&clk_usb>; - clock-names = "main_clk"; - reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; - vcc-supply = <&vusb_reg>; - #phy-cells = <0>; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; - -&ecspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>, - <&gpio4 25 GPIO_ACTIVE_LOW>; - status = "okay"; - - pmic: mc13892@0 { - compatible = "fsl,mc13892"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - spi-max-frequency = <6000000>; - spi-cs-high; - reg = <0>; - interrupt-parent = <&gpio1>; - interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; - fsl,mc13xxx-uses-adc; - fsl,mc13xxx-uses-rtc; - - regulators { - sw1_reg: sw1 { - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1375000>; - regulator-boot-on; - regulator-always-on; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1850000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3_reg: sw3 { - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1850000>; - regulator-boot-on; - regulator-always-on; - }; - - sw4_reg: sw4 { - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1850000>; - regulator-boot-on; - regulator-always-on; - }; - - vpll_reg: vpll { - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - vdig_reg: vdig { - regulator-min-microvolt = <1650000>; - regulator-max-microvolt = <1650000>; - regulator-boot-on; - }; - - vsd_reg: vsd { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3150000>; - }; - - vusb_reg: vusb { - regulator-boot-on; - }; - - vusb2_reg: vusb2 { - regulator-min-microvolt = <2400000>; - regulator-max-microvolt = <2775000>; - regulator-boot-on; - regulator-always-on; - }; - - vvideo_reg: vvideo { - regulator-min-microvolt = <2775000>; - regulator-max-microvolt = <2775000>; - }; - - vaudio_reg: vaudio { - regulator-min-microvolt = <2300000>; - regulator-max-microvolt = <3000000>; - }; - - vcam_reg: vcam { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <3000000>; - }; - - vgen1_reg: vgen1 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - vgen2_reg: vgen2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3150000>; - regulator-always-on; - }; - - vgen3_reg: vgen3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2900000>; - regulator-always-on; - }; - }; - }; - - flash: at45db321d@1 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "atmel,at45db321d", "atmel,at45", "atmel,dataflash"; - spi-max-frequency = <25000000>; - reg = <1>; - - partition@0 { - label = "U-Boot"; - reg = <0x0 0x40000>; - read-only; - }; - - partition@40000 { - label = "Kernel"; - reg = <0x40000 0x3c0000>; - }; - }; -}; - -&esdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc1>; - cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&esdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc2>; - cd-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec>; - phy-mode = "mii"; - phy-reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>; - phy-reset-duration = <1>; - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - sgtl5000: codec@a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - #sound-dai-cells = <0>; - clocks = <&clk_audio>; - VDDA-supply = <&vdig_reg>; - VDDIO-supply = <&vvideo_reg>; - }; -}; - -&ipu_di0_disp1 { - remote-endpoint = <&display0_in>; -}; - -&ipu_di1_disp2 { - remote-endpoint = <&display1_in>; -}; - -&kpp { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_kpp>; - linux,keymap = < - MATRIX_KEY(0, 0, KEY_UP) - MATRIX_KEY(0, 1, KEY_DOWN) - MATRIX_KEY(0, 2, KEY_VOLUMEDOWN) - MATRIX_KEY(0, 3, KEY_HOME) - MATRIX_KEY(1, 0, KEY_RIGHT) - MATRIX_KEY(1, 1, KEY_LEFT) - MATRIX_KEY(1, 2, KEY_ENTER) - MATRIX_KEY(1, 3, KEY_VOLUMEUP) - MATRIX_KEY(2, 0, KEY_F6) - MATRIX_KEY(2, 1, KEY_F8) - MATRIX_KEY(2, 2, KEY_F9) - MATRIX_KEY(2, 3, KEY_F10) - MATRIX_KEY(3, 0, KEY_F1) - MATRIX_KEY(3, 1, KEY_F2) - MATRIX_KEY(3, 2, KEY_F3) - MATRIX_KEY(3, 3, KEY_POWER) - >; - status = "okay"; -}; - -&pmu { - secure-reg-access; -}; - -&ssi2 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - uart-has-rtscts; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - uart-has-rtscts; - status = "okay"; -}; - -&usbh1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh1>; - vbus-supply = <®_hub_reset>; - fsl,usbphy = <&usbphy1>; - phy_type = "ulpi"; - status = "okay"; -}; - -&usbphy0 { - vcc-supply = <&vusb_reg>; -}; - -&usbotg { - dr_mode = "otg"; - disable-over-current; - phy_type = "utmi_wide"; - status = "okay"; -}; - -&iomuxc { - imx51-babbage { - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000 - MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000 - MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x80000000 - MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000 - >; - }; - - pinctrl_clk26mhz_audio: clk26mhzaudiocgrp { - fsl,pins = < - MX51_PAD_CSPI1_RDY__GPIO4_26 0x85 - >; - }; - - pinctrl_clk26mhz_osc: clk26mhzoscgrp { - fsl,pins = < - MX51_PAD_DI1_PIN12__GPIO3_1 0x85 - >; - }; - - pinctrl_clk26mhz_usb: clk26mhzusbgrp { - fsl,pins = < - MX51_PAD_EIM_D17__GPIO2_1 0x85 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185 - MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185 - MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185 - MX51_PAD_CSPI1_SS0__GPIO4_24 0x85 /* CS0 */ - MX51_PAD_CSPI1_SS1__GPIO4_25 0x85 /* CS1 */ - >; - }; - - pinctrl_esdhc1: esdhc1grp { - fsl,pins = < - MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5 - MX51_PAD_SD1_CLK__SD1_CLK 0x20d5 - MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5 - MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5 - MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5 - MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5 - MX51_PAD_GPIO1_0__GPIO1_0 0x100 - MX51_PAD_GPIO1_1__GPIO1_1 0x100 - >; - }; - - pinctrl_esdhc2: esdhc2grp { - fsl,pins = < - MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5 - MX51_PAD_SD2_CLK__SD2_CLK 0x20d5 - MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5 - MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5 - MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5 - MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5 - MX51_PAD_GPIO1_5__GPIO1_5 0x100 /* WP */ - MX51_PAD_GPIO1_6__GPIO1_6 0x100 /* CD */ - >; - }; - - pinctrl_fec: fecgrp { - fsl,pins = < - MX51_PAD_EIM_EB2__FEC_MDIO 0x000001f5 - MX51_PAD_EIM_EB3__FEC_RDATA1 0x00000085 - MX51_PAD_EIM_CS2__FEC_RDATA2 0x00000085 - MX51_PAD_EIM_CS3__FEC_RDATA3 0x00000085 - MX51_PAD_EIM_CS4__FEC_RX_ER 0x00000180 - MX51_PAD_EIM_CS5__FEC_CRS 0x00000180 - MX51_PAD_NANDF_RB2__FEC_COL 0x00000180 - MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x00000180 - MX51_PAD_NANDF_D9__FEC_RDATA0 0x00002180 - MX51_PAD_NANDF_D8__FEC_TDATA0 0x00002004 - MX51_PAD_NANDF_CS2__FEC_TX_ER 0x00002004 - MX51_PAD_NANDF_CS3__FEC_MDC 0x00002004 - MX51_PAD_NANDF_CS4__FEC_TDATA1 0x00002004 - MX51_PAD_NANDF_CS5__FEC_TDATA2 0x00002004 - MX51_PAD_NANDF_CS6__FEC_TDATA3 0x00002004 - MX51_PAD_NANDF_CS7__FEC_TX_EN 0x00002004 - MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x00002180 - MX51_PAD_NANDF_D11__FEC_RX_DV 0x000020a4 - MX51_PAD_EIM_A20__GPIO2_14 0x00000085 /* Phy Reset */ - >; - }; - - pinctrl_gpio_keys: gpiokeysgrp { - fsl,pins = < - MX51_PAD_EIM_A27__GPIO2_21 0x5 - >; - }; - - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - MX51_PAD_EIM_D22__GPIO2_6 0x80000000 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX51_PAD_EIM_D19__I2C1_SCL 0x400001ed - MX51_PAD_EIM_D16__I2C1_SDA 0x400001ed - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed - MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed - >; - }; - - pinctrl_ipu_disp1: ipudisp1grp { - fsl,pins = < - MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5 - MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5 - MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5 - MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5 - MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5 - MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5 - MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5 - MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5 - MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5 - MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5 - MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5 - MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5 - MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5 - MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5 - MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5 - MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5 - MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5 - MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5 - MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5 - MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5 - MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5 - MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5 - MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5 - MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5 - MX51_PAD_DI1_PIN2__DI1_PIN2 0x5 - MX51_PAD_DI1_PIN3__DI1_PIN3 0x5 - >; - }; - - pinctrl_ipu_disp2: ipudisp2grp { - fsl,pins = < - MX51_PAD_DISP2_DAT0__DISP2_DAT0 0x5 - MX51_PAD_DISP2_DAT1__DISP2_DAT1 0x5 - MX51_PAD_DISP2_DAT2__DISP2_DAT2 0x5 - MX51_PAD_DISP2_DAT3__DISP2_DAT3 0x5 - MX51_PAD_DISP2_DAT4__DISP2_DAT4 0x5 - MX51_PAD_DISP2_DAT5__DISP2_DAT5 0x5 - MX51_PAD_DISP2_DAT6__DISP2_DAT6 0x5 - MX51_PAD_DISP2_DAT7__DISP2_DAT7 0x5 - MX51_PAD_DISP2_DAT8__DISP2_DAT8 0x5 - MX51_PAD_DISP2_DAT9__DISP2_DAT9 0x5 - MX51_PAD_DISP2_DAT10__DISP2_DAT10 0x5 - MX51_PAD_DISP2_DAT11__DISP2_DAT11 0x5 - MX51_PAD_DISP2_DAT12__DISP2_DAT12 0x5 - MX51_PAD_DISP2_DAT13__DISP2_DAT13 0x5 - MX51_PAD_DISP2_DAT14__DISP2_DAT14 0x5 - MX51_PAD_DISP2_DAT15__DISP2_DAT15 0x5 - MX51_PAD_DI2_PIN2__DI2_PIN2 0x5 - MX51_PAD_DI2_PIN3__DI2_PIN3 0x5 - MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5 - MX51_PAD_DI_GP4__DI2_PIN15 0x5 - >; - }; - - pinctrl_kpp: kppgrp { - fsl,pins = < - MX51_PAD_KEY_ROW0__KEY_ROW0 0xe0 - MX51_PAD_KEY_ROW1__KEY_ROW1 0xe0 - MX51_PAD_KEY_ROW2__KEY_ROW2 0xe0 - MX51_PAD_KEY_ROW3__KEY_ROW3 0xe0 - MX51_PAD_KEY_COL0__KEY_COL0 0xe8 - MX51_PAD_KEY_COL1__KEY_COL1 0xe8 - MX51_PAD_KEY_COL2__KEY_COL2 0xe8 - MX51_PAD_KEY_COL3__KEY_COL3 0xe8 - >; - }; - - pinctrl_pmic: pmicgrp { - fsl,pins = < - MX51_PAD_GPIO1_8__GPIO1_8 0xe5 /* IRQ */ - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX51_PAD_UART1_RXD__UART1_RXD 0x1c5 - MX51_PAD_UART1_TXD__UART1_TXD 0x1c5 - MX51_PAD_UART1_RTS__UART1_RTS 0x1c5 - MX51_PAD_UART1_CTS__UART1_CTS 0x1c5 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX51_PAD_UART2_RXD__UART2_RXD 0x1c5 - MX51_PAD_UART2_TXD__UART2_TXD 0x1c5 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX51_PAD_EIM_D25__UART3_RXD 0x1c5 - MX51_PAD_EIM_D26__UART3_TXD 0x1c5 - MX51_PAD_EIM_D27__UART3_RTS 0x1c5 - MX51_PAD_EIM_D24__UART3_CTS 0x1c5 - >; - }; - - pinctrl_usbh1: usbh1grp { - fsl,pins = < - MX51_PAD_USBH1_CLK__USBH1_CLK 0x80000000 - MX51_PAD_USBH1_DIR__USBH1_DIR 0x80000000 - MX51_PAD_USBH1_NXT__USBH1_NXT 0x80000000 - MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x80000000 - MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x80000000 - MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x80000000 - MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x80000000 - MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x80000000 - MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x80000000 - MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x80000000 - MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x80000000 - >; - }; - - pinctrl_usbh1reg: usbh1reggrp { - fsl,pins = < - MX51_PAD_EIM_D21__GPIO2_5 0x85 - >; - }; - - pinctrl_usbotgreg: usbotgreggrp { - fsl,pins = < - MX51_PAD_GPIO1_7__GPIO1_7 0x85 - >; - }; - }; -}; diff --git a/sys/gnu/dts/arm/imx51-digi-connectcore-jsk.dts b/sys/gnu/dts/arm/imx51-digi-connectcore-jsk.dts deleted file mode 100644 index aab8d6f137c..00000000000 --- a/sys/gnu/dts/arm/imx51-digi-connectcore-jsk.dts +++ /dev/null @@ -1,118 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (C) 2014 Alexander Shiyan - */ - -#include "imx51-digi-connectcore-som.dtsi" - -/ { - model = "Digi ConnectCore CC(W)-MX51 JSK"; - compatible = "digi,connectcore-ccxmx51-jsk", - "digi,connectcore-ccxmx51-som", "fsl,imx51"; - - chosen { - stdout-path = &uart1; - }; -}; - -&esdhc1 { - status = "okay"; -}; - -&owire { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_owire>; - status = "okay"; -}; - -&pmic { - fsl,mc13xxx-uses-rtc; - - regulators { - vcoincell_reg: vcoincell { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - }; - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -&usbotg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbh1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh1>; - dr_mode = "host"; - phy_type = "ulpi"; - disable-over-current; - status = "okay"; -}; - -&iomuxc { - imx51-digi-connectcore-jsk { - pinctrl_owire: owiregrp { - fsl,pins = < - MX51_PAD_OWIRE_LINE__OWIRE_LINE 0x40000000 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX51_PAD_UART1_RXD__UART1_RXD 0x1c5 - MX51_PAD_UART1_TXD__UART1_TXD 0x1c5 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX51_PAD_UART2_RXD__UART2_RXD 0x1c5 - MX51_PAD_UART2_TXD__UART2_TXD 0x1c5 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX51_PAD_UART3_RXD__UART3_RXD 0x1c5 - MX51_PAD_UART3_TXD__UART3_TXD 0x1c5 - >; - }; - - pinctrl_usbh1: usbh1grp { - fsl,pins = < - MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x1e5 - MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x1e5 - MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x1e5 - MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x1e5 - MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x1e5 - MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x1e5 - MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x1e5 - MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x1e5 - MX51_PAD_USBH1_CLK__USBH1_CLK 0x1e5 - MX51_PAD_USBH1_DIR__USBH1_DIR 0x1e5 - MX51_PAD_USBH1_NXT__USBH1_NXT 0x1e5 - MX51_PAD_USBH1_STP__USBH1_STP 0x1e5 - >; - }; - }; -}; diff --git a/sys/gnu/dts/arm/imx51-digi-connectcore-som.dtsi b/sys/gnu/dts/arm/imx51-digi-connectcore-som.dtsi deleted file mode 100644 index 16addb3a2a1..00000000000 --- a/sys/gnu/dts/arm/imx51-digi-connectcore-som.dtsi +++ /dev/null @@ -1,389 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (C) 2014 Alexander Shiyan - */ - -/dts-v1/; -#include "imx51.dtsi" - -/ { - model = "Digi ConnectCore CC(W)-MX51"; - compatible = "digi,connectcore-ccxmx51-som", "fsl,imx51"; - - memory@90000000 { - device_type = "memory"; - reg = <0x90000000 0x08000000>; - }; -}; - -&ecspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>; - status = "okay"; - - pmic: mc13892@0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mc13892>; - compatible = "fsl,mc13892"; - spi-max-frequency = <16000000>; - spi-cs-high; - reg = <0>; - interrupt-parent = <&gpio1>; - interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; - - regulators { - sw1_reg: sw1 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1100000>; - regulator-boot-on; - regulator-always-on; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3_reg: sw3 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-boot-on; - regulator-always-on; - }; - - swbst_reg: swbst { }; - - viohi_reg: viohi { - regulator-always-on; - }; - - vpll_reg: vpll { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vdig_reg: vdig { - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1250000>; - regulator-always-on; - }; - - vsd_reg: vsd { - regulator-min-microvolt = <3150000>; - regulator-max-microvolt = <3150000>; - regulator-always-on; - }; - - vusb2_reg: vusb2 { - regulator-min-microvolt = <2600000>; - regulator-max-microvolt = <2600000>; - regulator-always-on; - }; - - vvideo_reg: vvideo { - regulator-min-microvolt = <2775000>; - regulator-max-microvolt = <2775000>; - regulator-always-on; - }; - - vaudio_reg: vaudio { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - }; - - vcam_reg: vcam { - regulator-min-microvolt = <2750000>; - regulator-max-microvolt = <2750000>; - regulator-always-on; - }; - - vgen1_reg: vgen1 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - vgen2_reg: vgen2 { - regulator-min-microvolt = <3150000>; - regulator-max-microvolt = <3150000>; - regulator-always-on; - }; - - vgen3_reg: vgen3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vusb_reg: vusb { - regulator-always-on; - }; - - gpo1_reg: gpo1 { }; - - gpo2_reg: gpo2 { }; - - gpo3_reg: gpo3 { }; - - gpo4_reg: gpo4 { }; - - pwgt2spi_reg: pwgt2spi { - regulator-always-on; - }; - }; - }; -}; - -&esdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc1>; - max-frequency = <50000000>; - bus-width = <1>; -}; - -&esdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc2>; - cap-sdio-irq; - wakeup-source; - keep-power-in-suspend; - max-frequency = <50000000>; - no-1-8-v; - non-removable; - vmmc-supply = <&gpo4_reg>; - status = "okay"; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec>; - phy-mode = "mii"; - phy-supply = <&gpo3_reg>; - /* Pins shared with LCD2, keep status disabled */ -}; - -&i2c2 { - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c2>; - pinctrl-1 = <&pinctrl_i2c2_gpio>; - clock-frequency = <400000>; - scl-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; - status = "okay"; - - mma7455l@1d { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mma7455l>; - compatible = "fsl,mma7455l"; - reg = <0x1d>; - interrupt-parent = <&gpio1>; - interrupts = <7 IRQ_TYPE_LEVEL_HIGH>, <6 IRQ_TYPE_LEVEL_HIGH>; - }; -}; - -&nfc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nfc>; - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - nand-on-flash-bbt; - status = "okay"; -}; - -&usbotg { - phy_type = "utmi_wide"; - disable-over-current; - /* Device role is not known, keep status disabled */ -}; - -&weim { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_weim>; - status = "okay"; - - lan9221: lan9221@5,0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lan9221>; - compatible = "smsc,lan9221", "smsc,lan9115"; - reg = <5 0x00000000 0x1000>; - fsl,weim-cs-timing = < - 0x00420081 0x00000000 - 0x32260000 0x00000000 - 0x72080f00 0x00000000 - >; - clocks = <&clks IMX5_CLK_DUMMY>; - interrupt-parent = <&gpio1>; - interrupts = <9 IRQ_TYPE_LEVEL_LOW>; - phy-mode = "mii"; - reg-io-width = <2>; - smsc,irq-push-pull; - vdd33a-supply = <&gpo2_reg>; - vddvario-supply = <&gpo2_reg>; - }; -}; - -&iomuxc { - imx51-digi-connectcore-som { - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185 - MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185 - MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185 - MX51_PAD_CSPI1_SS0__GPIO4_24 0x85 /* CS0 */ - >; - }; - - pinctrl_esdhc1: esdhc1grp { - fsl,pins = < - MX51_PAD_SD1_CLK__SD1_CLK 0x400021d5 - MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5 - MX51_PAD_SD1_DATA0__SD1_DATA0 0x400020d5 - >; - }; - - pinctrl_esdhc2: esdhc2grp { - fsl,pins = < - MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5 - MX51_PAD_SD2_CLK__SD2_CLK 0x20d5 - MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5 - MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5 - MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5 - MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5 - >; - }; - - pinctrl_fec: fecgrp { - fsl,pins = < - MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000 - MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000 - MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000 - MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000 - MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000 - MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000 - MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000 - MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000 - MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000 - MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000 - MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000 - MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000 - MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000 - MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000 - MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000 - MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000 - MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000 - MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX51_PAD_GPIO1_2__I2C2_SCL 0x400001ed - MX51_PAD_GPIO1_3__I2C2_SDA 0x400001ed - >; - }; - - pinctrl_i2c2_gpio: i2c2gpiogrp { - fsl,pins = < - MX51_PAD_GPIO1_2__GPIO1_2 0x400001ed - MX51_PAD_GPIO1_3__GPIO1_3 0x400001ed - >; - }; - - pinctrl_nfc: nfcgrp { - fsl,pins = < - MX51_PAD_NANDF_D0__NANDF_D0 0x80000000 - MX51_PAD_NANDF_D1__NANDF_D1 0x80000000 - MX51_PAD_NANDF_D2__NANDF_D2 0x80000000 - MX51_PAD_NANDF_D3__NANDF_D3 0x80000000 - MX51_PAD_NANDF_D4__NANDF_D4 0x80000000 - MX51_PAD_NANDF_D5__NANDF_D5 0x80000000 - MX51_PAD_NANDF_D6__NANDF_D6 0x80000000 - MX51_PAD_NANDF_D7__NANDF_D7 0x80000000 - MX51_PAD_NANDF_ALE__NANDF_ALE 0x80000000 - MX51_PAD_NANDF_CLE__NANDF_CLE 0x80000000 - MX51_PAD_NANDF_RE_B__NANDF_RE_B 0x80000000 - MX51_PAD_NANDF_WE_B__NANDF_WE_B 0x80000000 - MX51_PAD_NANDF_WP_B__NANDF_WP_B 0x80000000 - MX51_PAD_NANDF_CS0__NANDF_CS0 0x80000000 - MX51_PAD_NANDF_RB0__NANDF_RB0 0x80000000 - >; - }; - - pinctrl_lan9221: lan9221grp { - fsl,pins = < - MX51_PAD_GPIO1_9__GPIO1_9 0xe5 /* IRQ */ - >; - }; - - pinctrl_mc13892: mc13892grp { - fsl,pins = < - MX51_PAD_GPIO1_5__GPIO1_5 0xe5 /* IRQ */ - >; - }; - - pinctrl_mma7455l: mma7455lgrp { - fsl,pins = < - MX51_PAD_GPIO1_7__GPIO1_7 0xe5 /* IRQ1 */ - MX51_PAD_GPIO1_6__GPIO1_6 0xe5 /* IRQ2 */ - >; - }; - - pinctrl_weim: weimgrp { - fsl,pins = < - MX51_PAD_EIM_DA0__EIM_DA0 0x80000000 - MX51_PAD_EIM_DA1__EIM_DA1 0x80000000 - MX51_PAD_EIM_DA2__EIM_DA2 0x80000000 - MX51_PAD_EIM_DA3__EIM_DA3 0x80000000 - MX51_PAD_EIM_DA4__EIM_DA4 0x80000000 - MX51_PAD_EIM_DA5__EIM_DA5 0x80000000 - MX51_PAD_EIM_DA6__EIM_DA6 0x80000000 - MX51_PAD_EIM_DA7__EIM_DA7 0x80000000 - MX51_PAD_EIM_DA8__EIM_DA8 0x80000000 - MX51_PAD_EIM_DA9__EIM_DA9 0x80000000 - MX51_PAD_EIM_DA10__EIM_DA10 0x80000000 - MX51_PAD_EIM_DA11__EIM_DA11 0x80000000 - MX51_PAD_EIM_DA12__EIM_DA12 0x80000000 - MX51_PAD_EIM_DA13__EIM_DA13 0x80000000 - MX51_PAD_EIM_DA14__EIM_DA14 0x80000000 - MX51_PAD_EIM_DA15__EIM_DA15 0x80000000 - MX51_PAD_EIM_A16__EIM_A16 0x80000000 - MX51_PAD_EIM_A17__EIM_A17 0x80000000 - MX51_PAD_EIM_A18__EIM_A18 0x80000000 - MX51_PAD_EIM_A19__EIM_A19 0x80000000 - MX51_PAD_EIM_A20__EIM_A20 0x80000000 - MX51_PAD_EIM_A21__EIM_A21 0x80000000 - MX51_PAD_EIM_A22__EIM_A22 0x80000000 - MX51_PAD_EIM_A23__EIM_A23 0x80000000 - MX51_PAD_EIM_A24__EIM_A24 0x80000000 - MX51_PAD_EIM_A25__EIM_A25 0x80000000 - MX51_PAD_EIM_A26__EIM_A26 0x80000000 - MX51_PAD_EIM_A27__EIM_A27 0x80000000 - MX51_PAD_EIM_D16__EIM_D16 0x80000000 - MX51_PAD_EIM_D17__EIM_D17 0x80000000 - MX51_PAD_EIM_D18__EIM_D18 0x80000000 - MX51_PAD_EIM_D19__EIM_D19 0x80000000 - MX51_PAD_EIM_D20__EIM_D20 0x80000000 - MX51_PAD_EIM_D21__EIM_D21 0x80000000 - MX51_PAD_EIM_D22__EIM_D22 0x80000000 - MX51_PAD_EIM_D23__EIM_D23 0x80000000 - MX51_PAD_EIM_D24__EIM_D24 0x80000000 - MX51_PAD_EIM_D25__EIM_D25 0x80000000 - MX51_PAD_EIM_D26__EIM_D26 0x80000000 - MX51_PAD_EIM_D27__EIM_D27 0x80000000 - MX51_PAD_EIM_D28__EIM_D28 0x80000000 - MX51_PAD_EIM_D29__EIM_D29 0x80000000 - MX51_PAD_EIM_D30__EIM_D30 0x80000000 - MX51_PAD_EIM_D31__EIM_D31 0x80000000 - MX51_PAD_EIM_OE__EIM_OE 0x80000000 - MX51_PAD_EIM_DTACK__EIM_DTACK 0x80000000 - MX51_PAD_EIM_LBA__EIM_LBA 0x80000000 - MX51_PAD_EIM_CS5__EIM_CS5 0x80000000 /* CS5 */ - >; - }; - }; -}; diff --git a/sys/gnu/dts/arm/imx51-eukrea-cpuimx51.dtsi b/sys/gnu/dts/arm/imx51-eukrea-cpuimx51.dtsi deleted file mode 100644 index c2a929ba8ce..00000000000 --- a/sys/gnu/dts/arm/imx51-eukrea-cpuimx51.dtsi +++ /dev/null @@ -1,92 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Eukréa Electromatique - */ - -#include "imx51.dtsi" - -/ { - model = "Eukrea CPUIMX51"; - compatible = "eukrea,cpuimx51", "fsl,imx51"; - - memory@90000000 { - device_type = "memory"; - reg = <0x90000000 0x10000000>; /* 256M */ - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec>; - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pcf8563@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; - - tsc2007: tsc2007@49 { - compatible = "ti,tsc2007"; - gpios = <&gpio4 0 1>; - interrupt-parent = <&gpio4>; - interrupts = <0x0 0x8>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_tsc2007_1>; - reg = <0x49>; - ti,x-plate-ohms = <180>; - }; -}; - -&iomuxc { - imx51-eukrea { - pinctrl_tsc2007_1: tsc2007grp-1 { - fsl,pins = < - MX51_PAD_GPIO_NAND__GPIO_NAND 0x1f5 - MX51_PAD_NANDF_D8__GPIO4_0 0x1f5 - >; - }; - - pinctrl_fec: fecgrp { - fsl,pins = < - MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000 - MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000 - MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000 - MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000 - MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000 - MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000 - MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000 - MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000 - MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000 - MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000 - MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000 - MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000 - MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000 - MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000 - MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000 - MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000 - MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000 - MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX51_PAD_SD2_CMD__I2C1_SCL 0x400001ed - MX51_PAD_SD2_CLK__I2C1_SDA 0x400001ed - >; - }; - }; -}; - -&nfc { - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - nand-on-flash-bbt; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx51-eukrea-mbimxsd51-baseboard.dts b/sys/gnu/dts/arm/imx51-eukrea-mbimxsd51-baseboard.dts deleted file mode 100644 index b6d931e96a8..00000000000 --- a/sys/gnu/dts/arm/imx51-eukrea-mbimxsd51-baseboard.dts +++ /dev/null @@ -1,274 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Eukréa Electromatique - */ - -/dts-v1/; -#include "imx51-eukrea-cpuimx51.dtsi" -#include - -/ { - model = "Eukrea CPUIMX51"; - compatible = "eukrea,mbimxsd51","eukrea,cpuimx51", "fsl,imx51"; - - clocks { - clk24M: can_clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpiokeys_1>; - - button-1 { - label = "BP1"; - gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; - linux,code = <256>; - wakeup-source; - linux,input-type = <1>; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpioled>; - - led1 { - label = "led1"; - gpios = <&gpio3 30 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_can: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "CAN_RST"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; - startup-delay-us = <20000>; - enable-active-high; - }; - }; - - sound { - compatible = "eukrea,asoc-tlv320"; - eukrea,model = "imx51-eukrea-tlv320aic23"; - ssi-controller = <&ssi2>; - fsl,mux-int-port = <2>; - fsl,mux-ext-port = <3>; - }; - - usbphy1: usbphy1 { - compatible = "usb-nop-xceiv"; - clocks = <&clks IMX5_CLK_USB_PHY_GATE>; - clock-names = "main_clk"; - clock-frequency = <19200000>; - #phy-cells = <0>; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; - -&esdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc1 &pinctrl_esdhc1_cd>; - cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&ecspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; - status = "okay"; - - can0: can@0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can>; - compatible = "microchip,mcp2515"; - reg = <0>; - clocks = <&clk24M>; - spi-max-frequency = <10000000>; - interrupt-parent = <&gpio1>; - interrupts = <1 IRQ_TYPE_EDGE_FALLING>; - vdd-supply = <®_can>; - }; -}; - -&i2c1 { - tlv320aic23: codec@1a { - compatible = "ti,tlv320aic23"; - reg = <0x1a>; - }; -}; - -&iomuxc { - imx51-eukrea { - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000 - MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000 - MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x80000000 - MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000 - >; - }; - - - pinctrl_can: cangrp { - fsl,pins = < - MX51_PAD_CSI2_PIXCLK__GPIO4_15 0x80000000 /* nReset */ - MX51_PAD_GPIO1_1__GPIO1_1 0x80000000 /* IRQ */ - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185 - MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185 - MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185 - MX51_PAD_CSPI1_SS0__GPIO4_24 0x80000000 /* CS0 */ - >; - }; - - pinctrl_esdhc1: esdhc1grp { - fsl,pins = < - MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5 - MX51_PAD_SD1_CLK__SD1_CLK 0x20d5 - MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5 - MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5 - MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5 - MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX51_PAD_UART1_RXD__UART1_RXD 0x1c5 - MX51_PAD_UART1_TXD__UART1_TXD 0x1c5 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX51_PAD_UART3_RXD__UART3_RXD 0x1c5 - MX51_PAD_UART3_TXD__UART3_TXD 0x1c5 - >; - }; - - pinctrl_uart3_rtscts: uart3rtsctsgrp { - fsl,pins = < - MX51_PAD_KEY_COL4__UART3_RTS 0x1c5 - MX51_PAD_KEY_COL5__UART3_CTS 0x1c5 - >; - }; - - pinctrl_backlight_1: backlightgrp-1 { - fsl,pins = < - MX51_PAD_DI1_D1_CS__GPIO3_4 0x1f5 - >; - }; - - pinctrl_esdhc1_cd: esdhc1_cd { - fsl,pins = < - MX51_PAD_GPIO1_0__GPIO1_0 0xd5 - >; - }; - - pinctrl_gpiokeys_1: gpiokeysgrp-1 { - fsl,pins = < - MX51_PAD_NANDF_D9__GPIO3_31 0x1f5 - >; - }; - - pinctrl_gpioled: gpioledgrp-1 { - fsl,pins = < - MX51_PAD_NANDF_D10__GPIO3_30 0x80000000 - >; - }; - - pinctrl_reg_lcd_3v3: reg_lcd_3v3 { - fsl,pins = < - MX51_PAD_CSI1_D9__GPIO3_13 0x1f5 - >; - }; - - pinctrl_usbh1: usbh1grp { - fsl,pins = < - MX51_PAD_USBH1_CLK__USBH1_CLK 0x1e5 - MX51_PAD_USBH1_DIR__USBH1_DIR 0x1e5 - MX51_PAD_USBH1_NXT__USBH1_NXT 0x1e5 - MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x1e5 - MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x1e5 - MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x1e5 - MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x1e5 - MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x1e5 - MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x1e5 - MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x1e5 - MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x1e5 - MX51_PAD_USBH1_STP__USBH1_STP 0x1e5 - >; - }; - - pinctrl_usbh1_vbus: usbh1-vbusgrp { - fsl,pins = < - MX51_PAD_EIM_CS3__GPIO2_28 0x1f5 - >; - }; - }; -}; - -&ssi2 { - codec-handle = <&tlv320aic23>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - uart-has-rtscts; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3 &pinctrl_uart3_rtscts>; - uart-has-rtscts; - status = "okay"; -}; - -&usbh1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh1>; - fsl,usbphy = <&usbphy1>; - dr_mode = "host"; - phy_type = "ulpi"; - status = "okay"; -}; - -&usbotg { - dr_mode = "otg"; - phy_type = "utmi_wide"; - status = "okay"; -}; - -&usbphy0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh1_vbus>; - reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; -}; diff --git a/sys/gnu/dts/arm/imx51-pinfunc.h b/sys/gnu/dts/arm/imx51-pinfunc.h deleted file mode 100644 index 910e0ec50ef..00000000000 --- a/sys/gnu/dts/arm/imx51-pinfunc.h +++ /dev/null @@ -1,768 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - */ - -#ifndef __DTS_IMX51_PINFUNC_H -#define __DTS_IMX51_PINFUNC_H - -/* - * The pin function ID is a tuple of - * - */ -#define MX51_PAD_EIM_D16__AUD4_RXFS 0x05c 0x3f0 0x000 0x5 0x0 -#define MX51_PAD_EIM_D16__AUD5_TXD 0x05c 0x3f0 0x8d8 0x7 0x0 -#define MX51_PAD_EIM_D16__EIM_D16 0x05c 0x3f0 0x000 0x0 0x0 -#define MX51_PAD_EIM_D16__GPIO2_0 0x05c 0x3f0 0x000 0x1 0x0 -#define MX51_PAD_EIM_D16__I2C1_SDA 0x05c 0x3f0 0x9b4 0x4 0x0 -#define MX51_PAD_EIM_D16__UART2_CTS 0x05c 0x3f0 0x000 0x3 0x0 -#define MX51_PAD_EIM_D16__USBH2_DATA0 0x05c 0x3f0 0x000 0x2 0x0 -#define MX51_PAD_EIM_D17__AUD5_RXD 0x060 0x3f4 0x8d4 0x7 0x0 -#define MX51_PAD_EIM_D17__EIM_D17 0x060 0x3f4 0x000 0x0 0x0 -#define MX51_PAD_EIM_D17__GPIO2_1 0x060 0x3f4 0x000 0x1 0x0 -#define MX51_PAD_EIM_D17__UART2_RXD 0x060 0x3f4 0x9ec 0x3 0x0 -#define MX51_PAD_EIM_D17__UART3_CTS 0x060 0x3f4 0x000 0x4 0x0 -#define MX51_PAD_EIM_D17__USBH2_DATA1 0x060 0x3f4 0x000 0x2 0x0 -#define MX51_PAD_EIM_D18__AUD5_TXC 0x064 0x3f8 0x8e4 0x7 0x0 -#define MX51_PAD_EIM_D18__EIM_D18 0x064 0x3f8 0x000 0x0 0x0 -#define MX51_PAD_EIM_D18__GPIO2_2 0x064 0x3f8 0x000 0x1 0x0 -#define MX51_PAD_EIM_D18__UART2_TXD 0x064 0x3f8 0x000 0x3 0x0 -#define MX51_PAD_EIM_D18__UART3_RTS 0x064 0x3f8 0x9f0 0x4 0x1 -#define MX51_PAD_EIM_D18__USBH2_DATA2 0x064 0x3f8 0x000 0x2 0x0 -#define MX51_PAD_EIM_D19__AUD4_RXC 0x068 0x3fc 0x000 0x5 0x0 -#define MX51_PAD_EIM_D19__AUD5_TXFS 0x068 0x3fc 0x8e8 0x7 0x0 -#define MX51_PAD_EIM_D19__EIM_D19 0x068 0x3fc 0x000 0x0 0x0 -#define MX51_PAD_EIM_D19__GPIO2_3 0x068 0x3fc 0x000 0x1 0x0 -#define MX51_PAD_EIM_D19__I2C1_SCL 0x068 0x3fc 0x9b0 0x4 0x0 -#define MX51_PAD_EIM_D19__UART2_RTS 0x068 0x3fc 0x9e8 0x3 0x1 -#define MX51_PAD_EIM_D19__USBH2_DATA3 0x068 0x3fc 0x000 0x2 0x0 -#define MX51_PAD_EIM_D20__AUD4_TXD 0x06c 0x400 0x8c8 0x5 0x0 -#define MX51_PAD_EIM_D20__EIM_D20 0x06c 0x400 0x000 0x0 0x0 -#define MX51_PAD_EIM_D20__GPIO2_4 0x06c 0x400 0x000 0x1 0x0 -#define MX51_PAD_EIM_D20__SRTC_ALARM_DEB 0x06c 0x400 0x000 0x4 0x0 -#define MX51_PAD_EIM_D20__USBH2_DATA4 0x06c 0x400 0x000 0x2 0x0 -#define MX51_PAD_EIM_D21__AUD4_RXD 0x070 0x404 0x8c4 0x5 0x0 -#define MX51_PAD_EIM_D21__EIM_D21 0x070 0x404 0x000 0x0 0x0 -#define MX51_PAD_EIM_D21__GPIO2_5 0x070 0x404 0x000 0x1 0x0 -#define MX51_PAD_EIM_D21__SRTC_ALARM_DEB 0x070 0x404 0x000 0x3 0x0 -#define MX51_PAD_EIM_D21__USBH2_DATA5 0x070 0x404 0x000 0x2 0x0 -#define MX51_PAD_EIM_D22__AUD4_TXC 0x074 0x408 0x8cc 0x5 0x0 -#define MX51_PAD_EIM_D22__EIM_D22 0x074 0x408 0x000 0x0 0x0 -#define MX51_PAD_EIM_D22__GPIO2_6 0x074 0x408 0x000 0x1 0x0 -#define MX51_PAD_EIM_D22__USBH2_DATA6 0x074 0x408 0x000 0x2 0x0 -#define MX51_PAD_EIM_D23__AUD4_TXFS 0x078 0x40c 0x8d0 0x5 0x0 -#define MX51_PAD_EIM_D23__EIM_D23 0x078 0x40c 0x000 0x0 0x0 -#define MX51_PAD_EIM_D23__GPIO2_7 0x078 0x40c 0x000 0x1 0x0 -#define MX51_PAD_EIM_D23__SPDIF_OUT1 0x078 0x40c 0x000 0x4 0x0 -#define MX51_PAD_EIM_D23__USBH2_DATA7 0x078 0x40c 0x000 0x2 0x0 -#define MX51_PAD_EIM_D24__AUD6_RXFS 0x07c 0x410 0x8f8 0x5 0x0 -#define MX51_PAD_EIM_D24__EIM_D24 0x07c 0x410 0x000 0x0 0x0 -#define MX51_PAD_EIM_D24__GPIO2_8 0x07c 0x410 0x000 0x1 0x0 -#define MX51_PAD_EIM_D24__I2C2_SDA 0x07c 0x410 0x9bc 0x4 0x0 -#define MX51_PAD_EIM_D24__UART3_CTS 0x07c 0x410 0x000 0x3 0x0 -#define MX51_PAD_EIM_D24__USBOTG_DATA0 0x07c 0x410 0x000 0x2 0x0 -#define MX51_PAD_EIM_D25__EIM_D25 0x080 0x414 0x000 0x0 0x0 -#define MX51_PAD_EIM_D25__KEY_COL6 0x080 0x414 0x9c8 0x1 0x0 -#define MX51_PAD_EIM_D25__UART2_CTS 0x080 0x414 0x000 0x4 0x0 -#define MX51_PAD_EIM_D25__UART3_RXD 0x080 0x414 0x9f4 0x3 0x0 -#define MX51_PAD_EIM_D25__USBOTG_DATA1 0x080 0x414 0x000 0x2 0x0 -#define MX51_PAD_EIM_D26__EIM_D26 0x084 0x418 0x000 0x0 0x0 -#define MX51_PAD_EIM_D26__KEY_COL7 0x084 0x418 0x9cc 0x1 0x0 -#define MX51_PAD_EIM_D26__UART2_RTS 0x084 0x418 0x9e8 0x4 0x3 -#define MX51_PAD_EIM_D26__UART3_TXD 0x084 0x418 0x000 0x3 0x0 -#define MX51_PAD_EIM_D26__USBOTG_DATA2 0x084 0x418 0x000 0x2 0x0 -#define MX51_PAD_EIM_D27__AUD6_RXC 0x088 0x41c 0x8f4 0x5 0x0 -#define MX51_PAD_EIM_D27__EIM_D27 0x088 0x41c 0x000 0x0 0x0 -#define MX51_PAD_EIM_D27__GPIO2_9 0x088 0x41c 0x000 0x1 0x0 -#define MX51_PAD_EIM_D27__I2C2_SCL 0x088 0x41c 0x9b8 0x4 0x0 -#define MX51_PAD_EIM_D27__UART3_RTS 0x088 0x41c 0x9f0 0x3 0x3 -#define MX51_PAD_EIM_D27__USBOTG_DATA3 0x088 0x41c 0x000 0x2 0x0 -#define MX51_PAD_EIM_D28__AUD6_TXD 0x08c 0x420 0x8f0 0x5 0x0 -#define MX51_PAD_EIM_D28__EIM_D28 0x08c 0x420 0x000 0x0 0x0 -#define MX51_PAD_EIM_D28__KEY_ROW4 0x08c 0x420 0x9d0 0x1 0x0 -#define MX51_PAD_EIM_D28__USBOTG_DATA4 0x08c 0x420 0x000 0x2 0x0 -#define MX51_PAD_EIM_D29__AUD6_RXD 0x090 0x424 0x8ec 0x5 0x0 -#define MX51_PAD_EIM_D29__EIM_D29 0x090 0x424 0x000 0x0 0x0 -#define MX51_PAD_EIM_D29__KEY_ROW5 0x090 0x424 0x9d4 0x1 0x0 -#define MX51_PAD_EIM_D29__USBOTG_DATA5 0x090 0x424 0x000 0x2 0x0 -#define MX51_PAD_EIM_D30__AUD6_TXC 0x094 0x428 0x8fc 0x5 0x0 -#define MX51_PAD_EIM_D30__EIM_D30 0x094 0x428 0x000 0x0 0x0 -#define MX51_PAD_EIM_D30__KEY_ROW6 0x094 0x428 0x9d8 0x1 0x0 -#define MX51_PAD_EIM_D30__USBOTG_DATA6 0x094 0x428 0x000 0x2 0x0 -#define MX51_PAD_EIM_D31__AUD6_TXFS 0x098 0x42c 0x900 0x5 0x0 -#define MX51_PAD_EIM_D31__EIM_D31 0x098 0x42c 0x000 0x0 0x0 -#define MX51_PAD_EIM_D31__KEY_ROW7 0x098 0x42c 0x9dc 0x1 0x0 -#define MX51_PAD_EIM_D31__USBOTG_DATA7 0x098 0x42c 0x000 0x2 0x0 -#define MX51_PAD_EIM_A16__EIM_A16 0x09c 0x430 0x000 0x0 0x0 -#define MX51_PAD_EIM_A16__GPIO2_10 0x09c 0x430 0x000 0x1 0x0 -#define MX51_PAD_EIM_A16__OSC_FREQ_SEL0 0x09c 0x430 0x000 0x7 0x0 -#define MX51_PAD_EIM_A17__EIM_A17 0x0a0 0x434 0x000 0x0 0x0 -#define MX51_PAD_EIM_A17__GPIO2_11 0x0a0 0x434 0x000 0x1 0x0 -#define MX51_PAD_EIM_A17__OSC_FREQ_SEL1 0x0a0 0x434 0x000 0x7 0x0 -#define MX51_PAD_EIM_A18__BOOT_LPB0 0x0a4 0x438 0x000 0x7 0x0 -#define MX51_PAD_EIM_A18__EIM_A18 0x0a4 0x438 0x000 0x0 0x0 -#define MX51_PAD_EIM_A18__GPIO2_12 0x0a4 0x438 0x000 0x1 0x0 -#define MX51_PAD_EIM_A19__BOOT_LPB1 0x0a8 0x43c 0x000 0x7 0x0 -#define MX51_PAD_EIM_A19__EIM_A19 0x0a8 0x43c 0x000 0x0 0x0 -#define MX51_PAD_EIM_A19__GPIO2_13 0x0a8 0x43c 0x000 0x1 0x0 -#define MX51_PAD_EIM_A20__BOOT_UART_SRC0 0x0ac 0x440 0x000 0x7 0x0 -#define MX51_PAD_EIM_A20__EIM_A20 0x0ac 0x440 0x000 0x0 0x0 -#define MX51_PAD_EIM_A20__GPIO2_14 0x0ac 0x440 0x000 0x1 0x0 -#define MX51_PAD_EIM_A21__BOOT_UART_SRC1 0x0b0 0x444 0x000 0x7 0x0 -#define MX51_PAD_EIM_A21__EIM_A21 0x0b0 0x444 0x000 0x0 0x0 -#define MX51_PAD_EIM_A21__GPIO2_15 0x0b0 0x444 0x000 0x1 0x0 -#define MX51_PAD_EIM_A22__EIM_A22 0x0b4 0x448 0x000 0x0 0x0 -#define MX51_PAD_EIM_A22__GPIO2_16 0x0b4 0x448 0x000 0x1 0x0 -#define MX51_PAD_EIM_A23__BOOT_HPN_EN 0x0b8 0x44c 0x000 0x7 0x0 -#define MX51_PAD_EIM_A23__EIM_A23 0x0b8 0x44c 0x000 0x0 0x0 -#define MX51_PAD_EIM_A23__GPIO2_17 0x0b8 0x44c 0x000 0x1 0x0 -#define MX51_PAD_EIM_A24__EIM_A24 0x0bc 0x450 0x000 0x0 0x0 -#define MX51_PAD_EIM_A24__GPIO2_18 0x0bc 0x450 0x000 0x1 0x0 -#define MX51_PAD_EIM_A24__USBH2_CLK 0x0bc 0x450 0x000 0x2 0x0 -#define MX51_PAD_EIM_A25__DISP1_PIN4 0x0c0 0x454 0x000 0x6 0x0 -#define MX51_PAD_EIM_A25__EIM_A25 0x0c0 0x454 0x000 0x0 0x0 -#define MX51_PAD_EIM_A25__GPIO2_19 0x0c0 0x454 0x000 0x1 0x0 -#define MX51_PAD_EIM_A25__USBH2_DIR 0x0c0 0x454 0x000 0x2 0x0 -#define MX51_PAD_EIM_A26__CSI1_DATA_EN 0x0c4 0x458 0x9a0 0x5 0x0 -#define MX51_PAD_EIM_A26__DISP2_EXT_CLK 0x0c4 0x458 0x908 0x6 0x0 -#define MX51_PAD_EIM_A26__EIM_A26 0x0c4 0x458 0x000 0x0 0x0 -#define MX51_PAD_EIM_A26__GPIO2_20 0x0c4 0x458 0x000 0x1 0x0 -#define MX51_PAD_EIM_A26__USBH2_STP 0x0c4 0x458 0x000 0x2 0x0 -#define MX51_PAD_EIM_A27__CSI2_DATA_EN 0x0c8 0x45c 0x99c 0x5 0x0 -#define MX51_PAD_EIM_A27__DISP1_PIN1 0x0c8 0x45c 0x9a4 0x6 0x0 -#define MX51_PAD_EIM_A27__EIM_A27 0x0c8 0x45c 0x000 0x0 0x0 -#define MX51_PAD_EIM_A27__GPIO2_21 0x0c8 0x45c 0x000 0x1 0x0 -#define MX51_PAD_EIM_A27__USBH2_NXT 0x0c8 0x45c 0x000 0x2 0x0 -#define MX51_PAD_EIM_EB0__EIM_EB0 0x0cc 0x460 0x000 0x0 0x0 -#define MX51_PAD_EIM_EB1__EIM_EB1 0x0d0 0x464 0x000 0x0 0x0 -#define MX51_PAD_EIM_EB2__AUD5_RXFS 0x0d4 0x468 0x8e0 0x6 0x0 -#define MX51_PAD_EIM_EB2__CSI1_D2 0x0d4 0x468 0x000 0x5 0x0 -#define MX51_PAD_EIM_EB2__EIM_EB2 0x0d4 0x468 0x000 0x0 0x0 -#define MX51_PAD_EIM_EB2__FEC_MDIO 0x0d4 0x468 0x954 0x3 0x0 -#define MX51_PAD_EIM_EB2__GPIO2_22 0x0d4 0x468 0x000 0x1 0x0 -#define MX51_PAD_EIM_EB2__GPT_CMPOUT1 0x0d4 0x468 0x000 0x7 0x0 -#define MX51_PAD_EIM_EB3__AUD5_RXC 0x0d8 0x46c 0x8dc 0x6 0x0 -#define MX51_PAD_EIM_EB3__CSI1_D3 0x0d8 0x46c 0x000 0x5 0x0 -#define MX51_PAD_EIM_EB3__EIM_EB3 0x0d8 0x46c 0x000 0x0 0x0 -#define MX51_PAD_EIM_EB3__FEC_RDATA1 0x0d8 0x46c 0x95c 0x3 0x0 -#define MX51_PAD_EIM_EB3__GPIO2_23 0x0d8 0x46c 0x000 0x1 0x0 -#define MX51_PAD_EIM_EB3__GPT_CMPOUT2 0x0d8 0x46c 0x000 0x7 0x0 -#define MX51_PAD_EIM_OE__EIM_OE 0x0dc 0x470 0x000 0x0 0x0 -#define MX51_PAD_EIM_OE__GPIO2_24 0x0dc 0x470 0x000 0x1 0x0 -#define MX51_PAD_EIM_CS0__EIM_CS0 0x0e0 0x474 0x000 0x0 0x0 -#define MX51_PAD_EIM_CS0__GPIO2_25 0x0e0 0x474 0x000 0x1 0x0 -#define MX51_PAD_EIM_CS1__EIM_CS1 0x0e4 0x478 0x000 0x0 0x0 -#define MX51_PAD_EIM_CS1__GPIO2_26 0x0e4 0x478 0x000 0x1 0x0 -#define MX51_PAD_EIM_CS2__AUD5_TXD 0x0e8 0x47c 0x8d8 0x6 0x1 -#define MX51_PAD_EIM_CS2__CSI1_D4 0x0e8 0x47c 0x000 0x5 0x0 -#define MX51_PAD_EIM_CS2__EIM_CS2 0x0e8 0x47c 0x000 0x0 0x0 -#define MX51_PAD_EIM_CS2__FEC_RDATA2 0x0e8 0x47c 0x960 0x3 0x0 -#define MX51_PAD_EIM_CS2__GPIO2_27 0x0e8 0x47c 0x000 0x1 0x0 -#define MX51_PAD_EIM_CS2__USBOTG_STP 0x0e8 0x47c 0x000 0x2 0x0 -#define MX51_PAD_EIM_CS3__AUD5_RXD 0x0ec 0x480 0x8d4 0x6 0x1 -#define MX51_PAD_EIM_CS3__CSI1_D5 0x0ec 0x480 0x000 0x5 0x0 -#define MX51_PAD_EIM_CS3__EIM_CS3 0x0ec 0x480 0x000 0x0 0x0 -#define MX51_PAD_EIM_CS3__FEC_RDATA3 0x0ec 0x480 0x964 0x3 0x0 -#define MX51_PAD_EIM_CS3__GPIO2_28 0x0ec 0x480 0x000 0x1 0x0 -#define MX51_PAD_EIM_CS3__USBOTG_NXT 0x0ec 0x480 0x000 0x2 0x0 -#define MX51_PAD_EIM_CS4__AUD5_TXC 0x0f0 0x484 0x8e4 0x6 0x1 -#define MX51_PAD_EIM_CS4__CSI1_D6 0x0f0 0x484 0x000 0x5 0x0 -#define MX51_PAD_EIM_CS4__EIM_CS4 0x0f0 0x484 0x000 0x0 0x0 -#define MX51_PAD_EIM_CS4__FEC_RX_ER 0x0f0 0x484 0x970 0x3 0x0 -#define MX51_PAD_EIM_CS4__GPIO2_29 0x0f0 0x484 0x000 0x1 0x0 -#define MX51_PAD_EIM_CS4__USBOTG_CLK 0x0f0 0x484 0x000 0x2 0x0 -#define MX51_PAD_EIM_CS5__AUD5_TXFS 0x0f4 0x488 0x8e8 0x6 0x1 -#define MX51_PAD_EIM_CS5__CSI1_D7 0x0f4 0x488 0x000 0x5 0x0 -#define MX51_PAD_EIM_CS5__DISP1_EXT_CLK 0x0f4 0x488 0x904 0x4 0x0 -#define MX51_PAD_EIM_CS5__EIM_CS5 0x0f4 0x488 0x000 0x0 0x0 -#define MX51_PAD_EIM_CS5__FEC_CRS 0x0f4 0x488 0x950 0x3 0x0 -#define MX51_PAD_EIM_CS5__GPIO2_30 0x0f4 0x488 0x000 0x1 0x0 -#define MX51_PAD_EIM_CS5__USBOTG_DIR 0x0f4 0x488 0x000 0x2 0x0 -#define MX51_PAD_EIM_DTACK__EIM_DTACK 0x0f8 0x48c 0x000 0x0 0x0 -#define MX51_PAD_EIM_DTACK__GPIO2_31 0x0f8 0x48c 0x000 0x1 0x0 -#define MX51_PAD_EIM_LBA__EIM_LBA 0x0fc 0x494 0x000 0x0 0x0 -#define MX51_PAD_EIM_LBA__GPIO3_1 0x0fc 0x494 0x978 0x1 0x0 -#define MX51_PAD_EIM_CRE__EIM_CRE 0x100 0x4a0 0x000 0x0 0x0 -#define MX51_PAD_EIM_CRE__GPIO3_2 0x100 0x4a0 0x97c 0x1 0x0 -#define MX51_PAD_DRAM_CS1__DRAM_CS1 0x104 0x4d0 0x000 0x0 0x0 -#define MX51_PAD_NANDF_WE_B__GPIO3_3 0x108 0x4e4 0x980 0x3 0x0 -#define MX51_PAD_NANDF_WE_B__NANDF_WE_B 0x108 0x4e4 0x000 0x0 0x0 -#define MX51_PAD_NANDF_WE_B__PATA_DIOW 0x108 0x4e4 0x000 0x1 0x0 -#define MX51_PAD_NANDF_WE_B__SD3_DATA0 0x108 0x4e4 0x93c 0x2 0x0 -#define MX51_PAD_NANDF_RE_B__GPIO3_4 0x10c 0x4e8 0x984 0x3 0x0 -#define MX51_PAD_NANDF_RE_B__NANDF_RE_B 0x10c 0x4e8 0x000 0x0 0x0 -#define MX51_PAD_NANDF_RE_B__PATA_DIOR 0x10c 0x4e8 0x000 0x1 0x0 -#define MX51_PAD_NANDF_RE_B__SD3_DATA1 0x10c 0x4e8 0x940 0x2 0x0 -#define MX51_PAD_NANDF_ALE__GPIO3_5 0x110 0x4ec 0x988 0x3 0x0 -#define MX51_PAD_NANDF_ALE__NANDF_ALE 0x110 0x4ec 0x000 0x0 0x0 -#define MX51_PAD_NANDF_ALE__PATA_BUFFER_EN 0x110 0x4ec 0x000 0x1 0x0 -#define MX51_PAD_NANDF_CLE__GPIO3_6 0x114 0x4f0 0x98c 0x3 0x0 -#define MX51_PAD_NANDF_CLE__NANDF_CLE 0x114 0x4f0 0x000 0x0 0x0 -#define MX51_PAD_NANDF_CLE__PATA_RESET_B 0x114 0x4f0 0x000 0x1 0x0 -#define MX51_PAD_NANDF_WP_B__GPIO3_7 0x118 0x4f4 0x990 0x3 0x0 -#define MX51_PAD_NANDF_WP_B__NANDF_WP_B 0x118 0x4f4 0x000 0x0 0x0 -#define MX51_PAD_NANDF_WP_B__PATA_DMACK 0x118 0x4f4 0x000 0x1 0x0 -#define MX51_PAD_NANDF_WP_B__SD3_DATA2 0x118 0x4f4 0x944 0x2 0x0 -#define MX51_PAD_NANDF_RB0__ECSPI2_SS1 0x11c 0x4f8 0x930 0x5 0x0 -#define MX51_PAD_NANDF_RB0__GPIO3_8 0x11c 0x4f8 0x994 0x3 0x0 -#define MX51_PAD_NANDF_RB0__NANDF_RB0 0x11c 0x4f8 0x000 0x0 0x0 -#define MX51_PAD_NANDF_RB0__PATA_DMARQ 0x11c 0x4f8 0x000 0x1 0x0 -#define MX51_PAD_NANDF_RB0__SD3_DATA3 0x11c 0x4f8 0x948 0x2 0x0 -#define MX51_PAD_NANDF_RB1__CSPI_MOSI 0x120 0x4fc 0x91c 0x6 0x0 -#define MX51_PAD_NANDF_RB1__ECSPI2_RDY 0x120 0x4fc 0x000 0x2 0x0 -#define MX51_PAD_NANDF_RB1__GPIO3_9 0x120 0x4fc 0x000 0x3 0x0 -#define MX51_PAD_NANDF_RB1__NANDF_RB1 0x120 0x4fc 0x000 0x0 0x0 -#define MX51_PAD_NANDF_RB1__PATA_IORDY 0x120 0x4fc 0x000 0x1 0x0 -#define MX51_PAD_NANDF_RB1__SD4_CMD 0x120 0x4fc 0x000 0x5 0x0 -#define MX51_PAD_NANDF_RB2__DISP2_WAIT 0x124 0x500 0x9a8 0x5 0x0 -#define MX51_PAD_NANDF_RB2__ECSPI2_SCLK 0x124 0x500 0x000 0x2 0x0 -#define MX51_PAD_NANDF_RB2__FEC_COL 0x124 0x500 0x94c 0x1 0x0 -#define MX51_PAD_NANDF_RB2__GPIO3_10 0x124 0x500 0x000 0x3 0x0 -#define MX51_PAD_NANDF_RB2__NANDF_RB2 0x124 0x500 0x000 0x0 0x0 -#define MX51_PAD_NANDF_RB2__USBH3_H3_DP 0x124 0x500 0x000 0x7 0x0 -#define MX51_PAD_NANDF_RB2__USBH3_NXT 0x124 0x500 0xa20 0x6 0x0 -#define MX51_PAD_NANDF_RB3__DISP1_WAIT 0x128 0x504 0x000 0x5 0x0 -#define MX51_PAD_NANDF_RB3__ECSPI2_MISO 0x128 0x504 0x000 0x2 0x0 -#define MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x128 0x504 0x968 0x1 0x0 -#define MX51_PAD_NANDF_RB3__GPIO3_11 0x128 0x504 0x000 0x3 0x0 -#define MX51_PAD_NANDF_RB3__NANDF_RB3 0x128 0x504 0x000 0x0 0x0 -#define MX51_PAD_NANDF_RB3__USBH3_CLK 0x128 0x504 0x9f8 0x6 0x0 -#define MX51_PAD_NANDF_RB3__USBH3_H3_DM 0x128 0x504 0x000 0x7 0x0 -#define MX51_PAD_GPIO_NAND__GPIO_NAND 0x12c 0x514 0x998 0x0 0x0 -#define MX51_PAD_GPIO_NAND__PATA_INTRQ 0x12c 0x514 0x000 0x1 0x0 -#define MX51_PAD_NANDF_CS0__GPIO3_16 0x130 0x518 0x000 0x3 0x0 -#define MX51_PAD_NANDF_CS0__NANDF_CS0 0x130 0x518 0x000 0x0 0x0 -#define MX51_PAD_NANDF_CS1__GPIO3_17 0x134 0x51c 0x000 0x3 0x0 -#define MX51_PAD_NANDF_CS1__NANDF_CS1 0x134 0x51c 0x000 0x0 0x0 -#define MX51_PAD_NANDF_CS2__CSPI_SCLK 0x138 0x520 0x914 0x6 0x0 -#define MX51_PAD_NANDF_CS2__FEC_TX_ER 0x138 0x520 0x000 0x2 0x0 -#define MX51_PAD_NANDF_CS2__GPIO3_18 0x138 0x520 0x000 0x3 0x0 -#define MX51_PAD_NANDF_CS2__NANDF_CS2 0x138 0x520 0x000 0x0 0x0 -#define MX51_PAD_NANDF_CS2__PATA_CS_0 0x138 0x520 0x000 0x1 0x0 -#define MX51_PAD_NANDF_CS2__SD4_CLK 0x138 0x520 0x000 0x5 0x0 -#define MX51_PAD_NANDF_CS2__USBH3_H1_DP 0x138 0x520 0x000 0x7 0x0 -#define MX51_PAD_NANDF_CS3__FEC_MDC 0x13c 0x524 0x000 0x2 0x0 -#define MX51_PAD_NANDF_CS3__GPIO3_19 0x13c 0x524 0x000 0x3 0x0 -#define MX51_PAD_NANDF_CS3__NANDF_CS3 0x13c 0x524 0x000 0x0 0x0 -#define MX51_PAD_NANDF_CS3__PATA_CS_1 0x13c 0x524 0x000 0x1 0x0 -#define MX51_PAD_NANDF_CS3__SD4_DAT0 0x13c 0x524 0x000 0x5 0x0 -#define MX51_PAD_NANDF_CS3__USBH3_H1_DM 0x13c 0x524 0x000 0x7 0x0 -#define MX51_PAD_NANDF_CS4__FEC_TDATA1 0x140 0x528 0x000 0x2 0x0 -#define MX51_PAD_NANDF_CS4__GPIO3_20 0x140 0x528 0x000 0x3 0x0 -#define MX51_PAD_NANDF_CS4__NANDF_CS4 0x140 0x528 0x000 0x0 0x0 -#define MX51_PAD_NANDF_CS4__PATA_DA_0 0x140 0x528 0x000 0x1 0x0 -#define MX51_PAD_NANDF_CS4__SD4_DAT1 0x140 0x528 0x000 0x5 0x0 -#define MX51_PAD_NANDF_CS4__USBH3_STP 0x140 0x528 0xa24 0x7 0x0 -#define MX51_PAD_NANDF_CS5__FEC_TDATA2 0x144 0x52c 0x000 0x2 0x0 -#define MX51_PAD_NANDF_CS5__GPIO3_21 0x144 0x52c 0x000 0x3 0x0 -#define MX51_PAD_NANDF_CS5__NANDF_CS5 0x144 0x52c 0x000 0x0 0x0 -#define MX51_PAD_NANDF_CS5__PATA_DA_1 0x144 0x52c 0x000 0x1 0x0 -#define MX51_PAD_NANDF_CS5__SD4_DAT2 0x144 0x52c 0x000 0x5 0x0 -#define MX51_PAD_NANDF_CS5__USBH3_DIR 0x144 0x52c 0xa1c 0x7 0x0 -#define MX51_PAD_NANDF_CS6__CSPI_SS3 0x148 0x530 0x928 0x7 0x0 -#define MX51_PAD_NANDF_CS6__FEC_TDATA3 0x148 0x530 0x000 0x2 0x0 -#define MX51_PAD_NANDF_CS6__GPIO3_22 0x148 0x530 0x000 0x3 0x0 -#define MX51_PAD_NANDF_CS6__NANDF_CS6 0x148 0x530 0x000 0x0 0x0 -#define MX51_PAD_NANDF_CS6__PATA_DA_2 0x148 0x530 0x000 0x1 0x0 -#define MX51_PAD_NANDF_CS6__SD4_DAT3 0x148 0x530 0x000 0x5 0x0 -#define MX51_PAD_NANDF_CS7__FEC_TX_EN 0x14c 0x534 0x000 0x1 0x0 -#define MX51_PAD_NANDF_CS7__GPIO3_23 0x14c 0x534 0x000 0x3 0x0 -#define MX51_PAD_NANDF_CS7__NANDF_CS7 0x14c 0x534 0x000 0x0 0x0 -#define MX51_PAD_NANDF_CS7__SD3_CLK 0x14c 0x534 0x000 0x5 0x0 -#define MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0 0x150 0x538 0x000 0x2 0x0 -#define MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x150 0x538 0x974 0x1 0x0 -#define MX51_PAD_NANDF_RDY_INT__GPIO3_24 0x150 0x538 0x000 0x3 0x0 -#define MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT 0x150 0x538 0x938 0x0 0x0 -#define MX51_PAD_NANDF_RDY_INT__SD3_CMD 0x150 0x538 0x000 0x5 0x0 -#define MX51_PAD_NANDF_D15__ECSPI2_MOSI 0x154 0x53c 0x000 0x2 0x0 -#define MX51_PAD_NANDF_D15__GPIO3_25 0x154 0x53c 0x000 0x3 0x0 -#define MX51_PAD_NANDF_D15__NANDF_D15 0x154 0x53c 0x000 0x0 0x0 -#define MX51_PAD_NANDF_D15__PATA_DATA15 0x154 0x53c 0x000 0x1 0x0 -#define MX51_PAD_NANDF_D15__SD3_DAT7 0x154 0x53c 0x000 0x5 0x0 -#define MX51_PAD_NANDF_D14__ECSPI2_SS3 0x158 0x540 0x934 0x2 0x0 -#define MX51_PAD_NANDF_D14__GPIO3_26 0x158 0x540 0x000 0x3 0x0 -#define MX51_PAD_NANDF_D14__NANDF_D14 0x158 0x540 0x000 0x0 0x0 -#define MX51_PAD_NANDF_D14__PATA_DATA14 0x158 0x540 0x000 0x1 0x0 -#define MX51_PAD_NANDF_D14__SD3_DAT6 0x158 0x540 0x000 0x5 0x0 -#define MX51_PAD_NANDF_D13__ECSPI2_SS2 0x15c 0x544 0x000 0x2 0x0 -#define MX51_PAD_NANDF_D13__GPIO3_27 0x15c 0x544 0x000 0x3 0x0 -#define MX51_PAD_NANDF_D13__NANDF_D13 0x15c 0x544 0x000 0x0 0x0 -#define MX51_PAD_NANDF_D13__PATA_DATA13 0x15c 0x544 0x000 0x1 0x0 -#define MX51_PAD_NANDF_D13__SD3_DAT5 0x15c 0x544 0x000 0x5 0x0 -#define MX51_PAD_NANDF_D12__ECSPI2_SS1 0x160 0x548 0x930 0x2 0x1 -#define MX51_PAD_NANDF_D12__GPIO3_28 0x160 0x548 0x000 0x3 0x0 -#define MX51_PAD_NANDF_D12__NANDF_D12 0x160 0x548 0x000 0x0 0x0 -#define MX51_PAD_NANDF_D12__PATA_DATA12 0x160 0x548 0x000 0x1 0x0 -#define MX51_PAD_NANDF_D12__SD3_DAT4 0x160 0x548 0x000 0x5 0x0 -#define MX51_PAD_NANDF_D11__FEC_RX_DV 0x164 0x54c 0x96c 0x2 0x0 -#define MX51_PAD_NANDF_D11__GPIO3_29 0x164 0x54c 0x000 0x3 0x0 -#define MX51_PAD_NANDF_D11__NANDF_D11 0x164 0x54c 0x000 0x0 0x0 -#define MX51_PAD_NANDF_D11__PATA_DATA11 0x164 0x54c 0x000 0x1 0x0 -#define MX51_PAD_NANDF_D11__SD3_DATA3 0x164 0x54c 0x948 0x5 0x1 -#define MX51_PAD_NANDF_D10__GPIO3_30 0x168 0x550 0x000 0x3 0x0 -#define MX51_PAD_NANDF_D10__NANDF_D10 0x168 0x550 0x000 0x0 0x0 -#define MX51_PAD_NANDF_D10__PATA_DATA10 0x168 0x550 0x000 0x1 0x0 -#define MX51_PAD_NANDF_D10__SD3_DATA2 0x168 0x550 0x944 0x5 0x1 -#define MX51_PAD_NANDF_D9__FEC_RDATA0 0x16c 0x554 0x958 0x2 0x0 -#define MX51_PAD_NANDF_D9__GPIO3_31 0x16c 0x554 0x000 0x3 0x0 -#define MX51_PAD_NANDF_D9__NANDF_D9 0x16c 0x554 0x000 0x0 0x0 -#define MX51_PAD_NANDF_D9__PATA_DATA9 0x16c 0x554 0x000 0x1 0x0 -#define MX51_PAD_NANDF_D9__SD3_DATA1 0x16c 0x554 0x940 0x5 0x1 -#define MX51_PAD_NANDF_D8__FEC_TDATA0 0x170 0x558 0x000 0x2 0x0 -#define MX51_PAD_NANDF_D8__GPIO4_0 0x170 0x558 0x000 0x3 0x0 -#define MX51_PAD_NANDF_D8__NANDF_D8 0x170 0x558 0x000 0x0 0x0 -#define MX51_PAD_NANDF_D8__PATA_DATA8 0x170 0x558 0x000 0x1 0x0 -#define MX51_PAD_NANDF_D8__SD3_DATA0 0x170 0x558 0x93c 0x5 0x1 -#define MX51_PAD_NANDF_D7__GPIO4_1 0x174 0x55c 0x000 0x3 0x0 -#define MX51_PAD_NANDF_D7__NANDF_D7 0x174 0x55c 0x000 0x0 0x0 -#define MX51_PAD_NANDF_D7__PATA_DATA7 0x174 0x55c 0x000 0x1 0x0 -#define MX51_PAD_NANDF_D7__USBH3_DATA0 0x174 0x55c 0x9fc 0x5 0x0 -#define MX51_PAD_NANDF_D6__GPIO4_2 0x178 0x560 0x000 0x3 0x0 -#define MX51_PAD_NANDF_D6__NANDF_D6 0x178 0x560 0x000 0x0 0x0 -#define MX51_PAD_NANDF_D6__PATA_DATA6 0x178 0x560 0x000 0x1 0x0 -#define MX51_PAD_NANDF_D6__SD4_LCTL 0x178 0x560 0x000 0x2 0x0 -#define MX51_PAD_NANDF_D6__USBH3_DATA1 0x178 0x560 0xa00 0x5 0x0 -#define MX51_PAD_NANDF_D5__GPIO4_3 0x17c 0x564 0x000 0x3 0x0 -#define MX51_PAD_NANDF_D5__NANDF_D5 0x17c 0x564 0x000 0x0 0x0 -#define MX51_PAD_NANDF_D5__PATA_DATA5 0x17c 0x564 0x000 0x1 0x0 -#define MX51_PAD_NANDF_D5__SD4_WP 0x17c 0x564 0x000 0x2 0x0 -#define MX51_PAD_NANDF_D5__USBH3_DATA2 0x17c 0x564 0xa04 0x5 0x0 -#define MX51_PAD_NANDF_D4__GPIO4_4 0x180 0x568 0x000 0x3 0x0 -#define MX51_PAD_NANDF_D4__NANDF_D4 0x180 0x568 0x000 0x0 0x0 -#define MX51_PAD_NANDF_D4__PATA_DATA4 0x180 0x568 0x000 0x1 0x0 -#define MX51_PAD_NANDF_D4__SD4_CD 0x180 0x568 0x000 0x2 0x0 -#define MX51_PAD_NANDF_D4__USBH3_DATA3 0x180 0x568 0xa08 0x5 0x0 -#define MX51_PAD_NANDF_D3__GPIO4_5 0x184 0x56c 0x000 0x3 0x0 -#define MX51_PAD_NANDF_D3__NANDF_D3 0x184 0x56c 0x000 0x0 0x0 -#define MX51_PAD_NANDF_D3__PATA_DATA3 0x184 0x56c 0x000 0x1 0x0 -#define MX51_PAD_NANDF_D3__SD4_DAT4 0x184 0x56c 0x000 0x2 0x0 -#define MX51_PAD_NANDF_D3__USBH3_DATA4 0x184 0x56c 0xa0c 0x5 0x0 -#define MX51_PAD_NANDF_D2__GPIO4_6 0x188 0x570 0x000 0x3 0x0 -#define MX51_PAD_NANDF_D2__NANDF_D2 0x188 0x570 0x000 0x0 0x0 -#define MX51_PAD_NANDF_D2__PATA_DATA2 0x188 0x570 0x000 0x1 0x0 -#define MX51_PAD_NANDF_D2__SD4_DAT5 0x188 0x570 0x000 0x2 0x0 -#define MX51_PAD_NANDF_D2__USBH3_DATA5 0x188 0x570 0xa10 0x5 0x0 -#define MX51_PAD_NANDF_D1__GPIO4_7 0x18c 0x574 0x000 0x3 0x0 -#define MX51_PAD_NANDF_D1__NANDF_D1 0x18c 0x574 0x000 0x0 0x0 -#define MX51_PAD_NANDF_D1__PATA_DATA1 0x18c 0x574 0x000 0x1 0x0 -#define MX51_PAD_NANDF_D1__SD4_DAT6 0x18c 0x574 0x000 0x2 0x0 -#define MX51_PAD_NANDF_D1__USBH3_DATA6 0x18c 0x574 0xa14 0x5 0x0 -#define MX51_PAD_NANDF_D0__GPIO4_8 0x190 0x578 0x000 0x3 0x0 -#define MX51_PAD_NANDF_D0__NANDF_D0 0x190 0x578 0x000 0x0 0x0 -#define MX51_PAD_NANDF_D0__PATA_DATA0 0x190 0x578 0x000 0x1 0x0 -#define MX51_PAD_NANDF_D0__SD4_DAT7 0x190 0x578 0x000 0x2 0x0 -#define MX51_PAD_NANDF_D0__USBH3_DATA7 0x190 0x578 0xa18 0x5 0x0 -#define MX51_PAD_CSI1_D8__CSI1_D8 0x194 0x57c 0x000 0x0 0x0 -#define MX51_PAD_CSI1_D8__GPIO3_12 0x194 0x57c 0x998 0x3 0x1 -#define MX51_PAD_CSI1_D9__CSI1_D9 0x198 0x580 0x000 0x0 0x0 -#define MX51_PAD_CSI1_D9__GPIO3_13 0x198 0x580 0x000 0x3 0x0 -#define MX51_PAD_CSI1_D10__CSI1_D10 0x19c 0x584 0x000 0x0 0x0 -#define MX51_PAD_CSI1_D11__CSI1_D11 0x1a0 0x588 0x000 0x0 0x0 -#define MX51_PAD_CSI1_D12__CSI1_D12 0x1a4 0x58c 0x000 0x0 0x0 -#define MX51_PAD_CSI1_D13__CSI1_D13 0x1a8 0x590 0x000 0x0 0x0 -#define MX51_PAD_CSI1_D14__CSI1_D14 0x1ac 0x594 0x000 0x0 0x0 -#define MX51_PAD_CSI1_D15__CSI1_D15 0x1b0 0x598 0x000 0x0 0x0 -#define MX51_PAD_CSI1_D16__CSI1_D16 0x1b4 0x59c 0x000 0x0 0x0 -#define MX51_PAD_CSI1_D17__CSI1_D17 0x1b8 0x5a0 0x000 0x0 0x0 -#define MX51_PAD_CSI1_D18__CSI1_D18 0x1bc 0x5a4 0x000 0x0 0x0 -#define MX51_PAD_CSI1_D19__CSI1_D19 0x1c0 0x5a8 0x000 0x0 0x0 -#define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC 0x1c4 0x5ac 0x000 0x0 0x0 -#define MX51_PAD_CSI1_VSYNC__GPIO3_14 0x1c4 0x5ac 0x000 0x3 0x0 -#define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC 0x1c8 0x5b0 0x000 0x0 0x0 -#define MX51_PAD_CSI1_HSYNC__GPIO3_15 0x1c8 0x5b0 0x000 0x3 0x0 -#define MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK 0x000 0x5b4 0x000 0x0 0x0 -#define MX51_PAD_CSI1_MCLK__CSI1_MCLK 0x000 0x5b8 0x000 0x0 0x0 -#define MX51_PAD_CSI2_D12__CSI2_D12 0x1cc 0x5bc 0x000 0x0 0x0 -#define MX51_PAD_CSI2_D12__GPIO4_9 0x1cc 0x5bc 0x000 0x3 0x0 -#define MX51_PAD_CSI2_D13__CSI2_D13 0x1d0 0x5c0 0x000 0x0 0x0 -#define MX51_PAD_CSI2_D13__GPIO4_10 0x1d0 0x5c0 0x000 0x3 0x0 -#define MX51_PAD_CSI2_D14__CSI2_D14 0x1d4 0x5c4 0x000 0x0 0x0 -#define MX51_PAD_CSI2_D15__CSI2_D15 0x1d8 0x5c8 0x000 0x0 0x0 -#define MX51_PAD_CSI2_D16__CSI2_D16 0x1dc 0x5cc 0x000 0x0 0x0 -#define MX51_PAD_CSI2_D17__CSI2_D17 0x1e0 0x5d0 0x000 0x0 0x0 -#define MX51_PAD_CSI2_D18__CSI2_D18 0x1e4 0x5d4 0x000 0x0 0x0 -#define MX51_PAD_CSI2_D18__GPIO4_11 0x1e4 0x5d4 0x000 0x3 0x0 -#define MX51_PAD_CSI2_D19__CSI2_D19 0x1e8 0x5d8 0x000 0x0 0x0 -#define MX51_PAD_CSI2_D19__GPIO4_12 0x1e8 0x5d8 0x000 0x3 0x0 -#define MX51_PAD_CSI2_VSYNC__CSI2_VSYNC 0x1ec 0x5dc 0x000 0x0 0x0 -#define MX51_PAD_CSI2_VSYNC__GPIO4_13 0x1ec 0x5dc 0x000 0x3 0x0 -#define MX51_PAD_CSI2_HSYNC__CSI2_HSYNC 0x1f0 0x5e0 0x000 0x0 0x0 -#define MX51_PAD_CSI2_HSYNC__GPIO4_14 0x1f0 0x5e0 0x000 0x3 0x0 -#define MX51_PAD_CSI2_PIXCLK__CSI2_PIXCLK 0x1f4 0x5e4 0x000 0x0 0x0 -#define MX51_PAD_CSI2_PIXCLK__GPIO4_15 0x1f4 0x5e4 0x000 0x3 0x0 -#define MX51_PAD_I2C1_CLK__GPIO4_16 0x1f8 0x5e8 0x000 0x3 0x0 -#define MX51_PAD_I2C1_CLK__I2C1_CLK 0x1f8 0x5e8 0x000 0x0 0x0 -#define MX51_PAD_I2C1_DAT__GPIO4_17 0x1fc 0x5ec 0x000 0x3 0x0 -#define MX51_PAD_I2C1_DAT__I2C1_DAT 0x1fc 0x5ec 0x000 0x0 0x0 -#define MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x200 0x5f0 0x000 0x0 0x0 -#define MX51_PAD_AUD3_BB_TXD__GPIO4_18 0x200 0x5f0 0x000 0x3 0x0 -#define MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x204 0x5f4 0x000 0x0 0x0 -#define MX51_PAD_AUD3_BB_RXD__GPIO4_19 0x204 0x5f4 0x000 0x3 0x0 -#define MX51_PAD_AUD3_BB_RXD__UART3_RXD 0x204 0x5f4 0x9f4 0x1 0x2 -#define MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x208 0x5f8 0x000 0x0 0x0 -#define MX51_PAD_AUD3_BB_CK__GPIO4_20 0x208 0x5f8 0x000 0x3 0x0 -#define MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x20c 0x5fc 0x000 0x0 0x0 -#define MX51_PAD_AUD3_BB_FS__GPIO4_21 0x20c 0x5fc 0x000 0x3 0x0 -#define MX51_PAD_AUD3_BB_FS__UART3_TXD 0x20c 0x5fc 0x000 0x1 0x0 -#define MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x210 0x600 0x000 0x0 0x0 -#define MX51_PAD_CSPI1_MOSI__GPIO4_22 0x210 0x600 0x000 0x3 0x0 -#define MX51_PAD_CSPI1_MOSI__I2C1_SDA 0x210 0x600 0x9b4 0x1 0x1 -#define MX51_PAD_CSPI1_MISO__AUD4_RXD 0x214 0x604 0x8c4 0x1 0x1 -#define MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x214 0x604 0x000 0x0 0x0 -#define MX51_PAD_CSPI1_MISO__GPIO4_23 0x214 0x604 0x000 0x3 0x0 -#define MX51_PAD_CSPI1_SS0__AUD4_TXC 0x218 0x608 0x8cc 0x1 0x1 -#define MX51_PAD_CSPI1_SS0__ECSPI1_SS0 0x218 0x608 0x000 0x0 0x0 -#define MX51_PAD_CSPI1_SS0__GPIO4_24 0x218 0x608 0x000 0x3 0x0 -#define MX51_PAD_CSPI1_SS1__AUD4_TXD 0x21c 0x60c 0x8c8 0x1 0x1 -#define MX51_PAD_CSPI1_SS1__ECSPI1_SS1 0x21c 0x60c 0x000 0x0 0x0 -#define MX51_PAD_CSPI1_SS1__GPIO4_25 0x21c 0x60c 0x000 0x3 0x0 -#define MX51_PAD_CSPI1_RDY__AUD4_TXFS 0x220 0x610 0x8d0 0x1 0x1 -#define MX51_PAD_CSPI1_RDY__ECSPI1_RDY 0x220 0x610 0x000 0x0 0x0 -#define MX51_PAD_CSPI1_RDY__GPIO4_26 0x220 0x610 0x000 0x3 0x0 -#define MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x224 0x614 0x000 0x0 0x0 -#define MX51_PAD_CSPI1_SCLK__GPIO4_27 0x224 0x614 0x000 0x3 0x0 -#define MX51_PAD_CSPI1_SCLK__I2C1_SCL 0x224 0x614 0x9b0 0x1 0x1 -#define MX51_PAD_UART1_RXD__GPIO4_28 0x228 0x618 0x000 0x3 0x0 -#define MX51_PAD_UART1_RXD__UART1_RXD 0x228 0x618 0x9e4 0x0 0x0 -#define MX51_PAD_UART1_TXD__GPIO4_29 0x22c 0x61c 0x000 0x3 0x0 -#define MX51_PAD_UART1_TXD__PWM2_PWMO 0x22c 0x61c 0x000 0x1 0x0 -#define MX51_PAD_UART1_TXD__UART1_TXD 0x22c 0x61c 0x000 0x0 0x0 -#define MX51_PAD_UART1_RTS__GPIO4_30 0x230 0x620 0x000 0x3 0x0 -#define MX51_PAD_UART1_RTS__UART1_RTS 0x230 0x620 0x9e0 0x0 0x0 -#define MX51_PAD_UART1_CTS__GPIO4_31 0x234 0x624 0x000 0x3 0x0 -#define MX51_PAD_UART1_CTS__UART1_CTS 0x234 0x624 0x000 0x0 0x0 -#define MX51_PAD_UART2_RXD__FIRI_TXD 0x238 0x628 0x000 0x1 0x0 -#define MX51_PAD_UART2_RXD__GPIO1_20 0x238 0x628 0x000 0x3 0x0 -#define MX51_PAD_UART2_RXD__UART2_RXD 0x238 0x628 0x9ec 0x0 0x2 -#define MX51_PAD_UART2_TXD__FIRI_RXD 0x23c 0x62c 0x000 0x1 0x0 -#define MX51_PAD_UART2_TXD__GPIO1_21 0x23c 0x62c 0x000 0x3 0x0 -#define MX51_PAD_UART2_TXD__UART2_TXD 0x23c 0x62c 0x000 0x0 0x0 -#define MX51_PAD_UART3_RXD__CSI1_D0 0x240 0x630 0x000 0x2 0x0 -#define MX51_PAD_UART3_RXD__GPIO1_22 0x240 0x630 0x000 0x3 0x0 -#define MX51_PAD_UART3_RXD__UART1_DTR 0x240 0x630 0x000 0x0 0x0 -#define MX51_PAD_UART3_RXD__UART3_RXD 0x240 0x630 0x9f4 0x1 0x4 -#define MX51_PAD_UART3_TXD__CSI1_D1 0x244 0x634 0x000 0x2 0x0 -#define MX51_PAD_UART3_TXD__GPIO1_23 0x244 0x634 0x000 0x3 0x0 -#define MX51_PAD_UART3_TXD__UART1_DSR 0x244 0x634 0x000 0x0 0x0 -#define MX51_PAD_UART3_TXD__UART3_TXD 0x244 0x634 0x000 0x1 0x0 -#define MX51_PAD_OWIRE_LINE__GPIO1_24 0x248 0x638 0x000 0x3 0x0 -#define MX51_PAD_OWIRE_LINE__OWIRE_LINE 0x248 0x638 0x000 0x0 0x0 -#define MX51_PAD_OWIRE_LINE__SPDIF_OUT 0x248 0x638 0x000 0x6 0x0 -#define MX51_PAD_KEY_ROW0__KEY_ROW0 0x24c 0x63c 0x000 0x0 0x0 -#define MX51_PAD_KEY_ROW1__KEY_ROW1 0x250 0x640 0x000 0x0 0x0 -#define MX51_PAD_KEY_ROW2__KEY_ROW2 0x254 0x644 0x000 0x0 0x0 -#define MX51_PAD_KEY_ROW3__KEY_ROW3 0x258 0x648 0x000 0x0 0x0 -#define MX51_PAD_KEY_COL0__KEY_COL0 0x25c 0x64c 0x000 0x0 0x0 -#define MX51_PAD_KEY_COL0__PLL1_BYP 0x25c 0x64c 0x90c 0x7 0x0 -#define MX51_PAD_KEY_COL1__KEY_COL1 0x260 0x650 0x000 0x0 0x0 -#define MX51_PAD_KEY_COL1__PLL2_BYP 0x260 0x650 0x910 0x7 0x0 -#define MX51_PAD_KEY_COL2__KEY_COL2 0x264 0x654 0x000 0x0 0x0 -#define MX51_PAD_KEY_COL2__PLL3_BYP 0x264 0x654 0x000 0x7 0x0 -#define MX51_PAD_KEY_COL3__KEY_COL3 0x268 0x658 0x000 0x0 0x0 -#define MX51_PAD_KEY_COL4__I2C2_SCL 0x26c 0x65c 0x9b8 0x3 0x1 -#define MX51_PAD_KEY_COL4__KEY_COL4 0x26c 0x65c 0x000 0x0 0x0 -#define MX51_PAD_KEY_COL4__SPDIF_OUT1 0x26c 0x65c 0x000 0x6 0x0 -#define MX51_PAD_KEY_COL4__UART1_RI 0x26c 0x65c 0x000 0x1 0x0 -#define MX51_PAD_KEY_COL4__UART3_RTS 0x26c 0x65c 0x9f0 0x2 0x4 -#define MX51_PAD_KEY_COL5__I2C2_SDA 0x270 0x660 0x9bc 0x3 0x1 -#define MX51_PAD_KEY_COL5__KEY_COL5 0x270 0x660 0x000 0x0 0x0 -#define MX51_PAD_KEY_COL5__UART1_DCD 0x270 0x660 0x000 0x1 0x0 -#define MX51_PAD_KEY_COL5__UART3_CTS 0x270 0x660 0x000 0x2 0x0 -#define MX51_PAD_USBH1_CLK__CSPI_SCLK 0x278 0x678 0x914 0x1 0x1 -#define MX51_PAD_USBH1_CLK__GPIO1_25 0x278 0x678 0x000 0x2 0x0 -#define MX51_PAD_USBH1_CLK__I2C2_SCL 0x278 0x678 0x9b8 0x5 0x2 -#define MX51_PAD_USBH1_CLK__USBH1_CLK 0x278 0x678 0x000 0x0 0x0 -#define MX51_PAD_USBH1_DIR__CSPI_MOSI 0x27c 0x67c 0x91c 0x1 0x1 -#define MX51_PAD_USBH1_DIR__GPIO1_26 0x27c 0x67c 0x000 0x2 0x0 -#define MX51_PAD_USBH1_DIR__I2C2_SDA 0x27c 0x67c 0x9bc 0x5 0x2 -#define MX51_PAD_USBH1_DIR__USBH1_DIR 0x27c 0x67c 0x000 0x0 0x0 -#define MX51_PAD_USBH1_STP__CSPI_RDY 0x280 0x680 0x000 0x1 0x0 -#define MX51_PAD_USBH1_STP__GPIO1_27 0x280 0x680 0x000 0x2 0x0 -#define MX51_PAD_USBH1_STP__UART3_RXD 0x280 0x680 0x9f4 0x5 0x6 -#define MX51_PAD_USBH1_STP__USBH1_STP 0x280 0x680 0x000 0x0 0x0 -#define MX51_PAD_USBH1_NXT__CSPI_MISO 0x284 0x684 0x918 0x1 0x0 -#define MX51_PAD_USBH1_NXT__GPIO1_28 0x284 0x684 0x000 0x2 0x0 -#define MX51_PAD_USBH1_NXT__UART3_TXD 0x284 0x684 0x000 0x5 0x0 -#define MX51_PAD_USBH1_NXT__USBH1_NXT 0x284 0x684 0x000 0x0 0x0 -#define MX51_PAD_USBH1_DATA0__GPIO1_11 0x288 0x688 0x000 0x2 0x0 -#define MX51_PAD_USBH1_DATA0__UART2_CTS 0x288 0x688 0x000 0x1 0x0 -#define MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x288 0x688 0x000 0x0 0x0 -#define MX51_PAD_USBH1_DATA1__GPIO1_12 0x28c 0x68c 0x000 0x2 0x0 -#define MX51_PAD_USBH1_DATA1__UART2_RXD 0x28c 0x68c 0x9ec 0x1 0x4 -#define MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x28c 0x68c 0x000 0x0 0x0 -#define MX51_PAD_USBH1_DATA2__GPIO1_13 0x290 0x690 0x000 0x2 0x0 -#define MX51_PAD_USBH1_DATA2__UART2_TXD 0x290 0x690 0x000 0x1 0x0 -#define MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x290 0x690 0x000 0x0 0x0 -#define MX51_PAD_USBH1_DATA3__GPIO1_14 0x294 0x694 0x000 0x2 0x0 -#define MX51_PAD_USBH1_DATA3__UART2_RTS 0x294 0x694 0x9e8 0x1 0x5 -#define MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x294 0x694 0x000 0x0 0x0 -#define MX51_PAD_USBH1_DATA4__CSPI_SS0 0x298 0x698 0x000 0x1 0x0 -#define MX51_PAD_USBH1_DATA4__GPIO1_15 0x298 0x698 0x000 0x2 0x0 -#define MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x298 0x698 0x000 0x0 0x0 -#define MX51_PAD_USBH1_DATA5__CSPI_SS1 0x29c 0x69c 0x920 0x1 0x0 -#define MX51_PAD_USBH1_DATA5__GPIO1_16 0x29c 0x69c 0x000 0x2 0x0 -#define MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x29c 0x69c 0x000 0x0 0x0 -#define MX51_PAD_USBH1_DATA6__CSPI_SS3 0x2a0 0x6a0 0x928 0x1 0x1 -#define MX51_PAD_USBH1_DATA6__GPIO1_17 0x2a0 0x6a0 0x000 0x2 0x0 -#define MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x2a0 0x6a0 0x000 0x0 0x0 -#define MX51_PAD_USBH1_DATA7__ECSPI1_SS3 0x2a4 0x6a4 0x000 0x1 0x0 -#define MX51_PAD_USBH1_DATA7__ECSPI2_SS3 0x2a4 0x6a4 0x934 0x5 0x1 -#define MX51_PAD_USBH1_DATA7__GPIO1_18 0x2a4 0x6a4 0x000 0x2 0x0 -#define MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x2a4 0x6a4 0x000 0x0 0x0 -#define MX51_PAD_DI1_PIN11__DI1_PIN11 0x2a8 0x6a8 0x000 0x0 0x0 -#define MX51_PAD_DI1_PIN11__ECSPI1_SS2 0x2a8 0x6a8 0x000 0x7 0x0 -#define MX51_PAD_DI1_PIN11__GPIO3_0 0x2a8 0x6a8 0x000 0x4 0x0 -#define MX51_PAD_DI1_PIN12__DI1_PIN12 0x2ac 0x6ac 0x000 0x0 0x0 -#define MX51_PAD_DI1_PIN12__GPIO3_1 0x2ac 0x6ac 0x978 0x4 0x1 -#define MX51_PAD_DI1_PIN13__DI1_PIN13 0x2b0 0x6b0 0x000 0x0 0x0 -#define MX51_PAD_DI1_PIN13__GPIO3_2 0x2b0 0x6b0 0x97c 0x4 0x1 -#define MX51_PAD_DI1_D0_CS__DI1_D0_CS 0x2b4 0x6b4 0x000 0x0 0x0 -#define MX51_PAD_DI1_D0_CS__GPIO3_3 0x2b4 0x6b4 0x980 0x4 0x1 -#define MX51_PAD_DI1_D1_CS__DI1_D1_CS 0x2b8 0x6b8 0x000 0x0 0x0 -#define MX51_PAD_DI1_D1_CS__DISP1_PIN14 0x2b8 0x6b8 0x000 0x2 0x0 -#define MX51_PAD_DI1_D1_CS__DISP1_PIN5 0x2b8 0x6b8 0x000 0x3 0x0 -#define MX51_PAD_DI1_D1_CS__GPIO3_4 0x2b8 0x6b8 0x984 0x4 0x1 -#define MX51_PAD_DISPB2_SER_DIN__DISP1_PIN1 0x2bc 0x6bc 0x9a4 0x2 0x1 -#define MX51_PAD_DISPB2_SER_DIN__DISPB2_SER_DIN 0x2bc 0x6bc 0x9c4 0x0 0x0 -#define MX51_PAD_DISPB2_SER_DIN__GPIO3_5 0x2bc 0x6bc 0x988 0x4 0x1 -#define MX51_PAD_DISPB2_SER_DIO__DISP1_PIN6 0x2c0 0x6c0 0x000 0x3 0x0 -#define MX51_PAD_DISPB2_SER_DIO__DISPB2_SER_DIO 0x2c0 0x6c0 0x9c4 0x0 0x1 -#define MX51_PAD_DISPB2_SER_DIO__GPIO3_6 0x2c0 0x6c0 0x98c 0x4 0x1 -#define MX51_PAD_DISPB2_SER_CLK__DISP1_PIN17 0x2c4 0x6c4 0x000 0x2 0x0 -#define MX51_PAD_DISPB2_SER_CLK__DISP1_PIN7 0x2c4 0x6c4 0x000 0x3 0x0 -#define MX51_PAD_DISPB2_SER_CLK__DISPB2_SER_CLK 0x2c4 0x6c4 0x000 0x0 0x0 -#define MX51_PAD_DISPB2_SER_CLK__GPIO3_7 0x2c4 0x6c4 0x990 0x4 0x1 -#define MX51_PAD_DISPB2_SER_RS__DISP1_PIN16 0x2c8 0x6c8 0x000 0x2 0x0 -#define MX51_PAD_DISPB2_SER_RS__DISP1_PIN8 0x2c8 0x6c8 0x000 0x3 0x0 -#define MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS 0x2c8 0x6c8 0x000 0x0 0x0 -#define MX51_PAD_DISPB2_SER_RS__GPIO3_8 0x2c8 0x6c8 0x994 0x4 0x1 -#define MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x2cc 0x6cc 0x000 0x0 0x0 -#define MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x2d0 0x6d0 0x000 0x0 0x0 -#define MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x2d4 0x6d4 0x000 0x0 0x0 -#define MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x2d8 0x6d8 0x000 0x0 0x0 -#define MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x2dc 0x6dc 0x000 0x0 0x0 -#define MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x2e0 0x6e0 0x000 0x0 0x0 -#define MX51_PAD_DISP1_DAT6__BOOT_USB_SRC 0x2e4 0x6e4 0x000 0x7 0x0 -#define MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x2e4 0x6e4 0x000 0x0 0x0 -#define MX51_PAD_DISP1_DAT7__BOOT_EEPROM_CFG 0x2e8 0x6e8 0x000 0x7 0x0 -#define MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x2e8 0x6e8 0x000 0x0 0x0 -#define MX51_PAD_DISP1_DAT8__BOOT_SRC0 0x2ec 0x6ec 0x000 0x7 0x0 -#define MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x2ec 0x6ec 0x000 0x0 0x0 -#define MX51_PAD_DISP1_DAT9__BOOT_SRC1 0x2f0 0x6f0 0x000 0x7 0x0 -#define MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x2f0 0x6f0 0x000 0x0 0x0 -#define MX51_PAD_DISP1_DAT10__BOOT_SPARE_SIZE 0x2f4 0x6f4 0x000 0x7 0x0 -#define MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x2f4 0x6f4 0x000 0x0 0x0 -#define MX51_PAD_DISP1_DAT11__BOOT_LPB_FREQ2 0x2f8 0x6f8 0x000 0x7 0x0 -#define MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x2f8 0x6f8 0x000 0x0 0x0 -#define MX51_PAD_DISP1_DAT12__BOOT_MLC_SEL 0x2fc 0x6fc 0x000 0x7 0x0 -#define MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x2fc 0x6fc 0x000 0x0 0x0 -#define MX51_PAD_DISP1_DAT13__BOOT_MEM_CTL0 0x300 0x700 0x000 0x7 0x0 -#define MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x300 0x700 0x000 0x0 0x0 -#define MX51_PAD_DISP1_DAT14__BOOT_MEM_CTL1 0x304 0x704 0x000 0x7 0x0 -#define MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x304 0x704 0x000 0x0 0x0 -#define MX51_PAD_DISP1_DAT15__BOOT_BUS_WIDTH 0x308 0x708 0x000 0x7 0x0 -#define MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x308 0x708 0x000 0x0 0x0 -#define MX51_PAD_DISP1_DAT16__BOOT_PAGE_SIZE0 0x30c 0x70c 0x000 0x7 0x0 -#define MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x30c 0x70c 0x000 0x0 0x0 -#define MX51_PAD_DISP1_DAT17__BOOT_PAGE_SIZE1 0x310 0x710 0x000 0x7 0x0 -#define MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x310 0x710 0x000 0x0 0x0 -#define MX51_PAD_DISP1_DAT18__BOOT_WEIM_MUXED0 0x314 0x714 0x000 0x7 0x0 -#define MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x314 0x714 0x000 0x0 0x0 -#define MX51_PAD_DISP1_DAT18__DISP2_PIN11 0x314 0x714 0x000 0x5 0x0 -#define MX51_PAD_DISP1_DAT18__DISP2_PIN5 0x314 0x714 0x000 0x4 0x0 -#define MX51_PAD_DISP1_DAT19__BOOT_WEIM_MUXED1 0x318 0x718 0x000 0x7 0x0 -#define MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x318 0x718 0x000 0x0 0x0 -#define MX51_PAD_DISP1_DAT19__DISP2_PIN12 0x318 0x718 0x000 0x5 0x0 -#define MX51_PAD_DISP1_DAT19__DISP2_PIN6 0x318 0x718 0x000 0x4 0x0 -#define MX51_PAD_DISP1_DAT20__BOOT_MEM_TYPE0 0x31c 0x71c 0x000 0x7 0x0 -#define MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x31c 0x71c 0x000 0x0 0x0 -#define MX51_PAD_DISP1_DAT20__DISP2_PIN13 0x31c 0x71c 0x000 0x5 0x0 -#define MX51_PAD_DISP1_DAT20__DISP2_PIN7 0x31c 0x71c 0x000 0x4 0x0 -#define MX51_PAD_DISP1_DAT21__BOOT_MEM_TYPE1 0x320 0x720 0x000 0x7 0x0 -#define MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x320 0x720 0x000 0x0 0x0 -#define MX51_PAD_DISP1_DAT21__DISP2_PIN14 0x320 0x720 0x000 0x5 0x0 -#define MX51_PAD_DISP1_DAT21__DISP2_PIN8 0x320 0x720 0x000 0x4 0x0 -#define MX51_PAD_DISP1_DAT22__BOOT_LPB_FREQ0 0x324 0x724 0x000 0x7 0x0 -#define MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x324 0x724 0x000 0x0 0x0 -#define MX51_PAD_DISP1_DAT22__DISP2_D0_CS 0x324 0x724 0x000 0x6 0x0 -#define MX51_PAD_DISP1_DAT22__DISP2_DAT16 0x324 0x724 0x000 0x5 0x0 -#define MX51_PAD_DISP1_DAT23__BOOT_LPB_FREQ1 0x328 0x728 0x000 0x7 0x0 -#define MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x328 0x728 0x000 0x0 0x0 -#define MX51_PAD_DISP1_DAT23__DISP2_D1_CS 0x328 0x728 0x000 0x6 0x0 -#define MX51_PAD_DISP1_DAT23__DISP2_DAT17 0x328 0x728 0x000 0x5 0x0 -#define MX51_PAD_DISP1_DAT23__DISP2_SER_CS 0x328 0x728 0x000 0x4 0x0 -#define MX51_PAD_DI1_PIN3__DI1_PIN3 0x32c 0x72c 0x000 0x0 0x0 -#define MX51_PAD_DI1_PIN2__DI1_PIN2 0x330 0x734 0x000 0x0 0x0 -#define MX51_PAD_DI_GP2__DISP1_SER_CLK 0x338 0x740 0x000 0x0 0x0 -#define MX51_PAD_DI_GP2__DISP2_WAIT 0x338 0x740 0x9a8 0x2 0x1 -#define MX51_PAD_DI_GP3__CSI1_DATA_EN 0x33c 0x744 0x9a0 0x3 0x1 -#define MX51_PAD_DI_GP3__DISP1_SER_DIO 0x33c 0x744 0x9c0 0x0 0x0 -#define MX51_PAD_DI_GP3__FEC_TX_ER 0x33c 0x744 0x000 0x2 0x0 -#define MX51_PAD_DI2_PIN4__CSI2_DATA_EN 0x340 0x748 0x99c 0x3 0x1 -#define MX51_PAD_DI2_PIN4__DI2_PIN4 0x340 0x748 0x000 0x0 0x0 -#define MX51_PAD_DI2_PIN4__FEC_CRS 0x340 0x748 0x950 0x2 0x1 -#define MX51_PAD_DI2_PIN2__DI2_PIN2 0x344 0x74c 0x000 0x0 0x0 -#define MX51_PAD_DI2_PIN2__FEC_MDC 0x344 0x74c 0x000 0x2 0x0 -#define MX51_PAD_DI2_PIN3__DI2_PIN3 0x348 0x750 0x000 0x0 0x0 -#define MX51_PAD_DI2_PIN3__FEC_MDIO 0x348 0x750 0x954 0x2 0x1 -#define MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x34c 0x754 0x000 0x0 0x0 -#define MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x34c 0x754 0x95c 0x2 0x1 -#define MX51_PAD_DI_GP4__DI2_PIN15 0x350 0x758 0x000 0x4 0x0 -#define MX51_PAD_DI_GP4__DISP1_SER_DIN 0x350 0x758 0x9c0 0x0 0x1 -#define MX51_PAD_DI_GP4__DISP2_PIN1 0x350 0x758 0x000 0x3 0x0 -#define MX51_PAD_DI_GP4__FEC_RDATA2 0x350 0x758 0x960 0x2 0x1 -#define MX51_PAD_DISP2_DAT0__DISP2_DAT0 0x354 0x75c 0x000 0x0 0x0 -#define MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x354 0x75c 0x964 0x2 0x1 -#define MX51_PAD_DISP2_DAT0__KEY_COL6 0x354 0x75c 0x9c8 0x4 0x1 -#define MX51_PAD_DISP2_DAT0__UART3_RXD 0x354 0x75c 0x9f4 0x5 0x8 -#define MX51_PAD_DISP2_DAT0__USBH3_CLK 0x354 0x75c 0x9f8 0x3 0x1 -#define MX51_PAD_DISP2_DAT1__DISP2_DAT1 0x358 0x760 0x000 0x0 0x0 -#define MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x358 0x760 0x970 0x2 0x1 -#define MX51_PAD_DISP2_DAT1__KEY_COL7 0x358 0x760 0x9cc 0x4 0x1 -#define MX51_PAD_DISP2_DAT1__UART3_TXD 0x358 0x760 0x000 0x5 0x0 -#define MX51_PAD_DISP2_DAT1__USBH3_DIR 0x358 0x760 0xa1c 0x3 0x1 -#define MX51_PAD_DISP2_DAT2__DISP2_DAT2 0x35c 0x764 0x000 0x0 0x0 -#define MX51_PAD_DISP2_DAT3__DISP2_DAT3 0x360 0x768 0x000 0x0 0x0 -#define MX51_PAD_DISP2_DAT4__DISP2_DAT4 0x364 0x76c 0x000 0x0 0x0 -#define MX51_PAD_DISP2_DAT5__DISP2_DAT5 0x368 0x770 0x000 0x0 0x0 -#define MX51_PAD_DISP2_DAT6__DISP2_DAT6 0x36c 0x774 0x000 0x0 0x0 -#define MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x36c 0x774 0x000 0x2 0x0 -#define MX51_PAD_DISP2_DAT6__GPIO1_19 0x36c 0x774 0x000 0x5 0x0 -#define MX51_PAD_DISP2_DAT6__KEY_ROW4 0x36c 0x774 0x9d0 0x4 0x1 -#define MX51_PAD_DISP2_DAT6__USBH3_STP 0x36c 0x774 0xa24 0x3 0x1 -#define MX51_PAD_DISP2_DAT7__DISP2_DAT7 0x370 0x778 0x000 0x0 0x0 -#define MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x370 0x778 0x000 0x2 0x0 -#define MX51_PAD_DISP2_DAT7__GPIO1_29 0x370 0x778 0x000 0x5 0x0 -#define MX51_PAD_DISP2_DAT7__KEY_ROW5 0x370 0x778 0x9d4 0x4 0x1 -#define MX51_PAD_DISP2_DAT7__USBH3_NXT 0x370 0x778 0xa20 0x3 0x1 -#define MX51_PAD_DISP2_DAT8__DISP2_DAT8 0x374 0x77c 0x000 0x0 0x0 -#define MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x374 0x77c 0x000 0x2 0x0 -#define MX51_PAD_DISP2_DAT8__GPIO1_30 0x374 0x77c 0x000 0x5 0x0 -#define MX51_PAD_DISP2_DAT8__KEY_ROW6 0x374 0x77c 0x9d8 0x4 0x1 -#define MX51_PAD_DISP2_DAT8__USBH3_DATA0 0x374 0x77c 0x9fc 0x3 0x1 -#define MX51_PAD_DISP2_DAT9__AUD6_RXC 0x378 0x780 0x8f4 0x4 0x1 -#define MX51_PAD_DISP2_DAT9__DISP2_DAT9 0x378 0x780 0x000 0x0 0x0 -#define MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x378 0x780 0x000 0x2 0x0 -#define MX51_PAD_DISP2_DAT9__GPIO1_31 0x378 0x780 0x000 0x5 0x0 -#define MX51_PAD_DISP2_DAT9__USBH3_DATA1 0x378 0x780 0xa00 0x3 0x1 -#define MX51_PAD_DISP2_DAT10__DISP2_DAT10 0x37c 0x784 0x000 0x0 0x0 -#define MX51_PAD_DISP2_DAT10__DISP2_SER_CS 0x37c 0x784 0x000 0x5 0x0 -#define MX51_PAD_DISP2_DAT10__FEC_COL 0x37c 0x784 0x94c 0x2 0x1 -#define MX51_PAD_DISP2_DAT10__KEY_ROW7 0x37c 0x784 0x9dc 0x4 0x1 -#define MX51_PAD_DISP2_DAT10__USBH3_DATA2 0x37c 0x784 0xa04 0x3 0x1 -#define MX51_PAD_DISP2_DAT11__AUD6_TXD 0x380 0x788 0x8f0 0x4 0x1 -#define MX51_PAD_DISP2_DAT11__DISP2_DAT11 0x380 0x788 0x000 0x0 0x0 -#define MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x380 0x788 0x968 0x2 0x1 -#define MX51_PAD_DISP2_DAT11__GPIO1_10 0x380 0x788 0x000 0x7 0x0 -#define MX51_PAD_DISP2_DAT11__USBH3_DATA3 0x380 0x788 0xa08 0x3 0x1 -#define MX51_PAD_DISP2_DAT12__AUD6_RXD 0x384 0x78c 0x8ec 0x4 0x1 -#define MX51_PAD_DISP2_DAT12__DISP2_DAT12 0x384 0x78c 0x000 0x0 0x0 -#define MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x384 0x78c 0x96c 0x2 0x1 -#define MX51_PAD_DISP2_DAT12__USBH3_DATA4 0x384 0x78c 0xa0c 0x3 0x1 -#define MX51_PAD_DISP2_DAT13__AUD6_TXC 0x388 0x790 0x8fc 0x4 0x1 -#define MX51_PAD_DISP2_DAT13__DISP2_DAT13 0x388 0x790 0x000 0x0 0x0 -#define MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x388 0x790 0x974 0x2 0x1 -#define MX51_PAD_DISP2_DAT13__USBH3_DATA5 0x388 0x790 0xa10 0x3 0x1 -#define MX51_PAD_DISP2_DAT14__AUD6_TXFS 0x38c 0x794 0x900 0x4 0x1 -#define MX51_PAD_DISP2_DAT14__DISP2_DAT14 0x38c 0x794 0x000 0x0 0x0 -#define MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x38c 0x794 0x958 0x2 0x1 -#define MX51_PAD_DISP2_DAT14__USBH3_DATA6 0x38c 0x794 0xa14 0x3 0x1 -#define MX51_PAD_DISP2_DAT15__AUD6_RXFS 0x390 0x798 0x8f8 0x4 0x1 -#define MX51_PAD_DISP2_DAT15__DISP1_SER_CS 0x390 0x798 0x000 0x5 0x0 -#define MX51_PAD_DISP2_DAT15__DISP2_DAT15 0x390 0x798 0x000 0x0 0x0 -#define MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x390 0x798 0x000 0x2 0x0 -#define MX51_PAD_DISP2_DAT15__USBH3_DATA7 0x390 0x798 0xa18 0x3 0x1 -#define MX51_PAD_SD1_CMD__AUD5_RXFS 0x394 0x79c 0x8e0 0x1 0x1 -#define MX51_PAD_SD1_CMD__CSPI_MOSI 0x394 0x79c 0x91c 0x2 0x2 -#define MX51_PAD_SD1_CMD__SD1_CMD 0x394 0x79c 0x000 0x0 0x0 -#define MX51_PAD_SD1_CLK__AUD5_RXC 0x398 0x7a0 0x8dc 0x1 0x1 -#define MX51_PAD_SD1_CLK__CSPI_SCLK 0x398 0x7a0 0x914 0x2 0x2 -#define MX51_PAD_SD1_CLK__SD1_CLK 0x398 0x7a0 0x000 0x0 0x0 -#define MX51_PAD_SD1_DATA0__AUD5_TXD 0x39c 0x7a4 0x8d8 0x1 0x2 -#define MX51_PAD_SD1_DATA0__CSPI_MISO 0x39c 0x7a4 0x918 0x2 0x1 -#define MX51_PAD_SD1_DATA0__SD1_DATA0 0x39c 0x7a4 0x000 0x0 0x0 -#define MX51_PAD_EIM_DA0__EIM_DA0 0x01c 0x000 0x000 0x0 0x0 -#define MX51_PAD_EIM_DA1__EIM_DA1 0x020 0x000 0x000 0x0 0x0 -#define MX51_PAD_EIM_DA2__EIM_DA2 0x024 0x000 0x000 0x0 0x0 -#define MX51_PAD_EIM_DA3__EIM_DA3 0x028 0x000 0x000 0x0 0x0 -#define MX51_PAD_SD1_DATA1__AUD5_RXD 0x3a0 0x7a8 0x8d4 0x1 0x2 -#define MX51_PAD_SD1_DATA1__SD1_DATA1 0x3a0 0x7a8 0x000 0x0 0x0 -#define MX51_PAD_EIM_DA4__EIM_DA4 0x02c 0x000 0x000 0x0 0x0 -#define MX51_PAD_EIM_DA5__EIM_DA5 0x030 0x000 0x000 0x0 0x0 -#define MX51_PAD_EIM_DA6__EIM_DA6 0x034 0x000 0x000 0x0 0x0 -#define MX51_PAD_EIM_DA7__EIM_DA7 0x038 0x000 0x000 0x0 0x0 -#define MX51_PAD_SD1_DATA2__AUD5_TXC 0x3a4 0x7ac 0x8e4 0x1 0x2 -#define MX51_PAD_SD1_DATA2__SD1_DATA2 0x3a4 0x7ac 0x000 0x0 0x0 -#define MX51_PAD_EIM_DA10__EIM_DA10 0x044 0x000 0x000 0x0 0x0 -#define MX51_PAD_EIM_DA11__EIM_DA11 0x048 0x000 0x000 0x0 0x0 -#define MX51_PAD_EIM_DA8__EIM_DA8 0x03c 0x000 0x000 0x0 0x0 -#define MX51_PAD_EIM_DA9__EIM_DA9 0x040 0x000 0x000 0x0 0x0 -#define MX51_PAD_SD1_DATA3__AUD5_TXFS 0x3a8 0x7b0 0x8e8 0x1 0x2 -#define MX51_PAD_SD1_DATA3__CSPI_SS1 0x3a8 0x7b0 0x920 0x2 0x1 -#define MX51_PAD_SD1_DATA3__SD1_DATA3 0x3a8 0x7b0 0x000 0x0 0x0 -#define MX51_PAD_GPIO1_0__CSPI_SS2 0x3ac 0x7b4 0x924 0x2 0x0 -#define MX51_PAD_GPIO1_0__GPIO1_0 0x3ac 0x7b4 0x000 0x1 0x0 -#define MX51_PAD_GPIO1_0__SD1_CD 0x3ac 0x7b4 0x000 0x0 0x0 -#define MX51_PAD_GPIO1_1__CSPI_MISO 0x3b0 0x7b8 0x918 0x2 0x2 -#define MX51_PAD_GPIO1_1__GPIO1_1 0x3b0 0x7b8 0x000 0x1 0x0 -#define MX51_PAD_GPIO1_1__SD1_WP 0x3b0 0x7b8 0x000 0x0 0x0 -#define MX51_PAD_EIM_DA12__EIM_DA12 0x04c 0x000 0x000 0x0 0x0 -#define MX51_PAD_EIM_DA13__EIM_DA13 0x050 0x000 0x000 0x0 0x0 -#define MX51_PAD_EIM_DA14__EIM_DA14 0x054 0x000 0x000 0x0 0x0 -#define MX51_PAD_EIM_DA15__EIM_DA15 0x058 0x000 0x000 0x0 0x0 -#define MX51_PAD_SD2_CMD__CSPI_MOSI 0x3b4 0x7bc 0x91c 0x2 0x3 -#define MX51_PAD_SD2_CMD__I2C1_SCL 0x3b4 0x7bc 0x9b0 0x1 0x2 -#define MX51_PAD_SD2_CMD__SD2_CMD 0x3b4 0x7bc 0x000 0x0 0x0 -#define MX51_PAD_SD2_CLK__CSPI_SCLK 0x3b8 0x7c0 0x914 0x2 0x3 -#define MX51_PAD_SD2_CLK__I2C1_SDA 0x3b8 0x7c0 0x9b4 0x1 0x2 -#define MX51_PAD_SD2_CLK__SD2_CLK 0x3b8 0x7c0 0x000 0x0 0x0 -#define MX51_PAD_SD2_DATA0__CSPI_MISO 0x3bc 0x7c4 0x918 0x2 0x3 -#define MX51_PAD_SD2_DATA0__SD1_DAT4 0x3bc 0x7c4 0x000 0x1 0x0 -#define MX51_PAD_SD2_DATA0__SD2_DATA0 0x3bc 0x7c4 0x000 0x0 0x0 -#define MX51_PAD_SD2_DATA1__SD1_DAT5 0x3c0 0x7c8 0x000 0x1 0x0 -#define MX51_PAD_SD2_DATA1__SD2_DATA1 0x3c0 0x7c8 0x000 0x0 0x0 -#define MX51_PAD_SD2_DATA1__USBH3_H2_DP 0x3c0 0x7c8 0x000 0x2 0x0 -#define MX51_PAD_SD2_DATA2__SD1_DAT6 0x3c4 0x7cc 0x000 0x1 0x0 -#define MX51_PAD_SD2_DATA2__SD2_DATA2 0x3c4 0x7cc 0x000 0x0 0x0 -#define MX51_PAD_SD2_DATA2__USBH3_H2_DM 0x3c4 0x7cc 0x000 0x2 0x0 -#define MX51_PAD_SD2_DATA3__CSPI_SS2 0x3c8 0x7d0 0x924 0x2 0x1 -#define MX51_PAD_SD2_DATA3__SD1_DAT7 0x3c8 0x7d0 0x000 0x1 0x0 -#define MX51_PAD_SD2_DATA3__SD2_DATA3 0x3c8 0x7d0 0x000 0x0 0x0 -#define MX51_PAD_GPIO1_2__CCM_OUT_2 0x3cc 0x7d4 0x000 0x5 0x0 -#define MX51_PAD_GPIO1_2__GPIO1_2 0x3cc 0x7d4 0x000 0x0 0x0 -#define MX51_PAD_GPIO1_2__I2C2_SCL 0x3cc 0x7d4 0x9b8 0x2 0x3 -#define MX51_PAD_GPIO1_2__PLL1_BYP 0x3cc 0x7d4 0x90c 0x7 0x1 -#define MX51_PAD_GPIO1_2__PWM1_PWMO 0x3cc 0x7d4 0x000 0x1 0x0 -#define MX51_PAD_GPIO1_3__GPIO1_3 0x3d0 0x7d8 0x000 0x0 0x0 -#define MX51_PAD_GPIO1_3__I2C2_SDA 0x3d0 0x7d8 0x9bc 0x2 0x3 -#define MX51_PAD_GPIO1_3__PLL2_BYP 0x3d0 0x7d8 0x910 0x7 0x1 -#define MX51_PAD_GPIO1_3__PWM2_PWMO 0x3d0 0x7d8 0x000 0x1 0x0 -#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ 0x3d4 0x7fc 0x000 0x0 0x0 -#define MX51_PAD_PMIC_INT_REQ__PMIC_PMU_IRQ_B 0x3d4 0x7fc 0x000 0x1 0x0 -#define MX51_PAD_GPIO1_4__DISP2_EXT_CLK 0x3d8 0x804 0x908 0x4 0x1 -#define MX51_PAD_GPIO1_4__EIM_RDY 0x3d8 0x804 0x938 0x3 0x1 -#define MX51_PAD_GPIO1_4__GPIO1_4 0x3d8 0x804 0x000 0x0 0x0 -#define MX51_PAD_GPIO1_4__WDOG1_WDOG_B 0x3d8 0x804 0x000 0x2 0x0 -#define MX51_PAD_GPIO1_5__CSI2_MCLK 0x3dc 0x808 0x000 0x6 0x0 -#define MX51_PAD_GPIO1_5__DISP2_PIN16 0x3dc 0x808 0x000 0x3 0x0 -#define MX51_PAD_GPIO1_5__GPIO1_5 0x3dc 0x808 0x000 0x0 0x0 -#define MX51_PAD_GPIO1_5__WDOG2_WDOG_B 0x3dc 0x808 0x000 0x2 0x0 -#define MX51_PAD_GPIO1_6__DISP2_PIN17 0x3e0 0x80c 0x000 0x4 0x0 -#define MX51_PAD_GPIO1_6__GPIO1_6 0x3e0 0x80c 0x000 0x0 0x0 -#define MX51_PAD_GPIO1_6__REF_EN_B 0x3e0 0x80c 0x000 0x3 0x0 -#define MX51_PAD_GPIO1_7__CCM_OUT_0 0x3e4 0x810 0x000 0x3 0x0 -#define MX51_PAD_GPIO1_7__GPIO1_7 0x3e4 0x810 0x000 0x0 0x0 -#define MX51_PAD_GPIO1_7__SD2_WP 0x3e4 0x810 0x000 0x6 0x0 -#define MX51_PAD_GPIO1_7__SPDIF_OUT1 0x3e4 0x810 0x000 0x2 0x0 -#define MX51_PAD_GPIO1_8__CSI2_DATA_EN 0x3e8 0x814 0x99c 0x2 0x2 -#define MX51_PAD_GPIO1_8__GPIO1_8 0x3e8 0x814 0x000 0x0 0x0 -#define MX51_PAD_GPIO1_8__SD2_CD 0x3e8 0x814 0x000 0x6 0x0 -#define MX51_PAD_GPIO1_8__USBH3_PWR 0x3e8 0x814 0x000 0x1 0x0 -#define MX51_PAD_GPIO1_9__CCM_OUT_1 0x3ec 0x818 0x000 0x3 0x0 -#define MX51_PAD_GPIO1_9__DISP2_D1_CS 0x3ec 0x818 0x000 0x2 0x0 -#define MX51_PAD_GPIO1_9__DISP2_SER_CS 0x3ec 0x818 0x000 0x7 0x0 -#define MX51_PAD_GPIO1_9__GPIO1_9 0x3ec 0x818 0x000 0x0 0x0 -#define MX51_PAD_GPIO1_9__SD2_LCTL 0x3ec 0x818 0x000 0x6 0x0 -#define MX51_PAD_GPIO1_9__USBH3_OC 0x3ec 0x818 0x000 0x1 0x0 - -#endif /* __DTS_IMX51_PINFUNC_H */ diff --git a/sys/gnu/dts/arm/imx51-ts4800.dts b/sys/gnu/dts/arm/imx51-ts4800.dts deleted file mode 100644 index 4344632f794..00000000000 --- a/sys/gnu/dts/arm/imx51-ts4800.dts +++ /dev/null @@ -1,330 +0,0 @@ -/* - * Copyright 2015 Savoir-faire Linux - * - * This device tree is based on imx51-babbage.dts - * - * Licensed under the X11 license or the GPL v2 (or later) - */ - -/dts-v1/; -#include "imx51.dtsi" - -/ { - model = "Technologic Systems TS-4800"; - compatible = "technologic,imx51-ts4800", "fsl,imx51"; - - chosen { - stdout-path = &uart1; - }; - - memory@90000000 { - device_type = "memory"; - reg = <0x90000000 0x10000000>; - }; - - clocks { - ckih1 { - clock-frequency = <22579200>; - }; - - ckih2 { - clock-frequency = <24576000>; - }; - }; - - backlight_reg: regulator-backlight { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enable_lcd>; - regulator-name = "enable_lcd_reg"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio4 9 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 78770>; - brightness-levels = <0 150 200 255>; - default-brightness-level = <1>; - power-supply = <&backlight_reg>; - }; - - display1: disp1 { - compatible = "fsl,imx-parallel-display"; - interface-pix-fmt = "rgb24"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd>; - - display-timings { - 800x480p60 { - native-mode; - clock-frequency = <30066000>; - hactive = <800>; - vactive = <480>; - hfront-porch = <50>; - hback-porch = <70>; - hsync-len = <50>; - vback-porch = <0>; - vfront-porch = <0>; - vsync-len = <50>; - }; - }; - - port { - display0_in: endpoint { - remote-endpoint = <&ipu_di0_disp1>; - }; - }; - }; -}; - -&esdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc1>; - cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec>; - phy-mode = "mii"; - phy-reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>; - phy-reset-duration = <1>; - status = "okay"; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - rtc: m41t00@68 { - compatible = "st,m41t00"; - reg = <0x68>; - }; -}; - -&ipu_di0_disp1 { - remote-endpoint = <&display0_in>; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm_backlight>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -&weim { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_weim>; - status = "okay"; - - fpga@0 { - compatible = "simple-bus"; - fsl,weim-cs-timing = <0x0061008F 0x00000002 0x1c022000 - 0x00000000 0x1c092480 0x00000000>; - reg = <0 0x0000000 0x1d000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0 0x1d000>; - - syscon: syscon@10000 { - compatible = "syscon", "simple-mfd"; - reg = <0x10000 0x3d>; - reg-io-width = <2>; - - wdt { - compatible = "technologic,ts4800-wdt"; - syscon = <&syscon 0xe>; - }; - }; - - touchscreen@12000 { - compatible = "technologic,ts4800-ts"; - reg = <0x12000 0x1000>; - syscon = <&syscon 0x10 6>; - }; - - fpga_irqc: fpga-irqc@15000 { - compatible = "technologic,ts4800-irqc"; - reg = <0x15000 0x1000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_interrupt_fpga>; - interrupt-parent = <&gpio2>; - interrupts= <9 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - #interrupt-cells = <1>; - }; - - can@1a000 { - compatible = "technologic,sja1000"; - reg = <0x1a000 0x100>; - interrupt-parent = <&fpga_irqc>; - interrupts = <1>; - reg-io-width = <2>; - nxp,tx-output-config = <0x06>; - nxp,external-clock-frequency = <24000000>; - }; - }; -}; - -&iomuxc { - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185 - MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185 - MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185 - MX51_PAD_CSPI1_SS0__GPIO4_24 0x85 /* CS0 */ - >; - }; - - pinctrl_enable_lcd: enablelcdgrp { - fsl,pins = < - MX51_PAD_CSI2_D12__GPIO4_9 0x1c5 - >; - }; - - pinctrl_esdhc1: esdhc1grp { - fsl,pins = < - MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5 - MX51_PAD_SD1_CLK__SD1_CLK 0x20d5 - MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5 - MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5 - MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5 - MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5 - MX51_PAD_GPIO1_0__GPIO1_0 0x100 - MX51_PAD_GPIO1_1__GPIO1_1 0x100 - >; - }; - - pinctrl_fec: fecgrp { - fsl,pins = < - MX51_PAD_EIM_EB2__FEC_MDIO 0x000001f5 - MX51_PAD_EIM_EB3__FEC_RDATA1 0x00000085 - MX51_PAD_EIM_CS2__FEC_RDATA2 0x00000085 - MX51_PAD_EIM_CS3__FEC_RDATA3 0x00000085 - MX51_PAD_EIM_CS4__FEC_RX_ER 0x00000180 - MX51_PAD_EIM_CS5__FEC_CRS 0x00000180 - MX51_PAD_DISP2_DAT10__FEC_COL 0x00000180 - MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x00000180 - MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x00002180 - MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x00002004 - MX51_PAD_NANDF_CS2__FEC_TX_ER 0x00002004 - MX51_PAD_DI2_PIN2__FEC_MDC 0x00002004 - MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x00002004 - MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x00002004 - MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x00002004 - MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x00002004 - MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x00002180 - MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x000020a4 - MX51_PAD_EIM_A20__GPIO2_14 0x00000085 /* Phy Reset */ - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed - MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed - >; - }; - - pinctrl_interrupt_fpga: fpgaicgrp { - fsl,pins = < - MX51_PAD_EIM_D27__GPIO2_9 0xe5 - >; - }; - - pinctrl_lcd: lcdgrp { - fsl,pins = < - MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5 - MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5 - MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5 - MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5 - MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5 - MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5 - MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5 - MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5 - MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5 - MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5 - MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5 - MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5 - MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5 - MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5 - MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5 - MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5 - MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5 - MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5 - MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5 - MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5 - MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5 - MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5 - MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5 - MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5 - MX51_PAD_DI1_PIN2__DI1_PIN2 0x5 - MX51_PAD_DI1_PIN3__DI1_PIN3 0x5 - MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5 - MX51_PAD_DI_GP4__DI2_PIN15 0x5 - >; - }; - - pinctrl_pwm_backlight: backlightgrp { - fsl,pins = < - MX51_PAD_GPIO1_2__PWM1_PWMO 0x80000000 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX51_PAD_UART1_RXD__UART1_RXD 0x1c5 - MX51_PAD_UART1_TXD__UART1_TXD 0x1c5 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX51_PAD_UART2_RXD__UART2_RXD 0x1c5 - MX51_PAD_UART2_TXD__UART2_TXD 0x1c5 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX51_PAD_EIM_D25__UART3_RXD 0x1c5 - MX51_PAD_EIM_D26__UART3_TXD 0x1c5 - >; - }; - - pinctrl_weim: weimgrp { - fsl,pins = < - MX51_PAD_EIM_DTACK__EIM_DTACK 0x85 - MX51_PAD_EIM_CS0__EIM_CS0 0x0 - MX51_PAD_EIM_CS1__EIM_CS1 0x0 - MX51_PAD_EIM_EB0__EIM_EB0 0x85 - MX51_PAD_EIM_EB1__EIM_EB1 0x85 - MX51_PAD_EIM_OE__EIM_OE 0x85 - MX51_PAD_EIM_LBA__EIM_LBA 0x85 - >; - }; -}; diff --git a/sys/gnu/dts/arm/imx51-zii-rdu1.dts b/sys/gnu/dts/arm/imx51-zii-rdu1.dts deleted file mode 100644 index 3596060f52e..00000000000 --- a/sys/gnu/dts/arm/imx51-zii-rdu1.dts +++ /dev/null @@ -1,893 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2017 Zodiac Inflight Innovations - */ - -/dts-v1/; -#include "imx51.dtsi" -#include - -/ { - model = "ZII RDU1 Board"; - compatible = "zii,imx51-rdu1", "fsl,imx51"; - - chosen { - stdout-path = &uart1; - }; - - /* Will be filled by the bootloader */ - memory@90000000 { - device_type = "memory"; - reg = <0x90000000 0>; - }; - - aliases { - mdio-gpio0 = &mdio_gpio; - rtc0 = &ds1341; - }; - - clk_26M_osc: 26M_osc { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <26000000>; - }; - - clk_26M_osc_gate: 26M_gate { - compatible = "gpio-gate-clock"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_clk26mhz>; - clocks = <&clk_26M_osc>; - #clock-cells = <0>; - enable-gpios = <&gpio3 1 GPIO_ACTIVE_HIGH>; - }; - - clk_26M_usb: usbhost_gate { - compatible = "gpio-gate-clock"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbgate26mhz>; - clocks = <&clk_26M_osc_gate>; - #clock-cells = <0>; - enable-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; - }; - - clk_26M_snd: snd_gate { - compatible = "gpio-gate-clock"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sndgate26mhz>; - clocks = <&clk_26M_osc_gate>; - #clock-cells = <0>; - enable-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; - }; - - reg_5p0v_main: regulator-5p0v-main { - compatible = "regulator-fixed"; - regulator-name = "5V_MAIN"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - disp0 { - compatible = "fsl,imx-parallel-display"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu_disp1>; - - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - display_in: endpoint { - remote-endpoint = <&ipu_di0_disp1>; - }; - }; - - port@1 { - reg = <1>; - - display_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; - - panel { - /* no compatible here, bootloader will patch in correct one */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_panel>; - power-supply = <®_3p3v>; - enable-gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>; - status = "disabled"; - - port { - panel_in: endpoint { - remote-endpoint = <&display_out>; - }; - }; - }; - - i2c_gpio: i2c-gpio { - compatible = "i2c-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_swi2c>; - gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>, /* sda */ - <&gpio3 4 GPIO_ACTIVE_HIGH>; /* scl */ - i2c-gpio,delay-us = <50>; - status = "okay"; - - #address-cells = <1>; - #size-cells = <0>; - - sgtl5000: codec@a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - clocks = <&clk_26M_snd>; - VDDA-supply = <&vdig_reg>; - VDDIO-supply = <&vvideo_reg>; - #sound-dai-cells = <0>; - }; - }; - - spi_gpio: spi-gpio { - compatible = "spi-gpio"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpiospi0>; - status = "okay"; - - gpio-sck = <&gpio4 15 GPIO_ACTIVE_HIGH>; - gpio-mosi = <&gpio4 12 GPIO_ACTIVE_HIGH>; - gpio-miso = <&gpio4 11 GPIO_ACTIVE_HIGH>; - num-chipselects = <1>; - cs-gpios = <&gpio4 14 GPIO_ACTIVE_HIGH>; - - eeprom@0 { - compatible = "eeprom-93xx46"; - reg = <0>; - spi-max-frequency = <1000000>; - spi-cs-high; - data-size = <8>; - }; - }; - - mdio_gpio: mdio-gpio { - compatible = "virtual,mdio-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_swmdio>; - gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>, /* mdc */ - <&gpio3 25 GPIO_ACTIVE_HIGH>; /* mdio */ - - #address-cells = <1>; - #size-cells = <0>; - - switch@0 { - compatible = "marvell,mv88e6085"; - reg = <0>; - dsa,member = <0 0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "cpu"; - ethernet = <&fec>; - - fixed-link { - speed = <100>; - full-duplex; - }; - }; - - port@1 { - reg = <1>; - label = "netaux"; - }; - - port@3 { - reg = <3>; - label = "netright"; - }; - - port@4 { - reg = <4>; - label = "netleft"; - }; - }; - }; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "Front"; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&sound_codec>; - simple-audio-card,frame-master = <&sound_codec>; - simple-audio-card,widgets = - "Headphone", "Headphone Jack"; - simple-audio-card,routing = - "Headphone Jack", "HPLEFT", - "Headphone Jack", "HPRIGHT"; - simple-audio-card,aux-devs = <&hpa1>; - - sound_cpu: simple-audio-card,cpu { - sound-dai = <&ssi2>; - }; - - sound_codec: simple-audio-card,codec { - sound-dai = <&sgtl5000>; - clocks = <&clk_26M_snd>; - }; - }; - - usbh1phy: usbphy1 { - compatible = "usb-nop-xceiv"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh1phy>; - clocks = <&clk_26M_usb>; - clock-names = "main_clk"; - reset-gpios = <&gpio4 8 GPIO_ACTIVE_LOW>; - vcc-supply = <&vusb_reg>; - #phy-cells = <0>; - }; - - usbh2phy: usbphy2 { - compatible = "usb-nop-xceiv"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh2phy>; - clocks = <&clk_26M_usb>; - clock-names = "main_clk"; - reset-gpios = <&gpio4 7 GPIO_ACTIVE_LOW>; - vcc-supply = <&vusb_reg>; - #phy-cells = <0>; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; - - ssi2 { - fsl,audmux-port = <1>; - fsl,port-config = < - (IMX_AUDMUX_V2_PTCR_SYN | - IMX_AUDMUX_V2_PTCR_TFSEL(2) | - IMX_AUDMUX_V2_PTCR_TCSEL(2) | - IMX_AUDMUX_V2_PTCR_TFSDIR | - IMX_AUDMUX_V2_PTCR_TCLKDIR) - IMX_AUDMUX_V2_PDCR_RXDSEL(2) - >; - }; - - aud3 { - fsl,audmux-port = <2>; - fsl,port-config = < - IMX_AUDMUX_V2_PTCR_SYN - IMX_AUDMUX_V2_PDCR_RXDSEL(1) - >; - }; -}; - -&cpu { - cpu-supply = <&sw1_reg>; -}; - -&ecspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>, - <&gpio4 25 GPIO_ACTIVE_LOW>; - status = "okay"; - - pmic@0 { - compatible = "fsl,mc13892"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - spi-max-frequency = <6000000>; - spi-cs-high; - reg = <0>; - interrupt-parent = <&gpio1>; - interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; - fsl,mc13xxx-uses-adc; - - regulators { - sw1_reg: sw1 { - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1375000>; - regulator-boot-on; - regulator-always-on; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1850000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3_reg: sw3 { - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1850000>; - regulator-boot-on; - regulator-always-on; - }; - - sw4_reg: sw4 { - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1850000>; - regulator-boot-on; - regulator-always-on; - }; - - vpll_reg: vpll { - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - vdig_reg: vdig { - regulator-min-microvolt = <1650000>; - regulator-max-microvolt = <1650000>; - regulator-boot-on; - }; - - vsd_reg: vsd { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3150000>; - }; - - vusb_reg: vusb { - regulator-always-on; - }; - - vusb2_reg: vusb2 { - regulator-min-microvolt = <2400000>; - regulator-max-microvolt = <2775000>; - regulator-boot-on; - regulator-always-on; - }; - - vvideo_reg: vvideo { - regulator-min-microvolt = <2775000>; - regulator-max-microvolt = <2775000>; - }; - - vaudio_reg: vaudio { - regulator-min-microvolt = <2300000>; - regulator-max-microvolt = <3000000>; - }; - - vcam_reg: vcam { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <3000000>; - }; - - vgen1_reg: vgen1 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - vgen2_reg: vgen2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3150000>; - regulator-always-on; - }; - - vgen3_reg: vgen3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2900000>; - regulator-always-on; - }; - }; - - leds { - #address-cells = <1>; - #size-cells = <0>; - led-control = <0x0 0x0 0x3f83f8 0x0>; - - sysled0@3 { - reg = <3>; - label = "system:green:status"; - linux,default-trigger = "default-on"; - }; - - sysled1@4 { - reg = <4>; - label = "system:green:act"; - linux,default-trigger = "heartbeat"; - }; - }; - }; - - flash@1 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "atmel,at45db642d", "atmel,at45", "atmel,dataflash"; - spi-max-frequency = <25000000>; - reg = <1>; - }; -}; - -&esdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc1>; - bus-width = <4>; - no-1-8-v; - non-removable; - no-sdio; - no-sd; - status = "okay"; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec>; - phy-mode = "mii"; - phy-reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>; - phy-supply = <&vgen3_reg>; - status = "okay"; -}; - -&gpio1 { - gpio-line-names = "", "", "", "", - "", "", "", "", - "", "hp-amp-shutdown-b", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", ""; - - unused-sd3-wp-gpio { - /* - * See pinctrl_esdhc1 below for more details on this - */ - gpio-hog; - gpios = <1 GPIO_ACTIVE_HIGH>; - output-high; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - hpa1: amp@60 { - compatible = "ti,tpa6130a2"; - reg = <0x60>; - Vdd-supply = <®_3p3v>; - }; - - ds1341: rtc@68 { - compatible = "dallas,ds1341"; - reg = <0x68>; - }; - - /* touch nodes default disabled, bootloader will enable the right one */ - - touchscreen@4b { - compatible = "atmel,maxtouch"; - reg = <0x4b>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ts>; - interrupt-parent = <&gpio3>; - interrupts = <12 IRQ_TYPE_LEVEL_LOW>; - status = "disabled"; - }; - - touchscreen@4c { - compatible = "atmel,maxtouch"; - reg = <0x4c>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ts>; - interrupt-parent = <&gpio3>; - interrupts = <12 IRQ_TYPE_LEVEL_LOW>; - status = "disabled"; - }; - - touchscreen@20 { - compatible = "syna,rmi4-i2c"; - reg = <0x20>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ts>; - interrupt-parent = <&gpio3>; - interrupts = <12 IRQ_TYPE_LEVEL_LOW>; - status = "disabled"; - - #address-cells = <1>; - #size-cells = <0>; - - rmi4-f01@1 { - reg = <0x1>; - syna,nosleep-mode = <2>; - }; - - rmi4-f11@11 { - reg = <0x11>; - touchscreen-inverted-x; - touchscreen-swapped-x-y; - syna,sensor-type = <1>; - }; - }; - -}; - -&ipu_di0_disp1 { - remote-endpoint = <&display_in>; -}; - -&pmu { - secure-reg-access; -}; - -&ssi2 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; - - rave-sp { - compatible = "zii,rave-sp-rdu1"; - current-speed = <38400>; - #address-cells = <1>; - #size-cells = <1>; - - watchdog { - compatible = "zii,rave-sp-watchdog"; - }; - - backlight { - compatible = "zii,rave-sp-backlight"; - }; - - pwrbutton { - compatible = "zii,rave-sp-pwrbutton"; - }; - - eeprom@a3 { - compatible = "zii,rave-sp-eeprom"; - reg = <0xa3 0x2000>; - #address-cells = <1>; - #size-cells = <1>; - zii,eeprom-name = "dds-eeprom"; - }; - - eeprom@a4 { - compatible = "zii,rave-sp-eeprom"; - reg = <0xa4 0x4000>; - #address-cells = <1>; - #size-cells = <1>; - zii,eeprom-name = "main-eeprom"; - }; - - eeprom@ae { - compatible = "zii,rave-sp-eeprom"; - reg = <0xae 0x200>; - zii,eeprom-name = "switch-eeprom"; - /* - * Not all RDU1s have this functionality, so we - * rely on the bootloader to enable this - */ - status = "disabled"; - }; - }; -}; - -&usbh1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh1>; - dr_mode = "host"; - phy_type = "ulpi"; - fsl,usbphy = <&usbh1phy>; - disable-over-current; - maximum-speed = "full-speed"; - vbus-supply = <®_5p0v_main>; - status = "okay"; -}; - -&usbh2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh2>; - dr_mode = "host"; - phy_type = "ulpi"; - fsl,usbphy = <&usbh2phy>; - disable-over-current; - vbus-supply = <®_5p0v_main>; - status = "okay"; -}; - -&usbphy0 { - vcc-supply = <&vusb_reg>; -}; - -&usbotg { - dr_mode = "host"; - disable-over-current; - phy_type = "utmi_wide"; - vbus-supply = <®_5p0v_main>; - status = "okay"; -}; - -&wdog1 { - status = "disabled"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_hog: hoggrp { - fsl,pins = < - MX51_PAD_GPIO1_9__GPIO1_9 0x5e - >; - }; - - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0xa5 - MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x85 - MX51_PAD_AUD3_BB_CK__AUD3_TXC 0xa5 - MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x85 - >; - }; - - pinctrl_clk26mhz: clk26mhzgrp { - fsl,pins = < - MX51_PAD_DI1_PIN12__GPIO3_1 0x85 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185 - MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185 - MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185 - MX51_PAD_CSPI1_SS0__GPIO4_24 0x85 - MX51_PAD_CSPI1_SS1__GPIO4_25 0x85 - >; - }; - - pinctrl_esdhc1: esdhc1grp { - fsl,pins = < - MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5 - MX51_PAD_SD1_CLK__SD1_CLK 0x20d5 - MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5 - MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5 - MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5 - MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5 - /* - * GPIO1_1 is not directly used by eSDHC1 in - * any capacity, but earlier versions of RDU1 - * used that pin as WP GPIO for eSDHC3 and - * because of that that pad has an external - * pull-up resistor. This is problematic - * because out of reset the pad is configured - * as ALT0 which serves as SD1_WP, which, when - * pulled high by and external pull-up, will - * inhibit execution of any write request to - * attached eMMC device. - * - * To avoid this problem we configure the pad - * to ALT1/GPIO and avoid driving SD1_WP - * signal high. - */ - MX51_PAD_GPIO1_1__GPIO1_1 0x0000 - >; - }; - - pinctrl_fec: fecgrp { - fsl,pins = < - MX51_PAD_EIM_EB2__FEC_MDIO 0x1f5 - MX51_PAD_NANDF_D9__FEC_RDATA0 0x2180 - MX51_PAD_EIM_EB3__FEC_RDATA1 0x180 - MX51_PAD_EIM_CS2__FEC_RDATA2 0x180 - MX51_PAD_EIM_CS3__FEC_RDATA3 0x180 - MX51_PAD_EIM_CS4__FEC_RX_ER 0x180 - MX51_PAD_NANDF_D11__FEC_RX_DV 0x2084 - MX51_PAD_EIM_CS5__FEC_CRS 0x180 - MX51_PAD_NANDF_RB2__FEC_COL 0x2180 - MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x2180 - MX51_PAD_NANDF_CS2__FEC_TX_ER 0x2004 - MX51_PAD_NANDF_CS3__FEC_MDC 0x2004 - MX51_PAD_NANDF_D8__FEC_TDATA0 0x2180 - MX51_PAD_NANDF_CS4__FEC_TDATA1 0x2004 - MX51_PAD_NANDF_CS5__FEC_TDATA2 0x2004 - MX51_PAD_NANDF_CS6__FEC_TDATA3 0x2004 - MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x2004 - MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x2180 - MX51_PAD_EIM_A20__GPIO2_14 0x85 - >; - }; - - pinctrl_gpiospi0: gpiospi0grp { - fsl,pins = < - MX51_PAD_CSI2_D18__GPIO4_11 0x85 - MX51_PAD_CSI2_D19__GPIO4_12 0x85 - MX51_PAD_CSI2_HSYNC__GPIO4_14 0x85 - MX51_PAD_CSI2_PIXCLK__GPIO4_15 0x85 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed - MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed - >; - }; - - pinctrl_ipu_disp1: ipudisp1grp { - fsl,pins = < - MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5 - MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5 - MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5 - MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5 - MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5 - MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5 - MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5 - MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5 - MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5 - MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5 - MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5 - MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5 - MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5 - MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5 - MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5 - MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5 - MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5 - MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5 - MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5 - MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5 - MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5 - MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5 - MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5 - MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5 - MX51_PAD_DI1_PIN2__DI1_PIN2 0x5 - MX51_PAD_DI1_PIN3__DI1_PIN3 0x5 - MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5 - >; - }; - - pinctrl_panel: panelgrp { - fsl,pins = < - MX51_PAD_DI1_D0_CS__GPIO3_3 0x85 - >; - }; - - pinctrl_pmic: pmicgrp { - fsl,pins = < - MX51_PAD_GPIO1_4__GPIO1_4 0x1e0 - MX51_PAD_GPIO1_8__GPIO1_8 0x21e2 - >; - }; - - pinctrl_sndgate26mhz: sndgate26mhzgrp { - fsl,pins = < - MX51_PAD_CSPI1_RDY__GPIO4_26 0x85 - >; - }; - - pinctrl_swi2c: swi2cgrp { - fsl,pins = < - MX51_PAD_GPIO1_2__GPIO1_2 0xc5 - MX51_PAD_DI1_D1_CS__GPIO3_4 0x400001f5 - >; - }; - - pinctrl_swmdio: swmdiogrp { - fsl,pins = < - MX51_PAD_NANDF_D14__GPIO3_26 0x21e6 - MX51_PAD_NANDF_D15__GPIO3_25 0x21e6 - >; - }; - - pinctrl_ts: tsgrp { - fsl,pins = < - MX51_PAD_CSI1_D8__GPIO3_12 0x04 - MX51_PAD_CSI1_D9__GPIO3_13 0x85 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX51_PAD_UART1_RXD__UART1_RXD 0x1c5 - MX51_PAD_UART1_TXD__UART1_TXD 0x1c5 - MX51_PAD_UART1_RTS__UART1_RTS 0x1c4 - MX51_PAD_UART1_CTS__UART1_CTS 0x1c4 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX51_PAD_UART2_RXD__UART2_RXD 0xc5 - MX51_PAD_UART2_TXD__UART2_TXD 0xc5 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX51_PAD_EIM_D25__UART3_RXD 0x1c5 - MX51_PAD_EIM_D26__UART3_TXD 0x1c5 - >; - }; - - pinctrl_usbgate26mhz: usbgate26mhzgrp { - fsl,pins = < - MX51_PAD_DISP2_DAT6__GPIO1_19 0x85 - >; - }; - - pinctrl_usbh1: usbh1grp { - fsl,pins = < - MX51_PAD_USBH1_STP__USBH1_STP 0x0 - MX51_PAD_USBH1_CLK__USBH1_CLK 0x0 - MX51_PAD_USBH1_DIR__USBH1_DIR 0x0 - MX51_PAD_USBH1_NXT__USBH1_NXT 0x0 - MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x0 - MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x0 - MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x0 - MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x0 - MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x0 - MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x0 - MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x0 - MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x0 - >; - }; - - pinctrl_usbh1phy: usbh1phygrp { - fsl,pins = < - MX51_PAD_NANDF_D0__GPIO4_8 0x85 - >; - }; - - pinctrl_usbh2: usbh2grp { - fsl,pins = < - MX51_PAD_EIM_A26__USBH2_STP 0x0 - MX51_PAD_EIM_A24__USBH2_CLK 0x0 - MX51_PAD_EIM_A25__USBH2_DIR 0x0 - MX51_PAD_EIM_A27__USBH2_NXT 0x0 - MX51_PAD_EIM_D16__USBH2_DATA0 0x0 - MX51_PAD_EIM_D17__USBH2_DATA1 0x0 - MX51_PAD_EIM_D18__USBH2_DATA2 0x0 - MX51_PAD_EIM_D19__USBH2_DATA3 0x0 - MX51_PAD_EIM_D20__USBH2_DATA4 0x0 - MX51_PAD_EIM_D21__USBH2_DATA5 0x0 - MX51_PAD_EIM_D22__USBH2_DATA6 0x0 - MX51_PAD_EIM_D23__USBH2_DATA7 0x0 - >; - }; - - pinctrl_usbh2phy: usbh2phygrp { - fsl,pins = < - MX51_PAD_NANDF_D1__GPIO4_7 0x85 - >; - }; -}; diff --git a/sys/gnu/dts/arm/imx51-zii-scu2-mezz.dts b/sys/gnu/dts/arm/imx51-zii-scu2-mezz.dts deleted file mode 100644 index aa91e5dde4b..00000000000 --- a/sys/gnu/dts/arm/imx51-zii-scu2-mezz.dts +++ /dev/null @@ -1,457 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) - -/* - * Copyright (C) 2018 Zodiac Inflight Innovations - */ - -/dts-v1/; - -#include "imx51.dtsi" - -/ { - model = "ZII SCU2 Mezz Board"; - compatible = "zii,imx51-scu2-mezz", "fsl,imx51"; - - chosen { - stdout-path = &uart1; - }; - - /* Will be filled by the bootloader */ - memory@90000000 { - device_type = "memory"; - reg = <0x90000000 0>; - }; - - aliases { - mdio-gpio0 = &mdio_gpio; - }; - - usb_vbus: regulator-usb-vbus { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_mmc_reset>; - gpio = <&gpio3 13 GPIO_ACTIVE_LOW>; - startup-delay-us = <150000>; - regulator-name = "usb_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - mdio_gpio: mdio-gpio { - compatible = "virtual,mdio-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_swmdio>; - gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>, /* mdc */ - <&gpio2 6 GPIO_ACTIVE_HIGH>; /* mdio */ - #address-cells = <1>; - #size-cells = <0>; - - switch@0 { - compatible = "marvell,mv88e6085"; - reg = <0>; - dsa,member = <0 0>; - eeprom-length = <512>; - interrupt-parent = <&gpio1>; - interrupts = <7 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells = <2>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "port4"; - }; - - port@1 { - reg = <1>; - label = "port5"; - }; - - port@2 { - reg = <2>; - label = "port6"; - }; - - port@3 { - reg = <3>; - label = "port7"; - }; - - port@4 { - reg = <4>; - label = "cpu"; - ethernet = <&fec>; - - fixed-link { - speed = <100>; - full-duplex; - }; - }; - - port@5 { - reg = <5>; - label = "mezz2esb"; - phy-mode = "sgmii"; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; - }; - }; -}; - -&cpu { - cpu-supply = <&sw1_reg>; -}; - -&ecspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>, - <&gpio4 25 GPIO_ACTIVE_LOW>; - status = "okay"; - - pmic@0 { - compatible = "fsl,mc13892"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - spi-max-frequency = <6000000>; - spi-cs-high; - reg = <0>; - interrupt-parent = <&gpio1>; - interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; - fsl,mc13xxx-uses-adc; - - regulators { - sw1_reg: sw1 { - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1375000>; - regulator-boot-on; - regulator-always-on; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1850000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3_reg: sw3 { - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1850000>; - regulator-boot-on; - regulator-always-on; - }; - - sw4_reg: sw4 { - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1850000>; - regulator-boot-on; - regulator-always-on; - }; - - vpll_reg: vpll { - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - vdig_reg: vdig { - regulator-min-microvolt = <1650000>; - regulator-max-microvolt = <1650000>; - regulator-boot-on; - }; - - vsd_reg: vsd { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3150000>; - regulator-always-on; - }; - - vusb_reg: vusb { - regulator-always-on; - }; - - vusb2_reg: vusb2 { - regulator-min-microvolt = <2400000>; - regulator-max-microvolt = <2775000>; - regulator-boot-on; - regulator-always-on; - }; - - vvideo_reg: vvideo { - regulator-min-microvolt = <2775000>; - regulator-max-microvolt = <2775000>; - }; - - vaudio_reg: vaudio { - regulator-min-microvolt = <2300000>; - regulator-max-microvolt = <3000000>; - }; - - vcam_reg: vcam { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <3000000>; - }; - - vgen1_reg: vgen1 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - vgen2_reg: vgen2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3150000>; - regulator-always-on; - }; - - vgen3_reg: vgen3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2900000>; - regulator-always-on; - }; - }; - - leds { - #address-cells = <1>; - #size-cells = <0>; - led-control = <0x0 0x0 0x3f83f8 0x0>; - - sysled3: led3@3 { - reg = <3>; - label = "system:red:power"; - linux,default-trigger = "default-on"; - }; - - sysled4: led4@4 { - reg = <4>; - label = "system:green:act"; - linux,default-trigger = "heartbeat"; - }; - }; - }; - - flash@1 { - compatible = "atmel,at45", "atmel,dataflash"; - reg = <1>; - spi-max-frequency = <25000000>; - }; -}; - -&esdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc1>; - bus-width = <8>; - non-removable; - no-1-8-v; - no-sdio; - no-sd; - status = "okay"; -}; - -&esdhc4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc4>; - bus-width = <4>; - no-1-8-v; - no-sdio; - cd-gpios = <&gpio4 8 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec>; - phy-mode = "mii"; - status = "okay"; - phy-reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>; - phy-reset-duration = <1>; - phy-supply = <&vgen3_reg>; - phy-handle = <ðphy>; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy: ethernet-phy@0 { - reg = <0>; - max-speed = <100>; - }; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - eeprom@50 { - compatible = "atmel,24c04"; - pagesize = <16>; - reg = <0x50>; - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; - - rave-sp { - compatible = "zii,rave-sp-mezz"; - current-speed = <57600>; - #address-cells = <1>; - #size-cells = <1>; - - watchdog { - compatible = "zii,rave-sp-watchdog-legacy"; - }; - - eeprom@a4 { - compatible = "zii,rave-sp-eeprom"; - reg = <0xa4 0x4000>; - #address-cells = <1>; - #size-cells = <1>; - zii,eeprom-name = "main-eeprom"; - }; - }; -}; - -&usbotg { - dr_mode = "host"; - disable-over-current; - phy_type = "utmi_wide"; - vbus-supply = <&usb_vbus>; - status = "okay"; -}; - -&usbphy0 { - vcc-supply = <&vusb2_reg>; -}; - -&vpu { - status = "disabled"; -}; - -&wdog1 { - status = "disabled"; -}; - -&iomuxc { - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185 - MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185 - MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185 - MX51_PAD_CSPI1_SS0__GPIO4_24 0x85 - MX51_PAD_CSPI1_SS1__GPIO4_25 0x85 - >; - }; - - pinctrl_esdhc1: esdhc1grp { - fsl,pins = < - MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5 - MX51_PAD_SD1_CLK__SD1_CLK 0x20d5 - MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5 - MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5 - MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5 - MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5 - MX51_PAD_SD2_DATA0__SD1_DAT4 0x20d5 - MX51_PAD_SD2_DATA1__SD1_DAT5 0x20d5 - MX51_PAD_SD2_DATA2__SD1_DAT6 0x20d5 - MX51_PAD_SD2_DATA3__SD1_DAT7 0x20d5 - >; - }; - - pinctrl_esdhc4: esdhc4grp { - fsl,pins = < - MX51_PAD_NANDF_RB1__SD4_CMD 0x400020d5 - MX51_PAD_NANDF_CS2__SD4_CLK 0x20d5 - MX51_PAD_NANDF_CS3__SD4_DAT0 0x20d5 - MX51_PAD_NANDF_CS4__SD4_DAT1 0x20d5 - MX51_PAD_NANDF_CS5__SD4_DAT2 0x20d5 - MX51_PAD_NANDF_CS6__SD4_DAT3 0x20d5 - MX51_PAD_NANDF_D0__GPIO4_8 0x100 - >; - }; - - pinctrl_fec: fecgrp { - fsl,pins = < - MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x2004 - MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x2004 - MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x2004 - MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x2004 - MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x2004 - MX51_PAD_DISP2_DAT10__FEC_COL 0x0180 - MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x0180 - MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x20a4 - MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x20a4 - MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x2180 - MX51_PAD_DI_GP3__FEC_TX_ER 0x2004 - MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x2180 - MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x0085 - MX51_PAD_DI_GP4__FEC_RDATA2 0x0085 - MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x0085 - MX51_PAD_DI2_PIN2__FEC_MDC 0x2004 - MX51_PAD_DI2_PIN3__FEC_MDIO 0x01f5 - MX51_PAD_DI2_PIN4__FEC_CRS 0x0180 - MX51_PAD_EIM_A20__GPIO2_14 0x0085 - MX51_PAD_EIM_A21__GPIO2_15 0x00e5 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed - MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed - >; - }; - - pinctrl_pmic: pmicgrp { - fsl,pins = < - MX51_PAD_GPIO1_4__GPIO1_4 0x85 - MX51_PAD_GPIO1_8__GPIO1_8 0xe5 - >; - }; - - pinctrl_swmdio: swmdiogrp { - fsl,pins = < - MX51_PAD_EIM_D22__GPIO2_6 0x100 - MX51_PAD_EIM_D23__GPIO2_7 0x100 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX51_PAD_UART1_RXD__UART1_RXD 0x1c5 - MX51_PAD_UART1_TXD__UART1_TXD 0x1c5 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX51_PAD_UART3_RXD__UART3_RXD 0x1c5 - MX51_PAD_UART3_TXD__UART3_TXD 0x1c5 - >; - }; - - pinctrl_usb_mmc_reset: usbmmcgrp { - fsl,pins = < - MX51_PAD_CSI1_D9__GPIO3_13 0x85 - >; - }; -}; diff --git a/sys/gnu/dts/arm/imx51-zii-scu3-esb.dts b/sys/gnu/dts/arm/imx51-zii-scu3-esb.dts deleted file mode 100644 index 875b10a7d67..00000000000 --- a/sys/gnu/dts/arm/imx51-zii-scu3-esb.dts +++ /dev/null @@ -1,472 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) - -/* - * Copyright (C) 2018 Zodiac Inflight Innovations - */ - -/dts-v1/; - -#include "imx51.dtsi" - -/ { - model = "ZII SCU3 ESB board"; - compatible = "zii,imx51-scu3-esb", "fsl,imx51"; - - chosen { - stdout-path = &uart1; - }; - - /* Will be filled by the bootloader */ - memory@90000000 { - device_type = "memory"; - reg = <0x90000000 0>; - }; - - usb_vbus: regulator-usb-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_mmc_reset>; - gpio = <&gpio4 19 GPIO_ACTIVE_LOW>; - startup-delay-us = <150000>; - }; -}; - -&cpu { - cpu-supply = <&sw1_reg>; -}; - -&ecspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>, - <&gpio4 25 GPIO_ACTIVE_LOW>; - status = "okay"; - - pmic@0 { - compatible = "fsl,mc13892"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - spi-max-frequency = <6000000>; - spi-cs-high; - reg = <0>; - interrupt-parent = <&gpio1>; - interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; - fsl,mc13xxx-uses-adc; - - regulators { - sw1_reg: sw1 { - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1375000>; - regulator-boot-on; - regulator-always-on; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1850000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3_reg: sw3 { - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1850000>; - regulator-boot-on; - regulator-always-on; - }; - - sw4_reg: sw4 { - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1850000>; - regulator-boot-on; - regulator-always-on; - }; - - vpll_reg: vpll { - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - vdig_reg: vdig { - regulator-min-microvolt = <1650000>; - regulator-max-microvolt = <1650000>; - regulator-boot-on; - }; - - vsd_reg: vsd { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3150000>; - }; - - vusb_reg: vusb { - regulator-always-on; - }; - - vusb2_reg: vusb2 { - regulator-min-microvolt = <2400000>; - regulator-max-microvolt = <2775000>; - regulator-boot-on; - regulator-always-on; - }; - - vvideo_reg: vvideo { - regulator-min-microvolt = <2775000>; - regulator-max-microvolt = <2775000>; - }; - - vaudio_reg: vaudio { - regulator-min-microvolt = <2300000>; - regulator-max-microvolt = <3000000>; - }; - - vcam_reg: vcam { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <3000000>; - }; - - vgen1_reg: vgen1 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - vgen2_reg: vgen2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3150000>; - regulator-always-on; - }; - - vgen3_reg: vgen3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2900000>; - regulator-always-on; - }; - }; - - leds { - #address-cells = <1>; - #size-cells = <0>; - led-control = <0x0 0x0 0x3f83f8 0x0>; - - sysled3: led3@3 { - reg = <3>; - label = "system:red:power"; - linux,default-trigger = "default-on"; - }; - - sysled4: led4@4 { - reg = <4>; - label = "system:green:act"; - linux,default-trigger = "heartbeat"; - }; - }; - }; - - flash@1 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "atmel,at45", "atmel,dataflash"; - spi-max-frequency = <25000000>; - reg = <1>; - }; -}; - -&esdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc1>; - bus-width = <8>; - non-removable; - no-1-8-v; - no-sdio; - no-sd; - status = "okay"; -}; - -&esdhc4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc4>; - bus-width = <4>; - no-1-8-v; - no-sdio; - cd-gpios = <&gpio4 8 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec>; - phy-mode = "mii"; - status = "okay"; - - fixed-link { - speed = <100>; - full-duplex; - }; - - fec_mdio: mdio { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - switch@0 { - compatible = "marvell,mv88e6085"; - reg = <0>; - dsa,member = <0 0>; - eeprom-length = <512>; - interrupt-parent = <&gpio4>; - interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - #interrupt-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_switch>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "port1"; - }; - - port@1 { - reg = <1>; - label = "port2"; - }; - - port@2 { - reg = <2>; - label = "port3"; - }; - - port@3 { - reg = <3>; - label = "scu2scu"; - }; - - port@4 { - reg = <4>; - label = "esb2host"; - }; - - port@5 { - reg = <5>; - label = "esb2mezz"; - phy-mode = "sgmii"; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - - port@6 { - reg = <6>; - label = "cpu"; - phy-mode = "mii"; - ethernet = <&fec>; - - fixed-link { - speed = <100>; - full-duplex; - }; - }; - }; - }; - }; -}; - -&ipu { - status = "disabled"; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - eeprom@50 { - compatible = "atmel,24c04"; - pagesize = <16>; - reg = <0x50>; - }; - - lm75@48 { - compatible = "national,lm75"; - reg = <0x48>; - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; - - rave-sp { - compatible = "zii,rave-sp-esb"; - current-speed = <57600>; - #address-cells = <1>; - #size-cells = <1>; - - watchdog { - compatible = "zii,rave-sp-watchdog-legacy"; - }; - - eeprom@a4 { - compatible = "zii,rave-sp-eeprom"; - reg = <0xa4 0x4000>; - #address-cells = <1>; - #size-cells = <1>; - zii,eeprom-name = "main-eeprom"; - }; - }; -}; - -&usbotg { - dr_mode = "host"; - disable-over-current; - phy_type = "utmi_wide"; - vbus-supply = <&usb_vbus>; - status = "okay"; -}; - -&usbphy0 { - vcc-supply = <&vusb2_reg>; -}; - -&vpu { - status = "disabled"; -}; - -&wdog1 { - status = "disabled"; -}; - -&iomuxc { - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185 - MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185 - MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185 - MX51_PAD_CSPI1_SS0__GPIO4_24 0x85 - MX51_PAD_CSPI1_SS1__GPIO4_25 0x85 - >; - }; - - pinctrl_esdhc1: esdhc1grp { - fsl,pins = < - MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5 - MX51_PAD_SD1_CLK__SD1_CLK 0x20d5 - MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5 - MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5 - MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5 - MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5 - MX51_PAD_SD2_DATA0__SD1_DAT4 0x20d5 - MX51_PAD_SD2_DATA1__SD1_DAT5 0x20d5 - MX51_PAD_SD2_DATA2__SD1_DAT6 0x20d5 - MX51_PAD_SD2_DATA3__SD1_DAT7 0x20d5 - >; - }; - - pinctrl_esdhc4: esdhc4grp { - fsl,pins = < - MX51_PAD_NANDF_RB1__SD4_CMD 0x400020d5 - MX51_PAD_NANDF_CS2__SD4_CLK 0x20d5 - MX51_PAD_NANDF_CS3__SD4_DAT0 0x20d5 - MX51_PAD_NANDF_CS4__SD4_DAT1 0x20d5 - MX51_PAD_NANDF_CS5__SD4_DAT2 0x20d5 - MX51_PAD_NANDF_CS6__SD4_DAT3 0x20d5 - MX51_PAD_NANDF_D0__GPIO4_8 0x100 - >; - }; - - pinctrl_fec: fecgrp { - fsl,pins = < - MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x2004 - MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x2004 - MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x2004 - MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x2004 - MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x2004 - MX51_PAD_DISP2_DAT10__FEC_COL 0x0180 - MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x0180 - MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x20a4 - - MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x2180 - MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x2180 - MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x0085 - MX51_PAD_DI_GP4__FEC_RDATA2 0x0085 - MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x0085 - MX51_PAD_DI2_PIN2__FEC_MDC 0x2004 - MX51_PAD_DI2_PIN3__FEC_MDIO 0x01f5 - MX51_PAD_DI2_PIN4__FEC_CRS 0x0180 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed - MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed - >; - }; - - pinctrl_pmic: pmicgrp { - fsl,pins = < - MX51_PAD_GPIO1_4__GPIO1_4 0x85 - MX51_PAD_GPIO1_8__GPIO1_8 0xe5 - >; - }; - - pinctrl_switch: switchgrp { - fsl,pins = < - MX51_PAD_AUD3_BB_CK__GPIO4_20 0xc5 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX51_PAD_UART1_RXD__UART1_RXD 0x1c5 - MX51_PAD_UART1_TXD__UART1_TXD 0x1c5 - MX51_PAD_UART1_RTS__UART1_RTS 0x1c5 - MX51_PAD_UART1_CTS__UART1_CTS 0x1c5 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX51_PAD_UART2_RXD__UART2_RXD 0x1c5 - MX51_PAD_UART2_TXD__UART2_TXD 0x1c5 - MX51_PAD_USBH1_DATA0__UART2_CTS 0x1c5 - MX51_PAD_USBH1_DATA3__UART2_RTS 0x1c5 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX51_PAD_UART3_RXD__UART3_RXD 0x1c5 - MX51_PAD_UART3_TXD__UART3_TXD 0x1c5 - >; - }; - - pinctrl_usb_mmc_reset: usbmmcgrp { - fsl,pins = < - MX51_PAD_AUD3_BB_RXD__GPIO4_19 0x100 - >; - }; -}; diff --git a/sys/gnu/dts/arm/imx51.dtsi b/sys/gnu/dts/arm/imx51.dtsi deleted file mode 100644 index dea86b98e9c..00000000000 --- a/sys/gnu/dts/arm/imx51.dtsi +++ /dev/null @@ -1,640 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// -// Copyright 2011 Freescale Semiconductor, Inc. -// Copyright 2011 Linaro Ltd. - -#include "imx51-pinfunc.h" -#include -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - /* - * The decompressor and also some bootloaders rely on a - * pre-existing /chosen node to be available to insert the - * command line and merge other ATAGS info. - */ - chosen {}; - - aliases { - ethernet0 = &fec; - gpio0 = &gpio1; - gpio1 = &gpio2; - gpio2 = &gpio3; - gpio3 = &gpio4; - i2c0 = &i2c1; - i2c1 = &i2c2; - mmc0 = &esdhc1; - mmc1 = &esdhc2; - mmc2 = &esdhc3; - mmc3 = &esdhc4; - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - spi0 = &ecspi1; - spi1 = &ecspi2; - spi2 = &cspi; - }; - - tzic: tz-interrupt-controller@e0000000 { - compatible = "fsl,imx51-tzic", "fsl,tzic"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0xe0000000 0x4000>; - }; - - clocks { - ckil { - compatible = "fsl,imx-ckil", "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - - ckih1 { - compatible = "fsl,imx-ckih1", "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - ckih2 { - compatible = "fsl,imx-ckih2", "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - osc { - compatible = "fsl,imx-osc", "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a8"; - reg = <0>; - clock-latency = <62500>; - clocks = <&clks IMX5_CLK_CPU_PODF>; - clock-names = "cpu"; - operating-points = < - 166000 1000000 - 600000 1050000 - 800000 1100000 - >; - voltage-tolerance = <5>; - }; - }; - - pmu: pmu { - compatible = "arm,cortex-a8-pmu"; - interrupt-parent = <&tzic>; - interrupts = <77>; - }; - - usbphy0: usbphy0 { - compatible = "usb-nop-xceiv"; - clocks = <&clks IMX5_CLK_USB_PHY_GATE>; - clock-names = "main_clk"; - #phy-cells = <0>; - }; - - display-subsystem { - compatible = "fsl,imx-display-subsystem"; - ports = <&ipu_di0>, <&ipu_di1>; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&tzic>; - ranges; - - iram: sram@1ffe0000 { - compatible = "mmio-sram"; - reg = <0x1ffe0000 0x20000>; - }; - - gpu: gpu@30000000 { - compatible = "amd,imageon-200.1", "amd,imageon"; - reg = <0x30000000 0x20000>; - reg-names = "kgsl_3d0_reg_memory"; - interrupts = <12>; - interrupt-names = "kgsl_3d0_irq"; - clocks = <&clks IMX5_CLK_GPU3D_GATE>, <&clks IMX5_CLK_GARB_GATE>; - clock-names = "core_clk", "mem_iface_clk"; - }; - - ipu: ipu@40000000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx51-ipu"; - reg = <0x40000000 0x20000000>; - interrupts = <11 10>; - clocks = <&clks IMX5_CLK_IPU_GATE>, - <&clks IMX5_CLK_IPU_DI0_GATE>, - <&clks IMX5_CLK_IPU_DI1_GATE>; - clock-names = "bus", "di0", "di1"; - resets = <&src 2>; - - ipu_di0: port@2 { - reg = <2>; - - ipu_di0_disp1: endpoint { - }; - }; - - ipu_di1: port@3 { - reg = <3>; - - ipu_di1_disp2: endpoint { - }; - }; - }; - - aips@70000000 { /* AIPS1 */ - compatible = "fsl,aips-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x70000000 0x10000000>; - ranges; - - spba@70000000 { - compatible = "fsl,spba-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x70000000 0x40000>; - ranges; - - esdhc1: esdhc@70004000 { - compatible = "fsl,imx51-esdhc"; - reg = <0x70004000 0x4000>; - interrupts = <1>; - clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>, - <&clks IMX5_CLK_DUMMY>, - <&clks IMX5_CLK_ESDHC1_PER_GATE>; - clock-names = "ipg", "ahb", "per"; - status = "disabled"; - }; - - esdhc2: esdhc@70008000 { - compatible = "fsl,imx51-esdhc"; - reg = <0x70008000 0x4000>; - interrupts = <2>; - clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>, - <&clks IMX5_CLK_DUMMY>, - <&clks IMX5_CLK_ESDHC2_PER_GATE>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - status = "disabled"; - }; - - uart3: serial@7000c000 { - compatible = "fsl,imx51-uart", "fsl,imx21-uart"; - reg = <0x7000c000 0x4000>; - interrupts = <33>; - clocks = <&clks IMX5_CLK_UART3_IPG_GATE>, - <&clks IMX5_CLK_UART3_PER_GATE>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - ecspi1: spi@70010000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx51-ecspi"; - reg = <0x70010000 0x4000>; - interrupts = <36>; - clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>, - <&clks IMX5_CLK_ECSPI1_PER_GATE>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - ssi2: ssi@70014000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; - reg = <0x70014000 0x4000>; - interrupts = <30>; - clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>, - <&clks IMX5_CLK_SSI2_ROOT_GATE>; - clock-names = "ipg", "baud"; - dmas = <&sdma 24 1 0>, - <&sdma 25 1 0>; - dma-names = "rx", "tx"; - fsl,fifo-depth = <15>; - status = "disabled"; - }; - - esdhc3: esdhc@70020000 { - compatible = "fsl,imx51-esdhc"; - reg = <0x70020000 0x4000>; - interrupts = <3>; - clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>, - <&clks IMX5_CLK_DUMMY>, - <&clks IMX5_CLK_ESDHC3_PER_GATE>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - status = "disabled"; - }; - - esdhc4: esdhc@70024000 { - compatible = "fsl,imx51-esdhc"; - reg = <0x70024000 0x4000>; - interrupts = <4>; - clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>, - <&clks IMX5_CLK_DUMMY>, - <&clks IMX5_CLK_ESDHC4_PER_GATE>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - status = "disabled"; - }; - }; - - aipstz1: bridge@73f00000 { - compatible = "fsl,imx51-aipstz"; - reg = <0x73f00000 0x60>; - }; - - usbotg: usb@73f80000 { - compatible = "fsl,imx51-usb", "fsl,imx27-usb"; - reg = <0x73f80000 0x0200>; - interrupts = <18>; - clocks = <&clks IMX5_CLK_USBOH3_GATE>; - fsl,usbmisc = <&usbmisc 0>; - fsl,usbphy = <&usbphy0>; - status = "disabled"; - }; - - usbh1: usb@73f80200 { - compatible = "fsl,imx51-usb", "fsl,imx27-usb"; - reg = <0x73f80200 0x0200>; - interrupts = <14>; - clocks = <&clks IMX5_CLK_USBOH3_GATE>; - fsl,usbmisc = <&usbmisc 1>; - dr_mode = "host"; - status = "disabled"; - }; - - usbh2: usb@73f80400 { - compatible = "fsl,imx51-usb", "fsl,imx27-usb"; - reg = <0x73f80400 0x0200>; - interrupts = <16>; - clocks = <&clks IMX5_CLK_USBOH3_GATE>; - fsl,usbmisc = <&usbmisc 2>; - dr_mode = "host"; - status = "disabled"; - }; - - usbh3: usb@73f80600 { - compatible = "fsl,imx51-usb", "fsl,imx27-usb"; - reg = <0x73f80600 0x0200>; - interrupts = <17>; - clocks = <&clks IMX5_CLK_USBOH3_GATE>; - fsl,usbmisc = <&usbmisc 3>; - dr_mode = "host"; - status = "disabled"; - }; - - usbmisc: usbmisc@73f80800 { - #index-cells = <1>; - compatible = "fsl,imx51-usbmisc"; - reg = <0x73f80800 0x200>; - clocks = <&clks IMX5_CLK_USBOH3_GATE>; - }; - - gpio1: gpio@73f84000 { - compatible = "fsl,imx51-gpio", "fsl,imx35-gpio"; - reg = <0x73f84000 0x4000>; - interrupts = <50 51>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@73f88000 { - compatible = "fsl,imx51-gpio", "fsl,imx35-gpio"; - reg = <0x73f88000 0x4000>; - interrupts = <52 53>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio@73f8c000 { - compatible = "fsl,imx51-gpio", "fsl,imx35-gpio"; - reg = <0x73f8c000 0x4000>; - interrupts = <54 55>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio4: gpio@73f90000 { - compatible = "fsl,imx51-gpio", "fsl,imx35-gpio"; - reg = <0x73f90000 0x4000>; - interrupts = <56 57>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - kpp: kpp@73f94000 { - compatible = "fsl,imx51-kpp", "fsl,imx21-kpp"; - reg = <0x73f94000 0x4000>; - interrupts = <60>; - clocks = <&clks IMX5_CLK_DUMMY>; - status = "disabled"; - }; - - wdog1: wdog@73f98000 { - compatible = "fsl,imx51-wdt", "fsl,imx21-wdt"; - reg = <0x73f98000 0x4000>; - interrupts = <58>; - clocks = <&clks IMX5_CLK_DUMMY>; - }; - - wdog2: wdog@73f9c000 { - compatible = "fsl,imx51-wdt", "fsl,imx21-wdt"; - reg = <0x73f9c000 0x4000>; - interrupts = <59>; - clocks = <&clks IMX5_CLK_DUMMY>; - status = "disabled"; - }; - - gpt: timer@73fa0000 { - compatible = "fsl,imx51-gpt", "fsl,imx31-gpt"; - reg = <0x73fa0000 0x4000>; - interrupts = <39>; - clocks = <&clks IMX5_CLK_GPT_IPG_GATE>, - <&clks IMX5_CLK_GPT_HF_GATE>; - clock-names = "ipg", "per"; - }; - - iomuxc: iomuxc@73fa8000 { - compatible = "fsl,imx51-iomuxc"; - reg = <0x73fa8000 0x4000>; - }; - - pwm1: pwm@73fb4000 { - #pwm-cells = <2>; - compatible = "fsl,imx51-pwm", "fsl,imx27-pwm"; - reg = <0x73fb4000 0x4000>; - clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>, - <&clks IMX5_CLK_PWM1_HF_GATE>; - clock-names = "ipg", "per"; - interrupts = <61>; - }; - - pwm2: pwm@73fb8000 { - #pwm-cells = <2>; - compatible = "fsl,imx51-pwm", "fsl,imx27-pwm"; - reg = <0x73fb8000 0x4000>; - clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>, - <&clks IMX5_CLK_PWM2_HF_GATE>; - clock-names = "ipg", "per"; - interrupts = <94>; - }; - - uart1: serial@73fbc000 { - compatible = "fsl,imx51-uart", "fsl,imx21-uart"; - reg = <0x73fbc000 0x4000>; - interrupts = <31>; - clocks = <&clks IMX5_CLK_UART1_IPG_GATE>, - <&clks IMX5_CLK_UART1_PER_GATE>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart2: serial@73fc0000 { - compatible = "fsl,imx51-uart", "fsl,imx21-uart"; - reg = <0x73fc0000 0x4000>; - interrupts = <32>; - clocks = <&clks IMX5_CLK_UART2_IPG_GATE>, - <&clks IMX5_CLK_UART2_PER_GATE>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - src: src@73fd0000 { - compatible = "fsl,imx51-src"; - reg = <0x73fd0000 0x4000>; - #reset-cells = <1>; - }; - - clks: ccm@73fd4000{ - compatible = "fsl,imx51-ccm"; - reg = <0x73fd4000 0x4000>; - interrupts = <0 71 0x04 0 72 0x04>; - #clock-cells = <1>; - }; - }; - - aips@80000000 { /* AIPS2 */ - compatible = "fsl,aips-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x80000000 0x10000000>; - ranges; - - aipstz2: bridge@83f00000 { - compatible = "fsl,imx51-aipstz"; - reg = <0x83f00000 0x60>; - }; - - iim: iim@83f98000 { - compatible = "fsl,imx51-iim", "fsl,imx27-iim"; - reg = <0x83f98000 0x4000>; - interrupts = <69>; - clocks = <&clks IMX5_CLK_IIM_GATE>; - }; - - tigerp: tigerp@83fa0000 { - compatible = "fsl,imx51-tigerp"; - reg = <0x83fa0000 0x28>; - }; - - owire: owire@83fa4000 { - compatible = "fsl,imx51-owire", "fsl,imx21-owire"; - reg = <0x83fa4000 0x4000>; - interrupts = <88>; - clocks = <&clks IMX5_CLK_OWIRE_GATE>; - status = "disabled"; - }; - - ecspi2: spi@83fac000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx51-ecspi"; - reg = <0x83fac000 0x4000>; - interrupts = <37>; - clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>, - <&clks IMX5_CLK_ECSPI2_PER_GATE>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - sdma: sdma@83fb0000 { - compatible = "fsl,imx51-sdma", "fsl,imx35-sdma"; - reg = <0x83fb0000 0x4000>; - interrupts = <6>; - clocks = <&clks IMX5_CLK_SDMA_GATE>, - <&clks IMX5_CLK_AHB>; - clock-names = "ipg", "ahb"; - #dma-cells = <3>; - fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin"; - }; - - cspi: spi@83fc0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx51-cspi", "fsl,imx35-cspi"; - reg = <0x83fc0000 0x4000>; - interrupts = <38>; - clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>, - <&clks IMX5_CLK_CSPI_IPG_GATE>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - i2c2: i2c@83fc4000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx51-i2c", "fsl,imx21-i2c"; - reg = <0x83fc4000 0x4000>; - interrupts = <63>; - clocks = <&clks IMX5_CLK_I2C2_GATE>; - status = "disabled"; - }; - - i2c1: i2c@83fc8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx51-i2c", "fsl,imx21-i2c"; - reg = <0x83fc8000 0x4000>; - interrupts = <62>; - clocks = <&clks IMX5_CLK_I2C1_GATE>; - status = "disabled"; - }; - - ssi1: ssi@83fcc000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; - reg = <0x83fcc000 0x4000>; - interrupts = <29>; - clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>, - <&clks IMX5_CLK_SSI1_ROOT_GATE>; - clock-names = "ipg", "baud"; - dmas = <&sdma 28 0 0>, - <&sdma 29 0 0>; - dma-names = "rx", "tx"; - fsl,fifo-depth = <15>; - status = "disabled"; - }; - - audmux: audmux@83fd0000 { - compatible = "fsl,imx51-audmux", "fsl,imx31-audmux"; - reg = <0x83fd0000 0x4000>; - clocks = <&clks IMX5_CLK_DUMMY>; - clock-names = "audmux"; - status = "disabled"; - }; - - m4if: m4if@83fd8000 { - compatible = "fsl,imx51-m4if"; - reg = <0x83fd8000 0x1000>; - }; - - weim: weim@83fda000 { - #address-cells = <2>; - #size-cells = <1>; - compatible = "fsl,imx51-weim"; - reg = <0x83fda000 0x1000>; - clocks = <&clks IMX5_CLK_EMI_SLOW_GATE>; - ranges = < - 0 0 0xb0000000 0x08000000 - 1 0 0xb8000000 0x08000000 - 2 0 0xc0000000 0x08000000 - 3 0 0xc8000000 0x04000000 - 4 0 0xcc000000 0x02000000 - 5 0 0xce000000 0x02000000 - >; - status = "disabled"; - }; - - nfc: nand@83fdb000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "fsl,imx51-nand"; - reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>; - interrupts = <8>; - clocks = <&clks IMX5_CLK_NFC_GATE>; - status = "disabled"; - }; - - pata: pata@83fe0000 { - compatible = "fsl,imx51-pata", "fsl,imx27-pata"; - reg = <0x83fe0000 0x4000>; - interrupts = <70>; - clocks = <&clks IMX5_CLK_PATA_GATE>; - status = "disabled"; - }; - - ssi3: ssi@83fe8000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; - reg = <0x83fe8000 0x4000>; - interrupts = <96>; - clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>, - <&clks IMX5_CLK_SSI3_ROOT_GATE>; - clock-names = "ipg", "baud"; - dmas = <&sdma 46 0 0>, - <&sdma 47 0 0>; - dma-names = "rx", "tx"; - fsl,fifo-depth = <15>; - status = "disabled"; - }; - - fec: ethernet@83fec000 { - compatible = "fsl,imx51-fec", "fsl,imx27-fec"; - reg = <0x83fec000 0x4000>; - interrupts = <87>; - clocks = <&clks IMX5_CLK_FEC_GATE>, - <&clks IMX5_CLK_FEC_GATE>, - <&clks IMX5_CLK_FEC_GATE>; - clock-names = "ipg", "ahb", "ptp"; - status = "disabled"; - }; - - vpu: vpu@83ff4000 { - compatible = "fsl,imx51-vpu", "cnm,codahx4"; - reg = <0x83ff4000 0x1000>; - interrupts = <9>; - clocks = <&clks IMX5_CLK_VPU_REFERENCE_GATE>, - <&clks IMX5_CLK_VPU_GATE>; - clock-names = "per", "ahb"; - resets = <&src 1>; - iram = <&iram>; - }; - - sahara: crypto@83ff8000 { - compatible = "fsl,imx53-sahara", "fsl,imx51-sahara"; - reg = <0x83ff8000 0x4000>; - interrupts = <19 20>; - clocks = <&clks IMX5_CLK_SAHARA_IPG_GATE>, - <&clks IMX5_CLK_SAHARA_IPG_GATE>; - clock-names = "ipg", "ahb"; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/imx53-ard.dts b/sys/gnu/dts/arm/imx53-ard.dts deleted file mode 100644 index 9a2e1fde712..00000000000 --- a/sys/gnu/dts/arm/imx53-ard.dts +++ /dev/null @@ -1,179 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2011 Freescale Semiconductor, Inc. - * Copyright 2011 Linaro Ltd. - */ - -/dts-v1/; -#include -#include "imx53.dtsi" - -/ { - model = "Freescale i.MX53 Automotive Reference Design Board"; - compatible = "fsl,imx53-ard", "fsl,imx53"; - - memory@70000000 { - device_type = "memory"; - reg = <0x70000000 0x40000000>; - }; - - eim-cs1@f4000000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "fsl,eim-bus", "simple-bus"; - reg = <0xf4000000 0x3ff0000>; - ranges; - - lan9220@f4000000 { - compatible = "smsc,lan9220", "smsc,lan9115"; - reg = <0xf4000000 0x2000000>; - phy-mode = "mii"; - interrupt-parent = <&gpio2>; - interrupts = <31 0x8>; - reg-io-width = <4>; - /* - * VDD33A and VDDVARIO of LAN9220 are supplied by - * SW4_3V3 of LTC3589. Before the regulator driver - * for this PMIC is available, we use a fixed dummy - * 3V3 regulator to get LAN9220 driver probing work. - */ - vdd33a-supply = <®_3p3v>; - vddvario-supply = <®_3p3v>; - smsc,irq-push-pull; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_3p3v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - home { - label = "Home"; - gpios = <&gpio5 10 0>; - linux,code = ; - wakeup-source; - }; - - back { - label = "Back"; - gpios = <&gpio5 11 0>; - linux,code = ; - wakeup-source; - }; - - program { - label = "Program"; - gpios = <&gpio5 12 0>; - linux,code = ; - wakeup-source; - }; - - volume-up { - label = "Volume Up"; - gpios = <&gpio5 13 0>; - linux,code = ; - }; - - volume-down { - label = "Volume Down"; - gpios = <&gpio4 0 0>; - linux,code = ; - }; - }; -}; - -&esdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc1>; - cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - imx53-ard { - pinctrl_hog: hoggrp { - fsl,pins = < - MX53_PAD_GPIO_1__GPIO1_1 0x80000000 - MX53_PAD_GPIO_9__GPIO1_9 0x80000000 - MX53_PAD_EIM_EB3__GPIO2_31 0x80000000 - MX53_PAD_GPIO_10__GPIO4_0 0x80000000 - MX53_PAD_DISP0_DAT16__GPIO5_10 0x80000000 - MX53_PAD_DISP0_DAT17__GPIO5_11 0x80000000 - MX53_PAD_DISP0_DAT18__GPIO5_12 0x80000000 - MX53_PAD_DISP0_DAT19__GPIO5_13 0x80000000 - MX53_PAD_EIM_D16__EMI_WEIM_D_16 0x80000000 - MX53_PAD_EIM_D17__EMI_WEIM_D_17 0x80000000 - MX53_PAD_EIM_D18__EMI_WEIM_D_18 0x80000000 - MX53_PAD_EIM_D19__EMI_WEIM_D_19 0x80000000 - MX53_PAD_EIM_D20__EMI_WEIM_D_20 0x80000000 - MX53_PAD_EIM_D21__EMI_WEIM_D_21 0x80000000 - MX53_PAD_EIM_D22__EMI_WEIM_D_22 0x80000000 - MX53_PAD_EIM_D23__EMI_WEIM_D_23 0x80000000 - MX53_PAD_EIM_D24__EMI_WEIM_D_24 0x80000000 - MX53_PAD_EIM_D25__EMI_WEIM_D_25 0x80000000 - MX53_PAD_EIM_D26__EMI_WEIM_D_26 0x80000000 - MX53_PAD_EIM_D27__EMI_WEIM_D_27 0x80000000 - MX53_PAD_EIM_D28__EMI_WEIM_D_28 0x80000000 - MX53_PAD_EIM_D29__EMI_WEIM_D_29 0x80000000 - MX53_PAD_EIM_D30__EMI_WEIM_D_30 0x80000000 - MX53_PAD_EIM_D31__EMI_WEIM_D_31 0x80000000 - MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 0x80000000 - MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 0x80000000 - MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 0x80000000 - MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 0x80000000 - MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 0x80000000 - MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 0x80000000 - MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 0x80000000 - MX53_PAD_EIM_OE__EMI_WEIM_OE 0x80000000 - MX53_PAD_EIM_RW__EMI_WEIM_RW 0x80000000 - MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 0x80000000 - >; - }; - - pinctrl_esdhc1: esdhc1grp { - fsl,pins = < - MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 - MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 - MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 - MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 - MX53_PAD_PATA_DATA8__ESDHC1_DAT4 0x1d5 - MX53_PAD_PATA_DATA9__ESDHC1_DAT5 0x1d5 - MX53_PAD_PATA_DATA10__ESDHC1_DAT6 0x1d5 - MX53_PAD_PATA_DATA11__ESDHC1_DAT7 0x1d5 - MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 - MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4 - MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4 - >; - }; - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx53-cx9020.dts b/sys/gnu/dts/arm/imx53-cx9020.dts deleted file mode 100644 index 0a475c23405..00000000000 --- a/sys/gnu/dts/arm/imx53-cx9020.dts +++ /dev/null @@ -1,292 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2017 Beckhoff Automation GmbH & Co. KG - * based on imx53-qsb.dts - */ - -/dts-v1/; -#include "imx53.dtsi" - -/ { - model = "Beckhoff CX9020 Embedded PC"; - compatible = "bhf,cx9020", "fsl,imx53"; - - chosen { - stdout-path = &uart2; - }; - - memory@70000000 { - device_type = "memory"; - reg = <0x70000000 0x20000000>, - <0xb0000000 0x20000000>; - }; - - display-0 { - #address-cells =<1>; - #size-cells = <0>; - compatible = "fsl,imx-parallel-display"; - interface-pix-fmt = "rgb24"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu_disp0>; - - port@0 { - reg = <0>; - - display0_in: endpoint { - remote-endpoint = <&ipu_di0_disp0>; - }; - }; - - port@1 { - reg = <1>; - - display0_out: endpoint { - remote-endpoint = <&tfp410_in>; - }; - }; - }; - - dvi-connector { - compatible = "dvi-connector"; - ddc-i2c-bus = <&i2c2>; - digital; - - port { - dvi_connector_in: endpoint { - remote-endpoint = <&tfp410_out>; - }; - }; - }; - - dvi-converter { - #address-cells = <1>; - #size-cells = <0>; - compatible = "ti,tfp410"; - - port@0 { - reg = <0>; - - tfp410_in: endpoint { - remote-endpoint = <&display0_out>; - }; - }; - - port@1 { - reg = <1>; - - tfp410_out: endpoint { - remote-endpoint = <&dvi_connector_in>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - pwr-r { - gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - pwr-g { - gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - pwr-b { - gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - sd1-b { - linux,default-trigger = "mmc0"; - gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>; - }; - - sd2-b { - linux,default-trigger = "mmc1"; - gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>; - }; - }; - - regulator-3p2v { - compatible = "regulator-fixed"; - regulator-name = "3P2V"; - regulator-min-microvolt = <3200000>; - regulator-max-microvolt = <3200000>; - regulator-always-on; - }; - - reg_usb_vbus: regulator-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio7 8 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&esdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc1>; - cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; - bus-width = <4>; - status = "okay"; -}; - -&esdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc2>; - cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - bus-width = <4>; - status = "okay"; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec>; - phy-mode = "rmii"; - phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&ipu_di0_disp0 { - remote-endpoint = <&display0_in>; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - fsl,dte-mode; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usb_vbus>; - phy_type = "utmi"; - status = "okay"; -}; - -&usbotg { - dr_mode = "peripheral"; - status = "okay"; -}; - -&vpu { - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_hog: hoggrp { - fsl,pins = < - MX53_PAD_GPIO_0__CCM_CLKO 0x1c4 - MX53_PAD_GPIO_16__I2C3_SDA 0x1c4 - MX53_PAD_EIM_D22__GPIO3_22 0x1c4 - MX53_PAD_EIM_D23__GPIO3_23 0x1e4 - MX53_PAD_EIM_D24__GPIO3_24 0x1e4 - >; - }; - - pinctrl_esdhc1: esdhc1grp { - fsl,pins = < - MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 - MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 - MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 - MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 - MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 - MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5 - MX53_PAD_GPIO_1__ESDHC1_CD 0x1c4 - MX53_PAD_EIM_D17__GPIO3_17 0x1e4 - MX53_PAD_GPIO_3__GPIO1_3 0x1c4 - >; - }; - - pinctrl_esdhc2: esdhc2grp { - fsl,pins = < - MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5 - MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5 - MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5 - MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5 - MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5 - MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5 - MX53_PAD_GPIO_4__ESDHC2_CD 0x1e4 - MX53_PAD_EIM_D20__GPIO3_20 0x1e4 - MX53_PAD_GPIO_8__GPIO1_8 0x1c4 - >; - }; - - pinctrl_fec: fecgrp { - fsl,pins = < - MX53_PAD_FEC_MDC__FEC_MDC 0x4 - MX53_PAD_FEC_MDIO__FEC_MDIO 0x1fc - MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x180 - MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x180 - MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x180 - MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x180 - MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x180 - MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x4 - MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x4 - MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x4 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000 - MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000 - >; - }; - - pinctrl_ipu_disp0: ipudisp0grp { - fsl,pins = < - MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x5 - MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 0x5 - MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 0x5 - MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 0x5 - MX53_PAD_DI0_PIN4__IPU_DI0_PIN4 0x5 - MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 0x5 - MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 0x5 - MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 0x5 - MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 0x5 - MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 0x5 - MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 0x5 - MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 0x5 - MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 0x5 - MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 0x5 - MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 0x5 - MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 0x5 - MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 0x5 - MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 0x5 - MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 0x5 - MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 0x5 - MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 0x5 - MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 0x5 - MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 0x5 - MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 0x5 - MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 0x5 - MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 0x5 - MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 0x5 - MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 0x5 - MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 0x5 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX53_PAD_EIM_D26__UART2_RXD_MUX 0x1e4 - MX53_PAD_EIM_D27__UART2_TXD_MUX 0x1e4 - MX53_PAD_EIM_D28__UART2_RTS 0x1e4 - MX53_PAD_EIM_D29__UART2_CTS 0x1e4 - >; - }; -}; diff --git a/sys/gnu/dts/arm/imx53-kp-ddc.dts b/sys/gnu/dts/arm/imx53-kp-ddc.dts deleted file mode 100644 index 0e7f071fd10..00000000000 --- a/sys/gnu/dts/arm/imx53-kp-ddc.dts +++ /dev/null @@ -1,146 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2018 - * Lukasz Majewski, DENX Software Engineering, lukma@denx.de - */ - -/dts-v1/; -#include "imx53-kp.dtsi" - -/ { - model = "K+P imx53 DDC"; - compatible = "kiebackpeter,imx53-ddc", "fsl,imx53"; - - backlight_lcd: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm2 0 50000>; - power-supply = <®_backlight>; - brightness-levels = <0 24 28 32 36 - 40 44 48 52 56 - 60 64 68 72 76 - 80 84 88 92 96 100>; - default-brightness-level = <20>; - }; - - lcd_display: display { - compatible = "fsl,imx-parallel-display"; - #address-cells = <1>; - #size-cells = <0>; - interface-pix-fmt = "rgb24"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_disp>; - - port@0 { - reg = <0>; - - display1_in: endpoint { - remote-endpoint = <&ipu_di1_disp1>; - }; - }; - - port@1 { - reg = <1>; - - lcd_display_out: endpoint { - remote-endpoint = <&lcd_panel_in>; - }; - }; - }; - - lcd_panel: lcd-panel { - compatible = "koe,tx14d24vm1bpa"; - backlight = <&backlight_lcd>; - power-supply = <®_3v3>; - - port { - lcd_panel_in: endpoint { - remote-endpoint = <&lcd_display_out>; - }; - }; - }; - - reg_backlight: regulator-backlight { - compatible = "regulator-fixed"; - regulator-name = "backlight-supply"; - regulator-min-microvolt = <15000000>; - regulator-max-microvolt = <15000000>; - regulator-always-on; - }; -}; - -&fec { - status = "okay"; -}; - -&i2c3 { - adc@48 { - compatible = "ti,ads1015"; - reg = <0x48>; - #address-cells = <1>; - #size-cells = <0>; - - channel@4 { - reg = <4>; - ti,gain = <2>; - ti,datarate = <4>; - }; - - channel@6 { - reg = <6>; - ti,gain = <2>; - ti,datarate = <4>; - }; - }; - - gpio-expander2@21 { - compatible = "nxp,pcf8574"; - reg = <0x21>; - interrupts = <109>; - #gpio-cells = <2>; - gpio-controller; - }; -}; - -&iomuxc { - imx53-kp-ddc { - pinctrl_disp: dispgrp { - fsl,pins = < - MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x4 - MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x4 - MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x4 - MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x4 - MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x4 - MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x4 - MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x4 - MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x4 - MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x4 - MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x4 - MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x4 - MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x4 - MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x4 - MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x4 - MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x4 - MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x4 - MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x4 - MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x4 - MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x4 - MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x4 - MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x4 - MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x4 - MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x4 - MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x4 - MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x4 - MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x4 - MX53_PAD_GPIO_1__PWM2_PWMO 0x4 - >; - }; - }; -}; - -&ipu_di1_disp1 { - remote-endpoint = <&display1_in>; -}; - -&pmic { - fsl,mc13xxx-uses-touch; -}; diff --git a/sys/gnu/dts/arm/imx53-kp-hsc.dts b/sys/gnu/dts/arm/imx53-kp-hsc.dts deleted file mode 100644 index 6e3d71baac0..00000000000 --- a/sys/gnu/dts/arm/imx53-kp-hsc.dts +++ /dev/null @@ -1,52 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2018 - * Lukasz Majewski, DENX Software Engineering, lukma@denx.de - */ - -/dts-v1/; -#include "imx53-kp.dtsi" - -/ { - model = "K+P imx53 HSC"; - compatible = "kiebackpeter,imx53-hsc", "fsl,imx53"; -}; - -&fec { - status = "okay"; - - fixed-link { /* RMII fixed link to LAN9303 */ - speed = <100>; - full-duplex; - }; -}; - -&i2c3 { - switch: switch@a { - compatible = "smsc,lan9303-i2c"; - reg = <0xa>; - reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>; - reset-duration = <400>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { /* RMII fixed link to master */ - reg = <0>; - label = "cpu"; - ethernet = <&fec>; - }; - - port@1 { /* external port 1 */ - reg = <1>; - label = "lan1"; - }; - - port@2 { /* external port 2 */ - reg = <2>; - label = "lan2"; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/imx53-kp.dtsi b/sys/gnu/dts/arm/imx53-kp.dtsi deleted file mode 100644 index 8b25416a530..00000000000 --- a/sys/gnu/dts/arm/imx53-kp.dtsi +++ /dev/null @@ -1,189 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2018 - * Lukasz Majewski, DENX Software Engineering, lukma@denx.de - */ - -/dts-v1/; -#include "imx53-tqma53.dtsi" -#include - -/ { - buzzer { - compatible = "pwm-beeper"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_buzzer>; - pwms = <&pwm1 0 500000>; - }; - - gpio-buttons { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpiobuttons>; - - button-kalt { - label = "Kaltstart"; - linux,code = ; - gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>; - }; - - button-pwr { - label = "PowerFailInterrupt"; - linux,code = ; - gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_leds>; - - led-bus { - label = "bus"; - gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "gpio"; - default-state = "off"; - }; - - led-error { - label = "error"; - gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "gpio"; - default-state = "off"; - }; - - led-flash { - label = "flash"; - gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - reg_3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; -}; - -&can1 { - status = "okay"; -}; - -&can2 { - status = "okay"; -}; - -&i2c3 { - status = "okay"; - - gpio-expander1@22 { - compatible = "nxp,pcf8574"; - reg = <0x22>; - interrupts = <109>; - #gpio-cells = <2>; - gpio-controller; - }; - - rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_kp_common>; - - imx53-kp-common { - pinctrl_buzzer: buzzergrp { - fsl,pins = < - MX53_PAD_SD1_DATA3__PWM1_PWMO 0x1e4 - >; - }; - - pinctrl_gpiobuttons: gpiobuttonsgrp { - fsl,pins = < - MX53_PAD_EIM_RW__GPIO2_26 0x1e4 - MX53_PAD_EIM_D22__GPIO3_22 0x1e4 - >; - }; - - pinctrl_kp_common: kpcommongrp { - fsl,pins = < - MX53_PAD_EIM_CS0__GPIO2_23 0x1e4 - MX53_PAD_GPIO_19__GPIO4_5 0x1e4 - MX53_PAD_PATA_DATA6__GPIO2_6 0x1e4 - MX53_PAD_PATA_DATA7__GPIO2_7 0xe0 - MX53_PAD_CSI0_DAT14__GPIO6_0 0x1e4 - MX53_PAD_CSI0_DAT16__GPIO6_2 0x1e4 - MX53_PAD_CSI0_DAT18__GPIO6_4 0x1e4 - MX53_PAD_EIM_D17__GPIO3_17 0x1e4 - MX53_PAD_EIM_D18__GPIO3_18 0x1e4 - MX53_PAD_EIM_D21__GPIO3_21 0x1e4 - MX53_PAD_EIM_D29__GPIO3_29 0x1e4 - MX53_PAD_EIM_DA11__GPIO3_11 0x1e4 - MX53_PAD_EIM_DA13__GPIO3_13 0x1e4 - MX53_PAD_EIM_DA14__GPIO3_14 0x1e4 - MX53_PAD_SD1_DATA0__GPIO1_16 0x1e4 - MX53_PAD_SD1_CMD__GPIO1_18 0x1e4 - MX53_PAD_SD1_CLK__GPIO1_20 0x1e4 - >; - }; - - pinctrl_leds: ledgrp { - fsl,pins = < - MX53_PAD_EIM_EB2__GPIO2_30 0x1d4 - MX53_PAD_EIM_D28__GPIO3_28 0x1d4 - MX53_PAD_EIM_WAIT__GPIO5_0 0x1d4 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX53_PAD_CSI0_DAT12__UART4_TXD_MUX 0x1e4 - MX53_PAD_CSI0_DAT13__UART4_RXD_MUX 0x1e4 - >; - }; - }; -}; - -&pinctrl_uart1 { - fsl,pins = < - MX53_PAD_EIM_D23__GPIO3_23 0x1e4 - MX53_PAD_EIM_EB3__GPIO2_31 0x1e4 - MX53_PAD_EIM_D24__GPIO3_24 0x1e4 - MX53_PAD_EIM_D25__GPIO3_25 0x1e4 - MX53_PAD_EIM_D19__GPIO3_19 0x1e4 - MX53_PAD_EIM_D20__GPIO3_20 0x1e4 - >; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -&usbh1 { - status = "okay"; -}; - -&usbphy0 { - status = "disabled"; -}; diff --git a/sys/gnu/dts/arm/imx53-m53.dtsi b/sys/gnu/dts/arm/imx53-m53.dtsi deleted file mode 100644 index fe5e0d308e9..00000000000 --- a/sys/gnu/dts/arm/imx53-m53.dtsi +++ /dev/null @@ -1,132 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (C) 2014 Marek Vasut - */ - -#include "imx53.dtsi" - -/ { - model = "Aries/DENX M53"; - compatible = "aries,imx53-m53", "denx,imx53-m53", "fsl,imx53"; - - memory@70000000 { - device_type = "memory"; - reg = <0x70000000 0x20000000>, - <0xb0000000 0x20000000>; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_3p2v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "3P2V"; - regulator-min-microvolt = <3200000>; - regulator-max-microvolt = <3200000>; - regulator-always-on; - }; - - reg_backlight: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "lcd-supply"; - regulator-min-microvolt = <3200000>; - regulator-max-microvolt = <3200000>; - regulator-always-on; - }; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - clock-frequency = <400000>; - status = "okay"; - - touchscreen@41 { - compatible = "st,stmpe610"; - reg = <0x41>; - id = <0>; - blocks = <0x5>; - interrupts = <6 0x0>; - interrupt-parent = <&gpio7>; - irq-trigger = <0x1>; - - stmpe_touchscreen { - compatible = "st,stmpe-ts"; - st,sample-time = <4>; - st,mod-12b = <1>; - st,ref-sel = <0>; - st,adc-freq = <1>; - st,ave-ctrl = <3>; - st,touch-det-delay = <3>; - st,settling = <4>; - st,fraction-z = <7>; - st,i-drive = <1>; - }; - }; - - eeprom: eeprom@50 { - compatible = "atmel,24c128"; - reg = <0x50>; - pagesize = <32>; - }; - - rtc: rtc@68 { - compatible = "st,m41t62"; - reg = <0x68>; - }; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - imx53-m53evk { - pinctrl_hog: hoggrp { - fsl,pins = < - MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000 - MX53_PAD_EIM_EB3__GPIO2_31 0x80000000 - MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX53_PAD_EIM_D16__I2C2_SDA 0xc0000000 - MX53_PAD_EIM_EB2__I2C2_SCL 0xc0000000 - >; - }; - - pinctrl_nand: nandgrp { - fsl,pins = < - MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 0x4 - MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 0x4 - MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 0x4 - MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 0x4 - MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 0xe0 - MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 0xe0 - MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 0x4 - MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 0xa4 - MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 0xa4 - MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 0xa4 - MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 0xa4 - MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 0xa4 - MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 0xa4 - MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 0xa4 - MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 0xa4 - >; - }; - }; -}; - -&nfc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nand>; - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx53-m53evk.dts b/sys/gnu/dts/arm/imx53-m53evk.dts deleted file mode 100644 index daab56abe94..00000000000 --- a/sys/gnu/dts/arm/imx53-m53evk.dts +++ /dev/null @@ -1,370 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (C) 2013 Marek Vasut - */ - -/dts-v1/; -#include "imx53-m53.dtsi" - -/ { - model = "Aries/DENX M53EVK"; - compatible = "aries,imx53-m53evk", "denx,imx53-m53evk", "fsl,imx53"; - - display1: disp1 { - compatible = "fsl,imx-parallel-display"; - interface-pix-fmt = "bgr666"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu_disp1>; - - display-timings { - 800x480p60 { - native-mode; - clock-frequency = <31500000>; - hactive = <800>; - vactive = <480>; - hfront-porch = <40>; - hback-porch = <88>; - hsync-len = <128>; - vback-porch = <33>; - vfront-porch = <9>; - vsync-len = <3>; - vsync-active = <1>; - }; - }; - - port { - display1_in: endpoint { - remote-endpoint = <&ipu_di1_disp1>; - }; - }; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 3000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - power-supply = <®_backlight>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pin_gpio>; - - user1 { - label = "user1"; - gpios = <&gpio2 8 0>; - linux,default-trigger = "heartbeat"; - }; - - user2 { - label = "user2"; - gpios = <&gpio2 9 0>; - linux,default-trigger = "heartbeat"; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_usbh1_vbus: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 2 0>; - }; - - reg_usb_otg_vbus: regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 4 0>; - }; - }; - - sound { - compatible = "fsl,imx53-m53evk-sgtl5000", - "fsl,imx-audio-sgtl5000"; - model = "imx53-m53evk-sgtl5000"; - ssi-controller = <&ssi2>; - audio-codec = <&sgtl5000>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "LINE_IN", "Line In Jack", - "Headphone Jack", "HP_OUT", - "Ext Spk", "LINE_OUT"; - mux-int-port = <2>; - mux-ext-port = <4>; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can1>; - status = "okay"; -}; - -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can2>; - status = "okay"; -}; - -&esdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc1>; - cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec>; - phy-mode = "rmii"; - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - sgtl5000: codec@a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - #sound-dai-cells = <0>; - VDDA-supply = <®_3p2v>; - VDDIO-supply = <®_3p2v>; - clocks = <&clks IMX5_CLK_SSI_EXT1_GATE>; - }; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - imx53-m53evk { - pinctrl_usb: usbgrp { - fsl,pins = < - MX53_PAD_GPIO_2__GPIO1_2 0x80000000 - MX53_PAD_GPIO_3__USBOH3_USBH1_OC 0x80000000 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX53_PAD_GPIO_4__GPIO1_4 0x000b0 - >; - }; - - led_pin_gpio: led_gpio { - fsl,pins = < - MX53_PAD_PATA_DATA8__GPIO2_8 0x80000000 - MX53_PAD_PATA_DATA9__GPIO2_9 0x80000000 - >; - }; - - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC 0x80000000 - MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD 0x80000000 - MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS 0x80000000 - MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD 0x80000000 - >; - }; - - pinctrl_can1: can1grp { - fsl,pins = < - MX53_PAD_GPIO_7__CAN1_TXCAN 0x80000000 - MX53_PAD_GPIO_8__CAN1_RXCAN 0x80000000 - >; - }; - - pinctrl_can2: can2grp { - fsl,pins = < - MX53_PAD_KEY_COL4__CAN2_TXCAN 0x80000000 - MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x80000000 - >; - }; - - pinctrl_esdhc1: esdhc1grp { - fsl,pins = < - MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 - MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 - MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 - MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 - MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 - MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5 - >; - }; - - pinctrl_fec: fecgrp { - fsl,pins = < - MX53_PAD_FEC_MDC__FEC_MDC 0x80000000 - MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000 - MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000 - MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000 - MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000 - MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000 - MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000 - MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 - MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000 - MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX53_PAD_EIM_D21__I2C1_SCL 0xc0000000 - MX53_PAD_EIM_D28__I2C1_SDA 0xc0000000 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000 - MX53_PAD_GPIO_5__I2C3_SCL 0xc0000000 - >; - }; - - pinctrl_ipu_disp1: ipudisp1grp { - fsl,pins = < - MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x5 - MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x5 - MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x5 - MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x5 - MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x5 - MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x5 - MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x5 - MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x5 - MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x5 - MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x5 - MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x5 - MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x5 - MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x5 - MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x5 - MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x5 - MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x5 - MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x5 - MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x5 - MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x5 - MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x5 - MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x5 - MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x5 - MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x5 - MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x5 - MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x5 - MX53_PAD_EIM_DA13__IPU_DI1_D0_CS 0x5 - MX53_PAD_EIM_DA14__IPU_DI1_D1_CS 0x5 - MX53_PAD_EIM_DA15__IPU_DI1_PIN1 0x5 - MX53_PAD_EIM_DA11__IPU_DI1_PIN2 0x5 - MX53_PAD_EIM_DA12__IPU_DI1_PIN3 0x5 - MX53_PAD_EIM_A25__IPU_DI1_PIN12 0x5 - MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x5 - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX53_PAD_DISP0_DAT8__PWM1_PWMO 0x5 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4 - MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4 - MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4 - MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4 - MX53_PAD_PATA_DA_1__UART3_CTS 0x1e4 - MX53_PAD_PATA_DA_2__UART3_RTS 0x1e4 - >; - }; - }; -}; - -&ipu_di1_disp1 { - remote-endpoint = <&display1_in>; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "okay"; -}; - -&sata { - status = "okay"; -}; - -&ssi2 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -&usbh1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb>; - vbus-supply = <®_usbh1_vbus>; - phy_type = "utmi"; - status = "okay"; -}; - -&usbotg { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - dr_mode = "otg"; - vbus-supply = <®_usb_otg_vbus>; - disable-over-current; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx53-m53menlo.dts b/sys/gnu/dts/arm/imx53-m53menlo.dts deleted file mode 100644 index 719ed5ca454..00000000000 --- a/sys/gnu/dts/arm/imx53-m53menlo.dts +++ /dev/null @@ -1,492 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2019 Marek Vasut - */ - -/dts-v1/; -#include "imx53-m53.dtsi" - -/ { - model = "MENLO M53 EMBEDDED DEVICE"; - compatible = "menlo,m53menlo", "fsl,imx53"; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-0 = <&pinctrl_power_button>; - pinctrl-names = "default"; - - power-button { - label = "Power button"; - gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - gpio-poweroff { - compatible = "gpio-poweroff"; - pinctrl-0 = <&pinctrl_power_out>; - pinctrl-names = "default"; - gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_led>; - - user1 { - label = "TestLed601"; - gpios = <&gpio6 1 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc0"; - }; - - user2 { - label = "TestLed602"; - gpios = <&gpio6 2 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - - eth { - label = "EthLedYe"; - gpios = <&gpio2 11 GPIO_ACTIVE_LOW>; - linux,default-trigger = "netdev"; - }; - }; - - panel { - compatible = "edt,etm0700g0dh6"; - pinctrl-0 = <&pinctrl_display_gpio>; - enable-gpios = <&gpio6 0 GPIO_ACTIVE_HIGH>; - - port { - panel_in: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - }; - - beeper { - compatible = "gpio-beeper"; - pinctrl-0 = <&pinctrl_beeper>; - gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>; - }; - - reg_usbh1_vbus: regulator-usbh1-vbus { - compatible = "regulator-fixed"; - regulator-name = "vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can1>; - status = "okay"; -}; - -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can2>; - status = "okay"; -}; - -&clks { - assigned-clocks = <&clks IMX5_CLK_CKO1_SEL>, - <&clks IMX5_CLK_CKO1_PODF>, - <&clks IMX5_CLK_CKO1>; - assigned-clock-parents = <&clks IMX5_CLK_AHB>; - assigned-clock-rates = <133333334>, <33333334>, <33333334>; -}; - -&ecspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi2>; - cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>, <&gpio2 27 GPIO_ACTIVE_HIGH>; - status = "okay"; - - spidev@0 { - compatible = "menlo,m53cpld"; - spi-max-frequency = <25000000>; - reg = <0>; - }; - - spidev@1 { - compatible = "menlo,m53cpld"; - spi-max-frequency = <25000000>; - reg = <1>; - }; -}; - -&esdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc1>; - cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec>; - phy-mode = "rmii"; - phy-reset-gpios = <&gpio7 7 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&gpio1 { - gpio-line-names = - "", "", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", ""; -}; - -&gpio2 { - gpio-line-names = - "", "", "", "", - "", "", "", "", - "TestPin_SV2_3", "", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", ""; -}; - -&gpio3 { - gpio-line-names = - "", "", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", "", - "CPLD_JTAG_TDI", "CPLD_JTAG_TMS", "", "", - "", "CPLD_JTAG_TDO", "", ""; -}; - -&gpio5 { - gpio-line-names = - "", "", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", "", - "", "", "CPLD_JTAG_TCK", "KBD_intK", - "CPLD_int", "CPLD_JTAG_internal", "CPLD_D[0]", "CPLD_D[1]", - "CPLD_D[2]", "CPLD_D[3]", "CPLD_D[4]", "CPLD_D[5]", - "CPLD_D[6]", "CPLD_D[7]", "DISP_reset", "KBD_intI"; -}; - -&gpio6 { - gpio-line-names = - "", "", "", "", - "CPLD_reset", "", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", ""; -}; - -&gpio7 { - gpio-line-names = - "", "", "", "", - "", "", "", "", - "", "", "", "", - "", "USB-OTG_OverCurrent", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", ""; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - touchscreen@38 { - compatible = "edt,edt-ft5x06"; - reg = <0x38>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_edt_ft5x06>; - interrupt-parent = <&gpio6>; - interrupts = <5 IRQ_TYPE_EDGE_FALLING>; - reset-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>; - wake-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; - }; - - eeprom@50 { - compatible = "atmel,24c64"; - reg = <0x50>; - pagesize = <32>; - }; - - dac@60 { - compatible = "microchip,mcp4725"; - reg = <0x60>; - }; -}; - -&i2c2 { - touchscreen@41 { - status = "disabled"; - }; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - imx53-m53evk { - hoggrp { - fsl,pins = < - MX53_PAD_GPIO_19__CCM_CLKO 0x1e4 - MX53_PAD_CSI0_DATA_EN__GPIO5_20 0x1e4 - MX53_PAD_CSI0_DAT4__GPIO5_22 0x1e4 - MX53_PAD_CSI0_DAT5__GPIO5_23 0x1c4 - MX53_PAD_CSI0_DAT6__GPIO5_24 0x1e4 - MX53_PAD_CSI0_DAT7__GPIO5_25 0x1e4 - MX53_PAD_CSI0_DAT8__GPIO5_26 0x1e4 - MX53_PAD_CSI0_DAT9__GPIO5_27 0x1c4 - MX53_PAD_CSI0_DAT10__GPIO5_28 0x1e4 - MX53_PAD_CSI0_DAT11__GPIO5_29 0x1e4 - MX53_PAD_PATA_DATA11__GPIO2_11 0x1e4 - MX53_PAD_EIM_D24__GPIO3_24 0x1e4 - MX53_PAD_EIM_D25__GPIO3_25 0x1e4 - MX53_PAD_EIM_D29__GPIO3_29 0x1e4 - MX53_PAD_CSI0_PIXCLK__GPIO5_18 0x1e4 - MX53_PAD_CSI0_VSYNC__GPIO5_21 0x1e4 - MX53_PAD_CSI0_DAT18__GPIO6_4 0x1c4 - MX53_PAD_PATA_DATA8__GPIO2_8 0x1e4 - >; - }; - - pinctrl_led: ledgrp { - fsl,pins = < - MX53_PAD_CSI0_DAT15__GPIO6_1 0x1c4 - MX53_PAD_CSI0_DAT16__GPIO6_2 0x1c4 - >; - }; - - pinctrl_beeper: beepergrp { - fsl,pins = < - MX53_PAD_CSI0_DAT17__GPIO6_3 0x1c4 - >; - }; - - pinctrl_can1: can1grp { - fsl,pins = < - MX53_PAD_GPIO_7__CAN1_TXCAN 0x1c4 - MX53_PAD_GPIO_8__CAN1_RXCAN 0x1c4 - >; - }; - - pinctrl_can2: can2grp { - fsl,pins = < - MX53_PAD_KEY_COL4__CAN2_TXCAN 0x1e4 - MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x1c4 - >; - }; - - pinctrl_display_gpio: display-gpiogrp { - fsl,pins = < - MX53_PAD_CSI0_DAT12__GPIO5_30 0x1c4 /* Reset */ - MX53_PAD_CSI0_MCLK__GPIO5_19 0x1e4 /* Int-K */ - MX53_PAD_CSI0_DAT13__GPIO5_31 0x1c4 /* Int-I */ - - MX53_PAD_CSI0_DAT14__GPIO6_0 0x1c4 /* Power down */ - >; - }; - - pinctrl_edt_ft5x06: edt-ft5x06grp { - fsl,pins = < - MX53_PAD_PATA_DATA9__GPIO2_9 0x1e4 /* Reset */ - MX53_PAD_CSI0_DAT19__GPIO6_5 0x1c4 /* Interrupt */ - MX53_PAD_PATA_DATA10__GPIO2_10 0x1e4 /* Wake */ - >; - }; - - pinctrl_ecspi2: ecspi2grp { - fsl,pins = < - MX53_PAD_EIM_CS0__ECSPI2_SCLK 0xe4 - MX53_PAD_EIM_OE__ECSPI2_MISO 0xe4 - MX53_PAD_EIM_CS1__ECSPI2_MOSI 0xe4 - MX53_PAD_EIM_RW__GPIO2_26 0xe4 - MX53_PAD_EIM_LBA__GPIO2_27 0xe4 - >; - }; - - pinctrl_esdhc1: esdhc1grp { - fsl,pins = < - MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1e4 - MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1e4 - MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1e4 - MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1e4 - MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1e4 - MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1e4 - MX53_PAD_GPIO_1__GPIO1_1 0x1c4 - MX53_PAD_GPIO_9__GPIO1_9 0x1e4 - >; - }; - - pinctrl_fec: fecgrp { - fsl,pins = < - MX53_PAD_FEC_MDC__FEC_MDC 0x1e4 - MX53_PAD_FEC_MDIO__FEC_MDIO 0x1e4 - MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x1e4 - MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x1e4 - MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x1e4 - MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x1e4 - MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x1e4 - MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x1c4 - MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x1e4 - MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x1e4 - MX53_PAD_PATA_DA_1__GPIO7_7 0x1e4 - MX53_PAD_EIM_EB3__GPIO2_31 0x1e4 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX53_PAD_EIM_D21__I2C1_SCL 0x400001e4 - MX53_PAD_EIM_D28__I2C1_SDA 0x400001e4 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX53_PAD_GPIO_6__I2C3_SDA 0x400001e4 - MX53_PAD_GPIO_5__I2C3_SCL 0x400001e4 - >; - }; - - pinctrl_lvds0: lvds0grp { - /* LVDS pins only have pin mux configuration */ - fsl,pins = < - MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000 - MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x80000000 - MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x80000000 - MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000 - MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000 - >; - }; - - pinctrl_power_button: powerbutgrp { - fsl,pins = < - MX53_PAD_SD2_DATA2__GPIO1_13 0x1e4 - >; - }; - - pinctrl_power_out: poweroutgrp { - fsl,pins = < - MX53_PAD_SD2_DATA0__GPIO1_15 0x1e4 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4 - MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4 - MX53_PAD_PATA_IORDY__UART1_RTS 0x1e4 - MX53_PAD_PATA_RESET_B__UART1_CTS 0x1e4 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4 - MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4 - MX53_PAD_PATA_DIOR__UART2_RTS 0x1e4 - MX53_PAD_PATA_INTRQ__UART2_CTS 0x1e4 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4 - MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4 - MX53_PAD_PATA_DA_2__UART3_RTS 0x1e4 - >; - }; - - pinctrl_usb: usbgrp { - fsl,pins = < - MX53_PAD_GPIO_2__GPIO1_2 0x1c4 - MX53_PAD_GPIO_3__USBOH3_USBH1_OC 0x1c4 - MX53_PAD_GPIO_4__GPIO1_4 0x1c4 - MX53_PAD_GPIO_18__GPIO7_13 0x1c4 - >; - }; - }; -}; - -&ldb { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lvds0>; - status = "okay"; - - lvds0: lvds-channel@0 { - reg = <0>; - fsl,data-mapping = "spwg"; - fsl,data-width = <18>; - status = "okay"; - - port@2 { - reg = <2>; - - lvds0_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - uart-has-rtscts; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - uart-has-rtscts; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - linux,rs485-enabled-at-boot-time; - status = "okay"; -}; - -&usbh1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb>; - vbus-supply = <®_usbh1_vbus>; - phy_type = "utmi"; - dr_mode = "host"; - status = "okay"; -}; - -&usbotg { - dr_mode = "peripheral"; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx53-mba53.dts b/sys/gnu/dts/arm/imx53-mba53.dts deleted file mode 100644 index 09eee0dd44c..00000000000 --- a/sys/gnu/dts/arm/imx53-mba53.dts +++ /dev/null @@ -1,249 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2012 Sascha Hauer , Pengutronix - * Copyright 2012 Steffen Trumtrar , Pengutronix - */ - -/dts-v1/; -#include "imx53-tqma53.dtsi" - -/ { - model = "TQ MBa53 starter kit"; - compatible = "tq,mba53", "tq,tqma53", "fsl,imx53"; - - chosen { - stdout-path = &uart2; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm2 0 50000>; - brightness-levels = <0 24 28 32 36 40 44 48 52 56 60 64 68 72 76 80 84 88 92 96 100>; - default-brightness-level = <10>; - enable-gpios = <&gpio7 7 0>; - power-supply = <®_backlight>; - }; - - disp1: disp1 { - compatible = "fsl,imx-parallel-display"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_disp1_1>; - interface-pix-fmt = "rgb24"; - status = "disabled"; - - port { - display1_in: endpoint { - remote-endpoint = <&ipu_di1_disp1>; - }; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_backlight: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "lcd-supply"; - gpio = <&gpio2 5 0>; - startup-delay-us = <5000>; - }; - - reg_3p2v: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "3P2V"; - regulator-min-microvolt = <3200000>; - regulator-max-microvolt = <3200000>; - regulator-always-on; - }; - }; - - sound { - compatible = "tq,imx53-mba53-sgtl5000", - "fsl,imx-audio-sgtl5000"; - model = "imx53-mba53-sgtl5000"; - ssi-controller = <&ssi2>; - audio-codec = <&codec>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - mux-int-port = <2>; - mux-ext-port = <5>; - }; -}; - -&ldb { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lvds1_1>; - status = "disabled"; -}; - -&iomuxc { - lvds1 { - pinctrl_lvds1_1: lvds1-grp1 { - fsl,pins = < - MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000 - MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000 - MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000 - MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x80000000 - MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x80000000 - >; - }; - - pinctrl_lvds1_2: lvds1-grp2 { - fsl,pins = < - MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x80000000 - MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x80000000 - MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x80000000 - MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x80000000 - MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x80000000 - >; - }; - }; - - disp1 { - pinctrl_disp1_1: disp1-grp1 { - fsl,pins = < - MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x80000000 /* DISP1_CLK */ - MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x80000000 /* DISP1_DRDY */ - MX53_PAD_EIM_D23__IPU_DI1_PIN2 0x80000000 /* DISP1_HSYNC */ - MX53_PAD_EIM_EB3__IPU_DI1_PIN3 0x80000000 /* DISP1_VSYNC */ - MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x80000000 - MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x80000000 - MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x80000000 - MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x80000000 - MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x80000000 - MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x80000000 - MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x80000000 - MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x80000000 - MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x80000000 - MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x80000000 - MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x80000000 - MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x80000000 - MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x80000000 - MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x80000000 - MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x80000000 - MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x80000000 - MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x80000000 - MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x80000000 - MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x80000000 - MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x80000000 - MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x80000000 - MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x80000000 - MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x80000000 - MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x80000000 - >; - }; - }; - - tve { - pinctrl_vga_sync_1: vgasync-grp1 { - fsl,pins = < - /* VGA_VSYNC, HSYNC with max drive strength */ - MX53_PAD_EIM_CS1__IPU_DI1_PIN6 0xe6 - MX53_PAD_EIM_DA15__IPU_DI1_PIN4 0xe6 - >; - }; - }; -}; - -&ipu_di1_disp1 { - remote-endpoint = <&display1_in>; -}; - -&cspi { - status = "okay"; -}; - -&audmux { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; -}; - -&i2c2 { - codec: sgtl5000@a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - clocks = <&clks IMX5_CLK_SSI_EXT1_GATE>; - VDDA-supply = <®_3p2v>; - VDDIO-supply = <®_3p2v>; - }; - - expander: pca9554@20 { - compatible = "pca9554"; - reg = <0x20>; - interrupts = <109>; - #gpio-cells = <2>; - gpio-controller; - }; - - sensor2: lm75@49 { - compatible = "lm75"; - reg = <0x49>; - }; -}; - -&fec { - phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&esdhc2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&ecspi1 { - status = "okay"; -}; - -&usbotg { - dr_mode = "host"; - status = "okay"; -}; - -&usbh1 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&ssi2 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&can1 { - status = "okay"; -}; - -&can2 { - status = "okay"; -}; - -&i2c3 { - status = "okay"; -}; - -&tve { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_vga_sync_1>; - ddc-i2c-bus = <&i2c3>; - fsl,tve-mode = "vga"; - fsl,hsync-pin = <4>; - fsl,vsync-pin = <6>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx53-pinfunc.h b/sys/gnu/dts/arm/imx53-pinfunc.h deleted file mode 100644 index 67bd06610fd..00000000000 --- a/sys/gnu/dts/arm/imx53-pinfunc.h +++ /dev/null @@ -1,1189 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - */ - -#ifndef __DTS_IMX53_PINFUNC_H -#define __DTS_IMX53_PINFUNC_H - -/* - * The pin function ID is a tuple of - * - */ -#define MX53_PAD_GPIO_19__KPP_COL_5 0x020 0x348 0x840 0x0 0x0 -#define MX53_PAD_GPIO_19__GPIO4_5 0x020 0x348 0x000 0x1 0x0 -#define MX53_PAD_GPIO_19__CCM_CLKO 0x020 0x348 0x000 0x2 0x0 -#define MX53_PAD_GPIO_19__SPDIF_OUT1 0x020 0x348 0x000 0x3 0x0 -#define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 0x020 0x348 0x000 0x4 0x0 -#define MX53_PAD_GPIO_19__ECSPI1_RDY 0x020 0x348 0x000 0x5 0x0 -#define MX53_PAD_GPIO_19__FEC_TDATA_3 0x020 0x348 0x000 0x6 0x0 -#define MX53_PAD_GPIO_19__SRC_INT_BOOT 0x020 0x348 0x000 0x7 0x0 -#define MX53_PAD_KEY_COL0__KPP_COL_0 0x024 0x34c 0x000 0x0 0x0 -#define MX53_PAD_KEY_COL0__GPIO4_6 0x024 0x34c 0x000 0x1 0x0 -#define MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x024 0x34c 0x758 0x2 0x0 -#define MX53_PAD_KEY_COL0__UART4_TXD_MUX 0x024 0x34c 0x000 0x4 0x0 -#define MX53_PAD_KEY_COL0__ECSPI1_SCLK 0x024 0x34c 0x79c 0x5 0x0 -#define MX53_PAD_KEY_COL0__FEC_RDATA_3 0x024 0x34c 0x000 0x6 0x0 -#define MX53_PAD_KEY_COL0__SRC_ANY_PU_RST 0x024 0x34c 0x000 0x7 0x0 -#define MX53_PAD_KEY_ROW0__KPP_ROW_0 0x028 0x350 0x000 0x0 0x0 -#define MX53_PAD_KEY_ROW0__GPIO4_7 0x028 0x350 0x000 0x1 0x0 -#define MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x028 0x350 0x74c 0x2 0x0 -#define MX53_PAD_KEY_ROW0__UART4_RXD_MUX 0x028 0x350 0x890 0x4 0x1 -#define MX53_PAD_KEY_ROW0__ECSPI1_MOSI 0x028 0x350 0x7a4 0x5 0x0 -#define MX53_PAD_KEY_ROW0__FEC_TX_ER 0x028 0x350 0x000 0x6 0x0 -#define MX53_PAD_KEY_COL1__KPP_COL_1 0x02c 0x354 0x000 0x0 0x0 -#define MX53_PAD_KEY_COL1__GPIO4_8 0x02c 0x354 0x000 0x1 0x0 -#define MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x02c 0x354 0x75c 0x2 0x0 -#define MX53_PAD_KEY_COL1__UART5_TXD_MUX 0x02c 0x354 0x000 0x4 0x0 -#define MX53_PAD_KEY_COL1__ECSPI1_MISO 0x02c 0x354 0x7a0 0x5 0x0 -#define MX53_PAD_KEY_COL1__FEC_RX_CLK 0x02c 0x354 0x808 0x6 0x0 -#define MX53_PAD_KEY_COL1__USBPHY1_TXREADY 0x02c 0x354 0x000 0x7 0x0 -#define MX53_PAD_KEY_ROW1__KPP_ROW_1 0x030 0x358 0x000 0x0 0x0 -#define MX53_PAD_KEY_ROW1__GPIO4_9 0x030 0x358 0x000 0x1 0x0 -#define MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x030 0x358 0x748 0x2 0x0 -#define MX53_PAD_KEY_ROW1__UART5_RXD_MUX 0x030 0x358 0x898 0x4 0x1 -#define MX53_PAD_KEY_ROW1__ECSPI1_SS0 0x030 0x358 0x7a8 0x5 0x0 -#define MX53_PAD_KEY_ROW1__FEC_COL 0x030 0x358 0x800 0x6 0x0 -#define MX53_PAD_KEY_ROW1__USBPHY1_RXVALID 0x030 0x358 0x000 0x7 0x0 -#define MX53_PAD_KEY_COL2__KPP_COL_2 0x034 0x35c 0x000 0x0 0x0 -#define MX53_PAD_KEY_COL2__GPIO4_10 0x034 0x35c 0x000 0x1 0x0 -#define MX53_PAD_KEY_COL2__CAN1_TXCAN 0x034 0x35c 0x000 0x2 0x0 -#define MX53_PAD_KEY_COL2__FEC_MDIO 0x034 0x35c 0x804 0x4 0x0 -#define MX53_PAD_KEY_COL2__ECSPI1_SS1 0x034 0x35c 0x7ac 0x5 0x0 -#define MX53_PAD_KEY_COL2__FEC_RDATA_2 0x034 0x35c 0x000 0x6 0x0 -#define MX53_PAD_KEY_COL2__USBPHY1_RXACTIVE 0x034 0x35c 0x000 0x7 0x0 -#define MX53_PAD_KEY_ROW2__KPP_ROW_2 0x038 0x360 0x000 0x0 0x0 -#define MX53_PAD_KEY_ROW2__GPIO4_11 0x038 0x360 0x000 0x1 0x0 -#define MX53_PAD_KEY_ROW2__CAN1_RXCAN 0x038 0x360 0x760 0x2 0x0 -#define MX53_PAD_KEY_ROW2__FEC_MDC 0x038 0x360 0x000 0x4 0x0 -#define MX53_PAD_KEY_ROW2__ECSPI1_SS2 0x038 0x360 0x7b0 0x5 0x0 -#define MX53_PAD_KEY_ROW2__FEC_TDATA_2 0x038 0x360 0x000 0x6 0x0 -#define MX53_PAD_KEY_ROW2__USBPHY1_RXERROR 0x038 0x360 0x000 0x7 0x0 -#define MX53_PAD_KEY_COL3__KPP_COL_3 0x03c 0x364 0x000 0x0 0x0 -#define MX53_PAD_KEY_COL3__GPIO4_12 0x03c 0x364 0x000 0x1 0x0 -#define MX53_PAD_KEY_COL3__USBOH3_H2_DP 0x03c 0x364 0x000 0x2 0x0 -#define MX53_PAD_KEY_COL3__SPDIF_IN1 0x03c 0x364 0x870 0x3 0x0 -#define MX53_PAD_KEY_COL3__I2C2_SCL 0x03c 0x364 0x81c 0x4 0x0 -#define MX53_PAD_KEY_COL3__ECSPI1_SS3 0x03c 0x364 0x7b4 0x5 0x0 -#define MX53_PAD_KEY_COL3__FEC_CRS 0x03c 0x364 0x000 0x6 0x0 -#define MX53_PAD_KEY_COL3__USBPHY1_SIECLOCK 0x03c 0x364 0x000 0x7 0x0 -#define MX53_PAD_KEY_ROW3__KPP_ROW_3 0x040 0x368 0x000 0x0 0x0 -#define MX53_PAD_KEY_ROW3__GPIO4_13 0x040 0x368 0x000 0x1 0x0 -#define MX53_PAD_KEY_ROW3__USBOH3_H2_DM 0x040 0x368 0x000 0x2 0x0 -#define MX53_PAD_KEY_ROW3__CCM_ASRC_EXT_CLK 0x040 0x368 0x768 0x3 0x0 -#define MX53_PAD_KEY_ROW3__I2C2_SDA 0x040 0x368 0x820 0x4 0x0 -#define MX53_PAD_KEY_ROW3__OSC32K_32K_OUT 0x040 0x368 0x000 0x5 0x0 -#define MX53_PAD_KEY_ROW3__CCM_PLL4_BYP 0x040 0x368 0x77c 0x6 0x0 -#define MX53_PAD_KEY_ROW3__USBPHY1_LINESTATE_0 0x040 0x368 0x000 0x7 0x0 -#define MX53_PAD_KEY_COL4__KPP_COL_4 0x044 0x36c 0x000 0x0 0x0 -#define MX53_PAD_KEY_COL4__GPIO4_14 0x044 0x36c 0x000 0x1 0x0 -#define MX53_PAD_KEY_COL4__CAN2_TXCAN 0x044 0x36c 0x000 0x2 0x0 -#define MX53_PAD_KEY_COL4__IPU_SISG_4 0x044 0x36c 0x000 0x3 0x0 -#define MX53_PAD_KEY_COL4__UART5_RTS 0x044 0x36c 0x894 0x4 0x0 -#define MX53_PAD_KEY_COL4__USBOH3_USBOTG_OC 0x044 0x36c 0x89c 0x5 0x0 -#define MX53_PAD_KEY_COL4__USBPHY1_LINESTATE_1 0x044 0x36c 0x000 0x7 0x0 -#define MX53_PAD_KEY_ROW4__KPP_ROW_4 0x048 0x370 0x000 0x0 0x0 -#define MX53_PAD_KEY_ROW4__GPIO4_15 0x048 0x370 0x000 0x1 0x0 -#define MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x048 0x370 0x764 0x2 0x0 -#define MX53_PAD_KEY_ROW4__IPU_SISG_5 0x048 0x370 0x000 0x3 0x0 -#define MX53_PAD_KEY_ROW4__UART5_CTS 0x048 0x370 0x000 0x4 0x0 -#define MX53_PAD_KEY_ROW4__USBOH3_USBOTG_PWR 0x048 0x370 0x000 0x5 0x0 -#define MX53_PAD_KEY_ROW4__USBPHY1_VBUSVALID 0x048 0x370 0x000 0x7 0x0 -#define MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x04c 0x378 0x000 0x0 0x0 -#define MX53_PAD_DI0_DISP_CLK__GPIO4_16 0x04c 0x378 0x000 0x1 0x0 -#define MX53_PAD_DI0_DISP_CLK__USBOH3_USBH2_DIR 0x04c 0x378 0x000 0x2 0x0 -#define MX53_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 0x04c 0x378 0x000 0x5 0x0 -#define MX53_PAD_DI0_DISP_CLK__EMI_EMI_DEBUG_0 0x04c 0x378 0x000 0x6 0x0 -#define MX53_PAD_DI0_DISP_CLK__USBPHY1_AVALID 0x04c 0x378 0x000 0x7 0x0 -#define MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 0x050 0x37c 0x000 0x0 0x0 -#define MX53_PAD_DI0_PIN15__GPIO4_17 0x050 0x37c 0x000 0x1 0x0 -#define MX53_PAD_DI0_PIN15__AUDMUX_AUD6_TXC 0x050 0x37c 0x000 0x2 0x0 -#define MX53_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 0x050 0x37c 0x000 0x5 0x0 -#define MX53_PAD_DI0_PIN15__EMI_EMI_DEBUG_1 0x050 0x37c 0x000 0x6 0x0 -#define MX53_PAD_DI0_PIN15__USBPHY1_BVALID 0x050 0x37c 0x000 0x7 0x0 -#define MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 0x054 0x380 0x000 0x0 0x0 -#define MX53_PAD_DI0_PIN2__GPIO4_18 0x054 0x380 0x000 0x1 0x0 -#define MX53_PAD_DI0_PIN2__AUDMUX_AUD6_TXD 0x054 0x380 0x000 0x2 0x0 -#define MX53_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 0x054 0x380 0x000 0x5 0x0 -#define MX53_PAD_DI0_PIN2__EMI_EMI_DEBUG_2 0x054 0x380 0x000 0x6 0x0 -#define MX53_PAD_DI0_PIN2__USBPHY1_ENDSESSION 0x054 0x380 0x000 0x7 0x0 -#define MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 0x058 0x384 0x000 0x0 0x0 -#define MX53_PAD_DI0_PIN3__GPIO4_19 0x058 0x384 0x000 0x1 0x0 -#define MX53_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS 0x058 0x384 0x000 0x2 0x0 -#define MX53_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 0x058 0x384 0x000 0x5 0x0 -#define MX53_PAD_DI0_PIN3__EMI_EMI_DEBUG_3 0x058 0x384 0x000 0x6 0x0 -#define MX53_PAD_DI0_PIN3__USBPHY1_IDDIG 0x058 0x384 0x000 0x7 0x0 -#define MX53_PAD_DI0_PIN4__IPU_DI0_PIN4 0x05c 0x388 0x000 0x0 0x0 -#define MX53_PAD_DI0_PIN4__GPIO4_20 0x05c 0x388 0x000 0x1 0x0 -#define MX53_PAD_DI0_PIN4__AUDMUX_AUD6_RXD 0x05c 0x388 0x000 0x2 0x0 -#define MX53_PAD_DI0_PIN4__ESDHC1_WP 0x05c 0x388 0x7fc 0x3 0x0 -#define MX53_PAD_DI0_PIN4__SDMA_DEBUG_YIELD 0x05c 0x388 0x000 0x5 0x0 -#define MX53_PAD_DI0_PIN4__EMI_EMI_DEBUG_4 0x05c 0x388 0x000 0x6 0x0 -#define MX53_PAD_DI0_PIN4__USBPHY1_HOSTDISCONNECT 0x05c 0x388 0x000 0x7 0x0 -#define MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 0x060 0x38c 0x000 0x0 0x0 -#define MX53_PAD_DISP0_DAT0__GPIO4_21 0x060 0x38c 0x000 0x1 0x0 -#define MX53_PAD_DISP0_DAT0__CSPI_SCLK 0x060 0x38c 0x780 0x2 0x0 -#define MX53_PAD_DISP0_DAT0__USBOH3_USBH2_DATA_0 0x060 0x38c 0x000 0x3 0x0 -#define MX53_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN 0x060 0x38c 0x000 0x5 0x0 -#define MX53_PAD_DISP0_DAT0__EMI_EMI_DEBUG_5 0x060 0x38c 0x000 0x6 0x0 -#define MX53_PAD_DISP0_DAT0__USBPHY2_TXREADY 0x060 0x38c 0x000 0x7 0x0 -#define MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 0x064 0x390 0x000 0x0 0x0 -#define MX53_PAD_DISP0_DAT1__GPIO4_22 0x064 0x390 0x000 0x1 0x0 -#define MX53_PAD_DISP0_DAT1__CSPI_MOSI 0x064 0x390 0x788 0x2 0x0 -#define MX53_PAD_DISP0_DAT1__USBOH3_USBH2_DATA_1 0x064 0x390 0x000 0x3 0x0 -#define MX53_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL 0x064 0x390 0x000 0x5 0x0 -#define MX53_PAD_DISP0_DAT1__EMI_EMI_DEBUG_6 0x064 0x390 0x000 0x6 0x0 -#define MX53_PAD_DISP0_DAT1__USBPHY2_RXVALID 0x064 0x390 0x000 0x7 0x0 -#define MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 0x068 0x394 0x000 0x0 0x0 -#define MX53_PAD_DISP0_DAT2__GPIO4_23 0x068 0x394 0x000 0x1 0x0 -#define MX53_PAD_DISP0_DAT2__CSPI_MISO 0x068 0x394 0x784 0x2 0x0 -#define MX53_PAD_DISP0_DAT2__USBOH3_USBH2_DATA_2 0x068 0x394 0x000 0x3 0x0 -#define MX53_PAD_DISP0_DAT2__SDMA_DEBUG_MODE 0x068 0x394 0x000 0x5 0x0 -#define MX53_PAD_DISP0_DAT2__EMI_EMI_DEBUG_7 0x068 0x394 0x000 0x6 0x0 -#define MX53_PAD_DISP0_DAT2__USBPHY2_RXACTIVE 0x068 0x394 0x000 0x7 0x0 -#define MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 0x06c 0x398 0x000 0x0 0x0 -#define MX53_PAD_DISP0_DAT3__GPIO4_24 0x06c 0x398 0x000 0x1 0x0 -#define MX53_PAD_DISP0_DAT3__CSPI_SS0 0x06c 0x398 0x78c 0x2 0x0 -#define MX53_PAD_DISP0_DAT3__USBOH3_USBH2_DATA_3 0x06c 0x398 0x000 0x3 0x0 -#define MX53_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR 0x06c 0x398 0x000 0x5 0x0 -#define MX53_PAD_DISP0_DAT3__EMI_EMI_DEBUG_8 0x06c 0x398 0x000 0x6 0x0 -#define MX53_PAD_DISP0_DAT3__USBPHY2_RXERROR 0x06c 0x398 0x000 0x7 0x0 -#define MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 0x070 0x39c 0x000 0x0 0x0 -#define MX53_PAD_DISP0_DAT4__GPIO4_25 0x070 0x39c 0x000 0x1 0x0 -#define MX53_PAD_DISP0_DAT4__CSPI_SS1 0x070 0x39c 0x790 0x2 0x0 -#define MX53_PAD_DISP0_DAT4__USBOH3_USBH2_DATA_4 0x070 0x39c 0x000 0x3 0x0 -#define MX53_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB 0x070 0x39c 0x000 0x5 0x0 -#define MX53_PAD_DISP0_DAT4__EMI_EMI_DEBUG_9 0x070 0x39c 0x000 0x6 0x0 -#define MX53_PAD_DISP0_DAT4__USBPHY2_SIECLOCK 0x070 0x39c 0x000 0x7 0x0 -#define MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 0x074 0x3a0 0x000 0x0 0x0 -#define MX53_PAD_DISP0_DAT5__GPIO4_26 0x074 0x3a0 0x000 0x1 0x0 -#define MX53_PAD_DISP0_DAT5__CSPI_SS2 0x074 0x3a0 0x794 0x2 0x0 -#define MX53_PAD_DISP0_DAT5__USBOH3_USBH2_DATA_5 0x074 0x3a0 0x000 0x3 0x0 -#define MX53_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS 0x074 0x3a0 0x000 0x5 0x0 -#define MX53_PAD_DISP0_DAT5__EMI_EMI_DEBUG_10 0x074 0x3a0 0x000 0x6 0x0 -#define MX53_PAD_DISP0_DAT5__USBPHY2_LINESTATE_0 0x074 0x3a0 0x000 0x7 0x0 -#define MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 0x078 0x3a4 0x000 0x0 0x0 -#define MX53_PAD_DISP0_DAT6__GPIO4_27 0x078 0x3a4 0x000 0x1 0x0 -#define MX53_PAD_DISP0_DAT6__CSPI_SS3 0x078 0x3a4 0x798 0x2 0x0 -#define MX53_PAD_DISP0_DAT6__USBOH3_USBH2_DATA_6 0x078 0x3a4 0x000 0x3 0x0 -#define MX53_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE 0x078 0x3a4 0x000 0x5 0x0 -#define MX53_PAD_DISP0_DAT6__EMI_EMI_DEBUG_11 0x078 0x3a4 0x000 0x6 0x0 -#define MX53_PAD_DISP0_DAT6__USBPHY2_LINESTATE_1 0x078 0x3a4 0x000 0x7 0x0 -#define MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 0x07c 0x3a8 0x000 0x0 0x0 -#define MX53_PAD_DISP0_DAT7__GPIO4_28 0x07c 0x3a8 0x000 0x1 0x0 -#define MX53_PAD_DISP0_DAT7__CSPI_RDY 0x07c 0x3a8 0x000 0x2 0x0 -#define MX53_PAD_DISP0_DAT7__USBOH3_USBH2_DATA_7 0x07c 0x3a8 0x000 0x3 0x0 -#define MX53_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 0x07c 0x3a8 0x000 0x5 0x0 -#define MX53_PAD_DISP0_DAT7__EMI_EMI_DEBUG_12 0x07c 0x3a8 0x000 0x6 0x0 -#define MX53_PAD_DISP0_DAT7__USBPHY2_VBUSVALID 0x07c 0x3a8 0x000 0x7 0x0 -#define MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 0x080 0x3ac 0x000 0x0 0x0 -#define MX53_PAD_DISP0_DAT8__GPIO4_29 0x080 0x3ac 0x000 0x1 0x0 -#define MX53_PAD_DISP0_DAT8__PWM1_PWMO 0x080 0x3ac 0x000 0x2 0x0 -#define MX53_PAD_DISP0_DAT8__WDOG1_WDOG_B 0x080 0x3ac 0x000 0x3 0x0 -#define MX53_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 0x080 0x3ac 0x000 0x5 0x0 -#define MX53_PAD_DISP0_DAT8__EMI_EMI_DEBUG_13 0x080 0x3ac 0x000 0x6 0x0 -#define MX53_PAD_DISP0_DAT8__USBPHY2_AVALID 0x080 0x3ac 0x000 0x7 0x0 -#define MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 0x084 0x3b0 0x000 0x0 0x0 -#define MX53_PAD_DISP0_DAT9__GPIO4_30 0x084 0x3b0 0x000 0x1 0x0 -#define MX53_PAD_DISP0_DAT9__PWM2_PWMO 0x084 0x3b0 0x000 0x2 0x0 -#define MX53_PAD_DISP0_DAT9__WDOG2_WDOG_B 0x084 0x3b0 0x000 0x3 0x0 -#define MX53_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 0x084 0x3b0 0x000 0x5 0x0 -#define MX53_PAD_DISP0_DAT9__EMI_EMI_DEBUG_14 0x084 0x3b0 0x000 0x6 0x0 -#define MX53_PAD_DISP0_DAT9__USBPHY2_VSTATUS_0 0x084 0x3b0 0x000 0x7 0x0 -#define MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 0x088 0x3b4 0x000 0x0 0x0 -#define MX53_PAD_DISP0_DAT10__GPIO4_31 0x088 0x3b4 0x000 0x1 0x0 -#define MX53_PAD_DISP0_DAT10__USBOH3_USBH2_STP 0x088 0x3b4 0x000 0x2 0x0 -#define MX53_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 0x088 0x3b4 0x000 0x5 0x0 -#define MX53_PAD_DISP0_DAT10__EMI_EMI_DEBUG_15 0x088 0x3b4 0x000 0x6 0x0 -#define MX53_PAD_DISP0_DAT10__USBPHY2_VSTATUS_1 0x088 0x3b4 0x000 0x7 0x0 -#define MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 0x08c 0x3b8 0x000 0x0 0x0 -#define MX53_PAD_DISP0_DAT11__GPIO5_5 0x08c 0x3b8 0x000 0x1 0x0 -#define MX53_PAD_DISP0_DAT11__USBOH3_USBH2_NXT 0x08c 0x3b8 0x000 0x2 0x0 -#define MX53_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 0x08c 0x3b8 0x000 0x5 0x0 -#define MX53_PAD_DISP0_DAT11__EMI_EMI_DEBUG_16 0x08c 0x3b8 0x000 0x6 0x0 -#define MX53_PAD_DISP0_DAT11__USBPHY2_VSTATUS_2 0x08c 0x3b8 0x000 0x7 0x0 -#define MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 0x090 0x3bc 0x000 0x0 0x0 -#define MX53_PAD_DISP0_DAT12__GPIO5_6 0x090 0x3bc 0x000 0x1 0x0 -#define MX53_PAD_DISP0_DAT12__USBOH3_USBH2_CLK 0x090 0x3bc 0x000 0x2 0x0 -#define MX53_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 0x090 0x3bc 0x000 0x5 0x0 -#define MX53_PAD_DISP0_DAT12__EMI_EMI_DEBUG_17 0x090 0x3bc 0x000 0x6 0x0 -#define MX53_PAD_DISP0_DAT12__USBPHY2_VSTATUS_3 0x090 0x3bc 0x000 0x7 0x0 -#define MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 0x094 0x3c0 0x000 0x0 0x0 -#define MX53_PAD_DISP0_DAT13__GPIO5_7 0x094 0x3c0 0x000 0x1 0x0 -#define MX53_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS 0x094 0x3c0 0x754 0x3 0x0 -#define MX53_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 0x094 0x3c0 0x000 0x5 0x0 -#define MX53_PAD_DISP0_DAT13__EMI_EMI_DEBUG_18 0x094 0x3c0 0x000 0x6 0x0 -#define MX53_PAD_DISP0_DAT13__USBPHY2_VSTATUS_4 0x094 0x3c0 0x000 0x7 0x0 -#define MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 0x098 0x3c4 0x000 0x0 0x0 -#define MX53_PAD_DISP0_DAT14__GPIO5_8 0x098 0x3c4 0x000 0x1 0x0 -#define MX53_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC 0x098 0x3c4 0x750 0x3 0x0 -#define MX53_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 0x098 0x3c4 0x000 0x5 0x0 -#define MX53_PAD_DISP0_DAT14__EMI_EMI_DEBUG_19 0x098 0x3c4 0x000 0x6 0x0 -#define MX53_PAD_DISP0_DAT14__USBPHY2_VSTATUS_5 0x098 0x3c4 0x000 0x7 0x0 -#define MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 0x09c 0x3c8 0x000 0x0 0x0 -#define MX53_PAD_DISP0_DAT15__GPIO5_9 0x09c 0x3c8 0x000 0x1 0x0 -#define MX53_PAD_DISP0_DAT15__ECSPI1_SS1 0x09c 0x3c8 0x7ac 0x2 0x1 -#define MX53_PAD_DISP0_DAT15__ECSPI2_SS1 0x09c 0x3c8 0x7c8 0x3 0x0 -#define MX53_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 0x09c 0x3c8 0x000 0x5 0x0 -#define MX53_PAD_DISP0_DAT15__EMI_EMI_DEBUG_20 0x09c 0x3c8 0x000 0x6 0x0 -#define MX53_PAD_DISP0_DAT15__USBPHY2_VSTATUS_6 0x09c 0x3c8 0x000 0x7 0x0 -#define MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 0x0a0 0x3cc 0x000 0x0 0x0 -#define MX53_PAD_DISP0_DAT16__GPIO5_10 0x0a0 0x3cc 0x000 0x1 0x0 -#define MX53_PAD_DISP0_DAT16__ECSPI2_MOSI 0x0a0 0x3cc 0x7c0 0x2 0x0 -#define MX53_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC 0x0a0 0x3cc 0x758 0x3 0x1 -#define MX53_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0 0x0a0 0x3cc 0x868 0x4 0x0 -#define MX53_PAD_DISP0_DAT16__SDMA_DEBUG_EVT_CHN_LINES_3 0x0a0 0x3cc 0x000 0x5 0x0 -#define MX53_PAD_DISP0_DAT16__EMI_EMI_DEBUG_21 0x0a0 0x3cc 0x000 0x6 0x0 -#define MX53_PAD_DISP0_DAT16__USBPHY2_VSTATUS_7 0x0a0 0x3cc 0x000 0x7 0x0 -#define MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 0x0a4 0x3d0 0x000 0x0 0x0 -#define MX53_PAD_DISP0_DAT17__GPIO5_11 0x0a4 0x3d0 0x000 0x1 0x0 -#define MX53_PAD_DISP0_DAT17__ECSPI2_MISO 0x0a4 0x3d0 0x7bc 0x2 0x0 -#define MX53_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD 0x0a4 0x3d0 0x74c 0x3 0x1 -#define MX53_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1 0x0a4 0x3d0 0x86c 0x4 0x0 -#define MX53_PAD_DISP0_DAT17__SDMA_DEBUG_EVT_CHN_LINES_4 0x0a4 0x3d0 0x000 0x5 0x0 -#define MX53_PAD_DISP0_DAT17__EMI_EMI_DEBUG_22 0x0a4 0x3d0 0x000 0x6 0x0 -#define MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 0x0a8 0x3d4 0x000 0x0 0x0 -#define MX53_PAD_DISP0_DAT18__GPIO5_12 0x0a8 0x3d4 0x000 0x1 0x0 -#define MX53_PAD_DISP0_DAT18__ECSPI2_SS0 0x0a8 0x3d4 0x7c4 0x2 0x0 -#define MX53_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS 0x0a8 0x3d4 0x75c 0x3 0x1 -#define MX53_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS 0x0a8 0x3d4 0x73c 0x4 0x0 -#define MX53_PAD_DISP0_DAT18__SDMA_DEBUG_EVT_CHN_LINES_5 0x0a8 0x3d4 0x000 0x5 0x0 -#define MX53_PAD_DISP0_DAT18__EMI_EMI_DEBUG_23 0x0a8 0x3d4 0x000 0x6 0x0 -#define MX53_PAD_DISP0_DAT18__EMI_WEIM_CS_2 0x0a8 0x3d4 0x000 0x7 0x0 -#define MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 0x0ac 0x3d8 0x000 0x0 0x0 -#define MX53_PAD_DISP0_DAT19__GPIO5_13 0x0ac 0x3d8 0x000 0x1 0x0 -#define MX53_PAD_DISP0_DAT19__ECSPI2_SCLK 0x0ac 0x3d8 0x7b8 0x2 0x0 -#define MX53_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD 0x0ac 0x3d8 0x748 0x3 0x1 -#define MX53_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC 0x0ac 0x3d8 0x738 0x4 0x0 -#define MX53_PAD_DISP0_DAT19__SDMA_DEBUG_EVT_CHN_LINES_6 0x0ac 0x3d8 0x000 0x5 0x0 -#define MX53_PAD_DISP0_DAT19__EMI_EMI_DEBUG_24 0x0ac 0x3d8 0x000 0x6 0x0 -#define MX53_PAD_DISP0_DAT19__EMI_WEIM_CS_3 0x0ac 0x3d8 0x000 0x7 0x0 -#define MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 0x0b0 0x3dc 0x000 0x0 0x0 -#define MX53_PAD_DISP0_DAT20__GPIO5_14 0x0b0 0x3dc 0x000 0x1 0x0 -#define MX53_PAD_DISP0_DAT20__ECSPI1_SCLK 0x0b0 0x3dc 0x79c 0x2 0x1 -#define MX53_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC 0x0b0 0x3dc 0x740 0x3 0x0 -#define MX53_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 0x0b0 0x3dc 0x000 0x5 0x0 -#define MX53_PAD_DISP0_DAT20__EMI_EMI_DEBUG_25 0x0b0 0x3dc 0x000 0x6 0x0 -#define MX53_PAD_DISP0_DAT20__SATA_PHY_TDI 0x0b0 0x3dc 0x000 0x7 0x0 -#define MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 0x0b4 0x3e0 0x000 0x0 0x0 -#define MX53_PAD_DISP0_DAT21__GPIO5_15 0x0b4 0x3e0 0x000 0x1 0x0 -#define MX53_PAD_DISP0_DAT21__ECSPI1_MOSI 0x0b4 0x3e0 0x7a4 0x2 0x1 -#define MX53_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD 0x0b4 0x3e0 0x734 0x3 0x0 -#define MX53_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 0x0b4 0x3e0 0x000 0x5 0x0 -#define MX53_PAD_DISP0_DAT21__EMI_EMI_DEBUG_26 0x0b4 0x3e0 0x000 0x6 0x0 -#define MX53_PAD_DISP0_DAT21__SATA_PHY_TDO 0x0b4 0x3e0 0x000 0x7 0x0 -#define MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 0x0b8 0x3e4 0x000 0x0 0x0 -#define MX53_PAD_DISP0_DAT22__GPIO5_16 0x0b8 0x3e4 0x000 0x1 0x0 -#define MX53_PAD_DISP0_DAT22__ECSPI1_MISO 0x0b8 0x3e4 0x7a0 0x2 0x1 -#define MX53_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS 0x0b8 0x3e4 0x744 0x3 0x0 -#define MX53_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 0x0b8 0x3e4 0x000 0x5 0x0 -#define MX53_PAD_DISP0_DAT22__EMI_EMI_DEBUG_27 0x0b8 0x3e4 0x000 0x6 0x0 -#define MX53_PAD_DISP0_DAT22__SATA_PHY_TCK 0x0b8 0x3e4 0x000 0x7 0x0 -#define MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 0x0bc 0x3e8 0x000 0x0 0x0 -#define MX53_PAD_DISP0_DAT23__GPIO5_17 0x0bc 0x3e8 0x000 0x1 0x0 -#define MX53_PAD_DISP0_DAT23__ECSPI1_SS0 0x0bc 0x3e8 0x7a8 0x2 0x1 -#define MX53_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD 0x0bc 0x3e8 0x730 0x3 0x0 -#define MX53_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 0x0bc 0x3e8 0x000 0x5 0x0 -#define MX53_PAD_DISP0_DAT23__EMI_EMI_DEBUG_28 0x0bc 0x3e8 0x000 0x6 0x0 -#define MX53_PAD_DISP0_DAT23__SATA_PHY_TMS 0x0bc 0x3e8 0x000 0x7 0x0 -#define MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x0c0 0x3ec 0x000 0x0 0x0 -#define MX53_PAD_CSI0_PIXCLK__GPIO5_18 0x0c0 0x3ec 0x000 0x1 0x0 -#define MX53_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 0x0c0 0x3ec 0x000 0x5 0x0 -#define MX53_PAD_CSI0_PIXCLK__EMI_EMI_DEBUG_29 0x0c0 0x3ec 0x000 0x6 0x0 -#define MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC 0x0c4 0x3f0 0x000 0x0 0x0 -#define MX53_PAD_CSI0_MCLK__GPIO5_19 0x0c4 0x3f0 0x000 0x1 0x0 -#define MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK 0x0c4 0x3f0 0x000 0x2 0x0 -#define MX53_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 0x0c4 0x3f0 0x000 0x5 0x0 -#define MX53_PAD_CSI0_MCLK__EMI_EMI_DEBUG_30 0x0c4 0x3f0 0x000 0x6 0x0 -#define MX53_PAD_CSI0_MCLK__TPIU_TRCTL 0x0c4 0x3f0 0x000 0x7 0x0 -#define MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN 0x0c8 0x3f4 0x000 0x0 0x0 -#define MX53_PAD_CSI0_DATA_EN__GPIO5_20 0x0c8 0x3f4 0x000 0x1 0x0 -#define MX53_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 0x0c8 0x3f4 0x000 0x5 0x0 -#define MX53_PAD_CSI0_DATA_EN__EMI_EMI_DEBUG_31 0x0c8 0x3f4 0x000 0x6 0x0 -#define MX53_PAD_CSI0_DATA_EN__TPIU_TRCLK 0x0c8 0x3f4 0x000 0x7 0x0 -#define MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC 0x0cc 0x3f8 0x000 0x0 0x0 -#define MX53_PAD_CSI0_VSYNC__GPIO5_21 0x0cc 0x3f8 0x000 0x1 0x0 -#define MX53_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 0x0cc 0x3f8 0x000 0x5 0x0 -#define MX53_PAD_CSI0_VSYNC__EMI_EMI_DEBUG_32 0x0cc 0x3f8 0x000 0x6 0x0 -#define MX53_PAD_CSI0_VSYNC__TPIU_TRACE_0 0x0cc 0x3f8 0x000 0x7 0x0 -#define MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 0x0d0 0x3fc 0x000 0x0 0x0 -#define MX53_PAD_CSI0_DAT4__GPIO5_22 0x0d0 0x3fc 0x000 0x1 0x0 -#define MX53_PAD_CSI0_DAT4__KPP_COL_5 0x0d0 0x3fc 0x840 0x2 0x1 -#define MX53_PAD_CSI0_DAT4__ECSPI1_SCLK 0x0d0 0x3fc 0x79c 0x3 0x2 -#define MX53_PAD_CSI0_DAT4__USBOH3_USBH3_STP 0x0d0 0x3fc 0x000 0x4 0x0 -#define MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC 0x0d0 0x3fc 0x000 0x5 0x0 -#define MX53_PAD_CSI0_DAT4__EMI_EMI_DEBUG_33 0x0d0 0x3fc 0x000 0x6 0x0 -#define MX53_PAD_CSI0_DAT4__TPIU_TRACE_1 0x0d0 0x3fc 0x000 0x7 0x0 -#define MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 0x0d4 0x400 0x000 0x0 0x0 -#define MX53_PAD_CSI0_DAT5__GPIO5_23 0x0d4 0x400 0x000 0x1 0x0 -#define MX53_PAD_CSI0_DAT5__KPP_ROW_5 0x0d4 0x400 0x84c 0x2 0x0 -#define MX53_PAD_CSI0_DAT5__ECSPI1_MOSI 0x0d4 0x400 0x7a4 0x3 0x2 -#define MX53_PAD_CSI0_DAT5__USBOH3_USBH3_NXT 0x0d4 0x400 0x000 0x4 0x0 -#define MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD 0x0d4 0x400 0x000 0x5 0x0 -#define MX53_PAD_CSI0_DAT5__EMI_EMI_DEBUG_34 0x0d4 0x400 0x000 0x6 0x0 -#define MX53_PAD_CSI0_DAT5__TPIU_TRACE_2 0x0d4 0x400 0x000 0x7 0x0 -#define MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 0x0d8 0x404 0x000 0x0 0x0 -#define MX53_PAD_CSI0_DAT6__GPIO5_24 0x0d8 0x404 0x000 0x1 0x0 -#define MX53_PAD_CSI0_DAT6__KPP_COL_6 0x0d8 0x404 0x844 0x2 0x0 -#define MX53_PAD_CSI0_DAT6__ECSPI1_MISO 0x0d8 0x404 0x7a0 0x3 0x2 -#define MX53_PAD_CSI0_DAT6__USBOH3_USBH3_CLK 0x0d8 0x404 0x000 0x4 0x0 -#define MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS 0x0d8 0x404 0x000 0x5 0x0 -#define MX53_PAD_CSI0_DAT6__EMI_EMI_DEBUG_35 0x0d8 0x404 0x000 0x6 0x0 -#define MX53_PAD_CSI0_DAT6__TPIU_TRACE_3 0x0d8 0x404 0x000 0x7 0x0 -#define MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 0x0dc 0x408 0x000 0x0 0x0 -#define MX53_PAD_CSI0_DAT7__GPIO5_25 0x0dc 0x408 0x000 0x1 0x0 -#define MX53_PAD_CSI0_DAT7__KPP_ROW_6 0x0dc 0x408 0x850 0x2 0x0 -#define MX53_PAD_CSI0_DAT7__ECSPI1_SS0 0x0dc 0x408 0x7a8 0x3 0x2 -#define MX53_PAD_CSI0_DAT7__USBOH3_USBH3_DIR 0x0dc 0x408 0x000 0x4 0x0 -#define MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD 0x0dc 0x408 0x000 0x5 0x0 -#define MX53_PAD_CSI0_DAT7__EMI_EMI_DEBUG_36 0x0dc 0x408 0x000 0x6 0x0 -#define MX53_PAD_CSI0_DAT7__TPIU_TRACE_4 0x0dc 0x408 0x000 0x7 0x0 -#define MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 0x0e0 0x40c 0x000 0x0 0x0 -#define MX53_PAD_CSI0_DAT8__GPIO5_26 0x0e0 0x40c 0x000 0x1 0x0 -#define MX53_PAD_CSI0_DAT8__KPP_COL_7 0x0e0 0x40c 0x848 0x2 0x0 -#define MX53_PAD_CSI0_DAT8__ECSPI2_SCLK 0x0e0 0x40c 0x7b8 0x3 0x1 -#define MX53_PAD_CSI0_DAT8__USBOH3_USBH3_OC 0x0e0 0x40c 0x000 0x4 0x0 -#define MX53_PAD_CSI0_DAT8__I2C1_SDA 0x0e0 0x40c 0x818 0x5 0x0 -#define MX53_PAD_CSI0_DAT8__EMI_EMI_DEBUG_37 0x0e0 0x40c 0x000 0x6 0x0 -#define MX53_PAD_CSI0_DAT8__TPIU_TRACE_5 0x0e0 0x40c 0x000 0x7 0x0 -#define MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 0x0e4 0x410 0x000 0x0 0x0 -#define MX53_PAD_CSI0_DAT9__GPIO5_27 0x0e4 0x410 0x000 0x1 0x0 -#define MX53_PAD_CSI0_DAT9__KPP_ROW_7 0x0e4 0x410 0x854 0x2 0x0 -#define MX53_PAD_CSI0_DAT9__ECSPI2_MOSI 0x0e4 0x410 0x7c0 0x3 0x1 -#define MX53_PAD_CSI0_DAT9__USBOH3_USBH3_PWR 0x0e4 0x410 0x000 0x4 0x0 -#define MX53_PAD_CSI0_DAT9__I2C1_SCL 0x0e4 0x410 0x814 0x5 0x0 -#define MX53_PAD_CSI0_DAT9__EMI_EMI_DEBUG_38 0x0e4 0x410 0x000 0x6 0x0 -#define MX53_PAD_CSI0_DAT9__TPIU_TRACE_6 0x0e4 0x410 0x000 0x7 0x0 -#define MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 0x0e8 0x414 0x000 0x0 0x0 -#define MX53_PAD_CSI0_DAT10__GPIO5_28 0x0e8 0x414 0x000 0x1 0x0 -#define MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x0e8 0x414 0x000 0x2 0x0 -#define MX53_PAD_CSI0_DAT10__ECSPI2_MISO 0x0e8 0x414 0x7bc 0x3 0x1 -#define MX53_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC 0x0e8 0x414 0x000 0x4 0x0 -#define MX53_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 0x0e8 0x414 0x000 0x5 0x0 -#define MX53_PAD_CSI0_DAT10__EMI_EMI_DEBUG_39 0x0e8 0x414 0x000 0x6 0x0 -#define MX53_PAD_CSI0_DAT10__TPIU_TRACE_7 0x0e8 0x414 0x000 0x7 0x0 -#define MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 0x0ec 0x418 0x000 0x0 0x0 -#define MX53_PAD_CSI0_DAT11__GPIO5_29 0x0ec 0x418 0x000 0x1 0x0 -#define MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x0ec 0x418 0x878 0x2 0x1 -#define MX53_PAD_CSI0_DAT11__ECSPI2_SS0 0x0ec 0x418 0x7c4 0x3 0x1 -#define MX53_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS 0x0ec 0x418 0x000 0x4 0x0 -#define MX53_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 0x0ec 0x418 0x000 0x5 0x0 -#define MX53_PAD_CSI0_DAT11__EMI_EMI_DEBUG_40 0x0ec 0x418 0x000 0x6 0x0 -#define MX53_PAD_CSI0_DAT11__TPIU_TRACE_8 0x0ec 0x418 0x000 0x7 0x0 -#define MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 0x0f0 0x41c 0x000 0x0 0x0 -#define MX53_PAD_CSI0_DAT12__GPIO5_30 0x0f0 0x41c 0x000 0x1 0x0 -#define MX53_PAD_CSI0_DAT12__UART4_TXD_MUX 0x0f0 0x41c 0x000 0x2 0x0 -#define MX53_PAD_CSI0_DAT12__USBOH3_USBH3_DATA_0 0x0f0 0x41c 0x000 0x4 0x0 -#define MX53_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 0x0f0 0x41c 0x000 0x5 0x0 -#define MX53_PAD_CSI0_DAT12__EMI_EMI_DEBUG_41 0x0f0 0x41c 0x000 0x6 0x0 -#define MX53_PAD_CSI0_DAT12__TPIU_TRACE_9 0x0f0 0x41c 0x000 0x7 0x0 -#define MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 0x0f4 0x420 0x000 0x0 0x0 -#define MX53_PAD_CSI0_DAT13__GPIO5_31 0x0f4 0x420 0x000 0x1 0x0 -#define MX53_PAD_CSI0_DAT13__UART4_RXD_MUX 0x0f4 0x420 0x890 0x2 0x3 -#define MX53_PAD_CSI0_DAT13__USBOH3_USBH3_DATA_1 0x0f4 0x420 0x000 0x4 0x0 -#define MX53_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 0x0f4 0x420 0x000 0x5 0x0 -#define MX53_PAD_CSI0_DAT13__EMI_EMI_DEBUG_42 0x0f4 0x420 0x000 0x6 0x0 -#define MX53_PAD_CSI0_DAT13__TPIU_TRACE_10 0x0f4 0x420 0x000 0x7 0x0 -#define MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 0x0f8 0x424 0x000 0x0 0x0 -#define MX53_PAD_CSI0_DAT14__GPIO6_0 0x0f8 0x424 0x000 0x1 0x0 -#define MX53_PAD_CSI0_DAT14__UART5_TXD_MUX 0x0f8 0x424 0x000 0x2 0x0 -#define MX53_PAD_CSI0_DAT14__USBOH3_USBH3_DATA_2 0x0f8 0x424 0x000 0x4 0x0 -#define MX53_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 0x0f8 0x424 0x000 0x5 0x0 -#define MX53_PAD_CSI0_DAT14__EMI_EMI_DEBUG_43 0x0f8 0x424 0x000 0x6 0x0 -#define MX53_PAD_CSI0_DAT14__TPIU_TRACE_11 0x0f8 0x424 0x000 0x7 0x0 -#define MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 0x0fc 0x428 0x000 0x0 0x0 -#define MX53_PAD_CSI0_DAT15__GPIO6_1 0x0fc 0x428 0x000 0x1 0x0 -#define MX53_PAD_CSI0_DAT15__UART5_RXD_MUX 0x0fc 0x428 0x898 0x2 0x3 -#define MX53_PAD_CSI0_DAT15__USBOH3_USBH3_DATA_3 0x0fc 0x428 0x000 0x4 0x0 -#define MX53_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 0x0fc 0x428 0x000 0x5 0x0 -#define MX53_PAD_CSI0_DAT15__EMI_EMI_DEBUG_44 0x0fc 0x428 0x000 0x6 0x0 -#define MX53_PAD_CSI0_DAT15__TPIU_TRACE_12 0x0fc 0x428 0x000 0x7 0x0 -#define MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 0x100 0x42c 0x000 0x0 0x0 -#define MX53_PAD_CSI0_DAT16__GPIO6_2 0x100 0x42c 0x000 0x1 0x0 -#define MX53_PAD_CSI0_DAT16__UART4_RTS 0x100 0x42c 0x88c 0x2 0x0 -#define MX53_PAD_CSI0_DAT16__USBOH3_USBH3_DATA_4 0x100 0x42c 0x000 0x4 0x0 -#define MX53_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 0x100 0x42c 0x000 0x5 0x0 -#define MX53_PAD_CSI0_DAT16__EMI_EMI_DEBUG_45 0x100 0x42c 0x000 0x6 0x0 -#define MX53_PAD_CSI0_DAT16__TPIU_TRACE_13 0x100 0x42c 0x000 0x7 0x0 -#define MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 0x104 0x430 0x000 0x0 0x0 -#define MX53_PAD_CSI0_DAT17__GPIO6_3 0x104 0x430 0x000 0x1 0x0 -#define MX53_PAD_CSI0_DAT17__UART4_CTS 0x104 0x430 0x000 0x2 0x0 -#define MX53_PAD_CSI0_DAT17__USBOH3_USBH3_DATA_5 0x104 0x430 0x000 0x4 0x0 -#define MX53_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 0x104 0x430 0x000 0x5 0x0 -#define MX53_PAD_CSI0_DAT17__EMI_EMI_DEBUG_46 0x104 0x430 0x000 0x6 0x0 -#define MX53_PAD_CSI0_DAT17__TPIU_TRACE_14 0x104 0x430 0x000 0x7 0x0 -#define MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 0x108 0x434 0x000 0x0 0x0 -#define MX53_PAD_CSI0_DAT18__GPIO6_4 0x108 0x434 0x000 0x1 0x0 -#define MX53_PAD_CSI0_DAT18__UART5_RTS 0x108 0x434 0x894 0x2 0x2 -#define MX53_PAD_CSI0_DAT18__USBOH3_USBH3_DATA_6 0x108 0x434 0x000 0x4 0x0 -#define MX53_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 0x108 0x434 0x000 0x5 0x0 -#define MX53_PAD_CSI0_DAT18__EMI_EMI_DEBUG_47 0x108 0x434 0x000 0x6 0x0 -#define MX53_PAD_CSI0_DAT18__TPIU_TRACE_15 0x108 0x434 0x000 0x7 0x0 -#define MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 0x10c 0x438 0x000 0x0 0x0 -#define MX53_PAD_CSI0_DAT19__GPIO6_5 0x10c 0x438 0x000 0x1 0x0 -#define MX53_PAD_CSI0_DAT19__UART5_CTS 0x10c 0x438 0x000 0x2 0x0 -#define MX53_PAD_CSI0_DAT19__USBOH3_USBH3_DATA_7 0x10c 0x438 0x000 0x4 0x0 -#define MX53_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 0x10c 0x438 0x000 0x5 0x0 -#define MX53_PAD_CSI0_DAT19__EMI_EMI_DEBUG_48 0x10c 0x438 0x000 0x6 0x0 -#define MX53_PAD_CSI0_DAT19__USBPHY2_BISTOK 0x10c 0x438 0x000 0x7 0x0 -#define MX53_PAD_EIM_A25__EMI_WEIM_A_25 0x110 0x458 0x000 0x0 0x0 -#define MX53_PAD_EIM_A25__GPIO5_2 0x110 0x458 0x000 0x1 0x0 -#define MX53_PAD_EIM_A25__ECSPI2_RDY 0x110 0x458 0x000 0x2 0x0 -#define MX53_PAD_EIM_A25__IPU_DI1_PIN12 0x110 0x458 0x000 0x3 0x0 -#define MX53_PAD_EIM_A25__CSPI_SS1 0x110 0x458 0x790 0x4 0x1 -#define MX53_PAD_EIM_A25__IPU_DI0_D1_CS 0x110 0x458 0x000 0x6 0x0 -#define MX53_PAD_EIM_A25__USBPHY1_BISTOK 0x110 0x458 0x000 0x7 0x0 -#define MX53_PAD_EIM_EB2__EMI_WEIM_EB_2 0x114 0x45c 0x000 0x0 0x0 -#define MX53_PAD_EIM_EB2__GPIO2_30 0x114 0x45c 0x000 0x1 0x0 -#define MX53_PAD_EIM_EB2__CCM_DI1_EXT_CLK 0x114 0x45c 0x76c 0x2 0x0 -#define MX53_PAD_EIM_EB2__IPU_SER_DISP1_CS 0x114 0x45c 0x000 0x3 0x0 -#define MX53_PAD_EIM_EB2__ECSPI1_SS0 0x114 0x45c 0x7a8 0x4 0x3 -#define MX53_PAD_EIM_EB2__I2C2_SCL 0x114 0x45c 0x81c 0x5 0x1 -#define MX53_PAD_EIM_D16__EMI_WEIM_D_16 0x118 0x460 0x000 0x0 0x0 -#define MX53_PAD_EIM_D16__GPIO3_16 0x118 0x460 0x000 0x1 0x0 -#define MX53_PAD_EIM_D16__IPU_DI0_PIN5 0x118 0x460 0x000 0x2 0x0 -#define MX53_PAD_EIM_D16__IPU_DISPB1_SER_CLK 0x118 0x460 0x000 0x3 0x0 -#define MX53_PAD_EIM_D16__ECSPI1_SCLK 0x118 0x460 0x79c 0x4 0x3 -#define MX53_PAD_EIM_D16__I2C2_SDA 0x118 0x460 0x820 0x5 0x1 -#define MX53_PAD_EIM_D17__EMI_WEIM_D_17 0x11c 0x464 0x000 0x0 0x0 -#define MX53_PAD_EIM_D17__GPIO3_17 0x11c 0x464 0x000 0x1 0x0 -#define MX53_PAD_EIM_D17__IPU_DI0_PIN6 0x11c 0x464 0x000 0x2 0x0 -#define MX53_PAD_EIM_D17__IPU_DISPB1_SER_DIN 0x11c 0x464 0x830 0x3 0x0 -#define MX53_PAD_EIM_D17__ECSPI1_MISO 0x11c 0x464 0x7a0 0x4 0x3 -#define MX53_PAD_EIM_D17__I2C3_SCL 0x11c 0x464 0x824 0x5 0x0 -#define MX53_PAD_EIM_D18__EMI_WEIM_D_18 0x120 0x468 0x000 0x0 0x0 -#define MX53_PAD_EIM_D18__GPIO3_18 0x120 0x468 0x000 0x1 0x0 -#define MX53_PAD_EIM_D18__IPU_DI0_PIN7 0x120 0x468 0x000 0x2 0x0 -#define MX53_PAD_EIM_D18__IPU_DISPB1_SER_DIO 0x120 0x468 0x830 0x3 0x1 -#define MX53_PAD_EIM_D18__ECSPI1_MOSI 0x120 0x468 0x7a4 0x4 0x3 -#define MX53_PAD_EIM_D18__I2C3_SDA 0x120 0x468 0x828 0x5 0x0 -#define MX53_PAD_EIM_D18__IPU_DI1_D0_CS 0x120 0x468 0x000 0x6 0x0 -#define MX53_PAD_EIM_D19__EMI_WEIM_D_19 0x124 0x46c 0x000 0x0 0x0 -#define MX53_PAD_EIM_D19__GPIO3_19 0x124 0x46c 0x000 0x1 0x0 -#define MX53_PAD_EIM_D19__IPU_DI0_PIN8 0x124 0x46c 0x000 0x2 0x0 -#define MX53_PAD_EIM_D19__IPU_DISPB1_SER_RS 0x124 0x46c 0x000 0x3 0x0 -#define MX53_PAD_EIM_D19__ECSPI1_SS1 0x124 0x46c 0x7ac 0x4 0x2 -#define MX53_PAD_EIM_D19__EPIT1_EPITO 0x124 0x46c 0x000 0x5 0x0 -#define MX53_PAD_EIM_D19__UART1_CTS 0x124 0x46c 0x000 0x6 0x0 -#define MX53_PAD_EIM_D19__USBOH3_USBH2_OC 0x124 0x46c 0x8a4 0x7 0x0 -#define MX53_PAD_EIM_D20__EMI_WEIM_D_20 0x128 0x470 0x000 0x0 0x0 -#define MX53_PAD_EIM_D20__GPIO3_20 0x128 0x470 0x000 0x1 0x0 -#define MX53_PAD_EIM_D20__IPU_DI0_PIN16 0x128 0x470 0x000 0x2 0x0 -#define MX53_PAD_EIM_D20__IPU_SER_DISP0_CS 0x128 0x470 0x000 0x3 0x0 -#define MX53_PAD_EIM_D20__CSPI_SS0 0x128 0x470 0x78c 0x4 0x1 -#define MX53_PAD_EIM_D20__EPIT2_EPITO 0x128 0x470 0x000 0x5 0x0 -#define MX53_PAD_EIM_D20__UART1_RTS 0x128 0x470 0x874 0x6 0x1 -#define MX53_PAD_EIM_D20__USBOH3_USBH2_PWR 0x128 0x470 0x000 0x7 0x0 -#define MX53_PAD_EIM_D21__EMI_WEIM_D_21 0x12c 0x474 0x000 0x0 0x0 -#define MX53_PAD_EIM_D21__GPIO3_21 0x12c 0x474 0x000 0x1 0x0 -#define MX53_PAD_EIM_D21__IPU_DI0_PIN17 0x12c 0x474 0x000 0x2 0x0 -#define MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK 0x12c 0x474 0x000 0x3 0x0 -#define MX53_PAD_EIM_D21__CSPI_SCLK 0x12c 0x474 0x780 0x4 0x1 -#define MX53_PAD_EIM_D21__I2C1_SCL 0x12c 0x474 0x814 0x5 0x1 -#define MX53_PAD_EIM_D21__USBOH3_USBOTG_OC 0x12c 0x474 0x89c 0x6 0x1 -#define MX53_PAD_EIM_D22__EMI_WEIM_D_22 0x130 0x478 0x000 0x0 0x0 -#define MX53_PAD_EIM_D22__GPIO3_22 0x130 0x478 0x000 0x1 0x0 -#define MX53_PAD_EIM_D22__IPU_DI0_PIN1 0x130 0x478 0x000 0x2 0x0 -#define MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN 0x130 0x478 0x82c 0x3 0x0 -#define MX53_PAD_EIM_D22__CSPI_MISO 0x130 0x478 0x784 0x4 0x1 -#define MX53_PAD_EIM_D22__USBOH3_USBOTG_PWR 0x130 0x478 0x000 0x6 0x0 -#define MX53_PAD_EIM_D23__EMI_WEIM_D_23 0x134 0x47c 0x000 0x0 0x0 -#define MX53_PAD_EIM_D23__GPIO3_23 0x134 0x47c 0x000 0x1 0x0 -#define MX53_PAD_EIM_D23__UART3_CTS 0x134 0x47c 0x000 0x2 0x0 -#define MX53_PAD_EIM_D23__UART1_DCD 0x134 0x47c 0x000 0x3 0x0 -#define MX53_PAD_EIM_D23__IPU_DI0_D0_CS 0x134 0x47c 0x000 0x4 0x0 -#define MX53_PAD_EIM_D23__IPU_DI1_PIN2 0x134 0x47c 0x000 0x5 0x0 -#define MX53_PAD_EIM_D23__IPU_CSI1_DATA_EN 0x134 0x47c 0x834 0x6 0x0 -#define MX53_PAD_EIM_D23__IPU_DI1_PIN14 0x134 0x47c 0x000 0x7 0x0 -#define MX53_PAD_EIM_EB3__EMI_WEIM_EB_3 0x138 0x480 0x000 0x0 0x0 -#define MX53_PAD_EIM_EB3__GPIO2_31 0x138 0x480 0x000 0x1 0x0 -#define MX53_PAD_EIM_EB3__UART3_RTS 0x138 0x480 0x884 0x2 0x1 -#define MX53_PAD_EIM_EB3__UART1_RI 0x138 0x480 0x000 0x3 0x0 -#define MX53_PAD_EIM_EB3__IPU_DI1_PIN3 0x138 0x480 0x000 0x5 0x0 -#define MX53_PAD_EIM_EB3__IPU_CSI1_HSYNC 0x138 0x480 0x838 0x6 0x0 -#define MX53_PAD_EIM_EB3__IPU_DI1_PIN16 0x138 0x480 0x000 0x7 0x0 -#define MX53_PAD_EIM_D24__EMI_WEIM_D_24 0x13c 0x484 0x000 0x0 0x0 -#define MX53_PAD_EIM_D24__GPIO3_24 0x13c 0x484 0x000 0x1 0x0 -#define MX53_PAD_EIM_D24__UART3_TXD_MUX 0x13c 0x484 0x000 0x2 0x0 -#define MX53_PAD_EIM_D24__ECSPI1_SS2 0x13c 0x484 0x7b0 0x3 0x1 -#define MX53_PAD_EIM_D24__CSPI_SS2 0x13c 0x484 0x794 0x4 0x1 -#define MX53_PAD_EIM_D24__AUDMUX_AUD5_RXFS 0x13c 0x484 0x754 0x5 0x1 -#define MX53_PAD_EIM_D24__ECSPI2_SS2 0x13c 0x484 0x000 0x6 0x0 -#define MX53_PAD_EIM_D24__UART1_DTR 0x13c 0x484 0x000 0x7 0x0 -#define MX53_PAD_EIM_D25__EMI_WEIM_D_25 0x140 0x488 0x000 0x0 0x0 -#define MX53_PAD_EIM_D25__GPIO3_25 0x140 0x488 0x000 0x1 0x0 -#define MX53_PAD_EIM_D25__UART3_RXD_MUX 0x140 0x488 0x888 0x2 0x1 -#define MX53_PAD_EIM_D25__ECSPI1_SS3 0x140 0x488 0x7b4 0x3 0x1 -#define MX53_PAD_EIM_D25__CSPI_SS3 0x140 0x488 0x798 0x4 0x1 -#define MX53_PAD_EIM_D25__AUDMUX_AUD5_RXC 0x140 0x488 0x750 0x5 0x1 -#define MX53_PAD_EIM_D25__ECSPI2_SS3 0x140 0x488 0x000 0x6 0x0 -#define MX53_PAD_EIM_D25__UART1_DSR 0x140 0x488 0x000 0x7 0x0 -#define MX53_PAD_EIM_D26__EMI_WEIM_D_26 0x144 0x48c 0x000 0x0 0x0 -#define MX53_PAD_EIM_D26__GPIO3_26 0x144 0x48c 0x000 0x1 0x0 -#define MX53_PAD_EIM_D26__UART2_RXD_MUX 0x144 0x48c 0x880 0x2 0x0 -#define MX53_PAD_EIM_D26__UART2_TXD_MUX 0x144 0x48c 0x000 0x2 0x0 -#define MX53_PAD_EIM_D26__FIRI_RXD 0x144 0x48c 0x80c 0x3 0x0 -#define MX53_PAD_EIM_D26__IPU_CSI0_D_1 0x144 0x48c 0x000 0x4 0x0 -#define MX53_PAD_EIM_D26__IPU_DI1_PIN11 0x144 0x48c 0x000 0x5 0x0 -#define MX53_PAD_EIM_D26__IPU_SISG_2 0x144 0x48c 0x000 0x6 0x0 -#define MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x144 0x48c 0x000 0x7 0x0 -#define MX53_PAD_EIM_D27__EMI_WEIM_D_27 0x148 0x490 0x000 0x0 0x0 -#define MX53_PAD_EIM_D27__GPIO3_27 0x148 0x490 0x000 0x1 0x0 -#define MX53_PAD_EIM_D27__UART2_RXD_MUX 0x148 0x490 0x880 0x2 0x1 -#define MX53_PAD_EIM_D27__UART2_TXD_MUX 0x148 0x490 0x000 0x2 0x0 -#define MX53_PAD_EIM_D27__FIRI_TXD 0x148 0x490 0x000 0x3 0x0 -#define MX53_PAD_EIM_D27__IPU_CSI0_D_0 0x148 0x490 0x000 0x4 0x0 -#define MX53_PAD_EIM_D27__IPU_DI1_PIN13 0x148 0x490 0x000 0x5 0x0 -#define MX53_PAD_EIM_D27__IPU_SISG_3 0x148 0x490 0x000 0x6 0x0 -#define MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x148 0x490 0x000 0x7 0x0 -#define MX53_PAD_EIM_D28__EMI_WEIM_D_28 0x14c 0x494 0x000 0x0 0x0 -#define MX53_PAD_EIM_D28__GPIO3_28 0x14c 0x494 0x000 0x1 0x0 -#define MX53_PAD_EIM_D28__UART2_CTS 0x14c 0x494 0x000 0x2 0x0 -#define MX53_PAD_EIM_D28__UART2_RTS 0x14c 0x494 0x87c 0x2 0x0 -#define MX53_PAD_EIM_D28__IPU_DISPB0_SER_DIO 0x14c 0x494 0x82c 0x3 0x1 -#define MX53_PAD_EIM_D28__CSPI_MOSI 0x14c 0x494 0x788 0x4 0x1 -#define MX53_PAD_EIM_D28__I2C1_SDA 0x14c 0x494 0x818 0x5 0x1 -#define MX53_PAD_EIM_D28__IPU_EXT_TRIG 0x14c 0x494 0x000 0x6 0x0 -#define MX53_PAD_EIM_D28__IPU_DI0_PIN13 0x14c 0x494 0x000 0x7 0x0 -#define MX53_PAD_EIM_D29__EMI_WEIM_D_29 0x150 0x498 0x000 0x0 0x0 -#define MX53_PAD_EIM_D29__GPIO3_29 0x150 0x498 0x000 0x1 0x0 -#define MX53_PAD_EIM_D29__UART2_CTS 0x150 0x498 0x000 0x2 0x0 -#define MX53_PAD_EIM_D29__UART2_RTS 0x150 0x498 0x87c 0x2 0x1 -#define MX53_PAD_EIM_D29__IPU_DISPB0_SER_RS 0x150 0x498 0x000 0x3 0x0 -#define MX53_PAD_EIM_D29__CSPI_SS0 0x150 0x498 0x78c 0x4 0x2 -#define MX53_PAD_EIM_D29__IPU_DI1_PIN15 0x150 0x498 0x000 0x5 0x0 -#define MX53_PAD_EIM_D29__IPU_CSI1_VSYNC 0x150 0x498 0x83c 0x6 0x0 -#define MX53_PAD_EIM_D29__IPU_DI0_PIN14 0x150 0x498 0x000 0x7 0x0 -#define MX53_PAD_EIM_D30__EMI_WEIM_D_30 0x154 0x49c 0x000 0x0 0x0 -#define MX53_PAD_EIM_D30__GPIO3_30 0x154 0x49c 0x000 0x1 0x0 -#define MX53_PAD_EIM_D30__UART3_CTS 0x154 0x49c 0x000 0x2 0x0 -#define MX53_PAD_EIM_D30__IPU_CSI0_D_3 0x154 0x49c 0x000 0x3 0x0 -#define MX53_PAD_EIM_D30__IPU_DI0_PIN11 0x154 0x49c 0x000 0x4 0x0 -#define MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x154 0x49c 0x000 0x5 0x0 -#define MX53_PAD_EIM_D30__USBOH3_USBH1_OC 0x154 0x49c 0x8a0 0x6 0x0 -#define MX53_PAD_EIM_D30__USBOH3_USBH2_OC 0x154 0x49c 0x8a4 0x7 0x1 -#define MX53_PAD_EIM_D31__EMI_WEIM_D_31 0x158 0x4a0 0x000 0x0 0x0 -#define MX53_PAD_EIM_D31__GPIO3_31 0x158 0x4a0 0x000 0x1 0x0 -#define MX53_PAD_EIM_D31__UART3_RTS 0x158 0x4a0 0x884 0x2 0x3 -#define MX53_PAD_EIM_D31__IPU_CSI0_D_2 0x158 0x4a0 0x000 0x3 0x0 -#define MX53_PAD_EIM_D31__IPU_DI0_PIN12 0x158 0x4a0 0x000 0x4 0x0 -#define MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x158 0x4a0 0x000 0x5 0x0 -#define MX53_PAD_EIM_D31__USBOH3_USBH1_PWR 0x158 0x4a0 0x000 0x6 0x0 -#define MX53_PAD_EIM_D31__USBOH3_USBH2_PWR 0x158 0x4a0 0x000 0x7 0x0 -#define MX53_PAD_EIM_A24__EMI_WEIM_A_24 0x15c 0x4a8 0x000 0x0 0x0 -#define MX53_PAD_EIM_A24__GPIO5_4 0x15c 0x4a8 0x000 0x1 0x0 -#define MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x15c 0x4a8 0x000 0x2 0x0 -#define MX53_PAD_EIM_A24__IPU_CSI1_D_19 0x15c 0x4a8 0x000 0x3 0x0 -#define MX53_PAD_EIM_A24__IPU_SISG_2 0x15c 0x4a8 0x000 0x6 0x0 -#define MX53_PAD_EIM_A24__USBPHY2_BVALID 0x15c 0x4a8 0x000 0x7 0x0 -#define MX53_PAD_EIM_A23__EMI_WEIM_A_23 0x160 0x4ac 0x000 0x0 0x0 -#define MX53_PAD_EIM_A23__GPIO6_6 0x160 0x4ac 0x000 0x1 0x0 -#define MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x160 0x4ac 0x000 0x2 0x0 -#define MX53_PAD_EIM_A23__IPU_CSI1_D_18 0x160 0x4ac 0x000 0x3 0x0 -#define MX53_PAD_EIM_A23__IPU_SISG_3 0x160 0x4ac 0x000 0x6 0x0 -#define MX53_PAD_EIM_A23__USBPHY2_ENDSESSION 0x160 0x4ac 0x000 0x7 0x0 -#define MX53_PAD_EIM_A22__EMI_WEIM_A_22 0x164 0x4b0 0x000 0x0 0x0 -#define MX53_PAD_EIM_A22__GPIO2_16 0x164 0x4b0 0x000 0x1 0x0 -#define MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x164 0x4b0 0x000 0x2 0x0 -#define MX53_PAD_EIM_A22__IPU_CSI1_D_17 0x164 0x4b0 0x000 0x3 0x0 -#define MX53_PAD_EIM_A22__SRC_BT_CFG1_7 0x164 0x4b0 0x000 0x7 0x0 -#define MX53_PAD_EIM_A21__EMI_WEIM_A_21 0x168 0x4b4 0x000 0x0 0x0 -#define MX53_PAD_EIM_A21__GPIO2_17 0x168 0x4b4 0x000 0x1 0x0 -#define MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x168 0x4b4 0x000 0x2 0x0 -#define MX53_PAD_EIM_A21__IPU_CSI1_D_16 0x168 0x4b4 0x000 0x3 0x0 -#define MX53_PAD_EIM_A21__SRC_BT_CFG1_6 0x168 0x4b4 0x000 0x7 0x0 -#define MX53_PAD_EIM_A20__EMI_WEIM_A_20 0x16c 0x4b8 0x000 0x0 0x0 -#define MX53_PAD_EIM_A20__GPIO2_18 0x16c 0x4b8 0x000 0x1 0x0 -#define MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x16c 0x4b8 0x000 0x2 0x0 -#define MX53_PAD_EIM_A20__IPU_CSI1_D_15 0x16c 0x4b8 0x000 0x3 0x0 -#define MX53_PAD_EIM_A20__SRC_BT_CFG1_5 0x16c 0x4b8 0x000 0x7 0x0 -#define MX53_PAD_EIM_A19__EMI_WEIM_A_19 0x170 0x4bc 0x000 0x0 0x0 -#define MX53_PAD_EIM_A19__GPIO2_19 0x170 0x4bc 0x000 0x1 0x0 -#define MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x170 0x4bc 0x000 0x2 0x0 -#define MX53_PAD_EIM_A19__IPU_CSI1_D_14 0x170 0x4bc 0x000 0x3 0x0 -#define MX53_PAD_EIM_A19__SRC_BT_CFG1_4 0x170 0x4bc 0x000 0x7 0x0 -#define MX53_PAD_EIM_A18__EMI_WEIM_A_18 0x174 0x4c0 0x000 0x0 0x0 -#define MX53_PAD_EIM_A18__GPIO2_20 0x174 0x4c0 0x000 0x1 0x0 -#define MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x174 0x4c0 0x000 0x2 0x0 -#define MX53_PAD_EIM_A18__IPU_CSI1_D_13 0x174 0x4c0 0x000 0x3 0x0 -#define MX53_PAD_EIM_A18__SRC_BT_CFG1_3 0x174 0x4c0 0x000 0x7 0x0 -#define MX53_PAD_EIM_A17__EMI_WEIM_A_17 0x178 0x4c4 0x000 0x0 0x0 -#define MX53_PAD_EIM_A17__GPIO2_21 0x178 0x4c4 0x000 0x1 0x0 -#define MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x178 0x4c4 0x000 0x2 0x0 -#define MX53_PAD_EIM_A17__IPU_CSI1_D_12 0x178 0x4c4 0x000 0x3 0x0 -#define MX53_PAD_EIM_A17__SRC_BT_CFG1_2 0x178 0x4c4 0x000 0x7 0x0 -#define MX53_PAD_EIM_A16__EMI_WEIM_A_16 0x17c 0x4c8 0x000 0x0 0x0 -#define MX53_PAD_EIM_A16__GPIO2_22 0x17c 0x4c8 0x000 0x1 0x0 -#define MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x17c 0x4c8 0x000 0x2 0x0 -#define MX53_PAD_EIM_A16__IPU_CSI1_PIXCLK 0x17c 0x4c8 0x000 0x3 0x0 -#define MX53_PAD_EIM_A16__SRC_BT_CFG1_1 0x17c 0x4c8 0x000 0x7 0x0 -#define MX53_PAD_EIM_CS0__EMI_WEIM_CS_0 0x180 0x4cc 0x000 0x0 0x0 -#define MX53_PAD_EIM_CS0__GPIO2_23 0x180 0x4cc 0x000 0x1 0x0 -#define MX53_PAD_EIM_CS0__ECSPI2_SCLK 0x180 0x4cc 0x7b8 0x2 0x2 -#define MX53_PAD_EIM_CS0__IPU_DI1_PIN5 0x180 0x4cc 0x000 0x3 0x0 -#define MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 0x184 0x4d0 0x000 0x0 0x0 -#define MX53_PAD_EIM_CS1__GPIO2_24 0x184 0x4d0 0x000 0x1 0x0 -#define MX53_PAD_EIM_CS1__ECSPI2_MOSI 0x184 0x4d0 0x7c0 0x2 0x2 -#define MX53_PAD_EIM_CS1__IPU_DI1_PIN6 0x184 0x4d0 0x000 0x3 0x0 -#define MX53_PAD_EIM_OE__EMI_WEIM_OE 0x188 0x4d4 0x000 0x0 0x0 -#define MX53_PAD_EIM_OE__GPIO2_25 0x188 0x4d4 0x000 0x1 0x0 -#define MX53_PAD_EIM_OE__ECSPI2_MISO 0x188 0x4d4 0x7bc 0x2 0x2 -#define MX53_PAD_EIM_OE__IPU_DI1_PIN7 0x188 0x4d4 0x000 0x3 0x0 -#define MX53_PAD_EIM_OE__USBPHY2_IDDIG 0x188 0x4d4 0x000 0x7 0x0 -#define MX53_PAD_EIM_RW__EMI_WEIM_RW 0x18c 0x4d8 0x000 0x0 0x0 -#define MX53_PAD_EIM_RW__GPIO2_26 0x18c 0x4d8 0x000 0x1 0x0 -#define MX53_PAD_EIM_RW__ECSPI2_SS0 0x18c 0x4d8 0x7c4 0x2 0x2 -#define MX53_PAD_EIM_RW__IPU_DI1_PIN8 0x18c 0x4d8 0x000 0x3 0x0 -#define MX53_PAD_EIM_RW__USBPHY2_HOSTDISCONNECT 0x18c 0x4d8 0x000 0x7 0x0 -#define MX53_PAD_EIM_LBA__EMI_WEIM_LBA 0x190 0x4dc 0x000 0x0 0x0 -#define MX53_PAD_EIM_LBA__GPIO2_27 0x190 0x4dc 0x000 0x1 0x0 -#define MX53_PAD_EIM_LBA__ECSPI2_SS1 0x190 0x4dc 0x7c8 0x2 0x1 -#define MX53_PAD_EIM_LBA__IPU_DI1_PIN17 0x190 0x4dc 0x000 0x3 0x0 -#define MX53_PAD_EIM_LBA__SRC_BT_CFG1_0 0x190 0x4dc 0x000 0x7 0x0 -#define MX53_PAD_EIM_EB0__EMI_WEIM_EB_0 0x194 0x4e4 0x000 0x0 0x0 -#define MX53_PAD_EIM_EB0__GPIO2_28 0x194 0x4e4 0x000 0x1 0x0 -#define MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x194 0x4e4 0x000 0x3 0x0 -#define MX53_PAD_EIM_EB0__IPU_CSI1_D_11 0x194 0x4e4 0x000 0x4 0x0 -#define MX53_PAD_EIM_EB0__GPC_PMIC_RDY 0x194 0x4e4 0x810 0x5 0x0 -#define MX53_PAD_EIM_EB0__SRC_BT_CFG2_7 0x194 0x4e4 0x000 0x7 0x0 -#define MX53_PAD_EIM_EB1__EMI_WEIM_EB_1 0x198 0x4e8 0x000 0x0 0x0 -#define MX53_PAD_EIM_EB1__GPIO2_29 0x198 0x4e8 0x000 0x1 0x0 -#define MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x198 0x4e8 0x000 0x3 0x0 -#define MX53_PAD_EIM_EB1__IPU_CSI1_D_10 0x198 0x4e8 0x000 0x4 0x0 -#define MX53_PAD_EIM_EB1__SRC_BT_CFG2_6 0x198 0x4e8 0x000 0x7 0x0 -#define MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 0x19c 0x4ec 0x000 0x0 0x0 -#define MX53_PAD_EIM_DA0__GPIO3_0 0x19c 0x4ec 0x000 0x1 0x0 -#define MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x19c 0x4ec 0x000 0x3 0x0 -#define MX53_PAD_EIM_DA0__IPU_CSI1_D_9 0x19c 0x4ec 0x000 0x4 0x0 -#define MX53_PAD_EIM_DA0__SRC_BT_CFG2_5 0x19c 0x4ec 0x000 0x7 0x0 -#define MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 0x1a0 0x4f0 0x000 0x0 0x0 -#define MX53_PAD_EIM_DA1__GPIO3_1 0x1a0 0x4f0 0x000 0x1 0x0 -#define MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x1a0 0x4f0 0x000 0x3 0x0 -#define MX53_PAD_EIM_DA1__IPU_CSI1_D_8 0x1a0 0x4f0 0x000 0x4 0x0 -#define MX53_PAD_EIM_DA1__SRC_BT_CFG2_4 0x1a0 0x4f0 0x000 0x7 0x0 -#define MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 0x1a4 0x4f4 0x000 0x0 0x0 -#define MX53_PAD_EIM_DA2__GPIO3_2 0x1a4 0x4f4 0x000 0x1 0x0 -#define MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x1a4 0x4f4 0x000 0x3 0x0 -#define MX53_PAD_EIM_DA2__IPU_CSI1_D_7 0x1a4 0x4f4 0x000 0x4 0x0 -#define MX53_PAD_EIM_DA2__SRC_BT_CFG2_3 0x1a4 0x4f4 0x000 0x7 0x0 -#define MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 0x1a8 0x4f8 0x000 0x0 0x0 -#define MX53_PAD_EIM_DA3__GPIO3_3 0x1a8 0x4f8 0x000 0x1 0x0 -#define MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x1a8 0x4f8 0x000 0x3 0x0 -#define MX53_PAD_EIM_DA3__IPU_CSI1_D_6 0x1a8 0x4f8 0x000 0x4 0x0 -#define MX53_PAD_EIM_DA3__SRC_BT_CFG2_2 0x1a8 0x4f8 0x000 0x7 0x0 -#define MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 0x1ac 0x4fc 0x000 0x0 0x0 -#define MX53_PAD_EIM_DA4__GPIO3_4 0x1ac 0x4fc 0x000 0x1 0x0 -#define MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x1ac 0x4fc 0x000 0x3 0x0 -#define MX53_PAD_EIM_DA4__IPU_CSI1_D_5 0x1ac 0x4fc 0x000 0x4 0x0 -#define MX53_PAD_EIM_DA4__SRC_BT_CFG3_7 0x1ac 0x4fc 0x000 0x7 0x0 -#define MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 0x1b0 0x500 0x000 0x0 0x0 -#define MX53_PAD_EIM_DA5__GPIO3_5 0x1b0 0x500 0x000 0x1 0x0 -#define MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x1b0 0x500 0x000 0x3 0x0 -#define MX53_PAD_EIM_DA5__IPU_CSI1_D_4 0x1b0 0x500 0x000 0x4 0x0 -#define MX53_PAD_EIM_DA5__SRC_BT_CFG3_6 0x1b0 0x500 0x000 0x7 0x0 -#define MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 0x1b4 0x504 0x000 0x0 0x0 -#define MX53_PAD_EIM_DA6__GPIO3_6 0x1b4 0x504 0x000 0x1 0x0 -#define MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x1b4 0x504 0x000 0x3 0x0 -#define MX53_PAD_EIM_DA6__IPU_CSI1_D_3 0x1b4 0x504 0x000 0x4 0x0 -#define MX53_PAD_EIM_DA6__SRC_BT_CFG3_5 0x1b4 0x504 0x000 0x7 0x0 -#define MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7 0x1b8 0x508 0x000 0x0 0x0 -#define MX53_PAD_EIM_DA7__GPIO3_7 0x1b8 0x508 0x000 0x1 0x0 -#define MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x1b8 0x508 0x000 0x3 0x0 -#define MX53_PAD_EIM_DA7__IPU_CSI1_D_2 0x1b8 0x508 0x000 0x4 0x0 -#define MX53_PAD_EIM_DA7__SRC_BT_CFG3_4 0x1b8 0x508 0x000 0x7 0x0 -#define MX53_PAD_EIM_DA8__EMI_NAND_WEIM_DA_8 0x1bc 0x50c 0x000 0x0 0x0 -#define MX53_PAD_EIM_DA8__GPIO3_8 0x1bc 0x50c 0x000 0x1 0x0 -#define MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x1bc 0x50c 0x000 0x3 0x0 -#define MX53_PAD_EIM_DA8__IPU_CSI1_D_1 0x1bc 0x50c 0x000 0x4 0x0 -#define MX53_PAD_EIM_DA8__SRC_BT_CFG3_3 0x1bc 0x50c 0x000 0x7 0x0 -#define MX53_PAD_EIM_DA9__EMI_NAND_WEIM_DA_9 0x1c0 0x510 0x000 0x0 0x0 -#define MX53_PAD_EIM_DA9__GPIO3_9 0x1c0 0x510 0x000 0x1 0x0 -#define MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x1c0 0x510 0x000 0x3 0x0 -#define MX53_PAD_EIM_DA9__IPU_CSI1_D_0 0x1c0 0x510 0x000 0x4 0x0 -#define MX53_PAD_EIM_DA9__SRC_BT_CFG3_2 0x1c0 0x510 0x000 0x7 0x0 -#define MX53_PAD_EIM_DA10__EMI_NAND_WEIM_DA_10 0x1c4 0x514 0x000 0x0 0x0 -#define MX53_PAD_EIM_DA10__GPIO3_10 0x1c4 0x514 0x000 0x1 0x0 -#define MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x1c4 0x514 0x000 0x3 0x0 -#define MX53_PAD_EIM_DA10__IPU_CSI1_DATA_EN 0x1c4 0x514 0x834 0x4 0x1 -#define MX53_PAD_EIM_DA10__SRC_BT_CFG3_1 0x1c4 0x514 0x000 0x7 0x0 -#define MX53_PAD_EIM_DA11__EMI_NAND_WEIM_DA_11 0x1c8 0x518 0x000 0x0 0x0 -#define MX53_PAD_EIM_DA11__GPIO3_11 0x1c8 0x518 0x000 0x1 0x0 -#define MX53_PAD_EIM_DA11__IPU_DI1_PIN2 0x1c8 0x518 0x000 0x3 0x0 -#define MX53_PAD_EIM_DA11__IPU_CSI1_HSYNC 0x1c8 0x518 0x838 0x4 0x1 -#define MX53_PAD_EIM_DA12__EMI_NAND_WEIM_DA_12 0x1cc 0x51c 0x000 0x0 0x0 -#define MX53_PAD_EIM_DA12__GPIO3_12 0x1cc 0x51c 0x000 0x1 0x0 -#define MX53_PAD_EIM_DA12__IPU_DI1_PIN3 0x1cc 0x51c 0x000 0x3 0x0 -#define MX53_PAD_EIM_DA12__IPU_CSI1_VSYNC 0x1cc 0x51c 0x83c 0x4 0x1 -#define MX53_PAD_EIM_DA13__EMI_NAND_WEIM_DA_13 0x1d0 0x520 0x000 0x0 0x0 -#define MX53_PAD_EIM_DA13__GPIO3_13 0x1d0 0x520 0x000 0x1 0x0 -#define MX53_PAD_EIM_DA13__IPU_DI1_D0_CS 0x1d0 0x520 0x000 0x3 0x0 -#define MX53_PAD_EIM_DA13__CCM_DI1_EXT_CLK 0x1d0 0x520 0x76c 0x4 0x1 -#define MX53_PAD_EIM_DA14__EMI_NAND_WEIM_DA_14 0x1d4 0x524 0x000 0x0 0x0 -#define MX53_PAD_EIM_DA14__GPIO3_14 0x1d4 0x524 0x000 0x1 0x0 -#define MX53_PAD_EIM_DA14__IPU_DI1_D1_CS 0x1d4 0x524 0x000 0x3 0x0 -#define MX53_PAD_EIM_DA14__CCM_DI0_EXT_CLK 0x1d4 0x524 0x000 0x4 0x0 -#define MX53_PAD_EIM_DA15__EMI_NAND_WEIM_DA_15 0x1d8 0x528 0x000 0x0 0x0 -#define MX53_PAD_EIM_DA15__GPIO3_15 0x1d8 0x528 0x000 0x1 0x0 -#define MX53_PAD_EIM_DA15__IPU_DI1_PIN1 0x1d8 0x528 0x000 0x3 0x0 -#define MX53_PAD_EIM_DA15__IPU_DI1_PIN4 0x1d8 0x528 0x000 0x4 0x0 -#define MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 0x1dc 0x52c 0x000 0x0 0x0 -#define MX53_PAD_NANDF_WE_B__GPIO6_12 0x1dc 0x52c 0x000 0x1 0x0 -#define MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 0x1e0 0x530 0x000 0x0 0x0 -#define MX53_PAD_NANDF_RE_B__GPIO6_13 0x1e0 0x530 0x000 0x1 0x0 -#define MX53_PAD_EIM_WAIT__EMI_WEIM_WAIT 0x1e4 0x534 0x000 0x0 0x0 -#define MX53_PAD_EIM_WAIT__GPIO5_0 0x1e4 0x534 0x000 0x1 0x0 -#define MX53_PAD_EIM_WAIT__EMI_WEIM_DTACK_B 0x1e4 0x534 0x000 0x2 0x0 -#define MX53_PAD_LVDS1_TX3_P__GPIO6_22 0x1ec 0x000 0x000 0x0 0x0 -#define MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x1ec 0x000 0x000 0x1 0x0 -#define MX53_PAD_LVDS1_TX2_P__GPIO6_24 0x1f0 0x000 0x000 0x0 0x0 -#define MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x1f0 0x000 0x000 0x1 0x0 -#define MX53_PAD_LVDS1_CLK_P__GPIO6_26 0x1f4 0x000 0x000 0x0 0x0 -#define MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x1f4 0x000 0x000 0x1 0x0 -#define MX53_PAD_LVDS1_TX1_P__GPIO6_28 0x1f8 0x000 0x000 0x0 0x0 -#define MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x1f8 0x000 0x000 0x1 0x0 -#define MX53_PAD_LVDS1_TX0_P__GPIO6_30 0x1fc 0x000 0x000 0x0 0x0 -#define MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x1fc 0x000 0x000 0x1 0x0 -#define MX53_PAD_LVDS0_TX3_P__GPIO7_22 0x200 0x000 0x000 0x0 0x0 -#define MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x200 0x000 0x000 0x1 0x0 -#define MX53_PAD_LVDS0_CLK_P__GPIO7_24 0x204 0x000 0x000 0x0 0x0 -#define MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x204 0x000 0x000 0x1 0x0 -#define MX53_PAD_LVDS0_TX2_P__GPIO7_26 0x208 0x000 0x000 0x0 0x0 -#define MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x208 0x000 0x000 0x1 0x0 -#define MX53_PAD_LVDS0_TX1_P__GPIO7_28 0x20c 0x000 0x000 0x0 0x0 -#define MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x20c 0x000 0x000 0x1 0x0 -#define MX53_PAD_LVDS0_TX0_P__GPIO7_30 0x210 0x000 0x000 0x0 0x0 -#define MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x210 0x000 0x000 0x1 0x0 -#define MX53_PAD_GPIO_10__GPIO4_0 0x214 0x540 0x000 0x0 0x0 -#define MX53_PAD_GPIO_10__OSC32k_32K_OUT 0x214 0x540 0x000 0x1 0x0 -#define MX53_PAD_GPIO_11__GPIO4_1 0x218 0x544 0x000 0x0 0x0 -#define MX53_PAD_GPIO_12__GPIO4_2 0x21c 0x548 0x000 0x0 0x0 -#define MX53_PAD_GPIO_13__GPIO4_3 0x220 0x54c 0x000 0x0 0x0 -#define MX53_PAD_GPIO_14__GPIO4_4 0x224 0x550 0x000 0x0 0x0 -#define MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 0x228 0x5a0 0x000 0x0 0x0 -#define MX53_PAD_NANDF_CLE__GPIO6_7 0x228 0x5a0 0x000 0x1 0x0 -#define MX53_PAD_NANDF_CLE__USBPHY1_VSTATUS_0 0x228 0x5a0 0x000 0x7 0x0 -#define MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 0x22c 0x5a4 0x000 0x0 0x0 -#define MX53_PAD_NANDF_ALE__GPIO6_8 0x22c 0x5a4 0x000 0x1 0x0 -#define MX53_PAD_NANDF_ALE__USBPHY1_VSTATUS_1 0x22c 0x5a4 0x000 0x7 0x0 -#define MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 0x230 0x5a8 0x000 0x0 0x0 -#define MX53_PAD_NANDF_WP_B__GPIO6_9 0x230 0x5a8 0x000 0x1 0x0 -#define MX53_PAD_NANDF_WP_B__USBPHY1_VSTATUS_2 0x230 0x5a8 0x000 0x7 0x0 -#define MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 0x234 0x5ac 0x000 0x0 0x0 -#define MX53_PAD_NANDF_RB0__GPIO6_10 0x234 0x5ac 0x000 0x1 0x0 -#define MX53_PAD_NANDF_RB0__USBPHY1_VSTATUS_3 0x234 0x5ac 0x000 0x7 0x0 -#define MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 0x238 0x5b0 0x000 0x0 0x0 -#define MX53_PAD_NANDF_CS0__GPIO6_11 0x238 0x5b0 0x000 0x1 0x0 -#define MX53_PAD_NANDF_CS0__USBPHY1_VSTATUS_4 0x238 0x5b0 0x000 0x7 0x0 -#define MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1 0x23c 0x5b4 0x000 0x0 0x0 -#define MX53_PAD_NANDF_CS1__GPIO6_14 0x23c 0x5b4 0x000 0x1 0x0 -#define MX53_PAD_NANDF_CS1__MLB_MLBCLK 0x23c 0x5b4 0x858 0x6 0x0 -#define MX53_PAD_NANDF_CS1__USBPHY1_VSTATUS_5 0x23c 0x5b4 0x000 0x7 0x0 -#define MX53_PAD_NANDF_CS2__EMI_NANDF_CS_2 0x240 0x5b8 0x000 0x0 0x0 -#define MX53_PAD_NANDF_CS2__GPIO6_15 0x240 0x5b8 0x000 0x1 0x0 -#define MX53_PAD_NANDF_CS2__IPU_SISG_0 0x240 0x5b8 0x000 0x2 0x0 -#define MX53_PAD_NANDF_CS2__ESAI1_TX0 0x240 0x5b8 0x7e4 0x3 0x0 -#define MX53_PAD_NANDF_CS2__EMI_WEIM_CRE 0x240 0x5b8 0x000 0x4 0x0 -#define MX53_PAD_NANDF_CS2__CCM_CSI0_MCLK 0x240 0x5b8 0x000 0x5 0x0 -#define MX53_PAD_NANDF_CS2__MLB_MLBSIG 0x240 0x5b8 0x860 0x6 0x0 -#define MX53_PAD_NANDF_CS2__USBPHY1_VSTATUS_6 0x240 0x5b8 0x000 0x7 0x0 -#define MX53_PAD_NANDF_CS3__EMI_NANDF_CS_3 0x244 0x5bc 0x000 0x0 0x0 -#define MX53_PAD_NANDF_CS3__GPIO6_16 0x244 0x5bc 0x000 0x1 0x0 -#define MX53_PAD_NANDF_CS3__IPU_SISG_1 0x244 0x5bc 0x000 0x2 0x0 -#define MX53_PAD_NANDF_CS3__ESAI1_TX1 0x244 0x5bc 0x7e8 0x3 0x0 -#define MX53_PAD_NANDF_CS3__EMI_WEIM_A_26 0x244 0x5bc 0x000 0x4 0x0 -#define MX53_PAD_NANDF_CS3__MLB_MLBDAT 0x244 0x5bc 0x85c 0x6 0x0 -#define MX53_PAD_NANDF_CS3__USBPHY1_VSTATUS_7 0x244 0x5bc 0x000 0x7 0x0 -#define MX53_PAD_FEC_MDIO__FEC_MDIO 0x248 0x5c4 0x804 0x0 0x1 -#define MX53_PAD_FEC_MDIO__GPIO1_22 0x248 0x5c4 0x000 0x1 0x0 -#define MX53_PAD_FEC_MDIO__ESAI1_SCKR 0x248 0x5c4 0x7dc 0x2 0x0 -#define MX53_PAD_FEC_MDIO__FEC_COL 0x248 0x5c4 0x800 0x3 0x1 -#define MX53_PAD_FEC_MDIO__RTC_CE_RTC_PS2 0x248 0x5c4 0x000 0x4 0x0 -#define MX53_PAD_FEC_MDIO__SDMA_DEBUG_BUS_DEVICE_3 0x248 0x5c4 0x000 0x5 0x0 -#define MX53_PAD_FEC_MDIO__EMI_EMI_DEBUG_49 0x248 0x5c4 0x000 0x6 0x0 -#define MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x24c 0x5c8 0x000 0x0 0x0 -#define MX53_PAD_FEC_REF_CLK__GPIO1_23 0x24c 0x5c8 0x000 0x1 0x0 -#define MX53_PAD_FEC_REF_CLK__ESAI1_FSR 0x24c 0x5c8 0x7cc 0x2 0x0 -#define MX53_PAD_FEC_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 0x24c 0x5c8 0x000 0x5 0x0 -#define MX53_PAD_FEC_REF_CLK__EMI_EMI_DEBUG_50 0x24c 0x5c8 0x000 0x6 0x0 -#define MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x250 0x5cc 0x000 0x0 0x0 -#define MX53_PAD_FEC_RX_ER__GPIO1_24 0x250 0x5cc 0x000 0x1 0x0 -#define MX53_PAD_FEC_RX_ER__ESAI1_HCKR 0x250 0x5cc 0x7d4 0x2 0x0 -#define MX53_PAD_FEC_RX_ER__FEC_RX_CLK 0x250 0x5cc 0x808 0x3 0x1 -#define MX53_PAD_FEC_RX_ER__RTC_CE_RTC_PS3 0x250 0x5cc 0x000 0x4 0x0 -#define MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x254 0x5d0 0x000 0x0 0x0 -#define MX53_PAD_FEC_CRS_DV__GPIO1_25 0x254 0x5d0 0x000 0x1 0x0 -#define MX53_PAD_FEC_CRS_DV__ESAI1_SCKT 0x254 0x5d0 0x7e0 0x2 0x0 -#define MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x258 0x5d4 0x000 0x0 0x0 -#define MX53_PAD_FEC_RXD1__GPIO1_26 0x258 0x5d4 0x000 0x1 0x0 -#define MX53_PAD_FEC_RXD1__ESAI1_FST 0x258 0x5d4 0x7d0 0x2 0x0 -#define MX53_PAD_FEC_RXD1__MLB_MLBSIG 0x258 0x5d4 0x860 0x3 0x1 -#define MX53_PAD_FEC_RXD1__RTC_CE_RTC_PS1 0x258 0x5d4 0x000 0x4 0x0 -#define MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x25c 0x5d8 0x000 0x0 0x0 -#define MX53_PAD_FEC_RXD0__GPIO1_27 0x25c 0x5d8 0x000 0x1 0x0 -#define MX53_PAD_FEC_RXD0__ESAI1_HCKT 0x25c 0x5d8 0x7d8 0x2 0x0 -#define MX53_PAD_FEC_RXD0__OSC32k_32K_OUT 0x25c 0x5d8 0x000 0x3 0x0 -#define MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x260 0x5dc 0x000 0x0 0x0 -#define MX53_PAD_FEC_TX_EN__GPIO1_28 0x260 0x5dc 0x000 0x1 0x0 -#define MX53_PAD_FEC_TX_EN__ESAI1_TX3_RX2 0x260 0x5dc 0x7f0 0x2 0x0 -#define MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x264 0x5e0 0x000 0x0 0x0 -#define MX53_PAD_FEC_TXD1__GPIO1_29 0x264 0x5e0 0x000 0x1 0x0 -#define MX53_PAD_FEC_TXD1__ESAI1_TX2_RX3 0x264 0x5e0 0x7ec 0x2 0x0 -#define MX53_PAD_FEC_TXD1__MLB_MLBCLK 0x264 0x5e0 0x858 0x3 0x1 -#define MX53_PAD_FEC_TXD1__RTC_CE_RTC_PRSC_CLK 0x264 0x5e0 0x000 0x4 0x0 -#define MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x268 0x5e4 0x000 0x0 0x0 -#define MX53_PAD_FEC_TXD0__GPIO1_30 0x268 0x5e4 0x000 0x1 0x0 -#define MX53_PAD_FEC_TXD0__ESAI1_TX4_RX1 0x268 0x5e4 0x7f4 0x2 0x0 -#define MX53_PAD_FEC_TXD0__USBPHY2_DATAOUT_0 0x268 0x5e4 0x000 0x7 0x0 -#define MX53_PAD_FEC_MDC__FEC_MDC 0x26c 0x5e8 0x000 0x0 0x0 -#define MX53_PAD_FEC_MDC__GPIO1_31 0x26c 0x5e8 0x000 0x1 0x0 -#define MX53_PAD_FEC_MDC__ESAI1_TX5_RX0 0x26c 0x5e8 0x7f8 0x2 0x0 -#define MX53_PAD_FEC_MDC__MLB_MLBDAT 0x26c 0x5e8 0x85c 0x3 0x1 -#define MX53_PAD_FEC_MDC__RTC_CE_RTC_ALARM1_TRIG 0x26c 0x5e8 0x000 0x4 0x0 -#define MX53_PAD_FEC_MDC__USBPHY2_DATAOUT_1 0x26c 0x5e8 0x000 0x7 0x0 -#define MX53_PAD_PATA_DIOW__PATA_DIOW 0x270 0x5f0 0x000 0x0 0x0 -#define MX53_PAD_PATA_DIOW__GPIO6_17 0x270 0x5f0 0x000 0x1 0x0 -#define MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x270 0x5f0 0x000 0x3 0x0 -#define MX53_PAD_PATA_DIOW__USBPHY2_DATAOUT_2 0x270 0x5f0 0x000 0x7 0x0 -#define MX53_PAD_PATA_DMACK__PATA_DMACK 0x274 0x5f4 0x000 0x0 0x0 -#define MX53_PAD_PATA_DMACK__GPIO6_18 0x274 0x5f4 0x000 0x1 0x0 -#define MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x274 0x5f4 0x878 0x3 0x3 -#define MX53_PAD_PATA_DMACK__USBPHY2_DATAOUT_3 0x274 0x5f4 0x000 0x7 0x0 -#define MX53_PAD_PATA_DMARQ__PATA_DMARQ 0x278 0x5f8 0x000 0x0 0x0 -#define MX53_PAD_PATA_DMARQ__GPIO7_0 0x278 0x5f8 0x000 0x1 0x0 -#define MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x278 0x5f8 0x000 0x3 0x0 -#define MX53_PAD_PATA_DMARQ__CCM_CCM_OUT_0 0x278 0x5f8 0x000 0x5 0x0 -#define MX53_PAD_PATA_DMARQ__USBPHY2_DATAOUT_4 0x278 0x5f8 0x000 0x7 0x0 -#define MX53_PAD_PATA_BUFFER_EN__PATA_BUFFER_EN 0x27c 0x5fc 0x000 0x0 0x0 -#define MX53_PAD_PATA_BUFFER_EN__GPIO7_1 0x27c 0x5fc 0x000 0x1 0x0 -#define MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x27c 0x5fc 0x880 0x3 0x3 -#define MX53_PAD_PATA_BUFFER_EN__CCM_CCM_OUT_1 0x27c 0x5fc 0x000 0x5 0x0 -#define MX53_PAD_PATA_BUFFER_EN__USBPHY2_DATAOUT_5 0x27c 0x5fc 0x000 0x7 0x0 -#define MX53_PAD_PATA_INTRQ__PATA_INTRQ 0x280 0x600 0x000 0x0 0x0 -#define MX53_PAD_PATA_INTRQ__GPIO7_2 0x280 0x600 0x000 0x1 0x0 -#define MX53_PAD_PATA_INTRQ__UART2_CTS 0x280 0x600 0x000 0x3 0x0 -#define MX53_PAD_PATA_INTRQ__CAN1_TXCAN 0x280 0x600 0x000 0x4 0x0 -#define MX53_PAD_PATA_INTRQ__CCM_CCM_OUT_2 0x280 0x600 0x000 0x5 0x0 -#define MX53_PAD_PATA_INTRQ__USBPHY2_DATAOUT_6 0x280 0x600 0x000 0x7 0x0 -#define MX53_PAD_PATA_DIOR__PATA_DIOR 0x284 0x604 0x000 0x0 0x0 -#define MX53_PAD_PATA_DIOR__GPIO7_3 0x284 0x604 0x000 0x1 0x0 -#define MX53_PAD_PATA_DIOR__UART2_RTS 0x284 0x604 0x87c 0x3 0x3 -#define MX53_PAD_PATA_DIOR__CAN1_RXCAN 0x284 0x604 0x760 0x4 0x1 -#define MX53_PAD_PATA_DIOR__USBPHY2_DATAOUT_7 0x284 0x604 0x000 0x7 0x0 -#define MX53_PAD_PATA_RESET_B__PATA_PATA_RESET_B 0x288 0x608 0x000 0x0 0x0 -#define MX53_PAD_PATA_RESET_B__GPIO7_4 0x288 0x608 0x000 0x1 0x0 -#define MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x288 0x608 0x000 0x2 0x0 -#define MX53_PAD_PATA_RESET_B__UART1_CTS 0x288 0x608 0x000 0x3 0x0 -#define MX53_PAD_PATA_RESET_B__CAN2_TXCAN 0x288 0x608 0x000 0x4 0x0 -#define MX53_PAD_PATA_RESET_B__USBPHY1_DATAOUT_0 0x288 0x608 0x000 0x7 0x0 -#define MX53_PAD_PATA_IORDY__PATA_IORDY 0x28c 0x60c 0x000 0x0 0x0 -#define MX53_PAD_PATA_IORDY__GPIO7_5 0x28c 0x60c 0x000 0x1 0x0 -#define MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x28c 0x60c 0x000 0x2 0x0 -#define MX53_PAD_PATA_IORDY__UART1_RTS 0x28c 0x60c 0x874 0x3 0x3 -#define MX53_PAD_PATA_IORDY__CAN2_RXCAN 0x28c 0x60c 0x764 0x4 0x1 -#define MX53_PAD_PATA_IORDY__USBPHY1_DATAOUT_1 0x28c 0x60c 0x000 0x7 0x0 -#define MX53_PAD_PATA_DA_0__PATA_DA_0 0x290 0x610 0x000 0x0 0x0 -#define MX53_PAD_PATA_DA_0__GPIO7_6 0x290 0x610 0x000 0x1 0x0 -#define MX53_PAD_PATA_DA_0__ESDHC3_RST 0x290 0x610 0x000 0x2 0x0 -#define MX53_PAD_PATA_DA_0__OWIRE_LINE 0x290 0x610 0x864 0x4 0x0 -#define MX53_PAD_PATA_DA_0__USBPHY1_DATAOUT_2 0x290 0x610 0x000 0x7 0x0 -#define MX53_PAD_PATA_DA_1__PATA_DA_1 0x294 0x614 0x000 0x0 0x0 -#define MX53_PAD_PATA_DA_1__GPIO7_7 0x294 0x614 0x000 0x1 0x0 -#define MX53_PAD_PATA_DA_1__ESDHC4_CMD 0x294 0x614 0x000 0x2 0x0 -#define MX53_PAD_PATA_DA_1__UART3_CTS 0x294 0x614 0x000 0x4 0x0 -#define MX53_PAD_PATA_DA_1__USBPHY1_DATAOUT_3 0x294 0x614 0x000 0x7 0x0 -#define MX53_PAD_PATA_DA_2__PATA_DA_2 0x298 0x618 0x000 0x0 0x0 -#define MX53_PAD_PATA_DA_2__GPIO7_8 0x298 0x618 0x000 0x1 0x0 -#define MX53_PAD_PATA_DA_2__ESDHC4_CLK 0x298 0x618 0x000 0x2 0x0 -#define MX53_PAD_PATA_DA_2__UART3_RTS 0x298 0x618 0x884 0x4 0x5 -#define MX53_PAD_PATA_DA_2__USBPHY1_DATAOUT_4 0x298 0x618 0x000 0x7 0x0 -#define MX53_PAD_PATA_CS_0__PATA_CS_0 0x29c 0x61c 0x000 0x0 0x0 -#define MX53_PAD_PATA_CS_0__GPIO7_9 0x29c 0x61c 0x000 0x1 0x0 -#define MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x29c 0x61c 0x000 0x4 0x0 -#define MX53_PAD_PATA_CS_0__USBPHY1_DATAOUT_5 0x29c 0x61c 0x000 0x7 0x0 -#define MX53_PAD_PATA_CS_1__PATA_CS_1 0x2a0 0x620 0x000 0x0 0x0 -#define MX53_PAD_PATA_CS_1__GPIO7_10 0x2a0 0x620 0x000 0x1 0x0 -#define MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x2a0 0x620 0x888 0x4 0x3 -#define MX53_PAD_PATA_CS_1__USBPHY1_DATAOUT_6 0x2a0 0x620 0x000 0x7 0x0 -#define MX53_PAD_PATA_DATA0__PATA_DATA_0 0x2a4 0x628 0x000 0x0 0x0 -#define MX53_PAD_PATA_DATA0__GPIO2_0 0x2a4 0x628 0x000 0x1 0x0 -#define MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 0x2a4 0x628 0x000 0x3 0x0 -#define MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x2a4 0x628 0x000 0x4 0x0 -#define MX53_PAD_PATA_DATA0__GPU3d_GPU_DEBUG_OUT_0 0x2a4 0x628 0x000 0x5 0x0 -#define MX53_PAD_PATA_DATA0__IPU_DIAG_BUS_0 0x2a4 0x628 0x000 0x6 0x0 -#define MX53_PAD_PATA_DATA0__USBPHY1_DATAOUT_7 0x2a4 0x628 0x000 0x7 0x0 -#define MX53_PAD_PATA_DATA1__PATA_DATA_1 0x2a8 0x62c 0x000 0x0 0x0 -#define MX53_PAD_PATA_DATA1__GPIO2_1 0x2a8 0x62c 0x000 0x1 0x0 -#define MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 0x2a8 0x62c 0x000 0x3 0x0 -#define MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x2a8 0x62c 0x000 0x4 0x0 -#define MX53_PAD_PATA_DATA1__GPU3d_GPU_DEBUG_OUT_1 0x2a8 0x62c 0x000 0x5 0x0 -#define MX53_PAD_PATA_DATA1__IPU_DIAG_BUS_1 0x2a8 0x62c 0x000 0x6 0x0 -#define MX53_PAD_PATA_DATA2__PATA_DATA_2 0x2ac 0x630 0x000 0x0 0x0 -#define MX53_PAD_PATA_DATA2__GPIO2_2 0x2ac 0x630 0x000 0x1 0x0 -#define MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 0x2ac 0x630 0x000 0x3 0x0 -#define MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x2ac 0x630 0x000 0x4 0x0 -#define MX53_PAD_PATA_DATA2__GPU3d_GPU_DEBUG_OUT_2 0x2ac 0x630 0x000 0x5 0x0 -#define MX53_PAD_PATA_DATA2__IPU_DIAG_BUS_2 0x2ac 0x630 0x000 0x6 0x0 -#define MX53_PAD_PATA_DATA3__PATA_DATA_3 0x2b0 0x634 0x000 0x0 0x0 -#define MX53_PAD_PATA_DATA3__GPIO2_3 0x2b0 0x634 0x000 0x1 0x0 -#define MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 0x2b0 0x634 0x000 0x3 0x0 -#define MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x2b0 0x634 0x000 0x4 0x0 -#define MX53_PAD_PATA_DATA3__GPU3d_GPU_DEBUG_OUT_3 0x2b0 0x634 0x000 0x5 0x0 -#define MX53_PAD_PATA_DATA3__IPU_DIAG_BUS_3 0x2b0 0x634 0x000 0x6 0x0 -#define MX53_PAD_PATA_DATA4__PATA_DATA_4 0x2b4 0x638 0x000 0x0 0x0 -#define MX53_PAD_PATA_DATA4__GPIO2_4 0x2b4 0x638 0x000 0x1 0x0 -#define MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 0x2b4 0x638 0x000 0x3 0x0 -#define MX53_PAD_PATA_DATA4__ESDHC4_DAT4 0x2b4 0x638 0x000 0x4 0x0 -#define MX53_PAD_PATA_DATA4__GPU3d_GPU_DEBUG_OUT_4 0x2b4 0x638 0x000 0x5 0x0 -#define MX53_PAD_PATA_DATA4__IPU_DIAG_BUS_4 0x2b4 0x638 0x000 0x6 0x0 -#define MX53_PAD_PATA_DATA5__PATA_DATA_5 0x2b8 0x63c 0x000 0x0 0x0 -#define MX53_PAD_PATA_DATA5__GPIO2_5 0x2b8 0x63c 0x000 0x1 0x0 -#define MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 0x2b8 0x63c 0x000 0x3 0x0 -#define MX53_PAD_PATA_DATA5__ESDHC4_DAT5 0x2b8 0x63c 0x000 0x4 0x0 -#define MX53_PAD_PATA_DATA5__GPU3d_GPU_DEBUG_OUT_5 0x2b8 0x63c 0x000 0x5 0x0 -#define MX53_PAD_PATA_DATA5__IPU_DIAG_BUS_5 0x2b8 0x63c 0x000 0x6 0x0 -#define MX53_PAD_PATA_DATA6__PATA_DATA_6 0x2bc 0x640 0x000 0x0 0x0 -#define MX53_PAD_PATA_DATA6__GPIO2_6 0x2bc 0x640 0x000 0x1 0x0 -#define MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 0x2bc 0x640 0x000 0x3 0x0 -#define MX53_PAD_PATA_DATA6__ESDHC4_DAT6 0x2bc 0x640 0x000 0x4 0x0 -#define MX53_PAD_PATA_DATA6__GPU3d_GPU_DEBUG_OUT_6 0x2bc 0x640 0x000 0x5 0x0 -#define MX53_PAD_PATA_DATA6__IPU_DIAG_BUS_6 0x2bc 0x640 0x000 0x6 0x0 -#define MX53_PAD_PATA_DATA7__PATA_DATA_7 0x2c0 0x644 0x000 0x0 0x0 -#define MX53_PAD_PATA_DATA7__GPIO2_7 0x2c0 0x644 0x000 0x1 0x0 -#define MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 0x2c0 0x644 0x000 0x3 0x0 -#define MX53_PAD_PATA_DATA7__ESDHC4_DAT7 0x2c0 0x644 0x000 0x4 0x0 -#define MX53_PAD_PATA_DATA7__GPU3d_GPU_DEBUG_OUT_7 0x2c0 0x644 0x000 0x5 0x0 -#define MX53_PAD_PATA_DATA7__IPU_DIAG_BUS_7 0x2c0 0x644 0x000 0x6 0x0 -#define MX53_PAD_PATA_DATA8__PATA_DATA_8 0x2c4 0x648 0x000 0x0 0x0 -#define MX53_PAD_PATA_DATA8__GPIO2_8 0x2c4 0x648 0x000 0x1 0x0 -#define MX53_PAD_PATA_DATA8__ESDHC1_DAT4 0x2c4 0x648 0x000 0x2 0x0 -#define MX53_PAD_PATA_DATA8__EMI_NANDF_D_8 0x2c4 0x648 0x000 0x3 0x0 -#define MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x2c4 0x648 0x000 0x4 0x0 -#define MX53_PAD_PATA_DATA8__GPU3d_GPU_DEBUG_OUT_8 0x2c4 0x648 0x000 0x5 0x0 -#define MX53_PAD_PATA_DATA8__IPU_DIAG_BUS_8 0x2c4 0x648 0x000 0x6 0x0 -#define MX53_PAD_PATA_DATA9__PATA_DATA_9 0x2c8 0x64c 0x000 0x0 0x0 -#define MX53_PAD_PATA_DATA9__GPIO2_9 0x2c8 0x64c 0x000 0x1 0x0 -#define MX53_PAD_PATA_DATA9__ESDHC1_DAT5 0x2c8 0x64c 0x000 0x2 0x0 -#define MX53_PAD_PATA_DATA9__EMI_NANDF_D_9 0x2c8 0x64c 0x000 0x3 0x0 -#define MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x2c8 0x64c 0x000 0x4 0x0 -#define MX53_PAD_PATA_DATA9__GPU3d_GPU_DEBUG_OUT_9 0x2c8 0x64c 0x000 0x5 0x0 -#define MX53_PAD_PATA_DATA9__IPU_DIAG_BUS_9 0x2c8 0x64c 0x000 0x6 0x0 -#define MX53_PAD_PATA_DATA10__PATA_DATA_10 0x2cc 0x650 0x000 0x0 0x0 -#define MX53_PAD_PATA_DATA10__GPIO2_10 0x2cc 0x650 0x000 0x1 0x0 -#define MX53_PAD_PATA_DATA10__ESDHC1_DAT6 0x2cc 0x650 0x000 0x2 0x0 -#define MX53_PAD_PATA_DATA10__EMI_NANDF_D_10 0x2cc 0x650 0x000 0x3 0x0 -#define MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x2cc 0x650 0x000 0x4 0x0 -#define MX53_PAD_PATA_DATA10__GPU3d_GPU_DEBUG_OUT_10 0x2cc 0x650 0x000 0x5 0x0 -#define MX53_PAD_PATA_DATA10__IPU_DIAG_BUS_10 0x2cc 0x650 0x000 0x6 0x0 -#define MX53_PAD_PATA_DATA11__PATA_DATA_11 0x2d0 0x654 0x000 0x0 0x0 -#define MX53_PAD_PATA_DATA11__GPIO2_11 0x2d0 0x654 0x000 0x1 0x0 -#define MX53_PAD_PATA_DATA11__ESDHC1_DAT7 0x2d0 0x654 0x000 0x2 0x0 -#define MX53_PAD_PATA_DATA11__EMI_NANDF_D_11 0x2d0 0x654 0x000 0x3 0x0 -#define MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x2d0 0x654 0x000 0x4 0x0 -#define MX53_PAD_PATA_DATA11__GPU3d_GPU_DEBUG_OUT_11 0x2d0 0x654 0x000 0x5 0x0 -#define MX53_PAD_PATA_DATA11__IPU_DIAG_BUS_11 0x2d0 0x654 0x000 0x6 0x0 -#define MX53_PAD_PATA_DATA12__PATA_DATA_12 0x2d4 0x658 0x000 0x0 0x0 -#define MX53_PAD_PATA_DATA12__GPIO2_12 0x2d4 0x658 0x000 0x1 0x0 -#define MX53_PAD_PATA_DATA12__ESDHC2_DAT4 0x2d4 0x658 0x000 0x2 0x0 -#define MX53_PAD_PATA_DATA12__EMI_NANDF_D_12 0x2d4 0x658 0x000 0x3 0x0 -#define MX53_PAD_PATA_DATA12__ESDHC4_DAT0 0x2d4 0x658 0x000 0x4 0x0 -#define MX53_PAD_PATA_DATA12__GPU3d_GPU_DEBUG_OUT_12 0x2d4 0x658 0x000 0x5 0x0 -#define MX53_PAD_PATA_DATA12__IPU_DIAG_BUS_12 0x2d4 0x658 0x000 0x6 0x0 -#define MX53_PAD_PATA_DATA13__PATA_DATA_13 0x2d8 0x65c 0x000 0x0 0x0 -#define MX53_PAD_PATA_DATA13__GPIO2_13 0x2d8 0x65c 0x000 0x1 0x0 -#define MX53_PAD_PATA_DATA13__ESDHC2_DAT5 0x2d8 0x65c 0x000 0x2 0x0 -#define MX53_PAD_PATA_DATA13__EMI_NANDF_D_13 0x2d8 0x65c 0x000 0x3 0x0 -#define MX53_PAD_PATA_DATA13__ESDHC4_DAT1 0x2d8 0x65c 0x000 0x4 0x0 -#define MX53_PAD_PATA_DATA13__GPU3d_GPU_DEBUG_OUT_13 0x2d8 0x65c 0x000 0x5 0x0 -#define MX53_PAD_PATA_DATA13__IPU_DIAG_BUS_13 0x2d8 0x65c 0x000 0x6 0x0 -#define MX53_PAD_PATA_DATA14__PATA_DATA_14 0x2dc 0x660 0x000 0x0 0x0 -#define MX53_PAD_PATA_DATA14__GPIO2_14 0x2dc 0x660 0x000 0x1 0x0 -#define MX53_PAD_PATA_DATA14__ESDHC2_DAT6 0x2dc 0x660 0x000 0x2 0x0 -#define MX53_PAD_PATA_DATA14__EMI_NANDF_D_14 0x2dc 0x660 0x000 0x3 0x0 -#define MX53_PAD_PATA_DATA14__ESDHC4_DAT2 0x2dc 0x660 0x000 0x4 0x0 -#define MX53_PAD_PATA_DATA14__GPU3d_GPU_DEBUG_OUT_14 0x2dc 0x660 0x000 0x5 0x0 -#define MX53_PAD_PATA_DATA14__IPU_DIAG_BUS_14 0x2dc 0x660 0x000 0x6 0x0 -#define MX53_PAD_PATA_DATA15__PATA_DATA_15 0x2e0 0x664 0x000 0x0 0x0 -#define MX53_PAD_PATA_DATA15__GPIO2_15 0x2e0 0x664 0x000 0x1 0x0 -#define MX53_PAD_PATA_DATA15__ESDHC2_DAT7 0x2e0 0x664 0x000 0x2 0x0 -#define MX53_PAD_PATA_DATA15__EMI_NANDF_D_15 0x2e0 0x664 0x000 0x3 0x0 -#define MX53_PAD_PATA_DATA15__ESDHC4_DAT3 0x2e0 0x664 0x000 0x4 0x0 -#define MX53_PAD_PATA_DATA15__GPU3d_GPU_DEBUG_OUT_15 0x2e0 0x664 0x000 0x5 0x0 -#define MX53_PAD_PATA_DATA15__IPU_DIAG_BUS_15 0x2e0 0x664 0x000 0x6 0x0 -#define MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x2e4 0x66c 0x000 0x0 0x0 -#define MX53_PAD_SD1_DATA0__GPIO1_16 0x2e4 0x66c 0x000 0x1 0x0 -#define MX53_PAD_SD1_DATA0__GPT_CAPIN1 0x2e4 0x66c 0x000 0x3 0x0 -#define MX53_PAD_SD1_DATA0__CSPI_MISO 0x2e4 0x66c 0x784 0x5 0x2 -#define MX53_PAD_SD1_DATA0__CCM_PLL3_BYP 0x2e4 0x66c 0x778 0x7 0x0 -#define MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x2e8 0x670 0x000 0x0 0x0 -#define MX53_PAD_SD1_DATA1__GPIO1_17 0x2e8 0x670 0x000 0x1 0x0 -#define MX53_PAD_SD1_DATA1__GPT_CAPIN2 0x2e8 0x670 0x000 0x3 0x0 -#define MX53_PAD_SD1_DATA1__CSPI_SS0 0x2e8 0x670 0x78c 0x5 0x3 -#define MX53_PAD_SD1_DATA1__CCM_PLL4_BYP 0x2e8 0x670 0x77c 0x7 0x1 -#define MX53_PAD_SD1_CMD__ESDHC1_CMD 0x2ec 0x674 0x000 0x0 0x0 -#define MX53_PAD_SD1_CMD__GPIO1_18 0x2ec 0x674 0x000 0x1 0x0 -#define MX53_PAD_SD1_CMD__GPT_CMPOUT1 0x2ec 0x674 0x000 0x3 0x0 -#define MX53_PAD_SD1_CMD__CSPI_MOSI 0x2ec 0x674 0x788 0x5 0x2 -#define MX53_PAD_SD1_CMD__CCM_PLL1_BYP 0x2ec 0x674 0x770 0x7 0x0 -#define MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x2f0 0x678 0x000 0x0 0x0 -#define MX53_PAD_SD1_DATA2__GPIO1_19 0x2f0 0x678 0x000 0x1 0x0 -#define MX53_PAD_SD1_DATA2__GPT_CMPOUT2 0x2f0 0x678 0x000 0x2 0x0 -#define MX53_PAD_SD1_DATA2__PWM2_PWMO 0x2f0 0x678 0x000 0x3 0x0 -#define MX53_PAD_SD1_DATA2__WDOG1_WDOG_B 0x2f0 0x678 0x000 0x4 0x0 -#define MX53_PAD_SD1_DATA2__CSPI_SS1 0x2f0 0x678 0x790 0x5 0x2 -#define MX53_PAD_SD1_DATA2__WDOG1_WDOG_RST_B_DEB 0x2f0 0x678 0x000 0x6 0x0 -#define MX53_PAD_SD1_DATA2__CCM_PLL2_BYP 0x2f0 0x678 0x774 0x7 0x0 -#define MX53_PAD_SD1_CLK__ESDHC1_CLK 0x2f4 0x67c 0x000 0x0 0x0 -#define MX53_PAD_SD1_CLK__GPIO1_20 0x2f4 0x67c 0x000 0x1 0x0 -#define MX53_PAD_SD1_CLK__OSC32k_32K_OUT 0x2f4 0x67c 0x000 0x2 0x0 -#define MX53_PAD_SD1_CLK__GPT_CLKIN 0x2f4 0x67c 0x000 0x3 0x0 -#define MX53_PAD_SD1_CLK__CSPI_SCLK 0x2f4 0x67c 0x780 0x5 0x2 -#define MX53_PAD_SD1_CLK__SATA_PHY_DTB_0 0x2f4 0x67c 0x000 0x7 0x0 -#define MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x2f8 0x680 0x000 0x0 0x0 -#define MX53_PAD_SD1_DATA3__GPIO1_21 0x2f8 0x680 0x000 0x1 0x0 -#define MX53_PAD_SD1_DATA3__GPT_CMPOUT3 0x2f8 0x680 0x000 0x2 0x0 -#define MX53_PAD_SD1_DATA3__PWM1_PWMO 0x2f8 0x680 0x000 0x3 0x0 -#define MX53_PAD_SD1_DATA3__WDOG2_WDOG_B 0x2f8 0x680 0x000 0x4 0x0 -#define MX53_PAD_SD1_DATA3__CSPI_SS2 0x2f8 0x680 0x794 0x5 0x2 -#define MX53_PAD_SD1_DATA3__WDOG2_WDOG_RST_B_DEB 0x2f8 0x680 0x000 0x6 0x0 -#define MX53_PAD_SD1_DATA3__SATA_PHY_DTB_1 0x2f8 0x680 0x000 0x7 0x0 -#define MX53_PAD_SD2_CLK__ESDHC2_CLK 0x2fc 0x688 0x000 0x0 0x0 -#define MX53_PAD_SD2_CLK__GPIO1_10 0x2fc 0x688 0x000 0x1 0x0 -#define MX53_PAD_SD2_CLK__KPP_COL_5 0x2fc 0x688 0x840 0x2 0x2 -#define MX53_PAD_SD2_CLK__AUDMUX_AUD4_RXFS 0x2fc 0x688 0x73c 0x3 0x1 -#define MX53_PAD_SD2_CLK__CSPI_SCLK 0x2fc 0x688 0x780 0x5 0x3 -#define MX53_PAD_SD2_CLK__SCC_RANDOM_V 0x2fc 0x688 0x000 0x7 0x0 -#define MX53_PAD_SD2_CMD__ESDHC2_CMD 0x300 0x68c 0x000 0x0 0x0 -#define MX53_PAD_SD2_CMD__GPIO1_11 0x300 0x68c 0x000 0x1 0x0 -#define MX53_PAD_SD2_CMD__KPP_ROW_5 0x300 0x68c 0x84c 0x2 0x1 -#define MX53_PAD_SD2_CMD__AUDMUX_AUD4_RXC 0x300 0x68c 0x738 0x3 0x1 -#define MX53_PAD_SD2_CMD__CSPI_MOSI 0x300 0x68c 0x788 0x5 0x3 -#define MX53_PAD_SD2_CMD__SCC_RANDOM 0x300 0x68c 0x000 0x7 0x0 -#define MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x304 0x690 0x000 0x0 0x0 -#define MX53_PAD_SD2_DATA3__GPIO1_12 0x304 0x690 0x000 0x1 0x0 -#define MX53_PAD_SD2_DATA3__KPP_COL_6 0x304 0x690 0x844 0x2 0x1 -#define MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC 0x304 0x690 0x740 0x3 0x1 -#define MX53_PAD_SD2_DATA3__CSPI_SS2 0x304 0x690 0x794 0x5 0x3 -#define MX53_PAD_SD2_DATA3__SJC_DONE 0x304 0x690 0x000 0x7 0x0 -#define MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x308 0x694 0x000 0x0 0x0 -#define MX53_PAD_SD2_DATA2__GPIO1_13 0x308 0x694 0x000 0x1 0x0 -#define MX53_PAD_SD2_DATA2__KPP_ROW_6 0x308 0x694 0x850 0x2 0x1 -#define MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD 0x308 0x694 0x734 0x3 0x1 -#define MX53_PAD_SD2_DATA2__CSPI_SS1 0x308 0x694 0x790 0x5 0x3 -#define MX53_PAD_SD2_DATA2__SJC_FAIL 0x308 0x694 0x000 0x7 0x0 -#define MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x30c 0x698 0x000 0x0 0x0 -#define MX53_PAD_SD2_DATA1__GPIO1_14 0x30c 0x698 0x000 0x1 0x0 -#define MX53_PAD_SD2_DATA1__KPP_COL_7 0x30c 0x698 0x848 0x2 0x1 -#define MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS 0x30c 0x698 0x744 0x3 0x1 -#define MX53_PAD_SD2_DATA1__CSPI_SS0 0x30c 0x698 0x78c 0x5 0x4 -#define MX53_PAD_SD2_DATA1__RTIC_SEC_VIO 0x30c 0x698 0x000 0x7 0x0 -#define MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x310 0x69c 0x000 0x0 0x0 -#define MX53_PAD_SD2_DATA0__GPIO1_15 0x310 0x69c 0x000 0x1 0x0 -#define MX53_PAD_SD2_DATA0__KPP_ROW_7 0x310 0x69c 0x854 0x2 0x1 -#define MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD 0x310 0x69c 0x730 0x3 0x1 -#define MX53_PAD_SD2_DATA0__CSPI_MISO 0x310 0x69c 0x784 0x5 0x3 -#define MX53_PAD_SD2_DATA0__RTIC_DONE_INT 0x310 0x69c 0x000 0x7 0x0 -#define MX53_PAD_GPIO_0__CCM_CLKO 0x314 0x6a4 0x000 0x0 0x0 -#define MX53_PAD_GPIO_0__GPIO1_0 0x314 0x6a4 0x000 0x1 0x0 -#define MX53_PAD_GPIO_0__KPP_COL_5 0x314 0x6a4 0x840 0x2 0x3 -#define MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x314 0x6a4 0x000 0x3 0x0 -#define MX53_PAD_GPIO_0__EPIT1_EPITO 0x314 0x6a4 0x000 0x4 0x0 -#define MX53_PAD_GPIO_0__SRTC_ALARM_DEB 0x314 0x6a4 0x000 0x5 0x0 -#define MX53_PAD_GPIO_0__USBOH3_USBH1_PWR 0x314 0x6a4 0x000 0x6 0x0 -#define MX53_PAD_GPIO_0__CSU_TD 0x314 0x6a4 0x000 0x7 0x0 -#define MX53_PAD_GPIO_1__ESAI1_SCKR 0x318 0x6a8 0x7dc 0x0 0x1 -#define MX53_PAD_GPIO_1__GPIO1_1 0x318 0x6a8 0x000 0x1 0x0 -#define MX53_PAD_GPIO_1__KPP_ROW_5 0x318 0x6a8 0x84c 0x2 0x2 -#define MX53_PAD_GPIO_1__CCM_SSI_EXT2_CLK 0x318 0x6a8 0x000 0x3 0x0 -#define MX53_PAD_GPIO_1__PWM2_PWMO 0x318 0x6a8 0x000 0x4 0x0 -#define MX53_PAD_GPIO_1__WDOG2_WDOG_B 0x318 0x6a8 0x000 0x5 0x0 -#define MX53_PAD_GPIO_1__ESDHC1_CD 0x318 0x6a8 0x000 0x6 0x0 -#define MX53_PAD_GPIO_1__SRC_TESTER_ACK 0x318 0x6a8 0x000 0x7 0x0 -#define MX53_PAD_GPIO_9__ESAI1_FSR 0x31c 0x6ac 0x7cc 0x0 0x1 -#define MX53_PAD_GPIO_9__GPIO1_9 0x31c 0x6ac 0x000 0x1 0x0 -#define MX53_PAD_GPIO_9__KPP_COL_6 0x31c 0x6ac 0x844 0x2 0x2 -#define MX53_PAD_GPIO_9__CCM_REF_EN_B 0x31c 0x6ac 0x000 0x3 0x0 -#define MX53_PAD_GPIO_9__PWM1_PWMO 0x31c 0x6ac 0x000 0x4 0x0 -#define MX53_PAD_GPIO_9__WDOG1_WDOG_B 0x31c 0x6ac 0x000 0x5 0x0 -#define MX53_PAD_GPIO_9__ESDHC1_WP 0x31c 0x6ac 0x7fc 0x6 0x1 -#define MX53_PAD_GPIO_9__SCC_FAIL_STATE 0x31c 0x6ac 0x000 0x7 0x0 -#define MX53_PAD_GPIO_3__ESAI1_HCKR 0x320 0x6b0 0x7d4 0x0 0x1 -#define MX53_PAD_GPIO_3__GPIO1_3 0x320 0x6b0 0x000 0x1 0x0 -#define MX53_PAD_GPIO_3__I2C3_SCL 0x320 0x6b0 0x824 0x2 0x1 -#define MX53_PAD_GPIO_3__DPLLIP1_TOG_EN 0x320 0x6b0 0x000 0x3 0x0 -#define MX53_PAD_GPIO_3__CCM_CLKO2 0x320 0x6b0 0x000 0x4 0x0 -#define MX53_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 0x320 0x6b0 0x000 0x5 0x0 -#define MX53_PAD_GPIO_3__USBOH3_USBH1_OC 0x320 0x6b0 0x8a0 0x6 0x1 -#define MX53_PAD_GPIO_3__MLB_MLBCLK 0x320 0x6b0 0x858 0x7 0x2 -#define MX53_PAD_GPIO_6__ESAI1_SCKT 0x324 0x6b4 0x7e0 0x0 0x1 -#define MX53_PAD_GPIO_6__GPIO1_6 0x324 0x6b4 0x000 0x1 0x0 -#define MX53_PAD_GPIO_6__I2C3_SDA 0x324 0x6b4 0x828 0x2 0x1 -#define MX53_PAD_GPIO_6__CCM_CCM_OUT_0 0x324 0x6b4 0x000 0x3 0x0 -#define MX53_PAD_GPIO_6__CSU_CSU_INT_DEB 0x324 0x6b4 0x000 0x4 0x0 -#define MX53_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 0x324 0x6b4 0x000 0x5 0x0 -#define MX53_PAD_GPIO_6__ESDHC2_LCTL 0x324 0x6b4 0x000 0x6 0x0 -#define MX53_PAD_GPIO_6__MLB_MLBSIG 0x324 0x6b4 0x860 0x7 0x2 -#define MX53_PAD_GPIO_2__ESAI1_FST 0x328 0x6b8 0x7d0 0x0 0x1 -#define MX53_PAD_GPIO_2__GPIO1_2 0x328 0x6b8 0x000 0x1 0x0 -#define MX53_PAD_GPIO_2__KPP_ROW_6 0x328 0x6b8 0x850 0x2 0x2 -#define MX53_PAD_GPIO_2__CCM_CCM_OUT_1 0x328 0x6b8 0x000 0x3 0x0 -#define MX53_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 0x328 0x6b8 0x000 0x4 0x0 -#define MX53_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 0x328 0x6b8 0x000 0x5 0x0 -#define MX53_PAD_GPIO_2__ESDHC2_WP 0x328 0x6b8 0x000 0x6 0x0 -#define MX53_PAD_GPIO_2__MLB_MLBDAT 0x328 0x6b8 0x85c 0x7 0x2 -#define MX53_PAD_GPIO_4__ESAI1_HCKT 0x32c 0x6bc 0x7d8 0x0 0x1 -#define MX53_PAD_GPIO_4__GPIO1_4 0x32c 0x6bc 0x000 0x1 0x0 -#define MX53_PAD_GPIO_4__KPP_COL_7 0x32c 0x6bc 0x848 0x2 0x2 -#define MX53_PAD_GPIO_4__CCM_CCM_OUT_2 0x32c 0x6bc 0x000 0x3 0x0 -#define MX53_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 0x32c 0x6bc 0x000 0x4 0x0 -#define MX53_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 0x32c 0x6bc 0x000 0x5 0x0 -#define MX53_PAD_GPIO_4__ESDHC2_CD 0x32c 0x6bc 0x000 0x6 0x0 -#define MX53_PAD_GPIO_4__SCC_SEC_STATE 0x32c 0x6bc 0x000 0x7 0x0 -#define MX53_PAD_GPIO_5__ESAI1_TX2_RX3 0x330 0x6c0 0x7ec 0x0 0x1 -#define MX53_PAD_GPIO_5__GPIO1_5 0x330 0x6c0 0x000 0x1 0x0 -#define MX53_PAD_GPIO_5__KPP_ROW_7 0x330 0x6c0 0x854 0x2 0x2 -#define MX53_PAD_GPIO_5__CCM_CLKO 0x330 0x6c0 0x000 0x3 0x0 -#define MX53_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 0x330 0x6c0 0x000 0x4 0x0 -#define MX53_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 0x330 0x6c0 0x000 0x5 0x0 -#define MX53_PAD_GPIO_5__I2C3_SCL 0x330 0x6c0 0x824 0x6 0x2 -#define MX53_PAD_GPIO_5__CCM_PLL1_BYP 0x330 0x6c0 0x770 0x7 0x1 -#define MX53_PAD_GPIO_7__ESAI1_TX4_RX1 0x334 0x6c4 0x7f4 0x0 0x1 -#define MX53_PAD_GPIO_7__GPIO1_7 0x334 0x6c4 0x000 0x1 0x0 -#define MX53_PAD_GPIO_7__EPIT1_EPITO 0x334 0x6c4 0x000 0x2 0x0 -#define MX53_PAD_GPIO_7__CAN1_TXCAN 0x334 0x6c4 0x000 0x3 0x0 -#define MX53_PAD_GPIO_7__UART2_TXD_MUX 0x334 0x6c4 0x000 0x4 0x0 -#define MX53_PAD_GPIO_7__FIRI_RXD 0x334 0x6c4 0x80c 0x5 0x1 -#define MX53_PAD_GPIO_7__SPDIF_PLOCK 0x334 0x6c4 0x000 0x6 0x0 -#define MX53_PAD_GPIO_7__CCM_PLL2_BYP 0x334 0x6c4 0x774 0x7 0x1 -#define MX53_PAD_GPIO_8__ESAI1_TX5_RX0 0x338 0x6c8 0x7f8 0x0 0x1 -#define MX53_PAD_GPIO_8__GPIO1_8 0x338 0x6c8 0x000 0x1 0x0 -#define MX53_PAD_GPIO_8__EPIT2_EPITO 0x338 0x6c8 0x000 0x2 0x0 -#define MX53_PAD_GPIO_8__CAN1_RXCAN 0x338 0x6c8 0x760 0x3 0x2 -#define MX53_PAD_GPIO_8__UART2_RXD_MUX 0x338 0x6c8 0x880 0x4 0x5 -#define MX53_PAD_GPIO_8__FIRI_TXD 0x338 0x6c8 0x000 0x5 0x0 -#define MX53_PAD_GPIO_8__SPDIF_SRCLK 0x338 0x6c8 0x000 0x6 0x0 -#define MX53_PAD_GPIO_8__CCM_PLL3_BYP 0x338 0x6c8 0x778 0x7 0x1 -#define MX53_PAD_GPIO_16__ESAI1_TX3_RX2 0x33c 0x6cc 0x7f0 0x0 0x1 -#define MX53_PAD_GPIO_16__GPIO7_11 0x33c 0x6cc 0x000 0x1 0x0 -#define MX53_PAD_GPIO_16__TZIC_PWRFAIL_INT 0x33c 0x6cc 0x000 0x2 0x0 -#define MX53_PAD_GPIO_16__RTC_CE_RTC_EXT_TRIG1 0x33c 0x6cc 0x000 0x4 0x0 -#define MX53_PAD_GPIO_16__SPDIF_IN1 0x33c 0x6cc 0x870 0x5 0x1 -#define MX53_PAD_GPIO_16__I2C3_SDA 0x33c 0x6cc 0x828 0x6 0x2 -#define MX53_PAD_GPIO_16__SJC_DE_B 0x33c 0x6cc 0x000 0x7 0x0 -#define MX53_PAD_GPIO_17__ESAI1_TX0 0x340 0x6d0 0x7e4 0x0 0x1 -#define MX53_PAD_GPIO_17__GPIO7_12 0x340 0x6d0 0x000 0x1 0x0 -#define MX53_PAD_GPIO_17__SDMA_EXT_EVENT_0 0x340 0x6d0 0x868 0x2 0x1 -#define MX53_PAD_GPIO_17__GPC_PMIC_RDY 0x340 0x6d0 0x810 0x3 0x1 -#define MX53_PAD_GPIO_17__RTC_CE_RTC_FSV_TRIG 0x340 0x6d0 0x000 0x4 0x0 -#define MX53_PAD_GPIO_17__SPDIF_OUT1 0x340 0x6d0 0x000 0x5 0x0 -#define MX53_PAD_GPIO_17__IPU_SNOOP2 0x340 0x6d0 0x000 0x6 0x0 -#define MX53_PAD_GPIO_17__SJC_JTAG_ACT 0x340 0x6d0 0x000 0x7 0x0 -#define MX53_PAD_GPIO_18__ESAI1_TX1 0x344 0x6d4 0x7e8 0x0 0x1 -#define MX53_PAD_GPIO_18__GPIO7_13 0x344 0x6d4 0x000 0x1 0x0 -#define MX53_PAD_GPIO_18__SDMA_EXT_EVENT_1 0x344 0x6d4 0x86c 0x2 0x1 -#define MX53_PAD_GPIO_18__OWIRE_LINE 0x344 0x6d4 0x864 0x3 0x1 -#define MX53_PAD_GPIO_18__RTC_CE_RTC_ALARM2_TRIG 0x344 0x6d4 0x000 0x4 0x0 -#define MX53_PAD_GPIO_18__CCM_ASRC_EXT_CLK 0x344 0x6d4 0x768 0x5 0x1 -#define MX53_PAD_GPIO_18__ESDHC1_LCTL 0x344 0x6d4 0x000 0x6 0x0 -#define MX53_PAD_GPIO_18__SRC_SYSTEM_RST 0x344 0x6d4 0x000 0x7 0x0 - -#endif /* __DTS_IMX53_PINFUNC_H */ diff --git a/sys/gnu/dts/arm/imx53-ppd.dts b/sys/gnu/dts/arm/imx53-ppd.dts deleted file mode 100644 index 5ff9a179c83..00000000000 --- a/sys/gnu/dts/arm/imx53-ppd.dts +++ /dev/null @@ -1,1083 +0,0 @@ -/* - * Copyright 2014 General Electric Company - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include "imx53.dtsi" -#include - -/ { - model = "General Electric CS ONE"; - compatible = "ge,imx53-cpuvo", "fsl,imx53"; - - aliases { - spi0 = &cspi; - spi1 = &ecspi1; - spi2 = &ecspi2; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@70000000 { - device_type = "memory"; - reg = <0x70000000 0x20000000>, - <0xb0000000 0x20000000>; - }; - - cko2_11M: sgtl-clock-cko2 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <11289600>; - }; - - sgtlsound: sound { - compatible = "fsl,imx53-cpuvo-sgtl5000", - "fsl,imx-audio-sgtl5000"; - model = "imx53-cpuvo-sgtl5000"; - ssi-controller = <&ssi2>; - audio-codec = <&sgtl5000>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - mux-int-port = <2>; - mux-ext-port = <6>; - }; - - reg_sgtl5k: regulator-sgtl5k { - compatible = "regulator-fixed"; - regulator-name = "regulator-sgtl5k"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_usb_otg_vbus: regulator-usb-otg-vbus { - compatible = "regulator-fixed"; - regulator-name = "usbotg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - pinctrl-0 = <&pinctrl_usb_otg_vbus>; - gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usb_vbus: regulator-usb-vbus { - compatible = "regulator-fixed"; - regulator-name = "usbh1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - reg_usbh2_vbus: regulator-usbh2-vbus { - compatible = "regulator-fixed"; - regulator-name = "usbh2_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh2_vbus>; - gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usbh3_vbus: regulator-usbh3-vbus { - compatible = "regulator-fixed"; - regulator-name = "usbh3_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh3_vbus>; - gpio = <&gpio5 27 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_tsiref: regulator-tsiref { - compatible = "regulator-fixed"; - regulator-name = "tsiref"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - reg_3v3: regulator-3v3 { - /* TPS54320 */ - compatible = "regulator-fixed"; - regulator-name = "3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_3v3_lcd: regulator-3v3-lcd { - /* MIC2009 */ - compatible = "regulator-fixed"; - regulator-name = "LCD_3V3"; - vin-supply = <®_3v3>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - pwm_bl: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm2 0 50000>; - brightness-levels = <0 2 5 7 10 12 15 17 20 22 25 28 30 33 35 - 38 40 43 45 48 51 53 56 58 61 63 66 68 71 - 73 76 79 81 84 86 89 91 94 96 99 102 104 - 107 109 112 114 117 119 122 124 127 130 - 132 135 137 140 142 145 147 150 153 155 - 158 160 163 165 168 170 173 175 178 181 - 183 186 188 191 193 196 198 201 204 206 - 209 211 214 216 219 221 224 226 229 232 - 234 237 239 242 244 247 249 252 255>; - default-brightness-level = <0>; - enable-gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>; - power-supply = <®_3v3_lcd>; - }; - - leds { - compatible = "pwm-leds"; - - alarm-brightness { - pwms = <&pwm1 0 100000>; - max-brightness = <255>; - }; - }; - - gpio-poweroff { - compatible = "gpio-poweroff"; - gpios = <&gpio3 9 GPIO_ACTIVE_HIGH>; - }; - - gpio-restart { - compatible = "gpio-restart"; - gpios = <&gpio3 8 GPIO_ACTIVE_HIGH>; - active-delay = <100>; - inactive-delay = <10>; - wait-delay = <100>; - }; - - power-gpio-keys { - compatible = "gpio-keys"; - - power-button { - label = "Power button"; - gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>; - linux,code = ; - }; - }; - - touch-lock-key { - compatible = "gpio-keys"; - - touch-lock-button { - label = "Touch lock button"; - gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - usbphy2: usbphy-2 { - compatible = "usb-nop-xceiv"; - vcc-supply = <®_3v3>; - reset-gpios = <&gpio4 4 GPIO_ACTIVE_LOW>; - clock-names = "main_clk"; - clock-frequency = <24000000>; - clocks = <&clks IMX5_CLK_CKO2>; - assigned-clocks = <&clks IMX5_CLK_CKO2_SEL>, <&clks IMX5_CLK_OSC>; - assigned-clock-parents = <&clks IMX5_CLK_OSC>; - }; - - usbphy3: usbphy-3 { - compatible = "usb-nop-xceiv"; - vcc-supply = <®_3v3>; - reset-gpios = <&gpio2 19 GPIO_ACTIVE_LOW>; - clock-names = "main_clk"; - - clock-frequency = <24000000>; - clocks = <&clks IMX5_CLK_CKO2>; - assigned-clocks = <&clks IMX5_CLK_CKO2_SEL>, <&clks IMX5_CLK_OSC>; - assigned-clock-parents = <&clks IMX5_CLK_OSC>; - }; - - panel-lvds0 { - compatible = "nvd,9128"; - power-supply = <®_3v3_lcd>; - - port { - panel_in_lvds0: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - }; -}; - -&usbphy0 { - vcc-supply = <®_3v3>; -}; - -&usbphy1 { - vcc-supply = <®_3v3>; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; - -&cpu0 { - /* CPU rated to 1GHz, not 1.2GHz as per the default settings */ - operating-points = < - /* kHz uV */ - 166666 850000 - 400000 900000 - 800000 1050000 - 1000000 1200000 - >; -}; - -&ecspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - cs-gpios = <&gpio5 17 GPIO_ACTIVE_LOW - &gpio4 10 GPIO_ACTIVE_LOW - &gpio4 11 GPIO_ACTIVE_LOW - &gpio4 12 GPIO_ACTIVE_LOW>; - status = "okay"; - - spidev0: spi@0 { - compatible = "ge,achc"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - - spidev1: spi@1 { - compatible = "ge,achc"; - reg = <1>; - spi-max-frequency = <1000000>; - }; - - gpioxra0: gpio@2 { - compatible = "exar,xra1403"; - reg = <2>; - gpio-controller; - #gpio-cells = <2>; - spi-max-frequency = <1000000>; - }; - - gpioxra1: gpio@3 { - compatible = "exar,xra1403"; - reg = <3>; - gpio-controller; - #gpio-cells = <2>; - spi-max-frequency = <1000000>; - }; -}; - -&ecspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi2>; - cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>; - status = "okay"; - - da9053@0 { - compatible = "dlg,da9053-aa"; - reg = <0>; - interrupt-parent = <&gpio3>; - interrupts = <12 IRQ_TYPE_LEVEL_LOW>; - spi-max-frequency = <1000000>; - dlg,tsi-as-adc; - tsiref-supply = <®_tsiref>; - - regulators { - buck1_reg: buck1 { - regulator-name = "BUCKCORE"; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <2075000>; - regulator-always-on; - }; - - buck2_reg: buck2 { - regulator-name = "BUCKPRO"; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <2075000>; - regulator-always-on; - }; - - buck3_reg: buck3 { - regulator-name = "BUCKMEM"; - regulator-min-microvolt = <925000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - buck4_reg: buck4 { - regulator-name = "BUCKPERI"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3600000>; - regulator-always-on; - }; - - ldo1_reg: ldo1 { - regulator-name = "ldo1_1v3"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo2_reg: ldo2 { - regulator-name = "ldo2_1v3"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo3_reg: ldo3 { - regulator-name = "ldo3_3v3"; - regulator-min-microvolt = <1725000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo4_reg: ldo4 { - regulator-name = "ldo4_2v775"; - regulator-min-microvolt = <1725000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo5_reg: ldo5 { - regulator-name = "ldo5_3v3"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3600000>; - regulator-always-on; - }; - - ldo6_reg: ldo6 { - regulator-name = "ldo6_1v3"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3600000>; - regulator-always-on; - }; - - ldo7_reg: ldo7 { - regulator-name = "ldo7_2v75"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3600000>; - regulator-always-on; - }; - - ldo8_reg: ldo8 { - regulator-name = "ldo8_1v8"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3600000>; - regulator-always-on; - }; - - ldo9_reg: ldo9 { - regulator-name = "ldo9_1v5"; - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <3650000>; - regulator-always-on; - }; - - ldo10_reg: ldo10 { - regulator-name = "ldo10_1v3"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3600000>; - regulator-always-on; - }; - }; - }; - -}; - -&esdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc3>; - bus-width = <8>; - status = "okay"; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec>; - phy-supply = <®_3v3>; - phy-mode = "rmii"; - phy-reset-gpios = <&gpio2 16 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c1>; - pinctrl-1 = <&pinctrl_i2c1_gpio>; - sda-gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>; - scl-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; - status = "okay"; - - i2c-switch@70 { - compatible = "nxp,pca9547"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x70>; - reset-gpios = <&gpio2 18 GPIO_ACTIVE_LOW>; - - i2c4: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - sgtl5000: codec@a { - compatible = "fsl,sgtl5000"; - reg = <0xa>; - #sound-dai-cells = <0>; - VDDA-supply = <®_sgtl5k>; - VDDIO-supply = <®_sgtl5k>; - clocks = <&cko2_11M>; - status = "okay"; - }; - }; - - i2c5: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - rtc@30 { - compatible = "sii,s35390a"; - reg = <0x30>; - }; - - temp@48 { - compatible = "ti,tmp112"; - reg = <0x48>; - }; - - mma8453q: accelerometer@1c { - compatible = "fsl,mma8453"; - reg = <0x1c>; - interrupt-parent = <&gpio1>; - interrupts = <6 IRQ_TYPE_NONE>; - interrupt-names = "INT1"; - }; - - mpl3115: pressure-sensor@60 { - compatible = "fsl,mpl3115"; - reg = <0x60>; - }; - - eeprom: eeprom@50 { - compatible = "atmel,24c08"; - reg = <0x50>; - }; - }; - - i2c6: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - i2c7: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - - i2c8: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - - i2c9: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - - i2c10: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - }; - - i2c11: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - }; -}; - -&i2c2 { - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c2>; - pinctrl-1 = <&pinctrl_i2c2_gpio>; - sda-gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; - scl-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>; - status = "okay"; - - touchscreen@4b { - compatible = "atmel,maxtouch"; - reset-gpio = <&gpio5 19 GPIO_ACTIVE_HIGH>; - reg = <0x4b>; - interrupt-parent = <&gpio5>; - interrupts = <4 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&i2c3 { - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c3>; - pinctrl-1 = <&pinctrl_i2c3_gpio>; - sda-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>; - scl-gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&ldb { - status = "okay"; - - lvds0: lvds-channel@0 { - status = "okay"; - - port@2 { - lvds0_out: endpoint { - remote-endpoint = <&panel_in_lvds0>; - }; - }; - }; -}; - -&pmu { - secure-reg-access; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "okay"; -}; - -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm2>; - status = "okay"; -}; - -&ssi2 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - uart-has-rtscts; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - status = "okay"; -}; - -&usbotg { - dr_mode = "otg"; - phy_type = "utmi"; - vbus-supply = <®_usb_otg_vbus>; - pinctrl-0 = <&pinctrl_usb_otg>; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usb_vbus>; - phy_type = "utmi"; - dr_mode = "host"; - status = "okay"; -}; - -&usbh2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh2>; - phy_type = "ulpi"; - dr_mode = "host"; - fsl,usbphy = <&usbphy2>; - vbus-supply = <®_usbh2_vbus>; - status = "okay"; -}; - -&usbh3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh3>; - phy_type = "ulpi"; - dr_mode = "host"; - vbus-supply = <®_usbh3_vbus>; - fsl,usbphy = <&usbphy3>; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog_rev6>; - - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX53_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD 0x400 - MX53_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD 0x400 - MX53_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC 0x400 - MX53_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS 0x400 - MX53_PAD_DI0_PIN15__AUDMUX_AUD6_TXC 0x400 - MX53_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS 0x400 - MX53_PAD_DI0_PIN4__AUDMUX_AUD6_RXD 0x400 - MX53_PAD_DI0_PIN2__AUDMUX_AUD6_TXD 0x400 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX53_PAD_DISP0_DAT21__ECSPI1_MOSI 0x400 - MX53_PAD_DISP0_DAT22__ECSPI1_MISO 0x400 - MX53_PAD_DISP0_DAT20__ECSPI1_SCLK 0x400 - /* ECSPI1_SS0, must treat as GPIO for EzPort */ - MX53_PAD_DISP0_DAT23__GPIO5_17 0x400 - MX53_PAD_KEY_COL2__GPIO4_10 0x0 - MX53_PAD_KEY_ROW2__GPIO4_11 0x0 - MX53_PAD_KEY_COL3__GPIO4_12 0x0 - >; - }; - - pinctrl_ecspi2: ecspi2grp { - fsl,pins = < - MX53_PAD_EIM_CS1__ECSPI2_MOSI 0x0 - MX53_PAD_EIM_OE__ECSPI2_MISO 0x0 - MX53_PAD_EIM_CS0__ECSPI2_SCLK 0x0 - MX53_PAD_EIM_RW__GPIO2_26 0x0 - >; - }; - - pinctrl_esdhc1: esdhc1grp { - fsl,pins = < - MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 - MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 - MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 - MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 - MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 - MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5 - >; - }; - - pinctrl_esdhc3: esdhc3grp { - fsl,pins = < - MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5 - MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5 - MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5 - MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5 - MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5 - MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5 - MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5 - MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5 - MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5 - MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5 - >; - }; - - pinctrl_fec: fecgrp { - fsl,pins = < - MX53_PAD_FEC_MDC__FEC_MDC 0x0 - MX53_PAD_FEC_MDIO__FEC_MDIO 0x0 - MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x0 - MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x0 - MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x0 - MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x0 - MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x0 - MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x0 - MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x0 - MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x0 - >; - }; - - pinctrl_hog_rev6: hoggrp { - fsl,pins = < - /* CKO2 */ - MX53_PAD_GPIO_3__CCM_CLKO2 0x4 - /* DEFIB_SYNC_MARKER_IN_IRQ */ - MX53_PAD_GPIO_5__GPIO1_5 0x0 - /* ACCELEROMETER_DATA_RDY_N */ - MX53_PAD_GPIO_6__GPIO1_6 0x0 - /* TEMPERATURE_ALERT_N */ - MX53_PAD_GPIO_7__GPIO1_7 0x0 - /* BAROMETRIC_PRESSURE_DATA_RDY_N */ - MX53_PAD_GPIO_8__GPIO1_8 0x0 - /* DOCKING_I2C_INTERFACE_IRQ_N */ - MX53_PAD_PATA_DATA4__GPIO2_4 0x0 - /* PWR_OUT_TO_DOCK_FAULT_N */ - MX53_PAD_PATA_DATA5__GPIO2_5 0x0 - /* ENABLE_PWR_TO_DOCK_N */ - MX53_PAD_PATA_DATA6__GPIO2_6 0x0 - /* HOST_CONTROLLED_RESET_TO_DOCKING_CONNECTOR_N */ - MX53_PAD_PATA_DATA7__GPIO2_7 0x0 - /* REMOTE_ON_REQUEST_FROM_DOCKING_CONNECTOR_IS_ACTIVE_N */ - MX53_PAD_PATA_DATA12__GPIO2_12 0x0 - /* DOCK_PRESENT_N */ - MX53_PAD_PATA_DATA13__GPIO2_13 0x0 - /* ECG_MARKER_IN_FROM_DOCKING_CONNECTOR_IRQ */ - MX53_PAD_PATA_DATA14__GPIO2_14 0x0 - /* ENABLE_ECG_MARKER_INTERFACE_TO_DOCKING_CONNECTOR */ - MX53_PAD_PATA_DATA15__GPIO2_15 0x0 - /* RESET_IMX535_ETHERNET_PHY_N */ - MX53_PAD_EIM_A22__GPIO2_16 0x0 - /* ENABLE_PWR_TO_LCD_AND_UI_INTERFACE */ - MX53_PAD_EIM_A21__GPIO2_17 0x0 - /* RESET_I2C1_BUS_SEGMENT_MUX_N */ - MX53_PAD_EIM_A20__GPIO2_18 0x0 - /* RESET_IMX535_USB_HOST3_PHY_N */ - MX53_PAD_EIM_A19__GPIO2_19 0x0 - /* ESDHC3_EMMC_NAND_RST_N */ - MX53_PAD_EIM_A18__GPIO2_20 0x0 - /* LCD_AND_UI_INTERFACE_PWR_FAULT_N */ - MX53_PAD_EIM_A17__GPIO2_21 0x0 - /* POWER_DOWN_LVDS0_DESERIALIZER_N */ - MX53_PAD_EIM_A16__GPIO2_22 0x0 - /* POWER_DOWN_LVDS1_DESERIALIZER_N */ - MX53_PAD_EIM_LBA__GPIO2_27 0x0 - /* RESET_DP0_TRANSMITTER_N */ - MX53_PAD_EIM_EB0__GPIO2_28 0x0 - /* RESET_DP1_TRANSMITTER_N */ - MX53_PAD_EIM_EB1__GPIO2_29 0x0 - /* ENABLE_SPDIF_AUDIO_TO_DP0 */ - MX53_PAD_EIM_DA0__GPIO3_0 0x0 - /* ENABLE_SPDIF_AUDIO_TO_DP1 */ - MX53_PAD_EIM_DA1__GPIO3_1 0x0 - /* LVDS1_MUX_CTRL */ - MX53_PAD_EIM_DA2__GPIO3_2 0x0 - /* LVDS0_MUX_CTRL */ - MX53_PAD_EIM_DA3__GPIO3_3 0x0 - /* DP1_TRANSMITTER_IRQ */ - MX53_PAD_EIM_DA4__GPIO3_4 0x0 - /* DP0_TRANSMITTER_IRQ */ - MX53_PAD_EIM_DA5__GPIO3_5 0x0 - /* USB_RESET_N */ - MX53_PAD_EIM_DA6__GPIO3_6 0x0 - /* ENABLE_BATTERY_CHARGER */ - MX53_PAD_EIM_DA7__GPIO3_7 0x0 - /* SOFTWARE_CONTROLLED_PWR_CYCLE */ - MX53_PAD_EIM_DA8__GPIO3_8 0x0 - /* SOFTWARE_CONTROLLED_POWERDOWN */ - MX53_PAD_EIM_DA9__GPIO3_9 0x0 - /* DC_PWR_IN_OK */ - MX53_PAD_EIM_DA10__GPIO3_10 0x0 - /* BATT_PRESENT_N */ - MX53_PAD_EIM_DA11__GPIO3_11 0xe4 - /* PMIC_IRQ_N */ - MX53_PAD_EIM_DA12__GPIO3_12 0x0 - /* PMIC_VDD_FAULT_STATUS_N */ - MX53_PAD_EIM_DA13__GPIO3_13 0x0 - /* IMX535_ETHERNET_PHY_STATUS_IRQ_N */ - MX53_PAD_EIM_DA14__GPIO3_14 0x0 - /* NOT USED - AVAILABLE 3.3V GPIO */ - MX53_PAD_EIM_DA15__GPIO3_15 0x0 - /* NOT USED - AVAILABLE 3.3V GPIO */ - MX53_PAD_EIM_D22__GPIO3_22 0x0 - /* NOT USED - AVAILABLE 3.3V GPIO */ - MX53_PAD_EIM_D24__GPIO3_24 0x0 - /* NBP_PUMP_VALVE_PWR_ENABLE */ - MX53_PAD_EIM_D25__GPIO3_25 0x0 - /* NIBP_RESET_N */ - MX53_PAD_EIM_D26__GPIO3_26 0x0 - /* LATCHED_OVERPRESSURE_N */ - MX53_PAD_EIM_D27__GPIO3_27 0x0 - /* NBP_SBWTCLK */ - MX53_PAD_EIM_D29__GPIO3_29 0x0 - /* ENABLE_WIFI_MODULE */ - MX53_PAD_GPIO_11__GPIO4_1 0x400 - /* WIFI_MODULE_IRQ_N */ - MX53_PAD_GPIO_12__GPIO4_2 0x400 - /* ENABLE_BLUETOOTH_MODULE */ - MX53_PAD_GPIO_13__GPIO4_3 0x400 - /* RESET_IMX535_USB_HOST2_PHY_N */ - MX53_PAD_GPIO_14__GPIO4_4 0x400 - /* ONKEY_IS_DEPRESSED */ - MX53_PAD_KEY_ROW3__GPIO4_13 0x0 - /* UNUSED_GPIO_TO_ALARM_LIGHT_BOARD */ - MX53_PAD_EIM_WAIT__GPIO5_0 0x0 - /* DISPLAY_LOCK_BUTTON_IS_DEPRESSED_N */ - MX53_PAD_EIM_A25__GPIO5_2 0x0 - /* I2C_PCAP_TOUCHSCREEN_IRQ_N */ - MX53_PAD_EIM_A24__GPIO5_4 0x0 - /* NOT USED - AVAILABLE 1.8V GPIO */ - MX53_PAD_DISP0_DAT13__GPIO5_7 0x400 - /* NOT USED - AVAILABLE 1.8V GPIO */ - MX53_PAD_DISP0_DAT14__GPIO5_8 0x400 - /* NOT USED - AVAILABLE 1.8V GPIO */ - MX53_PAD_DISP0_DAT15__GPIO5_9 0x400 - /* HOST_CONTROLLED_RESET_TO_LCD_N */ - MX53_PAD_CSI0_PIXCLK__GPIO5_18 0x0 - /* HOST_CONTROLLED_RESET_TO_PCAP_N */ - MX53_PAD_CSI0_MCLK__GPIO5_19 0x0 - /* LR_SCAN_CTRL */ - MX53_PAD_CSI0_DATA_EN__GPIO5_20 0x0 - /* UD_SCAN_CTRL */ - MX53_PAD_CSI0_VSYNC__GPIO5_21 0x0 - /* DATA_WIDTH_CTRL */ - MX53_PAD_CSI0_DAT10__GPIO5_28 0x0 - /* BACKLIGHT_ENABLE */ - MX53_PAD_CSI0_DAT11__GPIO5_29 0x0 - /* MED_USB_PORT_1_HOST_SELECT */ - MX53_PAD_EIM_A23__GPIO6_6 0x0 - /* MED_USB_PORT_2_HOST_SELECT */ - MX53_PAD_NANDF_CLE__GPIO6_7 0x0 - /* MED_USB_PORT_3_HOST_SELECT */ - MX53_PAD_NANDF_ALE__GPIO6_8 0x0 - /* MED_USB_PORT_4_HOST_SELECT */ - MX53_PAD_NANDF_WP_B__GPIO6_9 0x0 - /* MED_USB_PORT_5_HOST_SELECT */ - MX53_PAD_NANDF_RB0__GPIO6_10 0x0 - /* MED_USB_PORT_6_HOST_SELECT */ - MX53_PAD_NANDF_CS0__GPIO6_11 0x0 - /* MED_USB_PORT_7_HOST_SELECT */ - MX53_PAD_NANDF_WE_B__GPIO6_12 0x0 - /* MED_USB_PORT_8_HOST_SELECT */ - MX53_PAD_NANDF_RE_B__GPIO6_13 0x0 - /* MED_USB_PORT_TO_IMX_SELECT_0 */ - MX53_PAD_NANDF_CS1__GPIO6_14 0x0 - /* MED_USB_PORT_TO_IMX_SELECT_1 */ - MX53_PAD_NANDF_CS2__GPIO6_15 0x0 - /* MED_USB_PORT_TO_IMX_SELECT_2 */ - MX53_PAD_NANDF_CS3__GPIO6_16 0x0 - /* POWER_AND_BOOT_STATUS_INDICATOR */ - MX53_PAD_PATA_INTRQ__GPIO7_2 0x1e4 - /* ACTIVATE_ALARM_LIGHT_RED */ - MX53_PAD_PATA_DIOR__GPIO7_3 0x0 - /* ACTIVATE_ALARM_LIGHT_YELLOW */ - MX53_PAD_PATA_DA_1__GPIO7_7 0x0 - /* ACTIVATE_ALARM_LIGHT_CYAN */ - MX53_PAD_PATA_DA_2__GPIO7_8 0x0 - /* RUNNING_ON_BATTERY_INDICATOR_GREEN */ - MX53_PAD_GPIO_16__GPIO7_11 0x0 - /* BATTERY_STATUS_INDICATOR_AMBER */ - MX53_PAD_GPIO_17__GPIO7_12 0x0 - /* AUDIO_ALARMS_SILENCED_INDICATOR */ - MX53_PAD_GPIO_18__GPIO7_13 0x0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX53_PAD_EIM_D21__I2C1_SCL 0x400001e4 - MX53_PAD_EIM_D28__I2C1_SDA 0x400001e4 - >; - }; - - pinctrl_i2c1_gpio: i2c1gpiogrp { - fsl,pins = < - MX53_PAD_EIM_D28__GPIO3_28 0x1e4 - MX53_PAD_EIM_D21__GPIO3_21 0x1e4 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX53_PAD_EIM_EB2__I2C2_SCL 0x400001e4 - MX53_PAD_EIM_D16__I2C2_SDA 0x400001e4 - >; - }; - - pinctrl_i2c2_gpio: i2c2gpiogrp { - fsl,pins = < - MX53_PAD_EIM_D16__GPIO3_16 0x1e4 - MX53_PAD_EIM_EB2__GPIO2_30 0x1e4 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX53_PAD_EIM_D17__I2C3_SCL 0x400001e4 - MX53_PAD_EIM_D18__I2C3_SDA 0x400001e4 - >; - }; - - pinctrl_i2c3_gpio: i2c3gpiogrp { - fsl,pins = < - MX53_PAD_EIM_D18__GPIO3_18 0x1e4 - MX53_PAD_EIM_D17__GPIO3_17 0x1e4 - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX53_PAD_GPIO_9__PWM1_PWMO 0x5 - >; - }; - - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX53_PAD_DISP0_DAT9__PWM2_PWMO 0x5 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4 - MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4 - MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4 - MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4 - MX53_PAD_EIM_D23__UART3_CTS 0x1e4 - MX53_PAD_EIM_EB3__UART3_RTS 0x1e4 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX53_PAD_KEY_COL0__UART4_TXD_MUX 0x1e4 - MX53_PAD_KEY_ROW0__UART4_RXD_MUX 0x1e4 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX53_PAD_KEY_COL1__UART5_TXD_MUX 0x1e4 - MX53_PAD_KEY_ROW1__UART5_RXD_MUX 0x1e4 - >; - }; - - pinctrl_usb_otg_vbus: usb-otg-vbusgrp { - fsl,pins = < - /* USB_HS_OTG_VBUS_ENABLE */ - MX53_PAD_KEY_ROW4__GPIO4_15 0x1c4 - >; - }; - - pinctrl_usbh2: usbh2grp { - fsl,pins = < - /* USB H2 */ - MX53_PAD_DISP0_DAT0__USBOH3_USBH2_DATA_0 0x180 - MX53_PAD_DISP0_DAT1__USBOH3_USBH2_DATA_1 0x180 - MX53_PAD_DISP0_DAT2__USBOH3_USBH2_DATA_2 0x180 - MX53_PAD_DISP0_DAT3__USBOH3_USBH2_DATA_3 0x180 - MX53_PAD_DISP0_DAT4__USBOH3_USBH2_DATA_4 0x180 - MX53_PAD_DISP0_DAT5__USBOH3_USBH2_DATA_5 0x180 - MX53_PAD_DISP0_DAT6__USBOH3_USBH2_DATA_6 0x180 - MX53_PAD_DISP0_DAT7__USBOH3_USBH2_DATA_7 0x180 - MX53_PAD_DISP0_DAT10__USBOH3_USBH2_STP 0x180 - MX53_PAD_DISP0_DAT11__USBOH3_USBH2_NXT 0x180 - MX53_PAD_DISP0_DAT12__USBOH3_USBH2_CLK 0x180 - MX53_PAD_DI0_DISP_CLK__USBOH3_USBH2_DIR 0x5 - MX53_PAD_EIM_D30__USBOH3_USBH2_OC 0x180 - >; - }; - - pinctrl_usbh2_vbus: usbh2-vbusgrp { - fsl,pins = < - /* USB_HS_HOST2_VBUS_ENABLE */ - MX53_PAD_EIM_D31__GPIO3_31 0x0 - >; - }; - - pinctrl_usbh3_vbus: usbh3-vbusgrp { - fsl,pins = < - /* USB_HS_HOST3_VBUS_ENABLE */ - MX53_PAD_CSI0_DAT9__GPIO5_27 0x0 - >; - }; - - pinctrl_usbh3: usbh3grp { - fsl,pins = < - /* USB H3 */ - MX53_PAD_CSI0_DAT12__USBOH3_USBH3_DATA_0 0x180 - MX53_PAD_CSI0_DAT13__USBOH3_USBH3_DATA_1 0x180 - MX53_PAD_CSI0_DAT14__USBOH3_USBH3_DATA_2 0x180 - MX53_PAD_CSI0_DAT15__USBOH3_USBH3_DATA_3 0x180 - MX53_PAD_CSI0_DAT16__USBOH3_USBH3_DATA_4 0x180 - MX53_PAD_CSI0_DAT17__USBOH3_USBH3_DATA_5 0x180 - MX53_PAD_CSI0_DAT18__USBOH3_USBH3_DATA_6 0x180 - MX53_PAD_CSI0_DAT19__USBOH3_USBH3_DATA_7 0x180 - MX53_PAD_CSI0_DAT7__USBOH3_USBH3_DIR 0x5 - MX53_PAD_CSI0_DAT6__USBOH3_USBH3_CLK 0x180 - MX53_PAD_CSI0_DAT5__USBOH3_USBH3_NXT 0x180 - MX53_PAD_CSI0_DAT4__USBOH3_USBH3_STP 0x180 - MX53_PAD_CSI0_DAT8__USBOH3_USBH3_OC 0x180 - >; - }; - - pinctrl_usb_otg: usbotggrp { - fsl,pins = < - /* USB_OTG_FAULT_N */ - MX53_PAD_KEY_COL4__USBOH3_USBOTG_OC 0x180 - >; - }; -}; diff --git a/sys/gnu/dts/arm/imx53-qsb-common.dtsi b/sys/gnu/dts/arm/imx53-qsb-common.dtsi deleted file mode 100644 index 9b4efcd8263..00000000000 --- a/sys/gnu/dts/arm/imx53-qsb-common.dtsi +++ /dev/null @@ -1,385 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// -// Copyright 2011 Freescale Semiconductor, Inc. -// Copyright 2011 Linaro Ltd. - -#include "imx53.dtsi" - -/ { - chosen { - stdout-path = &uart1; - }; - - memory@70000000 { - device_type = "memory"; - reg = <0x70000000 0x20000000>, - <0xb0000000 0x20000000>; - }; - - display0: disp0 { - compatible = "fsl,imx-parallel-display"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu_disp0>; - - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - port@0 { - reg = <0>; - - display0_in: endpoint { - remote-endpoint = <&ipu_di0_disp0>; - }; - }; - - port@1 { - reg = <1>; - - display_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - power { - label = "Power Button"; - gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - volume-up { - label = "Volume Up"; - gpios = <&gpio2 14 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - - volume-down { - label = "Volume Down"; - gpios = <&gpio2 15 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pin_gpio7_7>; - - user { - label = "Heartbeat"; - gpios = <&gpio7 7 0>; - linux,default-trigger = "heartbeat"; - }; - }; - - panel { - compatible = "sii,43wvf1g"; - - port { - panel_in: endpoint { - remote-endpoint = <&display_out>; - }; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_3p2v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "3P2V"; - regulator-min-microvolt = <3200000>; - regulator-max-microvolt = <3200000>; - regulator-always-on; - }; - - reg_usb_vbus: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "usb_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio7 8 0>; - enable-active-high; - }; - }; - - sound { - compatible = "fsl,imx53-qsb-sgtl5000", - "fsl,imx-audio-sgtl5000"; - model = "imx53-qsb-sgtl5000"; - ssi-controller = <&ssi2>; - audio-codec = <&sgtl5000>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - mux-int-port = <2>; - mux-ext-port = <5>; - }; -}; - -&cpu0 { - /* CPU rated to 1GHz, not 1.2GHz as per the default settings */ - operating-points = < - /* kHz uV */ - 166666 850000 - 400000 900000 - 800000 1050000 - 1000000 1200000 - >; -}; - -&esdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc1>; - status = "okay"; -}; - -&ipu_di0_disp0 { - remote-endpoint = <&display0_in>; -}; - -&ssi2 { - status = "okay"; -}; - -&esdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc3>; - cd-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio3 12 GPIO_ACTIVE_HIGH>; - bus-width = <8>; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - imx53-qsb { - pinctrl_hog: hoggrp { - fsl,pins = < - MX53_PAD_GPIO_8__GPIO1_8 0x80000000 - MX53_PAD_PATA_DATA14__GPIO2_14 0x80000000 - MX53_PAD_PATA_DATA15__GPIO2_15 0x80000000 - MX53_PAD_EIM_DA11__GPIO3_11 0x80000000 - MX53_PAD_EIM_DA12__GPIO3_12 0x80000000 - MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000 - MX53_PAD_PATA_DA_2__GPIO7_8 0x80000000 - MX53_PAD_GPIO_16__GPIO7_11 0x80000000 - >; - }; - - led_pin_gpio7_7: led_gpio7_7 { - fsl,pins = < - MX53_PAD_PATA_DA_1__GPIO7_7 0x80000000 - >; - }; - - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000 - MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000 - MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000 - MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000 - >; - }; - - pinctrl_codec: codecgrp { - fsl,pins = < - MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x1c4 - >; - }; - - pinctrl_esdhc1: esdhc1grp { - fsl,pins = < - MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 - MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 - MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 - MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 - MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 - MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5 - >; - }; - - pinctrl_esdhc3: esdhc3grp { - fsl,pins = < - MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5 - MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5 - MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5 - MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5 - MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5 - MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5 - MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5 - MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5 - MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5 - MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5 - >; - }; - - pinctrl_fec: fecgrp { - fsl,pins = < - MX53_PAD_FEC_MDC__FEC_MDC 0x4 - MX53_PAD_FEC_MDIO__FEC_MDIO 0x1fc - MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x180 - MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x180 - MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x180 - MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x180 - MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x180 - MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x4 - MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x4 - MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x4 - >; - }; - - /* open drain */ - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX53_PAD_CSI0_DAT8__I2C1_SDA 0x400001ec - MX53_PAD_CSI0_DAT9__I2C1_SCL 0x400001ec - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000 - MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000 - >; - }; - - pinctrl_ipu_disp0: ipudisp0grp { - fsl,pins = < - MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x5 - MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 0x5 - MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 0x5 - MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 0x5 - MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 0x5 - MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 0x5 - MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 0x5 - MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 0x5 - MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 0x5 - MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 0x5 - MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 0x5 - MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 0x5 - MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 0x5 - MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 0x5 - MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 0x5 - MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 0x5 - MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 0x5 - MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 0x5 - MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 0x5 - MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 0x5 - MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 0x5 - MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 0x5 - MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 0x5 - MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 0x5 - MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 0x5 - MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 0x5 - MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 0x5 - MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 0x5 - >; - }; - - pinctrl_vga_sync: vgasync-grp { - fsl,pins = < - /* VGA_HSYNC, VSYNC with max drive strength */ - MX53_PAD_EIM_OE__IPU_DI1_PIN7 0xe6 - MX53_PAD_EIM_RW__IPU_DI1_PIN8 0xe6 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1e4 - MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1e4 - >; - }; - }; -}; - -&tve { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_vga_sync>; - ddc-i2c-bus = <&i2c2>; - fsl,tve-mode = "vga"; - fsl,hsync-pin = <7>; /* IPU DI1 PIN7 via EIM_OE */ - fsl,vsync-pin = <8>; /* IPU DI1 PIN8 via EIM_RW */ - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - sgtl5000: codec@a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_codec>; - #sound-dai-cells = <0>; - VDDA-supply = <®_3p2v>; - VDDIO-supply = <®_3p2v>; - clocks = <&clks IMX5_CLK_SSI_EXT1_GATE>; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - accelerometer: mma8450@1c { - compatible = "fsl,mma8450"; - reg = <0x1c>; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec>; - phy-mode = "rmii"; - phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&sata { - status = "okay"; -}; - -&vpu { - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usb_vbus>; - phy_type = "utmi"; - status = "okay"; -}; - -&usbotg { - dr_mode = "peripheral"; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx53-qsb.dts b/sys/gnu/dts/arm/imx53-qsb.dts deleted file mode 100644 index 6831836bd72..00000000000 --- a/sys/gnu/dts/arm/imx53-qsb.dts +++ /dev/null @@ -1,111 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// -// Copyright 2011 Freescale Semiconductor, Inc. -// Copyright 2011 Linaro Ltd. - -/dts-v1/; -#include "imx53-qsb-common.dtsi" - -/ { - model = "Freescale i.MX53 Quick Start Board"; - compatible = "fsl,imx53-qsb", "fsl,imx53"; -}; - -&i2c1 { - pmic: dialog@48 { - compatible = "dlg,da9053-aa", "dlg,da9052"; - reg = <0x48>; - interrupt-parent = <&gpio7>; - interrupts = <11 IRQ_TYPE_LEVEL_LOW>; /* low-level active IRQ at GPIO7_11 */ - - regulators { - buck1_reg: buck1 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <2075000>; - regulator-always-on; - }; - - buck2_reg: buck2 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <2075000>; - regulator-always-on; - }; - - buck3_reg: buck3 { - regulator-min-microvolt = <925000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - buck4_reg: buck4 { - regulator-min-microvolt = <925000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - ldo1_reg: ldo1 { - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo2_reg: ldo2 { - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo3_reg: ldo3 { - regulator-min-microvolt = <1725000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo4_reg: ldo4 { - regulator-min-microvolt = <1725000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo5_reg: ldo5 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3600000>; - regulator-always-on; - }; - - ldo6_reg: ldo6 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3600000>; - regulator-always-on; - }; - - ldo7_reg: ldo7 { - regulator-min-microvolt = <2750000>; - regulator-max-microvolt = <2750000>; - }; - - ldo8_reg: ldo8 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3600000>; - regulator-always-on; - }; - - ldo9_reg: ldo9 { - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <3600000>; - regulator-always-on; - }; - - ldo10_reg: ldo10 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3600000>; - regulator-always-on; - }; - }; - }; -}; - -&tve { - dac-supply = <&ldo7_reg>; -}; diff --git a/sys/gnu/dts/arm/imx53-qsrb.dts b/sys/gnu/dts/arm/imx53-qsrb.dts deleted file mode 100644 index 1bbf24ad308..00000000000 --- a/sys/gnu/dts/arm/imx53-qsrb.dts +++ /dev/null @@ -1,149 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// -// Copyright 2011 Freescale Semiconductor, Inc. -// Copyright 2011 Linaro Ltd. - -/dts-v1/; - -#include "imx53-qsb-common.dtsi" - -/ { - model = "Freescale i.MX53 Quick Start-R Board"; - compatible = "fsl,imx53-qsrb", "fsl,imx53"; -}; - -&iomuxc { - imx53-qsrb { - pinctrl_pmic: pmicgrp { - fsl,pins = < - MX53_PAD_CSI0_DAT5__GPIO5_23 0x1c4 /* IRQ */ - >; - }; - }; -}; - -&i2c1 { - pmic: mc34708@8 { - compatible = "fsl,mc34708"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - reg = <0x08>; - interrupt-parent = <&gpio5>; - interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; - regulators { - sw1_reg: sw1a { - regulator-name = "SW1"; - regulator-min-microvolt = <650000>; - regulator-max-microvolt = <1437500>; - regulator-boot-on; - regulator-always-on; - }; - - sw1b_reg: sw1b { - regulator-name = "SW1B"; - regulator-min-microvolt = <650000>; - regulator-max-microvolt = <1437500>; - regulator-boot-on; - regulator-always-on; - }; - - sw2_reg: sw2 { - regulator-name = "SW2"; - regulator-min-microvolt = <650000>; - regulator-max-microvolt = <1437500>; - regulator-boot-on; - regulator-always-on; - }; - - sw3_reg: sw3 { - regulator-name = "SW3"; - regulator-min-microvolt = <650000>; - regulator-max-microvolt = <1425000>; - regulator-boot-on; - }; - - sw4a_reg: sw4a { - regulator-name = "SW4A"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - sw4b_reg: sw4b { - regulator-name = "SW4B"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - sw5_reg: sw5 { - regulator-name = "SW5"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - swbst_reg: swbst { - regulator-name = "SWBST"; - regulator-boot-on; - regulator-always-on; - }; - - vpll_reg: vpll { - regulator-name = "VPLL"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - }; - - vrefddr_reg: vrefddr { - regulator-name = "VREFDDR"; - regulator-boot-on; - regulator-always-on; - }; - - vusb_reg: vusb { - regulator-name = "VUSB"; - regulator-boot-on; - regulator-always-on; - }; - - vusb2_reg: vusb2 { - regulator-name = "VUSB2"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - vdac_reg: vdac { - regulator-name = "VDAC"; - regulator-min-microvolt = <2750000>; - regulator-max-microvolt = <2750000>; - }; - - vgen1_reg: vgen1 { - regulator-name = "VGEN1"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1550000>; - regulator-boot-on; - regulator-always-on; - }; - - vgen2_reg: vgen2 { - regulator-name = "VGEN2"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; -}; - -&tve { - dac-supply = <&vdac_reg>; -}; diff --git a/sys/gnu/dts/arm/imx53-smd.dts b/sys/gnu/dts/arm/imx53-smd.dts deleted file mode 100644 index ec9fb8940ff..00000000000 --- a/sys/gnu/dts/arm/imx53-smd.dts +++ /dev/null @@ -1,346 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// -// Copyright 2011 Freescale Semiconductor, Inc. -// Copyright 2011 Linaro Ltd. - -/dts-v1/; -#include -#include "imx53.dtsi" - -/ { - model = "Freescale i.MX53 Smart Mobile Reference Design Board"; - compatible = "fsl,imx53-smd", "fsl,imx53"; - - memory@70000000 { - device_type = "memory"; - reg = <0x70000000 0x40000000>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - volume-up { - label = "Volume Up"; - gpios = <&gpio2 14 0>; - linux,code = ; - }; - - volume-down { - label = "Volume Down"; - gpios = <&gpio2 15 0>; - linux,code = ; - }; - }; -}; - -&esdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc1>; - cd-gpios = <&gpio3 13 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&esdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc2>; - non-removable; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - uart-has-rtscts; - status = "okay"; -}; - -&ecspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>; - status = "okay"; - - zigbee: mc1323@0 { - compatible = "fsl,mc1323"; - spi-max-frequency = <8000000>; - reg = <0>; - }; - - flash: m25p32@1 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,m25p32", "st,m25p", "jedec,spi-nor"; - spi-max-frequency = <20000000>; - reg = <1>; - - partition@0 { - label = "U-Boot"; - reg = <0x0 0x40000>; - read-only; - }; - - partition@40000 { - label = "Kernel"; - reg = <0x40000 0x3c0000>; - }; - }; -}; - -&esdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc3>; - non-removable; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - imx53-smd { - pinctrl_hog: hoggrp { - fsl,pins = < - MX53_PAD_PATA_DATA14__GPIO2_14 0x80000000 - MX53_PAD_PATA_DATA15__GPIO2_15 0x80000000 - MX53_PAD_EIM_EB2__GPIO2_30 0x80000000 - MX53_PAD_EIM_DA13__GPIO3_13 0x80000000 - MX53_PAD_EIM_D19__GPIO3_19 0x80000000 - MX53_PAD_KEY_ROW2__GPIO4_11 0x80000000 - MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000 - MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000 - MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000 - >; - }; - - pinctrl_esdhc1: esdhc1grp { - fsl,pins = < - MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 - MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 - MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 - MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 - MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 - MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5 - >; - }; - - pinctrl_esdhc2: esdhc2grp { - fsl,pins = < - MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5 - MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5 - MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5 - MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5 - MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5 - MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5 - >; - }; - - pinctrl_esdhc3: esdhc3grp { - fsl,pins = < - MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5 - MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5 - MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5 - MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5 - MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5 - MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5 - MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5 - MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5 - MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5 - MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5 - >; - }; - - pinctrl_fec: fecgrp { - fsl,pins = < - MX53_PAD_FEC_MDC__FEC_MDC 0x80000000 - MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000 - MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000 - MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000 - MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000 - MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000 - MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000 - MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 - MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000 - MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX53_PAD_CSI0_DAT8__I2C1_SDA 0xc0000000 - MX53_PAD_CSI0_DAT9__I2C1_SCL 0xc0000000 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000 - MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000 - >; - }; - - pinctrl_ipu_csi0: ipucsi0grp { - fsl,pins = < - MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 0x1c4 - MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 0x1c4 - MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 0x1c4 - MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 0x1c4 - MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 0x1c4 - MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 0x1c4 - MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 0x1c4 - MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 0x1c4 - MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x1e4 - MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC 0x1e4 - MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC 0x1e4 - MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN 0x1e4 - >; - }; - - pinctrl_ov5642: ov5642grp { - fsl,pins = < - MX53_PAD_NANDF_WP_B__GPIO6_9 0x1e4 - MX53_PAD_NANDF_RB0__GPIO6_10 0x1e4 - MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x1c4 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1e4 - MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1e4 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4 - MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4 - MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4 - MX53_PAD_PATA_DA_1__UART3_CTS 0x1e4 - MX53_PAD_PATA_DA_2__UART3_RTS 0x1e4 - >; - }; - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - codec: sgtl5000@a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - }; - - magnetometer: mag3110@e { - compatible = "fsl,mag3110"; - reg = <0x0e>; - }; - - touchkey: mpr121@5a { - compatible = "fsl,mpr121"; - reg = <0x5a>; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - accelerometer: mma8450@1c { - compatible = "fsl,mma8450"; - reg = <0x1c>; - }; - - camera: ov5642@3c { - compatible = "ovti,ov5642"; - reg = <0x3c>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ov5642>; - assigned-clocks = <&clks IMX5_CLK_SSI_EXT1_SEL>, - <&clks IMX5_CLK_SSI_EXT1_COM_SEL>; - assigned-clock-parents = <&clks IMX5_CLK_PLL2_SW>, - <&clks IMX5_CLK_SSI_EXT1_PODF>; - assigned-clock-rates = <0>, <24000000>; - clocks = <&clks IMX5_CLK_SSI_EXT1_GATE>; - clock-names = "xclk"; - DVDD-supply = <&ldo9_reg>; - AVDD-supply = <&ldo7_reg>; - reset-gpios = <&gpio6 9 GPIO_ACTIVE_LOW>; - powerdown-gpios = <&gpio6 10 GPIO_ACTIVE_HIGH>; - - port { - ov5642_to_ipu_csi0: endpoint { - remote-endpoint = <&ipu_csi0_from_parallel_sensor>; - bus-width = <8>; - hsync-active = <1>; - vsync-active = <1>; - }; - }; - }; - - pmic: dialog@48 { - compatible = "dlg,da9053", "dlg,da9052"; - reg = <0x48>; - interrupt-parent = <&gpio7>; - interrupts = <11 IRQ_TYPE_LEVEL_LOW>; - - regulators { - ldo7_reg: ldo7 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3600000>; - }; - - ldo9_reg: ldo9 { - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <3650000>; - }; - }; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec>; - phy-mode = "rmii"; - phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&ipu_csi0_from_parallel_sensor { - remote-endpoint = <&ov5642_to_ipu_csi0>; - data-shift = <12>; /* Lines 19:12 used */ - hsync-active = <1>; - vsync-active = <1>; -}; - -&ipu_csi0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu_csi0>; -}; diff --git a/sys/gnu/dts/arm/imx53-tqma53.dtsi b/sys/gnu/dts/arm/imx53-tqma53.dtsi deleted file mode 100644 index ea90fd95ad0..00000000000 --- a/sys/gnu/dts/arm/imx53-tqma53.dtsi +++ /dev/null @@ -1,281 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2012 Sascha Hauer , Pengutronix - * Copyright 2012 Steffen Trumtrar , Pengutronix - */ - -#include "imx53.dtsi" - -/ { - model = "TQ TQMa53"; - compatible = "tq,tqma53", "fsl,imx53"; - - memory@70000000 { - device_type = "memory"; - reg = <0x70000000 0x40000000>; /* Up to 1GiB */ - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_3p3v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; -}; - -&esdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc2>, - <&pinctrl_esdhc2_cdwp>; - vmmc-supply = <®_3p3v>; - wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; - cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - status = "disabled"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "disabled"; -}; - -&ecspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>, - <&gpio3 24 0>, <&gpio3 25 0>; - status = "disabled"; -}; - -&esdhc3 { /* EMMC */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc3>; - vmmc-supply = <®_3p3v>; - non-removable; - bus-width = <8>; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - imx53-tqma53 { - pinctrl_hog: hoggrp { - fsl,pins = < - MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000 /* SSI_MCLK */ - MX53_PAD_PATA_DA_1__GPIO7_7 0x80000000 /* LCD_BLT_EN */ - MX53_PAD_PATA_DA_2__GPIO7_8 0x80000000 /* LCD_RESET */ - MX53_PAD_PATA_DATA5__GPIO2_5 0x80000000 /* LCD_POWER */ - MX53_PAD_PATA_DATA6__GPIO2_6 0x80000000 /* PMIC_INT */ - MX53_PAD_PATA_DATA14__GPIO2_14 0x80000000 /* CSI_RST */ - MX53_PAD_PATA_DATA15__GPIO2_15 0x80000000 /* CSI_PWDN */ - MX53_PAD_GPIO_19__GPIO4_5 0x80000000 /* #SYSTEM_DOWN */ - MX53_PAD_GPIO_3__GPIO1_3 0x80000000 - MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000 /* #PHY_RESET */ - MX53_PAD_GPIO_1__PWM2_PWMO 0x80000000 /* LCD_CONTRAST */ - >; - }; - - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000 - MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000 - MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000 - MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000 - >; - }; - - pinctrl_can1: can1grp { - fsl,pins = < - MX53_PAD_KEY_COL2__CAN1_TXCAN 0x80000000 - MX53_PAD_KEY_ROW2__CAN1_RXCAN 0x80000000 - >; - }; - - pinctrl_can2: can2grp { - fsl,pins = < - MX53_PAD_KEY_COL4__CAN2_TXCAN 0x80000000 - MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x80000000 - >; - }; - - pinctrl_cspi: cspigrp { - fsl,pins = < - MX53_PAD_SD1_DATA0__CSPI_MISO 0x1d5 - MX53_PAD_SD1_CMD__CSPI_MOSI 0x1d5 - MX53_PAD_SD1_CLK__CSPI_SCLK 0x1d5 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000 - MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000 - MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000 - >; - }; - - pinctrl_esdhc2: esdhc2grp { - fsl,pins = < - MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5 - MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5 - MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5 - MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5 - MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5 - MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5 - >; - }; - - pinctrl_esdhc2_cdwp: esdhc2cdwp { - fsl,pins = < - MX53_PAD_GPIO_4__GPIO1_4 0x80000000 /* SD2_CD */ - MX53_PAD_GPIO_2__GPIO1_2 0x80000000 /* SD2_WP */ - >; - }; - - pinctrl_esdhc3: esdhc3grp { - fsl,pins = < - MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5 - MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5 - MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5 - MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5 - MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5 - MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5 - MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5 - MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5 - MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5 - MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5 - >; - }; - - pinctrl_fec: fecgrp { - fsl,pins = < - MX53_PAD_FEC_MDC__FEC_MDC 0x80000000 - MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000 - MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000 - MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000 - MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000 - MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000 - MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000 - MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 - MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000 - MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000 - MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000 - MX53_PAD_GPIO_5__I2C3_SCL 0xc0000000 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4 - MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4 - MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4 - MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4 - >; - }; - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - uart-has-rtscts; - status = "disabled"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "disabled"; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can1>; - status = "disabled"; -}; - -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can2>; - status = "disabled"; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "disabled"; -}; - -&cspi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_cspi>; - cs-gpios = <&gpio1 18 0>, <&gpio1 19 0>, - <&gpio1 21 0>; - status = "disabled"; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - pmic: mc34708@8 { - compatible = "fsl,mc34708"; - reg = <0x8>; - fsl,mc13xxx-uses-rtc; - interrupt-parent = <&gpio2>; - interrupts = <6 4>; /* PATA_DATA6, active high */ - }; - - sensor1: lm75@48 { - compatible = "lm75"; - reg = <0x48>; - }; - - eeprom: 24c64@50 { - compatible = "atmel,24c64"; - pagesize = <32>; - reg = <0x50>; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec>; - phy-mode = "rmii"; - status = "disabled"; -}; diff --git a/sys/gnu/dts/arm/imx53-tx53-x03x.dts b/sys/gnu/dts/arm/imx53-tx53-x03x.dts deleted file mode 100644 index a7f77527269..00000000000 --- a/sys/gnu/dts/arm/imx53-tx53-x03x.dts +++ /dev/null @@ -1,351 +0,0 @@ -/* - * Copyright 2013-2017 Lothar Waßmann - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx53-tx53.dtsi" -#include -#include -#include - -/ { - model = "Ka-Ro electronics TX53 module (LCD)"; - compatible = "karo,tx53", "fsl,imx53"; - - aliases { - display = &display; - }; - - display: disp0 { - compatible = "fsl,imx-parallel-display"; - interface-pix-fmt = "rgb24"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rgb24_vga1>; - status = "okay"; - - port { - display0_in: endpoint { - remote-endpoint = <&ipu_di0_disp0>; - }; - }; - - display-timings { - VGA { - clock-frequency = <25200000>; - hactive = <640>; - vactive = <480>; - hback-porch = <48>; - hsync-len = <96>; - hfront-porch = <16>; - vback-porch = <31>; - vsync-len = <2>; - vfront-porch = <12>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ETV570 { - clock-frequency = <25200000>; - hactive = <640>; - vactive = <480>; - hback-porch = <114>; - hsync-len = <30>; - hfront-porch = <16>; - vback-porch = <32>; - vsync-len = <3>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ET0350 { - clock-frequency = <6413760>; - hactive = <320>; - vactive = <240>; - hback-porch = <34>; - hsync-len = <34>; - hfront-porch = <20>; - vback-porch = <15>; - vsync-len = <3>; - vfront-porch = <4>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ET0430 { - clock-frequency = <9009000>; - hactive = <480>; - vactive = <272>; - hback-porch = <2>; - hsync-len = <41>; - hfront-porch = <2>; - vback-porch = <2>; - vsync-len = <10>; - vfront-porch = <2>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - - ET0500 { - clock-frequency = <33264000>; - hactive = <800>; - vactive = <480>; - hback-porch = <88>; - hsync-len = <128>; - hfront-porch = <40>; - vback-porch = <33>; - vsync-len = <2>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ET0700 { /* same as ET0500 */ - clock-frequency = <33264000>; - hactive = <800>; - vactive = <480>; - hback-porch = <88>; - hsync-len = <128>; - hfront-porch = <40>; - vback-porch = <33>; - vsync-len = <2>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ETQ570 { - clock-frequency = <6596040>; - hactive = <320>; - vactive = <240>; - hback-porch = <38>; - hsync-len = <30>; - hfront-porch = <30>; - vback-porch = <16>; - vsync-len = <3>; - vfront-porch = <4>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - }; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>; - power-supply = <®_3v3>; - brightness-levels = < - 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100 - >; - default-brightness-level = <50>; - }; - - reg_lcd_pwr: regulator-lcd-pwr { - compatible = "regulator-fixed"; - regulator-name = "LCD POWER"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-boot-on; - }; - - reg_lcd_reset: regulator-lcd-reset { - compatible = "regulator-fixed"; - regulator-name = "LCD RESET"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio3 29 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-boot-on; - }; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - sgtl5000: codec@a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - #sound-dai-cells = <0>; - VDDA-supply = <®_2v5>; - VDDIO-supply = <®_3v3>; - clocks = <&mclk>; - }; - - polytouch: edt-ft5x06@38 { - compatible = "edt,edt-ft5x06"; - reg = <0x38>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_edt_ft5x06_1>; - interrupt-parent = <&gpio6>; - interrupts = <15 IRQ_TYPE_EDGE_FALLING>; - reset-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>; - wake-gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>; - wakeup-source; - }; - - touchscreen: tsc2007@48 { - compatible = "ti,tsc2007"; - reg = <0x48>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_tsc2007>; - interrupt-parent = <&gpio3>; - interrupts = <26 IRQ_TYPE_EDGE_FALLING>; - gpios = <&gpio3 26 GPIO_ACTIVE_LOW>; - ti,x-plate-ohms = <660>; - wakeup-source; - }; -}; - -&iomuxc { - imx53-tx53-x03x { - pinctrl_edt_ft5x06_1: edt-ft5x06grp-1 { - fsl,pins = < - MX53_PAD_NANDF_CS2__GPIO6_15 0x1f0 /* Interrupt */ - MX53_PAD_EIM_A16__GPIO2_22 0x04 /* Reset */ - MX53_PAD_EIM_A17__GPIO2_21 0x04 /* Wake */ - >; - }; - - pinctrl_kpp: kppgrp { - fsl,pins = < - MX53_PAD_GPIO_9__KPP_COL_6 0x1f4 - MX53_PAD_GPIO_4__KPP_COL_7 0x1f4 - MX53_PAD_KEY_COL2__KPP_COL_2 0x1f4 - MX53_PAD_KEY_COL3__KPP_COL_3 0x1f4 - MX53_PAD_GPIO_2__KPP_ROW_6 0x1f4 - MX53_PAD_GPIO_5__KPP_ROW_7 0x1f4 - MX53_PAD_KEY_ROW2__KPP_ROW_2 0x1f4 - MX53_PAD_KEY_ROW3__KPP_ROW_3 0x1f4 - >; - }; - - pinctrl_rgb24_vga1: rgb24-vgagrp1 { - fsl,pins = < - MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x5 - MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 0x5 - MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 0x5 - MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 0x5 - MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 0x5 - MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 0x5 - MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 0x5 - MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 0x5 - MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 0x5 - MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 0x5 - MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 0x5 - MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 0x5 - MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 0x5 - MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 0x5 - MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 0x5 - MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 0x5 - MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 0x5 - MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 0x5 - MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 0x5 - MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 0x5 - MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 0x5 - MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 0x5 - MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 0x5 - MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 0x5 - MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 0x5 - MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 0x5 - MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 0x5 - MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 0x5 - >; - }; - - pinctrl_tsc2007: tsc2007grp { - fsl,pins = < - MX53_PAD_EIM_D26__GPIO3_26 0x1f0 /* Interrupt */ - >; - }; - }; -}; - -&ipu_di0_disp0 { - remote-endpoint = <&display0_in>; -}; - -&kpp { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_kpp>; - /* sample keymap */ - /* row/col 0,1 are mapped to KPP row/col 6,7 */ - linux,keymap = < - MATRIX_KEY(6, 6, KEY_POWER) - MATRIX_KEY(6, 7, KEY_KP0) - MATRIX_KEY(6, 2, KEY_KP1) - MATRIX_KEY(6, 3, KEY_KP2) - MATRIX_KEY(7, 6, KEY_KP3) - MATRIX_KEY(7, 7, KEY_KP4) - MATRIX_KEY(7, 2, KEY_KP5) - MATRIX_KEY(7, 3, KEY_KP6) - MATRIX_KEY(2, 6, KEY_KP7) - MATRIX_KEY(2, 7, KEY_KP8) - MATRIX_KEY(2, 2, KEY_KP9) - >; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx53-tx53-x13x.dts b/sys/gnu/dts/arm/imx53-tx53-x13x.dts deleted file mode 100644 index 6cdf2082c74..00000000000 --- a/sys/gnu/dts/arm/imx53-tx53-x13x.dts +++ /dev/null @@ -1,262 +0,0 @@ -/* - * Copyright 2013-2017 Lothar Waßmann - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; -#include "imx53-tx53.dtsi" -#include - -/ { - model = "Ka-Ro electronics TX53 module (LVDS)"; - compatible = "karo,tx53", "fsl,imx53"; - - aliases { - display = &lvds0; - lvds0 = &lvds0; - lvds1 = &lvds1; - }; - - backlight0: backlight0 { - compatible = "pwm-backlight"; - pwms = <&pwm2 0 500000 0>; - power-supply = <®_3v3>; - brightness-levels = < - 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100 - >; - default-brightness-level = <50>; - }; - - backlight1: backlight1 { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 500000 0>; - power-supply = <®_3v3>; - brightness-levels = < - 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100 - >; - default-brightness-level = <50>; - }; - - reg_lcd_pwr0: regulator-lvds0-pwr { - compatible = "regulator-fixed"; - regulator-name = "LVDS0 POWER"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio3 29 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-boot-on; - }; - - reg_lcd_pwr1: regulator-lvds1-pwr { - compatible = "regulator-fixed"; - regulator-name = "LVDS1 POWER"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-boot-on; - }; -}; - -&i2c3 { - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c3>; - pinctrl-1 = <&pinctrl_i2c3_gpio>; - scl-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>; - status = "okay"; - - sgtl5000: codec@a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - #sound-dai-cells = <0>; - VDDA-supply = <®_2v5>; - VDDIO-supply = <®_3v3>; - clocks = <&mclk>; - }; -}; - -&iomuxc { - imx53-tx53-x13x { - pinctrl_lvds0: lvds0grp { - fsl,pins = < - MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000 - MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000 - MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000 - MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x80000000 - MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x80000000 - >; - }; - - pinctrl_lvds1: lvds1grp { - fsl,pins = < - MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x80000000 - MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x80000000 - MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x80000000 - MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x80000000 - MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x80000000 - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = ; - }; - - pinctrl_eeti1: eeti1grp { - fsl,pins = < - MX53_PAD_EIM_D22__GPIO3_22 0x1f0 /* Interrupt */ - >; - }; - - pinctrl_eeti2: eeti2grp { - fsl,pins = < - MX53_PAD_EIM_D23__GPIO3_23 0x1f0 /* Interrupt */ - >; - }; - }; -}; - -&ldb { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lvds0 &pinctrl_lvds1>; - status = "okay"; - - lvds0: lvds-channel@0 { - fsl,data-mapping = "spwg"; - fsl,data-width = <18>; - status = "okay"; - - display-timings { - native-mode = <&lvds0_timing0>; - - lvds0_timing0: hsd100pxn1 { - clock-frequency = <65000000>; - hactive = <1024>; - vactive = <768>; - hback-porch = <220>; - hsync-len = <60>; - hfront-porch = <40>; - vback-porch = <21>; - vsync-len = <10>; - vfront-porch = <7>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - - lvds0_timing1: nl12880bc20 { - clock-frequency = <71000000>; - hactive = <1280>; - vactive = <800>; - hback-porch = <50>; - hsync-len = <60>; - hfront-porch = <50>; - vback-porch = <5>; - vsync-len = <13>; - vfront-porch = <5>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - }; - - lvds1: lvds-channel@1 { - fsl,data-mapping = "spwg"; - fsl,data-width = <18>; - status = "okay"; - - display-timings { - native-mode = <&lvds1_timing0>; - - lvds1_timing0: hsd100pxn1 { - clock-frequency = <65000000>; - hactive = <1024>; - vactive = <768>; - hback-porch = <220>; - hsync-len = <60>; - hfront-porch = <40>; - vback-porch = <21>; - vsync-len = <10>; - vfront-porch = <7>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - }; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; -}; - -&sata { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx53-tx53.dtsi b/sys/gnu/dts/arm/imx53-tx53.dtsi deleted file mode 100644 index 4ab13590694..00000000000 --- a/sys/gnu/dts/arm/imx53-tx53.dtsi +++ /dev/null @@ -1,596 +0,0 @@ -/* - * Copyright 2012-2017 - * based on imx53-qsb.dts - * Copyright 2011 Freescale Semiconductor, Inc. - * Copyright 2011 Linaro Ltd. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "imx53.dtsi" -#include - -/ { - model = "Ka-Ro electronics TX53 module"; - compatible = "karo,tx53", "fsl,imx53"; - - /* Will be filled by the bootloader */ - memory@70000000 { - device_type = "memory"; - reg = <0x70000000 0>; - }; - - aliases { - can0 = &can2; /* Make the can interface indices consistent with TX28/TX48 modules */ - can1 = &can1; - ipu = &ipu; - reg-can-xcvr = ®_can_xcvr; - usbh1 = &usbh1; - usbotg = &usbotg; - }; - - clocks { - ckih1 { - clock-frequency = <0>; - }; - }; - - mclk: clock-mclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <26000000>; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_key>; - - power { - label = "Power Button"; - gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; - linux,code = <116>; /* KEY_POWER */ - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_stk5led>; - - user { - label = "Heartbeat"; - gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - reg_2v5: regulator-2v5 { - compatible = "regulator-fixed"; - regulator-name = "2V5"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - }; - - reg_3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_can_xcvr: regulator-can-xcvr { - compatible = "regulator-fixed"; - regulator-name = "CAN XCVR"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can_xcvr>; - gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; - }; - - reg_usbh1_vbus: regulator-usbh1-vbus { - compatible = "regulator-fixed"; - regulator-name = "usbh1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh1_vbus>; - gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usbotg_vbus: regulator-usbotg-vbus { - compatible = "regulator-fixed"; - regulator-name = "usbotg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg_vbus>; - gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - sound { - compatible = "karo,tx53-audio-sgtl5000", "fsl,imx-audio-sgtl5000"; - model = "tx53-audio-sgtl5000"; - ssi-controller = <&ssi1>; - audio-codec = <&sgtl5000>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - /* '1' based port numbers according to datasheet names */ - mux-int-port = <1>; - mux-ext-port = <5>; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ssi1>; - status = "okay"; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can1>; - xceiver-supply = <®_can_xcvr>; - status = "okay"; -}; - -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can2>; - xceiver-supply = <®_can_xcvr>; - status = "okay"; -}; - -&ecspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - status = "okay"; - - cs-gpios = < - &gpio2 30 GPIO_ACTIVE_HIGH - &gpio3 19 GPIO_ACTIVE_HIGH - >; - - spidev0: spi@0 { - compatible = "spidev"; - reg = <0>; - spi-max-frequency = <54000000>; - }; - - spidev1: spi@1 { - compatible = "spidev"; - reg = <1>; - spi-max-frequency = <54000000>; - }; -}; - -&esdhc1 { - cd-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>; - fsl,wp-controller; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc1>; - status = "okay"; -}; - -&esdhc2 { - cd-gpios = <&gpio3 25 GPIO_ACTIVE_LOW>; - fsl,wp-controller; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc2>; - status = "okay"; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec>; - phy-mode = "rmii"; - phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>; - phy-handle = <&phy0>; - mac-address = [000000000000]; /* placeholder; will be overwritten by bootloader */ - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - phy0: ethernet-phy@0 { - reg = <0>; - interrupt-parent = <&gpio2>; - interrupts = <4 IRQ_TYPE_EDGE_FALLING>; - device_type = "ethernet-phy"; - }; - }; -}; - -&i2c1 { - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c1>; - pinctrl-0 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>; - clock-frequency = <400000>; - status = "okay"; - - rtc1: ds1339@68 { - compatible = "dallas,ds1339"; - reg = <0x68>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ds1339>; - interrupt-parent = <&gpio4>; - interrupts = <20 IRQ_TYPE_EDGE_FALLING>; - trickle-resistor-ohms = <250>; - trickle-diode-disable; - }; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - imx53-tx53 { - pinctrl_hog: hoggrp { - /* pins not in use by any device on the Starterkit board series */ - fsl,pins = < - /* CMOS Sensor Interface */ - MX53_PAD_CSI0_DAT12__GPIO5_30 0x1f4 - MX53_PAD_CSI0_DAT13__GPIO5_31 0x1f4 - MX53_PAD_CSI0_DAT14__GPIO6_0 0x1f4 - MX53_PAD_CSI0_DAT15__GPIO6_1 0x1f4 - MX53_PAD_CSI0_DAT16__GPIO6_2 0x1f4 - MX53_PAD_CSI0_DAT17__GPIO6_3 0x1f4 - MX53_PAD_CSI0_DAT18__GPIO6_4 0x1f4 - MX53_PAD_CSI0_DAT19__GPIO6_5 0x1f4 - MX53_PAD_CSI0_MCLK__GPIO5_19 0x1f4 - MX53_PAD_CSI0_VSYNC__GPIO5_21 0x1f4 - MX53_PAD_CSI0_PIXCLK__GPIO5_18 0x1f4 - MX53_PAD_GPIO_0__GPIO1_0 0x1f4 - /* Module Specific Signal */ - /* MX53_PAD_NANDF_CS2__GPIO6_15 0x1f4 maybe used by EDT-FT5x06 */ - /* MX53_PAD_EIM_A16__GPIO2_22 0x1f4 maybe used by EDT-FT5x06 */ - MX53_PAD_EIM_D29__GPIO3_29 0x1f4 - MX53_PAD_EIM_EB3__GPIO2_31 0x1f4 - /* MX53_PAD_EIM_A17__GPIO2_21 0x1f4 maybe used by EDT-FT5x06 */ - /* MX53_PAD_EIM_A18__GPIO2_20 0x1f4 used by LED */ - MX53_PAD_EIM_A19__GPIO2_19 0x1f4 - MX53_PAD_EIM_A20__GPIO2_18 0x1f4 - MX53_PAD_EIM_A21__GPIO2_17 0x1f4 - MX53_PAD_EIM_A22__GPIO2_16 0x1f4 - MX53_PAD_EIM_A23__GPIO6_6 0x1f4 - MX53_PAD_EIM_A24__GPIO5_4 0x1f4 - MX53_PAD_CSI0_DAT8__GPIO5_26 0x1f4 - MX53_PAD_CSI0_DAT9__GPIO5_27 0x1f4 - MX53_PAD_CSI0_DAT10__GPIO5_28 0x1f4 - MX53_PAD_CSI0_DAT11__GPIO5_29 0x1f4 - /* MX53_PAD_EIM_D22__GPIO3_22 0x1f4 maybe used by EETI touchpanel driver */ - /* MX53_PAD_EIM_D23__GPIO3_23 0x1f4 maybe used by EETI touchpanel driver */ - MX53_PAD_GPIO_13__GPIO4_3 0x1f4 - MX53_PAD_EIM_CS0__GPIO2_23 0x1f4 - MX53_PAD_EIM_CS1__GPIO2_24 0x1f4 - MX53_PAD_CSI0_DATA_EN__GPIO5_20 0x1f4 - MX53_PAD_EIM_WAIT__GPIO5_0 0x1f4 - MX53_PAD_EIM_EB0__GPIO2_28 0x1f4 - MX53_PAD_EIM_EB1__GPIO2_29 0x1f4 - MX53_PAD_EIM_OE__GPIO2_25 0x1f4 - MX53_PAD_EIM_LBA__GPIO2_27 0x1f4 - MX53_PAD_EIM_RW__GPIO2_26 0x1f4 - MX53_PAD_EIM_DA8__GPIO3_8 0x1f4 - MX53_PAD_EIM_DA9__GPIO3_9 0x1f4 - MX53_PAD_EIM_DA10__GPIO3_10 0x1f4 - MX53_PAD_EIM_DA11__GPIO3_11 0x1f4 - MX53_PAD_EIM_DA12__GPIO3_12 0x1f4 - MX53_PAD_EIM_DA13__GPIO3_13 0x1f4 - MX53_PAD_EIM_DA14__GPIO3_14 0x1f4 - MX53_PAD_EIM_DA15__GPIO3_15 0x1f4 - >; - }; - - pinctrl_can1: can1grp { - fsl,pins = < - MX53_PAD_GPIO_7__CAN1_TXCAN 0x80000000 - MX53_PAD_GPIO_8__CAN1_RXCAN 0x80000000 - >; - }; - - pinctrl_can2: can2grp { - fsl,pins = < - MX53_PAD_KEY_COL4__CAN2_TXCAN 0x80000000 - MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x80000000 - >; - }; - - pinctrl_can_xcvr: can-xcvrgrp { - fsl,pins = ; /* Flexcan XCVR enable */ - }; - - pinctrl_ds1339: ds1339grp { - fsl,pins = ; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX53_PAD_GPIO_19__ECSPI1_RDY 0x80000000 - MX53_PAD_EIM_EB2__ECSPI1_SS0 0x80000000 - MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000 - MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000 - MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000 - MX53_PAD_EIM_D19__ECSPI1_SS1 0x80000000 - >; - }; - - pinctrl_esdhc1: esdhc1grp { - fsl,pins = < - MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 - MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 - MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 - MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 - MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 - MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5 - MX53_PAD_EIM_D24__GPIO3_24 0x1f0 - >; - }; - - pinctrl_esdhc2: esdhc2grp { - fsl,pins = < - MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5 - MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5 - MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5 - MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5 - MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5 - MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5 - MX53_PAD_EIM_D25__GPIO3_25 0x1f0 - >; - }; - - pinctrl_fec: fecgrp { - fsl,pins = < - MX53_PAD_FEC_MDC__FEC_MDC 0x80000000 - MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000 - MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000 - MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000 - MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000 - MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000 - MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000 - MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 - MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000 - MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000 - >; - }; - - pinctrl_gpio_key: gpio-keygrp { - fsl,pins = ; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX53_PAD_EIM_D21__I2C1_SCL 0x400001e4 - MX53_PAD_EIM_D28__I2C1_SDA 0x400001e4 - >; - }; - - pinctrl_i2c1_gpio: i2c1-gpiogrp { - fsl,pins = < - MX53_PAD_EIM_D21__GPIO3_21 0x400001e6 - MX53_PAD_EIM_D28__GPIO3_28 0x400001e6 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX53_PAD_GPIO_3__I2C3_SCL 0x400001e4 - MX53_PAD_GPIO_6__I2C3_SDA 0x400001e4 - >; - }; - - pinctrl_i2c3_gpio: i2c3-gpiogrp { - fsl,pins = < - MX53_PAD_GPIO_3__GPIO1_3 0x400001e6 - MX53_PAD_GPIO_6__GPIO1_6 0x400001e6 - >; - }; - - pinctrl_nand: nandgrp { - fsl,pins = < - MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 0x4 - MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 0x4 - MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 0x4 - MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 0x4 - MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 0xe0 - MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 0xe0 - MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 0x4 - MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 0xa4 - MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 0xa4 - MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 0xa4 - MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 0xa4 - MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 0xa4 - MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 0xa4 - MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 0xa4 - MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7 0xa4 - >; - }; - - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX53_PAD_GPIO_1__PWM2_PWMO 0x80000000 - >; - }; - - pinctrl_ssi1: ssi1grp { - fsl,pins = < - MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000 - MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000 - MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000 - MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000 - >; - }; - - pinctrl_ssi2: ssi2grp { - fsl,pins = < - MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC 0x80000000 - MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD 0x80000000 - MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS 0x80000000 - MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD 0x80000000 - MX53_PAD_EIM_D27__GPIO3_27 0x1f0 - >; - }; - - pinctrl_stk5led: stk5ledgrp { - fsl,pins = ; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4 - MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4 - MX53_PAD_PATA_RESET_B__UART1_CTS 0x1c5 - MX53_PAD_PATA_IORDY__UART1_RTS 0x1c5 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1c5 - MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1c5 - MX53_PAD_PATA_DIOR__UART2_RTS 0x1c5 - MX53_PAD_PATA_INTRQ__UART2_CTS 0x1c5 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4 - MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4 - MX53_PAD_PATA_DA_1__UART3_CTS 0x1e4 - MX53_PAD_PATA_DA_2__UART3_RTS 0x1e4 - >; - }; - - pinctrl_usbh1: usbh1grp { - fsl,pins = < - MX53_PAD_EIM_D30__GPIO3_30 0x100 /* OC */ - >; - }; - - pinctrl_usbh1_vbus: usbh1-vbusgrp { - fsl,pins = < - MX53_PAD_EIM_D31__GPIO3_31 0xe0 /* VBUS ENABLE */ - >; - }; - - pinctrl_usbotg_vbus: usbotg-vbusgrp { - fsl,pins = < - MX53_PAD_GPIO_7__GPIO1_7 0xe0 /* VBUS ENABLE */ - MX53_PAD_GPIO_8__GPIO1_8 0x100 /* OC */ - >; - }; - }; -}; - -&ipu { - status = "okay"; -}; - -&nfc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nand>; - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - nand-on-flash-bbt; - status = "okay"; -}; - -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm2>; - #pwm-cells = <3>; -}; - -&sdma { - fsl,sdma-ram-script-name = "sdma-imx53.bin"; -}; - -&ssi1 { - status = "okay"; -}; - -&ssi2 { - status = "disabled"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - uart-has-rtscts; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - uart-has-rtscts; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - uart-has-rtscts; - status = "okay"; -}; - -&usbh1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh1>; - phy_type = "utmi"; - disable-over-current; - vbus-supply = <®_usbh1_vbus>; - status = "okay"; -}; - -&usbotg { - phy_type = "utmi"; - dr_mode = "peripheral"; - disable-over-current; - vbus-supply = <®_usbotg_vbus>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx53-usbarmory.dts b/sys/gnu/dts/arm/imx53-usbarmory.dts deleted file mode 100644 index f34993a490e..00000000000 --- a/sys/gnu/dts/arm/imx53-usbarmory.dts +++ /dev/null @@ -1,225 +0,0 @@ -/* - * USB armory MkI device tree file - * https://inversepath.com/usbarmory - * - * Copyright (C) 2015, Inverse Path - * Andrej Rosano - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx53.dtsi" - -/ { - model = "Inverse Path USB armory"; - compatible = "inversepath,imx53-usbarmory", "fsl,imx53"; -}; - -/ { - chosen { - stdout-path = &uart1; - }; - - memory@70000000 { - device_type = "memory"; - reg = <0x70000000 0x20000000>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_led>; - - user { - label = "LED"; - gpios = <&gpio4 27 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - }; - }; -}; - -/* - * Not every i.MX53 P/N supports clock > 800MHz. - * As USB armory does not mount a specific P/N set a safe clock upper limit. - */ -&cpu0 { - operating-points = < - /* kHz */ - 166666 850000 - 400000 900000 - 800000 1050000 - >; -}; - -&esdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc1>; - status = "okay"; -}; - -&iomuxc { - pinctrl_esdhc1: esdhc1grp { - fsl,pins = < - MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 - MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 - MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 - MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 - MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 - MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5 - >; - }; - - pinctrl_i2c1_pmic: i2c1grp { - fsl,pins = < - MX53_PAD_EIM_D21__I2C1_SCL 0x80 - MX53_PAD_EIM_D28__I2C1_SDA 0x80 - >; - }; - - pinctrl_led: ledgrp { - fsl,pins = < - MX53_PAD_DISP0_DAT6__GPIO4_27 0x1e4 - >; - }; - - /* - * UART mode pin header configuration - * 3 - GPIO5[26], pull-down 100K - * 4 - GPIO5[27], pull-down 100K - * 5 - TX, pull-up 100K - * 6 - RX, pull-up 100K - * 7 - GPIO5[30], pull-down 100K - */ - pinctrl_uart1: uart1grp { - fsl,pins = < - MX53_PAD_CSI0_DAT8__GPIO5_26 0xc0 - MX53_PAD_CSI0_DAT9__GPIO5_27 0xc0 - MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1e4 - MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1e4 - MX53_PAD_CSI0_DAT12__GPIO5_30 0xc0 - >; - }; -}; - -&i2c1 { - pinctrl-0 = <&pinctrl_i2c1_pmic>; - status = "okay"; - - ltc3589: pmic@34 { - compatible = "lltc,ltc3589-2"; - reg = <0x34>; - - regulators { - sw1_reg: sw1 { - regulator-min-microvolt = <591930>; - regulator-max-microvolt = <1224671>; - lltc,fb-voltage-divider = <100000 158000>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <704123>; - regulator-max-microvolt = <1456803>; - lltc,fb-voltage-divider = <180000 191000>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3_reg: sw3 { - regulator-min-microvolt = <1341250>; - regulator-max-microvolt = <2775000>; - lltc,fb-voltage-divider = <270000 100000>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - }; - - bb_out_reg: bb-out { - regulator-min-microvolt = <3387341>; - regulator-max-microvolt = <3387341>; - lltc,fb-voltage-divider = <511000 158000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1_reg: ldo1 { - regulator-min-microvolt = <1306329>; - regulator-max-microvolt = <1306329>; - lltc,fb-voltage-divider = <100000 158000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo2_reg: ldo2 { - regulator-min-microvolt = <704123>; - regulator-max-microvolt = <1456806>; - lltc,fb-voltage-divider = <180000 191000>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo3_reg: ldo3 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-boot-on; - }; - - ldo4_reg: ldo4 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3200000>; - }; - }; - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&usbotg { - dr_mode = "peripheral"; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx53-voipac-bsb.dts b/sys/gnu/dts/arm/imx53-voipac-bsb.dts deleted file mode 100644 index ae53d178a68..00000000000 --- a/sys/gnu/dts/arm/imx53-voipac-bsb.dts +++ /dev/null @@ -1,153 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Rostislav Lisovy , PiKRON s.r.o. - */ - -/dts-v1/; -#include "imx53-voipac-dmm-668.dtsi" - -/ { - sound { - compatible = "fsl,imx53-voipac-sgtl5000", - "fsl,imx-audio-sgtl5000"; - model = "imx53-voipac-sgtl5000"; - ssi-controller = <&ssi2>; - audio-codec = <&sgtl5000>; - audio-routing = - "Headphone Jack", "HP_OUT"; - mux-int-port = <2>; - mux-ext-port = <5>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pin_gpio>; - - led1 { - label = "led-red"; - gpios = <&gpio3 29 0>; - default-state = "off"; - }; - - led2 { - label = "led-orange"; - gpios = <&gpio2 31 0>; - default-state = "off"; - }; - }; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - imx53-voipac { - pinctrl_hog: hoggrp { - fsl,pins = < - /* SD2_CD */ - MX53_PAD_EIM_D25__GPIO3_25 0x80000000 - /* SD2_WP */ - MX53_PAD_EIM_A19__GPIO2_19 0x80000000 - >; - }; - - led_pin_gpio: led_gpio { - fsl,pins = < - MX53_PAD_EIM_D29__GPIO3_29 0x80000000 - MX53_PAD_EIM_EB3__GPIO2_31 0x80000000 - >; - }; - - /* Keyboard controller */ - pinctrl_kpp_1: kppgrp-1 { - fsl,pins = < - MX53_PAD_GPIO_9__KPP_COL_6 0xe8 - MX53_PAD_GPIO_4__KPP_COL_7 0xe8 - MX53_PAD_KEY_COL2__KPP_COL_2 0xe8 - MX53_PAD_KEY_COL3__KPP_COL_3 0xe8 - MX53_PAD_KEY_COL4__KPP_COL_4 0xe8 - MX53_PAD_GPIO_2__KPP_ROW_6 0xe0 - MX53_PAD_GPIO_5__KPP_ROW_7 0xe0 - MX53_PAD_KEY_ROW2__KPP_ROW_2 0xe0 - MX53_PAD_KEY_ROW3__KPP_ROW_3 0xe0 - MX53_PAD_KEY_ROW4__KPP_ROW_4 0xe0 - >; - }; - - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000 - MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000 - MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000 - MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000 - >; - }; - - pinctrl_esdhc2: esdhc2grp { - fsl,pins = < - MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5 - MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5 - MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5 - MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5 - MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5 - MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX53_PAD_GPIO_3__I2C3_SCL 0xc0000000 - MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000 - >; - }; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; /* SSI1 */ - status = "okay"; -}; - -&esdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc2>; - cd-gpios = <&gpio3 25 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>; - vmmc-supply = <®_3p3v>; - status = "okay"; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - sgtl5000: codec@a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - #sound-dai-cells = <0>; - VDDA-supply = <®_3p3v>; - VDDIO-supply = <®_3p3v>; - clocks = <&clks 150>; - }; -}; - -&kpp { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_kpp_1>; - linux,keymap = < - 0x0203003b /* KEY_F1 */ - 0x0603003c /* KEY_F2 */ - 0x0207003d /* KEY_F3 */ - 0x0607003e /* KEY_F4 */ - >; - keypad,num-rows = <8>; - keypad,num-columns = <1>; - status = "okay"; -}; - -&ssi2 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx53-voipac-dmm-668.dtsi b/sys/gnu/dts/arm/imx53-voipac-dmm-668.dtsi deleted file mode 100644 index 289feab42b8..00000000000 --- a/sys/gnu/dts/arm/imx53-voipac-dmm-668.dtsi +++ /dev/null @@ -1,266 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Rostislav Lisovy , PiKRON s.r.o. - */ - -#include "imx53.dtsi" - -/ { - model = "Voipac i.MX53 X53-DMM-668"; - compatible = "voipac,imx53-dmm-668", "fsl,imx53"; - - memory@70000000 { - device_type = "memory"; - reg = <0x70000000 0x20000000>, - <0xb0000000 0x20000000>; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_3p3v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_usb_vbus: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "usb_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 31 0>; /* PEN */ - enable-active-high; - }; - }; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - imx53-voipac { - pinctrl_hog: hoggrp { - fsl,pins = < - /* Make DA9053 regulator functional */ - MX53_PAD_GPIO_16__GPIO7_11 0x80000000 - /* FEC Power enable */ - MX53_PAD_GPIO_11__GPIO4_1 0x80000000 - /* FEC RST */ - MX53_PAD_GPIO_12__GPIO4_2 0x80000000 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000 - MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000 - MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000 - >; - }; - - pinctrl_fec: fecgrp { - fsl,pins = < - MX53_PAD_FEC_MDC__FEC_MDC 0x80000000 - MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000 - MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000 - MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000 - MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000 - MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000 - MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000 - MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 - MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000 - MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX53_PAD_EIM_D21__I2C1_SCL 0xc0000000 - MX53_PAD_EIM_D28__I2C1_SDA 0xc0000000 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4 - MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4 - >; - }; - - pinctrl_nand: nandgrp { - fsl,pins = < - MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 0x4 - MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 0x4 - MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 0x4 - MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 0x4 - MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 0xe0 - MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 0xe0 - MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 0x4 - MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 0xa4 - MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 0xa4 - MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 0xa4 - MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 0xa4 - MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 0xa4 - MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 0xa4 - MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 0xa4 - MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 0xa4 - >; - }; - }; -}; - -&ecspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>, <&gpio2 16 0>, <&gpio2 17 0>; - status = "okay"; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec>; - phy-mode = "rmii"; - phy-reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pmic: dialog@48 { - compatible = "dlg,da9053-aa", "dlg,da9052"; - reg = <0x48>; - interrupt-parent = <&gpio7>; - interrupts = <11 IRQ_TYPE_LEVEL_LOW>; /* low-level active IRQ at GPIO7_11 */ - - regulators { - buck1_reg: buck1 { - regulator-name = "BUCKCORE"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - }; - - buck2_reg: buck2 { - regulator-name = "BUCKPRO"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - }; - - buck3_reg: buck3 { - regulator-name = "BUCKMEM"; - regulator-min-microvolt = <1420000>; - regulator-max-microvolt = <1580000>; - regulator-always-on; - }; - - buck4_reg: buck4 { - regulator-name = "BUCKPERI"; - regulator-min-microvolt = <2370000>; - regulator-max-microvolt = <2630000>; - regulator-always-on; - }; - - ldo1_reg: ldo1 { - regulator-name = "ldo1_1v3"; - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1350000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo2_reg: ldo2 { - regulator-name = "ldo2_1v3"; - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - }; - - ldo3_reg: ldo3 { - regulator-name = "ldo3_3v3"; - regulator-min-microvolt = <3250000>; - regulator-max-microvolt = <3350000>; - regulator-always-on; - }; - - ldo4_reg: ldo4 { - regulator-name = "ldo4_2v775"; - regulator-min-microvolt = <2770000>; - regulator-max-microvolt = <2780000>; - regulator-always-on; - }; - - ldo5_reg: ldo5 { - regulator-name = "ldo5_3v3"; - regulator-min-microvolt = <3250000>; - regulator-max-microvolt = <3350000>; - regulator-always-on; - }; - - ldo6_reg: ldo6 { - regulator-name = "ldo6_1v3"; - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - }; - - ldo7_reg: ldo7 { - regulator-name = "ldo7_2v75"; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - ldo8_reg: ldo8 { - regulator-name = "ldo8_1v8"; - regulator-min-microvolt = <1750000>; - regulator-max-microvolt = <1850000>; - regulator-always-on; - }; - - ldo9_reg: ldo9 { - regulator-name = "ldo9_1v5"; - regulator-min-microvolt = <1450000>; - regulator-max-microvolt = <1550000>; - regulator-always-on; - }; - - ldo10_reg: ldo10 { - regulator-name = "ldo10_1v3"; - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - }; - }; - }; -}; - -&nfc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nand>; - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usb_vbus>; - phy_type = "utmi"; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx53.dtsi b/sys/gnu/dts/arm/imx53.dtsi deleted file mode 100644 index ed341cfd9d0..00000000000 --- a/sys/gnu/dts/arm/imx53.dtsi +++ /dev/null @@ -1,855 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// -// Copyright 2011 Freescale Semiconductor, Inc. -// Copyright 2011 Linaro Ltd. - -#include "imx53-pinfunc.h" -#include -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - /* - * The decompressor and also some bootloaders rely on a - * pre-existing /chosen node to be available to insert the - * command line and merge other ATAGS info. - */ - chosen {}; - - aliases { - ethernet0 = &fec; - gpio0 = &gpio1; - gpio1 = &gpio2; - gpio2 = &gpio3; - gpio3 = &gpio4; - gpio4 = &gpio5; - gpio5 = &gpio6; - gpio6 = &gpio7; - i2c0 = &i2c1; - i2c1 = &i2c2; - i2c2 = &i2c3; - ipu0 = &ipu; - mmc0 = &esdhc1; - mmc1 = &esdhc2; - mmc2 = &esdhc3; - mmc3 = &esdhc4; - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - serial3 = &uart4; - serial4 = &uart5; - spi0 = &ecspi1; - spi1 = &ecspi2; - spi2 = &cspi; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a8"; - reg = <0x0>; - clocks = <&clks IMX5_CLK_ARM>; - clock-latency = <61036>; - voltage-tolerance = <5>; - operating-points = < - /* kHz */ - 166666 850000 - 400000 900000 - 800000 1050000 - 1000000 1200000 - 1200000 1300000 - >; - }; - }; - - display-subsystem { - compatible = "fsl,imx-display-subsystem"; - ports = <&ipu_di0>, <&ipu_di1>; - }; - - capture_subsystem { - compatible = "fsl,imx-capture-subsystem"; - ports = <&ipu_csi0>, <&ipu_csi1>; - }; - - tzic: tz-interrupt-controller@fffc000 { - compatible = "fsl,imx53-tzic", "fsl,tzic"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x0fffc000 0x4000>; - }; - - clocks { - ckil { - compatible = "fsl,imx-ckil", "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - - ckih1 { - compatible = "fsl,imx-ckih1", "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <22579200>; - }; - - ckih2 { - compatible = "fsl,imx-ckih2", "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - osc { - compatible = "fsl,imx-osc", "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - }; - }; - - pmu: pmu { - compatible = "arm,cortex-a8-pmu"; - interrupt-parent = <&tzic>; - interrupts = <77>; - }; - - usbphy0: usbphy-0 { - compatible = "usb-nop-xceiv"; - clocks = <&clks IMX5_CLK_USB_PHY1_GATE>; - clock-names = "main_clk"; - #phy-cells = <0>; - status = "okay"; - }; - - usbphy1: usbphy-1 { - compatible = "usb-nop-xceiv"; - clocks = <&clks IMX5_CLK_USB_PHY2_GATE>; - clock-names = "main_clk"; - #phy-cells = <0>; - status = "okay"; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&tzic>; - ranges; - - sata: sata@10000000 { - compatible = "fsl,imx53-ahci"; - reg = <0x10000000 0x1000>; - interrupts = <28>; - clocks = <&clks IMX5_CLK_SATA_GATE>, - <&clks IMX5_CLK_SATA_REF>, - <&clks IMX5_CLK_AHB>; - clock-names = "sata", "sata_ref", "ahb"; - status = "disabled"; - }; - - ipu: ipu@18000000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx53-ipu"; - reg = <0x18000000 0x08000000>; - interrupts = <11 10>; - clocks = <&clks IMX5_CLK_IPU_GATE>, - <&clks IMX5_CLK_IPU_DI0_GATE>, - <&clks IMX5_CLK_IPU_DI1_GATE>; - clock-names = "bus", "di0", "di1"; - resets = <&src 2>; - - ipu_csi0: port@0 { - reg = <0>; - - ipu_csi0_from_parallel_sensor: endpoint { - }; - }; - - ipu_csi1: port@1 { - reg = <1>; - - ipu_csi1_from_parallel_sensor: endpoint { - }; - }; - - ipu_di0: port@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - - ipu_di0_disp0: endpoint@0 { - reg = <0>; - }; - - ipu_di0_lvds0: endpoint@1 { - reg = <1>; - remote-endpoint = <&lvds0_in>; - }; - }; - - ipu_di1: port@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - - ipu_di1_disp1: endpoint@0 { - reg = <0>; - }; - - ipu_di1_lvds1: endpoint@1 { - reg = <1>; - remote-endpoint = <&lvds1_in>; - }; - - ipu_di1_tve: endpoint@2 { - reg = <2>; - remote-endpoint = <&tve_in>; - }; - }; - }; - - gpu: gpu@30000000 { - compatible = "amd,imageon-200.0", "amd,imageon"; - reg = <0x30000000 0x20000>; - reg-names = "kgsl_3d0_reg_memory"; - interrupts = <12>; - interrupt-names = "kgsl_3d0_irq"; - clocks = <&clks IMX5_CLK_GPU3D_GATE>, <&clks IMX5_CLK_GARB_GATE>; - clock-names = "core_clk", "mem_iface_clk"; - }; - - aips@50000000 { /* AIPS1 */ - compatible = "fsl,aips-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x50000000 0x10000000>; - ranges; - - spba@50000000 { - compatible = "fsl,spba-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x50000000 0x40000>; - ranges; - - esdhc1: esdhc@50004000 { - compatible = "fsl,imx53-esdhc"; - reg = <0x50004000 0x4000>; - interrupts = <1>; - clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>, - <&clks IMX5_CLK_DUMMY>, - <&clks IMX5_CLK_ESDHC1_PER_GATE>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - status = "disabled"; - }; - - esdhc2: esdhc@50008000 { - compatible = "fsl,imx53-esdhc"; - reg = <0x50008000 0x4000>; - interrupts = <2>; - clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>, - <&clks IMX5_CLK_DUMMY>, - <&clks IMX5_CLK_ESDHC2_PER_GATE>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - status = "disabled"; - }; - - uart3: serial@5000c000 { - compatible = "fsl,imx53-uart", "fsl,imx21-uart"; - reg = <0x5000c000 0x4000>; - interrupts = <33>; - clocks = <&clks IMX5_CLK_UART3_IPG_GATE>, - <&clks IMX5_CLK_UART3_PER_GATE>; - clock-names = "ipg", "per"; - dmas = <&sdma 42 4 0>, <&sdma 43 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - ecspi1: spi@50010000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi"; - reg = <0x50010000 0x4000>; - interrupts = <36>; - clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>, - <&clks IMX5_CLK_ECSPI1_PER_GATE>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - ssi2: ssi@50014000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx53-ssi", - "fsl,imx51-ssi", - "fsl,imx21-ssi"; - reg = <0x50014000 0x4000>; - interrupts = <30>; - clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>, - <&clks IMX5_CLK_SSI2_ROOT_GATE>; - clock-names = "ipg", "baud"; - dmas = <&sdma 24 1 0>, - <&sdma 25 1 0>; - dma-names = "rx", "tx"; - fsl,fifo-depth = <15>; - status = "disabled"; - }; - - esdhc3: esdhc@50020000 { - compatible = "fsl,imx53-esdhc"; - reg = <0x50020000 0x4000>; - interrupts = <3>; - clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>, - <&clks IMX5_CLK_DUMMY>, - <&clks IMX5_CLK_ESDHC3_PER_GATE>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - status = "disabled"; - }; - - esdhc4: esdhc@50024000 { - compatible = "fsl,imx53-esdhc"; - reg = <0x50024000 0x4000>; - interrupts = <4>; - clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>, - <&clks IMX5_CLK_DUMMY>, - <&clks IMX5_CLK_ESDHC4_PER_GATE>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - status = "disabled"; - }; - }; - - aipstz1: bridge@53f00000 { - compatible = "fsl,imx53-aipstz"; - reg = <0x53f00000 0x60>; - }; - - usbotg: usb@53f80000 { - compatible = "fsl,imx53-usb", "fsl,imx27-usb"; - reg = <0x53f80000 0x0200>; - interrupts = <18>; - clocks = <&clks IMX5_CLK_USBOH3_GATE>; - fsl,usbmisc = <&usbmisc 0>; - fsl,usbphy = <&usbphy0>; - status = "disabled"; - }; - - usbh1: usb@53f80200 { - compatible = "fsl,imx53-usb", "fsl,imx27-usb"; - reg = <0x53f80200 0x0200>; - interrupts = <14>; - clocks = <&clks IMX5_CLK_USBOH3_GATE>; - fsl,usbmisc = <&usbmisc 1>; - fsl,usbphy = <&usbphy1>; - dr_mode = "host"; - status = "disabled"; - }; - - usbh2: usb@53f80400 { - compatible = "fsl,imx53-usb", "fsl,imx27-usb"; - reg = <0x53f80400 0x0200>; - interrupts = <16>; - clocks = <&clks IMX5_CLK_USBOH3_GATE>; - fsl,usbmisc = <&usbmisc 2>; - dr_mode = "host"; - status = "disabled"; - }; - - usbh3: usb@53f80600 { - compatible = "fsl,imx53-usb", "fsl,imx27-usb"; - reg = <0x53f80600 0x0200>; - interrupts = <17>; - clocks = <&clks IMX5_CLK_USBOH3_GATE>; - fsl,usbmisc = <&usbmisc 3>; - dr_mode = "host"; - status = "disabled"; - }; - - usbmisc: usbmisc@53f80800 { - #index-cells = <1>; - compatible = "fsl,imx53-usbmisc"; - reg = <0x53f80800 0x200>; - clocks = <&clks IMX5_CLK_USBOH3_GATE>; - }; - - gpio1: gpio@53f84000 { - compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; - reg = <0x53f84000 0x4000>; - interrupts = <50 51>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@53f88000 { - compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; - reg = <0x53f88000 0x4000>; - interrupts = <52 53>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio@53f8c000 { - compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; - reg = <0x53f8c000 0x4000>; - interrupts = <54 55>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio4: gpio@53f90000 { - compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; - reg = <0x53f90000 0x4000>; - interrupts = <56 57>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - kpp: kpp@53f94000 { - compatible = "fsl,imx53-kpp", "fsl,imx21-kpp"; - reg = <0x53f94000 0x4000>; - interrupts = <60>; - clocks = <&clks IMX5_CLK_DUMMY>; - status = "disabled"; - }; - - wdog1: wdog@53f98000 { - compatible = "fsl,imx53-wdt", "fsl,imx21-wdt"; - reg = <0x53f98000 0x4000>; - interrupts = <58>; - clocks = <&clks IMX5_CLK_DUMMY>; - }; - - wdog2: wdog@53f9c000 { - compatible = "fsl,imx53-wdt", "fsl,imx21-wdt"; - reg = <0x53f9c000 0x4000>; - interrupts = <59>; - clocks = <&clks IMX5_CLK_DUMMY>; - status = "disabled"; - }; - - gpt: timer@53fa0000 { - compatible = "fsl,imx53-gpt", "fsl,imx31-gpt"; - reg = <0x53fa0000 0x4000>; - interrupts = <39>; - clocks = <&clks IMX5_CLK_GPT_IPG_GATE>, - <&clks IMX5_CLK_GPT_HF_GATE>; - clock-names = "ipg", "per"; - }; - - srtc: rtc@53fa4000 { - compatible = "fsl,imx53-rtc"; - reg = <0x53fa4000 0x4000>; - interrupts = <24>; - clocks = <&clks IMX5_CLK_SRTC_GATE>; - }; - - iomuxc: iomuxc@53fa8000 { - compatible = "fsl,imx53-iomuxc"; - reg = <0x53fa8000 0x4000>; - }; - - gpr: iomuxc-gpr@53fa8000 { - compatible = "fsl,imx53-iomuxc-gpr", "syscon"; - reg = <0x53fa8000 0xc>; - }; - - ldb: ldb@53fa8008 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx53-ldb"; - reg = <0x53fa8008 0x4>; - gpr = <&gpr>; - clocks = <&clks IMX5_CLK_LDB_DI0_SEL>, - <&clks IMX5_CLK_LDB_DI1_SEL>, - <&clks IMX5_CLK_IPU_DI0_SEL>, - <&clks IMX5_CLK_IPU_DI1_SEL>, - <&clks IMX5_CLK_LDB_DI0_GATE>, - <&clks IMX5_CLK_LDB_DI1_GATE>; - clock-names = "di0_pll", "di1_pll", - "di0_sel", "di1_sel", - "di0", "di1"; - status = "disabled"; - - lvds-channel@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - status = "disabled"; - - port@0 { - reg = <0>; - - lvds0_in: endpoint { - remote-endpoint = <&ipu_di0_lvds0>; - }; - }; - - port@2 { - reg = <2>; - }; - }; - - lvds-channel@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - status = "disabled"; - - port@1 { - reg = <1>; - - lvds1_in: endpoint { - remote-endpoint = <&ipu_di1_lvds1>; - }; - }; - - port@2 { - reg = <2>; - }; - }; - }; - - pwm1: pwm@53fb4000 { - #pwm-cells = <2>; - compatible = "fsl,imx53-pwm", "fsl,imx27-pwm"; - reg = <0x53fb4000 0x4000>; - clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>, - <&clks IMX5_CLK_PWM1_HF_GATE>; - clock-names = "ipg", "per"; - interrupts = <61>; - }; - - pwm2: pwm@53fb8000 { - #pwm-cells = <2>; - compatible = "fsl,imx53-pwm", "fsl,imx27-pwm"; - reg = <0x53fb8000 0x4000>; - clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>, - <&clks IMX5_CLK_PWM2_HF_GATE>; - clock-names = "ipg", "per"; - interrupts = <94>; - }; - - uart1: serial@53fbc000 { - compatible = "fsl,imx53-uart", "fsl,imx21-uart"; - reg = <0x53fbc000 0x4000>; - interrupts = <31>; - clocks = <&clks IMX5_CLK_UART1_IPG_GATE>, - <&clks IMX5_CLK_UART1_PER_GATE>; - clock-names = "ipg", "per"; - dmas = <&sdma 18 4 0>, <&sdma 19 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart2: serial@53fc0000 { - compatible = "fsl,imx53-uart", "fsl,imx21-uart"; - reg = <0x53fc0000 0x4000>; - interrupts = <32>; - clocks = <&clks IMX5_CLK_UART2_IPG_GATE>, - <&clks IMX5_CLK_UART2_PER_GATE>; - clock-names = "ipg", "per"; - dmas = <&sdma 12 4 0>, <&sdma 13 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - can1: can@53fc8000 { - compatible = "fsl,imx53-flexcan", "fsl,imx25-flexcan"; - reg = <0x53fc8000 0x4000>; - interrupts = <82>; - clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>, - <&clks IMX5_CLK_CAN1_SERIAL_GATE>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - can2: can@53fcc000 { - compatible = "fsl,imx53-flexcan", "fsl,imx25-flexcan"; - reg = <0x53fcc000 0x4000>; - interrupts = <83>; - clocks = <&clks IMX5_CLK_CAN2_IPG_GATE>, - <&clks IMX5_CLK_CAN2_SERIAL_GATE>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - src: src@53fd0000 { - compatible = "fsl,imx53-src", "fsl,imx51-src"; - reg = <0x53fd0000 0x4000>; - #reset-cells = <1>; - }; - - clks: ccm@53fd4000{ - compatible = "fsl,imx53-ccm"; - reg = <0x53fd4000 0x4000>; - interrupts = <0 71 0x04 0 72 0x04>; - #clock-cells = <1>; - }; - - gpio5: gpio@53fdc000 { - compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; - reg = <0x53fdc000 0x4000>; - interrupts = <103 104>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio6: gpio@53fe0000 { - compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; - reg = <0x53fe0000 0x4000>; - interrupts = <105 106>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio7: gpio@53fe4000 { - compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; - reg = <0x53fe4000 0x4000>; - interrupts = <107 108>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - i2c3: i2c@53fec000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx53-i2c", "fsl,imx21-i2c"; - reg = <0x53fec000 0x4000>; - interrupts = <64>; - clocks = <&clks IMX5_CLK_I2C3_GATE>; - status = "disabled"; - }; - - uart4: serial@53ff0000 { - compatible = "fsl,imx53-uart", "fsl,imx21-uart"; - reg = <0x53ff0000 0x4000>; - interrupts = <13>; - clocks = <&clks IMX5_CLK_UART4_IPG_GATE>, - <&clks IMX5_CLK_UART4_PER_GATE>; - clock-names = "ipg", "per"; - dmas = <&sdma 2 4 0>, <&sdma 3 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - }; - - aips@60000000 { /* AIPS2 */ - compatible = "fsl,aips-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x60000000 0x10000000>; - ranges; - - aipstz2: bridge@63f00000 { - compatible = "fsl,imx53-aipstz"; - reg = <0x63f00000 0x60>; - }; - - iim: iim@63f98000 { - compatible = "fsl,imx53-iim", "fsl,imx27-iim"; - reg = <0x63f98000 0x4000>; - interrupts = <69>; - clocks = <&clks IMX5_CLK_IIM_GATE>; - }; - - uart5: serial@63f90000 { - compatible = "fsl,imx53-uart", "fsl,imx21-uart"; - reg = <0x63f90000 0x4000>; - interrupts = <86>; - clocks = <&clks IMX5_CLK_UART5_IPG_GATE>, - <&clks IMX5_CLK_UART5_PER_GATE>; - clock-names = "ipg", "per"; - dmas = <&sdma 16 4 0>, <&sdma 17 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - tigerp: tigerp@63fa0000 { - compatible = "fsl,imx53-tigerp", "fsl,imx51-tigerp"; - reg = <0x63fa0000 0x28>; - }; - - owire: owire@63fa4000 { - compatible = "fsl,imx53-owire", "fsl,imx21-owire"; - reg = <0x63fa4000 0x4000>; - clocks = <&clks IMX5_CLK_OWIRE_GATE>; - status = "disabled"; - }; - - ecspi2: spi@63fac000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi"; - reg = <0x63fac000 0x4000>; - interrupts = <37>; - clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>, - <&clks IMX5_CLK_ECSPI2_PER_GATE>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - sdma: sdma@63fb0000 { - compatible = "fsl,imx53-sdma", "fsl,imx35-sdma"; - reg = <0x63fb0000 0x4000>; - interrupts = <6>; - clocks = <&clks IMX5_CLK_SDMA_GATE>, - <&clks IMX5_CLK_AHB>; - clock-names = "ipg", "ahb"; - #dma-cells = <3>; - fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin"; - }; - - cspi: spi@63fc0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx53-cspi", "fsl,imx35-cspi"; - reg = <0x63fc0000 0x4000>; - interrupts = <38>; - clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>, - <&clks IMX5_CLK_CSPI_IPG_GATE>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - i2c2: i2c@63fc4000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx53-i2c", "fsl,imx21-i2c"; - reg = <0x63fc4000 0x4000>; - interrupts = <63>; - clocks = <&clks IMX5_CLK_I2C2_GATE>; - status = "disabled"; - }; - - i2c1: i2c@63fc8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx53-i2c", "fsl,imx21-i2c"; - reg = <0x63fc8000 0x4000>; - interrupts = <62>; - clocks = <&clks IMX5_CLK_I2C1_GATE>; - status = "disabled"; - }; - - ssi1: ssi@63fcc000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx53-ssi", "fsl,imx51-ssi", - "fsl,imx21-ssi"; - reg = <0x63fcc000 0x4000>; - interrupts = <29>; - clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>, - <&clks IMX5_CLK_SSI1_ROOT_GATE>; - clock-names = "ipg", "baud"; - dmas = <&sdma 28 0 0>, - <&sdma 29 0 0>; - dma-names = "rx", "tx"; - fsl,fifo-depth = <15>; - status = "disabled"; - }; - - audmux: audmux@63fd0000 { - compatible = "fsl,imx53-audmux", "fsl,imx31-audmux"; - reg = <0x63fd0000 0x4000>; - status = "disabled"; - }; - - nfc: nand@63fdb000 { - compatible = "fsl,imx53-nand"; - reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>; - interrupts = <8>; - clocks = <&clks IMX5_CLK_NFC_GATE>; - status = "disabled"; - }; - - ssi3: ssi@63fe8000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx53-ssi", "fsl,imx51-ssi", - "fsl,imx21-ssi"; - reg = <0x63fe8000 0x4000>; - interrupts = <96>; - clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>, - <&clks IMX5_CLK_SSI3_ROOT_GATE>; - clock-names = "ipg", "baud"; - dmas = <&sdma 46 0 0>, - <&sdma 47 0 0>; - dma-names = "rx", "tx"; - fsl,fifo-depth = <15>; - status = "disabled"; - }; - - fec: ethernet@63fec000 { - compatible = "fsl,imx53-fec", "fsl,imx25-fec"; - reg = <0x63fec000 0x4000>; - interrupts = <87>; - clocks = <&clks IMX5_CLK_FEC_GATE>, - <&clks IMX5_CLK_FEC_GATE>, - <&clks IMX5_CLK_FEC_GATE>; - clock-names = "ipg", "ahb", "ptp"; - status = "disabled"; - }; - - tve: tve@63ff0000 { - compatible = "fsl,imx53-tve"; - reg = <0x63ff0000 0x1000>; - interrupts = <92>; - clocks = <&clks IMX5_CLK_TVE_GATE>, - <&clks IMX5_CLK_IPU_DI1_SEL>; - clock-names = "tve", "di_sel"; - status = "disabled"; - - port { - tve_in: endpoint { - remote-endpoint = <&ipu_di1_tve>; - }; - }; - }; - - vpu: vpu@63ff4000 { - compatible = "fsl,imx53-vpu", "cnm,coda7541"; - reg = <0x63ff4000 0x1000>; - interrupts = <9>; - clocks = <&clks IMX5_CLK_VPU_REFERENCE_GATE>, - <&clks IMX5_CLK_VPU_GATE>; - clock-names = "per", "ahb"; - resets = <&src 1>; - iram = <&ocram>; - }; - - sahara: crypto@63ff8000 { - compatible = "fsl,imx53-sahara"; - reg = <0x63ff8000 0x4000>; - interrupts = <19 20>; - clocks = <&clks IMX5_CLK_SAHARA_IPG_GATE>, - <&clks IMX5_CLK_SAHARA_IPG_GATE>; - clock-names = "ipg", "ahb"; - }; - }; - - ocram: sram@f8000000 { - compatible = "mmio-sram"; - reg = <0xf8000000 0x20000>; - clocks = <&clks IMX5_CLK_OCRAM>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/imx6-logicpd-baseboard.dtsi b/sys/gnu/dts/arm/imx6-logicpd-baseboard.dtsi deleted file mode 100644 index 9e027b9a5f9..00000000000 --- a/sys/gnu/dts/arm/imx6-logicpd-baseboard.dtsi +++ /dev/null @@ -1,561 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// -// Copyright (C) 2019 Logic PD, Inc. - -/ { - keyboard { - compatible = "gpio-keys"; - - btn0 { - gpios = <&pcf8575 0 GPIO_ACTIVE_LOW>; - label = "btn0"; - linux,code = ; - debounce-interval = <10>; - wakeup-source; - }; - - btn1 { - gpios = <&pcf8575 1 GPIO_ACTIVE_LOW>; - label = "btn1"; - linux,code = ; - debounce-interval = <10>; - wakeup-source; - }; - - btn2 { - gpios = <&pcf8575 2 GPIO_ACTIVE_LOW>; - label = "btn2"; - linux,code = ; - debounce-interval = <10>; - wakeup-source; - }; - - btn3 { - gpios = <&pcf8575 3 GPIO_ACTIVE_LOW>; - label = "btn3"; - linux,code = ; - debounce-interval = <10>; - wakeup-source; - }; - - }; - - leds { - compatible = "gpio-leds"; - - gen-led0 { - label = "led0"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_led0>; - gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "cpu0"; - }; - - gen-led1 { - label = "led1"; - gpios = <&pcf8575 8 GPIO_ACTIVE_HIGH>; - }; - - gen-led2 { - label = "led2"; - gpios = <&pcf8575 9 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - - gen-led3 { - label = "led3"; - gpios = <&pcf8575 10 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - }; - }; - - reg_usb_otg_vbus: regulator-otg-vbus { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usb_otg>; - compatible = "regulator-fixed"; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usb_h1_vbus: regulator-usb-h1-vbus { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usb_h1_vbus>; - compatible = "regulator-fixed"; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>; - startup-delay-us = <70000>; - enable-active-high; - }; - - reg_3v3: regulator-3v3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_3v3>; - compatible = "regulator-fixed"; - regulator-name = "reg_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>; - startup-delay-us = <70000>; - enable-active-high; - regulator-always-on; - }; - - reg_enet: regulator-ethernet { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_enet>; - compatible = "regulator-fixed"; - regulator-name = "ethernet-supply"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; - startup-delay-us = <70000>; - enable-active-high; - vin-supply = <&sw4_reg>; - }; - - reg_audio: regulator-audio { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_audio>; - compatible = "regulator-fixed"; - regulator-name = "3v3_aud"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <®_3v3>; - }; - - reg_hdmi: regulator-hdmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_hdmi>; - compatible = "regulator-fixed"; - regulator-name = "hdmi-supply"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <®_3v3>; - }; - - reg_uart3: regulator-uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_uart3>; - compatible = "regulator-fixed"; - regulator-name = "uart3-supply"; - gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - vin-supply = <®_3v3>; - }; - - reg_1v8: regulator-1v8 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_1v8>; - compatible = "regulator-fixed"; - regulator-name = "1v8-supply"; - gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - vin-supply = <®_3v3>; - }; - - reg_pcie: regulator-pcie { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_pcie>; - regulator-name = "mpcie_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_mipi: regulator-mipi { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_mipi>; - regulator-name = "mipi_pwr_en"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - sound { - compatible = "fsl,imx-audio-wm8962"; - model = "wm8962-audio"; - ssi-controller = <&ssi2>; - audio-codec = <&wm8962>; - audio-routing = - "Headphone Jack", "HPOUTL", - "Headphone Jack", "HPOUTR", - "Ext Spk", "SPKOUTL", - "Ext Spk", "SPKOUTR", - "AMIC", "MICBIAS", - "IN3R", "AMIC"; - mux-int-port = <2>; - mux-ext-port = <4>; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; - -&ecspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - status = "disabled"; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii-id"; - phy-reset-duration = <10>; - phy-reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; - phy-supply = <®_enet>; - interrupt-parent = <&gpio1>; - interrupts = <25 IRQ_TYPE_EDGE_FALLING>; - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - clock-frequency = <400000>; - status = "okay"; - - wm8962: audio-codec@1a { - compatible = "wlf,wm8962"; - reg = <0x1a>; - clocks = <&clks IMX6QDL_CLK_CKO>; - clock-names = "xclk"; - DCVDD-supply = <®_audio>; - DBVDD-supply = <®_audio>; - AVDD-supply = <®_audio>; - CPVDD-supply = <®_audio>; - MICVDD-supply = <®_audio>; - PLLVDD-supply = <®_audio>; - SPKVDD1-supply = <®_audio>; - SPKVDD2-supply = <®_audio>; - gpio-cfg = < - 0x0000 /* 0:Default */ - 0x0000 /* 1:Default */ - 0x0000 /* 2:FN_DMICCLK */ - 0x0000 /* 3:Default */ - 0x0000 /* 4:FN_DMICCDAT */ - 0x0000 /* 5:Default */ - >; - }; -}; - -&i2c3 { - ov5640: camera@10 { - compatible = "ovti,ov5640"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ov5640>; - reg = <0x10>; - clocks = <&clks IMX6QDL_CLK_CKO>; - clock-names = "xclk"; - DOVDD-supply = <®_mipi>; - AVDD-supply = <®_mipi>; - DVDD-supply = <®_mipi>; - reset-gpios = <&gpio3 26 GPIO_ACTIVE_LOW>; - powerdown-gpios = <&gpio3 27 GPIO_ACTIVE_HIGH>; - - port { - ov5640_to_mipi_csi2: endpoint { - remote-endpoint = <&mipi_csi2_in>; - clock-lanes = <0>; - data-lanes = <1 2>; - }; - }; - }; - - pcf8575: gpio@20 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcf8574>; - compatible = "nxp,pcf8575"; - reg = <0x20>; - interrupt-parent = <&gpio6>; - interrupts = <31 IRQ_TYPE_EDGE_FALLING>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - lines-initial-states = <0x0710>; - wakeup-source; - }; -}; - -&ipu1_csi1_from_mipi_vc1 { - clock-lanes = <0>; - data-lanes = <1 2>; -}; - -&mipi_csi { - status = "okay"; - - port@0 { - reg = <0>; - - mipi_csi2_in: endpoint { - remote-endpoint = <&ov5640_to_mipi_csi2>; - clock-lanes = <0>; - data-lanes = <1 2>; - }; - }; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio1 9 GPIO_ACTIVE_LOW>; - vpcie-supply = <®_pcie>; - status = "okay"; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; -}; - -&snvs_pwrkey { - status = "okay"; -}; - -&ssi2 { - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usb_h1_vbus>; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - dr_mode = "otg"; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>; - vmmc-supply = <®_3v3>; - no-1-8-v; - keep-power-in-suspend; - cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&iomuxc { - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0 - MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x110b0 - MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0 - MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1 - MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_KEY_ROW1__ECSPI1_SS0 0x100b1 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b8b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x13030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030 - MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 /* ENET_INT */ - MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x1b0b0 /* ETHR_nRST */ - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_led0: led0grp { - fsl,pins = < - MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 - >; - }; - - pinctrl_ov5640: ov5640grp { - fsl,pins = < - MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x1b0b1 - MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x1b0b1 - >; - }; - - pinctrl_pcf8574: pcf8575grp { - fsl,pins = < - MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b0 - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = < - MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 - MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 - >; - }; - - pinctrl_reg_1v8: reg1v8grp { - fsl,pins = < - MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x1b0b0 - >; - }; - - pinctrl_reg_3v3: reg3v3grp { - fsl,pins = < - MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b0 - >; - }; - - pinctrl_reg_audio: reg-audiogrp { - fsl,pins = < - MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 - >; - }; - - pinctrl_reg_enet: reg-enetgrp { - fsl,pins = < - MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b0 - >; - }; - - pinctrl_reg_hdmi: reg-hdmigrp { - fsl,pins = < - MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b0 - >; - }; - - pinctrl_reg_mipi: reg-mipigrp { - fsl,pins = ; - }; - - pinctrl_reg_pcie: reg-pciegrp { - fsl,pins = < - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 - >; - }; - - pinctrl_reg_uart3: reguart3grp { - fsl,pins = < - MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 - >; - }; - - pinctrl_reg_usb_h1_vbus: usbh1grp { - fsl,pins = < - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 - >; - }; - - pinctrl_reg_usb_otg: reg-usb-otggrp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0xd17059 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* CD */ - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17069 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10069 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17069 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17069 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17069 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17069 - >; - }; - - pinctrl_usdhc2_100mhz: h100-usdhc2-100mhz { - fsl,pins = < - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* CD */ - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 - >; - }; - - pinctrl_usdhc2_200mhz: h100-usdhc2-200mhz { - fsl,pins = < - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* CD */ - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170f9 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100f9 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170f9 - >; - }; - -}; diff --git a/sys/gnu/dts/arm/imx6-logicpd-som.dtsi b/sys/gnu/dts/arm/imx6-logicpd-som.dtsi deleted file mode 100644 index 547fb141ec0..00000000000 --- a/sys/gnu/dts/arm/imx6-logicpd-som.dtsi +++ /dev/null @@ -1,369 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// -// Copyright (C) 2019 Logic PD, Inc. - -#include -#include - -/ { - chosen { - stdout-path = &uart1; - }; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x80000000>; - }; - - reg_wl18xx_vmmc: regulator-wl18xx { - compatible = "regulator-fixed"; - regulator-name = "vwl1837"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio7 0 GPIO_ACTIVE_HIGH>; - startup-delay-us = <70000>; - enable-active-high; - }; -}; - -&clks { - assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, - <&clks IMX6QDL_CLK_LDB_DI1_SEL>; - assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, - <&clks IMX6QDL_CLK_PLL3_USB_OTG>; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - nand-on-flash-bbt; - status = "okay"; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - pfuze100: pmic@8 { - compatible = "fsl,pfuze100"; - reg = <0x08>; - - regulators { - sw1a_reg: sw1ab { - regulator-min-microvolt = <725000>; - regulator-max-microvolt = <1450000>; - regulator-name = "vddcore"; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw1c_reg: sw1c { - regulator-min-microvolt = <725000>; - regulator-max-microvolt = <1450000>; - regulator-name = "vddsoc"; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "gen_3v3"; - regulator-boot-on; - }; - - sw3a_reg: sw3a { - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-name = "sw3a_vddr"; - regulator-boot-on; - regulator-always-on; - }; - - sw3b_reg: sw3b { - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-name = "sw3b_vddr"; - regulator-boot-on; - regulator-always-on; - }; - - sw4_reg: sw4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-name = "gen_rgmii"; - }; - - swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - regulator-name = "gen_5v0"; - }; - - snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "gen_vsns"; - regulator-boot-on; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - vgen1_reg: vgen1 { - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-name = "gen_1v5"; - }; - - vgen2_reg: vgen2 { - regulator-name = "vgen2"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen3_reg: vgen3 { - regulator-name = "gen_vadj_0"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - vgen4_reg: vgen4 { - regulator-name = "gen_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vgen5_reg: vgen5 { - regulator-name = "gen_vadj_1"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen6_reg: vgen6 { - regulator-name = "gen_2v5"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - coin_reg: coin { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - }; - }; - }; - - temperature-sensor@49 { - compatible = "ti,tmp102"; - reg = <0x49>; - interrupt-parent = <&gpio6>; - interrupts = <15 IRQ_TYPE_LEVEL_LOW>; - #thermal-sensor-cells = <1>; - }; - - temperature-sensor@4a { - compatible = "ti,tmp102"; - reg = <0x4a>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_tempsense>; - interrupt-parent = <&gpio6>; - interrupts = <15 IRQ_TYPE_LEVEL_LOW>; - #thermal-sensor-cells = <1>; - }; - - eeprom@51 { - compatible = "atmel,24c64"; - pagesize = <32>; - read-only; /* Manufacturing EEPROM programmed at factory */ - reg = <0x51>; - }; - - eeprom@52 { - compatible = "atmel,24c64"; - pagesize = <32>; - reg = <0x52>; - }; -}; - -/* Reroute power feeding the CPU to come from the external PMIC */ -®_arm -{ - vin-supply = <&sw1a_reg>; -}; - -®_soc -{ - vin-supply = <&sw1c_reg>; -}; - -&snvs_poweroff { - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_gpmi_nand: gpmi-nandgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0x0b0b1 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0x0b0b1 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0x0b0b1 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0x0b000 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0x0b0b1 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0x0b0b1 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0x0b0b1 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0x0b0b1 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0x0b0b1 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0x0b0b1 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0x0b0b1 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0x0b0b1 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0x0b0b1 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0x0b0b1 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0x0b0b1 - >; - }; - - pinctrl_hog: hoggrp { - fsl,pins = < /* Enable ARM Debugger */ - MX6QDL_PAD_CSI0_MCLK__ARM_TRACE_CTL 0x1b0b0 - MX6QDL_PAD_CSI0_PIXCLK__ARM_EVENTO 0x1b0b0 - MX6QDL_PAD_CSI0_VSYNC__ARM_TRACE00 0x1b0b0 - MX6QDL_PAD_CSI0_DATA_EN__ARM_TRACE_CLK 0x1b0b0 - MX6QDL_PAD_CSI0_DAT4__ARM_TRACE01 0x1b0b0 - MX6QDL_PAD_CSI0_DAT5__ARM_TRACE02 0x1b0b0 - MX6QDL_PAD_CSI0_DAT6__ARM_TRACE03 0x1b0b0 - MX6QDL_PAD_CSI0_DAT7__ARM_TRACE04 0x1b0b0 - MX6QDL_PAD_CSI0_DAT8__ARM_TRACE05 0x1b0b0 - MX6QDL_PAD_CSI0_DAT9__ARM_TRACE06 0x1b0b0 - MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x1b0b0 - MX6QDL_PAD_CSI0_DAT11__ARM_TRACE08 0x1b0b0 - MX6QDL_PAD_CSI0_DAT12__ARM_TRACE09 0x1b0b0 - MX6QDL_PAD_CSI0_DAT13__ARM_TRACE10 0x1b0b0 - MX6QDL_PAD_CSI0_DAT14__ARM_TRACE11 0x1b0b0 - MX6QDL_PAD_CSI0_DAT15__ARM_TRACE12 0x1b0b0 - MX6QDL_PAD_CSI0_DAT16__ARM_TRACE13 0x1b0b0 - MX6QDL_PAD_CSI0_DAT17__ARM_TRACE14 0x1b0b0 - MX6QDL_PAD_CSI0_DAT18__ARM_TRACE15 0x1b0b0 - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_tempsense: tempsensegrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x13059 /* BT_EN */ - MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1 - MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1 - MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170B9 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100B9 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170B9 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170B9 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170B9 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170B9 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17049 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10049 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17049 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17049 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17049 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17049 - MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x130b0 /* WL_IRQ */ - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* WLAN_EN */ - >; - }; -}; - -&snvs_poweroff { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - uart-has-rtscts; - status = "okay"; - - bluetooth { - compatible = "ti,wl1837-st"; - enable-gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>; - }; -}; - -&usdhc1 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>; - non-removable; - keep-power-in-suspend; - wakeup-source; - vmmc-supply = <&sw2_reg>; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - non-removable; - cap-power-off-card; - keep-power-in-suspend; - wakeup-source; - vmmc-supply = <®_wl18xx_vmmc>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - wlcore: wlcore@2 { - compatible = "ti,wl1837"; - reg = <2>; - interrupt-parent = <&gpio7>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; - tcxo-clock-frequency = <26000000>; - }; -}; diff --git a/sys/gnu/dts/arm/imx6dl-apf6dev.dts b/sys/gnu/dts/arm/imx6dl-apf6dev.dts deleted file mode 100644 index 3dcce3454b0..00000000000 --- a/sys/gnu/dts/arm/imx6dl-apf6dev.dts +++ /dev/null @@ -1,18 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -// -// Copyright 2015 Armadeus Systems - -/dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-apf6.dtsi" -#include "imx6qdl-apf6dev.dtsi" - -/ { - model = "Armadeus APF6 Solo Module on APF6Dev Board"; - compatible = "armadeus,imx6dl-apf6dev", "armadeus,imx6dl-apf6", "fsl,imx6dl"; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x20000000>; - }; -}; diff --git a/sys/gnu/dts/arm/imx6dl-aristainetos2_4.dts b/sys/gnu/dts/arm/imx6dl-aristainetos2_4.dts deleted file mode 100644 index b16603f27dc..00000000000 --- a/sys/gnu/dts/arm/imx6dl-aristainetos2_4.dts +++ /dev/null @@ -1,158 +0,0 @@ -/* - * support for the imx6 based aristainetos2 board - * - * Copyright (C) 2015 Heiko Schocher - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -/dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-aristainetos2.dtsi" - -/ { - model = "aristainetos2 i.MX6 Dual Lite Board 4"; - compatible = "fsl,imx6dl"; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x40000000>; - }; - - display0: disp0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx-parallel-display"; - interface-pix-fmt = "rgb24"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu_disp>; - - port@0 { - reg = <0>; - display0_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - - port@1 { - reg = <1>; - display_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; -}; - -&ecspi1 { - lcd_panel: display@0 { - compatible = "lg,lg4573"; - spi-max-frequency = <10000000>; - reg = <0>; - power-on-delay = <10>; - - display-timings { - 480x800p57 { - native-mode; - clock-frequency = <27000027>; - hactive = <480>; - vactive = <800>; - hfront-porch = <10>; - hback-porch = <59>; - hsync-len = <10>; - vback-porch = <15>; - vfront-porch = <15>; - vsync-len = <15>; - hsync-active = <1>; - vsync-active = <1>; - }; - }; - - port { - panel_in: endpoint { - remote-endpoint = <&display_out>; - }; - }; - }; -}; - -&i2c3 { - touch: touch@4b { - compatible = "atmel,maxtouch"; - reg = <0x4b>; - interrupt-parent = <&gpio2>; - interrupts = <9 8>; - }; -}; - -&ipu1_di0_disp0 { - remote-endpoint = <&display0_in>; -}; - -&iomuxc { - pinctrl_ipu_disp: ipudisp1grp { - fsl,pins = < - MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x31 - MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0xE1 - MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 - MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 - MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0xE1 - MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0xE1 - MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0xE1 - MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0xE1 - MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0xE1 - MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0xE1 - MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0xE1 - MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0xE1 - MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0xE1 - MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0xE1 - MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0xE1 - MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0xE1 - MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0xE1 - MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0xE1 - MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0xe1 - MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0xE1 - MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0xE1 - MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0xE1 - MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0xE1 - MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0xE1 - MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0xE1 - MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0xE1 - MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0xE1 - MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0xE1 - >; - }; -}; diff --git a/sys/gnu/dts/arm/imx6dl-aristainetos2_7.dts b/sys/gnu/dts/arm/imx6dl-aristainetos2_7.dts deleted file mode 100644 index abb2a1b9ce0..00000000000 --- a/sys/gnu/dts/arm/imx6dl-aristainetos2_7.dts +++ /dev/null @@ -1,98 +0,0 @@ -/* - * support for the imx6 based aristainetos2 board - * - * Copyright (C) 2015 Heiko Schocher - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -/dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-aristainetos2.dtsi" - -/ { - model = "aristainetos2 i.MX6 Dual Lite Board 7"; - compatible = "fsl,imx6dl"; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x40000000>; - }; - - panel: panel { - compatible = "lg,lb070wv8"; - backlight = <&backlight>; - enable-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>; - - port { - panel_in: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - }; -}; - -&i2c3 { - touch: touch@4d { - compatible = "atmel,maxtouch"; - reg = <0x4d>; - interrupt-parent = <&gpio2>; - interrupts = <9 8>; - }; -}; - -&ldb { - status = "okay"; - - lvds-channel@0 { - status = "okay"; - - port@0 { - reg = <0>; - lvds0_in: endpoint { - remote-endpoint = <&ipu1_di0_lvds0>; - }; - }; - - port@4 { - reg = <4>; - lvds0_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/imx6dl-aristainetos_4.dts b/sys/gnu/dts/arm/imx6dl-aristainetos_4.dts deleted file mode 100644 index 37f80ab8ccd..00000000000 --- a/sys/gnu/dts/arm/imx6dl-aristainetos_4.dts +++ /dev/null @@ -1,83 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * support fot the imx6 based aristainetos board - * - * Copyright (C) 2014 Heiko Schocher - */ -/dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-aristainetos.dtsi" - -/ { - model = "aristainetos i.MX6 Dual Lite Board 4"; - compatible = "fsl,imx6dl"; - - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <7>; - enable-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_backlight>; - status = "okay"; - }; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x40000000>; - }; - - display0: disp0 { - compatible = "fsl,imx-parallel-display"; - interface-pix-fmt = "rgb24"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu_disp>; - status = "okay"; - - display-timings { - 480x800p60 { - native-mode; - clock-frequency = <30000000>; - hactive = <480>; - vactive = <800>; - hfront-porch = <59>; - hback-porch = <10>; - hsync-len = <10>; - vback-porch = <15>; - vfront-porch = <15>; - vsync-len = <15>; - hsync-active = <1>; - vsync-active = <1>; - }; - }; - - port { - display0_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - }; -}; - -&ecspi2 { - cs-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi2>; - status = "okay"; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&ipu1_di0_disp0 { - remote-endpoint = <&display0_in>; -}; - -&pwm1 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx6dl-aristainetos_7.dts b/sys/gnu/dts/arm/imx6dl-aristainetos_7.dts deleted file mode 100644 index 8d8c8c27e48..00000000000 --- a/sys/gnu/dts/arm/imx6dl-aristainetos_7.dts +++ /dev/null @@ -1,73 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * support fot the imx6 based aristainetos board - * - * Copyright (C) 2014 Heiko Schocher - */ -/dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-aristainetos.dtsi" - -/ { - model = "aristainetos i.MX6 Dual Lite Board 7"; - compatible = "fsl,imx6dl"; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x40000000>; - }; - - display0: disp0 { - compatible = "fsl,imx-parallel-display"; - interface-pix-fmt = "rgb24"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu_disp>; - status = "okay"; - - display-timings { - 800x480p60 { - native-mode; - clock-frequency = <33246000>; - hactive = <800>; - vactive = <480>; - hfront-porch = <88>; - hback-porch = <88>; - hsync-len = <80>; - vback-porch = <10>; - vfront-porch = <10>; - vsync-len = <25>; - vsync-active = <1>; - }; - }; - - port { - display0_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm3 0 3000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_backlight>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&ipu1_di0_disp0 { - remote-endpoint = <&display0_in>; -}; - -&pwm3 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx6dl-colibri-eval-v3.dts b/sys/gnu/dts/arm/imx6dl-colibri-eval-v3.dts deleted file mode 100644 index 84fcc203a2e..00000000000 --- a/sys/gnu/dts/arm/imx6dl-colibri-eval-v3.dts +++ /dev/null @@ -1,297 +0,0 @@ -/* - * Copyright 2014-2016 Toradex AG - * Copyright 2012 Freescale Semiconductor, Inc. - * Copyright 2011 Linaro Ltd. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include -#include -#include "imx6dl.dtsi" -#include "imx6qdl-colibri.dtsi" - -/ { - model = "Toradex Colibri iMX6DL/S on Colibri Evaluation Board V3"; - compatible = "toradex,colibri_imx6dl-eval-v3", "toradex,colibri_imx6dl", - "fsl,imx6dl"; - - /* Will be filled by the bootloader */ - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0>; - }; - - aliases { - i2c0 = &i2c2; - i2c1 = &i2c3; - }; - - aliases { - rtc0 = &rtc_i2c; - rtc1 = &snvs_rtc; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - /* Fixed crystal dedicated to mcp251x */ - clk16m: clock-16m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <16000000>; - clock-output-names = "clk16m"; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_keys>; - - wakeup { - label = "Wake-Up"; - gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; /* SODIMM 45 */ - linux,code = ; - debounce-interval = <10>; - wakeup-source; - }; - }; - - lcd_display: disp0 { - compatible = "fsl,imx-parallel-display"; - #address-cells = <1>; - #size-cells = <0>; - interface-pix-fmt = "bgr666"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu1_lcdif>; - status = "okay"; - - port@0 { - reg = <0>; - - lcd_display_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - - port@1 { - reg = <1>; - - lcd_display_out: endpoint { - remote-endpoint = <&lcd_panel_in>; - }; - }; - }; - - panel: panel { - /* - * edt,et057090dhu: EDT 5.7" LCD TFT - * edt,et070080dh6: EDT 7.0" LCD TFT - */ - compatible = "edt,et057090dhu"; - backlight = <&backlight>; - - port { - lcd_panel_in: endpoint { - remote-endpoint = <&lcd_display_out>; - }; - }; - }; -}; - -&backlight { - brightness-levels = <0 127 191 223 239 247 251 255>; - default-brightness-level = <1>; - status = "okay"; -}; - -/* Colibri SSP */ -&ecspi4 { - status = "okay"; - - mcp251x0: mcp251x@0 { - compatible = "microchip,mcp2515"; - reg = <0>; - clocks = <&clk16m>; - interrupt-parent = <&gpio3>; - interrupts = <27 0x2>; - spi-max-frequency = <10000000>; - status = "okay"; - }; -}; - -&hdmi { - status = "okay"; -}; - -/* - * Colibri I2C: I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board) - */ -&i2c3 { - status = "okay"; - - /* - * Touchscreen is using SODIMM 28/30, also used for PWM, PWM, - * aka pwm2, pwm3. so if you enable touchscreen, disable the pwms - */ - touchscreen@4a { - compatible = "atmel,maxtouch"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcap_1>; - reg = <0x4a>; - interrupt-parent = <&gpio1>; - interrupts = <9 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 28 */ - reset-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; /* SODIMM 30 */ - status = "disabled"; - }; - - /* M41T0M6 real time clock on carrier board */ - rtc_i2c: rtc@68 { - compatible = "st,m41t0"; - reg = <0x68>; - }; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = < - &pinctrl_weim_gpio_1 &pinctrl_weim_gpio_2 - &pinctrl_weim_gpio_3 &pinctrl_weim_gpio_4 - &pinctrl_weim_gpio_5 &pinctrl_weim_gpio_6 - &pinctrl_usbh_oc_1 &pinctrl_usbc_id_1 - >; - - pinctrl_pcap_1: pcap1grp { - fsl,pins = < - MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 /* SODIMM 28 */ - MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0 /* SODIMM 30 */ - >; - }; - - pinctrl_mxt_ts: mxttsgrp { - fsl,pins = < - MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x130b0 /* SODIMM 107 */ - MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x130b0 /* SODIMM 106 */ - >; - }; -}; - -&ipu1_di0_disp0 { - remote-endpoint = <&lcd_display_in>; -}; - -&pwm1 { - status = "okay"; -}; - -&pwm2 { - status = "okay"; -}; - -&pwm3 { - status = "okay"; -}; - -&pwm4 { - status = "okay"; -}; - -®_usb_host_vbus { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usb_host_vbus>; - status = "okay"; -}; - -&usbotg { - status = "okay"; -}; - -/* Colibri MMC */ -&usdhc1 { - status = "okay"; -}; - -&weim { - status = "okay"; - - /* weim memory map: 32MB on CS0, CS1, CS2 and CS3 */ - ranges = <0 0 0x08000000 0x02000000 - 1 0 0x0a000000 0x02000000 - 2 0 0x0c000000 0x02000000 - 3 0 0x0e000000 0x02000000>; - - /* SRAM on Colibri nEXT_CS0 */ - sram@0,0 { - compatible = "cypress,cy7c1019dv33-10zsxi", "mtd-ram"; - reg = <0 0 0x00010000>; - #address-cells = <1>; - #size-cells = <1>; - bank-width = <2>; - fsl,weim-cs-timing = <0x00010081 0x00000000 0x04000000 - 0x00000000 0x04000040 0x00000000>; - }; - - /* SRAM on Colibri nEXT_CS1 */ - sram@1,0 { - compatible = "cypress,cy7c1019dv33-10zsxi", "mtd-ram"; - reg = <1 0 0x00010000>; - #address-cells = <1>; - #size-cells = <1>; - bank-width = <2>; - fsl,weim-cs-timing = <0x00010081 0x00000000 0x04000000 - 0x00000000 0x04000040 0x00000000>; - }; -}; diff --git a/sys/gnu/dts/arm/imx6dl-cubox-i-emmc-som-v15.dts b/sys/gnu/dts/arm/imx6dl-cubox-i-emmc-som-v15.dts deleted file mode 100644 index 2b2fc360b86..00000000000 --- a/sys/gnu/dts/arm/imx6dl-cubox-i-emmc-som-v15.dts +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright (C) 2014 Russell King - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -/dts-v1/; - -#include "imx6dl.dtsi" -#include "imx6qdl-sr-som.dtsi" -#include "imx6qdl-sr-som-ti.dtsi" -#include "imx6qdl-sr-som-emmc.dtsi" -#include "imx6qdl-cubox-i.dtsi" - -/ { - model = "SolidRun Cubox-i Solo/DualLite (1.5som+emmc)"; - compatible = "solidrun,cubox-i/dl", "fsl,imx6dl"; -}; diff --git a/sys/gnu/dts/arm/imx6dl-cubox-i-som-v15.dts b/sys/gnu/dts/arm/imx6dl-cubox-i-som-v15.dts deleted file mode 100644 index e09c565d1d1..00000000000 --- a/sys/gnu/dts/arm/imx6dl-cubox-i-som-v15.dts +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright (C) 2014 Russell King - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -/dts-v1/; - -#include "imx6dl.dtsi" -#include "imx6qdl-sr-som.dtsi" -#include "imx6qdl-sr-som-ti.dtsi" -#include "imx6qdl-cubox-i.dtsi" - -/ { - model = "SolidRun Cubox-i Solo/DualLite (1.5som)"; - compatible = "solidrun,cubox-i/dl", "fsl,imx6dl"; -}; diff --git a/sys/gnu/dts/arm/imx6dl-cubox-i.dts b/sys/gnu/dts/arm/imx6dl-cubox-i.dts deleted file mode 100644 index 2b1b3e193f5..00000000000 --- a/sys/gnu/dts/arm/imx6dl-cubox-i.dts +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright (C) 2014 Russell King - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -/dts-v1/; - -#include "imx6dl.dtsi" -#include "imx6qdl-sr-som.dtsi" -#include "imx6qdl-sr-som-brcm.dtsi" -#include "imx6qdl-cubox-i.dtsi" - -/ { - model = "SolidRun Cubox-i Solo/DualLite"; - compatible = "solidrun,cubox-i/dl", "fsl,imx6dl"; -}; diff --git a/sys/gnu/dts/arm/imx6dl-dfi-fs700-m60.dts b/sys/gnu/dts/arm/imx6dl-dfi-fs700-m60.dts deleted file mode 100644 index cece4aafdad..00000000000 --- a/sys/gnu/dts/arm/imx6dl-dfi-fs700-m60.dts +++ /dev/null @@ -1,23 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Sascha Hauer - */ - -#ifndef __DTS_V1__ -#define __DTS_V1__ -/dts-v1/; -#endif - -#include "imx6dl.dtsi" -#include "imx6qdl-dfi-fs700-m60.dtsi" - -/ { - model = "DFI FS700-M60-6DL i.MX6dl Q7 Board"; - compatible = "dfi,fs700-m60-6dl", "dfi,fs700e-m60", "fsl,imx6dl"; - - /* Will be filled by the bootloader */ - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0>; - }; -}; diff --git a/sys/gnu/dts/arm/imx6dl-eckelmann-ci4x10.dts b/sys/gnu/dts/arm/imx6dl-eckelmann-ci4x10.dts deleted file mode 100644 index 9eb2b73951b..00000000000 --- a/sys/gnu/dts/arm/imx6dl-eckelmann-ci4x10.dts +++ /dev/null @@ -1,381 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2016 Eckelmann AG. - * Copyright (C) 2013 Freescale Semiconductor, Inc. - */ - -/dts-v1/; - -#include - -#include "imx6dl.dtsi" - -/ { - model = "Eckelmann CI 4X10 Board"; - compatible = "eckelmann,imx6dl-ci4x10", "fsl,imx6dl"; - - chosen { - stdout-path = &uart3; - }; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x40000000>; - }; - - rmii_clk: clock-rmii { - /* This clock is provided by the phy (KSZ8091RNB) */ - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <50000000>; - }; - - reg_usb_h1_vbus: regulator-usb-h1-vbus { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usb_h1_vbus>; - compatible = "regulator-fixed"; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - siox { - compatible = "eckelmann,siox-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_siox>; - din-gpios = <&gpio6 11 GPIO_ACTIVE_HIGH>; - dout-gpios = <&gpio6 8 GPIO_ACTIVE_HIGH>; - dclk-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; - dld-gpios = <&gpio6 10 GPIO_ACTIVE_HIGH>; - }; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - status = "okay"; -}; - -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - status = "okay"; -}; - -&ecspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi2>; - cs-gpios = <&gpio5 12 GPIO_ACTIVE_HIGH>; - status = "okay"; - - flash@0 { - compatible = "everspin,mr25h256"; - reg = <0>; - spi-max-frequency = <15000000>; - }; -}; - -&ecspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - cs-gpios = <&gpio5 25 GPIO_ACTIVE_HIGH>; - status = "okay"; - - tpm@0 { - compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; - reg = <0>; - spi-max-frequency = <10000000>; - }; -}; - -&gpio2 { - gpio-line-names = "buzzer", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&gpio4 { - gpio-line-names = "", "", "", "", "", "", "", "in2", - "prio2", "prio1", "aux", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&gpio6 { - gpio-line-names = "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "in1", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - temperature-sensor@49 { - compatible = "ad,ad7414"; - reg = <0x49>; - }; - - rtc@51 { - compatible = "nxp,pcf2127"; - reg = <0x51>; - }; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_hog: hog { - fsl,pins = < - MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x00000018 /* buzzer */ - MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x00000018 /* OUT_1 */ - MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x00000018 /* OUT_2 */ - MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x00000018 /* OUT_3 */ - MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x00000000 /* In1 */ - MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x00000000 /* In2 */ - MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x00000018 /* unused watchdog pin */ - MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x00000018 /* unused watchdog pin */ - - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK 0x000100a0 - MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI 0x000100a0 - MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO 0x000100a0 - MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25 0x000100a0 - >; - }; - - pinctrl_ecspi2: ecspi2grp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK 0x000100b1 - MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x000100b1 - MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x000100b1 - MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x000100b1 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x0001b098 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x0001b098 - MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x0001b098 - MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x0001b098 - MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x0001b098 - MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x0001b0b0 - MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x0001b0b0 - MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x0001b0b0 - MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x0001b0b0 - MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0x00000018 - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x0001b020 - MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x0001b0b0 - >; - }; - - pinctrl_flexcan2: flexcan2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x0001b020 - MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x0001b0b0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - /* without SION i2c doesn't detect bus busy */ - MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b820 - MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b820 - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = < - MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x00000018 - >; - }; - - pinctrl_reg_usb_h1_vbus: reg_usb_h1_vbusgrp { - fsl,pins = < - MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x0001b0b0 - >; - }; - - pinctrl_siox: sioxgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x0001b010 /* DIN */ - MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x0001b010 /* DOUT */ - MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x0001b010 /* DCLK */ - MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x0001b010 /* DLD */ - >; - }; - - pinctrl_uart1_dte: uart1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x0001b010 - MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x0001b010 - MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x0001b010 - MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x0001b010 - MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x0001b010 /* DCD */ - MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x0001b010 /* DTR */ - MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x0001b010 /* DSR */ - >; - }; - - pinctrl_uart2_dte: uart2grp { - fsl,pins = < - MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x0001b010 - MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x0001b010 - MX6QDL_PAD_EIM_D28__UART2_RTS_B 0x0001b010 - MX6QDL_PAD_EIM_D29__UART2_CTS_B 0x0001b010 - MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x0001b010 /* DCD */ - MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x0001b010 /* DTR */ - MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x0001b010 /* DSR */ - >; - }; - - pinctrl_uart3_dce: uart3grp { - fsl,pins = < - MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x0001b010 - MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x0001b010 - >; - }; - - pinctrl_uart4_dce: uart4grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x0001b010 - MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x0001b010 - MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x0001b010 - >; - }; - - pinctrl_uart5_dce: uart5grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x0001b010 - MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x0001b010 - MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05 0x0001b010 /* RTS */ - >; - }; - - pinctrl_usbh1: usbh1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D30__USB_H1_OC 0x0001b0b0 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x00017059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x00010059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x00017059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x00017059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x00017059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x00017059 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x00017059 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x00017059 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x00017059 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x00017059 - >; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rmii"; - phy-reset-gpios = <&gpio1 18 GPIO_ACTIVE_LOW>; - phy-handle = <&phy>; - clocks = <&clks IMX6QDL_CLK_ENET>, <&clks IMX6QDL_CLK_ENET>, <&rmii_clk>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - phy: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; - }; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio1 20 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1_dte>; - uart-has-rtscts; - fsl,dte-mode; - dcd-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; - dtr-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>; - dsr-gpios = <&gpio3 25 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2_dte>; - uart-has-rtscts; - fsl,dte-mode; - dcd-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; - dtr-gpios = <&gpio7 13 GPIO_ACTIVE_LOW>; - dsr-gpios = <&gpio6 16 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3_dce>; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4_dce>; - rts-gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5_dce>; - rts-gpios = <&gpio6 5 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&usbh1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh1>; - vbus-supply = <®_usb_h1_vbus>; - status = "okay"; -}; - -&usbotg { - dr_mode = "peripheral"; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - bus-width = <8>; - non-removable; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx6dl-emcon-avari.dts b/sys/gnu/dts/arm/imx6dl-emcon-avari.dts deleted file mode 100644 index 407ad8d43c8..00000000000 --- a/sys/gnu/dts/arm/imx6dl-emcon-avari.dts +++ /dev/null @@ -1,14 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 or MIT) -// -// Copyright (C) 2018 emtrion GmbH -// - -/dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-emcon.dtsi" -#include "imx6qdl-emcon-avari.dtsi" - -/ { - model = "emtrion SoM emCON-MX6 Solo/Dual-Lite Avari"; - compatible = "emtrion,emcon-mx6-avari", "fsl,imx6dl"; -}; diff --git a/sys/gnu/dts/arm/imx6dl-gw51xx.dts b/sys/gnu/dts/arm/imx6dl-gw51xx.dts deleted file mode 100644 index 9956d12a124..00000000000 --- a/sys/gnu/dts/arm/imx6dl-gw51xx.dts +++ /dev/null @@ -1,13 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Gateworks Corporation - */ - -/dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-gw51xx.dtsi" - -/ { - model = "Gateworks Ventana i.MX6 DualLite/Solo GW51XX"; - compatible = "gw,imx6dl-gw51xx", "gw,ventana", "fsl,imx6dl"; -}; diff --git a/sys/gnu/dts/arm/imx6dl-gw52xx.dts b/sys/gnu/dts/arm/imx6dl-gw52xx.dts deleted file mode 100644 index 9ea23dd54f3..00000000000 --- a/sys/gnu/dts/arm/imx6dl-gw52xx.dts +++ /dev/null @@ -1,71 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Gateworks Corporation - */ - -/dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-gw52xx.dtsi" - -/ { - model = "Gateworks Ventana i.MX6 DualLite/Solo GW52XX"; - compatible = "gw,imx6dl-gw52xx", "gw,ventana", "fsl,imx6dl"; -}; - -&i2c3 { - adv7180: camera@20 { - compatible = "adi,adv7180"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_adv7180>; - reg = <0x20>; - powerdown-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; - interrupt-parent = <&gpio3>; - interrupts = <30 IRQ_TYPE_LEVEL_LOW>; - - port { - adv7180_to_ipu1_csi1_mux: endpoint { - remote-endpoint = <&ipu1_csi1_mux_from_parallel_sensor>; - bus-width = <8>; - }; - }; - }; -}; - -&ipu1_csi1_from_ipu1_csi1_mux { - bus-width = <8>; -}; - -&ipu1_csi1_mux_from_parallel_sensor { - remote-endpoint = <&adv7180_to_ipu1_csi1_mux>; - bus-width = <8>; -}; - -&ipu1_csi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu1_csi1>; -}; - -&iomuxc { - pinctrl_adv7180: adv7180grp { - fsl,pins = < - MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x0001b0b0 - MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x4001b0b0 - >; - }; - - pinctrl_ipu1_csi1: ipu1_csi1grp { - fsl,pins = < - MX6QDL_PAD_EIM_EB2__IPU1_CSI1_DATA19 0x1b0b0 - MX6QDL_PAD_EIM_D16__IPU1_CSI1_DATA18 0x1b0b0 - MX6QDL_PAD_EIM_D18__IPU1_CSI1_DATA17 0x1b0b0 - MX6QDL_PAD_EIM_D19__IPU1_CSI1_DATA16 0x1b0b0 - MX6QDL_PAD_EIM_D20__IPU1_CSI1_DATA15 0x1b0b0 - MX6QDL_PAD_EIM_D26__IPU1_CSI1_DATA14 0x1b0b0 - MX6QDL_PAD_EIM_D27__IPU1_CSI1_DATA13 0x1b0b0 - MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12 0x1b0b0 - MX6QDL_PAD_EIM_D29__IPU1_CSI1_VSYNC 0x1b0b0 - MX6QDL_PAD_EIM_EB3__IPU1_CSI1_HSYNC 0x1b0b0 - MX6QDL_PAD_EIM_A16__IPU1_CSI1_PIXCLK 0x1b0b0 - >; - }; -}; diff --git a/sys/gnu/dts/arm/imx6dl-gw53xx.dts b/sys/gnu/dts/arm/imx6dl-gw53xx.dts deleted file mode 100644 index 182e8194c24..00000000000 --- a/sys/gnu/dts/arm/imx6dl-gw53xx.dts +++ /dev/null @@ -1,71 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Gateworks Corporation - */ - -/dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-gw53xx.dtsi" - -/ { - model = "Gateworks Ventana i.MX6 DualLite/Solo GW53XX"; - compatible = "gw,imx6dl-gw53xx", "gw,ventana", "fsl,imx6dl"; -}; - -&i2c3 { - adv7180: camera@20 { - compatible = "adi,adv7180"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_adv7180>; - reg = <0x20>; - powerdown-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; - interrupt-parent = <&gpio3>; - interrupts = <30 IRQ_TYPE_LEVEL_LOW>; - - port { - adv7180_to_ipu1_csi1_mux: endpoint { - remote-endpoint = <&ipu1_csi1_mux_from_parallel_sensor>; - bus-width = <8>; - }; - }; - }; -}; - -&ipu1_csi1_from_ipu1_csi1_mux { - bus-width = <8>; -}; - -&ipu1_csi1_mux_from_parallel_sensor { - remote-endpoint = <&adv7180_to_ipu1_csi1_mux>; - bus-width = <8>; -}; - -&ipu1_csi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu1_csi1>; -}; - -&iomuxc { - pinctrl_adv7180: adv7180grp { - fsl,pins = < - MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x0001b0b0 - MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x4001b0b0 - >; - }; - - pinctrl_ipu1_csi1: ipu1_csi1grp { - fsl,pins = < - MX6QDL_PAD_EIM_EB2__IPU1_CSI1_DATA19 0x1b0b0 - MX6QDL_PAD_EIM_D16__IPU1_CSI1_DATA18 0x1b0b0 - MX6QDL_PAD_EIM_D18__IPU1_CSI1_DATA17 0x1b0b0 - MX6QDL_PAD_EIM_D19__IPU1_CSI1_DATA16 0x1b0b0 - MX6QDL_PAD_EIM_D20__IPU1_CSI1_DATA15 0x1b0b0 - MX6QDL_PAD_EIM_D26__IPU1_CSI1_DATA14 0x1b0b0 - MX6QDL_PAD_EIM_D27__IPU1_CSI1_DATA13 0x1b0b0 - MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12 0x1b0b0 - MX6QDL_PAD_EIM_D29__IPU1_CSI1_VSYNC 0x1b0b0 - MX6QDL_PAD_EIM_EB3__IPU1_CSI1_HSYNC 0x1b0b0 - MX6QDL_PAD_EIM_A16__IPU1_CSI1_PIXCLK 0x1b0b0 - >; - }; -}; diff --git a/sys/gnu/dts/arm/imx6dl-gw54xx.dts b/sys/gnu/dts/arm/imx6dl-gw54xx.dts deleted file mode 100644 index a106c4e3e32..00000000000 --- a/sys/gnu/dts/arm/imx6dl-gw54xx.dts +++ /dev/null @@ -1,71 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Gateworks Corporation - */ - -/dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-gw54xx.dtsi" - -/ { - model = "Gateworks Ventana i.MX6 DualLite/Solo GW54XX"; - compatible = "gw,imx6dl-gw54xx", "gw,ventana", "fsl,imx6dl"; -}; - -&i2c3 { - adv7180: camera@20 { - compatible = "adi,adv7180"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_adv7180>; - reg = <0x20>; - powerdown-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; - interrupt-parent = <&gpio3>; - interrupts = <30 IRQ_TYPE_LEVEL_LOW>; - - port { - adv7180_to_ipu1_csi1_mux: endpoint { - remote-endpoint = <&ipu1_csi1_mux_from_parallel_sensor>; - bus-width = <8>; - }; - }; - }; -}; - -&ipu1_csi1_from_ipu1_csi1_mux { - bus-width = <8>; -}; - -&ipu1_csi1_mux_from_parallel_sensor { - remote-endpoint = <&adv7180_to_ipu1_csi1_mux>; - bus-width = <8>; -}; - -&ipu1_csi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu1_csi1>; -}; - -&iomuxc { - pinctrl_adv7180: adv7180grp { - fsl,pins = < - MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x0001b0b0 - MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x4001b0b0 - >; - }; - - pinctrl_ipu1_csi1: ipu1_csi1grp { - fsl,pins = < - MX6QDL_PAD_EIM_EB2__IPU1_CSI1_DATA19 0x1b0b0 - MX6QDL_PAD_EIM_D16__IPU1_CSI1_DATA18 0x1b0b0 - MX6QDL_PAD_EIM_D18__IPU1_CSI1_DATA17 0x1b0b0 - MX6QDL_PAD_EIM_D19__IPU1_CSI1_DATA16 0x1b0b0 - MX6QDL_PAD_EIM_D20__IPU1_CSI1_DATA15 0x1b0b0 - MX6QDL_PAD_EIM_D26__IPU1_CSI1_DATA14 0x1b0b0 - MX6QDL_PAD_EIM_D27__IPU1_CSI1_DATA13 0x1b0b0 - MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12 0x1b0b0 - MX6QDL_PAD_EIM_D29__IPU1_CSI1_VSYNC 0x1b0b0 - MX6QDL_PAD_EIM_EB3__IPU1_CSI1_HSYNC 0x1b0b0 - MX6QDL_PAD_EIM_A16__IPU1_CSI1_PIXCLK 0x1b0b0 - >; - }; -}; diff --git a/sys/gnu/dts/arm/imx6dl-gw551x.dts b/sys/gnu/dts/arm/imx6dl-gw551x.dts deleted file mode 100644 index 82d5f85722e..00000000000 --- a/sys/gnu/dts/arm/imx6dl-gw551x.dts +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Copyright 2014 Gateworks Corporation - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-gw551x.dtsi" - -/ { - model = "Gateworks Ventana i.MX6 DualLite/Solo GW551X"; - compatible = "gw,imx6dl-gw551x", "gw,ventana", "fsl,imx6dl"; -}; diff --git a/sys/gnu/dts/arm/imx6dl-gw552x.dts b/sys/gnu/dts/arm/imx6dl-gw552x.dts deleted file mode 100644 index 4864a36f9b3..00000000000 --- a/sys/gnu/dts/arm/imx6dl-gw552x.dts +++ /dev/null @@ -1,14 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2014 Gateworks Corporation - */ - -/dts-v1/; - -#include "imx6dl.dtsi" -#include "imx6qdl-gw552x.dtsi" - -/ { - model = "Gateworks Ventana i.MX6 DualLite/Solo GW552X"; - compatible = "gw,imx6dl-gw552x", "gw,ventana", "fsl,imx6dl"; -}; diff --git a/sys/gnu/dts/arm/imx6dl-gw553x.dts b/sys/gnu/dts/arm/imx6dl-gw553x.dts deleted file mode 100644 index 59b8afc36e6..00000000000 --- a/sys/gnu/dts/arm/imx6dl-gw553x.dts +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Copyright 2016 Gateworks Corporation - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-gw553x.dtsi" - -/ { - model = "Gateworks Ventana i.MX6 DualLite/Solo GW553X"; - compatible = "gw,imx6dl-gw553x", "gw,ventana", "fsl,imx6dl"; -}; diff --git a/sys/gnu/dts/arm/imx6dl-gw560x.dts b/sys/gnu/dts/arm/imx6dl-gw560x.dts deleted file mode 100644 index 21bdfaf8df5..00000000000 --- a/sys/gnu/dts/arm/imx6dl-gw560x.dts +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Copyright 2017 Gateworks Corporation - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-gw560x.dtsi" - -/ { - model = "Gateworks Ventana i.MX6 DualLite/Solo GW560X"; - compatible = "gw,imx6dl-gw560x", "gw,ventana", "fsl,imx6dl"; -}; diff --git a/sys/gnu/dts/arm/imx6dl-gw5903.dts b/sys/gnu/dts/arm/imx6dl-gw5903.dts deleted file mode 100644 index 103261ea933..00000000000 --- a/sys/gnu/dts/arm/imx6dl-gw5903.dts +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Copyright 2017 Gateworks Corporation - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-gw5903.dtsi" - -/ { - model = "Gateworks Ventana i.MX6 Duallite/Solo GW5903"; - compatible = "gw,imx6dl-gw5903", "gw,ventana", "fsl,imx6dl"; -}; diff --git a/sys/gnu/dts/arm/imx6dl-gw5904.dts b/sys/gnu/dts/arm/imx6dl-gw5904.dts deleted file mode 100644 index 9c6d3cd3d6a..00000000000 --- a/sys/gnu/dts/arm/imx6dl-gw5904.dts +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Copyright 2017 Gateworks Corporation - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-gw5904.dtsi" - -/ { - model = "Gateworks Ventana i.MX6 DualLite/Solo GW5904"; - compatible = "gw,imx6dl-gw5904", "gw,ventana", "fsl,imx6dl"; -}; diff --git a/sys/gnu/dts/arm/imx6dl-gw5907.dts b/sys/gnu/dts/arm/imx6dl-gw5907.dts deleted file mode 100644 index 3fa2822beff..00000000000 --- a/sys/gnu/dts/arm/imx6dl-gw5907.dts +++ /dev/null @@ -1,14 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2019 Gateworks Corporation - */ - -/dts-v1/; - -#include "imx6dl.dtsi" -#include "imx6qdl-gw5907.dtsi" - -/ { - model = "Gateworks Ventana i.MX6 DualLite/Solo GW5907"; - compatible = "gw,imx6dl-gw5907", "gw,ventana", "fsl,imx6dl"; -}; diff --git a/sys/gnu/dts/arm/imx6dl-gw5910.dts b/sys/gnu/dts/arm/imx6dl-gw5910.dts deleted file mode 100644 index 0d5e7e5da53..00000000000 --- a/sys/gnu/dts/arm/imx6dl-gw5910.dts +++ /dev/null @@ -1,14 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2019 Gateworks Corporation - */ - -/dts-v1/; - -#include "imx6dl.dtsi" -#include "imx6qdl-gw5910.dtsi" - -/ { - model = "Gateworks Ventana i.MX6 DualLite/Solo GW5910"; - compatible = "gw,imx6dl-gw5910", "gw,ventana", "fsl,imx6dl"; -}; diff --git a/sys/gnu/dts/arm/imx6dl-gw5912.dts b/sys/gnu/dts/arm/imx6dl-gw5912.dts deleted file mode 100644 index 5260e0142d6..00000000000 --- a/sys/gnu/dts/arm/imx6dl-gw5912.dts +++ /dev/null @@ -1,13 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2019 Gateworks Corporation - */ - -/dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-gw5912.dtsi" - -/ { - model = "Gateworks Ventana i.MX6 DualLite/Solo GW5912"; - compatible = "gw,imx6dl-gw5912", "gw,ventana", "fsl,imx6dl"; -}; diff --git a/sys/gnu/dts/arm/imx6dl-gw5913.dts b/sys/gnu/dts/arm/imx6dl-gw5913.dts deleted file mode 100644 index b74e533c8e6..00000000000 --- a/sys/gnu/dts/arm/imx6dl-gw5913.dts +++ /dev/null @@ -1,14 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2019 Gateworks Corporation - */ - -/dts-v1/; - -#include "imx6dl.dtsi" -#include "imx6qdl-gw5913.dtsi" - -/ { - model = "Gateworks Ventana i.MX6 DualLite/Solo GW5913"; - compatible = "gw,imx6dl-gw5913", "gw,ventana", "fsl,imx6dl"; -}; diff --git a/sys/gnu/dts/arm/imx6dl-hummingboard-emmc-som-v15.dts b/sys/gnu/dts/arm/imx6dl-hummingboard-emmc-som-v15.dts deleted file mode 100644 index a63f742f20d..00000000000 --- a/sys/gnu/dts/arm/imx6dl-hummingboard-emmc-som-v15.dts +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright (C) 2014 Rabeeh Khoury (rabeeh@solid-run.com) - * Based on dt work by Russell King - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -/dts-v1/; - -#include "imx6dl.dtsi" -#include "imx6qdl-sr-som.dtsi" -#include "imx6qdl-sr-som-ti.dtsi" -#include "imx6qdl-sr-som-emmc.dtsi" -#include "imx6qdl-hummingboard.dtsi" - -/ { - model = "SolidRun HummingBoard Solo/DualLite (1.5som+emmc)"; - compatible = "solidrun,hummingboard/dl", "fsl,imx6dl"; -}; diff --git a/sys/gnu/dts/arm/imx6dl-hummingboard-som-v15.dts b/sys/gnu/dts/arm/imx6dl-hummingboard-som-v15.dts deleted file mode 100644 index 66a06cf3cdf..00000000000 --- a/sys/gnu/dts/arm/imx6dl-hummingboard-som-v15.dts +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright (C) 2014 Rabeeh Khoury (rabeeh@solid-run.com) - * Based on dt work by Russell King - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -/dts-v1/; - -#include "imx6dl.dtsi" -#include "imx6qdl-sr-som.dtsi" -#include "imx6qdl-sr-som-ti.dtsi" -#include "imx6qdl-hummingboard.dtsi" - -/ { - model = "SolidRun HummingBoard Solo/DualLite (1.5som)"; - compatible = "solidrun,hummingboard/dl", "fsl,imx6dl"; -}; diff --git a/sys/gnu/dts/arm/imx6dl-hummingboard.dts b/sys/gnu/dts/arm/imx6dl-hummingboard.dts deleted file mode 100644 index cbd02eb486e..00000000000 --- a/sys/gnu/dts/arm/imx6dl-hummingboard.dts +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright (C) 2014 Rabeeh Khoury (rabeeh@solid-run.com) - * Based on dt work by Russell King - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -/dts-v1/; - -#include "imx6dl.dtsi" -#include "imx6qdl-sr-som.dtsi" -#include "imx6qdl-sr-som-brcm.dtsi" -#include "imx6qdl-hummingboard.dtsi" - -/ { - model = "SolidRun HummingBoard Solo/DualLite"; - compatible = "solidrun,hummingboard/dl", "fsl,imx6dl"; -}; diff --git a/sys/gnu/dts/arm/imx6dl-hummingboard2-emmc-som-v15.dts b/sys/gnu/dts/arm/imx6dl-hummingboard2-emmc-som-v15.dts deleted file mode 100644 index 80313c13bcd..00000000000 --- a/sys/gnu/dts/arm/imx6dl-hummingboard2-emmc-som-v15.dts +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Device Tree file for SolidRun HummingBoard2 - * Copyright (C) 2015 Rabeeh Khoury - * Based on work by Russell King - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -/dts-v1/; - -#include "imx6dl.dtsi" -#include "imx6qdl-sr-som.dtsi" -#include "imx6qdl-sr-som-emmc.dtsi" -#include "imx6qdl-sr-som-ti.dtsi" -#include "imx6qdl-hummingboard2.dtsi" - -/ { - model = "SolidRun HummingBoard2 Solo/DualLite (1.5som+emmc)"; - compatible = "solidrun,hummingboard2/dl", "fsl,imx6dl"; -}; diff --git a/sys/gnu/dts/arm/imx6dl-hummingboard2-som-v15.dts b/sys/gnu/dts/arm/imx6dl-hummingboard2-som-v15.dts deleted file mode 100644 index e61ef1156f8..00000000000 --- a/sys/gnu/dts/arm/imx6dl-hummingboard2-som-v15.dts +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Device Tree file for SolidRun HummingBoard2 - * Copyright (C) 2015 Rabeeh Khoury - * Based on work by Russell King - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -/dts-v1/; - -#include "imx6dl.dtsi" -#include "imx6qdl-sr-som.dtsi" -#include "imx6qdl-sr-som-ti.dtsi" -#include "imx6qdl-hummingboard2.dtsi" - -/ { - model = "SolidRun HummingBoard2 Solo/DualLite (1.5som)"; - compatible = "solidrun,hummingboard2/dl", "fsl,imx6dl"; -}; diff --git a/sys/gnu/dts/arm/imx6dl-hummingboard2.dts b/sys/gnu/dts/arm/imx6dl-hummingboard2.dts deleted file mode 100644 index b12cd87f3f9..00000000000 --- a/sys/gnu/dts/arm/imx6dl-hummingboard2.dts +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright (C) 2015 Rabeeh Khoury - * Based on dt work by Russell King - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -/dts-v1/; - -#include "imx6dl.dtsi" -#include "imx6qdl-sr-som.dtsi" -#include "imx6qdl-sr-som-brcm.dtsi" -#include "imx6qdl-hummingboard2.dtsi" -#include "imx6qdl-hummingboard2-emmc.dtsi" - -/ { - model = "SolidRun HummingBoard2 Solo/DualLite"; - compatible = "solidrun,hummingboard2/dl", "fsl,imx6dl"; -}; diff --git a/sys/gnu/dts/arm/imx6dl-icore-mipi.dts b/sys/gnu/dts/arm/imx6dl-icore-mipi.dts deleted file mode 100644 index d8f3821a0ff..00000000000 --- a/sys/gnu/dts/arm/imx6dl-icore-mipi.dts +++ /dev/null @@ -1,25 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR X11 -/* - * Copyright (C) 2018 Engicam S.r.l. - * Copyright (C) 2018 Amarula Solutions B.V. - * Author: Jagan Teki - */ - -/dts-v1/; - -#include "imx6dl.dtsi" -#include "imx6qdl-icore-1.5.dtsi" - -/ { - model = "Engicam i.CoreM6 DualLite/Solo MIPI Starter Kit"; - compatible = "engicam,imx6-icore", "fsl,imx6dl"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c2>; - status = "okay"; -}; - -&usdhc3 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx6dl-icore-rqs.dts b/sys/gnu/dts/arm/imx6dl-icore-rqs.dts deleted file mode 100644 index 73d710d34b9..00000000000 --- a/sys/gnu/dts/arm/imx6dl-icore-rqs.dts +++ /dev/null @@ -1,15 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR X11 -/* - * Copyright (C) 2016 Amarula Solutions B.V. - * Copyright (C) 2016 Engicam S.r.l. - */ - -/dts-v1/; - -#include "imx6dl.dtsi" -#include "imx6qdl-icore-rqs.dtsi" - -/ { - model = "Engicam i.CoreM6 DualLite/Solo RQS Starter Kit"; - compatible = "engicam,imx6-icore-rqs", "fsl,imx6dl"; -}; diff --git a/sys/gnu/dts/arm/imx6dl-icore.dts b/sys/gnu/dts/arm/imx6dl-icore.dts deleted file mode 100644 index 80fa60607ab..00000000000 --- a/sys/gnu/dts/arm/imx6dl-icore.dts +++ /dev/null @@ -1,32 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR X11 -/* - * Copyright (C) 2016 Amarula Solutions B.V. - * Copyright (C) 2016 Engicam S.r.l. - */ - -/dts-v1/; - -#include "imx6dl.dtsi" -#include "imx6qdl-icore.dtsi" - -/ { - model = "Engicam i.CoreM6 DualLite/Solo Starter Kit"; - compatible = "engicam,imx6-icore", "fsl,imx6dl"; -}; - -&can1 { - status = "okay"; -}; - -&can2 { - status = "okay"; -}; - -&i2c1 { - max11801: touchscreen@48 { - compatible = "maxim,max11801"; - reg = <0x48>; - interrupt-parent = <&gpio3>; - interrupts = <31 IRQ_TYPE_EDGE_FALLING>; - }; -}; diff --git a/sys/gnu/dts/arm/imx6dl-kontron-samx6i.dtsi b/sys/gnu/dts/arm/imx6dl-kontron-samx6i.dtsi deleted file mode 100644 index a864fdbd5f1..00000000000 --- a/sys/gnu/dts/arm/imx6dl-kontron-samx6i.dtsi +++ /dev/null @@ -1,12 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR X11 -/* - * Copyright 2019 (C) Pengutronix, Marco Felsch - */ - -#include "imx6dl.dtsi" -#include "imx6qdl-kontron-samx6i.dtsi" - -/ { - model = "Kontron SMARC sAMX6i Dual-Lite/Solo"; - compatible = "kontron,imx6dl-samx6i", "fsl,imx6dl"; -}; diff --git a/sys/gnu/dts/arm/imx6dl-mamoj.dts b/sys/gnu/dts/arm/imx6dl-mamoj.dts deleted file mode 100644 index 385ce7b0029..00000000000 --- a/sys/gnu/dts/arm/imx6dl-mamoj.dts +++ /dev/null @@ -1,495 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2018 BTicino - * Copyright (C) 2018 Amarula Solutions B.V. - */ - -/dts-v1/; - -#include -#include "imx6dl.dtsi" - -/ { - model = "BTicino i.MX6DL Mamoj board"; - compatible = "bticino,imx6dl-mamoj", "fsl,imx6dl"; - - /* Will be filled by the bootloader */ - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0>; - }; - - backlight_lcd: backlight-lcd { - compatible = "pwm-backlight"; - pwms = <&pwm3 0 25000>; /* 25000ns -> 40kHz */ - brightness-levels = <0 4 8 16 32 64 128 160 192 224 255>; - default-brightness-level = <7>; - }; - - display: disp0 { - compatible = "fsl,imx-parallel-display"; - #address-cells = <1>; - #size-cells = <0>; - interface-pix-fmt = "rgb24"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu1_lcdif>; - status = "okay"; - - port@0 { - reg = <0>; - - lcd_display_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - - port@1 { - reg = <1>; - - lcd_display_out: endpoint { - remote-endpoint = <&lcd_panel_in>; - }; - }; - }; - - panel-lcd { - compatible = "rocktech,rk070er9427"; - backlight = <&backlight_lcd>; - power-supply = <®_lcd_lr>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu1_lcdif_pwr>; - - port { - lcd_panel_in: endpoint { - remote-endpoint = <&lcd_display_out>; - }; - }; - }; - - reg_lcd_3v3: regulator-lcd-dvdd { - compatible = "regulator-fixed"; - regulator-name = "lcd-dvdd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio3 1 0>; - enable-active-high; - startup-delay-us = <21000>; - }; - - reg_lcd_power: regulator-lcd-power { - compatible = "regulator-fixed"; - regulator-name = "lcd-enable"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio3 6 0>; - enable-active-high; - vin-supply = <®_lcd_3v3>; - }; - - reg_lcd_vgl: regulator-lcd-vgl { - compatible = "regulator-fixed"; - regulator-name = "lcd-vgl"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>; - startup-delay-us = <6000>; - enable-active-high; - vin-supply = <®_lcd_power>; - }; - - reg_lcd_vgh: regulator-lcd-vgh { - compatible = "regulator-fixed"; - regulator-name = "lcd-vgh"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; - startup-delay-us = <6000>; - enable-active-high; - vin-supply = <®_lcd_avdd>; - }; - - reg_lcd_vcom: regulator-lcd-vcom { - compatible = "regulator-fixed"; - regulator-name = "lcd-vcom"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio4 14 GPIO_ACTIVE_HIGH>; - startup-delay-us = <11000>; - enable-active-high; - vin-supply = <®_lcd_vgh>; - }; - - reg_lcd_lr: regulator-lcd-lr { - compatible = "regulator-fixed"; - regulator-name = "lcd-lr"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <®_lcd_vcom>; - }; - - reg_lcd_avdd: regulator-lcd-avdd { - compatible = "regulator-fixed"; - regulator-name = "lcd-avdd"; - regulator-min-microvolt = <10280000>; - regulator-max-microvolt = <10280000>; - gpio = <&gpio2 13 GPIO_ACTIVE_HIGH>; - startup-delay-us = <6000>; - enable-active-high; - vin-supply = <®_lcd_vgl>; - }; - - reg_usb_host: regulator-usb-vbus { - compatible = "regulator-fixed"; - regulator-name = "usbhost-vbus"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbhost>; - regulator-min-microvolt = <50000000>; - regulator-max-microvolt = <50000000>; - gpio = <&gpio6 6 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_wl18xx_vmmc: regulator-wl18xx-vmcc { - compatible = "regulator-fixed"; - regulator-name = "vwl1807"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wlan>; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio6 21 GPIO_ACTIVE_HIGH>; - startup-delay-us = <70000>; - enable-active-high; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "mii"; - status = "okay"; -}; - -&i2c3 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; -}; - -&i2c4 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4>; - status = "okay"; - - pfuze100: pmic@8 { - compatible = "fsl,pfuze100"; - reg = <0x08>; - - regulators { - /* CPU vdd_arm core */ - sw1a_reg: sw1ab { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - /* SOC vdd_soc */ - sw1c_reg: sw1c { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - /* I/O power GEN_3V3 */ - sw2_reg: sw2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - /* DDR memory */ - sw3a_reg: sw3a { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - /* DDR memory */ - sw3b_reg: sw3b { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - /* not used */ - sw4_reg: sw4 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - }; - - /* not used */ - swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - }; - - /* PMIC vsnvs. EX boot mode */ - snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - /* not used */ - vgen1_reg: vgen1 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - /* not used */ - vgen2_reg: vgen2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - /* not used */ - vgen3_reg: vgen3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - /* 1v8 general power */ - vgen4_reg: vgen4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - /* 2v8 general power IMX6 */ - vgen5_reg: vgen5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - /* 3v3 Ethernet */ - vgen6_reg: vgen6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; -}; - -&ipu1_di0_disp0 { - remote-endpoint = <&lcd_display_in>; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usb_host>; - status = "okay"; -}; - -&usbotg { - dr_mode = "peripheral"; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - bus-width = <4>; - vmmc-supply = <®_wl18xx_vmmc>; - no-1-8-v; - non-removable; - wakeup-source; - keep-power-in-suspend; - cap-power-off-card; - max-frequency = <25000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - wlcore: wlcore@2 { - compatible = "ti,wl1837"; - reg = <2>; - interrupt-parent = <&gpio6>; - interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; - tcxo-clock-frequency = <26000000>; - }; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - bus-width = <8>; - non-removable; - keep-power-in-suspend; - status = "okay"; -}; - -&iomuxc { - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b1 - MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 - MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 - MX6QDL_PAD_KEY_ROW2__ENET_TX_DATA2 0x1b0b0 - MX6QDL_PAD_KEY_ROW0__ENET_TX_DATA3 0x1b0b0 - MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 - MX6QDL_PAD_GPIO_19__ENET_TX_ER 0x1b0b0 - MX6QDL_PAD_GPIO_18__ENET_RX_CLK 0x1b0b1 - MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 - MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 - MX6QDL_PAD_KEY_COL2__ENET_RX_DATA2 0x1b0b0 - MX6QDL_PAD_KEY_COL0__ENET_RX_DATA3 0x1b0b0 - MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 - MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 - MX6QDL_PAD_KEY_COL3__ENET_CRS 0x1b0b0 - MX6QDL_PAD_KEY_ROW1__ENET_COL 0x1b0b0 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c4: i2c4grp { - fsl,pins = < - MX6QDL_PAD_GPIO_7__I2C4_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_8__I2C4_SDA 0x4001b8b1 - >; - }; - - pinctrl_ipu1_lcdif: pinctrlipu1lcdif { /* parallel port 24-bit */ - fsl,pins = < - MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 /* VDOUT_PCLK */ - MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 - MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 /* VDOUT_HSYNC */ - MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 /* VDOUT_VSYNC */ - MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x10 /* VDOUT_RESET */ - MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 - MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 - MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 - MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 - MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 - MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 - MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 - MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 - MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 - MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 - MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 - MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 - MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 - MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 - MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 - MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 - MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 - MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 - MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 - MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 - MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 - MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 - MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 - MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 - >; - }; - - pinctrl_ipu1_lcdif_pwr: ipu1lcdifpwrgrp { - fsl,pins = < - MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x40013058 /* EN_LCD33V */ - MX6QDL_PAD_SD4_DAT5__GPIO2_IO13 0x4001b0b0 /* EN_AVDD */ - MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x40013058 /* ENVGH */ - MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x40013058 /* ENVGL */ - MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x40013058 /* LCD_POWER */ - MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x40013058 /* EN_VCOM_LCD */ - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x40013058 /* LCD_L_R */ - MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x40013058 /* LCD_U_D */ - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbhost: usbhostgrp { - fsl,pins = < - MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x4001b0b0 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17069 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10079 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17069 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17069 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17069 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17069 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 - >; - }; - - pinctrl_wlan: wlangrp { - fsl,pins = < - MX6QDL_PAD_RGMII_TD1__GPIO6_IO21 0x4001b0b0 - >; - }; -}; diff --git a/sys/gnu/dts/arm/imx6dl-nit6xlite.dts b/sys/gnu/dts/arm/imx6dl-nit6xlite.dts deleted file mode 100644 index 61fa30991d6..00000000000 --- a/sys/gnu/dts/arm/imx6dl-nit6xlite.dts +++ /dev/null @@ -1,13 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR X11 -/* - * Copyright 2015 Boundary Devices, Inc. - */ -/dts-v1/; - -#include "imx6dl.dtsi" -#include "imx6qdl-nit6xlite.dtsi" - -/ { - model = "Boundary Devices i.MX6 Solo Nitrogen6_Lite Board"; - compatible = "boundary,imx6dl-nit6xlite", "fsl,imx6dl"; -}; diff --git a/sys/gnu/dts/arm/imx6dl-nitrogen6x.dts b/sys/gnu/dts/arm/imx6dl-nitrogen6x.dts deleted file mode 100644 index ef58d3b0ea0..00000000000 --- a/sys/gnu/dts/arm/imx6dl-nitrogen6x.dts +++ /dev/null @@ -1,15 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR X11 -/* - * Copyright 2013 Boundary Devices, Inc. - * Copyright 2012 Freescale Semiconductor, Inc. - * Copyright 2011 Linaro Ltd. - */ - -/dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-nitrogen6x.dtsi" - -/ { - model = "Boundary Devices i.MX6 DualLite Nitrogen6x Board"; - compatible = "boundary,imx6dl-nitrogen6x", "fsl,imx6dl"; -}; diff --git a/sys/gnu/dts/arm/imx6dl-phytec-mira-rdk-nand.dts b/sys/gnu/dts/arm/imx6dl-phytec-mira-rdk-nand.dts deleted file mode 100644 index 9f7f9f98139..00000000000 --- a/sys/gnu/dts/arm/imx6dl-phytec-mira-rdk-nand.dts +++ /dev/null @@ -1,64 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2018 PHYTEC Messtechnik GmbH - * Author: Christian Hemp - */ - -/dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-phytec-phycore-som.dtsi" -#include "imx6qdl-phytec-mira.dtsi" - -/ { - model = "PHYTEC phyBOARD-Mira DualLite/Solo Carrier-Board with NAND"; - compatible = "phytec,imx6dl-pbac06-nand", "phytec,imx6dl-pbac06", - "phytec,imx6qdl-pcm058", "fsl,imx6dl"; - - chosen { - stdout-path = &uart2; - }; -}; - -ðphy { - max-speed = <100>; -}; - -&fec { - status = "okay"; -}; - -&gpmi { - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c_rtc { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&usbh1 { - status = "okay"; -}; - -&usbotg { - status = "okay"; -}; - -&usdhc1 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx6dl-phytec-pbab01.dts b/sys/gnu/dts/arm/imx6dl-phytec-pbab01.dts deleted file mode 100644 index 0a07cc6f815..00000000000 --- a/sys/gnu/dts/arm/imx6dl-phytec-pbab01.dts +++ /dev/null @@ -1,13 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH - */ - -/dts-v1/; -#include "imx6dl-phytec-pfla02.dtsi" -#include "imx6qdl-phytec-pbab01.dtsi" - -/ { - model = "Phytec phyFLEX-i.MX6 DualLite/Solo Carrier-Board"; - compatible = "phytec,imx6dl-pbab01", "phytec,imx6dl-pfla02", "fsl,imx6dl"; -}; diff --git a/sys/gnu/dts/arm/imx6dl-phytec-pfla02.dtsi b/sys/gnu/dts/arm/imx6dl-phytec-pfla02.dtsi deleted file mode 100644 index 6f8aaf52442..00000000000 --- a/sys/gnu/dts/arm/imx6dl-phytec-pfla02.dtsi +++ /dev/null @@ -1,17 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH - */ - -#include "imx6dl.dtsi" -#include "imx6qdl-phytec-pfla02.dtsi" - -/ { - model = "Phytec phyFLEX-i.MX6 DualLite/Solo"; - compatible = "phytec,imx6dl-pfla02", "fsl,imx6dl"; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x20000000>; - }; -}; diff --git a/sys/gnu/dts/arm/imx6dl-pinfunc.h b/sys/gnu/dts/arm/imx6dl-pinfunc.h deleted file mode 100644 index 9d88d09f9bf..00000000000 --- a/sys/gnu/dts/arm/imx6dl-pinfunc.h +++ /dev/null @@ -1,1088 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - */ - -#ifndef __DTS_IMX6DL_PINFUNC_H -#define __DTS_IMX6DL_PINFUNC_H - -/* - * The pin function ID is a tuple of - * - */ -#define MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x04c 0x360 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT10__AUD3_RXC 0x04c 0x360 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x04c 0x360 0x7f8 0x2 0x0 -#define MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x04c 0x360 0x000 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x04c 0x360 0x8fc 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x04c 0x360 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x04c 0x360 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x050 0x364 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT11__AUD3_RXFS 0x050 0x364 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT11__ECSPI2_SS0 0x050 0x364 0x800 0x2 0x0 -#define MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x050 0x364 0x8fc 0x3 0x1 -#define MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x050 0x364 0x000 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x050 0x364 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT11__ARM_TRACE08 0x050 0x364 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x054 0x368 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT12__EIM_DATA08 0x054 0x368 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x054 0x368 0x000 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT12__UART4_RX_DATA 0x054 0x368 0x914 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x054 0x368 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT12__ARM_TRACE09 0x054 0x368 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x058 0x36c 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT13__EIM_DATA09 0x058 0x36c 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x058 0x36c 0x914 0x3 0x1 -#define MX6QDL_PAD_CSI0_DAT13__UART4_TX_DATA 0x058 0x36c 0x000 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x058 0x36c 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT13__ARM_TRACE10 0x058 0x36c 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x05c 0x370 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT14__EIM_DATA10 0x05c 0x370 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x05c 0x370 0x000 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT14__UART5_RX_DATA 0x05c 0x370 0x91c 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00 0x05c 0x370 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT14__ARM_TRACE11 0x05c 0x370 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x060 0x374 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT15__EIM_DATA11 0x060 0x374 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x060 0x374 0x91c 0x3 0x1 -#define MX6QDL_PAD_CSI0_DAT15__UART5_TX_DATA 0x060 0x374 0x000 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT15__GPIO6_IO01 0x060 0x374 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT15__ARM_TRACE12 0x060 0x374 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x064 0x378 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT16__EIM_DATA12 0x064 0x378 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x064 0x378 0x910 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT16__UART4_CTS_B 0x064 0x378 0x000 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT16__GPIO6_IO02 0x064 0x378 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT16__ARM_TRACE13 0x064 0x378 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x068 0x37c 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT17__EIM_DATA13 0x068 0x37c 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x068 0x37c 0x000 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT17__UART4_RTS_B 0x068 0x37c 0x910 0x3 0x1 -#define MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x068 0x37c 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT17__ARM_TRACE14 0x068 0x37c 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x06c 0x380 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT18__EIM_DATA14 0x06c 0x380 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT18__UART5_RTS_B 0x06c 0x380 0x918 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT18__UART5_CTS_B 0x06c 0x380 0x000 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04 0x06c 0x380 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT18__ARM_TRACE15 0x06c 0x380 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x070 0x384 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT19__EIM_DATA15 0x070 0x384 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT19__UART5_CTS_B 0x070 0x384 0x000 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT19__UART5_RTS_B 0x070 0x384 0x918 0x3 0x1 -#define MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05 0x070 0x384 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x074 0x388 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT4__EIM_DATA02 0x074 0x388 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK 0x074 0x388 0x7d8 0x2 0x0 -#define MX6QDL_PAD_CSI0_DAT4__KEY_COL5 0x074 0x388 0x8c0 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x074 0x388 0x000 0x4 0x0 -#define MX6QDL_PAD_CSI0_DAT4__GPIO5_IO22 0x074 0x388 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT4__ARM_TRACE01 0x074 0x388 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x078 0x38c 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT5__EIM_DATA03 0x078 0x38c 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI 0x078 0x38c 0x7e0 0x2 0x0 -#define MX6QDL_PAD_CSI0_DAT5__KEY_ROW5 0x078 0x38c 0x8cc 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x078 0x38c 0x000 0x4 0x0 -#define MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x078 0x38c 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT5__ARM_TRACE02 0x078 0x38c 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x07c 0x390 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT6__EIM_DATA04 0x07c 0x390 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO 0x07c 0x390 0x7dc 0x2 0x0 -#define MX6QDL_PAD_CSI0_DAT6__KEY_COL6 0x07c 0x390 0x8c4 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x07c 0x390 0x000 0x4 0x0 -#define MX6QDL_PAD_CSI0_DAT6__GPIO5_IO24 0x07c 0x390 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT6__ARM_TRACE03 0x07c 0x390 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x080 0x394 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT7__EIM_DATA05 0x080 0x394 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT7__ECSPI1_SS0 0x080 0x394 0x7e4 0x2 0x0 -#define MX6QDL_PAD_CSI0_DAT7__KEY_ROW6 0x080 0x394 0x8d0 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x080 0x394 0x000 0x4 0x0 -#define MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25 0x080 0x394 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT7__ARM_TRACE04 0x080 0x394 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x084 0x398 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT8__EIM_DATA06 0x084 0x398 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x084 0x398 0x7f4 0x2 0x0 -#define MX6QDL_PAD_CSI0_DAT8__KEY_COL7 0x084 0x398 0x8c8 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x084 0x398 0x86c 0x4 0x0 -#define MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x084 0x398 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT8__ARM_TRACE05 0x084 0x398 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x088 0x39c 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT9__EIM_DATA07 0x088 0x39c 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x088 0x39c 0x7fc 0x2 0x0 -#define MX6QDL_PAD_CSI0_DAT9__KEY_ROW7 0x088 0x39c 0x8d4 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x088 0x39c 0x868 0x4 0x0 -#define MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x088 0x39c 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT9__ARM_TRACE06 0x088 0x39c 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x08c 0x3a0 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DATA_EN__EIM_DATA00 0x08c 0x3a0 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x08c 0x3a0 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DATA_EN__ARM_TRACE_CLK 0x08c 0x3a0 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x090 0x3a4 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x090 0x3a4 0x000 0x3 0x0 -#define MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x090 0x3a4 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_MCLK__ARM_TRACE_CTL 0x090 0x3a4 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x094 0x3a8 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x094 0x3a8 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_PIXCLK__ARM_EVENTO 0x094 0x3a8 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x098 0x3ac 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_VSYNC__EIM_DATA01 0x098 0x3ac 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x098 0x3ac 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_VSYNC__ARM_TRACE00 0x098 0x3ac 0x000 0x7 0x0 -#define MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x09c 0x3b0 0x000 0x0 0x0 -#define MX6QDL_PAD_DI0_DISP_CLK__LCD_CLK 0x09c 0x3b0 0x000 0x1 0x0 -#define MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x09c 0x3b0 0x000 0x5 0x0 -#define MX6QDL_PAD_DI0_DISP_CLK__LCD_WR_RWN 0x09c 0x3b0 0x000 0x8 0x0 -#define MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x0a0 0x3b4 0x000 0x0 0x0 -#define MX6QDL_PAD_DI0_PIN15__LCD_ENABLE 0x0a0 0x3b4 0x000 0x1 0x0 -#define MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x0a0 0x3b4 0x000 0x2 0x0 -#define MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x0a0 0x3b4 0x000 0x5 0x0 -#define MX6QDL_PAD_DI0_PIN15__LCD_RD_E 0x0a0 0x3b4 0x000 0x8 0x0 -#define MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x0a4 0x3b8 0x000 0x0 0x0 -#define MX6QDL_PAD_DI0_PIN2__LCD_HSYNC 0x0a4 0x3b8 0x8d8 0x1 0x0 -#define MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x0a4 0x3b8 0x000 0x2 0x0 -#define MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x0a4 0x3b8 0x000 0x5 0x0 -#define MX6QDL_PAD_DI0_PIN2__LCD_RS 0x0a4 0x3b8 0x000 0x8 0x0 -#define MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x0a8 0x3bc 0x000 0x0 0x0 -#define MX6QDL_PAD_DI0_PIN3__LCD_VSYNC 0x0a8 0x3bc 0x000 0x1 0x0 -#define MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x0a8 0x3bc 0x000 0x2 0x0 -#define MX6QDL_PAD_DI0_PIN3__GPIO4_IO19 0x0a8 0x3bc 0x000 0x5 0x0 -#define MX6QDL_PAD_DI0_PIN3__LCD_CS 0x0a8 0x3bc 0x000 0x8 0x0 -#define MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x0ac 0x3c0 0x000 0x0 0x0 -#define MX6QDL_PAD_DI0_PIN4__LCD_BUSY 0x0ac 0x3c0 0x8d8 0x1 0x1 -#define MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x0ac 0x3c0 0x000 0x2 0x0 -#define MX6QDL_PAD_DI0_PIN4__SD1_WP 0x0ac 0x3c0 0x92c 0x3 0x0 -#define MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x0ac 0x3c0 0x000 0x5 0x0 -#define MX6QDL_PAD_DI0_PIN4__LCD_RESET 0x0ac 0x3c0 0x000 0x8 0x0 -#define MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x0b0 0x3c4 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT0__LCD_DATA00 0x0b0 0x3c4 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x0b0 0x3c4 0x000 0x2 0x0 -#define MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21 0x0b0 0x3c4 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x0b4 0x3c8 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT1__LCD_DATA01 0x0b4 0x3c8 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x0b4 0x3c8 0x000 0x2 0x0 -#define MX6QDL_PAD_DISP0_DAT1__GPIO4_IO22 0x0b4 0x3c8 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x0b8 0x3cc 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT10__LCD_DATA10 0x0b8 0x3cc 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31 0x0b8 0x3cc 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x0bc 0x3d0 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT11__LCD_DATA11 0x0bc 0x3d0 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x0bc 0x3d0 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x0c0 0x3d4 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT12__LCD_DATA12 0x0c0 0x3d4 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06 0x0c0 0x3d4 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x0c4 0x3d8 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT13__LCD_DATA13 0x0c4 0x3d8 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT13__AUD5_RXFS 0x0c4 0x3d8 0x7bc 0x3 0x0 -#define MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07 0x0c4 0x3d8 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x0c8 0x3dc 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT14__LCD_DATA14 0x0c8 0x3dc 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT14__AUD5_RXC 0x0c8 0x3dc 0x7b8 0x3 0x0 -#define MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x0c8 0x3dc 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x0cc 0x3e0 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT15__LCD_DATA15 0x0cc 0x3e0 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT15__ECSPI1_SS1 0x0cc 0x3e0 0x7e8 0x2 0x0 -#define MX6QDL_PAD_DISP0_DAT15__ECSPI2_SS1 0x0cc 0x3e0 0x804 0x3 0x0 -#define MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x0cc 0x3e0 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x0d0 0x3e4 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT16__LCD_DATA16 0x0d0 0x3e4 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI 0x0d0 0x3e4 0x7fc 0x2 0x1 -#define MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x0d0 0x3e4 0x7c0 0x3 0x0 -#define MX6QDL_PAD_DISP0_DAT16__SDMA_EXT_EVENT0 0x0d0 0x3e4 0x8e8 0x4 0x0 -#define MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 0x0d0 0x3e4 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x0d4 0x3e8 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT17__LCD_DATA17 0x0d4 0x3e8 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT17__ECSPI2_MISO 0x0d4 0x3e8 0x7f8 0x2 0x1 -#define MX6QDL_PAD_DISP0_DAT17__AUD5_TXD 0x0d4 0x3e8 0x7b4 0x3 0x0 -#define MX6QDL_PAD_DISP0_DAT17__SDMA_EXT_EVENT1 0x0d4 0x3e8 0x8ec 0x4 0x0 -#define MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x0d4 0x3e8 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x0d8 0x3ec 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT18__LCD_DATA18 0x0d8 0x3ec 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT18__ECSPI2_SS0 0x0d8 0x3ec 0x800 0x2 0x1 -#define MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x0d8 0x3ec 0x7c4 0x3 0x0 -#define MX6QDL_PAD_DISP0_DAT18__AUD4_RXFS 0x0d8 0x3ec 0x7a4 0x4 0x0 -#define MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x0d8 0x3ec 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT18__EIM_CS2_B 0x0d8 0x3ec 0x000 0x7 0x0 -#define MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x0dc 0x3f0 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT19__LCD_DATA19 0x0dc 0x3f0 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK 0x0dc 0x3f0 0x7f4 0x2 0x1 -#define MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x0dc 0x3f0 0x7b0 0x3 0x0 -#define MX6QDL_PAD_DISP0_DAT19__AUD4_RXC 0x0dc 0x3f0 0x7a0 0x4 0x0 -#define MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x0dc 0x3f0 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT19__EIM_CS3_B 0x0dc 0x3f0 0x000 0x7 0x0 -#define MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x0e0 0x3f4 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT2__LCD_DATA02 0x0e0 0x3f4 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x0e0 0x3f4 0x000 0x2 0x0 -#define MX6QDL_PAD_DISP0_DAT2__GPIO4_IO23 0x0e0 0x3f4 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x0e4 0x3f8 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT20__LCD_DATA20 0x0e4 0x3f8 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT20__ECSPI1_SCLK 0x0e4 0x3f8 0x7d8 0x2 0x1 -#define MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x0e4 0x3f8 0x7a8 0x3 0x0 -#define MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x0e4 0x3f8 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x0e8 0x3fc 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT21__LCD_DATA21 0x0e8 0x3fc 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT21__ECSPI1_MOSI 0x0e8 0x3fc 0x7e0 0x2 0x1 -#define MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x0e8 0x3fc 0x79c 0x3 0x0 -#define MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x0e8 0x3fc 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x0ec 0x400 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT22__LCD_DATA22 0x0ec 0x400 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT22__ECSPI1_MISO 0x0ec 0x400 0x7dc 0x2 0x1 -#define MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x0ec 0x400 0x7ac 0x3 0x0 -#define MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x0ec 0x400 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x0f0 0x404 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT23__LCD_DATA23 0x0f0 0x404 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT23__ECSPI1_SS0 0x0f0 0x404 0x7e4 0x2 0x1 -#define MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x0f0 0x404 0x798 0x3 0x0 -#define MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x0f0 0x404 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x0f4 0x408 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT3__LCD_DATA03 0x0f4 0x408 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT3__ECSPI3_SS0 0x0f4 0x408 0x000 0x2 0x0 -#define MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x0f4 0x408 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x0f8 0x40c 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT4__LCD_DATA04 0x0f8 0x40c 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT4__ECSPI3_SS1 0x0f8 0x40c 0x000 0x2 0x0 -#define MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x0f8 0x40c 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x0fc 0x410 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT5__LCD_DATA05 0x0fc 0x410 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT5__ECSPI3_SS2 0x0fc 0x410 0x000 0x2 0x0 -#define MX6QDL_PAD_DISP0_DAT5__AUD6_RXFS 0x0fc 0x410 0x000 0x3 0x0 -#define MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x0fc 0x410 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x100 0x414 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT6__LCD_DATA06 0x100 0x414 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT6__ECSPI3_SS3 0x100 0x414 0x000 0x2 0x0 -#define MX6QDL_PAD_DISP0_DAT6__AUD6_RXC 0x100 0x414 0x000 0x3 0x0 -#define MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x100 0x414 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x104 0x418 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT7__LCD_DATA07 0x104 0x418 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT7__ECSPI3_RDY 0x104 0x418 0x000 0x2 0x0 -#define MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x104 0x418 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x108 0x41c 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT8__LCD_DATA08 0x108 0x41c 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x108 0x41c 0x000 0x2 0x0 -#define MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x108 0x41c 0x000 0x3 0x0 -#define MX6QDL_PAD_DISP0_DAT8__GPIO4_IO29 0x108 0x41c 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10c 0x420 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT9__LCD_DATA09 0x10c 0x420 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 0x10c 0x420 0x000 0x2 0x0 -#define MX6QDL_PAD_DISP0_DAT9__WDOG2_B 0x10c 0x420 0x000 0x3 0x0 -#define MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x10c 0x420 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_A16__EIM_ADDR16 0x110 0x4e0 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_A16__IPU1_DI1_DISP_CLK 0x110 0x4e0 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_A16__IPU1_CSI1_PIXCLK 0x110 0x4e0 0x8b8 0x2 0x0 -#define MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x110 0x4e0 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_A16__SRC_BOOT_CFG16 0x110 0x4e0 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_A16__EPDC_DATA00 0x110 0x4e0 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_A17__EIM_ADDR17 0x114 0x4e4 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_A17__IPU1_DISP1_DATA12 0x114 0x4e4 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12 0x114 0x4e4 0x890 0x2 0x0 -#define MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x114 0x4e4 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_A17__SRC_BOOT_CFG17 0x114 0x4e4 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_A17__EPDC_PWR_STAT 0x114 0x4e4 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_A18__EIM_ADDR18 0x118 0x4e8 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_A18__IPU1_DISP1_DATA13 0x118 0x4e8 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_A18__IPU1_CSI1_DATA13 0x118 0x4e8 0x894 0x2 0x0 -#define MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x118 0x4e8 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_A18__SRC_BOOT_CFG18 0x118 0x4e8 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_A18__EPDC_PWR_CTRL0 0x118 0x4e8 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_A19__EIM_ADDR19 0x11c 0x4ec 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_A19__IPU1_DISP1_DATA14 0x11c 0x4ec 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_A19__IPU1_CSI1_DATA14 0x11c 0x4ec 0x898 0x2 0x0 -#define MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x11c 0x4ec 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_A19__SRC_BOOT_CFG19 0x11c 0x4ec 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_A19__EPDC_PWR_CTRL1 0x11c 0x4ec 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_A20__EIM_ADDR20 0x120 0x4f0 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_A20__IPU1_DISP1_DATA15 0x120 0x4f0 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_A20__IPU1_CSI1_DATA15 0x120 0x4f0 0x89c 0x2 0x0 -#define MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x120 0x4f0 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_A20__SRC_BOOT_CFG20 0x120 0x4f0 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_A20__EPDC_PWR_CTRL2 0x120 0x4f0 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_A21__EIM_ADDR21 0x124 0x4f4 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_A21__IPU1_DISP1_DATA16 0x124 0x4f4 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_A21__IPU1_CSI1_DATA16 0x124 0x4f4 0x8a0 0x2 0x0 -#define MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x124 0x4f4 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_A21__SRC_BOOT_CFG21 0x124 0x4f4 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_A21__EPDC_GDCLK 0x124 0x4f4 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_A22__EIM_ADDR22 0x128 0x4f8 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_A22__IPU1_DISP1_DATA17 0x128 0x4f8 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_A22__IPU1_CSI1_DATA17 0x128 0x4f8 0x8a4 0x2 0x0 -#define MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x128 0x4f8 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_A22__SRC_BOOT_CFG22 0x128 0x4f8 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_A22__EPDC_GDSP 0x128 0x4f8 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_A23__EIM_ADDR23 0x12c 0x4fc 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_A23__IPU1_DISP1_DATA18 0x12c 0x4fc 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_A23__IPU1_CSI1_DATA18 0x12c 0x4fc 0x8a8 0x2 0x0 -#define MX6QDL_PAD_EIM_A23__IPU1_SISG3 0x12c 0x4fc 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x12c 0x4fc 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_A23__SRC_BOOT_CFG23 0x12c 0x4fc 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_A23__EPDC_GDOE 0x12c 0x4fc 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_A24__EIM_ADDR24 0x130 0x500 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_A24__IPU1_DISP1_DATA19 0x130 0x500 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_A24__IPU1_CSI1_DATA19 0x130 0x500 0x8ac 0x2 0x0 -#define MX6QDL_PAD_EIM_A24__IPU1_SISG2 0x130 0x500 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x130 0x500 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_A24__SRC_BOOT_CFG24 0x130 0x500 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_A24__EPDC_GDRL 0x130 0x500 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_A25__EIM_ADDR25 0x134 0x504 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_A25__ECSPI4_SS1 0x134 0x504 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_A25__ECSPI2_RDY 0x134 0x504 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_A25__IPU1_DI1_PIN12 0x134 0x504 0x000 0x3 0x0 -#define MX6QDL_PAD_EIM_A25__IPU1_DI0_D1_CS 0x134 0x504 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x134 0x504 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x134 0x504 0x85c 0x6 0x0 -#define MX6QDL_PAD_EIM_A25__EPDC_DATA15 0x134 0x504 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_A25__EIM_ACLK_FREERUN 0x134 0x504 0x000 0x9 0x0 -#define MX6QDL_PAD_EIM_BCLK__EIM_BCLK 0x138 0x508 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_BCLK__IPU1_DI1_PIN16 0x138 0x508 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x138 0x508 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_BCLK__EPDC_SDCE9 0x138 0x508 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0x13c 0x50c 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_CS0__IPU1_DI1_PIN05 0x13c 0x50c 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x13c 0x50c 0x7f4 0x2 0x2 -#define MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x13c 0x50c 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_CS0__EPDC_DATA06 0x13c 0x50c 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_CS1__EIM_CS1_B 0x140 0x510 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_CS1__IPU1_DI1_PIN06 0x140 0x510 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x140 0x510 0x7fc 0x2 0x2 -#define MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x140 0x510 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_CS1__EPDC_DATA08 0x140 0x510 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_D16__EIM_DATA16 0x144 0x514 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x144 0x514 0x7d8 0x1 0x2 -#define MX6QDL_PAD_EIM_D16__IPU1_DI0_PIN05 0x144 0x514 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D16__IPU1_CSI1_DATA18 0x144 0x514 0x8a8 0x3 0x1 -#define MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x144 0x514 0x864 0x4 0x0 -#define MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x144 0x514 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D16__I2C2_SDA 0x144 0x514 0x874 0x6 0x0 -#define MX6QDL_PAD_EIM_D16__EPDC_DATA10 0x144 0x514 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_D17__EIM_DATA17 0x148 0x518 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x148 0x518 0x7dc 0x1 0x2 -#define MX6QDL_PAD_EIM_D17__IPU1_DI0_PIN06 0x148 0x518 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D17__IPU1_CSI1_PIXCLK 0x148 0x518 0x8b8 0x3 0x1 -#define MX6QDL_PAD_EIM_D17__DCIC1_OUT 0x148 0x518 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D17__GPIO3_IO17 0x148 0x518 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D17__I2C3_SCL 0x148 0x518 0x878 0x6 0x0 -#define MX6QDL_PAD_EIM_D17__EPDC_VCOM0 0x148 0x518 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_D18__EIM_DATA18 0x14c 0x51c 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x14c 0x51c 0x7e0 0x1 0x2 -#define MX6QDL_PAD_EIM_D18__IPU1_DI0_PIN07 0x14c 0x51c 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D18__IPU1_CSI1_DATA17 0x14c 0x51c 0x8a4 0x3 0x1 -#define MX6QDL_PAD_EIM_D18__IPU1_DI1_D0_CS 0x14c 0x51c 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x14c 0x51c 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D18__I2C3_SDA 0x14c 0x51c 0x87c 0x6 0x0 -#define MX6QDL_PAD_EIM_D18__EPDC_VCOM1 0x14c 0x51c 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_D19__EIM_DATA19 0x150 0x520 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D19__ECSPI1_SS1 0x150 0x520 0x7e8 0x1 0x1 -#define MX6QDL_PAD_EIM_D19__IPU1_DI0_PIN08 0x150 0x520 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D19__IPU1_CSI1_DATA16 0x150 0x520 0x8a0 0x3 0x1 -#define MX6QDL_PAD_EIM_D19__UART1_CTS_B 0x150 0x520 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x150 0x520 0x8f8 0x4 0x0 -#define MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x150 0x520 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D19__EPIT1_OUT 0x150 0x520 0x000 0x6 0x0 -#define MX6QDL_PAD_EIM_D19__EPDC_DATA12 0x150 0x520 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_D20__EIM_DATA20 0x154 0x524 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D20__ECSPI4_SS0 0x154 0x524 0x808 0x1 0x0 -#define MX6QDL_PAD_EIM_D20__IPU1_DI0_PIN16 0x154 0x524 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D20__IPU1_CSI1_DATA15 0x154 0x524 0x89c 0x3 0x1 -#define MX6QDL_PAD_EIM_D20__UART1_RTS_B 0x154 0x524 0x8f8 0x4 0x1 -#define MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x154 0x524 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x154 0x524 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D20__EPIT2_OUT 0x154 0x524 0x000 0x6 0x0 -#define MX6QDL_PAD_EIM_D21__EIM_DATA21 0x158 0x528 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x158 0x528 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_D21__IPU1_DI0_PIN17 0x158 0x528 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D21__IPU1_CSI1_DATA11 0x158 0x528 0x88c 0x3 0x0 -#define MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x158 0x528 0x920 0x4 0x0 -#define MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x158 0x528 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D21__I2C1_SCL 0x158 0x528 0x868 0x6 0x1 -#define MX6QDL_PAD_EIM_D21__SPDIF_IN 0x158 0x528 0x8f0 0x7 0x0 -#define MX6QDL_PAD_EIM_D22__EIM_DATA22 0x15c 0x52c 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x15c 0x52c 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_D22__IPU1_DI0_PIN01 0x15c 0x52c 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D22__IPU1_CSI1_DATA10 0x15c 0x52c 0x888 0x3 0x0 -#define MX6QDL_PAD_EIM_D22__USB_OTG_PWR 0x15c 0x52c 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x15c 0x52c 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D22__SPDIF_OUT 0x15c 0x52c 0x000 0x6 0x0 -#define MX6QDL_PAD_EIM_D22__EPDC_SDCE6 0x15c 0x52c 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_D23__EIM_DATA23 0x160 0x530 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D23__IPU1_DI0_D0_CS 0x160 0x530 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x160 0x530 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D23__UART3_RTS_B 0x160 0x530 0x908 0x2 0x0 -#define MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x160 0x530 0x000 0x3 0x0 -#define MX6QDL_PAD_EIM_D23__IPU1_CSI1_DATA_EN 0x160 0x530 0x8b0 0x4 0x0 -#define MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x160 0x530 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D23__IPU1_DI1_PIN02 0x160 0x530 0x000 0x6 0x0 -#define MX6QDL_PAD_EIM_D23__IPU1_DI1_PIN14 0x160 0x530 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_D23__EPDC_DATA11 0x160 0x530 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_D24__EIM_DATA24 0x164 0x534 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D24__ECSPI4_SS2 0x164 0x534 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x164 0x534 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D24__UART3_RX_DATA 0x164 0x534 0x90c 0x2 0x0 -#define MX6QDL_PAD_EIM_D24__ECSPI1_SS2 0x164 0x534 0x7ec 0x3 0x0 -#define MX6QDL_PAD_EIM_D24__ECSPI2_SS2 0x164 0x534 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x164 0x534 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D24__AUD5_RXFS 0x164 0x534 0x7bc 0x6 0x1 -#define MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x164 0x534 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_D24__EPDC_SDCE7 0x164 0x534 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_D25__EIM_DATA25 0x168 0x538 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D25__ECSPI4_SS3 0x168 0x538 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x168 0x538 0x90c 0x2 0x1 -#define MX6QDL_PAD_EIM_D25__UART3_TX_DATA 0x168 0x538 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D25__ECSPI1_SS3 0x168 0x538 0x7f0 0x3 0x0 -#define MX6QDL_PAD_EIM_D25__ECSPI2_SS3 0x168 0x538 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x168 0x538 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D25__AUD5_RXC 0x168 0x538 0x7b8 0x6 0x1 -#define MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x168 0x538 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_D25__EPDC_SDCE8 0x168 0x538 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_D26__EIM_DATA26 0x16c 0x53c 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D26__IPU1_DI1_PIN11 0x16c 0x53c 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_D26__IPU1_CSI0_DATA01 0x16c 0x53c 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D26__IPU1_CSI1_DATA14 0x16c 0x53c 0x898 0x3 0x1 -#define MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x16c 0x53c 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x16c 0x53c 0x904 0x4 0x0 -#define MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x16c 0x53c 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D26__IPU1_SISG2 0x16c 0x53c 0x000 0x6 0x0 -#define MX6QDL_PAD_EIM_D26__IPU1_DISP1_DATA22 0x16c 0x53c 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_D26__EPDC_SDOED 0x16c 0x53c 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_D27__EIM_DATA27 0x170 0x540 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D27__IPU1_DI1_PIN13 0x170 0x540 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_D27__IPU1_CSI0_DATA00 0x170 0x540 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D27__IPU1_CSI1_DATA13 0x170 0x540 0x894 0x3 0x1 -#define MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x170 0x540 0x904 0x4 0x1 -#define MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x170 0x540 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x170 0x540 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D27__IPU1_SISG3 0x170 0x540 0x000 0x6 0x0 -#define MX6QDL_PAD_EIM_D27__IPU1_DISP1_DATA23 0x170 0x540 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_D27__EPDC_SDOE 0x170 0x540 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_D28__EIM_DATA28 0x174 0x544 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D28__I2C1_SDA 0x174 0x544 0x86c 0x1 0x1 -#define MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x174 0x544 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D28__IPU1_CSI1_DATA12 0x174 0x544 0x890 0x3 0x1 -#define MX6QDL_PAD_EIM_D28__UART2_CTS_B 0x174 0x544 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D28__UART2_RTS_B 0x174 0x544 0x900 0x4 0x0 -#define MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x174 0x544 0x900 0x4 0x0 -#define MX6QDL_PAD_EIM_D28__UART2_DTE_RTS_B 0x174 0x544 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x174 0x544 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D28__IPU1_EXT_TRIG 0x174 0x544 0x000 0x6 0x0 -#define MX6QDL_PAD_EIM_D28__IPU1_DI0_PIN13 0x174 0x544 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_D28__EPDC_PWR_CTRL3 0x174 0x544 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_D29__EIM_DATA29 0x178 0x548 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D29__IPU1_DI1_PIN15 0x178 0x548 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_D29__ECSPI4_SS0 0x178 0x548 0x808 0x2 0x1 -#define MX6QDL_PAD_EIM_D29__UART2_RTS_B 0x178 0x548 0x900 0x4 0x1 -#define MX6QDL_PAD_EIM_D29__UART2_CTS_B 0x178 0x548 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x178 0x548 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D29__UART2_DTE_CTS_B 0x178 0x548 0x900 0x4 0x1 -#define MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x178 0x548 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D29__IPU1_CSI1_VSYNC 0x178 0x548 0x8bc 0x6 0x0 -#define MX6QDL_PAD_EIM_D29__IPU1_DI0_PIN14 0x178 0x548 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_D29__EPDC_PWR_WAKE 0x178 0x548 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_D30__EIM_DATA30 0x17c 0x54c 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D30__IPU1_DISP1_DATA21 0x17c 0x54c 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_D30__IPU1_DI0_PIN11 0x17c 0x54c 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D30__IPU1_CSI0_DATA03 0x17c 0x54c 0x000 0x3 0x0 -#define MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x17c 0x54c 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D30__UART3_RTS_B 0x17c 0x54c 0x908 0x4 0x1 -#define MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x17c 0x54c 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D30__USB_H1_OC 0x17c 0x54c 0x924 0x6 0x0 -#define MX6QDL_PAD_EIM_D30__EPDC_SDOEZ 0x17c 0x54c 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_D31__EIM_DATA31 0x180 0x550 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D31__IPU1_DISP1_DATA20 0x180 0x550 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_D31__IPU1_DI0_PIN12 0x180 0x550 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D31__IPU1_CSI0_DATA02 0x180 0x550 0x000 0x3 0x0 -#define MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x180 0x550 0x908 0x4 0x2 -#define MX6QDL_PAD_EIM_D31__UART3_CTS_B 0x180 0x550 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x180 0x550 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D31__USB_H1_PWR 0x180 0x550 0x000 0x6 0x0 -#define MX6QDL_PAD_EIM_D31__EPDC_SDCLK_P 0x180 0x550 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_D31__EIM_ACLK_FREERUN 0x180 0x550 0x000 0x9 0x0 -#define MX6QDL_PAD_EIM_DA0__EIM_AD00 0x184 0x554 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA0__IPU1_DISP1_DATA09 0x184 0x554 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA0__IPU1_CSI1_DATA09 0x184 0x554 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x184 0x554 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA0__SRC_BOOT_CFG00 0x184 0x554 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA0__EPDC_SDCLK_N 0x184 0x554 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_DA1__EIM_AD01 0x188 0x558 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA1__IPU1_DISP1_DATA08 0x188 0x558 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA1__IPU1_CSI1_DATA08 0x188 0x558 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x188 0x558 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA1__SRC_BOOT_CFG01 0x188 0x558 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA1__EPDC_SDLE 0x188 0x558 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_DA10__EIM_AD10 0x18c 0x55c 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA10__IPU1_DI1_PIN15 0x18c 0x55c 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA10__IPU1_CSI1_DATA_EN 0x18c 0x55c 0x8b0 0x2 0x1 -#define MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x18c 0x55c 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA10__SRC_BOOT_CFG10 0x18c 0x55c 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA10__EPDC_DATA01 0x18c 0x55c 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_DA11__EIM_AD11 0x190 0x560 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA11__IPU1_DI1_PIN02 0x190 0x560 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA11__IPU1_CSI1_HSYNC 0x190 0x560 0x8b4 0x2 0x0 -#define MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0x190 0x560 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA11__SRC_BOOT_CFG11 0x190 0x560 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA11__EPDC_DATA03 0x190 0x560 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_DA12__EIM_AD12 0x194 0x564 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA12__IPU1_DI1_PIN03 0x194 0x564 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA12__IPU1_CSI1_VSYNC 0x194 0x564 0x8bc 0x2 0x1 -#define MX6QDL_PAD_EIM_DA12__GPIO3_IO12 0x194 0x564 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA12__SRC_BOOT_CFG12 0x194 0x564 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA12__EPDC_DATA02 0x194 0x564 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_DA13__EIM_AD13 0x198 0x568 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA13__IPU1_DI1_D0_CS 0x198 0x568 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x198 0x568 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA13__SRC_BOOT_CFG13 0x198 0x568 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA13__EPDC_DATA13 0x198 0x568 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_DA14__EIM_AD14 0x19c 0x56c 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA14__IPU1_DI1_D1_CS 0x19c 0x56c 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x19c 0x56c 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA14__SRC_BOOT_CFG14 0x19c 0x56c 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA14__EPDC_DATA14 0x19c 0x56c 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_DA15__EIM_AD15 0x1a0 0x570 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA15__IPU1_DI1_PIN01 0x1a0 0x570 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA15__IPU1_DI1_PIN04 0x1a0 0x570 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x1a0 0x570 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA15__SRC_BOOT_CFG15 0x1a0 0x570 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA15__EPDC_DATA09 0x1a0 0x570 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_DA2__EIM_AD02 0x1a4 0x574 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA2__IPU1_DISP1_DATA07 0x1a4 0x574 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA2__IPU1_CSI1_DATA07 0x1a4 0x574 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x1a4 0x574 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA2__SRC_BOOT_CFG02 0x1a4 0x574 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA2__EPDC_BDR0 0x1a4 0x574 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_DA3__EIM_AD03 0x1a8 0x578 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA3__IPU1_DISP1_DATA06 0x1a8 0x578 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA3__IPU1_CSI1_DATA06 0x1a8 0x578 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x1a8 0x578 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA3__SRC_BOOT_CFG03 0x1a8 0x578 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA3__EPDC_BDR1 0x1a8 0x578 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_DA4__EIM_AD04 0x1ac 0x57c 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA4__IPU1_DISP1_DATA05 0x1ac 0x57c 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA4__IPU1_CSI1_DATA05 0x1ac 0x57c 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x1ac 0x57c 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA4__SRC_BOOT_CFG04 0x1ac 0x57c 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA4__EPDC_SDCE0 0x1ac 0x57c 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_DA5__EIM_AD05 0x1b0 0x580 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA5__IPU1_DISP1_DATA04 0x1b0 0x580 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA5__IPU1_CSI1_DATA04 0x1b0 0x580 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x1b0 0x580 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA5__SRC_BOOT_CFG05 0x1b0 0x580 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA5__EPDC_SDCE1 0x1b0 0x580 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_DA6__EIM_AD06 0x1b4 0x584 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA6__IPU1_DISP1_DATA03 0x1b4 0x584 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA6__IPU1_CSI1_DATA03 0x1b4 0x584 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x1b4 0x584 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA6__SRC_BOOT_CFG06 0x1b4 0x584 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA6__EPDC_SDCE2 0x1b4 0x584 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_DA7__EIM_AD07 0x1b8 0x588 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA7__IPU1_DISP1_DATA02 0x1b8 0x588 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA7__IPU1_CSI1_DATA02 0x1b8 0x588 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x1b8 0x588 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA7__SRC_BOOT_CFG07 0x1b8 0x588 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA7__EPDC_SDCE3 0x1b8 0x588 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_DA8__EIM_AD08 0x1bc 0x58c 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA8__IPU1_DISP1_DATA01 0x1bc 0x58c 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA8__IPU1_CSI1_DATA01 0x1bc 0x58c 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x1bc 0x58c 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA8__SRC_BOOT_CFG08 0x1bc 0x58c 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA8__EPDC_SDCE4 0x1bc 0x58c 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_DA9__EIM_AD09 0x1c0 0x590 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA9__IPU1_DISP1_DATA00 0x1c0 0x590 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA9__IPU1_CSI1_DATA00 0x1c0 0x590 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x1c0 0x590 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA9__SRC_BOOT_CFG09 0x1c0 0x590 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA9__EPDC_SDCE5 0x1c0 0x590 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_EB0__EIM_EB0_B 0x1c4 0x594 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_EB0__IPU1_DISP1_DATA11 0x1c4 0x594 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_EB0__IPU1_CSI1_DATA11 0x1c4 0x594 0x88c 0x2 0x1 -#define MX6QDL_PAD_EIM_EB0__CCM_PMIC_READY 0x1c4 0x594 0x7d4 0x4 0x0 -#define MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x1c4 0x594 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_EB0__SRC_BOOT_CFG27 0x1c4 0x594 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_EB0__EPDC_PWR_COM 0x1c4 0x594 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_EB1__EIM_EB1_B 0x1c8 0x598 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_EB1__IPU1_DISP1_DATA10 0x1c8 0x598 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_EB1__IPU1_CSI1_DATA10 0x1c8 0x598 0x888 0x2 0x1 -#define MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x1c8 0x598 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_EB1__SRC_BOOT_CFG28 0x1c8 0x598 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_EB1__EPDC_SDSHR 0x1c8 0x598 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_EB2__EIM_EB2_B 0x1cc 0x59c 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_EB2__ECSPI1_SS0 0x1cc 0x59c 0x7e4 0x1 0x2 -#define MX6QDL_PAD_EIM_EB2__IPU1_CSI1_DATA19 0x1cc 0x59c 0x8ac 0x3 0x1 -#define MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x1cc 0x59c 0x860 0x4 0x0 -#define MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1cc 0x59c 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x1cc 0x59c 0x870 0x6 0x0 -#define MX6QDL_PAD_EIM_EB2__SRC_BOOT_CFG30 0x1cc 0x59c 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_EB2__EPDC_DATA05 0x1cc 0x59c 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_EB3__EIM_EB3_B 0x1d0 0x5a0 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_EB3__ECSPI4_RDY 0x1d0 0x5a0 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1d0 0x5a0 0x908 0x2 0x3 -#define MX6QDL_PAD_EIM_EB3__UART3_CTS_B 0x1d0 0x5a0 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_EB3__UART1_RI_B 0x1d0 0x5a0 0x000 0x3 0x0 -#define MX6QDL_PAD_EIM_EB3__IPU1_CSI1_HSYNC 0x1d0 0x5a0 0x8b4 0x4 0x1 -#define MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x1d0 0x5a0 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_EB3__IPU1_DI1_PIN03 0x1d0 0x5a0 0x000 0x6 0x0 -#define MX6QDL_PAD_EIM_EB3__SRC_BOOT_CFG31 0x1d0 0x5a0 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_EB3__EPDC_SDCE0 0x1d0 0x5a0 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_EB3__EIM_ACLK_FREERUN 0x1d0 0x5a0 0x000 0x9 0x0 -#define MX6QDL_PAD_EIM_LBA__EIM_LBA_B 0x1d4 0x5a4 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_LBA__IPU1_DI1_PIN17 0x1d4 0x5a4 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_LBA__ECSPI2_SS1 0x1d4 0x5a4 0x804 0x2 0x1 -#define MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1d4 0x5a4 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_LBA__SRC_BOOT_CFG26 0x1d4 0x5a4 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_LBA__EPDC_DATA04 0x1d4 0x5a4 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_OE__EIM_OE_B 0x1d8 0x5a8 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_OE__IPU1_DI1_PIN07 0x1d8 0x5a8 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x1d8 0x5a8 0x7f8 0x2 0x2 -#define MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x1d8 0x5a8 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_OE__EPDC_PWR_IRQ 0x1d8 0x5a8 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_RW__EIM_RW 0x1dc 0x5ac 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_RW__IPU1_DI1_PIN08 0x1dc 0x5ac 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_RW__ECSPI2_SS0 0x1dc 0x5ac 0x800 0x2 0x2 -#define MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x1dc 0x5ac 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_RW__SRC_BOOT_CFG29 0x1dc 0x5ac 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_RW__EPDC_DATA07 0x1dc 0x5ac 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0x1e0 0x5b0 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_WAIT__EIM_DTACK_B 0x1e0 0x5b0 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1e0 0x5b0 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_WAIT__SRC_BOOT_CFG25 0x1e0 0x5b0 0x000 0x7 0x0 -#define MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1e4 0x5b4 0x828 0x1 0x0 -#define MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1e4 0x5b4 0x840 0x2 0x0 -#define MX6QDL_PAD_ENET_CRS_DV__SPDIF_EXT_CLK 0x1e4 0x5b4 0x8f4 0x3 0x0 -#define MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1e4 0x5b4 0x000 0x5 0x0 -#define MX6QDL_PAD_ENET_MDC__MLB_DATA 0x1e8 0x5b8 0x8e0 0x0 0x0 -#define MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1e8 0x5b8 0x000 0x1 0x0 -#define MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1e8 0x5b8 0x858 0x2 0x0 -#define MX6QDL_PAD_ENET_MDC__ENET_1588_EVENT1_IN 0x1e8 0x5b8 0x000 0x4 0x0 -#define MX6QDL_PAD_ENET_MDC__GPIO1_IO31 0x1e8 0x5b8 0x000 0x5 0x0 -#define MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1ec 0x5bc 0x810 0x1 0x0 -#define MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1ec 0x5bc 0x83c 0x2 0x0 -#define MX6QDL_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT 0x1ec 0x5bc 0x000 0x4 0x0 -#define MX6QDL_PAD_ENET_MDIO__GPIO1_IO22 0x1ec 0x5bc 0x000 0x5 0x0 -#define MX6QDL_PAD_ENET_MDIO__SPDIF_LOCK 0x1ec 0x5bc 0x000 0x6 0x0 -#define MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1f0 0x5c0 0x000 0x1 0x0 -#define MX6QDL_PAD_ENET_REF_CLK__ESAI_RX_FS 0x1f0 0x5c0 0x82c 0x2 0x0 -#define MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1f0 0x5c0 0x000 0x5 0x0 -#define MX6QDL_PAD_ENET_REF_CLK__SPDIF_SR_CLK 0x1f0 0x5c0 0x000 0x6 0x0 -#define MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x1f4 0x5c4 0x790 0x0 0x0 -#define MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1f4 0x5c4 0x000 0x1 0x0 -#define MX6QDL_PAD_ENET_RX_ER__ESAI_RX_HF_CLK 0x1f4 0x5c4 0x834 0x2 0x0 -#define MX6QDL_PAD_ENET_RX_ER__SPDIF_IN 0x1f4 0x5c4 0x8f0 0x3 0x1 -#define MX6QDL_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT 0x1f4 0x5c4 0x000 0x4 0x0 -#define MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x1f4 0x5c4 0x000 0x5 0x0 -#define MX6QDL_PAD_ENET_RXD0__OSC32K_32K_OUT 0x1f8 0x5c8 0x000 0x0 0x0 -#define MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1f8 0x5c8 0x818 0x1 0x0 -#define MX6QDL_PAD_ENET_RXD0__ESAI_TX_HF_CLK 0x1f8 0x5c8 0x838 0x2 0x0 -#define MX6QDL_PAD_ENET_RXD0__SPDIF_OUT 0x1f8 0x5c8 0x000 0x3 0x0 -#define MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1f8 0x5c8 0x000 0x5 0x0 -#define MX6QDL_PAD_ENET_RXD1__MLB_SIG 0x1fc 0x5cc 0x8e4 0x0 0x0 -#define MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1fc 0x5cc 0x81c 0x1 0x0 -#define MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1fc 0x5cc 0x830 0x2 0x0 -#define MX6QDL_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT 0x1fc 0x5cc 0x000 0x4 0x0 -#define MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1fc 0x5cc 0x000 0x5 0x0 -#define MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x200 0x5d0 0x000 0x1 0x0 -#define MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x200 0x5d0 0x850 0x2 0x0 -#define MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x200 0x5d0 0x000 0x5 0x0 -#define MX6QDL_PAD_ENET_TX_EN__I2C4_SCL 0x200 0x5d0 0x880 0x9 0x0 -#define MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x204 0x5d4 0x000 0x1 0x0 -#define MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x204 0x5d4 0x854 0x2 0x0 -#define MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x204 0x5d4 0x000 0x5 0x0 -#define MX6QDL_PAD_ENET_TXD1__MLB_CLK 0x208 0x5d8 0x8dc 0x0 0x0 -#define MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x208 0x5d8 0x000 0x1 0x0 -#define MX6QDL_PAD_ENET_TXD1__ESAI_TX2_RX3 0x208 0x5d8 0x84c 0x2 0x0 -#define MX6QDL_PAD_ENET_TXD1__ENET_1588_EVENT0_IN 0x208 0x5d8 0x000 0x4 0x0 -#define MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x208 0x5d8 0x000 0x5 0x0 -#define MX6QDL_PAD_ENET_TXD1__I2C4_SDA 0x208 0x5d8 0x884 0x9 0x0 -#define MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x20c 0x5dc 0x000 0x0 0x0 -#define MX6QDL_PAD_GPIO_0__KEY_COL5 0x20c 0x5dc 0x8c0 0x2 0x1 -#define MX6QDL_PAD_GPIO_0__ASRC_EXT_CLK 0x20c 0x5dc 0x794 0x3 0x0 -#define MX6QDL_PAD_GPIO_0__EPIT1_OUT 0x20c 0x5dc 0x000 0x4 0x0 -#define MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x20c 0x5dc 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_0__USB_H1_PWR 0x20c 0x5dc 0x000 0x6 0x0 -#define MX6QDL_PAD_GPIO_0__SNVS_VIO_5 0x20c 0x5dc 0x000 0x7 0x0 -#define MX6QDL_PAD_GPIO_1__ESAI_RX_CLK 0x210 0x5e0 0x83c 0x0 0x1 -#define MX6QDL_PAD_GPIO_1__WDOG2_B 0x210 0x5e0 0x000 0x1 0x0 -#define MX6QDL_PAD_GPIO_1__KEY_ROW5 0x210 0x5e0 0x8cc 0x2 0x1 -#define MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x210 0x5e0 0x790 0x3 0x1 -#define MX6QDL_PAD_GPIO_1__PWM2_OUT 0x210 0x5e0 0x000 0x4 0x0 -#define MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x210 0x5e0 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_1__SD1_CD_B 0x210 0x5e0 0x000 0x6 0x0 -#define MX6QDL_PAD_GPIO_16__ESAI_TX3_RX2 0x214 0x5e4 0x850 0x0 0x1 -#define MX6QDL_PAD_GPIO_16__ENET_1588_EVENT2_IN 0x214 0x5e4 0x000 0x1 0x0 -#define MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x214 0x5e4 0x80c 0x2 0x0 -#define MX6QDL_PAD_GPIO_16__SD1_LCTL 0x214 0x5e4 0x000 0x3 0x0 -#define MX6QDL_PAD_GPIO_16__SPDIF_IN 0x214 0x5e4 0x8f0 0x4 0x2 -#define MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x214 0x5e4 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_16__I2C3_SDA 0x214 0x5e4 0x87c 0x6 0x1 -#define MX6QDL_PAD_GPIO_16__JTAG_DE_B 0x214 0x5e4 0x000 0x7 0x0 -#define MX6QDL_PAD_GPIO_17__ESAI_TX0 0x218 0x5e8 0x844 0x0 0x0 -#define MX6QDL_PAD_GPIO_17__ENET_1588_EVENT3_IN 0x218 0x5e8 0x000 0x1 0x0 -#define MX6QDL_PAD_GPIO_17__CCM_PMIC_READY 0x218 0x5e8 0x7d4 0x2 0x1 -#define MX6QDL_PAD_GPIO_17__SDMA_EXT_EVENT0 0x218 0x5e8 0x8e8 0x3 0x1 -#define MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x218 0x5e8 0x000 0x4 0x0 -#define MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x218 0x5e8 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_18__ESAI_TX1 0x21c 0x5ec 0x848 0x0 0x0 -#define MX6QDL_PAD_GPIO_18__ENET_RX_CLK 0x21c 0x5ec 0x814 0x1 0x0 -#define MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x21c 0x5ec 0x000 0x2 0x0 -#define MX6QDL_PAD_GPIO_18__SDMA_EXT_EVENT1 0x21c 0x5ec 0x8ec 0x3 0x1 -#define MX6QDL_PAD_GPIO_18__ASRC_EXT_CLK 0x21c 0x5ec 0x794 0x4 0x1 -#define MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x21c 0x5ec 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_18__SNVS_VIO_5_CTL 0x21c 0x5ec 0x000 0x6 0x0 -#define MX6QDL_PAD_GPIO_19__KEY_COL5 0x220 0x5f0 0x8c0 0x0 0x2 -#define MX6QDL_PAD_GPIO_19__ENET_1588_EVENT0_OUT 0x220 0x5f0 0x000 0x1 0x0 -#define MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x220 0x5f0 0x000 0x2 0x0 -#define MX6QDL_PAD_GPIO_19__CCM_CLKO1 0x220 0x5f0 0x000 0x3 0x0 -#define MX6QDL_PAD_GPIO_19__ECSPI1_RDY 0x220 0x5f0 0x000 0x4 0x0 -#define MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x220 0x5f0 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_19__ENET_TX_ER 0x220 0x5f0 0x000 0x6 0x0 -#define MX6QDL_PAD_GPIO_2__ESAI_TX_FS 0x224 0x5f4 0x830 0x0 0x1 -#define MX6QDL_PAD_GPIO_2__KEY_ROW6 0x224 0x5f4 0x8d0 0x2 0x1 -#define MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x224 0x5f4 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_2__SD2_WP 0x224 0x5f4 0x000 0x6 0x0 -#define MX6QDL_PAD_GPIO_2__MLB_DATA 0x224 0x5f4 0x8e0 0x7 0x1 -#define MX6QDL_PAD_GPIO_3__ESAI_RX_HF_CLK 0x228 0x5f8 0x834 0x0 0x1 -#define MX6QDL_PAD_GPIO_3__I2C3_SCL 0x228 0x5f8 0x878 0x2 0x1 -#define MX6QDL_PAD_GPIO_3__XTALOSC_REF_CLK_24M 0x228 0x5f8 0x000 0x3 0x0 -#define MX6QDL_PAD_GPIO_3__CCM_CLKO2 0x228 0x5f8 0x000 0x4 0x0 -#define MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x228 0x5f8 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_3__USB_H1_OC 0x228 0x5f8 0x924 0x6 0x1 -#define MX6QDL_PAD_GPIO_3__MLB_CLK 0x228 0x5f8 0x8dc 0x7 0x1 -#define MX6QDL_PAD_GPIO_4__ESAI_TX_HF_CLK 0x22c 0x5fc 0x838 0x0 0x1 -#define MX6QDL_PAD_GPIO_4__KEY_COL7 0x22c 0x5fc 0x8c8 0x2 0x1 -#define MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x22c 0x5fc 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_4__SD2_CD_B 0x22c 0x5fc 0x000 0x6 0x0 -#define MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3 0x230 0x600 0x84c 0x0 0x1 -#define MX6QDL_PAD_GPIO_5__KEY_ROW7 0x230 0x600 0x8d4 0x2 0x1 -#define MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x230 0x600 0x000 0x3 0x0 -#define MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x230 0x600 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_5__I2C3_SCL 0x230 0x600 0x878 0x6 0x2 -#define MX6QDL_PAD_GPIO_5__ARM_EVENTI 0x230 0x600 0x000 0x7 0x0 -#define MX6QDL_PAD_GPIO_6__ESAI_TX_CLK 0x234 0x604 0x840 0x0 0x1 -#define MX6QDL_PAD_GPIO_6__ENET_IRQ 0x234 0x604 0x03c 0x11 0xff000609 -#define MX6QDL_PAD_GPIO_6__I2C3_SDA 0x234 0x604 0x87c 0x2 0x2 -#define MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x234 0x604 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_6__SD2_LCTL 0x234 0x604 0x000 0x6 0x0 -#define MX6QDL_PAD_GPIO_6__MLB_SIG 0x234 0x604 0x8e4 0x7 0x1 -#define MX6QDL_PAD_GPIO_7__ESAI_TX4_RX1 0x238 0x608 0x854 0x0 0x1 -#define MX6QDL_PAD_GPIO_7__EPIT1_OUT 0x238 0x608 0x000 0x2 0x0 -#define MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x238 0x608 0x000 0x3 0x0 -#define MX6QDL_PAD_GPIO_7__UART2_TX_DATA 0x238 0x608 0x000 0x4 0x0 -#define MX6QDL_PAD_GPIO_7__UART2_RX_DATA 0x238 0x608 0x904 0x4 0x2 -#define MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x238 0x608 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_7__SPDIF_LOCK 0x238 0x608 0x000 0x6 0x0 -#define MX6QDL_PAD_GPIO_7__USB_OTG_HOST_MODE 0x238 0x608 0x000 0x7 0x0 -#define MX6QDL_PAD_GPIO_7__I2C4_SCL 0x238 0x608 0x880 0x8 0x1 -#define MX6QDL_PAD_GPIO_8__ESAI_TX5_RX0 0x23c 0x60c 0x858 0x0 0x1 -#define MX6QDL_PAD_GPIO_8__XTALOSC_REF_CLK_32K 0x23c 0x60c 0x000 0x1 0x0 -#define MX6QDL_PAD_GPIO_8__EPIT2_OUT 0x23c 0x60c 0x000 0x2 0x0 -#define MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x23c 0x60c 0x7c8 0x3 0x0 -#define MX6QDL_PAD_GPIO_8__UART2_RX_DATA 0x23c 0x60c 0x904 0x4 0x3 -#define MX6QDL_PAD_GPIO_8__UART2_TX_DATA 0x23c 0x60c 0x000 0x4 0x0 -#define MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x23c 0x60c 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_8__SPDIF_SR_CLK 0x23c 0x60c 0x000 0x6 0x0 -#define MX6QDL_PAD_GPIO_8__USB_OTG_PWR_CTL_WAKE 0x23c 0x60c 0x000 0x7 0x0 -#define MX6QDL_PAD_GPIO_8__I2C4_SDA 0x23c 0x60c 0x884 0x8 0x1 -#define MX6QDL_PAD_GPIO_9__ESAI_RX_FS 0x240 0x610 0x82c 0x0 0x1 -#define MX6QDL_PAD_GPIO_9__WDOG1_B 0x240 0x610 0x000 0x1 0x0 -#define MX6QDL_PAD_GPIO_9__KEY_COL6 0x240 0x610 0x8c4 0x2 0x1 -#define MX6QDL_PAD_GPIO_9__CCM_REF_EN_B 0x240 0x610 0x000 0x3 0x0 -#define MX6QDL_PAD_GPIO_9__PWM1_OUT 0x240 0x610 0x000 0x4 0x0 -#define MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x240 0x610 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_9__SD1_WP 0x240 0x610 0x92c 0x6 0x1 -#define MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x244 0x62c 0x7d8 0x0 0x3 -#define MX6QDL_PAD_KEY_COL0__ENET_RX_DATA3 0x244 0x62c 0x824 0x1 0x0 -#define MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x244 0x62c 0x7c0 0x2 0x1 -#define MX6QDL_PAD_KEY_COL0__KEY_COL0 0x244 0x62c 0x000 0x3 0x0 -#define MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x244 0x62c 0x000 0x4 0x0 -#define MX6QDL_PAD_KEY_COL0__UART4_RX_DATA 0x244 0x62c 0x914 0x4 0x2 -#define MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x244 0x62c 0x000 0x5 0x0 -#define MX6QDL_PAD_KEY_COL0__DCIC1_OUT 0x244 0x62c 0x000 0x6 0x0 -#define MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x248 0x630 0x7dc 0x0 0x3 -#define MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x248 0x630 0x810 0x1 0x1 -#define MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x248 0x630 0x7c4 0x2 0x1 -#define MX6QDL_PAD_KEY_COL1__KEY_COL1 0x248 0x630 0x000 0x3 0x0 -#define MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x248 0x630 0x000 0x4 0x0 -#define MX6QDL_PAD_KEY_COL1__UART5_RX_DATA 0x248 0x630 0x91c 0x4 0x2 -#define MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x248 0x630 0x000 0x5 0x0 -#define MX6QDL_PAD_KEY_COL1__SD1_VSELECT 0x248 0x630 0x000 0x6 0x0 -#define MX6QDL_PAD_KEY_COL2__ECSPI1_SS1 0x24c 0x634 0x7e8 0x0 0x2 -#define MX6QDL_PAD_KEY_COL2__ENET_RX_DATA2 0x24c 0x634 0x820 0x1 0x0 -#define MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x24c 0x634 0x000 0x2 0x0 -#define MX6QDL_PAD_KEY_COL2__KEY_COL2 0x24c 0x634 0x000 0x3 0x0 -#define MX6QDL_PAD_KEY_COL2__ENET_MDC 0x24c 0x634 0x000 0x4 0x0 -#define MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x24c 0x634 0x000 0x5 0x0 -#define MX6QDL_PAD_KEY_COL2__USB_H1_PWR_CTL_WAKE 0x24c 0x634 0x000 0x6 0x0 -#define MX6QDL_PAD_KEY_COL3__ECSPI1_SS3 0x250 0x638 0x7f0 0x0 0x1 -#define MX6QDL_PAD_KEY_COL3__ENET_CRS 0x250 0x638 0x000 0x1 0x0 -#define MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x250 0x638 0x860 0x2 0x1 -#define MX6QDL_PAD_KEY_COL3__KEY_COL3 0x250 0x638 0x000 0x3 0x0 -#define MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x250 0x638 0x870 0x4 0x1 -#define MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x250 0x638 0x000 0x5 0x0 -#define MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x250 0x638 0x8f0 0x6 0x3 -#define MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x254 0x63c 0x000 0x0 0x0 -#define MX6QDL_PAD_KEY_COL4__IPU1_SISG4 0x254 0x63c 0x000 0x1 0x0 -#define MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x254 0x63c 0x920 0x2 0x1 -#define MX6QDL_PAD_KEY_COL4__KEY_COL4 0x254 0x63c 0x000 0x3 0x0 -#define MX6QDL_PAD_KEY_COL4__UART5_RTS_B 0x254 0x63c 0x918 0x4 0x2 -#define MX6QDL_PAD_KEY_COL4__UART5_CTS_B 0x254 0x63c 0x000 0x4 0x0 -#define MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x254 0x63c 0x000 0x5 0x0 -#define MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x258 0x640 0x7e0 0x0 0x3 -#define MX6QDL_PAD_KEY_ROW0__ENET_TX_DATA3 0x258 0x640 0x000 0x1 0x0 -#define MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x258 0x640 0x7b4 0x2 0x1 -#define MX6QDL_PAD_KEY_ROW0__KEY_ROW0 0x258 0x640 0x000 0x3 0x0 -#define MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x258 0x640 0x914 0x4 0x3 -#define MX6QDL_PAD_KEY_ROW0__UART4_TX_DATA 0x258 0x640 0x000 0x4 0x0 -#define MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x258 0x640 0x000 0x5 0x0 -#define MX6QDL_PAD_KEY_ROW0__DCIC2_OUT 0x258 0x640 0x000 0x6 0x0 -#define MX6QDL_PAD_KEY_ROW1__ECSPI1_SS0 0x25c 0x644 0x7e4 0x0 0x3 -#define MX6QDL_PAD_KEY_ROW1__ENET_COL 0x25c 0x644 0x000 0x1 0x0 -#define MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x25c 0x644 0x7b0 0x2 0x1 -#define MX6QDL_PAD_KEY_ROW1__KEY_ROW1 0x25c 0x644 0x000 0x3 0x0 -#define MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x25c 0x644 0x91c 0x4 0x3 -#define MX6QDL_PAD_KEY_ROW1__UART5_TX_DATA 0x25c 0x644 0x000 0x4 0x0 -#define MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x25c 0x644 0x000 0x5 0x0 -#define MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x25c 0x644 0x000 0x6 0x0 -#define MX6QDL_PAD_KEY_ROW2__ECSPI1_SS2 0x260 0x648 0x7ec 0x0 0x1 -#define MX6QDL_PAD_KEY_ROW2__ENET_TX_DATA2 0x260 0x648 0x000 0x1 0x0 -#define MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x260 0x648 0x7c8 0x2 0x1 -#define MX6QDL_PAD_KEY_ROW2__KEY_ROW2 0x260 0x648 0x000 0x3 0x0 -#define MX6QDL_PAD_KEY_ROW2__SD2_VSELECT 0x260 0x648 0x000 0x4 0x0 -#define MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x260 0x648 0x000 0x5 0x0 -#define MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x260 0x648 0x85c 0x6 0x1 -#define MX6QDL_PAD_KEY_ROW3__ASRC_EXT_CLK 0x264 0x64c 0x794 0x1 0x2 -#define MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x264 0x64c 0x864 0x2 0x1 -#define MX6QDL_PAD_KEY_ROW3__KEY_ROW3 0x264 0x64c 0x000 0x3 0x0 -#define MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x264 0x64c 0x874 0x4 0x1 -#define MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x264 0x64c 0x000 0x5 0x0 -#define MX6QDL_PAD_KEY_ROW3__SD1_VSELECT 0x264 0x64c 0x000 0x6 0x0 -#define MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x268 0x650 0x7cc 0x0 0x0 -#define MX6QDL_PAD_KEY_ROW4__IPU1_SISG5 0x268 0x650 0x000 0x1 0x0 -#define MX6QDL_PAD_KEY_ROW4__USB_OTG_PWR 0x268 0x650 0x000 0x2 0x0 -#define MX6QDL_PAD_KEY_ROW4__KEY_ROW4 0x268 0x650 0x000 0x3 0x0 -#define MX6QDL_PAD_KEY_ROW4__UART5_CTS_B 0x268 0x650 0x000 0x4 0x0 -#define MX6QDL_PAD_KEY_ROW4__UART5_RTS_B 0x268 0x650 0x918 0x4 0x3 -#define MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x268 0x650 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_ALE__NAND_ALE 0x26c 0x654 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x26c 0x654 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x26c 0x654 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_CLE__NAND_CLE 0x270 0x658 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x270 0x658 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0x274 0x65c 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x274 0x65c 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0x278 0x660 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_CS1__SD4_VSELECT 0x278 0x660 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x278 0x660 0x000 0x2 0x0 -#define MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x278 0x660 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_CS2__NAND_CE2_B 0x27c 0x664 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_CS2__IPU1_SISG0 0x27c 0x664 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_CS2__ESAI_TX0 0x27c 0x664 0x844 0x2 0x1 -#define MX6QDL_PAD_NANDF_CS2__EIM_CRE 0x27c 0x664 0x000 0x3 0x0 -#define MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x27c 0x664 0x000 0x4 0x0 -#define MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x27c 0x664 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_CS3__NAND_CE3_B 0x280 0x668 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_CS3__IPU1_SISG1 0x280 0x668 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x280 0x668 0x848 0x2 0x1 -#define MX6QDL_PAD_NANDF_CS3__EIM_ADDR26 0x280 0x668 0x000 0x3 0x0 -#define MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x280 0x668 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_CS3__I2C4_SDA 0x280 0x668 0x884 0x9 0x2 -#define MX6QDL_PAD_NANDF_D0__NAND_DATA00 0x284 0x66c 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x284 0x66c 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x284 0x66c 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_D1__NAND_DATA01 0x288 0x670 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x288 0x670 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x288 0x670 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_D2__NAND_DATA02 0x28c 0x674 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x28c 0x674 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x28c 0x674 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_D3__NAND_DATA03 0x290 0x678 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x290 0x678 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x290 0x678 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_D4__NAND_DATA04 0x294 0x67c 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x294 0x67c 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x294 0x67c 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_D5__NAND_DATA05 0x298 0x680 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x298 0x680 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x298 0x680 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_D6__NAND_DATA06 0x29c 0x684 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x29c 0x684 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x29c 0x684 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_D7__NAND_DATA07 0x2a0 0x688 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x2a0 0x688 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x2a0 0x688 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0x2a4 0x68c 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x2a4 0x68c 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0x2a8 0x690 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x2a8 0x690 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_WP_B__I2C4_SCL 0x2a8 0x690 0x880 0x9 0x2 -#define MX6QDL_PAD_RGMII_RD0__HSI_RX_READY 0x2ac 0x694 0x000 0x0 0x0 -#define MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x2ac 0x694 0x818 0x1 0x1 -#define MX6QDL_PAD_RGMII_RD0__GPIO6_IO25 0x2ac 0x694 0x000 0x5 0x0 -#define MX6QDL_PAD_RGMII_RD1__HSI_TX_FLAG 0x2b0 0x698 0x000 0x0 0x0 -#define MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x2b0 0x698 0x81c 0x1 0x1 -#define MX6QDL_PAD_RGMII_RD1__GPIO6_IO27 0x2b0 0x698 0x000 0x5 0x0 -#define MX6QDL_PAD_RGMII_RD2__HSI_TX_DATA 0x2b4 0x69c 0x000 0x0 0x0 -#define MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x2b4 0x69c 0x820 0x1 0x1 -#define MX6QDL_PAD_RGMII_RD2__GPIO6_IO28 0x2b4 0x69c 0x000 0x5 0x0 -#define MX6QDL_PAD_RGMII_RD3__HSI_TX_WAKE 0x2b8 0x6a0 0x000 0x0 0x0 -#define MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x2b8 0x6a0 0x824 0x1 0x1 -#define MX6QDL_PAD_RGMII_RD3__GPIO6_IO29 0x2b8 0x6a0 0x000 0x5 0x0 -#define MX6QDL_PAD_RGMII_RX_CTL__USB_H3_DATA 0x2bc 0x6a4 0x000 0x0 0x0 -#define MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x2bc 0x6a4 0x828 0x1 0x1 -#define MX6QDL_PAD_RGMII_RX_CTL__GPIO6_IO24 0x2bc 0x6a4 0x000 0x5 0x0 -#define MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x2c0 0x6a8 0x000 0x0 0x0 -#define MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x2c0 0x6a8 0x814 0x1 0x1 -#define MX6QDL_PAD_RGMII_RXC__GPIO6_IO30 0x2c0 0x6a8 0x000 0x5 0x0 -#define MX6QDL_PAD_RGMII_TD0__HSI_TX_READY 0x2c4 0x6ac 0x000 0x0 0x0 -#define MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x2c4 0x6ac 0x000 0x1 0x0 -#define MX6QDL_PAD_RGMII_TD0__GPIO6_IO20 0x2c4 0x6ac 0x000 0x5 0x0 -#define MX6QDL_PAD_RGMII_TD1__HSI_RX_FLAG 0x2c8 0x6b0 0x000 0x0 0x0 -#define MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x2c8 0x6b0 0x000 0x1 0x0 -#define MX6QDL_PAD_RGMII_TD1__GPIO6_IO21 0x2c8 0x6b0 0x000 0x5 0x0 -#define MX6QDL_PAD_RGMII_TD2__HSI_RX_DATA 0x2cc 0x6b4 0x000 0x0 0x0 -#define MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x2cc 0x6b4 0x000 0x1 0x0 -#define MX6QDL_PAD_RGMII_TD2__GPIO6_IO22 0x2cc 0x6b4 0x000 0x5 0x0 -#define MX6QDL_PAD_RGMII_TD3__HSI_RX_WAKE 0x2d0 0x6b8 0x000 0x0 0x0 -#define MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x2d0 0x6b8 0x000 0x1 0x0 -#define MX6QDL_PAD_RGMII_TD3__GPIO6_IO23 0x2d0 0x6b8 0x000 0x5 0x0 -#define MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x2d4 0x6bc 0x000 0x0 0x0 -#define MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x2d4 0x6bc 0x000 0x1 0x0 -#define MX6QDL_PAD_RGMII_TX_CTL__GPIO6_IO26 0x2d4 0x6bc 0x000 0x5 0x0 -#define MX6QDL_PAD_RGMII_TX_CTL__ENET_REF_CLK 0x2d4 0x6bc 0x80c 0x7 0x1 -#define MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x2d8 0x6c0 0x000 0x0 0x0 -#define MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x2d8 0x6c0 0x000 0x1 0x0 -#define MX6QDL_PAD_RGMII_TXC__SPDIF_EXT_CLK 0x2d8 0x6c0 0x8f4 0x2 0x1 -#define MX6QDL_PAD_RGMII_TXC__GPIO6_IO19 0x2d8 0x6c0 0x000 0x5 0x0 -#define MX6QDL_PAD_RGMII_TXC__XTALOSC_REF_CLK_24M 0x2d8 0x6c0 0x000 0x7 0x0 -#define MX6QDL_PAD_SD1_CLK__SD1_CLK 0x2dc 0x6c4 0x928 0x0 0x1 -#define MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x2dc 0x6c4 0x000 0x2 0x0 -#define MX6QDL_PAD_SD1_CLK__GPT_CLKIN 0x2dc 0x6c4 0x000 0x3 0x0 -#define MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x2dc 0x6c4 0x000 0x5 0x0 -#define MX6QDL_PAD_SD1_CMD__SD1_CMD 0x2e0 0x6c8 0x000 0x0 0x0 -#define MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x2e0 0x6c8 0x000 0x2 0x0 -#define MX6QDL_PAD_SD1_CMD__GPT_COMPARE1 0x2e0 0x6c8 0x000 0x3 0x0 -#define MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0x2e0 0x6c8 0x000 0x5 0x0 -#define MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x2e4 0x6cc 0x000 0x0 0x0 -#define MX6QDL_PAD_SD1_DAT0__GPT_CAPTURE1 0x2e4 0x6cc 0x000 0x3 0x0 -#define MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x2e4 0x6cc 0x000 0x5 0x0 -#define MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x2e8 0x6d0 0x000 0x0 0x0 -#define MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x2e8 0x6d0 0x000 0x2 0x0 -#define MX6QDL_PAD_SD1_DAT1__GPT_CAPTURE2 0x2e8 0x6d0 0x000 0x3 0x0 -#define MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x2e8 0x6d0 0x000 0x5 0x0 -#define MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x2ec 0x6d4 0x000 0x0 0x0 -#define MX6QDL_PAD_SD1_DAT2__GPT_COMPARE2 0x2ec 0x6d4 0x000 0x2 0x0 -#define MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x2ec 0x6d4 0x000 0x3 0x0 -#define MX6QDL_PAD_SD1_DAT2__WDOG1_B 0x2ec 0x6d4 0x000 0x4 0x0 -#define MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x2ec 0x6d4 0x000 0x5 0x0 -#define MX6QDL_PAD_SD1_DAT2__WDOG1_RESET_B_DEB 0x2ec 0x6d4 0x000 0x6 0x0 -#define MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x2f0 0x6d8 0x000 0x0 0x0 -#define MX6QDL_PAD_SD1_DAT3__GPT_COMPARE3 0x2f0 0x6d8 0x000 0x2 0x0 -#define MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x2f0 0x6d8 0x000 0x3 0x0 -#define MX6QDL_PAD_SD1_DAT3__WDOG2_B 0x2f0 0x6d8 0x000 0x4 0x0 -#define MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x2f0 0x6d8 0x000 0x5 0x0 -#define MX6QDL_PAD_SD1_DAT3__WDOG2_RESET_B_DEB 0x2f0 0x6d8 0x000 0x6 0x0 -#define MX6QDL_PAD_SD2_CLK__SD2_CLK 0x2f4 0x6dc 0x930 0x0 0x1 -#define MX6QDL_PAD_SD2_CLK__KEY_COL5 0x2f4 0x6dc 0x8c0 0x2 0x3 -#define MX6QDL_PAD_SD2_CLK__AUD4_RXFS 0x2f4 0x6dc 0x7a4 0x3 0x1 -#define MX6QDL_PAD_SD2_CLK__GPIO1_IO10 0x2f4 0x6dc 0x000 0x5 0x0 -#define MX6QDL_PAD_SD2_CMD__SD2_CMD 0x2f8 0x6e0 0x000 0x0 0x0 -#define MX6QDL_PAD_SD2_CMD__KEY_ROW5 0x2f8 0x6e0 0x8cc 0x2 0x2 -#define MX6QDL_PAD_SD2_CMD__AUD4_RXC 0x2f8 0x6e0 0x7a0 0x3 0x1 -#define MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x2f8 0x6e0 0x000 0x5 0x0 -#define MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x2fc 0x6e4 0x000 0x0 0x0 -#define MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x2fc 0x6e4 0x798 0x3 0x1 -#define MX6QDL_PAD_SD2_DAT0__KEY_ROW7 0x2fc 0x6e4 0x8d4 0x4 0x2 -#define MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x2fc 0x6e4 0x000 0x5 0x0 -#define MX6QDL_PAD_SD2_DAT0__DCIC2_OUT 0x2fc 0x6e4 0x000 0x6 0x0 -#define MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x300 0x6e8 0x000 0x0 0x0 -#define MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0x300 0x6e8 0x000 0x2 0x0 -#define MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x300 0x6e8 0x7ac 0x3 0x1 -#define MX6QDL_PAD_SD2_DAT1__KEY_COL7 0x300 0x6e8 0x8c8 0x4 0x2 -#define MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x300 0x6e8 0x000 0x5 0x0 -#define MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x304 0x6ec 0x000 0x0 0x0 -#define MX6QDL_PAD_SD2_DAT2__EIM_CS3_B 0x304 0x6ec 0x000 0x2 0x0 -#define MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x304 0x6ec 0x79c 0x3 0x1 -#define MX6QDL_PAD_SD2_DAT2__KEY_ROW6 0x304 0x6ec 0x8d0 0x4 0x2 -#define MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x304 0x6ec 0x000 0x5 0x0 -#define MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x308 0x6f0 0x000 0x0 0x0 -#define MX6QDL_PAD_SD2_DAT3__KEY_COL6 0x308 0x6f0 0x8c4 0x2 0x2 -#define MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x308 0x6f0 0x7a8 0x3 0x1 -#define MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x308 0x6f0 0x000 0x5 0x0 -#define MX6QDL_PAD_SD3_CLK__SD3_CLK 0x30c 0x6f4 0x934 0x0 0x1 -#define MX6QDL_PAD_SD3_CLK__UART2_RTS_B 0x30c 0x6f4 0x900 0x1 0x2 -#define MX6QDL_PAD_SD3_CLK__UART2_CTS_B 0x30c 0x6f4 0x000 0x1 0x0 -#define MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x30c 0x6f4 0x7c8 0x2 0x2 -#define MX6QDL_PAD_SD3_CLK__GPIO7_IO03 0x30c 0x6f4 0x000 0x5 0x0 -#define MX6QDL_PAD_SD3_CMD__SD3_CMD 0x310 0x6f8 0x000 0x0 0x0 -#define MX6QDL_PAD_SD3_CMD__UART2_CTS_B 0x310 0x6f8 0x000 0x1 0x0 -#define MX6QDL_PAD_SD3_CMD__UART2_RTS_B 0x310 0x6f8 0x900 0x1 0x3 -#define MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x310 0x6f8 0x000 0x2 0x0 -#define MX6QDL_PAD_SD3_CMD__GPIO7_IO02 0x310 0x6f8 0x000 0x5 0x0 -#define MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x314 0x6fc 0x000 0x0 0x0 -#define MX6QDL_PAD_SD3_DAT0__UART1_CTS_B 0x314 0x6fc 0x000 0x1 0x0 -#define MX6QDL_PAD_SD3_DAT0__UART1_RTS_B 0x314 0x6fc 0x8f8 0x1 0x2 -#define MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x314 0x6fc 0x000 0x2 0x0 -#define MX6QDL_PAD_SD3_DAT0__GPIO7_IO04 0x314 0x6fc 0x000 0x5 0x0 -#define MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x318 0x700 0x000 0x0 0x0 -#define MX6QDL_PAD_SD3_DAT1__UART1_RTS_B 0x318 0x700 0x8f8 0x1 0x3 -#define MX6QDL_PAD_SD3_DAT1__UART1_CTS_B 0x318 0x700 0x000 0x1 0x0 -#define MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x318 0x700 0x7cc 0x2 0x1 -#define MX6QDL_PAD_SD3_DAT1__GPIO7_IO05 0x318 0x700 0x000 0x5 0x0 -#define MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x31c 0x704 0x000 0x0 0x0 -#define MX6QDL_PAD_SD3_DAT2__GPIO7_IO06 0x31c 0x704 0x000 0x5 0x0 -#define MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x320 0x708 0x000 0x0 0x0 -#define MX6QDL_PAD_SD3_DAT3__UART3_CTS_B 0x320 0x708 0x000 0x1 0x0 -#define MX6QDL_PAD_SD3_DAT3__UART3_RTS_B 0x320 0x708 0x908 0x1 0x4 -#define MX6QDL_PAD_SD3_DAT3__GPIO7_IO07 0x320 0x708 0x000 0x5 0x0 -#define MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x324 0x70c 0x000 0x0 0x0 -#define MX6QDL_PAD_SD3_DAT4__UART2_RX_DATA 0x324 0x70c 0x904 0x1 0x4 -#define MX6QDL_PAD_SD3_DAT4__UART2_TX_DATA 0x324 0x70c 0x000 0x1 0x0 -#define MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x324 0x70c 0x000 0x5 0x0 -#define MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x328 0x710 0x000 0x0 0x0 -#define MX6QDL_PAD_SD3_DAT5__UART2_TX_DATA 0x328 0x710 0x000 0x1 0x0 -#define MX6QDL_PAD_SD3_DAT5__UART2_RX_DATA 0x328 0x710 0x904 0x1 0x5 -#define MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x328 0x710 0x000 0x5 0x0 -#define MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x32c 0x714 0x000 0x0 0x0 -#define MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x32c 0x714 0x8fc 0x1 0x2 -#define MX6QDL_PAD_SD3_DAT6__UART1_TX_DATA 0x32c 0x714 0x000 0x1 0x0 -#define MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x32c 0x714 0x000 0x5 0x0 -#define MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x330 0x718 0x000 0x0 0x0 -#define MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x330 0x718 0x000 0x1 0x0 -#define MX6QDL_PAD_SD3_DAT7__UART1_RX_DATA 0x330 0x718 0x8fc 0x1 0x3 -#define MX6QDL_PAD_SD3_DAT7__GPIO6_IO17 0x330 0x718 0x000 0x5 0x0 -#define MX6QDL_PAD_SD3_RST__SD3_RESET 0x334 0x71c 0x000 0x0 0x0 -#define MX6QDL_PAD_SD3_RST__UART3_RTS_B 0x334 0x71c 0x908 0x1 0x5 -#define MX6QDL_PAD_SD3_RST__UART3_CTS_B 0x334 0x71c 0x000 0x1 0x0 -#define MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x334 0x71c 0x000 0x5 0x0 -#define MX6QDL_PAD_SD4_CLK__SD4_CLK 0x338 0x720 0x938 0x0 0x1 -#define MX6QDL_PAD_SD4_CLK__NAND_WE_B 0x338 0x720 0x000 0x1 0x0 -#define MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x338 0x720 0x90c 0x2 0x2 -#define MX6QDL_PAD_SD4_CLK__UART3_TX_DATA 0x338 0x720 0x000 0x2 0x0 -#define MX6QDL_PAD_SD4_CLK__GPIO7_IO10 0x338 0x720 0x000 0x5 0x0 -#define MX6QDL_PAD_SD4_CMD__SD4_CMD 0x33c 0x724 0x000 0x0 0x0 -#define MX6QDL_PAD_SD4_CMD__NAND_RE_B 0x33c 0x724 0x000 0x1 0x0 -#define MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x33c 0x724 0x000 0x2 0x0 -#define MX6QDL_PAD_SD4_CMD__UART3_RX_DATA 0x33c 0x724 0x90c 0x2 0x3 -#define MX6QDL_PAD_SD4_CMD__GPIO7_IO09 0x33c 0x724 0x000 0x5 0x0 -#define MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x340 0x728 0x000 0x1 0x0 -#define MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x340 0x728 0x000 0x2 0x0 -#define MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x340 0x728 0x000 0x5 0x0 -#define MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x344 0x72c 0x000 0x1 0x0 -#define MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x344 0x72c 0x000 0x2 0x0 -#define MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x344 0x72c 0x000 0x5 0x0 -#define MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x348 0x730 0x000 0x1 0x0 -#define MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x348 0x730 0x000 0x2 0x0 -#define MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x348 0x730 0x000 0x5 0x0 -#define MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x34c 0x734 0x000 0x1 0x0 -#define MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x34c 0x734 0x000 0x5 0x0 -#define MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x350 0x738 0x000 0x1 0x0 -#define MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x350 0x738 0x904 0x2 0x6 -#define MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA 0x350 0x738 0x000 0x2 0x0 -#define MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x350 0x738 0x000 0x5 0x0 -#define MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x354 0x73c 0x000 0x1 0x0 -#define MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x354 0x73c 0x900 0x2 0x4 -#define MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 0x354 0x73c 0x000 0x2 0x0 -#define MX6QDL_PAD_SD4_DAT5__GPIO2_IO13 0x354 0x73c 0x000 0x5 0x0 -#define MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x358 0x740 0x000 0x1 0x0 -#define MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x358 0x740 0x000 0x2 0x0 -#define MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x358 0x740 0x900 0x2 0x5 -#define MX6QDL_PAD_SD4_DAT6__GPIO2_IO14 0x358 0x740 0x000 0x5 0x0 -#define MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x35c 0x744 0x000 0x1 0x0 -#define MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x35c 0x744 0x000 0x2 0x0 -#define MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x35c 0x744 0x904 0x2 0x7 -#define MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x35c 0x744 0x000 0x5 0x0 - -#endif /* __DTS_IMX6DL_PINFUNC_H */ diff --git a/sys/gnu/dts/arm/imx6dl-rex-basic.dts b/sys/gnu/dts/arm/imx6dl-rex-basic.dts deleted file mode 100644 index 0f1616bfa9a..00000000000 --- a/sys/gnu/dts/arm/imx6dl-rex-basic.dts +++ /dev/null @@ -1,27 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright 2014 FEDEVEL, Inc. - * - * Author: Robert Nelson - */ -/dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-rex.dtsi" - -/ { - model = "Rex Basic i.MX6 Dual Lite Board"; - compatible = "rex,imx6dl-rex-basic", "fsl,imx6dl"; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x20000000>; - }; -}; - -&ecspi3 { - flash: m25p80@0 { - compatible = "sst,sst25vf016b", "jedec,spi-nor"; - spi-max-frequency = <20000000>; - reg = <0>; - }; -}; diff --git a/sys/gnu/dts/arm/imx6dl-riotboard.dts b/sys/gnu/dts/arm/imx6dl-riotboard.dts deleted file mode 100644 index 829654e1835..00000000000 --- a/sys/gnu/dts/arm/imx6dl-riotboard.dts +++ /dev/null @@ -1,580 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright 2014 Iain Paton - */ - -/dts-v1/; -#include "imx6dl.dtsi" -#include - -/ { - model = "RIoTboard i.MX6S"; - compatible = "riot,imx6s-riotboard", "fsl,imx6dl"; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x40000000>; - }; - - chosen { - stdout-path = "serial1:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_led>; - - led0: user1 { - label = "user1"; - gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - - led1: user2 { - label = "user2"; - gpios = <&gpio3 28 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - }; - - sound { - compatible = "fsl,imx-audio-sgtl5000"; - model = "imx6-riotboard-sgtl5000"; - ssi-controller = <&ssi1>; - audio-codec = <&codec>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - mux-int-port = <1>; - mux-ext-port = <3>; - }; - - reg_2p5v: regulator-2p5v { - compatible = "regulator-fixed"; - regulator-name = "2P5V"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_usb_otg_vbus: regulator-usbotgvbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 GPIO_ACTIVE_LOW>; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; - -&clks { - fsl,pmic-stby-poweroff; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii-id"; - phy-reset-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; - interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, - <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; - fsl,err006687-workaround-present; - status = "okay"; -}; - -&gpio1 { - gpio-line-names = - "", "", "SD2_WP", "", "SD2_CD", "I2C3_SCL", - "I2C3_SDA", "I2C4_SCL", - "I2C4_SDA", "", "", "", "", "", "", "", - "", "PWM3", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&gpio3 { - gpio-line-names = - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "USB_OTG_VBUS", "", - "UART3_TXD", "UART3_RXD", "", "", "EIM_D28", "", "", ""; -}; - -&gpio4 { - gpio-line-names = - "", "", "", "", "", "", "UART4_TXD", "UART4_RXD", - "UART5_TXD", "UART5_RXD", "", "", "", "", "", "", - "GPIO4_16", "GPIO4_17", "GPIO4_18", "GPIO4_19", "", - "CSPI3_CLK", "CSPI3_MOSI", "CSPI3_MISO", - "CSPI3_CS0", "CSPI3_CS1", "GPIO4_26", "GPIO4_27", - "CSPI3_RDY", "PWM1", "PWM2", "GPIO4_31"; -}; - -&gpio5 { - gpio-line-names = - "", "", "EIM_A25", "", "", "GPIO5_05", "GPIO5_06", - "GPIO5_07", - "GPIO5_08", "CSPI2_CS1", "CSPI2_MOSI", "CSPI2_MISO", - "CSPI2_CS0", "CSPI2_CLK", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&gpio7 { - gpio-line-names = - "SD3_CD", "SD3_WP", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&hdmi { - ddc-i2c-bus = <&i2c2>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - codec: sgtl5000@a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - clocks = <&clks IMX6QDL_CLK_CKO>; - VDDA-supply = <®_2p5v>; - VDDIO-supply = <®_3p3v>; - }; - - pmic: pf0100@8 { - compatible = "fsl,pfuze100"; - reg = <0x08>; - interrupt-parent = <&gpio5>; - interrupts = <16 8>; - fsl,pmic-stby-poweroff; - - regulators { - reg_vddcore: sw1ab { /* VDDARM_IN */ - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-always-on; - }; - - reg_vddsoc: sw1c { /* VDDSOC_IN */ - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-always-on; - }; - - reg_gen_3v3: sw2 { /* VDDHIGH_IN */ - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_ddr_1v5a: sw3a { /* NVCC_DRAM, NVCC_RGMII */ - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-always-on; - }; - - reg_ddr_1v5b: sw3b { /* NVCC_DRAM, NVCC_RGMII */ - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-always-on; - }; - - reg_ddr_vtt: sw4 { /* MIPI conn */ - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-always-on; - }; - - reg_5v_600mA: swbst { /* not used */ - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - }; - - reg_snvs_3v: vsnvs { /* VDD_SNVS_IN */ - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - }; - - vref_reg: vrefddr { /* VREF_DDR */ - regulator-boot-on; - regulator-always-on; - }; - - reg_vgen1_1v5: vgen1 { /* not used */ - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - reg_vgen2_1v2_eth: vgen2 { /* pcie ? */ - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - regulator-always-on; - }; - - reg_vgen3_2v8: vgen3 { /* not used */ - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - reg_vgen4_1v8: vgen4 { /* NVCC_SD3 */ - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_vgen5_2v5_sgtl: vgen5 { /* Pwr LED & 5V0_delayed enable */ - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_vgen6_3v3: vgen6 { /* #V#_DELAYED enable, MIPI */ - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&i2c4 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4>; - clocks = <&clks 116>; - status = "okay"; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "okay"; -}; - -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm2>; - status = "okay"; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; - status = "okay"; -}; - -&pwm4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm4>; - status = "okay"; -}; - -&ssi1 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - status = "okay"; -}; - -&usbh1 { - dr_mode = "host"; - disable-over-current; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - dr_mode = "otg"; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; - vmmc-supply = <®_3p3v>; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; - vmmc-supply = <®_3p3v>; - status = "okay"; -}; - -&usdhc4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc4>; - vmmc-supply = <®_3p3v>; - non-removable; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - - imx6-riotboard { - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 - MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 - MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 - MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* CAM_MCLK */ - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 - MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x000b1 /* CS0 */ - >; - }; - - pinctrl_ecspi2: ecspi2grp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x000b1 /* CS1 */ - MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI 0x100b1 - MX6QDL_PAD_DISP0_DAT17__ECSPI2_MISO 0x100b1 - MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x000b1 /* CS0 */ - MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK 0x100b1 - >; - }; - - pinctrl_ecspi3: ecspi3grp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 - MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 - MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 - MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x000b1 /* CS0 */ - MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x000b1 /* CS1 */ - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x0a0b1 /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */ - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 /* AR8035 pin strapping: IO voltage: pull up */ - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x13030 /* AR8035 pin strapping: PHYADDR#0: pull down */ - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030 /* AR8035 pin strapping: PHYADDR#1: pull down */ - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 /* AR8035 pin strapping: MODE#1: pull up */ - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 /* AR8035 pin strapping: MODE#3: pull up */ - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x130b0 /* AR8035 pin strapping: MODE#0: pull down */ - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 /* GPIO16 -> AR8035 25MHz */ - MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x130b0 /* RGMII_nRST */ - MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x180b0 /* AR8035 interrupt */ - MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 - MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c4: i2c4grp { - fsl,pins = < - MX6QDL_PAD_GPIO_7__I2C4_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_8__I2C4_SDA 0x4001b8b1 - >; - }; - - pinctrl_led: ledgrp { - fsl,pins = < - MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b1 /* user led0 */ - MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x1b0b1 /* user led1 */ - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm4: pwm4grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x000b0 /* MX6QDL_PAD_EIM_D22__USB_OTG_PWR */ - MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* SD2 CD */ - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1f0b0 /* SD2 WP */ - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* SD3 CD */ - MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0 /* SD3 WP */ - >; - }; - - pinctrl_usdhc4: usdhc4grp { - fsl,pins = < - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 - MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x17059 /* SD4 RST (eMMC) */ - >; - }; - }; -}; diff --git a/sys/gnu/dts/arm/imx6dl-sabreauto.dts b/sys/gnu/dts/arm/imx6dl-sabreauto.dts deleted file mode 100644 index ff3283c83a3..00000000000 --- a/sys/gnu/dts/arm/imx6dl-sabreauto.dts +++ /dev/null @@ -1,28 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// -// Copyright (C) 2013 Freescale Semiconductor, Inc. - -/dts-v1/; - -#include "imx6dl.dtsi" -#include "imx6qdl-sabreauto.dtsi" - -/ { - model = "Freescale i.MX6 DualLite/Solo SABRE Automotive Board"; - compatible = "fsl,imx6dl-sabreauto", "fsl,imx6dl"; -}; - -&cpu0 { - operating-points = < - /* kHz uV */ - 996000 1275000 - 792000 1175000 - 396000 1150000 - >; - fsl,soc-operating-points = < - /* ARM kHz SOC-PU uV */ - 996000 1200000 - 792000 1175000 - 396000 1175000 - >; -}; diff --git a/sys/gnu/dts/arm/imx6dl-sabrelite.dts b/sys/gnu/dts/arm/imx6dl-sabrelite.dts deleted file mode 100644 index 33040761b25..00000000000 --- a/sys/gnu/dts/arm/imx6dl-sabrelite.dts +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Copyright 2011 Freescale Semiconductor, Inc. - * Copyright 2011 Linaro Ltd. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-sabrelite.dtsi" - -/ { - model = "Freescale i.MX6 DualLite SABRE Lite Board"; - compatible = "fsl,imx6dl-sabrelite", "fsl,imx6dl"; -}; - -&ipu1_csi1_from_ipu1_csi1_mux { - clock-lanes = <0>; - data-lanes = <1 2>; -}; diff --git a/sys/gnu/dts/arm/imx6dl-sabresd.dts b/sys/gnu/dts/arm/imx6dl-sabresd.dts deleted file mode 100644 index cd6bbf22a16..00000000000 --- a/sys/gnu/dts/arm/imx6dl-sabresd.dts +++ /dev/null @@ -1,18 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// -// Copyright (C) 2013 Freescale Semiconductor, Inc. - -/dts-v1/; - -#include "imx6dl.dtsi" -#include "imx6qdl-sabresd.dtsi" - -/ { - model = "Freescale i.MX6 DualLite SABRE Smart Device Board"; - compatible = "fsl,imx6dl-sabresd", "fsl,imx6dl"; -}; - -&ipu1_csi1_from_ipu1_csi1_mux { - clock-lanes = <0>; - data-lanes = <1 2>; -}; diff --git a/sys/gnu/dts/arm/imx6dl-savageboard.dts b/sys/gnu/dts/arm/imx6dl-savageboard.dts deleted file mode 100644 index b95469c520a..00000000000 --- a/sys/gnu/dts/arm/imx6dl-savageboard.dts +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright (C) 2017 Milo Kim - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include "imx6dl.dtsi" -#include "imx6qdl-savageboard.dtsi" - -/ { - model = "Poslab SavageBoard Dual"; - compatible = "poslab,imx6dl-savageboard", "fsl,imx6dl"; -}; diff --git a/sys/gnu/dts/arm/imx6dl-ts4900.dts b/sys/gnu/dts/arm/imx6dl-ts4900.dts deleted file mode 100644 index 3d60cc725d9..00000000000 --- a/sys/gnu/dts/arm/imx6dl-ts4900.dts +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Copyright 2015 Technologic Systems - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-ts4900.dtsi" - -/ { - model = "Technologic Systems i.MX6 Solo/DualLite TS-4900 (Default Device Tree)"; - compatible = "technologic,imx6dl-ts4900", "fsl,imx6dl"; - - /* Will be filled by the bootloader */ - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0>; - }; -}; diff --git a/sys/gnu/dts/arm/imx6dl-ts7970.dts b/sys/gnu/dts/arm/imx6dl-ts7970.dts deleted file mode 100644 index 5da6feba2e6..00000000000 --- a/sys/gnu/dts/arm/imx6dl-ts7970.dts +++ /dev/null @@ -1,56 +0,0 @@ -/* - * Copyright 2015 Technologic Systems - * Copyright 2017 Savoir-faire Linux - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-ts7970.dtsi" - -/ { - model = "Technologic Systems i.MX6 Solo/DualLite TS-7970 (Default Device Tree)"; - compatible = "technologic,imx6dl-ts7970", "fsl,imx6dl"; - - /* Will be filled by the bootloader */ - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0>; - }; -}; diff --git a/sys/gnu/dts/arm/imx6dl-tx6dl-comtft.dts b/sys/gnu/dts/arm/imx6dl-tx6dl-comtft.dts deleted file mode 100644 index 51a9bb9d6bc..00000000000 --- a/sys/gnu/dts/arm/imx6dl-tx6dl-comtft.dts +++ /dev/null @@ -1,79 +0,0 @@ -/* - * Copyright 2014-2017 Lothar Waßmann - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-tx6.dtsi" -#include "imx6qdl-tx6-lcd.dtsi" - -/ { - model = "Ka-Ro electronics TX6DL Module on CoMpact TFT"; - compatible = "karo,imx6dl-tx6dl", "fsl,imx6dl"; -}; - -&backlight { - pwms = <&pwm2 0 500000 0>; - /delete-property/ turn-on-delay-ms; -}; - -&can1 { - status = "disabled"; -}; - -&can2 { - xceiver-supply = <®_3v3>; -}; - -&kpp { - status = "disabled"; -}; - -&lcd_panel { - compatible = "edt,etm0700g0edh6"; -}; - -®_can_xcvr { - status = "disabled"; -}; - -&touchscreen { - status = "disabled"; -}; diff --git a/sys/gnu/dts/arm/imx6dl-tx6s-8034-mb7.dts b/sys/gnu/dts/arm/imx6dl-tx6s-8034-mb7.dts deleted file mode 100644 index fc23b4d291a..00000000000 --- a/sys/gnu/dts/arm/imx6dl-tx6s-8034-mb7.dts +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Copyright 2017 Lothar Waßmann - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6dl-tx6s-8034.dts" -#include "imx6qdl-tx6-mb7.dtsi" - -/ { - model = "Ka-Ro electronics TX6S-8034 Module on MB7 baseboard"; -}; diff --git a/sys/gnu/dts/arm/imx6dl-tx6s-8034.dts b/sys/gnu/dts/arm/imx6dl-tx6s-8034.dts deleted file mode 100644 index 9eb2ef17339..00000000000 --- a/sys/gnu/dts/arm/imx6dl-tx6s-8034.dts +++ /dev/null @@ -1,70 +0,0 @@ -/* - * Copyright 2015-2017 Lothar Waßmann - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-tx6.dtsi" -#include "imx6qdl-tx6-lcd.dtsi" - -/ { - model = "Ka-Ro electronics TX6S-8034 Module"; - compatible = "karo,imx6dl-tx6dl", "fsl,imx6dl"; - - cpus { - /delete-node/ cpu@1; - }; -}; - -&ds1339 { - status = "disabled"; -}; - -&pinctrl_usdhc1 { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x070b1 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x070b1 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x070b1 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x070b1 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x070b1 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x070b1 - MX6QDL_PAD_SD3_CMD__GPIO7_IO02 0x170b0 /* SD1 CD */ - >; -}; diff --git a/sys/gnu/dts/arm/imx6dl-tx6s-8035-mb7.dts b/sys/gnu/dts/arm/imx6dl-tx6s-8035-mb7.dts deleted file mode 100644 index 4101c659772..00000000000 --- a/sys/gnu/dts/arm/imx6dl-tx6s-8035-mb7.dts +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Copyright 2017 Lothar Waßmann - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6dl-tx6s-8035.dts" -#include "imx6qdl-tx6-mb7.dtsi" - -/ { - model = "Ka-Ro electronics TX6U-8035 Module on MB7 baseboard"; -}; diff --git a/sys/gnu/dts/arm/imx6dl-tx6s-8035.dts b/sys/gnu/dts/arm/imx6dl-tx6s-8035.dts deleted file mode 100644 index a5532ecc18c..00000000000 --- a/sys/gnu/dts/arm/imx6dl-tx6s-8035.dts +++ /dev/null @@ -1,86 +0,0 @@ -/* - * Copyright 2015-2017 Lothar Waßmann - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-tx6.dtsi" -#include "imx6qdl-tx6-lcd.dtsi" - -/ { - model = "Ka-Ro electronics TX6S-8035 Module"; - compatible = "karo,imx6dl-tx6dl", "fsl,imx6dl"; - - cpus { - /delete-node/ cpu@1; - }; -}; - -&ds1339 { - status = "disabled"; -}; - -&gpmi { - status = "disabled"; -}; - -&usdhc4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc4>; - bus-width = <4>; - non-removable; - no-1-8-v; - fsl,wp-controller; - status = "okay"; -}; - -&iomuxc { - pinctrl_usdhc4: usdhc4grp { - fsl,pins = < - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x070b1 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x070b1 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x070b1 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x070b1 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x070b1 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x070b1 - MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x0b0b1 - >; - }; -}; diff --git a/sys/gnu/dts/arm/imx6dl-tx6u-801x.dts b/sys/gnu/dts/arm/imx6dl-tx6u-801x.dts deleted file mode 100644 index 67ed0452f5d..00000000000 --- a/sys/gnu/dts/arm/imx6dl-tx6u-801x.dts +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Copyright 2014-2017 Lothar Waßmann - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-tx6.dtsi" -#include "imx6qdl-tx6-lcd.dtsi" - -/ { - model = "Ka-Ro electronics TX6U-801x Module"; - compatible = "karo,imx6dl-tx6dl", "fsl,imx6dl"; -}; diff --git a/sys/gnu/dts/arm/imx6dl-tx6u-8033-mb7.dts b/sys/gnu/dts/arm/imx6dl-tx6u-8033-mb7.dts deleted file mode 100644 index d34189fc52d..00000000000 --- a/sys/gnu/dts/arm/imx6dl-tx6u-8033-mb7.dts +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Copyright 2017 Lothar Waßmann - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6dl-tx6u-8033.dts" -#include "imx6qdl-tx6-mb7.dtsi" - -/ { - model = "Ka-Ro electronics TX6U-8033 Module on MB7 baseboard"; -}; diff --git a/sys/gnu/dts/arm/imx6dl-tx6u-8033.dts b/sys/gnu/dts/arm/imx6dl-tx6u-8033.dts deleted file mode 100644 index 7030b2654bb..00000000000 --- a/sys/gnu/dts/arm/imx6dl-tx6u-8033.dts +++ /dev/null @@ -1,82 +0,0 @@ -/* - * Copyright 2014-2017 Lothar Waßmann - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-tx6.dtsi" -#include "imx6qdl-tx6-lcd.dtsi" - -/ { - model = "Ka-Ro electronics TX6U-8033 Module"; - compatible = "karo,imx6dl-tx6dl", "fsl,imx6dl"; -}; - -&ds1339 { - status = "disabled"; -}; - -&gpmi { - status = "disabled"; -}; - -&usdhc4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc4>; - bus-width = <4>; - non-removable; - no-1-8-v; - fsl,wp-controller; - status = "okay"; -}; - -&iomuxc { - pinctrl_usdhc4: usdhc4grp { - fsl,pins = < - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x070b1 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x070b1 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x070b1 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x070b1 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x070b1 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x070b1 - MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x0b0b1 - >; - }; -}; diff --git a/sys/gnu/dts/arm/imx6dl-tx6u-80xx-mb7.dts b/sys/gnu/dts/arm/imx6dl-tx6u-80xx-mb7.dts deleted file mode 100644 index aef5fcc4290..00000000000 --- a/sys/gnu/dts/arm/imx6dl-tx6u-80xx-mb7.dts +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Copyright 2017 Lothar Waßmann - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6dl-tx6u-801x.dts" -#include "imx6qdl-tx6-mb7.dtsi" - -/ { - model = "Ka-Ro electronics TX6U-8030/-8010/-8012 Module on MB7 baseboard"; -}; diff --git a/sys/gnu/dts/arm/imx6dl-tx6u-811x.dts b/sys/gnu/dts/arm/imx6dl-tx6u-811x.dts deleted file mode 100644 index 5342f2f5a8a..00000000000 --- a/sys/gnu/dts/arm/imx6dl-tx6u-811x.dts +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Copyright 2014-2017 Lothar Waßmann - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-tx6.dtsi" -#include "imx6qdl-tx6-lvds.dtsi" - -/ { - model = "Ka-Ro electronics TX6U-811x Module"; - compatible = "karo,imx6dl-tx6dl", "fsl,imx6dl"; -}; diff --git a/sys/gnu/dts/arm/imx6dl-tx6u-81xx-mb7.dts b/sys/gnu/dts/arm/imx6dl-tx6u-81xx-mb7.dts deleted file mode 100644 index c4588fb0bf6..00000000000 --- a/sys/gnu/dts/arm/imx6dl-tx6u-81xx-mb7.dts +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Copyright 2016-2017 Lothar Waßmann - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6dl-tx6u-811x.dts" -#include "imx6qdl-tx6-mb7.dtsi" - -/ { - model = "Ka-Ro electronics TX6U-8130/-8110 Module on MB7 baseboard"; -}; diff --git a/sys/gnu/dts/arm/imx6dl-udoo.dts b/sys/gnu/dts/arm/imx6dl-udoo.dts deleted file mode 100644 index d871cac1711..00000000000 --- a/sys/gnu/dts/arm/imx6dl-udoo.dts +++ /dev/null @@ -1,14 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2013 Freescale Semiconductor, Inc. - * - * Author: Fabio Estevam - */ -/dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-udoo.dtsi" - -/ { - model = "Udoo i.MX6 Dual-lite Board"; - compatible = "udoo,imx6dl-udoo", "fsl,imx6dl"; -}; diff --git a/sys/gnu/dts/arm/imx6dl-wandboard-revb1.dts b/sys/gnu/dts/arm/imx6dl-wandboard-revb1.dts deleted file mode 100644 index c2946fbaa0d..00000000000 --- a/sys/gnu/dts/arm/imx6dl-wandboard-revb1.dts +++ /dev/null @@ -1,19 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2013 Freescale Semiconductor, Inc. - * - * Author: Fabio Estevam - */ -/dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-wandboard-revb1.dtsi" - -/ { - model = "Wandboard i.MX6 Dual Lite Board rev B1"; - compatible = "wand,imx6dl-wandboard", "fsl,imx6dl"; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x40000000>; - }; -}; diff --git a/sys/gnu/dts/arm/imx6dl-wandboard-revd1.dts b/sys/gnu/dts/arm/imx6dl-wandboard-revd1.dts deleted file mode 100644 index 6d1d863c2e3..00000000000 --- a/sys/gnu/dts/arm/imx6dl-wandboard-revd1.dts +++ /dev/null @@ -1,19 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2013 Freescale Semiconductor, Inc. - * - * Author: Fabio Estevam - */ -/dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-wandboard-revd1.dtsi" - -/ { - model = "Wandboard i.MX6 Dual Lite Board revD1"; - compatible = "wand,imx6dl-wandboard", "fsl,imx6dl"; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x40000000>; - }; -}; diff --git a/sys/gnu/dts/arm/imx6dl-wandboard.dts b/sys/gnu/dts/arm/imx6dl-wandboard.dts deleted file mode 100644 index 4a08d5a9945..00000000000 --- a/sys/gnu/dts/arm/imx6dl-wandboard.dts +++ /dev/null @@ -1,19 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2013 Freescale Semiconductor, Inc. - * - * Author: Fabio Estevam - */ -/dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-wandboard-revc1.dtsi" - -/ { - model = "Wandboard i.MX6 Dual Lite Board"; - compatible = "wand,imx6dl-wandboard", "fsl,imx6dl"; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x40000000>; - }; -}; diff --git a/sys/gnu/dts/arm/imx6dl-yapp4-common.dtsi b/sys/gnu/dts/arm/imx6dl-yapp4-common.dtsi deleted file mode 100644 index 80ed5f16a76..00000000000 --- a/sys/gnu/dts/arm/imx6dl-yapp4-common.dtsi +++ /dev/null @@ -1,621 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// -// Copyright (C) 2015-2018 Y Soft Corporation, a.s. - -#include -#include -#include -#include - -/ { - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 500000 PWM_POLARITY_INVERTED>; - brightness-levels = <0 32 64 128 255>; - default-brightness-level = <32>; - num-interpolated-steps = <8>; - power-supply = <&sw2_reg>; - status = "disabled"; - }; - - lcd_display: display { - compatible = "fsl,imx-parallel-display"; - #address-cells = <1>; - #size-cells = <0>; - interface-pix-fmt = "rgb24"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu1>; - status = "disabled"; - - port@0 { - reg = <0>; - - lcd_display_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - - port@1 { - reg = <1>; - - lcd_display_out: endpoint { - remote-endpoint = <&lcd_panel_in>; - }; - }; - }; - - panel: panel { - compatible = "dataimage,scf0700c48ggu18"; - power-supply = <&sw2_reg>; - status = "disabled"; - - port { - lcd_panel_in: endpoint { - remote-endpoint = <&lcd_display_out>; - }; - }; - }; - - reg_pcie: regulator-pcie { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie_reg>; - regulator-name = "MPCIE_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>; - enable-active-high; - status = "disabled"; - }; - - reg_usb_h1_vbus: regulator-usb-h1-vbus { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh1_vbus>; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>; - enable-active-high; - status = "disabled"; - }; - - reg_usb_otg_vbus: regulator-usb-otg-vbus { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg_vbus>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; - enable-active-high; - status = "okay"; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii-id"; - phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; - phy-reset-duration = <20>; - phy-supply = <&sw2_reg>; - phy-handle = <ðphy0>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - phy_port2: phy@1 { - reg = <1>; - }; - - phy_port3: phy@2 { - reg = <2>; - }; - - switch@10 { - compatible = "qca,qca8334"; - reg = <10>; - - switch_ports: ports { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: port@0 { - reg = <0>; - label = "cpu"; - phy-mode = "rgmii-id"; - ethernet = <&fec>; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - - port@2 { - reg = <2>; - label = "eth2"; - phy-handle = <&phy_port2>; - }; - - port@3 { - reg = <3>; - label = "eth1"; - phy-handle = <&phy_port3>; - }; - }; - }; - }; -}; - -&hdmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hdmi_cec>; - ddc-i2c-bus = <&i2c2>; - status = "disabled"; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - pmic@8 { - compatible = "fsl,pfuze200"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - reg = <0x8>; - - regulators { - sw1a_reg: sw1ab { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3a_reg: sw3a { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3b_reg: sw3b { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - }; - - vgen1_reg: vgen1 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen2_reg: vgen2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen3_reg: vgen3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen4_reg: vgen4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen5_reg: vgen5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen6_reg: vgen6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - vsnvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; - - leds: led-controller@30 { - compatible = "ti,lp5562"; - reg = <0x30>; - clock-mode = /bits/ 8 <1>; - status = "disabled"; - - chan0 { - chan-name = "R"; - led-cur = /bits/ 8 <0x20>; - max-cur = /bits/ 8 <0x60>; - }; - - chan1 { - chan-name = "G"; - led-cur = /bits/ 8 <0x20>; - max-cur = /bits/ 8 <0x60>; - }; - - chan2 { - chan-name = "B"; - led-cur = /bits/ 8 <0x20>; - max-cur = /bits/ 8 <0x60>; - }; - - chan3 { - chan-name = "W"; - led-cur = /bits/ 8 <0x0>; - max-cur = /bits/ 8 <0x0>; - }; - }; - - eeprom@57 { - compatible = "atmel,24c128"; - reg = <0x57>; - pagesize = <64>; - status = "okay"; - }; - - touchscreen: touchscreen@5c { - compatible = "pixcir,pixcir_tangoc"; - reg = <0x5c>; - pinctrl-0 = <&pinctrl_touch>; - interrupt-parent = <&gpio4>; - interrupts = <5 IRQ_TYPE_EDGE_FALLING>; - attb-gpio = <&gpio4 5 GPIO_ACTIVE_HIGH>; - reset-gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>; - touchscreen-size-x = <800>; - touchscreen-size-y = <480>; - status = "disabled"; - }; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - oled: oled@3d { - compatible = "solomon,ssd1305fb-i2c"; - reg = <0x3d>; - solomon,height = <64>; - solomon,width = <128>; - solomon,page-offset = <0>; - solomon,prechargep2 = <15>; - reset-gpios = <&gpio_oled 1 GPIO_ACTIVE_LOW>; - vbat-supply = <&sw2_reg>; - status = "disabled"; - }; - - gpio_oled: gpio@41 { - compatible = "nxp,pca9536"; - gpio-controller; - #gpio-cells = <2>; - reg = <0x41>; - vcc-supply = <&sw2_reg>; - status = "disabled"; - }; - - touchkeys: keys@5a { - compatible = "fsl,mpr121-touchkey"; - reg = <0x5a>; - vdd-supply = <&sw2_reg>; - autorepeat; - linux,keycodes = , , , , , - , , , , - , , ; - poll-interval = <50>; - status = "disabled"; - }; -}; - -&iomuxc { - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b020 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b020 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b020 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b020 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b020 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b020 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b020 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b020 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b020 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b020 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b020 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b020 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b020 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b020 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b010 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x1b010 - MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b098 - >; - }; - - pinctrl_hdmi_cec: hdmicecgrp { - fsl,pins = < - MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1b898 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b899 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b899 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b899 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b899 - >; - }; - - pinctrl_ipu1: ipu1grp { - fsl,pins = < - MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 - MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 - MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 - MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 - MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 - MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 - MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 - MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 - MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 - MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 - MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 - MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 - MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 - MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 - MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 - MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 - MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 - MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 - MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 - MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 - MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 - MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 - MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 - MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 - MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 - MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 - MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = < - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b098 - MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b098 - MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b098 - >; - }; - - pinctrl_pcie_reg: pciereggrp { - fsl,pins = < - MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b098 - >; - }; - - pinctrl_pmic: pmicgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b098 - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX6QDL_PAD_GPIO_9__PWM1_OUT 0x8 - >; - }; - - pinctrl_touch: touchgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b098 - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b098 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0a8 - MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0a8 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_GPIO_7__UART2_TX_DATA 0x1b098 - MX6QDL_PAD_GPIO_8__UART2_RX_DATA 0x1b098 - >; - }; - - pinctrl_usbh1: usbh1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D30__USB_H1_OC 0x1b098 - >; - }; - - pinctrl_usbh1_vbus: usbh1-vbus { - fsl,pins = < - MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x98 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x1b098 - MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b098 - >; - }; - - pinctrl_usbotg_vbus: usbotg-vbus { - fsl,pins = < - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x98 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b018 - MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x1b018 - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - >; - }; - - pinctrl_usdhc4: usdhc4grp { - fsl,pins = < - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x1f069 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10069 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17069 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17069 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17069 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17069 - MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17069 - MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17069 - MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17069 - MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17069 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__WDOG2_B 0x1b0b0 - >; - }; -}; - -&ipu1_di0_disp0 { - remote-endpoint = <&lcd_display_in>; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>; - vpcie-supply = <®_pcie>; - status = "disabled"; -}; - -&pwm1 { - #pwm-cells = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "disabled"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&usbh1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh1>; - vbus-supply = <®_usb_h1_vbus>; - status = "disabled"; -}; - -&usbotg { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - vbus-supply = <®_usb_otg_vbus>; - srp-disable; - hnp-disable; - adp-disable; - status = "okay"; -}; - -&usbphy1 { - fsl,tx-d-cal = <106>; - status = "okay"; -}; - -&usbphy2 { - fsl,tx-d-cal = <109>; - status = "disabled"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - bus-width = <4>; - cd-gpios = <&gpio7 8 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; - no-1-8-v; - keep-power-in-suspend; - wakeup-source; - vmmc-supply = <&sw2_reg>; - status = "disabled"; -}; - -&usdhc4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc4>; - bus-width = <8>; - non-removable; - no-1-8-v; - keep-power-in-suspend; - vmmc-supply = <&sw2_reg>; - status = "okay"; -}; - -&wdog1 { - status = "disabled"; -}; - -&wdog2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx6dl-yapp4-draco.dts b/sys/gnu/dts/arm/imx6dl-yapp4-draco.dts deleted file mode 100644 index a38c407fd83..00000000000 --- a/sys/gnu/dts/arm/imx6dl-yapp4-draco.dts +++ /dev/null @@ -1,58 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// -// Copyright (C) 2015-2018 Y Soft Corporation, a.s. - -/dts-v1/; - -#include "imx6dl.dtsi" -#include "imx6dl-yapp4-common.dtsi" - -/ { - model = "Y Soft IOTA Draco i.MX6Solo board"; - compatible = "ysoft,imx6dl-yapp4-draco", "fsl,imx6dl"; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x20000000>; - }; -}; - -&backlight { - status = "okay"; -}; - -&lcd_display { - status = "okay"; -}; - -&leds { - status = "okay"; -}; - -&panel { - status = "okay"; -}; - -&pwm1 { - status = "okay"; -}; - -®_usb_h1_vbus { - status = "okay"; -}; - -&touchscreen { - status = "okay"; -}; - -&usbh1 { - status = "okay"; -}; - -&usbphy2 { - status = "okay"; -}; - -&usdhc3 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx6dl-yapp4-hydra.dts b/sys/gnu/dts/arm/imx6dl-yapp4-hydra.dts deleted file mode 100644 index 6010d3d872a..00000000000 --- a/sys/gnu/dts/arm/imx6dl-yapp4-hydra.dts +++ /dev/null @@ -1,50 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// -// Copyright (C) 2015-2018 Y Soft Corporation, a.s. - -/dts-v1/; - -#include "imx6dl.dtsi" -#include "imx6dl-yapp4-common.dtsi" - -/ { - model = "Y Soft IOTA Hydra i.MX6DualLite board"; - compatible = "ysoft,imx6dl-yapp4-hydra", "fsl,imx6dl"; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x80000000>; - }; -}; - -&gpio_oled { - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&leds { - status = "okay"; -}; - -&oled { - status = "okay"; -}; - -&pcie { - status = "okay"; -}; - -®_pcie { - status = "okay"; -}; - -&touchkeys { - status = "okay"; -}; - -&usdhc3 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx6dl-yapp4-ursa.dts b/sys/gnu/dts/arm/imx6dl-yapp4-ursa.dts deleted file mode 100644 index 0d594e4bd55..00000000000 --- a/sys/gnu/dts/arm/imx6dl-yapp4-ursa.dts +++ /dev/null @@ -1,54 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// -// Copyright (C) 2015-2018 Y Soft Corporation, a.s. - -/dts-v1/; - -#include "imx6dl.dtsi" -#include "imx6dl-yapp4-common.dtsi" - -/ { - model = "Y Soft IOTA Ursa i.MX6Solo board"; - compatible = "ysoft,imx6dl-yapp4-ursa", "fsl,imx6dl"; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x20000000>; - }; -}; - -&backlight { - status = "okay"; -}; - -&lcd_display { - status = "okay"; -}; - -&panel { - status = "okay"; -}; - -&pwm1 { - status = "okay"; -}; - -®_usb_h1_vbus { - status = "okay"; -}; - -&switch_ports { - /delete-node/ port@2; -}; - -&touchscreen { - status = "okay"; -}; - -&usbh1 { - status = "okay"; -}; - -&usbphy2 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx6dl.dtsi b/sys/gnu/dts/arm/imx6dl.dtsi deleted file mode 100644 index 008312ee0c3..00000000000 --- a/sys/gnu/dts/arm/imx6dl.dtsi +++ /dev/null @@ -1,392 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// -// Copyright 2013 Freescale Semiconductor, Inc. - -#include -#include "imx6dl-pinfunc.h" -#include "imx6qdl.dtsi" - -/ { - aliases { - i2c3 = &i2c4; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - reg = <0>; - next-level-cache = <&L2>; - operating-points = < - /* kHz uV */ - 996000 1250000 - 792000 1175000 - 396000 1150000 - >; - fsl,soc-operating-points = < - /* ARM kHz SOC-PU uV */ - 996000 1175000 - 792000 1175000 - 396000 1175000 - >; - clock-latency = <61036>; /* two CLK32 periods */ - #cooling-cells = <2>; - clocks = <&clks IMX6QDL_CLK_ARM>, - <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, - <&clks IMX6QDL_CLK_STEP>, - <&clks IMX6QDL_CLK_PLL1_SW>, - <&clks IMX6QDL_CLK_PLL1_SYS>; - clock-names = "arm", "pll2_pfd2_396m", "step", - "pll1_sw", "pll1_sys"; - arm-supply = <®_arm>; - pu-supply = <®_pu>; - soc-supply = <®_soc>; - }; - - cpu@1 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - reg = <1>; - next-level-cache = <&L2>; - operating-points = < - /* kHz uV */ - 996000 1250000 - 792000 1175000 - 396000 1150000 - >; - fsl,soc-operating-points = < - /* ARM kHz SOC-PU uV */ - 996000 1175000 - 792000 1175000 - 396000 1175000 - >; - clock-latency = <61036>; /* two CLK32 periods */ - #cooling-cells = <2>; - clocks = <&clks IMX6QDL_CLK_ARM>, - <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, - <&clks IMX6QDL_CLK_STEP>, - <&clks IMX6QDL_CLK_PLL1_SW>, - <&clks IMX6QDL_CLK_PLL1_SYS>; - clock-names = "arm", "pll2_pfd2_396m", "step", - "pll1_sw", "pll1_sys"; - arm-supply = <®_arm>; - pu-supply = <®_pu>; - soc-supply = <®_soc>; - }; - }; - - soc { - ocram: sram@900000 { - compatible = "mmio-sram"; - reg = <0x00900000 0x20000>; - clocks = <&clks IMX6QDL_CLK_OCRAM>; - }; - - aips1: aips-bus@2000000 { - iomuxc: iomuxc@20e0000 { - compatible = "fsl,imx6dl-iomuxc"; - }; - - pxp: pxp@20f0000 { - reg = <0x020f0000 0x4000>; - interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; - }; - - epdc: epdc@20f4000 { - reg = <0x020f4000 0x4000>; - interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - - aips2: aips-bus@2100000 { - i2c4: i2c@21f8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; - reg = <0x021f8000 0x4000>; - interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6DL_CLK_I2C4>; - status = "disabled"; - }; - }; - }; - - capture-subsystem { - compatible = "fsl,imx-capture-subsystem"; - ports = <&ipu1_csi0>, <&ipu1_csi1>; - }; - - display-subsystem { - compatible = "fsl,imx-display-subsystem"; - ports = <&ipu1_di0>, <&ipu1_di1>; - }; -}; - -&gpio1 { - gpio-ranges = <&iomuxc 0 131 2>, <&iomuxc 2 137 8>, <&iomuxc 10 189 2>, - <&iomuxc 12 194 1>, <&iomuxc 13 193 1>, <&iomuxc 14 192 1>, - <&iomuxc 15 191 1>, <&iomuxc 16 185 2>, <&iomuxc 18 184 1>, - <&iomuxc 19 187 1>, <&iomuxc 20 183 1>, <&iomuxc 21 188 1>, - <&iomuxc 22 123 3>, <&iomuxc 25 121 1>, <&iomuxc 26 127 1>, - <&iomuxc 27 126 1>, <&iomuxc 28 128 1>, <&iomuxc 29 130 1>, - <&iomuxc 30 129 1>, <&iomuxc 31 122 1>; -}; - -&gpio2 { - gpio-ranges = <&iomuxc 0 161 8>, <&iomuxc 8 208 8>, <&iomuxc 16 74 1>, - <&iomuxc 17 73 1>, <&iomuxc 18 72 1>, <&iomuxc 19 71 1>, - <&iomuxc 20 70 1>, <&iomuxc 21 69 1>, <&iomuxc 22 68 1>, - <&iomuxc 23 79 2>, <&iomuxc 25 118 2>, <&iomuxc 27 117 1>, - <&iomuxc 28 113 4>; -}; - -&gpio3 { - gpio-ranges = <&iomuxc 0 97 2>, <&iomuxc 2 105 8>, <&iomuxc 10 99 6>, - <&iomuxc 16 81 16>; -}; - -&gpio4 { - gpio-ranges = <&iomuxc 5 136 1>, <&iomuxc 6 145 1>, <&iomuxc 7 150 1>, - <&iomuxc 8 146 1>, <&iomuxc 9 151 1>, <&iomuxc 10 147 1>, - <&iomuxc 11 152 1>, <&iomuxc 12 148 1>, <&iomuxc 13 153 1>, - <&iomuxc 14 149 1>, <&iomuxc 15 154 1>, <&iomuxc 16 39 7>, - <&iomuxc 23 56 1>, <&iomuxc 24 61 7>, <&iomuxc 31 46 1>; -}; - -&gpio5 { - gpio-ranges = <&iomuxc 0 120 1>, <&iomuxc 2 77 1>, <&iomuxc 4 76 1>, - <&iomuxc 5 47 9>, <&iomuxc 14 57 4>, <&iomuxc 18 37 1>, - <&iomuxc 19 36 1>, <&iomuxc 20 35 1>, <&iomuxc 21 38 1>, - <&iomuxc 22 29 6>, <&iomuxc 28 19 4>; -}; - -&gpio6 { - gpio-ranges = <&iomuxc 0 23 6>, <&iomuxc 6 75 1>, <&iomuxc 7 156 1>, - <&iomuxc 8 155 1>, <&iomuxc 9 170 1>, <&iomuxc 10 169 1>, - <&iomuxc 11 157 1>, <&iomuxc 14 158 3>, <&iomuxc 17 204 1>, - <&iomuxc 18 203 1>, <&iomuxc 19 182 1>, <&iomuxc 20 177 4>, - <&iomuxc 24 175 1>, <&iomuxc 25 171 1>, <&iomuxc 26 181 1>, - <&iomuxc 27 172 3>, <&iomuxc 30 176 1>, <&iomuxc 31 78 1>; -}; - -&gpio7 { - gpio-ranges = <&iomuxc 0 202 1>, <&iomuxc 1 201 1>, <&iomuxc 2 196 1>, - <&iomuxc 3 195 1>, <&iomuxc 4 197 4>, <&iomuxc 8 205 1>, - <&iomuxc 9 207 1>, <&iomuxc 10 206 1>, <&iomuxc 11 133 3>; -}; - -&gpr { - ipu1_csi0_mux { - compatible = "video-mux"; - mux-controls = <&mux 0>; - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - ipu1_csi0_mux_from_mipi_vc0: endpoint { - remote-endpoint = <&mipi_vc0_to_ipu1_csi0_mux>; - }; - }; - - port@1 { - reg = <1>; - - ipu1_csi0_mux_from_mipi_vc1: endpoint { - remote-endpoint = <&mipi_vc1_to_ipu1_csi0_mux>; - }; - }; - - port@2 { - reg = <2>; - - ipu1_csi0_mux_from_mipi_vc2: endpoint { - remote-endpoint = <&mipi_vc2_to_ipu1_csi0_mux>; - }; - }; - - port@3 { - reg = <3>; - - ipu1_csi0_mux_from_mipi_vc3: endpoint { - remote-endpoint = <&mipi_vc3_to_ipu1_csi0_mux>; - }; - }; - - port@4 { - reg = <4>; - - ipu1_csi0_mux_from_parallel_sensor: endpoint { - }; - }; - - port@5 { - reg = <5>; - - ipu1_csi0_mux_to_ipu1_csi0: endpoint { - remote-endpoint = <&ipu1_csi0_from_ipu1_csi0_mux>; - }; - }; - }; - - ipu1_csi1_mux { - compatible = "video-mux"; - mux-controls = <&mux 1>; - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - ipu1_csi1_mux_from_mipi_vc0: endpoint { - remote-endpoint = <&mipi_vc0_to_ipu1_csi1_mux>; - }; - }; - - port@1 { - reg = <1>; - - ipu1_csi1_mux_from_mipi_vc1: endpoint { - remote-endpoint = <&mipi_vc1_to_ipu1_csi1_mux>; - }; - }; - - port@2 { - reg = <2>; - - ipu1_csi1_mux_from_mipi_vc2: endpoint { - remote-endpoint = <&mipi_vc2_to_ipu1_csi1_mux>; - }; - }; - - port@3 { - reg = <3>; - - ipu1_csi1_mux_from_mipi_vc3: endpoint { - remote-endpoint = <&mipi_vc3_to_ipu1_csi1_mux>; - }; - }; - - port@4 { - reg = <4>; - - ipu1_csi1_mux_from_parallel_sensor: endpoint { - }; - }; - - port@5 { - reg = <5>; - - ipu1_csi1_mux_to_ipu1_csi1: endpoint { - remote-endpoint = <&ipu1_csi1_from_ipu1_csi1_mux>; - }; - }; - }; -}; - -&gpt { - compatible = "fsl,imx6dl-gpt"; -}; - -&hdmi { - compatible = "fsl,imx6dl-hdmi"; -}; - -&ipu1_csi1 { - ipu1_csi1_from_ipu1_csi1_mux: endpoint { - remote-endpoint = <&ipu1_csi1_mux_to_ipu1_csi1>; - }; -}; - -&ldb { - clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>, - <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>, - <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>; - clock-names = "di0_pll", "di1_pll", - "di0_sel", "di1_sel", - "di0", "di1"; -}; - -&mipi_csi { - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - mipi_vc0_to_ipu1_csi0_mux: endpoint@0 { - reg = <0>; - remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc0>; - }; - - mipi_vc0_to_ipu1_csi1_mux: endpoint@1 { - reg = <1>; - remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc0>; - }; - }; - - port@2 { - reg = <2>; - #address-cells = <1>; - #size-cells = <0>; - - mipi_vc1_to_ipu1_csi0_mux: endpoint@0 { - reg = <0>; - remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc1>; - }; - - mipi_vc1_to_ipu1_csi1_mux: endpoint@1 { - reg = <1>; - remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc1>; - }; - }; - - port@3 { - reg = <3>; - #address-cells = <1>; - #size-cells = <0>; - - mipi_vc2_to_ipu1_csi0_mux: endpoint@0 { - reg = <0>; - remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc2>; - }; - - mipi_vc2_to_ipu1_csi1_mux: endpoint@1 { - reg = <1>; - remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc2>; - }; - }; - - port@4 { - reg = <4>; - #address-cells = <1>; - #size-cells = <0>; - - mipi_vc3_to_ipu1_csi0_mux: endpoint@0 { - reg = <0>; - remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc3>; - }; - - mipi_vc3_to_ipu1_csi1_mux: endpoint@1 { - reg = <1>; - remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc3>; - }; - }; -}; - -&mux { - mux-reg-masks = <0x34 0x00000007>, /* IPU_CSI0_MUX */ - <0x34 0x00000038>, /* IPU_CSI1_MUX */ - <0x0c 0x0000000c>, /* HDMI_MUX_CTL */ - <0x0c 0x000000c0>, /* LVDS0_MUX_CTL */ - <0x0c 0x00000300>, /* LVDS1_MUX_CTL */ - <0x28 0x00000003>, /* DCIC1_MUX_CTL */ - <0x28 0x0000000c>; /* DCIC2_MUX_CTL */ -}; - -&vpu { - compatible = "fsl,imx6dl-vpu", "cnm,coda960"; -}; diff --git a/sys/gnu/dts/arm/imx6q-apalis-eval.dts b/sys/gnu/dts/arm/imx6q-apalis-eval.dts deleted file mode 100644 index 4665e15b196..00000000000 --- a/sys/gnu/dts/arm/imx6q-apalis-eval.dts +++ /dev/null @@ -1,309 +0,0 @@ -/* - * Copyright 2014-2017 Toradex AG - * Copyright 2012 Freescale Semiconductor, Inc. - * Copyright 2011 Linaro Ltd. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include -#include -#include -#include "imx6q.dtsi" -#include "imx6qdl-apalis.dtsi" - -/ { - model = "Toradex Apalis iMX6Q/D Module on Apalis Evaluation Board"; - compatible = "toradex,apalis_imx6q-eval", "toradex,apalis_imx6q", - "fsl,imx6q"; - - aliases { - i2c0 = &i2c1; - i2c1 = &i2c3; - i2c2 = &i2c2; - rtc0 = &rtc_i2c; - rtc1 = &snvs_rtc; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_keys>; - - wakeup { - label = "Wake-Up"; - gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <10>; - wakeup-source; - }; - }; - - lcd_display: disp0 { - compatible = "fsl,imx-parallel-display"; - #address-cells = <1>; - #size-cells = <0>; - interface-pix-fmt = "rgb24"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu1_lcdif>; - status = "okay"; - - port@0 { - reg = <0>; - - lcd_display_in: endpoint { - remote-endpoint = <&ipu1_di1_disp1>; - }; - }; - - port@1 { - reg = <1>; - - lcd_display_out: endpoint { - remote-endpoint = <&lcd_panel_in>; - }; - }; - }; - - panel: panel { - /* - * edt,et057090dhu: EDT 5.7" LCD TFT - * edt,et070080dh6: EDT 7.0" LCD TFT - */ - compatible = "edt,et057090dhu"; - backlight = <&backlight>; - power-supply = <®_3v3_sw>; - - port { - lcd_panel_in: endpoint { - remote-endpoint = <&lcd_display_out>; - }; - }; - }; - - reg_pcie_switch: regulator-pcie-switch { - compatible = "regulator-fixed"; - regulator-name = "pcie_switch"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>; - startup-delay-us = <100000>; - enable-active-high; - status = "okay"; - }; - - reg_3v3_sw: regulator-3v3-sw { - compatible = "regulator-fixed"; - regulator-name = "3.3V_SW"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; -}; - -&backlight { - brightness-levels = <0 127 191 223 239 247 251 255>; - default-brightness-level = <1>; - power-supply = <®_3v3_sw>; - status = "okay"; -}; - -&can1 { - xceiver-supply = <®_3v3_sw>; - status = "okay"; -}; - -&can2 { - xceiver-supply = <®_3v3_sw>; - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -/* I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier board) */ -&i2c1 { - status = "okay"; - - /* - * Touchscreen is using SODIMM 28/30, also used for PWM, PWM, - * aka pwm2, pwm3. so if you enable touchscreen, disable the pwms - */ - touchscreen@4a { - compatible = "atmel,maxtouch"; - reg = <0x4a>; - interrupt-parent = <&gpio6>; - interrupts = <10 IRQ_TYPE_EDGE_FALLING>; - reset-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; /* SODIMM 13 */ - status = "disabled"; - }; - - pcie-switch@58 { - compatible = "plx,pex8605"; - reg = <0x58>; - }; - - /* M41T0M6 real time clock on carrier board */ - rtc_i2c: rtc@68 { - compatible = "st,m41t0"; - reg = <0x68>; - }; -}; - -/* - * I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor on carrier - * board) - */ -&i2c3 { - status = "okay"; -}; - -&ipu1_di1_disp1 { - remote-endpoint = <&lcd_display_in>; -}; - -&ldb { - status = "okay"; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reset_moci>; - /* active-high meaning opposite of regular PERST# active-low polarity */ - reset-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>; - reset-gpio-active-high; - vpcie-supply = <®_pcie_switch>; - status = "okay"; -}; - -&pwm1 { - status = "okay"; -}; - -&pwm2 { - status = "okay"; -}; - -&pwm3 { - status = "okay"; -}; - -&pwm4 { - status = "okay"; -}; - -®_usb_otg_vbus { - status = "okay"; -}; - -®_usb_host_vbus { - status = "okay"; -}; - -&sata { - status = "okay"; -}; - -&sound_spdif { - status = "okay"; -}; - -&spdif { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart4 { - status = "okay"; -}; - -&uart5 { - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usb_host_vbus>; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - status = "okay"; -}; - -/* MMC1 */ -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1_4bit &pinctrl_usdhc1_8bit &pinctrl_mmc_cd>; - cd-gpios = <&gpio4 20 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -/* SD1 */ -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2 &pinctrl_sd_cd>; - cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&iomuxc { - /* - * Mux the Apalis GPIOs - */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_apalis_gpio1 &pinctrl_apalis_gpio2 - &pinctrl_apalis_gpio3 &pinctrl_apalis_gpio4 - &pinctrl_apalis_gpio5 &pinctrl_apalis_gpio6 - &pinctrl_apalis_gpio7 &pinctrl_apalis_gpio8 - >; -}; diff --git a/sys/gnu/dts/arm/imx6q-apalis-ixora-v1.1.dts b/sys/gnu/dts/arm/imx6q-apalis-ixora-v1.1.dts deleted file mode 100644 index a3fa04a97d8..00000000000 --- a/sys/gnu/dts/arm/imx6q-apalis-ixora-v1.1.dts +++ /dev/null @@ -1,310 +0,0 @@ -/* - * Copyright 2014-2017 Toradex AG - * Copyright 2012 Freescale Semiconductor, Inc. - * Copyright 2011 Linaro Ltd. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include -#include -#include -#include "imx6q.dtsi" -#include "imx6qdl-apalis.dtsi" - -/ { - model = "Toradex Apalis iMX6Q/D Module on Ixora Carrier Board V1.1"; - compatible = "toradex,apalis_imx6q-ixora-v1.1", - "toradex,apalis_imx6q-ixora", "toradex,apalis_imx6q", - "fsl,imx6q"; - - aliases { - i2c0 = &i2c1; - i2c1 = &i2c3; - i2c2 = &i2c2; - rtc0 = &rtc_i2c; - rtc1 = &snvs_rtc; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_keys>; - - wakeup { - label = "Wake-Up"; - gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <10>; - wakeup-source; - }; - }; - - lcd_display: disp0 { - compatible = "fsl,imx-parallel-display"; - #address-cells = <1>; - #size-cells = <0>; - interface-pix-fmt = "rgb24"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu1_lcdif>; - status = "okay"; - - port@0 { - reg = <0>; - - lcd_display_in: endpoint { - remote-endpoint = <&ipu1_di1_disp1>; - }; - }; - - port@1 { - reg = <1>; - - lcd_display_out: endpoint { - remote-endpoint = <&lcd_panel_in>; - }; - }; - }; - - panel: panel { - /* - * edt,et057090dhu: EDT 5.7" LCD TFT - * edt,et070080dh6: EDT 7.0" LCD TFT - */ - compatible = "edt,et057090dhu"; - backlight = <&backlight>; - - port { - lcd_panel_in: endpoint { - remote-endpoint = <&lcd_display_out>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_leds_ixora>; - - led4-green { - label = "LED_4_GREEN"; - gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; - }; - - led4-red { - label = "LED_4_RED"; - gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; - }; - - led5-green { - label = "LED_5_GREEN"; - gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; - }; - - led5-red { - label = "LED_5_RED"; - gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&backlight { - brightness-levels = <0 127 191 223 239 247 251 255>; - default-brightness-level = <1>; - status = "okay"; -}; - -&can1 { - status = "okay"; -}; - -&can2 { - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -/* I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier board) */ -&i2c1 { - status = "okay"; - - /* - * Touchscreen is using SODIMM 28/30, also used for PWM, PWM, - * aka pwm2, pwm3. so if you enable touchscreen, disable the pwms - */ - touchscreen@4a { - compatible = "atmel,maxtouch"; - reg = <0x4a>; - interrupt-parent = <&gpio6>; - interrupts = <10 IRQ_TYPE_EDGE_FALLING>; - reset-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; /* SODIMM 13 */ - status = "disabled"; - }; - - /* M41T0M6 real time clock on carrier board */ - rtc_i2c: rtc@68 { - compatible = "st,m41t0"; - reg = <0x68>; - }; -}; - -/* - * I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor on carrier - * board) - */ -&i2c3 { - status = "okay"; -}; - -&ipu1_di1_disp1 { - remote-endpoint = <&lcd_display_in>; -}; - -&ldb { - status = "okay"; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reset_moci>; - /* active-high meaning opposite of regular PERST# active-low polarity */ - reset-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>; - reset-gpio-active-high; - status = "okay"; -}; - -&pwm1 { - status = "okay"; -}; - -&pwm2 { - status = "okay"; -}; - -&pwm3 { - status = "okay"; -}; - -&pwm4 { - status = "okay"; -}; - -®_usb_otg_vbus { - status = "okay"; -}; - -®_usb_host_vbus { - status = "okay"; -}; - -&sata { - status = "okay"; -}; - -&sound_spdif { - status = "okay"; -}; - -&spdif { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart4 { - status = "okay"; -}; - -&uart5 { - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usb_host_vbus>; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - status = "okay"; -}; - -/* MMC1 */ -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1_4bit &pinctrl_mmc_cd>; - cd-gpios = <&gpio4 20 GPIO_ACTIVE_LOW>; - bus-width = <4>; - status = "okay"; -}; - -&iomuxc { - /* - * Mux the Apalis GPIOs - */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_apalis_gpio1 &pinctrl_apalis_gpio2 - &pinctrl_apalis_gpio3 &pinctrl_apalis_gpio4 - &pinctrl_apalis_gpio5 &pinctrl_apalis_gpio6 - &pinctrl_apalis_gpio7 &pinctrl_apalis_gpio8 - >; - - pinctrl_leds_ixora: ledsixoragrp { - fsl,pins = < - MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x1b0b0 - MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x1b0b0 - MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 - MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 - >; - }; -}; diff --git a/sys/gnu/dts/arm/imx6q-apalis-ixora.dts b/sys/gnu/dts/arm/imx6q-apalis-ixora.dts deleted file mode 100644 index 5ba49d0f488..00000000000 --- a/sys/gnu/dts/arm/imx6q-apalis-ixora.dts +++ /dev/null @@ -1,311 +0,0 @@ -/* - * Copyright 2014-2017 Toradex AG - * Copyright 2012 Freescale Semiconductor, Inc. - * Copyright 2011 Linaro Ltd. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include -#include -#include -#include "imx6q.dtsi" -#include "imx6qdl-apalis.dtsi" - -/ { - model = "Toradex Apalis iMX6Q/D Module on Ixora Carrier Board"; - compatible = "toradex,apalis_imx6q-ixora", "toradex,apalis_imx6q", - "fsl,imx6q"; - - aliases { - i2c0 = &i2c1; - i2c1 = &i2c3; - i2c2 = &i2c2; - rtc0 = &rtc_i2c; - rtc1 = &snvs_rtc; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_keys>; - - wakeup { - label = "Wake-Up"; - gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <10>; - wakeup-source; - }; - }; - - lcd_display: disp0 { - compatible = "fsl,imx-parallel-display"; - #address-cells = <1>; - #size-cells = <0>; - interface-pix-fmt = "rgb24"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu1_lcdif>; - status = "okay"; - - port@0 { - reg = <0>; - - lcd_display_in: endpoint { - remote-endpoint = <&ipu1_di1_disp1>; - }; - }; - - port@1 { - reg = <1>; - - lcd_display_out: endpoint { - remote-endpoint = <&lcd_panel_in>; - }; - }; - }; - - panel: panel { - /* - * edt,et057090dhu: EDT 5.7" LCD TFT - * edt,et070080dh6: EDT 7.0" LCD TFT - */ - compatible = "edt,et057090dhu"; - backlight = <&backlight>; - - port { - lcd_panel_in: endpoint { - remote-endpoint = <&lcd_display_out>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_leds_ixora>; - - led4-green { - label = "LED_4_GREEN"; - gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; - }; - - led4-red { - label = "LED_4_RED"; - gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; - }; - - led5-green { - label = "LED_5_GREEN"; - gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; - }; - - led5-red { - label = "LED_5_RED"; - gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&backlight { - brightness-levels = <0 127 191 223 239 247 251 255>; - default-brightness-level = <1>; - status = "okay"; -}; - -&can1 { - status = "okay"; -}; - -&can2 { - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -/* I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier board) */ -&i2c1 { - status = "okay"; - - /* - * Touchscreen is using SODIMM 28/30, also used for PWM, PWM, - * aka pwm2, pwm3. so if you enable touchscreen, disable the pwms - */ - touchscreen@4a { - compatible = "atmel,maxtouch"; - reg = <0x4a>; - interrupt-parent = <&gpio6>; - interrupts = <10 IRQ_TYPE_EDGE_FALLING>; - reset-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; /* SODIMM 13 */ - status = "disabled"; - }; - - eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - }; - - /* M41T0M6 real time clock on carrier board */ - rtc_i2c: rtc@68 { - compatible = "st,m41t0"; - reg = <0x68>; - }; -}; - -/* - * I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor on carrier - * board) - */ -&i2c3 { - status = "okay"; -}; - -&ipu1_di1_disp1 { - remote-endpoint = <&lcd_display_in>; -}; - -&ldb { - status = "okay"; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reset_moci>; - /* active-high meaning opposite of regular PERST# active-low polarity */ - reset-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>; - reset-gpio-active-high; - status = "okay"; -}; - -&pwm1 { - status = "okay"; -}; - -&pwm2 { - status = "okay"; -}; - -&pwm3 { - status = "okay"; -}; - -&pwm4 { - status = "okay"; -}; - -®_usb_otg_vbus { - status = "okay"; -}; - -®_usb_host_vbus { - status = "okay"; -}; - -&sata { - status = "okay"; -}; - -&sound_spdif { - status = "okay"; -}; - -&spdif { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart4 { - status = "okay"; -}; - -&uart5 { - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usb_host_vbus>; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - status = "okay"; -}; - -/* SD1 */ -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2 &pinctrl_sd_cd>; - cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&iomuxc { - /* Mux the Apalis GPIOs */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_apalis_gpio1 &pinctrl_apalis_gpio2 - &pinctrl_apalis_gpio3 &pinctrl_apalis_gpio4 - &pinctrl_apalis_gpio5 &pinctrl_apalis_gpio6 - &pinctrl_apalis_gpio7 &pinctrl_apalis_gpio8 - >; - - pinctrl_leds_ixora: ledsixoragrp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b0b0 - MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x1b0b0 - MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 - MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 - >; - }; -}; diff --git a/sys/gnu/dts/arm/imx6q-apf6dev.dts b/sys/gnu/dts/arm/imx6q-apf6dev.dts deleted file mode 100644 index 664b0af8f0b..00000000000 --- a/sys/gnu/dts/arm/imx6q-apf6dev.dts +++ /dev/null @@ -1,22 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -// -// Copyright 2015 Armadeus Systems - -/dts-v1/; -#include "imx6q.dtsi" -#include "imx6qdl-apf6.dtsi" -#include "imx6qdl-apf6dev.dtsi" - -/ { - model = "Armadeus APF6 Quad / Dual Module on APF6Dev Board"; - compatible = "armadeus,imx6q-apf6dev", "armadeus,imx6q-apf6", "fsl,imx6q"; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x40000000>; - }; -}; - -&sata { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx6q-arm2.dts b/sys/gnu/dts/arm/imx6q-arm2.dts deleted file mode 100644 index 0b40f52268b..00000000000 --- a/sys/gnu/dts/arm/imx6q-arm2.dts +++ /dev/null @@ -1,225 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2011 Freescale Semiconductor, Inc. - * Copyright 2011 Linaro Ltd. - */ - -/dts-v1/; -#include -#include "imx6q.dtsi" - -/ { - model = "Freescale i.MX6 Quad Armadillo2 Board"; - compatible = "fsl,imx6q-arm2", "fsl,imx6q"; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x80000000>; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_3p3v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_usb_otg_vbus: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 0>; - enable-active-high; - }; - }; - - leds { - compatible = "gpio-leds"; - - debug-led { - label = "Heartbeat"; - gpios = <&gpio3 25 0>; - linux,default-trigger = "heartbeat"; - }; - }; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - status = "disabled"; /* gpmi nand conflicts with SD */ -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - imx6q-arm2 { - pinctrl_hog: hoggrp { - fsl,pins = < - MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x80000000 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 - >; - }; - - pinctrl_gpmi_nand: gpminandgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 - MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x1b0b1 - MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 - >; - }; - - pinctrl_usdhc3_cdwp: usdhc3cdwp { - fsl,pins = < - MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x80000000 - MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x80000000 - >; - }; - - pinctrl_usdhc4: usdhc4grp { - fsl,pins = < - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 - MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 - MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 - MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 - MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 - >; - }; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii"; - interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, - <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; - fsl,err006687-workaround-present; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "okay"; -}; - -&usdhc3 { - cd-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio6 14 GPIO_ACTIVE_HIGH>; - vmmc-supply = <®_3p3v>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3 - &pinctrl_usdhc3_cdwp>; - status = "okay"; -}; - -&usdhc4 { - non-removable; - vmmc-supply = <®_3p3v>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc4>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - fsl,dte-mode; - uart-has-rtscts; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx6q-b450v3.dts b/sys/gnu/dts/arm/imx6q-b450v3.dts deleted file mode 100644 index 95b8f2d7182..00000000000 --- a/sys/gnu/dts/arm/imx6q-b450v3.dts +++ /dev/null @@ -1,159 +0,0 @@ -/* - * Copyright 2015 Timesys Corporation. - * Copyright 2015 General Electric Company - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include "imx6q-bx50v3.dtsi" - -/ { - model = "General Electric B450v3"; - compatible = "ge,imx6q-b450v3", "advantech,imx6q-ba16", "fsl,imx6q"; - - chosen { - stdout-path = &uart3; - }; - - panel-lvds0 { - compatible = "innolux,g121x1-l03"; - backlight = <&backlight_lvds>; - power-supply = <®_lvds>; - - port { - panel_in_lvds0: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - }; -}; - -&clks { - assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, - <&clks IMX6QDL_CLK_LDB_DI1_SEL>; - assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, - <&clks IMX6QDL_CLK_PLL3_USB_OTG>; -}; - -&ldb { - status = "okay"; - - lvds0: lvds-channel@0 { - fsl,data-mapping = "spwg"; - fsl,data-width = <24>; - status = "okay"; - - port@4 { - reg = <4>; - - lvds0_out: endpoint { - remote-endpoint = <&panel_in_lvds0>; - }; - }; - }; -}; - -&pca9539 { - P04 { - gpio-hog; - gpios = <4 0>; - output-low; - line-name = "PCA9539-P04"; - }; - - P07 { - gpio-hog; - gpios = <7 0>; - output-low; - line-name = "PCA9539-P07"; - }; -}; - -&pci_root { - /* Intel Corporation I210 Gigabit Network Connection */ - switch_nic: ethernet@3,0 { - compatible = "pci8086,1533"; - reg = <0x00010000 0 0 0 0>; - }; -}; - -&switch_ports { - port@0 { - reg = <0>; - label = "enacq"; - phy-handle = <&switchphy0>; - }; - - port@1 { - reg = <1>; - label = "eneport1"; - phy-handle = <&switchphy1>; - }; - - port@2 { - reg = <2>; - label = "enix"; - phy-handle = <&switchphy2>; - }; - - port@3 { - reg = <3>; - label = "enid"; - phy-handle = <&switchphy3>; - }; - - port@4 { - reg = <4>; - label = "cpu"; - ethernet = <&switch_nic>; - phy-handle = <&switchphy4>; - }; - - port@5 { - reg = <5>; - label = "enembc"; - - /* connected to Ethernet MAC of AT91RM9200 in MII mode */ - fixed-link { - speed = <100>; - full-duplex; - }; - }; -}; diff --git a/sys/gnu/dts/arm/imx6q-b650v3.dts b/sys/gnu/dts/arm/imx6q-b650v3.dts deleted file mode 100644 index 611cb7ae7e5..00000000000 --- a/sys/gnu/dts/arm/imx6q-b650v3.dts +++ /dev/null @@ -1,158 +0,0 @@ -/* - * Copyright 2015 Timesys Corporation. - * Copyright 2015 General Electric Company - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include "imx6q-bx50v3.dtsi" - -/ { - model = "General Electric B650v3"; - compatible = "ge,imx6q-b650v3", "advantech,imx6q-ba16", "fsl,imx6q"; - - chosen { - stdout-path = &uart3; - }; - - panel-lvds0 { - compatible = "innolux,g121x1-l03"; - backlight = <&backlight_lvds>; - power-supply = <®_lvds>; - - port { - panel_in_lvds0: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - }; -}; - -&clks { - assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, - <&clks IMX6QDL_CLK_LDB_DI1_SEL>; - assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, - <&clks IMX6QDL_CLK_PLL3_USB_OTG>; -}; - -&ldb { - status = "okay"; - - lvds0: lvds-channel@0 { - fsl,data-mapping = "spwg"; - fsl,data-width = <24>; - status = "okay"; - - port@4 { - reg = <4>; - - lvds0_out: endpoint { - remote-endpoint = <&panel_in_lvds0>; - }; - }; - }; -}; - -&pca9539 { - P07 { - gpio-hog; - gpios = <7 0>; - output-low; - line-name = "PCA9539-P07"; - }; -}; - -&usbphy1 { - fsl,tx-cal-45-dn-ohms = <55>; - fsl,tx-cal-45-dp-ohms = <55>; - fsl,tx-d-cal = <100>; -}; - -&pci_root { - /* Intel Corporation I210 Gigabit Network Connection */ - switch_nic: ethernet@3,0 { - compatible = "pci8086,1533"; - reg = <0x00010000 0 0 0 0>; - }; -}; - -&switch_ports { - port@0 { - reg = <0>; - label = "enacq"; - phy-handle = <&switchphy0>; - }; - - port@1 { - reg = <1>; - label = "eneport1"; - phy-handle = <&switchphy1>; - }; - - port@2 { - reg = <2>; - label = "enix"; - phy-handle = <&switchphy2>; - }; - - port@3 { - reg = <3>; - label = "enid"; - phy-handle = <&switchphy3>; - }; - - port@4 { - reg = <4>; - label = "cpu"; - ethernet = <&switch_nic>; - phy-handle = <&switchphy4>; - }; - - port@5 { - reg = <5>; - label = "enembc"; - - /* connected to Ethernet MAC of AT91RM9200 in MII mode */ - fixed-link { - speed = <100>; - full-duplex; - }; - }; -}; diff --git a/sys/gnu/dts/arm/imx6q-b850v3.dts b/sys/gnu/dts/arm/imx6q-b850v3.dts deleted file mode 100644 index e4cb118f88c..00000000000 --- a/sys/gnu/dts/arm/imx6q-b850v3.dts +++ /dev/null @@ -1,301 +0,0 @@ -/* - * Copyright 2015 Timesys Corporation. - * Copyright 2015 General Electric Company - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include "imx6q-bx50v3.dtsi" - -/ { - model = "General Electric B850v3"; - compatible = "ge,imx6q-b850v3", "advantech,imx6q-ba16", "fsl,imx6q"; - - chosen { - stdout-path = &uart3; - }; -}; - -&clks { - assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, - <&clks IMX6QDL_CLK_LDB_DI1_SEL>, - <&clks IMX6QDL_CLK_IPU1_DI0_PRE_SEL>, - <&clks IMX6QDL_CLK_IPU2_DI0_PRE_SEL>; - assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>, - <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>, - <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, - <&clks IMX6QDL_CLK_PLL2_PFD2_396M>; -}; - -&ldb { - fsl,dual-channel; - status = "okay"; - - lvds0: lvds-channel@0 { - fsl,data-mapping = "spwg"; - fsl,data-width = <24>; - status = "okay"; - - port@4 { - reg = <4>; - - lvds0_out: endpoint { - remote-endpoint = <&stdp4028_in>; - }; - }; - }; -}; - -&i2c2 { - pca9547_ddc: mux@70 { - compatible = "nxp,pca9547"; - reg = <0x70>; - #address-cells = <1>; - #size-cells = <0>; - - mux2_i2c1: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0>; - }; - - mux2_i2c2: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x1>; - }; - - mux2_i2c3: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x2>; - }; - - mux2_i2c4: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x3>; - }; - - mux2_i2c5: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x4>; - }; - - mux2_i2c6: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x5>; - }; - - mux2_i2c7: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x6>; - }; - - mux2_i2c8: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x7>; - }; - }; -}; - -&hdmi { - ddc-i2c-bus = <&mux2_i2c1>; -}; - -&mux1_i2c1 { - ads7830@4a { - compatible = "ti,ads7830"; - reg = <0x4a>; - }; -}; - -&mux2_i2c2 { - clock-frequency = <100000>; - - stdp2690@72 { - compatible = "megachips,stdp2690-ge-b850v3-fw"; - reg = <0x72>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - stdp2690_in: endpoint { - remote-endpoint = <&stdp4028_out>; - }; - }; - - port@1 { - reg = <1>; - - stdp2690_out: endpoint { - /* Connector for external display */ - }; - }; - }; - }; - - stdp4028@73 { - compatible = "megachips,stdp4028-ge-b850v3-fw"; - reg = <0x73>; - interrupt-parent = <&gpio2>; - interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - stdp4028_in: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - - port@1 { - reg = <1>; - - stdp4028_out: endpoint { - remote-endpoint = <&stdp2690_in>; - }; - }; - }; - }; -}; - -&pca9539 { - P10 { - gpio-hog; - gpios = <8 0>; - output-low; - line-name = "PCA9539-P10"; - }; - - P11 { - gpio-hog; - gpios = <9 0>; - output-low; - line-name = "PCA9539-P11"; - }; -}; - -&pci_root { - /* PLX Technology, Inc. PEX 8605 PCI Express 4-port Gen2 Switch */ - bridge@1,0 { - compatible = "pci10b5,8605"; - reg = <0x00010000 0 0 0 0>; - - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - - bridge@2,1 { - compatible = "pci10b5,8605"; - reg = <0x00020800 0 0 0 0>; - - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - - /* Intel Corporation I210 Gigabit Network Connection */ - ethernet@3,0 { - compatible = "pci8086,1533"; - reg = <0x00030000 0 0 0 0>; - }; - }; - - bridge@2,2 { - compatible = "pci10b5,8605"; - reg = <0x00021000 0 0 0 0>; - - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - - /* Intel Corporation I210 Gigabit Network Connection */ - switch_nic: ethernet@4,0 { - compatible = "pci8086,1533"; - reg = <0x00040000 0 0 0 0>; - }; - }; - }; -}; - -&switch_ports { - port@0 { - reg = <0>; - label = "eneport1"; - phy-handle = <&switchphy0>; - }; - - port@1 { - reg = <1>; - label = "eneport2"; - phy-handle = <&switchphy1>; - }; - - port@2 { - reg = <2>; - label = "enix"; - phy-handle = <&switchphy2>; - }; - - port@3 { - reg = <3>; - label = "enid"; - phy-handle = <&switchphy3>; - }; - - port@4 { - reg = <4>; - label = "cpu"; - ethernet = <&switch_nic>; - phy-handle = <&switchphy4>; - }; -}; diff --git a/sys/gnu/dts/arm/imx6q-ba16.dtsi b/sys/gnu/dts/arm/imx6q-ba16.dtsi deleted file mode 100644 index 37c63402157..00000000000 --- a/sys/gnu/dts/arm/imx6q-ba16.dtsi +++ /dev/null @@ -1,639 +0,0 @@ -/* - * Support for imx6 based Advantech DMS-BA16 Qseven module - * - * Copyright 2015 Timesys Corporation. - * Copyright 2015 General Electric Company - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "imx6q.dtsi" -#include - -/ { - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x40000000>; - }; - - backlight_lvds: backlight { - compatible = "pwm-backlight"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_display>; - pwms = <&pwm1 0 5000000>; - brightness-levels = < 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100 101 102 103 104 105 106 107 108 109 - 110 111 112 113 114 115 116 117 118 119 - 120 121 122 123 124 125 126 127 128 129 - 130 131 132 133 134 135 136 137 138 139 - 140 141 142 143 144 145 146 147 148 149 - 150 151 152 153 154 155 156 157 158 159 - 160 161 162 163 164 165 166 167 168 169 - 170 171 172 173 174 175 176 177 178 179 - 180 181 182 183 184 185 186 187 188 189 - 190 191 192 193 194 195 196 197 198 199 - 200 201 202 203 204 205 206 207 208 209 - 210 211 212 213 214 215 216 217 218 219 - 220 221 222 223 224 225 226 227 228 229 - 230 231 232 233 234 235 236 237 238 239 - 240 241 242 243 244 245 246 247 248 249 - 250 251 252 253 254 255>; - default-brightness-level = <255>; - enable-gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; - }; - - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-name = "1P8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_lvds: regulator-lvds { - compatible = "regulator-fixed"; - regulator-name = "lvds_ppen"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usb_h1_vbus: regulator-usbh1vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_usb_otg_vbus: regulator-usbotgvbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; - -&ecspi1 { - cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - status = "okay"; - - flash: n25q032@0 { - compatible = "jedec,spi-nor"; - #address-cells = <1>; - #size-cells = <1>; - spi-max-frequency = <20000000>; - reg = <0>; - - partition@0 { - label = "U-Boot"; - reg = <0x0 0xc0000>; - }; - - partition@c0000 { - label = "env"; - reg = <0xc0000 0x10000>; - }; - - partition@d0000 { - label = "spare"; - reg = <0xd0000 0x320000>; - }; - - partition@3f0000 { - label = "mfg"; - reg = <0x3f0000 0x10000>; - }; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii-id"; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c2>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - pmic@58 { - compatible = "dlg,da9063"; - reg = <0x58>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - interrupt-parent = <&gpio7>; - interrupts = <13 IRQ_TYPE_LEVEL_LOW>; - - onkey { - compatible = "dlg,da9063-onkey"; - }; - - regulators { - vdd_bcore1: bcore1 { - regulator-min-microvolt = <1420000>; - regulator-max-microvolt = <1420000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_bcore2: bcore2 { - regulator-min-microvolt = <1420000>; - regulator-max-microvolt = <1420000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_bpro: bpro { - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_bmem: bmem { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_bio: bio { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_bperi: bperi { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_ldo1: ldo1 { - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1860000>; - }; - - vdd_ldo2: ldo2 { - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1860000>; - }; - - vdd_ldo3: ldo3 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <3440000>; - }; - - vdd_ldo4: ldo4 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <3440000>; - }; - - vdd_ldo5: ldo5 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <3600000>; - }; - - vdd_ldo6: ldo6 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <3600000>; - }; - - vdd_ldo7: ldo7 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <3600000>; - }; - - vdd_ldo8: ldo8 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <3600000>; - }; - - vdd_ldo9: ldo9 { - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <3600000>; - }; - - vdd_ldo10: ldo10 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <3600000>; - }; - - vdd_ldo11: ldo11 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <3600000>; - regulator-always-on; - regulator-boot-on; - }; - }; - }; - - rtc@32 { - compatible = "epson,rx8010"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rtc>; - reg = <0x32>; - interrupt-parent = <&gpio4>; - interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; - }; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>; - fsl,tx-swing-full = <103>; - fsl,tx-swing-low = <103>; - status = "okay"; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "okay"; -}; - -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm2>; - status = "disabled"; -}; - -&sata { - status = "okay"; -}; - -&ssi1 { - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - uart-has-rtscts; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -&usbh1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbhub>; - vbus-supply = <®_usb_h1_vbus>; - reset-gpios = <&gpio7 11 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - no-1-8-v; - keep-power-in-suspend; - wakeup-source; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3 &pinctrl_usdhc3_reset>; - bus-width = <8>; - vmmc-supply = <&vdd_bperi>; - non-removable; - keep-power-in-suspend; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0 - MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x130b0 - MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0 - MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0 - >; - }; - - pinctrl_display: dispgrp { - fsl,pins = < - /* BLEN_OUT */ - MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 - /* LVDS_PPEN_OUT */ - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 - /* SPI1 CS */ - MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 - >; - }; - - pinctrl_ecspi5: ecspi5grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT0__ECSPI5_MISO 0x1b0b0 - MX6QDL_PAD_SD1_CMD__ECSPI5_MOSI 0x1b0b0 - MX6QDL_PAD_SD1_CLK__ECSPI5_SCLK 0x1b0b0 - MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b0b0 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - /* FEC Reset */ - MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 - /* AR8033 Interrupt */ - MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 - >; - }; - - pinctrl_hog: hoggrp { - fsl,pins = < - /* GPIO 0-7 */ - MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0 - MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 - MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 - MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 - MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 - MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x1b0b0 - MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0 - MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x1b0b0 - /* SUS_S3_OUT to CPLD */ - MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 - MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = < - /* PCIe Reset */ - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 - /* PCIe Wake */ - MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0 - >; - }; - - pinctrl_pmic: pmicgrp { - fsl,pins = < - /* PMIC Interrupt */ - MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1 - >; - }; - - pinctrl_rtc: rtcgrp { - fsl,pins = < - /* RTC_INT */ - MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 - MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbhub: usbhubgrp { - fsl,pins = < - /* HUB_RESET */ - MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x1b0b0 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 - /* uSDHC2 CD */ - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 - >; - }; - - pinctrl_usdhc3_reset: usdhc3grp-reset { - fsl,pins = < - MX6QDL_PAD_SD3_RST__SD3_RESET 0x170F9 - >; - }; - - pinctrl_usdhc4: usdhc4grp { - fsl,pins = < - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x17059 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 - MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 - MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 - MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 - MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 - /* uSDHC4 CD */ - MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x1b0b0 - /* uSDHC4 SDIO PWR */ - MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0 - /* uSDHC4 SDIO WP */ - MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 - /* uSDHC4 SDIO LED */ - MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x1b0b0 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_9__WDOG1_B 0x1b0b0 - >; - }; -}; diff --git a/sys/gnu/dts/arm/imx6q-bx50v3.dtsi b/sys/gnu/dts/arm/imx6q-bx50v3.dtsi deleted file mode 100644 index fa27dcdf06f..00000000000 --- a/sys/gnu/dts/arm/imx6q-bx50v3.dtsi +++ /dev/null @@ -1,379 +0,0 @@ -/* - * Copyright 2015 Timesys Corporation. - * Copyright 2015 General Electric Company - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "imx6q-ba16.dtsi" - -/ { - mclk: clock-mclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <22000000>; - }; - - gpio-poweroff { - compatible = "gpio-poweroff"; - gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; - status = "okay"; - }; - - reg_wl18xx_vmmc: regulator-wl18xx { - compatible = "regulator-fixed"; - regulator-name = "vwl1807"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&pca9539 3 GPIO_ACTIVE_HIGH>; - startup-delay-us = <70000>; - enable-active-high; - }; - - reg_wlan: regulator-wlan { - compatible = "regulator-fixed"; - regulator-name = "3P3V_wlan"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio6 14 GPIO_ACTIVE_HIGH>; - }; - - sound { - compatible = "fsl,imx6q-ba16-sgtl5000", - "fsl,imx-audio-sgtl5000"; - model = "imx6q-ba16-sgtl5000"; - ssi-controller = <&ssi1>; - audio-codec = <&sgtl5000>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "LINE_IN", "Line In Jack", - "Headphone Jack", "HP_OUT"; - mux-int-port = <1>; - mux-ext-port = <4>; - }; - - aliases { - mdio-gpio0 = &mdio0; - }; - - mdio0: mdio-gpio { - compatible = "virtual,mdio-gpio"; - gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>, /* mdc */ - <&gpio2 7 GPIO_ACTIVE_HIGH>; /* mdio */ - - #address-cells = <1>; - #size-cells = <0>; - - switch@0 { - compatible = "marvell,mv88e6085"; /* 88e6240*/ - reg = <0>; - - switch_ports: ports { - #address-cells = <1>; - #size-cells = <0>; - }; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - switchphy0: switchphy@0 { - reg = <0>; - }; - - switchphy1: switchphy@1 { - reg = <1>; - }; - - switchphy2: switchphy@2 { - reg = <2>; - }; - - switchphy3: switchphy@3 { - reg = <3>; - }; - - switchphy4: switchphy@4 { - reg = <4>; - }; - }; - }; - }; -}; - -&ecspi5 { - cs-gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi5>; - status = "okay"; - - m25_eeprom: m25p80@0 { - compatible = "atmel,at25"; - spi-max-frequency = <10000000>; - size = <0x8000>; - pagesize = <64>; - reg = <0>; - address-width = <16>; - }; -}; - -&i2c1 { - pinctrl-names = "default", "gpio"; - pinctrl-1 = <&pinctrl_i2c1_gpio>; - sda-gpios = <&gpio5 26 GPIO_ACTIVE_HIGH>; - scl-gpios = <&gpio5 27 GPIO_ACTIVE_HIGH>; - - pca9547: mux@70 { - compatible = "nxp,pca9547"; - reg = <0x70>; - #address-cells = <1>; - #size-cells = <0>; - - mux1_i2c1: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0>; - - ads7830: ads7830@48 { - compatible = "ti,ads7830"; - reg = <0x48>; - }; - - mma8453: mma8453@1c { - compatible = "fsl,mma8453"; - reg = <0x1c>; - }; - }; - - mux1_i2c2: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x1>; - - eeprom: eeprom@50 { - compatible = "atmel,24c08"; - reg = <0x50>; - }; - - mpl3115: mpl3115@60 { - compatible = "fsl,mpl3115"; - reg = <0x60>; - }; - }; - - mux1_i2c3: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x2>; - }; - - mux1_i2c4: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x3>; - - sgtl5000: codec@a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - clocks = <&mclk>; - VDDA-supply = <®_1p8v>; - VDDIO-supply = <®_3p3v>; - }; - }; - - mux1_i2c5: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x4>; - - pca9539: pca9539@74 { - compatible = "nxp,pca9539"; - reg = <0x74>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - interrupt-parent = <&gpio2>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - - P12 { - gpio-hog; - gpios = <10 0>; - output-low; - line-name = "PCA9539-P12"; - }; - - P13 { - gpio-hog; - gpios = <11 0>; - output-low; - line-name = "PCA9539-P13"; - }; - - P14 { - gpio-hog; - gpios = <12 0>; - output-low; - line-name = "PCA9539-P14"; - }; - - P15 { - gpio-hog; - gpios = <13 0>; - output-low; - line-name = "PCA9539-P15"; - }; - - P16 { - gpio-hog; - gpios = <14 0>; - output-low; - line-name = "PCA9539-P16"; - }; - - P17 { - gpio-hog; - gpios = <15 0>; - output-low; - line-name = "PCA9539-P17"; - }; - }; - }; - - mux1_i2c6: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x5>; - }; - - mux1_i2c7: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x6>; - }; - - mux1_i2c8: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x7>; - }; - }; -}; - -&i2c2 { - pinctrl-names = "default", "gpio"; - pinctrl-1 = <&pinctrl_i2c2_gpio>; - sda-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>; - scl-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>; -}; - -&i2c3 { - pinctrl-names = "default", "gpio"; - pinctrl-1 = <&pinctrl_i2c3_gpio>; - sda-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; - scl-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; -}; - -&iomuxc { - pinctrl_i2c1_gpio: i2c1gpiogrp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x1b0b0 - MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x1b0b0 - >; - }; - - pinctrl_i2c2_gpio: i2c2gpiogrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x1b0b0 - MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x1b0b0 - >; - }; - - pinctrl_i2c3_gpio: i2c3gpiogrp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x1b0b0 - MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0 - >; - }; -}; - -&pmu { - secure-reg-access; -}; - -&usdhc2 { - status = "disabled"; -}; - -&usdhc4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc4>; - bus-width = <4>; - vmmc-supply = <®_wl18xx_vmmc>; - no-1-8-v; - non-removable; - wakeup-source; - keep-power-in-suspend; - cap-power-off-card; - max-frequency = <25000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - wlcore: wlcore@2 { - compatible = "ti,wl1837"; - reg = <2>; - interrupt-parent = <&gpio2>; - interrupts = <6 IRQ_TYPE_LEVEL_HIGH>; - tcxo-clock-frequency = <26000000>; - }; -}; - -&pcie { - /* Synopsys, Inc. Device */ - pci_root: root@0,0 { - compatible = "pci16c3,abcd"; - reg = <0x00000000 0 0 0 0>; - - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - }; -}; diff --git a/sys/gnu/dts/arm/imx6q-cm-fx6.dts b/sys/gnu/dts/arm/imx6q-cm-fx6.dts deleted file mode 100644 index cab9e92531c..00000000000 --- a/sys/gnu/dts/arm/imx6q-cm-fx6.dts +++ /dev/null @@ -1,491 +0,0 @@ -/* - * Copyright 2013 CompuLab Ltd. - * - * Author: Valentin Raevsky - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include -#include -#include "imx6q.dtsi" - -/ { - model = "CompuLab CM-FX6"; - compatible = "compulab,cm-fx6", "fsl,imx6q"; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x80000000>; - }; - - leds { - compatible = "gpio-leds"; - - heartbeat-led { - label = "Heartbeat"; - gpios = <&gpio2 31 0>; - linux,default-trigger = "heartbeat"; - }; - }; - - awnh387_pwrseq: pwrseq { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwrseq>; - compatible = "mmc-pwrseq-sd8787"; - powerdown-gpios = <&gpio7 12 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>; - }; - - reg_pcie_power_on_gpio: regulator-pcie-power-on-gpio { - compatible = "regulator-fixed"; - regulator-name = "regulator-pcie-power-on-gpio"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 24 GPIO_ACTIVE_LOW>; - }; - - reg_usb_h1_vbus: usb_h1_vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio7 8 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usb_otg_vbus: usb_otg_vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - sound-analog { - compatible = "simple-audio-card"; - simple-audio-card,name = "On-board analog audio"; - simple-audio-card,widgets = - "Headphone", "Headphone Jack", - "Line", "Line Out", - "Microphone", "Mic Jack", - "Line", "Line In"; - simple-audio-card,routing = - "Headphone Jack", "RHPOUT", - "Headphone Jack", "LHPOUT", - "MICIN", "Mic Bias", - "Mic Bias", "Mic Jack"; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&sound_master>; - simple-audio-card,frame-master = <&sound_master>; - simple-audio-card,bitclock-inversion; - - sound_master: simple-audio-card,cpu { - sound-dai = <&ssi2>; - system-clock-frequency = <2822400>; - }; - - simple-audio-card,codec { - sound-dai = <&wm8731>; - }; - }; - - sound-spdif { - compatible = "fsl,imx-audio-spdif"; - model = "imx-spdif"; - spdif-controller = <&spdif>; - spdif-out; - spdif-in; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; - - ssi2 { - fsl,audmux-port = <1>; - fsl,port-config = < - (IMX_AUDMUX_V2_PTCR_RCLKDIR | - IMX_AUDMUX_V2_PTCR_RCSEL(3 | 0x8) | - IMX_AUDMUX_V2_PTCR_TCLKDIR | - IMX_AUDMUX_V2_PTCR_TCSEL(3)) - IMX_AUDMUX_V2_PDCR_RXDSEL(3) - >; - }; - - audmux4 { - fsl,audmux-port = <3>; - fsl,port-config = < - (IMX_AUDMUX_V2_PTCR_TFSDIR | - IMX_AUDMUX_V2_PTCR_TFSEL(1) | - IMX_AUDMUX_V2_PTCR_RCLKDIR | - IMX_AUDMUX_V2_PTCR_RCSEL(1 | 0x8) | - IMX_AUDMUX_V2_PTCR_TCLKDIR | - IMX_AUDMUX_V2_PTCR_TCSEL(1)) - IMX_AUDMUX_V2_PDCR_RXDSEL(1) - >; - }; -}; - -&cpu0 { - /* - * Although the imx6q fuse indicates that 1.2GHz operation is possible, - * the module behaves unstable at this frequency. Hence, remove the - * 1.2GHz operation point here. - */ - operating-points = < - /* kHz uV */ - 996000 1250000 - 852000 1250000 - 792000 1175000 - 396000 975000 - >; - fsl,soc-operating-points = < - /* ARM kHz SOC-PU uV */ - 996000 1250000 - 852000 1250000 - 792000 1175000 - 396000 1175000 - >; -}; - -&cpu1 { - /* - * Although the imx6q fuse indicates that 1.2GHz operation is possible, - * the module behaves unstable at this frequency. Hence, remove the - * 1.2GHz operation point here. - */ - operating-points = < - /* kHz uV */ - 996000 1250000 - 852000 1250000 - 792000 1175000 - 396000 975000 - >; - fsl,soc-operating-points = < - /* ARM kHz SOC-PU uV */ - 996000 1250000 - 852000 1250000 - 792000 1175000 - 396000 1175000 - >; -}; - -&cpu2 { - /* - * Although the imx6q fuse indicates that 1.2GHz operation is possible, - * the module behaves unstable at this frequency. Hence, remove the - * 1.2GHz operation point here. - */ - operating-points = < - /* kHz uV */ - 996000 1250000 - 852000 1250000 - 792000 1175000 - 396000 975000 - >; - fsl,soc-operating-points = < - /* ARM kHz SOC-PU uV */ - 996000 1250000 - 852000 1250000 - 792000 1175000 - 396000 1175000 - >; -}; - -&cpu3 { - /* - * Although the imx6q fuse indicates that 1.2GHz operation is possible, - * the module behaves unstable at this frequency. Hence, remove the - * 1.2GHz operation point here. - */ - operating-points = < - /* kHz uV */ - 996000 1250000 - 852000 1250000 - 792000 1175000 - 396000 975000 - >; - fsl,soc-operating-points = < - /* ARM kHz SOC-PU uV */ - 996000 1250000 - 852000 1250000 - 792000 1175000 - 396000 1175000 - >; -}; - -&ecspi1 { - cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>, <&gpio3 19 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,m25p", "jedec,spi-nor"; - spi-max-frequency = <20000000>; - reg = <0>; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii"; - status = "okay"; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - status = "okay"; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - clock-frequency = <100000>; - - eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; - - wm8731: codec@1a { - #sound-dai-cells = <0>; - compatible = "wlf,wm8731"; - reg = <0x1a>; - }; -}; - -&iomuxc { - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__AUD4_RXC 0x17059 - MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x17059 - MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x17059 - MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x17059 - MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x17059 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 - MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x100b1 - MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x100b1 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - >; - }; - - pinctrl_gpmi_nand: gpminandgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 - MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = < - MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 - MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x1b0b1 - >; - }; - - pinctrl_pwrseq: pwrseqgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 - MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x1b0b0 - >; - }; - - pinctrl_spdif: spdifgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0 - MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x1b0b0 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbh1: usbh1grp { - fsl,pins = < - MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x130b0 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071 - >; - }; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio1 26 GPIO_ACTIVE_LOW>; - vpcie-supply = <®_pcie_power_on_gpio>; - status = "okay"; -}; - -&sata { - status = "okay"; -}; - -&snvs_poweroff { - status = "okay"; -}; - -&spdif { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spdif>; - status = "okay"; -}; - -&ssi2 { - assigned-clocks = <&clks IMX6QDL_CLK_SSI2_SEL>, - <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>; - assigned-clock-parents = <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>; - assigned-clock-rates = <0>, <786432000>; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usb_h1_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh1>; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - dr_mode = "otg"; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - mmc-pwrseq = <&awnh387_pwrseq>; - non-removable; - /* - * If the OS probes the Bluetooth AMP function advertised on this bus - * but the firmware in place does not support it, the WiFi/BT module - * gets unresponsive. - * Users who configured their OS properly can enable this node to gain - * WiFi and/or plain Bluetooth support. - */ - status = "disabled"; -}; diff --git a/sys/gnu/dts/arm/imx6q-cubox-i-emmc-som-v15.dts b/sys/gnu/dts/arm/imx6q-cubox-i-emmc-som-v15.dts deleted file mode 100644 index 3e59ebbb360..00000000000 --- a/sys/gnu/dts/arm/imx6q-cubox-i-emmc-som-v15.dts +++ /dev/null @@ -1,60 +0,0 @@ -/* - * Copyright (C) 2014 Russell King - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -/dts-v1/; - -#include "imx6q.dtsi" -#include "imx6qdl-sr-som.dtsi" -#include "imx6qdl-sr-som-ti.dtsi" -#include "imx6qdl-sr-som-emmc.dtsi" -#include "imx6qdl-cubox-i.dtsi" - -/ { - model = "SolidRun Cubox-i Dual/Quad (1.5som+emmc)"; - compatible = "solidrun,cubox-i/q", "fsl,imx6q"; -}; - -&sata { - status = "okay"; - fsl,transmit-level-mV = <1104>; - fsl,transmit-boost-mdB = <0>; - fsl,transmit-atten-16ths = <9>; - fsl,no-spread-spectrum; -}; diff --git a/sys/gnu/dts/arm/imx6q-cubox-i-som-v15.dts b/sys/gnu/dts/arm/imx6q-cubox-i-som-v15.dts deleted file mode 100644 index dab70d1230a..00000000000 --- a/sys/gnu/dts/arm/imx6q-cubox-i-som-v15.dts +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Copyright (C) 2014 Russell King - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -/dts-v1/; - -#include "imx6q.dtsi" -#include "imx6qdl-sr-som.dtsi" -#include "imx6qdl-sr-som-ti.dtsi" -#include "imx6qdl-cubox-i.dtsi" - -/ { - model = "SolidRun Cubox-i Dual/Quad (1.5som)"; - compatible = "solidrun,cubox-i/q", "fsl,imx6q"; -}; - -&sata { - status = "okay"; - fsl,transmit-level-mV = <1104>; - fsl,transmit-boost-mdB = <0>; - fsl,transmit-atten-16ths = <9>; - fsl,no-spread-spectrum; -}; diff --git a/sys/gnu/dts/arm/imx6q-cubox-i.dts b/sys/gnu/dts/arm/imx6q-cubox-i.dts deleted file mode 100644 index 1c7b262e370..00000000000 --- a/sys/gnu/dts/arm/imx6q-cubox-i.dts +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Copyright (C) 2014 Russell King - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -/dts-v1/; - -#include "imx6q.dtsi" -#include "imx6qdl-sr-som.dtsi" -#include "imx6qdl-sr-som-brcm.dtsi" -#include "imx6qdl-cubox-i.dtsi" - -/ { - model = "SolidRun Cubox-i Dual/Quad"; - compatible = "solidrun,cubox-i/q", "fsl,imx6q"; -}; - -&sata { - status = "okay"; - fsl,transmit-level-mV = <1104>; - fsl,transmit-boost-mdB = <0>; - fsl,transmit-atten-16ths = <9>; - fsl,no-spread-spectrum; -}; diff --git a/sys/gnu/dts/arm/imx6q-dfi-fs700-m60.dts b/sys/gnu/dts/arm/imx6q-dfi-fs700-m60.dts deleted file mode 100644 index 8bfe6337cd6..00000000000 --- a/sys/gnu/dts/arm/imx6q-dfi-fs700-m60.dts +++ /dev/null @@ -1,23 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Sascha Hauer - */ - -#ifndef __DTS_V1__ -#define __DTS_V1__ -/dts-v1/; -#endif - -#include "imx6q.dtsi" -#include "imx6qdl-dfi-fs700-m60.dtsi" - -/ { - model = "DFI FS700-M60-6QD i.MX6qd Q7 Board"; - compatible = "dfi,fs700-m60-6qd", "dfi,fs700e-m60", "fsl,imx6q"; - - /* Will be filled by the bootloader */ - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0>; - }; -}; diff --git a/sys/gnu/dts/arm/imx6q-dhcom-pdk2.dts b/sys/gnu/dts/arm/imx6q-dhcom-pdk2.dts deleted file mode 100644 index bb74fc62d91..00000000000 --- a/sys/gnu/dts/arm/imx6q-dhcom-pdk2.dts +++ /dev/null @@ -1,159 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+) -/* - * Copyright (C) 2015 DH electronics GmbH - * Copyright (C) 2018 Marek Vasut - */ - -/dts-v1/; - -#include "imx6q-dhcom-som.dtsi" - -/ { - model = "Freescale i.MX6 Quad DHCOM Premium Developer Kit (2)"; - compatible = "dh,imx6q-dhcom-pdk2", "dh,imx6q-dhcom-som", "fsl,imx6q"; - - chosen { - stdout-path = &uart1; - }; - - clk_ext_audio_codec: clock-codec { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - }; - - sound { - compatible = "fsl,imx-audio-sgtl5000"; - model = "imx-sgtl5000"; - ssi-controller = <&ssi1>; - audio-codec = <&sgtl5000>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "LINE_IN", "Line In Jack", - "Headphone Jack", "HP_OUT"; - mux-int-port = <1>; - mux-ext-port = <3>; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux_ext>; - status = "okay"; -}; - -&can1 { - status = "okay"; -}; - -&can2 { - status = "disabled"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c2>; - status = "okay"; -}; - -&i2c2 { - sgtl5000: codec@a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - #sound-dai-cells = <0>; - clocks = <&clk_ext_audio_codec>; - VDDA-supply = <®_3p3v>; - VDDIO-supply = <&sw2_reg>; - }; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog_base &pinctrl_hog>; - - pinctrl_hog: hog-grp { - fsl,pins = < - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x400120b0 - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x400120b0 - MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x400120b0 - MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x400120b0 - MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x120b0 - MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x400120b0 - MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x120b0 - MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x120b0 - MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x400120b0 - MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x400120b0 - MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x400120b0 - MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x400120b0 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x400120b0 - MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x400120b0 - MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x400120b0 - MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x400120b0 - MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0x400120b0 - MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x400120b0 - MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x400120b0 - MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x400120b0 - MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x400120b0 - MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x400120b0 - MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x400120b0 - MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x400120b0 - >; - }; - - pinctrl_audmux_ext: audmux-ext-grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 - MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 - MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 - MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 - >; - }; - - pinctrl_enet_1G: enet-1G-grp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 - MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x000b0 - MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x000b1 - MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x000b1 - >; - }; - - pinctrl_pcie: pcie-grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b1 - >; - }; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio6 14 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&ssi1 { - status = "okay"; -}; - -&sata { - status = "okay"; -}; - -&usdhc3 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx6q-dhcom-som.dtsi b/sys/gnu/dts/arm/imx6q-dhcom-som.dtsi deleted file mode 100644 index 87f0aa89708..00000000000 --- a/sys/gnu/dts/arm/imx6q-dhcom-som.dtsi +++ /dev/null @@ -1,475 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+) -/* - * Copyright (C) 2015 DH electronics GmbH - * Copyright (C) 2018 Marek Vasut - */ - -#include "imx6q.dtsi" -#include -#include -#include -#include - -/ { - aliases { - mmc0 = &usdhc2; - mmc1 = &usdhc3; - mmc2 = &usdhc4; - mmc3 = &usdhc1; - }; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x40000000>; - }; - - reg_usb_otg_vbus: regulator-usb-otg-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_usb_h1_vbus: regulator-usb-h1-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_3p3v: regulator-3P3V { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; -}; - -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; -}; - -&ecspi1 { - cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>, <&gpio4 11 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - status = "okay"; - - flash@0 { /* S25FL116K */ - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - spi-max-frequency = <50000000>; - reg = <0>; - m25p,fast-read; - }; -}; - -&ecspi2 { - cs-gpios = <&gpio5 29 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi2>; - status = "okay"; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet_100M>; - phy-mode = "rmii"; - phy-handle = <ðphy0>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@0 { /* SMSC LAN8710Ai */ - reg = <0>; - max-speed = <100>; - reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; - reset-delay-us = <1000>; - reset-post-delay-us = <1000>; - }; - }; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - ltc3676: pmic@3c { - compatible = "lltc,ltc3676"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic_hw300>; - reg = <0x3c>; - interrupt-parent = <&gpio5>; - interrupts = <2 IRQ_TYPE_EDGE_FALLING>; - - regulators { - sw1_reg: sw1 { - regulator-min-microvolt = <787500>; - regulator-max-microvolt = <1527272>; - lltc,fb-voltage-divider = <100000 110000>; - regulator-suspend-mem-microvolt = <1040000>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <1885714>; - regulator-max-microvolt = <3657142>; - lltc,fb-voltage-divider = <100000 28000>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3_reg: sw3 { - regulator-min-microvolt = <787500>; - regulator-max-microvolt = <1527272>; - lltc,fb-voltage-divider = <100000 110000>; - regulator-suspend-mem-microvolt = <980000>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - }; - - sw4_reg: sw4 { - regulator-min-microvolt = <855571>; - regulator-max-microvolt = <1659291>; - lltc,fb-voltage-divider = <100000 93100>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1_reg: ldo1 { - regulator-min-microvolt = <3240306>; - regulator-max-microvolt = <3240306>; - lltc,fb-voltage-divider = <102000 29400>; - regulator-boot-on; - regulator-always-on; - }; - - ldo2_reg: ldo2 { - regulator-min-microvolt = <2484708>; - regulator-max-microvolt = <2484708>; - lltc,fb-voltage-divider = <100000 41200>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; - - touchscreen@49 { /* TSC2004 */ - compatible = "ti,tsc2004"; - reg = <0x49>; - vio-supply = <®_3p3v>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_tsc2004_hw300>; - interrupts-extended = <&gpio4 14 IRQ_TYPE_EDGE_FALLING>; - status = "disabled"; - }; - - eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; - - rtc@56 { - compatible = "microcrystal,rv3029"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rtc_hw300>; - reg = <0x56>; - interrupt-parent = <&gpio7>; - interrupts = <12 2>; - }; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog_base>; - - pinctrl_hog_base: hog-base-grp { - fsl,pins = < - MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x120b0 - MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x120b0 - MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x120b0 - MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x120b0 - MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x120b0 - >; - }; - - pinctrl_ecspi1: ecspi1-grp { - fsl,pins = < - MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 - MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 - MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0 - >; - }; - - pinctrl_ecspi2: ecspi2-grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x100b1 - MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x100b1 - MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x100b1 - MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x1b0b0 - >; - }; - - pinctrl_enet_100M: enet-100M-grp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 - MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 - MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 - MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 - MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 - MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 - MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x000b0 - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x000b1 - MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x120b0 - >; - }; - - pinctrl_flexcan1: flexcan1-grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0 - MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0 - >; - }; - - pinctrl_flexcan2: flexcan2-grp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x1b0b0 - MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x1b0b0 - >; - }; - - pinctrl_i2c1: i2c1-grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2-grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3-grp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_pmic_hw300: pmic-hw300-grp { - fsl,pins = < - MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1B0B0 - >; - }; - - pinctrl_rtc_hw300: rtc-hw300-grp { - fsl,pins = < - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x120B0 - >; - }; - - pinctrl_tsc2004_hw300: tsc2004-hw300-grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x120B0 - >; - }; - - pinctrl_uart1: uart1-grp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D20__UART1_RTS_B 0x1b0b1 - MX6QDL_PAD_EIM_D19__UART1_CTS_B 0x4001b0b1 - MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x4001b0b1 - MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x4001b0b1 - MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x4001b0b1 - MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x4001b0b1 - >; - }; - - pinctrl_uart4: uart4-grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart5: uart5-grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT18__UART5_RTS_B 0x1b0b1 - MX6QDL_PAD_CSI0_DAT19__UART5_CTS_B 0x4001b0b1 - >; - }; - - pinctrl_usbh1: usbh1-grp { - fsl,pins = < - MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x120B0 - >; - }; - - pinctrl_usbotg: usbotg-grp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - >; - }; - - pinctrl_usdhc2: usdhc2-grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 - MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x120B0 - >; - }; - - pinctrl_usdhc3: usdhc3-grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x120B0 - >; - }; - - pinctrl_usdhc4: usdhc4-grp { - fsl,pins = < - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 - MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 - MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 - MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 - MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 - >; - }; -}; - -®_arm { - vin-supply = <&sw3_reg>; -}; - -®_soc { - vin-supply = <&sw1_reg>; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - uart-has-rtscts; - dtr-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>; - dsr-gpios = <&gpio3 25 GPIO_ACTIVE_LOW>; - dcd-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; - rng-gpios = <&gpio2 31 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - uart-has-rtscts; - status = "okay"; -}; - -&usbh1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh1>; - vbus-supply = <®_usb_h1_vbus>; - dr_mode = "host"; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - dr_mode = "otg"; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - cd-gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>; - keep-power-in-suspend; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - cd-gpios = <&gpio7 8 GPIO_ACTIVE_LOW>; - fsl,wp-controller; - keep-power-in-suspend; - status = "disabled"; -}; - -&usdhc4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc4>; - non-removable; - bus-width = <8>; - no-1-8-v; - keep-power-in-suspend; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx6q-display5-tianma-tm070-1280x768.dts b/sys/gnu/dts/arm/imx6q-display5-tianma-tm070-1280x768.dts deleted file mode 100644 index 16658b76fc4..00000000000 --- a/sys/gnu/dts/arm/imx6q-display5-tianma-tm070-1280x768.dts +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright 2017 - * Lukasz Majewski, DENX Software Engineering, lukma@denx.de - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without - * any warranty of any kind, whether express or implied. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include "imx6q-display5.dtsi" - -&panel { - compatible = "tianma,tm070jdhg30"; -}; - -&ldb { - lvds0: lvds-channel@0 { - fsl,data-mapping = "spwg"; - fsl,data-width = <18>; - }; -}; diff --git a/sys/gnu/dts/arm/imx6q-display5.dtsi b/sys/gnu/dts/arm/imx6q-display5.dtsi deleted file mode 100644 index 83524bb99eb..00000000000 --- a/sys/gnu/dts/arm/imx6q-display5.dtsi +++ /dev/null @@ -1,597 +0,0 @@ -/* - * Copyright 2017 - * Lukasz Majewski, DENX Software Engineering, lukma@denx.de - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without - * any warranty of any kind, whether express or implied. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include "imx6q.dtsi" - -#include -#include -#include - -/ { - model = "Liebherr (LWN) display5 i.MX6 Quad Board"; - compatible = "lwn,display5", "fsl,imx6q"; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x40000000>; - }; - - backlight_lvds: backlight { - compatible = "pwm-backlight"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_backlight>; - pwms = <&pwm2 0 5000000 0>; - brightness-levels = < 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100 101 102 103 104 105 106 107 108 109 - 110 111 112 113 114 115 116 117 118 119 - 120 121 122 123 124 125 126 127 128 129 - 130 131 132 133 134 135 136 137 138 139 - 140 141 142 143 144 145 146 147 148 149 - 150 151 152 153 154 155 156 157 158 159 - 160 161 162 163 164 165 166 167 168 169 - 170 171 172 173 174 175 176 177 178 179 - 180 181 182 183 184 185 186 187 188 189 - 190 191 192 193 194 195 196 197 198 199 - 200 201 202 203 204 205 206 207 208 209 - 210 211 212 213 214 215 216 217 218 219 - 220 221 222 223 224 225 226 227 228 229 - 230 231 232 233 234 235 236 237 238 239 - 240 241 242 243 244 245 246 247 248 249 - 250 251 252 253 254 255>; - default-brightness-level = <250>; - enable-gpios = <&gpio5 7 GPIO_ACTIVE_HIGH>; - }; - - reg_lvds: regulator-lvds { - compatible = "regulator-fixed"; - regulator-name = "lvds_ppen"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_lvds>; - gpio = <&gpio5 13 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usbh1_vbus: usb-h1-vbus { - compatible = "regulator-fixed"; - gpio = <&gpio3 31 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh1_vbus>; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-enable-ramp-delay = <300000>; - }; - - sound { - compatible = "simple-audio-card"; - label = "tfa9879-mono"; - - simple-audio-card,dai-link { - /* DAC */ - format = "i2s"; - bitclock-master = <&dailink_master>; - frame-master = <&dailink_master>; - - dailink_master: cpu { - sound-dai = <&ssi2>; - }; - codec { - sound-dai = <&codec>; - }; - }; - }; - - panel: panel-lvds0 { - backlight = <&backlight_lvds>; - power-supply = <®_lvds>; - - port { - panel_in_lvds0: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; - - ssi2 { - fsl,audmux-port = <1>; - fsl,port-config = < - (IMX_AUDMUX_V2_PTCR_SYN | - IMX_AUDMUX_V2_PTCR_TFSEL(5) | - IMX_AUDMUX_V2_PTCR_TCSEL(5) | - IMX_AUDMUX_V2_PTCR_TFSDIR | - IMX_AUDMUX_V2_PTCR_TCLKDIR) - IMX_AUDMUX_V2_PDCR_RXDSEL(5) - >; - }; - - aud6 { - fsl,audmux-port = <5>; - fsl,port-config = < - (IMX_AUDMUX_V2_PTCR_RFSEL(8) | - IMX_AUDMUX_V2_PTCR_RCSEL(8) | - IMX_AUDMUX_V2_PTCR_TFSEL(1) | - IMX_AUDMUX_V2_PTCR_TCSEL(1) | - IMX_AUDMUX_V2_PTCR_RFSDIR | - IMX_AUDMUX_V2_PTCR_RCLKDIR | - IMX_AUDMUX_V2_PTCR_TFSDIR | - IMX_AUDMUX_V2_PTCR_TCLKDIR) - IMX_AUDMUX_V2_PDCR_RXDSEL(1) - >; - }; -}; - -&ecspi2 { - cs-gpios = <&gpio5 29 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs &pinctrl_ecspi2_flwp>; - status = "okay"; - - s25fl256s: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - spi-max-frequency = <40000000>; - reg = <0>; - - partition@0 { - label = "SPL (spi)"; - reg = <0x0 0x20000>; - read-only; - }; - partition@1 { - label = "u-boot (spi)"; - reg = <0x20000 0x100000>; - read-only; - }; - partition@2 { - label = "uboot-env (spi)"; - reg = <0x120000 0x10000>; - }; - partition@3 { - label = "uboot-envr (spi)"; - reg = <0x130000 0x10000>; - }; - partition@4 { - label = "linux-recovery (spi)"; - reg = <0x140000 0x800000>; - }; - partition@5 { - label = "swupdate-fitImg (spi)"; - reg = <0x940000 0x400000>; - }; - partition@6 { - label = "swupdate-initramfs (spi)"; - reg = <0xD40000 0x800000>; - }; - }; -}; - -&ecspi3 { - cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3_cs &pinctrl_ecspi3_flwp>; - status = "okay"; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-handle = <ðernet_phy0>; - phy-mode = "rgmii-id"; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - ethernet_phy0: ethernet-phy@0 { - compatible = "marvell,88E1510"; - device_type = "ethernet-phy"; - /* Set LED0 control: */ - /* On - Link, Blink - Activity, Off - No Link */ - marvell,reg-init = <3 0x10 0 0x1011>; - max-speed = <100>; - reg = <0>; - }; - }; -}; - -&i2c1 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - codec: tfa9879@6c { - #sound-dai-cells = <0>; - compatible = "nxp,tfa9879"; - reg = <0x6C>; - }; -}; - -&i2c2 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&i2c3 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - at24@50 { - compatible = "atmel,24c256"; - pagesize = <64>; - reg = <0x50>; - }; - - pfuze100: pmic@8 { - compatible = "fsl,pfuze100"; - reg = <0x08>; - - regulators { - sw1a_reg: sw1ab { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw1c_reg: sw1c { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3950000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3a_reg: sw3a { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3b_reg: sw3b { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - sw4_reg: sw4 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - }; - - swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - }; - - snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - vgen1_reg: vgen1 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen2_reg: vgen2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen3_reg: vgen3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - vgen4_reg: vgen4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen5_reg: vgen5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen6_reg: vgen6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; -}; - -&ldb { - status = "okay"; - - lvds0: lvds-channel@0 { - status = "okay"; - - port@4 { - reg = <4>; - - lvds0_out: endpoint { - remote-endpoint = <&panel_in_lvds0>; - }; - }; - }; -}; - -&pwm2 { - #pwm-cells = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm2>; - status = "okay"; -}; - -&ssi2 { - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - uart-has-rtscts; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usbh1_vbus>; - pinctrl-0 = <&pinctrl_usbh1>; - status = "okay"; -}; - -&usdhc4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc4>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&iomuxc { - pinctrl_audmux: audmuxgrp { - fsl,pins = < - /* I2S OUTPUT AUD6*/ - MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x130b0 - MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x130b0 - MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x130b0 - MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x130b0 - >; - }; - - pinctrl_backlight: dispgrp { - fsl,pins = < - /* BLEN_OUT */ - MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07 0x1b0b0 - >; - }; - - pinctrl_ecspi2: ecspi2grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x100b1 - MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x100b1 - MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x100b1 - >; - }; - - pinctrl_ecspi2_cs: ecspi2csgrp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x100b1 - >; - }; - - pinctrl_ecspi2_flwp: ecspi2flwpgrp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 - >; - }; - - pinctrl_ecspi3: ecspi3grp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 - MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 - MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 - >; - }; - - pinctrl_ecspi3_cs: ecspi3csgrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x1b0b0 - >; - }; - - pinctrl_ecspi3_flwp: ecspi3flwpgrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x1b0b0 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 - MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1b0b0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 0x1b0b1 - >; - }; - - pinctrl_reg_lvds: reqlvdsgrp { - fsl,pins = < - /* LVDS_PPEN_OUT */ - MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b0 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1 - MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbh1: usbh1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D30__USB_H1_OC 0x030b0 - >; - }; - - pinctrl_usbh1_vbus: usbh1_vbus_grp { - fsl,pins = < - MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b0 - >; - }; - - pinctrl_usdhc4: usdhc4grp { - fsl,pins = < - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 - MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 - MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 - MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 - MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 - MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x17059 - >; - }; -}; diff --git a/sys/gnu/dts/arm/imx6q-dmo-edmqmx6.dts b/sys/gnu/dts/arm/imx6q-dmo-edmqmx6.dts deleted file mode 100644 index f9df207b277..00000000000 --- a/sys/gnu/dts/arm/imx6q-dmo-edmqmx6.dts +++ /dev/null @@ -1,481 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Data Modul AG - */ - -/dts-v1/; - -#include -#include "imx6q.dtsi" - -/ { - model = "Data Modul eDM-QMX6 Board"; - compatible = "dmo,imx6q-edmqmx6", "fsl,imx6q"; - - chosen { - stdout-path = &uart2; - }; - - aliases { - gpio7 = &stmpe_gpio1; - gpio8 = &stmpe_gpio2; - stmpe-i2c0 = &stmpe1; - stmpe-i2c1 = &stmpe2; - }; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x80000000>; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_3p3v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_usb_otg_switch: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "usb_otg_switch"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio7 12 0>; - regulator-boot-on; - regulator-always-on; - }; - - reg_usb_host1: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "usb_host1_en"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio3 31 0>; - enable-active-high; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - led-blue { - label = "blue"; - gpios = <&stmpe_gpio1 8 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - - led-green { - label = "green"; - gpios = <&stmpe_gpio1 9 GPIO_ACTIVE_HIGH>; - }; - - led-pink { - label = "pink"; - gpios = <&stmpe_gpio1 10 GPIO_ACTIVE_HIGH>; - }; - - led-red { - label = "red"; - gpios = <&stmpe_gpio1 11 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can1>; - status = "okay"; -}; - -&ecspi5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi5>; - cs-gpios = <&gpio1 12 0>; - status = "okay"; - - flash: m25p80@0 { - compatible = "m25p80", "jedec,spi-nor"; - spi-max-frequency = <40000000>; - reg = <0>; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii"; - phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; - phy-supply = <&vgen2_1v2_eth>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2 - &pinctrl_stmpe1 - &pinctrl_stmpe2 - &pinctrl_pfuze>; - status = "okay"; - - pmic: pfuze100@8 { - compatible = "fsl,pfuze100"; - reg = <0x08>; - interrupt-parent = <&gpio3>; - interrupts = <20 8>; - - regulators { - sw1a_reg: sw1ab { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - }; - - sw1c_reg: sw1c { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3a_reg: sw3a { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3b_reg: sw3b { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - sw4_reg: sw4 { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-always-on; - }; - - swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - regulator-always-on; - }; - - snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - vgen1_reg: vgen1 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen2_1v2_eth: vgen2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vdd_high_in: vgen3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - vgen4_reg: vgen4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen5_reg: vgen5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen6_reg: vgen6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; - - stmpe1: stmpe1601@40 { - compatible = "st,stmpe1601"; - reg = <0x40>; - interrupts = <30 0>; - interrupt-parent = <&gpio3>; - vcc-supply = <&sw2_reg>; - vio-supply = <&sw2_reg>; - - stmpe_gpio1: stmpe_gpio { - #gpio-cells = <2>; - compatible = "st,stmpe-gpio"; - }; - }; - - stmpe2: stmpe1601@44 { - compatible = "st,stmpe1601"; - reg = <0x44>; - interrupts = <2 0>; - interrupt-parent = <&gpio5>; - vcc-supply = <&sw2_reg>; - vio-supply = <&sw2_reg>; - - stmpe_gpio2: stmpe_gpio { - #gpio-cells = <2>; - compatible = "st,stmpe-gpio"; - }; - }; - - temp1: ad7414@4c { - compatible = "ad,ad7414"; - reg = <0x4c>; - }; - - temp2: ad7414@4d { - compatible = "ad,ad7414"; - reg = <0x4d>; - }; - - rtc: m41t62@68 { - compatible = "st,m41t62"; - reg = <0x68>; - }; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - imx6q-dmo-edmqmx6 { - pinctrl_hog: hoggrp { - fsl,pins = < - MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x80000000 - MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x80000000 - >; - }; - - pinctrl_can1: can1grp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0 - MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0 - >; - }; - - pinctrl_ecspi5: ecspi5rp-1 { - fsl,pins = < - MX6QDL_PAD_SD1_DAT0__ECSPI5_MISO 0x80000000 - MX6QDL_PAD_SD1_CMD__ECSPI5_MOSI 0x80000000 - MX6QDL_PAD_SD1_CLK__ECSPI5_SCLK 0x80000000 - MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x80000000 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x100b1 - >; - }; - - pinctrl_pfuze: pfuze100grp1 { - fsl,pins = < - MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x80000000 - >; - }; - - pinctrl_stmpe1: stmpe1grp { - fsl,pins = ; - }; - - pinctrl_stmpe2: stmpe2grp { - fsl,pins = ; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - >; - }; - - pinctrl_usdhc4: usdhc4grp { - fsl,pins = < - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 - MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 - MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 - MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 - MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 - >; - }; - }; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio4 8 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&sata { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usb_host1>; - disable-over-current; - dr_mode = "host"; - status = "okay"; -}; - -&usbotg { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - vmmc-supply = <®_3p3v>; - status = "okay"; -}; - -&usdhc4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc4>; - vmmc-supply = <®_3p3v>; - non-removable; - bus-width = <8>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx6q-dms-ba16.dts b/sys/gnu/dts/arm/imx6q-dms-ba16.dts deleted file mode 100644 index 57761f3172f..00000000000 --- a/sys/gnu/dts/arm/imx6q-dms-ba16.dts +++ /dev/null @@ -1,139 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -/dts-v1/; - -#include -#include "imx6q-ba16.dtsi" - -/ { - model = "Advantech DMS-BA16"; - compatible = "advantech,imx6q-dms-ba16", "advantech,imx6q-ba16", "fsl,imx6q"; - - reg_usb_otg_vbus: regulator-usbotgvbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotgvbus>; - gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - sys_mclk: clock-sys-mclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <22000000>; - }; - - sound { - compatible = "fsl,imx6q-ba16-sgtl5000", - "fsl,imx-audio-sgtl5000"; - model = "imx6q-ba16-sgtl5000"; - ssi-controller = <&ssi1>; - audio-codec = <&sgtl5000>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - mux-int-port = <1>; - mux-ext-port = <4>; - }; -}; - -&ecspi5 { - cs-gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi5>; - status = "okay"; - - m25_eeprom: m25p80@0 { - compatible = "atmel,at25256B", "atmel,at25"; - spi-max-frequency = <20000000>; - size = <0x8000>; - pagesize = <64>; - reg = <0>; - address-width = <16>; - }; -}; - -&iomuxc { - pinctrl_i2c1_gpio: i2c1gpiogrp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x1b0b0 - MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x1b0b0 - >; - }; - - pinctrl_i2c2_gpio: i2c2gpiogrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x1b0b0 - MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x1b0b0 - >; - }; - - pinctrl_i2c3_gpio: i2c3gpiogrp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x1b0b0 - MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0 - >; - }; - - pinctrl_usbotgvbus: usbotgvbusgrp { - fsl,pins = < - MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x000b0 - >; - }; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - sgtl5000: codec@a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - clocks = <&sys_mclk>; - lrclk-strength = <0x3>; - VDDA-supply = <®_1p8v>; - VDDIO-supply = <®_3p3v>; - }; -}; - -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm2>; - status = "okay"; -}; - -&sata { - fsl,no-spread-spectrum; - fsl,transmit-atten-16ths = <12>; - fsl,transmit-boost-mdB = <3330>; - fsl,transmit-level-mV = <1133>; - fsl,receive-dpll-mode = <1>; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - dr_mode = "otg"; - disable-over-current; - status = "okay"; -}; - -&usdhc4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc4>; - bus-width = <8>; - cd-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; - no-1-8-v; - keep-power-in-suspend; - wakeup-source; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx6q-emcon-avari.dts b/sys/gnu/dts/arm/imx6q-emcon-avari.dts deleted file mode 100644 index 0f582a9d4c0..00000000000 --- a/sys/gnu/dts/arm/imx6q-emcon-avari.dts +++ /dev/null @@ -1,14 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 or MIT) -// -// Copyright (C) 2018 emtrion GmbH -// - -/dts-v1/; -#include "imx6q.dtsi" -#include "imx6qdl-emcon.dtsi" -#include "imx6qdl-emcon-avari.dtsi" - -/ { - model = "emtrion SoM emCON-MX6 Dual/Quad on Avari"; - compatible = "emtrion,emcon-mx6-avari", "fsl,imx6q"; -}; diff --git a/sys/gnu/dts/arm/imx6q-evi.dts b/sys/gnu/dts/arm/imx6q-evi.dts deleted file mode 100644 index c63f371ede8..00000000000 --- a/sys/gnu/dts/arm/imx6q-evi.dts +++ /dev/null @@ -1,517 +0,0 @@ -/* - * Copyright 2016 United Western Technologies. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - -/dts-v1/; -#include "imx6q.dtsi" -#include -#include - -/ { - model = "Uniwest Evi"; - compatible = "uniwest,imx6q-evi", "fsl,imx6q"; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x40000000>; - }; - - reg_usbh1_vbus: regulator-usbhubreset { - compatible = "regulator-fixed"; - regulator-name = "usbh1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - startup-delay-us = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh1_hubreset>; - gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>; - }; - - reg_usb_otg_vbus: regulator-usbotgvbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotgvbus>; - gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - }; - - panel { - compatible = "sharp,lq101k1ly04"; - - port { - panel_in: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - }; -}; - -&ecspi1 { - cs-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1cs>; - status = "okay"; - - fpga: fpga@0 { - compatible = "altr,fpga-passive-serial"; - spi-max-frequency = <20000000>; - reg = <0>; - pinctrl-0 = <&pinctrl_fpgaspi>; - nconfig-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>; - nstat-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; - }; -}; - -&ecspi3 { - cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>, - <&gpio4 25 GPIO_ACTIVE_LOW>, - <&gpio4 26 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3cs>; - status = "okay"; -}; - -&ecspi5 { - cs-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>, - <&gpio1 13 GPIO_ACTIVE_LOW>, - <&gpio1 12 GPIO_ACTIVE_LOW>, - <&gpio2 9 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi5 &pinctrl_ecspi5cs>; - status = "okay"; - - eeprom: m95m02@1 { - compatible = "st,m95m02", "atmel,at25"; - size = <262144>; - pagesize = <256>; - address-width = <24>; - spi-max-frequency = <5000000>; - reg = <1>; - }; - - pb_rtc: rtc@3 { - compatible = "nxp,rtc-pcf2123"; - spi-max-frequency = <2450000>; - spi-cs-high; - reg = <3>; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii"; - phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; - interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, - <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; - fsl,err006687-workaround-present; - status = "okay"; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpminand>; - status = "okay"; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - clock-frequency = <100000>; - status = "okay"; -}; - -&i2c3 { - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c3>; - pinctrl-1 = <&pinctrl_i2c3_gpio>; - clock-frequency = <100000>; - scl-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio7 11 GPIO_ACTIVE_HIGH>; - status = "okay"; - - battery: sbs-battery@b { - compatible = "sbs,sbs-battery"; - reg = <0x0b>; - sbs,poll-retry-count = <100>; - sbs,i2c-retry-count = <100>; - }; -}; - -&ldb { - status = "okay"; - - lvds0: lvds-channel@0 { - status = "okay"; - - port@4 { - reg = <4>; - lvds0_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; -}; - -&ssi1 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usbh1_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh1>; - dr_mode = "host"; - disable-over-current; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - dr_mode = "otg"; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - non-removable; - status = "okay"; -}; - -&weim { - ranges = <0 0 0x08000000 0x08000000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_weimfpga &pinctrl_weimcs>; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_hog: hoggrp { - fsl,pins = < - /* pwr mcu alert irq */ - MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0 - /* remainder ???? */ - MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x1b0b0 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1 - >; - }; - - pinctrl_ecspi1cs: ecspi1csgrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 - >; - }; - - pinctrl_ecspi3: ecspi3grp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x10068 - MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x10068 - MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x1f068 - >; - }; - - pinctrl_ecspi3cs: ecspi3csgrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x1b0b0 - MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x1b0b0 - MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x1b0b0 - MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x1b0b0 - >; - }; - - pinctrl_ecspi5: ecspi5grp { - fsl,pins = < - MX6QDL_PAD_SD2_CLK__ECSPI5_SCLK 0x100b1 - MX6QDL_PAD_SD2_CMD__ECSPI5_MOSI 0x100b1 - MX6QDL_PAD_SD2_DAT0__ECSPI5_MISO 0x100b1 - >; - }; - - pinctrl_ecspi5cs: ecspi5csgrp { - fsl,pins = < - MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x1b0b0 - MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x1b0b0 - MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x1b0b0 - MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x1b0b0 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x4001b0a8 - MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 - MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 - >; - }; - - pinctrl_fpgaspi: fpgaspigrp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0 - MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0 - >; - }; - - pinctrl_gpminand: gpminandgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 - MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3_gpio: i2c3gpiogrp { - fsl,pins = < - MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x4001b8b1 - MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x4001b8b1 - >; - }; - - pinctrl_weimcs: weimcsgrp { - fsl,pins = < - MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1 - MX6QDL_PAD_EIM_CS1__EIM_CS1_B 0xb0b1 - >; - }; - - pinctrl_weimfpga: weimfpgagrp { - fsl,pins = < - /* weim misc */ - MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1 - MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1 - MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060 - MX6QDL_PAD_EIM_BCLK__EIM_BCLK 0xb0b1 - MX6QDL_PAD_EIM_LBA__EIM_LBA_B 0xb0b1 - MX6QDL_PAD_EIM_EB0__EIM_EB0_B 0xb0b1 - MX6QDL_PAD_EIM_EB1__EIM_EB1_B 0xb0b1 - MX6QDL_PAD_EIM_EB2__EIM_EB2_B 0xb0b1 - MX6QDL_PAD_EIM_EB3__EIM_EB3_B 0xb0b1 - /* weim data */ - MX6QDL_PAD_CSI0_DATA_EN__EIM_DATA00 0x1b0b0 - MX6QDL_PAD_CSI0_VSYNC__EIM_DATA01 0x1b0b0 - MX6QDL_PAD_CSI0_DAT4__EIM_DATA02 0x1b0b0 - MX6QDL_PAD_CSI0_DAT5__EIM_DATA03 0x1b0b0 - MX6QDL_PAD_CSI0_DAT6__EIM_DATA04 0x1b0b0 - MX6QDL_PAD_CSI0_DAT7__EIM_DATA05 0x1b0b0 - MX6QDL_PAD_CSI0_DAT8__EIM_DATA06 0x1b0b0 - MX6QDL_PAD_CSI0_DAT9__EIM_DATA07 0x1b0b0 - MX6QDL_PAD_CSI0_DAT12__EIM_DATA08 0x1b0b0 - MX6QDL_PAD_CSI0_DAT13__EIM_DATA09 0x1b0b0 - MX6QDL_PAD_CSI0_DAT14__EIM_DATA10 0x1b0b0 - MX6QDL_PAD_CSI0_DAT15__EIM_DATA11 0x1b0b0 - MX6QDL_PAD_CSI0_DAT16__EIM_DATA12 0x1b0b0 - MX6QDL_PAD_CSI0_DAT17__EIM_DATA13 0x1b0b0 - MX6QDL_PAD_CSI0_DAT18__EIM_DATA14 0x1b0b0 - MX6QDL_PAD_CSI0_DAT19__EIM_DATA15 0x1b0b0 - MX6QDL_PAD_EIM_D16__EIM_DATA16 0x1b0b0 - MX6QDL_PAD_EIM_D17__EIM_DATA17 0x1b0b0 - MX6QDL_PAD_EIM_D18__EIM_DATA18 0x1b0b0 - MX6QDL_PAD_EIM_D19__EIM_DATA19 0x1b0b0 - MX6QDL_PAD_EIM_D20__EIM_DATA20 0x1b0b0 - MX6QDL_PAD_EIM_D21__EIM_DATA21 0x1b0b0 - MX6QDL_PAD_EIM_D22__EIM_DATA22 0x1b0b0 - MX6QDL_PAD_EIM_D23__EIM_DATA23 0x1b0b0 - MX6QDL_PAD_EIM_D24__EIM_DATA24 0x1b0b0 - MX6QDL_PAD_EIM_D25__EIM_DATA25 0x1b0b0 - MX6QDL_PAD_EIM_D26__EIM_DATA26 0x1b0b0 - MX6QDL_PAD_EIM_D27__EIM_DATA27 0x1b0b0 - MX6QDL_PAD_EIM_D28__EIM_DATA28 0x1b0b0 - MX6QDL_PAD_EIM_D29__EIM_DATA29 0x1b0b0 - MX6QDL_PAD_EIM_D30__EIM_DATA30 0x1b0b0 - MX6QDL_PAD_EIM_D31__EIM_DATA31 0x1b0b0 - /* weim address */ - MX6QDL_PAD_EIM_A25__EIM_ADDR25 0xb0b1 - MX6QDL_PAD_EIM_A24__EIM_ADDR24 0xb0b1 - MX6QDL_PAD_EIM_A23__EIM_ADDR23 0xb0b1 - MX6QDL_PAD_EIM_A22__EIM_ADDR22 0xb0b1 - MX6QDL_PAD_EIM_A21__EIM_ADDR21 0xb0b1 - MX6QDL_PAD_EIM_A20__EIM_ADDR20 0xb0b1 - MX6QDL_PAD_EIM_A19__EIM_ADDR19 0xb0b1 - MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0b1 - MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0b1 - MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0b1 - MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1 - MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1 - MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1 - MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1 - MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1 - MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1 - MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1 - MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1 - MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1 - MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1 - MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1 - MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1 - MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1 - MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1 - MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1 - MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT5__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_DAT4__UART2_RX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_CLK__UART2_RTS_B 0x1b0b1 - MX6QDL_PAD_SD3_CMD__UART2_CTS_B 0x1b0b1 - >; - }; - - pinctrl_usbh1: usbh1grp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__USB_H1_OC 0x1b0b0 - /* usbh1_b OC */ - MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 - >; - }; - - pinctrl_usbh1_hubreset: usbh1hubresetgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 - >; - }; - - pinctrl_usbotgvbus: usbotgvbusgrp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x000b0 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 - >; - }; -}; diff --git a/sys/gnu/dts/arm/imx6q-gk802.dts b/sys/gnu/dts/arm/imx6q-gk802.dts deleted file mode 100644 index ccc2487d47c..00000000000 --- a/sys/gnu/dts/arm/imx6q-gk802.dts +++ /dev/null @@ -1,179 +0,0 @@ -/* - * Copyright (C) 2013 Philipp Zabel - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -/dts-v1/; -#include -#include -#include "imx6q.dtsi" - -/ { - model = "Zealz GK802"; - compatible = "zealz,imx6q-gk802", "fsl,imx6q"; - - chosen { - stdout-path = &uart4; - }; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x40000000>; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_3p3v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - recovery-button { - label = "recovery"; - gpios = <&gpio3 16 1>; - linux,code = ; - wakeup-source; - }; - }; -}; - -&hdmi { - ddc-i2c-bus = <&i2c3>; - status = "okay"; -}; - -/* Internal I2C */ -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - clock-frequency = <100000>; - status = "okay"; - - /* SDMC DM2016 1024 bit EEPROM + 128 bit OTP */ - eeprom: dm2016@51 { - compatible = "sdmc,dm2016"; - reg = <0x51>; - }; -}; - -/* External I2C via HDMI */ -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - clock-frequency = <100000>; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - imx6q-gk802 { - pinctrl_hog: hoggrp { - fsl,pins = < - /* Recovery button, active-low */ - MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x100b1 - /* RTL8192CU enable GPIO, active-low */ - MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - >; - }; - - pinctrl_usdhc4: usdhc4grp { - fsl,pins = < - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 - >; - }; - }; -}; - -&uart2 { - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -/* External USB-A port (USBOTG) */ -&usbotg { - disable-over-current; - status = "okay"; -}; - -/* Internal USB port (USBH1), connected to RTL8192CU */ -&usbh1 { - disable-over-current; - status = "okay"; -}; - -/* External microSD */ -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - bus-width = <4>; - cd-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_3p3v>; - status = "okay"; -}; - -/* Internal microSD */ -&usdhc4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc4>; - bus-width = <4>; - vmmc-supply = <®_3p3v>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx6q-gw51xx.dts b/sys/gnu/dts/arm/imx6q-gw51xx.dts deleted file mode 100644 index f80173458e3..00000000000 --- a/sys/gnu/dts/arm/imx6q-gw51xx.dts +++ /dev/null @@ -1,13 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Gateworks Corporation - */ - -/dts-v1/; -#include "imx6q.dtsi" -#include "imx6qdl-gw51xx.dtsi" - -/ { - model = "Gateworks Ventana i.MX6 Dual/Quad GW51XX"; - compatible = "gw,imx6q-gw51xx", "gw,ventana", "fsl,imx6q"; -}; diff --git a/sys/gnu/dts/arm/imx6q-gw52xx.dts b/sys/gnu/dts/arm/imx6q-gw52xx.dts deleted file mode 100644 index 6e1c493c9c8..00000000000 --- a/sys/gnu/dts/arm/imx6q-gw52xx.dts +++ /dev/null @@ -1,75 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Gateworks Corporation - */ - -/dts-v1/; -#include "imx6q.dtsi" -#include "imx6qdl-gw52xx.dtsi" - -/ { - model = "Gateworks Ventana i.MX6 Dual/Quad GW52XX"; - compatible = "gw,imx6q-gw52xx", "gw,ventana", "fsl,imx6q"; -}; - -&i2c3 { - adv7180: camera@20 { - compatible = "adi,adv7180"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_adv7180>; - reg = <0x20>; - powerdown-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; - interrupt-parent = <&gpio3>; - interrupts = <30 IRQ_TYPE_LEVEL_LOW>; - - port { - adv7180_to_ipu2_csi1_mux: endpoint { - remote-endpoint = <&ipu2_csi1_mux_from_parallel_sensor>; - bus-width = <8>; - }; - }; - }; -}; - -&ipu2_csi1_from_ipu2_csi1_mux { - bus-width = <8>; -}; - -&ipu2_csi1_mux_from_parallel_sensor { - remote-endpoint = <&adv7180_to_ipu2_csi1_mux>; - bus-width = <8>; -}; - -&ipu2_csi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu2_csi1>; -}; - -&iomuxc { - pinctrl_adv7180: adv7180grp { - fsl,pins = < - MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x0001b0b0 - MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x4001b0b0 - >; - }; - - pinctrl_ipu2_csi1: ipu2_csi1grp { - fsl,pins = < - MX6QDL_PAD_EIM_EB2__IPU2_CSI1_DATA19 0x1b0b0 - MX6QDL_PAD_EIM_D16__IPU2_CSI1_DATA18 0x1b0b0 - MX6QDL_PAD_EIM_D18__IPU2_CSI1_DATA17 0x1b0b0 - MX6QDL_PAD_EIM_D19__IPU2_CSI1_DATA16 0x1b0b0 - MX6QDL_PAD_EIM_D20__IPU2_CSI1_DATA15 0x1b0b0 - MX6QDL_PAD_EIM_D26__IPU2_CSI1_DATA14 0x1b0b0 - MX6QDL_PAD_EIM_D27__IPU2_CSI1_DATA13 0x1b0b0 - MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA12 0x1b0b0 - MX6QDL_PAD_EIM_D29__IPU2_CSI1_VSYNC 0x1b0b0 - MX6QDL_PAD_EIM_EB3__IPU2_CSI1_HSYNC 0x1b0b0 - MX6QDL_PAD_EIM_A16__IPU2_CSI1_PIXCLK 0x1b0b0 - >; - }; -}; - -&sata { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx6q-gw53xx.dts b/sys/gnu/dts/arm/imx6q-gw53xx.dts deleted file mode 100644 index f13df8e9c8c..00000000000 --- a/sys/gnu/dts/arm/imx6q-gw53xx.dts +++ /dev/null @@ -1,75 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Gateworks Corporation - */ - -/dts-v1/; -#include "imx6q.dtsi" -#include "imx6qdl-gw53xx.dtsi" - -/ { - model = "Gateworks Ventana i.MX6 Dual/Quad GW53XX"; - compatible = "gw,imx6q-gw53xx", "gw,ventana", "fsl,imx6q"; -}; - -&i2c3 { - adv7180: camera@20 { - compatible = "adi,adv7180"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_adv7180>; - reg = <0x20>; - powerdown-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; - interrupt-parent = <&gpio3>; - interrupts = <30 IRQ_TYPE_LEVEL_LOW>; - - port { - adv7180_to_ipu2_csi1_mux: endpoint { - remote-endpoint = <&ipu2_csi1_mux_from_parallel_sensor>; - bus-width = <8>; - }; - }; - }; -}; - -&ipu2_csi1_from_ipu2_csi1_mux { - bus-width = <8>; -}; - -&ipu2_csi1_mux_from_parallel_sensor { - remote-endpoint = <&adv7180_to_ipu2_csi1_mux>; - bus-width = <8>; -}; - -&ipu2_csi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu2_csi1>; -}; - -&sata { - status = "okay"; -}; - -&iomuxc { - pinctrl_adv7180: adv7180grp { - fsl,pins = < - MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x0001b0b0 - MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x4001b0b0 - >; - }; - - pinctrl_ipu2_csi1: ipu2_csi1grp { - fsl,pins = < - MX6QDL_PAD_EIM_EB2__IPU2_CSI1_DATA19 0x1b0b0 - MX6QDL_PAD_EIM_D16__IPU2_CSI1_DATA18 0x1b0b0 - MX6QDL_PAD_EIM_D18__IPU2_CSI1_DATA17 0x1b0b0 - MX6QDL_PAD_EIM_D19__IPU2_CSI1_DATA16 0x1b0b0 - MX6QDL_PAD_EIM_D20__IPU2_CSI1_DATA15 0x1b0b0 - MX6QDL_PAD_EIM_D26__IPU2_CSI1_DATA14 0x1b0b0 - MX6QDL_PAD_EIM_D27__IPU2_CSI1_DATA13 0x1b0b0 - MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA12 0x1b0b0 - MX6QDL_PAD_EIM_D29__IPU2_CSI1_VSYNC 0x1b0b0 - MX6QDL_PAD_EIM_EB3__IPU2_CSI1_HSYNC 0x1b0b0 - MX6QDL_PAD_EIM_A16__IPU2_CSI1_PIXCLK 0x1b0b0 - >; - }; -}; diff --git a/sys/gnu/dts/arm/imx6q-gw5400-a.dts b/sys/gnu/dts/arm/imx6q-gw5400-a.dts deleted file mode 100644 index b6e2b580051..00000000000 --- a/sys/gnu/dts/arm/imx6q-gw5400-a.dts +++ /dev/null @@ -1,510 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Gateworks Corporation - */ - -/dts-v1/; -#include -#include "imx6q.dtsi" - -/ { - model = "Gateworks Ventana GW5400-A"; - compatible = "gw,imx6q-gw5400-a", "gw,ventana", "fsl,imx6q"; - - /* these are used by bootloader for disabling nodes */ - aliases { - i2c0 = &i2c1; - i2c1 = &i2c2; - i2c2 = &i2c3; - led0 = &led0; - led1 = &led1; - led2 = &led2; - ssi0 = &ssi1; - spi0 = &ecspi1; - usb0 = &usbh1; - usb1 = &usbotg; - }; - - chosen { - bootargs = "console=ttymxc1,115200"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led0: user1 { - label = "user1"; - gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* 102 -> MX6_PANLEDG */ - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - - led1: user2 { - label = "user2"; - gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>; /* 106 -> MX6_PANLEDR */ - default-state = "off"; - }; - - led2: user3 { - label = "user3"; - gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* 111 -> MX6_LOCLED# */ - default-state = "off"; - }; - }; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x40000000>; - }; - - pps { - compatible = "pps-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_1p0v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "1P0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - reg_3p3v: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_usb_h1_vbus: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - reg_usb_otg_vbus: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - }; - - sound { - compatible = "fsl,imx6q-ventana-sgtl5000", - "fsl,imx-audio-sgtl5000"; - model = "sgtl5000-audio"; - ssi-controller = <&ssi1>; - audio-codec = <&codec>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - mux-int-port = <1>; - mux-ext-port = <4>; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; - -&ecspi1 { - cs-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - status = "okay"; - - flash: m25p80@0 { - compatible = "sst,w25q256", "jedec,spi-nor"; - spi-max-frequency = <30000000>; - reg = <0>; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii-id"; - phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c3>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - eeprom1: eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; - - eeprom2: eeprom@51 { - compatible = "atmel,24c02"; - reg = <0x51>; - pagesize = <16>; - }; - - eeprom3: eeprom@52 { - compatible = "atmel,24c02"; - reg = <0x52>; - pagesize = <16>; - }; - - eeprom4: eeprom@53 { - compatible = "atmel,24c02"; - reg = <0x53>; - pagesize = <16>; - }; - - gpio: pca9555@23 { - compatible = "nxp,pca9555"; - reg = <0x23>; - gpio-controller; - #gpio-cells = <2>; - }; - - rtc: ds1672@68 { - compatible = "dallas,ds1672"; - reg = <0x68>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - pmic: pfuze100@8 { - compatible = "fsl,pfuze100"; - reg = <0x08>; - - regulators { - sw1a_reg: sw1ab { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw1c_reg: sw1c { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3950000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3a_reg: sw3a { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3b_reg: sw3b { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - sw4_reg: sw4 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - }; - - swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - }; - - snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - vgen1_reg: vgen1 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen2_reg: vgen2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen3_reg: vgen3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - vgen4_reg: vgen4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen5_reg: vgen5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen6_reg: vgen6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - accelerometer: mma8450@1c { - compatible = "fsl,mma8450"; - reg = <0x1c>; - }; - - codec: sgtl5000@a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - clocks = <&clks IMX6QDL_CLK_CKO>; - VDDA-supply = <&sw4_reg>; - VDDIO-supply = <®_3p3v>; - }; - - touchscreen: egalax_ts@4 { - compatible = "eeti,egalax_ts"; - reg = <0x04>; - interrupt-parent = <&gpio7>; - interrupts = <12 2>; - wakeup-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>; - }; -}; - -&ldb { - status = "okay"; -}; - -&pcie { - reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&ssi1 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usb_h1_vbus>; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_3p3v>; - status = "okay"; -}; - -&iomuxc { - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 - MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 - MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 - MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */ - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 - MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b0 /* SPINOR_CS0# */ - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - >; - }; - - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 /* user1 led */ - MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 /* user2 led */ - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 /* user3 led */ - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = < - MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* PCIE IRQ */ - MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE RST */ - >; - }; - - pinctrl_pps: ppsgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0 /* GPS_PPS */ - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */ - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - >; - }; -}; diff --git a/sys/gnu/dts/arm/imx6q-gw54xx.dts b/sys/gnu/dts/arm/imx6q-gw54xx.dts deleted file mode 100644 index d5d46908cf6..00000000000 --- a/sys/gnu/dts/arm/imx6q-gw54xx.dts +++ /dev/null @@ -1,177 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Gateworks Corporation - */ - -/dts-v1/; -#include "imx6q.dtsi" -#include "imx6qdl-gw54xx.dtsi" -#include - -/ { - model = "Gateworks Ventana i.MX6 Dual/Quad GW54XX"; - compatible = "gw,imx6q-gw54xx", "gw,ventana", "fsl,imx6q"; - - sound-digital { - compatible = "simple-audio-card"; - simple-audio-card,name = "tda1997x-audio"; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&sound_codec>; - simple-audio-card,frame-master = <&sound_codec>; - - sound_cpu: simple-audio-card,cpu { - sound-dai = <&ssi2>; - }; - - sound_codec: simple-audio-card,codec { - sound-dai = <&hdmi_receiver>; - }; - }; -}; - -&i2c3 { - adv7180: camera@20 { - compatible = "adi,adv7180"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_adv7180>; - reg = <0x20>; - powerdown-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; - interrupt-parent = <&gpio3>; - interrupts = <30 IRQ_TYPE_LEVEL_LOW>; - - port { - adv7180_to_ipu2_csi1_mux: endpoint { - remote-endpoint = <&ipu2_csi1_mux_from_parallel_sensor>; - bus-width = <8>; - }; - }; - }; - - hdmi_receiver: hdmi-receiver@48 { - compatible = "nxp,tda19971"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_tda1997x>; - reg = <0x48>; - interrupt-parent = <&gpio1>; - interrupts = <7 IRQ_TYPE_LEVEL_LOW>; - DOVDD-supply = <®_3p3v>; - AVDD-supply = <&sw4_reg>; - DVDD-supply = <&sw4_reg>; - #sound-dai-cells = <0>; - nxp,audout-format = "i2s"; - nxp,audout-layout = <0>; - nxp,audout-width = <16>; - nxp,audout-mclk-fs = <128>; - /* - * The 8bpp YUV422 semi-planar mode outputs CbCr[11:4] - * and Y[11:4] across 16bits in the same cycle - * which we map to VP[15:08]<->CSI_DATA[19:12] - */ - nxp,vidout-portcfg = - /*G_Y_11_8<->VP[15:12]<->CSI_DATA[19:16]*/ - < TDA1997X_VP24_V15_12 TDA1997X_G_Y_11_8 >, - /*G_Y_7_4<->VP[11:08]<->CSI_DATA[15:12]*/ - < TDA1997X_VP24_V11_08 TDA1997X_G_Y_7_4 >, - /*R_CR_CBCR_11_8<->VP[07:04]<->CSI_DATA[11:08]*/ - < TDA1997X_VP24_V07_04 TDA1997X_R_CR_CBCR_11_8 >, - /*R_CR_CBCR_7_4<->VP[03:00]<->CSI_DATA[07:04]*/ - < TDA1997X_VP24_V03_00 TDA1997X_R_CR_CBCR_7_4 >; - - port { - tda1997x_to_ipu1_csi0_mux: endpoint { - remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; - bus-width = <16>; - hsync-active = <1>; - vsync-active = <1>; - data-active = <1>; - }; - }; - }; -}; - -&ipu1_csi0_from_ipu1_csi0_mux { - bus-width = <16>; -}; - -&ipu1_csi0_mux_from_parallel_sensor { - remote-endpoint = <&tda1997x_to_ipu1_csi0_mux>; - bus-width = <16>; -}; - -&ipu1_csi0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu1_csi0>; -}; - -&ipu2_csi1_from_ipu2_csi1_mux { - bus-width = <8>; -}; - -&ipu2_csi1_mux_from_parallel_sensor { - remote-endpoint = <&adv7180_to_ipu2_csi1_mux>; - bus-width = <8>; -}; - -&ipu2_csi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu2_csi1>; -}; - -&sata { - status = "okay"; -}; - -&iomuxc { - pinctrl_adv7180: adv7180grp { - fsl,pins = < - MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x0001b0b0 - MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x4001b0b0 - >; - }; - - pinctrl_ipu1_csi0: ipu1_csi0grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x1b0b0 - MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x1b0b0 - MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x1b0b0 - MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x1b0b0 - MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x1b0b0 - MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x1b0b0 - MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x1b0b0 - MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x1b0b0 - MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 - MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 - MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 - MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 - MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 - MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 - MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 - MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 - MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0 - MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 - MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0 - >; - }; - - pinctrl_ipu2_csi1: ipu2_csi1grp { - fsl,pins = < - MX6QDL_PAD_EIM_EB2__IPU2_CSI1_DATA19 0x1b0b0 - MX6QDL_PAD_EIM_D16__IPU2_CSI1_DATA18 0x1b0b0 - MX6QDL_PAD_EIM_D18__IPU2_CSI1_DATA17 0x1b0b0 - MX6QDL_PAD_EIM_D19__IPU2_CSI1_DATA16 0x1b0b0 - MX6QDL_PAD_EIM_D20__IPU2_CSI1_DATA15 0x1b0b0 - MX6QDL_PAD_EIM_D26__IPU2_CSI1_DATA14 0x1b0b0 - MX6QDL_PAD_EIM_D27__IPU2_CSI1_DATA13 0x1b0b0 - MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA12 0x1b0b0 - MX6QDL_PAD_EIM_D29__IPU2_CSI1_VSYNC 0x1b0b0 - MX6QDL_PAD_EIM_EB3__IPU2_CSI1_HSYNC 0x1b0b0 - MX6QDL_PAD_EIM_A16__IPU2_CSI1_PIXCLK 0x1b0b0 - >; - }; - - pinctrl_tda1997x: tda1997xgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 - >; - }; -}; diff --git a/sys/gnu/dts/arm/imx6q-gw551x.dts b/sys/gnu/dts/arm/imx6q-gw551x.dts deleted file mode 100644 index 2c7feeef1b0..00000000000 --- a/sys/gnu/dts/arm/imx6q-gw551x.dts +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Copyright 2014 Gateworks Corporation - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6q.dtsi" -#include "imx6qdl-gw551x.dtsi" - -/ { - model = "Gateworks Ventana i.MX6 Dual/Quad GW551X"; - compatible = "gw,imx6q-gw551x", "gw,ventana", "fsl,imx6q"; -}; diff --git a/sys/gnu/dts/arm/imx6q-gw552x.dts b/sys/gnu/dts/arm/imx6q-gw552x.dts deleted file mode 100644 index c973b730422..00000000000 --- a/sys/gnu/dts/arm/imx6q-gw552x.dts +++ /dev/null @@ -1,18 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2014 Gateworks Corporation - */ - -/dts-v1/; - -#include "imx6q.dtsi" -#include "imx6qdl-gw552x.dtsi" - -/ { - model = "Gateworks Ventana i.MX6 Dual/Quad GW552X"; - compatible = "gw,imx6q-gw552x", "gw,ventana", "fsl,imx6q"; -}; - -&sata { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx6q-gw553x.dts b/sys/gnu/dts/arm/imx6q-gw553x.dts deleted file mode 100644 index e9c224cea75..00000000000 --- a/sys/gnu/dts/arm/imx6q-gw553x.dts +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Copyright 2016 Gateworks Corporation - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6q.dtsi" -#include "imx6qdl-gw553x.dtsi" - -/ { - model = "Gateworks Ventana i.MX6 Dual/Quad GW553X"; - compatible = "gw,imx6q-gw553x", "gw,ventana", "fsl,imx6q"; -}; diff --git a/sys/gnu/dts/arm/imx6q-gw560x.dts b/sys/gnu/dts/arm/imx6q-gw560x.dts deleted file mode 100644 index 735f2bbf143..00000000000 --- a/sys/gnu/dts/arm/imx6q-gw560x.dts +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Copyright 2017 Gateworks Corporation - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6q.dtsi" -#include "imx6qdl-gw560x.dtsi" - -/ { - model = "Gateworks Ventana i.MX6 Dual/Quad GW560X"; - compatible = "gw,imx6q-gw560x", "gw,ventana", "fsl,imx6q"; -}; - -&sata { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx6q-gw5903.dts b/sys/gnu/dts/arm/imx6q-gw5903.dts deleted file mode 100644 index a182e4cb0e6..00000000000 --- a/sys/gnu/dts/arm/imx6q-gw5903.dts +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Copyright 2017 Gateworks Corporation - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6q.dtsi" -#include "imx6qdl-gw5903.dtsi" - -/ { - model = "Gateworks Ventana i.MX6 Dual/Quad GW5903"; - compatible = "gw,imx6q-gw5903", "gw,ventana", "fsl,imx6q"; -}; diff --git a/sys/gnu/dts/arm/imx6q-gw5904.dts b/sys/gnu/dts/arm/imx6q-gw5904.dts deleted file mode 100644 index ca1e2ae3341..00000000000 --- a/sys/gnu/dts/arm/imx6q-gw5904.dts +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Copyright 2017 Gateworks Corporation - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6q.dtsi" -#include "imx6qdl-gw5904.dtsi" - -/ { - model = "Gateworks Ventana i.MX6 Dual/Quad GW5904"; - compatible = "gw,imx6q-gw5904", "gw,ventana", "fsl,imx6q"; -}; - -&sata { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx6q-gw5907.dts b/sys/gnu/dts/arm/imx6q-gw5907.dts deleted file mode 100644 index b25526ef588..00000000000 --- a/sys/gnu/dts/arm/imx6q-gw5907.dts +++ /dev/null @@ -1,14 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2019 Gateworks Corporation - */ - -/dts-v1/; - -#include "imx6q.dtsi" -#include "imx6qdl-gw5907.dtsi" - -/ { - model = "Gateworks Ventana i.MX6 Dual/Quad GW5907"; - compatible = "gw,imx6q-gw5907", "gw,ventana", "fsl,imx6q"; -}; diff --git a/sys/gnu/dts/arm/imx6q-gw5910.dts b/sys/gnu/dts/arm/imx6q-gw5910.dts deleted file mode 100644 index 6aafa2fcee0..00000000000 --- a/sys/gnu/dts/arm/imx6q-gw5910.dts +++ /dev/null @@ -1,14 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2019 Gateworks Corporation - */ - -/dts-v1/; - -#include "imx6q.dtsi" -#include "imx6qdl-gw5910.dtsi" - -/ { - model = "Gateworks Ventana i.MX6 Dual/Quad GW5910"; - compatible = "gw,imx6q-gw5910", "gw,ventana", "fsl,imx6q"; -}; diff --git a/sys/gnu/dts/arm/imx6q-gw5912.dts b/sys/gnu/dts/arm/imx6q-gw5912.dts deleted file mode 100644 index 4dcbd943cd9..00000000000 --- a/sys/gnu/dts/arm/imx6q-gw5912.dts +++ /dev/null @@ -1,13 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2019 Gateworks Corporation - */ - -/dts-v1/; -#include "imx6q.dtsi" -#include "imx6qdl-gw5912.dtsi" - -/ { - model = "Gateworks Ventana i.MX6 Dual/Quad GW5912"; - compatible = "gw,imx6q-gw5912", "gw,ventana", "fsl,imx6q"; -}; diff --git a/sys/gnu/dts/arm/imx6q-gw5913.dts b/sys/gnu/dts/arm/imx6q-gw5913.dts deleted file mode 100644 index 6f511f1665f..00000000000 --- a/sys/gnu/dts/arm/imx6q-gw5913.dts +++ /dev/null @@ -1,14 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2019 Gateworks Corporation - */ - -/dts-v1/; - -#include "imx6q.dtsi" -#include "imx6qdl-gw5913.dtsi" - -/ { - model = "Gateworks Ventana i.MX6 Dual/Quad GW5913"; - compatible = "gw,imx6q-gw5913", "gw,ventana", "fsl,imx6q"; -}; diff --git a/sys/gnu/dts/arm/imx6q-h100.dts b/sys/gnu/dts/arm/imx6q-h100.dts deleted file mode 100644 index b8feadbff96..00000000000 --- a/sys/gnu/dts/arm/imx6q-h100.dts +++ /dev/null @@ -1,382 +0,0 @@ -/* - * Copyright (C) 2015 Lucas Stach - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include "imx6q.dtsi" -#include "imx6qdl-sr-som.dtsi" -#include "imx6qdl-sr-som-brcm.dtsi" - -/ { - model = "Auvidea H100"; - compatible = "auvidea,h100", "fsl,imx6q"; - - /* Will be filled by the bootloader */ - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0>; - }; - - aliases { - rtc0 = &rtc; - rtc1 = &snvs_rtc; - }; - - chosen { - stdout-path = &uart2; - }; - - hdmi_osc: hdmi-osc { - compatible = "fixed-clock"; - clock-output-names = "hdmi-osc"; - clock-frequency = <27000000>; - #clock-cells = <0>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_h100_leds>; - - led0: power { - label = "power"; - gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; - default-state = "on"; - }; - - led1: stream { - label = "stream"; - gpios = <&gpio2 29 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led2: rec { - label = "rec"; - gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_hdmi: regulator-hdmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_h100_reg_hdmi>; - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>; - regulator-name = "V_HDMI"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - reg_usbh1_vbus: regulator-usb-h1-vbus { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_h100_usbh1_vbus>; - regulator-name = "USB_H1_VBUS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_usbotg_vbus: regulator-usb-otg-vbus { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_h100_usbotg_vbus>; - regulator-name = "USB_OTG_VBUS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - sound-sgtl5000 { - compatible = "fsl,imx-audio-sgtl5000"; - model = "H100 on-board codec"; - audio-codec = <&sgtl5000>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - mux-ext-port = <5>; - mux-int-port = <1>; - ssi-controller = <&ssi1>; - }; -}; - -&audmux { - status = "okay"; -}; - -&hdmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_h100_hdmi>; - ddc-i2c-bus = <&i2c2>; - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_h100_i2c1>; - status = "okay"; - - eeprom: 24c02@51 { - compatible = "microchip,24c02", "atmel,24c02"; - reg = <0x51>; - }; - - rtc: pcf8523@68 { - compatible = "nxp,pcf8523"; - reg = <0x68>; - }; - - sgtl5000: sgtl5000@a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_h100_sgtl5000>; - clocks = <&clks IMX6QDL_CLK_CKO>; - VDDA-supply = <®_3p3v>; - VDDIO-supply = <®_3p3v>; - }; - - tc358743: tc358743@f { - compatible = "toshiba,tc358743"; - reg = <0x0f>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_h100_tc358743>; - clocks = <&hdmi_osc>; - clock-names = "refclk"; - reset-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>; - /* IRQ has a wrong pull resistor which renders it useless */ - - port { - tc358743_out: endpoint { - remote-endpoint = <&mipi_csi2_in>; - data-lanes = <1 2 3 4>; - clock-lanes = <0>; - clock-noncontinuous; - link-frequencies = /bits/ 64 <297000000>; - }; - }; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_h100_i2c2>; - status = "okay"; -}; - -&iomuxc { - h100 { - pinctrl_h100_hdmi: h100-hdmi { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 - >; - }; - - pinctrl_h100_i2c1: h100-i2c1 { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_h100_i2c2: h100-i2c2 { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_h100_leds: pinctrl-h100-leds { - fsl,pins = < - MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x1b0b0 - MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x1b0b0 - MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x1b0b0 - >; - }; - - pinctrl_h100_reg_hdmi: h100-reg-hdmi { - fsl,pins = < - MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b0 - >; - }; - - pinctrl_h100_sgtl5000: h100-sgtl5000 { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0 - MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0 - MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x110b0 - MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0 - MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x130b0 - >; - }; - - pinctrl_h100_tc358743: h100-tc358743 { - fsl,pins = < - MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 - >; - }; - - pinctrl_h100_uart2: h100-uart2 { - fsl,pins = < - MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 - >; - }; - - pinctrl_h100_usbh1_vbus: hummingboard-usbh1-vbus { - fsl,pins = < - MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 - >; - }; - - pinctrl_h100_usbotg_id: hummingboard-usbotg-id { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059 - >; - }; - - pinctrl_h100_usbotg_vbus: hummingboard-usbotg-vbus { - fsl,pins = < - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 - >; - }; - - pinctrl_h100_usdhc2: h100-usdhc2 { - fsl,pins = < - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1f071 - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059 - MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x1b0b0 - >; - }; - - pinctrl_h100_usdhc2_100mhz: h100-usdhc2-100mhz { - fsl,pins = < - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1f071 - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 - MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x1b0b0 - >; - }; - - pinctrl_h100_usdhc2_200mhz: h100-usdhc2-200mhz { - fsl,pins = < - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1f071 - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170f9 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100f9 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170f9 - MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x1b0b0 - >; - }; - }; -}; - -&mipi_csi { - status = "okay"; - - port { - mipi_csi2_in: endpoint { - remote-endpoint = <&tc358743_out>; - data-lanes = <1 2 3 4>; - clock-lanes = <0>; - clock-noncontinuous; - link-frequencies = /bits/ 64 <297000000>; - }; - }; -}; - -&ssi1 { - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_h100_uart2>; - status = "okay"; -}; - -&usbh1 { - disable-over-current; - vbus-supply = <®_usbh1_vbus>; - status = "okay"; -}; - -&usbotg { - disable-over-current; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_h100_usbotg_id>; - vbus-supply = <®_usbotg_vbus>; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_h100_usdhc2>; - pinctrl-1 = <&pinctrl_h100_usdhc2_100mhz>; - pinctrl-2 = <&pinctrl_h100_usdhc2_200mhz>; - vmmc-supply = <®_3p3v>; - cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx6q-hummingboard-emmc-som-v15.dts b/sys/gnu/dts/arm/imx6q-hummingboard-emmc-som-v15.dts deleted file mode 100644 index c51b4e4fd71..00000000000 --- a/sys/gnu/dts/arm/imx6q-hummingboard-emmc-som-v15.dts +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright (C) 2014 Rabeeh Khoury (rabeeh@solid-run.com) - * Based on dt work by Russell King - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -/dts-v1/; - -#include "imx6q.dtsi" -#include "imx6qdl-sr-som.dtsi" -#include "imx6qdl-sr-som-ti.dtsi" -#include "imx6qdl-sr-som-emmc.dtsi" -#include "imx6qdl-hummingboard.dtsi" - -/ { - model = "SolidRun HummingBoard Dual/Quad (1.5som+emmc)"; - compatible = "solidrun,hummingboard/q", "fsl,imx6q"; -}; - -&sata { - status = "okay"; - fsl,transmit-level-mV = <1025>; - fsl,transmit-boost-mdB = <3330>; - fsl,transmit-atten-16ths = <9>; - fsl,receive-eq-mdB = <3000>; -}; diff --git a/sys/gnu/dts/arm/imx6q-hummingboard-som-v15.dts b/sys/gnu/dts/arm/imx6q-hummingboard-som-v15.dts deleted file mode 100644 index e4132d62ffa..00000000000 --- a/sys/gnu/dts/arm/imx6q-hummingboard-som-v15.dts +++ /dev/null @@ -1,60 +0,0 @@ -/* - * Copyright (C) 2014 Rabeeh Khoury (rabeeh@solid-run.com) - * Based on dt work by Russell King - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -/dts-v1/; - -#include "imx6q.dtsi" -#include "imx6qdl-sr-som.dtsi" -#include "imx6qdl-sr-som-ti.dtsi" -#include "imx6qdl-hummingboard.dtsi" - -/ { - model = "SolidRun HummingBoard Dual/Quad (1.5som)"; - compatible = "solidrun,hummingboard/q", "fsl,imx6q"; -}; - -&sata { - status = "okay"; - fsl,transmit-level-mV = <1025>; - fsl,transmit-boost-mdB = <3330>; - fsl,transmit-atten-16ths = <9>; - fsl,receive-eq-mdB = <3000>; -}; diff --git a/sys/gnu/dts/arm/imx6q-hummingboard.dts b/sys/gnu/dts/arm/imx6q-hummingboard.dts deleted file mode 100644 index 8c9e94e648a..00000000000 --- a/sys/gnu/dts/arm/imx6q-hummingboard.dts +++ /dev/null @@ -1,60 +0,0 @@ -/* - * Copyright (C) 2014 Rabeeh Khoury (rabeeh@solid-run.com) - * Based on dt work by Russell King - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -/dts-v1/; - -#include "imx6q.dtsi" -#include "imx6qdl-sr-som.dtsi" -#include "imx6qdl-sr-som-brcm.dtsi" -#include "imx6qdl-hummingboard.dtsi" - -/ { - model = "SolidRun HummingBoard Dual/Quad"; - compatible = "solidrun,hummingboard/q", "fsl,imx6q"; -}; - -&sata { - status = "okay"; - fsl,transmit-level-mV = <1025>; - fsl,transmit-boost-mdB = <3330>; - fsl,transmit-atten-16ths = <9>; - fsl,receive-eq-mdB = <3000>; -}; diff --git a/sys/gnu/dts/arm/imx6q-hummingboard2-emmc-som-v15.dts b/sys/gnu/dts/arm/imx6q-hummingboard2-emmc-som-v15.dts deleted file mode 100644 index 1998ebfa0fe..00000000000 --- a/sys/gnu/dts/arm/imx6q-hummingboard2-emmc-som-v15.dts +++ /dev/null @@ -1,63 +0,0 @@ -/* - * Device Tree file for SolidRun HummingBoard2 - * Copyright (C) 2015 Rabeeh Khoury - * Based on work by Russell King - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -/dts-v1/; - -#include "imx6q.dtsi" -#include "imx6qdl-sr-som.dtsi" -#include "imx6qdl-sr-som-emmc.dtsi" -#include "imx6qdl-sr-som-ti.dtsi" -#include "imx6qdl-hummingboard2.dtsi" - -/ { - model = "SolidRun HummingBoard2 Dual/Quad (1.5som+emmc)"; - compatible = "solidrun,hummingboard2/q", "fsl,imx6q"; -}; - -&sata { - status = "okay"; - fsl,transmit-level-mV = <1104>; - fsl,transmit-boost-mdB = <0>; - fsl,transmit-atten-16ths = <9>; - fsl,no-spread-spectrum; -}; diff --git a/sys/gnu/dts/arm/imx6q-hummingboard2-som-v15.dts b/sys/gnu/dts/arm/imx6q-hummingboard2-som-v15.dts deleted file mode 100644 index d3ad7329cd6..00000000000 --- a/sys/gnu/dts/arm/imx6q-hummingboard2-som-v15.dts +++ /dev/null @@ -1,62 +0,0 @@ -/* - * Device Tree file for SolidRun HummingBoard2 - * Copyright (C) 2015 Rabeeh Khoury - * Based on work by Russell King - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -/dts-v1/; - -#include "imx6q.dtsi" -#include "imx6qdl-sr-som.dtsi" -#include "imx6qdl-sr-som-ti.dtsi" -#include "imx6qdl-hummingboard2.dtsi" - -/ { - model = "SolidRun HummingBoard2 Dual/Quad (1.5som)"; - compatible = "solidrun,hummingboard2/q", "fsl,imx6q"; -}; - -&sata { - status = "okay"; - fsl,transmit-level-mV = <1104>; - fsl,transmit-boost-mdB = <0>; - fsl,transmit-atten-16ths = <9>; - fsl,no-spread-spectrum; -}; diff --git a/sys/gnu/dts/arm/imx6q-hummingboard2.dts b/sys/gnu/dts/arm/imx6q-hummingboard2.dts deleted file mode 100644 index 5249f53dcdb..00000000000 --- a/sys/gnu/dts/arm/imx6q-hummingboard2.dts +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright (C) 2015 Rabeeh Khoury - * Based on dt work by Russell King - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -/dts-v1/; - -#include "imx6q.dtsi" -#include "imx6qdl-sr-som.dtsi" -#include "imx6qdl-sr-som-brcm.dtsi" -#include "imx6qdl-hummingboard2.dtsi" -#include "imx6qdl-hummingboard2-emmc.dtsi" - -/ { - model = "SolidRun HummingBoard2 Dual/Quad"; - compatible = "solidrun,hummingboard2/q", "fsl,imx6q"; -}; - -&sata { - status = "okay"; - fsl,transmit-level-mV = <1104>; - fsl,transmit-boost-mdB = <0>; - fsl,transmit-atten-16ths = <9>; - fsl,no-spread-spectrum; -}; diff --git a/sys/gnu/dts/arm/imx6q-icore-mipi.dts b/sys/gnu/dts/arm/imx6q-icore-mipi.dts deleted file mode 100644 index d51745268db..00000000000 --- a/sys/gnu/dts/arm/imx6q-icore-mipi.dts +++ /dev/null @@ -1,33 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR X11 -/* - * Copyright (C) 2017 Engicam S.r.l. - * Copyright (C) 2017 Amarula Solutions B.V. - * Author: Jagan Teki - */ - -/dts-v1/; - -#include "imx6q.dtsi" -#include "imx6qdl-icore-1.5.dtsi" - -/ { - model = "Engicam i.CoreM6 1.5 Quad/Dual MIPI Starter Kit"; - compatible = "engicam,imx6-icore", "fsl,imx6q"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c2>; - status = "okay"; -}; - -&mipi_csi { - status = "okay"; -}; - -&ov5640 { - status = "okay"; -}; - -&usdhc3 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx6q-icore-ofcap10.dts b/sys/gnu/dts/arm/imx6q-icore-ofcap10.dts deleted file mode 100644 index 81cc346dd14..00000000000 --- a/sys/gnu/dts/arm/imx6q-icore-ofcap10.dts +++ /dev/null @@ -1,40 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2016 Amarula Solutions B.V. - * Copyright (C) 2016 Engicam S.r.l. - */ - -/dts-v1/; - -#include "imx6q.dtsi" -#include "imx6qdl-icore.dtsi" - -/ { - model = "Engicam i.CoreM6 Quad/Dual OpenFrame Capacitive touch 10.1 Kit"; - compatible = "engicam,imx6-icore", "fsl,imx6q"; -}; - -&ldb { - status = "okay"; - - lvds-channel@0 { - fsl,data-mapping = "spwg"; - fsl,data-width = <24>; - status = "okay"; - - display-timings { - native-mode = <&timing0>; - timing0: timing0 { - clock-frequency = <60000000>; - hactive = <1280>; - vactive = <800>; - hback-porch = <40>; - hfront-porch = <40>; - vback-porch = <10>; - vfront-porch = <3>; - hsync-len = <80>; - vsync-len = <10>; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/imx6q-icore-ofcap12.dts b/sys/gnu/dts/arm/imx6q-icore-ofcap12.dts deleted file mode 100644 index 241811c52b6..00000000000 --- a/sys/gnu/dts/arm/imx6q-icore-ofcap12.dts +++ /dev/null @@ -1,43 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2016 Amarula Solutions B.V. - * Copyright (C) 2016 Engicam S.r.l. - */ - -/dts-v1/; - -#include "imx6q.dtsi" -#include "imx6qdl-icore.dtsi" - -/ { - model = "Engicam i.CoreM6 Quad/Dual OpenFrame Capacitive touch 12 Kit"; - compatible = "engicam,imx6-icore", "fsl,imx6q"; - - panel { - compatible = "koe,tx31d200vm0baa"; - backlight = <&backlight_lvds>; - - port { - panel_in: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - }; -}; - -&ldb { - status = "okay"; - - lvds-channel@0 { - reg = <0>; - status = "okay"; - - port@4 { - reg = <4>; - - lvds0_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/imx6q-icore-rqs.dts b/sys/gnu/dts/arm/imx6q-icore-rqs.dts deleted file mode 100644 index cf6ba724f49..00000000000 --- a/sys/gnu/dts/arm/imx6q-icore-rqs.dts +++ /dev/null @@ -1,19 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2015 Amarula Solutions B.V. - * Copyright (C) 2015 Engicam S.r.l. - */ - -/dts-v1/; - -#include "imx6q.dtsi" -#include "imx6qdl-icore-rqs.dtsi" - -/ { - model = "Engicam i.CoreM6 Quad/Dual RQS Starter Kit"; - compatible = "engicam,imx6-icore-rqs", "fsl,imx6q"; -}; - -&sata { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx6q-icore.dts b/sys/gnu/dts/arm/imx6q-icore.dts deleted file mode 100644 index fe28c3cf54c..00000000000 --- a/sys/gnu/dts/arm/imx6q-icore.dts +++ /dev/null @@ -1,57 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR X11 -/* - * Copyright (C) 2016 Amarula Solutions B.V. - * Copyright (C) 2016 Engicam S.r.l. - */ - -/dts-v1/; - -#include "imx6q.dtsi" -#include "imx6qdl-icore.dtsi" - -/ { - model = "Engicam i.CoreM6 Quad/Dual Starter Kit"; - compatible = "engicam,imx6-icore", "fsl,imx6q"; -}; - -&can1 { - status = "okay"; -}; - -&can2 { - status = "okay"; -}; - -&i2c1 { - max11801: touchscreen@48 { - compatible = "maxim,max11801"; - reg = <0x48>; - interrupt-parent = <&gpio3>; - interrupts = <31 IRQ_TYPE_EDGE_FALLING>; - }; -}; - -&ldb { - status = "okay"; - - lvds-channel@0 { - fsl,data-mapping = "spwg"; - fsl,data-width = <18>; - status = "okay"; - - display-timings { - native-mode = <&timing0>; - timing0: timing0 { - clock-frequency = <60000000>; - hactive = <800>; - vactive = <480>; - hback-porch = <30>; - hfront-porch = <30>; - vback-porch = <5>; - vfront-porch = <5>; - hsync-len = <64>; - vsync-len = <20>; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/imx6q-kontron-samx6i.dtsi b/sys/gnu/dts/arm/imx6q-kontron-samx6i.dtsi deleted file mode 100644 index 2618eccfe50..00000000000 --- a/sys/gnu/dts/arm/imx6q-kontron-samx6i.dtsi +++ /dev/null @@ -1,36 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR X11 -/* - * Copyright 2019 (C) Pengutronix, Marco Felsch - */ - -#include "imx6q.dtsi" -#include "imx6qdl-kontron-samx6i.dtsi" -#include - -/ { - model = "Kontron SMARC sAMX6i Quad/Dual"; - compatible = "kontron,imx6q-samx6i", "fsl,imx6q"; -}; - -/* Quad/Dual SoMs have 3 chip-select signals */ -&ecspi4 { - fsl,spi-num-chipselects = <3>; - cs-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>, - <&gpio3 29 GPIO_ACTIVE_HIGH>, - <&gpio3 25 GPIO_ACTIVE_HIGH>; -}; - -&pinctrl_ecspi4 { - fsl,pins = < - MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1 - MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1 - MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1 - - /* SPI4_IMX_CS2# - connected to internal flash */ - MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x1b0b0 - /* SPI4_IMX_CS0# - connected to SMARC SPI0_CS0# */ - MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0 - /* SPI4_CS3# - connected to SMARC SPI0_CS1# */ - MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x1b0b0 - >; -}; diff --git a/sys/gnu/dts/arm/imx6q-kp-tpc.dts b/sys/gnu/dts/arm/imx6q-kp-tpc.dts deleted file mode 100644 index 50fbf46d17c..00000000000 --- a/sys/gnu/dts/arm/imx6q-kp-tpc.dts +++ /dev/null @@ -1,23 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2018 - * Lukasz Majewski, DENX Software Engineering, lukma@denx.de - */ - -/dts-v1/; - -#include "imx6q-kp.dtsi" - -/ { - model = "Freescale i.MX6 Qwuad K+P TPC Board"; - compatible = "kiebackpeter,imx6q-tpc", "fsl,imx6q"; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x40000000>; - }; -}; - -&ipu1_di0_disp0 { - remote-endpoint = <&lcd_display_in>; -}; diff --git a/sys/gnu/dts/arm/imx6q-kp.dtsi b/sys/gnu/dts/arm/imx6q-kp.dtsi deleted file mode 100644 index 24c8169baf4..00000000000 --- a/sys/gnu/dts/arm/imx6q-kp.dtsi +++ /dev/null @@ -1,432 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2018 - * Lukasz Majewski, DENX Software Engineering, lukma@denx.de - */ - -/dts-v1/; - -#include "imx6q.dtsi" - -#include -#include -#include - -/ { - backlight_lcd: backlight-lcd { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 5000000>; - brightness-levels = <0 255>; - num-interpolated-steps = <255>; - default-brightness-level = <250>; - }; - - beeper { - compatible = "pwm-beeper"; - pwms = <&pwm2 0 500000>; - }; - - lcd_display: display { - compatible = "fsl,imx-parallel-display"; - #address-cells = <1>; - #size-cells = <0>; - interface-pix-fmt = "rgb24"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu1>; - - port@0 { - reg = <0>; - - lcd_display_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - - port@1 { - reg = <1>; - - lcd_display_out: endpoint { - remote-endpoint = <&lcd_panel_in>; - }; - }; - }; - - lcd_panel: lcd-panel { - compatible = "auo,g070vvn01"; - backlight = <&backlight_lcd>; - power-supply = <®_display>; - - port { - lcd_panel_in: endpoint { - remote-endpoint = <&lcd_display_out>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - green { - label = "led1"; - gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "gpio"; - default-state = "off"; - }; - - red { - label = "led0"; - gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "gpio"; - default-state = "off"; - }; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_audio: regulator-audio { - compatible = "regulator-fixed"; - regulator-name = "sgtl5000-supply"; - gpio = <&gpio6 31 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - }; - - reg_display: regulator-display { - compatible = "regulator-fixed"; - regulator-name = "display-supply"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_usb_h1_vbus: regulator-usb_h1_vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "imx6q-sgtl5000-audio"; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&codec_dai>; - simple-audio-card,frame-master = <&codec_dai>; - - cpu_dai: simple-audio-card,cpu { - sound-dai = <&ssi1>; - }; - - codec_dai: simple-audio-card,codec { - sound-dai = <&sgtl5000>; - }; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; - - ssi1 { - fsl,audmux-port = <0>; - fsl,port-config = < - (IMX_AUDMUX_V2_PTCR_SYN | - IMX_AUDMUX_V2_PTCR_TFSEL(2) | - IMX_AUDMUX_V2_PTCR_TCSEL(2) | - IMX_AUDMUX_V2_PTCR_TFSDIR | - IMX_AUDMUX_V2_PTCR_TCLKDIR) - IMX_AUDMUX_V2_PDCR_RXDSEL(2) - >; - }; - - aud3 { - fsl,audmux-port = <2>; - fsl,port-config = < - IMX_AUDMUX_V2_PTCR_SYN - IMX_AUDMUX_V2_PDCR_RXDSEL(0) - >; - }; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; -}; - -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii"; - fsl,magic-packet; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - touchscreen@5d { - compatible = "goodix,gt911"; - reg = <0x5d>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ts>; - interrupt-parent = <&gpio1>; - interrupts = <9 IRQ_TYPE_EDGE_FALLING>; - irq-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; - }; - - ds1307: rtc@32 { - compatible = "dallas,ds1307"; - reg = <0x32>; - }; -}; - -&i2c2 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - sgtl5000: audio-codec@a { - compatible = "fsl,sgtl5000"; - #sound-dai-cells = <0>; - reg = <0x0a>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_codec>; - clocks = <&clks IMX6QDL_CLK_CKO>; - VDDA-supply = <®_3p3v>; - VDDIO-supply = <®_3p3v>; - }; -}; - -&iomuxc { - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 - MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 - MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 - MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 - >; - }; - - pinctrl_codec: codecgrp { - fsl,pins = < - MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b0 - /* sgtl5000 sys_mclk clock routed to CLKO1 */ - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - >; - }; - - pinctrl_flexcan1: can1grp { - fsl,pins = < - MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0 - MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0 - >; - }; - - pinctrl_flexcan2: can2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0 - MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 - MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_ipu1: ipu1grp { - fsl,pins = < - MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 - MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 - MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 - MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 - MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 - MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 - MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 - MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 - MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 - MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 - MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 - MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 - MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 - MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 - MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 - MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 - MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 - MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 - MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 - MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 - MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 - MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 - MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 - MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 - MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 - MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 - MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 - MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 - >; - }; - - pinctrl_ts: tsgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 - MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b0 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D28__UART2_CTS_B 0x1b0b1 - MX6QDL_PAD_EIM_D29__UART2_RTS_B 0x1b0b1 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 - >; - }; - - pinctrl_usdhc4: usdhc4grp { - fsl,pins = < - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 - MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 - MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 - MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 - MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 - >; - }; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "okay"; -}; - -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm2>; - status = "okay"; -}; - -&ssi1 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - uart-has-rtscts; -}; - -&usbh1 { - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - bus-width = <4>; - cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&usdhc4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc4>; - bus-width = <8>; - non-removable; - no-1-8-v; - keep-power-in-suspend; - status = "okay"; -}; - -&wdog1 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx6q-logicpd.dts b/sys/gnu/dts/arm/imx6q-logicpd.dts deleted file mode 100644 index 7a3d1d3e54a..00000000000 --- a/sys/gnu/dts/arm/imx6q-logicpd.dts +++ /dev/null @@ -1,130 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// -// Copyright (C) 2019 Logic PD, Inc. - -/dts-v1/; -#include "imx6q.dtsi" -#include "imx6-logicpd-som.dtsi" -#include "imx6-logicpd-baseboard.dtsi" - -/ { - model = "Logic PD i.MX6QD SOM-M3"; - compatible = "fsl,imx6q"; - - backlight: backlight-lvds { - compatible = "pwm-backlight"; - pwms = <&pwm3 0 20000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - power-supply = <®_lcd>; - }; - - panel-lvds0 { - compatible = "okaya,rs800480t-7x0gp"; - power-supply = <®_lcd_reset>; - backlight = <&backlight>; - - port { - panel_in_lvds0: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - }; - - reg_lcd: regulator-lcd { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd_reg>; - compatible = "regulator-fixed"; - regulator-name = "lcd_panel_pwr"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio4 17 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <®_3v3>; - startup-delay-us = <500000>; - }; - - reg_lcd_reset: regulator-lcd-reset { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd_reset>; - compatible = "regulator-fixed"; - regulator-name = "nLCD_RESET"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <®_lcd>; - }; -}; - -&clks { - assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, - <&clks IMX6QDL_CLK_LDB_DI1_SEL>, - <&clks IMX6QDL_CLK_IPU1_DI0_PRE_SEL>, - <&clks IMX6QDL_CLK_IPU2_DI0_PRE_SEL>; - assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>, - <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>, - <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, - <&clks IMX6QDL_CLK_PLL2_PFD2_396M>; -}; - -&hdmi { - ddc-i2c-bus = <&i2c3>; - status = "okay"; -}; - -&i2c1 { - touchscreen@26 { - compatible = "ilitek,ili2117"; - reg = <0x26>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_touchscreen>; - interrupts-extended = <&gpio1 6 IRQ_TYPE_EDGE_RISING>; - }; -}; - -&ldb { - status = "okay"; - - lvds-channel@0 { - fsl,data-mapping = "spwg"; - fsl,data-width = <24>; - status = "okay"; - - port@4 { - reg = <4>; - lvds0_out: endpoint { - remote-endpoint = <&panel_in_lvds0>; - }; - }; - }; - -}; - -&pwm3 { - status = "okay"; -}; - -®_hdmi { - regulator-always-on; /* Without this, the level shifter on HDMI doesn't turn on */ -}; - -&iomuxc { - pinctrl_lcd_reg: lcdreg { - fsl,pins = < - MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x100b0 /* R_LCD_PANEL_PWR */ - >; - }; - - pinctrl_lcd_reset: lcdreset { - fsl,pins = < - MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b0 /* LCD_nRESET */ - >; - }; - - pinctrl_touchscreen: touchscreengrp { - fsl,pins = < - MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0 /* TOUCH_nPINTDAV */ - >; - }; -}; diff --git a/sys/gnu/dts/arm/imx6q-marsboard.dts b/sys/gnu/dts/arm/imx6q-marsboard.dts deleted file mode 100644 index 84b30bd6908..00000000000 --- a/sys/gnu/dts/arm/imx6q-marsboard.dts +++ /dev/null @@ -1,403 +0,0 @@ -/* - * Copyright (C) 2016 Sergio Prado (sergio.prado@e-labworks.com) - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6q.dtsi" -#include - -/ { - model = "Embest MarS Board i.MX6Dual"; - compatible = "embest,imx6q-marsboard", "fsl,imx6q"; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x40000000>; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_usb_otg_vbus: regulator-usb-otg-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_led>; - - user1 { - label = "imx6:green:user1"; - gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; - default-state = "off"; - linux,default-trigger = "heartbeat"; - }; - - user2 { - label = "imx6:green:user2"; - gpios = <&gpio3 28 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; - -&ecspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>; - status = "okay"; - - m25p80@0 { - compatible = "microchip,sst25vf016b"; - spi-max-frequency = <20000000>; - reg = <0>; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii-id"; - phy-reset-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c2>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "okay"; -}; - -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm2>; - status = "okay"; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; - status = "okay"; -}; - -&pwm4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm4>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - status = "okay"; -}; - -&usbh1 { - dr_mode = "host"; - disable-over-current; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - dr_mode = "otg"; - disable-over-current; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - vmmc-supply = <®_3p3v>; - cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - vmmc-supply = <®_3p3v>; - non-removable; - status = "okay"; -}; - -&iomuxc { - - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 - MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 - MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 - MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* CAM_MCLK */ - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 - MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x000b1 /* CS0 */ - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */ - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x0a0b1 - /* AR8035 pin strapping: IO voltage: pull up */ - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - /* AR8035 pin strapping: PHYADDR#0: pull down */ - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x13030 - /* AR8035 pin strapping: PHYADDR#1: pull down */ - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030 - /* AR8035 pin strapping: MODE#1: pull up */ - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - /* AR8035 pin strapping: MODE#3: pull up */ - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - /* AR8035 pin strapping: MODE#0: pull down */ - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030 - /* GPIO16 -> AR8035 25MHz */ - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - /* RGMII_nRST */ - MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x130b0 - /* AR8035 interrupt */ - MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x180b0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 - MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_led: ledgrp { - fsl,pins = < - MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b1 /* LED1 */ - MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x1b0b1 /* LED2 */ - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm4: pwm4grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 - MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0 - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x000b0 /* USB OTG POWER ENABLE */ - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* CD */ - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1f0b0 /* WP */ - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17009 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10009 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17009 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17009 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17009 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17009 - MX6QDL_PAD_SD3_RST__SD3_RESET 0x17009 - >; - }; -}; diff --git a/sys/gnu/dts/arm/imx6q-mccmon6.dts b/sys/gnu/dts/arm/imx6q-mccmon6.dts deleted file mode 100644 index a4d295455e6..00000000000 --- a/sys/gnu/dts/arm/imx6q-mccmon6.dts +++ /dev/null @@ -1,470 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright 2016-2017 - * Lukasz Majewski, DENX Software Engineering, lukma@denx.de - */ - -/dts-v1/; - -#include "imx6q.dtsi" - -#include -#include - -/ { - model = "Liebherr (LWN) monitor6 i.MX6 Quad Board"; - compatible = "lwn,mccmon6", "fsl,imx6q"; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x80000000>; - }; - - backlight_lvds: backlight { - compatible = "pwm-backlight"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_backlight>; - pwms = <&pwm2 0 5000000 PWM_POLARITY_INVERTED>; - brightness-levels = < 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100 101 102 103 104 105 106 107 108 109 - 110 111 112 113 114 115 116 117 118 119 - 120 121 122 123 124 125 126 127 128 129 - 130 131 132 133 134 135 136 137 138 139 - 140 141 142 143 144 145 146 147 148 149 - 150 151 152 153 154 155 156 157 158 159 - 160 161 162 163 164 165 166 167 168 169 - 170 171 172 173 174 175 176 177 178 179 - 180 181 182 183 184 185 186 187 188 189 - 190 191 192 193 194 195 196 197 198 199 - 200 201 202 203 204 205 206 207 208 209 - 210 211 212 213 214 215 216 217 218 219 - 220 221 222 223 224 225 226 227 228 229 - 230 231 232 233 234 235 236 237 238 239 - 240 241 242 243 244 245 246 247 248 249 - 250 251 252 253 254 255>; - default-brightness-level = <50>; - enable-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; - }; - - reg_lvds: regulator-lvds { - compatible = "regulator-fixed"; - regulator-name = "lvds_ppen"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_lvds>; - gpio = <&gpio1 19 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - panel-lvds0 { - compatible = "innolux,g121x1-l03"; - backlight = <&backlight_lvds>; - power-supply = <®_lvds>; - - port { - panel_in_lvds0: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - }; -}; - -&ecspi3 { - cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3_cs &pinctrl_ecspi3_flwp>; - status = "okay"; - - s25sl032p: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - spi-max-frequency = <40000000>; - reg = <0>; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii"; - phy-reset-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>; - interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, - <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - pfuze100: pmic@8 { - compatible = "fsl,pfuze100"; - reg = <0x08>; - - regulators { - sw1a_reg: sw1ab { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw1c_reg: sw1c { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3950000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3a_reg: sw3a { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3b_reg: sw3b { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - sw4_reg: sw4 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - }; - - swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - }; - - snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - vgen1_reg: vgen1 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen2_reg: vgen2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen3_reg: vgen3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - vgen4_reg: vgen4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen5_reg: vgen5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen6_reg: vgen6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; -}; - -&ldb { - status = "okay"; - - lvds0: lvds-channel@0 { - fsl,data-mapping = "spwg"; - fsl,data-width = <24>; - status = "okay"; - - port@4 { - reg = <4>; - - lvds0_out: endpoint { - remote-endpoint = <&panel_in_lvds0>; - }; - }; - }; -}; - -&pwm2 { - #pwm-cells = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm2>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - uart-has-rtscts; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - bus-width = <4>; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&weim { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_weim_nor &pinctrl_weim_cs0>; - ranges = <0 0 0x08000000 0x08000000>; - status = "okay"; - - nor@0,0 { - compatible = "cfi-flash"; - reg = <0 0 0x02000000>; - #address-cells = <1>; - #size-cells = <1>; - bank-width = <2>; - use-advanced-sector-protection; - fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000 - 0x0000c000 0x1404a38e 0x00000000>; - }; -}; - -&iomuxc { - pinctrl-names = "default"; - - pinctrl_backlight: dispgrp { - fsl,pins = < - /* BLEN_OUT */ - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 - >; - }; - - pinctrl_ecspi3: ecspi3grp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 - MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 - MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 - >; - }; - - pinctrl_ecspi3_cs: ecspi3csgrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 - >; - }; - - pinctrl_ecspi3_flwp: ecspi3flwpgrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x80000000 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 - MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1b0b0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1 - >; - }; - - pinctrl_reg_lvds: reqlvdsgrp { - fsl,pins = < - /* LVDS_PPEN_OUT */ - MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x1b0b0 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1 - MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b1 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 - MX6QDL_PAD_SD3_RST__SD3_RESET 0x17059 - >; - }; - - pinctrl_weim_cs0: weimcs0grp { - fsl,pins = < - MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1 - >; - }; - - pinctrl_weim_nor: weimnorgrp { - fsl,pins = < - MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1 - MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1 - MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060 - MX6QDL_PAD_EIM_D16__EIM_DATA16 0x1b0b0 - MX6QDL_PAD_EIM_D17__EIM_DATA17 0x1b0b0 - MX6QDL_PAD_EIM_D18__EIM_DATA18 0x1b0b0 - MX6QDL_PAD_EIM_D19__EIM_DATA19 0x1b0b0 - MX6QDL_PAD_EIM_D20__EIM_DATA20 0x1b0b0 - MX6QDL_PAD_EIM_D21__EIM_DATA21 0x1b0b0 - MX6QDL_PAD_EIM_D22__EIM_DATA22 0x1b0b0 - MX6QDL_PAD_EIM_D23__EIM_DATA23 0x1b0b0 - MX6QDL_PAD_EIM_D24__EIM_DATA24 0x1b0b0 - MX6QDL_PAD_EIM_D25__EIM_DATA25 0x1b0b0 - MX6QDL_PAD_EIM_D26__EIM_DATA26 0x1b0b0 - MX6QDL_PAD_EIM_D27__EIM_DATA27 0x1b0b0 - MX6QDL_PAD_EIM_D28__EIM_DATA28 0x1b0b0 - MX6QDL_PAD_EIM_D29__EIM_DATA29 0x1b0b0 - MX6QDL_PAD_EIM_D30__EIM_DATA30 0x1b0b0 - MX6QDL_PAD_EIM_D31__EIM_DATA31 0x1b0b0 - MX6QDL_PAD_EIM_A23__EIM_ADDR23 0xb0b1 - MX6QDL_PAD_EIM_A22__EIM_ADDR22 0xb0b1 - MX6QDL_PAD_EIM_A21__EIM_ADDR21 0xb0b1 - MX6QDL_PAD_EIM_A20__EIM_ADDR20 0xb0b1 - MX6QDL_PAD_EIM_A19__EIM_ADDR19 0xb0b1 - MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0b1 - MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0b1 - MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0b1 - MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1 - MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1 - MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1 - MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1 - MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1 - MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1 - MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1 - MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1 - MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1 - MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1 - MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1 - MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1 - MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1 - MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1 - MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1 - MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1 - >; - }; -}; diff --git a/sys/gnu/dts/arm/imx6q-nitrogen6_max.dts b/sys/gnu/dts/arm/imx6q-nitrogen6_max.dts deleted file mode 100644 index 03bec0c5306..00000000000 --- a/sys/gnu/dts/arm/imx6q-nitrogen6_max.dts +++ /dev/null @@ -1,17 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR X11 -/* - * Copyright 2015 Boundary Devices, Inc. - */ -/dts-v1/; - -#include "imx6q.dtsi" -#include "imx6qdl-nitrogen6_max.dtsi" - -/ { - model = "Boundary Devices i.MX6 Quad Nitrogen6_MAX Board"; - compatible = "boundary,imx6q-nitrogen6_max", "fsl,imx6q"; -}; - -&sata { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx6q-nitrogen6_som2.dts b/sys/gnu/dts/arm/imx6q-nitrogen6_som2.dts deleted file mode 100644 index eb4eecb6ed2..00000000000 --- a/sys/gnu/dts/arm/imx6q-nitrogen6_som2.dts +++ /dev/null @@ -1,17 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR X11 -/* - * Copyright 2016 Boundary Devices, Inc. - */ -/dts-v1/; - -#include "imx6q.dtsi" -#include "imx6qdl-nitrogen6_som2.dtsi" - -/ { - model = "Boundary Devices i.MX6 Quad Nitrogen6_SOM2 Board"; - compatible = "boundary,imx6q-nitrogen6_som2", "fsl,imx6q"; -}; - -&sata { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx6q-nitrogen6x.dts b/sys/gnu/dts/arm/imx6q-nitrogen6x.dts deleted file mode 100644 index 435445a34ad..00000000000 --- a/sys/gnu/dts/arm/imx6q-nitrogen6x.dts +++ /dev/null @@ -1,19 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR X11 -/* - * Copyright 2013 Boundary Devices, Inc. - * Copyright 2012 Freescale Semiconductor, Inc. - * Copyright 2011 Linaro Ltd. - */ - -/dts-v1/; -#include "imx6q.dtsi" -#include "imx6qdl-nitrogen6x.dtsi" - -/ { - model = "Boundary Devices i.MX6 Quad Nitrogen6x Board"; - compatible = "boundary,imx6q-nitrogen6x", "fsl,imx6q"; -}; - -&sata { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx6q-novena.dts b/sys/gnu/dts/arm/imx6q-novena.dts deleted file mode 100644 index 61347a545d6..00000000000 --- a/sys/gnu/dts/arm/imx6q-novena.dts +++ /dev/null @@ -1,792 +0,0 @@ -/* - * Copyright 2015 Sutajio Ko-Usagi PTE LTD - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - -/dts-v1/; -#include "imx6q.dtsi" -#include -#include - -/ { - model = "Kosagi Novena Dual/Quad"; - compatible = "kosagi,imx6q-novena", "fsl,imx6q"; - - /* Will be filled by the bootloader */ - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0>; - }; - - chosen { - stdout-path = &uart2; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 10000000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_backlight_novena>; - power-supply = <®_lvds_lcd>; - brightness-levels = <0 3 6 12 16 24 32 48 64 96 128 192 255>; - default-brightness-level = <12>; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_keys_novena>; - - user-button { - label = "User Button"; - gpios = <&gpio4 14 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - lid { - label = "Lid"; - gpios = <&gpio4 12 GPIO_ACTIVE_LOW>; - linux,input-type = <5>; /* EV_SW */ - linux,code = <0>; /* SW_LID */ - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_leds_novena>; - - heartbeat { - label = "novena:white:panel"; - gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - }; - }; - - panel: panel { - compatible = "innolux,n133hse-ea1", "simple-panel"; - backlight = <&backlight>; - }; - - reg_2p5v: regulator-2p5v { - compatible = "regulator-fixed"; - regulator-name = "2P5V"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_audio_codec: regulator-audio-codec { - compatible = "regulator-fixed"; - regulator-name = "es8328-power"; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - startup-delay-us = <400000>; - gpio = <&gpio5 17 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_display: regulator-display { - compatible = "regulator-fixed"; - regulator-name = "lcd-display-power"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <200000>; - gpio = <&gpio5 28 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_lvds_lcd: regulator-lvds-lcd { - compatible = "regulator-fixed"; - regulator-name = "lcd-lvds-power"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_pcie: regulator-pcie { - compatible = "regulator-fixed"; - regulator-name = "pcie-bus-power"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_sata: regulator-sata { - compatible = "regulator-fixed"; - regulator-name = "sata-power"; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <10000>; - gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usb_otg_vbus: regulator-usb-otg-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - }; - - sound { - compatible = "fsl,imx-audio-es8328"; - model = "imx-audio-es8328"; - ssi-controller = <&ssi1>; - audio-codec = <&codec>; - audio-amp-supply = <®_audio_codec>; - jack-gpio = <&gpio5 15 GPIO_ACTIVE_HIGH>; - audio-routing = - "Speaker", "LOUT2", - "Speaker", "ROUT2", - "Speaker", "audio-amp", - "Headphone", "ROUT1", - "Headphone", "LOUT1", - "LINPUT1", "Mic Jack", - "RINPUT1", "Mic Jack", - "Mic Jack", "Mic Bias"; - mux-int-port = <0x1>; - mux-ext-port = <0x3>; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux_novena>; - status = "okay"; -}; - -&ecspi3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi3_novena>; - status = "okay"; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet_novena>; - phy-mode = "rgmii"; - phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; - rxc-skew-ps = <3000>; - rxdv-skew-ps = <0>; - txc-skew-ps = <3000>; - txen-skew-ps = <0>; - rxd0-skew-ps = <0>; - rxd1-skew-ps = <0>; - rxd2-skew-ps = <0>; - rxd3-skew-ps = <0>; - txd0-skew-ps = <3000>; - txd1-skew-ps = <3000>; - txd2-skew-ps = <3000>; - txd3-skew-ps = <3000>; - status = "okay"; -}; - -&hdmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hdmi_novena>; - ddc-i2c-bus = <&i2c2>; - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1_novena>; - status = "okay"; - - accel: mma8452@1c { - compatible = "fsl,mma8452"; - reg = <0x1c>; - }; - - rtc: pcf8523@68 { - compatible = "nxp,pcf8523"; - reg = <0x68>; - }; - - sbs_battery: bq20z75@b { - compatible = "sbs,sbs-battery"; - reg = <0x0b>; - sbs,i2c-retry-count = <50>; - }; - - touch: stmpe811@44 { - compatible = "st,stmpe811"; - reg = <0x44>; - irq-gpio = <&gpio5 13 GPIO_ACTIVE_HIGH>; - id = <0>; - blocks = <0x5>; - irq-trigger = <0x1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_stmpe_novena>; - vio-supply = <®_3p3v>; - vcc-supply = <®_3p3v>; - - stmpe_touchscreen { - compatible = "st,stmpe-ts"; - st,sample-time = <4>; - st,mod-12b = <1>; - st,ref-sel = <0>; - st,adc-freq = <1>; - st,ave-ctrl = <1>; - st,touch-det-delay = <2>; - st,settling = <2>; - st,fraction-z = <7>; - st,i-drive = <1>; - }; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2_novena>; - status = "okay"; - - pmic: pfuze100@8 { - compatible = "fsl,pfuze100"; - reg = <0x08>; - - regulators { - reg_sw1a: sw1a { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - reg_sw1c: sw1c { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_sw2: sw2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_sw3a: sw3a { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_sw3b: sw3b { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_sw4: sw4 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - }; - - reg_swbst: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - regulator-boot-on; - }; - - reg_snvs: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_vref: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - reg_vgen1: vgen1 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - reg_vgen2: vgen2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - reg_vgen3: vgen3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - reg_vgen4: vgen4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_vgen5: vgen5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_vgen6: vgen6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3_novena>; - status = "okay"; - - codec: es8328@11 { - compatible = "everest,es8328"; - reg = <0x11>; - DVDD-supply = <®_audio_codec>; - AVDD-supply = <®_audio_codec>; - PVDD-supply = <®_audio_codec>; - HPVDD-supply = <®_audio_codec>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sound_novena>; - clocks = <&clks IMX6QDL_CLK_CKO1>; - assigned-clocks = <&clks IMX6QDL_CLK_CKO>, - <&clks IMX6QDL_CLK_CKO1_SEL>, - <&clks IMX6QDL_CLK_PLL4_AUDIO>, - <&clks IMX6QDL_CLK_CKO1>; - assigned-clock-parents = <&clks IMX6QDL_CLK_CKO1>, - <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>, - <&clks IMX6QDL_CLK_OSC>, - <&clks IMX6QDL_CLK_CKO1_PODF>; - assigned-clock-rates = <0 0 722534400 22579200>; - }; -}; - -&kpp { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_kpp_novena>; - linux,keymap = < - MATRIX_KEY(1, 1, KEY_CONFIG) - >; - status = "okay"; -}; - -&ldb { - fsl,dual-channel; - status = "okay"; - - lvds-channel@0 { - fsl,data-mapping = "jeida"; - fsl,data-width = <24>; - fsl,panel = <&panel>; - status = "okay"; - }; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie_novena>; - reset-gpio = <&gpio3 29 GPIO_ACTIVE_LOW>; - vpcie-supply = <®_pcie>; - status = "okay"; -}; - -&pwm1 { - status = "okay"; -}; - -&sata { - target-supply = <®_sata>; - fsl,transmit-level-mV = <1025>; - fsl,transmit-boost-mdB = <0>; - fsl,transmit-atten-16ths = <8>; - status = "okay"; -}; - -&ssi1 { - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2_novena>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3_novena>; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4_novena>; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - dr_mode = "otg"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg_novena>; - disable-over-current; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_swbst>; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2_novena>; - cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; - bus-width = <4>; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3_novena>; - bus-width = <4>; - non-removable; - status = "okay"; -}; - -&iomuxc { - pinctrl_audmux_novena: audmuxgrp-novena { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 - MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 - MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 - MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 - >; - }; - - pinctrl_backlight_novena: backlightgrp-novena { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b0 - MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x1b0b1 - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b1 - >; - }; - - pinctrl_ecspi3_novena: ecspi3grp-novena { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 - MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 - MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 - >; - }; - - pinctrl_enet_novena: enetgrp-novena { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b020 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b028 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b028 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b028 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b028 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b028 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - /* Ethernet reset */ - MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b0b1 - >; - }; - - pinctrl_fpga_gpio: fpgagpiogrp-novena { - fsl,pins = < - /* FPGA power */ - MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b0b1 - /* Reset */ - MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07 0x1b0b1 - /* FPGA GPIOs */ - MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x1b0b1 - MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x1b0b1 - MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x1b0b1 - MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x1b0b1 - MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x1b0b1 - MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x1b0b1 - MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x1b0b1 - MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x1b0b1 - MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x1b0b1 - MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x1b0b1 - MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x1b0b1 - MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0x1b0b1 - MX6QDL_PAD_EIM_DA12__GPIO3_IO12 0x1b0b1 - MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x1b0b1 - MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x1b0b1 - MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x1b0b1 - MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b1 - MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b1 - MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b1 - MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x1b0b1 - MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x1b0b1 - MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b1 - MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x1b0b1 - MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x1b0b1 - MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1b0b1 - MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b1 - >; - }; - - pinctrl_fpga_eim: fpgaeimgrp-novena { - fsl,pins = < - /* FPGA power */ - MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b0b1 - /* Reset */ - MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07 0x1b0b1 - /* FPGA GPIOs */ - MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0f1 - MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0f1 - MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0f1 - MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0f1 - MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0f1 - MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0f1 - MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0f1 - MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0f1 - MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0f1 - MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0f1 - MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0f1 - MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0f1 - MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0f1 - MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0f1 - MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0f1 - MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0f1 - MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0f1 - MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0f1 - MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0f1 - MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0f1 - MX6QDL_PAD_EIM_CS1__EIM_CS1_B 0xb0f1 - MX6QDL_PAD_EIM_LBA__EIM_LBA_B 0xb0f1 - MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0f1 - MX6QDL_PAD_EIM_RW__EIM_RW 0xb0f1 - MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb0f1 - MX6QDL_PAD_EIM_BCLK__EIM_BCLK 0xb0f1 - >; - }; - - pinctrl_gpio_keys_novena: gpiokeysgrp-novena { - fsl,pins = < - /* User button */ - MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 - /* PCIe Wakeup */ - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1f0e0 - /* Lid switch */ - MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x1b0b0 - >; - }; - - pinctrl_hdmi_novena: hdmigrp-novena { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 - MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x1b0b1 - >; - }; - - pinctrl_i2c1_novena: i2c1grp-novena { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c2_novena: i2c2grp-novena { - fsl,pins = < - MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3_novena: i2c3grp-novena { - fsl,pins = < - MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_kpp_novena: kppgrp-novena { - fsl,pins = < - /* Front panel button */ - MX6QDL_PAD_KEY_ROW1__KEY_ROW1 0x1b0b1 - /* Fake column driver, not connected */ - MX6QDL_PAD_KEY_COL1__KEY_COL1 0x1b0b1 - >; - }; - - pinctrl_leds_novena: ledsgrp-novena { - fsl,pins = < - MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x1b0b1 - >; - }; - - pinctrl_pcie_novena: pciegrp-novena { - fsl,pins = < - /* Reset */ - MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b1 - /* Power On */ - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b1 - /* Wifi kill */ - MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x1b0b1 - >; - }; - - pinctrl_sata_novena: satagrp-novena { - fsl,pins = < - MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x1b0b1 - >; - }; - - pinctrl_senoko_novena: senokogrp-novena { - fsl,pins = < - /* Senoko IRQ line */ - MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x13048 - /* Senoko reset line */ - MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1b0b1 - >; - }; - - pinctrl_sound_novena: soundgrp-novena { - fsl,pins = < - /* Audio power regulator */ - MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b1 - /* Headphone plug */ - MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1b0b1 - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 - >; - }; - - pinctrl_stmpe_novena: stmpegrp-novena { - fsl,pins = < - /* Touchscreen interrupt */ - MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b1 - >; - }; - - pinctrl_uart2_novena: uart2grp-novena { - fsl,pins = < - MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart3_novena: uart3grp-novena { - fsl,pins = < - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart4_novena: uart4grp-novena { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg_novena: usbotggrp-novena { - fsl,pins = < - MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 - >; - }; - - pinctrl_usdhc2_novena: usdhc2grp-novena { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170f9 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100f9 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170f9 - /* Write protect */ - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b1 - /* Card detect */ - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b1 - >; - }; - - pinctrl_usdhc3_novena: usdhc3grp-novena { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 - >; - }; -}; diff --git a/sys/gnu/dts/arm/imx6q-phytec-mira-rdk-emmc.dts b/sys/gnu/dts/arm/imx6q-phytec-mira-rdk-emmc.dts deleted file mode 100644 index 2e70ea5623c..00000000000 --- a/sys/gnu/dts/arm/imx6q-phytec-mira-rdk-emmc.dts +++ /dev/null @@ -1,72 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2018 PHYTEC Messtechnik GmbH - * Author: Christian Hemp - */ - -/dts-v1/; -#include "imx6q.dtsi" -#include "imx6qdl-phytec-phycore-som.dtsi" -#include "imx6qdl-phytec-mira.dtsi" - -/ { - model = "PHYTEC phyBOARD-Mira Quad Carrier-Board with eMMC"; - compatible = "phytec,imx6q-pbac06-emmc", "phytec,imx6q-pbac06", - "phytec,imx6qdl-pcm058", "fsl,imx6q"; - - chosen { - stdout-path = &uart2; - }; -}; - -&can1 { - status = "okay"; -}; - -&fec { - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c_rtc { - status = "okay"; -}; - -&m25p80 { - status = "okay"; -}; - -&pcie { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&usbh1 { - status = "okay"; -}; - -&usbotg { - status = "okay"; -}; - -&usdhc1 { - status = "okay"; -}; - -&usdhc4 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx6q-phytec-mira-rdk-nand.dts b/sys/gnu/dts/arm/imx6q-phytec-mira-rdk-nand.dts deleted file mode 100644 index 65d2e483c13..00000000000 --- a/sys/gnu/dts/arm/imx6q-phytec-mira-rdk-nand.dts +++ /dev/null @@ -1,72 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2018 PHYTEC Messtechnik GmbH - * Author: Christian Hemp - */ - -/dts-v1/; -#include "imx6q.dtsi" -#include "imx6qdl-phytec-phycore-som.dtsi" -#include "imx6qdl-phytec-mira.dtsi" - -/ { - model = "PHYTEC phyBOARD-Mira Quad Carrier-Board with NAND"; - compatible = "phytec,imx6q-pbac06-nand", "phytec,imx6q-pbac06", - "phytec,imx6qdl-pcm058", "fsl,imx6q"; - - chosen { - stdout-path = &uart2; - }; -}; - -&can1 { - status = "okay"; -}; - -&fec { - status = "okay"; -}; - -&gpmi { - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c_rtc { - status = "okay"; -}; - -&m25p80 { - status = "okay"; -}; - -&pcie { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&usbh1 { - status = "okay"; -}; - -&usbotg { - status = "okay"; -}; - -&usdhc1 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx6q-phytec-pbab01.dts b/sys/gnu/dts/arm/imx6q-phytec-pbab01.dts deleted file mode 100644 index affe30b02d5..00000000000 --- a/sys/gnu/dts/arm/imx6q-phytec-pbab01.dts +++ /dev/null @@ -1,21 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH - */ - -/dts-v1/; -#include "imx6q-phytec-pfla02.dtsi" -#include "imx6qdl-phytec-pbab01.dtsi" - -/ { - model = "Phytec phyFLEX-i.MX6 Quad Carrier-Board"; - compatible = "phytec,imx6q-pbab01", "phytec,imx6q-pfla02", "fsl,imx6q"; - - chosen { - stdout-path = &uart4; - }; -}; - -&sata { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx6q-phytec-pfla02.dtsi b/sys/gnu/dts/arm/imx6q-phytec-pfla02.dtsi deleted file mode 100644 index 500944bd2a0..00000000000 --- a/sys/gnu/dts/arm/imx6q-phytec-pfla02.dtsi +++ /dev/null @@ -1,17 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH - */ - -#include "imx6q.dtsi" -#include "imx6qdl-phytec-pfla02.dtsi" - -/ { - model = "Phytec phyFLEX-i.MX6 Quad"; - compatible = "phytec,imx6q-pfla02", "fsl,imx6q"; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x80000000>; - }; -}; diff --git a/sys/gnu/dts/arm/imx6q-pinfunc.h b/sys/gnu/dts/arm/imx6q-pinfunc.h deleted file mode 100644 index e40409d04b9..00000000000 --- a/sys/gnu/dts/arm/imx6q-pinfunc.h +++ /dev/null @@ -1,1044 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - */ - -#ifndef __DTS_IMX6Q_PINFUNC_H -#define __DTS_IMX6Q_PINFUNC_H - -/* - * The pin function ID is a tuple of - * - */ -#define MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x04c 0x360 0x000 0x0 0x0 -#define MX6QDL_PAD_SD2_DAT1__ECSPI5_SS0 0x04c 0x360 0x834 0x1 0x0 -#define MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0x04c 0x360 0x000 0x2 0x0 -#define MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x04c 0x360 0x7c8 0x3 0x0 -#define MX6QDL_PAD_SD2_DAT1__KEY_COL7 0x04c 0x360 0x8f0 0x4 0x0 -#define MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x04c 0x360 0x000 0x5 0x0 -#define MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x050 0x364 0x000 0x0 0x0 -#define MX6QDL_PAD_SD2_DAT2__ECSPI5_SS1 0x050 0x364 0x838 0x1 0x0 -#define MX6QDL_PAD_SD2_DAT2__EIM_CS3_B 0x050 0x364 0x000 0x2 0x0 -#define MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x050 0x364 0x7b8 0x3 0x0 -#define MX6QDL_PAD_SD2_DAT2__KEY_ROW6 0x050 0x364 0x8f8 0x4 0x0 -#define MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x050 0x364 0x000 0x5 0x0 -#define MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x054 0x368 0x000 0x0 0x0 -#define MX6QDL_PAD_SD2_DAT0__ECSPI5_MISO 0x054 0x368 0x82c 0x1 0x0 -#define MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x054 0x368 0x7b4 0x3 0x0 -#define MX6QDL_PAD_SD2_DAT0__KEY_ROW7 0x054 0x368 0x8fc 0x4 0x0 -#define MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x054 0x368 0x000 0x5 0x0 -#define MX6QDL_PAD_SD2_DAT0__DCIC2_OUT 0x054 0x368 0x000 0x6 0x0 -#define MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x058 0x36c 0x000 0x0 0x0 -#define MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x058 0x36c 0x000 0x1 0x0 -#define MX6QDL_PAD_RGMII_TXC__SPDIF_EXT_CLK 0x058 0x36c 0x918 0x2 0x0 -#define MX6QDL_PAD_RGMII_TXC__GPIO6_IO19 0x058 0x36c 0x000 0x5 0x0 -#define MX6QDL_PAD_RGMII_TXC__XTALOSC_REF_CLK_24M 0x058 0x36c 0x000 0x7 0x0 -#define MX6QDL_PAD_RGMII_TD0__HSI_TX_READY 0x05c 0x370 0x000 0x0 0x0 -#define MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x05c 0x370 0x000 0x1 0x0 -#define MX6QDL_PAD_RGMII_TD0__GPIO6_IO20 0x05c 0x370 0x000 0x5 0x0 -#define MX6QDL_PAD_RGMII_TD1__HSI_RX_FLAG 0x060 0x374 0x000 0x0 0x0 -#define MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x060 0x374 0x000 0x1 0x0 -#define MX6QDL_PAD_RGMII_TD1__GPIO6_IO21 0x060 0x374 0x000 0x5 0x0 -#define MX6QDL_PAD_RGMII_TD2__HSI_RX_DATA 0x064 0x378 0x000 0x0 0x0 -#define MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x064 0x378 0x000 0x1 0x0 -#define MX6QDL_PAD_RGMII_TD2__GPIO6_IO22 0x064 0x378 0x000 0x5 0x0 -#define MX6QDL_PAD_RGMII_TD3__HSI_RX_WAKE 0x068 0x37c 0x000 0x0 0x0 -#define MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x068 0x37c 0x000 0x1 0x0 -#define MX6QDL_PAD_RGMII_TD3__GPIO6_IO23 0x068 0x37c 0x000 0x5 0x0 -#define MX6QDL_PAD_RGMII_RX_CTL__USB_H3_DATA 0x06c 0x380 0x000 0x0 0x0 -#define MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x06c 0x380 0x858 0x1 0x0 -#define MX6QDL_PAD_RGMII_RX_CTL__GPIO6_IO24 0x06c 0x380 0x000 0x5 0x0 -#define MX6QDL_PAD_RGMII_RD0__HSI_RX_READY 0x070 0x384 0x000 0x0 0x0 -#define MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x070 0x384 0x848 0x1 0x0 -#define MX6QDL_PAD_RGMII_RD0__GPIO6_IO25 0x070 0x384 0x000 0x5 0x0 -#define MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x074 0x388 0x000 0x0 0x0 -#define MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x074 0x388 0x000 0x1 0x0 -#define MX6QDL_PAD_RGMII_TX_CTL__GPIO6_IO26 0x074 0x388 0x000 0x5 0x0 -#define MX6QDL_PAD_RGMII_TX_CTL__ENET_REF_CLK 0x074 0x388 0x83c 0x7 0x0 -#define MX6QDL_PAD_RGMII_RD1__HSI_TX_FLAG 0x078 0x38c 0x000 0x0 0x0 -#define MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x078 0x38c 0x84c 0x1 0x0 -#define MX6QDL_PAD_RGMII_RD1__GPIO6_IO27 0x078 0x38c 0x000 0x5 0x0 -#define MX6QDL_PAD_RGMII_RD2__HSI_TX_DATA 0x07c 0x390 0x000 0x0 0x0 -#define MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x07c 0x390 0x850 0x1 0x0 -#define MX6QDL_PAD_RGMII_RD2__GPIO6_IO28 0x07c 0x390 0x000 0x5 0x0 -#define MX6QDL_PAD_RGMII_RD3__HSI_TX_WAKE 0x080 0x394 0x000 0x0 0x0 -#define MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x080 0x394 0x854 0x1 0x0 -#define MX6QDL_PAD_RGMII_RD3__GPIO6_IO29 0x080 0x394 0x000 0x5 0x0 -#define MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x084 0x398 0x000 0x0 0x0 -#define MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x084 0x398 0x844 0x1 0x0 -#define MX6QDL_PAD_RGMII_RXC__GPIO6_IO30 0x084 0x398 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_A25__EIM_ADDR25 0x088 0x39c 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_A25__ECSPI4_SS1 0x088 0x39c 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_A25__ECSPI2_RDY 0x088 0x39c 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_A25__IPU1_DI1_PIN12 0x088 0x39c 0x000 0x3 0x0 -#define MX6QDL_PAD_EIM_A25__IPU1_DI0_D1_CS 0x088 0x39c 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x088 0x39c 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x088 0x39c 0x88c 0x6 0x0 -#define MX6QDL_PAD_EIM_EB2__EIM_EB2_B 0x08c 0x3a0 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_EB2__ECSPI1_SS0 0x08c 0x3a0 0x800 0x1 0x0 -#define MX6QDL_PAD_EIM_EB2__IPU2_CSI1_DATA19 0x08c 0x3a0 0x8d4 0x3 0x0 -#define MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x08c 0x3a0 0x890 0x4 0x0 -#define MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x08c 0x3a0 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x08c 0x3a0 0x8a0 0x6 0x0 -#define MX6QDL_PAD_EIM_EB2__SRC_BOOT_CFG30 0x08c 0x3a0 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_D16__EIM_DATA16 0x090 0x3a4 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x090 0x3a4 0x7f4 0x1 0x0 -#define MX6QDL_PAD_EIM_D16__IPU1_DI0_PIN05 0x090 0x3a4 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D16__IPU2_CSI1_DATA18 0x090 0x3a4 0x8d0 0x3 0x0 -#define MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x090 0x3a4 0x894 0x4 0x0 -#define MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x090 0x3a4 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D16__I2C2_SDA 0x090 0x3a4 0x8a4 0x6 0x0 -#define MX6QDL_PAD_EIM_D17__EIM_DATA17 0x094 0x3a8 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x094 0x3a8 0x7f8 0x1 0x0 -#define MX6QDL_PAD_EIM_D17__IPU1_DI0_PIN06 0x094 0x3a8 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D17__IPU2_CSI1_PIXCLK 0x094 0x3a8 0x8e0 0x3 0x0 -#define MX6QDL_PAD_EIM_D17__DCIC1_OUT 0x094 0x3a8 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D17__GPIO3_IO17 0x094 0x3a8 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D17__I2C3_SCL 0x094 0x3a8 0x8a8 0x6 0x0 -#define MX6QDL_PAD_EIM_D18__EIM_DATA18 0x098 0x3ac 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x098 0x3ac 0x7fc 0x1 0x0 -#define MX6QDL_PAD_EIM_D18__IPU1_DI0_PIN07 0x098 0x3ac 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D18__IPU2_CSI1_DATA17 0x098 0x3ac 0x8cc 0x3 0x0 -#define MX6QDL_PAD_EIM_D18__IPU1_DI1_D0_CS 0x098 0x3ac 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x098 0x3ac 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D18__I2C3_SDA 0x098 0x3ac 0x8ac 0x6 0x0 -#define MX6QDL_PAD_EIM_D19__EIM_DATA19 0x09c 0x3b0 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D19__ECSPI1_SS1 0x09c 0x3b0 0x804 0x1 0x0 -#define MX6QDL_PAD_EIM_D19__IPU1_DI0_PIN08 0x09c 0x3b0 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D19__IPU2_CSI1_DATA16 0x09c 0x3b0 0x8c8 0x3 0x0 -#define MX6QDL_PAD_EIM_D19__UART1_CTS_B 0x09c 0x3b0 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x09c 0x3b0 0x91c 0x4 0x0 -#define MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x09c 0x3b0 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D19__EPIT1_OUT 0x09c 0x3b0 0x000 0x6 0x0 -#define MX6QDL_PAD_EIM_D20__EIM_DATA20 0x0a0 0x3b4 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D20__ECSPI4_SS0 0x0a0 0x3b4 0x824 0x1 0x0 -#define MX6QDL_PAD_EIM_D20__IPU1_DI0_PIN16 0x0a0 0x3b4 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D20__IPU2_CSI1_DATA15 0x0a0 0x3b4 0x8c4 0x3 0x0 -#define MX6QDL_PAD_EIM_D20__UART1_RTS_B 0x0a0 0x3b4 0x91c 0x4 0x1 -#define MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x0a0 0x3b4 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x0a0 0x3b4 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D20__EPIT2_OUT 0x0a0 0x3b4 0x000 0x6 0x0 -#define MX6QDL_PAD_EIM_D21__EIM_DATA21 0x0a4 0x3b8 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x0a4 0x3b8 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_D21__IPU1_DI0_PIN17 0x0a4 0x3b8 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D21__IPU2_CSI1_DATA11 0x0a4 0x3b8 0x8b4 0x3 0x0 -#define MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x0a4 0x3b8 0x944 0x4 0x0 -#define MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x0a4 0x3b8 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D21__I2C1_SCL 0x0a4 0x3b8 0x898 0x6 0x0 -#define MX6QDL_PAD_EIM_D21__SPDIF_IN 0x0a4 0x3b8 0x914 0x7 0x0 -#define MX6QDL_PAD_EIM_D22__EIM_DATA22 0x0a8 0x3bc 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x0a8 0x3bc 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_D22__IPU1_DI0_PIN01 0x0a8 0x3bc 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D22__IPU2_CSI1_DATA10 0x0a8 0x3bc 0x8b0 0x3 0x0 -#define MX6QDL_PAD_EIM_D22__USB_OTG_PWR 0x0a8 0x3bc 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x0a8 0x3bc 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D22__SPDIF_OUT 0x0a8 0x3bc 0x000 0x6 0x0 -#define MX6QDL_PAD_EIM_D23__EIM_DATA23 0x0ac 0x3c0 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D23__IPU1_DI0_D0_CS 0x0ac 0x3c0 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x0ac 0x3c0 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D23__UART3_RTS_B 0x0ac 0x3c0 0x92c 0x2 0x0 -#define MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x0ac 0x3c0 0x000 0x3 0x0 -#define MX6QDL_PAD_EIM_D23__IPU2_CSI1_DATA_EN 0x0ac 0x3c0 0x8d8 0x4 0x0 -#define MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x0ac 0x3c0 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D23__IPU1_DI1_PIN02 0x0ac 0x3c0 0x000 0x6 0x0 -#define MX6QDL_PAD_EIM_D23__IPU1_DI1_PIN14 0x0ac 0x3c0 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_EB3__EIM_EB3_B 0x0b0 0x3c4 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_EB3__ECSPI4_RDY 0x0b0 0x3c4 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x0b0 0x3c4 0x92c 0x2 0x1 -#define MX6QDL_PAD_EIM_EB3__UART3_CTS_B 0x0b0 0x3c4 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_EB3__UART1_RI_B 0x0b0 0x3c4 0x000 0x3 0x0 -#define MX6QDL_PAD_EIM_EB3__IPU2_CSI1_HSYNC 0x0b0 0x3c4 0x8dc 0x4 0x0 -#define MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x0b0 0x3c4 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_EB3__IPU1_DI1_PIN03 0x0b0 0x3c4 0x000 0x6 0x0 -#define MX6QDL_PAD_EIM_EB3__SRC_BOOT_CFG31 0x0b0 0x3c4 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_D24__EIM_DATA24 0x0b4 0x3c8 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D24__ECSPI4_SS2 0x0b4 0x3c8 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x0b4 0x3c8 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D24__UART3_RX_DATA 0x0b4 0x3c8 0x930 0x2 0x0 -#define MX6QDL_PAD_EIM_D24__ECSPI1_SS2 0x0b4 0x3c8 0x808 0x3 0x0 -#define MX6QDL_PAD_EIM_D24__ECSPI2_SS2 0x0b4 0x3c8 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x0b4 0x3c8 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D24__AUD5_RXFS 0x0b4 0x3c8 0x7d8 0x6 0x0 -#define MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x0b4 0x3c8 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_D25__EIM_DATA25 0x0b8 0x3cc 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D25__ECSPI4_SS3 0x0b8 0x3cc 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x0b8 0x3cc 0x930 0x2 0x1 -#define MX6QDL_PAD_EIM_D25__UART3_TX_DATA 0x0b8 0x3cc 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D25__ECSPI1_SS3 0x0b8 0x3cc 0x80c 0x3 0x0 -#define MX6QDL_PAD_EIM_D25__ECSPI2_SS3 0x0b8 0x3cc 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x0b8 0x3cc 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D25__AUD5_RXC 0x0b8 0x3cc 0x7d4 0x6 0x0 -#define MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x0b8 0x3cc 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_D26__EIM_DATA26 0x0bc 0x3d0 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D26__IPU1_DI1_PIN11 0x0bc 0x3d0 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_D26__IPU1_CSI0_DATA01 0x0bc 0x3d0 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D26__IPU2_CSI1_DATA14 0x0bc 0x3d0 0x8c0 0x3 0x0 -#define MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x0bc 0x3d0 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x0bc 0x3d0 0x928 0x4 0x0 -#define MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x0bc 0x3d0 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D26__IPU1_SISG2 0x0bc 0x3d0 0x000 0x6 0x0 -#define MX6QDL_PAD_EIM_D26__IPU1_DISP1_DATA22 0x0bc 0x3d0 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_D27__EIM_DATA27 0x0c0 0x3d4 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D27__IPU1_DI1_PIN13 0x0c0 0x3d4 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_D27__IPU1_CSI0_DATA00 0x0c0 0x3d4 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D27__IPU2_CSI1_DATA13 0x0c0 0x3d4 0x8bc 0x3 0x0 -#define MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x0c0 0x3d4 0x928 0x4 0x1 -#define MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x0c0 0x3d4 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x0c0 0x3d4 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D27__IPU1_SISG3 0x0c0 0x3d4 0x000 0x6 0x0 -#define MX6QDL_PAD_EIM_D27__IPU1_DISP1_DATA23 0x0c0 0x3d4 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_D28__EIM_DATA28 0x0c4 0x3d8 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D28__I2C1_SDA 0x0c4 0x3d8 0x89c 0x1 0x0 -#define MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x0c4 0x3d8 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D28__IPU2_CSI1_DATA12 0x0c4 0x3d8 0x8b8 0x3 0x0 -#define MX6QDL_PAD_EIM_D28__UART2_CTS_B 0x0c4 0x3d8 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D28__UART2_RTS_B 0x0c4 0x3d8 0x924 0x4 0x0 -#define MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x0c4 0x3d8 0x924 0x4 0x0 -#define MX6QDL_PAD_EIM_D28__UART2_DTE_RTS_B 0x0c4 0x3d8 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x0c4 0x3d8 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D28__IPU1_EXT_TRIG 0x0c4 0x3d8 0x000 0x6 0x0 -#define MX6QDL_PAD_EIM_D28__IPU1_DI0_PIN13 0x0c4 0x3d8 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_D29__EIM_DATA29 0x0c8 0x3dc 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D29__IPU1_DI1_PIN15 0x0c8 0x3dc 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_D29__ECSPI4_SS0 0x0c8 0x3dc 0x824 0x2 0x1 -#define MX6QDL_PAD_EIM_D29__UART2_RTS_B 0x0c8 0x3dc 0x924 0x4 0x1 -#define MX6QDL_PAD_EIM_D29__UART2_CTS_B 0x0c8 0x3dc 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x0c8 0x3dc 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D29__UART2_DTE_CTS_B 0x0c8 0x3dc 0x924 0x4 0x1 -#define MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x0c8 0x3dc 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D29__IPU2_CSI1_VSYNC 0x0c8 0x3dc 0x8e4 0x6 0x0 -#define MX6QDL_PAD_EIM_D29__IPU1_DI0_PIN14 0x0c8 0x3dc 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_D30__EIM_DATA30 0x0cc 0x3e0 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D30__IPU1_DISP1_DATA21 0x0cc 0x3e0 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_D30__IPU1_DI0_PIN11 0x0cc 0x3e0 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D30__IPU1_CSI0_DATA03 0x0cc 0x3e0 0x000 0x3 0x0 -#define MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x0cc 0x3e0 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D30__UART3_RTS_B 0x0cc 0x3e0 0x92c 0x4 0x2 -#define MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x0cc 0x3e0 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D30__USB_H1_OC 0x0cc 0x3e0 0x948 0x6 0x0 -#define MX6QDL_PAD_EIM_D31__EIM_DATA31 0x0d0 0x3e4 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D31__IPU1_DISP1_DATA20 0x0d0 0x3e4 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_D31__IPU1_DI0_PIN12 0x0d0 0x3e4 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D31__IPU1_CSI0_DATA02 0x0d0 0x3e4 0x000 0x3 0x0 -#define MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x0d0 0x3e4 0x92c 0x4 0x3 -#define MX6QDL_PAD_EIM_D31__UART3_CTS_B 0x0d0 0x3e4 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x0d0 0x3e4 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D31__USB_H1_PWR 0x0d0 0x3e4 0x000 0x6 0x0 -#define MX6QDL_PAD_EIM_A24__EIM_ADDR24 0x0d4 0x3e8 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_A24__IPU1_DISP1_DATA19 0x0d4 0x3e8 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_A24__IPU2_CSI1_DATA19 0x0d4 0x3e8 0x8d4 0x2 0x1 -#define MX6QDL_PAD_EIM_A24__IPU2_SISG2 0x0d4 0x3e8 0x000 0x3 0x0 -#define MX6QDL_PAD_EIM_A24__IPU1_SISG2 0x0d4 0x3e8 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x0d4 0x3e8 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_A24__SRC_BOOT_CFG24 0x0d4 0x3e8 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_A23__EIM_ADDR23 0x0d8 0x3ec 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_A23__IPU1_DISP1_DATA18 0x0d8 0x3ec 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_A23__IPU2_CSI1_DATA18 0x0d8 0x3ec 0x8d0 0x2 0x1 -#define MX6QDL_PAD_EIM_A23__IPU2_SISG3 0x0d8 0x3ec 0x000 0x3 0x0 -#define MX6QDL_PAD_EIM_A23__IPU1_SISG3 0x0d8 0x3ec 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x0d8 0x3ec 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_A23__SRC_BOOT_CFG23 0x0d8 0x3ec 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_A22__EIM_ADDR22 0x0dc 0x3f0 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_A22__IPU1_DISP1_DATA17 0x0dc 0x3f0 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_A22__IPU2_CSI1_DATA17 0x0dc 0x3f0 0x8cc 0x2 0x1 -#define MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x0dc 0x3f0 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_A22__SRC_BOOT_CFG22 0x0dc 0x3f0 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_A21__EIM_ADDR21 0x0e0 0x3f4 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_A21__IPU1_DISP1_DATA16 0x0e0 0x3f4 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_A21__IPU2_CSI1_DATA16 0x0e0 0x3f4 0x8c8 0x2 0x1 -#define MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x0e0 0x3f4 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_A21__SRC_BOOT_CFG21 0x0e0 0x3f4 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_A20__EIM_ADDR20 0x0e4 0x3f8 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_A20__IPU1_DISP1_DATA15 0x0e4 0x3f8 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_A20__IPU2_CSI1_DATA15 0x0e4 0x3f8 0x8c4 0x2 0x1 -#define MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x0e4 0x3f8 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_A20__SRC_BOOT_CFG20 0x0e4 0x3f8 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_A19__EIM_ADDR19 0x0e8 0x3fc 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_A19__IPU1_DISP1_DATA14 0x0e8 0x3fc 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_A19__IPU2_CSI1_DATA14 0x0e8 0x3fc 0x8c0 0x2 0x1 -#define MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x0e8 0x3fc 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_A19__SRC_BOOT_CFG19 0x0e8 0x3fc 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_A18__EIM_ADDR18 0x0ec 0x400 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_A18__IPU1_DISP1_DATA13 0x0ec 0x400 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_A18__IPU2_CSI1_DATA13 0x0ec 0x400 0x8bc 0x2 0x1 -#define MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x0ec 0x400 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_A18__SRC_BOOT_CFG18 0x0ec 0x400 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_A17__EIM_ADDR17 0x0f0 0x404 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_A17__IPU1_DISP1_DATA12 0x0f0 0x404 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA12 0x0f0 0x404 0x8b8 0x2 0x1 -#define MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x0f0 0x404 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_A17__SRC_BOOT_CFG17 0x0f0 0x404 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_A16__EIM_ADDR16 0x0f4 0x408 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_A16__IPU1_DI1_DISP_CLK 0x0f4 0x408 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_A16__IPU2_CSI1_PIXCLK 0x0f4 0x408 0x8e0 0x2 0x1 -#define MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x0f4 0x408 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_A16__SRC_BOOT_CFG16 0x0f4 0x408 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0x0f8 0x40c 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_CS0__IPU1_DI1_PIN05 0x0f8 0x40c 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x0f8 0x40c 0x810 0x2 0x0 -#define MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x0f8 0x40c 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_CS1__EIM_CS1_B 0x0fc 0x410 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_CS1__IPU1_DI1_PIN06 0x0fc 0x410 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x0fc 0x410 0x818 0x2 0x0 -#define MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x0fc 0x410 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_OE__EIM_OE_B 0x100 0x414 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_OE__IPU1_DI1_PIN07 0x100 0x414 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100 0x414 0x814 0x2 0x0 -#define MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x100 0x414 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_RW__EIM_RW 0x104 0x418 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_RW__IPU1_DI1_PIN08 0x104 0x418 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_RW__ECSPI2_SS0 0x104 0x418 0x81c 0x2 0x0 -#define MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x104 0x418 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_RW__SRC_BOOT_CFG29 0x104 0x418 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_LBA__EIM_LBA_B 0x108 0x41c 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_LBA__IPU1_DI1_PIN17 0x108 0x41c 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_LBA__ECSPI2_SS1 0x108 0x41c 0x820 0x2 0x0 -#define MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x108 0x41c 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_LBA__SRC_BOOT_CFG26 0x108 0x41c 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_EB0__EIM_EB0_B 0x10c 0x420 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_EB0__IPU1_DISP1_DATA11 0x10c 0x420 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_EB0__IPU2_CSI1_DATA11 0x10c 0x420 0x8b4 0x2 0x1 -#define MX6QDL_PAD_EIM_EB0__CCM_PMIC_READY 0x10c 0x420 0x7f0 0x4 0x0 -#define MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x10c 0x420 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_EB0__SRC_BOOT_CFG27 0x10c 0x420 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_EB1__EIM_EB1_B 0x110 0x424 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_EB1__IPU1_DISP1_DATA10 0x110 0x424 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_EB1__IPU2_CSI1_DATA10 0x110 0x424 0x8b0 0x2 0x1 -#define MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x110 0x424 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_EB1__SRC_BOOT_CFG28 0x110 0x424 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA0__EIM_AD00 0x114 0x428 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA0__IPU1_DISP1_DATA09 0x114 0x428 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA0__IPU2_CSI1_DATA09 0x114 0x428 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x114 0x428 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA0__SRC_BOOT_CFG00 0x114 0x428 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA1__EIM_AD01 0x118 0x42c 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA1__IPU1_DISP1_DATA08 0x118 0x42c 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA1__IPU2_CSI1_DATA08 0x118 0x42c 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x118 0x42c 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA1__SRC_BOOT_CFG01 0x118 0x42c 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA2__EIM_AD02 0x11c 0x430 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA2__IPU1_DISP1_DATA07 0x11c 0x430 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA2__IPU2_CSI1_DATA07 0x11c 0x430 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x11c 0x430 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA2__SRC_BOOT_CFG02 0x11c 0x430 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA3__EIM_AD03 0x120 0x434 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA3__IPU1_DISP1_DATA06 0x120 0x434 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA3__IPU2_CSI1_DATA06 0x120 0x434 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x120 0x434 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA3__SRC_BOOT_CFG03 0x120 0x434 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA4__EIM_AD04 0x124 0x438 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA4__IPU1_DISP1_DATA05 0x124 0x438 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA4__IPU2_CSI1_DATA05 0x124 0x438 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x124 0x438 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA4__SRC_BOOT_CFG04 0x124 0x438 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA5__EIM_AD05 0x128 0x43c 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA5__IPU1_DISP1_DATA04 0x128 0x43c 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA5__IPU2_CSI1_DATA04 0x128 0x43c 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x128 0x43c 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA5__SRC_BOOT_CFG05 0x128 0x43c 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA6__EIM_AD06 0x12c 0x440 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA6__IPU1_DISP1_DATA03 0x12c 0x440 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA6__IPU2_CSI1_DATA03 0x12c 0x440 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x12c 0x440 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA6__SRC_BOOT_CFG06 0x12c 0x440 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA7__EIM_AD07 0x130 0x444 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA7__IPU1_DISP1_DATA02 0x130 0x444 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA7__IPU2_CSI1_DATA02 0x130 0x444 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x130 0x444 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA7__SRC_BOOT_CFG07 0x130 0x444 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA8__EIM_AD08 0x134 0x448 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA8__IPU1_DISP1_DATA01 0x134 0x448 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA8__IPU2_CSI1_DATA01 0x134 0x448 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x134 0x448 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA8__SRC_BOOT_CFG08 0x134 0x448 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA9__EIM_AD09 0x138 0x44c 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA9__IPU1_DISP1_DATA00 0x138 0x44c 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA9__IPU2_CSI1_DATA00 0x138 0x44c 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x138 0x44c 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA9__SRC_BOOT_CFG09 0x138 0x44c 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA10__EIM_AD10 0x13c 0x450 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA10__IPU1_DI1_PIN15 0x13c 0x450 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA10__IPU2_CSI1_DATA_EN 0x13c 0x450 0x8d8 0x2 0x1 -#define MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x13c 0x450 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA10__SRC_BOOT_CFG10 0x13c 0x450 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA11__EIM_AD11 0x140 0x454 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA11__IPU1_DI1_PIN02 0x140 0x454 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA11__IPU2_CSI1_HSYNC 0x140 0x454 0x8dc 0x2 0x1 -#define MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0x140 0x454 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA11__SRC_BOOT_CFG11 0x140 0x454 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA12__EIM_AD12 0x144 0x458 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA12__IPU1_DI1_PIN03 0x144 0x458 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA12__IPU2_CSI1_VSYNC 0x144 0x458 0x8e4 0x2 0x1 -#define MX6QDL_PAD_EIM_DA12__GPIO3_IO12 0x144 0x458 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA12__SRC_BOOT_CFG12 0x144 0x458 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA13__EIM_AD13 0x148 0x45c 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA13__IPU1_DI1_D0_CS 0x148 0x45c 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x148 0x45c 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA13__SRC_BOOT_CFG13 0x148 0x45c 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA14__EIM_AD14 0x14c 0x460 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA14__IPU1_DI1_D1_CS 0x14c 0x460 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x14c 0x460 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA14__SRC_BOOT_CFG14 0x14c 0x460 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA15__EIM_AD15 0x150 0x464 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA15__IPU1_DI1_PIN01 0x150 0x464 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA15__IPU1_DI1_PIN04 0x150 0x464 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x150 0x464 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA15__SRC_BOOT_CFG15 0x150 0x464 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0x154 0x468 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_WAIT__EIM_DTACK_B 0x154 0x468 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x154 0x468 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_WAIT__SRC_BOOT_CFG25 0x154 0x468 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_BCLK__EIM_BCLK 0x158 0x46c 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_BCLK__IPU1_DI1_PIN16 0x158 0x46c 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x158 0x46c 0x000 0x5 0x0 -#define MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x15c 0x470 0x000 0x0 0x0 -#define MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0x15c 0x470 0x000 0x1 0x0 -#define MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x15c 0x470 0x000 0x5 0x0 -#define MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x160 0x474 0x000 0x0 0x0 -#define MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN15 0x160 0x474 0x000 0x1 0x0 -#define MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x160 0x474 0x000 0x2 0x0 -#define MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x160 0x474 0x000 0x5 0x0 -#define MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x164 0x478 0x000 0x0 0x0 -#define MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN02 0x164 0x478 0x000 0x1 0x0 -#define MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x164 0x478 0x000 0x2 0x0 -#define MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x164 0x478 0x000 0x5 0x0 -#define MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x168 0x47c 0x000 0x0 0x0 -#define MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN03 0x168 0x47c 0x000 0x1 0x0 -#define MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x168 0x47c 0x000 0x2 0x0 -#define MX6QDL_PAD_DI0_PIN3__GPIO4_IO19 0x168 0x47c 0x000 0x5 0x0 -#define MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x16c 0x480 0x000 0x0 0x0 -#define MX6QDL_PAD_DI0_PIN4__IPU2_DI0_PIN04 0x16c 0x480 0x000 0x1 0x0 -#define MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x16c 0x480 0x000 0x2 0x0 -#define MX6QDL_PAD_DI0_PIN4__SD1_WP 0x16c 0x480 0x94c 0x3 0x0 -#define MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x16c 0x480 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x170 0x484 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_DATA00 0x170 0x484 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x170 0x484 0x000 0x2 0x0 -#define MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21 0x170 0x484 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x174 0x488 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_DATA01 0x174 0x488 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x174 0x488 0x000 0x2 0x0 -#define MX6QDL_PAD_DISP0_DAT1__GPIO4_IO22 0x174 0x488 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x178 0x48c 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_DATA02 0x178 0x48c 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x178 0x48c 0x000 0x2 0x0 -#define MX6QDL_PAD_DISP0_DAT2__GPIO4_IO23 0x178 0x48c 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x17c 0x490 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_DATA03 0x17c 0x490 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT3__ECSPI3_SS0 0x17c 0x490 0x000 0x2 0x0 -#define MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x17c 0x490 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x180 0x494 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_DATA04 0x180 0x494 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT4__ECSPI3_SS1 0x180 0x494 0x000 0x2 0x0 -#define MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x180 0x494 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x184 0x498 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_DATA05 0x184 0x498 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT5__ECSPI3_SS2 0x184 0x498 0x000 0x2 0x0 -#define MX6QDL_PAD_DISP0_DAT5__AUD6_RXFS 0x184 0x498 0x000 0x3 0x0 -#define MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x184 0x498 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x188 0x49c 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_DATA06 0x188 0x49c 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT6__ECSPI3_SS3 0x188 0x49c 0x000 0x2 0x0 -#define MX6QDL_PAD_DISP0_DAT6__AUD6_RXC 0x188 0x49c 0x000 0x3 0x0 -#define MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x188 0x49c 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x18c 0x4a0 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_DATA07 0x18c 0x4a0 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT7__ECSPI3_RDY 0x18c 0x4a0 0x000 0x2 0x0 -#define MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x18c 0x4a0 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x190 0x4a4 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_DATA08 0x190 0x4a4 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x190 0x4a4 0x000 0x2 0x0 -#define MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x190 0x4a4 0x000 0x3 0x0 -#define MX6QDL_PAD_DISP0_DAT8__GPIO4_IO29 0x190 0x4a4 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x194 0x4a8 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_DATA09 0x194 0x4a8 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 0x194 0x4a8 0x000 0x2 0x0 -#define MX6QDL_PAD_DISP0_DAT9__WDOG2_B 0x194 0x4a8 0x000 0x3 0x0 -#define MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x194 0x4a8 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x198 0x4ac 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0_DATA10 0x198 0x4ac 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31 0x198 0x4ac 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x19c 0x4b0 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0_DATA11 0x19c 0x4b0 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x19c 0x4b0 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x1a0 0x4b4 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0_DATA12 0x1a0 0x4b4 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06 0x1a0 0x4b4 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x1a4 0x4b8 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0_DATA13 0x1a4 0x4b8 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT13__AUD5_RXFS 0x1a4 0x4b8 0x7d8 0x3 0x1 -#define MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07 0x1a4 0x4b8 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x1a8 0x4bc 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0_DATA14 0x1a8 0x4bc 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT14__AUD5_RXC 0x1a8 0x4bc 0x7d4 0x3 0x1 -#define MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x1a8 0x4bc 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x1ac 0x4c0 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DATA15 0x1ac 0x4c0 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT15__ECSPI1_SS1 0x1ac 0x4c0 0x804 0x2 0x1 -#define MX6QDL_PAD_DISP0_DAT15__ECSPI2_SS1 0x1ac 0x4c0 0x820 0x3 0x1 -#define MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x1ac 0x4c0 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x1b0 0x4c4 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT16__IPU2_DISP0_DATA16 0x1b0 0x4c4 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI 0x1b0 0x4c4 0x818 0x2 0x1 -#define MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x1b0 0x4c4 0x7dc 0x3 0x0 -#define MX6QDL_PAD_DISP0_DAT16__SDMA_EXT_EVENT0 0x1b0 0x4c4 0x90c 0x4 0x0 -#define MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 0x1b0 0x4c4 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x1b4 0x4c8 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT17__IPU2_DISP0_DATA17 0x1b4 0x4c8 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT17__ECSPI2_MISO 0x1b4 0x4c8 0x814 0x2 0x1 -#define MX6QDL_PAD_DISP0_DAT17__AUD5_TXD 0x1b4 0x4c8 0x7d0 0x3 0x0 -#define MX6QDL_PAD_DISP0_DAT17__SDMA_EXT_EVENT1 0x1b4 0x4c8 0x910 0x4 0x0 -#define MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x1b4 0x4c8 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x1b8 0x4cc 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT18__IPU2_DISP0_DATA18 0x1b8 0x4cc 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT18__ECSPI2_SS0 0x1b8 0x4cc 0x81c 0x2 0x1 -#define MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x1b8 0x4cc 0x7e0 0x3 0x0 -#define MX6QDL_PAD_DISP0_DAT18__AUD4_RXFS 0x1b8 0x4cc 0x7c0 0x4 0x0 -#define MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b8 0x4cc 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT18__EIM_CS2_B 0x1b8 0x4cc 0x000 0x7 0x0 -#define MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x1bc 0x4d0 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT19__IPU2_DISP0_DATA19 0x1bc 0x4d0 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK 0x1bc 0x4d0 0x810 0x2 0x1 -#define MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x1bc 0x4d0 0x7cc 0x3 0x0 -#define MX6QDL_PAD_DISP0_DAT19__AUD4_RXC 0x1bc 0x4d0 0x7bc 0x4 0x0 -#define MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1bc 0x4d0 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT19__EIM_CS3_B 0x1bc 0x4d0 0x000 0x7 0x0 -#define MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x1c0 0x4d4 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT20__IPU2_DISP0_DATA20 0x1c0 0x4d4 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT20__ECSPI1_SCLK 0x1c0 0x4d4 0x7f4 0x2 0x1 -#define MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x1c0 0x4d4 0x7c4 0x3 0x0 -#define MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1c0 0x4d4 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x1c4 0x4d8 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT21__IPU2_DISP0_DATA21 0x1c4 0x4d8 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT21__ECSPI1_MOSI 0x1c4 0x4d8 0x7fc 0x2 0x1 -#define MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x1c4 0x4d8 0x7b8 0x3 0x1 -#define MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1c4 0x4d8 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x1c8 0x4dc 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT22__IPU2_DISP0_DATA22 0x1c8 0x4dc 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT22__ECSPI1_MISO 0x1c8 0x4dc 0x7f8 0x2 0x1 -#define MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x1c8 0x4dc 0x7c8 0x3 0x1 -#define MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1c8 0x4dc 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x1cc 0x4e0 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT23__IPU2_DISP0_DATA23 0x1cc 0x4e0 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT23__ECSPI1_SS0 0x1cc 0x4e0 0x800 0x2 0x1 -#define MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x1cc 0x4e0 0x7b4 0x3 0x1 -#define MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1cc 0x4e0 0x000 0x5 0x0 -#define MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1d0 0x4e4 0x840 0x1 0x0 -#define MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1d0 0x4e4 0x86c 0x2 0x0 -#define MX6QDL_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT 0x1d0 0x4e4 0x000 0x4 0x0 -#define MX6QDL_PAD_ENET_MDIO__GPIO1_IO22 0x1d0 0x4e4 0x000 0x5 0x0 -#define MX6QDL_PAD_ENET_MDIO__SPDIF_LOCK 0x1d0 0x4e4 0x000 0x6 0x0 -#define MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1d4 0x4e8 0x000 0x1 0x0 -#define MX6QDL_PAD_ENET_REF_CLK__ESAI_RX_FS 0x1d4 0x4e8 0x85c 0x2 0x0 -#define MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1d4 0x4e8 0x000 0x5 0x0 -#define MX6QDL_PAD_ENET_REF_CLK__SPDIF_SR_CLK 0x1d4 0x4e8 0x000 0x6 0x0 -#define MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x1d8 0x4ec 0x004 0x0 0xff0d0100 -#define MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1d8 0x4ec 0x000 0x1 0x0 -#define MX6QDL_PAD_ENET_RX_ER__ESAI_RX_HF_CLK 0x1d8 0x4ec 0x864 0x2 0x0 -#define MX6QDL_PAD_ENET_RX_ER__SPDIF_IN 0x1d8 0x4ec 0x914 0x3 0x1 -#define MX6QDL_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT 0x1d8 0x4ec 0x000 0x4 0x0 -#define MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x1d8 0x4ec 0x000 0x5 0x0 -#define MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1dc 0x4f0 0x858 0x1 0x1 -#define MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1dc 0x4f0 0x870 0x2 0x0 -#define MX6QDL_PAD_ENET_CRS_DV__SPDIF_EXT_CLK 0x1dc 0x4f0 0x918 0x3 0x1 -#define MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1dc 0x4f0 0x000 0x5 0x0 -#define MX6QDL_PAD_ENET_RXD1__MLB_SIG 0x1e0 0x4f4 0x908 0x0 0x0 -#define MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1e0 0x4f4 0x84c 0x1 0x1 -#define MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1e0 0x4f4 0x860 0x2 0x0 -#define MX6QDL_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT 0x1e0 0x4f4 0x000 0x4 0x0 -#define MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1e0 0x4f4 0x000 0x5 0x0 -#define MX6QDL_PAD_ENET_RXD0__OSC32K_32K_OUT 0x1e4 0x4f8 0x000 0x0 0x0 -#define MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1e4 0x4f8 0x848 0x1 0x1 -#define MX6QDL_PAD_ENET_RXD0__ESAI_TX_HF_CLK 0x1e4 0x4f8 0x868 0x2 0x0 -#define MX6QDL_PAD_ENET_RXD0__SPDIF_OUT 0x1e4 0x4f8 0x000 0x3 0x0 -#define MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1e4 0x4f8 0x000 0x5 0x0 -#define MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1e8 0x4fc 0x000 0x1 0x0 -#define MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1e8 0x4fc 0x880 0x2 0x0 -#define MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1e8 0x4fc 0x000 0x5 0x0 -#define MX6QDL_PAD_ENET_TXD1__MLB_CLK 0x1ec 0x500 0x900 0x0 0x0 -#define MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1ec 0x500 0x000 0x1 0x0 -#define MX6QDL_PAD_ENET_TXD1__ESAI_TX2_RX3 0x1ec 0x500 0x87c 0x2 0x0 -#define MX6QDL_PAD_ENET_TXD1__ENET_1588_EVENT0_IN 0x1ec 0x500 0x000 0x4 0x0 -#define MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1ec 0x500 0x000 0x5 0x0 -#define MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1f0 0x504 0x000 0x1 0x0 -#define MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1f0 0x504 0x884 0x2 0x0 -#define MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1f0 0x504 0x000 0x5 0x0 -#define MX6QDL_PAD_ENET_MDC__MLB_DATA 0x1f4 0x508 0x904 0x0 0x0 -#define MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1f4 0x508 0x000 0x1 0x0 -#define MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1f4 0x508 0x888 0x2 0x0 -#define MX6QDL_PAD_ENET_MDC__ENET_1588_EVENT1_IN 0x1f4 0x508 0x000 0x4 0x0 -#define MX6QDL_PAD_ENET_MDC__GPIO1_IO31 0x1f4 0x508 0x000 0x5 0x0 -#define MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x1f8 0x5c8 0x7f4 0x0 0x2 -#define MX6QDL_PAD_KEY_COL0__ENET_RX_DATA3 0x1f8 0x5c8 0x854 0x1 0x1 -#define MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x1f8 0x5c8 0x7dc 0x2 0x1 -#define MX6QDL_PAD_KEY_COL0__KEY_COL0 0x1f8 0x5c8 0x000 0x3 0x0 -#define MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1f8 0x5c8 0x000 0x4 0x0 -#define MX6QDL_PAD_KEY_COL0__UART4_RX_DATA 0x1f8 0x5c8 0x938 0x4 0x0 -#define MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1f8 0x5c8 0x000 0x5 0x0 -#define MX6QDL_PAD_KEY_COL0__DCIC1_OUT 0x1f8 0x5c8 0x000 0x6 0x0 -#define MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x1fc 0x5cc 0x7fc 0x0 0x2 -#define MX6QDL_PAD_KEY_ROW0__ENET_TX_DATA3 0x1fc 0x5cc 0x000 0x1 0x0 -#define MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x1fc 0x5cc 0x7d0 0x2 0x1 -#define MX6QDL_PAD_KEY_ROW0__KEY_ROW0 0x1fc 0x5cc 0x000 0x3 0x0 -#define MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1fc 0x5cc 0x938 0x4 0x1 -#define MX6QDL_PAD_KEY_ROW0__UART4_TX_DATA 0x1fc 0x5cc 0x000 0x4 0x0 -#define MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1fc 0x5cc 0x000 0x5 0x0 -#define MX6QDL_PAD_KEY_ROW0__DCIC2_OUT 0x1fc 0x5cc 0x000 0x6 0x0 -#define MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x200 0x5d0 0x7f8 0x0 0x2 -#define MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x200 0x5d0 0x840 0x1 0x1 -#define MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x200 0x5d0 0x7e0 0x2 0x1 -#define MX6QDL_PAD_KEY_COL1__KEY_COL1 0x200 0x5d0 0x000 0x3 0x0 -#define MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x200 0x5d0 0x000 0x4 0x0 -#define MX6QDL_PAD_KEY_COL1__UART5_RX_DATA 0x200 0x5d0 0x940 0x4 0x0 -#define MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x200 0x5d0 0x000 0x5 0x0 -#define MX6QDL_PAD_KEY_COL1__SD1_VSELECT 0x200 0x5d0 0x000 0x6 0x0 -#define MX6QDL_PAD_KEY_ROW1__ECSPI1_SS0 0x204 0x5d4 0x800 0x0 0x2 -#define MX6QDL_PAD_KEY_ROW1__ENET_COL 0x204 0x5d4 0x000 0x1 0x0 -#define MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x204 0x5d4 0x7cc 0x2 0x1 -#define MX6QDL_PAD_KEY_ROW1__KEY_ROW1 0x204 0x5d4 0x000 0x3 0x0 -#define MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x204 0x5d4 0x940 0x4 0x1 -#define MX6QDL_PAD_KEY_ROW1__UART5_TX_DATA 0x204 0x5d4 0x000 0x4 0x0 -#define MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x204 0x5d4 0x000 0x5 0x0 -#define MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x204 0x5d4 0x000 0x6 0x0 -#define MX6QDL_PAD_KEY_COL2__ECSPI1_SS1 0x208 0x5d8 0x804 0x0 0x2 -#define MX6QDL_PAD_KEY_COL2__ENET_RX_DATA2 0x208 0x5d8 0x850 0x1 0x1 -#define MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x208 0x5d8 0x000 0x2 0x0 -#define MX6QDL_PAD_KEY_COL2__KEY_COL2 0x208 0x5d8 0x000 0x3 0x0 -#define MX6QDL_PAD_KEY_COL2__ENET_MDC 0x208 0x5d8 0x000 0x4 0x0 -#define MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x208 0x5d8 0x000 0x5 0x0 -#define MX6QDL_PAD_KEY_COL2__USB_H1_PWR_CTL_WAKE 0x208 0x5d8 0x000 0x6 0x0 -#define MX6QDL_PAD_KEY_ROW2__ECSPI1_SS2 0x20c 0x5dc 0x808 0x0 0x1 -#define MX6QDL_PAD_KEY_ROW2__ENET_TX_DATA2 0x20c 0x5dc 0x000 0x1 0x0 -#define MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x20c 0x5dc 0x7e4 0x2 0x0 -#define MX6QDL_PAD_KEY_ROW2__KEY_ROW2 0x20c 0x5dc 0x000 0x3 0x0 -#define MX6QDL_PAD_KEY_ROW2__SD2_VSELECT 0x20c 0x5dc 0x000 0x4 0x0 -#define MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x20c 0x5dc 0x000 0x5 0x0 -#define MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x20c 0x5dc 0x88c 0x6 0x1 -#define MX6QDL_PAD_KEY_COL3__ECSPI1_SS3 0x210 0x5e0 0x80c 0x0 0x1 -#define MX6QDL_PAD_KEY_COL3__ENET_CRS 0x210 0x5e0 0x000 0x1 0x0 -#define MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x210 0x5e0 0x890 0x2 0x1 -#define MX6QDL_PAD_KEY_COL3__KEY_COL3 0x210 0x5e0 0x000 0x3 0x0 -#define MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x210 0x5e0 0x8a0 0x4 0x1 -#define MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x210 0x5e0 0x000 0x5 0x0 -#define MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x210 0x5e0 0x914 0x6 0x2 -#define MX6QDL_PAD_KEY_ROW3__ASRC_EXT_CLK 0x214 0x5e4 0x7b0 0x1 0x0 -#define MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x214 0x5e4 0x894 0x2 0x1 -#define MX6QDL_PAD_KEY_ROW3__KEY_ROW3 0x214 0x5e4 0x000 0x3 0x0 -#define MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x214 0x5e4 0x8a4 0x4 0x1 -#define MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x214 0x5e4 0x000 0x5 0x0 -#define MX6QDL_PAD_KEY_ROW3__SD1_VSELECT 0x214 0x5e4 0x000 0x6 0x0 -#define MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x218 0x5e8 0x000 0x0 0x0 -#define MX6QDL_PAD_KEY_COL4__IPU1_SISG4 0x218 0x5e8 0x000 0x1 0x0 -#define MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x218 0x5e8 0x944 0x2 0x1 -#define MX6QDL_PAD_KEY_COL4__KEY_COL4 0x218 0x5e8 0x000 0x3 0x0 -#define MX6QDL_PAD_KEY_COL4__UART5_RTS_B 0x218 0x5e8 0x93c 0x4 0x0 -#define MX6QDL_PAD_KEY_COL4__UART5_CTS_B 0x218 0x5e8 0x000 0x4 0x0 -#define MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x218 0x5e8 0x000 0x5 0x0 -#define MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x21c 0x5ec 0x7e8 0x0 0x0 -#define MX6QDL_PAD_KEY_ROW4__IPU1_SISG5 0x21c 0x5ec 0x000 0x1 0x0 -#define MX6QDL_PAD_KEY_ROW4__USB_OTG_PWR 0x21c 0x5ec 0x000 0x2 0x0 -#define MX6QDL_PAD_KEY_ROW4__KEY_ROW4 0x21c 0x5ec 0x000 0x3 0x0 -#define MX6QDL_PAD_KEY_ROW4__UART5_CTS_B 0x21c 0x5ec 0x000 0x4 0x0 -#define MX6QDL_PAD_KEY_ROW4__UART5_RTS_B 0x21c 0x5ec 0x93c 0x4 0x1 -#define MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x21c 0x5ec 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x220 0x5f0 0x000 0x0 0x0 -#define MX6QDL_PAD_GPIO_0__KEY_COL5 0x220 0x5f0 0x8e8 0x2 0x0 -#define MX6QDL_PAD_GPIO_0__ASRC_EXT_CLK 0x220 0x5f0 0x7b0 0x3 0x1 -#define MX6QDL_PAD_GPIO_0__EPIT1_OUT 0x220 0x5f0 0x000 0x4 0x0 -#define MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x220 0x5f0 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_0__USB_H1_PWR 0x220 0x5f0 0x000 0x6 0x0 -#define MX6QDL_PAD_GPIO_0__SNVS_VIO_5 0x220 0x5f0 0x000 0x7 0x0 -#define MX6QDL_PAD_GPIO_1__ESAI_RX_CLK 0x224 0x5f4 0x86c 0x0 0x1 -#define MX6QDL_PAD_GPIO_1__WDOG2_B 0x224 0x5f4 0x000 0x1 0x0 -#define MX6QDL_PAD_GPIO_1__KEY_ROW5 0x224 0x5f4 0x8f4 0x2 0x0 -#define MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x224 0x5f4 0x004 0x3 0xff0d0101 -#define MX6QDL_PAD_GPIO_1__PWM2_OUT 0x224 0x5f4 0x000 0x4 0x0 -#define MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x224 0x5f4 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_1__SD1_CD_B 0x224 0x5f4 0x000 0x6 0x0 -#define MX6QDL_PAD_GPIO_9__ESAI_RX_FS 0x228 0x5f8 0x85c 0x0 0x1 -#define MX6QDL_PAD_GPIO_9__WDOG1_B 0x228 0x5f8 0x000 0x1 0x0 -#define MX6QDL_PAD_GPIO_9__KEY_COL6 0x228 0x5f8 0x8ec 0x2 0x0 -#define MX6QDL_PAD_GPIO_9__CCM_REF_EN_B 0x228 0x5f8 0x000 0x3 0x0 -#define MX6QDL_PAD_GPIO_9__PWM1_OUT 0x228 0x5f8 0x000 0x4 0x0 -#define MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x228 0x5f8 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_9__SD1_WP 0x228 0x5f8 0x94c 0x6 0x1 -#define MX6QDL_PAD_GPIO_3__ESAI_RX_HF_CLK 0x22c 0x5fc 0x864 0x0 0x1 -#define MX6QDL_PAD_GPIO_3__I2C3_SCL 0x22c 0x5fc 0x8a8 0x2 0x1 -#define MX6QDL_PAD_GPIO_3__XTALOSC_REF_CLK_24M 0x22c 0x5fc 0x000 0x3 0x0 -#define MX6QDL_PAD_GPIO_3__CCM_CLKO2 0x22c 0x5fc 0x000 0x4 0x0 -#define MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x22c 0x5fc 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_3__USB_H1_OC 0x22c 0x5fc 0x948 0x6 0x1 -#define MX6QDL_PAD_GPIO_3__MLB_CLK 0x22c 0x5fc 0x900 0x7 0x1 -#define MX6QDL_PAD_GPIO_6__ESAI_TX_CLK 0x230 0x600 0x870 0x0 0x1 -#define MX6QDL_PAD_GPIO_6__ENET_IRQ 0x230 0x600 0x03c 0x11 0xff000609 -#define MX6QDL_PAD_GPIO_6__I2C3_SDA 0x230 0x600 0x8ac 0x2 0x1 -#define MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x230 0x600 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_6__SD2_LCTL 0x230 0x600 0x000 0x6 0x0 -#define MX6QDL_PAD_GPIO_6__MLB_SIG 0x230 0x600 0x908 0x7 0x1 -#define MX6QDL_PAD_GPIO_2__ESAI_TX_FS 0x234 0x604 0x860 0x0 0x1 -#define MX6QDL_PAD_GPIO_2__KEY_ROW6 0x234 0x604 0x8f8 0x2 0x1 -#define MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x234 0x604 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_2__SD2_WP 0x234 0x604 0x000 0x6 0x0 -#define MX6QDL_PAD_GPIO_2__MLB_DATA 0x234 0x604 0x904 0x7 0x1 -#define MX6QDL_PAD_GPIO_4__ESAI_TX_HF_CLK 0x238 0x608 0x868 0x0 0x1 -#define MX6QDL_PAD_GPIO_4__KEY_COL7 0x238 0x608 0x8f0 0x2 0x1 -#define MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x238 0x608 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_4__SD2_CD_B 0x238 0x608 0x000 0x6 0x0 -#define MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3 0x23c 0x60c 0x87c 0x0 0x1 -#define MX6QDL_PAD_GPIO_5__KEY_ROW7 0x23c 0x60c 0x8fc 0x2 0x1 -#define MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x23c 0x60c 0x000 0x3 0x0 -#define MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x23c 0x60c 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_5__I2C3_SCL 0x23c 0x60c 0x8a8 0x6 0x2 -#define MX6QDL_PAD_GPIO_5__ARM_EVENTI 0x23c 0x60c 0x000 0x7 0x0 -#define MX6QDL_PAD_GPIO_7__ESAI_TX4_RX1 0x240 0x610 0x884 0x0 0x1 -#define MX6QDL_PAD_GPIO_7__ECSPI5_RDY 0x240 0x610 0x000 0x1 0x0 -#define MX6QDL_PAD_GPIO_7__EPIT1_OUT 0x240 0x610 0x000 0x2 0x0 -#define MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x240 0x610 0x000 0x3 0x0 -#define MX6QDL_PAD_GPIO_7__UART2_TX_DATA 0x240 0x610 0x000 0x4 0x0 -#define MX6QDL_PAD_GPIO_7__UART2_RX_DATA 0x240 0x610 0x928 0x4 0x2 -#define MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x240 0x610 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_7__SPDIF_LOCK 0x240 0x610 0x000 0x6 0x0 -#define MX6QDL_PAD_GPIO_7__USB_OTG_HOST_MODE 0x240 0x610 0x000 0x7 0x0 -#define MX6QDL_PAD_GPIO_8__ESAI_TX5_RX0 0x244 0x614 0x888 0x0 0x1 -#define MX6QDL_PAD_GPIO_8__XTALOSC_REF_CLK_32K 0x244 0x614 0x000 0x1 0x0 -#define MX6QDL_PAD_GPIO_8__EPIT2_OUT 0x244 0x614 0x000 0x2 0x0 -#define MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x244 0x614 0x7e4 0x3 0x1 -#define MX6QDL_PAD_GPIO_8__UART2_RX_DATA 0x244 0x614 0x928 0x4 0x3 -#define MX6QDL_PAD_GPIO_8__UART2_TX_DATA 0x244 0x614 0x000 0x4 0x0 -#define MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x244 0x614 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_8__SPDIF_SR_CLK 0x244 0x614 0x000 0x6 0x0 -#define MX6QDL_PAD_GPIO_8__USB_OTG_PWR_CTL_WAKE 0x244 0x614 0x000 0x7 0x0 -#define MX6QDL_PAD_GPIO_16__ESAI_TX3_RX2 0x248 0x618 0x880 0x0 0x1 -#define MX6QDL_PAD_GPIO_16__ENET_1588_EVENT2_IN 0x248 0x618 0x000 0x1 0x0 -#define MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x248 0x618 0x83c 0x2 0x1 -#define MX6QDL_PAD_GPIO_16__SD1_LCTL 0x248 0x618 0x000 0x3 0x0 -#define MX6QDL_PAD_GPIO_16__SPDIF_IN 0x248 0x618 0x914 0x4 0x3 -#define MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x248 0x618 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_16__I2C3_SDA 0x248 0x618 0x8ac 0x6 0x2 -#define MX6QDL_PAD_GPIO_16__JTAG_DE_B 0x248 0x618 0x000 0x7 0x0 -#define MX6QDL_PAD_GPIO_17__ESAI_TX0 0x24c 0x61c 0x874 0x0 0x0 -#define MX6QDL_PAD_GPIO_17__ENET_1588_EVENT3_IN 0x24c 0x61c 0x000 0x1 0x0 -#define MX6QDL_PAD_GPIO_17__CCM_PMIC_READY 0x24c 0x61c 0x7f0 0x2 0x1 -#define MX6QDL_PAD_GPIO_17__SDMA_EXT_EVENT0 0x24c 0x61c 0x90c 0x3 0x1 -#define MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x24c 0x61c 0x000 0x4 0x0 -#define MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x24c 0x61c 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_18__ESAI_TX1 0x250 0x620 0x878 0x0 0x0 -#define MX6QDL_PAD_GPIO_18__ENET_RX_CLK 0x250 0x620 0x844 0x1 0x1 -#define MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x250 0x620 0x000 0x2 0x0 -#define MX6QDL_PAD_GPIO_18__SDMA_EXT_EVENT1 0x250 0x620 0x910 0x3 0x1 -#define MX6QDL_PAD_GPIO_18__ASRC_EXT_CLK 0x250 0x620 0x7b0 0x4 0x2 -#define MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x250 0x620 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_18__SNVS_VIO_5_CTL 0x250 0x620 0x000 0x6 0x0 -#define MX6QDL_PAD_GPIO_19__KEY_COL5 0x254 0x624 0x8e8 0x0 0x1 -#define MX6QDL_PAD_GPIO_19__ENET_1588_EVENT0_OUT 0x254 0x624 0x000 0x1 0x0 -#define MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x254 0x624 0x000 0x2 0x0 -#define MX6QDL_PAD_GPIO_19__CCM_CLKO1 0x254 0x624 0x000 0x3 0x0 -#define MX6QDL_PAD_GPIO_19__ECSPI1_RDY 0x254 0x624 0x000 0x4 0x0 -#define MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x254 0x624 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_19__ENET_TX_ER 0x254 0x624 0x000 0x6 0x0 -#define MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x258 0x628 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x258 0x628 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_PIXCLK__ARM_EVENTO 0x258 0x628 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x25c 0x62c 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x25c 0x62c 0x000 0x3 0x0 -#define MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x25c 0x62c 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_MCLK__ARM_TRACE_CTL 0x25c 0x62c 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x260 0x630 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DATA_EN__EIM_DATA00 0x260 0x630 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x260 0x630 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DATA_EN__ARM_TRACE_CLK 0x260 0x630 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x264 0x634 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_VSYNC__EIM_DATA01 0x264 0x634 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x264 0x634 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_VSYNC__ARM_TRACE00 0x264 0x634 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x268 0x638 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT4__EIM_DATA02 0x268 0x638 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK 0x268 0x638 0x7f4 0x2 0x3 -#define MX6QDL_PAD_CSI0_DAT4__KEY_COL5 0x268 0x638 0x8e8 0x3 0x2 -#define MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x268 0x638 0x000 0x4 0x0 -#define MX6QDL_PAD_CSI0_DAT4__GPIO5_IO22 0x268 0x638 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT4__ARM_TRACE01 0x268 0x638 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x26c 0x63c 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT5__EIM_DATA03 0x26c 0x63c 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI 0x26c 0x63c 0x7fc 0x2 0x3 -#define MX6QDL_PAD_CSI0_DAT5__KEY_ROW5 0x26c 0x63c 0x8f4 0x3 0x1 -#define MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x26c 0x63c 0x000 0x4 0x0 -#define MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x26c 0x63c 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT5__ARM_TRACE02 0x26c 0x63c 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x270 0x640 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT6__EIM_DATA04 0x270 0x640 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO 0x270 0x640 0x7f8 0x2 0x3 -#define MX6QDL_PAD_CSI0_DAT6__KEY_COL6 0x270 0x640 0x8ec 0x3 0x1 -#define MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x270 0x640 0x000 0x4 0x0 -#define MX6QDL_PAD_CSI0_DAT6__GPIO5_IO24 0x270 0x640 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT6__ARM_TRACE03 0x270 0x640 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x274 0x644 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT7__EIM_DATA05 0x274 0x644 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT7__ECSPI1_SS0 0x274 0x644 0x800 0x2 0x3 -#define MX6QDL_PAD_CSI0_DAT7__KEY_ROW6 0x274 0x644 0x8f8 0x3 0x2 -#define MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x274 0x644 0x000 0x4 0x0 -#define MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25 0x274 0x644 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT7__ARM_TRACE04 0x274 0x644 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x278 0x648 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT8__EIM_DATA06 0x278 0x648 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x278 0x648 0x810 0x2 0x2 -#define MX6QDL_PAD_CSI0_DAT8__KEY_COL7 0x278 0x648 0x8f0 0x3 0x2 -#define MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x278 0x648 0x89c 0x4 0x1 -#define MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x278 0x648 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT8__ARM_TRACE05 0x278 0x648 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x27c 0x64c 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT9__EIM_DATA07 0x27c 0x64c 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x27c 0x64c 0x818 0x2 0x2 -#define MX6QDL_PAD_CSI0_DAT9__KEY_ROW7 0x27c 0x64c 0x8fc 0x3 0x2 -#define MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x27c 0x64c 0x898 0x4 0x1 -#define MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x27c 0x64c 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT9__ARM_TRACE06 0x27c 0x64c 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x280 0x650 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT10__AUD3_RXC 0x280 0x650 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x280 0x650 0x814 0x2 0x2 -#define MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x280 0x650 0x000 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x280 0x650 0x920 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x280 0x650 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x280 0x650 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x284 0x654 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT11__AUD3_RXFS 0x284 0x654 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT11__ECSPI2_SS0 0x284 0x654 0x81c 0x2 0x2 -#define MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x284 0x654 0x920 0x3 0x1 -#define MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x284 0x654 0x000 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x284 0x654 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT11__ARM_TRACE08 0x284 0x654 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x288 0x658 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT12__EIM_DATA08 0x288 0x658 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x288 0x658 0x000 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT12__UART4_RX_DATA 0x288 0x658 0x938 0x3 0x2 -#define MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x288 0x658 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT12__ARM_TRACE09 0x288 0x658 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x28c 0x65c 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT13__EIM_DATA09 0x28c 0x65c 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x28c 0x65c 0x938 0x3 0x3 -#define MX6QDL_PAD_CSI0_DAT13__UART4_TX_DATA 0x28c 0x65c 0x000 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x28c 0x65c 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT13__ARM_TRACE10 0x28c 0x65c 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x290 0x660 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT14__EIM_DATA10 0x290 0x660 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x290 0x660 0x000 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT14__UART5_RX_DATA 0x290 0x660 0x940 0x3 0x2 -#define MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00 0x290 0x660 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT14__ARM_TRACE11 0x290 0x660 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x294 0x664 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT15__EIM_DATA11 0x294 0x664 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x294 0x664 0x940 0x3 0x3 -#define MX6QDL_PAD_CSI0_DAT15__UART5_TX_DATA 0x294 0x664 0x000 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT15__GPIO6_IO01 0x294 0x664 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT15__ARM_TRACE12 0x294 0x664 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x298 0x668 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT16__EIM_DATA12 0x298 0x668 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x298 0x668 0x934 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT16__UART4_CTS_B 0x298 0x668 0x000 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT16__GPIO6_IO02 0x298 0x668 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT16__ARM_TRACE13 0x298 0x668 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x29c 0x66c 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT17__EIM_DATA13 0x29c 0x66c 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x29c 0x66c 0x000 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT17__UART4_RTS_B 0x29c 0x66c 0x934 0x3 0x1 -#define MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x29c 0x66c 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT17__ARM_TRACE14 0x29c 0x66c 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x2a0 0x670 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT18__EIM_DATA14 0x2a0 0x670 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT18__UART5_RTS_B 0x2a0 0x670 0x93c 0x3 0x2 -#define MX6QDL_PAD_CSI0_DAT18__UART5_CTS_B 0x2a0 0x670 0x000 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04 0x2a0 0x670 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT18__ARM_TRACE15 0x2a0 0x670 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x2a4 0x674 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT19__EIM_DATA15 0x2a4 0x674 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT19__UART5_CTS_B 0x2a4 0x674 0x000 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT19__UART5_RTS_B 0x2a4 0x674 0x93c 0x3 0x3 -#define MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05 0x2a4 0x674 0x000 0x5 0x0 -#define MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x2a8 0x690 0x000 0x0 0x0 -#define MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x2a8 0x690 0x000 0x1 0x0 -#define MX6QDL_PAD_SD3_DAT7__UART1_RX_DATA 0x2a8 0x690 0x920 0x1 0x2 -#define MX6QDL_PAD_SD3_DAT7__GPIO6_IO17 0x2a8 0x690 0x000 0x5 0x0 -#define MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x2ac 0x694 0x000 0x0 0x0 -#define MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x2ac 0x694 0x920 0x1 0x3 -#define MX6QDL_PAD_SD3_DAT6__UART1_TX_DATA 0x2ac 0x694 0x000 0x1 0x0 -#define MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x2ac 0x694 0x000 0x5 0x0 -#define MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x2b0 0x698 0x000 0x0 0x0 -#define MX6QDL_PAD_SD3_DAT5__UART2_TX_DATA 0x2b0 0x698 0x000 0x1 0x0 -#define MX6QDL_PAD_SD3_DAT5__UART2_RX_DATA 0x2b0 0x698 0x928 0x1 0x4 -#define MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x2b0 0x698 0x000 0x5 0x0 -#define MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x2b4 0x69c 0x000 0x0 0x0 -#define MX6QDL_PAD_SD3_DAT4__UART2_RX_DATA 0x2b4 0x69c 0x928 0x1 0x5 -#define MX6QDL_PAD_SD3_DAT4__UART2_TX_DATA 0x2b4 0x69c 0x000 0x1 0x0 -#define MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x2b4 0x69c 0x000 0x5 0x0 -#define MX6QDL_PAD_SD3_CMD__SD3_CMD 0x2b8 0x6a0 0x000 0x0 0x0 -#define MX6QDL_PAD_SD3_CMD__UART2_CTS_B 0x2b8 0x6a0 0x000 0x1 0x0 -#define MX6QDL_PAD_SD3_CMD__UART2_RTS_B 0x2b8 0x6a0 0x924 0x1 0x2 -#define MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x2b8 0x6a0 0x000 0x2 0x0 -#define MX6QDL_PAD_SD3_CMD__GPIO7_IO02 0x2b8 0x6a0 0x000 0x5 0x0 -#define MX6QDL_PAD_SD3_CLK__SD3_CLK 0x2bc 0x6a4 0x000 0x0 0x0 -#define MX6QDL_PAD_SD3_CLK__UART2_RTS_B 0x2bc 0x6a4 0x924 0x1 0x3 -#define MX6QDL_PAD_SD3_CLK__UART2_CTS_B 0x2bc 0x6a4 0x000 0x1 0x0 -#define MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x2bc 0x6a4 0x7e4 0x2 0x2 -#define MX6QDL_PAD_SD3_CLK__GPIO7_IO03 0x2bc 0x6a4 0x000 0x5 0x0 -#define MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x2c0 0x6a8 0x000 0x0 0x0 -#define MX6QDL_PAD_SD3_DAT0__UART1_CTS_B 0x2c0 0x6a8 0x000 0x1 0x0 -#define MX6QDL_PAD_SD3_DAT0__UART1_RTS_B 0x2c0 0x6a8 0x91c 0x1 0x2 -#define MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x2c0 0x6a8 0x000 0x2 0x0 -#define MX6QDL_PAD_SD3_DAT0__GPIO7_IO04 0x2c0 0x6a8 0x000 0x5 0x0 -#define MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x2c4 0x6ac 0x000 0x0 0x0 -#define MX6QDL_PAD_SD3_DAT1__UART1_RTS_B 0x2c4 0x6ac 0x91c 0x1 0x3 -#define MX6QDL_PAD_SD3_DAT1__UART1_CTS_B 0x2c4 0x6ac 0x000 0x1 0x0 -#define MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x2c4 0x6ac 0x7e8 0x2 0x1 -#define MX6QDL_PAD_SD3_DAT1__GPIO7_IO05 0x2c4 0x6ac 0x000 0x5 0x0 -#define MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x2c8 0x6b0 0x000 0x0 0x0 -#define MX6QDL_PAD_SD3_DAT2__GPIO7_IO06 0x2c8 0x6b0 0x000 0x5 0x0 -#define MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x2cc 0x6b4 0x000 0x0 0x0 -#define MX6QDL_PAD_SD3_DAT3__UART3_CTS_B 0x2cc 0x6b4 0x000 0x1 0x0 -#define MX6QDL_PAD_SD3_DAT3__UART3_RTS_B 0x2cc 0x6b4 0x92c 0x1 0x4 -#define MX6QDL_PAD_SD3_DAT3__GPIO7_IO07 0x2cc 0x6b4 0x000 0x5 0x0 -#define MX6QDL_PAD_SD3_RST__SD3_RESET 0x2d0 0x6b8 0x000 0x0 0x0 -#define MX6QDL_PAD_SD3_RST__UART3_RTS_B 0x2d0 0x6b8 0x92c 0x1 0x5 -#define MX6QDL_PAD_SD3_RST__UART3_CTS_B 0x2d0 0x6b8 0x000 0x1 0x0 -#define MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x2d0 0x6b8 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_CLE__NAND_CLE 0x2d4 0x6bc 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_CLE__IPU2_SISG4 0x2d4 0x6bc 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x2d4 0x6bc 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_ALE__NAND_ALE 0x2d8 0x6c0 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x2d8 0x6c0 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x2d8 0x6c0 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0x2dc 0x6c4 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_WP_B__IPU2_SISG5 0x2dc 0x6c4 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x2dc 0x6c4 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0x2e0 0x6c8 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_RB0__IPU2_DI0_PIN01 0x2e0 0x6c8 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x2e0 0x6c8 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0x2e4 0x6cc 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x2e4 0x6cc 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0x2e8 0x6d0 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_CS1__SD4_VSELECT 0x2e8 0x6d0 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x2e8 0x6d0 0x000 0x2 0x0 -#define MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x2e8 0x6d0 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_CS2__NAND_CE2_B 0x2ec 0x6d4 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_CS2__IPU1_SISG0 0x2ec 0x6d4 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_CS2__ESAI_TX0 0x2ec 0x6d4 0x874 0x2 0x1 -#define MX6QDL_PAD_NANDF_CS2__EIM_CRE 0x2ec 0x6d4 0x000 0x3 0x0 -#define MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x2ec 0x6d4 0x000 0x4 0x0 -#define MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x2ec 0x6d4 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_CS2__IPU2_SISG0 0x2ec 0x6d4 0x000 0x6 0x0 -#define MX6QDL_PAD_NANDF_CS3__NAND_CE3_B 0x2f0 0x6d8 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_CS3__IPU1_SISG1 0x2f0 0x6d8 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x2f0 0x6d8 0x878 0x2 0x1 -#define MX6QDL_PAD_NANDF_CS3__EIM_ADDR26 0x2f0 0x6d8 0x000 0x3 0x0 -#define MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x2f0 0x6d8 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_CS3__IPU2_SISG1 0x2f0 0x6d8 0x000 0x6 0x0 -#define MX6QDL_PAD_SD4_CMD__SD4_CMD 0x2f4 0x6dc 0x000 0x0 0x0 -#define MX6QDL_PAD_SD4_CMD__NAND_RE_B 0x2f4 0x6dc 0x000 0x1 0x0 -#define MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x2f4 0x6dc 0x000 0x2 0x0 -#define MX6QDL_PAD_SD4_CMD__UART3_RX_DATA 0x2f4 0x6dc 0x930 0x2 0x2 -#define MX6QDL_PAD_SD4_CMD__GPIO7_IO09 0x2f4 0x6dc 0x000 0x5 0x0 -#define MX6QDL_PAD_SD4_CLK__SD4_CLK 0x2f8 0x6e0 0x000 0x0 0x0 -#define MX6QDL_PAD_SD4_CLK__NAND_WE_B 0x2f8 0x6e0 0x000 0x1 0x0 -#define MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x2f8 0x6e0 0x930 0x2 0x3 -#define MX6QDL_PAD_SD4_CLK__UART3_TX_DATA 0x2f8 0x6e0 0x000 0x2 0x0 -#define MX6QDL_PAD_SD4_CLK__GPIO7_IO10 0x2f8 0x6e0 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_D0__NAND_DATA00 0x2fc 0x6e4 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x2fc 0x6e4 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x2fc 0x6e4 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_D1__NAND_DATA01 0x300 0x6e8 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x300 0x6e8 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x300 0x6e8 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_D2__NAND_DATA02 0x304 0x6ec 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x304 0x6ec 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x304 0x6ec 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_D3__NAND_DATA03 0x308 0x6f0 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x308 0x6f0 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x308 0x6f0 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_D4__NAND_DATA04 0x30c 0x6f4 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x30c 0x6f4 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x30c 0x6f4 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_D5__NAND_DATA05 0x310 0x6f8 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x310 0x6f8 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x310 0x6f8 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_D6__NAND_DATA06 0x314 0x6fc 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x314 0x6fc 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x314 0x6fc 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_D7__NAND_DATA07 0x318 0x700 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x318 0x700 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x318 0x700 0x000 0x5 0x0 -#define MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x31c 0x704 0x000 0x1 0x0 -#define MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x31c 0x704 0x000 0x2 0x0 -#define MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x31c 0x704 0x000 0x5 0x0 -#define MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x320 0x708 0x000 0x1 0x0 -#define MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x320 0x708 0x000 0x2 0x0 -#define MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x320 0x708 0x000 0x5 0x0 -#define MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x324 0x70c 0x000 0x1 0x0 -#define MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x324 0x70c 0x000 0x2 0x0 -#define MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x324 0x70c 0x000 0x5 0x0 -#define MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x328 0x710 0x000 0x1 0x0 -#define MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x328 0x710 0x000 0x5 0x0 -#define MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x32c 0x714 0x000 0x1 0x0 -#define MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x32c 0x714 0x928 0x2 0x6 -#define MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA 0x32c 0x714 0x000 0x2 0x0 -#define MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x32c 0x714 0x000 0x5 0x0 -#define MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x330 0x718 0x000 0x1 0x0 -#define MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x330 0x718 0x924 0x2 0x4 -#define MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 0x330 0x718 0x000 0x2 0x0 -#define MX6QDL_PAD_SD4_DAT5__GPIO2_IO13 0x330 0x718 0x000 0x5 0x0 -#define MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x334 0x71c 0x000 0x1 0x0 -#define MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x334 0x71c 0x000 0x2 0x0 -#define MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x334 0x71c 0x924 0x2 0x5 -#define MX6QDL_PAD_SD4_DAT6__GPIO2_IO14 0x334 0x71c 0x000 0x5 0x0 -#define MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x338 0x720 0x000 0x1 0x0 -#define MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x338 0x720 0x000 0x2 0x0 -#define MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x338 0x720 0x928 0x2 0x7 -#define MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x338 0x720 0x000 0x5 0x0 -#define MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x33c 0x724 0x000 0x0 0x0 -#define MX6QDL_PAD_SD1_DAT1__ECSPI5_SS0 0x33c 0x724 0x834 0x1 0x1 -#define MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x33c 0x724 0x000 0x2 0x0 -#define MX6QDL_PAD_SD1_DAT1__GPT_CAPTURE2 0x33c 0x724 0x000 0x3 0x0 -#define MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x33c 0x724 0x000 0x5 0x0 -#define MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x340 0x728 0x000 0x0 0x0 -#define MX6QDL_PAD_SD1_DAT0__ECSPI5_MISO 0x340 0x728 0x82c 0x1 0x1 -#define MX6QDL_PAD_SD1_DAT0__GPT_CAPTURE1 0x340 0x728 0x000 0x3 0x0 -#define MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x340 0x728 0x000 0x5 0x0 -#define MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x344 0x72c 0x000 0x0 0x0 -#define MX6QDL_PAD_SD1_DAT3__ECSPI5_SS2 0x344 0x72c 0x000 0x1 0x0 -#define MX6QDL_PAD_SD1_DAT3__GPT_COMPARE3 0x344 0x72c 0x000 0x2 0x0 -#define MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x344 0x72c 0x000 0x3 0x0 -#define MX6QDL_PAD_SD1_DAT3__WDOG2_B 0x344 0x72c 0x000 0x4 0x0 -#define MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x344 0x72c 0x000 0x5 0x0 -#define MX6QDL_PAD_SD1_DAT3__WDOG2_RESET_B_DEB 0x344 0x72c 0x000 0x6 0x0 -#define MX6QDL_PAD_SD1_CMD__SD1_CMD 0x348 0x730 0x000 0x0 0x0 -#define MX6QDL_PAD_SD1_CMD__ECSPI5_MOSI 0x348 0x730 0x830 0x1 0x0 -#define MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x348 0x730 0x000 0x2 0x0 -#define MX6QDL_PAD_SD1_CMD__GPT_COMPARE1 0x348 0x730 0x000 0x3 0x0 -#define MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0x348 0x730 0x000 0x5 0x0 -#define MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x34c 0x734 0x000 0x0 0x0 -#define MX6QDL_PAD_SD1_DAT2__ECSPI5_SS1 0x34c 0x734 0x838 0x1 0x1 -#define MX6QDL_PAD_SD1_DAT2__GPT_COMPARE2 0x34c 0x734 0x000 0x2 0x0 -#define MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x34c 0x734 0x000 0x3 0x0 -#define MX6QDL_PAD_SD1_DAT2__WDOG1_B 0x34c 0x734 0x000 0x4 0x0 -#define MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x34c 0x734 0x000 0x5 0x0 -#define MX6QDL_PAD_SD1_DAT2__WDOG1_RESET_B_DEB 0x34c 0x734 0x000 0x6 0x0 -#define MX6QDL_PAD_SD1_CLK__SD1_CLK 0x350 0x738 0x000 0x0 0x0 -#define MX6QDL_PAD_SD1_CLK__ECSPI5_SCLK 0x350 0x738 0x828 0x1 0x0 -#define MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x350 0x738 0x000 0x2 0x0 -#define MX6QDL_PAD_SD1_CLK__GPT_CLKIN 0x350 0x738 0x000 0x3 0x0 -#define MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x350 0x738 0x000 0x5 0x0 -#define MX6QDL_PAD_SD2_CLK__SD2_CLK 0x354 0x73c 0x000 0x0 0x0 -#define MX6QDL_PAD_SD2_CLK__ECSPI5_SCLK 0x354 0x73c 0x828 0x1 0x1 -#define MX6QDL_PAD_SD2_CLK__KEY_COL5 0x354 0x73c 0x8e8 0x2 0x3 -#define MX6QDL_PAD_SD2_CLK__AUD4_RXFS 0x354 0x73c 0x7c0 0x3 0x1 -#define MX6QDL_PAD_SD2_CLK__GPIO1_IO10 0x354 0x73c 0x000 0x5 0x0 -#define MX6QDL_PAD_SD2_CMD__SD2_CMD 0x358 0x740 0x000 0x0 0x0 -#define MX6QDL_PAD_SD2_CMD__ECSPI5_MOSI 0x358 0x740 0x830 0x1 0x1 -#define MX6QDL_PAD_SD2_CMD__KEY_ROW5 0x358 0x740 0x8f4 0x2 0x2 -#define MX6QDL_PAD_SD2_CMD__AUD4_RXC 0x358 0x740 0x7bc 0x3 0x1 -#define MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x358 0x740 0x000 0x5 0x0 -#define MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x35c 0x744 0x000 0x0 0x0 -#define MX6QDL_PAD_SD2_DAT3__ECSPI5_SS3 0x35c 0x744 0x000 0x1 0x0 -#define MX6QDL_PAD_SD2_DAT3__KEY_COL6 0x35c 0x744 0x8ec 0x2 0x2 -#define MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x35c 0x744 0x7c4 0x3 0x1 -#define MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x35c 0x744 0x000 0x5 0x0 - -#endif /* __DTS_IMX6Q_PINFUNC_H */ diff --git a/sys/gnu/dts/arm/imx6q-pistachio.dts b/sys/gnu/dts/arm/imx6q-pistachio.dts deleted file mode 100644 index a31b17eaf51..00000000000 --- a/sys/gnu/dts/arm/imx6q-pistachio.dts +++ /dev/null @@ -1,694 +0,0 @@ -/* - * Copyright (C) 2017 NutsBoard.Org - * - * Author: Wig Cheng - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include -#include -#include "imx6q.dtsi" - -/ { - model = "NutsBoard i.MX6 Quad Pistachio board"; - compatible = "nutsboard,imx6q-pistachio", "fsl,imx6q"; - - chosen { - stdout-path = &uart4; - }; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x80000000>; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-name = "1P8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - wlan_en_reg: regulator-wlan_en { - compatible = "regulator-fixed"; - regulator-name = "wlan-en-regulator"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio2 24 GPIO_ACTIVE_HIGH>; - startup-delay-us = <70000>; - enable-active-high; - }; - - reg_usb_otg_vbus: regulator-usb_vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&swbst_reg>; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_keys>; - - power { - label = "Power Button"; - gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; - wakeup-source; - linux,code = ; - }; - }; - - sound { - compatible = "fsl,imx-sgtl5000", - "fsl,imx-audio-sgtl5000"; - model = "audio-sgtl5000"; - ssi-controller = <&ssi1>; - audio-codec = <&codec>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - mux-int-port = <1>; - mux-ext-port = <3>; - }; - - backlight_lvds: backlight-lvds { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 50000>; - brightness-levels = < - 0 /*1 2 3 4 5 6*/ 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100 - >; - default-brightness-level = <94>; - status = "okay"; - }; - - panel { - compatible = "hannstar,hsd100pxn1"; - backlight = <&backlight_lvds>; - - port { - panel_in: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; - -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - status = "okay"; -}; - -&clks { - assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, - <&clks IMX6QDL_CLK_LDB_DI1_SEL>; - assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, - <&clks IMX6QDL_CLK_PLL3_USB_OTG>; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii"; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c2>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - codec: sgtl5000@a { - compatible = "fsl,sgtl5000"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1_sgtl5000>; - reg = <0x0a>; - clocks = <&clks IMX6QDL_CLK_CKO>; - VDDA-supply = <®_1p8v>; - VDDIO-supply = <®_1p8v>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - pmic: pfuze100@8 { - compatible = "fsl,pfuze100"; - reg = <0x08>; - - regulators { - sw1a_reg: sw1ab { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw1c_reg: sw1c { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw3a_reg: sw3a { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3b_reg: sw3b { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - sw4_reg: sw4 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - }; - - swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - }; - - snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - vgen1_reg: vgen1 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen2_reg: vgen2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen3_reg: vgen3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - vgen4_reg: vgen4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen5_reg: vgen5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - vgen6_reg: vgen6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; - - ar1021@4d { - compatible = "microchip,ar1021-i2c"; - reg = <0x4d>; - interrupt-parent = <&gpio6>; - interrupts = <8 IRQ_TYPE_EDGE_FALLING>; - }; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - - pinctrl_hog: hoggrp { - fsl,pins = < - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /*pcie power*/ - MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b0 /*LCD power*/ - MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x1b0b0 /*backlight power*/ - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b1 /*SD3 CD pin*/ - MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 /*codec power*/ - MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b0 /*touch reset*/ - MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x1b0b01 /*touch irq*/ - MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0/*backlight pwr*/ - MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x1b0b0 /*gpio 5V_1*/ - MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x1b0b0 /*gpio 5V_2*/ - MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x1b0b0 /*gpio 5V_3*/ - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 /*gpio 5V_4*/ - MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0 /*AUX_5V_EN*/ - MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x1b0b0 /*AUX_5VB_EN*/ - MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x1b0b0 /*AUX_3V3_EN*/ - MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x1b0b0 /*I2C expander pwr*/ - >; - }; - - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 - MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 - MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 - MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1 - MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b8b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - /* AR8035 reset */ - MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x130b0 - /* AR8035 interrupt */ - MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x1b0b1 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */ - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x0a0b1 - /* AR8035 pin strapping: IO voltage: pull up */ - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - /* AR8035 pin strapping: PHYADDR#0: pull down */ - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x13030 - /* AR8035 pin strapping: PHYADDR#1: pull down */ - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030 - /* AR8035 pin strapping: MODE#1: pull up */ - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - /* AR8035 pin strapping: MODE#3: pull up */ - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - /* AR8035 pin strapping: MODE#0: pull down */ - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030 - >; - }; - - pinctrl_flexcan2: flexcan2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0 - MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0 - >; - }; - - pinctrl_gpio_keys: gpio_keysgrp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x1b0b0 - >; - }; - - pinctrl_hdmi_cec: hdmicecgrp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x108b0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 - MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c1_sgtl5000: i2c1-sgtl5000grp { - fsl,pins = < - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 /* sys_mclk */ - MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x130b0 /*headphone det*/ - MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x130b0 /*microphone det*/ - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x1b0b1 - MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x1b0b1 - MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x1b0b0 - MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x1b0b0 - MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D28__UART2_CTS_B 0x1b0b1 - MX6QDL_PAD_EIM_D29__UART2_RTS_B 0x1b0b1 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x1b0b1 - MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1 - MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT18__UART5_RTS_B 0x1b0b1 - MX6QDL_PAD_CSI0_DAT19__UART5_CTS_B 0x1b0b1 - MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x15059 /*BT_EN*/ - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 - MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x17059 - MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x17059 - MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x17059 - MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x17059 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 - MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x15059 /*WL_EN_LDO*/ - MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x15059 /*WL_EN*/ - MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x15059 /*WL_IRQ*/ - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17071 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10071 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17071 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17071 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17071 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17071 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__WDOG2_B 0x1b0b00 - >; - }; -}; - -&ldb { - status = "okay"; - - lvds-channel@1 { - fsl,data-mapping = "spwg"; - fsl,data-width = <18>; - status = "okay"; - - port@4 { - reg = <4>; - - lvds0_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "okay"; -}; - -&snvs_poweroff { - status = "okay"; -}; - -&ssi1 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - uart-has-rtscts; - fsl,dte-mode; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - uart-has-rtscts; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - uart-has-rtscts; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - uart-has-rtscts; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - uart-has-rtscts; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - srp-disable; - hnp-disable; - adp-disable; - status = "okay"; -}; - -&usbh1 { - status = "okay"; -}; - -&usbphy1 { - fsl,tx-d-cal = <0x5>; -}; - -&usbphy2 { - fsl,tx-d-cal = <0x5>; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - bus-width = <8>; - keep-power-in-suspend; - vmmc-supply = <®_3p3v>; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - bus-width = <4>; - vmmc-supply = <&wlan_en_reg>; - no-1-8-v; - keep-power-in-suspend; - non-removable; - cap-power-off-card; - status = "okay"; - - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@2 { - compatible = "ti,wl1835"; - reg = <2>; - interrupt-parent = <&gpio5>; - interrupts = <18 IRQ_TYPE_LEVEL_HIGH>; - ref-clock-frequency = <38400000>; - tcxo-clock-frequency = <26000000>; - }; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - bus-width = <4>; - cd-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; - no-1-8-v; - keep-power-in-suspend; - wakeup-source; - status = "okay"; -}; - -&sata { - status = "okay"; -}; - -&wdog1 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx6q-rex-pro.dts b/sys/gnu/dts/arm/imx6q-rex-pro.dts deleted file mode 100644 index 1767e1a3cd5..00000000000 --- a/sys/gnu/dts/arm/imx6q-rex-pro.dts +++ /dev/null @@ -1,31 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright 2014 FEDEVEL, Inc. - * - * Author: Robert Nelson - */ -/dts-v1/; -#include "imx6q.dtsi" -#include "imx6qdl-rex.dtsi" - -/ { - model = "Rex Pro i.MX6 Quad Board"; - compatible = "rex,imx6q-rex-pro", "fsl,imx6q"; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x80000000>; - }; -}; - -&ecspi3 { - flash: m25p80@0 { - compatible = "sst,sst25vf032b", "jedec,spi-nor"; - spi-max-frequency = <20000000>; - reg = <0>; - }; -}; - -&sata { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx6q-sabreauto.dts b/sys/gnu/dts/arm/imx6q-sabreauto.dts deleted file mode 100644 index 6e981a3e0a8..00000000000 --- a/sys/gnu/dts/arm/imx6q-sabreauto.dts +++ /dev/null @@ -1,18 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// -// Copyright 2012 Freescale Semiconductor, Inc. -// Copyright 2011 Linaro Ltd. - -/dts-v1/; - -#include "imx6q.dtsi" -#include "imx6qdl-sabreauto.dtsi" - -/ { - model = "Freescale i.MX6 Quad SABRE Automotive Board"; - compatible = "fsl,imx6q-sabreauto", "fsl,imx6q"; -}; - -&sata { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx6q-sabrelite.dts b/sys/gnu/dts/arm/imx6q-sabrelite.dts deleted file mode 100644 index dc51262e7b2..00000000000 --- a/sys/gnu/dts/arm/imx6q-sabrelite.dts +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Copyright 2011 Freescale Semiconductor, Inc. - * Copyright 2011 Linaro Ltd. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6q.dtsi" -#include "imx6qdl-sabrelite.dtsi" - -/ { - model = "Freescale i.MX6 Quad SABRE Lite Board"; - compatible = "fsl,imx6q-sabrelite", "fsl,imx6q"; -}; - -&sata { - status = "okay"; -}; - -&ipu1_csi1_from_mipi_vc1 { - clock-lanes = <0>; - data-lanes = <1 2>; -}; diff --git a/sys/gnu/dts/arm/imx6q-sabresd.dts b/sys/gnu/dts/arm/imx6q-sabresd.dts deleted file mode 100644 index eec944673c0..00000000000 --- a/sys/gnu/dts/arm/imx6q-sabresd.dts +++ /dev/null @@ -1,23 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// -// Copyright 2012 Freescale Semiconductor, Inc. -// Copyright 2011 Linaro Ltd. - -/dts-v1/; - -#include "imx6q.dtsi" -#include "imx6qdl-sabresd.dtsi" - -/ { - model = "Freescale i.MX6 Quad SABRE Smart Device Board"; - compatible = "fsl,imx6q-sabresd", "fsl,imx6q"; -}; - -&sata { - status = "okay"; -}; - -&ipu1_csi1_from_mipi_vc1 { - clock-lanes = <0>; - data-lanes = <1 2>; -}; diff --git a/sys/gnu/dts/arm/imx6q-savageboard.dts b/sys/gnu/dts/arm/imx6q-savageboard.dts deleted file mode 100644 index 717ac62fc2c..00000000000 --- a/sys/gnu/dts/arm/imx6q-savageboard.dts +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Copyright (C) 2017 Milo Kim - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include "imx6q.dtsi" -#include "imx6qdl-savageboard.dtsi" - -/ { - model = "Poslab SavageBoard Quad"; - compatible = "poslab,imx6q-savageboard", "fsl,imx6q"; -}; - -&sata { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx6q-sbc6x.dts b/sys/gnu/dts/arm/imx6q-sbc6x.dts deleted file mode 100644 index 9054c1d58b9..00000000000 --- a/sys/gnu/dts/arm/imx6q-sbc6x.dts +++ /dev/null @@ -1,93 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright 2013 Pavel Machek - */ - -/dts-v1/; -#include "imx6q.dtsi" - -/ { - model = "MicroSys sbc6x board"; - compatible = "microsys,sbc6x", "fsl,imx6q"; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x80000000>; - }; -}; - - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii"; - status = "okay"; -}; - -&iomuxc { - imx6q-sbc6x { - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - >; - }; - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&usbotg { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx6q-tbs2910.dts b/sys/gnu/dts/arm/imx6q-tbs2910.dts deleted file mode 100644 index bfff87ce2e1..00000000000 --- a/sys/gnu/dts/arm/imx6q-tbs2910.dts +++ /dev/null @@ -1,388 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -// -// Copyright 2014 Soeren Moch - -/dts-v1/; - -#include "imx6q.dtsi" -#include -#include - -/ { - model = "TBS2910 Matrix ARM mini PC"; - compatible = "tbs,imx6q-tbs2910", "fsl,imx6q"; - - chosen { - stdout-path = &uart1; - }; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x80000000>; - }; - - fan { - compatible = "gpio-fan"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_fan>; - gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>; - gpio-fan,speed-map = <0 0 - 3000 1>; - }; - - ir_recv { - compatible = "gpio-ir-receiver"; - gpios = <&gpio3 18 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ir>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - blue { - label = "blue_status_led"; - gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - }; - - reg_2p5v: regulator-2p5v { - compatible = "regulator-fixed"; - regulator-name = "2P5V"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_5p0v: regulator-5p0v { - compatible = "regulator-fixed"; - regulator-name = "5P0V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - sound-sgtl5000 { - audio-codec = <&sgtl5000>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - compatible = "fsl,imx-audio-sgtl5000"; - model = "On-board Codec"; - mux-ext-port = <3>; - mux-int-port = <1>; - ssi-controller = <&ssi1>; - }; - - sound-spdif { - compatible = "fsl,imx-audio-spdif"; - model = "On-board SPDIF"; - spdif-controller = <&spdif>; - spdif-out; - }; -}; - -&audmux { - status = "okay"; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii-id"; - phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&hdmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hdmi>; - ddc-i2c-bus = <&i2c2>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - sgtl5000: sgtl5000@a { - clocks = <&clks IMX6QDL_CLK_CKO>; - compatible = "fsl,sgtl5000"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sgtl5000>; - reg = <0x0a>; - VDDA-supply = <®_2p5v>; - VDDIO-supply = <®_3p3v>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - rtc: ds1307@68 { - compatible = "dallas,ds1307"; - reg = <0x68>; - }; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&sata { - fsl,transmit-level-mV = <1104>; - fsl,transmit-boost-mdB = <3330>; - fsl,transmit-atten-16ths = <16>; - fsl,receive-eq-mdB = <3000>; - status = "okay"; -}; - -&snvs_poweroff { - status = "okay"; -}; - -&spdif { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spdif>; - status = "okay"; -}; - -&ssi1 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_5p0v>; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_5p0v>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - bus-width = <4>; - cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_3p3v>; - vqmmc-supply = <®_3p3v>; - voltage-ranges = <3300 3300>; - no-1-8-v; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - bus-width = <4>; - cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; - vmmc-supply = <®_3p3v>; - vqmmc-supply = <®_3p3v>; - voltage-ranges = <3300 3300>; - no-1-8-v; - status = "okay"; -}; - -&usdhc4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc4>; - bus-width = <8>; - vmmc-supply = <®_3p3v>; - vqmmc-supply = <®_3p3v>; - voltage-ranges = <3300 3300>; - non-removable; - no-1-8-v; - status = "okay"; -}; - -&iomuxc { - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b059 - >; - }; - - pinctrl_gpio_fan: gpiofangrp { - fsl,pins = < - MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x130b1 - >; - }; - - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x130b1 - >; - }; - - pinctrl_hdmi: hdmigrp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_ir: irgrp { - fsl,pins = < - MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x17059 - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = < - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x17059 - >; - }; - - pinctrl_sgtl5000: sgtl5000grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 - MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 - MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 - MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 - >; - }; - - pinctrl_spdif: spdifgrp { - fsl,pins = ; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 - MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x17059 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x17059 - MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x17059 - >; - }; - - pinctrl_usdhc4: usdhc4grp { - fsl,pins = < - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 - MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 - MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 - MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 - MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 - >; - }; -}; diff --git a/sys/gnu/dts/arm/imx6q-ts4900.dts b/sys/gnu/dts/arm/imx6q-ts4900.dts deleted file mode 100644 index dce1e8671eb..00000000000 --- a/sys/gnu/dts/arm/imx6q-ts4900.dts +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Copyright 2015 Technologic Systems - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6q.dtsi" -#include "imx6qdl-ts4900.dtsi" - -/ { - model = "Technologic Systems i.MX6 Quad TS-4900 (Default Device Tree)"; - compatible = "technologic,imx6q-ts4900", "fsl,imx6q"; - - /* Will be filled by the bootloader */ - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0>; - }; -}; - -&sata { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx6q-ts7970.dts b/sys/gnu/dts/arm/imx6q-ts7970.dts deleted file mode 100644 index 570bd3c309a..00000000000 --- a/sys/gnu/dts/arm/imx6q-ts7970.dts +++ /dev/null @@ -1,60 +0,0 @@ -/* - * Copyright 2015 Technologic Systems - * Copyright 2017 Savoir-faire Linux - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6q.dtsi" -#include "imx6qdl-ts7970.dtsi" - -/ { - model = "Technologic Systems i.MX6 Quad TS-7970 (Default Device Tree)"; - compatible = "technologic,imx6q-ts7970", "fsl,imx6q"; - - /* Will be filled by the bootloader */ - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0>; - }; -}; - -&sata { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx6q-tx6q-1010-comtft.dts b/sys/gnu/dts/arm/imx6q-tx6q-1010-comtft.dts deleted file mode 100644 index ac3050a835e..00000000000 --- a/sys/gnu/dts/arm/imx6q-tx6q-1010-comtft.dts +++ /dev/null @@ -1,79 +0,0 @@ -/* - * Copyright 2014-2017 Lothar Waßmann - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6q.dtsi" -#include "imx6qdl-tx6.dtsi" -#include "imx6qdl-tx6-lcd.dtsi" - -/ { - model = "Ka-Ro electronics TX6Q-1010 Module on CoMpact TFT"; - compatible = "karo,imx6q-tx6q", "fsl,imx6q"; -}; - -&backlight { - pwms = <&pwm2 0 500000 0>; - /delete-property/ turn-on-delay-ms; -}; - -&can1 { - status = "disabled"; -}; - -&can2 { - xceiver-supply = <®_3v3>; -}; - -&kpp { - status = "disabled"; -}; - -&lcd_panel { - compatible = "edt,etm0700g0edh6"; -}; - -®_can_xcvr { - status = "disabled"; -}; - -&touchscreen { - status = "disabled"; -}; diff --git a/sys/gnu/dts/arm/imx6q-tx6q-1010.dts b/sys/gnu/dts/arm/imx6q-tx6q-1010.dts deleted file mode 100644 index 4ee860b626f..00000000000 --- a/sys/gnu/dts/arm/imx6q-tx6q-1010.dts +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright 2014-2017 Lothar Waßmann - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6q.dtsi" -#include "imx6qdl-tx6.dtsi" -#include "imx6qdl-tx6-lcd.dtsi" - -/ { - model = "Ka-Ro electronics TX6Q-1010/-1030 Module"; - compatible = "karo,imx6q-tx6q", "fsl,imx6q"; -}; - -&ipu2 { - status = "disabled"; -}; diff --git a/sys/gnu/dts/arm/imx6q-tx6q-1020-comtft.dts b/sys/gnu/dts/arm/imx6q-tx6q-1020-comtft.dts deleted file mode 100644 index a773f252816..00000000000 --- a/sys/gnu/dts/arm/imx6q-tx6q-1020-comtft.dts +++ /dev/null @@ -1,110 +0,0 @@ -/* - * Copyright 2014-2017 Lothar Waßmann - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6q.dtsi" -#include "imx6qdl-tx6.dtsi" -#include "imx6qdl-tx6-lcd.dtsi" - -/ { - model = "Ka-Ro electronics TX6Q-1020 Module on CoMpact TFT"; - compatible = "karo,imx6q-tx6q", "fsl,imx6q"; -}; - -&backlight { - pwms = <&pwm2 0 500000 0>; - /delete-property/ turn-on-delay-ms; -}; - -&can1 { - status = "disabled"; -}; - -&can2 { - xceiver-supply = <®_3v3>; -}; - -&ds1339 { - status = "disabled"; -}; - -&gpmi { - status = "disabled"; -}; - -&kpp { - status = "disabled"; -}; - -&lcd_panel { - compatible = "edt,etm0700g0edh6"; -}; - -®_can_xcvr { - status = "disabled"; -}; - -&touchscreen { - status = "disabled"; -}; - -&usdhc4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc4>; - bus-width = <4>; - no-1-8-v; - fsl,wp-controller; - status = "okay"; -}; - -&iomuxc { - pinctrl_usdhc4: usdhc4grp { - fsl,pins = < - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x070b1 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x070b1 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x070b1 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x070b1 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x070b1 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x070b1 - MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x0b0b1 - >; - }; -}; diff --git a/sys/gnu/dts/arm/imx6q-tx6q-1020.dts b/sys/gnu/dts/arm/imx6q-tx6q-1020.dts deleted file mode 100644 index 0a4daec8d3a..00000000000 --- a/sys/gnu/dts/arm/imx6q-tx6q-1020.dts +++ /dev/null @@ -1,86 +0,0 @@ -/* - * Copyright 2014-2017 Lothar Waßmann - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6q.dtsi" -#include "imx6qdl-tx6.dtsi" -#include "imx6qdl-tx6-lcd.dtsi" - -/ { - model = "Ka-Ro electronics TX6Q-1020 Module"; - compatible = "karo,imx6q-tx6q", "fsl,imx6q"; -}; - -&ds1339 { - status = "disabled"; -}; - -&gpmi { - status = "disabled"; -}; - -&ipu2 { - status = "disabled"; -}; - -&usdhc4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc4>; - bus-width = <4>; - non-removable; - no-1-8-v; - fsl,wp-controller; - status = "okay"; -}; - -&iomuxc { - pinctrl_usdhc4: usdhc4grp { - fsl,pins = < - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x070b1 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x070b1 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x070b1 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x070b1 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x070b1 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x070b1 - MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x0b0b1 - >; - }; -}; diff --git a/sys/gnu/dts/arm/imx6q-tx6q-1036-mb7.dts b/sys/gnu/dts/arm/imx6q-tx6q-1036-mb7.dts deleted file mode 100644 index 9ffbb0fe7df..00000000000 --- a/sys/gnu/dts/arm/imx6q-tx6q-1036-mb7.dts +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Copyright 2017 Lothar Waßmann - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6q-tx6q-1036.dts" -#include "imx6qdl-tx6-mb7.dtsi" - -/ { - model = "Ka-Ro electronics TX6Q-1036 Module on MB7 baseboard"; -}; diff --git a/sys/gnu/dts/arm/imx6q-tx6q-1036.dts b/sys/gnu/dts/arm/imx6q-tx6q-1036.dts deleted file mode 100644 index cb2fcb4896c..00000000000 --- a/sys/gnu/dts/arm/imx6q-tx6q-1036.dts +++ /dev/null @@ -1,86 +0,0 @@ -/* - * Copyright 2014-2017 Lothar Waßmann - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6q.dtsi" -#include "imx6qdl-tx6.dtsi" -#include "imx6qdl-tx6-lcd.dtsi" - -/ { - model = "Ka-Ro electronics TX6Q-1036 Module"; - compatible = "karo,imx6q-tx6q", "fsl,imx6q"; -}; - -&ds1339 { - status = "disabled"; -}; - -&gpmi { - status = "disabled"; -}; - -&ipu2 { - status = "disabled"; -}; - -&usdhc4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc4>; - bus-width = <4>; - non-removable; - no-1-8-v; - fsl,wp-controller; - status = "okay"; -}; - -&iomuxc { - pinctrl_usdhc4: usdhc4grp { - fsl,pins = < - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x070b1 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x070b1 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x070b1 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x070b1 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x070b1 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x070b1 - MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x0b0b1 - >; - }; -}; diff --git a/sys/gnu/dts/arm/imx6q-tx6q-10x0-mb7.dts b/sys/gnu/dts/arm/imx6q-tx6q-10x0-mb7.dts deleted file mode 100644 index d43a5d8f174..00000000000 --- a/sys/gnu/dts/arm/imx6q-tx6q-10x0-mb7.dts +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Copyright 2017 Lothar Waßmann - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6q-tx6q-1010.dts" -#include "imx6qdl-tx6-mb7.dtsi" - -/ { - model = "Ka-Ro electronics TX6Q-1010/-1030 Module on MB7 baseboard"; -}; diff --git a/sys/gnu/dts/arm/imx6q-tx6q-1110.dts b/sys/gnu/dts/arm/imx6q-tx6q-1110.dts deleted file mode 100644 index f7b0acb6535..00000000000 --- a/sys/gnu/dts/arm/imx6q-tx6q-1110.dts +++ /dev/null @@ -1,58 +0,0 @@ -/* - * Copyright 2014-2017 Lothar Waßmann - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6q.dtsi" -#include "imx6qdl-tx6.dtsi" -#include "imx6qdl-tx6-lvds.dtsi" - -/ { - model = "Ka-Ro electronics TX6Q-1110/-1130 Module"; - compatible = "karo,imx6q-tx6q", "fsl,imx6q"; -}; - -&ipu2 { - status = "disabled"; -}; - -&sata { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx6q-tx6q-11x0-mb7.dts b/sys/gnu/dts/arm/imx6q-tx6q-11x0-mb7.dts deleted file mode 100644 index 387edf2b3f9..00000000000 --- a/sys/gnu/dts/arm/imx6q-tx6q-11x0-mb7.dts +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Copyright 2016-2017 Lothar Waßmann - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6q-tx6q-1110.dts" -#include "imx6qdl-tx6-mb7.dtsi" - -/ { - model = "Ka-Ro electronics TX6Q-1110/-1130 Module on MB7 baseboard"; -}; diff --git a/sys/gnu/dts/arm/imx6q-udoo.dts b/sys/gnu/dts/arm/imx6q-udoo.dts deleted file mode 100644 index 52e9f4a211d..00000000000 --- a/sys/gnu/dts/arm/imx6q-udoo.dts +++ /dev/null @@ -1,18 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2013 Freescale Semiconductor, Inc. - * - * Author: Fabio Estevam - */ -/dts-v1/; -#include "imx6q.dtsi" -#include "imx6qdl-udoo.dtsi" - -/ { - model = "Udoo i.MX6 Quad Board"; - compatible = "udoo,imx6q-udoo", "fsl,imx6q"; -}; - -&sata { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx6q-utilite-pro.dts b/sys/gnu/dts/arm/imx6q-utilite-pro.dts deleted file mode 100644 index d16ff2083d6..00000000000 --- a/sys/gnu/dts/arm/imx6q-utilite-pro.dts +++ /dev/null @@ -1,355 +0,0 @@ -/* - * Copyright 2013 CompuLab Ltd. - * Copyright 2016 Christopher Spinrath - * - * Based on the devicetree distributed with the vendor kernel for the - * Utilite Pro: - * Copyright 2013 CompuLab Ltd. - * Author: Valentin Raevsky - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include -#include "imx6q-cm-fx6.dts" - -/ { - model = "CompuLab Utilite Pro"; - compatible = "compulab,utilite-pro", "compulab,cm-fx6", "fsl,imx6q"; - - aliases { - ethernet1 = ð1; - rtc0 = &em3027; - rtc1 = &snvs_rtc; - }; - - encoder { - compatible = "ti,tfp410"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - tfp410_in: endpoint { - remote-endpoint = <¶llel_display_out>; - }; - }; - - port@1 { - reg = <1>; - - tfp410_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; - }; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_keys>; - - power { - label = "Power Button"; - gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hpd>; - type = "a"; - ddc-i2c-bus = <&i2c_dvi_ddc>; - hpd-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&tfp410_out>; - }; - }; - }; - - i2cmux { - compatible = "i2c-mux-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1mux>; - #address-cells = <1>; - #size-cells = <0>; - - mux-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; - i2c-parent = <&i2c1>; - - i2c@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; - - em3027: rtc@56 { - compatible = "emmicro,em3027"; - reg = <0x56>; - }; - }; - - i2c_dvi_ddc: i2c@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - parallel-display { - compatible = "fsl,imx-parallel-display"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu1>; - - interface-pix-fmt = "rgb24"; - - port@0 { - reg = <0>; - - parallel_display_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - - port@1 { - reg = <1>; - - parallel_display_out: endpoint { - remote-endpoint = <&tfp410_in>; - }; - }; - }; -}; - -/* - * A single IPU is not able to drive both display interfaces available on the - * Utilite Pro at high resolution due to its bandwidth limitation. Since the - * tfp410 encoder is wired up to IPU1, sever the link between IPU1 and the - * SoC-internal Designware HDMI encoder forcing the latter to be connected to - * IPU2 instead of IPU1. - */ -/delete-node/&ipu1_di0_hdmi; -/delete-node/&hdmi_mux_0; -/delete-node/&ipu1_di1_hdmi; -/delete-node/&hdmi_mux_1; - -&hdmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hdmicec>; - ddc-i2c-bus = <&i2c2>; - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&iomuxc { - pinctrl_gpio_keys: gpio_keysgrp { - fsl,pins = < - MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 - >; - }; - - pinctrl_hdmicec: hdmicecgrp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 - >; - }; - - pinctrl_hpd: hpdgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c1mux: i2c1muxgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_ipu1: ipu1grp { - fsl,pins = < - MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x38 - MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x38 - MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x38 - MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x38 - MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x38 - MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x38 - MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x38 - MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x38 - MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x38 - MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x38 - MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x38 - MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x38 - MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x38 - MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x38 - MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x38 - MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x38 - MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x38 - MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x38 - MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x38 - MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x38 - MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x38 - MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x38 - MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x38 - MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x38 - MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x38 - MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x38 - MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x38 - MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x38 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_GPIO_7__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_GPIO_8__UART2_RX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1 - MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3grp-100mhz { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170B9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100B9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170B9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170B9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170B9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170B9 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3grp-200mhz { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170F9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100F9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170F9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170F9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170F9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170F9 - >; - }; -}; - -&ipu1_di0_disp0 { - remote-endpoint = <¶llel_display_in>; -}; - -&pcie { - pcie@0,0 { - reg = <0x000000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - - /* non-removable i211 ethernet card */ - eth1: intel,i211@pcie0,0 { - reg = <0x010000 0 0 0 0>; - }; - }; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - uart-has-rtscts; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - no-1-8-v; - broken-cd; - keep-power-in-suspend; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx6q-var-dt6customboard.dts b/sys/gnu/dts/arm/imx6q-var-dt6customboard.dts deleted file mode 100644 index c54362fcc50..00000000000 --- a/sys/gnu/dts/arm/imx6q-var-dt6customboard.dts +++ /dev/null @@ -1,234 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Support for Variscite DART-MX6 Carrier-board - * - * Copyright 2017 BayLibre, SAS - * Author: Neil Armstrong - */ - -/dts-v1/; - -#include "imx6q.dtsi" -#include "imx6qdl-var-dart.dtsi" -#include - -/ { - model = "Variscite DART-MX6 Carrier-board"; - compatible = "variscite,dt6customboard", "fsl,imx6q"; - - backlight_lvds: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm2 0 50000>; - brightness-levels = <0 4 8 16 32 64 128 248>; - default-brightness-level = <7>; - status = "okay"; - }; - - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - - back { - gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "Key Back"; - linux,input-type = <1>; - debounce-interval = <100>; - wakeup-source; - }; - - home { - gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "Key Home"; - linux,input-type = <1>; - debounce-interval = <100>; - wakeup-source; - }; - - menu { - gpios = <&gpio4 25 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "Key Menu"; - linux,input-type = <1>; - debounce-interval = <100>; - wakeup-source; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - led1 { - gpios = <&gpio4 27 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - - led2 { - gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - }; - }; - - panel1: lvds-panel { - compatible = "sgd,gktw70sdae4se", "panel-lvds"; - backlight = <&backlight_lvds>; - width-mm = <153>; - height-mm = <86>; - label = "gktw70sdae4se"; - data-mapping = "jeida-18"; - - panel-timing { - clock-frequency = <32000000>; - hactive = <800>; - vactive = <480>; - hback-porch = <39>; - hfront-porch = <39>; - vback-porch = <29>; - vfront-porch = <13>; - hsync-len = <47>; - vsync-len = <2>; - }; - - port { - panel_in: endpoint { - remote-endpoint = <&lvds1_out>; - }; - }; - }; - - reg_usb_h1_vbus: regulator-usbh1vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usb_otg_vbus: regulator-usbotgvbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "dt6-customboard-audio"; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&sound_codec>; - simple-audio-card,frame-master = <&sound_codec>; - simple-audio-card,widgets = "Headphone", "Headphone Jack", - "Line", "Line In"; - simple-audio-card,routing = "Headphone Jack", "HPLOUT", - "Headphone Jack", "HPROUT", - "LINE1L", "Line In", - "LINE1R", "Line In"; - - sound_cpu: simple-audio-card,cpu { - sound-dai = <&ssi2>; - }; - - sound_codec: simple-audio-card,codec { - sound-dai = <&tlv320aic3106>; - clocks = <&clks IMX6QDL_CLK_CKO>; - }; - }; -}; - -&can1 { - status = "okay"; -}; - -&ecspi1 { - cs-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH>, - <&gpio4 10 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&fec { - status = "okay"; - phy-mode = "rgmii"; - phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; -}; - -&hdmi { - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - status = "okay"; -}; - -&i2c3 { - clock-frequency = <100000>; - status = "okay"; - - touchscreen@38 { - compatible = "edt,edt-ft5x06"; - reg = <0x38>; - interrupt-parent = <&gpio1>; - interrupts = <4 IRQ_TYPE_EDGE_FALLING>; - touchscreen-size-x = <800>; - touchscreen-size-y = <480>; - touchscreen-inverted-x; - touchscreen-inverted-y; - wakeup-source; - }; - - rtc@68 { - compatible = "isil,isl12057"; - reg = <0x68>; - }; -}; - -&ldb { - status = "okay"; - - lvds-channel@1 { - status = "okay"; - - port@4 { - reg = <4>; - - lvds1_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; -}; - -&pwm2 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usb_h1_vbus>; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - dr_mode = "otg"; - srp-disable; - hnp-disable; - adp-disable; - status = "okay"; -}; - -&usdhc2 { - cd-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx6q-wandboard-revb1.dts b/sys/gnu/dts/arm/imx6q-wandboard-revb1.dts deleted file mode 100644 index f6ccbecff92..00000000000 --- a/sys/gnu/dts/arm/imx6q-wandboard-revb1.dts +++ /dev/null @@ -1,23 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2013 Freescale Semiconductor, Inc. - * - * Author: Fabio Estevam - */ -/dts-v1/; -#include "imx6q.dtsi" -#include "imx6qdl-wandboard-revb1.dtsi" - -/ { - model = "Wandboard i.MX6 Quad Board rev B1"; - compatible = "wand,imx6q-wandboard", "fsl,imx6q"; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x80000000>; - }; -}; - -&sata { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx6q-wandboard-revd1.dts b/sys/gnu/dts/arm/imx6q-wandboard-revd1.dts deleted file mode 100644 index 55331021d80..00000000000 --- a/sys/gnu/dts/arm/imx6q-wandboard-revd1.dts +++ /dev/null @@ -1,23 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2013 Freescale Semiconductor, Inc. - * - * Author: Fabio Estevam - */ -/dts-v1/; -#include "imx6q.dtsi" -#include "imx6qdl-wandboard-revd1.dtsi" - -/ { - model = "Wandboard i.MX6 Quad Board revD1"; - compatible = "wand,imx6q-wandboard", "fsl,imx6q"; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x80000000>; - }; -}; - -&sata { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx6q-wandboard.dts b/sys/gnu/dts/arm/imx6q-wandboard.dts deleted file mode 100644 index 0be548beef8..00000000000 --- a/sys/gnu/dts/arm/imx6q-wandboard.dts +++ /dev/null @@ -1,23 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2013 Freescale Semiconductor, Inc. - * - * Author: Fabio Estevam - */ -/dts-v1/; -#include "imx6q.dtsi" -#include "imx6qdl-wandboard-revc1.dtsi" - -/ { - model = "Wandboard i.MX6 Quad Board"; - compatible = "wand,imx6q-wandboard", "fsl,imx6q"; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x80000000>; - }; -}; - -&sata { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx6q-zii-rdu2.dts b/sys/gnu/dts/arm/imx6q-zii-rdu2.dts deleted file mode 100644 index a1c5e69d81b..00000000000 --- a/sys/gnu/dts/arm/imx6q-zii-rdu2.dts +++ /dev/null @@ -1,20 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2016-2017 Zodiac Inflight Innovations - */ - -/dts-v1/; - -#include "imx6q.dtsi" -#include "imx6qdl-zii-rdu2.dtsi" - -/ { - model = "ZII RDU2 Board"; - compatible = "zii,imx6q-zii-rdu2", "fsl,imx6q"; - - /* Will be filled by the bootloader */ - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0>; - }; -}; diff --git a/sys/gnu/dts/arm/imx6q.dtsi b/sys/gnu/dts/arm/imx6q.dtsi deleted file mode 100644 index 9d3be1cc6b6..00000000000 --- a/sys/gnu/dts/arm/imx6q.dtsi +++ /dev/null @@ -1,546 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// -// Copyright 2013 Freescale Semiconductor, Inc. - -#include -#include "imx6q-pinfunc.h" -#include "imx6qdl.dtsi" - -/ { - aliases { - ipu1 = &ipu2; - spi4 = &ecspi5; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - reg = <0>; - next-level-cache = <&L2>; - operating-points = < - /* kHz uV */ - 1200000 1275000 - 996000 1250000 - 852000 1250000 - 792000 1175000 - 396000 975000 - >; - fsl,soc-operating-points = < - /* ARM kHz SOC-PU uV */ - 1200000 1275000 - 996000 1250000 - 852000 1250000 - 792000 1175000 - 396000 1175000 - >; - clock-latency = <61036>; /* two CLK32 periods */ - #cooling-cells = <2>; - clocks = <&clks IMX6QDL_CLK_ARM>, - <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, - <&clks IMX6QDL_CLK_STEP>, - <&clks IMX6QDL_CLK_PLL1_SW>, - <&clks IMX6QDL_CLK_PLL1_SYS>; - clock-names = "arm", "pll2_pfd2_396m", "step", - "pll1_sw", "pll1_sys"; - arm-supply = <®_arm>; - pu-supply = <®_pu>; - soc-supply = <®_soc>; - }; - - cpu1: cpu@1 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - reg = <1>; - next-level-cache = <&L2>; - operating-points = < - /* kHz uV */ - 1200000 1275000 - 996000 1250000 - 852000 1250000 - 792000 1175000 - 396000 975000 - >; - fsl,soc-operating-points = < - /* ARM kHz SOC-PU uV */ - 1200000 1275000 - 996000 1250000 - 852000 1250000 - 792000 1175000 - 396000 1175000 - >; - clock-latency = <61036>; /* two CLK32 periods */ - #cooling-cells = <2>; - clocks = <&clks IMX6QDL_CLK_ARM>, - <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, - <&clks IMX6QDL_CLK_STEP>, - <&clks IMX6QDL_CLK_PLL1_SW>, - <&clks IMX6QDL_CLK_PLL1_SYS>; - clock-names = "arm", "pll2_pfd2_396m", "step", - "pll1_sw", "pll1_sys"; - arm-supply = <®_arm>; - pu-supply = <®_pu>; - soc-supply = <®_soc>; - }; - - cpu2: cpu@2 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - reg = <2>; - next-level-cache = <&L2>; - operating-points = < - /* kHz uV */ - 1200000 1275000 - 996000 1250000 - 852000 1250000 - 792000 1175000 - 396000 975000 - >; - fsl,soc-operating-points = < - /* ARM kHz SOC-PU uV */ - 1200000 1275000 - 996000 1250000 - 852000 1250000 - 792000 1175000 - 396000 1175000 - >; - clock-latency = <61036>; /* two CLK32 periods */ - #cooling-cells = <2>; - clocks = <&clks IMX6QDL_CLK_ARM>, - <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, - <&clks IMX6QDL_CLK_STEP>, - <&clks IMX6QDL_CLK_PLL1_SW>, - <&clks IMX6QDL_CLK_PLL1_SYS>; - clock-names = "arm", "pll2_pfd2_396m", "step", - "pll1_sw", "pll1_sys"; - arm-supply = <®_arm>; - pu-supply = <®_pu>; - soc-supply = <®_soc>; - }; - - cpu3: cpu@3 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - reg = <3>; - next-level-cache = <&L2>; - operating-points = < - /* kHz uV */ - 1200000 1275000 - 996000 1250000 - 852000 1250000 - 792000 1175000 - 396000 975000 - >; - fsl,soc-operating-points = < - /* ARM kHz SOC-PU uV */ - 1200000 1275000 - 996000 1250000 - 852000 1250000 - 792000 1175000 - 396000 1175000 - >; - clock-latency = <61036>; /* two CLK32 periods */ - #cooling-cells = <2>; - clocks = <&clks IMX6QDL_CLK_ARM>, - <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, - <&clks IMX6QDL_CLK_STEP>, - <&clks IMX6QDL_CLK_PLL1_SW>, - <&clks IMX6QDL_CLK_PLL1_SYS>; - clock-names = "arm", "pll2_pfd2_396m", "step", - "pll1_sw", "pll1_sys"; - arm-supply = <®_arm>; - pu-supply = <®_pu>; - soc-supply = <®_soc>; - }; - }; - - soc { - ocram: sram@900000 { - compatible = "mmio-sram"; - reg = <0x00900000 0x40000>; - clocks = <&clks IMX6QDL_CLK_OCRAM>; - }; - - aips-bus@2000000 { /* AIPS1 */ - spba-bus@2000000 { - ecspi5: spi@2018000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; - reg = <0x02018000 0x4000>; - interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6Q_CLK_ECSPI5>, - <&clks IMX6Q_CLK_ECSPI5>; - clock-names = "ipg", "per"; - dmas = <&sdma 11 8 1>, <&sdma 12 8 2>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - }; - - iomuxc: iomuxc@20e0000 { - compatible = "fsl,imx6q-iomuxc"; - }; - }; - - sata: sata@2200000 { - compatible = "fsl,imx6q-ahci"; - reg = <0x02200000 0x4000>; - interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_SATA>, - <&clks IMX6QDL_CLK_SATA_REF_100M>, - <&clks IMX6QDL_CLK_AHB>; - clock-names = "sata", "sata_ref", "ahb"; - status = "disabled"; - }; - - gpu_vg: gpu@2204000 { - compatible = "vivante,gc"; - reg = <0x02204000 0x4000>; - interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_OPENVG_AXI>, - <&clks IMX6QDL_CLK_GPU2D_CORE>; - clock-names = "bus", "core"; - power-domains = <&pd_pu>; - #cooling-cells = <2>; - }; - - ipu2: ipu@2800000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6q-ipu"; - reg = <0x02800000 0x400000>; - interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>, - <0 7 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_IPU2>, - <&clks IMX6QDL_CLK_IPU2_DI0>, - <&clks IMX6QDL_CLK_IPU2_DI1>; - clock-names = "bus", "di0", "di1"; - resets = <&src 4>; - - ipu2_csi0: port@0 { - reg = <0>; - - ipu2_csi0_from_mipi_vc2: endpoint { - remote-endpoint = <&mipi_vc2_to_ipu2_csi0>; - }; - }; - - ipu2_csi1: port@1 { - reg = <1>; - - ipu2_csi1_from_ipu2_csi1_mux: endpoint { - remote-endpoint = <&ipu2_csi1_mux_to_ipu2_csi1>; - }; - }; - - ipu2_di0: port@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - - ipu2_di0_disp0: endpoint@0 { - reg = <0>; - }; - - ipu2_di0_hdmi: endpoint@1 { - reg = <1>; - remote-endpoint = <&hdmi_mux_2>; - }; - - ipu2_di0_mipi: endpoint@2 { - reg = <2>; - remote-endpoint = <&mipi_mux_2>; - }; - - ipu2_di0_lvds0: endpoint@3 { - reg = <3>; - remote-endpoint = <&lvds0_mux_2>; - }; - - ipu2_di0_lvds1: endpoint@4 { - reg = <4>; - remote-endpoint = <&lvds1_mux_2>; - }; - }; - - ipu2_di1: port@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - - ipu2_di1_hdmi: endpoint@1 { - reg = <1>; - remote-endpoint = <&hdmi_mux_3>; - }; - - ipu2_di1_mipi: endpoint@2 { - reg = <2>; - remote-endpoint = <&mipi_mux_3>; - }; - - ipu2_di1_lvds0: endpoint@3 { - reg = <3>; - remote-endpoint = <&lvds0_mux_3>; - }; - - ipu2_di1_lvds1: endpoint@4 { - reg = <4>; - remote-endpoint = <&lvds1_mux_3>; - }; - }; - }; - }; - - capture-subsystem { - compatible = "fsl,imx-capture-subsystem"; - ports = <&ipu1_csi0>, <&ipu1_csi1>, <&ipu2_csi0>, <&ipu2_csi1>; - }; - - display-subsystem { - compatible = "fsl,imx-display-subsystem"; - ports = <&ipu1_di0>, <&ipu1_di1>, <&ipu2_di0>, <&ipu2_di1>; - }; -}; - -&gpio1 { - gpio-ranges = <&iomuxc 0 136 2>, <&iomuxc 2 141 1>, <&iomuxc 3 139 1>, - <&iomuxc 4 142 2>, <&iomuxc 6 140 1>, <&iomuxc 7 144 2>, - <&iomuxc 9 138 1>, <&iomuxc 10 213 3>, <&iomuxc 13 20 1>, - <&iomuxc 14 19 1>, <&iomuxc 15 21 1>, <&iomuxc 16 208 1>, - <&iomuxc 17 207 1>, <&iomuxc 18 210 3>, <&iomuxc 21 209 1>, - <&iomuxc 22 116 10>; -}; - -&gpio2 { - gpio-ranges = <&iomuxc 0 191 16>, <&iomuxc 16 55 14>, <&iomuxc 30 35 1>, - <&iomuxc 31 44 1>; -}; - -&gpio3 { - gpio-ranges = <&iomuxc 0 69 16>, <&iomuxc 16 36 8>, <&iomuxc 24 45 8>; -}; - -&gpio4 { - gpio-ranges = <&iomuxc 5 149 1>, <&iomuxc 6 126 10>, <&iomuxc 16 87 16>; -}; - -&gpio5 { - gpio-ranges = <&iomuxc 0 85 1>, <&iomuxc 2 34 1>, <&iomuxc 4 53 1>, - <&iomuxc 5 103 13>, <&iomuxc 18 150 14>; -}; - -&gpio6 { - gpio-ranges = <&iomuxc 0 164 6>, <&iomuxc 6 54 1>, <&iomuxc 7 181 5>, - <&iomuxc 14 186 3>, <&iomuxc 17 170 2>, <&iomuxc 19 22 12>, - <&iomuxc 31 86 1>; -}; - -&gpio7 { - gpio-ranges = <&iomuxc 0 172 9>, <&iomuxc 9 189 2>, <&iomuxc 11 146 3>; -}; - -&gpr { - ipu1_csi0_mux { - compatible = "video-mux"; - mux-controls = <&mux 0>; - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - ipu1_csi0_mux_from_mipi_vc0: endpoint { - remote-endpoint = <&mipi_vc0_to_ipu1_csi0_mux>; - }; - }; - - port@1 { - reg = <1>; - - ipu1_csi0_mux_from_parallel_sensor: endpoint { - }; - }; - - port@2 { - reg = <2>; - - ipu1_csi0_mux_to_ipu1_csi0: endpoint { - remote-endpoint = <&ipu1_csi0_from_ipu1_csi0_mux>; - }; - }; - }; - - ipu2_csi1_mux { - compatible = "video-mux"; - mux-controls = <&mux 1>; - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - ipu2_csi1_mux_from_mipi_vc3: endpoint { - remote-endpoint = <&mipi_vc3_to_ipu2_csi1_mux>; - }; - }; - - port@1 { - reg = <1>; - - ipu2_csi1_mux_from_parallel_sensor: endpoint { - }; - }; - - port@2 { - reg = <2>; - - ipu2_csi1_mux_to_ipu2_csi1: endpoint { - remote-endpoint = <&ipu2_csi1_from_ipu2_csi1_mux>; - }; - }; - }; -}; - -&hdmi { - compatible = "fsl,imx6q-hdmi"; - - port@2 { - reg = <2>; - - hdmi_mux_2: endpoint { - remote-endpoint = <&ipu2_di0_hdmi>; - }; - }; - - port@3 { - reg = <3>; - - hdmi_mux_3: endpoint { - remote-endpoint = <&ipu2_di1_hdmi>; - }; - }; -}; - -&ipu1_csi1 { - ipu1_csi1_from_mipi_vc1: endpoint { - remote-endpoint = <&mipi_vc1_to_ipu1_csi1>; - }; -}; - -&ldb { - clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>, - <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>, - <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>, - <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>; - clock-names = "di0_pll", "di1_pll", - "di0_sel", "di1_sel", "di2_sel", "di3_sel", - "di0", "di1"; - - lvds-channel@0 { - port@2 { - reg = <2>; - - lvds0_mux_2: endpoint { - remote-endpoint = <&ipu2_di0_lvds0>; - }; - }; - - port@3 { - reg = <3>; - - lvds0_mux_3: endpoint { - remote-endpoint = <&ipu2_di1_lvds0>; - }; - }; - }; - - lvds-channel@1 { - port@2 { - reg = <2>; - - lvds1_mux_2: endpoint { - remote-endpoint = <&ipu2_di0_lvds1>; - }; - }; - - port@3 { - reg = <3>; - - lvds1_mux_3: endpoint { - remote-endpoint = <&ipu2_di1_lvds1>; - }; - }; - }; -}; - -&mipi_csi { - port@1 { - reg = <1>; - - mipi_vc0_to_ipu1_csi0_mux: endpoint { - remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc0>; - }; - }; - - port@2 { - reg = <2>; - - mipi_vc1_to_ipu1_csi1: endpoint { - remote-endpoint = <&ipu1_csi1_from_mipi_vc1>; - }; - }; - - port@3 { - reg = <3>; - - mipi_vc2_to_ipu2_csi0: endpoint { - remote-endpoint = <&ipu2_csi0_from_mipi_vc2>; - }; - }; - - port@4 { - reg = <4>; - - mipi_vc3_to_ipu2_csi1_mux: endpoint { - remote-endpoint = <&ipu2_csi1_mux_from_mipi_vc3>; - }; - }; -}; - -&mipi_dsi { - ports { - port@2 { - reg = <2>; - - mipi_mux_2: endpoint { - remote-endpoint = <&ipu2_di0_mipi>; - }; - }; - - port@3 { - reg = <3>; - - mipi_mux_3: endpoint { - remote-endpoint = <&ipu2_di1_mipi>; - }; - }; - }; -}; - -&mux { - mux-reg-masks = <0x04 0x00080000>, /* MIPI_IPU1_MUX */ - <0x04 0x00100000>, /* MIPI_IPU2_MUX */ - <0x0c 0x0000000c>, /* HDMI_MUX_CTL */ - <0x0c 0x000000c0>, /* LVDS0_MUX_CTL */ - <0x0c 0x00000300>, /* LVDS1_MUX_CTL */ - <0x28 0x00000003>, /* DCIC1_MUX_CTL */ - <0x28 0x0000000c>; /* DCIC2_MUX_CTL */ -}; - -&vpu { - compatible = "fsl,imx6q-vpu", "cnm,coda960"; -}; diff --git a/sys/gnu/dts/arm/imx6qdl-apalis.dtsi b/sys/gnu/dts/arm/imx6qdl-apalis.dtsi deleted file mode 100644 index 1b5bc6b5e80..00000000000 --- a/sys/gnu/dts/arm/imx6qdl-apalis.dtsi +++ /dev/null @@ -1,988 +0,0 @@ -/* - * Copyright 2014-2017 Toradex AG - * Copyright 2012 Freescale Semiconductor, Inc. - * Copyright 2011 Linaro Ltd. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include - -/ { - model = "Toradex Apalis iMX6Q/D Module"; - compatible = "toradex,apalis_imx6q", "fsl,imx6q"; - - /* Will be filled by the bootloader */ - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0>; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_bl_on>; - pwms = <&pwm4 0 5000000>; - enable-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; - status = "disabled"; - }; - - reg_module_3v3: regulator-module-3v3 { - compatible = "regulator-fixed"; - regulator-name = "+V3.3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_module_3v3_audio: regulator-module-3v3-audio { - compatible = "regulator-fixed"; - regulator-name = "+V3.3_AUDIO"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_usb_otg_vbus: regulator-usb-otg-vbus { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_regulator_usbotg_pwr>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; - enable-active-high; - status = "disabled"; - }; - - /* on module USB hub */ - reg_usb_host_vbus_hub: regulator-usb-host-vbus-hub { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_regulator_usbhub_pwr>; - regulator-name = "usb_host_vbus_hub"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 28 GPIO_ACTIVE_HIGH>; - startup-delay-us = <2000>; - enable-active-high; - status = "okay"; - }; - - reg_usb_host_vbus: regulator-usb-host-vbus { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_regulator_usbh_pwr>; - regulator-name = "usb_host_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <®_usb_host_vbus_hub>; - status = "disabled"; - }; - - sound { - compatible = "fsl,imx-audio-sgtl5000"; - model = "imx6q-apalis-sgtl5000"; - ssi-controller = <&ssi1>; - audio-codec = <&codec>; - audio-routing = - "LINE_IN", "Line In Jack", - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - mux-int-port = <1>; - mux-ext-port = <4>; - }; - - sound_spdif: sound-spdif { - compatible = "fsl,imx-audio-spdif"; - model = "imx-spdif"; - spdif-controller = <&spdif>; - spdif-in; - spdif-out; - status = "disabled"; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; - -&can1 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&pinctrl_flexcan1_default>; - pinctrl-1 = <&pinctrl_flexcan1_sleep>; - status = "disabled"; -}; - -&can2 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&pinctrl_flexcan2_default>; - pinctrl-1 = <&pinctrl_flexcan2_sleep>; - status = "disabled"; -}; - -/* Apalis SPI1 */ -&ecspi1 { - cs-gpios = <&gpio5 25 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - status = "disabled"; -}; - -/* Apalis SPI2 */ -&ecspi2 { - cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi2>; - status = "disabled"; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii"; - phy-handle = <ðphy>; - phy-reset-duration = <10>; - phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy: ethernet-phy@7 { - interrupt-parent = <&gpio1>; - interrupts = <30 IRQ_TYPE_LEVEL_LOW>; - reg = <7>; - }; - }; -}; - -&hdmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hdmi_ddc &pinctrl_hdmi_cec>; - status = "disabled"; -}; - -/* I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier board) */ -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c1>; - pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio5 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "disabled"; -}; - -/* - * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and - * touch screen controller - */ -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c2>; - pinctrl-1 = <&pinctrl_i2c2_gpio>; - scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; - - pmic: pfuze100@8 { - compatible = "fsl,pfuze100"; - reg = <0x08>; - - regulators { - sw1a_reg: sw1ab { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw1c_reg: sw1c { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw3a_reg: sw3a { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - regulator-boot-on; - regulator-always-on; - }; - - snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - vgen1_reg: vgen1 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - regulator-boot-on; - regulator-always-on; - }; - - vgen2_reg: vgen2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - regulator-boot-on; - regulator-always-on; - }; - - vgen3_reg: vgen3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - vgen4_reg: vgen4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - vgen5_reg: vgen5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - vgen6_reg: vgen6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; - - codec: sgtl5000@a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - clocks = <&clks IMX6QDL_CLK_CKO>; - VDDA-supply = <®_module_3v3_audio>; - VDDIO-supply = <®_module_3v3>; - VDDD-supply = <&vgen4_reg>; - }; - - /* STMPE811 touch screen controller */ - stmpe811@41 { - compatible = "st,stmpe811"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_touch_int>; - reg = <0x41>; - interrupts = <10 IRQ_TYPE_LEVEL_LOW>; - interrupt-parent = <&gpio4>; - interrupt-controller; - id = <0>; - blocks = <0x5>; - irq-trigger = <0x1>; - /* 3.25 MHz ADC clock speed */ - st,adc-freq = <1>; - /* 12-bit ADC */ - st,mod-12b = <1>; - /* internal ADC reference */ - st,ref-sel = <0>; - /* ADC converstion time: 80 clocks */ - st,sample-time = <4>; - - stmpe_touchscreen { - compatible = "st,stmpe-ts"; - /* 8 sample average control */ - st,ave-ctrl = <3>; - /* 7 length fractional part in z */ - st,fraction-z = <7>; - /* - * 50 mA typical 80 mA max touchscreen drivers - * current limit value - */ - st,i-drive = <1>; - /* 1 ms panel driver settling time */ - st,settling = <3>; - /* 5 ms touch detect interrupt delay */ - st,touch-det-delay = <5>; - }; - - stmpe_adc { - compatible = "st,stmpe-adc"; - /* forbid to use ADC channels 3-0 (touch) */ - st,norequest-mask = <0x0F>; - }; - }; -}; - -/* - * I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor on carrier - * board) - */ -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c3>; - pinctrl-1 = <&pinctrl_i2c3_gpio>; - scl-gpios = <&gpio3 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio3 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "disabled"; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "disabled"; -}; - -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm2>; - status = "disabled"; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; - status = "disabled"; -}; - -&pwm4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm4>; - status = "disabled"; -}; - -&spdif { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spdif>; - status = "disabled"; -}; - -&ssi1 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1_dte &pinctrl_uart1_ctrl>; - fsl,dte-mode; - uart-has-rtscts; - status = "disabled"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2_dte>; - fsl,dte-mode; - uart-has-rtscts; - status = "disabled"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4_dte>; - fsl,dte-mode; - status = "disabled"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5_dte>; - fsl,dte-mode; - status = "disabled"; -}; - -&usbotg { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "disabled"; -}; - -/* MMC1 */ -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1_4bit &pinctrl_usdhc1_8bit>; - vqmmc-supply = <®_module_3v3>; - bus-width = <8>; - disable-wp; - no-1-8-v; - status = "disabled"; -}; - -/* SD1 */ -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - vqmmc-supply = <®_module_3v3>; - bus-width = <4>; - disable-wp; - no-1-8-v; - status = "disabled"; -}; - -/* eMMC */ -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - vqmmc-supply = <®_module_3v3>; - bus-width = <8>; - no-1-8-v; - non-removable; - status = "okay"; -}; - -&weim { - status = "disabled"; -}; - -&iomuxc { - pinctrl_apalis_gpio1: gpio2io04grp { - fsl,pins = < - MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x130b0 - >; - }; - - pinctrl_apalis_gpio2: gpio2io05grp { - fsl,pins = < - MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x130b0 - >; - }; - - pinctrl_apalis_gpio3: gpio2io06grp { - fsl,pins = < - MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x130b0 - >; - }; - - pinctrl_apalis_gpio4: gpio2io07grp { - fsl,pins = < - MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x130b0 - >; - }; - - pinctrl_apalis_gpio5: gpio6io10grp { - fsl,pins = < - MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x130b0 - >; - }; - - pinctrl_apalis_gpio6: gpio6io09grp { - fsl,pins = < - MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x130b0 - >; - }; - - pinctrl_apalis_gpio7: gpio1io02grp { - fsl,pins = < - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x130b0 - >; - }; - - pinctrl_apalis_gpio8: gpio1io06grp { - fsl,pins = < - MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x130b0 - >; - }; - - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0 - MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x130b0 - MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0 - MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0 - /* SGTL5000 sys_mclk */ - MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x130b0 - >; - }; - - pinctrl_cam_mclk: cammclkgrp { - fsl,pins = < - /* CAM sys_mclk */ - MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x00b0 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK 0x100b1 - /* SPI1 cs */ - MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25 0x000b1 - >; - }; - - pinctrl_ecspi2: ecspi2grp { - fsl,pins = < - MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 - MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 - MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 - /* SPI2 cs */ - MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x000b1 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - /* Ethernet PHY reset */ - MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x000b0 - /* Ethernet PHY interrupt */ - MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x000b1 - >; - }; - - pinctrl_flexcan1_default: flexcan1defgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0 - MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0 - >; - }; - - pinctrl_flexcan1_sleep: flexcan1slpgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x0 - MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0 - >; - }; - - pinctrl_flexcan2_default: flexcan2defgrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0 - MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0 - >; - }; - pinctrl_flexcan2_sleep: flexcan2slpgrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x0 - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x0 - >; - }; - - pinctrl_gpio_bl_on: gpioblon { - fsl,pins = < - MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x1b0b0 - >; - }; - - pinctrl_gpio_keys: gpio1io04grp { - fsl,pins = < - /* Power button */ - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 - >; - }; - - pinctrl_hdmi_cec: hdmicecgrp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 - >; - }; - - pinctrl_hdmi_ddc: hdmiddcgrp { - fsl,pins = < - MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 - MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 - >; - }; - - pinctrl_i2c1_gpio: i2c1gpiogrp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x4001b8b1 - MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c2_gpio: i2c2gpiogrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3_gpio: i2c3gpiogrp { - fsl,pins = < - MX6QDL_PAD_EIM_D17__GPIO3_IO17 0x4001b8b1 - MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x4001b8b1 - >; - }; - - pinctrl_ipu1_csi0: ipu1csi0grp { /* parallel camera */ - fsl,pins = < - MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0xb0b1 - MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0xb0b1 - MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0xb0b1 - MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0xb0b1 - MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0xb0b1 - MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0xb0b1 - MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0xb0b1 - MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0xb0b1 - MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0xb0b1 - MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0xb0b1 - MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0xb0b1 - >; - }; - - pinctrl_ipu1_lcdif: ipu1lcdifgrp { - fsl,pins = < - MX6QDL_PAD_EIM_A16__IPU1_DI1_DISP_CLK 0x61 - /* DE */ - MX6QDL_PAD_EIM_DA10__IPU1_DI1_PIN15 0x61 - /* HSync */ - MX6QDL_PAD_EIM_DA11__IPU1_DI1_PIN02 0x61 - /* VSync */ - MX6QDL_PAD_EIM_DA12__IPU1_DI1_PIN03 0x61 - MX6QDL_PAD_EIM_DA9__IPU1_DISP1_DATA00 0x61 - MX6QDL_PAD_EIM_DA8__IPU1_DISP1_DATA01 0x61 - MX6QDL_PAD_EIM_DA7__IPU1_DISP1_DATA02 0x61 - MX6QDL_PAD_EIM_DA6__IPU1_DISP1_DATA03 0x61 - MX6QDL_PAD_EIM_DA5__IPU1_DISP1_DATA04 0x61 - MX6QDL_PAD_EIM_DA4__IPU1_DISP1_DATA05 0x61 - MX6QDL_PAD_EIM_DA3__IPU1_DISP1_DATA06 0x61 - MX6QDL_PAD_EIM_DA2__IPU1_DISP1_DATA07 0x61 - MX6QDL_PAD_EIM_DA1__IPU1_DISP1_DATA08 0x61 - MX6QDL_PAD_EIM_DA0__IPU1_DISP1_DATA09 0x61 - MX6QDL_PAD_EIM_EB1__IPU1_DISP1_DATA10 0x61 - MX6QDL_PAD_EIM_EB0__IPU1_DISP1_DATA11 0x61 - MX6QDL_PAD_EIM_A17__IPU1_DISP1_DATA12 0x61 - MX6QDL_PAD_EIM_A18__IPU1_DISP1_DATA13 0x61 - MX6QDL_PAD_EIM_A19__IPU1_DISP1_DATA14 0x61 - MX6QDL_PAD_EIM_A20__IPU1_DISP1_DATA15 0x61 - MX6QDL_PAD_EIM_A21__IPU1_DISP1_DATA16 0x61 - MX6QDL_PAD_EIM_A22__IPU1_DISP1_DATA17 0x61 - MX6QDL_PAD_EIM_A23__IPU1_DISP1_DATA18 0x61 - MX6QDL_PAD_EIM_A24__IPU1_DISP1_DATA19 0x61 - MX6QDL_PAD_EIM_D31__IPU1_DISP1_DATA20 0x61 - MX6QDL_PAD_EIM_D30__IPU1_DISP1_DATA21 0x61 - MX6QDL_PAD_EIM_D26__IPU1_DISP1_DATA22 0x61 - MX6QDL_PAD_EIM_D27__IPU1_DISP1_DATA23 0x61 - >; - }; - - pinctrl_ipu2_vdac: ipu2vdacgrp { - fsl,pins = < - MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0xd1 - MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN15 0xd1 - MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN02 0xd1 - MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN03 0xd1 - MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_DATA00 0xf9 - MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_DATA01 0xf9 - MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_DATA02 0xf9 - MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_DATA03 0xf9 - MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_DATA04 0xf9 - MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_DATA05 0xf9 - MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_DATA06 0xf9 - MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_DATA07 0xf9 - MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_DATA08 0xf9 - MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_DATA09 0xf9 - MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0_DATA10 0xf9 - MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0_DATA11 0xf9 - MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0_DATA12 0xf9 - MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0_DATA13 0xf9 - MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0_DATA14 0xf9 - MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DATA15 0xf9 - >; - }; - - pinctrl_mmc_cd: gpiommccdgrp { - fsl,pins = < - /* MMC1 CD */ - MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x000b0 - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm4: pwm4grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1 - >; - }; - - pinctrl_regulator_usbh_pwr: gpioregusbhpwrgrp { - fsl,pins = < - /* USBH_EN */ - MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x0f058 - >; - }; - - pinctrl_regulator_usbhub_pwr: gpioregusbhubpwrgrp { - fsl,pins = < - /* USBH_HUB_EN */ - MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x0f058 - >; - }; - - pinctrl_regulator_usbotg_pwr: gpioregusbotgpwrgrp { - fsl,pins = < - /* USBO1 power en */ - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x0f058 - >; - }; - - pinctrl_reset_moci: gpioresetmocigrp { - fsl,pins = < - /* RESET_MOCI control */ - MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x0f058 - >; - }; - - pinctrl_sd_cd: gpiosdcdgrp { - fsl,pins = < - /* SD1 CD */ - MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x000b0 - >; - }; - - pinctrl_spdif: spdifgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0 - MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0 - >; - }; - - pinctrl_touch_int: gpiotouchintgrp { - fsl,pins = < - /* STMPE811 interrupt */ - MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 - >; - }; - - pinctrl_uart1_dce: uart1dcegrp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 - >; - }; - - /* DTE mode */ - pinctrl_uart1_dte: uart1dtegrp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x1b0b1 - MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x1b0b1 - >; - }; - - /* Additional DTR, DSR, DCD */ - pinctrl_uart1_ctrl: uart1ctrlgrp { - fsl,pins = < - MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x1b0b0 - MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x1b0b0 - MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0 - >; - }; - - pinctrl_uart2_dce: uart2dcegrp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 - >; - }; - - /* DTE mode */ - pinctrl_uart2_dte: uart2dtegrp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x1b0b1 - MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 0x1b0b1 - >; - }; - - pinctrl_uart4_dce: uart4dcegrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 - >; - }; - - /* DTE mode */ - pinctrl_uart4_dte: uart4dtegrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__UART4_RX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW0__UART4_TX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart5_dce: uart5dcegrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 - >; - }; - - /* DTE mode */ - pinctrl_uart5_dte: uart5dtegrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__UART5_RX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW1__UART5_TX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 - >; - }; - - pinctrl_usdhc1_4bit: usdhc1grp_4bit { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071 - >; - }; - - pinctrl_usdhc1_8bit: usdhc1grp_8bit { - fsl,pins = < - MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x17071 - MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x17071 - MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x17071 - MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x17071 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17071 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10071 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17071 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17071 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17071 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17071 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 - /* eMMC reset */ - MX6QDL_PAD_SD3_RST__SD3_RESET 0x17059 - >; - }; -}; diff --git a/sys/gnu/dts/arm/imx6qdl-apf6.dtsi b/sys/gnu/dts/arm/imx6qdl-apf6.dtsi deleted file mode 100644 index b78ed7974ea..00000000000 --- a/sys/gnu/dts/arm/imx6qdl-apf6.dtsi +++ /dev/null @@ -1,152 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -// -// Copyright 2015 Armadeus Systems - -#include -#include - -/ { - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-name = "1P8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - vin-supply = <®_3p3v>; - }; - - usdhc1_pwrseq: usdhc1-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio2 8 GPIO_ACTIVE_LOW>; - post-power-on-delay-ms = <15>; - power-off-delay-us = <70>; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii-id"; - phy-reset-duration = <10>; - phy-reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; - phy-handle = <ðphy1>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy1: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - interrupt-parent = <&gpio1>; - interrupts = <28 IRQ_TYPE_LEVEL_LOW>; - status = "okay"; - }; - }; -}; - -/* Bluetooth */ -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - uart-has-rtscts; - status = "okay"; -}; - -/* Wi-Fi */ -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - bus-width = <4>; - mmc-pwrseq = <&usdhc1_pwrseq>; - vmmc-supply = <®_3p3v>; - vqmmc-supply = <®_1p8v>; - cap-power-off-card; - keep-power-in-suspend; - non-removable; - status = "okay"; - - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@2 { - compatible = "ti,wl1271"; - reg = <2>; - interrupt-parent = <&gpio2>; - interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; - ref-clock-frequency = <38400000>; - tcxo-clock-frequency = <38400000>; - }; -}; - -/* eMMC */ -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - bus-width = <8>; - no-1-8-v; - non-removable; - status = "okay"; -}; - -&iomuxc { - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b8b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x130b0 - MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x130b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x13030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1f030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1f030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b0 - MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b0 - MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b0 - MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b0 - MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x130b0 /* BT_EN */ - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 - MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x130b0 /* WL_EN */ - MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x130b0 /* WL_IRQ */ - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 - >; - }; -}; diff --git a/sys/gnu/dts/arm/imx6qdl-apf6dev.dtsi b/sys/gnu/dts/arm/imx6qdl-apf6dev.dtsi deleted file mode 100644 index b8e74ab3c99..00000000000 --- a/sys/gnu/dts/arm/imx6qdl-apf6dev.dtsi +++ /dev/null @@ -1,450 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -// -// Copyright 2015 Armadeus Systems - -#include -#include -#include - -/ { - chosen { - stdout-path = &uart4; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm3 0 191000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <0>; - power-supply = <®_5v>; - }; - - disp0 { - compatible = "fsl,imx-parallel-display"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu1_disp0>; - - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - display_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - - port@1 { - reg = <1>; - - display_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_keys>; - - user-button { - label = "User button"; - gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - user-led { - label = "User LED"; - gpios = <&gpio7 12 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - default-state = "on"; - }; - }; - - panel { - compatible = "armadeus,st0700-adapt"; - power-supply = <®_3p3v>; - backlight = <&backlight>; - - port { - panel_in: endpoint { - remote-endpoint = <&display_out>; - }; - }; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - vin-supply = <®_5v>; - }; - - reg_5v: regulator-5v { - compatible = "regulator-fixed"; - regulator-name = "5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - reg_usb_otg_vbus: regulator-usb-otg-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - sound { - compatible = "fsl,imx6-armadeus-sgtl5000", - "fsl,imx-audio-sgtl5000"; - model = "imx6-armadeus-sgtl5000"; - ssi-controller = <&ssi1>; - audio-codec = <&codec>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - mux-int-port = <1>; - mux-ext-port = <3>; - }; - - sound-spdif { - compatible = "fsl,imx-audio-spdif"; - model = "imx-spdif"; - spdif-controller = <&spdif>; - spdif-out; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; - -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - xceiver-supply = <®_5v>; - status = "okay"; -}; - -&ecspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - cs-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>, - <&gpio4 10 GPIO_ACTIVE_LOW>, - <&gpio4 11 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c3>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - touchscreen@48 { - compatible = "semtech,sx8654"; - reg = <0x48>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_touchscreen>; - interrupt-parent = <&gpio6>; - interrupts = <3 IRQ_TYPE_EDGE_FALLING>; - }; -}; - -&i2c2 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - codec: sgtl5000@a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - clocks = <&clks IMX6QDL_CLK_CKO>; - VDDA-supply = <®_3p3v>; - VDDIO-supply = <®_3p3v>; - }; - - rtc@6f { - compatible = "microchip,mcp7940x"; - reg = <0x6f>; - }; -}; - -&i2c3 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; -}; - -&ipu1_di0_disp0 { - remote-endpoint = <&display_in>; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio6 2 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; - status = "okay"; -}; - -/* GPS */ -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -/* GSM */ -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3 &pinctrl_gsm>; - uart-has-rtscts; - status = "okay"; -}; - -/* console */ -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_5v>; - phy_type = "utmi"; - status = "okay"; -}; - -&usbotg { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - vbus-supply = <®_usb_otg_vbus>; - dr_mode = "otg"; - status = "okay"; -}; - -/* microSD */ -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - cd-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; - no-1-8-v; - status = "okay"; -}; - -&spdif { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spdif>; - status = "okay"; -}; - -&ssi1 { - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpios>; - - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x1b0b0 - MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x1b0b0 - MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x1b0b0 - MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x1b0b0 - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1 - MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0 - MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0 - MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 - >; - }; - - pinctrl_flexcan2: flexcan2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0 - MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0 - >; - }; - - pinctrl_gpio_keys: gpiokeysgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 - >; - }; - - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x130b0 - >; - }; - - pinctrl_gpios: gpiosgrp { - fsl,pins = < - MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x100b1 - MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x100b1 - MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x100b1 - MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x100b1 - MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x100b1 - MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x100b1 - MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x100b1 - MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x100b1 - MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x100b1 - >; - }; - - pinctrl_gsm: gsmgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x130b0 /* GSM_POKIN */ - MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x130b0 /* GSM_PWR_EN */ - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 - MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 - >; - }; - - pinctrl_ipu1_disp0: ipu1disp0grp { - fsl,pins = < - MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x100b1 - MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x100b1 - MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x100b1 - MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x100b1 - MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x100b1 - MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x100b1 - MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x100b1 - MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x100b1 - MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x100b1 - MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x100b1 - MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x100b1 - MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x100b1 - MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x100b1 - MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x100b1 - MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x100b1 - MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x100b1 - MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x100b1 - MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x100b1 - MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x100b1 - MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x100b1 - MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x100b1 - MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x100b1 - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT16__GPIO6_IO02 0x130b0 - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b0 - MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b0 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b0 - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b0 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b0 - MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b0 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b0 - MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b0 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x1b0b0 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 - >; - }; - - pinctrl_spdif: spdifgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x1b0b0 - >; - }; - - pinctrl_touchscreen: touchscreengrp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x1b0b0 - >; - }; -}; diff --git a/sys/gnu/dts/arm/imx6qdl-aristainetos.dtsi b/sys/gnu/dts/arm/imx6qdl-aristainetos.dtsi deleted file mode 100644 index d954661fa05..00000000000 --- a/sys/gnu/dts/arm/imx6qdl-aristainetos.dtsi +++ /dev/null @@ -1,408 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * support fot the imx6 based aristainetos board - * - * Copyright (C) 2014 Heiko Schocher - */ - -#include - -/ { - - reg_2p5v: regulator-2p5v { - compatible = "regulator-fixed"; - regulator-name = "2P5V"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_usbh1_vbus: regulator-usbh1-vbus { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_aristainetos_usbh1_vbus>; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_usbotg_vbus: regulator-usbotg-vbus { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_aristainetos_usbotg_vbus>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - status = "okay"; -}; - -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - tmp103: tmp103@71 { - compatible = "ti,tmp103"; - reg = <0x71>; - }; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - rtc@68 { - compatible = "dallas,m41t00"; - reg = <0x68>; - }; -}; - -&ecspi4 { - cs-gpios = <&gpio3 20 0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi4>; - status = "okay"; - - flash: m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "micron,n25q128a11", "jedec,spi-nor"; - spi-max-frequency = <20000000>; - reg = <0>; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rmii"; - phy-reset-gpios = <&gpio3 29 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - status = "okay"; -}; - -&pcie { - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - uart-has-rtscts; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - uart-has-rtscts; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usbh1_vbus>; - dr_mode = "host"; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usbotg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - dr_mode = "host"; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - vmmc-supply = <®_3p3v>; - cd-gpios = <&gpio4 7 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - vmmc-supply = <®_3p3v>; - cd-gpios = <&gpio4 8 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog &pinctrl_gpio>; - - imx6qdl-aristainetos { - pinctrl_aristainetos_usbh1_vbus: aristainetos-usbh1-vbus { - fsl,pins = ; - }; - - pinctrl_aristainetos_usbotg_vbus: aristainetos-usbotg-vbus { - fsl,pins = ; - }; - - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x1b0b0 - MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x1b0b0 - MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x1b0b0 - MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x1b0b0 - >; - }; - - pinctrl_backlight: backlightgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b0 - MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b0 - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 - >; - }; - - pinctrl_ecspi2: ecspi2grp { - fsl,pins = < - MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 - MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 - MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 - MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x100b1 - >; - }; - - pinctrl_ecspi4: ecspi4grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1 - MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1 - MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1 - MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x100b1 - MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x1b0b0 /* WP pin */ - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 - MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 - MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 - MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 - MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 - MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 - MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0 - MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0 - >; - }; - - pinctrl_flexcan2: flexcan2grp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x1b0b0 - MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x1b0b0 - >; - }; - - pinctrl_gpio: gpiogrp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0 - MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b0 - MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x1b0b0 - MX6QDL_PAD_SD4_DAT5__GPIO2_IO13 0x1b0b0 - MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x1b0b0 - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 - MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0 - MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0 - MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 - MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 - MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 - >; - }; - - pinctrl_gpmi_nand: gpminandgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 - MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 - >; - }; - - pinctrl_hog: hoggrp { - fsl,pins = < - MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x10 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 - MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_ipu_disp: ipudisp1grp { - fsl,pins = < - MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 - MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 - MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 - MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 - MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x20000 - MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 - MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 - MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 - MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 - MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 - MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 - MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 - MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 - MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 - MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 - MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 - MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 - MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 - MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 - MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 - MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 - MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 - MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 - MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 - MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 - MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 - MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 - MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 - MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1 - MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 - MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 - MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x1b0b0 - >; - }; - }; -}; diff --git a/sys/gnu/dts/arm/imx6qdl-aristainetos2.dtsi b/sys/gnu/dts/arm/imx6qdl-aristainetos2.dtsi deleted file mode 100644 index 376750882ed..00000000000 --- a/sys/gnu/dts/arm/imx6qdl-aristainetos2.dtsi +++ /dev/null @@ -1,626 +0,0 @@ -/* - * support for the imx6 based aristainetos2 board - * - * Copyright (C) 2015 Heiko Schocher - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -#include -#include - -/ { - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <7>; - enable-gpios = <&gpio6 31 GPIO_ACTIVE_HIGH>; - }; - - reg_2p5v: regulator-2p5v { - compatible = "regulator-fixed"; - regulator-name = "2P5V"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_usbh1_vbus: regulator-usbh1-vbus { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_aristainetos2_usbh1_vbus>; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_usbotg_vbus: regulator-usbotg-vbus { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_aristainetos2_usbotg_vbus>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - status = "okay"; -}; - -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - status = "okay"; -}; - -&ecspi1 { - cs-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH - &gpio4 10 GPIO_ACTIVE_HIGH - &gpio4 11 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - status = "okay"; -}; - -&ecspi2 { - cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH &gpio2 27 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi2>; - status = "okay"; -}; - -&ecspi4 { - cs-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH &gpio5 2 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi4>; - status = "okay"; - - flash: m25p80@1 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "micron,n25q128a11", "jedec,spi-nor"; - spi-max-frequency = <20000000>; - reg = <1>; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pmic@58 { - compatible = "dlg,da9063"; - reg = <0x58>; - interrupt-parent = <&gpio1>; - interrupts = <04 0x8>; - - regulators { - bcore1 { - regulator-name = "bcore1"; - regulator-always-on = <1>; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <3300000>; - }; - - bcore2 { - regulator-name = "bcore2"; - regulator-always-on = <1>; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <3300000>; - }; - - bpro { - regulator-name = "bpro"; - regulator-always-on = <1>; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <3300000>; - }; - - bperi { - regulator-name = "bperi"; - regulator-always-on = <1>; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <3300000>; - }; - - bmem { - regulator-name = "bmem"; - regulator-always-on = <1>; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo2 { - regulator-name = "ldo2"; - regulator-always-on = <1>; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1800000>; - }; - - ldo3 { - regulator-name = "ldo3"; - regulator-always-on = <1>; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo4 { - regulator-name = "ldo4"; - regulator-always-on = <1>; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo5 { - regulator-name = "ldo5"; - regulator-always-on = <1>; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo6 { - regulator-name = "ldo6"; - regulator-always-on = <1>; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo7 { - regulator-name = "ldo7"; - regulator-always-on = <1>; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo8 { - regulator-name = "ldo8"; - regulator-always-on = <1>; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo9 { - regulator-name = "ldo9"; - regulator-always-on = <1>; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo10 { - regulator-name = "ldo10"; - regulator-always-on = <1>; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo11 { - regulator-name = "ldo11"; - regulator-always-on = <1>; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <3300000>; - }; - - bio { - regulator-name = "bio"; - regulator-always-on = <1>; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - }; - }; - - tmp103: tmp103@71 { - compatible = "ti,tmp103"; - reg = <0x71>; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - expander: tca6416@20 { - compatible = "ti,tca6416"; - reg = <0x20>; - #gpio-cells = <2>; - gpio-controller; - }; - - rtc@68 { - compatible = "dallas,m41t00"; - reg = <0x68>; - }; -}; - -&i2c4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4>; - status = "okay"; - - eeprom@50{ - compatible = "atmel,24c64"; - reg = <0x50>; - }; - - eeprom@57{ - compatible = "atmel,24c64"; - reg = <0x57>; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii"; - phy-reset-gpios = <&gpio7 18 GPIO_ACTIVE_LOW>; - txd0-skew-ps = <0>; - txd1-skew-ps = <0>; - txd2-skew-ps = <0>; - txd3-skew-ps = <0>; - status = "okay"; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - status = "okay"; -}; - -&pcie { - reset-gpio = <&gpio2 16 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - uart-has-rtscts; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - uart-has-rtscts; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usbh1_vbus>; - dr_mode = "host"; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usbotg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - dr_mode = "host"; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - cd-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>; - no-1-8-v; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - cd-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; - no-1-8-v; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio>; - - pinctrl_audmux: audmux { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x1b0b0 - MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x1b0b0 - MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x1b0b0 - MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x1b0b0 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 - MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x100b1 /* SS0# */ - MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x100b1 /* SS1# */ - MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x100b1 /* SS2# */ - >; - }; - - pinctrl_ecspi2: ecspi2grp { - fsl,pins = < - MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 - MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 - MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 - MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x100b1 /* SS0# */ - MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x100b1 /* SS1# */ - >; - }; - - pinctrl_ecspi4: ecspi4grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1 - MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1 - MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1 - MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x100b1 /* SS0# */ - MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b1 /* SS1# */ - MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x1b0b0 /* WP pin */ - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x1b0b0 - MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x1b0b0 - >; - }; - - pinctrl_flexcan2: flexcan2grp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x1b0b0 - MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x1b0b0 - >; - }; - - pinctrl_gpio: gpiogrp { - fsl,pins = < - MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 /* led enable */ - MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 /* LCD power enable */ - MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x1b0b0 /* led yellow */ - MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x1b0b0 /* led red */ - MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x1b0b0 /* led green */ - MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x1b0b0 /* led blue */ - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* Profibus IRQ */ - MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x1b0b0 /* FPGA IRQ */ - MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x1b0b0 /* spi bus #2 SS driver enable */ - MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 /* RST_LOC# PHY reset input (has pull-down!)*/ - MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x1b0b0 /* USB_OTG_ID = GPIO1_24*/ - MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x1b0b0 /* Touchscreen IRQ */ - MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x1b0b0 /* PCIe reset */ - >; - }; - - pinctrl_gpmi_nand: gpmi-nand { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 - MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c4: i2c4grp { - fsl,pins = < - MX6QDL_PAD_GPIO_7__I2C4_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_8__I2C4_SDA 0x4001b8b1 - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b0 - MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b0 /* backlight enable */ - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D20__UART1_RTS_B 0x1b0b1 - MX6QDL_PAD_EIM_D19__UART1_CTS_B 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 - MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - >; - }; - - pinctrl_aristainetos2_usbh1_vbus: aristainetos-usbh1-vbus { - fsl,pins = ; - }; - - pinctrl_aristainetos2_usbotg_vbus: aristainetos-usbotg-vbus { - fsl,pins = ; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 - MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1b0b0 /* SD1 card detect input */ - MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b0 /* SD1 write protect input */ - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x71 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x71 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x71 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x71 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x71 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x71 - MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x1b0b0 /* SD2 level shifter output enable */ - MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 /* SD2 card detect input */ - MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0 /* SD2 write protect input */ - >; - }; -}; diff --git a/sys/gnu/dts/arm/imx6qdl-colibri.dtsi b/sys/gnu/dts/arm/imx6qdl-colibri.dtsi deleted file mode 100644 index d03dff23863..00000000000 --- a/sys/gnu/dts/arm/imx6qdl-colibri.dtsi +++ /dev/null @@ -1,891 +0,0 @@ -/* - * Copyright 2014-2016 Toradex AG - * Copyright 2012 Freescale Semiconductor, Inc. - * Copyright 2011 Linaro Ltd. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include - -/ { - model = "Toradex Colibri iMX6DL/S Module"; - compatible = "toradex,colibri_imx6dl", "fsl,imx6dl"; - - backlight: backlight { - compatible = "pwm-backlight"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_bl_on>; - pwms = <&pwm3 0 5000000>; - enable-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>; /* Colibri BL_ON */ - status = "disabled"; - }; - - reg_module_3v3: regulator-module-3v3 { - compatible = "regulator-fixed"; - regulator-name = "+V3.3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_module_3v3_audio: regulator-module-3v3-audio { - compatible = "regulator-fixed"; - regulator-name = "+V3.3_AUDIO"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_usb_host_vbus: regulator-usb-host-vbus { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_regulator_usbh_pwr>; - regulator-name = "usb_host_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; /* USBH_PEN */ - status = "disabled"; - }; - - sound { - compatible = "fsl,imx-audio-sgtl5000"; - model = "imx6dl-colibri-sgtl5000"; - ssi-controller = <&ssi1>; - audio-codec = <&codec>; - audio-routing = - "Headphone Jack", "HP_OUT", - "LINE_IN", "Line In Jack", - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias"; - mux-int-port = <1>; - mux-ext-port = <5>; - }; - - /* Optional S/PDIF in on SODIMM 88 and out on SODIMM 90, 137 or 168 */ - sound_spdif: sound-spdif { - compatible = "fsl,imx-audio-spdif"; - model = "imx-spdif"; - spdif-controller = <&spdif>; - spdif-in; - spdif-out; - status = "disabled"; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux &pinctrl_mic_gnd>; - status = "okay"; -}; - -/* Optional on SODIMM 55/63 */ -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - status = "disabled"; -}; - -/* Optional on SODIMM 178/188 */ -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - status = "disabled"; -}; - -/* Colibri SSP */ -&ecspi4 { - cs-gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi4>; - status = "disabled"; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rmii"; - phy-handle = <ðphy>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy: ethernet-phy@0 { - reg = <0>; - micrel,led-mode = <0>; - }; - }; -}; - -&hdmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hdmi_ddc>; - status = "disabled"; -}; - -/* - * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and - * touch screen controller - */ -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c2>; - pinctrl-0 = <&pinctrl_i2c2_gpio>; - scl-gpios = <&gpio2 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio3 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; - - pmic: pfuze100@8 { - compatible = "fsl,pfuze100"; - reg = <0x08>; - - regulators { - sw1a_reg: sw1ab { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw1c_reg: sw1c { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw3a_reg: sw3a { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - regulator-boot-on; - regulator-always-on; - }; - - snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - /* vgen1: unused */ - - vgen2_reg: vgen2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - regulator-boot-on; - regulator-always-on; - }; - - /* vgen3: unused */ - - vgen4_reg: vgen4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - vgen5_reg: vgen5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - vgen6_reg: vgen6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; - - codec: sgtl5000@a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - clocks = <&clks IMX6QDL_CLK_CKO>; - VDDA-supply = <®_module_3v3_audio>; - VDDIO-supply = <®_module_3v3>; - VDDD-supply = <&vgen4_reg>; - lrclk-strength = <3>; - }; - - /* STMPE811 touch screen controller */ - stmpe811@41 { - compatible = "st,stmpe811"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_touch_int>; - reg = <0x41>; - interrupts = <20 IRQ_TYPE_LEVEL_LOW>; - interrupt-parent = <&gpio6>; - interrupt-controller; - id = <0>; - blocks = <0x5>; - irq-trigger = <0x1>; - /* 3.25 MHz ADC clock speed */ - st,adc-freq = <1>; - /* 12-bit ADC */ - st,mod-12b = <1>; - /* internal ADC reference */ - st,ref-sel = <0>; - /* ADC converstion time: 80 clocks */ - st,sample-time = <4>; - - stmpe_touchscreen { - compatible = "st,stmpe-ts"; - /* 8 sample average control */ - st,ave-ctrl = <3>; - /* 7 length fractional part in z */ - st,fraction-z = <7>; - /* - * 50 mA typical 80 mA max touchscreen drivers - * current limit value - */ - st,i-drive = <1>; - /* 1 ms panel driver settling time */ - st,settling = <3>; - /* 5 ms touch detect interrupt delay */ - st,touch-det-delay = <5>; - }; - - stmpe_adc { - compatible = "st,stmpe-adc"; - /* forbid to use ADC channels 3-0 (touch) */ - st,norequest-mask = <0x0F>; - }; - }; -}; - -/* - * I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board) - */ -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c3>; - pinctrl-1 = <&pinctrl_i2c3_gpio>; - scl-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "disabled"; -}; - -/* Colibri PWM */ -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "disabled"; -}; - -/* Colibri PWM */ -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm2>; - status = "disabled"; -}; - -/* Colibri PWM */ -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; - status = "disabled"; -}; - -/* Colibri PWM */ -&pwm4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm4>; - status = "disabled"; -}; - -/* Optional S/PDIF out on SODIMM 137 */ -&spdif { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spdif>; - status = "disabled"; -}; - -&ssi1 { - status = "okay"; -}; - -/* Colibri UART_A */ -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1_dte &pinctrl_uart1_ctrl>; - fsl,dte-mode; - uart-has-rtscts; - status = "disabled"; -}; - -/* Colibri UART_B */ -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2_dte>; - fsl,dte-mode; - uart-has-rtscts; - status = "disabled"; -}; - -/* Colibri UART_C */ -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3_dte>; - fsl,dte-mode; - status = "disabled"; -}; - -&usbotg { - pinctrl-names = "default"; - disable-over-current; - dr_mode = "peripheral"; - status = "disabled"; -}; - -/* Colibri MMC */ -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_mmc_cd>; - cd-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; /* MMCD */ - disable-wp; - vqmmc-supply = <®_module_3v3>; - bus-width = <4>; - no-1-8-v; - status = "disabled"; -}; - -/* eMMC */ -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - vqmmc-supply = <®_module_3v3>; - bus-width = <8>; - no-1-8-v; - non-removable; - status = "okay"; -}; - -&weim { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_weim_sram &pinctrl_weim_cs0 - &pinctrl_weim_cs1 &pinctrl_weim_cs2 - &pinctrl_weim_rdnwr &pinctrl_weim_npwe>; - #address-cells = <2>; - #size-cells = <1>; - status = "disabled"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh_oc_1>; - - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0 - MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x130b0 - MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0 - MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x130b0 - /* SGTL5000 sys_mclk */ - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 - >; - }; - - pinctrl_cam_mclk: cammclkgrp { - fsl,pins = < - /* Parallel Camera CAM sys_mclk */ - MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x00b0 - >; - }; - - pinctrl_ecspi4: ecspi4grp { - fsl,pins = < - MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1 - MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1 - MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1 - /* SPI CS */ - MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x000b1 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 - MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 - MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 - MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 - MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 - MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 - MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK ((1<<30) | 0x1b0b0) - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0 - MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0 - >; - }; - - pinctrl_flexcan2: flexcan2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0 - MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0 - >; - }; - - pinctrl_gpio_bl_on: gpioblon { - fsl,pins = < - MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x1b0b0 - >; - }; - - pinctrl_gpio_keys: gpiokeys { - fsl,pins = < - MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x130b0 - >; - }; - - pinctrl_hdmi_ddc: hdmiddcgrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c2_gpio: i2c2grp { - fsl,pins = < - MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x4001b8b1 - MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3_gpio: i2c3gpiogrp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x4001b8b1 - MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x4001b8b1 - >; - }; - - pinctrl_ipu1_csi0: ipu1csi0grp { /* Parallel Camera */ - fsl,pins = < - MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12 0xb0b1 - MX6QDL_PAD_EIM_A18__IPU1_CSI1_DATA13 0xb0b1 - MX6QDL_PAD_EIM_A19__IPU1_CSI1_DATA14 0xb0b1 - MX6QDL_PAD_EIM_A20__IPU1_CSI1_DATA15 0xb0b1 - MX6QDL_PAD_EIM_A21__IPU1_CSI1_DATA16 0xb0b1 - MX6QDL_PAD_EIM_A22__IPU1_CSI1_DATA17 0xb0b1 - MX6QDL_PAD_EIM_A23__IPU1_CSI1_DATA18 0xb0b1 - MX6QDL_PAD_EIM_A24__IPU1_CSI1_DATA19 0xb0b1 - MX6QDL_PAD_EIM_D17__IPU1_CSI1_PIXCLK 0xb0b1 - MX6QDL_PAD_EIM_EB3__IPU1_CSI1_HSYNC 0xb0b1 - MX6QDL_PAD_EIM_D29__IPU1_CSI1_VSYNC 0xb0b1 - /* Disable PWM pins on camera interface */ - MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x40 - MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x40 - >; - }; - - pinctrl_ipu1_lcdif: ipu1lcdifgrp { - fsl,pins = < - MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0xa1 - MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0xa1 - MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0xa1 - MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0xa1 - MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0xa1 - MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0xa1 - MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0xa1 - MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0xa1 - MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0xa1 - MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0xa1 - MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0xa1 - MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0xa1 - MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0xa1 - MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0xa1 - MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0xa1 - MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0xa1 - MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0xa1 - MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0xa1 - MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0xa1 - MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0xa1 - MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0xa1 - MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0xa1 - >; - }; - - pinctrl_mic_gnd: gpiomicgnd { - fsl,pins = < - /* Controls Mic GND, PU or '1' pull Mic GND to GND */ - MX6QDL_PAD_RGMII_TD1__GPIO6_IO21 0x1b0b0 - >; - }; - - pinctrl_mmc_cd: gpiommccd { - fsl,pins = < - MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x1b0b1 - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1 - MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x00040 - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 - MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x00040 - >; - }; - - pinctrl_pwm4: pwm4grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1 - >; - }; - - pinctrl_regulator_usbh_pwr: gpioregusbhpwrgrp { - fsl,pins = < - /* USBH_EN */ - MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x0f058 - >; - }; - - pinctrl_usbh_oc_1: usbhoc1grp { - fsl,pins = < - /* USBH_OC */ - MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x1b0b0 - >; - }; - - pinctrl_spdif: spdifgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0 - >; - }; - - pinctrl_touch_int: gpiotouchintgrp { - fsl,pins = < - /* STMPE811 interrupt */ - MX6QDL_PAD_RGMII_TD0__GPIO6_IO20 0x1b0b0 - >; - }; - - pinctrl_uart1_dce: uart1dcegrp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 - >; - }; - - /* DTE mode */ - pinctrl_uart1_dte: uart1dtegrp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x1b0b1 - MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x1b0b1 - >; - }; - - /* Additional DTR, DSR, DCD */ - pinctrl_uart1_ctrl: uart1ctrlgrp { - fsl,pins = < - MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x1b0b0 - MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x1b0b0 - MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0 - >; - }; - - pinctrl_uart2_dte: uart2dtegrp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x1b0b1 - MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 0x1b0b1 - >; - }; - - pinctrl_uart3_dte: uart3dtegrp { - fsl,pins = < - MX6QDL_PAD_SD4_CLK__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_CMD__UART3_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbc_det: usbcdetgrp { - fsl,pins = < - /* USBC_DET */ - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 - /* USBC_DET_EN */ - MX6QDL_PAD_RGMII_TX_CTL__GPIO6_IO26 0x0f058 - /* USBC_DET_OVERWRITE */ - MX6QDL_PAD_RGMII_RXC__GPIO6_IO30 0x0f058 - >; - }; - - pinctrl_usbc_id_1: usbc_id-1 { - fsl,pins = < - /* USBC_ID */ - MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 - /* eMMC reset */ - MX6QDL_PAD_SD3_RST__SD3_RESET 0x17059 - >; - }; - - pinctrl_weim_cs0: weimcs0grp { - fsl,pins = < - /* nEXT_CS0 */ - MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1 - >; - }; - - pinctrl_weim_cs1: weimcs1grp { - fsl,pins = < - /* nEXT_CS1 */ - MX6QDL_PAD_EIM_CS1__EIM_CS1_B 0xb0b1 - >; - }; - - pinctrl_weim_cs2: weimcs2grp { - fsl,pins = < - /* nEXT_CS2 */ - MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0xb0b1 - >; - }; - - pinctrl_weim_sram: weimsramgrp { - fsl,pins = < - MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1 - MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1 - /* Data */ - MX6QDL_PAD_CSI0_DATA_EN__EIM_DATA00 0x1b0b0 - MX6QDL_PAD_CSI0_VSYNC__EIM_DATA01 0x1b0b0 - MX6QDL_PAD_CSI0_DAT4__EIM_DATA02 0x1b0b0 - MX6QDL_PAD_CSI0_DAT5__EIM_DATA03 0x1b0b0 - MX6QDL_PAD_CSI0_DAT6__EIM_DATA04 0x1b0b0 - MX6QDL_PAD_CSI0_DAT7__EIM_DATA05 0x1b0b0 - MX6QDL_PAD_CSI0_DAT8__EIM_DATA06 0x1b0b0 - MX6QDL_PAD_CSI0_DAT9__EIM_DATA07 0x1b0b0 - MX6QDL_PAD_CSI0_DAT12__EIM_DATA08 0x1b0b0 - MX6QDL_PAD_CSI0_DAT13__EIM_DATA09 0x1b0b0 - MX6QDL_PAD_CSI0_DAT14__EIM_DATA10 0x1b0b0 - MX6QDL_PAD_CSI0_DAT15__EIM_DATA11 0x1b0b0 - MX6QDL_PAD_CSI0_DAT16__EIM_DATA12 0x1b0b0 - MX6QDL_PAD_CSI0_DAT17__EIM_DATA13 0x1b0b0 - MX6QDL_PAD_CSI0_DAT18__EIM_DATA14 0x1b0b0 - MX6QDL_PAD_CSI0_DAT19__EIM_DATA15 0x1b0b0 - /* Address */ - MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1 - MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1 - MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1 - MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1 - MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1 - MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1 - MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1 - MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1 - MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1 - MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1 - MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1 - MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1 - MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1 - MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1 - MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1 - MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1 - >; - }; - - pinctrl_weim_rdnwr: weimrdnwr { - fsl,pins = < - MX6QDL_PAD_SD2_CLK__GPIO1_IO10 0x0040 - MX6QDL_PAD_RGMII_TD3__GPIO6_IO23 0x130b0 - >; - }; - - pinctrl_weim_npwe: weimnpwe { - fsl,pins = < - MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x0040 - MX6QDL_PAD_RGMII_TD2__GPIO6_IO22 0x130b0 - >; - }; - - /* ADDRESS[16:18] [25] used as GPIO */ - pinctrl_weim_gpio_1: weimgpio-1 { - fsl,pins = < - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 - MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0 - MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 - MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b0 - MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1b0b0 - MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1b0b0 - MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0 - MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b0 - MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b0b0 - MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 - >; - }; - - /* ADDRESS[19:24] used as GPIO */ - pinctrl_weim_gpio_2: weimgpio-2 { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0 - MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 - MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b0 - MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1b0b0 - MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1b0b0 - MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0 - MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b0 - MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b0b0 - MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 - >; - }; - - /* DATA[16:31] used as GPIO */ - pinctrl_weim_gpio_3: weimgpio-3 { - fsl,pins = < - MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b0 - MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b0 - MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x1b0b0 - MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0 - MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x1b0b0 - MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x1b0b0 - MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x1b0b0 - MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x1b0b0 - MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0 - MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 - MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x1b0b0 - MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b0 - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 - MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0 - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 - >; - }; - - /* DQM[0:3] used as GPIO */ - pinctrl_weim_gpio_4: weimgpio-4 { - fsl,pins = < - MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x1b0b0 - MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x1b0b0 - MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x1b0b0 - MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0 - >; - }; - - /* RDY used as GPIO */ - pinctrl_weim_gpio_5: weimgpio-5 { - fsl,pins = < - MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1b0b0 - >; - }; - - /* ADDRESS[16] DATA[30] used as GPIO */ - pinctrl_weim_gpio_6: weimgpio-6 { - fsl,pins = < - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 - MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 - >; - }; -}; diff --git a/sys/gnu/dts/arm/imx6qdl-cubox-i.dtsi b/sys/gnu/dts/arm/imx6qdl-cubox-i.dtsi deleted file mode 100644 index e3be453d8a4..00000000000 --- a/sys/gnu/dts/arm/imx6qdl-cubox-i.dtsi +++ /dev/null @@ -1,269 +0,0 @@ -/* - * Copyright (C) 2014 Russell King - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -#include -#include - -/ { - /* Will be filled by the bootloader */ - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0>; - }; - - ir_recv: ir-receiver { - compatible = "gpio-ir-receiver"; - gpios = <&gpio3 9 1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_cubox_i_ir>; - }; - - pwmleds { - compatible = "pwm-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_cubox_i_pwm1>; - - front { - active-low; - label = "imx6:red:front"; - max-brightness = <248>; - pwms = <&pwm1 0 50000>; - }; - }; - - v_5v0: regulator-v-5v0 { - compatible = "regulator-fixed"; - regulator-always-on; - regulator-max-microvolt = <5000000>; - regulator-min-microvolt = <5000000>; - regulator-name = "v_5v0"; - }; - - v_usb2: regulator-v-usb2 { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_cubox_i_usbh1_vbus>; - regulator-max-microvolt = <5000000>; - regulator-min-microvolt = <5000000>; - regulator-name = "v_usb2"; - vin-supply = <&v_5v0>; - }; - - v_usb1: regulator-v-usb1 { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_cubox_i_usbotg_vbus>; - regulator-max-microvolt = <5000000>; - regulator-min-microvolt = <5000000>; - regulator-name = "v_usb1"; - vin-supply = <&v_5v0>; - }; - - sound-spdif { - compatible = "fsl,imx-audio-spdif"; - model = "Integrated SPDIF"; - /* IMX6 doesn't implement this yet */ - spdif-controller = <&spdif>; - spdif-out; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-0 = <&pinctrl_gpio_key>; - pinctrl-names = "default"; - - button_0 { - label = "Button 0"; - gpios = <&gpio3 8 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; -}; - -&hdmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_cubox_i_hdmi>; - ddc-i2c-bus = <&i2c2>; - status = "okay"; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_cubox_i_i2c2>; - status = "okay"; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_cubox_i_i2c3>; - - status = "okay"; - - rtc@68 { - compatible = "nxp,pcf8523"; - reg = <0x68>; - }; -}; - -&iomuxc { - cubox_i { - pinctrl_cubox_i_hdmi: cubox-i-hdmi { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 - >; - }; - - pinctrl_cubox_i_i2c2: cubox-i-i2c2 { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_cubox_i_i2c3: cubox-i-i2c3 { - fsl,pins = < - MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_cubox_i_ir: cubox-i-ir { - fsl,pins = < - MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x80000000 - >; - }; - - pinctrl_cubox_i_pwm1: cubox-i-pwm1-front-led { - fsl,pins = ; - }; - - pinctrl_cubox_i_spdif: cubox-i-spdif { - fsl,pins = ; - }; - - pinctrl_cubox_i_usbh1: cubox-i-usbh1 { - fsl,pins = ; - }; - - pinctrl_cubox_i_usbh1_vbus: cubox-i-usbh1-vbus { - fsl,pins = ; - }; - - pinctrl_cubox_i_usbotg: cubox-i-usbotg { - /* - * The Cubox-i pulls ID low, but as it's pointless - * leaving it as a pull-up, even if it is just 10uA. - */ - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059 - MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 - >; - }; - - pinctrl_cubox_i_usbotg_vbus: cubox-i-usbotg-vbus { - fsl,pins = ; - }; - - pinctrl_cubox_i_usdhc2_aux: cubox-i-usdhc2-aux { - fsl,pins = < - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1f071 - MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x1b071 - >; - }; - - pinctrl_cubox_i_usdhc2: cubox-i-usdhc2 { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059 - >; - }; - - pinctrl_gpio_key: gpio-key { - fsl,pins = < - MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x17059 - >; - }; - }; -}; - -&pwm1 { - status = "okay"; -}; - -&spdif { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_cubox_i_spdif>; - status = "okay"; -}; - -&usbh1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_cubox_i_usbh1>; - vbus-supply = <&v_usb2>; - status = "okay"; -}; - -&usbotg { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_cubox_i_usbotg>; - vbus-supply = <&v_usb1>; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_cubox_i_usdhc2_aux &pinctrl_cubox_i_usdhc2>; - vmmc-supply = <&vcc_3v3>; - cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&vcc_3v3 { - vin-supply = <&v_5v0>; -}; diff --git a/sys/gnu/dts/arm/imx6qdl-dfi-fs700-m60.dtsi b/sys/gnu/dts/arm/imx6qdl-dfi-fs700-m60.dtsi deleted file mode 100644 index ebe7a8bddf0..00000000000 --- a/sys/gnu/dts/arm/imx6qdl-dfi-fs700-m60.dtsi +++ /dev/null @@ -1,201 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include - -/ { - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - dummy_reg: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "dummy-supply"; - }; - - reg_usb_otg_vbus: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 0>; - enable-active-high; - }; - }; - - chosen { - stdout-path = &uart1; - }; -}; - -&ecspi3 { - cs-gpios = <&gpio4 24 0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi3>; - status = "okay"; - - flash: m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "sst,sst25vf040b", "jedec,spi-nor"; - spi-max-frequency = <20000000>; - reg = <0>; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - status = "okay"; - phy-mode = "rgmii"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - imx6qdl-dfi-fs700-m60 { - pinctrl_hog: hoggrp { - fsl,pins = < - MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x80000000 - MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x80000000 /* PMIC irq */ - MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x80000000 /* MAX11801 irq */ - MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x000030b0 /* Backlight enable */ - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 - MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000 /* card detect */ - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - >; - }; - - pinctrl_usdhc4: usdhc4grp { - fsl,pins = < - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 - MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 - MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 - MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 - MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 - >; - }; - - pinctrl_ecspi3: ecspi3grp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 - MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 - MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 - MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 /* SPI NOR chipselect */ - >; - }; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&usbh1 { - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - dr_mode = "host"; - status = "okay"; -}; - -&usdhc2 { /* module slot */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&usdhc3 { /* baseboard slot */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; -}; - -&usdhc4 { /* eMMC */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc4>; - bus-width = <8>; - non-removable; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx6qdl-emcon-avari.dtsi b/sys/gnu/dts/arm/imx6qdl-emcon-avari.dtsi deleted file mode 100644 index 828cf3e3978..00000000000 --- a/sys/gnu/dts/arm/imx6qdl-emcon-avari.dtsi +++ /dev/null @@ -1,177 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 or MIT) -// -// Copyright (C) 2018 emtrion GmbH -// - -/ { - aliases { - boardid = &boardid; - mmc0 = &usdhc3; - mmc1 = &usdhc2; - mmc2 = &usdhc1; - mmc3 = &usdhc4; - }; - - reg_wall_5p0: reg-wall5p0 { - compatible = "regulator-fixed"; - regulator-name = "Main-Supply"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - reg_base3p3: reg-base3p3 { - compatible = "regulator-fixed"; - vin-supply = <®_wall_5p0>; - regulator-name = "3V3-avari"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - reg_base1p5: reg-base1p5 { - compatible = "regulator-fixed"; - vin-supply = <®_base3p3>; - regulator-name = "1V5-avari"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - }; - - reg_usb_otg: reg-otgvbus { - compatible = "regulator-fixed"; - vin-supply = <®_wall_5p0>; - regulator-name = "OTG_VBUS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 8 GPIO_ACTIVE_LOW>; - regulator-always-on; - }; - - clk_codec: clock-codec { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <12000000>; - }; - - sound { - compatible = "fsl,imx-audio-sgtl5000"; - model = "emCON-avari-sgtl5000"; - ssi-controller = <&ssi2>; - audio-codec = <&sgtl5000>; - audio-routing = - "Headphone Jack", "HP_OUT"; - mux-int-port = <2>; - mux-ext-port = <3>; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; - -&can1 { - status = "okay"; -}; - -&can2 { - status = "okay"; -}; - -&ecspi2 { - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c2>; - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - sgtl5000: audio-codec@a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - #sound-dai-cells = <0>; - clocks = <&clk_codec>; - VDDA-supply = <®_base3p3>; - VDDIO-supply = <®_base3p3>; - }; - - captouch: touchscreen@38 { - compatible = "edt,edt-ft5406"; - reg = <0x38>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_irq_touch2 &pinctrl_emcon_gpio4>; - interrupt-parent = <&gpio6>; - interrupts = <31 IRQ_TYPE_EDGE_FALLING>; - wake-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; - wakeup-source; - }; - - boardid: gpio@3a { - compatible = "nxp,pca8574"; - reg = <0x3a>; - gpio-controller; - #gpio-cells = <1>; - }; -}; - -&pcie { - status = "okay"; -}; - -&rgb_encoder { - status = "okay"; -}; - -&rgb_panel { - compatible = "edt,etm0700g0bdh6"; - status = "okay"; -}; - -&ssi2 { - status = "okay"; -}; - -&uart2 { - status = "okay"; - uart-has-rtscts; -}; - -&uart3 { - status = "okay"; -}; - -&uart4 { - status = "okay"; -}; - -&uart5 { - status = "okay"; -}; - -&usbh1 { - status = "okay"; -}; - -&usbotg { - status = "okay"; -}; - -&usdhc1 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx6qdl-emcon.dtsi b/sys/gnu/dts/arm/imx6qdl-emcon.dtsi deleted file mode 100644 index 70d26616d77..00000000000 --- a/sys/gnu/dts/arm/imx6qdl-emcon.dtsi +++ /dev/null @@ -1,831 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 or MIT) -// -// Copyright (C) 2018 emtrion GmbH -// - -#include -#include -#include - -/ { - - model = "emtrion SoM emCON-MX6"; - compatible = "emtrion,emcon-mx6"; - - aliases { - mmc0 = &usdhc3; - mmc1 = &usdhc2; - mmc2 = &usdhc1; - rtc0 = &ds1307; - }; - - chosen { - stdout-path = &uart1; - }; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x40000000>; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_emcon_wake>; - - wake { - label = "Wake"; - linux,code = ; - gpios = <&gpio3 2 GPIO_ACTIVE_LOW>; - wakeup-source; - }; - }; - - som_leds: leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_som_leds>; - - green { - label = "som:green"; - gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - default-state = "on"; - }; - - red { - label = "som:red"; - gpios = <&gpio3 1 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - - }; - - lvds_backlight: lvds-backlight { - compatible = "pwm-backlight"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lvds_bl>; - enable-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; - pwms = <&pwm1 0 50000>; - brightness-levels = < - 0 4 8 16 32 64 80 96 112 - 128 144 160 176 250 - >; - default-brightness-level = <13>; - status = "okay"; - }; - - pwm_fan: pwm-fan { - compatible = "pwm-fan"; - #cooling-cells = <2>; - pwms = <&pwm4 0 50000>; - cooling-levels = <0 64 127 191 255>; - status = "disabled"; - }; - - - rgb_encoder: display { - compatible = "fsl,imx-parallel-display"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rgb24_display>; - status = "disabled"; - - port@0 { - reg = <0>; - - rgb_encoder_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - - port@1 { - reg = <1>; - - rgb_encoder_out: endpoint { - remote-endpoint = <&rgb_panel_in>; - }; - }; - }; - - rgb_panel: lcd { - backlight = <&rgb_backlight>; - power-supply = <®_parallel_disp>; - - port { - rgb_panel_in: endpoint { - remote-endpoint = <&rgb_encoder_out>; - }; - }; - }; - - reg_parallel_disp: reg-parallel-display { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rgb_bl_en>; - regulator-name = "LCD-Supply"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio7 9 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_lvds_disp: reg-lvds-display { - compatible = "regulator-fixed"; - regulator-name = "LVDS-Supply"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio7 10 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - rgb_backlight: rgb-backlight { - compatible = "pwm-backlight"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rgb_bl>; - enable-gpios = <&gpio6 8 GPIO_ACTIVE_HIGH>; - pwms = <&pwm3 0 5000000>; - brightness-levels = < - 250 176 160 144 128 112 - 96 80 64 48 32 16 8 1 - >; - default-brightness-level = <13>; - status = "okay"; - }; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can1>; -}; - -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can2>; -}; - -&ecspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi2>; - cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>, - <&gpio2 27 GPIO_ACTIVE_HIGH>; -}; - -&ecspi4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nor_flash>; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii"; - phy-reset-gpios = <&gpio5 20 GPIO_ACTIVE_LOW>; - phy-reset-duration = <50>; - phy-supply = <&vdd_1V8_reg>; - phy-handle = <&ksz9031>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ksz9031: phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - interrupt-parent = <&gpio1>; - interrupts = <30 IRQ_TYPE_EDGE_FALLING>; - rxdv-skew-ps = <480>; - txen-skew-ps = <480>; - rxd0-skew-ps = <480>; - rxd1-skew-ps = <480>; - rxd2-skew-ps = <480>; - rxd3-skew-ps = <480>; - txd0-skew-ps = <420>; - txd1-skew-ps = <420>; - txd2-skew-ps = <360>; - txd3-skew-ps = <360>; - txc-skew-ps = <1020>; - rxc-skew-ps = <960>; - }; - }; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - da9063: pmic@58 { - compatible = "dlg,da9063"; - reg = <0x58>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - interrupt-parent = <&gpio2>; - interrupts = <8 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - - onkey { - compatible = "dlg,da9063-onkey"; - wakeup-source; - }; - - watchdog { - compatible = "dlg,da9063-watchdog"; - timeout-sec = <0>; - }; - - regulators { - vddcore_reg: bcore1 { - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1450000>; - regulator-ramp-delay = <2>; - regulator-name = "DA9063_CORE"; - regulator-always-on; - }; - - vddsoc_reg: bcore2 { - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1450000>; - regulator-ramp-delay = <2>; - regulator-name = "DA9063_SOC"; - regulator-always-on; - }; - - vdd_ddr3_reg: bpro { - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-ramp-delay = <2>; - regulator-always-on; - }; - - vdd_3v3_reg: bperi { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <2>; - regulator-always-on; - }; - - vdd_sata_reg: ldo3 { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - vdd_mipi_reg: ldo4 { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - vdd_mx6_snvs_reg: ldo5 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_hdmi_reg: ldo6 { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_pcie_reg: ldo7 { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - vdd_1V8_reg: ldo8 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vdd_3V3_sdc_reg: ldo9 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_1V2_reg: ldo10 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - }; - }; - - ds1307: rtc@68 { - compatible = "dallas,ds1307"; - reg = <0x68>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; -}; - -&iomuxc { - - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 - MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x1b060 - MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x130B0 - MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x1b060 - >; - }; - - pinctrl_can1: can1grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 - MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 - >; - }; - - pinctrl_can2: can2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b1 - MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b1 - >; - }; - - pinctrl_cpi1: csi0grp { - fsl,pins = < - MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0xb0b1 - MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b1 - MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b1 - MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b1 - MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b1 - MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b1 - MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b1 - MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b1 - MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b1 - MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b1 - MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b1 - >; - }; - - /*camera2-pinctrl is in imx6q-emcon.dtsi or imx6dl-emcon.dtsi*/ - - pinctrl_ecspi2: ecspi2grp { - fsl,pins = < - MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 - MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 - MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 - MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x100b1 - MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x100b1 - >; - }; - - pinctrl_emcon_gpio1: emcongpio1 { - fsl,pins = < - MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x0b0b1 - >; - }; - - pinctrl_emcon_gpio2: emcongpio2 { - fsl,pins = < - MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x0b0b1 - >; - }; - - pinctrl_emcon_gpio3: emcongpio3 { - fsl,pins = < - MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x0b0b1 - >; - }; - - pinctrl_emcon_gpio4: emcongpio4 { - fsl,pins = < - MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x0b0b1 - >; - }; - - pinctrl_emcon_gpio5: emcongpio5 { - fsl,pins = < - MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x0b0b1 - >; - }; - - pinctrl_emcon_gpio6: emcongpio6 { - fsl,pins = < - MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x0b0b1 - >; - }; - - pinctrl_emcon_gpio7: emcongpio7 { - fsl,pins = < - MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x0b0b1 - >; - }; - - pinctrl_emcon_gpio8: emcongpio8 { - fsl,pins = < - MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x0b0b1 - >; - }; - - pinctrl_emcon_irq_a: emconirqa { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x0b0b1 - >; - }; - - pinctrl_emcon_irq_b: emconirqb { - fsl,pins = < - MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x0b0b1 - >; - }; - - pinctrl_emcon_irq_c: emconirqc { - fsl,pins = < - MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x0b0b1 - >; - }; - - pinctrl_emcon_irq_pwr: emconirqpwr { - fsl,pins = < - MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x0b0b1 - >; - }; - - pinctrl_emcon_wake: emconwake { - fsl,pins = < - MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x1b0b1 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b030 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b030 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x4001a0b1 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 - MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b058 - MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 - MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4000b070 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b870 - >; - }; - - pinctrl_irq_touch1: irqtouch1 { - fsl,pins = < - MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x0b0b1 - >; - }; - - pinctrl_irq_touch2: irqtouch2 { - fsl,pins = < - MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x0b0b1 - >; - }; - - pinctrl_lvds_bl: lvdsbacklightgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_9__PWM1_OUT 0x0b0b1 - MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x0b0b1 - >; - }; - - pinctrl_lvds_reg: lvdsreggrp { - fsl,pins = < - MX6QDL_PAD_SD4_CLK__GPIO7_IO10 0x0b0b1 - >; - }; - - - pinctrl_nor_flash: norflashgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x1b0b1 - MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1 - MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1 - MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1 - MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b1 - >; - }; - - pinctrl_pcie_ctrl: pciegrp { - fsl,pins = < - MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b1 - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b1 - >; - }; - - pinctrl_pmic: pmicgrp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x0b0b1 - >; - }; - - pinctrl_pwm_fan: pwmfan { - fsl,pins = < - MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x0b0b1 - >; - }; - - pinctrl_rgb_bl: rgbbacklightgrp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x0b0b1 - MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x0b0b1 - >; - }; - - pinctrl_rgb_bl_en: rgbenable { - fsl,pins = < - MX6QDL_PAD_SD4_CMD__GPIO7_IO09 0x0b0b1 - >; - }; - - pinctrl_rgb24_display: rgbgrp { - fsl,pins = < - MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 - MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 - MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 - MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 - MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 - MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 - MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 - MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 - MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 - MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 - MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 - MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 - MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 - MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 - MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 - MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 - MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 - MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 - MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 - MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 - MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 - MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 - MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 - MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 - MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 - MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 - MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 - MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 - >; - }; - - pinctrl_secure: securegrp { - fsl,pins = < - MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b1 - >; - }; - - pinctrl_som_leds: somledgrp { - fsl,pins = < - MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x0b0b1 - MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x0b0b1 - >; - }; - - pinctrl_spdif_in: spdifin { - fsl,pins = < - MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0 - >; - }; - - pinctrl_spdif_out: spdifout { - fsl,pins = < - MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x13091 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1 - MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1 - MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usb_host1: usbhgrp { - fsl,pins = < - MX6QDL_PAD_EIM_D31__USB_H1_PWR 0x1B058 - MX6QDL_PAD_EIM_D30__USB_H1_OC 0x1B058 - >; - }; - - pinctrl_usb_otg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 - MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x17059 - MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x17059 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 - MX6QDL_PAD_GPIO_1__SD1_CD_B 0x1b0b1 - MX6QDL_PAD_DI0_PIN4__SD1_WP 0x1b0b1 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 - MX6QDL_PAD_GPIO_4__SD2_CD_B 0x1b0b1 - MX6QDL_PAD_GPIO_2__SD2_WP 0x1b0b1 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 - MX6QDL_PAD_SD3_RST__SD3_RESET 0x1b0b1 - >; - }; -}; - -&ipu1_di0_disp0 { - remote-endpoint = <&rgb_encoder_in>; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie_ctrl>; - reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>; - disable-gpio = <&gpio2 22 GPIO_ACTIVE_LOW>; -}; - -&pwm1 { - status = "okay"; -}; - -&pwm3 { - status = "okay"; -}; - -&pwm4 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; -}; - -&usbh1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_host1>; -}; - -&usbotg { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_otg>; - vbus-supply = <®_usb_otg>; - dr_mode = "peripheral"; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - fsl,wp-controller; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - fsl,wp-controller; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - non-removable; - bus-width = <8>; - status = "okay"; -}; - -/******device power Management*********/ - -&cpu0 { - voltage-tolerance = <2>; -}; - -®_arm { - vin-supply = <&vddcore_reg>; -}; - -®_soc { - vin-supply = <&vddsoc_reg>; -}; - -®_pu { - vin-supply = <&vddsoc_reg>; -}; - -/*******Disabled HW following***********/ - -&snvs_rtc { - status = "disabled"; -}; diff --git a/sys/gnu/dts/arm/imx6qdl-gw51xx.dtsi b/sys/gnu/dts/arm/imx6qdl-gw51xx.dtsi deleted file mode 100644 index 419a7cdc8ab..00000000000 --- a/sys/gnu/dts/arm/imx6qdl-gw51xx.dtsi +++ /dev/null @@ -1,499 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Gateworks Corporation - */ - -#include - -/ { - /* these are used by bootloader for disabling nodes */ - aliases { - led0 = &led0; - led1 = &led1; - nand = &gpmi; - usb0 = &usbh1; - usb1 = &usbotg; - }; - - chosen { - bootargs = "console=ttymxc1,115200"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led0: user1 { - label = "user1"; - gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - - led1: user2 { - label = "user2"; - gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ - default-state = "off"; - }; - }; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x20000000>; - }; - - pps { - compatible = "pps-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pps>; - gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_5p0v: regulator-5p0v { - compatible = "regulator-fixed"; - regulator-name = "5P0V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - reg_usb_otg_vbus: regulator-usb-otg-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii-id"; - phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c3>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - eeprom1: eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; - - eeprom2: eeprom@51 { - compatible = "atmel,24c02"; - reg = <0x51>; - pagesize = <16>; - }; - - eeprom3: eeprom@52 { - compatible = "atmel,24c02"; - reg = <0x52>; - pagesize = <16>; - }; - - eeprom4: eeprom@53 { - compatible = "atmel,24c02"; - reg = <0x53>; - pagesize = <16>; - }; - - gpio: pca9555@23 { - compatible = "nxp,pca9555"; - reg = <0x23>; - gpio-controller; - #gpio-cells = <2>; - }; - - rtc: ds1672@68 { - compatible = "dallas,ds1672"; - reg = <0x68>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - ltc3676: pmic@3c { - compatible = "lltc,ltc3676"; - reg = <0x3c>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - interrupt-parent = <&gpio1>; - interrupts = <8 IRQ_TYPE_EDGE_FALLING>; - - regulators { - /* VDD_SOC (1+R1/R2 = 1.635) */ - reg_vdd_soc: sw1 { - regulator-name = "vddsoc"; - regulator-min-microvolt = <674400>; - regulator-max-microvolt = <1308000>; - lltc,fb-voltage-divider = <127000 200000>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - }; - - /* VDD_1P8 (1+R1/R2 = 2.505): GPS/VideoIn/ENET-PHY */ - reg_1p8v: sw2 { - regulator-name = "vdd1p8"; - regulator-min-microvolt = <1033310>; - regulator-max-microvolt = <2004000>; - lltc,fb-voltage-divider = <301000 200000>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - }; - - /* VDD_ARM (1+R1/R2 = 1.635) */ - reg_vdd_arm: sw3 { - regulator-name = "vddarm"; - regulator-min-microvolt = <674400>; - regulator-max-microvolt = <1308000>; - lltc,fb-voltage-divider = <127000 200000>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - }; - - /* VDD_DDR (1+R1/R2 = 2.105) */ - reg_vdd_ddr: sw4 { - regulator-name = "vddddr"; - regulator-min-microvolt = <868310>; - regulator-max-microvolt = <1684000>; - lltc,fb-voltage-divider = <221000 200000>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - }; - - /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */ - reg_2p5v: ldo2 { - regulator-name = "vdd2p5"; - regulator-min-microvolt = <2490375>; - regulator-max-microvolt = <2490375>; - lltc,fb-voltage-divider = <487000 200000>; - regulator-boot-on; - regulator-always-on; - }; - - /* VDD_HIGH (1+R1/R2 = 4.17) */ - reg_3p0v: ldo4 { - regulator-name = "vdd3p0"; - regulator-min-microvolt = <3023250>; - regulator-max-microvolt = <3023250>; - lltc,fb-voltage-divider = <634000 200000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - adv7180: camera@20 { - compatible = "adi,adv7180"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_adv7180>; - reg = <0x20>; - powerdown-gpios = <&gpio5 20 GPIO_ACTIVE_LOW>; - interrupt-parent = <&gpio5>; - interrupts = <23 IRQ_TYPE_LEVEL_LOW>; - - port { - adv7180_to_ipu1_csi0_mux: endpoint { - remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; - bus-width = <8>; - }; - }; - }; -}; - -&ipu1_csi0_from_ipu1_csi0_mux { - bus-width = <8>; -}; - -&ipu1_csi0_mux_from_parallel_sensor { - remote-endpoint = <&adv7180_to_ipu1_csi0_mux>; - bus-width = <8>; -}; - -&ipu1_csi0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu1_csi0>; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ - status = "disabled"; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ - status = "disabled"; -}; - -&pwm4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */ - status = "disabled"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "okay"; -}; - -&usbh1 { - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; -}; - -&iomuxc { - pinctrl_adv7180: adv7180grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x0001b0b0 - MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x4001b0b0 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 /* PHY Reset */ - >; - }; - - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 - MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 - >; - }; - - pinctrl_gpmi_nand: gpminandgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_ipu1_csi0: ipu1csi0grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 - MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 - MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 - MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 - MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 - MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 - MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 - MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 - MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0 - MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0 - MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = < - MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 - >; - }; - - pinctrl_pmic: pmicgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ - >; - }; - - pinctrl_pps: ppsgrp { - fsl,pins = < - MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 - >; - }; - - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm4: pwm4grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */ - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 - >; - }; -}; diff --git a/sys/gnu/dts/arm/imx6qdl-gw52xx.dtsi b/sys/gnu/dts/arm/imx6qdl-gw52xx.dtsi deleted file mode 100644 index 1a9a9d98f28..00000000000 --- a/sys/gnu/dts/arm/imx6qdl-gw52xx.dtsi +++ /dev/null @@ -1,628 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Gateworks Corporation - */ - -#include - -/ { - /* these are used by bootloader for disabling nodes */ - aliases { - led0 = &led0; - led1 = &led1; - led2 = &led2; - nand = &gpmi; - ssi0 = &ssi1; - usb0 = &usbh1; - usb1 = &usbotg; - }; - - chosen { - bootargs = "console=ttymxc1,115200"; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm4 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <7>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led0: user1 { - label = "user1"; - gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - - led1: user2 { - label = "user2"; - gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ - default-state = "off"; - }; - - led2: user3 { - label = "user3"; - gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ - default-state = "off"; - }; - }; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x20000000>; - }; - - pps { - compatible = "pps-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pps>; - gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - reg_1p0v: regulator-1p0v { - compatible = "regulator-fixed"; - regulator-name = "1P0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_5p0v: regulator-5p0v { - compatible = "regulator-fixed"; - regulator-name = "5P0V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - reg_usb_otg_vbus: regulator-usb-otg-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - sound { - compatible = "fsl,imx6q-ventana-sgtl5000", - "fsl,imx-audio-sgtl5000"; - model = "sgtl5000-audio"; - ssi-controller = <&ssi1>; - audio-codec = <&codec>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - mux-int-port = <1>; - mux-ext-port = <4>; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - status = "okay"; -}; - -&clks { - assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, - <&clks IMX6QDL_CLK_LDB_DI1_SEL>; - assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, - <&clks IMX6QDL_CLK_PLL3_USB_OTG>; -}; - -&ecspi3 { - cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi3>; - status = "okay"; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii-id"; - phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c3>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - eeprom1: eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; - - eeprom2: eeprom@51 { - compatible = "atmel,24c02"; - reg = <0x51>; - pagesize = <16>; - }; - - eeprom3: eeprom@52 { - compatible = "atmel,24c02"; - reg = <0x52>; - pagesize = <16>; - }; - - eeprom4: eeprom@53 { - compatible = "atmel,24c02"; - reg = <0x53>; - pagesize = <16>; - }; - - gpio: pca9555@23 { - compatible = "nxp,pca9555"; - reg = <0x23>; - gpio-controller; - #gpio-cells = <2>; - }; - - rtc: ds1672@68 { - compatible = "dallas,ds1672"; - reg = <0x68>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - ltc3676: pmic@3c { - compatible = "lltc,ltc3676"; - reg = <0x3c>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - interrupt-parent = <&gpio1>; - interrupts = <8 IRQ_TYPE_EDGE_FALLING>; - - regulators { - /* VDD_SOC (1+R1/R2 = 1.635) */ - reg_vdd_soc: sw1 { - regulator-name = "vddsoc"; - regulator-min-microvolt = <674400>; - regulator-max-microvolt = <1308000>; - lltc,fb-voltage-divider = <127000 200000>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - }; - - /* VDD_1P8 (1+R1/R2 = 2.505): GPS/VideoIn/ENET-PHY */ - reg_1p8v: sw2 { - regulator-name = "vdd1p8"; - regulator-min-microvolt = <1033310>; - regulator-max-microvolt = <2004000>; - lltc,fb-voltage-divider = <301000 200000>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - }; - - /* VDD_ARM (1+R1/R2 = 1.635) */ - reg_vdd_arm: sw3 { - regulator-name = "vddarm"; - regulator-min-microvolt = <674400>; - regulator-max-microvolt = <1308000>; - lltc,fb-voltage-divider = <127000 200000>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - }; - - /* VDD_DDR (1+R1/R2 = 2.105) */ - reg_vdd_ddr: sw4 { - regulator-name = "vddddr"; - regulator-min-microvolt = <868310>; - regulator-max-microvolt = <1684000>; - lltc,fb-voltage-divider = <221000 200000>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - }; - - /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */ - reg_2p5v: ldo2 { - regulator-name = "vdd2p5"; - regulator-min-microvolt = <2490375>; - regulator-max-microvolt = <2490375>; - lltc,fb-voltage-divider = <487000 200000>; - regulator-boot-on; - regulator-always-on; - }; - - /* VDD_AUD_1P8: Audio codec */ - reg_aud_1p8v: ldo3 { - regulator-name = "vdd1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - }; - - /* VDD_HIGH (1+R1/R2 = 4.17) */ - reg_3p0v: ldo4 { - regulator-name = "vdd3p0"; - regulator-min-microvolt = <3023250>; - regulator-max-microvolt = <3023250>; - lltc,fb-voltage-divider = <634000 200000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - codec: sgtl5000@a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - clocks = <&clks IMX6QDL_CLK_CKO>; - VDDA-supply = <®_1p8v>; - VDDIO-supply = <®_3p3v>; - }; - - touchscreen: egalax_ts@4 { - compatible = "eeti,egalax_ts"; - reg = <0x04>; - interrupt-parent = <&gpio7>; - interrupts = <12 2>; - wakeup-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>; - }; -}; - -&ldb { - status = "okay"; - - lvds-channel@0 { - fsl,data-mapping = "spwg"; - fsl,data-width = <18>; - status = "okay"; - - display-timings { - native-mode = <&timing0>; - timing0: hsd100pxn1 { - clock-frequency = <65000000>; - hactive = <1024>; - vactive = <768>; - hback-porch = <220>; - hfront-porch = <40>; - vback-porch = <21>; - vfront-porch = <7>; - hsync-len = <60>; - vsync-len = <10>; - }; - }; - }; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ - status = "disabled"; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ - status = "disabled"; -}; - -&pwm4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm4>; - status = "okay"; -}; - -&ssi1 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "okay"; -}; - -&usbh1 { - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_3p3v>; - no-1-8-v; /* firmware will remove if board revision supports */ - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; -}; - -&iomuxc { - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 - MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 - MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 - MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */ - >; - }; - - pinctrl_ecspi3: escpi3grp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 - MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 - MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 - MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x100b1 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 /* PHY Reset */ - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 - MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 - MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x4001b0b0 /* CAN_STBY */ - >; - }; - - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 - MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 - >; - }; - - pinctrl_gpmi_nand: gpminandgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = < - MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE_RST# */ - >; - }; - - pinctrl_pmic: pmicgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ - >; - }; - - pinctrl_pps: ppsgrp { - fsl,pins = < - MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 - >; - }; - - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm4: pwm4grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */ - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */ - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */ - MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3grp100mhz { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x170b9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */ - MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3grp200mhz { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */ - MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 - >; - }; -}; diff --git a/sys/gnu/dts/arm/imx6qdl-gw53xx.dtsi b/sys/gnu/dts/arm/imx6qdl-gw53xx.dtsi deleted file mode 100644 index 54b2beadd7a..00000000000 --- a/sys/gnu/dts/arm/imx6qdl-gw53xx.dtsi +++ /dev/null @@ -1,612 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Gateworks Corporation - */ - -#include - -/ { - /* these are used by bootloader for disabling nodes */ - aliases { - led0 = &led0; - led1 = &led1; - led2 = &led2; - nand = &gpmi; - ssi0 = &ssi1; - usb0 = &usbh1; - usb1 = &usbotg; - }; - - chosen { - bootargs = "console=ttymxc1,115200"; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm4 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <7>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led0: user1 { - label = "user1"; - gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - - led1: user2 { - label = "user2"; - gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ - default-state = "off"; - }; - - led2: user3 { - label = "user3"; - gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ - default-state = "off"; - }; - }; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x40000000>; - }; - - pps { - compatible = "pps-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pps>; - gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - reg_1p0v: regulator-1p0v { - compatible = "regulator-fixed"; - regulator-name = "1P0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_usb_h1_vbus: regulator-usb-h1-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - reg_usb_otg_vbus: regulator-usb-otg-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - sound { - compatible = "fsl,imx6q-ventana-sgtl5000", - "fsl,imx-audio-sgtl5000"; - model = "sgtl5000-audio"; - ssi-controller = <&ssi1>; - audio-codec = <&codec>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - mux-int-port = <1>; - mux-ext-port = <4>; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - status = "okay"; -}; - -&clks { - assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, - <&clks IMX6QDL_CLK_LDB_DI1_SEL>; - assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, - <&clks IMX6QDL_CLK_PLL3_USB_OTG>; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii-id"; - phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c3>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - eeprom1: eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; - - eeprom2: eeprom@51 { - compatible = "atmel,24c02"; - reg = <0x51>; - pagesize = <16>; - }; - - eeprom3: eeprom@52 { - compatible = "atmel,24c02"; - reg = <0x52>; - pagesize = <16>; - }; - - eeprom4: eeprom@53 { - compatible = "atmel,24c02"; - reg = <0x53>; - pagesize = <16>; - }; - - gpio: pca9555@23 { - compatible = "nxp,pca9555"; - reg = <0x23>; - gpio-controller; - #gpio-cells = <2>; - }; - - rtc: ds1672@68 { - compatible = "dallas,ds1672"; - reg = <0x68>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - ltc3676: pmic@3c { - compatible = "lltc,ltc3676"; - reg = <0x3c>; - interrupt-parent = <&gpio1>; - interrupts = <8 IRQ_TYPE_EDGE_FALLING>; - - regulators { - /* VDD_SOC (1+R1/R2 = 1.635) */ - reg_vdd_soc: sw1 { - regulator-name = "vddsoc"; - regulator-min-microvolt = <674400>; - regulator-max-microvolt = <1308000>; - lltc,fb-voltage-divider = <127000 200000>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - }; - - /* VDD_1P8 (1+R1/R2 = 2.505): GPS/VideoIn/ENET-PHY */ - reg_1p8v: sw2 { - regulator-name = "vdd1p8"; - regulator-min-microvolt = <1033310>; - regulator-max-microvolt = <2004000>; - lltc,fb-voltage-divider = <301000 200000>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - }; - - /* VDD_ARM (1+R1/R2 = 1.635) */ - reg_vdd_arm: sw3 { - regulator-name = "vddarm"; - regulator-min-microvolt = <674400>; - regulator-max-microvolt = <1308000>; - lltc,fb-voltage-divider = <127000 200000>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - }; - - /* VDD_DDR (1+R1/R2 = 2.105) */ - reg_vdd_ddr: sw4 { - regulator-name = "vddddr"; - regulator-min-microvolt = <868310>; - regulator-max-microvolt = <1684000>; - lltc,fb-voltage-divider = <221000 200000>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - }; - - /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */ - reg_2p5v: ldo2 { - regulator-name = "vdd2p5"; - regulator-min-microvolt = <2490375>; - regulator-max-microvolt = <2490375>; - lltc,fb-voltage-divider = <487000 200000>; - regulator-boot-on; - regulator-always-on; - }; - - /* VDD_AUD_1P8: Audio codec */ - reg_aud_1p8v: ldo3 { - regulator-name = "vdd1p8a"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - }; - - /* VDD_HIGH (1+R1/R2 = 4.17) */ - reg_3p0v: ldo4 { - regulator-name = "vdd3p0"; - regulator-min-microvolt = <3023250>; - regulator-max-microvolt = <3023250>; - lltc,fb-voltage-divider = <634000 200000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - codec: sgtl5000@a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - clocks = <&clks IMX6QDL_CLK_CKO>; - VDDA-supply = <®_1p8v>; - VDDIO-supply = <®_3p3v>; - }; - - touchscreen: egalax_ts@4 { - compatible = "eeti,egalax_ts"; - reg = <0x04>; - interrupt-parent = <&gpio1>; - interrupts = <11 2>; - wakeup-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; - }; -}; - -&ldb { - status = "okay"; - - lvds-channel@0 { - fsl,data-mapping = "spwg"; - fsl,data-width = <18>; - status = "okay"; - - display-timings { - native-mode = <&timing0>; - timing0: hsd100pxn1 { - clock-frequency = <65000000>; - hactive = <1024>; - vactive = <768>; - hback-porch = <220>; - hfront-porch = <40>; - vback-porch = <21>; - vfront-porch = <7>; - hsync-len = <60>; - vsync-len = <10>; - }; - }; - }; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ - status = "disabled"; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ - status = "disabled"; -}; - -&pwm4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm4>; - status = "okay"; -}; - -&ssi1 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usb_h1_vbus>; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_3p3v>; - no-1-8-v; /* firmware will remove if board revision supports */ - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; -}; - -&iomuxc { - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 - MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 - MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 - MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */ - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 - MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */ - >; - }; - - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 - MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 - >; - }; - - pinctrl_gpmi_nand: gpminandgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = < - MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* PCIE IRQ */ - MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE RST */ - >; - }; - - pinctrl_pmic: pmicgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ - >; - }; - - pinctrl_pps: ppsgrp { - fsl,pins = < - MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 - >; - }; - - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm4: pwm4grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */ - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */ - MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* OC */ - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */ - MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3grp100mhz { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */ - MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3grp200mhz { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */ - MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 - >; - }; -}; diff --git a/sys/gnu/dts/arm/imx6qdl-gw54xx.dtsi b/sys/gnu/dts/arm/imx6qdl-gw54xx.dtsi deleted file mode 100644 index 1b6c1331c22..00000000000 --- a/sys/gnu/dts/arm/imx6qdl-gw54xx.dtsi +++ /dev/null @@ -1,704 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Gateworks Corporation - */ - -#include -#include - -/ { - /* these are used by bootloader for disabling nodes */ - aliases { - led0 = &led0; - led1 = &led1; - led2 = &led2; - nand = &gpmi; - ssi0 = &ssi1; - usb0 = &usbh1; - usb1 = &usbotg; - }; - - chosen { - bootargs = "console=ttymxc1,115200"; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm4 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <7>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led0: user1 { - label = "user1"; - gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - - led1: user2 { - label = "user2"; - gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ - default-state = "off"; - }; - - led2: user3 { - label = "user3"; - gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ - default-state = "off"; - }; - }; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x40000000>; - }; - - pps { - compatible = "pps-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pps>; - gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_1p0v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "1P0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - reg_3p3v: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_usb_h1_vbus: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - reg_usb_otg_vbus: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - }; - - sound-analog { - compatible = "fsl,imx6q-ventana-sgtl5000", - "fsl,imx-audio-sgtl5000"; - model = "sgtl5000-audio"; - ssi-controller = <&ssi1>; - audio-codec = <&sgtl5000>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - mux-int-port = <1>; - mux-ext-port = <4>; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; /* AUD4<->sgtl5000 */ - status = "okay"; - - ssi2 { - fsl,audmux-port = <1>; - fsl,port-config = < - (IMX_AUDMUX_V2_PTCR_TFSDIR | - IMX_AUDMUX_V2_PTCR_TFSEL(4+8) | /* RXFS */ - IMX_AUDMUX_V2_PTCR_TCLKDIR | - IMX_AUDMUX_V2_PTCR_TCSEL(4+8) | /* RXC */ - IMX_AUDMUX_V2_PTCR_SYN) - IMX_AUDMUX_V2_PDCR_RXDSEL(4) - >; - }; - - aud5 { - fsl,audmux-port = <4>; - fsl,port-config = < - IMX_AUDMUX_V2_PTCR_SYN - IMX_AUDMUX_V2_PDCR_RXDSEL(1)>; - }; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - status = "okay"; -}; - -&clks { - assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, - <&clks IMX6QDL_CLK_LDB_DI1_SEL>; - assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, - <&clks IMX6QDL_CLK_PLL3_USB_OTG>; -}; - -&ecspi2 { - cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi2>; - status = "okay"; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii-id"; - phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c3>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - eeprom1: eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; - - eeprom2: eeprom@51 { - compatible = "atmel,24c02"; - reg = <0x51>; - pagesize = <16>; - }; - - eeprom3: eeprom@52 { - compatible = "atmel,24c02"; - reg = <0x52>; - pagesize = <16>; - }; - - eeprom4: eeprom@53 { - compatible = "atmel,24c02"; - reg = <0x53>; - pagesize = <16>; - }; - - gpio: pca9555@23 { - compatible = "nxp,pca9555"; - reg = <0x23>; - gpio-controller; - #gpio-cells = <2>; - }; - - rtc: ds1672@68 { - compatible = "dallas,ds1672"; - reg = <0x68>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - pmic: pfuze100@8 { - compatible = "fsl,pfuze100"; - reg = <0x08>; - - regulators { - sw1a_reg: sw1ab { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw1c_reg: sw1c { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3950000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3a_reg: sw3a { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3b_reg: sw3b { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - sw4_reg: sw4 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - }; - - swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - regulator-boot-on; - regulator-always-on; - }; - - snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - vgen1_reg: vgen1 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen2_reg: vgen2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen3_reg: vgen3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - vgen4_reg: vgen4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen5_reg: vgen5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen6_reg: vgen6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - sgtl5000: audio-codec@a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - clocks = <&clks IMX6QDL_CLK_CKO>; - VDDA-supply = <&sw4_reg>; - VDDIO-supply = <®_3p3v>; - }; - - touchscreen: egalax_ts@4 { - compatible = "eeti,egalax_ts"; - reg = <0x04>; - interrupt-parent = <&gpio7>; - interrupts = <12 2>; - wakeup-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>; - }; -}; - -&ldb { - status = "okay"; - - lvds-channel@0 { - fsl,data-mapping = "spwg"; - fsl,data-width = <18>; - status = "okay"; - - display-timings { - native-mode = <&timing0>; - timing0: hsd100pxn1 { - clock-frequency = <65000000>; - hactive = <1024>; - vactive = <768>; - hback-porch = <220>; - hfront-porch = <40>; - vback-porch = <21>; - vfront-porch = <7>; - hsync-len = <60>; - vsync-len = <10>; - }; - }; - }; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; /* MX6_DIO0 */ - status = "disabled"; -}; - -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ - status = "disabled"; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ - status = "disabled"; -}; - -&pwm4 { - pinctrl-names = "default", "state_dio"; - pinctrl-0 = <&pinctrl_pwm4_backlight>; - pinctrl-1 = <&pinctrl_pwm4_dio>; - status = "okay"; -}; - -&ssi1 { - status = "okay"; -}; - -&ssi2 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usb_h1_vbus>; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_3p3v>; - no-1-8-v; /* firmware will remove if board revision supports */ - status = "okay"; -}; - -&wdog1 { - status = "disabled"; -}; - -&wdog2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 - MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 - MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 - MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */ - MX6QDL_PAD_EIM_D25__AUD5_RXC 0x130b0 - MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0 - MX6QDL_PAD_EIM_D24__AUD5_RXFS 0x130b0 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - >; - }; - - pinctrl_ecspi2: escpi2grp { - fsl,pins = < - MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 - MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 - MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 - MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x100b1 - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 - MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */ - >; - }; - - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 - MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 - >; - }; - - pinctrl_gpmi_nand: gpminandgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = < - MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* PCIE IRQ */ - MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE RST */ - >; - }; - - pinctrl_pps: ppsgrp { - fsl,pins = < - MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm4_backlight: pwm4grpbacklight { - fsl,pins = < - /* LVDS_PWM J6.5 */ - MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm4_dio: pwm4grpdio { - fsl,pins = < - /* DIO3 J16.4 */ - MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */ - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */ - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */ - MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3grp100mhz { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */ - MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3grp200mhz { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */ - MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT3__WDOG2_B 0x1b0b0 - >; - }; -}; diff --git a/sys/gnu/dts/arm/imx6qdl-gw551x.dtsi b/sys/gnu/dts/arm/imx6qdl-gw551x.dtsi deleted file mode 100644 index c38e86eedcc..00000000000 --- a/sys/gnu/dts/arm/imx6qdl-gw551x.dtsi +++ /dev/null @@ -1,563 +0,0 @@ -/* - * Copyright 2014 Gateworks Corporation - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include -#include -#include - -/ { - /* these are used by bootloader for disabling nodes */ - aliases { - led0 = &led0; - nand = &gpmi; - ssi0 = &ssi1; - usb0 = &usbh1; - usb1 = &usbotg; - }; - - chosen { - bootargs = "console=ttymxc1,115200"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led0: user1 { - label = "user1"; - gpios = <&gpio4 7 GPIO_ACTIVE_LOW>; - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - }; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x20000000>; - }; - - reg_5p0v: regulator-5p0v { - compatible = "regulator-fixed"; - regulator-name = "5P0V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_usb_h1_vbus: regulator-usb-h1-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_usb_otg_vbus: regulator-usb-otg-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - sound-digital { - compatible = "simple-audio-card"; - simple-audio-card,name = "tda1997x-audio"; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&sound_codec>; - simple-audio-card,frame-master = <&sound_codec>; - - sound_cpu: simple-audio-card,cpu { - sound-dai = <&ssi2>; - }; - - sound_codec: simple-audio-card,codec { - sound-dai = <&hdmi_receiver>; - }; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; /* AUD5<->tda1997x */ - status = "okay"; - - ssi1 { - fsl,audmux-port = <0>; - fsl,port-config = < - (IMX_AUDMUX_V2_PTCR_TFSDIR | - IMX_AUDMUX_V2_PTCR_TFSEL(4+8) | /* RXFS */ - IMX_AUDMUX_V2_PTCR_TCLKDIR | - IMX_AUDMUX_V2_PTCR_TCSEL(4+8) | /* RXC */ - IMX_AUDMUX_V2_PTCR_SYN) - IMX_AUDMUX_V2_PDCR_RXDSEL(4) - >; - }; - - aud5 { - fsl,audmux-port = <4>; - fsl,port-config = < - IMX_AUDMUX_V2_PTCR_SYN - IMX_AUDMUX_V2_PDCR_RXDSEL(0)>; - }; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - status = "okay"; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c3>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - eeprom1: eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; - - eeprom2: eeprom@51 { - compatible = "atmel,24c02"; - reg = <0x51>; - pagesize = <16>; - }; - - eeprom3: eeprom@52 { - compatible = "atmel,24c02"; - reg = <0x52>; - pagesize = <16>; - }; - - eeprom4: eeprom@53 { - compatible = "atmel,24c02"; - reg = <0x53>; - pagesize = <16>; - }; - - gpio: pca9555@23 { - compatible = "nxp,pca9555"; - reg = <0x23>; - gpio-controller; - #gpio-cells = <2>; - }; - - rtc: ds1672@68 { - compatible = "dallas,ds1672"; - reg = <0x68>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - ltc3676: pmic@3c { - compatible = "lltc,ltc3676"; - reg = <0x3c>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - interrupt-parent = <&gpio1>; - interrupts = <8 IRQ_TYPE_EDGE_FALLING>; - - regulators { - /* VDD_SOC (1+R1/R2 = 1.635) */ - reg_vdd_soc: sw1 { - regulator-name = "vddsoc"; - regulator-min-microvolt = <674400>; - regulator-max-microvolt = <1308000>; - lltc,fb-voltage-divider = <127000 200000>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - }; - - /* VDD_DDR (1+R1/R2 = 2.105) */ - reg_vdd_ddr: sw2 { - regulator-name = "vddddr"; - regulator-min-microvolt = <868310>; - regulator-max-microvolt = <1684000>; - lltc,fb-voltage-divider = <221000 200000>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - }; - - /* VDD_ARM (1+R1/R2 = 1.635) */ - reg_vdd_arm: sw3 { - regulator-name = "vddarm"; - regulator-min-microvolt = <674400>; - regulator-max-microvolt = <1308000>; - lltc,fb-voltage-divider = <127000 200000>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - }; - - /* VDD_3P3 (1+R1/R2 = 1.281) */ - reg_3p3: sw4 { - regulator-name = "vdd3p3"; - regulator-min-microvolt = <1880000>; - regulator-max-microvolt = <3647000>; - lltc,fb-voltage-divider = <200000 56200>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - }; - - /* VDD_1P8a (1+R1/R2 = 2.505): HDMI In core */ - reg_1p8a: ldo2 { - regulator-name = "vdd1p8a"; - regulator-min-microvolt = <1816125>; - regulator-max-microvolt = <1816125>; - lltc,fb-voltage-divider = <301000 200000>; - regulator-boot-on; - regulator-always-on; - }; - - /* VDD_1P8b: HDMI In analog */ - reg_1p8b: ldo3 { - regulator-name = "vdd1p8b"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - }; - - /* VDD_HIGH (1+R1/R2 = 4.17) */ - reg_3p0: ldo4 { - regulator-name = "vdd3p0"; - regulator-min-microvolt = <3023250>; - regulator-max-microvolt = <3023250>; - lltc,fb-voltage-divider = <634000 200000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - gpio_exp: pca9555@24 { - compatible = "nxp,pca9555"; - reg = <0x24>; - gpio-controller; - #gpio-cells = <2>; - }; - - hdmi_receiver: hdmi-receiver@48 { - compatible = "nxp,tda19971"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_tda1997x>; - reg = <0x48>; - interrupt-parent = <&gpio1>; - interrupts = <7 IRQ_TYPE_LEVEL_LOW>; - DOVDD-supply = <®_3p3>; - AVDD-supply = <®_1p8b>; - DVDD-supply = <®_1p8a>; - #sound-dai-cells = <0>; - nxp,audout-format = "i2s"; - nxp,audout-layout = <0>; - nxp,audout-width = <16>; - nxp,audout-mclk-fs = <128>; - /* - * The 8bpp YUV422 semi-planar mode outputs CbCr[11:4] - * and Y[11:4] across 16bits in the same cycle - * which we map to VP[15:08]<->CSI_DATA[19:12] - */ - nxp,vidout-portcfg = - /*G_Y_11_8<->VP[15:12]<->CSI_DATA[19:16]*/ - < TDA1997X_VP24_V15_12 TDA1997X_G_Y_11_8 >, - /*G_Y_7_4<->VP[11:08]<->CSI_DATA[15:12]*/ - < TDA1997X_VP24_V11_08 TDA1997X_G_Y_7_4 >, - /*R_CR_CBCR_11_8<->VP[07:04]<->CSI_DATA[11:08]*/ - < TDA1997X_VP24_V07_04 TDA1997X_R_CR_CBCR_11_8 >, - /*R_CR_CBCR_7_4<->VP[03:00]<->CSI_DATA[07:04]*/ - < TDA1997X_VP24_V03_00 TDA1997X_R_CR_CBCR_7_4 >; - - port { - tda1997x_to_ipu1_csi0_mux: endpoint { - remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; - bus-width = <16>; - hsync-active = <1>; - vsync-active = <1>; - data-active = <1>; - }; - }; - }; -}; - -&ipu1_csi0_from_ipu1_csi0_mux { - bus-width = <16>; -}; - -&ipu1_csi0_mux_from_parallel_sensor { - remote-endpoint = <&tda1997x_to_ipu1_csi0_mux>; - bus-width = <16>; -}; - -&ipu1_csi0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu1_csi0>; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ - status = "disabled"; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ - status = "disabled"; -}; - -&ssi1 { - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usb_h1_vbus>; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; -}; - -&iomuxc { - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0 - MX6QDL_PAD_DISP0_DAT14__AUD5_RXC 0x130b0 - MX6QDL_PAD_DISP0_DAT13__AUD5_RXFS 0x130b0 - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 - MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 - MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x4001b0b0 /* CAN_STBY */ - >; - }; - - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 - >; - }; - - pinctrl_gpmi_nand: gpminandgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_ipu1_csi0: ipu1_csi0grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x1b0b0 - MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x1b0b0 - MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x1b0b0 - MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x1b0b0 - MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x1b0b0 - MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x1b0b0 - MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x1b0b0 - MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x1b0b0 - MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 - MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 - MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 - MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 - MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 - MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 - MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 - MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 - MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0 - MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 - MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0 - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = < - MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 /* PCIE RST */ - >; - }; - - pinctrl_pmic: pmicgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ - >; - }; - - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 - >; - }; - - pinctrl_tda1997x: tda1997xgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 - >; - }; -}; diff --git a/sys/gnu/dts/arm/imx6qdl-gw552x.dtsi b/sys/gnu/dts/arm/imx6qdl-gw552x.dtsi deleted file mode 100644 index dc646b72b59..00000000000 --- a/sys/gnu/dts/arm/imx6qdl-gw552x.dtsi +++ /dev/null @@ -1,367 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2014 Gateworks Corporation - */ - -#include - -/ { - /* these are used by bootloader for disabling nodes */ - aliases { - led0 = &led0; - led1 = &led1; - led2 = &led2; - nand = &gpmi; - usb0 = &usbh1; - usb1 = &usbotg; - }; - - chosen { - bootargs = "console=ttymxc1,115200"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led0: user1 { - label = "user1"; - gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - - led1: user2 { - label = "user2"; - gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ - default-state = "off"; - }; - - led2: user3 { - label = "user3"; - gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ - default-state = "off"; - }; - }; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x20000000>; - }; - - reg_1p0v: regulator-1p0v { - compatible = "regulator-fixed"; - regulator-name = "1P0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_5p0v: regulator-5p0v { - compatible = "regulator-fixed"; - regulator-name = "5P0V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c3>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - eeprom1: eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; - - eeprom2: eeprom@51 { - compatible = "atmel,24c02"; - reg = <0x51>; - pagesize = <16>; - }; - - eeprom3: eeprom@52 { - compatible = "atmel,24c02"; - reg = <0x52>; - pagesize = <16>; - }; - - eeprom4: eeprom@53 { - compatible = "atmel,24c02"; - reg = <0x53>; - pagesize = <16>; - }; - - gpio: pca9555@23 { - compatible = "nxp,pca9555"; - reg = <0x23>; - gpio-controller; - #gpio-cells = <2>; - }; - - rtc: ds1672@68 { - compatible = "dallas,ds1672"; - reg = <0x68>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - ltc3676: pmic@3c { - compatible = "lltc,ltc3676"; - reg = <0x3c>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - interrupt-parent = <&gpio1>; - interrupts = <8 IRQ_TYPE_EDGE_FALLING>; - - regulators { - /* VDD_SOC (1+R1/R2 = 1.635) */ - reg_vdd_soc: sw1 { - regulator-name = "vddsoc"; - regulator-min-microvolt = <674400>; - regulator-max-microvolt = <1308000>; - lltc,fb-voltage-divider = <127000 200000>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - }; - - /* VDD_1P8 (1+R1/R2 = 2.505): ENET-PHY */ - reg_1p8v: sw2 { - regulator-name = "vdd1p8"; - regulator-min-microvolt = <1033310>; - regulator-max-microvolt = <2004000>; - lltc,fb-voltage-divider = <301000 200000>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - }; - - /* VDD_ARM (1+R1/R2 = 1.635) */ - reg_vdd_arm: sw3 { - regulator-name = "vddarm"; - regulator-min-microvolt = <674400>; - regulator-max-microvolt = <1308000>; - lltc,fb-voltage-divider = <127000 200000>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - }; - - /* VDD_DDR (1+R1/R2 = 2.105) */ - reg_vdd_ddr: sw4 { - regulator-name = "vddddr"; - regulator-min-microvolt = <868310>; - regulator-max-microvolt = <1684000>; - lltc,fb-voltage-divider = <221000 200000>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - }; - - /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */ - reg_2p5v: ldo2 { - regulator-name = "vdd2p5"; - regulator-min-microvolt = <2490375>; - regulator-max-microvolt = <2490375>; - lltc,fb-voltage-divider = <487000 200000>; - regulator-boot-on; - regulator-always-on; - }; - - /* VDD_HIGH (1+R1/R2 = 4.17) */ - reg_3p0v: ldo4 { - regulator-name = "vdd3p0"; - regulator-min-microvolt = <3023250>; - regulator-max-microvolt = <3023250>; - lltc,fb-voltage-divider = <634000 200000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ - status = "disabled"; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ - status = "disabled"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - status = "okay"; }; - -&usbh1 { - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; -}; - -&iomuxc { - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 - MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 - >; - }; - - pinctrl_gpmi_nand: gpminandgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = < - MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 - >; - }; - - pinctrl_pmic: pmicgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ - >; - }; - - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 - >; - }; -}; diff --git a/sys/gnu/dts/arm/imx6qdl-gw553x.dtsi b/sys/gnu/dts/arm/imx6qdl-gw553x.dtsi deleted file mode 100644 index a1066897be1..00000000000 --- a/sys/gnu/dts/arm/imx6qdl-gw553x.dtsi +++ /dev/null @@ -1,568 +0,0 @@ -/* - * Copyright 2016 Gateworks Corporation - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include - -/ { - /* these are used by bootloader for disabling nodes */ - aliases { - led0 = &led0; - led1 = &led1; - nand = &gpmi; - usb0 = &usbh1; - usb1 = &usbotg; - }; - - chosen { - stdout-path = &uart2; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led0: user1 { - label = "user1"; - gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - - led1: user2 { - label = "user2"; - gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ - default-state = "off"; - }; - }; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x20000000>; - }; - - pps { - compatible = "pps-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pps>; - gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - reg_5p0v: regulator-5p0v { - compatible = "regulator-fixed"; - regulator-name = "5P0V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - reg_usb_otg_vbus: regulator-usb-otg-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - status = "okay"; -}; - -&hdmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hdmi>; - ddc-i2c-bus = <&i2c3>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - gpio: pca9555@23 { - compatible = "nxp,pca9555"; - reg = <0x23>; - gpio-controller; - #gpio-cells = <2>; - }; - - eeprom1: eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; - - eeprom2: eeprom@51 { - compatible = "atmel,24c02"; - reg = <0x51>; - pagesize = <16>; - }; - - eeprom3: eeprom@52 { - compatible = "atmel,24c02"; - reg = <0x52>; - pagesize = <16>; - }; - - eeprom4: eeprom@53 { - compatible = "atmel,24c02"; - reg = <0x53>; - pagesize = <16>; - }; - - rtc: ds1672@68 { - compatible = "dallas,ds1672"; - reg = <0x68>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - ltc3676: pmic@3c { - compatible = "lltc,ltc3676"; - reg = <0x3c>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - interrupt-parent = <&gpio1>; - interrupts = <8 IRQ_TYPE_EDGE_FALLING>; - - regulators { - /* VDD_SOC (1+R1/R2 = 1.635) */ - reg_vdd_soc: sw1 { - regulator-name = "vddsoc"; - regulator-min-microvolt = <674400>; - regulator-max-microvolt = <1308000>; - lltc,fb-voltage-divider = <127000 200000>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - }; - - /* VDD_DDR (1+R1/R2 = 2.105) */ - reg_vdd_ddr: sw2 { - regulator-name = "vddddr"; - regulator-min-microvolt = <868310>; - regulator-max-microvolt = <1684000>; - lltc,fb-voltage-divider = <221000 200000>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - }; - - /* VDD_ARM (1+R1/R2 = 1.635) */ - reg_vdd_arm: sw3 { - regulator-name = "vddarm"; - regulator-min-microvolt = <674400>; - regulator-max-microvolt = <1308000>; - lltc,fb-voltage-divider = <127000 200000>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - }; - - /* VDD_3P3 (1+R1/R2 = 1.281) */ - reg_3p3v: sw4 { - regulator-name = "vdd3p3"; - regulator-min-microvolt = <1880000>; - regulator-max-microvolt = <3647000>; - lltc,fb-voltage-divider = <200000 56200>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - }; - - /* VDD_1P8a (1+R1/R2 = 2.505): Analog Video Decoder */ - reg_1p8a: ldo2 { - regulator-name = "vdd1p8a"; - regulator-min-microvolt = <1816125>; - regulator-max-microvolt = <1816125>; - lltc,fb-voltage-divider = <301000 200000>; - regulator-boot-on; - regulator-always-on; - }; - - /* VDD_1P8b: microSD VDD_1P8 */ - reg_1p8b: ldo3 { - regulator-name = "vdd1p8b"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - }; - - /* VDD_HIGH (1+R1/R2 = 4.17) */ - reg_3p0v: ldo4 { - regulator-name = "vdd3p0"; - regulator-min-microvolt = <3023250>; - regulator-max-microvolt = <3023250>; - lltc,fb-voltage-divider = <634000 200000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - adv7180: camera@20 { - compatible = "adi,adv7180"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_adv7180>; - reg = <0x20>; - powerdown-gpios = <&gpio5 20 GPIO_ACTIVE_LOW>; - interrupt-parent = <&gpio5>; - interrupts = <23 IRQ_TYPE_LEVEL_LOW>; - - port { - adv7180_to_ipu1_csi0_mux: endpoint { - remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; - bus-width = <8>; - }; - }; - }; -}; - -&ipu1_csi0_from_ipu1_csi0_mux { - bus-width = <8>; -}; - -&ipu1_csi0_mux_from_parallel_sensor { - remote-endpoint = <&adv7180_to_ipu1_csi0_mux>; - bus-width = <8>; -}; - -&ipu1_csi0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu1_csi0>; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ - status = "disabled"; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ - status = "disabled"; -}; - -&pwm4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */ - status = "disabled"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - status = "okay"; -}; - -&usbh1 { - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; -}; - -&iomuxc { - pinctrl_adv7180: adv7180grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x0001b0b0 - MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x4001b0b0 - >; - }; - - pinctrl_gpmi_nand: gpminandgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 - >; - }; - - pinctrl_hdmi: hdmigrp { - fsl,pins = < - MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_ipu1_csi0: ipu1csi0grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 - MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 - MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 - MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 - MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 - MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 - MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 - MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 - MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0 - MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0 - MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 - >; - }; - - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 - MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0 - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = < - MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x4001b0b0 /* PCIESKT_WDIS# */ - >; - }; - - pinctrl_pmic: pmicgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ - >; - }; - - pinctrl_pps: ppsgrp { - fsl,pins = < - MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 - >; - }; - - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm4: pwm4grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */ - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */ - MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3grp100mhz { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */ - MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3grp200mhz { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */ - MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 - >; - }; -}; diff --git a/sys/gnu/dts/arm/imx6qdl-gw560x.dtsi b/sys/gnu/dts/arm/imx6qdl-gw560x.dtsi deleted file mode 100644 index e8e36dfd0a6..00000000000 --- a/sys/gnu/dts/arm/imx6qdl-gw560x.dtsi +++ /dev/null @@ -1,751 +0,0 @@ -/* - * Copyright 2017 Gateworks Corporation - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include -#include - -/ { - /* these are used by bootloader for disabling nodes */ - aliases { - led0 = &led0; - led1 = &led1; - led2 = &led2; - ssi0 = &ssi1; - usb0 = &usbh1; - usb1 = &usbotg; - }; - - chosen { - stdout-path = &uart2; - }; - - backlight-display { - compatible = "pwm-backlight"; - pwms = <&pwm4 0 5000000>; - brightness-levels = < - 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100 - >; - default-brightness-level = <100>; - }; - - backlight-keypad { - compatible = "gpio-backlight"; - gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>; - default-on; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led0: user1 { - label = "user1"; - gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - - led1: user2 { - label = "user2"; - gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ - default-state = "off"; - }; - - led2: user3 { - label = "user3"; - gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ - default-state = "off"; - }; - }; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x40000000>; - }; - - pps { - compatible = "pps-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pps>; - gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; - }; - - reg_2p5v: regulator-2p5v { - compatible = "regulator-fixed"; - regulator-name = "2P5V"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_5p0v: regulator-5p0v { - compatible = "regulator-fixed"; - regulator-name = "5P0V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - reg_12p0v: regulator-12p0v { - compatible = "regulator-fixed"; - regulator-name = "12P0V"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_1p4v: regulator-vddsoc { - compatible = "regulator-fixed"; - regulator-name = "vdd_soc"; - regulator-min-microvolt = <1400000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - }; - - reg_usb_h1_vbus: regulator-usb-h1-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - reg_usb_otg_vbus: regulator-usb-otg-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - sound { - compatible = "fsl,imx6q-ventana-sgtl5000", - "fsl,imx-audio-sgtl5000"; - model = "sgtl5000-audio"; - ssi-controller = <&ssi1>; - audio-codec = <&sgtl5000>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - mux-int-port = <1>; - mux-ext-port = <4>; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; - -&ecspi3 { - cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi3>; - status = "okay"; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan>; - status = "okay"; -}; - -&clks { - assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, - <&clks IMX6QDL_CLK_LDB_DI1_SEL>; - assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, - <&clks IMX6QDL_CLK_PLL3_USB_OTG>; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii-id"; - phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c3>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - eeprom1: eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; - - eeprom2: eeprom@51 { - compatible = "atmel,24c02"; - reg = <0x51>; - pagesize = <16>; - }; - - eeprom3: eeprom@52 { - compatible = "atmel,24c02"; - reg = <0x52>; - pagesize = <16>; - }; - - eeprom4: eeprom@53 { - compatible = "atmel,24c02"; - reg = <0x53>; - pagesize = <16>; - }; - - pca9555: gpio@23 { - compatible = "nxp,pca9555"; - reg = <0x23>; - gpio-controller; - #gpio-cells = <2>; - }; - - ds1672: rtc@68 { - compatible = "dallas,ds1672"; - reg = <0x68>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - sgtl5000: codec@a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - #sound-dai-cells = <0>; - clocks = <&clks IMX6QDL_CLK_CKO>; - VDDA-supply = <®_1p8v>; - VDDIO-supply = <®_3p3v>; - }; - - tca8418: keypad@34 { - compatible = "ti,tca8418"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_keypad>; - reg = <0x34>; - interrupt-parent = <&gpio5>; - interrupts = <11 IRQ_TYPE_EDGE_FALLING>; - linux,keymap = < MATRIX_KEY(0x00, 0x01, BTN_0) - MATRIX_KEY(0x00, 0x00, BTN_1) - MATRIX_KEY(0x01, 0x01, BTN_2) - MATRIX_KEY(0x01, 0x00, BTN_3) - MATRIX_KEY(0x02, 0x00, BTN_4) - MATRIX_KEY(0x00, 0x03, BTN_5) - MATRIX_KEY(0x00, 0x02, BTN_6) - MATRIX_KEY(0x01, 0x03, BTN_7) - MATRIX_KEY(0x01, 0x02, BTN_8) - MATRIX_KEY(0x02, 0x02, BTN_9) - >; - keypad,num-rows = <4>; - keypad,num-columns = <4>; - }; - - ltc3676: pmic@3c { - compatible = "lltc,ltc3676"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - reg = <0x3c>; - interrupt-parent = <&gpio1>; - interrupts = <8 IRQ_TYPE_EDGE_FALLING>; - - regulators { - /* VDD_DDR (1+R1/R2 = 2.105) */ - reg_vdd_ddr: sw2 { - regulator-name = "vddddr"; - regulator-min-microvolt = <868310>; - regulator-max-microvolt = <1684000>; - lltc,fb-voltage-divider = <221000 200000>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - }; - - /* VDD_ARM (1+R1/R2 = 1.931) */ - reg_vdd_arm: sw3 { - regulator-name = "vddarm"; - regulator-min-microvolt = <796551>; - regulator-max-microvolt = <1544827>; - lltc,fb-voltage-divider = <243000 261000>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - linux,phandle = <®_vdd_arm>; - }; - - /* VDD_1P8 (1+R1/R2 = 2.505): GPS/VideoIn/ENET-PHY */ - reg_1p8v: sw4 { - regulator-name = "vdd1p8"; - regulator-min-microvolt = <1033310>; - regulator-max-microvolt = <2004000>; - lltc,fb-voltage-divider = <301000 200000>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - }; - - /* VDD_1P0 (1+R1/R2 = 1.39): PCIe/ENET-PHY */ - reg_1p0v: ldo2 { - regulator-name = "vdd1p0"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1050000>; - lltc,fb-voltage-divider = <78700 200000>; - regulator-boot-on; - regulator-always-on; - }; - - /* VDD_AUD_1P8: Audio codec */ - reg_aud_1p8v: ldo3 { - regulator-name = "vdd1p8a"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - }; - - /* VDD_HIGH (1+R1/R2 = 4.17) */ - reg_3p0v: ldo4 { - regulator-name = "vdd3p0"; - regulator-min-microvolt = <3023250>; - regulator-max-microvolt = <3023250>; - lltc,fb-voltage-divider = <634000 200000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - egalax_ts: touchscreen@4 { - compatible = "eeti,egalax_ts"; - reg = <0x04>; - interrupt-parent = <&gpio5>; - interrupts = <12 IRQ_TYPE_EDGE_FALLING>; - wakeup-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; - }; -}; - -&ldb { - fsl,dual-channel; - status = "okay"; - - lvds-channel@0 { - fsl,data-mapping = "spwg"; - fsl,data-width = <18>; - status = "okay"; - - display-timings { - native-mode = <&timing0>; - timing0: hsd100pxn1 { - clock-frequency = <65000000>; - hactive = <1024>; - vactive = <768>; - hback-porch = <220>; - hfront-porch = <40>; - vback-porch = <21>; - vfront-porch = <7>; - hsync-len = <60>; - vsync-len = <10>; - }; - }; - }; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio4 31 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ - status = "disabled"; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ - status = "disabled"; -}; - -&pwm4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm4>; - status = "okay"; -}; - -&ssi1 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - uart-has-rtscts; - rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usb_h1_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh1>; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - bus-width = <8>; - vmmc-supply = <®_3p3v>; - non-removable; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - cd-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; - vmmc-supply = <®_3p3v>; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; -}; - -&iomuxc { - pinctrl_audmux: audmuxgrp { - fsl,pins = < - /* AUD4 */ - MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0 - MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x110b0 - MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0 - MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0 - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */ - /* AUD6 */ - MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x130b0 - MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x130b0 - MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x130b0 - MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x130b0 - >; - }; - - pinctrl_ecspi3: escpi3grp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 - MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 - MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 - MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x100b1 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x4001b0b0 /* PHY_RST# */ - >; - }; - - pinctrl_flexcan: flexcangrp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 - MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */ - >; - }; - - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 - MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x4001b0b0 /* DIOI2C_DIS# */ - MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x0001b0b0 /* LVDS_TOUCH_IRQ# */ - MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x0001b0b0 /* LVDS_BACKEN */ - >; - }; - - pinctrl_keypad: keypadgrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x0001b0b0 /* KEYPAD_IRQ# */ - MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x0001b0b0 /* KEYPAD_LED_EN */ - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31 0x1b0b0 /* PCI_RST# */ - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x4001b0b0 /* PCIESKT_WDIS# */ - >; - }; - - pinctrl_pmic: pmicgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ - >; - }; - - pinctrl_pps: ppsgrp { - fsl,pins = < - MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 - >; - }; - - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm4: pwm4grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */ - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbh1: usbh1grp { - fsl,pins = < - MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x4001b0b0 /* USBHUB_RST# */ - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */ - MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* OC */ - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170f9 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100f9 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170f9 - MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x170f9 - MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x170f9 - MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x170f9 - MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x170f9 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */ - MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3grp100mhz { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */ - MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3grp200mhz { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */ - MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 - >; - }; -}; diff --git a/sys/gnu/dts/arm/imx6qdl-gw5903.dtsi b/sys/gnu/dts/arm/imx6qdl-gw5903.dtsi deleted file mode 100644 index aee9221f0f2..00000000000 --- a/sys/gnu/dts/arm/imx6qdl-gw5903.dtsi +++ /dev/null @@ -1,655 +0,0 @@ -/* - * Copyright 2017 Gateworks Corporation - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include - -/ { - chosen { - stdout-path = &uart2; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 5000000>; - brightness-levels = < - 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100 - >; - default-brightness-level = <100>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led0: user1 { - label = "user1"; - gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ - default-state = "off"; - }; - }; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x40000000>; - }; - - reg_5p0v: regulator-5p0v { - compatible = "regulator-fixed"; - regulator-name = "5P0V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_2p5v: regulator-2p5v { - compatible = "regulator-fixed"; - regulator-name = "2P5V"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - reg_usb_h1_vbus: regulator-usb-h1-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 30 0>; - enable-active-high; - }; - - reg_usb_otg_vbus: regulator-usb-otg-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_12p0: regulator-12p0v { - compatible = "regulator-fixed"; - regulator-name = "12P0V"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - sound { - compatible = "fsl,imx-audio-tlv320"; - model = "imx-tlv320"; - ssi-controller = <&ssi1>; - audio-codec = <&tlv320aic3105>; - /* routing of sink, source */ - audio-routing = - /* TLV320 LINE1L pin <-> Mic Jack connector */ - "LINE1L", "Mic Jack", - /* board Headphone Jack <-> HPOUT */ - "Headphone Jack", "HPLOUT", - "Headphone Jack", "HPROUT", - "Mic Jack", "Mic Bias"; - mux-int-port = <1>; - mux-ext-port = <6>; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; - -&clks { - assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, - <&clks IMX6QDL_CLK_LDB_DI1_SEL>; - assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, - <&clks IMX6QDL_CLK_PLL3_USB_OTG>; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii-id"; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pca9555: gpio@23 { - compatible = "nxp,pca9555"; - reg = <0x23>; - gpio-controller; - #gpio-cells = <2>; - }; - - eeprom1: eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; - - eeprom2: eeprom@51 { - compatible = "atmel,24c02"; - reg = <0x51>; - pagesize = <16>; - }; - - eeprom3: eeprom@52 { - compatible = "atmel,24c02"; - reg = <0x52>; - pagesize = <16>; - }; - - eeprom4: eeprom@53 { - compatible = "atmel,24c02"; - reg = <0x53>; - pagesize = <16>; - }; - - dts1672: rtc@68 { - compatible = "dallas,ds1672"; - reg = <0x68>; - }; -}; - -&i2c2 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - ltc3676: pmic@3c { - compatible = "lltc,ltc3676"; - reg = <0x3c>; - interrupt-parent = <&gpio1>; - interrupts = <8 IRQ_TYPE_EDGE_FALLING>; - - regulators { - /* VDD_1P8 (1+R1/R2 = 2.505): Aud/eMMC/microSD/Touch */ - reg_1p8v: sw1 { - regulator-name = "vdd1p8"; - regulator-min-microvolt = <1033310>; - regulator-max-microvolt = <2004000>; - lltc,fb-voltage-divider = <301000 200000>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - }; - - /* VDD_DDR (1+R1/R2 = 2.105) */ - reg_vdd_ddr: sw2 { - regulator-name = "vddddr"; - regulator-min-microvolt = <868310>; - regulator-max-microvolt = <1684000>; - lltc,fb-voltage-divider = <221000 200000>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - }; - - /* VDD_ARM (1+R1/R2 = 1.635) */ - reg_vdd_arm: sw3 { - regulator-name = "vddarm"; - regulator-min-microvolt = <674400>; - regulator-max-microvolt = <1308000>; - lltc,fb-voltage-divider = <127000 200000>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - linux,phandle = <®_vdd_arm>; - }; - - /* VDD_SOC (1+R1/R2 = 1.635) */ - reg_vdd_soc: sw4 { - regulator-name = "vddsoc"; - regulator-min-microvolt = <674400>; - regulator-max-microvolt = <1308000>; - lltc,fb-voltage-divider = <127000 200000>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - linux,phandle = <®_vdd_soc>; - }; - - /* VDD_1P0 (1+R1/R2 = 1.38): */ - reg_1p0v: ldo2 { - regulator-name = "vdd1p0"; - regulator-min-microvolt = <1002777>; - regulator-max-microvolt = <1002777>; - lltc,fb-voltage-divider = <100000 261000>; - regulator-boot-on; - regulator-always-on; - }; - - /* VDD_HIGH (1+R1/R2 = 4.17) */ - reg_3p0v: ldo4 { - regulator-name = "vdd3p0"; - regulator-min-microvolt = <3023250>; - regulator-max-microvolt = <3023250>; - lltc,fb-voltage-divider = <634000 200000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; -}; - -&i2c3 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - tlv320aic3105: codec@18 { - compatible = "ti,tlv320aic3x"; - reg = <0x18>; - reset-gpios = <&gpio5 17 GPIO_ACTIVE_LOW>; - clocks = <&clks IMX6QDL_CLK_CKO>; - ai3x-micbias-vg = <2>; /* MICBIAS_2_5V */ - /* Regulators */ - DRVDD-supply = <®_3p3v>; - AVDD-supply = <®_3p3v>; - IOVDD-supply = <®_3p3v>; - DVDD-supply = <®_1p8v>; - }; - - accelerometer@1d { - compatible = "fsl,mma8451"; - reg = <0x1d>; - interrupt-parent = <&gpio7>; - interrupts = <11 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "INT2"; - }; - - /* headphone detect */ - ts3a227e@3b { - compatible = "ti,ts3a227e"; - reg = <0x3b>; - interrupt-parent = <&gpio5>; - interrupts = <15 IRQ_TYPE_LEVEL_LOW>; - ti,micbias = <4>; /* 2.5V micbias */ - }; -}; - -&ldb { - status = "okay"; - - lvds-channel@0 { - fsl,data-mapping = "spwg"; - fsl,data-width = <18>; - status = "okay"; - - display-timings { - native-mode = <&timing0>; - timing0: g101evn010 { - clock-frequency = <68930000>; - hactive = <1280>; - vactive = <800>; - hback-porch = <220>; - hfront-porch = <40>; - vback-porch = <21>; - vfront-porch = <7>; - hsync-len = <60>; - vsync-len = <10>; - }; - }; - }; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "okay"; -}; - -&ssi1 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usb_h1_vbus>; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1_200mhz>; - vmmc-supply = <®_3p3v>; - non-removable; - bus-width = <4>; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>; - cd-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_3p3v>; - max-frequency = <100000000>; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - non-removable; - vmmc-supply = <®_3p3v>; - keep-power-in-suspend; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; -}; - -&iomuxc { - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x130b0 - MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x130b0 - MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x130b0 - MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x130b0 - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* MCK */ - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x4001b0b0 /* PHY_RST# */ - MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x4001b0b0 /* PHY_EN */ - >; - }; - - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0 /* GSC_IRQ# */ - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - /* I2C3 */ - MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - - /* Headphone Detect */ - MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x0001b0b0 /* HPDET_IRQ# */ - MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x0001b0b0 /* HPDET_MIC# */ - - /* Codec */ - MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x0001b0b0 /* CODEC_RST# */ - - /* Touch Controller */ - MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x0001b0b0 /* TOUCH_IRQ# */ - MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x0001b0b0 /* TOUCH_RST */ - - /* Stow Sensor */ - MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x0001b0b0 /* ACCEL_IRQ2 */ - MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x0001b0b0 /* ACCEL_IRQ1 */ - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x1b0b1 /* TXEN */ - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059 - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x4001b0b0 /* PWR_EN */ - MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* OC */ - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1grp200mhz { - fsl,pins = < - MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x4001b0b0 /* EMMY_EN */ - MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x4001b0b0 /* EMMY_CFG1# */ - MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x4001b0b0 /* EMMY_CFG2# */ - MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x0001b0b0 /* EMMY_BTWAKE# */ - MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x0001b0b0 /* EMMY_WFWAKE# */ - - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f9 - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x100f9 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f9 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f9 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f9 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f9 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 - MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x17059 /* CD */ - MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x17059 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2grp100mhz { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 - MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x170b9 /* CD */ - MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x170b9 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2grp200mhz { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170f9 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100f9 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170f9 - MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x170f9 /* CD */ - MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x170f9 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_RST__SD3_RESET 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3grp100mhz { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 - MX6QDL_PAD_SD3_RST__SD3_RESET 0x100b9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3grp200mhz { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 - MX6QDL_PAD_SD3_RST__SD3_RESET 0x100f9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 - >; - }; -}; diff --git a/sys/gnu/dts/arm/imx6qdl-gw5904.dtsi b/sys/gnu/dts/arm/imx6qdl-gw5904.dtsi deleted file mode 100644 index 6d21cc6a9d4..00000000000 --- a/sys/gnu/dts/arm/imx6qdl-gw5904.dtsi +++ /dev/null @@ -1,640 +0,0 @@ -/* - * Copyright 2017 Gateworks Corporation - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include - -/ { - /* these are used by bootloader for disabling nodes */ - aliases { - led0 = &led0; - led1 = &led1; - led2 = &led2; - usb0 = &usbh1; - usb1 = &usbotg; - }; - - chosen { - stdout-path = &uart2; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm4 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <7>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led0: user1 { - label = "user1"; - gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - - led1: user2 { - label = "user2"; - gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ - default-state = "off"; - }; - - led2: user3 { - label = "user3"; - gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ - default-state = "off"; - }; - }; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x40000000>; - }; - - pps { - compatible = "pps-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pps>; - gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; - }; - - reg_1p0v: regulator-1p0v { - compatible = "regulator-fixed"; - regulator-name = "1P0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_usb_h1_vbus: regulator-usb-h1-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - reg_usb_otg_vbus: regulator-usb-otg-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&clks { - assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, - <&clks IMX6QDL_CLK_LDB_DI1_SEL>; - assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, - <&clks IMX6QDL_CLK_PLL3_USB_OTG>; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii-id"; - status = "okay"; - - fixed-link { - speed = <1000>; - full-duplex; - }; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - switch@0 { - compatible = "marvell,mv88e6085"; - reg = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "lan4"; - }; - - port@1 { - reg = <1>; - label = "lan3"; - }; - - port@2 { - reg = <2>; - label = "lan2"; - }; - - port@3 { - reg = <3>; - label = "lan1"; - }; - - port@5 { - reg = <5>; - label = "cpu"; - ethernet = <&fec>; - }; - }; - }; - }; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pca9555: gpio@23 { - compatible = "nxp,pca9555"; - reg = <0x23>; - gpio-controller; - #gpio-cells = <2>; - }; - - eeprom1: eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; - - eeprom2: eeprom@51 { - compatible = "atmel,24c02"; - reg = <0x51>; - pagesize = <16>; - }; - - eeprom3: eeprom@52 { - compatible = "atmel,24c02"; - reg = <0x52>; - pagesize = <16>; - }; - - eeprom4: eeprom@53 { - compatible = "atmel,24c02"; - reg = <0x53>; - pagesize = <16>; - }; - - dts1672: rtc@68 { - compatible = "dallas,ds1672"; - reg = <0x68>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - ltc3676: pmic@3c { - compatible = "lltc,ltc3676"; - reg = <0x3c>; - interrupt-parent = <&gpio1>; - interrupts = <8 IRQ_TYPE_EDGE_FALLING>; - - regulators { - /* VDD_SOC (1+R1/R2 = 1.635) */ - reg_vdd_soc: sw1 { - regulator-name = "vddsoc"; - regulator-min-microvolt = <674400>; - regulator-max-microvolt = <1308000>; - lltc,fb-voltage-divider = <127000 200000>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - }; - - /* VDD_1P8 (1+R1/R2 = 2.505): GbE switch */ - reg_1p8v: sw2 { - regulator-name = "vdd1p8"; - regulator-min-microvolt = <1033310>; - regulator-max-microvolt = <2004000>; - lltc,fb-voltage-divider = <301000 200000>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - }; - - /* VDD_ARM (1+R1/R2 = 1.635) */ - reg_vdd_arm: sw3 { - regulator-name = "vddarm"; - regulator-min-microvolt = <674400>; - regulator-max-microvolt = <1308000>; - lltc,fb-voltage-divider = <127000 200000>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - }; - - /* VDD_DDR (1+R1/R2 = 2.105) */ - reg_vdd_ddr: sw4 { - regulator-name = "vddddr"; - regulator-min-microvolt = <868310>; - regulator-max-microvolt = <1684000>; - lltc,fb-voltage-divider = <221000 200000>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - }; - - /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */ - reg_2p5v: ldo2 { - regulator-name = "vdd2p5"; - regulator-min-microvolt = <2490375>; - regulator-max-microvolt = <2490375>; - lltc,fb-voltage-divider = <487000 200000>; - regulator-boot-on; - regulator-always-on; - }; - - /* VDD_HIGH (1+R1/R2 = 4.17) */ - reg_3p0v: ldo4 { - regulator-name = "vdd3p0"; - regulator-min-microvolt = <3023250>; - regulator-max-microvolt = <3023250>; - lltc,fb-voltage-divider = <634000 200000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - egalax_ts: touchscreen@4 { - compatible = "eeti,egalax_ts"; - reg = <0x04>; - interrupt-parent = <&gpio1>; - interrupts = <11 IRQ_TYPE_EDGE_FALLING>; - wakeup-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; - }; -}; - -&ldb { - status = "okay"; - - lvds-channel@0 { - fsl,data-mapping = "spwg"; - fsl,data-width = <18>; - status = "okay"; - - display-timings { - native-mode = <&timing0>; - timing0: hsd100pxn1 { - clock-frequency = <65000000>; - hactive = <1024>; - vactive = <768>; - hback-porch = <220>; - hfront-porch = <40>; - vback-porch = <21>; - vfront-porch = <7>; - hsync-len = <60>; - vsync-len = <10>; - }; - }; - }; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ - status = "disabled"; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ - status = "disabled"; -}; - -&pwm4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm4>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - uart-has-rtscts; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - uart-has-rtscts; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usb_h1_vbus>; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - non-removable; - vmmc-supply = <®_3p3v>; - keep-power-in-suspend; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; -}; - -&iomuxc { - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x4001b0b0 /* PHY_RST# */ - >; - }; - - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 - MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = < - MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 /* PCIE RST */ - >; - }; - - pinctrl_pmic: pmicgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 /* PMIC_IRQ# */ - >; - }; - - pinctrl_pps: ppsgrp { - fsl,pins = < - MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 - >; - }; - - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm4: pwm4grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1 - MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */ - MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* OC */ - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_RST__SD3_RESET 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3grp100mhz { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 - MX6QDL_PAD_SD3_RST__SD3_RESET 0x100b9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3grp200mhz { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 - MX6QDL_PAD_SD3_RST__SD3_RESET 0x100f9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 - >; - }; -}; diff --git a/sys/gnu/dts/arm/imx6qdl-gw5907.dtsi b/sys/gnu/dts/arm/imx6qdl-gw5907.dtsi deleted file mode 100644 index 0bdebddffd5..00000000000 --- a/sys/gnu/dts/arm/imx6qdl-gw5907.dtsi +++ /dev/null @@ -1,399 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2019 Gateworks Corporation - */ - -#include - -/ { - /* these are used by bootloader for disabling nodes */ - aliases { - led0 = &led0; - led1 = &led1; - nand = &gpmi; - usb0 = &usbh1; - usb1 = &usbotg; - }; - - chosen { - stdout-path = &uart2; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led0: user1 { - label = "user1"; - gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - - led1: user2 { - label = "user2"; - gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ - default-state = "off"; - }; - }; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x20000000>; - }; - - pps { - compatible = "pps-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pps>; - gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_5p0v: regulator-5p0v { - compatible = "regulator-fixed"; - regulator-name = "5P0V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - reg_usb_otg_vbus: regulator-usb-otg-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii-id"; - phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c3>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - gpio@23 { - compatible = "nxp,pca9555"; - reg = <0x23>; - gpio-controller; - #gpio-cells = <2>; - }; - - eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; - - eeprom@51 { - compatible = "atmel,24c02"; - reg = <0x51>; - pagesize = <16>; - }; - - eeprom@52 { - compatible = "atmel,24c02"; - reg = <0x52>; - pagesize = <16>; - }; - - eeprom@53 { - compatible = "atmel,24c02"; - reg = <0x53>; - pagesize = <16>; - }; - - rtc@68 { - compatible = "dallas,ds1672"; - reg = <0x68>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - gpio@20 { - compatible = "nxp,pca9555"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - }; - - adc@48 { - compatible = "ti,ads1015"; - reg = <0x48>; - #address-cells = <1>; - #size-cells = <0>; - - channel@4 { - reg = <4>; - ti,gain = <0>; - ti,datarate = <5>; - }; - - channel@5 { - reg = <5>; - ti,gain = <0>; - ti,datarate = <5>; - }; - - channel@6 { - reg = <6>; - ti,gain = <0>; - ti,datarate = <5>; - }; - }; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ - status = "disabled"; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ - status = "disabled"; -}; - -&pwm4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */ - status = "disabled"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "okay"; -}; - -&usbh1 { - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; -}; - -&iomuxc { - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 - >; - }; - - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 - MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 - >; - }; - - pinctrl_gpmi_nand: gpminandgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 - MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = < - MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 - >; - }; - - pinctrl_pps: ppsgrp { - fsl,pins = < - MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 - >; - }; - - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm4: pwm4grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 - >; - }; -}; diff --git a/sys/gnu/dts/arm/imx6qdl-gw5910.dtsi b/sys/gnu/dts/arm/imx6qdl-gw5910.dtsi deleted file mode 100644 index be1af7482f8..00000000000 --- a/sys/gnu/dts/arm/imx6qdl-gw5910.dtsi +++ /dev/null @@ -1,491 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2019 Gateworks Corporation - */ - -#include - -/ { - /* these are used by bootloader for disabling nodes */ - aliases { - led0 = &led0; - led1 = &led1; - led2 = &led2; - }; - - chosen { - stdout-path = &uart2; - }; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x20000000>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led0: user1 { - label = "user1"; - gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - - led1: user2 { - label = "user2"; - gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ - default-state = "off"; - }; - - led2: user3 { - label = "user3"; - gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ - default-state = "off"; - }; - }; - - pps { - compatible = "pps-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pps>; - gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_5p0v: regulator-5p0v { - compatible = "regulator-fixed"; - regulator-name = "5P0V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - reg_wl: regulator-wl { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_wl>; - compatible = "regulator-fixed"; - regulator-name = "wl"; - gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; - startup-delay-us = <100>; - enable-active-high; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_bt: regulator-bt { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_bt>; - compatible = "regulator-fixed"; - regulator-name = "bt"; - gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>; - startup-delay-us = <100>; - enable-active-high; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; -}; - - -&ecspi3 { - cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi3>; - status = "okay"; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii-id"; - status = "okay"; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - gpio@23 { - compatible = "nxp,pca9555"; - reg = <0x23>; - gpio-controller; - #gpio-cells = <2>; - }; - - eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; - - eeprom@51 { - compatible = "atmel,24c02"; - reg = <0x51>; - pagesize = <16>; - }; - - eeprom@52 { - compatible = "atmel,24c02"; - reg = <0x52>; - pagesize = <16>; - }; - - eeprom@53 { - compatible = "atmel,24c02"; - reg = <0x53>; - pagesize = <16>; - }; - - rtc@68 { - compatible = "dallas,ds1672"; - reg = <0x68>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - accel@19 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_accel>; - compatible = "st,lis2de12"; - reg = <0x19>; - st,drdy-int-pin = <1>; - interrupt-parent = <&gpio7>; - interrupts = <13 0>; - interrupt-names = "INT1"; - }; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio3 20 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ - status = "disabled"; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ - status = "disabled"; -}; - -/* off-board RS232 */ -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -/* serial console */ -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -/* Sterling-LWB Bluetooth */ -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - uart-has-rtscts; - status = "okay"; -}; - -/* GPS */ -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_5p0v>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "okay"; -}; - -&usbh1 { - status = "okay"; -}; - -/* Sterling-LWB SDIO WiFi */ -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - vmmc-supply = <®_3p3v>; - non-removable; - bus-width = <4>; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_3p3v>; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; -}; - -&iomuxc { - pinctrl_accel: accelmuxgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b1 - >; - }; - - pinctrl_ecspi3: escpi3grp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 - MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 - MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 - MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x100b1 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 - >; - }; - - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 - MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 - >; - }; - - pinctrl_gpmi_nand: gpminandgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = < - MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b0 - >; - }; - - pinctrl_pps: ppsgrp { - fsl,pins = < - MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x1b0b1 - >; - }; - - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 - >; - }; - - pinctrl_reg_bt: regbtgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b1 - >; - }; - - pinctrl_reg_wl: regwlgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b1 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1 - MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */ - MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3grp100mhz { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x170b9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */ - MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3grp200mhz { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */ - MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 - >; - }; -}; diff --git a/sys/gnu/dts/arm/imx6qdl-gw5912.dtsi b/sys/gnu/dts/arm/imx6qdl-gw5912.dtsi deleted file mode 100644 index 8c57fd2f9a0..00000000000 --- a/sys/gnu/dts/arm/imx6qdl-gw5912.dtsi +++ /dev/null @@ -1,461 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2019 Gateworks Corporation - */ - -#include - -/ { - /* these are used by bootloader for disabling nodes */ - aliases { - led0 = &led0; - led1 = &led1; - led2 = &led2; - nand = &gpmi; - usb0 = &usbh1; - usb1 = &usbotg; - }; - - chosen { - stdout-path = &uart2; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led0: user1 { - label = "user1"; - gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - - led1: user2 { - label = "user2"; - gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ - default-state = "off"; - }; - - led2: user3 { - label = "user3"; - gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ - default-state = "off"; - }; - }; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x40000000>; - }; - - pps { - compatible = "pps-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pps>; - gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_usb_vbus: regulator-5p0v { - compatible = "regulator-fixed"; - regulator-name = "usb_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - status = "okay"; -}; - -&ecspi2 { - cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi2>; - status = "okay"; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii-id"; - status = "okay"; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - gpio@23 { - compatible = "nxp,pca9555"; - reg = <0x23>; - gpio-controller; - #gpio-cells = <2>; - }; - - eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; - - eeprom@51 { - compatible = "atmel,24c02"; - reg = <0x51>; - pagesize = <16>; - }; - - eeprom@52 { - compatible = "atmel,24c02"; - reg = <0x52>; - pagesize = <16>; - }; - - eeprom@53 { - compatible = "atmel,24c02"; - reg = <0x53>; - pagesize = <16>; - }; - - rtc@68 { - compatible = "dallas,ds1672"; - reg = <0x68>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - accel@19 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_accel>; - compatible = "st,lis2de12"; - reg = <0x19>; - st,drdy-int-pin = <1>; - interrupt-parent = <&gpio7>; - interrupts = <13 0>; - interrupt-names = "INT1"; - }; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; /* MX6_DIO0 */ - status = "disabled"; -}; - -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ - status = "disabled"; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ - status = "disabled"; -}; - -&pwm4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */ - status = "disabled"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - rts-gpios = <&gpio7 12 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - dr_mode = "host"; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usb_vbus>; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_3p3v>; - no-1-8-v; /* firmware will remove if board revision supports */ - status = "okay"; -}; - -&wdog1 { - status = "disabled"; -}; - -&wdog2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl_accel: accelmuxgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b1 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - >; - }; - - pinctrl_ecspi2: escpi2grp { - fsl,pins = < - MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 - MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 - MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 - MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x100b1 - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 - MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 - >; - }; - - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 - MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 - >; - }; - - pinctrl_gpmi_nand: gpminandgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = < - MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 - MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 - >; - }; - - pinctrl_pps: ppsgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b1 - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm4: pwm4grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x4001b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x4001b0b1 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */ - MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3grp100mhz { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */ - MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3grp200mhz { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */ - MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT3__WDOG2_B 0x1b0b0 - >; - }; -}; diff --git a/sys/gnu/dts/arm/imx6qdl-gw5913.dtsi b/sys/gnu/dts/arm/imx6qdl-gw5913.dtsi deleted file mode 100644 index 635c203bd64..00000000000 --- a/sys/gnu/dts/arm/imx6qdl-gw5913.dtsi +++ /dev/null @@ -1,348 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2019 Gateworks Corporation - */ - -#include - -/ { - /* these are used by bootloader for disabling nodes */ - aliases { - led0 = &led0; - led1 = &led1; - nand = &gpmi; - usb0 = &usbh1; - usb1 = &usbotg; - }; - - chosen { - stdout-path = &uart2; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led0: user1 { - label = "user1"; - gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - - led1: user2 { - label = "user2"; - gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ - default-state = "off"; - }; - }; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x20000000>; - }; - - pps { - compatible = "pps-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pps>; - gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_5p0v: regulator-5p0v { - compatible = "regulator-fixed"; - regulator-name = "5P0V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii-id"; - status = "okay"; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - gpio@23 { - compatible = "nxp,pca9555"; - reg = <0x23>; - gpio-controller; - #gpio-cells = <2>; - }; - - eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; - - eeprom@51 { - compatible = "atmel,24c02"; - reg = <0x51>; - pagesize = <16>; - }; - - eeprom@52 { - compatible = "atmel,24c02"; - reg = <0x52>; - pagesize = <16>; - }; - - eeprom@53 { - compatible = "atmel,24c02"; - reg = <0x53>; - pagesize = <16>; - }; - - rtc@68 { - compatible = "dallas,ds1672"; - reg = <0x68>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ - status = "disabled"; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ - status = "disabled"; -}; - -&pwm4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */ - status = "disabled"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - status = "okay"; -}; - -&usbotg { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "okay"; -}; - -&usbh1 { - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; -}; - -&iomuxc { - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 - >; - }; - - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 - MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 - >; - }; - - pinctrl_gpmi_nand: gpminandgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = < - MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 - >; - }; - - pinctrl_pps: ppsgrp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b1 - >; - }; - - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm4: pwm4grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 - >; - }; -}; diff --git a/sys/gnu/dts/arm/imx6qdl-hummingboard.dtsi b/sys/gnu/dts/arm/imx6qdl-hummingboard.dtsi deleted file mode 100644 index 2ffb21dd89f..00000000000 --- a/sys/gnu/dts/arm/imx6qdl-hummingboard.dtsi +++ /dev/null @@ -1,368 +0,0 @@ -/* - * Copyright (C) 2013,2014 Russell King - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -#include - -/ { - /* Will be filled by the bootloader */ - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0>; - }; - - chosen { - stdout-path = &uart1; - }; - - ir_recv: ir-receiver { - compatible = "gpio-ir-receiver"; - gpios = <&gpio3 5 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard_gpio3_5>; - }; - - v_3v2: regulator-v-3v2 { - compatible = "regulator-fixed"; - regulator-always-on; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "v_3v2"; - vin-supply = <&v_5v0>; - }; - - v_5v0: regulator-v-5v0 { - compatible = "regulator-fixed"; - regulator-always-on; - regulator-max-microvolt = <5000000>; - regulator-min-microvolt = <5000000>; - regulator-name = "v_5v0"; - }; - - v_sd: regulator-v-sd { - compatible = "regulator-fixed"; - gpio = <&gpio4 30 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard_vmmc>; - regulator-boot-on; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "v_sd"; - startup-delay-us = <1000>; - vin-supply = <&v_3v2>; - }; - - v_usb2: regulator-v-usb2 { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard_usbh1_vbus>; - regulator-max-microvolt = <5000000>; - regulator-min-microvolt = <5000000>; - regulator-name = "v_usb2"; - vin-supply = <&v_5v0>; - }; - - v_usb1: regulator-v-usb1 { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard_usbotg_vbus>; - regulator-max-microvolt = <5000000>; - regulator-min-microvolt = <5000000>; - regulator-name = "v_usb1"; - vin-supply = <&v_5v0>; - }; - - audio: sound-sgtl5000 { - compatible = "simple-audio-card"; - simple-audio-card,name = "On-board Codec"; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&sound_codec>; - simple-audio-card,frame-master = <&sound_codec>; - simple-audio-card,widgets = - "Microphone", "Headphone Jack", - "Headphone", "Headphone Jack"; - simple-audio-card,routing = - "MIC_IN", "Headphone Jack", - "Headphone Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - - sound_cpu: simple-audio-card,cpu { - sound-dai = <&ssi1>; - }; - - sound_codec: simple-audio-card,codec { - sound-dai = <&sgtl5000>; - }; - }; - - sound-spdif { - compatible = "fsl,imx-audio-spdif"; - model = "On-board SPDIF"; - /* IMX6 doesn't implement this yet */ - spdif-controller = <&spdif>; - spdif-out; - }; -}; - -&audmux { - status = "okay"; - - ssi1 { - fsl,audmux-port = <0>; - fsl,port-config = < - (IMX_AUDMUX_V2_PTCR_SYN | - IMX_AUDMUX_V2_PTCR_TFSEL(4) | - IMX_AUDMUX_V2_PTCR_TCSEL(4) | - IMX_AUDMUX_V2_PTCR_TFSDIR | - IMX_AUDMUX_V2_PTCR_TCLKDIR) - IMX_AUDMUX_V2_PDCR_RXDSEL(4) - >; - }; - - pins5 { - fsl,audmux-port = <4>; - fsl,port-config = < - IMX_AUDMUX_V2_PTCR_SYN - IMX_AUDMUX_V2_PDCR_RXDSEL(0) - >; - }; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard_flexcan1>; - status = "okay"; -}; - -&hdmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard_hdmi>; - ddc-i2c-bus = <&i2c2>; - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard_i2c1>; - status = "okay"; - - /* Pro baseboard model */ - rtc@68 { - compatible = "nxp,pcf8523"; - reg = <0x68>; - }; - - /* Pro baseboard model */ - sgtl5000: codec@a { - clocks = <&clks IMX6QDL_CLK_CKO>; - compatible = "fsl,sgtl5000"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard_sgtl5000>; - #sound-dai-cells = <0>; - reg = <0x0a>; - VDDA-supply = <&v_3v2>; - VDDIO-supply = <&v_3v2>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard_i2c2>; - status = "okay"; -}; - -&iomuxc { - hummingboard { - pinctrl_hummingboard_flexcan1: hummingboard-flexcan1 { - fsl,pins = < - MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x80000000 - MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x80000000 - >; - }; - - pinctrl_hummingboard_gpio3_5: hummingboard-gpio3_5 { - fsl,pins = < - MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x1b0b1 - >; - }; - - pinctrl_hummingboard_hdmi: hummingboard-hdmi { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 - >; - }; - - pinctrl_hummingboard_i2c1: hummingboard-i2c1 { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_hummingboard_i2c2: hummingboard-i2c2 { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_hummingboard_pcie_reset: hummingboard-pcie-reset { - fsl,pins = < - MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x1b0b1 - >; - }; - - pinctrl_hummingboard_pwm1: pwm1grp { - fsl,pins = ; - }; - - pinctrl_hummingboard_sgtl5000: hummingboard-sgtl5000 { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0 - MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0 - MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x110b0 - MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0 - MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x130b0 - >; - }; - - pinctrl_hummingboard_spdif: hummingboard-spdif { - fsl,pins = ; - }; - - pinctrl_hummingboard_usbh1_vbus: hummingboard-usbh1-vbus { - fsl,pins = ; - }; - - pinctrl_hummingboard_usbotg_id: hummingboard-usbotg-id { - /* - * We want it pulled down for a fixed host connection. - */ - fsl,pins = ; - }; - - pinctrl_hummingboard_usbotg_vbus: hummingboard-usbotg-vbus { - fsl,pins = ; - }; - - pinctrl_hummingboard_usdhc2_aux: hummingboard-usdhc2-aux { - fsl,pins = < - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1f071 - >; - }; - - pinctrl_hummingboard_usdhc2: hummingboard-usdhc2 { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059 - >; - }; - pinctrl_hummingboard_vmmc: hummingboard-vmmc { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x1b0b0 - >; - }; - }; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard_pcie_reset>; - reset-gpio = <&gpio3 4 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard_pwm1>; - status = "okay"; -}; - -&pwm2 { - pinctrl-names = "default"; - status = "okay"; -}; - -&spdif { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard_spdif>; - status = "okay"; -}; - -&ssi1 { - status = "okay"; -}; - -&usbh1 { - disable-over-current; - vbus-supply = <&v_usb2>; - status = "okay"; -}; - -&usbotg { - disable-over-current; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard_usbotg_id>; - vbus-supply = <&v_usb1>; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = < - &pinctrl_hummingboard_usdhc2_aux - &pinctrl_hummingboard_usdhc2 - >; - vmmc-supply = <&v_sd>; - cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&vcc_3v3 { - vin-supply = <&v_3v2>; -}; diff --git a/sys/gnu/dts/arm/imx6qdl-hummingboard2-emmc.dtsi b/sys/gnu/dts/arm/imx6qdl-hummingboard2-emmc.dtsi deleted file mode 100644 index f400405381a..00000000000 --- a/sys/gnu/dts/arm/imx6qdl-hummingboard2-emmc.dtsi +++ /dev/null @@ -1,72 +0,0 @@ -/* - * Device Tree file for SolidRun HummingBoard2 - * Copyright (C) 2015 Rabeeh Khoury - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -&iomuxc { - hummingboard2 { - pinctrl_hummingboard2_usdhc3: hummingboard2-usdhc3 { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 - MX6QDL_PAD_SD3_RST__SD3_RESET 0x17059 - >; - }; - }; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard2_usdhc3>; - vmmc-supply = <&v_3v2>; - vqmmc-supply = <&v_3v2>; - bus-width = <8>; - non-removable; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx6qdl-hummingboard2.dtsi b/sys/gnu/dts/arm/imx6qdl-hummingboard2.dtsi deleted file mode 100644 index e4231331f04..00000000000 --- a/sys/gnu/dts/arm/imx6qdl-hummingboard2.dtsi +++ /dev/null @@ -1,577 +0,0 @@ -/* - * Copyright (C) 2015 Rabeeh Khoury - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -#include - -/ { - /* Will be filled by the bootloader */ - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0>; - }; - - chosen { - stdout-path = &uart1; - }; - - ir_recv: ir-receiver { - compatible = "gpio-ir-receiver"; - gpios = <&gpio7 9 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard2_gpio7_9>; - linux,rc-map-name = "rc-rc6-mce"; - }; - - v_3v2: regulator-v-3v2 { - compatible = "regulator-fixed"; - regulator-always-on; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "v_3v2"; - }; - - v_5v0: regulator-v-5v0 { - compatible = "regulator-fixed"; - regulator-always-on; - regulator-max-microvolt = <5000000>; - regulator-min-microvolt = <5000000>; - regulator-name = "v_5v0"; - }; - - vcc_1p8: regulator-vcc-1p8 { - compatible = "regulator-fixed"; - regulator-always-on; - regulator-max-microvolt = <1800000>; - regulator-min-microvolt = <1800000>; - regulator-name = "vcc_1p8"; - vin-supply = <&v_3v2>; - }; - - v_sd: regulator-v-sd { - compatible = "regulator-fixed"; - gpio = <&gpio4 30 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard2_vmmc>; - regulator-boot-on; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "v_sd"; - startup-delay-us = <1000>; - vin-supply = <&v_3v2>; - }; - - v_usb1: regulator-v-usb1 { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard2_usbotg_vbus>; - regulator-always-on; - regulator-max-microvolt = <5000000>; - regulator-min-microvolt = <5000000>; - regulator-name = "v_usb1"; - vin-supply = <&v_5v0>; - }; - - v_usb2: regulator-v-usb2 { - /* USB hub port 1 */ - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard2_usbh1_vbus>; - regulator-always-on; - regulator-max-microvolt = <5000000>; - regulator-min-microvolt = <5000000>; - regulator-name = "v_usb2"; - vin-supply = <&v_5v0>; - }; - - v_usb3: regulator-v-usb3 { - /* USB hub port 3 */ - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio2 13 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard2_usbh2_vbus>; - regulator-always-on; - regulator-max-microvolt = <5000000>; - regulator-min-microvolt = <5000000>; - regulator-name = "v_usb3"; - vin-supply = <&v_5v0>; - }; - - v_usb4: regulator-v-usb4 { - /* USB hub port 4 */ - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio7 10 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard2_usbh3_vbus>; - regulator-always-on; - regulator-max-microvolt = <5000000>; - regulator-min-microvolt = <5000000>; - regulator-name = "v_usb4"; - vin-supply = <&v_5v0>; - }; - - audio: sound-sgtl5000 { - compatible = "simple-audio-card"; - simple-audio-card,name = "On-board Codec"; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&sound_codec>; - simple-audio-card,frame-master = <&sound_codec>; - simple-audio-card,widgets = - "Microphone", "Mic Jack", - "Headphone", "Headphone Jack"; - simple-audio-card,routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - - sound_cpu: simple-audio-card,cpu { - sound-dai = <&ssi1>; - }; - - sound_codec: simple-audio-card,codec { - sound-dai = <&sgtl5000>; - }; - }; -}; - -&audmux { - status = "okay"; - - ssi1 { - fsl,audmux-port = <0>; - fsl,port-config = < - (IMX_AUDMUX_V2_PTCR_SYN | - IMX_AUDMUX_V2_PTCR_TFSEL(4) | - IMX_AUDMUX_V2_PTCR_TCSEL(4) | - IMX_AUDMUX_V2_PTCR_TFSDIR | - IMX_AUDMUX_V2_PTCR_TCLKDIR) - IMX_AUDMUX_V2_PDCR_RXDSEL(4) - >; - }; - - pins5 { - fsl,audmux-port = <4>; - fsl,port-config = < - IMX_AUDMUX_V2_PTCR_SYN - IMX_AUDMUX_V2_PDCR_RXDSEL(0) - >; - }; -}; - -&ecspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard2_ecspi2>; - cs-gpios = <&gpio2 26 0>; - status = "okay"; -}; - -&hdmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard2_hdmi>; - ddc-i2c-bus = <&i2c2>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard2_i2c1>; - status = "okay"; - - pcf8523: rtc@68 { - compatible = "nxp,pcf8523"; - reg = <0x68>; - }; - - sgtl5000: codec@a { - clocks = <&clks IMX6QDL_CLK_CKO>; - compatible = "fsl,sgtl5000"; - #sound-dai-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard2_sgtl5000>; - reg = <0x0a>; - VDDA-supply = <&v_3v2>; - VDDD-supply = <&vcc_1p8>; - VDDIO-supply = <&v_3v2>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard2_i2c2>; - status = "okay"; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard2_i2c3>; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - hummingboard2 { - pinctrl_hog: hoggrp { - fsl,pins = < - /* - * 36 pin headers GPIO description. The pins - * numbering as following - - * - * 3.2v 5v 74 75 - * 73 72 71 70 - * 69 68 67 66 - * - * 77 78 79 76 - * 65 64 61 60 - * 53 52 51 50 - * 49 48 166 132 - * 95 94 90 91 - * GND 54 24 204 - * - * The GPIO numbers can be extracted using - * signal name from below. - * Example - - * MX6QDL_PAD_EIM_DA10__GPIO3_IO10 is - * GPIO(3,10) which is (3-1)*32+10 = gpio 74 - * - * i.e. The mapping of GPIO(X,Y) to Linux gpio - * number is : gpio number = (X-1) * 32 + Y - */ - /* DI1_PIN15 */ - MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x400130b1 - /* DI1_PIN02 */ - MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0x400130b1 - /* DISP1_DATA00 */ - MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x400130b1 - /* DISP1_DATA01 */ - MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x400130b1 - /* DISP1_DATA02 */ - MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x400130b1 - /* DISP1_DATA03 */ - MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x400130b1 - /* DISP1_DATA04 */ - MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x400130b1 - /* DISP1_DATA05 */ - MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x400130b1 - /* DISP1_DATA06 */ - MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x400130b1 - /* DISP1_DATA07 */ - MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x400130b1 - /* DI1_D0_CS */ - MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x400130b1 - /* DI1_D1_CS */ - MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x400130b1 - /* DI1_PIN01 */ - MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x400130b1 - /* DI1_PIN03 */ - MX6QDL_PAD_EIM_DA12__GPIO3_IO12 0x400130b1 - /* DISP1_DATA08 */ - MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x400130b1 - /* DISP1_DATA09 */ - MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x400130b1 - /* DISP1_DATA10 */ - MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x400130b1 - /* DISP1_DATA11 */ - MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x400130b1 - /* DISP1_DATA12 */ - MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x400130b1 - /* DISP1_DATA13 */ - MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x400130b1 - /* DISP1_DATA14 */ - MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x400130b1 - /* DISP1_DATA15 */ - MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x400130b1 - /* DISP1_DATA16 */ - MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x400130b1 - /* DISP1_DATA17 */ - MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x400130b1 - /* DISP1_DATA18 */ - MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x400130b1 - /* DISP1_DATA19 */ - MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x400130b1 - /* DISP1_DATA20 */ - MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x400130b1 - /* DISP1_DATA21 */ - MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x400130b1 - /* DISP1_DATA22 */ - MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x400130b1 - /* DISP1_DATA23 */ - MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x400130b1 - /* DI1_DISP_CLK */ - MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x400130b1 - /* SPDIF_IN */ - MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x400130b1 - /* SPDIF_OUT */ - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x400130b1 - - /* MikroBUS GPIO pin number 10 */ - MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x400130b1 - >; - }; - - pinctrl_hummingboard2_ecspi2: hummingboard2-ecspi2grp { - fsl,pins = < - MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 - MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 - MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 - MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x000b1 /* CS */ - >; - }; - - pinctrl_hummingboard2_gpio7_9: hummingboard2-gpio7_9 { - fsl,pins = < - MX6QDL_PAD_SD4_CMD__GPIO7_IO09 0x80000000 - >; - }; - - pinctrl_hummingboard2_hdmi: hummingboard2-hdmi { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 - >; - }; - - pinctrl_hummingboard2_i2c1: hummingboard2-i2c1 { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_hummingboard2_i2c2: hummingboard2-i2c2 { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_hummingboard2_i2c3: hummingboard2-i2c3 { - fsl,pins = < - MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_hummingboard2_mipi: hummingboard2_mipi { - fsl,pins = < - MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x4001b8b1 - MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x4001b8b1 - MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x130b0 - >; - }; - - pinctrl_hummingboard2_pcie_reset: hummingboard2-pcie-reset { - fsl,pins = < - MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b1 - >; - }; - - pinctrl_hummingboard2_pwm1: pwm1grp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b1 - >; - }; - - pinctrl_hummingboard2_pwm3: pwm3grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 - >; - }; - - pinctrl_hummingboard2_sgtl5000: hummingboard2-sgtl5000 { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0 - MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0 - MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x110b0 - MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0 - MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x130b0 - >; - }; - - pinctrl_hummingboard2_usbh1_vbus: hummingboard2-usbh1-vbus { - fsl,pins = ; - }; - - pinctrl_hummingboard2_usbh2_vbus: hummingboard2-usbh2-vbus { - fsl,pins = ; - }; - - pinctrl_hummingboard2_usbh3_vbus: hummingboard2-usbh3-vbus { - fsl,pins = ; - }; - - pinctrl_hummingboard2_usbotg_id: hummingboard2-usbotg-id { - /* - * We want it pulled down for a fixed host connection. - */ - fsl,pins = ; - }; - - pinctrl_hummingboard2_usbotg_vbus: hummingboard2-usbotg-vbus { - fsl,pins = ; - }; - - pinctrl_hummingboard2_usdhc2_aux: hummingboard2-usdhc2-aux { - fsl,pins = < - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1f071 - MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x1b071 - >; - }; - - pinctrl_hummingboard2_usdhc2: hummingboard2-usdhc2 { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059 - >; - }; - - pinctrl_hummingboard2_usdhc2_100mhz: hummingboard2-usdhc2-100mhz { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x130b9 - >; - }; - - pinctrl_hummingboard2_usdhc2_200mhz: hummingboard2-usdhc2-200mhz { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170f9 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100f9 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x130f9 - >; - }; - - pinctrl_hummingboard2_vmmc: hummingboard2-vmmc { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x1b0b0 - >; - }; - - pinctrl_hummingboard2_uart3: hummingboard2-uart3 { - fsl,pins = < - MX6QDL_PAD_EIM_D25__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D24__UART3_RX_DATA 0x40013000 - >; - }; - }; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard2_pcie_reset>; - reset-gpio = <&gpio2 11 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard2_pwm1>; - status = "okay"; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard2_pwm3>; - status = "okay"; -}; - -&ssi1 { - status = "okay"; -}; - -&usbh1 { - disable-over-current; - status = "okay"; -}; - -&usbotg { - disable-over-current; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard2_usbotg_id>; - vbus-supply = <&v_usb1>; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = < - &pinctrl_hummingboard2_usdhc2_aux - &pinctrl_hummingboard2_usdhc2 - >; - pinctrl-1 = < - &pinctrl_hummingboard2_usdhc2_aux - &pinctrl_hummingboard2_usdhc2_100mhz - >; - pinctrl-2 = < - &pinctrl_hummingboard2_usdhc2_aux - &pinctrl_hummingboard2_usdhc2_200mhz - >; - vmmc-supply = <&v_sd>; - cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard2_uart3>; - status = "okay"; -}; - -&vcc_3v3 { - vin-supply = <&v_3v2>; -}; diff --git a/sys/gnu/dts/arm/imx6qdl-icore-1.5.dtsi b/sys/gnu/dts/arm/imx6qdl-icore-1.5.dtsi deleted file mode 100644 index 0fd7f2e24d9..00000000000 --- a/sys/gnu/dts/arm/imx6qdl-icore-1.5.dtsi +++ /dev/null @@ -1,32 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2018 Jacopo Mondi - */ - -#include "imx6qdl-icore.dtsi" - -&iomuxc { - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0b0 - MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 - MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 - MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 - MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 - MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 - >; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - clocks = <&clks IMX6QDL_CLK_ENET>, - <&clks IMX6QDL_CLK_ENET>, - <&clks IMX6QDL_CLK_ENET_REF>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx6qdl-icore-rqs.dtsi b/sys/gnu/dts/arm/imx6qdl-icore-rqs.dtsi deleted file mode 100644 index a4217f564a5..00000000000 --- a/sys/gnu/dts/arm/imx6qdl-icore-rqs.dtsi +++ /dev/null @@ -1,466 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR X11 -/* - * Copyright (C) 2015 Amarula Solutions B.V. - * Copyright (C) 2015 Engicam S.r.l. - */ - -#include -#include -#include - -/ { - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x80000000>; - }; - - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-name = "1P8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_2p5v: regulator-2p5v { - compatible = "regulator-fixed"; - regulator-name = "2P5V"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_sd3_vmmc: regulator-sd3-vmmc { - compatible = "regulator-fixed"; - regulator-name = "P3V3_SD3_SWITCHED"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio1 4 GPIO_ACTIVE_LOW>; - enable-active-high; - }; - - reg_sd4_vmmc: regulator-sd4-vmmc { - compatible = "regulator-fixed"; - regulator-name = "P3V3_SD4_SWITCHED"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_usb_h1_vbus: regulator-usb-h1-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_usb_otg_vbus: regulator-usb-otg-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - regulator-always-on; - }; - - usb_hub: usb-hub { - compatible = "smsc,usb3503a"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbhub>; - reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; - clocks = <&clks IMX6QDL_CLK_LVDS2_GATE>; - clock-names = "refclk"; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "imx6qdl-icore-rqs-sgtl5000"; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&dailink_master>; - simple-audio-card,frame-master = <&dailink_master>; - simple-audio-card,widgets = - "Microphone", "Mic Jack", - "Headphone", "Headphone Jack", - "Line", "Line In Jack", - "Speaker", "Line Out Jack", - "Speaker", "Ext Spk"; - simple-audio-card,routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - - simple-audio-card,cpu { - sound-dai = <&ssi1>; - }; - - dailink_master: simple-audio-card,codec { - sound-dai = <&sgtl5000>; - }; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; - - audmux_ssi1 { - fsl,audmux-port = ; - fsl,port-config = < - (IMX_AUDMUX_V2_PTCR_TFSDIR | - IMX_AUDMUX_V2_PTCR_TFSEL(MX51_AUDMUX_PORT4) | - IMX_AUDMUX_V2_PTCR_TCLKDIR | - IMX_AUDMUX_V2_PTCR_TCSEL(MX51_AUDMUX_PORT4) | - IMX_AUDMUX_V2_PTCR_SYN) - IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT4) - >; - }; - - audmux_aud4 { - fsl,audmux-port = ; - fsl,port-config = < - IMX_AUDMUX_V2_PTCR_SYN - IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT1_SSI0) - >; - }; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can1>; - xceiver-supply = <®_3p3v>; - status = "okay"; -}; - -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can2>; - xceiver-supply = <®_3p3v>; - status = "okay"; -}; - -&clks { - assigned-clocks = <&clks IMX6QDL_CLK_LVDS2_SEL>; - assigned-clock-parents = <&clks IMX6QDL_CLK_OSC>; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-handle = <ð_phy>; - phy-mode = "rgmii"; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - eth_phy: ethernet-phy@0 { - reg = <0x0>; - rxc-skew-ps = <1140>; - txc-skew-ps = <1140>; - txen-skew-ps = <600>; - rxdv-skew-ps = <240>; - rxd0-skew-ps = <420>; - rxd1-skew-ps = <600>; - rxd2-skew-ps = <420>; - rxd3-skew-ps = <240>; - txd0-skew-ps = <60>; - txd1-skew-ps = <60>; - txd2-skew-ps = <60>; - txd3-skew-ps = <240>; - }; - }; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - sgtl5000: codec@a { - #sound-dai-cells = <0>; - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - clocks = <&clks IMX6QDL_CLK_CKO>; - VDDA-supply = <®_2p5v>; - VDDIO-supply = <®_3p3v>; - VDDD-supply = <®_1p8v>; - }; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio3 29 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&ssi1 { - fsl,mode = "i2s-slave"; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usb_h1_vbus>; - disable-over-current; - clocks = <&clks IMX6QDL_CLK_USBOH3>; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - no-1-8-v; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - vmcc-supply = <®_sd3_vmmc>; - cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; - bus-width = <4>; - no-1-8-v; - status = "okay"; -}; - -&usdhc4 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc4>; - pinctrl-1 = <&pinctrl_usdhc4_100mhz>; - pinctrl-2 = <&pinctrl_usdhc4_200mhz>; - vmcc-supply = <®_sd4_vmmc>; - bus-width = <8>; - no-1-8-v; - non-removable; - status = "okay"; -}; - -&iomuxc { - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0 - MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x110b0 - MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0 - MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 - >; - }; - - pinctrl_can1: can1grp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b020 - MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b020 - >; - }; - - pinctrl_can2: can2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b020 - MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b020 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = < - MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1f059 /* PCIe Reset */ - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbhub: usbhubgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1f059 /* HUB USB Reset */ - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17070 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10070 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17070 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17070 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17070 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17070 - MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x1f059 /* CD */ - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1f059 /* PWR */ - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170B1 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100B1 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170B1 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170B1 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170B1 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170B1 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3grp_200mhz { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170F9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100F9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170F9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170F9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170F9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170F9 - >; - }; - - pinctrl_usdhc4: usdhc4grp { - fsl,pins = < - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17070 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10070 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17070 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17070 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17070 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17070 - MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17070 - MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17070 - MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17070 - MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17070 - >; - }; - - pinctrl_usdhc4_100mhz: usdhc4grp_100mhz { - fsl,pins = < - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x170B1 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x100B1 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x170B1 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x170B1 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x170B1 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x170B1 - MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x170B1 - MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x170B1 - MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x170B1 - MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x170B1 - >; - }; - - pinctrl_usdhc4_200mhz: usdhc4grp_200mhz { - fsl,pins = < - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x170F9 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x100F9 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x170F9 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x170F9 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x170F9 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x170F9 - MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x170F9 - MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x170F9 - MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x170F9 - MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x170F9 - >; - }; -}; diff --git a/sys/gnu/dts/arm/imx6qdl-icore.dtsi b/sys/gnu/dts/arm/imx6qdl-icore.dtsi deleted file mode 100644 index 756f3a9f1b4..00000000000 --- a/sys/gnu/dts/arm/imx6qdl-icore.dtsi +++ /dev/null @@ -1,429 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR X11 -/* - * Copyright (C) 2016 Amarula Solutions B.V. - * Copyright (C) 2016 Engicam S.r.l. - */ - -#include -#include -#include - -/ { - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x80000000>; - }; - - chosen { - stdout-path = &uart4; - }; - - backlight_lvds: backlight-lvds { - compatible = "pwm-backlight"; - pwms = <&pwm3 0 100000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <7>; - }; - - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-name = "1P8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_2p5v: regulator-2p5v { - compatible = "regulator-fixed"; - regulator-name = "2P5V"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_usb_h1_vbus: regulator-usb-h1-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_usb_otg_vbus: regulator-usb-otg-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - regulator-always-on; - }; - - rmii_clk: clock-rmii-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; /* 25MHz for example */ - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "imx6qdl-icore-sgtl5000"; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&dailink_master>; - simple-audio-card,frame-master = <&dailink_master>; - simple-audio-card,widgets = - "Microphone", "Mic Jack", - "Headphone", "Headphone Jack", - "Line", "Line In Jack", - "Speaker", "Line Out Jack", - "Speaker", "Ext Spk"; - simple-audio-card,routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - - simple-audio-card,cpu { - sound-dai = <&ssi1>; - }; - - dailink_master: simple-audio-card,codec { - sound-dai = <&sgtl5000>; - }; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; - - - audmux_ssi1 { - fsl,audmux-port = ; - fsl,port-config = < - (IMX_AUDMUX_V2_PTCR_TFSDIR | - IMX_AUDMUX_V2_PTCR_TFSEL(MX51_AUDMUX_PORT4) | - IMX_AUDMUX_V2_PTCR_TCLKDIR | - IMX_AUDMUX_V2_PTCR_TCSEL(MX51_AUDMUX_PORT4) | - IMX_AUDMUX_V2_PTCR_SYN) - IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT4) - >; - }; - - audmux_aud4 { - fsl,audmux-port = ; - fsl,port-config = < - IMX_AUDMUX_V2_PTCR_SYN - IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT1_SSI0) - >; - }; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - xceiver-supply = <®_3p3v>; -}; - -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - xceiver-supply = <®_3p3v>; -}; - -&clks { - assigned-clocks = <&clks IMX6QDL_CLK_LVDS2_SEL>; - assigned-clock-parents = <&clks IMX6QDL_CLK_OSC>; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - clocks = <&clks IMX6QDL_CLK_ENET>, <&clks IMX6QDL_CLK_ENET>, <&rmii_clk>; - phy-mode = "rmii"; - phy-handle = <ð_phy>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - eth_phy: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - reset-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>; - reset-assert-us = <4000>; - reset-deassert-us = <4000>; - }; - }; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - nand-on-flash-bbt; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - ov5640: camera@3c { - compatible = "ovti,ov5640"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ov5640>; - reg = <0x3c>; - clocks = <&clks IMX6QDL_CLK_CKO>; - clock-names = "xclk"; - DOVDD-supply = <®_1p8v>; - AVDD-supply = <®_3p3v>; - DVDD-supply = <®_3p3v>; - powerdown-gpios = <&gpio5 30 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio5 31 GPIO_ACTIVE_LOW>; - status = "disabled"; - - port { - ov5640_to_mipi_csi2: endpoint { - remote-endpoint = <&mipi_csi2_in>; - clock-lanes = <0>; - data-lanes = <1 2>; - }; - }; - }; - - sgtl5000: codec@a { - #sound-dai-cells = <0>; - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - clocks = <&clks IMX6QDL_CLK_CKO>; - VDDA-supply = <®_2p5v>; - VDDIO-supply = <®_3p3v>; - VDDD-supply = <®_1p8v>; - }; -}; - -&mipi_csi { - status = "disabled"; - - port@0 { - reg = <0>; - - mipi_csi2_in: endpoint { - remote-endpoint = <&ov5640_to_mipi_csi2>; - clock-lanes = <0>; - data-lanes = <1 2>; - }; - }; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; - status = "okay"; -}; - -&ssi1 { - fsl,mode = "i2s-slave"; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usb_h1_vbus>; - disable-over-current; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; - no-1-8-v; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - no-1-8-v; - non-removable; - status = "disabled"; -}; - -&iomuxc { - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0 - MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x110b0 - MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0 - MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x1b0b1 - MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 - MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 - MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 - MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 - MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1b0b0 - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b020 - MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b020 - >; - }; - - pinctrl_flexcan2: flexcan2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b020 - MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b020 - >; - }; - - pinctrl_gpmi_nand: gpminandgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 - MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_ov5640: ov5640grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x1b0b0 - MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x1b0b0 - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17070 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10070 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17070 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17070 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17070 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17070 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 - >; - }; -}; diff --git a/sys/gnu/dts/arm/imx6qdl-kontron-samx6i.dtsi b/sys/gnu/dts/arm/imx6qdl-kontron-samx6i.dtsi deleted file mode 100644 index 81c7ebb4b3f..00000000000 --- a/sys/gnu/dts/arm/imx6qdl-kontron-samx6i.dtsi +++ /dev/null @@ -1,815 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR X11 -/* - * Copyright 2017 (C) Priit Laes - * Copyright 2018 (C) Pengutronix, Michael Grzeschik - * Copyright 2019 (C) Pengutronix, Marco Felsch - * - * Based on initial work by Nikita Yushchenko - */ - -#include -#include - -/ { - reg_1p0v_s0: regulator-1p0v-s0 { - compatible = "regulator-fixed"; - regulator-name = "V_1V0_S0"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <®_smarc_suppy>; - }; - - reg_1p35v_vcoredig_s5: regulator-1p35v-vcoredig-s5 { - compatible = "regulator-fixed"; - regulator-name = "V_1V35_VCOREDIG_S5"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <®_3p3v_s5>; - }; - - reg_1p8v_s5: regulator-1p8v-s5 { - compatible = "regulator-fixed"; - regulator-name = "V_1V8_S5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <®_3p3v_s5>; - }; - - reg_3p3v_s0: regulator-3p3v-s0 { - compatible = "regulator-fixed"; - regulator-name = "V_3V3_S0"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <®_3p3v_s5>; - }; - - reg_3p3v_s0: regulator-3p3v-s0 { - compatible = "regulator-fixed"; - regulator-name = "V_3V3_S0"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <®_3p3v_s5>; - }; - - reg_3p3v_s5: regulator-3p3v-s5 { - compatible = "regulator-fixed"; - regulator-name = "V_3V3_S5"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <®_smarc_suppy>; - }; - - reg_smarc_lcdbklt: regulator-smarc-lcdbklt { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcdbklt_en>; - regulator-name = "LCD_BKLT_EN"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio1 16 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_smarc_lcdvdd: regulator-smarc-lcdvdd { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcdvdd_en>; - regulator-name = "LCD_VDD_EN"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio1 17 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_smarc_rtc: regulator-smarc-rtc { - compatible = "regulator-fixed"; - regulator-name = "V_IN_RTC_BATT"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - /* Module supply range can be 3.00V ... 5.25V */ - reg_smarc_suppy: regulator-smarc-supply { - compatible = "regulator-fixed"; - regulator-name = "V_IN_WIDE"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - lcd: lcd { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx-parallel-display"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd>; - status = "disabled"; - - port@0 { - reg = <0>; - - lcd_in: endpoint { - }; - }; - - port@1 { - reg = <1>; - - lcd_out: endpoint { - }; - }; - }; - - lcd_backlight: lcd-backlight { - compatible = "pwm-backlight"; - pwms = <&pwm4 0 5000000>; - pwm-names = "LCD_BKLT_PWM"; - - brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; - default-brightness-level = <4>; - - power-supply = <®_smarc_lcdbklt>; - status = "disabled"; - }; - - i2c_intern: i2c-gpio-intern { - compatible = "i2c-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c_gpio_intern>; - sda-gpios = <&gpio1 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <2>; /* ~100 kHz */ - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c_lcd: i2c-gpio-lcd { - compatible = "i2c-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c_gpio_lcd>; - sda-gpios = <&gpio1 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpio1 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <2>; /* ~100 kHz */ - #address-cells = <1>; - #size-cells = <0>; - status = "disabld"; - }; - - i2c_cam: i2c-gpio-cam { - compatible = "i2c-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c_gpio_cam>; - sda-gpios = <&gpio4 10 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <2>; /* ~100 kHz */ - #address-cells = <1>; - #size-cells = <0>; - status = "disabld"; - }; -}; - -/* I2S0, I2S1 */ -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - - audmux_ssi1 { - fsl,audmux-port = ; - fsl,port-config = < - (IMX_AUDMUX_V2_PTCR_TFSEL(MX51_AUDMUX_PORT3) | - IMX_AUDMUX_V2_PTCR_TCSEL(MX51_AUDMUX_PORT3) | - IMX_AUDMUX_V2_PTCR_SYN | - IMX_AUDMUX_V2_PTCR_TFSDIR | - IMX_AUDMUX_V2_PTCR_TCLKDIR) - IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT3) - >; - }; - - audmux_adu3 { - fsl,audmux-port = ; - fsl,port-config = < - IMX_AUDMUX_V2_PTCR_SYN - IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT1_SSI0) - >; - }; - - audmux_ssi2 { - fsl,audmux-port = ; - fsl,port-config = < - (IMX_AUDMUX_V2_PTCR_TFSEL(MX51_AUDMUX_PORT4) | - IMX_AUDMUX_V2_PTCR_TCSEL(MX51_AUDMUX_PORT4) | - IMX_AUDMUX_V2_PTCR_SYN | - IMX_AUDMUX_V2_PTCR_TFSDIR | - IMX_AUDMUX_V2_PTCR_TCLKDIR) - IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT4) - >; - }; - - audmux_adu4 { - fsl,audmux-port = ; - fsl,port-config = < - IMX_AUDMUX_V2_PTCR_SYN - IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT2_SSI1) - >; - }; -}; - -/* CAN0 */ -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; -}; - -/* CAN1 */ -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; -}; - -/* SPI1 */ -&ecspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi2>; - cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>, - <&gpio2 27 GPIO_ACTIVE_HIGH>; -}; - -/* SPI0 */ -&ecspi4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi4>; - cs-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>, - <&gpio3 29 GPIO_ACTIVE_HIGH>; - status = "okay"; - - /* default boot source: workaround #1 for errata ERR006282 */ - smarc_flash: spi-flash@0 { - compatible = "winbond,w25q16dw", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <20000000>; - }; -}; - -/* GBE */ -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii"; - phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; -}; - -&i2c_intern { - pmic@8 { - compatible = "fsl,pfuze100"; - reg = <0x08>; - - regulators { - reg_v_core_s0: sw1ab { - regulator-name = "V_CORE_S0"; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_vddsoc_s0: sw1c { - regulator-name = "V_VDDSOC_S0"; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_3p15v_s0: sw2 { - regulator-name = "V_3V15_S0"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - /* sw3a/b is used in dual mode, but driver does not - * support it. Although, there's no need to control - * DDR power - so just leaving dummy entries for sw3a - * and sw3b for now. - */ - sw3a { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3b { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_1p8v_s0: sw4 { - regulator-name = "V_1V8_S0"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - /* Regulator for USB */ - reg_5p0v_s0: swbst { - regulator-name = "V_5V0_S0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - regulator-boot-on; - }; - - reg_vsnvs: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_vrefddr: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - /* - * Per schematics, of all VGEN's, only VGEN5 has some - * usage ... but even that - over DNI resistor - */ - vgen1 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - vgen4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - reg_2p5v_s0: vgen5 { - regulator-name = "V_2V5_S0"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - vgen6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - }; - }; -}; - -/* I2C_GP */ -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; -}; - -/* HDMI_CTRL */ -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; -}; - -/* I2C_PM */ -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - smarc_eeprom: eeprom@50 { - compatible = "atmel,24c32"; - reg = <0x50>; - pagesize = <32>; - }; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mgmt_gpios &pinctrl_gpio>; - - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 - MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x130b0 - MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 - MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 - - MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0 - MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x130b0 - MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0 - MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0 - - /* AUDIO MCLK */ - MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x000b0 - >; - }; - - pinctrl_ecspi2: ecspi2grp { - fsl,pins = < - MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 - MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 - MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 - - MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x1b0b0 /* CS0 */ - MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b0 /* CS1 */ - >; - }; - - pinctrl_ecspi4: ecspi4grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1 - MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1 - MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1 - - /* SPI_IMX_CS2# - connected to internal flash */ - MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x1b0b0 - /* SPI_IMX_CS0# - connected to SMARC SPI0_CS0# */ - MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0 - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0 - MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0 - >; - }; - - pinctrl_flexcan2: flexcan2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0 - MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0 - >; - }; - - pinctrl_gpio: gpiogrp { - fsl,pins = < - MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x1b0b0 /* GPIO0 / CAM0_PWR# */ - MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x1b0b0 /* GPIO1 / CAM1_PWR# */ - MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x1b0b0 /* GPIO2 / CAM0_RST# */ - MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x1b0b0 /* GPIO3 / CAM1_RST# */ - MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x1b0b0 /* GPIO4 / HDA_RST# */ - MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x1b0b0 /* GPIO5 / PWM_OUT */ - MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x1b0b0 /* GPIO6 / TACHIN */ - MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x1b0b0 /* GPIO7 / PCAM_FLD */ - MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x1b0b0 /* GPIO8 / CAN0_ERR# */ - MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x1b0b0 /* GPIO9 / CAN1_ERR# */ - MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x1b0b0 /* GPIO10 */ - MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0x1b0b0 /* GPIO11 */ - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 - - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 /* RST_GBE0_PHY# */ - >; - }; - - pinctrl_i2c_gpio_cam: i2c-gpiocamgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0 /* SCL */ - MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 /* SDA */ - >; - }; - - pinctrl_i2c_gpio_intern: i2c-gpiointerngrp { - fsl,pins = < - MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 /* SCL */ - MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* SDA */ - >; - }; - - pinctrl_i2c_gpio_lcd: i2c-gpiolcdgrp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x1b0b0 /* SCL */ - MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x1b0b0 /* SDA */ - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_lcd: lcdgrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x100f1 - MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x100f1 - MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x100f1 - MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x100f1 - MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x100f1 - MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x100f1 - MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x100f1 - MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x100f1 - MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x100f1 - MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x100f1 - MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x100f1 - MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x100f1 - MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x100f1 - MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x100f1 - MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x100f1 - MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x100f1 - MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x100f1 - MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x100f1 - MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x100f1 - MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x100f1 - MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x100f1 - MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x100f1 - MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x100f1 - MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x100f1 - - MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x100f1 - MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x100f1 /* DE */ - MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x100f1 /* HSYNC */ - MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x100f1 /* VSYNC */ - >; - }; - - pinctrl_lcdbklt_en: lcdbkltengrp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b1 - >; - }; - - pinctrl_lcdvdd_en: lcdvddengrp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b0b0 - >; - }; - - pinctrl_mipi_csi: mipi-csigrp { - fsl,pins = < - MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x000b0 /* CSI0/1 MCLK */ - >; - }; - - pinctrl_mgmt_gpios: mgmt-gpiosgrp { - fsl,pins = < - MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1b0b0 /* LID# */ - MX6QDL_PAD_SD3_DAT7__GPIO6_IO17 0x1b0b0 /* SLEEP# */ - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 /* CHARGING# */ - MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 /* CHARGER_PRSNT# */ - MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x1b0b0 /* CARRIER_STBY# */ - MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b0 /* BATLOW# */ - MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1b0b0 /* TEST# */ - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 /* VDD_IO_SEL_D# */ - MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x1b0b0 /* POWER_BTN# */ - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = < - MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x1b0b0 /* PCI_A_PRSNT# */ - MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x1b0b0 /* RST_PCIE_A# */ - MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x1b0b0 /* PCIE_WAKE# */ - >; - }; - - pinctrl_pwm4: pwm4grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D20__UART1_RTS_B 0x1b0b1 - MX6QDL_PAD_EIM_D19__UART1_CTS_B 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1 - MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x1f8b0 - /* power, oc muxed but not used by the driver */ - MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b0 /* USB power */ - MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b0 /* USB OC */ - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x17059 - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - - MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0 /* CD */ - MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b0 /* WP */ - MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PWR_EN */ - >; - }; - - pinctrl_usdhc4: usdhc4grp { - fsl,pins = < - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x17059 - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 - MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 - MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 - MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 - MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 - >; - }; - - pinctrl_wdog1: wdog1rp { - fsl,pins = < - MX6QDL_PAD_GPIO_9__WDOG1_B 0x1b0b0 - >; - }; -}; - -&mipi_csi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mipi_csi>; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - wake-up-gpio = <&gpio6 18 GPIO_ACTIVE_HIGH>; - reset-gpio = <&gpio3 13 GPIO_ACTIVE_HIGH>; -}; - -/* LCD_BKLT_PWM */ -&pwm4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm4>; -}; - -®_arm { - vin-supply = <®_v_core_s0>; -}; - -®_pu { - vin-supply = <®_vddsoc_s0>; -}; - -®_soc { - vin-supply = <®_vddsoc_s0>; -}; - -/* SER0 */ -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - uart-has-rtscts; -}; - -/* SER1 */ -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; -}; - -/* SER2 */ -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - uart-has-rtscts; -}; - -/* SER3 */ -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; -}; - -/* USB0 */ -&usbotg { - /* - * no 'imx6-usb-charger-detection' - * since USB_OTG_CHD_B pin is not wired - */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; -}; - -/* USB1/2 via hub */ -&usbh1 { - vbus-supply = <®_5p0v_s0>; -}; - -/* SDIO */ -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; - no-1-8-v; -}; - -/* SDMMC */ -&usdhc4 { - /* Internal eMMC, optional on some boards */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc4>; - bus-width = <8>; - no-sdio; - no-sd; - non-removable; - vmmc-supply = <®_3p3v_s0>; - vqmmc-supply = <®_1p8v_s0>; -}; - -&wdog1 { - /* CPLD is feeded by watchdog (hardwired) */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog1>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx6qdl-microsom-ar8035.dtsi b/sys/gnu/dts/arm/imx6qdl-microsom-ar8035.dtsi deleted file mode 100644 index 469ef58ce4b..00000000000 --- a/sys/gnu/dts/arm/imx6qdl-microsom-ar8035.dtsi +++ /dev/null @@ -1,99 +0,0 @@ -/* - * Copyright (C) 2013,2014 Russell King - * - * This describes the hookup for an AR8035 to the iMX6 on the SolidRun - * MicroSOM. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_microsom_enet_ar8035>; - phy-mode = "rgmii"; - phy-reset-duration = <2>; - phy-reset-gpios = <&gpio4 15 0>; - status = "okay"; -}; - -&iomuxc { - enet { - pinctrl_microsom_enet_ar8035: microsom-enet-ar8035 { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b8b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - /* AR8035 reset */ - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x130b0 - /* AR8035 interrupt */ - MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x80000000 - /* GPIO16 -> AR8035 25MHz */ - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0xc0000000 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x80000000 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */ - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x0a0b1 - /* AR8035 pin strapping: IO voltage: pull up */ - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - /* AR8035 pin strapping: PHYADDR#0: pull down */ - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x13030 - /* AR8035 pin strapping: PHYADDR#1: pull down */ - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030 - /* AR8035 pin strapping: MODE#1: pull up */ - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - /* AR8035 pin strapping: MODE#3: pull up */ - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - /* AR8035 pin strapping: MODE#0: pull down */ - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030 - - /* - * As the RMII pins are also connected to RGMII - * so that an AR8030 can be placed, set these - * to high-z with the same pulls as above. - * Use the GPIO settings to avoid changing the - * input select registers. - */ - MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x03000 - MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x03000 - MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x03000 - >; - }; - }; -}; diff --git a/sys/gnu/dts/arm/imx6qdl-microsom.dtsi b/sys/gnu/dts/arm/imx6qdl-microsom.dtsi deleted file mode 100644 index 6d4069cc941..00000000000 --- a/sys/gnu/dts/arm/imx6qdl-microsom.dtsi +++ /dev/null @@ -1,160 +0,0 @@ -/* - * Copyright (C) 2013,2014 Russell King - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -#include -/ { - clk_sdio: sdio-clock { - compatible = "gpio-gate-clock"; - #clock-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_microsom_brcm_osc>; - enable-gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>; - }; - - regulators { - compatible = "simple-bus"; - - reg_brcm: brcm-reg { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio3 19 0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_microsom_brcm_reg>; - regulator-name = "brcm_reg"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <200000>; - }; - }; - - usdhc1_pwrseq: usdhc1_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio5 26 GPIO_ACTIVE_LOW>, - <&gpio6 0 GPIO_ACTIVE_LOW>; - clocks = <&clk_sdio>; - clock-names = "ext_clock"; - }; -}; - -&iomuxc { - microsom { - pinctrl_microsom_brcm_bt: microsom-brcm-bt { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00 0x40013070 - MX6QDL_PAD_CSI0_DAT15__GPIO6_IO01 0x40013070 - MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04 0x40013070 - >; - }; - - pinctrl_microsom_brcm_osc: microsom-brcm-osc { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x40013070 - >; - }; - - pinctrl_microsom_brcm_reg: microsom-brcm-reg { - fsl,pins = < - MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x40013070 - >; - }; - - pinctrl_microsom_brcm_wifi: microsom-brcm-wifi { - fsl,pins = < - MX6QDL_PAD_GPIO_8__XTALOSC_REF_CLK_32K 0x1b0b0 - MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x40013070 - MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x40013070 - MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x40013070 - >; - }; - - pinctrl_microsom_uart1: microsom-uart1 { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_microsom_uart4: microsom-uart4 { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1 - MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1 - >; - }; - - pinctrl_microsom_usdhc1: microsom-usdhc1 { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 - >; - }; - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_microsom_uart1>; - status = "okay"; -}; - -/* UART4 - Connected to optional BRCM Wifi/BT/FM */ -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_microsom_brcm_bt &pinctrl_microsom_uart4>; - fsl,uart-has-rtscts; - status = "okay"; -}; - -/* USDHC1 - Connected to optional BRCM Wifi/BT/FM */ -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_microsom_brcm_wifi &pinctrl_microsom_usdhc1>; - bus-width = <4>; - mmc-pwrseq = <&usdhc1_pwrseq>; - keep-power-in-suspend; - non-removable; - vmmc-supply = <®_brcm>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx6qdl-nit6xlite.dtsi b/sys/gnu/dts/arm/imx6qdl-nit6xlite.dtsi deleted file mode 100644 index 2418cf8f231..00000000000 --- a/sys/gnu/dts/arm/imx6qdl-nit6xlite.dtsi +++ /dev/null @@ -1,570 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR X11 -/* - * Copyright 2015 Boundary Devices, Inc. - */ -#include -#include - -/ { - chosen { - stdout-path = &uart2; - }; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x20000000>; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_2p5v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "2P5V"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - reg_3p3v: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_usb_otg_vbus: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_wlan_vmmc: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wlan_vmmc>; - regulator-name = "reg_wlan_vmmc"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio6 7 GPIO_ACTIVE_HIGH>; - startup-delay-us = <70000>; - enable-active-high; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_keys>; - - home { - label = "Home"; - gpios = <&gpio7 13 IRQ_TYPE_LEVEL_LOW>; - linux,code = <102>; - }; - - back { - label = "Back"; - gpios = <&gpio4 5 IRQ_TYPE_LEVEL_LOW>; - linux,code = <158>; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_leds>; - - j14-pin1 { - gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; - retain-state-suspended; - default-state = "off"; - }; - - j14-pin3 { - gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; - retain-state-suspended; - default-state = "off"; - }; - - j14-pins8-9 { - gpios = <&gpio3 29 GPIO_ACTIVE_LOW>; - retain-state-suspended; - default-state = "off"; - }; - - j46-pin2 { - gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; - retain-state-suspended; - default-state = "off"; - }; - - j46-pin3 { - gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; - retain-state-suspended; - default-state = "off"; - }; - }; - - backlight-lcd { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <7>; - power-supply = <®_3p3v>; - status = "okay"; - }; - - backlight_lvds0: backlight-lvds0 { - compatible = "pwm-backlight"; - pwms = <&pwm4 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <7>; - power-supply = <®_3p3v>; - status = "okay"; - }; - - panel-lvds0 { - compatible = "hannstar,hsd100pxn1"; - backlight = <&backlight_lvds0>; - - port { - panel_in_lvds0: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - }; - - sound { - compatible = "fsl,imx6dl-nit6xlite-sgtl5000", - "fsl,imx-audio-sgtl5000"; - model = "imx6dl-nit6xlite-sgtl5000"; - ssi-controller = <&ssi1>; - audio-codec = <&codec>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - mux-int-port = <1>; - mux-ext-port = <3>; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; - -&clks { - assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, - <&clks IMX6QDL_CLK_LDB_DI1_SEL>; - assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, - <&clks IMX6QDL_CLK_PLL3_USB_OTG>; -}; - -&ecspi1 { - cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - status = "okay"; - - flash: m25p80@0 { - compatible = "microchip,sst25vf016b"; - spi-max-frequency = <20000000>; - reg = <0>; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii"; - phy-reset-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>; - txen-skew-ps = <0>; - txc-skew-ps = <3000>; - rxdv-skew-ps = <0>; - rxc-skew-ps = <3000>; - rxd0-skew-ps = <0>; - rxd1-skew-ps = <0>; - rxd2-skew-ps = <0>; - rxd3-skew-ps = <0>; - txd0-skew-ps = <0>; - txd1-skew-ps = <0>; - txd2-skew-ps = <0>; - txd3-skew-ps = <0>; - interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, - <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; - fsl,err006687-workaround-present; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c2>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - codec: sgtl5000@a { - compatible = "fsl,sgtl5000"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sgtl5000>; - reg = <0x0a>; - clocks = <&clks IMX6QDL_CLK_CKO>; - VDDA-supply = <®_2p5v>; - VDDIO-supply = <®_3p3v>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - touchscreen@4 { - compatible = "eeti,egalax_ts"; - reg = <0x04>; - interrupt-parent = <&gpio1>; - interrupts = <9 IRQ_TYPE_EDGE_FALLING>; - wakeup-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; - }; - - touchscreen@38 { - compatible = "edt,edt-ft5x06"; - reg = <0x38>; - interrupt-parent = <&gpio1>; - interrupts = <9 IRQ_TYPE_EDGE_FALLING>; - wakeup-source; - }; - - rtc@6f { - compatible = "isil,isl1208"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rtc>; - reg = <0x6f>; - interrupts-extended = <&gpio2 26 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_j10>; - pinctrl-1 = <&pinctrl_j28>; - - imx6dl-nit6xlite { - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 - MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 - MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 - MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 - MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - /* Phy reset */ - MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x0f0b0 - MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 - MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 - >; - }; - - pinctrl_gpio_keys: gpio-keysgrp { - fsl,pins = < - /* Home Button: J14 pin 5 */ - MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 - /* Back Button: J14 pin 7 */ - MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 - /* Touch IRQ: J7 pin 4 */ - MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 - /* tcs2004 IRQ */ - MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b0 - /* tsc2004 reset */ - MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x0b0b0 - >; - }; - - pinctrl_j10: j10grp { - fsl,pins = < - /* Broadcom WiFi module pins */ - MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0 - MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 - MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 - MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 - MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x0b0b0 - MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0 - MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x000b0 - >; - }; - - pinctrl_j28: j28grp { - fsl,pins = < - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 - >; - }; - - pinctrl_leds: ledsgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x0b0b0 - MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x0b0b0 - MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x030b0 - MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x0b0b0 - MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0b0b0 - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm4: pwm4grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 - >; - }; - - pinctrl_wlan_vmmc: wlan-vmmcgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x030b0 - >; - }; - - pinctrl_rtc: rtcgrp { - fsl,pins = < - MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x1b0b0 - >; - }; - - pinctrl_sgtl5000: sgtl5000grp { - fsl,pins = < - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 - MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b0 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 - MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 - /* power enable, high active */ - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x000b0 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 - >; - }; - }; -}; - -&ldb { - status = "okay"; - - lvds-channel@0 { - status = "okay"; - - port@4 { - reg = <4>; - - lvds0_out: endpoint { - remote-endpoint = <&panel_in_lvds0>; - }; - }; - }; -}; - -&pcie { - status = "okay"; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "okay"; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; - status = "okay"; -}; - -&pwm4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm4>; - status = "okay"; -}; - -&ssi1 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - uart-has-rtscts; - status = "okay"; -}; - -&usbh1 { - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - bus-width = <4>; - non-removable; - vmmc-supply = <®_3p3v>; - vqmmc-supply = <®_wlan_vmmc>; - cap-power-off-card; - keep-power-in-suspend; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_3p3v>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx6qdl-nitrogen6_max.dtsi b/sys/gnu/dts/arm/imx6qdl-nitrogen6_max.dtsi deleted file mode 100644 index c3415aa348a..00000000000 --- a/sys/gnu/dts/arm/imx6qdl-nitrogen6_max.dtsi +++ /dev/null @@ -1,835 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR X11 -/* - * Copyright 2015 Boundary Devices, Inc. - */ -#include -#include - -/ { - chosen { - stdout-path = &uart2; - }; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0xF0000000>; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_1p8v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "1P8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - reg_2p5v: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "2P5V"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - reg_3p3v: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_usb_otg_vbus: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usb_h1_vbus: regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh1>; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_wlan_vmmc: regulator@5 { - compatible = "regulator-fixed"; - reg = <5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wlan_vmmc>; - regulator-name = "reg_wlan_vmmc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio6 15 GPIO_ACTIVE_HIGH>; - startup-delay-us = <70000>; - enable-active-high; - }; - - reg_can_xcvr: regulator@6 { - compatible = "regulator-fixed"; - reg = <6>; - regulator-name = "CAN XCVR"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can_xcvr>; - gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_keys>; - - power { - label = "Power Button"; - gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - - menu { - label = "Menu"; - gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - home { - label = "Home"; - gpios = <&gpio2 4 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - back { - label = "Back"; - gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - volume-up { - label = "Volume Up"; - gpios = <&gpio7 13 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - volume-down { - label = "Volume Down"; - gpios = <&gpio7 1 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - i2c2mux { - compatible = "i2c-mux-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2mux>; - #address-cells = <1>; - #size-cells = <0>; - mux-gpios = <&gpio3 20 GPIO_ACTIVE_HIGH - &gpio4 15 GPIO_ACTIVE_HIGH>; - i2c-parent = <&i2c2>; - idle-state = <0>; - - i2c2mux@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c2mux@2 { - reg = <2>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - i2c3mux { - compatible = "i2c-mux-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3mux>; - #address-cells = <1>; - #size-cells = <0>; - mux-gpios = <&gpio2 25 GPIO_ACTIVE_HIGH>; - i2c-parent = <&i2c3>; - idle-state = <0>; - - i2c3mux@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - leds { - compatible = "gpio-leds"; - - speaker-enable { - gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; - retain-state-suspended; - default-state = "off"; - }; - - ttymxc4-rs232 { - gpios = <&gpio6 10 GPIO_ACTIVE_HIGH>; - retain-state-suspended; - default-state = "on"; - }; - }; - - backlight_lcd: backlight-lcd { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <7>; - power-supply = <®_3p3v>; - status = "okay"; - }; - - backlight_lvds0: backlight-lvds0 { - compatible = "pwm-backlight"; - pwms = <&pwm4 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <7>; - power-supply = <®_3p3v>; - status = "okay"; - }; - - backlight_lvds1: backlight-lvds1 { - compatible = "pwm-backlight"; - pwms = <&pwm2 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <7>; - power-supply = <®_3p3v>; - status = "okay"; - }; - - lcd_display: disp0 { - compatible = "fsl,imx-parallel-display"; - #address-cells = <1>; - #size-cells = <0>; - interface-pix-fmt = "bgr666"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_j15>; - status = "okay"; - - port@0 { - reg = <0>; - - lcd_display_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - - port@1 { - reg = <1>; - - lcd_display_out: endpoint { - remote-endpoint = <&lcd_panel_in>; - }; - }; - }; - - panel-lcd { - compatible = "okaya,rs800480t-7x0gp"; - backlight = <&backlight_lcd>; - - port { - lcd_panel_in: endpoint { - remote-endpoint = <&lcd_display_out>; - }; - }; - }; - - panel-lvds0 { - compatible = "hannstar,hsd100pxn1"; - backlight = <&backlight_lvds0>; - - port { - panel_in_lvds0: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - }; - - panel-lvds1 { - compatible = "hannstar,hsd100pxn1"; - backlight = <&backlight_lvds1>; - - port { - panel_in_lvds1: endpoint { - remote-endpoint = <&lvds1_out>; - }; - }; - }; - - sound { - compatible = "fsl,imx6q-nitrogen6_max-sgtl5000", - "fsl,imx-audio-sgtl5000"; - model = "imx6q-nitrogen6_max-sgtl5000"; - ssi-controller = <&ssi1>; - audio-codec = <&codec>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - mux-int-port = <1>; - mux-ext-port = <3>; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can1>; - xceiver-supply = <®_can_xcvr>; - status = "okay"; -}; - -&clks { - assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, - <&clks IMX6QDL_CLK_LDB_DI1_SEL>; - assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, - <&clks IMX6QDL_CLK_PLL3_USB_OTG>; -}; - -&ecspi1 { - cs-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - status = "okay"; - - flash: m25p80@0 { - compatible = "microchip,sst25vf016b"; - spi-max-frequency = <20000000>; - reg = <0>; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii"; - phy-reset-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>; - txen-skew-ps = <0>; - txc-skew-ps = <3000>; - rxdv-skew-ps = <0>; - rxc-skew-ps = <3000>; - rxd0-skew-ps = <0>; - rxd1-skew-ps = <0>; - rxd2-skew-ps = <0>; - rxd3-skew-ps = <0>; - txd0-skew-ps = <0>; - txd1-skew-ps = <0>; - txd2-skew-ps = <0>; - txd3-skew-ps = <0>; - interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, - <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; - fsl,err006687-workaround-present; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c2>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - codec: sgtl5000@a { - compatible = "fsl,sgtl5000"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sgtl5000>; - reg = <0x0a>; - clocks = <&clks IMX6QDL_CLK_CKO>; - VDDA-supply = <®_2p5v>; - VDDIO-supply = <®_3p3v>; - }; - - rtc: rtc@68 { - compatible = "microcrystal,rv4162"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rv4162>; - reg = <0x68>; - interrupts-extended = <&gpio4 6 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - touchscreen@4 { - compatible = "eeti,egalax_ts"; - reg = <0x04>; - interrupt-parent = <&gpio1>; - interrupts = <9 IRQ_TYPE_EDGE_FALLING>; - wakeup-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; - }; - - touchscreen@38 { - compatible = "edt,edt-ft5x06"; - reg = <0x38>; - interrupt-parent = <&gpio1>; - interrupts = <9 IRQ_TYPE_EDGE_FALLING>; - wakeup-source; - }; -}; - -&iomuxc { - imx6q-nitrogen6-max { - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 - MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 - MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 - MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 - >; - }; - - pinctrl_can1: can1grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0 - MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0 - >; - }; - - pinctrl_can_xcvr: can-xcvrgrp { - fsl,pins = < - /* Flexcan XCVR enable */ - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 - MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - /* Phy reset */ - MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x0f0b0 - MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 - MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 - >; - }; - - pinctrl_gpio_keys: gpio-keysgrp { - fsl,pins = < - /* Power Button */ - MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 - /* Menu Button */ - MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 - /* Home Button */ - MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 - /* Back Button */ - MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 - /* Volume Up Button */ - MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 - /* Volume Down Button */ - MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c2mux: i2c2muxgrp { - fsl,pins = < - /* ov5642 camera i2c enable */ - MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x000b0 - /* ov5640_mipi camera i2c enable */ - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x000b0 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 - MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 - >; - }; - - pinctrl_i2c3mux: i2c3muxgrp { - fsl,pins = < - /* PCIe I2C enable */ - MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x000b0 - >; - }; - - pinctrl_j15: j15grp { - fsl,pins = < - MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 - MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 - MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 - MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 - MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 - MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 - MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 - MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 - MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 - MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 - MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 - MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 - MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 - MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 - MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 - MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 - MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 - MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 - MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 - MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 - MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 - MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 - MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 - MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 - MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 - MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 - MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 - MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = < - /* PCIe reset */ - MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x000b0 - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm4: pwm4grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 - >; - }; - - pinctrl_rv4162: rv4162grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 - >; - }; - - pinctrl_sgtl5000: sgtl5000grp { - fsl,pins = < - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 - MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b0 - MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x130b1 - MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x030b1 - /* RS485 RX Enable: pull up */ - MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x1b0b1 - /* RS485 DEN: pull down */ - MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x030b1 - /* RS485/!RS232 Select: pull down (rs232) */ - MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x030b1 - /* ON: pull down */ - MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x030b1 - >; - }; - - pinctrl_usbh1: usbh1grp { - fsl,pins = < - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x0b0b0 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 - /* power enable, high active */ - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x000b0 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x100b0 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 - >; - }; - - pinctrl_usdhc4: usdhc4grp { - fsl,pins = < - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 - MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 - MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 - MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 - MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 - >; - }; - - pinctrl_wlan_vmmc: wlan-vmmcgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x100b0 - MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x000b0 - MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x000b0 - MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x000b0 - >; - }; - }; -}; - -&ipu1_di0_disp0 { - remote-endpoint = <&lcd_display_in>; -}; - -&ldb { - status = "okay"; - - lvds-channel@0 { - status = "okay"; - - port@4 { - reg = <4>; - - lvds0_out: endpoint { - remote-endpoint = <&panel_in_lvds0>; - }; - }; - }; - - lvds-channel@1 { - status = "okay"; - - port@4 { - reg = <4>; - - lvds1_out: endpoint { - remote-endpoint = <&panel_in_lvds1>; - }; - }; - }; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio6 31 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "okay"; -}; - -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm2>; - status = "okay"; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; - status = "okay"; -}; - -&pwm4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm4>; - status = "okay"; -}; - -&ssi1 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usb_h1_vbus>; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - bus-width = <4>; - non-removable; - vmmc-supply = <®_wlan_vmmc>; - cap-power-off-card; - keep-power-in-suspend; - status = "okay"; - - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@2 { - compatible = "ti,wl1271"; - reg = <2>; - interrupt-parent = <&gpio6>; - interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; - ref-clock-frequency = <38400000>; - }; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; - bus-width = <4>; - vmmc-supply = <®_3p3v>; - status = "okay"; -}; - -&usdhc4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc4>; - bus-width = <8>; - non-removable; - vmmc-supply = <®_1p8v>; - keep-power-in-suspend; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx6qdl-nitrogen6_som2.dtsi b/sys/gnu/dts/arm/imx6qdl-nitrogen6_som2.dtsi deleted file mode 100644 index ed53f07c6b7..00000000000 --- a/sys/gnu/dts/arm/imx6qdl-nitrogen6_som2.dtsi +++ /dev/null @@ -1,733 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR X11 -/* - * Copyright 2016 Boundary Devices, Inc. - */ -#include -#include - -/ { - chosen { - stdout-path = &uart2; - }; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x40000000>; - }; - - backlight_lcd: backlight-lcd { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <7>; - power-supply = <®_3p3v>; - status = "okay"; - }; - - backlight_lvds0: backlight-lvds0 { - compatible = "pwm-backlight"; - pwms = <&pwm4 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <7>; - power-supply = <®_3p3v>; - status = "okay"; - }; - - backlight_lvds1: backlight-lvds1 { - compatible = "gpio-backlight"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_backlight_lvds1>; - gpios = <&gpio2 31 GPIO_ACTIVE_HIGH>; - default-on; - status = "okay"; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_keys>; - - power { - label = "Power Button"; - gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - - menu { - label = "Menu"; - gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - home { - label = "Home"; - gpios = <&gpio2 4 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - back { - label = "Back"; - gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - volume-up { - label = "Volume Up"; - gpios = <&gpio7 13 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - volume-down { - label = "Volume Down"; - gpios = <&gpio7 1 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - lcd_display: disp0 { - compatible = "fsl,imx-parallel-display"; - #address-cells = <1>; - #size-cells = <0>; - interface-pix-fmt = "bgr666"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_j15>; - status = "okay"; - - port@0 { - reg = <0>; - - lcd_display_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - - port@1 { - reg = <1>; - - lcd_display_out: endpoint { - remote-endpoint = <&lcd_panel_in>; - }; - }; - }; - - panel-lcd { - compatible = "okaya,rs800480t-7x0gp"; - backlight = <&backlight_lcd>; - - port { - lcd_panel_in: endpoint { - remote-endpoint = <&lcd_display_out>; - }; - }; - }; - - panel-lvds0 { - compatible = "hannstar,hsd100pxn1"; - backlight = <&backlight_lvds0>; - - port { - panel_in_lvds0: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - }; - - panel-lvds1 { - compatible = "hannstar,hsd100pxn1"; - backlight = <&backlight_lvds1>; - - port { - panel_in_lvds1: endpoint { - remote-endpoint = <&lvds1_out>; - }; - }; - }; - - reg_1p8v: regulator-1v8 { - compatible = "regulator-fixed"; - regulator-name = "1P8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - reg_2p5v: regulator-2v5 { - compatible = "regulator-fixed"; - regulator-name = "2P5V"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - reg_3p3v: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_can_xcvr: regulator-can-xcvr { - compatible = "regulator-fixed"; - regulator-name = "CAN XCVR"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can_xcvr>; - gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; - }; - - reg_usb_h1_vbus: regulator-usb-h1-vbus { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh1>; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - }; - - reg_usb_otg_vbus: regulator-usb-otg-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_wlan_vmmc: regulator-wlan-vmmc { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wlan_vmmc>; - regulator-name = "reg_wlan_vmmc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio6 15 GPIO_ACTIVE_HIGH>; - startup-delay-us = <70000>; - enable-active-high; - }; - - sound { - compatible = "fsl,imx6q-nitrogen6_som2-sgtl5000", - "fsl,imx-audio-sgtl5000"; - model = "imx6q-nitrogen6_som2-sgtl5000"; - ssi-controller = <&ssi1>; - audio-codec = <&codec>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - mux-int-port = <1>; - mux-ext-port = <3>; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can1>; - xceiver-supply = <®_can_xcvr>; - status = "okay"; -}; - -&clks { - assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, - <&clks IMX6QDL_CLK_LDB_DI1_SEL>; - assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, - <&clks IMX6QDL_CLK_PLL3_USB_OTG>; -}; - -&ecspi1 { - cs-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - status = "okay"; - - flash: m25p80@0 { - compatible = "microchip,sst25vf016b"; - spi-max-frequency = <20000000>; - reg = <0>; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii"; - interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, - <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; - fsl,err006687-workaround-present; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c2>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - codec: sgtl5000@a { - compatible = "fsl,sgtl5000"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sgtl5000>; - reg = <0x0a>; - clocks = <&clks IMX6QDL_CLK_CKO>; - VDDA-supply = <®_2p5v>; - VDDIO-supply = <®_3p3v>; - }; - - rtc@68 { - compatible = "microcrystal,rv4162"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rv4162>; - reg = <0x68>; - interrupts-extended = <&gpio6 7 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - touchscreen@4 { - compatible = "eeti,egalax_ts"; - reg = <0x04>; - interrupt-parent = <&gpio1>; - interrupts = <9 IRQ_TYPE_EDGE_FALLING>; - wakeup-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; - }; - - touchscreen@38 { - compatible = "edt,edt-ft5x06"; - reg = <0x38>; - interrupt-parent = <&gpio1>; - interrupts = <9 IRQ_TYPE_EDGE_FALLING>; - wakeup-source; - }; -}; - -&iomuxc { - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 - MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 - MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 - MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 - >; - }; - - pinctrl_backlight_lvds1: backlight-lvds1grp { - fsl,pins = < - MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x0b0b0 - >; - }; - - pinctrl_can1: can1grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0 - MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0 - >; - }; - - pinctrl_can_xcvr: can-xcvrgrp { - fsl,pins = < - /* Flexcan XCVR enable */ - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x0b0b0 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 - MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x130b0 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x130b0 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x130b0 - MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x030b0 - MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 - MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 - >; - }; - - pinctrl_gpio_keys: gpio-keysgrp { - fsl,pins = < - /* Power Button */ - MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 - /* Menu Button */ - MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 - /* Home Button */ - MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 - /* Back Button */ - MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 - /* Volume Up Button */ - MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 - /* Volume Down Button */ - MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 - MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 - >; - }; - - pinctrl_i2c3mux: i2c3muxgrp { - fsl,pins = < - /* PCIe I2C enable */ - MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x000b0 - >; - }; - - pinctrl_j15: j15grp { - fsl,pins = < - MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 - MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 - MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 - MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 - MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 - MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 - MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 - MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 - MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 - MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 - MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 - MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 - MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 - MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 - MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 - MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 - MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 - MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 - MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 - MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 - MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 - MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 - MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 - MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 - MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 - MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 - MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 - MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = < - /* PCIe reset */ - MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x030b0 - MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x030b0 - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x030b1 - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x030b1 - >; - }; - - pinctrl_pwm4: pwm4grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x030b1 - >; - }; - - pinctrl_rv4162: rv4162grp { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0 - >; - }; - - pinctrl_sgtl5000: sgtl5000grp { - fsl,pins = < - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 - MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x130b0 - MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x130b0 - MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x130b0 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 - MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 - >; - }; - - pinctrl_usbh1: usbh1grp { - fsl,pins = < - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x030b0 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 - /* power enable, high active */ - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x030b0 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10071 - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17071 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17071 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17071 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17071 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17071 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10071 - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17071 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17071 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17071 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17071 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17071 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 - >; - }; - - pinctrl_usdhc4: usdhc4grp { - fsl,pins = < - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 - MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 - MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 - MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 - MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 - >; - }; - - pinctrl_wlan_vmmc: wlan-vmmcgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x100b0 - MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x030b0 - MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x030b0 - MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x000b0 - >; - }; -}; - -&ipu1_di0_disp0 { - remote-endpoint = <&lcd_display_in>; -}; - -&ldb { - status = "okay"; - - lvds-channel@0 { - status = "okay"; - - port@4 { - reg = <4>; - - lvds0_out: endpoint { - remote-endpoint = <&panel_in_lvds0>; - }; - }; - }; - - lvds-channel@1 { - fsl,data-mapping = "spwg"; - fsl,data-width = <18>; - status = "okay"; - - port@4 { - reg = <4>; - - lvds1_out: endpoint { - remote-endpoint = <&panel_in_lvds1>; - }; - }; - }; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio3 0 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "okay"; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; - status = "okay"; -}; - -&pwm4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm4>; - status = "okay"; -}; - -&ssi1 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - uart-has-rtscts; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usb_h1_vbus>; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - bus-width = <4>; - non-removable; - vmmc-supply = <®_wlan_vmmc>; - cap-power-off-card; - keep-power-in-suspend; - status = "okay"; - - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@2 { - compatible = "ti,wl1271"; - reg = <2>; - interrupt-parent = <&gpio6>; - interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; - ref-clock-frequency = <38400000>; - }; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; - bus-width = <4>; - vmmc-supply = <®_3p3v>; - status = "okay"; -}; - -&usdhc4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc4>; - bus-width = <8>; - non-removable; - vmmc-supply = <®_1p8v>; - keep-power-in-suspend; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx6qdl-nitrogen6x.dtsi b/sys/gnu/dts/arm/imx6qdl-nitrogen6x.dtsi deleted file mode 100644 index 8b0e432099b..00000000000 --- a/sys/gnu/dts/arm/imx6qdl-nitrogen6x.dtsi +++ /dev/null @@ -1,680 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR X11 -/* - * Copyright 2013 Boundary Devices, Inc. - * Copyright 2011 Freescale Semiconductor, Inc. - * Copyright 2011 Linaro Ltd. - */ -#include -#include - -/ { - chosen { - stdout-path = &uart2; - }; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x40000000>; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_2p5v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "2P5V"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - reg_3p3v: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_usb_otg_vbus: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 0>; - enable-active-high; - }; - - reg_can_xcvr: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "CAN XCVR"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can_xcvr>; - gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; - }; - - reg_wlan_vmmc: regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wlan_vmmc>; - regulator-name = "reg_wlan_vmmc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio6 15 GPIO_ACTIVE_HIGH>; - startup-delay-us = <70000>; - enable-active-high; - }; - - reg_usb_h1_vbus: regulator@5 { - compatible = "regulator-fixed"; - reg = <5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh1>; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_keys>; - - power { - label = "Power Button"; - gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - - menu { - label = "Menu"; - gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - home { - label = "Home"; - gpios = <&gpio2 4 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - back { - label = "Back"; - gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - volume-up { - label = "Volume Up"; - gpios = <&gpio7 13 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - volume-down { - label = "Volume Down"; - gpios = <&gpio4 5 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - sound { - compatible = "fsl,imx6q-nitrogen6x-sgtl5000", - "fsl,imx-audio-sgtl5000"; - model = "imx6q-nitrogen6x-sgtl5000"; - ssi-controller = <&ssi1>; - audio-codec = <&codec>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - mux-int-port = <1>; - mux-ext-port = <3>; - }; - - backlight_lcd: backlight-lcd { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <7>; - power-supply = <®_3p3v>; - status = "okay"; - }; - - backlight_lvds: backlight-lvds { - compatible = "pwm-backlight"; - pwms = <&pwm4 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <7>; - power-supply = <®_3p3v>; - status = "okay"; - }; - - lcd_display: disp0 { - compatible = "fsl,imx-parallel-display"; - #address-cells = <1>; - #size-cells = <0>; - interface-pix-fmt = "bgr666"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_j15>; - status = "okay"; - - port@0 { - reg = <0>; - - lcd_display_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - - port@1 { - reg = <1>; - - lcd_display_out: endpoint { - remote-endpoint = <&lcd_panel_in>; - }; - }; - }; - - panel-lcd { - compatible = "okaya,rs800480t-7x0gp"; - backlight = <&backlight_lcd>; - - port { - lcd_panel_in: endpoint { - remote-endpoint = <&lcd_display_out>; - }; - }; - }; - - panel-lvds0 { - compatible = "hannstar,hsd100pxn1"; - backlight = <&backlight_lvds>; - - port { - panel_in: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can1>; - xceiver-supply = <®_can_xcvr>; - status = "okay"; -}; - -&clks { - assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, - <&clks IMX6QDL_CLK_LDB_DI1_SEL>; - assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, - <&clks IMX6QDL_CLK_PLL3_USB_OTG>; -}; - -&ecspi1 { - cs-gpios = <&gpio3 19 0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - status = "okay"; - - flash: m25p80@0 { - compatible = "sst,sst25vf016b", "jedec,spi-nor"; - spi-max-frequency = <20000000>; - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "bootloader"; - reg = <0x0 0xc0000>; - }; - - partition@c0000 { - label = "env"; - reg = <0xc0000 0x2000>; - }; - - partition@c2000 { - label = "splash"; - reg = <0xc2000 0x13e000>; - }; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii"; - phy-reset-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>; - txen-skew-ps = <0>; - txc-skew-ps = <3000>; - rxdv-skew-ps = <0>; - rxc-skew-ps = <3000>; - rxd0-skew-ps = <0>; - rxd1-skew-ps = <0>; - rxd2-skew-ps = <0>; - rxd3-skew-ps = <0>; - txd0-skew-ps = <0>; - txd1-skew-ps = <0>; - txd2-skew-ps = <0>; - txd3-skew-ps = <0>; - interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, - <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; - fsl,err006687-workaround-present; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c2>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - codec: sgtl5000@a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - clocks = <&clks IMX6QDL_CLK_CKO>; - VDDA-supply = <®_2p5v>; - VDDIO-supply = <®_3p3v>; - }; - - rtc: rtc@6f { - compatible = "isil,isl1208"; - reg = <0x6f>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - touchscreen@4 { - compatible = "eeti,egalax_ts"; - reg = <0x04>; - interrupt-parent = <&gpio1>; - interrupts = <9 IRQ_TYPE_EDGE_FALLING>; - wakeup-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; - }; - - touchscreen@38 { - compatible = "edt,edt-ft5x06"; - reg = <0x38>; - interrupt-parent = <&gpio1>; - interrupts = <9 IRQ_TYPE_EDGE_FALLING>; - wakeup-source; - }; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - imx6q-nitrogen6x { - pinctrl_hog: hoggrp { - fsl,pins = < - /* SGTL5000 sys_mclk */ - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x030b0 - MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 - >; - }; - - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 - MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 - MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 - MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 - >; - }; - - pinctrl_can1: can1grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0 - MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0 - >; - }; - - pinctrl_can_xcvr: can-xcvrgrp { - fsl,pins = < - /* Flexcan XCVR enable */ - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 - MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 /* CS */ - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - /* Phy reset */ - MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x000b0 - MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 - >; - }; - - pinctrl_gpio_keys: gpio-keysgrp { - fsl,pins = < - /* Power Button */ - MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 - /* Menu Button */ - MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 - /* Home Button */ - MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 - /* Back Button */ - MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 - /* Volume Up Button */ - MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 - /* Volume Down Button */ - MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_j15: j15grp { - fsl,pins = < - MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 - MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 - MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 - MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 - MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 - MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 - MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 - MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 - MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 - MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 - MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 - MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 - MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 - MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 - MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 - MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 - MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 - MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 - MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 - MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 - MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 - MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 - MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 - MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 - MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 - MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 - MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 - MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm4: pwm4grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbh1: usbh1grp { - fsl,pins = < - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x030b0 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 - /* power enable, high active */ - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x000b0 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17071 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10071 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17071 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17071 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17071 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17071 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* CD */ - >; - }; - - pinctrl_usdhc4: usdhc4grp { - fsl,pins = < - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 - MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0 /* CD */ - >; - }; - - pinctrl_wlan_vmmc: wlan-vmmcgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x100b0 - MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x000b0 - MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x000b0 - MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x000b0 - >; - }; - }; -}; - -&ipu1_di0_disp0 { - remote-endpoint = <&lcd_display_in>; -}; - -&ldb { - status = "okay"; - - lvds-channel@0 { - status = "okay"; - - port@4 { - reg = <4>; - - lvds0_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; -}; - -&pcie { - status = "okay"; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "okay"; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; - status = "okay"; -}; - -&pwm4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm4>; - status = "okay"; -}; - -&ssi1 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usb_h1_vbus>; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - bus-width = <4>; - non-removable; - vmmc-supply = <®_wlan_vmmc>; - cap-power-off-card; - keep-power-in-suspend; - status = "okay"; - - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@2 { - compatible = "ti,wl1271"; - reg = <2>; - interrupt-parent = <&gpio6>; - interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; - ref-clock-frequency = <38400000>; - }; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_3p3v>; - status = "okay"; -}; - -&usdhc4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc4>; - cd-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_3p3v>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx6qdl-phytec-mira.dtsi b/sys/gnu/dts/arm/imx6qdl-phytec-mira.dtsi deleted file mode 100644 index 9ebd438dce7..00000000000 --- a/sys/gnu/dts/arm/imx6qdl-phytec-mira.dtsi +++ /dev/null @@ -1,390 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2018 PHYTEC Messtechnik GmbH - * Author: Christian Hemp - */ - - -/ { - aliases { - rtc0 = &i2c_rtc; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <7>; - power-supply = <®_backlight>; - pwms = <&pwm1 0 5000000>; - status = "okay"; - }; - - gpio_leds: leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpioleds>; - status = "disabled"; - - red { - label = "phyboard-mira:red"; - gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>; - }; - - green { - label = "phyboard-mira:green"; - gpios = <&gpio5 23 GPIO_ACTIVE_HIGH>; - }; - - blue { - label = "phyboard-mira:blue"; - gpios = <&gpio5 24 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc0"; - }; - }; - - reg_backlight: regulator-backlight { - compatible = "regulator-fixed"; - regulator-name = "backlight_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_en_switch: regulator-en-switch { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_en_switch>; - regulator-name = "Enable Switch"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpio = <&gpio3 4 GPIO_ACTIVE_HIGH>; - regulator-always-on; - }; - - reg_flexcan1: regulator-flexcan1 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1_en>; - regulator-name = "flexcan1-reg"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_panel: regulator-panel { - compatible = "regulator-fixed"; - regulator-name = "panel-power-supply"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-always-on; - }; - - reg_pcie: regulator-pcie { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie_reg>; - regulator-name = "mPCIe_1V5"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - gpio = <&gpio3 0 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usb_h1_vbus: usb-h1-vbus { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh1_vbus>; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio2 18 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usbotg_vbus: usbotg-vbus { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg_vbus>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - panel { - compatible = "auo,g104sn02"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_panel_en>; - power-supply = <®_panel>; - enable-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; - backlight = <&backlight>; - - port { - panel_in: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - }; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - xceiver-supply = <®_flexcan1>; - status = "disabled"; -}; - -&hdmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hdmicec>; - ddc-i2c-bus = <&i2c2>; - status = "disabled"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - clock-frequency = <400000>; - status = "disabled"; - - stmpe: touchctrl@44 { - compatible = "st,stmpe811"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_stmpe>; - reg = <0x44>; - interrupt-parent = <&gpio7>; - interrupts = <12 IRQ_TYPE_NONE>; - status = "disabled"; - - stmpe_touchscreen { - compatible = "st,stmpe-ts"; - st,sample-time = <4>; - st,mod-12b = <1>; - st,ref-sel = <0>; - st,adc-freq = <1>; - st,ave-ctrl = <1>; - st,touch-det-delay = <2>; - st,settling = <2>; - st,fraction-z = <7>; - st,i-drive = <1>; - }; - }; - - i2c_rtc: rtc@68 { - compatible = "microcrystal,rv4162"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rtc_int>; - reg = <0x68>; - interrupt-parent = <&gpio7>; - interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - clock-frequency = <100000>; - status = "disabled"; -}; - -&ldb { - status = "okay"; - - lvds-channel@0 { - fsl,data-mapping = "spwg"; - fsl,data-width = <24>; - status = "disabled"; - - port@4 { - reg = <4>; - - lvds0_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio2 25 GPIO_ACTIVE_LOW>; - vpcie-supply = <®_pcie>; - status = "disabled"; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - uart-has-rtscts; - status = "disabled"; -}; - -&usbh1 { - vbus-supply = <®_usb_h1_vbus>; - disable-over-current; - status = "disabled"; -}; - -&usbotg { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - vbus-supply = <®_usbotg_vbus>; - disable-over-current; - status = "disabled"; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - cd-gpios = <&gpio6 31 GPIO_ACTIVE_LOW>; - no-1-8-v; - status = "disabled"; -}; - -&iomuxc { - pinctrl_panel_en: panelen1grp { - fsl,pins = < - MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0xb0b1 - >; - }; - - pinctrl_en_switch: enswitchgrp { - fsl,pins = < - MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0xb0b1 - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0 - MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0 - >; - }; - - pinctrl_flexcan1_en: flexcan1engrp { - fsl,pins = < - MX6QDL_PAD_EIM_A18__GPIO2_IO20 0xb0b1 - >; - }; - - pinctrl_gpioleds: gpioledsgrp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT4__GPIO5_IO22 0x1b0b0 - MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x1b0b0 - MX6QDL_PAD_CSI0_DAT6__GPIO5_IO24 0x1b0b0 - >; - }; - - pinctrl_hdmicec: hdmicecgrp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = < - MX6QDL_PAD_EIM_OE__GPIO2_IO25 0xb0b1 - >; - }; - - pinctrl_pcie_reg: pciereggrp { - fsl,pins = < - MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0xb0b1 - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1 - >; - }; - - pinctrl_rtc_int: rtcintgrp { - fsl,pins = < - MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x1b0b0 - >; - }; - - pinctrl_stmpe: stmpegrp { - fsl,pins = < - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6QDL_PAD_EIM_EB3__UART3_CTS_B 0x1b0b1 - MX6QDL_PAD_EIM_D23__UART3_RTS_B 0x1b0b1 - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbh1_vbus: usbh1vbusgrp { - fsl,pins = < - MX6QDL_PAD_EIM_A20__GPIO2_IO18 0xb0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - >; - }; - - pinctrl_usbotg_vbus: usbotgvbusgrp { - fsl,pins = < - MX6QDL_PAD_EIM_A19__GPIO2_IO19 0xb0b1 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f9 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f9 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f9 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f9 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f9 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f9 - MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0xb0b1 /* CD */ - >; - }; -}; diff --git a/sys/gnu/dts/arm/imx6qdl-phytec-pbab01.dtsi b/sys/gnu/dts/arm/imx6qdl-phytec-pbab01.dtsi deleted file mode 100644 index d434868e870..00000000000 --- a/sys/gnu/dts/arm/imx6qdl-phytec-pbab01.dtsi +++ /dev/null @@ -1,175 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH - */ - -#include - -/ { - chosen { - stdout-path = &uart4; - }; - - regulators { - sound_1v8: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "i2s-audio-1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - sound_3v3: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "i2s-audio-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - }; - - tlv320_mclk: oscillator { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <19200000>; - clock-output-names = "tlv320-mclk"; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "OnboardTLV320AIC3007"; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&dailink_master>; - simple-audio-card,frame-master = <&dailink_master>; - simple-audio-card,widgets = - "Microphone", "Mic Jack", - "Line", "Line In", - "Line", "Line Out", - "Speaker", "Speaker", - "Headphone", "Headphone Jack"; - simple-audio-card,routing = - "Line Out", "LLOUT", - "Line Out", "RLOUT", - "Speaker", "SPOP", - "Speaker", "SPOM", - "Headphone Jack", "HPLOUT", - "Headphone Jack", "HPROUT", - "MIC3L", "Mic Jack", - "MIC3R", "Mic Jack", - "Mic Jack", "Mic Bias", - "LINE1L", "Line In", - "LINE1R", "Line In"; - - simple-audio-card,cpu { - sound-dai = <&ssi2>; - }; - - dailink_master: simple-audio-card,codec { - sound-dai = <&codec>; - clocks = <&tlv320_mclk>; - }; - }; - -}; - -&audmux { - status = "okay"; - - ssi2 { - fsl,audmux-port = <1>; - fsl,port-config = < - (IMX_AUDMUX_V2_PTCR_TFSDIR | - IMX_AUDMUX_V2_PTCR_TFSEL(4) | - IMX_AUDMUX_V2_PTCR_TCLKDIR | - IMX_AUDMUX_V2_PTCR_TCSEL(4)) - IMX_AUDMUX_V2_PDCR_RXDSEL(4) - >; - }; - - pins5 { - fsl,audmux-port = <4>; - fsl,port-config = < - 0x00000000 - IMX_AUDMUX_V2_PDCR_RXDSEL(1) - >; - }; -}; - -&can1 { - status = "okay"; -}; - -&fec { - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&i2c2 { - status = "okay"; - - codec: tlv320@18 { - compatible = "ti,tlv320aic3007"; - #sound-dai-cells = <0>; - reg = <0x18>; - ai3x-micbias-vg = <2>; - - AVDD-supply = <&sound_3v3>; - IOVDD-supply = <&sound_3v3>; - DRVDD-supply = <&sound_3v3>; - DVDD-supply = <&sound_1v8>; - }; - - stmpe@41 { - compatible = "st,stmpe811"; - reg = <0x41>; - }; - - rtc@51 { - compatible = "epson,rtc8564"; - reg = <0x51>; - }; - - adc@64 { - compatible = "maxim,max1037"; - reg = <0x64>; - }; -}; - -&i2c3 { - status = "okay"; -}; - -&pcie { - status = "okay"; -}; - -&ssi2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&uart4 { - status = "okay"; -}; - -&usbh1 { - status = "okay"; -}; - -&usbotg { - status = "okay"; -}; - -&usdhc2 { - status = "okay"; -}; - -&usdhc3 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx6qdl-phytec-pfla02.dtsi b/sys/gnu/dts/arm/imx6qdl-phytec-pfla02.dtsi deleted file mode 100644 index bc43c75f174..00000000000 --- a/sys/gnu/dts/arm/imx6qdl-phytec-pfla02.dtsi +++ /dev/null @@ -1,445 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH - */ - -#include - -/ { - model = "Phytec phyFLEX-i.MX6 Quad"; - compatible = "phytec,imx6q-pfla02", "fsl,imx6q"; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x80000000>; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_usb_otg_vbus: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio4 15 0>; - enable-active-high; - }; - - reg_usb_h1_vbus: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 0 0>; - enable-active-high; - }; - }; - - gpio_leds: leds { - compatible = "gpio-leds"; - - green { - label = "phyflex:green"; - gpios = <&gpio1 30 0>; - }; - - red { - label = "phyflex:red"; - gpios = <&gpio2 31 0>; - }; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "disabled"; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - status = "disabled"; -}; - -&ecspi3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi3>; - status = "okay"; - cs-gpios = <&gpio4 24 0>; - - som_flash: flash@0 { - compatible = "m25p80", "jedec,spi-nor"; - spi-max-frequency = <20000000>; - reg = <0>; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-handle = <ðphy>; - phy-mode = "rgmii"; - phy-reset-duration = <10>; /* in msecs */ - phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; - phy-supply = <&vdd_eth_io_reg>; - status = "disabled"; - - fec_mdio: mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - txc-skew-ps = <1680>; - rxc-skew-ps = <1860>; - }; - }; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - nand-on-flash-bbt; - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - som_eeprom: eeprom@50 { - compatible = "atmel,24c32"; - reg = <0x50>; - }; - - pmic@58 { - compatible = "dlg,da9063"; - reg = <0x58>; - interrupt-parent = <&gpio2>; - interrupts = <9 IRQ_TYPE_LEVEL_LOW>; /* active-low GPIO2_9 */ - interrupt-controller; - - regulators { - vddcore_reg: bcore1 { - regulator-min-microvolt = <730000>; - regulator-max-microvolt = <1380000>; - regulator-always-on; - }; - - vddsoc_reg: bcore2 { - regulator-min-microvolt = <730000>; - regulator-max-microvolt = <1380000>; - regulator-always-on; - }; - - vdd_ddr3_reg: bpro { - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - }; - - vdd_3v3_reg: bperi { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_buckmem_reg: bmem { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_eth_reg: bio { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - vdd_eth_io_reg: ldo4 { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - vdd_mx6_snvs_reg: ldo5 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - }; - - vdd_3v3_pmic_io_reg: ldo6 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_sd0_reg: ldo9 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vdd_sd1_reg: ldo10 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vdd_mx6_high_reg: ldo11 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - }; - }; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - clock-frequency = <100000>; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - clock-frequency = <100000>; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - imx6q-phytec-pfla02 { - pinctrl_hog: hoggrp { - fsl,pins = < - MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000 - MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 /* SPI NOR chipselect */ - MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x80000000 /* PMIC interrupt */ - MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* Green LED */ - MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x80000000 /* Red LED */ - >; - }; - - pinctrl_ecspi3: ecspi3grp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 - MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 - MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0 - MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0 - >; - }; - - pinctrl_gpmi_nand: gpminandgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 - MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = ; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D30__UART3_RTS_B 0x1b0b1 - MX6QDL_PAD_EIM_D31__UART3_CTS_B 0x1b0b1 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbh1: usbh1grp { - fsl,pins = < - MX6QDL_PAD_GPIO_0__USB_H1_PWR 0x80000000 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - >; - }; - - pinctrl_usdhc3_cdwp: usdhc3cdwp { - fsl,pins = < - MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000 - MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 - >; - }; - - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x130b0 - MX6QDL_PAD_DISP0_DAT17__AUD5_TXD 0x110b0 - MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x130b0 - MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0 - >; - }; - }; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio4 17 GPIO_ACTIVE_LOW>; - status = "disabled"; -}; - -®_arm { - vin-supply = <&vddcore_reg>; -}; - -®_pu { - vin-supply = <&vddsoc_reg>; -}; - -®_soc { - vin-supply = <&vddsoc_reg>; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "disabled"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "disabled"; -}; - -&usbh1 { - vbus-supply = <®_usb_h1_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh1>; - status = "disabled"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "disabled"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; - status = "disabled"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3 - &pinctrl_usdhc3_cdwp>; - cd-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; - status = "disabled"; -}; diff --git a/sys/gnu/dts/arm/imx6qdl-phytec-phycore-som.dtsi b/sys/gnu/dts/arm/imx6qdl-phytec-phycore-som.dtsi deleted file mode 100644 index 77d871340eb..00000000000 --- a/sys/gnu/dts/arm/imx6qdl-phytec-phycore-som.dtsi +++ /dev/null @@ -1,287 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2018 PHYTEC Messtechnik GmbH - * Author: Christian Hemp - */ - -#include -#include - -/ { - aliases { - rtc1 = &da9062_rtc; - rtc2 = &snvs_rtc; - }; - - /* - * Set the minimum memory size here and - * let the bootloader set the real size. - */ - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x8000000>; - }; - - gpio_leds_som: somleds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpioleds_som>; - - som-led-green { - label = "phycore:green"; - gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; -}; - -&ecspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; - status = "okay"; - - m25p80: flash@0 { - compatible = "jedec,spi-nor"; - spi-max-frequency = <20000000>; - reg = <0>; - status = "disabled"; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-handle = <ðphy>; - phy-mode = "rgmii"; - phy-supply = <&vdd_eth_io>; - phy-reset-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; - status = "disabled"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy: ethernet-phy@3 { - reg = <3>; - txc-skew-ps = <1680>; - rxc-skew-ps = <1860>; - }; - }; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - nand-on-flash-bbt; - status = "disabled"; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - clock-frequency = <400000>; - status = "okay"; - - eeprom@50 { - compatible = "atmel,24c32"; - reg = <0x50>; - }; - - pmic@58 { - compatible = "dlg,da9062"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - reg = <0x58>; - interrupt-parent = <&gpio1>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - - da9062_rtc: rtc { - compatible = "dlg,da9062-rtc"; - }; - - da9062_onkey: onkey { - compatible = "dlg,da9062-onkey"; - }; - - watchdog { - compatible = "dlg,da9062-watchdog"; - }; - - regulators { - vdd_arm: buck1 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <925000>; - regulator-max-microvolt = <1380000>; - regulator-initial-mode = ; - regulator-always-on; - }; - - vdd_soc: buck2 { - regulator-name = "vdd_soc"; - regulator-min-microvolt = <1150000>; - regulator-max-microvolt = <1380000>; - regulator-initial-mode = ; - regulator-always-on; - }; - - vdd_ddr3_1p5: buck3 { - regulator-name = "vdd_ddr3"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-initial-mode = ; - regulator-always-on; - }; - - vdd_eth_1p2: buck4 { - regulator-name = "vdd_eth"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - regulator-always-on; - }; - - vdd_snvs: ldo1 { - regulator-name = "vdd_snvs"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - }; - - vdd_high: ldo2 { - regulator-name = "vdd_high"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - }; - - vdd_eth_io: ldo3 { - regulator-name = "vdd_eth_io"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - }; - - vdd_emmc_1p8: ldo4 { - regulator-name = "vdd_emmc"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - }; - }; -}; - -®_arm { - vin-supply = <&vdd_arm>; -}; - -®_pu { - vin-supply = <&vdd_soc>; -}; - -®_soc { - vin-supply = <&vdd_soc>; -}; - -&snvs_poweroff { - status = "okay"; -}; - -&usdhc4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc4>; - bus-width = <8>; - non-removable; - status = "disabled"; -}; - -&iomuxc { - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 - MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 - MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x1b0b0 - >; - }; - - pinctrl_gpioleds_som: gpioledssomgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 - >; - }; - - pinctrl_gpmi_nand: gpminandgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 - MX6QDL_PAD_NANDF_CS2__NAND_CE2_B 0xb0b1 - MX6QDL_PAD_NANDF_CS3__NAND_CE3_B 0xb0b1 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 - MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 - MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b0 - >; - }; - - pinctrl_pmic: pmicgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 - >; - }; - - pinctrl_usdhc4: usdhc4grp { - fsl,pins = < - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 - MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 - MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 - MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 - MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 - >; - }; -}; diff --git a/sys/gnu/dts/arm/imx6qdl-rex.dtsi b/sys/gnu/dts/arm/imx6qdl-rex.dtsi deleted file mode 100644 index de514eb5aa9..00000000000 --- a/sys/gnu/dts/arm/imx6qdl-rex.dtsi +++ /dev/null @@ -1,367 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright 2014 FEDEVEL, Inc. - * - * Author: Robert Nelson - */ - -#include -#include - -/ { - chosen { - stdout-path = &uart1; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_3p3v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_usbh1_vbus: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - pinctrl-names = "default"; - regulator-name = "usbh1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usb_otg_vbus: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - pinctrl-names = "default"; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_led>; - - led0: usr { - label = "usr"; - gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; - default-state = "off"; - linux,default-trigger = "heartbeat"; - }; - }; - - sound { - compatible = "fsl,imx6-rex-sgtl5000", - "fsl,imx-audio-sgtl5000"; - model = "imx6-rex-sgtl5000"; - ssi-controller = <&ssi1>; - audio-codec = <&codec>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - mux-int-port = <1>; - mux-ext-port = <3>; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; - -&ecspi2 { - cs-gpios = <&gpio5 12 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi2>; - status = "okay"; -}; - -&ecspi3 { - cs-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi3>; - status = "okay"; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii"; - phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c2>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - codec: sgtl5000@a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - clocks = <&clks IMX6QDL_CLK_CKO>; - VDDA-supply = <®_3p3v>; - VDDIO-supply = <®_3p3v>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - pca9535: gpio-expander@27 { - compatible = "nxp,pca9535"; - reg = <0x27>; - gpio-controller; - #gpio-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pca9535>; - interrupt-parent = <&gpio6>; - interrupts = <16 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - eeprom@57 { - compatible = "atmel,24c02"; - reg = <0x57>; - }; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - imx6qdl-rex { - pinctrl_hog: hoggrp { - fsl,pins = < - /* SGTL5000 sys_mclk */ - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x030b0 - >; - }; - - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 - MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 - MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 - MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 - >; - }; - - pinctrl_ecspi2: ecspi2grp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 - MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 - MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 - /* CS */ - MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x000b1 - >; - }; - - pinctrl_ecspi3: ecspi3grp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT17__ECSPI2_MISO 0x100b1 - MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI 0x100b1 - MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK 0x100b1 - /* CS */ - MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x000b1 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - /* Phy reset */ - MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x000b0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 - MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_led: ledgrp { - fsl,pins = < - /* user led */ - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 - >; - }; - - pinctrl_pca9535: pca9535grp { - fsl,pins = < - MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x17059 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbh1: usbh1grp { - fsl,pins = < - /* power enable, high active */ - MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x10b0 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0 - /* power enable, high active */ - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x10b0 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 - /* CD */ - MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 - /* WP */ - MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1f0b0 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - /* CD */ - MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0 - /* WP */ - MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1f0b0 - >; - }; - }; -}; - -&ssi1 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usbh1_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh1>; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - bus-width = <4>; - cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - bus-width = <4>; - cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx6qdl-sabreauto.dtsi b/sys/gnu/dts/arm/imx6qdl-sabreauto.dtsi deleted file mode 100644 index cf628465cd0..00000000000 --- a/sys/gnu/dts/arm/imx6qdl-sabreauto.dtsi +++ /dev/null @@ -1,861 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// -// Copyright 2012 Freescale Semiconductor, Inc. -// Copyright 2011 Linaro Ltd. - -#include -#include - -/ { - chosen { - stdout-path = &uart4; - }; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x80000000>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - user { - label = "debug"; - gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_keys>; - - home { - label = "Home"; - gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - - back { - label = "Back"; - gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - - program { - label = "Program"; - gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - - volume-up { - label = "Volume Up"; - gpios = <&gpio2 15 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - - volume-down { - label = "Volume Down"; - gpios = <&gpio5 14 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - }; - - clocks { - codec_osc: anaclk2 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24576000>; - }; - }; - - reg_audio: regulator-audio { - compatible = "regulator-fixed"; - regulator-name = "cs42888_supply"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_usb_h1_vbus: regulator-usb-h1-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&max7310_b 7 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usb_otg_vbus: regulator-usb-otg-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&max7310_c 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_can_en: regulator-can-en { - compatible = "regulator-fixed"; - regulator-name = "can-en"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&max7310_b 6 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_can_stby: regulator-can-stby { - compatible = "regulator-fixed"; - regulator-name = "can-stby"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&max7310_b 5 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <®_can_en>; - }; - - sound-cs42888 { - compatible = "fsl,imx6-sabreauto-cs42888", - "fsl,imx-audio-cs42888"; - model = "imx-cs42888"; - audio-cpu = <&esai>; - audio-asrc = <&asrc>; - audio-codec = <&codec>; - audio-routing = - "Line Out Jack", "AOUT1L", - "Line Out Jack", "AOUT1R", - "Line Out Jack", "AOUT2L", - "Line Out Jack", "AOUT2R", - "Line Out Jack", "AOUT3L", - "Line Out Jack", "AOUT3R", - "Line Out Jack", "AOUT4L", - "Line Out Jack", "AOUT4R", - "AIN1L", "Line In Jack", - "AIN1R", "Line In Jack", - "AIN2L", "Line In Jack", - "AIN2R", "Line In Jack"; - }; - - sound-spdif { - compatible = "fsl,imx-audio-spdif", - "fsl,imx-sabreauto-spdif"; - model = "imx-spdif"; - spdif-controller = <&spdif>; - spdif-in; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm3 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <7>; - status = "okay"; - }; - - i2cmux { - compatible = "i2c-mux-gpio"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3mux>; - mux-gpios = <&gpio5 4 0>; - i2c-parent = <&i2c3>; - idle-state = <0>; - - i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - adv7180: camera@21 { - compatible = "adi,adv7180"; - reg = <0x21>; - powerdown-gpios = <&max7310_b 2 GPIO_ACTIVE_LOW>; - interrupt-parent = <&gpio1>; - interrupts = <27 IRQ_TYPE_LEVEL_LOW>; - - port { - adv7180_to_ipu1_csi0_mux: endpoint { - remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; - bus-width = <8>; - }; - }; - }; - - max7310_a: gpio@30 { - compatible = "maxim,max7310"; - reg = <0x30>; - gpio-controller; - #gpio-cells = <2>; - }; - - max7310_b: gpio@32 { - compatible = "maxim,max7310"; - reg = <0x32>; - gpio-controller; - #gpio-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_max7310>; - reset-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; - }; - - max7310_c: gpio@34 { - compatible = "maxim,max7310"; - reg = <0x34>; - gpio-controller; - #gpio-cells = <2>; - }; - - light-sensor@44 { - compatible = "isil,isl29023"; - reg = <0x44>; - interrupt-parent = <&gpio5>; - interrupts = <17 IRQ_TYPE_EDGE_FALLING>; - }; - - magnetometer@e { - compatible = "fsl,mag3110"; - reg = <0x0e>; - interrupt-parent = <&gpio2>; - interrupts = <29 IRQ_TYPE_EDGE_RISING>; - }; - - accelerometer@1c { - compatible = "fsl,mma8451"; - reg = <0x1c>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mma8451_int>; - interrupt-parent = <&gpio6>; - interrupts = <31 IRQ_TYPE_LEVEL_LOW>; - }; - }; - }; -}; - -&ipu1_csi0_from_ipu1_csi0_mux { - bus-width = <8>; -}; - -&ipu1_csi0_mux_from_parallel_sensor { - remote-endpoint = <&adv7180_to_ipu1_csi0_mux>; - bus-width = <8>; -}; - -&ipu1_csi0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu1_csi0>; -}; - -&clks { - assigned-clocks = <&clks IMX6QDL_PLL4_BYPASS_SRC>, - <&clks IMX6QDL_PLL4_BYPASS>, - <&clks IMX6QDL_CLK_LDB_DI0_SEL>, - <&clks IMX6QDL_CLK_LDB_DI1_SEL>, - <&clks IMX6QDL_CLK_PLL4_POST_DIV>; - assigned-clock-parents = <&clks IMX6QDL_CLK_LVDS2_IN>, - <&clks IMX6QDL_PLL4_BYPASS_SRC>, - <&clks IMX6QDL_CLK_PLL3_USB_OTG>, - <&clks IMX6QDL_CLK_PLL3_USB_OTG>; - assigned-clock-rates = <0>, <0>, <0>, <0>, <24576000>; -}; - -&ecspi1 { - cs-gpios = <&gpio3 19 0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>; - status = "disabled"; /* pin conflict with WEIM NOR */ - - flash: m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,m25p32", "jedec,spi-nor"; - spi-max-frequency = <20000000>; - reg = <0>; - }; -}; - -&esai { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esai>; - assigned-clocks = <&clks IMX6QDL_CLK_ESAI_SEL>, - <&clks IMX6QDL_CLK_ESAI_EXTAL>; - assigned-clock-parents = <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>; - assigned-clock-rates = <0>, <24576000>; - status = "okay"; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii-id"; - interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, - <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; - fsl,err006687-workaround-present; - status = "okay"; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - xceiver-supply = <®_can_stby>; - status = "disabled"; /* pin conflict with fec */ -}; - -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - xceiver-supply = <®_can_stby>; - status = "okay"; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - status = "okay"; -}; - -&hdmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hdmi_cec>; - ddc-i2c-bus = <&i2c2>; - status = "okay"; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - pmic: pfuze100@8 { - compatible = "fsl,pfuze100"; - reg = <0x08>; - - regulators { - sw1a_reg: sw1ab { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw1c_reg: sw1c { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3a_reg: sw3a { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3b_reg: sw3b { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - sw4_reg: sw4 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - }; - - swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - }; - - snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - vgen1_reg: vgen1 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen2_reg: vgen2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen3_reg: vgen3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - vgen4_reg: vgen4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen5_reg: vgen5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen6_reg: vgen6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; - - codec: cs42888@48 { - compatible = "cirrus,cs42888"; - reg = <0x48>; - clocks = <&codec_osc>; - clock-names = "mclk"; - VA-supply = <®_audio>; - VD-supply = <®_audio>; - VLS-supply = <®_audio>; - VLC-supply = <®_audio>; - }; - - touchscreen@4 { - compatible = "eeti,egalax_ts"; - reg = <0x04>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_egalax_int>; - interrupt-parent = <&gpio2>; - interrupts = <28 IRQ_TYPE_EDGE_FALLING>; - wakeup-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>; - }; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - imx6qdl-sabreauto { - pinctrl_hog: hoggrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000 - MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x80000000 - MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x17059 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 - >; - }; - - pinctrl_ecspi1_cs: ecspi1cs { - fsl,pins = < - MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000 - >; - }; - - pinctrl_egalax_int: egalax-intgrp { - fsl,pins = < - MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0xb0b1 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 - >; - }; - - pinctrl_esai: esaigrp { - fsl,pins = < - MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030 - MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b030 - MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030 - MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3 0x1b030 - MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b030 - MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b030 - MX6QDL_PAD_GPIO_17__ESAI_TX0 0x1b030 - MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b030 - MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1b030 - MX6QDL_PAD_GPIO_9__ESAI_RX_FS 0x1b030 - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x17059 - MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x17059 - >; - }; - - pinctrl_flexcan2: flexcan2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x17059 - MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x17059 - >; - }; - - pinctrl_gpio_keys: gpiokeysgrp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x1b0b0 - MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x1b0b0 - MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x1b0b0 - MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x1b0b0 - MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0 - >; - }; - - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x80000000 - >; - }; - - pinctrl_gpmi_nand: gpminandgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 - MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 - >; - }; - - pinctrl_hdmi_cec: hdmicecgrp { - fsl,pins = < - MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3mux: i2c3muxgrp { - fsl,pins = < - MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x0b0b1 - >; - }; - - pinctrl_ipu1_csi0: ipu1csi0grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 - MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 - MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 - MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 - MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 - MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 - MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 - MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 - MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 - MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0 - MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0 - >; - }; - - pinctrl_max7310: max7310grp { - fsl,pins = < - MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x1b0b0 - >; - }; - - pinctrl_mma8451_int: mma8451intgrp { - fsl,pins = < - MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0xb0b1 - >; - }; - - pinctrl_pwm3: pwm1grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 - >; - }; - - pinctrl_gpt_input_capture0: gptinputcapture0grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT0__GPT_CAPTURE1 0x1b0b0 - >; - }; - - pinctrl_gpt_input_capture1: gptinputcapture1grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT1__GPT_CAPTURE2 0x1b0b0 - >; - }; - - pinctrl_spdif: spdifgrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3grp100mhz { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3grp200mhz { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9 - >; - }; - - pinctrl_weim_cs0: weimcs0grp { - fsl,pins = < - MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1 - >; - }; - - pinctrl_weim_nor: weimnorgrp { - fsl,pins = < - MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1 - MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1 - MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060 - MX6QDL_PAD_EIM_D16__EIM_DATA16 0x1b0b0 - MX6QDL_PAD_EIM_D17__EIM_DATA17 0x1b0b0 - MX6QDL_PAD_EIM_D18__EIM_DATA18 0x1b0b0 - MX6QDL_PAD_EIM_D19__EIM_DATA19 0x1b0b0 - MX6QDL_PAD_EIM_D20__EIM_DATA20 0x1b0b0 - MX6QDL_PAD_EIM_D21__EIM_DATA21 0x1b0b0 - MX6QDL_PAD_EIM_D22__EIM_DATA22 0x1b0b0 - MX6QDL_PAD_EIM_D23__EIM_DATA23 0x1b0b0 - MX6QDL_PAD_EIM_D24__EIM_DATA24 0x1b0b0 - MX6QDL_PAD_EIM_D25__EIM_DATA25 0x1b0b0 - MX6QDL_PAD_EIM_D26__EIM_DATA26 0x1b0b0 - MX6QDL_PAD_EIM_D27__EIM_DATA27 0x1b0b0 - MX6QDL_PAD_EIM_D28__EIM_DATA28 0x1b0b0 - MX6QDL_PAD_EIM_D29__EIM_DATA29 0x1b0b0 - MX6QDL_PAD_EIM_D30__EIM_DATA30 0x1b0b0 - MX6QDL_PAD_EIM_D31__EIM_DATA31 0x1b0b0 - MX6QDL_PAD_EIM_A23__EIM_ADDR23 0xb0b1 - MX6QDL_PAD_EIM_A22__EIM_ADDR22 0xb0b1 - MX6QDL_PAD_EIM_A21__EIM_ADDR21 0xb0b1 - MX6QDL_PAD_EIM_A20__EIM_ADDR20 0xb0b1 - MX6QDL_PAD_EIM_A19__EIM_ADDR19 0xb0b1 - MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0b1 - MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0b1 - MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0b1 - MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1 - MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1 - MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1 - MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1 - MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1 - MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1 - MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1 - MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1 - MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1 - MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1 - MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1 - MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1 - MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1 - MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1 - MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1 - MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1 - >; - }; - }; -}; - -&ldb { - status = "okay"; - - lvds-channel@0 { - fsl,data-mapping = "spwg"; - fsl,data-width = <18>; - status = "okay"; - - display-timings { - native-mode = <&timing0>; - timing0: hsd100pxn1 { - clock-frequency = <65000000>; - hactive = <1024>; - vactive = <768>; - hback-porch = <220>; - hfront-porch = <40>; - vback-porch = <21>; - vfront-porch = <7>; - hsync-len = <60>; - vsync-len = <10>; - }; - }; - }; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; - status = "okay"; -}; - -&pcie { - status = "okay"; -}; - -&spdif { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spdif>; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usb_h1_vbus>; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - cd-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&weim { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_weim_nor &pinctrl_weim_cs0>; - ranges = <0 0 0x08000000 0x08000000>; - status = "disabled"; /* pin conflict with SPI NOR */ - - nor@0,0 { - compatible = "cfi-flash"; - reg = <0 0 0x02000000>; - #address-cells = <1>; - #size-cells = <1>; - bank-width = <2>; - fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000 - 0x0000c000 0x1404a38e 0x00000000>; - }; -}; diff --git a/sys/gnu/dts/arm/imx6qdl-sabrelite.dtsi b/sys/gnu/dts/arm/imx6qdl-sabrelite.dtsi deleted file mode 100644 index 8468216dae9..00000000000 --- a/sys/gnu/dts/arm/imx6qdl-sabrelite.dtsi +++ /dev/null @@ -1,765 +0,0 @@ -/* - * Copyright 2011 Freescale Semiconductor, Inc. - * Copyright 2011 Linaro Ltd. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include -#include -#include - -/ { - chosen { - stdout-path = &uart2; - }; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x40000000>; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_2p5v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "2P5V"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - reg_3p3v: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_usb_otg_vbus: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 0>; - enable-active-high; - }; - - reg_can_xcvr: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "CAN XCVR"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can_xcvr>; - gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; - }; - - reg_1p5v: regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "1P5V"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - }; - - reg_1p8v: regulator@5 { - compatible = "regulator-fixed"; - reg = <5>; - regulator-name = "1P8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - reg_2p8v: regulator@6 { - compatible = "regulator-fixed"; - reg = <6>; - regulator-name = "2P8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - reg_usb_h1_vbus: regulator@7 { - compatible = "regulator-fixed"; - reg = <7>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh1>; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - }; - - mipi_xclk: mipi_xclk { - compatible = "pwm-clock"; - #clock-cells = <0>; - clock-frequency = <22000000>; - clock-output-names = "mipi_pwm3"; - pwms = <&pwm3 0 45>; /* 1 / 45 ns = 22 MHz */ - status = "okay"; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_keys>; - - power { - label = "Power Button"; - gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - - menu { - label = "Menu"; - gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - home { - label = "Home"; - gpios = <&gpio2 4 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - back { - label = "Back"; - gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - volume-up { - label = "Volume Up"; - gpios = <&gpio7 13 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - volume-down { - label = "Volume Down"; - gpios = <&gpio4 5 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - sound { - compatible = "fsl,imx6q-sabrelite-sgtl5000", - "fsl,imx-audio-sgtl5000"; - model = "imx6q-sabrelite-sgtl5000"; - ssi-controller = <&ssi1>; - audio-codec = <&codec>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - mux-int-port = <1>; - mux-ext-port = <4>; - }; - - backlight_lcd: backlight-lcd { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <7>; - power-supply = <®_3p3v>; - status = "okay"; - }; - - backlight_lvds: backlight-lvds { - compatible = "pwm-backlight"; - pwms = <&pwm4 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <7>; - power-supply = <®_3p3v>; - status = "okay"; - }; - - lcd_display: disp0 { - compatible = "fsl,imx-parallel-display"; - #address-cells = <1>; - #size-cells = <0>; - interface-pix-fmt = "bgr666"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_j15>; - status = "okay"; - - port@0 { - reg = <0>; - - lcd_display_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - - port@1 { - reg = <1>; - - lcd_display_out: endpoint { - remote-endpoint = <&lcd_panel_in>; - }; - }; - }; - - panel-lcd { - compatible = "okaya,rs800480t-7x0gp"; - backlight = <&backlight_lcd>; - - port { - lcd_panel_in: endpoint { - remote-endpoint = <&lcd_display_out>; - }; - }; - }; - - panel-lvds0 { - compatible = "hannstar,hsd100pxn1"; - backlight = <&backlight_lvds>; - - port { - panel_in: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - }; -}; - -&ipu1_csi0_from_ipu1_csi0_mux { - bus-width = <8>; - data-shift = <12>; /* Lines 19:12 used */ - hsync-active = <1>; - vync-active = <1>; -}; - -&ipu1_csi0_mux_from_parallel_sensor { - remote-endpoint = <&ov5642_to_ipu1_csi0_mux>; -}; - -&ipu1_csi0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu1_csi0>; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can1>; - xceiver-supply = <®_can_xcvr>; - status = "okay"; -}; - -&clks { - assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, - <&clks IMX6QDL_CLK_LDB_DI1_SEL>; - assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, - <&clks IMX6QDL_CLK_PLL3_USB_OTG>; -}; - -&ecspi1 { - cs-gpios = <&gpio3 19 0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - status = "okay"; - - flash: m25p80@0 { - compatible = "sst,sst25vf016b", "jedec,spi-nor"; - spi-max-frequency = <20000000>; - reg = <0>; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii"; - phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; - txen-skew-ps = <0>; - txc-skew-ps = <3000>; - rxdv-skew-ps = <0>; - rxc-skew-ps = <3000>; - rxd0-skew-ps = <0>; - rxd1-skew-ps = <0>; - rxd2-skew-ps = <0>; - rxd3-skew-ps = <0>; - txd0-skew-ps = <0>; - txd1-skew-ps = <0>; - txd2-skew-ps = <0>; - txd3-skew-ps = <0>; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c2>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - codec: sgtl5000@a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - clocks = <&clks IMX6QDL_CLK_CKO>; - VDDA-supply = <®_2p5v>; - VDDIO-supply = <®_3p3v>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - ov5640: camera@40 { - compatible = "ovti,ov5640"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ov5640>; - reg = <0x40>; - clocks = <&mipi_xclk>; - clock-names = "xclk"; - DOVDD-supply = <®_1p8v>; - AVDD-supply = <®_2p8v>; - DVDD-supply = <®_1p5v>; - reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; /* NANDF_D5 */ - powerdown-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; /* NANDF_WP_B */ - - port { - ov5640_to_mipi_csi2: endpoint { - remote-endpoint = <&mipi_csi2_in>; - clock-lanes = <0>; - data-lanes = <1 2>; - }; - }; - }; - - ov5642: camera@42 { - compatible = "ovti,ov5642"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ov5642>; - clocks = <&clks IMX6QDL_CLK_CKO2>; - clock-names = "xclk"; - reg = <0x42>; - reset-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; - powerdown-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; - gp-gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>; - status = "disabled"; - - port { - ov5642_to_ipu1_csi0_mux: endpoint { - remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; - bus-width = <8>; - hsync-active = <1>; - vsync-active = <1>; - }; - }; - }; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - imx6q-sabrelite { - pinctrl_hog: hoggrp { - fsl,pins = < - /* SGTL5000 sys_mclk */ - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x030b0 - >; - }; - - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 - MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 - MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 - MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 - >; - }; - - pinctrl_can1: can1grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0 - MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0 - >; - }; - - pinctrl_can_xcvr: can-xcvrgrp { - fsl,pins = < - /* Flexcan XCVR enable */ - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 - MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 /* CS */ - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - /* Phy reset */ - MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x000b0 - >; - }; - - pinctrl_gpio_keys: gpio-keysgrp { - fsl,pins = < - /* Power Button */ - MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 - /* Menu Button */ - MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 - /* Home Button */ - MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 - /* Back Button */ - MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 - /* Volume Up Button */ - MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 - /* Volume Down Button */ - MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_ipu1_csi0: ipu1csi0grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 - MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 - MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 - MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 - MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 - MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 - MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 - MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 - MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 - MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0 - MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0 - MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x1b0b0 - >; - }; - - pinctrl_j15: j15grp { - fsl,pins = < - MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 - MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 - MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 - MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 - MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 - MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 - MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 - MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 - MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 - MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 - MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 - MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 - MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 - MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 - MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 - MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 - MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 - MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 - MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 - MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 - MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 - MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 - MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 - MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 - MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 - MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 - MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 - MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 - >; - }; - - pinctrl_ov5640: ov5640grp { - fsl,pins = < - MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x000b0 - MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x0b0b0 - >; - }; - - pinctrl_ov5642: ov5642grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0 - MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0 - MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x130b0 - MX6QDL_PAD_GPIO_3__CCM_CLKO2 0x000b0 - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm4: pwm4grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbh1: usbh1grp { - fsl,pins = < - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x030b0 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 - /* power enable, high active */ - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x000b0 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* CD */ - MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0 /* WP */ - >; - }; - - pinctrl_usdhc4: usdhc4grp { - fsl,pins = < - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 - MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0 /* CD */ - >; - }; - }; -}; - -&ipu1_di0_disp0 { - remote-endpoint = <&lcd_display_in>; -}; - -&ldb { - status = "okay"; - - lvds-channel@0 { - status = "okay"; - - port@4 { - reg = <4>; - - lvds0_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; -}; - -&pcie { - status = "okay"; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "okay"; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; - status = "okay"; -}; - -&pwm4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm4>; - status = "okay"; -}; - -&ssi1 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usb_h1_vbus>; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; - vmmc-supply = <®_3p3v>; - status = "okay"; -}; - -&usdhc4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc4>; - cd-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_3p3v>; - status = "okay"; -}; - -&mipi_csi { - status = "okay"; - - port@0 { - reg = <0>; - - mipi_csi2_in: endpoint { - remote-endpoint = <&ov5640_to_mipi_csi2>; - clock-lanes = <0>; - data-lanes = <1 2>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/imx6qdl-sabresd.dtsi b/sys/gnu/dts/arm/imx6qdl-sabresd.dtsi deleted file mode 100644 index fe59dde41b6..00000000000 --- a/sys/gnu/dts/arm/imx6qdl-sabresd.dtsi +++ /dev/null @@ -1,823 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// -// Copyright 2012 Freescale Semiconductor, Inc. -// Copyright 2011 Linaro Ltd. - -#include -#include -#include - -/ { - chosen { - stdout-path = &uart1; - }; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x40000000>; - }; - - reg_usb_otg_vbus: regulator-usb-otg-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&swbst_reg>; - }; - - reg_usb_h1_vbus: regulator-usb-h1-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&swbst_reg>; - }; - - reg_audio: regulator-audio { - compatible = "regulator-fixed"; - regulator-name = "wm8962-supply"; - gpio = <&gpio4 10 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_pcie: regulator-pcie { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie_reg>; - regulator-name = "MPCIE_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_sensors: regulator-sensors { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sensors_reg>; - regulator-name = "sensors-supply"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_keys>; - - power { - label = "Power Button"; - gpios = <&gpio3 29 GPIO_ACTIVE_LOW>; - wakeup-source; - linux,code = ; - }; - - volume-up { - label = "Volume Up"; - gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - wakeup-source; - linux,code = ; - }; - - volume-down { - label = "Volume Down"; - gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; - wakeup-source; - linux,code = ; - }; - }; - - sound { - compatible = "fsl,imx6q-sabresd-wm8962", - "fsl,imx-audio-wm8962"; - model = "wm8962-audio"; - ssi-controller = <&ssi2>; - audio-codec = <&codec>; - audio-routing = - "Headphone Jack", "HPOUTL", - "Headphone Jack", "HPOUTR", - "Ext Spk", "SPKOUTL", - "Ext Spk", "SPKOUTR", - "AMIC", "MICBIAS", - "IN3R", "AMIC"; - mux-int-port = <2>; - mux-ext-port = <3>; - }; - - backlight_lvds: backlight-lvds { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <7>; - status = "okay"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - red { - gpios = <&gpio1 2 0>; - default-state = "on"; - }; - }; - - panel { - compatible = "hannstar,hsd100pxn1"; - backlight = <&backlight_lvds>; - - port { - panel_in: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - }; -}; - -&ipu1_csi0_from_ipu1_csi0_mux { - bus-width = <8>; - data-shift = <12>; /* Lines 19:12 used */ - hsync-active = <1>; - vsync-active = <1>; -}; - -&ipu1_csi0_mux_from_parallel_sensor { - remote-endpoint = <&ov5642_to_ipu1_csi0_mux>; -}; - -&ipu1_csi0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu1_csi0>; -}; - -&mipi_csi { - status = "okay"; - - port@0 { - reg = <0>; - - mipi_csi2_in: endpoint { - remote-endpoint = <&ov5640_to_mipi_csi2>; - clock-lanes = <0>; - data-lanes = <1 2>; - }; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; - -&clks { - assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, - <&clks IMX6QDL_CLK_LDB_DI1_SEL>; - assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, - <&clks IMX6QDL_CLK_PLL3_USB_OTG>; -}; - -&ecspi1 { - cs-gpios = <&gpio4 9 0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - status = "okay"; - - flash: m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,m25p32", "jedec,spi-nor"; - spi-max-frequency = <20000000>; - reg = <0>; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii-id"; - phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&hdmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hdmi_cec>; - ddc-i2c-bus = <&i2c2>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - codec: wm8962@1a { - compatible = "wlf,wm8962"; - reg = <0x1a>; - clocks = <&clks IMX6QDL_CLK_CKO>; - DCVDD-supply = <®_audio>; - DBVDD-supply = <®_audio>; - AVDD-supply = <®_audio>; - CPVDD-supply = <®_audio>; - MICVDD-supply = <®_audio>; - PLLVDD-supply = <®_audio>; - SPKVDD1-supply = <®_audio>; - SPKVDD2-supply = <®_audio>; - gpio-cfg = < - 0x0000 /* 0:Default */ - 0x0000 /* 1:Default */ - 0x0013 /* 2:FN_DMICCLK */ - 0x0000 /* 3:Default */ - 0x8014 /* 4:FN_DMICCDAT */ - 0x0000 /* 5:Default */ - >; - }; - - accelerometer@1c { - compatible = "fsl,mma8451"; - reg = <0x1c>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1_mma8451_int>; - interrupt-parent = <&gpio1>; - interrupts = <18 IRQ_TYPE_LEVEL_LOW>; - vdd-supply = <®_sensors>; - vddio-supply = <®_sensors>; - }; - - ov5642: camera@3c { - compatible = "ovti,ov5642"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ov5642>; - clocks = <&clks IMX6QDL_CLK_CKO>; - clock-names = "xclk"; - reg = <0x3c>; - DOVDD-supply = <&vgen4_reg>; /* 1.8v */ - AVDD-supply = <&vgen3_reg>; /* 2.8v, rev C board is VGEN3 - rev B board is VGEN5 */ - DVDD-supply = <&vgen2_reg>; /* 1.5v*/ - powerdown-gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; - status = "disabled"; - - port { - ov5642_to_ipu1_csi0_mux: endpoint { - remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; - bus-width = <8>; - hsync-active = <1>; - vsync-active = <1>; - }; - }; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - touchscreen@4 { - compatible = "eeti,egalax_ts"; - reg = <0x04>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2_egalax_int>; - interrupt-parent = <&gpio6>; - interrupts = <8 IRQ_TYPE_EDGE_FALLING>; - wakeup-gpios = <&gpio6 8 GPIO_ACTIVE_HIGH>; - }; - - ov5640: camera@3c { - compatible = "ovti,ov5640"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ov5640>; - reg = <0x3c>; - clocks = <&clks IMX6QDL_CLK_CKO>; - clock-names = "xclk"; - DOVDD-supply = <&vgen4_reg>; /* 1.8v */ - AVDD-supply = <&vgen3_reg>; /* 2.8v, rev C board is VGEN3 - rev B board is VGEN5 */ - DVDD-supply = <&vgen2_reg>; /* 1.5v*/ - powerdown-gpios = <&gpio1 19 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; - - port { - ov5640_to_mipi_csi2: endpoint { - remote-endpoint = <&mipi_csi2_in>; - clock-lanes = <0>; - data-lanes = <1 2>; - }; - }; - }; - - pmic: pfuze100@8 { - compatible = "fsl,pfuze100"; - reg = <0x08>; - - regulators { - sw1a_reg: sw1ab { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw1c_reg: sw1c { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw3a_reg: sw3a { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3b_reg: sw3b { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - sw4_reg: sw4 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - }; - - snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - vgen1_reg: vgen1 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen2_reg: vgen2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen3_reg: vgen3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - vgen4_reg: vgen4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen5_reg: vgen5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen6_reg: vgen6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - egalax_ts@4 { - compatible = "eeti,egalax_ts"; - reg = <0x04>; - interrupt-parent = <&gpio6>; - interrupts = <7 2>; - wakeup-gpios = <&gpio6 7 0>; - }; - - magnetometer@e { - compatible = "fsl,mag3110"; - reg = <0x0e>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3_mag3110_int>; - interrupt-parent = <&gpio3>; - interrupts = <16 IRQ_TYPE_EDGE_RISING>; - vdd-supply = <®_sensors>; - vddio-supply = <®_sensors>; - }; - - light-sensor@44 { - compatible = "isil,isl29023"; - reg = <0x44>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3_isl29023_int>; - interrupt-parent = <&gpio3>; - interrupts = <9 IRQ_TYPE_EDGE_FALLING>; - vcc-supply = <®_sensors>; - }; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - imx6qdl-sabresd { - pinctrl_hog: hoggrp { - fsl,pins = < - MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0 - MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 - MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 - MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 - MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0 - MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 - MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 - >; - }; - - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 - MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 - MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 - MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1 - MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - >; - }; - - pinctrl_gpio_keys: gpio_keysgrp { - fsl,pins = < - MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0 - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 - MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0 - >; - }; - - pinctrl_hdmi_cec: hdmicecgrp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 - MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 - >; - }; - - pinctrl_i2c1_mma8451_int: i2c1mma8451intgrp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0xb0b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c2_egalax_int: i2c2egalaxintgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x1b0b0 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3_isl29023_int: i2c3isl29023intgrp { - fsl,pins = < - MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0xb0b1 - >; - }; - - pinctrl_i2c3_mag3110_int: i2c3mag3110intgrp { - fsl,pins = < - MX6QDL_PAD_EIM_D16__GPIO3_IO16 0xb0b1 - >; - }; - - pinctrl_ipu1_csi0: ipu1csi0grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 - MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 - MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 - MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 - MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 - MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 - MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 - MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 - MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 - MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0 - MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0 - >; - }; - - pinctrl_ov5640: ov5640grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x1b0b0 - MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x1b0b0 - >; - }; - - pinctrl_ov5642: ov5642grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0 - MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b0b0 - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = < - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 - >; - }; - - pinctrl_pcie_reg: pciereggrp { - fsl,pins = < - MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b0 - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 - >; - }; - - pinctrl_sensors_reg: sensorsreggrp { - fsl,pins = < - MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x1b0b0 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 - MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059 - MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059 - MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059 - MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 - >; - }; - - pinctrl_usdhc4: usdhc4grp { - fsl,pins = < - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 - MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 - MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 - MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 - MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__WDOG2_B 0x1b0b0 - >; - }; - }; - - gpio_leds { - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 - >; - }; - }; -}; - -&ldb { - status = "okay"; - - lvds-channel@1 { - fsl,data-mapping = "spwg"; - fsl,data-width = <18>; - status = "okay"; - - port@4 { - reg = <4>; - - lvds0_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>; - vpcie-supply = <®_pcie>; - status = "okay"; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "okay"; -}; - -®_arm { - vin-supply = <&sw1a_reg>; -}; - -®_pu { - vin-supply = <&sw1c_reg>; -}; - -®_soc { - vin-supply = <&sw1c_reg>; -}; - -®_vdd1p1 { - vin-supply = <&vgen5_reg>; -}; - -®_vdd2p5 { - vin-supply = <&vgen5_reg>; -}; - -&snvs_poweroff { - status = "okay"; -}; - -&snvs_pwrkey { - status = "okay"; -}; - -&ssi2 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usb_h1_vbus>; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - bus-width = <8>; - cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - bus-width = <8>; - cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&usdhc4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc4>; - bus-width = <8>; - non-removable; - no-1-8-v; - status = "okay"; -}; - -&wdog1 { - status = "disabled"; -}; - -&wdog2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx6qdl-savageboard.dtsi b/sys/gnu/dts/arm/imx6qdl-savageboard.dtsi deleted file mode 100644 index a616e3c400d..00000000000 --- a/sys/gnu/dts/arm/imx6qdl-savageboard.dtsi +++ /dev/null @@ -1,255 +0,0 @@ -/* - * Copyright (C) 2017 Milo Kim - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include -#include - -/ { - chosen { - stdout-path = &uart1; - }; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x40000000>; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_keys>; - - power { - gpios = <&gpio3 7 GPIO_ACTIVE_LOW>; - label = "Power Button"; - linux,code = ; - wakeup-source; - }; - }; - - panel { - compatible = "avic,tm097tdh02", "hannstar,hsd100pxn1"; - backlight = <&panel_bl>; - power-supply = <®_3p3v>; - - port { - panel_in: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - }; - - panel_bl: backlight { - compatible = "pwm-backlight"; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <4>; - power-supply = <®_3p3v>; - pwms = <&pwm1 0 10000>; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; -}; - -&clks { - assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, - <&clks IMX6QDL_CLK_LDB_DI1_SEL>; - assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, - <&clks IMX6QDL_CLK_PLL3_USB_OTG>; -}; - -&fec { - phy-mode = "rgmii"; - phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c2>; - status = "okay"; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&ldb { - status = "okay"; - - lvds-channel@0 { - reg = <0>; - status = "okay"; - - port@4 { - reg = <4>; - - lvds0_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&usbh1 { - status = "okay"; -}; - -/* SD card */ -&usdhc3 { - bus-width = <4>; - cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; - no-1-8-v; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sd>; - status = "okay"; -}; - -/* eMMC */ -&usdhc4 { - bus-width = <8>; - keep-power-in-suspend; - no-1-8-v; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_emmc>; - status = "okay"; -}; - -&iomuxc { - pinctrl_emmc: emmcgrp { - fsl,pins = < - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 - MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 - MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 - MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 - MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - /* PHY reset */ - MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 - >; - }; - - pinctrl_gpio_keys: gpiokeysgrp { - fsl,pins = < - MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x1b0b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 - >; - }; - - pinctrl_sd: sdgrp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - /* CD pin */ - MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b1 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 - >; - }; -}; diff --git a/sys/gnu/dts/arm/imx6qdl-sr-som-brcm.dtsi b/sys/gnu/dts/arm/imx6qdl-sr-som-brcm.dtsi deleted file mode 100644 index b55af61dfec..00000000000 --- a/sys/gnu/dts/arm/imx6qdl-sr-som-brcm.dtsi +++ /dev/null @@ -1,144 +0,0 @@ -/* - * Copyright (C) 2013,2014 Russell King - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -#include -/ { - clk_brcm: brcm-clock { - compatible = "gpio-gate-clock"; - #clock-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_microsom_brcm_osc>; - enable-gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>; - }; - - reg_brcm: brcm-reg { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio3 19 0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_microsom_brcm_reg>; - regulator-name = "brcm_reg"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <200000>; - }; - - usdhc1_pwrseq: usdhc1_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio5 26 GPIO_ACTIVE_LOW>, - <&gpio6 0 GPIO_ACTIVE_LOW>; - clocks = <&clk_brcm>; - clock-names = "ext_clock"; - }; -}; - -&iomuxc { - microsom { - pinctrl_microsom_brcm_bt: microsom-brcm-bt { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00 0x40013070 - MX6QDL_PAD_CSI0_DAT15__GPIO6_IO01 0x40013070 - MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04 0x40013070 - >; - }; - - pinctrl_microsom_brcm_osc: microsom-brcm-osc { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x40013070 - >; - }; - - pinctrl_microsom_brcm_reg: microsom-brcm-reg { - fsl,pins = < - MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x40013070 - >; - }; - - pinctrl_microsom_brcm_wifi: microsom-brcm-wifi { - fsl,pins = < - MX6QDL_PAD_GPIO_8__XTALOSC_REF_CLK_32K 0x1b0b0 - MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x40013070 - MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x40013070 - MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x40013070 - >; - }; - - pinctrl_microsom_uart4: microsom-uart4 { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1 - MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1 - >; - }; - - pinctrl_microsom_usdhc1: microsom-usdhc1 { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 - >; - }; - }; -}; - -/* UART4 - Connected to optional BRCM Wifi/BT/FM */ -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_microsom_brcm_bt &pinctrl_microsom_uart4>; - uart-has-rtscts; - status = "okay"; -}; - -/* USDHC1 - Connected to optional BRCM Wifi/BT/FM */ -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_microsom_brcm_wifi &pinctrl_microsom_usdhc1>; - bus-width = <4>; - mmc-pwrseq = <&usdhc1_pwrseq>; - keep-power-in-suspend; - no-1-8-v; - non-removable; - vmmc-supply = <®_brcm>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx6qdl-sr-som-emmc.dtsi b/sys/gnu/dts/arm/imx6qdl-sr-som-emmc.dtsi deleted file mode 100644 index 5f3b8baab20..00000000000 --- a/sys/gnu/dts/arm/imx6qdl-sr-som-emmc.dtsi +++ /dev/null @@ -1,70 +0,0 @@ -/* - * Copyright (C) 2013,2014 Russell King - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -&iomuxc { - microsom { - pinctrl_microsom_usdhc3: microsom-usdhc3 { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 - MX6QDL_PAD_SD3_RST__SD3_RESET 0x17059 - >; - }; - }; -}; - -/* USDHC3 - eMMC */ -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_microsom_usdhc3>; - bus-width = <8>; - non-removable; - vmmc-supply = <&vcc_3v3>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx6qdl-sr-som-ti.dtsi b/sys/gnu/dts/arm/imx6qdl-sr-som-ti.dtsi deleted file mode 100644 index 44a97ba93a9..00000000000 --- a/sys/gnu/dts/arm/imx6qdl-sr-som-ti.dtsi +++ /dev/null @@ -1,170 +0,0 @@ -/* - * Copyright (C) 2013,2014 Russell King - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -#include - -/ { - nvcc_sd1: regulator-nvcc-sd1 { - compatible = "regulator-fixed"; - regulator-always-on; - regulator-name = "nvcc_sd1"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_3v3>; - }; - - clk_ti_wifi: ti-wifi-clock { - /* This is a hack around the kernel - using "fixed clock" - * results in the "pinctrl" properties being ignored, and - * the clock not being output. Instead, use a gated clock - * and the unrouted WL_XTAL_PU gpio. - */ - compatible = "gpio-gate-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_microsom_ti_clk>; - enable-gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>; - }; - - pwrseq_ti_wifi: ti-wifi-pwrseq { - compatible = "mmc-pwrseq-simple"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_microsom_ti_wifi_en>; - reset-gpios = <&gpio5 26 GPIO_ACTIVE_LOW>; - post-power-on-delay-ms = <200>; - clocks = <&clk_ti_wifi>; - clock-names = "ext_clock"; - }; -}; - -&iomuxc { - microsom { - pinctrl_microsom_ti_bt: microsom-ti-bt { - fsl,pins = < - /* BT_EN_SOC */ - MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00 0x40013070 - >; - }; - - pinctrl_microsom_ti_clk: microsom-ti-clk { - fsl,pins = < - /* EXT_32K */ - MX6QDL_PAD_GPIO_8__XTALOSC_REF_CLK_32K 0x1b0b0 - /* WL_XTAL_PU (unrouted) */ - MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x40013070 - >; - }; - - pinctrl_microsom_ti_wifi_en: microsom-ti-wifi-en { - fsl,pins = < - /* WLAN_EN_SOC */ - MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x40013070 - >; - }; - - pinctrl_microsom_ti_wifi_irq: microsom-ti-wifi-irq { - fsl,pins = < - /* WLAN_IRQ */ - MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04 0x40013070 - >; - }; - - pinctrl_microsom_uart4: microsom-uart4 { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1 - MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1 - >; - }; - - pinctrl_microsom_usdhc1: microsom-usdhc1 { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 - >; - }; - }; -}; - -/* UART4 - Connected to optional TI Wi-Fi/BT/FM */ -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_microsom_uart4>; - uart-has-rtscts; - status = "okay"; - - bluetooth { - compatible = "ti,wl1837-st"; - clocks = <&clk_ti_wifi>; - clock-names = "ext_clock"; - enable-gpios = <&gpio6 0 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_microsom_ti_bt>; - }; -}; - -/* USDHC1 - Connected to optional TI Wi-Fi/BT/FM */ -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_microsom_usdhc1>; - bus-width = <4>; - keep-power-in-suspend; - mmc-pwrseq = <&pwrseq_ti_wifi>; - non-removable; - vmmc-supply = <&vcc_3v3>; - /* vqmmc-supply = <&nvcc_sd1>; - MMC layer doesn't like it! */ - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - - wlcore@2 { - compatible = "ti,wl1837"; - reg = <2>; - interrupts-extended = <&gpio6 4 IRQ_TYPE_LEVEL_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_microsom_ti_wifi_irq>; - }; -}; diff --git a/sys/gnu/dts/arm/imx6qdl-sr-som.dtsi b/sys/gnu/dts/arm/imx6qdl-sr-som.dtsi deleted file mode 100644 index 6d7f6b9035b..00000000000 --- a/sys/gnu/dts/arm/imx6qdl-sr-som.dtsi +++ /dev/null @@ -1,121 +0,0 @@ -/* - * Copyright (C) 2013,2014 Russell King - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -#include - -/ { - vcc_3v3: regulator-vcc-3v3 { - compatible = "regulator-fixed"; - regulator-always-on; - regulator-name = "vcc_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_microsom_enet_ar8035>; - phy-mode = "rgmii-id"; - phy-reset-duration = <2>; - phy-reset-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&iomuxc { - microsom { - pinctrl_microsom_enet_ar8035: microsom-enet-ar8035 { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b8b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - /* AR8035 reset */ - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x130b0 - /* AR8035 interrupt */ - MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b0 - /* GPIO16 -> AR8035 25MHz */ - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x13030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */ - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x0a0b1 - /* AR8035 pin strapping: IO voltage: pull up */ - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - /* AR8035 pin strapping: PHYADDR#0: pull down */ - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x13030 - /* AR8035 pin strapping: PHYADDR#1: pull down */ - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030 - /* AR8035 pin strapping: MODE#1: pull up */ - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - /* AR8035 pin strapping: MODE#3: pull up */ - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - /* AR8035 pin strapping: MODE#0: pull down */ - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030 - - /* - * As the RMII pins are also connected to RGMII - * so that an AR8030 can be placed, set these - * to high-z with the same pulls as above. - * Use the GPIO settings to avoid changing the - * input select registers. - */ - MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x03000 - MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x03000 - MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x03000 - >; - }; - - pinctrl_microsom_uart1: microsom-uart1 { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 - >; - }; - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_microsom_uart1>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx6qdl-ts4900.dtsi b/sys/gnu/dts/arm/imx6qdl-ts4900.dtsi deleted file mode 100644 index 267c956d891..00000000000 --- a/sys/gnu/dts/arm/imx6qdl-ts4900.dtsi +++ /dev/null @@ -1,479 +0,0 @@ -/* - * Copyright 2015 Technologic Systems - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include -#include - -/ { - aliases { - ethernet0 = &fec; - }; - - leds { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_leds1>; - compatible = "gpio-leds"; - - green-led { - label = "green-led"; - gpios = <&gpio2 24 GPIO_ACTIVE_LOW>; - default-state = "on"; - }; - - red-led { - label = "red-led"; - gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3p3v"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_usb_otg_vbus: regulator-usb-otg-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - status = "okay"; -}; - -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - status = "okay"; -}; - -&ecspi1 { - cs-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - status = "okay"; - - n25q064: flash@0 { - compatible = "micron,n25q064", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <20000000>; - }; -}; - -&ecspi2 { - cs-gpios = <&gpio6 2 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi2>; - status = "okay"; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii"; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c1>; - pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>; - status = "okay"; - - isl12022: rtc@6f { - compatible = "isil,isl12022"; - reg = <0x6f>; - }; - - gpio8: gpio@28 { - compatible = "technologic,ts4900-gpio"; - reg = <0x28>; - #gpio-cells = <2>; - gpio-controller; - ngpio = <32>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c2>; - pinctrl-1 = <&pinctrl_i2c2_gpio>; - scl-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 - MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x100b1 /* Onboard flash CS1# */ - >; - }; - - pinctrl_ecspi2: ecspi2grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x100b1 - MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x100b1 - MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x100b1 - MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x100b1 /* Offboard CS0# */ - MX6QDL_PAD_CSI0_DAT16__GPIO6_IO02 0x100b1 /* FPGA CS1# */ - MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1b0b1 /* FPGA_RESET# */ - MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b1 /* FPGA_DONE */ - MX6QDL_PAD_GPIO_3__XTALOSC_REF_CLK_24M 0x10 /* FPGA 24MHZ */ - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b1 /* FPGA_IRQ */ - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x4001b0a8 - MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b1 - MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b1 /* ETH_PHY_RESET */ - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 - MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 - >; - }; - - pinctrl_flexcan2: flexcan2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b1 - MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b1 - >; - }; - - pinctrl_hog: hoggrp { - fsl,pins = < - MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b1 /* OFF_BD_RESET# */ - MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b1 /* EN_USB_5V# */ - MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x1b0b1 /* EN_LCD_3.3V */ - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* Audio CLK */ - MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b1 /* DIO_1 */ - MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b1 /* DIO_2 */ - MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b1 /* DIO_3 */ - MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x1b0b1 /* DIO_4 */ - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b1 /* DIO_5 */ - MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b1 /* DIO_7 */ - MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x1b0b1 /* DIO_8 */ - MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b1 /* DIO_9 */ - MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x1b0b1 /* DIO_0 */ - MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x1b0b1 /* DIO_6 */ - MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x1b0b1 /* CPU_DIO_A */ - MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x1b0b1 /* DIO_2 */ - MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x1b0b1 /* CPU_DIO_B */ - MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b1 /* BUS_ALE# */ - MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x1b0b1 /* DIO_15 */ - MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x1b0b1 /* BUS_DIR */ - MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x1b0b1 /* BUS_CS# */ - MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b1 /* DIO_14 */ - MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x1b0b1 /* DIO_16 */ - MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x1b0b1 /* DIO_12 */ - MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x1b0b1 /* DIO_18 */ - MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x1b0b1 /* DIO_19 */ - MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x1b0b1 /* DIO_20 */ - MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b1 /* BUS_BHE# */ - MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b1 /* DIO_13 */ - MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1b0b1 /* EIM_WAIT# */ - MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x1b0b1 /* DIO_10 */ - MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x1b0b1 /* MUX_AD_00 */ - MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x1b0b1 /* MUX_AD_01 */ - MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x1b0b1 /* MUX_AD_02 */ - MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x1b0b1 /* MUX_AD_03 */ - MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x1b0b1 /* MUX_AD_04 */ - MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x1b0b1 /* MUX_AD_05 */ - MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x1b0b1 /* MUX_AD_06 */ - MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x1b0b1 /* MUX_AD_07 */ - MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x1b0b1 /* MUX_AD_08 */ - MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x1b0b1 /* MUX_AD_09 */ - MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x1b0b1 /* MUX_AD_10 */ - MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0x1b0b1 /* MUX_AD_11 */ - MX6QDL_PAD_EIM_DA12__GPIO3_IO12 0x1b0b1 /* MUX_AD_12 */ - MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x1b0b1 /* MUX_AD_13 */ - MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x1b0b1 /* MUX_AD_14 */ - MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x1b0b1 /* MUX_AD_15 */ - MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x1b0b1 /* LCD_CLK */ - MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x1b0b1 /* DE */ - MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b1 /* Hsync */ - MX6QDL_PAD_DI0_PIN3__GPIO4_IO19 0x1b0b1 /* Vsync */ - MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21 0x1b0b1 - MX6QDL_PAD_DISP0_DAT1__GPIO4_IO22 0x1b0b1 - MX6QDL_PAD_DISP0_DAT2__GPIO4_IO23 0x1b0b1 - MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x1b0b1 - MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x1b0b1 - MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x1b0b1 - MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x1b0b1 - MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x1b0b1 - MX6QDL_PAD_DISP0_DAT8__GPIO4_IO29 0x1b0b1 - MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x1b0b1 - MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31 0x1b0b1 - MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x1b0b1 - MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06 0x1b0b1 - MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07 0x1b0b1 - MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x1b0b1 - MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x1b0b1 - MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 0x1b0b1 - MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x1b0b1 - MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b0b1 - MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b1 - MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b1 - MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1b0b1 - MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1b0b1 - MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b1 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c1_gpio: i2c1gpiogrp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b1 - MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c2_gpio: i2c2gpiogrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1 - >; - }; - - pinctrl_leds1: leds1grp { - fsl,pins = < - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b1 /* RED_LED# */ - MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x1b0b1 /* GREEN_LED# */ - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_GPIO_7__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_GPIO_8__UART2_RX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1 - MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 - MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x17059 /* WIFI IRQ */ - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 - MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x1b0b1 /* EN_SD_POWER# */ - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - >; - }; -}; - -&pcie { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - uart-has-rtscts; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - status = "okay"; -}; - -&usbh1 { - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "okay"; -}; - -/* SD */ -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - vmmc-supply = <®_3p3v>; - bus-width = <4>; - fsl,wp-controller; - status = "okay"; -}; - -/* eMMC */ -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - vmmc-supply = <®_3p3v>; - bus-width = <4>; - non-removable; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx6qdl-ts7970.dtsi b/sys/gnu/dts/arm/imx6qdl-ts7970.dtsi deleted file mode 100644 index f0be516dc28..00000000000 --- a/sys/gnu/dts/arm/imx6qdl-ts7970.dtsi +++ /dev/null @@ -1,594 +0,0 @@ -/* - * Copyright 2015 Technologic Systems - * Copyright 2017 Savoir-Faire Linux - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include -#include - -/ { - leds { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_leds1>; - compatible = "gpio-leds"; - - green-led { - label = "green-led"; - gpios = <&gpio3 27 GPIO_ACTIVE_LOW>; - default-state = "on"; - }; - - red-led { - label = "red-led"; - gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - yel-led { - label = "yellow-led"; - gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - blue-led { - label = "blue-led"; - gpios = <&gpio4 25 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - en-usb-5v { - label = "en-usb-5v"; - gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - sel_dc_usb { - label = "sel_dc_usb"; - gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3p3v"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_can1_3v3: reg_can1_3v3 { - compatible = "regulator-fixed"; - regulator-name = "reg_can1_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_can2_3v3: en-reg_can2_3v3 { - compatible = "regulator-fixed"; - regulator-name = "reg_can2_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio6 31 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usb_otg_vbus: regulator-usb-otg-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_wlan_vmmc: regulator_wlan_vmmc { - compatible = "regulator-fixed"; - regulator-name = "wlan_vmmc"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio8 14 GPIO_ACTIVE_HIGH>; - startup-delay-us = <70000>; - enable-active-high; - }; - - sound-sgtl5000 { - audio-codec = <&sgtl5000>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - compatible = "fsl,imx-audio-sgtl5000"; - model = "On-board Codec"; - mux-ext-port = <3>; - mux-int-port = <1>; - ssi-controller = <&ssi1>; - }; -}; - -&audmux { - status = "okay"; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - xceiver-supply = <®_can1_3v3>; - status = "okay"; -}; - -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - xceiver-supply = <®_can2_3v3>; - status = "okay"; -}; - -&ecspi1 { - cs-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - status = "okay"; - - n25q064: flash@0 { - compatible = "micron,n25q064", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <20000000>; - }; -}; - -&ecspi2 { - cs-gpios = < - &gpio5 31 GPIO_ACTIVE_HIGH - &gpio7 12 GPIO_ACTIVE_HIGH - &gpio5 18 GPIO_ACTIVE_HIGH - >; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi2>; - status = "okay"; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii"; - interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, - <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; - fsl,err006687-workaround-present; - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c1>; - pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>; - status = "okay"; - - m41t00s: rtc@68 { - compatible = "m41t00"; - reg = <0x68>; - }; - - isl12022: rtc@6f { - compatible = "isl,isl12022"; - reg = <0x6f>; - }; - - gpio8: gpio@28 { - compatible = "technologic,ts7970-gpio"; - reg = <0x28>; - #gpio-cells = <2>; - gpio-controller; - ngpio = <32>; - }; - - sgtl5000: codec@a { - compatible = "fsl,sgtl5000"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sgtl5000>; - reg = <0x0a>; - clocks = <&clks IMX6QDL_CLK_CKO>; - VDDA-supply = <®_3p3v>; - VDDIO-supply = <®_3p3v>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c2>; - pinctrl-1 = <&pinctrl_i2c2_gpio>; - scl-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 - MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x100b1 /* Onboard Flash CS */ - >; - }; - - pinctrl_ecspi2: ecspi2 { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x100b1 - MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x100b1 - MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x100b1 - MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x100b1 /* FPGA_SPI_CS0 */ - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x100b1 /* FPGA_SPI_CS1 */ - MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x100b1 /* HD1_SPI_CS */ - MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1b088 /* FPGA_RESET */ - MX6QDL_PAD_GPIO_3__XTALOSC_REF_CLK_24M 0x10 /* FPGA 24MHZ */ - MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b088 /* FPGA_IRQ_0 */ - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b088 /* FPGA_IRQ_1 */ - >; - }; - - pinctrl_enet: enet { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b088 - MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b088 /* ETH_PHY_RESET */ - MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b088 - MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b088 - MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21 0x1b088 /* EN_CAN_1 */ - >; - }; - - pinctrl_flexcan2: flexcan2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b088 - MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b088 - MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b088 /* EN_CAN_2 */ - >; - }; - - pinctrl_hog: hoggrp { - fsl,pins = < - /* Onboard */ - MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b088 /* USB_HUB_RESET */ - MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b088 /* SEL_DC_USB */ - MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b088 /* EN_USB_5V */ - MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x1b088 /* JTAG_FPGA_TMS */ - MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x1b088 /* JTAG_FPGA_TCK */ - MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b088 /* JTAG_FPGA_TDO */ - MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1b088 /* JTAG_FPGA_TDI */ - MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b088 /* GYRO_INT */ - MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x1b088 /* MODBUS_FAULT */ - MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x1b088 /* BUS_DIR/JP_SD_BOOT */ - MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x1b088 /* EN_MODBUS_24V */ - MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x1b088 /* EN_MODBUS_3V */ - MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b088 /* I210_RESET */ - MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b088 /* EN_RTC_PWR */ - MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b088 /* REVSTRAP1 */ - - /* Offboard */ - MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x1b088 /* LCD_D09 */ - MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x1b088 /* HD1_IRQ */ - MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31 0x1b088 /* LCD_D10 */ - MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x1b088 /* LCD_D11 */ - MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x1b088 /* BUS_BHE */ - MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b088 /* BUS_ALE */ - MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x1b088 /* BUS_CS */ - MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x1b088 /* DIO_20 */ - MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1b088 /* BUS_WAIT */ - MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x1b088 /* MUX_AD_00 */ - MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x1b088 /* MUX_AD_01 */ - MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x1b088 /* MUX_AD_02 */ - MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x1b088 /* MUX_AD_03 */ - MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x1b088 /* MUX_AD_04 */ - MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x1b088 /* MUX_AD_05 */ - MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x1b088 /* MUX_AD_06 */ - MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x1b088 /* MUX_AD_07 */ - MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x1b088 /* MUX_AD_08 */ - MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x1b088 /* MUX_AD_09 */ - MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x1b088 /* MUX_AD_10 */ - MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0x1b088 /* MUX_AD_11 */ - MX6QDL_PAD_EIM_DA12__GPIO3_IO12 0x1b088 /* MUX_AD_12 */ - MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x1b088 /* MUX_AD_13 */ - MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x1b088 /* MUX_AD_14 */ - MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x1b088 /* MUX_AD_15 */ - - /* Strapping only */ - MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b088 - MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x1b088 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c1_gpio: i2c1gpiogrp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b1 - MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c2_gpio: i2c2gpiogrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1 - >; - }; - - pinctrl_leds1: leds1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x1b088 /* GREEN_LED */ - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b088 /* RED_LED */ - MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b088 /* YEL_LED */ - MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x1b088 /* IMX6_BLUE_LED */ - >; - }; - - pinctrl_sgtl5000: sgtl5000grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 - MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 - MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 - MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* Audio CLK */ - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b088 - MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b088 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_GPIO_7__UART2_TX_DATA 0x1b088 - MX6QDL_PAD_GPIO_8__UART2_RX_DATA 0x1b088 - MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b088 - MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b088 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b088 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b088 - MX6QDL_PAD_EIM_D30__UART3_RTS_B 0x1b088 - MX6QDL_PAD_EIM_D31__UART3_CTS_B 0x1b088 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b088 - MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b088 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b088 - MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b088 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 - MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x17059 /* WIFI IRQ */ - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 - MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x1b088 /* EN_SD_POWER */ - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - >; - }; -}; - -&pcie { - status = "okay"; -}; - -&snvs_rtc { - status = "disabled"; -}; - -&ssi1 { - fsl,mode = "i2s-slave"; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - uart-has-rtscts; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - status = "okay"; -}; - -&usbh1 { - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "okay"; -}; - -/* WIFI */ -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - vmmc-supply = <®_wlan_vmmc>; - bus-width = <4>; - non-removable; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - wlcore: wlcore@2 { - compatible = "ti,wl1271"; - reg = <2>; - interrupt-parent = <&gpio1>; - interrupts = <26 IRQ_TYPE_LEVEL_HIGH>; - ref-clock-frequency = <38400000>; - }; -}; - -/* SD */ -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - vmmc-supply = <®_3p3v>; - bus-width = <4>; - fsl,wp-controller; - status = "okay"; -}; - -/* eMMC */ -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - vmmc-supply = <®_3p3v>; - bus-width = <4>; - non-removable; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx6qdl-tx6-lcd.dtsi b/sys/gnu/dts/arm/imx6qdl-tx6-lcd.dtsi deleted file mode 100644 index 79f2354886b..00000000000 --- a/sys/gnu/dts/arm/imx6qdl-tx6-lcd.dtsi +++ /dev/null @@ -1,251 +0,0 @@ -/* - * Copyright 2017 Lothar Waßmann - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/ { - aliases { - display = &display; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd1_pwr>; - enable-gpios = <&gpio2 31 GPIO_ACTIVE_HIGH>; - power-supply = <®_3v3>; - turn-on-delay-ms = <35>; - /* - * a poor man's way to create a 1:1 relationship between - * the PWM value and the actual duty cycle - */ - brightness-levels = < 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100>; - default-brightness-level = <50>; - }; - - lcd_panel: lcd-panel { - compatible = "edt,etm0700g0dh6"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd0_pwr>; - enable-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>; - power-supply = <®_3v3>; - backlight = <&backlight>; - - port { - lcd_panel_in: endpoint { - remote-endpoint = <&lcd_out>; - }; - }; - }; - - display: disp0 { - compatible = "fsl,imx-parallel-display"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_disp0_1>; - status = "okay"; - - port@0 { - reg = <0>; - - lcd_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - - port@1 { - reg = <1>; - - lcd_out: endpoint { - remote-endpoint = <&lcd_panel_in>; - }; - }; - - display-timings { - VGA { - clock-frequency = <25200000>; - hactive = <640>; - vactive = <480>; - hback-porch = <48>; - hsync-len = <96>; - hfront-porch = <16>; - vback-porch = <31>; - vsync-len = <2>; - vfront-porch = <12>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ETV570 { - u-boot,panel-name = "edt,et057090dhu"; - clock-frequency = <25200000>; - hactive = <640>; - vactive = <480>; - hback-porch = <114>; - hsync-len = <30>; - hfront-porch = <16>; - vback-porch = <32>; - vsync-len = <3>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ET0350 { - u-boot,panel-name = "edt,et0350g0dh6"; - clock-frequency = <6413760>; - hactive = <320>; - vactive = <240>; - hback-porch = <34>; - hsync-len = <34>; - hfront-porch = <20>; - vback-porch = <15>; - vsync-len = <3>; - vfront-porch = <4>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ET0430 { - u-boot,panel-name = "edt,et0430g0dh6"; - clock-frequency = <9009000>; - hactive = <480>; - vactive = <272>; - hback-porch = <2>; - hsync-len = <41>; - hfront-porch = <2>; - vback-porch = <2>; - vsync-len = <10>; - vfront-porch = <2>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - - ET0500 { - clock-frequency = <33264000>; - hactive = <800>; - vactive = <480>; - hback-porch = <88>; - hsync-len = <128>; - hfront-porch = <40>; - vback-porch = <33>; - vsync-len = <2>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ET0700 { /* same as ET0500 */ - u-boot,panel-name = "edt,etm0700g0dh6"; - clock-frequency = <33264000>; - hactive = <800>; - vactive = <480>; - hback-porch = <88>; - hsync-len = <128>; - hfront-porch = <40>; - vback-porch = <33>; - vsync-len = <2>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ETQ570 { - clock-frequency = <6596040>; - hactive = <320>; - vactive = <240>; - hback-porch = <38>; - hsync-len = <30>; - hfront-porch = <30>; - vback-porch = <16>; - vsync-len = <3>; - vfront-porch = <4>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - CoMTFT { /* same as ET0700 but with inverted pixel clock */ - u-boot,panel-name = "edt,etm0700g0edh6"; - clock-frequency = <33264000>; - hactive = <800>; - vactive = <480>; - hback-porch = <88>; - hsync-len = <128>; - hfront-porch = <40>; - vback-porch = <33>; - vsync-len = <2>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - }; -}; - -&ipu1_di0_disp0 { - remote-endpoint = <&lcd_in>; -}; diff --git a/sys/gnu/dts/arm/imx6qdl-tx6-lvds.dtsi b/sys/gnu/dts/arm/imx6qdl-tx6-lvds.dtsi deleted file mode 100644 index 2ca2eb37e14..00000000000 --- a/sys/gnu/dts/arm/imx6qdl-tx6-lvds.dtsi +++ /dev/null @@ -1,286 +0,0 @@ -/* - * Copyright 2017 Lothar Waßmann - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/ { - aliases { - display = &lvds0; - lvds0 = &lvds0; - lvds1 = &lvds1; - }; - - backlight0: backlight0 { - compatible = "pwm-backlight"; - pwms = <&pwm2 0 500000 0>; - power-supply = <®_lcd0_pwr>; - brightness-levels = < 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100>; - default-brightness-level = <50>; - }; - - backlight1: backlight1 { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 500000 0>; - power-supply = <®_lcd1_pwr>; - brightness-levels = < 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100>; - default-brightness-level = <50>; - }; - - lvds0_panel: lvds0-panel { - compatible = "nlt,nl12880bc20-spwg-24"; - backlight = <&backlight0>; - power-supply = <®_3v3>; - - port { - panel_in_lvds0: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - }; - - lvds1_panel: lvds1-panel { - compatible = "nlt,nl12880bc20-spwg-24"; - backlight = <&backlight1>; - power-supply = <®_3v3>; - - port { - panel_in_lvds1: endpoint { - remote-endpoint = <&lvds1_out>; - }; - }; - }; -}; - -&kpp { - status = "disabled"; /* pad conflict with backlight1 PWM */ -}; - -&ldb { - status = "okay"; - - lvds0: lvds-channel@0 { - fsl,data-width = <18>; - status = "okay"; - - port@4 { - reg = <4>; - - lvds0_out: endpoint { - remote-endpoint = <&panel_in_lvds0>; - }; - }; - - display-timings { - hsd100pxn1 { - u-boot,panel-name = "hannstar,hsd100pxn1"; - clock-frequency = <65000000>; - hactive = <1024>; - vactive = <768>; - hback-porch = <220>; - hfront-porch = <40>; - vback-porch = <21>; - vfront-porch = <7>; - hsync-len = <60>; - vsync-len = <10>; - de-active = <1>; - pixelclk-active = <1>; - }; - - VGA { - clock-frequency = <25200000>; - hactive = <640>; - vactive = <480>; - hback-porch = <48>; - hfront-porch = <16>; - vback-porch = <31>; - vfront-porch = <12>; - hsync-len = <96>; - vsync-len = <2>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - nl12880bc20 { - u-boot,panel-name = "nlt,nl12880bc20-spwg-24"; - clock-frequency = <71000000>; - hactive = <1280>; - vactive = <800>; - hback-porch = <50>; - hfront-porch = <50>; - vback-porch = <5>; - vfront-porch = <5>; - hsync-len = <60>; - vsync-len = <13>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - - ET0700 { - u-boot,panel-name = "edt,etm0700g0dh6"; - clock-frequency = <33264000>; - hactive = <800>; - vactive = <480>; - hback-porch = <88>; - hsync-len = <128>; - hfront-porch = <40>; - vback-porch = <33>; - vsync-len = <2>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ETV570 { - u-boot,panel-name = "edt,et057090dhu"; - clock-frequency = <25200000>; - hactive = <640>; - vactive = <480>; - hback-porch = <114>; - hsync-len = <30>; - hfront-porch = <16>; - vback-porch = <32>; - vsync-len = <3>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - }; - }; - - lvds1: lvds-channel@1 { - fsl,data-width = <18>; - status = "okay"; - - port@4 { - reg = <4>; - - lvds1_out: endpoint { - remote-endpoint = <&panel_in_lvds1>; - }; - }; - - display-timings { - hsd100pxn1 { - clock-frequency = <65000000>; - hactive = <1024>; - vactive = <768>; - hback-porch = <220>; - hfront-porch = <40>; - vback-porch = <21>; - vfront-porch = <7>; - hsync-len = <60>; - vsync-len = <10>; - de-active = <1>; - pixelclk-active = <1>; - }; - - VGA { - clock-frequency = <25200000>; - hactive = <640>; - vactive = <480>; - hback-porch = <48>; - hfront-porch = <16>; - vback-porch = <31>; - vfront-porch = <12>; - hsync-len = <96>; - vsync-len = <2>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - nl12880bc20 { - clock-frequency = <71000000>; - hactive = <1280>; - vactive = <800>; - hback-porch = <50>; - hfront-porch = <50>; - vback-porch = <5>; - vfront-porch = <5>; - hsync-len = <60>; - vsync-len = <13>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - }; -}; - -&pwm1 { - status = "okay"; -}; - -®_lcd0_pwr { - status = "okay"; -}; - -®_lcd1_pwr { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx6qdl-tx6-mb7.dtsi b/sys/gnu/dts/arm/imx6qdl-tx6-mb7.dtsi deleted file mode 100644 index 410972e1dca..00000000000 --- a/sys/gnu/dts/arm/imx6qdl-tx6-mb7.dtsi +++ /dev/null @@ -1,96 +0,0 @@ -/* - * Copyright 2017 Lothar Waßmann - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/ { - backlight0 { - pwms = <&pwm1 0 500000 PWM_POLARITY_INVERTED>; - turn-on-delay-ms = <35>; - power-supply = <®_lcd1_pwr>; - }; - - backlight1 { - pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>; - turn-on-delay-ms = <35>; - power-supply = <®_lcd1_pwr>; - }; - - lcd-panel { - compatible = "edt,et057090dhu"; - pixelclk-active = <0>; - }; - - lvds0-panel { - compatible = "edt,etml1010g0dka"; - pixelclk-active = <0>; - }; - - lvds1-panel { - compatible = "edt,etml1010g0dka"; - pixelclk-active = <0>; - }; -}; - -&can1 { - status = "disabled"; -}; - -&can2 { - xceiver-supply = <®_3v3>; -}; - -&ds1339 { - /* - * The backup voltage of the module internal RTC is not wired - * by default on the MB7, so disable that RTC chip. - */ - status = "disabled"; -}; - -&i2c3 { - rtc: mcp7940x@6f { - compatible = "microchip,mcp7940x"; - reg = <0x6f>; - }; -}; - -®_lcd0_pwr { - status = "disabled"; -}; diff --git a/sys/gnu/dts/arm/imx6qdl-tx6.dtsi b/sys/gnu/dts/arm/imx6qdl-tx6.dtsi deleted file mode 100644 index c68cb90fd80..00000000000 --- a/sys/gnu/dts/arm/imx6qdl-tx6.dtsi +++ /dev/null @@ -1,811 +0,0 @@ -/* - * Copyright 2014-2017 Lothar Waßmann - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include -#include -#include -#include -#include - -/ { - aliases { - can0 = &can2; - can1 = &can1; - ethernet0 = &fec; - lcdif-23bit-pins-a = &pinctrl_disp0_1; - lcdif-24bit-pins-a = &pinctrl_disp0_2; - pwm0 = &pwm1; - pwm1 = &pwm2; - reg-can-xcvr = ®_can_xcvr; - stk5led = &user_led; - usbotg = &usbotg; - sdhc0 = &usdhc1; - sdhc1 = &usdhc2; - }; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0>; /* will be filled by U-Boot */ - }; - - clocks { - #address-cells = <1>; - #size-cells = <0>; - - mclk: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <26000000>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - power { - label = "Power Button"; - gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; - linux,code = ; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - - user_led: user { - label = "Heartbeat"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_user_led>; - gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - reg_3v3_etn: regulator-3v3-etn { - compatible = "regulator-fixed"; - regulator-name = "3V3_ETN"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_etnphy_power>; - gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_2v5: regulator-2v5 { - compatible = "regulator-fixed"; - regulator-name = "2V5"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - reg_3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_can_xcvr: regulator-can-xcvr { - compatible = "regulator-fixed"; - regulator-name = "CAN XCVR"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan_xcvr>; - gpio = <&gpio4 21 GPIO_ACTIVE_LOW>; - }; - - reg_lcd0_pwr: regulator-lcd0-pwr { - compatible = "regulator-fixed"; - regulator-name = "LCD0 POWER"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd0_pwr>; - gpio = <&gpio3 29 GPIO_ACTIVE_HIGH>; - enable-active-high; - status = "disabled"; - }; - - reg_lcd1_pwr: regulator-lcd1-pwr { - compatible = "regulator-fixed"; - regulator-name = "LCD1 POWER"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd1_pwr>; - gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>; - enable-active-high; - status = "disabled"; - }; - - reg_usbh1_vbus: regulator-usbh1-vbus { - compatible = "regulator-fixed"; - regulator-name = "usbh1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh1_vbus>; - gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usbotg_vbus: regulator-usbotg-vbus { - compatible = "regulator-fixed"; - regulator-name = "usbotg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg_vbus>; - gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - sound { - compatible = "karo,imx6qdl-tx6-sgtl5000", - "simple-audio-card"; - simple-audio-card,name = "imx6qdl-tx6-sgtl5000-audio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&codec_dai>; - simple-audio-card,frame-master = <&codec_dai>; - simple-audio-card,widgets = - "Microphone", "Mic Jack", - "Line", "Line In", - "Line", "Line Out", - "Headphone", "Headphone Jack"; - simple-audio-card,routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - - cpu_dai: simple-audio-card,cpu { - sound-dai = <&ssi1>; - }; - - codec_dai: simple-audio-card,codec { - sound-dai = <&sgtl5000>; - }; - }; -}; - -&audmux { - status = "okay"; - - ssi1 { - fsl,audmux-port = <0>; - fsl,port-config = < - (IMX_AUDMUX_V2_PTCR_SYN | - IMX_AUDMUX_V2_PTCR_TFSEL(4) | - IMX_AUDMUX_V2_PTCR_TCSEL(4) | - IMX_AUDMUX_V2_PTCR_TFSDIR | - IMX_AUDMUX_V2_PTCR_TCLKDIR) - IMX_AUDMUX_V2_PDCR_RXDSEL(4) - >; - }; - - pins5 { - fsl,audmux-port = <4>; - fsl,port-config = < - IMX_AUDMUX_V2_PTCR_SYN - IMX_AUDMUX_V2_PDCR_RXDSEL(0) - >; - }; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - xceiver-supply = <®_can_xcvr>; - status = "okay"; -}; - -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - xceiver-supply = <®_can_xcvr>; - status = "okay"; -}; - -&ecspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - cs-gpios = < - &gpio2 30 GPIO_ACTIVE_HIGH - &gpio3 19 GPIO_ACTIVE_HIGH - >; - status = "disabled"; - - spidev0: spi@0 { - compatible = "spidev"; - reg = <0>; - spi-max-frequency = <54000000>; - }; - - spidev1: spi@1 { - compatible = "spidev"; - reg = <1>; - spi-max-frequency = <54000000>; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet &pinctrl_enet_mdio &pinctrl_etnphy_rst>; - clocks = <&clks IMX6QDL_CLK_ENET>, - <&clks IMX6QDL_CLK_ENET>, - <&clks IMX6QDL_CLK_ENET_REF>, - <&clks IMX6QDL_CLK_ENET_REF>; - clock-names = "ipg", "ahb", "ptp", "enet_out"; - phy-mode = "rmii"; - phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>; - phy-reset-post-delay = <10>; - phy-handle = <&etnphy>; - phy-supply = <®_3v3_etn>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - etnphy: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_etnphy_int>; - interrupt-parent = <&gpio7>; - interrupts = <1 IRQ_TYPE_EDGE_FALLING>; - }; - }; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - nand-on-flash-bbt; - fsl,no-blockmark-swap; - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c1>; - pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>; - clock-frequency = <400000>; - status = "okay"; - - ds1339: rtc@68 { - compatible = "dallas,ds1339"; - reg = <0x68>; - trickle-resistor-ohms = <250>; - trickle-diode-disable; - }; -}; - -&i2c3 { - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c3>; - pinctrl-1 = <&pinctrl_i2c3_gpio>; - scl-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; - clock-frequency = <400000>; - status = "okay"; - - sgtl5000: sgtl5000@a { - compatible = "fsl,sgtl5000"; - #sound-dai-cells = <0>; - reg = <0x0a>; - VDDA-supply = <®_2v5>; - VDDIO-supply = <®_3v3>; - clocks = <&mclk>; - }; - - polytouch: edt-ft5x06@38 { - compatible = "edt,edt-ft5x06"; - reg = <0x38>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_edt_ft5x06>; - interrupt-parent = <&gpio6>; - interrupts = <15 IRQ_TYPE_EDGE_FALLING>; - reset-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>; - wake-gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>; - wakeup-source; - }; - - touchscreen: tsc2007@48 { - compatible = "ti,tsc2007"; - reg = <0x48>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_tsc2007>; - interrupt-parent = <&gpio3>; - interrupts = <26 0>; - gpios = <&gpio3 26 GPIO_ACTIVE_LOW>; - ti,x-plate-ohms = <660>; - wakeup-source; - }; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_hog: hoggrp { - fsl,pins = < - MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b1 /* PWR BTN */ - >; - }; - - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x130b0 /* SSI1_RXD */ - MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x110b0 /* SSI1_TXD */ - MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0 /* SSI1_CLK */ - MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0 /* SSI1_FS */ - >; - }; - - pinctrl_disp0_1: disp0grp-1 { - fsl,pins = < - MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 - MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 - MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 - MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 - /* PAD DISP0_DAT0 is used for the Flexcan transceiver control */ - MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 - MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 - MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 - MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 - MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 - MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 - MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 - MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 - MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 - MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 - MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 - MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 - MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 - MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 - MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 - MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 - MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 - MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 - MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 - MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 - MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 - MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 - MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 - >; - }; - - pinctrl_disp0_2: disp0grp-2 { - fsl,pins = < - MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 - MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 - MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 - MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 - MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 - MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 - MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 - MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 - MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 - MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 - MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 - MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 - MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 - MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 - MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 - MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 - MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 - MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 - MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 - MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 - MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 - MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 - MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 - MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 - MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 - MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 - MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 - MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x0b0b0 - MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x0b0b0 - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x0b0b0 - MX6QDL_PAD_GPIO_19__ECSPI1_RDY 0x0b0b0 - MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x0b0b0 /* SPI CS0 */ - MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x0b0b0 /* SPI CS1 */ - >; - }; - - pinctrl_edt_ft5x06: edt-ft5x06grp { - fsl,pins = < - MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 /* Interrupt */ - MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b0 /* Reset */ - MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0 /* Wake */ - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 - MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 - MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 - MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 - MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 - MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 - MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 - >; - }; - - pinctrl_enet_mdio: enet-mdiogrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - >; - }; - - pinctrl_etnphy_int: etnphy-intgrp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b1 /* ETN PHY INT */ - >; - }; - - pinctrl_etnphy_power: etnphy-pwrgrp { - fsl,pins = < - MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b1 /* ETN PHY POWER */ - >; - }; - - pinctrl_etnphy_rst: etnphy-rstgrp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT2__GPIO7_IO06 0x1b0b1 /* ETN PHY RESET */ - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0 - MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0 - >; - }; - - pinctrl_flexcan2: flexcan2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0 - MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0 - >; - }; - - pinctrl_flexcan_xcvr: flexcan-xcvrgrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21 0x1b0b0 /* Flexcan XCVR enable */ - >; - }; - - pinctrl_gpmi_nand: gpminandgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0x0b0b1 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0x0b0b1 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0x0b0b1 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0x0b000 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0x0b0b1 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0x0b0b1 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0x0b0b1 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0x0b0b1 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0x0b0b1 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0x0b0b1 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0x0b0b1 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0x0b0b1 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0x0b0b1 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0x0b0b1 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0x0b0b1 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c1_gpio: i2c1-gpiogrp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b1 - MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3_gpio: i2c3-gpiogrp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x4001b8b1 - MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x4001b8b1 - >; - }; - - pinctrl_kpp: kppgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_9__KEY_COL6 0x1b0b1 - MX6QDL_PAD_GPIO_4__KEY_COL7 0x1b0b1 - MX6QDL_PAD_KEY_COL2__KEY_COL2 0x1b0b1 - MX6QDL_PAD_KEY_COL3__KEY_COL3 0x1b0b1 - MX6QDL_PAD_GPIO_2__KEY_ROW6 0x1b0b1 - MX6QDL_PAD_GPIO_5__KEY_ROW7 0x1b0b1 - MX6QDL_PAD_KEY_ROW2__KEY_ROW2 0x1b0b1 - MX6QDL_PAD_KEY_ROW3__KEY_ROW3 0x1b0b1 - >; - }; - - pinctrl_lcd0_pwr: lcd0-pwrgrp { - fsl,pins = < - MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b1 /* LCD Reset */ - >; - }; - - pinctrl_lcd1_pwr: lcd-pwrgrp { - fsl,pins = < - MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x1b0b1 /* LCD Power Enable */ - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1 - >; - }; - - pinctrl_tsc2007: tsc2007grp { - fsl,pins = < - MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x1b0b0 /* Interrupt */ - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart1_rtscts: uart1_rtsctsgrp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT1__UART1_RTS_B 0x1b0b1 - MX6QDL_PAD_SD3_DAT0__UART1_CTS_B 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart2_rtscts: uart2_rtsctsgrp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1 - MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart3_rtscts: uart3_rtsctsgrp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT3__UART3_CTS_B 0x1b0b1 - MX6QDL_PAD_SD3_RST__UART3_RTS_B 0x1b0b1 - >; - }; - - pinctrl_usbh1_vbus: usbh1-vbusgrp { - fsl,pins = < - MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b0 /* USBH1_VBUSEN */ - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x17059 - >; - }; - - pinctrl_usbotg_vbus: usbotg-vbusgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 /* USBOTG_VBUSEN */ - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x070b1 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x070b1 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x070b1 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x070b1 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x070b1 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x070b1 - MX6QDL_PAD_SD3_CMD__GPIO7_IO02 0x170b0 /* SD1 CD */ - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x070b1 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x070b1 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x070b1 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x070b1 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x070b1 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x070b1 - MX6QDL_PAD_SD3_CLK__GPIO7_IO03 0x170b0 /* SD2 CD */ - >; - }; - - pinctrl_user_led: user-ledgrp { - fsl,pins = < - MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b1 /* LED */ - >; - }; -}; - -&kpp { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_kpp>; - /* sample keymap */ - /* row/col 0,1 are mapped to KPP row/col 6,7 */ - linux,keymap = < - MATRIX_KEY(6, 6, KEY_POWER) /* 0x06060074 */ - MATRIX_KEY(6, 7, KEY_KP0) /* 0x06070052 */ - MATRIX_KEY(6, 2, KEY_KP1) /* 0x0602004f */ - MATRIX_KEY(6, 3, KEY_KP2) /* 0x06030050 */ - MATRIX_KEY(7, 6, KEY_KP3) /* 0x07060051 */ - MATRIX_KEY(7, 7, KEY_KP4) /* 0x0707004b */ - MATRIX_KEY(7, 2, KEY_KP5) /* 0x0702004c */ - MATRIX_KEY(7, 3, KEY_KP6) /* 0x0703004d */ - MATRIX_KEY(2, 6, KEY_KP7) /* 0x02060047 */ - MATRIX_KEY(2, 7, KEY_KP8) /* 0x02070048 */ - MATRIX_KEY(2, 2, KEY_KP9) /* 0x02020049 */ - >; - status = "okay"; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - #pwm-cells = <3>; - status = "disabled"; -}; - -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm2>; - #pwm-cells = <3>; - status = "okay"; -}; - -&ssi1 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_rtscts>; - uart-has-rtscts; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2 &pinctrl_uart2_rtscts>; - uart-has-rtscts; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3 &pinctrl_uart3_rtscts>; - uart-has-rtscts; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usbh1_vbus>; - dr_mode = "host"; - disable-over-current; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usbotg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - dr_mode = "peripheral"; - disable-over-current; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - bus-width = <4>; - no-1-8-v; - cd-gpios = <&gpio7 2 GPIO_ACTIVE_LOW>; - fsl,wp-controller; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - bus-width = <4>; - no-1-8-v; - cd-gpios = <&gpio7 3 GPIO_ACTIVE_LOW>; - fsl,wp-controller; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx6qdl-udoo.dtsi b/sys/gnu/dts/arm/imx6qdl-udoo.dtsi deleted file mode 100644 index 828dd20cd27..00000000000 --- a/sys/gnu/dts/arm/imx6qdl-udoo.dtsi +++ /dev/null @@ -1,324 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2013 Freescale Semiconductor, Inc. - * - * Author: Fabio Estevam - */ - -/ { - aliases { - backlight = &backlight; - panelchan = &panelchan; - panel7 = &panel7; - touchscreenp7 = &touchscreenp7; - }; - - chosen { - stdout-path = &uart2; - }; - - backlight: backlight { - compatible = "gpio-backlight"; - gpios = <&gpio1 4 0>; - default-on; - status = "disabled"; - }; - - gpio-poweroff { - compatible = "gpio-poweroff"; - gpios = <&gpio2 4 0>; - pinctrl-0 = <&pinctrl_power_off>; - pinctrl-names = "default"; - }; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x40000000>; - }; - - panel7: panel7 { - /* - * in reality it is a -20t (parallel) model, - * but with LVDS bridge chip attached, - * so it is equivalent to -19t model in drive - * characteristics - */ - compatible = "urt,umsh-8596md-19t"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_panel>; - power-supply = <®_panel>; - backlight = <&backlight>; - status = "disabled"; - - port { - panel_in: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_usb_h1_vbus: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - startup-delay-us = <2>; /* USB2415 requires a POR of 1 us minimum */ - gpio = <&gpio7 12 0>; - }; - - reg_panel: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "lcd_panel"; - enable-active-high; - gpio = <&gpio1 2 0>; - }; - }; - - sound { - compatible = "fsl,imx6q-udoo-ac97", - "fsl,imx-audio-ac97"; - model = "fsl,imx6q-udoo-ac97"; - audio-cpu = <&ssi1>; - audio-routing = - "RX", "Mic Jack", - "Headphone Jack", "TX"; - mux-int-port = <1>; - mux-ext-port = <6>; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii"; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c2>; - status = "okay"; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - touchscreenp7: touchscreenp7@55 { - compatible = "sitronix,st1232"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_touchscreenp7>; - reg = <0x55>; - interrupt-parent = <&gpio1>; - interrupts = <13 8>; - gpios = <&gpio1 15 0>; - status = "disabled"; - }; -}; - -&iomuxc { - imx6q-udoo { - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001f8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001f8b1 - >; - }; - - pinctrl_panel: panelgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x70 - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x70 - >; - }; - - pinctrl_power_off: poweroffgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x30 - >; - }; - - pinctrl_touchscreenp7: touchscreenp7grp { - fsl,pins = < - MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x70 - MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x1b0b0 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbh: usbhgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000 - MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x130b0 - >; - }; - - pinctrl_usbotg: usbotg { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - MX6QDL_PAD_EIM_D22__USB_OTG_PWR 0x17059 - MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x17059 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - >; - }; - - pinctrl_ac97_running: ac97running { - fsl,pins = < - MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x1b0b0 - MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x1b0b0 - MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x13080 - MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x13080 - MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 - >; - }; - - pinctrl_ac97_warm_reset: ac97warmreset { - fsl,pins = < - MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x1b0b0 - MX6QDL_PAD_DI0_PIN3__GPIO4_IO19 0x1b0b0 - MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x13080 - MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x13080 - MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 - >; - }; - - pinctrl_ac97_reset: ac97reset { - fsl,pins = < - MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b0 - MX6QDL_PAD_DI0_PIN3__GPIO4_IO19 0x1b0b0 - MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x13080 - MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x13080 - MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 - >; - }; - }; -}; - -&ldb { - status = "okay"; - - panelchan: lvds-channel@0 { - port@4 { - reg = <4>; - - lvds0_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -&usbh1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh>; - vbus-supply = <®_usb_h1_vbus>; - clocks = <&clks IMX6QDL_CLK_CKO>; - status = "okay"; -}; - -&usbotg { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - non-removable; - status = "okay"; -}; - -&audmux { - status = "okay"; -}; - -&ssi1 { - cell-index = <0>; - fsl,mode = "ac97-slave"; - pinctrl-names = "ac97-running", "ac97-reset", "ac97-warm-reset"; - pinctrl-0 = <&pinctrl_ac97_running>; - pinctrl-1 = <&pinctrl_ac97_reset>; - pinctrl-2 = <&pinctrl_ac97_warm_reset>; - ac97-gpios = <&gpio4 19 0 &gpio4 18 0 &gpio2 30 0>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx6qdl-var-dart.dtsi b/sys/gnu/dts/arm/imx6qdl-var-dart.dtsi deleted file mode 100644 index c41cac502ba..00000000000 --- a/sys/gnu/dts/arm/imx6qdl-var-dart.dtsi +++ /dev/null @@ -1,504 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Support for Variscite DART-MX6 Module - * - * Copyright 2017 BayLibre, SAS - * Author: Neil Armstrong - */ - -#include -#include - -/ { - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x40000000>; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_wl18xx_vmmc: regulator-wl18xx { - compatible = "regulator-fixed"; - regulator-name = "vwl1807"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio7 8 GPIO_ACTIVE_HIGH>; - enable-active-high; - startup-delay-us = <70000>; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; - - ssi2 { - fsl,audmux-port = <1>; - fsl,port-config = < - (IMX_AUDMUX_V2_PTCR_SYN | - IMX_AUDMUX_V2_PTCR_TFSDIR | - IMX_AUDMUX_V2_PTCR_TFSEL(2) | - IMX_AUDMUX_V2_PTCR_TCLKDIR | - IMX_AUDMUX_V2_PTCR_TCSEL(2)) - IMX_AUDMUX_V2_PDCR_RXDSEL(2) - >; - }; - - aud3 { - fsl,audmux-port = <2>; - fsl,port-config = < - IMX_AUDMUX_V2_PTCR_SYN - IMX_AUDMUX_V2_PDCR_RXDSEL(1) - >; - }; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - status = "disabled"; -}; - -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - status = "disabled"; -}; - -&ecspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - status = "disabled"; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii"; - status = "disabled"; -}; - -&hdmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hdmicec>; - ddc-i2c-bus = <&i2c1>; - status = "disabled"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "disabled"; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - pmic@8 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - compatible = "fsl,pfuze100"; - reg = <0x08>; - - regulators { - sw1a_reg: sw1ab { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw1c_reg: sw1c { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3a_reg: sw3a { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3950000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3b_reg: sw3b { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3950000>; - regulator-boot-on; - regulator-always-on; - }; - - sw4_reg: sw4 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3950000>; - }; - - snvs_reg: vsnvs { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - vgen6_reg: vgen6 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - regulator-boot-on; - }; - }; - }; - - tlv320aic3106: codec@1b { - compatible = "ti,tlv320aic3106"; - reg = <0x1b>; - #sound-dai-cells = <0>; - DRVDD-supply = <®_3p3v>; - AVDD-supply = <®_3p3v>; - IOVDD-supply = <®_3p3v>; - DVDD-supply = <®_3p3v>; - ai3x-ocmv = <0>; - reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>; - }; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "disabled"; -}; - -&iomuxc { - pinctrl_audmux: audmux { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 - MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 - MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 - MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 - /* Audio Clock */ - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 - >; - }; - - pinctrl_bt: bt { - fsl,pins = < - /* Bluetooth enable */ - MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x1b0b1 - /* Bluetooth Slow Clock */ - MX6QDL_PAD_ENET_RXD0__OSC32K_32K_OUT 0x000b0 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1 - /* SPI1 CS0 */ - MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0 - /* SPI1 CS1 */ - MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0 - MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0 - >; - }; - - pinctrl_flexcan2: flexcan2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0 - MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0 - >; - }; - - pinctrl_hdmicec: hdmicecgrp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 - MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_pmic: pmicgrp { - fsl,pins = < - /* PMIC INT */ - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b1 - >; - }; - - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 0x1b0b1 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT4__UART2_RX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_DAT5__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1 - MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 - MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 - /* WL_EN */ - MX6QDL_PAD_SD3_DAT7__GPIO6_IO17 0x17071 - /* WL_IRQ */ - MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x17071 - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1grp100mhz { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170B9 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100B9 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170B9 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170B9 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170B9 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170B9 - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1grp200mhz { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170F9 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100F9 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170F9 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170F9 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170F9 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170F9 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - >; - }; -}; - -&pcie { - fsl,tx-swing-full = <103>; - fsl,tx-swing-low = <103>; - reset-gpio = <&gpio4 11 GPIO_ACTIVE_LOW>; - status = "disabled"; -}; - -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm2>; - status = "disabled"; -}; - -®_arm { - vin-supply = <&sw1a_reg>; -}; - -®_pu { - vin-supply = <&sw1c_reg>; -}; - -®_soc { - vin-supply = <&sw1c_reg>; -}; - -&snvs_poweroff { - status = "okay"; -}; - -&ssi2 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "disabled"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2 &pinctrl_bt>; - uart-has-rtscts; - status = "okay"; - - bluetooth { - compatible = "ti,wl1835-st"; - enable-gpios = <&gpio6 18 GPIO_ACTIVE_HIGH>; - }; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - uart-has-rtscts; - status = "disabled"; -}; - -&usbh1 { - status = "disabled"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "disabled"; -}; - -&usdhc1 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>; - bus-width = <4>; - vmmc-supply = <®_wl18xx_vmmc>; - non-removable; - wakeup-source; - keep-power-in-suspend; - cap-power-off-card; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - wlcore: wlcore@2 { - compatible = "ti,wl1835"; - reg = <2>; - interrupt-parent = <&gpio6>; - interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; - ref-clock-frequency = <38400000>; - }; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - no-1-8-v; - keep-power-in-suspend; - wakeup-source; - status = "disabled"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - non-removable; - keep-power-in-suspend; - wakeup-source; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx6qdl-wandboard-revb1.dtsi b/sys/gnu/dts/arm/imx6qdl-wandboard-revb1.dtsi deleted file mode 100644 index e781a45785e..00000000000 --- a/sys/gnu/dts/arm/imx6qdl-wandboard-revb1.dtsi +++ /dev/null @@ -1,36 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// -// Copyright 2013 Freescale Semiconductor, Inc. -// -// Author: Fabio Estevam - -#include "imx6qdl-wandboard.dtsi" - -&iomuxc { - pinctrl-0 = <&pinctrl_hog>; - - imx6qdl-wandboard { - pinctrl_hog: hoggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* uSDHC1 CD */ - MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x80000000 /* uSDHC3 CD */ - MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x0f0b0 /* WL_REF_ON */ - MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x0f0b0 /* WL_RST_N */ - MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x000b0 /* WL_REG_ON */ - MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 /* WL_HOST_WAKE */ - MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* WL_WAKE */ - MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x80000000 /* RGMII_nRST */ - MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x80000000 /* BT_ON */ - MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x80000000 /* BT_WAKE */ - MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x80000000 /* BT_HOST_WAKE */ - >; - }; - }; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - non-removable; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx6qdl-wandboard-revc1.dtsi b/sys/gnu/dts/arm/imx6qdl-wandboard-revc1.dtsi deleted file mode 100644 index 3874e74703f..00000000000 --- a/sys/gnu/dts/arm/imx6qdl-wandboard-revc1.dtsi +++ /dev/null @@ -1,35 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// -// Copyright 2013 Freescale Semiconductor, Inc. -// -// Author: Fabio Estevam - -#include "imx6qdl-wandboard.dtsi" - -&iomuxc { - pinctrl-0 = <&pinctrl_hog>; - - imx6qdl-wandboard { - pinctrl_hog: hoggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* uSDHC1 CD */ - MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x80000000 /* uSDHC3 CD */ - MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00 0x0f0b0 /* WIFI_ON (reset, active low) */ - MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x000b0 /* WL_REG_ON (unused) */ - MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 /* WL_HOST_WAKE, input */ - MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x0f0b0 /* GPIO5_IO31 (Wifi Power Enable) */ - MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* WL_WAKE (unused) */ - MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x80000000 /* BT_ON */ - MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x80000000 /* BT_WAKE */ - MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x80000000 /* BT_HOST_WAKE */ - MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x80000000 /* RGMII_nRST */ - >; - }; - }; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx6qdl-wandboard-revd1.dtsi b/sys/gnu/dts/arm/imx6qdl-wandboard-revd1.dtsi deleted file mode 100644 index 93909796885..00000000000 --- a/sys/gnu/dts/arm/imx6qdl-wandboard-revd1.dtsi +++ /dev/null @@ -1,195 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// -// Copyright 2013 Freescale Semiconductor, Inc. -// -// Author: Fabio Estevam - -#include "imx6qdl-wandboard.dtsi" - -/ { - reg_eth_phy: regulator-eth-phy { - compatible = "regulator-fixed"; - regulator-name = "ETH_PHY"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio7 13 GPIO_ACTIVE_LOW>; - }; -}; - -&hdmi { - ddc-i2c-bus = <&i2c2>; - status = "okay"; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - pmic: pfuze100@8 { - compatible = "fsl,pfuze100"; - reg = <0x08>; - - regulators { - sw1a_reg: sw1ab { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw1c_reg: sw1c { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw3a_reg: sw3a { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3b_reg: sw3b { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - sw4_reg: sw4 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - }; - - swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - }; - - snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - vgen1_reg: vgen1 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen2_reg: vgen2 { - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - regulator-always-on; - }; - - vgen3_reg: vgen3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen4_reg: vgen4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen5_reg: vgen5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen6_reg: vgen6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; -}; - -&fec { - phy-supply = <®_eth_phy>; - status = "okay"; -}; - -&iomuxc { - pinctrl-0 = <&pinctrl_hog>; - - imx6qdl-wandboard { - pinctrl_hog: hoggrp { - fsl,pins = < - MX6QDL_PAD_EIM_D22__USB_OTG_PWR 0x80000000 /* USB Power Enable */ - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* USDHC1 CD */ - MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x80000000 /* uSDHC3 CD */ - MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1f0b1 /* RGMII PHY reset */ - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_spdif: spdifgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x1b0b0 - >; - }; - }; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - bus-width = <4>; - no-1-8-v; - non-removable; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx6qdl-wandboard.dtsi b/sys/gnu/dts/arm/imx6qdl-wandboard.dtsi deleted file mode 100644 index c070893c509..00000000000 --- a/sys/gnu/dts/arm/imx6qdl-wandboard.dtsi +++ /dev/null @@ -1,358 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2013 Freescale Semiconductor, Inc. - * - * Author: Fabio Estevam - */ - -#include - -/ { - chosen { - stdout-path = &uart1; - }; - - sound { - compatible = "fsl,imx6-wandboard-sgtl5000", - "fsl,imx-audio-sgtl5000"; - model = "imx6-wandboard-sgtl5000"; - ssi-controller = <&ssi1>; - audio-codec = <&codec>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - mux-int-port = <1>; - mux-ext-port = <3>; - }; - - sound-spdif { - compatible = "fsl,imx-audio-spdif"; - model = "imx-spdif"; - spdif-controller = <&spdif>; - spdif-out; - }; - - reg_1p5v: regulator-1p5v { - compatible = "regulator-fixed"; - regulator-name = "1P5V"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - }; - - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-name = "1P8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - reg_2p8v: regulator-2p8v { - compatible = "regulator-fixed"; - regulator-name = "2P8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - reg_2p5v: regulator-2p5v { - compatible = "regulator-fixed"; - regulator-name = "2P5V"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_usb_otg_vbus: regulator-usbotgvbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotgvbus>; - gpio = <&gpio3 22 GPIO_ACTIVE_LOW>; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c1>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - codec: sgtl5000@a { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mclk>; - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - clocks = <&clks IMX6QDL_CLK_CKO>; - VDDA-supply = <®_2p5v>; - VDDIO-supply = <®_3p3v>; - lrclk-strength = <3>; - }; - - camera@3c { - compatible = "ovti,ov5645"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ov5645>; - reg = <0x3c>; - clocks = <&clks IMX6QDL_CLK_CKO2>; - clock-names = "xclk"; - clock-frequency = <24000000>; - vdddo-supply = <®_1p8v>; - vdda-supply = <®_2p8v>; - vddd-supply = <®_1p5v>; - enable-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>; - - port { - ov5645_to_mipi_csi2: endpoint { - remote-endpoint = <&mipi_csi2_in>; - clock-lanes = <0>; - data-lanes = <1 2>; - }; - }; - }; -}; - -&iomuxc { - pinctrl-names = "default"; - - imx6qdl-wandboard { - - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 - MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 - MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 - MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_mclk: mclkgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 - >; - }; - - pinctrl_ov5645: ov5645grp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__CCM_CLKO2 0x000b0 - MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0 - MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 - >; - }; - - pinctrl_spdif: spdifgrp { - fsl,pins = < - MX6QDL_PAD_ENET_RXD0__SPDIF_OUT 0x1b0b0 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 - MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - >; - }; - - pinctrl_usbotgvbus: usbotgvbusgrp { - fsl,pins = < - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x130b0 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - >; - }; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy>; - phy-reset-gpios = <&gpio3 29 GPIO_ACTIVE_LOW>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy: ethernet-phy@1 { - reg = <1>; - }; - }; -}; - -&mipi_csi { - status = "okay"; - - port@0 { - reg = <0>; - - mipi_csi2_in: endpoint { - remote-endpoint = <&ov5645_to_mipi_csi2>; - clock-lanes = <0>; - data-lanes = <1 2>; - }; - }; -}; - -&spdif { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spdif>; - status = "okay"; -}; - -&ssi1 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - uart-has-rtscts; - status = "okay"; -}; - -&usbh1 { - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - dr_mode = "otg"; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - cd-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - cd-gpios = <&gpio3 9 GPIO_ACTIVE_LOW>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx6qdl-zii-rdu2.dtsi b/sys/gnu/dts/arm/imx6qdl-zii-rdu2.dtsi deleted file mode 100644 index 0075637f9b0..00000000000 --- a/sys/gnu/dts/arm/imx6qdl-zii-rdu2.dtsi +++ /dev/null @@ -1,1133 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2016-2017 Zodiac Inflight Innovations - */ - -#include -#include - -/ { - chosen { - stdout-path = &uart1; - }; - - aliases { - mdio-gpio0 = &mdio1; - rtc0 = &ds1341; - }; - - mdio1: mdio { - compatible = "virtual,mdio-gpio"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mdio1>; - gpios = <&gpio6 5 GPIO_ACTIVE_HIGH - &gpio6 4 GPIO_ACTIVE_HIGH>; - - phy: ethernet-phy@0 { - pinctrl-0 = <&pinctrl_rmii_phy_irq>; - pinctrl-names = "default"; - reg = <0>; - interrupt-parent = <&gpio3>; - interrupts = <30 IRQ_TYPE_LEVEL_LOW>; - }; - }; - - reg_28p0v: regulator-28p0v { - compatible = "regulator-fixed"; - regulator-name = "28V_IN"; - regulator-min-microvolt = <28000000>; - regulator-max-microvolt = <28000000>; - regulator-always-on; - }; - - reg_12p0v: regulator-12p0v { - compatible = "regulator-fixed"; - vin-supply = <®_28p0v>; - regulator-name = "12V_MAIN"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-always-on; - }; - - reg_5p0v_main: regulator-5p0v-main { - compatible = "regulator-fixed"; - vin-supply = <®_12p0v>; - regulator-name = "5V_MAIN"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - reg_3p3v_pmic: regulator-3p3v-pmic { - compatible = "regulator-fixed"; - vin-supply = <®_12p0v>; - regulator-name = "PMIC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - vin-supply = <®_3p3v_pmic>; - regulator-name = "GEN_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_3p3v_sd: regulator-3p3v-sd { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_3p3v_sd>; - vin-supply = <®_3p3v>; - regulator-name = "3V3_SD"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio7 8 GPIO_ACTIVE_HIGH>; - startup-delay-us = <1000>; - enable-active-high; - regulator-always-on; - }; - - reg_3p3v_display: regulator-3p3v-display { - compatible = "regulator-fixed"; - vin-supply = <®_12p0v>; - regulator-name = "3V3_DISPLAY"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_3p3v_ssd: regulator-3p3v-ssd { - compatible = "regulator-fixed"; - vin-supply = <®_12p0v>; - regulator-name = "3V3_SSD"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - sound1 { - compatible = "simple-audio-card"; - simple-audio-card,name = "Front"; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&sound1_codec>; - simple-audio-card,frame-master = <&sound1_codec>; - simple-audio-card,widgets = - "Headphone", "Headphone Jack"; - simple-audio-card,routing = - "Headphone Jack", "HPLEFT", - "Headphone Jack", "HPRIGHT", - "LEFTIN", "HPL", - "RIGHTIN", "HPR"; - simple-audio-card,aux-devs = <&hpa1>; - - sound1_cpu: simple-audio-card,cpu { - sound-dai = <&ssi2>; - }; - - sound1_codec: simple-audio-card,codec { - sound-dai = <&codec1>; - clocks = <&cs2000>; - }; - }; - - sound2 { - compatible = "simple-audio-card"; - simple-audio-card,name = "Back"; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&sound2_codec>; - simple-audio-card,frame-master = <&sound2_codec>; - simple-audio-card,widgets = - "Headphone", "Headphone Jack"; - simple-audio-card,routing = - "Headphone Jack", "HPLEFT", - "Headphone Jack", "HPRIGHT", - "LEFTIN", "HPL", - "RIGHTIN", "HPR"; - simple-audio-card,aux-devs = <&hpa2>; - - sound2_cpu: simple-audio-card,cpu { - sound-dai = <&ssi1>; - }; - - sound2_codec: simple-audio-card,codec { - sound-dai = <&codec2>; - clocks = <&cs2000>; - }; - }; - - panel { - power-supply = <®_3p3v_display>; - backlight = <&sp_backlight>; - status = "disabled"; - - port { - panel_in: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - }; - - disp0: disp0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx-parallel-display"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_disp0>; - status = "disabled"; - - port@0 { - reg = <0>; - - disp0_in_0: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - - port@1 { - reg = <1>; - - disp0_out: endpoint { - remote-endpoint = <&tc358767_in>; - }; - }; - }; - - cs2000_ref: cs2000-ref { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24576000>; - }; - - cs2000_in_dummy: cs2000-in-dummy { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - edp_refclk: edp-refclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <19200000>; - }; -}; - -&cpu0 { - fsl,soc-operating-points = < - /* ARM kHz SOC-PU uV */ - 1200000 1300000 - 996000 1275000 - 852000 1275000 - 792000 1200000 - 396000 1200000 - >; -}; - -®_arm { - vin-supply = <&sw1a_reg>; -}; - -®_pu { - vin-supply = <&sw1c_reg>; -}; - -®_soc { - vin-supply = <&sw1c_reg>; -}; - -&ldb { - lvds-channel@0 { - port@4 { - reg = <4>; - - lvds0_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - uart-has-rtscts; - linux,rs485-enabled-at-boot-time; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; - - rave-sp { - compatible = "zii,rave-sp-rdu2"; - current-speed = <1000000>; - #address-cells = <1>; - #size-cells = <1>; - - watchdog { - compatible = "zii,rave-sp-watchdog"; - }; - - sp_backlight: backlight { - compatible = "zii,rave-sp-backlight"; - }; - - pwrbutton { - compatible = "zii,rave-sp-pwrbutton"; - }; - - eeprom@a3 { - compatible = "zii,rave-sp-eeprom"; - reg = <0xa3 0x4000>; - #address-cells = <1>; - #size-cells = <1>; - zii,eeprom-name = "dds-eeprom"; - }; - - eeprom@a4 { - compatible = "zii,rave-sp-eeprom"; - reg = <0xa4 0x4000>; - #address-cells = <1>; - #size-cells = <1>; - zii,eeprom-name = "main-eeprom"; - }; - }; -}; - -&ecspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>; - status = "okay"; - - flash@0 { - compatible = "st,m25p128", "jedec,spi-nor"; - spi-max-frequency = <20000000>; - reg = <0>; - }; -}; - -&gpio3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio3_hog>; - - usb-emulation { - gpio-hog; - gpios = <19 GPIO_ACTIVE_HIGH>; - output-low; - line-name = "usb-emulation"; - }; - - usb-mode1 { - gpio-hog; - gpios = <20 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "usb-mode1"; - }; - - usb-pwr { - gpio-hog; - gpios = <22 GPIO_ACTIVE_LOW>; - output-high; - line-name = "usb-pwr-ctrl-en-n"; - }; - - usb-mode2 { - gpio-hog; - gpios = <23 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "usb-mode2"; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - clock-frequency = <100000>; - status = "okay"; - - codec2: codec@18 { - compatible = "ti,tlv320dac3100"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_codec2>; - reg = <0x18>; - #sound-dai-cells = <0>; - HPVDD-supply = <®_3p3v>; - SPRVDD-supply = <®_3p3v>; - SPLVDD-supply = <®_3p3v>; - AVDD-supply = <®_3p3v>; - IOVDD-supply = <®_3p3v>; - DVDD-supply = <&vgen4_reg>; - reset-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; - }; - - accel@1c { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_accel>; - compatible = "fsl,mma8451"; - reg = <0x1c>; - interrupt-parent = <&gpio1>; - interrupt-names = "INT2"; - interrupts = <20 IRQ_TYPE_LEVEL_LOW>; - vdd-supply = <®_3p3v>; - vddio-supply = <®_3p3v>; - }; - - hpa2: amp@60 { - compatible = "ti,tpa6130a2"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_tpa2>; - reg = <0x60>; - power-gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; - Vdd-supply = <®_5p0v_main>; - }; - - edp-bridge@68 { - compatible = "toshiba,tc358767"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_tc358767>; - reg = <0x68>; - shutdown-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; - clock-names = "ref"; - clocks = <&edp_refclk>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - - tc358767_in: endpoint { - remote-endpoint = <&disp0_out>; - }; - }; - }; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - clock-frequency = <100000>; - status = "okay"; - - pmic@8 { - compatible = "fsl,pfuze100"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pfuze100_irq>; - reg = <0x08>; - interrupt-parent = <&gpio7>; - interrupts = <13 IRQ_TYPE_LEVEL_LOW>; - - regulators { - sw1a_reg: sw1ab { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw1c_reg: sw1c { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3a_reg: sw3a { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3b_reg: sw3b { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - regulator-always-on; - }; - - sw4_reg: sw4 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - vgen2_reg: vgen2 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - }; - - vgen4_reg: vgen4 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vgen5_reg: vgen5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - vgen6_reg: vgen6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - }; - }; - - watchdog@38 { - compatible = "zii,rave-wdt"; - reg = <0x38>; - }; - - temp-sense@48 { - compatible = "national,lm75"; - reg = <0x48>; - }; - - cs2000: clkgen@4e { - compatible = "cirrus,cs2000-cp"; - reg = <0x4e>; - #clock-cells = <0>; - clock-names = "clk_in", "ref_clk"; - clocks = <&cs2000_in_dummy>, <&cs2000_ref>; - assigned-clocks = <&cs2000>; - assigned-clock-rates = <24000000>; - }; - - eeprom@54 { - compatible = "atmel,24c128"; - reg = <0x54>; - }; - - ds1341: rtc@68 { - compatible = "dallas,ds1341"; - reg = <0x68>; - }; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - clock-frequency = <400000>; - status = "okay"; - - codec1: codec@18 { - compatible = "ti,tlv320dac3100"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_codec1>; - reg = <0x18>; - #sound-dai-cells = <0>; - HPVDD-supply = <®_3p3v>; - SPRVDD-supply = <®_3p3v>; - SPLVDD-supply = <®_3p3v>; - AVDD-supply = <®_3p3v>; - IOVDD-supply = <®_3p3v>; - DVDD-supply = <&vgen4_reg>; - reset-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; - }; - - touchscreen@20 { - compatible = "syna,rmi4-i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ts>; - reg = <0x20>; - interrupt-parent = <&gpio1>; - interrupts = <8 IRQ_TYPE_LEVEL_LOW>; - vdd-supply = <®_5p0v_main>; - vio-supply = <®_3p3v>; - - #address-cells = <1>; - #size-cells = <0>; - - rmi4-f01@1 { - reg = <0x1>; - syna,nosleep-mode = <2>; - }; - - rmi4-f11@11 { - reg = <0x11>; - touchscreen-inverted-x; - touchscreen-swapped-x-y; - syna,sensor-type = <1>; - }; - - rmi4-f12@12 { - reg = <0x12>; - touchscreen-inverted-x; - touchscreen-swapped-x-y; - syna,sensor-type = <1>; - }; - }; - - touchscreen@2a { - compatible = "eeti,exc3000"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ts>; - reg = <0x2a>; - interrupt-parent = <&gpio1>; - interrupts = <8 IRQ_TYPE_LEVEL_LOW>; - touchscreen-inverted-x; - touchscreen-swapped-x-y; - status = "disabled"; - }; - - reg_5p0v_user_usb: charger@32 { - compatible = "microchip,ucs1002"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ucs1002_pins>; - reg = <0x32>; - interrupts-extended = <&gpio5 2 IRQ_TYPE_EDGE_BOTH>, - <&gpio3 21 IRQ_TYPE_EDGE_BOTH>; - interrupt-names = "a_det", "alert"; - }; - - hpa1: amp@60 { - compatible = "ti,tpa6130a2"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_tpa1>; - reg = <0x60>; - power-gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>; - Vdd-supply = <®_5p0v_main>; - }; -}; - -&ipu1_di0_disp0 { - remote-endpoint = <&disp0_in_0>; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>; - status = "okay"; - - host@0 { - reg = <0 0 0 0 0>; - - #address-cells = <3>; - #size-cells = <2>; - - i210: i210@0 { - reg = <0 0 0 0 0>; - }; - }; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - bus-width = <4>; - cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; - disable-wp; - vmmc-supply = <®_3p3v_sd>; - vqmmc-supply = <®_3p3v>; - no-1-8-v; - no-sdio; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - bus-width = <4>; - cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; - disable-wp; - vmmc-supply = <®_3p3v_sd>; - vqmmc-supply = <®_3p3v>; - no-1-8-v; - no-sdio; - status = "okay"; -}; - -&usdhc4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc4>; - bus-width = <8>; - vmmc-supply = <®_3p3v>; - vqmmc-supply = <®_3p3v>; - no-1-8-v; - non-removable; - no-sdio; - no-sd; - status = "okay"; -}; - -&sata { - target-supply = <®_3p3v_ssd>; - status = "okay"; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rmii"; - phy-handle = <&phy>; - phy-reset-gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; - phy-reset-duration = <100>; - phy-supply = <®_3p3v>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - switch: switch@0 { - compatible = "marvell,mv88e6085"; - pinctrl-0 = <&pinctrl_switch_irq>; - pinctrl-names = "default"; - reg = <0>; - dsa,member = <0 0>; - eeprom-length = <512>; - interrupt-parent = <&gpio6>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells = <2>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "gigabit_proc"; - phy-handle = <&switchphy0>; - }; - - port@1 { - reg = <1>; - label = "netaux"; - phy-handle = <&switchphy1>; - }; - - port@2 { - reg = <2>; - label = "cpu"; - ethernet = <&fec>; - - fixed-link { - speed = <100>; - full-duplex; - }; - }; - - port@3 { - reg = <3>; - label = "netright"; - phy-handle = <&switchphy3>; - }; - - port@4 { - reg = <4>; - label = "netleft"; - phy-handle = <&switchphy4>; - }; - }; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - switchphy0: switchphy@0 { - reg = <0>; - interrupt-parent = <&switch>; - interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; - }; - - switchphy1: switchphy@1 { - reg = <1>; - interrupt-parent = <&switch>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; - }; - - switchphy2: switchphy@2 { - reg = <2>; - interrupt-parent = <&switch>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; - }; - - switchphy3: switchphy@3 { - reg = <3>; - interrupt-parent = <&switch>; - interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; - }; - - switchphy4: switchphy@4 { - reg = <4>; - interrupt-parent = <&switch>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - }; - }; -}; - -&usbh1 { - vbus-supply = <®_5p0v_main>; - disable-over-current; - maximum-speed = "full-speed"; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_5p0v_user_usb>; - disable-over-current; - dr_mode = "host"; - status = "okay"; -}; - -&snvs_rtc { - status = "disabled"; -}; - -&ssi1 { - status = "okay"; -}; - -&ssi2 { - status = "okay"; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; - - ssi1 { - fsl,audmux-port = <0>; - fsl,port-config = < - (IMX_AUDMUX_V2_PTCR_SYN | - IMX_AUDMUX_V2_PTCR_TFSEL(2) | - IMX_AUDMUX_V2_PTCR_TCSEL(2) | - IMX_AUDMUX_V2_PTCR_TFSDIR | - IMX_AUDMUX_V2_PTCR_TCLKDIR) - IMX_AUDMUX_V2_PDCR_RXDSEL(2) - >; - }; - - aud3 { - fsl,audmux-port = <2>; - fsl,port-config = < - IMX_AUDMUX_V2_PTCR_SYN - IMX_AUDMUX_V2_PDCR_RXDSEL(0) - >; - }; - - ssi2 { - fsl,audmux-port = <1>; - fsl,port-config = < - (IMX_AUDMUX_V2_PTCR_SYN | - IMX_AUDMUX_V2_PTCR_TFSEL(4) | - IMX_AUDMUX_V2_PTCR_TCSEL(4) | - IMX_AUDMUX_V2_PTCR_TFSDIR | - IMX_AUDMUX_V2_PTCR_TCLKDIR) - IMX_AUDMUX_V2_PDCR_RXDSEL(4) - >; - }; - - aud5 { - fsl,audmux-port = <4>; - fsl,port-config = < - IMX_AUDMUX_V2_PTCR_SYN - IMX_AUDMUX_V2_PDCR_RXDSEL(1) - >; - }; -}; - -&wdog1 { - status = "disabled"; -}; - -&iomuxc { - pinctrl_accel: accelgrp { - fsl,pins = < - MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x4001b000 - >; - }; - - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0 - MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x130b0 - MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0 - MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 - MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x130b0 - MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 - >; - }; - - pinctrl_codec1: dac1grp { - fsl,pins = < - MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x40000038 - >; - }; - - pinctrl_codec2: dac2grp { - fsl,pins = < - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x40000038 - >; - }; - - pinctrl_disp0: disp0grp { - fsl,pins = < - MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x100f9 - MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x100f9 - MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x100f9 - MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x100f9 - MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x100f9 - MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x100f9 - MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x100f9 - MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x100f9 - MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x100f9 - MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x100f9 - MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x100f9 - MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x100f9 - MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x100f9 - MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x100f9 - MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x100f9 - MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x100f9 - MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x100f9 - MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x100f9 - MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x100f9 - MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x100f9 - MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x100f9 - MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x100f9 - MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x100f9 - MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x100f9 - MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x100f9 - MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x100f9 - MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x100f9 - MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x100f9 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 - MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b1 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x000b1 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b1 - MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x100f5 - MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x100f5 - MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x100c0 - MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x100c0 - MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x100f5 - MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x100f5 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x40010040 - MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x100b0 - MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1b0b0 - >; - }; - - pinctrl_gpio3_hog: gpio3hoggrp { - fsl,pins = < - MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b0 - MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b0 - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 - MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b0b0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 - MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_mdio1: bitbangmdiogrp { - fsl,pins = < - /* Bitbang MDIO for DEB Switch */ - MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05 0x4001b030 - MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04 0x40018830 - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = < - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x10038 - >; - }; - - pinctrl_pfuze100_irq: pfuze100grp { - fsl,pins = < - MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x40010000 - >; - }; - - pinctrl_reg_3p3v_sd: mmcsupply1grp { - fsl,pins = < - MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x858 - >; - }; - - pinctrl_rmii_phy_irq: phygrp { - fsl,pins = < - MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x40010000 - >; - }; - - pinctrl_switch_irq: switchgrp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x4001b000 - >; - }; - - pinctrl_tc358767: tc358767grp { - fsl,pins = < - MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x10 - >; - }; - - pinctrl_tpa1: tpa6130-1grp { - fsl,pins = < - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x40000038 - >; - }; - - pinctrl_tpa2: tpa6130-2grp { - fsl,pins = < - MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x40000038 - >; - }; - - pinctrl_ts: tsgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 - MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_ucs1002_pins: ucs1002grp { - fsl,pins = < - MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b0 - MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x1b0b0 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x10059 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10069 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 - MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x40010040 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x10059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10069 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x40010040 - - >; - }; - - pinctrl_usdhc4: usdhc4grp { - fsl,pins = < - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 - MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 - MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 - MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 - MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 - MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x1b0b1 - >; - }; -}; diff --git a/sys/gnu/dts/arm/imx6qdl.dtsi b/sys/gnu/dts/arm/imx6qdl.dtsi deleted file mode 100644 index e6b4b8525f9..00000000000 --- a/sys/gnu/dts/arm/imx6qdl.dtsi +++ /dev/null @@ -1,1367 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// -// Copyright 2011 Freescale Semiconductor, Inc. -// Copyright 2011 Linaro Ltd. - -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - /* - * The decompressor and also some bootloaders rely on a - * pre-existing /chosen node to be available to insert the - * command line and merge other ATAGS info. - */ - chosen {}; - - aliases { - ethernet0 = &fec; - can0 = &can1; - can1 = &can2; - gpio0 = &gpio1; - gpio1 = &gpio2; - gpio2 = &gpio3; - gpio3 = &gpio4; - gpio4 = &gpio5; - gpio5 = &gpio6; - gpio6 = &gpio7; - i2c0 = &i2c1; - i2c1 = &i2c2; - i2c2 = &i2c3; - ipu0 = &ipu1; - mmc0 = &usdhc1; - mmc1 = &usdhc2; - mmc2 = &usdhc3; - mmc3 = &usdhc4; - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - serial3 = &uart4; - serial4 = &uart5; - spi0 = &ecspi1; - spi1 = &ecspi2; - spi2 = &ecspi3; - spi3 = &ecspi4; - usbphy0 = &usbphy1; - usbphy1 = &usbphy2; - }; - - clocks { - ckil { - compatible = "fsl,imx-ckil", "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - - ckih1 { - compatible = "fsl,imx-ckih1", "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - osc { - compatible = "fsl,imx-osc", "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - }; - }; - - tempmon: tempmon { - compatible = "fsl,imx6q-tempmon"; - interrupt-parent = <&gpc>; - interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>; - fsl,tempmon = <&anatop>; - fsl,tempmon-data = <&ocotp>; - clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>; - #thermal-sensor-cells = <0>; - }; - - ldb: ldb { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb"; - gpr = <&gpr>; - status = "disabled"; - - lvds-channel@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - status = "disabled"; - - port@0 { - reg = <0>; - - lvds0_mux_0: endpoint { - remote-endpoint = <&ipu1_di0_lvds0>; - }; - }; - - port@1 { - reg = <1>; - - lvds0_mux_1: endpoint { - remote-endpoint = <&ipu1_di1_lvds0>; - }; - }; - }; - - lvds-channel@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - status = "disabled"; - - port@0 { - reg = <0>; - - lvds1_mux_0: endpoint { - remote-endpoint = <&ipu1_di0_lvds1>; - }; - }; - - port@1 { - reg = <1>; - - lvds1_mux_1: endpoint { - remote-endpoint = <&ipu1_di1_lvds1>; - }; - }; - }; - }; - - pmu: pmu { - compatible = "arm,cortex-a9-pmu"; - interrupt-parent = <&gpc>; - interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>; - }; - - usbphynop1: usbphynop1 { - compatible = "usb-nop-xceiv"; - #phy-cells = <0>; - }; - - usbphynop2: usbphynop2 { - compatible = "usb-nop-xceiv"; - #phy-cells = <0>; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&gpc>; - ranges; - - dma_apbh: dma-apbh@110000 { - compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh"; - reg = <0x00110000 0x2000>; - interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>, - <0 13 IRQ_TYPE_LEVEL_HIGH>, - <0 13 IRQ_TYPE_LEVEL_HIGH>, - <0 13 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; - #dma-cells = <1>; - dma-channels = <4>; - clocks = <&clks IMX6QDL_CLK_APBH_DMA>; - }; - - gpmi: gpmi-nand@112000 { - compatible = "fsl,imx6q-gpmi-nand"; - reg = <0x00112000 0x2000>, <0x00114000 0x2000>; - reg-names = "gpmi-nand", "bch"; - interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "bch"; - clocks = <&clks IMX6QDL_CLK_GPMI_IO>, - <&clks IMX6QDL_CLK_GPMI_APB>, - <&clks IMX6QDL_CLK_GPMI_BCH>, - <&clks IMX6QDL_CLK_GPMI_BCH_APB>, - <&clks IMX6QDL_CLK_PER1_BCH>; - clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch", - "gpmi_bch_apb", "per1_bch"; - dmas = <&dma_apbh 0>; - dma-names = "rx-tx"; - status = "disabled"; - }; - - hdmi: hdmi@120000 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x00120000 0x9000>; - interrupts = <0 115 0x04>; - gpr = <&gpr>; - clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>, - <&clks IMX6QDL_CLK_HDMI_ISFR>; - clock-names = "iahb", "isfr"; - status = "disabled"; - - port@0 { - reg = <0>; - - hdmi_mux_0: endpoint { - remote-endpoint = <&ipu1_di0_hdmi>; - }; - }; - - port@1 { - reg = <1>; - - hdmi_mux_1: endpoint { - remote-endpoint = <&ipu1_di1_hdmi>; - }; - }; - }; - - gpu_3d: gpu@130000 { - compatible = "vivante,gc"; - reg = <0x00130000 0x4000>; - interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_GPU3D_AXI>, - <&clks IMX6QDL_CLK_GPU3D_CORE>, - <&clks IMX6QDL_CLK_GPU3D_SHADER>; - clock-names = "bus", "core", "shader"; - power-domains = <&pd_pu>; - #cooling-cells = <2>; - }; - - gpu_2d: gpu@134000 { - compatible = "vivante,gc"; - reg = <0x00134000 0x4000>; - interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_GPU2D_AXI>, - <&clks IMX6QDL_CLK_GPU2D_CORE>; - clock-names = "bus", "core"; - power-domains = <&pd_pu>; - #cooling-cells = <2>; - }; - - timer@a00600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0x00a00600 0x20>; - interrupts = <1 13 0xf01>; - interrupt-parent = <&intc>; - clocks = <&clks IMX6QDL_CLK_TWD>; - }; - - intc: interrupt-controller@a01000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x00a01000 0x1000>, - <0x00a00100 0x100>; - interrupt-parent = <&intc>; - }; - - L2: l2-cache@a02000 { - compatible = "arm,pl310-cache"; - reg = <0x00a02000 0x1000>; - interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>; - cache-unified; - cache-level = <2>; - arm,tag-latency = <4 2 3>; - arm,data-latency = <4 2 3>; - arm,shared-override; - }; - - pcie: pcie@1ffc000 { - compatible = "fsl,imx6q-pcie", "snps,dw-pcie"; - reg = <0x01ffc000 0x04000>, - <0x01f00000 0x80000>; - reg-names = "dbi", "config"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - bus-range = <0x00 0xff>; - ranges = <0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */ - 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */ - num-lanes = <1>; - num-viewport = <4>; - interrupts = ; - interrupt-names = "msi"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_PCIE_AXI>, - <&clks IMX6QDL_CLK_LVDS1_GATE>, - <&clks IMX6QDL_CLK_PCIE_REF_125M>; - clock-names = "pcie", "pcie_bus", "pcie_phy"; - status = "disabled"; - }; - - aips-bus@2000000 { /* AIPS1 */ - compatible = "fsl,aips-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x02000000 0x100000>; - ranges; - - spba-bus@2000000 { - compatible = "fsl,spba-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x02000000 0x40000>; - ranges; - - spdif: spdif@2004000 { - compatible = "fsl,imx35-spdif"; - reg = <0x02004000 0x4000>; - interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&sdma 14 18 0>, - <&sdma 15 18 0>; - dma-names = "rx", "tx"; - clocks = <&clks IMX6QDL_CLK_SPDIF_GCLK>, <&clks IMX6QDL_CLK_OSC>, - <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_ASRC>, - <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_ESAI_EXTAL>, - <&clks IMX6QDL_CLK_IPG>, <&clks IMX6QDL_CLK_DUMMY>, - <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_SPBA>; - clock-names = "core", "rxtx0", - "rxtx1", "rxtx2", - "rxtx3", "rxtx4", - "rxtx5", "rxtx6", - "rxtx7", "spba"; - status = "disabled"; - }; - - ecspi1: spi@2008000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; - reg = <0x02008000 0x4000>; - interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_ECSPI1>, - <&clks IMX6QDL_CLK_ECSPI1>; - clock-names = "ipg", "per"; - dmas = <&sdma 3 8 1>, <&sdma 4 8 2>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - ecspi2: spi@200c000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; - reg = <0x0200c000 0x4000>; - interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_ECSPI2>, - <&clks IMX6QDL_CLK_ECSPI2>; - clock-names = "ipg", "per"; - dmas = <&sdma 5 8 1>, <&sdma 6 8 2>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - ecspi3: spi@2010000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; - reg = <0x02010000 0x4000>; - interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_ECSPI3>, - <&clks IMX6QDL_CLK_ECSPI3>; - clock-names = "ipg", "per"; - dmas = <&sdma 7 8 1>, <&sdma 8 8 2>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - ecspi4: spi@2014000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; - reg = <0x02014000 0x4000>; - interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_ECSPI4>, - <&clks IMX6QDL_CLK_ECSPI4>; - clock-names = "ipg", "per"; - dmas = <&sdma 9 8 1>, <&sdma 10 8 2>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart1: serial@2020000 { - compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; - reg = <0x02020000 0x4000>; - interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_UART_IPG>, - <&clks IMX6QDL_CLK_UART_SERIAL>; - clock-names = "ipg", "per"; - dmas = <&sdma 25 4 0>, <&sdma 26 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - esai: esai@2024000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx35-esai"; - reg = <0x02024000 0x4000>; - interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_ESAI_IPG>, - <&clks IMX6QDL_CLK_ESAI_MEM>, - <&clks IMX6QDL_CLK_ESAI_EXTAL>, - <&clks IMX6QDL_CLK_ESAI_IPG>, - <&clks IMX6QDL_CLK_SPBA>; - clock-names = "core", "mem", "extal", "fsys", "spba"; - dmas = <&sdma 23 21 0>, <&sdma 24 21 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - ssi1: ssi@2028000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx6q-ssi", - "fsl,imx51-ssi"; - reg = <0x02028000 0x4000>; - interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_SSI1_IPG>, - <&clks IMX6QDL_CLK_SSI1>; - clock-names = "ipg", "baud"; - dmas = <&sdma 37 1 0>, - <&sdma 38 1 0>; - dma-names = "rx", "tx"; - fsl,fifo-depth = <15>; - status = "disabled"; - }; - - ssi2: ssi@202c000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx6q-ssi", - "fsl,imx51-ssi"; - reg = <0x0202c000 0x4000>; - interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_SSI2_IPG>, - <&clks IMX6QDL_CLK_SSI2>; - clock-names = "ipg", "baud"; - dmas = <&sdma 41 1 0>, - <&sdma 42 1 0>; - dma-names = "rx", "tx"; - fsl,fifo-depth = <15>; - status = "disabled"; - }; - - ssi3: ssi@2030000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx6q-ssi", - "fsl,imx51-ssi"; - reg = <0x02030000 0x4000>; - interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_SSI3_IPG>, - <&clks IMX6QDL_CLK_SSI3>; - clock-names = "ipg", "baud"; - dmas = <&sdma 45 1 0>, - <&sdma 46 1 0>; - dma-names = "rx", "tx"; - fsl,fifo-depth = <15>; - status = "disabled"; - }; - - asrc: asrc@2034000 { - compatible = "fsl,imx53-asrc"; - reg = <0x02034000 0x4000>; - interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_ASRC_IPG>, - <&clks IMX6QDL_CLK_ASRC_MEM>, <&clks 0>, - <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, - <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, - <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, - <&clks IMX6QDL_CLK_ASRC>, <&clks 0>, <&clks 0>, - <&clks IMX6QDL_CLK_SPBA>; - clock-names = "mem", "ipg", "asrck_0", - "asrck_1", "asrck_2", "asrck_3", "asrck_4", - "asrck_5", "asrck_6", "asrck_7", "asrck_8", - "asrck_9", "asrck_a", "asrck_b", "asrck_c", - "asrck_d", "asrck_e", "asrck_f", "spba"; - dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>, - <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>; - dma-names = "rxa", "rxb", "rxc", - "txa", "txb", "txc"; - fsl,asrc-rate = <48000>; - fsl,asrc-width = <16>; - status = "okay"; - }; - - spba@203c000 { - reg = <0x0203c000 0x4000>; - }; - }; - - vpu: vpu@2040000 { - compatible = "cnm,coda960"; - reg = <0x02040000 0x3c000>; - interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>, - <0 3 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "bit", "jpeg"; - clocks = <&clks IMX6QDL_CLK_VPU_AXI>, - <&clks IMX6QDL_CLK_MMDC_CH0_AXI>; - clock-names = "per", "ahb"; - power-domains = <&pd_pu>; - resets = <&src 1>; - iram = <&ocram>; - }; - - aipstz@207c000 { /* AIPSTZ1 */ - reg = <0x0207c000 0x4000>; - }; - - pwm1: pwm@2080000 { - #pwm-cells = <2>; - compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; - reg = <0x02080000 0x4000>; - interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_IPG>, - <&clks IMX6QDL_CLK_PWM1>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - pwm2: pwm@2084000 { - #pwm-cells = <2>; - compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; - reg = <0x02084000 0x4000>; - interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_IPG>, - <&clks IMX6QDL_CLK_PWM2>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - pwm3: pwm@2088000 { - #pwm-cells = <2>; - compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; - reg = <0x02088000 0x4000>; - interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_IPG>, - <&clks IMX6QDL_CLK_PWM3>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - pwm4: pwm@208c000 { - #pwm-cells = <2>; - compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; - reg = <0x0208c000 0x4000>; - interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_IPG>, - <&clks IMX6QDL_CLK_PWM4>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - can1: flexcan@2090000 { - compatible = "fsl,imx6q-flexcan"; - reg = <0x02090000 0x4000>; - interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_CAN1_IPG>, - <&clks IMX6QDL_CLK_CAN1_SERIAL>; - clock-names = "ipg", "per"; - fsl,stop-mode = <&gpr 0x34 28 0x10 17>; - status = "disabled"; - }; - - can2: flexcan@2094000 { - compatible = "fsl,imx6q-flexcan"; - reg = <0x02094000 0x4000>; - interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_CAN2_IPG>, - <&clks IMX6QDL_CLK_CAN2_SERIAL>; - clock-names = "ipg", "per"; - fsl,stop-mode = <&gpr 0x34 29 0x10 18>; - status = "disabled"; - }; - - gpt: gpt@2098000 { - compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt"; - reg = <0x02098000 0x4000>; - interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_GPT_IPG>, - <&clks IMX6QDL_CLK_GPT_IPG_PER>, - <&clks IMX6QDL_CLK_GPT_3M>; - clock-names = "ipg", "per", "osc_per"; - }; - - gpio1: gpio@209c000 { - compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; - reg = <0x0209c000 0x4000>; - interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>, - <0 67 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@20a0000 { - compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; - reg = <0x020a0000 0x4000>; - interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>, - <0 69 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio@20a4000 { - compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; - reg = <0x020a4000 0x4000>; - interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>, - <0 71 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio4: gpio@20a8000 { - compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; - reg = <0x020a8000 0x4000>; - interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>, - <0 73 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio5: gpio@20ac000 { - compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; - reg = <0x020ac000 0x4000>; - interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>, - <0 75 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio6: gpio@20b0000 { - compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; - reg = <0x020b0000 0x4000>; - interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>, - <0 77 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio7: gpio@20b4000 { - compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; - reg = <0x020b4000 0x4000>; - interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>, - <0 79 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - kpp: kpp@20b8000 { - compatible = "fsl,imx6q-kpp", "fsl,imx21-kpp"; - reg = <0x020b8000 0x4000>; - interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_IPG>; - status = "disabled"; - }; - - wdog1: wdog@20bc000 { - compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; - reg = <0x020bc000 0x4000>; - interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_IPG>; - }; - - wdog2: wdog@20c0000 { - compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; - reg = <0x020c0000 0x4000>; - interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_IPG>; - status = "disabled"; - }; - - clks: ccm@20c4000 { - compatible = "fsl,imx6q-ccm"; - reg = <0x020c4000 0x4000>; - interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>, - <0 88 IRQ_TYPE_LEVEL_HIGH>; - #clock-cells = <1>; - }; - - anatop: anatop@20c8000 { - compatible = "fsl,imx6q-anatop", "syscon", "simple-mfd"; - reg = <0x020c8000 0x1000>; - interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>, - <0 54 IRQ_TYPE_LEVEL_HIGH>, - <0 127 IRQ_TYPE_LEVEL_HIGH>; - - reg_vdd1p1: regulator-1p1 { - compatible = "fsl,anatop-regulator"; - regulator-name = "vdd1p1"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - anatop-reg-offset = <0x110>; - anatop-vol-bit-shift = <8>; - anatop-vol-bit-width = <5>; - anatop-min-bit-val = <4>; - anatop-min-voltage = <800000>; - anatop-max-voltage = <1375000>; - anatop-enable-bit = <0>; - }; - - reg_vdd3p0: regulator-3p0 { - compatible = "fsl,anatop-regulator"; - regulator-name = "vdd3p0"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <3150000>; - regulator-always-on; - anatop-reg-offset = <0x120>; - anatop-vol-bit-shift = <8>; - anatop-vol-bit-width = <5>; - anatop-min-bit-val = <0>; - anatop-min-voltage = <2625000>; - anatop-max-voltage = <3400000>; - anatop-enable-bit = <0>; - }; - - reg_vdd2p5: regulator-2p5 { - compatible = "fsl,anatop-regulator"; - regulator-name = "vdd2p5"; - regulator-min-microvolt = <2250000>; - regulator-max-microvolt = <2750000>; - regulator-always-on; - anatop-reg-offset = <0x130>; - anatop-vol-bit-shift = <8>; - anatop-vol-bit-width = <5>; - anatop-min-bit-val = <0>; - anatop-min-voltage = <2100000>; - anatop-max-voltage = <2875000>; - anatop-enable-bit = <0>; - }; - - reg_arm: regulator-vddcore { - compatible = "fsl,anatop-regulator"; - regulator-name = "vddarm"; - regulator-min-microvolt = <725000>; - regulator-max-microvolt = <1450000>; - regulator-always-on; - anatop-reg-offset = <0x140>; - anatop-vol-bit-shift = <0>; - anatop-vol-bit-width = <5>; - anatop-delay-reg-offset = <0x170>; - anatop-delay-bit-shift = <24>; - anatop-delay-bit-width = <2>; - anatop-min-bit-val = <1>; - anatop-min-voltage = <725000>; - anatop-max-voltage = <1450000>; - }; - - reg_pu: regulator-vddpu { - compatible = "fsl,anatop-regulator"; - regulator-name = "vddpu"; - regulator-min-microvolt = <725000>; - regulator-max-microvolt = <1450000>; - regulator-enable-ramp-delay = <150>; - anatop-reg-offset = <0x140>; - anatop-vol-bit-shift = <9>; - anatop-vol-bit-width = <5>; - anatop-delay-reg-offset = <0x170>; - anatop-delay-bit-shift = <26>; - anatop-delay-bit-width = <2>; - anatop-min-bit-val = <1>; - anatop-min-voltage = <725000>; - anatop-max-voltage = <1450000>; - }; - - reg_soc: regulator-vddsoc { - compatible = "fsl,anatop-regulator"; - regulator-name = "vddsoc"; - regulator-min-microvolt = <725000>; - regulator-max-microvolt = <1450000>; - regulator-always-on; - anatop-reg-offset = <0x140>; - anatop-vol-bit-shift = <18>; - anatop-vol-bit-width = <5>; - anatop-delay-reg-offset = <0x170>; - anatop-delay-bit-shift = <28>; - anatop-delay-bit-width = <2>; - anatop-min-bit-val = <1>; - anatop-min-voltage = <725000>; - anatop-max-voltage = <1450000>; - }; - }; - - usbphy1: usbphy@20c9000 { - compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; - reg = <0x020c9000 0x1000>; - interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_USBPHY1>; - fsl,anatop = <&anatop>; - }; - - usbphy2: usbphy@20ca000 { - compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; - reg = <0x020ca000 0x1000>; - interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_USBPHY2>; - fsl,anatop = <&anatop>; - }; - - snvs: snvs@20cc000 { - compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; - reg = <0x020cc000 0x4000>; - - snvs_rtc: snvs-rtc-lp { - compatible = "fsl,sec-v4.0-mon-rtc-lp"; - regmap = <&snvs>; - offset = <0x34>; - interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>, - <0 20 IRQ_TYPE_LEVEL_HIGH>; - }; - - snvs_poweroff: snvs-poweroff { - compatible = "syscon-poweroff"; - regmap = <&snvs>; - offset = <0x38>; - value = <0x60>; - mask = <0x60>; - status = "disabled"; - }; - - snvs_pwrkey: snvs-powerkey { - compatible = "fsl,sec-v4.0-pwrkey"; - regmap = <&snvs>; - interrupts = ; - linux,keycode = ; - wakeup-source; - status = "disabled"; - }; - - snvs_lpgpr: snvs-lpgpr { - compatible = "fsl,imx6q-snvs-lpgpr"; - }; - }; - - epit1: epit@20d0000 { /* EPIT1 */ - reg = <0x020d0000 0x4000>; - interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>; - }; - - epit2: epit@20d4000 { /* EPIT2 */ - reg = <0x020d4000 0x4000>; - interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>; - }; - - src: src@20d8000 { - compatible = "fsl,imx6q-src", "fsl,imx51-src"; - reg = <0x020d8000 0x4000>; - interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>, - <0 96 IRQ_TYPE_LEVEL_HIGH>; - #reset-cells = <1>; - }; - - gpc: gpc@20dc000 { - compatible = "fsl,imx6q-gpc"; - reg = <0x020dc000 0x4000>; - interrupt-controller; - #interrupt-cells = <3>; - interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>, - <0 90 IRQ_TYPE_LEVEL_HIGH>; - interrupt-parent = <&intc>; - clocks = <&clks IMX6QDL_CLK_IPG>; - clock-names = "ipg"; - - pgc { - #address-cells = <1>; - #size-cells = <0>; - - power-domain@0 { - reg = <0>; - #power-domain-cells = <0>; - }; - pd_pu: power-domain@1 { - reg = <1>; - #power-domain-cells = <0>; - power-supply = <®_pu>; - clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>, - <&clks IMX6QDL_CLK_GPU3D_SHADER>, - <&clks IMX6QDL_CLK_GPU2D_CORE>, - <&clks IMX6QDL_CLK_GPU2D_AXI>, - <&clks IMX6QDL_CLK_OPENVG_AXI>, - <&clks IMX6QDL_CLK_VPU_AXI>; - }; - }; - }; - - gpr: iomuxc-gpr@20e0000 { - compatible = "fsl,imx6q-iomuxc-gpr", "syscon", "simple-mfd"; - reg = <0x20e0000 0x38>; - - mux: mux-controller { - compatible = "mmio-mux"; - #mux-control-cells = <1>; - }; - }; - - iomuxc: iomuxc@20e0000 { - compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc"; - reg = <0x20e0000 0x4000>; - }; - - dcic1: dcic@20e4000 { - reg = <0x020e4000 0x4000>; - interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>; - }; - - dcic2: dcic@20e8000 { - reg = <0x020e8000 0x4000>; - interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>; - }; - - sdma: sdma@20ec000 { - compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma"; - reg = <0x020ec000 0x4000>; - interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_IPG>, - <&clks IMX6QDL_CLK_SDMA>; - clock-names = "ipg", "ahb"; - #dma-cells = <3>; - fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; - }; - }; - - aips-bus@2100000 { /* AIPS2 */ - compatible = "fsl,aips-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x02100000 0x100000>; - ranges; - - crypto: caam@2100000 { - compatible = "fsl,sec-v4.0"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x2100000 0x10000>; - ranges = <0 0x2100000 0x10000>; - clocks = <&clks IMX6QDL_CLK_CAAM_MEM>, - <&clks IMX6QDL_CLK_CAAM_ACLK>, - <&clks IMX6QDL_CLK_CAAM_IPG>, - <&clks IMX6QDL_CLK_EIM_SLOW>; - clock-names = "mem", "aclk", "ipg", "emi_slow"; - - sec_jr0: jr0@1000 { - compatible = "fsl,sec-v4.0-job-ring"; - reg = <0x1000 0x1000>; - interrupts = ; - }; - - sec_jr1: jr1@2000 { - compatible = "fsl,sec-v4.0-job-ring"; - reg = <0x2000 0x1000>; - interrupts = ; - }; - }; - - aipstz@217c000 { /* AIPSTZ2 */ - reg = <0x0217c000 0x4000>; - }; - - usbotg: usb@2184000 { - compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; - reg = <0x02184000 0x200>; - interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_USBOH3>; - fsl,usbphy = <&usbphy1>; - fsl,usbmisc = <&usbmisc 0>; - ahb-burst-config = <0x0>; - tx-burst-size-dword = <0x10>; - rx-burst-size-dword = <0x10>; - status = "disabled"; - }; - - usbh1: usb@2184200 { - compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; - reg = <0x02184200 0x200>; - interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_USBOH3>; - fsl,usbphy = <&usbphy2>; - fsl,usbmisc = <&usbmisc 1>; - dr_mode = "host"; - ahb-burst-config = <0x0>; - tx-burst-size-dword = <0x10>; - rx-burst-size-dword = <0x10>; - status = "disabled"; - }; - - usbh2: usb@2184400 { - compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; - reg = <0x02184400 0x200>; - interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_USBOH3>; - fsl,usbphy = <&usbphynop1>; - phy_type = "hsic"; - fsl,usbmisc = <&usbmisc 2>; - dr_mode = "host"; - ahb-burst-config = <0x0>; - tx-burst-size-dword = <0x10>; - rx-burst-size-dword = <0x10>; - status = "disabled"; - }; - - usbh3: usb@2184600 { - compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; - reg = <0x02184600 0x200>; - interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_USBOH3>; - fsl,usbphy = <&usbphynop2>; - phy_type = "hsic"; - fsl,usbmisc = <&usbmisc 3>; - dr_mode = "host"; - ahb-burst-config = <0x0>; - tx-burst-size-dword = <0x10>; - rx-burst-size-dword = <0x10>; - status = "disabled"; - }; - - usbmisc: usbmisc@2184800 { - #index-cells = <1>; - compatible = "fsl,imx6q-usbmisc"; - reg = <0x02184800 0x200>; - clocks = <&clks IMX6QDL_CLK_USBOH3>; - }; - - fec: ethernet@2188000 { - compatible = "fsl,imx6q-fec"; - reg = <0x02188000 0x4000>; - interrupt-names = "int0", "pps"; - interrupts-extended = - <&intc 0 118 IRQ_TYPE_LEVEL_HIGH>, - <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_ENET>, - <&clks IMX6QDL_CLK_ENET>, - <&clks IMX6QDL_CLK_ENET_REF>; - clock-names = "ipg", "ahb", "ptp"; - status = "disabled"; - }; - - mlb@218c000 { - reg = <0x0218c000 0x4000>; - interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>, - <0 117 IRQ_TYPE_LEVEL_HIGH>, - <0 126 IRQ_TYPE_LEVEL_HIGH>; - }; - - usdhc1: usdhc@2190000 { - compatible = "fsl,imx6q-usdhc"; - reg = <0x02190000 0x4000>; - interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_USDHC1>, - <&clks IMX6QDL_CLK_USDHC1>, - <&clks IMX6QDL_CLK_USDHC1>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - status = "disabled"; - }; - - usdhc2: usdhc@2194000 { - compatible = "fsl,imx6q-usdhc"; - reg = <0x02194000 0x4000>; - interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_USDHC2>, - <&clks IMX6QDL_CLK_USDHC2>, - <&clks IMX6QDL_CLK_USDHC2>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - status = "disabled"; - }; - - usdhc3: usdhc@2198000 { - compatible = "fsl,imx6q-usdhc"; - reg = <0x02198000 0x4000>; - interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_USDHC3>, - <&clks IMX6QDL_CLK_USDHC3>, - <&clks IMX6QDL_CLK_USDHC3>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - status = "disabled"; - }; - - usdhc4: usdhc@219c000 { - compatible = "fsl,imx6q-usdhc"; - reg = <0x0219c000 0x4000>; - interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_USDHC4>, - <&clks IMX6QDL_CLK_USDHC4>, - <&clks IMX6QDL_CLK_USDHC4>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - status = "disabled"; - }; - - i2c1: i2c@21a0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; - reg = <0x021a0000 0x4000>; - interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_I2C1>; - status = "disabled"; - }; - - i2c2: i2c@21a4000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; - reg = <0x021a4000 0x4000>; - interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_I2C2>; - status = "disabled"; - }; - - i2c3: i2c@21a8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; - reg = <0x021a8000 0x4000>; - interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_I2C3>; - status = "disabled"; - }; - - romcp@21ac000 { - reg = <0x021ac000 0x4000>; - }; - - mmdc0: memory-controller@21b0000 { /* MMDC0 */ - compatible = "fsl,imx6q-mmdc"; - reg = <0x021b0000 0x4000>; - clocks = <&clks IMX6QDL_CLK_MMDC_P0_IPG>; - }; - - mmdc1: memory-controller@21b4000 { /* MMDC1 */ - compatible = "fsl,imx6q-mmdc"; - reg = <0x021b4000 0x4000>; - status = "disabled"; - }; - - weim: weim@21b8000 { - #address-cells = <2>; - #size-cells = <1>; - compatible = "fsl,imx6q-weim"; - reg = <0x021b8000 0x4000>; - interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_EIM_SLOW>; - fsl,weim-cs-gpr = <&gpr>; - status = "disabled"; - }; - - ocotp: ocotp@21bc000 { - compatible = "fsl,imx6q-ocotp", "syscon"; - reg = <0x021bc000 0x4000>; - clocks = <&clks IMX6QDL_CLK_IIM>; - }; - - tzasc@21d0000 { /* TZASC1 */ - reg = <0x021d0000 0x4000>; - interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; - }; - - tzasc@21d4000 { /* TZASC2 */ - reg = <0x021d4000 0x4000>; - interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>; - }; - - audmux: audmux@21d8000 { - compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux"; - reg = <0x021d8000 0x4000>; - status = "disabled"; - }; - - mipi_csi: mipi@21dc000 { - compatible = "fsl,imx6-mipi-csi2"; - reg = <0x021dc000 0x4000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 100 0x04>, <0 101 0x04>; - clocks = <&clks IMX6QDL_CLK_HSI_TX>, - <&clks IMX6QDL_CLK_VIDEO_27M>, - <&clks IMX6QDL_CLK_EIM_PODF>; - clock-names = "dphy", "ref", "pix"; - status = "disabled"; - }; - - mipi_dsi: mipi@21e0000 { - reg = <0x021e0000 0x4000>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - mipi_mux_0: endpoint { - remote-endpoint = <&ipu1_di0_mipi>; - }; - }; - - port@1 { - reg = <1>; - - mipi_mux_1: endpoint { - remote-endpoint = <&ipu1_di1_mipi>; - }; - }; - }; - }; - - vdoa@21e4000 { - compatible = "fsl,imx6q-vdoa"; - reg = <0x021e4000 0x4000>; - interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_VDOA>; - }; - - uart2: serial@21e8000 { - compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; - reg = <0x021e8000 0x4000>; - interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_UART_IPG>, - <&clks IMX6QDL_CLK_UART_SERIAL>; - clock-names = "ipg", "per"; - dmas = <&sdma 27 4 0>, <&sdma 28 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart3: serial@21ec000 { - compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; - reg = <0x021ec000 0x4000>; - interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_UART_IPG>, - <&clks IMX6QDL_CLK_UART_SERIAL>; - clock-names = "ipg", "per"; - dmas = <&sdma 29 4 0>, <&sdma 30 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart4: serial@21f0000 { - compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; - reg = <0x021f0000 0x4000>; - interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_UART_IPG>, - <&clks IMX6QDL_CLK_UART_SERIAL>; - clock-names = "ipg", "per"; - dmas = <&sdma 31 4 0>, <&sdma 32 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart5: serial@21f4000 { - compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; - reg = <0x021f4000 0x4000>; - interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_UART_IPG>, - <&clks IMX6QDL_CLK_UART_SERIAL>; - clock-names = "ipg", "per"; - dmas = <&sdma 33 4 0>, <&sdma 34 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - }; - - ipu1: ipu@2400000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6q-ipu"; - reg = <0x02400000 0x400000>; - interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>, - <0 5 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_IPU1>, - <&clks IMX6QDL_CLK_IPU1_DI0>, - <&clks IMX6QDL_CLK_IPU1_DI1>; - clock-names = "bus", "di0", "di1"; - resets = <&src 2>; - - ipu1_csi0: port@0 { - reg = <0>; - - ipu1_csi0_from_ipu1_csi0_mux: endpoint { - remote-endpoint = <&ipu1_csi0_mux_to_ipu1_csi0>; - }; - }; - - ipu1_csi1: port@1 { - reg = <1>; - }; - - ipu1_di0: port@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - - ipu1_di0_disp0: endpoint@0 { - reg = <0>; - }; - - ipu1_di0_hdmi: endpoint@1 { - reg = <1>; - remote-endpoint = <&hdmi_mux_0>; - }; - - ipu1_di0_mipi: endpoint@2 { - reg = <2>; - remote-endpoint = <&mipi_mux_0>; - }; - - ipu1_di0_lvds0: endpoint@3 { - reg = <3>; - remote-endpoint = <&lvds0_mux_0>; - }; - - ipu1_di0_lvds1: endpoint@4 { - reg = <4>; - remote-endpoint = <&lvds1_mux_0>; - }; - }; - - ipu1_di1: port@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - - ipu1_di1_disp1: endpoint@0 { - reg = <0>; - }; - - ipu1_di1_hdmi: endpoint@1 { - reg = <1>; - remote-endpoint = <&hdmi_mux_1>; - }; - - ipu1_di1_mipi: endpoint@2 { - reg = <2>; - remote-endpoint = <&mipi_mux_1>; - }; - - ipu1_di1_lvds0: endpoint@3 { - reg = <3>; - remote-endpoint = <&lvds0_mux_1>; - }; - - ipu1_di1_lvds1: endpoint@4 { - reg = <4>; - remote-endpoint = <&lvds1_mux_1>; - }; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/imx6qp-nitrogen6_max.dts b/sys/gnu/dts/arm/imx6qp-nitrogen6_max.dts deleted file mode 100644 index 741d1ed338c..00000000000 --- a/sys/gnu/dts/arm/imx6qp-nitrogen6_max.dts +++ /dev/null @@ -1,22 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR X11 -/* - * Copyright 2016 Boundary Devices, Inc. - */ - -/dts-v1/; - -#include "imx6qp.dtsi" -#include "imx6qdl-nitrogen6_max.dtsi" - -/ { - model = "Boundary Devices i.MX6 Quad Plus Nitrogen6_MAX Board"; - compatible = "boundary,imx6qp-nitrogen6_max", "fsl,imx6qp"; -}; - -&pcie { - status = "disabled"; -}; - -&sata { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx6qp-nitrogen6_som2.dts b/sys/gnu/dts/arm/imx6qp-nitrogen6_som2.dts deleted file mode 100644 index 1593ac86b2a..00000000000 --- a/sys/gnu/dts/arm/imx6qp-nitrogen6_som2.dts +++ /dev/null @@ -1,18 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR X11 -/* - * Copyright 2017 Boundary Devices, Inc. - */ - -/dts-v1/; - -#include "imx6qp.dtsi" -#include "imx6qdl-nitrogen6_som2.dtsi" - -/ { - model = "Boundary Devices i.MX6 Quad Plus Nitrogen6_SOM2 Board"; - compatible = "boundary,imx6qp-nitrogen6_som2", "fsl,imx6qp"; -}; - -&sata { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx6qp-phytec-mira-rdk-nand.dts b/sys/gnu/dts/arm/imx6qp-phytec-mira-rdk-nand.dts deleted file mode 100644 index f27d7ab4262..00000000000 --- a/sys/gnu/dts/arm/imx6qp-phytec-mira-rdk-nand.dts +++ /dev/null @@ -1,72 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2018 PHYTEC Messtechnik GmbH - * Author: Enrico Scholz - */ - -/dts-v1/; -#include "imx6qp.dtsi" -#include "imx6qdl-phytec-phycore-som.dtsi" -#include "imx6qdl-phytec-mira.dtsi" - -/ { - model = "PHYTEC phyBOARD-Mira QuadPlus Carrier-Board with NAND"; - compatible = "phytec,imx6qp-pbac06-nand", "phytec,imx6qp-pbac06", - "phytec,imx6qdl-pcm058", "fsl,imx6qp"; - - chosen { - stdout-path = &uart2; - }; -}; - -&can1 { - status = "okay"; -}; - -&fec { - status = "okay"; -}; - -&gpmi { - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c_rtc { - status = "okay"; -}; - -&m25p80 { - status = "okay"; -}; - -&pcie { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&usbh1 { - status = "okay"; -}; - -&usbotg { - status = "okay"; -}; - -&usdhc1 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx6qp-sabreauto.dts b/sys/gnu/dts/arm/imx6qp-sabreauto.dts deleted file mode 100644 index d4caeeb0af7..00000000000 --- a/sys/gnu/dts/arm/imx6qp-sabreauto.dts +++ /dev/null @@ -1,55 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -// -// Copyright 2016 Freescale Semiconductor, Inc. - -/dts-v1/; - -#include "imx6qp.dtsi" -#include "imx6qdl-sabreauto.dtsi" - -/ { - model = "Freescale i.MX6 Quad Plus SABRE Automotive Board"; - compatible = "fsl,imx6qp-sabreauto", "fsl,imx6qp"; -}; - -&i2c2 { - max7322: gpio@68 { - compatible = "maxim,max7322"; - reg = <0x68>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -&iomuxc { - imx6qdl-sabreauto { - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b018 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b018 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b018 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b018 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b018 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b018 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b018 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b018 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b018 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b018 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b018 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b018 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 - >; - }; - }; -}; - -&pcie { - status = "disabled"; -}; - -&vgen3_reg { - regulator-always-on; -}; diff --git a/sys/gnu/dts/arm/imx6qp-sabresd.dts b/sys/gnu/dts/arm/imx6qp-sabresd.dts deleted file mode 100644 index f1b9cb104fd..00000000000 --- a/sys/gnu/dts/arm/imx6qp-sabresd.dts +++ /dev/null @@ -1,55 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -// -// Copyright 2016 Freescale Semiconductor, Inc. - -/dts-v1/; - -#include "imx6qp.dtsi" -#include "imx6qdl-sabresd.dtsi" - -/ { - model = "Freescale i.MX6 Quad Plus SABRE Smart Device Board"; - compatible = "fsl,imx6qp-sabresd", "fsl,imx6qp"; -}; - -®_arm { - vin-supply = <&sw2_reg>; -}; - -&iomuxc { - imx6qdl-sabresd { - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10071 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 - MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059 - MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059 - MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059 - MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10071 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 - >; - }; - }; -}; - -&pcie { - status = "disabled"; -}; diff --git a/sys/gnu/dts/arm/imx6qp-tx6qp-8037-mb7.dts b/sys/gnu/dts/arm/imx6qp-tx6qp-8037-mb7.dts deleted file mode 100644 index 92b38e6699a..00000000000 --- a/sys/gnu/dts/arm/imx6qp-tx6qp-8037-mb7.dts +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Copyright 2017 Lothar Waßmann - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6qp-tx6qp-8037.dts" -#include "imx6qdl-tx6-mb7.dtsi" - -/ { - model = "Ka-Ro electronics TX6Q-8037 Module on MB7 baseboard"; -}; diff --git a/sys/gnu/dts/arm/imx6qp-tx6qp-8037.dts b/sys/gnu/dts/arm/imx6qp-tx6qp-8037.dts deleted file mode 100644 index ffc0f2ee11d..00000000000 --- a/sys/gnu/dts/arm/imx6qp-tx6qp-8037.dts +++ /dev/null @@ -1,86 +0,0 @@ -/* - * Copyright 2017 Lothar Waßmann - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6qp.dtsi" -#include "imx6qdl-tx6.dtsi" -#include "imx6qdl-tx6-lcd.dtsi" - -/ { - model = "Ka-Ro electronics TX6QP-8037 Module"; - compatible = "karo,imx6qp-tx6qp", "fsl,imx6qp"; -}; - -&ds1339 { - status = "disabled"; -}; - -&gpmi { - status = "disabled"; -}; - -&ipu2 { - status = "disabled"; -}; - -&usdhc4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc4>; - bus-width = <4>; - non-removable; - no-1-8-v; - fsl,wp-controller; - status = "okay"; -}; - -&iomuxc { - pinctrl_usdhc4: usdhc4grp { - fsl,pins = < - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x070b1 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x070b1 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x070b1 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x070b1 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x070b1 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x070b1 - MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x0b0b1 - >; - }; -}; diff --git a/sys/gnu/dts/arm/imx6qp-tx6qp-8137-mb7.dts b/sys/gnu/dts/arm/imx6qp-tx6qp-8137-mb7.dts deleted file mode 100644 index 07ad70718ae..00000000000 --- a/sys/gnu/dts/arm/imx6qp-tx6qp-8137-mb7.dts +++ /dev/null @@ -1,57 +0,0 @@ -/* - * Copyright 2017 Lothar Waßmann - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6qp-tx6qp-8137.dts" -#include "imx6qdl-tx6-mb7.dtsi" - -/ { - model = "Ka-Ro electronics TX6Q-8137 Module on MB7 baseboard"; - compatible = "karo,imx6qp-tx6qp", "fsl,imx6qp"; -}; - -&ipu2 { - status = "disabled"; -}; - -&sata { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx6qp-tx6qp-8137.dts b/sys/gnu/dts/arm/imx6qp-tx6qp-8137.dts deleted file mode 100644 index dd494d58701..00000000000 --- a/sys/gnu/dts/arm/imx6qp-tx6qp-8137.dts +++ /dev/null @@ -1,90 +0,0 @@ -/* - * Copyright 2017 Lothar Waßmann - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6qp.dtsi" -#include "imx6qdl-tx6.dtsi" -#include "imx6qdl-tx6-lvds.dtsi" - -/ { - model = "Ka-Ro electronics TX6QP-8137 Module"; - compatible = "karo,imx6qp-tx6qp", "fsl,imx6qp"; -}; - -&ds1339 { - status = "disabled"; -}; - -&gpmi { - status = "disabled"; -}; - -&ipu2 { - status = "disabled"; -}; - -&sata { - status = "okay"; -}; - -&usdhc4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc4>; - bus-width = <4>; - non-removable; - no-1-8-v; - fsl,wp-controller; - status = "okay"; -}; - -&iomuxc { - pinctrl_usdhc4: usdhc4grp { - fsl,pins = < - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x070b1 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x070b1 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x070b1 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x070b1 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x070b1 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x070b1 - MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x0b0b1 - >; - }; -}; diff --git a/sys/gnu/dts/arm/imx6qp-wandboard-revd1.dts b/sys/gnu/dts/arm/imx6qp-wandboard-revd1.dts deleted file mode 100644 index 08d8b78a209..00000000000 --- a/sys/gnu/dts/arm/imx6qp-wandboard-revd1.dts +++ /dev/null @@ -1,23 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2013 Freescale Semiconductor, Inc. - * - * Author: Fabio Estevam - */ -/dts-v1/; -#include "imx6qp.dtsi" -#include "imx6qdl-wandboard-revd1.dtsi" - -/ { - model = "Wandboard i.MX6 QuadPlus Board revD1"; - compatible = "wand,imx6qp-wandboard", "fsl,imx6qp"; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x80000000>; - }; -}; - -&sata { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx6qp-zii-rdu2.dts b/sys/gnu/dts/arm/imx6qp-zii-rdu2.dts deleted file mode 100644 index 57de447c460..00000000000 --- a/sys/gnu/dts/arm/imx6qp-zii-rdu2.dts +++ /dev/null @@ -1,25 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2016-2017 Zodiac Inflight Innovations - */ - -/dts-v1/; - -#include "imx6qp.dtsi" -#include "imx6qdl-zii-rdu2.dtsi" - -/ { - model = "ZII RDU2+ Board"; - compatible = "zii,imx6qp-zii-rdu2", "fsl,imx6qp"; - - /* Will be filled by the bootloader */ - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0>; - }; -}; - -&gpu_3d { - assigned-clocks = <&clks IMX6QDL_CLK_GPU3D_SHADER_SEL>; - assigned-clock-parents = <&clks IMX6QDL_CLK_PLL2_PFD1_594M>; -}; diff --git a/sys/gnu/dts/arm/imx6qp.dtsi b/sys/gnu/dts/arm/imx6qp.dtsi deleted file mode 100644 index 5f51f8e5c1f..00000000000 --- a/sys/gnu/dts/arm/imx6qp.dtsi +++ /dev/null @@ -1,115 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -// -// Copyright 2016 Freescale Semiconductor, Inc. - -#include "imx6q.dtsi" - -/ { - soc { - ocram2: sram@940000 { - compatible = "mmio-sram"; - reg = <0x00940000 0x20000>; - clocks = <&clks IMX6QDL_CLK_OCRAM>; - }; - - ocram3: sram@960000 { - compatible = "mmio-sram"; - reg = <0x00960000 0x20000>; - clocks = <&clks IMX6QDL_CLK_OCRAM>; - }; - - aips-bus@2100000 { - pre1: pre@21c8000 { - compatible = "fsl,imx6qp-pre"; - reg = <0x021c8000 0x1000>; - interrupts = ; - clocks = <&clks IMX6QDL_CLK_PRE0>; - clock-names = "axi"; - fsl,iram = <&ocram2>; - }; - - pre2: pre@21c9000 { - compatible = "fsl,imx6qp-pre"; - reg = <0x021c9000 0x1000>; - interrupts = ; - clocks = <&clks IMX6QDL_CLK_PRE1>; - clock-names = "axi"; - fsl,iram = <&ocram2>; - }; - - pre3: pre@21ca000 { - compatible = "fsl,imx6qp-pre"; - reg = <0x021ca000 0x1000>; - interrupts = ; - clocks = <&clks IMX6QDL_CLK_PRE2>; - clock-names = "axi"; - fsl,iram = <&ocram3>; - }; - - pre4: pre@21cb000 { - compatible = "fsl,imx6qp-pre"; - reg = <0x021cb000 0x1000>; - interrupts = ; - clocks = <&clks IMX6QDL_CLK_PRE3>; - clock-names = "axi"; - fsl,iram = <&ocram3>; - }; - - prg1: prg@21cc000 { - compatible = "fsl,imx6qp-prg"; - reg = <0x021cc000 0x1000>; - clocks = <&clks IMX6QDL_CLK_PRG0_APB>, - <&clks IMX6QDL_CLK_PRG0_AXI>; - clock-names = "ipg", "axi"; - fsl,pres = <&pre1>, <&pre2>, <&pre3>; - }; - - prg2: prg@21cd000 { - compatible = "fsl,imx6qp-prg"; - reg = <0x021cd000 0x1000>; - clocks = <&clks IMX6QDL_CLK_PRG1_APB>, - <&clks IMX6QDL_CLK_PRG1_AXI>; - clock-names = "ipg", "axi"; - fsl,pres = <&pre4>, <&pre2>, <&pre3>; - }; - }; - }; -}; - -&fec { - /delete-property/interrupts-extended; - interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>, - <0 119 IRQ_TYPE_LEVEL_HIGH>; -}; - -&gpc { - compatible = "fsl,imx6qp-gpc", "fsl,imx6q-gpc"; -}; - -&ipu1 { - compatible = "fsl,imx6qp-ipu", "fsl,imx6q-ipu"; - fsl,prg = <&prg1>; -}; - -&ipu2 { - compatible = "fsl,imx6qp-ipu", "fsl,imx6q-ipu"; - fsl,prg = <&prg2>; -}; - -&ldb { - clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>, - <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>, - <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>, - <&clks IMX6QDL_CLK_LDB_DI0_PODF>, <&clks IMX6QDL_CLK_LDB_DI1_PODF>; - clock-names = "di0_pll", "di1_pll", - "di0_sel", "di1_sel", "di2_sel", "di3_sel", - "di0", "di1"; -}; - -&mmdc0 { - compatible = "fsl,imx6qp-mmdc", "fsl,imx6q-mmdc"; -}; - -&pcie { - compatible = "fsl,imx6qp-pcie", "snps,dw-pcie"; -}; diff --git a/sys/gnu/dts/arm/imx6sl-evk.dts b/sys/gnu/dts/arm/imx6sl-evk.dts deleted file mode 100644 index bc86cfaaa9c..00000000000 --- a/sys/gnu/dts/arm/imx6sl-evk.dts +++ /dev/null @@ -1,648 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// -//Copyright (C) 2013 Freescale Semiconductor, Inc. - -/dts-v1/; - -#include -#include -#include "imx6sl.dtsi" - -/ { - model = "Freescale i.MX6 SoloLite EVK Board"; - compatible = "fsl,imx6sl-evk", "fsl,imx6sl"; - - chosen { - stdout-path = &uart1; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x40000000>; - }; - - backlight_display: backlight_display { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_led>; - - user { - label = "debug"; - gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - reg_usb_otg1_vbus: regulator-usb-otg1-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio4 0 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&swbst_reg>; - }; - - reg_usb_otg2_vbus: regulator-usb-otg2-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg2_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&swbst_reg>; - }; - - reg_aud3v: regulator-aud3v { - compatible = "regulator-fixed"; - regulator-name = "wm8962-supply-3v15"; - regulator-min-microvolt = <3150000>; - regulator-max-microvolt = <3150000>; - regulator-boot-on; - }; - - reg_aud4v: regulator-aud4v { - compatible = "regulator-fixed"; - regulator-name = "wm8962-supply-4v2"; - regulator-min-microvolt = <4325000>; - regulator-max-microvolt = <4325000>; - regulator-boot-on; - }; - - reg_lcd_3v3: regulator-lcd-3v3 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_lcd_3v3>; - regulator-name = "lcd-3v3"; - gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_lcd_5v: regulator-lcd-5v { - compatible = "regulator-fixed"; - regulator-name = "lcd-5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - sound { - compatible = "fsl,imx6sl-evk-wm8962", "fsl,imx-audio-wm8962"; - model = "wm8962-audio"; - ssi-controller = <&ssi2>; - audio-codec = <&codec>; - audio-routing = - "Headphone Jack", "HPOUTL", - "Headphone Jack", "HPOUTR", - "Ext Spk", "SPKOUTL", - "Ext Spk", "SPKOUTR", - "AMIC", "MICBIAS", - "IN3R", "AMIC"; - mux-int-port = <2>; - mux-ext-port = <3>; - }; - - panel { - compatible = "sii,43wvf1g"; - backlight = <&backlight_display>; - dvdd-supply = <®_lcd_3v3>; - avdd-supply = <®_lcd_5v>; - - port { - panel_in: endpoint { - remote-endpoint = <&display_out>; - }; - }; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux3>; - status = "okay"; -}; - -&ecspi1 { - cs-gpios = <&gpio4 11 0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - status = "okay"; - - flash: m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,m25p32", "jedec,spi-nor"; - spi-max-frequency = <20000000>; - reg = <0>; - }; -}; - -&fec { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&pinctrl_fec>; - pinctrl-1 = <&pinctrl_fec_sleep>; - phy-mode = "rmii"; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pmic: pfuze100@8 { - compatible = "fsl,pfuze100"; - reg = <0x08>; - - regulators { - sw1a_reg: sw1ab { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw1c_reg: sw1c { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3a_reg: sw3a { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3b_reg: sw3b { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - sw4_reg: sw4 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - }; - - snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - vgen1_reg: vgen1 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - regulator-always-on; - }; - - vgen2_reg: vgen2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen3_reg: vgen3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - vgen4_reg: vgen4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen5_reg: vgen5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen6_reg: vgen6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - codec: wm8962@1a { - compatible = "wlf,wm8962"; - reg = <0x1a>; - clocks = <&clks IMX6SL_CLK_EXTERN_AUDIO>; - DCVDD-supply = <&vgen3_reg>; - DBVDD-supply = <®_aud3v>; - AVDD-supply = <&vgen3_reg>; - CPVDD-supply = <&vgen3_reg>; - MICVDD-supply = <®_aud3v>; - PLLVDD-supply = <&vgen3_reg>; - SPKVDD1-supply = <®_aud4v>; - SPKVDD2-supply = <®_aud4v>; - }; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - imx6sl-evk { - pinctrl_hog: hoggrp { - fsl,pins = < - MX6SL_PAD_KEY_ROW7__GPIO4_IO07 0x17059 - MX6SL_PAD_KEY_COL7__GPIO4_IO06 0x17059 - MX6SL_PAD_SD2_DAT7__GPIO5_IO00 0x17059 - MX6SL_PAD_SD2_DAT6__GPIO4_IO29 0x17059 - MX6SL_PAD_REF_CLK_32K__GPIO3_IO22 0x17059 - MX6SL_PAD_KEY_COL4__GPIO4_IO00 0x80000000 - MX6SL_PAD_KEY_COL5__GPIO4_IO02 0x80000000 - MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x4130b0 - >; - }; - - pinctrl_audmux3: audmux3grp { - fsl,pins = < - MX6SL_PAD_AUD_RXD__AUD3_RXD 0x4130b0 - MX6SL_PAD_AUD_TXC__AUD3_TXC 0x4130b0 - MX6SL_PAD_AUD_TXD__AUD3_TXD 0x4110b0 - MX6SL_PAD_AUD_TXFS__AUD3_TXFS 0x4130b0 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6SL_PAD_ECSPI1_MISO__ECSPI1_MISO 0x100b1 - MX6SL_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x100b1 - MX6SL_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x100b1 - MX6SL_PAD_ECSPI1_SS0__GPIO4_IO11 0x80000000 - >; - }; - - pinctrl_fec: fecgrp { - fsl,pins = < - MX6SL_PAD_FEC_MDC__FEC_MDC 0x1b0b0 - MX6SL_PAD_FEC_MDIO__FEC_MDIO 0x1b0b0 - MX6SL_PAD_FEC_CRS_DV__FEC_RX_DV 0x1b0b0 - MX6SL_PAD_FEC_RXD0__FEC_RX_DATA0 0x1b0b0 - MX6SL_PAD_FEC_RXD1__FEC_RX_DATA1 0x1b0b0 - MX6SL_PAD_FEC_TX_EN__FEC_TX_EN 0x1b0b0 - MX6SL_PAD_FEC_TXD0__FEC_TX_DATA0 0x1b0b0 - MX6SL_PAD_FEC_TXD1__FEC_TX_DATA1 0x1b0b0 - MX6SL_PAD_FEC_REF_CLK__FEC_REF_OUT 0x4001b0a8 - >; - }; - - pinctrl_fec_sleep: fecgrp-sleep { - fsl,pins = < - MX6SL_PAD_FEC_MDC__GPIO4_IO23 0x3080 - MX6SL_PAD_FEC_CRS_DV__GPIO4_IO25 0x3080 - MX6SL_PAD_FEC_RXD0__GPIO4_IO17 0x3080 - MX6SL_PAD_FEC_RXD1__GPIO4_IO18 0x3080 - MX6SL_PAD_FEC_TX_EN__GPIO4_IO22 0x3080 - MX6SL_PAD_FEC_TXD0__GPIO4_IO24 0x3080 - MX6SL_PAD_FEC_TXD1__GPIO4_IO16 0x3080 - MX6SL_PAD_FEC_REF_CLK__GPIO4_IO26 0x3080 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x4001b8b1 - MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x4001b8b1 - >; - }; - - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6SL_PAD_I2C2_SCL__I2C2_SCL 0x4001b8b1 - MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_kpp: kppgrp { - fsl,pins = < - MX6SL_PAD_KEY_ROW0__KEY_ROW0 0x1b010 - MX6SL_PAD_KEY_ROW1__KEY_ROW1 0x1b010 - MX6SL_PAD_KEY_ROW2__KEY_ROW2 0x1b0b0 - MX6SL_PAD_KEY_COL0__KEY_COL0 0x110b0 - MX6SL_PAD_KEY_COL1__KEY_COL1 0x110b0 - MX6SL_PAD_KEY_COL2__KEY_COL2 0x110b0 - >; - }; - - pinctrl_lcd: lcdgrp { - fsl,pins = < - MX6SL_PAD_LCD_DAT0__LCD_DATA00 0x1b0b0 - MX6SL_PAD_LCD_DAT1__LCD_DATA01 0x1b0b0 - MX6SL_PAD_LCD_DAT2__LCD_DATA02 0x1b0b0 - MX6SL_PAD_LCD_DAT3__LCD_DATA03 0x1b0b0 - MX6SL_PAD_LCD_DAT4__LCD_DATA04 0x1b0b0 - MX6SL_PAD_LCD_DAT5__LCD_DATA05 0x1b0b0 - MX6SL_PAD_LCD_DAT6__LCD_DATA06 0x1b0b0 - MX6SL_PAD_LCD_DAT7__LCD_DATA07 0x1b0b0 - MX6SL_PAD_LCD_DAT8__LCD_DATA08 0x1b0b0 - MX6SL_PAD_LCD_DAT9__LCD_DATA09 0x1b0b0 - MX6SL_PAD_LCD_DAT10__LCD_DATA10 0x1b0b0 - MX6SL_PAD_LCD_DAT11__LCD_DATA11 0x1b0b0 - MX6SL_PAD_LCD_DAT12__LCD_DATA12 0x1b0b0 - MX6SL_PAD_LCD_DAT13__LCD_DATA13 0x1b0b0 - MX6SL_PAD_LCD_DAT14__LCD_DATA14 0x1b0b0 - MX6SL_PAD_LCD_DAT15__LCD_DATA15 0x1b0b0 - MX6SL_PAD_LCD_DAT16__LCD_DATA16 0x1b0b0 - MX6SL_PAD_LCD_DAT17__LCD_DATA17 0x1b0b0 - MX6SL_PAD_LCD_DAT18__LCD_DATA18 0x1b0b0 - MX6SL_PAD_LCD_DAT19__LCD_DATA19 0x1b0b0 - MX6SL_PAD_LCD_DAT20__LCD_DATA20 0x1b0b0 - MX6SL_PAD_LCD_DAT21__LCD_DATA21 0x1b0b0 - MX6SL_PAD_LCD_DAT22__LCD_DATA22 0x1b0b0 - MX6SL_PAD_LCD_DAT23__LCD_DATA23 0x1b0b0 - MX6SL_PAD_LCD_CLK__LCD_CLK 0x1b0b0 - MX6SL_PAD_LCD_ENABLE__LCD_ENABLE 0x1b0b0 - MX6SL_PAD_LCD_HSYNC__LCD_HSYNC 0x1b0b0 - MX6SL_PAD_LCD_VSYNC__LCD_VSYNC 0x1b0b0 - >; - }; - - pinctrl_led: ledgrp { - fsl,pins = < - MX6SL_PAD_HSIC_STROBE__GPIO3_IO20 0x17059 - >; - }; - - pinctrl_pwm1: pwmgrp { - fsl,pins = < - MX6SL_PAD_PWM1__PWM1_OUT 0x110b0 - >; - }; - - pinctrl_reg_lcd_3v3: reglcd3v3grp { - fsl,pins = < - MX6SL_PAD_KEY_ROW5__GPIO4_IO03 0x17059 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1 - MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg1: usbotg1grp { - fsl,pins = < - MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID 0x17059 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6SL_PAD_SD1_CMD__SD1_CMD 0x17059 - MX6SL_PAD_SD1_CLK__SD1_CLK 0x10059 - MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x17059 - MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x17059 - MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x17059 - MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x17059 - MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x17059 - MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x17059 - MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x17059 - MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x17059 - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1grp100mhz { - fsl,pins = < - MX6SL_PAD_SD1_CMD__SD1_CMD 0x170b9 - MX6SL_PAD_SD1_CLK__SD1_CLK 0x100b9 - MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x170b9 - MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x170b9 - MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x170b9 - MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x170b9 - MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x170b9 - MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x170b9 - MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x170b9 - MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x170b9 - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1grp200mhz { - fsl,pins = < - MX6SL_PAD_SD1_CMD__SD1_CMD 0x170f9 - MX6SL_PAD_SD1_CLK__SD1_CLK 0x100f9 - MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x170f9 - MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x170f9 - MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x170f9 - MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x170f9 - MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x170f9 - MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x170f9 - MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x170f9 - MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x170f9 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6SL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6SL_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x17059 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2grp100mhz { - fsl,pins = < - MX6SL_PAD_SD2_CMD__SD2_CMD 0x170b9 - MX6SL_PAD_SD2_CLK__SD2_CLK 0x100b9 - MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 - MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 - MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 - MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2grp200mhz { - fsl,pins = < - MX6SL_PAD_SD2_CMD__SD2_CMD 0x170f9 - MX6SL_PAD_SD2_CLK__SD2_CLK 0x100f9 - MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 - MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 - MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 - MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170f9 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6SL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6SL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3grp100mhz { - fsl,pins = < - MX6SL_PAD_SD3_CMD__SD3_CMD 0x170b9 - MX6SL_PAD_SD3_CLK__SD3_CLK 0x100b9 - MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 - MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 - MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 - MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3grp200mhz { - fsl,pins = < - MX6SL_PAD_SD3_CMD__SD3_CMD 0x170f9 - MX6SL_PAD_SD3_CLK__SD3_CLK 0x100f9 - MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 - MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 - MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 - MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 - >; - }; - }; -}; - -&kpp { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_kpp>; - linux,keymap = < - MATRIX_KEY(0x0, 0x0, KEY_UP) /* ROW0, COL0 */ - MATRIX_KEY(0x0, 0x1, KEY_DOWN) /* ROW0, COL1 */ - MATRIX_KEY(0x0, 0x2, KEY_ENTER) /* ROW0, COL2 */ - MATRIX_KEY(0x1, 0x0, KEY_HOME) /* ROW1, COL0 */ - MATRIX_KEY(0x1, 0x1, KEY_RIGHT) /* ROW1, COL1 */ - MATRIX_KEY(0x1, 0x2, KEY_LEFT) /* ROW1, COL2 */ - MATRIX_KEY(0x2, 0x0, KEY_VOLUMEDOWN) /* ROW2, COL0 */ - MATRIX_KEY(0x2, 0x1, KEY_VOLUMEUP) /* ROW2, COL1 */ - >; - status = "okay"; -}; - -&lcdif { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd>; - status = "okay"; - - port { - display_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "okay"; -}; - -®_vdd1p1 { - vin-supply = <&sw2_reg>; -}; - -®_vdd2p5 { - vin-supply = <&sw2_reg>; -}; - -&snvs_poweroff { - status = "okay"; -}; - -&ssi2 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&usbotg1 { - vbus-supply = <®_usb_otg1_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg1>; - disable-over-current; - status = "okay"; -}; - -&usbotg2 { - vbus-supply = <®_usb_otg2_vbus>; - dr_mode = "host"; - disable-over-current; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>; - bus-width = <8>; - cd-gpios = <&gpio4 7 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>; - cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - cd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx6sl-pinfunc.h b/sys/gnu/dts/arm/imx6sl-pinfunc.h deleted file mode 100644 index bcf16060ecd..00000000000 --- a/sys/gnu/dts/arm/imx6sl-pinfunc.h +++ /dev/null @@ -1,1073 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - */ - -#ifndef __DTS_IMX6SL_PINFUNC_H -#define __DTS_IMX6SL_PINFUNC_H - -/* - * The pin function ID is a tuple of - * - */ -#define MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x04c 0x2a4 0x000 0x0 0x0 -#define MX6SL_PAD_AUD_MCLK__PWM4_OUT 0x04c 0x2a4 0x000 0x1 0x0 -#define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY 0x04c 0x2a4 0x6b4 0x2 0x0 -#define MX6SL_PAD_AUD_MCLK__FEC_MDC 0x04c 0x2a4 0x000 0x3 0x0 -#define MX6SL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x04c 0x2a4 0x000 0x4 0x0 -#define MX6SL_PAD_AUD_MCLK__GPIO1_IO06 0x04c 0x2a4 0x000 0x5 0x0 -#define MX6SL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x04c 0x2a4 0x7f4 0x6 0x0 -#define MX6SL_PAD_AUD_RXC__AUD3_RXC 0x050 0x2a8 0x000 0x0 0x0 -#define MX6SL_PAD_AUD_RXC__I2C1_SDA 0x050 0x2a8 0x720 0x1 0x0 -#define MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x050 0x2a8 0x000 0x2 0x0 -#define MX6SL_PAD_AUD_RXC__UART3_RX_DATA 0x050 0x2a8 0x80c 0x2 0x0 -#define MX6SL_PAD_AUD_RXC__FEC_TX_CLK 0x050 0x2a8 0x70c 0x3 0x0 -#define MX6SL_PAD_AUD_RXC__I2C3_SDA 0x050 0x2a8 0x730 0x4 0x0 -#define MX6SL_PAD_AUD_RXC__GPIO1_IO01 0x050 0x2a8 0x000 0x5 0x0 -#define MX6SL_PAD_AUD_RXC__ECSPI3_SS1 0x050 0x2a8 0x6c4 0x6 0x0 -#define MX6SL_PAD_AUD_RXD__AUD3_RXD 0x054 0x2ac 0x000 0x0 0x0 -#define MX6SL_PAD_AUD_RXD__ECSPI3_MOSI 0x054 0x2ac 0x6bc 0x1 0x0 -#define MX6SL_PAD_AUD_RXD__UART4_RX_DATA 0x054 0x2ac 0x814 0x2 0x0 -#define MX6SL_PAD_AUD_RXD__UART4_TX_DATA 0x054 0x2ac 0x000 0x2 0x0 -#define MX6SL_PAD_AUD_RXD__FEC_RX_ER 0x054 0x2ac 0x708 0x3 0x0 -#define MX6SL_PAD_AUD_RXD__SD1_LCTL 0x054 0x2ac 0x000 0x4 0x0 -#define MX6SL_PAD_AUD_RXD__GPIO1_IO02 0x054 0x2ac 0x000 0x5 0x0 -#define MX6SL_PAD_AUD_RXFS__AUD3_RXFS 0x058 0x2b0 0x000 0x0 0x0 -#define MX6SL_PAD_AUD_RXFS__I2C1_SCL 0x058 0x2b0 0x71c 0x1 0x0 -#define MX6SL_PAD_AUD_RXFS__UART3_RX_DATA 0x058 0x2b0 0x80c 0x2 0x1 -#define MX6SL_PAD_AUD_RXFS__UART3_TX_DATA 0x058 0x2b0 0x000 0x2 0x0 -#define MX6SL_PAD_AUD_RXFS__FEC_MDIO 0x058 0x2b0 0x6f4 0x3 0x0 -#define MX6SL_PAD_AUD_RXFS__I2C3_SCL 0x058 0x2b0 0x72c 0x4 0x0 -#define MX6SL_PAD_AUD_RXFS__GPIO1_IO00 0x058 0x2b0 0x000 0x5 0x0 -#define MX6SL_PAD_AUD_RXFS__ECSPI3_SS0 0x058 0x2b0 0x6c0 0x6 0x0 -#define MX6SL_PAD_AUD_TXC__AUD3_TXC 0x05c 0x2b4 0x000 0x0 0x0 -#define MX6SL_PAD_AUD_TXC__ECSPI3_MISO 0x05c 0x2b4 0x6b8 0x1 0x0 -#define MX6SL_PAD_AUD_TXC__UART4_TX_DATA 0x05c 0x2b4 0x000 0x2 0x0 -#define MX6SL_PAD_AUD_TXC__UART4_RX_DATA 0x05c 0x2b4 0x814 0x2 0x1 -#define MX6SL_PAD_AUD_TXC__FEC_RX_DV 0x05c 0x2b4 0x704 0x3 0x0 -#define MX6SL_PAD_AUD_TXC__SD2_LCTL 0x05c 0x2b4 0x000 0x4 0x0 -#define MX6SL_PAD_AUD_TXC__GPIO1_IO03 0x05c 0x2b4 0x000 0x5 0x0 -#define MX6SL_PAD_AUD_TXD__AUD3_TXD 0x060 0x2b8 0x000 0x0 0x0 -#define MX6SL_PAD_AUD_TXD__ECSPI3_SCLK 0x060 0x2b8 0x6b0 0x1 0x0 -#define MX6SL_PAD_AUD_TXD__UART4_CTS_B 0x060 0x2b8 0x000 0x2 0x0 -#define MX6SL_PAD_AUD_TXD__UART4_RTS_B 0x060 0x2b8 0x810 0x2 0x0 -#define MX6SL_PAD_AUD_TXD__FEC_TX_DATA0 0x060 0x2b8 0x000 0x3 0x0 -#define MX6SL_PAD_AUD_TXD__SD4_LCTL 0x060 0x2b8 0x000 0x4 0x0 -#define MX6SL_PAD_AUD_TXD__GPIO1_IO05 0x060 0x2b8 0x000 0x5 0x0 -#define MX6SL_PAD_AUD_TXFS__AUD3_TXFS 0x064 0x2bc 0x000 0x0 0x0 -#define MX6SL_PAD_AUD_TXFS__PWM3_OUT 0x064 0x2bc 0x000 0x1 0x0 -#define MX6SL_PAD_AUD_TXFS__UART4_RTS_B 0x064 0x2bc 0x810 0x2 0x1 -#define MX6SL_PAD_AUD_TXFS__UART4_CTS_B 0x064 0x2bc 0x000 0x2 0x0 -#define MX6SL_PAD_AUD_TXFS__FEC_RX_DATA1 0x064 0x2bc 0x6fc 0x3 0x0 -#define MX6SL_PAD_AUD_TXFS__SD3_LCTL 0x064 0x2bc 0x000 0x4 0x0 -#define MX6SL_PAD_AUD_TXFS__GPIO1_IO04 0x064 0x2bc 0x000 0x5 0x0 -#define MX6SL_PAD_ECSPI1_MISO__ECSPI1_MISO 0x068 0x358 0x684 0x0 0x0 -#define MX6SL_PAD_ECSPI1_MISO__AUD4_TXFS 0x068 0x358 0x5f8 0x1 0x0 -#define MX6SL_PAD_ECSPI1_MISO__UART5_RTS_B 0x068 0x358 0x818 0x2 0x0 -#define MX6SL_PAD_ECSPI1_MISO__UART5_CTS_B 0x068 0x358 0x000 0x2 0x0 -#define MX6SL_PAD_ECSPI1_MISO__EPDC_BDR0 0x068 0x358 0x000 0x3 0x0 -#define MX6SL_PAD_ECSPI1_MISO__SD2_WP 0x068 0x358 0x834 0x4 0x0 -#define MX6SL_PAD_ECSPI1_MISO__GPIO4_IO10 0x068 0x358 0x000 0x5 0x0 -#define MX6SL_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x06c 0x35c 0x688 0x0 0x0 -#define MX6SL_PAD_ECSPI1_MOSI__AUD4_TXC 0x06c 0x35c 0x5f4 0x1 0x0 -#define MX6SL_PAD_ECSPI1_MOSI__UART5_TX_DATA 0x06c 0x35c 0x000 0x2 0x0 -#define MX6SL_PAD_ECSPI1_MOSI__UART5_RX_DATA 0x06c 0x35c 0x81c 0x2 0x0 -#define MX6SL_PAD_ECSPI1_MOSI__EPDC_VCOM1 0x06c 0x35c 0x000 0x3 0x0 -#define MX6SL_PAD_ECSPI1_MOSI__SD2_VSELECT 0x06c 0x35c 0x000 0x4 0x0 -#define MX6SL_PAD_ECSPI1_MOSI__GPIO4_IO09 0x06c 0x35c 0x000 0x5 0x0 -#define MX6SL_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x070 0x360 0x67c 0x0 0x0 -#define MX6SL_PAD_ECSPI1_SCLK__AUD4_TXD 0x070 0x360 0x5e8 0x1 0x0 -#define MX6SL_PAD_ECSPI1_SCLK__UART5_RX_DATA 0x070 0x360 0x81c 0x2 0x1 -#define MX6SL_PAD_ECSPI1_SCLK__UART5_TX_DATA 0x070 0x360 0x000 0x2 0x0 -#define MX6SL_PAD_ECSPI1_SCLK__EPDC_VCOM0 0x070 0x360 0x000 0x3 0x0 -#define MX6SL_PAD_ECSPI1_SCLK__SD2_RESET 0x070 0x360 0x000 0x4 0x0 -#define MX6SL_PAD_ECSPI1_SCLK__GPIO4_IO08 0x070 0x360 0x000 0x5 0x0 -#define MX6SL_PAD_ECSPI1_SCLK__USB_OTG2_OC 0x070 0x360 0x820 0x6 0x0 -#define MX6SL_PAD_ECSPI1_SS0__ECSPI1_SS0 0x074 0x364 0x68c 0x0 0x0 -#define MX6SL_PAD_ECSPI1_SS0__AUD4_RXD 0x074 0x364 0x5e4 0x1 0x0 -#define MX6SL_PAD_ECSPI1_SS0__UART5_CTS_B 0x074 0x364 0x000 0x2 0x0 -#define MX6SL_PAD_ECSPI1_SS0__UART5_RTS_B 0x074 0x364 0x818 0x2 0x1 -#define MX6SL_PAD_ECSPI1_SS0__EPDC_BDR1 0x074 0x364 0x000 0x3 0x0 -#define MX6SL_PAD_ECSPI1_SS0__SD2_CD_B 0x074 0x364 0x830 0x4 0x0 -#define MX6SL_PAD_ECSPI1_SS0__GPIO4_IO11 0x074 0x364 0x000 0x5 0x0 -#define MX6SL_PAD_ECSPI1_SS0__USB_OTG2_PWR 0x074 0x364 0x000 0x6 0x0 -#define MX6SL_PAD_ECSPI2_MISO__ECSPI2_MISO 0x078 0x368 0x6a0 0x0 0x0 -#define MX6SL_PAD_ECSPI2_MISO__SDMA_EXT_EVENT0 0x078 0x368 0x000 0x1 0x0 -#define MX6SL_PAD_ECSPI2_MISO__UART3_RTS_B 0x078 0x368 0x808 0x2 0x0 -#define MX6SL_PAD_ECSPI2_MISO__UART3_CTS_B 0x078 0x368 0x000 0x2 0x0 -#define MX6SL_PAD_ECSPI2_MISO__CSI_MCLK 0x078 0x368 0x000 0x3 0x0 -#define MX6SL_PAD_ECSPI2_MISO__SD1_WP 0x078 0x368 0x82c 0x4 0x0 -#define MX6SL_PAD_ECSPI2_MISO__GPIO4_IO14 0x078 0x368 0x000 0x5 0x0 -#define MX6SL_PAD_ECSPI2_MISO__USB_OTG1_OC 0x078 0x368 0x824 0x6 0x0 -#define MX6SL_PAD_ECSPI2_MOSI__ECSPI2_MOSI 0x07c 0x36c 0x6a4 0x0 0x0 -#define MX6SL_PAD_ECSPI2_MOSI__SDMA_EXT_EVENT1 0x07c 0x36c 0x000 0x1 0x0 -#define MX6SL_PAD_ECSPI2_MOSI__UART3_TX_DATA 0x07c 0x36c 0x000 0x2 0x0 -#define MX6SL_PAD_ECSPI2_MOSI__UART3_RX_DATA 0x07c 0x36c 0x80c 0x2 0x2 -#define MX6SL_PAD_ECSPI2_MOSI__CSI_HSYNC 0x07c 0x36c 0x670 0x3 0x0 -#define MX6SL_PAD_ECSPI2_MOSI__SD1_VSELECT 0x07c 0x36c 0x000 0x4 0x0 -#define MX6SL_PAD_ECSPI2_MOSI__GPIO4_IO13 0x07c 0x36c 0x000 0x5 0x0 -#define MX6SL_PAD_ECSPI2_SCLK__ECSPI2_SCLK 0x080 0x370 0x69c 0x0 0x0 -#define MX6SL_PAD_ECSPI2_SCLK__SPDIF_EXT_CLK 0x080 0x370 0x7f4 0x1 0x1 -#define MX6SL_PAD_ECSPI2_SCLK__UART3_RX_DATA 0x080 0x370 0x80c 0x2 0x3 -#define MX6SL_PAD_ECSPI2_SCLK__UART3_TX_DATA 0x080 0x370 0x000 0x2 0x0 -#define MX6SL_PAD_ECSPI2_SCLK__CSI_PIXCLK 0x080 0x370 0x674 0x3 0x0 -#define MX6SL_PAD_ECSPI2_SCLK__SD1_RESET 0x080 0x370 0x000 0x4 0x0 -#define MX6SL_PAD_ECSPI2_SCLK__GPIO4_IO12 0x080 0x370 0x000 0x5 0x0 -#define MX6SL_PAD_ECSPI2_SCLK__USB_OTG2_OC 0x080 0x370 0x820 0x6 0x1 -#define MX6SL_PAD_ECSPI2_SS0__ECSPI2_SS0 0x084 0x374 0x6a8 0x0 0x0 -#define MX6SL_PAD_ECSPI2_SS0__ECSPI1_SS3 0x084 0x374 0x698 0x1 0x0 -#define MX6SL_PAD_ECSPI2_SS0__UART3_CTS_B 0x084 0x374 0x000 0x2 0x0 -#define MX6SL_PAD_ECSPI2_SS0__UART3_RTS_B 0x084 0x374 0x808 0x2 0x1 -#define MX6SL_PAD_ECSPI2_SS0__CSI_VSYNC 0x084 0x374 0x678 0x3 0x0 -#define MX6SL_PAD_ECSPI2_SS0__SD1_CD_B 0x084 0x374 0x828 0x4 0x0 -#define MX6SL_PAD_ECSPI2_SS0__GPIO4_IO15 0x084 0x374 0x000 0x5 0x0 -#define MX6SL_PAD_ECSPI2_SS0__USB_OTG1_PWR 0x084 0x374 0x000 0x6 0x0 -#define MX6SL_PAD_EPDC_BDR0__EPDC_BDR0 0x088 0x378 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_BDR0__SD4_CLK 0x088 0x378 0x850 0x1 0x0 -#define MX6SL_PAD_EPDC_BDR0__UART3_RTS_B 0x088 0x378 0x808 0x2 0x2 -#define MX6SL_PAD_EPDC_BDR0__UART3_CTS_B 0x088 0x378 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_BDR0__EIM_ADDR26 0x088 0x378 0x000 0x3 0x0 -#define MX6SL_PAD_EPDC_BDR0__SPDC_RL 0x088 0x378 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_BDR0__GPIO2_IO05 0x088 0x378 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_BDR0__EPDC_SDCE7 0x088 0x378 0x000 0x6 0x0 -#define MX6SL_PAD_EPDC_BDR1__EPDC_BDR1 0x08c 0x37c 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_BDR1__SD4_CMD 0x08c 0x37c 0x858 0x1 0x0 -#define MX6SL_PAD_EPDC_BDR1__UART3_CTS_B 0x08c 0x37c 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_BDR1__UART3_RTS_B 0x08c 0x37c 0x808 0x2 0x3 -#define MX6SL_PAD_EPDC_BDR1__EIM_CRE 0x08c 0x37c 0x000 0x3 0x0 -#define MX6SL_PAD_EPDC_BDR1__SPDC_UD 0x08c 0x37c 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_BDR1__GPIO2_IO06 0x08c 0x37c 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_BDR1__EPDC_SDCE8 0x08c 0x37c 0x000 0x6 0x0 -#define MX6SL_PAD_EPDC_D0__EPDC_DATA00 0x090 0x380 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_D0__ECSPI4_MOSI 0x090 0x380 0x6d8 0x1 0x0 -#define MX6SL_PAD_EPDC_D0__LCD_DATA24 0x090 0x380 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_D0__CSI_DATA00 0x090 0x380 0x630 0x3 0x0 -#define MX6SL_PAD_EPDC_D0__SPDC_DATA00 0x090 0x380 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_D0__GPIO1_IO07 0x090 0x380 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_D1__EPDC_DATA01 0x094 0x384 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_D1__ECSPI4_MISO 0x094 0x384 0x6d4 0x1 0x0 -#define MX6SL_PAD_EPDC_D1__LCD_DATA25 0x094 0x384 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_D1__CSI_DATA01 0x094 0x384 0x634 0x3 0x0 -#define MX6SL_PAD_EPDC_D1__SPDC_DATA01 0x094 0x384 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_D1__GPIO1_IO08 0x094 0x384 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_D10__EPDC_DATA10 0x098 0x388 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_D10__ECSPI3_SS0 0x098 0x388 0x6c0 0x1 0x1 -#define MX6SL_PAD_EPDC_D10__EPDC_PWR_CTRL2 0x098 0x388 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_D10__EIM_ADDR18 0x098 0x388 0x000 0x3 0x0 -#define MX6SL_PAD_EPDC_D10__SPDC_DATA10 0x098 0x388 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_D10__GPIO1_IO17 0x098 0x388 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_D10__SD4_WP 0x098 0x388 0x87c 0x6 0x0 -#define MX6SL_PAD_EPDC_D11__EPDC_DATA11 0x09c 0x38c 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_D11__ECSPI3_SCLK 0x09c 0x38c 0x6b0 0x1 0x1 -#define MX6SL_PAD_EPDC_D11__EPDC_PWR_CTRL3 0x09c 0x38c 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_D11__EIM_ADDR19 0x09c 0x38c 0x000 0x3 0x0 -#define MX6SL_PAD_EPDC_D11__SPDC_DATA11 0x09c 0x38c 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_D11__GPIO1_IO18 0x09c 0x38c 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_D11__SD4_CD_B 0x09c 0x38c 0x854 0x6 0x0 -#define MX6SL_PAD_EPDC_D12__EPDC_DATA12 0x0a0 0x390 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_D12__UART2_RX_DATA 0x0a0 0x390 0x804 0x1 0x0 -#define MX6SL_PAD_EPDC_D12__UART2_TX_DATA 0x0a0 0x390 0x000 0x1 0x0 -#define MX6SL_PAD_EPDC_D12__EPDC_PWR_COM 0x0a0 0x390 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_D12__EIM_ADDR20 0x0a0 0x390 0x000 0x3 0x0 -#define MX6SL_PAD_EPDC_D12__SPDC_DATA12 0x0a0 0x390 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_D12__GPIO1_IO19 0x0a0 0x390 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_D12__ECSPI3_SS1 0x0a0 0x390 0x6c4 0x6 0x1 -#define MX6SL_PAD_EPDC_D13__EPDC_DATA13 0x0a4 0x394 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_D13__UART2_TX_DATA 0x0a4 0x394 0x000 0x1 0x0 -#define MX6SL_PAD_EPDC_D13__UART2_RX_DATA 0x0a4 0x394 0x804 0x1 0x1 -#define MX6SL_PAD_EPDC_D13__EPDC_PWR_IRQ 0x0a4 0x394 0x6e8 0x2 0x0 -#define MX6SL_PAD_EPDC_D13__EIM_ADDR21 0x0a4 0x394 0x000 0x3 0x0 -#define MX6SL_PAD_EPDC_D13__SPDC_DATA13 0x0a4 0x394 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_D13__GPIO1_IO20 0x0a4 0x394 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_D13__ECSPI3_SS2 0x0a4 0x394 0x6c8 0x6 0x0 -#define MX6SL_PAD_EPDC_D14__EPDC_DATA14 0x0a8 0x398 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_D14__UART2_RTS_B 0x0a8 0x398 0x800 0x1 0x0 -#define MX6SL_PAD_EPDC_D14__UART2_CTS_B 0x0a8 0x398 0x000 0x1 0x0 -#define MX6SL_PAD_EPDC_D14__EPDC_PWR_STAT 0x0a8 0x398 0x6ec 0x2 0x0 -#define MX6SL_PAD_EPDC_D14__EIM_ADDR22 0x0a8 0x398 0x000 0x3 0x0 -#define MX6SL_PAD_EPDC_D14__SPDC_DATA14 0x0a8 0x398 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_D14__GPIO1_IO21 0x0a8 0x398 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_D14__ECSPI3_SS3 0x0a8 0x398 0x6cc 0x6 0x0 -#define MX6SL_PAD_EPDC_D15__EPDC_DATA15 0x0ac 0x39c 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_D15__UART2_CTS_B 0x0ac 0x39c 0x000 0x1 0x0 -#define MX6SL_PAD_EPDC_D15__UART2_RTS_B 0x0ac 0x39c 0x800 0x1 0x1 -#define MX6SL_PAD_EPDC_D15__EPDC_PWR_WAKE 0x0ac 0x39c 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_D15__EIM_ADDR23 0x0ac 0x39c 0x000 0x3 0x0 -#define MX6SL_PAD_EPDC_D15__SPDC_DATA15 0x0ac 0x39c 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_D15__GPIO1_IO22 0x0ac 0x39c 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_D15__ECSPI3_RDY 0x0ac 0x39c 0x6b4 0x6 0x1 -#define MX6SL_PAD_EPDC_D2__EPDC_DATA02 0x0b0 0x3a0 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_D2__ECSPI4_SS0 0x0b0 0x3a0 0x6dc 0x1 0x0 -#define MX6SL_PAD_EPDC_D2__LCD_DATA26 0x0b0 0x3a0 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_D2__CSI_DATA02 0x0b0 0x3a0 0x638 0x3 0x0 -#define MX6SL_PAD_EPDC_D2__SPDC_DATA02 0x0b0 0x3a0 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_D2__GPIO1_IO09 0x0b0 0x3a0 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_D3__EPDC_DATA03 0x0b4 0x3a4 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_D3__ECSPI4_SCLK 0x0b4 0x3a4 0x6d0 0x1 0x0 -#define MX6SL_PAD_EPDC_D3__LCD_DATA27 0x0b4 0x3a4 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_D3__CSI_DATA03 0x0b4 0x3a4 0x63c 0x3 0x0 -#define MX6SL_PAD_EPDC_D3__SPDC_DATA03 0x0b4 0x3a4 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_D3__GPIO1_IO10 0x0b4 0x3a4 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_D4__EPDC_DATA04 0x0b8 0x3a8 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_D4__ECSPI4_SS1 0x0b8 0x3a8 0x6e0 0x1 0x0 -#define MX6SL_PAD_EPDC_D4__LCD_DATA28 0x0b8 0x3a8 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_D4__CSI_DATA04 0x0b8 0x3a8 0x640 0x3 0x0 -#define MX6SL_PAD_EPDC_D4__SPDC_DATA04 0x0b8 0x3a8 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_D4__GPIO1_IO11 0x0b8 0x3a8 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_D5__EPDC_DATA05 0x0bc 0x3ac 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_D5__ECSPI4_SS2 0x0bc 0x3ac 0x6e4 0x1 0x0 -#define MX6SL_PAD_EPDC_D5__LCD_DATA29 0x0bc 0x3ac 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_D5__CSI_DATA05 0x0bc 0x3ac 0x644 0x3 0x0 -#define MX6SL_PAD_EPDC_D5__SPDC_DATA05 0x0bc 0x3ac 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_D5__GPIO1_IO12 0x0bc 0x3ac 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_D6__EPDC_DATA06 0x0c0 0x3b0 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_D6__ECSPI4_SS3 0x0c0 0x3b0 0x000 0x1 0x0 -#define MX6SL_PAD_EPDC_D6__LCD_DATA30 0x0c0 0x3b0 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_D6__CSI_DATA06 0x0c0 0x3b0 0x648 0x3 0x0 -#define MX6SL_PAD_EPDC_D6__SPDC_DATA06 0x0c0 0x3b0 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_D6__GPIO1_IO13 0x0c0 0x3b0 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_D7__EPDC_DATA07 0x0c4 0x3b4 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_D7__ECSPI4_RDY 0x0c4 0x3b4 0x000 0x1 0x0 -#define MX6SL_PAD_EPDC_D7__LCD_DATA31 0x0c4 0x3b4 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_D7__CSI_DATA07 0x0c4 0x3b4 0x64c 0x3 0x0 -#define MX6SL_PAD_EPDC_D7__SPDC_DATA07 0x0c4 0x3b4 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_D7__GPIO1_IO14 0x0c4 0x3b4 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_D8__EPDC_DATA08 0x0c8 0x3b8 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_D8__ECSPI3_MOSI 0x0c8 0x3b8 0x6bc 0x1 0x1 -#define MX6SL_PAD_EPDC_D8__EPDC_PWR_CTRL0 0x0c8 0x3b8 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_D8__EIM_ADDR16 0x0c8 0x3b8 0x000 0x3 0x0 -#define MX6SL_PAD_EPDC_D8__SPDC_DATA08 0x0c8 0x3b8 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_D8__GPIO1_IO15 0x0c8 0x3b8 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_D8__SD4_RESET 0x0c8 0x3b8 0x000 0x6 0x0 -#define MX6SL_PAD_EPDC_D9__EPDC_DATA09 0x0cc 0x3bc 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_D9__ECSPI3_MISO 0x0cc 0x3bc 0x6b8 0x1 0x1 -#define MX6SL_PAD_EPDC_D9__EPDC_PWR_CTRL1 0x0cc 0x3bc 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_D9__EIM_ADDR17 0x0cc 0x3bc 0x000 0x3 0x0 -#define MX6SL_PAD_EPDC_D9__SPDC_DATA09 0x0cc 0x3bc 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_D9__GPIO1_IO16 0x0cc 0x3bc 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_D9__SD4_VSELECT 0x0cc 0x3bc 0x000 0x6 0x0 -#define MX6SL_PAD_EPDC_GDCLK__EPDC_GDCLK 0x0d0 0x3c0 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_GDCLK__ECSPI2_SS2 0x0d0 0x3c0 0x000 0x1 0x0 -#define MX6SL_PAD_EPDC_GDCLK__SPDC_YCKR 0x0d0 0x3c0 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_GDCLK__CSI_PIXCLK 0x0d0 0x3c0 0x674 0x3 0x1 -#define MX6SL_PAD_EPDC_GDCLK__SPDC_YCKL 0x0d0 0x3c0 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_GDCLK__GPIO1_IO31 0x0d0 0x3c0 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_GDCLK__SD2_RESET 0x0d0 0x3c0 0x000 0x6 0x0 -#define MX6SL_PAD_EPDC_GDOE__EPDC_GDOE 0x0d4 0x3c4 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_GDOE__ECSPI2_SS3 0x0d4 0x3c4 0x000 0x1 0x0 -#define MX6SL_PAD_EPDC_GDOE__SPDC_YOER 0x0d4 0x3c4 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_GDOE__CSI_HSYNC 0x0d4 0x3c4 0x670 0x3 0x1 -#define MX6SL_PAD_EPDC_GDOE__SPDC_YOEL 0x0d4 0x3c4 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_GDOE__GPIO2_IO00 0x0d4 0x3c4 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_GDOE__SD2_VSELECT 0x0d4 0x3c4 0x000 0x6 0x0 -#define MX6SL_PAD_EPDC_GDRL__EPDC_GDRL 0x0d8 0x3c8 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_GDRL__ECSPI2_RDY 0x0d8 0x3c8 0x000 0x1 0x0 -#define MX6SL_PAD_EPDC_GDRL__SPDC_YDIOUR 0x0d8 0x3c8 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_GDRL__CSI_MCLK 0x0d8 0x3c8 0x000 0x3 0x0 -#define MX6SL_PAD_EPDC_GDRL__SPDC_YDIOUL 0x0d8 0x3c8 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_GDRL__GPIO2_IO01 0x0d8 0x3c8 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_GDRL__SD2_WP 0x0d8 0x3c8 0x834 0x6 0x1 -#define MX6SL_PAD_EPDC_GDSP__EPDC_GDSP 0x0dc 0x3cc 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_GDSP__PWM4_OUT 0x0dc 0x3cc 0x000 0x1 0x0 -#define MX6SL_PAD_EPDC_GDSP__SPDC_YDIODR 0x0dc 0x3cc 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_GDSP__CSI_VSYNC 0x0dc 0x3cc 0x678 0x3 0x1 -#define MX6SL_PAD_EPDC_GDSP__SPDC_YDIODL 0x0dc 0x3cc 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_GDSP__GPIO2_IO02 0x0dc 0x3cc 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_GDSP__SD2_CD_B 0x0dc 0x3cc 0x830 0x6 0x1 -#define MX6SL_PAD_EPDC_PWRCOM__EPDC_PWR_COM 0x0e0 0x3d0 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_PWRCOM__SD4_DATA0 0x0e0 0x3d0 0x85c 0x1 0x0 -#define MX6SL_PAD_EPDC_PWRCOM__LCD_DATA20 0x0e0 0x3d0 0x7c8 0x2 0x0 -#define MX6SL_PAD_EPDC_PWRCOM__EIM_BCLK 0x0e0 0x3d0 0x000 0x3 0x0 -#define MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID 0x0e0 0x3d0 0x5dc 0x4 0x0 -#define MX6SL_PAD_EPDC_PWRCOM__GPIO2_IO11 0x0e0 0x3d0 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_PWRCOM__SD3_RESET 0x0e0 0x3d0 0x000 0x6 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL0__EPDC_PWR_CTRL0 0x0e4 0x3d4 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL0__AUD5_RXC 0x0e4 0x3d4 0x604 0x1 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL0__LCD_DATA16 0x0e4 0x3d4 0x7b8 0x2 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL0__EIM_RW 0x0e4 0x3d4 0x000 0x3 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL0__SPDC_YCKL 0x0e4 0x3d4 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL0__GPIO2_IO07 0x0e4 0x3d4 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL0__SD4_RESET 0x0e4 0x3d4 0x000 0x6 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL1__EPDC_PWR_CTRL1 0x0e8 0x3d8 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL1__AUD5_TXFS 0x0e8 0x3d8 0x610 0x1 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL1__LCD_DATA17 0x0e8 0x3d8 0x7bc 0x2 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL1__EIM_OE_B 0x0e8 0x3d8 0x000 0x3 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL1__SPDC_YOEL 0x0e8 0x3d8 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL1__GPIO2_IO08 0x0e8 0x3d8 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL1__SD4_VSELECT 0x0e8 0x3d8 0x000 0x6 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL2__EPDC_PWR_CTRL2 0x0ec 0x3dc 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL2__AUD5_TXD 0x0ec 0x3dc 0x600 0x1 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL2__LCD_DATA18 0x0ec 0x3dc 0x7c0 0x2 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL2__EIM_CS0_B 0x0ec 0x3dc 0x000 0x3 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL2__SPDC_YDIOUL 0x0ec 0x3dc 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL2__GPIO2_IO09 0x0ec 0x3dc 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL2__SD4_WP 0x0ec 0x3dc 0x87c 0x6 0x1 -#define MX6SL_PAD_EPDC_PWRCTRL3__EPDC_PWR_CTRL3 0x0f0 0x3e0 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL3__AUD5_TXC 0x0f0 0x3e0 0x60c 0x1 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL3__LCD_DATA19 0x0f0 0x3e0 0x7c4 0x2 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL3__EIM_CS1_B 0x0f0 0x3e0 0x000 0x3 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL3__SPDC_YDIODL 0x0f0 0x3e0 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL3__GPIO2_IO10 0x0f0 0x3e0 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL3__SD4_CD_B 0x0f0 0x3e0 0x854 0x6 0x1 -#define MX6SL_PAD_EPDC_PWRINT__EPDC_PWR_IRQ 0x0f4 0x3e4 0x6e8 0x0 0x1 -#define MX6SL_PAD_EPDC_PWRINT__SD4_DATA1 0x0f4 0x3e4 0x860 0x1 0x0 -#define MX6SL_PAD_EPDC_PWRINT__LCD_DATA21 0x0f4 0x3e4 0x7cc 0x2 0x0 -#define MX6SL_PAD_EPDC_PWRINT__EIM_ACLK_FREERUN 0x0f4 0x3e4 0x000 0x3 0x0 -#define MX6SL_PAD_EPDC_PWRINT__USB_OTG2_ID 0x0f4 0x3e4 0x5e0 0x4 0x0 -#define MX6SL_PAD_EPDC_PWRINT__GPIO2_IO12 0x0f4 0x3e4 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_PWRINT__SD3_VSELECT 0x0f4 0x3e4 0x000 0x6 0x0 -#define MX6SL_PAD_EPDC_PWRSTAT__EPDC_PWR_STAT 0x0f8 0x3e8 0x6ec 0x0 0x1 -#define MX6SL_PAD_EPDC_PWRSTAT__SD4_DATA2 0x0f8 0x3e8 0x864 0x1 0x0 -#define MX6SL_PAD_EPDC_PWRSTAT__LCD_DATA22 0x0f8 0x3e8 0x7d0 0x2 0x0 -#define MX6SL_PAD_EPDC_PWRSTAT__EIM_WAIT_B 0x0f8 0x3e8 0x884 0x3 0x0 -#define MX6SL_PAD_EPDC_PWRSTAT__ARM_EVENTI 0x0f8 0x3e8 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_PWRSTAT__GPIO2_IO13 0x0f8 0x3e8 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_PWRSTAT__SD3_WP 0x0f8 0x3e8 0x84c 0x6 0x0 -#define MX6SL_PAD_EPDC_PWRWAKEUP__EPDC_PWR_WAKE 0x0fc 0x3ec 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_PWRWAKEUP__SD4_DATA3 0x0fc 0x3ec 0x868 0x1 0x0 -#define MX6SL_PAD_EPDC_PWRWAKEUP__LCD_DATA23 0x0fc 0x3ec 0x7d4 0x2 0x0 -#define MX6SL_PAD_EPDC_PWRWAKEUP__EIM_DTACK_B 0x0fc 0x3ec 0x880 0x3 0x0 -#define MX6SL_PAD_EPDC_PWRWAKEUP__ARM_EVENTO 0x0fc 0x3ec 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_PWRWAKEUP__GPIO2_IO14 0x0fc 0x3ec 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_PWRWAKEUP__SD3_CD_B 0x0fc 0x3ec 0x838 0x6 0x0 -#define MX6SL_PAD_EPDC_SDCE0__EPDC_SDCE0 0x100 0x3f0 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_SDCE0__ECSPI2_SS1 0x100 0x3f0 0x6ac 0x1 0x0 -#define MX6SL_PAD_EPDC_SDCE0__PWM3_OUT 0x100 0x3f0 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_SDCE0__EIM_CS2_B 0x100 0x3f0 0x000 0x3 0x0 -#define MX6SL_PAD_EPDC_SDCE0__SPDC_YCKR 0x100 0x3f0 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_SDCE0__GPIO1_IO27 0x100 0x3f0 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_SDCE1__EPDC_SDCE1 0x104 0x3f4 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_SDCE1__WDOG2_B 0x104 0x3f4 0x000 0x1 0x0 -#define MX6SL_PAD_EPDC_SDCE1__PWM4_OUT 0x104 0x3f4 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_SDCE1__EIM_LBA_B 0x104 0x3f4 0x000 0x3 0x0 -#define MX6SL_PAD_EPDC_SDCE1__SPDC_YOER 0x104 0x3f4 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_SDCE1__GPIO1_IO28 0x104 0x3f4 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_SDCE2__EPDC_SDCE2 0x108 0x3f8 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_SDCE2__I2C3_SCL 0x108 0x3f8 0x72c 0x1 0x1 -#define MX6SL_PAD_EPDC_SDCE2__PWM1_OUT 0x108 0x3f8 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_SDCE2__EIM_EB0_B 0x108 0x3f8 0x000 0x3 0x0 -#define MX6SL_PAD_EPDC_SDCE2__SPDC_YDIOUR 0x108 0x3f8 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_SDCE2__GPIO1_IO29 0x108 0x3f8 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_SDCE3__EPDC_SDCE3 0x10c 0x3fc 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_SDCE3__I2C3_SDA 0x10c 0x3fc 0x730 0x1 0x1 -#define MX6SL_PAD_EPDC_SDCE3__PWM2_OUT 0x10c 0x3fc 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_SDCE3__EIM_EB1_B 0x10c 0x3fc 0x000 0x3 0x0 -#define MX6SL_PAD_EPDC_SDCE3__SPDC_YDIODR 0x10c 0x3fc 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_SDCE3__GPIO1_IO30 0x10c 0x3fc 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_SDCLK__EPDC_SDCLK_P 0x110 0x400 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_SDCLK__ECSPI2_MOSI 0x110 0x400 0x6a4 0x1 0x1 -#define MX6SL_PAD_EPDC_SDCLK__I2C2_SCL 0x110 0x400 0x724 0x2 0x0 -#define MX6SL_PAD_EPDC_SDCLK__CSI_DATA08 0x110 0x400 0x650 0x3 0x0 -#define MX6SL_PAD_EPDC_SDCLK__SPDC_CL 0x110 0x400 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_SDCLK__GPIO1_IO23 0x110 0x400 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_SDLE__EPDC_SDLE 0x114 0x404 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_SDLE__ECSPI2_MISO 0x114 0x404 0x6a0 0x1 0x1 -#define MX6SL_PAD_EPDC_SDLE__I2C2_SDA 0x114 0x404 0x728 0x2 0x0 -#define MX6SL_PAD_EPDC_SDLE__CSI_DATA09 0x114 0x404 0x654 0x3 0x0 -#define MX6SL_PAD_EPDC_SDLE__SPDC_LD 0x114 0x404 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_SDLE__GPIO1_IO24 0x114 0x404 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_SDOE__EPDC_SDOE 0x118 0x408 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_SDOE__ECSPI2_SS0 0x118 0x408 0x6a8 0x1 0x1 -#define MX6SL_PAD_EPDC_SDOE__SPDC_XDIOR 0x118 0x408 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_SDOE__CSI_DATA10 0x118 0x408 0x658 0x3 0x0 -#define MX6SL_PAD_EPDC_SDOE__SPDC_XDIOL 0x118 0x408 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_SDOE__GPIO1_IO25 0x118 0x408 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_SDSHR__EPDC_SDSHR 0x11c 0x40c 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_SDSHR__ECSPI2_SCLK 0x11c 0x40c 0x69c 0x1 0x1 -#define MX6SL_PAD_EPDC_SDSHR__EPDC_SDCE4 0x11c 0x40c 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_SDSHR__CSI_DATA11 0x11c 0x40c 0x65c 0x3 0x0 -#define MX6SL_PAD_EPDC_SDSHR__SPDC_XDIOR 0x11c 0x40c 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_SDSHR__GPIO1_IO26 0x11c 0x40c 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_VCOM0__EPDC_VCOM0 0x120 0x410 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_VCOM0__AUD5_RXFS 0x120 0x410 0x608 0x1 0x0 -#define MX6SL_PAD_EPDC_VCOM0__UART3_RX_DATA 0x120 0x410 0x80c 0x2 0x4 -#define MX6SL_PAD_EPDC_VCOM0__UART3_TX_DATA 0x120 0x410 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_VCOM0__EIM_ADDR24 0x120 0x410 0x000 0x3 0x0 -#define MX6SL_PAD_EPDC_VCOM0__SPDC_VCOM0 0x120 0x410 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_VCOM0__GPIO2_IO03 0x120 0x410 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_VCOM0__EPDC_SDCE5 0x120 0x410 0x000 0x6 0x0 -#define MX6SL_PAD_EPDC_VCOM1__EPDC_VCOM1 0x124 0x414 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_VCOM1__AUD5_RXD 0x124 0x414 0x5fc 0x1 0x0 -#define MX6SL_PAD_EPDC_VCOM1__UART3_TX_DATA 0x124 0x414 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_VCOM1__UART3_RX_DATA 0x124 0x414 0x80c 0x2 0x5 -#define MX6SL_PAD_EPDC_VCOM1__EIM_ADDR25 0x124 0x414 0x000 0x3 0x0 -#define MX6SL_PAD_EPDC_VCOM1__SPDC_VCOM1 0x124 0x414 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_VCOM1__GPIO2_IO04 0x124 0x414 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_VCOM1__EPDC_SDCE6 0x124 0x414 0x000 0x6 0x0 -#define MX6SL_PAD_FEC_CRS_DV__FEC_RX_DV 0x128 0x418 0x704 0x0 0x1 -#define MX6SL_PAD_FEC_CRS_DV__SD4_DATA1 0x128 0x418 0x860 0x1 0x1 -#define MX6SL_PAD_FEC_CRS_DV__AUD6_TXC 0x128 0x418 0x624 0x2 0x0 -#define MX6SL_PAD_FEC_CRS_DV__ECSPI4_MISO 0x128 0x418 0x6d4 0x3 0x1 -#define MX6SL_PAD_FEC_CRS_DV__GPT_COMPARE2 0x128 0x418 0x000 0x4 0x0 -#define MX6SL_PAD_FEC_CRS_DV__GPIO4_IO25 0x128 0x418 0x000 0x5 0x0 -#define MX6SL_PAD_FEC_CRS_DV__ARM_TRACE31 0x128 0x418 0x000 0x6 0x0 -#define MX6SL_PAD_FEC_MDC__FEC_MDC 0x12c 0x41c 0x000 0x0 0x0 -#define MX6SL_PAD_FEC_MDC__SD4_DATA4 0x12c 0x41c 0x86c 0x1 0x0 -#define MX6SL_PAD_FEC_MDC__AUDIO_CLK_OUT 0x12c 0x41c 0x000 0x2 0x0 -#define MX6SL_PAD_FEC_MDC__SD1_RESET 0x12c 0x41c 0x000 0x3 0x0 -#define MX6SL_PAD_FEC_MDC__SD3_RESET 0x12c 0x41c 0x000 0x4 0x0 -#define MX6SL_PAD_FEC_MDC__GPIO4_IO23 0x12c 0x41c 0x000 0x5 0x0 -#define MX6SL_PAD_FEC_MDC__ARM_TRACE29 0x12c 0x41c 0x000 0x6 0x0 -#define MX6SL_PAD_FEC_MDIO__FEC_MDIO 0x130 0x420 0x6f4 0x0 0x1 -#define MX6SL_PAD_FEC_MDIO__SD4_CLK 0x130 0x420 0x850 0x1 0x1 -#define MX6SL_PAD_FEC_MDIO__AUD6_RXFS 0x130 0x420 0x620 0x2 0x0 -#define MX6SL_PAD_FEC_MDIO__ECSPI4_SS0 0x130 0x420 0x6dc 0x3 0x1 -#define MX6SL_PAD_FEC_MDIO__GPT_CAPTURE1 0x130 0x420 0x710 0x4 0x0 -#define MX6SL_PAD_FEC_MDIO__GPIO4_IO20 0x130 0x420 0x000 0x5 0x0 -#define MX6SL_PAD_FEC_MDIO__ARM_TRACE26 0x130 0x420 0x000 0x6 0x0 -#define MX6SL_PAD_FEC_REF_CLK__FEC_REF_OUT 0x134 0x424 0x000 0x0 0x0 -#define MX6SL_PAD_FEC_REF_CLK__SD4_RESET 0x134 0x424 0x000 0x1 0x0 -#define MX6SL_PAD_FEC_REF_CLK__WDOG1_B 0x134 0x424 0x000 0x2 0x0 -#define MX6SL_PAD_FEC_REF_CLK__PWM4_OUT 0x134 0x424 0x000 0x3 0x0 -#define MX6SL_PAD_FEC_REF_CLK__CCM_PMIC_READY 0x134 0x424 0x62c 0x4 0x0 -#define MX6SL_PAD_FEC_REF_CLK__GPIO4_IO26 0x134 0x424 0x000 0x5 0x0 -#define MX6SL_PAD_FEC_REF_CLK__SPDIF_EXT_CLK 0x134 0x424 0x7f4 0x6 0x2 -#define MX6SL_PAD_FEC_RX_ER__FEC_RX_ER 0x138 0x428 0x708 0x0 0x1 -#define MX6SL_PAD_FEC_RX_ER__SD4_DATA0 0x138 0x428 0x85c 0x1 0x1 -#define MX6SL_PAD_FEC_RX_ER__AUD6_RXD 0x138 0x428 0x614 0x2 0x0 -#define MX6SL_PAD_FEC_RX_ER__ECSPI4_MOSI 0x138 0x428 0x6d8 0x3 0x1 -#define MX6SL_PAD_FEC_RX_ER__GPT_COMPARE1 0x138 0x428 0x000 0x4 0x0 -#define MX6SL_PAD_FEC_RX_ER__GPIO4_IO19 0x138 0x428 0x000 0x5 0x0 -#define MX6SL_PAD_FEC_RX_ER__ARM_TRACE25 0x138 0x428 0x000 0x6 0x0 -#define MX6SL_PAD_FEC_RXD0__FEC_RX_DATA0 0x13c 0x42c 0x6f8 0x0 0x0 -#define MX6SL_PAD_FEC_RXD0__SD4_DATA5 0x13c 0x42c 0x870 0x1 0x0 -#define MX6SL_PAD_FEC_RXD0__USB_OTG1_ID 0x13c 0x42c 0x5dc 0x2 0x1 -#define MX6SL_PAD_FEC_RXD0__SD1_VSELECT 0x13c 0x42c 0x000 0x3 0x0 -#define MX6SL_PAD_FEC_RXD0__SD3_VSELECT 0x13c 0x42c 0x000 0x4 0x0 -#define MX6SL_PAD_FEC_RXD0__GPIO4_IO17 0x13c 0x42c 0x000 0x5 0x0 -#define MX6SL_PAD_FEC_RXD0__ARM_TRACE24 0x13c 0x42c 0x000 0x6 0x0 -#define MX6SL_PAD_FEC_RXD1__FEC_RX_DATA1 0x140 0x430 0x6fc 0x0 0x1 -#define MX6SL_PAD_FEC_RXD1__SD4_DATA2 0x140 0x430 0x864 0x1 0x1 -#define MX6SL_PAD_FEC_RXD1__AUD6_TXFS 0x140 0x430 0x628 0x2 0x0 -#define MX6SL_PAD_FEC_RXD1__ECSPI4_SS1 0x140 0x430 0x6e0 0x3 0x1 -#define MX6SL_PAD_FEC_RXD1__GPT_COMPARE3 0x140 0x430 0x000 0x4 0x0 -#define MX6SL_PAD_FEC_RXD1__GPIO4_IO18 0x140 0x430 0x000 0x5 0x0 -#define MX6SL_PAD_FEC_RXD1__FEC_COL 0x140 0x430 0x6f0 0x6 0x0 -#define MX6SL_PAD_FEC_TX_CLK__FEC_TX_CLK 0x144 0x434 0x70c 0x0 0x1 -#define MX6SL_PAD_FEC_TX_CLK__SD4_CMD 0x144 0x434 0x858 0x1 0x1 -#define MX6SL_PAD_FEC_TX_CLK__AUD6_RXC 0x144 0x434 0x61c 0x2 0x0 -#define MX6SL_PAD_FEC_TX_CLK__ECSPI4_SCLK 0x144 0x434 0x6d0 0x3 0x1 -#define MX6SL_PAD_FEC_TX_CLK__GPT_CAPTURE2 0x144 0x434 0x714 0x4 0x0 -#define MX6SL_PAD_FEC_TX_CLK__GPIO4_IO21 0x144 0x434 0x000 0x5 0x0 -#define MX6SL_PAD_FEC_TX_CLK__ARM_TRACE27 0x144 0x434 0x000 0x6 0x0 -#define MX6SL_PAD_FEC_TX_EN__FEC_TX_EN 0x148 0x438 0x000 0x0 0x0 -#define MX6SL_PAD_FEC_TX_EN__SD4_DATA6 0x148 0x438 0x874 0x1 0x0 -#define MX6SL_PAD_FEC_TX_EN__SPDIF_IN 0x148 0x438 0x7f0 0x2 0x0 -#define MX6SL_PAD_FEC_TX_EN__SD1_WP 0x148 0x438 0x82c 0x3 0x1 -#define MX6SL_PAD_FEC_TX_EN__SD3_WP 0x148 0x438 0x84c 0x4 0x1 -#define MX6SL_PAD_FEC_TX_EN__GPIO4_IO22 0x148 0x438 0x000 0x5 0x0 -#define MX6SL_PAD_FEC_TX_EN__ARM_TRACE28 0x148 0x438 0x000 0x6 0x0 -#define MX6SL_PAD_FEC_TXD0__FEC_TX_DATA0 0x14c 0x43c 0x000 0x0 0x0 -#define MX6SL_PAD_FEC_TXD0__SD4_DATA3 0x14c 0x43c 0x868 0x1 0x1 -#define MX6SL_PAD_FEC_TXD0__AUD6_TXD 0x14c 0x43c 0x618 0x2 0x0 -#define MX6SL_PAD_FEC_TXD0__ECSPI4_SS2 0x14c 0x43c 0x6e4 0x3 0x1 -#define MX6SL_PAD_FEC_TXD0__GPT_CLKIN 0x14c 0x43c 0x718 0x4 0x0 -#define MX6SL_PAD_FEC_TXD0__GPIO4_IO24 0x14c 0x43c 0x000 0x5 0x0 -#define MX6SL_PAD_FEC_TXD0__ARM_TRACE30 0x14c 0x43c 0x000 0x6 0x0 -#define MX6SL_PAD_FEC_TXD1__FEC_TX_DATA1 0x150 0x440 0x000 0x0 0x0 -#define MX6SL_PAD_FEC_TXD1__SD4_DATA7 0x150 0x440 0x878 0x1 0x0 -#define MX6SL_PAD_FEC_TXD1__SPDIF_OUT 0x150 0x440 0x000 0x2 0x0 -#define MX6SL_PAD_FEC_TXD1__SD1_CD_B 0x150 0x440 0x828 0x3 0x1 -#define MX6SL_PAD_FEC_TXD1__SD3_CD_B 0x150 0x440 0x838 0x4 0x1 -#define MX6SL_PAD_FEC_TXD1__GPIO4_IO16 0x150 0x440 0x000 0x5 0x0 -#define MX6SL_PAD_FEC_TXD1__FEC_RX_CLK 0x150 0x440 0x700 0x6 0x0 -#define MX6SL_PAD_HSIC_DAT__USB_H_DATA 0x154 0x444 0x000 0x0 0x0 -#define MX6SL_PAD_HSIC_DAT__I2C1_SCL 0x154 0x444 0x71c 0x1 0x1 -#define MX6SL_PAD_HSIC_DAT__PWM1_OUT 0x154 0x444 0x000 0x2 0x0 -#define MX6SL_PAD_HSIC_DAT__XTALOSC_REF_CLK_24M 0x154 0x444 0x000 0x3 0x0 -#define MX6SL_PAD_HSIC_DAT__GPIO3_IO19 0x154 0x444 0x000 0x5 0x0 -#define MX6SL_PAD_HSIC_STROBE__USB_H_STROBE 0x158 0x448 0x000 0x0 0x0 -#define MX6SL_PAD_HSIC_STROBE__I2C1_SDA 0x158 0x448 0x720 0x1 0x1 -#define MX6SL_PAD_HSIC_STROBE__PWM2_OUT 0x158 0x448 0x000 0x2 0x0 -#define MX6SL_PAD_HSIC_STROBE__XTALOSC_REF_CLK_32K 0x158 0x448 0x000 0x3 0x0 -#define MX6SL_PAD_HSIC_STROBE__GPIO3_IO20 0x158 0x448 0x000 0x5 0x0 -#define MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x15c 0x44c 0x71c 0x0 0x2 -#define MX6SL_PAD_I2C1_SCL__UART1_RTS_B 0x15c 0x44c 0x7f8 0x1 0x0 -#define MX6SL_PAD_I2C1_SCL__UART1_CTS_B 0x15c 0x44c 0x000 0x1 0x0 -#define MX6SL_PAD_I2C1_SCL__ECSPI3_SS2 0x15c 0x44c 0x6c8 0x2 0x1 -#define MX6SL_PAD_I2C1_SCL__FEC_RX_DATA0 0x15c 0x44c 0x6f8 0x3 0x1 -#define MX6SL_PAD_I2C1_SCL__SD3_RESET 0x15c 0x44c 0x000 0x4 0x0 -#define MX6SL_PAD_I2C1_SCL__GPIO3_IO12 0x15c 0x44c 0x000 0x5 0x0 -#define MX6SL_PAD_I2C1_SCL__ECSPI1_SS1 0x15c 0x44c 0x690 0x6 0x0 -#define MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x160 0x450 0x720 0x0 0x2 -#define MX6SL_PAD_I2C1_SDA__UART1_CTS_B 0x160 0x450 0x000 0x1 0x0 -#define MX6SL_PAD_I2C1_SDA__UART1_RTS_B 0x160 0x450 0x7f8 0x1 0x1 -#define MX6SL_PAD_I2C1_SDA__ECSPI3_SS3 0x160 0x450 0x6cc 0x2 0x1 -#define MX6SL_PAD_I2C1_SDA__FEC_TX_EN 0x160 0x450 0x000 0x3 0x0 -#define MX6SL_PAD_I2C1_SDA__SD3_VSELECT 0x160 0x450 0x000 0x4 0x0 -#define MX6SL_PAD_I2C1_SDA__GPIO3_IO13 0x160 0x450 0x000 0x5 0x0 -#define MX6SL_PAD_I2C1_SDA__ECSPI1_SS2 0x160 0x450 0x694 0x6 0x0 -#define MX6SL_PAD_I2C2_SCL__I2C2_SCL 0x164 0x454 0x724 0x0 0x1 -#define MX6SL_PAD_I2C2_SCL__AUD4_RXFS 0x164 0x454 0x5f0 0x1 0x0 -#define MX6SL_PAD_I2C2_SCL__SPDIF_IN 0x164 0x454 0x7f0 0x2 0x1 -#define MX6SL_PAD_I2C2_SCL__FEC_TX_DATA1 0x164 0x454 0x000 0x3 0x0 -#define MX6SL_PAD_I2C2_SCL__SD3_WP 0x164 0x454 0x84c 0x4 0x2 -#define MX6SL_PAD_I2C2_SCL__GPIO3_IO14 0x164 0x454 0x000 0x5 0x0 -#define MX6SL_PAD_I2C2_SCL__ECSPI1_RDY 0x164 0x454 0x680 0x6 0x0 -#define MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x168 0x458 0x728 0x0 0x1 -#define MX6SL_PAD_I2C2_SDA__AUD4_RXC 0x168 0x458 0x5ec 0x1 0x0 -#define MX6SL_PAD_I2C2_SDA__SPDIF_OUT 0x168 0x458 0x000 0x2 0x0 -#define MX6SL_PAD_I2C2_SDA__FEC_REF_OUT 0x168 0x458 0x000 0x3 0x0 -#define MX6SL_PAD_I2C2_SDA__SD3_CD_B 0x168 0x458 0x838 0x4 0x2 -#define MX6SL_PAD_I2C2_SDA__GPIO3_IO15 0x168 0x458 0x000 0x5 0x0 -#define MX6SL_PAD_KEY_COL0__KEY_COL0 0x16c 0x474 0x734 0x0 0x0 -#define MX6SL_PAD_KEY_COL0__I2C2_SCL 0x16c 0x474 0x724 0x1 0x2 -#define MX6SL_PAD_KEY_COL0__LCD_DATA00 0x16c 0x474 0x778 0x2 0x0 -#define MX6SL_PAD_KEY_COL0__EIM_AD00 0x16c 0x474 0x000 0x3 0x0 -#define MX6SL_PAD_KEY_COL0__SD1_CD_B 0x16c 0x474 0x828 0x4 0x2 -#define MX6SL_PAD_KEY_COL0__GPIO3_IO24 0x16c 0x474 0x000 0x5 0x0 -#define MX6SL_PAD_KEY_COL1__KEY_COL1 0x170 0x478 0x738 0x0 0x0 -#define MX6SL_PAD_KEY_COL1__ECSPI4_MOSI 0x170 0x478 0x6d8 0x1 0x2 -#define MX6SL_PAD_KEY_COL1__LCD_DATA02 0x170 0x478 0x780 0x2 0x0 -#define MX6SL_PAD_KEY_COL1__EIM_AD02 0x170 0x478 0x000 0x3 0x0 -#define MX6SL_PAD_KEY_COL1__SD3_DATA4 0x170 0x478 0x83c 0x4 0x0 -#define MX6SL_PAD_KEY_COL1__GPIO3_IO26 0x170 0x478 0x000 0x5 0x0 -#define MX6SL_PAD_KEY_COL2__KEY_COL2 0x174 0x47c 0x73c 0x0 0x0 -#define MX6SL_PAD_KEY_COL2__ECSPI4_SS0 0x174 0x47c 0x6dc 0x1 0x2 -#define MX6SL_PAD_KEY_COL2__LCD_DATA04 0x174 0x47c 0x788 0x2 0x0 -#define MX6SL_PAD_KEY_COL2__EIM_AD04 0x174 0x47c 0x000 0x3 0x0 -#define MX6SL_PAD_KEY_COL2__SD3_DATA6 0x174 0x47c 0x844 0x4 0x0 -#define MX6SL_PAD_KEY_COL2__GPIO3_IO28 0x174 0x47c 0x000 0x5 0x0 -#define MX6SL_PAD_KEY_COL3__KEY_COL3 0x178 0x480 0x740 0x0 0x0 -#define MX6SL_PAD_KEY_COL3__AUD6_RXFS 0x178 0x480 0x620 0x1 0x1 -#define MX6SL_PAD_KEY_COL3__LCD_DATA06 0x178 0x480 0x790 0x2 0x0 -#define MX6SL_PAD_KEY_COL3__EIM_AD06 0x178 0x480 0x000 0x3 0x0 -#define MX6SL_PAD_KEY_COL3__SD4_DATA6 0x178 0x480 0x874 0x4 0x1 -#define MX6SL_PAD_KEY_COL3__GPIO3_IO30 0x178 0x480 0x000 0x5 0x0 -#define MX6SL_PAD_KEY_COL3__SD1_RESET 0x178 0x480 0x000 0x6 0x0 -#define MX6SL_PAD_KEY_COL4__KEY_COL4 0x17c 0x484 0x744 0x0 0x0 -#define MX6SL_PAD_KEY_COL4__AUD6_RXD 0x17c 0x484 0x614 0x1 0x1 -#define MX6SL_PAD_KEY_COL4__LCD_DATA08 0x17c 0x484 0x798 0x2 0x0 -#define MX6SL_PAD_KEY_COL4__EIM_AD08 0x17c 0x484 0x000 0x3 0x0 -#define MX6SL_PAD_KEY_COL4__SD4_CLK 0x17c 0x484 0x850 0x4 0x2 -#define MX6SL_PAD_KEY_COL4__GPIO4_IO00 0x17c 0x484 0x000 0x5 0x0 -#define MX6SL_PAD_KEY_COL4__USB_OTG1_PWR 0x17c 0x484 0x000 0x6 0x0 -#define MX6SL_PAD_KEY_COL5__KEY_COL5 0x180 0x488 0x748 0x0 0x0 -#define MX6SL_PAD_KEY_COL5__AUD6_TXFS 0x180 0x488 0x628 0x1 0x1 -#define MX6SL_PAD_KEY_COL5__LCD_DATA10 0x180 0x488 0x7a0 0x2 0x0 -#define MX6SL_PAD_KEY_COL5__EIM_AD10 0x180 0x488 0x000 0x3 0x0 -#define MX6SL_PAD_KEY_COL5__SD4_DATA0 0x180 0x488 0x85c 0x4 0x2 -#define MX6SL_PAD_KEY_COL5__GPIO4_IO02 0x180 0x488 0x000 0x5 0x0 -#define MX6SL_PAD_KEY_COL5__USB_OTG2_PWR 0x180 0x488 0x000 0x6 0x0 -#define MX6SL_PAD_KEY_COL6__KEY_COL6 0x184 0x48c 0x74c 0x0 0x0 -#define MX6SL_PAD_KEY_COL6__UART4_RX_DATA 0x184 0x48c 0x814 0x1 0x2 -#define MX6SL_PAD_KEY_COL6__UART4_TX_DATA 0x184 0x48c 0x000 0x1 0x0 -#define MX6SL_PAD_KEY_COL6__LCD_DATA12 0x184 0x48c 0x7a8 0x2 0x0 -#define MX6SL_PAD_KEY_COL6__EIM_AD12 0x184 0x48c 0x000 0x3 0x0 -#define MX6SL_PAD_KEY_COL6__SD4_DATA2 0x184 0x48c 0x864 0x4 0x2 -#define MX6SL_PAD_KEY_COL6__GPIO4_IO04 0x184 0x48c 0x000 0x5 0x0 -#define MX6SL_PAD_KEY_COL6__SD3_RESET 0x184 0x48c 0x000 0x6 0x0 -#define MX6SL_PAD_KEY_COL7__KEY_COL7 0x188 0x490 0x750 0x0 0x0 -#define MX6SL_PAD_KEY_COL7__UART4_RTS_B 0x188 0x490 0x810 0x1 0x2 -#define MX6SL_PAD_KEY_COL7__UART4_CTS_B 0x188 0x490 0x000 0x1 0x0 -#define MX6SL_PAD_KEY_COL7__LCD_DATA14 0x188 0x490 0x7b0 0x2 0x0 -#define MX6SL_PAD_KEY_COL7__EIM_AD14 0x188 0x490 0x000 0x3 0x0 -#define MX6SL_PAD_KEY_COL7__SD4_DATA4 0x188 0x490 0x86c 0x4 0x1 -#define MX6SL_PAD_KEY_COL7__GPIO4_IO06 0x188 0x490 0x000 0x5 0x0 -#define MX6SL_PAD_KEY_COL7__SD1_WP 0x188 0x490 0x82c 0x6 0x2 -#define MX6SL_PAD_KEY_ROW0__KEY_ROW0 0x18c 0x494 0x754 0x0 0x0 -#define MX6SL_PAD_KEY_ROW0__I2C2_SDA 0x18c 0x494 0x728 0x1 0x2 -#define MX6SL_PAD_KEY_ROW0__LCD_DATA01 0x18c 0x494 0x77c 0x2 0x0 -#define MX6SL_PAD_KEY_ROW0__EIM_AD01 0x18c 0x494 0x000 0x3 0x0 -#define MX6SL_PAD_KEY_ROW0__SD1_WP 0x18c 0x494 0x82c 0x4 0x3 -#define MX6SL_PAD_KEY_ROW0__GPIO3_IO25 0x18c 0x494 0x000 0x5 0x0 -#define MX6SL_PAD_KEY_ROW1__KEY_ROW1 0x190 0x498 0x758 0x0 0x0 -#define MX6SL_PAD_KEY_ROW1__ECSPI4_MISO 0x190 0x498 0x6d4 0x1 0x2 -#define MX6SL_PAD_KEY_ROW1__LCD_DATA03 0x190 0x498 0x784 0x2 0x0 -#define MX6SL_PAD_KEY_ROW1__EIM_AD03 0x190 0x498 0x000 0x3 0x0 -#define MX6SL_PAD_KEY_ROW1__SD3_DATA5 0x190 0x498 0x840 0x4 0x0 -#define MX6SL_PAD_KEY_ROW1__GPIO3_IO27 0x190 0x498 0x000 0x5 0x0 -#define MX6SL_PAD_KEY_ROW2__KEY_ROW2 0x194 0x49c 0x75c 0x0 0x0 -#define MX6SL_PAD_KEY_ROW2__ECSPI4_SCLK 0x194 0x49c 0x6d0 0x1 0x2 -#define MX6SL_PAD_KEY_ROW2__LCD_DATA05 0x194 0x49c 0x78c 0x2 0x0 -#define MX6SL_PAD_KEY_ROW2__EIM_AD05 0x194 0x49c 0x000 0x3 0x0 -#define MX6SL_PAD_KEY_ROW2__SD3_DATA7 0x194 0x49c 0x848 0x4 0x0 -#define MX6SL_PAD_KEY_ROW2__GPIO3_IO29 0x194 0x49c 0x000 0x5 0x0 -#define MX6SL_PAD_KEY_ROW3__KEY_ROW3 0x198 0x4a0 0x760 0x0 0x0 -#define MX6SL_PAD_KEY_ROW3__AUD6_RXC 0x198 0x4a0 0x61c 0x1 0x1 -#define MX6SL_PAD_KEY_ROW3__LCD_DATA07 0x198 0x4a0 0x794 0x2 0x0 -#define MX6SL_PAD_KEY_ROW3__EIM_AD07 0x198 0x4a0 0x000 0x3 0x0 -#define MX6SL_PAD_KEY_ROW3__SD4_DATA7 0x198 0x4a0 0x878 0x4 0x1 -#define MX6SL_PAD_KEY_ROW3__GPIO3_IO31 0x198 0x4a0 0x000 0x5 0x0 -#define MX6SL_PAD_KEY_ROW3__SD1_VSELECT 0x198 0x4a0 0x000 0x6 0x0 -#define MX6SL_PAD_KEY_ROW4__KEY_ROW4 0x19c 0x4a4 0x764 0x0 0x0 -#define MX6SL_PAD_KEY_ROW4__AUD6_TXC 0x19c 0x4a4 0x624 0x1 0x1 -#define MX6SL_PAD_KEY_ROW4__LCD_DATA09 0x19c 0x4a4 0x79c 0x2 0x0 -#define MX6SL_PAD_KEY_ROW4__EIM_AD09 0x19c 0x4a4 0x000 0x3 0x0 -#define MX6SL_PAD_KEY_ROW4__SD4_CMD 0x19c 0x4a4 0x858 0x4 0x2 -#define MX6SL_PAD_KEY_ROW4__GPIO4_IO01 0x19c 0x4a4 0x000 0x5 0x0 -#define MX6SL_PAD_KEY_ROW4__USB_OTG1_OC 0x19c 0x4a4 0x824 0x6 0x1 -#define MX6SL_PAD_KEY_ROW5__KEY_ROW5 0x1a0 0x4a8 0x768 0x0 0x0 -#define MX6SL_PAD_KEY_ROW5__AUD6_TXD 0x1a0 0x4a8 0x618 0x1 0x1 -#define MX6SL_PAD_KEY_ROW5__LCD_DATA11 0x1a0 0x4a8 0x7a4 0x2 0x0 -#define MX6SL_PAD_KEY_ROW5__EIM_AD11 0x1a0 0x4a8 0x000 0x3 0x0 -#define MX6SL_PAD_KEY_ROW5__SD4_DATA1 0x1a0 0x4a8 0x860 0x4 0x2 -#define MX6SL_PAD_KEY_ROW5__GPIO4_IO03 0x1a0 0x4a8 0x000 0x5 0x0 -#define MX6SL_PAD_KEY_ROW5__USB_OTG2_OC 0x1a0 0x4a8 0x820 0x6 0x2 -#define MX6SL_PAD_KEY_ROW6__KEY_ROW6 0x1a4 0x4ac 0x76c 0x0 0x0 -#define MX6SL_PAD_KEY_ROW6__UART4_TX_DATA 0x1a4 0x4ac 0x000 0x1 0x0 -#define MX6SL_PAD_KEY_ROW6__UART4_RX_DATA 0x1a4 0x4ac 0x814 0x1 0x3 -#define MX6SL_PAD_KEY_ROW6__LCD_DATA13 0x1a4 0x4ac 0x7ac 0x2 0x0 -#define MX6SL_PAD_KEY_ROW6__EIM_AD13 0x1a4 0x4ac 0x000 0x3 0x0 -#define MX6SL_PAD_KEY_ROW6__SD4_DATA3 0x1a4 0x4ac 0x868 0x4 0x2 -#define MX6SL_PAD_KEY_ROW6__GPIO4_IO05 0x1a4 0x4ac 0x000 0x5 0x0 -#define MX6SL_PAD_KEY_ROW6__SD3_VSELECT 0x1a4 0x4ac 0x000 0x6 0x0 -#define MX6SL_PAD_KEY_ROW7__KEY_ROW7 0x1a8 0x4b0 0x770 0x0 0x0 -#define MX6SL_PAD_KEY_ROW7__UART4_CTS_B 0x1a8 0x4b0 0x000 0x1 0x0 -#define MX6SL_PAD_KEY_ROW7__UART4_RTS_B 0x1a8 0x4b0 0x810 0x1 0x3 -#define MX6SL_PAD_KEY_ROW7__LCD_DATA15 0x1a8 0x4b0 0x7b4 0x2 0x0 -#define MX6SL_PAD_KEY_ROW7__EIM_AD15 0x1a8 0x4b0 0x000 0x3 0x0 -#define MX6SL_PAD_KEY_ROW7__SD4_DATA5 0x1a8 0x4b0 0x870 0x4 0x1 -#define MX6SL_PAD_KEY_ROW7__GPIO4_IO07 0x1a8 0x4b0 0x000 0x5 0x0 -#define MX6SL_PAD_KEY_ROW7__SD1_CD_B 0x1a8 0x4b0 0x828 0x6 0x3 -#define MX6SL_PAD_LCD_CLK__LCD_CLK 0x1ac 0x4b4 0x000 0x0 0x0 -#define MX6SL_PAD_LCD_CLK__SD4_DATA4 0x1ac 0x4b4 0x86c 0x1 0x2 -#define MX6SL_PAD_LCD_CLK__LCD_WR_RWN 0x1ac 0x4b4 0x000 0x2 0x0 -#define MX6SL_PAD_LCD_CLK__EIM_RW 0x1ac 0x4b4 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_CLK__PWM4_OUT 0x1ac 0x4b4 0x000 0x4 0x0 -#define MX6SL_PAD_LCD_CLK__GPIO2_IO15 0x1ac 0x4b4 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT0__LCD_DATA00 0x1b0 0x4b8 0x778 0x0 0x1 -#define MX6SL_PAD_LCD_DAT0__ECSPI1_MOSI 0x1b0 0x4b8 0x688 0x1 0x1 -#define MX6SL_PAD_LCD_DAT0__USB_OTG2_ID 0x1b0 0x4b8 0x5e0 0x2 0x1 -#define MX6SL_PAD_LCD_DAT0__PWM1_OUT 0x1b0 0x4b8 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_DAT0__UART5_DTR_B 0x1b0 0x4b8 0x000 0x4 0x0 -#define MX6SL_PAD_LCD_DAT0__GPIO2_IO20 0x1b0 0x4b8 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT0__ARM_TRACE00 0x1b0 0x4b8 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_DAT0__SRC_BOOT_CFG00 0x1b0 0x4b8 0x000 0x7 0x0 -#define MX6SL_PAD_LCD_DAT1__LCD_DATA01 0x1b4 0x4bc 0x77c 0x0 0x1 -#define MX6SL_PAD_LCD_DAT1__ECSPI1_MISO 0x1b4 0x4bc 0x684 0x1 0x1 -#define MX6SL_PAD_LCD_DAT1__USB_OTG1_ID 0x1b4 0x4bc 0x5dc 0x2 0x2 -#define MX6SL_PAD_LCD_DAT1__PWM2_OUT 0x1b4 0x4bc 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_DAT1__AUD4_RXFS 0x1b4 0x4bc 0x5f0 0x4 0x1 -#define MX6SL_PAD_LCD_DAT1__GPIO2_IO21 0x1b4 0x4bc 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT1__ARM_TRACE01 0x1b4 0x4bc 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_DAT1__SRC_BOOT_CFG01 0x1b4 0x4bc 0x000 0x7 0x0 -#define MX6SL_PAD_LCD_DAT10__LCD_DATA10 0x1b8 0x4c0 0x7a0 0x0 0x1 -#define MX6SL_PAD_LCD_DAT10__KEY_COL1 0x1b8 0x4c0 0x738 0x1 0x1 -#define MX6SL_PAD_LCD_DAT10__CSI_DATA07 0x1b8 0x4c0 0x64c 0x2 0x1 -#define MX6SL_PAD_LCD_DAT10__EIM_DATA04 0x1b8 0x4c0 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_DAT10__ECSPI2_MISO 0x1b8 0x4c0 0x6a0 0x4 0x2 -#define MX6SL_PAD_LCD_DAT10__GPIO2_IO30 0x1b8 0x4c0 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT10__ARM_TRACE10 0x1b8 0x4c0 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_DAT10__SRC_BOOT_CFG10 0x1b8 0x4c0 0x000 0x7 0x0 -#define MX6SL_PAD_LCD_DAT11__LCD_DATA11 0x1bc 0x4c4 0x7a4 0x0 0x1 -#define MX6SL_PAD_LCD_DAT11__KEY_ROW1 0x1bc 0x4c4 0x758 0x1 0x1 -#define MX6SL_PAD_LCD_DAT11__CSI_DATA06 0x1bc 0x4c4 0x648 0x2 0x1 -#define MX6SL_PAD_LCD_DAT11__EIM_DATA05 0x1bc 0x4c4 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_DAT11__ECSPI2_SS1 0x1bc 0x4c4 0x6ac 0x4 0x1 -#define MX6SL_PAD_LCD_DAT11__GPIO2_IO31 0x1bc 0x4c4 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT11__ARM_TRACE11 0x1bc 0x4c4 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_DAT11__SRC_BOOT_CFG11 0x1bc 0x4c4 0x000 0x7 0x0 -#define MX6SL_PAD_LCD_DAT12__LCD_DATA12 0x1c0 0x4c8 0x7a8 0x0 0x1 -#define MX6SL_PAD_LCD_DAT12__KEY_COL2 0x1c0 0x4c8 0x73c 0x1 0x1 -#define MX6SL_PAD_LCD_DAT12__CSI_DATA05 0x1c0 0x4c8 0x644 0x2 0x1 -#define MX6SL_PAD_LCD_DAT12__EIM_DATA06 0x1c0 0x4c8 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_DAT12__UART5_RTS_B 0x1c0 0x4c8 0x818 0x4 0x2 -#define MX6SL_PAD_LCD_DAT12__UART5_CTS_B 0x1c0 0x4c8 0x000 0x4 0x0 -#define MX6SL_PAD_LCD_DAT12__GPIO3_IO00 0x1c0 0x4c8 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT12__ARM_TRACE12 0x1c0 0x4c8 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_DAT12__SRC_BOOT_CFG12 0x1c0 0x4c8 0x000 0x7 0x0 -#define MX6SL_PAD_LCD_DAT13__LCD_DATA13 0x1c4 0x4cc 0x7ac 0x0 0x1 -#define MX6SL_PAD_LCD_DAT13__KEY_ROW2 0x1c4 0x4cc 0x75c 0x1 0x1 -#define MX6SL_PAD_LCD_DAT13__CSI_DATA04 0x1c4 0x4cc 0x640 0x2 0x1 -#define MX6SL_PAD_LCD_DAT13__EIM_DATA07 0x1c4 0x4cc 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_DAT13__UART5_CTS_B 0x1c4 0x4cc 0x000 0x4 0x0 -#define MX6SL_PAD_LCD_DAT13__UART5_RTS_B 0x1c4 0x4cc 0x818 0x4 0x3 -#define MX6SL_PAD_LCD_DAT13__GPIO3_IO01 0x1c4 0x4cc 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT13__ARM_TRACE13 0x1c4 0x4cc 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_DAT13__SRC_BOOT_CFG13 0x1c4 0x4cc 0x000 0x7 0x0 -#define MX6SL_PAD_LCD_DAT14__LCD_DATA14 0x1c8 0x4d0 0x7b0 0x0 0x1 -#define MX6SL_PAD_LCD_DAT14__KEY_COL3 0x1c8 0x4d0 0x740 0x1 0x1 -#define MX6SL_PAD_LCD_DAT14__CSI_DATA03 0x1c8 0x4d0 0x63c 0x2 0x1 -#define MX6SL_PAD_LCD_DAT14__EIM_DATA08 0x1c8 0x4d0 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_DAT14__UART5_RX_DATA 0x1c8 0x4d0 0x81c 0x4 0x2 -#define MX6SL_PAD_LCD_DAT14__UART5_TX_DATA 0x1c8 0x4d0 0x000 0x4 0x0 -#define MX6SL_PAD_LCD_DAT14__GPIO3_IO02 0x1c8 0x4d0 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT14__ARM_TRACE14 0x1c8 0x4d0 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_DAT14__SRC_BOOT_CFG14 0x1c8 0x4d0 0x000 0x7 0x0 -#define MX6SL_PAD_LCD_DAT15__LCD_DATA15 0x1cc 0x4d4 0x7b4 0x0 0x1 -#define MX6SL_PAD_LCD_DAT15__KEY_ROW3 0x1cc 0x4d4 0x760 0x1 0x1 -#define MX6SL_PAD_LCD_DAT15__CSI_DATA02 0x1cc 0x4d4 0x638 0x2 0x1 -#define MX6SL_PAD_LCD_DAT15__EIM_DATA09 0x1cc 0x4d4 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_DAT15__UART5_TX_DATA 0x1cc 0x4d4 0x000 0x4 0x0 -#define MX6SL_PAD_LCD_DAT15__UART5_RX_DATA 0x1cc 0x4d4 0x81c 0x4 0x3 -#define MX6SL_PAD_LCD_DAT15__GPIO3_IO03 0x1cc 0x4d4 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT15__ARM_TRACE15 0x1cc 0x4d4 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_DAT15__SRC_BOOT_CFG15 0x1cc 0x4d4 0x000 0x7 0x0 -#define MX6SL_PAD_LCD_DAT16__LCD_DATA16 0x1d0 0x4d8 0x7b8 0x0 0x1 -#define MX6SL_PAD_LCD_DAT16__KEY_COL4 0x1d0 0x4d8 0x744 0x1 0x1 -#define MX6SL_PAD_LCD_DAT16__CSI_DATA01 0x1d0 0x4d8 0x634 0x2 0x1 -#define MX6SL_PAD_LCD_DAT16__EIM_DATA10 0x1d0 0x4d8 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_DAT16__I2C2_SCL 0x1d0 0x4d8 0x724 0x4 0x3 -#define MX6SL_PAD_LCD_DAT16__GPIO3_IO04 0x1d0 0x4d8 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT16__ARM_TRACE16 0x1d0 0x4d8 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_DAT16__SRC_BOOT_CFG24 0x1d0 0x4d8 0x000 0x7 0x0 -#define MX6SL_PAD_LCD_DAT17__LCD_DATA17 0x1d4 0x4dc 0x7bc 0x0 0x1 -#define MX6SL_PAD_LCD_DAT17__KEY_ROW4 0x1d4 0x4dc 0x764 0x1 0x1 -#define MX6SL_PAD_LCD_DAT17__CSI_DATA00 0x1d4 0x4dc 0x630 0x2 0x1 -#define MX6SL_PAD_LCD_DAT17__EIM_DATA11 0x1d4 0x4dc 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_DAT17__I2C2_SDA 0x1d4 0x4dc 0x728 0x4 0x3 -#define MX6SL_PAD_LCD_DAT17__GPIO3_IO05 0x1d4 0x4dc 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT17__ARM_TRACE17 0x1d4 0x4dc 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_DAT17__SRC_BOOT_CFG25 0x1d4 0x4dc 0x000 0x7 0x0 -#define MX6SL_PAD_LCD_DAT18__LCD_DATA18 0x1d8 0x4e0 0x7c0 0x0 0x1 -#define MX6SL_PAD_LCD_DAT18__KEY_COL5 0x1d8 0x4e0 0x748 0x1 0x1 -#define MX6SL_PAD_LCD_DAT18__CSI_DATA15 0x1d8 0x4e0 0x66c 0x2 0x0 -#define MX6SL_PAD_LCD_DAT18__EIM_DATA12 0x1d8 0x4e0 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_DAT18__GPT_CAPTURE1 0x1d8 0x4e0 0x710 0x4 0x1 -#define MX6SL_PAD_LCD_DAT18__GPIO3_IO06 0x1d8 0x4e0 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT18__ARM_TRACE18 0x1d8 0x4e0 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_DAT18__SRC_BOOT_CFG26 0x1d8 0x4e0 0x000 0x7 0x0 -#define MX6SL_PAD_LCD_DAT19__LCD_DATA19 0x1dc 0x4e4 0x7c4 0x0 0x1 -#define MX6SL_PAD_LCD_DAT19__KEY_ROW5 0x1dc 0x4e4 0x768 0x1 0x1 -#define MX6SL_PAD_LCD_DAT19__CSI_DATA14 0x1dc 0x4e4 0x668 0x2 0x0 -#define MX6SL_PAD_LCD_DAT19__EIM_DATA13 0x1dc 0x4e4 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_DAT19__GPT_CAPTURE2 0x1dc 0x4e4 0x714 0x4 0x1 -#define MX6SL_PAD_LCD_DAT19__GPIO3_IO07 0x1dc 0x4e4 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT19__ARM_TRACE19 0x1dc 0x4e4 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_DAT19__SRC_BOOT_CFG27 0x1dc 0x4e4 0x000 0x7 0x0 -#define MX6SL_PAD_LCD_DAT2__LCD_DATA02 0x1e0 0x4e8 0x780 0x0 0x1 -#define MX6SL_PAD_LCD_DAT2__ECSPI1_SS0 0x1e0 0x4e8 0x68c 0x1 0x1 -#define MX6SL_PAD_LCD_DAT2__EPIT2_OUT 0x1e0 0x4e8 0x000 0x2 0x0 -#define MX6SL_PAD_LCD_DAT2__PWM3_OUT 0x1e0 0x4e8 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_DAT2__AUD4_RXC 0x1e0 0x4e8 0x5ec 0x4 0x1 -#define MX6SL_PAD_LCD_DAT2__GPIO2_IO22 0x1e0 0x4e8 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT2__ARM_TRACE02 0x1e0 0x4e8 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_DAT2__SRC_BOOT_CFG02 0x1e0 0x4e8 0x000 0x7 0x0 -#define MX6SL_PAD_LCD_DAT20__LCD_DATA20 0x1e4 0x4ec 0x7c8 0x0 0x1 -#define MX6SL_PAD_LCD_DAT20__KEY_COL6 0x1e4 0x4ec 0x74c 0x1 0x1 -#define MX6SL_PAD_LCD_DAT20__CSI_DATA13 0x1e4 0x4ec 0x664 0x2 0x0 -#define MX6SL_PAD_LCD_DAT20__EIM_DATA14 0x1e4 0x4ec 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_DAT20__GPT_COMPARE1 0x1e4 0x4ec 0x000 0x4 0x0 -#define MX6SL_PAD_LCD_DAT20__GPIO3_IO08 0x1e4 0x4ec 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT20__ARM_TRACE20 0x1e4 0x4ec 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_DAT20__SRC_BOOT_CFG28 0x1e4 0x4ec 0x000 0x7 0x0 -#define MX6SL_PAD_LCD_DAT21__LCD_DATA21 0x1e8 0x4f0 0x7cc 0x0 0x1 -#define MX6SL_PAD_LCD_DAT21__KEY_ROW6 0x1e8 0x4f0 0x76c 0x1 0x1 -#define MX6SL_PAD_LCD_DAT21__CSI_DATA12 0x1e8 0x4f0 0x660 0x2 0x0 -#define MX6SL_PAD_LCD_DAT21__EIM_DATA15 0x1e8 0x4f0 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_DAT21__GPT_COMPARE2 0x1e8 0x4f0 0x000 0x4 0x0 -#define MX6SL_PAD_LCD_DAT21__GPIO3_IO09 0x1e8 0x4f0 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT21__ARM_TRACE21 0x1e8 0x4f0 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_DAT21__SRC_BOOT_CFG29 0x1e8 0x4f0 0x000 0x7 0x0 -#define MX6SL_PAD_LCD_DAT22__LCD_DATA22 0x1ec 0x4f4 0x7d0 0x0 0x1 -#define MX6SL_PAD_LCD_DAT22__KEY_COL7 0x1ec 0x4f4 0x750 0x1 0x1 -#define MX6SL_PAD_LCD_DAT22__CSI_DATA11 0x1ec 0x4f4 0x65c 0x2 0x1 -#define MX6SL_PAD_LCD_DAT22__EIM_EB3_B 0x1ec 0x4f4 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_DAT22__GPT_COMPARE3 0x1ec 0x4f4 0x000 0x4 0x0 -#define MX6SL_PAD_LCD_DAT22__GPIO3_IO10 0x1ec 0x4f4 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT22__ARM_TRACE22 0x1ec 0x4f4 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_DAT22__SRC_BOOT_CFG30 0x1ec 0x4f4 0x000 0x7 0x0 -#define MX6SL_PAD_LCD_DAT23__LCD_DATA23 0x1f0 0x4f8 0x7d4 0x0 0x1 -#define MX6SL_PAD_LCD_DAT23__KEY_ROW7 0x1f0 0x4f8 0x770 0x1 0x1 -#define MX6SL_PAD_LCD_DAT23__CSI_DATA10 0x1f0 0x4f8 0x658 0x2 0x1 -#define MX6SL_PAD_LCD_DAT23__EIM_EB2_B 0x1f0 0x4f8 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_DAT23__GPT_CLKIN 0x1f0 0x4f8 0x718 0x4 0x1 -#define MX6SL_PAD_LCD_DAT23__GPIO3_IO11 0x1f0 0x4f8 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT23__ARM_TRACE23 0x1f0 0x4f8 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_DAT23__SRC_BOOT_CFG31 0x1f0 0x4f8 0x000 0x7 0x0 -#define MX6SL_PAD_LCD_DAT3__LCD_DATA03 0x1f4 0x4fc 0x784 0x0 0x1 -#define MX6SL_PAD_LCD_DAT3__ECSPI1_SCLK 0x1f4 0x4fc 0x67c 0x1 0x1 -#define MX6SL_PAD_LCD_DAT3__UART5_DSR_B 0x1f4 0x4fc 0x000 0x2 0x0 -#define MX6SL_PAD_LCD_DAT3__PWM4_OUT 0x1f4 0x4fc 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_DAT3__AUD4_RXD 0x1f4 0x4fc 0x5e4 0x4 0x1 -#define MX6SL_PAD_LCD_DAT3__GPIO2_IO23 0x1f4 0x4fc 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT3__ARM_TRACE03 0x1f4 0x4fc 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_DAT3__SRC_BOOT_CFG03 0x1f4 0x4fc 0x000 0x7 0x0 -#define MX6SL_PAD_LCD_DAT4__LCD_DATA04 0x1f8 0x500 0x788 0x0 0x1 -#define MX6SL_PAD_LCD_DAT4__ECSPI1_SS1 0x1f8 0x500 0x690 0x1 0x1 -#define MX6SL_PAD_LCD_DAT4__CSI_VSYNC 0x1f8 0x500 0x678 0x2 0x2 -#define MX6SL_PAD_LCD_DAT4__WDOG2_RESET_B_DEB 0x1f8 0x500 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_DAT4__AUD4_TXC 0x1f8 0x500 0x5f4 0x4 0x1 -#define MX6SL_PAD_LCD_DAT4__GPIO2_IO24 0x1f8 0x500 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT4__ARM_TRACE04 0x1f8 0x500 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_DAT4__SRC_BOOT_CFG04 0x1f8 0x500 0x000 0x7 0x0 -#define MX6SL_PAD_LCD_DAT5__LCD_DATA05 0x1fc 0x504 0x78c 0x0 0x1 -#define MX6SL_PAD_LCD_DAT5__ECSPI1_SS2 0x1fc 0x504 0x694 0x1 0x1 -#define MX6SL_PAD_LCD_DAT5__CSI_HSYNC 0x1fc 0x504 0x670 0x2 0x2 -#define MX6SL_PAD_LCD_DAT5__EIM_CS3_B 0x1fc 0x504 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_DAT5__AUD4_TXFS 0x1fc 0x504 0x5f8 0x4 0x1 -#define MX6SL_PAD_LCD_DAT5__GPIO2_IO25 0x1fc 0x504 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT5__ARM_TRACE05 0x1fc 0x504 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_DAT5__SRC_BOOT_CFG05 0x1fc 0x504 0x000 0x7 0x0 -#define MX6SL_PAD_LCD_DAT6__LCD_DATA06 0x200 0x508 0x790 0x0 0x1 -#define MX6SL_PAD_LCD_DAT6__ECSPI1_SS3 0x200 0x508 0x698 0x1 0x1 -#define MX6SL_PAD_LCD_DAT6__CSI_PIXCLK 0x200 0x508 0x674 0x2 0x2 -#define MX6SL_PAD_LCD_DAT6__EIM_DATA00 0x200 0x508 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_DAT6__AUD4_TXD 0x200 0x508 0x5e8 0x4 0x1 -#define MX6SL_PAD_LCD_DAT6__GPIO2_IO26 0x200 0x508 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT6__ARM_TRACE06 0x200 0x508 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_DAT6__SRC_BOOT_CFG06 0x200 0x508 0x000 0x7 0x0 -#define MX6SL_PAD_LCD_DAT7__LCD_DATA07 0x204 0x50c 0x794 0x0 0x1 -#define MX6SL_PAD_LCD_DAT7__ECSPI1_RDY 0x204 0x50c 0x680 0x1 0x1 -#define MX6SL_PAD_LCD_DAT7__CSI_MCLK 0x204 0x50c 0x000 0x2 0x0 -#define MX6SL_PAD_LCD_DAT7__EIM_DATA01 0x204 0x50c 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_DAT7__AUDIO_CLK_OUT 0x204 0x50c 0x000 0x4 0x0 -#define MX6SL_PAD_LCD_DAT7__GPIO2_IO27 0x204 0x50c 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT7__ARM_TRACE07 0x204 0x50c 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_DAT7__SRC_BOOT_CFG07 0x204 0x50c 0x000 0x7 0x0 -#define MX6SL_PAD_LCD_DAT8__LCD_DATA08 0x208 0x510 0x798 0x0 0x1 -#define MX6SL_PAD_LCD_DAT8__KEY_COL0 0x208 0x510 0x734 0x1 0x1 -#define MX6SL_PAD_LCD_DAT8__CSI_DATA09 0x208 0x510 0x654 0x2 0x1 -#define MX6SL_PAD_LCD_DAT8__EIM_DATA02 0x208 0x510 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_DAT8__ECSPI2_SCLK 0x208 0x510 0x69c 0x4 0x2 -#define MX6SL_PAD_LCD_DAT8__GPIO2_IO28 0x208 0x510 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT8__ARM_TRACE08 0x208 0x510 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_DAT8__SRC_BOOT_CFG08 0x208 0x510 0x000 0x7 0x0 -#define MX6SL_PAD_LCD_DAT9__LCD_DATA09 0x20c 0x514 0x79c 0x0 0x1 -#define MX6SL_PAD_LCD_DAT9__KEY_ROW0 0x20c 0x514 0x754 0x1 0x1 -#define MX6SL_PAD_LCD_DAT9__CSI_DATA08 0x20c 0x514 0x650 0x2 0x1 -#define MX6SL_PAD_LCD_DAT9__EIM_DATA03 0x20c 0x514 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_DAT9__ECSPI2_MOSI 0x20c 0x514 0x6a4 0x4 0x2 -#define MX6SL_PAD_LCD_DAT9__GPIO2_IO29 0x20c 0x514 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT9__ARM_TRACE09 0x20c 0x514 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_DAT9__SRC_BOOT_CFG09 0x20c 0x514 0x000 0x7 0x0 -#define MX6SL_PAD_LCD_ENABLE__LCD_ENABLE 0x210 0x518 0x000 0x0 0x0 -#define MX6SL_PAD_LCD_ENABLE__SD4_DATA5 0x210 0x518 0x870 0x1 0x2 -#define MX6SL_PAD_LCD_ENABLE__LCD_RD_E 0x210 0x518 0x000 0x2 0x0 -#define MX6SL_PAD_LCD_ENABLE__EIM_OE_B 0x210 0x518 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_ENABLE__UART2_RX_DATA 0x210 0x518 0x804 0x4 0x2 -#define MX6SL_PAD_LCD_ENABLE__UART2_TX_DATA 0x210 0x518 0x000 0x4 0x0 -#define MX6SL_PAD_LCD_ENABLE__GPIO2_IO16 0x210 0x518 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_HSYNC__LCD_HSYNC 0x214 0x51c 0x774 0x0 0x0 -#define MX6SL_PAD_LCD_HSYNC__SD4_DATA6 0x214 0x51c 0x874 0x1 0x2 -#define MX6SL_PAD_LCD_HSYNC__LCD_CS 0x214 0x51c 0x000 0x2 0x0 -#define MX6SL_PAD_LCD_HSYNC__EIM_CS0_B 0x214 0x51c 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_HSYNC__UART2_TX_DATA 0x214 0x51c 0x000 0x4 0x0 -#define MX6SL_PAD_LCD_HSYNC__UART2_RX_DATA 0x214 0x51c 0x804 0x4 0x3 -#define MX6SL_PAD_LCD_HSYNC__GPIO2_IO17 0x214 0x51c 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_HSYNC__ARM_TRACE_CLK 0x214 0x51c 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_RESET__LCD_RESET 0x218 0x520 0x000 0x0 0x0 -#define MX6SL_PAD_LCD_RESET__EIM_DTACK_B 0x218 0x520 0x880 0x1 0x1 -#define MX6SL_PAD_LCD_RESET__LCD_BUSY 0x218 0x520 0x774 0x2 0x1 -#define MX6SL_PAD_LCD_RESET__EIM_WAIT_B 0x218 0x520 0x884 0x3 0x1 -#define MX6SL_PAD_LCD_RESET__UART2_CTS_B 0x218 0x520 0x000 0x4 0x0 -#define MX6SL_PAD_LCD_RESET__UART2_RTS_B 0x218 0x520 0x800 0x4 0x2 -#define MX6SL_PAD_LCD_RESET__GPIO2_IO19 0x218 0x520 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_RESET__CCM_PMIC_READY 0x218 0x520 0x62c 0x6 0x1 -#define MX6SL_PAD_LCD_VSYNC__LCD_VSYNC 0x21c 0x524 0x000 0x0 0x0 -#define MX6SL_PAD_LCD_VSYNC__SD4_DATA7 0x21c 0x524 0x878 0x1 0x2 -#define MX6SL_PAD_LCD_VSYNC__LCD_RS 0x21c 0x524 0x000 0x2 0x0 -#define MX6SL_PAD_LCD_VSYNC__EIM_CS1_B 0x21c 0x524 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_VSYNC__UART2_RTS_B 0x21c 0x524 0x800 0x4 0x3 -#define MX6SL_PAD_LCD_VSYNC__UART2_CTS_B 0x21c 0x524 0x000 0x4 0x0 -#define MX6SL_PAD_LCD_VSYNC__GPIO2_IO18 0x21c 0x524 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_VSYNC__ARM_TRACE_CTL 0x21c 0x524 0x000 0x6 0x0 -#define MX6SL_PAD_PWM1__PWM1_OUT 0x220 0x528 0x000 0x0 0x0 -#define MX6SL_PAD_PWM1__CCM_CLKO 0x220 0x528 0x000 0x1 0x0 -#define MX6SL_PAD_PWM1__AUDIO_CLK_OUT 0x220 0x528 0x000 0x2 0x0 -#define MX6SL_PAD_PWM1__FEC_REF_OUT 0x220 0x528 0x000 0x3 0x0 -#define MX6SL_PAD_PWM1__CSI_MCLK 0x220 0x528 0x000 0x4 0x0 -#define MX6SL_PAD_PWM1__GPIO3_IO23 0x220 0x528 0x000 0x5 0x0 -#define MX6SL_PAD_PWM1__EPIT1_OUT 0x220 0x528 0x000 0x6 0x0 -#define MX6SL_PAD_REF_CLK_24M__XTALOSC_REF_CLK_24M 0x224 0x52c 0x000 0x0 0x0 -#define MX6SL_PAD_REF_CLK_24M__I2C3_SCL 0x224 0x52c 0x72c 0x1 0x2 -#define MX6SL_PAD_REF_CLK_24M__PWM3_OUT 0x224 0x52c 0x000 0x2 0x0 -#define MX6SL_PAD_REF_CLK_24M__USB_OTG2_ID 0x224 0x52c 0x5e0 0x3 0x2 -#define MX6SL_PAD_REF_CLK_24M__CCM_PMIC_READY 0x224 0x52c 0x62c 0x4 0x2 -#define MX6SL_PAD_REF_CLK_24M__GPIO3_IO21 0x224 0x52c 0x000 0x5 0x0 -#define MX6SL_PAD_REF_CLK_24M__SD3_WP 0x224 0x52c 0x84c 0x6 0x3 -#define MX6SL_PAD_REF_CLK_32K__XTALOSC_REF_CLK_32K 0x228 0x530 0x000 0x0 0x0 -#define MX6SL_PAD_REF_CLK_32K__I2C3_SDA 0x228 0x530 0x730 0x1 0x2 -#define MX6SL_PAD_REF_CLK_32K__PWM4_OUT 0x228 0x530 0x000 0x2 0x0 -#define MX6SL_PAD_REF_CLK_32K__USB_OTG1_ID 0x228 0x530 0x5dc 0x3 0x3 -#define MX6SL_PAD_REF_CLK_32K__SD1_LCTL 0x228 0x530 0x000 0x4 0x0 -#define MX6SL_PAD_REF_CLK_32K__GPIO3_IO22 0x228 0x530 0x000 0x5 0x0 -#define MX6SL_PAD_REF_CLK_32K__SD3_CD_B 0x228 0x530 0x838 0x6 0x3 -#define MX6SL_PAD_SD1_CLK__SD1_CLK 0x22c 0x534 0x000 0x0 0x0 -#define MX6SL_PAD_SD1_CLK__FEC_MDIO 0x22c 0x534 0x6f4 0x1 0x2 -#define MX6SL_PAD_SD1_CLK__KEY_COL0 0x22c 0x534 0x734 0x2 0x2 -#define MX6SL_PAD_SD1_CLK__EPDC_SDCE4 0x22c 0x534 0x000 0x3 0x0 -#define MX6SL_PAD_SD1_CLK__GPIO5_IO15 0x22c 0x534 0x000 0x5 0x0 -#define MX6SL_PAD_SD1_CMD__SD1_CMD 0x230 0x538 0x000 0x0 0x0 -#define MX6SL_PAD_SD1_CMD__FEC_TX_CLK 0x230 0x538 0x70c 0x1 0x2 -#define MX6SL_PAD_SD1_CMD__KEY_ROW0 0x230 0x538 0x754 0x2 0x2 -#define MX6SL_PAD_SD1_CMD__EPDC_SDCE5 0x230 0x538 0x000 0x3 0x0 -#define MX6SL_PAD_SD1_CMD__GPIO5_IO14 0x230 0x538 0x000 0x5 0x0 -#define MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x234 0x53c 0x000 0x0 0x0 -#define MX6SL_PAD_SD1_DAT0__FEC_RX_ER 0x234 0x53c 0x708 0x1 0x2 -#define MX6SL_PAD_SD1_DAT0__KEY_COL1 0x234 0x53c 0x738 0x2 0x2 -#define MX6SL_PAD_SD1_DAT0__EPDC_SDCE6 0x234 0x53c 0x000 0x3 0x0 -#define MX6SL_PAD_SD1_DAT0__GPIO5_IO11 0x234 0x53c 0x000 0x5 0x0 -#define MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x238 0x540 0x000 0x0 0x0 -#define MX6SL_PAD_SD1_DAT1__FEC_RX_DV 0x238 0x540 0x704 0x1 0x2 -#define MX6SL_PAD_SD1_DAT1__KEY_ROW1 0x238 0x540 0x758 0x2 0x2 -#define MX6SL_PAD_SD1_DAT1__EPDC_SDCE7 0x238 0x540 0x000 0x3 0x0 -#define MX6SL_PAD_SD1_DAT1__GPIO5_IO08 0x238 0x540 0x000 0x5 0x0 -#define MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x23c 0x544 0x000 0x0 0x0 -#define MX6SL_PAD_SD1_DAT2__FEC_RX_DATA1 0x23c 0x544 0x6fc 0x1 0x2 -#define MX6SL_PAD_SD1_DAT2__KEY_COL2 0x23c 0x544 0x73c 0x2 0x2 -#define MX6SL_PAD_SD1_DAT2__EPDC_SDCE8 0x23c 0x544 0x000 0x3 0x0 -#define MX6SL_PAD_SD1_DAT2__GPIO5_IO13 0x23c 0x544 0x000 0x5 0x0 -#define MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x240 0x548 0x000 0x0 0x0 -#define MX6SL_PAD_SD1_DAT3__FEC_TX_DATA0 0x240 0x548 0x000 0x1 0x0 -#define MX6SL_PAD_SD1_DAT3__KEY_ROW2 0x240 0x548 0x75c 0x2 0x2 -#define MX6SL_PAD_SD1_DAT3__EPDC_SDCE9 0x240 0x548 0x000 0x3 0x0 -#define MX6SL_PAD_SD1_DAT3__GPIO5_IO06 0x240 0x548 0x000 0x5 0x0 -#define MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x244 0x54c 0x000 0x0 0x0 -#define MX6SL_PAD_SD1_DAT4__FEC_MDC 0x244 0x54c 0x000 0x1 0x0 -#define MX6SL_PAD_SD1_DAT4__KEY_COL3 0x244 0x54c 0x740 0x2 0x2 -#define MX6SL_PAD_SD1_DAT4__EPDC_SDCLK_N 0x244 0x54c 0x000 0x3 0x0 -#define MX6SL_PAD_SD1_DAT4__UART4_RX_DATA 0x244 0x54c 0x814 0x4 0x4 -#define MX6SL_PAD_SD1_DAT4__UART4_TX_DATA 0x244 0x54c 0x000 0x4 0x0 -#define MX6SL_PAD_SD1_DAT4__GPIO5_IO12 0x244 0x54c 0x000 0x5 0x0 -#define MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x248 0x550 0x000 0x0 0x0 -#define MX6SL_PAD_SD1_DAT5__FEC_RX_DATA0 0x248 0x550 0x6f8 0x1 0x2 -#define MX6SL_PAD_SD1_DAT5__KEY_ROW3 0x248 0x550 0x760 0x2 0x2 -#define MX6SL_PAD_SD1_DAT5__EPDC_SDOED 0x248 0x550 0x000 0x3 0x0 -#define MX6SL_PAD_SD1_DAT5__UART4_TX_DATA 0x248 0x550 0x000 0x4 0x0 -#define MX6SL_PAD_SD1_DAT5__UART4_RX_DATA 0x248 0x550 0x814 0x4 0x5 -#define MX6SL_PAD_SD1_DAT5__GPIO5_IO09 0x248 0x550 0x000 0x5 0x0 -#define MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x24c 0x554 0x000 0x0 0x0 -#define MX6SL_PAD_SD1_DAT6__FEC_TX_EN 0x24c 0x554 0x000 0x1 0x0 -#define MX6SL_PAD_SD1_DAT6__KEY_COL4 0x24c 0x554 0x744 0x2 0x2 -#define MX6SL_PAD_SD1_DAT6__EPDC_SDOEZ 0x24c 0x554 0x000 0x3 0x0 -#define MX6SL_PAD_SD1_DAT6__UART4_RTS_B 0x24c 0x554 0x810 0x4 0x4 -#define MX6SL_PAD_SD1_DAT6__UART4_CTS_B 0x24c 0x554 0x000 0x4 0x0 -#define MX6SL_PAD_SD1_DAT6__GPIO5_IO07 0x24c 0x554 0x000 0x5 0x0 -#define MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x250 0x558 0x000 0x0 0x0 -#define MX6SL_PAD_SD1_DAT7__FEC_TX_DATA1 0x250 0x558 0x000 0x1 0x0 -#define MX6SL_PAD_SD1_DAT7__KEY_ROW4 0x250 0x558 0x764 0x2 0x2 -#define MX6SL_PAD_SD1_DAT7__CCM_PMIC_READY 0x250 0x558 0x62c 0x3 0x3 -#define MX6SL_PAD_SD1_DAT7__UART4_CTS_B 0x250 0x558 0x000 0x4 0x0 -#define MX6SL_PAD_SD1_DAT7__UART4_RTS_B 0x250 0x558 0x810 0x4 0x5 -#define MX6SL_PAD_SD1_DAT7__GPIO5_IO10 0x250 0x558 0x000 0x5 0x0 -#define MX6SL_PAD_SD2_CLK__SD2_CLK 0x254 0x55c 0x000 0x0 0x0 -#define MX6SL_PAD_SD2_CLK__AUD4_RXFS 0x254 0x55c 0x5f0 0x1 0x2 -#define MX6SL_PAD_SD2_CLK__ECSPI3_SCLK 0x254 0x55c 0x6b0 0x2 0x2 -#define MX6SL_PAD_SD2_CLK__CSI_DATA00 0x254 0x55c 0x630 0x3 0x2 -#define MX6SL_PAD_SD2_CLK__GPIO5_IO05 0x254 0x55c 0x000 0x5 0x0 -#define MX6SL_PAD_SD2_CMD__SD2_CMD 0x258 0x560 0x000 0x0 0x0 -#define MX6SL_PAD_SD2_CMD__AUD4_RXC 0x258 0x560 0x5ec 0x1 0x2 -#define MX6SL_PAD_SD2_CMD__ECSPI3_SS0 0x258 0x560 0x6c0 0x2 0x2 -#define MX6SL_PAD_SD2_CMD__CSI_DATA01 0x258 0x560 0x634 0x3 0x2 -#define MX6SL_PAD_SD2_CMD__EPIT1_OUT 0x258 0x560 0x000 0x4 0x0 -#define MX6SL_PAD_SD2_CMD__GPIO5_IO04 0x258 0x560 0x000 0x5 0x0 -#define MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x25c 0x564 0x000 0x0 0x0 -#define MX6SL_PAD_SD2_DAT0__AUD4_RXD 0x25c 0x564 0x5e4 0x1 0x2 -#define MX6SL_PAD_SD2_DAT0__ECSPI3_MOSI 0x25c 0x564 0x6bc 0x2 0x2 -#define MX6SL_PAD_SD2_DAT0__CSI_DATA02 0x25c 0x564 0x638 0x3 0x2 -#define MX6SL_PAD_SD2_DAT0__UART5_RTS_B 0x25c 0x564 0x818 0x4 0x4 -#define MX6SL_PAD_SD2_DAT0__UART5_CTS_B 0x25c 0x564 0x000 0x4 0x0 -#define MX6SL_PAD_SD2_DAT0__GPIO5_IO01 0x25c 0x564 0x000 0x5 0x0 -#define MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x260 0x568 0x000 0x0 0x0 -#define MX6SL_PAD_SD2_DAT1__AUD4_TXC 0x260 0x568 0x5f4 0x1 0x2 -#define MX6SL_PAD_SD2_DAT1__ECSPI3_MISO 0x260 0x568 0x6b8 0x2 0x2 -#define MX6SL_PAD_SD2_DAT1__CSI_DATA03 0x260 0x568 0x63c 0x3 0x2 -#define MX6SL_PAD_SD2_DAT1__UART5_CTS_B 0x260 0x568 0x000 0x4 0x0 -#define MX6SL_PAD_SD2_DAT1__UART5_RTS_B 0x260 0x568 0x818 0x4 0x5 -#define MX6SL_PAD_SD2_DAT1__GPIO4_IO30 0x260 0x568 0x000 0x5 0x0 -#define MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x264 0x56c 0x000 0x0 0x0 -#define MX6SL_PAD_SD2_DAT2__AUD4_TXFS 0x264 0x56c 0x5f8 0x1 0x2 -#define MX6SL_PAD_SD2_DAT2__FEC_COL 0x264 0x56c 0x6f0 0x2 0x1 -#define MX6SL_PAD_SD2_DAT2__CSI_DATA04 0x264 0x56c 0x640 0x3 0x2 -#define MX6SL_PAD_SD2_DAT2__UART5_RX_DATA 0x264 0x56c 0x81c 0x4 0x4 -#define MX6SL_PAD_SD2_DAT2__UART5_TX_DATA 0x264 0x56c 0x000 0x4 0x0 -#define MX6SL_PAD_SD2_DAT2__GPIO5_IO03 0x264 0x56c 0x000 0x5 0x0 -#define MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x268 0x570 0x000 0x0 0x0 -#define MX6SL_PAD_SD2_DAT3__AUD4_TXD 0x268 0x570 0x5e8 0x1 0x2 -#define MX6SL_PAD_SD2_DAT3__FEC_RX_CLK 0x268 0x570 0x700 0x2 0x1 -#define MX6SL_PAD_SD2_DAT3__CSI_DATA05 0x268 0x570 0x644 0x3 0x2 -#define MX6SL_PAD_SD2_DAT3__UART5_TX_DATA 0x268 0x570 0x000 0x4 0x0 -#define MX6SL_PAD_SD2_DAT3__UART5_RX_DATA 0x268 0x570 0x81c 0x4 0x5 -#define MX6SL_PAD_SD2_DAT3__GPIO4_IO28 0x268 0x570 0x000 0x5 0x0 -#define MX6SL_PAD_SD2_DAT4__SD2_DATA4 0x26c 0x574 0x000 0x0 0x0 -#define MX6SL_PAD_SD2_DAT4__SD3_DATA4 0x26c 0x574 0x83c 0x1 0x1 -#define MX6SL_PAD_SD2_DAT4__UART2_RX_DATA 0x26c 0x574 0x804 0x2 0x4 -#define MX6SL_PAD_SD2_DAT4__UART2_TX_DATA 0x26c 0x574 0x000 0x2 0x0 -#define MX6SL_PAD_SD2_DAT4__CSI_DATA06 0x26c 0x574 0x648 0x3 0x2 -#define MX6SL_PAD_SD2_DAT4__SPDIF_OUT 0x26c 0x574 0x000 0x4 0x0 -#define MX6SL_PAD_SD2_DAT4__GPIO5_IO02 0x26c 0x574 0x000 0x5 0x0 -#define MX6SL_PAD_SD2_DAT5__SD2_DATA5 0x270 0x578 0x000 0x0 0x0 -#define MX6SL_PAD_SD2_DAT5__SD3_DATA5 0x270 0x578 0x840 0x1 0x1 -#define MX6SL_PAD_SD2_DAT5__UART2_TX_DATA 0x270 0x578 0x000 0x2 0x0 -#define MX6SL_PAD_SD2_DAT5__UART2_RX_DATA 0x270 0x578 0x804 0x2 0x5 -#define MX6SL_PAD_SD2_DAT5__CSI_DATA07 0x270 0x578 0x64c 0x3 0x2 -#define MX6SL_PAD_SD2_DAT5__SPDIF_IN 0x270 0x578 0x7f0 0x4 0x2 -#define MX6SL_PAD_SD2_DAT5__GPIO4_IO31 0x270 0x578 0x000 0x5 0x0 -#define MX6SL_PAD_SD2_DAT6__SD2_DATA6 0x274 0x57c 0x000 0x0 0x0 -#define MX6SL_PAD_SD2_DAT6__SD3_DATA6 0x274 0x57c 0x844 0x1 0x1 -#define MX6SL_PAD_SD2_DAT6__UART2_RTS_B 0x274 0x57c 0x800 0x2 0x4 -#define MX6SL_PAD_SD2_DAT6__UART2_CTS_B 0x274 0x57c 0x000 0x2 0x0 -#define MX6SL_PAD_SD2_DAT6__CSI_DATA08 0x274 0x57c 0x650 0x3 0x2 -#define MX6SL_PAD_SD2_DAT6__SD2_WP 0x274 0x57c 0x834 0x4 0x2 -#define MX6SL_PAD_SD2_DAT6__GPIO4_IO29 0x274 0x57c 0x000 0x5 0x0 -#define MX6SL_PAD_SD2_DAT7__SD2_DATA7 0x278 0x580 0x000 0x0 0x0 -#define MX6SL_PAD_SD2_DAT7__SD3_DATA7 0x278 0x580 0x848 0x1 0x1 -#define MX6SL_PAD_SD2_DAT7__UART2_CTS_B 0x278 0x580 0x000 0x2 0x0 -#define MX6SL_PAD_SD2_DAT7__UART2_RTS_B 0x278 0x580 0x800 0x2 0x5 -#define MX6SL_PAD_SD2_DAT7__CSI_DATA09 0x278 0x580 0x654 0x3 0x2 -#define MX6SL_PAD_SD2_DAT7__SD2_CD_B 0x278 0x580 0x830 0x4 0x2 -#define MX6SL_PAD_SD2_DAT7__GPIO5_IO00 0x278 0x580 0x000 0x5 0x0 -#define MX6SL_PAD_SD2_RST__SD2_RESET 0x27c 0x584 0x000 0x0 0x0 -#define MX6SL_PAD_SD2_RST__FEC_REF_OUT 0x27c 0x584 0x000 0x1 0x0 -#define MX6SL_PAD_SD2_RST__WDOG2_B 0x27c 0x584 0x000 0x2 0x0 -#define MX6SL_PAD_SD2_RST__SPDIF_OUT 0x27c 0x584 0x000 0x3 0x0 -#define MX6SL_PAD_SD2_RST__CSI_MCLK 0x27c 0x584 0x000 0x4 0x0 -#define MX6SL_PAD_SD2_RST__GPIO4_IO27 0x27c 0x584 0x000 0x5 0x0 -#define MX6SL_PAD_SD3_CLK__SD3_CLK 0x280 0x588 0x000 0x0 0x0 -#define MX6SL_PAD_SD3_CLK__AUD5_RXFS 0x280 0x588 0x608 0x1 0x1 -#define MX6SL_PAD_SD3_CLK__KEY_COL5 0x280 0x588 0x748 0x2 0x2 -#define MX6SL_PAD_SD3_CLK__CSI_DATA10 0x280 0x588 0x658 0x3 0x2 -#define MX6SL_PAD_SD3_CLK__WDOG1_RESET_B_DEB 0x280 0x588 0x000 0x4 0x0 -#define MX6SL_PAD_SD3_CLK__GPIO5_IO18 0x280 0x588 0x000 0x5 0x0 -#define MX6SL_PAD_SD3_CLK__USB_OTG1_PWR 0x280 0x588 0x000 0x6 0x0 -#define MX6SL_PAD_SD3_CMD__SD3_CMD 0x284 0x58c 0x000 0x0 0x0 -#define MX6SL_PAD_SD3_CMD__AUD5_RXC 0x284 0x58c 0x604 0x1 0x1 -#define MX6SL_PAD_SD3_CMD__KEY_ROW5 0x284 0x58c 0x768 0x2 0x2 -#define MX6SL_PAD_SD3_CMD__CSI_DATA11 0x284 0x58c 0x65c 0x3 0x2 -#define MX6SL_PAD_SD3_CMD__USB_OTG2_ID 0x284 0x58c 0x5e0 0x4 0x3 -#define MX6SL_PAD_SD3_CMD__GPIO5_IO21 0x284 0x58c 0x000 0x5 0x0 -#define MX6SL_PAD_SD3_CMD__USB_OTG2_PWR 0x284 0x58c 0x000 0x6 0x0 -#define MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x288 0x590 0x000 0x0 0x0 -#define MX6SL_PAD_SD3_DAT0__AUD5_RXD 0x288 0x590 0x5fc 0x1 0x1 -#define MX6SL_PAD_SD3_DAT0__KEY_COL6 0x288 0x590 0x74c 0x2 0x2 -#define MX6SL_PAD_SD3_DAT0__CSI_DATA12 0x288 0x590 0x660 0x3 0x1 -#define MX6SL_PAD_SD3_DAT0__USB_OTG1_ID 0x288 0x590 0x5dc 0x4 0x4 -#define MX6SL_PAD_SD3_DAT0__GPIO5_IO19 0x288 0x590 0x000 0x5 0x0 -#define MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x28c 0x594 0x000 0x0 0x0 -#define MX6SL_PAD_SD3_DAT1__AUD5_TXC 0x28c 0x594 0x60c 0x1 0x1 -#define MX6SL_PAD_SD3_DAT1__KEY_ROW6 0x28c 0x594 0x76c 0x2 0x2 -#define MX6SL_PAD_SD3_DAT1__CSI_DATA13 0x28c 0x594 0x664 0x3 0x1 -#define MX6SL_PAD_SD3_DAT1__SD1_VSELECT 0x28c 0x594 0x000 0x4 0x0 -#define MX6SL_PAD_SD3_DAT1__GPIO5_IO20 0x28c 0x594 0x000 0x5 0x0 -#define MX6SL_PAD_SD3_DAT1__JTAG_DE_B 0x28c 0x594 0x000 0x6 0x0 -#define MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x290 0x598 0x000 0x0 0x0 -#define MX6SL_PAD_SD3_DAT2__AUD5_TXFS 0x290 0x598 0x610 0x1 0x1 -#define MX6SL_PAD_SD3_DAT2__KEY_COL7 0x290 0x598 0x750 0x2 0x2 -#define MX6SL_PAD_SD3_DAT2__CSI_DATA14 0x290 0x598 0x668 0x3 0x1 -#define MX6SL_PAD_SD3_DAT2__EPIT1_OUT 0x290 0x598 0x000 0x4 0x0 -#define MX6SL_PAD_SD3_DAT2__GPIO5_IO16 0x290 0x598 0x000 0x5 0x0 -#define MX6SL_PAD_SD3_DAT2__USB_OTG2_OC 0x290 0x598 0x820 0x6 0x3 -#define MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x294 0x59c 0x000 0x0 0x0 -#define MX6SL_PAD_SD3_DAT3__AUD5_TXD 0x294 0x59c 0x600 0x1 0x1 -#define MX6SL_PAD_SD3_DAT3__KEY_ROW7 0x294 0x59c 0x770 0x2 0x2 -#define MX6SL_PAD_SD3_DAT3__CSI_DATA15 0x294 0x59c 0x66c 0x3 0x1 -#define MX6SL_PAD_SD3_DAT3__EPIT2_OUT 0x294 0x59c 0x000 0x4 0x0 -#define MX6SL_PAD_SD3_DAT3__GPIO5_IO17 0x294 0x59c 0x000 0x5 0x0 -#define MX6SL_PAD_SD3_DAT3__USB_OTG1_OC 0x294 0x59c 0x824 0x6 0x2 -#define MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x298 0x5a0 0x7fc 0x0 0x0 -#define MX6SL_PAD_UART1_RXD__UART1_TX_DATA 0x298 0x5a0 0x000 0x0 0x0 -#define MX6SL_PAD_UART1_RXD__PWM1_OUT 0x298 0x5a0 0x000 0x1 0x0 -#define MX6SL_PAD_UART1_RXD__UART4_RX_DATA 0x298 0x5a0 0x814 0x2 0x6 -#define MX6SL_PAD_UART1_RXD__UART4_TX_DATA 0x298 0x5a0 0x000 0x2 0x0 -#define MX6SL_PAD_UART1_RXD__FEC_COL 0x298 0x5a0 0x6f0 0x3 0x2 -#define MX6SL_PAD_UART1_RXD__UART5_RX_DATA 0x298 0x5a0 0x81c 0x4 0x6 -#define MX6SL_PAD_UART1_RXD__UART5_TX_DATA 0x298 0x5a0 0x000 0x4 0x0 -#define MX6SL_PAD_UART1_RXD__GPIO3_IO16 0x298 0x5a0 0x000 0x5 0x0 -#define MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x29c 0x5a4 0x000 0x0 0x0 -#define MX6SL_PAD_UART1_TXD__UART1_RX_DATA 0x29c 0x5a4 0x7fc 0x0 0x1 -#define MX6SL_PAD_UART1_TXD__PWM2_OUT 0x29c 0x5a4 0x000 0x1 0x0 -#define MX6SL_PAD_UART1_TXD__UART4_TX_DATA 0x29c 0x5a4 0x000 0x2 0x0 -#define MX6SL_PAD_UART1_TXD__UART4_RX_DATA 0x29c 0x5a4 0x814 0x2 0x7 -#define MX6SL_PAD_UART1_TXD__FEC_RX_CLK 0x29c 0x5a4 0x700 0x3 0x2 -#define MX6SL_PAD_UART1_TXD__UART5_TX_DATA 0x29c 0x5a4 0x000 0x4 0x0 -#define MX6SL_PAD_UART1_TXD__UART5_RX_DATA 0x29c 0x5a4 0x81c 0x4 0x7 -#define MX6SL_PAD_UART1_TXD__GPIO3_IO17 0x29c 0x5a4 0x000 0x5 0x0 -#define MX6SL_PAD_UART1_TXD__UART5_DCD_B 0x29c 0x5a4 0x000 0x7 0x0 -#define MX6SL_PAD_WDOG_B__WDOG1_B 0x2a0 0x5a8 0x000 0x0 0x0 -#define MX6SL_PAD_WDOG_B__WDOG1_RESET_B_DEB 0x2a0 0x5a8 0x000 0x1 0x0 -#define MX6SL_PAD_WDOG_B__UART5_RI_B 0x2a0 0x5a8 0x000 0x2 0x0 -#define MX6SL_PAD_WDOG_B__GPIO3_IO18 0x2a0 0x5a8 0x000 0x5 0x0 - -#endif /* __DTS_IMX6SL_PINFUNC_H */ diff --git a/sys/gnu/dts/arm/imx6sl-tolino-shine3.dts b/sys/gnu/dts/arm/imx6sl-tolino-shine3.dts deleted file mode 100644 index 27143ea0f0f..00000000000 --- a/sys/gnu/dts/arm/imx6sl-tolino-shine3.dts +++ /dev/null @@ -1,322 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0) -/* - * Device tree for the Tolino Shine 3 ebook reader - * - * Name on mainboard is: 37NB-E60K00+4A4 - * Serials start with: E60K02 (a number also seen in - * vendor kernel sources) - * - * This mainboard seems to be equipped with different SoCs. - * In the Toline Shine 3 ebook reader it is a i.MX6SL - * - * Copyright 2019 Andreas Kemnade - * based on works - * Copyright 2016 Freescale Semiconductor, Inc. - */ - -/dts-v1/; - -#include -#include -#include "imx6sl.dtsi" -#include "e60k02.dtsi" - -/ { - model = "Tolino Shine 3"; - compatible = "kobo,tolino-shine3", "fsl,imx6sl"; -}; - -&gpio_keys { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_keys>; -}; - -&i2c1 { - pinctrl-names = "default","sleep"; - pinctrl-0 = <&pinctrl_i2c1>; - pinctrl-1 = <&pinctrl_i2c1_sleep>; -}; - -&i2c2 { - pinctrl-names = "default","sleep"; - pinctrl-0 = <&pinctrl_i2c2>; - pinctrl-1 = <&pinctrl_i2c2_sleep>; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_gpio_keys: gpio-keysgrp { - fsl,pins = < - MX6SL_PAD_SD1_DAT1__GPIO5_IO08 0x17059 /* PWR_SW */ - MX6SL_PAD_SD1_DAT4__GPIO5_IO12 0x17059 /* HALL_EN */ - >; - }; - - pinctrl_hog: hoggrp { - fsl,pins = < - MX6SL_PAD_LCD_DAT0__GPIO2_IO20 0x79 - MX6SL_PAD_LCD_DAT1__GPIO2_IO21 0x79 - MX6SL_PAD_LCD_DAT2__GPIO2_IO22 0x79 - MX6SL_PAD_LCD_DAT3__GPIO2_IO23 0x79 - MX6SL_PAD_LCD_DAT4__GPIO2_IO24 0x79 - MX6SL_PAD_LCD_DAT5__GPIO2_IO25 0x79 - MX6SL_PAD_LCD_DAT6__GPIO2_IO26 0x79 - MX6SL_PAD_LCD_DAT7__GPIO2_IO27 0x79 - MX6SL_PAD_LCD_DAT8__GPIO2_IO28 0x79 - MX6SL_PAD_LCD_DAT9__GPIO2_IO29 0x79 - MX6SL_PAD_LCD_DAT10__GPIO2_IO30 0x79 - MX6SL_PAD_LCD_DAT11__GPIO2_IO31 0x79 - MX6SL_PAD_LCD_DAT12__GPIO3_IO00 0x79 - MX6SL_PAD_LCD_DAT13__GPIO3_IO01 0x79 - MX6SL_PAD_LCD_DAT14__GPIO3_IO02 0x79 - MX6SL_PAD_LCD_DAT15__GPIO3_IO03 0x79 - MX6SL_PAD_LCD_DAT16__GPIO3_IO04 0x79 - MX6SL_PAD_LCD_DAT17__GPIO3_IO05 0x79 - MX6SL_PAD_LCD_DAT18__GPIO3_IO06 0x79 - MX6SL_PAD_LCD_DAT19__GPIO3_IO07 0x79 - MX6SL_PAD_LCD_DAT20__GPIO3_IO08 0x79 - MX6SL_PAD_LCD_DAT21__GPIO3_IO09 0x79 - MX6SL_PAD_LCD_DAT22__GPIO3_IO10 0x79 - MX6SL_PAD_LCD_DAT23__GPIO3_IO11 0x79 - MX6SL_PAD_LCD_CLK__GPIO2_IO15 0x79 - MX6SL_PAD_LCD_ENABLE__GPIO2_IO16 0x79 - MX6SL_PAD_LCD_HSYNC__GPIO2_IO17 0x79 - MX6SL_PAD_LCD_VSYNC__GPIO2_IO18 0x79 - MX6SL_PAD_LCD_RESET__GPIO2_IO19 0x79 - MX6SL_PAD_KEY_COL3__GPIO3_IO30 0x79 - MX6SL_PAD_KEY_ROW7__GPIO4_IO07 0x79 - MX6SL_PAD_ECSPI2_MOSI__GPIO4_IO13 0x79 - MX6SL_PAD_KEY_COL5__GPIO4_IO02 0x79 - MX6SL_PAD_KEY_ROW6__GPIO4_IO05 0x79 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x4001f8b1 - MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x4001f8b1 - >; - }; - - pinctrl_i2c1_sleep: i2c1grp-sleep { - fsl,pins = < - MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x400108b1 - MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x400108b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6SL_PAD_I2C2_SCL__I2C2_SCL 0x4001f8b1 - MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x4001f8b1 - >; - }; - - pinctrl_i2c2_sleep: i2c2grp-sleep { - fsl,pins = < - MX6SL_PAD_I2C2_SCL__I2C2_SCL 0x400108b1 - MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x400108b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6SL_PAD_REF_CLK_24M__I2C3_SCL 0x4001f8b1 - MX6SL_PAD_REF_CLK_32K__I2C3_SDA 0x4001f8b1 - >; - }; - - pinctrl_led: ledgrp { - fsl,pins = < - MX6SL_PAD_SD1_DAT6__GPIO5_IO07 0x17059 - >; - }; - - pinctrl_lm3630a_bl_gpio: lm3630a-bl-gpiogrp { - fsl,pins = < - MX6SL_PAD_EPDC_PWRCTRL3__GPIO2_IO10 0x10059 /* HWEN */ - >; - }; - - pinctrl_ricoh_gpio: ricoh_gpiogrp { - fsl,pins = < - MX6SL_PAD_SD1_CLK__GPIO5_IO15 0x1b8b1 /* ricoh619 chg */ - MX6SL_PAD_SD1_DAT0__GPIO5_IO11 0x1b8b1 /* ricoh619 irq */ - MX6SL_PAD_KEY_COL2__GPIO3_IO28 0x1b8b1 /* ricoh619 bat_low_int */ - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1 - MX6SL_PAD_UART1_RXD__UART1_TX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg1: usbotg1grp { - fsl,pins = < - MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID 0x17059 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6SL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6SL_PAD_SD2_CLK__SD2_CLK 0x13059 - MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x17059 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2grp-100mhz { - fsl,pins = < - MX6SL_PAD_SD2_CMD__SD2_CMD 0x170b9 - MX6SL_PAD_SD2_CLK__SD2_CLK 0x130b9 - MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 - MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 - MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 - MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2grp-200mhz { - fsl,pins = < - MX6SL_PAD_SD2_CMD__SD2_CMD 0x170f9 - MX6SL_PAD_SD2_CLK__SD2_CLK 0x130f9 - MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 - MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 - MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 - MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170f9 - >; - }; - - pinctrl_usdhc2_sleep: usdhc2grp-sleep { - fsl,pins = < - MX6SL_PAD_SD2_CMD__GPIO5_IO04 0x100f9 - MX6SL_PAD_SD2_CLK__GPIO5_IO05 0x100f9 - MX6SL_PAD_SD2_DAT0__GPIO5_IO01 0x100f9 - MX6SL_PAD_SD2_DAT1__GPIO4_IO30 0x100f9 - MX6SL_PAD_SD2_DAT2__GPIO5_IO03 0x100f9 - MX6SL_PAD_SD2_DAT3__GPIO4_IO28 0x100f9 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6SL_PAD_SD3_CMD__SD3_CMD 0x11059 - MX6SL_PAD_SD3_CLK__SD3_CLK 0x11059 - MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x11059 - MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x11059 - MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x11059 - MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x11059 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3grp-100mhz { - fsl,pins = < - MX6SL_PAD_SD3_CMD__SD3_CMD 0x170b9 - MX6SL_PAD_SD3_CLK__SD3_CLK 0x170b9 - MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 - MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 - MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 - MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3grp-200mhz { - fsl,pins = < - MX6SL_PAD_SD3_CMD__SD3_CMD 0x170f9 - MX6SL_PAD_SD3_CLK__SD3_CLK 0x170f9 - MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 - MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 - MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 - MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 - >; - }; - - pinctrl_usdhc3_sleep: usdhc3grp-sleep { - fsl,pins = < - MX6SL_PAD_SD3_CMD__GPIO5_IO21 0x100c1 - MX6SL_PAD_SD3_CLK__GPIO5_IO18 0x100c1 - MX6SL_PAD_SD3_DAT0__GPIO5_IO19 0x100c1 - MX6SL_PAD_SD3_DAT1__GPIO5_IO20 0x100c1 - MX6SL_PAD_SD3_DAT2__GPIO5_IO16 0x100c1 - MX6SL_PAD_SD3_DAT3__GPIO5_IO17 0x100c1 - >; - }; - - pinctrl_wifi_power: wifi-powergrp { - fsl,pins = < - MX6SL_PAD_SD2_DAT6__GPIO4_IO29 0x10059 /* WIFI_3V3_ON */ - >; - }; - - pinctrl_wifi_reset: wifi-resetgrp { - fsl,pins = < - MX6SL_PAD_SD2_DAT7__GPIO5_IO00 0x10059 /* WIFI_RST */ - >; - }; -}; - -&leds { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_led>; -}; - -&lm3630a { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lm3630a_bl_gpio>; -}; - -®_wifi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wifi_power>; -}; - -®_vdd1p1 { - vin-supply = <&dcdc2_reg>; -}; - -®_vdd2p5 { - vin-supply = <&dcdc2_reg>; -}; - -&ricoh619 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ricoh_gpio>; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; -}; - -&usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; - pinctrl-0 = <&pinctrl_usdhc2>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>; - pinctrl-3 = <&pinctrl_usdhc2_sleep>; -}; - -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - pinctrl-3 = <&pinctrl_usdhc3_sleep>; -}; - -&wifi_pwrseq { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wifi_reset>; -}; diff --git a/sys/gnu/dts/arm/imx6sl-warp.dts b/sys/gnu/dts/arm/imx6sl-warp.dts deleted file mode 100644 index 408da704c45..00000000000 --- a/sys/gnu/dts/arm/imx6sl-warp.dts +++ /dev/null @@ -1,234 +0,0 @@ -/* - * Copyright 2014, 2015 O.S. Systems Software LTDA. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include -#include "imx6sl.dtsi" - -/ { - model = "WaRP Board"; - compatible = "warp,imx6sl-warp", "fsl,imx6sl"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000>; - }; - - usdhc3_pwrseq: usdhc3_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>, /* WL_REG_ON */ - <&gpio4 7 GPIO_ACTIVE_LOW>, /* WL_HOSTWAKE */ - <&gpio3 25 GPIO_ACTIVE_LOW>, /* BT_REG_ON */ - <&gpio3 27 GPIO_ACTIVE_LOW>, /* BT_HOSTWAKE */ - <&gpio4 4 GPIO_ACTIVE_LOW>, /* BT_WAKE */ - <&gpio4 6 GPIO_ACTIVE_LOW>; /* BT_RST_N */ - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - uart-has-rtscts; - status = "okay"; -}; - -&usbotg1 { - dr_mode = "peripheral"; - disable-over-current; - status = "okay"; -}; - -&usbotg2 { - dr_mode = "host"; - disable-over-current; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - bus-width = <4>; - non-removable; - keep-power-in-suspend; - wakeup-source; - mmc-pwrseq = <&usdhc3_pwrseq>; - status = "okay"; -}; - -&iomuxc { - imx6sl-warp { - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x41b0b1 - MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x41b0b1 - >; - }; - - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6SL_PAD_AUD_RXC__UART3_RX_DATA 0x41b0b1 - MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x41b0b1 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6SL_PAD_ECSPI1_SCLK__UART5_RX_DATA 0x41b0b1 - MX6SL_PAD_ECSPI1_MOSI__UART5_TX_DATA 0x41b0b1 - MX6SL_PAD_ECSPI1_MISO__UART5_RTS_B 0x4130b1 - MX6SL_PAD_ECSPI1_SS0__UART5_CTS_B 0x4130b1 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6SL_PAD_SD2_CMD__SD2_CMD 0x417059 - MX6SL_PAD_SD2_CLK__SD2_CLK 0x410059 - MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x417059 - MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x417059 - MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x417059 - MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x417059 - MX6SL_PAD_SD2_DAT4__SD2_DATA4 0x417059 - MX6SL_PAD_SD2_DAT5__SD2_DATA5 0x417059 - MX6SL_PAD_SD2_DAT6__SD2_DATA6 0x417059 - MX6SL_PAD_SD2_DAT7__SD2_DATA7 0x417059 - MX6SL_PAD_SD2_RST__SD2_RESET 0x417059 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2grp100mhz { - fsl,pins = < - MX6SL_PAD_SD2_CMD__SD2_CMD 0x4170b9 - MX6SL_PAD_SD2_CLK__SD2_CLK 0x4100b9 - MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x4170b9 - MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x4170b9 - MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x4170b9 - MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x4170b9 - MX6SL_PAD_SD2_DAT4__SD2_DATA4 0x4170b9 - MX6SL_PAD_SD2_DAT5__SD2_DATA5 0x4170b9 - MX6SL_PAD_SD2_DAT6__SD2_DATA6 0x4170b9 - MX6SL_PAD_SD2_DAT7__SD2_DATA7 0x4170b9 - MX6SL_PAD_SD2_RST__SD2_RESET 0x4170b9 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2grp200mhz { - fsl,pins = < - MX6SL_PAD_SD2_CMD__SD2_CMD 0x4170f9 - MX6SL_PAD_SD2_CLK__SD2_CLK 0x4100f9 - MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x4170f9 - MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x4170f9 - MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x4170f9 - MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x4170f9 - MX6SL_PAD_SD2_DAT4__SD2_DATA4 0x4170f9 - MX6SL_PAD_SD2_DAT5__SD2_DATA5 0x4170f9 - MX6SL_PAD_SD2_DAT6__SD2_DATA6 0x4170f9 - MX6SL_PAD_SD2_DAT7__SD2_DATA7 0x4170f9 - MX6SL_PAD_SD2_RST__SD2_RESET 0x4170f9 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6SL_PAD_SD3_CMD__SD3_CMD 0x417059 - MX6SL_PAD_SD3_CLK__SD3_CLK 0x410059 - MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x417059 - MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x417059 - MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x417059 - MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x417059 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3grp100mhz { - fsl,pins = < - MX6SL_PAD_SD3_CMD__SD3_CMD 0x4170b9 - MX6SL_PAD_SD3_CLK__SD3_CLK 0x4100b9 - MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x4170b9 - MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x4170b9 - MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x4170b9 - MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x4170b9 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3grp200mhz { - fsl,pins = < - MX6SL_PAD_SD3_CMD__SD3_CMD 0x4170f9 - MX6SL_PAD_SD3_CLK__SD3_CLK 0x4100f9 - MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x4170f9 - MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x4170f9 - MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x4170f9 - MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x4170f9 - >; - }; - }; -}; diff --git a/sys/gnu/dts/arm/imx6sl.dtsi b/sys/gnu/dts/arm/imx6sl.dtsi deleted file mode 100644 index 59c54e6ad09..00000000000 --- a/sys/gnu/dts/arm/imx6sl.dtsi +++ /dev/null @@ -1,985 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// -// Copyright 2013 Freescale Semiconductor, Inc. - -#include -#include "imx6sl-pinfunc.h" -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - /* - * The decompressor and also some bootloaders rely on a - * pre-existing /chosen node to be available to insert the - * command line and merge other ATAGS info. - */ - chosen {}; - - aliases { - ethernet0 = &fec; - gpio0 = &gpio1; - gpio1 = &gpio2; - gpio2 = &gpio3; - gpio3 = &gpio4; - gpio4 = &gpio5; - i2c0 = &i2c1; - i2c1 = &i2c2; - i2c2 = &i2c3; - mmc0 = &usdhc1; - mmc1 = &usdhc2; - mmc2 = &usdhc3; - mmc3 = &usdhc4; - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - serial3 = &uart4; - serial4 = &uart5; - spi0 = &ecspi1; - spi1 = &ecspi2; - spi2 = &ecspi3; - spi3 = &ecspi4; - usbphy0 = &usbphy1; - usbphy1 = &usbphy2; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - reg = <0x0>; - next-level-cache = <&L2>; - operating-points = < - /* kHz uV */ - 996000 1275000 - 792000 1175000 - 396000 975000 - >; - fsl,soc-operating-points = < - /* ARM kHz SOC-PU uV */ - 996000 1225000 - 792000 1175000 - 396000 1175000 - >; - clock-latency = <61036>; /* two CLK32 periods */ - #cooling-cells = <2>; - clocks = <&clks IMX6SL_CLK_ARM>, <&clks IMX6SL_CLK_PLL2_PFD2>, - <&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_CLK_PLL1_SW>, - <&clks IMX6SL_CLK_PLL1_SYS>; - clock-names = "arm", "pll2_pfd2_396m", "step", - "pll1_sw", "pll1_sys"; - arm-supply = <®_arm>; - pu-supply = <®_pu>; - soc-supply = <®_soc>; - }; - }; - - clocks { - ckil { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - - osc { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - }; - }; - - tempmon: tempmon { - compatible = "fsl,imx6q-tempmon"; - interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>; - interrupt-parent = <&gpc>; - fsl,tempmon = <&anatop>; - fsl,tempmon-data = <&ocotp>; - clocks = <&clks IMX6SL_CLK_PLL3_USB_OTG>; - }; - - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupt-parent = <&gpc>; - interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>; - }; - - usbphynop1: usbphynop1 { - compatible = "usb-nop-xceiv"; - #phy-cells = <0>; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&gpc>; - ranges; - - ocram: sram@900000 { - compatible = "mmio-sram"; - reg = <0x00900000 0x20000>; - clocks = <&clks IMX6SL_CLK_OCRAM>; - }; - - intc: interrupt-controller@a01000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x00a01000 0x1000>, - <0x00a00100 0x100>; - interrupt-parent = <&intc>; - }; - - L2: l2-cache@a02000 { - compatible = "arm,pl310-cache"; - reg = <0x00a02000 0x1000>; - interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>; - cache-unified; - cache-level = <2>; - arm,tag-latency = <4 2 3>; - arm,data-latency = <4 2 3>; - }; - - aips1: aips-bus@2000000 { - compatible = "fsl,aips-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x02000000 0x100000>; - ranges; - - spba: spba-bus@2000000 { - compatible = "fsl,spba-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x02000000 0x40000>; - ranges; - - spdif: spdif@2004000 { - compatible = "fsl,imx6sl-spdif", - "fsl,imx35-spdif"; - reg = <0x02004000 0x4000>; - interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&sdma 14 18 0>, - <&sdma 15 18 0>; - dma-names = "rx", "tx"; - clocks = <&clks IMX6SL_CLK_SPDIF_GCLK>, <&clks IMX6SL_CLK_OSC>, - <&clks IMX6SL_CLK_SPDIF>, <&clks IMX6SL_CLK_DUMMY>, - <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_DUMMY>, - <&clks IMX6SL_CLK_IPG>, <&clks IMX6SL_CLK_DUMMY>, - <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_SPBA>; - clock-names = "core", "rxtx0", - "rxtx1", "rxtx2", - "rxtx3", "rxtx4", - "rxtx5", "rxtx6", - "rxtx7", "spba"; - status = "disabled"; - }; - - ecspi1: spi@2008000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi"; - reg = <0x02008000 0x4000>; - interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_ECSPI1>, - <&clks IMX6SL_CLK_ECSPI1>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - ecspi2: spi@200c000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi"; - reg = <0x0200c000 0x4000>; - interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_ECSPI2>, - <&clks IMX6SL_CLK_ECSPI2>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - ecspi3: spi@2010000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi"; - reg = <0x02010000 0x4000>; - interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_ECSPI3>, - <&clks IMX6SL_CLK_ECSPI3>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - ecspi4: spi@2014000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi"; - reg = <0x02014000 0x4000>; - interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_ECSPI4>, - <&clks IMX6SL_CLK_ECSPI4>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart5: serial@2018000 { - compatible = "fsl,imx6sl-uart", - "fsl,imx6q-uart", "fsl,imx21-uart"; - reg = <0x02018000 0x4000>; - interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_UART>, - <&clks IMX6SL_CLK_UART_SERIAL>; - clock-names = "ipg", "per"; - dmas = <&sdma 33 4 0>, <&sdma 34 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart1: serial@2020000 { - compatible = "fsl,imx6sl-uart", - "fsl,imx6q-uart", "fsl,imx21-uart"; - reg = <0x02020000 0x4000>; - interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_UART>, - <&clks IMX6SL_CLK_UART_SERIAL>; - clock-names = "ipg", "per"; - dmas = <&sdma 25 4 0>, <&sdma 26 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart2: serial@2024000 { - compatible = "fsl,imx6sl-uart", - "fsl,imx6q-uart", "fsl,imx21-uart"; - reg = <0x02024000 0x4000>; - interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_UART>, - <&clks IMX6SL_CLK_UART_SERIAL>; - clock-names = "ipg", "per"; - dmas = <&sdma 27 4 0>, <&sdma 28 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - ssi1: ssi@2028000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx6sl-ssi", - "fsl,imx51-ssi"; - reg = <0x02028000 0x4000>; - interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_SSI1_IPG>, - <&clks IMX6SL_CLK_SSI1>; - clock-names = "ipg", "baud"; - dmas = <&sdma 37 1 0>, - <&sdma 38 1 0>; - dma-names = "rx", "tx"; - fsl,fifo-depth = <15>; - status = "disabled"; - }; - - ssi2: ssi@202c000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx6sl-ssi", - "fsl,imx51-ssi"; - reg = <0x0202c000 0x4000>; - interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_SSI2_IPG>, - <&clks IMX6SL_CLK_SSI2>; - clock-names = "ipg", "baud"; - dmas = <&sdma 41 1 0>, - <&sdma 42 1 0>; - dma-names = "rx", "tx"; - fsl,fifo-depth = <15>; - status = "disabled"; - }; - - ssi3: ssi@2030000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx6sl-ssi", - "fsl,imx51-ssi"; - reg = <0x02030000 0x4000>; - interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_SSI3_IPG>, - <&clks IMX6SL_CLK_SSI3>; - clock-names = "ipg", "baud"; - dmas = <&sdma 45 1 0>, - <&sdma 46 1 0>; - dma-names = "rx", "tx"; - fsl,fifo-depth = <15>; - status = "disabled"; - }; - - uart3: serial@2034000 { - compatible = "fsl,imx6sl-uart", - "fsl,imx6q-uart", "fsl,imx21-uart"; - reg = <0x02034000 0x4000>; - interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_UART>, - <&clks IMX6SL_CLK_UART_SERIAL>; - clock-names = "ipg", "per"; - dmas = <&sdma 29 4 0>, <&sdma 30 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart4: serial@2038000 { - compatible = "fsl,imx6sl-uart", - "fsl,imx6q-uart", "fsl,imx21-uart"; - reg = <0x02038000 0x4000>; - interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_UART>, - <&clks IMX6SL_CLK_UART_SERIAL>; - clock-names = "ipg", "per"; - dmas = <&sdma 31 4 0>, <&sdma 32 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - }; - - pwm1: pwm@2080000 { - #pwm-cells = <2>; - compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm"; - reg = <0x02080000 0x4000>; - interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_PERCLK>, - <&clks IMX6SL_CLK_PWM1>; - clock-names = "ipg", "per"; - }; - - pwm2: pwm@2084000 { - #pwm-cells = <2>; - compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm"; - reg = <0x02084000 0x4000>; - interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_PERCLK>, - <&clks IMX6SL_CLK_PWM2>; - clock-names = "ipg", "per"; - }; - - pwm3: pwm@2088000 { - #pwm-cells = <2>; - compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm"; - reg = <0x02088000 0x4000>; - interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_PERCLK>, - <&clks IMX6SL_CLK_PWM3>; - clock-names = "ipg", "per"; - }; - - pwm4: pwm@208c000 { - #pwm-cells = <2>; - compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm"; - reg = <0x0208c000 0x4000>; - interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_PERCLK>, - <&clks IMX6SL_CLK_PWM4>; - clock-names = "ipg", "per"; - }; - - gpt: gpt@2098000 { - compatible = "fsl,imx6sl-gpt"; - reg = <0x02098000 0x4000>; - interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_GPT>, - <&clks IMX6SL_CLK_GPT_SERIAL>; - clock-names = "ipg", "per"; - }; - - gpio1: gpio@209c000 { - compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio"; - reg = <0x0209c000 0x4000>; - interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>, - <0 67 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 22 1>, <&iomuxc 1 20 2>, - <&iomuxc 3 23 1>, <&iomuxc 4 25 1>, - <&iomuxc 5 24 1>, <&iomuxc 6 19 1>, - <&iomuxc 7 36 2>, <&iomuxc 9 44 8>, - <&iomuxc 17 38 6>, <&iomuxc 23 68 4>, - <&iomuxc 27 64 4>, <&iomuxc 31 52 1>; - }; - - gpio2: gpio@20a0000 { - compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio"; - reg = <0x020a0000 0x4000>; - interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>, - <0 69 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 53 3>, <&iomuxc 3 72 2>, - <&iomuxc 5 34 2>, <&iomuxc 7 57 4>, - <&iomuxc 11 56 1>, <&iomuxc 12 61 3>, - <&iomuxc 15 107 1>, <&iomuxc 16 132 2>, - <&iomuxc 18 135 1>, <&iomuxc 19 134 1>, - <&iomuxc 20 108 2>, <&iomuxc 22 120 1>, - <&iomuxc 23 125 7>, <&iomuxc 30 110 2>; - }; - - gpio3: gpio@20a4000 { - compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio"; - reg = <0x020a4000 0x4000>; - interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>, - <0 71 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 112 8>, <&iomuxc 8 121 4>, - <&iomuxc 12 97 4>, <&iomuxc 16 166 3>, - <&iomuxc 19 85 2>, <&iomuxc 21 137 2>, - <&iomuxc 23 136 1>, <&iomuxc 24 91 1>, - <&iomuxc 25 99 1>, <&iomuxc 26 92 1>, - <&iomuxc 27 100 1>, <&iomuxc 28 93 1>, - <&iomuxc 29 101 1>, <&iomuxc 30 94 1>, - <&iomuxc 31 102 1>; - }; - - gpio4: gpio@20a8000 { - compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio"; - reg = <0x020a8000 0x4000>; - interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>, - <0 73 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 95 1>, <&iomuxc 1 103 1>, - <&iomuxc 2 96 1>, <&iomuxc 3 104 1>, - <&iomuxc 4 97 1>, <&iomuxc 5 105 1>, - <&iomuxc 6 98 1>, <&iomuxc 7 106 1>, - <&iomuxc 8 28 1>, <&iomuxc 9 27 1>, - <&iomuxc 10 26 1>, <&iomuxc 11 29 1>, - <&iomuxc 12 32 1>, <&iomuxc 13 31 1>, - <&iomuxc 14 30 1>, <&iomuxc 15 33 1>, - <&iomuxc 16 84 1>, <&iomuxc 17 79 2>, - <&iomuxc 19 78 1>, <&iomuxc 20 76 1>, - <&iomuxc 21 81 2>, <&iomuxc 23 75 1>, - <&iomuxc 24 83 1>, <&iomuxc 25 74 1>, - <&iomuxc 26 77 1>, <&iomuxc 27 159 1>, - <&iomuxc 28 154 1>, <&iomuxc 29 157 1>, - <&iomuxc 30 152 1>, <&iomuxc 31 156 1>; - }; - - gpio5: gpio@20ac000 { - compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio"; - reg = <0x020ac000 0x4000>; - interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>, - <0 75 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 158 1>, <&iomuxc 1 151 1>, - <&iomuxc 2 155 1>, <&iomuxc 3 153 1>, - <&iomuxc 4 150 1>, <&iomuxc 5 149 1>, - <&iomuxc 6 144 1>, <&iomuxc 7 147 1>, - <&iomuxc 8 142 1>, <&iomuxc 9 146 1>, - <&iomuxc 10 148 1>, <&iomuxc 11 141 1>, - <&iomuxc 12 145 1>, <&iomuxc 13 143 1>, - <&iomuxc 14 140 1>, <&iomuxc 15 139 1>, - <&iomuxc 16 164 2>, <&iomuxc 18 160 1>, - <&iomuxc 19 162 1>, <&iomuxc 20 163 1>, - <&iomuxc 21 161 1>; - }; - - kpp: kpp@20b8000 { - compatible = "fsl,imx6sl-kpp", "fsl,imx21-kpp"; - reg = <0x020b8000 0x4000>; - interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_IPG>; - status = "disabled"; - }; - - wdog1: wdog@20bc000 { - compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt"; - reg = <0x020bc000 0x4000>; - interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_IPG>; - }; - - wdog2: wdog@20c0000 { - compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt"; - reg = <0x020c0000 0x4000>; - interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_IPG>; - status = "disabled"; - }; - - clks: ccm@20c4000 { - compatible = "fsl,imx6sl-ccm"; - reg = <0x020c4000 0x4000>; - interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>, - <0 88 IRQ_TYPE_LEVEL_HIGH>; - #clock-cells = <1>; - }; - - anatop: anatop@20c8000 { - compatible = "fsl,imx6sl-anatop", - "fsl,imx6q-anatop", - "syscon", "simple-mfd"; - reg = <0x020c8000 0x1000>; - interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>, - <0 54 IRQ_TYPE_LEVEL_HIGH>, - <0 127 IRQ_TYPE_LEVEL_HIGH>; - - reg_vdd1p1: regulator-1p1 { - compatible = "fsl,anatop-regulator"; - regulator-name = "vdd1p1"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - anatop-reg-offset = <0x110>; - anatop-vol-bit-shift = <8>; - anatop-vol-bit-width = <5>; - anatop-min-bit-val = <4>; - anatop-min-voltage = <800000>; - anatop-max-voltage = <1375000>; - anatop-enable-bit = <0>; - }; - - reg_vdd3p0: regulator-3p0 { - compatible = "fsl,anatop-regulator"; - regulator-name = "vdd3p0"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <3150000>; - regulator-always-on; - anatop-reg-offset = <0x120>; - anatop-vol-bit-shift = <8>; - anatop-vol-bit-width = <5>; - anatop-min-bit-val = <0>; - anatop-min-voltage = <2625000>; - anatop-max-voltage = <3400000>; - anatop-enable-bit = <0>; - }; - - reg_vdd2p5: regulator-2p5 { - compatible = "fsl,anatop-regulator"; - regulator-name = "vdd2p5"; - regulator-min-microvolt = <2250000>; - regulator-max-microvolt = <2750000>; - regulator-always-on; - anatop-reg-offset = <0x130>; - anatop-vol-bit-shift = <8>; - anatop-vol-bit-width = <5>; - anatop-min-bit-val = <0>; - anatop-min-voltage = <2100000>; - anatop-max-voltage = <2850000>; - anatop-enable-bit = <0>; - }; - - reg_arm: regulator-vddcore { - compatible = "fsl,anatop-regulator"; - regulator-name = "vddarm"; - regulator-min-microvolt = <725000>; - regulator-max-microvolt = <1450000>; - regulator-always-on; - anatop-reg-offset = <0x140>; - anatop-vol-bit-shift = <0>; - anatop-vol-bit-width = <5>; - anatop-delay-reg-offset = <0x170>; - anatop-delay-bit-shift = <24>; - anatop-delay-bit-width = <2>; - anatop-min-bit-val = <1>; - anatop-min-voltage = <725000>; - anatop-max-voltage = <1450000>; - }; - - reg_pu: regulator-vddpu { - compatible = "fsl,anatop-regulator"; - regulator-name = "vddpu"; - regulator-min-microvolt = <725000>; - regulator-max-microvolt = <1450000>; - anatop-reg-offset = <0x140>; - anatop-vol-bit-shift = <9>; - anatop-vol-bit-width = <5>; - anatop-delay-reg-offset = <0x170>; - anatop-delay-bit-shift = <26>; - anatop-delay-bit-width = <2>; - anatop-min-bit-val = <1>; - anatop-min-voltage = <725000>; - anatop-max-voltage = <1450000>; - }; - - reg_soc: regulator-vddsoc { - compatible = "fsl,anatop-regulator"; - regulator-name = "vddsoc"; - regulator-min-microvolt = <725000>; - regulator-max-microvolt = <1450000>; - regulator-always-on; - anatop-reg-offset = <0x140>; - anatop-vol-bit-shift = <18>; - anatop-vol-bit-width = <5>; - anatop-delay-reg-offset = <0x170>; - anatop-delay-bit-shift = <28>; - anatop-delay-bit-width = <2>; - anatop-min-bit-val = <1>; - anatop-min-voltage = <725000>; - anatop-max-voltage = <1450000>; - }; - }; - - usbphy1: usbphy@20c9000 { - compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy"; - reg = <0x020c9000 0x1000>; - interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_USBPHY1>; - fsl,anatop = <&anatop>; - }; - - usbphy2: usbphy@20ca000 { - compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy"; - reg = <0x020ca000 0x1000>; - interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_USBPHY2>; - fsl,anatop = <&anatop>; - }; - - snvs: snvs@20cc000 { - compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; - reg = <0x020cc000 0x4000>; - - snvs_rtc: snvs-rtc-lp { - compatible = "fsl,sec-v4.0-mon-rtc-lp"; - regmap = <&snvs>; - offset = <0x34>; - interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>, - <0 20 IRQ_TYPE_LEVEL_HIGH>; - }; - - snvs_poweroff: snvs-poweroff { - compatible = "syscon-poweroff"; - regmap = <&snvs>; - offset = <0x38>; - value = <0x60>; - mask = <0x60>; - status = "disabled"; - }; - }; - - epit1: epit@20d0000 { - reg = <0x020d0000 0x4000>; - interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>; - }; - - epit2: epit@20d4000 { - reg = <0x020d4000 0x4000>; - interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>; - }; - - src: src@20d8000 { - compatible = "fsl,imx6sl-src", "fsl,imx51-src"; - reg = <0x020d8000 0x4000>; - interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>, - <0 96 IRQ_TYPE_LEVEL_HIGH>; - #reset-cells = <1>; - }; - - gpc: gpc@20dc000 { - compatible = "fsl,imx6sl-gpc", "fsl,imx6q-gpc"; - reg = <0x020dc000 0x4000>; - interrupt-controller; - #interrupt-cells = <3>; - interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>; - interrupt-parent = <&intc>; - clocks = <&clks IMX6SL_CLK_IPG>; - clock-names = "ipg"; - - pgc { - #address-cells = <1>; - #size-cells = <0>; - - power-domain@0 { - reg = <0>; - #power-domain-cells = <0>; - }; - - pd_pu: power-domain@1 { - reg = <1>; - #power-domain-cells = <0>; - power-supply = <®_pu>; - clocks = <&clks IMX6SL_CLK_GPU2D_OVG>, - <&clks IMX6SL_CLK_GPU2D_PODF>; - }; - - pd_disp: power-domain@2 { - reg = <2>; - #power-domain-cells = <0>; - clocks = <&clks IMX6SL_CLK_LCDIF_AXI>, - <&clks IMX6SL_CLK_LCDIF_PIX>, - <&clks IMX6SL_CLK_EPDC_AXI>, - <&clks IMX6SL_CLK_EPDC_PIX>, - <&clks IMX6SL_CLK_PXP_AXI>; - }; - }; - }; - - gpr: iomuxc-gpr@20e0000 { - compatible = "fsl,imx6sl-iomuxc-gpr", - "fsl,imx6q-iomuxc-gpr", "syscon"; - reg = <0x020e0000 0x38>; - }; - - iomuxc: iomuxc@20e0000 { - compatible = "fsl,imx6sl-iomuxc"; - reg = <0x020e0000 0x4000>; - }; - - csi: csi@20e4000 { - reg = <0x020e4000 0x4000>; - interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; - }; - - spdc: spdc@20e8000 { - reg = <0x020e8000 0x4000>; - interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; - }; - - sdma: sdma@20ec000 { - compatible = "fsl,imx6sl-sdma", "fsl,imx6q-sdma"; - reg = <0x020ec000 0x4000>; - interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_SDMA>, - <&clks IMX6SL_CLK_AHB>; - clock-names = "ipg", "ahb"; - #dma-cells = <3>; - /* imx6sl reuses imx6q sdma firmware */ - fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; - }; - - pxp: pxp@20f0000 { - reg = <0x020f0000 0x4000>; - interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; - }; - - epdc: epdc@20f4000 { - reg = <0x020f4000 0x4000>; - interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>; - }; - - lcdif: lcdif@20f8000 { - compatible = "fsl,imx6sl-lcdif", "fsl,imx28-lcdif"; - reg = <0x020f8000 0x4000>; - interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_LCDIF_PIX>, - <&clks IMX6SL_CLK_LCDIF_AXI>, - <&clks IMX6SL_CLK_DUMMY>; - clock-names = "pix", "axi", "disp_axi"; - status = "disabled"; - power-domains = <&pd_disp>; - }; - - dcp: dcp@20fc000 { - compatible = "fsl,imx6sl-dcp", "fsl,imx28-dcp"; - reg = <0x020fc000 0x4000>; - interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>, - <0 100 IRQ_TYPE_LEVEL_HIGH>, - <0 101 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - - aips2: aips-bus@2100000 { - compatible = "fsl,aips-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x02100000 0x100000>; - ranges; - - usbotg1: usb@2184000 { - compatible = "fsl,imx6sl-usb", "fsl,imx27-usb"; - reg = <0x02184000 0x200>; - interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_USBOH3>; - fsl,usbphy = <&usbphy1>; - fsl,usbmisc = <&usbmisc 0>; - ahb-burst-config = <0x0>; - tx-burst-size-dword = <0x10>; - rx-burst-size-dword = <0x10>; - status = "disabled"; - }; - - usbotg2: usb@2184200 { - compatible = "fsl,imx6sl-usb", "fsl,imx27-usb"; - reg = <0x02184200 0x200>; - interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_USBOH3>; - fsl,usbphy = <&usbphy2>; - fsl,usbmisc = <&usbmisc 1>; - ahb-burst-config = <0x0>; - tx-burst-size-dword = <0x10>; - rx-burst-size-dword = <0x10>; - status = "disabled"; - }; - - usbh: usb@2184400 { - compatible = "fsl,imx6sl-usb", "fsl,imx27-usb"; - reg = <0x02184400 0x200>; - interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_USBOH3>; - fsl,usbphy = <&usbphynop1>; - phy_type = "hsic"; - fsl,usbmisc = <&usbmisc 2>; - dr_mode = "host"; - ahb-burst-config = <0x0>; - tx-burst-size-dword = <0x10>; - rx-burst-size-dword = <0x10>; - status = "disabled"; - }; - - usbmisc: usbmisc@2184800 { - #index-cells = <1>; - compatible = "fsl,imx6sl-usbmisc", "fsl,imx6q-usbmisc"; - reg = <0x02184800 0x200>; - clocks = <&clks IMX6SL_CLK_USBOH3>; - }; - - fec: ethernet@2188000 { - compatible = "fsl,imx6sl-fec", "fsl,imx25-fec"; - reg = <0x02188000 0x4000>; - interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_ENET>, - <&clks IMX6SL_CLK_ENET_REF>; - clock-names = "ipg", "ahb"; - status = "disabled"; - }; - - usdhc1: usdhc@2190000 { - compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc"; - reg = <0x02190000 0x4000>; - interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_USDHC1>, - <&clks IMX6SL_CLK_USDHC1>, - <&clks IMX6SL_CLK_USDHC1>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - status = "disabled"; - }; - - usdhc2: usdhc@2194000 { - compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc"; - reg = <0x02194000 0x4000>; - interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_USDHC2>, - <&clks IMX6SL_CLK_USDHC2>, - <&clks IMX6SL_CLK_USDHC2>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - status = "disabled"; - }; - - usdhc3: usdhc@2198000 { - compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc"; - reg = <0x02198000 0x4000>; - interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_USDHC3>, - <&clks IMX6SL_CLK_USDHC3>, - <&clks IMX6SL_CLK_USDHC3>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - status = "disabled"; - }; - - usdhc4: usdhc@219c000 { - compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc"; - reg = <0x0219c000 0x4000>; - interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_USDHC4>, - <&clks IMX6SL_CLK_USDHC4>, - <&clks IMX6SL_CLK_USDHC4>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - status = "disabled"; - }; - - i2c1: i2c@21a0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c"; - reg = <0x021a0000 0x4000>; - interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_I2C1>; - status = "disabled"; - }; - - i2c2: i2c@21a4000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c"; - reg = <0x021a4000 0x4000>; - interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_I2C2>; - status = "disabled"; - }; - - i2c3: i2c@21a8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c"; - reg = <0x021a8000 0x4000>; - interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_I2C3>; - status = "disabled"; - }; - - memory-controller@21b0000 { - compatible = "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc"; - reg = <0x021b0000 0x4000>; - clocks = <&clks IMX6SL_CLK_MMDC_P0_IPG>; - }; - - rngb: rngb@21b4000 { - reg = <0x021b4000 0x4000>; - interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>; - }; - - weim: weim@21b8000 { - #address-cells = <2>; - #size-cells = <1>; - reg = <0x021b8000 0x4000>; - interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; - fsl,weim-cs-gpr = <&gpr>; - status = "disabled"; - }; - - ocotp: ocotp@21bc000 { - compatible = "fsl,imx6sl-ocotp", "syscon"; - reg = <0x021bc000 0x4000>; - clocks = <&clks IMX6SL_CLK_OCOTP>; - }; - - audmux: audmux@21d8000 { - compatible = "fsl,imx6sl-audmux", "fsl,imx31-audmux"; - reg = <0x021d8000 0x4000>; - status = "disabled"; - }; - }; - - gpu_2d: gpu@2200000 { - compatible = "vivante,gc"; - reg = <0x02200000 0x4000>; - interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_MMDC_ROOT>, - <&clks IMX6SL_CLK_GPU2D_OVG>; - clock-names = "bus", "core"; - power-domains = <&pd_pu>; - }; - - gpu_vg: gpu@2204000 { - compatible = "vivante,gc"; - reg = <0x02204000 0x4000>; - interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_MMDC_ROOT>, - <&clks IMX6SL_CLK_GPU2D_OVG>; - clock-names = "bus", "core"; - power-domains = <&pd_pu>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/imx6sll-evk.dts b/sys/gnu/dts/arm/imx6sll-evk.dts deleted file mode 100644 index 5ace9e6acf8..00000000000 --- a/sys/gnu/dts/arm/imx6sll-evk.dts +++ /dev/null @@ -1,502 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright 2016 Freescale Semiconductor, Inc. - * Copyright 2017-2018 NXP. - * - */ - -/dts-v1/; - -#include -#include -#include "imx6sll.dtsi" - -/ { - model = "Freescale i.MX6SLL EVK Board"; - compatible = "fsl,imx6sll-evk", "fsl,imx6sll"; - - chosen { - stdout-path = &uart1; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x80000000>; - }; - - backlight_display: backlight-display { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - status = "okay"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_led>; - - user { - label = "debug"; - gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - reg_usb_otg1_vbus: regulator-otg1-vbus { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_otg1_vbus>; - regulator-name = "usb_otg1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio4 0 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usb_otg2_vbus: regulator-otg2-vbus { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_otg2_vbus>; - regulator-name = "usb_otg2_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_aud3v: regulator-aud3v { - compatible = "regulator-fixed"; - regulator-name = "wm8962-supply-3v15"; - regulator-min-microvolt = <3150000>; - regulator-max-microvolt = <3150000>; - regulator-boot-on; - }; - - reg_aud4v: regulator-aud4v { - compatible = "regulator-fixed"; - regulator-name = "wm8962-supply-4v2"; - regulator-min-microvolt = <4325000>; - regulator-max-microvolt = <4325000>; - regulator-boot-on; - }; - - reg_lcd_3v3: regulator-lcd-3v3 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_lcd_3v3>; - regulator-name = "lcd-3v3"; - gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_lcd_5v: regulator-lcd-5v { - compatible = "regulator-fixed"; - regulator-name = "lcd-5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_sd1_vmmc: regulator-sd1-vmmc { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_sd1_vmmc>; - regulator-name = "SD1_SPWR"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_sd3_vmmc: regulator-sd3-vmmc { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_sd3_vmmc>; - regulator-name = "SD3_WIFI"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - gpio = <&gpio4 4 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - panel { - compatible = "sii,43wvf1g"; - backlight = <&backlight_display>; - dvdd-supply = <®_lcd_3v3>; - avdd-supply = <®_lcd_5v>; - - port { - panel_in: endpoint { - remote-endpoint = <&display_out>; - }; - }; - }; -}; - -&cpu0 { - arm-supply = <&sw1a_reg>; - soc-supply = <&sw1c_reg>; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pfuze100: pmic@8 { - compatible = "fsl,pfuze100"; - reg = <0x08>; - - regulators { - sw1a_reg: sw1ab { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw1c_reg: sw1c { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3a_reg: sw3a { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3b_reg: sw3b { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - sw4_reg: sw4 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - }; - - snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - vgen1_reg: vgen1 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - regulator-always-on; - }; - - vgen2_reg: vgen2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen3_reg: vgen3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - vgen4_reg: vgen4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen5_reg: vgen5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen6_reg: vgen6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; -}; - -&lcdif { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd>; - status = "okay"; - - port { - display_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "okay"; -}; - -&snvs_poweroff { - status = "okay"; -}; - -&snvs_pwrkey { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>; - cd-gpios = <&gpio4 7 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>; - keep-power-in-suspend; - wakeup-source; - vmmc-supply = <®_sd1_vmmc>; - status = "okay"; -}; - -&usbotg1 { - vbus-supply = <®_usb_otg1_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg1>; - disable-over-current; - srp-disable; - hnp-disable; - adp-disable; - status = "okay"; -}; - -&usbotg2 { - vbus-supply = <®_usb_otg2_vbus>; - dr_mode = "host"; - disable-over-current; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - cd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>; - keep-power-in-suspend; - wakeup-source; - vmmc-supply = <®_sd3_vmmc>; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog1>; - fsl,ext-reset-output; -}; - -&iomuxc { - pinctrl_reg_sd3_vmmc: sd3vmmcgrp { - fsl,pins = < - MX6SLL_PAD_KEY_COL6__GPIO4_IO04 0x17059 - >; - }; - - pinctrl_usb_otg1_vbus: vbus1grp { - fsl,pins = < - MX6SLL_PAD_KEY_COL4__GPIO4_IO00 0x17059 - >; - }; - - pinctrl_usb_otg2_vbus: vbus2grp { - fsl,pins = < - MX6SLL_PAD_KEY_COL5__GPIO4_IO02 0x17059 - >; - }; - - pinctrl_reg_lcd_3v3: reglcd3v3grp { - fsl,pins = < - MX6SLL_PAD_KEY_ROW5__GPIO4_IO03 0x17059 - >; - }; - - pinctrl_reg_sd1_vmmc: sd1vmmcgrp { - fsl,pins = < - MX6SLL_PAD_KEY_COL3__GPIO3_IO30 0x17059 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6SLL_PAD_UART1_TXD__UART1_DCE_TX 0x1b0b1 - MX6SLL_PAD_UART1_RXD__UART1_DCE_RX 0x1b0b1 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6SLL_PAD_SD1_CMD__SD1_CMD 0x17059 - MX6SLL_PAD_SD1_CLK__SD1_CLK 0x13059 - MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x17059 - MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x17059 - MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x17059 - MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x17059 - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1grp_100mhz { - fsl,pins = < - MX6SLL_PAD_SD1_CMD__SD1_CMD 0x170b9 - MX6SLL_PAD_SD1_CLK__SD1_CLK 0x130b9 - MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x170b9 - MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x170b9 - MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x170b9 - MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x170b9 - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1grp_200mhz { - fsl,pins = < - MX6SLL_PAD_SD1_CMD__SD1_CMD 0x170f9 - MX6SLL_PAD_SD1_CLK__SD1_CLK 0x130f9 - MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x170f9 - MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x170f9 - MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x170f9 - MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x170f9 - >; - }; - - pinctrl_usbotg1: usbotg1grp { - fsl,pins = < - MX6SLL_PAD_EPDC_PWR_COM__USB_OTG1_ID 0x17059 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6SLL_PAD_SD3_CMD__SD3_CMD 0x17061 - MX6SLL_PAD_SD3_CLK__SD3_CLK 0x13061 - MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x17061 - MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x17061 - MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x17061 - MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x17061 - MX6SLL_PAD_REF_CLK_32K__GPIO3_IO22 0x17059 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { - fsl,pins = < - MX6SLL_PAD_SD3_CMD__SD3_CMD 0x170a1 - MX6SLL_PAD_SD3_CLK__SD3_CLK 0x130a1 - MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x170a1 - MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x170a1 - MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x170a1 - MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x170a1 - MX6SLL_PAD_REF_CLK_32K__GPIO3_IO22 0x17059 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3grp_200mhz { - fsl,pins = < - MX6SLL_PAD_SD3_CMD__SD3_CMD 0x170e9 - MX6SLL_PAD_SD3_CLK__SD3_CLK 0x130f9 - MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x170e9 - MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x170e9 - MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x170e9 - MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x170e9 - MX6SLL_PAD_REF_CLK_32K__GPIO3_IO22 0x17059 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6SLL_PAD_I2C1_SCL__I2C1_SCL 0x4001b8b1 - MX6SLL_PAD_I2C1_SDA__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_lcd: lcdgrp { - fsl,pins = < - MX6SLL_PAD_LCD_DATA00__LCD_DATA00 0x79 - MX6SLL_PAD_LCD_DATA01__LCD_DATA01 0x79 - MX6SLL_PAD_LCD_DATA02__LCD_DATA02 0x79 - MX6SLL_PAD_LCD_DATA03__LCD_DATA03 0x79 - MX6SLL_PAD_LCD_DATA04__LCD_DATA04 0x79 - MX6SLL_PAD_LCD_DATA05__LCD_DATA05 0x79 - MX6SLL_PAD_LCD_DATA06__LCD_DATA06 0x79 - MX6SLL_PAD_LCD_DATA07__LCD_DATA07 0x79 - MX6SLL_PAD_LCD_DATA08__LCD_DATA08 0x79 - MX6SLL_PAD_LCD_DATA09__LCD_DATA09 0x79 - MX6SLL_PAD_LCD_DATA10__LCD_DATA10 0x79 - MX6SLL_PAD_LCD_DATA11__LCD_DATA11 0x79 - MX6SLL_PAD_LCD_DATA12__LCD_DATA12 0x79 - MX6SLL_PAD_LCD_DATA13__LCD_DATA13 0x79 - MX6SLL_PAD_LCD_DATA14__LCD_DATA14 0x79 - MX6SLL_PAD_LCD_DATA15__LCD_DATA15 0x79 - MX6SLL_PAD_LCD_DATA16__LCD_DATA16 0x79 - MX6SLL_PAD_LCD_DATA17__LCD_DATA17 0x79 - MX6SLL_PAD_LCD_DATA18__LCD_DATA18 0x79 - MX6SLL_PAD_LCD_DATA19__LCD_DATA19 0x79 - MX6SLL_PAD_LCD_DATA20__LCD_DATA20 0x79 - MX6SLL_PAD_LCD_DATA21__LCD_DATA21 0x79 - MX6SLL_PAD_LCD_DATA22__LCD_DATA22 0x79 - MX6SLL_PAD_LCD_DATA23__LCD_DATA23 0x79 - MX6SLL_PAD_LCD_CLK__LCD_CLK 0x79 - MX6SLL_PAD_LCD_ENABLE__LCD_ENABLE 0x79 - MX6SLL_PAD_LCD_HSYNC__LCD_HSYNC 0x79 - MX6SLL_PAD_LCD_VSYNC__LCD_VSYNC 0x79 - MX6SLL_PAD_LCD_RESET__LCD_RESET 0x79 - >; - }; - - pinctrl_led: ledgrp { - fsl,pins = < - MX6SLL_PAD_EPDC_VCOM1__GPIO2_IO04 0x17059 - >; - }; - - pinctrl_pwm1: pmw1grp { - fsl,pins = < - MX6SLL_PAD_PWM1__PWM1_OUT 0x110b0 - >; - }; - - pinctrl_wdog1: wdog1grp { - fsl,pins = < - MX6SLL_PAD_WDOG_B__WDOG1_B 0x170b0 - >; - }; -}; diff --git a/sys/gnu/dts/arm/imx6sll-kobo-clarahd.dts b/sys/gnu/dts/arm/imx6sll-kobo-clarahd.dts deleted file mode 100644 index 7214d1c9824..00000000000 --- a/sys/gnu/dts/arm/imx6sll-kobo-clarahd.dts +++ /dev/null @@ -1,324 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0) -/* - * Device tree for the Kobo Clara HD ebook reader - * - * Name on mainboard is: 37NB-E60K00+4A4 - * Serials start with: E60K02 (a number also seen in - * vendor kernel sources) - * - * This mainboard seems to be equipped with different SoCs. - * In the Kobo Clara HD ebook reader it is an i.MX6SLL - * - * Copyright 2019 Andreas Kemnade - * based on works - * Copyright 2016 Freescale Semiconductor, Inc. - */ - -/dts-v1/; - -#include -#include -#include "imx6sll.dtsi" -#include "e60k02.dtsi" - -/ { - model = "Kobo Clara HD"; - compatible = "kobo,clarahd", "fsl,imx6sll"; -}; - -&clks { - assigned-clocks = <&clks IMX6SLL_CLK_PLL4_AUDIO_DIV>; - assigned-clock-rates = <393216000>; -}; - -&cpu0 { - arm-supply = <&dcdc3_reg>; - soc-supply = <&dcdc1_reg>; -}; - -&gpio_keys { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_keys>; -}; - -&i2c1 { - pinctrl-names = "default","sleep"; - pinctrl-0 = <&pinctrl_i2c1>; - pinctrl-1 = <&pinctrl_i2c1_sleep>; -}; - -&i2c2 { - pinctrl-names = "default","sleep"; - pinctrl-0 = <&pinctrl_i2c2>; - pinctrl-1 = <&pinctrl_i2c2_sleep>; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_gpio_keys: gpio-keysgrp { - fsl,pins = < - MX6SLL_PAD_SD1_DATA1__GPIO5_IO08 0x17059 /* PWR_SW */ - MX6SLL_PAD_SD1_DATA4__GPIO5_IO12 0x17059 /* HALL_EN */ - >; - }; - - pinctrl_hog: hoggrp { - fsl,pins = < - MX6SLL_PAD_LCD_DATA00__GPIO2_IO20 0x79 - MX6SLL_PAD_LCD_DATA01__GPIO2_IO21 0x79 - MX6SLL_PAD_LCD_DATA02__GPIO2_IO22 0x79 - MX6SLL_PAD_LCD_DATA03__GPIO2_IO23 0x79 - MX6SLL_PAD_LCD_DATA04__GPIO2_IO24 0x79 - MX6SLL_PAD_LCD_DATA05__GPIO2_IO25 0x79 - MX6SLL_PAD_LCD_DATA06__GPIO2_IO26 0x79 - MX6SLL_PAD_LCD_DATA07__GPIO2_IO27 0x79 - MX6SLL_PAD_LCD_DATA08__GPIO2_IO28 0x79 - MX6SLL_PAD_LCD_DATA09__GPIO2_IO29 0x79 - MX6SLL_PAD_LCD_DATA10__GPIO2_IO30 0x79 - MX6SLL_PAD_LCD_DATA11__GPIO2_IO31 0x79 - MX6SLL_PAD_LCD_DATA12__GPIO3_IO00 0x79 - MX6SLL_PAD_LCD_DATA13__GPIO3_IO01 0x79 - MX6SLL_PAD_LCD_DATA14__GPIO3_IO02 0x79 - MX6SLL_PAD_LCD_DATA15__GPIO3_IO03 0x79 - MX6SLL_PAD_LCD_DATA16__GPIO3_IO04 0x79 - MX6SLL_PAD_LCD_DATA17__GPIO3_IO05 0x79 - MX6SLL_PAD_LCD_DATA18__GPIO3_IO06 0x79 - MX6SLL_PAD_LCD_DATA19__GPIO3_IO07 0x79 - MX6SLL_PAD_LCD_DATA20__GPIO3_IO08 0x79 - MX6SLL_PAD_LCD_DATA21__GPIO3_IO09 0x79 - MX6SLL_PAD_LCD_DATA22__GPIO3_IO10 0x79 - MX6SLL_PAD_LCD_DATA23__GPIO3_IO11 0x79 - MX6SLL_PAD_LCD_CLK__GPIO2_IO15 0x79 - MX6SLL_PAD_LCD_ENABLE__GPIO2_IO16 0x79 - MX6SLL_PAD_LCD_HSYNC__GPIO2_IO17 0x79 - MX6SLL_PAD_LCD_VSYNC__GPIO2_IO18 0x79 - MX6SLL_PAD_LCD_RESET__GPIO2_IO19 0x79 - MX6SLL_PAD_KEY_COL3__GPIO3_IO30 0x79 - MX6SLL_PAD_KEY_ROW7__GPIO4_IO07 0x79 - MX6SLL_PAD_ECSPI2_MOSI__GPIO4_IO13 0x79 - MX6SLL_PAD_KEY_COL5__GPIO4_IO02 0x79 - MX6SLL_PAD_KEY_ROW6__GPIO4_IO05 0x79 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6SLL_PAD_I2C1_SCL__I2C1_SCL 0x4001f8b1 - MX6SLL_PAD_I2C1_SDA__I2C1_SDA 0x4001f8b1 - >; - }; - - pinctrl_i2c1_sleep: i2c1grp-sleep { - fsl,pins = < - MX6SLL_PAD_I2C1_SCL__I2C1_SCL 0x400108b1 - MX6SLL_PAD_I2C1_SDA__I2C1_SDA 0x400108b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6SLL_PAD_I2C2_SCL__I2C2_SCL 0x4001f8b1 - MX6SLL_PAD_I2C2_SDA__I2C2_SDA 0x4001f8b1 - >; - }; - - pinctrl_i2c2_sleep: i2c2grp-sleep { - fsl,pins = < - MX6SLL_PAD_I2C2_SCL__I2C2_SCL 0x400108b1 - MX6SLL_PAD_I2C2_SDA__I2C2_SDA 0x400108b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6SLL_PAD_REF_CLK_24M__I2C3_SCL 0x4001f8b1 - MX6SLL_PAD_REF_CLK_32K__I2C3_SDA 0x4001f8b1 - >; - }; - - pinctrl_led: ledgrp { - fsl,pins = < - MX6SLL_PAD_SD1_DATA6__GPIO5_IO07 0x17059 - >; - }; - - pinctrl_lm3630a_bl_gpio: lm3630a-bl-gpiogrp { - fsl,pins = < - MX6SLL_PAD_EPDC_PWR_CTRL3__GPIO2_IO10 0x10059 /* HWEN */ - >; - }; - - pinctrl_ricoh_gpio: ricoh-gpiogrp { - fsl,pins = < - MX6SLL_PAD_SD1_CLK__GPIO5_IO15 0x1b8b1 /* ricoh619 chg */ - MX6SLL_PAD_SD1_DATA0__GPIO5_IO11 0x1b8b1 /* ricoh619 irq */ - MX6SLL_PAD_KEY_COL2__GPIO3_IO28 0x1b8b1 /* ricoh619 bat_low_int */ - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6SLL_PAD_UART1_TXD__UART1_DCE_TX 0x1b0b1 - MX6SLL_PAD_UART1_RXD__UART1_DCE_RX 0x1b0b1 - >; - }; - - pinctrl_usbotg1: usbotg1grp { - fsl,pins = < - MX6SLL_PAD_EPDC_PWR_COM__USB_OTG1_ID 0x17059 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6SLL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6SLL_PAD_SD2_CLK__SD2_CLK 0x13059 - MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x17059 - MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x17059 - MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x17059 - MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x17059 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2grp-100mhz { - fsl,pins = < - MX6SLL_PAD_SD2_CMD__SD2_CMD 0x170b9 - MX6SLL_PAD_SD2_CLK__SD2_CLK 0x130b9 - MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x170b9 - MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x170b9 - MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x170b9 - MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x170b9 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2grp-200mhz { - fsl,pins = < - MX6SLL_PAD_SD2_CMD__SD2_CMD 0x170f9 - MX6SLL_PAD_SD2_CLK__SD2_CLK 0x130f9 - MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x170f9 - MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x170f9 - MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x170f9 - MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x170f9 - >; - }; - - pinctrl_usdhc2_sleep: usdhc2grp-sleep { - fsl,pins = < - MX6SLL_PAD_SD2_CMD__GPIO5_IO04 0x100f9 - MX6SLL_PAD_SD2_CLK__GPIO5_IO05 0x100f9 - MX6SLL_PAD_SD2_DATA0__GPIO5_IO01 0x100f9 - MX6SLL_PAD_SD2_DATA1__GPIO4_IO30 0x100f9 - MX6SLL_PAD_SD2_DATA2__GPIO5_IO03 0x100f9 - MX6SLL_PAD_SD2_DATA3__GPIO4_IO28 0x100f9 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6SLL_PAD_SD3_CMD__SD3_CMD 0x11059 - MX6SLL_PAD_SD3_CLK__SD3_CLK 0x11059 - MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x11059 - MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x11059 - MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x11059 - MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x11059 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3grp-100mhz { - fsl,pins = < - MX6SLL_PAD_SD3_CMD__SD3_CMD 0x170b9 - MX6SLL_PAD_SD3_CLK__SD3_CLK 0x170b9 - MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x170b9 - MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x170b9 - MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x170b9 - MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x170b9 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3grp-200mhz { - fsl,pins = < - MX6SLL_PAD_SD3_CMD__SD3_CMD 0x170f9 - MX6SLL_PAD_SD3_CLK__SD3_CLK 0x170f9 - MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x170f9 - MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x170f9 - MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x170f9 - MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x170f9 - >; - }; - - pinctrl_usdhc3_sleep: usdhc3grp-sleep { - fsl,pins = < - MX6SLL_PAD_SD3_CMD__GPIO5_IO21 0x100c1 - MX6SLL_PAD_SD3_CLK__GPIO5_IO18 0x100c1 - MX6SLL_PAD_SD3_DATA0__GPIO5_IO19 0x100c1 - MX6SLL_PAD_SD3_DATA1__GPIO5_IO20 0x100c1 - MX6SLL_PAD_SD3_DATA2__GPIO5_IO16 0x100c1 - MX6SLL_PAD_SD3_DATA3__GPIO5_IO17 0x100c1 - >; - }; - - pinctrl_wifi_power: wifi-powergrp { - fsl,pins = < - MX6SLL_PAD_SD2_DATA6__GPIO4_IO29 0x10059 /* WIFI_3V3_ON */ - >; - }; - - pinctrl_wifi_reset: wifi-resetgrp { - fsl,pins = < - MX6SLL_PAD_SD2_DATA7__GPIO5_IO00 0x10059 /* WIFI_RST */ - >; - }; -}; - -&leds { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_led>; -}; - -&lm3630a { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lm3630a_bl_gpio>; -}; - -®_wifi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wifi_power>; -}; - -&ricoh619 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ricoh_gpio>; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; -}; - -&usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz","sleep"; - pinctrl-0 = <&pinctrl_usdhc2>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>; - pinctrl-3 = <&pinctrl_usdhc2_sleep>; -}; - -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz","sleep"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - pinctrl-3 = <&pinctrl_usdhc3_sleep>; -}; - -&wifi_pwrseq { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wifi_reset>; -}; diff --git a/sys/gnu/dts/arm/imx6sll-pinfunc.h b/sys/gnu/dts/arm/imx6sll-pinfunc.h deleted file mode 100644 index 713a346f4c8..00000000000 --- a/sys/gnu/dts/arm/imx6sll-pinfunc.h +++ /dev/null @@ -1,880 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright 2016 Freescale Semiconductor, Inc. - * Copyright 2017-2018 NXP. - * - */ - -#ifndef __DTS_IMX6SLL_PINFUNC_H -#define __DTS_IMX6SLL_PINFUNC_H - -/* - * The pin function ID is a tuple of - * - */ -#define MX6SLL_PAD_WDOG_B__WDOG1_B 0x0014 0x02DC 0x0000 0x0 0x0 -#define MX6SLL_PAD_WDOG_B__WDOG1_RESET_B_DEB 0x0014 0x02DC 0x0000 0x1 0x0 -#define MX6SLL_PAD_WDOG_B__UART5_RI_B 0x0014 0x02DC 0x0000 0x2 0x0 -#define MX6SLL_PAD_WDOG_B__GPIO3_IO18 0x0014 0x02DC 0x0000 0x5 0x0 -#define MX6SLL_PAD_REF_CLK_24M__XTALOSC_REF_CLK_24M 0x0018 0x02E0 0x0000 0x0 0x0 -#define MX6SLL_PAD_REF_CLK_24M__I2C3_SCL 0x0018 0x02E0 0x068C 0x1 0x0 -#define MX6SLL_PAD_REF_CLK_24M__PWM3_OUT 0x0018 0x02E0 0x0000 0x2 0x0 -#define MX6SLL_PAD_REF_CLK_24M__USB_OTG2_ID 0x0018 0x02E0 0x0560 0x3 0x0 -#define MX6SLL_PAD_REF_CLK_24M__CCM_PMIC_READY 0x0018 0x02E0 0x05AC 0x4 0x0 -#define MX6SLL_PAD_REF_CLK_24M__GPIO3_IO21 0x0018 0x02E0 0x0000 0x5 0x0 -#define MX6SLL_PAD_REF_CLK_24M__SD3_WP 0x0018 0x02E0 0x0794 0x6 0x0 -#define MX6SLL_PAD_REF_CLK_32K__XTALOSC_REF_CLK_32K 0x001C 0x02E4 0x0000 0x0 0x0 -#define MX6SLL_PAD_REF_CLK_32K__I2C3_SDA 0x001C 0x02E4 0x0690 0x1 0x0 -#define MX6SLL_PAD_REF_CLK_32K__PWM4_OUT 0x001C 0x02E4 0x0000 0x2 0x0 -#define MX6SLL_PAD_REF_CLK_32K__USB_OTG1_ID 0x001C 0x02E4 0x055C 0x3 0x0 -#define MX6SLL_PAD_REF_CLK_32K__SD1_LCTL 0x001C 0x02E4 0x0000 0x4 0x0 -#define MX6SLL_PAD_REF_CLK_32K__GPIO3_IO22 0x001C 0x02E4 0x0000 0x5 0x0 -#define MX6SLL_PAD_REF_CLK_32K__SD3_CD_B 0x001C 0x02E4 0x0780 0x6 0x0 -#define MX6SLL_PAD_PWM1__PWM1_OUT 0x0020 0x02E8 0x0000 0x0 0x0 -#define MX6SLL_PAD_PWM1__CCM_CLKO 0x0020 0x02E8 0x0000 0x1 0x0 -#define MX6SLL_PAD_PWM1__AUDIO_CLK_OUT 0x0020 0x02E8 0x0000 0x2 0x0 -#define MX6SLL_PAD_PWM1__CSI_MCLK 0x0020 0x02E8 0x0000 0x4 0x0 -#define MX6SLL_PAD_PWM1__GPIO3_IO23 0x0020 0x02E8 0x0000 0x5 0x0 -#define MX6SLL_PAD_PWM1__EPIT1_OUT 0x0020 0x02E8 0x0000 0x6 0x0 -#define MX6SLL_PAD_KEY_COL0__KEY_COL0 0x0024 0x02EC 0x06A0 0x0 0x0 -#define MX6SLL_PAD_KEY_COL0__I2C2_SCL 0x0024 0x02EC 0x0684 0x1 0x0 -#define MX6SLL_PAD_KEY_COL0__LCD_DATA00 0x0024 0x02EC 0x06D8 0x2 0x0 -#define MX6SLL_PAD_KEY_COL0__SD1_CD_B 0x0024 0x02EC 0x0770 0x4 0x1 -#define MX6SLL_PAD_KEY_COL0__GPIO3_IO24 0x0024 0x02EC 0x0000 0x5 0x0 -#define MX6SLL_PAD_KEY_ROW0__KEY_ROW0 0x0028 0x02F0 0x06C0 0x0 0x0 -#define MX6SLL_PAD_KEY_ROW0__I2C2_SDA 0x0028 0x02F0 0x0688 0x1 0x0 -#define MX6SLL_PAD_KEY_ROW0__LCD_DATA01 0x0028 0x02F0 0x06DC 0x2 0x0 -#define MX6SLL_PAD_KEY_ROW0__SD1_WP 0x0028 0x02F0 0x0774 0x4 0x1 -#define MX6SLL_PAD_KEY_ROW0__GPIO3_IO25 0x0028 0x02F0 0x0000 0x5 0x0 -#define MX6SLL_PAD_KEY_COL1__KEY_COL1 0x002C 0x02F4 0x06A4 0x0 0x0 -#define MX6SLL_PAD_KEY_COL1__ECSPI4_MOSI 0x002C 0x02F4 0x0658 0x1 0x1 -#define MX6SLL_PAD_KEY_COL1__LCD_DATA02 0x002C 0x02F4 0x06E0 0x2 0x0 -#define MX6SLL_PAD_KEY_COL1__SD3_DATA4 0x002C 0x02F4 0x0784 0x4 0x0 -#define MX6SLL_PAD_KEY_COL1__GPIO3_IO26 0x002C 0x02F4 0x0000 0x5 0x0 -#define MX6SLL_PAD_KEY_ROW1__KEY_ROW1 0x0030 0x02F8 0x06C4 0x0 0x0 -#define MX6SLL_PAD_KEY_ROW1__ECSPI4_MISO 0x0030 0x02F8 0x0654 0x1 0x1 -#define MX6SLL_PAD_KEY_ROW1__LCD_DATA03 0x0030 0x02F8 0x06E4 0x2 0x0 -#define MX6SLL_PAD_KEY_ROW1__CSI_FIELD 0x0030 0x02F8 0x0000 0x3 0x0 -#define MX6SLL_PAD_KEY_ROW1__SD3_DATA5 0x0030 0x02F8 0x0788 0x4 0x0 -#define MX6SLL_PAD_KEY_ROW1__GPIO3_IO27 0x0030 0x02F8 0x0000 0x5 0x0 -#define MX6SLL_PAD_KEY_COL2__KEY_COL2 0x0034 0x02FC 0x06A8 0x0 0x0 -#define MX6SLL_PAD_KEY_COL2__ECSPI4_SS0 0x0034 0x02FC 0x065C 0x1 0x1 -#define MX6SLL_PAD_KEY_COL2__LCD_DATA04 0x0034 0x02FC 0x06E8 0x2 0x0 -#define MX6SLL_PAD_KEY_COL2__CSI_DATA12 0x0034 0x02FC 0x05B8 0x3 0x1 -#define MX6SLL_PAD_KEY_COL2__SD3_DATA6 0x0034 0x02FC 0x078C 0x4 0x0 -#define MX6SLL_PAD_KEY_COL2__GPIO3_IO28 0x0034 0x02FC 0x0000 0x5 0x0 -#define MX6SLL_PAD_KEY_ROW2__KEY_ROW2 0x0038 0x0300 0x06C8 0x0 0x0 -#define MX6SLL_PAD_KEY_ROW2__ECSPI4_SCLK 0x0038 0x0300 0x0650 0x1 0x1 -#define MX6SLL_PAD_KEY_ROW2__LCD_DATA05 0x0038 0x0300 0x06EC 0x2 0x0 -#define MX6SLL_PAD_KEY_ROW2__CSI_DATA13 0x0038 0x0300 0x05BC 0x3 0x1 -#define MX6SLL_PAD_KEY_ROW2__SD3_DATA7 0x0038 0x0300 0x0790 0x4 0x0 -#define MX6SLL_PAD_KEY_ROW2__GPIO3_IO29 0x0038 0x0300 0x0000 0x5 0x0 -#define MX6SLL_PAD_KEY_COL3__KEY_COL3 0x003C 0x0304 0x06AC 0x0 0x0 -#define MX6SLL_PAD_KEY_COL3__AUD6_RXFS 0x003C 0x0304 0x05A0 0x1 0x1 -#define MX6SLL_PAD_KEY_COL3__LCD_DATA06 0x003C 0x0304 0x06F0 0x2 0x0 -#define MX6SLL_PAD_KEY_COL3__CSI_DATA14 0x003C 0x0304 0x05C0 0x3 0x1 -#define MX6SLL_PAD_KEY_COL3__GPIO3_IO30 0x003C 0x0304 0x0000 0x5 0x0 -#define MX6SLL_PAD_KEY_COL3__SD1_RESET 0x003C 0x0304 0x0000 0x6 0x0 -#define MX6SLL_PAD_KEY_ROW3__KEY_ROW3 0x0040 0x0308 0x06CC 0x0 0x1 -#define MX6SLL_PAD_KEY_ROW3__AUD6_RXC 0x0040 0x0308 0x059C 0x1 0x1 -#define MX6SLL_PAD_KEY_ROW3__LCD_DATA07 0x0040 0x0308 0x06F4 0x2 0x1 -#define MX6SLL_PAD_KEY_ROW3__CSI_DATA15 0x0040 0x0308 0x05C4 0x3 0x2 -#define MX6SLL_PAD_KEY_ROW3__GPIO3_IO31 0x0040 0x0308 0x0000 0x5 0x0 -#define MX6SLL_PAD_KEY_ROW3__SD1_VSELECT 0x0040 0x0308 0x0000 0x6 0x0 -#define MX6SLL_PAD_KEY_COL4__KEY_COL4 0x0044 0x030C 0x06B0 0x0 0x1 -#define MX6SLL_PAD_KEY_COL4__AUD6_RXD 0x0044 0x030C 0x0594 0x1 0x1 -#define MX6SLL_PAD_KEY_COL4__LCD_DATA08 0x0044 0x030C 0x06F8 0x2 0x1 -#define MX6SLL_PAD_KEY_COL4__CSI_DATA16 0x0044 0x030C 0x0000 0x3 0x0 -#define MX6SLL_PAD_KEY_COL4__GPIO4_IO00 0x0044 0x030C 0x0000 0x5 0x0 -#define MX6SLL_PAD_KEY_COL4__USB_OTG1_PWR 0x0044 0x030C 0x0000 0x6 0x0 -#define MX6SLL_PAD_KEY_ROW4__KEY_ROW4 0x0048 0x0310 0x06D0 0x0 0x1 -#define MX6SLL_PAD_KEY_ROW4__AUD6_TXC 0x0048 0x0310 0x05A4 0x1 0x1 -#define MX6SLL_PAD_KEY_ROW4__LCD_DATA09 0x0048 0x0310 0x06FC 0x2 0x1 -#define MX6SLL_PAD_KEY_ROW4__CSI_DATA17 0x0048 0x0310 0x0000 0x3 0x0 -#define MX6SLL_PAD_KEY_ROW4__GPIO4_IO01 0x0048 0x0310 0x0000 0x5 0x0 -#define MX6SLL_PAD_KEY_ROW4__USB_OTG1_OC 0x0048 0x0310 0x076C 0x6 0x2 -#define MX6SLL_PAD_KEY_COL5__KEY_COL5 0x004C 0x0314 0x0694 0x0 0x1 -#define MX6SLL_PAD_KEY_COL5__AUD6_TXFS 0x004C 0x0314 0x05A8 0x1 0x1 -#define MX6SLL_PAD_KEY_COL5__LCD_DATA10 0x004C 0x0314 0x0700 0x2 0x0 -#define MX6SLL_PAD_KEY_COL5__CSI_DATA18 0x004C 0x0314 0x0000 0x3 0x0 -#define MX6SLL_PAD_KEY_COL5__GPIO4_IO02 0x004C 0x0314 0x0000 0x5 0x0 -#define MX6SLL_PAD_KEY_COL5__USB_OTG2_PWR 0x004C 0x0314 0x0000 0x6 0x0 -#define MX6SLL_PAD_KEY_ROW5__KEY_ROW5 0x0050 0x0318 0x06B4 0x0 0x2 -#define MX6SLL_PAD_KEY_ROW5__AUD6_TXD 0x0050 0x0318 0x0598 0x1 0x1 -#define MX6SLL_PAD_KEY_ROW5__LCD_DATA11 0x0050 0x0318 0x0704 0x2 0x1 -#define MX6SLL_PAD_KEY_ROW5__CSI_DATA19 0x0050 0x0318 0x0000 0x3 0x0 -#define MX6SLL_PAD_KEY_ROW5__GPIO4_IO03 0x0050 0x0318 0x0000 0x5 0x0 -#define MX6SLL_PAD_KEY_ROW5__USB_OTG2_OC 0x0050 0x0318 0x0768 0x6 0x3 -#define MX6SLL_PAD_KEY_COL6__KEY_COL6 0x0054 0x031C 0x0698 0x0 0x2 -#define MX6SLL_PAD_KEY_COL6__UART4_DCE_RX 0x0054 0x031C 0x075C 0x1 0x2 -#define MX6SLL_PAD_KEY_COL6__UART4_DTE_TX 0x0054 0x031C 0x0000 0x1 0x0 -#define MX6SLL_PAD_KEY_COL6__LCD_DATA12 0x0054 0x031C 0x0708 0x2 0x1 -#define MX6SLL_PAD_KEY_COL6__CSI_DATA20 0x0054 0x031C 0x0000 0x3 0x0 -#define MX6SLL_PAD_KEY_COL6__GPIO4_IO04 0x0054 0x031C 0x0000 0x5 0x0 -#define MX6SLL_PAD_KEY_COL6__SD3_RESET 0x0054 0x031C 0x0000 0x6 0x0 -#define MX6SLL_PAD_KEY_ROW6__KEY_ROW6 0x0058 0x0320 0x06B8 0x0 0x2 -#define MX6SLL_PAD_KEY_ROW6__UART4_DCE_TX 0x0058 0x0320 0x0000 0x1 0x0 -#define MX6SLL_PAD_KEY_ROW6__UART4_DTE_RX 0x0058 0x0320 0x075C 0x1 0x3 -#define MX6SLL_PAD_KEY_ROW6__LCD_DATA13 0x0058 0x0320 0x070C 0x2 0x1 -#define MX6SLL_PAD_KEY_ROW6__CSI_DATA21 0x0058 0x0320 0x0000 0x3 0x0 -#define MX6SLL_PAD_KEY_ROW6__GPIO4_IO05 0x0058 0x0320 0x0000 0x5 0x0 -#define MX6SLL_PAD_KEY_ROW6__SD3_VSELECT 0x0058 0x0320 0x0000 0x6 0x0 -#define MX6SLL_PAD_KEY_COL7__KEY_COL7 0x005C 0x0324 0x069C 0x0 0x2 -#define MX6SLL_PAD_KEY_COL7__UART4_DCE_RTS 0x005C 0x0324 0x0758 0x1 0x2 -#define MX6SLL_PAD_KEY_COL7__UART4_DTE_CTS 0x005C 0x0324 0x0000 0x1 0x0 -#define MX6SLL_PAD_KEY_COL7__LCD_DATA14 0x005C 0x0324 0x0710 0x2 0x1 -#define MX6SLL_PAD_KEY_COL7__CSI_DATA22 0x005C 0x0324 0x0000 0x3 0x0 -#define MX6SLL_PAD_KEY_COL7__GPIO4_IO06 0x005C 0x0324 0x0000 0x5 0x0 -#define MX6SLL_PAD_KEY_COL7__SD1_WP 0x005C 0x0324 0x0774 0x6 0x3 -#define MX6SLL_PAD_KEY_ROW7__KEY_ROW7 0x0060 0x0328 0x06BC 0x0 0x2 -#define MX6SLL_PAD_KEY_ROW7__UART4_DCE_CTS 0x0060 0x0328 0x0000 0x1 0x0 -#define MX6SLL_PAD_KEY_ROW7__UART4_DTE_RTS 0x0060 0x0328 0x0758 0x1 0x3 -#define MX6SLL_PAD_KEY_ROW7__LCD_DATA15 0x0060 0x0328 0x0714 0x2 0x1 -#define MX6SLL_PAD_KEY_ROW7__CSI_DATA23 0x0060 0x0328 0x0000 0x3 0x0 -#define MX6SLL_PAD_KEY_ROW7__GPIO4_IO07 0x0060 0x0328 0x0000 0x5 0x0 -#define MX6SLL_PAD_KEY_ROW7__SD1_CD_B 0x0060 0x0328 0x0770 0x6 0x3 -#define MX6SLL_PAD_EPDC_DATA00__EPDC_DATA00 0x0064 0x032C 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_DATA00__ECSPI4_MOSI 0x0064 0x032C 0x0658 0x1 0x2 -#define MX6SLL_PAD_EPDC_DATA00__LCD_DATA24 0x0064 0x032C 0x0000 0x2 0x0 -#define MX6SLL_PAD_EPDC_DATA00__CSI_DATA00 0x0064 0x032C 0x05C8 0x3 0x2 -#define MX6SLL_PAD_EPDC_DATA00__GPIO1_IO07 0x0064 0x032C 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_DATA01__EPDC_DATA01 0x0068 0x0330 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_DATA01__ECSPI4_MISO 0x0068 0x0330 0x0654 0x1 0x2 -#define MX6SLL_PAD_EPDC_DATA01__LCD_DATA25 0x0068 0x0330 0x0000 0x2 0x0 -#define MX6SLL_PAD_EPDC_DATA01__CSI_DATA01 0x0068 0x0330 0x05CC 0x3 0x2 -#define MX6SLL_PAD_EPDC_DATA01__GPIO1_IO08 0x0068 0x0330 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_DATA02__EPDC_DATA02 0x006C 0x0334 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_DATA02__ECSPI4_SS0 0x006C 0x0334 0x065C 0x1 0x2 -#define MX6SLL_PAD_EPDC_DATA02__LCD_DATA26 0x006C 0x0334 0x0000 0x2 0x0 -#define MX6SLL_PAD_EPDC_DATA02__CSI_DATA02 0x006C 0x0334 0x05D0 0x3 0x2 -#define MX6SLL_PAD_EPDC_DATA02__GPIO1_IO09 0x006C 0x0334 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_DATA03__EPDC_DATA03 0x0070 0x0338 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_DATA03__ECSPI4_SCLK 0x0070 0x0338 0x0650 0x1 0x2 -#define MX6SLL_PAD_EPDC_DATA03__LCD_DATA27 0x0070 0x0338 0x0000 0x2 0x0 -#define MX6SLL_PAD_EPDC_DATA03__CSI_DATA03 0x0070 0x0338 0x05D4 0x3 0x2 -#define MX6SLL_PAD_EPDC_DATA03__GPIO1_IO10 0x0070 0x0338 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_DATA04__EPDC_DATA04 0x0074 0x033C 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_DATA04__ECSPI4_SS1 0x0074 0x033C 0x0660 0x1 0x1 -#define MX6SLL_PAD_EPDC_DATA04__LCD_DATA28 0x0074 0x033C 0x0000 0x2 0x0 -#define MX6SLL_PAD_EPDC_DATA04__CSI_DATA04 0x0074 0x033C 0x05D8 0x3 0x2 -#define MX6SLL_PAD_EPDC_DATA04__GPIO1_IO11 0x0074 0x033C 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_DATA05__EPDC_DATA05 0x0078 0x0340 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_DATA05__ECSPI4_SS2 0x0078 0x0340 0x0664 0x1 0x1 -#define MX6SLL_PAD_EPDC_DATA05__LCD_DATA29 0x0078 0x0340 0x0000 0x2 0x0 -#define MX6SLL_PAD_EPDC_DATA05__CSI_DATA05 0x0078 0x0340 0x05DC 0x3 0x2 -#define MX6SLL_PAD_EPDC_DATA05__GPIO1_IO12 0x0078 0x0340 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_DATA06__EPDC_DATA06 0x007C 0x0344 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_DATA06__ECSPI4_SS3 0x007C 0x0344 0x0000 0x1 0x0 -#define MX6SLL_PAD_EPDC_DATA06__LCD_DATA30 0x007C 0x0344 0x0000 0x2 0x0 -#define MX6SLL_PAD_EPDC_DATA06__CSI_DATA06 0x007C 0x0344 0x05E0 0x3 0x2 -#define MX6SLL_PAD_EPDC_DATA06__GPIO1_IO13 0x007C 0x0344 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_DATA07__EPDC_DATA07 0x0080 0x0348 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_DATA07__ECSPI4_RDY 0x0080 0x0348 0x0000 0x1 0x0 -#define MX6SLL_PAD_EPDC_DATA07__LCD_DATA31 0x0080 0x0348 0x0000 0x2 0x0 -#define MX6SLL_PAD_EPDC_DATA07__CSI_DATA07 0x0080 0x0348 0x05E4 0x3 0x2 -#define MX6SLL_PAD_EPDC_DATA07__GPIO1_IO14 0x0080 0x0348 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_DATA08__EPDC_DATA08 0x0084 0x034C 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_DATA08__ECSPI3_MOSI 0x0084 0x034C 0x063C 0x1 0x2 -#define MX6SLL_PAD_EPDC_DATA08__EPDC_PWR_CTRL0 0x0084 0x034C 0x0000 0x2 0x0 -#define MX6SLL_PAD_EPDC_DATA08__GPIO1_IO15 0x0084 0x034C 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_DATA09__EPDC_DATA09 0x0088 0x0350 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_DATA09__ECSPI3_MISO 0x0088 0x0350 0x0638 0x1 0x2 -#define MX6SLL_PAD_EPDC_DATA09__EPDC_PWR_CTRL1 0x0088 0x0350 0x0000 0x2 0x0 -#define MX6SLL_PAD_EPDC_DATA09__GPIO1_IO16 0x0088 0x0350 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_DATA10__EPDC_DATA10 0x008C 0x0354 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_DATA10__ECSPI3_SS0 0x008C 0x0354 0x0648 0x1 0x2 -#define MX6SLL_PAD_EPDC_DATA10__EPDC_PWR_CTRL2 0x008C 0x0354 0x0000 0x2 0x0 -#define MX6SLL_PAD_EPDC_DATA10__GPIO1_IO17 0x008C 0x0354 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_DATA11__EPDC_DATA11 0x0090 0x0358 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_DATA11__ECSPI3_SCLK 0x0090 0x0358 0x0630 0x1 0x2 -#define MX6SLL_PAD_EPDC_DATA11__EPDC_PWR_CTRL3 0x0090 0x0358 0x0000 0x2 0x0 -#define MX6SLL_PAD_EPDC_DATA11__GPIO1_IO18 0x0090 0x0358 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_DATA12__EPDC_DATA12 0x0094 0x035C 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_DATA12__UART2_DCE_RX 0x0094 0x035C 0x074C 0x1 0x4 -#define MX6SLL_PAD_EPDC_DATA12__UART2_DTE_TX 0x0094 0x035C 0x0000 0x1 0x0 -#define MX6SLL_PAD_EPDC_DATA12__EPDC_PWR_COM 0x0094 0x035C 0x0000 0x2 0x0 -#define MX6SLL_PAD_EPDC_DATA12__GPIO1_IO19 0x0094 0x035C 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_DATA12__ECSPI3_SS1 0x0094 0x035C 0x064C 0x6 0x1 -#define MX6SLL_PAD_EPDC_DATA13__EPDC_DATA13 0x0098 0x0360 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_DATA13__UART2_DCE_TX 0x0098 0x0360 0x0000 0x1 0x0 -#define MX6SLL_PAD_EPDC_DATA13__UART2_DTE_RX 0x0098 0x0360 0x074C 0x1 0x5 -#define MX6SLL_PAD_EPDC_DATA13__EPDC_PWR_IRQ 0x0098 0x0360 0x0668 0x2 0x0 -#define MX6SLL_PAD_EPDC_DATA13__GPIO1_IO20 0x0098 0x0360 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_DATA13__ECSPI3_SS2 0x0098 0x0360 0x0640 0x6 0x1 -#define MX6SLL_PAD_EPDC_DATA14__EPDC_DATA14 0x009C 0x0364 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_DATA14__UART2_DCE_RTS 0x009C 0x0364 0x0748 0x1 0x4 -#define MX6SLL_PAD_EPDC_DATA14__UART2_DTE_CTS 0x009C 0x0364 0x0000 0x1 0x0 -#define MX6SLL_PAD_EPDC_DATA14__EPDC_PWR_STAT 0x009C 0x0364 0x066C 0x2 0x0 -#define MX6SLL_PAD_EPDC_DATA14__GPIO1_IO21 0x009C 0x0364 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_DATA14__ECSPI3_SS3 0x009C 0x0364 0x0644 0x6 0x1 -#define MX6SLL_PAD_EPDC_DATA15__EPDC_DATA15 0x00A0 0x0368 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_DATA15__UART2_DCE_CTS 0x00A0 0x0368 0x0000 0x1 0x0 -#define MX6SLL_PAD_EPDC_DATA15__UART2_DTE_RTS 0x00A0 0x0368 0x0748 0x1 0x5 -#define MX6SLL_PAD_EPDC_DATA15__EPDC_PWR_WAKE 0x00A0 0x0368 0x0000 0x2 0x0 -#define MX6SLL_PAD_EPDC_DATA15__GPIO1_IO22 0x00A0 0x0368 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_DATA15__ECSPI3_RDY 0x00A0 0x0368 0x0634 0x6 0x1 -#define MX6SLL_PAD_EPDC_SDCLK__EPDC_SDCLK_P 0x00A4 0x036C 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_SDCLK__ECSPI2_MOSI 0x00A4 0x036C 0x0624 0x1 0x2 -#define MX6SLL_PAD_EPDC_SDCLK__I2C2_SCL 0x00A4 0x036C 0x0684 0x2 0x2 -#define MX6SLL_PAD_EPDC_SDCLK__CSI_DATA08 0x00A4 0x036C 0x05E8 0x3 0x2 -#define MX6SLL_PAD_EPDC_SDCLK__GPIO1_IO23 0x00A4 0x036C 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_SDLE__EPDC_SDLE 0x00A8 0x0370 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_SDLE__ECSPI2_MISO 0x00A8 0x0370 0x0620 0x1 0x2 -#define MX6SLL_PAD_EPDC_SDLE__I2C2_SDA 0x00A8 0x0370 0x0688 0x2 0x2 -#define MX6SLL_PAD_EPDC_SDLE__CSI_DATA09 0x00A8 0x0370 0x05EC 0x3 0x2 -#define MX6SLL_PAD_EPDC_SDLE__GPIO1_IO24 0x00A8 0x0370 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_SDOE__EPDC_SDOE 0x00AC 0x0374 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_SDOE__ECSPI2_SS0 0x00AC 0x0374 0x0628 0x1 0x1 -#define MX6SLL_PAD_EPDC_SDOE__CSI_DATA10 0x00AC 0x0374 0x05B0 0x3 0x2 -#define MX6SLL_PAD_EPDC_SDOE__GPIO1_IO25 0x00AC 0x0374 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_SDSHR__EPDC_SDSHR 0x00B0 0x0378 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_SDSHR__ECSPI2_SCLK 0x00B0 0x0378 0x061C 0x1 0x2 -#define MX6SLL_PAD_EPDC_SDSHR__EPDC_SDCE4 0x00B0 0x0378 0x0000 0x2 0x0 -#define MX6SLL_PAD_EPDC_SDSHR__CSI_DATA11 0x00B0 0x0378 0x05B4 0x3 0x2 -#define MX6SLL_PAD_EPDC_SDSHR__GPIO1_IO26 0x00B0 0x0378 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_SDCE0__EPDC_SDCE0 0x00B4 0x037C 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_SDCE0__ECSPI2_SS1 0x00B4 0x037C 0x062C 0x1 0x1 -#define MX6SLL_PAD_EPDC_SDCE0__PWM3_OUT 0x00B4 0x037C 0x0000 0x2 0x0 -#define MX6SLL_PAD_EPDC_SDCE0__GPIO1_IO27 0x00B4 0x037C 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_SDCE1__EPDC_SDCE1 0x00B8 0x0380 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_SDCE1__WDOG2_B 0x00B8 0x0380 0x0000 0x1 0x0 -#define MX6SLL_PAD_EPDC_SDCE1__PWM4_OUT 0x00B8 0x0380 0x0000 0x2 0x0 -#define MX6SLL_PAD_EPDC_SDCE1__GPIO1_IO28 0x00B8 0x0380 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_SDCE2__EPDC_SDCE2 0x00BC 0x0384 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_SDCE2__I2C3_SCL 0x00BC 0x0384 0x068C 0x1 0x2 -#define MX6SLL_PAD_EPDC_SDCE2__PWM1_OUT 0x00BC 0x0384 0x0000 0x2 0x0 -#define MX6SLL_PAD_EPDC_SDCE2__GPIO1_IO29 0x00BC 0x0384 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_SDCE3__EPDC_SDCE3 0x00C0 0x0388 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_SDCE3__I2C3_SDA 0x00C0 0x0388 0x0690 0x1 0x2 -#define MX6SLL_PAD_EPDC_SDCE3__PWM2_OUT 0x00C0 0x0388 0x0000 0x2 0x0 -#define MX6SLL_PAD_EPDC_SDCE3__GPIO1_IO30 0x00C0 0x0388 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_GDCLK__EPDC_GDCLK 0x00C4 0x038C 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_GDCLK__ECSPI2_SS2 0x00C4 0x038C 0x0000 0x1 0x0 -#define MX6SLL_PAD_EPDC_GDCLK__CSI_PIXCLK 0x00C4 0x038C 0x05F4 0x3 0x2 -#define MX6SLL_PAD_EPDC_GDCLK__GPIO1_IO31 0x00C4 0x038C 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_GDCLK__SD2_RESET 0x00C4 0x038C 0x0000 0x6 0x0 -#define MX6SLL_PAD_EPDC_GDOE__EPDC_GDOE 0x00C8 0x0390 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_GDOE__ECSPI2_SS3 0x00C8 0x0390 0x0000 0x1 0x0 -#define MX6SLL_PAD_EPDC_GDOE__CSI_HSYNC 0x00C8 0x0390 0x05F0 0x3 0x2 -#define MX6SLL_PAD_EPDC_GDOE__GPIO2_IO00 0x00C8 0x0390 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_GDOE__SD2_VSELECT 0x00C8 0x0390 0x0000 0x6 0x0 -#define MX6SLL_PAD_EPDC_GDRL__EPDC_GDRL 0x00CC 0x0394 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_GDRL__ECSPI2_RDY 0x00CC 0x0394 0x0000 0x1 0x0 -#define MX6SLL_PAD_EPDC_GDRL__CSI_MCLK 0x00CC 0x0394 0x0000 0x3 0x0 -#define MX6SLL_PAD_EPDC_GDRL__GPIO2_IO01 0x00CC 0x0394 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_GDRL__SD2_WP 0x00CC 0x0394 0x077C 0x6 0x2 -#define MX6SLL_PAD_EPDC_GDSP__EPDC_GDSP 0x00D0 0x0398 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_GDSP__PWM4_OUT 0x00D0 0x0398 0x0000 0x1 0x0 -#define MX6SLL_PAD_EPDC_GDSP__CSI_VSYNC 0x00D0 0x0398 0x05F8 0x3 0x2 -#define MX6SLL_PAD_EPDC_GDSP__GPIO2_IO02 0x00D0 0x0398 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_GDSP__SD2_CD_B 0x00D0 0x0398 0x0778 0x6 0x2 -#define MX6SLL_PAD_EPDC_VCOM0__EPDC_VCOM0 0x00D4 0x039C 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_VCOM0__AUD5_RXFS 0x00D4 0x039C 0x0588 0x1 0x1 -#define MX6SLL_PAD_EPDC_VCOM0__UART3_DCE_RX 0x00D4 0x039C 0x0754 0x2 0x4 -#define MX6SLL_PAD_EPDC_VCOM0__UART3_DTE_TX 0x00D4 0x039C 0x0000 0x2 0x0 -#define MX6SLL_PAD_EPDC_VCOM0__GPIO2_IO03 0x00D4 0x039C 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_VCOM0__EPDC_SDCE5 0x00D4 0x039C 0x0000 0x6 0x0 -#define MX6SLL_PAD_EPDC_VCOM1__EPDC_VCOM1 0x00D8 0x03A0 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_VCOM1__AUD5_RXD 0x00D8 0x03A0 0x057C 0x1 0x1 -#define MX6SLL_PAD_EPDC_VCOM1__UART3_DCE_TX 0x00D8 0x03A0 0x0000 0x2 0x0 -#define MX6SLL_PAD_EPDC_VCOM1__UART3_DTE_RX 0x00D8 0x03A0 0x0754 0x2 0x5 -#define MX6SLL_PAD_EPDC_VCOM1__GPIO2_IO04 0x00D8 0x03A0 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_VCOM1__EPDC_SDCE6 0x00D8 0x03A0 0x0000 0x6 0x0 -#define MX6SLL_PAD_EPDC_BDR0__EPDC_BDR0 0x00DC 0x03A4 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_BDR0__UART3_DCE_RTS 0x00DC 0x03A4 0x0750 0x2 0x2 -#define MX6SLL_PAD_EPDC_BDR0__UART3_DTE_CTS 0x00DC 0x03A4 0x0000 0x2 0x0 -#define MX6SLL_PAD_EPDC_BDR0__GPIO2_IO05 0x00DC 0x03A4 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_BDR0__EPDC_SDCE7 0x00DC 0x03A4 0x0000 0x6 0x0 -#define MX6SLL_PAD_EPDC_BDR1__EPDC_BDR1 0x00E0 0x03A8 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_BDR1__UART3_DCE_CTS 0x00E0 0x03A8 0x0000 0x2 0x0 -#define MX6SLL_PAD_EPDC_BDR1__UART3_DTE_RTS 0x00E0 0x03A8 0x0750 0x2 0x3 -#define MX6SLL_PAD_EPDC_BDR1__GPIO2_IO06 0x00E0 0x03A8 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_BDR1__EPDC_SDCE8 0x00E0 0x03A8 0x0000 0x6 0x0 -#define MX6SLL_PAD_EPDC_PWR_CTRL0__EPDC_PWR_CTRL0 0x00E4 0x03AC 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_PWR_CTRL0__AUD5_RXC 0x00E4 0x03AC 0x0584 0x1 0x1 -#define MX6SLL_PAD_EPDC_PWR_CTRL0__LCD_DATA16 0x00E4 0x03AC 0x0718 0x2 0x1 -#define MX6SLL_PAD_EPDC_PWR_CTRL0__GPIO2_IO07 0x00E4 0x03AC 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_PWR_CTRL1__EPDC_PWR_CTRL1 0x00E8 0x03B0 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_PWR_CTRL1__AUD5_TXFS 0x00E8 0x03B0 0x0590 0x1 0x1 -#define MX6SLL_PAD_EPDC_PWR_CTRL1__LCD_DATA17 0x00E8 0x03B0 0x071C 0x2 0x1 -#define MX6SLL_PAD_EPDC_PWR_CTRL1__GPIO2_IO08 0x00E8 0x03B0 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_PWR_CTRL2__EPDC_PWR_CTRL2 0x00EC 0x03B4 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_PWR_CTRL2__AUD5_TXD 0x00EC 0x03B4 0x0580 0x1 0x1 -#define MX6SLL_PAD_EPDC_PWR_CTRL2__LCD_DATA18 0x00EC 0x03B4 0x0720 0x2 0x1 -#define MX6SLL_PAD_EPDC_PWR_CTRL2__GPIO2_IO09 0x00EC 0x03B4 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_PWR_CTRL3__EPDC_PWR_CTRL3 0x00F0 0x03B8 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_PWR_CTRL3__AUD5_TXC 0x00F0 0x03B8 0x058C 0x1 0x1 -#define MX6SLL_PAD_EPDC_PWR_CTRL3__LCD_DATA19 0x00F0 0x03B8 0x0724 0x2 0x1 -#define MX6SLL_PAD_EPDC_PWR_CTRL3__GPIO2_IO10 0x00F0 0x03B8 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_PWR_COM__EPDC_PWR_COM 0x00F4 0x03BC 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_PWR_COM__LCD_DATA20 0x00F4 0x03BC 0x0728 0x2 0x1 -#define MX6SLL_PAD_EPDC_PWR_COM__USB_OTG1_ID 0x00F4 0x03BC 0x055C 0x4 0x4 -#define MX6SLL_PAD_EPDC_PWR_COM__GPIO2_IO11 0x00F4 0x03BC 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_PWR_COM__SD3_RESET 0x00F4 0x03BC 0x0000 0x6 0x0 -#define MX6SLL_PAD_EPDC_PWR_IRQ__EPDC_PWR_IRQ 0x00F8 0x03C0 0x0668 0x0 0x1 -#define MX6SLL_PAD_EPDC_PWR_IRQ__LCD_DATA21 0x00F8 0x03C0 0x072C 0x2 0x1 -#define MX6SLL_PAD_EPDC_PWR_IRQ__USB_OTG2_ID 0x00F8 0x03C0 0x0560 0x4 0x3 -#define MX6SLL_PAD_EPDC_PWR_IRQ__GPIO2_IO12 0x00F8 0x03C0 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_PWR_IRQ__SD3_VSELECT 0x00F8 0x03C0 0x0000 0x6 0x0 -#define MX6SLL_PAD_EPDC_PWR_STAT__EPDC_PWR_STAT 0x00FC 0x03C4 0x066C 0x0 0x1 -#define MX6SLL_PAD_EPDC_PWR_STAT__LCD_DATA22 0x00FC 0x03C4 0x0730 0x2 0x1 -#define MX6SLL_PAD_EPDC_PWR_STAT__ARM_EVENTI 0x00FC 0x03C4 0x0000 0x4 0x0 -#define MX6SLL_PAD_EPDC_PWR_STAT__GPIO2_IO13 0x00FC 0x03C4 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_PWR_STAT__SD3_WP 0x00FC 0x03C4 0x0794 0x6 0x2 -#define MX6SLL_PAD_EPDC_PWR_WAKE__EPDC_PWR_WAKE 0x0100 0x03C8 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_PWR_WAKE__LCD_DATA23 0x0100 0x03C8 0x0734 0x2 0x1 -#define MX6SLL_PAD_EPDC_PWR_WAKE__ARM_EVENTO 0x0100 0x03C8 0x0000 0x4 0x0 -#define MX6SLL_PAD_EPDC_PWR_WAKE__GPIO2_IO14 0x0100 0x03C8 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_PWR_WAKE__SD3_CD_B 0x0100 0x03C8 0x0780 0x6 0x2 -#define MX6SLL_PAD_LCD_CLK__LCD_CLK 0x0104 0x03CC 0x0000 0x0 0x0 -#define MX6SLL_PAD_LCD_CLK__LCD_WR_RWN 0x0104 0x03CC 0x0000 0x2 0x0 -#define MX6SLL_PAD_LCD_CLK__PWM4_OUT 0x0104 0x03CC 0x0000 0x4 0x0 -#define MX6SLL_PAD_LCD_CLK__GPIO2_IO15 0x0104 0x03CC 0x0000 0x5 0x0 -#define MX6SLL_PAD_LCD_ENABLE__LCD_ENABLE 0x0108 0x03D0 0x0000 0x0 0x0 -#define MX6SLL_PAD_LCD_ENABLE__LCD_RD_E 0x0108 0x03D0 0x0000 0x2 0x0 -#define MX6SLL_PAD_LCD_ENABLE__UART2_DCE_RX 0x0108 0x03D0 0x0000 0x4 0x0 -#define MX6SLL_PAD_LCD_ENABLE__UART2_DTE_TX 0x0108 0x03D0 0x0000 0x4 0x0 -#define MX6SLL_PAD_LCD_ENABLE__GPIO2_IO16 0x0108 0x03D0 0x0000 0x5 0x0 -#define MX6SLL_PAD_LCD_HSYNC__LCD_HSYNC 0x010C 0x03D4 0x06D4 0x0 0x0 -#define MX6SLL_PAD_LCD_HSYNC__LCD_CS 0x010C 0x03D4 0x0000 0x2 0x0 -#define MX6SLL_PAD_LCD_HSYNC__UART2_DCE_TX 0x010C 0x03D4 0x0000 0x4 0x0 -#define MX6SLL_PAD_LCD_HSYNC__UART2_DTE_RX 0x010C 0x03D4 0x074C 0x4 0x1 -#define MX6SLL_PAD_LCD_HSYNC__GPIO2_IO17 0x010C 0x03D4 0x0000 0x5 0x0 -#define MX6SLL_PAD_LCD_HSYNC__ARM_TRACE_CLK 0x010C 0x03D4 0x0000 0x6 0x0 -#define MX6SLL_PAD_LCD_VSYNC__LCD_VSYNC 0x0110 0x03D8 0x0000 0x0 0x0 -#define MX6SLL_PAD_LCD_VSYNC__LCD_RS 0x0110 0x03D8 0x0000 0x2 0x0 -#define MX6SLL_PAD_LCD_VSYNC__UART2_DCE_RTS 0x0110 0x03D8 0x0748 0x4 0x0 -#define MX6SLL_PAD_LCD_VSYNC__UART2_DTE_CTS 0x0110 0x03D8 0x0000 0x4 0x0 -#define MX6SLL_PAD_LCD_VSYNC__GPIO2_IO18 0x0110 0x03D8 0x0000 0x5 0x0 -#define MX6SLL_PAD_LCD_VSYNC__ARM_TRACE_CTL 0x0110 0x03D8 0x0000 0x6 0x0 -#define MX6SLL_PAD_LCD_RESET__LCD_RESET 0x0114 0x03DC 0x0000 0x0 0x0 -#define MX6SLL_PAD_LCD_RESET__LCD_BUSY 0x0114 0x03DC 0x06D4 0x2 0x1 -#define MX6SLL_PAD_LCD_RESET__UART2_DCE_CTS 0x0114 0x03DC 0x0000 0x4 0x0 -#define MX6SLL_PAD_LCD_RESET__UART2_DTE_RTS 0x0114 0x03DC 0x0748 0x4 0x1 -#define MX6SLL_PAD_LCD_RESET__GPIO2_IO19 0x0114 0x03DC 0x0000 0x5 0x0 -#define MX6SLL_PAD_LCD_RESET__CCM_PMIC_READY 0x0114 0x03DC 0x05AC 0x6 0x2 -#define MX6SLL_PAD_LCD_DATA00__LCD_DATA00 0x0118 0x03E0 0x06D8 0x0 0x1 -#define MX6SLL_PAD_LCD_DATA00__ECSPI1_MOSI 0x0118 0x03E0 0x0608 0x1 0x0 -#define MX6SLL_PAD_LCD_DATA00__USB_OTG2_ID 0x0118 0x03E0 0x0560 0x2 0x2 -#define MX6SLL_PAD_LCD_DATA00__PWM1_OUT 0x0118 0x03E0 0x0000 0x3 0x0 -#define MX6SLL_PAD_LCD_DATA00__UART5_DTR_B 0x0118 0x03E0 0x0000 0x4 0x0 -#define MX6SLL_PAD_LCD_DATA00__GPIO2_IO20 0x0118 0x03E0 0x0000 0x5 0x0 -#define MX6SLL_PAD_LCD_DATA00__ARM_TRACE00 0x0118 0x03E0 0x0000 0x6 0x0 -#define MX6SLL_PAD_LCD_DATA00__SRC_BOOT_CFG00 0x0118 0x03E0 0x0000 0x7 0x0 -#define MX6SLL_PAD_LCD_DATA01__LCD_DATA01 0x011C 0x03E4 0x06DC 0x0 0x1 -#define MX6SLL_PAD_LCD_DATA01__ECSPI1_MISO 0x011C 0x03E4 0x0604 0x1 0x0 -#define MX6SLL_PAD_LCD_DATA01__USB_OTG1_ID 0x011C 0x03E4 0x055C 0x2 0x3 -#define MX6SLL_PAD_LCD_DATA01__PWM2_OUT 0x011C 0x03E4 0x0000 0x3 0x0 -#define MX6SLL_PAD_LCD_DATA01__AUD4_RXFS 0x011C 0x03E4 0x0570 0x4 0x0 -#define MX6SLL_PAD_LCD_DATA01__GPIO2_IO21 0x011C 0x03E4 0x0000 0x5 0x0 -#define MX6SLL_PAD_LCD_DATA01__ARM_TRACE01 0x011C 0x03E4 0x0000 0x6 0x0 -#define MX6SLL_PAD_LCD_DATA01__SRC_BOOT_CFG01 0x011C 0x03E4 0x0000 0x7 0x0 -#define MX6SLL_PAD_LCD_DATA02__LCD_DATA02 0x0120 0x03E8 0x06E0 0x0 0x1 -#define MX6SLL_PAD_LCD_DATA02__ECSPI1_SS0 0x0120 0x03E8 0x0614 0x1 0x0 -#define MX6SLL_PAD_LCD_DATA02__EPIT2_OUT 0x0120 0x03E8 0x0000 0x2 0x0 -#define MX6SLL_PAD_LCD_DATA02__PWM3_OUT 0x0120 0x03E8 0x0000 0x3 0x0 -#define MX6SLL_PAD_LCD_DATA02__AUD4_RXC 0x0120 0x03E8 0x056C 0x4 0x0 -#define MX6SLL_PAD_LCD_DATA02__GPIO2_IO22 0x0120 0x03E8 0x0000 0x5 0x0 -#define MX6SLL_PAD_LCD_DATA02__ARM_TRACE02 0x0120 0x03E8 0x0000 0x6 0x0 -#define MX6SLL_PAD_LCD_DATA02__SRC_BOOT_CFG02 0x0120 0x03E8 0x0000 0x7 0x0 -#define MX6SLL_PAD_LCD_DATA03__LCD_DATA03 0x0124 0x03EC 0x06E4 0x0 0x1 -#define MX6SLL_PAD_LCD_DATA03__ECSPI1_SCLK 0x0124 0x03EC 0x05FC 0x1 0x0 -#define MX6SLL_PAD_LCD_DATA03__UART5_DSR_B 0x0124 0x03EC 0x0000 0x2 0x0 -#define MX6SLL_PAD_LCD_DATA03__PWM4_OUT 0x0124 0x03EC 0x0000 0x3 0x0 -#define MX6SLL_PAD_LCD_DATA03__AUD4_RXD 0x0124 0x03EC 0x0564 0x4 0x0 -#define MX6SLL_PAD_LCD_DATA03__GPIO2_IO23 0x0124 0x03EC 0x0000 0x5 0x0 -#define MX6SLL_PAD_LCD_DATA03__ARM_TRACE03 0x0124 0x03EC 0x0000 0x6 0x0 -#define MX6SLL_PAD_LCD_DATA03__SRC_BOOT_CFG03 0x0124 0x03EC 0x0000 0x7 0x0 -#define MX6SLL_PAD_LCD_DATA04__LCD_DATA04 0x0128 0x03F0 0x06E8 0x0 0x1 -#define MX6SLL_PAD_LCD_DATA04__ECSPI1_SS1 0x0128 0x03F0 0x060C 0x1 0x1 -#define MX6SLL_PAD_LCD_DATA04__CSI_VSYNC 0x0128 0x03F0 0x05F8 0x2 0x0 -#define MX6SLL_PAD_LCD_DATA04__WDOG2_RESET_B_DEB 0x0128 0x03F0 0x0000 0x3 0x0 -#define MX6SLL_PAD_LCD_DATA04__AUD4_TXC 0x0128 0x03F0 0x0574 0x4 0x0 -#define MX6SLL_PAD_LCD_DATA04__GPIO2_IO24 0x0128 0x03F0 0x0000 0x5 0x0 -#define MX6SLL_PAD_LCD_DATA04__ARM_TRACE04 0x0128 0x03F0 0x0000 0x6 0x0 -#define MX6SLL_PAD_LCD_DATA04__SRC_BOOT_CFG04 0x0128 0x03F0 0x0000 0x7 0x0 -#define MX6SLL_PAD_LCD_DATA05__LCD_DATA05 0x012C 0x03F4 0x06EC 0x0 0x1 -#define MX6SLL_PAD_LCD_DATA05__ECSPI1_SS2 0x012C 0x03F4 0x0610 0x1 0x1 -#define MX6SLL_PAD_LCD_DATA05__CSI_HSYNC 0x012C 0x03F4 0x05F0 0x2 0x0 -#define MX6SLL_PAD_LCD_DATA05__AUD4_TXFS 0x012C 0x03F4 0x0578 0x4 0x0 -#define MX6SLL_PAD_LCD_DATA05__GPIO2_IO25 0x012C 0x03F4 0x0000 0x5 0x0 -#define MX6SLL_PAD_LCD_DATA05__ARM_TRACE05 0x012C 0x03F4 0x0000 0x6 0x0 -#define MX6SLL_PAD_LCD_DATA05__SRC_BOOT_CFG05 0x012C 0x03F4 0x0000 0x7 0x0 -#define MX6SLL_PAD_LCD_DATA06__LCD_DATA06 0x0130 0x03F8 0x06F0 0x0 0x1 -#define MX6SLL_PAD_LCD_DATA06__ECSPI1_SS3 0x0130 0x03F8 0x0618 0x1 0x0 -#define MX6SLL_PAD_LCD_DATA06__CSI_PIXCLK 0x0130 0x03F8 0x05F4 0x2 0x0 -#define MX6SLL_PAD_LCD_DATA06__AUD4_TXD 0x0130 0x03F8 0x0568 0x4 0x0 -#define MX6SLL_PAD_LCD_DATA06__GPIO2_IO26 0x0130 0x03F8 0x0000 0x5 0x0 -#define MX6SLL_PAD_LCD_DATA06__ARM_TRACE06 0x0130 0x03F8 0x0000 0x6 0x0 -#define MX6SLL_PAD_LCD_DATA06__SRC_BOOT_CFG06 0x0130 0x03F8 0x0000 0x7 0x0 -#define MX6SLL_PAD_LCD_DATA07__LCD_DATA07 0x0134 0x03FC 0x06F4 0x0 0x0 -#define MX6SLL_PAD_LCD_DATA07__ECSPI1_RDY 0x0134 0x03FC 0x0600 0x1 0x0 -#define MX6SLL_PAD_LCD_DATA07__CSI_MCLK 0x0134 0x03FC 0x0000 0x2 0x0 -#define MX6SLL_PAD_LCD_DATA07__AUDIO_CLK_OUT 0x0134 0x03FC 0x0000 0x4 0x0 -#define MX6SLL_PAD_LCD_DATA07__GPIO2_IO27 0x0134 0x03FC 0x0000 0x5 0x0 -#define MX6SLL_PAD_LCD_DATA07__ARM_TRACE07 0x0134 0x03FC 0x0000 0x6 0x0 -#define MX6SLL_PAD_LCD_DATA07__SRC_BOOT_CFG07 0x0134 0x03FC 0x0000 0x7 0x0 -#define MX6SLL_PAD_LCD_DATA08__LCD_DATA08 0x0138 0x0400 0x06F8 0x0 0x0 -#define MX6SLL_PAD_LCD_DATA08__KEY_COL0 0x0138 0x0400 0x06A0 0x1 0x1 -#define MX6SLL_PAD_LCD_DATA08__CSI_DATA09 0x0138 0x0400 0x05EC 0x2 0x0 -#define MX6SLL_PAD_LCD_DATA08__ECSPI2_SCLK 0x0138 0x0400 0x061C 0x4 0x0 -#define MX6SLL_PAD_LCD_DATA08__GPIO2_IO28 0x0138 0x0400 0x0000 0x5 0x0 -#define MX6SLL_PAD_LCD_DATA08__ARM_TRACE08 0x0138 0x0400 0x0000 0x6 0x0 -#define MX6SLL_PAD_LCD_DATA08__SRC_BOOT_CFG08 0x0138 0x0400 0x0000 0x7 0x0 -#define MX6SLL_PAD_LCD_DATA09__LCD_DATA09 0x013C 0x0404 0x06FC 0x0 0x0 -#define MX6SLL_PAD_LCD_DATA09__KEY_ROW0 0x013C 0x0404 0x06C0 0x1 0x1 -#define MX6SLL_PAD_LCD_DATA09__CSI_DATA08 0x013C 0x0404 0x05E8 0x2 0x0 -#define MX6SLL_PAD_LCD_DATA09__ECSPI2_MOSI 0x013C 0x0404 0x0624 0x4 0x0 -#define MX6SLL_PAD_LCD_DATA09__GPIO2_IO29 0x013C 0x0404 0x0000 0x5 0x0 -#define MX6SLL_PAD_LCD_DATA09__ARM_TRACE09 0x013C 0x0404 0x0000 0x6 0x0 -#define MX6SLL_PAD_LCD_DATA09__SRC_BOOT_CFG09 0x013C 0x0404 0x0000 0x7 0x0 -#define MX6SLL_PAD_LCD_DATA10__LCD_DATA10 0x0140 0x0408 0x0700 0x0 0x1 -#define MX6SLL_PAD_LCD_DATA10__KEY_COL1 0x0140 0x0408 0x06A4 0x1 0x1 -#define MX6SLL_PAD_LCD_DATA10__CSI_DATA07 0x0140 0x0408 0x05E4 0x2 0x0 -#define MX6SLL_PAD_LCD_DATA10__ECSPI2_MISO 0x0140 0x0408 0x0620 0x4 0x0 -#define MX6SLL_PAD_LCD_DATA10__GPIO2_IO30 0x0140 0x0408 0x0000 0x5 0x0 -#define MX6SLL_PAD_LCD_DATA10__ARM_TRACE10 0x0140 0x0408 0x0000 0x6 0x0 -#define MX6SLL_PAD_LCD_DATA10__SRC_BOOT_CFG10 0x0140 0x0408 0x0000 0x7 0x0 -#define MX6SLL_PAD_LCD_DATA11__LCD_DATA11 0x0144 0x040C 0x0704 0x0 0x0 -#define MX6SLL_PAD_LCD_DATA11__KEY_ROW1 0x0144 0x040C 0x06C4 0x1 0x1 -#define MX6SLL_PAD_LCD_DATA11__CSI_DATA06 0x0144 0x040C 0x05E0 0x2 0x0 -#define MX6SLL_PAD_LCD_DATA11__ECSPI2_SS1 0x0144 0x040C 0x062C 0x4 0x0 -#define MX6SLL_PAD_LCD_DATA11__GPIO2_IO31 0x0144 0x040C 0x0000 0x5 0x0 -#define MX6SLL_PAD_LCD_DATA11__ARM_TRACE11 0x0144 0x040C 0x0000 0x6 0x0 -#define MX6SLL_PAD_LCD_DATA11__SRC_BOOT_CFG11 0x0144 0x040C 0x0000 0x7 0x0 -#define MX6SLL_PAD_LCD_DATA12__LCD_DATA12 0x0148 0x0410 0x0708 0x0 0x0 -#define MX6SLL_PAD_LCD_DATA12__KEY_COL2 0x0148 0x0410 0x06A8 0x1 0x1 -#define MX6SLL_PAD_LCD_DATA12__CSI_DATA05 0x0148 0x0410 0x05DC 0x2 0x0 -#define MX6SLL_PAD_LCD_DATA12__UART5_DCE_RTS 0x0148 0x0410 0x0760 0x4 0x0 -#define MX6SLL_PAD_LCD_DATA12__UART5_DTE_CTS 0x0148 0x0410 0x0000 0x4 0x0 -#define MX6SLL_PAD_LCD_DATA12__GPIO3_IO00 0x0148 0x0410 0x0000 0x5 0x0 -#define MX6SLL_PAD_LCD_DATA12__ARM_TRACE12 0x0148 0x0410 0x0000 0x6 0x0 -#define MX6SLL_PAD_LCD_DATA12__SRC_BOOT_CFG12 0x0148 0x0410 0x0000 0x7 0x0 -#define MX6SLL_PAD_LCD_DATA13__LCD_DATA13 0x014C 0x0414 0x070C 0x0 0x0 -#define MX6SLL_PAD_LCD_DATA13__KEY_ROW2 0x014C 0x0414 0x06C8 0x1 0x1 -#define MX6SLL_PAD_LCD_DATA13__CSI_DATA04 0x014C 0x0414 0x05D8 0x2 0x0 -#define MX6SLL_PAD_LCD_DATA13__UART5_DCE_CTS 0x014C 0x0414 0x0000 0x4 0x0 -#define MX6SLL_PAD_LCD_DATA13__UART5_DTE_RTS 0x014C 0x0414 0x0760 0x4 0x1 -#define MX6SLL_PAD_LCD_DATA13__GPIO3_IO01 0x014C 0x0414 0x0000 0x5 0x0 -#define MX6SLL_PAD_LCD_DATA13__ARM_TRACE13 0x014C 0x0414 0x0000 0x6 0x0 -#define MX6SLL_PAD_LCD_DATA13__SRC_BOOT_CFG13 0x014C 0x0414 0x0000 0x7 0x0 -#define MX6SLL_PAD_LCD_DATA14__LCD_DATA14 0x0150 0x0418 0x0710 0x0 0x0 -#define MX6SLL_PAD_LCD_DATA14__KEY_COL3 0x0150 0x0418 0x06AC 0x1 0x1 -#define MX6SLL_PAD_LCD_DATA14__CSI_DATA03 0x0150 0x0418 0x05D4 0x2 0x0 -#define MX6SLL_PAD_LCD_DATA14__UART5_DCE_RX 0x0150 0x0418 0x0764 0x4 0x0 -#define MX6SLL_PAD_LCD_DATA14__UART5_DTE_TX 0x0150 0x0418 0x0000 0x4 0x0 -#define MX6SLL_PAD_LCD_DATA14__GPIO3_IO02 0x0150 0x0418 0x0000 0x5 0x0 -#define MX6SLL_PAD_LCD_DATA14__ARM_TRACE14 0x0150 0x0418 0x0000 0x6 0x0 -#define MX6SLL_PAD_LCD_DATA14__SRC_BOOT_CFG14 0x0150 0x0418 0x0000 0x7 0x0 -#define MX6SLL_PAD_LCD_DATA15__LCD_DATA15 0x0154 0x041C 0x0714 0x0 0x0 -#define MX6SLL_PAD_LCD_DATA15__KEY_ROW3 0x0154 0x041C 0x06CC 0x1 0x0 -#define MX6SLL_PAD_LCD_DATA15__CSI_DATA02 0x0154 0x041C 0x05D0 0x2 0x0 -#define MX6SLL_PAD_LCD_DATA15__UART5_DCE_TX 0x0154 0x041C 0x0000 0x4 0x0 -#define MX6SLL_PAD_LCD_DATA15__UART5_DTE_RX 0x0154 0x041C 0x0764 0x4 0x1 -#define MX6SLL_PAD_LCD_DATA15__GPIO3_IO03 0x0154 0x041C 0x0000 0x5 0x0 -#define MX6SLL_PAD_LCD_DATA15__ARM_TRACE15 0x0154 0x041C 0x0000 0x6 0x0 -#define MX6SLL_PAD_LCD_DATA15__SRC_BOOT_CFG15 0x0154 0x041C 0x0000 0x7 0x0 -#define MX6SLL_PAD_LCD_DATA16__LCD_DATA16 0x0158 0x0420 0x0718 0x0 0x0 -#define MX6SLL_PAD_LCD_DATA16__KEY_COL4 0x0158 0x0420 0x06B0 0x1 0x0 -#define MX6SLL_PAD_LCD_DATA16__CSI_DATA01 0x0158 0x0420 0x05CC 0x2 0x0 -#define MX6SLL_PAD_LCD_DATA16__I2C2_SCL 0x0158 0x0420 0x0684 0x4 0x1 -#define MX6SLL_PAD_LCD_DATA16__GPIO3_IO04 0x0158 0x0420 0x0000 0x5 0x0 -#define MX6SLL_PAD_LCD_DATA16__SRC_BOOT_CFG24 0x0158 0x0420 0x0000 0x7 0x0 -#define MX6SLL_PAD_LCD_DATA17__LCD_DATA17 0x015C 0x0424 0x071C 0x0 0x0 -#define MX6SLL_PAD_LCD_DATA17__KEY_ROW4 0x015C 0x0424 0x06D0 0x1 0x0 -#define MX6SLL_PAD_LCD_DATA17__CSI_DATA00 0x015C 0x0424 0x05C8 0x2 0x0 -#define MX6SLL_PAD_LCD_DATA17__I2C2_SDA 0x015C 0x0424 0x0688 0x4 0x1 -#define MX6SLL_PAD_LCD_DATA17__GPIO3_IO05 0x015C 0x0424 0x0000 0x5 0x0 -#define MX6SLL_PAD_LCD_DATA17__SRC_BOOT_CFG25 0x015C 0x0424 0x0000 0x7 0x0 -#define MX6SLL_PAD_LCD_DATA18__LCD_DATA18 0x0160 0x0428 0x0720 0x0 0x0 -#define MX6SLL_PAD_LCD_DATA18__KEY_COL5 0x0160 0x0428 0x0694 0x1 0x2 -#define MX6SLL_PAD_LCD_DATA18__CSI_DATA15 0x0160 0x0428 0x05C4 0x2 0x1 -#define MX6SLL_PAD_LCD_DATA18__GPT_CAPTURE1 0x0160 0x0428 0x0670 0x4 0x1 -#define MX6SLL_PAD_LCD_DATA18__GPIO3_IO06 0x0160 0x0428 0x0000 0x5 0x0 -#define MX6SLL_PAD_LCD_DATA18__SRC_BOOT_CFG26 0x0160 0x0428 0x0000 0x7 0x0 -#define MX6SLL_PAD_LCD_DATA19__LCD_DATA19 0x0164 0x042C 0x0724 0x0 0x0 -#define MX6SLL_PAD_LCD_DATA19__KEY_ROW5 0x0164 0x042C 0x06B4 0x1 0x1 -#define MX6SLL_PAD_LCD_DATA19__CSI_DATA14 0x0164 0x042C 0x05C0 0x2 0x2 -#define MX6SLL_PAD_LCD_DATA19__GPT_CAPTURE2 0x0164 0x042C 0x0674 0x4 0x1 -#define MX6SLL_PAD_LCD_DATA19__GPIO3_IO07 0x0164 0x042C 0x0000 0x5 0x0 -#define MX6SLL_PAD_LCD_DATA19__SRC_BOOT_CFG27 0x0164 0x042C 0x0000 0x7 0x0 -#define MX6SLL_PAD_LCD_DATA20__LCD_DATA20 0x0168 0x0430 0x0728 0x0 0x0 -#define MX6SLL_PAD_LCD_DATA20__KEY_COL6 0x0168 0x0430 0x0698 0x1 0x1 -#define MX6SLL_PAD_LCD_DATA20__CSI_DATA13 0x0168 0x0430 0x05BC 0x2 0x2 -#define MX6SLL_PAD_LCD_DATA20__GPT_COMPARE1 0x0168 0x0430 0x0000 0x4 0x0 -#define MX6SLL_PAD_LCD_DATA20__GPIO3_IO08 0x0168 0x0430 0x0000 0x5 0x0 -#define MX6SLL_PAD_LCD_DATA20__SRC_BOOT_CFG28 0x0168 0x0430 0x0000 0x7 0x0 -#define MX6SLL_PAD_LCD_DATA21__LCD_DATA21 0x016C 0x0434 0x072C 0x0 0x0 -#define MX6SLL_PAD_LCD_DATA21__KEY_ROW6 0x016C 0x0434 0x06B8 0x1 0x1 -#define MX6SLL_PAD_LCD_DATA21__CSI_DATA12 0x016C 0x0434 0x05B8 0x2 0x2 -#define MX6SLL_PAD_LCD_DATA21__GPT_COMPARE2 0x016C 0x0434 0x0000 0x4 0x0 -#define MX6SLL_PAD_LCD_DATA21__GPIO3_IO09 0x016C 0x0434 0x0000 0x5 0x0 -#define MX6SLL_PAD_LCD_DATA21__SRC_BOOT_CFG29 0x016C 0x0434 0x0000 0x7 0x0 -#define MX6SLL_PAD_LCD_DATA22__LCD_DATA22 0x0170 0x0438 0x0730 0x0 0x0 -#define MX6SLL_PAD_LCD_DATA22__KEY_COL7 0x0170 0x0438 0x069C 0x1 0x1 -#define MX6SLL_PAD_LCD_DATA22__CSI_DATA11 0x0170 0x0438 0x05B4 0x2 0x1 -#define MX6SLL_PAD_LCD_DATA22__GPT_COMPARE3 0x0170 0x0438 0x0000 0x4 0x0 -#define MX6SLL_PAD_LCD_DATA22__GPIO3_IO10 0x0170 0x0438 0x0000 0x5 0x0 -#define MX6SLL_PAD_LCD_DATA22__SRC_BOOT_CFG30 0x0170 0x0438 0x0000 0x7 0x0 -#define MX6SLL_PAD_LCD_DATA23__LCD_DATA23 0x0174 0x043C 0x0734 0x0 0x0 -#define MX6SLL_PAD_LCD_DATA23__KEY_ROW7 0x0174 0x043C 0x06BC 0x1 0x1 -#define MX6SLL_PAD_LCD_DATA23__CSI_DATA10 0x0174 0x043C 0x05B0 0x2 0x1 -#define MX6SLL_PAD_LCD_DATA23__GPT_CLKIN 0x0174 0x043C 0x0678 0x4 0x1 -#define MX6SLL_PAD_LCD_DATA23__GPIO3_IO11 0x0174 0x043C 0x0000 0x5 0x0 -#define MX6SLL_PAD_LCD_DATA23__SRC_BOOT_CFG31 0x0174 0x043C 0x0000 0x7 0x0 -#define MX6SLL_PAD_AUD_RXFS__AUD3_RXFS 0x0178 0x0440 0x0000 0x0 0x0 -#define MX6SLL_PAD_AUD_RXFS__I2C1_SCL 0x0178 0x0440 0x067C 0x1 0x1 -#define MX6SLL_PAD_AUD_RXFS__UART3_DCE_RX 0x0178 0x0440 0x0754 0x2 0x0 -#define MX6SLL_PAD_AUD_RXFS__UART3_DTE_TX 0x0178 0x0440 0x0000 0x2 0x0 -#define MX6SLL_PAD_AUD_RXFS__I2C3_SCL 0x0178 0x0440 0x068C 0x4 0x1 -#define MX6SLL_PAD_AUD_RXFS__GPIO1_IO00 0x0178 0x0440 0x0000 0x5 0x0 -#define MX6SLL_PAD_AUD_RXFS__ECSPI3_SS0 0x0178 0x0440 0x0648 0x6 0x0 -#define MX6SLL_PAD_AUD_RXFS__MBIST_BEND 0x0178 0x0440 0x0000 0x7 0x0 -#define MX6SLL_PAD_AUD_RXC__AUD3_RXC 0x017C 0x0444 0x0000 0x0 0x0 -#define MX6SLL_PAD_AUD_RXC__I2C1_SDA 0x017C 0x0444 0x0680 0x1 0x1 -#define MX6SLL_PAD_AUD_RXC__UART3_DCE_TX 0x017C 0x0444 0x0000 0x2 0x0 -#define MX6SLL_PAD_AUD_RXC__UART3_DTE_RX 0x017C 0x0444 0x0754 0x2 0x1 -#define MX6SLL_PAD_AUD_RXC__I2C3_SDA 0x017C 0x0444 0x0690 0x4 0x1 -#define MX6SLL_PAD_AUD_RXC__GPIO1_IO01 0x017C 0x0444 0x0000 0x5 0x0 -#define MX6SLL_PAD_AUD_RXC__ECSPI3_SS1 0x017C 0x0444 0x064C 0x6 0x0 -#define MX6SLL_PAD_AUD_RXD__AUD3_RXD 0x0180 0x0448 0x0000 0x0 0x0 -#define MX6SLL_PAD_AUD_RXD__ECSPI3_MOSI 0x0180 0x0448 0x063C 0x1 0x0 -#define MX6SLL_PAD_AUD_RXD__UART4_DCE_RX 0x0180 0x0448 0x075C 0x2 0x0 -#define MX6SLL_PAD_AUD_RXD__UART4_DTE_TX 0x0180 0x0448 0x0000 0x2 0x0 -#define MX6SLL_PAD_AUD_RXD__SD1_LCTL 0x0180 0x0448 0x0000 0x4 0x0 -#define MX6SLL_PAD_AUD_RXD__GPIO1_IO02 0x0180 0x0448 0x0000 0x5 0x0 -#define MX6SLL_PAD_AUD_TXC__AUD3_TXC 0x0184 0x044C 0x0000 0x0 0x0 -#define MX6SLL_PAD_AUD_TXC__ECSPI3_MISO 0x0184 0x044C 0x0638 0x1 0x0 -#define MX6SLL_PAD_AUD_TXC__UART4_DCE_TX 0x0184 0x044C 0x0000 0x2 0x0 -#define MX6SLL_PAD_AUD_TXC__UART4_DTE_RX 0x0184 0x044C 0x075C 0x2 0x1 -#define MX6SLL_PAD_AUD_TXC__SD2_LCTL 0x0184 0x044C 0x0000 0x4 0x0 -#define MX6SLL_PAD_AUD_TXC__GPIO1_IO03 0x0184 0x044C 0x0000 0x5 0x0 -#define MX6SLL_PAD_AUD_TXFS__AUD3_TXFS 0x0188 0x0450 0x0000 0x0 0x0 -#define MX6SLL_PAD_AUD_TXFS__PWM3_OUT 0x0188 0x0450 0x0000 0x1 0x0 -#define MX6SLL_PAD_AUD_TXFS__UART4_DCE_RTS 0x0188 0x0450 0x0758 0x2 0x0 -#define MX6SLL_PAD_AUD_TXFS__UART4_DTE_CTS 0x0188 0x0450 0x0000 0x2 0x0 -#define MX6SLL_PAD_AUD_TXFS__SD3_LCTL 0x0188 0x0450 0x0000 0x4 0x0 -#define MX6SLL_PAD_AUD_TXFS__GPIO1_IO04 0x0188 0x0450 0x0000 0x5 0x0 -#define MX6SLL_PAD_AUD_TXD__AUD3_TXD 0x018C 0x0454 0x0000 0x0 0x0 -#define MX6SLL_PAD_AUD_TXD__ECSPI3_SCLK 0x018C 0x0454 0x0630 0x1 0x0 -#define MX6SLL_PAD_AUD_TXD__UART4_DCE_CTS 0x018C 0x0454 0x0000 0x2 0x0 -#define MX6SLL_PAD_AUD_TXD__UART4_DTE_RTS 0x018C 0x0454 0x0758 0x2 0x1 -#define MX6SLL_PAD_AUD_TXD__GPIO1_IO05 0x018C 0x0454 0x0000 0x5 0x0 -#define MX6SLL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x0190 0x0458 0x0000 0x0 0x0 -#define MX6SLL_PAD_AUD_MCLK__PWM4_OUT 0x0190 0x0458 0x0000 0x1 0x0 -#define MX6SLL_PAD_AUD_MCLK__ECSPI3_RDY 0x0190 0x0458 0x0634 0x2 0x0 -#define MX6SLL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x0190 0x0458 0x0000 0x4 0x0 -#define MX6SLL_PAD_AUD_MCLK__GPIO1_IO06 0x0190 0x0458 0x0000 0x5 0x0 -#define MX6SLL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x0190 0x0458 0x073C 0x6 0x1 -#define MX6SLL_PAD_UART1_RXD__UART1_DCE_RX 0x0194 0x045C 0x0744 0x0 0x0 -#define MX6SLL_PAD_UART1_RXD__UART1_DTE_TX 0x0194 0x045C 0x0000 0x0 0x0 -#define MX6SLL_PAD_UART1_RXD__PWM1_OUT 0x0194 0x045C 0x0000 0x1 0x0 -#define MX6SLL_PAD_UART1_RXD__UART4_DCE_RX 0x0194 0x045C 0x075C 0x2 0x4 -#define MX6SLL_PAD_UART1_RXD__UART4_DTE_TX 0x0194 0x045C 0x0000 0x2 0x0 -#define MX6SLL_PAD_UART1_RXD__UART5_DCE_RX 0x0194 0x045C 0x0764 0x4 0x6 -#define MX6SLL_PAD_UART1_RXD__UART5_DTE_TX 0x0194 0x045C 0x0000 0x4 0x0 -#define MX6SLL_PAD_UART1_RXD__GPIO3_IO16 0x0194 0x045C 0x0000 0x5 0x0 -#define MX6SLL_PAD_UART1_TXD__UART1_DCE_TX 0x0198 0x0460 0x0000 0x0 0x0 -#define MX6SLL_PAD_UART1_TXD__UART1_DTE_RX 0x0198 0x0460 0x0744 0x0 0x1 -#define MX6SLL_PAD_UART1_TXD__PWM2_OUT 0x0198 0x0460 0x0000 0x1 0x0 -#define MX6SLL_PAD_UART1_TXD__UART4_DCE_TX 0x0198 0x0460 0x0000 0x2 0x0 -#define MX6SLL_PAD_UART1_TXD__UART4_DTE_RX 0x0198 0x0460 0x075C 0x2 0x5 -#define MX6SLL_PAD_UART1_TXD__UART5_DCE_TX 0x0198 0x0460 0x0000 0x4 0x0 -#define MX6SLL_PAD_UART1_TXD__UART5_DTE_RX 0x0198 0x0460 0x0764 0x4 0x7 -#define MX6SLL_PAD_UART1_TXD__GPIO3_IO17 0x0198 0x0460 0x0000 0x5 0x0 -#define MX6SLL_PAD_UART1_TXD__UART5_DCD_B 0x0198 0x0460 0x0000 0x7 0x0 -#define MX6SLL_PAD_I2C1_SCL__I2C1_SCL 0x019C 0x0464 0x067C 0x0 0x0 -#define MX6SLL_PAD_I2C1_SCL__UART1_DCE_RTS 0x019C 0x0464 0x0740 0x1 0x0 -#define MX6SLL_PAD_I2C1_SCL__UART1_DTE_CTS 0x019C 0x0464 0x0000 0x1 0x0 -#define MX6SLL_PAD_I2C1_SCL__ECSPI3_SS2 0x019C 0x0464 0x0640 0x2 0x0 -#define MX6SLL_PAD_I2C1_SCL__SD3_RESET 0x019C 0x0464 0x0000 0x4 0x0 -#define MX6SLL_PAD_I2C1_SCL__GPIO3_IO12 0x019C 0x0464 0x0000 0x5 0x0 -#define MX6SLL_PAD_I2C1_SCL__ECSPI1_SS1 0x019C 0x0464 0x060C 0x6 0x0 -#define MX6SLL_PAD_I2C1_SDA__I2C1_SDA 0x01A0 0x0468 0x0680 0x0 0x0 -#define MX6SLL_PAD_I2C1_SDA__UART1_DCE_CTS 0x01A0 0x0468 0x0000 0x1 0x0 -#define MX6SLL_PAD_I2C1_SDA__UART1_DTE_RTS 0x01A0 0x0468 0x0740 0x1 0x1 -#define MX6SLL_PAD_I2C1_SDA__ECSPI3_SS3 0x01A0 0x0468 0x0644 0x2 0x0 -#define MX6SLL_PAD_I2C1_SDA__SD3_VSELECT 0x01A0 0x0468 0x0000 0x4 0x0 -#define MX6SLL_PAD_I2C1_SDA__GPIO3_IO13 0x01A0 0x0468 0x0000 0x5 0x0 -#define MX6SLL_PAD_I2C1_SDA__ECSPI1_SS2 0x01A0 0x0468 0x0610 0x6 0x0 -#define MX6SLL_PAD_I2C2_SCL__I2C2_SCL 0x01A4 0x046C 0x0684 0x0 0x3 -#define MX6SLL_PAD_I2C2_SCL__AUD4_RXFS 0x01A4 0x046C 0x0570 0x1 0x2 -#define MX6SLL_PAD_I2C2_SCL__SPDIF_IN 0x01A4 0x046C 0x0738 0x2 0x2 -#define MX6SLL_PAD_I2C2_SCL__SD3_WP 0x01A4 0x046C 0x0794 0x4 0x3 -#define MX6SLL_PAD_I2C2_SCL__GPIO3_IO14 0x01A4 0x046C 0x0000 0x5 0x0 -#define MX6SLL_PAD_I2C2_SCL__ECSPI1_RDY 0x01A4 0x046C 0x0600 0x6 0x1 -#define MX6SLL_PAD_I2C2_SDA__I2C2_SDA 0x01A8 0x0470 0x0688 0x0 0x3 -#define MX6SLL_PAD_I2C2_SDA__AUD4_RXC 0x01A8 0x0470 0x056C 0x1 0x2 -#define MX6SLL_PAD_I2C2_SDA__SPDIF_OUT 0x01A8 0x0470 0x0000 0x2 0x0 -#define MX6SLL_PAD_I2C2_SDA__SD3_CD_B 0x01A8 0x0470 0x0780 0x4 0x3 -#define MX6SLL_PAD_I2C2_SDA__GPIO3_IO15 0x01A8 0x0470 0x0000 0x5 0x0 -#define MX6SLL_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x01AC 0x0474 0x05FC 0x0 0x1 -#define MX6SLL_PAD_ECSPI1_SCLK__AUD4_TXD 0x01AC 0x0474 0x0568 0x1 0x1 -#define MX6SLL_PAD_ECSPI1_SCLK__UART5_DCE_RX 0x01AC 0x0474 0x0764 0x2 0x2 -#define MX6SLL_PAD_ECSPI1_SCLK__UART5_DTE_TX 0x01AC 0x0474 0x0000 0x2 0x0 -#define MX6SLL_PAD_ECSPI1_SCLK__EPDC_VCOM0 0x01AC 0x0474 0x0000 0x3 0x0 -#define MX6SLL_PAD_ECSPI1_SCLK__SD2_RESET 0x01AC 0x0474 0x0000 0x4 0x0 -#define MX6SLL_PAD_ECSPI1_SCLK__GPIO4_IO08 0x01AC 0x0474 0x0000 0x5 0x0 -#define MX6SLL_PAD_ECSPI1_SCLK__USB_OTG2_OC 0x01AC 0x0474 0x0768 0x6 0x1 -#define MX6SLL_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x01B0 0x0478 0x0608 0x0 0x1 -#define MX6SLL_PAD_ECSPI1_MOSI__AUD4_TXC 0x01B0 0x0478 0x0574 0x1 0x1 -#define MX6SLL_PAD_ECSPI1_MOSI__UART5_DCE_TX 0x01B0 0x0478 0x0000 0x2 0x0 -#define MX6SLL_PAD_ECSPI1_MOSI__UART5_DTE_RX 0x01B0 0x0478 0x0764 0x2 0x3 -#define MX6SLL_PAD_ECSPI1_MOSI__EPDC_VCOM1 0x01B0 0x0478 0x0000 0x3 0x0 -#define MX6SLL_PAD_ECSPI1_MOSI__SD2_VSELECT 0x01B0 0x0478 0x0000 0x4 0x0 -#define MX6SLL_PAD_ECSPI1_MOSI__GPIO4_IO09 0x01B0 0x0478 0x0000 0x5 0x0 -#define MX6SLL_PAD_ECSPI1_MISO__ECSPI1_MISO 0x01B4 0x047C 0x0604 0x0 0x1 -#define MX6SLL_PAD_ECSPI1_MISO__AUD4_TXFS 0x01B4 0x047C 0x0578 0x1 0x1 -#define MX6SLL_PAD_ECSPI1_MISO__UART5_DCE_RTS 0x01B4 0x047C 0x0760 0x2 0x2 -#define MX6SLL_PAD_ECSPI1_MISO__UART5_DTE_CTS 0x01B4 0x047C 0x0000 0x2 0x0 -#define MX6SLL_PAD_ECSPI1_MISO__EPDC_BDR0 0x01B4 0x047C 0x0000 0x3 0x0 -#define MX6SLL_PAD_ECSPI1_MISO__SD2_WP 0x01B4 0x047C 0x077C 0x4 0x0 -#define MX6SLL_PAD_ECSPI1_MISO__GPIO4_IO10 0x01B4 0x047C 0x0000 0x5 0x0 -#define MX6SLL_PAD_ECSPI1_SS0__ECSPI1_SS0 0x01B8 0x0480 0x0614 0x0 0x1 -#define MX6SLL_PAD_ECSPI1_SS0__AUD4_RXD 0x01B8 0x0480 0x0564 0x1 0x1 -#define MX6SLL_PAD_ECSPI1_SS0__UART5_DCE_CTS 0x01B8 0x0480 0x0000 0x2 0x0 -#define MX6SLL_PAD_ECSPI1_SS0__UART5_DTE_RTS 0x01B8 0x0480 0x0760 0x2 0x3 -#define MX6SLL_PAD_ECSPI1_SS0__EPDC_BDR1 0x01B8 0x0480 0x0000 0x3 0x0 -#define MX6SLL_PAD_ECSPI1_SS0__SD2_CD_B 0x01B8 0x0480 0x0778 0x4 0x0 -#define MX6SLL_PAD_ECSPI1_SS0__GPIO4_IO11 0x01B8 0x0480 0x0000 0x5 0x0 -#define MX6SLL_PAD_ECSPI1_SS0__USB_OTG2_PWR 0x01B8 0x0480 0x0000 0x6 0x0 -#define MX6SLL_PAD_ECSPI2_SCLK__ECSPI2_SCLK 0x01BC 0x0484 0x061C 0x0 0x1 -#define MX6SLL_PAD_ECSPI2_SCLK__SPDIF_EXT_CLK 0x01BC 0x0484 0x073C 0x1 0x2 -#define MX6SLL_PAD_ECSPI2_SCLK__UART3_DCE_RX 0x01BC 0x0484 0x0754 0x2 0x2 -#define MX6SLL_PAD_ECSPI2_SCLK__UART3_DTE_TX 0x01BC 0x0484 0x0000 0x2 0x0 -#define MX6SLL_PAD_ECSPI2_SCLK__CSI_PIXCLK 0x01BC 0x0484 0x05F4 0x3 0x1 -#define MX6SLL_PAD_ECSPI2_SCLK__SD1_RESET 0x01BC 0x0484 0x0000 0x4 0x0 -#define MX6SLL_PAD_ECSPI2_SCLK__GPIO4_IO12 0x01BC 0x0484 0x0000 0x5 0x0 -#define MX6SLL_PAD_ECSPI2_SCLK__USB_OTG2_OC 0x01BC 0x0484 0x0768 0x6 0x2 -#define MX6SLL_PAD_ECSPI2_MOSI__ECSPI2_MOSI 0x01C0 0x0488 0x0624 0x0 0x1 -#define MX6SLL_PAD_ECSPI2_MOSI__SDMA_EXT_EVENT1 0x01C0 0x0488 0x0000 0x1 0x0 -#define MX6SLL_PAD_ECSPI2_MOSI__UART3_DCE_TX 0x01C0 0x0488 0x0000 0x2 0x0 -#define MX6SLL_PAD_ECSPI2_MOSI__UART3_DTE_RX 0x01C0 0x0488 0x0754 0x2 0x3 -#define MX6SLL_PAD_ECSPI2_MOSI__CSI_HSYNC 0x01C0 0x0488 0x05F0 0x3 0x1 -#define MX6SLL_PAD_ECSPI2_MOSI__SD1_VSELECT 0x01C0 0x0488 0x0000 0x4 0x0 -#define MX6SLL_PAD_ECSPI2_MOSI__GPIO4_IO13 0x01C0 0x0488 0x0000 0x5 0x0 -#define MX6SLL_PAD_ECSPI2_MISO__ECSPI2_MISO 0x01C4 0x048C 0x0620 0x0 0x1 -#define MX6SLL_PAD_ECSPI2_MISO__SDMA_EXT_EVENT0 0x01C4 0x048C 0x0000 0x1 0x0 -#define MX6SLL_PAD_ECSPI2_MISO__UART3_DCE_RTS 0x01C4 0x048C 0x0750 0x2 0x0 -#define MX6SLL_PAD_ECSPI2_MISO__UART3_DTE_CTS 0x01C4 0x048C 0x0000 0x2 0x0 -#define MX6SLL_PAD_ECSPI2_MISO__CSI_MCLK 0x01C4 0x048C 0x0000 0x3 0x0 -#define MX6SLL_PAD_ECSPI2_MISO__SD1_WP 0x01C4 0x048C 0x0774 0x4 0x2 -#define MX6SLL_PAD_ECSPI2_MISO__GPIO4_IO14 0x01C4 0x048C 0x0000 0x5 0x0 -#define MX6SLL_PAD_ECSPI2_MISO__USB_OTG1_OC 0x01C4 0x048C 0x076C 0x6 0x1 -#define MX6SLL_PAD_ECSPI2_SS0__ECSPI2_SS0 0x01C8 0x0490 0x0628 0x0 0x0 -#define MX6SLL_PAD_ECSPI2_SS0__ECSPI1_SS3 0x01C8 0x0490 0x0618 0x1 0x1 -#define MX6SLL_PAD_ECSPI2_SS0__UART3_DCE_CTS 0x01C8 0x0490 0x0000 0x2 0x0 -#define MX6SLL_PAD_ECSPI2_SS0__UART3_DTE_RTS 0x01C8 0x0490 0x0750 0x2 0x1 -#define MX6SLL_PAD_ECSPI2_SS0__CSI_VSYNC 0x01C8 0x0490 0x05F8 0x3 0x1 -#define MX6SLL_PAD_ECSPI2_SS0__SD1_CD_B 0x01C8 0x0490 0x0770 0x4 0x2 -#define MX6SLL_PAD_ECSPI2_SS0__GPIO4_IO15 0x01C8 0x0490 0x0000 0x5 0x0 -#define MX6SLL_PAD_ECSPI2_SS0__USB_OTG1_PWR 0x01C8 0x0490 0x0000 0x6 0x0 -#define MX6SLL_PAD_SD1_CLK__SD1_CLK 0x01CC 0x0494 0x0000 0x0 0x0 -#define MX6SLL_PAD_SD1_CLK__KEY_COL0 0x01CC 0x0494 0x06A0 0x2 0x2 -#define MX6SLL_PAD_SD1_CLK__EPDC_SDCE4 0x01CC 0x0494 0x0000 0x3 0x0 -#define MX6SLL_PAD_SD1_CLK__GPIO5_IO15 0x01CC 0x0494 0x0000 0x5 0x0 -#define MX6SLL_PAD_SD1_CMD__SD1_CMD 0x01D0 0x0498 0x0000 0x0 0x0 -#define MX6SLL_PAD_SD1_CMD__KEY_ROW0 0x01D0 0x0498 0x06C0 0x2 0x2 -#define MX6SLL_PAD_SD1_CMD__EPDC_SDCE5 0x01D0 0x0498 0x0000 0x3 0x0 -#define MX6SLL_PAD_SD1_CMD__GPIO5_IO14 0x01D0 0x0498 0x0000 0x5 0x0 -#define MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x01D4 0x049C 0x0000 0x0 0x0 -#define MX6SLL_PAD_SD1_DATA0__KEY_COL1 0x01D4 0x049C 0x06A4 0x2 0x2 -#define MX6SLL_PAD_SD1_DATA0__EPDC_SDCE6 0x01D4 0x049C 0x0000 0x3 0x0 -#define MX6SLL_PAD_SD1_DATA0__GPIO5_IO11 0x01D4 0x049C 0x0000 0x5 0x0 -#define MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x01D8 0x04A0 0x0000 0x0 0x0 -#define MX6SLL_PAD_SD1_DATA1__KEY_ROW1 0x01D8 0x04A0 0x06C4 0x2 0x2 -#define MX6SLL_PAD_SD1_DATA1__EPDC_SDCE7 0x01D8 0x04A0 0x0000 0x3 0x0 -#define MX6SLL_PAD_SD1_DATA1__GPIO5_IO08 0x01D8 0x04A0 0x0000 0x5 0x0 -#define MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x01DC 0x04A4 0x0000 0x0 0x0 -#define MX6SLL_PAD_SD1_DATA2__KEY_COL2 0x01DC 0x04A4 0x06A8 0x2 0x2 -#define MX6SLL_PAD_SD1_DATA2__EPDC_SDCE8 0x01DC 0x04A4 0x0000 0x3 0x0 -#define MX6SLL_PAD_SD1_DATA2__GPIO5_IO13 0x01DC 0x04A4 0x0000 0x5 0x0 -#define MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x01E0 0x04A8 0x0000 0x0 0x0 -#define MX6SLL_PAD_SD1_DATA3__KEY_ROW2 0x01E0 0x04A8 0x06C8 0x2 0x2 -#define MX6SLL_PAD_SD1_DATA3__EPDC_SDCE9 0x01E0 0x04A8 0x0000 0x3 0x0 -#define MX6SLL_PAD_SD1_DATA3__GPIO5_IO06 0x01E0 0x04A8 0x0000 0x5 0x0 -#define MX6SLL_PAD_SD1_DATA4__SD1_DATA4 0x01E4 0x04AC 0x0000 0x0 0x0 -#define MX6SLL_PAD_SD1_DATA4__KEY_COL3 0x01E4 0x04AC 0x06AC 0x2 0x2 -#define MX6SLL_PAD_SD1_DATA4__EPDC_SDCLK_N 0x01E4 0x04AC 0x0000 0x3 0x0 -#define MX6SLL_PAD_SD1_DATA4__UART4_DCE_RX 0x01E4 0x04AC 0x075C 0x4 0x6 -#define MX6SLL_PAD_SD1_DATA4__UART4_DTE_TX 0x01E4 0x04AC 0x0000 0x4 0x0 -#define MX6SLL_PAD_SD1_DATA4__GPIO5_IO12 0x01E4 0x04AC 0x0000 0x5 0x0 -#define MX6SLL_PAD_SD1_DATA5__SD1_DATA5 0x01E8 0x04B0 0x0000 0x0 0x0 -#define MX6SLL_PAD_SD1_DATA5__KEY_ROW3 0x01E8 0x04B0 0x06CC 0x2 0x2 -#define MX6SLL_PAD_SD1_DATA5__EPDC_SDOED 0x01E8 0x04B0 0x0000 0x3 0x0 -#define MX6SLL_PAD_SD1_DATA5__UART4_DCE_TX 0x01E8 0x04B0 0x0000 0x4 0x0 -#define MX6SLL_PAD_SD1_DATA5__UART4_DTE_RX 0x01E8 0x04B0 0x075C 0x4 0x7 -#define MX6SLL_PAD_SD1_DATA5__GPIO5_IO09 0x01E8 0x04B0 0x0000 0x5 0x0 -#define MX6SLL_PAD_SD1_DATA6__SD1_DATA6 0x01EC 0x04B4 0x0000 0x0 0x0 -#define MX6SLL_PAD_SD1_DATA6__KEY_COL4 0x01EC 0x04B4 0x06B0 0x2 0x2 -#define MX6SLL_PAD_SD1_DATA6__EPDC_SDOEZ 0x01EC 0x04B4 0x0000 0x3 0x0 -#define MX6SLL_PAD_SD1_DATA6__UART4_DCE_RTS 0x01EC 0x04B4 0x0758 0x4 0x4 -#define MX6SLL_PAD_SD1_DATA6__UART4_DTE_CTS 0x01EC 0x04B4 0x0000 0x4 0x0 -#define MX6SLL_PAD_SD1_DATA6__GPIO5_IO07 0x01EC 0x04B4 0x0000 0x5 0x0 -#define MX6SLL_PAD_SD1_DATA7__SD1_DATA7 0x01F0 0x04B8 0x0000 0x0 0x0 -#define MX6SLL_PAD_SD1_DATA7__KEY_ROW4 0x01F0 0x04B8 0x06D0 0x2 0x2 -#define MX6SLL_PAD_SD1_DATA7__CCM_PMIC_READY 0x01F0 0x04B8 0x05AC 0x3 0x3 -#define MX6SLL_PAD_SD1_DATA7__UART4_DCE_CTS 0x01F0 0x04B8 0x0000 0x4 0x0 -#define MX6SLL_PAD_SD1_DATA7__UART4_DTE_RTS 0x01F0 0x04B8 0x0758 0x4 0x5 -#define MX6SLL_PAD_SD1_DATA7__GPIO5_IO10 0x01F0 0x04B8 0x0000 0x5 0x0 -#define MX6SLL_PAD_SD2_RESET__SD2_RESET 0x01F4 0x04BC 0x0000 0x0 0x0 -#define MX6SLL_PAD_SD2_RESET__WDOG2_B 0x01F4 0x04BC 0x0000 0x2 0x0 -#define MX6SLL_PAD_SD2_RESET__SPDIF_OUT 0x01F4 0x04BC 0x0000 0x3 0x0 -#define MX6SLL_PAD_SD2_RESET__CSI_MCLK 0x01F4 0x04BC 0x0000 0x4 0x0 -#define MX6SLL_PAD_SD2_RESET__GPIO4_IO27 0x01F4 0x04BC 0x0000 0x5 0x0 -#define MX6SLL_PAD_SD2_CLK__SD2_CLK 0x01F8 0x04C0 0x0000 0x0 0x0 -#define MX6SLL_PAD_SD2_CLK__AUD4_RXFS 0x01F8 0x04C0 0x0570 0x1 0x1 -#define MX6SLL_PAD_SD2_CLK__ECSPI3_SCLK 0x01F8 0x04C0 0x0630 0x2 0x1 -#define MX6SLL_PAD_SD2_CLK__CSI_DATA00 0x01F8 0x04C0 0x05C8 0x3 0x1 -#define MX6SLL_PAD_SD2_CLK__GPIO5_IO05 0x01F8 0x04C0 0x0000 0x5 0x0 -#define MX6SLL_PAD_SD2_CMD__SD2_CMD 0x01FC 0x04C4 0x0000 0x0 0x0 -#define MX6SLL_PAD_SD2_CMD__AUD4_RXC 0x01FC 0x04C4 0x056C 0x1 0x1 -#define MX6SLL_PAD_SD2_CMD__ECSPI3_SS0 0x01FC 0x04C4 0x0648 0x2 0x1 -#define MX6SLL_PAD_SD2_CMD__CSI_DATA01 0x01FC 0x04C4 0x05CC 0x3 0x1 -#define MX6SLL_PAD_SD2_CMD__EPIT1_OUT 0x01FC 0x04C4 0x0000 0x4 0x0 -#define MX6SLL_PAD_SD2_CMD__GPIO5_IO04 0x01FC 0x04C4 0x0000 0x5 0x0 -#define MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x0200 0x04C8 0x0000 0x0 0x0 -#define MX6SLL_PAD_SD2_DATA0__AUD4_RXD 0x0200 0x04C8 0x0564 0x1 0x2 -#define MX6SLL_PAD_SD2_DATA0__ECSPI3_MOSI 0x0200 0x04C8 0x063C 0x2 0x1 -#define MX6SLL_PAD_SD2_DATA0__CSI_DATA02 0x0200 0x04C8 0x05D0 0x3 0x1 -#define MX6SLL_PAD_SD2_DATA0__UART5_DCE_RTS 0x0200 0x04C8 0x0760 0x4 0x4 -#define MX6SLL_PAD_SD2_DATA0__UART5_DTE_CTS 0x0200 0x04C8 0x0000 0x4 0x0 -#define MX6SLL_PAD_SD2_DATA0__GPIO5_IO01 0x0200 0x04C8 0x0000 0x5 0x0 -#define MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x0204 0x04CC 0x0000 0x0 0x0 -#define MX6SLL_PAD_SD2_DATA1__AUD4_TXC 0x0204 0x04CC 0x0574 0x1 0x2 -#define MX6SLL_PAD_SD2_DATA1__ECSPI3_MISO 0x0204 0x04CC 0x0638 0x2 0x1 -#define MX6SLL_PAD_SD2_DATA1__CSI_DATA03 0x0204 0x04CC 0x05D4 0x3 0x1 -#define MX6SLL_PAD_SD2_DATA1__UART5_DCE_CTS 0x0204 0x04CC 0x0000 0x4 0x0 -#define MX6SLL_PAD_SD2_DATA1__UART5_DTE_RTS 0x0204 0x04CC 0x0760 0x4 0x5 -#define MX6SLL_PAD_SD2_DATA1__GPIO4_IO30 0x0204 0x04CC 0x0000 0x5 0x0 -#define MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x0208 0x04D0 0x0000 0x0 0x0 -#define MX6SLL_PAD_SD2_DATA2__AUD4_TXFS 0x0208 0x04D0 0x0578 0x1 0x2 -#define MX6SLL_PAD_SD2_DATA2__CSI_DATA04 0x0208 0x04D0 0x05D8 0x3 0x1 -#define MX6SLL_PAD_SD2_DATA2__UART5_DCE_RX 0x0208 0x04D0 0x0764 0x4 0x4 -#define MX6SLL_PAD_SD2_DATA2__UART5_DTE_TX 0x0208 0x04D0 0x0000 0x4 0x0 -#define MX6SLL_PAD_SD2_DATA2__GPIO5_IO03 0x0208 0x04D0 0x0000 0x5 0x0 -#define MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x020C 0x04D4 0x0000 0x0 0x0 -#define MX6SLL_PAD_SD2_DATA3__AUD4_TXD 0x020C 0x04D4 0x0568 0x1 0x2 -#define MX6SLL_PAD_SD2_DATA3__CSI_DATA05 0x020C 0x04D4 0x05DC 0x3 0x1 -#define MX6SLL_PAD_SD2_DATA3__UART5_DCE_TX 0x020C 0x04D4 0x0000 0x4 0x0 -#define MX6SLL_PAD_SD2_DATA3__UART5_DTE_RX 0x020C 0x04D4 0x0764 0x4 0x5 -#define MX6SLL_PAD_SD2_DATA3__GPIO4_IO28 0x020C 0x04D4 0x0000 0x5 0x0 -#define MX6SLL_PAD_SD2_DATA4__SD2_DATA4 0x0210 0x04D8 0x0000 0x0 0x0 -#define MX6SLL_PAD_SD2_DATA4__SD3_DATA4 0x0210 0x04D8 0x0784 0x1 0x1 -#define MX6SLL_PAD_SD2_DATA4__UART2_DCE_RX 0x0210 0x04D8 0x074C 0x2 0x2 -#define MX6SLL_PAD_SD2_DATA4__UART2_DTE_TX 0x0210 0x04D8 0x0000 0x2 0x0 -#define MX6SLL_PAD_SD2_DATA4__CSI_DATA06 0x0210 0x04D8 0x05E0 0x3 0x1 -#define MX6SLL_PAD_SD2_DATA4__SPDIF_OUT 0x0210 0x04D8 0x0000 0x4 0x0 -#define MX6SLL_PAD_SD2_DATA4__GPIO5_IO02 0x0210 0x04D8 0x0000 0x5 0x0 -#define MX6SLL_PAD_SD2_DATA5__SD2_DATA5 0x0214 0x04DC 0x0000 0x0 0x0 -#define MX6SLL_PAD_SD2_DATA5__SD3_DATA5 0x0214 0x04DC 0x0788 0x1 0x1 -#define MX6SLL_PAD_SD2_DATA5__UART2_DCE_TX 0x0214 0x04DC 0x0000 0x2 0x0 -#define MX6SLL_PAD_SD2_DATA5__UART2_DTE_RX 0x0214 0x04DC 0x074C 0x2 0x3 -#define MX6SLL_PAD_SD2_DATA5__CSI_DATA07 0x0214 0x04DC 0x05E4 0x3 0x1 -#define MX6SLL_PAD_SD2_DATA5__SPDIF_IN 0x0214 0x04DC 0x0738 0x4 0x1 -#define MX6SLL_PAD_SD2_DATA5__GPIO4_IO31 0x0214 0x04DC 0x0000 0x5 0x0 -#define MX6SLL_PAD_SD2_DATA6__SD2_DATA6 0x0218 0x04E0 0x0000 0x0 0x0 -#define MX6SLL_PAD_SD2_DATA6__SD3_DATA6 0x0218 0x04E0 0x078C 0x1 0x1 -#define MX6SLL_PAD_SD2_DATA6__UART2_DCE_RTS 0x0218 0x04E0 0x0748 0x2 0x2 -#define MX6SLL_PAD_SD2_DATA6__UART2_DTE_CTS 0x0218 0x04E0 0x0000 0x2 0x0 -#define MX6SLL_PAD_SD2_DATA6__CSI_DATA08 0x0218 0x04E0 0x05E8 0x3 0x1 -#define MX6SLL_PAD_SD2_DATA6__SD2_WP 0x0218 0x04E0 0x077C 0x4 0x1 -#define MX6SLL_PAD_SD2_DATA6__GPIO4_IO29 0x0218 0x04E0 0x0000 0x5 0x0 -#define MX6SLL_PAD_SD2_DATA7__SD2_DATA7 0x021C 0x04E4 0x0000 0x0 0x0 -#define MX6SLL_PAD_SD2_DATA7__SD3_DATA7 0x021C 0x04E4 0x0790 0x1 0x1 -#define MX6SLL_PAD_SD2_DATA7__UART2_DCE_CTS 0x021C 0x04E4 0x0000 0x2 0x0 -#define MX6SLL_PAD_SD2_DATA7__UART2_DTE_RTS 0x021C 0x04E4 0x0748 0x2 0x3 -#define MX6SLL_PAD_SD2_DATA7__CSI_DATA09 0x021C 0x04E4 0x05EC 0x3 0x1 -#define MX6SLL_PAD_SD2_DATA7__SD2_CD_B 0x021C 0x04E4 0x0778 0x4 0x1 -#define MX6SLL_PAD_SD2_DATA7__GPIO5_IO00 0x021C 0x04E4 0x0000 0x5 0x0 -#define MX6SLL_PAD_SD3_CLK__SD3_CLK 0x0220 0x04E8 0x0000 0x0 0x0 -#define MX6SLL_PAD_SD3_CLK__AUD5_RXFS 0x0220 0x04E8 0x0588 0x1 0x0 -#define MX6SLL_PAD_SD3_CLK__KEY_COL5 0x0220 0x04E8 0x0694 0x2 0x0 -#define MX6SLL_PAD_SD3_CLK__CSI_DATA10 0x0220 0x04E8 0x05B0 0x3 0x0 -#define MX6SLL_PAD_SD3_CLK__WDOG1_RESET_B_DEB 0x0220 0x04E8 0x0000 0x4 0x0 -#define MX6SLL_PAD_SD3_CLK__GPIO5_IO18 0x0220 0x04E8 0x0000 0x5 0x0 -#define MX6SLL_PAD_SD3_CLK__USB_OTG1_PWR 0x0220 0x04E8 0x0000 0x6 0x0 -#define MX6SLL_PAD_SD3_CMD__SD3_CMD 0x0224 0x04EC 0x0000 0x0 0x0 -#define MX6SLL_PAD_SD3_CMD__AUD5_RXC 0x0224 0x04EC 0x0584 0x1 0x0 -#define MX6SLL_PAD_SD3_CMD__KEY_ROW5 0x0224 0x04EC 0x06B4 0x2 0x0 -#define MX6SLL_PAD_SD3_CMD__CSI_DATA11 0x0224 0x04EC 0x05B4 0x3 0x0 -#define MX6SLL_PAD_SD3_CMD__USB_OTG2_ID 0x0224 0x04EC 0x0560 0x4 0x1 -#define MX6SLL_PAD_SD3_CMD__GPIO5_IO21 0x0224 0x04EC 0x0000 0x5 0x0 -#define MX6SLL_PAD_SD3_CMD__USB_OTG2_PWR 0x0224 0x04EC 0x0000 0x6 0x0 -#define MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x0228 0x04F0 0x0000 0x0 0x0 -#define MX6SLL_PAD_SD3_DATA0__AUD5_RXD 0x0228 0x04F0 0x057C 0x1 0x0 -#define MX6SLL_PAD_SD3_DATA0__KEY_COL6 0x0228 0x04F0 0x0698 0x2 0x0 -#define MX6SLL_PAD_SD3_DATA0__CSI_DATA12 0x0228 0x04F0 0x05B8 0x3 0x0 -#define MX6SLL_PAD_SD3_DATA0__USB_OTG1_ID 0x0228 0x04F0 0x055C 0x4 0x1 -#define MX6SLL_PAD_SD3_DATA0__GPIO5_IO19 0x0228 0x04F0 0x0000 0x5 0x0 -#define MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x022C 0x04F4 0x0000 0x0 0x0 -#define MX6SLL_PAD_SD3_DATA1__AUD5_TXC 0x022C 0x04F4 0x058C 0x1 0x0 -#define MX6SLL_PAD_SD3_DATA1__KEY_ROW6 0x022C 0x04F4 0x06B8 0x2 0x0 -#define MX6SLL_PAD_SD3_DATA1__CSI_DATA13 0x022C 0x04F4 0x05BC 0x3 0x0 -#define MX6SLL_PAD_SD3_DATA1__SD1_VSELECT 0x022C 0x04F4 0x0000 0x4 0x0 -#define MX6SLL_PAD_SD3_DATA1__GPIO5_IO20 0x022C 0x04F4 0x0000 0x5 0x0 -#define MX6SLL_PAD_SD3_DATA1__JTAG_DE_B 0x022C 0x04F4 0x0000 0x6 0x0 -#define MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x0230 0x04F8 0x0000 0x0 0x0 -#define MX6SLL_PAD_SD3_DATA2__AUD5_TXFS 0x0230 0x04F8 0x0590 0x1 0x0 -#define MX6SLL_PAD_SD3_DATA2__KEY_COL7 0x0230 0x04F8 0x069C 0x2 0x0 -#define MX6SLL_PAD_SD3_DATA2__CSI_DATA14 0x0230 0x04F8 0x05C0 0x3 0x0 -#define MX6SLL_PAD_SD3_DATA2__EPIT1_OUT 0x0230 0x04F8 0x0000 0x4 0x0 -#define MX6SLL_PAD_SD3_DATA2__GPIO5_IO16 0x0230 0x04F8 0x0000 0x5 0x0 -#define MX6SLL_PAD_SD3_DATA2__USB_OTG2_OC 0x0230 0x04F8 0x0768 0x6 0x0 -#define MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x0234 0x04FC 0x0000 0x0 0x0 -#define MX6SLL_PAD_SD3_DATA3__AUD5_TXD 0x0234 0x04FC 0x0580 0x1 0x0 -#define MX6SLL_PAD_SD3_DATA3__KEY_ROW7 0x0234 0x04FC 0x06BC 0x2 0x0 -#define MX6SLL_PAD_SD3_DATA3__CSI_DATA15 0x0234 0x04FC 0x05C4 0x3 0x0 -#define MX6SLL_PAD_SD3_DATA3__EPIT2_OUT 0x0234 0x04FC 0x0000 0x4 0x0 -#define MX6SLL_PAD_SD3_DATA3__GPIO5_IO17 0x0234 0x04FC 0x0000 0x5 0x0 -#define MX6SLL_PAD_SD3_DATA3__USB_OTG1_OC 0x0234 0x04FC 0x076C 0x6 0x0 -#define MX6SLL_PAD_GPIO4_IO20__SD1_STROBE 0x0238 0x0500 0x0000 0x0 0x0 -#define MX6SLL_PAD_GPIO4_IO20__AUD6_RXFS 0x0238 0x0500 0x05A0 0x2 0x0 -#define MX6SLL_PAD_GPIO4_IO20__ECSPI4_SS0 0x0238 0x0500 0x065C 0x3 0x0 -#define MX6SLL_PAD_GPIO4_IO20__GPT_CAPTURE1 0x0238 0x0500 0x0670 0x4 0x0 -#define MX6SLL_PAD_GPIO4_IO20__GPIO4_IO20 0x0238 0x0500 0x0000 0x5 0x0 -#define MX6SLL_PAD_GPIO4_IO21__SD2_STROBE 0x023C 0x0504 0x0000 0x0 0x0 -#define MX6SLL_PAD_GPIO4_IO21__AUD6_RXC 0x023C 0x0504 0x059C 0x2 0x0 -#define MX6SLL_PAD_GPIO4_IO21__ECSPI4_SCLK 0x023C 0x0504 0x0650 0x3 0x0 -#define MX6SLL_PAD_GPIO4_IO21__GPT_CAPTURE2 0x023C 0x0504 0x0674 0x4 0x0 -#define MX6SLL_PAD_GPIO4_IO21__GPIO4_IO21 0x023C 0x0504 0x0000 0x5 0x0 -#define MX6SLL_PAD_GPIO4_IO19__SD3_STROBE 0x0240 0x0508 0x0000 0x0 0x0 -#define MX6SLL_PAD_GPIO4_IO19__AUD6_RXD 0x0240 0x0508 0x0594 0x2 0x0 -#define MX6SLL_PAD_GPIO4_IO19__ECSPI4_MOSI 0x0240 0x0508 0x0658 0x3 0x0 -#define MX6SLL_PAD_GPIO4_IO19__GPT_COMPARE1 0x0240 0x0508 0x0000 0x4 0x0 -#define MX6SLL_PAD_GPIO4_IO19__GPIO4_IO19 0x0240 0x0508 0x0000 0x5 0x0 -#define MX6SLL_PAD_GPIO4_IO25__AUD6_TXC 0x0244 0x050C 0x05A4 0x2 0x0 -#define MX6SLL_PAD_GPIO4_IO25__ECSPI4_MISO 0x0244 0x050C 0x0654 0x3 0x0 -#define MX6SLL_PAD_GPIO4_IO25__GPT_COMPARE2 0x0244 0x050C 0x0000 0x4 0x0 -#define MX6SLL_PAD_GPIO4_IO25__GPIO4_IO25 0x0244 0x050C 0x0000 0x5 0x0 -#define MX6SLL_PAD_GPIO4_IO18__AUD6_TXFS 0x0248 0x0510 0x05A8 0x2 0x0 -#define MX6SLL_PAD_GPIO4_IO18__ECSPI4_SS1 0x0248 0x0510 0x0660 0x3 0x0 -#define MX6SLL_PAD_GPIO4_IO18__GPT_COMPARE3 0x0248 0x0510 0x0000 0x4 0x0 -#define MX6SLL_PAD_GPIO4_IO18__GPIO4_IO18 0x0248 0x0510 0x0000 0x5 0x0 -#define MX6SLL_PAD_GPIO4_IO24__AUD6_TXD 0x024C 0x0514 0x0598 0x2 0x0 -#define MX6SLL_PAD_GPIO4_IO24__ECSPI4_SS2 0x024C 0x0514 0x0664 0x3 0x0 -#define MX6SLL_PAD_GPIO4_IO24__GPT_CLKIN 0x024C 0x0514 0x0678 0x4 0x0 -#define MX6SLL_PAD_GPIO4_IO24__GPIO4_IO24 0x024C 0x0514 0x0000 0x5 0x0 -#define MX6SLL_PAD_GPIO4_IO23__AUDIO_CLK_OUT 0x0250 0x0518 0x0000 0x2 0x0 -#define MX6SLL_PAD_GPIO4_IO23__SD1_RESET 0x0250 0x0518 0x0000 0x3 0x0 -#define MX6SLL_PAD_GPIO4_IO23__SD3_RESET 0x0250 0x0518 0x0000 0x4 0x0 -#define MX6SLL_PAD_GPIO4_IO23__GPIO4_IO23 0x0250 0x0518 0x0000 0x5 0x0 -#define MX6SLL_PAD_GPIO4_IO17__USB_OTG1_ID 0x0254 0x051C 0x055C 0x2 0x2 -#define MX6SLL_PAD_GPIO4_IO17__SD1_VSELECT 0x0254 0x051C 0x0000 0x3 0x0 -#define MX6SLL_PAD_GPIO4_IO17__SD3_VSELECT 0x0254 0x051C 0x0000 0x4 0x0 -#define MX6SLL_PAD_GPIO4_IO17__GPIO4_IO17 0x0254 0x051C 0x0000 0x5 0x0 -#define MX6SLL_PAD_GPIO4_IO22__SPDIF_IN 0x0258 0x0520 0x0738 0x2 0x0 -#define MX6SLL_PAD_GPIO4_IO22__SD1_WP 0x0258 0x0520 0x0774 0x3 0x0 -#define MX6SLL_PAD_GPIO4_IO22__SD3_WP 0x0258 0x0520 0x0794 0x4 0x1 -#define MX6SLL_PAD_GPIO4_IO22__GPIO4_IO22 0x0258 0x0520 0x0000 0x5 0x0 -#define MX6SLL_PAD_GPIO4_IO16__SPDIF_OUT 0x025C 0x0524 0x0000 0x2 0x0 -#define MX6SLL_PAD_GPIO4_IO16__SD1_CD_B 0x025C 0x0524 0x0770 0x3 0x0 -#define MX6SLL_PAD_GPIO4_IO16__SD3_CD_B 0x025C 0x0524 0x0780 0x4 0x1 -#define MX6SLL_PAD_GPIO4_IO16__GPIO4_IO16 0x025C 0x0524 0x0000 0x5 0x0 -#define MX6SLL_PAD_GPIO4_IO26__WDOG1_B 0x0260 0x0528 0x0000 0x2 0x0 -#define MX6SLL_PAD_GPIO4_IO26__PWM4_OUT 0x0260 0x0528 0x0000 0x3 0x0 -#define MX6SLL_PAD_GPIO4_IO26__CCM_PMIC_READY 0x0260 0x0528 0x05AC 0x4 0x1 -#define MX6SLL_PAD_GPIO4_IO26__GPIO4_IO26 0x0260 0x0528 0x0000 0x5 0x0 -#define MX6SLL_PAD_GPIO4_IO26__SPDIF_EXT_CLK 0x0260 0x0528 0x073C 0x6 0x0 - -#endif /* __DTS_IMX6SLL_PINFUNC_H */ diff --git a/sys/gnu/dts/arm/imx6sll.dtsi b/sys/gnu/dts/arm/imx6sll.dtsi deleted file mode 100644 index a1bc5bb3175..00000000000 --- a/sys/gnu/dts/arm/imx6sll.dtsi +++ /dev/null @@ -1,823 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright 2016 Freescale Semiconductor, Inc. - * Copyright 2017-2018 NXP. - * - */ - -#include -#include -#include -#include "imx6sll-pinfunc.h" - -/ { - #address-cells = <1>; - #size-cells = <1>; - - aliases { - gpio0 = &gpio1; - gpio1 = &gpio2; - gpio2 = &gpio3; - gpio3 = &gpio4; - gpio4 = &gpio5; - gpio5 = &gpio6; - i2c0 = &i2c1; - i2c1 = &i2c2; - i2c2 = &i2c3; - mmc0 = &usdhc1; - mmc1 = &usdhc2; - mmc2 = &usdhc3; - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - serial3 = &uart4; - serial4 = &uart5; - spi0 = &ecspi1; - spi1 = &ecspi2; - spi3 = &ecspi3; - spi4 = &ecspi4; - usbphy0 = &usbphy1; - usbphy1 = &usbphy2; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - reg = <0>; - next-level-cache = <&L2>; - operating-points = < - /* kHz uV */ - 996000 1275000 - 792000 1175000 - 396000 1075000 - 198000 975000 - >; - fsl,soc-operating-points = < - /* ARM kHz SOC-PU uV */ - 996000 1175000 - 792000 1175000 - 396000 1175000 - 198000 1175000 - >; - clock-latency = <61036>; /* two CLK32 periods */ - #cooling-cells = <2>; - clocks = <&clks IMX6SLL_CLK_ARM>, - <&clks IMX6SLL_CLK_PLL2_PFD2>, - <&clks IMX6SLL_CLK_STEP>, - <&clks IMX6SLL_CLK_PLL1_SW>, - <&clks IMX6SLL_CLK_PLL1_SYS>; - clock-names = "arm", "pll2_pfd2_396m", "step", - "pll1_sw", "pll1_sys"; - }; - }; - - ckil: clock-ckil { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "ckil"; - }; - - osc: clock-osc-24m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "osc"; - }; - - ipp_di0: clock-ipp-di0 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - clock-output-names = "ipp_di0"; - }; - - ipp_di1: clock-ipp-di1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - clock-output-names = "ipp_di1"; - }; - - tempmon: temperature-sensor { - compatible = "fsl,imx6sll-tempmon", "fsl,imx6sx-tempmon"; - interrupts = ; - interrupt-parent = <&gpc>; - fsl,tempmon = <&anatop>; - nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>; - nvmem-cell-names = "calib", "temp_grade"; - clocks = <&clks IMX6SLL_CLK_PLL3_USB_OTG>; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&gpc>; - ranges; - - ocram: sram@900000 { - compatible = "mmio-sram"; - reg = <0x00900000 0x20000>; - }; - - intc: interrupt-controller@a01000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x00a01000 0x1000>, - <0x00a00100 0x100>; - interrupt-parent = <&intc>; - }; - - L2: l2-cache@a02000 { - compatible = "arm,pl310-cache"; - reg = <0x00a02000 0x1000>; - interrupts = ; - cache-unified; - cache-level = <2>; - arm,tag-latency = <4 2 3>; - arm,data-latency = <4 2 3>; - }; - - aips1: aips-bus@2000000 { - compatible = "fsl,aips-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x02000000 0x100000>; - ranges; - - spba: spba-bus@2000000 { - compatible = "fsl,spba-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x02000000 0x40000>; - ranges; - - spdif: spdif@2004000 { - compatible = "fsl,imx6sl-spdif", "fsl,imx35-spdif"; - reg = <0x02004000 0x4000>; - interrupts = ; - dmas = <&sdma 14 18 0>, <&sdma 15 18 0>; - dma-names = "rx", "tx"; - clocks = <&clks IMX6SLL_CLK_SPDIF_GCLK>, - <&clks IMX6SLL_CLK_OSC>, - <&clks IMX6SLL_CLK_SPDIF>, - <&clks IMX6SLL_CLK_DUMMY>, - <&clks IMX6SLL_CLK_DUMMY>, - <&clks IMX6SLL_CLK_DUMMY>, - <&clks IMX6SLL_CLK_IPG>, - <&clks IMX6SLL_CLK_DUMMY>, - <&clks IMX6SLL_CLK_DUMMY>, - <&clks IMX6SLL_CLK_SPBA>; - clock-names = "core", "rxtx0", - "rxtx1", "rxtx2", - "rxtx3", "rxtx4", - "rxtx5", "rxtx6", - "rxtx7", "dma"; - status = "disabled"; - }; - - ecspi1: spi@2008000 { - compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; - reg = <0x02008000 0x4000>; - interrupts = ; - dmas = <&sdma 3 7 1>, <&sdma 4 7 2>; - dma-names = "rx", "tx"; - clocks = <&clks IMX6SLL_CLK_ECSPI1>, - <&clks IMX6SLL_CLK_ECSPI1>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - ecspi2: spi@200c000 { - compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; - reg = <0x0200c000 0x4000>; - interrupts = ; - dmas = <&sdma 5 7 1>, <&sdma 6 7 2>; - dma-names = "rx", "tx"; - clocks = <&clks IMX6SLL_CLK_ECSPI2>, - <&clks IMX6SLL_CLK_ECSPI2>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - ecspi3: spi@2010000 { - compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; - reg = <0x02010000 0x4000>; - interrupts = ; - dmas = <&sdma 7 7 1>, <&sdma 8 7 2>; - dma-names = "rx", "tx"; - clocks = <&clks IMX6SLL_CLK_ECSPI3>, - <&clks IMX6SLL_CLK_ECSPI3>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - ecspi4: spi@2014000 { - compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; - reg = <0x02014000 0x4000>; - interrupts = ; - dmas = <&sdma 9 7 1>, <&sdma 10 7 2>; - dma-names = "rx", "tx"; - clocks = <&clks IMX6SLL_CLK_ECSPI4>, - <&clks IMX6SLL_CLK_ECSPI4>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart4: serial@2018000 { - compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart", - "fsl,imx21-uart"; - reg = <0x02018000 0x4000>; - interrupts = ; - dmas = <&sdma 31 4 0>, <&sdma 32 4 0>; - dma-names = "rx", "tx"; - clocks = <&clks IMX6SLL_CLK_UART4_IPG>, - <&clks IMX6SLL_CLK_UART4_SERIAL>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart1: serial@2020000 { - compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart", - "fsl,imx21-uart"; - reg = <0x02020000 0x4000>; - interrupts = ; - dmas = <&sdma 25 4 0>, <&sdma 26 4 0>; - dma-names = "rx", "tx"; - clocks = <&clks IMX6SLL_CLK_UART1_IPG>, - <&clks IMX6SLL_CLK_UART1_SERIAL>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart2: serial@2024000 { - compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart", - "fsl,imx21-uart"; - reg = <0x02024000 0x4000>; - interrupts = ; - dmas = <&sdma 27 4 0>, <&sdma 28 4 0>; - dma-names = "rx", "tx"; - clocks = <&clks IMX6SLL_CLK_UART2_IPG>, - <&clks IMX6SLL_CLK_UART2_SERIAL>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - ssi1: ssi-controller@2028000 { - compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi"; - reg = <0x02028000 0x4000>; - interrupts = ; - dmas = <&sdma 37 22 0>, <&sdma 38 22 0>; - dma-names = "rx", "tx"; - fsl,fifo-depth = <15>; - clocks = <&clks IMX6SLL_CLK_SSI1_IPG>, - <&clks IMX6SLL_CLK_SSI1>; - clock-names = "ipg", "baud"; - status = "disabled"; - }; - - ssi2: ssi-controller@202c000 { - compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi"; - reg = <0x0202c000 0x4000>; - interrupts = ; - dmas = <&sdma 41 22 0>, <&sdma 42 22 0>; - dma-names = "rx", "tx"; - fsl,fifo-depth = <15>; - clocks = <&clks IMX6SLL_CLK_SSI2_IPG>, - <&clks IMX6SLL_CLK_SSI2>; - clock-names = "ipg", "baud"; - status = "disabled"; - }; - - ssi3: ssi-controller@2030000 { - compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi"; - reg = <0x02030000 0x4000>; - interrupts = ; - dmas = <&sdma 45 22 0>, <&sdma 46 22 0>; - dma-names = "rx", "tx"; - fsl,fifo-depth = <15>; - clocks = <&clks IMX6SLL_CLK_SSI3_IPG>, - <&clks IMX6SLL_CLK_SSI3>; - clock-names = "ipg", "baud"; - status = "disabled"; - }; - - uart3: serial@2034000 { - compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart", - "fsl,imx21-uart"; - reg = <0x02034000 0x4000>; - interrupts = ; - dmas = <&sdma 29 4 0>, <&sdma 30 4 0>; - dma-name = "rx", "tx"; - clocks = <&clks IMX6SLL_CLK_UART3_IPG>, - <&clks IMX6SLL_CLK_UART3_SERIAL>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - }; - - pwm1: pwm@2080000 { - compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm"; - reg = <0x02080000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SLL_CLK_PWM1>, - <&clks IMX6SLL_CLK_PWM1>; - clock-names = "ipg", "per"; - #pwm-cells = <2>; - }; - - pwm2: pwm@2084000 { - compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm"; - reg = <0x02084000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SLL_CLK_PWM2>, - <&clks IMX6SLL_CLK_PWM2>; - clock-names = "ipg", "per"; - #pwm-cells = <2>; - }; - - pwm3: pwm@2088000 { - compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm"; - reg = <0x02088000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SLL_CLK_PWM3>, - <&clks IMX6SLL_CLK_PWM3>; - clock-names = "ipg", "per"; - #pwm-cells = <2>; - }; - - pwm4: pwm@208c000 { - compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm"; - reg = <0x0208c000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SLL_CLK_PWM4>, - <&clks IMX6SLL_CLK_PWM4>; - clock-names = "ipg", "per"; - #pwm-cells = <2>; - }; - - gpt1: timer@2098000 { - compatible = "fsl,imx6sl-gpt"; - reg = <0x02098000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SLL_CLK_GPT_BUS>, - <&clks IMX6SLL_CLK_GPT_SERIAL>; - clock-names = "ipg", "per"; - }; - - gpio1: gpio@209c000 { - compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio"; - reg = <0x0209c000 0x4000>; - interrupts = , - ; - clocks = <&clks IMX6SLL_CLK_GPIO1>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 94 7>, <&iomuxc 7 25 25>; - }; - - gpio2: gpio@20a0000 { - compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio"; - reg = <0x020a0000 0x4000>; - interrupts = , - ; - clocks = <&clks IMX6SLL_CLK_GPIO2>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 50 32>; - }; - - gpio3: gpio@20a4000 { - compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio"; - reg = <0x020a4000 0x4000>; - interrupts = , - ; - clocks = <&clks IMX6SLL_CLK_GPIO3>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 82 12>, <&iomuxc 12 103 4>, - <&iomuxc 16 101 2>, <&iomuxc 18 5 1>, - <&iomuxc 21 6 11>; - }; - - gpio4: gpio@20a8000 { - compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio"; - reg = <0x020a8000 0x4000>; - interrupts = , - ; - clocks = <&clks IMX6SLL_CLK_GPIO4>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 17 8>, <&iomuxc 8 107 8>, - <&iomuxc 16 151 1>, <&iomuxc 17 149 1>, - <&iomuxc 18 146 1>, <&iomuxc 19 144 1>, - <&iomuxc 20 142 1>, <&iomuxc 21 143 1>, - <&iomuxc 22 150 1>, <&iomuxc 23 148 1>, - <&iomuxc 24 147 1>, <&iomuxc 25 145 1>, - <&iomuxc 26 152 1>, <&iomuxc 27 125 1>, - <&iomuxc 28 131 1>, <&iomuxc 29 134 1>, - <&iomuxc 30 129 1>, <&iomuxc 31 133 1>; - }; - - gpio5: gpio@20ac000 { - compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio"; - reg = <0x020ac000 0x4000>; - interrupts = , - ; - clocks = <&clks IMX6SLL_CLK_GPIO5>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 135 1>, <&iomuxc 1 128 1>, - <&iomuxc 2 132 1>, <&iomuxc 3 130 1>, - <&iomuxc 4 127 1>, <&iomuxc 5 126 1>, - <&iomuxc 6 120 1>, <&iomuxc 7 123 1>, - <&iomuxc 8 118 1>, <&iomuxc 9 122 1>, - <&iomuxc 10 124 1>, <&iomuxc 11 117 1>, - <&iomuxc 12 121 1>, <&iomuxc 13 119 1>, - <&iomuxc 14 116 1>, <&iomuxc 15 115 1>, - <&iomuxc 16 140 2>, <&iomuxc 18 136 1>, - <&iomuxc 19 138 1>, <&iomuxc 20 139 1>, - <&iomuxc 21 137 1>; - }; - - gpio6: gpio@20b0000 { - compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio"; - reg = <0x020b0000 0x4000>; - interrupts = , - ; - clocks = <&clks IMX6SLL_CLK_GPIO6>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - kpp: keypad@20b8000 { - compatible = "fsl,imx6sll-kpp", "fsl,imx21-kpp"; - reg = <0x020b8000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SLL_CLK_KPP>; - status = "disabled"; - }; - - wdog1: watchdog@20bc000 { - compatible = "fsl,imx6sll-wdt", "fsl,imx21-wdt"; - reg = <0x020bc000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SLL_CLK_WDOG1>; - }; - - wdog2: watchdog@20c0000 { - compatible = "fsl,imx6sll-wdt", "fsl,imx21-wdt"; - reg = <0x020c0000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SLL_CLK_WDOG2>; - status = "disabled"; - }; - - clks: clock-controller@20c4000 { - compatible = "fsl,imx6sll-ccm"; - reg = <0x020c4000 0x4000>; - interrupts = , - ; - #clock-cells = <1>; - clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>; - clock-names = "ckil", "osc", "ipp_di0", "ipp_di1"; - - assigned-clocks = <&clks IMX6SLL_CLK_PERCLK_SEL>; - assigned-clock-parents = <&clks IMX6SLL_CLK_OSC>; - }; - - anatop: anatop@20c8000 { - compatible = "fsl,imx6sll-anatop", - "fsl,imx6q-anatop", - "syscon", "simple-mfd"; - reg = <0x020c8000 0x4000>; - interrupts = , - , - ; - #address-cells = <1>; - #size-cells = <0>; - - reg_3p0: regulator-3p0@20c8120 { - compatible = "fsl,anatop-regulator"; - reg = <0x20c8120>; - regulator-name = "vdd3p0"; - regulator-min-microvolt = <2625000>; - regulator-max-microvolt = <3400000>; - anatop-reg-offset = <0x120>; - anatop-vol-bit-shift = <8>; - anatop-vol-bit-width = <5>; - anatop-min-bit-val = <0>; - anatop-min-voltage = <2625000>; - anatop-max-voltage = <3400000>; - anatop-enable-bit = <0>; - }; - }; - - usbphy1: usb-phy@20c9000 { - compatible = "fsl,imx6sll-usbphy", "fsl,imx6ul-usbphy", - "fsl,imx23-usbphy"; - reg = <0x020c9000 0x1000>; - interrupts = ; - clocks = <&clks IMX6SLL_CLK_USBPHY1>; - phy-3p0-supply = <®_3p0>; - fsl,anatop = <&anatop>; - }; - - usbphy2: usb-phy@20ca000 { - compatible = "fsl,imx6sll-usbphy", "fsl,imx6ul-usbphy", - "fsl,imx23-usbphy"; - reg = <0x020ca000 0x1000>; - interrupts = ; - clocks = <&clks IMX6SLL_CLK_USBPHY2>; - phy-reg_3p0-supply = <®_3p0>; - fsl,anatop = <&anatop>; - }; - - snvs: snvs@20cc000 { - compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; - reg = <0x020cc000 0x4000>; - - snvs_rtc: snvs-rtc-lp { - compatible = "fsl,sec-v4.0-mon-rtc-lp"; - regmap = <&snvs>; - offset = <0x34>; - interrupts = , - ; - }; - - snvs_poweroff: snvs-poweroff { - compatible = "syscon-poweroff"; - regmap = <&snvs>; - offset = <0x38>; - mask = <0x61>; - status = "disabled"; - }; - - snvs_pwrkey: snvs-powerkey { - compatible = "fsl,sec-v4.0-pwrkey"; - regmap = <&snvs>; - interrupts = ; - linux,keycode = ; - wakeup-source; - status = "disabled"; - }; - }; - - src: reset-controller@20d8000 { - compatible = "fsl,imx6sll-src", "fsl,imx51-src"; - reg = <0x020d8000 0x4000>; - interrupts = , - ; - #reset-cells = <1>; - }; - - gpc: interrupt-controller@20dc000 { - compatible = "fsl,imx6sll-gpc", "fsl,imx6q-gpc"; - reg = <0x020dc000 0x4000>; - interrupt-controller; - #interrupt-cells = <3>; - interrupts = ; - interrupt-parent = <&intc>; - }; - - iomuxc: pinctrl@20e0000 { - compatible = "fsl,imx6sll-iomuxc"; - reg = <0x020e0000 0x4000>; - }; - - gpr: iomuxc-gpr@20e4000 { - compatible = "fsl,imx6sll-iomuxc-gpr", - "fsl,imx6q-iomuxc-gpr", "syscon"; - reg = <0x020e4000 0x4000>; - }; - - csi: csi@20e8000 { - compatible = "fsl,imx6sll-csi", "fsl,imx6s-csi"; - reg = <0x020e8000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SLL_CLK_DUMMY>, - <&clks IMX6SLL_CLK_CSI>, - <&clks IMX6SLL_CLK_DUMMY>; - clock-names = "disp-axi", "csi_mclk", "disp_dcic"; - status = "disabled"; - }; - - sdma: dma-controller@20ec000 { - compatible = "fsl,imx6sll-sdma", "fsl,imx6ul-sdma"; - reg = <0x020ec000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SLL_CLK_IPG>, - <&clks IMX6SLL_CLK_SDMA>; - clock-names = "ipg", "ahb"; - #dma-cells = <3>; - iram = <&ocram>; - fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; - }; - - pxp: pxp@20f0000 { - compatible = "fsl,imx6sll-pxp", "fsl,imx6ull-pxp"; - reg = <0x20f0000 0x4000>; - interrupts = , - ; - clocks = <&clks IMX6SLL_CLK_PXP>; - clock-names = "axi"; - }; - - lcdif: lcd-controller@20f8000 { - compatible = "fsl,imx6sll-lcdif", "fsl,imx28-lcdif"; - reg = <0x020f8000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SLL_CLK_LCDIF_PIX>, - <&clks IMX6SLL_CLK_LCDIF_APB>, - <&clks IMX6SLL_CLK_DUMMY>; - clock-names = "pix", "axi", "disp_axi"; - status = "disabled"; - }; - - dcp: dcp@20fc000 { - compatible = "fsl,imx28-dcp"; - reg = <0x020fc000 0x4000>; - interrupts = , - , - ; - clocks = <&clks IMX6SLL_CLK_DCP>; - clock-names = "dcp"; - }; - }; - - aips2: aips-bus@2100000 { - compatible = "fsl,aips-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x02100000 0x100000>; - ranges; - - usbotg1: usb@2184000 { - compatible = "fsl,imx6sll-usb", "fsl,imx6ul-usb", - "fsl,imx27-usb"; - reg = <0x02184000 0x200>; - interrupts = ; - clocks = <&clks IMX6SLL_CLK_USBOH3>; - fsl,usbphy = <&usbphy1>; - fsl,usbmisc = <&usbmisc 0>; - fsl,anatop = <&anatop>; - ahb-burst-config = <0x0>; - tx-burst-size-dword = <0x10>; - rx-burst-size-dword = <0x10>; - status = "disabled"; - }; - - usbotg2: usb@2184200 { - compatible = "fsl,imx6sll-usb", "fsl,imx6ul-usb", - "fsl,imx27-usb"; - reg = <0x02184200 0x200>; - interrupts = ; - clocks = <&clks IMX6SLL_CLK_USBOH3>; - fsl,usbphy = <&usbphy2>; - fsl,usbmisc = <&usbmisc 1>; - ahb-burst-config = <0x0>; - tx-burst-size-dword = <0x10>; - rx-burst-size-dword = <0x10>; - status = "disabled"; - }; - - usbmisc: usbmisc@2184800 { - #index-cells = <1>; - compatible = "fsl,imx6sll-usbmisc", "fsl,imx6ul-usbmisc", - "fsl,imx6q-usbmisc"; - reg = <0x02184800 0x200>; - }; - - usdhc1: mmc@2190000 { - compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc"; - reg = <0x02190000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SLL_CLK_USDHC1>, - <&clks IMX6SLL_CLK_USDHC1>, - <&clks IMX6SLL_CLK_USDHC1>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - fsl,tuning-step = <2>; - fsl,tuning-start-tap = <20>; - status = "disabled"; - }; - - usdhc2: mmc@2194000 { - compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc"; - reg = <0x02194000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SLL_CLK_USDHC2>, - <&clks IMX6SLL_CLK_USDHC2>, - <&clks IMX6SLL_CLK_USDHC2>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - fsl,tuning-step = <2>; - fsl,tuning-start-tap = <20>; - status = "disabled"; - }; - - usdhc3: mmc@2198000 { - compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc"; - reg = <0x02198000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SLL_CLK_USDHC3>, - <&clks IMX6SLL_CLK_USDHC3>, - <&clks IMX6SLL_CLK_USDHC3>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - fsl,tuning-step = <2>; - fsl,tuning-start-tap = <20>; - status = "disabled"; - }; - - i2c1: i2c@21a0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6sll-i2c", "fsl,imx21-i2c"; - reg = <0x021a0000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SLL_CLK_I2C1>; - status = "disabled"; - }; - - i2c2: i2c@21a4000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6sll-i2c", "fsl,imx21-i2c"; - reg = <0x021a4000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SLL_CLK_I2C2>; - status = "disabled"; - }; - - i2c3: i2c@21a8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6sll-i2c", "fsl,imx21-i2c"; - reg = <0x021a8000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SLL_CLK_I2C3>; - status = "disabled"; - }; - - mmdc: memory-controller@21b0000 { - compatible = "fsl,imx6sll-mmdc", "fsl,imx6q-mmdc"; - reg = <0x021b0000 0x4000>; - clocks = <&clks IMX6SLL_CLK_MMDC_P0_IPG>; - }; - - ocotp: ocotp-ctrl@21bc000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "fsl,imx6sll-ocotp", "syscon"; - reg = <0x021bc000 0x4000>; - clocks = <&clks IMX6SLL_CLK_OCOTP>; - - tempmon_calib: calib@38 { - reg = <0x38 4>; - }; - - tempmon_temp_grade: temp-grade@20 { - reg = <0x20 4>; - }; - }; - - audmux: audmux@21d8000 { - compatible = "fsl,imx6sll-audmux", "fsl,imx31-audmux"; - reg = <0x021d8000 0x4000>; - status = "disabled"; - }; - - uart5: serial@21f4000 { - compatible = "fsl,imx6sll-uart", "fsl,imx6q-uart", - "fsl,imx21-uart"; - reg = <0x021f4000 0x4000>; - interrupts = ; - dmas = <&sdma 33 4 0>, <&sdma 34 4 0>; - dma-names = "rx", "tx"; - clocks = <&clks IMX6SLL_CLK_UART5_IPG>, - <&clks IMX6SLL_CLK_UART5_SERIAL>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/imx6sx-nitrogen6sx.dts b/sys/gnu/dts/arm/imx6sx-nitrogen6sx.dts deleted file mode 100644 index 832b5c5d744..00000000000 --- a/sys/gnu/dts/arm/imx6sx-nitrogen6sx.dts +++ /dev/null @@ -1,602 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR X11 -/* - * Copyright (C) 2016 Boundary Devices, Inc. - */ - -/dts-v1/; - -#include "imx6sx.dtsi" - -/ { - model = "Boundary Devices i.MX6 SoloX Nitrogen6sx Board"; - compatible = "boundary,imx6sx-nitrogen6sx", "fsl,imx6sx"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x40000000>; - }; - - backlight-lvds { - compatible = "pwm-backlight"; - pwms = <&pwm4 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - power-supply = <®_3p3v>; - }; - - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-name = "1P8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_can1_3v3: regulator-can1-3v3 { - compatible = "regulator-fixed"; - regulator-name = "can1-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio4 27 GPIO_ACTIVE_LOW>; - }; - - reg_can2_3v3: regulator-can2-3v3 { - compatible = "regulator-fixed"; - regulator-name = "can2-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio4 24 GPIO_ACTIVE_LOW>; - }; - - reg_usb_otg1_vbus: regulator-usb-otg1-vbus { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg1_vbus>; - compatible = "regulator-fixed"; - regulator-name = "usb_otg1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_wlan: regulator-wlan { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_wlan>; - compatible = "regulator-fixed"; - clocks = <&clks IMX6SX_CLK_CKO>; - clock-names = "slow"; - regulator-name = "wlan-en"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <70000>; - gpio = <&gpio7 6 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - sound { - compatible = "fsl,imx-audio-sgtl5000"; - model = "imx6sx-nitrogen6sx-sgtl5000"; - cpu-dai = <&ssi1>; - audio-codec = <&codec>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - mux-int-port = <1>; - mux-ext-port = <5>; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; - -&ecspi1 { - cs-gpios = <&gpio2 16 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - status = "okay"; - - flash: m25p80@0 { - compatible = "microchip,sst25vf016b"; - spi-max-frequency = <20000000>; - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "U-Boot"; - reg = <0x0 0xc0000>; - read-only; - }; - - partition@c0000 { - label = "env"; - reg = <0xc0000 0x2000>; - read-only; - }; - - partition@c2000 { - label = "Kernel"; - reg = <0xc2000 0x11e000>; - }; - - partition@1e0000 { - label = "M4"; - reg = <0x1e0000 0x20000>; - }; - }; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet1>; - phy-mode = "rgmii"; - phy-handle = <ðphy1>; - phy-supply = <®_3p3v>; - fsl,magic-packet; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy1: ethernet-phy@4 { - reg = <4>; - }; - - ethphy2: ethernet-phy@5 { - reg = <5>; - }; - }; -}; - -&fec2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet2>; - phy-mode = "rgmii"; - phy-handle = <ðphy2>; - phy-supply = <®_3p3v>; - fsl,magic-packet; - status = "okay"; -}; - -&flexcan1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - xceiver-supply = <®_can1_3v3>; - status = "okay"; -}; - -&flexcan2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - xceiver-supply = <®_can2_3v3>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - codec: sgtl5000@a { - compatible = "fsl,sgtl5000"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sgtl5000>; - reg = <0x0a>; - clocks = <&clks IMX6SX_CLK_CKO2>; - VDDA-supply = <®_1p8v>; - VDDIO-supply = <®_1p8v>; - VDDD-supply = <®_1p8v>; - assigned-clocks = <&clks IMX6SX_CLK_CKO2_SEL>, - <&clks IMX6SX_CLK_CKO2>; - assigned-clock-parents = <&clks IMX6SX_CLK_OSC>; - assigned-clock-rates = <0>, <24000000>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio4 10 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&pwm4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm4>; - status = "okay"; -}; - -&ssi1 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - uart-has-rtscts; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - status = "okay"; -}; - -&usbotg1 { - vbus-supply = <®_usb_otg1_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg1>; - status = "okay"; -}; - -&usbotg2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg2>; - dr_mode = "host"; - disable-over-current; - reset-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - bus-width = <4>; - cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; - keep-power-in-suspend; - wakeup-source; - status = "okay"; -}; - -&usdhc3 { - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - bus-width = <4>; - non-removable; - keep-power-in-suspend; - vmmc-supply = <®_wlan>; - cap-power-off-card; - cap-sdio-irq; - status = "okay"; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - interrupt-parent = <&gpio7>; - interrupts = <7 IRQ_TYPE_LEVEL_LOW>; - }; - - wlcore: wlcore@2 { - compatible = "ti,wl1271"; - reg = <2>; - interrupt-parent = <&gpio7>; - interrupts = <7 IRQ_TYPE_LEVEL_LOW>; - ref-clock-frequency = <38400000>; - }; -}; - -&usdhc4 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc4_50mhz>; - pinctrl-1 = <&pinctrl_usdhc4_100mhz>; - pinctrl-2 = <&pinctrl_usdhc4_200mhz>; - bus-width = <8>; - non-removable; - vmmc-supply = <®_1p8v>; - keep-power-in-suspend; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6SX_PAD_SD1_DATA0__AUDMUX_AUD5_RXD 0x1b0b0 - MX6SX_PAD_SD1_DATA1__AUDMUX_AUD5_TXC 0x1b0b0 - MX6SX_PAD_SD1_DATA2__AUDMUX_AUD5_TXFS 0x1b0b0 - MX6SX_PAD_SD1_DATA3__AUDMUX_AUD5_TXD 0x1b0b0 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6SX_PAD_KEY_COL1__ECSPI1_MISO 0x100b1 - MX6SX_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1 - MX6SX_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1 - MX6SX_PAD_KEY_ROW1__GPIO2_IO_16 0x0b0b1 - >; - }; - - pinctrl_enet1: enet1grp { - fsl,pins = < - MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0x1b0b0 - MX6SX_PAD_ENET1_MDC__ENET1_MDC 0x1b0b0 - MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0x30b1 - MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0x30b1 - MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0x30b1 - MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0x30b1 - MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0x30b1 - MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0x30b1 - MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081 - MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081 - MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081 - MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081 - MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081 - MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x3081 - MX6SX_PAD_ENET2_CRS__GPIO2_IO_7 0xb0b0 - MX6SX_PAD_ENET1_RX_CLK__GPIO2_IO_4 0xb0b0 - MX6SX_PAD_ENET1_TX_CLK__GPIO2_IO_5 0xb0b0 - >; - }; - - pinctrl_enet2: enet2grp { - fsl,pins = < - MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0x30b1 - MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0x30b1 - MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0x30b1 - MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0x30b1 - MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0x30b1 - MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0x30b1 - MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x3081 - MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x3081 - MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x3081 - MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x3081 - MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x3081 - MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x3081 - MX6SX_PAD_ENET2_COL__GPIO2_IO_6 0xb0b0 - MX6SX_PAD_ENET2_RX_CLK__GPIO2_IO_8 0xb0b0 - MX6SX_PAD_ENET2_TX_CLK__GPIO2_IO_9 0xb0b0 - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x1b0b0 - MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x1b0b0 - MX6SX_PAD_QSPI1B_DATA3__GPIO4_IO_27 0x1b0b0 - MX6SX_PAD_QSPI1B_DATA3__GPIO4_IO_27 0x0b0b0 - >; - }; - - pinctrl_flexcan2: flexcan2grp { - fsl,pins = < - MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x1b0b0 - MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x1b0b0 - MX6SX_PAD_QSPI1B_DATA0__GPIO4_IO_24 0x0b0b0 - >; - }; - - pinctrl_hog: hoggrp { - fsl,pins = < - MX6SX_PAD_NAND_CE0_B__GPIO4_IO_1 0x1b0b0 - MX6SX_PAD_NAND_CLE__GPIO4_IO_3 0x1b0b0 - MX6SX_PAD_NAND_RE_B__GPIO4_IO_12 0x1b0b0 - MX6SX_PAD_NAND_WE_B__GPIO4_IO_14 0x1b0b0 - MX6SX_PAD_NAND_WP_B__GPIO4_IO_15 0x1b0b0 - MX6SX_PAD_NAND_READY_B__GPIO4_IO_13 0x1b0b0 - MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16 0x1b0b0 - MX6SX_PAD_QSPI1A_DATA1__GPIO4_IO_17 0x1b0b0 - MX6SX_PAD_QSPI1A_DATA2__GPIO4_IO_18 0x1b0b0 - MX6SX_PAD_QSPI1A_DATA3__GPIO4_IO_19 0x1b0b0 - MX6SX_PAD_SD1_CMD__CCM_CLKO1 0x000b0 - MX6SX_PAD_SD3_DATA5__GPIO7_IO_7 0x1b0b0 - /* Test points */ - MX6SX_PAD_NAND_DATA04__GPIO4_IO_8 0x1b0b0 - MX6SX_PAD_QSPI1B_DATA1__GPIO4_IO_25 0x1b0b0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x4001b8b1 - MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6SX_PAD_GPIO1_IO02__I2C2_SCL 0x4001b8b1 - MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1 - MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = < - MX6SX_PAD_NAND_DATA05__GPIO4_IO_9 0xb0b0 - MX6SX_PAD_NAND_DATA06__GPIO4_IO_10 0xb0b0 - MX6SX_PAD_NAND_DATA07__GPIO4_IO_11 0xb0b0 - >; - }; - - pinctrl_pwm4: pwm4grp { - fsl,pins = < - MX6SX_PAD_GPIO1_IO13__PWM4_OUT 0x110b0 - >; - }; - - pinctrl_reg_wlan: reg-wlangrp { - fsl,pins = < - MX6SX_PAD_SD3_DATA4__GPIO7_IO_6 0x1b0b0 - MX6SX_PAD_GPIO1_IO11__CCM_CLKO1 0x000b0 - >; - }; - - pinctrl_sgtl5000: sgtl5000grp { - fsl,pins = < - MX6SX_PAD_GPIO1_IO12__CCM_CLKO2 0x000b0 - MX6SX_PAD_ENET1_COL__GPIO2_IO_0 0x1b0b0 - MX6SX_PAD_ENET1_CRS__GPIO2_IO_1 0x1b0b0 - MX6SX_PAD_QSPI1A_SS0_B__GPIO4_IO_22 0xb0b0 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1 - MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6SX_PAD_GPIO1_IO06__UART2_TX 0x1b0b1 - MX6SX_PAD_GPIO1_IO07__UART2_RX 0x1b0b1 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6SX_PAD_QSPI1B_SS0_B__UART3_TX 0x1b0b1 - MX6SX_PAD_QSPI1B_SCLK__UART3_RX 0x1b0b1 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6SX_PAD_KEY_COL3__UART5_TX 0x1b0b1 - MX6SX_PAD_KEY_ROW3__UART5_RX 0x1b0b1 - MX6SX_PAD_SD3_DATA6__UART3_RTS_B 0x1b0b1 - MX6SX_PAD_SD3_DATA7__UART3_CTS_B 0x1b0b1 - >; - }; - - pinctrl_usbotg1: usbotg1grp { - fsl,pins = < - MX6SX_PAD_GPIO1_IO08__USB_OTG1_OC 0x1b0b0 - MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x170b1 - >; - }; - - pinctrl_usbotg1_vbus: usbotg1-vbusgrp { - fsl,pins = < - MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x1b0b0 - >; - }; - - pinctrl_usbotg2: usbotg2grp { - fsl,pins = < - MX6SX_PAD_QSPI1B_DATA2__GPIO4_IO_26 0xb0b0 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x17059 - MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x10059 - MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x17059 - MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x17059 - MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x17059 - MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x17059 - MX6SX_PAD_KEY_COL2__GPIO2_IO_12 0x1b0b0 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10071 - MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17071 - MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17071 - MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17071 - MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17071 - MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17071 - >; - }; - - pinctrl_usdhc4_50mhz: usdhc4-50mhzgrp { - fsl,pins = < - MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10071 - MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17071 - MX6SX_PAD_SD4_RESET_B__USDHC4_RESET_B 0x17071 - MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17071 - MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17071 - MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17071 - MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17071 - MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x17071 - MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x17071 - MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x17071 - MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x17071 - >; - }; - - pinctrl_usdhc4_100mhz: usdhc4-100mhzgrp { - fsl,pins = < - MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100b9 - MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170b9 - MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170b9 - MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170b9 - MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170b9 - MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170b9 - MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170b9 - MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170b9 - MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170b9 - MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170b9 - >; - }; - - pinctrl_usdhc4_200mhz: usdhc4-200mhzgrp { - fsl,pins = < - MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100f9 - MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170f9 - MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170f9 - MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170f9 - MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170f9 - MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170f9 - MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170f9 - MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170f9 - MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170f9 - MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170f9 - >; - }; -}; diff --git a/sys/gnu/dts/arm/imx6sx-pinfunc.h b/sys/gnu/dts/arm/imx6sx-pinfunc.h deleted file mode 100644 index aa194a2fdd5..00000000000 --- a/sys/gnu/dts/arm/imx6sx-pinfunc.h +++ /dev/null @@ -1,1554 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - */ - -#ifndef __DTS_IMX6SX_PINFUNC_H -#define __DTS_IMX6SX_PINFUNC_H - -/* - * The pin function ID is a tuple of - * - */ -#define MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x0014 0x035C 0x07A8 0x0 0x1 -#define MX6SX_PAD_GPIO1_IO00__USDHC1_VSELECT 0x0014 0x035C 0x0000 0x1 0x0 -#define MX6SX_PAD_GPIO1_IO00__SPDIF_LOCK 0x0014 0x035C 0x0000 0x2 0x0 -#define MX6SX_PAD_GPIO1_IO00__CCM_WAIT 0x0014 0x035C 0x0000 0x3 0x0 -#define MX6SX_PAD_GPIO1_IO00__WDOG1_WDOG_ANY 0x0014 0x035C 0x0000 0x4 0x0 -#define MX6SX_PAD_GPIO1_IO00__GPIO1_IO_0 0x0014 0x035C 0x0000 0x5 0x0 -#define MX6SX_PAD_GPIO1_IO00__SNVS_HP_WRAPPER_VIO_5 0x0014 0x035C 0x0000 0x6 0x0 -#define MX6SX_PAD_GPIO1_IO00__PHY_DTB_1 0x0014 0x035C 0x0000 0x7 0x0 -#define MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x0018 0x0360 0x07AC 0x0 0x1 -#define MX6SX_PAD_GPIO1_IO01__USDHC1_RESET_B 0x0018 0x0360 0x0000 0x1 0x0 -#define MX6SX_PAD_GPIO1_IO01__SPDIF_SR_CLK 0x0018 0x0360 0x0000 0x2 0x0 -#define MX6SX_PAD_GPIO1_IO01__CCM_STOP 0x0018 0x0360 0x0000 0x3 0x0 -#define MX6SX_PAD_GPIO1_IO01__WDOG3_WDOG_B 0x0018 0x0360 0x0000 0x4 0x0 -#define MX6SX_PAD_GPIO1_IO01__GPIO1_IO_1 0x0018 0x0360 0x0000 0x5 0x0 -#define MX6SX_PAD_GPIO1_IO01__SNVS_HP_WRAPPER_VIO_5_CTL 0x0018 0x0360 0x0000 0x6 0x0 -#define MX6SX_PAD_GPIO1_IO01__PHY_DTB_0 0x0018 0x0360 0x0000 0x7 0x0 -#define MX6SX_PAD_GPIO1_IO02__I2C2_SCL 0x001C 0x0364 0x07B0 0x0 0x1 -#define MX6SX_PAD_GPIO1_IO02__USDHC1_CD_B 0x001C 0x0364 0x0864 0x1 0x1 -#define MX6SX_PAD_GPIO1_IO02__CSI2_MCLK 0x001C 0x0364 0x0000 0x2 0x0 -#define MX6SX_PAD_GPIO1_IO02__CCM_DI0_EXT_CLK 0x001C 0x0364 0x0000 0x3 0x0 -#define MX6SX_PAD_GPIO1_IO02__WDOG1_WDOG_B 0x001C 0x0364 0x0000 0x4 0x0 -#define MX6SX_PAD_GPIO1_IO02__GPIO1_IO_2 0x001C 0x0364 0x0000 0x5 0x0 -#define MX6SX_PAD_GPIO1_IO02__CCM_REF_EN_B 0x001C 0x0364 0x0000 0x6 0x0 -#define MX6SX_PAD_GPIO1_IO02__PHY_TDI 0x001C 0x0364 0x0000 0x7 0x0 -#define MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x0020 0x0368 0x07B4 0x0 0x1 -#define MX6SX_PAD_GPIO1_IO03__USDHC1_WP 0x0020 0x0368 0x0868 0x1 0x1 -#define MX6SX_PAD_GPIO1_IO03__ENET1_REF_CLK_25M 0x0020 0x0368 0x0000 0x2 0x0 -#define MX6SX_PAD_GPIO1_IO03__CCM_DI1_EXT_CLK 0x0020 0x0368 0x0000 0x3 0x0 -#define MX6SX_PAD_GPIO1_IO03__WDOG2_WDOG_B 0x0020 0x0368 0x0000 0x4 0x0 -#define MX6SX_PAD_GPIO1_IO03__GPIO1_IO_3 0x0020 0x0368 0x0000 0x5 0x0 -#define MX6SX_PAD_GPIO1_IO03__CCM_PLL3_BYP 0x0020 0x0368 0x0000 0x6 0x0 -#define MX6SX_PAD_GPIO1_IO03__PHY_TCK 0x0020 0x0368 0x0000 0x7 0x0 -#define MX6SX_PAD_GPIO1_IO04__UART1_RX 0x0024 0x036C 0x0830 0x0 0x0 -#define MX6SX_PAD_GPIO1_IO04__UART1_TX 0x0024 0x036C 0x0000 0x0 0x0 -#define MX6SX_PAD_GPIO1_IO04__USDHC2_RESET_B 0x0024 0x036C 0x0000 0x1 0x0 -#define MX6SX_PAD_GPIO1_IO04__ENET1_MDC 0x0024 0x036C 0x0000 0x2 0x0 -#define MX6SX_PAD_GPIO1_IO04__OSC32K_32K_OUT 0x0024 0x036C 0x0000 0x3 0x0 -#define MX6SX_PAD_GPIO1_IO04__ENET2_REF_CLK2 0x0024 0x036C 0x076C 0x4 0x0 -#define MX6SX_PAD_GPIO1_IO04__GPIO1_IO_4 0x0024 0x036C 0x0000 0x5 0x0 -#define MX6SX_PAD_GPIO1_IO04__CCM_PLL2_BYP 0x0024 0x036C 0x0000 0x6 0x0 -#define MX6SX_PAD_GPIO1_IO04__PHY_TMS 0x0024 0x036C 0x0000 0x7 0x0 -#define MX6SX_PAD_GPIO1_IO05__UART1_RX 0x0028 0x0370 0x0830 0x0 0x1 -#define MX6SX_PAD_GPIO1_IO05__UART1_TX 0x0028 0x0370 0x0000 0x0 0x0 -#define MX6SX_PAD_GPIO1_IO05__USDHC2_VSELECT 0x0028 0x0370 0x0000 0x1 0x0 -#define MX6SX_PAD_GPIO1_IO05__ENET1_MDIO 0x0028 0x0370 0x0764 0x2 0x0 -#define MX6SX_PAD_GPIO1_IO05__ASRC_ASRC_EXT_CLK 0x0028 0x0370 0x0000 0x3 0x0 -#define MX6SX_PAD_GPIO1_IO05__ENET1_REF_CLK1 0x0028 0x0370 0x0760 0x4 0x0 -#define MX6SX_PAD_GPIO1_IO05__GPIO1_IO_5 0x0028 0x0370 0x0000 0x5 0x0 -#define MX6SX_PAD_GPIO1_IO05__SRC_TESTER_ACK 0x0028 0x0370 0x0000 0x6 0x0 -#define MX6SX_PAD_GPIO1_IO05__PHY_TDO 0x0028 0x0370 0x0000 0x7 0x0 -#define MX6SX_PAD_GPIO1_IO06__UART2_RX 0x002C 0x0374 0x0838 0x0 0x0 -#define MX6SX_PAD_GPIO1_IO06__UART2_TX 0x002C 0x0374 0x0000 0x0 0x0 -#define MX6SX_PAD_GPIO1_IO06__USDHC2_CD_B 0x002C 0x0374 0x086C 0x1 0x1 -#define MX6SX_PAD_GPIO1_IO06__ENET2_MDC 0x002C 0x0374 0x0000 0x2 0x0 -#define MX6SX_PAD_GPIO1_IO06__CSI1_MCLK 0x002C 0x0374 0x0000 0x3 0x0 -#define MX6SX_PAD_GPIO1_IO06__UART1_RTS_B 0x002C 0x0374 0x082C 0x4 0x0 -#define MX6SX_PAD_GPIO1_IO06__GPIO1_IO_6 0x002C 0x0374 0x0000 0x5 0x0 -#define MX6SX_PAD_GPIO1_IO06__SRC_ANY_PU_RESET 0x002C 0x0374 0x0000 0x6 0x0 -#define MX6SX_PAD_GPIO1_IO06__OCOTP_CTRL_WRAPPER_FUSE_LATCHED 0x002C 0x0374 0x0000 0x7 0x0 -#define MX6SX_PAD_GPIO1_IO07__UART2_RX 0x0030 0x0378 0x0838 0x0 0x1 -#define MX6SX_PAD_GPIO1_IO07__UART2_TX 0x0030 0x0378 0x0000 0x0 0x0 -#define MX6SX_PAD_GPIO1_IO07__USDHC2_WP 0x0030 0x0378 0x0870 0x1 0x1 -#define MX6SX_PAD_GPIO1_IO07__ENET2_MDIO 0x0030 0x0378 0x0770 0x2 0x0 -#define MX6SX_PAD_GPIO1_IO07__AUDMUX_MCLK 0x0030 0x0378 0x0000 0x3 0x0 -#define MX6SX_PAD_GPIO1_IO07__UART1_CTS_B 0x0030 0x0378 0x0000 0x4 0x0 -#define MX6SX_PAD_GPIO1_IO07__GPIO1_IO_7 0x0030 0x0378 0x0000 0x5 0x0 -#define MX6SX_PAD_GPIO1_IO07__SRC_EARLY_RESET 0x0030 0x0378 0x0000 0x6 0x0 -#define MX6SX_PAD_GPIO1_IO07__DCIC2_OUT 0x0030 0x0378 0x0000 0x7 0x0 -#define MX6SX_PAD_GPIO1_IO07__VDEC_DEBUG_44 0x0030 0x0378 0x0000 0x8 0x0 -#define MX6SX_PAD_GPIO1_IO08__USB_OTG1_OC 0x0034 0x037C 0x0860 0x0 0x0 -#define MX6SX_PAD_GPIO1_IO08__WDOG1_WDOG_B 0x0034 0x037C 0x0000 0x1 0x0 -#define MX6SX_PAD_GPIO1_IO08__SDMA_EXT_EVENT_0 0x0034 0x037C 0x081C 0x2 0x0 -#define MX6SX_PAD_GPIO1_IO08__CCM_PMIC_RDY 0x0034 0x037C 0x069C 0x3 0x1 -#define MX6SX_PAD_GPIO1_IO08__UART2_RTS_B 0x0034 0x037C 0x0834 0x4 0x0 -#define MX6SX_PAD_GPIO1_IO08__GPIO1_IO_8 0x0034 0x037C 0x0000 0x5 0x0 -#define MX6SX_PAD_GPIO1_IO08__SRC_SYSTEM_RESET 0x0034 0x037C 0x0000 0x6 0x0 -#define MX6SX_PAD_GPIO1_IO08__DCIC1_OUT 0x0034 0x037C 0x0000 0x7 0x0 -#define MX6SX_PAD_GPIO1_IO08__VDEC_DEBUG_43 0x0034 0x037C 0x0000 0x8 0x0 -#define MX6SX_PAD_GPIO1_IO09__USB_OTG1_PWR 0x0038 0x0380 0x0000 0x0 0x0 -#define MX6SX_PAD_GPIO1_IO09__WDOG2_WDOG_B 0x0038 0x0380 0x0000 0x1 0x0 -#define MX6SX_PAD_GPIO1_IO09__SDMA_EXT_EVENT_1 0x0038 0x0380 0x0820 0x2 0x0 -#define MX6SX_PAD_GPIO1_IO09__CCM_OUT0 0x0038 0x0380 0x0000 0x3 0x0 -#define MX6SX_PAD_GPIO1_IO09__UART2_CTS_B 0x0038 0x0380 0x0000 0x4 0x0 -#define MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x0038 0x0380 0x0000 0x5 0x0 -#define MX6SX_PAD_GPIO1_IO09__SRC_INT_BOOT 0x0038 0x0380 0x0000 0x6 0x0 -#define MX6SX_PAD_GPIO1_IO09__OBSERVE_MUX_OUT_4 0x0038 0x0380 0x0000 0x7 0x0 -#define MX6SX_PAD_GPIO1_IO09__VDEC_DEBUG_42 0x0038 0x0380 0x0000 0x8 0x0 -#define MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x003C 0x0384 0x0624 0x0 0x0 -#define MX6SX_PAD_GPIO1_IO10__SPDIF_EXT_CLK 0x003C 0x0384 0x0828 0x1 0x0 -#define MX6SX_PAD_GPIO1_IO10__PWM1_OUT 0x003C 0x0384 0x0000 0x2 0x0 -#define MX6SX_PAD_GPIO1_IO10__CCM_OUT1 0x003C 0x0384 0x0000 0x3 0x0 -#define MX6SX_PAD_GPIO1_IO10__CSI1_FIELD 0x003C 0x0384 0x070C 0x4 0x1 -#define MX6SX_PAD_GPIO1_IO10__GPIO1_IO_10 0x003C 0x0384 0x0000 0x5 0x0 -#define MX6SX_PAD_GPIO1_IO10__CSU_CSU_INT_DEB 0x003C 0x0384 0x0000 0x6 0x0 -#define MX6SX_PAD_GPIO1_IO10__OBSERVE_MUX_OUT_3 0x003C 0x0384 0x0000 0x7 0x0 -#define MX6SX_PAD_GPIO1_IO10__VDEC_DEBUG_41 0x003C 0x0384 0x0000 0x8 0x0 -#define MX6SX_PAD_GPIO1_IO11__USB_OTG2_OC 0x0040 0x0388 0x085C 0x0 0x0 -#define MX6SX_PAD_GPIO1_IO11__SPDIF_IN 0x0040 0x0388 0x0824 0x1 0x2 -#define MX6SX_PAD_GPIO1_IO11__PWM2_OUT 0x0040 0x0388 0x0000 0x2 0x0 -#define MX6SX_PAD_GPIO1_IO11__CCM_CLKO1 0x0040 0x0388 0x0000 0x3 0x0 -#define MX6SX_PAD_GPIO1_IO11__MLB_DATA 0x0040 0x0388 0x07EC 0x4 0x0 -#define MX6SX_PAD_GPIO1_IO11__GPIO1_IO_11 0x0040 0x0388 0x0000 0x5 0x0 -#define MX6SX_PAD_GPIO1_IO11__CSU_CSU_ALARM_AUT_0 0x0040 0x0388 0x0000 0x6 0x0 -#define MX6SX_PAD_GPIO1_IO11__OBSERVE_MUX_OUT_2 0x0040 0x0388 0x0000 0x7 0x0 -#define MX6SX_PAD_GPIO1_IO11__VDEC_DEBUG_40 0x0040 0x0388 0x0000 0x8 0x0 -#define MX6SX_PAD_GPIO1_IO12__USB_OTG2_PWR 0x0044 0x038C 0x0000 0x0 0x0 -#define MX6SX_PAD_GPIO1_IO12__SPDIF_OUT 0x0044 0x038C 0x0000 0x1 0x0 -#define MX6SX_PAD_GPIO1_IO12__PWM3_OUT 0x0044 0x038C 0x0000 0x2 0x0 -#define MX6SX_PAD_GPIO1_IO12__CCM_CLKO2 0x0044 0x038C 0x0000 0x3 0x0 -#define MX6SX_PAD_GPIO1_IO12__MLB_CLK 0x0044 0x038C 0x07E8 0x4 0x0 -#define MX6SX_PAD_GPIO1_IO12__GPIO1_IO_12 0x0044 0x038C 0x0000 0x5 0x0 -#define MX6SX_PAD_GPIO1_IO12__CSU_CSU_ALARM_AUT_1 0x0044 0x038C 0x0000 0x6 0x0 -#define MX6SX_PAD_GPIO1_IO12__OBSERVE_MUX_OUT_1 0x0044 0x038C 0x0000 0x7 0x0 -#define MX6SX_PAD_GPIO1_IO12__VDEC_DEBUG_39 0x0044 0x038C 0x0000 0x8 0x0 -#define MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY 0x0048 0x0390 0x0000 0x0 0x0 -#define MX6SX_PAD_GPIO1_IO13__ANATOP_OTG2_ID 0x0048 0x0390 0x0628 0x1 0x0 -#define MX6SX_PAD_GPIO1_IO13__PWM4_OUT 0x0048 0x0390 0x0000 0x2 0x0 -#define MX6SX_PAD_GPIO1_IO13__CCM_OUT2 0x0048 0x0390 0x0000 0x3 0x0 -#define MX6SX_PAD_GPIO1_IO13__MLB_SIG 0x0048 0x0390 0x07F0 0x4 0x0 -#define MX6SX_PAD_GPIO1_IO13__GPIO1_IO_13 0x0048 0x0390 0x0000 0x5 0x0 -#define MX6SX_PAD_GPIO1_IO13__CSU_CSU_ALARM_AUT_2 0x0048 0x0390 0x0000 0x6 0x0 -#define MX6SX_PAD_GPIO1_IO13__OBSERVE_MUX_OUT_0 0x0048 0x0390 0x0000 0x7 0x0 -#define MX6SX_PAD_GPIO1_IO13__VDEC_DEBUG_38 0x0048 0x0390 0x0000 0x8 0x0 -#define MX6SX_PAD_CSI_DATA00__CSI1_DATA_2 0x004C 0x0394 0x06A8 0x0 0x0 -#define MX6SX_PAD_CSI_DATA00__ESAI_TX_CLK 0x004C 0x0394 0x078C 0x1 0x1 -#define MX6SX_PAD_CSI_DATA00__AUDMUX_AUD6_TXC 0x004C 0x0394 0x0684 0x2 0x1 -#define MX6SX_PAD_CSI_DATA00__I2C1_SCL 0x004C 0x0394 0x07A8 0x3 0x0 -#define MX6SX_PAD_CSI_DATA00__UART6_RI_B 0x004C 0x0394 0x0000 0x4 0x0 -#define MX6SX_PAD_CSI_DATA00__GPIO1_IO_14 0x004C 0x0394 0x0000 0x5 0x0 -#define MX6SX_PAD_CSI_DATA00__WEIM_DATA_23 0x004C 0x0394 0x0000 0x6 0x0 -#define MX6SX_PAD_CSI_DATA00__SAI1_TX_BCLK 0x004C 0x0394 0x0800 0x7 0x0 -#define MX6SX_PAD_CSI_DATA00__VADC_DATA_4 0x004C 0x0394 0x0000 0x8 0x0 -#define MX6SX_PAD_CSI_DATA00__MMDC_DEBUG_37 0x004C 0x0394 0x0000 0x9 0x0 -#define MX6SX_PAD_CSI_DATA01__CSI1_DATA_3 0x0050 0x0398 0x06AC 0x0 0x0 -#define MX6SX_PAD_CSI_DATA01__ESAI_TX_FS 0x0050 0x0398 0x077C 0x1 0x1 -#define MX6SX_PAD_CSI_DATA01__AUDMUX_AUD6_TXFS 0x0050 0x0398 0x0688 0x2 0x1 -#define MX6SX_PAD_CSI_DATA01__I2C1_SDA 0x0050 0x0398 0x07AC 0x3 0x0 -#define MX6SX_PAD_CSI_DATA01__UART6_DSR_B 0x0050 0x0398 0x0000 0x4 0x0 -#define MX6SX_PAD_CSI_DATA01__GPIO1_IO_15 0x0050 0x0398 0x0000 0x5 0x0 -#define MX6SX_PAD_CSI_DATA01__WEIM_DATA_22 0x0050 0x0398 0x0000 0x6 0x0 -#define MX6SX_PAD_CSI_DATA01__SAI1_TX_SYNC 0x0050 0x0398 0x0804 0x7 0x0 -#define MX6SX_PAD_CSI_DATA01__VADC_DATA_5 0x0050 0x0398 0x0000 0x8 0x0 -#define MX6SX_PAD_CSI_DATA01__MMDC_DEBUG_38 0x0050 0x0398 0x0000 0x9 0x0 -#define MX6SX_PAD_CSI_DATA02__CSI1_DATA_4 0x0054 0x039C 0x06B0 0x0 0x0 -#define MX6SX_PAD_CSI_DATA02__ESAI_RX_CLK 0x0054 0x039C 0x0788 0x1 0x1 -#define MX6SX_PAD_CSI_DATA02__AUDMUX_AUD6_RXC 0x0054 0x039C 0x067C 0x2 0x1 -#define MX6SX_PAD_CSI_DATA02__KPP_COL_5 0x0054 0x039C 0x07C8 0x3 0x0 -#define MX6SX_PAD_CSI_DATA02__UART6_DTR_B 0x0054 0x039C 0x0000 0x4 0x0 -#define MX6SX_PAD_CSI_DATA02__GPIO1_IO_16 0x0054 0x039C 0x0000 0x5 0x0 -#define MX6SX_PAD_CSI_DATA02__WEIM_DATA_21 0x0054 0x039C 0x0000 0x6 0x0 -#define MX6SX_PAD_CSI_DATA02__SAI1_RX_BCLK 0x0054 0x039C 0x07F4 0x7 0x0 -#define MX6SX_PAD_CSI_DATA02__VADC_DATA_6 0x0054 0x039C 0x0000 0x8 0x0 -#define MX6SX_PAD_CSI_DATA02__MMDC_DEBUG_39 0x0054 0x039C 0x0000 0x9 0x0 -#define MX6SX_PAD_CSI_DATA03__CSI1_DATA_5 0x0058 0x03A0 0x06B4 0x0 0x0 -#define MX6SX_PAD_CSI_DATA03__ESAI_RX_FS 0x0058 0x03A0 0x0778 0x1 0x1 -#define MX6SX_PAD_CSI_DATA03__AUDMUX_AUD6_RXFS 0x0058 0x03A0 0x0680 0x2 0x1 -#define MX6SX_PAD_CSI_DATA03__KPP_ROW_5 0x0058 0x03A0 0x07D4 0x3 0x0 -#define MX6SX_PAD_CSI_DATA03__UART6_DCD_B 0x0058 0x03A0 0x0000 0x4 0x0 -#define MX6SX_PAD_CSI_DATA03__GPIO1_IO_17 0x0058 0x03A0 0x0000 0x5 0x0 -#define MX6SX_PAD_CSI_DATA03__WEIM_DATA_20 0x0058 0x03A0 0x0000 0x6 0x0 -#define MX6SX_PAD_CSI_DATA03__SAI1_RX_SYNC 0x0058 0x03A0 0x07FC 0x7 0x0 -#define MX6SX_PAD_CSI_DATA03__VADC_DATA_7 0x0058 0x03A0 0x0000 0x8 0x0 -#define MX6SX_PAD_CSI_DATA03__MMDC_DEBUG_40 0x0058 0x03A0 0x0000 0x9 0x0 -#define MX6SX_PAD_CSI_DATA04__CSI1_DATA_6 0x005C 0x03A4 0x06B8 0x0 0x0 -#define MX6SX_PAD_CSI_DATA04__ESAI_TX1 0x005C 0x03A4 0x0794 0x1 0x1 -#define MX6SX_PAD_CSI_DATA04__SPDIF_OUT 0x005C 0x03A4 0x0000 0x2 0x0 -#define MX6SX_PAD_CSI_DATA04__KPP_COL_6 0x005C 0x03A4 0x07CC 0x3 0x0 -#define MX6SX_PAD_CSI_DATA04__UART6_RX 0x005C 0x03A4 0x0858 0x4 0x0 -#define MX6SX_PAD_CSI_DATA04__UART6_TX 0x005C 0x03A4 0x0000 0x4 0x0 -#define MX6SX_PAD_CSI_DATA04__GPIO1_IO_18 0x005C 0x03A4 0x0000 0x5 0x0 -#define MX6SX_PAD_CSI_DATA04__WEIM_DATA_19 0x005C 0x03A4 0x0000 0x6 0x0 -#define MX6SX_PAD_CSI_DATA04__PWM5_OUT 0x005C 0x03A4 0x0000 0x7 0x0 -#define MX6SX_PAD_CSI_DATA04__VADC_DATA_8 0x005C 0x03A4 0x0000 0x8 0x0 -#define MX6SX_PAD_CSI_DATA04__MMDC_DEBUG_41 0x005C 0x03A4 0x0000 0x9 0x0 -#define MX6SX_PAD_CSI_DATA05__CSI1_DATA_7 0x0060 0x03A8 0x06BC 0x0 0x0 -#define MX6SX_PAD_CSI_DATA05__ESAI_TX4_RX1 0x0060 0x03A8 0x07A0 0x1 0x1 -#define MX6SX_PAD_CSI_DATA05__SPDIF_IN 0x0060 0x03A8 0x0824 0x2 0x1 -#define MX6SX_PAD_CSI_DATA05__KPP_ROW_6 0x0060 0x03A8 0x07D8 0x3 0x0 -#define MX6SX_PAD_CSI_DATA05__UART6_RX 0x0060 0x03A8 0x0858 0x4 0x1 -#define MX6SX_PAD_CSI_DATA05__UART6_TX 0x0060 0x03A8 0x0000 0x4 0x0 -#define MX6SX_PAD_CSI_DATA05__GPIO1_IO_19 0x0060 0x03A8 0x0000 0x5 0x0 -#define MX6SX_PAD_CSI_DATA05__WEIM_DATA_18 0x0060 0x03A8 0x0000 0x6 0x0 -#define MX6SX_PAD_CSI_DATA05__PWM6_OUT 0x0060 0x03A8 0x0000 0x7 0x0 -#define MX6SX_PAD_CSI_DATA05__VADC_DATA_9 0x0060 0x03A8 0x0000 0x8 0x0 -#define MX6SX_PAD_CSI_DATA05__MMDC_DEBUG_42 0x0060 0x03A8 0x0000 0x9 0x0 -#define MX6SX_PAD_CSI_DATA06__CSI1_DATA_8 0x0064 0x03AC 0x06C0 0x0 0x0 -#define MX6SX_PAD_CSI_DATA06__ESAI_TX2_RX3 0x0064 0x03AC 0x0798 0x1 0x1 -#define MX6SX_PAD_CSI_DATA06__I2C4_SCL 0x0064 0x03AC 0x07C0 0x2 0x2 -#define MX6SX_PAD_CSI_DATA06__KPP_COL_7 0x0064 0x03AC 0x07D0 0x3 0x0 -#define MX6SX_PAD_CSI_DATA06__UART6_RTS_B 0x0064 0x03AC 0x0854 0x4 0x0 -#define MX6SX_PAD_CSI_DATA06__GPIO1_IO_20 0x0064 0x03AC 0x0000 0x5 0x0 -#define MX6SX_PAD_CSI_DATA06__WEIM_DATA_17 0x0064 0x03AC 0x0000 0x6 0x0 -#define MX6SX_PAD_CSI_DATA06__DCIC2_OUT 0x0064 0x03AC 0x0000 0x7 0x0 -#define MX6SX_PAD_CSI_DATA06__VADC_DATA_10 0x0064 0x03AC 0x0000 0x8 0x0 -#define MX6SX_PAD_CSI_DATA06__MMDC_DEBUG_43 0x0064 0x03AC 0x0000 0x9 0x0 -#define MX6SX_PAD_CSI_DATA07__CSI1_DATA_9 0x0068 0x03B0 0x06C4 0x0 0x0 -#define MX6SX_PAD_CSI_DATA07__ESAI_TX3_RX2 0x0068 0x03B0 0x079C 0x1 0x1 -#define MX6SX_PAD_CSI_DATA07__I2C4_SDA 0x0068 0x03B0 0x07C4 0x2 0x2 -#define MX6SX_PAD_CSI_DATA07__KPP_ROW_7 0x0068 0x03B0 0x07DC 0x3 0x0 -#define MX6SX_PAD_CSI_DATA07__UART6_CTS_B 0x0068 0x03B0 0x0000 0x4 0x0 -#define MX6SX_PAD_CSI_DATA07__GPIO1_IO_21 0x0068 0x03B0 0x0000 0x5 0x0 -#define MX6SX_PAD_CSI_DATA07__WEIM_DATA_16 0x0068 0x03B0 0x0000 0x6 0x0 -#define MX6SX_PAD_CSI_DATA07__DCIC1_OUT 0x0068 0x03B0 0x0000 0x7 0x0 -#define MX6SX_PAD_CSI_DATA07__VADC_DATA_11 0x0068 0x03B0 0x0000 0x8 0x0 -#define MX6SX_PAD_CSI_DATA07__MMDC_DEBUG_44 0x0068 0x03B0 0x0000 0x9 0x0 -#define MX6SX_PAD_CSI_HSYNC__CSI1_HSYNC 0x006C 0x03B4 0x0700 0x0 0x0 -#define MX6SX_PAD_CSI_HSYNC__ESAI_TX0 0x006C 0x03B4 0x0790 0x1 0x1 -#define MX6SX_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD 0x006C 0x03B4 0x0678 0x2 0x1 -#define MX6SX_PAD_CSI_HSYNC__UART4_RTS_B 0x006C 0x03B4 0x0844 0x3 0x2 -#define MX6SX_PAD_CSI_HSYNC__MQS_LEFT 0x006C 0x03B4 0x0000 0x4 0x0 -#define MX6SX_PAD_CSI_HSYNC__GPIO1_IO_22 0x006C 0x03B4 0x0000 0x5 0x0 -#define MX6SX_PAD_CSI_HSYNC__WEIM_DATA_25 0x006C 0x03B4 0x0000 0x6 0x0 -#define MX6SX_PAD_CSI_HSYNC__SAI1_TX_DATA_0 0x006C 0x03B4 0x0000 0x7 0x0 -#define MX6SX_PAD_CSI_HSYNC__VADC_DATA_2 0x006C 0x03B4 0x0000 0x8 0x0 -#define MX6SX_PAD_CSI_HSYNC__MMDC_DEBUG_35 0x006C 0x03B4 0x0000 0x9 0x0 -#define MX6SX_PAD_CSI_MCLK__CSI1_MCLK 0x0070 0x03B8 0x0000 0x0 0x0 -#define MX6SX_PAD_CSI_MCLK__ESAI_TX_HF_CLK 0x0070 0x03B8 0x0784 0x1 0x1 -#define MX6SX_PAD_CSI_MCLK__OSC32K_32K_OUT 0x0070 0x03B8 0x0000 0x2 0x0 -#define MX6SX_PAD_CSI_MCLK__UART4_RX 0x0070 0x03B8 0x0848 0x3 0x2 -#define MX6SX_PAD_CSI_MCLK__UART4_TX 0x0070 0x03B8 0x0000 0x3 0x0 -#define MX6SX_PAD_CSI_MCLK__ANATOP_32K_OUT 0x0070 0x03B8 0x0000 0x4 0x0 -#define MX6SX_PAD_CSI_MCLK__GPIO1_IO_23 0x0070 0x03B8 0x0000 0x5 0x0 -#define MX6SX_PAD_CSI_MCLK__WEIM_DATA_26 0x0070 0x03B8 0x0000 0x6 0x0 -#define MX6SX_PAD_CSI_MCLK__CSI1_FIELD 0x0070 0x03B8 0x070C 0x7 0x0 -#define MX6SX_PAD_CSI_MCLK__VADC_DATA_1 0x0070 0x03B8 0x0000 0x8 0x0 -#define MX6SX_PAD_CSI_MCLK__MMDC_DEBUG_34 0x0070 0x03B8 0x0000 0x9 0x0 -#define MX6SX_PAD_CSI_PIXCLK__CSI1_PIXCLK 0x0074 0x03BC 0x0704 0x0 0x0 -#define MX6SX_PAD_CSI_PIXCLK__ESAI_RX_HF_CLK 0x0074 0x03BC 0x0780 0x1 0x1 -#define MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x0074 0x03BC 0x0000 0x2 0x0 -#define MX6SX_PAD_CSI_PIXCLK__UART4_RX 0x0074 0x03BC 0x0848 0x3 0x3 -#define MX6SX_PAD_CSI_PIXCLK__UART4_TX 0x0074 0x03BC 0x0000 0x3 0x0 -#define MX6SX_PAD_CSI_PIXCLK__ANATOP_24M_OUT 0x0074 0x03BC 0x0000 0x4 0x0 -#define MX6SX_PAD_CSI_PIXCLK__GPIO1_IO_24 0x0074 0x03BC 0x0000 0x5 0x0 -#define MX6SX_PAD_CSI_PIXCLK__WEIM_DATA_27 0x0074 0x03BC 0x0000 0x6 0x0 -#define MX6SX_PAD_CSI_PIXCLK__ESAI_TX_HF_CLK 0x0074 0x03BC 0x0784 0x7 0x2 -#define MX6SX_PAD_CSI_PIXCLK__VADC_CLK 0x0074 0x03BC 0x0000 0x8 0x0 -#define MX6SX_PAD_CSI_PIXCLK__MMDC_DEBUG_33 0x0074 0x03BC 0x0000 0x9 0x0 -#define MX6SX_PAD_CSI_VSYNC__CSI1_VSYNC 0x0078 0x03C0 0x0708 0x0 0x0 -#define MX6SX_PAD_CSI_VSYNC__ESAI_TX5_RX0 0x0078 0x03C0 0x07A4 0x1 0x1 -#define MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD 0x0078 0x03C0 0x0674 0x2 0x1 -#define MX6SX_PAD_CSI_VSYNC__UART4_CTS_B 0x0078 0x03C0 0x0000 0x3 0x0 -#define MX6SX_PAD_CSI_VSYNC__MQS_RIGHT 0x0078 0x03C0 0x0000 0x4 0x0 -#define MX6SX_PAD_CSI_VSYNC__GPIO1_IO_25 0x0078 0x03C0 0x0000 0x5 0x0 -#define MX6SX_PAD_CSI_VSYNC__WEIM_DATA_24 0x0078 0x03C0 0x0000 0x6 0x0 -#define MX6SX_PAD_CSI_VSYNC__SAI1_RX_DATA_0 0x0078 0x03C0 0x07F8 0x7 0x0 -#define MX6SX_PAD_CSI_VSYNC__VADC_DATA_3 0x0078 0x03C0 0x0000 0x8 0x0 -#define MX6SX_PAD_CSI_VSYNC__MMDC_DEBUG_36 0x0078 0x03C0 0x0000 0x9 0x0 -#define MX6SX_PAD_ENET1_COL__ENET1_COL 0x007C 0x03C4 0x0000 0x0 0x0 -#define MX6SX_PAD_ENET1_COL__ENET2_MDC 0x007C 0x03C4 0x0000 0x1 0x0 -#define MX6SX_PAD_ENET1_COL__AUDMUX_AUD4_TXC 0x007C 0x03C4 0x0654 0x2 0x1 -#define MX6SX_PAD_ENET1_COL__UART1_RI_B 0x007C 0x03C4 0x0000 0x3 0x0 -#define MX6SX_PAD_ENET1_COL__SPDIF_EXT_CLK 0x007C 0x03C4 0x0828 0x4 0x1 -#define MX6SX_PAD_ENET1_COL__GPIO2_IO_0 0x007C 0x03C4 0x0000 0x5 0x0 -#define MX6SX_PAD_ENET1_COL__CSI2_DATA_23 0x007C 0x03C4 0x0000 0x6 0x0 -#define MX6SX_PAD_ENET1_COL__LCDIF2_DATA_16 0x007C 0x03C4 0x0000 0x7 0x0 -#define MX6SX_PAD_ENET1_COL__VDEC_DEBUG_37 0x007C 0x03C4 0x0000 0x8 0x0 -#define MX6SX_PAD_ENET1_COL__PCIE_CTRL_DEBUG_31 0x007C 0x03C4 0x0000 0x9 0x0 -#define MX6SX_PAD_ENET1_CRS__ENET1_CRS 0x0080 0x03C8 0x0000 0x0 0x0 -#define MX6SX_PAD_ENET1_CRS__ENET2_MDIO 0x0080 0x03C8 0x0770 0x1 0x1 -#define MX6SX_PAD_ENET1_CRS__AUDMUX_AUD4_TXD 0x0080 0x03C8 0x0648 0x2 0x1 -#define MX6SX_PAD_ENET1_CRS__UART1_DCD_B 0x0080 0x03C8 0x0000 0x3 0x0 -#define MX6SX_PAD_ENET1_CRS__SPDIF_LOCK 0x0080 0x03C8 0x0000 0x4 0x0 -#define MX6SX_PAD_ENET1_CRS__GPIO2_IO_1 0x0080 0x03C8 0x0000 0x5 0x0 -#define MX6SX_PAD_ENET1_CRS__CSI2_DATA_22 0x0080 0x03C8 0x0000 0x6 0x0 -#define MX6SX_PAD_ENET1_CRS__LCDIF2_DATA_17 0x0080 0x03C8 0x0000 0x7 0x0 -#define MX6SX_PAD_ENET1_CRS__VDEC_DEBUG_36 0x0080 0x03C8 0x0000 0x8 0x0 -#define MX6SX_PAD_ENET1_CRS__PCIE_CTRL_DEBUG_30 0x0080 0x03C8 0x0000 0x9 0x0 -#define MX6SX_PAD_ENET1_MDC__ENET1_MDC 0x0084 0x03CC 0x0000 0x0 0x0 -#define MX6SX_PAD_ENET1_MDC__ENET2_MDC 0x0084 0x03CC 0x0000 0x1 0x0 -#define MX6SX_PAD_ENET1_MDC__AUDMUX_AUD3_RXFS 0x0084 0x03CC 0x0638 0x2 0x1 -#define MX6SX_PAD_ENET1_MDC__ANATOP_24M_OUT 0x0084 0x03CC 0x0000 0x3 0x0 -#define MX6SX_PAD_ENET1_MDC__EPIT2_OUT 0x0084 0x03CC 0x0000 0x4 0x0 -#define MX6SX_PAD_ENET1_MDC__GPIO2_IO_2 0x0084 0x03CC 0x0000 0x5 0x0 -#define MX6SX_PAD_ENET1_MDC__USB_OTG1_PWR 0x0084 0x03CC 0x0000 0x6 0x0 -#define MX6SX_PAD_ENET1_MDC__PWM7_OUT 0x0084 0x03CC 0x0000 0x7 0x0 -#define MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0x0088 0x03D0 0x0764 0x0 0x1 -#define MX6SX_PAD_ENET1_MDIO__ENET2_MDIO 0x0088 0x03D0 0x0770 0x1 0x2 -#define MX6SX_PAD_ENET1_MDIO__AUDMUX_MCLK 0x0088 0x03D0 0x0000 0x2 0x0 -#define MX6SX_PAD_ENET1_MDIO__OSC32K_32K_OUT 0x0088 0x03D0 0x0000 0x3 0x0 -#define MX6SX_PAD_ENET1_MDIO__EPIT1_OUT 0x0088 0x03D0 0x0000 0x4 0x0 -#define MX6SX_PAD_ENET1_MDIO__GPIO2_IO_3 0x0088 0x03D0 0x0000 0x5 0x0 -#define MX6SX_PAD_ENET1_MDIO__USB_OTG1_OC 0x0088 0x03D0 0x0860 0x6 0x1 -#define MX6SX_PAD_ENET1_MDIO__PWM8_OUT 0x0088 0x03D0 0x0000 0x7 0x0 -#define MX6SX_PAD_ENET1_RX_CLK__ENET1_RX_CLK 0x008C 0x03D4 0x0768 0x0 0x0 -#define MX6SX_PAD_ENET1_RX_CLK__ENET1_REF_CLK_25M 0x008C 0x03D4 0x0000 0x1 0x0 -#define MX6SX_PAD_ENET1_RX_CLK__AUDMUX_AUD4_TXFS 0x008C 0x03D4 0x0658 0x2 0x1 -#define MX6SX_PAD_ENET1_RX_CLK__UART1_DSR_B 0x008C 0x03D4 0x0000 0x3 0x0 -#define MX6SX_PAD_ENET1_RX_CLK__SPDIF_OUT 0x008C 0x03D4 0x0000 0x4 0x0 -#define MX6SX_PAD_ENET1_RX_CLK__GPIO2_IO_4 0x008C 0x03D4 0x0000 0x5 0x0 -#define MX6SX_PAD_ENET1_RX_CLK__CSI2_DATA_21 0x008C 0x03D4 0x0000 0x6 0x0 -#define MX6SX_PAD_ENET1_RX_CLK__LCDIF2_DATA_18 0x008C 0x03D4 0x0000 0x7 0x0 -#define MX6SX_PAD_ENET1_RX_CLK__VDEC_DEBUG_35 0x008C 0x03D4 0x0000 0x8 0x0 -#define MX6SX_PAD_ENET1_RX_CLK__PCIE_CTRL_DEBUG_29 0x008C 0x03D4 0x0000 0x9 0x0 -#define MX6SX_PAD_ENET1_TX_CLK__ENET1_TX_CLK 0x0090 0x03D8 0x0000 0x0 0x0 -/* - * SION bit is necessary for ENET1_REF_CLK1 (ENET2_REF_CLK2 untested) if it is - * used as clock output of IMX6SX_CLK_ENET_REF (ENET1_TX_CLK) to e.g. supply a - * PHY in RMII mode. This configuration is valid if: - * - bit 1 in field IMX6SX_GPR1_FEC_CLOCK_PAD_DIR_MASK is set - * - bit 1 in field IMX6SX_GPR1_FEC_CLOCK_MUX_SEL_MASK unset - * It seems to be a silicon bug that in this configuration ENET1_TX reference - * clock isn't provided automatically. According to i.MX6SX reference manual - * (IOMUXC_GPR_GPR1 field descriptions: ENET1_CLK_SEL, Rev. 0 from 2/2015) it - * should be the case. - * So this might have unwanted side effects for other hardware units that are - * also connected to that pin and using respective function as input (e.g. - * UART1's DTR handling on MX6SX_PAD_ENET1_TX_CLK__UART1_DTR_B). - */ -#define MX6SX_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x0090 0x03D8 0x0760 0x1 0x1 -#define MX6SX_PAD_ENET1_TX_CLK__AUDMUX_AUD4_RXD 0x0090 0x03D8 0x0644 0x2 0x1 -#define MX6SX_PAD_ENET1_TX_CLK__UART1_DTR_B 0x0090 0x03D8 0x0000 0x3 0x0 -#define MX6SX_PAD_ENET1_TX_CLK__SPDIF_SR_CLK 0x0090 0x03D8 0x0000 0x4 0x0 -#define MX6SX_PAD_ENET1_TX_CLK__GPIO2_IO_5 0x0090 0x03D8 0x0000 0x5 0x0 -#define MX6SX_PAD_ENET1_TX_CLK__CSI2_DATA_20 0x0090 0x03D8 0x0000 0x6 0x0 -#define MX6SX_PAD_ENET1_TX_CLK__LCDIF2_DATA_19 0x0090 0x03D8 0x0000 0x7 0x0 -#define MX6SX_PAD_ENET1_TX_CLK__VDEC_DEBUG_34 0x0090 0x03D8 0x0000 0x8 0x0 -#define MX6SX_PAD_ENET1_TX_CLK__PCIE_CTRL_DEBUG_28 0x0090 0x03D8 0x0000 0x9 0x0 -#define MX6SX_PAD_ENET2_COL__ENET2_COL 0x0094 0x03DC 0x0000 0x0 0x0 -#define MX6SX_PAD_ENET2_COL__ENET1_MDC 0x0094 0x03DC 0x0000 0x1 0x0 -#define MX6SX_PAD_ENET2_COL__AUDMUX_AUD4_RXC 0x0094 0x03DC 0x064C 0x2 0x1 -#define MX6SX_PAD_ENET2_COL__UART1_RX 0x0094 0x03DC 0x0830 0x3 0x2 -#define MX6SX_PAD_ENET2_COL__UART1_TX 0x0094 0x03DC 0x0000 0x3 0x0 -#define MX6SX_PAD_ENET2_COL__SPDIF_IN 0x0094 0x03DC 0x0824 0x4 0x3 -#define MX6SX_PAD_ENET2_COL__GPIO2_IO_6 0x0094 0x03DC 0x0000 0x5 0x0 -#define MX6SX_PAD_ENET2_COL__ANATOP_OTG1_ID 0x0094 0x03DC 0x0624 0x6 0x1 -#define MX6SX_PAD_ENET2_COL__LCDIF2_DATA_20 0x0094 0x03DC 0x0000 0x7 0x0 -#define MX6SX_PAD_ENET2_COL__VDEC_DEBUG_33 0x0094 0x03DC 0x0000 0x8 0x0 -#define MX6SX_PAD_ENET2_COL__PCIE_CTRL_DEBUG_27 0x0094 0x03DC 0x0000 0x9 0x0 -#define MX6SX_PAD_ENET2_CRS__ENET2_CRS 0x0098 0x03E0 0x0000 0x0 0x0 -#define MX6SX_PAD_ENET2_CRS__ENET1_MDIO 0x0098 0x03E0 0x0764 0x1 0x2 -#define MX6SX_PAD_ENET2_CRS__AUDMUX_AUD4_RXFS 0x0098 0x03E0 0x0650 0x2 0x1 -#define MX6SX_PAD_ENET2_CRS__UART1_RX 0x0098 0x03E0 0x0830 0x3 0x3 -#define MX6SX_PAD_ENET2_CRS__UART1_TX 0x0098 0x03E0 0x0000 0x3 0x0 -#define MX6SX_PAD_ENET2_CRS__MLB_SIG 0x0098 0x03E0 0x07F0 0x4 0x1 -#define MX6SX_PAD_ENET2_CRS__GPIO2_IO_7 0x0098 0x03E0 0x0000 0x5 0x0 -#define MX6SX_PAD_ENET2_CRS__ANATOP_OTG2_ID 0x0098 0x03E0 0x0628 0x6 0x1 -#define MX6SX_PAD_ENET2_CRS__LCDIF2_DATA_21 0x0098 0x03E0 0x0000 0x7 0x0 -#define MX6SX_PAD_ENET2_CRS__VDEC_DEBUG_32 0x0098 0x03E0 0x0000 0x8 0x0 -#define MX6SX_PAD_ENET2_CRS__PCIE_CTRL_DEBUG_26 0x0098 0x03E0 0x0000 0x9 0x0 -#define MX6SX_PAD_ENET2_RX_CLK__ENET2_RX_CLK 0x009C 0x03E4 0x0774 0x0 0x0 -#define MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M 0x009C 0x03E4 0x0000 0x1 0x0 -#define MX6SX_PAD_ENET2_RX_CLK__I2C3_SCL 0x009C 0x03E4 0x07B8 0x2 0x1 -#define MX6SX_PAD_ENET2_RX_CLK__UART1_RTS_B 0x009C 0x03E4 0x082C 0x3 0x2 -#define MX6SX_PAD_ENET2_RX_CLK__MLB_DATA 0x009C 0x03E4 0x07EC 0x4 0x1 -#define MX6SX_PAD_ENET2_RX_CLK__GPIO2_IO_8 0x009C 0x03E4 0x0000 0x5 0x0 -#define MX6SX_PAD_ENET2_RX_CLK__USB_OTG2_OC 0x009C 0x03E4 0x085C 0x6 0x1 -#define MX6SX_PAD_ENET2_RX_CLK__LCDIF2_DATA_22 0x009C 0x03E4 0x0000 0x7 0x0 -#define MX6SX_PAD_ENET2_RX_CLK__VDEC_DEBUG_31 0x009C 0x03E4 0x0000 0x8 0x0 -#define MX6SX_PAD_ENET2_RX_CLK__PCIE_CTRL_DEBUG_25 0x009C 0x03E4 0x0000 0x9 0x0 -#define MX6SX_PAD_ENET2_TX_CLK__ENET2_TX_CLK 0x00A0 0x03E8 0x0000 0x0 0x0 -#define MX6SX_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x00A0 0x03E8 0x076C 0x1 0x1 -#define MX6SX_PAD_ENET2_TX_CLK__I2C3_SDA 0x00A0 0x03E8 0x07BC 0x2 0x1 -#define MX6SX_PAD_ENET2_TX_CLK__UART1_CTS_B 0x00A0 0x03E8 0x0000 0x3 0x0 -#define MX6SX_PAD_ENET2_TX_CLK__MLB_CLK 0x00A0 0x03E8 0x07E8 0x4 0x1 -#define MX6SX_PAD_ENET2_TX_CLK__GPIO2_IO_9 0x00A0 0x03E8 0x0000 0x5 0x0 -#define MX6SX_PAD_ENET2_TX_CLK__USB_OTG2_PWR 0x00A0 0x03E8 0x0000 0x6 0x0 -#define MX6SX_PAD_ENET2_TX_CLK__LCDIF2_DATA_23 0x00A0 0x03E8 0x0000 0x7 0x0 -#define MX6SX_PAD_ENET2_TX_CLK__VDEC_DEBUG_30 0x00A0 0x03E8 0x0000 0x8 0x0 -#define MX6SX_PAD_ENET2_TX_CLK__PCIE_CTRL_DEBUG_24 0x00A0 0x03E8 0x0000 0x9 0x0 -#define MX6SX_PAD_KEY_COL0__KPP_COL_0 0x00A4 0x03EC 0x0000 0x0 0x0 -#define MX6SX_PAD_KEY_COL0__USDHC3_CD_B 0x00A4 0x03EC 0x0000 0x1 0x0 -#define MX6SX_PAD_KEY_COL0__UART6_RTS_B 0x00A4 0x03EC 0x0854 0x2 0x2 -#define MX6SX_PAD_KEY_COL0__ECSPI1_SCLK 0x00A4 0x03EC 0x0710 0x3 0x0 -#define MX6SX_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x00A4 0x03EC 0x066C 0x4 0x0 -#define MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x00A4 0x03EC 0x0000 0x5 0x0 -#define MX6SX_PAD_KEY_COL0__SDMA_EXT_EVENT_1 0x00A4 0x03EC 0x0820 0x6 0x1 -#define MX6SX_PAD_KEY_COL0__SAI2_TX_BCLK 0x00A4 0x03EC 0x0814 0x7 0x0 -#define MX6SX_PAD_KEY_COL0__VADC_DATA_0 0x00A4 0x03EC 0x0000 0x8 0x0 -#define MX6SX_PAD_KEY_COL1__KPP_COL_1 0x00A8 0x03F0 0x0000 0x0 0x0 -#define MX6SX_PAD_KEY_COL1__USDHC3_RESET_B 0x00A8 0x03F0 0x0000 0x1 0x0 -#define MX6SX_PAD_KEY_COL1__UART6_RX 0x00A8 0x03F0 0x0858 0x2 0x2 -#define MX6SX_PAD_KEY_COL1__UART6_TX 0x00A8 0x03F0 0x0000 0x2 0x0 -#define MX6SX_PAD_KEY_COL1__ECSPI1_MISO 0x00A8 0x03F0 0x0714 0x3 0x0 -#define MX6SX_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x00A8 0x03F0 0x0670 0x4 0x0 -#define MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x00A8 0x03F0 0x0000 0x5 0x0 -#define MX6SX_PAD_KEY_COL1__USDHC3_RESET 0x00A8 0x03F0 0x0000 0x6 0x0 -#define MX6SX_PAD_KEY_COL1__SAI2_TX_SYNC 0x00A8 0x03F0 0x0818 0x7 0x0 -#define MX6SX_PAD_KEY_COL2__KPP_COL_2 0x00AC 0x03F4 0x0000 0x0 0x0 -#define MX6SX_PAD_KEY_COL2__USDHC4_CD_B 0x00AC 0x03F4 0x0874 0x1 0x1 -#define MX6SX_PAD_KEY_COL2__UART5_RTS_B 0x00AC 0x03F4 0x084C 0x2 0x2 -#define MX6SX_PAD_KEY_COL2__CAN1_TX 0x00AC 0x03F4 0x0000 0x3 0x0 -#define MX6SX_PAD_KEY_COL2__CANFD_TX1 0x00AC 0x03F4 0x0000 0x4 0x0 -#define MX6SX_PAD_KEY_COL2__GPIO2_IO_12 0x00AC 0x03F4 0x0000 0x5 0x0 -#define MX6SX_PAD_KEY_COL2__WEIM_DATA_30 0x00AC 0x03F4 0x0000 0x6 0x0 -#define MX6SX_PAD_KEY_COL2__ECSPI1_RDY 0x00AC 0x03F4 0x0000 0x7 0x0 -#define MX6SX_PAD_KEY_COL3__KPP_COL_3 0x00B0 0x03F8 0x0000 0x0 0x0 -#define MX6SX_PAD_KEY_COL3__USDHC4_LCTL 0x00B0 0x03F8 0x0000 0x1 0x0 -#define MX6SX_PAD_KEY_COL3__UART5_RX 0x00B0 0x03F8 0x0850 0x2 0x2 -#define MX6SX_PAD_KEY_COL3__UART5_TX 0x00B0 0x03F8 0x0000 0x2 0x0 -#define MX6SX_PAD_KEY_COL3__CAN2_TX 0x00B0 0x03F8 0x0000 0x3 0x0 -#define MX6SX_PAD_KEY_COL3__CANFD_TX2 0x00B0 0x03F8 0x0000 0x4 0x0 -#define MX6SX_PAD_KEY_COL3__GPIO2_IO_13 0x00B0 0x03F8 0x0000 0x5 0x0 -#define MX6SX_PAD_KEY_COL3__WEIM_DATA_28 0x00B0 0x03F8 0x0000 0x6 0x0 -#define MX6SX_PAD_KEY_COL3__ECSPI1_SS2 0x00B0 0x03F8 0x0000 0x7 0x0 -#define MX6SX_PAD_KEY_COL4__KPP_COL_4 0x00B4 0x03FC 0x0000 0x0 0x0 -#define MX6SX_PAD_KEY_COL4__ENET2_MDC 0x00B4 0x03FC 0x0000 0x1 0x0 -#define MX6SX_PAD_KEY_COL4__I2C3_SCL 0x00B4 0x03FC 0x07B8 0x2 0x2 -#define MX6SX_PAD_KEY_COL4__USDHC2_LCTL 0x00B4 0x03FC 0x0000 0x3 0x0 -#define MX6SX_PAD_KEY_COL4__AUDMUX_AUD5_RXC 0x00B4 0x03FC 0x0664 0x4 0x0 -#define MX6SX_PAD_KEY_COL4__GPIO2_IO_14 0x00B4 0x03FC 0x0000 0x5 0x0 -#define MX6SX_PAD_KEY_COL4__WEIM_CRE 0x00B4 0x03FC 0x0000 0x6 0x0 -#define MX6SX_PAD_KEY_COL4__SAI2_RX_BCLK 0x00B4 0x03FC 0x0808 0x7 0x0 -#define MX6SX_PAD_KEY_ROW0__KPP_ROW_0 0x00B8 0x0400 0x0000 0x0 0x0 -#define MX6SX_PAD_KEY_ROW0__USDHC3_WP 0x00B8 0x0400 0x0000 0x1 0x0 -#define MX6SX_PAD_KEY_ROW0__UART6_CTS_B 0x00B8 0x0400 0x0000 0x2 0x0 -#define MX6SX_PAD_KEY_ROW0__ECSPI1_MOSI 0x00B8 0x0400 0x0718 0x3 0x0 -#define MX6SX_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x00B8 0x0400 0x0660 0x4 0x0 -#define MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x00B8 0x0400 0x0000 0x5 0x0 -#define MX6SX_PAD_KEY_ROW0__SDMA_EXT_EVENT_0 0x00B8 0x0400 0x081C 0x6 0x1 -#define MX6SX_PAD_KEY_ROW0__SAI2_TX_DATA_0 0x00B8 0x0400 0x0000 0x7 0x0 -#define MX6SX_PAD_KEY_ROW0__GPU_IDLE 0x00B8 0x0400 0x0000 0x8 0x0 -#define MX6SX_PAD_KEY_ROW1__KPP_ROW_1 0x00BC 0x0404 0x0000 0x0 0x0 -#define MX6SX_PAD_KEY_ROW1__USDHC4_VSELECT 0x00BC 0x0404 0x0000 0x1 0x0 -#define MX6SX_PAD_KEY_ROW1__UART6_RX 0x00BC 0x0404 0x0858 0x2 0x3 -#define MX6SX_PAD_KEY_ROW1__UART6_TX 0x00BC 0x0404 0x0000 0x2 0x0 -#define MX6SX_PAD_KEY_ROW1__ECSPI1_SS0 0x00BC 0x0404 0x071C 0x3 0x0 -#define MX6SX_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x00BC 0x0404 0x065C 0x4 0x0 -#define MX6SX_PAD_KEY_ROW1__GPIO2_IO_16 0x00BC 0x0404 0x0000 0x5 0x0 -#define MX6SX_PAD_KEY_ROW1__WEIM_DATA_31 0x00BC 0x0404 0x0000 0x6 0x0 -#define MX6SX_PAD_KEY_ROW1__SAI2_RX_DATA_0 0x00BC 0x0404 0x080C 0x7 0x0 -#define MX6SX_PAD_KEY_ROW1__M4_NMI 0x00BC 0x0404 0x0000 0x8 0x0 -#define MX6SX_PAD_KEY_ROW2__KPP_ROW_2 0x00C0 0x0408 0x0000 0x0 0x0 -#define MX6SX_PAD_KEY_ROW2__USDHC4_WP 0x00C0 0x0408 0x0878 0x1 0x1 -#define MX6SX_PAD_KEY_ROW2__UART5_CTS_B 0x00C0 0x0408 0x0000 0x2 0x0 -#define MX6SX_PAD_KEY_ROW2__CAN1_RX 0x00C0 0x0408 0x068C 0x3 0x1 -#define MX6SX_PAD_KEY_ROW2__CANFD_RX1 0x00C0 0x0408 0x0694 0x4 0x1 -#define MX6SX_PAD_KEY_ROW2__GPIO2_IO_17 0x00C0 0x0408 0x0000 0x5 0x0 -#define MX6SX_PAD_KEY_ROW2__WEIM_DATA_29 0x00C0 0x0408 0x0000 0x6 0x0 -#define MX6SX_PAD_KEY_ROW2__ECSPI1_SS3 0x00C0 0x0408 0x0000 0x7 0x0 -#define MX6SX_PAD_KEY_ROW3__KPP_ROW_3 0x00C4 0x040C 0x0000 0x0 0x0 -#define MX6SX_PAD_KEY_ROW3__USDHC3_LCTL 0x00C4 0x040C 0x0000 0x1 0x0 -#define MX6SX_PAD_KEY_ROW3__UART5_RX 0x00C4 0x040C 0x0850 0x2 0x3 -#define MX6SX_PAD_KEY_ROW3__UART5_TX 0x00C4 0x040C 0x0000 0x2 0x0 -#define MX6SX_PAD_KEY_ROW3__CAN2_RX 0x00C4 0x040C 0x0690 0x3 0x1 -#define MX6SX_PAD_KEY_ROW3__CANFD_RX2 0x00C4 0x040C 0x0698 0x4 0x1 -#define MX6SX_PAD_KEY_ROW3__GPIO2_IO_18 0x00C4 0x040C 0x0000 0x5 0x0 -#define MX6SX_PAD_KEY_ROW3__WEIM_DTACK_B 0x00C4 0x040C 0x0000 0x6 0x0 -#define MX6SX_PAD_KEY_ROW3__ECSPI1_SS1 0x00C4 0x040C 0x0000 0x7 0x0 -#define MX6SX_PAD_KEY_ROW4__KPP_ROW_4 0x00C8 0x0410 0x0000 0x0 0x0 -#define MX6SX_PAD_KEY_ROW4__ENET2_MDIO 0x00C8 0x0410 0x0770 0x1 0x3 -#define MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x00C8 0x0410 0x07BC 0x2 0x2 -#define MX6SX_PAD_KEY_ROW4__USDHC1_LCTL 0x00C8 0x0410 0x0000 0x3 0x0 -#define MX6SX_PAD_KEY_ROW4__AUDMUX_AUD5_RXFS 0x00C8 0x0410 0x0668 0x4 0x0 -#define MX6SX_PAD_KEY_ROW4__GPIO2_IO_19 0x00C8 0x0410 0x0000 0x5 0x0 -#define MX6SX_PAD_KEY_ROW4__WEIM_ACLK_FREERUN 0x00C8 0x0410 0x0000 0x6 0x0 -#define MX6SX_PAD_KEY_ROW4__SAI2_RX_SYNC 0x00C8 0x0410 0x0810 0x7 0x0 -#define MX6SX_PAD_LCD1_CLK__LCDIF1_CLK 0x00CC 0x0414 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_CLK__LCDIF1_WR_RWN 0x00CC 0x0414 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_CLK__AUDMUX_AUD3_RXC 0x00CC 0x0414 0x0634 0x2 0x1 -#define MX6SX_PAD_LCD1_CLK__ENET1_1588_EVENT2_IN 0x00CC 0x0414 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_CLK__CSI1_DATA_16 0x00CC 0x0414 0x06DC 0x4 0x0 -#define MX6SX_PAD_LCD1_CLK__GPIO3_IO_0 0x00CC 0x0414 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_CLK__USDHC1_WP 0x00CC 0x0414 0x0868 0x6 0x0 -#define MX6SX_PAD_LCD1_CLK__SIM_M_HADDR_16 0x00CC 0x0414 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_CLK__VADC_TEST_0 0x00CC 0x0414 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_CLK__MMDC_DEBUG_0 0x00CC 0x0414 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x00D0 0x0418 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_DATA00__WEIM_CS1_B 0x00D0 0x0418 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_DATA00__M4_TRACE_0 0x00D0 0x0418 0x0000 0x2 0x0 -#define MX6SX_PAD_LCD1_DATA00__KITTEN_TRACE_0 0x00D0 0x0418 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_DATA00__CSI1_DATA_20 0x00D0 0x0418 0x06EC 0x4 0x0 -#define MX6SX_PAD_LCD1_DATA00__GPIO3_IO_1 0x00D0 0x0418 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_DATA00__SRC_BT_CFG_0 0x00D0 0x0418 0x0000 0x6 0x0 -#define MX6SX_PAD_LCD1_DATA00__SIM_M_HADDR_21 0x00D0 0x0418 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_DATA00__VADC_TEST_5 0x00D0 0x0418 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_DATA00__MMDC_DEBUG_5 0x00D0 0x0418 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x00D4 0x041C 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_DATA01__WEIM_CS2_B 0x00D4 0x041C 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_DATA01__M4_TRACE_1 0x00D4 0x041C 0x0000 0x2 0x0 -#define MX6SX_PAD_LCD1_DATA01__KITTEN_TRACE_1 0x00D4 0x041C 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_DATA01__CSI1_DATA_21 0x00D4 0x041C 0x06F0 0x4 0x0 -#define MX6SX_PAD_LCD1_DATA01__GPIO3_IO_2 0x00D4 0x041C 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_DATA01__SRC_BT_CFG_1 0x00D4 0x041C 0x0000 0x6 0x0 -#define MX6SX_PAD_LCD1_DATA01__SIM_M_HADDR_22 0x00D4 0x041C 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_DATA01__VADC_TEST_6 0x00D4 0x041C 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_DATA01__MMDC_DEBUG_6 0x00D4 0x041C 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x00D8 0x0420 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_DATA02__WEIM_CS3_B 0x00D8 0x0420 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_DATA02__M4_TRACE_2 0x00D8 0x0420 0x0000 0x2 0x0 -#define MX6SX_PAD_LCD1_DATA02__KITTEN_TRACE_2 0x00D8 0x0420 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_DATA02__CSI1_DATA_22 0x00D8 0x0420 0x06F4 0x4 0x0 -#define MX6SX_PAD_LCD1_DATA02__GPIO3_IO_3 0x00D8 0x0420 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_DATA02__SRC_BT_CFG_2 0x00D8 0x0420 0x0000 0x6 0x0 -#define MX6SX_PAD_LCD1_DATA02__SIM_M_HADDR_23 0x00D8 0x0420 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_DATA02__VADC_TEST_7 0x00D8 0x0420 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_DATA02__MMDC_DEBUG_7 0x00D8 0x0420 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x00DC 0x0424 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_DATA03__WEIM_ADDR_24 0x00DC 0x0424 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_DATA03__M4_TRACE_3 0x00DC 0x0424 0x0000 0x2 0x0 -#define MX6SX_PAD_LCD1_DATA03__KITTEN_TRACE_3 0x00DC 0x0424 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_DATA03__CSI1_DATA_23 0x00DC 0x0424 0x06F8 0x4 0x0 -#define MX6SX_PAD_LCD1_DATA03__GPIO3_IO_4 0x00DC 0x0424 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_DATA03__SRC_BT_CFG_3 0x00DC 0x0424 0x0000 0x6 0x0 -#define MX6SX_PAD_LCD1_DATA03__SIM_M_HADDR_24 0x00DC 0x0424 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_DATA03__VADC_TEST_8 0x00DC 0x0424 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_DATA03__MMDC_DEBUG_8 0x00DC 0x0424 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x00E0 0x0428 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_DATA04__WEIM_ADDR_25 0x00E0 0x0428 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_DATA04__KITTEN_TRACE_4 0x00E0 0x0428 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_DATA04__CSI1_VSYNC 0x00E0 0x0428 0x0708 0x4 0x1 -#define MX6SX_PAD_LCD1_DATA04__GPIO3_IO_5 0x00E0 0x0428 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_DATA04__SRC_BT_CFG_4 0x00E0 0x0428 0x0000 0x6 0x0 -#define MX6SX_PAD_LCD1_DATA04__SIM_M_HADDR_25 0x00E0 0x0428 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_DATA04__VADC_TEST_9 0x00E0 0x0428 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_DATA04__MMDC_DEBUG_9 0x00E0 0x0428 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x00E4 0x042C 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_DATA05__WEIM_ADDR_26 0x00E4 0x042C 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_DATA05__KITTEN_TRACE_5 0x00E4 0x042C 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_DATA05__CSI1_HSYNC 0x00E4 0x042C 0x0700 0x4 0x1 -#define MX6SX_PAD_LCD1_DATA05__GPIO3_IO_6 0x00E4 0x042C 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_DATA05__SRC_BT_CFG_5 0x00E4 0x042C 0x0000 0x6 0x0 -#define MX6SX_PAD_LCD1_DATA05__SIM_M_HADDR_26 0x00E4 0x042C 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_DATA05__VADC_TEST_10 0x00E4 0x042C 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_DATA05__MMDC_DEBUG_10 0x00E4 0x042C 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x00E8 0x0430 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_DATA06__WEIM_EB_B_2 0x00E8 0x0430 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_DATA06__KITTEN_TRACE_6 0x00E8 0x0430 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_DATA06__CSI1_PIXCLK 0x00E8 0x0430 0x0704 0x4 0x1 -#define MX6SX_PAD_LCD1_DATA06__GPIO3_IO_7 0x00E8 0x0430 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_DATA06__SRC_BT_CFG_6 0x00E8 0x0430 0x0000 0x6 0x0 -#define MX6SX_PAD_LCD1_DATA06__SIM_M_HADDR_27 0x00E8 0x0430 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_DATA06__VADC_TEST_11 0x00E8 0x0430 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_DATA06__MMDC_DEBUG_11 0x00E8 0x0430 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x00EC 0x0434 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_DATA07__WEIM_EB_B_3 0x00EC 0x0434 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_DATA07__KITTEN_TRACE_7 0x00EC 0x0434 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_DATA07__CSI1_MCLK 0x00EC 0x0434 0x0000 0x4 0x0 -#define MX6SX_PAD_LCD1_DATA07__GPIO3_IO_8 0x00EC 0x0434 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_DATA07__SRC_BT_CFG_7 0x00EC 0x0434 0x0000 0x6 0x0 -#define MX6SX_PAD_LCD1_DATA07__SIM_M_HADDR_28 0x00EC 0x0434 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_DATA07__VADC_TEST_12 0x00EC 0x0434 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_DATA07__MMDC_DEBUG_12 0x00EC 0x0434 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x00F0 0x0438 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_DATA08__WEIM_AD_8 0x00F0 0x0438 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_DATA08__KITTEN_TRACE_8 0x00F0 0x0438 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_DATA08__CSI1_DATA_9 0x00F0 0x0438 0x06C4 0x4 0x1 -#define MX6SX_PAD_LCD1_DATA08__GPIO3_IO_9 0x00F0 0x0438 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_DATA08__SRC_BT_CFG_8 0x00F0 0x0438 0x0000 0x6 0x0 -#define MX6SX_PAD_LCD1_DATA08__SIM_M_HADDR_29 0x00F0 0x0438 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_DATA08__VADC_TEST_13 0x00F0 0x0438 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_DATA08__MMDC_DEBUG_13 0x00F0 0x0438 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x00F4 0x043C 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_DATA09__WEIM_AD_9 0x00F4 0x043C 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_DATA09__KITTEN_TRACE_9 0x00F4 0x043C 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_DATA09__CSI1_DATA_8 0x00F4 0x043C 0x06C0 0x4 0x1 -#define MX6SX_PAD_LCD1_DATA09__GPIO3_IO_10 0x00F4 0x043C 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_DATA09__SRC_BT_CFG_9 0x00F4 0x043C 0x0000 0x6 0x0 -#define MX6SX_PAD_LCD1_DATA09__SIM_M_HADDR_30 0x00F4 0x043C 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_DATA09__VADC_TEST_14 0x00F4 0x043C 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_DATA09__MMDC_DEBUG_14 0x00F4 0x043C 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x00F8 0x0440 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_DATA10__WEIM_AD_10 0x00F8 0x0440 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_DATA10__KITTEN_TRACE_10 0x00F8 0x0440 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_DATA10__CSI1_DATA_7 0x00F8 0x0440 0x06BC 0x4 0x1 -#define MX6SX_PAD_LCD1_DATA10__GPIO3_IO_11 0x00F8 0x0440 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_DATA10__SRC_BT_CFG_10 0x00F8 0x0440 0x0000 0x6 0x0 -#define MX6SX_PAD_LCD1_DATA10__SIM_M_HADDR_31 0x00F8 0x0440 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_DATA10__VADC_TEST_15 0x00F8 0x0440 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_DATA10__MMDC_DEBUG_15 0x00F8 0x0440 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x00FC 0x0444 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_DATA11__WEIM_AD_11 0x00FC 0x0444 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_DATA11__KITTEN_TRACE_11 0x00FC 0x0444 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_DATA11__CSI1_DATA_6 0x00FC 0x0444 0x06B8 0x4 0x1 -#define MX6SX_PAD_LCD1_DATA11__GPIO3_IO_12 0x00FC 0x0444 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_DATA11__SRC_BT_CFG_11 0x00FC 0x0444 0x0000 0x6 0x0 -#define MX6SX_PAD_LCD1_DATA11__SIM_M_HBURST_0 0x00FC 0x0444 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_DATA11__VADC_TEST_16 0x00FC 0x0444 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_DATA11__MMDC_DEBUG_16 0x00FC 0x0444 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x0100 0x0448 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_DATA12__WEIM_AD_12 0x0100 0x0448 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_DATA12__KITTEN_TRACE_12 0x0100 0x0448 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_DATA12__CSI1_DATA_5 0x0100 0x0448 0x06B4 0x4 0x1 -#define MX6SX_PAD_LCD1_DATA12__GPIO3_IO_13 0x0100 0x0448 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_DATA12__SRC_BT_CFG_12 0x0100 0x0448 0x0000 0x6 0x0 -#define MX6SX_PAD_LCD1_DATA12__SIM_M_HBURST_1 0x0100 0x0448 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_DATA12__VADC_TEST_17 0x0100 0x0448 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_DATA12__MMDC_DEBUG_17 0x0100 0x0448 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x0104 0x044C 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_DATA13__WEIM_AD_13 0x0104 0x044C 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_DATA13__KITTEN_TRACE_13 0x0104 0x044C 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_DATA13__CSI1_DATA_4 0x0104 0x044C 0x06B0 0x4 0x1 -#define MX6SX_PAD_LCD1_DATA13__GPIO3_IO_14 0x0104 0x044C 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_DATA13__SRC_BT_CFG_13 0x0104 0x044C 0x0000 0x6 0x0 -#define MX6SX_PAD_LCD1_DATA13__SIM_M_HBURST_2 0x0104 0x044C 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_DATA13__VADC_TEST_18 0x0104 0x044C 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_DATA13__MMDC_DEBUG_18 0x0104 0x044C 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x0108 0x0450 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_DATA14__WEIM_AD_14 0x0108 0x0450 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_DATA14__KITTEN_TRACE_14 0x0108 0x0450 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_DATA14__CSI1_DATA_3 0x0108 0x0450 0x06AC 0x4 0x1 -#define MX6SX_PAD_LCD1_DATA14__GPIO3_IO_15 0x0108 0x0450 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_DATA14__SRC_BT_CFG_14 0x0108 0x0450 0x0000 0x6 0x0 -#define MX6SX_PAD_LCD1_DATA14__SIM_M_HMASTLOCK 0x0108 0x0450 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_DATA14__VADC_TEST_19 0x0108 0x0450 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_DATA14__MMDC_DEBUG_19 0x0108 0x0450 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x010C 0x0454 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_DATA15__WEIM_AD_15 0x010C 0x0454 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_DATA15__KITTEN_TRACE_15 0x010C 0x0454 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_DATA15__CSI1_DATA_2 0x010C 0x0454 0x06A8 0x4 0x1 -#define MX6SX_PAD_LCD1_DATA15__GPIO3_IO_16 0x010C 0x0454 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_DATA15__SRC_BT_CFG_15 0x010C 0x0454 0x0000 0x6 0x0 -#define MX6SX_PAD_LCD1_DATA15__SIM_M_HPROT_0 0x010C 0x0454 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_DATA15__VDEC_DEBUG_0 0x010C 0x0454 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_DATA15__MMDC_DEBUG_20 0x010C 0x0454 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x0110 0x0458 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_DATA16__WEIM_ADDR_16 0x0110 0x0458 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_DATA16__M4_TRACE_CLK 0x0110 0x0458 0x0000 0x2 0x0 -#define MX6SX_PAD_LCD1_DATA16__KITTEN_TRACE_CLK 0x0110 0x0458 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_DATA16__CSI1_DATA_1 0x0110 0x0458 0x06A4 0x4 0x0 -#define MX6SX_PAD_LCD1_DATA16__GPIO3_IO_17 0x0110 0x0458 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_DATA16__SRC_BT_CFG_24 0x0110 0x0458 0x0000 0x6 0x0 -#define MX6SX_PAD_LCD1_DATA16__SIM_M_HPROT_1 0x0110 0x0458 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_DATA16__VDEC_DEBUG_1 0x0110 0x0458 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_DATA16__MMDC_DEBUG_21 0x0110 0x0458 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x0114 0x045C 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_DATA17__WEIM_ADDR_17 0x0114 0x045C 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_DATA17__KITTEN_TRACE_CTL 0x0114 0x045C 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_DATA17__CSI1_DATA_0 0x0114 0x045C 0x06A0 0x4 0x0 -#define MX6SX_PAD_LCD1_DATA17__GPIO3_IO_18 0x0114 0x045C 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_DATA17__SRC_BT_CFG_25 0x0114 0x045C 0x0000 0x6 0x0 -#define MX6SX_PAD_LCD1_DATA17__SIM_M_HPROT_2 0x0114 0x045C 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_DATA17__VDEC_DEBUG_2 0x0114 0x045C 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_DATA17__MMDC_DEBUG_22 0x0114 0x045C 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x0118 0x0460 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_DATA18__WEIM_ADDR_18 0x0118 0x0460 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_DATA18__M4_EVENTO 0x0118 0x0460 0x0000 0x2 0x0 -#define MX6SX_PAD_LCD1_DATA18__KITTEN_EVENTO 0x0118 0x0460 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_DATA18__CSI1_DATA_15 0x0118 0x0460 0x06D8 0x4 0x0 -#define MX6SX_PAD_LCD1_DATA18__GPIO3_IO_19 0x0118 0x0460 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_DATA18__SRC_BT_CFG_26 0x0118 0x0460 0x0000 0x6 0x0 -#define MX6SX_PAD_LCD1_DATA18__SIM_M_HPROT_3 0x0118 0x0460 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_DATA18__VDEC_DEBUG_3 0x0118 0x0460 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_DATA18__MMDC_DEBUG_23 0x0118 0x0460 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x011C 0x0464 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_DATA19__WEIM_ADDR_19 0x011C 0x0464 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_DATA19__M4_TRACE_SWO 0x011C 0x0464 0x0000 0x2 0x0 -#define MX6SX_PAD_LCD1_DATA19__CSI1_DATA_14 0x011C 0x0464 0x06D4 0x4 0x0 -#define MX6SX_PAD_LCD1_DATA19__GPIO3_IO_20 0x011C 0x0464 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_DATA19__SRC_BT_CFG_27 0x011C 0x0464 0x0000 0x6 0x0 -#define MX6SX_PAD_LCD1_DATA19__SIM_M_HREADYOUT 0x011C 0x0464 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_DATA19__VDEC_DEBUG_4 0x011C 0x0464 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_DATA19__MMDC_DEBUG_24 0x011C 0x0464 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x0120 0x0468 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_DATA20__WEIM_ADDR_20 0x0120 0x0468 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_DATA20__PWM8_OUT 0x0120 0x0468 0x0000 0x2 0x0 -#define MX6SX_PAD_LCD1_DATA20__ENET1_1588_EVENT2_OUT 0x0120 0x0468 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_DATA20__CSI1_DATA_13 0x0120 0x0468 0x06D0 0x4 0x0 -#define MX6SX_PAD_LCD1_DATA20__GPIO3_IO_21 0x0120 0x0468 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_DATA20__SRC_BT_CFG_28 0x0120 0x0468 0x0000 0x6 0x0 -#define MX6SX_PAD_LCD1_DATA20__SIM_M_HRESP 0x0120 0x0468 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_DATA20__VDEC_DEBUG_5 0x0120 0x0468 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_DATA20__MMDC_DEBUG_25 0x0120 0x0468 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x0124 0x046C 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_DATA21__WEIM_ADDR_21 0x0124 0x046C 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_DATA21__PWM7_OUT 0x0124 0x046C 0x0000 0x2 0x0 -#define MX6SX_PAD_LCD1_DATA21__ENET1_1588_EVENT3_OUT 0x0124 0x046C 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_DATA21__CSI1_DATA_12 0x0124 0x046C 0x06CC 0x4 0x0 -#define MX6SX_PAD_LCD1_DATA21__GPIO3_IO_22 0x0124 0x046C 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_DATA21__SRC_BT_CFG_29 0x0124 0x046C 0x0000 0x6 0x0 -#define MX6SX_PAD_LCD1_DATA21__SIM_M_HSIZE_0 0x0124 0x046C 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_DATA21__VDEC_DEBUG_6 0x0124 0x046C 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_DATA21__MMDC_DEBUG_26 0x0124 0x046C 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x0128 0x0470 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_DATA22__WEIM_ADDR_22 0x0128 0x0470 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_DATA22__PWM6_OUT 0x0128 0x0470 0x0000 0x2 0x0 -#define MX6SX_PAD_LCD1_DATA22__ENET2_1588_EVENT2_OUT 0x0128 0x0470 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_DATA22__CSI1_DATA_11 0x0128 0x0470 0x06C8 0x4 0x0 -#define MX6SX_PAD_LCD1_DATA22__GPIO3_IO_23 0x0128 0x0470 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_DATA22__SRC_BT_CFG_30 0x0128 0x0470 0x0000 0x6 0x0 -#define MX6SX_PAD_LCD1_DATA22__SIM_M_HSIZE_1 0x0128 0x0470 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_DATA22__VDEC_DEBUG_7 0x0128 0x0470 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_DATA22__MMDC_DEBUG_27 0x0128 0x0470 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x012C 0x0474 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_DATA23__WEIM_ADDR_23 0x012C 0x0474 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_DATA23__PWM5_OUT 0x012C 0x0474 0x0000 0x2 0x0 -#define MX6SX_PAD_LCD1_DATA23__ENET2_1588_EVENT3_OUT 0x012C 0x0474 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_DATA23__CSI1_DATA_10 0x012C 0x0474 0x06FC 0x4 0x0 -#define MX6SX_PAD_LCD1_DATA23__GPIO3_IO_24 0x012C 0x0474 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_DATA23__SRC_BT_CFG_31 0x012C 0x0474 0x0000 0x6 0x0 -#define MX6SX_PAD_LCD1_DATA23__SIM_M_HSIZE_2 0x012C 0x0474 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_DATA23__VDEC_DEBUG_8 0x012C 0x0474 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_DATA23__MMDC_DEBUG_28 0x012C 0x0474 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x0130 0x0478 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_ENABLE__LCDIF1_RD_E 0x0130 0x0478 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_ENABLE__AUDMUX_AUD3_TXC 0x0130 0x0478 0x063C 0x2 0x1 -#define MX6SX_PAD_LCD1_ENABLE__ENET1_1588_EVENT3_IN 0x0130 0x0478 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_ENABLE__CSI1_DATA_17 0x0130 0x0478 0x06E0 0x4 0x0 -#define MX6SX_PAD_LCD1_ENABLE__GPIO3_IO_25 0x0130 0x0478 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_ENABLE__USDHC1_CD_B 0x0130 0x0478 0x0864 0x6 0x0 -#define MX6SX_PAD_LCD1_ENABLE__SIM_M_HADDR_17 0x0130 0x0478 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_ENABLE__VADC_TEST_1 0x0130 0x0478 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_ENABLE__MMDC_DEBUG_1 0x0130 0x0478 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x0134 0x047C 0x07E0 0x0 0x0 -#define MX6SX_PAD_LCD1_HSYNC__LCDIF1_RS 0x0134 0x047C 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_HSYNC__AUDMUX_AUD3_TXD 0x0134 0x047C 0x0630 0x2 0x1 -#define MX6SX_PAD_LCD1_HSYNC__ENET2_1588_EVENT2_IN 0x0134 0x047C 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_HSYNC__CSI1_DATA_18 0x0134 0x047C 0x06E4 0x4 0x0 -#define MX6SX_PAD_LCD1_HSYNC__GPIO3_IO_26 0x0134 0x047C 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_HSYNC__USDHC2_WP 0x0134 0x047C 0x0870 0x6 0x0 -#define MX6SX_PAD_LCD1_HSYNC__SIM_M_HADDR_18 0x0134 0x047C 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_HSYNC__VADC_TEST_2 0x0134 0x047C 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_HSYNC__MMDC_DEBUG_2 0x0134 0x047C 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_RESET__LCDIF1_RESET 0x0138 0x0480 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_RESET__LCDIF1_CS 0x0138 0x0480 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_RESET__AUDMUX_AUD3_RXD 0x0138 0x0480 0x062C 0x2 0x1 -#define MX6SX_PAD_LCD1_RESET__KITTEN_EVENTI 0x0138 0x0480 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_RESET__M4_EVENTI 0x0138 0x0480 0x0000 0x4 0x0 -#define MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x0138 0x0480 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_RESET__CCM_PMIC_RDY 0x0138 0x0480 0x069C 0x6 0x0 -#define MX6SX_PAD_LCD1_RESET__SIM_M_HADDR_20 0x0138 0x0480 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_RESET__VADC_TEST_4 0x0138 0x0480 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_RESET__MMDC_DEBUG_4 0x0138 0x0480 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x013C 0x0484 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_VSYNC__LCDIF1_BUSY 0x013C 0x0484 0x07E0 0x1 0x1 -#define MX6SX_PAD_LCD1_VSYNC__AUDMUX_AUD3_TXFS 0x013C 0x0484 0x0640 0x2 0x1 -#define MX6SX_PAD_LCD1_VSYNC__ENET2_1588_EVENT3_IN 0x013C 0x0484 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_VSYNC__CSI1_DATA_19 0x013C 0x0484 0x06E8 0x4 0x0 -#define MX6SX_PAD_LCD1_VSYNC__GPIO3_IO_28 0x013C 0x0484 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_VSYNC__USDHC2_CD_B 0x013C 0x0484 0x086C 0x6 0x0 -#define MX6SX_PAD_LCD1_VSYNC__SIM_M_HADDR_19 0x013C 0x0484 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_VSYNC__VADC_TEST_3 0x013C 0x0484 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_VSYNC__MMDC_DEBUG_3 0x013C 0x0484 0x0000 0x9 0x0 -#define MX6SX_PAD_NAND_ALE__RAWNAND_ALE 0x0140 0x0488 0x0000 0x0 0x0 -#define MX6SX_PAD_NAND_ALE__I2C3_SDA 0x0140 0x0488 0x07BC 0x1 0x0 -#define MX6SX_PAD_NAND_ALE__QSPI2_A_SS0_B 0x0140 0x0488 0x0000 0x2 0x0 -#define MX6SX_PAD_NAND_ALE__ECSPI2_SS0 0x0140 0x0488 0x072C 0x3 0x0 -#define MX6SX_PAD_NAND_ALE__ESAI_TX3_RX2 0x0140 0x0488 0x079C 0x4 0x0 -#define MX6SX_PAD_NAND_ALE__GPIO4_IO_0 0x0140 0x0488 0x0000 0x5 0x0 -#define MX6SX_PAD_NAND_ALE__WEIM_CS0_B 0x0140 0x0488 0x0000 0x6 0x0 -#define MX6SX_PAD_NAND_ALE__TPSMP_HDATA_0 0x0140 0x0488 0x0000 0x7 0x0 -#define MX6SX_PAD_NAND_ALE__ANATOP_USBPHY1_TSTI_TX_EN 0x0140 0x0488 0x0000 0x8 0x0 -#define MX6SX_PAD_NAND_ALE__SDMA_DEBUG_PC_12 0x0140 0x0488 0x0000 0x9 0x0 -#define MX6SX_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0144 0x048C 0x0000 0x0 0x0 -#define MX6SX_PAD_NAND_CE0_B__USDHC2_VSELECT 0x0144 0x048C 0x0000 0x1 0x0 -#define MX6SX_PAD_NAND_CE0_B__QSPI2_A_DATA_2 0x0144 0x048C 0x0000 0x2 0x0 -#define MX6SX_PAD_NAND_CE0_B__AUDMUX_AUD4_TXC 0x0144 0x048C 0x0654 0x3 0x0 -#define MX6SX_PAD_NAND_CE0_B__ESAI_TX_CLK 0x0144 0x048C 0x078C 0x4 0x0 -#define MX6SX_PAD_NAND_CE0_B__GPIO4_IO_1 0x0144 0x048C 0x0000 0x5 0x0 -#define MX6SX_PAD_NAND_CE0_B__WEIM_LBA_B 0x0144 0x048C 0x0000 0x6 0x0 -#define MX6SX_PAD_NAND_CE0_B__TPSMP_HDATA_3 0x0144 0x048C 0x0000 0x7 0x0 -#define MX6SX_PAD_NAND_CE0_B__ANATOP_USBPHY1_TSTI_TX_HIZ 0x0144 0x048C 0x0000 0x8 0x0 -#define MX6SX_PAD_NAND_CE0_B__SDMA_DEBUG_PC_9 0x0144 0x048C 0x0000 0x9 0x0 -#define MX6SX_PAD_NAND_CE1_B__RAWNAND_CE1_B 0x0148 0x0490 0x0000 0x0 0x0 -#define MX6SX_PAD_NAND_CE1_B__USDHC3_RESET_B 0x0148 0x0490 0x0000 0x1 0x0 -#define MX6SX_PAD_NAND_CE1_B__QSPI2_A_DATA_3 0x0148 0x0490 0x0000 0x2 0x0 -#define MX6SX_PAD_NAND_CE1_B__AUDMUX_AUD4_TXD 0x0148 0x0490 0x0648 0x3 0x0 -#define MX6SX_PAD_NAND_CE1_B__ESAI_TX0 0x0148 0x0490 0x0790 0x4 0x0 -#define MX6SX_PAD_NAND_CE1_B__GPIO4_IO_2 0x0148 0x0490 0x0000 0x5 0x0 -#define MX6SX_PAD_NAND_CE1_B__WEIM_OE 0x0148 0x0490 0x0000 0x6 0x0 -#define MX6SX_PAD_NAND_CE1_B__TPSMP_HDATA_4 0x0148 0x0490 0x0000 0x7 0x0 -#define MX6SX_PAD_NAND_CE1_B__ANATOP_USBPHY1_TSTI_TX_LS_MODE 0x0148 0x0490 0x0000 0x8 0x0 -#define MX6SX_PAD_NAND_CE1_B__SDMA_DEBUG_PC_8 0x0148 0x0490 0x0000 0x9 0x0 -#define MX6SX_PAD_NAND_CLE__RAWNAND_CLE 0x014C 0x0494 0x0000 0x0 0x0 -#define MX6SX_PAD_NAND_CLE__I2C3_SCL 0x014C 0x0494 0x07B8 0x1 0x0 -#define MX6SX_PAD_NAND_CLE__QSPI2_A_SCLK 0x014C 0x0494 0x0000 0x2 0x0 -#define MX6SX_PAD_NAND_CLE__ECSPI2_SCLK 0x014C 0x0494 0x0720 0x3 0x0 -#define MX6SX_PAD_NAND_CLE__ESAI_TX2_RX3 0x014C 0x0494 0x0798 0x4 0x0 -#define MX6SX_PAD_NAND_CLE__GPIO4_IO_3 0x014C 0x0494 0x0000 0x5 0x0 -#define MX6SX_PAD_NAND_CLE__WEIM_BCLK 0x014C 0x0494 0x0000 0x6 0x0 -#define MX6SX_PAD_NAND_CLE__TPSMP_CLK 0x014C 0x0494 0x0000 0x7 0x0 -#define MX6SX_PAD_NAND_CLE__ANATOP_USBPHY1_TSTI_TX_DP 0x014C 0x0494 0x0000 0x8 0x0 -#define MX6SX_PAD_NAND_CLE__SDMA_DEBUG_PC_13 0x014C 0x0494 0x0000 0x9 0x0 -#define MX6SX_PAD_NAND_DATA00__RAWNAND_DATA00 0x0150 0x0498 0x0000 0x0 0x0 -#define MX6SX_PAD_NAND_DATA00__USDHC1_DATA4 0x0150 0x0498 0x0000 0x1 0x0 -#define MX6SX_PAD_NAND_DATA00__QSPI2_B_DATA_1 0x0150 0x0498 0x0000 0x2 0x0 -#define MX6SX_PAD_NAND_DATA00__ECSPI5_MISO 0x0150 0x0498 0x0754 0x3 0x0 -#define MX6SX_PAD_NAND_DATA00__ESAI_RX_CLK 0x0150 0x0498 0x0788 0x4 0x0 -#define MX6SX_PAD_NAND_DATA00__GPIO4_IO_4 0x0150 0x0498 0x0000 0x5 0x0 -#define MX6SX_PAD_NAND_DATA00__WEIM_AD_0 0x0150 0x0498 0x0000 0x6 0x0 -#define MX6SX_PAD_NAND_DATA00__TPSMP_HDATA_7 0x0150 0x0498 0x0000 0x7 0x0 -#define MX6SX_PAD_NAND_DATA00__ANATOP_USBPHY1_TSTO_RX_DISCON_DET 0x0150 0x0498 0x0000 0x8 0x0 -#define MX6SX_PAD_NAND_DATA00__SDMA_DEBUG_EVT_CHN_LINES_5 0x0150 0x0498 0x0000 0x9 0x0 -#define MX6SX_PAD_NAND_DATA01__RAWNAND_DATA01 0x0154 0x049C 0x0000 0x0 0x0 -#define MX6SX_PAD_NAND_DATA01__USDHC1_DATA5 0x0154 0x049C 0x0000 0x1 0x0 -#define MX6SX_PAD_NAND_DATA01__QSPI2_B_DATA_0 0x0154 0x049C 0x0000 0x2 0x0 -#define MX6SX_PAD_NAND_DATA01__ECSPI5_MOSI 0x0154 0x049C 0x0758 0x3 0x0 -#define MX6SX_PAD_NAND_DATA01__ESAI_RX_FS 0x0154 0x049C 0x0778 0x4 0x0 -#define MX6SX_PAD_NAND_DATA01__GPIO4_IO_5 0x0154 0x049C 0x0000 0x5 0x0 -#define MX6SX_PAD_NAND_DATA01__WEIM_AD_1 0x0154 0x049C 0x0000 0x6 0x0 -#define MX6SX_PAD_NAND_DATA01__TPSMP_HDATA_8 0x0154 0x049C 0x0000 0x7 0x0 -#define MX6SX_PAD_NAND_DATA01__ANATOP_USBPHY1_TSTO_RX_HS_RXD 0x0154 0x049C 0x0000 0x8 0x0 -#define MX6SX_PAD_NAND_DATA01__SDMA_DEBUG_EVT_CHN_LINES_4 0x0154 0x049C 0x0000 0x9 0x0 -#define MX6SX_PAD_NAND_DATA02__RAWNAND_DATA02 0x0158 0x04A0 0x0000 0x0 0x0 -#define MX6SX_PAD_NAND_DATA02__USDHC1_DATA6 0x0158 0x04A0 0x0000 0x1 0x0 -#define MX6SX_PAD_NAND_DATA02__QSPI2_B_SCLK 0x0158 0x04A0 0x0000 0x2 0x0 -#define MX6SX_PAD_NAND_DATA02__ECSPI5_SCLK 0x0158 0x04A0 0x0750 0x3 0x0 -#define MX6SX_PAD_NAND_DATA02__ESAI_TX_HF_CLK 0x0158 0x04A0 0x0784 0x4 0x0 -#define MX6SX_PAD_NAND_DATA02__GPIO4_IO_6 0x0158 0x04A0 0x0000 0x5 0x0 -#define MX6SX_PAD_NAND_DATA02__WEIM_AD_2 0x0158 0x04A0 0x0000 0x6 0x0 -#define MX6SX_PAD_NAND_DATA02__TPSMP_HDATA_9 0x0158 0x04A0 0x0000 0x7 0x0 -#define MX6SX_PAD_NAND_DATA02__ANATOP_USBPHY2_TSTO_PLL_CLK20DIV 0x0158 0x04A0 0x0000 0x8 0x0 -#define MX6SX_PAD_NAND_DATA02__SDMA_DEBUG_EVT_CHN_LINES_3 0x0158 0x04A0 0x0000 0x9 0x0 -#define MX6SX_PAD_NAND_DATA03__RAWNAND_DATA03 0x015C 0x04A4 0x0000 0x0 0x0 -#define MX6SX_PAD_NAND_DATA03__USDHC1_DATA7 0x015C 0x04A4 0x0000 0x1 0x0 -#define MX6SX_PAD_NAND_DATA03__QSPI2_B_SS0_B 0x015C 0x04A4 0x0000 0x2 0x0 -#define MX6SX_PAD_NAND_DATA03__ECSPI5_SS0 0x015C 0x04A4 0x075C 0x3 0x0 -#define MX6SX_PAD_NAND_DATA03__ESAI_RX_HF_CLK 0x015C 0x04A4 0x0780 0x4 0x0 -#define MX6SX_PAD_NAND_DATA03__GPIO4_IO_7 0x015C 0x04A4 0x0000 0x5 0x0 -#define MX6SX_PAD_NAND_DATA03__WEIM_AD_3 0x015C 0x04A4 0x0000 0x6 0x0 -#define MX6SX_PAD_NAND_DATA03__TPSMP_HDATA_10 0x015C 0x04A4 0x0000 0x7 0x0 -#define MX6SX_PAD_NAND_DATA03__ANATOP_USBPHY1_TSTO_RX_SQUELCH 0x015C 0x04A4 0x0000 0x8 0x0 -#define MX6SX_PAD_NAND_DATA03__SDMA_DEBUG_EVT_CHN_LINES_6 0x015C 0x04A4 0x0000 0x9 0x0 -#define MX6SX_PAD_NAND_DATA04__RAWNAND_DATA04 0x0160 0x04A8 0x0000 0x0 0x0 -#define MX6SX_PAD_NAND_DATA04__USDHC2_DATA4 0x0160 0x04A8 0x0000 0x1 0x0 -#define MX6SX_PAD_NAND_DATA04__QSPI2_B_SS1_B 0x0160 0x04A8 0x0000 0x2 0x0 -#define MX6SX_PAD_NAND_DATA04__UART3_RTS_B 0x0160 0x04A8 0x083C 0x3 0x0 -#define MX6SX_PAD_NAND_DATA04__AUDMUX_AUD4_RXFS 0x0160 0x04A8 0x0650 0x4 0x0 -#define MX6SX_PAD_NAND_DATA04__GPIO4_IO_8 0x0160 0x04A8 0x0000 0x5 0x0 -#define MX6SX_PAD_NAND_DATA04__WEIM_AD_4 0x0160 0x04A8 0x0000 0x6 0x0 -#define MX6SX_PAD_NAND_DATA04__TPSMP_HDATA_11 0x0160 0x04A8 0x0000 0x7 0x0 -#define MX6SX_PAD_NAND_DATA04__ANATOP_USBPHY2_TSTO_RX_SQUELCH 0x0160 0x04A8 0x0000 0x8 0x0 -#define MX6SX_PAD_NAND_DATA04__SDMA_DEBUG_CORE_STATE_0 0x0160 0x04A8 0x0000 0x9 0x0 -#define MX6SX_PAD_NAND_DATA05__RAWNAND_DATA05 0x0164 0x04AC 0x0000 0x0 0x0 -#define MX6SX_PAD_NAND_DATA05__USDHC2_DATA5 0x0164 0x04AC 0x0000 0x1 0x0 -#define MX6SX_PAD_NAND_DATA05__QSPI2_B_DQS 0x0164 0x04AC 0x0000 0x2 0x0 -#define MX6SX_PAD_NAND_DATA05__UART3_CTS_B 0x0164 0x04AC 0x0000 0x3 0x0 -#define MX6SX_PAD_NAND_DATA05__AUDMUX_AUD4_RXC 0x0164 0x04AC 0x064C 0x4 0x0 -#define MX6SX_PAD_NAND_DATA05__GPIO4_IO_9 0x0164 0x04AC 0x0000 0x5 0x0 -#define MX6SX_PAD_NAND_DATA05__WEIM_AD_5 0x0164 0x04AC 0x0000 0x6 0x0 -#define MX6SX_PAD_NAND_DATA05__TPSMP_HDATA_12 0x0164 0x04AC 0x0000 0x7 0x0 -#define MX6SX_PAD_NAND_DATA05__ANATOP_USBPHY2_TSTO_RX_DISCON_DET 0x0164 0x04AC 0x0000 0x8 0x0 -#define MX6SX_PAD_NAND_DATA05__SDMA_DEBUG_CORE_STATE_1 0x0164 0x04AC 0x0000 0x9 0x0 -#define MX6SX_PAD_NAND_DATA06__RAWNAND_DATA06 0x0168 0x04B0 0x0000 0x0 0x0 -#define MX6SX_PAD_NAND_DATA06__USDHC2_DATA6 0x0168 0x04B0 0x0000 0x1 0x0 -#define MX6SX_PAD_NAND_DATA06__QSPI2_A_SS1_B 0x0168 0x04B0 0x0000 0x2 0x0 -#define MX6SX_PAD_NAND_DATA06__UART3_RX 0x0168 0x04B0 0x0840 0x3 0x0 -#define MX6SX_PAD_NAND_DATA06__UART3_TX 0x0168 0x04B0 0x0000 0x3 0x0 -#define MX6SX_PAD_NAND_DATA06__PWM3_OUT 0x0168 0x04B0 0x0000 0x4 0x0 -#define MX6SX_PAD_NAND_DATA06__GPIO4_IO_10 0x0168 0x04B0 0x0000 0x5 0x0 -#define MX6SX_PAD_NAND_DATA06__WEIM_AD_6 0x0168 0x04B0 0x0000 0x6 0x0 -#define MX6SX_PAD_NAND_DATA06__TPSMP_HDATA_13 0x0168 0x04B0 0x0000 0x7 0x0 -#define MX6SX_PAD_NAND_DATA06__ANATOP_USBPHY2_TSTO_RX_FS_RXD 0x0168 0x04B0 0x0000 0x8 0x0 -#define MX6SX_PAD_NAND_DATA06__SDMA_DEBUG_CORE_STATE_2 0x0168 0x04B0 0x0000 0x9 0x0 -#define MX6SX_PAD_NAND_DATA07__RAWNAND_DATA07 0x016C 0x04B4 0x0000 0x0 0x0 -#define MX6SX_PAD_NAND_DATA07__USDHC2_DATA7 0x016C 0x04B4 0x0000 0x1 0x0 -#define MX6SX_PAD_NAND_DATA07__QSPI2_A_DQS 0x016C 0x04B4 0x0000 0x2 0x0 -#define MX6SX_PAD_NAND_DATA07__UART3_RX 0x016C 0x04B4 0x0840 0x3 0x1 -#define MX6SX_PAD_NAND_DATA07__UART3_TX 0x016C 0x04B4 0x0000 0x3 0x0 -#define MX6SX_PAD_NAND_DATA07__PWM4_OUT 0x016C 0x04B4 0x0000 0x4 0x0 -#define MX6SX_PAD_NAND_DATA07__GPIO4_IO_11 0x016C 0x04B4 0x0000 0x5 0x0 -#define MX6SX_PAD_NAND_DATA07__WEIM_AD_7 0x016C 0x04B4 0x0000 0x6 0x0 -#define MX6SX_PAD_NAND_DATA07__TPSMP_HDATA_14 0x016C 0x04B4 0x0000 0x7 0x0 -#define MX6SX_PAD_NAND_DATA07__ANATOP_USBPHY1_TSTO_RX_FS_RXD 0x016C 0x04B4 0x0000 0x8 0x0 -#define MX6SX_PAD_NAND_DATA07__SDMA_DEBUG_CORE_STATE_3 0x016C 0x04B4 0x0000 0x9 0x0 -#define MX6SX_PAD_NAND_RE_B__RAWNAND_RE_B 0x0170 0x04B8 0x0000 0x0 0x0 -#define MX6SX_PAD_NAND_RE_B__USDHC2_RESET_B 0x0170 0x04B8 0x0000 0x1 0x0 -#define MX6SX_PAD_NAND_RE_B__QSPI2_B_DATA_3 0x0170 0x04B8 0x0000 0x2 0x0 -#define MX6SX_PAD_NAND_RE_B__AUDMUX_AUD4_TXFS 0x0170 0x04B8 0x0658 0x3 0x0 -#define MX6SX_PAD_NAND_RE_B__ESAI_TX_FS 0x0170 0x04B8 0x077C 0x4 0x0 -#define MX6SX_PAD_NAND_RE_B__GPIO4_IO_12 0x0170 0x04B8 0x0000 0x5 0x0 -#define MX6SX_PAD_NAND_RE_B__WEIM_RW 0x0170 0x04B8 0x0000 0x6 0x0 -#define MX6SX_PAD_NAND_RE_B__TPSMP_HDATA_5 0x0170 0x04B8 0x0000 0x7 0x0 -#define MX6SX_PAD_NAND_RE_B__ANATOP_USBPHY2_TSTO_RX_HS_RXD 0x0170 0x04B8 0x0000 0x8 0x0 -#define MX6SX_PAD_NAND_RE_B__SDMA_DEBUG_PC_7 0x0170 0x04B8 0x0000 0x9 0x0 -#define MX6SX_PAD_NAND_READY_B__RAWNAND_READY_B 0x0174 0x04BC 0x0000 0x0 0x0 -#define MX6SX_PAD_NAND_READY_B__USDHC1_VSELECT 0x0174 0x04BC 0x0000 0x1 0x0 -#define MX6SX_PAD_NAND_READY_B__QSPI2_A_DATA_1 0x0174 0x04BC 0x0000 0x2 0x0 -#define MX6SX_PAD_NAND_READY_B__ECSPI2_MISO 0x0174 0x04BC 0x0724 0x3 0x0 -#define MX6SX_PAD_NAND_READY_B__ESAI_TX1 0x0174 0x04BC 0x0794 0x4 0x0 -#define MX6SX_PAD_NAND_READY_B__GPIO4_IO_13 0x0174 0x04BC 0x0000 0x5 0x0 -#define MX6SX_PAD_NAND_READY_B__WEIM_EB_B_1 0x0174 0x04BC 0x0000 0x6 0x0 -#define MX6SX_PAD_NAND_READY_B__TPSMP_HDATA_2 0x0174 0x04BC 0x0000 0x7 0x0 -#define MX6SX_PAD_NAND_READY_B__ANATOP_USBPHY1_TSTI_TX_DN 0x0174 0x04BC 0x0000 0x8 0x0 -#define MX6SX_PAD_NAND_READY_B__SDMA_DEBUG_PC_10 0x0174 0x04BC 0x0000 0x9 0x0 -#define MX6SX_PAD_NAND_WE_B__RAWNAND_WE_B 0x0178 0x04C0 0x0000 0x0 0x0 -#define MX6SX_PAD_NAND_WE_B__USDHC4_VSELECT 0x0178 0x04C0 0x0000 0x1 0x0 -#define MX6SX_PAD_NAND_WE_B__QSPI2_B_DATA_2 0x0178 0x04C0 0x0000 0x2 0x0 -#define MX6SX_PAD_NAND_WE_B__AUDMUX_AUD4_RXD 0x0178 0x04C0 0x0644 0x3 0x0 -#define MX6SX_PAD_NAND_WE_B__ESAI_TX5_RX0 0x0178 0x04C0 0x07A4 0x4 0x0 -#define MX6SX_PAD_NAND_WE_B__GPIO4_IO_14 0x0178 0x04C0 0x0000 0x5 0x0 -#define MX6SX_PAD_NAND_WE_B__WEIM_WAIT 0x0178 0x04C0 0x0000 0x6 0x0 -#define MX6SX_PAD_NAND_WE_B__TPSMP_HDATA_6 0x0178 0x04C0 0x0000 0x7 0x0 -#define MX6SX_PAD_NAND_WE_B__ANATOP_USBPHY1_TSTO_PLL_CLK20DIV 0x0178 0x04C0 0x0000 0x8 0x0 -#define MX6SX_PAD_NAND_WE_B__SDMA_DEBUG_PC_6 0x0178 0x04C0 0x0000 0x9 0x0 -#define MX6SX_PAD_NAND_WP_B__RAWNAND_WP_B 0x017C 0x04C4 0x0000 0x0 0x0 -#define MX6SX_PAD_NAND_WP_B__USDHC1_RESET_B 0x017C 0x04C4 0x0000 0x1 0x0 -#define MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0 0x017C 0x04C4 0x0000 0x2 0x0 -#define MX6SX_PAD_NAND_WP_B__ECSPI2_MOSI 0x017C 0x04C4 0x0728 0x3 0x0 -#define MX6SX_PAD_NAND_WP_B__ESAI_TX4_RX1 0x017C 0x04C4 0x07A0 0x4 0x0 -#define MX6SX_PAD_NAND_WP_B__GPIO4_IO_15 0x017C 0x04C4 0x0000 0x5 0x0 -#define MX6SX_PAD_NAND_WP_B__WEIM_EB_B_0 0x017C 0x04C4 0x0000 0x6 0x0 -#define MX6SX_PAD_NAND_WP_B__TPSMP_HDATA_1 0x017C 0x04C4 0x0000 0x7 0x0 -#define MX6SX_PAD_NAND_WP_B__ANATOP_USBPHY1_TSTI_TX_HS_MODE 0x017C 0x04C4 0x0000 0x8 0x0 -#define MX6SX_PAD_NAND_WP_B__SDMA_DEBUG_PC_11 0x017C 0x04C4 0x0000 0x9 0x0 -#define MX6SX_PAD_QSPI1A_DATA0__QSPI1_A_DATA_0 0x0180 0x04C8 0x0000 0x0 0x0 -#define MX6SX_PAD_QSPI1A_DATA0__USB_OTG2_OC 0x0180 0x04C8 0x085C 0x1 0x2 -#define MX6SX_PAD_QSPI1A_DATA0__ECSPI1_MOSI 0x0180 0x04C8 0x0718 0x2 0x1 -#define MX6SX_PAD_QSPI1A_DATA0__ESAI_TX4_RX1 0x0180 0x04C8 0x07A0 0x3 0x2 -#define MX6SX_PAD_QSPI1A_DATA0__CSI1_DATA_14 0x0180 0x04C8 0x06D4 0x4 0x1 -#define MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16 0x0180 0x04C8 0x0000 0x5 0x0 -#define MX6SX_PAD_QSPI1A_DATA0__WEIM_DATA_6 0x0180 0x04C8 0x0000 0x6 0x0 -#define MX6SX_PAD_QSPI1A_DATA0__SIM_M_HADDR_3 0x0180 0x04C8 0x0000 0x7 0x0 -#define MX6SX_PAD_QSPI1A_DATA0__SDMA_DEBUG_BUS_DEVICE_3 0x0180 0x04C8 0x0000 0x9 0x0 -#define MX6SX_PAD_QSPI1A_DATA1__QSPI1_A_DATA_1 0x0184 0x04CC 0x0000 0x0 0x0 -#define MX6SX_PAD_QSPI1A_DATA1__ANATOP_OTG1_ID 0x0184 0x04CC 0x0624 0x1 0x2 -#define MX6SX_PAD_QSPI1A_DATA1__ECSPI1_MISO 0x0184 0x04CC 0x0714 0x2 0x1 -#define MX6SX_PAD_QSPI1A_DATA1__ESAI_TX1 0x0184 0x04CC 0x0794 0x3 0x2 -#define MX6SX_PAD_QSPI1A_DATA1__CSI1_DATA_13 0x0184 0x04CC 0x06D0 0x4 0x1 -#define MX6SX_PAD_QSPI1A_DATA1__GPIO4_IO_17 0x0184 0x04CC 0x0000 0x5 0x0 -#define MX6SX_PAD_QSPI1A_DATA1__WEIM_DATA_5 0x0184 0x04CC 0x0000 0x6 0x0 -#define MX6SX_PAD_QSPI1A_DATA1__SIM_M_HADDR_4 0x0184 0x04CC 0x0000 0x7 0x0 -#define MX6SX_PAD_QSPI1A_DATA1__SDMA_DEBUG_PC_0 0x0184 0x04CC 0x0000 0x9 0x0 -#define MX6SX_PAD_QSPI1A_DATA2__QSPI1_A_DATA_2 0x0188 0x04D0 0x0000 0x0 0x0 -#define MX6SX_PAD_QSPI1A_DATA2__USB_OTG1_PWR 0x0188 0x04D0 0x0000 0x1 0x0 -#define MX6SX_PAD_QSPI1A_DATA2__ECSPI5_SS1 0x0188 0x04D0 0x0000 0x2 0x0 -#define MX6SX_PAD_QSPI1A_DATA2__ESAI_TX_CLK 0x0188 0x04D0 0x078C 0x3 0x2 -#define MX6SX_PAD_QSPI1A_DATA2__CSI1_DATA_12 0x0188 0x04D0 0x06CC 0x4 0x1 -#define MX6SX_PAD_QSPI1A_DATA2__GPIO4_IO_18 0x0188 0x04D0 0x0000 0x5 0x0 -#define MX6SX_PAD_QSPI1A_DATA2__WEIM_DATA_4 0x0188 0x04D0 0x0000 0x6 0x0 -#define MX6SX_PAD_QSPI1A_DATA2__SIM_M_HADDR_6 0x0188 0x04D0 0x0000 0x7 0x0 -#define MX6SX_PAD_QSPI1A_DATA2__SDMA_DEBUG_PC_1 0x0188 0x04D0 0x0000 0x9 0x0 -#define MX6SX_PAD_QSPI1A_DATA3__QSPI1_A_DATA_3 0x018C 0x04D4 0x0000 0x0 0x0 -#define MX6SX_PAD_QSPI1A_DATA3__USB_OTG1_OC 0x018C 0x04D4 0x0860 0x1 0x2 -#define MX6SX_PAD_QSPI1A_DATA3__ECSPI5_SS2 0x018C 0x04D4 0x0000 0x2 0x0 -#define MX6SX_PAD_QSPI1A_DATA3__ESAI_TX0 0x018C 0x04D4 0x0790 0x3 0x2 -#define MX6SX_PAD_QSPI1A_DATA3__CSI1_DATA_11 0x018C 0x04D4 0x06C8 0x4 0x1 -#define MX6SX_PAD_QSPI1A_DATA3__GPIO4_IO_19 0x018C 0x04D4 0x0000 0x5 0x0 -#define MX6SX_PAD_QSPI1A_DATA3__WEIM_DATA_3 0x018C 0x04D4 0x0000 0x6 0x0 -#define MX6SX_PAD_QSPI1A_DATA3__SIM_M_HADDR_7 0x018C 0x04D4 0x0000 0x7 0x0 -#define MX6SX_PAD_QSPI1A_DATA3__SDMA_DEBUG_PC_2 0x018C 0x04D4 0x0000 0x9 0x0 -#define MX6SX_PAD_QSPI1A_DQS__QSPI1_A_DQS 0x0190 0x04D8 0x0000 0x0 0x0 -#define MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x0190 0x04D8 0x0000 0x1 0x0 -#define MX6SX_PAD_QSPI1A_DQS__CANFD_TX2 0x0190 0x04D8 0x0000 0x2 0x0 -#define MX6SX_PAD_QSPI1A_DQS__ECSPI5_MOSI 0x0190 0x04D8 0x0758 0x3 0x1 -#define MX6SX_PAD_QSPI1A_DQS__CSI1_DATA_15 0x0190 0x04D8 0x06D8 0x4 0x1 -#define MX6SX_PAD_QSPI1A_DQS__GPIO4_IO_20 0x0190 0x04D8 0x0000 0x5 0x0 -#define MX6SX_PAD_QSPI1A_DQS__WEIM_DATA_7 0x0190 0x04D8 0x0000 0x6 0x0 -#define MX6SX_PAD_QSPI1A_DQS__SIM_M_HADDR_13 0x0190 0x04D8 0x0000 0x7 0x0 -#define MX6SX_PAD_QSPI1A_DQS__SDMA_DEBUG_BUS_DEVICE_4 0x0190 0x04D8 0x0000 0x9 0x0 -#define MX6SX_PAD_QSPI1A_SCLK__QSPI1_A_SCLK 0x0194 0x04DC 0x0000 0x0 0x0 -#define MX6SX_PAD_QSPI1A_SCLK__ANATOP_OTG2_ID 0x0194 0x04DC 0x0628 0x1 0x2 -#define MX6SX_PAD_QSPI1A_SCLK__ECSPI1_SCLK 0x0194 0x04DC 0x0710 0x2 0x1 -#define MX6SX_PAD_QSPI1A_SCLK__ESAI_TX2_RX3 0x0194 0x04DC 0x0798 0x3 0x2 -#define MX6SX_PAD_QSPI1A_SCLK__CSI1_DATA_1 0x0194 0x04DC 0x06A4 0x4 0x1 -#define MX6SX_PAD_QSPI1A_SCLK__GPIO4_IO_21 0x0194 0x04DC 0x0000 0x5 0x0 -#define MX6SX_PAD_QSPI1A_SCLK__WEIM_DATA_0 0x0194 0x04DC 0x0000 0x6 0x0 -#define MX6SX_PAD_QSPI1A_SCLK__SIM_M_HADDR_0 0x0194 0x04DC 0x0000 0x7 0x0 -#define MX6SX_PAD_QSPI1A_SCLK__SDMA_DEBUG_PC_5 0x0194 0x04DC 0x0000 0x9 0x0 -#define MX6SX_PAD_QSPI1A_SS0_B__QSPI1_A_SS0_B 0x0198 0x04E0 0x0000 0x0 0x0 -#define MX6SX_PAD_QSPI1A_SS0_B__USB_OTG2_PWR 0x0198 0x04E0 0x0000 0x1 0x0 -#define MX6SX_PAD_QSPI1A_SS0_B__ECSPI1_SS0 0x0198 0x04E0 0x071C 0x2 0x1 -#define MX6SX_PAD_QSPI1A_SS0_B__ESAI_TX3_RX2 0x0198 0x04E0 0x079C 0x3 0x2 -#define MX6SX_PAD_QSPI1A_SS0_B__CSI1_DATA_0 0x0198 0x04E0 0x06A0 0x4 0x1 -#define MX6SX_PAD_QSPI1A_SS0_B__GPIO4_IO_22 0x0198 0x04E0 0x0000 0x5 0x0 -#define MX6SX_PAD_QSPI1A_SS0_B__WEIM_DATA_1 0x0198 0x04E0 0x0000 0x6 0x0 -#define MX6SX_PAD_QSPI1A_SS0_B__SIM_M_HADDR_1 0x0198 0x04E0 0x0000 0x7 0x0 -#define MX6SX_PAD_QSPI1A_SS0_B__SDMA_DEBUG_PC_4 0x0198 0x04E0 0x0000 0x9 0x0 -#define MX6SX_PAD_QSPI1A_SS1_B__QSPI1_A_SS1_B 0x019C 0x04E4 0x0000 0x0 0x0 -#define MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x019C 0x04E4 0x068C 0x1 0x2 -#define MX6SX_PAD_QSPI1A_SS1_B__CANFD_RX1 0x019C 0x04E4 0x0694 0x2 0x2 -#define MX6SX_PAD_QSPI1A_SS1_B__ECSPI5_MISO 0x019C 0x04E4 0x0754 0x3 0x1 -#define MX6SX_PAD_QSPI1A_SS1_B__CSI1_DATA_10 0x019C 0x04E4 0x06FC 0x4 0x1 -#define MX6SX_PAD_QSPI1A_SS1_B__GPIO4_IO_23 0x019C 0x04E4 0x0000 0x5 0x0 -#define MX6SX_PAD_QSPI1A_SS1_B__WEIM_DATA_2 0x019C 0x04E4 0x0000 0x6 0x0 -#define MX6SX_PAD_QSPI1A_SS1_B__SIM_M_HADDR_12 0x019C 0x04E4 0x0000 0x7 0x0 -#define MX6SX_PAD_QSPI1A_SS1_B__SDMA_DEBUG_PC_3 0x019C 0x04E4 0x0000 0x9 0x0 -#define MX6SX_PAD_QSPI1B_DATA0__QSPI1_B_DATA_0 0x01A0 0x04E8 0x0000 0x0 0x0 -#define MX6SX_PAD_QSPI1B_DATA0__UART3_CTS_B 0x01A0 0x04E8 0x0000 0x1 0x0 -#define MX6SX_PAD_QSPI1B_DATA0__ECSPI3_MOSI 0x01A0 0x04E8 0x0738 0x2 0x1 -#define MX6SX_PAD_QSPI1B_DATA0__ESAI_RX_FS 0x01A0 0x04E8 0x0778 0x3 0x2 -#define MX6SX_PAD_QSPI1B_DATA0__CSI1_DATA_22 0x01A0 0x04E8 0x06F4 0x4 0x1 -#define MX6SX_PAD_QSPI1B_DATA0__GPIO4_IO_24 0x01A0 0x04E8 0x0000 0x5 0x0 -#define MX6SX_PAD_QSPI1B_DATA0__WEIM_DATA_14 0x01A0 0x04E8 0x0000 0x6 0x0 -#define MX6SX_PAD_QSPI1B_DATA0__SIM_M_HADDR_9 0x01A0 0x04E8 0x0000 0x7 0x0 -#define MX6SX_PAD_QSPI1B_DATA1__QSPI1_B_DATA_1 0x01A4 0x04EC 0x0000 0x0 0x0 -#define MX6SX_PAD_QSPI1B_DATA1__UART3_RTS_B 0x01A4 0x04EC 0x083C 0x1 0x5 -#define MX6SX_PAD_QSPI1B_DATA1__ECSPI3_MISO 0x01A4 0x04EC 0x0734 0x2 0x1 -#define MX6SX_PAD_QSPI1B_DATA1__ESAI_RX_CLK 0x01A4 0x04EC 0x0788 0x3 0x2 -#define MX6SX_PAD_QSPI1B_DATA1__CSI1_DATA_21 0x01A4 0x04EC 0x06F0 0x4 0x1 -#define MX6SX_PAD_QSPI1B_DATA1__GPIO4_IO_25 0x01A4 0x04EC 0x0000 0x5 0x0 -#define MX6SX_PAD_QSPI1B_DATA1__WEIM_DATA_13 0x01A4 0x04EC 0x0000 0x6 0x0 -#define MX6SX_PAD_QSPI1B_DATA1__SIM_M_HADDR_8 0x01A4 0x04EC 0x0000 0x7 0x0 -#define MX6SX_PAD_QSPI1B_DATA2__QSPI1_B_DATA_2 0x01A8 0x04F0 0x0000 0x0 0x0 -#define MX6SX_PAD_QSPI1B_DATA2__I2C2_SDA 0x01A8 0x04F0 0x07B4 0x1 0x2 -#define MX6SX_PAD_QSPI1B_DATA2__ECSPI5_RDY 0x01A8 0x04F0 0x0000 0x2 0x0 -#define MX6SX_PAD_QSPI1B_DATA2__ESAI_TX5_RX0 0x01A8 0x04F0 0x07A4 0x3 0x2 -#define MX6SX_PAD_QSPI1B_DATA2__CSI1_DATA_20 0x01A8 0x04F0 0x06EC 0x4 0x1 -#define MX6SX_PAD_QSPI1B_DATA2__GPIO4_IO_26 0x01A8 0x04F0 0x0000 0x5 0x0 -#define MX6SX_PAD_QSPI1B_DATA2__WEIM_DATA_12 0x01A8 0x04F0 0x0000 0x6 0x0 -#define MX6SX_PAD_QSPI1B_DATA2__SIM_M_HADDR_5 0x01A8 0x04F0 0x0000 0x7 0x0 -#define MX6SX_PAD_QSPI1B_DATA3__QSPI1_B_DATA_3 0x01AC 0x04F4 0x0000 0x0 0x0 -#define MX6SX_PAD_QSPI1B_DATA3__I2C2_SCL 0x01AC 0x04F4 0x07B0 0x1 0x2 -#define MX6SX_PAD_QSPI1B_DATA3__ECSPI5_SS3 0x01AC 0x04F4 0x0000 0x2 0x0 -#define MX6SX_PAD_QSPI1B_DATA3__ESAI_TX_FS 0x01AC 0x04F4 0x077C 0x3 0x2 -#define MX6SX_PAD_QSPI1B_DATA3__CSI1_DATA_19 0x01AC 0x04F4 0x06E8 0x4 0x1 -#define MX6SX_PAD_QSPI1B_DATA3__GPIO4_IO_27 0x01AC 0x04F4 0x0000 0x5 0x0 -#define MX6SX_PAD_QSPI1B_DATA3__WEIM_DATA_11 0x01AC 0x04F4 0x0000 0x6 0x0 -#define MX6SX_PAD_QSPI1B_DATA3__SIM_M_HADDR_2 0x01AC 0x04F4 0x0000 0x7 0x0 -#define MX6SX_PAD_QSPI1B_DQS__QSPI1_B_DQS 0x01B0 0x04F8 0x0000 0x0 0x0 -#define MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x01B0 0x04F8 0x0000 0x1 0x0 -#define MX6SX_PAD_QSPI1B_DQS__CANFD_TX1 0x01B0 0x04F8 0x0000 0x2 0x0 -#define MX6SX_PAD_QSPI1B_DQS__ECSPI5_SS0 0x01B0 0x04F8 0x075C 0x3 0x1 -#define MX6SX_PAD_QSPI1B_DQS__CSI1_DATA_23 0x01B0 0x04F8 0x06F8 0x4 0x1 -#define MX6SX_PAD_QSPI1B_DQS__GPIO4_IO_28 0x01B0 0x04F8 0x0000 0x5 0x0 -#define MX6SX_PAD_QSPI1B_DQS__WEIM_DATA_15 0x01B0 0x04F8 0x0000 0x6 0x0 -#define MX6SX_PAD_QSPI1B_DQS__SIM_M_HADDR_15 0x01B0 0x04F8 0x0000 0x7 0x0 -#define MX6SX_PAD_QSPI1B_SCLK__QSPI1_B_SCLK 0x01B4 0x04FC 0x0000 0x0 0x0 -#define MX6SX_PAD_QSPI1B_SCLK__UART3_RX 0x01B4 0x04FC 0x0840 0x1 0x4 -#define MX6SX_PAD_QSPI1B_SCLK__UART3_TX 0x01B4 0x04FC 0x0000 0x0 0x0 -#define MX6SX_PAD_QSPI1B_SCLK__ECSPI3_SCLK 0x01B4 0x04FC 0x0730 0x2 0x1 -#define MX6SX_PAD_QSPI1B_SCLK__ESAI_RX_HF_CLK 0x01B4 0x04FC 0x0780 0x3 0x2 -#define MX6SX_PAD_QSPI1B_SCLK__CSI1_DATA_16 0x01B4 0x04FC 0x06DC 0x4 0x1 -#define MX6SX_PAD_QSPI1B_SCLK__GPIO4_IO_29 0x01B4 0x04FC 0x0000 0x5 0x0 -#define MX6SX_PAD_QSPI1B_SCLK__WEIM_DATA_8 0x01B4 0x04FC 0x0000 0x6 0x0 -#define MX6SX_PAD_QSPI1B_SCLK__SIM_M_HADDR_11 0x01B4 0x04FC 0x0000 0x7 0x0 -#define MX6SX_PAD_QSPI1B_SS0_B__QSPI1_B_SS0_B 0x01B8 0x0500 0x0000 0x0 0x0 -#define MX6SX_PAD_QSPI1B_SS0_B__UART3_RX 0x01B8 0x0500 0x0840 0x1 0x5 -#define MX6SX_PAD_QSPI1B_SS0_B__UART3_TX 0x01B8 0x0500 0x0000 0x1 0x0 -#define MX6SX_PAD_QSPI1B_SS0_B__ECSPI3_SS0 0x01B8 0x0500 0x073C 0x2 0x1 -#define MX6SX_PAD_QSPI1B_SS0_B__ESAI_TX_HF_CLK 0x01B8 0x0500 0x0784 0x3 0x3 -#define MX6SX_PAD_QSPI1B_SS0_B__CSI1_DATA_17 0x01B8 0x0500 0x06E0 0x4 0x1 -#define MX6SX_PAD_QSPI1B_SS0_B__GPIO4_IO_30 0x01B8 0x0500 0x0000 0x5 0x0 -#define MX6SX_PAD_QSPI1B_SS0_B__WEIM_DATA_9 0x01B8 0x0500 0x0000 0x6 0x0 -#define MX6SX_PAD_QSPI1B_SS0_B__SIM_M_HADDR_10 0x01B8 0x0500 0x0000 0x7 0x0 -#define MX6SX_PAD_QSPI1B_SS1_B__QSPI1_B_SS1_B 0x01BC 0x0504 0x0000 0x0 0x0 -#define MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x01BC 0x0504 0x0690 0x1 0x2 -#define MX6SX_PAD_QSPI1B_SS1_B__CANFD_RX2 0x01BC 0x0504 0x0698 0x2 0x2 -#define MX6SX_PAD_QSPI1B_SS1_B__ECSPI5_SCLK 0x01BC 0x0504 0x0750 0x3 0x1 -#define MX6SX_PAD_QSPI1B_SS1_B__CSI1_DATA_18 0x01BC 0x0504 0x06E4 0x4 0x1 -#define MX6SX_PAD_QSPI1B_SS1_B__GPIO4_IO_31 0x01BC 0x0504 0x0000 0x5 0x0 -#define MX6SX_PAD_QSPI1B_SS1_B__WEIM_DATA_10 0x01BC 0x0504 0x0000 0x6 0x0 -#define MX6SX_PAD_QSPI1B_SS1_B__SIM_M_HADDR_14 0x01BC 0x0504 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x01C0 0x0508 0x0000 0x0 0x0 -#define MX6SX_PAD_RGMII1_RD0__GPIO5_IO_0 0x01C0 0x0508 0x0000 0x5 0x0 -#define MX6SX_PAD_RGMII1_RD0__CSI2_DATA_10 0x01C0 0x0508 0x0000 0x6 0x0 -#define MX6SX_PAD_RGMII1_RD0__ANATOP_TESTI_0 0x01C0 0x0508 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII1_RD0__RAWNAND_TESTER_TRIGGER 0x01C0 0x0508 0x0000 0x8 0x0 -#define MX6SX_PAD_RGMII1_RD0__PCIE_CTRL_DEBUG_0 0x01C0 0x0508 0x0000 0x9 0x0 -#define MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x01C4 0x050C 0x0000 0x0 0x0 -#define MX6SX_PAD_RGMII1_RD1__GPIO5_IO_1 0x01C4 0x050C 0x0000 0x5 0x0 -#define MX6SX_PAD_RGMII1_RD1__CSI2_DATA_11 0x01C4 0x050C 0x0000 0x6 0x0 -#define MX6SX_PAD_RGMII1_RD1__ANATOP_TESTI_1 0x01C4 0x050C 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII1_RD1__USDHC1_TESTER_TRIGGER 0x01C4 0x050C 0x0000 0x8 0x0 -#define MX6SX_PAD_RGMII1_RD1__PCIE_CTRL_DEBUG_1 0x01C4 0x050C 0x0000 0x9 0x0 -#define MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x01C8 0x0510 0x0000 0x0 0x0 -#define MX6SX_PAD_RGMII1_RD2__GPIO5_IO_2 0x01C8 0x0510 0x0000 0x5 0x0 -#define MX6SX_PAD_RGMII1_RD2__CSI2_DATA_12 0x01C8 0x0510 0x0000 0x6 0x0 -#define MX6SX_PAD_RGMII1_RD2__ANATOP_TESTI_2 0x01C8 0x0510 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII1_RD2__USDHC2_TESTER_TRIGGER 0x01C8 0x0510 0x0000 0x8 0x0 -#define MX6SX_PAD_RGMII1_RD2__PCIE_CTRL_DEBUG_2 0x01C8 0x0510 0x0000 0x9 0x0 -#define MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x01CC 0x0514 0x0000 0x0 0x0 -#define MX6SX_PAD_RGMII1_RD3__GPIO5_IO_3 0x01CC 0x0514 0x0000 0x5 0x0 -#define MX6SX_PAD_RGMII1_RD3__CSI2_DATA_13 0x01CC 0x0514 0x0000 0x6 0x0 -#define MX6SX_PAD_RGMII1_RD3__ANATOP_TESTI_3 0x01CC 0x0514 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII1_RD3__USDHC3_TESTER_TRIGGER 0x01CC 0x0514 0x0000 0x8 0x0 -#define MX6SX_PAD_RGMII1_RD3__PCIE_CTRL_DEBUG_3 0x01CC 0x0514 0x0000 0x9 0x0 -#define MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x01D0 0x0518 0x0000 0x0 0x0 -#define MX6SX_PAD_RGMII1_RX_CTL__GPIO5_IO_4 0x01D0 0x0518 0x0000 0x5 0x0 -#define MX6SX_PAD_RGMII1_RX_CTL__CSI2_DATA_14 0x01D0 0x0518 0x0000 0x6 0x0 -#define MX6SX_PAD_RGMII1_RX_CTL__ANATOP_TESTO_0 0x01D0 0x0518 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII1_RX_CTL__USDHC4_TESTER_TRIGGER 0x01D0 0x0518 0x0000 0x8 0x0 -#define MX6SX_PAD_RGMII1_RX_CTL__PCIE_CTRL_DEBUG_4 0x01D0 0x0518 0x0000 0x9 0x0 -#define MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x01D4 0x051C 0x0768 0x0 0x1 -#define MX6SX_PAD_RGMII1_RXC__ENET1_RX_ER 0x01D4 0x051C 0x0000 0x1 0x0 -#define MX6SX_PAD_RGMII1_RXC__GPIO5_IO_5 0x01D4 0x051C 0x0000 0x5 0x0 -#define MX6SX_PAD_RGMII1_RXC__CSI2_DATA_15 0x01D4 0x051C 0x0000 0x6 0x0 -#define MX6SX_PAD_RGMII1_RXC__ANATOP_TESTO_1 0x01D4 0x051C 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII1_RXC__ECSPI1_TESTER_TRIGGER 0x01D4 0x051C 0x0000 0x8 0x0 -#define MX6SX_PAD_RGMII1_RXC__PCIE_CTRL_DEBUG_5 0x01D4 0x051C 0x0000 0x9 0x0 -#define MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0x01D8 0x0520 0x0000 0x0 0x0 -#define MX6SX_PAD_RGMII1_TD0__SAI2_RX_SYNC 0x01D8 0x0520 0x0810 0x2 0x1 -#define MX6SX_PAD_RGMII1_TD0__GPIO5_IO_6 0x01D8 0x0520 0x0000 0x5 0x0 -#define MX6SX_PAD_RGMII1_TD0__CSI2_DATA_16 0x01D8 0x0520 0x0000 0x6 0x0 -#define MX6SX_PAD_RGMII1_TD0__ANATOP_TESTO_2 0x01D8 0x0520 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII1_TD0__ECSPI2_TESTER_TRIGGER 0x01D8 0x0520 0x0000 0x8 0x0 -#define MX6SX_PAD_RGMII1_TD0__PCIE_CTRL_DEBUG_6 0x01D8 0x0520 0x0000 0x9 0x0 -#define MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0x01DC 0x0524 0x0000 0x0 0x0 -#define MX6SX_PAD_RGMII1_TD1__SAI2_RX_BCLK 0x01DC 0x0524 0x0808 0x2 0x1 -#define MX6SX_PAD_RGMII1_TD1__GPIO5_IO_7 0x01DC 0x0524 0x0000 0x5 0x0 -#define MX6SX_PAD_RGMII1_TD1__CSI2_DATA_17 0x01DC 0x0524 0x0000 0x6 0x0 -#define MX6SX_PAD_RGMII1_TD1__ANATOP_TESTO_3 0x01DC 0x0524 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII1_TD1__ECSPI3_TESTER_TRIGGER 0x01DC 0x0524 0x0000 0x8 0x0 -#define MX6SX_PAD_RGMII1_TD1__PCIE_CTRL_DEBUG_7 0x01DC 0x0524 0x0000 0x9 0x0 -#define MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0x01E0 0x0528 0x0000 0x0 0x0 -#define MX6SX_PAD_RGMII1_TD2__SAI2_TX_SYNC 0x01E0 0x0528 0x0818 0x2 0x1 -#define MX6SX_PAD_RGMII1_TD2__GPIO5_IO_8 0x01E0 0x0528 0x0000 0x5 0x0 -#define MX6SX_PAD_RGMII1_TD2__CSI2_DATA_18 0x01E0 0x0528 0x0000 0x6 0x0 -#define MX6SX_PAD_RGMII1_TD2__ANATOP_TESTO_4 0x01E0 0x0528 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII1_TD2__ECSPI4_TESTER_TRIGGER 0x01E0 0x0528 0x0000 0x8 0x0 -#define MX6SX_PAD_RGMII1_TD2__PCIE_CTRL_DEBUG_8 0x01E0 0x0528 0x0000 0x9 0x0 -#define MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0x01E4 0x052C 0x0000 0x0 0x0 -#define MX6SX_PAD_RGMII1_TD3__SAI2_TX_BCLK 0x01E4 0x052C 0x0814 0x2 0x1 -#define MX6SX_PAD_RGMII1_TD3__GPIO5_IO_9 0x01E4 0x052C 0x0000 0x5 0x0 -#define MX6SX_PAD_RGMII1_TD3__CSI2_DATA_19 0x01E4 0x052C 0x0000 0x6 0x0 -#define MX6SX_PAD_RGMII1_TD3__ANATOP_TESTO_5 0x01E4 0x052C 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII1_TD3__ECSPI5_TESTER_TRIGGER 0x01E4 0x052C 0x0000 0x8 0x0 -#define MX6SX_PAD_RGMII1_TD3__PCIE_CTRL_DEBUG_9 0x01E4 0x052C 0x0000 0x9 0x0 -#define MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0x01E8 0x0530 0x0000 0x0 0x0 -#define MX6SX_PAD_RGMII1_TX_CTL__SAI2_RX_DATA_0 0x01E8 0x0530 0x080C 0x2 0x1 -#define MX6SX_PAD_RGMII1_TX_CTL__GPIO5_IO_10 0x01E8 0x0530 0x0000 0x5 0x0 -#define MX6SX_PAD_RGMII1_TX_CTL__CSI2_DATA_0 0x01E8 0x0530 0x0000 0x6 0x0 -#define MX6SX_PAD_RGMII1_TX_CTL__ANATOP_TESTO_6 0x01E8 0x0530 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII1_TX_CTL__QSPI1_TESTER_TRIGGER 0x01E8 0x0530 0x0000 0x8 0x0 -#define MX6SX_PAD_RGMII1_TX_CTL__PCIE_CTRL_DEBUG_10 0x01E8 0x0530 0x0000 0x9 0x0 -#define MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0x01EC 0x0534 0x0000 0x0 0x0 -#define MX6SX_PAD_RGMII1_TXC__ENET1_TX_ER 0x01EC 0x0534 0x0000 0x1 0x0 -#define MX6SX_PAD_RGMII1_TXC__SAI2_TX_DATA_0 0x01EC 0x0534 0x0000 0x2 0x0 -#define MX6SX_PAD_RGMII1_TXC__GPIO5_IO_11 0x01EC 0x0534 0x0000 0x5 0x0 -#define MX6SX_PAD_RGMII1_TXC__CSI2_DATA_1 0x01EC 0x0534 0x0000 0x6 0x0 -#define MX6SX_PAD_RGMII1_TXC__ANATOP_TESTO_7 0x01EC 0x0534 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII1_TXC__QSPI2_TESTER_TRIGGER 0x01EC 0x0534 0x0000 0x8 0x0 -#define MX6SX_PAD_RGMII1_TXC__PCIE_CTRL_DEBUG_11 0x01EC 0x0534 0x0000 0x9 0x0 -#define MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x01F0 0x0538 0x0000 0x0 0x0 -#define MX6SX_PAD_RGMII2_RD0__PWM4_OUT 0x01F0 0x0538 0x0000 0x2 0x0 -#define MX6SX_PAD_RGMII2_RD0__GPIO5_IO_12 0x01F0 0x0538 0x0000 0x5 0x0 -#define MX6SX_PAD_RGMII2_RD0__CSI2_DATA_2 0x01F0 0x0538 0x0000 0x6 0x0 -#define MX6SX_PAD_RGMII2_RD0__ANATOP_TESTO_8 0x01F0 0x0538 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII2_RD0__VDEC_DEBUG_18 0x01F0 0x0538 0x0000 0x8 0x0 -#define MX6SX_PAD_RGMII2_RD0__PCIE_CTRL_DEBUG_12 0x01F0 0x0538 0x0000 0x9 0x0 -#define MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x01F4 0x053C 0x0000 0x0 0x0 -#define MX6SX_PAD_RGMII2_RD1__PWM3_OUT 0x01F4 0x053C 0x0000 0x2 0x0 -#define MX6SX_PAD_RGMII2_RD1__GPIO5_IO_13 0x01F4 0x053C 0x0000 0x5 0x0 -#define MX6SX_PAD_RGMII2_RD1__CSI2_DATA_3 0x01F4 0x053C 0x0000 0x6 0x0 -#define MX6SX_PAD_RGMII2_RD1__ANATOP_TESTO_9 0x01F4 0x053C 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII2_RD1__VDEC_DEBUG_19 0x01F4 0x053C 0x0000 0x8 0x0 -#define MX6SX_PAD_RGMII2_RD1__PCIE_CTRL_DEBUG_13 0x01F4 0x053C 0x0000 0x9 0x0 -#define MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x01F8 0x0540 0x0000 0x0 0x0 -#define MX6SX_PAD_RGMII2_RD2__PWM2_OUT 0x01F8 0x0540 0x0000 0x2 0x0 -#define MX6SX_PAD_RGMII2_RD2__GPIO5_IO_14 0x01F8 0x0540 0x0000 0x5 0x0 -#define MX6SX_PAD_RGMII2_RD2__CSI2_DATA_4 0x01F8 0x0540 0x0000 0x6 0x0 -#define MX6SX_PAD_RGMII2_RD2__ANATOP_TESTO_10 0x01F8 0x0540 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII2_RD2__VDEC_DEBUG_20 0x01F8 0x0540 0x0000 0x8 0x0 -#define MX6SX_PAD_RGMII2_RD2__PCIE_CTRL_DEBUG_14 0x01F8 0x0540 0x0000 0x9 0x0 -#define MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x01FC 0x0544 0x0000 0x0 0x0 -#define MX6SX_PAD_RGMII2_RD3__PWM1_OUT 0x01FC 0x0544 0x0000 0x2 0x0 -#define MX6SX_PAD_RGMII2_RD3__GPIO5_IO_15 0x01FC 0x0544 0x0000 0x5 0x0 -#define MX6SX_PAD_RGMII2_RD3__CSI2_DATA_5 0x01FC 0x0544 0x0000 0x6 0x0 -#define MX6SX_PAD_RGMII2_RD3__ANATOP_TESTO_11 0x01FC 0x0544 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII2_RD3__VDEC_DEBUG_21 0x01FC 0x0544 0x0000 0x8 0x0 -#define MX6SX_PAD_RGMII2_RD3__PCIE_CTRL_DEBUG_15 0x01FC 0x0544 0x0000 0x9 0x0 -#define MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x0200 0x0548 0x0000 0x0 0x0 -#define MX6SX_PAD_RGMII2_RX_CTL__GPIO5_IO_16 0x0200 0x0548 0x0000 0x5 0x0 -#define MX6SX_PAD_RGMII2_RX_CTL__CSI2_DATA_6 0x0200 0x0548 0x0000 0x6 0x0 -#define MX6SX_PAD_RGMII2_RX_CTL__ANATOP_TESTO_12 0x0200 0x0548 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII2_RX_CTL__VDEC_DEBUG_22 0x0200 0x0548 0x0000 0x8 0x0 -#define MX6SX_PAD_RGMII2_RX_CTL__PCIE_CTRL_DEBUG_16 0x0200 0x0548 0x0000 0x9 0x0 -#define MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x0204 0x054C 0x0774 0x0 0x1 -#define MX6SX_PAD_RGMII2_RXC__ENET2_RX_ER 0x0204 0x054C 0x0000 0x1 0x0 -#define MX6SX_PAD_RGMII2_RXC__GPIO5_IO_17 0x0204 0x054C 0x0000 0x5 0x0 -#define MX6SX_PAD_RGMII2_RXC__CSI2_DATA_7 0x0204 0x054C 0x0000 0x6 0x0 -#define MX6SX_PAD_RGMII2_RXC__ANATOP_TESTO_13 0x0204 0x054C 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII2_RXC__VDEC_DEBUG_23 0x0204 0x054C 0x0000 0x8 0x0 -#define MX6SX_PAD_RGMII2_RXC__PCIE_CTRL_DEBUG_17 0x0204 0x054C 0x0000 0x9 0x0 -#define MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0x0208 0x0550 0x0000 0x0 0x0 -#define MX6SX_PAD_RGMII2_TD0__SAI1_RX_SYNC 0x0208 0x0550 0x07FC 0x2 0x1 -#define MX6SX_PAD_RGMII2_TD0__PWM8_OUT 0x0208 0x0550 0x0000 0x3 0x0 -#define MX6SX_PAD_RGMII2_TD0__GPIO5_IO_18 0x0208 0x0550 0x0000 0x5 0x0 -#define MX6SX_PAD_RGMII2_TD0__CSI2_DATA_8 0x0208 0x0550 0x0000 0x6 0x0 -#define MX6SX_PAD_RGMII2_TD0__ANATOP_TESTO_14 0x0208 0x0550 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII2_TD0__VDEC_DEBUG_24 0x0208 0x0550 0x0000 0x8 0x0 -#define MX6SX_PAD_RGMII2_TD0__PCIE_CTRL_DEBUG_18 0x0208 0x0550 0x0000 0x9 0x0 -#define MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0x020C 0x0554 0x0000 0x0 0x0 -#define MX6SX_PAD_RGMII2_TD1__SAI1_RX_BCLK 0x020C 0x0554 0x07F4 0x2 0x1 -#define MX6SX_PAD_RGMII2_TD1__PWM7_OUT 0x020C 0x0554 0x0000 0x3 0x0 -#define MX6SX_PAD_RGMII2_TD1__GPIO5_IO_19 0x020C 0x0554 0x0000 0x5 0x0 -#define MX6SX_PAD_RGMII2_TD1__CSI2_DATA_9 0x020C 0x0554 0x0000 0x6 0x0 -#define MX6SX_PAD_RGMII2_TD1__ANATOP_TESTO_15 0x020C 0x0554 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII2_TD1__VDEC_DEBUG_25 0x020C 0x0554 0x0000 0x8 0x0 -#define MX6SX_PAD_RGMII2_TD1__PCIE_CTRL_DEBUG_19 0x020C 0x0554 0x0000 0x9 0x0 -#define MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0x0210 0x0558 0x0000 0x0 0x0 -#define MX6SX_PAD_RGMII2_TD2__SAI1_TX_SYNC 0x0210 0x0558 0x0804 0x2 0x1 -#define MX6SX_PAD_RGMII2_TD2__PWM6_OUT 0x0210 0x0558 0x0000 0x3 0x0 -#define MX6SX_PAD_RGMII2_TD2__GPIO5_IO_20 0x0210 0x0558 0x0000 0x5 0x0 -#define MX6SX_PAD_RGMII2_TD2__CSI2_VSYNC 0x0210 0x0558 0x0000 0x6 0x0 -#define MX6SX_PAD_RGMII2_TD2__SJC_FAIL 0x0210 0x0558 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII2_TD2__VDEC_DEBUG_26 0x0210 0x0558 0x0000 0x8 0x0 -#define MX6SX_PAD_RGMII2_TD2__PCIE_CTRL_DEBUG_20 0x0210 0x0558 0x0000 0x9 0x0 -#define MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0x0214 0x055C 0x0000 0x0 0x0 -#define MX6SX_PAD_RGMII2_TD3__SAI1_TX_BCLK 0x0214 0x055C 0x0800 0x2 0x1 -#define MX6SX_PAD_RGMII2_TD3__PWM5_OUT 0x0214 0x055C 0x0000 0x3 0x0 -#define MX6SX_PAD_RGMII2_TD3__GPIO5_IO_21 0x0214 0x055C 0x0000 0x5 0x0 -#define MX6SX_PAD_RGMII2_TD3__CSI2_HSYNC 0x0214 0x055C 0x0000 0x6 0x0 -#define MX6SX_PAD_RGMII2_TD3__SJC_JTAG_ACT 0x0214 0x055C 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII2_TD3__VDEC_DEBUG_27 0x0214 0x055C 0x0000 0x8 0x0 -#define MX6SX_PAD_RGMII2_TD3__PCIE_CTRL_DEBUG_21 0x0214 0x055C 0x0000 0x9 0x0 -#define MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0x0218 0x0560 0x0000 0x0 0x0 -#define MX6SX_PAD_RGMII2_TX_CTL__SAI1_RX_DATA_0 0x0218 0x0560 0x07F8 0x2 0x1 -#define MX6SX_PAD_RGMII2_TX_CTL__GPIO5_IO_22 0x0218 0x0560 0x0000 0x5 0x0 -#define MX6SX_PAD_RGMII2_TX_CTL__CSI2_FIELD 0x0218 0x0560 0x0000 0x6 0x0 -#define MX6SX_PAD_RGMII2_TX_CTL__SJC_DE_B 0x0218 0x0560 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII2_TX_CTL__VDEC_DEBUG_28 0x0218 0x0560 0x0000 0x8 0x0 -#define MX6SX_PAD_RGMII2_TX_CTL__PCIE_CTRL_DEBUG_22 0x0218 0x0560 0x0000 0x9 0x0 -#define MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0x021C 0x0564 0x0000 0x0 0x0 -#define MX6SX_PAD_RGMII2_TXC__ENET2_TX_ER 0x021C 0x0564 0x0000 0x1 0x0 -#define MX6SX_PAD_RGMII2_TXC__SAI1_TX_DATA_0 0x021C 0x0564 0x0000 0x2 0x0 -#define MX6SX_PAD_RGMII2_TXC__GPIO5_IO_23 0x021C 0x0564 0x0000 0x5 0x0 -#define MX6SX_PAD_RGMII2_TXC__CSI2_PIXCLK 0x021C 0x0564 0x0000 0x6 0x0 -#define MX6SX_PAD_RGMII2_TXC__SJC_DONE 0x021C 0x0564 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII2_TXC__VDEC_DEBUG_29 0x021C 0x0564 0x0000 0x8 0x0 -#define MX6SX_PAD_RGMII2_TXC__PCIE_CTRL_DEBUG_23 0x021C 0x0564 0x0000 0x9 0x0 -#define MX6SX_PAD_SD1_CLK__USDHC1_CLK 0x0220 0x0568 0x0000 0x0 0x0 -#define MX6SX_PAD_SD1_CLK__AUDMUX_AUD5_RXFS 0x0220 0x0568 0x0668 0x1 0x1 -#define MX6SX_PAD_SD1_CLK__WDOG2_WDOG_B 0x0220 0x0568 0x0000 0x2 0x0 -#define MX6SX_PAD_SD1_CLK__GPT_CLK 0x0220 0x0568 0x0000 0x3 0x0 -#define MX6SX_PAD_SD1_CLK__WDOG2_WDOG_RST_B_DEB 0x0220 0x0568 0x0000 0x4 0x0 -#define MX6SX_PAD_SD1_CLK__GPIO6_IO_0 0x0220 0x0568 0x0000 0x5 0x0 -#define MX6SX_PAD_SD1_CLK__ENET2_1588_EVENT1_OUT 0x0220 0x0568 0x0000 0x6 0x0 -#define MX6SX_PAD_SD1_CLK__CCM_OUT1 0x0220 0x0568 0x0000 0x7 0x0 -#define MX6SX_PAD_SD1_CLK__VADC_ADC_PROC_CLK 0x0220 0x0568 0x0000 0x8 0x0 -#define MX6SX_PAD_SD1_CLK__MMDC_DEBUG_45 0x0220 0x0568 0x0000 0x9 0x0 -#define MX6SX_PAD_SD1_CMD__USDHC1_CMD 0x0224 0x056C 0x0000 0x0 0x0 -#define MX6SX_PAD_SD1_CMD__AUDMUX_AUD5_RXC 0x0224 0x056C 0x0664 0x1 0x1 -#define MX6SX_PAD_SD1_CMD__WDOG1_WDOG_B 0x0224 0x056C 0x0000 0x2 0x0 -#define MX6SX_PAD_SD1_CMD__GPT_COMPARE1 0x0224 0x056C 0x0000 0x3 0x0 -#define MX6SX_PAD_SD1_CMD__WDOG1_WDOG_RST_B_DEB 0x0224 0x056C 0x0000 0x4 0x0 -#define MX6SX_PAD_SD1_CMD__GPIO6_IO_1 0x0224 0x056C 0x0000 0x5 0x0 -#define MX6SX_PAD_SD1_CMD__ENET2_1588_EVENT1_IN 0x0224 0x056C 0x0000 0x6 0x0 -#define MX6SX_PAD_SD1_CMD__CCM_CLKO1 0x0224 0x056C 0x0000 0x7 0x0 -#define MX6SX_PAD_SD1_CMD__VADC_EXT_SYSCLK 0x0224 0x056C 0x0000 0x8 0x0 -#define MX6SX_PAD_SD1_CMD__MMDC_DEBUG_46 0x0224 0x056C 0x0000 0x9 0x0 -#define MX6SX_PAD_SD1_DATA0__USDHC1_DATA0 0x0228 0x0570 0x0000 0x0 0x0 -#define MX6SX_PAD_SD1_DATA0__AUDMUX_AUD5_RXD 0x0228 0x0570 0x065C 0x1 0x1 -#define MX6SX_PAD_SD1_DATA0__CAAM_WRAPPER_RNG_OSC_OBS 0x0228 0x0570 0x0000 0x2 0x0 -#define MX6SX_PAD_SD1_DATA0__GPT_CAPTURE1 0x0228 0x0570 0x0000 0x3 0x0 -#define MX6SX_PAD_SD1_DATA0__UART2_RX 0x0228 0x0570 0x0838 0x4 0x2 -#define MX6SX_PAD_SD1_DATA0__UART2_TX 0x0228 0x0570 0x0000 0x4 0x0 -#define MX6SX_PAD_SD1_DATA0__GPIO6_IO_2 0x0228 0x0570 0x0000 0x5 0x0 -#define MX6SX_PAD_SD1_DATA0__ENET1_1588_EVENT1_IN 0x0228 0x0570 0x0000 0x6 0x0 -#define MX6SX_PAD_SD1_DATA0__CCM_OUT2 0x0228 0x0570 0x0000 0x7 0x0 -#define MX6SX_PAD_SD1_DATA0__VADC_CLAMP_UP 0x0228 0x0570 0x0000 0x8 0x0 -#define MX6SX_PAD_SD1_DATA0__MMDC_DEBUG_48 0x0228 0x0570 0x0000 0x9 0x0 -#define MX6SX_PAD_SD1_DATA1__USDHC1_DATA1 0x022C 0x0574 0x0000 0x0 0x0 -#define MX6SX_PAD_SD1_DATA1__AUDMUX_AUD5_TXC 0x022C 0x0574 0x066C 0x1 0x1 -#define MX6SX_PAD_SD1_DATA1__PWM4_OUT 0x022C 0x0574 0x0000 0x2 0x0 -#define MX6SX_PAD_SD1_DATA1__GPT_CAPTURE2 0x022C 0x0574 0x0000 0x3 0x0 -#define MX6SX_PAD_SD1_DATA1__UART2_RX 0x022C 0x0574 0x0838 0x4 0x3 -#define MX6SX_PAD_SD1_DATA1__UART2_TX 0x022C 0x0574 0x0000 0x4 0x0 -#define MX6SX_PAD_SD1_DATA1__GPIO6_IO_3 0x022C 0x0574 0x0000 0x5 0x0 -#define MX6SX_PAD_SD1_DATA1__ENET1_1588_EVENT1_OUT 0x022C 0x0574 0x0000 0x6 0x0 -#define MX6SX_PAD_SD1_DATA1__CCM_CLKO2 0x022C 0x0574 0x0000 0x7 0x0 -#define MX6SX_PAD_SD1_DATA1__VADC_CLAMP_DOWN 0x022C 0x0574 0x0000 0x8 0x0 -#define MX6SX_PAD_SD1_DATA1__MMDC_DEBUG_47 0x022C 0x0574 0x0000 0x9 0x0 -#define MX6SX_PAD_SD1_DATA2__USDHC1_DATA2 0x0230 0x0578 0x0000 0x0 0x0 -#define MX6SX_PAD_SD1_DATA2__AUDMUX_AUD5_TXFS 0x0230 0x0578 0x0670 0x1 0x1 -#define MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x0230 0x0578 0x0000 0x2 0x0 -#define MX6SX_PAD_SD1_DATA2__GPT_COMPARE2 0x0230 0x0578 0x0000 0x3 0x0 -#define MX6SX_PAD_SD1_DATA2__UART2_CTS_B 0x0230 0x0578 0x0000 0x4 0x0 -#define MX6SX_PAD_SD1_DATA2__GPIO6_IO_4 0x0230 0x0578 0x0000 0x5 0x0 -#define MX6SX_PAD_SD1_DATA2__ECSPI4_RDY 0x0230 0x0578 0x0000 0x6 0x0 -#define MX6SX_PAD_SD1_DATA2__CCM_OUT0 0x0230 0x0578 0x0000 0x7 0x0 -#define MX6SX_PAD_SD1_DATA2__VADC_EXT_PD_N 0x0230 0x0578 0x0000 0x8 0x0 -#define MX6SX_PAD_SD1_DATA3__USDHC1_DATA3 0x0234 0x057C 0x0000 0x0 0x0 -#define MX6SX_PAD_SD1_DATA3__AUDMUX_AUD5_TXD 0x0234 0x057C 0x0660 0x1 0x1 -#define MX6SX_PAD_SD1_DATA3__AUDMUX_AUD5_RXD 0x0234 0x057C 0x065C 0x2 0x2 -#define MX6SX_PAD_SD1_DATA3__GPT_COMPARE3 0x0234 0x057C 0x0000 0x3 0x0 -#define MX6SX_PAD_SD1_DATA3__UART2_RTS_B 0x0234 0x057C 0x0834 0x4 0x3 -#define MX6SX_PAD_SD1_DATA3__GPIO6_IO_5 0x0234 0x057C 0x0000 0x5 0x0 -#define MX6SX_PAD_SD1_DATA3__ECSPI4_SS1 0x0234 0x057C 0x0000 0x6 0x0 -#define MX6SX_PAD_SD1_DATA3__CCM_PMIC_RDY 0x0234 0x057C 0x069C 0x7 0x2 -#define MX6SX_PAD_SD1_DATA3__VADC_RST_N 0x0234 0x057C 0x0000 0x8 0x0 -#define MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x0238 0x0580 0x0000 0x0 0x0 -#define MX6SX_PAD_SD2_CLK__AUDMUX_AUD6_RXFS 0x0238 0x0580 0x0680 0x1 0x2 -#define MX6SX_PAD_SD2_CLK__KPP_COL_5 0x0238 0x0580 0x07C8 0x2 0x1 -#define MX6SX_PAD_SD2_CLK__ECSPI4_SCLK 0x0238 0x0580 0x0740 0x3 0x1 -#define MX6SX_PAD_SD2_CLK__MLB_SIG 0x0238 0x0580 0x07F0 0x4 0x2 -#define MX6SX_PAD_SD2_CLK__GPIO6_IO_6 0x0238 0x0580 0x0000 0x5 0x0 -#define MX6SX_PAD_SD2_CLK__MQS_RIGHT 0x0238 0x0580 0x0000 0x6 0x0 -#define MX6SX_PAD_SD2_CLK__WDOG1_WDOG_ANY 0x0238 0x0580 0x0000 0x7 0x0 -#define MX6SX_PAD_SD2_CLK__VADC_CLAMP_CURRENT_5 0x0238 0x0580 0x0000 0x8 0x0 -#define MX6SX_PAD_SD2_CLK__MMDC_DEBUG_29 0x0238 0x0580 0x0000 0x9 0x0 -#define MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x023C 0x0584 0x0000 0x0 0x0 -#define MX6SX_PAD_SD2_CMD__AUDMUX_AUD6_RXC 0x023C 0x0584 0x067C 0x1 0x2 -#define MX6SX_PAD_SD2_CMD__KPP_ROW_5 0x023C 0x0584 0x07D4 0x2 0x1 -#define MX6SX_PAD_SD2_CMD__ECSPI4_MOSI 0x023C 0x0584 0x0748 0x3 0x1 -#define MX6SX_PAD_SD2_CMD__MLB_CLK 0x023C 0x0584 0x07E8 0x4 0x2 -#define MX6SX_PAD_SD2_CMD__GPIO6_IO_7 0x023C 0x0584 0x0000 0x5 0x0 -#define MX6SX_PAD_SD2_CMD__MQS_LEFT 0x023C 0x0584 0x0000 0x6 0x0 -#define MX6SX_PAD_SD2_CMD__WDOG3_WDOG_B 0x023C 0x0584 0x0000 0x7 0x0 -#define MX6SX_PAD_SD2_CMD__VADC_CLAMP_CURRENT_4 0x023C 0x0584 0x0000 0x8 0x0 -#define MX6SX_PAD_SD2_CMD__MMDC_DEBUG_30 0x023C 0x0584 0x0000 0x9 0x0 -#define MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x0240 0x0588 0x0000 0x0 0x0 -#define MX6SX_PAD_SD2_DATA0__AUDMUX_AUD6_RXD 0x0240 0x0588 0x0674 0x1 0x2 -#define MX6SX_PAD_SD2_DATA0__KPP_ROW_7 0x0240 0x0588 0x07DC 0x2 0x1 -#define MX6SX_PAD_SD2_DATA0__PWM1_OUT 0x0240 0x0588 0x0000 0x3 0x0 -#define MX6SX_PAD_SD2_DATA0__I2C4_SDA 0x0240 0x0588 0x07C4 0x4 0x3 -#define MX6SX_PAD_SD2_DATA0__GPIO6_IO_8 0x0240 0x0588 0x0000 0x5 0x0 -#define MX6SX_PAD_SD2_DATA0__ECSPI4_SS3 0x0240 0x0588 0x0000 0x6 0x0 -#define MX6SX_PAD_SD2_DATA0__UART4_RX 0x0240 0x0588 0x0848 0x7 0x4 -#define MX6SX_PAD_SD2_DATA0__UART4_TX 0x0240 0x0588 0x0000 0x7 0x0 -#define MX6SX_PAD_SD2_DATA0__VADC_CLAMP_CURRENT_0 0x0240 0x0588 0x0000 0x8 0x0 -#define MX6SX_PAD_SD2_DATA0__MMDC_DEBUG_50 0x0240 0x0588 0x0000 0x9 0x0 -#define MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x0244 0x058C 0x0000 0x0 0x0 -#define MX6SX_PAD_SD2_DATA1__AUDMUX_AUD6_TXC 0x0244 0x058C 0x0684 0x1 0x2 -#define MX6SX_PAD_SD2_DATA1__KPP_COL_7 0x0244 0x058C 0x07D0 0x2 0x1 -#define MX6SX_PAD_SD2_DATA1__PWM2_OUT 0x0244 0x058C 0x0000 0x3 0x0 -#define MX6SX_PAD_SD2_DATA1__I2C4_SCL 0x0244 0x058C 0x07C0 0x4 0x3 -#define MX6SX_PAD_SD2_DATA1__GPIO6_IO_9 0x0244 0x058C 0x0000 0x5 0x0 -#define MX6SX_PAD_SD2_DATA1__ECSPI4_SS2 0x0244 0x058C 0x0000 0x6 0x0 -#define MX6SX_PAD_SD2_DATA1__UART4_RX 0x0244 0x058C 0x0848 0x7 0x5 -#define MX6SX_PAD_SD2_DATA1__UART4_TX 0x0244 0x058C 0x0000 0x7 0x0 -#define MX6SX_PAD_SD2_DATA1__VADC_CLAMP_CURRENT_1 0x0244 0x058C 0x0000 0x8 0x0 -#define MX6SX_PAD_SD2_DATA1__MMDC_DEBUG_49 0x0244 0x058C 0x0000 0x9 0x0 -#define MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x0248 0x0590 0x0000 0x0 0x0 -#define MX6SX_PAD_SD2_DATA2__AUDMUX_AUD6_TXFS 0x0248 0x0590 0x0688 0x1 0x2 -#define MX6SX_PAD_SD2_DATA2__KPP_ROW_6 0x0248 0x0590 0x07D8 0x2 0x1 -#define MX6SX_PAD_SD2_DATA2__ECSPI4_SS0 0x0248 0x0590 0x074C 0x3 0x1 -#define MX6SX_PAD_SD2_DATA2__SDMA_EXT_EVENT_0 0x0248 0x0590 0x081C 0x4 0x2 -#define MX6SX_PAD_SD2_DATA2__GPIO6_IO_10 0x0248 0x0590 0x0000 0x5 0x0 -#define MX6SX_PAD_SD2_DATA2__SPDIF_OUT 0x0248 0x0590 0x0000 0x6 0x0 -#define MX6SX_PAD_SD2_DATA2__UART6_RX 0x0248 0x0590 0x0858 0x7 0x4 -#define MX6SX_PAD_SD2_DATA2__UART6_TX 0x0248 0x0590 0x0000 0x7 0x0 -#define MX6SX_PAD_SD2_DATA2__VADC_CLAMP_CURRENT_2 0x0248 0x0590 0x0000 0x8 0x0 -#define MX6SX_PAD_SD2_DATA2__MMDC_DEBUG_32 0x0248 0x0590 0x0000 0x9 0x0 -#define MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x024C 0x0594 0x0000 0x0 0x0 -#define MX6SX_PAD_SD2_DATA3__AUDMUX_AUD6_TXD 0x024C 0x0594 0x0678 0x1 0x2 -#define MX6SX_PAD_SD2_DATA3__KPP_COL_6 0x024C 0x0594 0x07CC 0x2 0x1 -#define MX6SX_PAD_SD2_DATA3__ECSPI4_MISO 0x024C 0x0594 0x0744 0x3 0x1 -#define MX6SX_PAD_SD2_DATA3__MLB_DATA 0x024C 0x0594 0x07EC 0x4 0x2 -#define MX6SX_PAD_SD2_DATA3__GPIO6_IO_11 0x024C 0x0594 0x0000 0x5 0x0 -#define MX6SX_PAD_SD2_DATA3__SPDIF_IN 0x024C 0x0594 0x0824 0x6 0x4 -#define MX6SX_PAD_SD2_DATA3__UART6_RX 0x024C 0x0594 0x0858 0x7 0x5 -#define MX6SX_PAD_SD2_DATA3__UART6_TX 0x024C 0x0594 0x0000 0x7 0x0 -#define MX6SX_PAD_SD2_DATA3__VADC_CLAMP_CURRENT_3 0x024C 0x0594 0x0000 0x8 0x0 -#define MX6SX_PAD_SD2_DATA3__MMDC_DEBUG_31 0x024C 0x0594 0x0000 0x9 0x0 -#define MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x0250 0x0598 0x0000 0x0 0x0 -#define MX6SX_PAD_SD3_CLK__UART4_CTS_B 0x0250 0x0598 0x0000 0x1 0x0 -#define MX6SX_PAD_SD3_CLK__ECSPI4_SCLK 0x0250 0x0598 0x0740 0x2 0x0 -#define MX6SX_PAD_SD3_CLK__AUDMUX_AUD6_RXFS 0x0250 0x0598 0x0680 0x3 0x0 -#define MX6SX_PAD_SD3_CLK__LCDIF2_VSYNC 0x0250 0x0598 0x0000 0x4 0x0 -#define MX6SX_PAD_SD3_CLK__GPIO7_IO_0 0x0250 0x0598 0x0000 0x5 0x0 -#define MX6SX_PAD_SD3_CLK__LCDIF2_BUSY 0x0250 0x0598 0x07E4 0x6 0x0 -#define MX6SX_PAD_SD3_CLK__TPSMP_HDATA_29 0x0250 0x0598 0x0000 0x7 0x0 -#define MX6SX_PAD_SD3_CLK__SDMA_DEBUG_EVENT_CHANNEL_5 0x0250 0x0598 0x0000 0x9 0x0 -#define MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x0254 0x059C 0x0000 0x0 0x0 -#define MX6SX_PAD_SD3_CMD__UART4_RX 0x0254 0x059C 0x0848 0x1 0x0 -#define MX6SX_PAD_SD3_CMD__UART4_TX 0x0254 0x059C 0x0000 0x1 0x0 -#define MX6SX_PAD_SD3_CMD__ECSPI4_MOSI 0x0254 0x059C 0x0748 0x2 0x0 -#define MX6SX_PAD_SD3_CMD__AUDMUX_AUD6_RXC 0x0254 0x059C 0x067C 0x3 0x0 -#define MX6SX_PAD_SD3_CMD__LCDIF2_HSYNC 0x0254 0x059C 0x07E4 0x4 0x1 -#define MX6SX_PAD_SD3_CMD__GPIO7_IO_1 0x0254 0x059C 0x0000 0x5 0x0 -#define MX6SX_PAD_SD3_CMD__LCDIF2_RS 0x0254 0x059C 0x0000 0x6 0x0 -#define MX6SX_PAD_SD3_CMD__TPSMP_HDATA_28 0x0254 0x059C 0x0000 0x7 0x0 -#define MX6SX_PAD_SD3_CMD__SDMA_DEBUG_EVENT_CHANNEL_4 0x0254 0x059C 0x0000 0x9 0x0 -#define MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x0258 0x05A0 0x0000 0x0 0x0 -#define MX6SX_PAD_SD3_DATA0__I2C4_SCL 0x0258 0x05A0 0x07C0 0x1 0x0 -#define MX6SX_PAD_SD3_DATA0__ECSPI2_SS1 0x0258 0x05A0 0x0000 0x2 0x0 -#define MX6SX_PAD_SD3_DATA0__AUDMUX_AUD6_RXD 0x0258 0x05A0 0x0674 0x3 0x0 -#define MX6SX_PAD_SD3_DATA0__LCDIF2_DATA_1 0x0258 0x05A0 0x0000 0x4 0x0 -#define MX6SX_PAD_SD3_DATA0__GPIO7_IO_2 0x0258 0x05A0 0x0000 0x5 0x0 -#define MX6SX_PAD_SD3_DATA0__DCIC1_OUT 0x0258 0x05A0 0x0000 0x6 0x0 -#define MX6SX_PAD_SD3_DATA0__TPSMP_HDATA_30 0x0258 0x05A0 0x0000 0x7 0x0 -#define MX6SX_PAD_SD3_DATA0__GPU_DEBUG_0 0x0258 0x05A0 0x0000 0x8 0x0 -#define MX6SX_PAD_SD3_DATA0__SDMA_DEBUG_EVT_CHN_LINES_0 0x0258 0x05A0 0x0000 0x9 0x0 -#define MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x025C 0x05A4 0x0000 0x0 0x0 -#define MX6SX_PAD_SD3_DATA1__I2C4_SDA 0x025C 0x05A4 0x07C4 0x1 0x0 -#define MX6SX_PAD_SD3_DATA1__ECSPI2_SS2 0x025C 0x05A4 0x0000 0x2 0x0 -#define MX6SX_PAD_SD3_DATA1__AUDMUX_AUD6_TXC 0x025C 0x05A4 0x0684 0x3 0x0 -#define MX6SX_PAD_SD3_DATA1__LCDIF2_DATA_0 0x025C 0x05A4 0x0000 0x4 0x0 -#define MX6SX_PAD_SD3_DATA1__GPIO7_IO_3 0x025C 0x05A4 0x0000 0x5 0x0 -#define MX6SX_PAD_SD3_DATA1__DCIC2_OUT 0x025C 0x05A4 0x0000 0x6 0x0 -#define MX6SX_PAD_SD3_DATA1__TPSMP_HDATA_31 0x025C 0x05A4 0x0000 0x7 0x0 -#define MX6SX_PAD_SD3_DATA1__GPU_DEBUG_1 0x025C 0x05A4 0x0000 0x8 0x0 -#define MX6SX_PAD_SD3_DATA1__SDMA_DEBUG_EVT_CHN_LINES_1 0x025C 0x05A4 0x0000 0x9 0x0 -#define MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x0260 0x05A8 0x0000 0x0 0x0 -#define MX6SX_PAD_SD3_DATA2__UART4_RTS_B 0x0260 0x05A8 0x0844 0x1 0x1 -#define MX6SX_PAD_SD3_DATA2__ECSPI4_SS0 0x0260 0x05A8 0x074C 0x2 0x0 -#define MX6SX_PAD_SD3_DATA2__AUDMUX_AUD6_TXFS 0x0260 0x05A8 0x0688 0x3 0x0 -#define MX6SX_PAD_SD3_DATA2__LCDIF2_CLK 0x0260 0x05A8 0x0000 0x4 0x0 -#define MX6SX_PAD_SD3_DATA2__GPIO7_IO_4 0x0260 0x05A8 0x0000 0x5 0x0 -#define MX6SX_PAD_SD3_DATA2__LCDIF2_WR_RWN 0x0260 0x05A8 0x0000 0x6 0x0 -#define MX6SX_PAD_SD3_DATA2__TPSMP_HDATA_26 0x0260 0x05A8 0x0000 0x7 0x0 -#define MX6SX_PAD_SD3_DATA2__GPU_DEBUG_2 0x0260 0x05A8 0x0000 0x8 0x0 -#define MX6SX_PAD_SD3_DATA2__SDMA_DEBUG_EVENT_CHANNEL_2 0x0260 0x05A8 0x0000 0x9 0x0 -#define MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x0264 0x05AC 0x0000 0x0 0x0 -#define MX6SX_PAD_SD3_DATA3__UART4_RX 0x0264 0x05AC 0x0848 0x1 0x1 -#define MX6SX_PAD_SD3_DATA3__UART4_TX 0x0264 0x05AC 0x0000 0x1 0x0 -#define MX6SX_PAD_SD3_DATA3__ECSPI4_MISO 0x0264 0x05AC 0x0744 0x2 0x0 -#define MX6SX_PAD_SD3_DATA3__AUDMUX_AUD6_TXD 0x0264 0x05AC 0x0678 0x3 0x0 -#define MX6SX_PAD_SD3_DATA3__LCDIF2_ENABLE 0x0264 0x05AC 0x0000 0x4 0x0 -#define MX6SX_PAD_SD3_DATA3__GPIO7_IO_5 0x0264 0x05AC 0x0000 0x5 0x0 -#define MX6SX_PAD_SD3_DATA3__LCDIF2_RD_E 0x0264 0x05AC 0x0000 0x6 0x0 -#define MX6SX_PAD_SD3_DATA3__TPSMP_HDATA_27 0x0264 0x05AC 0x0000 0x7 0x0 -#define MX6SX_PAD_SD3_DATA3__GPU_DEBUG_3 0x0264 0x05AC 0x0000 0x8 0x0 -#define MX6SX_PAD_SD3_DATA3__SDMA_DEBUG_EVENT_CHANNEL_3 0x0264 0x05AC 0x0000 0x9 0x0 -#define MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x0268 0x05B0 0x0000 0x0 0x0 -#define MX6SX_PAD_SD3_DATA4__CAN2_RX 0x0268 0x05B0 0x0690 0x1 0x0 -#define MX6SX_PAD_SD3_DATA4__CANFD_RX2 0x0268 0x05B0 0x0698 0x2 0x0 -#define MX6SX_PAD_SD3_DATA4__UART3_RX 0x0268 0x05B0 0x0840 0x3 0x2 -#define MX6SX_PAD_SD3_DATA4__UART3_TX 0x0268 0x05B0 0x0000 0x3 0x0 -#define MX6SX_PAD_SD3_DATA4__LCDIF2_DATA_3 0x0268 0x05B0 0x0000 0x4 0x0 -#define MX6SX_PAD_SD3_DATA4__GPIO7_IO_6 0x0268 0x05B0 0x0000 0x5 0x0 -#define MX6SX_PAD_SD3_DATA4__ENET2_1588_EVENT0_IN 0x0268 0x05B0 0x0000 0x6 0x0 -#define MX6SX_PAD_SD3_DATA4__TPSMP_HTRANS_1 0x0268 0x05B0 0x0000 0x7 0x0 -#define MX6SX_PAD_SD3_DATA4__GPU_DEBUG_4 0x0268 0x05B0 0x0000 0x8 0x0 -#define MX6SX_PAD_SD3_DATA4__SDMA_DEBUG_BUS_DEVICE_0 0x0268 0x05B0 0x0000 0x9 0x0 -#define MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x026C 0x05B4 0x0000 0x0 0x0 -#define MX6SX_PAD_SD3_DATA5__CAN1_TX 0x026C 0x05B4 0x0000 0x1 0x0 -#define MX6SX_PAD_SD3_DATA5__CANFD_TX1 0x026C 0x05B4 0x0000 0x2 0x0 -#define MX6SX_PAD_SD3_DATA5__UART3_RX 0x026C 0x05B4 0x0840 0x3 0x3 -#define MX6SX_PAD_SD3_DATA5__UART3_TX 0x026C 0x05B4 0x0000 0x3 0x0 -#define MX6SX_PAD_SD3_DATA5__LCDIF2_DATA_2 0x026C 0x05B4 0x0000 0x4 0x0 -#define MX6SX_PAD_SD3_DATA5__GPIO7_IO_7 0x026C 0x05B4 0x0000 0x5 0x0 -#define MX6SX_PAD_SD3_DATA5__ENET2_1588_EVENT0_OUT 0x026C 0x05B4 0x0000 0x6 0x0 -#define MX6SX_PAD_SD3_DATA5__SIM_M_HWRITE 0x026C 0x05B4 0x0000 0x7 0x0 -#define MX6SX_PAD_SD3_DATA5__GPU_DEBUG_5 0x026C 0x05B4 0x0000 0x8 0x0 -#define MX6SX_PAD_SD3_DATA5__SDMA_DEBUG_BUS_DEVICE_1 0x026C 0x05B4 0x0000 0x9 0x0 -#define MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x0270 0x05B8 0x0000 0x0 0x0 -#define MX6SX_PAD_SD3_DATA6__CAN2_TX 0x0270 0x05B8 0x0000 0x1 0x0 -#define MX6SX_PAD_SD3_DATA6__CANFD_TX2 0x0270 0x05B8 0x0000 0x2 0x0 -#define MX6SX_PAD_SD3_DATA6__UART3_RTS_B 0x0270 0x05B8 0x083C 0x3 0x2 -#define MX6SX_PAD_SD3_DATA6__LCDIF2_DATA_4 0x0270 0x05B8 0x0000 0x4 0x0 -#define MX6SX_PAD_SD3_DATA6__GPIO7_IO_8 0x0270 0x05B8 0x0000 0x5 0x0 -#define MX6SX_PAD_SD3_DATA6__ENET1_1588_EVENT0_OUT 0x0270 0x05B8 0x0000 0x6 0x0 -#define MX6SX_PAD_SD3_DATA6__TPSMP_HTRANS_0 0x0270 0x05B8 0x0000 0x7 0x0 -#define MX6SX_PAD_SD3_DATA6__GPU_DEBUG_7 0x0270 0x05B8 0x0000 0x8 0x0 -#define MX6SX_PAD_SD3_DATA6__SDMA_DEBUG_EVT_CHN_LINES_7 0x0270 0x05B8 0x0000 0x9 0x0 -#define MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x0274 0x05BC 0x0000 0x0 0x0 -#define MX6SX_PAD_SD3_DATA7__CAN1_RX 0x0274 0x05BC 0x068C 0x1 0x0 -#define MX6SX_PAD_SD3_DATA7__CANFD_RX1 0x0274 0x05BC 0x0694 0x2 0x0 -#define MX6SX_PAD_SD3_DATA7__UART3_CTS_B 0x0274 0x05BC 0x0000 0x3 0x0 -#define MX6SX_PAD_SD3_DATA7__LCDIF2_DATA_5 0x0274 0x05BC 0x0000 0x4 0x0 -#define MX6SX_PAD_SD3_DATA7__GPIO7_IO_9 0x0274 0x05BC 0x0000 0x5 0x0 -#define MX6SX_PAD_SD3_DATA7__ENET1_1588_EVENT0_IN 0x0274 0x05BC 0x0000 0x6 0x0 -#define MX6SX_PAD_SD3_DATA7__TPSMP_HDATA_DIR 0x0274 0x05BC 0x0000 0x7 0x0 -#define MX6SX_PAD_SD3_DATA7__GPU_DEBUG_6 0x0274 0x05BC 0x0000 0x8 0x0 -#define MX6SX_PAD_SD3_DATA7__SDMA_DEBUG_EVT_CHN_LINES_2 0x0274 0x05BC 0x0000 0x9 0x0 -#define MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x0278 0x05C0 0x0000 0x0 0x0 -#define MX6SX_PAD_SD4_CLK__RAWNAND_DATA15 0x0278 0x05C0 0x0000 0x1 0x0 -#define MX6SX_PAD_SD4_CLK__ECSPI2_MISO 0x0278 0x05C0 0x0724 0x2 0x1 -#define MX6SX_PAD_SD4_CLK__AUDMUX_AUD3_RXFS 0x0278 0x05C0 0x0638 0x3 0x0 -#define MX6SX_PAD_SD4_CLK__LCDIF2_DATA_13 0x0278 0x05C0 0x0000 0x4 0x0 -#define MX6SX_PAD_SD4_CLK__GPIO6_IO_12 0x0278 0x05C0 0x0000 0x5 0x0 -#define MX6SX_PAD_SD4_CLK__ECSPI3_SS2 0x0278 0x05C0 0x0000 0x6 0x0 -#define MX6SX_PAD_SD4_CLK__TPSMP_HDATA_20 0x0278 0x05C0 0x0000 0x7 0x0 -#define MX6SX_PAD_SD4_CLK__VDEC_DEBUG_12 0x0278 0x05C0 0x0000 0x8 0x0 -#define MX6SX_PAD_SD4_CLK__SDMA_DEBUG_EVENT_CHANNEL_SEL 0x0278 0x05C0 0x0000 0x9 0x0 -#define MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x027C 0x05C4 0x0000 0x0 0x0 -#define MX6SX_PAD_SD4_CMD__RAWNAND_DATA14 0x027C 0x05C4 0x0000 0x1 0x0 -#define MX6SX_PAD_SD4_CMD__ECSPI2_MOSI 0x027C 0x05C4 0x0728 0x2 0x1 -#define MX6SX_PAD_SD4_CMD__AUDMUX_AUD3_RXC 0x027C 0x05C4 0x0634 0x3 0x0 -#define MX6SX_PAD_SD4_CMD__LCDIF2_DATA_14 0x027C 0x05C4 0x0000 0x4 0x0 -#define MX6SX_PAD_SD4_CMD__GPIO6_IO_13 0x027C 0x05C4 0x0000 0x5 0x0 -#define MX6SX_PAD_SD4_CMD__ECSPI3_SS1 0x027C 0x05C4 0x0000 0x6 0x0 -#define MX6SX_PAD_SD4_CMD__TPSMP_HDATA_19 0x027C 0x05C4 0x0000 0x7 0x0 -#define MX6SX_PAD_SD4_CMD__VDEC_DEBUG_11 0x027C 0x05C4 0x0000 0x8 0x0 -#define MX6SX_PAD_SD4_CMD__SDMA_DEBUG_CORE_RUN 0x027C 0x05C4 0x0000 0x9 0x0 -#define MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x0280 0x05C8 0x0000 0x0 0x0 -#define MX6SX_PAD_SD4_DATA0__RAWNAND_DATA10 0x0280 0x05C8 0x0000 0x1 0x0 -#define MX6SX_PAD_SD4_DATA0__ECSPI2_SS0 0x0280 0x05C8 0x072C 0x2 0x1 -#define MX6SX_PAD_SD4_DATA0__AUDMUX_AUD3_RXD 0x0280 0x05C8 0x062C 0x3 0x0 -#define MX6SX_PAD_SD4_DATA0__LCDIF2_DATA_12 0x0280 0x05C8 0x0000 0x4 0x0 -#define MX6SX_PAD_SD4_DATA0__GPIO6_IO_14 0x0280 0x05C8 0x0000 0x5 0x0 -#define MX6SX_PAD_SD4_DATA0__ECSPI3_SS3 0x0280 0x05C8 0x0000 0x6 0x0 -#define MX6SX_PAD_SD4_DATA0__TPSMP_HDATA_21 0x0280 0x05C8 0x0000 0x7 0x0 -#define MX6SX_PAD_SD4_DATA0__VDEC_DEBUG_13 0x0280 0x05C8 0x0000 0x8 0x0 -#define MX6SX_PAD_SD4_DATA0__SDMA_DEBUG_MODE 0x0280 0x05C8 0x0000 0x9 0x0 -#define MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x0284 0x05CC 0x0000 0x0 0x0 -#define MX6SX_PAD_SD4_DATA1__RAWNAND_DATA11 0x0284 0x05CC 0x0000 0x1 0x0 -#define MX6SX_PAD_SD4_DATA1__ECSPI2_SCLK 0x0284 0x05CC 0x0720 0x2 0x1 -#define MX6SX_PAD_SD4_DATA1__AUDMUX_AUD3_TXC 0x0284 0x05CC 0x063C 0x3 0x0 -#define MX6SX_PAD_SD4_DATA1__LCDIF2_DATA_11 0x0284 0x05CC 0x0000 0x4 0x0 -#define MX6SX_PAD_SD4_DATA1__GPIO6_IO_15 0x0284 0x05CC 0x0000 0x5 0x0 -#define MX6SX_PAD_SD4_DATA1__ECSPI3_RDY 0x0284 0x05CC 0x0000 0x6 0x0 -#define MX6SX_PAD_SD4_DATA1__TPSMP_HDATA_22 0x0284 0x05CC 0x0000 0x7 0x0 -#define MX6SX_PAD_SD4_DATA1__VDEC_DEBUG_14 0x0284 0x05CC 0x0000 0x8 0x0 -#define MX6SX_PAD_SD4_DATA1__SDMA_DEBUG_BUS_ERROR 0x0284 0x05CC 0x0000 0x9 0x0 -#define MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x0288 0x05D0 0x0000 0x0 0x0 -#define MX6SX_PAD_SD4_DATA2__RAWNAND_DATA12 0x0288 0x05D0 0x0000 0x1 0x0 -#define MX6SX_PAD_SD4_DATA2__I2C2_SDA 0x0288 0x05D0 0x07B4 0x2 0x0 -#define MX6SX_PAD_SD4_DATA2__AUDMUX_AUD3_TXFS 0x0288 0x05D0 0x0640 0x3 0x0 -#define MX6SX_PAD_SD4_DATA2__LCDIF2_DATA_10 0x0288 0x05D0 0x0000 0x4 0x0 -#define MX6SX_PAD_SD4_DATA2__GPIO6_IO_16 0x0288 0x05D0 0x0000 0x5 0x0 -#define MX6SX_PAD_SD4_DATA2__ECSPI2_SS3 0x0288 0x05D0 0x0000 0x6 0x0 -#define MX6SX_PAD_SD4_DATA2__TPSMP_HDATA_23 0x0288 0x05D0 0x0000 0x7 0x0 -#define MX6SX_PAD_SD4_DATA2__VDEC_DEBUG_15 0x0288 0x05D0 0x0000 0x8 0x0 -#define MX6SX_PAD_SD4_DATA2__SDMA_DEBUG_BUS_RWB 0x0288 0x05D0 0x0000 0x9 0x0 -#define MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x028C 0x05D4 0x0000 0x0 0x0 -#define MX6SX_PAD_SD4_DATA3__RAWNAND_DATA13 0x028C 0x05D4 0x0000 0x1 0x0 -#define MX6SX_PAD_SD4_DATA3__I2C2_SCL 0x028C 0x05D4 0x07B0 0x2 0x0 -#define MX6SX_PAD_SD4_DATA3__AUDMUX_AUD3_TXD 0x028C 0x05D4 0x0630 0x3 0x0 -#define MX6SX_PAD_SD4_DATA3__LCDIF2_DATA_9 0x028C 0x05D4 0x0000 0x4 0x0 -#define MX6SX_PAD_SD4_DATA3__GPIO6_IO_17 0x028C 0x05D4 0x0000 0x5 0x0 -#define MX6SX_PAD_SD4_DATA3__ECSPI2_RDY 0x028C 0x05D4 0x0000 0x6 0x0 -#define MX6SX_PAD_SD4_DATA3__TPSMP_HDATA_24 0x028C 0x05D4 0x0000 0x7 0x0 -#define MX6SX_PAD_SD4_DATA3__VDEC_DEBUG_16 0x028C 0x05D4 0x0000 0x8 0x0 -#define MX6SX_PAD_SD4_DATA3__SDMA_DEBUG_MATCHED_DMBUS 0x028C 0x05D4 0x0000 0x9 0x0 -#define MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x0290 0x05D8 0x0000 0x0 0x0 -#define MX6SX_PAD_SD4_DATA4__RAWNAND_DATA09 0x0290 0x05D8 0x0000 0x1 0x0 -#define MX6SX_PAD_SD4_DATA4__UART5_RX 0x0290 0x05D8 0x0850 0x2 0x0 -#define MX6SX_PAD_SD4_DATA4__UART5_TX 0x0290 0x05D8 0x0000 0x2 0x0 -#define MX6SX_PAD_SD4_DATA4__ECSPI3_SCLK 0x0290 0x05D8 0x0730 0x3 0x0 -#define MX6SX_PAD_SD4_DATA4__LCDIF2_DATA_8 0x0290 0x05D8 0x0000 0x4 0x0 -#define MX6SX_PAD_SD4_DATA4__GPIO6_IO_18 0x0290 0x05D8 0x0000 0x5 0x0 -#define MX6SX_PAD_SD4_DATA4__SPDIF_OUT 0x0290 0x05D8 0x0000 0x6 0x0 -#define MX6SX_PAD_SD4_DATA4__TPSMP_HDATA_16 0x0290 0x05D8 0x0000 0x7 0x0 -#define MX6SX_PAD_SD4_DATA4__USB_OTG_HOST_MODE 0x0290 0x05D8 0x0000 0x8 0x0 -#define MX6SX_PAD_SD4_DATA4__SDMA_DEBUG_RTBUFFER_WRITE 0x0290 0x05D8 0x0000 0x9 0x0 -#define MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x0294 0x05DC 0x0000 0x0 0x0 -#define MX6SX_PAD_SD4_DATA5__RAWNAND_CE2_B 0x0294 0x05DC 0x0000 0x1 0x0 -#define MX6SX_PAD_SD4_DATA5__UART5_RX 0x0294 0x05DC 0x0850 0x2 0x1 -#define MX6SX_PAD_SD4_DATA5__UART5_TX 0x0294 0x05DC 0x0000 0x2 0x0 -#define MX6SX_PAD_SD4_DATA5__ECSPI3_MOSI 0x0294 0x05DC 0x0738 0x3 0x0 -#define MX6SX_PAD_SD4_DATA5__LCDIF2_DATA_7 0x0294 0x05DC 0x0000 0x4 0x0 -#define MX6SX_PAD_SD4_DATA5__GPIO6_IO_19 0x0294 0x05DC 0x0000 0x5 0x0 -#define MX6SX_PAD_SD4_DATA5__SPDIF_IN 0x0294 0x05DC 0x0824 0x6 0x0 -#define MX6SX_PAD_SD4_DATA5__TPSMP_HDATA_17 0x0294 0x05DC 0x0000 0x7 0x0 -#define MX6SX_PAD_SD4_DATA5__VDEC_DEBUG_9 0x0294 0x05DC 0x0000 0x8 0x0 -#define MX6SX_PAD_SD4_DATA5__SDMA_DEBUG_EVENT_CHANNEL_0 0x0294 0x05DC 0x0000 0x9 0x0 -#define MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x0298 0x05E0 0x0000 0x0 0x0 -#define MX6SX_PAD_SD4_DATA6__RAWNAND_CE3_B 0x0298 0x05E0 0x0000 0x1 0x0 -#define MX6SX_PAD_SD4_DATA6__UART5_RTS_B 0x0298 0x05E0 0x084C 0x2 0x0 -#define MX6SX_PAD_SD4_DATA6__ECSPI3_MISO 0x0298 0x05E0 0x0734 0x3 0x0 -#define MX6SX_PAD_SD4_DATA6__LCDIF2_DATA_6 0x0298 0x05E0 0x0000 0x4 0x0 -#define MX6SX_PAD_SD4_DATA6__GPIO6_IO_20 0x0298 0x05E0 0x0000 0x5 0x0 -#define MX6SX_PAD_SD4_DATA6__USDHC4_WP 0x0298 0x05E0 0x0878 0x6 0x0 -#define MX6SX_PAD_SD4_DATA6__TPSMP_HDATA_18 0x0298 0x05E0 0x0000 0x7 0x0 -#define MX6SX_PAD_SD4_DATA6__VDEC_DEBUG_10 0x0298 0x05E0 0x0000 0x8 0x0 -#define MX6SX_PAD_SD4_DATA6__SDMA_DEBUG_EVENT_CHANNEL_1 0x0298 0x05E0 0x0000 0x9 0x0 -#define MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x029C 0x05E4 0x0000 0x0 0x0 -#define MX6SX_PAD_SD4_DATA7__RAWNAND_DATA08 0x029C 0x05E4 0x0000 0x1 0x0 -#define MX6SX_PAD_SD4_DATA7__UART5_CTS_B 0x029C 0x05E4 0x0000 0x2 0x0 -#define MX6SX_PAD_SD4_DATA7__ECSPI3_SS0 0x029C 0x05E4 0x073C 0x3 0x0 -#define MX6SX_PAD_SD4_DATA7__LCDIF2_DATA_15 0x029C 0x05E4 0x0000 0x4 0x0 -#define MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x029C 0x05E4 0x0000 0x5 0x0 -#define MX6SX_PAD_SD4_DATA7__USDHC4_CD_B 0x029C 0x05E4 0x0874 0x6 0x0 -#define MX6SX_PAD_SD4_DATA7__TPSMP_HDATA_15 0x029C 0x05E4 0x0000 0x7 0x0 -#define MX6SX_PAD_SD4_DATA7__USB_OTG_PWR_WAKE 0x029C 0x05E4 0x0000 0x8 0x0 -#define MX6SX_PAD_SD4_DATA7__SDMA_DEBUG_YIELD 0x029C 0x05E4 0x0000 0x9 0x0 -#define MX6SX_PAD_SD4_RESET_B__USDHC4_RESET_B 0x02A0 0x05E8 0x0000 0x0 0x0 -#define MX6SX_PAD_SD4_RESET_B__RAWNAND_DQS 0x02A0 0x05E8 0x0000 0x1 0x0 -#define MX6SX_PAD_SD4_RESET_B__USDHC4_RESET 0x02A0 0x05E8 0x0000 0x2 0x0 -#define MX6SX_PAD_SD4_RESET_B__AUDMUX_MCLK 0x02A0 0x05E8 0x0000 0x3 0x0 -#define MX6SX_PAD_SD4_RESET_B__LCDIF2_RESET 0x02A0 0x05E8 0x0000 0x4 0x0 -#define MX6SX_PAD_SD4_RESET_B__GPIO6_IO_22 0x02A0 0x05E8 0x0000 0x5 0x0 -#define MX6SX_PAD_SD4_RESET_B__LCDIF2_CS 0x02A0 0x05E8 0x0000 0x6 0x0 -#define MX6SX_PAD_SD4_RESET_B__TPSMP_HDATA_25 0x02A0 0x05E8 0x0000 0x7 0x0 -#define MX6SX_PAD_SD4_RESET_B__VDEC_DEBUG_17 0x02A0 0x05E8 0x0000 0x8 0x0 -#define MX6SX_PAD_SD4_RESET_B__SDMA_DEBUG_BUS_DEVICE_2 0x02A0 0x05E8 0x0000 0x9 0x0 -#define MX6SX_PAD_USB_H_DATA__USB_H_DATA 0x02A4 0x05EC 0x0000 0x0 0x0 -#define MX6SX_PAD_USB_H_DATA__PWM2_OUT 0x02A4 0x05EC 0x0000 0x1 0x0 -#define MX6SX_PAD_USB_H_DATA__ANATOP_24M_OUT 0x02A4 0x05EC 0x0000 0x2 0x0 -#define MX6SX_PAD_USB_H_DATA__I2C4_SDA 0x02A4 0x05EC 0x07C4 0x3 0x1 -#define MX6SX_PAD_USB_H_DATA__WDOG3_WDOG_B 0x02A4 0x05EC 0x0000 0x4 0x0 -#define MX6SX_PAD_USB_H_DATA__GPIO7_IO_10 0x02A4 0x05EC 0x0000 0x5 0x0 -#define MX6SX_PAD_USB_H_STROBE__USB_H_STROBE 0x02A8 0x05F0 0x0000 0x0 0x0 -#define MX6SX_PAD_USB_H_STROBE__PWM1_OUT 0x02A8 0x05F0 0x0000 0x1 0x0 -#define MX6SX_PAD_USB_H_STROBE__ANATOP_32K_OUT 0x02A8 0x05F0 0x0000 0x2 0x0 -#define MX6SX_PAD_USB_H_STROBE__I2C4_SCL 0x02A8 0x05F0 0x07C0 0x3 0x1 -#define MX6SX_PAD_USB_H_STROBE__WDOG3_WDOG_RST_B_DEB 0x02A8 0x05F0 0x0000 0x4 0x0 -#define MX6SX_PAD_USB_H_STROBE__GPIO7_IO_11 0x02A8 0x05F0 0x0000 0x5 0x0 - -#endif /* __DTS_IMX6SX_PINFUNC_H */ diff --git a/sys/gnu/dts/arm/imx6sx-sabreauto.dts b/sys/gnu/dts/arm/imx6sx-sabreauto.dts deleted file mode 100644 index 315044ccd65..00000000000 --- a/sys/gnu/dts/arm/imx6sx-sabreauto.dts +++ /dev/null @@ -1,461 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// -// Copyright (C) 2014 Freescale Semiconductor, Inc. - -/dts-v1/; - -#include "imx6sx.dtsi" - -/ { - model = "Freescale i.MX6 SoloX Sabre Auto Board"; - compatible = "fsl,imx6sx-sabreauto", "fsl,imx6sx"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x80000000>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_led>; - - user { - label = "debug"; - gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - vcc_sd3: regulator-vcc-sd3 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_vcc_sd3>; - regulator-name = "VCC_SD3"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_can_wake: regulator-can-wake { - compatible = "regulator-fixed"; - regulator-name = "can-wake"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&max7310_b 7 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_can_en: regulator-can-en { - compatible = "regulator-fixed"; - regulator-name = "can-en"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&max7310_b 5 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <®_can_wake>; - }; - - reg_can_stby: regulator-can-stby { - compatible = "regulator-fixed"; - regulator-name = "can-stby"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&max7310_b 4 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <®_can_en>; - }; -}; - -&anaclk2 { - clock-frequency = <24576000>; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet1>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy1>; - fsl,magic-packet; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - }; - - ethphy1: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; - }; -}; - -&fec2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet2>; - phy-mode = "rgmii"; - phy-handle = <ðphy0>; - fsl,magic-packet; - status = "okay"; -}; - -&flexcan1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - xceiver-supply = <®_can_stby>; - status = "okay"; -}; - -&flexcan2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - xceiver-supply = <®_can_stby>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - bus-width = <8>; - cd-gpios = <&gpio7 10 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; - keep-power-in-suspend; - wakeup-source; - vmmc-supply = <&vcc_sd3>; - status = "okay"; -}; - -&usdhc4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc4>; - bus-width = <8>; - cd-gpios = <&gpio7 11 GPIO_ACTIVE_LOW>; - no-1-8-v; - keep-power-in-suspend; - wakeup-source; - status = "okay"; -}; - -&iomuxc { - pinctrl_egalax_int: egalax-intgrp { - fsl,pins = < - MX6SX_PAD_SD4_RESET_B__GPIO6_IO_22 0x10b0 - >; - }; - - pinctrl_enet1: enet1grp { - fsl,pins = < - MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0b1 - MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0b1 - MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b9 - MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0b1 - MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0b1 - MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0xa0b1 - MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0xa0b1 - MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0b1 - MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x3081 - MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081 - MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081 - MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081 - MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081 - MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081 - >; - }; - - pinctrl_enet2: enet2grp { - fsl,pins = < - MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0xa0b9 - MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0xa0b1 - MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0xa0b1 - MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0xa0b1 - MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0xa0b1 - MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0xa0b1 - MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x3081 - MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x3081 - MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x3081 - MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x3081 - MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x3081 - MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x3081 - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x1b020 - MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x1b020 - >; - }; - - pinctrl_flexcan2: flexcan2grp { - fsl,pins = < - MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x1b020 - MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x1b020 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x4001b8b1 - MX6SX_PAD_GPIO1_IO02__I2C2_SCL 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1 - MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1 - >; - }; - - pinctrl_led: ledgrp { - fsl,pins = < - MX6SX_PAD_CSI_PIXCLK__GPIO1_IO_24 0x17059 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1 - MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17059 - MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10059 - MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17059 - MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17059 - MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17059 - MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17059 - MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x17059 - MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x17059 - MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x17059 - MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x17059 - MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x17059 /* CD */ - MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x17059 /* WP */ - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3grp-100mhz { - fsl,pins = < - MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170b9 - MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100b9 - MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170b9 - MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170b9 - MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170b9 - MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170b9 - MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170b9 - MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170b9 - MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170b9 - MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170b9 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3grp-200mhz { - fsl,pins = < - MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170f9 - MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100f9 - MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170f9 - MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170f9 - MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170f9 - MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170f9 - MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170f9 - MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170f9 - MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170f9 - MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170f9 - >; - }; - - pinctrl_usdhc4: usdhc4grp { - fsl,pins = < - MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059 - MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059 - MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059 - MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059 - MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059 - MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059 - MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x17059 /* CD */ - MX6SX_PAD_SD4_DATA6__GPIO6_IO_20 0x17059 /* WP */ - >; - }; - - pinctrl_vcc_sd3: vccsd3grp { - fsl,pins = < - MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY 0x30b0 - >; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - touchscreen@4 { - compatible = "eeti,egalax_ts"; - reg = <0x04>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_egalax_int>; - interrupt-parent = <&gpio6>; - interrupts = <22 IRQ_TYPE_EDGE_FALLING>; - wakeup-gpios = <&gpio6 22 GPIO_ACTIVE_HIGH>; - }; - - pfuze100: pmic@8 { - compatible = "fsl,pfuze100"; - reg = <0x08>; - - regulators { - sw1a_reg: sw1ab { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw1c_reg: sw1c { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3a_reg: sw3a { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3b_reg: sw3b { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - sw4_reg: sw4 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - }; - - snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - vgen1_reg: vgen1 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - regulator-always-on; - }; - - vgen2_reg: vgen2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen3_reg: vgen3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen4_reg: vgen4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen5_reg: vgen5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen6_reg: vgen6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; - - max7322: gpio@68 { - compatible = "maxim,max7322"; - reg = <0x68>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - max7310_a: gpio@30 { - compatible = "maxim,max7310"; - reg = <0x30>; - gpio-controller; - #gpio-cells = <2>; - }; - - max7310_b: gpio@32 { - compatible = "maxim,max7310"; - reg = <0x32>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; -}; diff --git a/sys/gnu/dts/arm/imx6sx-sdb-reva.dts b/sys/gnu/dts/arm/imx6sx-sdb-reva.dts deleted file mode 100644 index dce5dcf96c2..00000000000 --- a/sys/gnu/dts/arm/imx6sx-sdb-reva.dts +++ /dev/null @@ -1,169 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// -// Copyright (C) 2015 Freescale Semiconductor, Inc. - -#include "imx6sx-sdb.dtsi" - -/ { - model = "Freescale i.MX6 SoloX SDB RevA Board"; - compatible = "fsl,imx6sx-sdb-reva", "fsl,imx6sx"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pmic: pfuze100@8 { - compatible = "fsl,pfuze100"; - reg = <0x08>; - - regulators { - sw1a_reg: sw1ab { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw1c_reg: sw1c { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3a_reg: sw3a { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3b_reg: sw3b { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - sw4_reg: sw4 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - }; - - snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - vgen1_reg: vgen1 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - regulator-always-on; - }; - - vgen2_reg: vgen2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen3_reg: vgen3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen4_reg: vgen4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen5_reg: vgen5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen6_reg: vgen6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; -}; - -&qspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_qspi2>; - status = "okay"; - - flash0: s25fl128s@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; - compatible = "spansion,s25fl128s", "jedec,spi-nor"; - spi-max-frequency = <66000000>; - spi-rx-bus-width = <4>; - spi-tx-bus-width = <4>; - }; - - flash1: s25fl128s@2 { - reg = <2>; - #address-cells = <1>; - #size-cells = <1>; - compatible = "spansion,s25fl128s", "jedec,spi-nor"; - spi-max-frequency = <66000000>; - spi-rx-bus-width = <4>; - spi-tx-bus-width = <4>; - }; -}; - -®_can_en { - /* Transceiver EN/STBY is active high on RevA board */ - gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>; - enable-active-high; -}; - -®_can_stby { - gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <®_can_en>; -}; - -®_vdd1p1 { - vin-supply = <&vgen6_reg>; -}; - -®_vdd2p5 { - vin-supply = <&vgen6_reg>; -}; - -&snvs_pwrkey { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx6sx-sdb-sai.dts b/sys/gnu/dts/arm/imx6sx-sdb-sai.dts deleted file mode 100644 index 1c4eacd68e1..00000000000 --- a/sys/gnu/dts/arm/imx6sx-sdb-sai.dts +++ /dev/null @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -// -// Copyright (C) 2016 Freescale Semiconductor, Inc. - -#include "imx6sx-sdb.dts" - -/ { - sound { - audio-cpu = <&sai1>; - }; -}; - -&audmux { - /* pin conflict with sai */ - status = "disabled"; -}; - -&sai1 { - status = "okay"; -}; - -&sdma { - gpr = <&gpr>; - /* SDMA event remap for SAI1 */ - fsl,sdma-event-remap = <0 15 1>, <0 16 1>; -}; - -&ssi2 { - status = "disabled"; -}; diff --git a/sys/gnu/dts/arm/imx6sx-sdb.dts b/sys/gnu/dts/arm/imx6sx-sdb.dts deleted file mode 100644 index 5a63ca61572..00000000000 --- a/sys/gnu/dts/arm/imx6sx-sdb.dts +++ /dev/null @@ -1,155 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// -// Copyright (C) 2015 Freescale Semiconductor, Inc. - -#include "imx6sx-sdb.dtsi" - -/ { - model = "Freescale i.MX6 SoloX SDB RevB Board"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pmic: pfuze100@8 { - compatible = "fsl,pfuze200"; - reg = <0x08>; - - regulators { - sw1a_reg: sw1ab { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3a_reg: sw3a { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3b_reg: sw3b { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - }; - - snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - vgen1_reg: vgen1 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - regulator-always-on; - }; - - vgen2_reg: vgen2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen3_reg: vgen3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen4_reg: vgen4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen5_reg: vgen5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen6_reg: vgen6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; -}; - -&qspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_qspi2>; - status = "okay"; - - flash0: n25q256a@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "micron,n25q256a", "jedec,spi-nor"; - spi-max-frequency = <29000000>; - spi-rx-bus-width = <4>; - spi-tx-bus-width = <4>; - reg = <0>; - }; - - flash1: n25q256a@2 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "micron,n25q256a", "jedec,spi-nor"; - spi-max-frequency = <29000000>; - spi-rx-bus-width = <4>; - spi-tx-bus-width = <4>; - reg = <2>; - }; -}; - -®_arm { - vin-supply = <&sw1a_reg>; -}; - -®_soc { - vin-supply = <&sw1a_reg>; -}; - -®_vdd1p1 { - vin-supply = <&vgen6_reg>; -}; - -®_vdd2p5 { - vin-supply = <&vgen6_reg>; -}; - -®_can_stby { - /* Transceiver EN/STBY is active low on RevB board */ - gpio = <&gpio4 27 GPIO_ACTIVE_LOW>; -}; - -&snvs_pwrkey { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx6sx-sdb.dtsi b/sys/gnu/dts/arm/imx6sx-sdb.dtsi deleted file mode 100644 index f6972deb5e3..00000000000 --- a/sys/gnu/dts/arm/imx6sx-sdb.dtsi +++ /dev/null @@ -1,676 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// -// Copyright (C) 2014 Freescale Semiconductor, Inc. - -/dts-v1/; - -#include -#include -#include "imx6sx.dtsi" - -/ { - model = "Freescale i.MX6 SoloX SDB Board"; - compatible = "fsl,imx6sx-sdb", "fsl,imx6sx"; - - chosen { - stdout-path = &uart1; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x40000000>; - }; - - backlight_display: backlight-display { - compatible = "pwm-backlight"; - pwms = <&pwm3 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_keys>; - - volume-up { - label = "Volume Up"; - gpios = <&gpio1 18 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - - volume-down { - label = "Volume Down"; - gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - }; - - vcc_sd3: regulator-vcc-sd3 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_vcc_sd3>; - regulator-name = "VCC_SD3"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usb_otg1_vbus: regulator-usb-otg1-vbus { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_otg1>; - regulator-name = "usb_otg1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usb_otg2_vbus: regulator-usb-otg2-vbus { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_otg2>; - regulator-name = "usb_otg2_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_psu_5v: regulator-psu-5v { - compatible = "regulator-fixed"; - regulator-name = "PSU-5V0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_lcd_3v3: regulator-lcd-3v3 { - compatible = "regulator-fixed"; - regulator-name = "lcd-3v3"; - gpio = <&gpio3 27 0>; - enable-active-high; - }; - - reg_peri_3v3: regulator-peri-3v3 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_peri_3v3>; - regulator-name = "peri_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio4 16 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - }; - - reg_enet_3v3: regulator-enet-3v3 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet_3v3>; - regulator-name = "enet_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 6 GPIO_ACTIVE_LOW>; - regulator-boot-on; - regulator-always-on; - }; - - reg_pcie_gpio: regulator-pcie-gpio { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie_reg>; - regulator-name = "MPCIE_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_lcd_5v: regulator-lcd-5v { - compatible = "regulator-fixed"; - regulator-name = "lcd-5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_can_en: regulator-can-en { - compatible = "regulator-fixed"; - regulator-name = "can-en"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_can_stby: regulator-can-stby { - compatible = "regulator-fixed"; - regulator-name = "can-stby"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - sound { - compatible = "fsl,imx6sx-sdb-wm8962", "fsl,imx-audio-wm8962"; - model = "wm8962-audio"; - ssi-controller = <&ssi2>; - audio-codec = <&codec>; - audio-routing = - "Headphone Jack", "HPOUTL", - "Headphone Jack", "HPOUTR", - "Ext Spk", "SPKOUTL", - "Ext Spk", "SPKOUTR", - "AMIC", "MICBIAS", - "IN3R", "AMIC"; - mux-int-port = <2>; - mux-ext-port = <6>; - }; - - panel { - compatible = "sii,43wvf1g"; - backlight = <&backlight_display>; - dvdd-supply = <®_lcd_3v3>; - avdd-supply = <®_lcd_5v>; - - port { - panel_in: endpoint { - remote-endpoint = <&display_out>; - }; - }; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet1>; - phy-supply = <®_enet_3v3>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy1>; - phy-reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy1: ethernet-phy@1 { - reg = <1>; - }; - - ethphy2: ethernet-phy@2 { - reg = <2>; - }; - }; -}; - -&fec2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet2>; - phy-mode = "rgmii"; - phy-handle = <ðphy2>; - status = "okay"; -}; - -&flexcan1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - xceiver-supply = <®_can_stby>; - status = "okay"; -}; - -&flexcan2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - xceiver-supply = <®_can_stby>; - status = "okay"; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; -}; - -&i2c4 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4>; - status = "okay"; - - codec: wm8962@1a { - compatible = "wlf,wm8962"; - reg = <0x1a>; - clocks = <&clks IMX6SX_CLK_AUDIO>; - DCVDD-supply = <&vgen4_reg>; - DBVDD-supply = <&vgen4_reg>; - AVDD-supply = <&vgen4_reg>; - CPVDD-supply = <&vgen4_reg>; - MICVDD-supply = <&vgen3_reg>; - PLLVDD-supply = <&vgen4_reg>; - SPKVDD1-supply = <®_psu_5v>; - SPKVDD2-supply = <®_psu_5v>; - }; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio2 0 GPIO_ACTIVE_LOW>; - vpcie-supply = <®_pcie_gpio>; - status = "okay"; -}; - -&lcdif1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd>; - status = "okay"; - - port { - display_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; - status = "okay"; -}; - -&snvs_poweroff { - status = "okay"; -}; - -&sai1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai1>; - status = "disabled"; -}; - -&ssi2 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart5 { /* for bluetooth */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - uart-has-rtscts; - status = "okay"; -}; - -&usbotg1 { - vbus-supply = <®_usb_otg1_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_otg1_id>; - status = "okay"; -}; - -&usbotg2 { - vbus-supply = <®_usb_otg2_vbus>; - dr_mode = "host"; - status = "okay"; -}; - -&usbphy1 { - fsl,tx-d-cal = <106>; -}; - -&usbphy2 { - fsl,tx-d-cal = <106>; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - non-removable; - no-1-8-v; - keep-power-in-suspend; - wakeup-source; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - bus-width = <8>; - cd-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>; - keep-power-in-suspend; - wakeup-source; - vmmc-supply = <&vcc_sd3>; - status = "okay"; -}; - -&usdhc4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc4>; - cd-gpios = <&gpio6 21 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio6 20 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; -}; - -&iomuxc { - imx6x-sdb { - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6SX_PAD_CSI_DATA00__AUDMUX_AUD6_TXC 0x130b0 - MX6SX_PAD_CSI_DATA01__AUDMUX_AUD6_TXFS 0x130b0 - MX6SX_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD 0x120b0 - MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD 0x130b0 - MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x130b0 - >; - }; - - pinctrl_enet1: enet1grp { - fsl,pins = < - MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0b1 - MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0b1 - MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b1 - MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0b1 - MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0b1 - MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0xa0b1 - MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0xa0b1 - MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0b1 - MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x3081 - MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081 - MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081 - MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081 - MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081 - MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081 - MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M 0x91 - /* phy reset */ - MX6SX_PAD_ENET2_CRS__GPIO2_IO_7 0x10b0 - >; - }; - - pinctrl_enet_3v3: enet3v3grp { - fsl,pins = < - MX6SX_PAD_ENET2_COL__GPIO2_IO_6 0x80000000 - >; - }; - - pinctrl_enet2: enet2grp { - fsl,pins = < - MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0xa0b9 - MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0xa0b1 - MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0xa0b1 - MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0xa0b1 - MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0xa0b1 - MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0xa0b1 - MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x3081 - MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x3081 - MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x3081 - MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x3081 - MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x3081 - MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x3081 - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x1b020 - MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x1b020 - >; - }; - - pinctrl_flexcan2: flexcan2grp { - fsl,pins = < - MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x1b020 - MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x1b020 - >; - }; - - pinctrl_gpio_keys: gpio_keysgrp { - fsl,pins = < - MX6SX_PAD_CSI_DATA04__GPIO1_IO_18 0x17059 - MX6SX_PAD_CSI_DATA05__GPIO1_IO_19 0x17059 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1 - MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1 - MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1 - >; - }; - - pinctrl_i2c4: i2c4grp { - fsl,pins = < - MX6SX_PAD_CSI_DATA07__I2C4_SDA 0x4001b8b1 - MX6SX_PAD_CSI_DATA06__I2C4_SCL 0x4001b8b1 - >; - }; - - pinctrl_lcd: lcdgrp { - fsl,pins = < - MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0 - MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x4001b0b0 - MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x4001b0b0 - MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x4001b0b0 - MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x4001b0b0 - MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x4001b0b0 - MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x4001b0b0 - MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x4001b0b0 - MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x4001b0b0 - MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x4001b0b0 - MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x4001b0b0 - MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x4001b0b0 - MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x4001b0b0 - MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x4001b0b0 - MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x4001b0b0 - MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x4001b0b0 - MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x4001b0b0 - MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x4001b0b0 - MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x4001b0b0 - MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x4001b0b0 - MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x4001b0b0 - MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x4001b0b0 - MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x4001b0b0 - MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x4001b0b0 - MX6SX_PAD_LCD1_CLK__LCDIF1_CLK 0x4001b0b0 - MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x4001b0b0 - MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x4001b0b0 - MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x4001b0b0 - MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x4001b0b0 - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = < - MX6SX_PAD_ENET1_COL__GPIO2_IO_0 0x10b0 - >; - }; - - pinctrl_pcie_reg: pciereggrp { - fsl,pins = < - MX6SX_PAD_ENET1_CRS__GPIO2_IO_1 0x10b0 - >; - }; - - pinctrl_peri_3v3: peri3v3grp { - fsl,pins = < - MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16 0x80000000 - >; - }; - - pinctrl_pwm3: pwm3grp-1 { - fsl,pins = < - MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x110b0 - >; - }; - - pinctrl_qspi2: qspi2grp { - fsl,pins = < - MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0 0x70f1 - MX6SX_PAD_NAND_READY_B__QSPI2_A_DATA_1 0x70f1 - MX6SX_PAD_NAND_CE0_B__QSPI2_A_DATA_2 0x70f1 - MX6SX_PAD_NAND_CE1_B__QSPI2_A_DATA_3 0x70f1 - MX6SX_PAD_NAND_CLE__QSPI2_A_SCLK 0x70f1 - MX6SX_PAD_NAND_ALE__QSPI2_A_SS0_B 0x70f1 - MX6SX_PAD_NAND_DATA01__QSPI2_B_DATA_0 0x70f1 - MX6SX_PAD_NAND_DATA00__QSPI2_B_DATA_1 0x70f1 - MX6SX_PAD_NAND_WE_B__QSPI2_B_DATA_2 0x70f1 - MX6SX_PAD_NAND_RE_B__QSPI2_B_DATA_3 0x70f1 - MX6SX_PAD_NAND_DATA02__QSPI2_B_SCLK 0x70f1 - MX6SX_PAD_NAND_DATA03__QSPI2_B_SS0_B 0x70f1 - >; - }; - - pinctrl_vcc_sd3: vccsd3grp { - fsl,pins = < - MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059 - >; - }; - - pinctrl_sai1: sai1grp { - fsl,pins = < - MX6SX_PAD_CSI_DATA00__SAI1_TX_BCLK 0x130b0 - MX6SX_PAD_CSI_DATA01__SAI1_TX_SYNC 0x130b0 - MX6SX_PAD_CSI_HSYNC__SAI1_TX_DATA_0 0x120b0 - MX6SX_PAD_CSI_VSYNC__SAI1_RX_DATA_0 0x130b0 - MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x130b0 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1 - MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6SX_PAD_KEY_ROW3__UART5_RX 0x1b0b1 - MX6SX_PAD_KEY_COL3__UART5_TX 0x1b0b1 - MX6SX_PAD_KEY_ROW2__UART5_CTS_B 0x1b0b1 - MX6SX_PAD_KEY_COL2__UART5_RTS_B 0x1b0b1 - >; - }; - - pinctrl_usb_otg1: usbotg1grp { - fsl,pins = < - MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x10b0 - >; - }; - - pinctrl_usb_otg1_id: usbotg1idgrp { - fsl,pins = < - MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x17059 - >; - }; - - pinctrl_usb_otg2: usbot2ggrp { - fsl,pins = < - MX6SX_PAD_GPIO1_IO12__GPIO1_IO_12 0x10b0 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x17059 - MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x10059 - MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x17059 - MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x17059 - MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x17059 - MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x17059 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17059 - MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10059 - MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17059 - MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17059 - MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17059 - MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17059 - MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x17059 - MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x17059 - MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x17059 - MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x17059 - MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x17059 /* CD */ - MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x17059 /* WP */ - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3grp-100mhz { - fsl,pins = < - MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170b9 - MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100b9 - MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170b9 - MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170b9 - MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170b9 - MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170b9 - MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170b9 - MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170b9 - MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170b9 - MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170b9 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3grp-200mhz { - fsl,pins = < - MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170f9 - MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100f9 - MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170f9 - MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170f9 - MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170f9 - MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170f9 - MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170f9 - MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170f9 - MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170f9 - MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170f9 - >; - }; - - pinctrl_usdhc4: usdhc4grp { - fsl,pins = < - MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059 - MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059 - MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059 - MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059 - MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059 - MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059 - MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x17059 /* CD */ - MX6SX_PAD_SD4_DATA6__GPIO6_IO_20 0x17059 /* WP */ - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY 0x30b0 - >; - }; - }; -}; diff --git a/sys/gnu/dts/arm/imx6sx-softing-vining-2000.dts b/sys/gnu/dts/arm/imx6sx-softing-vining-2000.dts deleted file mode 100644 index 28563f21024..00000000000 --- a/sys/gnu/dts/arm/imx6sx-softing-vining-2000.dts +++ /dev/null @@ -1,570 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2016 Christoph Fritz - */ - -/dts-v1/; - -#include -#include -#include "imx6sx.dtsi" - -/ { - model = "Softing VIN|ING 2000"; - compatible = "samtec,imx6sx-vining-2000", "fsl,imx6sx"; - - chosen { - stdout-path = &uart1; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x40000000>; - }; - - reg_usb_otg1_vbus: regulator-usb_otg1_vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg1_vbus"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_otg1>; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_peri_3v3: regulator-peri_3v3 { - compatible = "regulator-fixed"; - regulator-name = "peri_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - pwmleds { - compatible = "pwm-leds"; - - red { - label = "red"; - max-brightness = <255>; - pwms = <&pwm6 0 50000>; - }; - - green { - label = "green"; - max-brightness = <255>; - pwms = <&pwm2 0 50000>; - }; - - blue { - label = "blue"; - max-brightness = <255>; - pwms = <&pwm1 0 50000>; - }; - }; -}; - -&adc1 { - vref-supply = <®_peri_3v3>; - status = "okay"; -}; - -&cpu0 { - /* - * This board has a shared rail of reg_arm and reg_soc (supplied by - * sw1a_reg) which is modeled below, but still this module behaves - * unstable without higher voltages. Hence, set higher voltages here. - */ - operating-points = < - /* kHz uV */ - 996000 1250000 - 792000 1175000 - 396000 1175000 - 198000 1175000 - >; - fsl,soc-operating-points = < - /* ARM kHz SOC uV */ - 996000 1250000 - 792000 1175000 - 396000 1175000 - 198000 1175000 - >; -}; - -&ecspi4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi4>; - cs-gpios = <&gpio7 4 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet1>; - phy-supply = <®_peri_3v3>; - phy-reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; - phy-reset-duration = <5>; - phy-mode = "rmii"; - phy-handle = <ðphy0>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet0-phy@0 { - reg = <0>; - max-speed = <100>; - interrupt-parent = <&gpio2>; - interrupts = <17 IRQ_TYPE_LEVEL_LOW>; - }; - }; -}; - -&fec2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet2>; - phy-supply = <®_peri_3v3>; - phy-reset-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>; - phy-reset-duration = <5>; - phy-mode = "rmii"; - phy-handle = <ðphy1>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy1: ethernet1-phy@0 { - reg = <0>; - max-speed = <100>; - interrupt-parent = <&gpio2>; - interrupts = <19 IRQ_TYPE_LEVEL_LOW>; - }; - }; -}; - -&flexcan1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - status = "okay"; -}; - -&flexcan2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - proximity: sx9500@28 { - compatible = "semtech,sx9500"; - reg = <0x28>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sx9500>; - interrupt-parent = <&gpio2>; - interrupts = <16 IRQ_TYPE_LEVEL_LOW>; - reset-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; - }; - - pmic: pfuze100@8 { - compatible = "fsl,pfuze200"; - reg = <0x08>; - - regulators { - sw1a_reg: sw1ab { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3a_reg: sw3a { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3b_reg: sw3b { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - vgen1_reg: vgen1 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - regulator-always-on; - }; - - vgen2_reg: vgen2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen3_reg: vgen3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen4_reg: vgen4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen5_reg: vgen5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen6_reg: vgen6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpios>; - - pinctrl_ecspi4: ecspi4grp { - fsl,pins = < - MX6SX_PAD_SD3_CLK__ECSPI4_SCLK 0x130b1 - MX6SX_PAD_SD3_DATA3__ECSPI4_MISO 0x130b1 - MX6SX_PAD_SD3_CMD__ECSPI4_MOSI 0x130b1 - MX6SX_PAD_SD3_DATA2__GPIO7_IO_4 0x30b0 - >; - }; - - pinctrl_enet1: enet1grp { - fsl,pins = < - MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x30c1 - MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x30c1 - MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0f9 - MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0f9 - MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x30c1 - MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0f9 - MX6SX_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4000a038 - /* LAN8720 PHY Reset */ - MX6SX_PAD_RGMII1_TD3__GPIO5_IO_9 0x10b0 - /* MDIO */ - MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0f9 - MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0f9 - /* IRQ from PHY */ - MX6SX_PAD_KEY_ROW2__GPIO2_IO_17 0x10b0 - >; - }; - - pinctrl_enet2: enet2grp { - fsl,pins = < - MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0x1b0b0 - MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0x1b0b0 - MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x1b0b0 - MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x1b0b0 - MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x1b0b0 - MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0x1b0b0 - MX6SX_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4000a038 - /* LAN8720 PHY Reset */ - MX6SX_PAD_RGMII2_TD3__GPIO5_IO_21 0x10b0 - /* MDIO */ - MX6SX_PAD_ENET1_COL__ENET2_MDC 0xa0f9 - MX6SX_PAD_ENET1_CRS__ENET2_MDIO 0xa0f9 - /* IRQ from PHY */ - MX6SX_PAD_KEY_ROW4__GPIO2_IO_19 0x10b0 - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x1b0b0 - MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x1b0b0 - >; - }; - - pinctrl_flexcan2: flexcan2grp { - fsl,pins = < - MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x1b0b0 - MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x1b0b0 - >; - }; - - pinctrl_gpios: gpiosgrp { - fsl,pins = < - /* reset external uC */ - MX6SX_PAD_QSPI1A_DATA3__GPIO4_IO_19 0x10b0 - /* IRQ from external uC */ - MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x10b0 - /* overcurrent detection */ - MX6SX_PAD_GPIO1_IO08__GPIO1_IO_8 0x10b0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1 - MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6SX_PAD_NAND_ALE__I2C3_SDA 0x4001b8b1 - MX6SX_PAD_NAND_CLE__I2C3_SCL 0x4001b8b1 - >; - }; - - pinctrl_pwm1: pwm1grp-1 { - fsl,pins = < - /* blue LED */ - MX6SX_PAD_RGMII2_RD3__PWM1_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm2: pwm2grp-1 { - fsl,pins = < - /* green LED */ - MX6SX_PAD_RGMII2_RD2__PWM2_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm6: pwm6grp-1 { - fsl,pins = < - /* red LED */ - MX6SX_PAD_RGMII2_TD2__PWM6_OUT 0x1b0b1 - >; - }; - - pinctrl_sx9500: sx9500grp { - fsl,pins = < - /* Reset */ - MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x838 - /* IRQ */ - MX6SX_PAD_KEY_ROW1__GPIO2_IO_16 0x70e0 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1 - MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6SX_PAD_GPIO1_IO06__UART2_TX 0x1b0b1 - MX6SX_PAD_GPIO1_IO07__UART2_RX 0x1b0b1 - >; - }; - - pinctrl_usb_otg1: usbotg1grp { - fsl,pins = < - MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x10b0 - >; - }; - - pinctrl_usb_otg1_id: usbotg1idgrp { - fsl,pins = < - MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x17059 - >; - }; - - pinctrl_usdhc2_50mhz: usdhc2grp-50mhz { - fsl,pins = < - MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x10059 - MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x17059 - MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x17059 - MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x17059 - MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x17059 - MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x17059 - MX6SX_PAD_LCD1_VSYNC__GPIO3_IO_28 0x1b000 - MX6SX_PAD_LCD1_HSYNC__GPIO3_IO_26 0x10b0 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2grp-100mhz { - fsl,pins = < - MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x100b9 - MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x170b9 - MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x170b9 - MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x170b9 - MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x170b9 - MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x170b9 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2grp-200mhz { - fsl,pins = < - MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x100f9 - MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x170f9 - MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x170f9 - MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x170f9 - MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x170f9 - MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x170f9 - >; - }; - - pinctrl_usdhc4_50mhz: usdhc4grp-50mhz { - fsl,pins = < - MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059 - MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059 - MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059 - MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059 - MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059 - MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059 - MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x17059 - MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x17059 - MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x17059 - MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x17059 - MX6SX_PAD_SD4_RESET_B__USDHC4_RESET_B 0x17068 - >; - }; - - pinctrl_usdhc4_100mhz: usdhc4-100mhz { - fsl,pins = < - MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100b9 - MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170b9 - MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170b9 - MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170b9 - MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170b9 - MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170b9 - MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170b9 - MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170b9 - MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170b9 - MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170b9 - >; - }; - - pinctrl_usdhc4_200mhz: usdhc4-200mhz { - fsl,pins = < - MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100f9 - MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170f9 - MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170f9 - MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170f9 - MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170f9 - MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170f9 - MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170f9 - MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170f9 - MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170f9 - MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170f9 - >; - }; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "okay"; -}; - -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm2>; - status = "okay"; -}; - -&pwm6 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm6>; - status = "okay"; -}; - -®_arm { - vin-supply = <&sw1a_reg>; -}; - -®_soc { - vin-supply = <&sw1a_reg>; -}; - -&snvs_poweroff { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&usbotg1 { - vbus-supply = <®_usb_otg1_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_otg1_id>; - status = "okay"; -}; - -&usbotg2 { - dr_mode = "host"; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2_50mhz>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>; - cd-gpios = <&gpio3 28 GPIO_ACTIVE_LOW>; - keep-power-in-suspend; - status = "okay"; -}; - -&usdhc4 { - /* hs200-mode is currently unsupported because Vccq is on 3.1V, but - * not on necessary 1.8V. - */ - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc4_50mhz>; - pinctrl-1 = <&pinctrl_usdhc4_100mhz>; - pinctrl-2 = <&pinctrl_usdhc4_200mhz>; - bus-width = <8>; - keep-power-in-suspend; - non-removable; - cap-mmc-hw-reset; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx6sx-udoo-neo-basic.dts b/sys/gnu/dts/arm/imx6sx-udoo-neo-basic.dts deleted file mode 100644 index 205ea26484e..00000000000 --- a/sys/gnu/dts/arm/imx6sx-udoo-neo-basic.dts +++ /dev/null @@ -1,33 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Andreas Färber - */ - -/dts-v1/; - -#include "imx6sx-udoo-neo.dtsi" - -/ { - model = "UDOO Neo Basic"; - compatible = "udoo,neobasic", "fsl,imx6sx"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000>; - }; -}; - -&fec1 { - phy-handle = <ðphy1>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy1: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/imx6sx-udoo-neo-extended.dts b/sys/gnu/dts/arm/imx6sx-udoo-neo-extended.dts deleted file mode 100644 index 5817b498539..00000000000 --- a/sys/gnu/dts/arm/imx6sx-udoo-neo-extended.dts +++ /dev/null @@ -1,26 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Andreas Färber - */ - -/dts-v1/; - -#include "imx6sx-udoo-neo.dtsi" - -/ { - model = "UDOO Neo Extended"; - compatible = "udoo,neoextended", "fsl,imx6sx"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x40000000>; - }; -}; - -&i2c4 { /* Onboard Motion sensors */ - status = "okay"; -}; - -&uart3 { /* Bluetooth */ - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx6sx-udoo-neo-full.dts b/sys/gnu/dts/arm/imx6sx-udoo-neo-full.dts deleted file mode 100644 index 96f4d89848a..00000000000 --- a/sys/gnu/dts/arm/imx6sx-udoo-neo-full.dts +++ /dev/null @@ -1,41 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Andreas Färber - */ - -/dts-v1/; - -#include "imx6sx-udoo-neo.dtsi" - -/ { - model = "UDOO Neo Full"; - compatible = "udoo,neofull", "fsl,imx6sx"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x40000000>; - }; -}; - -&fec1 { - phy-handle = <ðphy1>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy1: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - }; - }; -}; - -&i2c4 { /* Onboard Motion sensors */ - status = "okay"; -}; - -&uart3 { /* Bluetooth */ - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx6sx-udoo-neo.dtsi b/sys/gnu/dts/arm/imx6sx-udoo-neo.dtsi deleted file mode 100644 index 25d4aa985a6..00000000000 --- a/sys/gnu/dts/arm/imx6sx-udoo-neo.dtsi +++ /dev/null @@ -1,410 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Andreas Färber - */ - -#include "imx6sx.dtsi" - -/ { - compatible = "fsl,imx6sx"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - red { - label = "udoo-neo:red:mmc"; - gpios = <&gpio6 0 GPIO_ACTIVE_HIGH>; - default-state = "off"; - linux,default-trigger = "mmc0"; - }; - - orange { - label = "udoo-neo:orange:user"; - gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - }; - - reg_sdio_pwr: regulator-sdio-pwr { - compatible = "regulator-fixed"; - gpio = <&gpio6 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-name = "SDIO_PWR"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; - - reg_usb_otg1_vbus: regulator-usb-otg1-vbus { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_otg1_reg>; - regulator-name = "usb_otg1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usb_otg2_vbus: regulator-usb-otg2-vbus { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_otg2_reg>; - regulator-name = "usb_otg2_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio4 12 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_wlan: regulator-wlan { - compatible = "regulator-fixed"; - regulator-name = "wlan-en-regulator"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio2 12 GPIO_ACTIVE_HIGH>; - startup-delay-us = <70000>; - enable-active-high; - }; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet1>; - phy-mode = "rmii"; - phy-reset-duration = <10>; - phy-reset-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - clock-frequency = <100000>; - status = "okay"; - - pmic: pmic@8 { - compatible = "fsl,pfuze3000"; - reg = <0x08>; - - regulators { - sw1a_reg: sw1a { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1475000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw1c_reg: sw1b { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1475000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1850000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3a_reg: sw3 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1650000>; - regulator-boot-on; - regulator-always-on; - }; - - swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - }; - - snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - vgen1_reg: vldo1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen2_reg: vldo2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen3_reg: vccsd { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen4_reg: v33 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen5_reg: vldo3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen6_reg: vldo4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; -}; - -&i2c2 { /* Brick snap in sensors connector */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - clock-frequency = <100000>; - status = "okay"; -}; - -&i2c4 { /* Onboard Motion sensors */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4>; - clock-frequency = <100000>; - status = "disabled"; -}; - -&iomuxc { - pinctrl_bt_reg: btreggrp { - fsl,pins = - ; - }; - - pinctrl_enet1: enet1grp { - fsl,pins = - , - , - , - , - , - , - - , - , - , - , - , - , - - ; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = - , - ; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = - , - ; - }; - - pinctrl_i2c4: i2c4grp { - fsl,pins = - , - ; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = - , - ; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = - , - ; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = - , - , - , - ; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = - , - ; - }; - - pinctrl_uart6: uart6grp { - fsl,pins = - , - , - , - , - , - , - , - ; - }; - - pinctrl_otg1_reg: otg1grp { - fsl,pins = - ; - }; - - - pinctrl_otg2_reg: otg2grp { - fsl,pins = - ; - }; - - pinctrl_usb_otg1: usbotg1grp { - fsl,pins = - , - ; - }; - - pinctrl_usb_otg2: usbot2ggrp { - fsl,pins = - ; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = - , - , - , - , - , - , - ; /* CD */ - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = - , - , - , - , - , - , - , - , - ; - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -/* Cortex-M4 serial */ -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "disabled"; -}; - -&uart3 { /* Bluetooth - only on Extended/Full versions */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - uart-has-rtscts; - status = "disabled"; - - bluetooth { - compatible = "ti,wl1831-st"; - enable-gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_bt_reg>; - max-speed = <921600>; - }; -}; - -/* Arduino serial */ -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - status = "disabled"; -}; - -&uart6 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart6>; - uart-has-rtscts; - status = "disabled"; -}; - -&usbotg1 { /* J2 micro USB port */ - vbus-supply = <®_usb_otg1_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_otg1>; - status = "okay"; -}; - -&usbotg2 { /* J3 host USB port */ - vbus-supply = <®_usb_otg2_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_otg2>; - dr_mode = "host"; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - vmmc-supply = <®_sdio_pwr>; - bus-width = <4>; - cd-gpios = <&gpio6 2 GPIO_ACTIVE_LOW>; - no-1-8-v; - keep-power-in-suspend; - wakeup-source; - status = "okay"; -}; - -&usdhc3 { /* Wi-Fi */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - non-removable; - vmmc-supply = <®_wlan>; - cap-power-off-card; - wakeup-source; - keep-power-in-suspend; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - wlcore: wlcore@2 { - compatible = "ti,wl1831"; - reg = <2>; - interrupt-parent = <&gpio2>; - interrupts = <16 IRQ_TYPE_EDGE_RISING>; - ref-clock-frequency = <38400000>; - tcxo-clock-frequency = <26000000>; - }; -}; diff --git a/sys/gnu/dts/arm/imx6sx.dtsi b/sys/gnu/dts/arm/imx6sx.dtsi deleted file mode 100644 index 59bad60a47d..00000000000 --- a/sys/gnu/dts/arm/imx6sx.dtsi +++ /dev/null @@ -1,1395 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// -// Copyright 2014 Freescale Semiconductor, Inc. - -#include -#include -#include -#include -#include "imx6sx-pinfunc.h" - -/ { - #address-cells = <1>; - #size-cells = <1>; - /* - * The decompressor and also some bootloaders rely on a - * pre-existing /chosen node to be available to insert the - * command line and merge other ATAGS info. - */ - chosen {}; - - aliases { - can0 = &flexcan1; - can1 = &flexcan2; - ethernet0 = &fec1; - ethernet1 = &fec2; - gpio0 = &gpio1; - gpio1 = &gpio2; - gpio2 = &gpio3; - gpio3 = &gpio4; - gpio4 = &gpio5; - gpio5 = &gpio6; - gpio6 = &gpio7; - i2c0 = &i2c1; - i2c1 = &i2c2; - i2c2 = &i2c3; - i2c3 = &i2c4; - mmc0 = &usdhc1; - mmc1 = &usdhc2; - mmc2 = &usdhc3; - mmc3 = &usdhc4; - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - serial3 = &uart4; - serial4 = &uart5; - serial5 = &uart6; - spi0 = &ecspi1; - spi1 = &ecspi2; - spi2 = &ecspi3; - spi3 = &ecspi4; - spi4 = &ecspi5; - usbphy0 = &usbphy1; - usbphy1 = &usbphy2; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - reg = <0>; - next-level-cache = <&L2>; - operating-points = < - /* kHz uV */ - 996000 1250000 - 792000 1175000 - 396000 1075000 - 198000 975000 - >; - fsl,soc-operating-points = < - /* ARM kHz SOC uV */ - 996000 1175000 - 792000 1175000 - 396000 1175000 - 198000 1175000 - >; - clock-latency = <61036>; /* two CLK32 periods */ - #cooling-cells = <2>; - clocks = <&clks IMX6SX_CLK_ARM>, - <&clks IMX6SX_CLK_PLL2_PFD2>, - <&clks IMX6SX_CLK_STEP>, - <&clks IMX6SX_CLK_PLL1_SW>, - <&clks IMX6SX_CLK_PLL1_SYS>; - clock-names = "arm", "pll2_pfd2_396m", "step", - "pll1_sw", "pll1_sys"; - arm-supply = <®_arm>; - soc-supply = <®_soc>; - }; - }; - - ckil: clock-ckil { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "ckil"; - }; - - osc: clock-osc { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "osc"; - }; - - ipp_di0: clock-ipp-di0 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - clock-output-names = "ipp_di0"; - }; - - ipp_di1: clock-ipp-di1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - clock-output-names = "ipp_di1"; - }; - - anaclk1: clock-anaclk1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - clock-output-names = "anaclk1"; - }; - - anaclk2: clock-anaclk2 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - clock-output-names = "anaclk2"; - }; - - tempmon: tempmon { - compatible = "fsl,imx6sx-tempmon", "fsl,imx6q-tempmon"; - interrupt-parent = <&gpc>; - interrupts = ; - fsl,tempmon = <&anatop>; - nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>; - nvmem-cell-names = "calib", "temp_grade"; - clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>; - }; - - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupt-parent = <&gpc>; - interrupts = ; - }; - - usbphynop1: usbphynop1 { - compatible = "usb-nop-xceiv"; - #phy-cells = <0>; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&gpc>; - ranges; - - ocram_s: sram@8f8000 { - compatible = "mmio-sram"; - reg = <0x008f8000 0x4000>; - clocks = <&clks IMX6SX_CLK_OCRAM_S>; - }; - - ocram: sram@900000 { - compatible = "mmio-sram"; - reg = <0x00900000 0x20000>; - clocks = <&clks IMX6SX_CLK_OCRAM>; - }; - - intc: interrupt-controller@a01000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x00a01000 0x1000>, - <0x00a00100 0x100>; - interrupt-parent = <&intc>; - }; - - L2: l2-cache@a02000 { - compatible = "arm,pl310-cache"; - reg = <0x00a02000 0x1000>; - interrupts = ; - cache-unified; - cache-level = <2>; - arm,tag-latency = <4 2 3>; - arm,data-latency = <4 2 3>; - }; - - gpu: gpu@1800000 { - compatible = "vivante,gc"; - reg = <0x01800000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_GPU>, - <&clks IMX6SX_CLK_GPU>, - <&clks IMX6SX_CLK_GPU>; - clock-names = "bus", "core", "shader"; - power-domains = <&pd_pu>; - }; - - dma_apbh: dma-apbh@1804000 { - compatible = "fsl,imx6sx-dma-apbh", "fsl,imx28-dma-apbh"; - reg = <0x01804000 0x2000>; - interrupts = , - , - , - ; - interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; - #dma-cells = <1>; - dma-channels = <4>; - clocks = <&clks IMX6SX_CLK_APBH_DMA>; - }; - - gpmi: gpmi-nand@1806000{ - compatible = "fsl,imx6sx-gpmi-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x01806000 0x2000>, <0x01808000 0x4000>; - reg-names = "gpmi-nand", "bch"; - interrupts = ; - interrupt-names = "bch"; - clocks = <&clks IMX6SX_CLK_GPMI_IO>, - <&clks IMX6SX_CLK_GPMI_APB>, - <&clks IMX6SX_CLK_GPMI_BCH>, - <&clks IMX6SX_CLK_GPMI_BCH_APB>, - <&clks IMX6SX_CLK_PER1_BCH>; - clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch", - "gpmi_bch_apb", "per1_bch"; - dmas = <&dma_apbh 0>; - dma-names = "rx-tx"; - status = "disabled"; - }; - - aips1: aips-bus@2000000 { - compatible = "fsl,aips-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x02000000 0x100000>; - ranges; - - spba-bus@2000000 { - compatible = "fsl,spba-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x02000000 0x40000>; - ranges; - - spdif: spdif@2004000 { - compatible = "fsl,imx6sx-spdif", "fsl,imx35-spdif"; - reg = <0x02004000 0x4000>; - interrupts = ; - dmas = <&sdma 14 18 0>, - <&sdma 15 18 0>; - dma-names = "rx", "tx"; - clocks = <&clks IMX6SX_CLK_SPDIF_GCLK>, - <&clks IMX6SX_CLK_OSC>, - <&clks IMX6SX_CLK_SPDIF>, - <&clks 0>, <&clks 0>, <&clks 0>, - <&clks IMX6SX_CLK_IPG>, - <&clks 0>, <&clks 0>, - <&clks IMX6SX_CLK_SPBA>; - clock-names = "core", "rxtx0", - "rxtx1", "rxtx2", - "rxtx3", "rxtx4", - "rxtx5", "rxtx6", - "rxtx7", "spba"; - status = "disabled"; - }; - - ecspi1: spi@2008000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; - reg = <0x02008000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_ECSPI1>, - <&clks IMX6SX_CLK_ECSPI1>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - ecspi2: spi@200c000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; - reg = <0x0200c000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_ECSPI2>, - <&clks IMX6SX_CLK_ECSPI2>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - ecspi3: spi@2010000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; - reg = <0x02010000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_ECSPI3>, - <&clks IMX6SX_CLK_ECSPI3>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - ecspi4: spi@2014000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; - reg = <0x02014000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_ECSPI4>, - <&clks IMX6SX_CLK_ECSPI4>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart1: serial@2020000 { - compatible = "fsl,imx6sx-uart", - "fsl,imx6q-uart", "fsl,imx21-uart"; - reg = <0x02020000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_UART_IPG>, - <&clks IMX6SX_CLK_UART_SERIAL>; - clock-names = "ipg", "per"; - dmas = <&sdma 25 4 0>, <&sdma 26 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - esai: esai@2024000 { - reg = <0x02024000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_ESAI_IPG>, - <&clks IMX6SX_CLK_ESAI_MEM>, - <&clks IMX6SX_CLK_ESAI_EXTAL>, - <&clks IMX6SX_CLK_ESAI_IPG>, - <&clks IMX6SX_CLK_SPBA>; - clock-names = "core", "mem", "extal", - "fsys", "spba"; - status = "disabled"; - }; - - ssi1: ssi@2028000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi"; - reg = <0x02028000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_SSI1_IPG>, - <&clks IMX6SX_CLK_SSI1>; - clock-names = "ipg", "baud"; - dmas = <&sdma 37 1 0>, <&sdma 38 1 0>; - dma-names = "rx", "tx"; - fsl,fifo-depth = <15>; - status = "disabled"; - }; - - ssi2: ssi@202c000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi"; - reg = <0x0202c000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_SSI2_IPG>, - <&clks IMX6SX_CLK_SSI2>; - clock-names = "ipg", "baud"; - dmas = <&sdma 41 1 0>, <&sdma 42 1 0>; - dma-names = "rx", "tx"; - fsl,fifo-depth = <15>; - status = "disabled"; - }; - - ssi3: ssi@2030000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi"; - reg = <0x02030000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_SSI3_IPG>, - <&clks IMX6SX_CLK_SSI3>; - clock-names = "ipg", "baud"; - dmas = <&sdma 45 1 0>, <&sdma 46 1 0>; - dma-names = "rx", "tx"; - fsl,fifo-depth = <15>; - status = "disabled"; - }; - - asrc: asrc@2034000 { - reg = <0x02034000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_ASRC_MEM>, - <&clks IMX6SX_CLK_ASRC_IPG>, - <&clks IMX6SX_CLK_SPDIF>, - <&clks IMX6SX_CLK_SPBA>; - clock-names = "mem", "ipg", "asrck", "spba"; - dmas = <&sdma 17 20 1>, <&sdma 18 20 1>, - <&sdma 19 20 1>, <&sdma 20 20 1>, - <&sdma 21 20 1>, <&sdma 22 20 1>; - dma-names = "rxa", "rxb", "rxc", - "txa", "txb", "txc"; - status = "okay"; - }; - }; - - pwm1: pwm@2080000 { - compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; - reg = <0x02080000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_PWM1>, - <&clks IMX6SX_CLK_PWM1>; - clock-names = "ipg", "per"; - #pwm-cells = <2>; - }; - - pwm2: pwm@2084000 { - compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; - reg = <0x02084000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_PWM2>, - <&clks IMX6SX_CLK_PWM2>; - clock-names = "ipg", "per"; - #pwm-cells = <2>; - }; - - pwm3: pwm@2088000 { - compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; - reg = <0x02088000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_PWM3>, - <&clks IMX6SX_CLK_PWM3>; - clock-names = "ipg", "per"; - #pwm-cells = <2>; - }; - - pwm4: pwm@208c000 { - compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; - reg = <0x0208c000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_PWM4>, - <&clks IMX6SX_CLK_PWM4>; - clock-names = "ipg", "per"; - #pwm-cells = <2>; - }; - - flexcan1: can@2090000 { - compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan"; - reg = <0x02090000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_CAN1_IPG>, - <&clks IMX6SX_CLK_CAN1_SERIAL>; - clock-names = "ipg", "per"; - fsl,stop-mode = <&gpr 0x10 1 0x10 17>; - status = "disabled"; - }; - - flexcan2: can@2094000 { - compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan"; - reg = <0x02094000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_CAN2_IPG>, - <&clks IMX6SX_CLK_CAN2_SERIAL>; - clock-names = "ipg", "per"; - fsl,stop-mode = <&gpr 0x10 2 0x10 18>; - status = "disabled"; - }; - - gpt: gpt@2098000 { - compatible = "fsl,imx6sx-gpt", "fsl,imx6dl-gpt"; - reg = <0x02098000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_GPT_BUS>, - <&clks IMX6SX_CLK_GPT_3M>; - clock-names = "ipg", "per"; - }; - - gpio1: gpio@209c000 { - compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; - reg = <0x0209c000 0x4000>; - interrupts = , - ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 5 26>; - }; - - gpio2: gpio@20a0000 { - compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; - reg = <0x020a0000 0x4000>; - interrupts = , - ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 31 20>; - }; - - gpio3: gpio@20a4000 { - compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; - reg = <0x020a4000 0x4000>; - interrupts = , - ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 51 29>; - }; - - gpio4: gpio@20a8000 { - compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; - reg = <0x020a8000 0x4000>; - interrupts = , - ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 80 32>; - }; - - gpio5: gpio@20ac000 { - compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; - reg = <0x020ac000 0x4000>; - interrupts = , - ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 112 24>; - }; - - gpio6: gpio@20b0000 { - compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; - reg = <0x020b0000 0x4000>; - interrupts = , - ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 136 12>, <&iomuxc 12 158 11>; - }; - - gpio7: gpio@20b4000 { - compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; - reg = <0x020b4000 0x4000>; - interrupts = , - ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 148 10>, <&iomuxc 10 169 2>; - }; - - kpp: kpp@20b8000 { - compatible = "fsl,imx6sx-kpp", "fsl,imx21-kpp"; - reg = <0x020b8000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_IPG>; - status = "disabled"; - }; - - wdog1: wdog@20bc000 { - compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt"; - reg = <0x020bc000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_IPG>; - }; - - wdog2: wdog@20c0000 { - compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt"; - reg = <0x020c0000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_IPG>; - status = "disabled"; - }; - - clks: ccm@20c4000 { - compatible = "fsl,imx6sx-ccm"; - reg = <0x020c4000 0x4000>; - interrupts = , - ; - #clock-cells = <1>; - clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>, <&anaclk1>, <&anaclk2>; - clock-names = "ckil", "osc", "ipp_di0", "ipp_di1", "anaclk1", "anaclk2"; - }; - - anatop: anatop@20c8000 { - compatible = "fsl,imx6sx-anatop", "fsl,imx6q-anatop", - "syscon", "simple-mfd"; - reg = <0x020c8000 0x1000>; - interrupts = , - , - ; - - reg_vdd1p1: regulator-1p1 { - compatible = "fsl,anatop-regulator"; - regulator-name = "vdd1p1"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - anatop-reg-offset = <0x110>; - anatop-vol-bit-shift = <8>; - anatop-vol-bit-width = <5>; - anatop-min-bit-val = <4>; - anatop-min-voltage = <800000>; - anatop-max-voltage = <1375000>; - anatop-enable-bit = <0>; - }; - - reg_vdd3p0: regulator-3p0 { - compatible = "fsl,anatop-regulator"; - regulator-name = "vdd3p0"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <3150000>; - regulator-always-on; - anatop-reg-offset = <0x120>; - anatop-vol-bit-shift = <8>; - anatop-vol-bit-width = <5>; - anatop-min-bit-val = <0>; - anatop-min-voltage = <2625000>; - anatop-max-voltage = <3400000>; - anatop-enable-bit = <0>; - }; - - reg_vdd2p5: regulator-2p5 { - compatible = "fsl,anatop-regulator"; - regulator-name = "vdd2p5"; - regulator-min-microvolt = <2250000>; - regulator-max-microvolt = <2750000>; - regulator-always-on; - anatop-reg-offset = <0x130>; - anatop-vol-bit-shift = <8>; - anatop-vol-bit-width = <5>; - anatop-min-bit-val = <0>; - anatop-min-voltage = <2100000>; - anatop-max-voltage = <2875000>; - anatop-enable-bit = <0>; - }; - - reg_arm: regulator-vddcore { - compatible = "fsl,anatop-regulator"; - regulator-name = "vddarm"; - regulator-min-microvolt = <725000>; - regulator-max-microvolt = <1450000>; - regulator-always-on; - anatop-reg-offset = <0x140>; - anatop-vol-bit-shift = <0>; - anatop-vol-bit-width = <5>; - anatop-delay-reg-offset = <0x170>; - anatop-delay-bit-shift = <24>; - anatop-delay-bit-width = <2>; - anatop-min-bit-val = <1>; - anatop-min-voltage = <725000>; - anatop-max-voltage = <1450000>; - }; - - reg_pcie: regulator-vddpcie { - compatible = "fsl,anatop-regulator"; - regulator-name = "vddpcie"; - regulator-min-microvolt = <725000>; - regulator-max-microvolt = <1450000>; - anatop-reg-offset = <0x140>; - anatop-vol-bit-shift = <9>; - anatop-vol-bit-width = <5>; - anatop-delay-reg-offset = <0x170>; - anatop-delay-bit-shift = <26>; - anatop-delay-bit-width = <2>; - anatop-min-bit-val = <1>; - anatop-min-voltage = <725000>; - anatop-max-voltage = <1450000>; - }; - - reg_soc: regulator-vddsoc { - compatible = "fsl,anatop-regulator"; - regulator-name = "vddsoc"; - regulator-min-microvolt = <725000>; - regulator-max-microvolt = <1450000>; - regulator-always-on; - anatop-reg-offset = <0x140>; - anatop-vol-bit-shift = <18>; - anatop-vol-bit-width = <5>; - anatop-delay-reg-offset = <0x170>; - anatop-delay-bit-shift = <28>; - anatop-delay-bit-width = <2>; - anatop-min-bit-val = <1>; - anatop-min-voltage = <725000>; - anatop-max-voltage = <1450000>; - }; - }; - - usbphy1: usbphy@20c9000 { - compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy"; - reg = <0x020c9000 0x1000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_USBPHY1>; - fsl,anatop = <&anatop>; - }; - - usbphy2: usbphy@20ca000 { - compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy"; - reg = <0x020ca000 0x1000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_USBPHY2>; - fsl,anatop = <&anatop>; - }; - - snvs: snvs@20cc000 { - compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; - reg = <0x020cc000 0x4000>; - - snvs_rtc: snvs-rtc-lp { - compatible = "fsl,sec-v4.0-mon-rtc-lp"; - regmap = <&snvs>; - offset = <0x34>; - interrupts = , ; - }; - - snvs_poweroff: snvs-poweroff { - compatible = "syscon-poweroff"; - regmap = <&snvs>; - offset = <0x38>; - value = <0x60>; - mask = <0x60>; - status = "disabled"; - }; - - snvs_pwrkey: snvs-powerkey { - compatible = "fsl,sec-v4.0-pwrkey"; - regmap = <&snvs>; - interrupts = ; - linux,keycode = ; - wakeup-source; - status = "disabled"; - }; - }; - - epit1: epit@20d0000 { - reg = <0x020d0000 0x4000>; - interrupts = ; - }; - - epit2: epit@20d4000 { - reg = <0x020d4000 0x4000>; - interrupts = ; - }; - - src: src@20d8000 { - compatible = "fsl,imx6sx-src", "fsl,imx51-src"; - reg = <0x020d8000 0x4000>; - interrupts = , - ; - #reset-cells = <1>; - }; - - gpc: gpc@20dc000 { - compatible = "fsl,imx6sx-gpc", "fsl,imx6q-gpc"; - reg = <0x020dc000 0x4000>; - interrupt-controller; - #interrupt-cells = <3>; - interrupts = ; - interrupt-parent = <&intc>; - clocks = <&clks IMX6SX_CLK_IPG>; - clock-names = "ipg"; - - pgc { - #address-cells = <1>; - #size-cells = <0>; - - power-domain@0 { - reg = <0>; - #power-domain-cells = <0>; - }; - - pd_pu: power-domain@1 { - reg = <1>; - #power-domain-cells = <0>; - power-supply = <®_soc>; - clocks = <&clks IMX6SX_CLK_GPU>; - }; - - pd_disp: power-domain@2 { - reg = <2>; - #power-domain-cells = <0>; - clocks = <&clks IMX6SX_CLK_PXP_AXI>, - <&clks IMX6SX_CLK_DISPLAY_AXI>, - <&clks IMX6SX_CLK_LCDIF1_PIX>, - <&clks IMX6SX_CLK_LCDIF_APB>, - <&clks IMX6SX_CLK_LCDIF2_PIX>, - <&clks IMX6SX_CLK_CSI>, - <&clks IMX6SX_CLK_VADC>; - }; - - pd_pci: power-domain@3 { - reg = <3>; - #power-domain-cells = <0>; - power-supply = <®_pcie>; - }; - }; - }; - - iomuxc: iomuxc@20e0000 { - compatible = "fsl,imx6sx-iomuxc"; - reg = <0x020e0000 0x4000>; - }; - - gpr: iomuxc-gpr@20e4000 { - compatible = "fsl,imx6sx-iomuxc-gpr", - "fsl,imx6q-iomuxc-gpr", "syscon"; - reg = <0x020e4000 0x4000>; - }; - - sdma: sdma@20ec000 { - compatible = "fsl,imx6sx-sdma", "fsl,imx6q-sdma"; - reg = <0x020ec000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_IPG>, - <&clks IMX6SX_CLK_SDMA>; - clock-names = "ipg", "ahb"; - #dma-cells = <3>; - /* imx6sx reuses imx6q sdma firmware */ - fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; - }; - }; - - aips2: aips-bus@2100000 { - compatible = "fsl,aips-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x02100000 0x100000>; - ranges; - - crypto: caam@2100000 { - compatible = "fsl,sec-v4.0"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x2100000 0x10000>; - ranges = <0 0x2100000 0x10000>; - interrupt-parent = <&intc>; - clocks = <&clks IMX6SX_CLK_CAAM_MEM>, - <&clks IMX6SX_CLK_CAAM_ACLK>, - <&clks IMX6SX_CLK_CAAM_IPG>, - <&clks IMX6SX_CLK_EIM_SLOW>; - clock-names = "mem", "aclk", "ipg", "emi_slow"; - - sec_jr0: jr0@1000 { - compatible = "fsl,sec-v4.0-job-ring"; - reg = <0x1000 0x1000>; - interrupts = ; - }; - - sec_jr1: jr1@2000 { - compatible = "fsl,sec-v4.0-job-ring"; - reg = <0x2000 0x1000>; - interrupts = ; - }; - }; - - usbotg1: usb@2184000 { - compatible = "fsl,imx6sx-usb", "fsl,imx27-usb"; - reg = <0x02184000 0x200>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_USBOH3>; - fsl,usbphy = <&usbphy1>; - fsl,usbmisc = <&usbmisc 0>; - fsl,anatop = <&anatop>; - ahb-burst-config = <0x0>; - tx-burst-size-dword = <0x10>; - rx-burst-size-dword = <0x10>; - status = "disabled"; - }; - - usbotg2: usb@2184200 { - compatible = "fsl,imx6sx-usb", "fsl,imx27-usb"; - reg = <0x02184200 0x200>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_USBOH3>; - fsl,usbphy = <&usbphy2>; - fsl,usbmisc = <&usbmisc 1>; - ahb-burst-config = <0x0>; - tx-burst-size-dword = <0x10>; - rx-burst-size-dword = <0x10>; - status = "disabled"; - }; - - usbh: usb@2184400 { - compatible = "fsl,imx6sx-usb", "fsl,imx27-usb"; - reg = <0x02184400 0x200>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_USBOH3>; - fsl,usbphy = <&usbphynop1>; - fsl,usbmisc = <&usbmisc 2>; - phy_type = "hsic"; - fsl,anatop = <&anatop>; - dr_mode = "host"; - ahb-burst-config = <0x0>; - tx-burst-size-dword = <0x10>; - rx-burst-size-dword = <0x10>; - status = "disabled"; - }; - - usbmisc: usbmisc@2184800 { - #index-cells = <1>; - compatible = "fsl,imx6sx-usbmisc", "fsl,imx6q-usbmisc"; - reg = <0x02184800 0x200>; - clocks = <&clks IMX6SX_CLK_USBOH3>; - }; - - fec1: ethernet@2188000 { - compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec"; - reg = <0x02188000 0x4000>; - interrupt-names = "int0", "pps"; - interrupts = , - ; - clocks = <&clks IMX6SX_CLK_ENET>, - <&clks IMX6SX_CLK_ENET_AHB>, - <&clks IMX6SX_CLK_ENET_PTP>, - <&clks IMX6SX_CLK_ENET_REF>, - <&clks IMX6SX_CLK_ENET_PTP>; - clock-names = "ipg", "ahb", "ptp", - "enet_clk_ref", "enet_out"; - fsl,num-tx-queues = <3>; - fsl,num-rx-queues = <3>; - status = "disabled"; - }; - - mlb: mlb@218c000 { - reg = <0x0218c000 0x4000>; - interrupts = , - , - ; - clocks = <&clks IMX6SX_CLK_MLB>; - status = "disabled"; - }; - - usdhc1: usdhc@2190000 { - compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc"; - reg = <0x02190000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_USDHC1>, - <&clks IMX6SX_CLK_USDHC1>, - <&clks IMX6SX_CLK_USDHC1>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - status = "disabled"; - }; - - usdhc2: usdhc@2194000 { - compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc"; - reg = <0x02194000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_USDHC2>, - <&clks IMX6SX_CLK_USDHC2>, - <&clks IMX6SX_CLK_USDHC2>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - status = "disabled"; - }; - - usdhc3: usdhc@2198000 { - compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc"; - reg = <0x02198000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_USDHC3>, - <&clks IMX6SX_CLK_USDHC3>, - <&clks IMX6SX_CLK_USDHC3>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - status = "disabled"; - }; - - usdhc4: usdhc@219c000 { - compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc"; - reg = <0x0219c000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_USDHC4>, - <&clks IMX6SX_CLK_USDHC4>, - <&clks IMX6SX_CLK_USDHC4>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - status = "disabled"; - }; - - i2c1: i2c@21a0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c"; - reg = <0x021a0000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_I2C1>; - status = "disabled"; - }; - - i2c2: i2c@21a4000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c"; - reg = <0x021a4000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_I2C2>; - status = "disabled"; - }; - - i2c3: i2c@21a8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c"; - reg = <0x021a8000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_I2C3>; - status = "disabled"; - }; - - memory-controller@21b0000 { - compatible = "fsl,imx6sx-mmdc", "fsl,imx6q-mmdc"; - reg = <0x021b0000 0x4000>; - clocks = <&clks IMX6SX_CLK_MMDC_P0_IPG>; - }; - - fec2: ethernet@21b4000 { - compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec"; - reg = <0x021b4000 0x4000>; - interrupt-names = "int0", "pps"; - interrupts = , - ; - clocks = <&clks IMX6SX_CLK_ENET>, - <&clks IMX6SX_CLK_ENET_AHB>, - <&clks IMX6SX_CLK_ENET_PTP>, - <&clks IMX6SX_CLK_ENET2_REF_125M>, - <&clks IMX6SX_CLK_ENET_PTP>; - clock-names = "ipg", "ahb", "ptp", - "enet_clk_ref", "enet_out"; - status = "disabled"; - }; - - weim: weim@21b8000 { - #address-cells = <2>; - #size-cells = <1>; - compatible = "fsl,imx6sx-weim", "fsl,imx6q-weim"; - reg = <0x021b8000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_EIM_SLOW>; - fsl,weim-cs-gpr = <&gpr>; - status = "disabled"; - }; - - ocotp: ocotp@21bc000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "fsl,imx6sx-ocotp", "syscon"; - reg = <0x021bc000 0x4000>; - clocks = <&clks IMX6SX_CLK_OCOTP>; - - tempmon_calib: calib@38 { - reg = <0x38 4>; - }; - - tempmon_temp_grade: temp-grade@20 { - reg = <0x20 4>; - }; - }; - - sai1: sai@21d4000 { - compatible = "fsl,imx6sx-sai"; - reg = <0x021d4000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_SAI1_IPG>, - <&clks IMX6SX_CLK_SAI1>, - <&clks 0>, <&clks 0>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dma-names = "rx", "tx"; - dmas = <&sdma 31 24 0>, <&sdma 32 24 0>; - status = "disabled"; - }; - - audmux: audmux@21d8000 { - compatible = "fsl,imx6sx-audmux", "fsl,imx31-audmux"; - reg = <0x021d8000 0x4000>; - status = "disabled"; - }; - - sai2: sai@21dc000 { - compatible = "fsl,imx6sx-sai"; - reg = <0x021dc000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_SAI2_IPG>, - <&clks IMX6SX_CLK_SAI2>, - <&clks 0>, <&clks 0>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dma-names = "rx", "tx"; - dmas = <&sdma 33 24 0>, <&sdma 34 24 0>; - status = "disabled"; - }; - - qspi1: spi@21e0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6sx-qspi"; - reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>; - reg-names = "QuadSPI", "QuadSPI-memory"; - interrupts = ; - clocks = <&clks IMX6SX_CLK_QSPI1>, - <&clks IMX6SX_CLK_QSPI1>; - clock-names = "qspi_en", "qspi"; - status = "disabled"; - }; - - qspi2: spi@21e4000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6sx-qspi"; - reg = <0x021e4000 0x4000>, <0x70000000 0x10000000>; - reg-names = "QuadSPI", "QuadSPI-memory"; - interrupts = ; - clocks = <&clks IMX6SX_CLK_QSPI2>, - <&clks IMX6SX_CLK_QSPI2>; - clock-names = "qspi_en", "qspi"; - status = "disabled"; - }; - - uart2: serial@21e8000 { - compatible = "fsl,imx6sx-uart", - "fsl,imx6q-uart", "fsl,imx21-uart"; - reg = <0x021e8000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_UART_IPG>, - <&clks IMX6SX_CLK_UART_SERIAL>; - clock-names = "ipg", "per"; - dmas = <&sdma 27 4 0>, <&sdma 28 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart3: serial@21ec000 { - compatible = "fsl,imx6sx-uart", - "fsl,imx6q-uart", "fsl,imx21-uart"; - reg = <0x021ec000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_UART_IPG>, - <&clks IMX6SX_CLK_UART_SERIAL>; - clock-names = "ipg", "per"; - dmas = <&sdma 29 4 0>, <&sdma 30 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart4: serial@21f0000 { - compatible = "fsl,imx6sx-uart", - "fsl,imx6q-uart", "fsl,imx21-uart"; - reg = <0x021f0000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_UART_IPG>, - <&clks IMX6SX_CLK_UART_SERIAL>; - clock-names = "ipg", "per"; - dmas = <&sdma 31 4 0>, <&sdma 32 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart5: serial@21f4000 { - compatible = "fsl,imx6sx-uart", - "fsl,imx6q-uart", "fsl,imx21-uart"; - reg = <0x021f4000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_UART_IPG>, - <&clks IMX6SX_CLK_UART_SERIAL>; - clock-names = "ipg", "per"; - dmas = <&sdma 33 4 0>, <&sdma 34 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c4: i2c@21f8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c"; - reg = <0x021f8000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_I2C4>; - status = "disabled"; - }; - }; - - aips3: aips-bus@2200000 { - compatible = "fsl,aips-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x02200000 0x100000>; - ranges; - - spba-bus@2240000 { - compatible = "fsl,spba-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x02240000 0x40000>; - ranges; - - csi1: csi@2214000 { - reg = <0x02214000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>, - <&clks IMX6SX_CLK_CSI>, - <&clks IMX6SX_CLK_DCIC1>; - clock-names = "disp-axi", "csi_mclk", "dcic"; - status = "disabled"; - }; - - pxp: pxp@2218000 { - compatible = "fsl,imx6sx-pxp", "fsl,imx6ull-pxp"; - reg = <0x02218000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_PXP_AXI>; - clock-names = "axi"; - power-domains = <&pd_disp>; - status = "disabled"; - }; - - csi2: csi@221c000 { - reg = <0x0221c000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>, - <&clks IMX6SX_CLK_CSI>, - <&clks IMX6SX_CLK_DCIC2>; - clock-names = "disp-axi", "csi_mclk", "dcic"; - status = "disabled"; - }; - - lcdif1: lcdif@2220000 { - compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif"; - reg = <0x02220000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_LCDIF1_PIX>, - <&clks IMX6SX_CLK_LCDIF_APB>, - <&clks IMX6SX_CLK_DISPLAY_AXI>; - clock-names = "pix", "axi", "disp_axi"; - power-domains = <&pd_disp>; - status = "disabled"; - }; - - lcdif2: lcdif@2224000 { - compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif"; - reg = <0x02224000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_LCDIF2_PIX>, - <&clks IMX6SX_CLK_LCDIF_APB>, - <&clks IMX6SX_CLK_DISPLAY_AXI>; - clock-names = "pix", "axi", "disp_axi"; - power-domains = <&pd_disp>; - status = "disabled"; - }; - - vadc: vadc@2228000 { - reg = <0x02228000 0x4000>, <0x0222c000 0x4000>; - reg-names = "vadc-vafe", "vadc-vdec"; - clocks = <&clks IMX6SX_CLK_VADC>, - <&clks IMX6SX_CLK_CSI>; - clock-names = "vadc", "csi"; - power-domains = <&pd_disp>; - status = "disabled"; - }; - }; - - adc1: adc@2280000 { - compatible = "fsl,imx6sx-adc", "fsl,vf610-adc"; - reg = <0x02280000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_IPG>; - clock-names = "adc"; - fsl,adck-max-frequency = <30000000>, <40000000>, - <20000000>; - status = "disabled"; - }; - - adc2: adc@2284000 { - compatible = "fsl,imx6sx-adc", "fsl,vf610-adc"; - reg = <0x02284000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_IPG>; - clock-names = "adc"; - fsl,adck-max-frequency = <30000000>, <40000000>, - <20000000>; - status = "disabled"; - }; - - wdog3: wdog@2288000 { - compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt"; - reg = <0x02288000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_IPG>; - status = "disabled"; - }; - - ecspi5: spi@228c000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; - reg = <0x0228c000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_ECSPI5>, - <&clks IMX6SX_CLK_ECSPI5>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart6: serial@22a0000 { - compatible = "fsl,imx6sx-uart", - "fsl,imx6q-uart", "fsl,imx21-uart"; - reg = <0x022a0000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_UART_IPG>, - <&clks IMX6SX_CLK_UART_SERIAL>; - clock-names = "ipg", "per"; - dmas = <&sdma 0 4 0>, <&sdma 47 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - pwm5: pwm@22a4000 { - compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; - reg = <0x022a4000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_PWM5>, - <&clks IMX6SX_CLK_PWM5>; - clock-names = "ipg", "per"; - #pwm-cells = <2>; - }; - - pwm6: pwm@22a8000 { - compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; - reg = <0x022a8000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_PWM6>, - <&clks IMX6SX_CLK_PWM6>; - clock-names = "ipg", "per"; - #pwm-cells = <2>; - }; - - pwm7: pwm@22ac000 { - compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; - reg = <0x022ac000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_PWM7>, - <&clks IMX6SX_CLK_PWM7>; - clock-names = "ipg", "per"; - #pwm-cells = <2>; - }; - - pwm8: pwm@22b0000 { - compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; - reg = <0x0022b0000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_PWM8>, - <&clks IMX6SX_CLK_PWM8>; - clock-names = "ipg", "per"; - #pwm-cells = <2>; - }; - }; - - pcie: pcie@8ffc000 { - compatible = "fsl,imx6sx-pcie", "snps,dw-pcie"; - reg = <0x08ffc000 0x04000>, <0x08f00000 0x80000>; - reg-names = "dbi", "config"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - bus-range = <0x00 0xff>; - ranges = <0x81000000 0 0 0x08f80000 0 0x00010000 /* downstream I/O */ - 0x82000000 0 0x08000000 0x08000000 0 0x00f00000>; /* non-prefetchable memory */ - num-lanes = <1>; - interrupts = ; - interrupt-names = "msi"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SX_CLK_PCIE_AXI>, - <&clks IMX6SX_CLK_LVDS1_OUT>, - <&clks IMX6SX_CLK_PCIE_REF_125M>, - <&clks IMX6SX_CLK_DISPLAY_AXI>; - clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_inbound_axi"; - power-domains = <&pd_disp>, <&pd_pci>; - power-domain-names = "pcie", "pcie_phy"; - status = "disabled"; - }; - }; -}; diff --git a/sys/gnu/dts/arm/imx6ul-14x14-evk.dts b/sys/gnu/dts/arm/imx6ul-14x14-evk.dts deleted file mode 100644 index 2438669f149..00000000000 --- a/sys/gnu/dts/arm/imx6ul-14x14-evk.dts +++ /dev/null @@ -1,13 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// -// Copyright (C) 2015 Freescale Semiconductor, Inc. - -/dts-v1/; - -#include "imx6ul.dtsi" -#include "imx6ul-14x14-evk.dtsi" - -/ { - model = "Freescale i.MX6 UltraLite 14x14 EVK Board"; - compatible = "fsl,imx6ul-14x14-evk", "fsl,imx6ul"; -}; diff --git a/sys/gnu/dts/arm/imx6ul-14x14-evk.dtsi b/sys/gnu/dts/arm/imx6ul-14x14-evk.dtsi deleted file mode 100644 index 265bf4108cb..00000000000 --- a/sys/gnu/dts/arm/imx6ul-14x14-evk.dtsi +++ /dev/null @@ -1,596 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// -// Copyright (C) 2015 Freescale Semiconductor, Inc. - -/ { - chosen { - stdout-path = &uart1; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000>; - }; - - backlight_display: backlight-display { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - status = "okay"; - }; - - - reg_sd1_vmmc: regulator-sd1-vmmc { - compatible = "regulator-fixed"; - regulator-name = "VSD_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_peri_3v3: regulator-peri-3v3 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_peri_3v3>; - regulator-name = "VPERI_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio5 2 GPIO_ACTIVE_LOW>; - /* - * If you want to want to make this dynamic please - * check schematics and test all affected peripherals: - * - * - sensors - * - ethernet phy - * - can - * - bluetooth - * - wm8960 audio codec - * - ov5640 camera - */ - regulator-always-on; - }; - - reg_can_3v3: regulator-can-3v3 { - compatible = "regulator-fixed"; - regulator-name = "can-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpios = <&gpio_spi 3 GPIO_ACTIVE_LOW>; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "mx6ul-wm8960"; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&dailink_master>; - simple-audio-card,frame-master = <&dailink_master>; - simple-audio-card,widgets = - "Microphone", "Mic Jack", - "Line", "Line In", - "Line", "Line Out", - "Speaker", "Speaker", - "Headphone", "Headphone Jack"; - simple-audio-card,routing = - "Headphone Jack", "HP_L", - "Headphone Jack", "HP_R", - "Speaker", "SPK_LP", - "Speaker", "SPK_LN", - "Speaker", "SPK_RP", - "Speaker", "SPK_RN", - "LINPUT1", "Mic Jack", - "LINPUT3", "Mic Jack", - "RINPUT1", "Mic Jack", - "RINPUT2", "Mic Jack"; - - simple-audio-card,cpu { - sound-dai = <&sai2>; - }; - - dailink_master: simple-audio-card,codec { - sound-dai = <&codec>; - clocks = <&clks IMX6UL_CLK_SAI2>; - }; - }; - - spi4 { - compatible = "spi-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi4>; - status = "okay"; - gpio-sck = <&gpio5 11 0>; - gpio-mosi = <&gpio5 10 0>; - cs-gpios = <&gpio5 7 0>; - num-chipselects = <1>; - #address-cells = <1>; - #size-cells = <0>; - - gpio_spi: gpio@0 { - compatible = "fairchild,74hc595"; - gpio-controller; - #gpio-cells = <2>; - reg = <0>; - registers-number = <1>; - spi-max-frequency = <100000>; - }; - }; - - panel { - compatible = "innolux,at043tn24"; - backlight = <&backlight_display>; - - port { - panel_in: endpoint { - remote-endpoint = <&display_out>; - }; - }; - }; -}; - -&clks { - assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; - assigned-clock-rates = <786432000>; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - codec: wm8960@1a { - #sound-dai-cells = <0>; - compatible = "wlf,wm8960"; - reg = <0x1a>; - wlf,shared-lrclk; - }; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet1>; - phy-mode = "rmii"; - phy-handle = <ðphy0>; - phy-supply = <®_peri_3v3>; - status = "okay"; -}; - -&fec2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet2>; - phy-mode = "rmii"; - phy-handle = <ðphy1>; - phy-supply = <®_peri_3v3>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@2 { - reg = <2>; - micrel,led-mode = <1>; - clocks = <&clks IMX6UL_CLK_ENET_REF>; - clock-names = "rmii-ref"; - }; - - ethphy1: ethernet-phy@1 { - reg = <1>; - micrel,led-mode = <1>; - clocks = <&clks IMX6UL_CLK_ENET2_REF>; - clock-names = "rmii-ref"; - }; - }; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - xceiver-supply = <®_can_3v3>; - status = "okay"; -}; - -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - xceiver-supply = <®_can_3v3>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - magnetometer@e { - compatible = "fsl,mag3110"; - reg = <0x0e>; - vdd-supply = <®_peri_3v3>; - vddio-supply = <®_peri_3v3>; - }; -}; - -&lcdif { - assigned-clocks = <&clks IMX6UL_CLK_LCDIF_PRE_SEL>; - assigned-clock-parents = <&clks IMX6UL_CLK_PLL5_VIDEO_DIV>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcdif_dat - &pinctrl_lcdif_ctrl>; - status = "okay"; - - port { - display_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "okay"; -}; - -&qspi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_qspi>; - status = "okay"; - - flash0: n25q256a@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "micron,n25q256a", "jedec,spi-nor"; - spi-max-frequency = <29000000>; - spi-rx-bus-width = <4>; - spi-tx-bus-width = <4>; - reg = <0>; - }; -}; - -&sai2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai2>; - assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>, - <&clks IMX6UL_CLK_SAI2>; - assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; - assigned-clock-rates = <0>, <12288000>; - fsl,sai-mclk-direction-output; - status = "okay"; -}; - -&snvs_poweroff { - status = "okay"; -}; - -&snvs_pwrkey { - status = "okay"; -}; - -&tsc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_tsc>; - xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; - measure-delay-time = <0xffff>; - pre-charge-time = <0xfff>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - uart-has-rtscts; - status = "okay"; -}; - -&usbotg1 { - dr_mode = "otg"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_otg1>; - status = "okay"; -}; - -&usbotg2 { - dr_mode = "host"; - disable-over-current; - status = "okay"; -}; - -&usbphy1 { - fsl,tx-d-cal = <106>; -}; - -&usbphy2 { - fsl,tx-d-cal = <106>; -}; - -&usdhc1 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>; - cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; - keep-power-in-suspend; - wakeup-source; - vmmc-supply = <®_sd1_vmmc>; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - no-1-8-v; - broken-cd; - keep-power-in-suspend; - wakeup-source; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; -}; - -&iomuxc { - pinctrl-names = "default"; - - pinctrl_csi1: csi1grp { - fsl,pins = < - MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088 - MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088 - MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088 - MX6UL_PAD_CSI_HSYNC__CSI_HSYNC 0x1b088 - MX6UL_PAD_CSI_DATA00__CSI_DATA02 0x1b088 - MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x1b088 - MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x1b088 - MX6UL_PAD_CSI_DATA03__CSI_DATA05 0x1b088 - MX6UL_PAD_CSI_DATA04__CSI_DATA06 0x1b088 - MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x1b088 - MX6UL_PAD_CSI_DATA06__CSI_DATA08 0x1b088 - MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x1b088 - >; - }; - - pinctrl_enet1: enet1grp { - fsl,pins = < - MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 - MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 - MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 - MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 - MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 - MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 - MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 - MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 - >; - }; - - pinctrl_enet2: enet2grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 - MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 - MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 - MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 - MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 - MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 - MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 - MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 - MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 - MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 - >; - }; - - pinctrl_flexcan1: flexcan1grp{ - fsl,pins = < - MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020 - MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020 - >; - }; - - pinctrl_flexcan2: flexcan2grp{ - fsl,pins = < - MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 - MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 - MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 - MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 - >; - }; - - pinctrl_lcdif_dat: lcdifdatgrp { - fsl,pins = < - MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 - MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 - MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 - MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 - MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 - MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 - MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 - MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 - MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 - MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 - MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 - MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 - MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 - MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 - MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 - MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 - MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 - MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 - MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79 - MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79 - MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79 - MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79 - MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79 - MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79 - >; - }; - - pinctrl_lcdif_ctrl: lcdifctrlgrp { - fsl,pins = < - MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 - MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 - MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 - MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 - /* used for lcd reset */ - MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79 - >; - }; - - pinctrl_qspi: qspigrp { - fsl,pins = < - MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1 - MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1 - MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1 - MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1 - MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1 - MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 - >; - }; - - pinctrl_sai2: sai2grp { - fsl,pins = < - MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 - MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 - MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088 - MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088 - MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088 - MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x17059 - >; - }; - - pinctrl_peri_3v3: peri3v3grp { - fsl,pins = < - MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x110b0 - >; - }; - - pinctrl_sim2: sim2grp { - fsl,pins = < - MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD 0xb808 - MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK 0x31 - MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B 0xb808 - MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN 0xb808 - MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD 0xb809 - MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x3008 - >; - }; - - pinctrl_spi4: spi4grp { - fsl,pins = < - MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x70a1 - MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x70a1 - MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x70a1 - MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x80000000 - >; - }; - - pinctrl_tsc: tscgrp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 - MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 - MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 - MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 - MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 - MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 - MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1 - MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1 - >; - }; - - pinctrl_usb_otg1: usbotg1grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 - MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */ - MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */ - MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */ - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1grp100mhz { - fsl,pins = < - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 - - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1grp200mhz { - fsl,pins = < - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17059 - MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 - MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 - MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 - MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 - MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0 - >; - }; -}; diff --git a/sys/gnu/dts/arm/imx6ul-ccimx6ulsbcexpress.dts b/sys/gnu/dts/arm/imx6ul-ccimx6ulsbcexpress.dts deleted file mode 100644 index 3792679c0c9..00000000000 --- a/sys/gnu/dts/arm/imx6ul-ccimx6ulsbcexpress.dts +++ /dev/null @@ -1,200 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Digi International's ConnectCore6UL SBC Express board device tree source - * - * Copyright 2018 Digi International, Inc. - * - */ - -/dts-v1/; -#include -#include -#include "imx6ul.dtsi" -#include "imx6ul-ccimx6ulsom.dtsi" - -/ { - model = "Digi International ConnectCore 6UL SBC Express."; - compatible = "digi,ccimx6ulsbcexpress", "digi,ccimx6ulsom", - "fsl,imx6ul"; -}; - -&adc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_adc1>; - status = "okay"; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - xceiver-supply = <&ext_3v3>; - status = "okay"; -}; - -&ecspi3 { - cs-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi3_master>; - status = "okay"; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet1>; - phy-mode = "rmii"; - phy-handle = <ðphy0>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - smsc,disable-energy-detect; - reg = <0>; - }; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - status = "okay"; -}; - -&usbotg1 { - dr_mode = "host"; - disable-over-current; - status = "okay"; -}; - -&usbotg2 { - dr_mode = "host"; - disable-over-current; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - broken-cd; /* no carrier detect line (use polling) */ - no-1-8-v; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_adc1: adc1grp { - fsl,pins = < - /* GPIO1_4/ADC1_IN4 (pin 7 of the expansion header) */ - MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 - >; - }; - - pinctrl_ecspi3_master: ecspi3grp1 { - fsl,pins = < - MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK 0x10b0 - MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI 0x10b0 - MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO 0x10b0 - MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x10b0 /* Chip Select */ - >; - }; - - pinctrl_ecspi3_slave: ecspi3grp2 { - fsl,pins = < - MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK 0x10b0 - MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI 0x10b0 - MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO 0x10b0 - MX6UL_PAD_UART2_TX_DATA__ECSPI3_SS0 0x10b0 /* Chip Select */ - >; - }; - - pinctrl_enet1: enet1grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 - MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 - MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 - MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 - MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 - MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 - MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 - MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 - MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 - MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x40017051 - >; - }; - - pinctrl_flexcan1: flexcan1grp{ - fsl,pins = < - MX6UL_PAD_LCD_DATA08__FLEXCAN1_TX 0x1b020 - MX6UL_PAD_LCD_DATA09__FLEXCAN1_RX 0x1b020 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO00__I2C2_SCL 0x4001b8b0 - MX6UL_PAD_GPIO1_IO01__I2C2_SDA 0x4001b8b0 - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX6UL_PAD_LCD_DATA00__PWM1_OUT 0x10b0 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6UL_PAD_LCD_CLK__UART4_DCE_TX 0x1b0b1 - MX6UL_PAD_LCD_ENABLE__UART4_DCE_RX 0x1b0b1 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x1b0b1 - MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x1b0b1 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x17059 - MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x10071 - MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x17059 - MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x17059 - MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x17059 - MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17059 - >; - }; - - /* General purpose pinctrl */ - pinctrl_hog: hoggrp { - fsl,pins = < - /* GPIOs BANK 3 */ - MX6UL_PAD_LCD_RESET__GPIO3_IO04 0xf030 - >; - }; -}; diff --git a/sys/gnu/dts/arm/imx6ul-ccimx6ulsbcpro.dts b/sys/gnu/dts/arm/imx6ul-ccimx6ulsbcpro.dts deleted file mode 100644 index 3749fdda361..00000000000 --- a/sys/gnu/dts/arm/imx6ul-ccimx6ulsbcpro.dts +++ /dev/null @@ -1,427 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Digi International's ConnectCore6UL SBC Pro board device tree source - * - * Copyright 2018 Digi International, Inc. - * - */ - -/dts-v1/; -#include -#include -#include "imx6ul.dtsi" -#include "imx6ul-ccimx6ulsom.dtsi" - -/ { - model = "Digi International ConnectCore 6UL SBC Pro."; - compatible = "digi,ccimx6ulsbcpro", "digi,ccimx6ulsom", "fsl,imx6ul"; - - lcd_backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm5 0 50000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - status = "okay"; - }; - - panel { - compatible = "auo,g101evn010", "simple-panel"; - power-supply = <&ldo4_ext>; - backlight = <&lcd_backlight>; - - port { - panel_in: endpoint { - remote-endpoint = <&display_out>; - }; - }; - }; - - reg_usb_otg1_vbus: regulator-usb-otg1 { - compatible = "regulator-fixed"; - regulator-name = "usb_otg1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&adc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_adc1>; - status = "okay"; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - xceiver-supply = <&ext_3v3>; - status = "okay"; -}; - -/* CAN2 is multiplexed with UART2 RTS/CTS */ -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - xceiver-supply = <&ext_3v3>; - status = "disabled"; -}; - -&ecspi1 { - cs-gpios = <&gpio3 26 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1_master>; - status = "okay"; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet1>; - phy-mode = "rmii"; - phy-handle = <ðphy0>; - status = "okay"; -}; - -&fec2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_mdio>; - phy-mode = "rmii"; - phy-handle = <ðphy1>; - phy-reset-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>; - phy-reset-duration = <26>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - smsc,disable-energy-detect; - reg = <0>; - }; - - ethphy1: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - smsc,disable-energy-detect; - reg = <1>; - }; - }; -}; - -&gpio5 { - emmc-usd-mux { - gpio-hog; - gpios = <1 GPIO_ACTIVE_LOW>; - output-high; - }; -}; - -&i2c1 { - touchscreen@14 { - compatible = "goodix,gt911"; - reg = <0x14>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_goodix_touch>; - interrupt-parent = <&gpio5>; - interrupts = <2 IRQ_TYPE_EDGE_RISING>; - irq-gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; -}; - -&lcdif { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcdif_dat0_17 - &pinctrl_lcdif_clken - &pinctrl_lcdif_hvsync>; - lcd-supply = <&ldo4_ext>; /* BU90T82 LVDS bridge power */ - status = "okay"; - - port { - display_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; -}; - -&ldo4_ext { - regulator-max-microvolt = <1800000>; -}; - -&pwm1 { - status = "okay"; -}; - -&pwm2 { - status = "okay"; -}; - -&pwm3 { - status = "okay"; -}; - -&pwm4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm4>; - status = "okay"; -}; - -&pwm5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm5>; - status = "okay"; -}; - -&pwm6 { - status = "okay"; -}; - -&pwm7 { - status = "okay"; -}; - -&pwm8 { - status = "okay"; -}; - -&sai2 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&pinctrl_sai2>; - pinctrl-1 = <&pinctrl_sai2_sleep>; - assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>, - <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>, - <&clks IMX6UL_CLK_SAI2>; - assigned-clock-rates = <0>, <786432000>, <12288000>; - assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; - status = "okay"; -}; - -/* UART2 RTS/CTS muxed with CAN2 */ -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2_4wires>; - uart-has-rtscts; - status = "okay"; -}; - -/* UART3 RTS/CTS muxed with CAN 1 */ -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3_2wires>; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - status = "okay"; -}; - -&usbotg1 { - dr_mode = "otg"; - vbus-supply = <®_usb_otg1_vbus>; - pinctrl-0 = <&pinctrl_usbotg1>; - status = "okay"; -}; - -&usbotg2 { - dr_mode = "host"; - disable-over-current; - status = "okay"; -}; - -/* USDHC2 (microSD conflicts with eMMC) */ -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - no-1-8-v; - broken-cd; /* no carrier detect line (use polling) */ - status = "okay"; -}; - -&iomuxc { - pinctrl_adc1: adc1grp { - fsl,pins = < - /* EXP_GPIO_2 -> GPIO1_3/ADC1_IN3 */ - MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 - >; - }; - - pinctrl_ecspi1_master: ecspi1grp1 { - fsl,pins = < - MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x10b0 - MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x10b0 - MX6UL_PAD_LCD_DATA23__ECSPI1_MISO 0x10b0 - MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x10b0 - >; - }; - - pinctrl_enet1: enet1grp { - fsl,pins = < - MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 - MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 - MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 - MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 - MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 - MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 - MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 - MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x40017051 - >; - }; - - pinctrl_enet2: enet2grp { - fsl,pins = < - MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 - MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 - MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 - MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 - MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 - MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 - MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 - MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x40017051 - >; - }; - - pinctrl_enet2_mdio: mdioenet2grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 - MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 - >; - }; - - pinctrl_flexcan1: flexcan1grp{ - fsl,pins = < - MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020 - MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020 - >; - }; - pinctrl_flexcan2: flexcan2grp{ - fsl,pins = < - MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 - MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 - >; - }; - - pinctrl_goodix_touch: goodixgrp{ - fsl,pins = < - MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1020 - >; - }; - - pinctrl_lcdif_dat0_17: lcdifdatgrp0-17 { - fsl,pins = < - MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 - MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 - MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 - MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 - MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 - MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 - MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 - MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 - MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 - MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 - MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 - MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 - MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 - MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 - MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 - MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 - MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 - MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 - >; - }; - - pinctrl_lcdif_clken: lcdifctrlgrp1 { - fsl,pins = < - MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x17050 - MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 - >; - }; - - pinctrl_lcdif_hvsync: lcdifctrlgrp2 { - fsl,pins = < - MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 - MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 - >; - }; - - pinctrl_pwm4: pwm4grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO05__PWM4_OUT 0x110b0 - >; - }; - - pinctrl_pwm5: pwm5grp { - fsl,pins = < - MX6UL_PAD_NAND_DQS__PWM5_OUT 0x110b0 - >; - }; - - pinctrl_sai2: sai2grp { - fsl,pins = < - MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088 - MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088 - MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088 - MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 - MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 - /* Interrupt */ - MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x10b0 - >; - }; - - pinctrl_sai2_sleep: sai2grp-sleep { - fsl,pins = < - MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15 0x3000 - MX6UL_PAD_JTAG_TCK__GPIO1_IO14 0x3000 - MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x3000 - MX6UL_PAD_JTAG_TDO__GPIO1_IO12 0x3000 - /* Interrupt */ - MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x3000 - >; - }; - - pinctrl_uart2_4wires: uart2grp-4wires { - fsl,pins = < - MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 - MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 - MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS 0x1b0b1 - MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS 0x1b0b1 - >; - }; - - pinctrl_uart3_2wires: uart3grp-2wires { - fsl,pins = < - MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1 - MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x1b0b1 - MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x1b0b1 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x17059 - MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x10039 - MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x17059 - MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x17059 - MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x17059 - MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17059 - /* Mux selector between eMMC/SD# */ - MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x79 - >; - }; - - pinctrl_usbotg1: usbotg1grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 - MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x17059 - MX6UL_PAD_GPIO1_IO01__USB_OTG1_OC 0x17059 - >; - }; -}; diff --git a/sys/gnu/dts/arm/imx6ul-ccimx6ulsom.dtsi b/sys/gnu/dts/arm/imx6ul-ccimx6ulsom.dtsi deleted file mode 100644 index b5781c3656d..00000000000 --- a/sys/gnu/dts/arm/imx6ul-ccimx6ulsom.dtsi +++ /dev/null @@ -1,270 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Digi International's ConnectCore 6UL System-On-Module device tree source - * - * Copyright 2018 Digi International, Inc. - * - */ - -/ { - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0>; /* will be filled by U-Boot */ - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - linux,cma { - compatible = "shared-dma-pool"; - reusable; - size = <0x4000000>; - linux,cma-default; - }; - }; -}; - -&adc1 { - vref-supply = <&vdda_adc_3v3>; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pfuze3000: pmic@8 { - compatible = "fsl,pfuze3000"; - reg = <0x08>; - - regulators { - int_3v3: sw1a { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <6250>; - regulator-boot-on; - regulator-always-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_arm_soc_in: sw1b { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1475000>; - regulator-ramp-delay = <6250>; - regulator-boot-on; - regulator-always-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <925000>; - }; - }; - - ext_3v3: sw2 { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <6250>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_ddr3: sw3 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1650000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1300000>; - }; - }; - - swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - }; - - vdd_snvs_3v3: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - vrefddr: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - vdda_adc_3v3: vldo1 { - compatible = "regulator-fixed"; - regulator-name = "vref-adc-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo2_ext: vldo2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vdda_wlan: vccsd { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_high_in: v33 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo3_int: vldo3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - ldo4_ext: vldo4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - vcoin_chg: vcoin { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <3300000>; - }; - }; - }; -}; - -/* UART1 (Bluetooth) */ -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - uart-has-rtscts; - status = "okay"; -}; - -/* USDHC1 (Wireless) */ -&usdhc1 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_wifibt_ctrl>; - pinctrl-1 = <&pinctrl_usdhc1_sleep &pinctrl_wifibt_ctrl_sleep>; - non-removable; - no-1-8-v; - bus-width = <4>; - status = "okay"; -}; - -&iomuxc { - pinctrl_gpmi_nand: gpmigrp { - fsl,pins = < - MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1 - MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1 - MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1 - MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1 - MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1 - MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1 - MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1 - MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1 - MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1 - MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1 - MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1 - MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1 - MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1 - MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1 - MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb0b1 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 - MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 - MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 - MX6UL_PAD_UART1_RTS_B__UART1_DCE_RTS 0x1b0b1 - MX6UL_PAD_UART1_CTS_B__UART1_DCE_CTS 0x1b0b1 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x17051 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 - >; - }; - - pinctrl_usdhc1_sleep: usdhc1grp-sleep { - fsl,pins = < - MX6UL_PAD_SD1_CMD__GPIO2_IO16 0x3000 - MX6UL_PAD_SD1_CLK__GPIO2_IO17 0x3000 - MX6UL_PAD_SD1_DATA0__GPIO2_IO18 0x3000 - MX6UL_PAD_SD1_DATA1__GPIO2_IO19 0x3000 - MX6UL_PAD_SD1_DATA2__GPIO2_IO20 0x3000 - MX6UL_PAD_SD1_DATA3__GPIO2_IO21 0x3000 - >; - }; - - pinctrl_wifibt_ctrl: wifibt-ctrl-grp { - fsl,pins = < - MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x08a0 - MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x08a0 - >; - }; - - pinctrl_wifibt_ctrl_sleep: wifibt-ctrl-grp-sleep { - fsl,pins = < - MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x3000 - MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x3000 - >; - }; -}; - -®_arm { - vin-supply = <&vdd_arm_soc_in>; - regulator-allow-bypass; -}; - -®_soc { - vin-supply = <&vdd_arm_soc_in>; - regulator-allow-bypass; -}; diff --git a/sys/gnu/dts/arm/imx6ul-geam.dts b/sys/gnu/dts/arm/imx6ul-geam.dts deleted file mode 100644 index 9f63706383a..00000000000 --- a/sys/gnu/dts/arm/imx6ul-geam.dts +++ /dev/null @@ -1,446 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR X11 -/* - * Copyright (C) 2016 Amarula Solutions B.V. - * Copyright (C) 2016 Engicam S.r.l. - */ - -/dts-v1/; - -#include -#include -#include "imx6ul.dtsi" - -/ { - model = "Engicam GEAM6UL Starter Kit"; - compatible = "engicam,imx6ul-geam", "fsl,imx6ul"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x08000000>; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm8 0 100000>; - brightness-levels = < 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100>; - default-brightness-level = <100>; - }; - - chosen { - stdout-path = &uart1; - }; - - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-name = "1P8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "imx6ul-geam-sgtl5000"; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&dailink_master>; - simple-audio-card,frame-master = <&dailink_master>; - simple-audio-card,widgets = - "Microphone", "Mic Jack", - "Line", "Line In", - "Line", "Line Out", - "Headphone", "Headphone Jack"; - simple-audio-card,routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - - simple-audio-card,cpu { - sound-dai = <&sai2>; - }; - - dailink_master: simple-audio-card,codec { - sound-dai = <&sgtl5000>; - clocks = <&clks IMX6UL_CLK_SAI2>; - }; - }; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - xceiver-supply = <®_3p3v>; - status = "okay"; -}; - -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - xceiver-supply = <®_3p3v>; - status = "okay"; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet1>; - phy-mode = "rmii"; - phy-handle = <ðphy0>; - status = "okay"; -}; - -&fec2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet2>; - phy-mode = "rmii"; - phy-handle = <ðphy1>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - }; - - ethphy1: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; - }; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - nand-on-flash-bbt; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - sgtl5000: codec@a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - #sound-dai-cells = <0>; - clocks = <&clks IMX6UL_CLK_OSC>; - clock-names = "mclk"; - VDDA-supply = <®_3p3v>; - VDDIO-supply = <®_3p3v>; - VDDD-supply = <®_1p8v>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&lcdif { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcdif_dat - &pinctrl_lcdif_ctrl>; - display = <&display0>; - status = "okay"; - - display0: display0 { - bits-per-pixel = <16>; - bus-width = <18>; - - display-timings { - native-mode = <&timing0>; - timing0: timing0 { - clock-frequency = <28000000>; - hactive = <800>; - vactive = <480>; - hfront-porch = <30>; - hback-porch = <30>; - hsync-len = <64>; - vback-porch = <5>; - vfront-porch = <5>; - vsync-len = <20>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - }; - }; -}; - -&pwm8 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm8>; - status = "okay"; -}; - -&tsc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_tsc>; - xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; -}; - -&sai2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai2>; - status = "okay"; -}; - -&tsc { - measure-delay-time = <0x1ffff>; - pre-charge-time = <0x1fff>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&usbotg1 { - dr_mode = "peripheral"; - status = "okay"; -}; - -&usbotg2 { - dr_mode = "host"; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>; - bus-width = <4>; - cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; - no-1-8-v; - status = "okay"; -}; - -&iomuxc { - pinctrl_enet1: enet1grp { - fsl,pins = < - MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 - MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 - MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 - MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 - MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 - MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 - MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 - >; - }; - - pinctrl_enet2: enet2grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 - MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 - MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 - MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x1b0b0 /* ENET_nRST */ - MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 - MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 - MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 - MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 - MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 - MX6UL_PAD_GPIO1_IO05__ENET2_REF_CLK2 0x4001b031 - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020 - MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020 - >; - }; - - pinctrl_flexcan2: flexcan2grp { - fsl,pins = < - MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 - MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 - >; - }; - - pinctrl_gpmi_nand: gpminandgrp { - fsl,pins = < - MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1 - MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1 - MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1 - MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000 - MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1 - MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1 - MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1 - MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1 - MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1 - MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1 - MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1 - MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1 - MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1 - MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1 - MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 - MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 - MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 - >; - }; - - pinctrl_lcdif_ctrl: lcdifctrlgrp { - fsl,pins = < - MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 - MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 - MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 - MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 - >; - }; - - pinctrl_lcdif_dat: lcdifdatgrp { - fsl,pins = < - MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 - MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 - MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 - MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 - MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 - MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 - MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 - MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 - MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 - MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 - MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 - MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 - MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 - MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 - MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 - MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 - MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 - MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 - >; - }; - - pinctrl_pwm8: pwm8grp { - fsl,pins = < - MX6UL_PAD_ENET1_RX_ER__PWM8_OUT 0x110b0 - >; - }; - - pinctrl_tsc: tscgrp { - fsl,pin = < - MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 - MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 - MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 - MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 - >; - }; - - pinctrl_sai2: sai2grp { - fsl,pins = < - MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x130b0 - MX6UL_PAD_JTAG_TMS__CCM_CLKO1 0x4001b031 - MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 - MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 - MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x120b0 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 - MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 - MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 - MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1 - MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1grp100mhz { - fsl,pins = < - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1grp200mhz { - fsl,pins = < - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x17070 - MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x10070 - MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x17070 - MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x17070 - MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x17070 - MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17070 - >; - }; -}; diff --git a/sys/gnu/dts/arm/imx6ul-imx6ull-opos6ul.dtsi b/sys/gnu/dts/arm/imx6ul-imx6ull-opos6ul.dtsi deleted file mode 100644 index f2386dcb9ff..00000000000 --- a/sys/gnu/dts/arm/imx6ul-imx6ull-opos6ul.dtsi +++ /dev/null @@ -1,148 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT -// -// Copyright 2019 Armadeus Systems - -/ { - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0>; /* will be filled by U-Boot */ - }; - - reg_3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - usdhc3_pwrseq: usdhc3-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>; - }; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet1>; - phy-mode = "rmii"; - phy-reset-duration = <1>; - phy-reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; - phy-handle = <ðphy1>; - phy-supply = <®_3v3>; - status = "okay"; - - mdio: mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy1: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - interrupt-parent = <&gpio4>; - interrupts = <16 IRQ_TYPE_LEVEL_LOW>; - status = "okay"; - }; - }; -}; - -/* Bluetooth */ -&uart8 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart8>; - uart-has-rtscts; - status = "okay"; -}; - -/* eMMC */ -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - bus-width = <8>; - no-1-8-v; - non-removable; - status = "okay"; -}; - -/* WiFi */ -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - bus-width = <4>; - no-1-8-v; - non-removable; - mmc-pwrseq = <&usdhc3_pwrseq>; - status = "okay"; - - #address-cells = <1>; - #size-cells = <0>; - - brcmf: wifi@1 { - compatible = "brcm,bcm4329-fmac"; - reg = <1>; - interrupt-parent = <&gpio2>; - interrupts = <8 IRQ_TYPE_LEVEL_LOW>; - interrupt-names = "host-wake"; - }; -}; - -&iomuxc { - pinctrl_enet1: enet1grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 - MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 - MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x130b0 - MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x130b0 - MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x130b0 - MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x130b0 - MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 - MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 - MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 - /* INT# */ - MX6UL_PAD_NAND_DQS__GPIO4_IO16 0x1b0b0 - /* RST# */ - MX6UL_PAD_NAND_DATA00__GPIO4_IO02 0x130b0 - MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 - >; - }; - - pinctrl_uart8: uart8grp { - fsl,pins = < - MX6UL_PAD_ENET2_TX_EN__UART8_DCE_RX 0x1b0b0 - MX6UL_PAD_ENET2_TX_DATA1__UART8_DCE_TX 0x1b0b0 - MX6UL_PAD_ENET2_RX_ER__UART8_DCE_RTS 0x1b0b0 - MX6UL_PAD_ENET2_TX_CLK__UART8_DCE_CTS 0x1b0b0 - /* BT_REG_ON */ - MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x130b0 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 - MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x17059 - MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x17059 - MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x17059 - MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x17059 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6UL_PAD_LCD_DATA18__USDHC2_CMD 0x1b0b0 - MX6UL_PAD_LCD_DATA19__USDHC2_CLK 0x100b0 - MX6UL_PAD_LCD_DATA20__USDHC2_DATA0 0x1b0b0 - MX6UL_PAD_LCD_DATA21__USDHC2_DATA1 0x1b0b0 - MX6UL_PAD_LCD_DATA22__USDHC2_DATA2 0x1b0b0 - MX6UL_PAD_LCD_DATA23__USDHC2_DATA3 0x1b0b0 - /* WL_REG_ON */ - MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09 0x130b0 - /* WL_IRQ */ - MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x1b0b0 - >; - }; -}; diff --git a/sys/gnu/dts/arm/imx6ul-imx6ull-opos6uldev.dtsi b/sys/gnu/dts/arm/imx6ul-imx6ull-opos6uldev.dtsi deleted file mode 100644 index 18966350bfd..00000000000 --- a/sys/gnu/dts/arm/imx6ul-imx6ull-opos6uldev.dtsi +++ /dev/null @@ -1,338 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT -// -// Copyright 2019 Armadeus Systems - -/ { - chosen { - stdout-path = &uart1; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm3 0 191000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <7>; - power-supply = <®_5v>; - status = "okay"; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_keys>; - - user-button { - label = "User button"; - gpios = <&gpio2 11 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - - user-led { - label = "User"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_led>; - gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - onewire { - compatible = "w1-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_w1>; - gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; - }; - - panel: panel { - compatible = "armadeus,st0700-adapt"; - power-supply = <®_3v3>; - backlight = <&backlight>; - - port { - panel_in: endpoint { - remote-endpoint = <&lcdif_out>; - }; - }; - }; - - reg_5v: regulator-5v { - compatible = "regulator-fixed"; - regulator-name = "5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_usbotg1_vbus: regulator-usbotg1vbus { - compatible = "regulator-fixed"; - regulator-name = "usbotg1vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg1_vbus>; - gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usbotg2_vbus: regulator-usbotg2vbus { - compatible = "regulator-fixed"; - regulator-name = "usbotg2vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg2_vbus>; - gpio = <&gpio5 9 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&adc1 { - vref-supply = <®_3v3>; - status = "okay"; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - xceiver-supply = <®_5v>; - status = "okay"; -}; - -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - xceiver-supply = <®_5v>; - status = "okay"; -}; - -&ecspi4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi4>; - cs-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>, <&gpio4 3 GPIO_ACTIVE_LOW>; - status = "okay"; - - spidev0: spi@0 { - compatible = "spidev"; - reg = <0>; - spi-max-frequency = <5000000>; - }; - - spidev1: spi@1 { - compatible = "spidev"; - reg = <1>; - spi-max-frequency = <5000000>; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - clock-frequency = <400000>; - status = "okay"; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - clock-frequency = <400000>; - status = "okay"; -}; - -&lcdif { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcdif>; - status = "okay"; - - port { - lcdif_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; - status = "okay"; -}; - -&snvs_pwrkey { - status = "disabled"; -}; - -&tsc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_tsc>; - xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; - measure-delay-time = <0xffff>; - pre-charge-time = <0xffff>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&usbotg1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg1_id>; - vbus-supply = <®_usbotg1_vbus>; - dr_mode = "otg"; - disable-over-current; - status = "okay"; -}; - -&usbotg2 { - vbus-supply = <®_usbotg2_vbus>; - dr_mode = "host"; - disable-over-current; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpios>; - - pinctrl_ecspi4: ecspi4grp { - fsl,pins = < - MX6UL_PAD_NAND_DATA04__ECSPI4_SCLK 0x1b0b0 - MX6UL_PAD_NAND_DATA05__ECSPI4_MOSI 0x1b0b0 - MX6UL_PAD_NAND_DATA06__ECSPI4_MISO 0x1b0b0 - MX6UL_PAD_NAND_DATA01__GPIO4_IO03 0x1b0b0 - MX6UL_PAD_NAND_DATA07__GPIO4_IO09 0x1b0b0 - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x0b0b0 - MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x0b0b0 - >; - }; - - pinctrl_flexcan2: flexcan2grp { - fsl,pins = < - MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x0b0b0 - MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x0b0b0 - >; - }; - - pinctrl_gpios: gpiosgrp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x0b0b0 - MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x0b0b0 - MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24 0x0b0b0 - MX6UL_PAD_NAND_RE_B__GPIO4_IO00 0x0b0b0 - MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0x0b0b0 - MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x0b0b0 - MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x0b0b0 - MX6UL_PAD_NAND_WE_B__GPIO4_IO01 0x0b0b0 - >; - }; - - pinctrl_gpio_keys: gpiokeysgrp { - fsl,pins = < - MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11 0x0b0b0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 - MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 - MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 - >; - }; - - pinctrl_lcdif: lcdifgrp { - fsl,pins = < - MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x100b1 - MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x100b1 - MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x100b1 - MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x100b1 - MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x100b1 - MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x100b1 - MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x100b1 - MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x100b1 - MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x100b1 - MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x100b1 - MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x100b1 - MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x100b1 - MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x100b1 - MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x100b1 - MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x100b1 - MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x100b1 - MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x100b1 - MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x100b1 - MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x100b1 - MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x100b1 - MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x100b1 - MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x100b1 - >; - }; - - pinctrl_led: ledgrp { - fsl,pins = < - MX6UL_PAD_LCD_RESET__GPIO3_IO04 0x0b0b0 - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6UL_PAD_NAND_ALE__PWM3_OUT 0x1b0b0 - >; - }; - - pinctrl_tsc: tscgrp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 - MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 - MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 - MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 - MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 - MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 - >; - }; - - pinctrl_usbotg1_id: usbotg1idgrp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x1b0b0 - >; - }; - - pinctrl_usbotg1_vbus: usbotg1vbusgrp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO05__GPIO1_IO05 0x1b0b0 - >; - }; -}; diff --git a/sys/gnu/dts/arm/imx6ul-isiot-emmc.dts b/sys/gnu/dts/arm/imx6ul-isiot-emmc.dts deleted file mode 100644 index 1df3e376ae2..00000000000 --- a/sys/gnu/dts/arm/imx6ul-isiot-emmc.dts +++ /dev/null @@ -1,18 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR X11 -/* - * Copyright (C) 2016 Amarula Solutions B.V. - * Copyright (C) 2016 Engicam S.r.l. - */ - -/dts-v1/; - -#include "imx6ul-isiot.dtsi" - -/ { - model = "Engicam Is.IoT MX6UL eMMC Starter kit"; - compatible = "engicam,imx6ul-isiot", "fsl,imx6ul"; -}; - -&usdhc2 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx6ul-isiot-nand.dts b/sys/gnu/dts/arm/imx6ul-isiot-nand.dts deleted file mode 100644 index 8c26d4d1a7b..00000000000 --- a/sys/gnu/dts/arm/imx6ul-isiot-nand.dts +++ /dev/null @@ -1,18 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR X11 -/* - * Copyright (C) 2016 Amarula Solutions B.V. - * Copyright (C) 2016 Engicam S.r.l. - */ - -/dts-v1/; - -#include "imx6ul-isiot.dtsi" - -/ { - model = "Engicam Is.IoT MX6UL NAND Starter kit"; - compatible = "engicam,imx6ul-isiot", "fsl,imx6ul"; -}; - -&gpmi { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx6ul-isiot.dtsi b/sys/gnu/dts/arm/imx6ul-isiot.dtsi deleted file mode 100644 index cc9adce638f..00000000000 --- a/sys/gnu/dts/arm/imx6ul-isiot.dtsi +++ /dev/null @@ -1,386 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR X11 -/* - * Copyright (C) 2016 Amarula Solutions B.V. - * Copyright (C) 2016 Engicam S.r.l. - */ - -#include -#include -#include "imx6ul.dtsi" - -/ { - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000>; - }; - - chosen { - stdout-path = &uart1; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm8 0 100000>; - brightness-levels = < 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100>; - default-brightness-level = <100>; - }; - - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-name = "1P8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "imx6ul-isiot-sgtl5000"; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&dailink_master>; - simple-audio-card,frame-master = <&dailink_master>; - simple-audio-card,widgets = - "Microphone", "Mic Jack", - "Line", "Line In", - "Line", "Line Out", - "Headphone", "Headphone Jack"; - simple-audio-card,routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - - simple-audio-card,cpu { - sound-dai = <&sai2>; - }; - - dailink_master: simple-audio-card,codec { - sound-dai = <&sgtl5000>; - clocks = <&clks IMX6UL_CLK_SAI2>; - }; - }; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet1>; - phy-mode = "rmii"; - phy-handle = <ðphy0>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - }; - }; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - nand-on-flash-bbt; - status = "disabled"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - sgtl5000: codec@a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - #sound-dai-cells = <0>; - clocks = <&clks IMX6UL_CLK_OSC>; - clock-names = "mclk"; - VDDA-supply = <®_3p3v>; - VDDIO-supply = <®_3p3v>; - VDDD-supply = <®_1p8v>; - }; - - stmpe811: gpio-expander@44 { - compatible = "st,stmpe811"; - reg = <0x44>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_stmpe>; - interrupt-parent = <&gpio1>; - interrupts = <18 IRQ_TYPE_EDGE_FALLING>; - interrupt-controller; - #interrupt-cells = <2>; - - stmpe: touchscreen { - compatible = "st,stmpe-ts"; - st,sample-time = <4>; - st,mod-12b = <1>; - st,ref-sel = <0>; - st,adc-freq = <1>; - st,ave-ctrl = <1>; - st,touch-det-delay = <2>; - st,settling = <2>; - st,fraction-z = <7>; - st,i-drive = <1>; - }; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&lcdif { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcdif_dat - &pinctrl_lcdif_ctrl>; - display = <&display0>; - status = "okay"; - - display0: display0 { - bits-per-pixel = <16>; - bus-width = <18>; - - display-timings { - native-mode = <&timing0>; - timing0: timing0 { - clock-frequency = <28000000>; - hactive = <800>; - vactive = <480>; - hfront-porch = <30>; - hback-porch = <30>; - hsync-len = <64>; - vback-porch = <5>; - vfront-porch = <5>; - vsync-len = <20>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - }; - }; -}; - -&pwm8 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm8>; - status = "okay"; -}; - -&sai2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai2>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>; - cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; - bus-width = <4>; - no-1-8-v; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - cd-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>; - bus-width = <8>; - no-1-8-v; - status = "disabled"; -}; - -&iomuxc { - pinctrl_enet1: enet1grp { - fsl,pins = < - MX6UL_PAD_ENET2_RX_DATA0__ENET1_MDIO 0x1b0b0 - MX6UL_PAD_ENET2_RX_DATA1__ENET1_MDC 0x1b0b0 - MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 - MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 - MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 - MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 - MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 - MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 - MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 - MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x1b0b0 - >; - }; - - pinctrl_gpmi_nand: gpminandgrp { - fsl,pins = < - MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1 - MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1 - MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1 - MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000 - MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1 - MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1 - MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1 - MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1 - MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1 - MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1 - MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1 - MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1 - MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1 - MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1 - MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 - MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO00__I2C2_SCL 0x4001b8b0 - MX6UL_PAD_GPIO1_IO01__I2C2_SDA 0x4001b8b0 - >; - }; - - pinctrl_lcdif_ctrl: lcdifctrlgrp { - fsl,pins = < - MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 - MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 - MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 - MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 - >; - }; - - pinctrl_lcdif_dat: lcdifdatgrp { - fsl,pins = < - MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 - MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 - MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 - MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 - MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 - MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 - MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 - MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 - MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 - MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 - MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 - MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 - MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 - MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 - MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 - MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 - MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 - MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 - >; - }; - - pinctrl_pwm8: pwm8grp { - fsl,pins = < - MX6UL_PAD_ENET1_RX_ER__PWM8_OUT 0x110b0 - >; - }; - - pinctrl_sai2: sai2grp { - fsl,pins = < - MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x130b0 - MX6UL_PAD_JTAG_TMS__CCM_CLKO1 0x4001b031 - MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 - MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 - MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x120b0 - >; - }; - - pinctrl_stmpe: stmpegrp { - fsl,pins = < - MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x1b0b0 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 - MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1grp100mhz { - fsl,pins = < - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1grp200mhz { - fsl,pins = < - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17070 - MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x10070 - MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17070 - MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17070 - MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17070 - MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17070 - MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17070 - MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17070 - MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17070 - MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17070 - MX6UL_PAD_NAND_ALE__USDHC2_RESET_B 0x17070 - >; - }; -}; diff --git a/sys/gnu/dts/arm/imx6ul-kontron-n6310-s-43.dts b/sys/gnu/dts/arm/imx6ul-kontron-n6310-s-43.dts deleted file mode 100644 index 5bad29683cc..00000000000 --- a/sys/gnu/dts/arm/imx6ul-kontron-n6310-s-43.dts +++ /dev/null @@ -1,102 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2017 exceet electronics GmbH - * Copyright (C) 2018 Kontron Electronics GmbH - * Copyright (c) 2019 Krzysztof Kozlowski - */ - -#include "imx6ul-kontron-n6310-s.dts" - -/ { - model = "Kontron N6310 S 43"; - compatible = "kontron,imx6ul-n6310-s-43", "kontron,imx6ul-n6310-s", - "kontron,imx6ul-n6310-som", "fsl,imx6ul"; - - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm7 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - status = "okay"; - }; -}; - -&i2c4 { - touchscreen@5d { - compatible = "goodix,gt928"; - reg = <0x5d>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_cap_touch>; - interrupt-parent = <&gpio5>; - interrupts = <6 IRQ_TYPE_LEVEL_LOW>; - reset-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>; - irq-gpios = <&gpio5 6 GPIO_ACTIVE_HIGH>; - }; -}; - -&lcdif { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcdif_dat &pinctrl_lcdif_ctrl>; - /* Leave status disabled because of missing display panel node */ -}; - -&pwm7 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm7>; - status = "okay"; -}; - -&iomuxc { - pinctrl_cap_touch: captouchgrp { - fsl,pins = < - MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x1b0b0 /* Touch Interrupt */ - MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x1b0b0 /* Touch Reset */ - MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x1b0b0 /* Touch Wake */ - >; - }; - - pinctrl_lcdif_ctrl: lcdifctrlgrp { - fsl,pins = < - MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 - MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 - MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 - MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 - MX6UL_PAD_LCD_RESET__LCDIF_RESET 0x79 - >; - }; - - pinctrl_lcdif_dat: lcdifdatgrp { - fsl,pins = < - MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 - MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 - MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 - MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 - MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 - MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 - MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 - MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 - MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 - MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 - MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 - MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 - MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 - MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 - MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 - MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 - MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 - MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 - MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79 - MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79 - MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79 - MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79 - MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79 - MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79 - >; - }; - - pinctrl_pwm7: pwm7grp { - fsl,pins = < - MX6UL_PAD_CSI_VSYNC__PWM7_OUT 0x110b0 - >; - }; -}; diff --git a/sys/gnu/dts/arm/imx6ul-kontron-n6310-s.dts b/sys/gnu/dts/arm/imx6ul-kontron-n6310-s.dts deleted file mode 100644 index 5a3e06d6219..00000000000 --- a/sys/gnu/dts/arm/imx6ul-kontron-n6310-s.dts +++ /dev/null @@ -1,17 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2017 exceet electronics GmbH - * Copyright (C) 2018 Kontron Electronics GmbH - * Copyright (c) 2019 Krzysztof Kozlowski - */ - -/dts-v1/; - -#include "imx6ul-kontron-n6310-som.dtsi" -#include "imx6ul-kontron-n6x1x-s.dtsi" - -/ { - model = "Kontron N6310 S"; - compatible = "kontron,imx6ul-n6310-s", "kontron,imx6ul-n6310-som", - "fsl,imx6ul"; -}; diff --git a/sys/gnu/dts/arm/imx6ul-kontron-n6310-som.dtsi b/sys/gnu/dts/arm/imx6ul-kontron-n6310-som.dtsi deleted file mode 100644 index 47d3ce5d255..00000000000 --- a/sys/gnu/dts/arm/imx6ul-kontron-n6310-som.dtsi +++ /dev/null @@ -1,41 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2017 exceet electronics GmbH - * Copyright (C) 2018 Kontron Electronics GmbH - * Copyright (c) 2019 Krzysztof Kozlowski - */ - -#include "imx6ul.dtsi" -#include "imx6ul-kontron-n6x1x-som-common.dtsi" - -/ { - model = "Kontron N6310 SOM"; - compatible = "kontron,imx6ul-n6310-som", "fsl,imx6ul"; - - memory@80000000 { - reg = <0x80000000 0x10000000>; - device_type = "memory"; - }; -}; - -&qspi { - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "spi-nand"; - spi-max-frequency = <108000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - reg = <0>; - - partition@0 { - label = "ubi1"; - reg = <0x00000000 0x08000000>; - }; - - partition@8000000 { - label = "ubi2"; - reg = <0x08000000 0x08000000>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/imx6ul-kontron-n6311-s.dts b/sys/gnu/dts/arm/imx6ul-kontron-n6311-s.dts deleted file mode 100644 index 239a1af3aea..00000000000 --- a/sys/gnu/dts/arm/imx6ul-kontron-n6311-s.dts +++ /dev/null @@ -1,16 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2017 exceet electronics GmbH - * Copyright (C) 2018 Kontron Electronics GmbH - */ - -/dts-v1/; - -#include "imx6ul-kontron-n6311-som.dtsi" -#include "imx6ul-kontron-n6x1x-s.dtsi" - -/ { - model = "Kontron N6311 S"; - compatible = "kontron,imx6ul-n6311-s", "kontron,imx6ul-n6311-som", - "fsl,imx6ul"; -}; diff --git a/sys/gnu/dts/arm/imx6ul-kontron-n6311-som.dtsi b/sys/gnu/dts/arm/imx6ul-kontron-n6311-som.dtsi deleted file mode 100644 index a095a7654ac..00000000000 --- a/sys/gnu/dts/arm/imx6ul-kontron-n6311-som.dtsi +++ /dev/null @@ -1,40 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2017 exceet electronics GmbH - * Copyright (C) 2018 Kontron Electronics GmbH - */ - -#include "imx6ul.dtsi" -#include "imx6ul-kontron-n6x1x-som-common.dtsi" - -/ { - model = "Kontron N6311 SOM"; - compatible = "kontron,imx6ul-n6311-som", "fsl,imx6ul"; - - memory@80000000 { - reg = <0x80000000 0x20000000>; - device_type = "memory"; - }; -}; - -&qspi { - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "spi-nand"; - spi-max-frequency = <104000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - reg = <0>; - - partition@0 { - label = "ubi1"; - reg = <0x00000000 0x08000000>; - }; - - partition@8000000 { - label = "ubi2"; - reg = <0x08000000 0x18000000>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/imx6ul-kontron-n6x1x-s.dtsi b/sys/gnu/dts/arm/imx6ul-kontron-n6x1x-s.dtsi deleted file mode 100644 index f05e9184120..00000000000 --- a/sys/gnu/dts/arm/imx6ul-kontron-n6x1x-s.dtsi +++ /dev/null @@ -1,418 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2017 exceet electronics GmbH - * Copyright (C) 2018 Kontron Electronics GmbH - * Copyright (c) 2019 Krzysztof Kozlowski - */ - -#include - -/ { - gpio-leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led1 { - label = "debug-led1"; - gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; - default-state = "off"; - linux,default-trigger = "heartbeat"; - }; - - led2 { - label = "debug-led2"; - gpios = <&gpio5 3 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led3 { - label = "debug-led3"; - gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - }; - - pwm-beeper { - compatible = "pwm-beeper"; - pwms = <&pwm8 0 5000>; - }; - - reg_3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_5v: regulator-5v { - compatible = "regulator-fixed"; - regulator-name = "5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_usb_otg1_vbus: regulator-usb-otg1-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_vref_adc: regulator-vref-adc { - compatible = "regulator-fixed"; - regulator-name = "vref-adc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&adc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_adc1>; - num-channels = <3>; - vref-supply = <®_vref_adc>; - status = "okay"; -}; - -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - status = "okay"; -}; - -&ecspi1 { - cs-gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - status = "okay"; - - eeprom@0 { - compatible = "anvo,anv32e61w", "atmel,at25"; - reg = <0>; - spi-max-frequency = <20000000>; - spi-cpha; - spi-cpol; - pagesize = <1>; - size = <8192>; - address-width = <16>; - }; -}; - -&fec1 { - pinctrl-0 = <&pinctrl_enet1>; - /delete-node/ mdio; -}; - -&fec2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_mdio>; - phy-mode = "rmii"; - phy-handle = <ðphy2>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy1: ethernet-phy@1 { - reg = <1>; - micrel,led-mode = <0>; - clocks = <&clks IMX6UL_CLK_ENET_REF>; - clock-names = "rmii-ref"; - }; - - ethphy2: ethernet-phy@2 { - reg = <2>; - micrel,led-mode = <0>; - clocks = <&clks IMX6UL_CLK_ENET2_REF>; - clock-names = "rmii-ref"; - }; - }; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; -}; - -&i2c4 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4>; - status = "okay"; - - rtc@32 { - compatible = "epson,rx8900"; - reg = <0x32>; - }; -}; - -&pwm8 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm8>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - linux,rs485-enabled-at-boot-time; - rs485-rx-during-tx; - rs485-rts-active-low; - uart-has-rtscts; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - fsl,uart-has-rtscts; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -&usbotg1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg1>; - dr_mode = "otg"; - srp-disable; - hnp-disable; - adp-disable; - over-current-active-low; - vbus-supply = <®_usb_otg1_vbus>; - status = "okay"; -}; - -&usbotg2 { - dr_mode = "host"; - disable-over-current; - vbus-supply = <®_5v>; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; - keep-power-in-suspend; - wakeup-source; - vmmc-supply = <®_3v3>; - voltage-ranges = <3300 3300>; - no-1-8-v; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>; - non-removable; - keep-power-in-suspend; - wakeup-source; - vmmc-supply = <®_3v3>; - voltage-ranges = <3300 3300>; - no-1-8-v; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl-0 = <&pinctrl_reset_out &pinctrl_gpio>; - - pinctrl_adc1: adc1grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 - MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 - MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0xb0 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6UL_PAD_CSI_DATA07__ECSPI1_MISO 0x100b1 - MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI 0x100b1 - MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK 0x100b1 - MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x100b1 /* ECSPI1-CS1 */ - >; - }; - - pinctrl_enet2: enet2grp { - fsl,pins = < - MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 - MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 - MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 - MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 - MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 - MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 - MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 - MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b009 - >; - }; - - pinctrl_enet2_mdio: enet2mdiogrp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 - MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 - >; - }; - - pinctrl_flexcan2: flexcan2grp{ - fsl,pins = < - MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 - MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 - >; - }; - - pinctrl_gpio: gpiogrp { - fsl,pins = < - MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0 /* DOUT1 */ - MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x1b0b0 /* DIN1 */ - MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x1b0b0 /* DOUT2 */ - MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 /* DIN2 */ - >; - }; - - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x1b0b0 /* LED H14 */ - MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x1b0b0 /* LED H15 */ - MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 /* LED H16 */ - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x4001b8b0 - MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x4001b8b0 - >; - }; - - pinctrl_i2c4: i2c4grp { - fsl,pins = < - MX6UL_PAD_UART2_TX_DATA__I2C4_SCL 0x4001f8b0 - MX6UL_PAD_UART2_RX_DATA__I2C4_SDA 0x4001f8b0 - >; - }; - - pinctrl_pwm8: pwm8grp { - fsl,pins = < - MX6UL_PAD_CSI_HSYNC__PWM8_OUT 0x110b0 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 - MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6UL_PAD_NAND_DATA04__UART2_DCE_TX 0x1b0b1 - MX6UL_PAD_NAND_DATA05__UART2_DCE_RX 0x1b0b1 - MX6UL_PAD_NAND_DATA06__UART2_DCE_CTS 0x1b0b1 - /* - * mux unused RTS to make sure it doesn't cause - * any interrupts when it is undefined - */ - MX6UL_PAD_NAND_DATA07__UART2_DCE_RTS 0x1b0b1 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1 - MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1 - MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b0b1 - MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b1 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x1b0b1 - MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x1b0b1 - >; - }; - - pinctrl_usbotg1: usbotg1 { - fsl,pins = < - MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x1b0b0 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 - MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x100b1 /* SD1_CD */ - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10059 - MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 - MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 - MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 - MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 - MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = < - MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9 - MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9 - MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9 - MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9 - MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9 - MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = < - MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9 - MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9 - MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9 - MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9 - MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9 - MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO09__WDOG1_WDOG_ANY 0x30b0 - >; - }; -}; diff --git a/sys/gnu/dts/arm/imx6ul-kontron-n6x1x-som-common.dtsi b/sys/gnu/dts/arm/imx6ul-kontron-n6x1x-som-common.dtsi deleted file mode 100644 index a17af4d9bfd..00000000000 --- a/sys/gnu/dts/arm/imx6ul-kontron-n6x1x-som-common.dtsi +++ /dev/null @@ -1,109 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2017 exceet electronics GmbH - * Copyright (C) 2018 Kontron Electronics GmbH - * Copyright (c) 2019 Krzysztof Kozlowski - */ - -#include - -/ { - chosen { - stdout-path = &uart4; - }; -}; - -&ecspi2 { - cs-gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi2>; - status = "okay"; - - spi-flash@0 { - compatible = "mxicy,mx25v8035f", "jedec,spi-nor"; - spi-max-frequency = <50000000>; - reg = <0>; - }; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet1 &pinctrl_enet1_mdio>; - phy-mode = "rmii"; - phy-handle = <ðphy1>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy1: ethernet-phy@1 { - reg = <1>; - micrel,led-mode = <0>; - clocks = <&clks IMX6UL_CLK_ENET_REF>; - clock-names = "rmii-ref"; - }; - }; -}; - -&fec2 { - phy-mode = "rmii"; - status = "disabled"; -}; - -&qspi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_qspi>; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reset_out>; - - pinctrl_ecspi2: ecspi2grp { - fsl,pins = < - MX6UL_PAD_CSI_DATA03__ECSPI2_MISO 0x100b1 - MX6UL_PAD_CSI_DATA02__ECSPI2_MOSI 0x100b1 - MX6UL_PAD_CSI_DATA00__ECSPI2_SCLK 0x100b1 - MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x100b1 - >; - }; - - pinctrl_enet1: enet1grp { - fsl,pins = < - MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 - MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 - MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 - MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 - MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 - MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 - MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 - MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b009 - >; - }; - - pinctrl_enet1_mdio: enet1mdiogrp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 - MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 - >; - }; - - pinctrl_qspi: qspigrp { - fsl,pins = < - MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1 - MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1 - MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1 - MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1 - MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1 - MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 - >; - }; - - pinctrl_reset_out: rstoutgrp { - fsl,pins = < - MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x1b0b0 - >; - }; -}; diff --git a/sys/gnu/dts/arm/imx6ul-liteboard.dts b/sys/gnu/dts/arm/imx6ul-liteboard.dts deleted file mode 100644 index 1d863a16bcf..00000000000 --- a/sys/gnu/dts/arm/imx6ul-liteboard.dts +++ /dev/null @@ -1,151 +0,0 @@ -/* - * Copyright 2016 Grinn - * - * Author: Marcin Niestroj - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include "imx6ul-litesom.dtsi" - -/ { - model = "Grinn i.MX6UL liteBoard"; - compatible = "grinn,imx6ul-liteboard", "grinn,imx6ul-litesom", - "fsl,imx6ul"; - - chosen { - stdout-path = &uart1; - }; - - reg_usb_otg1_vbus: regulator-usb-otg1-vbus { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_otg1_vbus>; - regulator-name = "usb_otg1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio2 8 GPIO_ACTIVE_LOW>; - }; -}; - -&iomuxc { - pinctrl_enet1: enet1grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 - MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 - MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 - MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 - MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 - MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 - MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 - MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 - MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 - MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 - MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10071 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 - >; - }; - - pinctrl_usb_otg1_vbus: usb-otg1-vbus { - fsl,pins = < - MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x79 - >; - }; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet1>; - phy-mode = "rmii"; - phy-handle = <ðphy0>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; - }; -}; - -&snvs_poweroff { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&usbotg1 { - vbus-supply = <®_usb_otg1_vbus>; - dr_mode = "host"; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; - no-1-8-v; - keep-power-in-suspend; - wakeup-source; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx6ul-litesom.dtsi b/sys/gnu/dts/arm/imx6ul-litesom.dtsi deleted file mode 100644 index 8d689321084..00000000000 --- a/sys/gnu/dts/arm/imx6ul-litesom.dtsi +++ /dev/null @@ -1,83 +0,0 @@ -/* - * Copyright 2016 Grinn - * - * Author: Marcin Niestroj - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "imx6ul.dtsi" - -/ { - model = "Grinn i.MX6UL liteSOM"; - compatible = "grinn,imx6ul-litesom", "fsl,imx6ul"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000>; - }; -}; - -&iomuxc { - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069 - MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 - MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 - MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 - MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 - MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 - MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059 - MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059 - MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059 - MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059 - MX6UL_PAD_NAND_ALE__USDHC2_RESET_B 0x17059 - >; - }; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - no-1-8-v; - non-removable; - keep-power-in-suspend; - wakeup-source; - bus-width = <8>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx6ul-opos6ul.dtsi b/sys/gnu/dts/arm/imx6ul-opos6ul.dtsi deleted file mode 100644 index 6ce84f92b02..00000000000 --- a/sys/gnu/dts/arm/imx6ul-opos6ul.dtsi +++ /dev/null @@ -1,6 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT -// -// Copyright 2017 Armadeus Systems - -#include "imx6ul.dtsi" -#include "imx6ul-imx6ull-opos6ul.dtsi" diff --git a/sys/gnu/dts/arm/imx6ul-opos6uldev.dts b/sys/gnu/dts/arm/imx6ul-opos6uldev.dts deleted file mode 100644 index 375b98d7205..00000000000 --- a/sys/gnu/dts/arm/imx6ul-opos6uldev.dts +++ /dev/null @@ -1,41 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT -// -// Copyright 2017 Armadeus Systems - -/dts-v1/; -#include "imx6ul-opos6ul.dtsi" -#include "imx6ul-imx6ull-opos6uldev.dtsi" - -/ { - model = "Armadeus Systems OPOS6UL SoM (i.MX6UL) on OPOS6ULDev board"; - compatible = "armadeus,imx6ul-opos6uldev", "armadeus,imx6ul-opos6ul", "fsl,imx6ul"; -}; - -&iomuxc { - pinctrl-0 = <&pinctrl_gpios>, <&pinctrl_tamper_gpios>; - - pinctrl_tamper_gpios: tampergpiosgrp { - fsl,pins = < - MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x0b0b0 - MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0b0b0 - MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0b0b0 - MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x0b0b0 - MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0b0b0 - MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0b0b0 - MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0b0b0 - MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x0b0b0 - >; - }; - - pinctrl_usbotg2_vbus: usbotg2vbusgrp { - fsl,pins = < - MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x1b0b0 - >; - }; - - pinctrl_w1: w1grp { - fsl,pins = < - MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x0b0b0 - >; - }; -}; diff --git a/sys/gnu/dts/arm/imx6ul-phytec-phycore-som.dtsi b/sys/gnu/dts/arm/imx6ul-phytec-phycore-som.dtsi deleted file mode 100644 index 88f631c8fab..00000000000 --- a/sys/gnu/dts/arm/imx6ul-phytec-phycore-som.dtsi +++ /dev/null @@ -1,171 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2016 PHYTEC Messtechnik GmbH - * Author: Christian Hemp - */ - -#include -#include -#include - -/ { - model = "PHYTEC phyCORE-i.MX6 UltraLite"; - compatible = "phytec,imx6ul-pcl063", "fsl,imx6ul"; - - chosen { - stdout-path = &uart1; - }; - - /* - * Set the minimum memory size here and - * let the bootloader set the real size. - */ - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x8000000>; - }; - - gpio_leds_som: leds { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpioleds_som>; - compatible = "gpio-leds"; - - phycore-green { - gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet1>; - phy-mode = "rmii"; - phy-handle = <ðphy1>; - status = "disabled"; - - mdio: mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy1: ethernet-phy@1 { - reg = <1>; - interrupt-parent = <&gpio1>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - micrel,led-mode = <1>; - clocks = <&clks IMX6UL_CLK_ENET_REF>; - clock-names = "rmii-ref"; - status = "disabled"; - }; - }; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - nand-on-flash-bbt; - status = "disabled"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - clock-frequency = <100000>; - status = "okay"; - - eeprom@52 { - compatible = "catalyst,24c32", "atmel,24c32"; - reg = <0x52>; - }; -}; - -&snvs_poweroff { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - bus-width = <8>; - no-1-8-v; - non-removable; - status = "disabled"; -}; - -&iomuxc { - pinctrl_enet1: enet1grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x10010 - MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x10010 - MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 - MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 - MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 - MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 - MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b010 - MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b010 - MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b010 - MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b010 - MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x17059 - >; - }; - - pinctrl_gpioleds_som: gpioledssomgrp { - fsl,pins = ; - }; - - pinctrl_gpmi_nand: gpminandgrp { - fsl,pins = < - MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x0b0b1 - MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x0b0b1 - MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x0b0b1 - MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000 - MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0b0b1 - MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0b0b1 - MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x0b0b1 - MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0b0b1 - MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0b0b1 - MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0b0b1 - MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x0b0b1 - MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0b0b1 - MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0b0b1 - MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0b0b1 - MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x0b0b1 - >; - }; - - pinctrl_i2c1: i2cgrp { - fsl,pins = < - MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 - MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 - MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9 - MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9 - MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9 - MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9 - MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9 - MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9 - MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9 - MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9 - MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9 - MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9 - >; - }; - -}; diff --git a/sys/gnu/dts/arm/imx6ul-phytec-segin-ff-rdk-nand.dts b/sys/gnu/dts/arm/imx6ul-phytec-segin-ff-rdk-nand.dts deleted file mode 100644 index 699dfcbf9a6..00000000000 --- a/sys/gnu/dts/arm/imx6ul-phytec-segin-ff-rdk-nand.dts +++ /dev/null @@ -1,93 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2016 PHYTEC Messtechnik GmbH - * Author: Christian Hemp - */ - -/dts-v1/; -#include "imx6ul.dtsi" -#include "imx6ul-phytec-phycore-som.dtsi" -#include "imx6ul-phytec-segin.dtsi" -#include "imx6ul-phytec-segin-peb-eval-01.dtsi" - -/ { - model = "PHYTEC phyBOARD-Segin i.MX6 UltraLite Full Featured with NAND"; - compatible = "phytec,imx6ul-pbacd10-nand", "phytec,imx6ul-pbacd10", - "phytec,imx6ul-pcl063", "fsl,imx6ul"; -}; - -&adc1 { - status = "okay"; -}; - -&can1 { - status = "okay"; -}; - -&tlv320 { - status = "okay"; -}; - -&ecspi3 { - status = "okay"; -}; - -ðphy1 { - status = "okay"; -}; - -ðphy2 { - status = "okay"; -}; - -&fec1 { - status = "okay"; -}; - -&fec2 { - status = "okay"; -}; - -&gpmi { - status = "okay"; -}; - -&i2c_rtc { - status = "okay"; -}; - -®_can1_en { - status = "okay"; -}; - -®_sound_1v8 { - status = "okay"; -}; - -®_sound_3v3 { - status = "okay"; -}; - -&sai2 { - status = "okay"; -}; - -&sound { - status = "okay"; -}; - -&uart5 { - status = "okay"; -}; - -&usbotg1 { - status = "okay"; -}; - -&usbotg2 { - status = "okay"; -}; - -&usdhc1 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx6ul-phytec-segin-peb-eval-01.dtsi b/sys/gnu/dts/arm/imx6ul-phytec-segin-peb-eval-01.dtsi deleted file mode 100644 index 2f3fd32a116..00000000000 --- a/sys/gnu/dts/arm/imx6ul-phytec-segin-peb-eval-01.dtsi +++ /dev/null @@ -1,57 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2016 PHYTEC Messtechnik - * Author: Christian Hemp - */ - -#include - -/ { - gpio_keys: gpio-keys { - compatible = "gpio-key"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_keys>; - status = "disabled"; - - power { - label = "Power Button"; - gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - }; - - user_leds: user-leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_user_leds>; - status = "disabled"; - - user-led1 { - gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "gpio"; - default-state = "on"; - }; - - user-led2 { - gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "gpio"; - default-state = "on"; - }; - }; -}; - -&iomuxc { - pinctrl_gpio_keys: gpio_keysgrp { - fsl,pins = < - MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x79 - >; - }; - - pinctrl_user_leds: user_ledsgrp { - fsl,pins = < - MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x79 - MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0x79 - >; - }; -}; diff --git a/sys/gnu/dts/arm/imx6ul-phytec-segin.dtsi b/sys/gnu/dts/arm/imx6ul-phytec-segin.dtsi deleted file mode 100644 index 8d5f8dc6ad5..00000000000 --- a/sys/gnu/dts/arm/imx6ul-phytec-segin.dtsi +++ /dev/null @@ -1,346 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2016 PHYTEC Messtechnik GmbH - * Author: Christian Hemp - */ - -/ { - model = "PHYTEC phyBOARD-Segin i.MX6 UltraLite"; - compatible = "phytec,imx6ul-pbacd-10", "phytec,imx6ul-pcl063", "fsl,imx6ul"; - - aliases { - rtc0 = &i2c_rtc; - rtc1 = &snvs_rtc; - }; - - reg_sound_1v8: regulator-1v8 { - compatible = "regulator-fixed"; - regulator-name = "i2s-audio-1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - status = "disabled"; - }; - - reg_sound_3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "i2s-audio-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - status = "disabled"; - }; - - reg_can1_en: regulator-can1 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&princtrl_flexcan1_en>; - regulator-name = "Can"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; - enable-active-high; - status = "disabled"; - }; - - reg_adc1_vref_3v3: regulator-vref-3v3 { - compatible = "regulator-fixed"; - regulator-name = "vref-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - sound: sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "phyBOARD-Segin-TLV320AIC3007"; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&dailink_master>; - simple-audio-card,frame-master = <&dailink_master>; - simple-audio-card,widgets = - "Line", "Line In", - "Line", "Line Out", - "Speaker", "Speaker"; - simple-audio-card,routing = - "Line Out", "LLOUT", - "Line Out", "RLOUT", - "Speaker", "SPOP", - "Speaker", "SPOM", - "LINE1L", "Line In", - "LINE1R", "Line In"; - status = "disabled"; - - simple-audio-card,cpu { - sound-dai = <&sai2>; - }; - - dailink_master: simple-audio-card,codec { - sound-dai = <&tlv320>; - clocks = <&clks IMX6UL_CLK_SAI2>; - }; - }; - -}; - -&adc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_adc1>; - vref-supply = <®_adc1_vref_3v3>; - /* - * driver can not separate a specific channel so we request 4 channels - * here - we need only the fourth channel - */ - num-channels = <4>; - status = "disabled"; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - xceiver-supply = <®_can1_en>; - status = "disabled"; -}; - -&clks { - assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; - assigned-clock-rates = <786432000>; -}; - -&ecspi3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi3>; - cs-gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>; - status = "disabled"; -}; - -&fec2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet2>; - phy-mode = "rmii"; - phy-handle = <ðphy2>; - status = "disabled"; -}; - -&i2c1 { - tlv320: codec@18 { - compatible = "ti,tlv320aic3007"; - #sound-dai-cells = <0>; - reg = <0x18>; - AVDD-supply = <®_sound_3v3>; - IOVDD-supply = <®_sound_3v3>; - DRVDD-supply = <®_sound_3v3>; - DVDD-supply = <®_sound_1v8>; - status = "disabled"; - }; - - stmpe: touchscreen@44 { - compatible = "st,stmpe811"; - reg = <0x44>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - interrupt-parent = <&gpio5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_stmpe>; - status = "disabled"; - - touchscreen { - compatible = "st,stmpe-ts"; - st,sample-time = <4>; - st,mod-12b = <1>; - st,ref-sel = <0>; - st,adc-freq = <1>; - st,ave-ctrl = <1>; - st,touch-det-delay = <2>; - st,settling = <2>; - st,fraction-z = <7>; - st,i-drive = <1>; - touchscreen-inverted-x = <1>; - touchscreen-inverted-y = <1>; - }; - }; - - i2c_rtc: rtc@68 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rtc_int>; - compatible = "microcrystal,rv4162"; - reg = <0x68>; - interrupt-parent = <&gpio5>; - interrupts = <1 IRQ_TYPE_LEVEL_LOW>; - status = "disabled"; - }; -}; - -&mdio { - ethphy2: ethernet-phy@2 { - reg = <2>; - micrel,led-mode = <1>; - clocks = <&clks IMX6UL_CLK_ENET2_REF>; - clock-names = "rmii-ref"; - status = "disabled"; - }; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; - status = "disabled"; -}; - -&sai2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai2>; - assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>, - <&clks IMX6UL_CLK_SAI2>; - assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; - assigned-clock-rates = <0>, <19200000>; - fsl,sai-mclk-direction-output; - status = "disabled"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - uart-has-rtscts; - status = "disabled"; -}; - -&usbotg1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_otg1_id>; - dr_mode = "otg"; - status = "disabled"; -}; - -&usbotg2 { - dr_mode = "host"; - disable-over-current; - status = "disabled"; -}; - -&usdhc1 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>; - cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; - no-1-8-v; - keep-power-in-suspend; - wakeup-source; - status = "disabled"; -}; - -&iomuxc { - pinctrl_adc1: adc1grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 - >; - }; - - pinctrl_ecspi3: ecspi3grp { - fsl,pins = < - MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO 0x10b0 - MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI 0x10b0 - MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK 0x10b0 - MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x10b0 - >; - }; - - pinctrl_enet2: enet2grp { - fsl,pins = < - MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 - MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 - MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 - MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 - MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b010 - MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b010 - MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b010 - MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b010 - >; - }; - - pinctrl_flexcan1: flexcan1 { - fsl,pins = < - MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x0b0b0 - MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x0b0b0 - >; - }; - - princtrl_flexcan1_en: flexcan1engrp { - fsl,pins = < - MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x17059 - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO04__PWM3_OUT 0x0b0b0 - >; - }; - - pinctrl_rtc_int: rtcintgrp { - fsl,pins = < - MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x17059 - >; - }; - - pinctrl_sai2: sai2grp { - fsl,pins = < - MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 - MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 - MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088 - MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088 - MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088 - >; - }; - - pinctrl_stmpe: stmpegrp { - fsl,pins = < - MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x17059 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x1b0b1 - MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x1b0b1 - MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x1b0b1 - MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x1b0b1 - >; - }; - - pinctrl_usb_otg1_id: usbotg1idgrp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 - MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1grp100mhz { - fsl,pins = < - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1grp200mhz { - fsl,pins = < - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 - >; - }; -}; diff --git a/sys/gnu/dts/arm/imx6ul-pico-hobbit.dts b/sys/gnu/dts/arm/imx6ul-pico-hobbit.dts deleted file mode 100644 index 09f7ffa9ad8..00000000000 --- a/sys/gnu/dts/arm/imx6ul-pico-hobbit.dts +++ /dev/null @@ -1,100 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -// -// Copyright 2015 Technexion Ltd. -// -// Author: Wig Cheng -// Richard Hu -// Tapani Utriainen -/dts-v1/; - -#include "imx6ul-pico.dtsi" -/ { - model = "TechNexion PICO-IMX6UL and HOBBIT baseboard"; - compatible = "technexion,imx6ul-pico-hobbit", "fsl,imx6ul"; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led { - label = "gpio-led"; - gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; - }; - }; - - sound { - compatible = "fsl,imx-audio-sgtl5000"; - model = "imx6ul-sgtl5000"; - audio-cpu = <&sai1>; - audio-codec = <&sgtl5000>; - audio-routing = - "LINE_IN", "Line In Jack", - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - }; - - sys_mclk: clock-sys-mclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24576000>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - sgtl5000: codec@a { - reg = <0x0a>; - compatible = "fsl,sgtl5000"; - clocks = <&sys_mclk>; - VDDA-supply = <®_2p5v>; - VDDIO-supply = <®_3p3v>; - }; -}; - -&i2c3 { - status = "okay"; - - polytouch: touchscreen@38 { - compatible = "edt,edt-ft5x06"; - reg = <0x38>; - interrupt-parent = <&gpio1>; - interrupts = <29 IRQ_TYPE_EDGE_FALLING>; - reset-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; - touchscreen-size-x = <800>; - touchscreen-size-y = <480>; - }; - - adc081c: adc@50 { - compatible = "ti,adc081c"; - reg = <0x50>; - vref-supply = <®_3p3v>; - }; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_hog: hoggrp { - fsl,pins = < - MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x10b0 - MX6UL_PAD_CSI_DATA00__GPIO4_IO21 0x10b0 - MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x10b0 - MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x10b0 - MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x10b0 - MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x10b0 - >; - }; - - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x10b0 - >; - }; -}; diff --git a/sys/gnu/dts/arm/imx6ul-pico-pi.dts b/sys/gnu/dts/arm/imx6ul-pico-pi.dts deleted file mode 100644 index 6cd7d5877d2..00000000000 --- a/sys/gnu/dts/arm/imx6ul-pico-pi.dts +++ /dev/null @@ -1,97 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -// -// Copyright 2015 Technexion Ltd. -// -// Author: Wig Cheng -// Richard Hu -// Tapani Utriainen -/dts-v1/; - -#include "imx6ul-pico.dtsi" -/ { - model = "TechNexion PICO-IMX6UL and PI baseboard"; - compatible = "technexion,imx6ul-pico-pi", "fsl,imx6ul"; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led { - label = "gpio-led"; - gpios = <&gpio4 20 GPIO_ACTIVE_HIGH>; - }; - }; - - sound { - compatible = "fsl,imx-audio-sgtl5000"; - model = "imx6ul-sgtl5000"; - audio-cpu = <&sai1>; - audio-codec = <&sgtl5000>; - audio-routing = - "LINE_IN", "Line In Jack", - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - }; - - sys_mclk: clock-sys-mclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24576000>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - sgtl5000: codec@a { - reg = <0x0a>; - compatible = "fsl,sgtl5000"; - clocks = <&sys_mclk>; - VDDA-supply = <®_2p5v>; - VDDIO-supply = <®_3p3v>; - }; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - polytouch: touchscreen@38 { - compatible = "edt,edt-ft5x06"; - reg = <0x38>; - interrupt-parent = <&gpio1>; - interrupts = <29 IRQ_TYPE_EDGE_FALLING>; - reset-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; - touchscreen-size-x = <800>; - touchscreen-size-y = <480>; - }; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_hog: hoggrp { - fsl,pins = < - MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x10b0 - MX6UL_PAD_CSI_DATA00__GPIO4_IO21 0x10b0 - MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x10b0 - MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x10b0 - MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x10b0 - MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x10b0 - >; - }; - - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - MX6UL_PAD_CSI_HSYNC__GPIO4_IO20 0x10b0 - >; - }; -}; diff --git a/sys/gnu/dts/arm/imx6ul-pico.dtsi b/sys/gnu/dts/arm/imx6ul-pico.dtsi deleted file mode 100644 index de9f83189ba..00000000000 --- a/sys/gnu/dts/arm/imx6ul-pico.dtsi +++ /dev/null @@ -1,461 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -// -// Copyright 2015 Technexion Ltd. -// -// Author: Wig Cheng -// Richard Hu -// Tapani Utriainen -/dts-v1/; - -#include "imx6ul.dtsi" - -/ { - /* Will be filled by the bootloader */ - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0>; - }; - - chosen { - stdout-path = &uart6; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm3 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - status = "okay"; - }; - - reg_2p5v: regulator-2p5v { - compatible = "regulator-fixed"; - regulator-name = "2P5V"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_sd1_vmmc: regulator-sd1-vmmc { - compatible = "regulator-fixed"; - regulator-name = "VSD_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usb_otg_vbus: regulator-usb-otg-vbus { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_otg1>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 6 0>; - }; - - reg_brcm: regulator-brcm { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio4 8 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_brcm_reg>; - regulator-name = "brcm_reg"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <200000>; - }; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - status = "okay"; -}; - -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - status = "okay"; -}; - -&clks { - assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; - assigned-clock-rates = <786432000>; -}; - -&fec2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet2>; - phy-mode = "rmii"; - phy-handle = <ðphy1>; - status = "okay"; - phy-reset-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>; - phy-reset-duration = <1>; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy1: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - max-speed = <100>; - interrupt-parent = <&gpio5>; - interrupts = <6 IRQ_TYPE_LEVEL_LOW>; - }; - }; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pmic: pfuze3000@8 { - compatible = "fsl,pfuze3000"; - reg = <0x08>; - - regulators { - /* VDD_ARM_SOC_IN*/ - sw1b_reg: sw1b { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1475000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - /* DRAM */ - sw3a_reg: sw3 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1650000>; - regulator-boot-on; - regulator-always-on; - }; - - /* DRAM */ - vref_reg: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - }; - }; -}; - -&lcdif { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcdif_dat &pinctrl_lcdif_ctrl>; - display = <&display0>; - status = "okay"; - - display0: display0 { - bits-per-pixel = <32>; - bus-width = <24>; - - display-timings { - native-mode = <&timing0>; - - timing0: timing0 { - clock-frequency = <33200000>; - hactive = <800>; - vactive = <480>; - hfront-porch = <210>; - hback-porch = <46>; - hsync-len = <1>; - vback-porch = <22>; - vfront-porch = <23>; - vsync-len = <1>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - }; - }; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; - status = "okay"; -}; - -&pwm7 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm7>; - status = "okay"; -}; - -&pwm8 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm8>; - status = "okay"; -}; - -&sai1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai1>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - uart-has-rtscts; - status = "okay"; -}; - -&uart6 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart6>; - status = "okay"; -}; - -&usbotg1 { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_otg1_id>; - dr_mode = "otg"; - disable-over-current; - status = "okay"; -}; - -&usbotg2 { - dr_mode = "host"; - disable-over-current; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - bus-width = <8>; - no-1-8-v; - non-removable; - keep-power-in-suspend; - status = "okay"; -}; - -&usdhc2 { /* Wifi SDIO */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - no-1-8-v; - non-removable; - keep-power-in-suspend; - wakeup-source; - vmmc-supply = <®_brcm>; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; -}; - -&iomuxc { - pinctrl_brcm_reg: brcmreggrp { - fsl,pins = < - MX6UL_PAD_NAND_DATA06__GPIO4_IO08 0x10b0 /* WL_REG_ON */ - MX6UL_PAD_NAND_DATA04__GPIO4_IO06 0x10b0 /* WL_HOST_WAKE */ - >; - }; - - pinctrl_enet2: enet2grp { - fsl,pins = < - MX6UL_PAD_ENET1_TX_DATA1__ENET2_MDIO 0x1b0b0 - MX6UL_PAD_ENET1_TX_EN__ENET2_MDC 0x1b0b0 - MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 - MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 - MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 - MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 - MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 - MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 - MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 - MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 - MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x800 - MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x79 - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX 0x1b020 - MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX 0x1b020 - >; - }; - - pinctrl_flexcan2: flexcan2grp { - fsl,pins = < - MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX 0x1b020 - MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX 0x1b020 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO02__I2C1_SCL 0x4001b8b0 - MX6UL_PAD_GPIO1_IO03__I2C1_SDA 0x4001b8b0 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 - MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6UL_PAD_UART1_TX_DATA__I2C3_SCL 0x4001b8b0 - MX6UL_PAD_UART1_RX_DATA__I2C3_SDA 0x4001b8b0 - >; - }; - - pinctrl_lcdif_dat: lcdifdatgrp { - fsl,pins = < - MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 - MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 - MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 - MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 - MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 - MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 - MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 - MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 - MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 - MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 - MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 - MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 - MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 - MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 - MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 - MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 - MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 - MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 - MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79 - MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79 - MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79 - MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79 - MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79 - MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79 - >; - }; - - pinctrl_lcdif_ctrl: lcdifctrlgrp { - fsl,pins = < - MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 - MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 - MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 - MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 - /* LCD reset */ - MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79 - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6UL_PAD_NAND_ALE__PWM3_OUT 0x110b0 - >; - }; - - pinctrl_pwm7: pwm7grp { - fsl,pins = < - MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT 0x110b0 - >; - }; - - pinctrl_pwm8: pwm8grp { - fsl,pins = < - MX6UL_PAD_ENET1_RX_ER__PWM8_OUT 0x110b0 - >; - }; - - pinctrl_sai1: sai1grp { - fsl,pins = < - MX6UL_PAD_CSI_DATA04__SAI1_TX_SYNC 0x1b0b0 - MX6UL_PAD_CSI_DATA05__SAI1_TX_BCLK 0x1b0b0 - MX6UL_PAD_CSI_DATA06__SAI1_RX_DATA 0x110b0 - MX6UL_PAD_CSI_DATA07__SAI1_TX_DATA 0x1f0b8 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b0 - MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b0 - MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b0 - MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b0b0 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO04__UART5_DCE_TX 0x1b0b1 - MX6UL_PAD_GPIO1_IO05__UART5_DCE_RX 0x1b0b1 - MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x1b0b1 - MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x1b0b1 - >; - }; - - pinctrl_uart6: uart6grp { - fsl,pins = < - MX6UL_PAD_CSI_MCLK__UART6_DCE_TX 0x1b0b1 - MX6UL_PAD_CSI_PIXCLK__UART6_DCE_RX 0x1b0b1 - >; - }; - - pinctrl_usb_otg1: usbotg1grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO06__GPIO1_IO06 0x10b0 - >; - }; - - pinctrl_usb_otg1_id: usbotg1idgrp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10071 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 - MX6UL_PAD_UART1_RTS_B__USDHC1_CD_B 0x03029 - MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x17059 - MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x17059 - MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x17059 - MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x17059 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 - MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10059 - MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 - MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 - MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 - MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0 - >; - }; -}; diff --git a/sys/gnu/dts/arm/imx6ul-pinfunc.h b/sys/gnu/dts/arm/imx6ul-pinfunc.h deleted file mode 100644 index 380d2db13a9..00000000000 --- a/sys/gnu/dts/arm/imx6ul-pinfunc.h +++ /dev/null @@ -1,959 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2014 - 2015 Freescale Semiconductor, Inc. - */ - -#ifndef __DTS_IMX6UL_PINFUNC_H -#define __DTS_IMX6UL_PINFUNC_H - -/* - * The pin function ID is a tuple of - * - */ -#define MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x0014 0x02a0 0x0000 5 0 -#define MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x0018 0x02a4 0x0000 5 0 - -#define MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x001c 0x02a8 0x0000 5 0 -#define MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x0020 0x02ac 0x0000 5 0 -#define MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0024 0x02b0 0x0000 5 0 -#define MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0028 0x02b4 0x0000 5 0 -#define MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x002c 0x02b8 0x0000 5 0 -#define MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0030 0x02bc 0x0000 5 0 -#define MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0034 0x02c0 0x0000 5 0 -#define MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0038 0x02c4 0x0000 5 0 -#define MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x003c 0x02c8 0x0000 5 0 -#define MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x0040 0x02cc 0x0000 5 0 - -#define MX6UL_PAD_JTAG_MOD__SJC_MOD 0x0044 0x02d0 0x0000 0 0 -#define MX6UL_PAD_JTAG_MOD__GPT2_CLK 0x0044 0x02d0 0x05a0 1 0 -#define MX6UL_PAD_JTAG_MOD__SPDIF_OUT 0x0044 0x02d0 0x0000 2 0 -#define MX6UL_PAD_JTAG_MOD__ENET1_REF_CLK_25M 0x0044 0x02d0 0x0000 3 0 -#define MX6UL_PAD_JTAG_MOD__CCM_PMIC_RDY 0x0044 0x02d0 0x04c0 4 0 -#define MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x0044 0x02d0 0x0000 5 0 -#define MX6UL_PAD_JTAG_MOD__SDMA_EXT_EVENT00 0x0044 0x02d0 0x0610 6 0 -#define MX6UL_PAD_JTAG_TMS__SJC_TMS 0x0048 0x02d4 0x0000 0 0 -#define MX6UL_PAD_JTAG_TMS__GPT2_CAPTURE1 0x0048 0x02d4 0x0598 1 0 -#define MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x0048 0x02d4 0x05f0 2 0 -#define MX6UL_PAD_JTAG_TMS__CCM_CLKO1 0x0048 0x02d4 0x0000 3 0 -#define MX6UL_PAD_JTAG_TMS__CCM_WAIT 0x0048 0x02d4 0x0000 4 0 -#define MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x0048 0x02d4 0x0000 5 0 -#define MX6UL_PAD_JTAG_TMS__SDMA_EXT_EVENT01 0x0048 0x02d4 0x0614 6 0 -#define MX6UL_PAD_JTAG_TMS__EPIT1_OUT 0x0048 0x02d4 0x0000 8 0 -#define MX6UL_PAD_JTAG_TDO__SJC_TDO 0x004c 0x02d8 0x0000 0 0 -#define MX6UL_PAD_JTAG_TDO__GPT2_CAPTURE2 0x004c 0x02d8 0x059c 1 0 -#define MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x004c 0x02d8 0x05fc 2 0 -#define MX6UL_PAD_JTAG_TDO__CCM_CLKO2 0x004c 0x02d8 0x0000 3 0 -#define MX6UL_PAD_JTAG_TDO__CCM_STOP 0x004c 0x02d8 0x0000 4 0 -#define MX6UL_PAD_JTAG_TDO__GPIO1_IO12 0x004c 0x02d8 0x0000 5 0 -#define MX6UL_PAD_JTAG_TDO__MQS_RIGHT 0x004c 0x02d8 0x0000 6 0 -#define MX6UL_PAD_JTAG_TDO__EPIT2_OUT 0x004c 0x02d8 0x0000 8 0 -#define MX6UL_PAD_JTAG_TDI__SJC_TDI 0x0050 0x02dc 0x0000 0 0 -#define MX6UL_PAD_JTAG_TDI__GPT2_COMPARE1 0x0050 0x02dc 0x0000 1 0 -#define MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x0050 0x02dc 0x05f8 2 0 -#define MX6UL_PAD_JTAG_TDI__PWM6_OUT 0x0050 0x02dc 0x0000 4 0 -#define MX6UL_PAD_JTAG_TDI__GPIO1_IO13 0x0050 0x02dc 0x0000 5 0 -#define MX6UL_PAD_JTAG_TDI__MQS_LEFT 0x0050 0x02dc 0x0000 6 0 -#define MX6UL_PAD_JTAG_TDI__SIM1_POWER_FAIL 0x0050 0x02dc 0x0000 8 0 -#define MX6UL_PAD_JTAG_TCK__SJC_TCK 0x0054 0x02e0 0x0000 0 0 -#define MX6UL_PAD_JTAG_TCK__GPT2_COMPARE2 0x0054 0x02e0 0x0000 1 0 -#define MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x0054 0x02e0 0x05f4 2 0 -#define MX6UL_PAD_JTAG_TCK__PWM7_OUT 0x0054 0x02e0 0x0000 4 0 -#define MX6UL_PAD_JTAG_TCK__GPIO1_IO14 0x0054 0x02e0 0x0000 5 0 -#define MX6UL_PAD_JTAG_TCK__OSC32K_32K_OUT 0x0054 0x02e0 0x0000 6 0 -#define MX6UL_PAD_JTAG_TCK__SIM2_POWER_FAIL 0x0054 0x02e0 0x0000 8 0 -#define MX6UL_PAD_JTAG_TRST_B__SJC_TRSTB 0x0058 0x02e4 0x0000 0 0 -#define MX6UL_PAD_JTAG_TRST_B__GPT2_COMPARE3 0x0058 0x02e4 0x0000 1 0 -#define MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x0058 0x02e4 0x0000 2 0 -#define MX6UL_PAD_JTAG_TRST_B__PWM8_OUT 0x0058 0x02e4 0x0000 4 0 -#define MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15 0x0058 0x02e4 0x0000 5 0 -#define MX6UL_PAD_JTAG_TRST_B__REF_CLK_24M 0x0058 0x02e4 0x0000 6 0 -#define MX6UL_PAD_JTAG_TRST_B__CAAM_RNG_OSC_OBS 0x0058 0x02e4 0x0000 8 0 -#define MX6UL_PAD_GPIO1_IO00__I2C2_SCL 0x005c 0x02e8 0x05ac 0 1 -#define MX6UL_PAD_GPIO1_IO00__GPT1_CAPTURE1 0x005c 0x02e8 0x058c 1 0 -#define MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x005c 0x02e8 0x04b8 2 0 -#define MX6UL_PAD_GPIO1_IO00__ENET1_REF_CLK1 0x005c 0x02e8 0x0574 3 0 -#define MX6UL_PAD_GPIO1_IO00__MQS_RIGHT 0x005c 0x02e8 0x0000 4 0 -#define MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0x005c 0x02e8 0x0000 5 0 -#define MX6UL_PAD_GPIO1_IO00__ENET1_1588_EVENT0_IN 0x005c 0x02e8 0x0000 6 0 -#define MX6UL_PAD_GPIO1_IO00__SRC_SYSTEM_RESET 0x005c 0x02e8 0x0000 7 0 -#define MX6UL_PAD_GPIO1_IO00__WDOG3_WDOG_B 0x005c 0x02e8 0x0000 8 0 -#define MX6UL_PAD_GPIO1_IO01__I2C2_SDA 0x0060 0x02ec 0x05b0 0 1 -#define MX6UL_PAD_GPIO1_IO01__GPT1_COMPARE1 0x0060 0x02ec 0x0000 1 0 -#define MX6UL_PAD_GPIO1_IO01__USB_OTG1_OC 0x0060 0x02ec 0x0664 2 0 -#define MX6UL_PAD_GPIO1_IO01__ENET2_REF_CLK2 0x0060 0x02ec 0x057c 3 0 -#define MX6UL_PAD_GPIO1_IO01__MQS_LEFT 0x0060 0x02ec 0x0000 4 0 -#define MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0x0060 0x02ec 0x0000 5 0 -#define MX6UL_PAD_GPIO1_IO01__ENET1_1588_EVENT0_OUT 0x0060 0x02ec 0x0000 6 0 -#define MX6UL_PAD_GPIO1_IO01__SRC_EARLY_RESET 0x0060 0x02ec 0x0000 7 0 -#define MX6UL_PAD_GPIO1_IO01__WDOG1_WDOG_B 0x0060 0x02ec 0x0000 8 0 -#define MX6UL_PAD_GPIO1_IO02__I2C1_SCL 0x0064 0x02f0 0x05a4 0 0 -#define MX6UL_PAD_GPIO1_IO02__GPT1_COMPARE2 0x0064 0x02f0 0x0000 1 0 -#define MX6UL_PAD_GPIO1_IO02__USB_OTG2_PWR 0x0064 0x02f0 0x0000 2 0 -#define MX6UL_PAD_GPIO1_IO02__ENET1_REF_CLK_25M 0x0064 0x02f0 0x0000 3 0 -#define MX6UL_PAD_GPIO1_IO02__USDHC1_WP 0x0064 0x02f0 0x066c 4 0 -#define MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x0064 0x02f0 0x0000 5 0 -#define MX6UL_PAD_GPIO1_IO02__SDMA_EXT_EVENT00 0x0064 0x02f0 0x0610 6 1 -#define MX6UL_PAD_GPIO1_IO02__SRC_ANY_PU_RESET 0x0064 0x02f0 0x0000 7 0 -#define MX6UL_PAD_GPIO1_IO02__UART1_DCE_TX 0x0064 0x02f0 0x0000 8 0 -#define MX6UL_PAD_GPIO1_IO02__UART1_DTE_RX 0x0064 0x02f0 0x0624 8 0 -#define MX6UL_PAD_GPIO1_IO03__I2C1_SDA 0x0068 0x02f4 0x05a8 0 1 -#define MX6UL_PAD_GPIO1_IO03__GPT1_COMPARE3 0x0068 0x02f4 0x0000 1 0 -#define MX6UL_PAD_GPIO1_IO03__USB_OTG2_OC 0x0068 0x02f4 0x0660 2 0 -#define MX6UL_PAD_GPIO1_IO03__OSC32K_32K_OUT 0x0068 0x02f4 0x0000 3 0 -#define MX6UL_PAD_GPIO1_IO03__USDHC1_CD_B 0x0068 0x02f4 0x0668 4 0 -#define MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x0068 0x02f4 0x0000 5 0 -#define MX6UL_PAD_GPIO1_IO03__CCM_DI0_EXT_CLK 0x0068 0x02f4 0x0000 6 0 -#define MX6UL_PAD_GPIO1_IO03__SRC_TESTER_ACK 0x0068 0x02f4 0x0000 7 0 -#define MX6UL_PAD_GPIO1_IO03__UART1_DCE_RX 0x0068 0x02f4 0x0624 8 1 -#define MX6UL_PAD_GPIO1_IO03__UART1_DTE_TX 0x0068 0x02f4 0x0000 8 0 -#define MX6UL_PAD_GPIO1_IO04__ENET1_REF_CLK1 0x006c 0x02f8 0x0574 0 1 -#define MX6UL_PAD_GPIO1_IO04__PWM3_OUT 0x006c 0x02f8 0x0000 1 0 -#define MX6UL_PAD_GPIO1_IO04__USB_OTG1_PWR 0x006c 0x02f8 0x0000 2 0 -#define MX6UL_PAD_GPIO1_IO04__REF_CLK_24M 0x006c 0x02f8 0x0000 3 0 -#define MX6UL_PAD_GPIO1_IO04__USDHC1_RESET_B 0x006c 0x02f8 0x0000 4 0 -#define MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x006c 0x02f8 0x0000 5 0 -#define MX6UL_PAD_GPIO1_IO04__ENET2_1588_EVENT0_IN 0x006c 0x02f8 0x0000 6 0 -#define MX6UL_PAD_GPIO1_IO04__UART5_DCE_TX 0x006c 0x02f8 0x0000 8 0 -#define MX6UL_PAD_GPIO1_IO04__UART5_DTE_RX 0x006c 0x02f8 0x0644 8 2 -#define MX6UL_PAD_GPIO1_IO05__ENET2_REF_CLK2 0x0070 0x02fc 0x057c 0 1 -#define MX6UL_PAD_GPIO1_IO05__PWM4_OUT 0x0070 0x02fc 0x0000 1 0 -#define MX6UL_PAD_GPIO1_IO05__ANATOP_OTG2_ID 0x0070 0x02fc 0x04bc 2 0 -#define MX6UL_PAD_GPIO1_IO05__CSI_FIELD 0x0070 0x02fc 0x0530 3 0 -#define MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x0070 0x02fc 0x0000 4 0 -#define MX6UL_PAD_GPIO1_IO05__GPIO1_IO05 0x0070 0x02fc 0x0000 5 0 -#define MX6UL_PAD_GPIO1_IO05__ENET2_1588_EVENT0_OUT 0x0070 0x02fc 0x0000 6 0 -#define MX6UL_PAD_GPIO1_IO05__UART5_DCE_RX 0x0070 0x02fc 0x0644 8 3 -#define MX6UL_PAD_GPIO1_IO05__UART5_DTE_TX 0x0070 0x02fc 0x0000 8 0 -#define MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x0074 0x0300 0x0578 0 0 -#define MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x0074 0x0300 0x0580 1 0 -#define MX6UL_PAD_GPIO1_IO06__USB_OTG_PWR_WAKE 0x0074 0x0300 0x0000 2 0 -#define MX6UL_PAD_GPIO1_IO06__CSI_MCLK 0x0074 0x0300 0x0000 3 0 -#define MX6UL_PAD_GPIO1_IO06__USDHC2_WP 0x0074 0x0300 0x069c 4 0 -#define MX6UL_PAD_GPIO1_IO06__GPIO1_IO06 0x0074 0x0300 0x0000 5 0 -#define MX6UL_PAD_GPIO1_IO06__CCM_WAIT 0x0074 0x0300 0x0000 6 0 -#define MX6UL_PAD_GPIO1_IO06__CCM_REF_EN_B 0x0074 0x0300 0x0000 7 0 -#define MX6UL_PAD_GPIO1_IO06__UART1_DCE_CTS 0x0074 0x0300 0x0000 8 0 -#define MX6UL_PAD_GPIO1_IO06__UART1_DTE_RTS 0x0074 0x0300 0x0620 8 0 -#define MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x0078 0x0304 0x0000 0 0 -#define MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x0078 0x0304 0x0000 1 0 -#define MX6UL_PAD_GPIO1_IO07__USB_OTG_HOST_MODE 0x0078 0x0304 0x0000 2 0 -#define MX6UL_PAD_GPIO1_IO07__CSI_PIXCLK 0x0078 0x0304 0x0528 3 0 -#define MX6UL_PAD_GPIO1_IO07__USDHC2_CD_B 0x0078 0x0304 0x0674 4 1 -#define MX6UL_PAD_GPIO1_IO07__GPIO1_IO07 0x0078 0x0304 0x0000 5 0 -#define MX6UL_PAD_GPIO1_IO07__CCM_STOP 0x0078 0x0304 0x0000 6 0 -#define MX6UL_PAD_GPIO1_IO07__UART1_DCE_RTS 0x0078 0x0304 0x0620 8 1 -#define MX6UL_PAD_GPIO1_IO07__UART1_DTE_CTS 0x0078 0x0304 0x0000 8 0 -#define MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x007c 0x0308 0x0000 0 0 -#define MX6UL_PAD_GPIO1_IO08__WDOG1_WDOG_B 0x007c 0x0308 0x0000 1 0 -#define MX6UL_PAD_GPIO1_IO08__SPDIF_OUT 0x007c 0x0308 0x0000 2 0 -#define MX6UL_PAD_GPIO1_IO08__CSI_VSYNC 0x007c 0x0308 0x052c 3 1 -#define MX6UL_PAD_GPIO1_IO08__USDHC2_VSELECT 0x007c 0x0308 0x0000 4 0 -#define MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0x007c 0x0308 0x0000 5 0 -#define MX6UL_PAD_GPIO1_IO08__CCM_PMIC_RDY 0x007c 0x0308 0x04c0 6 1 -#define MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x007c 0x0308 0x0640 8 1 -#define MX6UL_PAD_GPIO1_IO08__UART5_DTE_CTS 0x007c 0x0308 0x0000 8 0 -#define MX6UL_PAD_GPIO1_IO09__PWM2_OUT 0x0080 0x030c 0x0000 0 0 -#define MX6UL_PAD_GPIO1_IO09__WDOG1_WDOG_ANY 0x0080 0x030c 0x0000 1 0 -#define MX6UL_PAD_GPIO1_IO09__SPDIF_IN 0x0080 0x030c 0x0618 2 0 -#define MX6UL_PAD_GPIO1_IO09__CSI_HSYNC 0x0080 0x030c 0x0524 3 1 -#define MX6UL_PAD_GPIO1_IO09__USDHC2_RESET_B 0x0080 0x030c 0x0000 4 0 -#define MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x0080 0x030c 0x0000 5 0 -#define MX6UL_PAD_GPIO1_IO09__USDHC1_RESET_B 0x0080 0x030c 0x0000 6 0 -#define MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x0080 0x030c 0x0000 8 0 -#define MX6UL_PAD_GPIO1_IO09__UART5_DTE_RTS 0x0080 0x030c 0x0640 8 2 -#define MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x0084 0x0310 0x0000 0 0 -#define MX6UL_PAD_UART1_TX_DATA__UART1_DTE_RX 0x0084 0x0310 0x0624 0 2 -#define MX6UL_PAD_UART1_TX_DATA__ENET1_RDATA02 0x0084 0x0310 0x0000 1 0 -#define MX6UL_PAD_UART1_TX_DATA__I2C3_SCL 0x0084 0x0310 0x05b4 2 0 -#define MX6UL_PAD_UART1_TX_DATA__CSI_DATA02 0x0084 0x0310 0x04c4 3 1 -#define MX6UL_PAD_UART1_TX_DATA__GPT1_COMPARE1 0x0084 0x0310 0x0000 4 0 -#define MX6UL_PAD_UART1_TX_DATA__GPIO1_IO16 0x0084 0x0310 0x0000 5 0 -#define MX6UL_PAD_UART1_TX_DATA__SPDIF_OUT 0x0084 0x0310 0x0000 8 0 -#define MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x0088 0x0314 0x0624 0 3 -#define MX6UL_PAD_UART1_RX_DATA__UART1_DTE_TX 0x0088 0x0314 0x0000 0 0 -#define MX6UL_PAD_UART1_RX_DATA__ENET1_RDATA03 0x0088 0x0314 0x0000 1 0 -#define MX6UL_PAD_UART1_RX_DATA__I2C3_SDA 0x0088 0x0314 0x05b8 2 0 -#define MX6UL_PAD_UART1_RX_DATA__CSI_DATA03 0x0088 0x0314 0x04c8 3 1 -#define MX6UL_PAD_UART1_RX_DATA__GPT1_CLK 0x0088 0x0314 0x0594 4 0 -#define MX6UL_PAD_UART1_RX_DATA__GPIO1_IO17 0x0088 0x0314 0x0000 5 0 -#define MX6UL_PAD_UART1_RX_DATA__SPDIF_IN 0x0088 0x0314 0x0618 8 1 -#define MX6UL_PAD_UART1_CTS_B__UART1_DCE_CTS 0x008c 0x0318 0x0000 0 0 -#define MX6UL_PAD_UART1_CTS_B__UART1_DTE_RTS 0x008c 0x0318 0x0620 0 2 -#define MX6UL_PAD_UART1_CTS_B__ENET1_RX_CLK 0x008c 0x0318 0x0000 1 0 -#define MX6UL_PAD_UART1_CTS_B__USDHC1_WP 0x008c 0x0318 0x066c 2 1 -#define MX6UL_PAD_UART1_CTS_B__CSI_DATA04 0x008c 0x0318 0x04d8 3 0 -#define MX6UL_PAD_UART1_CTS_B__ENET2_1588_EVENT1_IN 0x008c 0x0318 0x0000 4 0 -#define MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x008c 0x0318 0x0000 5 0 -#define MX6UL_PAD_UART1_CTS_B__USDHC2_WP 0x008c 0x0318 0x069c 8 1 -#define MX6UL_PAD_UART1_RTS_B__UART1_DCE_RTS 0x0090 0x031c 0x0620 0 3 -#define MX6UL_PAD_UART1_RTS_B__UART1_DTE_CTS 0x0090 0x031c 0x0000 0 0 -#define MX6UL_PAD_UART1_RTS_B__ENET1_TX_ER 0x0090 0x031c 0x0000 1 0 -#define MX6UL_PAD_UART1_RTS_B__USDHC1_CD_B 0x0090 0x031c 0x0668 2 1 -#define MX6UL_PAD_UART1_RTS_B__CSI_DATA05 0x0090 0x031c 0x04cc 3 1 -#define MX6UL_PAD_UART1_RTS_B__ENET2_1588_EVENT1_OUT 0x0090 0x031c 0x0000 4 0 -#define MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x0090 0x031c 0x0000 5 0 -#define MX6UL_PAD_UART1_RTS_B__USDHC2_CD_B 0x0090 0x031c 0x0674 8 2 -#define MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x0094 0x0320 0x0000 0 0 -#define MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x0094 0x0320 0x062c 0 0 -#define MX6UL_PAD_UART2_TX_DATA__ENET1_TDATA02 0x0094 0x0320 0x0000 1 0 -#define MX6UL_PAD_UART2_TX_DATA__I2C4_SCL 0x0094 0x0320 0x05bc 2 0 -#define MX6UL_PAD_UART2_TX_DATA__CSI_DATA06 0x0094 0x0320 0x04dc 3 0 -#define MX6UL_PAD_UART2_TX_DATA__GPT1_CAPTURE1 0x0094 0x0320 0x058c 4 1 -#define MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x0094 0x0320 0x0000 5 0 -#define MX6UL_PAD_UART2_TX_DATA__ECSPI3_SS0 0x0094 0x0320 0x0560 8 0 -#define MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x0098 0x0324 0x062c 0 1 -#define MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x0098 0x0324 0x0000 0 0 -#define MX6UL_PAD_UART2_RX_DATA__ENET1_TDATA03 0x0098 0x0324 0x0000 1 0 -#define MX6UL_PAD_UART2_RX_DATA__I2C4_SDA 0x0098 0x0324 0x05c0 2 0 -#define MX6UL_PAD_UART2_RX_DATA__CSI_DATA07 0x0098 0x0324 0x04e0 3 0 -#define MX6UL_PAD_UART2_RX_DATA__GPT1_CAPTURE2 0x0098 0x0324 0x0590 4 0 -#define MX6UL_PAD_UART2_RX_DATA__GPIO1_IO21 0x0098 0x0324 0x0000 5 0 -#define MX6UL_PAD_UART2_RX_DATA__SJC_DONE 0x0098 0x0324 0x0000 7 0 -#define MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK 0x0098 0x0324 0x0554 8 0 -#define MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS 0x009c 0x0328 0x0000 0 0 -#define MX6UL_PAD_UART2_CTS_B__UART2_DTE_RTS 0x009c 0x0328 0x0628 0 0 -#define MX6UL_PAD_UART2_CTS_B__ENET1_CRS 0x009c 0x0328 0x0000 1 0 -#define MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x009c 0x0328 0x0000 2 0 -#define MX6UL_PAD_UART2_CTS_B__CSI_DATA08 0x009c 0x0328 0x04e4 3 0 -#define MX6UL_PAD_UART2_CTS_B__GPT1_COMPARE2 0x009c 0x0328 0x0000 4 0 -#define MX6UL_PAD_UART2_CTS_B__GPIO1_IO22 0x009c 0x0328 0x0000 5 0 -#define MX6UL_PAD_UART2_CTS_B__SJC_DE_B 0x009c 0x0328 0x0000 7 0 -#define MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI 0x009c 0x0328 0x055c 8 0 -#define MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS 0x00a0 0x032c 0x0628 0 1 -#define MX6UL_PAD_UART2_RTS_B__UART2_DTE_CTS 0x00a0 0x032c 0x0000 0 0 -#define MX6UL_PAD_UART2_RTS_B__ENET1_COL 0x00a0 0x032c 0x0000 1 0 -#define MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x00a0 0x032c 0x0588 2 0 -#define MX6UL_PAD_UART2_RTS_B__CSI_DATA09 0x00a0 0x032c 0x04e8 3 0 -#define MX6UL_PAD_UART2_RTS_B__GPT1_COMPARE3 0x00a0 0x032c 0x0000 4 0 -#define MX6UL_PAD_UART2_RTS_B__GPIO1_IO23 0x00a0 0x032c 0x0000 5 0 -#define MX6UL_PAD_UART2_RTS_B__SJC_FAIL 0x00a0 0x032c 0x0000 7 0 -#define MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO 0x00a0 0x032c 0x0558 8 0 -#define MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x00a4 0x0330 0x0000 0 0 -#define MX6UL_PAD_UART3_TX_DATA__UART3_DTE_RX 0x00a4 0x0330 0x0634 0 0 -#define MX6UL_PAD_UART3_TX_DATA__ENET2_RDATA02 0x00a4 0x0330 0x0000 1 0 -#define MX6UL_PAD_UART3_TX_DATA__SIM1_PORT0_PD 0x00a4 0x0330 0x0000 2 0 -#define MX6UL_PAD_UART3_TX_DATA__CSI_DATA01 0x00a4 0x0330 0x04d4 3 0 -#define MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x00a4 0x0330 0x0000 4 0 -#define MX6UL_PAD_UART3_TX_DATA__UART2_DTE_RTS 0x00a4 0x0330 0x0628 4 2 -#define MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24 0x00a4 0x0330 0x0000 5 0 -#define MX6UL_PAD_UART3_TX_DATA__SJC_JTAG_ACT 0x00a4 0x0330 0x0000 7 0 -#define MX6UL_PAD_UART3_TX_DATA__ANATOP_OTG1_ID 0x00a4 0x0330 0x04b8 8 1 -#define MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x00a8 0x0334 0x0634 0 1 -#define MX6UL_PAD_UART3_RX_DATA__UART3_DTE_TX 0x00a8 0x0334 0x0000 0 0 -#define MX6UL_PAD_UART3_RX_DATA__ENET2_RDATA03 0x00a8 0x0334 0x0000 1 0 -#define MX6UL_PAD_UART3_RX_DATA__SIM2_PORT0_PD 0x00a8 0x0334 0x0000 2 0 -#define MX6UL_PAD_UART3_RX_DATA__CSI_DATA00 0x00a8 0x0334 0x04d0 3 0 -#define MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x00a8 0x0334 0x0628 4 3 -#define MX6UL_PAD_UART3_RX_DATA__UART2_DTE_CTS 0x00a8 0x0334 0x0000 4 0 -#define MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x00a8 0x0334 0x0000 5 0 -#define MX6UL_PAD_UART3_RX_DATA__EPIT1_OUT 0x00a8 0x0334 0x0000 8 0 -#define MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x00ac 0x0338 0x0000 0 0 -#define MX6UL_PAD_UART3_CTS_B__UART3_DTE_RTS 0x00ac 0x0338 0x0630 0 0 -#define MX6UL_PAD_UART3_CTS_B__ENET2_RX_CLK 0x00ac 0x0338 0x0000 1 0 -#define MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x00ac 0x0338 0x0000 2 0 -#define MX6UL_PAD_UART3_CTS_B__CSI_DATA10 0x00ac 0x0338 0x04ec 3 0 -#define MX6UL_PAD_UART3_CTS_B__ENET1_1588_EVENT1_IN 0x00ac 0x0338 0x0000 4 0 -#define MX6UL_PAD_UART3_CTS_B__GPIO1_IO26 0x00ac 0x0338 0x0000 5 0 -#define MX6UL_PAD_UART3_CTS_B__EPIT2_OUT 0x00ac 0x0338 0x0000 8 0 -#define MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x00b0 0x033c 0x0630 0 1 -#define MX6UL_PAD_UART3_RTS_B__UART3_DTE_CTS 0x00b0 0x033c 0x0000 0 0 -#define MX6UL_PAD_UART3_RTS_B__ENET2_TX_ER 0x00b0 0x033c 0x0000 1 0 -#define MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x00b0 0x033c 0x0584 2 0 -#define MX6UL_PAD_UART3_RTS_B__CSI_DATA11 0x00b0 0x033c 0x04f0 3 0 -#define MX6UL_PAD_UART3_RTS_B__ENET1_1588_EVENT1_OUT 0x00b0 0x033c 0x0000 4 0 -#define MX6UL_PAD_UART3_RTS_B__GPIO1_IO27 0x00b0 0x033c 0x0000 5 0 -#define MX6UL_PAD_UART3_RTS_B__WDOG1_WDOG_B 0x00b0 0x033c 0x0000 8 0 -#define MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x00b4 0x0340 0x0000 0 0 -#define MX6UL_PAD_UART4_TX_DATA__UART4_DTE_RX 0x00b4 0x0340 0x063c 0 0 -#define MX6UL_PAD_UART4_TX_DATA__ENET2_TDATA02 0x00b4 0x0340 0x0000 1 0 -#define MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x00b4 0x0340 0x05a4 2 1 -#define MX6UL_PAD_UART4_TX_DATA__CSI_DATA12 0x00b4 0x0340 0x04f4 3 0 -#define MX6UL_PAD_UART4_TX_DATA__CSU_CSU_ALARM_AUT02 0x00b4 0x0340 0x0000 4 0 -#define MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x00b4 0x0340 0x0000 5 0 -#define MX6UL_PAD_UART4_TX_DATA__ECSPI2_SCLK 0x00b4 0x0340 0x0544 8 1 -#define MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x00b8 0x0344 0x063c 0 1 -#define MX6UL_PAD_UART4_RX_DATA__UART4_DTE_TX 0x00b8 0x0344 0x0000 0 0 -#define MX6UL_PAD_UART4_RX_DATA__ENET2_TDATA03 0x00b8 0x0344 0x0000 1 0 -#define MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x00b8 0x0344 0x05a8 2 2 -#define MX6UL_PAD_UART4_RX_DATA__CSI_DATA13 0x00b8 0x0344 0x04f8 3 0 -#define MX6UL_PAD_UART4_RX_DATA__CSU_CSU_ALARM_AUT01 0x00b8 0x0344 0x0000 4 0 -#define MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x00b8 0x0344 0x0000 5 0 -#define MX6UL_PAD_UART4_RX_DATA__ECSPI2_SS0 0x00b8 0x0344 0x0550 8 1 -#define MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x00bc 0x0348 0x0000 5 0 -#define MX6UL_PAD_UART5_TX_DATA__ECSPI2_MOSI 0x00bc 0x0348 0x054c 8 0 -#define MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x00bc 0x0348 0x0000 0 0 -#define MX6UL_PAD_UART5_TX_DATA__UART5_DTE_RX 0x00bc 0x0348 0x0644 0 4 -#define MX6UL_PAD_UART5_TX_DATA__ENET2_CRS 0x00bc 0x0348 0x0000 1 0 -#define MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x00bc 0x0348 0x05ac 2 2 -#define MX6UL_PAD_UART5_TX_DATA__CSI_DATA14 0x00bc 0x0348 0x04fc 3 0 -#define MX6UL_PAD_UART5_TX_DATA__CSU_CSU_ALARM_AUT00 0x00bc 0x0348 0x0000 4 0 -#define MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x00c0 0x034c 0x0644 0 5 -#define MX6UL_PAD_UART5_RX_DATA__UART5_DTE_TX 0x00c0 0x034c 0x0000 0 0 -#define MX6UL_PAD_UART5_RX_DATA__ENET2_COL 0x00c0 0x034c 0x0000 1 0 -#define MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x00c0 0x034c 0x05b0 2 2 -#define MX6UL_PAD_UART5_RX_DATA__CSI_DATA15 0x00c0 0x034c 0x0500 3 0 -#define MX6UL_PAD_UART5_RX_DATA__CSU_CSU_INT_DEB 0x00c0 0x034c 0x0000 4 0 -#define MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x00c0 0x034c 0x0000 5 0 -#define MX6UL_PAD_UART5_RX_DATA__ECSPI2_MISO 0x00c0 0x034c 0x0548 8 1 -#define MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x00c4 0x0350 0x0000 0 0 -#define MX6UL_PAD_ENET1_RX_DATA0__UART4_DCE_RTS 0x00c4 0x0350 0x0638 1 0 -#define MX6UL_PAD_ENET1_RX_DATA0__UART4_DTE_CTS 0x00c4 0x0350 0x0000 1 0 -#define MX6UL_PAD_ENET1_RX_DATA0__PWM1_OUT 0x00c4 0x0350 0x0000 2 0 -#define MX6UL_PAD_ENET1_RX_DATA0__CSI_DATA16 0x00c4 0x0350 0x0504 3 0 -#define MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX 0x00c4 0x0350 0x0000 4 0 -#define MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00 0x00c4 0x0350 0x0000 5 0 -#define MX6UL_PAD_ENET1_RX_DATA0__KPP_ROW00 0x00c4 0x0350 0x05d0 6 0 -#define MX6UL_PAD_ENET1_RX_DATA0__USDHC1_LCTL 0x00c4 0x0350 0x0000 8 0 -#define MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x00c8 0x0354 0x0000 0 0 -#define MX6UL_PAD_ENET1_RX_DATA1__UART4_DCE_CTS 0x00c8 0x0354 0x0000 1 0 -#define MX6UL_PAD_ENET1_RX_DATA1__UART4_DTE_RTS 0x00c8 0x0354 0x0638 1 1 -#define MX6UL_PAD_ENET1_RX_DATA1__PWM2_OUT 0x00c8 0x0354 0x0000 2 0 -#define MX6UL_PAD_ENET1_RX_DATA1__CSI_DATA17 0x00c8 0x0354 0x0508 3 0 -#define MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX 0x00c8 0x0354 0x0584 4 1 -#define MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01 0x00c8 0x0354 0x0000 5 0 -#define MX6UL_PAD_ENET1_RX_DATA1__KPP_COL00 0x00c8 0x0354 0x05c4 6 0 -#define MX6UL_PAD_ENET1_RX_DATA1__USDHC2_LCTL 0x00c8 0x0354 0x0000 8 0 -#define MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x00cc 0x0358 0x0000 0 0 -#define MX6UL_PAD_ENET1_RX_EN__UART5_DCE_RTS 0x00cc 0x0358 0x0640 1 3 -#define MX6UL_PAD_ENET1_RX_EN__UART5_DTE_CTS 0x00cc 0x0358 0x0000 1 0 -#define MX6UL_PAD_ENET1_RX_EN__OSC32K_32K_OUT 0x00cc 0x0358 0x0000 2 0 -#define MX6UL_PAD_ENET1_RX_EN__CSI_DATA18 0x00cc 0x0358 0x050c 3 0 -#define MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX 0x00cc 0x0358 0x0000 4 0 -#define MX6UL_PAD_ENET1_RX_EN__GPIO2_IO02 0x00cc 0x0358 0x0000 5 0 -#define MX6UL_PAD_ENET1_RX_EN__KPP_ROW01 0x00cc 0x0358 0x05d4 6 0 -#define MX6UL_PAD_ENET1_RX_EN__USDHC1_VSELECT 0x00cc 0x0358 0x0000 8 0 -#define MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x00d0 0x035c 0x0000 0 0 -#define MX6UL_PAD_ENET1_TX_DATA0__UART5_DCE_CTS 0x00d0 0x035c 0x0000 1 0 -#define MX6UL_PAD_ENET1_TX_DATA0__UART5_DTE_RTS 0x00d0 0x035c 0x0640 1 4 -#define MX6UL_PAD_ENET1_TX_DATA0__REF_CLK_24M 0x00d0 0x035c 0x0000 2 0 -#define MX6UL_PAD_ENET1_TX_DATA0__CSI_DATA19 0x00d0 0x035c 0x0510 3 0 -#define MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX 0x00d0 0x035c 0x0588 4 1 -#define MX6UL_PAD_ENET1_TX_DATA0__GPIO2_IO03 0x00d0 0x035c 0x0000 5 0 -#define MX6UL_PAD_ENET1_TX_DATA0__KPP_COL01 0x00d0 0x035c 0x05c8 6 0 -#define MX6UL_PAD_ENET1_TX_DATA0__USDHC2_VSELECT 0x00d0 0x035c 0x0000 8 0 -#define MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x00d4 0x0360 0x0000 0 0 -#define MX6UL_PAD_ENET1_TX_DATA1__UART6_DCE_CTS 0x00d4 0x0360 0x0000 1 0 -#define MX6UL_PAD_ENET1_TX_DATA1__UART6_DTE_RTS 0x00d4 0x0360 0x0648 1 2 -#define MX6UL_PAD_ENET1_TX_DATA1__PWM5_OUT 0x00d4 0x0360 0x0000 2 0 -#define MX6UL_PAD_ENET1_TX_DATA1__CSI_DATA20 0x00d4 0x0360 0x0514 3 0 -#define MX6UL_PAD_ENET1_TX_DATA1__ENET2_MDIO 0x00d4 0x0360 0x0580 4 1 -#define MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04 0x00d4 0x0360 0x0000 5 0 -#define MX6UL_PAD_ENET1_TX_DATA1__KPP_ROW02 0x00d4 0x0360 0x05d8 6 0 -#define MX6UL_PAD_ENET1_TX_DATA1__WDOG1_WDOG_RST_B_DEB 0x00d4 0x0360 0x0000 8 0 -#define MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x00d8 0x0364 0x0000 0 0 -#define MX6UL_PAD_ENET1_TX_EN__UART6_DCE_RTS 0x00d8 0x0364 0x0648 1 3 -#define MX6UL_PAD_ENET1_TX_EN__UART6_DTE_CTS 0x00d8 0x0364 0x0000 1 0 -#define MX6UL_PAD_ENET1_TX_EN__PWM6_OUT 0x00d8 0x0364 0x0000 2 0 -#define MX6UL_PAD_ENET1_TX_EN__CSI_DATA21 0x00d8 0x0364 0x0518 3 0 -#define MX6UL_PAD_ENET1_TX_EN__ENET2_MDC 0x00d8 0x0364 0x0000 4 0 -#define MX6UL_PAD_ENET1_TX_EN__GPIO2_IO05 0x00d8 0x0364 0x0000 5 0 -#define MX6UL_PAD_ENET1_TX_EN__KPP_COL02 0x00d8 0x0364 0x05cc 6 0 -#define MX6UL_PAD_ENET1_TX_EN__WDOG2_WDOG_RST_B_DEB 0x00d8 0x0364 0x0000 8 0 -#define MX6UL_PAD_ENET1_TX_CLK__ENET1_TX_CLK 0x00dc 0x0368 0x0000 0 0 -#define MX6UL_PAD_ENET1_TX_CLK__UART7_DCE_CTS 0x00dc 0x0368 0x0000 1 0 -#define MX6UL_PAD_ENET1_TX_CLK__UART7_DTE_RTS 0x00dc 0x0368 0x0650 1 0 -#define MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT 0x00dc 0x0368 0x0000 2 0 -#define MX6UL_PAD_ENET1_TX_CLK__CSI_DATA22 0x00dc 0x0368 0x051c 3 0 -#define MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x00dc 0x0368 0x0574 4 2 -#define MX6UL_PAD_ENET1_TX_CLK__GPIO2_IO06 0x00dc 0x0368 0x0000 5 0 -#define MX6UL_PAD_ENET1_TX_CLK__KPP_ROW03 0x00dc 0x0368 0x0000 6 0 -#define MX6UL_PAD_ENET1_TX_CLK__GPT1_CLK 0x00dc 0x0368 0x0594 8 1 -#define MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x00e0 0x036c 0x0000 0 0 -#define MX6UL_PAD_ENET1_RX_ER__UART7_DCE_RTS 0x00e0 0x036c 0x0650 1 1 -#define MX6UL_PAD_ENET1_RX_ER__UART7_DTE_CTS 0x00e0 0x036c 0x0000 1 0 -#define MX6UL_PAD_ENET1_RX_ER__PWM8_OUT 0x00e0 0x036c 0x0000 2 0 -#define MX6UL_PAD_ENET1_RX_ER__CSI_DATA23 0x00e0 0x036c 0x0520 3 0 -#define MX6UL_PAD_ENET1_RX_ER__EIM_CRE 0x00e0 0x036c 0x0000 4 0 -#define MX6UL_PAD_ENET1_RX_ER__GPIO2_IO07 0x00e0 0x036c 0x0000 5 0 -#define MX6UL_PAD_ENET1_RX_ER__KPP_COL03 0x00e0 0x036c 0x0000 6 0 -#define MX6UL_PAD_ENET1_RX_ER__GPT1_CAPTURE2 0x00e0 0x036c 0x0590 8 1 -#define MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x00e4 0x0370 0x0000 0 0 -#define MX6UL_PAD_ENET2_RX_DATA0__UART6_DCE_TX 0x00e4 0x0370 0x0000 1 0 -#define MX6UL_PAD_ENET2_RX_DATA0__UART6_DTE_RX 0x00e4 0x0370 0x064c 1 1 -#define MX6UL_PAD_ENET2_RX_DATA0__SIM1_PORT0_TRXD 0x00e4 0x0370 0x0000 2 0 -#define MX6UL_PAD_ENET2_RX_DATA0__I2C3_SCL 0x00e4 0x0370 0x05b4 3 1 -#define MX6UL_PAD_ENET2_RX_DATA0__ENET1_MDIO 0x00e4 0x0370 0x0578 4 1 -#define MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x00e4 0x0370 0x0000 5 0 -#define MX6UL_PAD_ENET2_RX_DATA0__KPP_ROW04 0x00e4 0x0370 0x0000 6 0 -#define MX6UL_PAD_ENET2_RX_DATA0__USB_OTG1_PWR 0x00e4 0x0370 0x0000 8 0 -#define MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x00e8 0x0374 0x0000 0 0 -#define MX6UL_PAD_ENET2_RX_DATA1__UART6_DCE_RX 0x00e8 0x0374 0x064c 1 2 -#define MX6UL_PAD_ENET2_RX_DATA1__UART6_DTE_TX 0x00e8 0x0374 0x0000 1 0 -#define MX6UL_PAD_ENET2_RX_DATA1__SIM1_PORT0_CLK 0x00e8 0x0374 0x0000 2 0 -#define MX6UL_PAD_ENET2_RX_DATA1__I2C3_SDA 0x00e8 0x0374 0x05b8 3 1 -#define MX6UL_PAD_ENET2_RX_DATA1__ENET1_MDC 0x00e8 0x0374 0x0000 4 0 -#define MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09 0x00e8 0x0374 0x0000 5 0 -#define MX6UL_PAD_ENET2_RX_DATA1__KPP_COL04 0x00e8 0x0374 0x0000 6 0 -#define MX6UL_PAD_ENET2_RX_DATA1__USB_OTG1_OC 0x00e8 0x0374 0x0664 8 1 -#define MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x00ec 0x0378 0x0000 0 0 -#define MX6UL_PAD_ENET2_RX_EN__UART7_DCE_TX 0x00ec 0x0378 0x0000 1 0 -#define MX6UL_PAD_ENET2_RX_EN__UART7_DTE_RX 0x00ec 0x0378 0x0654 1 0 -#define MX6UL_PAD_ENET2_RX_EN__SIM1_PORT0_RST_B 0x00ec 0x0378 0x0000 2 0 -#define MX6UL_PAD_ENET2_RX_EN__I2C4_SCL 0x00ec 0x0378 0x05bc 3 1 -#define MX6UL_PAD_ENET2_RX_EN__EIM_ADDR26 0x00ec 0x0378 0x0000 4 0 -#define MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x00ec 0x0378 0x0000 5 0 -#define MX6UL_PAD_ENET2_RX_EN__KPP_ROW05 0x00ec 0x0378 0x0000 6 0 -#define MX6UL_PAD_ENET2_RX_EN__ENET1_REF_CLK_25M 0x00ec 0x0378 0x0000 8 0 -#define MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x00f0 0x037c 0x0000 0 0 -#define MX6UL_PAD_ENET2_TX_DATA0__UART7_DCE_RX 0x00f0 0x037c 0x0654 1 1 -#define MX6UL_PAD_ENET2_TX_DATA0__UART7_DTE_TX 0x00f0 0x037c 0x0000 1 0 -#define MX6UL_PAD_ENET2_TX_DATA0__SIM1_PORT0_SVEN 0x00f0 0x037c 0x0000 2 0 -#define MX6UL_PAD_ENET2_TX_DATA0__I2C4_SDA 0x00f0 0x037c 0x05c0 3 1 -#define MX6UL_PAD_ENET2_TX_DATA0__EIM_EB_B02 0x00f0 0x037c 0x0000 4 0 -#define MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11 0x00f0 0x037c 0x0000 5 0 -#define MX6UL_PAD_ENET2_TX_DATA0__KPP_COL05 0x00f0 0x037c 0x0000 6 0 -#define MX6UL_PAD_ENET2_TX_DATA0__REF_CLK_24M 0x00f0 0x037c 0x0000 8 0 -#define MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x00f4 0x0380 0x0000 0 0 -#define MX6UL_PAD_ENET2_TX_DATA1__UART8_DCE_TX 0x00f4 0x0380 0x0000 1 0 -#define MX6UL_PAD_ENET2_TX_DATA1__UART8_DTE_RX 0x00f4 0x0380 0x065c 1 0 -#define MX6UL_PAD_ENET2_TX_DATA1__SIM2_PORT0_TRXD 0x00f4 0x0380 0x0000 2 0 -#define MX6UL_PAD_ENET2_TX_DATA1__ECSPI4_SCLK 0x00f4 0x0380 0x0564 3 0 -#define MX6UL_PAD_ENET2_TX_DATA1__EIM_EB_B03 0x00f4 0x0380 0x0000 4 0 -#define MX6UL_PAD_ENET2_TX_DATA1__GPIO2_IO12 0x00f4 0x0380 0x0000 5 0 -#define MX6UL_PAD_ENET2_TX_DATA1__KPP_ROW06 0x00f4 0x0380 0x0000 6 0 -#define MX6UL_PAD_ENET2_TX_DATA1__USB_OTG2_PWR 0x00f4 0x0380 0x0000 8 0 -#define MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x00f8 0x0384 0x0000 0 0 -#define MX6UL_PAD_ENET2_TX_EN__UART8_DCE_RX 0x00f8 0x0384 0x065c 1 1 -#define MX6UL_PAD_ENET2_TX_EN__UART8_DTE_TX 0x00f8 0x0384 0x0000 1 0 -#define MX6UL_PAD_ENET2_TX_EN__SIM2_PORT0_CLK 0x00f8 0x0384 0x0000 2 0 -#define MX6UL_PAD_ENET2_TX_EN__ECSPI4_MOSI 0x00f8 0x0384 0x056c 3 0 -#define MX6UL_PAD_ENET2_TX_EN__EIM_ACLK_FREERUN 0x00f8 0x0384 0x0000 4 0 -#define MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13 0x00f8 0x0384 0x0000 5 0 -#define MX6UL_PAD_ENET2_TX_EN__KPP_COL06 0x00f8 0x0384 0x0000 6 0 -#define MX6UL_PAD_ENET2_TX_EN__USB_OTG2_OC 0x00f8 0x0384 0x0660 8 1 -#define MX6UL_PAD_ENET2_TX_CLK__ENET2_TX_CLK 0x00fc 0x0388 0x0000 0 0 -#define MX6UL_PAD_ENET2_TX_CLK__UART8_DCE_CTS 0x00fc 0x0388 0x0000 1 0 -#define MX6UL_PAD_ENET2_TX_CLK__UART8_DTE_RTS 0x00fc 0x0388 0x0658 1 0 -#define MX6UL_PAD_ENET2_TX_CLK__SIM2_PORT0_RST_B 0x00fc 0x0388 0x0000 2 0 -#define MX6UL_PAD_ENET2_TX_CLK__ECSPI4_MISO 0x00fc 0x0388 0x0568 3 0 -#define MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x00fc 0x0388 0x057c 4 2 -#define MX6UL_PAD_ENET2_TX_CLK__GPIO2_IO14 0x00fc 0x0388 0x0000 5 0 -#define MX6UL_PAD_ENET2_TX_CLK__KPP_ROW07 0x00fc 0x0388 0x0000 6 0 -#define MX6UL_PAD_ENET2_TX_CLK__ANATOP_OTG2_ID 0x00fc 0x0388 0x04bc 8 1 -#define MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x0100 0x038c 0x0000 0 0 -#define MX6UL_PAD_ENET2_RX_ER__UART8_DCE_RTS 0x0100 0x038c 0x0658 1 1 -#define MX6UL_PAD_ENET2_RX_ER__UART8_DTE_CTS 0x0100 0x038c 0x0000 1 0 -#define MX6UL_PAD_ENET2_RX_ER__SIM2_PORT0_SVEN 0x0100 0x038c 0x0000 2 0 -#define MX6UL_PAD_ENET2_RX_ER__ECSPI4_SS0 0x0100 0x038c 0x0570 3 0 -#define MX6UL_PAD_ENET2_RX_ER__EIM_ADDR25 0x0100 0x038c 0x0000 4 0 -#define MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x0100 0x038c 0x0000 5 0 -#define MX6UL_PAD_ENET2_RX_ER__KPP_COL07 0x0100 0x038c 0x0000 6 0 -#define MX6UL_PAD_ENET2_RX_ER__WDOG1_WDOG_ANY 0x0100 0x038c 0x0000 8 0 -#define MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x0104 0x0390 0x0000 0 0 -#define MX6UL_PAD_LCD_CLK__LCDIF_WR_RWN 0x0104 0x0390 0x0000 1 0 -#define MX6UL_PAD_LCD_CLK__UART4_DCE_TX 0x0104 0x0390 0x0000 2 0 -#define MX6UL_PAD_LCD_CLK__UART4_DTE_RX 0x0104 0x0390 0x063c 2 2 -#define MX6UL_PAD_LCD_CLK__SAI3_MCLK 0x0104 0x0390 0x0600 3 0 -#define MX6UL_PAD_LCD_CLK__EIM_CS2_B 0x0104 0x0390 0x0000 4 0 -#define MX6UL_PAD_LCD_CLK__GPIO3_IO00 0x0104 0x0390 0x0000 5 0 -#define MX6UL_PAD_LCD_CLK__WDOG1_WDOG_RST_B_DEB 0x0104 0x0390 0x0000 8 0 -#define MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x0108 0x0394 0x0000 0 0 -#define MX6UL_PAD_LCD_ENABLE__LCDIF_RD_E 0x0108 0x0394 0x0000 1 0 -#define MX6UL_PAD_LCD_ENABLE__UART4_DCE_RX 0x0108 0x0394 0x063c 2 3 -#define MX6UL_PAD_LCD_ENABLE__UART4_DTE_TX 0x0108 0x0394 0x0000 2 0 -#define MX6UL_PAD_LCD_ENABLE__SAI3_TX_SYNC 0x0108 0x0394 0x060c 3 0 -#define MX6UL_PAD_LCD_ENABLE__EIM_CS3_B 0x0108 0x0394 0x0000 4 0 -#define MX6UL_PAD_LCD_ENABLE__GPIO3_IO01 0x0108 0x0394 0x0000 5 0 -#define MX6UL_PAD_LCD_ENABLE__ECSPI2_RDY 0x0108 0x0394 0x0000 8 0 -#define MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x010c 0x0398 0x05dc 0 0 -#define MX6UL_PAD_LCD_HSYNC__LCDIF_RS 0x010c 0x0398 0x0000 1 0 -#define MX6UL_PAD_LCD_HSYNC__UART4_DCE_CTS 0x010c 0x0398 0x0000 2 0 -#define MX6UL_PAD_LCD_HSYNC__UART4_DTE_RTS 0x010c 0x0398 0x0638 2 2 -#define MX6UL_PAD_LCD_HSYNC__SAI3_TX_BCLK 0x010c 0x0398 0x0608 3 0 -#define MX6UL_PAD_LCD_HSYNC__WDOG3_WDOG_RST_B_DEB 0x010c 0x0398 0x0000 4 0 -#define MX6UL_PAD_LCD_HSYNC__GPIO3_IO02 0x010c 0x0398 0x0000 5 0 -#define MX6UL_PAD_LCD_HSYNC__ECSPI2_SS1 0x010c 0x0398 0x0000 8 0 -#define MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x0110 0x039c 0x0000 0 0 -#define MX6UL_PAD_LCD_VSYNC__LCDIF_BUSY 0x0110 0x039c 0x05dc 1 1 -#define MX6UL_PAD_LCD_VSYNC__UART4_DCE_RTS 0x0110 0x039c 0x0638 2 3 -#define MX6UL_PAD_LCD_VSYNC__UART4_DTE_CTS 0x0110 0x039c 0x0000 2 0 -#define MX6UL_PAD_LCD_VSYNC__SAI3_RX_DATA 0x0110 0x039c 0x0604 3 0 -#define MX6UL_PAD_LCD_VSYNC__WDOG2_WDOG_B 0x0110 0x039c 0x0000 4 0 -#define MX6UL_PAD_LCD_VSYNC__GPIO3_IO03 0x0110 0x039c 0x0000 5 0 -#define MX6UL_PAD_LCD_VSYNC__ECSPI2_SS2 0x0110 0x039c 0x0000 8 0 -#define MX6UL_PAD_LCD_RESET__LCDIF_RESET 0x0114 0x03a0 0x0000 0 0 -#define MX6UL_PAD_LCD_RESET__LCDIF_CS 0x0114 0x03a0 0x0000 1 0 -#define MX6UL_PAD_LCD_RESET__CA7_MX6UL_EVENTI 0x0114 0x03a0 0x0000 2 0 -#define MX6UL_PAD_LCD_RESET__SAI3_TX_DATA 0x0114 0x03a0 0x0000 3 0 -#define MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x0114 0x03a0 0x0000 4 0 -#define MX6UL_PAD_LCD_RESET__GPIO3_IO04 0x0114 0x03a0 0x0000 5 0 -#define MX6UL_PAD_LCD_RESET__ECSPI2_SS3 0x0114 0x03a0 0x0000 8 0 -#define MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x0118 0x03a4 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA00__PWM1_OUT 0x0118 0x03a4 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA00__CA7_MX6UL_TRACE0 0x0118 0x03a4 0x0000 2 0 -#define MX6UL_PAD_LCD_DATA00__ENET1_1588_EVENT2_IN 0x0118 0x03a4 0x0000 3 0 -#define MX6UL_PAD_LCD_DATA00__I2C3_SDA 0x0118 0x03a4 0x05b8 4 2 -#define MX6UL_PAD_LCD_DATA00__GPIO3_IO05 0x0118 0x03a4 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA00__SRC_BT_CFG00 0x0118 0x03a4 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA00__SAI1_MCLK 0x0118 0x03a4 0x05e0 8 1 -#define MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x011c 0x03a8 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA01__PWM2_OUT 0x011c 0x03a8 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA01__CA7_MX6UL_TRACE1 0x011c 0x03a8 0x0000 2 0 -#define MX6UL_PAD_LCD_DATA01__ENET1_1588_EVENT2_OUT 0x011c 0x03a8 0x0000 3 0 -#define MX6UL_PAD_LCD_DATA01__I2C3_SCL 0x011c 0x03a8 0x05b4 4 2 -#define MX6UL_PAD_LCD_DATA01__GPIO3_IO06 0x011c 0x03a8 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA01__SRC_BT_CFG01 0x011c 0x03a8 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA01__SAI1_TX_SYNC 0x011c 0x03a8 0x05ec 8 0 -#define MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x0120 0x03ac 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA02__PWM3_OUT 0x0120 0x03ac 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA02__CA7_MX6UL_TRACE2 0x0120 0x03ac 0x0000 2 0 -#define MX6UL_PAD_LCD_DATA02__ENET1_1588_EVENT3_IN 0x0120 0x03ac 0x0000 3 0 -#define MX6UL_PAD_LCD_DATA02__I2C4_SDA 0x0120 0x03ac 0x05c0 4 2 -#define MX6UL_PAD_LCD_DATA02__GPIO3_IO07 0x0120 0x03ac 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA02__SRC_BT_CFG02 0x0120 0x03ac 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA02__SAI1_TX_BCLK 0x0120 0x03ac 0x05e8 8 0 -#define MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x0124 0x03b0 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA03__PWM4_OUT 0x0124 0x03b0 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA03__CA7_MX6UL_TRACE3 0x0124 0x03b0 0x0000 2 0 -#define MX6UL_PAD_LCD_DATA03__ENET1_1588_EVENT3_OUT 0x0124 0x03b0 0x0000 3 0 -#define MX6UL_PAD_LCD_DATA03__I2C4_SCL 0x0124 0x03b0 0x05bc 4 2 -#define MX6UL_PAD_LCD_DATA03__GPIO3_IO08 0x0124 0x03b0 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA03__SRC_BT_CFG03 0x0124 0x03b0 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA03__SAI1_RX_DATA 0x0124 0x03b0 0x05e4 8 0 -#define MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x0128 0x03b4 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA04__UART8_DCE_CTS 0x0128 0x03b4 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA04__UART8_DTE_RTS 0x0128 0x03b4 0x0658 1 2 -#define MX6UL_PAD_LCD_DATA04__CA7_MX6UL_TRACE4 0x0128 0x03b4 0x0000 2 0 -#define MX6UL_PAD_LCD_DATA04__ENET2_1588_EVENT2_IN 0x0128 0x03b4 0x0000 3 0 -#define MX6UL_PAD_LCD_DATA04__SPDIF_SR_CLK 0x0128 0x03b4 0x0000 4 0 -#define MX6UL_PAD_LCD_DATA04__GPIO3_IO09 0x0128 0x03b4 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA04__SRC_BT_CFG04 0x0128 0x03b4 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA04__SAI1_TX_DATA 0x0128 0x03b4 0x0000 8 0 -#define MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x012c 0x03b8 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA05__UART8_DCE_RTS 0x012c 0x03b8 0x0658 1 3 -#define MX6UL_PAD_LCD_DATA05__UART8_DTE_CTS 0x012c 0x03b8 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA05__CA7_MX6UL_TRACE5 0x012c 0x03b8 0x0000 2 0 -#define MX6UL_PAD_LCD_DATA05__ENET2_1588_EVENT2_OUT 0x012c 0x03b8 0x0000 3 0 -#define MX6UL_PAD_LCD_DATA05__SPDIF_OUT 0x012c 0x03b8 0x0000 4 0 -#define MX6UL_PAD_LCD_DATA05__GPIO3_IO10 0x012c 0x03b8 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA05__SRC_BT_CFG05 0x012c 0x03b8 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA05__ECSPI1_SS1 0x012c 0x03b8 0x0000 8 0 -#define MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x0130 0x03bc 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA06__UART7_DCE_CTS 0x0130 0x03bc 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA06__UART7_DTE_RTS 0x0130 0x03bc 0x0650 1 2 -#define MX6UL_PAD_LCD_DATA06__CA7_MX6UL_TRACE6 0x0130 0x03bc 0x0000 2 0 -#define MX6UL_PAD_LCD_DATA06__ENET2_1588_EVENT3_IN 0x0130 0x03bc 0x0000 3 0 -#define MX6UL_PAD_LCD_DATA06__SPDIF_LOCK 0x0130 0x03bc 0x0000 4 0 -#define MX6UL_PAD_LCD_DATA06__GPIO3_IO11 0x0130 0x03bc 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA06__SRC_BT_CFG06 0x0130 0x03bc 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA06__ECSPI1_SS2 0x0130 0x03bc 0x0000 8 0 -#define MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x0134 0x03c0 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA07__UART7_DCE_RTS 0x0134 0x03c0 0x0650 1 3 -#define MX6UL_PAD_LCD_DATA07__UART7_DTE_CTS 0x0134 0x03c0 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA07__CA7_MX6UL_TRACE7 0x0134 0x03c0 0x0000 2 0 -#define MX6UL_PAD_LCD_DATA07__ENET2_1588_EVENT3_OUT 0x0134 0x03c0 0x0000 3 0 -#define MX6UL_PAD_LCD_DATA07__SPDIF_EXT_CLK 0x0134 0x03c0 0x061c 4 0 -#define MX6UL_PAD_LCD_DATA07__GPIO3_IO12 0x0134 0x03c0 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA07__SRC_BT_CFG07 0x0134 0x03c0 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA07__ECSPI1_SS3 0x0134 0x03c0 0x0000 8 0 -#define MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x0138 0x03c4 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA08__SPDIF_IN 0x0138 0x03c4 0x0618 1 2 -#define MX6UL_PAD_LCD_DATA08__CA7_MX6UL_TRACE8 0x0138 0x03c4 0x0000 2 0 -#define MX6UL_PAD_LCD_DATA08__CSI_DATA16 0x0138 0x03c4 0x0504 3 1 -#define MX6UL_PAD_LCD_DATA08__EIM_DATA00 0x0138 0x03c4 0x0000 4 0 -#define MX6UL_PAD_LCD_DATA08__GPIO3_IO13 0x0138 0x03c4 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA08__SRC_BT_CFG08 0x0138 0x03c4 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA08__FLEXCAN1_TX 0x0138 0x03c4 0x0000 8 0 -#define MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x013c 0x03c8 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA09__SAI3_MCLK 0x013c 0x03c8 0x0600 1 1 -#define MX6UL_PAD_LCD_DATA09__CA7_MX6UL_TRACE9 0x013c 0x03c8 0x0000 2 0 -#define MX6UL_PAD_LCD_DATA09__CSI_DATA17 0x013c 0x03c8 0x0508 3 1 -#define MX6UL_PAD_LCD_DATA09__EIM_DATA01 0x013c 0x03c8 0x0000 4 0 -#define MX6UL_PAD_LCD_DATA09__GPIO3_IO14 0x013c 0x03c8 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA09__SRC_BT_CFG09 0x013c 0x03c8 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA09__FLEXCAN1_RX 0x013c 0x03c8 0x0584 8 2 -#define MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x0140 0x03cc 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA10__SAI3_RX_SYNC 0x0140 0x03cc 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA10__CA7_MX6UL_TRACE10 0x0140 0x03cc 0x0000 2 0 -#define MX6UL_PAD_LCD_DATA10__CSI_DATA18 0x0140 0x03cc 0x050c 3 1 -#define MX6UL_PAD_LCD_DATA10__EIM_DATA02 0x0140 0x03cc 0x0000 4 0 -#define MX6UL_PAD_LCD_DATA10__GPIO3_IO15 0x0140 0x03cc 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA10__SRC_BT_CFG10 0x0140 0x03cc 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA10__FLEXCAN2_TX 0x0140 0x03cc 0x0000 8 0 -#define MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x0144 0x03d0 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA11__SAI3_RX_BCLK 0x0144 0x03d0 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA11__CA7_MX6UL_TRACE11 0x0144 0x03d0 0x0000 2 0 -#define MX6UL_PAD_LCD_DATA11__CSI_DATA19 0x0144 0x03d0 0x0510 3 1 -#define MX6UL_PAD_LCD_DATA11__EIM_DATA03 0x0144 0x03d0 0x0000 4 0 -#define MX6UL_PAD_LCD_DATA11__GPIO3_IO16 0x0144 0x03d0 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA11__SRC_BT_CFG11 0x0144 0x03d0 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA11__FLEXCAN2_RX 0x0144 0x03d0 0x0588 8 2 -#define MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x0148 0x03d4 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA12__SAI3_TX_SYNC 0x0148 0x03d4 0x060c 1 1 -#define MX6UL_PAD_LCD_DATA12__CA7_MX6UL_TRACE12 0x0148 0x03d4 0x0000 2 0 -#define MX6UL_PAD_LCD_DATA12__CSI_DATA20 0x0148 0x03d4 0x0514 3 1 -#define MX6UL_PAD_LCD_DATA12__EIM_DATA04 0x0148 0x03d4 0x0000 4 0 -#define MX6UL_PAD_LCD_DATA12__GPIO3_IO17 0x0148 0x03d4 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA12__SRC_BT_CFG12 0x0148 0x03d4 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA12__ECSPI1_RDY 0x0148 0x03d4 0x0000 8 0 -#define MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x014c 0x03d8 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA13__SAI3_TX_BCLK 0x014c 0x03d8 0x0608 1 1 -#define MX6UL_PAD_LCD_DATA13__CA7_MX6UL_TRACE13 0x014c 0x03d8 0x0000 2 0 -#define MX6UL_PAD_LCD_DATA13__CSI_DATA21 0x014c 0x03d8 0x0518 3 1 -#define MX6UL_PAD_LCD_DATA13__EIM_DATA05 0x014c 0x03d8 0x0000 4 0 -#define MX6UL_PAD_LCD_DATA13__GPIO3_IO18 0x014c 0x03d8 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA13__SRC_BT_CFG13 0x014c 0x03d8 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA13__USDHC2_RESET_B 0x014c 0x03d8 0x0000 8 0 -#define MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x0150 0x03dc 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA14__SAI3_RX_DATA 0x0150 0x03dc 0x0604 1 1 -#define MX6UL_PAD_LCD_DATA14__CA7_MX6UL_TRACE14 0x0150 0x03dc 0x0000 2 0 -#define MX6UL_PAD_LCD_DATA14__CSI_DATA22 0x0150 0x03dc 0x051c 3 1 -#define MX6UL_PAD_LCD_DATA14__EIM_DATA06 0x0150 0x03dc 0x0000 4 0 -#define MX6UL_PAD_LCD_DATA14__GPIO3_IO19 0x0150 0x03dc 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA14__SRC_BT_CFG14 0x0150 0x03dc 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA14__USDHC2_DATA4 0x0150 0x03dc 0x068c 8 0 -#define MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x0154 0x03e0 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA15__SAI3_TX_DATA 0x0154 0x03e0 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA15__CA7_MX6UL_TRACE15 0x0154 0x03e0 0x0000 2 0 -#define MX6UL_PAD_LCD_DATA15__CSI_DATA23 0x0154 0x03e0 0x0520 3 1 -#define MX6UL_PAD_LCD_DATA15__EIM_DATA07 0x0154 0x03e0 0x0000 4 0 -#define MX6UL_PAD_LCD_DATA15__GPIO3_IO20 0x0154 0x03e0 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA15__SRC_BT_CFG15 0x0154 0x03e0 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA15__USDHC2_DATA5 0x0154 0x03e0 0x0690 8 0 -#define MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x0158 0x03e4 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA16__UART7_DCE_TX 0x0158 0x03e4 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA16__UART7_DTE_RX 0x0158 0x03e4 0x0654 1 2 -#define MX6UL_PAD_LCD_DATA16__CA7_MX6UL_TRACE_CLK 0x0158 0x03e4 0x0000 2 0 -#define MX6UL_PAD_LCD_DATA16__CSI_DATA01 0x0158 0x03e4 0x04d4 3 1 -#define MX6UL_PAD_LCD_DATA16__EIM_DATA08 0x0158 0x03e4 0x0000 4 0 -#define MX6UL_PAD_LCD_DATA16__GPIO3_IO21 0x0158 0x03e4 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA16__SRC_BT_CFG24 0x0158 0x03e4 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA16__USDHC2_DATA6 0x0158 0x03e4 0x0694 8 0 -#define MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x015c 0x03e8 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA17__UART7_DCE_RX 0x015c 0x03e8 0x0654 1 3 -#define MX6UL_PAD_LCD_DATA17__UART7_DTE_TX 0x015c 0x03e8 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA17__CA7_MX6UL_TRACE_CTL 0x015c 0x03e8 0x0000 2 0 -#define MX6UL_PAD_LCD_DATA17__CSI_DATA00 0x015c 0x03e8 0x04d0 3 1 -#define MX6UL_PAD_LCD_DATA17__EIM_DATA09 0x015c 0x03e8 0x0000 4 0 -#define MX6UL_PAD_LCD_DATA17__GPIO3_IO22 0x015c 0x03e8 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA17__SRC_BT_CFG25 0x015c 0x03e8 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA17__USDHC2_DATA7 0x015c 0x03e8 0x0698 8 0 -#define MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x0160 0x03ec 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA18__PWM5_OUT 0x0160 0x03ec 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA18__CA7_MX6UL_EVENTO 0x0160 0x03ec 0x0000 2 0 -#define MX6UL_PAD_LCD_DATA18__CSI_DATA10 0x0160 0x03ec 0x04ec 3 1 -#define MX6UL_PAD_LCD_DATA18__EIM_DATA10 0x0160 0x03ec 0x0000 4 0 -#define MX6UL_PAD_LCD_DATA18__GPIO3_IO23 0x0160 0x03ec 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA18__SRC_BT_CFG26 0x0160 0x03ec 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA18__USDHC2_CMD 0x0160 0x03ec 0x0678 8 1 -#define MX6UL_PAD_LCD_DATA19__EIM_DATA11 0x0164 0x03f0 0x0000 4 0 -#define MX6UL_PAD_LCD_DATA19__GPIO3_IO24 0x0164 0x03f0 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA19__SRC_BT_CFG27 0x0164 0x03f0 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA19__USDHC2_CLK 0x0164 0x03f0 0x0670 8 1 -#define MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x0164 0x03f0 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA19__PWM6_OUT 0x0164 0x03f0 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA19__WDOG1_WDOG_ANY 0x0164 0x03f0 0x0000 2 0 -#define MX6UL_PAD_LCD_DATA19__CSI_DATA11 0x0164 0x03f0 0x04f0 3 1 -#define MX6UL_PAD_LCD_DATA20__EIM_DATA12 0x0168 0x03f4 0x0000 4 0 -#define MX6UL_PAD_LCD_DATA20__GPIO3_IO25 0x0168 0x03f4 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA20__SRC_BT_CFG28 0x0168 0x03f4 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA20__USDHC2_DATA0 0x0168 0x03f4 0x067c 8 1 -#define MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x0168 0x03f4 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA20__UART8_DCE_TX 0x0168 0x03f4 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA20__UART8_DTE_RX 0x0168 0x03f4 0x065c 1 2 -#define MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x0168 0x03f4 0x0534 2 0 -#define MX6UL_PAD_LCD_DATA20__CSI_DATA12 0x0168 0x03f4 0x04f4 3 1 -#define MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x016c 0x03f8 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA21__UART8_DCE_RX 0x016c 0x03f8 0x065c 1 3 -#define MX6UL_PAD_LCD_DATA21__UART8_DTE_TX 0x016c 0x03f8 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA21__ECSPI1_SS0 0x016c 0x03f8 0x0540 2 0 -#define MX6UL_PAD_LCD_DATA21__CSI_DATA13 0x016c 0x03f8 0x04f8 3 1 -#define MX6UL_PAD_LCD_DATA21__EIM_DATA13 0x016c 0x03f8 0x0000 4 0 -#define MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x016c 0x03f8 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA21__SRC_BT_CFG29 0x016c 0x03f8 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA21__USDHC2_DATA1 0x016c 0x03f8 0x0680 8 1 -#define MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x0170 0x03fc 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA22__MQS_RIGHT 0x0170 0x03fc 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x0170 0x03fc 0x053c 2 0 -#define MX6UL_PAD_LCD_DATA22__CSI_DATA14 0x0170 0x03fc 0x04fc 3 1 -#define MX6UL_PAD_LCD_DATA22__EIM_DATA14 0x0170 0x03fc 0x0000 4 0 -#define MX6UL_PAD_LCD_DATA22__GPIO3_IO27 0x0170 0x03fc 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA22__SRC_BT_CFG30 0x0170 0x03fc 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA22__USDHC2_DATA2 0x0170 0x03fc 0x0684 8 0 -#define MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x0174 0x0400 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA23__MQS_LEFT 0x0174 0x0400 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA23__ECSPI1_MISO 0x0174 0x0400 0x0538 2 0 -#define MX6UL_PAD_LCD_DATA23__CSI_DATA15 0x0174 0x0400 0x0500 3 1 -#define MX6UL_PAD_LCD_DATA23__EIM_DATA15 0x0174 0x0400 0x0000 4 0 -#define MX6UL_PAD_LCD_DATA23__GPIO3_IO28 0x0174 0x0400 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA23__SRC_BT_CFG31 0x0174 0x0400 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA23__USDHC2_DATA3 0x0174 0x0400 0x0688 8 1 -#define MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0178 0x0404 0x0000 0 0 -#define MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x0178 0x0404 0x0670 1 2 -#define MX6UL_PAD_NAND_RE_B__QSPI_B_SCLK 0x0178 0x0404 0x0000 2 0 -#define MX6UL_PAD_NAND_RE_B__KPP_ROW00 0x0178 0x0404 0x05d0 3 1 -#define MX6UL_PAD_NAND_RE_B__EIM_EB_B00 0x0178 0x0404 0x0000 4 0 -#define MX6UL_PAD_NAND_RE_B__GPIO4_IO00 0x0178 0x0404 0x0000 5 0 -#define MX6UL_PAD_NAND_RE_B__ECSPI3_SS2 0x0178 0x0404 0x0000 8 0 -#define MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x017c 0x0408 0x0000 0 0 -#define MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x017c 0x0408 0x0678 1 2 -#define MX6UL_PAD_NAND_WE_B__QSPI_B_SS0_B 0x017c 0x0408 0x0000 2 0 -#define MX6UL_PAD_NAND_WE_B__KPP_COL00 0x017c 0x0408 0x05c4 3 1 -#define MX6UL_PAD_NAND_WE_B__EIM_EB_B01 0x017c 0x0408 0x0000 4 0 -#define MX6UL_PAD_NAND_WE_B__GPIO4_IO01 0x017c 0x0408 0x0000 5 0 -#define MX6UL_PAD_NAND_WE_B__ECSPI3_SS3 0x017c 0x0408 0x0000 8 0 -#define MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0180 0x040c 0x0000 0 0 -#define MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x0180 0x040c 0x067c 1 2 -#define MX6UL_PAD_NAND_DATA00__QSPI_B_SS1_B 0x0180 0x040c 0x0000 2 0 -#define MX6UL_PAD_NAND_DATA00__KPP_ROW01 0x0180 0x040c 0x05d4 3 1 -#define MX6UL_PAD_NAND_DATA00__EIM_AD08 0x0180 0x040c 0x0000 4 0 -#define MX6UL_PAD_NAND_DATA00__GPIO4_IO02 0x0180 0x040c 0x0000 5 0 -#define MX6UL_PAD_NAND_DATA00__ECSPI4_RDY 0x0180 0x040c 0x0000 8 0 -#define MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0184 0x0410 0x0000 0 0 -#define MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x0184 0x0410 0x0680 1 2 -#define MX6UL_PAD_NAND_DATA01__QSPI_B_DQS 0x0184 0x0410 0x0000 2 0 -#define MX6UL_PAD_NAND_DATA01__KPP_COL01 0x0184 0x0410 0x05c8 3 1 -#define MX6UL_PAD_NAND_DATA01__EIM_AD09 0x0184 0x0410 0x0000 4 0 -#define MX6UL_PAD_NAND_DATA01__GPIO4_IO03 0x0184 0x0410 0x0000 5 0 -#define MX6UL_PAD_NAND_DATA01__ECSPI4_SS1 0x0184 0x0410 0x0000 8 0 -#define MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0188 0x0414 0x0000 0 0 -#define MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x0188 0x0414 0x0684 1 1 -#define MX6UL_PAD_NAND_DATA02__QSPI_B_DATA00 0x0188 0x0414 0x0000 2 0 -#define MX6UL_PAD_NAND_DATA02__KPP_ROW02 0x0188 0x0414 0x05d8 3 1 -#define MX6UL_PAD_NAND_DATA02__EIM_AD10 0x0188 0x0414 0x0000 4 0 -#define MX6UL_PAD_NAND_DATA02__GPIO4_IO04 0x0188 0x0414 0x0000 5 0 -#define MX6UL_PAD_NAND_DATA02__ECSPI4_SS2 0x0188 0x0414 0x0000 8 0 -#define MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x018c 0x0418 0x0000 0 0 -#define MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x018c 0x0418 0x0688 1 2 -#define MX6UL_PAD_NAND_DATA03__QSPI_B_DATA01 0x018c 0x0418 0x0000 2 0 -#define MX6UL_PAD_NAND_DATA03__KPP_COL02 0x018c 0x0418 0x05cc 3 1 -#define MX6UL_PAD_NAND_DATA03__EIM_AD11 0x018c 0x0418 0x0000 4 0 -#define MX6UL_PAD_NAND_DATA03__GPIO4_IO05 0x018c 0x0418 0x0000 5 0 -#define MX6UL_PAD_NAND_DATA03__ECSPI4_SS3 0x018c 0x0418 0x0000 8 0 -#define MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0190 0x041c 0x0000 0 0 -#define MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x0190 0x041c 0x068c 1 1 -#define MX6UL_PAD_NAND_DATA04__QSPI_B_DATA02 0x0190 0x041c 0x0000 2 0 -#define MX6UL_PAD_NAND_DATA04__ECSPI4_SCLK 0x0190 0x041c 0x0564 3 1 -#define MX6UL_PAD_NAND_DATA04__EIM_AD12 0x0190 0x041c 0x0000 4 0 -#define MX6UL_PAD_NAND_DATA04__GPIO4_IO06 0x0190 0x041c 0x0000 5 0 -#define MX6UL_PAD_NAND_DATA04__UART2_DCE_TX 0x0190 0x041c 0x0000 8 0 -#define MX6UL_PAD_NAND_DATA04__UART2_DTE_RX 0x0190 0x041c 0x062c 8 2 -#define MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0194 0x0420 0x0000 0 0 -#define MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x0194 0x0420 0x0690 1 1 -#define MX6UL_PAD_NAND_DATA05__QSPI_B_DATA03 0x0194 0x0420 0x0000 2 0 -#define MX6UL_PAD_NAND_DATA05__ECSPI4_MOSI 0x0194 0x0420 0x056c 3 1 -#define MX6UL_PAD_NAND_DATA05__EIM_AD13 0x0194 0x0420 0x0000 4 0 -#define MX6UL_PAD_NAND_DATA05__GPIO4_IO07 0x0194 0x0420 0x0000 5 0 -#define MX6UL_PAD_NAND_DATA05__UART2_DCE_RX 0x0194 0x0420 0x062c 8 3 -#define MX6UL_PAD_NAND_DATA05__UART2_DTE_TX 0x0194 0x0420 0x0000 8 0 -#define MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0198 0x0424 0x0000 0 0 -#define MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x0198 0x0424 0x0694 1 1 -#define MX6UL_PAD_NAND_DATA06__SAI2_RX_BCLK 0x0198 0x0424 0x0000 2 0 -#define MX6UL_PAD_NAND_DATA06__ECSPI4_MISO 0x0198 0x0424 0x0568 3 1 -#define MX6UL_PAD_NAND_DATA06__EIM_AD14 0x0198 0x0424 0x0000 4 0 -#define MX6UL_PAD_NAND_DATA06__GPIO4_IO08 0x0198 0x0424 0x0000 5 0 -#define MX6UL_PAD_NAND_DATA06__UART2_DCE_CTS 0x0198 0x0424 0x0000 8 0 -#define MX6UL_PAD_NAND_DATA06__UART2_DTE_RTS 0x0198 0x0424 0x0628 8 4 -#define MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x019c 0x0428 0x0000 0 0 -#define MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x019c 0x0428 0x0698 1 1 -#define MX6UL_PAD_NAND_DATA07__QSPI_A_SS1_B 0x019c 0x0428 0x0000 2 0 -#define MX6UL_PAD_NAND_DATA07__ECSPI4_SS0 0x019c 0x0428 0x0570 3 1 -#define MX6UL_PAD_NAND_DATA07__EIM_AD15 0x019c 0x0428 0x0000 4 0 -#define MX6UL_PAD_NAND_DATA07__GPIO4_IO09 0x019c 0x0428 0x0000 5 0 -#define MX6UL_PAD_NAND_DATA07__UART2_DCE_RTS 0x019c 0x0428 0x0628 8 5 -#define MX6UL_PAD_NAND_DATA07__UART2_DTE_CTS 0x019c 0x0428 0x0000 8 0 -#define MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x01a0 0x042c 0x0000 0 0 -#define MX6UL_PAD_NAND_ALE__USDHC2_RESET_B 0x01a0 0x042c 0x0000 1 0 -#define MX6UL_PAD_NAND_ALE__QSPI_A_DQS 0x01a0 0x042c 0x0000 2 0 -#define MX6UL_PAD_NAND_ALE__PWM3_OUT 0x01a0 0x042c 0x0000 3 0 -#define MX6UL_PAD_NAND_ALE__EIM_ADDR17 0x01a0 0x042c 0x0000 4 0 -#define MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x01a0 0x042c 0x0000 5 0 -#define MX6UL_PAD_NAND_ALE__ECSPI3_SS1 0x01a0 0x042c 0x0000 8 0 -#define MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x01a4 0x0430 0x0000 0 0 -#define MX6UL_PAD_NAND_WP_B__USDHC1_RESET_B 0x01a4 0x0430 0x0000 1 0 -#define MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x01a4 0x0430 0x0000 2 0 -#define MX6UL_PAD_NAND_WP_B__PWM4_OUT 0x01a4 0x0430 0x0000 3 0 -#define MX6UL_PAD_NAND_WP_B__EIM_BCLK 0x01a4 0x0430 0x0000 4 0 -#define MX6UL_PAD_NAND_WP_B__GPIO4_IO11 0x01a4 0x0430 0x0000 5 0 -#define MX6UL_PAD_NAND_WP_B__ECSPI3_RDY 0x01a4 0x0430 0x0000 8 0 -#define MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x01a8 0x0434 0x0000 0 0 -#define MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x01a8 0x0434 0x0000 1 0 -#define MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x01a8 0x0434 0x0000 2 0 -#define MX6UL_PAD_NAND_READY_B__ECSPI3_SS0 0x01a8 0x0434 0x0560 3 1 -#define MX6UL_PAD_NAND_READY_B__EIM_CS1_B 0x01a8 0x0434 0x0000 4 0 -#define MX6UL_PAD_NAND_READY_B__GPIO4_IO12 0x01a8 0x0434 0x0000 5 0 -#define MX6UL_PAD_NAND_READY_B__UART3_DCE_TX 0x01a8 0x0434 0x0000 8 0 -#define MX6UL_PAD_NAND_READY_B__UART3_DTE_RX 0x01a8 0x0434 0x0634 8 2 -#define MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x01ac 0x0438 0x0000 0 0 -#define MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x01ac 0x0438 0x0000 1 0 -#define MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x01ac 0x0438 0x0000 2 0 -#define MX6UL_PAD_NAND_CE0_B__ECSPI3_SCLK 0x01ac 0x0438 0x0554 3 1 -#define MX6UL_PAD_NAND_CE0_B__EIM_DTACK_B 0x01ac 0x0438 0x0000 4 0 -#define MX6UL_PAD_NAND_CE0_B__GPIO4_IO13 0x01ac 0x0438 0x0000 5 0 -#define MX6UL_PAD_NAND_CE0_B__UART3_DCE_RX 0x01ac 0x0438 0x0634 8 3 -#define MX6UL_PAD_NAND_CE0_B__UART3_DTE_TX 0x01ac 0x0438 0x0000 8 0 -#define MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B 0x01b0 0x043c 0x0000 0 0 -#define MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x01b0 0x043c 0x0000 1 0 -#define MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x01b0 0x043c 0x0000 2 0 -#define MX6UL_PAD_NAND_CE1_B__ECSPI3_MOSI 0x01b0 0x043c 0x055c 3 1 -#define MX6UL_PAD_NAND_CE1_B__EIM_ADDR18 0x01b0 0x043c 0x0000 4 0 -#define MX6UL_PAD_NAND_CE1_B__GPIO4_IO14 0x01b0 0x043c 0x0000 5 0 -#define MX6UL_PAD_NAND_CE1_B__UART3_DCE_CTS 0x01b0 0x043c 0x0000 8 0 -#define MX6UL_PAD_NAND_CE1_B__UART3_DTE_RTS 0x01b0 0x043c 0x0630 8 2 -#define MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x01b4 0x0440 0x0000 0 0 -#define MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x01b4 0x0440 0x0000 1 0 -#define MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x01b4 0x0440 0x0000 2 0 -#define MX6UL_PAD_NAND_CLE__ECSPI3_MISO 0x01b4 0x0440 0x0558 3 1 -#define MX6UL_PAD_NAND_CLE__EIM_ADDR16 0x01b4 0x0440 0x0000 4 0 -#define MX6UL_PAD_NAND_CLE__GPIO4_IO15 0x01b4 0x0440 0x0000 5 0 -#define MX6UL_PAD_NAND_CLE__UART3_DCE_RTS 0x01b4 0x0440 0x0630 8 3 -#define MX6UL_PAD_NAND_CLE__UART3_DTE_CTS 0x01b4 0x0440 0x0000 8 0 -#define MX6UL_PAD_NAND_DQS__RAWNAND_DQS 0x01b8 0x0444 0x0000 0 0 -#define MX6UL_PAD_NAND_DQS__CSI_FIELD 0x01b8 0x0444 0x0530 1 1 -#define MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x01b8 0x0444 0x0000 2 0 -#define MX6UL_PAD_NAND_DQS__PWM5_OUT 0x01b8 0x0444 0x0000 3 0 -#define MX6UL_PAD_NAND_DQS__EIM_WAIT 0x01b8 0x0444 0x0000 4 0 -#define MX6UL_PAD_NAND_DQS__GPIO4_IO16 0x01b8 0x0444 0x0000 5 0 -#define MX6UL_PAD_NAND_DQS__SDMA_EXT_EVENT01 0x01b8 0x0444 0x0614 6 1 -#define MX6UL_PAD_NAND_DQS__SPDIF_EXT_CLK 0x01b8 0x0444 0x061c 8 1 -#define MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x01bc 0x0448 0x0000 0 0 -#define MX6UL_PAD_SD1_CMD__GPT2_COMPARE1 0x01bc 0x0448 0x0000 1 0 -#define MX6UL_PAD_SD1_CMD__SAI2_RX_SYNC 0x01bc 0x0448 0x0000 2 0 -#define MX6UL_PAD_SD1_CMD__SPDIF_OUT 0x01bc 0x0448 0x0000 3 0 -#define MX6UL_PAD_SD1_CMD__EIM_ADDR19 0x01bc 0x0448 0x0000 4 0 -#define MX6UL_PAD_SD1_CMD__GPIO2_IO16 0x01bc 0x0448 0x0000 5 0 -#define MX6UL_PAD_SD1_CMD__SDMA_EXT_EVENT00 0x01bc 0x0448 0x0610 6 2 -#define MX6UL_PAD_SD1_CMD__USB_OTG1_PWR 0x01bc 0x0448 0x0000 8 0 -#define MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x01c0 0x044c 0x0000 0 0 -#define MX6UL_PAD_SD1_CLK__GPT2_COMPARE2 0x01c0 0x044c 0x0000 1 0 -#define MX6UL_PAD_SD1_CLK__SAI2_MCLK 0x01c0 0x044c 0x05f0 2 1 -#define MX6UL_PAD_SD1_CLK__SPDIF_IN 0x01c0 0x044c 0x0618 3 3 -#define MX6UL_PAD_SD1_CLK__EIM_ADDR20 0x01c0 0x044c 0x0000 4 0 -#define MX6UL_PAD_SD1_CLK__GPIO2_IO17 0x01c0 0x044c 0x0000 5 0 -#define MX6UL_PAD_SD1_CLK__USB_OTG1_OC 0x01c0 0x044c 0x0664 8 2 -#define MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x01c4 0x0450 0x0000 0 0 -#define MX6UL_PAD_SD1_DATA0__GPT2_COMPARE3 0x01c4 0x0450 0x0000 1 0 -#define MX6UL_PAD_SD1_DATA0__SAI2_TX_SYNC 0x01c4 0x0450 0x05fc 2 1 -#define MX6UL_PAD_SD1_DATA0__FLEXCAN1_TX 0x01c4 0x0450 0x0000 3 0 -#define MX6UL_PAD_SD1_DATA0__EIM_ADDR21 0x01c4 0x0450 0x0000 4 0 -#define MX6UL_PAD_SD1_DATA0__GPIO2_IO18 0x01c4 0x0450 0x0000 5 0 -#define MX6UL_PAD_SD1_DATA0__ANATOP_OTG1_ID 0x01c4 0x0450 0x04b8 8 2 -#define MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x01c8 0x0454 0x0000 0 0 -#define MX6UL_PAD_SD1_DATA1__GPT2_CLK 0x01c8 0x0454 0x05a0 1 1 -#define MX6UL_PAD_SD1_DATA1__SAI2_TX_BCLK 0x01c8 0x0454 0x05f8 2 1 -#define MX6UL_PAD_SD1_DATA1__FLEXCAN1_RX 0x01c8 0x0454 0x0584 3 3 -#define MX6UL_PAD_SD1_DATA1__EIM_ADDR22 0x01c8 0x0454 0x0000 4 0 -#define MX6UL_PAD_SD1_DATA1__GPIO2_IO19 0x01c8 0x0454 0x0000 5 0 -#define MX6UL_PAD_SD1_DATA1__USB_OTG2_PWR 0x01c8 0x0454 0x0000 8 0 -#define MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x01cc 0x0458 0x0000 0 0 -#define MX6UL_PAD_SD1_DATA2__GPT2_CAPTURE1 0x01cc 0x0458 0x0598 1 1 -#define MX6UL_PAD_SD1_DATA2__SAI2_RX_DATA 0x01cc 0x0458 0x05f4 2 1 -#define MX6UL_PAD_SD1_DATA2__FLEXCAN2_TX 0x01cc 0x0458 0x0000 3 0 -#define MX6UL_PAD_SD1_DATA2__EIM_ADDR23 0x01cc 0x0458 0x0000 4 0 -#define MX6UL_PAD_SD1_DATA2__GPIO2_IO20 0x01cc 0x0458 0x0000 5 0 -#define MX6UL_PAD_SD1_DATA2__CCM_CLKO1 0x01cc 0x0458 0x0000 6 0 -#define MX6UL_PAD_SD1_DATA2__USB_OTG2_OC 0x01cc 0x0458 0x0660 8 2 -#define MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x01d0 0x045c 0x0000 0 0 -#define MX6UL_PAD_SD1_DATA3__GPT2_CAPTURE2 0x01d0 0x045c 0x059c 1 1 -#define MX6UL_PAD_SD1_DATA3__SAI2_TX_DATA 0x01d0 0x045c 0x0000 2 0 -#define MX6UL_PAD_SD1_DATA3__FLEXCAN2_RX 0x01d0 0x045c 0x0588 3 3 -#define MX6UL_PAD_SD1_DATA3__EIM_ADDR24 0x01d0 0x045c 0x0000 4 0 -#define MX6UL_PAD_SD1_DATA3__GPIO2_IO21 0x01d0 0x045c 0x0000 5 0 -#define MX6UL_PAD_SD1_DATA3__CCM_CLKO2 0x01d0 0x045c 0x0000 6 0 -#define MX6UL_PAD_SD1_DATA3__ANATOP_OTG2_ID 0x01d0 0x045c 0x04bc 8 2 -#define MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x01d4 0x0460 0x0000 0 0 -#define MX6UL_PAD_CSI_MCLK__USDHC2_CD_B 0x01d4 0x0460 0x0674 1 0 -#define MX6UL_PAD_CSI_MCLK__RAWNAND_CE2_B 0x01d4 0x0460 0x0000 2 0 -#define MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x01d4 0x0460 0x05a8 3 0 -#define MX6UL_PAD_CSI_MCLK__EIM_CS0_B 0x01d4 0x0460 0x0000 4 0 -#define MX6UL_PAD_CSI_MCLK__GPIO4_IO17 0x01d4 0x0460 0x0000 5 0 -#define MX6UL_PAD_CSI_MCLK__SNVS_HP_VIO_5_CTL 0x01d4 0x0460 0x0000 6 0 -#define MX6UL_PAD_CSI_MCLK__UART6_DCE_TX 0x01d4 0x0460 0x0000 8 0 -#define MX6UL_PAD_CSI_MCLK__UART6_DTE_RX 0x01d4 0x0460 0x064c 8 0 -#define MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x01d8 0x0464 0x0528 0 1 -#define MX6UL_PAD_CSI_PIXCLK__USDHC2_WP 0x01d8 0x0464 0x069c 1 2 -#define MX6UL_PAD_CSI_PIXCLK__RAWNAND_CE3_B 0x01d8 0x0464 0x0000 2 0 -#define MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x01d8 0x0464 0x05a4 3 2 -#define MX6UL_PAD_CSI_PIXCLK__EIM_OE 0x01d8 0x0464 0x0000 4 0 -#define MX6UL_PAD_CSI_PIXCLK__GPIO4_IO18 0x01d8 0x0464 0x0000 5 0 -#define MX6UL_PAD_CSI_PIXCLK__SNVS_HP_VIO_5 0x01d8 0x0464 0x0000 6 0 -#define MX6UL_PAD_CSI_PIXCLK__UART6_DCE_RX 0x01d8 0x0464 0x064c 8 3 -#define MX6UL_PAD_CSI_PIXCLK__UART6_DTE_TX 0x01d8 0x0464 0x0000 8 0 -#define MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x01dc 0x0468 0x052c 0 0 -#define MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x01dc 0x0468 0x0670 1 0 -#define MX6UL_PAD_CSI_VSYNC__SIM1_PORT1_CLK 0x01dc 0x0468 0x0000 2 0 -#define MX6UL_PAD_CSI_VSYNC__I2C2_SDA 0x01dc 0x0468 0x05b0 3 0 -#define MX6UL_PAD_CSI_VSYNC__EIM_RW 0x01dc 0x0468 0x0000 4 0 -#define MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x01dc 0x0468 0x0000 5 0 -#define MX6UL_PAD_CSI_VSYNC__PWM7_OUT 0x01dc 0x0468 0x0000 6 0 -#define MX6UL_PAD_CSI_VSYNC__UART6_DCE_RTS 0x01dc 0x0468 0x0648 8 0 -#define MX6UL_PAD_CSI_VSYNC__UART6_DTE_CTS 0x01dc 0x0468 0x0000 8 0 -#define MX6UL_PAD_CSI_HSYNC__CSI_HSYNC 0x01e0 0x046c 0x0524 0 0 -#define MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x01e0 0x046c 0x0678 1 0 -#define MX6UL_PAD_CSI_HSYNC__SIM1_PORT1_PD 0x01e0 0x046c 0x0000 2 0 -#define MX6UL_PAD_CSI_HSYNC__I2C2_SCL 0x01e0 0x046c 0x05ac 3 0 -#define MX6UL_PAD_CSI_HSYNC__EIM_LBA_B 0x01e0 0x046c 0x0000 4 0 -#define MX6UL_PAD_CSI_HSYNC__GPIO4_IO20 0x01e0 0x046c 0x0000 5 0 -#define MX6UL_PAD_CSI_HSYNC__PWM8_OUT 0x01e0 0x046c 0x0000 6 0 -#define MX6UL_PAD_CSI_HSYNC__UART6_DCE_CTS 0x01e0 0x046c 0x0000 8 0 -#define MX6UL_PAD_CSI_HSYNC__UART6_DTE_RTS 0x01e0 0x046c 0x0648 8 1 -#define MX6UL_PAD_CSI_DATA00__CSI_DATA02 0x01e4 0x0470 0x04c4 0 0 -#define MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x01e4 0x0470 0x067c 1 0 -#define MX6UL_PAD_CSI_DATA00__SIM1_PORT1_RST_B 0x01e4 0x0470 0x0000 2 0 -#define MX6UL_PAD_CSI_DATA00__ECSPI2_SCLK 0x01e4 0x0470 0x0544 3 0 -#define MX6UL_PAD_CSI_DATA00__EIM_AD00 0x01e4 0x0470 0x0000 4 0 -#define MX6UL_PAD_CSI_DATA00__GPIO4_IO21 0x01e4 0x0470 0x0000 5 0 -#define MX6UL_PAD_CSI_DATA00__SRC_INT_BOOT 0x01e4 0x0470 0x0000 6 0 -#define MX6UL_PAD_CSI_DATA00__UART5_DCE_TX 0x01e4 0x0470 0x0000 8 0 -#define MX6UL_PAD_CSI_DATA00__UART5_DTE_RX 0x01e4 0x0470 0x0644 8 0 -#define MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x01e8 0x0474 0x04c8 0 0 -#define MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x01e8 0x0474 0x0680 1 0 -#define MX6UL_PAD_CSI_DATA01__SIM1_PORT1_SVEN 0x01e8 0x0474 0x0000 2 0 -#define MX6UL_PAD_CSI_DATA01__ECSPI2_SS0 0x01e8 0x0474 0x0550 3 0 -#define MX6UL_PAD_CSI_DATA01__EIM_AD01 0x01e8 0x0474 0x0000 4 0 -#define MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x01e8 0x0474 0x0000 5 0 -#define MX6UL_PAD_CSI_DATA01__SAI1_MCLK 0x01e8 0x0474 0x05e0 6 0 -#define MX6UL_PAD_CSI_DATA01__UART5_DCE_RX 0x01e8 0x0474 0x0644 8 1 -#define MX6UL_PAD_CSI_DATA01__UART5_DTE_TX 0x01e8 0x0474 0x0000 8 0 -#define MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x01ec 0x0478 0x04d8 0 1 -#define MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x01ec 0x0478 0x0684 1 2 -#define MX6UL_PAD_CSI_DATA02__SIM1_PORT1_TRXD 0x01ec 0x0478 0x0000 2 0 -#define MX6UL_PAD_CSI_DATA02__ECSPI2_MOSI 0x01ec 0x0478 0x054c 3 1 -#define MX6UL_PAD_CSI_DATA02__EIM_AD02 0x01ec 0x0478 0x0000 4 0 -#define MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x01ec 0x0478 0x0000 5 0 -#define MX6UL_PAD_CSI_DATA02__SAI1_RX_SYNC 0x01ec 0x0478 0x0000 6 0 -#define MX6UL_PAD_CSI_DATA02__UART5_DCE_RTS 0x01ec 0x0478 0x0640 8 5 -#define MX6UL_PAD_CSI_DATA02__UART5_DTE_CTS 0x01ec 0x0478 0x0000 8 0 -#define MX6UL_PAD_CSI_DATA03__CSI_DATA05 0x01f0 0x047c 0x04cc 0 0 -#define MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x01f0 0x047c 0x0688 1 0 -#define MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD 0x01f0 0x047c 0x0000 2 0 -#define MX6UL_PAD_CSI_DATA03__ECSPI2_MISO 0x01f0 0x047c 0x0548 3 0 -#define MX6UL_PAD_CSI_DATA03__EIM_AD03 0x01f0 0x047c 0x0000 4 0 -#define MX6UL_PAD_CSI_DATA03__GPIO4_IO24 0x01f0 0x047c 0x0000 5 0 -#define MX6UL_PAD_CSI_DATA03__SAI1_RX_BCLK 0x01f0 0x047c 0x0000 6 0 -#define MX6UL_PAD_CSI_DATA03__UART5_DCE_CTS 0x01f0 0x047c 0x0000 8 0 -#define MX6UL_PAD_CSI_DATA03__UART5_DTE_RTS 0x01f0 0x047c 0x0640 8 0 -#define MX6UL_PAD_CSI_DATA04__CSI_DATA06 0x01f4 0x0480 0x04dc 0 1 -#define MX6UL_PAD_CSI_DATA04__USDHC2_DATA4 0x01f4 0x0480 0x068c 1 2 -#define MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK 0x01f4 0x0480 0x0000 2 0 -#define MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK 0x01f4 0x0480 0x0534 3 1 -#define MX6UL_PAD_CSI_DATA04__EIM_AD04 0x01f4 0x0480 0x0000 4 0 -#define MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x01f4 0x0480 0x0000 5 0 -#define MX6UL_PAD_CSI_DATA04__SAI1_TX_SYNC 0x01f4 0x0480 0x05ec 6 1 -#define MX6UL_PAD_CSI_DATA04__USDHC1_WP 0x01f4 0x0480 0x066c 8 2 -#define MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x01f8 0x0484 0x04e0 0 1 -#define MX6UL_PAD_CSI_DATA05__USDHC2_DATA5 0x01f8 0x0484 0x0690 1 2 -#define MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B 0x01f8 0x0484 0x0000 2 0 -#define MX6UL_PAD_CSI_DATA05__ECSPI1_SS0 0x01f8 0x0484 0x0540 3 1 -#define MX6UL_PAD_CSI_DATA05__EIM_AD05 0x01f8 0x0484 0x0000 4 0 -#define MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x01f8 0x0484 0x0000 5 0 -#define MX6UL_PAD_CSI_DATA05__SAI1_TX_BCLK 0x01f8 0x0484 0x05e8 6 1 -#define MX6UL_PAD_CSI_DATA05__USDHC1_CD_B 0x01f8 0x0484 0x0668 8 2 -#define MX6UL_PAD_CSI_DATA06__CSI_DATA08 0x01fc 0x0488 0x04e4 0 1 -#define MX6UL_PAD_CSI_DATA06__USDHC2_DATA6 0x01fc 0x0488 0x0694 1 2 -#define MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN 0x01fc 0x0488 0x0000 2 0 -#define MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI 0x01fc 0x0488 0x053c 3 1 -#define MX6UL_PAD_CSI_DATA06__EIM_AD06 0x01fc 0x0488 0x0000 4 0 -#define MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x01fc 0x0488 0x0000 5 0 -#define MX6UL_PAD_CSI_DATA06__SAI1_RX_DATA 0x01fc 0x0488 0x05e4 6 1 -#define MX6UL_PAD_CSI_DATA06__USDHC1_RESET_B 0x01fc 0x0488 0x0000 8 0 -#define MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x0200 0x048c 0x04e8 0 1 -#define MX6UL_PAD_CSI_DATA07__USDHC2_DATA7 0x0200 0x048c 0x0698 1 2 -#define MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD 0x0200 0x048c 0x0000 2 0 -#define MX6UL_PAD_CSI_DATA07__ECSPI1_MISO 0x0200 0x048c 0x0538 3 1 -#define MX6UL_PAD_CSI_DATA07__EIM_AD07 0x0200 0x048c 0x0000 4 0 -#define MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x0200 0x048c 0x0000 5 0 -#define MX6UL_PAD_CSI_DATA07__SAI1_TX_DATA 0x0200 0x048c 0x0000 6 0 -#define MX6UL_PAD_CSI_DATA07__USDHC1_VSELECT 0x0200 0x048c 0x0000 8 0 - -#endif /* __DTS_IMX6UL_PINFUNC_H */ diff --git a/sys/gnu/dts/arm/imx6ul-tx6ul-0010.dts b/sys/gnu/dts/arm/imx6ul-tx6ul-0010.dts deleted file mode 100644 index 8c2f3df79b4..00000000000 --- a/sys/gnu/dts/arm/imx6ul-tx6ul-0010.dts +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright 2015 Lothar Waßmann - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6ul.dtsi" -#include "imx6ul-tx6ul.dtsi" - -/ { - model = "Ka-Ro electronics TXUL-0010 Module"; - compatible = "karo,imx6ul-tx6ul", "fsl,imx6ul"; - - aliases { - /delete-property/ mmc1; - }; -}; diff --git a/sys/gnu/dts/arm/imx6ul-tx6ul-0011.dts b/sys/gnu/dts/arm/imx6ul-tx6ul-0011.dts deleted file mode 100644 index d82698e7d50..00000000000 --- a/sys/gnu/dts/arm/imx6ul-tx6ul-0011.dts +++ /dev/null @@ -1,68 +0,0 @@ -/* - * Copyright 2015 Lothar Waßmann - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6ul.dtsi" -#include "imx6ul-tx6ul.dtsi" - -/ { - model = "Ka-Ro electronics TXUL-0011 Module"; - compatible = "karo,imx6ul-tx6ul", "fsl,imx6ul"; - - aliases { - mmc0 = &usdhc2; - mmc1 = &usdhc1; - }; -}; - -&gpmi { - status = "disabled"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - bus-width = <4>; - no-1-8-v; - non-removable; - fsl,wp-controller; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx6ul-tx6ul-mainboard.dts b/sys/gnu/dts/arm/imx6ul-tx6ul-mainboard.dts deleted file mode 100644 index 97686097a86..00000000000 --- a/sys/gnu/dts/arm/imx6ul-tx6ul-mainboard.dts +++ /dev/null @@ -1,271 +0,0 @@ -/* - * Copyright 2015 Lothar Waßmann - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6ul.dtsi" -#include "imx6ul-tx6ul.dtsi" - -/ { - model = "Ka-Ro electronics TXUL-0010 Module on TXUL Mainboard"; - compatible = "karo,imx6ul-tx6ul", "fsl,imx6ul"; - - aliases { - lcdif-24bit-pins-a = &pinctrl_disp0_3; - mmc0 = &usdhc1; - /delete-property/ mmc1; - serial2 = &uart3; - serial4 = &uart5; - }; - /delete-node/ sound; -}; - -&can1 { - xceiver-supply = <®_3v3>; -}; - -&can2 { - xceiver-supply = <®_3v3>; -}; - -&ds1339 { - status = "disabled"; -}; - -&fec1 { - pinctrl-0 = <&pinctrl_enet1 &pinctrl_etnphy0_rst>; - /delete-node/ mdio; -}; - -&fec2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_mdio &pinctrl_etnphy1_rst>; - phy-mode = "rmii"; - phy-reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; - phy-supply = <®_3v3_etn>; - phy-handle = <&etnphy1>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - etnphy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_etnphy0_int>; - interrupt-parent = <&gpio5>; - interrupts = <5 IRQ_TYPE_EDGE_FALLING>; - interrupts-extended = <&gpio5 5 IRQ_TYPE_EDGE_FALLING>; - status = "okay"; - }; - - etnphy1: ethernet-phy@2 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_etnphy1_int>; - interrupt-parent = <&gpio4>; - interrupts = <27 IRQ_TYPE_EDGE_FALLING>; - interrupts-extended = <&gpio4 27 IRQ_TYPE_EDGE_FALLING>; - status = "okay"; - }; - }; -}; - -&i2c_gpio { - status = "disabled"; -}; - -&i2c2 { - /delete-node/ codec@a; - /delete-node/ touchscreen@48; - - rtc: mcp7940x@6f { - compatible = "microchip,mcp7940x"; - reg = <0x6f>; - }; -}; - -&kpp { - status = "disabled"; -}; - -&lcdif { - pinctrl-0 = <&pinctrl_disp0_3>; -}; - -®_usbotg_vbus{ - status = "disabled"; -}; - -&usdhc1 { - pinctrl-0 = <&pinctrl_usdhc1>; - non-removable; - /delete-property/ cd-gpios; - cap-sdio-irq; -}; - -&uart1 { - pinctrl-0 = <&pinctrl_uart1>; - /delete-property/ uart-has-rtscts; -}; - -&uart2 { - pinctrl-0 = <&pinctrl_uart2>; - /delete-property/ uart-has-rtscts; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - status = "okay"; -}; - -&uart6 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart6>; - status = "okay"; -}; - -&uart7 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart7>; - status = "okay"; -}; - -&uart8 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart8>; - status = "disabled"; /* conflicts with LCDIF */ -}; - -&iomuxc { - hoggrp { - fsl,pins = < - MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x0b0b0 /* WLAN_RESET */ - >; - }; - - pinctrl_disp0_3: disp0grp-3 { - fsl,pins = < - MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x10 /* LSCLK */ - MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x10 /* OE_ACD */ - MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x10 /* HSYNC */ - MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x10 /* VSYNC */ - MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x10 - MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x10 - MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x10 - MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x10 - MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x10 - MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x10 - /* LCD_DATA08..09 not wired */ - MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x10 - MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x10 - MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x10 - MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x10 - MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x10 - MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x10 - /* LCD_DATA16..17 not wired */ - MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x10 - MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x10 - MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x10 - MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x10 - MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x10 - MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x10 - >; - }; - - pinctrl_enet2_mdio: enet2-mdiogrp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x0b0b0 - MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x0b0b0 - MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x0b0b0 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x0b0b0 - MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x0b0b0 - >; - }; - - pinctrl_uart6: uart6grp { - fsl,pins = < - MX6UL_PAD_CSI_MCLK__UART6_DCE_TX 0x0b0b0 - MX6UL_PAD_CSI_PIXCLK__UART6_DCE_RX 0x0b0b0 - >; - }; - - pinctrl_uart7: uart7grp { - fsl,pins = < - MX6UL_PAD_LCD_DATA16__UART7_DCE_TX 0x0b0b0 - MX6UL_PAD_LCD_DATA17__UART7_DCE_RX 0x0b0b0 - >; - }; - - pinctrl_uart8: uart8grp { - fsl,pins = < - MX6UL_PAD_LCD_DATA20__UART8_DCE_TX 0x0b0b0 - MX6UL_PAD_LCD_DATA21__UART8_DCE_RX 0x0b0b0 - >; - }; -}; diff --git a/sys/gnu/dts/arm/imx6ul-tx6ul.dtsi b/sys/gnu/dts/arm/imx6ul-tx6ul.dtsi deleted file mode 100644 index bb6dbfd5546..00000000000 --- a/sys/gnu/dts/arm/imx6ul-tx6ul.dtsi +++ /dev/null @@ -1,972 +0,0 @@ -/* - * Copyright 2015 Lothar Waßmann - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include -#include -#include - -/ { - aliases { - can0 = &can2; - can1 = &can1; - display = &display; - i2c0 = &i2c2; - i2c1 = &i2c_gpio; - i2c2 = &i2c1; - i2c3 = &i2c3; - i2c4 = &i2c4; - lcdif-23bit-pins-a = &pinctrl_disp0_1; - lcdif-24bit-pins-a = &pinctrl_disp0_2; - pwm0 = &pwm5; - reg-can-xcvr = ®_can_xcvr; - serial2 = &uart5; - serial4 = &uart3; - spi0 = &ecspi2; - spi1 = &spi_gpio; - stk5led = &user_led; - usbh1 = &usbotg2; - usbotg = &usbotg1; - }; - - chosen { - stdout-path = &uart1; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0>; /* will be filled by U-Boot */ - }; - - clocks { - mclk: mclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <26000000>; - }; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd_rst>; - enable-gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>; - pwms = <&pwm5 0 500000 PWM_POLARITY_INVERTED>; - power-supply = <®_lcd_pwr>; - /* - * a poor man's way to create a 1:1 relationship between - * the PWM value and the actual duty cycle - */ - brightness-levels = < 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100>; - default-brightness-level = <50>; - }; - - i2c_gpio: i2c-gpio { - compatible = "i2c-gpio"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c_gpio>; - gpios = < - &gpio5 1 GPIO_ACTIVE_HIGH /* SDA */ - &gpio5 0 GPIO_ACTIVE_HIGH /* SCL */ - >; - clock-frequency = <400000>; - status = "okay"; - - ds1339: rtc@68 { - compatible = "dallas,ds1339"; - reg = <0x68>; - status = "disabled"; - }; - }; - - leds { - compatible = "gpio-leds"; - - user_led: user { - label = "Heartbeat"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_led>; - gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - reg_3v3_etn: regulator-3v3etn { - compatible = "regulator-fixed"; - regulator-name = "3V3_ETN"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_etnphy_power>; - gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_2v5: regulator-2v5 { - compatible = "regulator-fixed"; - regulator-name = "2V5"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - reg_3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_can_xcvr: regulator-canxcvr { - compatible = "regulator-fixed"; - regulator-name = "CAN XCVR"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan_xcvr>; - gpio = <&gpio3 5 GPIO_ACTIVE_LOW>; - }; - - reg_lcd_pwr: regulator-lcdpwr { - compatible = "regulator-fixed"; - regulator-name = "LCD POWER"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd_pwr>; - gpio = <&gpio5 4 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-boot-on; - regulator-always-on; - }; - - reg_usbh1_vbus: regulator-usbh1vbus { - compatible = "regulator-fixed"; - regulator-name = "usbh1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh1_vbus &pinctrl_usbh1_oc>; - gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usbotg_vbus: regulator-usbotgvbus { - compatible = "regulator-fixed"; - regulator-name = "usbotg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg_vbus &pinctrl_usbotg_oc>; - gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - spi_gpio: spi-gpio { - #address-cells = <1>; - #size-cells = <0>; - compatible = "spi-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi_gpio>; - gpio-mosi = <&gpio1 30 GPIO_ACTIVE_HIGH>; - gpio-miso = <&gpio1 31 GPIO_ACTIVE_HIGH>; - gpio-sck = <&gpio1 28 GPIO_ACTIVE_HIGH>; - num-chipselects = <2>; - cs-gpios = < - &gpio1 29 GPIO_ACTIVE_HIGH - &gpio1 10 GPIO_ACTIVE_HIGH - >; - status = "disabled"; - - spi@0 { - compatible = "spidev"; - reg = <0>; - spi-max-frequency = <660000>; - }; - - spi@1 { - compatible = "spidev"; - reg = <1>; - spi-max-frequency = <660000>; - }; - }; - - sound { - compatible = "karo,imx6ul-tx6ul-sgtl5000", - "simple-audio-card"; - simple-audio-card,name = "imx6ul-tx6ul-sgtl5000-audio"; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&codec_dai>; - simple-audio-card,frame-master = <&codec_dai>; - simple-audio-card,widgets = - "Microphone", "Mic Jack", - "Line", "Line In", - "Line", "Line Out", - "Headphone", "Headphone Jack"; - simple-audio-card,routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - - cpu_dai: simple-audio-card,cpu { - sound-dai = <&sai2>; - }; - - codec_dai: simple-audio-card,codec { - sound-dai = <&sgtl5000>; - }; - }; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - xceiver-supply = <®_can_xcvr>; - status = "okay"; -}; - -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - xceiver-supply = <®_can_xcvr>; - status = "okay"; -}; - -&ecspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi2>; - cs-gpios = < - &gpio1 29 GPIO_ACTIVE_HIGH - &gpio1 10 GPIO_ACTIVE_HIGH - >; - status = "disabled"; - - spidev0: spi@0 { - compatible = "spidev"; - reg = <0>; - spi-max-frequency = <60000000>; - }; - - spidev1: spi@1 { - compatible = "spidev"; - reg = <1>; - spi-max-frequency = <60000000>; - }; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet1 &pinctrl_enet1_mdio &pinctrl_etnphy0_rst>; - phy-mode = "rmii"; - phy-reset-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>; - phy-supply = <®_3v3_etn>; - phy-handle = <&etnphy0>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - etnphy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_etnphy0_int>; - interrupt-parent = <&gpio5>; - interrupts = <5 IRQ_TYPE_EDGE_FALLING>; - status = "okay"; - }; - - etnphy1: ethernet-phy@2 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_etnphy1_int>; - interrupt-parent = <&gpio4>; - interrupts = <27 IRQ_TYPE_EDGE_FALLING>; - status = "okay"; - }; - }; -}; - -&fec2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet2 &pinctrl_etnphy1_rst>; - phy-mode = "rmii"; - phy-reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; - phy-supply = <®_3v3_etn>; - phy-handle = <&etnphy1>; - status = "disabled"; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - nand-on-flash-bbt; - fsl,no-blockmark-swap; - status = "okay"; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - clock-frequency = <400000>; - status = "okay"; - - sgtl5000: codec@a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - #sound-dai-cells = <0>; - VDDA-supply = <®_2v5>; - VDDIO-supply = <®_3v3>; - clocks = <&mclk>; - }; - - polytouch: polytouch@38 { - compatible = "edt,edt-ft5x06"; - reg = <0x38>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_edt_ft5x06>; - interrupt-parent = <&gpio5>; - interrupts = <2 IRQ_TYPE_EDGE_FALLING>; - reset-gpios = <&gpio5 3 GPIO_ACTIVE_LOW>; - wake-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>; - wakeup-source; - }; - - touchscreen: touchscreen@48 { - compatible = "ti,tsc2007"; - reg = <0x48>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_tsc2007>; - interrupt-parent = <&gpio3>; - interrupts = <26 IRQ_TYPE_NONE>; - gpios = <&gpio3 26 GPIO_ACTIVE_LOW>; - ti,x-plate-ohms = <660>; - wakeup-source; - }; -}; - -&kpp { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_kpp>; - /* sample keymap */ - /* row/col 0..3 are mapped to KPP row/col 4..7 */ - linux,keymap = < - MATRIX_KEY(4, 4, KEY_POWER) - MATRIX_KEY(4, 5, KEY_KP0) - MATRIX_KEY(4, 6, KEY_KP1) - MATRIX_KEY(4, 7, KEY_KP2) - MATRIX_KEY(5, 4, KEY_KP3) - MATRIX_KEY(5, 5, KEY_KP4) - MATRIX_KEY(5, 6, KEY_KP5) - MATRIX_KEY(5, 7, KEY_KP6) - MATRIX_KEY(6, 4, KEY_KP7) - MATRIX_KEY(6, 5, KEY_KP8) - MATRIX_KEY(6, 6, KEY_KP9) - >; - status = "okay"; -}; - -&lcdif { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_disp0_1>; - lcd-supply = <®_lcd_pwr>; - display = <&display>; - status = "okay"; - - display: disp0 { - bits-per-pixel = <32>; - bus-width = <24>; - status = "okay"; - - display-timings { - VGA { - clock-frequency = <25200000>; - hactive = <640>; - vactive = <480>; - hback-porch = <48>; - hsync-len = <96>; - hfront-porch = <16>; - vback-porch = <31>; - vsync-len = <2>; - vfront-porch = <12>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - - ETV570 { - clock-frequency = <25200000>; - hactive = <640>; - vactive = <480>; - hback-porch = <114>; - hsync-len = <30>; - hfront-porch = <16>; - vback-porch = <32>; - vsync-len = <3>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - - ET0350 { - clock-frequency = <6413760>; - hactive = <320>; - vactive = <240>; - hback-porch = <34>; - hsync-len = <34>; - hfront-porch = <20>; - vback-porch = <15>; - vsync-len = <3>; - vfront-porch = <4>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - - ET0430 { - clock-frequency = <9009000>; - hactive = <480>; - vactive = <272>; - hback-porch = <2>; - hsync-len = <41>; - hfront-porch = <2>; - vback-porch = <2>; - vsync-len = <10>; - vfront-porch = <2>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ET0500 { - clock-frequency = <33264000>; - hactive = <800>; - vactive = <480>; - hback-porch = <88>; - hsync-len = <128>; - hfront-porch = <40>; - vback-porch = <33>; - vsync-len = <2>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - - ET0700 { /* same as ET0500 */ - clock-frequency = <33264000>; - hactive = <800>; - vactive = <480>; - hback-porch = <88>; - hsync-len = <128>; - hfront-porch = <40>; - vback-porch = <33>; - vsync-len = <2>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - - ETQ570 { - clock-frequency = <6596040>; - hactive = <320>; - vactive = <240>; - hback-porch = <38>; - hsync-len = <30>; - hfront-porch = <30>; - vback-porch = <16>; - vsync-len = <3>; - vfront-porch = <4>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - }; -}; - -&pwm5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm5>; - #pwm-cells = <3>; - status = "okay"; -}; - -&sai2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai2>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_rtscts>; - uart-has-rtscts; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2 &pinctrl_uart2_rtscts>; - uart-has-rtscts; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5 &pinctrl_uart5_rtscts>; - uart-has-rtscts; - status = "okay"; -}; - -&usbotg1 { - vbus-supply = <®_usbotg_vbus>; - dr_mode = "peripheral"; - disable-over-current; - status = "okay"; -}; - -&usbotg2 { - vbus-supply = <®_usbh1_vbus>; - dr_mode = "host"; - disable-over-current; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_usdhc1_cd>; - bus-width = <4>; - no-1-8-v; - cd-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>; - fsl,wp-controller; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_hog: hoggrp { - }; - - pinctrl_led: ledgrp { - fsl,pins = < - MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x0b0b0 /* LED */ - >; - }; - - pinctrl_disp0_1: disp0grp-1 { - fsl,pins = < - MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x10 /* LSCLK */ - MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x10 /* OE_ACD */ - MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x10 /* HSYNC */ - MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x10 /* VSYNC */ - /* PAD DISP0_DAT0 is used for the Flexcan transceiver control on STK5-v5 */ - MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x10 - MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x10 - MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x10 - MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x10 - MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x10 - MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x10 - MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x10 - MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x10 - MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x10 - MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x10 - MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x10 - MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x10 - MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x10 - MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x10 - MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x10 - MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x10 - MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x10 - MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x10 - MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x10 - MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x10 - MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x10 - MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x10 - MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x10 - >; - }; - - pinctrl_disp0_2: disp0grp-2 { - fsl,pins = < - MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x10 /* LSCLK */ - MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x10 /* OE_ACD */ - MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x10 /* HSYNC */ - MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x10 /* VSYNC */ - MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x10 - MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x10 - MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x10 - MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x10 - MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x10 - MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x10 - MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x10 - MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x10 - MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x10 - MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x10 - MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x10 - MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x10 - MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x10 - MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x10 - MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x10 - MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x10 - MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x10 - MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x10 - MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x10 - MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x10 - MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x10 - MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x10 - MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x10 - MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x10 - >; - }; - - pinctrl_ecspi2: ecspi2grp { - fsl,pins = < - MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x0b0b0 /* CSPI_SS */ - MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x0b0b0 /* CSPI_SS */ - MX6UL_PAD_UART5_TX_DATA__ECSPI2_MOSI 0x0b0b0 /* CSPI_MOSI */ - MX6UL_PAD_UART5_RX_DATA__ECSPI2_MISO 0x0b0b0 /* CSPI_MISO */ - MX6UL_PAD_UART4_TX_DATA__ECSPI2_SCLK 0x0b0b0 /* CSPI_SCLK */ - >; - }; - - pinctrl_edt_ft5x06: edt-ft5x06grp { - fsl,pins = < - MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 /* Interrupt */ - MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x1b0b0 /* Reset */ - MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x1b0b0 /* Wake */ - >; - }; - - pinctrl_enet1: enet1grp { - fsl,pins = < - MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x000b0 - MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x000b0 - MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x000b0 - MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x000b0 - MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x000b0 - MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x000b0 - MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x000b0 - MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x400000b1 - >; - }; - - pinctrl_enet2: enet2grp { - fsl,pins = < - MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x000b0 - MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x000b0 - MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x000b0 - MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x000b0 - MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x000b0 - MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x000b0 - MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x000b0 - MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x400000b1 - >; - }; - - pinctrl_enet1_mdio: enet1-mdiogrp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x0b0b0 - MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 - >; - }; - - pinctrl_etnphy_power: etnphy-pwrgrp { - fsl,pins = < - MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0b0b0 /* ETN PHY POWER */ - >; - }; - - pinctrl_etnphy0_int: etnphy-intgrp-0 { - fsl,pins = < - MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0b0b0 /* ETN PHY INT */ - >; - }; - - pinctrl_etnphy0_rst: etnphy-rstgrp-0 { - fsl,pins = < - MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0b0b0 /* ETN PHY RESET */ - >; - }; - - pinctrl_etnphy1_int: etnphy-intgrp-1 { - fsl,pins = < - MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x0b0b0 /* ETN PHY INT */ - >; - }; - - pinctrl_etnphy1_rst: etnphy-rstgrp-1 { - fsl,pins = < - MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x0b0b0 /* ETN PHY RESET */ - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x0b0b0 - MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x0b0b0 - >; - }; - - pinctrl_flexcan2: flexcan2grp { - fsl,pins = < - MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x0b0b0 - MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x0b0b0 - >; - }; - - pinctrl_flexcan_xcvr: flexcan-xcvrgrp { - fsl,pins = < - MX6UL_PAD_LCD_DATA00__GPIO3_IO05 0x0b0b0 /* Flexcan XCVR enable */ - >; - }; - - pinctrl_gpmi_nand: gpminandgrp { - fsl,pins = < - MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x0b0b1 - MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x0b0b1 - MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x0b0b1 - MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000 - MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0b0b1 - MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0b0b1 - MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x0b0b1 - MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0b0b1 - MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0b0b1 - MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0b0b1 - MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x0b0b1 - MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0b0b1 - MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0b0b1 - MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0b0b1 - MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x0b0b1 - >; - }; - - pinctrl_i2c_gpio: i2c-gpiogrp { - fsl,pins = < - MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x4001b8b1 /* I2C SCL */ - MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x4001b8b1 /* I2C SDA */ - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO00__I2C2_SCL 0x4001b8b1 - MX6UL_PAD_GPIO1_IO01__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_kpp: kppgrp { - fsl,pins = < - MX6UL_PAD_ENET2_RX_DATA1__KPP_COL04 0x1b0b0 - MX6UL_PAD_ENET2_TX_DATA0__KPP_COL05 0x1b0b0 - MX6UL_PAD_ENET2_TX_EN__KPP_COL06 0x1b0b0 - MX6UL_PAD_ENET2_RX_ER__KPP_COL07 0x1b0b0 - MX6UL_PAD_ENET2_RX_DATA0__KPP_ROW04 0x1b0b0 - MX6UL_PAD_ENET2_RX_EN__KPP_ROW05 0x1b0b0 - MX6UL_PAD_ENET2_TX_DATA1__KPP_ROW06 0x1b0b0 - MX6UL_PAD_ENET2_TX_CLK__KPP_ROW07 0x1b0b0 - >; - }; - - pinctrl_lcd_pwr: lcd-pwrgrp { - fsl,pins = < - MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x0b0b0 /* LCD Power Enable */ - >; - }; - - pinctrl_lcd_rst: lcd-rstgrp { - fsl,pins = < - MX6UL_PAD_LCD_RESET__GPIO3_IO04 0x0b0b0 /* LCD Reset */ - >; - }; - - pinctrl_pwm5: pwm5grp { - fsl,pins = < - MX6UL_PAD_NAND_DQS__PWM5_OUT 0x0b0b0 - >; - }; - - pinctrl_sai2: sai2grp { - fsl,pins = < - MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x0b0b0 /* SSI1_RXD */ - MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x0b0b0 /* SSI1_TXD */ - MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x0b0b0 /* SSI1_CLK */ - MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x0b0b0 /* SSI1_FS */ - >; - }; - - pinctrl_spi_gpio: spi-gpiogrp { - fsl,pins = < - MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x0b0b0 /* CSPI_SS */ - MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x0b0b0 /* CSPI_SS */ - MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x0b0b0 /* CSPI_MOSI */ - MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x0b0b0 /* CSPI_MISO */ - MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x0b0b0 /* CSPI_SCLK */ - >; - }; - - pinctrl_tsc2007: tsc2007grp { - fsl,pins = < - MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x1b0b0 /* Interrupt */ - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x0b0b0 - MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x0b0b0 - >; - }; - - pinctrl_uart1_rtscts: uart1-rtsctsgrp { - fsl,pins = < - MX6UL_PAD_UART1_RTS_B__UART1_DCE_RTS 0x0b0b0 - MX6UL_PAD_UART1_CTS_B__UART1_DCE_CTS 0x0b0b0 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x0b0b0 - MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x0b0b0 - >; - }; - - pinctrl_uart2_rtscts: uart2-rtsctsgrp { - fsl,pins = < - MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x0b0b0 - MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x0b0b0 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO04__UART5_DCE_TX 0x0b0b0 - MX6UL_PAD_GPIO1_IO05__UART5_DCE_RX 0x0b0b0 - >; - }; - - pinctrl_uart5_rtscts: uart5-rtsctsgrp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x0b0b0 - MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x0b0b0 - >; - }; - - pinctrl_usbh1_oc: usbh1-ocgrp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x17059 /* USBH1_OC */ - >; - }; - - pinctrl_usbh1_vbus: usbh1-vbusgrp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x0b0b0 /* USBH1_VBUSEN */ - >; - }; - - pinctrl_usbotg_oc: usbotg-ocgrp { - fsl,pins = < - MX6UL_PAD_UART3_RTS_B__GPIO1_IO27 0x17059 /* USBOTG_OC */ - >; - }; - - pinctrl_usbotg_vbus: usbotg-vbusgrp { - fsl,pins = < - MX6UL_PAD_UART3_CTS_B__GPIO1_IO26 0x1b0b0 /* USBOTG_VBUSEN */ - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x070b1 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x07099 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x070b1 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x070b1 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x070b1 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x070b1 - >; - }; - - pinctrl_usdhc1_cd: usdhc1cdgrp { - fsl,pins = < - MX6UL_PAD_NAND_CE1_B__GPIO4_IO14 0x170b0 /* SD1 CD */ - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x070b1 - MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x070b1 - MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x070b1 - MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x070b1 - MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x070b1 - MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x070b1 - /* eMMC RESET */ - MX6UL_PAD_NAND_ALE__USDHC2_RESET_B 0x170b0 - >; - }; -}; diff --git a/sys/gnu/dts/arm/imx6ul.dtsi b/sys/gnu/dts/arm/imx6ul.dtsi deleted file mode 100644 index d9fdca12819..00000000000 --- a/sys/gnu/dts/arm/imx6ul.dtsi +++ /dev/null @@ -1,1084 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// -// Copyright 2015 Freescale Semiconductor, Inc. - -#include -#include -#include -#include -#include "imx6ul-pinfunc.h" - -/ { - #address-cells = <1>; - #size-cells = <1>; - /* - * The decompressor and also some bootloaders rely on a - * pre-existing /chosen node to be available to insert the - * command line and merge other ATAGS info. - */ - chosen {}; - - aliases { - ethernet0 = &fec1; - ethernet1 = &fec2; - gpio0 = &gpio1; - gpio1 = &gpio2; - gpio2 = &gpio3; - gpio3 = &gpio4; - gpio4 = &gpio5; - i2c0 = &i2c1; - i2c1 = &i2c2; - i2c2 = &i2c3; - i2c3 = &i2c4; - mmc0 = &usdhc1; - mmc1 = &usdhc2; - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - serial3 = &uart4; - serial4 = &uart5; - serial5 = &uart6; - serial6 = &uart7; - serial7 = &uart8; - sai1 = &sai1; - sai2 = &sai2; - sai3 = &sai3; - spi0 = &ecspi1; - spi1 = &ecspi2; - spi2 = &ecspi3; - spi3 = &ecspi4; - usbphy0 = &usbphy1; - usbphy1 = &usbphy2; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <0>; - clock-frequency = <696000000>; - clock-latency = <61036>; /* two CLK32 periods */ - #cooling-cells = <2>; - operating-points = < - /* kHz uV */ - 696000 1275000 - 528000 1175000 - 396000 1025000 - 198000 950000 - >; - fsl,soc-operating-points = < - /* KHz uV */ - 696000 1275000 - 528000 1175000 - 396000 1175000 - 198000 1175000 - >; - clocks = <&clks IMX6UL_CLK_ARM>, - <&clks IMX6UL_CLK_PLL2_BUS>, - <&clks IMX6UL_CLK_PLL2_PFD2>, - <&clks IMX6UL_CA7_SECONDARY_SEL>, - <&clks IMX6UL_CLK_STEP>, - <&clks IMX6UL_CLK_PLL1_SW>, - <&clks IMX6UL_CLK_PLL1_SYS>; - clock-names = "arm", "pll2_bus", "pll2_pfd2_396m", - "secondary_sel", "step", "pll1_sw", - "pll1_sys"; - arm-supply = <®_arm>; - soc-supply = <®_soc>; - nvmem-cells = <&cpu_speed_grade>; - nvmem-cell-names = "speed_grade"; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; - interrupt-parent = <&intc>; - status = "disabled"; - }; - - ckil: clock-cli { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "ckil"; - }; - - osc: clock-osc { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "osc"; - }; - - ipp_di0: clock-di0 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - clock-output-names = "ipp_di0"; - }; - - ipp_di1: clock-di1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - clock-output-names = "ipp_di1"; - }; - - tempmon: tempmon { - compatible = "fsl,imx6ul-tempmon", "fsl,imx6sx-tempmon"; - interrupt-parent = <&gpc>; - interrupts = ; - fsl,tempmon = <&anatop>; - nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>; - nvmem-cell-names = "calib", "temp_grade"; - clocks = <&clks IMX6UL_CLK_PLL3_USB_OTG>; - }; - - pmu { - compatible = "arm,cortex-a7-pmu"; - interrupt-parent = <&gpc>; - interrupts = ; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&gpc>; - ranges; - - ocram: sram@900000 { - compatible = "mmio-sram"; - reg = <0x00900000 0x20000>; - }; - - intc: interrupt-controller@a01000 { - compatible = "arm,gic-400", "arm,cortex-a7-gic"; - interrupts = ; - #interrupt-cells = <3>; - interrupt-controller; - interrupt-parent = <&intc>; - reg = <0x00a01000 0x1000>, - <0x00a02000 0x2000>, - <0x00a04000 0x2000>, - <0x00a06000 0x2000>; - }; - - dma_apbh: dma-apbh@1804000 { - compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh"; - reg = <0x01804000 0x2000>; - interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>, - <0 13 IRQ_TYPE_LEVEL_HIGH>, - <0 13 IRQ_TYPE_LEVEL_HIGH>, - <0 13 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; - #dma-cells = <1>; - dma-channels = <4>; - clocks = <&clks IMX6UL_CLK_APBHDMA>; - }; - - gpmi: gpmi-nand@1806000 { - compatible = "fsl,imx6q-gpmi-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x01806000 0x2000>, <0x01808000 0x2000>; - reg-names = "gpmi-nand", "bch"; - interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "bch"; - clocks = <&clks IMX6UL_CLK_GPMI_IO>, - <&clks IMX6UL_CLK_GPMI_APB>, - <&clks IMX6UL_CLK_GPMI_BCH>, - <&clks IMX6UL_CLK_GPMI_BCH_APB>, - <&clks IMX6UL_CLK_PER_BCH>; - clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch", - "gpmi_bch_apb", "per1_bch"; - dmas = <&dma_apbh 0>; - dma-names = "rx-tx"; - status = "disabled"; - }; - - aips1: aips-bus@2000000 { - compatible = "fsl,aips-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x02000000 0x100000>; - ranges; - - spba-bus@2000000 { - compatible = "fsl,spba-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x02000000 0x40000>; - ranges; - - ecspi1: spi@2008000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; - reg = <0x02008000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_ECSPI1>, - <&clks IMX6UL_CLK_ECSPI1>; - clock-names = "ipg", "per"; - dmas = <&sdma 3 7 1>, <&sdma 4 7 2>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - ecspi2: spi@200c000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; - reg = <0x0200c000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_ECSPI2>, - <&clks IMX6UL_CLK_ECSPI2>; - clock-names = "ipg", "per"; - dmas = <&sdma 5 7 1>, <&sdma 6 7 2>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - ecspi3: spi@2010000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; - reg = <0x02010000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_ECSPI3>, - <&clks IMX6UL_CLK_ECSPI3>; - clock-names = "ipg", "per"; - dmas = <&sdma 7 7 1>, <&sdma 8 7 2>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - ecspi4: spi@2014000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; - reg = <0x02014000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_ECSPI4>, - <&clks IMX6UL_CLK_ECSPI4>; - clock-names = "ipg", "per"; - dmas = <&sdma 9 7 1>, <&sdma 10 7 2>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart7: serial@2018000 { - compatible = "fsl,imx6ul-uart", - "fsl,imx6q-uart"; - reg = <0x02018000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_UART7_IPG>, - <&clks IMX6UL_CLK_UART7_SERIAL>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart1: serial@2020000 { - compatible = "fsl,imx6ul-uart", - "fsl,imx6q-uart"; - reg = <0x02020000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_UART1_IPG>, - <&clks IMX6UL_CLK_UART1_SERIAL>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart8: serial@2024000 { - compatible = "fsl,imx6ul-uart", - "fsl,imx6q-uart"; - reg = <0x02024000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_UART8_IPG>, - <&clks IMX6UL_CLK_UART8_SERIAL>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - sai1: sai@2028000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai"; - reg = <0x02028000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_SAI1_IPG>, - <&clks IMX6UL_CLK_SAI1>, - <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dmas = <&sdma 35 24 0>, - <&sdma 36 24 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - sai2: sai@202c000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai"; - reg = <0x0202c000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_SAI2_IPG>, - <&clks IMX6UL_CLK_SAI2>, - <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dmas = <&sdma 37 24 0>, - <&sdma 38 24 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - sai3: sai@2030000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai"; - reg = <0x02030000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_SAI3_IPG>, - <&clks IMX6UL_CLK_SAI3>, - <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dmas = <&sdma 39 24 0>, - <&sdma 40 24 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - }; - - tsc: tsc@2040000 { - compatible = "fsl,imx6ul-tsc"; - reg = <0x02040000 0x4000>, <0x0219c000 0x4000>; - interrupts = , - ; - clocks = <&clks IMX6UL_CLK_IPG>, - <&clks IMX6UL_CLK_ADC2>; - clock-names = "tsc", "adc"; - status = "disabled"; - }; - - pwm1: pwm@2080000 { - compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; - reg = <0x02080000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_PWM1>, - <&clks IMX6UL_CLK_PWM1>; - clock-names = "ipg", "per"; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm2: pwm@2084000 { - compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; - reg = <0x02084000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_PWM2>, - <&clks IMX6UL_CLK_PWM2>; - clock-names = "ipg", "per"; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm3: pwm@2088000 { - compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; - reg = <0x02088000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_PWM3>, - <&clks IMX6UL_CLK_PWM3>; - clock-names = "ipg", "per"; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm4: pwm@208c000 { - compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; - reg = <0x0208c000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_PWM4>, - <&clks IMX6UL_CLK_PWM4>; - clock-names = "ipg", "per"; - #pwm-cells = <2>; - status = "disabled"; - }; - - can1: flexcan@2090000 { - compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan"; - reg = <0x02090000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_CAN1_IPG>, - <&clks IMX6UL_CLK_CAN1_SERIAL>; - clock-names = "ipg", "per"; - fsl,stop-mode = <&gpr 0x10 1 0x10 17>; - status = "disabled"; - }; - - can2: flexcan@2094000 { - compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan"; - reg = <0x02094000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_CAN2_IPG>, - <&clks IMX6UL_CLK_CAN2_SERIAL>; - clock-names = "ipg", "per"; - fsl,stop-mode = <&gpr 0x10 2 0x10 18>; - status = "disabled"; - }; - - gpt1: gpt@2098000 { - compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt"; - reg = <0x02098000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_GPT1_BUS>, - <&clks IMX6UL_CLK_GPT1_SERIAL>; - clock-names = "ipg", "per"; - }; - - gpio1: gpio@209c000 { - compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; - reg = <0x0209c000 0x4000>; - interrupts = , - ; - clocks = <&clks IMX6UL_CLK_GPIO1>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 23 10>, <&iomuxc 10 17 6>, - <&iomuxc 16 33 16>; - }; - - gpio2: gpio@20a0000 { - compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; - reg = <0x020a0000 0x4000>; - interrupts = , - ; - clocks = <&clks IMX6UL_CLK_GPIO2>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 49 16>, <&iomuxc 16 111 6>; - }; - - gpio3: gpio@20a4000 { - compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; - reg = <0x020a4000 0x4000>; - interrupts = , - ; - clocks = <&clks IMX6UL_CLK_GPIO3>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 65 29>; - }; - - gpio4: gpio@20a8000 { - compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; - reg = <0x020a8000 0x4000>; - interrupts = , - ; - clocks = <&clks IMX6UL_CLK_GPIO4>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 94 17>, <&iomuxc 17 117 12>; - }; - - gpio5: gpio@20ac000 { - compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; - reg = <0x020ac000 0x4000>; - interrupts = , - ; - clocks = <&clks IMX6UL_CLK_GPIO5>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 7 10>, <&iomuxc 10 5 2>; - }; - - fec2: ethernet@20b4000 { - compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec"; - reg = <0x020b4000 0x4000>; - interrupt-names = "int0", "pps"; - interrupts = , - ; - clocks = <&clks IMX6UL_CLK_ENET>, - <&clks IMX6UL_CLK_ENET_AHB>, - <&clks IMX6UL_CLK_ENET_PTP>, - <&clks IMX6UL_CLK_ENET2_REF_125M>, - <&clks IMX6UL_CLK_ENET2_REF_125M>; - clock-names = "ipg", "ahb", "ptp", - "enet_clk_ref", "enet_out"; - fsl,num-tx-queues = <1>; - fsl,num-rx-queues = <1>; - status = "disabled"; - }; - - kpp: kpp@20b8000 { - compatible = "fsl,imx6ul-kpp", "fsl,imx6q-kpp", "fsl,imx21-kpp"; - reg = <0x020b8000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_KPP>; - status = "disabled"; - }; - - wdog1: wdog@20bc000 { - compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt"; - reg = <0x020bc000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_WDOG1>; - }; - - wdog2: wdog@20c0000 { - compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt"; - reg = <0x020c0000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_WDOG2>; - status = "disabled"; - }; - - clks: ccm@20c4000 { - compatible = "fsl,imx6ul-ccm"; - reg = <0x020c4000 0x4000>; - interrupts = , - ; - #clock-cells = <1>; - clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>; - clock-names = "ckil", "osc", "ipp_di0", "ipp_di1"; - }; - - anatop: anatop@20c8000 { - compatible = "fsl,imx6ul-anatop", "fsl,imx6q-anatop", - "syscon", "simple-mfd"; - reg = <0x020c8000 0x1000>; - interrupts = , - , - ; - - reg_3p0: regulator-3p0 { - compatible = "fsl,anatop-regulator"; - regulator-name = "vdd3p0"; - regulator-min-microvolt = <2625000>; - regulator-max-microvolt = <3400000>; - anatop-reg-offset = <0x120>; - anatop-vol-bit-shift = <8>; - anatop-vol-bit-width = <5>; - anatop-min-bit-val = <0>; - anatop-min-voltage = <2625000>; - anatop-max-voltage = <3400000>; - anatop-enable-bit = <0>; - }; - - reg_arm: regulator-vddcore { - compatible = "fsl,anatop-regulator"; - regulator-name = "cpu"; - regulator-min-microvolt = <725000>; - regulator-max-microvolt = <1450000>; - regulator-always-on; - anatop-reg-offset = <0x140>; - anatop-vol-bit-shift = <0>; - anatop-vol-bit-width = <5>; - anatop-delay-reg-offset = <0x170>; - anatop-delay-bit-shift = <24>; - anatop-delay-bit-width = <2>; - anatop-min-bit-val = <1>; - anatop-min-voltage = <725000>; - anatop-max-voltage = <1450000>; - }; - - reg_soc: regulator-vddsoc { - compatible = "fsl,anatop-regulator"; - regulator-name = "vddsoc"; - regulator-min-microvolt = <725000>; - regulator-max-microvolt = <1450000>; - regulator-always-on; - anatop-reg-offset = <0x140>; - anatop-vol-bit-shift = <18>; - anatop-vol-bit-width = <5>; - anatop-delay-reg-offset = <0x170>; - anatop-delay-bit-shift = <28>; - anatop-delay-bit-width = <2>; - anatop-min-bit-val = <1>; - anatop-min-voltage = <725000>; - anatop-max-voltage = <1450000>; - }; - }; - - usbphy1: usbphy@20c9000 { - compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy"; - reg = <0x020c9000 0x1000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_USBPHY1>; - phy-3p0-supply = <®_3p0>; - fsl,anatop = <&anatop>; - }; - - usbphy2: usbphy@20ca000 { - compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy"; - reg = <0x020ca000 0x1000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_USBPHY2>; - phy-3p0-supply = <®_3p0>; - fsl,anatop = <&anatop>; - }; - - snvs: snvs@20cc000 { - compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; - reg = <0x020cc000 0x4000>; - - snvs_rtc: snvs-rtc-lp { - compatible = "fsl,sec-v4.0-mon-rtc-lp"; - regmap = <&snvs>; - offset = <0x34>; - interrupts = , - ; - }; - - snvs_poweroff: snvs-poweroff { - compatible = "syscon-poweroff"; - regmap = <&snvs>; - offset = <0x38>; - value = <0x60>; - mask = <0x60>; - status = "disabled"; - }; - - snvs_pwrkey: snvs-powerkey { - compatible = "fsl,sec-v4.0-pwrkey"; - regmap = <&snvs>; - interrupts = ; - linux,keycode = ; - wakeup-source; - status = "disabled"; - }; - - snvs_lpgpr: snvs-lpgpr { - compatible = "fsl,imx6ul-snvs-lpgpr"; - }; - }; - - epit1: epit@20d0000 { - reg = <0x020d0000 0x4000>; - interrupts = ; - }; - - epit2: epit@20d4000 { - reg = <0x020d4000 0x4000>; - interrupts = ; - }; - - src: src@20d8000 { - compatible = "fsl,imx6ul-src", "fsl,imx51-src"; - reg = <0x020d8000 0x4000>; - interrupts = , - ; - #reset-cells = <1>; - }; - - gpc: gpc@20dc000 { - compatible = "fsl,imx6ul-gpc", "fsl,imx6q-gpc"; - reg = <0x020dc000 0x4000>; - interrupt-controller; - #interrupt-cells = <3>; - interrupts = ; - interrupt-parent = <&intc>; - }; - - iomuxc: iomuxc@20e0000 { - compatible = "fsl,imx6ul-iomuxc"; - reg = <0x020e0000 0x4000>; - }; - - gpr: iomuxc-gpr@20e4000 { - compatible = "fsl,imx6ul-iomuxc-gpr", - "fsl,imx6q-iomuxc-gpr", "syscon"; - reg = <0x020e4000 0x4000>; - }; - - gpt2: gpt@20e8000 { - compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt"; - reg = <0x020e8000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_GPT2_BUS>, - <&clks IMX6UL_CLK_GPT2_SERIAL>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - sdma: sdma@20ec000 { - compatible = "fsl,imx6ul-sdma", "fsl,imx6q-sdma", - "fsl,imx35-sdma"; - reg = <0x020ec000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_IPG>, - <&clks IMX6UL_CLK_SDMA>; - clock-names = "ipg", "ahb"; - #dma-cells = <3>; - fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; - }; - - pwm5: pwm@20f0000 { - compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; - reg = <0x020f0000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_PWM5>, - <&clks IMX6UL_CLK_PWM5>; - clock-names = "ipg", "per"; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm6: pwm@20f4000 { - compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; - reg = <0x020f4000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_PWM6>, - <&clks IMX6UL_CLK_PWM6>; - clock-names = "ipg", "per"; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm7: pwm@20f8000 { - compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; - reg = <0x020f8000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_PWM7>, - <&clks IMX6UL_CLK_PWM7>; - clock-names = "ipg", "per"; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm8: pwm@20fc000 { - compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; - reg = <0x020fc000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_PWM8>, - <&clks IMX6UL_CLK_PWM8>; - clock-names = "ipg", "per"; - #pwm-cells = <2>; - status = "disabled"; - }; - }; - - aips2: aips-bus@2100000 { - compatible = "fsl,aips-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x02100000 0x100000>; - ranges; - - crypto: caam@2140000 { - compatible = "fsl,imx6ul-caam", "fsl,sec-v4.0"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x2140000 0x3c000>; - ranges = <0 0x2140000 0x3c000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_CAAM_IPG>, <&clks IMX6UL_CLK_CAAM_ACLK>, - <&clks IMX6UL_CLK_CAAM_MEM>; - clock-names = "ipg", "aclk", "mem"; - - sec_jr0: jr0@1000 { - compatible = "fsl,sec-v4.0-job-ring"; - reg = <0x1000 0x1000>; - interrupts = ; - }; - - sec_jr1: jr1@2000 { - compatible = "fsl,sec-v4.0-job-ring"; - reg = <0x2000 0x1000>; - interrupts = ; - }; - - sec_jr2: jr2@3000 { - compatible = "fsl,sec-v4.0-job-ring"; - reg = <0x3000 0x1000>; - interrupts = ; - }; - }; - - usbotg1: usb@2184000 { - compatible = "fsl,imx6ul-usb", "fsl,imx27-usb"; - reg = <0x02184000 0x200>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_USBOH3>; - fsl,usbphy = <&usbphy1>; - fsl,usbmisc = <&usbmisc 0>; - fsl,anatop = <&anatop>; - ahb-burst-config = <0x0>; - tx-burst-size-dword = <0x10>; - rx-burst-size-dword = <0x10>; - status = "disabled"; - }; - - usbotg2: usb@2184200 { - compatible = "fsl,imx6ul-usb", "fsl,imx27-usb"; - reg = <0x02184200 0x200>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_USBOH3>; - fsl,usbphy = <&usbphy2>; - fsl,usbmisc = <&usbmisc 1>; - ahb-burst-config = <0x0>; - tx-burst-size-dword = <0x10>; - rx-burst-size-dword = <0x10>; - status = "disabled"; - }; - - usbmisc: usbmisc@2184800 { - #index-cells = <1>; - compatible = "fsl,imx6ul-usbmisc", "fsl,imx6q-usbmisc"; - reg = <0x02184800 0x200>; - }; - - fec1: ethernet@2188000 { - compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec"; - reg = <0x02188000 0x4000>; - interrupt-names = "int0", "pps"; - interrupts = , - ; - clocks = <&clks IMX6UL_CLK_ENET>, - <&clks IMX6UL_CLK_ENET_AHB>, - <&clks IMX6UL_CLK_ENET_PTP>, - <&clks IMX6UL_CLK_ENET_REF>, - <&clks IMX6UL_CLK_ENET_REF>; - clock-names = "ipg", "ahb", "ptp", - "enet_clk_ref", "enet_out"; - fsl,num-tx-queues = <1>; - fsl,num-rx-queues = <1>; - status = "disabled"; - }; - - usdhc1: usdhc@2190000 { - compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc"; - reg = <0x02190000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_USDHC1>, - <&clks IMX6UL_CLK_USDHC1>, - <&clks IMX6UL_CLK_USDHC1>; - clock-names = "ipg", "ahb", "per"; - fsl,tuning-step = <2>; - fsl,tuning-start-tap = <20>; - bus-width = <4>; - status = "disabled"; - }; - - usdhc2: usdhc@2194000 { - compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc"; - reg = <0x02194000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_USDHC2>, - <&clks IMX6UL_CLK_USDHC2>, - <&clks IMX6UL_CLK_USDHC2>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - fsl,tuning-step = <2>; - fsl,tuning-start-tap = <20>; - status = "disabled"; - }; - - adc1: adc@2198000 { - compatible = "fsl,imx6ul-adc", "fsl,vf610-adc"; - reg = <0x02198000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_ADC1>; - num-channels = <2>; - clock-names = "adc"; - fsl,adck-max-frequency = <30000000>, <40000000>, - <20000000>; - status = "disabled"; - }; - - i2c1: i2c@21a0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; - reg = <0x021a0000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_I2C1>; - status = "disabled"; - }; - - i2c2: i2c@21a4000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; - reg = <0x021a4000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_I2C2>; - status = "disabled"; - }; - - i2c3: i2c@21a8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; - reg = <0x021a8000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_I2C3>; - status = "disabled"; - }; - - memory-controller@21b0000 { - compatible = "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc"; - reg = <0x021b0000 0x4000>; - clocks = <&clks IMX6UL_CLK_MMDC_P0_IPG>; - }; - - weim: weim@21b8000 { - #address-cells = <2>; - #size-cells = <1>; - compatible = "fsl,imx6ul-weim", "fsl,imx6q-weim"; - reg = <0x021b8000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_EIM>; - fsl,weim-cs-gpr = <&gpr>; - status = "disabled"; - }; - - ocotp: ocotp-ctrl@21bc000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "fsl,imx6ul-ocotp", "syscon"; - reg = <0x021bc000 0x4000>; - clocks = <&clks IMX6UL_CLK_OCOTP>; - - tempmon_calib: calib@38 { - reg = <0x38 4>; - }; - - tempmon_temp_grade: temp-grade@20 { - reg = <0x20 4>; - }; - - cpu_speed_grade: speed-grade@10 { - reg = <0x10 4>; - }; - }; - - csi: csi@21c4000 { - compatible = "fsl,imx6ul-csi", "fsl,imx7-csi"; - reg = <0x021c4000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_CSI>; - clock-names = "mclk"; - status = "disabled"; - }; - - lcdif: lcdif@21c8000 { - compatible = "fsl,imx6ul-lcdif", "fsl,imx28-lcdif"; - reg = <0x021c8000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_LCDIF_PIX>, - <&clks IMX6UL_CLK_LCDIF_APB>, - <&clks IMX6UL_CLK_DUMMY>; - clock-names = "pix", "axi", "disp_axi"; - status = "disabled"; - }; - - pxp: pxp@21cc000 { - compatible = "fsl,imx6ul-pxp"; - reg = <0x021cc000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_PXP>; - clock-names = "axi"; - }; - - qspi: spi@21e0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6ul-qspi", "fsl,imx6sx-qspi"; - reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>; - reg-names = "QuadSPI", "QuadSPI-memory"; - interrupts = ; - clocks = <&clks IMX6UL_CLK_QSPI>, - <&clks IMX6UL_CLK_QSPI>; - clock-names = "qspi_en", "qspi"; - status = "disabled"; - }; - - wdog3: wdog@21e4000 { - compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt"; - reg = <0x021e4000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_WDOG3>; - status = "disabled"; - }; - - uart2: serial@21e8000 { - compatible = "fsl,imx6ul-uart", - "fsl,imx6q-uart"; - reg = <0x021e8000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_UART2_IPG>, - <&clks IMX6UL_CLK_UART2_SERIAL>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart3: serial@21ec000 { - compatible = "fsl,imx6ul-uart", - "fsl,imx6q-uart"; - reg = <0x021ec000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_UART3_IPG>, - <&clks IMX6UL_CLK_UART3_SERIAL>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart4: serial@21f0000 { - compatible = "fsl,imx6ul-uart", - "fsl,imx6q-uart"; - reg = <0x021f0000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_UART4_IPG>, - <&clks IMX6UL_CLK_UART4_SERIAL>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart5: serial@21f4000 { - compatible = "fsl,imx6ul-uart", - "fsl,imx6q-uart"; - reg = <0x021f4000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_UART5_IPG>, - <&clks IMX6UL_CLK_UART5_SERIAL>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - i2c4: i2c@21f8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; - reg = <0x021f8000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_I2C4>; - status = "disabled"; - }; - - uart6: serial@21fc000 { - compatible = "fsl,imx6ul-uart", - "fsl,imx6q-uart"; - reg = <0x021fc000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_UART6_IPG>, - <&clks IMX6UL_CLK_UART6_SERIAL>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/imx6ull-14x14-evk.dts b/sys/gnu/dts/arm/imx6ull-14x14-evk.dts deleted file mode 100644 index 74aaa8a56a3..00000000000 --- a/sys/gnu/dts/arm/imx6ull-14x14-evk.dts +++ /dev/null @@ -1,18 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -// -// Copyright (C) 2016 Freescale Semiconductor, Inc. - -/dts-v1/; - -#include "imx6ull.dtsi" -#include "imx6ul-14x14-evk.dtsi" - -/ { - model = "Freescale i.MX6 UltraLiteLite 14x14 EVK Board"; - compatible = "fsl,imx6ull-14x14-evk", "fsl,imx6ull"; -}; - -&clks { - assigned-clocks = <&clks IMX6UL_CLK_PLL3_PFD2>; - assigned-clock-rates = <320000000>; -}; diff --git a/sys/gnu/dts/arm/imx6ull-colibri-eval-v3.dts b/sys/gnu/dts/arm/imx6ull-colibri-eval-v3.dts deleted file mode 100644 index 08669a18349..00000000000 --- a/sys/gnu/dts/arm/imx6ull-colibri-eval-v3.dts +++ /dev/null @@ -1,14 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright 2018 Toradex AG - */ - -/dts-v1/; - -#include "imx6ull-colibri-nonwifi.dtsi" -#include "imx6ull-colibri-eval-v3.dtsi" - -/ { - model = "Toradex Colibri iMX6ULL 256MB on Colibri Evaluation Board V3"; - compatible = "toradex,colibri-imx6ull-eval", "fsl,imx6ull"; -}; diff --git a/sys/gnu/dts/arm/imx6ull-colibri-eval-v3.dtsi b/sys/gnu/dts/arm/imx6ull-colibri-eval-v3.dtsi deleted file mode 100644 index a78849fd2af..00000000000 --- a/sys/gnu/dts/arm/imx6ull-colibri-eval-v3.dtsi +++ /dev/null @@ -1,178 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright 2017 Toradex AG - */ - -/ { - chosen { - stdout-path = "serial0:115200n8"; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_snvs_gpiokeys>; - - power { - label = "Wake-Up"; - gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; - linux,code = ; - debounce-interval = <10>; - wakeup-source; - }; - }; - - /* fixed crystal dedicated to mcp2515 */ - clk16m: clk16m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <16000000>; - }; - - panel: panel { - compatible = "edt,et057090dhu"; - backlight = <&bl>; - power-supply = <®_3v3>; - - port { - panel_in: endpoint { - remote-endpoint = <&lcdif_out>; - }; - }; - }; - - reg_3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_5v0: regulator-5v0 { - compatible = "regulator-fixed"; - regulator-name = "5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_usbh_vbus: regulator-usbh-vbus { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh_reg>; - regulator-name = "VCC_USB[1-4]"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; - vin-supply = <®_5v0>; - }; -}; - -&adc1 { - status = "okay"; -}; - -&bl { - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - power-supply = <®_3v3>; - pwms = <&pwm4 0 5000000 1>; - status = "okay"; -}; - -&ecspi1 { - status = "okay"; - - mcp2515: can@0 { - compatible = "microchip,mcp2515"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can_int>; - reg = <0>; - clocks = <&clk16m>; - interrupt-parent = <&gpio2>; - interrupts = <4 IRQ_TYPE_EDGE_FALLING>; - spi-max-frequency = <10000000>; - vdd-supply = <®_3v3>; - xceiver-supply = <®_5v0>; - status = "okay"; - }; -}; - -&i2c1 { - status = "okay"; - - /* M41T0M6 real time clock on carrier board */ - m41t0m6: rtc@68 { - compatible = "st,m41t0"; - reg = <0x68>; - }; -}; - -&lcdif { - status = "okay"; - - port { - lcdif_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; -}; - -/* PWM */ -&pwm4 { - status = "okay"; -}; - -/* PWM */ -&pwm5 { - status = "okay"; -}; - -/* PWM */ -&pwm6 { - status = "okay"; -}; - -/* PWM */ -&pwm7 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart5 { - status = "okay"; -}; - -&usbotg1 { - status = "okay"; -}; - -&usbotg2 { - vbus-supply = <®_usbh_vbus>; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; - pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_cd>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_snvs_usdhc1_cd>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_snvs_usdhc1_cd>; - pinctrl-3 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_sleep_cd>; - cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; - disable-wp; - wakeup-source; - keep-power-in-suspend; - vmmc-supply = <®_3v3>; - vqmmc-supply = <®_sd1_vmmc>; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-sdr104; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx6ull-colibri-nonwifi.dtsi b/sys/gnu/dts/arm/imx6ull-colibri-nonwifi.dtsi deleted file mode 100644 index 95a11b8bcbd..00000000000 --- a/sys/gnu/dts/arm/imx6ull-colibri-nonwifi.dtsi +++ /dev/null @@ -1,24 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright 2018 Toradex AG - */ - -#include "imx6ull-colibri.dtsi" - -/ { - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x10000000>; - }; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3 - &pinctrl_gpio4 &pinctrl_gpio5 &pinctrl_gpio6 &pinctrl_gpio7>; -}; - -&iomuxc_snvs { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_snvs_gpio1 &pinctrl_snvs_gpio2 &pinctrl_snvs_gpio3>; -}; diff --git a/sys/gnu/dts/arm/imx6ull-colibri-wifi-eval-v3.dts b/sys/gnu/dts/arm/imx6ull-colibri-wifi-eval-v3.dts deleted file mode 100644 index df72ce1ae2c..00000000000 --- a/sys/gnu/dts/arm/imx6ull-colibri-wifi-eval-v3.dts +++ /dev/null @@ -1,14 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright 2018 Toradex AG - */ - -/dts-v1/; - -#include "imx6ull-colibri-wifi.dtsi" -#include "imx6ull-colibri-eval-v3.dtsi" - -/ { - model = "Toradex Colibri iMX6ULL 512MB on Colibri Evaluation Board V3"; - compatible = "toradex,colibri-imx6ull-wifi-eval", "fsl,imx6ull"; -}; diff --git a/sys/gnu/dts/arm/imx6ull-colibri-wifi.dtsi b/sys/gnu/dts/arm/imx6ull-colibri-wifi.dtsi deleted file mode 100644 index a0545431b3d..00000000000 --- a/sys/gnu/dts/arm/imx6ull-colibri-wifi.dtsi +++ /dev/null @@ -1,52 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright 2018 Toradex AG - */ - -#include "imx6ull-colibri.dtsi" - -/ { - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000>; - }; - - wifi_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_snvs_wifi_pdn>; - reset-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; - }; -}; - -&cpu0 { - clock-frequency = <792000000>; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3 - &pinctrl_gpio4 &pinctrl_gpio5 &pinctrl_gpio7>; - -}; - -&iomuxc_snvs { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_snvs_gpio1 &pinctrl_snvs_gpio2>; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - assigned-clocks = <&clks IMX6UL_CLK_USDHC2_SEL>, <&clks IMX6UL_CLK_USDHC2>; - assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>; - assigned-clock-rates = <0>, <198000000>; - cap-power-off-card; - keep-power-in-suspend; - mmc-pwrseq = <&wifi_pwrseq>; - no-1-8-v; - non-removable; - vmmc-supply = <®_module_3v3>; - wakeup-source; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx6ull-colibri.dtsi b/sys/gnu/dts/arm/imx6ull-colibri.dtsi deleted file mode 100644 index 9145c536d71..00000000000 --- a/sys/gnu/dts/arm/imx6ull-colibri.dtsi +++ /dev/null @@ -1,611 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright 2018 Toradex AG - */ - -#include "imx6ull.dtsi" - -/ { - aliases { - ethernet0 = &fec2; - ethernet1 = &fec1; - }; - - bl: backlight { - compatible = "pwm-backlight"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_bl_on>; - enable-gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; - status = "disabled"; - }; - - reg_module_3v3: regulator-module-3v3 { - compatible = "regulator-fixed"; - regulator-always-on; - regulator-name = "+V3.3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_module_3v3_avdd: regulator-module-3v3-avdd { - compatible = "regulator-fixed"; - regulator-always-on; - regulator-name = "+V3.3_AVDD_AUDIO"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_sd1_vmmc: regulator-sd1-vmmc { - compatible = "regulator-gpio"; - gpio = <&gpio5 9 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_snvs_reg_sd>; - regulator-always-on; - regulator-name = "+V3.3_1.8_SD"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - states = <1800000 0x1 3300000 0x0>; - vin-supply = <®_module_3v3>; - }; -}; - -&adc1 { - num-channels = <10>; - vref-supply = <®_module_3v3_avdd>; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - status = "disabled"; -}; - -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - status = "disabled"; -}; - -/* Colibri SPI */ -&ecspi1 { - cs-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>; -}; - -&fec2 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&pinctrl_enet2>; - pinctrl-1 = <&pinctrl_enet2_sleep>; - phy-mode = "rmii"; - phy-handle = <ðphy1>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy1: ethernet-phy@2 { - compatible = "ethernet-phy-ieee802.3-c22"; - max-speed = <100>; - reg = <2>; - }; - }; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - nand-on-flash-bbt; - nand-ecc-mode = "hw"; - nand-ecc-strength = <8>; - nand-ecc-step-size = <512>; - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c1>; - pinctrl-1 = <&pinctrl_i2c1_gpio>; - sda-gpios = <&gpio1 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpio1 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; -}; - -&i2c2 { - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c2>; - pinctrl-1 = <&pinctrl_i2c2_gpio>; - sda-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; - - ad7879@2c { - compatible = "adi,ad7879-1"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_snvs_ad7879_int>; - reg = <0x2c>; - interrupt-parent = <&gpio5>; - interrupts = <7 IRQ_TYPE_EDGE_FALLING>; - touchscreen-max-pressure = <4096>; - adi,resistance-plate-x = <120>; - adi,first-conversion-delay = /bits/ 8 <3>; - adi,acquisition-time = /bits/ 8 <1>; - adi,median-filter-size = /bits/ 8 <2>; - adi,averaging = /bits/ 8 <1>; - adi,conversion-interval = /bits/ 8 <255>; - }; -}; - -&lcdif { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcdif_dat - &pinctrl_lcdif_ctrl>; -}; - -&pwm4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm4>; - #pwm-cells = <3>; -}; - -&pwm5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm5>; - #pwm-cells = <3>; -}; - -&pwm6 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm6>; - #pwm-cells = <3>; -}; - -&pwm7 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm7>; - #pwm-cells = <3>; -}; - -&sdma { - status = "okay"; -}; - -&snvs_pwrkey { - status = "disabled"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_ctrl1>; - uart-has-rtscts; - fsl,dte-mode; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - uart-has-rtscts; - fsl,dte-mode; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - fsl,dte-mode; -}; - -&usbotg1 { - dr_mode = "otg"; - srp-disable; - hnp-disable; - adp-disable; -}; - -&usbotg2 { - dr_mode = "host"; -}; - -&usdhc1 { - assigned-clocks = <&clks IMX6UL_CLK_USDHC1_SEL>, <&clks IMX6UL_CLK_USDHC1>; - assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>; - assigned-clock-rates = <0>, <198000000>; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; -}; - -&iomuxc { - pinctrl_can_int: canint-grp { - fsl,pins = < - MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04 0x13010 /* SODIMM 73 */ - >; - }; - - pinctrl_enet2: enet2-grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 - MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 - MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 - MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 - MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 - MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 - MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 - MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 - MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 - MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 - >; - }; - - pinctrl_enet2_sleep: enet2sleepgrp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO06__GPIO1_IO06 0x0 - MX6UL_PAD_GPIO1_IO07__GPIO1_IO07 0x0 - MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x0 - MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09 0x0 - MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x0 - MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x0 - MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 - MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11 0x0 - MX6UL_PAD_ENET2_TX_DATA1__GPIO2_IO12 0x0 - MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13 0x0 - >; - }; - - pinctrl_ecspi1_cs: ecspi1-cs-grp { - fsl,pins = < - MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x70a0 /* SODIMM 86 */ - >; - }; - - pinctrl_ecspi1: ecspi1-grp { - fsl,pins = < - MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x000a0 /* SODIMM 88 */ - MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x000a0 /* SODIMM 92 */ - MX6UL_PAD_LCD_DATA23__ECSPI1_MISO 0x100a0 /* SODIMM 90 */ - >; - }; - - pinctrl_flexcan1: flexcan1-grp { - fsl,pins = < - MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX 0x1b020 - MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX 0x1b020 - >; - }; - - pinctrl_flexcan2: flexcan2-grp { - fsl,pins = < - MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX 0x1b020 - MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX 0x1b020 - >; - }; - - pinctrl_gpio_bl_on: gpio-bl-on-grp { - fsl,pins = < - MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x30a0 /* SODIMM 71 */ - >; - }; - - pinctrl_gpio1: gpio1-grp { - fsl,pins = < - MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x10b0 /* SODIMM 77 */ - MX6UL_PAD_JTAG_TCK__GPIO1_IO14 0x70a0 /* SODIMM 99 */ - MX6UL_PAD_NAND_CE1_B__GPIO4_IO14 0x10b0 /* SODIMM 133 */ - MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24 0x10b0 /* SODIMM 135 */ - MX6UL_PAD_UART3_CTS_B__GPIO1_IO26 0x10b0 /* SODIMM 100 */ - MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15 0x70a0 /* SODIMM 102 */ - MX6UL_PAD_ENET1_RX_ER__GPIO2_IO07 0x10b0 /* SODIMM 104 */ - MX6UL_PAD_UART3_RTS_B__GPIO1_IO27 0x10b0 /* SODIMM 186 */ - >; - }; - - pinctrl_gpio2: gpio2-grp { /* Camera */ - fsl,pins = < - MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x10b0 /* SODIMM 69 */ - MX6UL_PAD_CSI_MCLK__GPIO4_IO17 0x10b0 /* SODIMM 75 */ - MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x10b0 /* SODIMM 85 */ - MX6UL_PAD_CSI_PIXCLK__GPIO4_IO18 0x10b0 /* SODIMM 96 */ - MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x10b0 /* SODIMM 98 */ - >; - }; - - pinctrl_gpio3: gpio3-grp { /* CAN2 */ - fsl,pins = < - MX6UL_PAD_ENET1_RX_EN__GPIO2_IO02 0x10b0 /* SODIMM 178 */ - MX6UL_PAD_ENET1_TX_DATA0__GPIO2_IO03 0x10b0 /* SODIMM 188 */ - >; - }; - - pinctrl_gpio4: gpio4-grp { - fsl,pins = < - MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x10b0 /* SODIMM 65 */ - >; - }; - - pinctrl_gpio5: gpio5-grp { /* ATMEL MXT TOUCH */ - fsl,pins = < - MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0xb0a0 /* SODIMM 106 */ - >; - }; - - pinctrl_gpio6: gpio6-grp { /* Wifi pins */ - fsl,pins = < - MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x10b0 /* SODIMM 89 */ - MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x10b0 /* SODIMM 79 */ - MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x10b0 /* SODIMM 81 */ - MX6UL_PAD_CSI_DATA03__GPIO4_IO24 0x10b0 /* SODIMM 97 */ - MX6UL_PAD_CSI_DATA00__GPIO4_IO21 0x10b0 /* SODIMM 101 */ - MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x10b0 /* SODIMM 103 */ - MX6UL_PAD_CSI_HSYNC__GPIO4_IO20 0x10b0 /* SODIMM 94 */ - >; - }; - - pinctrl_gpio7: gpio7-grp { /* CAN1 */ - fsl,pins = < - MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00 0xb0b0/* SODIMM 55 */ - MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01 0xb0b0 /* SODIMM 63 */ - >; - }; - - pinctrl_gpmi_nand: gpmi-nand-grp { - fsl,pins = < - MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x100a9 - MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x100a9 - MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x100a9 - MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x100a9 - MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x100a9 - MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x100a9 - MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x100a9 - MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x100a9 - MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x100a9 - MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x100a9 - MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x100a9 - MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x100a9 - MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x100a9 - MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x100a9 - >; - }; - - pinctrl_i2c1: i2c1-grp { - fsl,pins = < - MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 /* SODIMM 196 */ - MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 /* SODIMM 194 */ - >; - }; - - pinctrl_i2c1_gpio: i2c1-gpio-grp { - fsl,pins = < - MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x4001b8b0 /* SODIMM 196 */ - MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x4001b8b0 /* SODIMM 194 */ - >; - }; - - pinctrl_i2c2: i2c2-grp { - fsl,pins = < - MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 - MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 - >; - }; - - pinctrl_i2c2_gpio: i2c2-gpio-grp { - fsl,pins = < - MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x4001b8b0 - MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x4001b8b0 - >; - }; - - pinctrl_lcdif_dat: lcdif-dat-grp { - fsl,pins = < - MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x00079 /* SODIMM 76 */ - MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x00079 /* SODIMM 70 */ - MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x00079 /* SODIMM 60 */ - MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x00079 /* SODIMM 58 */ - MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x00079 /* SODIMM 78 */ - MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x00079 /* SODIMM 72 */ - MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x00079 /* SODIMM 80 */ - MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x00079 /* SODIMM 46 */ - MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x00079 /* SODIMM 62 */ - MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x00079 /* SODIMM 48 */ - MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x00079 /* SODIMM 74 */ - MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x00079 /* SODIMM 50 */ - MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x00079 /* SODIMM 52 */ - MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x00079 /* SODIMM 54 */ - MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x00079 /* SODIMM 66 */ - MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x00079 /* SODIMM 64 */ - MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x00079 /* SODIMM 57 */ - MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x00079 /* SODIMM 61 */ - >; - }; - - pinctrl_lcdif_ctrl: lcdif-ctrl-grp { - fsl,pins = < - MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x00079 /* SODIMM 56 */ - MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x00079 /* SODIMM 44 */ - MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x00079 /* SODIMM 68 */ - MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x00079 /* SODIMM 82 */ - >; - }; - - pinctrl_pwm4: pwm4-grp { - fsl,pins = < - MX6UL_PAD_NAND_WP_B__PWM4_OUT 0x00079 /* SODIMM 59 */ - >; - }; - - pinctrl_pwm5: pwm5-grp { - fsl,pins = < - MX6UL_PAD_NAND_DQS__PWM5_OUT 0x00079 /* SODIMM 28 */ - >; - }; - - pinctrl_pwm6: pwm6-grp { - fsl,pins = < - MX6UL_PAD_ENET1_TX_EN__PWM6_OUT 0x00079 /* SODIMM 30 */ - >; - }; - - pinctrl_pwm7: pwm7-grp { - fsl,pins = < - MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT 0x00079 /* SODIMM 67 */ - >; - }; - - pinctrl_uart1: uart1-grp { - fsl,pins = < - MX6UL_PAD_UART1_TX_DATA__UART1_DTE_RX 0x1b0b1 /* SODIMM 33 */ - MX6UL_PAD_UART1_RX_DATA__UART1_DTE_TX 0x1b0b1 /* SODIMM 35 */ - MX6UL_PAD_UART1_RTS_B__UART1_DTE_CTS 0x1b0b1 /* SODIMM 27 */ - MX6UL_PAD_UART1_CTS_B__UART1_DTE_RTS 0x1b0b1 /* SODIMM 25 */ - >; - }; - - pinctrl_uart1_ctrl1: uart1-ctrl1-grp { /* Additional DTR, DCD */ - fsl,pins = < - MX6UL_PAD_JTAG_TDI__GPIO1_IO13 0x70a0 /* SODIMM 31 */ - MX6UL_PAD_LCD_DATA18__GPIO3_IO23 0x10b0 /* SODIMM 29 */ - MX6UL_PAD_JTAG_TDO__GPIO1_IO12 0x90b1 /* SODIMM 23 */ - MX6UL_PAD_LCD_DATA19__GPIO3_IO24 0x10b0 /* SODIMM 37 */ - >; - }; - - pinctrl_uart2: uart2-grp { - fsl,pins = < - MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1 /* SODIMM 36 */ - MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1 /* SODIMM 38 */ - MX6UL_PAD_UART2_CTS_B__UART2_DTE_RTS 0x1b0b1 /* SODIMM 32 */ - MX6UL_PAD_UART2_RTS_B__UART2_DTE_CTS 0x1b0b1 /* SODIMM 34 */ - >; - }; - pinctrl_uart5: uart5-grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO04__UART5_DTE_RX 0x1b0b1 /* SODIMM 19 */ - MX6UL_PAD_GPIO1_IO05__UART5_DTE_TX 0x1b0b1 /* SODIMM 21 */ - >; - }; - - pinctrl_usbh_reg: gpio-usbh-reg { - fsl,pins = < - MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x10b0 /* SODIMM 129 */ - >; - }; - - pinctrl_usdhc1: usdhc1-grp { - fsl,pins = < - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x17059 /* SODIMM 47 */ - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x10059 /* SODIMM 190 */ - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 /* SODIMM 192 */ - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 /* SODIMM 49 */ - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 /* SODIMM 51 */ - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 /* SODIMM 53 */ - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp { - fsl,pins = < - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x170b9 - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x100b9 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp { - fsl,pins = < - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x170f9 - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x100f9 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 - >; - }; - - pinctrl_usdhc2: usdhc2-grp { - fsl,pins = < - MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x17059 - MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x17059 - MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x17059 - MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17059 - MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x17059 - MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x17059 - - MX6UL_PAD_GPIO1_IO03__OSC32K_32K_OUT 0x10 - >; - }; - - pinctrl_wdog: wdog-grp { - fsl,pins = < - MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0 - >; - }; -}; - -&iomuxc_snvs { - pinctrl_snvs_gpio1: snvs-gpio1-grp { - fsl,pins = < - MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x110a0 /* SODIMM 93 */ - MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x110a0 /* SODIMM 95 */ - MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10 0x1b0a0 /* SODIMM 105 */ - MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0b0a0 /* SODIMM 131 */ - MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x110a0 /* SODIMM 138 */ - >; - }; - - pinctrl_snvs_gpio2: snvs-gpio2-grp { /* ATMEL MXT TOUCH */ - fsl,pins = < - MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0xb0a0 /* SODIMM 107 */ - >; - }; - - pinctrl_snvs_gpio3: snvs-gpio3-grp { /* Wifi pins */ - fsl,pins = < - MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x130a0 /* SODIMM 127 */ - >; - }; - - pinctrl_snvs_ad7879_int: snvs-ad7879-int-grp { /* TOUCH Interrupt */ - fsl,pins = < - MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x100b0 - >; - }; - - pinctrl_snvs_reg_sd: snvs-reg-sd-grp { - fsl,pins = < - MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x400100b0 - >; - }; - - pinctrl_snvs_usbc_det: snvs-usbc-det-grp { - fsl,pins = < - MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x130b0 - >; - }; - - pinctrl_snvs_gpiokeys: snvs-gpiokeys-grp { - fsl,pins = < - MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x130a0 /* SODIMM 45 */ - >; - }; - - pinctrl_snvs_usdhc1_cd: snvs-usdhc1-cd-grp { - fsl,pins = < - MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0a0 /* SODIMM 43 */ - >; - }; - - pinctrl_snvs_usdhc1_sleep_cd: snvs-usdhc1-cd-grp-slp { - fsl,pins = < - MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x0 - >; - }; - - pinctrl_snvs_wifi_pdn: snvs-wifi-pdn-grp { - fsl,pins = < - MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x130a0 - >; - }; -}; diff --git a/sys/gnu/dts/arm/imx6ull-kontron-n6411-s.dts b/sys/gnu/dts/arm/imx6ull-kontron-n6411-s.dts deleted file mode 100644 index 57588a5e1e3..00000000000 --- a/sys/gnu/dts/arm/imx6ull-kontron-n6411-s.dts +++ /dev/null @@ -1,16 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2017 exceet electronics GmbH - * Copyright (C) 2019 Kontron Electronics GmbH - */ - -/dts-v1/; - -#include "imx6ull-kontron-n6411-som.dtsi" -#include "imx6ul-kontron-n6x1x-s.dtsi" - -/ { - model = "Kontron N6411 S"; - compatible = "kontron,imx6ull-n6411-s", "kontron,imx6ull-n6411-som", - "fsl,imx6ull"; -}; diff --git a/sys/gnu/dts/arm/imx6ull-kontron-n6411-som.dtsi b/sys/gnu/dts/arm/imx6ull-kontron-n6411-som.dtsi deleted file mode 100644 index b7e984284e1..00000000000 --- a/sys/gnu/dts/arm/imx6ull-kontron-n6411-som.dtsi +++ /dev/null @@ -1,40 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2017 exceet electronics GmbH - * Copyright (C) 2018 Kontron Electronics GmbH - */ - -#include "imx6ull.dtsi" -#include "imx6ul-kontron-n6x1x-som-common.dtsi" - -/ { - model = "Kontron N6411 SOM"; - compatible = "kontron,imx6ull-n6311-som", "fsl,imx6ull"; - - memory@80000000 { - reg = <0x80000000 0x20000000>; - device_type = "memory"; - }; -}; - -&qspi { - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "spi-nand"; - spi-max-frequency = <104000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - reg = <0>; - - partition@0 { - label = "ubi1"; - reg = <0x00000000 0x08000000>; - }; - - partition@8000000 { - label = "ubi2"; - reg = <0x08000000 0x18000000>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/imx6ull-opos6ul.dtsi b/sys/gnu/dts/arm/imx6ull-opos6ul.dtsi deleted file mode 100644 index 155f941f281..00000000000 --- a/sys/gnu/dts/arm/imx6ull-opos6ul.dtsi +++ /dev/null @@ -1,6 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT -// -// Copyright 2019 Armadeus Systems - -#include "imx6ull.dtsi" -#include "imx6ul-imx6ull-opos6ul.dtsi" diff --git a/sys/gnu/dts/arm/imx6ull-opos6uldev.dts b/sys/gnu/dts/arm/imx6ull-opos6uldev.dts deleted file mode 100644 index 198fdb72641..00000000000 --- a/sys/gnu/dts/arm/imx6ull-opos6uldev.dts +++ /dev/null @@ -1,42 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT -// -// Copyright 2019 Armadeus Systems - -/dts-v1/; -#include "imx6ull-opos6ul.dtsi" -#include "imx6ul-imx6ull-opos6uldev.dtsi" - -/ { - model = "Armadeus Systems OPOS6UL SoM (i.MX6ULL) on OPOS6ULDev board"; - compatible = "armadeus,imx6ull-opos6uldev", "armadeus,imx6ull-opos6ul", "fsl,imx6ull"; -}; - -&iomuxc_snvs { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_tamper_gpios>; - - pinctrl_tamper_gpios: tampergpiosgrp { - fsl,pins = < - MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x0b0b0 - MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0b0b0 - MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0b0b0 - MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x0b0b0 - MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0b0b0 - MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0b0b0 - MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0b0b0 - MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x0b0b0 - >; - }; - - pinctrl_usbotg2_vbus: usbotg2vbusgrp { - fsl,pins = < - MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x1b0b0 - >; - }; - - pinctrl_w1: w1grp { - fsl,pins = < - MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x0b0b0 - >; - }; -}; diff --git a/sys/gnu/dts/arm/imx6ull-phytec-phycore-som.dtsi b/sys/gnu/dts/arm/imx6ull-phytec-phycore-som.dtsi deleted file mode 100644 index 56cd16e5a77..00000000000 --- a/sys/gnu/dts/arm/imx6ull-phytec-phycore-som.dtsi +++ /dev/null @@ -1,24 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2019 PHYTEC Messtechnik GmbH - * Author: Stefan Riedmueller - */ - -#include "imx6ul-phytec-phycore-som.dtsi" - -/ { - model = "PHYTEC phyCORE-i.MX6 ULL"; - compatible = "phytec,imx6ull-pcl063", "fsl,imx6ull"; -}; - -&iomuxc { - /delete-node/ gpioledssomgrp; -}; - -&iomuxc_snvs { - pinctrl_gpioleds_som: gpioledssomgrp { - fsl,pins = < - MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x0b0b0 - >; - }; -}; diff --git a/sys/gnu/dts/arm/imx6ull-phytec-segin-ff-rdk-emmc.dts b/sys/gnu/dts/arm/imx6ull-phytec-segin-ff-rdk-emmc.dts deleted file mode 100644 index 9648d4ecaf5..00000000000 --- a/sys/gnu/dts/arm/imx6ull-phytec-segin-ff-rdk-emmc.dts +++ /dev/null @@ -1,93 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2019 PHYTEC Messtechnik GmbH - * Author: Stefan Riedmueller - */ - -/dts-v1/; -#include "imx6ull.dtsi" -#include "imx6ull-phytec-phycore-som.dtsi" -#include "imx6ull-phytec-segin.dtsi" -#include "imx6ull-phytec-segin-peb-eval-01.dtsi" - -/ { - model = "PHYTEC phyBOARD-Segin i.MX6 ULL Full Featured with eMMC"; - compatible = "phytec,imx6ull-pbacd10-emmc", "phytec,imx6ull-pbacd10", - "phytec,imx6ull-pcl063","fsl,imx6ull"; -}; - -&adc1 { - status = "okay"; -}; - -&can1 { - status = "okay"; -}; - -&tlv320 { - status = "okay"; -}; - -&ecspi3 { - status = "okay"; -}; - -ðphy1 { - status = "okay"; -}; - -ðphy2 { - status = "okay"; -}; - -&fec1 { - status = "okay"; -}; - -&fec2 { - status = "okay"; -}; - -&i2c_rtc { - status = "okay"; -}; - -®_can1_en { - status = "okay"; -}; - -®_sound_1v8 { - status = "okay"; -}; - -®_sound_3v3 { - status = "okay"; -}; - -&sai2 { - status = "okay"; -}; - -&sound { - status = "okay"; -}; - -&uart5 { - status = "okay"; -}; - -&usbotg1 { - status = "okay"; -}; - -&usbotg2 { - status = "okay"; -}; - -&usdhc1 { - status = "okay"; -}; - -&usdhc2 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx6ull-phytec-segin-ff-rdk-nand.dts b/sys/gnu/dts/arm/imx6ull-phytec-segin-ff-rdk-nand.dts deleted file mode 100644 index 656baf84645..00000000000 --- a/sys/gnu/dts/arm/imx6ull-phytec-segin-ff-rdk-nand.dts +++ /dev/null @@ -1,93 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2019 PHYTEC Messtechnik GmbH - * Author: Stefan Riedmueller - */ - -/dts-v1/; -#include "imx6ull.dtsi" -#include "imx6ull-phytec-phycore-som.dtsi" -#include "imx6ull-phytec-segin.dtsi" -#include "imx6ull-phytec-segin-peb-eval-01.dtsi" - -/ { - model = "PHYTEC phyBOARD-Segin i.MX6 ULL Full Featured with NAND"; - compatible = "phytec,imx6ull-pbacd10-nand", "phytec,imx6ull-pbacd10", - "phytec,imx6ull-pcl063", "fsl,imx6ull"; -}; - -&adc1 { - status = "okay"; -}; - -&can1 { - status = "okay"; -}; - -&tlv320 { - status = "okay"; -}; - -&ecspi3 { - status = "okay"; -}; - -ðphy1 { - status = "okay"; -}; - -ðphy2 { - status = "okay"; -}; - -&fec1 { - status = "okay"; -}; - -&fec2 { - status = "okay"; -}; - -&gpmi { - status = "okay"; -}; - -&i2c_rtc { - status = "okay"; -}; - -®_can1_en { - status = "okay"; -}; - -®_sound_1v8 { - status = "okay"; -}; - -®_sound_3v3 { - status = "okay"; -}; - -&sai2 { - status = "okay"; -}; - -&sound { - status = "okay"; -}; - -&uart5 { - status = "okay"; -}; - -&usbotg1 { - status = "okay"; -}; - -&usbotg2 { - status = "okay"; -}; - -&usdhc1 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx6ull-phytec-segin-lc-rdk-nand.dts b/sys/gnu/dts/arm/imx6ull-phytec-segin-lc-rdk-nand.dts deleted file mode 100644 index e168494e0a6..00000000000 --- a/sys/gnu/dts/arm/imx6ull-phytec-segin-lc-rdk-nand.dts +++ /dev/null @@ -1,45 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2019 PHYTEC Messtechnik GmbH - * Author: Stefan Riedmueller - */ - -/dts-v1/; -#include "imx6ull.dtsi" -#include "imx6ull-phytec-phycore-som.dtsi" -#include "imx6ull-phytec-segin.dtsi" -#include "imx6ull-phytec-segin-peb-eval-01.dtsi" - -/ { - model = "PHYTEC phyBOARD-Segin i.MX6 ULL Low Cost with NAND"; - compatible = "phytec,imx6ull-pbacd10-nand", "phytec,imx6ull-pbacd10", - "phytec,imx6ull-pcl063", "fsl,imx6ull"; -}; - -&adc1 { - status = "okay"; -}; - -ðphy1 { - status = "okay"; -}; - -&fec1 { - status = "okay"; -}; - -&gpmi { - status = "okay"; -}; - -&i2c_rtc { - status = "okay"; -}; - -&usbotg1 { - status = "okay"; -}; - -&usdhc1 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx6ull-phytec-segin-peb-eval-01.dtsi b/sys/gnu/dts/arm/imx6ull-phytec-segin-peb-eval-01.dtsi deleted file mode 100644 index ff08d95a1aa..00000000000 --- a/sys/gnu/dts/arm/imx6ull-phytec-segin-peb-eval-01.dtsi +++ /dev/null @@ -1,19 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2019 PHYTEC Messtechnik GmbH - * Author: Stefan Riedmueller - */ - -#include "imx6ul-phytec-segin-peb-eval-01.dtsi" - -&iomuxc { - /delete-node/ gpio_keysgrp; -}; - -&iomuxc_snvs { - pinctrl_gpio_keys: gpio_keysgrp { - fsl,pins = < - MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x79 - >; - }; -}; diff --git a/sys/gnu/dts/arm/imx6ull-phytec-segin.dtsi b/sys/gnu/dts/arm/imx6ull-phytec-segin.dtsi deleted file mode 100644 index c1595fc785f..00000000000 --- a/sys/gnu/dts/arm/imx6ull-phytec-segin.dtsi +++ /dev/null @@ -1,38 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2019 PHYTEC Messtechnik GmbH - * Author: Stefan Riedmueller - */ - -#include "imx6ul-phytec-segin.dtsi" - -/ { - model = "PHYTEC phyBOARD-Segin i.MX6 ULL"; - compatible = "phytec,imx6ull-pbacd-10", "phytec,imx6ull-pcl063","fsl,imx6ull"; -}; - -&iomuxc { - /delete-node/ flexcan1engrp; - /delete-node/ rtcintgrp; - /delete-node/ stmpegrp; -}; - -&iomuxc_snvs { - princtrl_flexcan1_en: flexcan1engrp { - fsl,pins = < - MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x17059 - >; - }; - - pinctrl_rtc_int: rtcintgrp { - fsl,pins = < - MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x17059 - >; - }; - - pinctrl_stmpe: stmpegrp { - fsl,pins = < - MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x17059 - >; - }; -}; diff --git a/sys/gnu/dts/arm/imx6ull-pinfunc-snvs.h b/sys/gnu/dts/arm/imx6ull-pinfunc-snvs.h deleted file mode 100644 index 54cfe72295a..00000000000 --- a/sys/gnu/dts/arm/imx6ull-pinfunc-snvs.h +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2016 Freescale Semiconductor, Inc. - * Copyright (C) 2017 NXP - */ - -#ifndef __DTS_IMX6ULL_PINFUNC_SNVS_H -#define __DTS_IMX6ULL_PINFUNC_SNVS_H -/* - * The pin function ID is a tuple of - * - */ -#define MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10 0x0000 0x0044 0x0000 0x5 0x0 -#define MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x0004 0x0048 0x0000 0x5 0x0 -#define MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x0008 0x004C 0x0000 0x5 0x0 -#define MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x000C 0x0050 0x0000 0x5 0x0 -#define MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0010 0x0054 0x0000 0x5 0x0 -#define MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0014 0x0058 0x0000 0x5 0x0 -#define MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x0018 0x005C 0x0000 0x5 0x0 -#define MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x001C 0x0060 0x0000 0x5 0x0 -#define MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0020 0x0064 0x0000 0x5 0x0 -#define MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0024 0x0068 0x0000 0x5 0x0 -#define MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x0028 0x006C 0x0000 0x5 0x0 -#define MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x002C 0x0070 0x0000 0x5 0x0 - -#endif /* __DTS_IMX6ULL_PINFUNC_SNVS_H */ diff --git a/sys/gnu/dts/arm/imx6ull-pinfunc.h b/sys/gnu/dts/arm/imx6ull-pinfunc.h deleted file mode 100644 index eb025a9d475..00000000000 --- a/sys/gnu/dts/arm/imx6ull-pinfunc.h +++ /dev/null @@ -1,87 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) 2016 Freescale Semiconductor, Inc. - */ - -#ifndef __DTS_IMX6ULL_PINFUNC_H -#define __DTS_IMX6ULL_PINFUNC_H - -#include "imx6ul-pinfunc.h" -/* - * The pin function ID is a tuple of - * - */ -/* signals common for i.MX6UL and i.MX6ULL */ -#undef MX6UL_PAD_UART5_TX_DATA__UART5_DTE_RX -#define MX6UL_PAD_UART5_TX_DATA__UART5_DTE_RX 0x00BC 0x0348 0x0644 0x0 0x6 -#undef MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX -#define MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x00C0 0x034C 0x0644 0x0 0x7 -#undef MX6UL_PAD_ENET1_RX_EN__UART5_DCE_RTS -#define MX6UL_PAD_ENET1_RX_EN__UART5_DCE_RTS 0x00CC 0x0358 0x0640 0x1 0x5 -#undef MX6UL_PAD_ENET1_TX_DATA0__UART5_DTE_RTS -#define MX6UL_PAD_ENET1_TX_DATA0__UART5_DTE_RTS 0x00D0 0x035C 0x0640 0x1 0x6 -#undef MX6UL_PAD_CSI_DATA02__UART5_DCE_RTS -#define MX6UL_PAD_CSI_DATA02__UART5_DCE_RTS 0x01EC 0x0478 0x0640 0x8 0x7 - -/* signals for i.MX6ULL only */ -#define MX6ULL_PAD_UART1_TX_DATA__UART5_DCE_TX 0x0084 0x0310 0x0000 0x9 0x0 -#define MX6ULL_PAD_UART1_TX_DATA__UART5_DTE_RX 0x0084 0x0310 0x0644 0x9 0x4 -#define MX6ULL_PAD_UART1_RX_DATA__UART5_DCE_RX 0x0088 0x0314 0x0644 0x9 0x5 -#define MX6ULL_PAD_UART1_RX_DATA__UART5_DTE_TX 0x0088 0x0314 0x0000 0x9 0x0 -#define MX6ULL_PAD_UART1_CTS_B__UART5_DCE_CTS 0x008C 0x0318 0x0000 0x9 0x0 -#define MX6ULL_PAD_UART1_CTS_B__UART5_DTE_RTS 0x008C 0x0318 0x0640 0x9 0x3 -#define MX6ULL_PAD_UART1_RTS_B__UART5_DCE_RTS 0x0090 0x031C 0x0640 0x9 0x4 -#define MX6ULL_PAD_UART1_RTS_B__UART5_DTE_CTS 0x0090 0x031C 0x0000 0x9 0x0 -#define MX6ULL_PAD_UART4_RX_DATA__EPDC_PWRCTRL01 0x00B8 0x0344 0x0000 0x9 0x0 -#define MX6ULL_PAD_UART5_TX_DATA__EPDC_PWRCTRL02 0x00BC 0x0348 0x0000 0x9 0x0 -#define MX6ULL_PAD_UART5_RX_DATA__EPDC_PWRCTRL03 0x00C0 0x034C 0x0000 0x9 0x0 -#define MX6ULL_PAD_ENET1_RX_DATA0__EPDC_SDCE04 0x00C4 0x0350 0x0000 0x9 0x0 -#define MX6ULL_PAD_ENET1_RX_DATA1__EPDC_SDCE05 0x00C8 0x0354 0x0000 0x9 0x0 -#define MX6ULL_PAD_ENET1_RX_EN__EPDC_SDCE06 0x00CC 0x0358 0x0000 0x9 0x0 -#define MX6ULL_PAD_ENET1_TX_DATA0__EPDC_SDCE07 0x00D0 0x035C 0x0000 0x9 0x0 -#define MX6ULL_PAD_ENET1_TX_DATA1__EPDC_SDCE08 0x00D4 0x0360 0x0000 0x9 0x0 -#define MX6ULL_PAD_ENET1_TX_EN__EPDC_SDCE09 0x00D8 0x0364 0x0000 0x9 0x0 -#define MX6ULL_PAD_ENET1_TX_CLK__EPDC_SDOED 0x00DC 0x0368 0x0000 0x9 0x0 -#define MX6ULL_PAD_ENET1_RX_ER__EPDC_SDOEZ 0x00E0 0x036C 0x0000 0x9 0x0 -#define MX6ULL_PAD_ENET2_RX_DATA0__EPDC_SDDO08 0x00E4 0x0370 0x0000 0x9 0x0 -#define MX6ULL_PAD_ENET2_RX_DATA1__EPDC_SDDO09 0x00E8 0x0374 0x0000 0x9 0x0 -#define MX6ULL_PAD_ENET2_RX_EN__EPDC_SDDO10 0x00EC 0x0378 0x0000 0x9 0x0 -#define MX6ULL_PAD_ENET2_TX_DATA0__EPDC_SDDO11 0x00F0 0x037C 0x0000 0x9 0x0 -#define MX6ULL_PAD_ENET2_TX_DATA1__EPDC_SDDO12 0x00F4 0x0380 0x0000 0x9 0x0 -#define MX6ULL_PAD_ENET2_TX_EN__EPDC_SDDO13 0x00F8 0x0384 0x0000 0x9 0x0 -#define MX6ULL_PAD_ENET2_TX_CLK__EPDC_SDDO14 0x00FC 0x0388 0x0000 0x9 0x0 -#define MX6ULL_PAD_ENET2_RX_ER__EPDC_SDDO15 0x0100 0x038C 0x0000 0x9 0x0 -#define MX6ULL_PAD_LCD_CLK__EPDC_SDCLK 0x0104 0x0390 0x0000 0x9 0x0 -#define MX6ULL_PAD_LCD_ENABLE__EPDC_SDLE 0x0108 0x0394 0x0000 0x9 0x0 -#define MX6ULL_PAD_LCD_HSYNC__EPDC_SDOE 0x010C 0x0398 0x0000 0x9 0x0 -#define MX6ULL_PAD_LCD_VSYNC__EPDC_SDCE0 0x0110 0x039C 0x0000 0x9 0x0 -#define MX6ULL_PAD_LCD_RESET__EPDC_GDOE 0x0114 0x03A0 0x0000 0x9 0x0 -#define MX6ULL_PAD_LCD_DATA00__EPDC_SDDO00 0x0118 0x03A4 0x0000 0x9 0x0 -#define MX6ULL_PAD_LCD_DATA01__EPDC_SDDO01 0x011C 0x03A8 0x0000 0x9 0x0 -#define MX6ULL_PAD_LCD_DATA02__EPDC_SDDO02 0x0120 0x03AC 0x0000 0x9 0x0 -#define MX6ULL_PAD_LCD_DATA03__EPDC_SDDO03 0x0124 0x03B0 0x0000 0x9 0x0 -#define MX6ULL_PAD_LCD_DATA04__EPDC_SDDO04 0x0128 0x03B4 0x0000 0x9 0x0 -#define MX6ULL_PAD_LCD_DATA05__EPDC_SDDO05 0x012C 0x03B8 0x0000 0x9 0x0 -#define MX6ULL_PAD_LCD_DATA06__EPDC_SDDO06 0x0130 0x03BC 0x0000 0x9 0x0 -#define MX6ULL_PAD_LCD_DATA07__EPDC_SDDO07 0x0134 0x03C0 0x0000 0x9 0x0 -#define MX6ULL_PAD_LCD_DATA14__EPDC_SDSHR 0x0150 0x03DC 0x0000 0x9 0x0 -#define MX6ULL_PAD_LCD_DATA15__EPDC_GDRL 0x0154 0x03E0 0x0000 0x9 0x0 -#define MX6ULL_PAD_LCD_DATA16__EPDC_GDCLK 0x0158 0x03E4 0x0000 0x9 0x0 -#define MX6ULL_PAD_LCD_DATA17__EPDC_GDSP 0x015C 0x03E8 0x0000 0x9 0x0 -#define MX6ULL_PAD_LCD_DATA21__EPDC_SDCE1 0x016C 0x03F8 0x0000 0x9 0x0 -#define MX6ULL_PAD_LCD_DATA22__EPDC_SDCE02 0x0170 0x03FC 0x0000 0x9 0x0 -#define MX6ULL_PAD_LCD_DATA23__EPDC_SDCE03 0x0174 0x0400 0x0000 0x9 0x0 -#define MX6ULL_PAD_CSI_MCLK__ESAI_TX3_RX2 0x01D4 0x0460 0x0000 0x9 0x0 -#define MX6ULL_PAD_CSI_PIXCLK__ESAI_TX2_RX3 0x01D8 0x0464 0x0000 0x9 0x0 -#define MX6ULL_PAD_CSI_VSYNC__ESAI_TX4_RX1 0x01DC 0x0468 0x0000 0x9 0x0 -#define MX6ULL_PAD_CSI_HSYNC__ESAI_TX1 0x01E0 0x046C 0x0000 0x9 0x0 -#define MX6ULL_PAD_CSI_DATA00__ESAI_TX_HF_CLK 0x01E4 0x0470 0x0000 0x9 0x0 -#define MX6ULL_PAD_CSI_DATA01__ESAI_RX_HF_CLK 0x01E8 0x0474 0x0000 0x9 0x0 -#define MX6ULL_PAD_CSI_DATA02__ESAI_RX_FS 0x01EC 0x0478 0x0000 0x9 0x0 -#define MX6ULL_PAD_CSI_DATA03__ESAI_RX_CLK 0x01F0 0x047C 0x0000 0x9 0x0 -#define MX6ULL_PAD_CSI_DATA04__ESAI_TX_FS 0x01F4 0x0480 0x0000 0x9 0x0 -#define MX6ULL_PAD_CSI_DATA05__ESAI_TX_CLK 0x01F8 0x0484 0x0000 0x9 0x0 -#define MX6ULL_PAD_CSI_DATA06__ESAI_TX5_RX0 0x01FC 0x0488 0x0000 0x9 0x0 -#define MX6ULL_PAD_CSI_DATA07__ESAI_T0 0x0200 0x048C 0x0000 0x9 0x0 - -#endif /* __DTS_IMX6ULL_PINFUNC_H */ diff --git a/sys/gnu/dts/arm/imx6ull.dtsi b/sys/gnu/dts/arm/imx6ull.dtsi deleted file mode 100644 index b7e67d12132..00000000000 --- a/sys/gnu/dts/arm/imx6ull.dtsi +++ /dev/null @@ -1,88 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -// -// Copyright 2016 Freescale Semiconductor, Inc. - -#include "imx6ul.dtsi" -#include "imx6ull-pinfunc.h" -#include "imx6ull-pinfunc-snvs.h" - -/* Delete UART8 in AIPS-1 (i.MX6UL specific) */ -/delete-node/ &uart8; -/* Delete CAAM node in AIPS-2 (i.MX6UL specific) */ -/delete-node/ &crypto; - -&cpu0 { - clock-frequency = <900000000>; - operating-points = < - /* kHz uV */ - 900000 1275000 - 792000 1225000 - 528000 1175000 - 396000 1025000 - 198000 950000 - >; - fsl,soc-operating-points = < - /* KHz uV */ - 900000 1250000 - 792000 1175000 - 528000 1175000 - 396000 1175000 - 198000 1175000 - >; -}; - -&ocotp { - compatible = "fsl,imx6ull-ocotp", "syscon"; -}; - -&pxp { - compatible = "fsl,imx6ull-pxp"; - interrupts = , - ; -}; - -&usdhc1 { - compatible = "fsl,imx6ull-usdhc", "fsl,imx6sx-usdhc"; -}; - -&usdhc2 { - compatible = "fsl,imx6ull-usdhc", "fsl,imx6sx-usdhc"; -}; - -/ { - soc { - aips3: aips-bus@2200000 { - compatible = "fsl,aips-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x02200000 0x100000>; - ranges; - - dcp: crypto@2280000 { - compatible = "fsl,imx6ull-dcp", "fsl,imx28-dcp"; - reg = <0x02280000 0x4000>; - interrupts = , - , - ; - clocks = <&clks IMX6ULL_CLK_DCP_CLK>; - clock-names = "dcp"; - }; - - iomuxc_snvs: iomuxc-snvs@2290000 { - compatible = "fsl,imx6ull-iomuxc-snvs"; - reg = <0x02290000 0x4000>; - }; - - uart8: serial@2288000 { - compatible = "fsl,imx6ul-uart", - "fsl,imx6q-uart"; - reg = <0x02288000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_UART8_IPG>, - <&clks IMX6UL_CLK_UART8_SERIAL>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/imx6ulz-14x14-evk.dts b/sys/gnu/dts/arm/imx6ulz-14x14-evk.dts deleted file mode 100644 index 483d9732c00..00000000000 --- a/sys/gnu/dts/arm/imx6ulz-14x14-evk.dts +++ /dev/null @@ -1,22 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -// -// Copyright 2018 NXP. - -/dts-v1/; - -#include "imx6ulz.dtsi" -#include "imx6ul-14x14-evk.dtsi" - -/delete-node/ &fec1; -/delete-node/ &fec2; -/delete-node/ &can1; -/delete-node/ &can2; -/delete-node/ &lcdif; -/delete-node/ &tsc; - -/ { - model = "Freescale i.MX6 ULZ 14x14 EVK Board"; - compatible = "fsl,imx6ulz-14x14-evk", "fsl,imx6ull", "fsl,imx6ulz"; - - /delete-node/ panel; -}; diff --git a/sys/gnu/dts/arm/imx6ulz.dtsi b/sys/gnu/dts/arm/imx6ulz.dtsi deleted file mode 100644 index 0b5f1a76356..00000000000 --- a/sys/gnu/dts/arm/imx6ulz.dtsi +++ /dev/null @@ -1,36 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -// -// Copyright 2018 NXP. - -#include "imx6ull.dtsi" - -/ { - aliases { - /delete-property/ ethernet0; - /delete-property/ ethernet1; - /delete-property/ i2c2; - /delete-property/ i2c3; - /delete-property/ serial4; - /delete-property/ serial5; - /delete-property/ serial6; - /delete-property/ serial7; - /delete-property/ spi2; - /delete-property/ spi3; - }; -}; - -/delete-node/ &adc1; -/delete-node/ &ecspi3; -/delete-node/ &ecspi4; -/delete-node/ &epit2; -/delete-node/ &gpt2; -/delete-node/ &i2c3; -/delete-node/ &i2c4; -/delete-node/ &pwm5; -/delete-node/ &pwm6; -/delete-node/ &pwm7; -/delete-node/ &pwm8; -/delete-node/ &uart5; -/delete-node/ &uart6; -/delete-node/ &uart7; -/delete-node/ &uart8; diff --git a/sys/gnu/dts/arm/imx7-colibri-eval-v3.dtsi b/sys/gnu/dts/arm/imx7-colibri-eval-v3.dtsi deleted file mode 100644 index 6aa123cbdad..00000000000 --- a/sys/gnu/dts/arm/imx7-colibri-eval-v3.dtsi +++ /dev/null @@ -1,226 +0,0 @@ -/* - * Copyright 2016 Toradex AG - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/ { - chosen { - stdout-path = "serial0:115200n8"; - }; - - /* fixed crystal dedicated to mpc258x */ - clk16m: clk16m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <16000000>; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpiokeys>; - - power { - label = "Wake-Up"; - gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; - linux,code = ; - debounce-interval = <10>; - wakeup-source; - }; - }; - - panel: panel { - compatible = "edt,et057090dhu"; - backlight = <&bl>; - power-supply = <®_3v3>; - - port { - panel_in: endpoint { - remote-endpoint = <&lcdif_out>; - }; - }; - }; - - reg_3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_5v0: regulator-5v0 { - compatible = "regulator-fixed"; - regulator-name = "5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_usbh_vbus: regulator-usbh-vbus { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh_reg>; - regulator-name = "VCC_USB[1-4]"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio4 7 GPIO_ACTIVE_LOW>; - vin-supply = <®_5v0>; - }; -}; - -&bl { - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - power-supply = <®_3v3>; - - status = "okay"; -}; - -&adc1 { - status = "okay"; -}; - -&adc2 { - status = "okay"; -}; - -&ecspi3 { - status = "okay"; - - mcp2515: can@0 { - compatible = "microchip,mcp2515"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can_int>; - reg = <0>; - clocks = <&clk16m>; - interrupt-parent = <&gpio5>; - interrupts = <2 IRQ_TYPE_EDGE_FALLING>; - spi-max-frequency = <10000000>; - vdd-supply = <®_3v3>; - xceiver-supply = <®_5v0>; - status = "okay"; - }; -}; - -&fec1 { - status = "okay"; -}; - -&i2c4 { - status = "okay"; - - /* - * Touchscreen is using SODIMM 28/30, also used for PWM, PWM, - * aka pwm2, pwm3. so if you enable touchscreen, disable the pwms - */ - touchscreen@4a { - compatible = "atmel,maxtouch"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpiotouch>; - reg = <0x4a>; - interrupt-parent = <&gpio1>; - interrupts = <9 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 28 */ - reset-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; /* SODIMM 30 */ - status = "disabled"; - }; - - /* M41T0M6 real time clock on carrier board */ - rtc: m41t0m6@68 { - compatible = "st,m41t0"; - reg = <0x68>; - }; -}; - -&lcdif { - status = "okay"; - - port { - lcdif_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; -}; - -&pwm1 { - status = "okay"; -}; - -&pwm2 { - status = "okay"; -}; - -&pwm3 { - status = "okay"; -}; - -&pwm4 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&usbotg1 { - status = "okay"; -}; - -&usdhc1 { - keep-power-in-suspend; - wakeup-source; - vmmc-supply = <®_3v3>; - status = "okay"; -}; - -&iomuxc { - pinctrl_gpiotouch: touchgpios { - fsl,pins = < - MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x74 - MX7D_PAD_GPIO1_IO10__GPIO1_IO10 0x14 - >; - }; -}; diff --git a/sys/gnu/dts/arm/imx7-colibri.dtsi b/sys/gnu/dts/arm/imx7-colibri.dtsi deleted file mode 100644 index 04717cf69db..00000000000 --- a/sys/gnu/dts/arm/imx7-colibri.dtsi +++ /dev/null @@ -1,797 +0,0 @@ -/* - * Copyright 2016 Toradex AG - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/ { - bl: backlight { - compatible = "pwm-backlight"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_bl_on>; - pwms = <&pwm1 0 5000000 0>; - enable-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; - }; - - reg_module_3v3: regulator-module-3v3 { - compatible = "regulator-fixed"; - regulator-name = "+V3.3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_module_3v3_avdd: regulator-module-3v3-avdd { - compatible = "regulator-fixed"; - regulator-name = "+V3.3_AVDD_AUDIO"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "imx7-sgtl5000"; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&dailink_master>; - simple-audio-card,frame-master = <&dailink_master>; - simple-audio-card,cpu { - sound-dai = <&sai1>; - }; - - dailink_master: simple-audio-card,codec { - sound-dai = <&codec>; - clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; - }; - }; -}; - -&adc1 { - vref-supply = <®_DCDC3>; -}; - -&adc2 { - vref-supply = <®_DCDC3>; -}; - -&cpu0 { - cpu-supply = <®_DCDC2>; -}; - -&ecspi3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3_cs>; - cs-gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>; -}; - -&fec1 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&pinctrl_enet1>; - pinctrl-1 = <&pinctrl_enet1_sleep>; - clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>, - <&clks IMX7D_ENET_AXI_ROOT_CLK>, - <&clks IMX7D_ENET1_TIME_ROOT_CLK>, - <&clks IMX7D_PLL_ENET_MAIN_50M_CLK>; - clock-names = "ipg", "ahb", "ptp", "enet_clk_ref"; - assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>, - <&clks IMX7D_ENET1_TIME_ROOT_CLK>; - assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; - assigned-clock-rates = <0>, <100000000>; - phy-mode = "rmii"; - phy-supply = <®_LDO1>; - fsl,magic-packet; -}; - -&flexcan1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - status = "disabled"; -}; - -&flexcan2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - status = "disabled"; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - fsl,use-minimum-ecc; - nand-on-flash-bbt; - nand-ecc-mode = "hw"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c1 &pinctrl_i2c1_int>; - pinctrl-1 = <&pinctrl_i2c1_recovery &pinctrl_i2c1_int>; - scl-gpios = <&gpio1 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio1 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - - status = "okay"; - - codec: sgtl5000@a { - compatible = "fsl,sgtl5000"; - #sound-dai-cells = <0>; - reg = <0x0a>; - clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai1_mclk>; - VDDA-supply = <®_module_3v3_avdd>; - VDDIO-supply = <®_module_3v3>; - VDDD-supply = <®_DCDC3>; - }; - - ad7879@2c { - compatible = "adi,ad7879-1"; - reg = <0x2c>; - interrupt-parent = <&gpio1>; - interrupts = <13 IRQ_TYPE_EDGE_FALLING>; - touchscreen-max-pressure = <4096>; - adi,resistance-plate-x = <120>; - adi,first-conversion-delay = /bits/ 8 <3>; - adi,acquisition-time = /bits/ 8 <1>; - adi,median-filter-size = /bits/ 8 <2>; - adi,averaging = /bits/ 8 <1>; - adi,conversion-interval = /bits/ 8 <255>; - }; - - pmic@33 { - compatible = "ricoh,rn5t567"; - reg = <0x33>; - - regulators { - reg_DCDC1: DCDC1 { /* V1.0_SOC */ - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1100000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_DCDC2: DCDC2 { /* V1.1_ARM */ - regulator-min-microvolt = <975000>; - regulator-max-microvolt = <1100000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_DCDC3: DCDC3 { /* V1.8 */ - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_DCDC4: DCDC4 { /* V1.35_DRAM */ - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_LDO1: LDO1 { /* PWR_EN_+V3.3_ETH */ - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; - - reg_LDO2: LDO2 { /* +V1.8_SD */ - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_LDO3: LDO3 { /* PWR_EN_+V3.3_LPSR */ - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_LDO4: LDO4 { /* V1.8_LPSR */ - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_LDO5: LDO5 { /* PWR_EN_+V3.3 */ - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; -}; - -&i2c4 { - clock-frequency = <100000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c4>; - pinctrl-1 = <&pinctrl_i2c4_recovery>; - scl-gpios = <&gpio7 8 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio7 9 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; -}; - -&lcdif { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcdif_dat - &pinctrl_lcdif_ctrl>; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; -}; - -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm2>; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; -}; - -&pwm4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm4>; -}; - -®_1p0d { - vin-supply = <®_DCDC3>; -}; - -&sai1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai1>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_ctrl1 &pinctrl_uart1_ctrl2>; - assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>; - assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; - uart-has-rtscts; - fsl,dte-mode; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - assigned-clocks = <&clks IMX7D_UART2_ROOT_SRC>; - assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; - uart-has-rtscts; - fsl,dte-mode; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>; - assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; - fsl,dte-mode; -}; - -&usbotg1 { - dr_mode = "host"; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_cd_usdhc1>; - cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; - disable-wp; - vqmmc-supply = <®_LDO2>; -}; - -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>; - assigned-clock-rates = <400000000>; - bus-width = <8>; - fsl,tuning-step = <2>; - vmmc-supply = <®_module_3v3>; - vqmmc-supply = <®_DCDC3>; - non-removable; - sdhci-caps-mask = <0x80000000 0x0>; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3 &pinctrl_gpio4 - &pinctrl_gpio7>; - - pinctrl_gpio1: gpio1-grp { - fsl,pins = < - MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 0x14 /* SODIMM 77 */ - MX7D_PAD_EPDC_DATA09__GPIO2_IO9 0x14 /* SODIMM 89 */ - MX7D_PAD_EPDC_DATA08__GPIO2_IO8 0x74 /* SODIMM 91 */ - MX7D_PAD_LCD_RESET__GPIO3_IO4 0x14 /* SODIMM 93 */ - MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x14 /* SODIMM 95 */ - MX7D_PAD_ENET1_RGMII_TXC__GPIO7_IO11 0x14 /* SODIMM 99 */ - MX7D_PAD_EPDC_DATA10__GPIO2_IO10 0x74 /* SODIMM 105 */ - MX7D_PAD_EPDC_DATA15__GPIO2_IO15 0x74 /* SODIMM 107 */ - MX7D_PAD_EPDC_DATA00__GPIO2_IO0 0x14 /* SODIMM 111 */ - MX7D_PAD_EPDC_DATA01__GPIO2_IO1 0x14 /* SODIMM 113 */ - MX7D_PAD_EPDC_DATA02__GPIO2_IO2 0x14 /* SODIMM 115 */ - MX7D_PAD_EPDC_DATA03__GPIO2_IO3 0x14 /* SODIMM 117 */ - MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x14 /* SODIMM 119 */ - MX7D_PAD_EPDC_DATA05__GPIO2_IO5 0x14 /* SODIMM 121 */ - MX7D_PAD_EPDC_DATA06__GPIO2_IO6 0x14 /* SODIMM 123 */ - MX7D_PAD_EPDC_DATA07__GPIO2_IO7 0x14 /* SODIMM 125 */ - MX7D_PAD_EPDC_SDCE2__GPIO2_IO22 0x14 /* SODIMM 127 */ - MX7D_PAD_UART3_RTS_B__GPIO4_IO6 0x14 /* SODIMM 131 */ - MX7D_PAD_EPDC_GDRL__GPIO2_IO26 0x14 /* SODIMM 133 */ - MX7D_PAD_SAI1_RX_DATA__GPIO6_IO12 0x14 /* SODIMM 169 */ - MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17 0x14 /* SODIMM 24 */ - MX7D_PAD_SD2_DATA2__GPIO5_IO16 0x14 /* SODIMM 100 */ - MX7D_PAD_SD2_DATA3__GPIO5_IO17 0x14 /* SODIMM 102 */ - MX7D_PAD_EPDC_GDSP__GPIO2_IO27 0x14 /* SODIMM 104 */ - MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x74 /* SODIMM 106 */ - MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x14 /* SODIMM 110 */ - MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x14 /* SODIMM 112 */ - MX7D_PAD_EPDC_SDCLK__GPIO2_IO16 0x14 /* SODIMM 114 */ - MX7D_PAD_EPDC_SDLE__GPIO2_IO17 0x14 /* SODIMM 116 */ - MX7D_PAD_EPDC_SDOE__GPIO2_IO18 0x14 /* SODIMM 118 */ - MX7D_PAD_EPDC_SDSHR__GPIO2_IO19 0x14 /* SODIMM 120 */ - MX7D_PAD_EPDC_SDCE0__GPIO2_IO20 0x14 /* SODIMM 122 */ - MX7D_PAD_EPDC_SDCE1__GPIO2_IO21 0x14 /* SODIMM 124 */ - MX7D_PAD_EPDC_DATA14__GPIO2_IO14 0x14 /* SODIMM 126 */ - MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 0x14 /* SODIMM 128 */ - MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 0x14 /* SODIMM 130 */ - MX7D_PAD_EPDC_GDCLK__GPIO2_IO24 0x14 /* SODIMM 132 */ - MX7D_PAD_EPDC_GDOE__GPIO2_IO25 0x14 /* SODIMM 134 */ - MX7D_PAD_EPDC_DATA12__GPIO2_IO12 0x14 /* SODIMM 150 */ - MX7D_PAD_EPDC_DATA11__GPIO2_IO11 0x14 /* SODIMM 152 */ - MX7D_PAD_SD2_CLK__GPIO5_IO12 0x14 /* SODIMM 184 */ - MX7D_PAD_SD2_CMD__GPIO5_IO13 0x14 /* SODIMM 186 */ - >; - }; - - pinctrl_gpio2: gpio2-grp { /* On X22 Camera interface */ - fsl,pins = < - MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x14 /* SODIMM 65 */ - MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x74 /* SODIMM 69 */ - MX7D_PAD_I2C4_SDA__GPIO4_IO15 0x14 /* SODIMM 75 */ - MX7D_PAD_ECSPI1_MISO__GPIO4_IO18 0x14 /* SODIMM 79 */ - MX7D_PAD_I2C3_SCL__GPIO4_IO12 0x14 /* SODIMM 81 */ - MX7D_PAD_ECSPI2_MISO__GPIO4_IO22 0x14 /* SODIMM 85 */ - MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 0x14 /* SODIMM 97 */ - MX7D_PAD_ECSPI1_SCLK__GPIO4_IO16 0x14 /* SODIMM 101 */ - MX7D_PAD_ECSPI1_MOSI__GPIO4_IO17 0x14 /* SODIMM 103 */ - MX7D_PAD_I2C3_SDA__GPIO4_IO13 0x14 /* SODIMM 94 */ - MX7D_PAD_I2C4_SCL__GPIO4_IO14 0x14 /* SODIMM 96 */ - MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x14 /* SODIMM 98 */ - >; - }; - - pinctrl_gpio3: gpio3-grp { /* LCD 18-23 */ - fsl,pins = < - MX7D_PAD_LCD_DATA18__GPIO3_IO23 0x14 /* SODIMM 136 */ - MX7D_PAD_LCD_DATA19__GPIO3_IO24 0x14 /* SODIMM 138 */ - MX7D_PAD_LCD_DATA20__GPIO3_IO25 0x14 /* SODIMM 140 */ - MX7D_PAD_LCD_DATA21__GPIO3_IO26 0x14 /* SODIMM 142 */ - MX7D_PAD_LCD_DATA22__GPIO3_IO27 0x74 /* SODIMM 144 */ - MX7D_PAD_LCD_DATA23__GPIO3_IO28 0x74 /* SODIMM 146 */ - >; - }; - - pinctrl_gpio4: gpio4-grp { /* Alternatively CAN2 */ - fsl,pins = < - MX7D_PAD_GPIO1_IO15__GPIO1_IO15 0x14 /* SODIMM 178 */ - MX7D_PAD_GPIO1_IO14__GPIO1_IO14 0x14 /* SODIMM 188 */ - >; - }; - - pinctrl_gpio7: gpio7-grp { /* Alternatively CAN1 */ - fsl,pins = < - MX7D_PAD_ENET1_RGMII_RD3__GPIO7_IO3 0x14 /* SODIMM 55 */ - MX7D_PAD_ENET1_RGMII_RD2__GPIO7_IO2 0x14 /* SODIMM 63 */ - >; - }; - - pinctrl_i2c1_int: i2c1-int-grp { /* PMIC / TOUCH */ - fsl,pins = < - MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x79 - >; - }; - - pinctrl_can_int: can-int-grp { - fsl,pins = < - MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0X14 /* SODIMM 73 */ - >; - }; - - pinctrl_enet1: enet1grp { - fsl,pins = < - MX7D_PAD_ENET1_CRS__GPIO7_IO14 0x14 - MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x73 - MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x73 - MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x73 - MX7D_PAD_ENET1_RGMII_RXC__ENET1_RX_ER 0x73 - - MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x73 - MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x73 - MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x73 - MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 0x73 - MX7D_PAD_SD2_CD_B__ENET1_MDIO 0x3 - MX7D_PAD_SD2_WP__ENET1_MDC 0x3 - >; - }; - - pinctrl_enet1_sleep: enet1sleepgrp { - fsl,pins = < - MX7D_PAD_ENET1_RGMII_RX_CTL__GPIO7_IO4 0x0 - MX7D_PAD_ENET1_RGMII_RD0__GPIO7_IO0 0x0 - MX7D_PAD_ENET1_RGMII_RD1__GPIO7_IO1 0x0 - MX7D_PAD_ENET1_RGMII_RXC__GPIO7_IO5 0x0 - - MX7D_PAD_ENET1_RGMII_TX_CTL__GPIO7_IO10 0x0 - MX7D_PAD_ENET1_RGMII_TD0__GPIO7_IO6 0x0 - MX7D_PAD_ENET1_RGMII_TD1__GPIO7_IO7 0x0 - MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x0 - MX7D_PAD_SD2_CD_B__GPIO5_IO9 0x0 - MX7D_PAD_SD2_WP__GPIO5_IO10 0x0 - >; - }; - - pinctrl_ecspi3_cs: ecspi3-cs-grp { - fsl,pins = < - MX7D_PAD_I2C2_SDA__GPIO4_IO11 0x14 - >; - }; - - pinctrl_ecspi3: ecspi3-grp { - fsl,pins = < - MX7D_PAD_I2C1_SCL__ECSPI3_MISO 0x2 - MX7D_PAD_I2C1_SDA__ECSPI3_MOSI 0x2 - MX7D_PAD_I2C2_SCL__ECSPI3_SCLK 0x2 - >; - }; - - pinctrl_flexcan1: flexcan1-grp { - fsl,pins = < - MX7D_PAD_ENET1_RGMII_RD3__FLEXCAN1_TX 0x79 /* SODIMM 55 */ - MX7D_PAD_ENET1_RGMII_RD2__FLEXCAN1_RX 0x79 /* SODIMM 63 */ - >; - }; - - pinctrl_flexcan2: flexcan2-grp { - fsl,pins = < - MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x79 /* SODIMM 188 */ - MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x79 /* SODIMM 178 */ - >; - }; - - pinctrl_gpio_bl_on: gpio-bl-on { - fsl,pins = < - MX7D_PAD_SD1_WP__GPIO5_IO1 0x14 /* SODIMM 71 */ - >; - }; - - pinctrl_gpmi_nand: gpmi-nand-grp { - fsl,pins = < - MX7D_PAD_SD3_CLK__NAND_CLE 0x71 - MX7D_PAD_SD3_CMD__NAND_ALE 0x71 - MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B 0x71 - MX7D_PAD_SAI1_TX_DATA__NAND_READY_B 0x74 - MX7D_PAD_SD3_STROBE__NAND_RE_B 0x71 - MX7D_PAD_SD3_RESET_B__NAND_WE_B 0x71 - MX7D_PAD_SD3_DATA0__NAND_DATA00 0x71 - MX7D_PAD_SD3_DATA1__NAND_DATA01 0x71 - MX7D_PAD_SD3_DATA2__NAND_DATA02 0x71 - MX7D_PAD_SD3_DATA3__NAND_DATA03 0x71 - MX7D_PAD_SD3_DATA4__NAND_DATA04 0x71 - MX7D_PAD_SD3_DATA5__NAND_DATA05 0x71 - MX7D_PAD_SD3_DATA6__NAND_DATA06 0x71 - MX7D_PAD_SD3_DATA7__NAND_DATA07 0x71 - >; - }; - - pinctrl_i2c4: i2c4-grp { - fsl,pins = < - MX7D_PAD_ENET1_RGMII_TD3__I2C4_SDA 0x4000007f - MX7D_PAD_ENET1_RGMII_TD2__I2C4_SCL 0x4000007f - >; - }; - - pinctrl_i2c4_recovery: i2c4-recoverygrp { - fsl,pins = < - MX7D_PAD_ENET1_RGMII_TD2__GPIO7_IO8 0x4000007f - MX7D_PAD_ENET1_RGMII_TD3__GPIO7_IO9 0x4000007f - >; - }; - - pinctrl_lcdif_dat: lcdif-dat-grp { - fsl,pins = < - MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79 - MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79 - MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79 - MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79 - MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79 - MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79 - MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79 - MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79 - MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79 - MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79 - MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79 - MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79 - MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79 - MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79 - MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79 - MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79 - MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79 - MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79 - >; - }; - - pinctrl_lcdif_dat_24: lcdif-dat-24-grp { - fsl,pins = < - MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79 - MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79 - MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79 - MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79 - MX7D_PAD_LCD_DATA22__LCD_DATA22 0x79 - MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79 - >; - }; - - pinctrl_lcdif_ctrl: lcdif-ctrl-grp { - fsl,pins = < - MX7D_PAD_LCD_CLK__LCD_CLK 0x79 - MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x79 - MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x79 - MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x79 - >; - }; - - pinctrl_pwm1: pwm1-grp { - fsl,pins = < - MX7D_PAD_GPIO1_IO08__PWM1_OUT 0x79 - MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x4 - >; - }; - - pinctrl_pwm2: pwm2-grp { - fsl,pins = < - MX7D_PAD_GPIO1_IO09__PWM2_OUT 0x79 - >; - }; - - pinctrl_pwm3: pwm3-grp { - fsl,pins = < - MX7D_PAD_GPIO1_IO10__PWM3_OUT 0x79 - >; - }; - - pinctrl_pwm4: pwm4-grp { - fsl,pins = < - MX7D_PAD_GPIO1_IO11__PWM4_OUT 0x79 - MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20 0x4 - >; - }; - - pinctrl_uart1: uart1-grp { - fsl,pins = < - MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX 0x79 - MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX 0x79 - MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS 0x79 - MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS 0x79 - >; - }; - - pinctrl_uart1_ctrl1: uart1-ctrl1-grp { - fsl,pins = < - MX7D_PAD_SD2_DATA1__GPIO5_IO15 0x14 /* DCD */ - MX7D_PAD_SD2_DATA0__GPIO5_IO14 0x14 /* DTR */ - >; - }; - - pinctrl_uart2: uart2-grp { - fsl,pins = < - MX7D_PAD_UART2_TX_DATA__UART2_DTE_RX 0x79 - MX7D_PAD_UART2_RX_DATA__UART2_DTE_TX 0x79 - MX7D_PAD_SAI2_RX_DATA__UART2_DTE_RTS 0x79 - MX7D_PAD_SAI2_TX_DATA__UART2_DTE_CTS 0x79 - >; - }; - pinctrl_uart3: uart3-grp { - fsl,pins = < - MX7D_PAD_UART3_TX_DATA__UART3_DTE_RX 0x79 - MX7D_PAD_UART3_RX_DATA__UART3_DTE_TX 0x79 - >; - }; - - pinctrl_usbh_reg: gpio-usbh-vbus { - fsl,pins = < - MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x14 /* SODIMM 129 USBH PEN */ - >; - }; - - pinctrl_usdhc1: usdhc1-grp { - fsl,pins = < - MX7D_PAD_SD1_CMD__SD1_CMD 0x59 - MX7D_PAD_SD1_CLK__SD1_CLK 0x19 - MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 - MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 - MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 - MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1grp_100mhz { - fsl,pins = < - MX7D_PAD_SD1_CMD__SD1_CMD 0x5a - MX7D_PAD_SD1_CLK__SD1_CLK 0x1a - MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a - MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a - MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a - MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1grp_200mhz { - fsl,pins = < - MX7D_PAD_SD1_CMD__SD1_CMD 0x5b - MX7D_PAD_SD1_CLK__SD1_CLK 0x1b - MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b - MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b - MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b - MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX7D_PAD_SD3_CMD__SD3_CMD 0x59 - MX7D_PAD_SD3_CLK__SD3_CLK 0x19 - MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 - MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 - MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 - MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 - MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 - MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 - MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 - MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 - MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { - fsl,pins = < - MX7D_PAD_SD3_CMD__SD3_CMD 0x5a - MX7D_PAD_SD3_CLK__SD3_CLK 0x1a - MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a - MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a - MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a - MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a - MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a - MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a - MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a - MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a - MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3grp_200mhz { - fsl,pins = < - MX7D_PAD_SD3_CMD__SD3_CMD 0x5b - MX7D_PAD_SD3_CLK__SD3_CLK 0x1b - MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b - MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b - MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b - MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b - MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b - MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b - MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b - MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b - MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1b - >; - }; - - pinctrl_sai1: sai1-grp { - fsl,pins = < - MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK 0x1f - MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x1f - MX7D_PAD_ENET1_COL__SAI1_TX_DATA0 0x30 - MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0 0x1f - >; - }; - - pinctrl_sai1_mclk: sai1grp_mclk { - fsl,pins = < - MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x1f - >; - }; -}; - -&iomuxc_lpsr { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_lpsr>; - - pinctrl_gpio_lpsr: gpio1-grp { - fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO02__GPIO1_IO2 0x59 - MX7D_PAD_LPSR_GPIO1_IO03__GPIO1_IO3 0x59 - >; - }; - - pinctrl_gpiokeys: gpiokeysgrp { - fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x19 - >; - }; - - pinctrl_i2c1: i2c1-grp { - fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO05__I2C1_SDA 0x4000007f - MX7D_PAD_LPSR_GPIO1_IO04__I2C1_SCL 0x4000007f - >; - }; - - pinctrl_i2c1_recovery: i2c1-recoverygrp { - fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4 0x4000007f - MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x4000007f - >; - }; - - pinctrl_cd_usdhc1: usdhc1-cd-grp { - fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x59 /* CD */ - >; - }; - - pinctrl_uart1_ctrl2: uart1-ctrl2-grp { - fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x14 /* DSR */ - MX7D_PAD_LPSR_GPIO1_IO06__GPIO1_IO6 0x14 /* RI */ - >; - }; -}; diff --git a/sys/gnu/dts/arm/imx7-mba7.dtsi b/sys/gnu/dts/arm/imx7-mba7.dtsi deleted file mode 100644 index 50abf18ad30..00000000000 --- a/sys/gnu/dts/arm/imx7-mba7.dtsi +++ /dev/null @@ -1,550 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR X11 -/* - * Device Tree Include file for TQ Systems MBa7 carrier board. - * - * Copyright (C) 2016 TQ Systems GmbH - * Author: Markus Niebel - * Copyright (C) 2019 Bruno Thomsen - * - * Note: This file does not include nodes for all peripheral devices. - * As device driver coverage increases additional nodes can be added. - */ - -#include -#include - -/ { - beeper { - compatible = "gpio-beeper"; - gpios = <&pca9555 0 GPIO_ACTIVE_HIGH>; - }; - - chosen { - stdout-path = &uart6; - }; - - gpio_buttons: gpio-keys { - compatible = "gpio-keys"; - - button-0 { - /* #SWITCH_A */ - label = "S11"; - linux,code = ; - gpios = <&pca9555 13 GPIO_ACTIVE_LOW>; - }; - - button-1 { - /* #SWITCH_B */ - label = "S12"; - linux,code = ; - gpios = <&pca9555 14 GPIO_ACTIVE_LOW>; - }; - - button-2 { - /* #SWITCH_C */ - label = "S13"; - linux,code = ; - gpios = <&pca9555 15 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - led1 { - label = "led1"; - gpios = <&pca9555 8 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - }; - - led2 { - label = "led2"; - gpios = <&pca9555 9 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - reg_sd1_vmmc: regulator-sd1-vmmc { - compatible = "regulator-fixed"; - regulator-name = "VCC3V3_SD1"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_fec1_pwdn: regulator-fec1-pwdn { - compatible = "regulator-fixed"; - regulator-name = "PWDN_FEC1"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_fec2_pwdn: regulator-fec2-pwdn { - compatible = "regulator-fixed"; - regulator-name = "PWDN_FEC2"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usb_otg1_vbus: regulator-usb-otg1-vbus { - compatible = "regulator-fixed"; - regulator-name = "VBUS_USBOTG1"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usb_otg2_vbus: regulator-usb-otg2-vbus { - compatible = "regulator-fixed"; - regulator-name = "VBUS_USBOTG2"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_mpcie_1v5: regulator-mpcie-1v5 { - compatible = "regulator-fixed"; - regulator-name = "VCC1V5_MPCIE"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - gpio = <&pca9555 12 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - }; - - reg_mpcie_3v3: regulator-mpcie-3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC3V3_MPCIE"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&pca9555 10 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - }; - - reg_mba_12v0: regulator-mba-12v0 { - compatible = "regulator-fixed"; - regulator-name = "VCC12V0_MBA7"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - gpio = <&pca9555 11 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_lvds_transmitter: regulator-lvds-transmitter { - compatible = "regulator-fixed"; - regulator-name = "#SHTDN_LVDS"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&pca9555 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_vref_1v8: regulator-vref-1v8 { - compatible = "regulator-fixed"; - regulator-name = "VCC1V8_REF"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - vin-supply = <&sw2_reg>; - }; - - reg_audio_3v3: regulator-audio-3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC3V3_AUDIO"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; -}; - -&adc1 { - vref-supply = <®_vref_1v8>; - status = "okay"; -}; - -&adc2 { - vref-supply = <®_vref_1v8>; - status = "okay"; -}; - -&ecspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - num-chipselects = <3>; - cs-gpios = <&gpio4 0 GPIO_ACTIVE_LOW>, <&gpio4 1 GPIO_ACTIVE_LOW>, - <&gpio4 2 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&ecspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi2>; - num-chipselects = <1>; - status = "okay"; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet1>; - phy-mode = "rgmii-id"; - phy-reset-gpios = <&gpio7 15 GPIO_ACTIVE_LOW>; - phy-reset-duration = <1>; - phy-reset-delay = <1>; - phy-supply = <®_fec1_pwdn>; - phy-handle = <ðphy1_0>; - fsl,magic-packet; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy1_0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - ti,rx-internal-delay = ; - ti,tx-internal-delay = ; - ti,fifo-depth = ; - /* LED1: Link/Activity, LED2: Error */ - ti,led-function = <0x0db0>; - /* Active low, LED1 and LED2 driven by phy */ - ti,led-ctrl = <0x1001>; - }; - }; -}; - -&flexcan1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - status = "okay"; -}; - -&flexcan2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - status = "okay"; -}; - -&i2c1 { - lm75: temperature-sensor@49 { - compatible = "national,lm75"; - reg = <0x49>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - tlv320aic32x4: audio-codec@18 { - compatible = "ti,tlv320aic32x4"; - reg = <0x18>; - clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; - clock-names = "mclk"; - ldoin-supply = <®_audio_3v3>; - iov-supply = <®_audio_3v3>; - }; - - pca9555: gpio-expander@20 { - compatible = "nxp,pca9555"; - reg = <0x20>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pca9555>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&gpio7>; - interrupts = <12 IRQ_TYPE_EDGE_FALLING>; - interrupt-controller; - #interrupt-cells = <2>; - }; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog_mba7_1>; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO 0x7c - MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x74 - MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x74 - MX7D_PAD_UART1_RX_DATA__GPIO4_IO0 0x74 - MX7D_PAD_UART1_TX_DATA__GPIO4_IO1 0x74 - MX7D_PAD_UART2_RX_DATA__GPIO4_IO2 0x74 - >; - }; - - pinctrl_ecspi2: ecspi2grp { - fsl,pins = < - MX7D_PAD_ECSPI2_MISO__ECSPI2_MISO 0x7c - MX7D_PAD_ECSPI2_MOSI__ECSPI2_MOSI 0x74 - MX7D_PAD_ECSPI2_SCLK__ECSPI2_SCLK 0x74 - MX7D_PAD_ECSPI2_SS0__ECSPI2_SS0 0x74 - >; - }; - - pinctrl_enet1: enet1grp { - fsl,pins = < - MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x02 - MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x00 - MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x71 - MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x71 - MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x71 - MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x71 - MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x71 - MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x71 - MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x79 - MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x79 - MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x79 - MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x79 - MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x79 - MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x79 - /* Reset: SION, 100kPU, SRE_FAST, DSE_X1 */ - MX7D_PAD_ENET1_COL__GPIO7_IO15 0x40000070 - /* INT/PWDN: SION, 100kPU, HYS, SRE_FAST, DSE_X1 */ - MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x40000078 - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX7D_PAD_GPIO1_IO12__FLEXCAN1_RX 0x5a - MX7D_PAD_GPIO1_IO13__FLEXCAN1_TX 0x52 - >; - }; - - pinctrl_flexcan2: flexcan2grp { - fsl,pins = < - MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x5a - MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x52 - >; - }; - - pinctrl_hog_mba7_1: hogmba71grp { - fsl,pins = < - /* Limitation: WDOG2_B / WDOG2_RESET not usable */ - MX7D_PAD_ENET1_RX_CLK__GPIO7_IO13 0x4000007c - MX7D_PAD_ENET1_CRS__GPIO7_IO14 0x40000074 - /* #BOOT_EN */ - MX7D_PAD_UART2_TX_DATA__GPIO4_IO3 0x40000010 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX7D_PAD_I2C2_SCL__I2C2_SCL 0x40000078 - MX7D_PAD_I2C2_SDA__I2C2_SDA 0x40000078 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX7D_PAD_I2C3_SCL__I2C3_SCL 0x40000078 - MX7D_PAD_I2C3_SDA__I2C3_SDA 0x40000078 - >; - }; - - - pinctrl_pca9555: pca95550grp { - fsl,pins = < - MX7D_PAD_ENET1_TX_CLK__GPIO7_IO12 0x78 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x7e - MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x76 - MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS 0x76 - MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS 0x7e - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX7D_PAD_SAI2_TX_SYNC__UART4_DCE_RX 0x7e - MX7D_PAD_SAI2_TX_BCLK__UART4_DCE_TX 0x76 - MX7D_PAD_SAI2_RX_DATA__UART4_DCE_CTS 0x76 - MX7D_PAD_SAI2_TX_DATA__UART4_DCE_RTS 0x7e - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX7D_PAD_I2C4_SCL__UART5_DCE_RX 0x7e - MX7D_PAD_I2C4_SDA__UART5_DCE_TX 0x76 - >; - }; - - pinctrl_uart6: uart6grp { - fsl,pins = < - MX7D_PAD_EPDC_DATA08__UART6_DCE_RX 0x7d - MX7D_PAD_EPDC_DATA09__UART6_DCE_TX 0x75 - MX7D_PAD_EPDC_DATA11__UART6_DCE_CTS 0x75 - MX7D_PAD_EPDC_DATA10__UART6_DCE_RTS 0x7d - >; - }; - - pinctrl_uart7: uart7grp { - fsl,pins = < - MX7D_PAD_EPDC_DATA12__UART7_DCE_RX 0x7e - MX7D_PAD_EPDC_DATA13__UART7_DCE_TX 0x76 - MX7D_PAD_EPDC_DATA15__UART7_DCE_CTS 0x76 - /* Limitation: RTS is not connected */ - MX7D_PAD_EPDC_DATA14__UART7_DCE_RTS 0x7e - >; - }; - - pinctrl_usdhc1_gpio: usdhc1grp_gpio { - fsl,pins = < - /* WP */ - MX7D_PAD_SD1_WP__GPIO5_IO1 0x7c - /* CD */ - MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x7c - /* VSELECT */ - MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x59 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX7D_PAD_SD1_CMD__SD1_CMD 0x5e - MX7D_PAD_SD1_CLK__SD1_CLK 0x57 - MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5e - MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5e - MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5e - MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5e - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1grp_100mhz { - fsl,pins = < - MX7D_PAD_SD1_CMD__SD1_CMD 0x5a - MX7D_PAD_SD1_CLK__SD1_CLK 0x57 - MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a - MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a - MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a - MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1grp_200mhz { - fsl,pins = < - MX7D_PAD_SD1_CMD__SD1_CMD 0x5b - MX7D_PAD_SD1_CLK__SD1_CLK 0x57 - MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b - MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b - MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b - MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b - >; - }; -}; - -&iomuxc_lpsr { - pinctrl_pwm1: pwm1grp { - fsl,pins = < - /* LCD_CONTRAST */ - MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x50 - >; - }; - - pinctrl_usbotg1: usbotg1grp { - fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO04__USB_OTG1_OC 0x5c - MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x59 - >; - }; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>; - assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - assigned-clocks = <&clks IMX7D_UART4_ROOT_SRC>; - assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - assigned-clocks = <&clks IMX7D_UART5_ROOT_SRC>; - assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; - status = "okay"; -}; - -&uart6 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart6>; - assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>; - assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; - status = "okay"; -}; - -&uart7 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart7>; - assigned-clocks = <&clks IMX7D_UART7_ROOT_SRC>; - assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; - uart-has-rtscts; - status = "okay"; -}; - -&usbh { - status = "okay"; -}; - -&usbotg1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg1>; - vbus-supply = <®_usb_otg1_vbus>; - srp-disable; - hnp-disable; - adp-disable; - dr_mode = "host"; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>; - cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; - vmmc-supply = <®_sd1_vmmc>; - bus-width = <4>; - no-1-8-v; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx7-tqma7.dtsi b/sys/gnu/dts/arm/imx7-tqma7.dtsi deleted file mode 100644 index 9aaed85138c..00000000000 --- a/sys/gnu/dts/arm/imx7-tqma7.dtsi +++ /dev/null @@ -1,249 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR X11 -/* - * Device Tree Include file for TQ Systems TQMa7x boards with full mounted PCB. - * - * Copyright (C) 2016 TQ Systems GmbH - * Author: Markus Niebel - * Copyright (C) 2019 Bruno Thomsen - */ - -/ { - memory@80000000 { - device_type = "memory"; - /* 512 MB - default configuration */ - reg = <0x80000000 0x20000000>; - }; -}; - -&cpu0 { - arm-supply = <&sw1a_reg>; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - clock-frequency = <100000>; - status = "okay"; - - pfuze3000: pmic@8 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic1>; - compatible = "fsl,pfuze3000"; - reg = <0x08>; - - regulators { - sw1a_reg: sw1a { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - /* use sw1c_reg to align with pfuze100/pfuze200 */ - sw1c_reg: sw1b { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1475000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1850000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3a_reg: sw3 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1650000>; - regulator-boot-on; - regulator-always-on; - }; - - swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - }; - - snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - vgen1_reg: vldo1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen2_reg: vldo2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - regulator-always-on; - }; - - vgen3_reg: vccsd { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen4_reg: v33 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen5_reg: vldo3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen6_reg: vldo4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; - - /* NXP SE97BTP with temperature sensor + eeprom */ - se97b: temperature-sensor-eeprom@1e { - compatible = "nxp,se97b", "jedec,jc-42.4-temp"; - reg = <0x1e>; - status = "okay"; - }; - - /* ST M24C64 */ - m24c64: eeprom@50 { - compatible = "atmel,24c64"; - reg = <0x50>; - pagesize = <32>; - status = "okay"; - }; - - at24c02: eeprom@56 { - compatible = "atmel,24c02"; - reg = <0x56>; - pagesize = <16>; - status = "okay"; - }; - - ds1339: rtc@68 { - compatible = "dallas,ds1339"; - reg = <0x68>; - }; -}; - -&iomuxc { - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX7D_PAD_I2C1_SDA__I2C1_SDA 0x40000078 - MX7D_PAD_I2C1_SCL__I2C1_SCL 0x40000078 - >; - }; - - pinctrl_pmic1: pmic1grp { - fsl,pins = < - MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x4000005C - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX7D_PAD_SD3_CMD__SD3_CMD 0x59 - MX7D_PAD_SD3_CLK__SD3_CLK 0x56 - MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 - MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 - MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 - MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 - MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 - MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 - MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 - MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 - MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { - fsl,pins = < - MX7D_PAD_SD3_CMD__SD3_CMD 0x5a - MX7D_PAD_SD3_CLK__SD3_CLK 0x51 - MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a - MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a - MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a - MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a - MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a - MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a - MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a - MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a - MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3grp_200mhz { - fsl,pins = < - MX7D_PAD_SD3_CMD__SD3_CMD 0x5b - MX7D_PAD_SD3_CLK__SD3_CLK 0x51 - MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b - MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b - MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b - MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b - MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b - MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b - MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b - MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b - MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1b - >; - }; -}; - -&iomuxc_lpsr { - pinctrl_wdog1: wdog1grp { - fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x30 - >; - }; -}; - -&sdma { - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>; - assigned-clock-rates = <400000000>; - bus-width = <8>; - non-removable; - vmmc-supply = <&vgen4_reg>; - vqmmc-supply = <&sw2_reg>; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog1>; - /* - * Errata e10574: - * WDOG reset needs to run with WDOG_RESET_B signal enabled. - * X1-51 (WDOG1#) signal needs carrier board handling to reset - * TQMa7 on X1-22 (RESET_IN#). - */ - fsl,ext-reset-output; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx7d-cl-som-imx7.dts b/sys/gnu/dts/arm/imx7d-cl-som-imx7.dts deleted file mode 100644 index 7646284e13a..00000000000 --- a/sys/gnu/dts/arm/imx7d-cl-som-imx7.dts +++ /dev/null @@ -1,290 +0,0 @@ -/* - * Support for CompuLab CL-SOM-iMX7 System-on-Module - * - * Copyright (C) 2015 CompuLab Ltd. - http://www.compulab.co.il/ - * Author: Ilya Ledvich - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - */ - -/dts-v1/; - -#include "imx7d.dtsi" - -/ { - model = "CompuLab CL-SOM-iMX7"; - compatible = "compulab,cl-som-imx7", "fsl,imx7d"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x10000000>; /* 256 MB - minimal configuration */ - }; - - reg_usb_otg1_vbus: regulator-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&cpu0 { - cpu-supply = <&sw1a_reg>; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet1>; - assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>, - <&clks IMX7D_ENET1_TIME_ROOT_CLK>; - assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; - assigned-clock-rates = <0>, <100000000>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy0>; - fsl,magic-packet; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - }; - - ethphy1: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; - }; -}; - -&fec2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet2>; - assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>, - <&clks IMX7D_ENET2_TIME_ROOT_CLK>; - assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; - assigned-clock-rates = <0>, <100000000>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy1>; - fsl,magic-packet; - status = "okay"; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - pmic: pmic@8 { - compatible = "fsl,pfuze3000"; - reg = <0x08>; - - regulators { - sw1a_reg: sw1a { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1475000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - /* use sw1c_reg to align with pfuze100/pfuze200 */ - sw1c_reg: sw1b { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1475000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1850000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3a_reg: sw3 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1650000>; - regulator-boot-on; - regulator-always-on; - }; - - swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - }; - - snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - vgen1_reg: vldo1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen2_reg: vldo2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen3_reg: vccsd { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen4_reg: v33 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen5_reg: vldo3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen6_reg: vldo4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; - - pca9555: pca9555@20 { - compatible = "nxp,pca9555"; - gpio-controller; - #gpio-cells = <2>; - reg = <0x20>; - }; - - eeprom@50 { - compatible = "atmel,24c08"; - reg = <0x50>; - pagesize = <16>; - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>; - assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; - status = "okay"; -}; - -&usbotg1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg1>; - vbus-supply = <®_usb_otg1_vbus>; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>; - assigned-clock-rates = <400000000>; - bus-width = <8>; - fsl,tuning-step = <2>; - non-removable; - status = "okay"; -}; - -&iomuxc { - pinctrl_enet1: enet1grp { - fsl,pins = < - MX7D_PAD_SD2_CD_B__ENET1_MDIO 0x30 - MX7D_PAD_SD2_WP__ENET1_MDC 0x30 - MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x11 - MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x11 - MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x11 - MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x11 - MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x11 - MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x11 - MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x11 - MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x11 - MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x11 - MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x11 - MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x11 - MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x11 - >; - }; - - pinctrl_enet2: enet2grp { - fsl,pins = < - MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x11 - MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x11 - MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x11 - MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x11 - MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x11 - MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x11 - MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x11 - MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x11 - MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x11 - MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x11 - MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x11 - MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x11 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f - MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79 - MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX7D_PAD_SD3_CMD__SD3_CMD 0x59 - MX7D_PAD_SD3_CLK__SD3_CLK 0x19 - MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 - MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 - MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 - MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 - MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 - MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 - MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 - MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 - MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19 - >; - }; -}; - -&iomuxc_lpsr { - pinctrl_usbotg1: usbotg1grp { - fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x14 /* OTG PWREN */ - >; - }; -}; diff --git a/sys/gnu/dts/arm/imx7d-colibri-emmc-eval-v3.dts b/sys/gnu/dts/arm/imx7d-colibri-emmc-eval-v3.dts deleted file mode 100644 index 8ee73c870b1..00000000000 --- a/sys/gnu/dts/arm/imx7d-colibri-emmc-eval-v3.dts +++ /dev/null @@ -1,19 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright 2017 Toradex AG - */ - -/dts-v1/; -#include "imx7d-colibri-emmc.dtsi" -#include "imx7-colibri-eval-v3.dtsi" - -/ { - model = "Toradex Colibri iMX7D 1GB (eMMC) on Colibri Evaluation Board V3"; - compatible = "toradex,colibri-imx7d-emmc-eval-v3", - "toradex,colibri-imx7d-emmc", "fsl,imx7d"; -}; - -&usbotg2 { - vbus-supply = <®_usbh_vbus>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx7d-colibri-emmc.dtsi b/sys/gnu/dts/arm/imx7d-colibri-emmc.dtsi deleted file mode 100644 index 898f4b8d742..00000000000 --- a/sys/gnu/dts/arm/imx7d-colibri-emmc.dtsi +++ /dev/null @@ -1,22 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright 2017 Toradex AG - */ - -#include "imx7d.dtsi" -#include "imx7-colibri.dtsi" - -/ { - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x40000000>; - }; -}; - -&usbotg2 { - dr_mode = "host"; -}; - -&usdhc3 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx7d-colibri-eval-v3.dts b/sys/gnu/dts/arm/imx7d-colibri-eval-v3.dts deleted file mode 100644 index 136e11ab489..00000000000 --- a/sys/gnu/dts/arm/imx7d-colibri-eval-v3.dts +++ /dev/null @@ -1,56 +0,0 @@ -/* - * Copyright 2016 Toradex AG - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx7d-colibri.dtsi" -#include "imx7-colibri-eval-v3.dtsi" - -/ { - model = "Toradex Colibri iMX7D on Colibri Evaluation Board V3"; - compatible = "toradex,colibri-imx7d-eval-v3", "toradex,colibri-imx7d", - "fsl,imx7d"; -}; - -&usbotg2 { - vbus-supply = <®_usbh_vbus>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx7d-colibri.dtsi b/sys/gnu/dts/arm/imx7d-colibri.dtsi deleted file mode 100644 index e2e327f437e..00000000000 --- a/sys/gnu/dts/arm/imx7d-colibri.dtsi +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Copyright 2016 Toradex AG - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "imx7d.dtsi" -#include "imx7-colibri.dtsi" - -/ { - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000>; - }; -}; - -&gpmi { - status = "okay"; -}; - -&usbotg2 { - dr_mode = "host"; -}; diff --git a/sys/gnu/dts/arm/imx7d-mba7.dts b/sys/gnu/dts/arm/imx7d-mba7.dts deleted file mode 100644 index 221274c73db..00000000000 --- a/sys/gnu/dts/arm/imx7d-mba7.dts +++ /dev/null @@ -1,119 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR X11 -/* - * Device Tree Source for TQ Systems TQMa7D board on MBa7 carrier board. - * - * Copyright (C) 2016 TQ Systems GmbH - * Author: Markus Niebel - * Copyright (C) 2019 Bruno Thomsen - */ - -/dts-v1/; - -#include "imx7d-tqma7.dtsi" -#include "imx7-mba7.dtsi" - -/ { - model = "TQ Systems TQMa7D board on MBa7 carrier board"; - compatible = "tq,imx7d-mba7", "fsl,imx7d"; -}; - -&fec2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet2>; - phy-mode = "rgmii-id"; - phy-reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; - phy-reset-duration = <1>; - phy-reset-delay = <1>; - phy-supply = <®_fec2_pwdn>; - phy-handle = <ðphy2_0>; - fsl,magic-packet; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy2_0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - ti,rx-internal-delay = ; - ti,tx-internal-delay = ; - ti,fifo-depth = ; - /* LED1: Link/Activity, LED2: error */ - ti,led-function = <0x0db0>; - /* active low, LED1/2 driven by phy */ - ti,led-ctrl = <0x1001>; - }; - }; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog_mba7_1>; - - pinctrl_enet2: enet2grp { - fsl,pins = < - MX7D_PAD_SD2_CD_B__ENET2_MDIO 0x02 - MX7D_PAD_SD2_WP__ENET2_MDC 0x00 - MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x71 - MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x71 - MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x71 - MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x71 - MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x71 - MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x71 - MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x79 - MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x79 - MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x79 - MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x79 - MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x79 - MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x79 - /* Reset: SION, 100kPU, SRE_FAST, DSE_X1 */ - MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x40000070 - /* INT/PWDN: SION, 100kPU, HYS, SRE_FAST, DSE_X1 */ - MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 0x40000078 - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = < - /* #pcie_wake */ - MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x70 - /* #pcie_rst */ - MX7D_PAD_SD2_CLK__GPIO5_IO12 0x70 - /* #pcie_dis */ - MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x70 - >; - }; -}; - -&iomuxc_lpsr { - pinctrl_usbotg2: usbotg2grp { - fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO06__USB_OTG2_OC 0x5c - MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x59 - >; - }; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - /* 1.5V logically from 3.3V */ - /* probe deferral not supported */ - /* pcie-bus-supply = <®_mpcie_1v5>; */ - reset-gpio = <&gpio5 12 GPIO_ACTIVE_LOW>; - disable-gpio = <&gpio2 29 GPIO_ACTIVE_LOW>; - power-on-gpio = <&gpio2 30 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&usbotg2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg2>; - vbus-supply = <®_usb_otg2_vbus>; - srp-disable; - hnp-disable; - adp-disable; - dr_mode = "host"; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx7d-meerkat96.dts b/sys/gnu/dts/arm/imx7d-meerkat96.dts deleted file mode 100644 index 5339210b63d..00000000000 --- a/sys/gnu/dts/arm/imx7d-meerkat96.dts +++ /dev/null @@ -1,375 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -/* - * Copyright (C) 2019 Linaro Ltd. - */ - -/dts-v1/; - -#include "imx7d.dtsi" - -/ { - model = "96Boards Meerkat96 Board"; - compatible = "novtech,imx7d-meerkat96", "fsl,imx7d"; - - chosen { - stdout-path = &uart6; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000>; /* 512MB */ - }; - - reg_wlreg_on: regulator-wlreg-on { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wlreg_on>; - regulator-name = "wlreg_on"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <100>; - gpio = <&gpio6 15 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_usb_otg1_vbus: regulator-usb-otg1-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_usb_otg2_vbus: regulator-usb-otg2-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg2_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led1 { - label = "green:user1"; - gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - - led2 { - label = "green:user2"; - gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; - linux,default-trigger = "mmc0"; - default-state = "off"; - }; - - led3 { - label = "green:user3"; - gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; - linux,default-trigger = "mmc1"; - default-state = "off"; - }; - - led4 { - label = "green:user4"; - gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; - linux,default-trigger = "none"; - default-state = "off"; - panic-indicator; - }; - - led5 { - label = "yellow:wlan"; - gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "phy0tx"; - default-state = "off"; - }; - - led6 { - label = "blue:bt"; - gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "bluetooth-power"; - default-state = "off"; - }; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; -}; - -&i2c4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4>; - status = "okay"; -}; - -&lcdif { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcdif>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>; - assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>; - assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; - uart-has-rtscts; - status = "okay"; -}; - -&uart6 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart6>; - assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>; - assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; - status = "okay"; -}; - -&uart7 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart7 &pinctrl_bt_gpios>; - assigned-clocks = <&clks IMX7D_UART7_ROOT_SRC>; - assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; - uart-has-rtscts; - fsl,dte-mode; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - device-wakeup-gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>; - host-wakeup-gpios = <&gpio4 17 GPIO_ACTIVE_HIGH>; - }; -}; - -&usbotg1 { - vbus-supply = <®_usb_otg1_vbus>; - status = "okay"; -}; - -&usbotg2 { - vbus-supply = <®_usb_otg2_vbus>; - dr_mode = "host"; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - keep-power-in-suspend; - tuning-step = <2>; - vmmc-supply = <®_3p3v>; - no-1-8-v; - broken-cd; - status = "okay"; -}; - -&usdhc3 { - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - bus-width = <4>; - no-1-8-v; - no-mmc; - non-removable; - keep-power-in-suspend; - wakeup-source; - vmmc-supply = <®_wlreg_on>; - vqmmc-supply =<®_3p3v>; - status = "okay"; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wlan_irq>; - interrupt-parent = <&gpio6>; - interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "host-wake"; - }; -}; - -&iomuxc { - pinctrl_bt_gpios: btgpiosgrp { - fsl,pins = < - MX7D_PAD_SAI1_TX_BCLK__GPIO6_IO13 0x59 - MX7D_PAD_ECSPI1_MOSI__GPIO4_IO17 0x1f - >; - }; - - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x59 - MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4 0x59 - MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x59 - MX7D_PAD_LPSR_GPIO1_IO06__GPIO1_IO6 0x59 - MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x59 - MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f - MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f - MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX7D_PAD_ENET1_RGMII_RD1__I2C3_SDA 0x4000007f - MX7D_PAD_ENET1_RGMII_RD0__I2C3_SCL 0x4000007f - >; - }; - - pinctrl_i2c4: i2c4grp { - fsl,pins = < - MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA 0x4000007f - MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL 0x4000007f - >; - }; - - pinctrl_lcdif: lcdifgrp { - fsl,pins = < - MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79 - MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79 - MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79 - MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79 - MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79 - MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79 - MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79 - MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79 - MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79 - MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79 - MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79 - MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79 - MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79 - MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79 - MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79 - MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79 - MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79 - MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79 - MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79 - MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79 - MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79 - MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79 - MX7D_PAD_LCD_DATA22__LCD_DATA22 0x79 - MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79 - MX7D_PAD_LCD_CLK__LCD_CLK 0x79 - MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x79 - MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x79 - MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x79 - MX7D_PAD_LCD_RESET__LCD_RESET 0x79 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79 - MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX7D_PAD_SD3_DATA4__UART3_DCE_RX 0x79 - MX7D_PAD_SD3_DATA5__UART3_DCE_TX 0x79 - MX7D_PAD_SD3_DATA6__UART3_DCE_RTS 0x79 - MX7D_PAD_SD3_DATA7__UART3_DCE_CTS 0x79 - >; - }; - - pinctrl_uart6: uart6grp { - fsl,pins = < - MX7D_PAD_SD1_CD_B__UART6_DCE_RX 0x79 - MX7D_PAD_SD1_WP__UART6_DCE_TX 0x79 - >; - }; - - pinctrl_uart7: uart7grp { - fsl,pins = < - MX7D_PAD_ECSPI2_SCLK__UART7_DTE_TX 0x79 - MX7D_PAD_ECSPI2_MOSI__UART7_DTE_RX 0x79 - MX7D_PAD_ECSPI2_MISO__UART7_DTE_CTS 0x79 - MX7D_PAD_ECSPI2_SS0__UART7_DTE_RTS 0x79 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX7D_PAD_SD1_CMD__SD1_CMD 0x59 - MX7D_PAD_SD1_CLK__SD1_CLK 0x19 - MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 - MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 - MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 - MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX7D_PAD_SD3_CMD__SD3_CMD 0x59 - MX7D_PAD_SD3_CLK__SD3_CLK 0x0D - MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 - MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 - MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 - MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 - >; - }; - - pinctrl_wlan_irq: wlanirqgrp { - fsl,pins = < - MX7D_PAD_SAI1_TX_SYNC__GPIO6_IO14 0x19 - >; - }; - - pinctrl_wlreg_on: wlregongrp { - fsl,pins = < - MX7D_PAD_SAI1_TX_DATA__GPIO6_IO15 0x19 - >; - }; -}; diff --git a/sys/gnu/dts/arm/imx7d-nitrogen7.dts b/sys/gnu/dts/arm/imx7d-nitrogen7.dts deleted file mode 100644 index 6b4acea1ef7..00000000000 --- a/sys/gnu/dts/arm/imx7d-nitrogen7.dts +++ /dev/null @@ -1,695 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR X11 -/* - * Copyright 2016 Boundary Devices, Inc. - */ - -/dts-v1/; - -#include "imx7d.dtsi" - -/ { - model = "Boundary Devices i.MX7 Nitrogen7 Board"; - compatible = "boundary,imx7d-nitrogen7", "fsl,imx7d"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x40000000>; - }; - - backlight-j9 { - compatible = "gpio-backlight"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_backlight_j9>; - gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; - default-on; - }; - - backlight_lcd: backlight-j20 { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 5000000 0>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - status = "okay"; - }; - - panel-lcd { - compatible = "okaya,rs800480t-7x0gp"; - backlight = <&backlight_lcd>; - - port { - panel_in: endpoint { - remote-endpoint = <&lcdif_out>; - }; - }; - }; - - reg_usb_otg1_vbus: regulator-usb-otg1-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usb_otg2_vbus: regulator-usb-otg2-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg2_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_can2_3v3: regulator-can2-3v3 { - compatible = "regulator-fixed"; - regulator-name = "can2-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 14 GPIO_ACTIVE_LOW>; - }; - - reg_vref_1v8: regulator-vref-1v8 { - compatible = "regulator-fixed"; - regulator-name = "vref-1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - reg_vref_3v3: regulator-vref-3v3 { - compatible = "regulator-fixed"; - regulator-name = "vref-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_wlan: regulator-wlan { - compatible = "regulator-fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "reg_wlan"; - startup-delay-us = <70000>; - gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - usdhc2_pwrseq: usdhc2_pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&clks IMX7D_CLKO2_ROOT_DIV>; - clock-names = "ext_clock"; - }; -}; - -&adc1 { - vref-supply = <®_vref_1v8>; - status = "okay"; -}; - -&adc2 { - vref-supply = <®_vref_1v8>; - status = "okay"; -}; - -&clks { - assigned-clocks = <&clks IMX7D_CLKO2_ROOT_SRC>, - <&clks IMX7D_CLKO2_ROOT_DIV>; - assigned-clock-parents = <&clks IMX7D_CKIL>; - assigned-clock-rates = <0>, <32768>; -}; - -&cpu0 { - cpu-supply = <&sw1a_reg>; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet1>; - assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>, - <&clks IMX7D_ENET1_TIME_ROOT_CLK>; - assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; - assigned-clock-rates = <0>, <100000000>; - phy-mode = "rgmii"; - phy-handle = <ðphy0>; - fsl,magic-packet; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@4 { - reg = <4>; - }; - }; -}; - -&flexcan2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - xceiver-supply = <®_can2_3v3>; - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pmic: pfuze3000@8 { - compatible = "fsl,pfuze3000"; - reg = <0x08>; - - regulators { - sw1a_reg: sw1a { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1475000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - /* use sw1c_reg to align with pfuze100/pfuze200 */ - sw1c_reg: sw1b { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1475000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1850000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3a_reg: sw3 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1650000>; - regulator-boot-on; - regulator-always-on; - }; - - swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - }; - - snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - vgen1_reg: vldo1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen2_reg: vldo2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - regulator-always-on; - }; - - vgen3_reg: vccsd { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen4_reg: v33 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen5_reg: vldo3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen6_reg: vldo4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - rtc@68 { - compatible = "microcrystal,rv4162"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2_rv4162>; - reg = <0x68>; - interrupts-extended = <&gpio2 15 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - touch@48 { - compatible = "ti,tsc2004"; - reg = <0x48>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3_tsc2004>; - interrupts-extended = <&gpio3 4 IRQ_TYPE_EDGE_FALLING>; - wakeup-gpios = <&gpio3 4 GPIO_ACTIVE_LOW>; - }; -}; - -&i2c4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4>; - status = "okay"; - - codec: wm8960@1a { - compatible = "wlf,wm8960"; - reg = <0x1a>; - clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; - clock-names = "mclk"; - wlf,shared-lrclk; - }; -}; - -&lcdif { - status = "okay"; - - port { - lcdif_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "okay"; -}; - -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm2>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>; - assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - assigned-clocks = <&clks IMX7D_UART2_ROOT_SRC>; - assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>; - assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; - status = "okay"; -}; - -&uart6 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart6>; - assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>; - assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; - uart-has-rtscts; - status = "okay"; -}; - -&usbotg1 { - vbus-supply = <®_usb_otg1_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg1>; - status = "okay"; -}; - -&usbotg2 { - vbus-supply = <®_usb_otg2_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg2>; - dr_mode = "host"; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; - vmmc-supply = <&vgen3_reg>; - bus-width = <4>; - fsl,tuning-step = <2>; - wakeup-source; - keep-power-in-suspend; - status = "okay"; -}; - -&usdhc2 { - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - bus-width = <4>; - non-removable; - vmmc-supply = <®_wlan>; - mmc-pwrseq = <&usdhc2_pwrseq>; - cap-power-off-card; - keep-power-in-suspend; - status = "okay"; - - wlcore: wlcore@2 { - compatible = "ti,wl1271"; - reg = <2>; - interrupt-parent = <&gpio4>; - interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; - ref-clock-frequency = <38400000>; - }; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>; - assigned-clock-rates = <400000000>; - bus-width = <8>; - fsl,tuning-step = <2>; - non-removable; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog1>; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog_1 &pinctrl_j2>; - - pinctrl_hog_1: hoggrp-1 { - fsl,pins = < - MX7D_PAD_SD3_RESET_B__GPIO6_IO11 0x5d - MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x7d - MX7D_PAD_ECSPI2_MISO__GPIO4_IO22 0x7d - >; - }; - - pinctrl_enet1: enet1grp { - fsl,pins = < - MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x3 - MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x3 - MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 0x3 - MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x71 - MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x71 - MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x71 - MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x71 - MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x71 - MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x71 - MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x71 - MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x11 - MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x11 - MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x11 - MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x71 - MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x11 - MX7D_PAD_SD3_STROBE__GPIO6_IO10 0x75 - >; - }; - - pinctrl_flexcan2: flexcan2grp { - fsl,pins = < - MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x7d - MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x7d - MX7D_PAD_EPDC_DATA14__GPIO2_IO14 0x7d - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f - MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f - MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f - >; - }; - - pinctrl_i2c2_rv4162: i2c2-rv4162grp { - fsl,pins = < - MX7D_PAD_EPDC_DATA15__GPIO2_IO15 0x7d - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f - MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f - >; - }; - - pinctrl_i2c3_tsc2004: i2c3tsc2004grp { - fsl,pins = < - MX7D_PAD_LCD_RESET__GPIO3_IO4 0x79 - MX7D_PAD_SD2_WP__GPIO5_IO10 0x7d - >; - }; - - pinctrl_i2c4: i2c4grp { - fsl,pins = < - MX7D_PAD_I2C4_SDA__I2C4_SDA 0x4000007f - MX7D_PAD_I2C4_SCL__I2C4_SCL 0x4000007f - >; - }; - - pinctrl_j2: j2grp { - fsl,pins = < - MX7D_PAD_SAI1_TX_DATA__GPIO6_IO15 0x7d - MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x7d - MX7D_PAD_SAI1_RX_DATA__GPIO6_IO12 0x7d - MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x7d - MX7D_PAD_SD1_WP__GPIO5_IO1 0x7d - MX7D_PAD_EPDC_SDSHR__GPIO2_IO19 0x7d - MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x7d - MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x7d - MX7D_PAD_EPDC_DATA07__GPIO2_IO7 0x7d - MX7D_PAD_EPDC_DATA08__GPIO2_IO8 0x7d - MX7D_PAD_EPDC_DATA09__GPIO2_IO9 0x7d - MX7D_PAD_EPDC_DATA10__GPIO2_IO10 0x7d - MX7D_PAD_EPDC_DATA11__GPIO2_IO11 0x7d - MX7D_PAD_EPDC_DATA12__GPIO2_IO12 0x7d - MX7D_PAD_SAI1_TX_SYNC__GPIO6_IO14 0x7d - MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x7d - MX7D_PAD_SAI1_TX_BCLK__GPIO6_IO13 0x7d - MX7D_PAD_SD2_CD_B__GPIO5_IO9 0x7d - MX7D_PAD_EPDC_GDCLK__GPIO2_IO24 0x7d - MX7D_PAD_SAI2_RX_DATA__GPIO6_IO21 0x7d - MX7D_PAD_EPDC_GDOE__GPIO2_IO25 0x7d - MX7D_PAD_EPDC_GDRL__GPIO2_IO26 0x7d - MX7D_PAD_SAI2_TX_DATA__GPIO6_IO22 0x7d - MX7D_PAD_EPDC_SDCE0__GPIO2_IO20 0x7d - MX7D_PAD_SAI2_TX_BCLK__GPIO6_IO20 0x7d - MX7D_PAD_EPDC_SDCE1__GPIO2_IO21 0x7d - MX7D_PAD_SAI2_TX_SYNC__GPIO6_IO19 0x7d - MX7D_PAD_EPDC_SDCE2__GPIO2_IO22 0x7d - MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 0x7d - MX7D_PAD_EPDC_GDSP__GPIO2_IO27 0x7d - MX7D_PAD_EPDC_SDCLK__GPIO2_IO16 0x7d - MX7D_PAD_EPDC_SDLE__GPIO2_IO17 0x7d - MX7D_PAD_EPDC_SDOE__GPIO2_IO18 0x7d - MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x7d - MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 0x7d - >; - }; - - pinctrl_lcdif_dat: lcdifdatgrp { - fsl,pins = < - MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79 - MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79 - MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79 - MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79 - MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79 - MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79 - MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79 - MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79 - MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79 - MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79 - MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79 - MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79 - MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79 - MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79 - MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79 - MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79 - MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79 - MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79 - MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79 - MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79 - MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79 - MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79 - MX7D_PAD_LCD_DATA22__LCD_DATA22 0x79 - MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79 - >; - }; - - pinctrl_lcdif_ctrl: lcdifctrlgrp { - fsl,pins = < - MX7D_PAD_LCD_CLK__LCD_CLK 0x79 - MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x79 - MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x79 - MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x79 - >; - }; - - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX7D_PAD_GPIO1_IO09__PWM2_OUT 0x7d - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79 - MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX 0x79 - MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX 0x79 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x79 - MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x79 - MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x7d - >; - }; - - pinctrl_uart6: uart6grp { - fsl,pins = < - MX7D_PAD_ECSPI1_MOSI__UART6_DCE_TX 0x79 - MX7D_PAD_ECSPI1_SCLK__UART6_DCE_RX 0x79 - MX7D_PAD_ECSPI1_SS0__UART6_DCE_CTS 0x79 - MX7D_PAD_ECSPI1_MISO__UART6_DCE_RTS 0x79 - >; - }; - - pinctrl_usbotg2: usbotg2grp { - fsl,pins = < - MX7D_PAD_UART3_RTS_B__USB_OTG2_OC 0x7d - MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x14 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX7D_PAD_SD1_CMD__SD1_CMD 0x59 - MX7D_PAD_SD1_CLK__SD1_CLK 0x19 - MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 - MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 - MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 - MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 - MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x75 - MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x75 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX7D_PAD_SD2_CMD__SD2_CMD 0x59 - MX7D_PAD_SD2_CLK__SD2_CLK 0x19 - MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59 - MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59 - MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59 - MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59 - MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20 0x59 - MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x59 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX7D_PAD_SD3_CMD__SD3_CMD 0x59 - MX7D_PAD_SD3_CLK__SD3_CLK 0x19 - MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 - MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 - MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 - MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 - MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 - MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 - MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 - MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 - >; - }; -}; - -&iomuxc_lpsr { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog_2>; - - pinctrl_hog_2: hoggrp-2 { - fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO02__GPIO1_IO2 0x7d - MX7D_PAD_LPSR_GPIO1_IO03__CCM_CLKO2 0x7d - >; - }; - - pinctrl_backlight_j9: backlightj9grp { - fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x7d - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x7d - >; - }; - - pinctrl_usbotg1: usbotg1grp { - fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO04__USB_OTG1_OC 0x7d - MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x14 - >; - }; - - pinctrl_wdog1: wdog1grp { - fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x75 - >; - }; -}; diff --git a/sys/gnu/dts/arm/imx7d-pico-hobbit.dts b/sys/gnu/dts/arm/imx7d-pico-hobbit.dts deleted file mode 100644 index 7b2198a9372..00000000000 --- a/sys/gnu/dts/arm/imx7d-pico-hobbit.dts +++ /dev/null @@ -1,105 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// -// Copyright 2017 NXP - -#include "imx7d-pico.dtsi" - -/ { - model = "TechNexion PICO-IMX7D Board using Hobbit baseboard"; - compatible = "technexion,imx7d-pico-hobbit", "fsl,imx7d"; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led { - label = "gpio-led"; - gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>; - }; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "imx7-sgtl5000"; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&dailink_master>; - simple-audio-card,frame-master = <&dailink_master>; - simple-audio-card,cpu { - sound-dai = <&sai1>; - }; - - dailink_master: simple-audio-card,codec { - sound-dai = <&sgtl5000>; - clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; - }; - }; -}; - -&i2c1 { - sgtl5000: codec@a { - #sound-dai-cells = <0>; - reg = <0x0a>; - compatible = "fsl,sgtl5000"; - clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; - VDDA-supply = <®_2p5v>; - VDDIO-supply = <®_vref_1v8>; - }; -}; - -&i2c4 { - status = "okay"; - - adc081c: adc@50 { - compatible = "ti,adc081c"; - reg = <0x50>; - vref-supply = <®_3p3v>; - }; -}; - -&ecspi3 { - ads7846@0 { - reg = <0>; - compatible = "ti,ads7846"; - interrupt-parent = <&gpio2>; - interrupts = <7 0>; - spi-max-frequency = <1000000>; - pendown-gpio = <&gpio2 7 0>; - vcc-supply = <®_3p3v>; - ti,x-min = /bits/ 16 <0>; - ti,x-max = /bits/ 16 <4095>; - ti,y-min = /bits/ 16 <0>; - ti,y-max = /bits/ 16 <4095>; - ti,pressure-max = /bits/ 16 <1024>; - ti,x-plate-ohms = /bits/ 16 <90>; - ti,y-plate-ohms = /bits/ 16 <90>; - ti,debounce-max = /bits/ 16 <70>; - ti,debounce-tol = /bits/ 16 <3>; - ti,debounce-rep = /bits/ 16 <2>; - ti,settle-delay-usec = /bits/ 16 <150>; - wakeup-source; - }; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_hog: hoggrp { - fsl,pins = < - MX7D_PAD_EPDC_DATA00__GPIO2_IO0 0x14 - MX7D_PAD_EPDC_DATA01__GPIO2_IO1 0x14 - MX7D_PAD_EPDC_DATA02__GPIO2_IO2 0x14 - MX7D_PAD_EPDC_DATA03__GPIO2_IO3 0x14 - MX7D_PAD_EPDC_DATA05__GPIO2_IO5 0x14 - MX7D_PAD_EPDC_DATA12__GPIO2_IO12 0x14 - MX7D_PAD_EPDC_DATA07__GPIO2_IO7 0x14 - >; - }; - - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x14 - >; - }; -}; diff --git a/sys/gnu/dts/arm/imx7d-pico-pi.dts b/sys/gnu/dts/arm/imx7d-pico-pi.dts deleted file mode 100644 index 70bea95c06d..00000000000 --- a/sys/gnu/dts/arm/imx7d-pico-pi.dts +++ /dev/null @@ -1,93 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// -// Copyright 2017 NXP - -#include "imx7d-pico.dtsi" - -/ { - model = "TechNexion PICO-IMX7D Board and PI baseboard"; - compatible = "technexion,imx7d-pico-pi", "fsl,imx7d"; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led { - label = "gpio-led"; - gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>; - }; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "imx7-sgtl5000"; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&dailink_master>; - simple-audio-card,frame-master = <&dailink_master>; - simple-audio-card,cpu { - sound-dai = <&sai1>; - }; - - dailink_master: simple-audio-card,codec { - sound-dai = <&sgtl5000>; - clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; - }; - }; -}; - -&i2c1 { - sgtl5000: codec@a { - #sound-dai-cells = <0>; - reg = <0x0a>; - compatible = "fsl,sgtl5000"; - clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; - VDDA-supply = <®_2p5v>; - VDDIO-supply = <®_vref_1v8>; - }; -}; - -&i2c4 { - polytouch: touchscreen@38 { - compatible = "edt,edt-ft5x06"; - reg = <0x38>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_touchscreen>; - interrupt-parent = <&gpio2>; - interrupts = <13 IRQ_TYPE_EDGE_FALLING>; - reset-gpios = <&gpio2 4 GPIO_ACTIVE_LOW>; - touchscreen-size-x = <800>; - touchscreen-size-y = <480>; - }; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_hog: hoggrp { - fsl,pins = < - MX7D_PAD_EPDC_DATA00__GPIO2_IO0 0x14 - MX7D_PAD_EPDC_DATA01__GPIO2_IO1 0x14 - MX7D_PAD_EPDC_DATA02__GPIO2_IO2 0x14 - MX7D_PAD_EPDC_DATA03__GPIO2_IO3 0x14 - MX7D_PAD_EPDC_DATA05__GPIO2_IO5 0x14 - MX7D_PAD_EPDC_DATA12__GPIO2_IO12 0x14 - MX7D_PAD_EPDC_DATA07__GPIO2_IO7 0x14 - >; - }; - - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - MX7D_PAD_EPDC_DATA06__GPIO2_IO6 0x14 - >; - }; - - pinctrl_touchscreen: touchscreengrp { - fsl,pins = < - MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x14 - MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x14 - >; - }; - -}; diff --git a/sys/gnu/dts/arm/imx7d-pico.dtsi b/sys/gnu/dts/arm/imx7d-pico.dtsi deleted file mode 100644 index e57da0d32b9..00000000000 --- a/sys/gnu/dts/arm/imx7d-pico.dtsi +++ /dev/null @@ -1,675 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// -// Copyright 2017 NXP - -/dts-v1/; - -#include "imx7d.dtsi" - -/ { - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm4 0 50000 0>; - brightness-levels = <0 36 72 108 144 180 216 255>; - default-brightness-level = <6>; - }; - - /* Will be filled by the bootloader */ - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0>; - }; - - panel { - compatible = "vxt,vl050-8048nt-c01"; - backlight = <&backlight>; - power-supply = <®_lcd_3v3>; - - port { - panel_in: endpoint { - remote-endpoint = <&display_out>; - }; - }; - }; - - reg_lcd_3v3: regulator-lcd-3v3 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_lcdreg_on>; - regulator-name = "lcd-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio1 6 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_wlreg_on: regulator-wlreg_on { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_wlreg_on>; - regulator-name = "wlreg_on"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio4 16 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_2p5v: regulator-2p5v { - compatible = "regulator-fixed"; - regulator-name = "2P5V"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_usb_otg1_vbus: regulator-usb-otg1-vbus { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg1_pwr>; - compatible = "regulator-fixed"; - regulator-name = "usb_otg1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio4 5 GPIO_ACTIVE_LOW>; - }; - - reg_usb_otg2_vbus: regulator-usb-otg2-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg2_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_vref_1v8: regulator-vref-1v8 { - compatible = "regulator-fixed"; - regulator-name = "vref-1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - usdhc2_pwrseq: usdhc2_pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&clks IMX7D_CLKO2_ROOT_DIV>; - clock-names = "ext_clock"; - }; -}; - -&clks { - assigned-clocks = <&clks IMX7D_CLKO2_ROOT_SRC>, - <&clks IMX7D_CLKO2_ROOT_DIV>; - assigned-clock-parents = <&clks IMX7D_CKIL>; - assigned-clock-rates = <0>, <32768>; -}; - -&ecspi3 { - cs-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi3>; - status = "okay"; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet1>; - assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>, - <&clks IMX7D_ENET1_TIME_ROOT_CLK>; - assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; - assigned-clock-rates = <0>, <100000000>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy0>; - fsl,magic-packet; - phy-reset-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - status = "okay"; - }; - }; -}; - -&flexcan1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can1>; - status = "okay"; -}; - -&flexcan2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can2>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&i2c4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4>; - status = "okay"; - - pmic: pfuze3000@8 { - compatible = "fsl,pfuze3000"; - reg = <0x08>; - - regulators { - sw1a_reg: sw1a { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - /* use sw1c_reg to align with pfuze100/pfuze200 */ - sw1c_reg: sw1b { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1475000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1850000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3a_reg: sw3 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1650000>; - regulator-boot-on; - regulator-always-on; - }; - - swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - }; - - snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - vgen1_reg: vldo1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen2_reg: vldo2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen3_reg: vccsd { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen4_reg: v33 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen5_reg: vldo3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen6_reg: vldo4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; -}; - -&lcdif { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcdif>; - status = "okay"; - - port { - display_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; -}; - -&sai1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai1>; - assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>, - <&clks IMX7D_SAI1_ROOT_CLK>; - assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; - assigned-clock-rates = <0>, <24576000>; - status = "okay"; -}; - - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "okay"; -}; - -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm2>; - status = "okay"; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; - status = "okay"; -}; - -&pwm4 { /* Backlight */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm4>; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - assigned-clocks = <&clks IMX7D_UART5_ROOT_SRC>; - assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; - status = "okay"; -}; - -&uart6 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart6>; - assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>; - assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; - uart-has-rtscts; - status = "okay"; -}; - -&uart7 { /* Bluetooth */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart7>; - assigned-clocks = <&clks IMX7D_UART7_ROOT_SRC>; - assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; - uart-has-rtscts; - status = "okay"; -}; - -&usbotg1 { - vbus-supply = <®_usb_otg1_vbus>; - status = "okay"; -}; - -&usbotg2 { - vbus-supply = <®_usb_otg2_vbus>; - dr_mode = "host"; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>; - cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; - bus-width = <4>; - tuning-step = <2>; - vmmc-supply = <®_3p3v>; - wakeup-source; - no-1-8-v; - keep-power-in-suspend; - status = "okay"; -}; - -&usdhc2 { /* Wifi SDIO */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2 &pinctrl_wifi_clk>; - no-1-8-v; - non-removable; - keep-power-in-suspend; - wakeup-source; - vmmc-supply = <®_wlreg_on>; - mmc-pwrseq = <&usdhc2_pwrseq>; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>; - assigned-clock-rates = <400000000>; - bus-width = <8>; - no-1-8-v; - fsl,tuning-step = <2>; - non-removable; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl_ecspi3: ecspi3grp { - fsl,pins = < - MX7D_PAD_I2C1_SCL__ECSPI3_MISO 0x2 - MX7D_PAD_I2C1_SDA__ECSPI3_MOSI 0x2 - MX7D_PAD_I2C2_SCL__ECSPI3_SCLK 0x2 - MX7D_PAD_I2C2_SDA__GPIO4_IO11 0x14 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX7D_PAD_UART1_TX_DATA__I2C1_SDA 0x4000007f - MX7D_PAD_UART1_RX_DATA__I2C1_SCL 0x4000007f - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX7D_PAD_UART2_TX_DATA__I2C2_SDA 0x4000007f - MX7D_PAD_UART2_RX_DATA__I2C2_SCL 0x4000007f - >; - }; - - pinctrl_enet1: enet1grp { - fsl,pins = < - MX7D_PAD_SD2_CD_B__ENET1_MDIO 0x3 - MX7D_PAD_SD2_WP__ENET1_MDC 0x3 - MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1 - MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1 - MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1 - MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1 - MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1 - MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1 - MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1 - MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1 - MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1 - MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1 - MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1 - MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1 - MX7D_PAD_SD3_RESET_B__GPIO6_IO11 0x1 /* Ethernet reset */ - >; - }; - - pinctrl_can1: can1frp { - fsl,pins = < - MX7D_PAD_SAI1_RX_DATA__FLEXCAN1_RX 0x59 - MX7D_PAD_SAI1_TX_BCLK__FLEXCAN1_TX 0x59 - >; - }; - - pinctrl_can2: can2frp { - fsl,pins = < - MX7D_PAD_SAI1_TX_SYNC__FLEXCAN2_RX 0x59 - MX7D_PAD_SAI1_TX_DATA__FLEXCAN2_TX 0x59 - >; - }; - - pinctrl_i2c4: i2c4grp { - fsl,pins = < - MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA 0x4000007f - MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL 0x4000007f - >; - }; - - pinctrl_lcdif: lcdifgrp { - fsl,pins = < - MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79 - MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79 - MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79 - MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79 - MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79 - MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79 - MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79 - MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79 - MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79 - MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79 - MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79 - MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79 - MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79 - MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79 - MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79 - MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79 - MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79 - MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79 - MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79 - MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79 - MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79 - MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79 - MX7D_PAD_LCD_DATA22__LCD_DATA22 0x79 - MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79 - MX7D_PAD_LCD_CLK__LCD_CLK 0x79 - MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x78 - MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x78 - MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x78 - MX7D_PAD_LCD_RESET__GPIO3_IO4 0x14 - >; - }; - - pinctrl_pwm1: pwm1 { - fsl,pins = < - MX7D_PAD_GPIO1_IO08__PWM1_OUT 0x7f - >; - }; - - pinctrl_pwm2: pwm2 { - fsl,pins = < - MX7D_PAD_GPIO1_IO09__PWM2_OUT 0x7f - >; - }; - - pinctrl_pwm3: pwm3 { - fsl,pins = < - MX7D_PAD_GPIO1_IO10__PWM3_OUT 0x7f - >; - }; - - pinctrl_pwm4: pwm4grp{ - fsl,pins = < - MX7D_PAD_GPIO1_IO11__PWM4_OUT 0x7f - >; - }; - - pinctrl_reg_wlreg_on: regregongrp { - fsl,pins = < - MX7D_PAD_ECSPI1_SCLK__GPIO4_IO16 0x59 - >; - }; - - pinctrl_sai1: sai1grp { - fsl,pins = < - MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK 0x1f - MX7D_PAD_ENET1_CRS__SAI1_TX_SYNC 0x1f - MX7D_PAD_ENET1_COL__SAI1_TX_DATA0 0x30 - MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0 0x1f - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX7D_PAD_I2C4_SDA__UART5_DCE_TX 0x79 - MX7D_PAD_I2C4_SCL__UART5_DCE_RX 0x79 - >; - }; - - pinctrl_uart6: uart6grp { - fsl,pins = < - MX7D_PAD_EPDC_DATA08__UART6_DCE_RX 0x79 - MX7D_PAD_EPDC_DATA09__UART6_DCE_TX 0x79 - MX7D_PAD_EPDC_DATA10__UART6_DCE_RTS 0x79 - MX7D_PAD_EPDC_DATA11__UART6_DCE_CTS 0x79 - >; - }; - - pinctrl_uart7: uart7grp { - fsl,pins = < - MX7D_PAD_ECSPI2_MOSI__UART7_DCE_TX 0x79 - MX7D_PAD_ECSPI2_SCLK__UART7_DCE_RX 0x79 - MX7D_PAD_ECSPI2_SS0__UART7_DCE_CTS 0x79 - MX7D_PAD_ECSPI2_MISO__UART7_DCE_RTS 0x79 - >; - }; - - pinctrl_usbotg1_pwr: usbotg_pwr { - fsl,pins = < - MX7D_PAD_UART3_TX_DATA__GPIO4_IO5 0x14 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX7D_PAD_SD1_CMD__SD1_CMD 0x59 - MX7D_PAD_SD1_CLK__SD1_CLK 0x19 - MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 - MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 - MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 - MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 - MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x15 - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1grp_100mhz { - fsl,pins = < - MX7D_PAD_SD1_CMD__SD1_CMD 0x5a - MX7D_PAD_SD1_CLK__SD1_CLK 0x1a - MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a - MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a - MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a - MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a - MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x15 - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1grp_200mhz { - fsl,pins = < - MX7D_PAD_SD1_CMD__SD1_CMD 0x5b - MX7D_PAD_SD1_CLK__SD1_CLK 0x1b - MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b - MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b - MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b - MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b - MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x15 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX7D_PAD_SD2_CMD__SD2_CMD 0x59 - MX7D_PAD_SD2_CLK__SD2_CLK 0x19 - MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59 - MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59 - MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59 - MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX7D_PAD_SD3_CMD__SD3_CMD 0x59 - MX7D_PAD_SD3_CLK__SD3_CLK 0x19 - MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 - MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 - MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 - MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 - MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 - MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 - MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 - MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { - fsl,pins = < - MX7D_PAD_SD3_CMD__SD3_CMD 0x5a - MX7D_PAD_SD3_CLK__SD3_CLK 0x1a - MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a - MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a - MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a - MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a - MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a - MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a - MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a - MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3grp_200mhz { - fsl,pins = < - MX7D_PAD_SD3_CMD__SD3_CMD 0x5b - MX7D_PAD_SD3_CLK__SD3_CLK 0x1b - MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b - MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b - MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b - MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b - MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b - MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b - MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b - MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b - >; - }; -}; - -&iomuxc_lpsr { - pinctrl_wifi_clk: wificlkgrp { - fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO03__CCM_CLKO2 0x7d - >; - }; - - pinctrl_reg_lcdreg_on: reglcdongrp { - fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO06__GPIO1_IO6 0x59 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74 - >; - }; -}; diff --git a/sys/gnu/dts/arm/imx7d-pinfunc.h b/sys/gnu/dts/arm/imx7d-pinfunc.h deleted file mode 100644 index 08ca1608fdb..00000000000 --- a/sys/gnu/dts/arm/imx7d-pinfunc.h +++ /dev/null @@ -1,1154 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. - */ - -#ifndef __DTS_IMX7D_PINFUNC_H -#define __DTS_IMX7D_PINFUNC_H - -/* - * The pin function ID is a tuple of - * - */ - -#define MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x0000 0x0030 0x0000 0x0 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO00__PWM4_OUT 0x0000 0x0030 0x0000 0x1 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_ANY 0x0000 0x0030 0x0000 0x2 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x0000 0x0030 0x0000 0x3 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG__RST_B_DEB 0x0000 0x0030 0x0000 0x4 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x0004 0x0034 0x0000 0x0 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x0004 0x0034 0x0000 0x1 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO01__CCM_ENET_REF_CLK3 0x0004 0x0034 0x0000 0x2 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO01__SAI1_MCLK 0x0004 0x0034 0x0000 0x3 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO01__ANATOP_24M_OUT 0x0004 0x0034 0x0000 0x4 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO01__OBSERVE0_OUT 0x0004 0x0034 0x0000 0x6 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO02__GPIO1_IO2 0x0008 0x0038 0x0000 0x0 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO02__PWM2_OUT 0x0008 0x0038 0x0000 0x1 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO02__CCM_ENET_REF_CLK1 0x0008 0x0038 0x0564 0x2 0x3 -#define MX7D_PAD_LPSR_GPIO1_IO02__SAI2_MCLK 0x0008 0x0038 0x0000 0x3 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO02__CCM_CLKO1 0x0008 0x0038 0x0000 0x5 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO02__OBSERVE1_OUT 0x0008 0x0038 0x0000 0x6 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO02__USB_OTG1_ID 0x0008 0x0038 0x0734 0x7 0x3 -#define MX7D_PAD_LPSR_GPIO1_IO03__GPIO1_IO3 0x000C 0x003C 0x0000 0x0 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO03__PWM3_OUT 0x000C 0x003C 0x0000 0x1 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO03__CCM_ENET_REF_CLK2 0x000C 0x003C 0x0570 0x2 0x3 -#define MX7D_PAD_LPSR_GPIO1_IO03__SAI3_MCLK 0x000C 0x003C 0x0000 0x3 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO03__CCM_CLKO2 0x000C 0x003C 0x0000 0x5 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO03__OBSERVE2_OUT 0x000C 0x003C 0x0000 0x6 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO03__USB_OTG2_ID 0x000C 0x003C 0x0730 0x7 0x3 -#define MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4 0x0010 0x0040 0x0000 0x0 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO04__USB_OTG1_OC 0x0010 0x0040 0x072C 0x1 0x1 -#define MX7D_PAD_LPSR_GPIO1_IO04__FLEXTIMER1_CH4 0x0010 0x0040 0x0594 0x2 0x1 -#define MX7D_PAD_LPSR_GPIO1_IO04__UART5_DCE_CTS 0x0010 0x0040 0x0000 0x3 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO04__UART5_DTE_RTS 0x0010 0x0040 0x0710 0x3 0x4 -#define MX7D_PAD_LPSR_GPIO1_IO04__I2C1_SCL 0x0010 0x0040 0x05D4 0x4 0x2 -#define MX7D_PAD_LPSR_GPIO1_IO04__OBSERVE3_OUT 0x0010 0x0040 0x0000 0x6 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x0014 0x0044 0x0000 0x0 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO05__USB_OTG1_PWR 0x0014 0x0044 0x0000 0x1 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO05__FLEXTIMER1_CH5 0x0014 0x0044 0x0598 0x2 0x1 -#define MX7D_PAD_LPSR_GPIO1_IO05__UART5_DCE_RTS 0x0014 0x0044 0x0710 0x3 0x5 -#define MX7D_PAD_LPSR_GPIO1_IO05__UART5_DTE_CTS 0x0014 0x0044 0x0000 0x3 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO05__I2C1_SDA 0x0014 0x0044 0x05D8 0x4 0x2 -#define MX7D_PAD_LPSR_GPIO1_IO05__OBSERVE4_OUT 0x0014 0x0044 0x0000 0x6 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO06__GPIO1_IO6 0x0018 0x0048 0x0000 0x0 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO06__USB_OTG2_OC 0x0018 0x0048 0x0728 0x1 0x1 -#define MX7D_PAD_LPSR_GPIO1_IO06__FLEXTIMER1_CH6 0x0018 0x0048 0x059C 0x2 0x1 -#define MX7D_PAD_LPSR_GPIO1_IO06__UART5_DCE_RX 0x0018 0x0048 0x0714 0x3 0x4 -#define MX7D_PAD_LPSR_GPIO1_IO06__UART5_DTE_TX 0x0018 0x0048 0x0000 0x3 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO06__I2C2_SCL 0x0018 0x0048 0x05DC 0x4 0x2 -#define MX7D_PAD_LPSR_GPIO1_IO06__CCM_WAIT 0x0018 0x0048 0x0000 0x5 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO06__KPP_ROW4 0x0018 0x0048 0x0624 0x6 0x1 -#define MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x001C 0x004C 0x0000 0x0 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO07__USB_OTG2_PWR 0x001C 0x004C 0x0000 0x1 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO07__FLEXTIMER1_CH7 0x001C 0x004C 0x05A0 0x2 0x1 -#define MX7D_PAD_LPSR_GPIO1_IO07__UART5_DCE_TX 0x001C 0x004C 0x0000 0x3 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO07__UART5_DTE_RX 0x001C 0x004C 0x0714 0x3 0x5 -#define MX7D_PAD_LPSR_GPIO1_IO07__I2C2_SDA 0x001C 0x004C 0x05E0 0x4 0x2 -#define MX7D_PAD_LPSR_GPIO1_IO07__CCM_STOP 0x001C 0x004C 0x0000 0x5 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO07__KPP_COL4 0x001C 0x004C 0x0604 0x6 0x1 -#define MX7D_PAD_GPIO1_IO08__GPIO1_IO8 0x0014 0x026C 0x0000 0x0 0x0 -#define MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x0014 0x026C 0x0000 0x1 0x0 -#define MX7D_PAD_GPIO1_IO08__WDOG1_WDOG_B 0x0014 0x026C 0x0000 0x2 0x0 -#define MX7D_PAD_GPIO1_IO08__UART3_DCE_RX 0x0014 0x026C 0x0704 0x3 0x0 -#define MX7D_PAD_GPIO1_IO08__UART3_DTE_TX 0x0014 0x026C 0x0000 0x3 0x0 -#define MX7D_PAD_GPIO1_IO08__I2C3_SCL 0x0014 0x026C 0x05E4 0x4 0x0 -#define MX7D_PAD_GPIO1_IO08__KPP_COL5 0x0014 0x026C 0x0608 0x6 0x0 -#define MX7D_PAD_GPIO1_IO08__PWM1_OUT 0x0014 0x026C 0x0000 0x7 0x0 -#define MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x0018 0x0270 0x0000 0x0 0x0 -#define MX7D_PAD_GPIO1_IO09__SD1_LCTL 0x0018 0x0270 0x0000 0x1 0x0 -#define MX7D_PAD_GPIO1_IO09__CCM_ENET_REF_CLK3 0x0018 0x0270 0x0000 0x2 0x0 -#define MX7D_PAD_GPIO1_IO09__UART3_DCE_TX 0x0018 0x0270 0x0000 0x3 0x0 -#define MX7D_PAD_GPIO1_IO09__UART3_DTE_RX 0x0018 0x0270 0x0704 0x3 0x1 -#define MX7D_PAD_GPIO1_IO09__I2C3_SDA 0x0018 0x0270 0x05E8 0x4 0x0 -#define MX7D_PAD_GPIO1_IO09__CCM_PMIC_READY 0x0018 0x0270 0x04F4 0x5 0x0 -#define MX7D_PAD_GPIO1_IO09__KPP_ROW5 0x0018 0x0270 0x0628 0x6 0x0 -#define MX7D_PAD_GPIO1_IO09__PWM2_OUT 0x0018 0x0270 0x0000 0x7 0x0 -#define MX7D_PAD_GPIO1_IO10__GPIO1_IO10 0x001C 0x0274 0x0000 0x0 0x0 -#define MX7D_PAD_GPIO1_IO10__SD2_LCTL 0x001C 0x0274 0x0000 0x1 0x0 -#define MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x001C 0x0274 0x0568 0x2 0x0 -#define MX7D_PAD_GPIO1_IO10__UART3_DCE_RTS 0x001C 0x0274 0x0700 0x3 0x0 -#define MX7D_PAD_GPIO1_IO10__UART3_DTE_CTS 0x001C 0x0274 0x0000 0x3 0x0 -#define MX7D_PAD_GPIO1_IO10__I2C4_SCL 0x001C 0x0274 0x05EC 0x4 0x0 -#define MX7D_PAD_GPIO1_IO10__FLEXTIMER1_PHA 0x001C 0x0274 0x05A4 0x5 0x0 -#define MX7D_PAD_GPIO1_IO10__KPP_COL6 0x001C 0x0274 0x060C 0x6 0x0 -#define MX7D_PAD_GPIO1_IO10__PWM3_OUT 0x001C 0x0274 0x0000 0x7 0x0 -#define MX7D_PAD_GPIO1_IO11__GPIO1_IO11 0x0020 0x0278 0x0000 0x0 0x0 -#define MX7D_PAD_GPIO1_IO11__SD3_LCTL 0x0020 0x0278 0x0000 0x1 0x0 -#define MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x0020 0x0278 0x0000 0x2 0x0 -#define MX7D_PAD_GPIO1_IO11__UART3_DCE_CTS 0x0020 0x0278 0x0000 0x3 0x0 -#define MX7D_PAD_GPIO1_IO11__UART3_DTE_RTS 0x0020 0x0278 0x0700 0x3 0x1 -#define MX7D_PAD_GPIO1_IO11__I2C4_SDA 0x0020 0x0278 0x05F0 0x4 0x0 -#define MX7D_PAD_GPIO1_IO11__FLEXTIMER1_PHB 0x0020 0x0278 0x05A8 0x5 0x0 -#define MX7D_PAD_GPIO1_IO11__KPP_ROW6 0x0020 0x0278 0x062C 0x6 0x0 -#define MX7D_PAD_GPIO1_IO11__PWM4_OUT 0x0020 0x0278 0x0000 0x7 0x0 -#define MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x0024 0x027C 0x0000 0x0 0x0 -#define MX7D_PAD_GPIO1_IO12__SD2_VSELECT 0x0024 0x027C 0x0000 0x1 0x0 -#define MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 0x0024 0x027C 0x0564 0x2 0x0 -#define MX7D_PAD_GPIO1_IO12__FLEXCAN1_RX 0x0024 0x027C 0x04DC 0x3 0x0 -#define MX7D_PAD_GPIO1_IO12__CM4_NMI 0x0024 0x027C 0x0000 0x4 0x0 -#define MX7D_PAD_GPIO1_IO12__CCM_EXT_CLK1 0x0024 0x027C 0x04E4 0x5 0x0 -#define MX7D_PAD_GPIO1_IO12__SNVS_VIO_5 0x0024 0x027C 0x0000 0x6 0x0 -#define MX7D_PAD_GPIO1_IO12__USB_OTG1_ID 0x0024 0x027C 0x0734 0x7 0x0 -#define MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x0028 0x0280 0x0000 0x0 0x0 -#define MX7D_PAD_GPIO1_IO13__SD3_VSELECT 0x0028 0x0280 0x0000 0x1 0x0 -#define MX7D_PAD_GPIO1_IO13__CCM_ENET_REF_CLK2 0x0028 0x0280 0x0570 0x2 0x0 -#define MX7D_PAD_GPIO1_IO13__FLEXCAN1_TX 0x0028 0x0280 0x0000 0x3 0x0 -#define MX7D_PAD_GPIO1_IO13__CCM_PMIC_READY 0x0028 0x0280 0x04F4 0x4 0x1 -#define MX7D_PAD_GPIO1_IO13__CCM_EXT_CLK2 0x0028 0x0280 0x04E8 0x5 0x0 -#define MX7D_PAD_GPIO1_IO13__SNVS_VIO_5_CTL 0x0028 0x0280 0x0000 0x6 0x0 -#define MX7D_PAD_GPIO1_IO13__USB_OTG2_ID 0x0028 0x0280 0x0730 0x7 0x0 -#define MX7D_PAD_GPIO1_IO14__GPIO1_IO14 0x002C 0x0284 0x0000 0x0 0x0 -#define MX7D_PAD_GPIO1_IO14__SD3_CD_B 0x002C 0x0284 0x0738 0x1 0x0 -#define MX7D_PAD_GPIO1_IO14__ENET2_MDIO 0x002C 0x0284 0x0574 0x2 0x0 -#define MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x002C 0x0284 0x04E0 0x3 0x0 -#define MX7D_PAD_GPIO1_IO14__WDOG3_WDOG_B 0x002C 0x0284 0x0000 0x4 0x0 -#define MX7D_PAD_GPIO1_IO14__CCM_EXT_CLK3 0x002C 0x0284 0x04EC 0x5 0x0 -#define MX7D_PAD_GPIO1_IO14__SDMA_EXT_EVENT0 0x002C 0x0284 0x06D8 0x6 0x0 -#define MX7D_PAD_GPIO1_IO15__GPIO1_IO15 0x0030 0x0288 0x0000 0x0 0x0 -#define MX7D_PAD_GPIO1_IO15__SD3_WP 0x0030 0x0288 0x073C 0x1 0x0 -#define MX7D_PAD_GPIO1_IO15__ENET2_MDC 0x0030 0x0288 0x0000 0x2 0x0 -#define MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x0030 0x0288 0x0000 0x3 0x0 -#define MX7D_PAD_GPIO1_IO15__WDOG4_WDOG_B 0x0030 0x0288 0x0000 0x4 0x0 -#define MX7D_PAD_GPIO1_IO15__CCM_EXT_CLK4 0x0030 0x0288 0x04F0 0x5 0x0 -#define MX7D_PAD_GPIO1_IO15__SDMA_EXT_EVENT1 0x0030 0x0288 0x06DC 0x6 0x0 -#define MX7D_PAD_EPDC_DATA00__EPDC_DATA0 0x0034 0x02A4 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_DATA00__SIM1_PORT2_TRXD 0x0034 0x02A4 0x0000 0x1 0x0 -#define MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 0x0034 0x02A4 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_DATA00__KPP_ROW3 0x0034 0x02A4 0x0620 0x3 0x0 -#define MX7D_PAD_EPDC_DATA00__EIM_AD0 0x0034 0x02A4 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_DATA00__GPIO2_IO0 0x0034 0x02A4 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_DATA00__LCD_DATA0 0x0034 0x02A4 0x0638 0x6 0x0 -#define MX7D_PAD_EPDC_DATA00__LCD_CLK 0x0034 0x02A4 0x0000 0x7 0x0 -#define MX7D_PAD_EPDC_DATA01__EPDC_DATA1 0x0038 0x02A8 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_DATA01__SIM1_PORT2_CLK 0x0038 0x02A8 0x0000 0x1 0x0 -#define MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 0x0038 0x02A8 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_DATA01__KPP_COL3 0x0038 0x02A8 0x0600 0x3 0x0 -#define MX7D_PAD_EPDC_DATA01__EIM_AD1 0x0038 0x02A8 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_DATA01__GPIO2_IO1 0x0038 0x02A8 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_DATA01__LCD_DATA1 0x0038 0x02A8 0x063C 0x6 0x0 -#define MX7D_PAD_EPDC_DATA01__LCD_ENABLE 0x0038 0x02A8 0x0000 0x7 0x0 -#define MX7D_PAD_EPDC_DATA02__EPDC_DATA2 0x003C 0x02AC 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_DATA02__SIM1_PORT2_RST_B 0x003C 0x02AC 0x0000 0x1 0x0 -#define MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 0x003C 0x02AC 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_DATA02__KPP_ROW2 0x003C 0x02AC 0x061C 0x3 0x0 -#define MX7D_PAD_EPDC_DATA02__EIM_AD2 0x003C 0x02AC 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_DATA02__GPIO2_IO2 0x003C 0x02AC 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_DATA02__LCD_DATA2 0x003C 0x02AC 0x0640 0x6 0x0 -#define MX7D_PAD_EPDC_DATA02__LCD_VSYNC 0x003C 0x02AC 0x0698 0x7 0x0 -#define MX7D_PAD_EPDC_DATA03__EPDC_DATA3 0x0040 0x02B0 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_DATA03__SIM1_PORT2_SVEN 0x0040 0x02B0 0x0000 0x1 0x0 -#define MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 0x0040 0x02B0 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_DATA03__KPP_COL2 0x0040 0x02B0 0x05FC 0x3 0x0 -#define MX7D_PAD_EPDC_DATA03__EIM_AD3 0x0040 0x02B0 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_DATA03__GPIO2_IO3 0x0040 0x02B0 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_DATA03__LCD_DATA3 0x0040 0x02B0 0x0644 0x6 0x0 -#define MX7D_PAD_EPDC_DATA03__LCD_HSYNC 0x0040 0x02B0 0x0000 0x7 0x0 -#define MX7D_PAD_EPDC_DATA04__EPDC_DATA4 0x0044 0x02B4 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_DATA04__SIM1_PORT2_PD 0x0044 0x02B4 0x0000 0x1 0x0 -#define MX7D_PAD_EPDC_DATA04__QSPI_A_DQS 0x0044 0x02B4 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_DATA04__KPP_ROW1 0x0044 0x02B4 0x0618 0x3 0x0 -#define MX7D_PAD_EPDC_DATA04__EIM_AD4 0x0044 0x02B4 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x0044 0x02B4 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_DATA04__LCD_DATA4 0x0044 0x02B4 0x0648 0x6 0x0 -#define MX7D_PAD_EPDC_DATA04__JTAG_FAIL 0x0044 0x02B4 0x0000 0x7 0x0 -#define MX7D_PAD_EPDC_DATA05__EPDC_DATA5 0x0048 0x02B8 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_DATA05__SIM2_PORT2_TRXD 0x0048 0x02B8 0x0000 0x1 0x0 -#define MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK 0x0048 0x02B8 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_DATA05__KPP_COL1 0x0048 0x02B8 0x05F8 0x3 0x0 -#define MX7D_PAD_EPDC_DATA05__EIM_AD5 0x0048 0x02B8 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_DATA05__GPIO2_IO5 0x0048 0x02B8 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_DATA05__LCD_DATA5 0x0048 0x02B8 0x064C 0x6 0x0 -#define MX7D_PAD_EPDC_DATA05__JTAG_ACTIVE 0x0048 0x02B8 0x0000 0x7 0x0 -#define MX7D_PAD_EPDC_DATA06__EPDC_DATA6 0x004C 0x02BC 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_DATA06__SIM2_PORT2_CLK 0x004C 0x02BC 0x0000 0x1 0x0 -#define MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B 0x004C 0x02BC 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_DATA06__KPP_ROW0 0x004C 0x02BC 0x0614 0x3 0x0 -#define MX7D_PAD_EPDC_DATA06__EIM_AD6 0x004C 0x02BC 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_DATA06__GPIO2_IO6 0x004C 0x02BC 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_DATA06__LCD_DATA6 0x004C 0x02BC 0x0650 0x6 0x0 -#define MX7D_PAD_EPDC_DATA06__JTAG_DE_B 0x004C 0x02BC 0x0000 0x7 0x0 -#define MX7D_PAD_EPDC_DATA07__EPDC_DATA7 0x0050 0x02C0 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_DATA07__SIM2_PORT2_RST_B 0x0050 0x02C0 0x0000 0x1 0x0 -#define MX7D_PAD_EPDC_DATA07__QSPI_A_SS1_B 0x0050 0x02C0 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_DATA07__KPP_COL0 0x0050 0x02C0 0x05F4 0x3 0x0 -#define MX7D_PAD_EPDC_DATA07__EIM_AD7 0x0050 0x02C0 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_DATA07__GPIO2_IO7 0x0050 0x02C0 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_DATA07__LCD_DATA7 0x0050 0x02C0 0x0654 0x6 0x0 -#define MX7D_PAD_EPDC_DATA07__JTAG_DONE 0x0050 0x02C0 0x0000 0x7 0x0 -#define MX7D_PAD_EPDC_DATA08__EPDC_DATA8 0x0054 0x02C4 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_DATA08__SIM1_PORT1_TRXD 0x0054 0x02C4 0x06E4 0x1 0x0 -#define MX7D_PAD_EPDC_DATA08__QSPI_B_DATA0 0x0054 0x02C4 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_DATA08__UART6_DCE_RX 0x0054 0x02C4 0x071C 0x3 0x0 -#define MX7D_PAD_EPDC_DATA08__UART6_DTE_TX 0x0054 0x02C4 0x0000 0x3 0x0 -#define MX7D_PAD_EPDC_DATA08__EIM_OE 0x0054 0x02C4 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_DATA08__GPIO2_IO8 0x0054 0x02C4 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_DATA08__LCD_DATA8 0x0054 0x02C4 0x0658 0x6 0x0 -#define MX7D_PAD_EPDC_DATA08__LCD_BUSY 0x0054 0x02C4 0x0634 0x7 0x0 -#define MX7D_PAD_EPDC_DATA08__EPDC_SDCLK 0x0054 0x02C4 0x0000 0x8 0x0 -#define MX7D_PAD_EPDC_DATA09__EPDC_DATA9 0x0058 0x02C8 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_DATA09__SIM1_PORT1_CLK 0x0058 0x02C8 0x0000 0x1 0x0 -#define MX7D_PAD_EPDC_DATA09__QSPI_B_DATA1 0x0058 0x02C8 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_DATA09__UART6_DCE_TX 0x0058 0x02C8 0x0000 0x3 0x0 -#define MX7D_PAD_EPDC_DATA09__UART6_DTE_RX 0x0058 0x02C8 0x071C 0x3 0x1 -#define MX7D_PAD_EPDC_DATA09__EIM_RW 0x0058 0x02C8 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_DATA09__GPIO2_IO9 0x0058 0x02C8 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_DATA09__LCD_DATA9 0x0058 0x02C8 0x065C 0x6 0x0 -#define MX7D_PAD_EPDC_DATA09__LCD_DATA0 0x0058 0x02C8 0x0638 0x7 0x1 -#define MX7D_PAD_EPDC_DATA09__EPDC_SDLE 0x0058 0x02C8 0x0000 0x8 0x0 -#define MX7D_PAD_EPDC_DATA10__EPDC_DATA10 0x005C 0x02CC 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_DATA10__SIM1_PORT1_RST_B 0x005C 0x02CC 0x0000 0x1 0x0 -#define MX7D_PAD_EPDC_DATA10__QSPI_B_DATA2 0x005C 0x02CC 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_DATA10__UART6_DCE_RTS 0x005C 0x02CC 0x0718 0x3 0x0 -#define MX7D_PAD_EPDC_DATA10__UART6_DTE_CTS 0x005C 0x02CC 0x0000 0x3 0x0 -#define MX7D_PAD_EPDC_DATA10__EIM_CS0_B 0x005C 0x02CC 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_DATA10__GPIO2_IO10 0x005C 0x02CC 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_DATA10__LCD_DATA10 0x005C 0x02CC 0x0660 0x6 0x0 -#define MX7D_PAD_EPDC_DATA10__LCD_DATA9 0x005C 0x02CC 0x065C 0x7 0x1 -#define MX7D_PAD_EPDC_DATA10__EPDC_SDOE 0x005C 0x02CC 0x0000 0x8 0x0 -#define MX7D_PAD_EPDC_DATA11__EPDC_DATA11 0x0060 0x02D0 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_DATA11__SIM1_PORT1_SVEN 0x0060 0x02D0 0x0000 0x1 0x0 -#define MX7D_PAD_EPDC_DATA11__QSPI_B_DATA3 0x0060 0x02D0 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_DATA11__UART6_DCE_CTS 0x0060 0x02D0 0x0000 0x3 0x0 -#define MX7D_PAD_EPDC_DATA11__UART6_DTE_RTS 0x0060 0x02D0 0x0718 0x3 0x1 -#define MX7D_PAD_EPDC_DATA11__EIM_BCLK 0x0060 0x02D0 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_DATA11__GPIO2_IO11 0x0060 0x02D0 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_DATA11__LCD_DATA11 0x0060 0x02D0 0x0664 0x6 0x0 -#define MX7D_PAD_EPDC_DATA11__LCD_DATA1 0x0060 0x02D0 0x063C 0x7 0x1 -#define MX7D_PAD_EPDC_DATA11__EPDC_SDCE0 0x0060 0x02D0 0x0000 0x8 0x0 -#define MX7D_PAD_EPDC_DATA12__EPDC_DATA12 0x0064 0x02D4 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_DATA12__SIM1_PORT1_PD 0x0064 0x02D4 0x06E0 0x1 0x0 -#define MX7D_PAD_EPDC_DATA12__QSPI_B_DQS 0x0064 0x02D4 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_DATA12__UART7_DCE_RX 0x0064 0x02D4 0x0724 0x3 0x0 -#define MX7D_PAD_EPDC_DATA12__UART7_DTE_TX 0x0064 0x02D4 0x0000 0x3 0x0 -#define MX7D_PAD_EPDC_DATA12__EIM_LBA_B 0x0064 0x02D4 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_DATA12__GPIO2_IO12 0x0064 0x02D4 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_DATA12__LCD_DATA12 0x0064 0x02D4 0x0668 0x6 0x0 -#define MX7D_PAD_EPDC_DATA12__LCD_DATA21 0x0064 0x02D4 0x068C 0x7 0x0 -#define MX7D_PAD_EPDC_DATA12__EPDC_GDCLK 0x0064 0x02D4 0x0000 0x8 0x0 -#define MX7D_PAD_EPDC_DATA13__EPDC_DATA13 0x0068 0x02D8 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_DATA13__SIM2_PORT1_TRXD 0x0068 0x02D8 0x06EC 0x1 0x0 -#define MX7D_PAD_EPDC_DATA13__QSPI_B_SCLK 0x0068 0x02D8 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_DATA13__UART7_DCE_TX 0x0068 0x02D8 0x0000 0x3 0x0 -#define MX7D_PAD_EPDC_DATA13__UART7_DTE_RX 0x0068 0x02D8 0x0724 0x3 0x1 -#define MX7D_PAD_EPDC_DATA13__EIM_WAIT 0x0068 0x02D8 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x0068 0x02D8 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_DATA13__LCD_DATA13 0x0068 0x02D8 0x066C 0x6 0x0 -#define MX7D_PAD_EPDC_DATA13__LCD_CS 0x0068 0x02D8 0x0000 0x7 0x0 -#define MX7D_PAD_EPDC_DATA13__EPDC_GDOE 0x0068 0x02D8 0x0000 0x8 0x0 -#define MX7D_PAD_EPDC_DATA14__EPDC_DATA14 0x006C 0x02DC 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_DATA14__SIM2_PORT1_CLK 0x006C 0x02DC 0x0000 0x1 0x0 -#define MX7D_PAD_EPDC_DATA14__QSPI_B_SS0_B 0x006C 0x02DC 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_DATA14__UART7_DCE_RTS 0x006C 0x02DC 0x0720 0x3 0x0 -#define MX7D_PAD_EPDC_DATA14__UART7_DTE_CTS 0x006C 0x02DC 0x0000 0x3 0x0 -#define MX7D_PAD_EPDC_DATA14__EIM_EB_B0 0x006C 0x02DC 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_DATA14__GPIO2_IO14 0x006C 0x02DC 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_DATA14__LCD_DATA14 0x006C 0x02DC 0x0670 0x6 0x0 -#define MX7D_PAD_EPDC_DATA14__LCD_DATA22 0x006C 0x02DC 0x0690 0x7 0x0 -#define MX7D_PAD_EPDC_DATA14__EPDC_GDSP 0x006C 0x02DC 0x0000 0x8 0x0 -#define MX7D_PAD_EPDC_DATA15__EPDC_DATA15 0x0070 0x02E0 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_DATA15__SIM2_PORT1_RST_B 0x0070 0x02E0 0x0000 0x1 0x0 -#define MX7D_PAD_EPDC_DATA15__QSPI_B_SS1_B 0x0070 0x02E0 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_DATA15__UART7_DCE_CTS 0x0070 0x02E0 0x0000 0x3 0x0 -#define MX7D_PAD_EPDC_DATA15__UART7_DTE_RTS 0x0070 0x02E0 0x0720 0x3 0x1 -#define MX7D_PAD_EPDC_DATA15__EIM_CS1_B 0x0070 0x02E0 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_DATA15__GPIO2_IO15 0x0070 0x02E0 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_DATA15__LCD_DATA15 0x0070 0x02E0 0x0674 0x6 0x0 -#define MX7D_PAD_EPDC_DATA15__LCD_WR_RWN 0x0070 0x02E0 0x0000 0x7 0x0 -#define MX7D_PAD_EPDC_DATA15__EPDC_PWR_COM 0x0070 0x02E0 0x0000 0x8 0x0 -#define MX7D_PAD_EPDC_SDCLK__EPDC_SDCLK 0x0074 0x02E4 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_SDCLK__SIM2_PORT2_SVEN 0x0074 0x02E4 0x0000 0x1 0x0 -#define MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x0074 0x02E4 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_SDCLK__KPP_ROW4 0x0074 0x02E4 0x0624 0x3 0x0 -#define MX7D_PAD_EPDC_SDCLK__EIM_AD10 0x0074 0x02E4 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_SDCLK__GPIO2_IO16 0x0074 0x02E4 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_SDCLK__LCD_CLK 0x0074 0x02E4 0x0000 0x6 0x0 -#define MX7D_PAD_EPDC_SDCLK__LCD_DATA20 0x0074 0x02E4 0x0688 0x7 0x0 -#define MX7D_PAD_EPDC_SDLE__EPDC_SDLE 0x0078 0x02E8 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_SDLE__SIM2_PORT2_PD 0x0078 0x02E8 0x0000 0x1 0x0 -#define MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x0078 0x02E8 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_SDLE__KPP_COL4 0x0078 0x02E8 0x0604 0x3 0x0 -#define MX7D_PAD_EPDC_SDLE__EIM_AD11 0x0078 0x02E8 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_SDLE__GPIO2_IO17 0x0078 0x02E8 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_SDLE__LCD_DATA16 0x0078 0x02E8 0x0678 0x6 0x0 -#define MX7D_PAD_EPDC_SDLE__LCD_DATA8 0x0078 0x02E8 0x0658 0x7 0x1 -#define MX7D_PAD_EPDC_SDOE__EPDC_SDOE 0x007C 0x02EC 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_SDOE__FLEXTIMER1_CH0 0x007C 0x02EC 0x0584 0x1 0x0 -#define MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x007C 0x02EC 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_SDOE__KPP_COL5 0x007C 0x02EC 0x0608 0x3 0x1 -#define MX7D_PAD_EPDC_SDOE__EIM_AD12 0x007C 0x02EC 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_SDOE__GPIO2_IO18 0x007C 0x02EC 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_SDOE__LCD_DATA17 0x007C 0x02EC 0x067C 0x6 0x0 -#define MX7D_PAD_EPDC_SDOE__LCD_DATA23 0x007C 0x02EC 0x0694 0x7 0x0 -#define MX7D_PAD_EPDC_SDSHR__EPDC_SDSHR 0x0080 0x02F0 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_SDSHR__FLEXTIMER1_CH1 0x0080 0x02F0 0x0588 0x1 0x0 -#define MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x0080 0x02F0 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_SDSHR__KPP_ROW5 0x0080 0x02F0 0x0628 0x3 0x1 -#define MX7D_PAD_EPDC_SDSHR__EIM_AD13 0x0080 0x02F0 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_SDSHR__GPIO2_IO19 0x0080 0x02F0 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_SDSHR__LCD_DATA18 0x0080 0x02F0 0x0680 0x6 0x0 -#define MX7D_PAD_EPDC_SDSHR__LCD_DATA10 0x0080 0x02F0 0x0660 0x7 0x1 -#define MX7D_PAD_EPDC_SDCE0__EPDC_SDCE0 0x0084 0x02F4 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_SDCE0__FLEXTIMER1_CH2 0x0084 0x02F4 0x058C 0x1 0x0 -#define MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x0084 0x02F4 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_SDCE0__EIM_AD14 0x0084 0x02F4 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_SDCE0__GPIO2_IO20 0x0084 0x02F4 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_SDCE0__LCD_DATA19 0x0084 0x02F4 0x0684 0x6 0x0 -#define MX7D_PAD_EPDC_SDCE0__LCD_DATA5 0x0084 0x02F4 0x064C 0x7 0x1 -#define MX7D_PAD_EPDC_SDCE1__EPDC_SDCE1 0x0088 0x02F8 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_SDCE1__FLEXTIMER1_CH3 0x0088 0x02F8 0x0590 0x1 0x0 -#define MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x0088 0x02F8 0x0578 0x2 0x0 -#define MX7D_PAD_EPDC_SDCE1__ENET2_RX_ER 0x0088 0x02F8 0x0000 0x3 0x0 -#define MX7D_PAD_EPDC_SDCE1__EIM_AD15 0x0088 0x02F8 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_SDCE1__GPIO2_IO21 0x0088 0x02F8 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_SDCE1__LCD_DATA20 0x0088 0x02F8 0x0688 0x6 0x1 -#define MX7D_PAD_EPDC_SDCE1__LCD_DATA4 0x0088 0x02F8 0x0648 0x7 0x1 -#define MX7D_PAD_EPDC_SDCE2__EPDC_SDCE2 0x008C 0x02FC 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_SDCE2__SIM2_PORT1_SVEN 0x008C 0x02FC 0x0000 0x1 0x0 -#define MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x008C 0x02FC 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_SDCE2__KPP_COL6 0x008C 0x02FC 0x060C 0x3 0x1 -#define MX7D_PAD_EPDC_SDCE2__EIM_ADDR16 0x008C 0x02FC 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_SDCE2__GPIO2_IO22 0x008C 0x02FC 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_SDCE2__LCD_DATA21 0x008C 0x02FC 0x068C 0x6 0x1 -#define MX7D_PAD_EPDC_SDCE2__LCD_DATA3 0x008C 0x02FC 0x0644 0x7 0x1 -#define MX7D_PAD_EPDC_SDCE3__EPDC_SDCE3 0x0090 0x0300 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_SDCE3__SIM2_PORT1_PD 0x0090 0x0300 0x06E8 0x1 0x0 -#define MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x0090 0x0300 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_SDCE3__KPP_ROW6 0x0090 0x0300 0x062C 0x3 0x1 -#define MX7D_PAD_EPDC_SDCE3__EIM_ADDR17 0x0090 0x0300 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 0x0090 0x0300 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_SDCE3__LCD_DATA22 0x0090 0x0300 0x0690 0x6 0x1 -#define MX7D_PAD_EPDC_SDCE3__LCD_DATA2 0x0090 0x0300 0x0640 0x7 0x1 -#define MX7D_PAD_EPDC_GDCLK__EPDC_GDCLK 0x0094 0x0304 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_GDCLK__FLEXTIMER2_CH0 0x0094 0x0304 0x05AC 0x1 0x0 -#define MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x0094 0x0304 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_GDCLK__KPP_COL7 0x0094 0x0304 0x0610 0x3 0x0 -#define MX7D_PAD_EPDC_GDCLK__EIM_ADDR18 0x0094 0x0304 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_GDCLK__GPIO2_IO24 0x0094 0x0304 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_GDCLK__LCD_DATA23 0x0094 0x0304 0x0694 0x6 0x1 -#define MX7D_PAD_EPDC_GDCLK__LCD_DATA16 0x0094 0x0304 0x0678 0x7 0x1 -#define MX7D_PAD_EPDC_GDOE__EPDC_GDOE 0x0098 0x0308 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_GDOE__FLEXTIMER2_CH1 0x0098 0x0308 0x05B0 0x1 0x0 -#define MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x0098 0x0308 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_GDOE__KPP_ROW7 0x0098 0x0308 0x0630 0x3 0x0 -#define MX7D_PAD_EPDC_GDOE__EIM_ADDR19 0x0098 0x0308 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_GDOE__GPIO2_IO25 0x0098 0x0308 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_GDOE__LCD_WR_RWN 0x0098 0x0308 0x0000 0x6 0x0 -#define MX7D_PAD_EPDC_GDOE__LCD_DATA18 0x0098 0x0308 0x0680 0x7 0x1 -#define MX7D_PAD_EPDC_GDRL__EPDC_GDRL 0x009C 0x030C 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_GDRL__FLEXTIMER2_CH2 0x009C 0x030C 0x05B4 0x1 0x0 -#define MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x009C 0x030C 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_GDRL__EIM_ADDR20 0x009C 0x030C 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_GDRL__GPIO2_IO26 0x009C 0x030C 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_GDRL__LCD_RD_E 0x009C 0x030C 0x0000 0x6 0x0 -#define MX7D_PAD_EPDC_GDRL__LCD_DATA19 0x009C 0x030C 0x0684 0x7 0x1 -#define MX7D_PAD_EPDC_GDSP__EPDC_GDSP 0x00A0 0x0310 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_GDSP__FLEXTIMER2_CH3 0x00A0 0x0310 0x05B8 0x1 0x0 -#define MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x00A0 0x0310 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_GDSP__ENET2_TX_ER 0x00A0 0x0310 0x0000 0x3 0x0 -#define MX7D_PAD_EPDC_GDSP__EIM_ADDR21 0x00A0 0x0310 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_GDSP__GPIO2_IO27 0x00A0 0x0310 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_GDSP__LCD_BUSY 0x00A0 0x0310 0x0634 0x6 0x1 -#define MX7D_PAD_EPDC_GDSP__LCD_DATA17 0x00A0 0x0310 0x067C 0x7 0x1 -#define MX7D_PAD_EPDC_BDR0__EPDC_BDR0 0x00A4 0x0314 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_BDR0__ENET2_TX_CLK 0x00A4 0x0314 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_BDR0__CCM_ENET_REF_CLK2 0x00A4 0x0314 0x0570 0x3 0x1 -#define MX7D_PAD_EPDC_BDR0__EIM_ADDR22 0x00A4 0x0314 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x00A4 0x0314 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_BDR0__LCD_CS 0x00A4 0x0314 0x0000 0x6 0x0 -#define MX7D_PAD_EPDC_BDR0__LCD_DATA7 0x00A4 0x0314 0x0654 0x7 0x1 -#define MX7D_PAD_EPDC_BDR1__EPDC_BDR1 0x00A8 0x0318 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_BDR1__EPDC_SDCLKN 0x00A8 0x0318 0x0000 0x1 0x0 -#define MX7D_PAD_EPDC_BDR1__ENET2_RX_CLK 0x00A8 0x0318 0x0578 0x2 0x1 -#define MX7D_PAD_EPDC_BDR1__EIM_AD8 0x00A8 0x0318 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x00A8 0x0318 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_BDR1__LCD_ENABLE 0x00A8 0x0318 0x0000 0x6 0x0 -#define MX7D_PAD_EPDC_BDR1__LCD_DATA6 0x00A8 0x0318 0x0650 0x7 0x1 -#define MX7D_PAD_EPDC_PWR_COM__EPDC_PWR_COM 0x00AC 0x031C 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_PWR_COM__FLEXTIMER2_PHA 0x00AC 0x031C 0x05CC 0x1 0x0 -#define MX7D_PAD_EPDC_PWR_COM__ENET2_CRS 0x00AC 0x031C 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_PWR_COM__EIM_AD9 0x00AC 0x031C 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x00AC 0x031C 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_PWR_COM__LCD_HSYNC 0x00AC 0x031C 0x0000 0x6 0x0 -#define MX7D_PAD_EPDC_PWR_COM__LCD_DATA11 0x00AC 0x031C 0x0664 0x7 0x1 -#define MX7D_PAD_EPDC_PWR_STAT__EPDC_PWR_STAT 0x00B0 0x0320 0x0580 0x0 0x0 -#define MX7D_PAD_EPDC_PWR_STAT__FLEXTIMER2_PHB 0x00B0 0x0320 0x05D0 0x1 0x0 -#define MX7D_PAD_EPDC_PWR_STAT__ENET2_COL 0x00B0 0x0320 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_PWR_STAT__EIM_EB_B1 0x00B0 0x0320 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 0x00B0 0x0320 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_PWR_STAT__LCD_VSYNC 0x00B0 0x0320 0x0698 0x6 0x1 -#define MX7D_PAD_EPDC_PWR_STAT__LCD_DATA12 0x00B0 0x0320 0x0668 0x7 0x1 -#define MX7D_PAD_LCD_CLK__LCD_CLK 0x00B4 0x0324 0x0000 0x0 0x0 -#define MX7D_PAD_LCD_CLK__ECSPI4_MISO 0x00B4 0x0324 0x0558 0x1 0x0 -#define MX7D_PAD_LCD_CLK__ENET1_1588_EVENT2_IN 0x00B4 0x0324 0x0000 0x2 0x0 -#define MX7D_PAD_LCD_CLK__CSI_DATA16 0x00B4 0x0324 0x0000 0x3 0x0 -#define MX7D_PAD_LCD_CLK__UART2_DCE_RX 0x00B4 0x0324 0x06FC 0x4 0x0 -#define MX7D_PAD_LCD_CLK__UART2_DTE_TX 0x00B4 0x0324 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_CLK__GPIO3_IO0 0x00B4 0x0324 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x00B8 0x0328 0x0000 0x0 0x0 -#define MX7D_PAD_LCD_ENABLE__ECSPI4_MOSI 0x00B8 0x0328 0x055C 0x1 0x0 -#define MX7D_PAD_LCD_ENABLE__ENET1_1588_EVENT3_IN 0x00B8 0x0328 0x0000 0x2 0x0 -#define MX7D_PAD_LCD_ENABLE__CSI_DATA17 0x00B8 0x0328 0x0000 0x3 0x0 -#define MX7D_PAD_LCD_ENABLE__UART2_DCE_TX 0x00B8 0x0328 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_ENABLE__UART2_DTE_RX 0x00B8 0x0328 0x06FC 0x4 0x1 -#define MX7D_PAD_LCD_ENABLE__GPIO3_IO1 0x00B8 0x0328 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x00BC 0x032C 0x0000 0x0 0x0 -#define MX7D_PAD_LCD_HSYNC__ECSPI4_SCLK 0x00BC 0x032C 0x0554 0x1 0x0 -#define MX7D_PAD_LCD_HSYNC__ENET2_1588_EVENT2_IN 0x00BC 0x032C 0x0000 0x2 0x0 -#define MX7D_PAD_LCD_HSYNC__CSI_DATA18 0x00BC 0x032C 0x0000 0x3 0x0 -#define MX7D_PAD_LCD_HSYNC__UART2_DCE_RTS 0x00BC 0x032C 0x06F8 0x4 0x0 -#define MX7D_PAD_LCD_HSYNC__UART2_DTE_CTS 0x00BC 0x032C 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_HSYNC__GPIO3_IO2 0x00BC 0x032C 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x00C0 0x0330 0x0698 0x0 0x2 -#define MX7D_PAD_LCD_VSYNC__ECSPI4_SS0 0x00C0 0x0330 0x0560 0x1 0x0 -#define MX7D_PAD_LCD_VSYNC__ENET2_1588_EVENT3_IN 0x00C0 0x0330 0x0000 0x2 0x0 -#define MX7D_PAD_LCD_VSYNC__CSI_DATA19 0x00C0 0x0330 0x0000 0x3 0x0 -#define MX7D_PAD_LCD_VSYNC__UART2_DCE_CTS 0x00C0 0x0330 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_VSYNC__UART2_DTE_RTS 0x00C0 0x0330 0x06F8 0x4 0x1 -#define MX7D_PAD_LCD_VSYNC__GPIO3_IO3 0x00C0 0x0330 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_RESET__LCD_RESET 0x00C4 0x0334 0x0000 0x0 0x0 -#define MX7D_PAD_LCD_RESET__GPT1_COMPARE1 0x00C4 0x0334 0x0000 0x1 0x0 -#define MX7D_PAD_LCD_RESET__ARM_PLATFORM_EVENTI 0x00C4 0x0334 0x0000 0x2 0x0 -#define MX7D_PAD_LCD_RESET__CSI_FIELD 0x00C4 0x0334 0x0000 0x3 0x0 -#define MX7D_PAD_LCD_RESET__EIM_DTACK_B 0x00C4 0x0334 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_RESET__GPIO3_IO4 0x00C4 0x0334 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA00__LCD_DATA0 0x00C8 0x0338 0x0638 0x0 0x2 -#define MX7D_PAD_LCD_DATA00__GPT1_COMPARE2 0x00C8 0x0338 0x0000 0x1 0x0 -#define MX7D_PAD_LCD_DATA00__CSI_DATA20 0x00C8 0x0338 0x0000 0x3 0x0 -#define MX7D_PAD_LCD_DATA00__EIM_DATA0 0x00C8 0x0338 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_DATA00__GPIO3_IO5 0x00C8 0x0338 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA00__SRC_BOOT_CFG0 0x00C8 0x0338 0x0000 0x6 0x0 -#define MX7D_PAD_LCD_DATA01__LCD_DATA1 0x00CC 0x033C 0x063C 0x0 0x2 -#define MX7D_PAD_LCD_DATA01__GPT1_COMPARE3 0x00CC 0x033C 0x0000 0x1 0x0 -#define MX7D_PAD_LCD_DATA01__CSI_DATA21 0x00CC 0x033C 0x0000 0x3 0x0 -#define MX7D_PAD_LCD_DATA01__EIM_DATA1 0x00CC 0x033C 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_DATA01__GPIO3_IO6 0x00CC 0x033C 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA01__SRC_BOOT_CFG1 0x00CC 0x033C 0x0000 0x6 0x0 -#define MX7D_PAD_LCD_DATA02__LCD_DATA2 0x00D0 0x0340 0x0640 0x0 0x2 -#define MX7D_PAD_LCD_DATA02__GPT1_CLK 0x00D0 0x0340 0x0000 0x1 0x0 -#define MX7D_PAD_LCD_DATA02__CSI_DATA22 0x00D0 0x0340 0x0000 0x3 0x0 -#define MX7D_PAD_LCD_DATA02__EIM_DATA2 0x00D0 0x0340 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_DATA02__GPIO3_IO7 0x00D0 0x0340 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA02__SRC_BOOT_CFG2 0x00D0 0x0340 0x0000 0x6 0x0 -#define MX7D_PAD_LCD_DATA03__LCD_DATA3 0x00D4 0x0344 0x0644 0x0 0x2 -#define MX7D_PAD_LCD_DATA03__GPT1_CAPTURE1 0x00D4 0x0344 0x0000 0x1 0x0 -#define MX7D_PAD_LCD_DATA03__CSI_DATA23 0x00D4 0x0344 0x0000 0x3 0x0 -#define MX7D_PAD_LCD_DATA03__EIM_DATA3 0x00D4 0x0344 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_DATA03__GPIO3_IO8 0x00D4 0x0344 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA03__SRC_BOOT_CFG3 0x00D4 0x0344 0x0000 0x6 0x0 -#define MX7D_PAD_LCD_DATA04__LCD_DATA4 0x00D8 0x0348 0x0648 0x0 0x2 -#define MX7D_PAD_LCD_DATA04__GPT1_CAPTURE2 0x00D8 0x0348 0x0000 0x1 0x0 -#define MX7D_PAD_LCD_DATA04__CSI_VSYNC 0x00D8 0x0348 0x0520 0x3 0x0 -#define MX7D_PAD_LCD_DATA04__EIM_DATA4 0x00D8 0x0348 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_DATA04__GPIO3_IO9 0x00D8 0x0348 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA04__SRC_BOOT_CFG4 0x00D8 0x0348 0x0000 0x6 0x0 -#define MX7D_PAD_LCD_DATA05__LCD_DATA5 0x00DC 0x034C 0x064C 0x0 0x2 -#define MX7D_PAD_LCD_DATA05__CSI_HSYNC 0x00DC 0x034C 0x0518 0x3 0x0 -#define MX7D_PAD_LCD_DATA05__EIM_DATA5 0x00DC 0x034C 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_DATA05__GPIO3_IO10 0x00DC 0x034C 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA05__SRC_BOOT_CFG5 0x00DC 0x034C 0x0000 0x6 0x0 -#define MX7D_PAD_LCD_DATA06__LCD_DATA6 0x00E0 0x0350 0x0650 0x0 0x2 -#define MX7D_PAD_LCD_DATA06__CSI_PIXCLK 0x00E0 0x0350 0x051C 0x3 0x0 -#define MX7D_PAD_LCD_DATA06__EIM_DATA6 0x00E0 0x0350 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_DATA06__GPIO3_IO11 0x00E0 0x0350 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA06__SRC_BOOT_CFG6 0x00E0 0x0350 0x0000 0x6 0x0 -#define MX7D_PAD_LCD_DATA07__LCD_DATA7 0x00E4 0x0354 0x0654 0x0 0x2 -#define MX7D_PAD_LCD_DATA07__CSI_MCLK 0x00E4 0x0354 0x0000 0x3 0x0 -#define MX7D_PAD_LCD_DATA07__EIM_DATA7 0x00E4 0x0354 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_DATA07__GPIO3_IO12 0x00E4 0x0354 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA07__SRC_BOOT_CFG7 0x00E4 0x0354 0x0000 0x6 0x0 -#define MX7D_PAD_LCD_DATA08__LCD_DATA8 0x00E8 0x0358 0x0658 0x0 0x2 -#define MX7D_PAD_LCD_DATA08__CSI_DATA9 0x00E8 0x0358 0x0514 0x3 0x0 -#define MX7D_PAD_LCD_DATA08__EIM_DATA8 0x00E8 0x0358 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_DATA08__GPIO3_IO13 0x00E8 0x0358 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA08__SRC_BOOT_CFG8 0x00E8 0x0358 0x0000 0x6 0x0 -#define MX7D_PAD_LCD_DATA09__LCD_DATA9 0x00EC 0x035C 0x065C 0x0 0x2 -#define MX7D_PAD_LCD_DATA09__CSI_DATA8 0x00EC 0x035C 0x0510 0x3 0x0 -#define MX7D_PAD_LCD_DATA09__EIM_DATA9 0x00EC 0x035C 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_DATA09__GPIO3_IO14 0x00EC 0x035C 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA09__SRC_BOOT_CFG9 0x00EC 0x035C 0x0000 0x6 0x0 -#define MX7D_PAD_LCD_DATA10__LCD_DATA10 0x00F0 0x0360 0x0660 0x0 0x2 -#define MX7D_PAD_LCD_DATA10__CSI_DATA7 0x00F0 0x0360 0x050C 0x3 0x0 -#define MX7D_PAD_LCD_DATA10__EIM_DATA10 0x00F0 0x0360 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_DATA10__GPIO3_IO15 0x00F0 0x0360 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA10__SRC_BOOT_CFG10 0x00F0 0x0360 0x0000 0x6 0x0 -#define MX7D_PAD_LCD_DATA11__LCD_DATA11 0x00F4 0x0364 0x0664 0x0 0x2 -#define MX7D_PAD_LCD_DATA11__CSI_DATA6 0x00F4 0x0364 0x0508 0x3 0x0 -#define MX7D_PAD_LCD_DATA11__EIM_DATA11 0x00F4 0x0364 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_DATA11__GPIO3_IO16 0x00F4 0x0364 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA11__SRC_BOOT_CFG11 0x00F4 0x0364 0x0000 0x6 0x0 -#define MX7D_PAD_LCD_DATA12__LCD_DATA12 0x00F8 0x0368 0x0668 0x0 0x2 -#define MX7D_PAD_LCD_DATA12__CSI_DATA5 0x00F8 0x0368 0x0504 0x3 0x0 -#define MX7D_PAD_LCD_DATA12__EIM_DATA12 0x00F8 0x0368 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_DATA12__GPIO3_IO17 0x00F8 0x0368 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA12__SRC_BOOT_CFG12 0x00F8 0x0368 0x0000 0x6 0x0 -#define MX7D_PAD_LCD_DATA13__LCD_DATA13 0x00FC 0x036C 0x066C 0x0 0x1 -#define MX7D_PAD_LCD_DATA13__CSI_DATA4 0x00FC 0x036C 0x0500 0x3 0x0 -#define MX7D_PAD_LCD_DATA13__EIM_DATA13 0x00FC 0x036C 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_DATA13__GPIO3_IO18 0x00FC 0x036C 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA13__SRC_BOOT_CFG13 0x00FC 0x036C 0x0000 0x6 0x0 -#define MX7D_PAD_LCD_DATA14__LCD_DATA14 0x0100 0x0370 0x0670 0x0 0x1 -#define MX7D_PAD_LCD_DATA14__CSI_DATA3 0x0100 0x0370 0x04FC 0x3 0x0 -#define MX7D_PAD_LCD_DATA14__EIM_DATA14 0x0100 0x0370 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_DATA14__GPIO3_IO19 0x0100 0x0370 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA14__SRC_BOOT_CFG14 0x0100 0x0370 0x0000 0x6 0x0 -#define MX7D_PAD_LCD_DATA15__LCD_DATA15 0x0104 0x0374 0x0674 0x0 0x1 -#define MX7D_PAD_LCD_DATA15__CSI_DATA2 0x0104 0x0374 0x04F8 0x3 0x0 -#define MX7D_PAD_LCD_DATA15__EIM_DATA15 0x0104 0x0374 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_DATA15__GPIO3_IO20 0x0104 0x0374 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA15__SRC_BOOT_CFG15 0x0104 0x0374 0x0000 0x6 0x0 -#define MX7D_PAD_LCD_DATA16__LCD_DATA16 0x0108 0x0378 0x0678 0x0 0x2 -#define MX7D_PAD_LCD_DATA16__FLEXTIMER1_CH4 0x0108 0x0378 0x0594 0x1 0x0 -#define MX7D_PAD_LCD_DATA16__CSI_DATA1 0x0108 0x0378 0x0000 0x3 0x0 -#define MX7D_PAD_LCD_DATA16__EIM_CRE 0x0108 0x0378 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_DATA16__GPIO3_IO21 0x0108 0x0378 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA16__SRC_BOOT_CFG16 0x0108 0x0378 0x0000 0x6 0x0 -#define MX7D_PAD_LCD_DATA17__LCD_DATA17 0x010C 0x037C 0x067C 0x0 0x2 -#define MX7D_PAD_LCD_DATA17__FLEXTIMER1_CH5 0x010C 0x037C 0x0598 0x1 0x0 -#define MX7D_PAD_LCD_DATA17__CSI_DATA0 0x010C 0x037C 0x0000 0x3 0x0 -#define MX7D_PAD_LCD_DATA17__EIM_ACLK_FREERUN 0x010C 0x037C 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_DATA17__GPIO3_IO22 0x010C 0x037C 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA17__SRC_BOOT_CFG17 0x010C 0x037C 0x0000 0x6 0x0 -#define MX7D_PAD_LCD_DATA18__LCD_DATA18 0x0110 0x0380 0x0680 0x0 0x2 -#define MX7D_PAD_LCD_DATA18__FLEXTIMER1_CH6 0x0110 0x0380 0x059C 0x1 0x0 -#define MX7D_PAD_LCD_DATA18__ARM_PLATFORM_EVENTO 0x0110 0x0380 0x0000 0x2 0x0 -#define MX7D_PAD_LCD_DATA18__CSI_DATA15 0x0110 0x0380 0x0000 0x3 0x0 -#define MX7D_PAD_LCD_DATA18__EIM_CS2_B 0x0110 0x0380 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_DATA18__GPIO3_IO23 0x0110 0x0380 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA18__SRC_BOOT_CFG18 0x0110 0x0380 0x0000 0x6 0x0 -#define MX7D_PAD_LCD_DATA19__EIM_CS3_B 0x0114 0x0384 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_DATA19__GPIO3_IO24 0x0114 0x0384 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA19__SRC_BOOT_CFG19 0x0114 0x0384 0x0000 0x6 0x0 -#define MX7D_PAD_LCD_DATA19__LCD_DATA19 0x0114 0x0384 0x0684 0x0 0x2 -#define MX7D_PAD_LCD_DATA19__FLEXTIMER1_CH7 0x0114 0x0384 0x05A0 0x1 0x0 -#define MX7D_PAD_LCD_DATA19__CSI_DATA14 0x0114 0x0384 0x0000 0x3 0x0 -#define MX7D_PAD_LCD_DATA20__EIM_ADDR23 0x0118 0x0388 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_DATA20__GPIO3_IO25 0x0118 0x0388 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA20__I2C3_SCL 0x0118 0x0388 0x05E4 0x6 0x1 -#define MX7D_PAD_LCD_DATA20__LCD_DATA20 0x0118 0x0388 0x0688 0x0 0x2 -#define MX7D_PAD_LCD_DATA20__FLEXTIMER2_CH4 0x0118 0x0388 0x05BC 0x1 0x0 -#define MX7D_PAD_LCD_DATA20__ENET1_1588_EVENT2_OUT 0x0118 0x0388 0x0000 0x2 0x0 -#define MX7D_PAD_LCD_DATA20__CSI_DATA13 0x0118 0x0388 0x0000 0x3 0x0 -#define MX7D_PAD_LCD_DATA21__LCD_DATA21 0x011C 0x038C 0x068C 0x0 0x2 -#define MX7D_PAD_LCD_DATA21__FLEXTIMER2_CH5 0x011C 0x038C 0x05C0 0x1 0x0 -#define MX7D_PAD_LCD_DATA21__ENET1_1588_EVENT3_OUT 0x011C 0x038C 0x0000 0x2 0x0 -#define MX7D_PAD_LCD_DATA21__CSI_DATA12 0x011C 0x038C 0x0000 0x3 0x0 -#define MX7D_PAD_LCD_DATA21__EIM_ADDR24 0x011C 0x038C 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_DATA21__GPIO3_IO26 0x011C 0x038C 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA21__I2C3_SDA 0x011C 0x038C 0x05E8 0x6 0x1 -#define MX7D_PAD_LCD_DATA22__LCD_DATA22 0x0120 0x0390 0x0690 0x0 0x2 -#define MX7D_PAD_LCD_DATA22__FLEXTIMER2_CH6 0x0120 0x0390 0x05C4 0x1 0x0 -#define MX7D_PAD_LCD_DATA22__ENET2_1588_EVENT2_OUT 0x0120 0x0390 0x0000 0x2 0x0 -#define MX7D_PAD_LCD_DATA22__CSI_DATA11 0x0120 0x0390 0x0000 0x3 0x0 -#define MX7D_PAD_LCD_DATA22__EIM_ADDR25 0x0120 0x0390 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_DATA22__GPIO3_IO27 0x0120 0x0390 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA22__I2C4_SCL 0x0120 0x0390 0x05EC 0x6 0x1 -#define MX7D_PAD_LCD_DATA23__LCD_DATA23 0x0124 0x0394 0x0694 0x0 0x2 -#define MX7D_PAD_LCD_DATA23__FLEXTIMER2_CH7 0x0124 0x0394 0x05C8 0x1 0x0 -#define MX7D_PAD_LCD_DATA23__ENET2_1588_EVENT3_OUT 0x0124 0x0394 0x0000 0x2 0x0 -#define MX7D_PAD_LCD_DATA23__CSI_DATA10 0x0124 0x0394 0x0000 0x3 0x0 -#define MX7D_PAD_LCD_DATA23__EIM_ADDR26 0x0124 0x0394 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_DATA23__GPIO3_IO28 0x0124 0x0394 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA23__I2C4_SDA 0x0124 0x0394 0x05F0 0x6 0x1 -#define MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x0128 0x0398 0x06F4 0x0 0x0 -#define MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX 0x0128 0x0398 0x0000 0x0 0x0 -#define MX7D_PAD_UART1_RX_DATA__I2C1_SCL 0x0128 0x0398 0x05D4 0x1 0x0 -#define MX7D_PAD_UART1_RX_DATA__CCM_PMIC_READY 0x0128 0x0398 0x0000 0x2 0x0 -#define MX7D_PAD_UART1_RX_DATA__ECSPI1_SS1 0x0128 0x0398 0x0000 0x3 0x0 -#define MX7D_PAD_UART1_RX_DATA__ENET2_1588_EVENT0_IN 0x0128 0x0398 0x0000 0x4 0x0 -#define MX7D_PAD_UART1_RX_DATA__GPIO4_IO0 0x0128 0x0398 0x0000 0x5 0x0 -#define MX7D_PAD_UART1_RX_DATA__ENET1_MDIO 0x0128 0x0398 0x0000 0x6 0x0 -#define MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x012C 0x039C 0x0000 0x0 0x0 -#define MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX 0x012C 0x039C 0x06F4 0x0 0x1 -#define MX7D_PAD_UART1_TX_DATA__I2C1_SDA 0x012C 0x039C 0x05D8 0x1 0x0 -#define MX7D_PAD_UART1_TX_DATA__SAI3_MCLK 0x012C 0x039C 0x0000 0x2 0x0 -#define MX7D_PAD_UART1_TX_DATA__ECSPI1_SS2 0x012C 0x039C 0x0000 0x3 0x0 -#define MX7D_PAD_UART1_TX_DATA__ENET2_1588_EVENT0_OUT 0x012C 0x039C 0x0000 0x4 0x0 -#define MX7D_PAD_UART1_TX_DATA__GPIO4_IO1 0x012C 0x039C 0x0000 0x5 0x0 -#define MX7D_PAD_UART1_TX_DATA__ENET1_MDC 0x012C 0x039C 0x0000 0x6 0x0 -#define MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX 0x0130 0x03A0 0x06FC 0x0 0x2 -#define MX7D_PAD_UART2_RX_DATA__UART2_DTE_TX 0x0130 0x03A0 0x0000 0x0 0x0 -#define MX7D_PAD_UART2_RX_DATA__I2C2_SCL 0x0130 0x03A0 0x05DC 0x1 0x0 -#define MX7D_PAD_UART2_RX_DATA__SAI3_RX_BCLK 0x0130 0x03A0 0x06C4 0x2 0x0 -#define MX7D_PAD_UART2_RX_DATA__ECSPI1_SS3 0x0130 0x03A0 0x0000 0x3 0x0 -#define MX7D_PAD_UART2_RX_DATA__ENET2_1588_EVENT1_IN 0x0130 0x03A0 0x0000 0x4 0x0 -#define MX7D_PAD_UART2_RX_DATA__GPIO4_IO2 0x0130 0x03A0 0x0000 0x5 0x0 -#define MX7D_PAD_UART2_RX_DATA__ENET2_MDIO 0x0130 0x03A0 0x0000 0x6 0x0 -#define MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX 0x0134 0x03A4 0x0000 0x0 0x0 -#define MX7D_PAD_UART2_TX_DATA__UART2_DTE_RX 0x0134 0x03A4 0x06FC 0x0 0x3 -#define MX7D_PAD_UART2_TX_DATA__I2C2_SDA 0x0134 0x03A4 0x05E0 0x1 0x0 -#define MX7D_PAD_UART2_TX_DATA__SAI3_RX_DATA0 0x0134 0x03A4 0x06C8 0x2 0x0 -#define MX7D_PAD_UART2_TX_DATA__ECSPI1_RDY 0x0134 0x03A4 0x0000 0x3 0x0 -#define MX7D_PAD_UART2_TX_DATA__ENET2_1588_EVENT1_OUT 0x0134 0x03A4 0x0000 0x4 0x0 -#define MX7D_PAD_UART2_TX_DATA__GPIO4_IO3 0x0134 0x03A4 0x0000 0x5 0x0 -#define MX7D_PAD_UART2_TX_DATA__ENET2_MDC 0x0134 0x03A4 0x0000 0x6 0x0 -#define MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x0138 0x03A8 0x0704 0x0 0x2 -#define MX7D_PAD_UART3_RX_DATA__UART3_DTE_TX 0x0138 0x03A8 0x0000 0x0 0x0 -#define MX7D_PAD_UART3_RX_DATA__USB_OTG1_OC 0x0138 0x03A8 0x072C 0x1 0x0 -#define MX7D_PAD_UART3_RX_DATA__SAI3_RX_SYNC 0x0138 0x03A8 0x06CC 0x2 0x0 -#define MX7D_PAD_UART3_RX_DATA__ECSPI1_MISO 0x0138 0x03A8 0x0528 0x3 0x0 -#define MX7D_PAD_UART3_RX_DATA__ENET1_1588_EVENT0_IN 0x0138 0x03A8 0x0000 0x4 0x0 -#define MX7D_PAD_UART3_RX_DATA__GPIO4_IO4 0x0138 0x03A8 0x0000 0x5 0x0 -#define MX7D_PAD_UART3_RX_DATA__SD1_LCTL 0x0138 0x03A8 0x0000 0x6 0x0 -#define MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x013C 0x03AC 0x0000 0x0 0x0 -#define MX7D_PAD_UART3_TX_DATA__UART3_DTE_RX 0x013C 0x03AC 0x0704 0x0 0x3 -#define MX7D_PAD_UART3_TX_DATA__USB_OTG1_PWR 0x013C 0x03AC 0x0000 0x1 0x0 -#define MX7D_PAD_UART3_TX_DATA__SAI3_TX_BCLK 0x013C 0x03AC 0x06D0 0x2 0x0 -#define MX7D_PAD_UART3_TX_DATA__ECSPI1_MOSI 0x013C 0x03AC 0x052C 0x3 0x0 -#define MX7D_PAD_UART3_TX_DATA__ENET1_1588_EVENT0_OUT 0x013C 0x03AC 0x0000 0x4 0x0 -#define MX7D_PAD_UART3_TX_DATA__GPIO4_IO5 0x013C 0x03AC 0x0000 0x5 0x0 -#define MX7D_PAD_UART3_TX_DATA__SD2_LCTL 0x013C 0x03AC 0x0000 0x6 0x0 -#define MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS 0x0140 0x03B0 0x0700 0x0 0x2 -#define MX7D_PAD_UART3_RTS_B__UART3_DTE_CTS 0x0140 0x03B0 0x0000 0x0 0x0 -#define MX7D_PAD_UART3_RTS_B__USB_OTG2_OC 0x0140 0x03B0 0x0728 0x1 0x0 -#define MX7D_PAD_UART3_RTS_B__SAI3_TX_DATA0 0x0140 0x03B0 0x0000 0x2 0x0 -#define MX7D_PAD_UART3_RTS_B__ECSPI1_SCLK 0x0140 0x03B0 0x0000 0x3 0x0 -#define MX7D_PAD_UART3_RTS_B__ENET1_1588_EVENT1_IN 0x0140 0x03B0 0x0000 0x4 0x0 -#define MX7D_PAD_UART3_RTS_B__GPIO4_IO6 0x0140 0x03B0 0x0000 0x5 0x0 -#define MX7D_PAD_UART3_RTS_B__SD3_LCTL 0x0140 0x03B0 0x0000 0x6 0x0 -#define MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS 0x0144 0x03B4 0x0000 0x0 0x0 -#define MX7D_PAD_UART3_CTS_B__UART3_DTE_RTS 0x0144 0x03B4 0x0700 0x0 0x3 -#define MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR 0x0144 0x03B4 0x0000 0x1 0x0 -#define MX7D_PAD_UART3_CTS_B__SAI3_TX_SYNC 0x0144 0x03B4 0x06D4 0x2 0x0 -#define MX7D_PAD_UART3_CTS_B__ECSPI1_SS0 0x0144 0x03B4 0x0530 0x3 0x0 -#define MX7D_PAD_UART3_CTS_B__ENET1_1588_EVENT1_OUT 0x0144 0x03B4 0x0000 0x4 0x0 -#define MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x0144 0x03B4 0x0000 0x5 0x0 -#define MX7D_PAD_UART3_CTS_B__SD1_VSELECT 0x0144 0x03B4 0x0000 0x6 0x0 -#define MX7D_PAD_I2C1_SCL__I2C1_SCL 0x0148 0x03B8 0x05D4 0x0 0x1 -#define MX7D_PAD_I2C1_SCL__UART4_DCE_CTS 0x0148 0x03B8 0x0000 0x1 0x0 -#define MX7D_PAD_I2C1_SCL__UART4_DTE_RTS 0x0148 0x03B8 0x0708 0x1 0x0 -#define MX7D_PAD_I2C1_SCL__FLEXCAN1_RX 0x0148 0x03B8 0x04DC 0x2 0x1 -#define MX7D_PAD_I2C1_SCL__ECSPI3_MISO 0x0148 0x03B8 0x0548 0x3 0x0 -#define MX7D_PAD_I2C1_SCL__GPIO4_IO8 0x0148 0x03B8 0x0000 0x5 0x0 -#define MX7D_PAD_I2C1_SCL__SD2_VSELECT 0x0148 0x03B8 0x0000 0x6 0x0 -#define MX7D_PAD_I2C1_SDA__I2C1_SDA 0x014C 0x03BC 0x05D8 0x0 0x1 -#define MX7D_PAD_I2C1_SDA__UART4_DCE_RTS 0x014C 0x03BC 0x0708 0x1 0x1 -#define MX7D_PAD_I2C1_SDA__UART4_DTE_CTS 0x014C 0x03BC 0x0000 0x1 0x0 -#define MX7D_PAD_I2C1_SDA__FLEXCAN1_TX 0x014C 0x03BC 0x0000 0x2 0x0 -#define MX7D_PAD_I2C1_SDA__ECSPI3_MOSI 0x014C 0x03BC 0x054C 0x3 0x0 -#define MX7D_PAD_I2C1_SDA__CCM_ENET_REF_CLK1 0x014C 0x03BC 0x0564 0x4 0x1 -#define MX7D_PAD_I2C1_SDA__GPIO4_IO9 0x014C 0x03BC 0x0000 0x5 0x0 -#define MX7D_PAD_I2C1_SDA__SD3_VSELECT 0x014C 0x03BC 0x0000 0x6 0x0 -#define MX7D_PAD_I2C2_SCL__I2C2_SCL 0x0150 0x03C0 0x05DC 0x0 0x1 -#define MX7D_PAD_I2C2_SCL__UART4_DCE_RX 0x0150 0x03C0 0x070C 0x1 0x0 -#define MX7D_PAD_I2C2_SCL__UART4_DTE_TX 0x0150 0x03C0 0x0000 0x1 0x0 -#define MX7D_PAD_I2C2_SCL__WDOG3_WDOG_B 0x0150 0x03C0 0x0000 0x2 0x0 -#define MX7D_PAD_I2C2_SCL__ECSPI3_SCLK 0x0150 0x03C0 0x0544 0x3 0x0 -#define MX7D_PAD_I2C2_SCL__CCM_ENET_REF_CLK2 0x0150 0x03C0 0x0570 0x4 0x2 -#define MX7D_PAD_I2C2_SCL__GPIO4_IO10 0x0150 0x03C0 0x0000 0x5 0x0 -#define MX7D_PAD_I2C2_SCL__SD3_CD_B 0x0150 0x03C0 0x0738 0x6 0x1 -#define MX7D_PAD_I2C2_SDA__I2C2_SDA 0x0154 0x03C4 0x05E0 0x0 0x1 -#define MX7D_PAD_I2C2_SDA__UART4_DCE_TX 0x0154 0x03C4 0x0000 0x1 0x0 -#define MX7D_PAD_I2C2_SDA__UART4_DTE_RX 0x0154 0x03C4 0x070C 0x1 0x1 -#define MX7D_PAD_I2C2_SDA__WDOG3_WDOG_RST_B_DEB 0x0154 0x03C4 0x0000 0x2 0x0 -#define MX7D_PAD_I2C2_SDA__ECSPI3_SS0 0x0154 0x03C4 0x0550 0x3 0x0 -#define MX7D_PAD_I2C2_SDA__CCM_ENET_REF_CLK3 0x0154 0x03C4 0x0000 0x4 0x0 -#define MX7D_PAD_I2C2_SDA__GPIO4_IO11 0x0154 0x03C4 0x0000 0x5 0x0 -#define MX7D_PAD_I2C2_SDA__SD3_WP 0x0154 0x03C4 0x073C 0x6 0x1 -#define MX7D_PAD_I2C3_SCL__I2C3_SCL 0x0158 0x03C8 0x05E4 0x0 0x2 -#define MX7D_PAD_I2C3_SCL__UART5_DCE_CTS 0x0158 0x03C8 0x0000 0x1 0x0 -#define MX7D_PAD_I2C3_SCL__UART5_DTE_RTS 0x0158 0x03C8 0x0710 0x1 0x0 -#define MX7D_PAD_I2C3_SCL__FLEXCAN2_RX 0x0158 0x03C8 0x04E0 0x2 0x1 -#define MX7D_PAD_I2C3_SCL__CSI_VSYNC 0x0158 0x03C8 0x0520 0x3 0x1 -#define MX7D_PAD_I2C3_SCL__SDMA_EXT_EVENT0 0x0158 0x03C8 0x06D8 0x4 0x1 -#define MX7D_PAD_I2C3_SCL__GPIO4_IO12 0x0158 0x03C8 0x0000 0x5 0x0 -#define MX7D_PAD_I2C3_SCL__EPDC_BDR0 0x0158 0x03C8 0x0000 0x6 0x0 -#define MX7D_PAD_I2C3_SDA__I2C3_SDA 0x015C 0x03CC 0x05E8 0x0 0x2 -#define MX7D_PAD_I2C3_SDA__UART5_DCE_RTS 0x015C 0x03CC 0x0710 0x1 0x1 -#define MX7D_PAD_I2C3_SDA__UART5_DTE_CTS 0x015C 0x03CC 0x0000 0x1 0x0 -#define MX7D_PAD_I2C3_SDA__FLEXCAN2_TX 0x015C 0x03CC 0x0000 0x2 0x0 -#define MX7D_PAD_I2C3_SDA__CSI_HSYNC 0x015C 0x03CC 0x0518 0x3 0x1 -#define MX7D_PAD_I2C3_SDA__SDMA_EXT_EVENT1 0x015C 0x03CC 0x06DC 0x4 0x1 -#define MX7D_PAD_I2C3_SDA__GPIO4_IO13 0x015C 0x03CC 0x0000 0x5 0x0 -#define MX7D_PAD_I2C3_SDA__EPDC_BDR1 0x015C 0x03CC 0x0000 0x6 0x0 -#define MX7D_PAD_I2C4_SCL__I2C4_SCL 0x0160 0x03D0 0x05EC 0x0 0x2 -#define MX7D_PAD_I2C4_SCL__UART5_DCE_RX 0x0160 0x03D0 0x0714 0x1 0x0 -#define MX7D_PAD_I2C4_SCL__UART5_DTE_TX 0x0160 0x03D0 0x0000 0x1 0x0 -#define MX7D_PAD_I2C4_SCL__WDOG4_WDOG_B 0x0160 0x03D0 0x0000 0x2 0x0 -#define MX7D_PAD_I2C4_SCL__CSI_PIXCLK 0x0160 0x03D0 0x051C 0x3 0x1 -#define MX7D_PAD_I2C4_SCL__USB_OTG1_ID 0x0160 0x03D0 0x0734 0x4 0x1 -#define MX7D_PAD_I2C4_SCL__GPIO4_IO14 0x0160 0x03D0 0x0000 0x5 0x0 -#define MX7D_PAD_I2C4_SCL__EPDC_VCOM0 0x0160 0x03D0 0x0000 0x6 0x0 -#define MX7D_PAD_I2C4_SDA__I2C4_SDA 0x0164 0x03D4 0x05F0 0x0 0x2 -#define MX7D_PAD_I2C4_SDA__UART5_DCE_TX 0x0164 0x03D4 0x0000 0x1 0x0 -#define MX7D_PAD_I2C4_SDA__UART5_DTE_RX 0x0164 0x03D4 0x0714 0x1 0x1 -#define MX7D_PAD_I2C4_SDA__WDOG4_WDOG_RST_B_DEB 0x0164 0x03D4 0x0000 0x2 0x0 -#define MX7D_PAD_I2C4_SDA__CSI_MCLK 0x0164 0x03D4 0x0000 0x3 0x0 -#define MX7D_PAD_I2C4_SDA__USB_OTG2_ID 0x0164 0x03D4 0x0730 0x4 0x1 -#define MX7D_PAD_I2C4_SDA__GPIO4_IO15 0x0164 0x03D4 0x0000 0x5 0x0 -#define MX7D_PAD_I2C4_SDA__EPDC_VCOM1 0x0164 0x03D4 0x0000 0x6 0x0 -#define MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x0168 0x03D8 0x0524 0x0 0x1 -#define MX7D_PAD_ECSPI1_SCLK__UART6_DCE_RX 0x0168 0x03D8 0x071C 0x1 0x2 -#define MX7D_PAD_ECSPI1_SCLK__UART6_DTE_TX 0x0168 0x03D8 0x0000 0x1 0x0 -#define MX7D_PAD_ECSPI1_SCLK__SD2_DATA4 0x0168 0x03D8 0x0000 0x2 0x0 -#define MX7D_PAD_ECSPI1_SCLK__CSI_DATA2 0x0168 0x03D8 0x04F8 0x3 0x1 -#define MX7D_PAD_ECSPI1_SCLK__GPIO4_IO16 0x0168 0x03D8 0x0000 0x5 0x0 -#define MX7D_PAD_ECSPI1_SCLK__EPDC_PWR_COM 0x0168 0x03D8 0x0000 0x6 0x0 -#define MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x016C 0x03DC 0x052C 0x0 0x1 -#define MX7D_PAD_ECSPI1_MOSI__UART6_DCE_TX 0x016C 0x03DC 0x0000 0x1 0x0 -#define MX7D_PAD_ECSPI1_MOSI__UART6_DTE_RX 0x016C 0x03DC 0x071C 0x1 0x3 -#define MX7D_PAD_ECSPI1_MOSI__SD2_DATA5 0x016C 0x03DC 0x0000 0x2 0x0 -#define MX7D_PAD_ECSPI1_MOSI__CSI_DATA3 0x016C 0x03DC 0x04FC 0x3 0x1 -#define MX7D_PAD_ECSPI1_MOSI__GPIO4_IO17 0x016C 0x03DC 0x0000 0x5 0x0 -#define MX7D_PAD_ECSPI1_MOSI__EPDC_PWR_STAT 0x016C 0x03DC 0x0580 0x6 0x1 -#define MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO 0x0170 0x03E0 0x0528 0x0 0x1 -#define MX7D_PAD_ECSPI1_MISO__UART6_DCE_RTS 0x0170 0x03E0 0x0718 0x1 0x2 -#define MX7D_PAD_ECSPI1_MISO__UART6_DTE_CTS 0x0170 0x03E0 0x0000 0x1 0x0 -#define MX7D_PAD_ECSPI1_MISO__SD2_DATA6 0x0170 0x03E0 0x0000 0x2 0x0 -#define MX7D_PAD_ECSPI1_MISO__CSI_DATA4 0x0170 0x03E0 0x0500 0x3 0x1 -#define MX7D_PAD_ECSPI1_MISO__GPIO4_IO18 0x0170 0x03E0 0x0000 0x5 0x0 -#define MX7D_PAD_ECSPI1_MISO__EPDC_PWR_IRQ 0x0170 0x03E0 0x057C 0x6 0x0 -#define MX7D_PAD_ECSPI1_SS0__ECSPI1_SS0 0x0174 0x03E4 0x0530 0x0 0x1 -#define MX7D_PAD_ECSPI1_SS0__UART6_DCE_CTS 0x0174 0x03E4 0x0000 0x1 0x0 -#define MX7D_PAD_ECSPI1_SS0__UART6_DTE_RTS 0x0174 0x03E4 0x0718 0x1 0x3 -#define MX7D_PAD_ECSPI1_SS0__SD2_DATA7 0x0174 0x03E4 0x0000 0x2 0x0 -#define MX7D_PAD_ECSPI1_SS0__CSI_DATA5 0x0174 0x03E4 0x0504 0x3 0x1 -#define MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 0x0174 0x03E4 0x0000 0x5 0x0 -#define MX7D_PAD_ECSPI1_SS0__EPDC_PWR_CTRL3 0x0174 0x03E4 0x0000 0x6 0x0 -#define MX7D_PAD_ECSPI2_SCLK__ECSPI2_SCLK 0x0178 0x03E8 0x0534 0x0 0x0 -#define MX7D_PAD_ECSPI2_SCLK__UART7_DCE_RX 0x0178 0x03E8 0x0724 0x1 0x2 -#define MX7D_PAD_ECSPI2_SCLK__UART7_DTE_TX 0x0178 0x03E8 0x0000 0x1 0x0 -#define MX7D_PAD_ECSPI2_SCLK__SD1_DATA4 0x0178 0x03E8 0x0000 0x2 0x0 -#define MX7D_PAD_ECSPI2_SCLK__CSI_DATA6 0x0178 0x03E8 0x0508 0x3 0x1 -#define MX7D_PAD_ECSPI2_SCLK__LCD_DATA13 0x0178 0x03E8 0x066C 0x4 0x2 -#define MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20 0x0178 0x03E8 0x0000 0x5 0x0 -#define MX7D_PAD_ECSPI2_SCLK__EPDC_PWR_CTRL0 0x0178 0x03E8 0x0000 0x6 0x0 -#define MX7D_PAD_ECSPI2_MOSI__ECSPI2_MOSI 0x017C 0x03EC 0x053C 0x0 0x0 -#define MX7D_PAD_ECSPI2_MOSI__UART7_DCE_TX 0x017C 0x03EC 0x0000 0x1 0x0 -#define MX7D_PAD_ECSPI2_MOSI__UART7_DTE_RX 0x017C 0x03EC 0x0724 0x1 0x3 -#define MX7D_PAD_ECSPI2_MOSI__SD1_DATA5 0x017C 0x03EC 0x0000 0x2 0x0 -#define MX7D_PAD_ECSPI2_MOSI__CSI_DATA7 0x017C 0x03EC 0x050C 0x3 0x1 -#define MX7D_PAD_ECSPI2_MOSI__LCD_DATA14 0x017C 0x03EC 0x0670 0x4 0x2 -#define MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x017C 0x03EC 0x0000 0x5 0x0 -#define MX7D_PAD_ECSPI2_MOSI__EPDC_PWR_CTRL1 0x017C 0x03EC 0x0000 0x6 0x0 -#define MX7D_PAD_ECSPI2_MISO__GPIO4_IO22 0x0180 0x03F0 0x0000 0x5 0x0 -#define MX7D_PAD_ECSPI2_MISO__EPDC_PWR_CTRL2 0x0180 0x03F0 0x0000 0x6 0x0 -#define MX7D_PAD_ECSPI2_MISO__ECSPI2_MISO 0x0180 0x03F0 0x0538 0x0 0x0 -#define MX7D_PAD_ECSPI2_MISO__UART7_DCE_RTS 0x0180 0x03F0 0x0720 0x1 0x2 -#define MX7D_PAD_ECSPI2_MISO__UART7_DTE_CTS 0x0180 0x03F0 0x0000 0x1 0x0 -#define MX7D_PAD_ECSPI2_MISO__SD1_DATA6 0x0180 0x03F0 0x0000 0x2 0x0 -#define MX7D_PAD_ECSPI2_MISO__CSI_DATA8 0x0180 0x03F0 0x0510 0x3 0x1 -#define MX7D_PAD_ECSPI2_MISO__LCD_DATA15 0x0180 0x03F0 0x0674 0x4 0x2 -#define MX7D_PAD_ECSPI2_SS0__ECSPI2_SS0 0x0184 0x03F4 0x0540 0x0 0x0 -#define MX7D_PAD_ECSPI2_SS0__UART7_DCE_CTS 0x0184 0x03F4 0x0000 0x1 0x0 -#define MX7D_PAD_ECSPI2_SS0__UART7_DTE_RTS 0x0184 0x03F4 0x0720 0x1 0x3 -#define MX7D_PAD_ECSPI2_SS0__SD1_DATA7 0x0184 0x03F4 0x0000 0x2 0x0 -#define MX7D_PAD_ECSPI2_SS0__CSI_DATA9 0x0184 0x03F4 0x0514 0x3 0x1 -#define MX7D_PAD_ECSPI2_SS0__LCD_RESET 0x0184 0x03F4 0x0000 0x4 0x0 -#define MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x0184 0x03F4 0x0000 0x5 0x0 -#define MX7D_PAD_ECSPI2_SS0__EPDC_PWR_WAKE 0x0184 0x03F4 0x0000 0x6 0x0 -#define MX7D_PAD_SD1_CD_B__SD1_CD_B 0x0188 0x03F8 0x0000 0x0 0x0 -#define MX7D_PAD_SD1_CD_B__UART6_DCE_RX 0x0188 0x03F8 0x071C 0x2 0x4 -#define MX7D_PAD_SD1_CD_B__UART6_DTE_TX 0x0188 0x03F8 0x0000 0x2 0x0 -#define MX7D_PAD_SD1_CD_B__ECSPI4_MISO 0x0188 0x03F8 0x0558 0x3 0x1 -#define MX7D_PAD_SD1_CD_B__FLEXTIMER1_CH0 0x0188 0x03F8 0x0584 0x4 0x1 -#define MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x0188 0x03F8 0x0000 0x5 0x0 -#define MX7D_PAD_SD1_CD_B__CCM_CLKO1 0x0188 0x03F8 0x0000 0x6 0x0 -#define MX7D_PAD_SD1_WP__SD1_WP 0x018C 0x03FC 0x0000 0x0 0x0 -#define MX7D_PAD_SD1_WP__UART6_DCE_TX 0x018C 0x03FC 0x0000 0x2 0x0 -#define MX7D_PAD_SD1_WP__UART6_DTE_RX 0x018C 0x03FC 0x071C 0x2 0x5 -#define MX7D_PAD_SD1_WP__ECSPI4_MOSI 0x018C 0x03FC 0x055C 0x3 0x1 -#define MX7D_PAD_SD1_WP__FLEXTIMER1_CH1 0x018C 0x03FC 0x0588 0x4 0x1 -#define MX7D_PAD_SD1_WP__GPIO5_IO1 0x018C 0x03FC 0x0000 0x5 0x0 -#define MX7D_PAD_SD1_WP__CCM_CLKO2 0x018C 0x03FC 0x0000 0x6 0x0 -#define MX7D_PAD_SD1_RESET_B__SD1_RESET_B 0x0190 0x0400 0x0000 0x0 0x0 -#define MX7D_PAD_SD1_RESET_B__SAI3_MCLK 0x0190 0x0400 0x0000 0x1 0x0 -#define MX7D_PAD_SD1_RESET_B__UART6_DCE_RTS 0x0190 0x0400 0x0718 0x2 0x4 -#define MX7D_PAD_SD1_RESET_B__UART6_DTE_CTS 0x0190 0x0400 0x0000 0x2 0x0 -#define MX7D_PAD_SD1_RESET_B__ECSPI4_SCLK 0x0190 0x0400 0x0554 0x3 0x1 -#define MX7D_PAD_SD1_RESET_B__FLEXTIMER1_CH2 0x0190 0x0400 0x058C 0x4 0x1 -#define MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x0190 0x0400 0x0000 0x5 0x0 -#define MX7D_PAD_SD1_CLK__SD1_CLK 0x0194 0x0404 0x0000 0x0 0x0 -#define MX7D_PAD_SD1_CLK__SAI3_RX_SYNC 0x0194 0x0404 0x06CC 0x1 0x1 -#define MX7D_PAD_SD1_CLK__UART6_DCE_CTS 0x0194 0x0404 0x0000 0x2 0x0 -#define MX7D_PAD_SD1_CLK__UART6_DTE_RTS 0x0194 0x0404 0x0718 0x2 0x5 -#define MX7D_PAD_SD1_CLK__ECSPI4_SS0 0x0194 0x0404 0x0560 0x3 0x1 -#define MX7D_PAD_SD1_CLK__FLEXTIMER1_CH3 0x0194 0x0404 0x0590 0x4 0x1 -#define MX7D_PAD_SD1_CLK__GPIO5_IO3 0x0194 0x0404 0x0000 0x5 0x0 -#define MX7D_PAD_SD1_CMD__SD1_CMD 0x0198 0x0408 0x0000 0x0 0x0 -#define MX7D_PAD_SD1_CMD__SAI3_RX_BCLK 0x0198 0x0408 0x06C4 0x1 0x1 -#define MX7D_PAD_SD1_CMD__ECSPI4_SS1 0x0198 0x0408 0x0000 0x3 0x0 -#define MX7D_PAD_SD1_CMD__FLEXTIMER2_CH0 0x0198 0x0408 0x05AC 0x4 0x1 -#define MX7D_PAD_SD1_CMD__GPIO5_IO4 0x0198 0x0408 0x0000 0x5 0x0 -#define MX7D_PAD_SD1_DATA0__SD1_DATA0 0x019C 0x040C 0x0000 0x0 0x0 -#define MX7D_PAD_SD1_DATA0__SAI3_RX_DATA0 0x019C 0x040C 0x06C8 0x1 0x1 -#define MX7D_PAD_SD1_DATA0__UART7_DCE_RX 0x019C 0x040C 0x0724 0x2 0x4 -#define MX7D_PAD_SD1_DATA0__UART7_DTE_TX 0x019C 0x040C 0x0000 0x2 0x0 -#define MX7D_PAD_SD1_DATA0__ECSPI4_SS2 0x019C 0x040C 0x0000 0x3 0x0 -#define MX7D_PAD_SD1_DATA0__FLEXTIMER2_CH1 0x019C 0x040C 0x05B0 0x4 0x1 -#define MX7D_PAD_SD1_DATA0__GPIO5_IO5 0x019C 0x040C 0x0000 0x5 0x0 -#define MX7D_PAD_SD1_DATA0__CCM_EXT_CLK1 0x019C 0x040C 0x04E4 0x6 0x1 -#define MX7D_PAD_SD1_DATA1__SD1_DATA1 0x01A0 0x0410 0x0000 0x0 0x0 -#define MX7D_PAD_SD1_DATA1__SAI3_TX_BCLK 0x01A0 0x0410 0x06D0 0x1 0x1 -#define MX7D_PAD_SD1_DATA1__UART7_DCE_TX 0x01A0 0x0410 0x0000 0x2 0x0 -#define MX7D_PAD_SD1_DATA1__UART7_DTE_RX 0x01A0 0x0410 0x0724 0x2 0x5 -#define MX7D_PAD_SD1_DATA1__ECSPI4_SS3 0x01A0 0x0410 0x0000 0x3 0x0 -#define MX7D_PAD_SD1_DATA1__FLEXTIMER2_CH2 0x01A0 0x0410 0x05B4 0x4 0x1 -#define MX7D_PAD_SD1_DATA1__GPIO5_IO6 0x01A0 0x0410 0x0000 0x5 0x0 -#define MX7D_PAD_SD1_DATA1__CCM_EXT_CLK2 0x01A0 0x0410 0x04E8 0x6 0x1 -#define MX7D_PAD_SD1_DATA2__SD1_DATA2 0x01A4 0x0414 0x0000 0x0 0x0 -#define MX7D_PAD_SD1_DATA2__SAI3_TX_SYNC 0x01A4 0x0414 0x06D4 0x1 0x1 -#define MX7D_PAD_SD1_DATA2__UART7_DCE_CTS 0x01A4 0x0414 0x0000 0x2 0x0 -#define MX7D_PAD_SD1_DATA2__UART7_DTE_RTS 0x01A4 0x0414 0x0720 0x2 0x4 -#define MX7D_PAD_SD1_DATA2__ECSPI4_RDY 0x01A4 0x0414 0x0000 0x3 0x0 -#define MX7D_PAD_SD1_DATA2__FLEXTIMER2_CH3 0x01A4 0x0414 0x05B8 0x4 0x1 -#define MX7D_PAD_SD1_DATA2__GPIO5_IO7 0x01A4 0x0414 0x0000 0x5 0x0 -#define MX7D_PAD_SD1_DATA2__CCM_EXT_CLK3 0x01A4 0x0414 0x04EC 0x6 0x1 -#define MX7D_PAD_SD1_DATA3__SD1_DATA3 0x01A8 0x0418 0x0000 0x0 0x0 -#define MX7D_PAD_SD1_DATA3__SAI3_TX_DATA0 0x01A8 0x0418 0x0000 0x1 0x0 -#define MX7D_PAD_SD1_DATA3__UART7_DCE_RTS 0x01A8 0x0418 0x0720 0x2 0x5 -#define MX7D_PAD_SD1_DATA3__UART7_DTE_CTS 0x01A8 0x0418 0x0000 0x2 0x0 -#define MX7D_PAD_SD1_DATA3__ECSPI3_SS1 0x01A8 0x0418 0x0000 0x3 0x0 -#define MX7D_PAD_SD1_DATA3__FLEXTIMER1_PHA 0x01A8 0x0418 0x05A4 0x4 0x1 -#define MX7D_PAD_SD1_DATA3__GPIO5_IO8 0x01A8 0x0418 0x0000 0x5 0x0 -#define MX7D_PAD_SD1_DATA3__CCM_EXT_CLK4 0x01A8 0x0418 0x04F0 0x6 0x1 -#define MX7D_PAD_SD2_CD_B__SD2_CD_B 0x01AC 0x041C 0x0000 0x0 0x0 -#define MX7D_PAD_SD2_CD_B__ENET1_MDIO 0x01AC 0x041C 0x0568 0x1 0x2 -#define MX7D_PAD_SD2_CD_B__ENET2_MDIO 0x01AC 0x041C 0x0574 0x2 0x2 -#define MX7D_PAD_SD2_CD_B__ECSPI3_SS2 0x01AC 0x041C 0x0000 0x3 0x0 -#define MX7D_PAD_SD2_CD_B__FLEXTIMER1_PHB 0x01AC 0x041C 0x05A8 0x4 0x1 -#define MX7D_PAD_SD2_CD_B__GPIO5_IO9 0x01AC 0x041C 0x0000 0x5 0x0 -#define MX7D_PAD_SD2_CD_B__SDMA_EXT_EVENT0 0x01AC 0x041C 0x06D8 0x6 0x2 -#define MX7D_PAD_SD2_WP__SD2_WP 0x01B0 0x0420 0x0000 0x0 0x0 -#define MX7D_PAD_SD2_WP__ENET1_MDC 0x01B0 0x0420 0x0000 0x1 0x0 -#define MX7D_PAD_SD2_WP__ENET2_MDC 0x01B0 0x0420 0x0000 0x2 0x0 -#define MX7D_PAD_SD2_WP__ECSPI3_SS3 0x01B0 0x0420 0x0000 0x3 0x0 -#define MX7D_PAD_SD2_WP__USB_OTG1_ID 0x01B0 0x0420 0x0734 0x4 0x2 -#define MX7D_PAD_SD2_WP__GPIO5_IO10 0x01B0 0x0420 0x0000 0x5 0x0 -#define MX7D_PAD_SD2_WP__SDMA_EXT_EVENT1 0x01B0 0x0420 0x06DC 0x6 0x2 -#define MX7D_PAD_SD2_RESET_B__SD2_RESET_B 0x01B4 0x0424 0x0000 0x0 0x0 -#define MX7D_PAD_SD2_RESET_B__SAI2_MCLK 0x01B4 0x0424 0x0000 0x1 0x0 -#define MX7D_PAD_SD2_RESET_B__SD2_RESET 0x01B4 0x0424 0x0000 0x2 0x0 -#define MX7D_PAD_SD2_RESET_B__ECSPI3_RDY 0x01B4 0x0424 0x0000 0x3 0x0 -#define MX7D_PAD_SD2_RESET_B__USB_OTG2_ID 0x01B4 0x0424 0x0730 0x4 0x2 -#define MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x01B4 0x0424 0x0000 0x5 0x0 -#define MX7D_PAD_SD2_CLK__SD2_CLK 0x01B8 0x0428 0x0000 0x0 0x0 -#define MX7D_PAD_SD2_CLK__SAI2_RX_SYNC 0x01B8 0x0428 0x06B8 0x1 0x0 -#define MX7D_PAD_SD2_CLK__MQS_RIGHT 0x01B8 0x0428 0x0000 0x2 0x0 -#define MX7D_PAD_SD2_CLK__GPT4_CLK 0x01B8 0x0428 0x0000 0x3 0x0 -#define MX7D_PAD_SD2_CLK__GPIO5_IO12 0x01B8 0x0428 0x0000 0x5 0x0 -#define MX7D_PAD_SD2_CMD__SD2_CMD 0x01BC 0x042C 0x0000 0x0 0x0 -#define MX7D_PAD_SD2_CMD__SAI2_RX_BCLK 0x01BC 0x042C 0x06B0 0x1 0x0 -#define MX7D_PAD_SD2_CMD__MQS_LEFT 0x01BC 0x042C 0x0000 0x2 0x0 -#define MX7D_PAD_SD2_CMD__GPT4_CAPTURE1 0x01BC 0x042C 0x0000 0x3 0x0 -#define MX7D_PAD_SD2_CMD__SIM2_PORT1_TRXD 0x01BC 0x042C 0x06EC 0x4 0x1 -#define MX7D_PAD_SD2_CMD__GPIO5_IO13 0x01BC 0x042C 0x0000 0x5 0x0 -#define MX7D_PAD_SD2_DATA0__SD2_DATA0 0x01C0 0x0430 0x0000 0x0 0x0 -#define MX7D_PAD_SD2_DATA0__SAI2_RX_DATA0 0x01C0 0x0430 0x06B4 0x1 0x0 -#define MX7D_PAD_SD2_DATA0__UART4_DCE_RX 0x01C0 0x0430 0x070C 0x2 0x2 -#define MX7D_PAD_SD2_DATA0__UART4_DTE_TX 0x01C0 0x0430 0x0000 0x2 0x0 -#define MX7D_PAD_SD2_DATA0__GPT4_CAPTURE2 0x01C0 0x0430 0x0000 0x3 0x0 -#define MX7D_PAD_SD2_DATA0__SIM2_PORT1_CLK 0x01C0 0x0430 0x0000 0x4 0x0 -#define MX7D_PAD_SD2_DATA0__GPIO5_IO14 0x01C0 0x0430 0x0000 0x5 0x0 -#define MX7D_PAD_SD2_DATA1__SD2_DATA1 0x01C4 0x0434 0x0000 0x0 0x0 -#define MX7D_PAD_SD2_DATA1__SAI2_TX_BCLK 0x01C4 0x0434 0x06BC 0x1 0x0 -#define MX7D_PAD_SD2_DATA1__UART4_DCE_TX 0x01C4 0x0434 0x0000 0x2 0x0 -#define MX7D_PAD_SD2_DATA1__UART4_DTE_RX 0x01C4 0x0434 0x070C 0x2 0x3 -#define MX7D_PAD_SD2_DATA1__GPT4_COMPARE1 0x01C4 0x0434 0x0000 0x3 0x0 -#define MX7D_PAD_SD2_DATA1__SIM2_PORT1_RST_B 0x01C4 0x0434 0x0000 0x4 0x0 -#define MX7D_PAD_SD2_DATA1__GPIO5_IO15 0x01C4 0x0434 0x0000 0x5 0x0 -#define MX7D_PAD_SD2_DATA2__SD2_DATA2 0x01C8 0x0438 0x0000 0x0 0x0 -#define MX7D_PAD_SD2_DATA2__SAI2_TX_SYNC 0x01C8 0x0438 0x06C0 0x1 0x0 -#define MX7D_PAD_SD2_DATA2__UART4_DCE_CTS 0x01C8 0x0438 0x0000 0x2 0x0 -#define MX7D_PAD_SD2_DATA2__UART4_DTE_RTS 0x01C8 0x0438 0x0708 0x2 0x2 -#define MX7D_PAD_SD2_DATA2__GPT4_COMPARE2 0x01C8 0x0438 0x0000 0x3 0x0 -#define MX7D_PAD_SD2_DATA2__SIM2_PORT1_SVEN 0x01C8 0x0438 0x0000 0x4 0x0 -#define MX7D_PAD_SD2_DATA2__GPIO5_IO16 0x01C8 0x0438 0x0000 0x5 0x0 -#define MX7D_PAD_SD2_DATA3__SD2_DATA3 0x01CC 0x043C 0x0000 0x0 0x0 -#define MX7D_PAD_SD2_DATA3__SAI2_TX_DATA0 0x01CC 0x043C 0x0000 0x1 0x0 -#define MX7D_PAD_SD2_DATA3__UART4_DCE_RTS 0x01CC 0x043C 0x0708 0x2 0x3 -#define MX7D_PAD_SD2_DATA3__UART4_DTE_CTS 0x01CC 0x043C 0x0000 0x2 0x0 -#define MX7D_PAD_SD2_DATA3__GPT4_COMPARE3 0x01CC 0x043C 0x0000 0x3 0x0 -#define MX7D_PAD_SD2_DATA3__SIM2_PORT1_PD 0x01CC 0x043C 0x06E8 0x4 0x1 -#define MX7D_PAD_SD2_DATA3__GPIO5_IO17 0x01CC 0x043C 0x0000 0x5 0x0 -#define MX7D_PAD_SD3_CLK__SD3_CLK 0x01D0 0x0440 0x0000 0x0 0x0 -#define MX7D_PAD_SD3_CLK__NAND_CLE 0x01D0 0x0440 0x0000 0x1 0x0 -#define MX7D_PAD_SD3_CLK__ECSPI4_MISO 0x01D0 0x0440 0x0558 0x2 0x2 -#define MX7D_PAD_SD3_CLK__SAI3_RX_SYNC 0x01D0 0x0440 0x06CC 0x3 0x2 -#define MX7D_PAD_SD3_CLK__GPT3_CLK 0x01D0 0x0440 0x0000 0x4 0x0 -#define MX7D_PAD_SD3_CLK__GPIO6_IO0 0x01D0 0x0440 0x0000 0x5 0x0 -#define MX7D_PAD_SD3_CMD__SD3_CMD 0x01D4 0x0444 0x0000 0x0 0x0 -#define MX7D_PAD_SD3_CMD__NAND_ALE 0x01D4 0x0444 0x0000 0x1 0x0 -#define MX7D_PAD_SD3_CMD__ECSPI4_MOSI 0x01D4 0x0444 0x055C 0x2 0x2 -#define MX7D_PAD_SD3_CMD__SAI3_RX_BCLK 0x01D4 0x0444 0x06C4 0x3 0x2 -#define MX7D_PAD_SD3_CMD__GPT3_CAPTURE1 0x01D4 0x0444 0x0000 0x4 0x0 -#define MX7D_PAD_SD3_CMD__GPIO6_IO1 0x01D4 0x0444 0x0000 0x5 0x0 -#define MX7D_PAD_SD3_DATA0__SD3_DATA0 0x01D8 0x0448 0x0000 0x0 0x0 -#define MX7D_PAD_SD3_DATA0__NAND_DATA00 0x01D8 0x0448 0x0000 0x1 0x0 -#define MX7D_PAD_SD3_DATA0__ECSPI4_SS0 0x01D8 0x0448 0x0560 0x2 0x2 -#define MX7D_PAD_SD3_DATA0__SAI3_RX_DATA0 0x01D8 0x0448 0x06C8 0x3 0x2 -#define MX7D_PAD_SD3_DATA0__GPT3_CAPTURE2 0x01D8 0x0448 0x0000 0x4 0x0 -#define MX7D_PAD_SD3_DATA0__GPIO6_IO2 0x01D8 0x0448 0x0000 0x5 0x0 -#define MX7D_PAD_SD3_DATA1__SD3_DATA1 0x01DC 0x044C 0x0000 0x0 0x0 -#define MX7D_PAD_SD3_DATA1__NAND_DATA01 0x01DC 0x044C 0x0000 0x1 0x0 -#define MX7D_PAD_SD3_DATA1__ECSPI4_SCLK 0x01DC 0x044C 0x0554 0x2 0x2 -#define MX7D_PAD_SD3_DATA1__SAI3_TX_BCLK 0x01DC 0x044C 0x06D0 0x3 0x2 -#define MX7D_PAD_SD3_DATA1__GPT3_COMPARE1 0x01DC 0x044C 0x0000 0x4 0x0 -#define MX7D_PAD_SD3_DATA1__GPIO6_IO3 0x01DC 0x044C 0x0000 0x5 0x0 -#define MX7D_PAD_SD3_DATA2__SD3_DATA2 0x01E0 0x0450 0x0000 0x0 0x0 -#define MX7D_PAD_SD3_DATA2__NAND_DATA02 0x01E0 0x0450 0x0000 0x1 0x0 -#define MX7D_PAD_SD3_DATA2__I2C3_SDA 0x01E0 0x0450 0x05E8 0x2 0x3 -#define MX7D_PAD_SD3_DATA2__SAI3_TX_SYNC 0x01E0 0x0450 0x06D4 0x3 0x2 -#define MX7D_PAD_SD3_DATA2__GPT3_COMPARE2 0x01E0 0x0450 0x0000 0x4 0x0 -#define MX7D_PAD_SD3_DATA2__GPIO6_IO4 0x01E0 0x0450 0x0000 0x5 0x0 -#define MX7D_PAD_SD3_DATA3__SD3_DATA3 0x01E4 0x0454 0x0000 0x0 0x0 -#define MX7D_PAD_SD3_DATA3__NAND_DATA03 0x01E4 0x0454 0x0000 0x1 0x0 -#define MX7D_PAD_SD3_DATA3__I2C3_SCL 0x01E4 0x0454 0x05E4 0x2 0x3 -#define MX7D_PAD_SD3_DATA3__SAI3_TX_DATA0 0x01E4 0x0454 0x0000 0x3 0x0 -#define MX7D_PAD_SD3_DATA3__GPT3_COMPARE3 0x01E4 0x0454 0x0000 0x4 0x0 -#define MX7D_PAD_SD3_DATA3__GPIO6_IO5 0x01E4 0x0454 0x0000 0x5 0x0 -#define MX7D_PAD_SD3_DATA4__SD3_DATA4 0x01E8 0x0458 0x0000 0x0 0x0 -#define MX7D_PAD_SD3_DATA4__NAND_DATA04 0x01E8 0x0458 0x0000 0x1 0x0 -#define MX7D_PAD_SD3_DATA4__UART3_DCE_RX 0x01E8 0x0458 0x0704 0x3 0x4 -#define MX7D_PAD_SD3_DATA4__UART3_DTE_TX 0x01E8 0x0458 0x0000 0x3 0x0 -#define MX7D_PAD_SD3_DATA4__FLEXCAN2_RX 0x01E8 0x0458 0x04E0 0x4 0x2 -#define MX7D_PAD_SD3_DATA4__GPIO6_IO6 0x01E8 0x0458 0x0000 0x5 0x0 -#define MX7D_PAD_SD3_DATA5__SD3_DATA5 0x01EC 0x045C 0x0000 0x0 0x0 -#define MX7D_PAD_SD3_DATA5__NAND_DATA05 0x01EC 0x045C 0x0000 0x1 0x0 -#define MX7D_PAD_SD3_DATA5__UART3_DCE_TX 0x01EC 0x045C 0x0000 0x3 0x0 -#define MX7D_PAD_SD3_DATA5__UART3_DTE_RX 0x01EC 0x045C 0x0704 0x3 0x5 -#define MX7D_PAD_SD3_DATA5__FLEXCAN1_TX 0x01EC 0x045C 0x0000 0x4 0x0 -#define MX7D_PAD_SD3_DATA5__GPIO6_IO7 0x01EC 0x045C 0x0000 0x5 0x0 -#define MX7D_PAD_SD3_DATA6__SD3_DATA6 0x01F0 0x0460 0x0000 0x0 0x0 -#define MX7D_PAD_SD3_DATA6__NAND_DATA06 0x01F0 0x0460 0x0000 0x1 0x0 -#define MX7D_PAD_SD3_DATA6__SD3_WP 0x01F0 0x0460 0x073C 0x2 0x2 -#define MX7D_PAD_SD3_DATA6__UART3_DCE_RTS 0x01F0 0x0460 0x0700 0x3 0x4 -#define MX7D_PAD_SD3_DATA6__UART3_DTE_CTS 0x01F0 0x0460 0x0000 0x3 0x0 -#define MX7D_PAD_SD3_DATA6__FLEXCAN2_TX 0x01F0 0x0460 0x0000 0x4 0x0 -#define MX7D_PAD_SD3_DATA6__GPIO6_IO8 0x01F0 0x0460 0x0000 0x5 0x0 -#define MX7D_PAD_SD3_DATA7__SD3_DATA7 0x01F4 0x0464 0x0000 0x0 0x0 -#define MX7D_PAD_SD3_DATA7__NAND_DATA07 0x01F4 0x0464 0x0000 0x1 0x0 -#define MX7D_PAD_SD3_DATA7__SD3_CD_B 0x01F4 0x0464 0x0738 0x2 0x2 -#define MX7D_PAD_SD3_DATA7__UART3_DCE_CTS 0x01F4 0x0464 0x0000 0x3 0x0 -#define MX7D_PAD_SD3_DATA7__UART3_DTE_RTS 0x01F4 0x0464 0x0700 0x3 0x5 -#define MX7D_PAD_SD3_DATA7__FLEXCAN1_RX 0x01F4 0x0464 0x04DC 0x4 0x2 -#define MX7D_PAD_SD3_DATA7__GPIO6_IO9 0x01F4 0x0464 0x0000 0x5 0x0 -#define MX7D_PAD_SD3_STROBE__SD3_STROBE 0x01F8 0x0468 0x0000 0x0 0x0 -#define MX7D_PAD_SD3_STROBE__NAND_RE_B 0x01F8 0x0468 0x0000 0x1 0x0 -#define MX7D_PAD_SD3_STROBE__GPIO6_IO10 0x01F8 0x0468 0x0000 0x5 0x0 -#define MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x01FC 0x046C 0x0000 0x0 0x0 -#define MX7D_PAD_SD3_RESET_B__NAND_WE_B 0x01FC 0x046C 0x0000 0x1 0x0 -#define MX7D_PAD_SD3_RESET_B__SD3_RESET 0x01FC 0x046C 0x0000 0x2 0x0 -#define MX7D_PAD_SD3_RESET_B__SAI3_MCLK 0x01FC 0x046C 0x0000 0x3 0x0 -#define MX7D_PAD_SD3_RESET_B__GPIO6_IO11 0x01FC 0x046C 0x0000 0x5 0x0 -#define MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0 0x0200 0x0470 0x06A0 0x0 0x0 -#define MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B 0x0200 0x0470 0x0000 0x1 0x0 -#define MX7D_PAD_SAI1_RX_DATA__UART5_DCE_RX 0x0200 0x0470 0x0714 0x2 0x2 -#define MX7D_PAD_SAI1_RX_DATA__UART5_DTE_TX 0x0200 0x0470 0x0000 0x2 0x0 -#define MX7D_PAD_SAI1_RX_DATA__FLEXCAN1_RX 0x0200 0x0470 0x04DC 0x3 0x3 -#define MX7D_PAD_SAI1_RX_DATA__SIM1_PORT1_TRXD 0x0200 0x0470 0x06E4 0x4 0x1 -#define MX7D_PAD_SAI1_RX_DATA__GPIO6_IO12 0x0200 0x0470 0x0000 0x5 0x0 -#define MX7D_PAD_SAI1_RX_DATA__SRC_ANY_PU_RESET 0x0200 0x0470 0x0000 0x7 0x0 -#define MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK 0x0204 0x0474 0x06A8 0x0 0x0 -#define MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B 0x0204 0x0474 0x0000 0x1 0x0 -#define MX7D_PAD_SAI1_TX_BCLK__UART5_DCE_TX 0x0204 0x0474 0x0000 0x2 0x0 -#define MX7D_PAD_SAI1_TX_BCLK__UART5_DTE_RX 0x0204 0x0474 0x0714 0x2 0x3 -#define MX7D_PAD_SAI1_TX_BCLK__FLEXCAN1_TX 0x0204 0x0474 0x0000 0x3 0x0 -#define MX7D_PAD_SAI1_TX_BCLK__SIM1_PORT1_CLK 0x0204 0x0474 0x0000 0x4 0x0 -#define MX7D_PAD_SAI1_TX_BCLK__GPIO6_IO13 0x0204 0x0474 0x0000 0x5 0x0 -#define MX7D_PAD_SAI1_TX_BCLK__SRC_EARLY_RESET 0x0204 0x0474 0x0000 0x7 0x0 -#define MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x0208 0x0478 0x06AC 0x0 0x0 -#define MX7D_PAD_SAI1_TX_SYNC__NAND_DQS 0x0208 0x0478 0x0000 0x1 0x0 -#define MX7D_PAD_SAI1_TX_SYNC__UART5_DCE_CTS 0x0208 0x0478 0x0000 0x2 0x0 -#define MX7D_PAD_SAI1_TX_SYNC__UART5_DTE_RTS 0x0208 0x0478 0x0710 0x2 0x2 -#define MX7D_PAD_SAI1_TX_SYNC__FLEXCAN2_RX 0x0208 0x0478 0x04E0 0x3 0x3 -#define MX7D_PAD_SAI1_TX_SYNC__SIM1_PORT1_RST_B 0x0208 0x0478 0x0000 0x4 0x0 -#define MX7D_PAD_SAI1_TX_SYNC__GPIO6_IO14 0x0208 0x0478 0x0000 0x5 0x0 -#define MX7D_PAD_SAI1_TX_SYNC__SRC_INT_BOOT 0x0208 0x0478 0x0000 0x7 0x0 -#define MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0 0x020C 0x047C 0x0000 0x0 0x0 -#define MX7D_PAD_SAI1_TX_DATA__NAND_READY_B 0x020C 0x047C 0x0000 0x1 0x0 -#define MX7D_PAD_SAI1_TX_DATA__UART5_DCE_RTS 0x020C 0x047C 0x0710 0x2 0x3 -#define MX7D_PAD_SAI1_TX_DATA__UART5_DTE_CTS 0x020C 0x047C 0x0000 0x2 0x0 -#define MX7D_PAD_SAI1_TX_DATA__FLEXCAN2_TX 0x020C 0x047C 0x0000 0x3 0x0 -#define MX7D_PAD_SAI1_TX_DATA__SIM1_PORT1_SVEN 0x020C 0x047C 0x0000 0x4 0x0 -#define MX7D_PAD_SAI1_TX_DATA__GPIO6_IO15 0x020C 0x047C 0x0000 0x5 0x0 -#define MX7D_PAD_SAI1_TX_DATA__SRC_SYSTEM_RESET 0x020C 0x047C 0x0000 0x7 0x0 -#define MX7D_PAD_SAI1_RX_SYNC__SAI1_RX_SYNC 0x0210 0x0480 0x06A4 0x0 0x0 -#define MX7D_PAD_SAI1_RX_SYNC__NAND_CE2_B 0x0210 0x0480 0x0000 0x1 0x0 -#define MX7D_PAD_SAI1_RX_SYNC__SAI2_RX_SYNC 0x0210 0x0480 0x06B8 0x2 0x1 -#define MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL 0x0210 0x0480 0x05EC 0x3 0x3 -#define MX7D_PAD_SAI1_RX_SYNC__SIM1_PORT1_PD 0x0210 0x0480 0x06E0 0x4 0x1 -#define MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 0x0210 0x0480 0x0000 0x5 0x0 -#define MX7D_PAD_SAI1_RX_SYNC__MQS_RIGHT 0x0210 0x0480 0x0000 0x6 0x0 -#define MX7D_PAD_SAI1_RX_SYNC__SRC_CA7_RESET_B0 0x0210 0x0480 0x0000 0x7 0x0 -#define MX7D_PAD_SAI1_RX_BCLK__SAI1_RX_BCLK 0x0214 0x0484 0x069C 0x0 0x0 -#define MX7D_PAD_SAI1_RX_BCLK__NAND_CE3_B 0x0214 0x0484 0x0000 0x1 0x0 -#define MX7D_PAD_SAI1_RX_BCLK__SAI2_RX_BCLK 0x0214 0x0484 0x06B0 0x2 0x1 -#define MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA 0x0214 0x0484 0x05F0 0x3 0x3 -#define MX7D_PAD_SAI1_RX_BCLK__FLEXTIMER2_PHA 0x0214 0x0484 0x05CC 0x4 0x1 -#define MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17 0x0214 0x0484 0x0000 0x5 0x0 -#define MX7D_PAD_SAI1_RX_BCLK__MQS_LEFT 0x0214 0x0484 0x0000 0x6 0x0 -#define MX7D_PAD_SAI1_RX_BCLK__SRC_CA7_RESET_B1 0x0214 0x0484 0x0000 0x7 0x0 -#define MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x0218 0x0488 0x0000 0x0 0x0 -#define MX7D_PAD_SAI1_MCLK__NAND_WP_B 0x0218 0x0488 0x0000 0x1 0x0 -#define MX7D_PAD_SAI1_MCLK__SAI2_MCLK 0x0218 0x0488 0x0000 0x2 0x0 -#define MX7D_PAD_SAI1_MCLK__CCM_PMIC_READY 0x0218 0x0488 0x04F4 0x3 0x3 -#define MX7D_PAD_SAI1_MCLK__FLEXTIMER2_PHB 0x0218 0x0488 0x05D0 0x4 0x1 -#define MX7D_PAD_SAI1_MCLK__GPIO6_IO18 0x0218 0x0488 0x0000 0x5 0x0 -#define MX7D_PAD_SAI1_MCLK__SRC_TESTER_ACK 0x0218 0x0488 0x0000 0x7 0x0 -#define MX7D_PAD_SAI2_TX_SYNC__SAI2_TX_SYNC 0x021C 0x048C 0x06C0 0x0 0x1 -#define MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO 0x021C 0x048C 0x0548 0x1 0x1 -#define MX7D_PAD_SAI2_TX_SYNC__UART4_DCE_RX 0x021C 0x048C 0x070C 0x2 0x4 -#define MX7D_PAD_SAI2_TX_SYNC__UART4_DTE_TX 0x021C 0x048C 0x0000 0x2 0x0 -#define MX7D_PAD_SAI2_TX_SYNC__UART1_DCE_CTS 0x021C 0x048C 0x0000 0x3 0x0 -#define MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS 0x021C 0x048C 0x06F0 0x3 0x0 -#define MX7D_PAD_SAI2_TX_SYNC__FLEXTIMER2_CH4 0x021C 0x048C 0x05BC 0x4 0x1 -#define MX7D_PAD_SAI2_TX_SYNC__GPIO6_IO19 0x021C 0x048C 0x0000 0x5 0x0 -#define MX7D_PAD_SAI2_TX_BCLK__SAI2_TX_BCLK 0x0220 0x0490 0x06BC 0x0 0x1 -#define MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI 0x0220 0x0490 0x054C 0x1 0x1 -#define MX7D_PAD_SAI2_TX_BCLK__UART4_DCE_TX 0x0220 0x0490 0x0000 0x2 0x0 -#define MX7D_PAD_SAI2_TX_BCLK__UART4_DTE_RX 0x0220 0x0490 0x070C 0x2 0x5 -#define MX7D_PAD_SAI2_TX_BCLK__UART1_DCE_RTS 0x0220 0x0490 0x06F0 0x3 0x1 -#define MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS 0x0220 0x0490 0x0000 0x3 0x0 -#define MX7D_PAD_SAI2_TX_BCLK__FLEXTIMER2_CH5 0x0220 0x0490 0x05C0 0x4 0x1 -#define MX7D_PAD_SAI2_TX_BCLK__GPIO6_IO20 0x0220 0x0490 0x0000 0x5 0x0 -#define MX7D_PAD_SAI2_RX_DATA__SAI2_RX_DATA0 0x0224 0x0494 0x06B4 0x0 0x1 -#define MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK 0x0224 0x0494 0x0544 0x1 0x1 -#define MX7D_PAD_SAI2_RX_DATA__UART4_DCE_CTS 0x0224 0x0494 0x0000 0x2 0x0 -#define MX7D_PAD_SAI2_RX_DATA__UART4_DTE_RTS 0x0224 0x0494 0x0708 0x2 0x4 -#define MX7D_PAD_SAI2_RX_DATA__UART2_DCE_CTS 0x0224 0x0494 0x0000 0x3 0x0 -#define MX7D_PAD_SAI2_RX_DATA__UART2_DTE_RTS 0x0224 0x0494 0x06F8 0x3 0x2 -#define MX7D_PAD_SAI2_RX_DATA__FLEXTIMER2_CH6 0x0224 0x0494 0x05C4 0x4 0x1 -#define MX7D_PAD_SAI2_RX_DATA__GPIO6_IO21 0x0224 0x0494 0x0000 0x5 0x0 -#define MX7D_PAD_SAI2_RX_DATA__KPP_COL7 0x0224 0x0494 0x0610 0x6 0x1 -#define MX7D_PAD_SAI2_TX_DATA__SAI2_TX_DATA0 0x0228 0x0498 0x0000 0x0 0x0 -#define MX7D_PAD_SAI2_TX_DATA__ECSPI3_SS0 0x0228 0x0498 0x0550 0x1 0x1 -#define MX7D_PAD_SAI2_TX_DATA__UART4_DCE_RTS 0x0228 0x0498 0x0708 0x2 0x5 -#define MX7D_PAD_SAI2_TX_DATA__UART4_DTE_CTS 0x0228 0x0498 0x0000 0x2 0x0 -#define MX7D_PAD_SAI2_TX_DATA__UART2_DCE_RTS 0x0228 0x0498 0x06F8 0x3 0x3 -#define MX7D_PAD_SAI2_TX_DATA__UART2_DTE_CTS 0x0228 0x0498 0x0000 0x3 0x0 -#define MX7D_PAD_SAI2_TX_DATA__FLEXTIMER2_CH7 0x0228 0x0498 0x05C8 0x4 0x1 -#define MX7D_PAD_SAI2_TX_DATA__GPIO6_IO22 0x0228 0x0498 0x0000 0x5 0x0 -#define MX7D_PAD_SAI2_TX_DATA__KPP_ROW7 0x0228 0x0498 0x0630 0x6 0x1 -#define MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x022C 0x049C 0x0000 0x0 0x0 -#define MX7D_PAD_ENET1_RGMII_RD0__PWM1_OUT 0x022C 0x049C 0x0000 0x1 0x0 -#define MX7D_PAD_ENET1_RGMII_RD0__I2C3_SCL 0x022C 0x049C 0x05E4 0x2 0x4 -#define MX7D_PAD_ENET1_RGMII_RD0__UART1_DCE_CTS 0x022C 0x049C 0x0000 0x3 0x0 -#define MX7D_PAD_ENET1_RGMII_RD0__UART1_DTE_RTS 0x022C 0x049C 0x06F0 0x3 0x2 -#define MX7D_PAD_ENET1_RGMII_RD0__EPDC_VCOM0 0x022C 0x049C 0x0000 0x4 0x0 -#define MX7D_PAD_ENET1_RGMII_RD0__GPIO7_IO0 0x022C 0x049C 0x0000 0x5 0x0 -#define MX7D_PAD_ENET1_RGMII_RD0__KPP_ROW3 0x022C 0x049C 0x0620 0x6 0x1 -#define MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x0230 0x04A0 0x0000 0x0 0x0 -#define MX7D_PAD_ENET1_RGMII_RD1__PWM2_OUT 0x0230 0x04A0 0x0000 0x1 0x0 -#define MX7D_PAD_ENET1_RGMII_RD1__I2C3_SDA 0x0230 0x04A0 0x05E8 0x2 0x4 -#define MX7D_PAD_ENET1_RGMII_RD1__UART1_DCE_RTS 0x0230 0x04A0 0x06F0 0x3 0x3 -#define MX7D_PAD_ENET1_RGMII_RD1__UART1_DTE_CTS 0x0230 0x04A0 0x0000 0x3 0x0 -#define MX7D_PAD_ENET1_RGMII_RD1__EPDC_VCOM1 0x0230 0x04A0 0x0000 0x4 0x0 -#define MX7D_PAD_ENET1_RGMII_RD1__GPIO7_IO1 0x0230 0x04A0 0x0000 0x5 0x0 -#define MX7D_PAD_ENET1_RGMII_RD1__KPP_COL3 0x0230 0x04A0 0x0600 0x6 0x1 -#define MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x0234 0x04A4 0x0000 0x0 0x0 -#define MX7D_PAD_ENET1_RGMII_RD2__FLEXCAN1_RX 0x0234 0x04A4 0x04DC 0x1 0x4 -#define MX7D_PAD_ENET1_RGMII_RD2__ECSPI2_SCLK 0x0234 0x04A4 0x0534 0x2 0x1 -#define MX7D_PAD_ENET1_RGMII_RD2__UART1_DCE_RX 0x0234 0x04A4 0x06F4 0x3 0x2 -#define MX7D_PAD_ENET1_RGMII_RD2__UART1_DTE_TX 0x0234 0x04A4 0x0000 0x3 0x0 -#define MX7D_PAD_ENET1_RGMII_RD2__EPDC_SDCE4 0x0234 0x04A4 0x0000 0x4 0x0 -#define MX7D_PAD_ENET1_RGMII_RD2__GPIO7_IO2 0x0234 0x04A4 0x0000 0x5 0x0 -#define MX7D_PAD_ENET1_RGMII_RD2__KPP_ROW2 0x0234 0x04A4 0x061C 0x6 0x1 -#define MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x0238 0x04A8 0x0000 0x0 0x0 -#define MX7D_PAD_ENET1_RGMII_RD3__FLEXCAN1_TX 0x0238 0x04A8 0x0000 0x1 0x0 -#define MX7D_PAD_ENET1_RGMII_RD3__ECSPI2_MOSI 0x0238 0x04A8 0x053C 0x2 0x1 -#define MX7D_PAD_ENET1_RGMII_RD3__UART1_DCE_TX 0x0238 0x04A8 0x0000 0x3 0x0 -#define MX7D_PAD_ENET1_RGMII_RD3__UART1_DTE_RX 0x0238 0x04A8 0x06F4 0x3 0x3 -#define MX7D_PAD_ENET1_RGMII_RD3__EPDC_SDCE5 0x0238 0x04A8 0x0000 0x4 0x0 -#define MX7D_PAD_ENET1_RGMII_RD3__GPIO7_IO3 0x0238 0x04A8 0x0000 0x5 0x0 -#define MX7D_PAD_ENET1_RGMII_RD3__KPP_COL2 0x0238 0x04A8 0x05FC 0x6 0x1 -#define MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x023C 0x04AC 0x0000 0x0 0x0 -#define MX7D_PAD_ENET1_RGMII_RX_CTL__ECSPI2_SS1 0x023C 0x04AC 0x0000 0x2 0x0 -#define MX7D_PAD_ENET1_RGMII_RX_CTL__EPDC_SDCE6 0x023C 0x04AC 0x0000 0x4 0x0 -#define MX7D_PAD_ENET1_RGMII_RX_CTL__GPIO7_IO4 0x023C 0x04AC 0x0000 0x5 0x0 -#define MX7D_PAD_ENET1_RGMII_RX_CTL__KPP_ROW1 0x023C 0x04AC 0x0618 0x6 0x1 -#define MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x0240 0x04B0 0x0000 0x0 0x0 -#define MX7D_PAD_ENET1_RGMII_RXC__ENET1_RX_ER 0x0240 0x04B0 0x0000 0x1 0x0 -#define MX7D_PAD_ENET1_RGMII_RXC__ECSPI2_SS2 0x0240 0x04B0 0x0000 0x2 0x0 -#define MX7D_PAD_ENET1_RGMII_RXC__EPDC_SDCE7 0x0240 0x04B0 0x0000 0x4 0x0 -#define MX7D_PAD_ENET1_RGMII_RXC__GPIO7_IO5 0x0240 0x04B0 0x0000 0x5 0x0 -#define MX7D_PAD_ENET1_RGMII_RXC__KPP_COL1 0x0240 0x04B0 0x0000 0x6 0x0 -#define MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x0244 0x04B4 0x0000 0x0 0x0 -#define MX7D_PAD_ENET1_RGMII_TD0__PWM3_OUT 0x0244 0x04B4 0x0000 0x1 0x0 -#define MX7D_PAD_ENET1_RGMII_TD0__ECSPI2_SS3 0x0244 0x04B4 0x0000 0x2 0x0 -#define MX7D_PAD_ENET1_RGMII_TD0__EPDC_SDCE8 0x0244 0x04B4 0x0000 0x4 0x0 -#define MX7D_PAD_ENET1_RGMII_TD0__GPIO7_IO6 0x0244 0x04B4 0x0000 0x5 0x0 -#define MX7D_PAD_ENET1_RGMII_TD0__KPP_ROW0 0x0244 0x04B4 0x0614 0x6 0x1 -#define MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x0248 0x04B8 0x0000 0x0 0x0 -#define MX7D_PAD_ENET1_RGMII_TD1__PWM4_OUT 0x0248 0x04B8 0x0000 0x1 0x0 -#define MX7D_PAD_ENET1_RGMII_TD1__ECSPI2_RDY 0x0248 0x04B8 0x0000 0x2 0x0 -#define MX7D_PAD_ENET1_RGMII_TD1__EPDC_SDCE9 0x0248 0x04B8 0x0000 0x4 0x0 -#define MX7D_PAD_ENET1_RGMII_TD1__GPIO7_IO7 0x0248 0x04B8 0x0000 0x5 0x0 -#define MX7D_PAD_ENET1_RGMII_TD1__KPP_COL0 0x0248 0x04B8 0x05F4 0x6 0x1 -#define MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x024C 0x04BC 0x0000 0x0 0x0 -#define MX7D_PAD_ENET1_RGMII_TD2__FLEXCAN2_RX 0x024C 0x04BC 0x04E0 0x1 0x4 -#define MX7D_PAD_ENET1_RGMII_TD2__ECSPI2_MISO 0x024C 0x04BC 0x0538 0x2 0x1 -#define MX7D_PAD_ENET1_RGMII_TD2__I2C4_SCL 0x024C 0x04BC 0x05EC 0x3 0x4 -#define MX7D_PAD_ENET1_RGMII_TD2__EPDC_SDOED 0x024C 0x04BC 0x0000 0x4 0x0 -#define MX7D_PAD_ENET1_RGMII_TD2__GPIO7_IO8 0x024C 0x04BC 0x0000 0x5 0x0 -#define MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x0250 0x04C0 0x0000 0x0 0x0 -#define MX7D_PAD_ENET1_RGMII_TD3__FLEXCAN2_TX 0x0250 0x04C0 0x0000 0x1 0x0 -#define MX7D_PAD_ENET1_RGMII_TD3__ECSPI2_SS0 0x0250 0x04C0 0x0540 0x2 0x1 -#define MX7D_PAD_ENET1_RGMII_TD3__I2C4_SDA 0x0250 0x04C0 0x05F0 0x3 0x4 -#define MX7D_PAD_ENET1_RGMII_TD3__EPDC_SDOEZ 0x0250 0x04C0 0x0000 0x4 0x0 -#define MX7D_PAD_ENET1_RGMII_TD3__GPIO7_IO9 0x0250 0x04C0 0x0000 0x5 0x0 -#define MX7D_PAD_ENET1_RGMII_TD3__CAAM_RNG_OSC_OBS 0x0250 0x04C0 0x0000 0x7 0x0 -#define MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x0254 0x04C4 0x0000 0x0 0x0 -#define MX7D_PAD_ENET1_RGMII_TX_CTL__SAI1_RX_SYNC 0x0254 0x04C4 0x06A4 0x2 0x1 -#define MX7D_PAD_ENET1_RGMII_TX_CTL__GPT2_COMPARE1 0x0254 0x04C4 0x0000 0x3 0x0 -#define MX7D_PAD_ENET1_RGMII_TX_CTL__EPDC_PWR_CTRL2 0x0254 0x04C4 0x0000 0x4 0x0 -#define MX7D_PAD_ENET1_RGMII_TX_CTL__GPIO7_IO10 0x0254 0x04C4 0x0000 0x5 0x0 -#define MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x0258 0x04C8 0x0000 0x0 0x0 -#define MX7D_PAD_ENET1_RGMII_TXC__ENET1_TX_ER 0x0258 0x04C8 0x0000 0x1 0x0 -#define MX7D_PAD_ENET1_RGMII_TXC__SAI1_RX_BCLK 0x0258 0x04C8 0x069C 0x2 0x1 -#define MX7D_PAD_ENET1_RGMII_TXC__GPT2_COMPARE2 0x0258 0x04C8 0x0000 0x3 0x0 -#define MX7D_PAD_ENET1_RGMII_TXC__EPDC_PWR_CTRL3 0x0258 0x04C8 0x0000 0x4 0x0 -#define MX7D_PAD_ENET1_RGMII_TXC__GPIO7_IO11 0x0258 0x04C8 0x0000 0x5 0x0 -#define MX7D_PAD_ENET1_TX_CLK__ENET1_TX_CLK 0x025C 0x04CC 0x0000 0x0 0x0 -#define MX7D_PAD_ENET1_TX_CLK__CCM_ENET_REF_CLK1 0x025C 0x04CC 0x0564 0x1 0x2 -#define MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0 0x025C 0x04CC 0x06A0 0x2 0x1 -#define MX7D_PAD_ENET1_TX_CLK__GPT2_COMPARE3 0x025C 0x04CC 0x0000 0x3 0x0 -#define MX7D_PAD_ENET1_TX_CLK__EPDC_PWR_IRQ 0x025C 0x04CC 0x057C 0x4 0x1 -#define MX7D_PAD_ENET1_TX_CLK__GPIO7_IO12 0x025C 0x04CC 0x0000 0x5 0x0 -#define MX7D_PAD_ENET1_TX_CLK__CCM_EXT_CLK1 0x025C 0x04CC 0x04E4 0x6 0x2 -#define MX7D_PAD_ENET1_TX_CLK__CSU_ALARM_AUT0 0x025C 0x04CC 0x0000 0x7 0x0 -#define MX7D_PAD_ENET1_RX_CLK__ENET1_RX_CLK 0x0260 0x04D0 0x056C 0x0 0x0 -#define MX7D_PAD_ENET1_RX_CLK__WDOG2_WDOG_B 0x0260 0x04D0 0x0000 0x1 0x0 -#define MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK 0x0260 0x04D0 0x06A8 0x2 0x1 -#define MX7D_PAD_ENET1_RX_CLK__GPT2_CLK 0x0260 0x04D0 0x0000 0x3 0x0 -#define MX7D_PAD_ENET1_RX_CLK__EPDC_PWR_WAKE 0x0260 0x04D0 0x0000 0x4 0x0 -#define MX7D_PAD_ENET1_RX_CLK__GPIO7_IO13 0x0260 0x04D0 0x0000 0x5 0x0 -#define MX7D_PAD_ENET1_RX_CLK__CCM_EXT_CLK2 0x0260 0x04D0 0x04E8 0x6 0x2 -#define MX7D_PAD_ENET1_RX_CLK__CSU_ALARM_AUT1 0x0260 0x04D0 0x0000 0x7 0x0 -#define MX7D_PAD_ENET1_CRS__ENET1_CRS 0x0264 0x04D4 0x0000 0x0 0x0 -#define MX7D_PAD_ENET1_CRS__WDOG2_WDOG_RST_B_DEB 0x0264 0x04D4 0x0000 0x1 0x0 -#define MX7D_PAD_ENET1_CRS__SAI1_TX_SYNC 0x0264 0x04D4 0x06AC 0x2 0x1 -#define MX7D_PAD_ENET1_CRS__GPT2_CAPTURE1 0x0264 0x04D4 0x0000 0x3 0x0 -#define MX7D_PAD_ENET1_CRS__EPDC_PWR_CTRL0 0x0264 0x04D4 0x0000 0x4 0x0 -#define MX7D_PAD_ENET1_CRS__GPIO7_IO14 0x0264 0x04D4 0x0000 0x5 0x0 -#define MX7D_PAD_ENET1_CRS__CCM_EXT_CLK3 0x0264 0x04D4 0x04EC 0x6 0x2 -#define MX7D_PAD_ENET1_CRS__CSU_ALARM_AUT2 0x0264 0x04D4 0x0000 0x7 0x0 -#define MX7D_PAD_ENET1_COL__ENET1_COL 0x0268 0x04D8 0x0000 0x0 0x0 -#define MX7D_PAD_ENET1_COL__WDOG1_WDOG_ANY 0x0268 0x04D8 0x0000 0x1 0x0 -#define MX7D_PAD_ENET1_COL__SAI1_TX_DATA0 0x0268 0x04D8 0x0000 0x2 0x0 -#define MX7D_PAD_ENET1_COL__GPT2_CAPTURE2 0x0268 0x04D8 0x0000 0x3 0x0 -#define MX7D_PAD_ENET1_COL__EPDC_PWR_CTRL1 0x0268 0x04D8 0x0000 0x4 0x0 -#define MX7D_PAD_ENET1_COL__GPIO7_IO15 0x0268 0x04D8 0x0000 0x5 0x0 -#define MX7D_PAD_ENET1_COL__CCM_EXT_CLK4 0x0268 0x04D8 0x04F0 0x6 0x2 -#define MX7D_PAD_ENET1_COL__CSU_INT_DEB 0x0268 0x04D8 0x0000 0x7 0x0 - -#endif /* __DTS_IMX7D_PINFUNC_H */ diff --git a/sys/gnu/dts/arm/imx7d-sbc-imx7.dts b/sys/gnu/dts/arm/imx7d-sbc-imx7.dts deleted file mode 100644 index f8a86855270..00000000000 --- a/sys/gnu/dts/arm/imx7d-sbc-imx7.dts +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Support for CompuLab SBC-iMX7 Single Board Computer - * - * Copyright (C) 2015 CompuLab Ltd. - http://www.compulab.co.il/ - * Author: Ilya Ledvich - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - */ - -#include "imx7d-cl-som-imx7.dts" - -/ { - model = "CompuLab SBC-iMX7"; - compatible = "compulab,sbc-imx7", "compulab,cl-som-imx7", "fsl,imx7d"; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; - wakeup-source; - status = "okay"; -}; - -&iomuxc { - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX7D_PAD_SD1_CMD__SD1_CMD 0x59 - MX7D_PAD_SD1_CLK__SD1_CLK 0x19 - MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 - MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 - MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 - MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 - MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */ - MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */ - >; - }; -}; diff --git a/sys/gnu/dts/arm/imx7d-sdb-reva.dts b/sys/gnu/dts/arm/imx7d-sdb-reva.dts deleted file mode 100644 index cabdaa6dc51..00000000000 --- a/sys/gnu/dts/arm/imx7d-sdb-reva.dts +++ /dev/null @@ -1,43 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -// -// Copyright (C) 2015 Freescale Semiconductor, Inc. - -/dts-v1/; - -#include "imx7d-sdb.dts" - -/ { - model = "Freescale i.MX7 SabreSD RevA Board"; - compatible = "fsl,imx7d-sdb-reva", "fsl,imx7d"; - - reg_usb_otg2_vbus: regulator-usb-otg2-vbus { - pinctrl-0 = <&pinctrl_usb_otg2_vbus_reg_reva>; - gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>; - }; -}; - -&fec2 { - /delete-property/phy-supply; -}; - -&iomuxc { - imx7d-sdb { - pinctrl_tsc2046_pendown: tsc2046_pendown { - fsl,pins = < - MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x59 - >; - }; - - pinctrl_hog: hoggrp { - fsl,pins = < - MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x34 /* bt reg on */ - >; - }; - - pinctrl_usb_otg2_vbus_reg_reva: usbotg2vbusregrevagrp { - fsl,pins = < - MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x14 - >; - }; - }; -}; diff --git a/sys/gnu/dts/arm/imx7d-sdb-sht11.dts b/sys/gnu/dts/arm/imx7d-sdb-sht11.dts deleted file mode 100644 index 996555596d4..00000000000 --- a/sys/gnu/dts/arm/imx7d-sdb-sht11.dts +++ /dev/null @@ -1,36 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -// -// Copyright (C) 2015 Freescale Semiconductor, Inc. - -#include "imx7d-sdb.dts" - -/ { - sensor { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sensor>; - compatible = "sensirion,sht15"; - clk-gpios = <&gpio4 12 0>; - data-gpios = <&gpio4 13 0>; - vcc-supply = <®_sht15>; - }; - - reg_sht15: regulator-sht15 { - compatible = "regulator-fixed"; - regulator-name = "reg_sht15"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&i2c3 { - status = "disabled"; -}; - -&iomuxc { - pinctrl_sensor: sensorgrp { - fsl,pins = < - MX7D_PAD_I2C3_SDA__GPIO4_IO13 0x4000007f - MX7D_PAD_I2C3_SCL__GPIO4_IO12 0x4000007f - >; - }; -}; diff --git a/sys/gnu/dts/arm/imx7d-sdb.dts b/sys/gnu/dts/arm/imx7d-sdb.dts deleted file mode 100644 index 869efbc4af4..00000000000 --- a/sys/gnu/dts/arm/imx7d-sdb.dts +++ /dev/null @@ -1,775 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -// -// Copyright (C) 2015 Freescale Semiconductor, Inc. - -/dts-v1/; - -#include "imx7d.dtsi" - -/ { - model = "Freescale i.MX7 SabreSD Board"; - compatible = "fsl,imx7d-sdb", "fsl,imx7d"; - - chosen { - stdout-path = &uart1; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x80000000>; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_keys>; - - volume-up { - label = "Volume Up"; - gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - - volume-down { - label = "Volume Down"; - gpios = <&gpio5 10 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - }; - - spi4 { - compatible = "spi-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi4>; - gpio-sck = <&gpio1 13 GPIO_ACTIVE_HIGH>; - gpio-mosi = <&gpio1 9 GPIO_ACTIVE_HIGH>; - cs-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; - num-chipselects = <1>; - #address-cells = <1>; - #size-cells = <0>; - - extended_io: gpio-expander@0 { - compatible = "fairchild,74hc595"; - gpio-controller; - #gpio-cells = <2>; - reg = <0>; - registers-number = <1>; - spi-max-frequency = <100000>; - }; - }; - - reg_usb_otg1_vbus: regulator-usb-otg1-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usb_otg2_vbus: regulator-usb-otg2-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg2_vbus"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_otg2_vbus_reg>; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_vref_1v8: regulator-vref-1v8 { - compatible = "regulator-fixed"; - regulator-name = "vref-1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - reg_brcm: regulator-brcm { - compatible = "regulator-fixed"; - gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-name = "brcm_reg"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_brcm_reg>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <200000>; - }; - - reg_lcd_3v3: regulator-lcd-3v3 { - compatible = "regulator-fixed"; - regulator-name = "lcd-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&extended_io 7 GPIO_ACTIVE_LOW>; - }; - - reg_can2_3v3: regulator-can2-3v3 { - compatible = "regulator-fixed"; - regulator-name = "can2-3v3"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2_reg>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 14 GPIO_ACTIVE_LOW>; - }; - - reg_fec2_3v3: regulator-fec2-3v3 { - compatible = "regulator-fixed"; - regulator-name = "fec2-3v3"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet2_reg>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio1 4 GPIO_ACTIVE_LOW>; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 5000000 0>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - status = "okay"; - }; - - panel { - compatible = "innolux,at043tn24"; - backlight = <&backlight>; - power-supply = <®_lcd_3v3>; - - port { - panel_in: endpoint { - remote-endpoint = <&display_out>; - }; - }; - }; -}; - -&adc1 { - vref-supply = <®_vref_1v8>; - status = "okay"; -}; - -&adc2 { - vref-supply = <®_vref_1v8>; - status = "okay"; -}; - -&cpu0 { - cpu-supply = <&sw1a_reg>; -}; - -&ecspi3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi3>; - cs-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; - status = "okay"; - - tsc2046@0 { - compatible = "ti,tsc2046"; - reg = <0>; - spi-max-frequency = <1000000>; - pinctrl-names ="default"; - pinctrl-0 = <&pinctrl_tsc2046_pendown>; - interrupt-parent = <&gpio2>; - interrupts = <29 0>; - pendown-gpio = <&gpio2 29 GPIO_ACTIVE_HIGH>; - ti,x-min = /bits/ 16 <0>; - ti,x-max = /bits/ 16 <0>; - ti,y-min = /bits/ 16 <0>; - ti,y-max = /bits/ 16 <0>; - ti,pressure-max = /bits/ 16 <0>; - ti,x-plate-ohms = /bits/ 16 <400>; - wakeup-source; - }; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet1>; - assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>, - <&clks IMX7D_ENET1_TIME_ROOT_CLK>; - assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; - assigned-clock-rates = <0>, <100000000>; - phy-mode = "rgmii"; - phy-handle = <ðphy0>; - fsl,magic-packet; - phy-reset-gpios = <&extended_io 5 GPIO_ACTIVE_LOW>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; - - ethphy1: ethernet-phy@1 { - reg = <1>; - }; - }; -}; - -&fec2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet2>; - assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>, - <&clks IMX7D_ENET2_TIME_ROOT_CLK>; - assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; - assigned-clock-rates = <0>, <100000000>; - phy-mode = "rgmii"; - phy-handle = <ðphy1>; - phy-supply = <®_fec2_3v3>; - fsl,magic-packet; - status = "okay"; -}; - -&flexcan2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - xceiver-supply = <®_can2_3v3>; - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pmic: pfuze3000@8 { - compatible = "fsl,pfuze3000"; - reg = <0x08>; - - regulators { - sw1a_reg: sw1a { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1475000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - /* use sw1c_reg to align with pfuze100/pfuze200 */ - sw1c_reg: sw1b { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1475000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3a_reg: sw3 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1650000>; - regulator-boot-on; - regulator-always-on; - }; - - swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - }; - - snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - vgen1_reg: vldo1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen2_reg: vldo2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen3_reg: vccsd { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen4_reg: v33 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen5_reg: vldo3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen6_reg: vldo4 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - }; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - mpl3115@60 { - compatible = "fsl,mpl3115"; - reg = <0x60>; - }; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; -}; - -&i2c4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4>; - status = "okay"; - - codec: wm8960@1a { - compatible = "wlf,wm8960"; - reg = <0x1a>; - clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; - clock-names = "mclk"; - wlf,shared-lrclk; - }; -}; - -&lcdif { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcdif>; - status = "okay"; - - port { - display_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; -}; - -&pcie { - reset-gpio = <&extended_io 1 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -®_1p0d { - vin-supply = <&sw2_reg>; -}; - -®_1p2 { - vin-supply = <&sw2_reg>; -}; - -&snvs_pwrkey { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>; - assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; - status = "okay"; -}; - -&uart6 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart6>; - assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>; - assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; - uart-has-rtscts; - status = "okay"; -}; - -&usbotg1 { - vbus-supply = <®_usb_otg1_vbus>; - status = "okay"; -}; - -&usbotg2 { - vbus-supply = <®_usb_otg2_vbus>; - dr_mode = "host"; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; - wakeup-source; - keep-power-in-suspend; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>; - wakeup-source; - keep-power-in-suspend; - non-removable; - vmmc-supply = <®_brcm>; - fsl,tuning-step = <2>; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>; - assigned-clock-rates = <400000000>; - bus-width = <8>; - fsl,tuning-step = <2>; - non-removable; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - imx7d-sdb { - pinctrl_brcm_reg: brcmreggrp { - fsl,pins = < - MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x14 - >; - }; - - pinctrl_ecspi3: ecspi3grp { - fsl,pins = < - MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO 0x2 - MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI 0x2 - MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK 0x2 - MX7D_PAD_SD2_CD_B__GPIO5_IO9 0x59 - >; - }; - - pinctrl_enet1: enet1grp { - fsl,pins = < - MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x3 - MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x3 - MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1 - MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1 - MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1 - MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1 - MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1 - MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1 - MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1 - MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1 - MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1 - MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1 - MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1 - MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1 - >; - }; - - pinctrl_enet2: enet2grp { - fsl,pins = < - MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x1 - MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x1 - MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x1 - MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x1 - MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x1 - MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x1 - MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x1 - MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x1 - MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x1 - MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x1 - MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x1 - MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x1 - >; - }; - - pinctrl_enet2_reg: enet2reggrp { - fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4 0x14 - >; - }; - - pinctrl_flexcan2: flexcan2grp { - fsl,pins = < - MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x59 - MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x59 - >; - }; - - pinctrl_flexcan2_reg: flexcan2reggrp { - fsl,pins = < - MX7D_PAD_EPDC_DATA14__GPIO2_IO14 0x59 /* CAN_STBY */ - >; - }; - - pinctrl_gpio_keys: gpio_keysgrp { - fsl,pins = < - MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x59 - MX7D_PAD_SD2_WP__GPIO5_IO10 0x59 - >; - }; - - pinctrl_hog: hoggrp { - fsl,pins = < - MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x34 /* bt reg on */ - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f - MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f - MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f - MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f - >; - }; - - pinctrl_i2c4: i2c4grp { - fsl,pins = < - MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA 0x4000007f - MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL 0x4000007f - >; - }; - - pinctrl_lcdif: lcdifgrp { - fsl,pins = < - MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79 - MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79 - MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79 - MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79 - MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79 - MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79 - MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79 - MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79 - MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79 - MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79 - MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79 - MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79 - MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79 - MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79 - MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79 - MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79 - MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79 - MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79 - MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79 - MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79 - MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79 - MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79 - MX7D_PAD_LCD_DATA22__LCD_DATA22 0x79 - MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79 - MX7D_PAD_LCD_CLK__LCD_CLK 0x79 - MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x79 - MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x79 - MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x79 - MX7D_PAD_LCD_RESET__LCD_RESET 0x79 - >; - }; - - pinctrl_spi4: spi4grp { - fsl,pins = < - MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x59 - MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x59 - MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x59 - >; - }; - - pinctrl_tsc2046_pendown: tsc2046_pendown { - fsl,pins = < - MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x59 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79 - MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX7D_PAD_SAI1_TX_BCLK__UART5_DCE_TX 0x79 - MX7D_PAD_SAI1_RX_DATA__UART5_DCE_RX 0x79 - MX7D_PAD_SAI1_TX_SYNC__UART5_DCE_CTS 0x79 - MX7D_PAD_SAI1_TX_DATA__UART5_DCE_RTS 0x79 - >; - }; - - pinctrl_uart6: uart6grp { - fsl,pins = < - MX7D_PAD_ECSPI1_MOSI__UART6_DCE_TX 0x79 - MX7D_PAD_ECSPI1_SCLK__UART6_DCE_RX 0x79 - MX7D_PAD_ECSPI1_SS0__UART6_DCE_CTS 0x79 - MX7D_PAD_ECSPI1_MISO__UART6_DCE_RTS 0x79 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX7D_PAD_SD1_CMD__SD1_CMD 0x59 - MX7D_PAD_SD1_CLK__SD1_CLK 0x19 - MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 - MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 - MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 - MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 - MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */ - MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */ - MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 /* vmmc */ - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX7D_PAD_SD2_CMD__SD2_CMD 0x59 - MX7D_PAD_SD2_CLK__SD2_CLK 0x19 - MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59 - MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59 - MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59 - MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2grp_100mhz { - fsl,pins = < - MX7D_PAD_SD2_CMD__SD2_CMD 0x5a - MX7D_PAD_SD2_CLK__SD2_CLK 0x1a - MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5a - MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5a - MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5a - MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5a - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2grp_200mhz { - fsl,pins = < - MX7D_PAD_SD2_CMD__SD2_CMD 0x5b - MX7D_PAD_SD2_CLK__SD2_CLK 0x1b - MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5b - MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5b - MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5b - MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5b - >; - }; - - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX7D_PAD_SD3_CMD__SD3_CMD 0x59 - MX7D_PAD_SD3_CLK__SD3_CLK 0x19 - MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 - MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 - MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 - MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 - MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 - MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 - MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 - MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 - MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { - fsl,pins = < - MX7D_PAD_SD3_CMD__SD3_CMD 0x5a - MX7D_PAD_SD3_CLK__SD3_CLK 0x1a - MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a - MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a - MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a - MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a - MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a - MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a - MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a - MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a - MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3grp_200mhz { - fsl,pins = < - MX7D_PAD_SD3_CMD__SD3_CMD 0x5b - MX7D_PAD_SD3_CLK__SD3_CLK 0x1b - MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b - MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b - MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b - MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b - MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b - MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b - MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b - MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b - MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1b - >; - }; - }; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "okay"; -}; - -&iomuxc_lpsr { - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74 - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x30 - >; - }; - - pinctrl_usb_otg2_vbus_reg: usbotg2vbusreggrp { - fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x14 - >; - }; -}; diff --git a/sys/gnu/dts/arm/imx7d-tqma7.dtsi b/sys/gnu/dts/arm/imx7d-tqma7.dtsi deleted file mode 100644 index 8ad3048dac0..00000000000 --- a/sys/gnu/dts/arm/imx7d-tqma7.dtsi +++ /dev/null @@ -1,11 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR X11 -/* - * Device Tree Include file for TQ Systems TQMa7D board with NXP i.MX7Dual SoC. - * - * Copyright (C) 2016 TQ Systems GmbH - * Author: Markus Niebel - * Copyright (C) 2019 Bruno Thomsen - */ - -#include "imx7d.dtsi" -#include "imx7-tqma7.dtsi" diff --git a/sys/gnu/dts/arm/imx7d-zii-rmu2.dts b/sys/gnu/dts/arm/imx7d-zii-rmu2.dts deleted file mode 100644 index 2b8d6cc45a5..00000000000 --- a/sys/gnu/dts/arm/imx7d-zii-rmu2.dts +++ /dev/null @@ -1,357 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Device tree file for ZII's RMU2 board - * - * RMU - Remote Modem Unit - * - * Copyright (C) 2019 Zodiac Inflight Innovations - */ - -/dts-v1/; -#include -#include "imx7d.dtsi" - -/ { - model = "ZII RMU2 Board"; - compatible = "zii,imx7d-rmu2", "fsl,imx7d"; - - chosen { - stdout-path = &uart2; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pinctrl_leds_debug>; - pinctrl-names = "default"; - - debug { - label = "zii:green:debug1"; - gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; -}; - -&cpu0 { - arm-supply = <&sw1a_reg>; -}; - -&ecspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - cs-gpios = <&gpio4 19 GPIO_ACTIVE_HIGH>; - status = "okay"; - - flash@0 { - compatible = "jedec,spi-nor"; - spi-max-frequency = <20000000>; - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; - }; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet1>; - assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>, - <&clks IMX7D_ENET1_TIME_ROOT_CLK>; - assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; - assigned-clock-rates = <0>, <100000000>; - phy-mode = "rgmii"; - phy-handle = <&fec1_phy>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - fec1_phy: ethernet-phy@0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet1_phy_reset>, - <&pinctrl_enet1_phy_interrupt>; - reg = <0>; - interrupt-parent = <&gpio1>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - reset-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pmic@8 { - compatible = "fsl,pfuze3000"; - reg = <0x08>; - - regulators { - sw1a_reg: sw1a { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw1c_reg: sw1b { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1475000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1850000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3a_reg: sw3 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1650000>; - regulator-boot-on; - regulator-always-on; - }; - - swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - }; - - snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - vgen1_reg: vldo1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen2_reg: vldo2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - regulator-always-on; - }; - - vgen3_reg: vccsd { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen4_reg: v33 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen5_reg: vldo3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen6_reg: vldo4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; - - eeprom@50 { - compatible = "atmel,24c04"; - reg = <0x50>; - }; - - eeprom@52 { - compatible = "atmel,24c04"; - reg = <0x52>; - }; -}; - -&snvs_rtc { - status = "disabled"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - assigned-clocks = <&clks IMX7D_UART2_ROOT_SRC>; - assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - assigned-clocks = <&clks IMX7D_UART4_ROOT_SRC>; - assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; - status = "okay"; - - rave-sp { - compatible = "zii,rave-sp-rdu2"; - current-speed = <1000000>; - #address-cells = <1>; - #size-cells = <1>; - - watchdog { - compatible = "zii,rave-sp-watchdog"; - }; - - eeprom@a3 { - compatible = "zii,rave-sp-eeprom"; - reg = <0xa3 0x4000>; - #address-cells = <1>; - #size-cells = <1>; - zii,eeprom-name = "main-eeprom"; - }; - }; -}; - -&usbotg2 { - dr_mode = "host"; - disable-over-current; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - bus-width = <4>; - no-1-8-v; - no-sdio; - keep-power-in-suspend; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - bus-width = <8>; - no-1-8-v; - non-removable; - no-sdio; - no-sd; - keep-power-in-suspend; - status = "okay"; -}; - -&wdog1 { - status = "disabled"; -}; - -&iomuxc { - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x2 - MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x2 - MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO 0x2 - MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 0x59 - >; - }; - - pinctrl_enet1: enet1grp { - fsl,pins = < - MX7D_PAD_SD2_CD_B__ENET1_MDIO 0x3 - MX7D_PAD_SD2_WP__ENET1_MDC 0x3 - MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1 - MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1 - MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1 - MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1 - MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1 - MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1 - MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1 - MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1 - MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1 - MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1 - MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1 - MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1 - >; - }; - - pinctrl_enet1_phy_reset: enet1phyresetgrp { - fsl,pins = < - MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x14 - - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f - MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f - >; - }; - - pinctrl_leds_debug: ledsgrp { - fsl,pins = < - MX7D_PAD_EPDC_DATA08__GPIO2_IO8 0x59 - >; - }; - - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX 0x79 - MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX 0x79 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX7D_PAD_SD2_DATA0__UART4_DCE_RX 0x79 - MX7D_PAD_SD2_DATA1__UART4_DCE_TX 0x79 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX7D_PAD_SD1_CMD__SD1_CMD 0x59 - MX7D_PAD_SD1_CLK__SD1_CLK 0x19 - MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 - MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 - MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 - MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX7D_PAD_SD3_CMD__SD3_CMD 0x59 - MX7D_PAD_SD3_CLK__SD3_CLK 0x19 - MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 - MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 - MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 - MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 - MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 - MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 - MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 - MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 - MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x59 - >; - }; -}; - -&iomuxc_lpsr { - pinctrl_enet1_phy_interrupt: enet1phyinterruptgrp { - fsl,phy = < - MX7D_PAD_LPSR_GPIO1_IO02__GPIO1_IO2 0x08 - >; - }; -}; diff --git a/sys/gnu/dts/arm/imx7d-zii-rpu2.dts b/sys/gnu/dts/arm/imx7d-zii-rpu2.dts deleted file mode 100644 index 39812c92bf0..00000000000 --- a/sys/gnu/dts/arm/imx7d-zii-rpu2.dts +++ /dev/null @@ -1,923 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Device tree file for ZII's RPU2 board - * - * RPU - Remote Peripheral Unit - * - * Copyright (C) 2019 Zodiac Inflight Innovations - */ - -/dts-v1/; -#include -#include "imx7d.dtsi" - -/ { - model = "ZII RPU2 Board"; - compatible = "zii,imx7d-rpu2", "fsl,imx7d"; - - chosen { - stdout-path = &uart2; - }; - - cs2000_ref: oscillator { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24576000>; - }; - - cs2000_in_dummy: dummy-oscillator { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pinctrl_leds_debug>; - pinctrl-names = "default"; - - debug { - label = "zii:green:debug1"; - gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - iio-hwmon { - compatible = "iio-hwmon"; - io-channels = <&adc1 0>, <&adc1 1>, <&adc1 2>, <&adc1 3>, - <&adc2 1>; - }; - - reg_can1_stby: regulator-can1-stby { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1_stby>; - regulator-name = "can1-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_can2_stby: regulator-can2-stby { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2_stby>; - regulator-name = "can2-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_vref_1v8: regulator-vref-1v8 { - compatible = "regulator-fixed"; - regulator-name = "vref-1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "GEN_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_5p0v_main: regulator-5p0v-main { - compatible = "regulator-fixed"; - regulator-name = "5V_MAIN"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - sound1 { - compatible = "simple-audio-card"; - simple-audio-card,name = "Audio Output 1"; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&sound1_codec>; - simple-audio-card,frame-master = <&sound1_codec>; - simple-audio-card,widgets = - "Headphone", "Headphone Jack"; - simple-audio-card,routing = - "Headphone Jack", "HPLEFT", - "Headphone Jack", "HPRIGHT", - "LEFTIN", "HPL", - "RIGHTIN", "HPR"; - simple-audio-card,aux-devs = <&hpa1>; - - simple-audio-card,cpu { - sound-dai = <&sai1>; - }; - - sound1_codec: simple-audio-card,codec { - sound-dai = <&codec1>; - clocks = <&cs2000>; - }; - }; - - sound2 { - compatible = "simple-audio-card"; - simple-audio-card,name = "Audio Output 2"; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&sound2_codec>; - simple-audio-card,frame-master = <&sound2_codec>; - simple-audio-card,widgets = - "Headphone", "Headphone Jack"; - simple-audio-card,routing = - "Headphone Jack", "HPLEFT", - "Headphone Jack", "HPRIGHT", - "LEFTIN", "HPL", - "RIGHTIN", "HPR"; - simple-audio-card,aux-devs = <&hpa2>; - - simple-audio-card,cpu { - sound-dai = <&sai2>; - }; - - sound2_codec: simple-audio-card,codec { - sound-dai = <&codec2>; - clocks = <&cs2000>; - }; - }; - - sound3 { - compatible = "simple-audio-card"; - simple-audio-card,name = "Audio Output 3"; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&sound3_codec>; - simple-audio-card,frame-master = <&sound3_codec>; - simple-audio-card,widgets = - "Headphone", "Headphone Jack"; - simple-audio-card,routing = - "Headphone Jack", "HPLEFT", - "Headphone Jack", "HPRIGHT", - "LEFTIN", "HPL", - "RIGHTIN", "HPR"; - simple-audio-card,aux-devs = <&hpa3>; - - simple-audio-card,cpu { - sound-dai = <&sai3>; - }; - - sound3_codec: simple-audio-card,codec { - sound-dai = <&codec3>; - clocks = <&cs2000>; - }; - }; -}; - -&adc1 { - vref-supply = <®_vref_1v8>; - status = "okay"; -}; - -&adc2 { - vref-supply = <®_vref_1v8>; - status = "okay"; -}; - -&cpu0 { - arm-supply = <&sw1a_reg>; -}; - -&clks { - assigned-clocks = <&clks IMX7D_PLL_AUDIO_POST_DIV>; - assigned-clock-rates = <884736000>; -}; - -&ecspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - cs-gpios = <&gpio4 19 GPIO_ACTIVE_HIGH>; - status = "okay"; - - flash@0 { - compatible = "jedec,spi-nor"; - spi-max-frequency = <20000000>; - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; - }; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet1>; - assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>, - <&clks IMX7D_ENET1_TIME_ROOT_CLK>; - assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; - assigned-clock-rates = <0>, <100000000>; - phy-mode = "rgmii"; - status = "okay"; - - fixed-link { - speed = <1000>; - full-duplex; - }; - - mdio1: mdio { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - switch: switch@0 { - compatible = "marvell,mv88e6085"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_switch>; - reg = <0>; - eeprom-length = <512>; - interrupt-parent = <&gpio1>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells = <2>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "eth_cu_1000_1"; - }; - - port@1 { - reg = <1>; - label = "eth_cu_1000_2"; - }; - - port@2 { - reg = <2>; - label = "pic"; - - fixed-link { - speed = <100>; - full-duplex; - }; - }; - - port@5 { - reg = <5>; - label = "cpu"; - ethernet = <&fec1>; - phy-mode = "rgmii-id"; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - - port@6 { - reg = <6>; - label = "gigabit_proc"; - ethernet = <&fec2>; - phy-mode = "rgmii-id"; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; - }; - }; -}; - -&fec2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet2>; - assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>, - <&clks IMX7D_ENET2_TIME_ROOT_CLK>; - assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; - assigned-clock-rates = <0>, <100000000>; - phy-mode = "rgmii"; - fsl,magic-packet; - status = "okay"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&flexcan1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - xceiver-supply = <®_can1_stby>; - status = "okay"; -}; - -&flexcan2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - xceiver-supply = <®_can2_stby>; - status = "okay"; -}; - -&gpio1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio1>; - - gpio-line-names = "", "", "", "", "", "", "", "", - "", "", - "usb_1_en_b", - "usb_2_en_b", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", ""; -}; - -&gpio2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio2>; - - gpio-line-names = "12v_out_en_1", - "12v_out_en_2", - "12v_out_en_3", - "28v_out_en_5", - "28v_out_en_1", - "28v_out_en_2", - "28v_out_en_3", - "28v_out_en_4", - "", "", - "usb_3_en_b", - "usb_4_en_b", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", ""; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pmic: pmic@8 { - compatible = "fsl,pfuze3000"; - reg = <0x08>; - - regulators { - sw1a_reg: sw1a { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw1c_reg: sw1b { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1475000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1850000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3a_reg: sw3 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1650000>; - regulator-boot-on; - regulator-always-on; - }; - - swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - }; - - snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - vgen1_reg: vldo1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen2_reg: vldo2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - regulator-always-on; - }; - - vgen3_reg: vccsd { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen4_reg: v33 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen5_reg: vldo3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen6_reg: vldo4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; - - cs2000: clkgen@4e { - compatible = "cirrus,cs2000-cp"; - reg = <0x4e>; - #clock-cells = <0>; - clock-names = "clk_in", "ref_clk"; - clocks = <&cs2000_in_dummy>, <&cs2000_ref>; - assigned-clocks = <&cs2000>; - assigned-clock-rates = <24000000>; - }; - - eeprom@50 { - compatible = "atmel,24c04"; - reg = <0x50>; - }; - - eeprom@52 { - compatible = "atmel,24c04"; - reg = <0x52>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - codec2: codec@18 { - compatible = "ti,tlv320dac3100"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_codec2>; - reg = <0x18>; - #sound-dai-cells = <0>; - HPVDD-supply = <®_3p3v>; - SPRVDD-supply = <®_3p3v>; - SPLVDD-supply = <®_3p3v>; - AVDD-supply = <®_3p3v>; - IOVDD-supply = <®_3p3v>; - DVDD-supply = <&vgen4_reg>; - gpio-reset = <&gpio1 6 GPIO_ACTIVE_LOW>; - }; - - hpa2: amp@60 { - compatible = "ti,tpa6130a2"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_tpa2>; - reg = <0x60>; - power-gpio = <&gpio3 27 GPIO_ACTIVE_HIGH>; - Vdd-supply = <®_5p0v_main>; - }; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - codec3: codec@18 { - compatible = "ti,tlv320dac3100"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_codec3>; - reg = <0x18>; - #sound-dai-cells = <0>; - HPVDD-supply = <®_3p3v>; - SPRVDD-supply = <®_3p3v>; - SPLVDD-supply = <®_3p3v>; - AVDD-supply = <®_3p3v>; - IOVDD-supply = <®_3p3v>; - DVDD-supply = <&vgen4_reg>; - gpio-reset = <&gpio1 7 GPIO_ACTIVE_LOW>; - }; - - hpa3: amp@60 { - compatible = "ti,tpa6130a2"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_tpa3>; - reg = <0x60>; - power-gpio = <&gpio3 28 GPIO_ACTIVE_HIGH>; - Vdd-supply = <®_5p0v_main>; - }; -}; - -&i2c4 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4>; - status = "okay"; - - codec1: codec@18 { - compatible = "ti,tlv320dac3100"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_codec1>; - reg = <0x18>; - #sound-dai-cells = <0>; - HPVDD-supply = <®_3p3v>; - SPRVDD-supply = <®_3p3v>; - SPLVDD-supply = <®_3p3v>; - AVDD-supply = <®_3p3v>; - IOVDD-supply = <®_3p3v>; - DVDD-supply = <&vgen4_reg>; - gpio-reset = <&gpio1 5 GPIO_ACTIVE_LOW>; - }; - - hpa1: amp@60 { - compatible = "ti,tpa6130a2"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_tpa1>; - reg = <0x60>; - power-gpio = <&gpio3 26 GPIO_ACTIVE_HIGH>; - Vdd-supply = <®_5p0v_main>; - }; -}; - -&sai1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai1>; - assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>, - <&clks IMX7D_SAI1_ROOT_CLK>; - assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; - assigned-clock-rates = <0>, <36864000>; - status = "okay"; -}; - -&sai2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai2>; - assigned-clocks = <&clks IMX7D_SAI2_ROOT_SRC>, - <&clks IMX7D_SAI2_ROOT_CLK>; - assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; - assigned-clock-rates = <0>, <36864000>; - status = "okay"; -}; - -&sai3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai3>; - assigned-clocks = <&clks IMX7D_SAI3_ROOT_SRC>, - <&clks IMX7D_SAI3_ROOT_CLK>; - assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; - assigned-clock-rates = <0>, <36864000>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - assigned-clocks = <&clks IMX7D_UART2_ROOT_SRC>; - assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - assigned-clocks = <&clks IMX7D_UART4_ROOT_SRC>; - assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; - status = "okay"; - - rave-sp { - compatible = "zii,rave-sp-rdu2"; - current-speed = <1000000>; - #address-cells = <1>; - #size-cells = <1>; - - watchdog { - compatible = "zii,rave-sp-watchdog"; - }; - - eeprom@a3 { - compatible = "zii,rave-sp-eeprom"; - reg = <0xa3 0x4000>; - #address-cells = <1>; - #size-cells = <1>; - zii,eeprom-name = "main-eeprom"; - }; - }; -}; - -&usbotg1 { - dr_mode = "host"; - disable-over-current; - status = "okay"; -}; - -&usbotg2 { - dr_mode = "host"; - disable-over-current; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - bus-width = <4>; - no-1-8-v; - no-sdio; - keep-power-in-suspend; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - bus-width = <8>; - no-1-8-v; - non-removable; - no-sdio; - no-sd; - keep-power-in-suspend; - status = "okay"; -}; - -&wdog1 { - status = "disabled"; -}; - -&snvs_rtc { - status = "disabled"; -}; - -&iomuxc { - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x2 - MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x2 - MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO 0x2 - MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 0x59 - >; - }; - - pinctrl_enet1: enet1grp { - fsl,pins = < - MX7D_PAD_SD2_CD_B__ENET1_MDIO 0x3 - MX7D_PAD_SD2_WP__ENET1_MDC 0x3 - MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1 - MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1 - MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1 - MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1 - MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1 - MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1 - MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1 - MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1 - MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1 - MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1 - MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1 - MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1 - >; - }; - - pinctrl_enet2: enet2grp { - fsl,pins = < - MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x1 - MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x1 - MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x1 - MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x1 - MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x1 - MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x1 - MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x1 - MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x1 - MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x1 - MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x1 - MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x1 - MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x1 - MX7D_PAD_UART1_TX_DATA__ENET2_1588_EVENT0_OUT 0x1 - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX7D_PAD_GPIO1_IO12__FLEXCAN1_RX 0x59 - MX7D_PAD_GPIO1_IO13__FLEXCAN1_TX 0x59 - >; - }; - - pinctrl_flexcan1_stby: flexcan1stbygrp { - fsl,pins = < - MX7D_PAD_GPIO1_IO08__GPIO1_IO8 0x59 - >; - }; - - pinctrl_flexcan2: flexcan2grp { - fsl,pins = < - MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x59 - MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x59 - >; - }; - - pinctrl_flexcan2_stby: flexcan2stbygrp { - fsl,pins = < - MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x59 - >; - }; - - pinctrl_gpio1: gpio1grp { - fsl,pins = < - MX7D_PAD_GPIO1_IO10__GPIO1_IO10 0x00 - MX7D_PAD_GPIO1_IO11__GPIO1_IO11 0x00 - >; - }; - - pinctrl_gpio2: gpio2grp { - fsl,pins = < - MX7D_PAD_EPDC_DATA00__GPIO2_IO0 0x00 - MX7D_PAD_EPDC_DATA01__GPIO2_IO1 0x00 - MX7D_PAD_EPDC_DATA02__GPIO2_IO2 0x00 - MX7D_PAD_EPDC_DATA03__GPIO2_IO3 0x03 - MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x03 - MX7D_PAD_EPDC_DATA05__GPIO2_IO5 0x03 - MX7D_PAD_EPDC_DATA06__GPIO2_IO6 0x03 - MX7D_PAD_EPDC_DATA07__GPIO2_IO7 0x03 - MX7D_PAD_EPDC_DATA10__GPIO2_IO10 0x00 - MX7D_PAD_EPDC_DATA11__GPIO2_IO11 0x00 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f - MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f - MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f - MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f - >; - }; - - pinctrl_i2c3_gpio: i2c3gpiogrp { - fsl,pins = < - MX7D_PAD_I2C3_SDA__GPIO4_IO13 0x4000007f - MX7D_PAD_I2C3_SCL__GPIO4_IO12 0x4000007f - >; - }; - - pinctrl_i2c4: i2c4grp { - fsl,pins = < - MX7D_PAD_I2C4_SDA__I2C4_SDA 0x4000007f - MX7D_PAD_I2C4_SCL__I2C4_SCL 0x4000007f - >; - }; - - pinctrl_i2c4_gpio: i2c4gpiogrp { - fsl,pins = < - MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17 0x4000007f - MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 0x4000007f - >; - }; - - pinctrl_leds_debug: debuggrp { - fsl,pins = < - MX7D_PAD_EPDC_DATA08__GPIO2_IO8 0x59 - >; - }; - - pinctrl_sai1: sai1grp { - fsl,pins = < - MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK 0x1f - MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x1f - MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0 0x30 - >; - }; - - pinctrl_sai2: sai2grp { - fsl,pins = < - MX7D_PAD_SAI2_TX_BCLK__SAI2_TX_BCLK 0x1f - MX7D_PAD_SAI2_TX_SYNC__SAI2_TX_SYNC 0x1f - MX7D_PAD_SAI2_TX_DATA__SAI2_TX_DATA0 0x30 - >; - }; - - pinctrl_sai3: sai3grp { - fsl,pins = < - MX7D_PAD_UART3_TX_DATA__SAI3_TX_BCLK 0x1f - MX7D_PAD_UART3_CTS_B__SAI3_TX_SYNC 0x1f - MX7D_PAD_UART3_RTS_B__SAI3_TX_DATA0 0x30 - >; - }; - - pinctrl_tpa1: tpa6130-1grp { - fsl,pins = < - MX7D_PAD_LCD_DATA21__GPIO3_IO26 0x40000038 - >; - }; - - pinctrl_tpa2: tpa6130-2grp { - fsl,pins = < - MX7D_PAD_LCD_DATA22__GPIO3_IO27 0x40000038 - >; - }; - - pinctrl_tpa3: tpa6130-3grp { - fsl,pins = < - MX7D_PAD_LCD_DATA23__GPIO3_IO28 0x40000038 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX 0x79 - MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX 0x79 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX7D_PAD_SD2_DATA0__UART4_DCE_RX 0x79 - MX7D_PAD_SD2_DATA1__UART4_DCE_TX 0x79 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX7D_PAD_SD1_CMD__SD1_CMD 0x59 - MX7D_PAD_SD1_CLK__SD1_CLK 0x19 - MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 - MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 - MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 - MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX7D_PAD_SD3_CMD__SD3_CMD 0x59 - MX7D_PAD_SD3_CLK__SD3_CLK 0x19 - MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 - MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 - MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 - MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 - MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 - MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 - MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 - MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 - MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x59 - >; - }; -}; - -&iomuxc_lpsr { - pinctrl_codec1: dac1grp { - fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x40000038 - >; - }; - - pinctrl_codec2: dac2grp { - fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO06__GPIO1_IO6 0x40000038 - >; - }; - - pinctrl_codec3: dac3grp { - fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x40000038 - >; - }; - - pinctrl_switch: switchgrp { - fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO02__GPIO1_IO2 0x08 - >; - }; -}; diff --git a/sys/gnu/dts/arm/imx7d.dtsi b/sys/gnu/dts/arm/imx7d.dtsi deleted file mode 100644 index 4c22828df55..00000000000 --- a/sys/gnu/dts/arm/imx7d.dtsi +++ /dev/null @@ -1,214 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -// -// Copyright 2015 Freescale Semiconductor, Inc. -// Copyright 2016 Toradex AG - -#include "imx7s.dtsi" -#include - -/ { - cpus { - cpu0: cpu@0 { - clock-frequency = <996000000>; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; - nvmem-cells = <&fuse_grade>; - nvmem-cell-names = "speed_grade"; - }; - - cpu1: cpu@1 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <1>; - clock-frequency = <996000000>; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; - cpu-idle-states = <&cpu_sleep_wait>; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupt-parent = <&intc>; - interrupts = , - , - , - ; - }; - - cpu0_opp_table: opp-table { - compatible = "operating-points-v2"; - opp-shared; - - opp-792000000 { - opp-hz = /bits/ 64 <792000000>; - opp-microvolt = <1000000>; - clock-latency-ns = <150000>; - opp-supported-hw = <0xd>, <0x7>; - opp-suspend; - }; - - opp-996000000 { - opp-hz = /bits/ 64 <996000000>; - opp-microvolt = <1100000>; - clock-latency-ns = <150000>; - opp-supported-hw = <0xc>, <0x7>; - opp-suspend; - }; - - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <1225000>; - clock-latency-ns = <150000>; - opp-supported-hw = <0x8>, <0x3>; - opp-suspend; - }; - }; - - usbphynop2: usbphynop2 { - compatible = "usb-nop-xceiv"; - clocks = <&clks IMX7D_USB_PHY2_CLK>; - clock-names = "main_clk"; - #phy-cells = <0>; - }; - - soc { - etm@3007d000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0x3007d000 0x1000>; - - /* - * System will hang if added nosmp in kernel command line - * without arm,primecell-periphid because amba bus try to - * read id and core1 power off at this time. - */ - arm,primecell-periphid = <0xbb956>; - cpu = <&cpu1>; - clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; - clock-names = "apb_pclk"; - - out-ports { - port { - etm1_out_port: endpoint { - remote-endpoint = <&ca_funnel_in_port1>; - }; - }; - }; - }; - - intc: interrupt-controller@31001000 { - compatible = "arm,cortex-a7-gic"; - interrupts = ; - #interrupt-cells = <3>; - interrupt-controller; - interrupt-parent = <&intc>; - reg = <0x31001000 0x1000>, - <0x31002000 0x2000>, - <0x31004000 0x2000>, - <0x31006000 0x2000>; - }; - }; -}; - -&aips2 { - pcie_phy: pcie-phy@306d0000 { - compatible = "fsl,imx7d-pcie-phy"; - reg = <0x306d0000 0x10000>; - status = "disabled"; - }; -}; - -&aips3 { - usbotg2: usb@30b20000 { - compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; - reg = <0x30b20000 0x200>; - interrupts = ; - clocks = <&clks IMX7D_USB_CTRL_CLK>; - fsl,usbphy = <&usbphynop2>; - fsl,usbmisc = <&usbmisc2 0>; - phy-clkgate-delay-us = <400>; - status = "disabled"; - }; - - usbmisc2: usbmisc@30b20200 { - #index-cells = <1>; - compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; - reg = <0x30b20200 0x200>; - }; - - fec2: ethernet@30bf0000 { - compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec"; - reg = <0x30bf0000 0x10000>; - interrupt-names = "int0", "int1", "int2", "pps"; - interrupts = , - , - , - ; - clocks = <&clks IMX7D_ENET2_IPG_ROOT_CLK>, - <&clks IMX7D_ENET_AXI_ROOT_CLK>, - <&clks IMX7D_ENET2_TIME_ROOT_CLK>, - <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>, - <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>; - clock-names = "ipg", "ahb", "ptp", - "enet_clk_ref", "enet_out"; - fsl,num-tx-queues = <3>; - fsl,num-rx-queues = <3>; - status = "disabled"; - }; - - pcie: pcie@33800000 { - compatible = "fsl,imx7d-pcie", "snps,dw-pcie"; - reg = <0x33800000 0x4000>, - <0x4ff00000 0x80000>; - reg-names = "dbi", "config"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - bus-range = <0x00 0xff>; - ranges = <0x81000000 0 0 0x4ff80000 0 0x00010000 /* downstream I/O */ - 0x82000000 0 0x40000000 0x40000000 0 0x0ff00000>; /* non-prefetchable memory */ - num-lanes = <1>; - num-viewport = <4>; - interrupts = ; - interrupt-names = "msi"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - /* - * Reference manual lists pci irqs incorrectly - * Real hardware ordering is same as imx6: D+MSI, C, B, A - */ - interrupt-map = <0 0 0 1 &intc GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &intc GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX7D_PCIE_CTRL_ROOT_CLK>, - <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>, - <&clks IMX7D_PCIE_PHY_ROOT_CLK>; - clock-names = "pcie", "pcie_bus", "pcie_phy"; - assigned-clocks = <&clks IMX7D_PCIE_CTRL_ROOT_SRC>, - <&clks IMX7D_PCIE_PHY_ROOT_SRC>; - assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_250M_CLK>, - <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; - - fsl,max-link-speed = <2>; - power-domains = <&pgc_pcie_phy>; - resets = <&src IMX7_RESET_PCIEPHY>, - <&src IMX7_RESET_PCIE_CTRL_APPS_EN>, - <&src IMX7_RESET_PCIE_CTRL_APPS_TURNOFF>; - reset-names = "pciephy", "apps", "turnoff"; - fsl,imx7d-pcie-phy = <&pcie_phy>; - status = "disabled"; - }; -}; - -&ca_funnel_in_ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - ca_funnel_in_port1: endpoint { - remote-endpoint = <&etm1_out_port>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/imx7s-colibri-eval-v3.dts b/sys/gnu/dts/arm/imx7s-colibri-eval-v3.dts deleted file mode 100644 index bd2a49c1ade..00000000000 --- a/sys/gnu/dts/arm/imx7s-colibri-eval-v3.dts +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright 2016 Toradex AG - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx7s-colibri.dtsi" -#include "imx7-colibri-eval-v3.dtsi" - -/ { - model = "Toradex Colibri iMX7S on Colibri Evaluation Board V3"; - compatible = "toradex,colibri-imx7s-eval-v3", "toradex,colibri-imx7s", - "fsl,imx7s"; -}; diff --git a/sys/gnu/dts/arm/imx7s-colibri.dtsi b/sys/gnu/dts/arm/imx7s-colibri.dtsi deleted file mode 100644 index 6d16e32aed8..00000000000 --- a/sys/gnu/dts/arm/imx7s-colibri.dtsi +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Copyright 2016 Toradex AG - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "imx7s.dtsi" -#include "imx7-colibri.dtsi" - -/ { - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x10000000>; - }; -}; - -&gpmi { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/imx7s-mba7.dts b/sys/gnu/dts/arm/imx7s-mba7.dts deleted file mode 100644 index a143d566a38..00000000000 --- a/sys/gnu/dts/arm/imx7s-mba7.dts +++ /dev/null @@ -1,18 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR X11 -/* - * Device Tree Source for TQ Systems TQMa7S board on MBa7 carrier board. - * - * Copyright (C) 2016 TQ Systems GmbH - * Author: Markus Niebel - * Copyright (C) 2019 Bruno Thomsen - */ - -/dts-v1/; - -#include "imx7s-tqma7.dtsi" -#include "imx7-mba7.dtsi" - -/ { - model = "TQ Systems TQMa7S board on MBa7 carrier board"; - compatible = "tq,imx7s-mba7", "fsl,imx7s"; -}; diff --git a/sys/gnu/dts/arm/imx7s-tqma7.dtsi b/sys/gnu/dts/arm/imx7s-tqma7.dtsi deleted file mode 100644 index 5f5433eb7dd..00000000000 --- a/sys/gnu/dts/arm/imx7s-tqma7.dtsi +++ /dev/null @@ -1,11 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR X11 -/* - * Device Tree Include file for TQ Systems TQMa7S board with NXP i.MX7Solo SoC. - * - * Copyright (C) 2016 TQ Systems GmbH - * Author: Markus Niebel - * Copyright (C) 2019 Bruno Thomsen - */ - -#include "imx7s.dtsi" -#include "imx7-tqma7.dtsi" diff --git a/sys/gnu/dts/arm/imx7s-warp.dts b/sys/gnu/dts/arm/imx7s-warp.dts deleted file mode 100644 index d6b4888fa68..00000000000 --- a/sys/gnu/dts/arm/imx7s-warp.dts +++ /dev/null @@ -1,500 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2016 NXP Semiconductors. - * Author: Fabio Estevam - */ - -/dts-v1/; - -#include -#include "imx7s.dtsi" - -/ { - model = "Warp i.MX7 Board"; - compatible = "warp,imx7s-warp", "fsl,imx7s"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000>; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-0 = <&pinctrl_gpio>; - autorepeat; - - back { - label = "Back"; - gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; - linux,code = ; - wakeup-source; - }; - }; - - reg_brcm: regulator-brcm { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio5 10 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_brcm_reg>; - regulator-name = "brcm_reg"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <200000>; - }; - - reg_bt: regulator-bt { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_bt_reg>; - enable-active-high; - gpio = <&gpio5 17 GPIO_ACTIVE_HIGH>; - regulator-name = "bt_reg"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_peri_3p15v: regulator-peri-3p15v { - compatible = "regulator-fixed"; - regulator-name = "peri_3p15v_reg"; - regulator-min-microvolt = <3150000>; - regulator-max-microvolt = <3150000>; - regulator-always-on; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "imx7-sgtl5000"; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&dailink_master>; - simple-audio-card,frame-master = <&dailink_master>; - simple-audio-card,cpu { - sound-dai = <&sai1>; - }; - - dailink_master: simple-audio-card,codec { - sound-dai = <&codec>; - clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; - }; - }; -}; - -&clks { - assigned-clocks = <&clks IMX7D_PLL_AUDIO_POST_DIV>; - assigned-clock-rates = <884736000>; -}; - -&csi { - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pmic: pfuze3000@8 { - compatible = "fsl,pfuze3000"; - reg = <0x08>; - - regulators { - sw1a_reg: sw1a { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1475000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - /* use sw1c_reg to align with pfuze100/pfuze200 */ - sw1c_reg: sw1b { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1475000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1850000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3a_reg: sw3 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1650000>; - regulator-boot-on; - regulator-always-on; - }; - - swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - regulator-boot-on; - regulator-always-on; - }; - - snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - vgen1_reg: vldo1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen2_reg: vldo2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen3_reg: vccsd { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen4_reg: v33 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen5_reg: vldo3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen6_reg: vldo4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - ov2680: camera@36 { - compatible = "ovti,ov2680"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ov2680>; - reg = <0x36>; - clocks = <&osc>; - clock-names = "xvclk"; - reset-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; - DOVDD-supply = <&sw2_reg>; - DVDD-supply = <&sw2_reg>; - AVDD-supply = <®_peri_3p15v>; - - port { - ov2680_to_mipi: endpoint { - remote-endpoint = <&mipi_from_sensor>; - clock-lanes = <0>; - data-lanes = <1>; - }; - }; - }; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; -}; - -&i2c4 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4>; - status = "okay"; - - codec: sgtl5000@a { - #sound-dai-cells = <0>; - reg = <0x0a>; - compatible = "fsl,sgtl5000"; - clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai1_mclk>; - VDDA-supply = <&vgen4_reg>; - VDDIO-supply = <&vgen4_reg>; - VDDD-supply = <&vgen2_reg>; - }; - - mpl3115@60 { - compatible = "fsl,mpl3115"; - reg = <0x60>; - }; -}; - -&mipi_csi { - clock-frequency = <166000000>; - fsl,csis-hs-settle = <3>; - status = "okay"; - - port@0 { - reg = <0>; - - mipi_from_sensor: endpoint { - remote-endpoint = <&ov2680_to_mipi>; - data-lanes = <1>; - }; - - }; -}; - -&sai1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai1>; - assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>, - <&clks IMX7D_SAI1_ROOT_CLK>; - assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; - assigned-clock-rates = <0>, <36864000>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>; - assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>; - assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; - uart-has-rtscts; - status = "okay"; -}; - -&uart6 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart6>; - assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>; - assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; - fsl,dte-mode; - status = "okay"; -}; - -&usbotg1 { - dr_mode = "peripheral"; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - bus-width = <4>; - keep-power-in-suspend; - no-1-8-v; - non-removable; - vmmc-supply = <®_brcm>; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>; - assigned-clock-rates = <400000000>; - bus-width = <8>; - no-1-8-v; - fsl,tuning-step = <2>; - non-removable; - status = "okay"; -}; - -&video_mux { - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl_brcm_reg: brcmreggrp { - fsl,pins = < - MX7D_PAD_SD2_WP__GPIO5_IO10 0x14 /* WL_REG_ON */ - >; - }; - - pinctrl_bt_reg: btreggrp { - fsl,pins = < - MX7D_PAD_SD2_DATA3__GPIO5_IO17 0x14 /* BT_REG_ON */ - >; - }; - - pinctrl_gpio: gpiogrp { - fsl,pins = < - MX7D_PAD_ENET1_RGMII_RD1__GPIO7_IO1 0x14 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f - MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f - MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f - MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f - >; - }; - - pinctrl_i2c4: i2c4grp { - fsl,pins = < - MX7D_PAD_I2C4_SCL__I2C4_SCL 0x4000007f - MX7D_PAD_I2C4_SDA__I2C4_SDA 0x4000007f - >; - }; - - pinctrl_ov2680: ov2660grp { - fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO03__GPIO1_IO3 0x14 - >; - }; - - pinctrl_sai1: sai1grp { - fsl,pins = < - MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0 0x1f - MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK 0x1f - MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x1f - MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0 0x30 - >; - }; - - pinctrl_sai1_mclk: sai1mclkgrp { - fsl,pins = < - MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x1f - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79 - MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x79 - MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x79 - MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS 0x79 - MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS 0x79 - >; - }; - - pinctrl_uart6: uart6grp { - fsl,pins = < - MX7D_PAD_ECSPI1_MOSI__UART6_DTE_RX 0x79 - MX7D_PAD_ECSPI1_SCLK__UART6_DTE_TX 0x79 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX7D_PAD_SD1_CMD__SD1_CMD 0x59 - MX7D_PAD_SD1_CLK__SD1_CLK 0x19 - MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 - MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 - MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 - MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 - MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x14 /* WL_HOST_WAKE */ - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX7D_PAD_SD3_CMD__SD3_CMD 0x59 - MX7D_PAD_SD3_CLK__SD3_CLK 0x19 - MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 - MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 - MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 - MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 - MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 - MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 - MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 - MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 - MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x19 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { - fsl,pins = < - MX7D_PAD_SD3_CMD__SD3_CMD 0x5a - MX7D_PAD_SD3_CLK__SD3_CLK 0x1a - MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a - MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a - MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a - MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a - MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a - MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a - MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a - MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a - MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x1a - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3grp_200mhz { - fsl,pins = < - MX7D_PAD_SD3_CMD__SD3_CMD 0x5b - MX7D_PAD_SD3_CLK__SD3_CLK 0x1b - MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b - MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b - MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b - MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b - MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b - MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b - MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b - MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b - MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x1b - >; - }; -}; - -&iomuxc_lpsr { - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74 - >; - }; -}; diff --git a/sys/gnu/dts/arm/imx7s.dtsi b/sys/gnu/dts/arm/imx7s.dtsi deleted file mode 100644 index 568d7a984aa..00000000000 --- a/sys/gnu/dts/arm/imx7s.dtsi +++ /dev/null @@ -1,1226 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -// -// Copyright 2015 Freescale Semiconductor, Inc. -// Copyright 2016 Toradex AG - -#include -#include -#include -#include -#include -#include -#include "imx7d-pinfunc.h" - -/ { - #address-cells = <1>; - #size-cells = <1>; - /* - * The decompressor and also some bootloaders rely on a - * pre-existing /chosen node to be available to insert the - * command line and merge other ATAGS info. - */ - chosen {}; - - aliases { - gpio0 = &gpio1; - gpio1 = &gpio2; - gpio2 = &gpio3; - gpio3 = &gpio4; - gpio4 = &gpio5; - gpio5 = &gpio6; - gpio6 = &gpio7; - i2c0 = &i2c1; - i2c1 = &i2c2; - i2c2 = &i2c3; - i2c3 = &i2c4; - mmc0 = &usdhc1; - mmc1 = &usdhc2; - mmc2 = &usdhc3; - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - serial3 = &uart4; - serial4 = &uart5; - serial5 = &uart6; - serial6 = &uart7; - spi0 = &ecspi1; - spi1 = &ecspi2; - spi2 = &ecspi3; - spi3 = &ecspi4; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - idle-states { - entry-method = "psci"; - - cpu_sleep_wait: cpu-sleep-wait { - compatible = "arm,idle-state"; - arm,psci-suspend-param = <0x0010000>; - local-timer-stop; - entry-latency-us = <100>; - exit-latency-us = <50>; - min-residency-us = <1000>; - }; - }; - - cpu0: cpu@0 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <0>; - clock-frequency = <792000000>; - clock-latency = <61036>; /* two CLK32 periods */ - clocks = <&clks IMX7D_CLK_ARM>; - cpu-idle-states = <&cpu_sleep_wait>; - }; - }; - - ckil: clock-cki { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "ckil"; - }; - - osc: clock-osc { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "osc"; - }; - - usbphynop1: usbphynop1 { - compatible = "usb-nop-xceiv"; - clocks = <&clks IMX7D_USB_PHY1_CLK>; - clock-names = "main_clk"; - #phy-cells = <0>; - }; - - usbphynop3: usbphynop3 { - compatible = "usb-nop-xceiv"; - clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>; - clock-names = "main_clk"; - #phy-cells = <0>; - }; - - pmu { - compatible = "arm,cortex-a7-pmu"; - interrupt-parent = <&gpc>; - interrupts = ; - interrupt-affinity = <&cpu0>; - }; - - replicator { - /* - * non-configurable replicators don't show up on the - * AMBA bus. As such no need to add "arm,primecell" - */ - compatible = "arm,coresight-static-replicator"; - - out-ports { - #address-cells = <1>; - #size-cells = <0>; - /* replicator output ports */ - port@0 { - reg = <0>; - replicator_out_port0: endpoint { - remote-endpoint = <&tpiu_in_port>; - }; - }; - - port@1 { - reg = <1>; - replicator_out_port1: endpoint { - remote-endpoint = <&etr_in_port>; - }; - }; - }; - - in-ports { - port { - replicator_in_port0: endpoint { - remote-endpoint = <&etf_out_port>; - }; - }; - }; - }; - - tempmon: tempmon { - compatible = "fsl,imx7d-tempmon"; - interrupt-parent = <&gpc>; - interrupts = ; - fsl,tempmon = <&anatop>; - nvmem-cells = <&tempmon_calib>, <&fuse_grade>; - nvmem-cell-names = "calib", "temp_grade"; - clocks = <&clks IMX7D_PLL_SYS_MAIN_CLK>; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupt-parent = <&intc>; - interrupts = , - , - , - ; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&gpc>; - ranges; - - funnel@30041000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0x30041000 0x1000>; - clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; - clock-names = "apb_pclk"; - - ca_funnel_in_ports: in-ports { - port { - ca_funnel_in_port0: endpoint { - remote-endpoint = <&etm0_out_port>; - }; - }; - - /* the other input ports are not connect to anything */ - }; - - out-ports { - port { - ca_funnel_out_port0: endpoint { - remote-endpoint = <&hugo_funnel_in_port0>; - }; - }; - - }; - }; - - etm@3007c000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0x3007c000 0x1000>; - cpu = <&cpu0>; - clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; - clock-names = "apb_pclk"; - - out-ports { - port { - etm0_out_port: endpoint { - remote-endpoint = <&ca_funnel_in_port0>; - }; - }; - }; - }; - - funnel@30083000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0x30083000 0x1000>; - clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; - clock-names = "apb_pclk"; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - hugo_funnel_in_port0: endpoint { - remote-endpoint = <&ca_funnel_out_port0>; - }; - }; - - port@1 { - reg = <1>; - hugo_funnel_in_port1: endpoint { - /* M4 input */ - }; - }; - /* the other input ports are not connect to anything */ - }; - - out-ports { - port { - hugo_funnel_out_port0: endpoint { - remote-endpoint = <&etf_in_port>; - }; - }; - }; - }; - - etf@30084000 { - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0x30084000 0x1000>; - clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; - clock-names = "apb_pclk"; - - in-ports { - port { - etf_in_port: endpoint { - remote-endpoint = <&hugo_funnel_out_port0>; - }; - }; - }; - - out-ports { - port { - etf_out_port: endpoint { - remote-endpoint = <&replicator_in_port0>; - }; - }; - }; - }; - - etr@30086000 { - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0x30086000 0x1000>; - clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; - clock-names = "apb_pclk"; - - in-ports { - port { - etr_in_port: endpoint { - remote-endpoint = <&replicator_out_port1>; - }; - }; - }; - }; - - tpiu@30087000 { - compatible = "arm,coresight-tpiu", "arm,primecell"; - reg = <0x30087000 0x1000>; - clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; - clock-names = "apb_pclk"; - - in-ports { - port { - tpiu_in_port: endpoint { - remote-endpoint = <&replicator_out_port0>; - }; - }; - }; - }; - - intc: interrupt-controller@31001000 { - compatible = "arm,cortex-a7-gic"; - interrupts = ; - #interrupt-cells = <3>; - interrupt-controller; - interrupt-parent = <&intc>; - reg = <0x31001000 0x1000>, - <0x31002000 0x2000>, - <0x31004000 0x2000>, - <0x31006000 0x2000>; - }; - - aips1: aips-bus@30000000 { - compatible = "fsl,aips-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x30000000 0x400000>; - ranges; - - gpio1: gpio@30200000 { - compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; - reg = <0x30200000 0x10000>; - interrupts = , /* GPIO1_INT15_0 */ - ; /* GPIO1_INT31_16 */ - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc_lpsr 0 0 8>, <&iomuxc 8 5 8>; - }; - - gpio2: gpio@30210000 { - compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; - reg = <0x30210000 0x10000>; - interrupts = , - ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 13 32>; - }; - - gpio3: gpio@30220000 { - compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; - reg = <0x30220000 0x10000>; - interrupts = , - ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 45 29>; - }; - - gpio4: gpio@30230000 { - compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; - reg = <0x30230000 0x10000>; - interrupts = , - ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 74 24>; - }; - - gpio5: gpio@30240000 { - compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; - reg = <0x30240000 0x10000>; - interrupts = , - ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 98 18>; - }; - - gpio6: gpio@30250000 { - compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; - reg = <0x30250000 0x10000>; - interrupts = , - ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 116 23>; - }; - - gpio7: gpio@30260000 { - compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; - reg = <0x30260000 0x10000>; - interrupts = , - ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 139 16>; - }; - - wdog1: wdog@30280000 { - compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; - reg = <0x30280000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_WDOG1_ROOT_CLK>; - }; - - wdog2: wdog@30290000 { - compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; - reg = <0x30290000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_WDOG2_ROOT_CLK>; - status = "disabled"; - }; - - wdog3: wdog@302a0000 { - compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; - reg = <0x302a0000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_WDOG3_ROOT_CLK>; - status = "disabled"; - }; - - wdog4: wdog@302b0000 { - compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; - reg = <0x302b0000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_WDOG4_ROOT_CLK>; - status = "disabled"; - }; - - iomuxc_lpsr: iomuxc-lpsr@302c0000 { - compatible = "fsl,imx7d-iomuxc-lpsr"; - reg = <0x302c0000 0x10000>; - fsl,input-sel = <&iomuxc>; - }; - - gpt1: gpt@302d0000 { - compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; - reg = <0x302d0000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_GPT1_ROOT_CLK>, - <&clks IMX7D_GPT1_ROOT_CLK>; - clock-names = "ipg", "per"; - }; - - gpt2: gpt@302e0000 { - compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; - reg = <0x302e0000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_GPT2_ROOT_CLK>, - <&clks IMX7D_GPT2_ROOT_CLK>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - gpt3: gpt@302f0000 { - compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; - reg = <0x302f0000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_GPT3_ROOT_CLK>, - <&clks IMX7D_GPT3_ROOT_CLK>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - gpt4: gpt@30300000 { - compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; - reg = <0x30300000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_GPT4_ROOT_CLK>, - <&clks IMX7D_GPT4_ROOT_CLK>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - kpp: kpp@30320000 { - compatible = "fsl,imx7d-kpp", "fsl,imx21-kpp"; - reg = <0x30320000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_KPP_ROOT_CLK>; - status = "disabled"; - }; - - iomuxc: iomuxc@30330000 { - compatible = "fsl,imx7d-iomuxc"; - reg = <0x30330000 0x10000>; - }; - - gpr: iomuxc-gpr@30340000 { - compatible = "fsl,imx7d-iomuxc-gpr", - "fsl,imx6q-iomuxc-gpr", "syscon", - "simple-mfd"; - reg = <0x30340000 0x10000>; - - mux: mux-controller { - compatible = "mmio-mux"; - #mux-control-cells = <0>; - mux-reg-masks = <0x14 0x00000010>; - }; - - video_mux: csi-mux { - compatible = "video-mux"; - mux-controls = <&mux 0>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - port@0 { - reg = <0>; - }; - - port@1 { - reg = <1>; - - csi_mux_from_mipi_vc0: endpoint { - remote-endpoint = <&mipi_vc0_to_csi_mux>; - }; - }; - - port@2 { - reg = <2>; - - csi_mux_to_csi: endpoint { - remote-endpoint = <&csi_from_csi_mux>; - }; - }; - }; - }; - - ocotp: ocotp-ctrl@30350000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "fsl,imx7d-ocotp", "syscon"; - reg = <0x30350000 0x10000>; - clocks = <&clks IMX7D_OCOTP_CLK>; - - tempmon_calib: calib@3c { - reg = <0x3c 0x4>; - }; - - fuse_grade: fuse-grade@10 { - reg = <0x10 0x4>; - }; - }; - - anatop: anatop@30360000 { - compatible = "fsl,imx7d-anatop", "fsl,imx6q-anatop", - "syscon", "simple-mfd"; - reg = <0x30360000 0x10000>; - interrupts = , - ; - - reg_1p0d: regulator-vdd1p0d { - compatible = "fsl,anatop-regulator"; - regulator-name = "vdd1p0d"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1200000>; - anatop-reg-offset = <0x210>; - anatop-vol-bit-shift = <8>; - anatop-vol-bit-width = <5>; - anatop-min-bit-val = <8>; - anatop-min-voltage = <800000>; - anatop-max-voltage = <1200000>; - anatop-enable-bit = <0>; - }; - - reg_1p2: regulator-vdd1p2 { - compatible = "fsl,anatop-regulator"; - regulator-name = "vdd1p2"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1300000>; - anatop-reg-offset = <0x220>; - anatop-vol-bit-shift = <8>; - anatop-vol-bit-width = <5>; - anatop-min-bit-val = <0x14>; - anatop-min-voltage = <1100000>; - anatop-max-voltage = <1300000>; - anatop-enable-bit = <0>; - }; - }; - - snvs: snvs@30370000 { - compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; - reg = <0x30370000 0x10000>; - - snvs_rtc: snvs-rtc-lp { - compatible = "fsl,sec-v4.0-mon-rtc-lp"; - regmap = <&snvs>; - offset = <0x34>; - interrupts = , - ; - clocks = <&clks IMX7D_SNVS_CLK>; - clock-names = "snvs-rtc"; - }; - - snvs_pwrkey: snvs-powerkey { - compatible = "fsl,sec-v4.0-pwrkey"; - regmap = <&snvs>; - interrupts = ; - linux,keycode = ; - wakeup-source; - status = "disabled"; - }; - }; - - clks: ccm@30380000 { - compatible = "fsl,imx7d-ccm"; - reg = <0x30380000 0x10000>; - interrupts = , - ; - #clock-cells = <1>; - clocks = <&ckil>, <&osc>; - clock-names = "ckil", "osc"; - }; - - src: src@30390000 { - compatible = "fsl,imx7d-src", "syscon"; - reg = <0x30390000 0x10000>; - interrupts = ; - #reset-cells = <1>; - }; - - gpc: gpc@303a0000 { - compatible = "fsl,imx7d-gpc"; - reg = <0x303a0000 0x10000>; - interrupt-controller; - interrupts = ; - #interrupt-cells = <3>; - interrupt-parent = <&intc>; - #power-domain-cells = <1>; - - pgc { - #address-cells = <1>; - #size-cells = <0>; - - pgc_mipi_phy: power-domain@0 { - #power-domain-cells = <0>; - reg = <0>; - power-supply = <®_1p0d>; - }; - - pgc_pcie_phy: power-domain@1 { - #power-domain-cells = <0>; - reg = <1>; - power-supply = <®_1p0d>; - }; - - pgc_hsic_phy: power-domain@2 { - #power-domain-cells = <0>; - reg = <2>; - power-supply = <®_1p2>; - }; - }; - }; - }; - - aips2: aips-bus@30400000 { - compatible = "fsl,aips-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x30400000 0x400000>; - ranges; - - adc1: adc@30610000 { - compatible = "fsl,imx7d-adc"; - reg = <0x30610000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_ADC_ROOT_CLK>; - clock-names = "adc"; - #io-channel-cells = <1>; - status = "disabled"; - }; - - adc2: adc@30620000 { - compatible = "fsl,imx7d-adc"; - reg = <0x30620000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_ADC_ROOT_CLK>; - clock-names = "adc"; - #io-channel-cells = <1>; - status = "disabled"; - }; - - ecspi4: spi@30630000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; - reg = <0x30630000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_ECSPI4_ROOT_CLK>, - <&clks IMX7D_ECSPI4_ROOT_CLK>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - pwm1: pwm@30660000 { - compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; - reg = <0x30660000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_PWM1_ROOT_CLK>, - <&clks IMX7D_PWM1_ROOT_CLK>; - clock-names = "ipg", "per"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm2: pwm@30670000 { - compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; - reg = <0x30670000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_PWM2_ROOT_CLK>, - <&clks IMX7D_PWM2_ROOT_CLK>; - clock-names = "ipg", "per"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm3: pwm@30680000 { - compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; - reg = <0x30680000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_PWM3_ROOT_CLK>, - <&clks IMX7D_PWM3_ROOT_CLK>; - clock-names = "ipg", "per"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm4: pwm@30690000 { - compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; - reg = <0x30690000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_PWM4_ROOT_CLK>, - <&clks IMX7D_PWM4_ROOT_CLK>; - clock-names = "ipg", "per"; - #pwm-cells = <3>; - status = "disabled"; - }; - - csi: csi@30710000 { - compatible = "fsl,imx7-csi"; - reg = <0x30710000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_CLK_DUMMY>, - <&clks IMX7D_CSI_MCLK_ROOT_CLK>, - <&clks IMX7D_CLK_DUMMY>; - clock-names = "axi", "mclk", "dcic"; - status = "disabled"; - - port { - csi_from_csi_mux: endpoint { - remote-endpoint = <&csi_mux_to_csi>; - }; - }; - }; - - lcdif: lcdif@30730000 { - compatible = "fsl,imx7d-lcdif", "fsl,imx28-lcdif"; - reg = <0x30730000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>, - <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>; - clock-names = "pix", "axi"; - status = "disabled"; - }; - - mipi_csi: mipi-csi@30750000 { - compatible = "fsl,imx7-mipi-csi2"; - reg = <0x30750000 0x10000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clocks = <&clks IMX7D_IPG_ROOT_CLK>, - <&clks IMX7D_MIPI_CSI_ROOT_CLK>, - <&clks IMX7D_MIPI_DPHY_ROOT_CLK>; - clock-names = "pclk", "wrap", "phy"; - power-domains = <&pgc_mipi_phy>; - phy-supply = <®_1p0d>; - resets = <&src IMX7_RESET_MIPI_PHY_MRST>; - reset-names = "mrst"; - status = "disabled"; - - port@0 { - reg = <0>; - }; - - port@1 { - reg = <1>; - - mipi_vc0_to_csi_mux: endpoint { - remote-endpoint = <&csi_mux_from_mipi_vc0>; - }; - }; - }; - }; - - aips3: aips-bus@30800000 { - compatible = "fsl,aips-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x30800000 0x400000>; - ranges; - - spba-bus@30800000 { - compatible = "fsl,spba-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x30800000 0x100000>; - ranges; - - ecspi1: spi@30820000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; - reg = <0x30820000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_ECSPI1_ROOT_CLK>, - <&clks IMX7D_ECSPI1_ROOT_CLK>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - ecspi2: spi@30830000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; - reg = <0x30830000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_ECSPI2_ROOT_CLK>, - <&clks IMX7D_ECSPI2_ROOT_CLK>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - ecspi3: spi@30840000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; - reg = <0x30840000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_ECSPI3_ROOT_CLK>, - <&clks IMX7D_ECSPI3_ROOT_CLK>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart1: serial@30860000 { - compatible = "fsl,imx7d-uart", - "fsl,imx6q-uart"; - reg = <0x30860000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_UART1_ROOT_CLK>, - <&clks IMX7D_UART1_ROOT_CLK>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart2: serial@30890000 { - compatible = "fsl,imx7d-uart", - "fsl,imx6q-uart"; - reg = <0x30890000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_UART2_ROOT_CLK>, - <&clks IMX7D_UART2_ROOT_CLK>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart3: serial@30880000 { - compatible = "fsl,imx7d-uart", - "fsl,imx6q-uart"; - reg = <0x30880000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_UART3_ROOT_CLK>, - <&clks IMX7D_UART3_ROOT_CLK>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - sai1: sai@308a0000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai"; - reg = <0x308a0000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_SAI1_IPG_CLK>, - <&clks IMX7D_SAI1_ROOT_CLK>, - <&clks IMX7D_CLK_DUMMY>, - <&clks IMX7D_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dma-names = "rx", "tx"; - dmas = <&sdma 8 24 0>, <&sdma 9 24 0>; - status = "disabled"; - }; - - sai2: sai@308b0000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai"; - reg = <0x308b0000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_SAI2_IPG_CLK>, - <&clks IMX7D_SAI2_ROOT_CLK>, - <&clks IMX7D_CLK_DUMMY>, - <&clks IMX7D_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dma-names = "rx", "tx"; - dmas = <&sdma 10 24 0>, <&sdma 11 24 0>; - status = "disabled"; - }; - - sai3: sai@308c0000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai"; - reg = <0x308c0000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_SAI3_IPG_CLK>, - <&clks IMX7D_SAI3_ROOT_CLK>, - <&clks IMX7D_CLK_DUMMY>, - <&clks IMX7D_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dma-names = "rx", "tx"; - dmas = <&sdma 12 24 0>, <&sdma 13 24 0>; - status = "disabled"; - }; - }; - - crypto: caam@30900000 { - compatible = "fsl,sec-v4.0"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x30900000 0x40000>; - ranges = <0 0x30900000 0x40000>; - interrupts = ; - clocks = <&clks IMX7D_CAAM_CLK>, - <&clks IMX7D_AHB_CHANNEL_ROOT_CLK>; - clock-names = "ipg", "aclk"; - - sec_jr0: jr0@1000 { - compatible = "fsl,sec-v4.0-job-ring"; - reg = <0x1000 0x1000>; - interrupts = ; - }; - - sec_jr1: jr1@2000 { - compatible = "fsl,sec-v4.0-job-ring"; - reg = <0x2000 0x1000>; - interrupts = ; - }; - - sec_jr2: jr1@3000 { - compatible = "fsl,sec-v4.0-job-ring"; - reg = <0x3000 0x1000>; - interrupts = ; - }; - }; - - flexcan1: can@30a00000 { - compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan"; - reg = <0x30a00000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_CLK_DUMMY>, - <&clks IMX7D_CAN1_ROOT_CLK>; - clock-names = "ipg", "per"; - fsl,stop-mode = <&gpr 0x10 1 0x10 17>; - status = "disabled"; - }; - - flexcan2: can@30a10000 { - compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan"; - reg = <0x30a10000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_CLK_DUMMY>, - <&clks IMX7D_CAN2_ROOT_CLK>; - clock-names = "ipg", "per"; - fsl,stop-mode = <&gpr 0x10 2 0x10 18>; - status = "disabled"; - }; - - i2c1: i2c@30a20000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; - reg = <0x30a20000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_I2C1_ROOT_CLK>; - status = "disabled"; - }; - - i2c2: i2c@30a30000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; - reg = <0x30a30000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_I2C2_ROOT_CLK>; - status = "disabled"; - }; - - i2c3: i2c@30a40000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; - reg = <0x30a40000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_I2C3_ROOT_CLK>; - status = "disabled"; - }; - - i2c4: i2c@30a50000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; - reg = <0x30a50000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_I2C4_ROOT_CLK>; - status = "disabled"; - }; - - uart4: serial@30a60000 { - compatible = "fsl,imx7d-uart", - "fsl,imx6q-uart"; - reg = <0x30a60000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_UART4_ROOT_CLK>, - <&clks IMX7D_UART4_ROOT_CLK>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart5: serial@30a70000 { - compatible = "fsl,imx7d-uart", - "fsl,imx6q-uart"; - reg = <0x30a70000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_UART5_ROOT_CLK>, - <&clks IMX7D_UART5_ROOT_CLK>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart6: serial@30a80000 { - compatible = "fsl,imx7d-uart", - "fsl,imx6q-uart"; - reg = <0x30a80000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_UART6_ROOT_CLK>, - <&clks IMX7D_UART6_ROOT_CLK>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart7: serial@30a90000 { - compatible = "fsl,imx7d-uart", - "fsl,imx6q-uart"; - reg = <0x30a90000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_UART7_ROOT_CLK>, - <&clks IMX7D_UART7_ROOT_CLK>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - mu0a: mailbox@30aa0000 { - compatible = "fsl,imx7s-mu", "fsl,imx6sx-mu"; - reg = <0x30aa0000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_MU_ROOT_CLK>; - #mbox-cells = <2>; - status = "disabled"; - }; - - mu0b: mailbox@30ab0000 { - compatible = "fsl,imx7s-mu", "fsl,imx6sx-mu"; - reg = <0x30ab0000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_MU_ROOT_CLK>; - #mbox-cells = <2>; - fsl,mu-side-b; - status = "disabled"; - }; - - usbotg1: usb@30b10000 { - compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; - reg = <0x30b10000 0x200>; - interrupts = ; - clocks = <&clks IMX7D_USB_CTRL_CLK>; - fsl,usbphy = <&usbphynop1>; - fsl,usbmisc = <&usbmisc1 0>; - phy-clkgate-delay-us = <400>; - status = "disabled"; - }; - - usbh: usb@30b30000 { - compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; - reg = <0x30b30000 0x200>; - interrupts = ; - power-domains = <&pgc_hsic_phy>; - clocks = <&clks IMX7D_USB_CTRL_CLK>; - fsl,usbphy = <&usbphynop3>; - fsl,usbmisc = <&usbmisc3 0>; - phy_type = "hsic"; - dr_mode = "host"; - phy-clkgate-delay-us = <400>; - status = "disabled"; - }; - - usbmisc1: usbmisc@30b10200 { - #index-cells = <1>; - compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; - reg = <0x30b10200 0x200>; - }; - - usbmisc3: usbmisc@30b30200 { - #index-cells = <1>; - compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; - reg = <0x30b30200 0x200>; - }; - - usdhc1: usdhc@30b40000 { - compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; - reg = <0x30b40000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_IPG_ROOT_CLK>, - <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>, - <&clks IMX7D_USDHC1_ROOT_CLK>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - status = "disabled"; - }; - - usdhc2: usdhc@30b50000 { - compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; - reg = <0x30b50000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_IPG_ROOT_CLK>, - <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>, - <&clks IMX7D_USDHC2_ROOT_CLK>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - status = "disabled"; - }; - - usdhc3: usdhc@30b60000 { - compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; - reg = <0x30b60000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_IPG_ROOT_CLK>, - <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>, - <&clks IMX7D_USDHC3_ROOT_CLK>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - status = "disabled"; - }; - - sdma: sdma@30bd0000 { - compatible = "fsl,imx7d-sdma", "fsl,imx35-sdma"; - reg = <0x30bd0000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_IPG_ROOT_CLK>, - <&clks IMX7D_SDMA_CORE_CLK>; - clock-names = "ipg", "ahb"; - #dma-cells = <3>; - fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; - }; - - fec1: ethernet@30be0000 { - compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec"; - reg = <0x30be0000 0x10000>; - interrupt-names = "int0", "int1", "int2", "pps"; - interrupts = , - , - , - ; - clocks = <&clks IMX7D_ENET1_IPG_ROOT_CLK>, - <&clks IMX7D_ENET_AXI_ROOT_CLK>, - <&clks IMX7D_ENET1_TIME_ROOT_CLK>, - <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>, - <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>; - clock-names = "ipg", "ahb", "ptp", - "enet_clk_ref", "enet_out"; - fsl,num-tx-queues = <3>; - fsl,num-rx-queues = <3>; - status = "disabled"; - }; - }; - - dma_apbh: dma-apbh@33000000 { - compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh"; - reg = <0x33000000 0x2000>; - interrupts = , - , - , - ; - interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; - #dma-cells = <1>; - dma-channels = <4>; - clocks = <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>; - }; - - gpmi: gpmi-nand@33002000{ - compatible = "fsl,imx7d-gpmi-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x33002000 0x2000>, <0x33004000 0x4000>; - reg-names = "gpmi-nand", "bch"; - interrupts = ; - interrupt-names = "bch"; - clocks = <&clks IMX7D_NAND_RAWNAND_CLK>, - <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>; - clock-names = "gpmi_io", "gpmi_bch_apb"; - dmas = <&dma_apbh 0>; - dma-names = "rx-tx"; - status = "disabled"; - assigned-clocks = <&clks IMX7D_NAND_ROOT_SRC>; - assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_500M_CLK>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/imx7ulp-com.dts b/sys/gnu/dts/arm/imx7ulp-com.dts deleted file mode 100644 index d76fea3b35c..00000000000 --- a/sys/gnu/dts/arm/imx7ulp-com.dts +++ /dev/null @@ -1,79 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// -// Copyright 2019 NXP - -/dts-v1/; - -#include "imx7ulp.dtsi" -#include - -/ { - model = "Embedded Artists i.MX7ULP COM"; - compatible = "ea,imx7ulp-com", "fsl,imx7ulp"; - - chosen { - stdout-path = &lpuart4; - }; - - memory@60000000 { - device_type = "memory"; - reg = <0x60000000 0x4000000>; - }; -}; - -&lpuart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpuart4>; - status = "okay"; -}; - -&usbotg1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg1_id>; - srp-disable; - hnp-disable; - adp-disable; - status = "okay"; -}; - -&usdhc0 { - assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC0>; - assigned-clock-parents = <&scg1 IMX7ULP_CLK_APLL_PFD1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc0>; - non-removable; - bus-width = <8>; - no-1-8-v; - status = "okay"; -}; - -&iomuxc1 { - pinctrl_lpuart4: lpuart4grp { - fsl,pins = < - IMX7ULP_PAD_PTC3__LPUART4_RX 0x3 - IMX7ULP_PAD_PTC2__LPUART4_TX 0x3 - >; - }; - - pinctrl_usbotg1_id: otg1idgrp { - fsl,pins = < - IMX7ULP_PAD_PTC13__USB0_ID 0x10003 - >; - }; - - pinctrl_usdhc0: usdhc0grp { - fsl,pins = < - IMX7ULP_PAD_PTD1__SDHC0_CMD 0x43 - IMX7ULP_PAD_PTD2__SDHC0_CLK 0x10042 - IMX7ULP_PAD_PTD3__SDHC0_D7 0x43 - IMX7ULP_PAD_PTD4__SDHC0_D6 0x43 - IMX7ULP_PAD_PTD5__SDHC0_D5 0x43 - IMX7ULP_PAD_PTD6__SDHC0_D4 0x43 - IMX7ULP_PAD_PTD7__SDHC0_D3 0x43 - IMX7ULP_PAD_PTD8__SDHC0_D2 0x43 - IMX7ULP_PAD_PTD9__SDHC0_D1 0x43 - IMX7ULP_PAD_PTD10__SDHC0_D0 0x43 - IMX7ULP_PAD_PTD11__SDHC0_DQS 0x42 - >; - }; -}; diff --git a/sys/gnu/dts/arm/imx7ulp-evk.dts b/sys/gnu/dts/arm/imx7ulp-evk.dts deleted file mode 100644 index a863a2b337d..00000000000 --- a/sys/gnu/dts/arm/imx7ulp-evk.dts +++ /dev/null @@ -1,134 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2016 Freescale Semiconductor, Inc. - * Copyright 2017-2018 NXP - * Dong Aisheng - */ - -/dts-v1/; - -#include "imx7ulp.dtsi" - -/ { - model = "NXP i.MX7ULP EVK"; - compatible = "fsl,imx7ulp-evk", "fsl,imx7ulp"; - - chosen { - stdout-path = &lpuart4; - }; - - memory@60000000 { - device_type = "memory"; - reg = <0x60000000 0x40000000>; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&tpm4 1 50000 0>; - brightness-levels = <0 20 25 30 35 40 100>; - default-brightness-level = <6>; - status = "okay"; - }; - - reg_usb_otg1_vbus: regulator-usb-otg1-vbus { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg1_vbus>; - regulator-name = "usb_otg1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio_ptc 0 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_vsd_3v3: regulator-vsd-3v3 { - compatible = "regulator-fixed"; - regulator-name = "VSD_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc0_rst>; - gpio = <&gpio_ptd 0 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&lpuart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpuart4>; - status = "okay"; -}; - -&tpm4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm0>; - status = "okay"; -}; - -&usbotg1 { - vbus-supply = <®_usb_otg1_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg1_id>; - srp-disable; - hnp-disable; - adp-disable; - over-current-active-low; - status = "okay"; -}; - -&usdhc0 { - assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC0>; - assigned-clock-parents = <&scg1 IMX7ULP_CLK_APLL_PFD1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc0>; - cd-gpios = <&gpio_ptc 10 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_vsd_3v3>; - status = "okay"; -}; - -&iomuxc1 { - pinctrl_lpuart4: lpuart4grp { - fsl,pins = < - IMX7ULP_PAD_PTC3__LPUART4_RX 0x3 - IMX7ULP_PAD_PTC2__LPUART4_TX 0x3 - >; - bias-pull-up; - }; - - pinctrl_pwm0: pwm0grp { - fsl,pins = < - IMX7ULP_PAD_PTF2__TPM4_CH1 0x2 - >; - }; - - pinctrl_usbotg1_vbus: otg1vbusgrp { - fsl,pins = < - IMX7ULP_PAD_PTC0__PTC0 0x20000 - >; - }; - - pinctrl_usbotg1_id: otg1idgrp { - fsl,pins = < - IMX7ULP_PAD_PTC13__USB0_ID 0x10003 - IMX7ULP_PAD_PTC16__USB1_OC2 0x10003 - >; - }; - - pinctrl_usdhc0: usdhc0grp { - fsl,pins = < - IMX7ULP_PAD_PTD1__SDHC0_CMD 0x43 - IMX7ULP_PAD_PTD2__SDHC0_CLK 0x40 - IMX7ULP_PAD_PTD7__SDHC0_D3 0x43 - IMX7ULP_PAD_PTD8__SDHC0_D2 0x43 - IMX7ULP_PAD_PTD9__SDHC0_D1 0x43 - IMX7ULP_PAD_PTD10__SDHC0_D0 0x43 - IMX7ULP_PAD_PTC10__PTC10 0x3 /* CD */ - >; - }; - - pinctrl_usdhc0_rst: usdhc0-gpio-rst-grp { - fsl,pins = < - IMX7ULP_PAD_PTD0__PTD0 0x3 - >; - }; -}; diff --git a/sys/gnu/dts/arm/imx7ulp-pinfunc.h b/sys/gnu/dts/arm/imx7ulp-pinfunc.h deleted file mode 100644 index c0148d79b62..00000000000 --- a/sys/gnu/dts/arm/imx7ulp-pinfunc.h +++ /dev/null @@ -1,478 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2016 Freescale Semiconductor, Inc. - * Copyright 2017 NXP - */ - -#ifndef __DTS_IMX7ULP_PINFUNC_H -#define __DTS_IMX7ULP_PINFUNC_H - -/* - * The pin function ID is a tuple of - * - */ - -#define IMX7ULP_PAD_PTC0__PTC0 0x0000 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTC0__TRACE_D15 0x0000 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTC0__LPUART4_CTS_B 0x0000 0x0244 0x4 0x1 -#define IMX7ULP_PAD_PTC0__LPI2C4_SCL 0x0000 0x0278 0x5 0x1 -#define IMX7ULP_PAD_PTC0__TPM4_CLKIN 0x0000 0x0298 0x6 0x1 -#define IMX7ULP_PAD_PTC0__FB_AD0 0x0000 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTC1__PTC1 0x0004 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTC1__TRACE_D14 0x0004 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTC1__LPUART4_RTS_B 0x0004 0x0000 0x4 0x0 -#define IMX7ULP_PAD_PTC1__LPI2C4_SDA 0x0004 0x027c 0x5 0x1 -#define IMX7ULP_PAD_PTC1__TPM4_CH0 0x0004 0x0280 0x6 0x1 -#define IMX7ULP_PAD_PTC1__FB_AD1 0x0004 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTC2__PTC2 0x0008 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTC2__TRACE_D13 0x0008 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTC2__LPUART4_TX 0x0008 0x024c 0x4 0x1 -#define IMX7ULP_PAD_PTC2__LPI2C4_HREQ 0x0008 0x0274 0x5 0x1 -#define IMX7ULP_PAD_PTC2__TPM4_CH1 0x0008 0x0284 0x6 0x1 -#define IMX7ULP_PAD_PTC2__FB_AD2 0x0008 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTC3__PTC3 0x000c 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTC3__TRACE_D12 0x000c 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTC3__LPUART4_RX 0x000c 0x0248 0x4 0x1 -#define IMX7ULP_PAD_PTC3__TPM4_CH2 0x000c 0x0288 0x6 0x1 -#define IMX7ULP_PAD_PTC3__FB_AD3 0x000c 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTC4__PTC4 0x0010 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTC4__TRACE_D11 0x0010 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTC4__FXIO1_D0 0x0010 0x0204 0x2 0x1 -#define IMX7ULP_PAD_PTC4__LPSPI2_PCS1 0x0010 0x02a0 0x3 0x1 -#define IMX7ULP_PAD_PTC4__LPUART5_CTS_B 0x0010 0x0250 0x4 0x1 -#define IMX7ULP_PAD_PTC4__LPI2C5_SCL 0x0010 0x02bc 0x5 0x1 -#define IMX7ULP_PAD_PTC4__TPM4_CH3 0x0010 0x028c 0x6 0x1 -#define IMX7ULP_PAD_PTC4__FB_AD4 0x0010 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTC5__PTC5 0x0014 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTC5__TRACE_D10 0x0014 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTC5__FXIO1_D1 0x0014 0x0208 0x2 0x1 -#define IMX7ULP_PAD_PTC5__LPSPI2_PCS2 0x0014 0x02a4 0x3 0x1 -#define IMX7ULP_PAD_PTC5__LPUART5_RTS_B 0x0014 0x0000 0x4 0x0 -#define IMX7ULP_PAD_PTC5__LPI2C5_SDA 0x0014 0x02c0 0x5 0x1 -#define IMX7ULP_PAD_PTC5__TPM4_CH4 0x0014 0x0290 0x6 0x1 -#define IMX7ULP_PAD_PTC5__FB_AD5 0x0014 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTC6__PTC6 0x0018 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTC6__TRACE_D9 0x0018 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTC6__FXIO1_D2 0x0018 0x020c 0x2 0x1 -#define IMX7ULP_PAD_PTC6__LPSPI2_PCS3 0x0018 0x02a8 0x3 0x1 -#define IMX7ULP_PAD_PTC6__LPUART5_TX 0x0018 0x0258 0x4 0x1 -#define IMX7ULP_PAD_PTC6__LPI2C5_HREQ 0x0018 0x02b8 0x5 0x1 -#define IMX7ULP_PAD_PTC6__TPM4_CH5 0x0018 0x0294 0x6 0x1 -#define IMX7ULP_PAD_PTC6__FB_AD6 0x0018 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTC7__PTC7 0x001c 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTC7__TRACE_D8 0x001c 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTC7__FXIO1_D3 0x001c 0x0210 0x2 0x1 -#define IMX7ULP_PAD_PTC7__LPUART5_RX 0x001c 0x0254 0x4 0x1 -#define IMX7ULP_PAD_PTC7__TPM5_CH1 0x001c 0x02c8 0x6 0x1 -#define IMX7ULP_PAD_PTC7__FB_AD7 0x001c 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTC8__PTC8 0x0020 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTC8__TRACE_D7 0x0020 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTC8__FXIO1_D4 0x0020 0x0214 0x2 0x1 -#define IMX7ULP_PAD_PTC8__LPSPI2_SIN 0x0020 0x02b0 0x3 0x1 -#define IMX7ULP_PAD_PTC8__LPUART6_CTS_B 0x0020 0x025c 0x4 0x1 -#define IMX7ULP_PAD_PTC8__LPI2C6_SCL 0x0020 0x02fc 0x5 0x1 -#define IMX7ULP_PAD_PTC8__TPM5_CLKIN 0x0020 0x02cc 0x6 0x1 -#define IMX7ULP_PAD_PTC8__FB_AD8 0x0020 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTC9__PTC9 0x0024 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTC9__TRACE_D6 0x0024 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTC9__FXIO1_D5 0x0024 0x0218 0x2 0x1 -#define IMX7ULP_PAD_PTC9__LPSPI2_SOUT 0x0024 0x02b4 0x3 0x1 -#define IMX7ULP_PAD_PTC9__LPUART6_RTS_B 0x0024 0x0000 0x4 0x0 -#define IMX7ULP_PAD_PTC9__LPI2C6_SDA 0x0024 0x0300 0x5 0x1 -#define IMX7ULP_PAD_PTC9__TPM5_CH0 0x0024 0x02c4 0x6 0x1 -#define IMX7ULP_PAD_PTC9__FB_AD9 0x0024 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTC10__PTC10 0x0028 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTC10__TRACE_D5 0x0028 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTC10__FXIO1_D6 0x0028 0x021c 0x2 0x1 -#define IMX7ULP_PAD_PTC10__LPSPI2_SCK 0x0028 0x02ac 0x3 0x1 -#define IMX7ULP_PAD_PTC10__LPUART6_TX 0x0028 0x0264 0x4 0x1 -#define IMX7ULP_PAD_PTC10__LPI2C6_HREQ 0x0028 0x02f8 0x5 0x1 -#define IMX7ULP_PAD_PTC10__TPM7_CH3 0x0028 0x02e8 0x6 0x1 -#define IMX7ULP_PAD_PTC10__FB_AD10 0x0028 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTC11__PTC11 0x002c 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTC11__TRACE_D4 0x002c 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTC11__FXIO1_D7 0x002c 0x0220 0x2 0x1 -#define IMX7ULP_PAD_PTC11__LPSPI2_PCS0 0x002c 0x029c 0x3 0x1 -#define IMX7ULP_PAD_PTC11__LPUART6_RX 0x002c 0x0260 0x4 0x1 -#define IMX7ULP_PAD_PTC11__TPM7_CH4 0x002c 0x02ec 0x6 0x1 -#define IMX7ULP_PAD_PTC11__FB_AD11 0x002c 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTC12__PTC12 0x0030 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTC12__TRACE_D3 0x0030 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTC12__FXIO1_D8 0x0030 0x0224 0x2 0x1 -#define IMX7ULP_PAD_PTC12__LPSPI3_PCS1 0x0030 0x0314 0x3 0x1 -#define IMX7ULP_PAD_PTC12__LPUART7_CTS_B 0x0030 0x0268 0x4 0x1 -#define IMX7ULP_PAD_PTC12__LPI2C7_SCL 0x0030 0x0308 0x5 0x1 -#define IMX7ULP_PAD_PTC12__TPM7_CH5 0x0030 0x02f0 0x6 0x1 -#define IMX7ULP_PAD_PTC12__FB_AD12 0x0030 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTC13__PTC13 0x0034 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTC13__TRACE_D2 0x0034 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTC13__FXIO1_D9 0x0034 0x0228 0x2 0x1 -#define IMX7ULP_PAD_PTC13__LPSPI3_PCS2 0x0034 0x0318 0x3 0x1 -#define IMX7ULP_PAD_PTC13__LPUART7_RTS_B 0x0034 0x0000 0x4 0x0 -#define IMX7ULP_PAD_PTC13__LPI2C7_SDA 0x0034 0x030c 0x5 0x1 -#define IMX7ULP_PAD_PTC13__TPM7_CLKIN 0x0034 0x02f4 0x6 0x1 -#define IMX7ULP_PAD_PTC13__FB_AD13 0x0034 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTC13__USB0_ID 0x0034 0x0338 0xb 0x1 -#define IMX7ULP_PAD_PTC14__PTC14 0x0038 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTC14__TRACE_D1 0x0038 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTC14__FXIO1_D10 0x0038 0x022c 0x2 0x1 -#define IMX7ULP_PAD_PTC14__LPSPI3_PCS3 0x0038 0x031c 0x3 0x1 -#define IMX7ULP_PAD_PTC14__LPUART7_TX 0x0038 0x0270 0x4 0x1 -#define IMX7ULP_PAD_PTC14__LPI2C7_HREQ 0x0038 0x0304 0x5 0x1 -#define IMX7ULP_PAD_PTC14__TPM7_CH0 0x0038 0x02dc 0x6 0x1 -#define IMX7ULP_PAD_PTC14__FB_AD14 0x0038 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTC15__PTC15 0x003c 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTC15__TRACE_D0 0x003c 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTC15__FXIO1_D11 0x003c 0x0230 0x2 0x1 -#define IMX7ULP_PAD_PTC15__LPUART7_RX 0x003c 0x026c 0x4 0x1 -#define IMX7ULP_PAD_PTC15__TPM7_CH1 0x003c 0x02e0 0x6 0x1 -#define IMX7ULP_PAD_PTC15__FB_AD15 0x003c 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTC16__PTC16 0x0040 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTC16__TRACE_CLKOUT 0x0040 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTC16__FXIO1_D12 0x0040 0x0234 0x2 0x1 -#define IMX7ULP_PAD_PTC16__LPSPI3_SIN 0x0040 0x0324 0x3 0x1 -#define IMX7ULP_PAD_PTC16__TPM7_CH2 0x0040 0x02e4 0x6 0x1 -#define IMX7ULP_PAD_PTC16__FB_ALE_FB_CS1_B_FB_TS_B 0x0040 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTC16__USB1_OC2 0x0040 0x0334 0xb 0x1 -#define IMX7ULP_PAD_PTC17__PTC17 0x0044 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTC17__FXIO1_D13 0x0044 0x0238 0x2 0x1 -#define IMX7ULP_PAD_PTC17__LPSPI3_SOUT 0x0044 0x0328 0x3 0x1 -#define IMX7ULP_PAD_PTC17__TPM6_CLKIN 0x0044 0x02d8 0x6 0x1 -#define IMX7ULP_PAD_PTC17__FB_CS0_B 0x0044 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTC18__PTC18 0x0048 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTC18__FXIO1_D14 0x0048 0x023c 0x2 0x1 -#define IMX7ULP_PAD_PTC18__LPSPI3_SCK 0x0048 0x0320 0x3 0x1 -#define IMX7ULP_PAD_PTC18__TPM6_CH0 0x0048 0x02d0 0x6 0x1 -#define IMX7ULP_PAD_PTC18__FB_OE_B 0x0048 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTC18__USB0_ID 0x0048 0x0338 0xb 0x2 -#define IMX7ULP_PAD_PTC18__VIU_DE 0x0048 0x033c 0xc 0x1 -#define IMX7ULP_PAD_PTC19__PTC19 0x004c 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTC19__FXIO1_D15 0x004c 0x0240 0x2 0x1 -#define IMX7ULP_PAD_PTC19__LPSPI3_PCS0 0x004c 0x0310 0x3 0x1 -#define IMX7ULP_PAD_PTC19__TPM6_CH1 0x004c 0x02d4 0x6 0x1 -#define IMX7ULP_PAD_PTC19__FB_A16 0x004c 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTC19__USB0_ID 0x004c 0x0338 0xa 0x3 -#define IMX7ULP_PAD_PTC19__USB1_PWR2 0x004c 0x0000 0xb 0x0 -#define IMX7ULP_PAD_PTC19__VIU_DE 0x004c 0x033c 0xc 0x3 -#define IMX7ULP_PAD_PTD0__PTD0 0x0080 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTD0__SDHC0_RESET_B 0x0080 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTD1__PTD1 0x0084 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTD1__SDHC0_CMD 0x0084 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTD2__PTD2 0x0088 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTD2__SDHC0_CLK 0x0088 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTD3__PTD3 0x008c 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTD3__SDHC0_D7 0x008c 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTD4__PTD4 0x0090 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTD4__SDHC0_D6 0x0090 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTD5__PTD5 0x0094 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTD5__SDHC0_D5 0x0094 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTD6__PTD6 0x0098 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTD6__SDHC0_D4 0x0098 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTD7__PTD7 0x009c 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTD7__SDHC0_D3 0x009c 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTD8__PTD8 0x00a0 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTD8__TPM4_CLKIN 0x00a0 0x0298 0x6 0x2 -#define IMX7ULP_PAD_PTD8__SDHC0_D2 0x00a0 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTD9__PTD9 0x00a4 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTD9__TPM4_CH0 0x00a4 0x0280 0x6 0x2 -#define IMX7ULP_PAD_PTD9__SDHC0_D1 0x00a4 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTD10__PTD10 0x00a8 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTD10__TPM4_CH1 0x00a8 0x0284 0x6 0x2 -#define IMX7ULP_PAD_PTD10__SDHC0_D0 0x00a8 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTD11__PTD11 0x00ac 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTD11__TPM4_CH2 0x00ac 0x0288 0x6 0x2 -#define IMX7ULP_PAD_PTD11__SDHC0_DQS 0x00ac 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTE0__PTE0 0x0100 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTE0__FXIO1_D31 0x0100 0x0000 0x2 0x0 -#define IMX7ULP_PAD_PTE0__LPSPI2_PCS1 0x0100 0x02a0 0x3 0x2 -#define IMX7ULP_PAD_PTE0__LPUART4_CTS_B 0x0100 0x0244 0x4 0x2 -#define IMX7ULP_PAD_PTE0__LPI2C4_SCL 0x0100 0x0278 0x5 0x2 -#define IMX7ULP_PAD_PTE0__SDHC1_D1 0x0100 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTE0__FB_A25 0x0100 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTE1__PTE1 0x0104 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTE1__FXIO1_D30 0x0104 0x0000 0x2 0x0 -#define IMX7ULP_PAD_PTE1__LPSPI2_PCS2 0x0104 0x02a4 0x3 0x2 -#define IMX7ULP_PAD_PTE1__LPUART4_RTS_B 0x0104 0x0000 0x4 0x0 -#define IMX7ULP_PAD_PTE1__LPI2C4_SDA 0x0104 0x027c 0x5 0x2 -#define IMX7ULP_PAD_PTE1__SDHC1_D0 0x0104 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTE1__FB_A26 0x0104 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTE2__PTE2 0x0108 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTE2__FXIO1_D29 0x0108 0x0000 0x2 0x0 -#define IMX7ULP_PAD_PTE2__LPSPI2_PCS3 0x0108 0x02a8 0x3 0x2 -#define IMX7ULP_PAD_PTE2__LPUART4_TX 0x0108 0x024c 0x4 0x2 -#define IMX7ULP_PAD_PTE2__LPI2C4_HREQ 0x0108 0x0274 0x5 0x2 -#define IMX7ULP_PAD_PTE2__SDHC1_CLK 0x0108 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTE3__PTE3 0x010c 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTE3__FXIO1_D28 0x010c 0x0000 0x2 0x0 -#define IMX7ULP_PAD_PTE3__LPUART4_RX 0x010c 0x0248 0x4 0x2 -#define IMX7ULP_PAD_PTE3__TPM5_CH1 0x010c 0x02c8 0x6 0x2 -#define IMX7ULP_PAD_PTE3__SDHC1_CMD 0x010c 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTE4__PTE4 0x0110 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTE4__FXIO1_D27 0x0110 0x0000 0x2 0x0 -#define IMX7ULP_PAD_PTE4__LPSPI2_SIN 0x0110 0x02b0 0x3 0x2 -#define IMX7ULP_PAD_PTE4__LPUART5_CTS_B 0x0110 0x0250 0x4 0x2 -#define IMX7ULP_PAD_PTE4__LPI2C5_SCL 0x0110 0x02bc 0x5 0x2 -#define IMX7ULP_PAD_PTE4__TPM5_CLKIN 0x0110 0x02cc 0x6 0x2 -#define IMX7ULP_PAD_PTE4__SDHC1_D3 0x0110 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTE5__PTE5 0x0114 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTE5__FXIO1_D26 0x0114 0x0000 0x2 0x0 -#define IMX7ULP_PAD_PTE5__LPSPI2_SOUT 0x0114 0x02b4 0x3 0x2 -#define IMX7ULP_PAD_PTE5__LPUART5_RTS_B 0x0114 0x0000 0x4 0x0 -#define IMX7ULP_PAD_PTE5__LPI2C5_SDA 0x0114 0x02c0 0x5 0x2 -#define IMX7ULP_PAD_PTE5__TPM5_CH0 0x0114 0x02c4 0x6 0x2 -#define IMX7ULP_PAD_PTE5__SDHC1_D2 0x0114 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTE5__VIU_DE 0x0114 0x033c 0xc 0x2 -#define IMX7ULP_PAD_PTE6__PTE6 0x0118 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTE6__FXIO1_D25 0x0118 0x0000 0x2 0x0 -#define IMX7ULP_PAD_PTE6__LPSPI2_SCK 0x0118 0x02ac 0x3 0x2 -#define IMX7ULP_PAD_PTE6__LPUART5_TX 0x0118 0x0258 0x4 0x2 -#define IMX7ULP_PAD_PTE6__LPI2C5_HREQ 0x0118 0x02b8 0x5 0x2 -#define IMX7ULP_PAD_PTE6__TPM7_CH3 0x0118 0x02e8 0x6 0x2 -#define IMX7ULP_PAD_PTE6__SDHC1_D4 0x0118 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTE6__FB_A17 0x0118 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTE6__USB0_OC 0x0118 0x0330 0xb 0x1 -#define IMX7ULP_PAD_PTE7__PTE7 0x011c 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTE7__TRACE_D7 0x011c 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTE7__USB0_PWR 0x011c 0x0000 0xb 0x0 -#define IMX7ULP_PAD_PTE7__VIU_FID 0x011c 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTE7__FXIO1_D24 0x011c 0x0000 0x2 0x0 -#define IMX7ULP_PAD_PTE7__LPSPI2_PCS0 0x011c 0x029c 0x3 0x2 -#define IMX7ULP_PAD_PTE7__LPUART5_RX 0x011c 0x0254 0x4 0x2 -#define IMX7ULP_PAD_PTE7__TPM7_CH4 0x011c 0x02ec 0x6 0x2 -#define IMX7ULP_PAD_PTE7__SDHC1_D5 0x011c 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTE7__FB_A18 0x011c 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTE8__PTE8 0x0120 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTE8__TRACE_D6 0x0120 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTE8__VIU_D16 0x0120 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTE8__FXIO1_D23 0x0120 0x0000 0x2 0x0 -#define IMX7ULP_PAD_PTE8__LPSPI3_PCS1 0x0120 0x0314 0x3 0x2 -#define IMX7ULP_PAD_PTE8__LPUART6_CTS_B 0x0120 0x025c 0x4 0x2 -#define IMX7ULP_PAD_PTE8__LPI2C6_SCL 0x0120 0x02fc 0x5 0x2 -#define IMX7ULP_PAD_PTE8__TPM7_CH5 0x0120 0x02f0 0x6 0x2 -#define IMX7ULP_PAD_PTE8__SDHC1_WP 0x0120 0x0200 0x7 0x1 -#define IMX7ULP_PAD_PTE8__SDHC1_D6 0x0120 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTE8__FB_CS3_B_FB_BE7_0_BLS31_24_B 0x0120 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTE9__PTE9 0x0124 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTE9__TRACE_D5 0x0124 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTE9__VIU_D17 0x0124 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTE9__FXIO1_D22 0x0124 0x0000 0x2 0x0 -#define IMX7ULP_PAD_PTE9__LPSPI3_PCS2 0x0124 0x0318 0x3 0x2 -#define IMX7ULP_PAD_PTE9__LPUART6_RTS_B 0x0124 0x0000 0x4 0x0 -#define IMX7ULP_PAD_PTE9__LPI2C6_SDA 0x0124 0x0300 0x5 0x2 -#define IMX7ULP_PAD_PTE9__TPM7_CLKIN 0x0124 0x02f4 0x6 0x2 -#define IMX7ULP_PAD_PTE9__SDHC1_CD 0x0124 0x032c 0x7 0x1 -#define IMX7ULP_PAD_PTE9__SDHC1_D7 0x0124 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTE9__FB_TBST_B_FB_CS2_B_FB_BE15_8_BLS23_16_B 0x0124 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTE10__PTE10 0x0128 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTE10__TRACE_D4 0x0128 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTE10__VIU_D18 0x0128 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTE10__FXIO1_D21 0x0128 0x0000 0x2 0x0 -#define IMX7ULP_PAD_PTE10__LPSPI3_PCS3 0x0128 0x031c 0x3 0x2 -#define IMX7ULP_PAD_PTE10__LPUART6_TX 0x0128 0x0264 0x4 0x2 -#define IMX7ULP_PAD_PTE10__LPI2C6_HREQ 0x0128 0x02f8 0x5 0x2 -#define IMX7ULP_PAD_PTE10__TPM7_CH0 0x0128 0x02dc 0x6 0x2 -#define IMX7ULP_PAD_PTE10__SDHC1_VS 0x0128 0x0000 0x7 0x0 -#define IMX7ULP_PAD_PTE10__SDHC1_DQS 0x0128 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTE10__FB_A19 0x0128 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTE11__PTE11 0x012c 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTE11__TRACE_D3 0x012c 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTE11__VIU_D19 0x012c 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTE11__FXIO1_D20 0x012c 0x0000 0x2 0x0 -#define IMX7ULP_PAD_PTE11__LPUART6_RX 0x012c 0x0260 0x4 0x2 -#define IMX7ULP_PAD_PTE11__TPM7_CH1 0x012c 0x02e0 0x6 0x2 -#define IMX7ULP_PAD_PTE11__SDHC1_RESET_B 0x012c 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTE11__FB_A20 0x012c 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTE12__PTE12 0x0130 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTE12__TRACE_D2 0x0130 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTE12__USB1_OC2 0x0130 0x0334 0xb 0x2 -#define IMX7ULP_PAD_PTE12__VIU_D20 0x0130 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTE12__FXIO1_D19 0x0130 0x0000 0x2 0x0 -#define IMX7ULP_PAD_PTE12__LPSPI3_SIN 0x0130 0x0324 0x3 0x2 -#define IMX7ULP_PAD_PTE12__LPUART7_CTS_B 0x0130 0x0268 0x4 0x2 -#define IMX7ULP_PAD_PTE12__LPI2C7_SCL 0x0130 0x0308 0x5 0x2 -#define IMX7ULP_PAD_PTE12__TPM7_CH2 0x0130 0x02e4 0x6 0x2 -#define IMX7ULP_PAD_PTE12__SDHC1_WP 0x0130 0x0200 0x8 0x2 -#define IMX7ULP_PAD_PTE12__FB_A21 0x0130 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTE13__PTE13 0x0134 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTE13__TRACE_D1 0x0134 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTE13__USB1_PWR2 0x0134 0x0000 0xb 0x0 -#define IMX7ULP_PAD_PTE13__VIU_D21 0x0134 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTE13__FXIO1_D18 0x0134 0x0000 0x2 0x0 -#define IMX7ULP_PAD_PTE13__LPSPI3_SOUT 0x0134 0x0328 0x3 0x2 -#define IMX7ULP_PAD_PTE13__LPUART7_RTS_B 0x0134 0x0000 0x4 0x0 -#define IMX7ULP_PAD_PTE13__LPI2C7_SDA 0x0134 0x030c 0x5 0x2 -#define IMX7ULP_PAD_PTE13__TPM6_CLKIN 0x0134 0x02d8 0x6 0x2 -#define IMX7ULP_PAD_PTE13__SDHC1_CD 0x0134 0x032c 0x8 0x2 -#define IMX7ULP_PAD_PTE13__FB_A22 0x0134 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTE14__PTE14 0x0138 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTE14__TRACE_D0 0x0138 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTE14__USB0_OC 0x0138 0x0330 0xb 0x2 -#define IMX7ULP_PAD_PTE14__VIU_D22 0x0138 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTE14__FXIO1_D17 0x0138 0x0000 0x2 0x0 -#define IMX7ULP_PAD_PTE14__LPSPI3_SCK 0x0138 0x0320 0x3 0x2 -#define IMX7ULP_PAD_PTE14__LPUART7_TX 0x0138 0x0270 0x4 0x2 -#define IMX7ULP_PAD_PTE14__LPI2C7_HREQ 0x0138 0x0304 0x5 0x2 -#define IMX7ULP_PAD_PTE14__TPM6_CH0 0x0138 0x02d0 0x6 0x2 -#define IMX7ULP_PAD_PTE14__SDHC1_VS 0x0138 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTE14__FB_A23 0x0138 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTE15__PTE15 0x013c 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTE15__TRACE_CLKOUT 0x013c 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTE15__USB0_PWR 0x013c 0x0000 0xb 0x0 -#define IMX7ULP_PAD_PTE15__VIU_D23 0x013c 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTE15__FXIO1_D16 0x013c 0x0000 0x2 0x0 -#define IMX7ULP_PAD_PTE15__LPSPI3_PCS0 0x013c 0x0310 0x3 0x2 -#define IMX7ULP_PAD_PTE15__LPUART7_RX 0x013c 0x026c 0x4 0x2 -#define IMX7ULP_PAD_PTE15__TPM6_CH1 0x013c 0x02d4 0x6 0x2 -#define IMX7ULP_PAD_PTE15__FB_A24 0x013c 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTF0__PTF0 0x0180 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTF0__VIU_DE 0x0180 0x033c 0xc 0x0 -#define IMX7ULP_PAD_PTF0__LPUART4_CTS_B 0x0180 0x0244 0x4 0x3 -#define IMX7ULP_PAD_PTF0__LPI2C4_SCL 0x0180 0x0278 0x5 0x3 -#define IMX7ULP_PAD_PTF0__TPM4_CLKIN 0x0180 0x0298 0x6 0x3 -#define IMX7ULP_PAD_PTF0__FB_RW_B 0x0180 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTF1__PTF1 0x0184 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTF1__VIU_HSYNC 0x0184 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTF1__LPUART4_RTS_B 0x0184 0x0000 0x4 0x0 -#define IMX7ULP_PAD_PTF1__LPI2C4_SDA 0x0184 0x027c 0x5 0x3 -#define IMX7ULP_PAD_PTF1__TPM4_CH0 0x0184 0x0280 0x6 0x3 -#define IMX7ULP_PAD_PTF1__CLKOUT 0x0184 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTF2__PTF2 0x0188 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTF2__VIU_VSYNC 0x0188 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTF2__LPUART4_TX 0x0188 0x024c 0x4 0x3 -#define IMX7ULP_PAD_PTF2__LPI2C4_HREQ 0x0188 0x0274 0x5 0x3 -#define IMX7ULP_PAD_PTF2__TPM4_CH1 0x0188 0x0284 0x6 0x3 -#define IMX7ULP_PAD_PTF2__FB_TSIZ1_FB_CS5_B_FB_BE23_16_BLS15_8_B 0x0188 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTF3__PTF3 0x018c 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTF3__VIU_PCLK 0x018c 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTF3__LPUART4_RX 0x018c 0x0248 0x4 0x3 -#define IMX7ULP_PAD_PTF3__TPM4_CH2 0x018c 0x0288 0x6 0x3 -#define IMX7ULP_PAD_PTF3__FB_AD16 0x018c 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTF4__PTF4 0x0190 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTF4__VIU_D0 0x0190 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTF4__FXIO1_D0 0x0190 0x0204 0x2 0x2 -#define IMX7ULP_PAD_PTF4__LPSPI2_PCS1 0x0190 0x02a0 0x3 0x3 -#define IMX7ULP_PAD_PTF4__LPUART5_CTS_B 0x0190 0x0250 0x4 0x3 -#define IMX7ULP_PAD_PTF4__LPI2C5_SCL 0x0190 0x02bc 0x5 0x3 -#define IMX7ULP_PAD_PTF4__TPM4_CH3 0x0190 0x028c 0x6 0x2 -#define IMX7ULP_PAD_PTF4__FB_AD17 0x0190 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTF5__PTF5 0x0194 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTF5__VIU_D1 0x0194 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTF5__FXIO1_D1 0x0194 0x0208 0x2 0x2 -#define IMX7ULP_PAD_PTF5__LPSPI2_PCS2 0x0194 0x02a4 0x3 0x3 -#define IMX7ULP_PAD_PTF5__LPUART5_RTS_B 0x0194 0x0000 0x4 0x0 -#define IMX7ULP_PAD_PTF5__LPI2C5_SDA 0x0194 0x02c0 0x5 0x3 -#define IMX7ULP_PAD_PTF5__TPM4_CH4 0x0194 0x0290 0x6 0x2 -#define IMX7ULP_PAD_PTF5__FB_AD18 0x0194 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTF6__PTF6 0x0198 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTF6__VIU_D2 0x0198 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTF6__FXIO1_D2 0x0198 0x020c 0x2 0x2 -#define IMX7ULP_PAD_PTF6__LPSPI2_PCS3 0x0198 0x02a8 0x3 0x3 -#define IMX7ULP_PAD_PTF6__LPUART5_TX 0x0198 0x0258 0x4 0x3 -#define IMX7ULP_PAD_PTF6__LPI2C5_HREQ 0x0198 0x02b8 0x5 0x3 -#define IMX7ULP_PAD_PTF6__TPM4_CH5 0x0198 0x0294 0x6 0x2 -#define IMX7ULP_PAD_PTF6__FB_AD19 0x0198 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTF7__PTF7 0x019c 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTF7__VIU_D3 0x019c 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTF7__FXIO1_D3 0x019c 0x0210 0x2 0x2 -#define IMX7ULP_PAD_PTF7__LPUART5_RX 0x019c 0x0254 0x4 0x3 -#define IMX7ULP_PAD_PTF7__TPM5_CH1 0x019c 0x02c8 0x6 0x3 -#define IMX7ULP_PAD_PTF7__FB_AD20 0x019c 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTF8__PTF8 0x01a0 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTF8__USB1_ULPI_CLK 0x01a0 0x0000 0xb 0x0 -#define IMX7ULP_PAD_PTF8__VIU_D4 0x01a0 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTF8__FXIO1_D4 0x01a0 0x0214 0x2 0x2 -#define IMX7ULP_PAD_PTF8__LPSPI2_SIN 0x01a0 0x02b0 0x3 0x3 -#define IMX7ULP_PAD_PTF8__LPUART6_CTS_B 0x01a0 0x025c 0x4 0x3 -#define IMX7ULP_PAD_PTF8__LPI2C6_SCL 0x01a0 0x02fc 0x5 0x3 -#define IMX7ULP_PAD_PTF8__TPM5_CLKIN 0x01a0 0x02cc 0x6 0x3 -#define IMX7ULP_PAD_PTF8__FB_AD21 0x01a0 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTF9__PTF9 0x01a4 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTF9__USB1_ULPI_NXT 0x01a4 0x0000 0xb 0x0 -#define IMX7ULP_PAD_PTF9__VIU_D5 0x01a4 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTF9__FXIO1_D5 0x01a4 0x0218 0x2 0x2 -#define IMX7ULP_PAD_PTF9__LPSPI2_SOUT 0x01a4 0x02b4 0x3 0x3 -#define IMX7ULP_PAD_PTF9__LPUART6_RTS_B 0x01a4 0x0000 0x4 0x0 -#define IMX7ULP_PAD_PTF9__LPI2C6_SDA 0x01a4 0x0300 0x5 0x3 -#define IMX7ULP_PAD_PTF9__TPM5_CH0 0x01a4 0x02c4 0x6 0x3 -#define IMX7ULP_PAD_PTF9__FB_AD22 0x01a4 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTF10__PTF10 0x01a8 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTF10__USB1_ULPI_STP 0x01a8 0x0000 0xb 0x0 -#define IMX7ULP_PAD_PTF10__VIU_D6 0x01a8 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTF10__FXIO1_D6 0x01a8 0x021c 0x2 0x2 -#define IMX7ULP_PAD_PTF10__LPSPI2_SCK 0x01a8 0x02ac 0x3 0x3 -#define IMX7ULP_PAD_PTF10__LPUART6_TX 0x01a8 0x0264 0x4 0x3 -#define IMX7ULP_PAD_PTF10__LPI2C6_HREQ 0x01a8 0x02f8 0x5 0x3 -#define IMX7ULP_PAD_PTF10__TPM7_CH3 0x01a8 0x02e8 0x6 0x3 -#define IMX7ULP_PAD_PTF10__FB_AD23 0x01a8 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTF11__PTF11 0x01ac 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTF11__USB1_ULPI_DIR 0x01ac 0x0000 0xb 0x0 -#define IMX7ULP_PAD_PTF11__VIU_D7 0x01ac 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTF11__FXIO1_D7 0x01ac 0x0220 0x2 0x2 -#define IMX7ULP_PAD_PTF11__LPSPI2_PCS0 0x01ac 0x029c 0x3 0x3 -#define IMX7ULP_PAD_PTF11__LPUART6_RX 0x01ac 0x0260 0x4 0x3 -#define IMX7ULP_PAD_PTF11__TPM7_CH4 0x01ac 0x02ec 0x6 0x3 -#define IMX7ULP_PAD_PTF11__FB_CS4_B_FB_TSIZ0_FB_BE31_24_BLS7_0_B 0x01ac 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTF12__PTF12 0x01b0 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTF12__USB1_ULPI_DATA0 0x01b0 0x0000 0xb 0x0 -#define IMX7ULP_PAD_PTF12__VIU_D8 0x01b0 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTF12__FXIO1_D8 0x01b0 0x0224 0x2 0x2 -#define IMX7ULP_PAD_PTF12__LPSPI3_PCS1 0x01b0 0x0314 0x3 0x3 -#define IMX7ULP_PAD_PTF12__LPUART7_CTS_B 0x01b0 0x0268 0x4 0x3 -#define IMX7ULP_PAD_PTF12__LPI2C7_SCL 0x01b0 0x0308 0x5 0x3 -#define IMX7ULP_PAD_PTF12__TPM7_CH5 0x01b0 0x02f0 0x6 0x3 -#define IMX7ULP_PAD_PTF12__FB_AD24 0x01b0 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTF13__PTF13 0x01b4 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTF13__USB1_ULPI_DATA1 0x01b4 0x0000 0xb 0x0 -#define IMX7ULP_PAD_PTF13__VIU_D9 0x01b4 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTF13__FXIO1_D9 0x01b4 0x0228 0x2 0x2 -#define IMX7ULP_PAD_PTF13__LPSPI3_PCS2 0x01b4 0x0318 0x3 0x3 -#define IMX7ULP_PAD_PTF13__LPUART7_RTS_B 0x01b4 0x0000 0x4 0x0 -#define IMX7ULP_PAD_PTF13__LPI2C7_SDA 0x01b4 0x030c 0x5 0x3 -#define IMX7ULP_PAD_PTF13__TPM7_CLKIN 0x01b4 0x02f4 0x6 0x3 -#define IMX7ULP_PAD_PTF13__FB_AD25 0x01b4 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTF14__PTF14 0x01b8 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTF14__USB1_ULPI_DATA2 0x01b8 0x0000 0xb 0x0 -#define IMX7ULP_PAD_PTF14__VIU_D10 0x01b8 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTF14__FXIO1_D10 0x01b8 0x022c 0x2 0x2 -#define IMX7ULP_PAD_PTF14__LPSPI3_PCS3 0x01b8 0x031c 0x3 0x3 -#define IMX7ULP_PAD_PTF14__LPUART7_TX 0x01b8 0x0270 0x4 0x3 -#define IMX7ULP_PAD_PTF14__LPI2C7_HREQ 0x01b8 0x0304 0x5 0x3 -#define IMX7ULP_PAD_PTF14__TPM7_CH0 0x01b8 0x02dc 0x6 0x3 -#define IMX7ULP_PAD_PTF14__FB_AD26 0x01b8 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTF15__PTF15 0x01bc 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTF15__USB1_ULPI_DATA3 0x01bc 0x0000 0xb 0x0 -#define IMX7ULP_PAD_PTF15__VIU_D11 0x01bc 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTF15__FXIO1_D11 0x01bc 0x0230 0x2 0x2 -#define IMX7ULP_PAD_PTF15__LPUART7_RX 0x01bc 0x026c 0x4 0x3 -#define IMX7ULP_PAD_PTF15__TPM7_CH1 0x01bc 0x02e0 0x6 0x3 -#define IMX7ULP_PAD_PTF15__FB_AD27 0x01bc 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTF16__PTF16 0x01c0 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTF16__USB1_ULPI_DATA4 0x01c0 0x0000 0xb 0x0 -#define IMX7ULP_PAD_PTF16__VIU_D12 0x01c0 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTF16__FXIO1_D12 0x01c0 0x0234 0x2 0x2 -#define IMX7ULP_PAD_PTF16__LPSPI3_SIN 0x01c0 0x0324 0x3 0x3 -#define IMX7ULP_PAD_PTF16__TPM7_CH2 0x01c0 0x02e4 0x6 0x3 -#define IMX7ULP_PAD_PTF16__FB_AD28 0x01c0 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTF17__PTF17 0x01c4 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTF17__USB1_ULPI_DATA5 0x01c4 0x0000 0xb 0x0 -#define IMX7ULP_PAD_PTF17__VIU_D13 0x01c4 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTF17__FXIO1_D13 0x01c4 0x0238 0x2 0x2 -#define IMX7ULP_PAD_PTF17__LPSPI3_SOUT 0x01c4 0x0328 0x3 0x3 -#define IMX7ULP_PAD_PTF17__TPM6_CLKIN 0x01c4 0x02d8 0x6 0x3 -#define IMX7ULP_PAD_PTF17__FB_AD29 0x01c4 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTF18__PTF18 0x01c8 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTF18__USB1_ULPI_DATA6 0x01c8 0x0000 0xb 0x0 -#define IMX7ULP_PAD_PTF18__VIU_D14 0x01c8 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTF18__FXIO1_D14 0x01c8 0x023c 0x2 0x2 -#define IMX7ULP_PAD_PTF18__LPSPI3_SCK 0x01c8 0x0320 0x3 0x3 -#define IMX7ULP_PAD_PTF18__TPM6_CH0 0x01c8 0x02d0 0x6 0x3 -#define IMX7ULP_PAD_PTF18__FB_AD30 0x01c8 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTF19__PTF19 0x01cc 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTF19__USB1_ULPI_DATA7 0x01cc 0x0000 0xb 0x0 -#define IMX7ULP_PAD_PTF19__VIU_D15 0x01cc 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTF19__FXIO1_D15 0x01cc 0x0240 0x2 0x2 -#define IMX7ULP_PAD_PTF19__LPSPI3_PCS0 0x01cc 0x0310 0x3 0x3 -#define IMX7ULP_PAD_PTF19__TPM6_CH1 0x01cc 0x02d4 0x6 0x3 -#define IMX7ULP_PAD_PTF19__FB_AD31 0x01cc 0x0000 0x9 0x0 - -#endif /* __DTS_IMX7ULP_PINFUNC_H */ diff --git a/sys/gnu/dts/arm/imx7ulp.dtsi b/sys/gnu/dts/arm/imx7ulp.dtsi deleted file mode 100644 index ab91c98f212..00000000000 --- a/sys/gnu/dts/arm/imx7ulp.dtsi +++ /dev/null @@ -1,461 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2016 Freescale Semiconductor, Inc. - * Copyright 2017-2018 NXP - * Dong Aisheng - */ - -#include -#include -#include - -#include "imx7ulp-pinfunc.h" - -/ { - interrupt-parent = <&intc>; - - #address-cells = <1>; - #size-cells = <1>; - - aliases { - gpio0 = &gpio_ptc; - gpio1 = &gpio_ptd; - gpio2 = &gpio_pte; - gpio3 = &gpio_ptf; - i2c0 = &lpi2c6; - i2c1 = &lpi2c7; - mmc0 = &usdhc0; - mmc1 = &usdhc1; - serial0 = &lpuart4; - serial1 = &lpuart5; - serial2 = &lpuart6; - serial3 = &lpuart7; - usbphy0 = &usbphy1; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@f00 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <0xf00>; - }; - }; - - intc: interrupt-controller@40021000 { - compatible = "arm,cortex-a7-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x40021000 0x1000>, - <0x40022000 0x1000>; - }; - - rosc: clock-rosc { - compatible = "fixed-clock"; - clock-frequency = <32768>; - clock-output-names = "rosc"; - #clock-cells = <0>; - }; - - sosc: clock-sosc { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "sosc"; - #clock-cells = <0>; - }; - - sirc: clock-sirc { - compatible = "fixed-clock"; - clock-frequency = <16000000>; - clock-output-names = "sirc"; - #clock-cells = <0>; - }; - - firc: clock-firc { - compatible = "fixed-clock"; - clock-frequency = <48000000>; - clock-output-names = "firc"; - #clock-cells = <0>; - }; - - upll: clock-upll { - compatible = "fixed-clock"; - clock-frequency = <480000000>; - clock-output-names = "upll"; - #clock-cells = <0>; - }; - - ahbbridge0: bus@40000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x40000000 0x800000>; - ranges; - - edma1: dma-controller@40080000 { - #dma-cells = <2>; - compatible = "fsl,imx7ulp-edma"; - reg = <0x40080000 0x2000>, - <0x40210000 0x1000>; - dma-channels = <32>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - clock-names = "dma", "dmamux0"; - clocks = <&pcc2 IMX7ULP_CLK_DMA1>, - <&pcc2 IMX7ULP_CLK_DMA_MUX1>; - }; - - crypto: crypto@40240000 { - compatible = "fsl,sec-v4.0"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x40240000 0x10000>; - ranges = <0 0x40240000 0x10000>; - clocks = <&pcc2 IMX7ULP_CLK_CAAM>, - <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>; - clock-names = "aclk", "ipg"; - - sec_jr0: jr0@1000 { - compatible = "fsl,sec-v4.0-job-ring"; - reg = <0x1000 0x1000>; - interrupts = ; - }; - - sec_jr1: jr1@2000 { - compatible = "fsl,sec-v4.0-job-ring"; - reg = <0x2000 0x1000>; - interrupts = ; - }; - }; - - lpuart4: serial@402d0000 { - compatible = "fsl,imx7ulp-lpuart"; - reg = <0x402d0000 0x1000>; - interrupts = ; - clocks = <&pcc2 IMX7ULP_CLK_LPUART4>; - clock-names = "ipg"; - assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART4>; - assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>; - assigned-clock-rates = <24000000>; - status = "disabled"; - }; - - lpuart5: serial@402e0000 { - compatible = "fsl,imx7ulp-lpuart"; - reg = <0x402e0000 0x1000>; - interrupts = ; - clocks = <&pcc2 IMX7ULP_CLK_LPUART5>; - clock-names = "ipg"; - assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART5>; - assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>; - assigned-clock-rates = <48000000>; - status = "disabled"; - }; - - tpm4: pwm@40250000 { - compatible = "fsl,imx7ulp-pwm"; - reg = <0x40250000 0x1000>; - assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>; - assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>; - clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>; - #pwm-cells = <3>; - status = "disabled"; - }; - - tpm5: tpm@40260000 { - compatible = "fsl,imx7ulp-tpm"; - reg = <0x40260000 0x1000>; - interrupts = ; - clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>, - <&pcc2 IMX7ULP_CLK_LPTPM5>; - clock-names = "ipg", "per"; - }; - - usbotg1: usb@40330000 { - compatible = "fsl,imx7ulp-usb", "fsl,imx6ul-usb"; - reg = <0x40330000 0x200>; - interrupts = ; - clocks = <&pcc2 IMX7ULP_CLK_USB0>; - phys = <&usbphy1>; - fsl,usbmisc = <&usbmisc1 0>; - ahb-burst-config = <0x0>; - tx-burst-size-dword = <0x8>; - rx-burst-size-dword = <0x8>; - status = "disabled"; - }; - - usbmisc1: usbmisc@40330200 { - compatible = "fsl,imx7ulp-usbmisc", "fsl,imx7d-usbmisc"; - #index-cells = <1>; - reg = <0x40330200 0x200>; - }; - - usbphy1: usb-phy@40350000 { - compatible = "fsl,imx7ulp-usbphy", "fsl,imx6ul-usbphy"; - reg = <0x40350000 0x1000>; - interrupts = ; - clocks = <&pcc2 IMX7ULP_CLK_USB_PHY>; - #phy-cells = <0>; - }; - - usdhc0: mmc@40370000 { - compatible = "fsl,imx7ulp-usdhc", "fsl,imx6sx-usdhc"; - reg = <0x40370000 0x10000>; - interrupts = ; - clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>, - <&scg1 IMX7ULP_CLK_NIC1_DIV>, - <&pcc2 IMX7ULP_CLK_USDHC0>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - fsl,tuning-start-tap = <20>; - fsl,tuning-step = <2>; - status = "disabled"; - }; - - usdhc1: mmc@40380000 { - compatible = "fsl,imx7ulp-usdhc", "fsl,imx6sx-usdhc"; - reg = <0x40380000 0x10000>; - interrupts = ; - clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>, - <&scg1 IMX7ULP_CLK_NIC1_DIV>, - <&pcc2 IMX7ULP_CLK_USDHC1>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - fsl,tuning-start-tap = <20>; - fsl,tuning-step = <2>; - status = "disabled"; - }; - - scg1: clock-controller@403e0000 { - compatible = "fsl,imx7ulp-scg1"; - reg = <0x403e0000 0x10000>; - clocks = <&rosc>, <&sosc>, <&sirc>, - <&firc>, <&upll>; - clock-names = "rosc", "sosc", "sirc", - "firc", "upll"; - #clock-cells = <1>; - }; - - wdog1: watchdog@403d0000 { - compatible = "fsl,imx7ulp-wdt"; - reg = <0x403d0000 0x10000>; - interrupts = ; - clocks = <&pcc2 IMX7ULP_CLK_WDG1>; - assigned-clocks = <&pcc2 IMX7ULP_CLK_WDG1>; - assigned-clocks-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>; - timeout-sec = <40>; - }; - - pcc2: clock-controller@403f0000 { - compatible = "fsl,imx7ulp-pcc2"; - reg = <0x403f0000 0x10000>; - #clock-cells = <1>; - clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>, - <&scg1 IMX7ULP_CLK_NIC1_DIV>, - <&scg1 IMX7ULP_CLK_DDR_DIV>, - <&scg1 IMX7ULP_CLK_APLL_PFD2>, - <&scg1 IMX7ULP_CLK_APLL_PFD1>, - <&scg1 IMX7ULP_CLK_APLL_PFD0>, - <&scg1 IMX7ULP_CLK_UPLL>, - <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>, - <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>, - <&scg1 IMX7ULP_CLK_ROSC>, - <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>; - clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk", - "apll_pfd2", "apll_pfd1", "apll_pfd0", - "upll", "sosc_bus_clk", - "firc_bus_clk", "rosc", "spll_bus_clk"; - assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM5>; - assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>; - }; - - smc1: clock-controller@40410000 { - compatible = "fsl,imx7ulp-smc1"; - reg = <0x40410000 0x1000>; - #clock-cells = <1>; - clocks = <&scg1 IMX7ULP_CLK_CORE_DIV>, - <&scg1 IMX7ULP_CLK_HSRUN_CORE_DIV>; - clock-names = "divcore", "hsrun_divcore"; - }; - - pcc3: clock-controller@40b30000 { - compatible = "fsl,imx7ulp-pcc3"; - reg = <0x40b30000 0x10000>; - #clock-cells = <1>; - clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>, - <&scg1 IMX7ULP_CLK_NIC1_DIV>, - <&scg1 IMX7ULP_CLK_DDR_DIV>, - <&scg1 IMX7ULP_CLK_APLL_PFD2>, - <&scg1 IMX7ULP_CLK_APLL_PFD1>, - <&scg1 IMX7ULP_CLK_APLL_PFD0>, - <&scg1 IMX7ULP_CLK_UPLL>, - <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>, - <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>, - <&scg1 IMX7ULP_CLK_ROSC>, - <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>; - clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk", - "apll_pfd2", "apll_pfd1", "apll_pfd0", - "upll", "sosc_bus_clk", - "firc_bus_clk", "rosc", "spll_bus_clk"; - }; - }; - - ahbbridge1: bus@40800000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x40800000 0x800000>; - ranges; - - lpi2c6: i2c@40a40000 { - compatible = "fsl,imx7ulp-lpi2c"; - reg = <0x40a40000 0x10000>; - interrupts = ; - clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>; - clock-names = "ipg"; - assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>; - assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>; - assigned-clock-rates = <48000000>; - status = "disabled"; - }; - - lpi2c7: i2c@40a50000 { - compatible = "fsl,imx7ulp-lpi2c"; - reg = <0x40a50000 0x10000>; - interrupts = ; - clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>; - clock-names = "ipg"; - assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>; - assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>; - assigned-clock-rates = <48000000>; - status = "disabled"; - }; - - lpuart6: serial@40a60000 { - compatible = "fsl,imx7ulp-lpuart"; - reg = <0x40a60000 0x1000>; - interrupts = ; - clocks = <&pcc3 IMX7ULP_CLK_LPUART6>; - clock-names = "ipg"; - assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART6>; - assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>; - assigned-clock-rates = <48000000>; - status = "disabled"; - }; - - lpuart7: serial@40a70000 { - compatible = "fsl,imx7ulp-lpuart"; - reg = <0x40a70000 0x1000>; - interrupts = ; - clocks = <&pcc3 IMX7ULP_CLK_LPUART7>; - clock-names = "ipg"; - assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART7>; - assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>; - assigned-clock-rates = <48000000>; - status = "disabled"; - }; - - memory-controller@40ab0000 { - compatible = "fsl,imx7ulp-mmdc", "fsl,imx6q-mmdc"; - reg = <0x40ab0000 0x1000>; - clocks = <&pcc3 IMX7ULP_CLK_MMDC>; - }; - - iomuxc1: pinctrl@40ac0000 { - compatible = "fsl,imx7ulp-iomuxc1"; - reg = <0x40ac0000 0x1000>; - }; - - gpio_ptc: gpio@40ae0000 { - compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio"; - reg = <0x40ae0000 0x1000 0x400f0000 0x40>; - gpio-controller; - #gpio-cells = <2>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>, - <&pcc3 IMX7ULP_CLK_PCTLC>; - clock-names = "gpio", "port"; - gpio-ranges = <&iomuxc1 0 0 32>; - }; - - gpio_ptd: gpio@40af0000 { - compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio"; - reg = <0x40af0000 0x1000 0x400f0040 0x40>; - gpio-controller; - #gpio-cells = <2>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>, - <&pcc3 IMX7ULP_CLK_PCTLD>; - clock-names = "gpio", "port"; - gpio-ranges = <&iomuxc1 0 32 32>; - }; - - gpio_pte: gpio@40b00000 { - compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio"; - reg = <0x40b00000 0x1000 0x400f0080 0x40>; - gpio-controller; - #gpio-cells = <2>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>, - <&pcc3 IMX7ULP_CLK_PCTLE>; - clock-names = "gpio", "port"; - gpio-ranges = <&iomuxc1 0 64 32>; - }; - - gpio_ptf: gpio@40b10000 { - compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio"; - reg = <0x40b10000 0x1000 0x400f00c0 0x40>; - gpio-controller; - #gpio-cells = <2>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>, - <&pcc3 IMX7ULP_CLK_PCTLF>; - clock-names = "gpio", "port"; - gpio-ranges = <&iomuxc1 0 96 32>; - }; - }; - - m4aips1: bus@41080000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x41080000 0x80000>; - ranges; - - sim: sim@410a3000 { - compatible = "fsl,imx7ulp-sim", "syscon"; - reg = <0x410a3000 0x1000>; - }; - - ocotp: ocotp-ctrl@410a6000 { - compatible = "fsl,imx7ulp-ocotp", "syscon"; - reg = <0x410a6000 0x4000>; - clocks = <&scg1 IMX7ULP_CLK_DUMMY>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/integrator.dtsi b/sys/gnu/dts/arm/integrator.dtsi deleted file mode 100644 index 602f74d2c75..00000000000 --- a/sys/gnu/dts/arm/integrator.dtsi +++ /dev/null @@ -1,143 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * SoC core Device Tree for the ARM Integrator platforms - */ - -/ { - #address-cells = <1>; - #size-cells = <1>; - - memory { - device_type = "memory"; - reg = <0x0 0x0>; - }; - - core-module@10000000 { - compatible = "arm,core-module-integrator", "syscon", "simple-mfd"; - reg = <0x10000000 0x200>; - - /* Use core module LED to indicate CPU load */ - led@c.0 { - compatible = "register-bit-led"; - offset = <0x0c>; - mask = <0x01>; - label = "integrator:core_module"; - linux,default-trigger = "cpu0"; - default-state = "on"; - }; - }; - - ebi@12000000 { - compatible = "arm,external-bus-interface"; - reg = <0x12000000 0x100>; - }; - - timer@13000000 { - reg = <0x13000000 0x100>; - interrupt-parent = <&pic>; - interrupts = <5>; - }; - - timer@13000100 { - reg = <0x13000100 0x100>; - interrupt-parent = <&pic>; - interrupts = <6>; - }; - - timer@13000200 { - reg = <0x13000200 0x100>; - interrupt-parent = <&pic>; - interrupts = <7>; - }; - - pic@14000000 { - compatible = "arm,versatile-fpga-irq"; - #interrupt-cells = <1>; - interrupt-controller; - reg = <0x14000000 0x100>; - clear-mask = <0xffffffff>; - }; - - flash@24000000 { - compatible = "arm,versatile-flash", "cfi-flash"; - reg = <0x24000000 0x02000000>; - bank-width = <4>; - partitions { - compatible = "arm,arm-firmware-suite"; - }; - }; - - fpga { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - interrupt-parent = <&pic>; - - /* - * These PrimeCells are in the same locations and using the - * same interrupts in all Integrators, however the silicon - * version deployed is different. - */ - rtc@15000000 { - reg = <0x15000000 0x1000>; - interrupts = <8>; - }; - - uart@16000000 { - reg = <0x16000000 0x1000>; - interrupts = <1>; - }; - - uart@17000000 { - reg = <0x17000000 0x1000>; - interrupts = <2>; - }; - - kmi@18000000 { - reg = <0x18000000 0x1000>; - interrupts = <3>; - }; - - kmi@19000000 { - reg = <0x19000000 0x1000>; - interrupts = <4>; - }; - - syscon { - /* Debug registers mapped as syscon */ - compatible = "syscon", "simple-mfd"; - reg = <0x1a000000 0x10>; - - led@4.0 { - compatible = "register-bit-led"; - offset = <0x04>; - mask = <0x01>; - label = "integrator:green0"; - linux,default-trigger = "heartbeat"; - default-state = "on"; - }; - led@4.1 { - compatible = "register-bit-led"; - offset = <0x04>; - mask = <0x02>; - label = "integrator:yellow"; - default-state = "off"; - }; - led@4.2 { - compatible = "register-bit-led"; - offset = <0x04>; - mask = <0x04>; - label = "integrator:red"; - default-state = "off"; - }; - led@4.3 { - compatible = "register-bit-led"; - offset = <0x04>; - mask = <0x08>; - label = "integrator:green1"; - default-state = "off"; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/integratorap.dts b/sys/gnu/dts/arm/integratorap.dts deleted file mode 100644 index 94d2ff9836d..00000000000 --- a/sys/gnu/dts/arm/integratorap.dts +++ /dev/null @@ -1,243 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree for the ARM Integrator/AP platform - */ - -/dts-v1/; -/include/ "integrator.dtsi" - -/ { - model = "ARM Integrator/AP"; - compatible = "arm,integrator-ap"; - dma-ranges = <0x80000000 0x0 0x80000000>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - /* - * Since the board has pluggable CPU modules, we - * cannot define a proper compatible here. Let the - * boot loader fill in the apropriate compatible - * string if necessary. - */ - /* compatible = "arm,arm926ej-s"; */ - reg = <0>; - /* - * The documentation in ARM DUI 0138E page 3-12 states - * that the maximum frequency for this clock is 200 MHz - * but painful trial-and-error has proved to me that it - * is actually just hanging the system above 71 MHz. - * Sad but true. - */ - /* kHz uV */ - operating-points = <71000 0 - 66000 0 - 60000 0 - 48000 0 - 36000 0 - 24000 0 - 12000 0>; - clocks = <&cmosc>; - clock-names = "cpu"; - clock-latency = <1000000>; /* 1 ms */ - }; - }; - - aliases { - arm,timer-primary = &timer2; - arm,timer-secondary = &timer1; - }; - - chosen { - bootargs = "root=/dev/ram0 console=ttyAM0,38400n8 earlyprintk"; - }; - - /* 24 MHz chrystal on the Integrator/AP development board */ - xtal24mhz: xtal24mhz@24M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - }; - - pclk: pclk@0 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - /* The UART clock is 14.74 MHz divided by an ICS525 */ - uartclk: uartclk@14.74M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <14745600>; - clocks = <&xtal24mhz>; - }; - - core-module@10000000 { - /* 24 MHz chrystal on the core module */ - cm24mhz: cm24mhz@24M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - }; - - /* Oscillator on the core module, clocks the CPU core */ - cmosc: cmosc@24M { - compatible = "arm,syscon-icst525-integratorap-cm"; - #clock-cells = <0>; - lock-offset = <0x14>; - vco-offset = <0x08>; - clocks = <&cm24mhz>; - }; - - /* Auxilary oscillator on the core module, 32.369MHz at boot */ - auxosc: auxosc@24M { - compatible = "arm,syscon-icst525"; - #clock-cells = <0>; - lock-offset = <0x14>; - vco-offset = <0x1c>; - clocks = <&cm24mhz>; - }; - }; - - syscon { - compatible = "arm,integrator-ap-syscon", "syscon"; - reg = <0x11000000 0x100>; - interrupt-parent = <&pic>; - /* These are the logical module IRQs */ - interrupts = <9>, <10>, <11>, <12>; - - /* - * SYSCLK clocks PCIv3 bridge, system controller and the - * logic modules. - */ - sysclk: apsys@24M { - compatible = "arm,syscon-icst525-integratorap-sys"; - #clock-cells = <0>; - lock-offset = <0x1c>; - vco-offset = <0x04>; - clocks = <&xtal24mhz>; - }; - - /* One-bit control for the PCI bus clock (33 or 25 MHz) */ - pciclk: pciclk@24M { - compatible = "arm,syscon-icst525-integratorap-pci"; - #clock-cells = <0>; - lock-offset = <0x1c>; - vco-offset = <0x04>; - clocks = <&xtal24mhz>; - }; - }; - - timer0: timer@13000000 { - compatible = "arm,integrator-timer"; - clocks = <&xtal24mhz>; - }; - - timer1: timer@13000100 { - compatible = "arm,integrator-timer"; - clocks = <&xtal24mhz>; - }; - - timer2: timer@13000200 { - compatible = "arm,integrator-timer"; - clocks = <&xtal24mhz>; - }; - - pic: pic@14000000 { - valid-mask = <0x003fffff>; - }; - - pci: pciv3@62000000 { - compatible = "arm,integrator-ap-pci", "v3,v360epc-pci"; - #interrupt-cells = <1>; - #size-cells = <2>; - #address-cells = <3>; - /* Bridge registers and config access space */ - reg = <0x62000000 0x10000>, <0x61000000 0x01000000>; - interrupt-parent = <&pic>; - interrupts = <17>; /* Bus error IRQ */ - clocks = <&pciclk>; - bus-range = <0x00 0xff>; - ranges = <0x01000000 0 0x0000000 /* I/O space @00000000 */ - 0x60000000 0 0x00010000 /* 64 KB @ LB 60000000 */ - 0x02000000 0 0x40000000 /* non-prefectable memory @40000000 */ - 0x40000000 0 0x10000000 /* 256 MiB @ LB 40000000 1:1 */ - 0x42000000 0 0x50000000 /* prefetchable memory @50000000 */ - 0x50000000 0 0x10000000>; /* 256 MiB @ LB 50000000 1:1 */ - dma-ranges = <0x02000000 0 0x20000000 /* EBI memory space */ - 0x20000000 0 0x20000000 /* 512 MB @ LB 20000000 1:1 */ - 0x02000000 0 0x80000000 /* Core module alias memory */ - 0x80000000 0 0x40000000>; /* 1GB @ LB 80000000 */ - interrupt-map-mask = <0xf800 0 0 0x7>; - interrupt-map = < - /* IDSEL 9 */ - 0x4800 0 0 1 &pic 13 /* INT A on slot 9 is irq 13 */ - 0x4800 0 0 2 &pic 14 /* INT B on slot 9 is irq 14 */ - 0x4800 0 0 3 &pic 15 /* INT C on slot 9 is irq 15 */ - 0x4800 0 0 4 &pic 16 /* INT D on slot 9 is irq 16 */ - /* IDSEL 10 */ - 0x5000 0 0 1 &pic 14 /* INT A on slot 10 is irq 14 */ - 0x5000 0 0 2 &pic 15 /* INT B on slot 10 is irq 15 */ - 0x5000 0 0 3 &pic 16 /* INT C on slot 10 is irq 16 */ - 0x5000 0 0 4 &pic 13 /* INT D on slot 10 is irq 13 */ - /* IDSEL 11 */ - 0x5800 0 0 1 &pic 15 /* INT A on slot 11 is irq 15 */ - 0x5800 0 0 2 &pic 16 /* INT B on slot 11 is irq 16 */ - 0x5800 0 0 3 &pic 13 /* INT C on slot 11 is irq 13 */ - 0x5800 0 0 4 &pic 14 /* INT D on slot 11 is irq 14 */ - /* IDSEL 12 */ - 0x6000 0 0 1 &pic 16 /* INT A on slot 12 is irq 16 */ - 0x6000 0 0 2 &pic 13 /* INT B on slot 12 is irq 13 */ - 0x6000 0 0 3 &pic 14 /* INT C on slot 12 is irq 14 */ - 0x6000 0 0 4 &pic 15 /* INT D on slot 12 is irq 15 */ - >; - }; - - fpga { - /* - * The Integator/AP predates the idea to have magic numbers - * identifying the PrimeCell in hardware, thus we have to - * supply these from the device tree. - */ - rtc: rtc@15000000 { - compatible = "arm,pl030", "arm,primecell"; - arm,primecell-periphid = <0x00041030>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - uart0: uart@16000000 { - compatible = "arm,pl010", "arm,primecell"; - arm,primecell-periphid = <0x00041010>; - clocks = <&uartclk>, <&pclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - uart1: uart@17000000 { - compatible = "arm,pl010", "arm,primecell"; - arm,primecell-periphid = <0x00041010>; - clocks = <&uartclk>, <&pclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - kmi0: kmi@18000000 { - compatible = "arm,pl050", "arm,primecell"; - arm,primecell-periphid = <0x00041050>; - clocks = <&xtal24mhz>, <&pclk>; - clock-names = "KMIREFCLK", "apb_pclk"; - }; - - kmi1: kmi@19000000 { - compatible = "arm,pl050", "arm,primecell"; - arm,primecell-periphid = <0x00041050>; - clocks = <&xtal24mhz>, <&pclk>; - clock-names = "KMIREFCLK", "apb_pclk"; - }; - }; -}; diff --git a/sys/gnu/dts/arm/integratorcp.dts b/sys/gnu/dts/arm/integratorcp.dts deleted file mode 100644 index 01fa229e1bd..00000000000 --- a/sys/gnu/dts/arm/integratorcp.dts +++ /dev/null @@ -1,319 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree for the ARM Integrator/CP platform - */ - -/dts-v1/; -/include/ "integrator.dtsi" - -/ { - model = "ARM Integrator/CP"; - compatible = "arm,integrator-cp"; - - chosen { - bootargs = "root=/dev/ram0 console=ttyAMA0,38400n8 earlyprintk"; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - /* - * Since the board has pluggable CPU modules, we - * cannot define a proper compatible here. Let the - * boot loader fill in the apropriate compatible - * string if necessary. - */ - /* compatible = "arm,arm920t"; */ - reg = <0>; - /* - * TBD comment. - */ - /* kHz uV */ - operating-points = <50000 0 - 48000 0>; - clocks = <&cmcore>; - clock-names = "cpu"; - clock-latency = <1000000>; /* 1 ms */ - }; - }; - - /* - * The Integrator/CP overall clocking architecture can be found in - * ARM DUI 0184B page 7-28 "Integrator/CP922T system clocks" which - * appear to illustrate the layout used in most configurations. - */ - - /* The codec chrystal operates at 24.576 MHz */ - xtal_codec: xtal24.576@24.576M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24576000>; - }; - - /* The chrystal is divided by 2 by the codec for the AACI bit clock */ - aaci_bitclk: aaci_bitclk@12.288M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <2>; - clock-mult = <1>; - clocks = <&xtal_codec>; - }; - - /* This is a 25MHz chrystal on the base board */ - xtal25mhz: xtal25mhz@25M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <25000000>; - }; - - /* The UART clock is 14.74 MHz divided from 25MHz by an ICS525 */ - uartclk: uartclk@14.74M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <14745600>; - }; - - /* Actually sysclk I think */ - pclk: pclk@0 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - core-module@10000000 { - /* 24 MHz chrystal on the core module */ - cm24mhz: cm24mhz@24M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - }; - - /* Oscillator on the core module, clocks the CPU core */ - cmcore: cmosc@24M { - compatible = "arm,syscon-icst525-integratorcp-cm-core"; - #clock-cells = <0>; - lock-offset = <0x14>; - vco-offset = <0x08>; - clocks = <&cm24mhz>; - }; - - /* Oscillator on the core module, clocks the memory bus */ - cmmem: cmosc@24M { - compatible = "arm,syscon-icst525-integratorcp-cm-mem"; - #clock-cells = <0>; - lock-offset = <0x14>; - vco-offset = <0x08>; - clocks = <&cm24mhz>; - }; - - /* Auxilary oscillator on the core module, clocks the CLCD */ - auxosc: auxosc@24M { - compatible = "arm,syscon-icst525"; - #clock-cells = <0>; - lock-offset = <0x14>; - vco-offset = <0x1c>; - clocks = <&cm24mhz>; - }; - - /* The KMI clock is the 24 MHz oscillator divided to 8MHz */ - kmiclk: kmiclk@1M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <3>; - clock-mult = <1>; - clocks = <&cm24mhz>; - }; - - /* The timer clock is the 24 MHz oscillator divided to 1MHz */ - timclk: timclk@1M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <24>; - clock-mult = <1>; - clocks = <&cm24mhz>; - }; - }; - - syscon { - compatible = "arm,integrator-cp-syscon", "syscon"; - reg = <0xcb000000 0x100>; - }; - - timer0: timer@13000000 { - /* TIMER0 runs directly on the 25MHz chrystal */ - compatible = "arm,integrator-cp-timer"; - clocks = <&xtal25mhz>; - }; - - timer1: timer@13000100 { - /* TIMER1 runs @ 1MHz */ - compatible = "arm,integrator-cp-timer"; - clocks = <&timclk>; - }; - - timer2: timer@13000200 { - /* TIMER2 runs @ 1MHz */ - compatible = "arm,integrator-cp-timer"; - clocks = <&timclk>; - }; - - pic: pic@14000000 { - valid-mask = <0x1fc003ff>; - }; - - cic: cic@10000040 { - compatible = "arm,versatile-fpga-irq"; - #interrupt-cells = <1>; - interrupt-controller; - reg = <0x10000040 0x100>; - clear-mask = <0xffffffff>; - valid-mask = <0x00000007>; - }; - - /* The SIC is cascaded off IRQ 26 on the PIC */ - sic: sic@ca000000 { - compatible = "arm,versatile-fpga-irq"; - interrupt-parent = <&pic>; - interrupts = <26>; - #interrupt-cells = <1>; - interrupt-controller; - reg = <0xca000000 0x100>; - clear-mask = <0x00000fff>; - valid-mask = <0x00000fff>; - }; - - ethernet@c8000000 { - compatible = "smsc,lan91c111"; - reg = <0xc8000000 0x10>; - interrupt-parent = <&pic>; - interrupts = <27>; - }; - - bridge { - compatible = "ti,ths8134a", "ti,ths8134"; - #address-cells = <1>; - #size-cells = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - vga_bridge_in: endpoint { - remote-endpoint = <&clcd_pads_vga_dac>; - }; - }; - - port@1 { - reg = <1>; - - vga_bridge_out: endpoint { - remote-endpoint = <&vga_con_in>; - }; - }; - }; - }; - - vga { - compatible = "vga-connector"; - - port { - vga_con_in: endpoint { - remote-endpoint = <&vga_bridge_out>; - }; - }; - }; - - fpga { - /* - * These PrimeCells are at the same location and using - * the same interrupts in all Integrators, but in the CP - * slightly newer versions are deployed. - */ - rtc@15000000 { - compatible = "arm,pl031", "arm,primecell"; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - uart@16000000 { - compatible = "arm,pl011", "arm,primecell"; - clocks = <&uartclk>, <&pclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - uart@17000000 { - compatible = "arm,pl011", "arm,primecell"; - clocks = <&uartclk>, <&pclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - kmi@18000000 { - compatible = "arm,pl050", "arm,primecell"; - clocks = <&kmiclk>, <&pclk>; - clock-names = "KMIREFCLK", "apb_pclk"; - }; - - kmi@19000000 { - compatible = "arm,pl050", "arm,primecell"; - clocks = <&kmiclk>, <&pclk>; - clock-names = "KMIREFCLK", "apb_pclk"; - }; - - /* - * These PrimeCells are only available on the Integrator/CP - */ - mmc@1c000000 { - compatible = "arm,pl180", "arm,primecell"; - reg = <0x1c000000 0x1000>; - interrupts = <23 24>; - max-frequency = <515633>; - clocks = <&uartclk>, <&pclk>; - clock-names = "mclk", "apb_pclk"; - }; - - aaci@1d000000 { - compatible = "arm,pl041", "arm,primecell"; - reg = <0x1d000000 0x1000>; - interrupts = <25>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - clcd@c0000000 { - compatible = "arm,pl110", "arm,primecell"; - reg = <0xC0000000 0x1000>; - interrupts = <22>; - clocks = <&auxosc>, <&pclk>; - clock-names = "clcdclk", "apb_pclk"; - /* 640x480 16bpp @ 25.175MHz is 36827428 bytes/s */ - max-memory-bandwidth = <40000000>; - - /* - * This port is routed through a PLD (Programmable - * Logic Device) that routes the output from the CLCD - * (after transformations) to the VGA DAC and also an - * external panel connector. The PLD is essential for - * supporting RGB565/BGR565. - * - * The signals from the port thus reaches two endpoints. - * The PLD is managed through a few special bits in the - * FPGA "sysreg". - * - * This arrangement can be clearly seen in - * ARM DUI 0225D, page 3-41, figure 3-19. - */ - port@0 { - clcd_pads_vga_dac: endpoint { - remote-endpoint = <&vga_bridge_in>; - arm,pl11x,tft-r0g0b0-pads = <0 8 16>; - }; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/intel-ixp42x-linksys-nslu2.dts b/sys/gnu/dts/arm/intel-ixp42x-linksys-nslu2.dts deleted file mode 100644 index 8fcd95805ff..00000000000 --- a/sys/gnu/dts/arm/intel-ixp42x-linksys-nslu2.dts +++ /dev/null @@ -1,109 +0,0 @@ -// SPDX-License-Identifier: ISC -/* - * Device Tree file for Linksys NSLU2 - */ - -/dts-v1/; - -#include "intel-ixp42x.dtsi" -#include - -/ { - model = "Linksys NSLU2 (Network Storage Link for USB 2.0 Disk Drives)"; - compatible = "linksys,nslu2", "intel,ixp42x"; - #address-cells = <1>; - #size-cells = <1>; - - memory@0 { - /* 32 MB SDRAM */ - device_type = "memory"; - reg = <0x00000000 0x2000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8 root=/dev/mtdblock2 rw rootfstype=squashfs,jffs2 rootwait"; - stdout-path = "uart0:115200n8"; - }; - - aliases { - serial0 = &uart0; - }; - - leds { - compatible = "gpio-leds"; - led-status { - label = "nslu2:red:status"; - gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>; - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - led-ready { - label = "nslu2:green:ready"; - gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - led-disk-1 { - label = "nslu2:green:disk-1"; - gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - led-disk-2 { - label = "nslu2:green:disk-2"; - gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - - button-power { - wakeup-source; - linux,code = ; - label = "power"; - gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>; - }; - button-reset { - wakeup-source; - linux,code = ; - label = "reset"; - gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; - }; - }; - - i2c { - compatible = "i2c-gpio"; - sda-gpios = <&gpio0 7 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpio0 6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - #address-cells = <1>; - #size-cells = <0>; - - rtc@6f { - compatible = "xicor,x1205"; - reg = <0x6f>; - }; - }; - - gpio-poweroff { - compatible = "gpio-poweroff"; - gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>; - timeout-ms = <5000>; - }; - - /* The first 16MB region on the expansion bus */ - flash@50000000 { - compatible = "intel,ixp4xx-flash", "cfi-flash"; - bank-width = <2>; - /* - * 8 MB of Flash in 0x20000 byte blocks - * mapped in at 0x50000000 - */ - reg = <0x50000000 0x800000>; - - partitions { - compatible = "redboot-fis"; - /* Eraseblock at 0x7e0000 */ - fis-index-block = <0x3f>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/intel-ixp42x.dtsi b/sys/gnu/dts/arm/intel-ixp42x.dtsi deleted file mode 100644 index a9622ca850c..00000000000 --- a/sys/gnu/dts/arm/intel-ixp42x.dtsi +++ /dev/null @@ -1,25 +0,0 @@ -// SPDX-License-Identifier: ISC -/* - * Device Tree file for Intel XScale Network Processors - * in the IXP 42x series. This series has 32 interrupts. - */ -#include "intel-ixp4xx.dtsi" - -/ { - soc { - interrupt-controller@c8003000 { - compatible = "intel,ixp42x-interrupt"; - }; - - /* - * This is the USB Device Mode (UDC) controller, which is used - * to present the IXP4xx as a device on a USB bus. - */ - usb@c800b000 { - compatible = "intel,ixp4xx-udc"; - reg = <0xc800b000 0x1000>; - interrupts = <12 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - }; -}; diff --git a/sys/gnu/dts/arm/intel-ixp43x-gateworks-gw2358.dts b/sys/gnu/dts/arm/intel-ixp43x-gateworks-gw2358.dts deleted file mode 100644 index ba1163a1e1e..00000000000 --- a/sys/gnu/dts/arm/intel-ixp43x-gateworks-gw2358.dts +++ /dev/null @@ -1,94 +0,0 @@ -// SPDX-License-Identifier: ISC -/* - * Device Tree file for Gateworks IXP43x-based Cambria GW2358 - */ - -/dts-v1/; - -#include "intel-ixp43x.dtsi" - -/ { - model = "Gateworks Cambria GW2358"; - compatible = "gateworks,gw2358", "intel,ixp43x"; - #address-cells = <1>; - #size-cells = <1>; - - memory@0 { - /* 128 MB SDRAM */ - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8 root=/dev/mtdblock2 rw rootfstype=squashfs,jffs2 rootwait"; - stdout-path = "uart0:115200n8"; - }; - - aliases { - serial0 = &uart0; - }; - - leds { - compatible = "gpio-leds"; - led-user { - label = "gw2358:green:LED"; - gpios = <&pld1 0 GPIO_ACTIVE_LOW>; - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - }; - - - i2c { - compatible = "i2c-gpio"; - sda-gpios = <&gpio0 7 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpio0 6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - #address-cells = <1>; - #size-cells = <0>; - - hwmon@28 { - compatible = "adi,ad7418"; - reg = <0x28>; - }; - rtc: ds1672@68 { - compatible = "dallas,ds1672"; - reg = <0x68>; - }; - eeprom@51 { - compatible = "atmel,24c08"; - reg = <0x51>; - pagesize = <16>; - size = <1024>; - read-only; - }; - pld0: pld@56 { - compatible = "gateworks,pld-gpio"; - reg = <0x56>; - gpio-controller; - #gpio-cells = <2>; - }; - /* This PLD just handles the LED and user button */ - pld1: pld@57 { - compatible = "gateworks,pld-gpio"; - reg = <0x57>; - gpio-controller; - #gpio-cells = <2>; - }; - }; - - flash@50000000 { - compatible = "intel,ixp4xx-flash", "cfi-flash"; - bank-width = <2>; - /* - * 32 MB of Flash in 0x20000 byte blocks - * mapped in at 0x50000000 - */ - reg = <0x50000000 0x2000000>; - - partitions { - compatible = "redboot-fis"; - /* Eraseblock at 0x1fe0000 */ - fis-index-block = <0xff>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/intel-ixp43x.dtsi b/sys/gnu/dts/arm/intel-ixp43x.dtsi deleted file mode 100644 index 494fb2ff57a..00000000000 --- a/sys/gnu/dts/arm/intel-ixp43x.dtsi +++ /dev/null @@ -1,15 +0,0 @@ -// SPDX-License-Identifier: ISC -/* - * Device Tree file for Intel XScale Network Processors - * in the IXP 43x series. This series has 64 interrupts and adds a few more - * peripherals over the 42x series. - */ -#include "intel-ixp4xx.dtsi" - -/ { - soc { - interrupt-controller@c8003000 { - compatible = "intel,ixp43x-interrupt"; - }; - }; -}; diff --git a/sys/gnu/dts/arm/intel-ixp45x-ixp46x.dtsi b/sys/gnu/dts/arm/intel-ixp45x-ixp46x.dtsi deleted file mode 100644 index f8cd506659d..00000000000 --- a/sys/gnu/dts/arm/intel-ixp45x-ixp46x.dtsi +++ /dev/null @@ -1,34 +0,0 @@ -// SPDX-License-Identifier: ISC -/* - * Device Tree file for Intel XScale Network Processors - * in the IXP45x and IXP46x series. This series has 64 interrupts and adds a - * few more peripherals over the 42x and 43x series so this extends the - * basic IXP4xx DTSI. - */ -#include "intel-ixp4xx.dtsi" - -/ { - soc { - interrupt-controller@c8003000 { - compatible = "intel,ixp43x-interrupt"; - }; - - /* - * This is the USB Device Mode (UDC) controller, which is used - * to present the IXP4xx as a device on a USB bus. - */ - usb@c800b000 { - compatible = "intel,ixp4xx-udc"; - reg = <0xc800b000 0x1000>; - interrupts = <12 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - i2c@c8011000 { - compatible = "intel,ixp4xx-i2c"; - reg = <0xc8011000 0x18>; - interrupts = <33 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - }; -}; diff --git a/sys/gnu/dts/arm/intel-ixp4xx.dtsi b/sys/gnu/dts/arm/intel-ixp4xx.dtsi deleted file mode 100644 index d4a09584f41..00000000000 --- a/sys/gnu/dts/arm/intel-ixp4xx.dtsi +++ /dev/null @@ -1,69 +0,0 @@ -// SPDX-License-Identifier: ISC -/* - * Device Tree file for Intel XScale Network Processors - * in the IXP 4xx series. - */ -#include -#include - -/ { - soc { - #address-cells = <1>; - #size-cells = <1>; - ranges; - compatible = "simple-bus"; - interrupt-parent = <&intcon>; - - qmgr: queue-manager@60000000 { - compatible = "intel,ixp4xx-ahb-queue-manager"; - reg = <0x60000000 0x4000>; - interrupts = <3 IRQ_TYPE_LEVEL_HIGH>, <4 IRQ_TYPE_LEVEL_HIGH>; - }; - - uart0: serial@c8000000 { - compatible = "intel,xscale-uart"; - reg = <0xc8000000 0x1000>; - /* - * The reg-offset and reg-shift is a side effect - * of running the platform in big endian mode. - */ - reg-offset = <3>; - reg-shift = <2>; - interrupts = <15 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <14745600>; - no-loopback-test; - }; - - gpio0: gpio@c8004000 { - compatible = "intel,ixp4xx-gpio"; - reg = <0xc8004000 0x1000>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - intcon: interrupt-controller@c8003000 { - /* - * Note: no compatible string. The subvariant of the - * chip needs to define what version it is. The - * location of the interrupt controller is fixed in - * memory across all variants. - */ - reg = <0xc8003000 0x100>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - timer@c8005000 { - compatible = "intel,ixp4xx-timer"; - reg = <0xc8005000 0x100>; - interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; - }; - - npe@c8006000 { - compatible = "intel,ixp4xx-network-processing-engine"; - reg = <0xc8006000 0x1000>, <0xc8007000 0x1000>, <0xc8008000 0x1000>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/iwg20d-q7-common.dtsi b/sys/gnu/dts/arm/iwg20d-q7-common.dtsi deleted file mode 100644 index ebbe1518ef8..00000000000 --- a/sys/gnu/dts/arm/iwg20d-q7-common.dtsi +++ /dev/null @@ -1,360 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the iWave-RZ/G1M/G1N Qseven carrier board - * - * Copyright (C) 2017 Renesas Electronics Corp. - */ - -/* - * SSI-SGTL5000 - * - * This command is required when Playback/Capture - * - * amixer set "DVC Out" 100% - * amixer set "DVC In" 100% - * - * You can use Mute - * - * amixer set "DVC Out Mute" on - * amixer set "DVC In Mute" on - * - * You can use Volume Ramp - * - * amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps" - * amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps" - * amixer set "DVC Out Ramp" on - * aplay xxx.wav & - * amixer set "DVC Out" 80% // Volume Down - * amixer set "DVC Out" 100% // Volume Up - */ - -/ { - aliases { - serial0 = &scif0; - serial3 = &scifb1; - ethernet0 = &avb; - }; - - chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; - stdout-path = "serial0:115200n8"; - }; - - audio_clock: audio_clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <26000000>; - }; - - lcd_backlight: backlight { - compatible = "pwm-backlight"; - - pwms = <&pwm3 0 5000000 0>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <7>; - enable-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>; - }; - - lvds-receiver { - compatible = "ti,ds90cf384a", "lvds-decoder"; - powerdown-gpios = <&gpio7 25 GPIO_ACTIVE_LOW>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - lvds_receiver_in: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - port@1 { - reg = <1>; - lvds_receiver_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; - }; - - panel { - compatible = "edt,etm0700g0dh6"; - backlight = <&lcd_backlight>; - - port { - panel_in: endpoint { - remote-endpoint = <&lvds_receiver_out>; - }; - }; - }; - - reg_1p5v: 1p5v { - compatible = "regulator-fixed"; - regulator-name = "1P5V"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - }; - - rsnd_sgtl5000: sound { - compatible = "simple-audio-card"; - - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&sndcodec>; - simple-audio-card,frame-master = <&sndcodec>; - - sndcpu: simple-audio-card,cpu { - sound-dai = <&rcar_sound>; - }; - - sndcodec: simple-audio-card,codec { - sound-dai = <&sgtl5000>; - }; - }; - - vcc_sdhi1: regulator-vcc-sdhi1 { - compatible = "regulator-fixed"; - - regulator-name = "SDHI1 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&gpio1 16 GPIO_ACTIVE_LOW>; - }; - - vccq_sdhi1: regulator-vccq-sdhi1 { - compatible = "regulator-gpio"; - - regulator-name = "SDHI1 VccQ"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>; - gpios-states = <1>; - states = <3300000 1>, <1800000 0>; - }; -}; - -&avb { - pinctrl-0 = <&avb_pins>; - pinctrl-names = "default"; - - phy-handle = <&phy3>; - phy-mode = "gmii"; - renesas,no-ether-link; - status = "okay"; - - phy3: ethernet-phy@3 { - reg = <3>; - micrel,led-mode = <1>; - }; -}; - -&can0 { - pinctrl-0 = <&can0_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&cmt0 { - status = "okay"; -}; - -&du { - status = "okay"; -}; - -&gpio2 { - touch-interrupt { - gpio-hog; - gpios = <12 GPIO_ACTIVE_LOW>; - input; - }; -}; - -&hsusb { - status = "okay"; - pinctrl-0 = <&usb0_pins>; - pinctrl-names = "default"; -}; - -&i2c2 { - pinctrl-0 = <&i2c2_pins>; - pinctrl-names = "default"; - - status = "okay"; - clock-frequency = <400000>; - - rtc@68 { - compatible = "ti,bq32000"; - reg = <0x68>; - }; - - sgtl5000: codec@a { - compatible = "fsl,sgtl5000"; - #sound-dai-cells = <0>; - reg = <0x0a>; - clocks = <&audio_clock>; - VDDA-supply = <®_3p3v>; - VDDIO-supply = <®_3p3v>; - VDDD-supply = <®_1p5v>; - }; - - touch: touchpanel@38 { - compatible = "edt,edt-ft5406"; - reg = <0x38>; - interrupt-parent = <&gpio2>; - interrupts = <12 IRQ_TYPE_EDGE_FALLING>; - }; -}; - -&lvds0 { - status = "okay"; - - ports { - port@1 { - lvds0_out: endpoint { - remote-endpoint = <&lvds_receiver_in>; - }; - }; - }; -}; - -&pci0 { - pinctrl-0 = <&usb0_pins>; - pinctrl-names = "default"; -}; - -&pci1 { - status = "okay"; - pinctrl-0 = <&usb1_pins>; - pinctrl-names = "default"; -}; - -&pcie_bus_clk { - clock-frequency = <100000000>; -}; - -&pfc { - can0_pins: can0 { - groups = "can0_data_d"; - function = "can0"; - }; - - avb_pins: avb { - groups = "avb_mdio", "avb_gmii"; - function = "avb"; - }; - - i2c2_pins: i2c2 { - groups = "i2c2"; - function = "i2c2"; - }; - - pwm3_pins: pwm3 { - groups = "pwm3"; - function = "pwm3"; - }; - - scif0_pins: scif0 { - groups = "scif0_data_d"; - function = "scif0"; - }; - - scifb1_pins: scifb1 { - groups = "scifb1_data_d", "scifb1_ctrl"; - function = "scifb1"; - }; - - sdhi1_pins: sd1 { - groups = "sdhi1_data4", "sdhi1_ctrl"; - function = "sdhi1"; - power-source = <3300>; - }; - - sdhi1_pins_uhs: sd1_uhs { - groups = "sdhi1_data4", "sdhi1_ctrl"; - function = "sdhi1"; - power-source = <1800>; - }; - - sound_pins: sound { - groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data"; - function = "ssi"; - }; - - usb0_pins: usb0 { - groups = "usb0"; - function = "usb0"; - }; - - usb1_pins: usb1 { - groups = "usb1"; - function = "usb1"; - }; -}; - -&pwm3 { - pinctrl-0 = <&pwm3_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&rcar_sound { - pinctrl-0 = <&sound_pins>; - pinctrl-names = "default"; - status = "okay"; - - /* Single DAI */ - #sound-dai-cells = <0>; - - rcar_sound,dai { - dai0 { - playback = <&ssi1 &src3 &dvc1>; - capture = <&ssi0 &src2 &dvc0>; - }; - }; -}; - -&rwdt { - timeout-sec = <60>; - status = "okay"; -}; - -&scif0 { - pinctrl-0 = <&scif0_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&scifb1 { - pinctrl-0 = <&scifb1_pins>; - pinctrl-names = "default"; - - uart-has-rtscts; - status = "okay"; -}; - -&sdhi1 { - pinctrl-0 = <&sdhi1_pins>; - pinctrl-1 = <&sdhi1_pins_uhs>; - pinctrl-names = "default", "state_uhs"; - - vmmc-supply = <&vcc_sdhi1>; - vqmmc-supply = <&vccq_sdhi1>; - cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>; - sd-uhs-sdr50; - status = "okay"; -}; - -&ssi1 { - shared-pin; -}; - -&usbphy { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/iwg20d-q7-dbcm-ca.dtsi b/sys/gnu/dts/arm/iwg20d-q7-dbcm-ca.dtsi deleted file mode 100644 index ede2e0c999b..00000000000 --- a/sys/gnu/dts/arm/iwg20d-q7-dbcm-ca.dtsi +++ /dev/null @@ -1,126 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the iWave-RZ-G1M/N Daughter Board Camera Module - * - * Copyright (C) 2017 Renesas Electronics Corp. - */ - -/ { - aliases { - serial1 = &scif1; - serial4 = &hscif1; - }; - - cec_clock: cec-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <12000000>; - }; - - hdmi-out { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_out: endpoint { - remote-endpoint = <&adv7511_out>; - }; - }; - }; -}; - -&can1 { - pinctrl-0 = <&can1_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&du { - pinctrl-0 = <&du_pins>; - pinctrl-names = "default"; - - ports { - port@0 { - endpoint { - remote-endpoint = <&adv7511_in>; - }; - }; - }; -}; - -&hscif1 { - pinctrl-0 = <&hscif1_pins>; - pinctrl-names = "default"; - - uart-has-rtscts; - status = "okay"; -}; - -&i2c5 { - status = "okay"; - clock-frequency = <400000>; - - hdmi@39 { - compatible = "adi,adv7511w"; - reg = <0x39>; - interrupt-parent = <&gpio0>; - interrupts = <13 IRQ_TYPE_LEVEL_LOW>; - clocks = <&cec_clock>; - clock-names = "cec"; - - adi,input-depth = <8>; - adi,input-colorspace = "rgb"; - adi,input-clock = "1x"; - adi,input-style = <1>; - adi,input-justification = "evenly"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7511_in: endpoint { - remote-endpoint = <&du_out_rgb>; - }; - }; - - port@1 { - reg = <1>; - adv7511_out: endpoint { - remote-endpoint = <&hdmi_con_out>; - }; - }; - }; - }; -}; - -&pfc { - can1_pins: can1 { - groups = "can1_data_d"; - function = "can1"; - }; - - du_pins: du { - groups = "du_rgb888", "du_sync", "du_oddf", "du_clk_out_0"; - function = "du"; - }; - - hscif1_pins: hscif1 { - groups = "hscif1_data_c", "hscif1_ctrl_c"; - function = "hscif1"; - }; - - scif1_pins: scif1 { - groups = "scif1_data_d"; - function = "scif1"; - }; -}; - -&scif1 { - pinctrl-0 = <&scif1_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/k2e-clocks.dtsi b/sys/gnu/dts/arm/k2e-clocks.dtsi deleted file mode 100644 index d56d68fe7ff..00000000000 --- a/sys/gnu/dts/arm/k2e-clocks.dtsi +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Copyright 2014 Texas Instruments, Inc. - * - * Keystone 2 Edison SoC specific device tree - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -clocks { - mainpllclk: mainpllclk@2310110 { - #clock-cells = <0>; - compatible = "ti,keystone,main-pll-clock"; - clocks = <&refclksys>; - reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>; - reg-names = "control", "multiplier", "post-divider"; - }; - - papllclk: papllclk@2620358 { - #clock-cells = <0>; - compatible = "ti,keystone,pll-clock"; - clocks = <&refclkpass>; - clock-output-names = "papllclk"; - reg = <0x02620358 4>; - reg-names = "control"; - }; - - ddr3apllclk: ddr3apllclk@2620360 { - #clock-cells = <0>; - compatible = "ti,keystone,pll-clock"; - clocks = <&refclkddr3a>; - clock-output-names = "ddr-3a-pll-clk"; - reg = <0x02620360 4>; - reg-names = "control"; - }; - - clkusb1: clkusb1 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk16>; - clock-output-names = "usb1"; - reg = <0x02350004 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; - - clkhyperlink0: clkhyperlink0 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk12>; - clock-output-names = "hyperlink-0"; - reg = <0x02350030 0xb00>, <0x02350014 0x400>; - reg-names = "control", "domain"; - domain-id = <5>; - }; - - clkpcie1: clkpcie1 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk12>; - clock-output-names = "pcie1"; - reg = <0x0235006c 0xb00>, <0x02350048 0x400>; - reg-names = "control", "domain"; - domain-id = <18>; - }; - - clkxge: clkxge { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "xge"; - reg = <0x023500c8 0xb00>, <0x02350074 0x400>; - reg-names = "control", "domain"; - domain-id = <29>; - }; -}; diff --git a/sys/gnu/dts/arm/k2e-evm.dts b/sys/gnu/dts/arm/k2e-evm.dts deleted file mode 100644 index b7e99807f5c..00000000000 --- a/sys/gnu/dts/arm/k2e-evm.dts +++ /dev/null @@ -1,154 +0,0 @@ -/* - * Copyright 2013-2014 Texas Instruments, Inc. - * - * Keystone 2 Edison EVM device tree - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -/dts-v1/; - -#include "keystone.dtsi" -#include "k2e.dtsi" - -/ { - compatible = "ti,k2e-evm", "ti,k2e", "ti,keystone"; - model = "Texas Instruments Keystone 2 Edison EVM"; - - soc { - - clocks { - refclksys: refclksys { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <100000000>; - clock-output-names = "refclk-sys"; - }; - - refclkpass: refclkpass { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <100000000>; - clock-output-names = "refclk-pass"; - }; - - refclkddr3a: refclkddr3a { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <100000000>; - clock-output-names = "refclk-ddr3a"; - }; - }; - }; -}; - -&usb_phy { - status = "okay"; -}; - -&usb { - status = "okay"; -}; - -&usb1_phy { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; - -&i2c0 { - dtt@50 { - compatible = "at,24c1024"; - reg = <0x50>; - }; -}; - -&aemif { - cs0 { - #address-cells = <2>; - #size-cells = <1>; - clock-ranges; - ranges; - - ti,cs-chipselect = <0>; - /* all timings in nanoseconds */ - ti,cs-min-turnaround-ns = <12>; - ti,cs-read-hold-ns = <6>; - ti,cs-read-strobe-ns = <23>; - ti,cs-read-setup-ns = <9>; - ti,cs-write-hold-ns = <8>; - ti,cs-write-strobe-ns = <23>; - ti,cs-write-setup-ns = <8>; - - nand@0,0 { - compatible = "ti,keystone-nand","ti,davinci-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0 0 0x4000000 - 1 0 0x0000100>; - - ti,davinci-chipselect = <0>; - ti,davinci-mask-ale = <0x2000>; - ti,davinci-mask-cle = <0x4000>; - ti,davinci-mask-chipsel = <0>; - nand-ecc-mode = "hw"; - ti,davinci-ecc-bits = <4>; - nand-on-flash-bbt; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x100000>; - read-only; - }; - - partition@100000 { - label = "params"; - reg = <0x100000 0x80000>; - read-only; - }; - - partition@180000 { - label = "ubifs"; - reg = <0x180000 0x1FE80000>; - }; - }; - }; -}; - -&spi0 { - nor_flash: n25q128a11@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "Micron,n25q128a11"; - spi-max-frequency = <54000000>; - m25p,fast-read; - reg = <0>; - - partition@0 { - label = "u-boot-spl"; - reg = <0x0 0x80000>; - read-only; - }; - - partition@1 { - label = "misc"; - reg = <0x80000 0xf80000>; - }; - }; -}; - -&mdio { - status = "ok"; - ethphy0: ethernet-phy@0 { - compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22"; - reg = <0>; - }; - - ethphy1: ethernet-phy@1 { - compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; -}; diff --git a/sys/gnu/dts/arm/k2e-netcp.dtsi b/sys/gnu/dts/arm/k2e-netcp.dtsi deleted file mode 100644 index ac990f67972..00000000000 --- a/sys/gnu/dts/arm/k2e-netcp.dtsi +++ /dev/null @@ -1,229 +0,0 @@ -/* - * Device Tree Source for Keystone 2 Edison Netcp driver - * - * Copyright 2015 Texas Instruments, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -qmss: qmss@2a40000 { - compatible = "ti,keystone-navigator-qmss"; - dma-coherent; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&chipclk13>; - ranges; - queue-range = <0 0x2000>; - linkram0 = <0x100000 0x4000>; - linkram1 = <0 0x10000>; - - qmgrs { - #address-cells = <1>; - #size-cells = <1>; - ranges; - qmgr0 { - managed-queues = <0 0x2000>; - reg = <0x2a40000 0x20000>, - <0x2a06000 0x400>, - <0x2a02000 0x1000>, - <0x2a03000 0x1000>, - <0x23a80000 0x20000>, - <0x2a80000 0x20000>; - reg-names = "peek", "status", "config", - "region", "push", "pop"; - }; - }; - queue-pools { - qpend { - qpend-0 { - qrange = <658 8>; - interrupts =<0 40 0xf04 0 41 0xf04 0 42 0xf04 - 0 43 0xf04 0 44 0xf04 0 45 0xf04 - 0 46 0xf04 0 47 0xf04>; - }; - qpend-1 { - qrange = <528 16>; - interrupts = <0 48 0xf04 0 49 0xf04 0 50 0xf04 - 0 51 0xf04 0 52 0xf04 0 53 0xf04 - 0 54 0xf04 0 55 0xf04 0 56 0xf04 - 0 57 0xf04 0 58 0xf04 0 59 0xf04 - 0 60 0xf04 0 61 0xf04 0 62 0xf04 - 0 63 0xf04>; - qalloc-by-id; - }; - qpend-2 { - qrange = <544 16>; - interrupts = <0 64 0xf04 0 65 0xf04 0 66 0xf04 - 0 59 0xf04 0 68 0xf04 0 69 0xf04 - 0 70 0xf04 0 71 0xf04 0 72 0xf04 - 0 73 0xf04 0 74 0xf04 0 75 0xf04 - 0 76 0xf04 0 77 0xf04 0 78 0xf04 - 0 79 0xf04>; - }; - }; - general-purpose { - gp-0 { - qrange = <4000 64>; - }; - netcp-tx { - qrange = <896 128>; - qalloc-by-id; - }; - }; - accumulator { - acc-low-0 { - qrange = <480 32>; - accumulator = <0 47 16 2 50>; - interrupts = <0 226 0xf01>; - multi-queue; - qalloc-by-id; - }; - }; - }; - - descriptor-regions { - #address-cells = <1>; - #size-cells = <1>; - ranges; - region-12 { - id = <12>; - region-spec = <8192 128>; /* num_desc desc_size */ - link-index = <0x4000>; - }; - }; - - pdsps { - #address-cells = <1>; - #size-cells = <1>; - ranges; - pdsp0@0x2a10000 { - reg = <0x2a10000 0x1000 /*iram */ - 0x2a0f000 0x100 /*reg*/ - 0x2a0c000 0x3c8 /*intd */ - 0x2a20000 0x4000>; /*cmd*/ - id = <0>; - }; - }; -}; /* qmss */ - -knav_dmas: knav_dmas@0 { - compatible = "ti,keystone-navigator-dma"; - clocks = <&papllclk>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - ti,navigator-cloud-address = <0x23a80000 0x23a90000 - 0x23a80000 0x23a90000>; - - dma_gbe: dma_gbe@0 { - reg = <0x24186000 0x100>, - <0x24187000 0x2a0>, - <0x24188000 0xb60>, - <0x24186100 0x80>, - <0x24189000 0x1000>; - reg-names = "global", "txchan", "rxchan", - "txsched", "rxflow"; - }; -}; - -netcp: netcp@24000000 { - reg = <0x2620110 0x8>; - reg-names = "efuse"; - compatible = "ti,netcp-1.0"; - #address-cells = <1>; - #size-cells = <1>; - - /* NetCP address range */ - ranges = <0 0x24000000 0x1000000>; - - clocks = <&papllclk>, <&clkcpgmac>, <&chipclk12>; - dma-coherent; - - ti,navigator-dmas = <&dma_gbe 0>, - <&dma_gbe 8>, - <&dma_gbe 0>; - ti,navigator-dma-names = "netrx0", "netrx1", "nettx"; - - netcp-devices { - #address-cells = <1>; - #size-cells = <1>; - ranges; - gbe@200000 { /* ETHSS */ - label = "netcp-gbe"; - compatible = "ti,netcp-gbe-9"; - reg = <0x200000 0x900>, <0x220000 0x20000>; - /* enable-ale; */ - tx-queue = <896>; - tx-channel = "nettx"; - - interfaces { - gbe0: interface-0 { - slave-port = <0>; - link-interface = <1>; - phy-handle = <ðphy0>; - }; - gbe1: interface-1 { - slave-port = <1>; - link-interface = <1>; - phy-handle = <ðphy1>; - }; - }; - - secondary-slave-ports { - port-2 { - slave-port = <2>; - link-interface = <2>; - }; - port-3 { - slave-port = <3>; - link-interface = <2>; - }; - port-4 { - slave-port = <4>; - link-interface = <2>; - }; - port-5 { - slave-port = <5>; - link-interface = <2>; - }; - port-6 { - slave-port = <6>; - link-interface = <2>; - }; - port-7 { - slave-port = <7>; - link-interface = <2>; - }; - }; - }; - }; - - netcp-interfaces { - interface-0 { - rx-channel = "netrx0"; - rx-pool = <1024 12>; - tx-pool = <1024 12>; - rx-queue-depth = <128 128 0 0>; - rx-buffer-size = <1518 4096 0 0>; - rx-queue = <528>; - tx-completion-queue = <530>; - efuse-mac = <1>; - netcp-gbe = <&gbe0>; - - }; - interface-1 { - rx-channel = "netrx1"; - rx-pool = <1024 12>; - tx-pool = <1024 12>; - rx-queue-depth = <128 128 0 0>; - rx-buffer-size = <1518 4096 0 0>; - rx-queue = <529>; - tx-completion-queue = <531>; - efuse-mac = <0>; - local-mac-address = [02 18 31 7e 3e 00]; - netcp-gbe = <&gbe1>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/k2e.dtsi b/sys/gnu/dts/arm/k2e.dtsi deleted file mode 100644 index 1097dada56d..00000000000 --- a/sys/gnu/dts/arm/k2e.dtsi +++ /dev/null @@ -1,150 +0,0 @@ -/* - * Copyright 2013-2014 Texas Instruments, Inc. - * - * Keystone 2 Edison soc device tree - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/ { - compatible = "ti,k2e", "ti,keystone"; - model = "Texas Instruments Keystone 2 Edison SoC"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - interrupt-parent = <&gic>; - - cpu@0 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <0>; - }; - - cpu@1 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <1>; - }; - - cpu@2 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <2>; - }; - - cpu@3 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <3>; - }; - }; - - soc { - /include/ "k2e-clocks.dtsi" - - usb: usb@2680000 { - interrupts = ; - dwc3@2690000 { - interrupts = ; - }; - }; - - usb1_phy: usb_phy@2620750 { - compatible = "ti,keystone-usbphy"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x2620750 24>; - status = "disabled"; - }; - - usb1: usb@25000000 { - compatible = "ti,keystone-dwc3"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x25000000 0x10000>; - clocks = <&clkusb1>; - clock-names = "usb"; - interrupts = ; - ranges; - dma-coherent; - dma-ranges; - status = "disabled"; - - dwc3@25010000 { - compatible = "synopsys,dwc3"; - reg = <0x25010000 0x70000>; - interrupts = ; - usb-phy = <&usb1_phy>, <&usb1_phy>; - }; - }; - - dspgpio0: keystone_dsp_gpio@02620240 { - compatible = "ti,keystone-dsp-gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio,syscon-dev = <&devctrl 0x240>; - }; - - pcie1: pcie@21020000 { - compatible = "ti,keystone-pcie","snps,dw-pcie"; - clocks = <&clkpcie1>; - clock-names = "pcie"; - #address-cells = <3>; - #size-cells = <2>; - reg = <0x21021000 0x2000>, <0x21020000 0x1000>, <0x02620128 4>; - ranges = <0x81000000 0 0 0x23260000 0x4000 0x4000 - 0x82000000 0 0x60000000 0x60000000 0 0x10000000>; - - status = "disabled"; - device_type = "pci"; - num-lanes = <2>; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie_intc1 0>, /* INT A */ - <0 0 0 2 &pcie_intc1 1>, /* INT B */ - <0 0 0 3 &pcie_intc1 2>, /* INT C */ - <0 0 0 4 &pcie_intc1 3>; /* INT D */ - - pcie_msi_intc1: msi-interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - interrupt-parent = <&gic>; - interrupts = , - , - , - , - , - , - , - ; - }; - - pcie_intc1: legacy-interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - interrupt-parent = <&gic>; - interrupts = , - , - , - ; - }; - }; - - mdio: mdio@24200f00 { - compatible = "ti,keystone_mdio", "ti,davinci_mdio"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x24200f00 0x100>; - status = "disabled"; - clocks = <&clkcpgmac>; - clock-names = "fck"; - bus_freq = <2500000>; - }; - /include/ "k2e-netcp.dtsi" - }; -}; diff --git a/sys/gnu/dts/arm/k2hk-clocks.dtsi b/sys/gnu/dts/arm/k2hk-clocks.dtsi deleted file mode 100644 index af9b7190533..00000000000 --- a/sys/gnu/dts/arm/k2hk-clocks.dtsi +++ /dev/null @@ -1,425 +0,0 @@ -/* - * Copyright 2013-2014 Texas Instruments, Inc. - * - * Keystone 2 Kepler/Hawking SoC clock nodes - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -clocks { - armpllclk: armpllclk@2620370 { - #clock-cells = <0>; - compatible = "ti,keystone,pll-clock"; - clocks = <&refclkarm>; - clock-output-names = "arm-pll-clk"; - reg = <0x02620370 4>; - reg-names = "control"; - }; - - mainpllclk: mainpllclk@2310110 { - #clock-cells = <0>; - compatible = "ti,keystone,main-pll-clock"; - clocks = <&refclksys>; - reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>; - reg-names = "control", "multiplier", "post-divider"; - }; - - papllclk: papllclk@2620358 { - #clock-cells = <0>; - compatible = "ti,keystone,pll-clock"; - clocks = <&refclkpass>; - clock-output-names = "papllclk"; - reg = <0x02620358 4>; - reg-names = "control"; - }; - - ddr3apllclk: ddr3apllclk@2620360 { - #clock-cells = <0>; - compatible = "ti,keystone,pll-clock"; - clocks = <&refclkddr3a>; - clock-output-names = "ddr-3a-pll-clk"; - reg = <0x02620360 4>; - reg-names = "control"; - }; - - ddr3bpllclk: ddr3bpllclk@2620368 { - #clock-cells = <0>; - compatible = "ti,keystone,pll-clock"; - clocks = <&refclkddr3b>; - clock-output-names = "ddr-3b-pll-clk"; - reg = <0x02620368 4>; - reg-names = "control"; - }; - - clktsip: clktsip { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk16>; - clock-output-names = "tsip"; - reg = <0x02350000 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; - - clksrio: clksrio { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk1rstiso13>; - clock-output-names = "srio"; - reg = <0x0235002c 0xb00>, <0x02350010 0x400>; - reg-names = "control", "domain"; - domain-id = <4>; - }; - - clkhyperlink0: clkhyperlink0 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk12>; - clock-output-names = "hyperlink-0"; - reg = <0x02350030 0xb00>, <0x02350014 0x400>; - reg-names = "control", "domain"; - domain-id = <5>; - }; - - clkgem1: clkgem1 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk1>; - clock-output-names = "gem1"; - reg = <0x02350040 0xb00>, <0x02350024 0x400>; - reg-names = "control", "domain"; - domain-id = <9>; - }; - - clkgem2: clkgem2 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk1>; - clock-output-names = "gem2"; - reg = <0x02350044 0xb00>, <0x02350028 0x400>; - reg-names = "control", "domain"; - domain-id = <10>; - }; - - clkgem3: clkgem3 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk1>; - clock-output-names = "gem3"; - reg = <0x02350048 0xb00>, <0x0235002c 0x400>; - reg-names = "control", "domain"; - domain-id = <11>; - }; - - clkgem4: clkgem4 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk1>; - clock-output-names = "gem4"; - reg = <0x0235004c 0xb00>, <0x02350030 0x400>; - reg-names = "control", "domain"; - domain-id = <12>; - }; - - clkgem5: clkgem5 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk1>; - clock-output-names = "gem5"; - reg = <0x02350050 0xb00>, <0x02350034 0x400>; - reg-names = "control", "domain"; - domain-id = <13>; - }; - - clkgem6: clkgem6 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk1>; - clock-output-names = "gem6"; - reg = <0x02350054 0xb00>, <0x02350038 0x400>; - reg-names = "control", "domain"; - domain-id = <14>; - }; - - clkgem7: clkgem7 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk1>; - clock-output-names = "gem7"; - reg = <0x02350058 0xb00>, <0x0235003c 0x400>; - reg-names = "control", "domain"; - domain-id = <15>; - }; - - clkddr31: clkddr31 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "ddr3-1"; - reg = <0x02350060 0xb00>, <0x02350040 0x400>; - reg-names = "control", "domain"; - domain-id = <16>; - }; - - clktac: clktac { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "tac"; - reg = <0x02350064 0xb00>, <0x02350044 0x400>; - reg-names = "control", "domain"; - domain-id = <17>; - }; - - clkrac01: clkrac01 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "rac-01"; - reg = <0x02350068 0xb00>, <0x02350044 0x400>; - reg-names = "control", "domain"; - domain-id = <17>; - }; - - clkrac23: clkrac23 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "rac-23"; - reg = <0x0235006c 0xb00>, <0x02350048 0x400>; - reg-names = "control", "domain"; - domain-id = <18>; - }; - - clkfftc0: clkfftc0 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "fftc-0"; - reg = <0x02350070 0xb00>, <0x0235004c 0x400>; - reg-names = "control", "domain"; - domain-id = <19>; - }; - - clkfftc1: clkfftc1 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "fftc-1"; - reg = <0x02350074 0xb00>, <0x0235004c 0x400>; - reg-names = "control", "domain"; - domain-id = <19>; - }; - - clkfftc2: clkfftc2 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "fftc-2"; - reg = <0x02350078 0xb00>, <0x02350050 0x400>; - reg-names = "control", "domain"; - domain-id = <20>; - }; - - clkfftc3: clkfftc3 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "fftc-3"; - reg = <0x0235007c 0xb00>, <0x02350050 0x400>; - reg-names = "control", "domain"; - domain-id = <20>; - }; - - clkfftc4: clkfftc4 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "fftc-4"; - reg = <0x02350080 0xb00>, <0x02350050 0x400>; - reg-names = "control", "domain"; - domain-id = <20>; - }; - - clkfftc5: clkfftc5 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "fftc-5"; - reg = <0x02350084 0xb00>, <0x02350050 0x400>; - reg-names = "control", "domain"; - domain-id = <20>; - }; - - clkaif: clkaif { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "aif"; - reg = <0x02350088 0xb00>, <0x02350054 0x400>; - reg-names = "control", "domain"; - domain-id = <21>; - }; - - clktcp3d0: clktcp3d0 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "tcp3d-0"; - reg = <0x0235008c 0xb00>, <0x02350058 0x400>; - reg-names = "control", "domain"; - domain-id = <22>; - }; - - clktcp3d1: clktcp3d1 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "tcp3d-1"; - reg = <0x02350090 0xb00>, <0x02350058 0x400>; - reg-names = "control", "domain"; - domain-id = <22>; - }; - - clktcp3d2: clktcp3d2 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "tcp3d-2"; - reg = <0x02350094 0xb00>, <0x0235005c 0x400>; - reg-names = "control", "domain"; - domain-id = <23>; - }; - - clktcp3d3: clktcp3d3 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "tcp3d-3"; - reg = <0x02350098 0xb00>, <0x0235005c 0x400>; - reg-names = "control", "domain"; - domain-id = <23>; - }; - - clkvcp0: clkvcp0 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "vcp-0"; - reg = <0x0235009c 0xb00>, <0x02350060 0x400>; - reg-names = "control", "domain"; - domain-id = <24>; - }; - - clkvcp1: clkvcp1 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "vcp-1"; - reg = <0x023500a0 0xb00>, <0x02350060 0x400>; - reg-names = "control", "domain"; - domain-id = <24>; - }; - - clkvcp2: clkvcp2 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "vcp-2"; - reg = <0x023500a4 0xb00>, <0x02350060 0x400>; - reg-names = "control", "domain"; - domain-id = <24>; - }; - - clkvcp3: clkvcp3 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "vcp-3"; - reg = <0x023500a8 0xb00>, <0x02350060 0x400>; - reg-names = "control", "domain"; - domain-id = <24>; - }; - - clkvcp4: clkvcp4 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "vcp-4"; - reg = <0x023500ac 0xb00>, <0x02350064 0x400>; - reg-names = "control", "domain"; - domain-id = <25>; - }; - - clkvcp5: clkvcp5 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "vcp-5"; - reg = <0x023500b0 0xb00>, <0x02350064 0x400>; - reg-names = "control", "domain"; - domain-id = <25>; - }; - - clkvcp6: clkvcp6 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "vcp-6"; - reg = <0x023500b4 0xb00>, <0x02350064 0x400>; - reg-names = "control", "domain"; - domain-id = <25>; - }; - - clkvcp7: clkvcp7 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "vcp-7"; - reg = <0x023500b8 0xb00>, <0x02350064 0x400>; - reg-names = "control", "domain"; - domain-id = <25>; - }; - - clkbcp: clkbcp { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "bcp"; - reg = <0x023500bc 0xb00>, <0x02350068 0x400>; - reg-names = "control", "domain"; - domain-id = <26>; - }; - - clkdxb: clkdxb { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "dxb"; - reg = <0x023500c0 0xb00>, <0x0235006c 0x400>; - reg-names = "control", "domain"; - domain-id = <27>; - }; - - clkhyperlink1: clkhyperlink1 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk12>; - clock-output-names = "hyperlink-1"; - reg = <0x023500c4 0xb00>, <0x02350070 0x400>; - reg-names = "control", "domain"; - domain-id = <28>; - }; - - clkxge: clkxge { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "xge"; - reg = <0x023500c8 0xb00>, <0x02350074 0x400>; - reg-names = "control", "domain"; - domain-id = <29>; - }; -}; diff --git a/sys/gnu/dts/arm/k2hk-evm.dts b/sys/gnu/dts/arm/k2hk-evm.dts deleted file mode 100644 index 8161bf53271..00000000000 --- a/sys/gnu/dts/arm/k2hk-evm.dts +++ /dev/null @@ -1,182 +0,0 @@ -/* - * Copyright 2013-2014 Texas Instruments, Inc. - * - * Keystone 2 Kepler/Hawking EVM device tree - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -/dts-v1/; - -#include "keystone.dtsi" -#include "k2hk.dtsi" - -/ { - compatible = "ti,k2hk-evm", "ti,k2hk", "ti,keystone"; - model = "Texas Instruments Keystone 2 Kepler/Hawking EVM"; - - soc { - clocks { - refclksys: refclksys { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <122880000>; - clock-output-names = "refclk-sys"; - }; - - refclkpass: refclkpass { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <122880000>; - clock-output-names = "refclk-pass"; - }; - - refclkarm: refclkarm { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "refclk-arm"; - }; - - refclkddr3a: refclkddr3a { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <100000000>; - clock-output-names = "refclk-ddr3a"; - }; - - refclkddr3b: refclkddr3b { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <100000000>; - clock-output-names = "refclk-ddr3b"; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - debug1_1 { - label = "keystone:green:debug1"; - gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; /* 12 */ - }; - - debug1_2 { - label = "keystone:red:debug1"; - gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; /* 13 */ - }; - - debug2 { - label = "keystone:blue:debug2"; - gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; /* 14 */ - }; - - debug3 { - label = "keystone:blue:debug3"; - gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; /* 15 */ - }; - }; -}; - -&usb_phy { - status = "okay"; -}; - -&usb { - status = "okay"; -}; - -&aemif { - cs0 { - #address-cells = <2>; - #size-cells = <1>; - clock-ranges; - ranges; - - ti,cs-chipselect = <0>; - /* all timings in nanoseconds */ - ti,cs-min-turnaround-ns = <12>; - ti,cs-read-hold-ns = <6>; - ti,cs-read-strobe-ns = <23>; - ti,cs-read-setup-ns = <9>; - ti,cs-write-hold-ns = <8>; - ti,cs-write-strobe-ns = <23>; - ti,cs-write-setup-ns = <8>; - - nand@0,0 { - compatible = "ti,keystone-nand","ti,davinci-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0 0 0x4000000 - 1 0 0x0000100>; - - ti,davinci-chipselect = <0>; - ti,davinci-mask-ale = <0x2000>; - ti,davinci-mask-cle = <0x4000>; - ti,davinci-mask-chipsel = <0>; - nand-ecc-mode = "hw"; - ti,davinci-ecc-bits = <4>; - nand-on-flash-bbt; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x100000>; - read-only; - }; - - partition@100000 { - label = "params"; - reg = <0x100000 0x80000>; - read-only; - }; - - partition@180000 { - label = "ubifs"; - reg = <0x180000 0x1fe80000>; - }; - }; - }; -}; - -&i2c0 { - dtt@50 { - compatible = "at,24c1024"; - reg = <0x50>; - }; -}; - -&spi0 { - nor_flash: n25q128a11@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "Micron,n25q128a11"; - spi-max-frequency = <54000000>; - m25p,fast-read; - reg = <0>; - - partition@0 { - label = "u-boot-spl"; - reg = <0x0 0x80000>; - read-only; - }; - - partition@1 { - label = "misc"; - reg = <0x80000 0xf80000>; - }; - }; -}; - -&mdio { - status = "ok"; - ethphy0: ethernet-phy@0 { - compatible = "marvell,88E1111", "ethernet-phy-ieee802.3-c22"; - reg = <0>; - }; - - ethphy1: ethernet-phy@1 { - compatible = "marvell,88E1111", "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; -}; diff --git a/sys/gnu/dts/arm/k2hk-netcp.dtsi b/sys/gnu/dts/arm/k2hk-netcp.dtsi deleted file mode 100644 index f86d6ddb832..00000000000 --- a/sys/gnu/dts/arm/k2hk-netcp.dtsi +++ /dev/null @@ -1,232 +0,0 @@ -/* - * Device Tree Source for Keystone 2 Hawking Netcp driver - * - * Copyright 2015 Texas Instruments, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -qmss: qmss@2a40000 { - compatible = "ti,keystone-navigator-qmss"; - dma-coherent; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&chipclk13>; - ranges; - queue-range = <0 0x4000>; - linkram0 = <0x100000 0x8000>; - linkram1 = <0x0 0x10000>; - - qmgrs { - #address-cells = <1>; - #size-cells = <1>; - ranges; - qmgr0 { - managed-queues = <0 0x2000>; - reg = <0x2a40000 0x20000>, - <0x2a06000 0x400>, - <0x2a02000 0x1000>, - <0x2a03000 0x1000>, - <0x23a80000 0x20000>, - <0x2a80000 0x20000>; - reg-names = "peek", "status", "config", - "region", "push", "pop"; - }; - - qmgr1 { - managed-queues = <0x2000 0x2000>; - reg = <0x2a60000 0x20000>, - <0x2a06400 0x400>, - <0x2a04000 0x1000>, - <0x2a05000 0x1000>, - <0x23aa0000 0x20000>, - <0x2aa0000 0x20000>; - reg-names = "peek", "status", "config", - "region", "push", "pop"; - }; - }; - - queue-pools { - qpend { - qpend-0 { - qrange = <658 8>; - interrupts =<0 40 0xf04 0 41 0xf04 0 42 0xf04 - 0 43 0xf04 0 44 0xf04 0 45 0xf04 - 0 46 0xf04 0 47 0xf04>; - }; - qpend-1 { - qrange = <8704 16>; - interrupts = <0 48 0xf04 0 49 0xf04 0 50 0xf04 - 0 51 0xf04 0 52 0xf04 0 53 0xf04 - 0 54 0xf04 0 55 0xf04 0 56 0xf04 - 0 57 0xf04 0 58 0xf04 0 59 0xf04 - 0 60 0xf04 0 61 0xf04 0 62 0xf04 - 0 63 0xf04>; - qalloc-by-id; - }; - qpend-2 { - qrange = <8720 16>; - interrupts = <0 64 0xf04 0 65 0xf04 0 66 0xf04 - 0 59 0xf04 0 68 0xf04 0 69 0xf04 - 0 70 0xf04 0 71 0xf04 0 72 0xf04 - 0 73 0xf04 0 74 0xf04 0 75 0xf04 - 0 76 0xf04 0 77 0xf04 0 78 0xf04 - 0 79 0xf04>; - }; - }; - general-purpose { - gp-0 { - qrange = <4000 64>; - }; - netcp-tx { - qrange = <640 9>; - qalloc-by-id; - }; - netcpx-tx { - qrange = <8752 8>; - qalloc-by-id; - }; - }; - accumulator { - acc-low-0 { - qrange = <480 32>; - accumulator = <0 47 16 2 50>; - interrupts = <0 226 0xf01>; - multi-queue; - qalloc-by-id; - }; - }; - }; - - descriptor-regions { - #address-cells = <1>; - #size-cells = <1>; - ranges; - region-12 { - id = <12>; - region-spec = <8192 128>; /* num_desc desc_size */ - link-index = <0x4000>; - }; - }; - - pdsps { - #address-cells = <1>; - #size-cells = <1>; - ranges; - pdsp0@0x2a10000 { - reg = <0x2a10000 0x1000 /*iram */ - 0x2a0f000 0x100 /*reg*/ - 0x2a0c000 0x3c8 /*intd */ - 0x2a20000 0x4000>; /*cmd*/ - id = <0>; - }; - }; -}; /* qmss */ - -knav_dmas: knav_dmas@0 { - compatible = "ti,keystone-navigator-dma"; - clocks = <&papllclk>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - ti,navigator-cloud-address = <0x23a80000 0x23a90000 - 0x23aa0000 0x23ab0000>; - - dma_gbe: dma_gbe@0 { - reg = <0x2004000 0x100>, - <0x2004400 0x120>, - <0x2004800 0x300>, - <0x2004c00 0x120>, - <0x2005000 0x400>; - reg-names = "global", "txchan", "rxchan", - "txsched", "rxflow"; - }; -}; - -netcp: netcp@2000000 { - reg = <0x2620110 0x8>; - reg-names = "efuse"; - compatible = "ti,netcp-1.0"; - #address-cells = <1>; - #size-cells = <1>; - - /* NetCP address range */ - ranges = <0 0x2000000 0x100000>; - - clocks = <&papllclk>, <&clkcpgmac>, <&chipclk12>; - dma-coherent; - - ti,navigator-dmas = <&dma_gbe 22>, - <&dma_gbe 23>, - <&dma_gbe 8>; - ti,navigator-dma-names = "netrx0", "netrx1", "nettx"; - - netcp-devices { - ranges; - #address-cells = <1>; - #size-cells = <1>; - gbe@90000 { /* ETHSS */ - #address-cells = <1>; - #size-cells = <1>; - label = "netcp-gbe"; - compatible = "ti,netcp-gbe"; - reg = <0x90000 0x300>, <0x90400 0x400>, <0x90800 0x700>; - /* enable-ale; */ - tx-queue = <648>; - tx-channel = "nettx"; - - interfaces { - gbe0: interface-0 { - slave-port = <0>; - link-interface = <1>; - phy-handle = <ðphy0>; - }; - gbe1: interface-1 { - slave-port = <1>; - link-interface = <1>; - phy-handle = <ðphy1>; - }; - }; - - secondary-slave-ports { - port-2 { - slave-port = <2>; - link-interface = <2>; - }; - port-3 { - slave-port = <3>; - link-interface = <2>; - }; - }; - }; - }; - - netcp-interfaces { - interface-0 { - rx-channel = "netrx0"; - rx-pool = <1024 12>; - tx-pool = <1024 12>; - rx-queue-depth = <128 128 0 0>; - rx-buffer-size = <1518 4096 0 0>; - rx-queue = <8704>; - tx-completion-queue = <8706>; - efuse-mac = <1>; - netcp-gbe = <&gbe0>; - - }; - interface-1 { - rx-channel = "netrx1"; - rx-pool = <1024 12>; - tx-pool = <1024 12>; - rx-queue-depth = <128 128 0 0>; - rx-buffer-size = <1518 4096 0 0>; - rx-queue = <8705>; - tx-completion-queue = <8707>; - efuse-mac = <0>; - local-mac-address = [02 18 31 7e 3e 6f]; - netcp-gbe = <&gbe1>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/k2hk.dtsi b/sys/gnu/dts/arm/k2hk.dtsi deleted file mode 100644 index ada4c7ac96e..00000000000 --- a/sys/gnu/dts/arm/k2hk.dtsi +++ /dev/null @@ -1,117 +0,0 @@ -/* - * Copyright 2013-2014 Texas Instruments, Inc. - * - * Keystone 2 Kepler/Hawking soc specific device tree - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/ { - compatible = "ti,k2hk", "ti,keystone"; - model = "Texas Instruments Keystone 2 Kepler/Hawking SoC"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - interrupt-parent = <&gic>; - - cpu@0 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <0>; - }; - - cpu@1 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <1>; - }; - - cpu@2 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <2>; - }; - - cpu@3 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <3>; - }; - }; - - soc { - /include/ "k2hk-clocks.dtsi" - - dspgpio0: keystone_dsp_gpio@02620240 { - compatible = "ti,keystone-dsp-gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio,syscon-dev = <&devctrl 0x240>; - }; - - dspgpio1: keystone_dsp_gpio@2620244 { - compatible = "ti,keystone-dsp-gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio,syscon-dev = <&devctrl 0x244>; - }; - - dspgpio2: keystone_dsp_gpio@2620248 { - compatible = "ti,keystone-dsp-gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio,syscon-dev = <&devctrl 0x248>; - }; - - dspgpio3: keystone_dsp_gpio@262024c { - compatible = "ti,keystone-dsp-gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio,syscon-dev = <&devctrl 0x24c>; - }; - - dspgpio4: keystone_dsp_gpio@2620250 { - compatible = "ti,keystone-dsp-gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio,syscon-dev = <&devctrl 0x250>; - }; - - dspgpio5: keystone_dsp_gpio@2620254 { - compatible = "ti,keystone-dsp-gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio,syscon-dev = <&devctrl 0x254>; - }; - - dspgpio6: keystone_dsp_gpio@2620258 { - compatible = "ti,keystone-dsp-gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio,syscon-dev = <&devctrl 0x258>; - }; - - dspgpio7: keystone_dsp_gpio@262025c { - compatible = "ti,keystone-dsp-gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio,syscon-dev = <&devctrl 0x25c>; - }; - - mdio: mdio@02090300 { - compatible = "ti,keystone_mdio", "ti,davinci_mdio"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x02090300 0x100>; - status = "disabled"; - clocks = <&clkcpgmac>; - clock-names = "fck"; - bus_freq = <2500000>; - }; - /include/ "k2hk-netcp.dtsi" - }; -}; diff --git a/sys/gnu/dts/arm/k2l-clocks.dtsi b/sys/gnu/dts/arm/k2l-clocks.dtsi deleted file mode 100644 index ef8464bb11f..00000000000 --- a/sys/gnu/dts/arm/k2l-clocks.dtsi +++ /dev/null @@ -1,266 +0,0 @@ -/* - * Copyright 2013-2014 Texas Instruments, Inc. - * - * Keystone 2 lamarr SoC clock nodes - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -clocks { - armpllclk: armpllclk@2620370 { - #clock-cells = <0>; - compatible = "ti,keystone,pll-clock"; - clocks = <&refclksys>; - clock-output-names = "arm-pll-clk"; - reg = <0x02620370 4>; - reg-names = "control"; - }; - - mainpllclk: mainpllclk@2310110 { - #clock-cells = <0>; - compatible = "ti,keystone,main-pll-clock"; - clocks = <&refclksys>; - reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>; - reg-names = "control", "multiplier", "post-divider"; - }; - - papllclk: papllclk@2620358 { - #clock-cells = <0>; - compatible = "ti,keystone,pll-clock"; - clocks = <&refclksys>; - clock-output-names = "papllclk"; - reg = <0x02620358 4>; - reg-names = "control"; - }; - - ddr3apllclk: ddr3apllclk@2620360 { - #clock-cells = <0>; - compatible = "ti,keystone,pll-clock"; - clocks = <&refclksys>; - clock-output-names = "ddr-3a-pll-clk"; - reg = <0x02620360 4>; - reg-names = "control"; - }; - - clkdfeiqnsys: clkdfeiqnsys { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk12>; - clock-output-names = "dfe"; - reg-names = "control", "domain"; - reg = <0x02350004 0xb00>, <0x02350000 0x400>; - domain-id = <0>; - }; - - clkpcie1: clkpcie1 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk12>; - clock-output-names = "pcie"; - reg = <0x0235002c 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <4>; - }; - - clkgem1: clkgem1 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk1>; - clock-output-names = "gem1"; - reg = <0x02350040 0xb00>, <0x02350024 0x400>; - reg-names = "control", "domain"; - domain-id = <9>; - }; - - clkgem2: clkgem2 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk1>; - clock-output-names = "gem2"; - reg = <0x02350044 0xb00>, <0x02350028 0x400>; - reg-names = "control", "domain"; - domain-id = <10>; - }; - - clkgem3: clkgem3 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk1>; - clock-output-names = "gem3"; - reg = <0x02350048 0xb00>, <0x0235002c 0x400>; - reg-names = "control", "domain"; - domain-id = <11>; - }; - - clktac: clktac { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "tac"; - reg = <0x02350064 0xb00>, <0x02350044 0x400>; - reg-names = "control", "domain"; - domain-id = <17>; - }; - - clkrac: clkrac { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "rac"; - reg = <0x02350068 0xb00>, <0x02350044 0x400>; - reg-names = "control", "domain"; - domain-id = <17>; - }; - - clkdfepd0: clkdfepd0 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "dfe-pd0"; - reg = <0x0235006c 0xb00>, <0x02350044 0x400>; - reg-names = "control", "domain"; - domain-id = <18>; - }; - - clkfftc0: clkfftc0 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "fftc-0"; - reg = <0x02350070 0xb00>, <0x0235004c 0x400>; - reg-names = "control", "domain"; - domain-id = <19>; - }; - - clkosr: clkosr { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "osr"; - reg = <0x02350088 0xb00>, <0x0235004c 0x400>; - reg-names = "control", "domain"; - domain-id = <21>; - }; - - clktcp3d0: clktcp3d0 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "tcp3d-0"; - reg = <0x0235008c 0xb00>, <0x02350058 0x400>; - reg-names = "control", "domain"; - domain-id = <22>; - }; - - clktcp3d1: clktcp3d1 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "tcp3d-1"; - reg = <0x02350094 0xb00>, <0x02350058 0x400>; - reg-names = "control", "domain"; - domain-id = <23>; - }; - - clkvcp0: clkvcp0 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "vcp-0"; - reg = <0x0235009c 0xb00>, <0x02350060 0x400>; - reg-names = "control", "domain"; - domain-id = <24>; - }; - - clkvcp1: clkvcp1 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "vcp-1"; - reg = <0x023500a0 0xb00>, <0x02350060 0x400>; - reg-names = "control", "domain"; - domain-id = <24>; - }; - - clkvcp2: clkvcp2 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "vcp-2"; - reg = <0x023500a4 0xb00>, <0x02350060 0x400>; - reg-names = "control", "domain"; - domain-id = <24>; - }; - - clkvcp3: clkvcp3 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "vcp-3"; - reg = <0x023500a8 0xb00>, <0x02350060 0x400>; - reg-names = "control", "domain"; - domain-id = <24>; - }; - - clkbcp: clkbcp { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "bcp"; - reg = <0x023500bc 0xb00>, <0x02350068 0x400>; - reg-names = "control", "domain"; - domain-id = <26>; - }; - - clkdfepd1: clkdfepd1 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "dfe-pd1"; - reg = <0x023500c0 0xb00>, <0x02350044 0x400>; - reg-names = "control", "domain"; - domain-id = <27>; - }; - - clkfftc1: clkfftc1 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "fftc-1"; - reg = <0x023500c4 0xb00>, <0x023504c0 0x400>; - reg-names = "control", "domain"; - domain-id = <28>; - }; - - clkiqnail: clkiqnail { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "iqn-ail"; - reg = <0x023500c8 0xb00>, <0x0235004c 0x400>; - reg-names = "control", "domain"; - domain-id = <29>; - }; - - clkuart2: clkuart2 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&clkmodrst0>; - clock-output-names = "uart2"; - reg = <0x02350000 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; - - clkuart3: clkuart3 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&clkmodrst0>; - clock-output-names = "uart3"; - reg = <0x02350000 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; -}; diff --git a/sys/gnu/dts/arm/k2l-evm.dts b/sys/gnu/dts/arm/k2l-evm.dts deleted file mode 100644 index 00861244d78..00000000000 --- a/sys/gnu/dts/arm/k2l-evm.dts +++ /dev/null @@ -1,131 +0,0 @@ -/* - * Copyright 2014 Texas Instruments, Inc. - * - * Keystone 2 Lamarr EVM device tree - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -/dts-v1/; - -#include "keystone.dtsi" -#include "k2l.dtsi" - -/ { - compatible = "ti,k2l-evm", "ti,k2l", "ti,keystone"; - model = "Texas Instruments Keystone 2 Lamarr EVM"; - - soc { - clocks { - refclksys: refclksys { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <122880000>; - clock-output-names = "refclk-sys"; - }; - }; - }; -}; - -&usb_phy { - status = "okay"; -}; - -&usb { - status = "okay"; -}; - -&i2c0 { - dtt@50 { - compatible = "at,24c1024"; - reg = <0x50>; - }; -}; - -&aemif { - cs0 { - #address-cells = <2>; - #size-cells = <1>; - clock-ranges; - ranges; - - ti,cs-chipselect = <0>; - /* all timings in nanoseconds */ - ti,cs-min-turnaround-ns = <12>; - ti,cs-read-hold-ns = <6>; - ti,cs-read-strobe-ns = <23>; - ti,cs-read-setup-ns = <9>; - ti,cs-write-hold-ns = <8>; - ti,cs-write-strobe-ns = <23>; - ti,cs-write-setup-ns = <8>; - - nand@0,0 { - compatible = "ti,keystone-nand","ti,davinci-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0 0 0x4000000 - 1 0 0x0000100>; - - ti,davinci-chipselect = <0>; - ti,davinci-mask-ale = <0x2000>; - ti,davinci-mask-cle = <0x4000>; - ti,davinci-mask-chipsel = <0>; - nand-ecc-mode = "hw"; - ti,davinci-ecc-bits = <4>; - nand-on-flash-bbt; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x100000>; - read-only; - }; - - partition@100000 { - label = "params"; - reg = <0x100000 0x80000>; - read-only; - }; - - partition@180000 { - label = "ubifs"; - reg = <0x180000 0x7FE80000>; - }; - }; - }; -}; - -&spi0 { - nor_flash: n25q128a11@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "Micron,n25q128a11"; - spi-max-frequency = <54000000>; - m25p,fast-read; - reg = <0>; - - partition@0 { - label = "u-boot-spl"; - reg = <0x0 0x80000>; - read-only; - }; - - partition@1 { - label = "misc"; - reg = <0x80000 0xf80000>; - }; - }; -}; - -&mdio { - status = "ok"; - ethphy0: ethernet-phy@0 { - compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22"; - reg = <0>; - }; - - ethphy1: ethernet-phy@1 { - compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; -}; diff --git a/sys/gnu/dts/arm/k2l-netcp.dtsi b/sys/gnu/dts/arm/k2l-netcp.dtsi deleted file mode 100644 index 5acbd0dcc2a..00000000000 --- a/sys/gnu/dts/arm/k2l-netcp.dtsi +++ /dev/null @@ -1,212 +0,0 @@ -/* - * Device Tree Source for Keystone 2 Lamarr Netcp driver - * - * Copyright 2015 Texas Instruments, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -qmss: qmss@2a40000 { - compatible = "ti,keystone-navigator-qmss"; - dma-coherent; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&chipclk13>; - ranges; - queue-range = <0 0x2000>; - linkram0 = <0x100000 0x4000>; - linkram1 = <0x70000000 0x10000>; /* 1MB OSR mem */ - - qmgrs { - #address-cells = <1>; - #size-cells = <1>; - ranges; - qmgr0 { - managed-queues = <0 0x2000>; - reg = <0x2a40000 0x20000>, - <0x2a06000 0x400>, - <0x2a02000 0x1000>, - <0x2a03000 0x1000>, - <0x23a80000 0x20000>, - <0x2a80000 0x20000>; - reg-names = "peek", "status", "config", - "region", "push", "pop"; - }; - }; - queue-pools { - qpend { - qpend-0 { - qrange = <658 8>; - interrupts =<0 40 0xf04 0 41 0xf04 0 42 0xf04 - 0 43 0xf04 0 44 0xf04 0 45 0xf04 - 0 46 0xf04 0 47 0xf04>; - }; - qpend-1 { - qrange = <528 16>; - interrupts = <0 48 0xf04 0 49 0xf04 0 50 0xf04 - 0 51 0xf04 0 52 0xf04 0 53 0xf04 - 0 54 0xf04 0 55 0xf04 0 56 0xf04 - 0 57 0xf04 0 58 0xf04 0 59 0xf04 - 0 60 0xf04 0 61 0xf04 0 62 0xf04 - 0 63 0xf04>; - qalloc-by-id; - }; - qpend-2 { - qrange = <544 16>; - interrupts = <0 64 0xf04 0 65 0xf04 0 66 0xf04 - 0 59 0xf04 0 68 0xf04 0 69 0xf04 - 0 70 0xf04 0 71 0xf04 0 72 0xf04 - 0 73 0xf04 0 74 0xf04 0 75 0xf04 - 0 76 0xf04 0 77 0xf04 0 78 0xf04 - 0 79 0xf04>; - }; - }; - general-purpose { - gp-0 { - qrange = <4000 64>; - }; - netcp-tx { - qrange = <896 128>; - qalloc-by-id; - }; - }; - accumulator { - acc-low-0 { - qrange = <480 32>; - accumulator = <0 47 16 2 50>; - interrupts = <0 226 0xf01>; - multi-queue; - }; - }; - }; - - descriptor-regions { - #address-cells = <1>; - #size-cells = <1>; - ranges; - region-12 { - id = <12>; - region-spec = <8192 128>; /* num_desc desc_size */ - link-index = <0x4000>; - }; - }; - - pdsps { - #address-cells = <1>; - #size-cells = <1>; - ranges; - pdsp0@0x2a10000 { - reg = <0x2a10000 0x1000 /*iram */ - 0x2a0f000 0x100 /*reg*/ - 0x2a0c000 0x3c8 /*intd */ - 0x2a20000 0x4000>; /*cmd*/ - id = <0>; - }; - }; - -}; /* qmss */ - -knav_dmas: knav_dmas@0 { - compatible = "ti,keystone-navigator-dma"; - clocks = <&papllclk>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - ti,navigator-cloud-address = <0x23a80000 0x23a90000>; - - dma_gbe: dma_gbe@0 { - reg = <0x26186000 0x100>, - <0x26187000 0x2a0>, - <0x26188000 0xb60>, - <0x26186100 0x80>, - <0x26189000 0x1000>; - reg-names = "global", "txchan", "rxchan", - "txsched", "rxflow"; - }; -}; - -netcp: netcp@26000000 { - reg = <0x2620110 0x8>; - reg-names = "efuse"; - compatible = "ti,netcp-1.0"; - #address-cells = <1>; - #size-cells = <1>; - - /* NetCP address range */ - ranges = <0 0x26000000 0x1000000>; - - clocks = <&clkosr>, <&papllclk>, <&clkcpgmac>, <&chipclk12>; - dma-coherent; - - ti,navigator-dmas = <&dma_gbe 0>, - <&dma_gbe 8>, - <&dma_gbe 0>; - ti,navigator-dma-names = "netrx0", "netrx1", "nettx"; - - netcp-devices { - #address-cells = <1>; - #size-cells = <1>; - ranges; - gbe@200000 { /* ETHSS */ - label = "netcp-gbe"; - compatible = "ti,netcp-gbe-5"; - reg = <0x200000 0x900>, <0x220000 0x20000>; - /* enable-ale; */ - tx-queue = <896>; - tx-channel = "nettx"; - - interfaces { - gbe0: interface-0 { - slave-port = <0>; - link-interface = <1>; - phy-handle = <ðphy0>; - }; - gbe1: interface-1 { - slave-port = <1>; - link-interface = <1>; - phy-handle = <ðphy1>; - }; - }; - - secondary-slave-ports { - port-2 { - slave-port = <2>; - link-interface = <2>; - }; - port-3 { - slave-port = <3>; - link-interface = <2>; - }; - }; - }; - }; - - netcp-interfaces { - interface-0 { - rx-channel = "netrx0"; - rx-pool = <1024 12>; - tx-pool = <1024 12>; - rx-queue-depth = <128 128 0 0>; - rx-buffer-size = <1518 4096 0 0>; - rx-queue = <528>; - tx-completion-queue = <530>; - efuse-mac = <1>; - netcp-gbe = <&gbe0>; - - }; - interface-1 { - rx-channel = "netrx1"; - rx-pool = <1024 12>; - tx-pool = <1024 12>; - rx-queue-depth = <128 128 0 0>; - rx-buffer-size = <1518 4096 0 0>; - rx-queue = <529>; - tx-completion-queue = <531>; - efuse-mac = <0>; - local-mac-address = [02 18 31 7e 3e 7f]; - netcp-gbe = <&gbe1>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/k2l.dtsi b/sys/gnu/dts/arm/k2l.dtsi deleted file mode 100644 index 4446da72b0a..00000000000 --- a/sys/gnu/dts/arm/k2l.dtsi +++ /dev/null @@ -1,111 +0,0 @@ -/* - * Copyright 2014 Texas Instruments, Inc. - * - * Keystone 2 Lamarr SoC specific device tree - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/ { - compatible = "ti,k2l", "ti,keystone"; - model = "Texas Instruments Keystone 2 Lamarr SoC"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - interrupt-parent = <&gic>; - - cpu@0 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <0>; - }; - - cpu@1 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <1>; - }; - }; - - soc { - /include/ "k2l-clocks.dtsi" - - uart2: serial@02348400 { - compatible = "ns16550a"; - current-speed = <115200>; - reg-shift = <2>; - reg-io-width = <4>; - reg = <0x02348400 0x100>; - clocks = <&clkuart2>; - interrupts = ; - }; - - uart3: serial@02348800 { - compatible = "ns16550a"; - current-speed = <115200>; - reg-shift = <2>; - reg-io-width = <4>; - reg = <0x02348800 0x100>; - clocks = <&clkuart3>; - interrupts = ; - }; - - dspgpio0: keystone_dsp_gpio@02620240 { - compatible = "ti,keystone-dsp-gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio,syscon-dev = <&devctrl 0x240>; - }; - - dspgpio1: keystone_dsp_gpio@2620244 { - compatible = "ti,keystone-dsp-gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio,syscon-dev = <&devctrl 0x244>; - }; - - dspgpio2: keystone_dsp_gpio@2620248 { - compatible = "ti,keystone-dsp-gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio,syscon-dev = <&devctrl 0x248>; - }; - - dspgpio3: keystone_dsp_gpio@262024c { - compatible = "ti,keystone-dsp-gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio,syscon-dev = <&devctrl 0x24c>; - }; - - mdio: mdio@26200f00 { - compatible = "ti,keystone_mdio", "ti,davinci_mdio"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x26200f00 0x100>; - status = "disabled"; - clocks = <&clkcpgmac>; - clock-names = "fck"; - bus_freq = <2500000>; - }; - /include/ "k2l-netcp.dtsi" - }; -}; - -&spi0 { - ti,davinci-spi-num-cs = <5>; -}; - -&spi1 { - ti,davinci-spi-num-cs = <3>; -}; - -&spi2 { - ti,davinci-spi-num-cs = <5>; - /* Pin muxed. Enabled and configured by Bootloader */ - status = "disabled"; -}; diff --git a/sys/gnu/dts/arm/keystone-clocks.dtsi b/sys/gnu/dts/arm/keystone-clocks.dtsi deleted file mode 100644 index 0397c3423d2..00000000000 --- a/sys/gnu/dts/arm/keystone-clocks.dtsi +++ /dev/null @@ -1,438 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for Keystone 2 clock tree - * - * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/ - */ - -clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - mainmuxclk: mainmuxclk@2310108 { - #clock-cells = <0>; - compatible = "ti,keystone,pll-mux-clock"; - clocks = <&mainpllclk>, <&refclksys>; - reg = <0x02310108 4>; - bit-shift = <23>; - bit-mask = <1>; - clock-output-names = "mainmuxclk"; - }; - - chipclk1: chipclk1 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&mainmuxclk>; - clock-div = <1>; - clock-mult = <1>; - clock-output-names = "chipclk1"; - }; - - chipclk1rstiso: chipclk1rstiso { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&mainmuxclk>; - clock-div = <1>; - clock-mult = <1>; - clock-output-names = "chipclk1rstiso"; - }; - - gemtraceclk: gemtraceclk@2310120 { - #clock-cells = <0>; - compatible = "ti,keystone,pll-divider-clock"; - clocks = <&mainmuxclk>; - reg = <0x02310120 4>; - bit-shift = <0>; - bit-mask = <8>; - clock-output-names = "gemtraceclk"; - }; - - chipstmxptclk: chipstmxptclk@2310164 { - #clock-cells = <0>; - compatible = "ti,keystone,pll-divider-clock"; - clocks = <&mainmuxclk>; - reg = <0x02310164 4>; - bit-shift = <0>; - bit-mask = <8>; - clock-output-names = "chipstmxptclk"; - }; - - chipclk12: chipclk12 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&chipclk1>; - clock-div = <2>; - clock-mult = <1>; - clock-output-names = "chipclk12"; - }; - - chipclk13: chipclk13 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&chipclk1>; - clock-div = <3>; - clock-mult = <1>; - clock-output-names = "chipclk13"; - }; - - paclk13: paclk13 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&papllclk>; - clock-div = <3>; - clock-mult = <1>; - clock-output-names = "paclk13"; - }; - - chipclk14: chipclk14 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&chipclk1>; - clock-div = <4>; - clock-mult = <1>; - clock-output-names = "chipclk14"; - }; - - chipclk16: chipclk16 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&chipclk1>; - clock-div = <6>; - clock-mult = <1>; - clock-output-names = "chipclk16"; - }; - - chipclk112: chipclk112 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&chipclk1>; - clock-div = <12>; - clock-mult = <1>; - clock-output-names = "chipclk112"; - }; - - chipclk124: chipclk124 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&chipclk1>; - clock-div = <24>; - clock-mult = <1>; - clock-output-names = "chipclk114"; - }; - - chipclk1rstiso13: chipclk1rstiso13 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&chipclk1rstiso>; - clock-div = <3>; - clock-mult = <1>; - clock-output-names = "chipclk1rstiso13"; - }; - - chipclk1rstiso14: chipclk1rstiso14 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&chipclk1rstiso>; - clock-div = <4>; - clock-mult = <1>; - clock-output-names = "chipclk1rstiso14"; - }; - - chipclk1rstiso16: chipclk1rstiso16 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&chipclk1rstiso>; - clock-div = <6>; - clock-mult = <1>; - clock-output-names = "chipclk1rstiso16"; - }; - - chipclk1rstiso112: chipclk1rstiso112 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&chipclk1rstiso>; - clock-div = <12>; - clock-mult = <1>; - clock-output-names = "chipclk1rstiso112"; - }; - - clkmodrst0: clkmodrst0@2350000 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk16>; - clock-output-names = "modrst0"; - reg = <0x02350000 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; - - - clkusb: clkusb@2350008 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk16>; - clock-output-names = "usb"; - reg = <0x02350008 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; - - clkaemifspi: clkaemifspi@235000c { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk16>; - clock-output-names = "aemif-spi"; - reg = <0x0235000c 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; - - - clkdebugsstrc: clkdebugsstrc@2350014 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "debugss-trc"; - reg = <0x02350014 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <1>; - }; - - clktetbtrc: clktetbtrc@2350018 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "tetb-trc"; - reg = <0x02350018 0xb00>, <0x02350004 0x400>; - reg-names = "control", "domain"; - domain-id = <1>; - }; - - clkpa: clkpa@235001c { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&paclk13>; - clock-output-names = "pa"; - reg = <0x0235001c 0xb00>, <0x02350008 0x400>; - reg-names = "control", "domain"; - domain-id = <2>; - }; - - clkcpgmac: clkcpgmac@2350020 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&clkpa>; - clock-output-names = "cpgmac"; - reg = <0x02350020 0xb00>, <0x02350008 0x400>; - reg-names = "control", "domain"; - domain-id = <2>; - }; - - clksa: clksa@2350024 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&clkpa>; - clock-output-names = "sa"; - reg = <0x02350024 0xb00>, <0x02350008 0x400>; - reg-names = "control", "domain"; - domain-id = <2>; - }; - - clkpcie: clkpcie@2350028 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk12>; - clock-output-names = "pcie"; - reg = <0x02350028 0xb00>, <0x0235000c 0x400>; - reg-names = "control", "domain"; - domain-id = <3>; - }; - - clksr: clksr@2350034 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk1rstiso112>; - clock-output-names = "sr"; - reg = <0x02350034 0xb00>, <0x02350018 0x400>; - reg-names = "control", "domain"; - domain-id = <6>; - }; - - clkgem0: clkgem0@235003c { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk1>; - clock-output-names = "gem0"; - reg = <0x0235003c 0xb00>, <0x02350020 0x400>; - reg-names = "control", "domain"; - domain-id = <8>; - }; - - clkddr30: clkddr30@235005c { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk12>; - clock-output-names = "ddr3-0"; - reg = <0x0235005c 0xb00>, <0x02350040 0x400>; - reg-names = "control", "domain"; - domain-id = <16>; - }; - - clkwdtimer0: clkwdtimer0@2350000 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&clkmodrst0>; - clock-output-names = "timer0"; - reg = <0x02350000 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; - - clkwdtimer1: clkwdtimer1@2350000 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&clkmodrst0>; - clock-output-names = "timer1"; - reg = <0x02350000 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; - - clkwdtimer2: clkwdtimer2@2350000 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&clkmodrst0>; - clock-output-names = "timer2"; - reg = <0x02350000 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; - - clkwdtimer3: clkwdtimer3@2350000 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&clkmodrst0>; - clock-output-names = "timer3"; - reg = <0x02350000 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; - - clktimer15: clktimer15@2350000 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&clkmodrst0>; - clock-output-names = "timer15"; - reg = <0x02350000 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; - - clkuart0: clkuart0@2350000 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&clkmodrst0>; - clock-output-names = "uart0"; - reg = <0x02350000 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; - - clkuart1: clkuart1@2350000 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&clkmodrst0>; - clock-output-names = "uart1"; - reg = <0x02350000 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; - - clkaemif: clkaemif@2350000 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&clkaemifspi>; - clock-output-names = "aemif"; - reg = <0x02350000 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; - - clkusim: clkusim@2350000 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&clkmodrst0>; - clock-output-names = "usim"; - reg = <0x02350000 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; - - clki2c: clki2c@2350000 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&clkmodrst0>; - clock-output-names = "i2c"; - reg = <0x02350000 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; - - clkspi: clkspi@2350000 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&clkaemifspi>; - clock-output-names = "spi"; - reg = <0x02350000 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; - - clkgpio: clkgpio@2350000 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&clkmodrst0>; - clock-output-names = "gpio"; - reg = <0x02350000 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; - - clkkeymgr: clkkeymgr@2350000 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&clkmodrst0>; - clock-output-names = "keymgr"; - reg = <0x02350000 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; - - /* - * Below are set of fixed, input clocks definitions, - * for which real frequencies have to be defined in board files. - * Those clocks can be used as reference clocks for some HW modules - * (as cpts, for example) by configuring corresponding clock muxes. - */ - timi0: timi0 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - clock-output-names = "timi0"; - }; - - timi1: timi1 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - clock-output-names = "timi1"; - }; - - tsrefclk: tsrefclk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - clock-output-names = "tsrefclk"; - }; -}; diff --git a/sys/gnu/dts/arm/keystone-k2e-clocks.dtsi b/sys/gnu/dts/arm/keystone-k2e-clocks.dtsi deleted file mode 100644 index cf30e007fea..00000000000 --- a/sys/gnu/dts/arm/keystone-k2e-clocks.dtsi +++ /dev/null @@ -1,94 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Keystone 2 Edison SoC specific device tree - * - * Copyright (C) 2014-2017 Texas Instruments Incorporated - http://www.ti.com/ - */ - -clocks { - mainpllclk: mainpllclk@2310110 { - #clock-cells = <0>; - compatible = "ti,keystone,main-pll-clock"; - clocks = <&refclksys>; - reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>; - reg-names = "control", "multiplier", "post-divider"; - }; - - papllclk: papllclk@2620358 { - #clock-cells = <0>; - compatible = "ti,keystone,pll-clock"; - clocks = <&refclkpass>; - clock-output-names = "papllclk"; - reg = <0x02620358 4>; - reg-names = "control"; - }; - - ddr3apllclk: ddr3apllclk@2620360 { - #clock-cells = <0>; - compatible = "ti,keystone,pll-clock"; - clocks = <&refclkddr3a>; - clock-output-names = "ddr-3a-pll-clk"; - reg = <0x02620360 4>; - reg-names = "control"; - }; - - clkusb1: clkusb1@2350004 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk16>; - clock-output-names = "usb1"; - reg = <0x02350004 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; - - clkhyperlink0: clkhyperlink0@2350030 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk12>; - clock-output-names = "hyperlink-0"; - reg = <0x02350030 0xb00>, <0x02350014 0x400>; - reg-names = "control", "domain"; - domain-id = <5>; - }; - - clkpcie1: clkpcie1@235006c { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk12>; - clock-output-names = "pcie1"; - reg = <0x0235006c 0xb00>, <0x02350048 0x400>; - reg-names = "control", "domain"; - domain-id = <18>; - }; - - clkxge: clkxge@23500c8 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "xge"; - reg = <0x023500c8 0xb00>, <0x02350074 0x400>; - reg-names = "control", "domain"; - domain-id = <29>; - }; - - /* - * Below are set of fixed, input clocks definitions, - * for which real frequencies have to be defined in board files. - * Those clocks can be used as reference clocks for some HW modules - * (as cpts, for example) by configuring corresponding clock muxes. - */ - tsipclka: tsipclka { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - clock-output-names = "tsipclka"; - }; - - tsipclkb: tsipclkb { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - clock-output-names = "tsipclkb"; - }; -}; diff --git a/sys/gnu/dts/arm/keystone-k2e-evm.dts b/sys/gnu/dts/arm/keystone-k2e-evm.dts deleted file mode 100644 index 66fec5f5d08..00000000000 --- a/sys/gnu/dts/arm/keystone-k2e-evm.dts +++ /dev/null @@ -1,177 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Keystone 2 Edison EVM device tree - * - * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/ - */ -/dts-v1/; - -#include "keystone.dtsi" -#include "keystone-k2e.dtsi" - -/ { - compatible = "ti,k2e-evm", "ti,k2e", "ti,keystone"; - model = "Texas Instruments Keystone 2 Edison EVM"; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - dsp_common_memory: dsp-common-memory@81f800000 { - compatible = "shared-dma-pool"; - reg = <0x00000008 0x1f800000 0x00000000 0x800000>; - reusable; - status = "okay"; - }; - }; -}; - -&soc0 { - - clocks { - refclksys: refclksys { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <100000000>; - clock-output-names = "refclk-sys"; - }; - - refclkpass: refclkpass { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <100000000>; - clock-output-names = "refclk-pass"; - }; - - refclkddr3a: refclkddr3a { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <100000000>; - clock-output-names = "refclk-ddr3a"; - }; - }; -}; - -&usb_phy { - status = "okay"; -}; - -&keystone_usb0 { - status = "okay"; -}; - -&usb0 { - dr_mode = "host"; -}; - -&usb1_phy { - status = "okay"; -}; - -&keystone_usb1 { - status = "okay"; -}; - -&usb1 { - dr_mode = "peripheral"; -}; - -&i2c0 { - dtt@50 { - compatible = "atmel,24c1024"; - reg = <0x50>; - }; -}; - -&aemif { - cs0 { - #address-cells = <2>; - #size-cells = <1>; - clock-ranges; - ranges; - - ti,cs-chipselect = <0>; - /* all timings in nanoseconds */ - ti,cs-min-turnaround-ns = <12>; - ti,cs-read-hold-ns = <6>; - ti,cs-read-strobe-ns = <23>; - ti,cs-read-setup-ns = <9>; - ti,cs-write-hold-ns = <8>; - ti,cs-write-strobe-ns = <23>; - ti,cs-write-setup-ns = <8>; - - nand@0,0 { - compatible = "ti,keystone-nand","ti,davinci-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0 0 0x4000000 - 1 0 0x0000100>; - - ti,davinci-chipselect = <0>; - ti,davinci-mask-ale = <0x2000>; - ti,davinci-mask-cle = <0x4000>; - ti,davinci-mask-chipsel = <0>; - nand-ecc-mode = "hw"; - ti,davinci-ecc-bits = <4>; - nand-on-flash-bbt; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x100000>; - read-only; - }; - - partition@100000 { - label = "params"; - reg = <0x100000 0x80000>; - read-only; - }; - - partition@180000 { - label = "ubifs"; - reg = <0x180000 0x1FE80000>; - }; - }; - }; -}; - -&spi0 { - nor_flash: n25q128a11@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "Micron,n25q128a11"; - spi-max-frequency = <54000000>; - m25p,fast-read; - reg = <0>; - - partition@0 { - label = "u-boot-spl"; - reg = <0x0 0x80000>; - read-only; - }; - - partition@1 { - label = "misc"; - reg = <0x80000 0xf80000>; - }; - }; -}; - -&mdio { - status = "ok"; - ethphy0: ethernet-phy@0 { - compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22"; - reg = <0>; - }; - - ethphy1: ethernet-phy@1 { - compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; -}; - -&dsp0 { - memory-region = <&dsp_common_memory>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/keystone-k2e-netcp.dtsi b/sys/gnu/dts/arm/keystone-k2e-netcp.dtsi deleted file mode 100644 index ad15e77874b..00000000000 --- a/sys/gnu/dts/arm/keystone-k2e-netcp.dtsi +++ /dev/null @@ -1,264 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for Keystone 2 Edison Netcp driver - * - * Copyright (C) 2015-2017 Texas Instruments Incorporated - http://www.ti.com/ - */ - -qmss: qmss@2a40000 { - compatible = "ti,keystone-navigator-qmss"; - dma-coherent; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&chipclk13>; - ranges; - queue-range = <0 0x2000>; - linkram0 = <0x100000 0x4000>; - linkram1 = <0 0x10000>; - - qmgrs { - #address-cells = <1>; - #size-cells = <1>; - ranges; - qmgr0 { - managed-queues = <0 0x2000>; - reg = <0x2a40000 0x20000>, - <0x2a06000 0x400>, - <0x2a02000 0x1000>, - <0x2a03000 0x1000>, - <0x23a80000 0x20000>, - <0x2a80000 0x20000>; - reg-names = "peek", "status", "config", - "region", "push", "pop"; - }; - }; - queue-pools { - qpend { - qpend-0 { - qrange = <658 8>; - interrupts =<0 40 0xf04 0 41 0xf04 0 42 0xf04 - 0 43 0xf04 0 44 0xf04 0 45 0xf04 - 0 46 0xf04 0 47 0xf04>; - }; - qpend-1 { - qrange = <528 16>; - interrupts = <0 48 0xf04 0 49 0xf04 0 50 0xf04 - 0 51 0xf04 0 52 0xf04 0 53 0xf04 - 0 54 0xf04 0 55 0xf04 0 56 0xf04 - 0 57 0xf04 0 58 0xf04 0 59 0xf04 - 0 60 0xf04 0 61 0xf04 0 62 0xf04 - 0 63 0xf04>; - qalloc-by-id; - }; - qpend-2 { - qrange = <544 16>; - interrupts = <0 64 0xf04 0 65 0xf04 0 66 0xf04 - 0 59 0xf04 0 68 0xf04 0 69 0xf04 - 0 70 0xf04 0 71 0xf04 0 72 0xf04 - 0 73 0xf04 0 74 0xf04 0 75 0xf04 - 0 76 0xf04 0 77 0xf04 0 78 0xf04 - 0 79 0xf04>; - }; - }; - general-purpose { - gp-0 { - qrange = <4000 64>; - }; - netcp-tx { - qrange = <896 128>; - qalloc-by-id; - }; - }; - accumulator { - acc-low-0 { - qrange = <480 32>; - accumulator = <0 47 16 2 50>; - interrupts = <0 226 0xf01>; - multi-queue; - qalloc-by-id; - }; - }; - }; - - descriptor-regions { - #address-cells = <1>; - #size-cells = <1>; - ranges; - region-12 { - id = <12>; - region-spec = <8192 128>; /* num_desc desc_size */ - link-index = <0x4000>; - }; - }; - - pdsps { - #address-cells = <1>; - #size-cells = <1>; - ranges; - pdsp0@0x2a10000 { - reg = <0x2a10000 0x1000 /*iram */ - 0x2a0f000 0x100 /*reg*/ - 0x2a0c000 0x3c8 /*intd */ - 0x2a20000 0x4000>; /*cmd*/ - id = <0>; - }; - }; -}; /* qmss */ - -knav_dmas: knav_dmas@0 { - compatible = "ti,keystone-navigator-dma"; - clocks = <&papllclk>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - ti,navigator-cloud-address = <0x23a80000 0x23a90000 - 0x23a80000 0x23a90000>; - - dma_gbe: dma_gbe@0 { - reg = <0x24186000 0x100>, - <0x24187000 0x2a0>, - <0x24188000 0xb60>, - <0x24186100 0x80>, - <0x24189000 0x1000>; - reg-names = "global", "txchan", "rxchan", - "txsched", "rxflow"; - }; -}; - -netcp: netcp@24000000 { - reg = <0x2620110 0x8>; - reg-names = "efuse"; - compatible = "ti,netcp-1.0"; - #address-cells = <1>; - #size-cells = <1>; - - /* NetCP address range */ - ranges = <0 0x24000000 0x1000000>; - - clocks = <&clkpa>, <&clkcpgmac>; - clock-names = "pa_clk", "ethss_clk"; - dma-coherent; - - ti,navigator-dmas = <&dma_gbe 0>, - <&dma_gbe 8>, - <&dma_gbe 0>; - ti,navigator-dma-names = "netrx0", "netrx1", "nettx"; - - netcp-devices { - #address-cells = <1>; - #size-cells = <1>; - ranges; - gbe@200000 { /* ETHSS */ - label = "netcp-gbe"; - compatible = "ti,netcp-gbe-9"; - reg = <0x200000 0x900>, <0x220000 0x20000>; - /* enable-ale; */ - tx-queue = <896>; - tx-channel = "nettx"; - - cpts { - clocks = <&cpts_refclk_mux>; - clock-names = "cpts"; - - cpts_refclk_mux: cpts-refclk-mux { - #clock-cells = <0>; - clocks = <&chipclk12>, <&chipclk13>, - <&timi0>, <&timi1>, - <&tsipclka>, <&tsrefclk>, - <&tsipclkb>; - ti,mux-tbl = <0x0>, <0x1>, <0x2>, - <0x3>, <0x4>, <0x8>, <0xC>; - assigned-clocks = <&cpts_refclk_mux>; - assigned-clock-parents = <&chipclk12>; - }; - }; - - interfaces { - gbe0: interface-0 { - slave-port = <0>; - link-interface = <1>; - phy-handle = <ðphy0>; - }; - gbe1: interface-1 { - slave-port = <1>; - link-interface = <1>; - phy-handle = <ðphy1>; - }; - }; - - secondary-slave-ports { - port-2 { - slave-port = <2>; - link-interface = <2>; - }; - port-3 { - slave-port = <3>; - link-interface = <2>; - }; - port-4 { - slave-port = <4>; - link-interface = <2>; - }; - port-5 { - slave-port = <5>; - link-interface = <2>; - }; - port-6 { - slave-port = <6>; - link-interface = <2>; - }; - port-7 { - slave-port = <7>; - link-interface = <2>; - }; - }; - }; - }; - - netcp-interfaces { - interface-0 { - rx-channel = "netrx0"; - rx-pool = <1024 12>; - tx-pool = <1024 12>; - rx-queue-depth = <128 128 0 0>; - rx-buffer-size = <1518 4096 0 0>; - rx-queue = <528>; - tx-completion-queue = <530>; - efuse-mac = <1>; - netcp-gbe = <&gbe0>; - - }; - interface-1 { - rx-channel = "netrx1"; - rx-pool = <1024 12>; - tx-pool = <1024 12>; - rx-queue-depth = <128 128 0 0>; - rx-buffer-size = <1518 4096 0 0>; - rx-queue = <529>; - tx-completion-queue = <531>; - efuse-mac = <0>; - local-mac-address = [02 18 31 7e 3e 00]; - netcp-gbe = <&gbe1>; - }; - }; -}; - -sa_subsys: subsys@24080000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0 0x24080000 0x40000>; - - sa_config: subsys@0 { - compatible = "syscon"; - reg = <0x0 0x100>; - }; - - rng@24000 { - compatible = "ti,keystone-rng"; - reg = <0x24000 0x1000>; - ti,syscon-sa-cfg = <&sa_config>; - clocks = <&clksa>; - clock-names = "fck"; - }; -}; diff --git a/sys/gnu/dts/arm/keystone-k2e.dtsi b/sys/gnu/dts/arm/keystone-k2e.dtsi deleted file mode 100644 index 085e7326ea8..00000000000 --- a/sys/gnu/dts/arm/keystone-k2e.dtsi +++ /dev/null @@ -1,198 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Keystone 2 Edison soc device tree - * - * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/ - */ - -#include - -/ { - compatible = "ti,k2e", "ti,keystone"; - model = "Texas Instruments Keystone 2 Edison SoC"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - interrupt-parent = <&gic>; - - cpu@0 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <0>; - }; - - cpu@1 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <1>; - }; - - cpu@2 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <2>; - }; - - cpu@3 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <3>; - }; - }; - - aliases { - rproc0 = &dsp0; - }; -}; - -&soc0 { - /include/ "keystone-k2e-clocks.dtsi" - - usb: usb@2680000 { - interrupts = ; - dwc3@2690000 { - interrupts = ; - }; - }; - - usb1_phy: usb_phy@2620750 { - compatible = "ti,keystone-usbphy"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x2620750 24>; - status = "disabled"; - }; - - keystone_usb1: usb@25000000 { - compatible = "ti,keystone-dwc3"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x25000000 0x10000>; - clocks = <&clkusb1>; - clock-names = "usb"; - interrupts = ; - ranges; - dma-coherent; - dma-ranges; - status = "disabled"; - - usb1: dwc3@25010000 { - compatible = "synopsys,dwc3"; - reg = <0x25010000 0x70000>; - interrupts = ; - usb-phy = <&usb1_phy>, <&usb1_phy>; - }; - }; - - msm_ram: msmram@c000000 { - compatible = "mmio-sram"; - reg = <0x0c000000 0x200000>; - ranges = <0x0 0x0c000000 0x200000>; - #address-cells = <1>; - #size-cells = <1>; - - sram-bm@1f0000 { - reg = <0x001f0000 0x8000>; - }; - }; - - psc: power-sleep-controller@2350000 { - pscrst: reset-controller { - compatible = "ti,k2e-pscrst", "ti,syscon-reset"; - #reset-cells = <1>; - - ti,reset-bits = < - 0xa3c 8 0xa3c 8 0x83c 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 0: dsp0 */ - >; - }; - }; - - devctrl: device-state-control@2620000 { - dspgpio0: keystone_dsp_gpio@240 { - compatible = "ti,keystone-dsp-gpio"; - reg = <0x240 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio,syscon-dev = <&devctrl 0x240>; - }; - }; - - dsp0: dsp@10800000 { - compatible = "ti,k2e-dsp"; - reg = <0x10800000 0x00080000>, - <0x10e00000 0x00008000>, - <0x10f00000 0x00008000>; - reg-names = "l2sram", "l1pram", "l1dram"; - clocks = <&clkgem0>; - ti,syscon-dev = <&devctrl 0x844>; - resets = <&pscrst 0>; - interrupt-parent = <&kirq0>; - interrupts = <0 8>; - interrupt-names = "vring", "exception"; - kick-gpios = <&dspgpio0 27 0>; - status = "disabled"; - }; - - pcie1: pcie@21020000 { - compatible = "ti,keystone-pcie","snps,dw-pcie"; - clocks = <&clkpcie1>; - clock-names = "pcie"; - #address-cells = <3>; - #size-cells = <2>; - reg = <0x21021000 0x2000>, <0x21020000 0x1000>, <0x02620128 4>; - ranges = <0x82000000 0 0x60000000 0x60000000 - 0 0x10000000>; - - status = "disabled"; - device_type = "pci"; - num-lanes = <2>; - bus-range = <0x00 0xff>; - - /* error interrupt */ - interrupts = ; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie_intc1 0>, /* INT A */ - <0 0 0 2 &pcie_intc1 1>, /* INT B */ - <0 0 0 3 &pcie_intc1 2>, /* INT C */ - <0 0 0 4 &pcie_intc1 3>; /* INT D */ - - pcie_msi_intc1: msi-interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - interrupt-parent = <&gic>; - interrupts = , - , - , - , - , - , - , - ; - }; - - pcie_intc1: legacy-interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - interrupt-parent = <&gic>; - interrupts = , - , - , - ; - }; - }; - - mdio: mdio@24200f00 { - compatible = "ti,keystone_mdio", "ti,davinci_mdio"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x24200f00 0x100>; - status = "disabled"; - clocks = <&clkcpgmac>; - clock-names = "fck"; - bus_freq = <2500000>; - }; - /include/ "keystone-k2e-netcp.dtsi" -}; diff --git a/sys/gnu/dts/arm/keystone-k2g-evm.dts b/sys/gnu/dts/arm/keystone-k2g-evm.dts deleted file mode 100644 index b7f10bf9457..00000000000 --- a/sys/gnu/dts/arm/keystone-k2g-evm.dts +++ /dev/null @@ -1,359 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for K2G EVM - * - * Copyright (C) 2016-2017 Texas Instruments Incorporated - http://www.ti.com/ - */ -/dts-v1/; - -#include "keystone-k2g.dtsi" - -/ { - compatible = "ti,k2g-evm", "ti,k2g", "ti,keystone"; - model = "Texas Instruments K2G General Purpose EVM"; - - memory@800000000 { - device_type = "memory"; - reg = <0x00000008 0x00000000 0x00000000 0x80000000>; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - dsp_common_memory: dsp-common-memory@81f800000 { - compatible = "shared-dma-pool"; - reg = <0x00000008 0x1f800000 0x00000000 0x800000>; - reusable; - status = "okay"; - }; - }; - - vcc3v3_dcin_reg: fixedregulator-vcc3v3-dcin { - compatible = "regulator-fixed"; - regulator-name = "mmc0_fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vcc1v8_ldo1_reg: fixedregulator-vcc1v8-ldo1 { - compatible = "regulator-fixed"; - regulator-name = "ldo1"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; -}; - -&k2g_pinctrl { - uart0_pins: pinmux_uart0_pins { - pinctrl-single,pins = < - K2G_CORE_IOPAD(0x11cc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* uart0_rxd.uart0_rxd */ - K2G_CORE_IOPAD(0x11d0) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ - >; - }; - - mmc0_pins: pinmux_mmc0_pins { - pinctrl-single,pins = < - K2G_CORE_IOPAD(0x1300) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_dat3.mmc0_dat3 */ - K2G_CORE_IOPAD(0x1304) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_dat2.mmc0_dat2 */ - K2G_CORE_IOPAD(0x1308) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_dat1.mmc0_dat1 */ - K2G_CORE_IOPAD(0x130c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_dat0.mmc0_dat0 */ - K2G_CORE_IOPAD(0x1310) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_clk.mmc0_clk */ - K2G_CORE_IOPAD(0x1314) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_cmd.mmc0_cmd */ - K2G_CORE_IOPAD(0x12ec) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* mmc0_sdcd.gpio1_12 */ - >; - }; - - mmc1_pins: pinmux_mmc1_pins { - pinctrl-single,pins = < - K2G_CORE_IOPAD(0x10ec) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat7.mmc1_dat7 */ - K2G_CORE_IOPAD(0x10f0) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat6.mmc1_dat6 */ - K2G_CORE_IOPAD(0x10f4) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat5.mmc1_dat5 */ - K2G_CORE_IOPAD(0x10f8) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat4.mmc1_dat4 */ - K2G_CORE_IOPAD(0x10fc) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat3.mmc1_dat3 */ - K2G_CORE_IOPAD(0x1100) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat2.mmc1_dat2 */ - K2G_CORE_IOPAD(0x1104) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat1.mmc1_dat1 */ - K2G_CORE_IOPAD(0x1108) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat0.mmc1_dat0 */ - K2G_CORE_IOPAD(0x110c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_clk.mmc1_clk */ - K2G_CORE_IOPAD(0x1110) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_cmd.mmc1_cmd */ - >; - }; - - i2c0_pins: pinmux_i2c0_pins { - pinctrl-single,pins = < - K2G_CORE_IOPAD(0x137c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ - K2G_CORE_IOPAD(0x1380) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ - >; - }; - - ecap0_pins: ecap0_pins { - pinctrl-single,pins = < - K2G_CORE_IOPAD(0x1374) (BUFFER_CLASS_B | MUX_MODE4) /* pr1_mdio_data.ecap0_in_apwm0_out */ - >; - }; - - spi1_pins: pinmux_spi1_pins { - pinctrl-single,pins = < - K2G_CORE_IOPAD(0x11a4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* spi1_scs0.spi1_scs0 */ - K2G_CORE_IOPAD(0x11ac) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* spi1_clk.spi1_clk */ - K2G_CORE_IOPAD(0x11b0) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* spi1_miso.spi1_miso */ - K2G_CORE_IOPAD(0x11b4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* spi1_mosi.spi1_mosi */ - >; - }; - - qspi_pins: pinmux_qspi_pins { - pinctrl-single,pins = < - K2G_CORE_IOPAD(0x1204) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_clk.qspi_clk */ - K2G_CORE_IOPAD(0x1208) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_rclk.qspi_rclk */ - K2G_CORE_IOPAD(0x120c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d0.qspi_d0 */ - K2G_CORE_IOPAD(0x1210) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d1.qspi_d1 */ - K2G_CORE_IOPAD(0x1214) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d2.qspi_d2 */ - K2G_CORE_IOPAD(0x1218) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d3.qspi_d3 */ - K2G_CORE_IOPAD(0x121c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_csn0.qspi_csn0 */ - >; - }; - - uart2_pins: pinmux_uart2_pins { - pinctrl-single,pins = < - K2G_CORE_IOPAD(0x11ec) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* uart2_rxd.uart2_rxd */ - K2G_CORE_IOPAD(0x11f0) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0) /* uart2_txd.uart2_txd */ - >; - }; - - dcan0_pins: pinmux_dcan0_pins { - pinctrl-single,pins = < - K2G_CORE_IOPAD(0x11fc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dcan0tx.dcan0tx */ - K2G_CORE_IOPAD(0x1200) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0) /* dcan0rx.dcan0rx */ - >; - }; - - dcan1_pins: pinmux_dcan1_pins { - pinctrl-single,pins = < - K2G_CORE_IOPAD(0x1224) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE1) /* qspicsn2.dcan1tx */ - K2G_CORE_IOPAD(0x1228) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE1) /* qspicsn3.dcan1rx */ - >; - }; - - emac_pins: pinmux_emac_pins { - pinctrl-single,pins = < - K2G_CORE_IOPAD(0x113C) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD1.RGMII_RXD1 */ - K2G_CORE_IOPAD(0x1138) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD2.RGMII_RXD2 */ - K2G_CORE_IOPAD(0x1134) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD3.RGMII_RXD3 */ - K2G_CORE_IOPAD(0x1140) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD0.RGMII_RXD0 */ - K2G_CORE_IOPAD(0x1178) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD0.RGMII_TXD0 */ - K2G_CORE_IOPAD(0x1174) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD1.RGMII_TXD1 */ - K2G_CORE_IOPAD(0x1170) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD2.RGMII_TXD2 */ - K2G_CORE_IOPAD(0x116C) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD3.RGMII_TXD3 */ - K2G_CORE_IOPAD(0x1154) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXCLK.RGMII_TXC */ - K2G_CORE_IOPAD(0x117C) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXEN.RGMII_TXCTL */ - K2G_CORE_IOPAD(0x1120) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXCLK.RGMII_RXC */ - K2G_CORE_IOPAD(0x1144) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXDV.RGMII_RXCTL */ - >; - }; - - mdio_pins: pinmux_mdio_pins { - pinctrl-single,pins = < - K2G_CORE_IOPAD(0x118C) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* MDIO_CLK.MDIO_CLK */ - K2G_CORE_IOPAD(0x1188) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* MDIO_DATA.MDIO_DATA */ - >; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; - vmmc-supply = <&vcc3v3_dcin_reg>; - vqmmc-supply = <&vcc3v3_dcin_reg>; - cd-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - vmmc-supply = <&vcc3v3_dcin_reg>; /* VCC3V3_EMMC is connected to VCC3V3_DCIN */ - vqmmc-supply = <&vcc1v8_ldo1_reg>; - ti,non-removable; - status = "okay"; -}; - -&dsp0 { - memory-region = <&dsp_common_memory>; - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - status = "okay"; - - eeprom@50 { - compatible = "atmel,24c1024"; - reg = <0x50>; - }; -}; - -&keystone_usb0 { - status = "okay"; -}; - -&usb0_phy { - status = "okay"; -}; - -&usb0 { - dr_mode = "host"; - status = "okay"; -}; - -&keystone_usb1 { - status = "okay"; -}; - -&usb1_phy { - status = "okay"; -}; - -&usb1 { - dr_mode = "peripheral"; - status = "okay"; -}; - -&ecap0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&ecap0_pins>; -}; - -&spi1 { - pinctrl-names = "default"; - pinctrl-0 = <&spi1_pins>; - status = "okay"; - - spi_nor: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - spi-max-frequency = <5000000>; - m25p,fast-read; - reg = <0>; - - partition@0 { - label = "u-boot-spl"; - reg = <0x0 0x100000>; - read-only; - }; - - partition@1 { - label = "misc"; - reg = <0x100000 0xf00000>; - }; - }; -}; - -&qspi { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&qspi_pins>; - cdns,rclk-en; - - flash0: m25p80@0 { - compatible = "s25fl512s", "jedec,spi-nor"; - reg = <0>; - spi-tx-bus-width = <1>; - spi-rx-bus-width = <4>; - spi-max-frequency = <96000000>; - #address-cells = <1>; - #size-cells = <1>; - cdns,read-delay = <5>; - cdns,tshsl-ns = <500>; - cdns,tsd2d-ns = <500>; - cdns,tchsh-ns = <119>; - cdns,tslch-ns = <119>; - - partition@0 { - label = "QSPI.u-boot-spl-os"; - reg = <0x00000000 0x00100000>; - }; - partition@1 { - label = "QSPI.u-boot-env"; - reg = <0x00100000 0x00040000>; - }; - partition@2 { - label = "QSPI.skern"; - reg = <0x00140000 0x0040000>; - }; - partition@3 { - label = "QSPI.pmmc-firmware"; - reg = <0x00180000 0x0040000>; - }; - partition@4 { - label = "QSPI.kernel"; - reg = <0x001C0000 0x0800000>; - }; - partition@5 { - label = "QSPI.file-system"; - reg = <0x009C0000 0x3640000>; - }; - }; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; - status = "okay"; -}; - -&dcan0 { - pinctrl-names = "default"; - pinctrl-0 = <&dcan0_pins>; - status = "okay"; -}; - -&dcan1 { - pinctrl-names = "default"; - pinctrl-0 = <&dcan1_pins>; - status = "okay"; -}; - -&qmss { - status = "okay"; -}; - -&knav_dmas { - status = "okay"; -}; - -&mdio { - pinctrl-names = "default"; - pinctrl-0 = <&mdio_pins>; - status = "okay"; - ethphy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -&gbe0 { - phy-handle = <ðphy0>; - phy-mode = "rgmii-id"; - status = "okay"; -}; - -&netcp { - pinctrl-names = "default"; - pinctrl-0 = <&emac_pins>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/keystone-k2g-ice.dts b/sys/gnu/dts/arm/keystone-k2g-ice.dts deleted file mode 100644 index 2a2d38cf0ff..00000000000 --- a/sys/gnu/dts/arm/keystone-k2g-ice.dts +++ /dev/null @@ -1,447 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for K2G Industrial Communication Engine EVM - * - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ - */ -/dts-v1/; - -#include "keystone-k2g.dtsi" -#include - -/ { - compatible = "ti,k2g-ice", "ti,k2g", "ti,keystone"; - model = "Texas Instruments K2G Industrial Communication EVM"; - - memory@800000000 { - device_type = "memory"; - reg = <0x00000008 0x00000000 0x00000000 0x20000000>; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - dsp_common_memory: dsp-common-memory@81f800000 { - compatible = "shared-dma-pool"; - reg = <0x00000008 0x1f800000 0x00000000 0x800000>; - reusable; - status = "okay"; - }; - }; - - vmain: fixedregulator-vmain { - compatible = "regulator-fixed"; - regulator-name = "vmain_fixed"; - regulator-min-microvolt = <24000000>; - regulator-max-microvolt = <24000000>; - regulator-always-on; - }; - - v5_0: fixedregulator-v5_0 { - /* TPS54531 */ - compatible = "regulator-fixed"; - regulator-name = "v5_0_fixed"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vmain>; - regulator-always-on; - }; - - vdd_3v3: fixedregulator-vdd_3v3 { - /* TLV62084 */ - compatible = "regulator-fixed"; - regulator-name = "vdd_3v3_fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&v5_0>; - regulator-always-on; - }; - - vdd_1v8: fixedregulator-vdd_1v8 { - /* TLV62084 */ - compatible = "regulator-fixed"; - regulator-name = "vdd_1v8_fixed"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&v5_0>; - regulator-always-on; - }; - - vdds_ddr: fixedregulator-vdds_ddr { - /* TLV62080 */ - compatible = "regulator-fixed"; - regulator-name = "vdds_ddr_fixed"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - vin-supply = <&v5_0>; - regulator-always-on; - }; - - vref_ddr: fixedregulator-vref_ddr { - /* LP2996A */ - compatible = "regulator-fixed"; - regulator-name = "vref_ddr_fixed"; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <675000>; - vin-supply = <&vdd_3v3>; - regulator-always-on; - }; - - vtt_ddr: fixedregulator-vtt_ddr { - /* LP2996A */ - compatible = "regulator-fixed"; - regulator-name = "vtt_ddr_fixed"; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <675000>; - vin-supply = <&vdd_3v3>; - regulator-always-on; - }; - - vdd_0v9: fixedregulator-vdd_0v9 { - /* TPS62180 */ - compatible = "regulator-fixed"; - regulator-name = "vdd_0v9_fixed"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - vin-supply = <&v5_0>; - regulator-always-on; - }; - - vddb: fixedregulator-vddb { - /* TPS22945 */ - compatible = "regulator-fixed"; - regulator-name = "vddb_fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&gpio1 53 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - gpio-decoder { - compatible = "gpio-decoder"; - gpios = <&pca9536 3 GPIO_ACTIVE_HIGH>, - <&pca9536 2 GPIO_ACTIVE_HIGH>, - <&pca9536 1 GPIO_ACTIVE_HIGH>, - <&pca9536 0 GPIO_ACTIVE_HIGH>; - linux,axis = <0>; /* ABS_X */ - decoder-max-value = <9>; - }; - - leds1 { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&user_leds>; - - led0 { - label = "status0:red:cpu0"; - gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>; - default-state = "off"; - linux,default-trigger = "cpu0"; - }; - - led1 { - label = "status0:green:usr"; - gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led2 { - label = "status0:yellow:usr"; - gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led3 { - label = "status1:red:mmc0"; - gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; - default-state = "off"; - linux,default-trigger = "mmc0"; - }; - - led4 { - label = "status1:green:usr"; - gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led5 { - label = "status1:yellow:usr"; - gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led6 { - label = "status2:red:usr"; - gpios = <&gpio0 44 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led7 { - label = "status2:green:usr"; - gpios = <&gpio0 43 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led8 { - label = "status2:yellow:usr"; - gpios = <&gpio0 42 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led9 { - label = "status3:red:usr"; - gpios = <&gpio0 41 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led10 { - label = "status3:green:usr"; - gpios = <&gpio0 101 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led11 { - label = "status3:yellow:usr"; - gpios = <&gpio0 102 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led12 { - label = "status4:green:heartbeat"; - gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; -}; - -&k2g_pinctrl { - uart0_pins: pinmux_uart0_pins { - pinctrl-single,pins = < - K2G_CORE_IOPAD(0x11cc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* uart0_rxd.uart0_rxd */ - K2G_CORE_IOPAD(0x11d0) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ - >; - }; - - qspi_pins: pinmux_qspi_pins { - pinctrl-single,pins = < - K2G_CORE_IOPAD(0x1204) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_clk.qspi_clk */ - K2G_CORE_IOPAD(0x1208) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_rclk.qspi_rclk */ - K2G_CORE_IOPAD(0x120c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d0.qspi_d0 */ - K2G_CORE_IOPAD(0x1210) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d1.qspi_d1 */ - K2G_CORE_IOPAD(0x1214) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d2.qspi_d2 */ - K2G_CORE_IOPAD(0x1218) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d3.qspi_d3 */ - K2G_CORE_IOPAD(0x121c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_csn0.qspi_csn0 */ - >; - }; - - mmc1_pins: pinmux_mmc1_pins { - pinctrl-single,pins = < - K2G_CORE_IOPAD(0x10FC) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat3.mmc1_dat3 */ - K2G_CORE_IOPAD(0x1100) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat2.mmc1_dat2 */ - K2G_CORE_IOPAD(0x1104) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat1.mmc1_dat1 */ - K2G_CORE_IOPAD(0x1108) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat0.mmc1_dat0 */ - K2G_CORE_IOPAD(0x110C) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_clk.mmc1_clk */ - K2G_CORE_IOPAD(0x1110) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_cmd.mmc1_cmd */ - K2G_CORE_IOPAD(0x1114) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* mmc1_sdcd.gpio0_69 */ - K2G_CORE_IOPAD(0x1118) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_sdwp.mmc1_sdwp */ - K2G_CORE_IOPAD(0x111C) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_pow.mmc1_pow */ - >; - }; - - i2c0_pins: pinmux_i2c0_pins { - pinctrl-single,pins = < - K2G_CORE_IOPAD(0x137c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ - K2G_CORE_IOPAD(0x1380) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ - >; - }; - - i2c1_pins: pinmux_i2c1_pins { - pinctrl-single,pins = < - K2G_CORE_IOPAD(0x1384) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c1_scl.i2c1_scl */ - K2G_CORE_IOPAD(0x1388) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c1_sda.i2c1_sda */ - >; - }; - - user_leds: pinmux_user_leds { - pinctrl-single,pins = < - K2G_CORE_IOPAD(0x102c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* gpmc_ad11.gpio0_11 */ - K2G_CORE_IOPAD(0x1030) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* gpmc_ad12.gpio0_12 */ - K2G_CORE_IOPAD(0x1034) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* gpmc_ad13.gpio0_13 */ - K2G_CORE_IOPAD(0x1038) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* gpmc_ad14.gpio0_14 */ - K2G_CORE_IOPAD(0x103c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* gpmc_ad15.gpio0_15 */ - K2G_CORE_IOPAD(0x1040) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* gpmc_clk.gpio0_16 */ - K2G_CORE_IOPAD(0x104c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* gpmc_wen.gpio0_19 */ - K2G_CORE_IOPAD(0x10b0) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* dss_data9.gpio0_44 */ - K2G_CORE_IOPAD(0x10ac) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* dss_data10.gpio0_43 */ - K2G_CORE_IOPAD(0x10a8) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* dss_data11.gpio0_42 */ - K2G_CORE_IOPAD(0x10a4) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* dss_data12.gpio0_41 */ - K2G_CORE_IOPAD(0x11b8) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* spi2_scsn0.gpio0_101 */ - K2G_CORE_IOPAD(0x11bc) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* spi2_scsn1.gpio0_102 */ - >; - }; - - emac_pins: pinmux_emac_pins { - pinctrl-single,pins = < - K2G_CORE_IOPAD(0x113C) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD1.RGMII_RXD1 */ - K2G_CORE_IOPAD(0x1138) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD2.RGMII_RXD2 */ - K2G_CORE_IOPAD(0x1134) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD3.RGMII_RXD3 */ - K2G_CORE_IOPAD(0x1140) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD0.RGMII_RXD0 */ - K2G_CORE_IOPAD(0x1178) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD0.RGMII_TXD0 */ - K2G_CORE_IOPAD(0x1174) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD1.RGMII_TXD1 */ - K2G_CORE_IOPAD(0x1170) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD2.RGMII_TXD2 */ - K2G_CORE_IOPAD(0x116C) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD3.RGMII_TXD3 */ - K2G_CORE_IOPAD(0x1154) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXCLK.RGMII_TXC */ - K2G_CORE_IOPAD(0x117C) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXEN.RGMII_TXCTL */ - K2G_CORE_IOPAD(0x1120) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXCLK.RGMII_RXC */ - K2G_CORE_IOPAD(0x1144) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXDV.RGMII_RXCTL */ - >; - }; - - mdio_pins: pinmux_mdio_pins { - pinctrl-single,pins = < - K2G_CORE_IOPAD(0x118C) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* MDIO_CLK.MDIO_CLK */ - K2G_CORE_IOPAD(0x1188) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* MDIO_DATA.MDIO_DATA */ - >; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - status = "okay"; -}; - -&dsp0 { - memory-region = <&dsp_common_memory>; - status = "okay"; -}; - -&qspi { - pinctrl-names = "default"; - pinctrl-0 = <&qspi_pins>; - cdns,rclk-en; - status = "okay"; - - flash0: m25p80@0 { - compatible = "s25fl256s1", "jedec,spi-nor"; - reg = <0>; - spi-tx-bus-width = <1>; - spi-rx-bus-width = <4>; - spi-max-frequency = <96000000>; - #address-cells = <1>; - #size-cells = <1>; - cdns,read-delay = <5>; - cdns,tshsl-ns = <500>; - cdns,tsd2d-ns = <500>; - cdns,tchsh-ns = <119>; - cdns,tslch-ns = <119>; - - partition@0 { - label = "QSPI.u-boot"; - reg = <0x00000000 0x00100000>; - }; - partition@1 { - label = "QSPI.u-boot-env"; - reg = <0x00100000 0x00040000>; - }; - partition@2 { - label = "QSPI.skern"; - reg = <0x00140000 0x0040000>; - }; - partition@3 { - label = "QSPI.pmmc-firmware"; - reg = <0x00180000 0x0040000>; - }; - partition@4 { - label = "QSPI.kernel"; - reg = <0x001c0000 0x0800000>; - }; - partition@5 { - label = "QSPI.u-boot-spl-os"; - reg = <0x009c0000 0x0040000>; - }; - partition@6 { - label = "QSPI.file-system"; - reg = <0x00a00000 0x1600000>; - }; - }; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - vmmc-supply = <&vdd_3v3>; - cd-gpios = <&gpio0 69 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - status = "okay"; - - eeprom@50 { - compatible = "atmel,24c256"; - reg = <0x50>; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - status = "okay"; - clock-frequency = <400000>; - - pca9536: gpio@41 { - compatible = "ti,pca9536"; - reg = <0x41>; - gpio-controller; - #gpio-cells = <2>; - vcc-supply = <&vdd_3v3>; - }; -}; - -&qmss { - status = "okay"; -}; - -&knav_dmas { - status = "okay"; -}; - -&netcp { - pinctrl-names = "default"; - pinctrl-0 = <&emac_pins>; - status = "okay"; -}; - -&mdio { - pinctrl-names = "default"; - pinctrl-0 = <&mdio_pins>; - status = "okay"; - ethphy0: ethernet-phy@0 { - reg = <0>; - ti,rx-internal-delay = ; - ti,tx-internal-delay = ; - ti,fifo-depth = ; - ti,min-output-impedance; - ti,dp83867-rxctrl-strap-quirk; - }; -}; - -&gbe0 { - phy-handle = <ðphy0>; - phy-mode = "rgmii-id"; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/keystone-k2g-netcp.dtsi b/sys/gnu/dts/arm/keystone-k2g-netcp.dtsi deleted file mode 100644 index d0e6a9a4340..00000000000 --- a/sys/gnu/dts/arm/keystone-k2g-netcp.dtsi +++ /dev/null @@ -1,147 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for K2G Netcp driver - * - * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ - */ - -qmss: qmss@4020000 { - compatible = "ti,66ak2g-navss-qm"; - dma-coherent; - #address-cells = <1>; - #size-cells = <1>; - power-domains = <&k2g_pds 0x0018>; - clocks = <&k2g_clks 0x0018 0>; - clock-names = "nss_vclk"; - ranges; - queue-range = <0 0x80>; - linkram0 = <0x4020000 0x7ff>; - status = "disabled"; - - qmgrs { - #address-cells = <1>; - #size-cells = <1>; - ranges; - qmgr0 { - managed-queues = <0 0x80>; - reg = <0x4100000 0x800>, - <0x4040000 0x100>, - <0x4080000 0x800>, - <0x40c0000 0x800>; - reg-names = "peek", "config", - "region", "push"; - }; - - }; - queue-pools { - qpend { - qpend-0 { - qrange = <77 8>; - interrupts =<0 308 0xf04 0 309 0xf04 0 310 0xf04 - 0 311 0xf04 0 312 0xf04 0 313 0xf04 - 0 314 0xf04 0 315 0xf04>; - qalloc-by-id; - }; - }; - general-purpose { - gp-0 { - qrange = <112 8>; - }; - netcp-tx { - qrange = <5 8>; - qalloc-by-id; - }; - }; - }; - - descriptor-regions { - #address-cells = <1>; - #size-cells = <1>; - ranges; - region-12 { - id = <12>; - region-spec = <1023 128>; /* num_desc desc_size */ - link-index = <0x400>; - }; - }; -}; /* qmss */ - -knav_dmas: knav_dmas@0 { - compatible = "ti,keystone-navigator-dma"; - #address-cells = <1>; - #size-cells = <1>; - status = "disabled"; - power-domains = <&k2g_pds 0x0018>; - clocks = <&k2g_clks 0x0018 0>; - clock-names = "nss_vclk"; - ranges; - ti,navigator-cloud-address = <0x40c0000 0x40c0000 0x40c0000 0x40c0000>; - - dma_gbe: dma_gbe@0 { - reg = <0x4010000 0x100>, - <0x4011000 0x2a0>, /* 21 Tx channels */ - <0x4012000 0x400>, /* 32 Rx channels */ - <0x4010100 0x80>, - <0x4013000 0x400>; /* 32 Rx flows */ - reg-names = "global", "txchan", "rxchan", - "txsched", "rxflow"; - }; - -}; - -netcp: netcp@4000000 { - reg = <0x2620110 0x8>; - reg-names = "efuse"; - compatible = "ti,netcp-1.0"; - #address-cells = <1>; - #size-cells = <1>; - status = "disabled"; - power-domains = <&k2g_pds 0x0018>; - clocks = <&k2g_clks 0x0018 3>, <&k2g_clks 0x0018 8>; - clock-names = "ethss_clk", "cpts"; - - /* NetCP address range */ - ranges = <0 0x4000000 0x1000000>; - - dma-coherent; - - ti,navigator-dmas = <&dma_gbe 0>, <&dma_gbe 5>; - ti,navigator-dma-names = "netrx0", "nettx"; - - netcp-devices { - #address-cells = <1>; - #size-cells = <1>; - ranges; - gbe: gbe@200000 { - label = "netcp-gbe"; - compatible = "ti,netcp-gbe-2"; - reg = <0x200000 0x20>, <0x220000 0x20000>; - enable-ale; - tx-queue = <5>; - tx-channel = "nettx"; - cpts-rftclk-sel = <0>; - cpts-ext-ts-inputs = <8>; - - interfaces { - gbe0: interface-0 { - slave-port = <0>; - link-interface = <5>; - }; - }; - }; - }; - - netcp-interfaces { - interface-0 { - rx-channel = "netrx0"; - rx-pool = <512 12>; - tx-pool = <511 12>; - rx-queue-depth = <128 128 0 0>; - rx-buffer-size = <1518 4096 0 0>; - rx-queue = <77>; - tx-completion-queue = <78>; - efuse-mac = <1>; - netcp-gbe = <&gbe0>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/keystone-k2g.dtsi b/sys/gnu/dts/arm/keystone-k2g.dtsi deleted file mode 100644 index 1c833105d6c..00000000000 --- a/sys/gnu/dts/arm/keystone-k2g.dtsi +++ /dev/null @@ -1,622 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for K2G SOC - * - * Copyright (C) 2016-2017 Texas Instruments Incorporated - http://www.ti.com/ - */ - -#include -#include -#include - -/ { - compatible = "ti,k2g","ti,keystone"; - model = "Texas Instruments K2G SoC"; - #address-cells = <2>; - #size-cells = <2>; - interrupt-parent = <&gic>; - - chosen { }; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - rproc0 = &dsp0; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <0>; - }; - }; - - gic: interrupt-controller@2561000 { - compatible = "arm,gic-400", "arm,cortex-a15-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x0 0x02561000 0x0 0x1000>, - <0x0 0x02562000 0x0 0x2000>, - <0x0 0x02564000 0x0 0x2000>, - <0x0 0x02566000 0x0 0x2000>; - interrupts = ; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = - , - , - , - ; - }; - - pmu { - compatible = "arm,cortex-a15-pmu"; - interrupts = ; - }; - - usbphy { - #address-cells = <1>; - #size-cells = <0>; - compatible = "simple-bus"; - - usb0_phy: usb-phy@0 { - compatible = "usb-nop-xceiv"; - reg = <0>; - status = "disabled"; - }; - - usb1_phy: usb-phy@1 { - compatible = "usb-nop-xceiv"; - reg = <1>; - status = "disabled"; - }; - }; - - soc0: soc@0 { - #address-cells = <1>; - #size-cells = <1>; - #pinctrl-cells = <1>; - compatible = "ti,keystone","simple-bus"; - ranges = <0x0 0x0 0x0 0xc0000000>; - dma-ranges = <0x80000000 0x8 0x00000000 0x80000000>; - - msm_ram: msmram@c000000 { - compatible = "mmio-sram"; - reg = <0x0c000000 0x100000>; - ranges = <0x0 0x0c000000 0x100000>; - #address-cells = <1>; - #size-cells = <1>; - - sram-bm@f7000 { - reg = <0x000f7000 0x8000>; - }; - }; - - k2g_pinctrl: pinmux@2621000 { - compatible = "pinctrl-single"; - reg = <0x02621000 0x410>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0x001b0007>; - }; - - devctrl: device-state-control@2620000 { - compatible = "ti,keystone-devctrl", "syscon", "simple-mfd"; - reg = <0x02620000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x02620000 0x1000>; - - kirq0: keystone_irq@2a0 { - compatible = "ti,keystone-irq"; - reg = <0x2a0 0x10>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <1>; - ti,syscon-dev = <&devctrl 0x2a0>; - }; - - dspgpio0: keystone_dsp_gpio@240 { - compatible = "ti,keystone-dsp-gpio"; - reg = <0x240 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio,syscon-dev = <&devctrl 0x240>; - }; - }; - - uart0: serial@2530c00 { - compatible = "ti,da830-uart", "ns16550a"; - current-speed = <115200>; - reg-shift = <2>; - reg-io-width = <4>; - reg = <0x02530c00 0x100>; - interrupts = ; - clocks = <&k2g_clks 0x2c 0>; - power-domains = <&k2g_pds 0x2c>; - status = "disabled"; - }; - - uart1: serial@2531000 { - compatible = "ti,da830-uart", "ns16550a"; - current-speed = <115200>; - reg-shift = <2>; - reg-io-width = <4>; - reg = <0x02531000 0x100>; - interrupts = ; - clocks = <&k2g_clks 0x2d 0>; - power-domains = <&k2g_pds 0x2d>; - status = "disabled"; - }; - - uart2: serial@2531400 { - compatible = "ti,da830-uart", "ns16550a"; - current-speed = <115200>; - reg-shift = <2>; - reg-io-width = <4>; - reg = <0x02531400 0x100>; - interrupts = ; - clocks = <&k2g_clks 0x2e 0>; - power-domains = <&k2g_pds 0x2e>; - status = "disabled"; - }; - - dcan0: can@260b200 { - compatible = "ti,am4372-d_can", "ti,am3352-d_can"; - reg = <0x0260B200 0x200>; - interrupts = ; - status = "disabled"; - power-domains = <&k2g_pds 0x0008>; - clocks = <&k2g_clks 0x0008 1>; - }; - - dcan1: can@260b400 { - compatible = "ti,am4372-d_can", "ti,am3352-d_can"; - reg = <0x0260B400 0x200>; - interrupts = ; - status = "disabled"; - power-domains = <&k2g_pds 0x0009>; - clocks = <&k2g_clks 0x0009 1>; - }; - - i2c0: i2c@2530000 { - compatible = "ti,keystone-i2c"; - reg = <0x02530000 0x400>; - clocks = <&k2g_clks 0x003a 0>; - power-domains = <&k2g_pds 0x003a>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c1: i2c@2530400 { - compatible = "ti,keystone-i2c"; - reg = <0x02530400 0x400>; - clocks = <&k2g_clks 0x003b 0>; - power-domains = <&k2g_pds 0x003b>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@2530800 { - compatible = "ti,keystone-i2c"; - reg = <0x02530800 0x400>; - clocks = <&k2g_clks 0x003c 0>; - power-domains = <&k2g_pds 0x003c>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - dsp0: dsp@10800000 { - compatible = "ti,k2g-dsp"; - reg = <0x10800000 0x00100000>, - <0x10e00000 0x00008000>, - <0x10f00000 0x00008000>; - reg-names = "l2sram", "l1pram", "l1dram"; - power-domains = <&k2g_pds 0x0046>; - ti,syscon-dev = <&devctrl 0x844>; - resets = <&k2g_reset 0x0046 0x1>; - interrupt-parent = <&kirq0>; - interrupts = <0 8>; - interrupt-names = "vring", "exception"; - kick-gpios = <&dspgpio0 27 0>; - status = "disabled"; - }; - - msgmgr: msgmgr@2a00000 { - compatible = "ti,k2g-message-manager"; - #mbox-cells = <2>; - reg-names = "queue_proxy_region", - "queue_state_debug_region"; - reg = <0x02a00000 0x400000>, <0x028c3400 0x400>; - interrupt-names = "rx_005", - "rx_057"; - interrupts = , - ; - }; - - pmmc: pmmc@2921c00 { - compatible = "ti,k2g-sci"; - /* - * In case of rare platforms that does not use k2g as - * system master, use /delete-property/ - */ - ti,system-reboot-controller; - mbox-names = "rx", "tx"; - mboxes= <&msgmgr 5 2>, - <&msgmgr 0 0>; - reg-names = "debug_messages"; - reg = <0x02921c00 0x400>; - - k2g_pds: power-controller { - compatible = "ti,sci-pm-domain"; - #power-domain-cells = <1>; - }; - - k2g_clks: clocks { - compatible = "ti,k2g-sci-clk"; - #clock-cells = <2>; - }; - - k2g_reset: reset-controller { - compatible = "ti,sci-reset"; - #reset-cells = <2>; - }; - }; - - gpio0: gpio@2603000 { - compatible = "ti,k2g-gpio", "ti,keystone-gpio"; - reg = <0x02603000 0x100>; - gpio-controller; - #gpio-cells = <2>; - - interrupts = , - , - , - , - , - , - , - , - ; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <144>; - ti,davinci-gpio-unbanked = <0>; - clocks = <&k2g_clks 0x001b 0x0>; - clock-names = "gpio"; - }; - - gpio1: gpio@260a000 { - compatible = "ti,k2g-gpio", "ti,keystone-gpio"; - reg = <0x0260a000 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupts = , - , - , - , - ; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <68>; - ti,davinci-gpio-unbanked = <0>; - clocks = <&k2g_clks 0x001c 0x0>; - clock-names = "gpio"; - }; - - edma0: edma@2700000 { - compatible = "ti,k2g-edma3-tpcc", "ti,edma3-tpcc"; - reg = <0x02700000 0x8000>; - reg-names = "edma3_cc"; - interrupts = , - , - ; - interrupt-names = "edma3_ccint", "emda3_mperr", - "edma3_ccerrint"; - dma-requests = <64>; - #dma-cells = <2>; - - ti,tptcs = <&edma0_tptc0 7>, <&edma0_tptc1 0>; - - ti,edma-memcpy-channels = <32 33 34 35>; - - power-domains = <&k2g_pds 0x3f>; - }; - - edma0_tptc0: tptc@2760000 { - compatible = "ti,k2g-edma3-tptc", "ti,edma3-tptc"; - reg = <0x02760000 0x400>; - power-domains = <&k2g_pds 0x3f>; - }; - - edma0_tptc1: tptc@2768000 { - compatible = "ti,k2g-edma3-tptc", "ti,edma3-tptc"; - reg = <0x02768000 0x400>; - power-domains = <&k2g_pds 0x3f>; - }; - - edma1: edma@2728000 { - compatible = "ti,k2g-edma3-tpcc", "ti,edma3-tpcc"; - reg = <0x02728000 0x8000>; - reg-names = "edma3_cc"; - interrupts = , - , - ; - interrupt-names = "edma3_ccint", "emda3_mperr", - "edma3_ccerrint"; - dma-requests = <64>; - #dma-cells = <2>; - - ti,tptcs = <&edma1_tptc0 7>, <&edma1_tptc1 0>; - - /* - * memcpy is disabled, can be enabled with: - * ti,edma-memcpy-channels = <12 13 14 15>; - * for example. - */ - - power-domains = <&k2g_pds 0x4f>; - }; - - edma1_tptc0: tptc@27b0000 { - compatible = "ti,k2g-edma3-tptc", "ti,edma3-tptc"; - reg = <0x027b0000 0x400>; - power-domains = <&k2g_pds 0x4f>; - }; - - edma1_tptc1: tptc@27b8000 { - compatible = "ti,k2g-edma3-tptc", "ti,edma3-tptc"; - reg = <0x027b8000 0x400>; - power-domains = <&k2g_pds 0x4f>; - }; - - mmc0: mmc@23000000 { - compatible = "ti,k2g-sdhci"; - reg = <0x23000000 0x400>; - interrupts = ; - bus-width = <4>; - no-1-8-v; - max-frequency = <96000000>; - power-domains = <&k2g_pds 0xb>; - clocks = <&k2g_clks 0xb 1>, <&k2g_clks 0xb 2>; - clock-names = "fck", "mmchsdb_fck"; - status = "disabled"; - }; - - mmc1: mmc@23100000 { - compatible = "ti,k2g-sdhci"; - reg = <0x23100000 0x400>; - interrupts = ; - bus-width = <8>; - no-1-8-v; - non-removable; - max-frequency = <96000000>; - power-domains = <&k2g_pds 0xc>; - clocks = <&k2g_clks 0xc 1>, <&k2g_clks 0xc 2>; - clock-names = "fck", "mmchsdb_fck"; - }; - - qspi: spi@2940000 { - compatible = "ti,k2g-qspi", "cdns,qspi-nor"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x02940000 0x1000>, - <0x24000000 0x4000000>; - interrupts = ; - cdns,fifo-depth = <256>; - cdns,fifo-width = <4>; - cdns,trigger-address = <0x24000000>; - clocks = <&k2g_clks 0x43 0x0>; - power-domains = <&k2g_pds 0x43>; - status = "disabled"; - }; - - mcasp0: mcasp@2340000 { - compatible = "ti,am33xx-mcasp-audio"; - reg = <0x02340000 0x2000>, - <0x21804000 0x1000>; - reg-names = "mpu","dat"; - interrupts = , - ; - interrupt-names = "tx", "rx"; - dmas = <&edma0 24 1>, <&edma0 25 1>; - dma-names = "tx", "rx"; - power-domains = <&k2g_pds 0x4>; - clocks = <&k2g_clks 0x4 0>; - clock-names = "fck"; - status = "disabled"; - }; - - mcasp1: mcasp@2342000 { - compatible = "ti,am33xx-mcasp-audio"; - reg = <0x02342000 0x2000>, - <0x21804400 0x1000>; - reg-names = "mpu","dat"; - interrupts = , - ; - interrupt-names = "tx", "rx"; - dmas = <&edma1 48 1>, <&edma1 49 1>; - dma-names = "tx", "rx"; - power-domains = <&k2g_pds 0x5>; - clocks = <&k2g_clks 0x5 0>; - clock-names = "fck"; - status = "disabled"; - }; - - mcasp2: mcasp@2344000 { - compatible = "ti,am33xx-mcasp-audio"; - reg = <0x02344000 0x2000>, - <0x21804800 0x1000>; - reg-names = "mpu","dat"; - interrupts = , - ; - interrupt-names = "tx", "rx"; - dmas = <&edma1 50 1>, <&edma1 51 1>; - dma-names = "tx", "rx"; - power-domains = <&k2g_pds 0x6>; - clocks = <&k2g_clks 0x6 0>; - clock-names = "fck"; - status = "disabled"; - }; - - keystone_usb0: keystone-dwc3@2680000 { - compatible = "ti,keystone-dwc3"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x2680000 0x10000>; - interrupts = ; - ranges; - dma-coherent; - dma-ranges; - status = "disabled"; - power-domains = <&k2g_pds 0x0016>; - - usb0: usb@2690000 { - compatible = "snps,dwc3"; - reg = <0x2690000 0x10000>; - interrupts = ; - maximum-speed = "high-speed"; - dr_mode = "otg"; - usb-phy = <&usb0_phy>; - status = "disabled"; - }; - }; - - keystone_usb1: keystone-dwc3@2580000 { - compatible = "ti,keystone-dwc3"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x2580000 0x10000>; - interrupts = ; - ranges; - dma-coherent; - dma-ranges; - status = "disabled"; - power-domains = <&k2g_pds 0x0017>; - - usb1: usb@2590000 { - compatible = "snps,dwc3"; - reg = <0x2590000 0x10000>; - interrupts = ; - maximum-speed = "high-speed"; - dr_mode = "otg"; - usb-phy = <&usb1_phy>; - status = "disabled"; - }; - }; - - ecap0: pwm@21d1800 { - compatible = "ti,k2g-ecap", "ti,am3352-ecap"; - #pwm-cells = <3>; - reg = <0x021d1800 0x60>; - power-domains = <&k2g_pds 0x38>; - clocks = <&k2g_clks 0x38 0>; - clock-names = "fck"; - status = "disabled"; - }; - - ecap1: pwm@21d1c00 { - compatible = "ti,k2g-ecap", "ti,am3352-ecap"; - #pwm-cells = <3>; - reg = <0x021d1c00 0x60>; - power-domains = <&k2g_pds 0x39>; - clocks = <&k2g_clks 0x39 0x0>; - clock-names = "fck"; - status = "disabled"; - }; - - spi0: spi@21805400 { - compatible = "ti,keystone-spi"; - reg = <0x21805400 0x200>; - num-cs = <4>; - ti,davinci-spi-intr-line = <0>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k2g_pds 0x0010>; - clocks = <&k2g_clks 0x0010 0>; - }; - - spi1: spi@21805800 { - compatible = "ti,keystone-spi"; - reg = <0x21805800 0x200>; - num-cs = <4>; - ti,davinci-spi-intr-line = <0>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k2g_pds 0x0011>; - clocks = <&k2g_clks 0x0011 0>; - }; - - spi2: spi@21805c00 { - compatible = "ti,keystone-spi"; - reg = <0x21805C00 0x200>; - num-cs = <4>; - ti,davinci-spi-intr-line = <0>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k2g_pds 0x0012>; - clocks = <&k2g_clks 0x0012 0>; - }; - - spi3: spi@21806000 { - compatible = "ti,keystone-spi"; - reg = <0x21806000 0x200>; - num-cs = <4>; - ti,davinci-spi-intr-line = <0>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k2g_pds 0x0013>; - clocks = <&k2g_clks 0x0013 0>; - }; - - wdt: wdt@02250000 { - compatible = "ti,keystone-wdt", "ti,davinci-wdt"; - reg = <0x02250000 0x80>; - power-domains = <&k2g_pds 0x22>; - clocks = <&k2g_clks 0x22 0>; - }; - - emif: emif@21010000 { - compatible = "ti,emif-keystone"; - reg = <0x21010000 0x200>; - interrupts = ; - }; - - mdio: mdio@4200f00 { - compatible = "ti,keystone_mdio", "ti,davinci_mdio"; - reg = <0x04200f00 0x100>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&k2g_clks 0x0018 3>; - clock-names = "fck"; - power-domains = <&k2g_pds 0x0018>; - status = "disabled"; - bus_freq = <2500000>; - }; - #include "keystone-k2g-netcp.dtsi" - }; -}; diff --git a/sys/gnu/dts/arm/keystone-k2hk-clocks.dtsi b/sys/gnu/dts/arm/keystone-k2hk-clocks.dtsi deleted file mode 100644 index 4ba6912176e..00000000000 --- a/sys/gnu/dts/arm/keystone-k2hk-clocks.dtsi +++ /dev/null @@ -1,422 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Keystone 2 Kepler/Hawking SoC clock nodes - * - * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/ - */ - -clocks { - armpllclk: armpllclk@2620370 { - #clock-cells = <0>; - compatible = "ti,keystone,pll-clock"; - clocks = <&refclkarm>; - clock-output-names = "arm-pll-clk"; - reg = <0x02620370 4>; - reg-names = "control"; - }; - - mainpllclk: mainpllclk@2310110 { - #clock-cells = <0>; - compatible = "ti,keystone,main-pll-clock"; - clocks = <&refclksys>; - reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>; - reg-names = "control", "multiplier", "post-divider"; - }; - - papllclk: papllclk@2620358 { - #clock-cells = <0>; - compatible = "ti,keystone,pll-clock"; - clocks = <&refclkpass>; - clock-output-names = "papllclk"; - reg = <0x02620358 4>; - reg-names = "control"; - }; - - ddr3apllclk: ddr3apllclk@2620360 { - #clock-cells = <0>; - compatible = "ti,keystone,pll-clock"; - clocks = <&refclkddr3a>; - clock-output-names = "ddr-3a-pll-clk"; - reg = <0x02620360 4>; - reg-names = "control"; - }; - - ddr3bpllclk: ddr3bpllclk@2620368 { - #clock-cells = <0>; - compatible = "ti,keystone,pll-clock"; - clocks = <&refclkddr3b>; - clock-output-names = "ddr-3b-pll-clk"; - reg = <0x02620368 4>; - reg-names = "control"; - }; - - clktsip: clktsip@2350000 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk16>; - clock-output-names = "tsip"; - reg = <0x02350000 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; - - clksrio: clksrio@235002c { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk1rstiso13>; - clock-output-names = "srio"; - reg = <0x0235002c 0xb00>, <0x02350010 0x400>; - reg-names = "control", "domain"; - domain-id = <4>; - }; - - clkhyperlink0: clkhyperlink0@2350030 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk12>; - clock-output-names = "hyperlink-0"; - reg = <0x02350030 0xb00>, <0x02350014 0x400>; - reg-names = "control", "domain"; - domain-id = <5>; - }; - - clkgem1: clkgem1@2350040 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk1>; - clock-output-names = "gem1"; - reg = <0x02350040 0xb00>, <0x02350024 0x400>; - reg-names = "control", "domain"; - domain-id = <9>; - }; - - clkgem2: clkgem2@2350044 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk1>; - clock-output-names = "gem2"; - reg = <0x02350044 0xb00>, <0x02350028 0x400>; - reg-names = "control", "domain"; - domain-id = <10>; - }; - - clkgem3: clkgem3@2350048 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk1>; - clock-output-names = "gem3"; - reg = <0x02350048 0xb00>, <0x0235002c 0x400>; - reg-names = "control", "domain"; - domain-id = <11>; - }; - - clkgem4: clkgem4@235004c { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk1>; - clock-output-names = "gem4"; - reg = <0x0235004c 0xb00>, <0x02350030 0x400>; - reg-names = "control", "domain"; - domain-id = <12>; - }; - - clkgem5: clkgem5@2350050 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk1>; - clock-output-names = "gem5"; - reg = <0x02350050 0xb00>, <0x02350034 0x400>; - reg-names = "control", "domain"; - domain-id = <13>; - }; - - clkgem6: clkgem6@2350054 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk1>; - clock-output-names = "gem6"; - reg = <0x02350054 0xb00>, <0x02350038 0x400>; - reg-names = "control", "domain"; - domain-id = <14>; - }; - - clkgem7: clkgem7@2350058 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk1>; - clock-output-names = "gem7"; - reg = <0x02350058 0xb00>, <0x0235003c 0x400>; - reg-names = "control", "domain"; - domain-id = <15>; - }; - - clkddr31: clkddr31@2350060 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "ddr3-1"; - reg = <0x02350060 0xb00>, <0x02350040 0x400>; - reg-names = "control", "domain"; - domain-id = <16>; - }; - - clktac: clktac@2350064 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "tac"; - reg = <0x02350064 0xb00>, <0x02350044 0x400>; - reg-names = "control", "domain"; - domain-id = <17>; - }; - - clkrac01: clkrac01@2350068 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "rac-01"; - reg = <0x02350068 0xb00>, <0x02350044 0x400>; - reg-names = "control", "domain"; - domain-id = <17>; - }; - - clkrac23: clkrac23@235006c { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "rac-23"; - reg = <0x0235006c 0xb00>, <0x02350048 0x400>; - reg-names = "control", "domain"; - domain-id = <18>; - }; - - clkfftc0: clkfftc0@2350070 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "fftc-0"; - reg = <0x02350070 0xb00>, <0x0235004c 0x400>; - reg-names = "control", "domain"; - domain-id = <19>; - }; - - clkfftc1: clkfftc1@2350074 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "fftc-1"; - reg = <0x02350074 0xb00>, <0x0235004c 0x400>; - reg-names = "control", "domain"; - domain-id = <19>; - }; - - clkfftc2: clkfftc2@2350078 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "fftc-2"; - reg = <0x02350078 0xb00>, <0x02350050 0x400>; - reg-names = "control", "domain"; - domain-id = <20>; - }; - - clkfftc3: clkfftc3@235007c { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "fftc-3"; - reg = <0x0235007c 0xb00>, <0x02350050 0x400>; - reg-names = "control", "domain"; - domain-id = <20>; - }; - - clkfftc4: clkfftc4@2350080 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "fftc-4"; - reg = <0x02350080 0xb00>, <0x02350050 0x400>; - reg-names = "control", "domain"; - domain-id = <20>; - }; - - clkfftc5: clkfftc5@2350084 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "fftc-5"; - reg = <0x02350084 0xb00>, <0x02350050 0x400>; - reg-names = "control", "domain"; - domain-id = <20>; - }; - - clkaif: clkaif@2350088 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "aif"; - reg = <0x02350088 0xb00>, <0x02350054 0x400>; - reg-names = "control", "domain"; - domain-id = <21>; - }; - - clktcp3d0: clktcp3d0@235008c { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "tcp3d-0"; - reg = <0x0235008c 0xb00>, <0x02350058 0x400>; - reg-names = "control", "domain"; - domain-id = <22>; - }; - - clktcp3d1: clktcp3d1@2350090 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "tcp3d-1"; - reg = <0x02350090 0xb00>, <0x02350058 0x400>; - reg-names = "control", "domain"; - domain-id = <22>; - }; - - clktcp3d2: clktcp3d2@2350094 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "tcp3d-2"; - reg = <0x02350094 0xb00>, <0x0235005c 0x400>; - reg-names = "control", "domain"; - domain-id = <23>; - }; - - clktcp3d3: clktcp3d3@2350098 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "tcp3d-3"; - reg = <0x02350098 0xb00>, <0x0235005c 0x400>; - reg-names = "control", "domain"; - domain-id = <23>; - }; - - clkvcp0: clkvcp0@235009c { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "vcp-0"; - reg = <0x0235009c 0xb00>, <0x02350060 0x400>; - reg-names = "control", "domain"; - domain-id = <24>; - }; - - clkvcp1: clkvcp1@23500a0 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "vcp-1"; - reg = <0x023500a0 0xb00>, <0x02350060 0x400>; - reg-names = "control", "domain"; - domain-id = <24>; - }; - - clkvcp2: clkvcp2@23500a4 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "vcp-2"; - reg = <0x023500a4 0xb00>, <0x02350060 0x400>; - reg-names = "control", "domain"; - domain-id = <24>; - }; - - clkvcp3: clkvcp3@23500a8 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "vcp-3"; - reg = <0x023500a8 0xb00>, <0x02350060 0x400>; - reg-names = "control", "domain"; - domain-id = <24>; - }; - - clkvcp4: clkvcp4@23500ac { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "vcp-4"; - reg = <0x023500ac 0xb00>, <0x02350064 0x400>; - reg-names = "control", "domain"; - domain-id = <25>; - }; - - clkvcp5: clkvcp5@23500b0 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "vcp-5"; - reg = <0x023500b0 0xb00>, <0x02350064 0x400>; - reg-names = "control", "domain"; - domain-id = <25>; - }; - - clkvcp6: clkvcp6@23500b4 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "vcp-6"; - reg = <0x023500b4 0xb00>, <0x02350064 0x400>; - reg-names = "control", "domain"; - domain-id = <25>; - }; - - clkvcp7: clkvcp7@23500b8 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "vcp-7"; - reg = <0x023500b8 0xb00>, <0x02350064 0x400>; - reg-names = "control", "domain"; - domain-id = <25>; - }; - - clkbcp: clkbcp@23500bc { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "bcp"; - reg = <0x023500bc 0xb00>, <0x02350068 0x400>; - reg-names = "control", "domain"; - domain-id = <26>; - }; - - clkdxb: clkdxb@23500c0 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "dxb"; - reg = <0x023500c0 0xb00>, <0x0235006c 0x400>; - reg-names = "control", "domain"; - domain-id = <27>; - }; - - clkhyperlink1: clkhyperlink1@23500c4 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk12>; - clock-output-names = "hyperlink-1"; - reg = <0x023500c4 0xb00>, <0x02350070 0x400>; - reg-names = "control", "domain"; - domain-id = <28>; - }; - - clkxge: clkxge@23500c8 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "xge"; - reg = <0x023500c8 0xb00>, <0x02350074 0x400>; - reg-names = "control", "domain"; - domain-id = <29>; - }; -}; diff --git a/sys/gnu/dts/arm/keystone-k2hk-evm.dts b/sys/gnu/dts/arm/keystone-k2hk-evm.dts deleted file mode 100644 index ad4e22afe13..00000000000 --- a/sys/gnu/dts/arm/keystone-k2hk-evm.dts +++ /dev/null @@ -1,236 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Keystone 2 Kepler/Hawking EVM device tree - * - * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/ - */ -/dts-v1/; - -#include "keystone.dtsi" -#include "keystone-k2hk.dtsi" - -/ { - compatible = "ti,k2hk-evm", "ti,k2hk", "ti,keystone"; - model = "Texas Instruments Keystone 2 Kepler/Hawking EVM"; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - dsp_common_memory: dsp-common-memory@81f800000 { - compatible = "shared-dma-pool"; - reg = <0x00000008 0x1f800000 0x00000000 0x800000>; - reusable; - status = "okay"; - }; - }; - - leds { - compatible = "gpio-leds"; - debug1_1 { - label = "keystone:green:debug1"; - gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; /* 12 */ - }; - - debug1_2 { - label = "keystone:red:debug1"; - gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; /* 13 */ - }; - - debug2 { - label = "keystone:blue:debug2"; - gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; /* 14 */ - }; - - debug3 { - label = "keystone:blue:debug3"; - gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; /* 15 */ - }; - }; -}; - -&soc0 { - clocks { - refclksys: refclksys { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <122880000>; - clock-output-names = "refclk-sys"; - }; - - refclkpass: refclkpass { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <122880000>; - clock-output-names = "refclk-pass"; - }; - - refclkarm: refclkarm { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "refclk-arm"; - }; - - refclkddr3a: refclkddr3a { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <100000000>; - clock-output-names = "refclk-ddr3a"; - }; - - refclkddr3b: refclkddr3b { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <100000000>; - clock-output-names = "refclk-ddr3b"; - }; - }; -}; - -&usb_phy { - status = "okay"; -}; - -&keystone_usb0 { - status = "okay"; -}; - -&usb0 { - dr_mode = "host"; -}; - -&aemif { - cs0 { - #address-cells = <2>; - #size-cells = <1>; - clock-ranges; - ranges; - - ti,cs-chipselect = <0>; - /* all timings in nanoseconds */ - ti,cs-min-turnaround-ns = <12>; - ti,cs-read-hold-ns = <6>; - ti,cs-read-strobe-ns = <23>; - ti,cs-read-setup-ns = <9>; - ti,cs-write-hold-ns = <8>; - ti,cs-write-strobe-ns = <23>; - ti,cs-write-setup-ns = <8>; - - nand@0,0 { - compatible = "ti,keystone-nand","ti,davinci-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0 0 0x4000000 - 1 0 0x0000100>; - - ti,davinci-chipselect = <0>; - ti,davinci-mask-ale = <0x2000>; - ti,davinci-mask-cle = <0x4000>; - ti,davinci-mask-chipsel = <0>; - nand-ecc-mode = "hw"; - ti,davinci-ecc-bits = <4>; - nand-on-flash-bbt; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x100000>; - read-only; - }; - - partition@100000 { - label = "params"; - reg = <0x100000 0x80000>; - read-only; - }; - - partition@180000 { - label = "ubifs"; - reg = <0x180000 0x1fe80000>; - }; - }; - }; -}; - -&i2c0 { - dtt@50 { - compatible = "atmel,24c1024"; - reg = <0x50>; - }; -}; - -&spi0 { - nor_flash: n25q128a11@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "Micron,n25q128a11"; - spi-max-frequency = <54000000>; - m25p,fast-read; - reg = <0>; - - partition@0 { - label = "u-boot-spl"; - reg = <0x0 0x80000>; - read-only; - }; - - partition@1 { - label = "misc"; - reg = <0x80000 0xf80000>; - }; - }; -}; - -&mdio { - status = "ok"; - ethphy0: ethernet-phy@0 { - compatible = "marvell,88E1111", "ethernet-phy-ieee802.3-c22"; - reg = <0>; - }; - - ethphy1: ethernet-phy@1 { - compatible = "marvell,88E1111", "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; -}; - -&dsp0 { - memory-region = <&dsp_common_memory>; - status = "okay"; -}; - -&dsp1 { - memory-region = <&dsp_common_memory>; - status = "okay"; -}; - -&dsp2 { - memory-region = <&dsp_common_memory>; - status = "okay"; -}; - -&dsp3 { - memory-region = <&dsp_common_memory>; - status = "okay"; -}; - -&dsp4 { - memory-region = <&dsp_common_memory>; - status = "okay"; -}; - -&dsp5 { - memory-region = <&dsp_common_memory>; - status = "okay"; -}; - -&dsp6 { - memory-region = <&dsp_common_memory>; - status = "okay"; -}; - -&dsp7 { - memory-region = <&dsp_common_memory>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/keystone-k2hk-netcp.dtsi b/sys/gnu/dts/arm/keystone-k2hk-netcp.dtsi deleted file mode 100644 index d5a6c1f5633..00000000000 --- a/sys/gnu/dts/arm/keystone-k2hk-netcp.dtsi +++ /dev/null @@ -1,266 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for Keystone 2 Hawking Netcp driver - * - * Copyright (C) 2015-2017 Texas Instruments Incorporated - http://www.ti.com/ - */ - -qmss: qmss@2a40000 { - compatible = "ti,keystone-navigator-qmss"; - dma-coherent; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&chipclk13>; - ranges; - queue-range = <0 0x4000>; - linkram0 = <0x100000 0x8000>; - linkram1 = <0x0 0x10000>; - - qmgrs { - #address-cells = <1>; - #size-cells = <1>; - ranges; - qmgr0 { - managed-queues = <0 0x2000>; - reg = <0x2a40000 0x20000>, - <0x2a06000 0x400>, - <0x2a02000 0x1000>, - <0x2a03000 0x1000>, - <0x23a80000 0x20000>, - <0x2a80000 0x20000>; - reg-names = "peek", "status", "config", - "region", "push", "pop"; - }; - - qmgr1 { - managed-queues = <0x2000 0x2000>; - reg = <0x2a60000 0x20000>, - <0x2a06400 0x400>, - <0x2a04000 0x1000>, - <0x2a05000 0x1000>, - <0x23aa0000 0x20000>, - <0x2aa0000 0x20000>; - reg-names = "peek", "status", "config", - "region", "push", "pop"; - }; - }; - - queue-pools { - qpend { - qpend-0 { - qrange = <658 8>; - interrupts =<0 40 0xf04 0 41 0xf04 0 42 0xf04 - 0 43 0xf04 0 44 0xf04 0 45 0xf04 - 0 46 0xf04 0 47 0xf04>; - }; - qpend-1 { - qrange = <8704 16>; - interrupts = <0 48 0xf04 0 49 0xf04 0 50 0xf04 - 0 51 0xf04 0 52 0xf04 0 53 0xf04 - 0 54 0xf04 0 55 0xf04 0 56 0xf04 - 0 57 0xf04 0 58 0xf04 0 59 0xf04 - 0 60 0xf04 0 61 0xf04 0 62 0xf04 - 0 63 0xf04>; - qalloc-by-id; - }; - qpend-2 { - qrange = <8720 16>; - interrupts = <0 64 0xf04 0 65 0xf04 0 66 0xf04 - 0 59 0xf04 0 68 0xf04 0 69 0xf04 - 0 70 0xf04 0 71 0xf04 0 72 0xf04 - 0 73 0xf04 0 74 0xf04 0 75 0xf04 - 0 76 0xf04 0 77 0xf04 0 78 0xf04 - 0 79 0xf04>; - }; - }; - general-purpose { - gp-0 { - qrange = <4000 64>; - }; - netcp-tx { - qrange = <640 9>; - qalloc-by-id; - }; - netcpx-tx { - qrange = <8752 8>; - qalloc-by-id; - }; - }; - accumulator { - acc-low-0 { - qrange = <480 32>; - accumulator = <0 47 16 2 50>; - interrupts = <0 226 0xf01>; - multi-queue; - qalloc-by-id; - }; - }; - }; - - descriptor-regions { - #address-cells = <1>; - #size-cells = <1>; - ranges; - region-12 { - id = <12>; - region-spec = <8192 128>; /* num_desc desc_size */ - link-index = <0x4000>; - }; - }; - - pdsps { - #address-cells = <1>; - #size-cells = <1>; - ranges; - pdsp0@0x2a10000 { - reg = <0x2a10000 0x1000 /*iram */ - 0x2a0f000 0x100 /*reg*/ - 0x2a0c000 0x3c8 /*intd */ - 0x2a20000 0x4000>; /*cmd*/ - id = <0>; - }; - }; -}; /* qmss */ - -knav_dmas: knav_dmas@0 { - compatible = "ti,keystone-navigator-dma"; - clocks = <&papllclk>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - ti,navigator-cloud-address = <0x23a80000 0x23a90000 - 0x23aa0000 0x23ab0000>; - - dma_gbe: dma_gbe@0 { - reg = <0x2004000 0x100>, - <0x2004400 0x120>, - <0x2004800 0x300>, - <0x2004c00 0x120>, - <0x2005000 0x400>; - reg-names = "global", "txchan", "rxchan", - "txsched", "rxflow"; - }; -}; - -netcp: netcp@2000000 { - reg = <0x2620110 0x8>; - reg-names = "efuse"; - compatible = "ti,netcp-1.0"; - #address-cells = <1>; - #size-cells = <1>; - - /* NetCP address range */ - ranges = <0 0x2000000 0x100000>; - - clocks = <&clkpa>, <&clkcpgmac>; - clock-names = "pa_clk", "ethss_clk"; - dma-coherent; - - ti,navigator-dmas = <&dma_gbe 22>, - <&dma_gbe 23>, - <&dma_gbe 8>; - ti,navigator-dma-names = "netrx0", "netrx1", "nettx"; - - netcp-devices { - ranges; - #address-cells = <1>; - #size-cells = <1>; - gbe@90000 { /* ETHSS */ - #address-cells = <1>; - #size-cells = <1>; - label = "netcp-gbe"; - compatible = "ti,netcp-gbe"; - reg = <0x90000 0x300>, <0x90400 0x400>, <0x90800 0x700>; - /* enable-ale; */ - tx-queue = <648>; - tx-channel = "nettx"; - - cpts { - clocks = <&cpts_refclk_mux>; - clock-names = "cpts"; - - cpts_refclk_mux: cpts-refclk-mux { - #clock-cells = <0>; - clocks = <&chipclk12>, <&chipclk13>, - <&timi0>, <&timi1>, - <&tsrefclk>; - ti,mux-tbl = <0x0>, <0x1>, <0x2>, - <0x3>, <0x8>; - assigned-clocks = <&cpts_refclk_mux>; - assigned-clock-parents = <&chipclk12>; - }; - }; - - interfaces { - gbe0: interface-0 { - slave-port = <0>; - link-interface = <1>; - phy-handle = <ðphy0>; - }; - gbe1: interface-1 { - slave-port = <1>; - link-interface = <1>; - phy-handle = <ðphy1>; - }; - }; - - secondary-slave-ports { - port-2 { - slave-port = <2>; - link-interface = <2>; - }; - port-3 { - slave-port = <3>; - link-interface = <2>; - }; - }; - }; - }; - - netcp-interfaces { - interface-0 { - rx-channel = "netrx0"; - rx-pool = <1024 12>; - tx-pool = <1024 12>; - rx-queue-depth = <128 128 0 0>; - rx-buffer-size = <1518 4096 0 0>; - rx-queue = <8704>; - tx-completion-queue = <8706>; - efuse-mac = <1>; - netcp-gbe = <&gbe0>; - - }; - interface-1 { - rx-channel = "netrx1"; - rx-pool = <1024 12>; - tx-pool = <1024 12>; - rx-queue-depth = <128 128 0 0>; - rx-buffer-size = <1518 4096 0 0>; - rx-queue = <8705>; - tx-completion-queue = <8707>; - efuse-mac = <0>; - local-mac-address = [02 18 31 7e 3e 6f]; - netcp-gbe = <&gbe1>; - }; - }; -}; - -sa_subsys: subsys@20c0000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x20c0000 0x40000>; - - sa_config: subsys@0 { - compatible = "syscon"; - reg = <0x0 0x100>; - }; - - rng@24000 { - compatible = "ti,keystone-rng"; - reg = <0x24000 0x1000>; - ti,syscon-sa-cfg = <&sa_config>; - clocks = <&clksa>; - clock-names = "fck"; - }; -}; diff --git a/sys/gnu/dts/arm/keystone-k2hk.dtsi b/sys/gnu/dts/arm/keystone-k2hk.dtsi deleted file mode 100644 index ca0f198ba62..00000000000 --- a/sys/gnu/dts/arm/keystone-k2hk.dtsi +++ /dev/null @@ -1,295 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Keystone 2 Kepler/Hawking soc specific device tree - * - * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/ - */ - -#include - -/ { - compatible = "ti,k2hk", "ti,keystone"; - model = "Texas Instruments Keystone 2 Kepler/Hawking SoC"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - interrupt-parent = <&gic>; - - cpu@0 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <0>; - }; - - cpu@1 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <1>; - }; - - cpu@2 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <2>; - }; - - cpu@3 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <3>; - }; - }; - - aliases { - rproc0 = &dsp0; - rproc1 = &dsp1; - rproc2 = &dsp2; - rproc3 = &dsp3; - rproc4 = &dsp4; - rproc5 = &dsp5; - rproc6 = &dsp6; - rproc7 = &dsp7; - }; -}; - -&soc0 { - /include/ "keystone-k2hk-clocks.dtsi" - - msm_ram: msmram@c000000 { - compatible = "mmio-sram"; - reg = <0x0c000000 0x600000>; - ranges = <0x0 0x0c000000 0x600000>; - #address-cells = <1>; - #size-cells = <1>; - - sram-bm@5f0000 { - reg = <0x5f0000 0x8000>; - }; - }; - - psc: power-sleep-controller@2350000 { - pscrst: reset-controller { - compatible = "ti,k2hk-pscrst", "ti,syscon-reset"; - #reset-cells = <1>; - - ti,reset-bits = < - 0xa3c 8 0xa3c 8 0x83c 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 0: dsp0 */ - 0xa40 8 0xa40 8 0x840 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 1: dsp1 */ - 0xa44 8 0xa44 8 0x844 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 2: dsp2 */ - 0xa48 8 0xa48 8 0x848 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 3: dsp3 */ - 0xa4c 8 0xa4c 8 0x84c 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 4: dsp4 */ - 0xa50 8 0xa50 8 0x850 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 5: dsp5 */ - 0xa54 8 0xa54 8 0x854 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 6: dsp6 */ - 0xa58 8 0xa58 8 0x858 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 7: dsp7 */ - >; - }; - }; - - devctrl: device-state-control@2620000 { - dspgpio0: keystone_dsp_gpio@240 { - compatible = "ti,keystone-dsp-gpio"; - reg = <0x240 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio,syscon-dev = <&devctrl 0x240>; - }; - - dspgpio1: keystone_dsp_gpio@244 { - compatible = "ti,keystone-dsp-gpio"; - reg = <0x244 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio,syscon-dev = <&devctrl 0x244>; - }; - - dspgpio2: keystone_dsp_gpio@248 { - compatible = "ti,keystone-dsp-gpio"; - reg = <0x248 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio,syscon-dev = <&devctrl 0x248>; - }; - - dspgpio3: keystone_dsp_gpio@24c { - compatible = "ti,keystone-dsp-gpio"; - reg = <0x24c 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio,syscon-dev = <&devctrl 0x24c>; - }; - - dspgpio4: keystone_dsp_gpio@250 { - compatible = "ti,keystone-dsp-gpio"; - reg = <0x250 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio,syscon-dev = <&devctrl 0x250>; - }; - - dspgpio5: keystone_dsp_gpio@254 { - compatible = "ti,keystone-dsp-gpio"; - reg = <0x254 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio,syscon-dev = <&devctrl 0x254>; - }; - - dspgpio6: keystone_dsp_gpio@258 { - compatible = "ti,keystone-dsp-gpio"; - reg = <0x258 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio,syscon-dev = <&devctrl 0x258>; - }; - - dspgpio7: keystone_dsp_gpio@25c { - compatible = "ti,keystone-dsp-gpio"; - reg = <0x25c 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio,syscon-dev = <&devctrl 0x25c>; - }; - }; - - dsp0: dsp@10800000 { - compatible = "ti,k2hk-dsp"; - reg = <0x10800000 0x00100000>, - <0x10e00000 0x00008000>, - <0x10f00000 0x00008000>; - reg-names = "l2sram", "l1pram", "l1dram"; - clocks = <&clkgem0>; - ti,syscon-dev = <&devctrl 0x40>; - resets = <&pscrst 0>; - interrupt-parent = <&kirq0>; - interrupts = <0 8>; - interrupt-names = "vring", "exception"; - kick-gpios = <&dspgpio0 27 0>; - status = "disabled"; - }; - - dsp1: dsp@11800000 { - compatible = "ti,k2hk-dsp"; - reg = <0x11800000 0x00100000>, - <0x11e00000 0x00008000>, - <0x11f00000 0x00008000>; - reg-names = "l2sram", "l1pram", "l1dram"; - clocks = <&clkgem1>; - ti,syscon-dev = <&devctrl 0x44>; - resets = <&pscrst 1>; - interrupt-parent = <&kirq0>; - interrupts = <1 9>; - interrupt-names = "vring", "exception"; - kick-gpios = <&dspgpio1 27 0>; - status = "disabled"; - }; - - dsp2: dsp@12800000 { - compatible = "ti,k2hk-dsp"; - reg = <0x12800000 0x00100000>, - <0x12e00000 0x00008000>, - <0x12f00000 0x00008000>; - reg-names = "l2sram", "l1pram", "l1dram"; - clocks = <&clkgem2>; - ti,syscon-dev = <&devctrl 0x48>; - resets = <&pscrst 2>; - interrupt-parent = <&kirq0>; - interrupts = <2 10>; - interrupt-names = "vring", "exception"; - kick-gpios = <&dspgpio2 27 0>; - status = "disabled"; - }; - - dsp3: dsp@13800000 { - compatible = "ti,k2hk-dsp"; - reg = <0x13800000 0x00100000>, - <0x13e00000 0x00008000>, - <0x13f00000 0x00008000>; - reg-names = "l2sram", "l1pram", "l1dram"; - clocks = <&clkgem3>; - ti,syscon-dev = <&devctrl 0x4c>; - resets = <&pscrst 3>; - interrupt-parent = <&kirq0>; - interrupts = <3 11>; - interrupt-names = "vring", "exception"; - kick-gpios = <&dspgpio3 27 0>; - status = "disabled"; - }; - - dsp4: dsp@14800000 { - compatible = "ti,k2hk-dsp"; - reg = <0x14800000 0x00100000>, - <0x14e00000 0x00008000>, - <0x14f00000 0x00008000>; - reg-names = "l2sram", "l1pram", "l1dram"; - clocks = <&clkgem4>; - ti,syscon-dev = <&devctrl 0x50>; - resets = <&pscrst 4>; - interrupt-parent = <&kirq0>; - interrupts = <4 12>; - interrupt-names = "vring", "exception"; - kick-gpios = <&dspgpio4 27 0>; - status = "disabled"; - }; - - dsp5: dsp@15800000 { - compatible = "ti,k2hk-dsp"; - reg = <0x15800000 0x00100000>, - <0x15e00000 0x00008000>, - <0x15f00000 0x00008000>; - reg-names = "l2sram", "l1pram", "l1dram"; - clocks = <&clkgem5>; - ti,syscon-dev = <&devctrl 0x54>; - resets = <&pscrst 5>; - interrupt-parent = <&kirq0>; - interrupts = <5 13>; - interrupt-names = "vring", "exception"; - kick-gpios = <&dspgpio5 27 0>; - status = "disabled"; - }; - - dsp6: dsp@16800000 { - compatible = "ti,k2hk-dsp"; - reg = <0x16800000 0x00100000>, - <0x16e00000 0x00008000>, - <0x16f00000 0x00008000>; - reg-names = "l2sram", "l1pram", "l1dram"; - clocks = <&clkgem6>; - ti,syscon-dev = <&devctrl 0x58>; - resets = <&pscrst 6>; - interrupt-parent = <&kirq0>; - interrupts = <6 14>; - interrupt-names = "vring", "exception"; - kick-gpios = <&dspgpio6 27 0>; - status = "disabled"; - }; - - dsp7: dsp@17800000 { - compatible = "ti,k2hk-dsp"; - reg = <0x17800000 0x00100000>, - <0x17e00000 0x00008000>, - <0x17f00000 0x00008000>; - reg-names = "l2sram", "l1pram", "l1dram"; - clocks = <&clkgem7>; - ti,syscon-dev = <&devctrl 0x5c>; - resets = <&pscrst 7>; - interrupt-parent = <&kirq0>; - interrupts = <7 15>; - interrupt-names = "vring", "exception"; - kick-gpios = <&dspgpio7 27 0>; - status = "disabled"; - }; - - mdio: mdio@2090300 { - compatible = "ti,keystone_mdio", "ti,davinci_mdio"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x02090300 0x100>; - status = "disabled"; - clocks = <&clkcpgmac>; - clock-names = "fck"; - bus_freq = <2500000>; - }; - /include/ "keystone-k2hk-netcp.dtsi" -}; diff --git a/sys/gnu/dts/arm/keystone-k2l-clocks.dtsi b/sys/gnu/dts/arm/keystone-k2l-clocks.dtsi deleted file mode 100644 index 635528064de..00000000000 --- a/sys/gnu/dts/arm/keystone-k2l-clocks.dtsi +++ /dev/null @@ -1,263 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Keystone 2 lamarr SoC clock nodes - * - * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/ - */ - -clocks { - armpllclk: armpllclk@2620370 { - #clock-cells = <0>; - compatible = "ti,keystone,pll-clock"; - clocks = <&refclksys>; - clock-output-names = "arm-pll-clk"; - reg = <0x02620370 4>; - reg-names = "control"; - }; - - mainpllclk: mainpllclk@2310110 { - #clock-cells = <0>; - compatible = "ti,keystone,main-pll-clock"; - clocks = <&refclksys>; - reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>; - reg-names = "control", "multiplier", "post-divider"; - }; - - papllclk: papllclk@2620358 { - #clock-cells = <0>; - compatible = "ti,keystone,pll-clock"; - clocks = <&refclksys>; - clock-output-names = "papllclk"; - reg = <0x02620358 4>; - reg-names = "control"; - }; - - ddr3apllclk: ddr3apllclk@2620360 { - #clock-cells = <0>; - compatible = "ti,keystone,pll-clock"; - clocks = <&refclksys>; - clock-output-names = "ddr-3a-pll-clk"; - reg = <0x02620360 4>; - reg-names = "control"; - }; - - clkdfeiqnsys: clkdfeiqnsys@2350004 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk12>; - clock-output-names = "dfe"; - reg-names = "control", "domain"; - reg = <0x02350004 0xb00>, <0x02350000 0x400>; - domain-id = <0>; - }; - - clkpcie1: clkpcie1@235002c { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk12>; - clock-output-names = "pcie"; - reg = <0x0235002c 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <4>; - }; - - clkgem1: clkgem1@2350040 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk1>; - clock-output-names = "gem1"; - reg = <0x02350040 0xb00>, <0x02350024 0x400>; - reg-names = "control", "domain"; - domain-id = <9>; - }; - - clkgem2: clkgem2@2350044 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk1>; - clock-output-names = "gem2"; - reg = <0x02350044 0xb00>, <0x02350028 0x400>; - reg-names = "control", "domain"; - domain-id = <10>; - }; - - clkgem3: clkgem3@2350048 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk1>; - clock-output-names = "gem3"; - reg = <0x02350048 0xb00>, <0x0235002c 0x400>; - reg-names = "control", "domain"; - domain-id = <11>; - }; - - clktac: clktac@2350064 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "tac"; - reg = <0x02350064 0xb00>, <0x02350044 0x400>; - reg-names = "control", "domain"; - domain-id = <17>; - }; - - clkrac: clkrac@2350068 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "rac"; - reg = <0x02350068 0xb00>, <0x02350044 0x400>; - reg-names = "control", "domain"; - domain-id = <17>; - }; - - clkdfepd0: clkdfepd0@235006c { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "dfe-pd0"; - reg = <0x0235006c 0xb00>, <0x02350044 0x400>; - reg-names = "control", "domain"; - domain-id = <18>; - }; - - clkfftc0: clkfftc0@2350070 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "fftc-0"; - reg = <0x02350070 0xb00>, <0x0235004c 0x400>; - reg-names = "control", "domain"; - domain-id = <19>; - }; - - clkosr: clkosr@2350088 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "osr"; - reg = <0x02350088 0xb00>, <0x0235004c 0x400>; - reg-names = "control", "domain"; - domain-id = <21>; - }; - - clktcp3d0: clktcp3d0@235008c { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "tcp3d-0"; - reg = <0x0235008c 0xb00>, <0x02350058 0x400>; - reg-names = "control", "domain"; - domain-id = <22>; - }; - - clktcp3d1: clktcp3d1@2350094 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "tcp3d-1"; - reg = <0x02350094 0xb00>, <0x02350058 0x400>; - reg-names = "control", "domain"; - domain-id = <23>; - }; - - clkvcp0: clkvcp0@235009c { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "vcp-0"; - reg = <0x0235009c 0xb00>, <0x02350060 0x400>; - reg-names = "control", "domain"; - domain-id = <24>; - }; - - clkvcp1: clkvcp1@23500a0 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "vcp-1"; - reg = <0x023500a0 0xb00>, <0x02350060 0x400>; - reg-names = "control", "domain"; - domain-id = <24>; - }; - - clkvcp2: clkvcp2@23500a4 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "vcp-2"; - reg = <0x023500a4 0xb00>, <0x02350060 0x400>; - reg-names = "control", "domain"; - domain-id = <24>; - }; - - clkvcp3: clkvcp3@23500a8 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "vcp-3"; - reg = <0x023500a8 0xb00>, <0x02350060 0x400>; - reg-names = "control", "domain"; - domain-id = <24>; - }; - - clkbcp: clkbcp@23500bc { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "bcp"; - reg = <0x023500bc 0xb00>, <0x02350068 0x400>; - reg-names = "control", "domain"; - domain-id = <26>; - }; - - clkdfepd1: clkdfepd1@23500c0 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "dfe-pd1"; - reg = <0x023500c0 0xb00>, <0x02350044 0x400>; - reg-names = "control", "domain"; - domain-id = <27>; - }; - - clkfftc1: clkfftc1@23500c4 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "fftc-1"; - reg = <0x023500c4 0xb00>, <0x023504c0 0x400>; - reg-names = "control", "domain"; - domain-id = <28>; - }; - - clkiqnail: clkiqnail@23500c8 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "iqn-ail"; - reg = <0x023500c8 0xb00>, <0x0235004c 0x400>; - reg-names = "control", "domain"; - domain-id = <29>; - }; - - clkuart2: clkuart2@2350000 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&clkmodrst0>; - clock-output-names = "uart2"; - reg = <0x02350000 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; - - clkuart3: clkuart3@2350000 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&clkmodrst0>; - clock-output-names = "uart3"; - reg = <0x02350000 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; -}; diff --git a/sys/gnu/dts/arm/keystone-k2l-evm.dts b/sys/gnu/dts/arm/keystone-k2l-evm.dts deleted file mode 100644 index e200533d26a..00000000000 --- a/sys/gnu/dts/arm/keystone-k2l-evm.dts +++ /dev/null @@ -1,165 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Keystone 2 Lamarr EVM device tree - * - * Copyright (C) 2014-2017 Texas Instruments Incorporated - http://www.ti.com/ - */ -/dts-v1/; - -#include "keystone.dtsi" -#include "keystone-k2l.dtsi" - -/ { - compatible = "ti,k2l-evm", "ti,k2l", "ti,keystone"; - model = "Texas Instruments Keystone 2 Lamarr EVM"; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - dsp_common_memory: dsp-common-memory@81f800000 { - compatible = "shared-dma-pool"; - reg = <0x00000008 0x1f800000 0x00000000 0x800000>; - reusable; - status = "okay"; - }; - }; -}; - -&soc0 { - clocks { - refclksys: refclksys { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <122880000>; - clock-output-names = "refclk-sys"; - }; - }; -}; - -&usb_phy { - status = "okay"; -}; - -&keystone_usb0 { - status = "okay"; -}; - -&usb0 { - dr_mode = "host"; -}; - -&i2c0 { - dtt@50 { - compatible = "atmel,24c1024"; - reg = <0x50>; - }; -}; - -&aemif { - cs0 { - #address-cells = <2>; - #size-cells = <1>; - clock-ranges; - ranges; - - ti,cs-chipselect = <0>; - /* all timings in nanoseconds */ - ti,cs-min-turnaround-ns = <12>; - ti,cs-read-hold-ns = <6>; - ti,cs-read-strobe-ns = <23>; - ti,cs-read-setup-ns = <9>; - ti,cs-write-hold-ns = <8>; - ti,cs-write-strobe-ns = <23>; - ti,cs-write-setup-ns = <8>; - - nand@0,0 { - compatible = "ti,keystone-nand","ti,davinci-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0 0 0x4000000 - 1 0 0x0000100>; - - ti,davinci-chipselect = <0>; - ti,davinci-mask-ale = <0x2000>; - ti,davinci-mask-cle = <0x4000>; - ti,davinci-mask-chipsel = <0>; - nand-ecc-mode = "hw"; - ti,davinci-ecc-bits = <4>; - nand-on-flash-bbt; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x100000>; - read-only; - }; - - partition@100000 { - label = "params"; - reg = <0x100000 0x80000>; - read-only; - }; - - partition@180000 { - label = "ubifs"; - reg = <0x180000 0x7FE80000>; - }; - }; - }; -}; - -&spi0 { - nor_flash: n25q128a11@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "Micron,n25q128a11"; - spi-max-frequency = <54000000>; - m25p,fast-read; - reg = <0>; - - partition@0 { - label = "u-boot-spl"; - reg = <0x0 0x80000>; - read-only; - }; - - partition@1 { - label = "misc"; - reg = <0x80000 0xf80000>; - }; - }; -}; - -&mdio { - status = "ok"; - ethphy0: ethernet-phy@0 { - compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22"; - reg = <0>; - }; - - ethphy1: ethernet-phy@1 { - compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; -}; - -&dsp0 { - memory-region = <&dsp_common_memory>; - status = "okay"; -}; - -&dsp1 { - memory-region = <&dsp_common_memory>; - status = "okay"; -}; - -&dsp2 { - memory-region = <&dsp_common_memory>; - status = "okay"; -}; - -&dsp3 { - memory-region = <&dsp_common_memory>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/keystone-k2l-netcp.dtsi b/sys/gnu/dts/arm/keystone-k2l-netcp.dtsi deleted file mode 100644 index c1f98260414..00000000000 --- a/sys/gnu/dts/arm/keystone-k2l-netcp.dtsi +++ /dev/null @@ -1,246 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for Keystone 2 Lamarr Netcp driver - * - * Copyright (C) 2015-2017 Texas Instruments Incorporated - http://www.ti.com/ - */ - -qmss: qmss@2a40000 { - compatible = "ti,keystone-navigator-qmss"; - dma-coherent; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&chipclk13>; - ranges; - queue-range = <0 0x2000>; - linkram0 = <0x100000 0x4000>; - linkram1 = <0x70000000 0x10000>; /* 1MB OSR mem */ - - qmgrs { - #address-cells = <1>; - #size-cells = <1>; - ranges; - qmgr0 { - managed-queues = <0 0x2000>; - reg = <0x2a40000 0x20000>, - <0x2a06000 0x400>, - <0x2a02000 0x1000>, - <0x2a03000 0x1000>, - <0x23a80000 0x20000>, - <0x2a80000 0x20000>; - reg-names = "peek", "status", "config", - "region", "push", "pop"; - }; - }; - queue-pools { - qpend { - qpend-0 { - qrange = <658 8>; - interrupts =<0 40 0xf04 0 41 0xf04 0 42 0xf04 - 0 43 0xf04 0 44 0xf04 0 45 0xf04 - 0 46 0xf04 0 47 0xf04>; - }; - qpend-1 { - qrange = <528 16>; - interrupts = <0 48 0xf04 0 49 0xf04 0 50 0xf04 - 0 51 0xf04 0 52 0xf04 0 53 0xf04 - 0 54 0xf04 0 55 0xf04 0 56 0xf04 - 0 57 0xf04 0 58 0xf04 0 59 0xf04 - 0 60 0xf04 0 61 0xf04 0 62 0xf04 - 0 63 0xf04>; - qalloc-by-id; - }; - qpend-2 { - qrange = <544 16>; - interrupts = <0 64 0xf04 0 65 0xf04 0 66 0xf04 - 0 59 0xf04 0 68 0xf04 0 69 0xf04 - 0 70 0xf04 0 71 0xf04 0 72 0xf04 - 0 73 0xf04 0 74 0xf04 0 75 0xf04 - 0 76 0xf04 0 77 0xf04 0 78 0xf04 - 0 79 0xf04>; - }; - }; - general-purpose { - gp-0 { - qrange = <4000 64>; - }; - netcp-tx { - qrange = <896 128>; - qalloc-by-id; - }; - }; - accumulator { - acc-low-0 { - qrange = <480 32>; - accumulator = <0 47 16 2 50>; - interrupts = <0 226 0xf01>; - multi-queue; - }; - }; - }; - - descriptor-regions { - #address-cells = <1>; - #size-cells = <1>; - ranges; - region-12 { - id = <12>; - region-spec = <8192 128>; /* num_desc desc_size */ - link-index = <0x4000>; - }; - }; - - pdsps { - #address-cells = <1>; - #size-cells = <1>; - ranges; - pdsp0@0x2a10000 { - reg = <0x2a10000 0x1000 /*iram */ - 0x2a0f000 0x100 /*reg*/ - 0x2a0c000 0x3c8 /*intd */ - 0x2a20000 0x4000>; /*cmd*/ - id = <0>; - }; - }; - -}; /* qmss */ - -knav_dmas: knav_dmas@0 { - compatible = "ti,keystone-navigator-dma"; - clocks = <&papllclk>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - ti,navigator-cloud-address = <0x23a80000 0x23a90000>; - - dma_gbe: dma_gbe@0 { - reg = <0x26186000 0x100>, - <0x26187000 0x2a0>, - <0x26188000 0xb60>, - <0x26186100 0x80>, - <0x26189000 0x1000>; - reg-names = "global", "txchan", "rxchan", - "txsched", "rxflow"; - }; -}; - -netcp: netcp@26000000 { - reg = <0x2620110 0x8>; - reg-names = "efuse"; - compatible = "ti,netcp-1.0"; - #address-cells = <1>; - #size-cells = <1>; - - /* NetCP address range */ - ranges = <0 0x26000000 0x1000000>; - - clocks = <&clkpa>, <&clkcpgmac>; - clock-names = "pa_clk", "ethss_clk"; - dma-coherent; - - ti,navigator-dmas = <&dma_gbe 0>, - <&dma_gbe 8>, - <&dma_gbe 0>; - ti,navigator-dma-names = "netrx0", "netrx1", "nettx"; - - netcp-devices { - #address-cells = <1>; - #size-cells = <1>; - ranges; - gbe@200000 { /* ETHSS */ - label = "netcp-gbe"; - compatible = "ti,netcp-gbe-5"; - reg = <0x200000 0x900>, <0x220000 0x20000>; - /* enable-ale; */ - tx-queue = <896>; - tx-channel = "nettx"; - - cpts { - clocks = <&cpts_refclk_mux>; - clock-names = "cpts"; - - cpts_refclk_mux: cpts-refclk-mux { - #clock-cells = <0>; - clocks = <&chipclk12>, <&chipclk13>, - <&timi0>, <&timi1>, - <&tsrefclk>; - ti,mux-tbl = <0x0>, <0x1>, <0x2>, - <0x3>, <0x8>; - assigned-clocks = <&cpts_refclk_mux>; - assigned-clock-parents = <&chipclk12>; - }; - }; - - interfaces { - gbe0: interface-0 { - slave-port = <0>; - link-interface = <1>; - phy-handle = <ðphy0>; - }; - gbe1: interface-1 { - slave-port = <1>; - link-interface = <1>; - phy-handle = <ðphy1>; - }; - }; - - secondary-slave-ports { - port-2 { - slave-port = <2>; - link-interface = <2>; - }; - port-3 { - slave-port = <3>; - link-interface = <2>; - }; - }; - }; - }; - - netcp-interfaces { - interface-0 { - rx-channel = "netrx0"; - rx-pool = <1024 12>; - tx-pool = <1024 12>; - rx-queue-depth = <128 128 0 0>; - rx-buffer-size = <1518 4096 0 0>; - rx-queue = <528>; - tx-completion-queue = <530>; - efuse-mac = <1>; - netcp-gbe = <&gbe0>; - - }; - interface-1 { - rx-channel = "netrx1"; - rx-pool = <1024 12>; - tx-pool = <1024 12>; - rx-queue-depth = <128 128 0 0>; - rx-buffer-size = <1518 4096 0 0>; - rx-queue = <529>; - tx-completion-queue = <531>; - efuse-mac = <0>; - local-mac-address = [02 18 31 7e 3e 7f]; - netcp-gbe = <&gbe1>; - }; - }; -}; - -sa_subsys: subsys@26080000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0 0x26080000 0x40000>; - - sa_config: subsys@0 { - compatible = "syscon"; - reg = <0x0 0x100>; - }; - - rng@24000 { - compatible = "ti,keystone-rng"; - reg = <0x24000 0x1000>; - ti,syscon-sa-cfg = <&sa_config>; - clocks = <&clksa>; - clock-names = "fck"; - }; -}; diff --git a/sys/gnu/dts/arm/keystone-k2l.dtsi b/sys/gnu/dts/arm/keystone-k2l.dtsi deleted file mode 100644 index 374c80124c4..00000000000 --- a/sys/gnu/dts/arm/keystone-k2l.dtsi +++ /dev/null @@ -1,415 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Keystone 2 Lamarr SoC specific device tree - * - * Copyright (C) 2014-2017 Texas Instruments Incorporated - http://www.ti.com/ - */ - -#include - -/ { - compatible = "ti,k2l", "ti,keystone"; - model = "Texas Instruments Keystone 2 Lamarr SoC"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - interrupt-parent = <&gic>; - - cpu@0 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <0>; - }; - - cpu@1 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <1>; - }; - }; - - aliases { - rproc0 = &dsp0; - rproc1 = &dsp1; - rproc2 = &dsp2; - rproc3 = &dsp3; - }; -}; - -&soc0 { - /include/ "keystone-k2l-clocks.dtsi" - - uart2: serial@2348400 { - compatible = "ti,da830-uart", "ns16550a"; - current-speed = <115200>; - reg-shift = <2>; - reg-io-width = <4>; - reg = <0x02348400 0x100>; - clocks = <&clkuart2>; - interrupts = ; - }; - - uart3: serial@2348800 { - compatible = "ti,da830-uart", "ns16550a"; - current-speed = <115200>; - reg-shift = <2>; - reg-io-width = <4>; - reg = <0x02348800 0x100>; - clocks = <&clkuart3>; - interrupts = ; - }; - - gpio1: gpio@2348000 { - compatible = "ti,keystone-gpio"; - reg = <0x02348000 0x100>; - gpio-controller; - #gpio-cells = <2>; - /* HW Interrupts mapped to GPIO pins */ - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - clocks = <&clkgpio>; - clock-names = "gpio"; - ti,ngpio = <32>; - ti,davinci-gpio-unbanked = <32>; - }; - - k2l_pmx: pinmux@2620690 { - compatible = "pinctrl-single"; - reg = <0x02620690 0xc>; - #address-cells = <1>; - #size-cells = <0>; - #pinctrl-cells = <2>; - pinctrl-single,bit-per-mux; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0x1>; - status = "disabled"; - - uart3_emifa_pins: pinmux_uart3_emifa_pins { - pinctrl-single,bits = < - /* UART3_EMIFA_SEL */ - 0x0 0x0 0xc0 - >; - }; - - uart2_emifa_pins: pinmux_uart2_emifa_pins { - pinctrl-single,bits = < - /* UART2_EMIFA_SEL */ - 0x0 0x0 0x30 - >; - }; - - uart01_spi2_pins: pinmux_uart01_spi2_pins { - pinctrl-single,bits = < - /* UART01_SPI2_SEL */ - 0x0 0x0 0x4 - >; - }; - - dfesync_rp1_pins: pinmux_dfesync_rp1_pins{ - pinctrl-single,bits = < - /* DFESYNC_RP1_SEL */ - 0x0 0x0 0x2 - >; - }; - - avsif_pins: pinmux_avsif_pins { - pinctrl-single,bits = < - /* AVSIF_SEL */ - 0x0 0x0 0x1 - >; - }; - - gpio_emu_pins: pinmux_gpio_emu_pins { - pinctrl-single,bits = < - /* - * GPIO_EMU_SEL[31]: 0-GPIO31, 1-EMU33 - * GPIO_EMU_SEL[30]: 0-GPIO30, 1-EMU32 - * GPIO_EMU_SEL[29]: 0-GPIO29, 1-EMU31 - * GPIO_EMU_SEL[28]: 0-GPIO28, 1-EMU30 - * GPIO_EMU_SEL[27]: 0-GPIO27, 1-EMU29 - * GPIO_EMU_SEL[26]: 0-GPIO26, 1-EMU28 - * GPIO_EMU_SEL[25]: 0-GPIO25, 1-EMU27 - * GPIO_EMU_SEL[24]: 0-GPIO24, 1-EMU26 - * GPIO_EMU_SEL[23]: 0-GPIO23, 1-EMU25 - * GPIO_EMU_SEL[22]: 0-GPIO22, 1-EMU24 - * GPIO_EMU_SEL[21]: 0-GPIO21, 1-EMU23 - * GPIO_EMU_SEL[20]: 0-GPIO20, 1-EMU22 - * GPIO_EMU_SEL[19]: 0-GPIO19, 1-EMU21 - * GPIO_EMU_SEL[18]: 0-GPIO18, 1-EMU20 - * GPIO_EMU_SEL[17]: 0-GPIO17, 1-EMU19 - */ - 0x4 0x0000 0xFFFE0000 - >; - }; - - gpio_timio_pins: pinmux_gpio_timio_pins { - pinctrl-single,bits = < - /* - * GPIO_TIMIO_SEL[15]: 0-GPIO15, 1-TIMO7 - * GPIO_TIMIO_SEL[14]: 0-GPIO14, 1-TIMO6 - * GPIO_TIMIO_SEL[13]: 0-GPIO13, 1-TIMO5 - * GPIO_TIMIO_SEL[12]: 0-GPIO12, 1-TIMO4 - * GPIO_TIMIO_SEL[11]: 0-GPIO11, 1-TIMO3 - * GPIO_TIMIO_SEL[10]: 0-GPIO10, 1-TIMO2 - * GPIO_TIMIO_SEL[9]: 0-GPIO9, 1-TIMI7 - * GPIO_TIMIO_SEL[8]: 0-GPIO8, 1-TIMI6 - * GPIO_TIMIO_SEL[7]: 0-GPIO7, 1-TIMI5 - * GPIO_TIMIO_SEL[6]: 0-GPIO6, 1-TIMI4 - * GPIO_TIMIO_SEL[5]: 0-GPIO5, 1-TIMI3 - * GPIO_TIMIO_SEL[4]: 0-GPIO4, 1-TIMI2 - */ - 0x4 0x0 0xFFF0 - >; - }; - - gpio_spi2cs_pins: pinmux_gpio_spi2cs_pins { - pinctrl-single,bits = < - /* - * GPIO_SPI2CS_SEL[3]: 0-GPIO3, 1-SPI2CS4 - * GPIO_SPI2CS_SEL[2]: 0-GPIO2, 1-SPI2CS3 - * GPIO_SPI2CS_SEL[1]: 0-GPIO1, 1-SPI2CS2 - * GPIO_SPI2CS_SEL[0]: 0-GPIO0, 1-SPI2CS1 - */ - 0x4 0x0 0xF - >; - }; - - gpio_dfeio_pins: pinmux_gpio_dfeio_pins { - pinctrl-single,bits = < - /* - * GPIO_DFEIO_SEL[31]: 0-DFEIO17, 1-GPIO63 - * GPIO_DFEIO_SEL[30]: 0-DFEIO16, 1-GPIO62 - * GPIO_DFEIO_SEL[29]: 0-DFEIO15, 1-GPIO61 - * GPIO_DFEIO_SEL[28]: 0-DFEIO14, 1-GPIO60 - * GPIO_DFEIO_SEL[27]: 0-DFEIO13, 1-GPIO59 - * GPIO_DFEIO_SEL[26]: 0-DFEIO12, 1-GPIO58 - * GPIO_DFEIO_SEL[25]: 0-DFEIO11, 1-GPIO57 - * GPIO_DFEIO_SEL[24]: 0-DFEIO10, 1-GPIO56 - * GPIO_DFEIO_SEL[23]: 0-DFEIO9, 1-GPIO55 - * GPIO_DFEIO_SEL[22]: 0-DFEIO8, 1-GPIO54 - * GPIO_DFEIO_SEL[21]: 0-DFEIO7, 1-GPIO53 - * GPIO_DFEIO_SEL[20]: 0-DFEIO6, 1-GPIO52 - * GPIO_DFEIO_SEL[19]: 0-DFEIO5, 1-GPIO51 - * GPIO_DFEIO_SEL[18]: 0-DFEIO4, 1-GPIO50 - * GPIO_DFEIO_SEL[17]: 0-DFEIO3, 1-GPIO49 - * GPIO_DFEIO_SEL[16]: 0-DFEIO2, 1-GPIO48 - */ - 0x8 0x0 0xFFFF0000 - >; - }; - - gpio_emifa_pins: pinmux_gpio_emifa_pins { - pinctrl-single,bits = < - /* - * GPIO_EMIFA_SEL[15]: 0-EMIFA17, 1-GPIO47 - * GPIO_EMIFA_SEL[14]: 0-EMIFA16, 1-GPIO46 - * GPIO_EMIFA_SEL[13]: 0-EMIFA15, 1-GPIO45 - * GPIO_EMIFA_SEL[12]: 0-EMIFA14, 1-GPIO44 - * GPIO_EMIFA_SEL[11]: 0-EMIFA13, 1-GPIO43 - * GPIO_EMIFA_SEL[10]: 0-EMIFA10, 1-GPIO42 - * GPIO_EMIFA_SEL[9]: 0-EMIFA9, 1-GPIO41 - * GPIO_EMIFA_SEL[8]: 0-EMIFA8, 1-GPIO40 - * GPIO_EMIFA_SEL[7]: 0-EMIFA7, 1-GPIO39 - * GPIO_EMIFA_SEL[6]: 0-EMIFA6, 1-GPIO38 - * GPIO_EMIFA_SEL[5]: 0-EMIFA5, 1-GPIO37 - * GPIO_EMIFA_SEL[4]: 0-EMIFA4, 1-GPIO36 - * GPIO_EMIFA_SEL[3]: 0-EMIFA3, 1-GPIO35 - * GPIO_EMIFA_SEL[2]: 0-EMIFA2, 1-GPIO34 - * GPIO_EMIFA_SEL[1]: 0-EMIFA1, 1-GPIO33 - * GPIO_EMIFA_SEL[0]: 0-EMIFA0, 1-GPIO32 - */ - 0x8 0x0 0xFFFF - >; - }; - }; - - msm_ram: msmram@c000000 { - compatible = "mmio-sram"; - reg = <0x0c000000 0x200000>; - ranges = <0x0 0x0c000000 0x200000>; - #address-cells = <1>; - #size-cells = <1>; - - sram-bm@1f8000 { - reg = <0x001f8000 0x8000>; - }; - }; - - psc: power-sleep-controller@2350000 { - pscrst: reset-controller { - compatible = "ti,k2l-pscrst", "ti,syscon-reset"; - #reset-cells = <1>; - - ti,reset-bits = < - 0xa3c 8 0xa3c 8 0x83c 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 0: dsp0 */ - 0xa40 8 0xa40 8 0x840 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 1: dsp1 */ - 0xa44 8 0xa44 8 0x844 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 2: dsp2 */ - 0xa48 8 0xa48 8 0x848 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 3: dsp3 */ - >; - }; - }; - - osr: sram@70000000 { - compatible = "mmio-sram"; - reg = <0x70000000 0x10000>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&clkosr>; - }; - - devctrl: device-state-control@2620000 { - dspgpio0: keystone_dsp_gpio@240 { - compatible = "ti,keystone-dsp-gpio"; - reg = <0x240 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio,syscon-dev = <&devctrl 0x240>; - }; - - dspgpio1: keystone_dsp_gpio@244 { - compatible = "ti,keystone-dsp-gpio"; - reg = <0x244 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio,syscon-dev = <&devctrl 0x244>; - }; - - dspgpio2: keystone_dsp_gpio@248 { - compatible = "ti,keystone-dsp-gpio"; - reg = <0x248 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio,syscon-dev = <&devctrl 0x248>; - }; - - dspgpio3: keystone_dsp_gpio@24c { - compatible = "ti,keystone-dsp-gpio"; - reg = <0x24c 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio,syscon-dev = <&devctrl 0x24c>; - }; - }; - - dsp0: dsp@10800000 { - compatible = "ti,k2l-dsp"; - reg = <0x10800000 0x00100000>, - <0x10e00000 0x00008000>, - <0x10f00000 0x00008000>; - reg-names = "l2sram", "l1pram", "l1dram"; - clocks = <&clkgem0>; - ti,syscon-dev = <&devctrl 0x844>; - resets = <&pscrst 0>; - interrupt-parent = <&kirq0>; - interrupts = <0 8>; - interrupt-names = "vring", "exception"; - kick-gpios = <&dspgpio0 27 0>; - status = "disabled"; - }; - - dsp1: dsp@11800000 { - compatible = "ti,k2l-dsp"; - reg = <0x11800000 0x00100000>, - <0x11e00000 0x00008000>, - <0x11f00000 0x00008000>; - reg-names = "l2sram", "l1pram", "l1dram"; - clocks = <&clkgem1>; - ti,syscon-dev = <&devctrl 0x848>; - resets = <&pscrst 1>; - interrupt-parent = <&kirq0>; - interrupts = <1 9>; - interrupt-names = "vring", "exception"; - kick-gpios = <&dspgpio1 27 0>; - status = "disabled"; - }; - - dsp2: dsp@12800000 { - compatible = "ti,k2l-dsp"; - reg = <0x12800000 0x00100000>, - <0x12e00000 0x00008000>, - <0x12f00000 0x00008000>; - reg-names = "l2sram", "l1pram", "l1dram"; - clocks = <&clkgem2>; - ti,syscon-dev = <&devctrl 0x84c>; - resets = <&pscrst 2>; - interrupt-parent = <&kirq0>; - interrupts = <2 10>; - interrupt-names = "vring", "exception"; - kick-gpios = <&dspgpio2 27 0>; - status = "disabled"; - }; - - dsp3: dsp@13800000 { - compatible = "ti,k2l-dsp"; - reg = <0x13800000 0x00100000>, - <0x13e00000 0x00008000>, - <0x13f00000 0x00008000>; - reg-names = "l2sram", "l1pram", "l1dram"; - clocks = <&clkgem3>; - ti,syscon-dev = <&devctrl 0x850>; - resets = <&pscrst 3>; - interrupt-parent = <&kirq0>; - interrupts = <3 11>; - interrupt-names = "vring", "exception"; - kick-gpios = <&dspgpio3 27 0>; - status = "disabled"; - }; - - mdio: mdio@26200f00 { - compatible = "ti,keystone_mdio", "ti,davinci_mdio"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x26200f00 0x100>; - status = "disabled"; - clocks = <&clkcpgmac>; - clock-names = "fck"; - bus_freq = <2500000>; - }; - /include/ "keystone-k2l-netcp.dtsi" -}; - -&spi0 { - ti,davinci-spi-num-cs = <5>; -}; - -&spi1 { - ti,davinci-spi-num-cs = <3>; -}; - -&spi2 { - ti,davinci-spi-num-cs = <5>; - /* Pin muxed. Enabled and configured by Bootloader */ - status = "disabled"; -}; diff --git a/sys/gnu/dts/arm/keystone.dtsi b/sys/gnu/dts/arm/keystone.dtsi deleted file mode 100644 index c298675a29a..00000000000 --- a/sys/gnu/dts/arm/keystone.dtsi +++ /dev/null @@ -1,354 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/ - */ - -#include -#include - -/ { - compatible = "ti,keystone"; - model = "Texas Instruments Keystone 2 SoC"; - #address-cells = <2>; - #size-cells = <2>; - interrupt-parent = <&gic>; - - aliases { - serial0 = &uart0; - spi0 = &spi0; - spi1 = &spi1; - spi2 = &spi2; - }; - - chosen { }; - - memory: memory@80000000 { - device_type = "memory"; - reg = <0x00000000 0x80000000 0x00000000 0x40000000>; - }; - - gic: interrupt-controller@2561000 { - compatible = "arm,gic-400", "arm,cortex-a15-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x0 0x02561000 0x0 0x1000>, - <0x0 0x02562000 0x0 0x2000>, - <0x0 0x02564000 0x0 0x2000>, - <0x0 0x02566000 0x0 0x2000>; - interrupts = ; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = - , - , - , - ; - }; - - pmu { - compatible = "arm,cortex-a15-pmu"; - interrupts = , - , - , - ; - }; - - psci { - compatible = "arm,psci"; - method = "smc"; - cpu_suspend = <0x84000001>; - cpu_off = <0x84000002>; - cpu_on = <0x84000003>; - }; - - soc0: soc@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "ti,keystone","simple-bus"; - interrupt-parent = <&gic>; - ranges = <0x0 0x0 0x0 0xc0000000>; - dma-ranges = <0x80000000 0x8 0x00000000 0x80000000>; - - pllctrl: pll-controller@2310000 { - compatible = "ti,keystone-pllctrl", "syscon"; - reg = <0x02310000 0x200>; - }; - - psc: power-sleep-controller@2350000 { - compatible = "syscon", "simple-mfd"; - reg = <0x02350000 0x1000>; - }; - - devctrl: device-state-control@2620000 { - compatible = "ti,keystone-devctrl", "syscon", "simple-mfd"; - reg = <0x02620000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x02620000 0x1000>; - - kirq0: keystone_irq@2a0 { - compatible = "ti,keystone-irq"; - reg = <0x2a0 0x4>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <1>; - ti,syscon-dev = <&devctrl 0x2a0>; - }; - - rstctrl: reset-controller@328 { - compatible = "ti,keystone-reset"; - reg = <0x328 0x10>; - ti,syscon-pll = <&pllctrl 0xe4>; - ti,syscon-dev = <&devctrl 0x328>; - ti,wdt-list = <0>; - }; - }; - - /include/ "keystone-clocks.dtsi" - - uart0: serial@2530c00 { - compatible = "ti,da830-uart", "ns16550a"; - current-speed = <115200>; - reg-shift = <2>; - reg-io-width = <4>; - reg = <0x02530c00 0x100>; - clocks = <&clkuart0>; - interrupts = ; - }; - - uart1: serial@2531000 { - compatible = "ti,da830-uart", "ns16550a"; - current-speed = <115200>; - reg-shift = <2>; - reg-io-width = <4>; - reg = <0x02531000 0x100>; - clocks = <&clkuart1>; - interrupts = ; - }; - - i2c0: i2c@2530000 { - compatible = "ti,davinci-i2c"; - reg = <0x02530000 0x400>; - clock-frequency = <100000>; - clocks = <&clki2c>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c1: i2c@2530400 { - compatible = "ti,davinci-i2c"; - reg = <0x02530400 0x400>; - clock-frequency = <100000>; - clocks = <&clki2c>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c2: i2c@2530800 { - compatible = "ti,davinci-i2c"; - reg = <0x02530800 0x400>; - clock-frequency = <100000>; - clocks = <&clki2c>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - }; - - spi0: spi@21000400 { - compatible = "ti,keystone-spi", "ti,dm6441-spi"; - reg = <0x21000400 0x200>; - num-cs = <4>; - ti,davinci-spi-intr-line = <0>; - interrupts = ; - clocks = <&clkspi>; - #address-cells = <1>; - #size-cells = <0>; - }; - - spi1: spi@21000600 { - compatible = "ti,keystone-spi", "ti,dm6441-spi"; - reg = <0x21000600 0x200>; - num-cs = <4>; - ti,davinci-spi-intr-line = <0>; - interrupts = ; - clocks = <&clkspi>; - #address-cells = <1>; - #size-cells = <0>; - }; - - spi2: spi@21000800 { - compatible = "ti,keystone-spi", "ti,dm6441-spi"; - reg = <0x21000800 0x200>; - num-cs = <4>; - ti,davinci-spi-intr-line = <0>; - interrupts = ; - clocks = <&clkspi>; - #address-cells = <1>; - #size-cells = <0>; - }; - - usb_phy: usb_phy@2620738 { - compatible = "ti,keystone-usbphy"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x2620738 24>; - status = "disabled"; - }; - - keystone_usb0: usb@2680000 { - compatible = "ti,keystone-dwc3"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x2680000 0x10000>; - clocks = <&clkusb>; - clock-names = "usb"; - interrupts = ; - ranges; - dma-coherent; - dma-ranges; - status = "disabled"; - - usb0: dwc3@2690000 { - compatible = "synopsys,dwc3"; - reg = <0x2690000 0x70000>; - interrupts = ; - usb-phy = <&usb_phy>, <&usb_phy>; - }; - }; - - wdt: wdt@22f0080 { - compatible = "ti,keystone-wdt","ti,davinci-wdt"; - reg = <0x022f0080 0x80>; - clocks = <&clkwdtimer0>; - }; - - clock_event: timer@22f0000 { - compatible = "ti,keystone-timer"; - reg = <0x022f0000 0x80>; - interrupts = ; - clocks = <&clktimer15>; - }; - - gpio0: gpio@260bf00 { - compatible = "ti,keystone-gpio"; - reg = <0x0260bf00 0x100>; - gpio-controller; - #gpio-cells = <2>; - /* HW Interrupts mapped to GPIO pins */ - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - clocks = <&clkgpio>; - clock-names = "gpio"; - ti,ngpio = <32>; - ti,davinci-gpio-unbanked = <32>; - }; - - aemif: aemif@21000A00 { - compatible = "ti,keystone-aemif", "ti,davinci-aemif"; - #address-cells = <2>; - #size-cells = <1>; - clocks = <&clkaemif>; - clock-names = "aemif"; - clock-ranges; - - reg = <0x21000A00 0x00000100>; - ranges = <0 0 0x30000000 0x10000000 - 1 0 0x21000A00 0x00000100>; - }; - - pcie0: pcie@21800000 { - compatible = "ti,keystone-pcie", "snps,dw-pcie"; - clocks = <&clkpcie>; - clock-names = "pcie"; - #address-cells = <3>; - #size-cells = <2>; - reg = <0x21801000 0x2000>, <0x21800000 0x1000>, <0x02620128 4>; - ranges = <0x82000000 0 0x50000000 0x50000000 - 0 0x10000000>; - - status = "disabled"; - device_type = "pci"; - num-lanes = <2>; - bus-range = <0x00 0xff>; - - /* error interrupt */ - interrupts = ; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie_intc0 0>, /* INT A */ - <0 0 0 2 &pcie_intc0 1>, /* INT B */ - <0 0 0 3 &pcie_intc0 2>, /* INT C */ - <0 0 0 4 &pcie_intc0 3>; /* INT D */ - - pcie_msi_intc0: msi-interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - interrupt-parent = <&gic>; - interrupts = , - , - , - , - , - , - , - ; - }; - - pcie_intc0: legacy-interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - interrupt-parent = <&gic>; - interrupts = , - , - , - ; - }; - }; - - emif: emif@21010000 { - compatible = "ti,emif-keystone"; - reg = <0x21010000 0x200>; - interrupts = ; - interrupt-parent = <&gic>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/kirkwood-6192.dtsi b/sys/gnu/dts/arm/kirkwood-6192.dtsi deleted file mode 100644 index 396bcba08ad..00000000000 --- a/sys/gnu/dts/arm/kirkwood-6192.dtsi +++ /dev/null @@ -1,88 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/ { - mbus@f1000000 { - pciec: pcie@82000000 { - compatible = "marvell,kirkwood-pcie"; - status = "disabled"; - device_type = "pci"; - - #address-cells = <3>; - #size-cells = <2>; - - bus-range = <0x00 0xff>; - - ranges = - <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 - 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ - 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>; - - pcie0: pcie@1,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>; - reg = <0x0800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 - 0x81000000 0 0 0x81000000 0x1 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &intc 9>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <0>; - clocks = <&gate_clk 2>; - status = "disabled"; - }; - }; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - compatible = "marvell,88f6192-pinctrl"; - - pmx_sata0: pmx-sata0 { - marvell,pins = "mpp5", "mpp21", "mpp23"; - marvell,function = "sata0"; - }; - pmx_sata1: pmx-sata1 { - marvell,pins = "mpp4", "mpp20", "mpp22"; - marvell,function = "sata1"; - }; - pmx_sdio: pmx-sdio { - marvell,pins = "mpp12", "mpp13", "mpp14", - "mpp15", "mpp16", "mpp17"; - marvell,function = "sdio"; - }; - }; - - rtc: rtc@10300 { - compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc"; - reg = <0x10300 0x20>; - interrupts = <53>; - clocks = <&gate_clk 7>; - }; - - sata: sata@80000 { - compatible = "marvell,orion-sata"; - reg = <0x80000 0x5000>; - interrupts = <21>; - clocks = <&gate_clk 14>, <&gate_clk 15>; - clock-names = "0", "1"; - phys = <&sata_phy0>, <&sata_phy1>; - phy-names = "port0", "port1"; - status = "disabled"; - }; - - sdio: mvsdio@90000 { - compatible = "marvell,orion-sdio"; - reg = <0x90000 0x200>; - interrupts = <28>; - clocks = <&gate_clk 4>; - bus-width = <4>; - cap-sdio-irq; - cap-sd-highspeed; - cap-mmc-highspeed; - status = "disabled"; - }; - }; -}; diff --git a/sys/gnu/dts/arm/kirkwood-6281.dtsi b/sys/gnu/dts/arm/kirkwood-6281.dtsi deleted file mode 100644 index faa05849a40..00000000000 --- a/sys/gnu/dts/arm/kirkwood-6281.dtsi +++ /dev/null @@ -1,90 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/ { - mbus@f1000000 { - pciec: pcie@82000000 { - compatible = "marvell,kirkwood-pcie"; - status = "disabled"; - device_type = "pci"; - - #address-cells = <3>; - #size-cells = <2>; - - bus-range = <0x00 0xff>; - - ranges = - <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 - 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ - 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>; - - pcie0: pcie@1,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>; - reg = <0x0800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 - 0x81000000 0 0 0x81000000 0x1 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &intc 9>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <0>; - clocks = <&gate_clk 2>; - status = "disabled"; - }; - }; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - compatible = "marvell,88f6281-pinctrl"; - - pmx_sata0: pmx-sata0 { - marvell,pins = "mpp5", "mpp21", "mpp23"; - marvell,function = "sata0"; - }; - pmx_sata1: pmx-sata1 { - marvell,pins = "mpp4", "mpp20", "mpp22"; - marvell,function = "sata1"; - }; - pmx_sdio: pmx-sdio { - marvell,pins = "mpp12", "mpp13", "mpp14", - "mpp15", "mpp16", "mpp17"; - marvell,function = "sdio"; - }; - }; - - rtc: rtc@10300 { - compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc"; - reg = <0x10300 0x20>; - interrupts = <53>; - clocks = <&gate_clk 7>; - }; - - sata: sata@80000 { - compatible = "marvell,orion-sata"; - reg = <0x80000 0x5000>; - interrupts = <21>; - clocks = <&gate_clk 14>, <&gate_clk 15>; - clock-names = "0", "1"; - phys = <&sata_phy0>, <&sata_phy1>; - phy-names = "port0", "port1"; - status = "disabled"; - }; - - sdio: mvsdio@90000 { - compatible = "marvell,orion-sdio"; - reg = <0x90000 0x200>; - interrupts = <28>; - clocks = <&gate_clk 4>; - pinctrl-0 = <&pmx_sdio>; - pinctrl-names = "default"; - bus-width = <4>; - cap-sdio-irq; - cap-sd-highspeed; - cap-mmc-highspeed; - status = "disabled"; - }; - }; -}; diff --git a/sys/gnu/dts/arm/kirkwood-6282.dtsi b/sys/gnu/dts/arm/kirkwood-6282.dtsi deleted file mode 100644 index e84c54b77de..00000000000 --- a/sys/gnu/dts/arm/kirkwood-6282.dtsi +++ /dev/null @@ -1,141 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/ { - mbus@f1000000 { - pciec: pcie@82000000 { - compatible = "marvell,kirkwood-pcie"; - status = "disabled"; - device_type = "pci"; - - #address-cells = <3>; - #size-cells = <2>; - - bus-range = <0x00 0xff>; - - ranges = - <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 - 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 - 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 - 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ - 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ - 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1.0 MEM */ - 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1.0 IO */>; - - pcie0: pcie@1,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>; - reg = <0x0800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 - 0x81000000 0 0 0x81000000 0x1 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &intc 9>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <0>; - clocks = <&gate_clk 2>; - status = "disabled"; - }; - - pcie1: pcie@2,0 { - device_type = "pci"; - assigned-addresses = <0x82001000 0 0x00044000 0 0x2000>; - reg = <0x1000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 - 0x81000000 0 0 0x81000000 0x2 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &intc 10>; - marvell,pcie-port = <1>; - marvell,pcie-lane = <0>; - clocks = <&gate_clk 18>; - status = "disabled"; - }; - }; - }; - ocp@f1000000 { - - pinctrl: pin-controller@10000 { - compatible = "marvell,88f6282-pinctrl"; - - pmx_sata0: pmx-sata0 { - marvell,pins = "mpp5", "mpp21", "mpp23"; - marvell,function = "sata0"; - }; - pmx_sata1: pmx-sata1 { - marvell,pins = "mpp4", "mpp20", "mpp22"; - marvell,function = "sata1"; - }; - - /* - * Default I2C1 pinctrl setting on mpp36/mpp37, - * overwrite marvell,pins on board level if required. - */ - pmx_twsi1: pmx-twsi1 { - marvell,pins = "mpp36", "mpp37"; - marvell,function = "twsi1"; - }; - - pmx_sdio: pmx-sdio { - marvell,pins = "mpp12", "mpp13", "mpp14", - "mpp15", "mpp16", "mpp17"; - marvell,function = "sdio"; - }; - }; - - thermal: thermal@10078 { - compatible = "marvell,kirkwood-thermal"; - reg = <0x10078 0x4>; - status = "okay"; - }; - - rtc: rtc@10300 { - compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc"; - reg = <0x10300 0x20>; - interrupts = <53>; - clocks = <&gate_clk 7>; - }; - - i2c1: i2c@11100 { - compatible = "marvell,mv64xxx-i2c"; - reg = <0x11100 0x20>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <32>; - clock-frequency = <100000>; - clocks = <&gate_clk 7>; - pinctrl-0 = <&pmx_twsi1>; - pinctrl-names = "default"; - status = "disabled"; - }; - - sata: sata@80000 { - compatible = "marvell,orion-sata"; - reg = <0x80000 0x5000>; - interrupts = <21>; - clocks = <&gate_clk 14>, <&gate_clk 15>; - clock-names = "0", "1"; - phys = <&sata_phy0>, <&sata_phy1>; - phy-names = "port0", "port1"; - status = "disabled"; - }; - - sdio: mvsdio@90000 { - compatible = "marvell,orion-sdio"; - reg = <0x90000 0x200>; - interrupts = <28>; - clocks = <&gate_clk 4>; - pinctrl-0 = <&pmx_sdio>; - pinctrl-names = "default"; - bus-width = <4>; - cap-sdio-irq; - cap-sd-highspeed; - cap-mmc-highspeed; - status = "disabled"; - }; - }; -}; diff --git a/sys/gnu/dts/arm/kirkwood-98dx4122.dtsi b/sys/gnu/dts/arm/kirkwood-98dx4122.dtsi deleted file mode 100644 index 299c147298c..00000000000 --- a/sys/gnu/dts/arm/kirkwood-98dx4122.dtsi +++ /dev/null @@ -1,53 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/ { - mbus@f1000000 { - pciec: pcie@82000000 { - compatible = "marvell,kirkwood-pcie"; - status = "disabled"; - device_type = "pci"; - - #address-cells = <3>; - #size-cells = <2>; - - bus-range = <0x00 0xff>; - - ranges = - <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 - 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ - 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>; - - pcie0: pcie@1,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>; - reg = <0x0800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 - 0x81000000 0 0 0x81000000 0x1 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &intc 9>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <0>; - clocks = <&gate_clk 2>; - status = "disabled"; - }; - }; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - compatible = "marvell,98dx4122-pinctrl"; - - }; - }; -}; - -&sata_phy0 { - status = "disabled"; -}; - -&sata_phy1 { - status = "disabled"; -}; diff --git a/sys/gnu/dts/arm/kirkwood-b3.dts b/sys/gnu/dts/arm/kirkwood-b3.dts deleted file mode 100644 index 17f48f88a98..00000000000 --- a/sys/gnu/dts/arm/kirkwood-b3.dts +++ /dev/null @@ -1,195 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Device Tree file for Excito Bubba B3 - * - * Copyright (C) 2013, Andrew Lunn - * - * - * Note: This requires a new'ish version of u-boot, which disables the - * L2 cache. If your B3 silently fails to boot, u-boot is probably too - * old. Either upgrade, or consider the following email: - * - * http://lists.debian.org/debian-arm/2012/08/msg00128.html - */ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - model = "Excito B3"; - compatible = "excito,b3", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - memory { /* 512 MB */ - device_type = "memory"; - reg = <0x00000000 0x20000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pmx_button_power: pmx-button-power { - marvell,pins = "mpp39"; - marvell,function = "gpio"; - }; - pmx_led_green: pmx-led-green { - marvell,pins = "mpp38"; - marvell,function = "gpio"; - }; - pmx_led_red: pmx-led-red { - marvell,pins = "mpp41"; - marvell,function = "gpio"; - }; - pmx_led_blue: pmx-led-blue { - marvell,pins = "mpp42"; - marvell,function = "gpio"; - }; - pmx_beeper: pmx-beeper { - marvell,pins = "mpp40"; - marvell,function = "gpio"; - }; - }; - - spi@10600 { - status = "okay"; - - m25p16@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,m25p16", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <40000000>; - mode = <0>; - - partition@0 { - reg = <0x0 0xc0000>; - label = "u-boot"; - }; - - partition@c0000 { - reg = <0xc0000 0x20000>; - label = "u-boot env"; - }; - - partition@e0000 { - reg = <0xe0000 0x120000>; - label = "data"; - }; - }; - }; - - i2c@11000 { - status = "okay"; - /* - * There is something on the bus at address 0x64. - * Not yet identified what it is, maybe the eeprom - * for the Atheros WiFi chip? - */ - }; - - - serial@12000 { - /* Internal on test pins, 3.3v TTL - * UART0_RX = Testpoint 65 - * UART0_TX = Testpoint 66 - * See the Excito Wiki for more details. - */ - status = "okay"; - }; - - sata@80000 { - /* One internal, the second as eSATA */ - status = "okay"; - nr-ports = <2>; - }; - }; - - gpio-leds { - /* - * There is one LED "port" on the front and the colours - * mix together giving some interesting combinations. - */ - compatible = "gpio-leds"; - pinctrl-0 = < &pmx_led_green &pmx_led_red - &pmx_led_blue >; - pinctrl-names = "default"; - - programming_led { - label = "bubba3:green:programming"; - gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - error_led { - label = "bubba3:red:error"; - gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; - }; - - active_led { - label = "bubba3:blue:active"; - gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-0 = <&pmx_button_power>; - pinctrl-names = "default"; - - power-button { - /* On the back */ - label = "Power Button"; - linux,code = ; - gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; - }; - }; - - beeper: beeper { - /* 4KHz Piezoelectric buzzer */ - compatible = "gpio-beeper"; - pinctrl-0 = <&pmx_beeper>; - pinctrl-names = "default"; - gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@8 { - device_type = "ethernet-phy"; - reg = <8>; - }; - - ethphy1: ethernet-phy@24 { - device_type = "ethernet-phy"; - reg = <24>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; - -ð1 { - status = "okay"; - ethernet1-port@0 { - phy-handle = <ðphy1>; - }; -}; - -/* Wifi model has Atheros chipset on pcie port */ -&pciec { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/kirkwood-blackarmor-nas220.dts b/sys/gnu/dts/arm/kirkwood-blackarmor-nas220.dts deleted file mode 100644 index 07fbfca444d..00000000000 --- a/sys/gnu/dts/arm/kirkwood-blackarmor-nas220.dts +++ /dev/null @@ -1,172 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Device Tree file for Seagate Blackarmor NAS220 - * - * Copyright (C) 2014 Evgeni Dobrev - */ - -/dts-v1/; - -#include -#include -#include "kirkwood.dtsi" -#include "kirkwood-6192.dtsi" - -/ { - model = "Seagate Blackarmor NAS220"; - compatible = "seagate,blackarmor-nas220","marvell,kirkwood-88f6192", - "marvell,kirkwood"; - - memory { /* 128 MB */ - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - gpio_poweroff { - compatible = "gpio-poweroff"; - gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; - }; - - gpio_keys { - compatible = "gpio-keys"; - - reset { - label = "Reset"; - linux,code = ; - gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; - }; - - button { - label = "Power"; - linux,code = ; - gpios = <&gpio0 26 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - blue-power { - label = "nas220:blue:power"; - gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_power_sata0 &pmx_power_sata1>; - pinctrl-names = "default"; - - sata0_power: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "SATA0 Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 24 GPIO_ACTIVE_LOW>; - }; - - sata1_power: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "SATA1 Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 28 GPIO_ACTIVE_LOW>; - }; - }; -}; - -/* - * Serial port routed to connector CN5 - * - * pin 1 - TX (CPU's TX) - * pin 4 - RX (CPU's RX) - * pin 6 - GND - */ -&uart0 { - status = "okay"; -}; - -&pinctrl { - pinctrl-0 = <&pmx_button_reset &pmx_button_power>; - pinctrl-names = "default"; - - pmx_act_sata0: pmx-act-sata0 { - marvell,pins = "mpp15"; - marvell,function = "sata0"; - }; - - pmx_act_sata1: pmx-act-sata1 { - marvell,pins = "mpp16"; - marvell,function = "sata1"; - }; - - pmx_power_sata0: pmx-power-sata0 { - marvell,pins = "mpp24"; - marvell,function = "gpio"; - }; - - pmx_power_sata1: pmx-power-sata1 { - marvell,pins = "mpp28"; - marvell,function = "gpio"; - }; - - pmx_button_reset: pmx-button-reset { - marvell,pins = "mpp29"; - marvell,function = "gpio"; - }; - - pmx_button_power: pmx-button-power { - marvell,pins = "mpp26"; - marvell,function = "gpio"; - }; -}; - -&sata { - status = "okay"; - nr-ports = <2>; -}; - -&i2c0 { - status = "okay"; - - adt7476: thermal@2e { - compatible = "adi,adt7476"; - reg = <0x2e>; - }; -}; - -&nand { - status = "okay"; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@8 { - reg = <8>; - }; -}; - -ð0 { - status = "okay"; - - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; diff --git a/sys/gnu/dts/arm/kirkwood-cloudbox.dts b/sys/gnu/dts/arm/kirkwood-cloudbox.dts deleted file mode 100644 index 448b0cd23b5..00000000000 --- a/sys/gnu/dts/arm/kirkwood-cloudbox.dts +++ /dev/null @@ -1,103 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - model = "LaCie CloudBox"; - compatible = "lacie,cloudbox", "marvell,kirkwood-88f6702", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x10000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pmx_cloudbox_sata0: pmx-cloudbox-sata0 { - marvell,pins = "mpp15"; - marvell,function = "sata0"; - }; - }; - - serial@12000 { - status = "okay"; - }; - - sata@80000 { - pinctrl-0 = <&pmx_cloudbox_sata0>; - pinctrl-names = "default"; - status = "okay"; - nr-ports = <1>; - }; - - spi@10600 { - status = "okay"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "mxicy,mx25l4005a", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <20000000>; - mode = <0>; - - partition@0 { - reg = <0x0 0x80000>; - label = "u-boot"; - }; - }; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - power { - label = "Power push button"; - linux,code = ; - gpios = <&gpio0 16 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - red-fail { - label = "cloudbox:red:fail"; - gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; - }; - blue-sata { - label = "cloudbox:blue:sata"; - gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio_poweroff { - compatible = "gpio-poweroff"; - gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; diff --git a/sys/gnu/dts/arm/kirkwood-d2net.dts b/sys/gnu/dts/arm/kirkwood-d2net.dts deleted file mode 100644 index bd3b266dd76..00000000000 --- a/sys/gnu/dts/arm/kirkwood-d2net.dts +++ /dev/null @@ -1,45 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree file for d2 Network v2 - * - * Copyright (C) 2014 Simon Guinot - * -*/ - -/dts-v1/; - -#include -#include "kirkwood-netxbig.dtsi" - -/ { - model = "LaCie d2 Network v2"; - compatible = "lacie,d2net_v2", "lacie,netxbig", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x10000000>; - }; - - ns2-leds { - compatible = "lacie,ns2-leds"; - - blue-sata { - label = "d2net_v2:blue:sata"; - slow-gpio = <&gpio0 29 GPIO_ACTIVE_HIGH>; - cmd-gpio = <&gpio0 30 GPIO_ACTIVE_HIGH>; - modes-map = ; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - red-fail { - label = "d2net_v2:red:fail"; - gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/kirkwood-db-88f6281.dts b/sys/gnu/dts/arm/kirkwood-db-88f6281.dts deleted file mode 100644 index 2adb17c955a..00000000000 --- a/sys/gnu/dts/arm/kirkwood-db-88f6281.dts +++ /dev/null @@ -1,26 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Marvell DB-88F6281-BP Development Board Setup - * - * Saeed Bishara - * Thomas Petazzoni - * - */ - -/dts-v1/; - -#include "kirkwood-db.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - model = "Marvell DB-88F6281-BP Development Board"; - compatible = "marvell,db-88f6281-bp", "marvell,kirkwood-88f6281", "marvell,kirkwood"; -}; - -&pciec { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/kirkwood-db-88f6282.dts b/sys/gnu/dts/arm/kirkwood-db-88f6282.dts deleted file mode 100644 index f84a4853991..00000000000 --- a/sys/gnu/dts/arm/kirkwood-db-88f6282.dts +++ /dev/null @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Marvell DB-88F6282-BP Development Board Setup - * - * Saeed Bishara - * Thomas Petazzoni - * - */ - -/dts-v1/; - -#include "kirkwood-db.dtsi" -#include "kirkwood-6282.dtsi" - -/ { - model = "Marvell DB-88F6282-BP Development Board"; - compatible = "marvell,db-88f6282-bp", "marvell,kirkwood-88f6282", "marvell,kirkwood"; -}; - -&pciec { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; - -&pcie1 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/kirkwood-db.dtsi b/sys/gnu/dts/arm/kirkwood-db.dtsi deleted file mode 100644 index 6fe2e31534a..00000000000 --- a/sys/gnu/dts/arm/kirkwood-db.dtsi +++ /dev/null @@ -1,89 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Marvell DB-{88F6281,88F6282}-BP Development Board Setup - * - * Saeed Bishara - * Thomas Petazzoni - * - * This file contains the definitions that are common between the 6281 - * and 6282 variants of the Marvell Kirkwood Development Board. - */ - -#include "kirkwood.dtsi" - -/ { - memory { - device_type = "memory"; - reg = <0x00000000 0x20000000>; /* 512 MB */ - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pin-controller@10000 { - pmx_sdio_gpios: pmx-sdio-gpios { - marvell,pins = "mpp37", "mpp38"; - marvell,function = "gpio"; - }; - }; - - serial@12000 { - status = "okay"; - }; - - sata@80000 { - nr-ports = <2>; - status = "okay"; - }; - - ehci@50000 { - status = "okay"; - }; - - mvsdio@90000 { - pinctrl-0 = <&pmx_sdio_gpios>; - pinctrl-names = "default"; - wp-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; - cd-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - }; -}; - -&nand { - chip-delay = <25>; - status = "okay"; - - partition@0 { - label = "uboot"; - reg = <0x0 0x100000>; - }; - - partition@100000 { - label = "uImage"; - reg = <0x100000 0x400000>; - }; - - partition@500000 { - label = "root"; - reg = <0x500000 0x1fb00000>; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@8 { - reg = <8>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; diff --git a/sys/gnu/dts/arm/kirkwood-dir665.dts b/sys/gnu/dts/arm/kirkwood-dir665.dts deleted file mode 100644 index b3ad3f607d3..00000000000 --- a/sys/gnu/dts/arm/kirkwood-dir665.dts +++ /dev/null @@ -1,276 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2014 Claudio Leite - * - */ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - model = "D-Link DIR-665"; - compatible = "dlink,dir-665", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x8000000>; /* 128 MB */ - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pinctrl-0 =< &pmx_led_usb - &pmx_led_internet_blue - &pmx_led_internet_amber - &pmx_led_5g &pmx_led_status_blue - &pmx_led_wps &pmx_led_status_amber - &pmx_led_24g - &pmx_btn_restart &pmx_btn_wps>; - pinctrl-names = "default"; - - pmx_led_usb: pmx-led-usb { - marvell,pins = "mpp12"; - marvell,function = "gpio"; - }; - pmx_led_internet_blue: pmx-led-internet-blue { - marvell,pins = "mpp42"; - marvell,function = "gpio"; - }; - pmx_led_internet_amber: pmx-led-internet-amber { - marvell,pins = "mpp43"; - marvell,function = "gpio"; - }; - pmx_led_5g: pmx-led-5g { - marvell,pins = "mpp44"; - marvell,function = "gpio"; - }; - pmx_led_status_blue: pmx-led-status-blue { - marvell,pins = "mpp45"; - marvell,function = "gpio"; - }; - pmx_led_wps: pmx-led-wps { - marvell,pins = "mpp47"; - marvell,function = "gpio"; - }; - pmx_led_status_amber: pmx-led-status-amber { - marvell,pins = "mpp48"; - marvell,function = "gpio"; - }; - pmx_led_24g: pmx-led-24g { - marvell,pins = "mpp49"; - marvell,function = "gpio"; - }; - pmx_btn_restart: pmx-btn-restart { - marvell,pins = "mpp28"; - marvell,function = "gpio"; - }; - pmx_btn_wps: pmx-btn-wps { - marvell,pins = "mpp46"; - marvell,function = "gpio"; - }; - }; - - spi@10600 { - status = "okay"; - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "mxicy,mx25l12805d", "jedec,spi-nor"; - spi-max-frequency = <50000000>; - reg = <0>; - - partition@0 { - label = "uboot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "nvram"; - reg = <0x30000 0x10000>; - read-only; - }; - - partition@40000 { - label = "kernel"; - reg = <0x40000 0x180000>; - }; - - partition@1c0000 { - label = "rootfs"; - reg = <0x1c0000 0xe00000>; - }; - - cal_data: partition@fc0000 { - label = "cal_data"; - reg = <0xfc0000 0x10000>; - read-only; - }; - - partition@fd0000 { - label = "lang_pack"; - reg = <0xfd0000 0x30000>; - read-only; - }; - }; - }; - - serial@12000 { - status = "okay"; - }; - - i2c@11000 { - status = "okay"; - }; - - ehci@50000 { - status = "okay"; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - blue-usb { - label = "dir665:blue:usb"; - gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; - }; - blue-internet { - /* Can only be turned on if the Internet - * Ethernet port has Link - */ - label = "dir665:blue:internet"; - gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; - }; - amber-internet { - label = "dir665:amber:internet"; - gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; - }; - blue-wifi5g { - label = "dir665:blue:5g"; - gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; - }; - blue-status { - label = "dir665:blue:status"; - gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; - }; - blue-wps { - label = "dir665:blue:wps"; - gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>; - }; - amber-status { - label = "dir665:amber:status"; - gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>; - }; - blue-24g { - label = "dir665:blue:24g"; - gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - reset { - label = "reset"; - linux,code = ; - gpios = <&gpio0 28 GPIO_ACTIVE_LOW>; - }; - wps { - label = "wps"; - linux,code = ; - gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&mdio { - status = "okay"; - - switch@0 { - compatible = "marvell,mv88e6085"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "lan4"; - }; - - port@1 { - reg = <1>; - label = "lan3"; - }; - - port@2 { - reg = <2>; - label = "lan2"; - }; - - port@3 { - reg = <3>; - label = "lan1"; - }; - - port@4 { - reg = <4>; - label = "wan"; - }; - - port@6 { - reg = <6>; - label = "cpu"; - ethernet = <ð0port>; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; - }; -}; - -/* eth0 is connected to a Marvell 88E6171 switch, without a PHY. So set - * fixed speed and duplex. */ -ð0 { - status = "okay"; - - ethernet0-port@0 { - speed = <1000>; - duplex = <1>; - }; -}; - -/* eth1 is connected to the switch as well. However DSA only supports a - * single CPU port. So leave this port disabled to avoid confusion. */ - -ð1 { - status = "disabled"; -}; - -/* There is no battery on the boards, so the RTC does not keep time - * when there is no power, making it useless. */ -&rtc { - status = "disabled"; -}; - -&pciec { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/kirkwood-dns320.dts b/sys/gnu/dts/arm/kirkwood-dns320.dts deleted file mode 100644 index d6b0f418fd0..00000000000 --- a/sys/gnu/dts/arm/kirkwood-dns320.dts +++ /dev/null @@ -1,59 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "kirkwood-dnskw.dtsi" - -/ { - model = "D-Link DNS-320 NAS (Rev A1)"; - compatible = "dlink,dns-320-a1", "dlink,dns-320", "dlink,dns-kirkwood", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_led_power &pmx_led_red_usb_320 - &pmx_led_red_left_hdd &pmx_led_red_right_hdd - &pmx_led_white_usb>; - pinctrl-names = "default"; - - blue-power { - label = "dns320:blue:power"; - gpios = <&gpio0 26 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - blue-usb { - label = "dns320:blue:usb"; - gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; - }; - orange-l_hdd { - label = "dns320:orange:l_hdd"; - gpios = <&gpio0 28 GPIO_ACTIVE_LOW>; - }; - orange-r_hdd { - label = "dns320:orange:r_hdd"; - gpios = <&gpio0 27 GPIO_ACTIVE_LOW>; - }; - orange-usb { - label = "dns320:orange:usb"; - gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; /* GPIO 35 */ - }; - }; - - ocp@f1000000 { - serial@12000 { - status = "okay"; - }; - - serial@12100 { - status = "okay"; - }; - }; -}; diff --git a/sys/gnu/dts/arm/kirkwood-dns325.dts b/sys/gnu/dts/arm/kirkwood-dns325.dts deleted file mode 100644 index 94d9c06cbbf..00000000000 --- a/sys/gnu/dts/arm/kirkwood-dns325.dts +++ /dev/null @@ -1,63 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "kirkwood-dnskw.dtsi" - -/ { - model = "D-Link DNS-325 NAS (Rev A1)"; - compatible = "dlink,dns-325-a1", "dlink,dns-325", "dlink,dns-kirkwood", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x10000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_led_power &pmx_led_red_usb_325 - &pmx_led_red_left_hdd &pmx_led_red_right_hdd - &pmx_led_white_usb>; - pinctrl-names = "default"; - - white-power { - label = "dns325:white:power"; - gpios = <&gpio0 26 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - white-usb { - label = "dns325:white:usb"; - gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; /* GPIO 43 */ - }; - red-l_hdd { - label = "dns325:red:l_hdd"; - gpios = <&gpio0 28 GPIO_ACTIVE_LOW>; - }; - red-r_hdd { - label = "dns325:red:r_hdd"; - gpios = <&gpio0 27 GPIO_ACTIVE_LOW>; - }; - red-usb { - label = "dns325:red:usb"; - gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; - }; - }; - - ocp@f1000000 { - i2c@11000 { - status = "okay"; - - lm75: lm75@48 { - compatible = "national,lm75"; - reg = <0x48>; - }; - }; - serial@12000 { - status = "okay"; - }; - }; -}; diff --git a/sys/gnu/dts/arm/kirkwood-dnskw.dtsi b/sys/gnu/dts/arm/kirkwood-dnskw.dtsi deleted file mode 100644 index eb917462b21..00000000000 --- a/sys/gnu/dts/arm/kirkwood-dnskw.dtsi +++ /dev/null @@ -1,235 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - model = "D-Link DNS NASes (kirkwood-based)"; - compatible = "dlink,dns-kirkwood", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_button_power &pmx_button_unmount - &pmx_button_reset>; - pinctrl-names = "default"; - - power { - label = "Power button"; - linux,code = ; - gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; - }; - eject { - label = "USB unmount button"; - linux,code = ; - gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; - }; - reset { - label = "Reset button"; - linux,code = ; - gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; - }; - }; - - gpio_fan { - /* Fan: ADDA AD045HB-G73 40mm 6000rpm@5v */ - compatible = "gpio-fan"; - pinctrl-0 = <&pmx_fan_high_speed &pmx_fan_low_speed>; - pinctrl-names = "default"; - gpios = <&gpio1 14 GPIO_ACTIVE_HIGH - &gpio1 13 GPIO_ACTIVE_HIGH>; - gpio-fan,speed-map = <0 0 - 3000 1 - 6000 2>; - }; - - gpio_poweroff { - compatible = "gpio-poweroff"; - pinctrl-0 = <&pmx_power_off>; - pinctrl-names = "default"; - gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - - pinctrl-0 = <&pmx_power_back_on &pmx_present_sata0 - &pmx_present_sata1 &pmx_fan_tacho - &pmx_temp_alarm>; - pinctrl-names = "default"; - - pmx_sata0: pmx-sata0 { - marvell,pins = "mpp20"; - marvell,function = "sata1"; - }; - pmx_sata1: pmx-sata1 { - marvell,pins = "mpp21"; - marvell,function = "sata0"; - }; - pmx_led_power: pmx-led-power { - marvell,pins = "mpp26"; - marvell,function = "gpio"; - }; - pmx_led_red_right_hdd: pmx-led-red-right-hdd { - marvell,pins = "mpp27"; - marvell,function = "gpio"; - }; - pmx_led_red_left_hdd: pmx-led-red-left-hdd { - marvell,pins = "mpp28"; - marvell,function = "gpio"; - }; - pmx_led_red_usb_325: pmx-led-red-usb-325 { - marvell,pins = "mpp29"; - marvell,function = "gpio"; - }; - pmx_button_power: pmx-button-power { - marvell,pins = "mpp34"; - marvell,function = "gpio"; - }; - pmx_led_red_usb_320: pmx-led-red-usb-320 { - marvell,pins = "mpp35"; - marvell,function = "gpio"; - }; - pmx_power_off: pmx-power-off { - marvell,pins = "mpp36"; - marvell,function = "gpio"; - }; - pmx_power_back_on: pmx-power-back-on { - marvell,pins = "mpp37"; - marvell,function = "gpio"; - }; - pmx_power_sata0: pmx-power-sata0 { - marvell,pins = "mpp39"; - marvell,function = "gpio"; - }; - pmx_power_sata1: pmx-power-sata1 { - marvell,pins = "mpp40"; - marvell,function = "gpio"; - }; - pmx_present_sata0: pmx-present-sata0 { - marvell,pins = "mpp41"; - marvell,function = "gpio"; - }; - pmx_present_sata1: pmx-present-sata1 { - marvell,pins = "mpp42"; - marvell,function = "gpio"; - }; - pmx_led_white_usb: pmx-led-white-usb { - marvell,pins = "mpp43"; - marvell,function = "gpio"; - }; - pmx_fan_tacho: pmx-fan-tacho { - marvell,pins = "mpp44"; - marvell,function = "gpio"; - }; - pmx_fan_high_speed: pmx-fan-high-speed { - marvell,pins = "mpp45"; - marvell,function = "gpio"; - }; - pmx_fan_low_speed: pmx-fan-low-speed { - marvell,pins = "mpp46"; - marvell,function = "gpio"; - }; - pmx_button_unmount: pmx-button-unmount { - marvell,pins = "mpp47"; - marvell,function = "gpio"; - }; - pmx_button_reset: pmx-button-reset { - marvell,pins = "mpp48"; - marvell,function = "gpio"; - }; - pmx_temp_alarm: pmx-temp-alarm { - marvell,pins = "mpp49"; - marvell,function = "gpio"; - }; - }; - sata@80000 { - pinctrl-0 = <&pmx_sata0 &pmx_sata1>; - pinctrl-names = "default"; - status = "okay"; - nr-ports = <2>; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_power_sata0 &pmx_power_sata1>; - pinctrl-names = "default"; - - sata0_power: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "SATA0 Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio1 7 0>; - }; - sata1_power: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "SATA1 Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio1 8 0>; - }; - }; -}; - -&nand { - status = "okay"; - chip-delay = <35>; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0x100000>; - read-only; - }; - - partition@100000 { - label = "uImage"; - reg = <0x0100000 0x500000>; - }; - - partition@600000 { - label = "ramdisk"; - reg = <0x0600000 0x500000>; - }; - - partition@b00000 { - label = "image"; - reg = <0x0b00000 0x6600000>; - }; - - partition@7100000 { - label = "mini firmware"; - reg = <0x7100000 0xa00000>; - }; - - partition@7b00000 { - label = "config"; - reg = <0x7b00000 0x500000>; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@8 { - reg = <8>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; diff --git a/sys/gnu/dts/arm/kirkwood-dockstar.dts b/sys/gnu/dts/arm/kirkwood-dockstar.dts deleted file mode 100644 index 6a3f1bf6d9f..00000000000 --- a/sys/gnu/dts/arm/kirkwood-dockstar.dts +++ /dev/null @@ -1,110 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - model = "Seagate FreeAgent Dockstar"; - compatible = "seagate,dockstar", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk root=/dev/sda1 rootdelay=10"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pmx_usb_power_enable: pmx-usb-power-enable { - marvell,pins = "mpp29"; - marvell,function = "gpio"; - }; - pmx_led_green: pmx-led-green { - marvell,pins = "mpp46"; - marvell,function = "gpio"; - }; - pmx_led_orange: pmx-led-orange { - marvell,pins = "mpp47"; - marvell,function = "gpio"; - }; - }; - serial@12000 { - status = "ok"; - }; - }; - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_led_green &pmx_led_orange>; - pinctrl-names = "default"; - - health { - label = "status:green:health"; - gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - fault { - label = "status:orange:fault"; - gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; - }; - }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_usb_power_enable>; - pinctrl-names = "default"; - - usb_power: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "USB Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 29 0>; - }; - }; -}; - -&nand { - status = "okay"; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0x100000>; - read-only; - }; - - partition@100000 { - label = "uImage"; - reg = <0x0100000 0x400000>; - }; - - partition@500000 { - label = "data"; - reg = <0x0500000 0xfb00000>; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@0 { - compatible = "marvell,88e1116"; - reg = <0>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; diff --git a/sys/gnu/dts/arm/kirkwood-dreamplug.dts b/sys/gnu/dts/arm/kirkwood-dreamplug.dts deleted file mode 100644 index 7f326e26749..00000000000 --- a/sys/gnu/dts/arm/kirkwood-dreamplug.dts +++ /dev/null @@ -1,127 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - model = "Globalscale Technologies Dreamplug"; - compatible = "globalscale,dreamplug-003-ds2001", "globalscale,dreamplug", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x20000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pmx_led_bluetooth: pmx-led-bluetooth { - marvell,pins = "mpp47"; - marvell,function = "gpio"; - }; - pmx_led_wifi: pmx-led-wifi { - marvell,pins = "mpp48"; - marvell,function = "gpio"; - }; - pmx_led_wifi_ap: pmx-led-wifi-ap { - marvell,pins = "mpp49"; - marvell,function = "gpio"; - }; - }; - serial@12000 { - status = "ok"; - }; - - spi@10600 { - status = "okay"; - - m25p40@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "mxicy,mx25l1606e", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <50000000>; - mode = <0>; - - partition@0 { - reg = <0x0 0x80000>; - label = "u-boot"; - }; - - partition@100000 { - reg = <0x100000 0x10000>; - label = "u-boot env"; - }; - - partition@180000 { - reg = <0x180000 0x10000>; - label = "dtb"; - }; - }; - }; - - sata@80000 { - status = "okay"; - nr-ports = <1>; - }; - - mvsdio@90000 { - pinctrl-0 = <&pmx_sdio>; - pinctrl-names = "default"; - status = "okay"; - /* No CD or WP GPIOs */ - broken-cd; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_led_bluetooth &pmx_led_wifi - &pmx_led_wifi_ap >; - pinctrl-names = "default"; - - bluetooth { - label = "dreamplug:blue:bluetooth"; - gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; - }; - wifi { - label = "dreamplug:green:wifi"; - gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; - }; - wifi-ap { - label = "dreamplug:green:wifi_ap"; - gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; - - ethphy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; - -ð1 { - status = "okay"; - ethernet1-port@0 { - phy-handle = <ðphy1>; - }; -}; diff --git a/sys/gnu/dts/arm/kirkwood-ds109.dts b/sys/gnu/dts/arm/kirkwood-ds109.dts deleted file mode 100644 index 29982e7acb7..00000000000 --- a/sys/gnu/dts/arm/kirkwood-ds109.dts +++ /dev/null @@ -1,40 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Andrew Lunn - * Ben Peddell - * - */ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" -#include "kirkwood-synology.dtsi" - -/ { - model = "Synology DS109, DS110, DS110jv20"; - compatible = "synology,ds109", "synology,ds110jv20", - "synology,ds110", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - gpio-fan-150-32-35 { - status = "okay"; - }; - - gpio-leds-hdd-21-1 { - status = "okay"; - }; -}; - -&rs5c372 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/kirkwood-ds110jv10.dts b/sys/gnu/dts/arm/kirkwood-ds110jv10.dts deleted file mode 100644 index d68c616e930..00000000000 --- a/sys/gnu/dts/arm/kirkwood-ds110jv10.dts +++ /dev/null @@ -1,40 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Andrew Lunn - * Ben Peddell - * - */ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" -#include "kirkwood-synology.dtsi" - -/ { - model = "Synology DS110j v10 and v30"; - compatible = "synology,ds110jv10", "synology,ds110jv30", - "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - gpio-fan-150-32-35 { - status = "okay"; - }; - - gpio-leds-hdd-21-1 { - status = "okay"; - }; -}; - -&s35390a { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/kirkwood-ds111.dts b/sys/gnu/dts/arm/kirkwood-ds111.dts deleted file mode 100644 index e1420cbcd7e..00000000000 --- a/sys/gnu/dts/arm/kirkwood-ds111.dts +++ /dev/null @@ -1,43 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Andrew Lunn - * Ben Peddell - * - */ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6282.dtsi" -#include "kirkwood-synology.dtsi" - -/ { - model = "Synology DS111"; - compatible = "synology,ds111", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - gpio-fan-100-15-35-1 { - status = "okay"; - }; - - gpio-leds-hdd-21-1 { - status = "okay"; - }; -}; - -&s35390a { - status = "okay"; -}; - -&pcie1 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/kirkwood-ds112.dts b/sys/gnu/dts/arm/kirkwood-ds112.dts deleted file mode 100644 index f48609e95af..00000000000 --- a/sys/gnu/dts/arm/kirkwood-ds112.dts +++ /dev/null @@ -1,51 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Andrew Lunn - * Ben Peddell - * - */ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6282.dtsi" -#include "kirkwood-synology.dtsi" - -/ { - model = "Synology DS112"; - compatible = "synology,ds111", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - gpio-fan-100-15-35-1 { - status = "okay"; - }; - - gpio-leds-21-2 { - status = "okay"; - }; - - regulators-hdd-30 { - status = "okay"; - }; -}; - -&s35390a { - status = "okay"; -}; - -&pciec { - status = "okay"; -}; - -&pcie1 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/kirkwood-ds209.dts b/sys/gnu/dts/arm/kirkwood-ds209.dts deleted file mode 100644 index f41fe95e055..00000000000 --- a/sys/gnu/dts/arm/kirkwood-ds209.dts +++ /dev/null @@ -1,43 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Andrew Lunn - * Ben Peddell - * - */ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" -#include "kirkwood-synology.dtsi" - -/ { - model = "Synology DS209"; - compatible = "synology,ds209", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - gpio-fan-150-32-35 { - status = "okay"; - }; - - gpio-leds-hdd-21-2 { - status = "okay"; - }; - - regulators-hdd-31 { - status = "okay"; - }; -}; - -&rs5c372 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/kirkwood-ds210.dts b/sys/gnu/dts/arm/kirkwood-ds210.dts deleted file mode 100644 index 729f959a783..00000000000 --- a/sys/gnu/dts/arm/kirkwood-ds210.dts +++ /dev/null @@ -1,45 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Andrew Lunn - * Ben Peddell - * - */ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" -#include "kirkwood-synology.dtsi" - -/ { - model = "Synology DS210 v10, v20, v30, DS211j"; - compatible = "synology,ds210jv10", "synology,ds210jv20", - "synology,ds210jv30", "synology,ds211j", - "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - gpio-fan-150-32-35 { - status = "okay"; - }; - - gpio-leds-hdd-21-2 { - status = "okay"; - }; - - regulators-hdd-31 { - status = "okay"; - }; -}; - -&s35390a { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/kirkwood-ds212.dts b/sys/gnu/dts/arm/kirkwood-ds212.dts deleted file mode 100644 index 416bab50d17..00000000000 --- a/sys/gnu/dts/arm/kirkwood-ds212.dts +++ /dev/null @@ -1,46 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Andrew Lunn - * Ben Peddell - * - */ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6282.dtsi" -#include "kirkwood-synology.dtsi" - -/ { - model = "Synology DS212, DS212p v10, v20, DS213air v10, DS213 v10"; - compatible = "synology,ds212", "synology,ds212pv10", - "synology,ds212pv10", "synology,ds212pv20", - "synology,ds213airv10", "synology,ds213v10", - "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - gpio-fan-100-15-35-1 { - status = "okay"; - }; - - gpio-leds-hdd-21-2 { - status = "okay"; - }; -}; - -&s35390a { - status = "okay"; -}; - -&pcie1 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/kirkwood-ds212j.dts b/sys/gnu/dts/arm/kirkwood-ds212j.dts deleted file mode 100644 index 14cf4d8afaf..00000000000 --- a/sys/gnu/dts/arm/kirkwood-ds212j.dts +++ /dev/null @@ -1,40 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Andrew Lunn - * Ben Peddell - * - */ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" -#include "kirkwood-synology.dtsi" - -/ { - model = "Synology DS212j v10, v20"; - compatible = "synology,ds212jv10", "synology,ds212jv20", - "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - gpio-fan-100-32-35 { - status = "okay"; - }; - - gpio-leds-hdd-21-2 { - status = "okay"; - }; -}; - -&s35390a { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/kirkwood-ds409.dts b/sys/gnu/dts/arm/kirkwood-ds409.dts deleted file mode 100644 index a8650f9e3eb..00000000000 --- a/sys/gnu/dts/arm/kirkwood-ds409.dts +++ /dev/null @@ -1,47 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Andrew Lunn - * Ben Peddell - * - */ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" -#include "kirkwood-synology.dtsi" - -/ { - model = "Synology DS409, DS410j"; - compatible = "synology,ds409", "synology,ds410j", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - gpio-fan-150-15-18 { - status = "okay"; - }; - - gpio-leds-hdd-36 { - status = "okay"; - }; - - gpio-leds-alarm-12 { - status = "okay"; - }; -}; - -ð1 { - status = "okay"; -}; - -&rs5c372 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/kirkwood-ds409slim.dts b/sys/gnu/dts/arm/kirkwood-ds409slim.dts deleted file mode 100644 index 27a1d840bd1..00000000000 --- a/sys/gnu/dts/arm/kirkwood-ds409slim.dts +++ /dev/null @@ -1,39 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Andrew Lunn - * Ben Peddell - * - */ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" -#include "kirkwood-synology.dtsi" - -/ { - model = "Synology 409slim"; - compatible = "synology,ds409slim", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - gpio-fan-150-32-35 { - status = "okay"; - }; - - gpio-leds-hdd-20 { - status = "okay"; - }; -}; - -&rs5c372 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/kirkwood-ds411.dts b/sys/gnu/dts/arm/kirkwood-ds411.dts deleted file mode 100644 index 86907be70cf..00000000000 --- a/sys/gnu/dts/arm/kirkwood-ds411.dts +++ /dev/null @@ -1,55 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Andrew Lunn - * Ben Peddell - * - */ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6282.dtsi" -#include "kirkwood-synology.dtsi" - -/ { - model = "Synology DS411, DS413jv10"; - compatible = "synology,ds411", "synology,ds413jv10", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - gpio-fan-100-15-35-1 { - status = "okay"; - }; - - gpio-leds-hdd-36 { - status = "okay"; - }; - - regulators-hdd-34 { - status = "okay"; - }; -}; - -ð1 { - status = "okay"; -}; - -&s35390a { - status = "okay"; -}; - -&pciec { - status = "okay"; -}; - -&pcie1 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/kirkwood-ds411j.dts b/sys/gnu/dts/arm/kirkwood-ds411j.dts deleted file mode 100644 index bb3200daea1..00000000000 --- a/sys/gnu/dts/arm/kirkwood-ds411j.dts +++ /dev/null @@ -1,47 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Andrew Lunn - * Ben Peddell - * - */ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" -#include "kirkwood-synology.dtsi" - -/ { - model = "Synology DS411j"; - compatible = "synology,ds411j", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - gpio-fan-150-15-18 { - status = "okay"; - }; - - gpio-leds-hdd-36 { - status = "okay"; - }; - - gpio-leds-alarm-12 { - status = "okay"; - }; -}; - -ð1 { - status = "okay"; -}; - -&s35390a { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/kirkwood-ds411slim.dts b/sys/gnu/dts/arm/kirkwood-ds411slim.dts deleted file mode 100644 index 9c5364a4e0a..00000000000 --- a/sys/gnu/dts/arm/kirkwood-ds411slim.dts +++ /dev/null @@ -1,47 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Andrew Lunn - * Ben Peddell - * - */ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6282.dtsi" -#include "kirkwood-synology.dtsi" - -/ { - model = "Synology DS411slim"; - compatible = "synology,ds411slim", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - gpio-fan-100-15-35-1 { - status = "okay"; - }; - - gpio-leds-hdd-36 { - status = "okay"; - }; -}; - -ð1 { - status = "okay"; -}; - -&s35390a { - status = "okay"; -}; - -&pcie1 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/kirkwood-goflexnet.dts b/sys/gnu/dts/arm/kirkwood-goflexnet.dts deleted file mode 100644 index 02d87e0a106..00000000000 --- a/sys/gnu/dts/arm/kirkwood-goflexnet.dts +++ /dev/null @@ -1,190 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - model = "Seagate GoFlex Net"; - compatible = "seagate,goflexnet", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk root=/dev/sda1 rootdelay=10"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pmx_usb_power_enable: pmx-usb-power-enable { - marvell,pins = "mpp29"; - marvell,function = "gpio"; - }; - pmx_led_right_cap_0: pmx-led_right_cap_0 { - marvell,pins = "mpp38"; - marvell,function = "gpio"; - }; - pmx_led_right_cap_1: pmx-led_right_cap_1 { - marvell,pins = "mpp39"; - marvell,function = "gpio"; - }; - pmx_led_right_cap_2: pmx-led_right_cap_2 { - marvell,pins = "mpp40"; - marvell,function = "gpio"; - }; - pmx_led_right_cap_3: pmx-led_right_cap_3 { - marvell,pins = "mpp41"; - marvell,function = "gpio"; - }; - pmx_led_left_cap_0: pmx-led_left_cap_0 { - marvell,pins = "mpp42"; - marvell,function = "gpio"; - }; - pmx_led_left_cap_1: pmx-led_left_cap_1 { - marvell,pins = "mpp43"; - marvell,function = "gpio"; - }; - pmx_led_left_cap_2: pmx-led_left_cap_2 { - marvell,pins = "mpp44"; - marvell,function = "gpio"; - }; - pmx_led_left_cap_3: pmx-led_left_cap_3 { - marvell,pins = "mpp45"; - marvell,function = "gpio"; - }; - pmx_led_green: pmx-led_green { - marvell,pins = "mpp46"; - marvell,function = "gpio"; - }; - pmx_led_orange: pmx-led_orange { - marvell,pins = "mpp47"; - marvell,function = "gpio"; - }; - }; - serial@12000 { - status = "ok"; - }; - - sata@80000 { - status = "okay"; - nr-ports = <2>; - }; - - }; - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = < &pmx_led_orange - &pmx_led_left_cap_0 &pmx_led_left_cap_1 - &pmx_led_left_cap_2 &pmx_led_left_cap_3 - &pmx_led_right_cap_0 &pmx_led_right_cap_1 - &pmx_led_right_cap_2 &pmx_led_right_cap_3 - >; - pinctrl-names = "default"; - - health { - label = "status:green:health"; - gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - fault { - label = "status:orange:fault"; - gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; - }; - left0 { - label = "status:white:left0"; - gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; - }; - left1 { - label = "status:white:left1"; - gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; - }; - left2 { - label = "status:white:left2"; - gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; - }; - left3 { - label = "status:white:left3"; - gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; - }; - right0 { - label = "status:white:right0"; - gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; - }; - right1 { - label = "status:white:right1"; - gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; - }; - right2 { - label = "status:white:right2"; - gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; - }; - right3 { - label = "status:white:right3"; - gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; - }; - }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_usb_power_enable>; - pinctrl-names = "default"; - - usb_power: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "USB Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 29 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&nand { - chip-delay = <40>; - status = "okay"; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0x100000>; - read-only; - }; - - partition@100000 { - label = "uImage"; - reg = <0x0100000 0x400000>; - }; - - partition@500000 { - label = "pogoplug"; - reg = <0x0500000 0x2000000>; - }; - - partition@2500000 { - label = "root"; - reg = <0x02500000 0xd800000>; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; diff --git a/sys/gnu/dts/arm/kirkwood-guruplug-server-plus.dts b/sys/gnu/dts/arm/kirkwood-guruplug-server-plus.dts deleted file mode 100644 index ff1260ee3fe..00000000000 --- a/sys/gnu/dts/arm/kirkwood-guruplug-server-plus.dts +++ /dev/null @@ -1,133 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - model = "Globalscale Technologies Guruplug Server Plus"; - compatible = "globalscale,guruplug-server-plus", "globalscale,guruplug", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x20000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pmx_led_health_r: pmx-led-health-r { - marvell,pins = "mpp46"; - marvell,function = "gpio"; - }; - pmx_led_health_g: pmx-led-health-g { - marvell,pins = "mpp47"; - marvell,function = "gpio"; - }; - pmx_led_wmode_r: pmx-led-wmode-r { - marvell,pins = "mpp48"; - marvell,function = "gpio"; - }; - pmx_led_wmode_g: pmx-led-wmode-g { - marvell,pins = "mpp49"; - marvell,function = "gpio"; - }; - }; - serial@12000 { - status = "ok"; - }; - - sata@80000 { - status = "okay"; - nr-ports = <1>; - }; - - /* AzureWave AW-GH381 WiFi/BT */ - mvsdio@90000 { - status = "okay"; - non-removable; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = < &pmx_led_health_r &pmx_led_health_g - &pmx_led_wmode_r &pmx_led_wmode_g >; - pinctrl-names = "default"; - - health-r { - label = "guruplug:red:health"; - gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; - }; - health-g { - label = "guruplug:green:health"; - gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; - }; - wmode-r { - label = "guruplug:red:wmode"; - gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; - }; - wmode-g { - label = "guruplug:green:wmode"; - gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&nand { - status = "okay"; - - partition@0 { - label = "u-boot"; - reg = <0x00000000 0x00100000>; - read-only; - }; - - partition@100000 { - label = "uImage"; - reg = <0x00100000 0x00400000>; - }; - - partition@500000 { - label = "data"; - reg = <0x00500000 0x1fb00000>; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@0 { - /* Marvell 88E1121R */ - compatible = "ethernet-phy-id0141.0cb0", - "ethernet-phy-ieee802.3-c22"; - reg = <0>; - }; - - ethphy1: ethernet-phy@1 { - /* Marvell 88E1121R */ - compatible = "ethernet-phy-id0141.0cb0", - "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - phy-connection-type = "rgmii-id"; - }; -}; - -ð1 { - status = "okay"; - ethernet1-port@0 { - phy-handle = <ðphy1>; - phy-connection-type = "rgmii-id"; - }; -}; diff --git a/sys/gnu/dts/arm/kirkwood-ib62x0.dts b/sys/gnu/dts/arm/kirkwood-ib62x0.dts deleted file mode 100644 index 962a910a6f5..00000000000 --- a/sys/gnu/dts/arm/kirkwood-ib62x0.dts +++ /dev/null @@ -1,146 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - model = "RaidSonic ICY BOX IB-NAS62x0 (Rev B)"; - compatible = "raidsonic,ib-nas6210-b", "raidsonic,ib-nas6220-b", "raidsonic,ib-nas6210", "raidsonic,ib-nas6220", "raidsonic,ib-nas62x0", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x10000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pmx_led_os_red: pmx-led-os-red { - marvell,pins = "mpp22"; - marvell,function = "gpio"; - }; - pmx_power_off: pmx-power-off { - marvell,pins = "mpp24"; - marvell,function = "gpio"; - }; - pmx_led_os_green: pmx-led-os-green { - marvell,pins = "mpp25"; - marvell,function = "gpio"; - }; - pmx_led_usb_transfer: pmx-led-usb-transfer { - marvell,pins = "mpp27"; - marvell,function = "gpio"; - }; - pmx_button_reset: pmx-button-reset { - marvell,pins = "mpp28"; - marvell,function = "gpio"; - }; - pmx_button_usb_copy: pmx-button-usb-copy { - marvell,pins = "mpp29"; - marvell,function = "gpio"; - }; - }; - - serial@12000 { - status = "okay"; - }; - - sata@80000 { - status = "okay"; - nr-ports = <2>; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_button_reset &pmx_button_usb_copy>; - pinctrl-names = "default"; - - copy { - label = "USB Copy"; - linux,code = ; - gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; - }; - reset { - label = "Reset"; - linux,code = ; - gpios = <&gpio0 28 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_led_os_red &pmx_led_os_green - &pmx_led_usb_transfer>; - pinctrl-names = "default"; - - green-os { - label = "ib62x0:green:os"; - gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - red-os { - label = "ib62x0:red:os"; - gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>; - }; - usb-copy { - label = "ib62x0:red:usb_copy"; - gpios = <&gpio0 27 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio_poweroff { - compatible = "gpio-poweroff"; - pinctrl-0 = <&pmx_power_off>; - pinctrl-names = "default"; - gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>; - }; -}; - -&nand { - status = "okay"; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0xe0000>; - }; - - partition@e0000 { - label = "u-boot environment"; - reg = <0xe0000 0x20000>; - }; - - partition@100000 { - label = "uImage"; - reg = <0x0100000 0x600000>; - }; - - partition@700000 { - label = "root"; - reg = <0x0700000 0xf900000>; - }; - -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@8 { - reg = <8>; - }; -}; - -ð0 { - status = "okay"; - - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; diff --git a/sys/gnu/dts/arm/kirkwood-iconnect.dts b/sys/gnu/dts/arm/kirkwood-iconnect.dts deleted file mode 100644 index 4a512d80912..00000000000 --- a/sys/gnu/dts/arm/kirkwood-iconnect.dts +++ /dev/null @@ -1,195 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - model = "Iomega Iconnect"; - compatible = "iom,iconnect-1.1", "iom,iconnect", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x10000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; - linux,initrd-start = <0x4500040>; - linux,initrd-end = <0x4800000>; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pmx_button_reset: pmx-button-reset { - marvell,pins = "mpp12"; - marvell,function = "gpio"; - }; - pmx_button_otb: pmx-button-otb { - marvell,pins = "mpp35"; - marvell,function = "gpio"; - }; - pmx_led_level: pmx-led-level { - marvell,pins = "mpp41"; - marvell,function = "gpio"; - }; - pmx_led_power_blue: pmx-led-power-blue { - marvell,pins = "mpp42"; - marvell,function = "gpio"; - }; - pmx_led_power_red: pmx-power-red { - marvell,pins = "mpp43"; - marvell,function = "gpio"; - }; - pmx_led_usb1: pmx-led-usb1 { - marvell,pins = "mpp44"; - marvell,function = "gpio"; - }; - pmx_led_usb2: pmx-led-usb2 { - marvell,pins = "mpp45"; - marvell,function = "gpio"; - }; - pmx_led_usb3: pmx-led-usb3 { - marvell,pins = "mpp46"; - marvell,function = "gpio"; - }; - pmx_led_usb4: pmx-led-usb4 { - marvell,pins = "mpp47"; - marvell,function = "gpio"; - }; - pmx_led_otb: pmx-led-otb { - marvell,pins = "mpp48"; - marvell,function = "gpio"; - }; - }; - i2c@11000 { - status = "okay"; - - lm63: lm63@4c { - compatible = "national,lm63"; - reg = <0x4c>; - }; - }; - serial@12000 { - status = "ok"; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = < &pmx_led_level &pmx_led_power_blue - &pmx_led_power_red &pmx_led_usb1 - &pmx_led_usb2 &pmx_led_usb3 - &pmx_led_usb4 &pmx_led_otb >; - pinctrl-names = "default"; - - led-level { - label = "led_level"; - gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - power-blue { - label = "power:blue"; - gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - power-red { - label = "power:red"; - gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; - }; - usb1 { - label = "usb1:blue"; - gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; - }; - usb2 { - label = "usb2:blue"; - gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; - }; - usb3 { - label = "usb3:blue"; - gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; - }; - usb4 { - label = "usb4:blue"; - gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>; - }; - otb { - label = "otb:blue"; - gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = < &pmx_button_reset &pmx_button_otb >; - pinctrl-names = "default"; - - otb { - label = "OTB Button"; - linux,code = ; - gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; - debounce-interval = <100>; - }; - reset { - label = "Reset"; - linux,code = ; - gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; - debounce-interval = <100>; - }; - }; -}; - -&nand { - status = "okay"; - - partition@0 { - label = "uboot"; - reg = <0x0000000 0xc0000>; - }; - - partition@a0000 { - label = "env"; - reg = <0xa0000 0x20000>; - }; - - partition@100000 { - label = "zImage"; - reg = <0x100000 0x300000>; - }; - - partition@540000 { - label = "initrd"; - reg = <0x540000 0x300000>; - }; - - partition@980000 { - label = "boot"; - reg = <0x980000 0x1f400000>; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@11 { - reg = <11>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; - -&pciec { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/kirkwood-iomega_ix2_200.dts b/sys/gnu/dts/arm/kirkwood-iomega_ix2_200.dts deleted file mode 100644 index 62272d58664..00000000000 --- a/sys/gnu/dts/arm/kirkwood-iomega_ix2_200.dts +++ /dev/null @@ -1,226 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - model = "Iomega StorCenter ix2-200"; - compatible = "iom,ix2-200", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x10000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pinctrl-0 = < &pmx_led_sata_brt_ctrl_1 - &pmx_led_sata_brt_ctrl_2 - &pmx_led_backup_brt_ctrl_1 - &pmx_led_backup_brt_ctrl_2 - &pmx_led_power_brt_ctrl_1 - &pmx_led_power_brt_ctrl_2 - &pmx_led_health_brt_ctrl_1 - &pmx_led_health_brt_ctrl_2 - &pmx_led_rebuild_brt_ctrl_1 - &pmx_led_rebuild_brt_ctrl_2 >; - pinctrl-names = "default"; - - pmx_button_reset: pmx-button-reset { - marvell,pins = "mpp12"; - marvell,function = "gpio"; - }; - pmx_button_power: pmx-button-power { - marvell,pins = "mpp14"; - marvell,function = "gpio"; - }; - pmx_led_backup: pmx-led-backup { - marvell,pins = "mpp15"; - marvell,function = "gpio"; - }; - pmx_led_power: pmx-led-power { - marvell,pins = "mpp16"; - marvell,function = "gpio"; - }; - pmx_button_otb: pmx-button-otb { - marvell,pins = "mpp35"; - marvell,function = "gpio"; - }; - pmx_led_rebuild: pmx-led-rebuild { - marvell,pins = "mpp36"; - marvell,function = "gpio"; - }; - pmx_led_health: pmx-led_health { - marvell,pins = "mpp37"; - marvell,function = "gpio"; - }; - pmx_led_sata_brt_ctrl_1: pmx-led-sata-brt-ctrl-1 { - marvell,pins = "mpp38"; - marvell,function = "gpio"; - }; - pmx_led_sata_brt_ctrl_2: pmx-led-sata-brt-ctrl-2 { - marvell,pins = "mpp39"; - marvell,function = "gpio"; - }; - pmx_led_backup_brt_ctrl_1: pmx-led-backup-brt-ctrl-1 { - marvell,pins = "mpp40"; - marvell,function = "gpio"; - }; - pmx_led_backup_brt_ctrl_2: pmx-led-backup-brt-ctrl-2 { - marvell,pins = "mpp41"; - marvell,function = "gpio"; - }; - pmx_led_power_brt_ctrl_1: pmx-led-power-brt-ctrl-1 { - marvell,pins = "mpp42"; - marvell,function = "gpio"; - }; - pmx_led_power_brt_ctrl_2: pmx-led-power-brt-ctrl-2 { - marvell,pins = "mpp43"; - marvell,function = "gpio"; - }; - pmx_led_health_brt_ctrl_1: pmx-led-health-brt-ctrl-1 { - marvell,pins = "mpp44"; - marvell,function = "gpio"; - }; - pmx_led_health_brt_ctrl_2: pmx-led-health-brt-ctrl-2 { - marvell,pins = "mpp45"; - marvell,function = "gpio"; - }; - pmx_led_rebuild_brt_ctrl_1: pmx-led-rebuild-brt-ctrl-1 { - marvell,pins = "mpp46"; - marvell,function = "gpio"; - }; - pmx_led_rebuild_brt_ctrl_2: pmx-led-rebuild-brt-ctrl-2 { - marvell,pins = "mpp47"; - marvell,function = "gpio"; - }; - - }; - i2c@11000 { - status = "okay"; - - lm63: lm63@4c { - compatible = "national,lm63"; - reg = <0x4c>; - }; - }; - - serial@12000 { - status = "ok"; - }; - - sata@80000 { - status = "okay"; - nr-ports = <2>; - }; - - }; - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = < &pmx_led_backup &pmx_led_power - &pmx_led_rebuild &pmx_led_health >; - pinctrl-names = "default"; - - power_led { - label = "status:white:power_led"; - gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - rebuild_led { - label = "status:white:rebuild_led"; - gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; - }; - health_led { - label = "status:red:health_led"; - gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; - }; - backup_led { - label = "status:blue:backup_led"; - gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; - }; - }; - gpio-keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_button_reset &pmx_button_power - &pmx_button_otb>; - pinctrl-names = "default"; - - - Power { - label = "Power Button"; - linux,code = ; - gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; - }; - Reset { - label = "Reset Button"; - linux,code = ; - gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; - }; - OTB { - label = "OTB Button"; - linux,code = ; - gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; - }; - }; - gpio-poweroff { - compatible = "gpio-poweroff"; - gpios = <&gpio0 17 GPIO_ACTIVE_LOW>; - }; -}; - -&nand { - status = "okay"; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0x100000>; - read-only; - }; - - partition@a0000 { - label = "env"; - reg = <0xa0000 0x20000>; - read-only; - }; - - partition@100000 { - label = "uImage"; - reg = <0x100000 0x300000>; - }; - - partition@400000 { - label = "rootfs"; - reg = <0x400000 0x1C00000>; - }; -}; - -&mdio { - status = "okay"; - - ethphy1: ethernet-phy@11 { - reg = <11>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - speed = <1000>; - duplex = <1>; - }; -}; - -ð1 { - status = "okay"; - ethernet1-port@0 { - phy-handle = <ðphy1>; - }; -}; diff --git a/sys/gnu/dts/arm/kirkwood-is2.dts b/sys/gnu/dts/arm/kirkwood-is2.dts deleted file mode 100644 index 1bc16a5cdba..00000000000 --- a/sys/gnu/dts/arm/kirkwood-is2.dts +++ /dev/null @@ -1,40 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include -#include "kirkwood-ns2-common.dtsi" - -/ { - model = "LaCie Internet Space v2"; - compatible = "lacie,inetspace_v2", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - ocp@f1000000 { - sata@80000 { - pinctrl-0 = <&pmx_ns2_sata0>; - pinctrl-names = "default"; - status = "okay"; - nr-ports = <1>; - }; - }; - - ns2-leds { - compatible = "lacie,ns2-leds"; - - blue-sata { - label = "ns2:blue:sata"; - slow-gpio = <&gpio0 29 0>; - cmd-gpio = <&gpio0 30 0>; - modes-map = ; - }; - }; -}; - -ðphy0 { reg = <8>; }; diff --git a/sys/gnu/dts/arm/kirkwood-km_common.dtsi b/sys/gnu/dts/arm/kirkwood-km_common.dtsi deleted file mode 100644 index 75dc83914f5..00000000000 --- a/sys/gnu/dts/arm/kirkwood-km_common.dtsi +++ /dev/null @@ -1,47 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/ { - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pinctrl-0 = < &pmx_i2c_gpio_sda &pmx_i2c_gpio_scl >; - pinctrl-names = "default"; - - pmx_i2c_gpio_sda: pmx-gpio-sda { - marvell,pins = "mpp8"; - marvell,function = "gpio"; - }; - pmx_i2c_gpio_scl: pmx-gpio-scl { - marvell,pins = "mpp9"; - marvell,function = "gpio"; - }; - }; - - serial@12000 { - status = "okay"; - }; - }; - - i2c { - compatible = "i2c-gpio"; - gpios = < &gpio0 8 GPIO_ACTIVE_HIGH /* sda */ - &gpio0 9 GPIO_ACTIVE_HIGH>; /* scl */ - i2c-gpio,delay-us = <2>; /* ~100 kHz */ - }; -}; - -&nand { - status = "okay"; - chip-delay = <25>; -}; - -&pciec { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/kirkwood-km_fixedeth.dts b/sys/gnu/dts/arm/kirkwood-km_fixedeth.dts deleted file mode 100644 index 515be7bccc0..00000000000 --- a/sys/gnu/dts/arm/kirkwood-km_fixedeth.dts +++ /dev/null @@ -1,24 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-98dx4122.dtsi" -#include "kirkwood-km_common.dtsi" - -/ { - model = "Keymile Kirkwood Fixed Eth"; - compatible = "keymile,km_fixedeth", "marvell,kirkwood-98DX4122", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x10000000>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - speed = <1000>; /* */ - duplex = <1>; /* */ - }; -}; diff --git a/sys/gnu/dts/arm/kirkwood-km_kirkwood.dts b/sys/gnu/dts/arm/kirkwood-km_kirkwood.dts deleted file mode 100644 index f035eff1c11..00000000000 --- a/sys/gnu/dts/arm/kirkwood-km_kirkwood.dts +++ /dev/null @@ -1,31 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-98dx4122.dtsi" -#include "kirkwood-km_common.dtsi" - -/ { - model = "Keymile Kirkwood Reference Design"; - compatible = "keymile,km_kirkwood", "marvell,kirkwood-98DX4122", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x08000000>; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; diff --git a/sys/gnu/dts/arm/kirkwood-laplug.dts b/sys/gnu/dts/arm/kirkwood-laplug.dts deleted file mode 100644 index 6158214a939..00000000000 --- a/sys/gnu/dts/arm/kirkwood-laplug.dts +++ /dev/null @@ -1,168 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2013 Maxime Hadjinlian - * - */ - -/dts-v1/; - -#include -#include -#include "kirkwood.dtsi" -#include "kirkwood-6192.dtsi" - -/ { - model = "LaCie LaPlug"; - compatible = "lacie,laplug", "marvell,kirkwood-88f6192", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x8000000>; /* 128 MB */ - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - serial@12000 { - status = "okay"; - }; - - i2c@11000 { - status = "okay"; - - eeprom@50 { - compatible = "atmel,24c04"; - pagesize = <16>; - reg = <0x50>; - }; - }; - - pinctrl: pin-controller@10000 { - pmx_usb_power_enable: pmx-usb-power-enable { - marvell,pins = "mpp14"; - marvell,function = "gpio"; - }; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - - power { - label = "Power push button"; - linux,code = ; - gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - red-fail { - label = "laplug_v2:red:power"; - gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; - }; - blue-power { - label = "laplug_v2:blue:power"; - gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - }; - }; - - gpio_poweroff { - compatible = "gpio-poweroff"; - gpios = <&gpio0 31 GPIO_ACTIVE_HIGH>; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_usb_power_enable>; - pinctrl-names = "default"; - - usb_power_back1: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "USB Power Back 1"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 15 GPIO_ACTIVE_HIGH>; - }; - - usb_power_back2: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "USB Power Back 2"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 28 GPIO_ACTIVE_HIGH>; - }; - - usb_power_front: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "USB Power Front"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio1 3 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&nand { - /* Total size : 512MB */ - status = "okay"; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x100000>; /* 1MB */ - read-only; - }; - - partition@100000 { - label = "uImage"; - reg = <0x100000 0x1000000>; /* 16MB */ - }; - - partition@1100000 { - label = "rootfs"; - reg = <0x1100000 0x1EF00000>; /* 495MB */ - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@0 { - device_type = "ethernet-phy"; - reg = <0>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; - -&pciec { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/kirkwood-linkstation-6282.dtsi b/sys/gnu/dts/arm/kirkwood-linkstation-6282.dtsi deleted file mode 100644 index 377b6e97025..00000000000 --- a/sys/gnu/dts/arm/kirkwood-linkstation-6282.dtsi +++ /dev/null @@ -1,155 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree common file for kirkwood-6282 based Buffalo Linkstation - * - * Copyright (C) 2015, 2016 - * Roger Shimizu - */ - -#include "kirkwood.dtsi" -#include "kirkwood-6282.dtsi" -#include "kirkwood-linkstation.dtsi" - -/ { - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pmx_power_hdd0: pmx-power-hdd0 { - marvell,pins = "mpp8"; - marvell,function = "gpio"; - }; - pmx_usb_vbus: pmx-usb-vbus { - marvell,pins = "mpp12"; - marvell,function = "gpio"; - }; - pmx_fan_high: pmx-fan-high { - marvell,pins = "mpp16"; - marvell,function = "gpio"; - }; - pmx_fan_low: pmx-fan-low { - marvell,pins = "mpp17"; - marvell,function = "gpio"; - }; - pmx_led_alarm: pmx-led-alarm { - marvell,pins = "mpp36"; - marvell,function = "gpio"; - }; - pmx_led_function_red: pmx-led-function-red { - marvell,pins = "mpp37"; - marvell,function = "gpio"; - }; - pmx_led_info: pmx-led-info { - marvell,pins = "mpp38"; - marvell,function = "gpio"; - }; - pmx_led_function_blue: pmx-led-function-blue { - marvell,pins = "mpp39"; - marvell,function = "gpio"; - }; - pmx_led_power: pmx-led-power { - marvell,pins = "mpp40"; - marvell,function = "gpio"; - }; - pmx_fan_lock: pmx-fan-lock { - marvell,pins = "mpp43"; - marvell,function = "gpio"; - }; - pmx_button_function: pmx-button-function { - marvell,pins = "mpp45"; - marvell,function = "gpio"; - }; - pmx_power_switch: pmx-power-switch { - marvell,pins = "mpp46"; - marvell,function = "gpio"; - }; - pmx_power_auto_switch: pmx-power-auto-switch { - marvell,pins = "mpp47"; - marvell,function = "gpio"; - }; - }; - }; - - gpio_keys { - function-button { - gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; - }; - - power-on-switch { - gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; - }; - - power-auto-switch { - gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; - }; - }; - - gpio_leds { - red-alarm-led { - label = "linkstation:red:alarm"; - gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; - }; - - red-function-led { - label = "linkstation:red:function"; - gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; - }; - - amber-info-led { - label = "linkstation:amber:info"; - gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; - }; - - blue-function-led { - label = "linkstation:blue:function"; - gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; - }; - - blue-power-led { - label = "linkstation:blue:power"; - gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - }; - - gpio_fan { - compatible = "gpio-fan"; - pinctrl-0 = <&pmx_fan_low &pmx_fan_high &pmx_fan_lock>; - pinctrl-names = "default"; - - gpios = <&gpio0 17 GPIO_ACTIVE_LOW - &gpio0 16 GPIO_ACTIVE_LOW>; - - gpio-fan,speed-map = <0 3 - 1500 2 - 3250 1 - 5000 0>; - - alarm-gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; - }; - - regulators { - usb_power: regulator@1 { - gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>; - }; - - hdd_power0: regulator@2 { - gpio = <&gpio0 8 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@0 { - device_type = "ethernet-phy"; - reg = <0>; - }; -}; - -ð0 { - status = "okay"; - - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; diff --git a/sys/gnu/dts/arm/kirkwood-linkstation-duo-6281.dtsi b/sys/gnu/dts/arm/kirkwood-linkstation-duo-6281.dtsi deleted file mode 100644 index ba629e02ba3..00000000000 --- a/sys/gnu/dts/arm/kirkwood-linkstation-duo-6281.dtsi +++ /dev/null @@ -1,149 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree common file for kirkwood-6281 based 2-Bay Buffalo Linkstation - * - * Copyright (C) 2015, 2016 - * Roger Shimizu - */ - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" -#include "kirkwood-linkstation.dtsi" - -/ { - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pmx_power_hdd0: pmx-power-hdd0 { - marvell,pins = "mpp28"; - marvell,function = "gpio"; - }; - pmx_power_hdd1: pmx-power-hdd1 { - marvell,pins = "mpp29"; - marvell,function = "gpio"; - }; - pmx_usb_vbus: pmx-usb-vbus { - marvell,pins = "mpp37"; - marvell,function = "gpio"; - }; - pmx_led_alarm: pmx-led-alarm { - marvell,pins = "mpp49"; - marvell,function = "gpio"; - }; - pmx_led_function_red: pmx-led-function-red { - marvell,pins = "mpp34"; - marvell,function = "gpio"; - }; - pmx_led_function_blue: pmx-led-function-blue { - marvell,pins = "mpp36"; - marvell,function = "gpio"; - }; - pmx_led_info: pmx-led-info { - marvell,pins = "mpp38"; - marvell,function = "gpio"; - }; - pmx_led_power: pmx-led-power { - marvell,pins = "mpp39"; - marvell,function = "gpio"; - }; - pmx_button_function: pmx-button-function { - marvell,pins = "mpp41"; - marvell,function = "gpio"; - }; - pmx_power_switch: pmx-power-switch { - marvell,pins = "mpp42"; - marvell,function = "gpio"; - }; - pmx_power_auto_switch: pmx-power-auto-switch { - marvell,pins = "mpp43"; - marvell,function = "gpio"; - }; - }; - - sata@80000 { - nr-ports = <2>; - }; - }; - - gpio_keys { - function-button { - gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; - }; - - power-on-switch { - gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; - }; - - power-auto-switch { - gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; - }; - }; - - gpio_leds { - red-alarm-led { - label = "linkstation:red:alarm"; - gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; - }; - - red-function-led { - label = "linkstation:red:function"; - gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; - }; - - amber-info-led { - label = "linkstation:amber:info"; - gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; - }; - - blue-function-led { - label = "linkstation:blue:function"; - gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - }; - - blue-power-led { - label = "linkstation:blue:power"; - gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - }; - - regulators { - pinctrl-0 = <&pmx_power_hdd0 &pmx_power_hdd1 &pmx_usb_vbus>; - - usb_power: regulator@1 { - gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; - }; - - hdd_power0: regulator@2 { - gpio = <&gpio0 28 GPIO_ACTIVE_HIGH>; - }; - - hdd_power1: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "HDD1 Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 29 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&mdio { - status = "okay"; - - ethphy1: ethernet-phy@8 { - device_type = "ethernet-phy"; - reg = <8>; - }; -}; - -ð1 { - status = "okay"; - - ethernet1-port@0 { - phy-handle = <ðphy1>; - }; -}; diff --git a/sys/gnu/dts/arm/kirkwood-linkstation-lsqvl.dts b/sys/gnu/dts/arm/kirkwood-linkstation-lsqvl.dts deleted file mode 100644 index 8bb38108891..00000000000 --- a/sys/gnu/dts/arm/kirkwood-linkstation-lsqvl.dts +++ /dev/null @@ -1,98 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for Buffalo Linkstation LS-QVL - * - * Copyright (C) 2016, Mario Lange - * - * Based on kirkwood-linkstation-lswvl.dts, - * Copyright (C) 2015, 2016 - * Roger Shimizu - */ - -/dts-v1/; -#include "kirkwood-linkstation-6282.dtsi" - -/ { - model = "Buffalo Linkstation LS-QVL"; - compatible = "buffalo,lsqvl", "marvell,kirkwood-88f6282", "marvell,kirkwood"; - - memory { /* 256 MB */ - device_type = "memory"; - reg = <0x00000000 0x10000000>; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pmx_power_hdd1: pmx-power-hdd1 { - marvell,pins = "mpp9"; - marvell,function = "gpio"; - }; - pmx_led_hdderr0: pmx-led-hdderr0 { - marvell,pins = "mpp34"; - marvell,function = "gpio"; - }; - pmx_led_hdderr1: pmx-led-hdderr1 { - marvell,pins = "mpp35"; - marvell,function = "gpio"; - }; - pmx_led_hdderr2: pmx-led-hdderr2 { - marvell,pins = "mpp24"; - marvell,function = "gpio"; - }; - pmx_led_hdderr3: pmx-led-hdderr3 { - marvell,pins = "mpp25"; - marvell,function = "gpio"; - }; - }; - - sata@80000 { - nr-ports = <2>; - }; - }; - - gpio_leds { - pinctrl-0 = <&pmx_led_function_red &pmx_led_alarm - &pmx_led_info &pmx_led_power - &pmx_led_function_blue - &pmx_led_hdderr0 - &pmx_led_hdderr1 - &pmx_led_hdderr2 - &pmx_led_hdderr3>; - - red-hdderr0-led { - label = "linkstation:red:hdderr0"; - gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; - }; - - red-hdderr1-led { - label = "linkstation:red:hdderr1"; - gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; - }; - - red-hdderr2-led { - label = "linkstation:red:hdderr2"; - gpios = <&gpio0 24 GPIO_ACTIVE_LOW>; - }; - - red-hdderr3-led { - label = "linkstation:red:hdderr3"; - gpios = <&gpio0 25 GPIO_ACTIVE_LOW>; - }; - }; - - regulators { - pinctrl-0 = <&pmx_power_hdd0 &pmx_power_hdd1 &pmx_usb_vbus>; - - hdd_power1: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "HDD1 Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 9 GPIO_ACTIVE_HIGH>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/kirkwood-linkstation-lsvl.dts b/sys/gnu/dts/arm/kirkwood-linkstation-lsvl.dts deleted file mode 100644 index 3f2a0bfe03e..00000000000 --- a/sys/gnu/dts/arm/kirkwood-linkstation-lsvl.dts +++ /dev/null @@ -1,20 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for Buffalo Linkstation LS-VL - * - * Copyright (C) 2015, 2016 - * Roger Shimizu - */ - -/dts-v1/; -#include "kirkwood-linkstation-6282.dtsi" - -/ { - model = "Buffalo Linkstation LS-VL"; - compatible = "buffalo,lsvl", "marvell,kirkwood-88f6282", "marvell,kirkwood"; - - memory { /* 256 MB */ - device_type = "memory"; - reg = <0x00000000 0x10000000>; - }; -}; diff --git a/sys/gnu/dts/arm/kirkwood-linkstation-lswsxl.dts b/sys/gnu/dts/arm/kirkwood-linkstation-lswsxl.dts deleted file mode 100644 index c42d0da38fe..00000000000 --- a/sys/gnu/dts/arm/kirkwood-linkstation-lswsxl.dts +++ /dev/null @@ -1,20 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for Buffalo Linkstation LS-WSXL - * - * Copyright (C) 2015, 2016 - * Roger Shimizu - */ - -/dts-v1/; -#include "kirkwood-linkstation-duo-6281.dtsi" - -/ { - model = "Buffalo Linkstation LS-WSXL"; - compatible = "buffalo,lswsxl", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { /* 128 MB */ - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; -}; diff --git a/sys/gnu/dts/arm/kirkwood-linkstation-lswvl.dts b/sys/gnu/dts/arm/kirkwood-linkstation-lswvl.dts deleted file mode 100644 index e0f62adc0d5..00000000000 --- a/sys/gnu/dts/arm/kirkwood-linkstation-lswvl.dts +++ /dev/null @@ -1,75 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for Buffalo Linkstation LS-WVL - * - * Copyright (C) 2015, 2016 - * Roger Shimizu - */ - -/dts-v1/; -#include "kirkwood-linkstation-6282.dtsi" - -/ { - model = "Buffalo Linkstation LS-WVL"; - compatible = "buffalo,lswvl","marvell,kirkwood-88f6282", "marvell,kirkwood"; - - memory { /* 256 MB */ - device_type = "memory"; - reg = <0x00000000 0x10000000>; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pmx_power_hdd1: pmx-power-hdd1 { - marvell,pins = "mpp9"; - marvell,function = "gpio"; - }; - pmx_led_hdderr0: pmx-led-hdderr0 { - marvell,pins = "mpp34"; - marvell,function = "gpio"; - }; - pmx_led_hdderr1: pmx-led-hdderr1 { - marvell,pins = "mpp35"; - marvell,function = "gpio"; - }; - }; - - sata@80000 { - nr-ports = <2>; - }; - }; - - gpio_leds { - pinctrl-0 = <&pmx_led_function_red &pmx_led_alarm - &pmx_led_info &pmx_led_power - &pmx_led_function_blue - &pmx_led_hdderr0 - &pmx_led_hdderr1>; - - red-hdderr0-led { - label = "linkstation:red:hdderr0"; - gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; - }; - - red-hdderr1-led { - label = "linkstation:red:hdderr1"; - gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; - }; - }; - - regulators { - pinctrl-0 = <&pmx_power_hdd0 &pmx_power_hdd1 &pmx_usb_vbus>; - - hdd_power1: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "HDD1 Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 9 GPIO_ACTIVE_HIGH>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/kirkwood-linkstation-lswxl.dts b/sys/gnu/dts/arm/kirkwood-linkstation-lswxl.dts deleted file mode 100644 index c6024b56942..00000000000 --- a/sys/gnu/dts/arm/kirkwood-linkstation-lswxl.dts +++ /dev/null @@ -1,79 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for Buffalo Linkstation LS-WXL - * - * Copyright (C) 2015, 2016 - * Roger Shimizu - */ - -/dts-v1/; -#include "kirkwood-linkstation-duo-6281.dtsi" - -/ { - model = "Buffalo Linkstation LS-WXL"; - compatible = "buffalo,lswxl", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { /* 128 MB */ - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pmx_led_hdderr0: pmx-led-hdderr0 { - marvell,pins = "mpp8"; - marvell,function = "gpio"; - }; - pmx_led_hdderr1: pmx-led-hdderr1 { - marvell,pins = "mpp46"; - marvell,function = "gpio"; - }; - pmx_fan_lock: pmx-fan-lock { - marvell,pins = "mpp40"; - marvell,function = "gpio"; - }; - pmx_fan_high: pmx-fan-high { - marvell,pins = "mpp47"; - marvell,function = "gpio"; - }; - pmx_fan_low: pmx-fan-low { - marvell,pins = "mpp48"; - marvell,function = "gpio"; - }; - }; - }; - - gpio_leds { - pinctrl-0 = <&pmx_led_function_red &pmx_led_alarm - &pmx_led_info &pmx_led_power - &pmx_led_function_blue - &pmx_led_hdderr0 - &pmx_led_hdderr1>; - - red-hdderr0-led { - label = "linkstation:red:hdderr0"; - gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>; - }; - - red-hdderr1-led { - label = "linkstation:red:hdderr1"; - gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio_fan { - compatible = "gpio-fan"; - pinctrl-0 = <&pmx_fan_low &pmx_fan_high &pmx_fan_lock>; - pinctrl-names = "default"; - - gpios = <&gpio1 16 GPIO_ACTIVE_LOW - &gpio1 15 GPIO_ACTIVE_LOW>; - - gpio-fan,speed-map = <0 3 - 1500 2 - 3250 1 - 5000 0>; - - alarm-gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; - }; -}; diff --git a/sys/gnu/dts/arm/kirkwood-linkstation.dtsi b/sys/gnu/dts/arm/kirkwood-linkstation.dtsi deleted file mode 100644 index 407d6d8b3a7..00000000000 --- a/sys/gnu/dts/arm/kirkwood-linkstation.dtsi +++ /dev/null @@ -1,164 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree common file for kirkwood based Buffalo Linkstation - * - * Copyright (C) 2015, 2016 - * Roger Shimizu - */ - -/ { - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pmx_power_hdd0: pmx-power-hdd0 { - marvell,function = "gpio"; - }; - pmx_usb_vbus: pmx-usb-vbus { - marvell,function = "gpio"; - }; - pmx_led_alarm: pmx-led-alarm { - marvell,function = "gpio"; - }; - pmx_led_function_red: pmx-led-function-red { - marvell,function = "gpio"; - }; - pmx_led_function_blue: pmx-led-function-blue { - marvell,function = "gpio"; - }; - pmx_led_info: pmx-led-info { - marvell,function = "gpio"; - }; - pmx_led_power: pmx-led-power { - marvell,function = "gpio"; - }; - pmx_button_function: pmx-button-function { - marvell,function = "gpio"; - }; - pmx_power_switch: pmx-power-switch { - marvell,function = "gpio"; - }; - pmx_power_auto_switch: pmx-power-auto-switch { - marvell,function = "gpio"; - }; - }; - - serial@12000 { - status = "okay"; - }; - - sata@80000 { - status = "okay"; - nr-ports = <1>; - }; - - spi@10600 { - status = "okay"; - - m25p40@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,m25p40", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <25000000>; - mode = <0>; - - partition@0 { - reg = <0x0 0x60000>; - label = "uboot"; - read-only; - }; - - partition@60000 { - reg = <0x60000 0x10000>; - label = "dtb"; - read-only; - }; - - partition@70000 { - reg = <0x70000 0x10000>; - label = "uboot_env"; - }; - }; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_button_function &pmx_power_switch - &pmx_power_auto_switch>; - pinctrl-names = "default"; - - function-button { - label = "Function Button"; - linux,code = ; - }; - - power-on-switch { - label = "Power-on Switch"; - linux,code = ; - linux,input-type = <5>; - }; - - power-auto-switch { - label = "Power-auto Switch"; - linux,code = ; - linux,input-type = <5>; - }; - }; - - gpio_leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_led_function_red &pmx_led_alarm - &pmx_led_info &pmx_led_power - &pmx_led_function_blue>; - pinctrl-names = "default"; - }; - - restart_poweroff { - compatible = "restart-poweroff"; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_power_hdd0 &pmx_usb_vbus>; - pinctrl-names = "default"; - - usb_power: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "USB Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - }; - - hdd_power0: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "HDD0 Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - }; - }; -}; - -&pciec { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/kirkwood-linksys-viper.dts b/sys/gnu/dts/arm/kirkwood-linksys-viper.dts deleted file mode 100644 index 2f9660f3b45..00000000000 --- a/sys/gnu/dts/arm/kirkwood-linksys-viper.dts +++ /dev/null @@ -1,240 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * kirkwood-viper.dts - Device Tree file for Linksys viper (E4200v2 / EA4500) - * - * (c) 2013 Jonas Gorski - * (c) 2013 Deutsche Telekom Innovation Laboratories - * (c) 2014 Luka Perkov - * (c) 2014 Randy C. Will - * - */ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6282.dtsi" - -/ { - model = "Linksys Viper (E4200v2 / EA4500)"; - compatible = "linksys,viper", "marvell,kirkwood-88f6282", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = < &pmx_btn_wps &pmx_btn_reset >; - pinctrl-names = "default"; - - wps { - label = "WPS Button"; - linux,code = ; - gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; - }; - - reset { - label = "Reset Button"; - linux,code = ; - gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = < &pmx_led_white_health &pmx_led_white_pulse >; - pinctrl-names = "default"; - - white-health { - label = "viper:white:health"; - gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>; - }; - - white-pulse { - label = "viper:white:pulse"; - gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&pinctrl { - pmx_led_white_health: pmx-led-white-health { - marvell,pins = "mpp7"; - marvell,function = "gpo"; - }; - pmx_led_white_pulse: pmx-led-white-pulse { - marvell,pins = "mpp14"; - marvell,function = "gpio"; - }; - pmx_btn_wps: pmx-btn-wps { - marvell,pins = "mpp47"; - marvell,function = "gpio"; - }; - pmx_btn_reset: pmx-btn-reset { - marvell,pins = "mpp48"; - marvell,function = "gpio"; - }; -}; - -&nand { - status = "okay"; - pinctrl-0 = <&pmx_nand>; - pinctrl-names = "default"; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x80000>; - read-only; - }; - - partition@80000 { - label = "u_env"; - reg = <0x80000 0x20000>; - }; - - partition@a0000 { - label = "s_env"; - reg = <0xA0000 0x20000>; - }; - - partition@200000 { - label = "kernel"; - reg = <0x200000 0x2A0000>; - }; - - partition@4a0000 { - label = "rootfs"; - reg = <0x4A0000 0x1760000>; - }; - - partition@1c00000 { - label = "alt_kernel"; - reg = <0x1C00000 0x2A0000>; - }; - - partition@1ea0000 { - label = "alt_rootfs"; - reg = <0x1EA0000 0x1760000>; - }; - - partition@3600000 { - label = "syscfg"; - reg = <0x3600000 0x4A00000>; - }; - - partition@c0000 { - label = "unused"; - reg = <0xC0000 0x140000>; - }; - - }; -}; - -&pciec { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; - -&pcie1 { - status = "okay"; -}; - -&mdio { - status = "okay"; - - switch@10 { - compatible = "marvell,mv88e6085"; - #address-cells = <1>; - #size-cells = <0>; - reg = <16>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "ethernet1"; - }; - - port@1 { - reg = <1>; - label = "ethernet2"; - }; - - port@2 { - reg = <2>; - label = "ethernet3"; - }; - - port@3 { - reg = <3>; - label = "ethernet4"; - }; - - port@4 { - reg = <4>; - label = "internet"; - }; - - port@5 { - reg = <5>; - label = "cpu"; - ethernet = <ð0port>; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; - }; -}; - -&uart0 { - status = "okay"; -}; - -/* eth0 is connected to a Marvell 88E6171 switch, without a PHY. So set - * fixed speed and duplex. - */ -ð0 { - status = "okay"; - ethernet0-port@0 { - speed = <1000>; - duplex = <1>; - }; -}; - -/* eth1 is connected to the switch at port 6. However DSA only supports a - * single CPU port. So leave this port disabled to avoid confusion. - */ -ð1 { - status = "disabled"; -}; - -/* There is no battery on the board, so the RTC does not keep - * time when there is no power, making it useless. - */ -&rtc { - status = "disabled"; -}; - diff --git a/sys/gnu/dts/arm/kirkwood-lschlv2.dts b/sys/gnu/dts/arm/kirkwood-lschlv2.dts deleted file mode 100644 index 1d737d903f5..00000000000 --- a/sys/gnu/dts/arm/kirkwood-lschlv2.dts +++ /dev/null @@ -1,20 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "kirkwood-lsxl.dtsi" - -/ { - model = "Buffalo Linkstation LS-CHLv2"; - compatible = "buffalo,lschlv2", "buffalo,lsxl", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x4000000>; - }; - - ocp@f1000000 { - serial@12000 { - status = "okay"; - }; - }; -}; diff --git a/sys/gnu/dts/arm/kirkwood-lswvl.dts b/sys/gnu/dts/arm/kirkwood-lswvl.dts deleted file mode 100644 index 09eed3cea0a..00000000000 --- a/sys/gnu/dts/arm/kirkwood-lswvl.dts +++ /dev/null @@ -1,301 +0,0 @@ -/* - * Device Tree file for Buffalo Linkstation LS-WVL/VL - * - * Copyright (C) 2015, rogershimizu@gmail.com - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6282.dtsi" - -/ { - model = "Buffalo Linkstation LS-WVL/VL"; - compatible = "buffalo,lswvl", "buffalo,lsvl", "marvell,kirkwood-88f6282", "marvell,kirkwood"; - - memory { /* 256 MB */ - device_type = "memory"; - reg = <0x00000000 0x10000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; - }; - - mbus { - pcie-controller { - status = "okay"; - pcie@1,0 { - status = "okay"; - }; - }; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pmx_power_hdd0: pmx-power-hdd0 { - marvell,pins = "mpp8"; - marvell,function = "gpio"; - }; - pmx_power_hdd1: pmx-power-hdd1 { - marvell,pins = "mpp9"; - marvell,function = "gpio"; - }; - pmx_usb_vbus: pmx-usb-vbus { - marvell,pins = "mpp12"; - marvell,function = "gpio"; - }; - pmx_fan_high: pmx-fan-high { - marvell,pins = "mpp16"; - marvell,function = "gpio"; - }; - pmx_fan_low: pmx-fan-low { - marvell,pins = "mpp17"; - marvell,function = "gpio"; - }; - pmx_led_hdderr0: pmx-led-hdderr0 { - marvell,pins = "mpp34"; - marvell,function = "gpio"; - }; - pmx_led_hdderr1: pmx-led-hdderr1 { - marvell,pins = "mpp35"; - marvell,function = "gpio"; - }; - pmx_led_alarm: pmx-led-alarm { - marvell,pins = "mpp36"; - marvell,function = "gpio"; - }; - pmx_led_function_red: pmx-led-function-red { - marvell,pins = "mpp37"; - marvell,function = "gpio"; - }; - pmx_led_info: pmx-led-info { - marvell,pins = "mpp38"; - marvell,function = "gpio"; - }; - pmx_led_function_blue: pmx-led-function-blue { - marvell,pins = "mpp39"; - marvell,function = "gpio"; - }; - pmx_led_power: pmx-led-power { - marvell,pins = "mpp40"; - marvell,function = "gpio"; - }; - pmx_fan_lock: pmx-fan-lock { - marvell,pins = "mpp43"; - marvell,function = "gpio"; - }; - pmx_button_function: pmx-button-function { - marvell,pins = "mpp45"; - marvell,function = "gpio"; - }; - pmx_power_switch: pmx-power-switch { - marvell,pins = "mpp46"; - marvell,function = "gpio"; - }; - pmx_power_auto_switch: pmx-power-auto-switch { - marvell,pins = "mpp47"; - marvell,function = "gpio"; - }; - }; - - serial@12000 { - status = "okay"; - }; - - sata@80000 { - status = "okay"; - nr-ports = <2>; - }; - - spi@10600 { - status = "okay"; - - m25p40@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,m25p40", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <25000000>; - mode = <0>; - - partition@0 { - reg = <0x0 0x60000>; - label = "uboot"; - read-only; - }; - - partition@60000 { - reg = <0x60000 0x10000>; - label = "dtb"; - read-only; - }; - - partition@70000 { - reg = <0x70000 0x10000>; - label = "uboot_env"; - }; - }; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_button_function &pmx_power_switch - &pmx_power_auto_switch>; - pinctrl-names = "default"; - - button@1 { - label = "Function Button"; - linux,code = ; - gpios = <&gpio0 45 GPIO_ACTIVE_LOW>; - }; - - button@2 { - label = "Power-on Switch"; - linux,code = ; - linux,input-type = <5>; - gpios = <&gpio0 46 GPIO_ACTIVE_LOW>; - }; - - button@3 { - label = "Power-auto Switch"; - linux,code = ; - linux,input-type = <5>; - gpios = <&gpio0 47 GPIO_ACTIVE_LOW>; - }; - }; - - gpio_leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_led_function_red &pmx_led_alarm - &pmx_led_info &pmx_led_power - &pmx_led_function_blue - &pmx_led_hdderr0 - &pmx_led_hdderr1>; - pinctrl-names = "default"; - - led@1 { - label = "lswvl:red:alarm"; - gpios = <&gpio0 36 GPIO_ACTIVE_LOW>; - }; - - led@2 { - label = "lswvl:red:func"; - gpios = <&gpio0 37 GPIO_ACTIVE_LOW>; - }; - - led@3 { - label = "lswvl:amber:info"; - gpios = <&gpio0 38 GPIO_ACTIVE_LOW>; - }; - - led@4 { - label = "lswvl:blue:func"; - gpios = <&gpio0 39 GPIO_ACTIVE_LOW>; - }; - - led@5 { - label = "lswvl:blue:power"; - gpios = <&gpio0 40 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - - led@6 { - label = "lswvl:red:hdderr0"; - gpios = <&gpio0 34 GPIO_ACTIVE_LOW>; - }; - - led@7 { - label = "lswvl:red:hdderr1"; - gpios = <&gpio0 35 GPIO_ACTIVE_LOW>; - }; - }; - - gpio_fan { - compatible = "gpio-fan"; - pinctrl-0 = <&pmx_fan_low &pmx_fan_high &pmx_fan_lock>; - pinctrl-names = "default"; - - gpios = <&gpio0 17 GPIO_ACTIVE_LOW - &gpio0 16 GPIO_ACTIVE_LOW>; - - gpio-fan,speed-map = <0 3 - 1500 2 - 3250 1 - 5000 0>; - - alarm-gpios = <&gpio0 43 GPIO_ACTIVE_HIGH>; - }; - - restart_poweroff { - compatible = "restart-poweroff"; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_power_hdd0 &pmx_power_hdd1 &pmx_usb_vbus>; - pinctrl-names = "default"; - - usb_power: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "USB Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>; - }; - hdd_power0: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "HDD0 Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 8 GPIO_ACTIVE_HIGH>; - }; - hdd_power1: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "HDD1 Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 9 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@0 { - device_type = "ethernet-phy"; - reg = <0>; - }; -}; - -ð0 { - status = "okay"; - - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; diff --git a/sys/gnu/dts/arm/kirkwood-lswxl.dts b/sys/gnu/dts/arm/kirkwood-lswxl.dts deleted file mode 100644 index f5db16a0859..00000000000 --- a/sys/gnu/dts/arm/kirkwood-lswxl.dts +++ /dev/null @@ -1,301 +0,0 @@ -/* - * Device Tree file for Buffalo Linkstation LS-WXL/WSXL - * - * Copyright (C) 2015, rogershimizu@gmail.com - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - model = "Buffalo Linkstation LS-WXL/WSXL"; - compatible = "buffalo,lswxl", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { /* 128 MB */ - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; - }; - - mbus { - pcie-controller { - status = "okay"; - pcie@1,0 { - status = "okay"; - }; - }; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pmx_power_hdd0: pmx-power-hdd0 { - marvell,pins = "mpp28"; - marvell,function = "gpio"; - }; - pmx_power_hdd1: pmx-power-hdd1 { - marvell,pins = "mpp29"; - marvell,function = "gpio"; - }; - pmx_usb_vbus: pmx-usb-vbus { - marvell,pins = "mpp37"; - marvell,function = "gpio"; - }; - pmx_fan_high: pmx-fan-high { - marvell,pins = "mpp47"; - marvell,function = "gpio"; - }; - pmx_fan_low: pmx-fan-low { - marvell,pins = "mpp48"; - marvell,function = "gpio"; - }; - pmx_led_hdderr0: pmx-led-hdderr0 { - marvell,pins = "mpp8"; - marvell,function = "gpio"; - }; - pmx_led_hdderr1: pmx-led-hdderr1 { - marvell,pins = "mpp46"; - marvell,function = "gpio"; - }; - pmx_led_alarm: pmx-led-alarm { - marvell,pins = "mpp49"; - marvell,function = "gpio"; - }; - pmx_led_function_red: pmx-led-function-red { - marvell,pins = "mpp34"; - marvell,function = "gpio"; - }; - pmx_led_function_blue: pmx-led-function-blue { - marvell,pins = "mpp36"; - marvell,function = "gpio"; - }; - pmx_led_info: pmx-led-info { - marvell,pins = "mpp38"; - marvell,function = "gpio"; - }; - pmx_led_power: pmx-led-power { - marvell,pins = "mpp39"; - marvell,function = "gpio"; - }; - pmx_fan_lock: pmx-fan-lock { - marvell,pins = "mpp40"; - marvell,function = "gpio"; - }; - pmx_button_function: pmx-button-function { - marvell,pins = "mpp41"; - marvell,function = "gpio"; - }; - pmx_power_switch: pmx-power-switch { - marvell,pins = "mpp42"; - marvell,function = "gpio"; - }; - pmx_power_auto_switch: pmx-power-auto-switch { - marvell,pins = "mpp43"; - marvell,function = "gpio"; - }; - }; - - serial@12000 { - status = "okay"; - }; - - sata@80000 { - status = "okay"; - nr-ports = <2>; - }; - - spi@10600 { - status = "okay"; - - m25p40@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,m25p40", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <25000000>; - mode = <0>; - - partition@0 { - reg = <0x0 0x60000>; - label = "uboot"; - read-only; - }; - - partition@60000 { - reg = <0x60000 0x10000>; - label = "dtb"; - read-only; - }; - - partition@70000 { - reg = <0x70000 0x10000>; - label = "uboot_env"; - }; - }; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_button_function &pmx_power_switch - &pmx_power_auto_switch>; - pinctrl-names = "default"; - - button@1 { - label = "Function Button"; - linux,code = ; - gpios = <&gpio1 41 GPIO_ACTIVE_LOW>; - }; - - button@2 { - label = "Power-on Switch"; - linux,code = ; - linux,input-type = <5>; - gpios = <&gpio1 42 GPIO_ACTIVE_LOW>; - }; - - button@3 { - label = "Power-auto Switch"; - linux,code = ; - linux,input-type = <5>; - gpios = <&gpio1 43 GPIO_ACTIVE_LOW>; - }; - }; - - gpio_leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_led_function_red &pmx_led_alarm - &pmx_led_info &pmx_led_power - &pmx_led_function_blue - &pmx_led_hdderr0 - &pmx_led_hdderr1>; - pinctrl-names = "default"; - - led@1 { - label = "lswxl:blue:func"; - gpios = <&gpio1 36 GPIO_ACTIVE_LOW>; - }; - - led@2 { - label = "lswxl:red:alarm"; - gpios = <&gpio1 49 GPIO_ACTIVE_LOW>; - }; - - led@3 { - label = "lswxl:amber:info"; - gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; - }; - - led@4 { - label = "lswxl:blue:power"; - gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; - }; - - led@5 { - label = "lswxl:red:func"; - gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - - led@6 { - label = "lswxl:red:hdderr0"; - gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; - }; - - led@7 { - label = "lswxl:red:hdderr1"; - gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; - }; - }; - - gpio_fan { - compatible = "gpio-fan"; - pinctrl-0 = <&pmx_fan_low &pmx_fan_high &pmx_fan_lock>; - pinctrl-names = "default"; - - gpios = <&gpio0 47 GPIO_ACTIVE_LOW - &gpio0 48 GPIO_ACTIVE_LOW>; - - gpio-fan,speed-map = <0 3 - 1500 2 - 3250 1 - 5000 0>; - - alarm-gpios = <&gpio1 49 GPIO_ACTIVE_HIGH>; - }; - - restart_poweroff { - compatible = "restart-poweroff"; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_power_hdd0 &pmx_power_hdd1 &pmx_usb_vbus>; - pinctrl-names = "default"; - - usb_power: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "USB Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 37 GPIO_ACTIVE_HIGH>; - }; - hdd_power0: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "HDD0 Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 28 GPIO_ACTIVE_HIGH>; - }; - hdd_power1: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "HDD1 Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 29 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&mdio { - status = "okay"; - - ethphy1: ethernet-phy@8 { - device_type = "ethernet-phy"; - reg = <8>; - }; -}; - -ð1 { - status = "okay"; - - ethernet1-port@0 { - phy-handle = <ðphy1>; - }; -}; diff --git a/sys/gnu/dts/arm/kirkwood-lsxhl.dts b/sys/gnu/dts/arm/kirkwood-lsxhl.dts deleted file mode 100644 index a56e0d79777..00000000000 --- a/sys/gnu/dts/arm/kirkwood-lsxhl.dts +++ /dev/null @@ -1,20 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "kirkwood-lsxl.dtsi" - -/ { - model = "Buffalo Linkstation LS-XHL"; - compatible = "buffalo,lsxhl", "buffalo,lsxl", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x10000000>; - }; - - ocp@f1000000 { - serial@12000 { - status = "okay"; - }; - }; -}; diff --git a/sys/gnu/dts/arm/kirkwood-lsxl.dtsi b/sys/gnu/dts/arm/kirkwood-lsxl.dtsi deleted file mode 100644 index 7b151acb998..00000000000 --- a/sys/gnu/dts/arm/kirkwood-lsxl.dtsi +++ /dev/null @@ -1,237 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pmx_power_hdd: pmx-power-hdd { - marvell,pins = "mpp10"; - marvell,function = "gpo"; - }; - pmx_usb_vbus: pmx-usb-vbus { - marvell,pins = "mpp11"; - marvell,function = "gpio"; - }; - pmx_fan_high: pmx-fan-high { - marvell,pins = "mpp18"; - marvell,function = "gpo"; - }; - pmx_fan_low: pmx-fan-low { - marvell,pins = "mpp19"; - marvell,function = "gpo"; - }; - pmx_led_function_blue: pmx-led-function-blue { - marvell,pins = "mpp36"; - marvell,function = "gpio"; - }; - pmx_led_alarm: pmx-led-alarm { - marvell,pins = "mpp37"; - marvell,function = "gpio"; - }; - pmx_led_info: pmx-led-info { - marvell,pins = "mpp38"; - marvell,function = "gpio"; - }; - pmx_led_power: pmx-led-power { - marvell,pins = "mpp39"; - marvell,function = "gpio"; - }; - pmx_fan_lock: pmx-fan-lock { - marvell,pins = "mpp40"; - marvell,function = "gpio"; - }; - pmx_button_function: pmx-button-function { - marvell,pins = "mpp41"; - marvell,function = "gpio"; - }; - pmx_power_switch: pmx-power-switch { - marvell,pins = "mpp42"; - marvell,function = "gpio"; - }; - pmx_power_auto_switch: pmx-power-auto-switch { - marvell,pins = "mpp43"; - marvell,function = "gpio"; - }; - pmx_led_function_red: pmx-led-function_red { - marvell,pins = "mpp48"; - marvell,function = "gpio"; - }; - - }; - sata@80000 { - status = "okay"; - nr-ports = <1>; - }; - - spi@10600 { - status = "okay"; - - m25p40@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "m25p40", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <25000000>; - mode = <0>; - - partition@0 { - reg = <0x0 0x60000>; - label = "uboot"; - read-only; - }; - - partition@60000 { - reg = <0x60000 0x10000>; - label = "dtb"; - read-only; - }; - - partition@70000 { - reg = <0x70000 0x10000>; - label = "uboot_env"; - }; - }; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_button_function &pmx_power_switch - &pmx_power_auto_switch>; - pinctrl-names = "default"; - - option { - label = "Function Button"; - linux,code = ; - gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; - }; - reserved { - label = "Power-on Switch"; - linux,code = ; - linux,input-type = <5>; - gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; - }; - power { - label = "Power-auto Switch"; - linux,code = ; - linux,input-type = <5>; - gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; - }; - }; - - gpio_leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_led_function_red &pmx_led_alarm - &pmx_led_info &pmx_led_power - &pmx_led_function_blue>; - pinctrl-names = "default"; - - func_blue { - label = "lsxl:blue:func"; - gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - }; - - alarm { - label = "lsxl:red:alarm"; - gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; - }; - - info { - label = "lsxl:amber:info"; - gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; - }; - - power { - label = "lsxl:blue:power"; - gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - - func_red { - label = "lsxl:red:func"; - gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; - }; - }; - - gpio_fan { - compatible = "gpio-fan"; - pinctrl-0 = <&pmx_fan_low &pmx_fan_high &pmx_fan_lock>; - pinctrl-names = "default"; - gpios = <&gpio0 19 GPIO_ACTIVE_LOW - &gpio0 18 GPIO_ACTIVE_LOW>; - gpio-fan,speed-map = <0 3 - 1500 2 - 3250 1 - 5000 0>; - alarm-gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; - }; - - restart_poweroff { - compatible = "restart-poweroff"; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_power_hdd &pmx_usb_vbus>; - pinctrl-names = "default"; - - usb_power: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "USB Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 11 0>; - }; - hdd_power: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "HDD Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 10 0>; - }; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; - - ethphy1: ethernet-phy@8 { - reg = <8>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; - -ð1 { - status = "okay"; - ethernet1-port@0 { - phy-handle = <ðphy1>; - }; -}; diff --git a/sys/gnu/dts/arm/kirkwood-mplcec4.dts b/sys/gnu/dts/arm/kirkwood-mplcec4.dts deleted file mode 100644 index b80d12f6aa4..00000000000 --- a/sys/gnu/dts/arm/kirkwood-mplcec4.dts +++ /dev/null @@ -1,216 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - model = "MPL CEC4"; - compatible = "mpl,cec4-10", "mpl,cec4", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x20000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pmx_led_health: pmx-led-health { - marvell,pins = "mpp7"; - marvell,function = "gpo"; - }; - - pmx_sata1: pmx-sata1 { - marvell,pins = "mpp34"; - marvell,function = "sata1"; - }; - - pmx_sata0: pmx-sata0 { - marvell,pins = "mpp35"; - marvell,function = "sata0"; - }; - - pmx_led_user1o: pmx-led-user1o { - marvell,pins = "mpp40"; - marvell,function = "gpio"; - }; - - pmx_led_user1g: pmx-led-user1g { - marvell,pins = "mpp41"; - marvell,function = "gpio"; - }; - - pmx_led_user0o: pmx-led-user0o { - marvell,pins = "mpp44"; - marvell,function = "gpio"; - }; - - pmx_led_user0g: pmx-led-user0g { - marvell,pins = "mpp45"; - marvell,function = "gpio"; - }; - - pmx_led_misc: pmx-led-misc { - marvell,pins = "mpp46"; - marvell,function = "gpio"; - }; - - pmx_sdio_cd: pmx-sdio-cd { - marvell,pins = "mpp47"; - marvell,function = "gpio"; - }; - }; - - i2c@11000 { - status = "okay"; - - rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; - - eeprom@57 { - compatible = "atmel,24c02"; - reg = <0x57>; - }; - - }; - - serial@12000 { - status = "okay"; - }; - - rtc@10300 { - status = "disabled"; - }; - - sata@80000 { - pinctrl-0 = <&pmx_sata0 &pmx_sata1>; - pinctrl-names = "default"; - nr-ports = <2>; - status = "okay"; - }; - - mvsdio@90000 { - pinctrl-0 = <&pmx_sdio &pmx_sdio_cd>; - pinctrl-names = "default"; - status = "okay"; - cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; - /* No WP GPIO */ - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = < &pmx_led_health - &pmx_led_user1o - &pmx_led_user1g &pmx_led_user0o - &pmx_led_user0g &pmx_led_misc - >; - pinctrl-names = "default"; - - health { - label = "status:green:health"; - gpios = <&gpio0 7 GPIO_ACTIVE_LOW>; - }; - - user1o { - label = "user1:orange"; - gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; - default-state = "on"; - }; - - user1g { - label = "user1:green"; - gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; - default-state = "on"; - }; - - user0o { - label = "user0:orange"; - gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; - default-state = "on"; - }; - - user0g { - label = "user0:green"; - gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; - default-state = "on"; - }; - - misc { - label = "status:orange:misc"; - gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; - default-state = "on"; - }; - - }; -}; - -&nand { - status = "okay"; - - partition@0 { - label = "uboot"; - reg = <0x0000000 0x100000>; - }; - - partition@100000 { - label = "env"; - reg = <0x100000 0x80000>; - }; - - partition@180000 { - label = "fdt"; - reg = <0x180000 0x80000>; - }; - - partition@200000 { - label = "kernel"; - reg = <0x200000 0x400000>; - }; - - partition@600000 { - label = "rootfs"; - reg = <0x600000 0x1fa00000>; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@1 { - reg = <1>; - }; - - ethphy1: ethernet-phy@2 { - reg = <2>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; - -ð1 { - status = "okay"; - ethernet1-port@0 { - phy-handle = <ðphy1>; - }; -}; - -&pciec { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/kirkwood-mv88f6281gtw-ge.dts b/sys/gnu/dts/arm/kirkwood-mv88f6281gtw-ge.dts deleted file mode 100644 index 2e1a7534890..00000000000 --- a/sys/gnu/dts/arm/kirkwood-mv88f6281gtw-ge.dts +++ /dev/null @@ -1,178 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Marvell 88F6281 GTW GE Board - * - * Lennert Buytenhek - * Thomas Petazzoni - * - * This file contains the definitions that are common between the 6281 - * and 6282 variants of the Marvell Kirkwood Development Board. - */ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - model = "Marvell 88F6281 GTW GE Board"; - compatible = "marvell,mv88f6281gtw-ge", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x20000000>; /* 512 MB */ - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pin-controller@10000 { - pmx_usb_led: pmx-usb-led { - marvell,pins = "mpp12"; - marvell,function = "gpo"; - }; - - pmx_leds: pmx-leds { - marvell,pins = "mpp20", "mpp21"; - marvell,function = "gpio"; - }; - - pmx_keys: pmx-keys { - marvell,pins = "mpp46", "mpp47"; - marvell,function = "gpio"; - }; - }; - - spi@10600 { - status = "okay"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "mxicy,mx25l12805d", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <50000000>; - mode = <0>; - }; - }; - - serial@12000 { - status = "okay"; - }; - - ehci@50000 { - status = "okay"; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_leds &pmx_usb_led>; - pinctrl-names = "default"; - - green-status { - label = "gtw:green:Status"; - gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>; - }; - - red-status { - label = "gtw:red:Status"; - gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>; - }; - - green-usb { - label = "gtw:green:USB"; - gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_keys>; - pinctrl-names = "default"; - - restart { - label = "SWR Button"; - linux,code = ; - gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; - }; - wps { - label = "WPS Button"; - linux,code = ; - gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&mdio { - status = "okay"; - - switch@0 { - compatible = "marvell,mv88e6085"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "lan1"; - }; - - port@1 { - reg = <1>; - label = "lan2"; - }; - - port@2 { - reg = <2>; - label = "lan3"; - }; - - port@3 { - reg = <3>; - label = "lan4"; - }; - - port@4 { - reg = <4>; - label = "wan"; - }; - - port@5 { - reg = <5>; - label = "cpu"; - ethernet = <ð0port>; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; - }; -}; - -ð0 { - status = "okay"; - - ethernet0-port@0 { - speed = <1000>; - duplex = <1>; - }; -}; - -&pciec { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/kirkwood-nas2big.dts b/sys/gnu/dts/arm/kirkwood-nas2big.dts deleted file mode 100644 index 6a2934b7d0c..00000000000 --- a/sys/gnu/dts/arm/kirkwood-nas2big.dts +++ /dev/null @@ -1,139 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree file for LaCie 2Big NAS - * - * Copyright (C) 2015 Seagate - * - * Author: Simon Guinot - * -*/ - -/dts-v1/; - -#include "kirkwood-netxbig.dtsi" - -/ { - model = "LaCie 2Big NAS"; - compatible = "lacie,nas2big", "lacie,netxbig", "marvell,kirkwood-88f6282", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x10000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - rtc@10300 { - /* The on-chip RTC is not powered (no supercap). */ - status = "disabled"; - }; - spi@10600 { - /* - * A NAND flash is used instead of an SPI flash for - * the other netxbig-compatible boards. - */ - status = "disabled"; - }; - }; - - fan { - /* - * An I2C fan controller (GMT G762) is used but alarm is - * wired to a separate GPIO. - */ - compatible = "gpio-fan"; - alarm-gpios = <&gpio0 25 GPIO_ACTIVE_LOW>; - }; - - regulators: regulators { - status = "okay"; - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - - regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "hdd1power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 17 GPIO_ACTIVE_HIGH>; - }; - clocks { - g762_clk: g762-oscillator { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -&i2c0 { - status = "okay"; - - /* - * An external I2C RTC (Dallas DS1337S+) is used. This allows - * to power-up the board on an RTC alarm. The external RTC can - * be kept powered, even when the SoC is off. - */ - rtc@68 { - compatible = "dallas,ds1307"; - reg = <0x68>; - interrupts = <43>; - }; - g762@3e { - compatible = "gmt,g762"; - reg = <0x3e>; - clocks = <&g762_clk>; - }; -}; - -&nand { - chip-delay = <50>; - status = "okay"; - - partition@0 { - label = "U-Boot"; - reg = <0x0 0x100000>; - }; - - partition@100000 { - label = "uImage"; - reg = <0x100000 0x1000000>; - }; - - partition@1100000 { - label = "root"; - reg = <0x1100000 0x8000000>; - }; - - partition@9100000 { - label = "unused"; - reg = <0x9100000 0x6f00000>; - }; -}; - -&pciec { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/kirkwood-net2big.dts b/sys/gnu/dts/arm/kirkwood-net2big.dts deleted file mode 100644 index 3e3ac289e5b..00000000000 --- a/sys/gnu/dts/arm/kirkwood-net2big.dts +++ /dev/null @@ -1,63 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree file for LaCie 2Big Network v2 - * - * Copyright (C) 2014 - * - * Andrew Lunn - * - * Based on netxbig_v2-setup.c, - * Copyright (C) 2010 Simon Guinot - * -*/ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" -#include "kirkwood-netxbig.dtsi" - -/ { - model = "LaCie 2Big Network v2"; - compatible = "lacie,net2big_v2", "lacie,netxbig", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x10000000>; - }; - - fan { - compatible = "gpio-fan"; - alarm-gpios = <&gpio0 25 GPIO_ACTIVE_LOW>; - }; -}; - -®ulators { - regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "hdd1power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 17 GPIO_ACTIVE_HIGH>; - }; - - clocks { - g762_clk: g762-oscillator { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; -}; - -&i2c0 { - g762@3e { - compatible = "gmt,g762"; - reg = <0x3e>; - clocks = <&g762_clk>; - }; -}; diff --git a/sys/gnu/dts/arm/kirkwood-net5big.dts b/sys/gnu/dts/arm/kirkwood-net5big.dts deleted file mode 100644 index cba8a2b6f6d..00000000000 --- a/sys/gnu/dts/arm/kirkwood-net5big.dts +++ /dev/null @@ -1,169 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree file for LaCie 5Big Network v2 - * - * Copyright (C) 2014 - * - * Andrew Lunn - * - * Based on netxbig_v2-setup.c, - * Copyright (C) 2010 Simon Guinot - * -*/ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" -#include "kirkwood-netxbig.dtsi" - -/ { - model = "LaCie 5Big Network v2"; - compatible = "lacie,net5big_v2", "lacie,netxbig", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x20000000>; - }; - -}; - -®ulators { - regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "hdd1power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 17 GPIO_ACTIVE_HIGH>; - }; - - regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "hdd2power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; - }; - - regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "hdd3power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>; - }; - - regulator@5 { - compatible = "regulator-fixed"; - reg = <5>; - regulator-name = "hdd4power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio1 11 GPIO_ACTIVE_HIGH>; - }; - - clocks { - g762_clk: g762-oscillator { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - netxbig-leds { - blue-sata2 { - label = "netxbig:blue:sata2"; - mode-addr = <5>; - mode-val = ; - bright-addr = <2>; - max-brightness = <7>; - }; - red-sata2 { - label = "netxbig:red:sata2"; - mode-addr = <5>; - mode-val = ; - bright-addr = <2>; - max-brightness = <7>; - }; - blue-sata3 { - label = "netxbig:blue:sata3"; - mode-addr = <6>; - mode-val = ; - bright-addr = <2>; - max-brightness = <7>; - }; - red-sata3 { - label = "netxbig:red:sata3"; - mode-addr = <6>; - mode-val = ; - bright-addr = <2>; - max-brightness = <7>; - }; - blue-sata4 { - label = "netxbig:blue:sata4"; - mode-addr = <7>; - mode-val = ; - bright-addr = <2>; - max-brightness = <7>; - }; - red-sata4 { - label = "netxbig:red:sata4"; - mode-addr = <7>; - mode-val = ; - bright-addr = <2>; - max-brightness = <7>; - }; - }; -}; - -&mdio { - ethphy1: ethernet-phy@1 { - reg = <0>; - }; -}; - -ð1 { - status = "okay"; - ethernet1-port@0 { - phy-handle = <ðphy1>; - }; -}; - - -&i2c0 { - g762@3e { - compatible = "gmt,g762"; - reg = <0x3e>; - clocks = <&g762_clk>; - }; -}; diff --git a/sys/gnu/dts/arm/kirkwood-netgear_readynas_duo_v2.dts b/sys/gnu/dts/arm/kirkwood-netgear_readynas_duo_v2.dts deleted file mode 100644 index cb564c3bcdc..00000000000 --- a/sys/gnu/dts/arm/kirkwood-netgear_readynas_duo_v2.dts +++ /dev/null @@ -1,247 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Device Tree file for NETGEAR ReadyNAS Duo v2 - * - * Copyright (C) 2013, Arnaud EBALARD - */ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6282.dtsi" - -/ { - model = "NETGEAR ReadyNAS Duo v2"; - compatible = "netgear,readynas-duo-v2", "netgear,readynas", "marvell,kirkwood-88f6282", "marvell,kirkwood"; - - memory { /* 256 MB */ - device_type = "memory"; - reg = <0x00000000 0x10000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pmx_button_power: pmx-button-power { - marvell,pins = "mpp47"; - marvell,function = "gpio"; - }; - - pmx_button_backup: pmx-button-backup { - marvell,pins = "mpp45"; - marvell,function = "gpio"; - }; - - pmx_button_reset: pmx-button-reset { - marvell,pins = "mpp13"; - marvell,function = "gpio"; - }; - - pmx_led_blue_power: pmx-led-blue-power { - marvell,pins = "mpp31"; - marvell,function = "gpio"; - }; - - pmx_led_blue_activity: pmx-led-blue-activity { - marvell,pins = "mpp38"; - marvell,function = "gpio"; - }; - - pmx_led_blue_disk1: pmx-led-blue-disk1 { - marvell,pins = "mpp23"; - marvell,function = "gpio"; - }; - - pmx_led_blue_disk2: pmx-led-blue-disk2 { - marvell,pins = "mpp22"; - marvell,function = "gpio"; - }; - - pmx_led_blue_backup: pmx-led-blue-backup { - marvell,pins = "mpp29"; - marvell,function = "gpio"; - }; - - pmx_poweroff: pmx-poweroff { - marvell,pins = "mpp30"; - marvell,function = "gpio"; - }; - }; - - clocks { - g762_clk: g762-oscillator { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <8192>; - }; - }; - - i2c@11000 { - status = "okay"; - - rs5c372a: rs5c372a@32 { - compatible = "ricoh,rs5c372a"; - reg = <0x32>; - }; - - g762: g762@3e { - compatible = "gmt,g762"; - reg = <0x3e>; - clocks = <&g762_clk>; /* input clock */ - fan_gear_mode = <0>; - fan_startv = <1>; - pwm_polarity = <0>; - }; - }; - - serial@12000 { - status = "okay"; - }; - - sata@80000 { - status = "okay"; - nr-ports = <2>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = < &pmx_led_blue_power &pmx_led_blue_activity - &pmx_led_blue_disk1 &pmx_led_blue_disk2 - &pmx_led_blue_backup >; - pinctrl-names = "default"; - - power_led { - label = "status:blue:power_led"; - gpios = <&gpio0 31 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - - activity_led { - label = "status:blue:activity_led"; - gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; - }; - - disk1_led { - label = "status:blue:disk1_led"; - gpios = <&gpio0 23 GPIO_ACTIVE_LOW>; - }; - - disk2_led { - label = "status:blue:disk2_led"; - gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; - }; - - backup_led { - label = "status:blue:backup_led"; - gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-0 = <&pmx_button_power &pmx_button_backup - &pmx_button_reset>; - pinctrl-names = "default"; - - power-button { - label = "Power Button"; - linux,code = ; - gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; - }; - - reset-button { - label = "Reset Button"; - linux,code = ; - gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; - }; - - backup-button { - label = "Backup Button"; - linux,code = ; - gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-poweroff { - compatible = "gpio-poweroff"; - pinctrl-0 = <&pmx_poweroff>; - pinctrl-names = "default"; - gpios = <&gpio0 30 GPIO_ACTIVE_LOW>; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - usb3_regulator: usb3-regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "USB 3.0 Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&nand { - status = "okay"; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0x180000>; - read-only; - }; - - partition@180000 { - label = "u-boot-env"; - reg = <0x180000 0x20000>; - }; - - partition@200000 { - label = "uImage"; - reg = <0x0200000 0x600000>; - }; - - partition@800000 { - label = "minirootfs"; - reg = <0x0800000 0x1000000>; - }; - - partition@1800000 { - label = "jffs2"; - reg = <0x1800000 0x6800000>; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@0 { /* Marvell 88E1318 */ - reg = <0>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; - -&pciec { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/kirkwood-netgear_readynas_nv+_v2.dts b/sys/gnu/dts/arm/kirkwood-netgear_readynas_nv+_v2.dts deleted file mode 100644 index 8cc8550242e..00000000000 --- a/sys/gnu/dts/arm/kirkwood-netgear_readynas_nv+_v2.dts +++ /dev/null @@ -1,260 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Device Tree file for NETGEAR ReadyNAS NV+ v2 - * - * Copyright (C) 2013, Arnaud EBALARD - */ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6282.dtsi" - -/ { - model = "NETGEAR ReadyNAS NV+ v2"; - compatible = "netgear,readynas-nv+-v2", "netgear,readynas", "marvell,kirkwood-88f6282", "marvell,kirkwood"; - - memory { /* 256 MB */ - device_type = "memory"; - reg = <0x00000000 0x10000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pmx_button_power: pmx-button-power { - marvell,pins = "mpp47"; - marvell,function = "gpio"; - }; - - pmx_button_backup: pmx-button-backup { - marvell,pins = "mpp45"; - marvell,function = "gpio"; - }; - - pmx_button_reset: pmx-button-reset { - marvell,pins = "mpp13"; - marvell,function = "gpio"; - }; - - pmx_led_blue_power: pmx-led-blue-power { - marvell,pins = "mpp31"; - marvell,function = "gpio"; - }; - - pmx_led_blue_backup: pmx-led-blue-backup { - marvell,pins = "mpp22"; - marvell,function = "gpio"; - }; - - pmx_led_blue_disk1: pmx-led-blue-disk1 { - marvell,pins = "mpp20"; - marvell,function = "gpio"; - }; - - pmx_led_blue_disk2: pmx-led-blue-disk2 { - marvell,pins = "mpp23"; - marvell,function = "gpio"; - }; - - pmx_led_blue_disk3: pmx-led-blue-disk3 { - marvell,pins = "mpp24"; - marvell,function = "gpio"; - }; - - pmx_led_blue_disk4: pmx-led-blue-disk4 { - marvell,pins = "mpp29"; - marvell,function = "gpio"; - }; - - pmx_poweroff: pmx-poweroff { - marvell,pins = "mpp30"; - marvell,function = "gpio"; - }; - }; - - clocks { - g762_clk: g762-oscillator { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <8192>; - }; - }; - - i2c@11000 { - status = "okay"; - - rs5c372a: rs5c372a@32 { - compatible = "ricoh,rs5c372a"; - reg = <0x32>; - }; - - g762: g762@3e { - compatible = "gmt,g762"; - reg = <0x3e>; - clocks = <&g762_clk>; /* input clock */ - fan_gear_mode = <0>; - fan_startv = <1>; - pwm_polarity = <0>; - }; - }; - - serial@12000 { - status = "okay"; - }; - - sata@80000 { /* Connected to Marvell 88SM4140 SATA port multiplier */ - status = "okay"; - nr-ports = <1>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = < &pmx_led_blue_power &pmx_led_blue_backup - &pmx_led_blue_disk1 &pmx_led_blue_disk2 - &pmx_led_blue_disk3 &pmx_led_blue_disk3 >; - pinctrl-names = "default"; - - power_led { - label = "status:blue:power_led"; - gpios = <&gpio0 31 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-on"; - }; - - backup_led { - label = "status:blue:backup_led"; - gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; - }; - - disk1_led { - label = "status:blue:disk1_led"; - gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; - }; - - disk2_led { - label = "status:blue:disk2_led"; - gpios = <&gpio0 23 GPIO_ACTIVE_LOW>; - }; - - disk3_led { - label = "status:blue:disk3_led"; - gpios = <&gpio0 24 GPIO_ACTIVE_LOW>; - }; - - disk4_led { - label = "status:blue:disk4_led"; - gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-0 = <&pmx_button_power &pmx_button_backup - &pmx_button_reset>; - pinctrl-names = "default"; - - power-button { - label = "Power Button"; - linux,code = ; - gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; - }; - - reset-button { - label = "Reset Button"; - linux,code = ; - gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; - }; - - backup-button { - label = "Backup Button"; - linux,code = ; - gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-poweroff { - compatible = "gpio-poweroff"; - pinctrl-0 = <&pmx_poweroff>; - pinctrl-names = "default"; - gpios = <&gpio0 30 GPIO_ACTIVE_LOW>; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - usb3_regulator: usb3-regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "USB 3.0 Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&nand { - status = "okay"; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0x180000>; - read-only; - }; - - partition@180000 { - label = "u-boot-env"; - reg = <0x180000 0x20000>; - }; - - partition@200000 { - label = "uImage"; - reg = <0x0200000 0x600000>; - }; - - partition@800000 { - label = "minirootfs"; - reg = <0x0800000 0x1000000>; - }; - - partition@1800000 { - label = "jffs2"; - reg = <0x1800000 0x6800000>; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@0 { /* Marvell 88E1318 */ - device_type = "ethernet-phy"; - reg = <0>; - }; -}; - -ð0 { - status = "okay"; - - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; - -/* Connected to NEC uPD720200 USB 3.0 controller */ -&pciec { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/kirkwood-netxbig.dtsi b/sys/gnu/dts/arm/kirkwood-netxbig.dtsi deleted file mode 100644 index b5737026e24..00000000000 --- a/sys/gnu/dts/arm/kirkwood-netxbig.dtsi +++ /dev/null @@ -1,232 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree common file for LaCie 2Big and 5Big Network v2 - * - * Copyright (C) 2014 - * - * Andrew Lunn - * - * Based on netxbig_v2-setup.c, - * Copyright (C) 2010 Simon Guinot - * -*/ - -#include -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - serial@12000 { - status = "okay"; - }; - - spi@10600 { - status = "okay"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "mxicy,mx25l4005a", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <20000000>; - mode = <0>; - - partition@0 { - reg = <0x0 0x80000>; - label = "u-boot"; - }; - }; - }; - - sata@80000 { - status = "okay"; - nr-ports = <2>; - }; - - }; - - gpio-keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - /* - * esc and power represent a three position rocker - * switch. Thus the conventional KEY_POWER does not fit - */ - exc { - label = "Back power switch (on|auto)"; - linux,code = ; - linux,input-type = <5>; - gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; - }; - power { - label = "Back power switch (auto|off)"; - linux,code = ; - linux,input-type = <5>; - gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; - }; - option { - label = "Function button"; - linux,code = ; - gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; - }; - - }; - - gpio-poweroff { - compatible = "gpio-poweroff"; - gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>; - }; - - regulators: regulators { - status = "okay"; - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - - regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "hdd0power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 16 GPIO_ACTIVE_HIGH>; - }; - }; - - netxbig_gpio_ext: netxbig-gpio-ext { - compatible = "lacie,netxbig-gpio-ext"; - - addr-gpios = <&gpio1 15 GPIO_ACTIVE_HIGH - &gpio1 16 GPIO_ACTIVE_HIGH - &gpio1 17 GPIO_ACTIVE_HIGH>; - data-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH - &gpio1 13 GPIO_ACTIVE_HIGH - &gpio1 14 GPIO_ACTIVE_HIGH>; - enable-gpio = <&gpio0 29 GPIO_ACTIVE_HIGH>; - }; - - netxbig-leds { - compatible = "lacie,netxbig-leds"; - - gpio-ext = <&netxbig_gpio_ext>; - - timers = ; - - blue-power { - label = "netxbig:blue:power"; - mode-addr = <0>; - mode-val = ; - bright-addr = <1>; - max-brightness = <7>; - }; - red-power { - label = "netxbig:red:power"; - mode-addr = <0>; - mode-val = ; - bright-addr = <1>; - max-brightness = <7>; - }; - blue-sata0 { - label = "netxbig:blue:sata0"; - mode-addr = <3>; - mode-val = ; - bright-addr = <2>; - max-brightness = <7>; - }; - red-sata0 { - label = "netxbig:red:sata0"; - mode-addr = <3>; - mode-val = ; - bright-addr = <2>; - max-brightness = <7>; - }; - blue-sata1 { - label = "netxbig:blue:sata1"; - mode-addr = <4>; - mode-val = ; - bright-addr = <2>; - max-brightness = <7>; - }; - red-sata1 { - label = "netxbig:red:sata1"; - mode-addr = <4>; - mode-val = ; - bright-addr = <2>; - max-brightness = <7>; - }; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@0 { - reg = <8>; - }; - - ethphy1: ethernet-phy@1 { - reg = <0>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; - -&pinctrl { - pinctrl-names = "default"; - - pmx_button_function: pmx-button-function { - marvell,pins = "mpp34"; - marvell,function = "gpio"; - }; - pmx_button_power_off: pmx-button-power-off { - marvell,pins = "mpp15"; - marvell,function = "gpio"; - }; - pmx_button_power_on: pmx-button-power-on { - marvell,pins = "mpp13"; - marvell,function = "gpio"; - }; -}; - -&i2c0 { - status = "okay"; - - eeprom@50 { - compatible = "atmel,24c04"; - pagesize = <16>; - reg = <0x50>; - }; -}; diff --git a/sys/gnu/dts/arm/kirkwood-ns2-common.dtsi b/sys/gnu/dts/arm/kirkwood-ns2-common.dtsi deleted file mode 100644 index 51530ea8662..00000000000 --- a/sys/gnu/dts/arm/kirkwood-ns2-common.dtsi +++ /dev/null @@ -1,97 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pmx_ns2_sata0: pmx-ns2-sata0 { - marvell,pins = "mpp21"; - marvell,function = "sata0"; - }; - pmx_ns2_sata1: pmx-ns2-sata1 { - marvell,pins = "mpp20"; - marvell,function = "sata1"; - }; - }; - - serial@12000 { - status = "okay"; - }; - - spi@10600 { - status = "okay"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "mxicy,mx25l4005a", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <20000000>; - mode = <0>; - - partition@0 { - reg = <0x0 0x80000>; - label = "u-boot"; - }; - }; - }; - - i2c@11000 { - status = "okay"; - - eeprom@50 { - compatible = "atmel,24c04"; - pagesize = <16>; - reg = <0x50>; - }; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - power { - label = "Power push button"; - linux,code = ; - gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - red-fail { - label = "ns2:red:fail"; - gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio_poweroff { - compatible = "gpio-poweroff"; - gpios = <&gpio0 31 GPIO_ACTIVE_HIGH>; - }; - -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@X { - /* overwrite reg property in board file */ - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; diff --git a/sys/gnu/dts/arm/kirkwood-ns2.dts b/sys/gnu/dts/arm/kirkwood-ns2.dts deleted file mode 100644 index 7b67083e1ec..00000000000 --- a/sys/gnu/dts/arm/kirkwood-ns2.dts +++ /dev/null @@ -1,40 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include -#include "kirkwood-ns2-common.dtsi" - -/ { - model = "LaCie Network Space v2"; - compatible = "lacie,netspace_v2", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x10000000>; - }; - - ocp@f1000000 { - sata@80000 { - pinctrl-0 = <&pmx_ns2_sata0>; - pinctrl-names = "default"; - status = "okay"; - nr-ports = <1>; - }; - }; - - ns2-leds { - compatible = "lacie,ns2-leds"; - - blue-sata { - label = "ns2:blue:sata"; - slow-gpio = <&gpio0 29 0>; - cmd-gpio = <&gpio0 30 0>; - modes-map = ; - }; - }; -}; - -ðphy0 { reg = <8>; }; diff --git a/sys/gnu/dts/arm/kirkwood-ns2lite.dts b/sys/gnu/dts/arm/kirkwood-ns2lite.dts deleted file mode 100644 index b0cb5907ed6..00000000000 --- a/sys/gnu/dts/arm/kirkwood-ns2lite.dts +++ /dev/null @@ -1,35 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "kirkwood-ns2-common.dtsi" - -/ { - model = "LaCie Network Space Lite v2"; - compatible = "lacie,netspace_lite_v2", "marvell,kirkwood-88f6192", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - ocp@f1000000 { - sata@80000 { - pinctrl-0 = <&pmx_ns2_sata0>; - pinctrl-names = "default"; - status = "okay"; - nr-ports = <1>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - blue-sata { - label = "ns2:blue:sata"; - gpios = <&gpio0 30 GPIO_ACTIVE_LOW>; - linux,default-trigger = "disk-activity"; - }; - }; -}; - -ðphy0 { reg = <0>; }; diff --git a/sys/gnu/dts/arm/kirkwood-ns2max.dts b/sys/gnu/dts/arm/kirkwood-ns2max.dts deleted file mode 100644 index c0a087e7740..00000000000 --- a/sys/gnu/dts/arm/kirkwood-ns2max.dts +++ /dev/null @@ -1,59 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include -#include "kirkwood-ns2-common.dtsi" - -/ { - model = "LaCie Network Space Max v2"; - compatible = "lacie,netspace_max_v2", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x10000000>; - }; - - ocp@f1000000 { - sata@80000 { - pinctrl-0 = <&pmx_ns2_sata0 &pmx_ns2_sata1>; - pinctrl-names = "default"; - status = "okay"; - nr-ports = <2>; - }; - }; - - gpio_fan { - compatible = "gpio-fan"; - gpios = <&gpio0 22 GPIO_ACTIVE_LOW - &gpio0 7 GPIO_ACTIVE_LOW - &gpio1 1 GPIO_ACTIVE_LOW - &gpio0 23 GPIO_ACTIVE_LOW>; - gpio-fan,speed-map = - < 0 0 - 1500 15 - 1700 14 - 1800 13 - 2100 12 - 3100 11 - 3300 10 - 4300 9 - 5500 8>; - alarm-gpios = <&gpio0 25 GPIO_ACTIVE_LOW>; - }; - - ns2-leds { - compatible = "lacie,ns2-leds"; - - blue-sata { - label = "ns2:blue:sata"; - slow-gpio = <&gpio0 29 0>; - cmd-gpio = <&gpio0 30 0>; - modes-map = ; - }; - }; -}; - -ðphy0 { reg = <8>; }; diff --git a/sys/gnu/dts/arm/kirkwood-ns2mini.dts b/sys/gnu/dts/arm/kirkwood-ns2mini.dts deleted file mode 100644 index 5b9fa14b642..00000000000 --- a/sys/gnu/dts/arm/kirkwood-ns2mini.dts +++ /dev/null @@ -1,60 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include -#include "kirkwood-ns2-common.dtsi" - -/ { - /* This machine is embedded in the first LaCie CloudBox product. */ - model = "LaCie Network Space Mini v2"; - compatible = "lacie,netspace_mini_v2", "marvell,kirkwood-88f6192", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - ocp@f1000000 { - sata@80000 { - pinctrl-0 = <&pmx_ns2_sata0>; - pinctrl-names = "default"; - status = "okay"; - nr-ports = <1>; - }; - }; - - gpio_fan { - compatible = "gpio-fan"; - gpios = <&gpio0 22 GPIO_ACTIVE_LOW - &gpio0 7 GPIO_ACTIVE_LOW - &gpio1 1 GPIO_ACTIVE_LOW - &gpio0 23 GPIO_ACTIVE_LOW>; - gpio-fan,speed-map = - < 0 0 - 3000 15 - 3180 14 - 4140 13 - 4570 12 - 6760 11 - 7140 10 - 7980 9 - 9200 8>; - alarm-gpios = <&gpio0 25 GPIO_ACTIVE_LOW>; - }; - - ns2-leds { - compatible = "lacie,ns2-leds"; - - blue-sata { - label = "ns2:blue:sata"; - slow-gpio = <&gpio0 29 0>; - cmd-gpio = <&gpio0 30 0>; - modes-map = ; - }; - }; -}; - -ðphy0 { reg = <0>; }; diff --git a/sys/gnu/dts/arm/kirkwood-nsa310.dts b/sys/gnu/dts/arm/kirkwood-nsa310.dts deleted file mode 100644 index 9b861c2e76c..00000000000 --- a/sys/gnu/dts/arm/kirkwood-nsa310.dts +++ /dev/null @@ -1,139 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "kirkwood-nsa3x0-common.dtsi" - -/ { - compatible = "zyxel,nsa310", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x10000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pinctrl-0 = <&pmx_unknown>; - pinctrl-names = "default"; - - pmx_led_esata_green: pmx-led-esata-green { - marvell,pins = "mpp12"; - marvell,function = "gpio"; - }; - - pmx_led_esata_red: pmx-led-esata-red { - marvell,pins = "mpp13"; - marvell,function = "gpio"; - }; - - pmx_led_usb_green: pmx-led-usb-green { - marvell,pins = "mpp15"; - marvell,function = "gpio"; - }; - - pmx_led_usb_red: pmx-led-usb-red { - marvell,pins = "mpp16"; - marvell,function = "gpio"; - }; - - pmx_led_sys_green: pmx-led-sys-green { - marvell,pins = "mpp28"; - marvell,function = "gpio"; - }; - - pmx_led_sys_red: pmx-led-sys-red { - marvell,pins = "mpp29"; - marvell,function = "gpio"; - }; - - pmx_led_hdd_green: pmx-led-hdd-green { - marvell,pins = "mpp41"; - marvell,function = "gpio"; - }; - - pmx_led_hdd_red: pmx-led-hdd-red { - marvell,pins = "mpp42"; - marvell,function = "gpio"; - }; - - pmx_unknown: pmx-unknown { - marvell,pins = "mpp44"; - marvell,function = "gpio"; - }; - - }; - - i2c@11000 { - status = "okay"; - - adt7476: adt7476a@2e { - compatible = "adi,adt7476"; - reg = <0x2e>; - }; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_led_esata_green &pmx_led_esata_red - &pmx_led_usb_green &pmx_led_usb_red - &pmx_led_sys_green &pmx_led_sys_red - &pmx_led_copy_green &pmx_led_copy_red - &pmx_led_hdd_green &pmx_led_hdd_red>; - pinctrl-names = "default"; - - green-sys { - label = "nsa310:green:sys"; - gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; - }; - red-sys { - label = "nsa310:red:sys"; - gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; - }; - green-hdd { - label = "nsa310:green:hdd"; - gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; - }; - red-hdd { - label = "nsa310:red:hdd"; - gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; - }; - green-esata { - label = "nsa310:green:esata"; - gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; - }; - red-esata { - label = "nsa310:red:esata"; - gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; - }; - green-usb { - label = "nsa310:green:usb"; - gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; - }; - red-usb { - label = "nsa310:red:usb"; - gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; - }; - green-copy { - label = "nsa310:green:copy"; - gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; - }; - red-copy { - label = "nsa310:red:copy"; - gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&pciec { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/kirkwood-nsa310a.dts b/sys/gnu/dts/arm/kirkwood-nsa310a.dts deleted file mode 100644 index b85e314f045..00000000000 --- a/sys/gnu/dts/arm/kirkwood-nsa310a.dts +++ /dev/null @@ -1,115 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "kirkwood-nsa3x0-common.dtsi" - -/* - * There are at least two different NSA310 designs. This variant does - * not have the red USB Led. - */ - -/ { - compatible = "zyxel,nsa310a", "zyxel,nsa310", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x10000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pinctrl-names = "default"; - - pmx_led_esata_green: pmx-led-esata-green { - marvell,pins = "mpp12"; - marvell,function = "gpio"; - }; - - pmx_led_esata_red: pmx-led-esata-red { - marvell,pins = "mpp13"; - marvell,function = "gpio"; - }; - - pmx_led_usb_green: pmx-led-usb-green { - marvell,pins = "mpp15"; - marvell,function = "gpio"; - }; - - pmx_led_sys_green: pmx-led-sys-green { - marvell,pins = "mpp28"; - marvell,function = "gpio"; - }; - - pmx_led_sys_red: pmx-led-sys-red { - marvell,pins = "mpp29"; - marvell,function = "gpio"; - }; - - pmx_led_hdd_green: pmx-led-hdd-green { - marvell,pins = "mpp41"; - marvell,function = "gpio"; - }; - - pmx_led_hdd_red: pmx-led-hdd-red { - marvell,pins = "mpp42"; - marvell,function = "gpio"; - }; - - }; - - i2c@11000 { - status = "okay"; - - lm85: lm85@2e { - compatible = "national,lm85"; - reg = <0x2e>; - }; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - green-sys { - label = "nsa310:green:sys"; - gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; - }; - red-sys { - label = "nsa310:red:sys"; - gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; - }; - green-hdd { - label = "nsa310:green:hdd"; - gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; - }; - red-hdd { - label = "nsa310:red:hdd"; - gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; - }; - green-esata { - label = "nsa310:green:esata"; - gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; - }; - red-esata { - label = "nsa310:red:esata"; - gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; - }; - green-usb { - label = "nsa310:green:usb"; - gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; - }; - green-copy { - label = "nsa310:green:copy"; - gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; - }; - red-copy { - label = "nsa310:red:copy"; - gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/kirkwood-nsa320.dts b/sys/gnu/dts/arm/kirkwood-nsa320.dts deleted file mode 100644 index b69b096f267..00000000000 --- a/sys/gnu/dts/arm/kirkwood-nsa320.dts +++ /dev/null @@ -1,219 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* Device tree file for the Zyxel NSA 320 NAS box. - * - * Copyright (c) 2014, Adam Baker - * - * - * Based upon the board setup file created by Peter Schildmann */ - -/dts-v1/; - -#include "kirkwood-nsa3x0-common.dtsi" - -/ { - model = "Zyxel NSA320"; - compatible = "zyxel,nsa320", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x20000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pinctrl-names = "default"; - - /* SATA Activity and Present pins are not connected */ - pmx_sata0: pmx-sata0 { - marvell,pins ; - marvell,function = "sata0"; - }; - - pmx_sata1: pmx-sata1 { - marvell,pins ; - marvell,function = "sata1"; - }; - - pmx_led_hdd2_green: pmx-led-hdd2-green { - marvell,pins = "mpp12"; - marvell,function = "gpio"; - }; - - pmx_led_hdd2_red: pmx-led-hdd2-red { - marvell,pins = "mpp13"; - marvell,function = "gpio"; - }; - - pmx_mcu_data: pmx-mcu-data { - marvell,pins = "mpp14"; - marvell,function = "gpio"; - }; - - pmx_led_usb_green: pmx-led-usb-green { - marvell,pins = "mpp15"; - marvell,function = "gpio"; - }; - - pmx_mcu_clk: pmx-mcu-clk { - marvell,pins = "mpp16"; - marvell,function = "gpio"; - }; - - pmx_mcu_act: pmx-mcu-act { - marvell,pins = "mpp17"; - marvell,function = "gpio"; - }; - - pmx_led_sys_green: pmx-led-sys-green { - marvell,pins = "mpp28"; - marvell,function = "gpio"; - }; - - pmx_led_sys_orange: pmx-led-sys-orange { - marvell,pins = "mpp29"; - marvell,function = "gpio"; - }; - - pmx_led_hdd1_green: pmx-led-hdd1-green { - marvell,pins = "mpp41"; - marvell,function = "gpio"; - }; - - pmx_led_hdd1_red: pmx-led-hdd1-red { - marvell,pins = "mpp42"; - marvell,function = "gpio"; - }; - - pmx_htp: pmx-htp { - marvell,pins = "mpp43"; - marvell,function = "gpio"; - }; - - /* Buzzer needs to be switched at around 1kHz so is - not compatible with the gpio-beeper driver. */ - pmx_buzzer: pmx-buzzer { - marvell,pins = "mpp44"; - marvell,function = "gpio"; - }; - - pmx_vid_b1: pmx-vid-b1 { - marvell,pins = "mpp45"; - marvell,function = "gpio"; - }; - - pmx_power_resume_data: pmx-power-resume-data { - marvell,pins = "mpp47"; - marvell,function = "gpio"; - }; - - pmx_power_resume_clk: pmx-power-resume-clk { - marvell,pins = "mpp49"; - marvell,function = "gpio"; - }; - }; - - i2c@11000 { - status = "okay"; - - pcf8563: pcf8563@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; - }; - }; - - regulators { - usb0_power: regulator@1 { - enable-active-high; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_led_hdd2_green &pmx_led_hdd2_red - &pmx_led_usb_green - &pmx_led_sys_green &pmx_led_sys_orange - &pmx_led_copy_green &pmx_led_copy_red - &pmx_led_hdd1_green &pmx_led_hdd1_red>; - pinctrl-names = "default"; - - green-sys { - label = "nsa320:green:sys"; - gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; - }; - orange-sys { - label = "nsa320:orange:sys"; - gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; - }; - green-hdd1 { - label = "nsa320:green:hdd1"; - gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; - }; - red-hdd1 { - label = "nsa320:red:hdd1"; - gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; - }; - green-hdd2 { - label = "nsa320:green:hdd2"; - gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; - }; - red-hdd2 { - label = "nsa320:red:hdd2"; - gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; - }; - green-usb { - label = "nsa320:green:usb"; - gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; - }; - green-copy { - label = "nsa320:green:copy"; - gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; - }; - red-copy { - label = "nsa320:red:copy"; - gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; - }; - }; - - hwmon { - compatible = "zyxel,nsa320-mcu"; - pinctrl-0 = <&pmx_mcu_data &pmx_mcu_clk &pmx_mcu_act>; - pinctrl-names = "default"; - - data-gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; - clk-gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; - act-gpios = <&gpio0 17 GPIO_ACTIVE_LOW>; - }; - - /* The following pins are currently not assigned to a driver, - some of them should be configured as inputs. - pinctrl-0 = <&pmx_htp &pmx_vid_b1 - &pmx_power_resume_data &pmx_power_resume_clk>; */ -}; - -&mdio { - status = "okay"; - ethphy0: ethernet-phy@1 { - reg = <1>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; - -&pciec { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/kirkwood-nsa325.dts b/sys/gnu/dts/arm/kirkwood-nsa325.dts deleted file mode 100644 index 6f8085dbb1f..00000000000 --- a/sys/gnu/dts/arm/kirkwood-nsa325.dts +++ /dev/null @@ -1,232 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* Device tree file for the Zyxel NSA 325 NAS box. - * - * Copyright (c) 2015, Hans Ulli Kroll - * - * - * Based upon the board setup file created by Peter Schildmann - */ - -/dts-v1/; - -#include "kirkwood-nsa3x0-common.dtsi" - -/ { - model = "ZyXEL NSA325"; - compatible = "zyxel,nsa325", "marvell,kirkwood-88f6282", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x20000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pinctrl-names = "default"; - - pmx_led_hdd2_green: pmx-led-hdd2-green { - marvell,pins = "mpp12"; - marvell,function = "gpio"; - }; - - pmx_led_hdd2_red: pmx-led-hdd2-red { - marvell,pins = "mpp13"; - marvell,function = "gpio"; - }; - - pmx_mcu_data: pmx-mcu-data { - marvell,pins = "mpp14"; - marvell,function = "gpio"; - }; - - pmx_led_usb_green: pmx-led-usb-green { - marvell,pins = "mpp15"; - marvell,function = "gpio"; - }; - - pmx_mcu_clk: pmx-mcu-clk { - marvell,pins = "mpp16"; - marvell,function = "gpio"; - }; - - pmx_mcu_act: pmx-mcu-act { - marvell,pins = "mpp17"; - marvell,function = "gpio"; - }; - - pmx_led_sys_green: pmx-led-sys-green { - marvell,pins = "mpp28"; - marvell,function = "gpio"; - }; - - pmx_led_sys_orange: pmx-led-sys-orange { - marvell,pins = "mpp29"; - marvell,function = "gpio"; - }; - - pmx_led_hdd1_green: pmx-led-hdd1-green { - marvell,pins = "mpp41"; - marvell,function = "gpio"; - }; - - pmx_led_hdd1_red: pmx-led-hdd1-red { - marvell,pins = "mpp42"; - marvell,function = "gpio"; - }; - - pmx_htp: pmx-htp { - marvell,pins = "mpp43"; - marvell,function = "gpio"; - }; - - /* - * Buzzer needs to be switched at around 1kHz so is - * not compatible with the gpio-beeper driver. - */ - pmx_buzzer: pmx-buzzer { - marvell,pins = "mpp44"; - marvell,function = "gpio"; - }; - - pmx_vid_b1: pmx-vid-b1 { - marvell,pins = "mpp45"; - marvell,function = "gpio"; - }; - - pmx_power_resume_data: pmx-power-resume-data { - marvell,pins = "mpp47"; - marvell,function = "gpio"; - }; - - pmx_power_resume_clk: pmx-power-resume-clk { - marvell,pins = "mpp49"; - marvell,function = "gpio"; - }; - - pmx_pwr_sata1: pmx-pwr-sata1 { - marvell,pins = "mpp47"; - marvell,function = "gpio"; - }; - }; - - /* This board uses the pcf8563 RTC instead of the SoC RTC */ - rtc@10300 { - status = "disabled"; - }; - - i2c@11000 { - status = "okay"; - - pcf8563: pcf8563@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_pwr_sata1>; - pinctrl-names = "default"; - - usb0_power: regulator@1 { - enable-active-high; - }; - - sata1_power: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "SATA1 Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&gpio1 15 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_led_hdd2_green &pmx_led_hdd2_red - &pmx_led_usb_green - &pmx_led_sys_green &pmx_led_sys_orange - &pmx_led_copy_green &pmx_led_copy_red - &pmx_led_hdd1_green &pmx_led_hdd1_red>; - pinctrl-names = "default"; - - green-sys { - label = "nsa325:green:sys"; - gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; - }; - orange-sys { - label = "nsa325:orange:sys"; - gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; - }; - green-hdd1 { - label = "nsa325:green:hdd1"; - gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; - }; - red-hdd1 { - label = "nsa325:red:hdd1"; - gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; - }; - green-hdd2 { - label = "nsa325:green:hdd2"; - gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; - }; - red-hdd2 { - label = "nsa325:red:hdd2"; - gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; - }; - green-usb { - label = "nsa325:green:usb"; - gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; - }; - green-copy { - label = "nsa325:green:copy"; - gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; - }; - red-copy { - label = "nsa325:red:copy"; - gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; - }; - - /* The following pins are currently not assigned to a driver, - some of them should be configured as inputs. - pinctrl-0 = <&pmx_mcu_data &pmx_mcu_clk &pmx_mcu_act - &pmx_htp &pmx_vid_b1 - &pmx_power_resume_data &pmx_power_resume_clk>; */ - }; - - -}; - -&mdio { - status = "okay"; - ethphy0: ethernet-phy@1 { - reg = <1>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; - -&pciec { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/kirkwood-nsa3x0-common.dtsi b/sys/gnu/dts/arm/kirkwood-nsa3x0-common.dtsi deleted file mode 100644 index 2c4037b0728..00000000000 --- a/sys/gnu/dts/arm/kirkwood-nsa3x0-common.dtsi +++ /dev/null @@ -1,158 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - model = "ZyXEL NSA310"; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - - pmx_usb_power: pmx-usb-power { - marvell,pins = "mpp21"; - marvell,function = "gpio"; - }; - - pmx_pwr_off: pmx-pwr-off { - marvell,pins = "mpp48"; - marvell,function = "gpio"; - }; - - pmx_btn_reset: pmx-btn-reset { - marvell,pins = "mpp36"; - marvell,function = "gpio"; - }; - - pmx_btn_copy: pmx-btn-copy { - marvell,pins = "mpp37"; - marvell,function = "gpio"; - }; - - pmx_btn_power: pmx-btn-power { - marvell,pins = "mpp46"; - marvell,function = "gpio"; - }; - - pmx_led_copy_green: pmx-led-copy-green { - marvell,pins = "mpp39"; - marvell,function = "gpio"; - }; - - pmx_led_copy_red: pmx-led-copy-red { - marvell,pins = "mpp40"; - marvell,function = "gpio"; - }; - }; - - serial@12000 { - status = "ok"; - }; - - sata@80000 { - status = "okay"; - nr-ports = <2>; - }; - }; - - gpio_poweroff { - compatible = "gpio-poweroff"; - pinctrl-0 = <&pmx_pwr_off>; - pinctrl-names = "default"; - gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_btn_reset &pmx_btn_copy &pmx_btn_power>; - pinctrl-names = "default"; - - power { - label = "Power Button"; - linux,code = ; - gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; - }; - copy { - label = "Copy Button"; - linux,code = ; - gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; - }; - reset { - label = "Reset Button"; - linux,code = ; - gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - }; - }; - - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_usb_power>; - pinctrl-names = "default"; - - usb0_power: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "USB Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 21 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&nand { - status = "okay"; - chip-delay = <35>; - - partition@0 { - label = "uboot"; - reg = <0x0000000 0x0100000>; - read-only; - }; - partition@100000 { - label = "uboot_env"; - reg = <0x0100000 0x0080000>; - }; - partition@180000 { - label = "key_store"; - reg = <0x0180000 0x0080000>; - }; - partition@200000 { - label = "info"; - reg = <0x0200000 0x0080000>; - }; - partition@280000 { - label = "etc"; - reg = <0x0280000 0x0a00000>; - }; - partition@c80000 { - label = "kernel_1"; - reg = <0x0c80000 0x0a00000>; - }; - partition@1680000 { - label = "rootfs1"; - reg = <0x1680000 0x2fc0000>; - }; - partition@4640000 { - label = "kernel_2"; - reg = <0x4640000 0x0a00000>; - }; - partition@5040000 { - label = "rootfs2"; - reg = <0x5040000 0x2fc0000>; - }; -}; - -&pciec { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/kirkwood-openblocks_a6.dts b/sys/gnu/dts/arm/kirkwood-openblocks_a6.dts deleted file mode 100644 index 8ea430168ea..00000000000 --- a/sys/gnu/dts/arm/kirkwood-openblocks_a6.dts +++ /dev/null @@ -1,184 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6282.dtsi" - -/ { - model = "Plat'Home OpenBlocksA6"; - compatible = "plathome,openblocks-a6", "marvell,kirkwood-88f6283", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x20000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - serial@12000 { - status = "okay"; - }; - - serial@12100 { - status = "okay"; - }; - - sata@80000 { - nr-ports = <1>; - status = "okay"; - }; - - i2c@11100 { - status = "okay"; - - s35390a: s35390a@30 { - compatible = "sii,s35390a"; - reg = <0x30>; - }; - }; - - pinctrl: pin-controller@10000 { - pinctrl-0 = <&pmx_dip_switches>; - pinctrl-names = "default"; - - pmx_uart0: pmx-uart0 { - marvell,pins = "mpp10", "mpp11", "mpp15", - "mpp16"; - marvell,function = "uart0"; - }; - - pmx_uart1: pmx-uart1 { - marvell,pins = "mpp13", "mpp14", "mpp8", - "mpp9"; - marvell,function = "uart1"; - }; - - pmx_sysrst: pmx-sysrst { - marvell,pins = "mpp6"; - marvell,function = "sysrst"; - }; - - pmx_dip_switches: pmx-dip-switches { - marvell,pins = "mpp20", "mpp21", "mpp22", "mpp23"; - marvell,function = "gpio"; - }; - - pmx_gpio_header: pmx-gpio-header { - marvell,pins = "mpp24", "mpp25", "mpp26", "mpp27", - "mpp28", "mpp29", "mpp30", "mpp31"; - marvell,function = "gpio"; - }; - - pmx_gpio_init: pmx-init { - marvell,pins = "mpp38"; - marvell,function = "gpio"; - }; - - pmx_usb_oc: pmx-usb-oc { - marvell,pins = "mpp39"; - marvell,function = "gpio"; - }; - - pmx_leds: pmx-leds { - marvell,pins = "mpp41", "mpp42", "mpp43"; - marvell,function = "gpio"; - }; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_leds>; - pinctrl-names = "default"; - - led-red { - label = "obsa6:red:stat"; - gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; - }; - - led-green { - label = "obsa6:green:stat"; - gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; - }; - - led-yellow { - label = "obsa6:yellow:stat"; - gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - pinctrl-0 = <&pmx_gpio_init>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - - power { - label = "Init Button"; - linux,code = ; - gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&nand { - chip-delay = <25>; - status = "okay"; - - partition@0 { - label = "uboot"; - reg = <0x0 0x90000>; - }; - - partition@90000 { - label = "env"; - reg = <0x90000 0x44000>; - }; - - partition@d4000 { - label = "test"; - reg = <0xd4000 0x20000>; - }; - - partition@f4000 { - label = "conf"; - reg = <0xf4000 0x400000>; - }; - - partition@4f4000 { - label = "linux"; - reg = <0x4f4000 0x1d20000>; - }; - - partition@2214000 { - label = "user"; - reg = <0x2214000 0x1dec000>; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; - -&gpio0 { - status = "okay"; - - pinctrl-0 = <&pmx_gpio_header>; - pinctrl-names = "default"; -}; diff --git a/sys/gnu/dts/arm/kirkwood-openblocks_a7.dts b/sys/gnu/dts/arm/kirkwood-openblocks_a7.dts deleted file mode 100644 index 946f0f453dd..00000000000 --- a/sys/gnu/dts/arm/kirkwood-openblocks_a7.dts +++ /dev/null @@ -1,209 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree file for OpenBlocks A7 board - * - * Copyright (C) 2013 Free Electrons - * - * Thomas Petazzoni - * - */ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6282.dtsi" - -/ { - model = "Plat'Home OpenBlocksA7"; - compatible = "plathome,openblocks-a7", "marvell,kirkwood-88f6283", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x40000000>; /* 1 GB */ - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - serial@12000 { - status = "okay"; - }; - - serial@12100 { - status = "okay"; - }; - - sata@80000 { - nr-ports = <1>; - status = "okay"; - }; - - i2c@11100 { - status = "okay"; - - s24c02: s24c02@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - }; - }; - - pinctrl: pin-controller@10000 { - pinctrl-0 = <&pmx_dip_switches &pmx_gpio_header - &pmx_gpio_header_gpo>; - pinctrl-names = "default"; - - pmx_uart0: pmx-uart0 { - marvell,pins = "mpp10", "mpp11", "mpp15", - "mpp16"; - marvell,function = "uart0"; - }; - - pmx_uart1: pmx-uart1 { - marvell,pins = "mpp13", "mpp14", "mpp8", - "mpp9"; - marvell,function = "uart1"; - }; - - pmx_sysrst: pmx-sysrst { - marvell,pins = "mpp6"; - marvell,function = "sysrst"; - }; - - pmx_dip_switches: pmx-dip-switches { - marvell,pins = "mpp44", "mpp45", "mpp46", "mpp47"; - marvell,function = "gpio"; - }; - - /* - * Accessible on connector J202. The MPP - * listed below are pin 1-7, pin 8 is unused, - * pin 9 is external reset input and pin 10 is - * ground. - */ - pmx_gpio_header: pmx-gpio-header { - marvell,pins = "mpp17", "mpp29", "mpp28", - "mpp35", "mpp34", "mpp40"; - marvell,function = "gpio"; - }; - - pmx_gpio_header_gpo: pxm-gpio-header-gpo { - marvell,pins = "mpp7"; - marvell,function = "gpo"; - }; - - pmx_gpio_init: pmx-init { - marvell,pins = "mpp38"; - marvell,function = "gpio"; - }; - - pmx_usb_oc: pmx-usb-oc { - marvell,pins = "mpp39"; - marvell,function = "gpio"; - }; - - pmx_leds: pmx-leds { - marvell,pins = "mpp41", "mpp42", "mpp43"; - marvell,function = "gpio"; - }; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_leds>; - pinctrl-names = "default"; - - led-red { - label = "obsa7:red:stat"; - gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; - }; - - led-green { - label = "obsa7:green:stat"; - gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; - }; - - led-yellow { - label = "obsa7:yellow:stat"; - gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - pinctrl-0 = <&pmx_gpio_init>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - - button { - label = "Init Button"; - linux,code = ; - gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&nand { - chip-delay = <25>; - status = "okay"; - - partition@0 { - label = "uboot"; - reg = <0x0 0x1c0000>; - }; - - partition@1c0000 { - label = "env"; - reg = <0x1c0000 0x2c0000>; - }; - - partition@480000 { - label = "test"; - reg = <0x480000 0x160000>; - }; - - partition@5e0000 { - label = "conf"; - reg = <0x5e0000 0x540000>; - }; - - partition@b20000 { - label = "linux"; - reg = <0xb20000 0x3d40000>; - }; - - partition@4860000 { - label = "user"; - reg = <0x4860000 0xb7a0000>; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; - - ethphy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; - -ð1 { - status = "okay"; - ethernet1-port@0 { - phy-handle = <ðphy1>; - }; -}; diff --git a/sys/gnu/dts/arm/kirkwood-openrd-base.dts b/sys/gnu/dts/arm/kirkwood-openrd-base.dts deleted file mode 100644 index 094191ece3d..00000000000 --- a/sys/gnu/dts/arm/kirkwood-openrd-base.dts +++ /dev/null @@ -1,39 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Marvell OpenRD Base Board Description - * - * Andrew Lunn - * - * This file contains the definitions that are specific to OpenRD - * base variant of the Marvell Kirkwood Development Board. - */ - -/dts-v1/; - -#include "kirkwood-openrd.dtsi" - -/ { - model = "OpenRD Base"; - compatible = "marvell,openrd-base", "marvell,openrd", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - ocp@f1000000 { - serial@12100 { - status = "okay"; - }; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@8 { - reg = <8>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; diff --git a/sys/gnu/dts/arm/kirkwood-openrd-client.dts b/sys/gnu/dts/arm/kirkwood-openrd-client.dts deleted file mode 100644 index d4e0b8150a8..00000000000 --- a/sys/gnu/dts/arm/kirkwood-openrd-client.dts +++ /dev/null @@ -1,74 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Marvell OpenRD Client Board Description - * - * Andrew Lunn - * - * This file contains the definitions that are specific to OpenRD - * client variant of the Marvell Kirkwood Development Board. - */ - -/dts-v1/; - -#include "kirkwood-openrd.dtsi" - -/ { - model = "OpenRD Client"; - compatible = "marvell,openrd-client", "marvell,openrd", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - ocp@f1000000 { - audio-controller@a0000 { - status = "okay"; - }; - i2c@11000 { - status = "okay"; - clock-frequency = <400000>; - - cs42l51: cs42l51@4a { - compatible = "cirrus,cs42l51"; - reg = <0x4a>; - #sound-dai-cells = <0>; - }; - }; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,mclk-fs = <256>; - - simple-audio-card,cpu { - sound-dai = <&audio0 0>; - }; - - simple-audio-card,codec { - sound-dai = <&cs42l51>; - }; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@8 { - reg = <8>; - }; - ethphy1: ethernet-phy@24 { - reg = <24>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; - -ð1 { - status = "okay"; - ethernet1-port@0 { - phy-handle = <ðphy1>; - }; -}; - diff --git a/sys/gnu/dts/arm/kirkwood-openrd-ultimate.dts b/sys/gnu/dts/arm/kirkwood-openrd-ultimate.dts deleted file mode 100644 index 888e13320c1..00000000000 --- a/sys/gnu/dts/arm/kirkwood-openrd-ultimate.dts +++ /dev/null @@ -1,55 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Marvell OpenRD Ultimate Board Description - * - * Andrew Lunn - * - * This file contains the definitions that are specific to OpenRD - * ultimate variant of the Marvell Kirkwood Development Board. - */ - -/dts-v1/; - -#include "kirkwood-openrd.dtsi" - -/ { - model = "OpenRD Ultimate"; - compatible = "marvell,openrd-ultimate", "marvell,openrd", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - ocp@f1000000 { - i2c@11000 { - status = "okay"; - clock-frequency = <400000>; - - cs42l51: cs42l51@4a { - compatible = "cirrus,cs42l51"; - reg = <0x4a>; - }; - }; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; - ethphy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; - -ð1 { - status = "okay"; - ethernet1-port@0 { - phy-handle = <ðphy1>; - }; -}; diff --git a/sys/gnu/dts/arm/kirkwood-openrd.dtsi b/sys/gnu/dts/arm/kirkwood-openrd.dtsi deleted file mode 100644 index 47f03c69c55..00000000000 --- a/sys/gnu/dts/arm/kirkwood-openrd.dtsi +++ /dev/null @@ -1,122 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Marvell OpenRD (Base|Client|Ultimate) Board Description - * - * Andrew Lunn - * - * This file contains the definitions that are common between the three - * variants of the Marvell Kirkwood Development Board. - */ - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - memory { - device_type = "memory"; - reg = <0x00000000 0x20000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pinctrl-0 = <&pmx_select28 &pmx_sdio_cd &pmx_select34>; - pinctrl-names = "default"; - - pmx_select28: pmx-select-rs232-rs485 { - marvell,pins = "mpp28"; - marvell,function = "gpio"; - }; - pmx_sdio_cd: pmx-sdio-cd { - marvell,pins = "mpp29"; - marvell,function = "gpio"; - }; - pmx_select34: pmx-select-uart-sd { - marvell,pins = "mpp34"; - marvell,function = "gpio"; - }; - }; - serial@12000 { - status = "okay"; - - }; - sata@80000 { - status = "okay"; - nr-ports = <2>; - }; - mvsdio@90000 { - status = "okay"; - cd-gpios = <&gpio0 29 9>; - }; - gpio@10100 { - p28 { - gpio-hog; - gpios = <28 GPIO_ACTIVE_HIGH>; - /* - * SelRS232or485 selects between RS-232 or RS-485 - * mode for the second UART. - * - * Low: RS-232 - * High: RS-485 - * - * To use the second UART, you need to change also - * the SelUARTorSD. - */ - output-low; - line-name = "SelRS232or485"; - }; - }; - gpio@10140 { - p2 { - gpio-hog; - gpios = <2 GPIO_ACTIVE_HIGH>; - /* - * SelUARTorSD selects between the second UART - * (serial@12100) and SD (mvsdio@90000). - * - * Low: UART - * High: SD - * - * When changing this line make sure the newly - * selected device node is enabled and the - * previously selected device node is disabled. - */ - output-high; /* Select SD by default */ - line-name = "SelUARTorSD"; - }; - }; - }; -}; - -&nand { - status = "okay"; - pinctrl-0 = <&pmx_nand>; - pinctrl-names = "default"; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0x100000>; - }; - - partition@100000 { - label = "uImage"; - reg = <0x0100000 0x400000>; - }; - - partition@600000 { - label = "root"; - reg = <0x0600000 0x1FA00000>; - }; -}; - -&pciec { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/kirkwood-pogo_e02.dts b/sys/gnu/dts/arm/kirkwood-pogo_e02.dts deleted file mode 100644 index f9e95e55f36..00000000000 --- a/sys/gnu/dts/arm/kirkwood-pogo_e02.dts +++ /dev/null @@ -1,132 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * kirkwood-pogo_e02.dts - Device tree file for Pogoplug E02 - * - * Copyright (C) 2015 Christoph Junghans - * - * based on information of dts files from - * Arch Linux ARM by Oleg Rakhmanov - * OpenWrt by Felix Kaechele - * - */ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - model = "Cloud Engines Pogoplug E02"; - compatible = "cloudengines,pogoe02", "marvell,kirkwood-88f6281", - "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x10000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - gpio-leds { - compatible = "gpio-leds"; - - health { - label = "pogo_e02:green:health"; - gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - fault { - label = "pogo_e02:orange:fault"; - gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_usb_power_enable>; - pinctrl-names = "default"; - - usb_power: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "USB Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 29 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&pinctrl { - pinctrl-0 = < &pmx_usb_power_enable &pmx_led_orange - &pmx_led_green >; - pinctrl-names = "default"; - - pmx_usb_power_enable: pmx-usb-power-enable { - marvell,pins = "mpp29"; - marvell,function = "gpio"; - }; - - pmx_led_green: pmx-led-green { - marvell,pins = "mpp48"; - marvell,function = "gpio"; - }; - - pmx_led_orange: pmx-led-orange { - marvell,pins = "mpp49"; - marvell,function = "gpio"; - }; -}; - -&uart0 { - status = "okay"; -}; - -&nand { - chip-delay = <40>; - status = "okay"; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0x100000>; - read-only; - }; - - partition@100000 { - label = "uImage"; - reg = <0x0100000 0x400000>; - }; - - partition@500000 { - label = "pogoplug"; - reg = <0x0500000 0x2000000>; - }; - - partition@2500000 { - label = "root"; - reg = <0x02500000 0x5b00000>; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; diff --git a/sys/gnu/dts/arm/kirkwood-pogoplug-series-4.dts b/sys/gnu/dts/arm/kirkwood-pogoplug-series-4.dts deleted file mode 100644 index 5aa4669ae25..00000000000 --- a/sys/gnu/dts/arm/kirkwood-pogoplug-series-4.dts +++ /dev/null @@ -1,180 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * kirkwood-pogoplug-series-4.dts - Device tree file for PogoPlug Series 4 - * inspired by the board files made by Kevin Mihelich for ArchLinux, - * and their DTS file. - * - * Copyright (C) 2015 Linus Walleij - */ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6192.dtsi" -#include - -/ { - model = "Cloud Engines PogoPlug Series 4"; - compatible = "cloudengines,pogoplugv4", "marvell,kirkwood-88f6192", - "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x08000000>; - }; - - chosen { - stdout-path = "uart0:115200n8"; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_button_eject>; - pinctrl-names = "default"; - - eject { - debounce-interval = <50>; - wakeup-source; - linux,code = ; - label = "Eject Button"; - gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_led_green &pmx_led_red>; - pinctrl-names = "default"; - - health { - label = "pogoplugv4:green:health"; - gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; - default-state = "on"; - }; - fault { - label = "pogoplugv4:red:fault"; - gpios = <&gpio0 24 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&pinctrl { - pmx_sata0: pmx-sata0 { - marvell,pins = "mpp21"; - marvell,function = "sata0"; - }; - - pmx_sata1: pmx-sata1 { - marvell,pins = "mpp20"; - marvell,function = "sata1"; - }; - - pmx_sdio_cd: pmx-sdio-cd { - marvell,pins = "mpp27"; - marvell,function = "gpio"; - }; - - pmx_sdio_wp: pmx-sdio-wp { - marvell,pins = "mpp28"; - marvell,function = "gpio"; - }; - - pmx_button_eject: pmx-button-eject { - marvell,pins = "mpp29"; - marvell,function = "gpio"; - }; - - pmx_led_green: pmx-led-green { - marvell,pins = "mpp22"; - marvell,function = "gpio"; - }; - - pmx_led_red: pmx-led-red { - marvell,pins = "mpp24"; - marvell,function = "gpio"; - }; -}; - -&uart0 { - status = "okay"; -}; - -/* - * This PCIE controller has a USB 3.0 XHCI controller at 1,0 - */ -&pciec { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; - -&sata { - status = "okay"; - pinctrl-0 = <&pmx_sata0 &pmx_sata1>; - pinctrl-names = "default"; - nr-ports = <1>; -}; - -&sdio { - status = "okay"; - pinctrl-0 = <&pmx_sdio &pmx_sdio_cd &pmx_sdio_wp>; - pinctrl-names = "default"; - cd-gpios = <&gpio0 27 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; -}; - -&nand { - /* 128 MiB of NAND flash */ - chip-delay = <40>; - status = "okay"; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x00000000 0x200000>; - read-only; - }; - - partition@200000 { - label = "uImage"; - reg = <0x00200000 0x300000>; - }; - - partition@500000 { - label = "uImage2"; - reg = <0x00500000 0x300000>; - }; - - partition@800000 { - label = "failsafe"; - reg = <0x00800000 0x800000>; - }; - - partition@1000000 { - label = "root"; - reg = <0x01000000 0x7000000>; - }; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; diff --git a/sys/gnu/dts/arm/kirkwood-rd88f6192.dts b/sys/gnu/dts/arm/kirkwood-rd88f6192.dts deleted file mode 100644 index 712d6042b13..00000000000 --- a/sys/gnu/dts/arm/kirkwood-rd88f6192.dts +++ /dev/null @@ -1,106 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Marvell RD88F6192 Board descrition - * - * Andrew Lunn - * - * This file contains the definitions that are common between the three - * variants of the Marvell Kirkwood Development Board. - */ -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6192.dtsi" - -/ { - model = "Marvell RD88F6192 reference design"; - compatible = "marvell,rd88f6192", "marvell,kirkwood-88f6192", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x20000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pinctrl-0 = <&pmx_usb_power>; - pinctrl-names = "default"; - - pmx_usb_power: pmx-usb-power { - marvell,pins = "mpp10"; - marvell,function = "gpo"; - }; - }; - - serial@12000 { - status = "okay"; - - }; - - spi@10600 { - status = "okay"; - - m25p128@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,m25p128", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <20000000>; - mode = <0>; - }; - }; - - sata@80000 { - status = "okay"; - nr-ports = <2>; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_usb_power>; - pinctrl-names = "default"; - - usb_power: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "USB VBUS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 10 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@8 { - reg = <8>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; - -&pciec { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/kirkwood-rd88f6281-a.dts b/sys/gnu/dts/arm/kirkwood-rd88f6281-a.dts deleted file mode 100644 index 5da163591bb..00000000000 --- a/sys/gnu/dts/arm/kirkwood-rd88f6281-a.dts +++ /dev/null @@ -1,39 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Marvell RD88F6181 A Board descrition - * - * Andrew Lunn - * - * This file contains the definitions for the board with the A0 or - * higher stepping of the SoC. The ethernet switch does not have a - * "wan" port. - */ - -/dts-v1/; -#include "kirkwood-rd88f6281.dtsi" - -/ { - model = "Marvell RD88f6281 Reference design, with A0 or higher SoC"; - compatible = "marvell,rd88f6281-a", "marvell,rd88f6281","marvell,kirkwood-88f6281", "marvell,kirkwood"; - -}; - -&mdio { - status = "okay"; - - ethphy1: ethernet-phy@11 { - reg = <11>; - }; -}; - -&switch { - reg = <10>; -}; - -ð1 { - status = "okay"; - - ethernet1-port@0 { - phy-handle = <ðphy1>; - }; -}; diff --git a/sys/gnu/dts/arm/kirkwood-rd88f6281-z0.dts b/sys/gnu/dts/arm/kirkwood-rd88f6281-z0.dts deleted file mode 100644 index 9d88301daf0..00000000000 --- a/sys/gnu/dts/arm/kirkwood-rd88f6281-z0.dts +++ /dev/null @@ -1,34 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Marvell RD88F6181 Z0 stepping descrition - * - * Andrew Lunn - * - * This file contains the definitions for the board using the Z0 - * stepping of the SoC. The ethernet switch has a "wan" port. -*/ - -/dts-v1/; - -#include "kirkwood-rd88f6281.dtsi" - -/ { - model = "Marvell RD88f6281 Reference design, with Z0 SoC"; - compatible = "marvell,rd88f6281-z0", "marvell,rd88f6281","marvell,kirkwood-88f6281", "marvell,kirkwood"; - -}; - -ð1 { - status = "disabled"; -}; - -&switch { - reg = <0>; - - ports { - port@4 { - reg = <4>; - label = "wan"; - }; - }; -}; diff --git a/sys/gnu/dts/arm/kirkwood-rd88f6281.dtsi b/sys/gnu/dts/arm/kirkwood-rd88f6281.dtsi deleted file mode 100644 index f1f8eee132e..00000000000 --- a/sys/gnu/dts/arm/kirkwood-rd88f6281.dtsi +++ /dev/null @@ -1,134 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Marvell RD88F6181 Common Board descrition - * - * Andrew Lunn - * - * This file contains the definitions that are common between the two - * variants of the Marvell Kirkwood Development Board. - */ - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - memory { - device_type = "memory"; - reg = <0x00000000 0x20000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pinctrl-names = "default"; - - pmx_sdio_cd: pmx-sdio-cd { - marvell,pins = "mpp28"; - marvell,function = "gpio"; - }; - }; - - serial@12000 { - status = "okay"; - - }; - - sata@80000 { - status = "okay"; - nr-ports = <2>; - }; - mvsdio@90000 { - pinctrl-0 = <&pmx_sdio &pmx_sdio_cd>; - pinctrl-names = "default"; - status = "okay"; - cd-gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; - /* No WP GPIO */ - }; - }; -}; - -&nand { - status = "okay"; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0x100000>; - read-only; - }; - - partition@100000 { - label = "uImage"; - reg = <0x0100000 0x200000>; - }; - - partition@300000 { - label = "rootfs"; - reg = <0x0300000 0x500000>; - }; -}; - -&mdio { - status = "okay"; - - switch: switch@0 { - compatible = "marvell,mv88e6085"; - #address-cells = <1>; - #size-cells = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "lan1"; - }; - - port@1 { - reg = <1>; - label = "lan2"; - }; - - port@2 { - reg = <2>; - label = "lan3"; - }; - - port@3 { - reg = <3>; - label = "lan4"; - }; - - port@5 { - reg = <5>; - label = "cpu"; - ethernet = <ð0port>; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - - }; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - speed = <1000>; - duplex = <1>; - }; -}; - -&pciec { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/kirkwood-rs212.dts b/sys/gnu/dts/arm/kirkwood-rs212.dts deleted file mode 100644 index c51cea88321..00000000000 --- a/sys/gnu/dts/arm/kirkwood-rs212.dts +++ /dev/null @@ -1,51 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Andrew Lunn - * Ben Peddell - * - */ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6282.dtsi" -#include "kirkwood-synology.dtsi" - -/ { - model = "Synology RS212"; - compatible = "synology,rs212", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - gpio-fan-100-15-35-3 { - status = "okay"; - }; - - gpio-leds-hdd-38 { - status = "okay"; - }; - - regulators-hdd-30-2 { - status = "okay"; - }; -}; - -&s35390a { - status = "okay"; -}; - -&pciec { - status = "okay"; -}; - -&pcie1 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/kirkwood-rs409.dts b/sys/gnu/dts/arm/kirkwood-rs409.dts deleted file mode 100644 index 43673b03cb3..00000000000 --- a/sys/gnu/dts/arm/kirkwood-rs409.dts +++ /dev/null @@ -1,43 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Andrew Lunn - * Ben Peddell - * - */ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" -#include "kirkwood-synology.dtsi" - -/ { - model = "Synology RS409"; - compatible = "synology,rs409", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - gpio-fan-150-15-18 { - status = "okay"; - }; - - gpio-leds-hdd-36 { - status = "okay"; - }; -}; - -ð1 { - status = "okay"; -}; - -&rs5c372 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/kirkwood-rs411.dts b/sys/gnu/dts/arm/kirkwood-rs411.dts deleted file mode 100644 index 41fa63cec83..00000000000 --- a/sys/gnu/dts/arm/kirkwood-rs411.dts +++ /dev/null @@ -1,43 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Andrew Lunn - * Ben Peddell - * - */ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6282.dtsi" -#include "kirkwood-synology.dtsi" - -/ { - model = "Synology RS411 RS812"; - compatible = "synology,rs411", "synology,rs812", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - gpio-fan-100-15-35-3 { - status = "okay"; - }; - - gpio-leds-hdd-36 { - status = "okay"; - }; -}; - -ð1 { - status = "okay"; -}; - -&s35390a { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/kirkwood-sheevaplug-common.dtsi b/sys/gnu/dts/arm/kirkwood-sheevaplug-common.dtsi deleted file mode 100644 index 0a698d3b739..00000000000 --- a/sys/gnu/dts/arm/kirkwood-sheevaplug-common.dtsi +++ /dev/null @@ -1,104 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * kirkwood-sheevaplug-common.dtsi - Common parts for Sheevaplugs - * - * Copyright (C) 2013 Simon Baatz - */ - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - memory { - device_type = "memory"; - reg = <0x00000000 0x20000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - - pmx_usb_power_enable: pmx-usb-power-enable { - marvell,pins = "mpp29"; - marvell,function = "gpio"; - }; - pmx_led_red: pmx-led-red { - marvell,pins = "mpp46"; - marvell,function = "gpio"; - }; - pmx_led_blue: pmx-led-blue { - marvell,pins = "mpp49"; - marvell,function = "gpio"; - }; - pmx_sdio_cd: pmx-sdio-cd { - marvell,pins = "mpp44"; - marvell,function = "gpio"; - }; - pmx_sdio_wp: pmx-sdio-wp { - marvell,pins = "mpp47"; - marvell,function = "gpio"; - }; - }; - serial@12000 { - status = "okay"; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_usb_power_enable>; - pinctrl-names = "default"; - - usb_power: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "USB Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 29 0>; - }; - }; -}; - -&nand { - status = "okay"; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0x100000>; - }; - - partition@100000 { - label = "uImage"; - reg = <0x0100000 0x400000>; - }; - - partition@500000 { - label = "root"; - reg = <0x0500000 0x1fb00000>; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; diff --git a/sys/gnu/dts/arm/kirkwood-sheevaplug-esata.dts b/sys/gnu/dts/arm/kirkwood-sheevaplug-esata.dts deleted file mode 100644 index ae8f493c9a0..00000000000 --- a/sys/gnu/dts/arm/kirkwood-sheevaplug-esata.dts +++ /dev/null @@ -1,42 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * kirkwood-sheevaplug-esata.dts - Device tree file for eSATA Sheevaplug - * - * Copyright (C) 2013 Simon Baatz - */ - -/dts-v1/; - -#include "kirkwood-sheevaplug-common.dtsi" - -/ { - model = "Globalscale Technologies eSATA SheevaPlug"; - compatible = "globalscale,sheevaplug-esata-rev13", "globalscale,sheevaplug-esata", "globalscale,sheevaplug", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - ocp@f1000000 { - sata@80000 { - status = "okay"; - nr-ports = <2>; - }; - - mvsdio@90000 { - pinctrl-0 = <&pmx_sdio &pmx_sdio_cd &pmx_sdio_wp>; - pinctrl-names = "default"; - status = "okay"; - cd-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_led_blue>; - pinctrl-names = "default"; - - health { - label = "sheevaplug:blue:health"; - gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - }; -}; diff --git a/sys/gnu/dts/arm/kirkwood-sheevaplug.dts b/sys/gnu/dts/arm/kirkwood-sheevaplug.dts deleted file mode 100644 index c73cc904e5c..00000000000 --- a/sys/gnu/dts/arm/kirkwood-sheevaplug.dts +++ /dev/null @@ -1,42 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * kirkwood-sheevaplug.dts - Device tree file for Sheevaplug - * - * Copyright (C) 2013 Simon Baatz - */ - -/dts-v1/; - -#include "kirkwood-sheevaplug-common.dtsi" - -/ { - model = "Globalscale Technologies SheevaPlug"; - compatible = "globalscale,sheevaplug", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - ocp@f1000000 { - mvsdio@90000 { - pinctrl-0 = <&pmx_sdio>; - pinctrl-names = "default"; - status = "okay"; - /* No CD or WP GPIOs */ - broken-cd; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_led_blue &pmx_led_red>; - pinctrl-names = "default"; - - health { - label = "sheevaplug:blue:health"; - gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - - misc { - label = "sheevaplug:red:misc"; - gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/kirkwood-synology.dtsi b/sys/gnu/dts/arm/kirkwood-synology.dtsi deleted file mode 100644 index 217bd374e52..00000000000 --- a/sys/gnu/dts/arm/kirkwood-synology.dtsi +++ /dev/null @@ -1,855 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Nodes for Marvell 628x Synology devices - * - * Andrew Lunn - * Ben Peddell - * - */ - -/ { - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pmx_alarmled_12: pmx-alarmled-12 { - marvell,pins = "mpp12"; - marvell,function = "gpio"; - }; - - pmx_fanctrl_15: pmx-fanctrl-15 { - marvell,pins = "mpp15"; - marvell,function = "gpio"; - }; - - pmx_fanctrl_16: pmx-fanctrl-16 { - marvell,pins = "mpp16"; - marvell,function = "gpio"; - }; - - pmx_fanctrl_17: pmx-fanctrl-17 { - marvell,pins = "mpp17"; - marvell,function = "gpio"; - }; - - pmx_fanalarm_18: pmx-fanalarm-18 { - marvell,pins = "mpp18"; - marvell,function = "gpo"; - }; - - pmx_hddled_20: pmx-hddled-20 { - marvell,pins = "mpp20"; - marvell,function = "gpio"; - }; - - pmx_hddled_21: pmx-hddled-21 { - marvell,pins = "mpp21"; - marvell,function = "gpio"; - }; - - pmx_hddled_22: pmx-hddled-22 { - marvell,pins = "mpp22"; - marvell,function = "gpio"; - }; - - pmx_hddled_23: pmx-hddled-23 { - marvell,pins = "mpp23"; - marvell,function = "gpio"; - }; - - pmx_hddled_24: pmx-hddled-24 { - marvell,pins = "mpp24"; - marvell,function = "gpio"; - }; - - pmx_hddled_25: pmx-hddled-25 { - marvell,pins = "mpp25"; - marvell,function = "gpio"; - }; - - pmx_hddled_26: pmx-hddled-26 { - marvell,pins = "mpp26"; - marvell,function = "gpio"; - }; - - pmx_hddled_27: pmx-hddled-27 { - marvell,pins = "mpp27"; - marvell,function = "gpio"; - }; - - pmx_hddled_28: pmx-hddled-28 { - marvell,pins = "mpp28"; - marvell,function = "gpio"; - }; - - pmx_hdd1_pwr_29: pmx-hdd1-pwr-29 { - marvell,pins = "mpp29"; - marvell,function = "gpio"; - }; - - pmx_hdd1_pwr_30: pmx-hdd-pwr-30 { - marvell,pins = "mpp30"; - marvell,function = "gpio"; - }; - - pmx_hdd2_pwr_31: pmx-hdd2-pwr-31 { - marvell,pins = "mpp31"; - marvell,function = "gpio"; - }; - - pmx_fanctrl_32: pmx-fanctrl-32 { - marvell,pins = "mpp32"; - marvell,function = "gpio"; - }; - - pmx_fanctrl_33: pmx-fanctrl-33 { - marvell,pins = "mpp33"; - marvell,function = "gpo"; - }; - - pmx_fanctrl_34: pmx-fanctrl-34 { - marvell,pins = "mpp34"; - marvell,function = "gpio"; - }; - - pmx_hdd2_pwr_34: pmx-hdd2-pwr-34 { - marvell,pins = "mpp34"; - marvell,function = "gpio"; - }; - - pmx_fanalarm_35: pmx-fanalarm-35 { - marvell,pins = "mpp35"; - marvell,function = "gpio"; - }; - - pmx_hddled_36: pmx-hddled-36 { - marvell,pins = "mpp36"; - marvell,function = "gpio"; - }; - - pmx_hddled_37: pmx-hddled-37 { - marvell,pins = "mpp37"; - marvell,function = "gpio"; - }; - - pmx_hddled_38: pmx-hddled-38 { - marvell,pins = "mpp38"; - marvell,function = "gpio"; - }; - - pmx_hddled_39: pmx-hddled-39 { - marvell,pins = "mpp39"; - marvell,function = "gpio"; - }; - - pmx_hddled_40: pmx-hddled-40 { - marvell,pins = "mpp40"; - marvell,function = "gpio"; - }; - - pmx_hddled_41: pmx-hddled-41 { - marvell,pins = "mpp41"; - marvell,function = "gpio"; - }; - - pmx_hddled_42: pmx-hddled-42 { - marvell,pins = "mpp42"; - marvell,function = "gpio"; - }; - - pmx_hddled_43: pmx-hddled-43 { - marvell,pins = "mpp43"; - marvell,function = "gpio"; - }; - - pmx_hddled_44: pmx-hddled-44 { - marvell,pins = "mpp44"; - marvell,function = "gpio"; - }; - - pmx_hddled_45: pmx-hddled-45 { - marvell,pins = "mpp45"; - marvell,function = "gpio"; - }; - - pmx_hdd3_pwr_44: pmx-hdd3-pwr-44 { - marvell,pins = "mpp44"; - marvell,function = "gpio"; - }; - - pmx_hdd4_pwr_45: pmx-hdd4-pwr-45 { - marvell,pins = "mpp45"; - marvell,function = "gpio"; - }; - - pmx_fanalarm_44: pmx-fanalarm-44 { - marvell,pins = "mpp44"; - marvell,function = "gpio"; - }; - - pmx_fanalarm_45: pmx-fanalarm-45 { - marvell,pins = "mpp45"; - marvell,function = "gpio"; - }; - }; - - rtc@10300 { - status = "disabled"; - }; - - spi@10600 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,m25p80", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <20000000>; - mode = <0>; - - partition@0 { - reg = <0x00000000 0x00080000>; - label = "RedBoot"; - }; - - partition@80000 { - reg = <0x00080000 0x00200000>; - label = "zImage"; - }; - - partition@280000 { - reg = <0x00280000 0x00140000>; - label = "rd.gz"; - }; - - partition@3c0000 { - reg = <0x003c0000 0x00010000>; - label = "vendor"; - }; - - partition@3d0000 { - reg = <0x003d0000 0x00020000>; - label = "RedBoot config"; - }; - - partition@3f0000 { - reg = <0x003f0000 0x00010000>; - label = "FIS directory"; - }; - }; - }; - - i2c@11000 { - status = "okay"; - clock-frequency = <400000>; - - rs5c372: rs5c372@32 { - status = "disabled"; - compatible = "ricoh,rs5c372a"; - reg = <0x32>; - }; - - s35390a: s35390a@30 { - status = "disabled"; - compatible = "sii,s35390a"; - reg = <0x30>; - }; - }; - - serial@12000 { - status = "okay"; - }; - - serial@12100 { - status = "okay"; - }; - - poweroff@12100 { - compatible = "synology,power-off"; - reg = <0x12100 0x100>; - clocks = <&gate_clk 7>; - }; - - sata@80000 { - pinctrl-0 = <&pmx_sata0 &pmx_sata1>; - pinctrl-names = "default"; - status = "okay"; - nr-ports = <2>; - }; - }; - - gpio-fan-150-32-35 { - status = "disabled"; - compatible = "gpio-fan"; - pinctrl-0 = <&pmx_fanctrl_32 &pmx_fanctrl_33 &pmx_fanctrl_34 - &pmx_fanalarm_35>; - pinctrl-names = "default"; - gpios = <&gpio1 0 GPIO_ACTIVE_HIGH - &gpio1 1 GPIO_ACTIVE_HIGH - &gpio1 2 GPIO_ACTIVE_HIGH>; - gpio-fan,speed-map = < 0 0 - 2200 1 - 2500 2 - 3000 4 - 3300 3 - 3700 5 - 3800 6 - 4200 7 >; - }; - - gpio-fan-150-15-18 { - status = "disabled"; - compatible = "gpio-fan"; - pinctrl-0 = <&pmx_fanctrl_15 &pmx_fanctrl_16 &pmx_fanctrl_17 - &pmx_fanalarm_18>; - pinctrl-names = "default"; - gpios = <&gpio0 15 GPIO_ACTIVE_HIGH - &gpio0 16 GPIO_ACTIVE_HIGH - &gpio0 17 GPIO_ACTIVE_HIGH>; - alarm-gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>; - gpio-fan,speed-map = < 0 0 - 2200 1 - 2500 2 - 3000 4 - 3300 3 - 3700 5 - 3800 6 - 4200 7 >; - }; - - gpio-fan-100-32-35 { - status = "disabled"; - compatible = "gpio-fan"; - pinctrl-0 = <&pmx_fanctrl_32 &pmx_fanctrl_33 &pmx_fanctrl_34 - &pmx_fanalarm_35>; - pinctrl-names = "default"; - gpios = <&gpio1 0 GPIO_ACTIVE_HIGH - &gpio1 1 GPIO_ACTIVE_HIGH - &gpio1 2 GPIO_ACTIVE_HIGH>; - alarm-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; - gpio-fan,speed-map = < 0 0 - 2500 1 - 3100 2 - 3800 3 - 4600 4 - 4800 5 - 4900 6 - 5000 7 >; - }; - - gpio-fan-100-15-18 { - status = "disabled"; - compatible = "gpio-fan"; - pinctrl-0 = <&pmx_fanctrl_15 &pmx_fanctrl_16 &pmx_fanctrl_17 - &pmx_fanalarm_18>; - pinctrl-names = "default"; - gpios = <&gpio0 15 GPIO_ACTIVE_HIGH - &gpio0 16 GPIO_ACTIVE_HIGH - &gpio0 17 GPIO_ACTIVE_HIGH>; - alarm-gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>; - gpio-fan,speed-map = < 0 0 - 2500 1 - 3100 2 - 3800 3 - 4600 4 - 4800 5 - 4900 6 - 5000 7 >; - }; - - gpio-fan-100-15-35-1 { - status = "disabled"; - compatible = "gpio-fan"; - pinctrl-0 = <&pmx_fanctrl_15 &pmx_fanctrl_16 &pmx_fanctrl_17 - &pmx_fanalarm_35>; - pinctrl-names = "default"; - gpios = <&gpio0 15 GPIO_ACTIVE_HIGH - &gpio0 16 GPIO_ACTIVE_HIGH - &gpio0 17 GPIO_ACTIVE_HIGH>; - alarm-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; - gpio-fan,speed-map = < 0 0 - 2500 1 - 3100 2 - 3800 3 - 4600 4 - 4800 5 - 4900 6 - 5000 7 >; - }; - - gpio-fan-100-15-35-3 { - status = "disabled"; - compatible = "gpio-fan"; - pinctrl-0 = <&pmx_fanctrl_15 &pmx_fanctrl_16 &pmx_fanctrl_17 - &pmx_fanalarm_35 &pmx_fanalarm_44 &pmx_fanalarm_45>; - pinctrl-names = "default"; - gpios = <&gpio0 15 GPIO_ACTIVE_HIGH - &gpio0 16 GPIO_ACTIVE_HIGH - &gpio0 17 GPIO_ACTIVE_HIGH>; - alarm-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH - &gpio1 12 GPIO_ACTIVE_HIGH - &gpio1 13 GPIO_ACTIVE_HIGH>; - gpio-fan,speed-map = < 0 0 - 2500 1 - 3100 2 - 3800 3 - 4600 4 - 4800 5 - 4900 6 - 5000 7 >; - }; - - gpio-leds-alarm-12 { - status = "disabled"; - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_alarmled_12>; - pinctrl-names = "default"; - - hdd1-green { - label = "synology:alarm"; - gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-leds-hdd-20 { - status = "disabled"; - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_hddled_20 &pmx_hddled_21 &pmx_hddled_22 - &pmx_hddled_23 &pmx_hddled_24 &pmx_hddled_25 - &pmx_hddled_26 &pmx_hddled_27>; - pinctrl-names = "default"; - - hdd1-green { - label = "synology:green:hdd1"; - gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; - }; - - hdd1-amber { - label = "synology:amber:hdd1"; - gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; - }; - - hdd2-green { - label = "synology:green:hdd2"; - gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; - }; - - hdd2-amber { - label = "synology:amber:hdd2"; - gpios = <&gpio0 23 GPIO_ACTIVE_LOW>; - }; - - hdd3-green { - label = "synology:green:hdd3"; - gpios = <&gpio0 24 GPIO_ACTIVE_LOW>; - }; - - hdd3-amber { - label = "synology:amber:hdd3"; - gpios = <&gpio0 25 GPIO_ACTIVE_LOW>; - }; - - hdd4-green { - label = "synology:green:hdd4"; - gpios = <&gpio0 26 GPIO_ACTIVE_LOW>; - }; - - hdd4-amber { - label = "synology:amber:hdd4"; - gpios = <&gpio0 27 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-leds-hdd-21-1 { - status = "disabled"; - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_hddled_21 &pmx_hddled_23>; - pinctrl-names = "default"; - - hdd1-green { - label = "synology:green:hdd1"; - gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; - }; - - hdd1-amber { - label = "synology:amber:hdd1"; - gpios = <&gpio0 23 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-leds-hdd-21-2 { - status = "disabled"; - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_hddled_21 &pmx_hddled_23 &pmx_hddled_20 &pmx_hddled_22>; - pinctrl-names = "default"; - - hdd1-green { - label = "synology:green:hdd1"; - gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; - }; - - hdd1-amber { - label = "synology:amber:hdd1"; - gpios = <&gpio0 23 GPIO_ACTIVE_LOW>; - }; - - hdd2-green { - label = "synology:green:hdd2"; - gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; - }; - - hdd2-amber { - label = "synology:amber:hdd2"; - gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-leds-hdd-36 { - status = "disabled"; - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_hddled_36 &pmx_hddled_37 &pmx_hddled_38 - &pmx_hddled_39 &pmx_hddled_40 &pmx_hddled_41 - &pmx_hddled_42 &pmx_hddled_43 &pmx_hddled_44 - &pmx_hddled_45>; - pinctrl-names = "default"; - - hdd1-green { - label = "synology:green:hdd1"; - gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - }; - - hdd1-amber { - label = "synology:amber:hdd1"; - gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; - }; - - hdd2-green { - label = "synology:green:hdd2"; - gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; - }; - - hdd2-amber { - label = "synology:amber:hdd2"; - gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; - }; - - hdd3-green { - label = "synology:green:hdd3"; - gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; - }; - - hdd3-amber { - label = "synology:amber:hdd3"; - gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; - }; - - hdd4-green { - label = "synology:green:hdd4"; - gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; - }; - - hdd4-amber { - label = "synology:amber:hdd4"; - gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; - }; - - hdd5-green { - label = "synology:green:hdd5"; - gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; - }; - - hdd5-amber { - label = "synology:amber:hdd5"; - gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-leds-hdd-38 { - status = "disabled"; - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_hddled_38 &pmx_hddled_39 &pmx_hddled_36 &pmx_hddled_37>; - pinctrl-names = "default"; - - hdd1-green { - label = "synology:green:hdd1"; - gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; - }; - - hdd1-amber { - label = "synology:amber:hdd1"; - gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; - }; - - hdd2-green { - label = "synology:green:hdd2"; - gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - }; - - hdd2-amber { - label = "synology:amber:hdd2"; - gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; - }; - }; - - regulators-hdd-29 { - status = "disabled"; - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_hdd1_pwr_29 &pmx_hdd2_pwr_31>; - pinctrl-names = "default"; - - regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "hdd1power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - startup-delay-us = <5000000>; - gpio = <&gpio0 29 GPIO_ACTIVE_HIGH>; - }; - - regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "hdd2power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - startup-delay-us = <5000000>; - gpio = <&gpio0 31 GPIO_ACTIVE_HIGH>; - }; - }; - - regulators-hdd-30-1 { - status = "disabled"; - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_hdd1_pwr_30>; - pinctrl-names = "default"; - - regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "hdd1power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - startup-delay-us = <5000000>; - gpio = <&gpio0 30 GPIO_ACTIVE_HIGH>; - }; - }; - - regulators-hdd-30-2 { - status = "disabled"; - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_hdd1_pwr_30 &pmx_hdd2_pwr_34>; - pinctrl-names = "default"; - - regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "hdd1power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - startup-delay-us = <5000000>; - gpio = <&gpio0 30 GPIO_ACTIVE_HIGH>; - }; - - regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "hdd2power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - startup-delay-us = <5000000>; - gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>; - }; - }; - - regulators-hdd-30-4 { - status = "disabled"; - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_hdd1_pwr_30 &pmx_hdd2_pwr_34 - &pmx_hdd3_pwr_44 &pmx_hdd4_pwr_45>; - pinctrl-names = "default"; - - regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "hdd1power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - startup-delay-us = <5000000>; - gpio = <&gpio0 30 GPIO_ACTIVE_HIGH>; - }; - - regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "hdd2power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - startup-delay-us = <5000000>; - gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>; - }; - - regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "hdd3power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - startup-delay-us = <5000000>; - gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; - }; - - regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "hdd4power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - startup-delay-us = <5000000>; - gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>; - }; - }; - - regulators-hdd-31 { - status = "disabled"; - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_hdd2_pwr_31>; - pinctrl-names = "default"; - - regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "hdd2power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - startup-delay-us = <5000000>; - gpio = <&gpio0 31 GPIO_ACTIVE_HIGH>; - }; - }; - - regulators-hdd-34 { - status = "disabled"; - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_hdd2_pwr_34 &pmx_hdd3_pwr_44 - &pmx_hdd4_pwr_45>; - pinctrl-names = "default"; - - regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "hdd2power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - startup-delay-us = <5000000>; - gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>; - }; - - regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "hdd3power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - startup-delay-us = <5000000>; - gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; - }; - - regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "hdd4power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - startup-delay-us = <5000000>; - gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@0 { - device_type = "ethernet-phy"; - reg = <8>; - }; - - ethphy1: ethernet-phy@1 { - device_type = "ethernet-phy"; - reg = <9>; - }; -}; - -ð0 { - status = "okay"; - - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; - -ð1 { - status = "disabled"; - - ethernet1-port@0 { - phy-handle = <ðphy1>; - }; -}; - -&pciec { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/kirkwood-t5325.dts b/sys/gnu/dts/arm/kirkwood-t5325.dts deleted file mode 100644 index fe63b3a03a7..00000000000 --- a/sys/gnu/dts/arm/kirkwood-t5325.dts +++ /dev/null @@ -1,227 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree file for HP t5325 Thin Client" - * - * Copyright (C) 2014 - * - * Thomas Petazzoni - * Andrew Lunn - * -*/ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - model = "HP t5325 Thin Client"; - compatible = "hp,t5325", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x20000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pinctrl-0 = <&pmx_i2s &pmx_sysrst>; - pinctrl-names = "default"; - - pmx_button_power: pmx-button_power { - marvell,pins = "mpp45"; - marvell,function = "gpio"; - }; - - pmx_power_off: pmx-power-off { - marvell,pins = "mpp48"; - marvell,function = "gpio"; - }; - - pmx_led: pmx-led { - marvell,pins = "mpp21"; - marvell,function = "gpio"; - }; - - pmx_usb_sata_power_enable: pmx-usb-sata-power-enable { - marvell,pins = "mpp44"; - marvell,function = "gpio"; - }; - - pmx_spi: pmx-spi { - marvell,pins = "mpp1", "mpp2", "mpp3", "mpp7"; - marvell,function = "spi"; - }; - - pmx_sysrst: pmx-sysrst { - marvell,pins = "mpp6"; - marvell,function = "sysrst"; - }; - - pmx_i2s: pmx-i2s { - marvell,pins = "mpp39", "mpp40", "mpp41", "mpp42", - "mpp43"; - marvell,function = "audio"; - }; - }; - - spi@10600 { - status = "okay"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,m25p80", "jedec,spi-nor"; - spi-max-frequency = <86000000>; - reg = <0>; - mode = <0>; - - partition@0 { - reg = <0x0 0x80000>; - label = "u-boot"; - }; - - partition@1 { - reg = <0x80000 0x40000>; - label = "SSD firmware"; - }; - - partition@2 { - reg = <0xc0000 0x10000>; - label = "u-boot env"; - }; - - partition@3 { - reg = <0xd0000 0x10000>; - label = "permanent u-boot env"; - }; - - partition@4 { - reg = <0xd0000 0x10000>; - label = "permanent u-boot env"; - }; - }; - }; - - i2c@11000 { - status = "okay"; - - alc5621: alc5621@1a { - compatible = "realtek,alc5621"; - reg = <0x1a>; - #sound-dai-cells = <0>; - add-ctrl = <0x3700>; - jack-det-ctrl = <0x4810>; - }; - }; - - serial@12000 { - status = "okay"; - }; - - sata@80000 { - status = "okay"; - nr-ports = <2>; - }; - - audio: audio-controller@a0000 { - status = "okay"; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_usb_sata_power_enable>; - pinctrl-names = "default"; - - usb_power: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "USB-SATA Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_button_power>; - pinctrl-names = "default"; - - power { - label = "Power Button"; - linux,code = ; - gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio_poweroff { - compatible = "gpio-poweroff"; - pinctrl-0 = <&pmx_power_off>; - pinctrl-names = "default"; - gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,routing = - "Headphone Jack", "HPL", - "Headphone Jack", "HPR", - "Speaker", "SPKOUT", - "Speaker", "SPKOUTN", - "MIC1", "Mic Jack", - "MIC2", "Mic Jack"; - simple-audio-card,widgets = - "Headphone", "Headphone Jack", - "Speaker", "Speaker", - "Microphone", "Mic Jack"; - - simple-audio-card,mclk-fs = <256>; - - simple-audio-card,cpu { - sound-dai = <&audio>; - }; - - simple-audio-card,codec { - sound-dai = <&alc5621>; - }; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@8 { - device_type = "ethernet-phy"; - reg = <8>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; - -&pciec { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/kirkwood-topkick.dts b/sys/gnu/dts/arm/kirkwood-topkick.dts deleted file mode 100644 index a5b51e29f63..00000000000 --- a/sys/gnu/dts/arm/kirkwood-topkick.dts +++ /dev/null @@ -1,216 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6282.dtsi" - -/ { - model = "Universal Scientific Industrial Co. Topkick-1281P2"; - compatible = "usi,topkick-1281P2", "usi,topkick", "marvell,kirkwood-88f6282", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x10000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - /* - * Switch positions - * - * /-SW_LEFT(2) - * | - * | /-SW_IDLE - * | | - * | | /-SW_RIGHT - * | | | - * PS [L] [I] [R] LEDS - */ - pinctrl-0 = <&pmx_sw_left &pmx_sw_right - &pmx_sw_idle &pmx_sw_left2>; - pinctrl-names = "default"; - - pmx_led_disk_yellow: pmx-led-disk-yellow { - marvell,pins = "mpp21"; - marvell,function = "gpio"; - }; - - pmx_sata0_pwr_enable: pmx-sata0-pwr-enable { - marvell,pins = "mpp36"; - marvell,function = "gpio"; - }; - - pmx_led_sys_red: pmx-led-sys-red { - marvell,pins = "mpp37"; - marvell,function = "gpio"; - }; - - pmx_led_sys_blue: pmx-led-sys-blue { - marvell,pins = "mpp38"; - marvell,function = "gpio"; - }; - - pmx_led_wifi_green: pmx-led-wifi-green { - marvell,pins = "mpp39"; - marvell,function = "gpio"; - }; - - pmx_sw_left: pmx-sw-left { - marvell,pins = "mpp43"; - marvell,function = "gpio"; - }; - - pmx_sw_right: pmx-sw-right { - marvell,pins = "mpp44"; - marvell,function = "gpio"; - }; - - pmx_sw_idle: pmx-sw-idle { - marvell,pins = "mpp45"; - marvell,function = "gpio"; - }; - - pmx_sw_left2: pmx-sw-left2 { - marvell,pins = "mpp46"; - marvell,function = "gpio"; - }; - - pmx_led_wifi_yellow: pmx-led-wifi-yellow { - marvell,pins = "mpp48"; - marvell,function = "gpio"; - }; - }; - - serial@12000 { - status = "okay"; - }; - - sata@80000 { - status = "okay"; - nr-ports = <1>; - }; - - i2c@11000 { - status = "okay"; - }; - - mvsdio@90000 { - pinctrl-0 = <&pmx_sdio>; - pinctrl-names = "default"; - status = "okay"; - /* No CD or WP GPIOs */ - broken-cd; - }; - }; - - gpio-leds { - /* - * GPIO LED layout - * - * /-SYS_LED(2) - * | - * | /-DISK_LED - * | | - * | | /-WLAN_LED(2) - * | | | - * [SW] [*] [*] [*] - */ - - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_led_disk_yellow &pmx_led_sys_red - &pmx_led_sys_blue &pmx_led_wifi_green - &pmx_led_wifi_yellow>; - pinctrl-names = "default"; - - disk { - label = "topkick:yellow:disk"; - gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; - linux,default-trigger = "disk-activity"; - }; - system2 { - label = "topkick:red:system"; - gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; - }; - system { - label = "topkick:blue:system"; - gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; - default-state = "on"; - }; - wifi { - label = "topkick:green:wifi"; - gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; - }; - wifi2 { - label = "topkick:yellow:wifi"; - gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; - }; - }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_sata0_pwr_enable>; - pinctrl-names = "default"; - - sata0_power: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "SATA0 Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio1 4 0>; - }; - }; -}; - -&nand { - status = "okay"; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0x180000>; - }; - - partition@180000 { - label = "u-boot env"; - reg = <0x0180000 0x20000>; - }; - - partition@200000 { - label = "uImage"; - reg = <0x0200000 0x600000>; - }; - - partition@800000 { - label = "uInitrd"; - reg = <0x0800000 0x1000000>; - }; - - partition@1800000 { - label = "rootfs"; - reg = <0x1800000 0xe800000>; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; diff --git a/sys/gnu/dts/arm/kirkwood-ts219-6281.dts b/sys/gnu/dts/arm/kirkwood-ts219-6281.dts deleted file mode 100644 index 30892c19ace..00000000000 --- a/sys/gnu/dts/arm/kirkwood-ts219-6281.dts +++ /dev/null @@ -1,56 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" -#include "kirkwood-ts219.dtsi" - -/ { - ocp@f1000000 { - pinctrl: pin-controller@10000 { - - pinctrl-0 = <&pmx_ram_size &pmx_board_id>; - pinctrl-names = "default"; - - pmx_ram_size: pmx-ram-size { - /* RAM: 0: 256 MB, 1: 512 MB */ - marvell,pins = "mpp36"; - marvell,function = "gpio"; - }; - pmx_USB_copy_button: pmx-USB-copy-button { - marvell,pins = "mpp15"; - marvell,function = "gpio"; - }; - pmx_reset_button: pmx-reset-button { - marvell,pins = "mpp16"; - marvell,function = "gpio"; - }; - pmx_board_id: pmx-board-id { - /* 0: TS-11x, 1: TS-21x */ - marvell,pins = "mpp44"; - marvell,function = "gpio"; - }; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_reset_button &pmx_USB_copy_button>; - pinctrl-names = "default"; - - copy { - label = "USB Copy"; - linux,code = ; - gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; - }; - reset { - label = "Reset"; - linux,code = ; - gpios = <&gpio0 16 GPIO_ACTIVE_LOW>; - }; - }; -}; - -ðphy0 { reg = <8>; }; diff --git a/sys/gnu/dts/arm/kirkwood-ts219-6282.dts b/sys/gnu/dts/arm/kirkwood-ts219-6282.dts deleted file mode 100644 index aba1205981f..00000000000 --- a/sys/gnu/dts/arm/kirkwood-ts219-6282.dts +++ /dev/null @@ -1,58 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6282.dtsi" -#include "kirkwood-ts219.dtsi" - -/ { - ocp@f1000000 { - pinctrl: pin-controller@10000 { - - pinctrl-0 = <&pmx_ram_size &pmx_board_id>; - pinctrl-names = "default"; - - pmx_ram_size: pmx-ram-size { - /* RAM: 0: 256 MB, 1: 512 MB */ - marvell,pins = "mpp36"; - marvell,function = "gpio"; - }; - pmx_reset_button: pmx-reset-button { - marvell,pins = "mpp37"; - marvell,function = "gpio"; - }; - pmx_USB_copy_button: pmx-USB-copy-button { - marvell,pins = "mpp43"; - marvell,function = "gpio"; - }; - pmx_board_id: pmx-board-id { - /* 0: TS-11x, 1: TS-21x */ - marvell,pins = "mpp44"; - marvell,function = "gpio"; - }; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_reset_button &pmx_USB_copy_button>; - pinctrl-names = "default"; - - copy { - label = "USB Copy"; - linux,code = ; - gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; - }; - reset { - label = "Reset"; - linux,code = ; - gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; - }; - }; -}; - -ðphy0 { reg = <0>; }; - -&pcie1 { status = "okay"; }; diff --git a/sys/gnu/dts/arm/kirkwood-ts219.dtsi b/sys/gnu/dts/arm/kirkwood-ts219.dtsi deleted file mode 100644 index 994cabcf4b5..00000000000 --- a/sys/gnu/dts/arm/kirkwood-ts219.dtsi +++ /dev/null @@ -1,114 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/ { - model = "QNAP TS219 family"; - compatible = "qnap,ts219", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x20000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - i2c@11000 { - status = "okay"; - clock-frequency = <400000>; - - s35390a: s35390a@30 { - compatible = "s35390a"; - reg = <0x30>; - }; - }; - serial@12000 { - status = "okay"; - }; - serial@12100 { - status = "okay"; - }; - poweroff@12100 { - compatible = "qnap,power-off"; - reg = <0x12100 0x100>; - clocks = <&gate_clk 7>; - }; - spi@10600 { - status = "okay"; - - m25p128@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "m25p128", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <20000000>; - mode = <0>; - - partition@0 { - reg = <0x00000000 0x00080000>; - label = "U-Boot"; - }; - - partition@200000 { - reg = <0x00200000 0x00200000>; - label = "Kernel"; - }; - - partition@400000 { - reg = <0x00400000 0x00900000>; - label = "RootFS1"; - }; - partition@d00000 { - reg = <0x00d00000 0x00300000>; - label = "RootFS2"; - }; - partition@40000 { - reg = <0x00080000 0x00040000>; - label = "U-Boot Config"; - }; - partition@c0000 { - reg = <0x000c0000 0x00140000>; - label = "NAS Config"; - }; - }; - }; - sata@80000 { - pinctrl-0 = <&pmx_sata0 &pmx_sata1>; - pinctrl-names = "default"; - status = "okay"; - nr-ports = <2>; - }; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@X { - /* overwrite reg property in board file */ - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; - -&pciec { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; - -&rtc { - /* - * There is a s35390a available on the i2c bus, the internal rtc isn't - * working (probably no crystal assembled). - */ - status = "disabled"; -}; diff --git a/sys/gnu/dts/arm/kirkwood-ts419-6281.dts b/sys/gnu/dts/arm/kirkwood-ts419-6281.dts deleted file mode 100644 index 4a42ebcca4f..00000000000 --- a/sys/gnu/dts/arm/kirkwood-ts419-6281.dts +++ /dev/null @@ -1,16 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Device Tree file for QNAP TS41X with 6281 SoC - * - * Copyright (C) 2013, Andrew Lunn - */ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" -#include "kirkwood-ts219.dtsi" -#include "kirkwood-ts419.dtsi" - -ðphy0 { reg = <8>; }; -ðphy1 { reg = <0>; }; diff --git a/sys/gnu/dts/arm/kirkwood-ts419-6282.dts b/sys/gnu/dts/arm/kirkwood-ts419-6282.dts deleted file mode 100644 index be772e194c2..00000000000 --- a/sys/gnu/dts/arm/kirkwood-ts419-6282.dts +++ /dev/null @@ -1,19 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Device Tree file for QNAP TS41X with 6282 SoC - * - * Copyright (C) 2013, Andrew Lunn - */ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6282.dtsi" -#include "kirkwood-ts219.dtsi" -#include "kirkwood-ts419.dtsi" - -ðphy0 { reg = <0>; }; -ðphy1 { reg = <1>; }; - -&pciec { status = "okay"; }; -&pcie1 { status = "okay"; }; diff --git a/sys/gnu/dts/arm/kirkwood-ts419.dtsi b/sys/gnu/dts/arm/kirkwood-ts419.dtsi deleted file mode 100644 index 717236853e4..00000000000 --- a/sys/gnu/dts/arm/kirkwood-ts419.dtsi +++ /dev/null @@ -1,71 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Device Tree include file for QNAP TS41X - * - * Copyright (C) 2013, Andrew Lunn - */ - -/ { - model = "QNAP TS419 family"; - compatible = "qnap,ts419", "marvell,kirkwood"; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pinctrl-names = "default"; - - pmx_USB_copy_button: pmx-USB-copy-button { - marvell,pins = "mpp43"; - marvell,function = "gpio"; - }; - pmx_reset_button: pmx-reset-button { - marvell,pins = "mpp37"; - marvell,function = "gpio"; - }; - /* - * JP1 indicates if an LCD module is installed - * on the serial port (0), or if the port is used - * as a console (1). - */ - pmx_jumper_jp1: pmx-jumper_jp1 { - marvell,pins = "mpp45"; - marvell,function = "gpio"; - }; - - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_reset_button &pmx_USB_copy_button>; - pinctrl-names = "default"; - - copy { - label = "USB Copy"; - linux,code = ; - gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; - }; - reset { - label = "Reset"; - linux,code = ; - gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&mdio { - status = "okay"; - - ethphy1: ethernet-phy@1 { - device_type = "ethernet-phy"; - /* overwrite reg property in board file */ - }; -}; - -ð1 { - status = "okay"; - ethernet1-port@0 { - phy-handle = <ðphy1>; - }; -}; diff --git a/sys/gnu/dts/arm/kirkwood.dtsi b/sys/gnu/dts/arm/kirkwood.dtsi deleted file mode 100644 index 2161e23bd98..00000000000 --- a/sys/gnu/dts/arm/kirkwood.dtsi +++ /dev/null @@ -1,394 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include -#include - -#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) - -/ { - #address-cells = <1>; - #size-cells = <1>; - compatible = "marvell,kirkwood"; - interrupt-parent = <&intc>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "marvell,feroceon"; - reg = <0>; - clocks = <&core_clk 1>, <&core_clk 3>, <&gate_clk 11>; - clock-names = "cpu_clk", "ddrclk", "powersave"; - }; - }; - - aliases { - gpio0 = &gpio0; - gpio1 = &gpio1; - i2c0 = &i2c0; - }; - - mbus@f1000000 { - compatible = "marvell,kirkwood-mbus", "simple-bus"; - #address-cells = <2>; - #size-cells = <1>; - /* If a board file needs to change this ranges it must replace it completely */ - ranges = ; - controller = <&mbusc>; - pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256 MiB memory space */ - pcie-io-aperture = <0xf2000000 0x100000>; /* 1 MiB I/O space */ - - nand: nand@12f { - #address-cells = <1>; - #size-cells = <1>; - cle = <0>; - ale = <1>; - bank-width = <1>; - compatible = "marvell,orion-nand"; - reg = ; - chip-delay = <25>; - /* set partition map and/or chip-delay in board dts */ - clocks = <&gate_clk 7>; - pinctrl-0 = <&pmx_nand>; - pinctrl-names = "default"; - status = "disabled"; - }; - - crypto_sram: sa-sram@301 { - compatible = "mmio-sram"; - reg = ; - clocks = <&gate_clk 17>; - #address-cells = <1>; - #size-cells = <1>; - }; - }; - - ocp@f1000000 { - compatible = "simple-bus"; - ranges = <0x00000000 0xf1000000 0x0100000>; - #address-cells = <1>; - #size-cells = <1>; - - pinctrl: pin-controller@10000 { - /* set compatible property in SoC file */ - reg = <0x10000 0x20>; - - pmx_ge1: pmx-ge1 { - marvell,pins = "mpp20", "mpp21", "mpp22", "mpp23", - "mpp24", "mpp25", "mpp26", "mpp27", - "mpp30", "mpp31", "mpp32", "mpp33"; - marvell,function = "ge1"; - }; - - pmx_nand: pmx-nand { - marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3", - "mpp4", "mpp5", "mpp18", "mpp19"; - marvell,function = "nand"; - }; - - /* - * Default SPI0 pinctrl setting with CSn on mpp0, - * overwrite marvell,pins on board level if required. - */ - pmx_spi: pmx-spi { - marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3"; - marvell,function = "spi"; - }; - - pmx_twsi0: pmx-twsi0 { - marvell,pins = "mpp8", "mpp9"; - marvell,function = "twsi0"; - }; - - /* - * Default UART pinctrl setting without RTS/CTS, - * overwrite marvell,pins on board level if required. - */ - pmx_uart0: pmx-uart0 { - marvell,pins = "mpp10", "mpp11"; - marvell,function = "uart0"; - }; - - pmx_uart1: pmx-uart1 { - marvell,pins = "mpp13", "mpp14"; - marvell,function = "uart1"; - }; - }; - - core_clk: core-clocks@10030 { - compatible = "marvell,kirkwood-core-clock"; - reg = <0x10030 0x4>; - #clock-cells = <1>; - }; - - spi0: spi@10600 { - compatible = "marvell,orion-spi"; - #address-cells = <1>; - #size-cells = <0>; - cell-index = <0>; - interrupts = <23>; - reg = <0x10600 0x28>; - clocks = <&gate_clk 7>; - pinctrl-0 = <&pmx_spi>; - pinctrl-names = "default"; - status = "disabled"; - }; - - gpio0: gpio@10100 { - compatible = "marvell,orion-gpio"; - #gpio-cells = <2>; - gpio-controller; - reg = <0x10100 0x40>; - ngpios = <32>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <35>, <36>, <37>, <38>; - clocks = <&gate_clk 7>; - }; - - gpio1: gpio@10140 { - compatible = "marvell,orion-gpio"; - #gpio-cells = <2>; - gpio-controller; - reg = <0x10140 0x40>; - ngpios = <18>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <39>, <40>, <41>; - clocks = <&gate_clk 7>; - }; - - i2c0: i2c@11000 { - compatible = "marvell,mv64xxx-i2c"; - reg = <0x11000 0x20>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <29>; - clock-frequency = <100000>; - clocks = <&gate_clk 7>; - pinctrl-0 = <&pmx_twsi0>; - pinctrl-names = "default"; - status = "disabled"; - }; - - uart0: serial@12000 { - compatible = "ns16550a"; - reg = <0x12000 0x100>; - reg-shift = <2>; - interrupts = <33>; - clocks = <&gate_clk 7>; - pinctrl-0 = <&pmx_uart0>; - pinctrl-names = "default"; - status = "disabled"; - }; - - uart1: serial@12100 { - compatible = "ns16550a"; - reg = <0x12100 0x100>; - reg-shift = <2>; - interrupts = <34>; - clocks = <&gate_clk 7>; - pinctrl-0 = <&pmx_uart1>; - pinctrl-names = "default"; - status = "disabled"; - }; - - mbusc: mbus-controller@20000 { - compatible = "marvell,mbus-controller"; - reg = <0x20000 0x80>, <0x1500 0x20>; - }; - - sysc: system-controller@20000 { - compatible = "marvell,orion-system-controller"; - reg = <0x20000 0x120>; - }; - - bridge_intc: bridge-interrupt-ctrl@20110 { - compatible = "marvell,orion-bridge-intc"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x20110 0x8>; - interrupts = <1>; - marvell,#interrupts = <6>; - }; - - gate_clk: clock-gating-control@2011c { - compatible = "marvell,kirkwood-gating-clock"; - reg = <0x2011c 0x4>; - clocks = <&core_clk 0>; - #clock-cells = <1>; - }; - - l2: l2-cache@20128 { - compatible = "marvell,kirkwood-cache"; - reg = <0x20128 0x4>; - }; - - intc: main-interrupt-ctrl@20200 { - compatible = "marvell,orion-intc"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x20200 0x10>, <0x20210 0x10>; - }; - - timer: timer@20300 { - compatible = "marvell,orion-timer"; - reg = <0x20300 0x20>; - interrupt-parent = <&bridge_intc>; - interrupts = <1>, <2>; - clocks = <&core_clk 0>; - }; - - wdt: watchdog-timer@20300 { - compatible = "marvell,orion-wdt"; - reg = <0x20300 0x28>, <0x20108 0x4>; - interrupt-parent = <&bridge_intc>; - interrupts = <3>; - clocks = <&gate_clk 7>; - status = "okay"; - }; - - cesa: crypto@30000 { - compatible = "marvell,kirkwood-crypto"; - reg = <0x30000 0x10000>; - reg-names = "regs"; - interrupts = <22>; - clocks = <&gate_clk 17>; - marvell,crypto-srams = <&crypto_sram>; - marvell,crypto-sram-size = <0x800>; - status = "okay"; - }; - - usb0: ehci@50000 { - compatible = "marvell,orion-ehci"; - reg = <0x50000 0x1000>; - interrupts = <19>; - clocks = <&gate_clk 3>; - status = "okay"; - }; - - dma0: xor@60800 { - compatible = "marvell,orion-xor"; - reg = <0x60800 0x100 - 0x60A00 0x100>; - status = "okay"; - clocks = <&gate_clk 8>; - - xor00 { - interrupts = <5>; - dmacap,memcpy; - dmacap,xor; - }; - xor01 { - interrupts = <6>; - dmacap,memcpy; - dmacap,xor; - dmacap,memset; - }; - }; - - dma1: xor@60900 { - compatible = "marvell,orion-xor"; - reg = <0x60900 0x100 - 0x60B00 0x100>; - status = "okay"; - clocks = <&gate_clk 16>; - - xor00 { - interrupts = <7>; - dmacap,memcpy; - dmacap,xor; - }; - xor01 { - interrupts = <8>; - dmacap,memcpy; - dmacap,xor; - dmacap,memset; - }; - }; - - eth0: ethernet-controller@72000 { - compatible = "marvell,kirkwood-eth"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x72000 0x4000>; - clocks = <&gate_clk 0>; - marvell,tx-checksum-limit = <1600>; - status = "disabled"; - - eth0port: ethernet0-port@0 { - compatible = "marvell,kirkwood-eth-port"; - reg = <0>; - interrupts = <11>; - /* overwrite MAC address in bootloader */ - local-mac-address = [00 00 00 00 00 00]; - /* set phy-handle property in board file */ - }; - }; - - mdio: mdio-bus@72004 { - compatible = "marvell,orion-mdio"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x72004 0x84>; - interrupts = <46>; - clocks = <&gate_clk 0>; - status = "disabled"; - - /* add phy nodes in board file */ - }; - - eth1: ethernet-controller@76000 { - compatible = "marvell,kirkwood-eth"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x76000 0x4000>; - clocks = <&gate_clk 19>; - marvell,tx-checksum-limit = <1600>; - pinctrl-0 = <&pmx_ge1>; - pinctrl-names = "default"; - status = "disabled"; - - eth1port: ethernet1-port@0 { - compatible = "marvell,kirkwood-eth-port"; - reg = <0>; - interrupts = <15>; - /* overwrite MAC address in bootloader */ - local-mac-address = [00 00 00 00 00 00]; - /* set phy-handle property in board file */ - }; - }; - - sata_phy0: sata-phy@82000 { - compatible = "marvell,mvebu-sata-phy"; - reg = <0x82000 0x0334>; - clocks = <&gate_clk 14>; - clock-names = "sata"; - #phy-cells = <0>; - status = "ok"; - }; - - sata_phy1: sata-phy@84000 { - compatible = "marvell,mvebu-sata-phy"; - reg = <0x84000 0x0334>; - clocks = <&gate_clk 15>; - clock-names = "sata"; - #phy-cells = <0>; - status = "ok"; - }; - - audio0: audio-controller@a0000 { - compatible = "marvell,kirkwood-audio"; - #sound-dai-cells = <0>; - reg = <0xa0000 0x2210>; - interrupts = <24>; - clocks = <&gate_clk 9>; - clock-names = "internal"; - status = "disabled"; - }; - }; -}; diff --git a/sys/gnu/dts/arm/logicpd-som-lv-35xx-devkit.dts b/sys/gnu/dts/arm/logicpd-som-lv-35xx-devkit.dts deleted file mode 100644 index 2a0a98fe67f..00000000000 --- a/sys/gnu/dts/arm/logicpd-som-lv-35xx-devkit.dts +++ /dev/null @@ -1,13 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only - -/dts-v1/; - -#include "omap34xx.dtsi" -#include "logicpd-som-lv.dtsi" -#include "logicpd-som-lv-baseboard.dtsi" -#include "omap-gpmc-smsc9221.dtsi" - -/ { - model = "LogicPD Zoom OMAP35xx SOM-LV Development Kit"; - compatible = "logicpd,dm3730-som-lv-devkit", "ti,omap3430", "ti,omap3"; -}; diff --git a/sys/gnu/dts/arm/logicpd-som-lv-37xx-devkit.dts b/sys/gnu/dts/arm/logicpd-som-lv-37xx-devkit.dts deleted file mode 100644 index a604d92221a..00000000000 --- a/sys/gnu/dts/arm/logicpd-som-lv-37xx-devkit.dts +++ /dev/null @@ -1,13 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only - -/dts-v1/; - -#include "omap36xx.dtsi" -#include "logicpd-som-lv.dtsi" -#include "logicpd-som-lv-baseboard.dtsi" -#include "omap-gpmc-smsc9221.dtsi" - -/ { - model = "LogicPD Zoom DM3730 SOM-LV Development Kit"; - compatible = "logicpd,dm3730-som-lv-devkit", "ti,omap3630", "ti,omap3"; -}; diff --git a/sys/gnu/dts/arm/logicpd-som-lv-baseboard.dtsi b/sys/gnu/dts/arm/logicpd-som-lv-baseboard.dtsi deleted file mode 100644 index 100396f6c2f..00000000000 --- a/sys/gnu/dts/arm/logicpd-som-lv-baseboard.dtsi +++ /dev/null @@ -1,252 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only - -/ { - gpio_keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&gpio_key_pins>; - - sysboot2 { - label = "gpio3"; - gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* gpio_111 / uP_GPIO_3 */ - linux,code = ; - wakeup-source; - }; - }; - - sound { - compatible = "ti,omap-twl4030"; - ti,model = "omap3logic"; - ti,mcbsp = <&mcbsp2>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins &led_pins_wkup>; - - led1 { - label = "led1"; - gpios = <&gpio5 5 GPIO_ACTIVE_LOW>; /* gpio133 */ - linux,default-trigger = "cpu0"; - }; - - led2 { - label = "led2"; - gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; /* gpio11 */ - linux,default-trigger = "none"; - }; - }; -}; - -&vaux1 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; -}; - -&vaux4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; -}; - -&mcbsp2 { - status = "okay"; -}; - -&charger { - ti,bb-uvolt = <3200000>; - ti,bb-uamp = <150>; -}; - -&gpmc { - ranges = <0 0 0x30000000 0x1000000 /* CS0: 16MB for NAND */ - 1 0 0x2c000000 0x1000000 /* CS1: 16MB for LAN9221 */ - 2 0 0x10000000 0x2000000>; /* CS2: 32MB for NOR */ - - ethernet@gpmc { - pinctrl-names = "default"; - pinctrl-0 = <&lan9221_pins>; - interrupt-parent = <&gpio5>; - interrupts = <24 IRQ_TYPE_LEVEL_LOW>; /* gpio_152 */ - reg = <1 0 0xff>; - }; -}; - -&vpll2 { - regulator-always-on; -}; - -&dss { - status = "ok"; - vdds_dsi-supply = <&vpll2>; - vdda_video-supply = <&video_reg>; - pinctrl-names = "default"; - pinctrl-0 = <&dss_dpi_pins1>; - port { - dpi_out: endpoint { - remote-endpoint = <&lcd_in>; - data-lines = <16>; - }; - }; -}; - -/ { - aliases { - display0 = &lcd0; - }; - - video_reg: video_reg { - compatible = "regulator-fixed"; - regulator-name = "fixed-supply"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - lcd0: display@0 { - compatible = "panel-dpi"; - label = "28"; - status = "okay"; - /* default-on; */ - pinctrl-names = "default"; - pinctrl-0 = <&lcd_enable_pin>; - enable-gpios = <&gpio5 27 GPIO_ACTIVE_HIGH>; /* gpio155, lcd INI */ - port { - lcd_in: endpoint { - remote-endpoint = <&dpi_out>; - }; - }; - - panel-timing { - clock-frequency = <9000000>; - hactive = <480>; - vactive = <272>; - hfront-porch = <3>; - hback-porch = <2>; - hsync-len = <42>; - vback-porch = <3>; - vfront-porch = <2>; - vsync-len = <11>; - hsync-active = <1>; - vsync-active = <1>; - de-active = <1>; - pixelclk-active = <0>; - }; - }; - - bl: backlight { - compatible = "pwm-backlight"; - pinctrl-names = "default"; - pinctrl-0 = <&backlight_pins>; - pwms = <&twl_pwm 0 5000000>; - brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; - default-brightness-level = <7>; - enable-gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; /* gpio_8 */ - }; -}; - -&mmc1 { - interrupts-extended = <&intc 83 &omap3_pmx_core 0x11a>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - wp-gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>; /* gpio_126 */ - cd-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>; /* gpio_110 */ - vmmc-supply = <&vmmc1>; - bus-width = <4>; - cap-power-off-card; -}; - -&omap3_pmx_core { - gpio_key_pins: pinmux_gpio_key_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x212e, PIN_INPUT_PULLUP | MUX_MODE4) /* cam_xclkb.gpio_111 / uP_GPIO_3*/ - >; - }; - - led_pins: pinmux_led_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x215e, PIN_OUTPUT_PULLUP | MUX_MODE4) /* sdmmc2_dat1.gpio_133 / uP_GPIO_0 */ - >; - }; - - lan9221_pins: pinmux_lan9221_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT_PULLUP | MUX_MODE4) /* mcbsp4_clkx.gpio_152 */ - >; - }; - - mmc1_pins: pinmux_mmc1_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2144, PIN_OUTPUT | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ - OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ - OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ - OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ - OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ - OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ - OMAP3_CORE1_IOPAD(0x2132, PIN_INPUT_PULLUP | MUX_MODE4) /* cam_strobe.gpio_126 */ - OMAP3_CORE1_IOPAD(0x212c, PIN_INPUT_PULLUP | MUX_MODE4) /* cam_d11.gpio_110 */ - >; - }; - - lcd_enable_pin: pinmux_lcd_enable_pin { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x218a, PIN_OUTPUT | PIN_OFF_OUTPUT_LOW | MUX_MODE4) /* mcbsp4_fs.gpio_155 */ - >; - }; - - dss_dpi_pins1: pinmux_dss_dpi_pins1 { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_pclk.dss_pclk */ - OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_hsync.dss_hsync */ - OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_vsync.dss_vsync */ - OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_acbias.dss_acbias */ - - OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data0.dss_data0 */ - OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data1.dss_data1 */ - OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data2.dss_data2 */ - OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data3.dss_data3 */ - OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data4.dss_data4 */ - OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data5.dss_data5 */ - OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data6.dss_data6 */ - OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data7.dss_data7 */ - OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data8.dss_data8 */ - OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data9.dss_data9 */ - OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data10.dss_data10 */ - OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data11.dss_data11 */ - OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data12.dss_data12 */ - OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data13.dss_data13 */ - OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data14.dss_data14 */ - OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data15.dss_data15 */ - >; - }; -}; - -&omap3_pmx_wkup { - led_pins_wkup: pinmux_led_pins_wkup { - pinctrl-single,pins = < - OMAP3_WKUP_IOPAD(0x2a24, PIN_OUTPUT_PULLUP | MUX_MODE4) /* jtag_emu0.gpio_11 / uP_GPIO_1 */ - >; - }; - - backlight_pins: pinmux_backlight_pins { - pinctrl-single,pins = < - OMAP3_WKUP_IOPAD(0x2a16, PIN_OUTPUT | PIN_OFF_OUTPUT_LOW | MUX_MODE4) /* sys_boot6.gpio_8 */ - >; - }; -}; - - -&uart1 { - interrupts-extended = <&intc 72 &omap3_pmx_core OMAP3_UART1_RX>; -}; - -/* Wired to the tps65950 on the SOM, only the USB connector is on the devkit */ -&usb_otg_hs { - pinctrl-names = "default"; - pinctrl-0 = <&hsusb_otg_pins>; - interface-type = <0>; - usb-phy = <&usb2_phy>; - phys = <&usb2_phy>; - phy-names = "usb2-phy"; - mode = <3>; - power = <50>; -}; diff --git a/sys/gnu/dts/arm/logicpd-som-lv.dtsi b/sys/gnu/dts/arm/logicpd-som-lv.dtsi deleted file mode 100644 index b56524cc7fe..00000000000 --- a/sys/gnu/dts/arm/logicpd-som-lv.dtsi +++ /dev/null @@ -1,311 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only - -#include - -/ { - cpus { - cpu@0 { - cpu0-supply = <&vcc>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0>; - }; - - wl12xx_vmmc: wl12xx_vmmc { - compatible = "regulator-fixed"; - regulator-name = "vwl1271"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio1 3 0>; /* gpio_3 */ - startup-delay-us = <70000>; - enable-active-high; - vin-supply = <&vaux3>; - }; - - /* HS USB Host PHY on PORT 1 */ - hsusb2_phy: hsusb2_phy { - compatible = "usb-nop-xceiv"; - reset-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; /* gpio_4 */ - #phy-cells = <0>; - }; - - /* fixed 26MHz oscillator */ - hfclk_26m: oscillator { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <26000000>; - }; -}; - -&gpmc { - ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */ - - nand@0,0 { - compatible = "ti,omap2-nand"; - reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ - <1 IRQ_TYPE_NONE>; /* termcount */ - linux,mtd-name = "micron,mt29f4g16abbda3w"; - nand-bus-width = <16>; - ti,nand-ecc-opt = "bch8"; - rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <44>; - gpmc,cs-wr-off-ns = <44>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <34>; - gpmc,adv-wr-off-ns = <44>; - gpmc,we-off-ns = <40>; - gpmc,oe-off-ns = <54>; - gpmc,access-ns = <64>; - gpmc,rd-cycle-ns = <82>; - gpmc,wr-cycle-ns = <82>; - gpmc,wr-access-ns = <40>; - gpmc,wr-data-mux-bus-ns = <0>; - gpmc,device-width = <2>; - #address-cells = <1>; - #size-cells = <1>; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - clock-frequency = <2600000>; - - twl: twl@48 { - reg = <0x48>; - interrupts = <7>; /* SYS_NIRQ cascaded to intc */ - interrupt-parent = <&intc>; - clocks = <&hfclk_26m>; - clock-names = "fck"; - twl_audio: audio { - compatible = "ti,twl4030-audio"; - codec { - ti,hs_extmute_gpio = <&gpio2 25 GPIO_ACTIVE_HIGH>; - }; - }; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - clock-frequency = <400000>; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_pins>; - clock-frequency = <400000>; - - touchscreen: tsc2004@48 { - compatible = "ti,tsc2004"; - reg = <0x48>; - vio-supply = <&vaux1>; - pinctrl-names = "default"; - pinctrl-0 = <&tsc2004_pins>; - interrupts-extended = <&gpio5 25 IRQ_TYPE_EDGE_RISING>; /* gpio 153 */ - - touchscreen-fuzz-x = <4>; - touchscreen-fuzz-y = <7>; - touchscreen-fuzz-pressure = <2>; - touchscreen-size-x = <4096>; - touchscreen-size-y = <4096>; - touchscreen-max-pressure = <2048>; - - ti,x-plate-ohms = <280>; - ti,esd-recovery-timeout-ms = <8000>; - }; -}; - -&mmc3 { - interrupts-extended = <&intc 94 &omap3_pmx_core 0x136>; - pinctrl-0 = <&mmc3_pins &wl127x_gpio>; - pinctrl-names = "default"; - vmmc-supply = <&wl12xx_vmmc>; - non-removable; - bus-width = <4>; - cap-power-off-card; - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@2 { - compatible = "ti,wl1273"; - reg = <2>; - interrupt-parent = <&gpio1>; - interrupts = <2 IRQ_TYPE_EDGE_RISING>; /* gpio 2 */ - ref-clock-frequency = <26000000>; - }; -}; - -&usbhshost { - port2-mode = "ehci-phy"; -}; - -&usbhsehci { - phys = <0 &hsusb2_phy>; -}; - - -&omap3_pmx_core { - pinctrl-names = "default"; - pinctrl-0 = <&hsusb2_pins>; - - mmc3_pins: pinmux_mm3_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat4.sdmmc3_dat0 */ - OMAP3_CORE1_IOPAD(0x2166, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat5.sdmmc3_dat1 */ - OMAP3_CORE1_IOPAD(0x2168, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat6.sdmmc3_dat2 */ - OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat6.sdmmc3_dat3 */ - OMAP3_CORE1_IOPAD(0x21d0, PIN_INPUT_PULLUP | MUX_MODE3) /* mcspi1_cs1.sdmmc3_cmd */ - OMAP3_CORE1_IOPAD(0x21d2, PIN_INPUT_PULLUP | MUX_MODE3) /* mcspi1_cs2.sdmmc_clk */ - >; - }; - mcbsp2_pins: pinmux_mcbsp2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx */ - OMAP3_CORE1_IOPAD(0x213e, PIN_INPUT | MUX_MODE0) /* mcbsp2_clkx */ - OMAP3_CORE1_IOPAD(0x2140, PIN_INPUT | MUX_MODE0) /* mcbsp2_dr */ - OMAP3_CORE1_IOPAD(0x2142, PIN_OUTPUT | MUX_MODE0) /* mcbsp2_dx */ - >; - }; - uart2_pins: pinmux_uart2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT | MUX_MODE0) /* uart2_cts.uart2_cts */ - OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts .uart2_rts*/ - OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ - OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */ - OMAP3_CORE1_IOPAD(0x2198, PIN_OUTPUT | MUX_MODE4) /* GPIO_162,BT_EN */ - >; - }; - mcspi1_pins: pinmux_mcspi1_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */ - OMAP3_CORE1_IOPAD(0x21ca, PIN_OUTPUT | MUX_MODE0) /* mcspi1_simo.mcspi1_simo */ - OMAP3_CORE1_IOPAD(0x21cc, PIN_INPUT_PULLUP | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */ - OMAP3_CORE1_IOPAD(0x21ce, PIN_OUTPUT | MUX_MODE0) /* mcspi1_cs0.mcspi1_cs0 */ - >; - }; - - hsusb2_pins: pinmux_hsusb2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */ - OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */ - OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */ - OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */ - OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */ - OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */ - >; - }; - - hsusb_otg_pins: pinmux_hsusb_otg_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21a2, PIN_INPUT | MUX_MODE0) /* hsusb0_clk.hsusb0_clk */ - OMAP3_CORE1_IOPAD(0x21a4, PIN_OUTPUT | MUX_MODE0) /* hsusb0_stp.hsusb0_stp */ - OMAP3_CORE1_IOPAD(0x21a6, PIN_INPUT | MUX_MODE0) /* hsusb0_dir.hsusb0_dir */ - OMAP3_CORE1_IOPAD(0x21a8, PIN_INPUT | MUX_MODE0) /* hsusb0_nxt.hsusb0_nxt */ - OMAP3_CORE1_IOPAD(0x21aa, PIN_INPUT | MUX_MODE0) /* hsusb0_data0.hsusb0_data0 */ - OMAP3_CORE1_IOPAD(0x21ac, PIN_INPUT | MUX_MODE0) /* hsusb0_data1.hsusb0_data1 */ - OMAP3_CORE1_IOPAD(0x21ae, PIN_INPUT | MUX_MODE0) /* hsusb0_data2.hsusb0_data2 */ - OMAP3_CORE1_IOPAD(0x21b0, PIN_INPUT | MUX_MODE0) /* hsusb0_data3.hsusb0_data3 */ - OMAP3_CORE1_IOPAD(0x21b2, PIN_INPUT | MUX_MODE0) /* hsusb0_data4.hsusb0_data4 */ - OMAP3_CORE1_IOPAD(0x21b4, PIN_INPUT | MUX_MODE0) /* hsusb0_data5.hsusb0_data5 */ - OMAP3_CORE1_IOPAD(0x21b6, PIN_INPUT | MUX_MODE0) /* hsusb0_data6.hsusb0_data6 */ - OMAP3_CORE1_IOPAD(0x21b8, PIN_INPUT | MUX_MODE0) /* hsusb0_data7.hsusb0_data7 */ - >; - }; - - i2c1_pins: pinmux_i2c1_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */ - OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */ - OMAP3_CORE1_IOPAD(0x20ba, PIN_OUTPUT | MUX_MODE4) /* gpmc_ncs6.gpio_57 */ - >; - }; - - i2c2_pins: pinmux_i2c2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT | MUX_MODE0) /* i2c2_scl */ - OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT | MUX_MODE0) /* i2c2_sda */ - >; - }; - - i2c3_pins: pinmux_i2c3_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl */ - OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda */ - >; - }; - - tsc2004_pins: pinmux_tsc2004_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT | MUX_MODE4) /* mcbsp4_dr.gpio_153 */ - >; - }; -}; - -&omap3_pmx_wkup { - pinctrl-names = "default"; - pinctrl-0 = <&hsusb2_reset_pin>; - hsusb2_reset_pin: pinmux_hsusb1_reset_pin { - pinctrl-single,pins = < - OMAP3_WKUP_IOPAD(0x2a0e, PIN_OUTPUT | MUX_MODE4) /* sys_boot2.gpio_4 */ - >; - }; - wl127x_gpio: pinmux_wl127x_gpio_pin { - pinctrl-single,pins = < - OMAP3_WKUP_IOPAD(0x2a0a, PIN_INPUT | MUX_MODE4) /* sys_boot0.gpio_2 */ - OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE4) /* sys_boot1.gpio_3 */ - >; - }; -}; - -&omap3_pmx_core2 { - pinctrl-names = "default"; - pinctrl-0 = <&hsusb2_2_pins>; - hsusb2_2_pins: pinmux_hsusb2_2_pins { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ - OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ - OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ - OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ - OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ - OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ - >; - }; -}; - -&uart2 { - interrupts-extended = <&intc 73 &omap3_pmx_core OMAP3_UART2_RX>; - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; -}; - -&mcspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&mcspi1_pins>; -}; - -#include "twl4030.dtsi" -#include "twl4030_omap3.dtsi" - -&vaux3 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; -}; - -&twl { - twl_power: power { - compatible = "ti,twl4030-power-idle-osc-off", "ti,twl4030-power-idle"; - ti,use_poweroff; - }; -}; - -&twl_gpio { - ti,use-leds; -}; diff --git a/sys/gnu/dts/arm/logicpd-torpedo-35xx-devkit.dts b/sys/gnu/dts/arm/logicpd-torpedo-35xx-devkit.dts deleted file mode 100644 index 57bae2aa910..00000000000 --- a/sys/gnu/dts/arm/logicpd-torpedo-35xx-devkit.dts +++ /dev/null @@ -1,13 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only - -/dts-v1/; - -#include "omap34xx.dtsi" -#include "logicpd-torpedo-som.dtsi" -#include "logicpd-torpedo-baseboard.dtsi" -#include "omap-gpmc-smsc9221.dtsi" - -/ { - model = "LogicPD Zoom OMAP35xx Torpedo Development Kit"; - compatible = "logicpd,dm3730-torpedo-devkit", "ti,omap3430", "ti,omap3"; -}; diff --git a/sys/gnu/dts/arm/logicpd-torpedo-37xx-devkit-28.dts b/sys/gnu/dts/arm/logicpd-torpedo-37xx-devkit-28.dts deleted file mode 100644 index b5536132971..00000000000 --- a/sys/gnu/dts/arm/logicpd-torpedo-37xx-devkit-28.dts +++ /dev/null @@ -1,15 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -/dts-v1/; - -/* - * There are two types of 4.3" LCD, Type 15 and Type 28. - * By default, type 15 was used. This device tree file - * uses the timing for the type 28 LCD - */ - -#include "logicpd-torpedo-37xx-devkit.dts" - -&lcd0 { - compatible = "logicpd,type28"; -}; diff --git a/sys/gnu/dts/arm/logicpd-torpedo-37xx-devkit.dts b/sys/gnu/dts/arm/logicpd-torpedo-37xx-devkit.dts deleted file mode 100644 index 5532db04046..00000000000 --- a/sys/gnu/dts/arm/logicpd-torpedo-37xx-devkit.dts +++ /dev/null @@ -1,87 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only - -/dts-v1/; - -#include "omap36xx.dtsi" -#include "logicpd-torpedo-som.dtsi" -#include "omap-gpmc-smsc9221.dtsi" -#include "logicpd-torpedo-baseboard.dtsi" - -/ { - model = "LogicPD Zoom DM3730 Torpedo + Wireless Development Kit"; - compatible = "logicpd,dm3730-torpedo-devkit", "ti,omap3630", "ti,omap3"; - - wl12xx_vmmc: wl12xx_vmmc { - compatible = "regulator-fixed"; - regulator-name = "vwl1271"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio5 29 0>; /* gpio157 */ - startup-delay-us = <70000>; - enable-active-high; - vin-supply = <&vmmc2>; - }; -}; - -/* - * Only found on the wireless SOM. For the SOM without wireless, the pins for - * MMC3 can be routed with jumpers to the second MMC slot on the devkit and - * gpio157 is not connected. So this should be OK to keep common for now, - * probably device tree overlays is the way to go with the various SOM and - * jumpering combinations for the long run. - */ -&mmc3 { - interrupts-extended = <&intc 94 &omap3_pmx_core 0x136>; - pinctrl-0 = <&mmc3_pins &mmc3_core2_pins>; - pinctrl-names = "default"; - vmmc-supply = <&wl12xx_vmmc>; - non-removable; - bus-width = <4>; - cap-power-off-card; - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@2 { - compatible = "ti,wl1283"; - reg = <2>; - interrupt-parent = <&gpio5>; - interrupts = <24 IRQ_TYPE_EDGE_RISING>; /* gpio 152 */ - ref-clock-frequency = <26000000>; - tcxo-clock-frequency = <26000000>; - }; -}; - -&uart2 { - /delete-property/dma-names; - bluetooth { - compatible = "ti,wl1283-st"; - enable-gpios = <&gpio6 2 GPIO_ACTIVE_HIGH>; /* gpio 162 */ - max-speed = <3000000>; - }; -}; - -/* The DM3730 has a faster L3 than OMAP35, so increase pixel clock */ -&mt9p031_out { - pixel-clock-frequency = <90000000>; -}; - -&omap3_pmx_core { - mmc3_pins: pinmux_mm3_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat4.sdmmc3_dat0 */ - OMAP3_CORE1_IOPAD(0x2166, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat5.sdmmc3_dat1 */ - OMAP3_CORE1_IOPAD(0x2168, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat6.sdmmc3_dat2 */ - OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat6.sdmmc3_dat3 */ - OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT_PULLUP | MUX_MODE4) /* mcbsp4_clkx.gpio_152 */ - OMAP3_CORE1_IOPAD(0x218e, PIN_OUTPUT | MUX_MODE4) /* mcbsp1_fsr.gpio_157 */ - >; - }; -}; - -&omap3_pmx_core2 { - mmc3_core2_pins: pinmux_mmc3_core2_pins { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25d8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_clk.sdmmc3_clk */ - OMAP3630_CORE2_IOPAD(0x25da, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_ctl.sdmmc3_cmd */ - >; - }; -}; diff --git a/sys/gnu/dts/arm/logicpd-torpedo-baseboard.dtsi b/sys/gnu/dts/arm/logicpd-torpedo-baseboard.dtsi deleted file mode 100644 index f7b82ced408..00000000000 --- a/sys/gnu/dts/arm/logicpd-torpedo-baseboard.dtsi +++ /dev/null @@ -1,378 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only - -/ { - gpio_keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&gpio_key_pins &gpio_key_pins_wkup>; - - sysboot2 { - label = "sysboot2"; - gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; /* gpio2 */ - linux,code = ; - wakeup-source; - }; - - sysboot5 { - label = "sysboot5"; - gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; /* gpio7 */ - linux,code = ; - wakeup-source; - }; - - gpio1 { - label = "gpio1"; - gpios = <&gpio6 21 GPIO_ACTIVE_LOW>; /* gpio181 */ - linux,code = ; - wakeup-source; - }; - - gpio2 { - label = "gpio2"; - gpios = <&gpio6 18 GPIO_ACTIVE_LOW>; /* gpio178 */ - linux,code = ; - wakeup-source; - }; - }; - - sound { - compatible = "ti,omap-twl4030"; - ti,model = "omap3logic"; - ti,mcbsp = <&mcbsp2>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins>; - - led1 { - label = "led1"; - gpios = <&gpio6 20 GPIO_ACTIVE_HIGH>; /* gpio180 */ - linux,default-trigger = "cpu0"; - }; - - led2 { - label = "led2"; - gpios = <&gpio6 19 GPIO_ACTIVE_HIGH>; /* gpio179 */ - linux,default-trigger = "none"; - }; - }; - - pwm10: dmtimer-pwm { - compatible = "ti,omap-dmtimer-pwm"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm_pins>; - ti,timers = <&timer10>; - #pwm-cells = <3>; - }; - -}; - -&vaux1 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; -}; - -&vaux4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; -}; - -&mcbsp2 { - status = "okay"; -}; - -&charger { - ti,bb-uvolt = <3200000>; - ti,bb-uamp = <150>; -}; - -&gpmc { - ranges = <0 0 0x30000000 0x1000000 /* CS0: 16MB for NAND */ - 1 0 0x2c000000 0x1000000>; /* CS1: 16MB for LAN9221 */ - - ethernet@gpmc { - pinctrl-names = "default"; - pinctrl-0 = <&lan9221_pins>; - interrupt-parent = <&gpio5>; - interrupts = <1 IRQ_TYPE_LEVEL_LOW>; /* gpio129 */ - reg = <1 0 0xff>; - }; -}; - -&hdqw1w { - pinctrl-names = "default"; - pinctrl-0 = <&hdq_pins>; -}; - - -&vpll2 { - regulator-always-on; -}; - -&dss { - status = "ok"; - vdds_dsi-supply = <&vpll2>; - vdda_video-supply = <&vpll2>; - pinctrl-names = "default"; - pinctrl-0 = <&dss_dpi_pins1>; - port { - dpi_out: endpoint { - remote-endpoint = <&lcd_in>; - data-lines = <16>; - }; - }; -}; - -/ { - aliases { - display0 = &lcd0; - }; - - lcd0: display { - /* This isn't the exact LCD, but the timings meet spec */ - compatible = "newhaven,nhd-4.3-480272ef-atxl"; - label = "15"; - pinctrl-names = "default"; - pinctrl-0 = <&panel_pwr_pins>; - backlight = <&bl>; - enable-gpios = <&gpio5 27 GPIO_ACTIVE_HIGH>; - port { - lcd_in: endpoint { - remote-endpoint = <&dpi_out>; - }; - }; - }; - - bl: backlight { - compatible = "pwm-backlight"; - pinctrl-names = "default"; - pinctrl-0 = <&backlight_pins>; - pwms = <&pwm10 0 5000000 0>; - brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; - default-brightness-level = <7>; - enable-gpios = <&gpio5 26 GPIO_ACTIVE_HIGH>; /* gpio_154 */ - }; -}; - -&mmc1 { - interrupts-extended = <&intc 83 &omap3_pmx_core 0x11a>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins &mmc1_cd>; - cd-gpios = <&gpio4 31 GPIO_ACTIVE_LOW>; /* gpio127 */ - vmmc-supply = <&vmmc1>; - bus-width = <4>; - cap-power-off-card; -}; - -&omap3_pmx_core { - gpio_key_pins: pinmux_gpio_key_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLUP | MUX_MODE4) /* mcspi2_clk.gpio_178 */ - OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLUP | MUX_MODE4) /* mcspi2_cs0.gpio_181 */ - >; - }; - - hdq_pins: hdq_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21c6, PIN_INPUT_PULLUP | MUX_MODE0) /* hdq_sio */ - >; - }; - - pwm_pins: pinmux_pwm_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20B8, PIN_OUTPUT | PIN_OFF_OUTPUT_LOW | MUX_MODE3) /* gpmc_ncs5.gpt_10_pwm_evt */ - >; - }; - - led_pins: pinmux_led_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21d8, PIN_OUTPUT | MUX_MODE4) /* gpio_179 */ - OMAP3_CORE1_IOPAD(0x21da, PIN_OUTPUT | MUX_MODE4) /* gpio_180 */ - >; - }; - - mmc1_pins: pinmux_mmc1_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2144, PIN_OUTPUT | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ - OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ - OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ - OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ - OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ - OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ - >; - }; - - tsc2004_pins: pinmux_tsc2004_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT | MUX_MODE4) /* mcbsp4_dr.gpio_153 */ - >; - }; - - backlight_pins: pinmux_backlight_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2188, PIN_OUTPUT | PIN_OFF_OUTPUT_LOW | MUX_MODE4) /* mcbsp4_dx.gpio_154 */ - >; - }; - - isp_pins: pinmux_isp_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x210c, PIN_INPUT | MUX_MODE0) /* cam_hs.cam_hs */ - OMAP3_CORE1_IOPAD(0x210e, PIN_INPUT | MUX_MODE0) /* cam_vs.cam_vs */ - OMAP3_CORE1_IOPAD(0x2110, PIN_INPUT | MUX_MODE0) /* cam_xclka.cam_xclka */ - OMAP3_CORE1_IOPAD(0x2112, PIN_INPUT | MUX_MODE0) /* cam_pclk.cam_pclk */ - - OMAP3_CORE1_IOPAD(0x2116, PIN_INPUT | MUX_MODE0) /* cam_d0.cam_d0 */ - OMAP3_CORE1_IOPAD(0x2118, PIN_INPUT | MUX_MODE0) /* cam_d1.cam_d1 */ - OMAP3_CORE1_IOPAD(0x211a, PIN_INPUT | MUX_MODE0) /* cam_d2.cam_d2 */ - OMAP3_CORE1_IOPAD(0x211c, PIN_INPUT | MUX_MODE0) /* cam_d3.cam_d3 */ - OMAP3_CORE1_IOPAD(0x211e, PIN_INPUT | MUX_MODE0) /* cam_d4.cam_d4 */ - OMAP3_CORE1_IOPAD(0x2120, PIN_INPUT | MUX_MODE0) /* cam_d5.cam_d5 */ - OMAP3_CORE1_IOPAD(0x2122, PIN_INPUT | MUX_MODE0) /* cam_d6.cam_d6 */ - OMAP3_CORE1_IOPAD(0x2124, PIN_INPUT | MUX_MODE0) /* cam_d7.cam_d7 */ - >; - }; - - panel_pwr_pins: pinmux_panel_pwr_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x218a, PIN_OUTPUT | PIN_OFF_OUTPUT_LOW | MUX_MODE4) /* mcbsp4_fs.gpio_155 */ - >; - }; - - dss_dpi_pins1: pinmux_dss_dpi_pins1 { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_pclk.dss_pclk */ - OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_hsync.dss_hsync */ - OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_vsync.dss_vsync */ - OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_acbias.dss_acbias */ - - OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data6.dss_data6 */ - OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data7.dss_data7 */ - OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data8.dss_data8 */ - OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data9.dss_data9 */ - OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data10.dss_data10 */ - OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data11.dss_data11 */ - OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data12.dss_data12 */ - OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data13.dss_data13 */ - OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data14.dss_data14 */ - OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data15.dss_data15 */ - OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data16.dss_data16 */ - OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data17.dss_data17 */ - - OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE3) /* dss_data18.dss_data0 */ - OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE3) /* dss_data19.dss_data1 */ - OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE3) /* dss_data20.dss_data2 */ - OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE3) /* dss_data21.dss_data3 */ - OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE3) /* dss_data22.dss_data4 */ - OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE3) /* dss_data23.dss_data5 */ - >; - }; -}; - -&omap3_pmx_wkup { - gpio_key_pins_wkup: pinmux_gpio_key_pins_wkup { - pinctrl-single,pins = < - OMAP3_WKUP_IOPAD(0x2a0a, PIN_INPUT_PULLUP | MUX_MODE4) /* sys_boot0.gpio_2 */ - OMAP3_WKUP_IOPAD(0x2a14, PIN_INPUT_PULLUP | MUX_MODE4) /* sys_boot5.gpio_7 */ - >; - }; - - lan9221_pins: pinmux_lan9221_pins { - pinctrl-single,pins = < - OMAP3_WKUP_IOPAD(0x2a5a, PIN_INPUT | MUX_MODE4) /* reserved.gpio_129 */ - >; - }; - - mmc1_cd: pinmux_mmc1_cd { - pinctrl-single,pins = < - OMAP3_WKUP_IOPAD(0x2a54, PIN_INPUT_PULLUP | MUX_MODE4) /* reserved.gpio_127 */ - >; - }; -}; - -&i2c2 { - mt9p031@48 { - compatible = "aptina,mt9p031"; - reg = <0x48>; - clocks = <&isp 0>; - vaa-supply = <&vaux4>; - vdd-supply = <&vaux4>; - vdd_io-supply = <&vaux4>; - port { - mt9p031_out: endpoint { - input-clock-frequency = <24000000>; - pixel-clock-frequency = <72000000>; - remote-endpoint = <&ccdc_ep>; - }; - }; - }; -}; - -&i2c3 { - touchscreen: tsc2004@48 { - compatible = "ti,tsc2004"; - reg = <0x48>; - vio-supply = <&vaux1>; - pinctrl-names = "default"; - pinctrl-0 = <&tsc2004_pins>; - interrupts-extended = <&gpio5 25 IRQ_TYPE_EDGE_RISING>; /* gpio 153 */ - - touchscreen-fuzz-x = <4>; - touchscreen-fuzz-y = <7>; - touchscreen-fuzz-pressure = <2>; - touchscreen-size-x = <4096>; - touchscreen-size-y = <4096>; - touchscreen-max-pressure = <2048>; - - ti,x-plate-ohms = <280>; - ti,esd-recovery-timeout-ms = <8000>; - }; -}; - -&mcspi1 { - at25@0 { - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <5000000>; - spi-cpha; - spi-cpol; - - pagesize = <64>; - size = <32768>; - address-width = <16>; - }; -}; - -&isp { - pinctrl-names = "default"; - pinctrl-0 = <&isp_pins>; - ports { - port@0 { - reg = <0>; - ccdc_ep: endpoint { - remote-endpoint = <&mt9p031_out>; - bus-width = <8>; - hsync-active = <1>; - vsync-active = <1>; - pclk-sample = <0>; - }; - }; - }; -}; - -&uart1 { - interrupts-extended = <&intc 72 &omap3_pmx_core OMAP3_UART1_RX>; -}; - -/* Wired to the tps65950 on the SOM, only the USB connector is on the devkit */ -&usb_otg_hs { - pinctrl-names = "default"; - pinctrl-0 = <&hsusb_otg_pins>; - interface-type = <0>; - usb-phy = <&usb2_phy>; - phys = <&usb2_phy>; - phy-names = "usb2-phy"; - mode = <3>; - power = <50>; -}; diff --git a/sys/gnu/dts/arm/logicpd-torpedo-som.dtsi b/sys/gnu/dts/arm/logicpd-torpedo-som.dtsi deleted file mode 100644 index 3a5228562b0..00000000000 --- a/sys/gnu/dts/arm/logicpd-torpedo-som.dtsi +++ /dev/null @@ -1,203 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only - -#include - -/ { - chosen { - stdout-path = &uart1; - }; - - cpus { - cpu@0 { - cpu0-supply = <&vcc>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0>; - }; - - leds { - compatible = "gpio-leds"; - user0 { - label = "user0"; - gpios = <&twl_gpio 18 GPIO_ACTIVE_LOW>; /* LEDA */ - linux,default-trigger = "none"; - }; - }; - - /* fixed 26MHz oscillator */ - hfclk_26m: oscillator { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <26000000>; - }; -}; - -/* The Torpedo doesn't route the USB host pins */ -&usbhshost { - status = "disabled"; -}; - -&gpmc { - ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */ - - nand@0,0 { - compatible = "ti,omap2-nand"; - reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ - <1 IRQ_TYPE_NONE>; /* termcount */ - linux,mtd-name = "micron,mt29f4g16abbda3w"; - nand-bus-width = <16>; - ti,nand-ecc-opt = "bch8"; - rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <44>; - gpmc,cs-wr-off-ns = <44>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <34>; - gpmc,adv-wr-off-ns = <44>; - gpmc,we-off-ns = <40>; - gpmc,oe-off-ns = <54>; - gpmc,access-ns = <64>; - gpmc,rd-cycle-ns = <82>; - gpmc,wr-cycle-ns = <82>; - gpmc,wr-access-ns = <40>; - gpmc,wr-data-mux-bus-ns = <0>; - gpmc,device-width = <2>; - #address-cells = <1>; - #size-cells = <1>; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - clock-frequency = <2600000>; - - twl: twl@48 { - reg = <0x48>; - interrupts = <7>; /* SYS_NIRQ cascaded to intc */ - interrupt-parent = <&intc>; - clocks = <&hfclk_26m>; - clock-names = "fck"; - - twl_audio: audio { - compatible = "ti,twl4030-audio"; - codec { - }; - }; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - clock-frequency = <400000>; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_pins>; - clock-frequency = <400000>; - at24@50 { - compatible = "atmel,24c64"; - readonly; - reg = <0x50>; - }; -}; - -&omap3_pmx_core { - mcbsp2_pins: pinmux_mcbsp2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx */ - OMAP3_CORE1_IOPAD(0x213e, PIN_INPUT | MUX_MODE0) /* mcbsp2_clkx */ - OMAP3_CORE1_IOPAD(0x2140, PIN_INPUT | MUX_MODE0) /* mcbsp2_dr */ - OMAP3_CORE1_IOPAD(0x2142, PIN_OUTPUT | MUX_MODE0) /* mcbsp2_dx */ - >; - }; - uart2_pins: pinmux_uart2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT | MUX_MODE0) /* uart2_cts.uart2_cts */ - OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts .uart2_rts*/ - OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ - OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */ - OMAP3_CORE1_IOPAD(0x2198, PIN_OUTPUT | MUX_MODE4) /* GPIO_162,BT_EN */ - >; - }; - mcspi1_pins: pinmux_mcspi1_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */ - OMAP3_CORE1_IOPAD(0x21ca, PIN_OUTPUT | MUX_MODE0) /* mcspi1_simo.mcspi1_simo */ - OMAP3_CORE1_IOPAD(0x21cc, PIN_INPUT_PULLUP | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */ - OMAP3_CORE1_IOPAD(0x21ce, PIN_OUTPUT | MUX_MODE0) /* mcspi1_cs0.mcspi1_cs0 */ - >; - }; - hsusb_otg_pins: pinmux_hsusb_otg_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21a2, PIN_INPUT | MUX_MODE0) /* hsusb0_clk.hsusb0_clk */ - OMAP3_CORE1_IOPAD(0x21a4, PIN_OUTPUT | MUX_MODE0) /* hsusb0_stp.hsusb0_stp */ - OMAP3_CORE1_IOPAD(0x21a6, PIN_INPUT | MUX_MODE0) /* hsusb0_dir.hsusb0_dir */ - OMAP3_CORE1_IOPAD(0x21a8, PIN_INPUT | MUX_MODE0) /* hsusb0_nxt.hsusb0_nxt */ - - OMAP3_CORE1_IOPAD(0x21aa, PIN_INPUT | MUX_MODE0) /* hsusb0_data0.hsusb0_data0 */ - OMAP3_CORE1_IOPAD(0x21ac, PIN_INPUT | MUX_MODE0) /* hsusb0_data1.hsusb0_data1 */ - OMAP3_CORE1_IOPAD(0x21ae, PIN_INPUT | MUX_MODE0) /* hsusb0_data2.hsusb0_data2 */ - OMAP3_CORE1_IOPAD(0x21b0, PIN_INPUT | MUX_MODE0) /* hsusb0_data3.hsusb0_data3 */ - OMAP3_CORE1_IOPAD(0x21b2, PIN_INPUT | MUX_MODE0) /* hsusb0_data4.hsusb0_data4 */ - OMAP3_CORE1_IOPAD(0x21b4, PIN_INPUT | MUX_MODE0) /* hsusb0_data5.hsusb0_data5 */ - OMAP3_CORE1_IOPAD(0x21b6, PIN_INPUT | MUX_MODE0) /* hsusb0_data6.hsusb0_data6 */ - OMAP3_CORE1_IOPAD(0x21b8, PIN_INPUT | MUX_MODE0) /* hsusb0_data7.hsusb0_data7 */ - >; - }; - i2c1_pins: pinmux_i2c1_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */ - OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */ - >; - }; - i2c2_pins: pinmux_i2c2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT | MUX_MODE0) /* i2c2_scl */ - OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT | MUX_MODE0) /* i2c2_sda */ - >; - }; - i2c3_pins: pinmux_i2c3_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl */ - OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda */ - >; - }; -}; - -&uart2 { - interrupts-extended = <&intc 73 &omap3_pmx_core OMAP3_UART2_RX>; - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; -}; - -&mcspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&mcspi1_pins>; -}; - -#include "twl4030.dtsi" -#include "twl4030_omap3.dtsi" - -&twl { - twl_power: power { - compatible = "ti,twl4030-power-idle-osc-off", "ti,twl4030-power-idle"; - ti,use_poweroff; - }; -}; - -&twl_gpio { - ti,use-leds; -}; - -&twl_keypad { - status = "disabled"; -}; diff --git a/sys/gnu/dts/arm/lpc18xx.dtsi b/sys/gnu/dts/arm/lpc18xx.dtsi deleted file mode 100644 index 10b8249b8ab..00000000000 --- a/sys/gnu/dts/arm/lpc18xx.dtsi +++ /dev/null @@ -1,537 +0,0 @@ -/* - * Common base for NXP LPC18xx and LPC43xx devices. - * - * Copyright 2015 Joachim Eastwood - * - * This code is released using a dual license strategy: BSD/GPL - * You can choose the licence that better fits your requirements. - * - * Released under the terms of 3-clause BSD License - * Released under the terms of GNU General Public License Version 2.0 - * - */ - -#include "armv7-m.dtsi" - -#include "dt-bindings/clock/lpc18xx-cgu.h" -#include "dt-bindings/clock/lpc18xx-ccu.h" - -#define LPC_PIN(port, pin) (0x##port * 32 + pin) -#define LPC_GPIO(port, pin) (port * 32 + pin) - -/ { - #address-cells = <1>; - #size-cells = <1>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "arm,cortex-m3"; - device_type = "cpu"; - reg = <0x0>; - clocks = <&ccu1 CLK_CPU_CORE>; - }; - }; - - clocks { - xtal: xtal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <12000000>; - }; - - xtal32: xtal32 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - - enet_rx_clk: enet_rx_clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - clock-output-names = "enet_rx_clk"; - }; - - enet_tx_clk: enet_tx_clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - clock-output-names = "enet_tx_clk"; - }; - - gp_clkin: gp_clkin { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - clock-output-names = "gp_clkin"; - }; - }; - - soc { - sct_pwm: pwm@40000000 { - compatible = "nxp,lpc1850-sct-pwm"; - reg = <0x40000000 0x1000>; - clocks =<&ccu1 CLK_CPU_SCT>; - clock-names = "pwm"; - resets = <&rgu 37>; - #pwm-cells = <3>; - status = "disabled"; - }; - - dmac: dma-controller@40002000 { - compatible = "arm,pl080", "arm,primecell"; - arm,primecell-periphid = <0x00041080>; - reg = <0x40002000 0x1000>; - interrupts = <2>; - clocks = <&ccu1 CLK_CPU_DMA>; - clock-names = "apb_pclk"; - resets = <&rgu 19>; - #dma-cells = <2>; - dma-channels = <8>; - dma-requests = <16>; - lli-bus-interface-ahb1; - lli-bus-interface-ahb2; - mem-bus-interface-ahb1; - mem-bus-interface-ahb2; - memcpy-burst-size = <256>; - memcpy-bus-width = <32>; - }; - - spifi: flash-controller@40003000 { - compatible = "nxp,lpc1773-spifi"; - reg = <0x40003000 0x1000>, <0x14000000 0x4000000>; - reg-names = "spifi", "flash"; - interrupts = <30>; - clocks = <&ccu1 CLK_SPIFI>, <&ccu1 CLK_CPU_SPIFI>; - clock-names = "spifi", "reg"; - resets = <&rgu 53>; - status = "disabled"; - }; - - mmcsd: mmcsd@40004000 { - compatible = "snps,dw-mshc"; - reg = <0x40004000 0x1000>; - interrupts = <6>; - clocks = <&ccu2 CLK_SDIO>, <&ccu1 CLK_CPU_SDIO>; - clock-names = "ciu", "biu"; - resets = <&rgu 20>; - status = "disabled"; - }; - - usb0: ehci@40006100 { - compatible = "nxp,lpc1850-ehci", "generic-ehci"; - reg = <0x40006100 0x100>; - interrupts = <8>; - clocks = <&ccu1 CLK_CPU_USB0>; - resets = <&rgu 17>; - phys = <&usb0_otg_phy>; - phy-names = "usb"; - has-transaction-translator; - status = "disabled"; - }; - - usb1: ehci@40007100 { - compatible = "nxp,lpc1850-ehci", "generic-ehci"; - reg = <0x40007100 0x100>; - interrupts = <9>; - clocks = <&ccu1 CLK_CPU_USB1>; - resets = <&rgu 18>; - status = "disabled"; - }; - - emc: memory-controller@40005000 { - compatible = "arm,pl172", "arm,primecell"; - reg = <0x40005000 0x1000>; - clocks = <&ccu1 CLK_CPU_EMCDIV>, <&ccu1 CLK_CPU_EMC>; - clock-names = "mpmcclk", "apb_pclk"; - resets = <&rgu 21>; - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0x1c000000 0x1000000 - 1 0 0x1d000000 0x1000000 - 2 0 0x1e000000 0x1000000 - 3 0 0x1f000000 0x1000000>; - status = "disabled"; - }; - - lcdc: lcd-controller@40008000 { - compatible = "arm,pl111", "arm,primecell"; - reg = <0x40008000 0x1000>; - interrupts = <7>; - interrupt-names = "combined"; - clocks = <&cgu BASE_LCD_CLK>, <&ccu1 CLK_CPU_LCD>; - clock-names = "clcdclk", "apb_pclk"; - resets = <&rgu 16>; - status = "disabled"; - }; - - eeprom: eeprom@4000e000 { - compatible = "nxp,lpc1857-eeprom"; - reg = <0x4000e000 0x1000>, <0x20040000 0x4000>; - reg-names = "reg", "mem"; - clocks = <&ccu1 CLK_CPU_EEPROM>; - clock-names = "eeprom"; - resets = <&rgu 27>; - interrupts = <4>; - status = "disabled"; - }; - - mac: ethernet@40010000 { - compatible = "nxp,lpc1850-dwmac", "snps,dwmac-3.611", "snps,dwmac"; - reg = <0x40010000 0x2000>; - interrupts = <5>; - interrupt-names = "macirq"; - clocks = <&ccu1 CLK_CPU_ETHERNET>; - clock-names = "stmmaceth"; - resets = <&rgu 22>; - reset-names = "stmmaceth"; - rx-fifo-depth = <256>; - tx-fifo-depth = <256>; - snps,pbl = <4>; /* 32 (8x mode) */ - snps,force_thresh_dma_mode; - status = "disabled"; - }; - - creg: syscon@40043000 { - compatible = "nxp,lpc1850-creg", "syscon", "simple-mfd"; - reg = <0x40043000 0x1000>; - clocks = <&ccu1 CLK_CPU_CREG>; - resets = <&rgu 5>; - - creg_clk: clock-controller { - compatible = "nxp,lpc1850-creg-clk"; - clocks = <&xtal32>; - #clock-cells = <1>; - }; - - usb0_otg_phy: phy { - compatible = "nxp,lpc1850-usb-otg-phy"; - clocks = <&ccu1 CLK_USB0>; - #phy-cells = <0>; - }; - - dmamux: dma-mux { - compatible = "nxp,lpc1850-dmamux"; - #dma-cells = <3>; - dma-requests = <64>; - dma-masters = <&dmac>; - }; - }; - - rtc: rtc@40046000 { - compatible = "nxp,lpc1850-rtc", "nxp,lpc1788-rtc"; - reg = <0x40046000 0x1000>; - interrupts = <47>; - clocks = <&creg_clk 0>, <&ccu1 CLK_CPU_BUS>; - clock-names = "rtc", "reg"; - }; - - cgu: clock-controller@40050000 { - compatible = "nxp,lpc1850-cgu"; - reg = <0x40050000 0x1000>; - #clock-cells = <1>; - clocks = <&xtal>, <&creg_clk 1>, <&enet_rx_clk>, <&enet_tx_clk>, <&gp_clkin>; - }; - - ccu1: clock-controller@40051000 { - compatible = "nxp,lpc1850-ccu"; - reg = <0x40051000 0x1000>; - #clock-cells = <1>; - clocks = <&cgu BASE_APB3_CLK>, <&cgu BASE_APB1_CLK>, - <&cgu BASE_SPIFI_CLK>, <&cgu BASE_CPU_CLK>, - <&cgu BASE_PERIPH_CLK>, <&cgu BASE_USB0_CLK>, - <&cgu BASE_USB1_CLK>, <&cgu BASE_SPI_CLK>; - clock-names = "base_apb3_clk", "base_apb1_clk", - "base_spifi_clk", "base_cpu_clk", - "base_periph_clk", "base_usb0_clk", - "base_usb1_clk", "base_spi_clk"; - }; - - ccu2: clock-controller@40052000 { - compatible = "nxp,lpc1850-ccu"; - reg = <0x40052000 0x1000>; - #clock-cells = <1>; - clocks = <&cgu BASE_AUDIO_CLK>, <&cgu BASE_UART3_CLK>, - <&cgu BASE_UART2_CLK>, <&cgu BASE_UART1_CLK>, - <&cgu BASE_UART0_CLK>, <&cgu BASE_SSP1_CLK>, - <&cgu BASE_SSP0_CLK>, <&cgu BASE_SDIO_CLK>; - clock-names = "base_audio_clk", "base_uart3_clk", - "base_uart2_clk", "base_uart1_clk", - "base_uart0_clk", "base_ssp1_clk", - "base_ssp0_clk", "base_sdio_clk"; - }; - - rgu: reset-controller@40053000 { - compatible = "nxp,lpc1850-rgu"; - reg = <0x40053000 0x1000>; - clocks = <&cgu BASE_SAFE_CLK>, <&ccu1 CLK_CPU_BUS>; - clock-names = "delay", "reg"; - #reset-cells = <1>; - }; - - watchdog@40080000 { - compatible = "nxp,lpc1850-wwdt"; - reg = <0x40080000 0x24>; - interrupts = <49>; - clocks = <&cgu BASE_SAFE_CLK>, <&ccu1 CLK_CPU_WWDT>; - clock-names = "wdtclk", "reg"; - }; - - uart0: serial@40081000 { - compatible = "nxp,lpc1850-uart", "ns16550a"; - reg = <0x40081000 0x1000>; - reg-shift = <2>; - interrupts = <24>; - clocks = <&ccu2 CLK_APB0_UART0>, <&ccu1 CLK_CPU_UART0>; - clock-names = "uartclk", "reg"; - resets = <&rgu 44>; - dmas = <&dmamux 1 1 2 - &dmamux 2 1 2 - &dmamux 11 2 2 - &dmamux 12 2 2>; - dma-names = "tx", "rx", "tx", "rx"; - status = "disabled"; - }; - - uart1: serial@40082000 { - compatible = "nxp,lpc1850-uart", "ns16550a"; - reg = <0x40082000 0x1000>; - reg-shift = <2>; - interrupts = <25>; - clocks = <&ccu2 CLK_APB0_UART1>, <&ccu1 CLK_CPU_UART1>; - clock-names = "uartclk", "reg"; - resets = <&rgu 45>; - dmas = <&dmamux 3 1 2 - &dmamux 4 1 2>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - ssp0: spi@40083000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x40083000 0x1000>; - interrupts = <22>; - clocks = <&ccu2 CLK_APB0_SSP0>, <&ccu1 CLK_CPU_SSP0>; - clock-names = "sspclk", "apb_pclk"; - resets = <&rgu 50>; - dmas = <&dmamux 9 0 2 - &dmamux 10 0 2>; - dma-names = "rx", "tx"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - timer0: timer@40084000 { - compatible = "nxp,lpc3220-timer"; - reg = <0x40084000 0x1000>; - interrupts = <12>; - clocks = <&ccu1 CLK_CPU_TIMER0>; - clock-names = "timerclk"; - resets = <&rgu 32>; - }; - - timer1: timer@40085000 { - compatible = "nxp,lpc3220-timer"; - reg = <0x40085000 0x1000>; - interrupts = <13>; - clocks = <&ccu1 CLK_CPU_TIMER1>; - clock-names = "timerclk"; - resets = <&rgu 33>; - }; - - pinctrl: pinctrl@40086000 { - compatible = "nxp,lpc1850-scu"; - reg = <0x40086000 0x1000>; - clocks = <&ccu1 CLK_CPU_SCU>; - }; - - i2c0: i2c@400a1000 { - compatible = "nxp,lpc1788-i2c"; - reg = <0x400a1000 0x1000>; - interrupts = <18>; - clocks = <&ccu1 CLK_APB1_I2C0>; - resets = <&rgu 48>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - can1: can@400a4000 { - compatible = "bosch,c_can"; - reg = <0x400a4000 0x1000>; - interrupts = <43>; - clocks = <&ccu1 CLK_APB1_CAN1>; - resets = <&rgu 54>; - status = "disabled"; - }; - - uart2: serial@400c1000 { - compatible = "nxp,lpc1850-uart", "ns16550a"; - reg = <0x400c1000 0x1000>; - reg-shift = <2>; - interrupts = <26>; - clocks = <&ccu2 CLK_APB2_UART2>, <&ccu1 CLK_CPU_UART2>; - clock-names = "uartclk", "reg"; - resets = <&rgu 46>; - dmas = <&dmamux 5 1 2 - &dmamux 6 1 2>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - uart3: serial@400c2000 { - compatible = "nxp,lpc1850-uart", "ns16550a"; - reg = <0x400c2000 0x1000>; - reg-shift = <2>; - interrupts = <27>; - clocks = <&ccu2 CLK_APB2_UART3>, <&ccu1 CLK_CPU_UART3>; - clock-names = "uartclk", "reg"; - resets = <&rgu 47>; - dmas = <&dmamux 7 1 2 - &dmamux 8 1 2 - &dmamux 13 3 2 - &dmamux 14 3 2>; - dma-names = "tx", "rx", "rx", "tx"; - status = "disabled"; - }; - - timer2: timer@400c3000 { - compatible = "nxp,lpc3220-timer"; - reg = <0x400c3000 0x1000>; - interrupts = <14>; - clocks = <&ccu1 CLK_CPU_TIMER2>; - clock-names = "timerclk"; - resets = <&rgu 34>; - }; - - timer3: timer@400c4000 { - compatible = "nxp,lpc3220-timer"; - reg = <0x400c4000 0x1000>; - interrupts = <15>; - clocks = <&ccu1 CLK_CPU_TIMER3>; - clock-names = "timerclk"; - resets = <&rgu 35>; - }; - - ssp1: spi@400c5000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x400c5000 0x1000>; - interrupts = <23>; - clocks = <&ccu2 CLK_APB2_SSP1>, <&ccu1 CLK_CPU_SSP1>; - clock-names = "sspclk", "apb_pclk"; - resets = <&rgu 51>; - dmas = <&dmamux 11 2 2 - &dmamux 12 2 2 - &dmamux 3 3 2 - &dmamux 4 3 2 - &dmamux 5 2 2 - &dmamux 6 2 2 - &dmamux 13 2 2 - &dmamux 14 2 2>; - dma-names = "rx", "tx", "tx", "rx", - "tx", "rx", "rx", "tx"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c1: i2c@400e0000 { - compatible = "nxp,lpc1788-i2c"; - reg = <0x400e0000 0x1000>; - interrupts = <19>; - clocks = <&ccu1 CLK_APB3_I2C1>; - resets = <&rgu 49>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - dac: dac@400e1000 { - compatible = "nxp,lpc1850-dac"; - reg = <0x400e1000 0x1000>; - interrupts = <0>; - clocks = <&ccu1 CLK_APB3_DAC>; - resets = <&rgu 42>; - status = "disabled"; - }; - - can0: can@400e2000 { - compatible = "bosch,c_can"; - reg = <0x400e2000 0x1000>; - interrupts = <51>; - clocks = <&ccu1 CLK_APB3_CAN0>; - resets = <&rgu 55>; - status = "disabled"; - }; - - adc0: adc@400e3000 { - compatible = "nxp,lpc1850-adc"; - reg = <0x400e3000 0x1000>; - interrupts = <17>; - clocks = <&ccu1 CLK_APB3_ADC0>; - resets = <&rgu 40>; - status = "disabled"; - }; - - adc1: adc@400e4000 { - compatible = "nxp,lpc1850-adc"; - reg = <0x400e4000 0x1000>; - interrupts = <21>; - clocks = <&ccu1 CLK_APB3_ADC1>; - resets = <&rgu 41>; - status = "disabled"; - }; - - gpio: gpio@400f4000 { - compatible = "nxp,lpc1850-gpio"; - reg = <0x400f4000 0x4000>; - clocks = <&ccu1 CLK_CPU_GPIO>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl LPC_GPIO(0,0) LPC_PIN(0,0) 2>, - <&pinctrl LPC_GPIO(0,4) LPC_PIN(1,0) 1>, - <&pinctrl LPC_GPIO(0,8) LPC_PIN(1,1) 4>, - <&pinctrl LPC_GPIO(1,8) LPC_PIN(1,5) 2>, - <&pinctrl LPC_GPIO(1,0) LPC_PIN(1,7) 8>, - <&pinctrl LPC_GPIO(0,2) LPC_PIN(1,15) 2>, - <&pinctrl LPC_GPIO(0,12) LPC_PIN(1,17) 2>, - <&pinctrl LPC_GPIO(0,15) LPC_PIN(1,20) 1>, - <&pinctrl LPC_GPIO(5,0) LPC_PIN(2,0) 7>, - <&pinctrl LPC_GPIO(0,7) LPC_PIN(2,7) 1>, - <&pinctrl LPC_GPIO(5,7) LPC_PIN(2,8) 1>, - <&pinctrl LPC_GPIO(1,10) LPC_PIN(2,9) 1>, - <&pinctrl LPC_GPIO(0,14) LPC_PIN(2,10) 1>, - <&pinctrl LPC_GPIO(1,11) LPC_PIN(2,11) 3>, - <&pinctrl LPC_GPIO(5,8) LPC_PIN(3,1) 2>, - <&pinctrl LPC_GPIO(1,14) LPC_PIN(3,4) 2>, - <&pinctrl LPC_GPIO(0,6) LPC_PIN(3,6) 1>, - <&pinctrl LPC_GPIO(5,10) LPC_PIN(3,7) 2>, - <&pinctrl LPC_GPIO(2,0) LPC_PIN(4,0) 7>, - <&pinctrl LPC_GPIO(5,12) LPC_PIN(4,8) 3>, - <&pinctrl LPC_GPIO(2,9) LPC_PIN(5,0) 7>, - <&pinctrl LPC_GPIO(2,7) LPC_PIN(5,7) 1>, - <&pinctrl LPC_GPIO(3,0) LPC_PIN(6,1) 5>, - <&pinctrl LPC_GPIO(0,5) LPC_PIN(6,6) 1>, - <&pinctrl LPC_GPIO(5,15) LPC_PIN(6,7) 2>, - <&pinctrl LPC_GPIO(3,5) LPC_PIN(6,9) 3>, - <&pinctrl LPC_GPIO(2,8) LPC_PIN(6,12) 1>, - <&pinctrl LPC_GPIO(3,8) LPC_PIN(7,0) 8>, - <&pinctrl LPC_GPIO(4,0) LPC_PIN(8,0) 8>, - <&pinctrl LPC_GPIO(4,12) LPC_PIN(9,0) 4>, - <&pinctrl LPC_GPIO(5,17) LPC_PIN(9,4) 2>, - <&pinctrl LPC_GPIO(4,11) LPC_PIN(9,6) 1>, - <&pinctrl LPC_GPIO(4,8) LPC_PIN(a,1) 3>, - <&pinctrl LPC_GPIO(5,19) LPC_PIN(a,4) 1>, - <&pinctrl LPC_GPIO(5,20) LPC_PIN(b,0) 7>, - <&pinctrl LPC_GPIO(6,0) LPC_PIN(c,1) 14>, - <&pinctrl LPC_GPIO(6,14) LPC_PIN(d,0) 17>, - <&pinctrl LPC_GPIO(7,0) LPC_PIN(e,0) 16>, - <&pinctrl LPC_GPIO(7,16) LPC_PIN(f,1) 3>, - <&pinctrl LPC_GPIO(7,19) LPC_PIN(f,5) 7>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/lpc3250-ea3250.dts b/sys/gnu/dts/arm/lpc3250-ea3250.dts deleted file mode 100644 index 63c6f17bb7c..00000000000 --- a/sys/gnu/dts/arm/lpc3250-ea3250.dts +++ /dev/null @@ -1,273 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Embedded Artists LPC3250 board - * - * Copyright 2012 Roland Stigge - */ - -/dts-v1/; -#include "lpc32xx.dtsi" - -/ { - model = "Embedded Artists LPC3250 board based on NXP LPC3250"; - compatible = "ea,ea3250", "nxp,lpc3250"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x4000000>; - }; - - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - - button { - label = "Interrupt Key"; - linux,code = <103>; - gpios = <&gpio 4 1 0>; /* GPI_P3 1 */ - }; - - key1 { - label = "KEY1"; - linux,code = <1>; - gpios = <&pca9532 0 0>; - }; - - key2 { - label = "KEY2"; - linux,code = <2>; - gpios = <&pca9532 1 0>; - }; - - key3 { - label = "KEY3"; - linux,code = <3>; - gpios = <&pca9532 2 0>; - }; - - key4 { - label = "KEY4"; - linux,code = <4>; - gpios = <&pca9532 3 0>; - }; - - joy0 { - label = "Joystick Key 0"; - linux,code = <10>; - gpios = <&gpio 2 0 0>; /* P2.0 */ - }; - - joy1 { - label = "Joystick Key 1"; - linux,code = <11>; - gpios = <&gpio 2 1 0>; /* P2.1 */ - }; - - joy2 { - label = "Joystick Key 2"; - linux,code = <12>; - gpios = <&gpio 2 2 0>; /* P2.2 */ - }; - - joy3 { - label = "Joystick Key 3"; - linux,code = <13>; - gpios = <&gpio 2 3 0>; /* P2.3 */ - }; - - joy4 { - label = "Joystick Key 4"; - linux,code = <14>; - gpios = <&gpio 2 4 0>; /* P2.4 */ - }; - }; - - leds { - compatible = "gpio-leds"; - - /* LEDs on OEM Board */ - - led1 { - gpios = <&gpio 5 14 1>; /* GPO_P3 14, GPIO 93, active low */ - linux,default-trigger = "timer"; - default-state = "off"; - }; - - led2 { - gpios = <&gpio 2 10 1>; /* P2.10, active low */ - default-state = "off"; - }; - - led3 { - gpios = <&gpio 2 11 1>; /* P2.11, active low */ - default-state = "off"; - }; - - led4 { - gpios = <&gpio 2 12 1>; /* P2.12, active low */ - default-state = "off"; - }; - - /* LEDs on Base Board */ - - lede1 { - gpios = <&pca9532 8 0>; - default-state = "off"; - }; - lede2 { - gpios = <&pca9532 9 0>; - default-state = "off"; - }; - lede3 { - gpios = <&pca9532 10 0>; - default-state = "off"; - }; - lede4 { - gpios = <&pca9532 11 0>; - default-state = "off"; - }; - lede5 { - gpios = <&pca9532 12 0>; - default-state = "off"; - }; - lede6 { - gpios = <&pca9532 13 0>; - default-state = "off"; - }; - lede7 { - gpios = <&pca9532 14 0>; - default-state = "off"; - }; - lede8 { - gpios = <&pca9532 15 0>; - default-state = "off"; - }; - }; -}; - -/* 3-axis accelerometer X,Y,Z (or AD-IN instead of Z) */ -&adc { - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - - uda1380: uda1380@18 { - compatible = "nxp,uda1380"; - reg = <0x18>; - power-gpio = <&gpio 3 10 0>; - reset-gpio = <&gpio 3 2 0>; - dac-clk = "wspll"; - }; - - eeprom@50 { - compatible = "atmel,24c256"; - reg = <0x50>; - }; - - eeprom@57 { - compatible = "atmel,24c64"; - reg = <0x57>; - }; - - pca9532: pca9532@60 { - compatible = "nxp,pca9532"; - gpio-controller; - #gpio-cells = <2>; - reg = <0x60>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; -}; - -&i2cusb { - clock-frequency = <100000>; - - isp1301: usb-transceiver@2d { - compatible = "nxp,isp1301"; - reg = <0x2d>; - }; -}; - -&mac { - phy-mode = "rmii"; - use-iram; - status = "okay"; -}; - -/* Here, choose exactly one from: ohci, usbd */ -&ohci /* &usbd */ { - transceiver = <&isp1301>; - status = "okay"; -}; - -&sd { - wp-gpios = <&pca9532 5 0>; - cd-gpios = <&pca9532 4 0>; - cd-inverted; - bus-width = <4>; - status = "okay"; -}; - -/* 128MB Flash via SLC NAND controller */ -&slc { - status = "okay"; - - nxp,wdr-clks = <14>; - nxp,wwidth = <260000000>; - nxp,whold = <104000000>; - nxp,wsetup = <200000000>; - nxp,rdr-clks = <14>; - nxp,rwidth = <34666666>; - nxp,rhold = <104000000>; - nxp,rsetup = <200000000>; - nand-on-flash-bbt; - gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */ - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - mtd0@0 { - label = "ea3250-boot"; - reg = <0x00000000 0x00080000>; - read-only; - }; - - mtd1@80000 { - label = "ea3250-uboot"; - reg = <0x00080000 0x000c0000>; - read-only; - }; - - mtd2@140000 { - label = "ea3250-kernel"; - reg = <0x00140000 0x00400000>; - }; - - mtd3@540000 { - label = "ea3250-rootfs"; - reg = <0x00540000 0x07ac0000>; - }; - }; -}; - -&uart1 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&uart5 { - status = "okay"; -}; - -&uart6 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/lpc3250-phy3250.dts b/sys/gnu/dts/arm/lpc3250-phy3250.dts deleted file mode 100644 index 21a6d0bca1e..00000000000 --- a/sys/gnu/dts/arm/lpc3250-phy3250.dts +++ /dev/null @@ -1,236 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * PHYTEC phyCORE-LPC3250 board - * - * Copyright (C) 2015-2019 Vladimir Zapolskiy - * Copyright 2012 Roland Stigge - */ - -/dts-v1/; -#include "lpc32xx.dtsi" - -/ { - model = "PHYTEC phyCORE-LPC3250 board based on NXP LPC3250"; - compatible = "phytec,phy3250", "nxp,lpc3250"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x4000000>; - }; - - leds { - compatible = "gpio-leds"; - - led0 { /* red */ - gpios = <&gpio 5 1 0>; /* GPO_P3 1, GPIO 80, active high */ - default-state = "off"; - }; - - led1 { /* green */ - gpios = <&gpio 5 14 0>; /* GPO_P3 14, GPIO 93, active high */ - linux,default-trigger = "heartbeat"; - }; - }; - - panel: panel { - compatible = "sharp,lq035q7db03"; - power-supply = <®_lcd>; - - port { - panel_input: endpoint { - remote-endpoint = <&cldc_output>; - }; - }; - }; - - reg_backlight: regulator-backlight { - compatible = "regulator-fixed"; - regulator-name = "backlight"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio 5 4 0>; - enable-active-high; - regulator-boot-on; - }; - - reg_lcd: regulator-lcd { - compatible = "regulator-fixed"; - regulator-name = "lcd"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio 5 0 0>; - enable-active-high; - regulator-boot-on; - }; - - reg_sd: regulator-sd { - compatible = "regulator-fixed"; - regulator-name = "sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio 5 5 0>; - enable-active-high; - regulator-boot-on; - }; -}; - -&clcd { - max-memory-bandwidth = <18710000>; - status = "okay"; - - port { - cldc_output: endpoint { - remote-endpoint = <&panel_input>; - arm,pl11x,tft-r0g0b0-pads = <0 8 16>; - }; - }; -}; - -&i2c1 { - clock-frequency = <100000>; - - uda1380: uda1380@18 { - compatible = "nxp,uda1380"; - reg = <0x18>; - power-gpio = <&gpio 3 10 0>; - reset-gpio = <&gpio 3 2 0>; - dac-clk = "wspll"; - }; - - pcf8563: rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; -}; - -&i2cusb { - clock-frequency = <100000>; - - isp1301: usb-transceiver@2c { - compatible = "nxp,isp1301"; - reg = <0x2c>; - }; -}; - -&key { - keypad,num-rows = <1>; - keypad,num-columns = <1>; - nxp,debounce-delay-ms = <3>; - nxp,scan-delay-ms = <34>; - linux,keymap = <0x00000002>; - status = "okay"; -}; - -&mac { - phy-mode = "rmii"; - use-iram; - status = "okay"; -}; - -/* Here, choose exactly one from: ohci, usbd */ -&ohci /* &usbd */ { - transceiver = <&isp1301>; - status = "okay"; -}; - -&sd { - wp-gpios = <&gpio 3 0 0>; - cd-gpios = <&gpio 3 1 0>; - cd-inverted; - bus-width = <4>; - vmmc-supply = <®_sd>; - status = "okay"; -}; - -/* 64MB Flash via SLC NAND controller */ -&slc { - status = "okay"; - - nxp,wdr-clks = <14>; - nxp,wwidth = <40000000>; - nxp,whold = <100000000>; - nxp,wsetup = <100000000>; - nxp,rdr-clks = <14>; - nxp,rwidth = <40000000>; - nxp,rhold = <66666666>; - nxp,rsetup = <100000000>; - nand-on-flash-bbt; - gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */ - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - mtd0@0 { - label = "phy3250-boot"; - reg = <0x00000000 0x00064000>; - read-only; - }; - - mtd1@64000 { - label = "phy3250-uboot"; - reg = <0x00064000 0x00190000>; - read-only; - }; - - mtd2@1f4000 { - label = "phy3250-ubt-prms"; - reg = <0x001f4000 0x00010000>; - }; - - mtd3@204000 { - label = "phy3250-kernel"; - reg = <0x00204000 0x00400000>; - }; - - mtd4@604000 { - label = "phy3250-rootfs"; - reg = <0x00604000 0x039fc000>; - }; - }; -}; - -&ssp0 { - num-cs = <1>; - cs-gpios = <&gpio 3 5 0>; - status = "okay"; - - eeprom: at25@0 { - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <5000000>; - - pl022,interface = <0>; - pl022,com-mode = <0>; - pl022,rx-level-trig = <1>; - pl022,tx-level-trig = <1>; - pl022,ctrl-len = <11>; - pl022,wait-state = <0>; - pl022,duplex = <0>; - - at25,byte-len = <0x8000>; - at25,addr-mode = <2>; - at25,page-size = <64>; - }; -}; - -&tsc { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&uart5 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/lpc32xx.dtsi b/sys/gnu/dts/arm/lpc32xx.dtsi deleted file mode 100644 index 7b7ec7b1217..00000000000 --- a/sys/gnu/dts/arm/lpc32xx.dtsi +++ /dev/null @@ -1,514 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * NXP LPC32xx SoC - * - * Copyright (C) 2015-2019 Vladimir Zapolskiy - * Copyright 2012 Roland Stigge - */ - -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - compatible = "nxp,lpc3220"; - interrupt-parent = <&mic>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "arm,arm926ej-s"; - device_type = "cpu"; - reg = <0x0>; - }; - }; - - clocks { - xtal_32k: xtal_32k { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "xtal_32k"; - }; - - xtal: xtal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <13000000>; - clock-output-names = "xtal"; - }; - }; - - ahb { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0x00000000 0x00000000 0x10000000>, - <0x20000000 0x20000000 0x30000000>, - <0xe0000000 0xe0000000 0x04000000>; - - iram: sram@8000000 { - compatible = "mmio-sram"; - reg = <0x08000000 0x20000>; - - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x08000000 0x20000>; - }; - - /* - * Enable either SLC or MLC - */ - slc: flash@20020000 { - compatible = "nxp,lpc3220-slc"; - reg = <0x20020000 0x1000>; - clocks = <&clk LPC32XX_CLK_SLC>; - status = "disabled"; - }; - - mlc: flash@200a8000 { - compatible = "nxp,lpc3220-mlc"; - reg = <0x200a8000 0x11000>; - interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk LPC32XX_CLK_MLC>; - status = "disabled"; - }; - - dma: dma@31000000 { - compatible = "arm,pl080", "arm,primecell"; - reg = <0x31000000 0x1000>; - interrupts = <28 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk LPC32XX_CLK_DMA>; - clock-names = "apb_pclk"; - }; - - usb { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0x0 0x31020000 0x00001000>; - - /* - * Enable either ohci or usbd (gadget)! - */ - ohci: ohci@0 { - compatible = "nxp,ohci-nxp", "usb-ohci"; - reg = <0x0 0x300>; - interrupt-parent = <&sic1>; - interrupts = <27 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&usbclk LPC32XX_USB_CLK_HOST>; - status = "disabled"; - }; - - usbd: usbd@0 { - compatible = "nxp,lpc3220-udc"; - reg = <0x0 0x300>; - interrupt-parent = <&sic1>; - interrupts = <29 IRQ_TYPE_LEVEL_HIGH>, - <30 IRQ_TYPE_LEVEL_HIGH>, - <28 IRQ_TYPE_LEVEL_HIGH>, - <26 IRQ_TYPE_LEVEL_LOW>; - clocks = <&usbclk LPC32XX_USB_CLK_DEVICE>; - status = "disabled"; - }; - - i2cusb: i2c@300 { - compatible = "nxp,pnx-i2c"; - reg = <0x300 0x100>; - interrupt-parent = <&sic1>; - interrupts = <31 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&usbclk LPC32XX_USB_CLK_I2C>; - #address-cells = <1>; - #size-cells = <0>; - pnx,timeout = <0x64>; - }; - - usbclk: clock-controller@f00 { - compatible = "nxp,lpc3220-usb-clk"; - reg = <0xf00 0x100>; - #clock-cells = <1>; - }; - }; - - clcd: clcd@31040000 { - compatible = "arm,pl111", "arm,primecell"; - reg = <0x31040000 0x1000>; - interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk LPC32XX_CLK_LCD>, <&clk LPC32XX_CLK_LCD>; - clock-names = "clcdclk", "apb_pclk"; - status = "disabled"; - }; - - mac: ethernet@31060000 { - compatible = "nxp,lpc-eth"; - reg = <0x31060000 0x1000>; - interrupts = <29 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk LPC32XX_CLK_MAC>; - status = "disabled"; - }; - - emc: memory-controller@31080000 { - compatible = "arm,pl175", "arm,primecell"; - reg = <0x31080000 0x1000>; - clocks = <&clk LPC32XX_CLK_DDRAM>, <&clk LPC32XX_CLK_DDRAM>; - clock-names = "mpmcclk", "apb_pclk"; - #address-cells = <1>; - #size-cells = <1>; - - ranges = <0 0xe0000000 0x01000000>, - <1 0xe1000000 0x01000000>, - <2 0xe2000000 0x01000000>, - <3 0xe3000000 0x01000000>; - status = "disabled"; - }; - - apb { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0x20000000 0x20000000 0x30000000>; - - /* - * ssp0 and spi1 are shared pins; - * enable one in your board dts, as needed. - */ - ssp0: spi@20084000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x20084000 0x1000>; - interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk LPC32XX_CLK_SSP0>; - clock-names = "apb_pclk"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi1: spi@20088000 { - compatible = "nxp,lpc3220-spi"; - reg = <0x20088000 0x1000>; - clocks = <&clk LPC32XX_CLK_SPI1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - /* - * ssp1 and spi2 are shared pins; - * enable one in your board dts, as needed. - */ - ssp1: spi@2008c000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x2008c000 0x1000>; - interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk LPC32XX_CLK_SSP1>; - clock-names = "apb_pclk"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi2: spi@20090000 { - compatible = "nxp,lpc3220-spi"; - reg = <0x20090000 0x1000>; - clocks = <&clk LPC32XX_CLK_SPI2>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2s0: i2s@20094000 { - compatible = "nxp,lpc3220-i2s"; - reg = <0x20094000 0x1000>; - status = "disabled"; - }; - - sd: sd@20098000 { - compatible = "arm,pl18x", "arm,primecell"; - reg = <0x20098000 0x1000>; - interrupts = <15 IRQ_TYPE_LEVEL_HIGH>, - <13 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk LPC32XX_CLK_SD>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - i2s1: i2s@2009c000 { - compatible = "nxp,lpc3220-i2s"; - reg = <0x2009c000 0x1000>; - status = "disabled"; - }; - - /* UART5 first since it is the default console, ttyS0 */ - uart5: serial@40090000 { - /* actually, ns16550a w/ 64 byte fifos! */ - compatible = "nxp,lpc3220-uart"; - reg = <0x40090000 0x1000>; - interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - clocks = <&clk LPC32XX_CLK_UART5>; - status = "disabled"; - }; - - uart3: serial@40080000 { - compatible = "nxp,lpc3220-uart"; - reg = <0x40080000 0x1000>; - interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - clocks = <&clk LPC32XX_CLK_UART3>; - status = "disabled"; - }; - - uart4: serial@40088000 { - compatible = "nxp,lpc3220-uart"; - reg = <0x40088000 0x1000>; - interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - clocks = <&clk LPC32XX_CLK_UART4>; - status = "disabled"; - }; - - uart6: serial@40098000 { - compatible = "nxp,lpc3220-uart"; - reg = <0x40098000 0x1000>; - interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - clocks = <&clk LPC32XX_CLK_UART6>; - status = "disabled"; - }; - - i2c1: i2c@400a0000 { - compatible = "nxp,pnx-i2c"; - reg = <0x400a0000 0x100>; - interrupt-parent = <&sic1>; - interrupts = <19 IRQ_TYPE_LEVEL_LOW>; - #address-cells = <1>; - #size-cells = <0>; - pnx,timeout = <0x64>; - clocks = <&clk LPC32XX_CLK_I2C1>; - }; - - i2c2: i2c@400a8000 { - compatible = "nxp,pnx-i2c"; - reg = <0x400a8000 0x100>; - interrupt-parent = <&sic1>; - interrupts = <18 IRQ_TYPE_LEVEL_LOW>; - #address-cells = <1>; - #size-cells = <0>; - pnx,timeout = <0x64>; - clocks = <&clk LPC32XX_CLK_I2C2>; - }; - - mpwm: mpwm@400e8000 { - compatible = "nxp,lpc3220-motor-pwm"; - reg = <0x400e8000 0x78>; - status = "disabled"; - #pwm-cells = <2>; - }; - }; - - fab { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0x20000000 0x20000000 0x30000000>; - - /* System Control Block */ - scb { - compatible = "simple-bus"; - ranges = <0x0 0x040004000 0x00001000>; - #address-cells = <1>; - #size-cells = <1>; - - clk: clock-controller@0 { - compatible = "nxp,lpc3220-clk"; - reg = <0x00 0x114>; - #clock-cells = <1>; - - clocks = <&xtal_32k>, <&xtal>; - clock-names = "xtal_32k", "xtal"; - - assigned-clocks = <&clk LPC32XX_CLK_HCLK_PLL>; - assigned-clock-rates = <208000000>; - }; - }; - - mic: interrupt-controller@40008000 { - compatible = "nxp,lpc3220-mic"; - reg = <0x40008000 0x4000>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - sic1: interrupt-controller@4000c000 { - compatible = "nxp,lpc3220-sic"; - reg = <0x4000c000 0x4000>; - interrupt-controller; - #interrupt-cells = <2>; - - interrupt-parent = <&mic>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>, - <30 IRQ_TYPE_LEVEL_LOW>; - }; - - sic2: interrupt-controller@40010000 { - compatible = "nxp,lpc3220-sic"; - reg = <0x40010000 0x4000>; - interrupt-controller; - #interrupt-cells = <2>; - - interrupt-parent = <&mic>; - interrupts = <1 IRQ_TYPE_LEVEL_LOW>, - <31 IRQ_TYPE_LEVEL_LOW>; - }; - - uart1: serial@40014000 { - compatible = "nxp,lpc3220-hsuart"; - reg = <0x40014000 0x1000>; - interrupts = <26 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - uart2: serial@40018000 { - compatible = "nxp,lpc3220-hsuart"; - reg = <0x40018000 0x1000>; - interrupts = <25 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - uart7: serial@4001c000 { - compatible = "nxp,lpc3220-hsuart"; - reg = <0x4001c000 0x1000>; - interrupts = <24 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - rtc: rtc@40024000 { - compatible = "nxp,lpc3220-rtc"; - reg = <0x40024000 0x1000>; - interrupt-parent = <&sic1>; - interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk LPC32XX_CLK_RTC>; - }; - - gpio: gpio@40028000 { - compatible = "nxp,lpc3220-gpio"; - reg = <0x40028000 0x1000>; - gpio-controller; - #gpio-cells = <3>; /* bank, pin, flags */ - }; - - timer4: timer@4002c000 { - compatible = "nxp,lpc3220-timer"; - reg = <0x4002c000 0x1000>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - clocks = <&clk LPC32XX_CLK_TIMER4>; - clock-names = "timerclk"; - status = "disabled"; - }; - - timer5: timer@40030000 { - compatible = "nxp,lpc3220-timer"; - reg = <0x40030000 0x1000>; - interrupts = <4 IRQ_TYPE_LEVEL_LOW>; - clocks = <&clk LPC32XX_CLK_TIMER5>; - clock-names = "timerclk"; - status = "disabled"; - }; - - watchdog: watchdog@4003c000 { - compatible = "nxp,pnx4008-wdt"; - reg = <0x4003c000 0x1000>; - clocks = <&clk LPC32XX_CLK_WDOG>; - }; - - timer0: timer@40044000 { - compatible = "nxp,lpc3220-timer"; - reg = <0x40044000 0x1000>; - clocks = <&clk LPC32XX_CLK_TIMER0>; - clock-names = "timerclk"; - interrupts = <16 IRQ_TYPE_LEVEL_LOW>; - }; - - /* - * TSC vs. ADC: Since those two share the same - * hardware, you need to choose from one of the - * following two and do 'status = "okay";' for one of - * them - */ - - adc: adc@40048000 { - compatible = "nxp,lpc3220-adc"; - reg = <0x40048000 0x1000>; - interrupt-parent = <&sic1>; - interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk LPC32XX_CLK_ADC>; - status = "disabled"; - }; - - tsc: tsc@40048000 { - compatible = "nxp,lpc3220-tsc"; - reg = <0x40048000 0x1000>; - interrupt-parent = <&sic1>; - interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk LPC32XX_CLK_ADC>; - status = "disabled"; - }; - - timer1: timer@4004c000 { - compatible = "nxp,lpc3220-timer"; - reg = <0x4004c000 0x1000>; - interrupts = <17 IRQ_TYPE_LEVEL_LOW>; - clocks = <&clk LPC32XX_CLK_TIMER1>; - clock-names = "timerclk"; - }; - - key: key@40050000 { - compatible = "nxp,lpc3220-key"; - reg = <0x40050000 0x1000>; - clocks = <&clk LPC32XX_CLK_KEY>; - interrupt-parent = <&sic1>; - interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - timer2: timer@40058000 { - compatible = "nxp,lpc3220-timer"; - reg = <0x40058000 0x1000>; - interrupts = <18 IRQ_TYPE_LEVEL_LOW>; - clocks = <&clk LPC32XX_CLK_TIMER2>; - clock-names = "timerclk"; - status = "disabled"; - }; - - pwm1: pwm@4005c000 { - compatible = "nxp,lpc3220-pwm"; - reg = <0x4005c000 0x4>; - clocks = <&clk LPC32XX_CLK_PWM1>; - assigned-clocks = <&clk LPC32XX_CLK_PWM1>; - assigned-clock-parents = <&clk LPC32XX_CLK_PERIPH>; - status = "disabled"; - }; - - pwm2: pwm@4005c004 { - compatible = "nxp,lpc3220-pwm"; - reg = <0x4005c004 0x4>; - clocks = <&clk LPC32XX_CLK_PWM2>; - assigned-clocks = <&clk LPC32XX_CLK_PWM2>; - assigned-clock-parents = <&clk LPC32XX_CLK_PERIPH>; - status = "disabled"; - }; - - timer3: timer@40060000 { - compatible = "nxp,lpc3220-timer"; - reg = <0x40060000 0x1000>; - interrupts = <19 IRQ_TYPE_LEVEL_LOW>; - clocks = <&clk LPC32XX_CLK_TIMER3>; - clock-names = "timerclk"; - status = "disabled"; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/lpc4337-ciaa.dts b/sys/gnu/dts/arm/lpc4337-ciaa.dts deleted file mode 100644 index beddaba8539..00000000000 --- a/sys/gnu/dts/arm/lpc4337-ciaa.dts +++ /dev/null @@ -1,221 +0,0 @@ -/* - * CIAA NXP LPC4337 (http://www.proyecto-ciaa.com.ar) - * - * Copyright (C) 2015 VanguardiaSur - www.vanguardiasur.com.ar - * - * This code is released using a dual license strategy: BSD/GPL - * You can choose the licence that better fits your requirements. - * - * Released under the terms of 3-clause BSD License - * Released under the terms of GNU General Public License Version 2.0 - */ -/dts-v1/; - -#include "lpc18xx.dtsi" -#include "lpc4357.dtsi" - -#include "dt-bindings/gpio/gpio.h" - -/ { - model = "CIAA NXP LPC4337"; - compatible = "ciaa,lpc4337", "nxp,lpc4337", "nxp,lpc4350"; - - aliases { - serial0 = &uart2; - serial1 = &uart3; - }; - - chosen { - bootargs = "console=ttyS0,115200 earlyprintk"; - stdout-path = &uart2; - }; - - memory@28000000 { - device_type = "memory"; - reg = <0x28000000 0x0800000>; /* 8 MB */ - }; -}; - -&pinctrl { - enet_rmii_pins: enet-rmii-pins { - enet_rmii_rxd_cfg { - pins = "p1_15", "p0_0"; - function = "enet"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - enet_rmii_txd_cfg { - pins = "p1_18", "p1_20"; - function = "enet"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - enet_rmii_rx_dv_cfg { - pins = "p1_16"; - function = "enet"; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - enet_rmii_tx_en_cfg { - pins = "p0_1"; - function = "enet"; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - enet_ref_clk_cfg { - pins = "p1_19"; - function = "enet"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - enet_mdio_cfg { - pins = "p1_17"; - function = "enet"; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - enet_mdc_cfg { - pins = "p7_7"; - function = "enet"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - }; - - i2c0_pins: i2c0-pins { - i2c0_pins_cfg { - pins = "i2c0_scl", "i2c0_sda"; - function = "i2c0"; - input-enable; - }; - }; - - ssp_pins: ssp-pins { - ssp1_cs { - pins = "p6_7"; - function = "gpio"; - bias-pull-up; - bias-disable; - }; - - ssp1_miso_mosi { - pins = "p1_3", "p1_4"; - function = "ssp1"; - slew-rate = <1>; - bias-pull-down; - input-enable; - input-schmitt-disable; - }; - - ssp1_sck { - pins = "pf_4"; - function = "ssp1"; - slew-rate = <1>; - bias-disable; - }; - }; - - uart2_pins: uart2-pins { - uart2_rx_cfg { - pins = "p7_2"; - function = "uart2"; - bias-disable; - input-enable; - }; - - uart2_tx_cfg { - pins = "p7_1"; - function = "uart2"; - bias-disable; - }; - }; - - uart3_pins: uart3-pins { - uart3_rx_cfg { - pins = "p2_4"; - function = "uart3"; - bias-disable; - input-enable; - }; - - uart3_tx_cfg { - pins = "p2_3"; - function = "uart3"; - bias-disable; - }; - }; -}; - -&enet_tx_clk { - clock-frequency = <50000000>; -}; - -&i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - clock-frequency = <400000>; - - eeprom@50 { - compatible = "microchip,24c512", "atmel,24c512"; - reg = <0x50>; - }; - - eeprom@51 { - compatible = "microchip,24c02", "atmel,24c02"; - reg = <0x51>; - }; - - eeprom@54 { - compatible = "microchip,24c512", "atmel,24c512"; - reg = <0x54>; - }; -}; - -&mac { - status = "okay"; - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&enet_rmii_pins>; -}; - -&sct_pwm { - status = "okay"; -}; - -&ssp1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&ssp_pins>; - cs-gpios = <&gpio LPC_GPIO(5,15) GPIO_ACTIVE_HIGH>; - num-cs = <1>; -}; - -&uart2 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; -}; - -&uart3 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; -}; diff --git a/sys/gnu/dts/arm/lpc4350-hitex-eval.dts b/sys/gnu/dts/arm/lpc4350-hitex-eval.dts deleted file mode 100644 index 93d0c2e99e7..00000000000 --- a/sys/gnu/dts/arm/lpc4350-hitex-eval.dts +++ /dev/null @@ -1,481 +0,0 @@ -/* - * Hitex LPC4350 Evaluation Board - * - * Copyright 2015 Ariel D'Alessandro - * - * This code is released using a dual license strategy: BSD/GPL - * You can choose the licence that better fits your requirements. - * - * Released under the terms of 3-clause BSD License - * Released under the terms of GNU General Public License Version 2.0 - * - */ -/dts-v1/; - -#include "lpc18xx.dtsi" -#include "lpc4350.dtsi" - -#include "dt-bindings/input/input.h" -#include "dt-bindings/gpio/gpio.h" - -/ { - model = "Hitex LPC4350 Evaluation Board"; - compatible = "hitex,lpc4350-eval-board", "nxp,lpc4350"; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - }; - - chosen { - stdout-path = &uart0; - }; - - memory@28000000 { - device_type = "memory"; - reg = <0x28000000 0x800000>; /* 8 MB */ - }; - - pca_buttons { - compatible = "gpio-keys-polled"; - poll-interval = <100>; - autorepeat; - - button0 { - label = "joy:right"; - linux,code = ; - gpios = <&pca_gpio 8 GPIO_ACTIVE_LOW>; - }; - - button1 { - label = "joy:up"; - linux,code = ; - gpios = <&pca_gpio 9 GPIO_ACTIVE_LOW>; - }; - - - button2 { - label = "joy:enter"; - linux,code = ; - gpios = <&pca_gpio 10 GPIO_ACTIVE_LOW>; - }; - - button3 { - label = "joy:left"; - linux,code = ; - gpios = <&pca_gpio 11 GPIO_ACTIVE_LOW>; - }; - - button4 { - label = "joy:down"; - linux,code = ; - gpios = <&pca_gpio 12 GPIO_ACTIVE_LOW>; - }; - - button5 { - label = "user:sw3"; - linux,code = ; - gpios = <&pca_gpio 13 GPIO_ACTIVE_LOW>; - }; - - button6 { - label = "user:sw4"; - linux,code = ; - gpios = <&pca_gpio 14 GPIO_ACTIVE_LOW>; - }; - - button7 { - label = "user:sw5"; - linux,code = ; - gpios = <&pca_gpio 15 GPIO_ACTIVE_LOW>; - }; - }; - - pca_leds { - compatible = "gpio-leds"; - - led0 { - label = "ext:led0"; - gpios = <&pca_gpio 0 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - }; - - led1 { - label = "ext:led1"; - gpios = <&pca_gpio 1 GPIO_ACTIVE_LOW>; - }; - - led2 { - label = "ext:led2"; - gpios = <&pca_gpio 2 GPIO_ACTIVE_LOW>; - }; - - led3 { - label = "ext:led3"; - gpios = <&pca_gpio 3 GPIO_ACTIVE_LOW>; - }; - }; - - vcc: vcc_fixed { - compatible = "regulator-fixed"; - regulator-name = "3v3io"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&pinctrl { - adc1_pins: adc1-pins { - adc1_pins_cfg { - pins = "pf_9"; - function = "adc"; - input-disable; - bias-disable; - }; - }; - - emc_pins: emc-pins { - emc_addr0_23_cfg { - pins = "p2_9", "p2_10", "p2_11", "p2_12", - "p2_13", "p1_0", "p1_1", "p1_2", - "p2_8", "p2_7", "p2_6", "p2_2", - "p2_1", "p2_0", "p6_8", "p6_7", - "pd_16", "pd_15", "pe_0", "pe_1", - "pe_2", "pe_3", "pe_4", "pa_4"; - function = "emc"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - emc_data0_15_cfg { - pins = "p1_7", "p1_8", "p1_9", "p1_10", - "p1_11", "p1_12", "p1_13", "p1_14", - "p5_4", "p5_5", "p5_6", "p5_7", - "p5_0", "p5_1", "p5_2", "p5_3"; - function = "emc"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - emc_we_oe_cfg { - pins = "p1_6", "p1_3"; - function = "emc"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - emc_bls0_3_cfg { - pins = "p1_4", "p6_6", "pd_13", "pd_10"; - function = "emc"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - emc_cs0_cs2_cfg { - pins = "p1_5", "pd_12"; - function = "emc"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - emc_sdram_dqm0_3_cfg { - pins = "p6_12", "p6_10", "pd_0", "pe_13"; - function = "emc"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - emc_sdram_ras_cas_cfg { - pins = "p6_5", "p6_4"; - function = "emc"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - emc_sdram_dycs0_cfg { - pins = "p6_9"; - function = "emc"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - emc_sdram_cke_cfg { - pins = "p6_11"; - function = "emc"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - emc_sdram_clock_cfg { - pins = "clk0", "clk1", "clk2", "clk3"; - function = "emc"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - }; - - enet_mii_pins: enet-mii-pins { - enet_mii_rxd0_3_cfg { - pins = "p1_15", "p0_0", "p9_3", "p9_2"; - function = "enet"; - bias-disable; - input-enable; - }; - - enet_mii_txd0_3_cfg { - pins = "p1_18", "p1_20", "p9_4", "p9_5"; - function = "enet"; - bias-disable; - }; - - enet_mii_crs_col_cfg { - pins = "p9_0", "p9_6"; - function = "enet"; - bias-disable; - input-enable; - }; - - enet_mii_rx_clk_dv_er_cfg { - pins = "pc_0", "p1_16", "p9_1"; - function = "enet"; - bias-disable; - input-enable; - }; - - enet_mii_tx_clk_en_cfg { - pins = "p1_19", "p0_1"; - function = "enet"; - bias-disable; - input-enable; - }; - - enet_mdio_cfg { - pins = "p1_17"; - function = "enet"; - bias-disable; - input-enable; - }; - - enet_mdc_cfg { - pins = "pc_1"; - function = "enet"; - bias-disable; - }; - }; - - i2c0_pins: i2c0-pins { - i2c0_pins_cfg { - pins = "i2c0_scl", "i2c0_sda"; - function = "i2c0"; - input-enable; - }; - }; - - spifi_pins: spifi-pins { - spifi_clk_cfg { - pins = "p3_3"; - function = "spifi"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - spifi_mosi_miso_sio2_3_cfg { - pins = "p3_7", "p3_6", "p3_5", "p3_4"; - function = "spifi"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - spifi_cs_cfg { - pins = "p3_8"; - function = "spifi"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - }; - - uart0_pins: uart0-pins { - uart0_rx_cfg { - pins = "pf_11"; - function = "uart0"; - input-schmitt-disable; - bias-disable; - input-enable; - }; - - uart0_tx_cfg { - pins = "pf_10"; - function = "uart0"; - bias-pull-down; - }; - }; -}; - -&adc1 { - status = "okay"; - vref-supply = <&vcc>; - pinctrl-names = "default"; - pinctrl-0 = <&adc1_pins>; -}; - -&emc { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&emc_pins>; - - cs0 { - #address-cells = <2>; - #size-cells = <1>; - ranges; - - mpmc,cs = <0>; - mpmc,memory-width = <16>; - mpmc,byte-lane-low; - mpmc,write-enable-delay = <0>; - mpmc,output-enable-delay = <0>; - mpmc,read-access-delay = <70>; - mpmc,page-mode-read-delay = <70>; - - flash@0,0 { - compatible = "sst,sst39vf320", "cfi-flash"; - reg = <0 0 0x400000>; - bank-width = <2>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "bootloader"; - reg = <0x000000 0x040000>; /* 256 KiB */ - }; - - partition@1 { - label = "kernel"; - reg = <0x040000 0x2C0000>; /* 2.75 MiB */ - }; - - partition@2 { - label = "rootfs"; - reg = <0x300000 0x100000>; /* 1 MiB */ - }; - }; - }; - - cs2 { - #address-cells = <2>; - #size-cells = <1>; - ranges; - - mpmc,cs = <2>; - mpmc,memory-width = <16>; - mpmc,byte-lane-low; - mpmc,write-enable-delay = <0>; - mpmc,output-enable-delay = <30>; - mpmc,read-access-delay = <90>; - mpmc,page-mode-read-delay = <55>; - mpmc,write-access-delay = <55>; - mpmc,turn-round-delay = <55>; - - ext_sram: sram@2,0 { - compatible = "mmio-sram"; - reg = <2 0 0x80000>; /* 512 KiB SRAM on IS62WV25616 */ - }; - }; -}; - -&enet_tx_clk { - clock-frequency = <25000000>; -}; - -&i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - clock-frequency = <400000>; - - /* NXP SE97BTP with temperature sensor + eeprom */ - sensor@18 { - compatible = "nxp,se97", "jedec,jc-42.4-temp"; - reg = <0x18>; - }; - - eeprom@50 { - compatible = "nxp,24c02", "atmel,24c02"; - reg = <0x50>; - }; - - pca_gpio: gpio@24 { - compatible = "nxp,pca9673"; - reg = <0x24>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -&mac { - status = "okay"; - phy-mode = "mii"; - pinctrl-names = "default"; - pinctrl-0 = <&enet_mii_pins>; -}; - -&spifi { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&spifi_pins>; - - flash { - compatible = "jedec,spi-nor"; - spi-rx-bus-width = <4>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "bootloader"; - reg = <0x000000 0x040000>; /* 256 KiB */ - }; - - partition@1 { - label = "kernel"; - reg = <0x040000 0x2c0000>; /* 2.75 MiB */ - }; - - partition@2 { - label = "rootfs"; - reg = <0x300000 0x500000>; /* 5 MiB */ - }; - }; -}; - -&uart0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; -}; diff --git a/sys/gnu/dts/arm/lpc4350.dtsi b/sys/gnu/dts/arm/lpc4350.dtsi deleted file mode 100644 index c4422f58705..00000000000 --- a/sys/gnu/dts/arm/lpc4350.dtsi +++ /dev/null @@ -1,39 +0,0 @@ -/* - * NXP LPC4350 and LPC4330 SoC - * - * Copyright 2015 Ariel D'Alessandro - * - * This code is released using a dual license strategy: BSD/GPL - * You can choose the licence that better fits your requirements. - * - * Released under the terms of 3-clause BSD License - * Released under the terms of GNU General Public License Version 2.0 - * - */ - -/ { - compatible = "nxp,lpc4350", "nxp,lpc4330"; - - cpus { - cpu@0 { - compatible = "arm,cortex-m4"; - }; - }; - - soc { - sram0: sram@10000000 { - compatible = "mmio-sram"; - reg = <0x10000000 0x20000>; /* 96 + 32 KiB local SRAM */ - }; - - sram1: sram@10080000 { - compatible = "mmio-sram"; - reg = <0x10080000 0x12000>; /* 64 + 8 KiB local SRAM */ - }; - - sram2: sram@20000000 { - compatible = "mmio-sram"; - reg = <0x20000000 0x10000>; /* 4 x 16 KiB AHB SRAM */ - }; - }; -}; diff --git a/sys/gnu/dts/arm/lpc4357-ea4357-devkit.dts b/sys/gnu/dts/arm/lpc4357-ea4357-devkit.dts deleted file mode 100644 index 224f80a4a31..00000000000 --- a/sys/gnu/dts/arm/lpc4357-ea4357-devkit.dts +++ /dev/null @@ -1,623 +0,0 @@ -/* - * Embedded Artist LPC4357 Developer's Kit - * - * Copyright 2015 Joachim Eastwood - * - * This code is released using a dual license strategy: BSD/GPL - * You can choose the licence that better fits your requirements. - * - * Released under the terms of 3-clause BSD License - * Released under the terms of GNU General Public License Version 2.0 - * - */ -/dts-v1/; - -#include "lpc18xx.dtsi" -#include "lpc4357.dtsi" - -#include "dt-bindings/input/input.h" -#include "dt-bindings/gpio/gpio.h" - -/ { - model = "Embedded Artists' LPC4357 Developer's Kit"; - compatible = "ea,lpc4357-developers-kit", "nxp,lpc4357", "nxp,lpc4350"; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - }; - - chosen { - stdout-path = &uart0; - }; - - memory@28000000 { - device_type = "memory"; - reg = <0x28000000 0x2000000>; /* 32 MB */ - }; - - vcc: vcc_fixed { - compatible = "regulator-fixed"; - regulator-name = "3v3-supply"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - /* vmmc is controlled by sdmmc host internally */ - vmmc: vmmc_fixed { - compatible = "regulator-fixed"; - regulator-name = "vmmc-supply"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - gpio_joystick { - compatible = "gpio-keys-polled"; - pinctrl-names = "default"; - pinctrl-0 = <&gpio_joystick_pins>; - poll-interval = <100>; - autorepeat; - - button0 { - label = "joy_enter"; - linux,code = ; - gpios = <&gpio LPC_GPIO(4,8) GPIO_ACTIVE_LOW>; - }; - - button1 { - label = "joy_left"; - linux,code = ; - gpios = <&gpio LPC_GPIO(4,9) GPIO_ACTIVE_LOW>; - }; - - button2 { - label = "joy_up"; - linux,code = ; - gpios = <&gpio LPC_GPIO(4,10) GPIO_ACTIVE_LOW>; - }; - - button3 { - label = "joy_right"; - linux,code = ; - gpios = <&gpio LPC_GPIO(4,12) GPIO_ACTIVE_LOW>; - }; - - button4 { - label = "joy_down"; - linux,code = ; - gpios = <&gpio LPC_GPIO(4,13) GPIO_ACTIVE_LOW>; - }; - }; - - leds_mmio { - compatible = "gpio-leds"; - - led1 { - gpios = <&mmio_leds 15 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - - led2 { - gpios = <&mmio_leds 14 GPIO_ACTIVE_HIGH>; - }; - - led3 { - gpios = <&mmio_leds 13 GPIO_ACTIVE_HIGH>; - }; - - led4 { - gpios = <&mmio_leds 12 GPIO_ACTIVE_HIGH>; - }; - - led5 { - gpios = <&mmio_leds 11 GPIO_ACTIVE_HIGH>; - }; - - led6 { - gpios = <&mmio_leds 10 GPIO_ACTIVE_HIGH>; - }; - - led7 { - gpios = <&mmio_leds 9 GPIO_ACTIVE_HIGH>; - }; - - led8 { - gpios = <&mmio_leds 8 GPIO_ACTIVE_HIGH>; - }; - - led9 { - gpios = <&mmio_leds 7 GPIO_ACTIVE_HIGH>; - }; - - led10 { - gpios = <&mmio_leds 6 GPIO_ACTIVE_HIGH>; - }; - - led11 { - gpios = <&mmio_leds 5 GPIO_ACTIVE_HIGH>; - }; - - led12 { - gpios = <&mmio_leds 4 GPIO_ACTIVE_HIGH>; - }; - - led13 { - gpios = <&mmio_leds 3 GPIO_ACTIVE_HIGH>; - }; - - led14 { - gpios = <&mmio_leds 2 GPIO_ACTIVE_HIGH>; - }; - - led15 { - gpios = <&mmio_leds 1 GPIO_ACTIVE_HIGH>; - }; - - led16 { - gpios = <&mmio_leds 0 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&pinctrl { - emc_pins: emc-pins { - emc_addr0_23_cfg { - pins = "p2_9", "p2_10", "p2_11", "p2_12", - "p2_13", "p1_0", "p1_1", "p1_2", - "p2_8", "p2_7", "p2_6", "p2_2", - "p2_1", "p2_0", "p6_8", "p6_7", - "pd_16", "pd_15", "pe_0", "pe_1", - "pe_2", "pe_3", "pe_4", "pa_4"; - function = "emc"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - emc_data0_31_cfg { - pins = "p1_7", "p1_8", "p1_9", "p1_10", - "p1_11", "p1_12", "p1_13", "p1_14", - "p5_4", "p5_5", "p5_6", "p5_7", - "p5_0", "p5_1", "p5_2", "p5_3", - "pd_2", "pd_3", "pd_4", "pd_5", - "pd_6", "pd_7", "pd_8", "pd_9", - "pe_5", "pe_6", "pe_7", "pe_8", - "pe_9", "pe_10", "pe_11", "pe_12"; - function = "emc"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - emc_we_oe_cfg { - pins = "p1_6", "p1_3"; - function = "emc"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - emc_bls0_3_cfg { - pins = "p1_4", "p6_6", "pd_13", "pd_10"; - function = "emc"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - emc_cs0_3_cfg { - pins = "p1_5", "p6_3", "pd_12", "pd_11"; - function = "emc"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - emc_sdram_dqm0_3_cfg { - pins = "p6_12", "p6_10", "pd_0", "pe_13"; - function = "emc"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - emc_sdram_ras_cas_cfg { - pins = "p6_5", "p6_4"; - function = "emc"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - emc_sdram_dycs0_cfg { - pins = "p6_9"; - function = "emc"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - emc_sdram_cke_cfg { - pins = "p6_11"; - function = "emc"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - emc_sdram_clock_cfg { - pins = "clk0", "clk1", "clk2", "clk3"; - function = "emc"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - }; - - enet_rmii_pins: enet-rmii-pins { - enet_rmii_rxd_cfg { - pins = "p1_15", "p0_0"; - function = "enet"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - enet_rmii_txd_cfg { - pins = "p1_18", "p1_20"; - function = "enet"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - enet_rmii_rx_dv_cfg { - pins = "p1_16"; - function = "enet"; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - enet_rmii_tx_en_cfg { - pins = "p0_1"; - function = "enet"; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - enet_ref_clk_cfg { - pins = "p1_19"; - function = "enet"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - enet_mdio_cfg { - pins = "p1_17"; - function = "enet"; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - enet_mdc_cfg { - pins = "pc_1"; - function = "enet"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - }; - - gpio_joystick_pins: gpio-joystick-pins { - gpio_joystick_cfg { - pins = "p9_0", "p9_1", "pa_1", "pa_2", "pa_3"; - function = "gpio"; - input-enable; - bias-disable; - }; - }; - - i2c0_pins: i2c0-pins { - i2c0_pins_cfg { - pins = "i2c0_scl", "i2c0_sda"; - function = "i2c0"; - input-enable; - }; - }; - - sdmmc_pins: sdmmc-pins { - sdmmc_clk_cfg { - pins = "pc_0"; - function = "sdmmc"; - slew-rate = <1>; - bias-pull-down; - }; - - sdmmc_cmd_dat0_3_cfg { - pins = "pc_4", "pc_5", "pc_6", "pc_7", "pc_10"; - function = "sdmmc"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - sdmmc_cd_cfg { - pins = "pc_8"; - function = "sdmmc"; - bias-pull-down; - input-enable; - }; - - sdmmc_pow_cfg { - pins = "pc_9"; - function = "sdmmc"; - bias-pull-down; - }; - }; - - spifi_pins: spifi-pins { - spifi_clk_cfg { - pins = "p3_3"; - function = "spifi"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - spifi_mosi_miso_sio2_3_cfg { - pins = "p3_7", "p3_6", "p3_5", "p3_4"; - function = "spifi"; - slew-rate = <0>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - spifi_cs_cfg { - pins = "p3_8"; - function = "spifi"; - bias-disable; - }; - }; - - ssp0_pins: ssp0-pins { - ssp0_sck_miso_mosi { - pins = "pf_0", "pf_2", "pf_3"; - function = "ssp0"; - slew-rate = <1>; - bias-pull-down; - input-enable; - input-schmitt-disable; - }; - - ssp0_ssel { - pins = "pf_1"; - function = "ssp0"; - bias-pull-up; - }; - }; - - uart0_pins: uart0-pins { - uart0_rx_cfg { - pins = "pf_11"; - function = "uart0"; - input-schmitt-disable; - bias-disable; - input-enable; - }; - - uart0_tx_cfg { - pins = "pf_10"; - function = "uart0"; - bias-pull-down; - }; - }; - - uart3_pins: uart3-pins { - uart3_rx_cfg { - pins = "p2_4"; - function = "uart3"; - input-schmitt-disable; - bias-disable; - input-enable; - }; - - uart3_tx_cfg { - pins = "p9_3"; - function = "uart3"; - bias-pull-down; - }; - }; - - usb0_pins: usb0-pins { - usb0_pwr_enable { - pins = "p2_3"; - function = "usb0"; - }; - - usb0_pwr_fault { - pins = "p8_0"; - function = "usb0"; - bias-disable; - input-enable; - }; - }; -}; - -&adc0 { - status = "okay"; - vref-supply = <&vcc>; -}; - -&i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - clock-frequency = <400000>; - - mma7455@1d { - compatible = "fsl,mma7455"; - reg = <0x1d>; - }; - - lm75@48 { - compatible = "nxp,lm75"; - reg = <0x48>; - }; - - eeprom@57 { - compatible = "microchip,24c64", "atmel,24c64"; - reg = <0x57>; - }; -}; - -&dac { - status = "okay"; - vref-supply = <&vcc>; -}; - -&emc { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&emc_pins>; - - cs0 { - #address-cells = <2>; - #size-cells = <1>; - ranges; - - mpmc,cs = <0>; - mpmc,memory-width = <16>; - mpmc,byte-lane-low; - mpmc,write-enable-delay = <0>; - mpmc,output-enable-delay = <0>; - mpmc,read-access-delay = <70>; - mpmc,page-mode-read-delay = <70>; - - flash@0,0 { - compatible = "sst,sst39vf320", "cfi-flash"; - reg = <0 0 0x400000>; - bank-width = <2>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "bootloader"; - reg = <0x000000 0x040000>; /* 256 KiB */ - }; - - partition@1 { - label = "kernel"; - reg = <0x040000 0x2c0000>; /* 2.75 MiB */ - }; - - partition@2 { - label = "rootfs"; - reg = <0x300000 0x100000>; /* 1 MiB */ - }; - }; - }; - - cs2 { - #address-cells = <2>; - #size-cells = <1>; - ranges; - - mpmc,cs = <2>; - mpmc,memory-width = <16>; - - mmio_leds: gpio@2,0 { - compatible = "ti,7416374"; - reg = <2 0 0x2>; - gpio-controller; - #gpio-cells = <2>; - }; - - }; -}; - -&enet_tx_clk { - clock-frequency = <50000000>; -}; - -&mac { - status = "okay"; - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&enet_rmii_pins>; -}; - -&mmcsd { - status = "okay"; - bus-width = <4>; - vmmc-supply = <&vmmc>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_pins>; -}; - -&spifi { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&spifi_pins>; - - flash { - compatible = "jedec,spi-nor"; - spi-cpol; - spi-cpha; - spi-rx-bus-width = <4>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "data"; - reg = <0 0x200000>; - }; - }; -}; - -&ssp0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&ssp0_pins>; - num-cs = <1>; -}; - -&uart0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; -}; - -&uart3 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; -}; - -&usb0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&usb0_pins>; -}; diff --git a/sys/gnu/dts/arm/lpc4357-myd-lpc4357.dts b/sys/gnu/dts/arm/lpc4357-myd-lpc4357.dts deleted file mode 100644 index 1f84654df50..00000000000 --- a/sys/gnu/dts/arm/lpc4357-myd-lpc4357.dts +++ /dev/null @@ -1,619 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * MYIR Tech MYD-LPC4357 Development Board with 800x480 7" TFT panel - * - * Copyright (C) 2016-2018 Vladimir Zapolskiy - */ - -/dts-v1/; - -#include "lpc18xx.dtsi" -#include "lpc4357.dtsi" - -#include - -/ { - model = "MYIR Tech LPC4357 Development Board"; - compatible = "myir,myd-lpc4357", "nxp,lpc4357"; - - chosen { - stdout-path = "serial3:115200n8"; - }; - - memory@28000000 { - device_type = "memory"; - reg = <0x28000000 0x2000000>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins>; - - led1 { - gpios = <&gpio LPC_GPIO(6,15) GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led2 { - gpios = <&gpio LPC_GPIO(6,16) GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led3 { - gpios = <&gpio LPC_GPIO(6,17) GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led4 { - gpios = <&gpio LPC_GPIO(6,10) GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led5 { - gpios = <&gpio LPC_GPIO(7,14) GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led6 { - gpios = <&gpio LPC_GPIO(6,14) GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - }; - - panel: panel { - compatible = "innolux,at070tn92"; - - port { - panel_input: endpoint { - remote-endpoint = <&lcdc_output>; - }; - }; - }; - - vcc: vcc_fixed { - compatible = "regulator-fixed"; - regulator-name = "vcc-supply"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vmmc: vmmc_fixed { - compatible = "regulator-fixed"; - regulator-name = "vmmc-supply"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&pinctrl { - can0_pins: can0-pins { - can_rd_cfg { - pins = "p3_1"; - function = "can0"; - input-enable; - }; - - can_td_cfg { - pins = "p3_2"; - function = "can0"; - }; - }; - - can1_pins: can1-pins { - can_rd_cfg { - pins = "pe_1"; - function = "can1"; - input-enable; - }; - - can_td_cfg { - pins = "pe_0"; - function = "can1"; - }; - }; - - emc_pins: emc-pins { - emc_addr0_22_cfg { - pins = "p2_9", "p2_10", "p2_11", "p2_12", - "p2_13", "p1_0", "p1_1", "p1_2", - "p2_8", "p2_7", "p2_6", "p2_2", - "p2_1", "p2_0", "p6_8", "p6_7", - "pd_16", "pd_15", "pe_0", "pe_1", - "pe_2", "pe_3", "pe_4"; - function = "emc"; - slew-rate = <1>; - bias-disable; - }; - - emc_data0_15_cfg { - pins = "p1_7", "p1_8", "p1_9", "p1_10", - "p1_11", "p1_12", "p1_13", "p1_14", - "p5_4", "p5_5", "p5_6", "p5_7", - "p5_0", "p5_1", "p5_2", "p5_3"; - function = "emc"; - input-enable; - input-schmitt-disable; - slew-rate = <1>; - bias-disable; - }; - - emc_we_oe_cfg { - pins = "p1_6", "p1_3"; - function = "emc"; - slew-rate = <1>; - bias-disable; - }; - - emc_cs0_cfg { - pins = "p1_5"; - function = "emc"; - slew-rate = <1>; - bias-disable; - }; - - emc_sdram_dqm0_1_cfg { - pins = "p6_12", "p6_10"; - function = "emc"; - slew-rate = <1>; - bias-disable; - }; - - emc_sdram_ras_cas_cfg { - pins = "p6_5", "p6_4"; - function = "emc"; - slew-rate = <1>; - bias-disable; - }; - - emc_sdram_dycs0_cfg { - pins = "p6_9"; - function = "emc"; - slew-rate = <1>; - bias-disable; - }; - - emc_sdram_cke_cfg { - pins = "p6_11"; - function = "emc"; - slew-rate = <1>; - bias-disable; - }; - - emc_sdram_clock_cfg { - pins = "clk0"; - function = "emc"; - input-enable; - input-schmitt-disable; - slew-rate = <1>; - bias-disable; - }; - }; - - enet_rmii_pins: enet-rmii-pins { - enet_rmii_rxd_cfg { - pins = "p1_15", "p0_0"; - function = "enet"; - input-enable; - input-schmitt-disable; - slew-rate = <1>; - bias-disable; - }; - - enet_rmii_txd_cfg { - pins = "p1_18", "p1_20"; - function = "enet"; - slew-rate = <1>; - bias-disable; - }; - - enet_rmii_rx_dv_cfg { - pins = "p1_16"; - function = "enet"; - input-enable; - input-schmitt-disable; - bias-disable; - }; - - enet_mdio_cfg { - pins = "p1_17"; - function = "enet"; - input-enable; - input-schmitt-disable; - bias-disable; - }; - - enet_mdc_cfg { - pins = "pc_1"; - function = "enet"; - slew-rate = <1>; - bias-disable; - }; - - enet_rmii_tx_en_cfg { - pins = "p0_1"; - function = "enet"; - bias-disable; - }; - - enet_ref_clk_cfg { - pins = "p1_19"; - function = "enet"; - slew-rate = <1>; - input-enable; - input-schmitt-disable; - bias-disable; - }; - }; - - i2c0_pins: i2c0-pins { - i2c0_pins_cfg { - pins = "i2c0_scl", "i2c0_sda"; - function = "i2c0"; - input-enable; - }; - }; - - i2c1_pins: i2c1-pins { - i2c1_pins_cfg { - pins = "pe_15", "pe_13"; - function = "i2c1"; - input-enable; - }; - }; - - lcd_pins: lcd-pins { - lcd_vd0_23_cfg { - pins = "p4_1", "p4_4", "p4_3", "p4_2", - "p8_7", "p8_6", "p8_5", "p8_4", - "p7_5", "p4_8", "p4_10", "p4_9", - "p8_3", "pb_6", "pb_5", "pb_4", - "p7_4", "p7_3", "p7_2", "p7_1", - "pb_3", "pb_2", "pb_1", "pb_0"; - function = "lcd"; - }; - - lcd_vsync_en_dclk_lp_pwr_cfg { - pins = "p4_5", "p4_6", "p4_7", "p7_6", "p7_7"; - function = "lcd"; - }; - }; - - led_pins: led-pins { - led_1_6_cfg { - pins = "pd_1", "pd_2", "pd_3", "pc_11", "pe_14", "pd_0"; - function = "gpio"; - bias-pull-down; - }; - }; - - sdmmc_pins: sdmmc-pins { - sdmmc_clk_cfg { - pins = "pc_0"; - function = "sdmmc"; - slew-rate = <1>; - bias-pull-down; - }; - - sdmmc_cmd_dat0_3_cfg { - pins = "pc_4", "pc_5", "pc_6", "pc_7", "pc_10"; - function = "sdmmc"; - input-enable; - input-schmitt-disable; - slew-rate = <1>; - bias-disable; - }; - - sdmmc_cd_cfg { - pins = "pc_8"; - function = "sdmmc"; - input-enable; - bias-pull-down; - }; - }; - - spifi_pins: spifi-pins { - spifi_sck_cfg { - pins = "p3_3"; - function = "spifi"; - input-enable; - input-schmitt-disable; - slew-rate = <1>; - bias-disable; - }; - - spifi_mosi_miso_sio2_sio3_cfg { - pins = "p3_7", "p3_6", "p3_5", "p3_4"; - function = "spifi"; - input-enable; - input-schmitt-disable; - slew-rate = <1>; - bias-disable; - }; - - spifi_cs_cfg { - pins = "p3_8"; - function = "spifi"; - bias-disable; - }; - }; - - ssp1_pins: ssp1-pins { - ssp1_sck_cfg { - pins = "pf_4"; - function = "ssp1"; - slew-rate = <1>; - bias-pull-down; - }; - - ssp1_miso_cfg { - pins = "pf_6"; - function = "ssp1"; - input-enable; - input-schmitt-disable; - slew-rate = <1>; - bias-pull-down; - }; - - ssp1_mosi_cfg { - pins = "pf_7"; - function = "ssp1"; - slew-rate = <1>; - bias-pull-down; - }; - - ssp1_ssel_cfg { - pins = "pf_5"; - function = "gpio"; - bias-disable; - }; - }; - - uart0_pins: uart0-pins { - uart0_rxd_cfg { - pins = "pf_11"; - function = "uart0"; - input-enable; - input-schmitt-disable; - bias-disable; - }; - - uart0_clk_dir_txd_cfg { - pins = "pf_8", "pf_9", "pf_10"; - function = "uart0"; - bias-pull-down; - }; - }; - - uart1_pins: uart1-pins { - uart1_rxd_cfg { - pins = "pc_14"; - function = "uart1"; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - uart1_dtr_txd_cfg { - pins = "pc_12", "pc_13"; - function = "uart1"; - bias-pull-down; - }; - }; - - uart2_pins: uart2-pins { - uart2_rxd_cfg { - pins = "pa_2"; - function = "uart2"; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - uart2_txd_cfg { - pins = "pa_1"; - function = "uart2"; - bias-pull-down; - }; - }; - - uart3_pins: uart3-pins { - uart3_rx_cfg { - pins = "p2_4"; - function = "uart3"; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - uart3_tx_cfg { - pins = "p2_3"; - function = "uart3"; - bias-pull-down; - }; - }; - - usb0_pins: usb0-pins { - usb0_pwr_enable_cfg { - pins = "p6_3"; - function = "usb0"; - }; - - usb0_pwr_fault_cfg { - pins = "p8_0"; - function = "usb0"; - bias-disable; - input-enable; - }; - }; -}; - -&adc1 { - status = "okay"; - vref-supply = <&vcc>; -}; - -&can0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&can0_pins>; -}; - -/* Pin conflict with EMC, muxed by JP5 and JP6 */ -&can1 { - status = "disabled"; - pinctrl-names = "default"; - pinctrl-0 = <&can1_pins>; -}; - -&emc { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&emc_pins>; - - cs0 { - #address-cells = <2>; - #size-cells = <1>; - ranges; - - mpmc,cs = <0>; - mpmc,memory-width = <16>; - mpmc,byte-lane-low; - mpmc,write-enable-delay = <0>; - mpmc,output-enable-delay = <0>; - mpmc,read-access-delay = <70>; - mpmc,page-mode-read-delay = <70>; - - /* SST/Microchip SST39VF1601 */ - flash@0,0 { - compatible = "cfi-flash"; - reg = <0 0 0x400000>; - bank-width = <2>; - }; - }; -}; - -&enet_tx_clk { - clock-frequency = <50000000>; -}; - -&i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - clock-frequency = <400000>; -}; - -&i2c1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - clock-frequency = <400000>; - - sensor@49 { - compatible = "lm75"; - reg = <0x49>; - }; - - eeprom@50 { - compatible = "atmel,24c512"; - reg = <0x50>; - }; -}; - -&lcdc { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&lcd_pins>; - - max-memory-bandwidth = <92240000>; - - port { - lcdc_output: endpoint { - remote-endpoint = <&panel_input>; - arm,pl11x,tft-r0g0b0-pads = <0 8 16>; - }; - }; -}; - -&mac { - status = "okay"; - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&enet_rmii_pins>; - phy-handle = <&phy1>; - - mdio0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - - phy1: ethernet-phy@1 { - reg = <1>; - }; - }; -}; - -&mmcsd { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_pins>; - bus-width = <4>; - vmmc-supply = <&vmmc>; -}; - -/* Pin conflict with SSP0, the latter is routed to J17 pin header */ -&spifi { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&spifi_pins>; - - /* Atmel AT25DF321A */ - flash { - compatible = "jedec,spi-nor"; - spi-max-frequency = <51000000>; - spi-cpol; - spi-cpha; - }; -}; - -&ssp1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&ssp1_pins>; - num-cs = <1>; - cs-gpios = <&gpio LPC_GPIO(7,19) GPIO_ACTIVE_LOW>; -}; - -/* Routed to J17 pin header */ -&uart0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; -}; - -/* RS485 */ -&uart1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; -}; - -/* Routed to J17 pin header */ -&uart2 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; -}; - -&uart3 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; -}; - -&usb0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&usb0_pins>; -}; diff --git a/sys/gnu/dts/arm/lpc4357.dtsi b/sys/gnu/dts/arm/lpc4357.dtsi deleted file mode 100644 index 72f12db8d53..00000000000 --- a/sys/gnu/dts/arm/lpc4357.dtsi +++ /dev/null @@ -1,43 +0,0 @@ -/* - * NXP LPC435x, LPC433x, LPC4327, LPC4325, LPC4317 and LPC4315 SoC - * - * Copyright 2015 Joachim Eastwood - * - * This code is released using a dual license strategy: BSD/GPL - * You can choose the licence that better fits your requirements. - * - * Released under the terms of 3-clause BSD License - * Released under the terms of GNU General Public License Version 2.0 - * - */ - -/ { - compatible = "nxp,lpc4357"; - - cpus { - cpu@0 { - compatible = "arm,cortex-m4"; - }; - }; - - soc { - sram0: sram@10000000 { - compatible = "mmio-sram"; - reg = <0x10000000 0x8000>; /* 32 KiB local SRAM */ - }; - - sram1: sram@10080000 { - compatible = "mmio-sram"; - reg = <0x10080000 0xa000>; /* 32 + 8 KiB local SRAM */ - }; - - sram2: sram@20000000 { - compatible = "mmio-sram"; - reg = <0x20000000 0x10000>; /* 4 x 16 KiB AHB SRAM */ - }; - }; -}; - -&eeprom { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/ls1021a-moxa-uc-8410a.dts b/sys/gnu/dts/arm/ls1021a-moxa-uc-8410a.dts deleted file mode 100644 index f3ddea934f1..00000000000 --- a/sys/gnu/dts/arm/ls1021a-moxa-uc-8410a.dts +++ /dev/null @@ -1,237 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2017 Moxa Inc. - https://www.moxa.com/ - * - * Author: Harry YJ Jhou (周亞諄) - * Jimmy Chen (陳永達) - * SZ Lin (林上智) - */ - -/dts-v1/; - -#include -#include -#include "ls1021a.dtsi" - -/ { - model = "Moxa UC-8410A"; - compatible = "fsl,ls1021a-moxa-uc-8410a", "fsl,ls1021a"; - - aliases { - enet0_rgmii_phy = &rgmii_phy0; - enet1_rgmii_phy = &rgmii_phy1; - enet2_rgmii_phy = &rgmii_phy2; - }; - - sys_mclk: clock-mclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24576000>; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - leds { - compatible = "gpio-leds"; - - cel-pwr { - label = "UC8410A:CEL-PWR"; - gpios = <&gpio3 27 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - cel-reset { - label = "UC8410A:CEL-RESET"; - gpios = <&gpio3 28 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - str-led { - label = "UC8410A:RED:PROG"; - gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc0"; - }; - - sw-ready { - label = "UC8410A:GREEN:SWRDY"; - gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - beeper { - label = "UC8410A:BEEP"; - gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - prog-led0 { - label = "UC8410A:GREEN:PROG2"; - gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - prog-led1 { - label = "UC8410A:GREEN:PROG1"; - gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - prog-led2 { - label = "UC8410A:GREEN:PROG0"; - gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - wifi-signal0 { - label = "UC8410A:GREEN:CEL2"; - gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - wifi-signal1 { - label = "UC8410A:GREEN:CEL1"; - gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - wifi-signal2 { - label = "UC8410A:GREEN:CEL0"; - gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - cpu-diag-red { - label = "UC8410A:RED:DIA"; - gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - cpu-diag-green { - label = "UC8410A:GREEN:DIA"; - gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - cpu-diag-yellow { - label = "UC8410A:YELLOW:DIA"; - gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - pushbtn-key { - label = "push button key"; - gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; - linux,code = ; - default-state = "on"; - }; - }; -}; - -&enet0 { - phy-handle = <&rgmii_phy0>; - phy-connection-type = "rgmii-id"; - status = "okay"; -}; - -&enet1 { - phy-handle = <&rgmii_phy1>; - phy-connection-type = "rgmii-id"; - status = "okay"; -}; - -&enet2 { - phy-handle = <&rgmii_phy2>; - phy-connection-type = "rgmii-id"; - status = "okay"; -}; - -&i2c0 { - clock-frequency = <100000>; - status = "okay"; - - tpm@20 { - compatible = "infineon,slb9635tt"; - reg = <0x20>; - }; - - rtc@68 { - compatible = "dallas,ds1374"; - reg = <0x68>; - }; -}; - -&lpuart0 { - status = "okay"; -}; - -&mdio0 { - rgmii_phy0: ethernet-phy@0 { - compatible = "marvell,88e1118"; - reg = <0x0>; - marvell,reg-init = - <3 0x11 0 0x4415>, /* Reg 3,17 */ - <3 0x10 0 0x77>; /* Reg 3,16 */ - }; - - rgmii_phy1: ethernet-phy@1 { - compatible = "marvell,88e1118"; - reg = <0x1>; - marvell,reg-init = - <3 0x11 0 0x4415>, /* Reg 3,17 */ - <3 0x10 0 0x77>; /* Reg 3,16 */ - }; - - rgmii_phy2: ethernet-phy@2 { - compatible = "marvell,88e1118"; - reg = <0x2>; - marvell,reg-init = - <3 0x11 0 0x4415>, /* Reg 3,17 */ - <3 0x10 0 0x77>; /* Reg 3,16 */ - }; -}; - -&qspi { - status = "okay"; - - flash: flash@0 { - compatible = "spansion,s25fl064l", "spansion,s25fl164k"; - #address-cells = <1>; - #size-cells = <1>; - spi-max-frequency = <20000000>; - spi-rx-bus-width = <4>; - spi-tx-bus-width = <4>; - reg = <0>; - - partitions@0 { - label = "U-Boot"; - reg = <0x0 0x180000>; - }; - - partitions@180000 { - label = "U-Boot Env"; - reg = <0x180000 0x680000>; - }; - }; -}; - -&sata { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/ls1021a-qds.dts b/sys/gnu/dts/arm/ls1021a-qds.dts deleted file mode 100644 index 74a67604876..00000000000 --- a/sys/gnu/dts/arm/ls1021a-qds.dts +++ /dev/null @@ -1,361 +0,0 @@ -/* - * Copyright 2013-2014 Freescale Semiconductor, Inc. - * Copyright 2018 NXP - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "ls1021a.dtsi" - -/ { - model = "LS1021A QDS Board"; - compatible = "fsl,ls1021a-qds", "fsl,ls1021a"; - - aliases { - enet0_rgmii_phy = &rgmii_phy1; - enet1_rgmii_phy = &rgmii_phy2; - enet2_rgmii_phy = &rgmii_phy3; - enet0_sgmii_phy = &sgmii_phy1c; - enet1_sgmii_phy = &sgmii_phy1d; - }; - - sys_mclk: clock-mclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24576000>; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_3p3v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,widgets = - "Microphone", "Microphone Jack", - "Headphone", "Headphone Jack", - "Speaker", "Speaker Ext", - "Line", "Line In Jack"; - simple-audio-card,routing = - "MIC_IN", "Microphone Jack", - "Microphone Jack", "Mic Bias", - "LINE_IN", "Line In Jack", - "Headphone Jack", "HP_OUT", - "Speaker Ext", "LINE_OUT"; - - simple-audio-card,cpu { - sound-dai = <&sai2>; - frame-master; - bitclock-master; - }; - - simple-audio-card,codec { - sound-dai = <&codec>; - frame-master; - bitclock-master; - }; - }; -}; - -&dspi0 { - bus-num = <0>; - status = "okay"; - - dspiflash: at45db021d@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "atmel,at45db021d", "atmel,at45", "atmel,dataflash"; - spi-max-frequency = <16000000>; - spi-cpol; - spi-cpha; - reg = <0>; - }; -}; - -&enet0 { - tbi-handle = <&tbi0>; - phy-handle = <&sgmii_phy1c>; - phy-connection-type = "sgmii"; - status = "okay"; -}; - -&enet1 { - tbi-handle = <&tbi0>; - phy-handle = <&sgmii_phy1d>; - phy-connection-type = "sgmii"; - status = "okay"; -}; - -&enet2 { - phy-handle = <&rgmii_phy3>; - phy-connection-type = "rgmii-id"; - status = "okay"; -}; - -&esdhc { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - pca9547: mux@77 { - compatible = "nxp,pca9547"; - reg = <0x77>; - #address-cells = <1>; - #size-cells = <0>; - - i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0>; - - ds3232: rtc@68 { - compatible = "dallas,ds3232"; - reg = <0x68>; - interrupts = ; - }; - }; - - i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x2>; - - ina220@40 { - compatible = "ti,ina220"; - reg = <0x40>; - shunt-resistor = <1000>; - }; - - ina220@41 { - compatible = "ti,ina220"; - reg = <0x41>; - shunt-resistor = <1000>; - }; - }; - - i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x3>; - - eeprom@56 { - compatible = "atmel,24c512"; - reg = <0x56>; - }; - - eeprom@57 { - compatible = "atmel,24c512"; - reg = <0x57>; - }; - - adt7461a@4c { - compatible = "adi,adt7461a"; - reg = <0x4c>; - }; - }; - - i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x4>; - - codec: sgtl5000@2a { - #sound-dai-cells = <0>; - compatible = "fsl,sgtl5000"; - reg = <0x2a>; - VDDA-supply = <®_3p3v>; - VDDIO-supply = <®_3p3v>; - clocks = <&sys_mclk>; - }; - }; - }; -}; - -&ifc { - #address-cells = <2>; - #size-cells = <1>; - /* NOR, NAND Flashes and FPGA on board */ - ranges = <0x0 0x0 0x0 0x60000000 0x08000000 - 0x2 0x0 0x0 0x7e800000 0x00010000 - 0x3 0x0 0x0 0x7fb00000 0x00000100>; - status = "okay"; - - nor@0,0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "cfi-flash"; - reg = <0x0 0x0 0x8000000>; - big-endian; - bank-width = <2>; - device-width = <1>; - }; - - nand@2,0 { - compatible = "fsl,ifc-nand"; - reg = <0x2 0x0 0x10000>; - }; - - fpga: board-control@3,0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - reg = <0x3 0x0 0x0000100>; - bank-width = <1>; - device-width = <1>; - ranges = <0 3 0 0x100>; - - mdio-mux-emi1 { - compatible = "mdio-mux-mmioreg"; - mdio-parent-bus = <&mdio0>; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x54 1>; /* BRDCFG4 */ - mux-mask = <0xe0>; /* EMI1[2:0] */ - - /* Onboard PHYs */ - ls1021amdio0: mdio@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - rgmii_phy1: ethernet-phy@1 { - reg = <0x1>; - }; - }; - - ls1021amdio1: mdio@20 { - reg = <0x20>; - #address-cells = <1>; - #size-cells = <0>; - rgmii_phy2: ethernet-phy@2 { - reg = <0x2>; - }; - }; - - ls1021amdio2: mdio@40 { - reg = <0x40>; - #address-cells = <1>; - #size-cells = <0>; - rgmii_phy3: ethernet-phy@3 { - reg = <0x3>; - }; - }; - - ls1021amdio3: mdio@60 { - reg = <0x60>; - #address-cells = <1>; - #size-cells = <0>; - sgmii_phy1c: ethernet-phy@1c { - reg = <0x1c>; - }; - }; - - ls1021amdio4: mdio@80 { - reg = <0x80>; - #address-cells = <1>; - #size-cells = <0>; - sgmii_phy1d: ethernet-phy@1d { - reg = <0x1d>; - }; - }; - }; - }; -}; - -&lpuart0 { - status = "okay"; -}; - -&mdio0 { - tbi0: tbi-phy@8 { - reg = <0x8>; - device_type = "tbi-phy"; - }; -}; - -&sai2 { - status = "okay"; -}; - -&sata { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&can0 { - status = "okay"; -}; - -&can1 { - status = "okay"; -}; - -&can2 { - status = "disabled"; -}; - -&can3 { - status = "disabled"; -}; diff --git a/sys/gnu/dts/arm/ls1021a-tsn.dts b/sys/gnu/dts/arm/ls1021a-tsn.dts deleted file mode 100644 index 9d8f0c2a8ab..00000000000 --- a/sys/gnu/dts/arm/ls1021a-tsn.dts +++ /dev/null @@ -1,293 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* Copyright 2016-2018 NXP Semiconductors - * Copyright 2019 Vladimir Oltean - */ - -/dts-v1/; -#include "ls1021a.dtsi" - -/ { - model = "NXP LS1021A-TSN Board"; - - sys_mclk: clock-mclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24576000>; - }; - - reg_vdda_codec: regulator-3V3 { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_vddio_codec: regulator-2V5 { - compatible = "regulator-fixed"; - regulator-name = "2P5V"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; -}; - -&dspi0 { - bus-num = <0>; - status = "okay"; - - /* ADG704BRMZ 1:4 SPI mux/demux */ - sja1105: ethernet-switch@1 { - reg = <0x1>; - #address-cells = <1>; - #size-cells = <0>; - compatible = "nxp,sja1105t"; - /* 12 MHz */ - spi-max-frequency = <12000000>; - /* Sample data on trailing clock edge */ - spi-cpha; - /* SPI controller settings for SJA1105 timing requirements */ - fsl,spi-cs-sck-delay = <1000>; - fsl,spi-sck-cs-delay = <1000>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - /* ETH5 written on chassis */ - label = "swp5"; - phy-handle = <&rgmii_phy6>; - phy-mode = "rgmii-id"; - reg = <0>; - }; - - port@1 { - /* ETH2 written on chassis */ - label = "swp2"; - phy-handle = <&rgmii_phy3>; - phy-mode = "rgmii-id"; - reg = <1>; - }; - - port@2 { - /* ETH3 written on chassis */ - label = "swp3"; - phy-handle = <&rgmii_phy4>; - phy-mode = "rgmii-id"; - reg = <2>; - }; - - port@3 { - /* ETH4 written on chassis */ - label = "swp4"; - phy-handle = <&rgmii_phy5>; - phy-mode = "rgmii-id"; - reg = <3>; - }; - - port@4 { - /* Internal port connected to eth2 */ - ethernet = <&enet2>; - phy-mode = "rgmii"; - reg = <4>; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; - }; -}; - -&enet0 { - tbi-handle = <&tbi0>; - phy-handle = <&sgmii_phy2>; - phy-mode = "sgmii"; - status = "okay"; -}; - -&enet1 { - tbi-handle = <&tbi1>; - phy-handle = <&sgmii_phy1>; - phy-mode = "sgmii"; - status = "okay"; -}; - -/* RGMII delays added via PCB traces */ -&enet2 { - phy-mode = "rgmii"; - status = "okay"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&esdhc { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - /* 3 axis accelerometer */ - accelerometer@1e { - compatible = "fsl,fxls8471"; - position = <0>; - reg = <0x1e>; - }; - - /* Audio codec (SAI2) */ - audio-codec@2a { - compatible = "fsl,sgtl5000"; - VDDIO-supply = <®_vddio_codec>; - VDDA-supply = <®_vdda_codec>; - #sound-dai-cells = <0>; - clocks = <&sys_mclk>; - reg = <0x2a>; - }; - - /* Current sensing circuit for 1V VDDCORE PMIC rail */ - current-sensor@44 { - compatible = "ti,ina220"; - shunt-resistor = <1000>; - reg = <0x44>; - }; - - /* Current sensing circuit for 12V VCC rail */ - current-sensor@45 { - compatible = "ti,ina220"; - shunt-resistor = <1000>; - reg = <0x45>; - }; - - /* Thermal monitor - case */ - temperature-sensor@48 { - compatible = "national,lm75"; - reg = <0x48>; - }; - - /* Thermal monitor - chip */ - temperature-sensor@4c { - compatible = "ti,tmp451"; - reg = <0x4c>; - }; - - eeprom@51 { - compatible = "atmel,24c32"; - reg = <0x51>; - }; - - /* Unsupported devices: - * - FXAS21002C Gyroscope at 0x20 - * - TI ADS7924 4-channel ADC at 0x49 - */ -}; - -&ifc { - status = "disabled"; -}; - -&lpuart0 { - status = "okay"; -}; - -&lpuart3 { - status = "okay"; -}; - -&mdio0 { - /* AR8031 */ - sgmii_phy1: ethernet-phy@1 { - reg = <0x1>; - /* SGMII1_PHY_INT_B: connected to IRQ2, active low */ - interrupts-extended = <&extirq 2 IRQ_TYPE_LEVEL_LOW>; - }; - - /* AR8031 */ - sgmii_phy2: ethernet-phy@2 { - reg = <0x2>; - /* SGMII2_PHY_INT_B: connected to IRQ2, active low */ - interrupts-extended = <&extirq 2 IRQ_TYPE_LEVEL_LOW>; - }; - - /* BCM5464 quad PHY */ - rgmii_phy3: ethernet-phy@3 { - reg = <0x3>; - }; - - rgmii_phy4: ethernet-phy@4 { - reg = <0x4>; - }; - - rgmii_phy5: ethernet-phy@5 { - reg = <0x5>; - }; - - rgmii_phy6: ethernet-phy@6 { - reg = <0x6>; - }; - - /* SGMII PCS for enet0 */ - tbi0: tbi-phy@1f { - reg = <0x1f>; - device_type = "tbi-phy"; - }; -}; - -&mdio1 { - /* SGMII PCS for enet1 */ - tbi1: tbi-phy@1f { - reg = <0x1f>; - device_type = "tbi-phy"; - }; -}; - -&qspi { - status = "okay"; - - flash@0 { - /* Rev. A uses 64MB flash, Rev. B & C use 32MB flash */ - compatible = "jedec,spi-nor", "s25fl256s1", "s25fl512s"; - spi-max-frequency = <20000000>; - #address-cells = <1>; - #size-cells = <1>; - reg = <0>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "RCW"; - reg = <0x0 0x40000>; - }; - - partition@40000 { - label = "U-Boot"; - reg = <0x40000 0x300000>; - }; - - partition@340000 { - label = "U-Boot Env"; - reg = <0x340000 0x100000>; - }; - }; - }; -}; - -&sai2 { - status = "okay"; -}; - -&sata { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/ls1021a-twr.dts b/sys/gnu/dts/arm/ls1021a-twr.dts deleted file mode 100644 index 9b1fe99d55b..00000000000 --- a/sys/gnu/dts/arm/ls1021a-twr.dts +++ /dev/null @@ -1,275 +0,0 @@ -/* - * Copyright 2013-2014 Freescale Semiconductor, Inc. - * Copyright 2018 NXP - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "ls1021a.dtsi" - -/ { - model = "LS1021A TWR Board"; - compatible = "fsl,ls1021a-twr", "fsl,ls1021a"; - - aliases { - enet2_rgmii_phy = &rgmii_phy1; - enet0_sgmii_phy = &sgmii_phy2; - enet1_sgmii_phy = &sgmii_phy0; - }; - - sys_mclk: clock-mclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24576000>; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_3p3v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,widgets = - "Microphone", "Microphone Jack", - "Headphone", "Headphone Jack", - "Speaker", "Speaker Ext", - "Line", "Line In Jack"; - simple-audio-card,routing = - "MIC_IN", "Microphone Jack", - "Microphone Jack", "Mic Bias", - "LINE_IN", "Line In Jack", - "Headphone Jack", "HP_OUT", - "Speaker Ext", "LINE_OUT"; - - simple-audio-card,cpu { - sound-dai = <&sai1>; - frame-master; - bitclock-master; - }; - - simple-audio-card,codec { - sound-dai = <&codec>; - frame-master; - bitclock-master; - }; - }; - - panel: panel { - compatible = "nec,nl4827hc19-05b"; - - port { - panel_in: endpoint { - remote-endpoint = <&dcu_out>; - }; - }; - }; -}; - -&dcu { - status = "okay"; - - port { - dcu_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; -}; - -&dspi1 { - bus-num = <0>; - status = "okay"; - - dspiflash: s25fl064k@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "spansion,s25fl064k"; - spi-max-frequency = <16000000>; - spi-cpol; - spi-cpha; - reg = <0>; - }; -}; - -&enet0 { - tbi-handle = <&tbi0>; - phy-handle = <&sgmii_phy2>; - phy-connection-type = "sgmii"; - status = "okay"; -}; - -&enet1 { - tbi-handle = <&tbi1>; - phy-handle = <&sgmii_phy0>; - phy-connection-type = "sgmii"; - status = "okay"; -}; - -&enet2 { - phy-handle = <&rgmii_phy1>; - phy-connection-type = "rgmii-id"; - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - ina220@40 { - compatible = "ti,ina220"; - reg = <0x40>; - shunt-resistor = <1000>; - }; - - ina220@41 { - compatible = "ti,ina220"; - reg = <0x41>; - shunt-resistor = <1000>; - }; - -}; - -&i2c1 { - status = "okay"; - codec: sgtl5000@a { - #sound-dai-cells = <0>; - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - VDDA-supply = <®_3p3v>; - VDDIO-supply = <®_3p3v>; - clocks = <&sys_mclk>; - }; -}; - -&ifc { - #address-cells = <2>; - #size-cells = <1>; - /* NOR Flash on board */ - ranges = <0x0 0x0 0x0 0x60000000 0x08000000>; - status = "okay"; - - nor@0,0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "cfi-flash"; - reg = <0x0 0x0 0x8000000>; - big-endian; - bank-width = <2>; - device-width = <1>; - }; -}; - -&lpuart0 { - status = "okay"; -}; - -&mdio0 { - sgmii_phy0: ethernet-phy@0 { - reg = <0x0>; - }; - rgmii_phy1: ethernet-phy@1 { - reg = <0x1>; - }; - sgmii_phy2: ethernet-phy@2 { - reg = <0x2>; - }; - tbi0: tbi-phy@1f { - reg = <0x1f>; - device_type = "tbi-phy"; - }; -}; - -&mdio1 { - tbi1: tbi-phy@1f { - reg = <0x1f>; - device_type = "tbi-phy"; - }; -}; - -&esdhc { - status = "okay"; -}; - -&sai1 { - status = "okay"; -}; - -&sata { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&can0 { - status = "okay"; -}; - -&can1 { - status = "okay"; -}; - -&can2 { - status = "disabled"; -}; - -&can3 { - status = "disabled"; -}; diff --git a/sys/gnu/dts/arm/ls1021a.dtsi b/sys/gnu/dts/arm/ls1021a.dtsi deleted file mode 100644 index 760a68c163c..00000000000 --- a/sys/gnu/dts/arm/ls1021a.dtsi +++ /dev/null @@ -1,1006 +0,0 @@ -/* - * Copyright 2013-2014 Freescale Semiconductor, Inc. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include -#include - -/ { - #address-cells = <2>; - #size-cells = <2>; - compatible = "fsl,ls1021a"; - interrupt-parent = <&gic>; - - aliases { - crypto = &crypto; - ethernet0 = &enet0; - ethernet1 = &enet1; - ethernet2 = &enet2; - serial0 = &lpuart0; - serial1 = &lpuart1; - serial2 = &lpuart2; - serial3 = &lpuart3; - serial4 = &lpuart4; - serial5 = &lpuart5; - sysclk = &sysclk; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@f00 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <0xf00>; - clocks = <&clockgen 1 0>; - #cooling-cells = <2>; - }; - - cpu1: cpu@f01 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <0xf01>; - clocks = <&clockgen 1 0>; - #cooling-cells = <2>; - }; - }; - - memory { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x0>; - }; - - sysclk: sysclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - clock-output-names = "sysclk"; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; - }; - - pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts = , - ; - interrupt-affinity = <&cpu0>, <&cpu1>; - }; - - reboot { - compatible = "syscon-reboot"; - regmap = <&dcfg>; - offset = <0xb0>; - mask = <0x02>; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - device_type = "soc"; - interrupt-parent = <&gic>; - ranges; - - ddr: memory-controller@1080000 { - compatible = "fsl,qoriq-memory-controller"; - reg = <0x0 0x1080000 0x0 0x1000>; - interrupts = ; - big-endian; - }; - - gic: interrupt-controller@1400000 { - compatible = "arm,gic-400", "arm,cortex-a7-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x0 0x1401000 0x0 0x1000>, - <0x0 0x1402000 0x0 0x2000>, - <0x0 0x1404000 0x0 0x2000>, - <0x0 0x1406000 0x0 0x2000>; - interrupts = ; - - }; - - msi1: msi-controller@1570e00 { - compatible = "fsl,ls1021a-msi"; - reg = <0x0 0x1570e00 0x0 0x8>; - msi-controller; - interrupts = ; - }; - - msi2: msi-controller@1570e08 { - compatible = "fsl,ls1021a-msi"; - reg = <0x0 0x1570e08 0x0 0x8>; - msi-controller; - interrupts = ; - }; - - ifc: ifc@1530000 { - compatible = "fsl,ifc", "simple-bus"; - reg = <0x0 0x1530000 0x0 0x10000>; - interrupts = ; - }; - - dcfg: dcfg@1ee0000 { - compatible = "fsl,ls1021a-dcfg", "syscon"; - reg = <0x0 0x1ee0000 0x0 0x10000>; - big-endian; - }; - - qspi: spi@1550000 { - compatible = "fsl,ls1021a-qspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x1550000 0x0 0x10000>, - <0x0 0x40000000 0x0 0x40000000>; - reg-names = "QuadSPI", "QuadSPI-memory"; - interrupts = ; - clock-names = "qspi_en", "qspi"; - clocks = <&clockgen 4 1>, <&clockgen 4 1>; - status = "disabled"; - }; - - esdhc: esdhc@1560000 { - compatible = "fsl,ls1021a-esdhc", "fsl,esdhc"; - reg = <0x0 0x1560000 0x0 0x10000>; - interrupts = ; - clock-frequency = <0>; - voltage-ranges = <1800 1800 3300 3300>; - sdhci,auto-cmd12; - big-endian; - bus-width = <4>; - status = "disabled"; - }; - - sata: sata@3200000 { - compatible = "fsl,ls1021a-ahci"; - reg = <0x0 0x3200000 0x0 0x10000>, - <0x0 0x20220520 0x0 0x4>; - reg-names = "ahci", "sata-ecc"; - interrupts = ; - clocks = <&clockgen 4 1>; - dma-coherent; - status = "disabled"; - }; - - scfg: scfg@1570000 { - compatible = "fsl,ls1021a-scfg", "syscon"; - reg = <0x0 0x1570000 0x0 0x10000>; - big-endian; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x1570000 0x10000>; - - extirq: interrupt-controller@1ac { - compatible = "fsl,ls1021a-extirq"; - #interrupt-cells = <2>; - #address-cells = <0>; - interrupt-controller; - reg = <0x1ac 4>; - interrupt-map = - <0 0 &gic GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, - <1 0 &gic GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, - <2 0 &gic GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, - <3 0 &gic GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, - <4 0 &gic GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, - <5 0 &gic GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; - interrupt-map-mask = <0xffffffff 0x0>; - }; - }; - - crypto: crypto@1700000 { - compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; - fsl,sec-era = <7>; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x0 0x1700000 0x0 0x100000>; - ranges = <0x0 0x0 0x1700000 0x100000>; - interrupts = ; - - sec_jr0: jr@10000 { - compatible = "fsl,sec-v5.0-job-ring", - "fsl,sec-v4.0-job-ring"; - reg = <0x10000 0x10000>; - interrupts = ; - }; - - sec_jr1: jr@20000 { - compatible = "fsl,sec-v5.0-job-ring", - "fsl,sec-v4.0-job-ring"; - reg = <0x20000 0x10000>; - interrupts = ; - }; - - sec_jr2: jr@30000 { - compatible = "fsl,sec-v5.0-job-ring", - "fsl,sec-v4.0-job-ring"; - reg = <0x30000 0x10000>; - interrupts = ; - }; - - sec_jr3: jr@40000 { - compatible = "fsl,sec-v5.0-job-ring", - "fsl,sec-v4.0-job-ring"; - reg = <0x40000 0x10000>; - interrupts = ; - }; - - }; - - clockgen: clocking@1ee1000 { - compatible = "fsl,ls1021a-clockgen"; - reg = <0x0 0x1ee1000 0x0 0x1000>; - #clock-cells = <2>; - clocks = <&sysclk>; - }; - - tmu: tmu@1f00000 { - compatible = "fsl,qoriq-tmu"; - reg = <0x0 0x1f00000 0x0 0x10000>; - interrupts = ; - fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x30061>; - fsl,tmu-calibration = <0x00000000 0x0000000f - 0x00000001 0x00000017 - 0x00000002 0x0000001e - 0x00000003 0x00000026 - 0x00000004 0x0000002e - 0x00000005 0x00000035 - 0x00000006 0x0000003d - 0x00000007 0x00000044 - 0x00000008 0x0000004c - 0x00000009 0x00000053 - 0x0000000a 0x0000005b - 0x0000000b 0x00000064 - - 0x00010000 0x00000011 - 0x00010001 0x0000001c - 0x00010002 0x00000024 - 0x00010003 0x0000002b - 0x00010004 0x00000034 - 0x00010005 0x00000039 - 0x00010006 0x00000042 - 0x00010007 0x0000004c - 0x00010008 0x00000051 - 0x00010009 0x0000005a - 0x0001000a 0x00000063 - - 0x00020000 0x00000013 - 0x00020001 0x00000019 - 0x00020002 0x00000024 - 0x00020003 0x0000002c - 0x00020004 0x00000035 - 0x00020005 0x0000003d - 0x00020006 0x00000046 - 0x00020007 0x00000050 - 0x00020008 0x00000059 - - 0x00030000 0x00000002 - 0x00030001 0x0000000d - 0x00030002 0x00000019 - 0x00030003 0x00000024>; - #thermal-sensor-cells = <1>; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <1000>; - polling-delay = <5000>; - - thermal-sensors = <&tmu 0>; - - trips { - cpu_alert: cpu-alert { - temperature = <85000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu_crit: cpu-crit { - temperature = <95000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu_alert>; - cooling-device = - <&cpu0 THERMAL_NO_LIMIT - THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT - THERMAL_NO_LIMIT>; - }; - }; - }; - }; - - dspi0: spi@2100000 { - compatible = "fsl,ls1021a-v1.0-dspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2100000 0x0 0x10000>; - interrupts = ; - clock-names = "dspi"; - clocks = <&clockgen 4 1>; - spi-num-chipselects = <6>; - big-endian; - status = "disabled"; - }; - - dspi1: spi@2110000 { - compatible = "fsl,ls1021a-v1.0-dspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2110000 0x0 0x10000>; - interrupts = ; - clock-names = "dspi"; - clocks = <&clockgen 4 1>; - spi-num-chipselects = <6>; - big-endian; - status = "disabled"; - }; - - i2c0: i2c@2180000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2180000 0x0 0x10000>; - interrupts = ; - clock-names = "i2c"; - clocks = <&clockgen 4 1>; - dma-names = "tx", "rx"; - dmas = <&edma0 1 39>, <&edma0 1 38>; - status = "disabled"; - }; - - i2c1: i2c@2190000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2190000 0x0 0x10000>; - interrupts = ; - clock-names = "i2c"; - clocks = <&clockgen 4 1>; - dma-names = "tx", "rx"; - dmas = <&edma0 1 37>, <&edma0 1 36>; - status = "disabled"; - }; - - i2c2: i2c@21a0000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x21a0000 0x0 0x10000>; - interrupts = ; - clock-names = "i2c"; - clocks = <&clockgen 4 1>; - dma-names = "tx", "rx"; - dmas = <&edma0 1 35>, <&edma0 1 34>; - status = "disabled"; - }; - - uart0: serial@21c0500 { - compatible = "fsl,16550-FIFO64", "ns16550a"; - reg = <0x0 0x21c0500 0x0 0x100>; - interrupts = ; - clock-frequency = <0>; - fifo-size = <15>; - status = "disabled"; - }; - - uart1: serial@21c0600 { - compatible = "fsl,16550-FIFO64", "ns16550a"; - reg = <0x0 0x21c0600 0x0 0x100>; - interrupts = ; - clock-frequency = <0>; - fifo-size = <15>; - status = "disabled"; - }; - - uart2: serial@21d0500 { - compatible = "fsl,16550-FIFO64", "ns16550a"; - reg = <0x0 0x21d0500 0x0 0x100>; - interrupts = ; - clock-frequency = <0>; - fifo-size = <15>; - status = "disabled"; - }; - - uart3: serial@21d0600 { - compatible = "fsl,16550-FIFO64", "ns16550a"; - reg = <0x0 0x21d0600 0x0 0x100>; - interrupts = ; - clock-frequency = <0>; - fifo-size = <15>; - status = "disabled"; - }; - - counter0: counter@29d0000 { - compatible = "fsl,ftm-quaddec"; - reg = <0x0 0x29d0000 0x0 0x10000>; - big-endian; - status = "disabled"; - }; - - counter1: counter@29e0000 { - compatible = "fsl,ftm-quaddec"; - reg = <0x0 0x29e0000 0x0 0x10000>; - big-endian; - status = "disabled"; - }; - - counter2: counter@29f0000 { - compatible = "fsl,ftm-quaddec"; - reg = <0x0 0x29f0000 0x0 0x10000>; - big-endian; - status = "disabled"; - }; - - counter3: counter@2a00000 { - compatible = "fsl,ftm-quaddec"; - reg = <0x0 0x2a00000 0x0 0x10000>; - big-endian; - status = "disabled"; - }; - - gpio0: gpio@2300000 { - compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio"; - reg = <0x0 0x2300000 0x0 0x10000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio@2310000 { - compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio"; - reg = <0x0 0x2310000 0x0 0x10000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@2320000 { - compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio"; - reg = <0x0 0x2320000 0x0 0x10000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio@2330000 { - compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio"; - reg = <0x0 0x2330000 0x0 0x10000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - lpuart0: serial@2950000 { - compatible = "fsl,ls1021a-lpuart"; - reg = <0x0 0x2950000 0x0 0x1000>; - interrupts = ; - clocks = <&sysclk>; - clock-names = "ipg"; - status = "disabled"; - }; - - lpuart1: serial@2960000 { - compatible = "fsl,ls1021a-lpuart"; - reg = <0x0 0x2960000 0x0 0x1000>; - interrupts = ; - clocks = <&clockgen 4 1>; - clock-names = "ipg"; - status = "disabled"; - }; - - lpuart2: serial@2970000 { - compatible = "fsl,ls1021a-lpuart"; - reg = <0x0 0x2970000 0x0 0x1000>; - interrupts = ; - clocks = <&clockgen 4 1>; - clock-names = "ipg"; - status = "disabled"; - }; - - lpuart3: serial@2980000 { - compatible = "fsl,ls1021a-lpuart"; - reg = <0x0 0x2980000 0x0 0x1000>; - interrupts = ; - clocks = <&clockgen 4 1>; - clock-names = "ipg"; - status = "disabled"; - }; - - lpuart4: serial@2990000 { - compatible = "fsl,ls1021a-lpuart"; - reg = <0x0 0x2990000 0x0 0x1000>; - interrupts = ; - clocks = <&clockgen 4 1>; - clock-names = "ipg"; - status = "disabled"; - }; - - lpuart5: serial@29a0000 { - compatible = "fsl,ls1021a-lpuart"; - reg = <0x0 0x29a0000 0x0 0x1000>; - interrupts = ; - clocks = <&clockgen 4 1>; - clock-names = "ipg"; - status = "disabled"; - }; - - pwm0: pwm@29d0000 { - compatible = "fsl,vf610-ftm-pwm"; - #pwm-cells = <3>; - reg = <0x0 0x29d0000 0x0 0x10000>; - clock-names = "ftm_sys", "ftm_ext", - "ftm_fix", "ftm_cnt_clk_en"; - clocks = <&clockgen 4 1>, <&clockgen 4 1>, - <&clockgen 4 1>, <&clockgen 4 1>; - big-endian; - status = "disabled"; - }; - - pwm1: pwm@29e0000 { - compatible = "fsl,vf610-ftm-pwm"; - #pwm-cells = <3>; - reg = <0x0 0x29e0000 0x0 0x10000>; - clock-names = "ftm_sys", "ftm_ext", - "ftm_fix", "ftm_cnt_clk_en"; - clocks = <&clockgen 4 1>, <&clockgen 4 1>, - <&clockgen 4 1>, <&clockgen 4 1>; - big-endian; - status = "disabled"; - }; - - pwm2: pwm@29f0000 { - compatible = "fsl,vf610-ftm-pwm"; - #pwm-cells = <3>; - reg = <0x0 0x29f0000 0x0 0x10000>; - clock-names = "ftm_sys", "ftm_ext", - "ftm_fix", "ftm_cnt_clk_en"; - clocks = <&clockgen 4 1>, <&clockgen 4 1>, - <&clockgen 4 1>, <&clockgen 4 1>; - big-endian; - status = "disabled"; - }; - - pwm3: pwm@2a00000 { - compatible = "fsl,vf610-ftm-pwm"; - #pwm-cells = <3>; - reg = <0x0 0x2a00000 0x0 0x10000>; - clock-names = "ftm_sys", "ftm_ext", - "ftm_fix", "ftm_cnt_clk_en"; - clocks = <&clockgen 4 1>, <&clockgen 4 1>, - <&clockgen 4 1>, <&clockgen 4 1>; - big-endian; - status = "disabled"; - }; - - pwm4: pwm@2a10000 { - compatible = "fsl,vf610-ftm-pwm"; - #pwm-cells = <3>; - reg = <0x0 0x2a10000 0x0 0x10000>; - clock-names = "ftm_sys", "ftm_ext", - "ftm_fix", "ftm_cnt_clk_en"; - clocks = <&clockgen 4 1>, <&clockgen 4 1>, - <&clockgen 4 1>, <&clockgen 4 1>; - big-endian; - status = "disabled"; - }; - - pwm5: pwm@2a20000 { - compatible = "fsl,vf610-ftm-pwm"; - #pwm-cells = <3>; - reg = <0x0 0x2a20000 0x0 0x10000>; - clock-names = "ftm_sys", "ftm_ext", - "ftm_fix", "ftm_cnt_clk_en"; - clocks = <&clockgen 4 1>, <&clockgen 4 1>, - <&clockgen 4 1>, <&clockgen 4 1>; - big-endian; - status = "disabled"; - }; - - pwm6: pwm@2a30000 { - compatible = "fsl,vf610-ftm-pwm"; - #pwm-cells = <3>; - reg = <0x0 0x2a30000 0x0 0x10000>; - clock-names = "ftm_sys", "ftm_ext", - "ftm_fix", "ftm_cnt_clk_en"; - clocks = <&clockgen 4 1>, <&clockgen 4 1>, - <&clockgen 4 1>, <&clockgen 4 1>; - big-endian; - status = "disabled"; - }; - - pwm7: pwm@2a40000 { - compatible = "fsl,vf610-ftm-pwm"; - #pwm-cells = <3>; - reg = <0x0 0x2a40000 0x0 0x10000>; - clock-names = "ftm_sys", "ftm_ext", - "ftm_fix", "ftm_cnt_clk_en"; - clocks = <&clockgen 4 1>, <&clockgen 4 1>, - <&clockgen 4 1>, <&clockgen 4 1>; - big-endian; - status = "disabled"; - }; - - wdog0: watchdog@2ad0000 { - compatible = "fsl,imx21-wdt"; - reg = <0x0 0x2ad0000 0x0 0x10000>; - interrupts = ; - clocks = <&clockgen 4 1>; - clock-names = "wdog-en"; - big-endian; - }; - - sai1: sai@2b50000 { - #sound-dai-cells = <0>; - compatible = "fsl,vf610-sai"; - reg = <0x0 0x2b50000 0x0 0x10000>; - interrupts = ; - clocks = <&clockgen 4 1>, <&clockgen 4 1>, - <&clockgen 4 1>, <&clockgen 4 1>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dma-names = "tx", "rx"; - dmas = <&edma0 1 47>, - <&edma0 1 46>; - status = "disabled"; - }; - - sai2: sai@2b60000 { - #sound-dai-cells = <0>; - compatible = "fsl,vf610-sai"; - reg = <0x0 0x2b60000 0x0 0x10000>; - interrupts = ; - clocks = <&clockgen 4 1>, <&clockgen 4 1>, - <&clockgen 4 1>, <&clockgen 4 1>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dma-names = "tx", "rx"; - dmas = <&edma0 1 45>, - <&edma0 1 44>; - status = "disabled"; - }; - - edma0: edma@2c00000 { - #dma-cells = <2>; - compatible = "fsl,vf610-edma"; - reg = <0x0 0x2c00000 0x0 0x10000>, - <0x0 0x2c10000 0x0 0x10000>, - <0x0 0x2c20000 0x0 0x10000>; - interrupts = , - ; - interrupt-names = "edma-tx", "edma-err"; - dma-channels = <32>; - big-endian; - clock-names = "dmamux0", "dmamux1"; - clocks = <&clockgen 4 1>, - <&clockgen 4 1>; - }; - - dcu: dcu@2ce0000 { - compatible = "fsl,ls1021a-dcu"; - reg = <0x0 0x2ce0000 0x0 0x10000>; - interrupts = ; - clocks = <&clockgen 4 0>, - <&clockgen 4 0>; - clock-names = "dcu", "pix"; - big-endian; - status = "disabled"; - }; - - mdio0: mdio@2d24000 { - compatible = "gianfar"; - device_type = "mdio"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2d24000 0x0 0x4000>, - <0x0 0x2d10030 0x0 0x4>; - }; - - mdio1: mdio@2d64000 { - compatible = "gianfar"; - device_type = "mdio"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2d64000 0x0 0x4000>, - <0x0 0x2d50030 0x0 0x4>; - }; - - ptp_clock@2d10e00 { - compatible = "fsl,etsec-ptp"; - reg = <0x0 0x2d10e00 0x0 0xb0>; - interrupts = ; - fsl,tclk-period = <5>; - fsl,tmr-prsc = <2>; - fsl,tmr-add = <0xaaaaaaab>; - fsl,tmr-fiper1 = <999999995>; - fsl,tmr-fiper2 = <99990>; - fsl,max-adj = <499999999>; - fsl,extts-fifo; - }; - - enet0: ethernet@2d10000 { - compatible = "fsl,etsec2"; - device_type = "network"; - #address-cells = <2>; - #size-cells = <2>; - interrupt-parent = <&gic>; - model = "eTSEC"; - fsl,magic-packet; - ranges; - dma-coherent; - - queue-group@2d10000 { - #address-cells = <2>; - #size-cells = <2>; - reg = <0x0 0x2d10000 0x0 0x1000>; - interrupts = , - , - ; - }; - - queue-group@2d14000 { - #address-cells = <2>; - #size-cells = <2>; - reg = <0x0 0x2d14000 0x0 0x1000>; - interrupts = , - , - ; - }; - }; - - enet1: ethernet@2d50000 { - compatible = "fsl,etsec2"; - device_type = "network"; - #address-cells = <2>; - #size-cells = <2>; - interrupt-parent = <&gic>; - model = "eTSEC"; - ranges; - dma-coherent; - - queue-group@2d50000 { - #address-cells = <2>; - #size-cells = <2>; - reg = <0x0 0x2d50000 0x0 0x1000>; - interrupts = , - , - ; - }; - - queue-group@2d54000 { - #address-cells = <2>; - #size-cells = <2>; - reg = <0x0 0x2d54000 0x0 0x1000>; - interrupts = , - , - ; - }; - }; - - enet2: ethernet@2d90000 { - compatible = "fsl,etsec2"; - device_type = "network"; - #address-cells = <2>; - #size-cells = <2>; - interrupt-parent = <&gic>; - model = "eTSEC"; - ranges; - dma-coherent; - - queue-group@2d90000 { - #address-cells = <2>; - #size-cells = <2>; - reg = <0x0 0x2d90000 0x0 0x1000>; - interrupts = , - , - ; - }; - - queue-group@2d94000 { - #address-cells = <2>; - #size-cells = <2>; - reg = <0x0 0x2d94000 0x0 0x1000>; - interrupts = , - , - ; - }; - }; - - usb2: usb@8600000 { - compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr"; - reg = <0x0 0x8600000 0x0 0x1000>; - interrupts = ; - dr_mode = "host"; - phy_type = "ulpi"; - }; - - usb3: usb3@3100000 { - compatible = "snps,dwc3"; - reg = <0x0 0x3100000 0x0 0x10000>; - interrupts = ; - dr_mode = "host"; - snps,quirk-frame-length-adjustment = <0x20>; - snps,dis_rxdet_inp3_quirk; - snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; - }; - - pcie@3400000 { - compatible = "fsl,ls1021a-pcie"; - reg = <0x00 0x03400000 0x0 0x00010000 /* controller registers */ - 0x40 0x00000000 0x0 0x00002000>; /* configuration space */ - reg-names = "regs", "config"; - interrupts = ; /* controller interrupt */ - fsl,pcie-scfg = <&scfg 0>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - num-viewport = <6>; - bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */ - 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ - msi-parent = <&msi1>, <&msi2>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0000 0 0 1 &gic GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 2 &gic GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 3 &gic GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 4 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - pcie@3500000 { - compatible = "fsl,ls1021a-pcie"; - reg = <0x00 0x03500000 0x0 0x00010000 /* controller registers */ - 0x48 0x00000000 0x0 0x00002000>; /* configuration space */ - reg-names = "regs", "config"; - interrupts = ; - fsl,pcie-scfg = <&scfg 1>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - num-viewport = <6>; - bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */ - 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ - msi-parent = <&msi1>, <&msi2>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0000 0 0 1 &gic GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 2 &gic GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 3 &gic GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 4 &gic GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - can0: can@2a70000 { - compatible = "fsl,ls1021ar2-flexcan"; - reg = <0x0 0x2a70000 0x0 0x1000>; - interrupts = ; - clocks = <&clockgen 4 1>, <&clockgen 4 1>; - clock-names = "ipg", "per"; - big-endian; - }; - - can1: can@2a80000 { - compatible = "fsl,ls1021ar2-flexcan"; - reg = <0x0 0x2a80000 0x0 0x1000>; - interrupts = ; - clocks = <&clockgen 4 1>, <&clockgen 4 1>; - clock-names = "ipg", "per"; - big-endian; - }; - - can2: can@2a90000 { - compatible = "fsl,ls1021ar2-flexcan"; - reg = <0x0 0x2a90000 0x0 0x1000>; - interrupts = ; - clocks = <&clockgen 4 1>, <&clockgen 4 1>; - clock-names = "ipg", "per"; - big-endian; - }; - - can3: can@2aa0000 { - compatible = "fsl,ls1021ar2-flexcan"; - reg = <0x0 0x2aa0000 0x0 0x1000>; - interrupts = ; - clocks = <&clockgen 4 1>, <&clockgen 4 1>; - clock-names = "ipg", "per"; - big-endian; - }; - - ocram1: sram@10000000 { - compatible = "mmio-sram"; - reg = <0x0 0x10000000 0x0 0x10000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x10000000 0x10000>; - }; - - ocram2: sram@10010000 { - compatible = "mmio-sram"; - reg = <0x0 0x10010000 0x0 0x10000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x10010000 0x10000>; - }; - - qdma: dma-controller@8390000 { - compatible = "fsl,ls1021a-qdma"; - reg = <0x0 0x8388000 0x0 0x1000>, /* Controller regs */ - <0x0 0x8389000 0x0 0x1000>, /* Status regs */ - <0x0 0x838a000 0x0 0x2000>; /* Block regs */ - interrupts = , - , - ; - interrupt-names = "qdma-error", - "qdma-queue0", "qdma-queue1"; - dma-channels = <8>; - block-number = <1>; - block-offset = <0x1000>; - fsl,dma-queues = <2>; - status-sizes = <64>; - queue-sizes = <64 64>; - big-endian; - }; - - }; -}; diff --git a/sys/gnu/dts/arm/meson.dtsi b/sys/gnu/dts/arm/meson.dtsi deleted file mode 100644 index 5d198309058..00000000000 --- a/sys/gnu/dts/arm/meson.dtsi +++ /dev/null @@ -1,292 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT -/* - * Copyright 2014 Carlo Caione - */ - -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&gic>; - - L2: l2-cache-controller@c4200000 { - compatible = "arm,pl310-cache"; - reg = <0xc4200000 0x1000>; - cache-unified; - cache-level = <2>; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - cbus: cbus@c1100000 { - compatible = "simple-bus"; - reg = <0xc1100000 0x200000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xc1100000 0x200000>; - - hhi: system-controller@4000 { - compatible = "amlogic,meson-hhi-sysctrl", - "simple-mfd", - "syscon"; - reg = <0x4000 0x400>; - }; - - assist: assist@7c00 { - compatible = "amlogic,meson-mx-assist", "syscon"; - reg = <0x7c00 0x200>; - }; - - hwrng: rng@8100 { - compatible = "amlogic,meson-rng"; - reg = <0x8100 0x8>; - }; - - uart_A: serial@84c0 { - compatible = "amlogic,meson6-uart", "amlogic,meson-uart"; - reg = <0x84c0 0x18>; - interrupts = ; - status = "disabled"; - }; - - uart_B: serial@84dc { - compatible = "amlogic,meson6-uart", "amlogic,meson-uart"; - reg = <0x84dc 0x18>; - interrupts = ; - status = "disabled"; - }; - - i2c_A: i2c@8500 { - compatible = "amlogic,meson6-i2c"; - reg = <0x8500 0x20>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - pwm_ab: pwm@8550 { - compatible = "amlogic,meson-pwm"; - reg = <0x8550 0x10>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm_cd: pwm@8650 { - compatible = "amlogic,meson-pwm"; - reg = <0x8650 0x10>; - #pwm-cells = <3>; - status = "disabled"; - }; - - saradc: adc@8680 { - compatible = "amlogic,meson-saradc"; - reg = <0x8680 0x34>; - #io-channel-cells = <1>; - interrupts = ; - status = "disabled"; - }; - - uart_C: serial@8700 { - compatible = "amlogic,meson6-uart", "amlogic,meson-uart"; - reg = <0x8700 0x18>; - interrupts = ; - status = "disabled"; - }; - - i2c_B: i2c@87c0 { - compatible = "amlogic,meson6-i2c"; - reg = <0x87c0 0x20>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - usb0_phy: phy@8800 { - compatible = "amlogic,meson-mx-usb2-phy"; - #phy-cells = <0>; - reg = <0x8800 0x20>; - status = "disabled"; - }; - - usb1_phy: phy@8820 { - compatible = "amlogic,meson-mx-usb2-phy"; - #phy-cells = <0>; - reg = <0x8820 0x20>; - status = "disabled"; - }; - - sdio: mmc@8c20 { - compatible = "amlogic,meson-mx-sdio"; - reg = <0x8c20 0x20>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spifc: spi@8c80 { - compatible = "amlogic,meson6-spifc"; - reg = <0x8c80 0x80>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - gpio_intc: interrupt-controller@9880 { - compatible = "amlogic,meson-gpio-intc"; - reg = <0x9880 0x10>; - interrupt-controller; - #interrupt-cells = <2>; - amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>; - status = "disabled"; - }; - - wdt: watchdog@9900 { - compatible = "amlogic,meson6-wdt"; - reg = <0x9900 0x8>; - interrupts = ; - }; - - timer_abcde: timer@9940 { - compatible = "amlogic,meson6-timer"; - reg = <0x9940 0x18>; - interrupts = , - , - , - ; - }; - }; - - periph: bus@c4300000 { - compatible = "simple-bus"; - reg = <0xc4300000 0x10000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xc4300000 0x10000>; - - gic: interrupt-controller@1000 { - compatible = "arm,cortex-a9-gic"; - reg = <0x1000 0x1000>, - <0x100 0x100>; - interrupt-controller; - #interrupt-cells = <3>; - }; - }; - - aobus: aobus@c8100000 { - compatible = "simple-bus"; - reg = <0xc8100000 0x100000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xc8100000 0x100000>; - - ir_receiver: ir-receiver@480 { - compatible= "amlogic,meson6-ir"; - reg = <0x480 0x20>; - interrupts = ; - status = "disabled"; - }; - - uart_AO: serial@4c0 { - compatible = "amlogic,meson6-uart", "amlogic,meson-ao-uart", "amlogic,meson-uart"; - reg = <0x4c0 0x18>; - interrupts = ; - status = "disabled"; - }; - - i2c_AO: i2c@500 { - compatible = "amlogic,meson6-i2c"; - reg = <0x500 0x20>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - rtc: rtc@740 { - compatible = "amlogic,meson6-rtc"; - reg = <0x740 0x14>; - interrupts = ; - #address-cells = <1>; - #size-cells = <1>; - status = "disabled"; - }; - }; - - usb0: usb@c9040000 { - compatible = "snps,dwc2"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xc9040000 0x40000>; - interrupts = ; - phys = <&usb0_phy>; - phy-names = "usb2-phy"; - dr_mode = "host"; - status = "disabled"; - }; - - usb1: usb@c90c0000 { - compatible = "snps,dwc2"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xc90c0000 0x40000>; - interrupts = ; - phys = <&usb1_phy>; - phy-names = "usb2-phy"; - dr_mode = "host"; - status = "disabled"; - }; - - ethmac: ethernet@c9410000 { - compatible = "amlogic,meson6-dwmac", "snps,dwmac"; - reg = <0xc9410000 0x10000 - 0xc1108108 0x4>; - interrupts = ; - interrupt-names = "macirq"; - status = "disabled"; - }; - - ahb_sram: sram@d9000000 { - compatible = "mmio-sram"; - reg = <0xd9000000 0x20000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0xd9000000 0x20000>; - }; - - bootrom: bootrom@d9040000 { - compatible = "amlogic,meson-mx-bootrom", "syscon"; - reg = <0xd9040000 0x10000>; - }; - - secbus: secbus@da000000 { - compatible = "simple-bus"; - reg = <0xda000000 0x6000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xda000000 0x6000>; - - efuse: nvmem@0 { - compatible = "amlogic,meson6-efuse"; - reg = <0x0 0x2000>; - #address-cells = <1>; - #size-cells = <1>; - }; - }; - }; - - xtal: xtal-clk { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "xtal"; - #clock-cells = <0>; - }; -}; /* end of / */ diff --git a/sys/gnu/dts/arm/meson6-atv1200.dts b/sys/gnu/dts/arm/meson6-atv1200.dts deleted file mode 100644 index 98e1c94c026..00000000000 --- a/sys/gnu/dts/arm/meson6-atv1200.dts +++ /dev/null @@ -1,33 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT -/* - * Copyright 2014 Carlo Caione - */ - -/dts-v1/; -#include "meson6.dtsi" - -/ { - model = "Geniatech ATV1200"; - compatible = "geniatech,atv1200", "amlogic,meson6"; - - aliases { - serial0 = &uart_AO; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - device_type = "memory"; - reg = <0x40000000 0x80000000>; - }; -}; - -&uart_AO { - status = "okay"; -}; - -ðmac { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/meson6.dtsi b/sys/gnu/dts/arm/meson6.dtsi deleted file mode 100644 index 4716030a48d..00000000000 --- a/sys/gnu/dts/arm/meson6.dtsi +++ /dev/null @@ -1,73 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT -/* - * Copyright 2014 Carlo Caione - */ - -#include "meson.dtsi" - -/ { - model = "Amlogic Meson6 SoC"; - compatible = "amlogic,meson6"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@200 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - next-level-cache = <&L2>; - reg = <0x200>; - }; - - cpu@201 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - next-level-cache = <&L2>; - reg = <0x201>; - }; - }; - - apb2: bus@d0000000 { - compatible = "simple-bus"; - reg = <0xd0000000 0x40000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xd0000000 0x40000>; - }; - - clk81: clk@0 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <200000000>; - }; -}; /* end of / */ - -&efuse { - status = "disabled"; -}; - -&timer_abcde { - clocks = <&xtal>, <&clk81>; - clock-names = "xtal", "pclk"; -}; - -&uart_AO { - clocks = <&xtal>, <&clk81>, <&clk81>; - clock-names = "xtal", "pclk", "baud"; -}; - -&uart_A { - clocks = <&xtal>, <&clk81>, <&clk81>; - clock-names = "xtal", "pclk", "baud"; -}; - -&uart_B { - clocks = <&xtal>, <&clk81>, <&clk81>; - clock-names = "xtal", "pclk", "baud"; -}; - -&uart_C { - clocks = <&xtal>, <&clk81>, <&clk81>; - clock-names = "xtal", "pclk", "baud"; -}; diff --git a/sys/gnu/dts/arm/meson8-minix-neo-x8.dts b/sys/gnu/dts/arm/meson8-minix-neo-x8.dts deleted file mode 100644 index 61ec929ab86..00000000000 --- a/sys/gnu/dts/arm/meson8-minix-neo-x8.dts +++ /dev/null @@ -1,97 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT -/* - * Copyright 2014 Beniamino Galvani - */ - -/dts-v1/; -#include -#include "meson8.dtsi" - -/ { - model = "MINIX NEO-X8"; - compatible = "minix,neo-x8", "amlogic,meson8"; - - aliases { - serial0 = &uart_AO; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - device_type = "memory"; - reg = <0x40000000 0x80000000>; - }; - - gpio-leds { - compatible = "gpio-leds"; - - blue { - label = "x8:blue:power"; - gpios = <&gpio_ao GPIO_TEST_N GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -&i2c_AO { - status = "okay"; - pinctrl-0 = <&i2c_ao_pins>; - pinctrl-names = "default"; - - pmic@32 { - compatible = "ricoh,rn5t618"; - reg = <0x32>; - system-power-controller; - - regulators { - }; - }; - - rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; -}; - -&spifc { - status = "okay"; - pinctrl-0 = <&spi_nor_pins>; - pinctrl-names = "default"; - - spi-flash@0 { - compatible = "mxicy,mx25l1606e"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0>; - spi-max-frequency = <30000000>; - - partition@0 { - label = "boot"; - reg = <0x0 0x100000>; - }; - - partition@100000 { - label = "env"; - reg = <0x100000 0x10000>; - }; - }; -}; - -&ir_receiver { - status = "okay"; - pinctrl-0 = <&ir_recv_pins>; - pinctrl-names = "default"; -}; - -ðmac { - status = "okay"; - pinctrl-0 = <ð_pins>; - pnictrl-names = "default"; -}; diff --git a/sys/gnu/dts/arm/meson8.dtsi b/sys/gnu/dts/arm/meson8.dtsi deleted file mode 100644 index eedb9252696..00000000000 --- a/sys/gnu/dts/arm/meson8.dtsi +++ /dev/null @@ -1,613 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT -/* - * Copyright 2014 Carlo Caione - */ - -#include -#include -#include -#include -#include -#include "meson.dtsi" - -/ { - model = "Amlogic Meson8 SoC"; - compatible = "amlogic,meson8"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@200 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - next-level-cache = <&L2>; - reg = <0x200>; - enable-method = "amlogic,meson8-smp"; - resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPUCLK>; - }; - - cpu1: cpu@201 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - next-level-cache = <&L2>; - reg = <0x201>; - enable-method = "amlogic,meson8-smp"; - resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPUCLK>; - }; - - cpu2: cpu@202 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - next-level-cache = <&L2>; - reg = <0x202>; - enable-method = "amlogic,meson8-smp"; - resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPUCLK>; - }; - - cpu3: cpu@203 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - next-level-cache = <&L2>; - reg = <0x203>; - enable-method = "amlogic,meson8-smp"; - resets = <&clkc CLKC_RESET_CPU3_SOFT_RESET>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPUCLK>; - }; - }; - - cpu_opp_table: opp-table { - compatible = "operating-points-v2"; - opp-shared; - - opp-96000000 { - opp-hz = /bits/ 64 <96000000>; - opp-microvolt = <825000>; - }; - opp-192000000 { - opp-hz = /bits/ 64 <192000000>; - opp-microvolt = <825000>; - }; - opp-312000000 { - opp-hz = /bits/ 64 <312000000>; - opp-microvolt = <825000>; - }; - opp-408000000 { - opp-hz = /bits/ 64 <408000000>; - opp-microvolt = <825000>; - }; - opp-504000000 { - opp-hz = /bits/ 64 <504000000>; - opp-microvolt = <825000>; - }; - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <850000>; - }; - opp-720000000 { - opp-hz = /bits/ 64 <720000000>; - opp-microvolt = <850000>; - }; - opp-816000000 { - opp-hz = /bits/ 64 <816000000>; - opp-microvolt = <875000>; - }; - opp-1008000000 { - opp-hz = /bits/ 64 <1008000000>; - opp-microvolt = <925000>; - }; - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <975000>; - }; - opp-1416000000 { - opp-hz = /bits/ 64 <1416000000>; - opp-microvolt = <1025000>; - }; - opp-1608000000 { - opp-hz = /bits/ 64 <1608000000>; - opp-microvolt = <1100000>; - }; - opp-1800000000 { - status = "disabled"; - opp-hz = /bits/ 64 <1800000000>; - opp-microvolt = <1125000>; - }; - opp-1992000000 { - status = "disabled"; - opp-hz = /bits/ 64 <1992000000>; - opp-microvolt = <1150000>; - }; - }; - - gpu_opp_table: gpu-opp-table { - compatible = "operating-points-v2"; - - opp-182142857 { - opp-hz = /bits/ 64 <182142857>; - opp-microvolt = <1150000>; - }; - opp-318750000 { - opp-hz = /bits/ 64 <318750000>; - opp-microvolt = <1150000>; - }; - opp-425000000 { - opp-hz = /bits/ 64 <425000000>; - opp-microvolt = <1150000>; - }; - opp-510000000 { - opp-hz = /bits/ 64 <510000000>; - opp-microvolt = <1150000>; - }; - opp-637500000 { - opp-hz = /bits/ 64 <637500000>; - opp-microvolt = <1150000>; - turbo-mode; - }; - }; - - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts = , - , - , - ; - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - /* 2 MiB reserved for Hardware ROM Firmware? */ - hwrom@0 { - reg = <0x0 0x200000>; - no-map; - }; - - /* - * 1 MiB reserved for the "ARM Power Firmware": this is ARM - * code which is responsible for system suspend. It loads a - * piece of ARC code ("arc_power" in the vendor u-boot tree) - * into SRAM, executes that and shuts down the (last) ARM core. - * The arc_power firmware then checks various wakeup sources - * (IR remote receiver, HDMI CEC, WIFI and Bluetooth wakeup or - * simply the power key) and re-starts the ARM core once it - * detects a wakeup request. - */ - power-firmware@4f00000 { - reg = <0x4f00000 0x100000>; - no-map; - }; - }; - - mmcbus: bus@c8000000 { - compatible = "simple-bus"; - reg = <0xc8000000 0x8000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xc8000000 0x8000>; - - ddr_clkc: clock-controller@400 { - compatible = "amlogic,meson8-ddr-clkc"; - reg = <0x400 0x20>; - clocks = <&xtal>; - clock-names = "xtal"; - #clock-cells = <1>; - }; - - dmcbus: bus@6000 { - compatible = "simple-bus"; - reg = <0x6000 0x400>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x6000 0x400>; - - canvas: video-lut@20 { - compatible = "amlogic,meson8-canvas", - "amlogic,canvas"; - reg = <0x20 0x14>; - }; - }; - }; - - apb: bus@d0000000 { - compatible = "simple-bus"; - reg = <0xd0000000 0x200000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xd0000000 0x200000>; - - mali: gpu@c0000 { - compatible = "amlogic,meson8-mali", "arm,mali-450"; - reg = <0xc0000 0x40000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "gp", "gpmmu", "pp", "pmu", - "pp0", "ppmmu0", "pp1", "ppmmu1", - "pp2", "ppmmu2", "pp4", "ppmmu4", - "pp5", "ppmmu5", "pp6", "ppmmu6"; - resets = <&reset RESET_MALI>; - clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>; - clock-names = "bus", "core"; - operating-points-v2 = <&gpu_opp_table>; - }; - }; -}; /* end of / */ - -&aobus { - pmu: pmu@e0 { - compatible = "amlogic,meson8-pmu", "syscon"; - reg = <0xe0 0x18>; - }; - - pinctrl_aobus: pinctrl@84 { - compatible = "amlogic,meson8-aobus-pinctrl"; - reg = <0x84 0xc>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gpio_ao: ao-bank@14 { - reg = <0x14 0x4>, - <0x2c 0x4>, - <0x24 0x8>; - reg-names = "mux", "pull", "gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl_aobus 0 0 16>; - }; - - uart_ao_a_pins: uart_ao_a { - mux { - groups = "uart_tx_ao_a", "uart_rx_ao_a"; - function = "uart_ao"; - bias-disable; - }; - }; - - i2c_ao_pins: i2c_mst_ao { - mux { - groups = "i2c_mst_sck_ao", "i2c_mst_sda_ao"; - function = "i2c_mst_ao"; - bias-disable; - }; - }; - - ir_recv_pins: remote { - mux { - groups = "remote_input"; - function = "remote"; - bias-disable; - }; - }; - - pwm_f_ao_pins: pwm-f-ao { - mux { - groups = "pwm_f_ao"; - function = "pwm_f_ao"; - bias-disable; - }; - }; - }; -}; - -&cbus { - reset: reset-controller@4404 { - compatible = "amlogic,meson8b-reset"; - reg = <0x4404 0x9c>; - #reset-cells = <1>; - }; - - analog_top: analog-top@81a8 { - compatible = "amlogic,meson8-analog-top", "syscon"; - reg = <0x81a8 0x14>; - }; - - pwm_ef: pwm@86c0 { - compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm"; - reg = <0x86c0 0x10>; - #pwm-cells = <3>; - status = "disabled"; - }; - - clock-measure@8758 { - compatible = "amlogic,meson8-clk-measure"; - reg = <0x8758 0x1c>; - }; - - pinctrl_cbus: pinctrl@9880 { - compatible = "amlogic,meson8-cbus-pinctrl"; - reg = <0x9880 0x10>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gpio: banks@80b0 { - reg = <0x80b0 0x28>, - <0x80e8 0x18>, - <0x8120 0x18>, - <0x8030 0x30>; - reg-names = "mux", "pull", "pull-enable", "gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl_cbus 0 0 120>; - }; - - sd_a_pins: sd-a { - mux { - groups = "sd_d0_a", "sd_d1_a", "sd_d2_a", - "sd_d3_a", "sd_clk_a", "sd_cmd_a"; - function = "sd_a"; - bias-disable; - }; - }; - - sd_b_pins: sd-b { - mux { - groups = "sd_d0_b", "sd_d1_b", "sd_d2_b", - "sd_d3_b", "sd_clk_b", "sd_cmd_b"; - function = "sd_b"; - bias-disable; - }; - }; - - sd_c_pins: sd-c { - mux { - groups = "sd_d0_c", "sd_d1_c", "sd_d2_c", - "sd_d3_c", "sd_clk_c", "sd_cmd_c"; - function = "sd_c"; - bias-disable; - }; - }; - - spi_nor_pins: nor { - mux { - groups = "nor_d", "nor_q", "nor_c", "nor_cs"; - function = "nor"; - bias-disable; - }; - }; - - eth_pins: ethernet { - mux { - groups = "eth_tx_clk_50m", "eth_tx_en", - "eth_txd1", "eth_txd0", - "eth_rx_clk_in", "eth_rx_dv", - "eth_rxd1", "eth_rxd0", "eth_mdio", - "eth_mdc"; - function = "ethernet"; - bias-disable; - }; - }; - - pwm_e_pins: pwm-e { - mux { - groups = "pwm_e"; - function = "pwm_e"; - bias-disable; - }; - }; - - uart_a1_pins: uart-a1 { - mux { - groups = "uart_tx_a1", - "uart_rx_a1"; - function = "uart_a"; - bias-disable; - }; - }; - - uart_a1_cts_rts_pins: uart-a1-cts-rts { - mux { - groups = "uart_cts_a1", - "uart_rts_a1"; - function = "uart_a"; - bias-disable; - }; - }; - }; -}; - -&ahb_sram { - smp-sram@1ff80 { - compatible = "amlogic,meson8-smp-sram"; - reg = <0x1ff80 0x8>; - }; -}; - -&efuse { - compatible = "amlogic,meson8-efuse"; - clocks = <&clkc CLKID_EFUSE>; - clock-names = "core"; - - temperature_calib: calib@1f4 { - /* only the upper two bytes are relevant */ - reg = <0x1f4 0x4>; - }; -}; - -ðmac { - clocks = <&clkc CLKID_ETH>; - clock-names = "stmmaceth"; -}; - -&gpio_intc { - compatible = "amlogic,meson8-gpio-intc", "amlogic,meson-gpio-intc"; - status = "okay"; -}; - -&hhi { - clkc: clock-controller { - compatible = "amlogic,meson8-clkc"; - clocks = <&xtal>, <&ddr_clkc DDR_CLKID_DDR_PLL>; - clock-names = "xtal", "ddr_pll"; - #clock-cells = <1>; - #reset-cells = <1>; - }; -}; - -&hwrng { - compatible = "amlogic,meson8-rng", "amlogic,meson-rng"; - clocks = <&clkc CLKID_RNG0>; - clock-names = "core"; -}; - -&i2c_AO { - clocks = <&clkc CLKID_CLK81>; -}; - -&i2c_A { - clocks = <&clkc CLKID_CLK81>; -}; - -&i2c_B { - clocks = <&clkc CLKID_CLK81>; -}; - -&L2 { - arm,data-latency = <3 3 3>; - arm,tag-latency = <2 2 2>; - arm,filter-ranges = <0x100000 0xc0000000>; - prefetch-data = <1>; - prefetch-instr = <1>; - arm,shared-override; -}; - -&periph { - scu@0 { - compatible = "arm,cortex-a9-scu"; - reg = <0x0 0x100>; - }; - - timer@200 { - compatible = "arm,cortex-a9-global-timer"; - reg = <0x200 0x20>; - interrupts = ; - clocks = <&clkc CLKID_PERIPH>; - - /* - * the arm_global_timer driver currently does not handle clock - * rate changes. Keep it disabled for now. - */ - status = "disabled"; - }; - - timer@600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0x600 0x20>; - interrupts = ; - clocks = <&clkc CLKID_PERIPH>; - }; -}; - -&pwm_ab { - compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm"; -}; - -&pwm_cd { - compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm"; -}; - -&rtc { - compatible = "amlogic,meson8-rtc"; - resets = <&reset RESET_RTC>; -}; - -&saradc { - compatible = "amlogic,meson8-saradc", "amlogic,meson-saradc"; - clocks = <&xtal>, <&clkc CLKID_SAR_ADC>; - clock-names = "clkin", "core"; - amlogic,hhi-sysctrl = <&hhi>; - nvmem-cells = <&temperature_calib>; - nvmem-cell-names = "temperature_calib"; -}; - -&sdio { - compatible = "amlogic,meson8-sdio", "amlogic,meson-mx-sdio"; - clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>; - clock-names = "core", "clkin"; -}; - -&spifc { - clocks = <&clkc CLKID_CLK81>; -}; - -&timer_abcde { - clocks = <&xtal>, <&clkc CLKID_CLK81>; - clock-names = "xtal", "pclk"; -}; - -&uart_AO { - compatible = "amlogic,meson8-uart", "amlogic,meson-uart"; - clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_CLK81>; - clock-names = "baud", "xtal", "pclk"; -}; - -&uart_A { - compatible = "amlogic,meson8-uart", "amlogic,meson-uart"; - clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART0>; - clock-names = "baud", "xtal", "pclk"; -}; - -&uart_B { - compatible = "amlogic,meson8-uart", "amlogic,meson-uart"; - clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART1>; - clock-names = "baud", "xtal", "pclk"; -}; - -&uart_C { - compatible = "amlogic,meson8-uart", "amlogic,meson-uart"; - clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART2>; - clock-names = "baud", "xtal", "pclk"; -}; - -&usb0 { - compatible = "amlogic,meson8-usb", "snps,dwc2"; - clocks = <&clkc CLKID_USB0_DDR_BRIDGE>; - clock-names = "otg"; -}; - -&usb1 { - compatible = "amlogic,meson8-usb", "snps,dwc2"; - clocks = <&clkc CLKID_USB1_DDR_BRIDGE>; - clock-names = "otg"; -}; - -&usb0_phy { - compatible = "amlogic,meson8-usb2-phy", "amlogic,meson-mx-usb2-phy"; - clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>; - clock-names = "usb_general", "usb"; - resets = <&reset RESET_USB_OTG>; -}; - -&usb1_phy { - compatible = "amlogic,meson8-usb2-phy", "amlogic,meson-mx-usb2-phy"; - clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>; - clock-names = "usb_general", "usb"; - resets = <&reset RESET_USB_OTG>; -}; diff --git a/sys/gnu/dts/arm/meson8b-ec100.dts b/sys/gnu/dts/arm/meson8b-ec100.dts deleted file mode 100644 index 163a200d5a7..00000000000 --- a/sys/gnu/dts/arm/meson8b-ec100.dts +++ /dev/null @@ -1,415 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2018 Martin Blumenstingl . - */ - -/dts-v1/; - -#include -#include - -#include "meson8b.dtsi" - -/ { - model = "Endless Computers Endless Mini"; - compatible = "endless,ec100", "amlogic,meson8b"; - - aliases { - serial0 = &uart_AO; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - device_type = "memory"; - reg = <0x40000000 0x40000000>; - }; - - gpio-keys { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <100>; - - pal-switch { - label = "pal"; - linux,input-type = ; - linux,code = ; - gpios = <&gpio GPIOH_7 GPIO_ACTIVE_LOW>; - }; - - ntsc-switch { - label = "ntsc"; - linux,input-type = ; - linux,code = ; - gpios = <&gpio GPIOH_8 GPIO_ACTIVE_HIGH>; - }; - - power-button { - label = "power"; - linux,code = ; - gpios = <&gpio GPIOH_9 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-poweroff { - compatible = "gpio-poweroff"; - /* - * shutdown is managed by the EC (embedded micro-controller) - * which is configured through GPIOAO_2 (poweroff GPIO) and - * GPIOAO_7 (power LED, which has to go LOW as well). - */ - gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>; - timeout-ms = <20000>; - }; - - iio-hwmon { - compatible = "iio-hwmon"; - io-channels = <&saradc 8>; - }; - - leds { - compatible = "gpio-leds"; - - power { - label = "ec100:red:power"; - /* - * Needs to go LOW (together with the poweroff GPIO) - * during shutdown to allow the EC (embedded - * micro-controller) to shutdown the system. Setting - * the output to LOW signals the EC to start a - * "breathing"/pulsing effect until the power is fully - * turned off. - */ - gpios = <&gpio_ao GPIOAO_7 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; - - rtc32k_xtal: rtc32k-xtal-clk { - /* X2 in the schematics */ - compatible = "fixed-clock"; - clock-frequency = <32768>; - clock-output-names = "RTC32K"; - #clock-cells = <0>; - }; - - usb_vbus: regulator-usb-vbus { - /* - * Silergy SY6288CCAC-GP 2A Power Distribution Switch. - */ - compatible = "regulator-fixed"; - - regulator-name = "USB_VBUS"; - - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - vin-supply = <&vcc_5v>; - - /* - * signal name from the schematics: USB_PWR_EN - */ - gpio = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vcc_5v: regulator-vcc5v { - /* - * supplied by the main power input which called PWR_5V_STB - * in the schematics - */ - compatible = "regulator-fixed"; - - regulator-name = "VCC5V"; - - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - /* - * signal name from the schematics: 3V3_5V_EN - */ - gpio = <&gpio GPIODV_29 GPIO_ACTIVE_LOW>; - - regulator-boot-on; - regulator-always-on; - }; - - vcck: regulator-vcck { - /* - * Silergy SY8089AAC-GP 2A continuous, 3A peak, 1MHz - * Synchronous Step Down Regulator. - */ - compatible = "pwm-regulator"; - - regulator-name = "VCCK"; - regulator-min-microvolt = <860000>; - regulator-max-microvolt = <1140000>; - - vin-supply = <&vcc_5v>; - - pwms = <&pwm_cd 0 1148 0>; - pwm-dutycycle-range = <100 0>; - - regulator-boot-on; - regulator-always-on; - }; - - vcc_1v8: regulator-vcc1v8 { - /* - * ABLIC S-1339D18-M5001-GP - */ - compatible = "regulator-fixed"; - - regulator-name = "VCC1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - vin-supply = <&vcc_3v3>; - }; - - vcc_3v3: regulator-vcc3v3 { - /* - * Silergy SY8089AAC-GP 2A continuous, 3A peak, 1MHz - * Synchronous Step Down Regulator. Also called - * VDDIO_AO3.3V in the schematics. - */ - compatible = "regulator-fixed"; - - regulator-name = "VCC3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - vin-supply = <&vcc_5v>; - }; - - vcc_ddr3: regulator-vcc-ddr3 { - /* - * Silergy SY8089AAC-GP 2A continuous, 3A peak, 1MHz - * Synchronous Step Down Regulator. Also called - * DDR3_1.5V in the schematics. - */ - compatible = "regulator-fixed"; - - regulator-name = "VCC_DDR3_1V5"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - - vin-supply = <&vcc_5v>; - - regulator-boot-on; - regulator-always-on; - }; - - vcc_rtc: regulator-vcc-rtc { - /* - * Global Mixed-mode Technology Inc. G918T12U-GP - */ - compatible = "regulator-fixed"; - - regulator-name = "VCC_RTC"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - - /* - * When the board is powered then the input is VCC3V3, - * otherwise power is taken from the coin cell battery. - */ - vin-supply = <&vcc_3v3>; - }; - - vddee: regulator-vddee { - /* - * Silergy SY8089AAC-GP 2A continuous, 3A peak, 1MHz - * Synchronous Step Down Regulator. Also called VDDAO - * in a part of the schematics. - */ - compatible = "pwm-regulator"; - - regulator-name = "VDDEE"; - regulator-min-microvolt = <860000>; - regulator-max-microvolt = <1140000>; - - vin-supply = <&vcc_5v>; - - pwms = <&pwm_cd 1 1148 0>; - pwm-dutycycle-range = <100 0>; - - regulator-boot-on; - regulator-always-on; - }; -}; - -&cpu0 { - cpu-supply = <&vcck>; -}; - -ðmac { - status = "okay"; - - pinctrl-0 = <ð_rmii_pins>; - pinctrl-names = "default"; - - phy-handle = <ð_phy0>; - phy-mode = "rmii"; - - mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - eth_phy0: ethernet-phy@0 { - /* IC Plus IP101A/G (0x02430c54) */ - reg = <0>; - - reset-assert-us = <10000>; - reset-deassert-us = <10000>; - reset-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_LOW>; - - icplus,select-interrupt; - interrupt-parent = <&gpio_intc>; - /* GPIOH_3 */ - interrupts = <17 IRQ_TYPE_LEVEL_LOW>; - }; - }; -}; - -&i2c_A { - status = "okay"; - pinctrl-0 = <&i2c_a_pins>; - pinctrl-names = "default"; - - rt5640: codec@1c { - compatible = "realtek,rt5640"; - reg = <0x1c>; - interrupt-parent = <&gpio_intc>; - interrupts = <13 IRQ_TYPE_EDGE_BOTH>; /* GPIOAO_13 */ - realtek,in1-differential; - }; -}; - -&mali { - mali-supply = <&vddee>; -}; - -&saradc { - status = "okay"; - vref-supply = <&vcc_1v8>; -}; - -&sdio { - status = "okay"; - - pinctrl-0 = <&sd_b_pins>; - pinctrl-names = "default"; - - /* SD card */ - sd_card_slot: slot@1 { - compatible = "mmc-slot"; - reg = <1>; - status = "okay"; - - bus-width = <4>; - no-sdio; - cap-mmc-highspeed; - cap-sd-highspeed; - disable-wp; - - cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; - - vmmc-supply = <&vcc_3v3>; - }; -}; - -&gpio_ao { - gpio-line-names = "Linux_TX", "Linux_RX", - "SLP_S5_N", "USB2_OC_FLAG#", - "HUB_RST", "USB_PWR_EN", - "I2S_IN", "SLP_S1_N", - "TCK", "TMS", "TDI", "TDO", - "HDMI_CEC", "5640_IRQ", - "MUTE", "S805_TEST#"; -}; - -&gpio { - gpio-line-names = /* Bank GPIOX */ - "WIFI_SD_D0", "WIFI_SD_D1", "WIFI_SD_D2", - "WIFI_SD_D3", "BTPCM_DOUT", "BTPCM_DIN", - "BTPCM_SYNC", "BTPCM_CLK", "WIFI_SD_CLK", - "WIFI_SD_CMD", "WIFI_32K", "WIFI_PWREN", - "UART_B_TX", "UART_B_RX", "UART_B_CTS_N", - "UART_B_RTS_N", "BT_EN", "WIFI_WAKE_HOST", - /* Bank GPIOY */ - "", "", "", "", "", "", "", "", "", "", - "", "", - /* Bank GPIODV */ - "VCCK_PWM_C", "I2C_SDA_A", "I2C_SCL_A", - "I2C_SDA_B", "I2C_SCL_B", "VDDEE_PWM_D", - "VDDEE_PWM 3V3_5V_EN", - /* Bank GPIOH */ - "HDMI_HPD", "HDMI_I2C_SDA", "HDMI_I2C_SCL", - "RMII_IRQ", "RMII_RST#", "RMII_TXD1", - "RMII_TXD0", "AV_select_1", "AV_select_2", - "MCU_Control_S", - /* Bank CARD */ - "SD_D1_B", "SD_D0_B", "SD_CLK_8726MX", - "SD_CMD_8726MX", "SD_D3_B", "SD_D2_B", - "CARD_EN_DET (CARD_DET)", - /* Bank BOOT */ - "NAND_D0 (EMMC)", "NAND_D1 (EMMC)", - "NAND_D2 (EMMC)", "NAND_D3 (EMMC)", - "NAND_D4 (EMMC)", "NAND_D5 (EMMC)", - "NAND_D6 (EMMC)", "NAND_D7 (EMMC)", - "NAND_CS1 (EMMC)", "NAND_CS2 iNAND_RS1 (EMMC)", - "NAND_nR/B iNAND_CMD (EMMC)", "NAND_ALE (EMMC)", - "NAND_CLE (EMMC)", "nRE_S1 NAND_nRE (EMMC)", - "nWE_S1 NAND_nWE (EMMC)", "", "", "SPI_CS", - /* Bank DIF */ - "RMII_RXD1", "RMII_RXD0", "RMII_CRS_DV", - "RMII_50M_IN", "GPIODIF_4", "GPIODIF_5", - "RMII_TXEN", "CPUETH_25MOUT", "RMII_MDC", - "RMII_MDIO"; -}; - -&pwm_cd { - status = "okay"; - pinctrl-0 = <&pwm_c1_pins>, <&pwm_d_pins>; - pinctrl-names = "default"; - clocks = <&xtal>, <&xtal>; - clock-names = "clkin0", "clkin1"; -}; - -&rtc { - status = "okay"; - clocks = <&rtc32k_xtal>; - vdd-supply = <&vcc_rtc>; -}; - -/* exposed through the pin headers labeled "URDUG1" on the top of the PCB */ -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -/* - * connected to the Bluetooth part of the RTL8723BS SDIO wifi / Bluetooth - * combo chip. This is only available on the variant with 2GB RAM. - */ -&uart_B { - status = "okay"; - pinctrl-0 = <&uart_b0_pins>, <&uart_b0_cts_rts_pins>; - pinctrl-names = "default"; - uart-has-rtscts; -}; - -&usb1 { - status = "okay"; - vbus-supply = <&usb_vbus>; -}; - -&usb1_phy { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/meson8b-mxq.dts b/sys/gnu/dts/arm/meson8b-mxq.dts deleted file mode 100644 index 33037ef62d0..00000000000 --- a/sys/gnu/dts/arm/meson8b-mxq.dts +++ /dev/null @@ -1,192 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT -/* - * Copyright 2015 Endless Mobile, Inc. - * Author: Carlo Caione - */ - -/dts-v1/; - -#include - -#include "meson8b.dtsi" - -/ { - model = "TRONFY MXQ S805"; - compatible = "tronfy,mxq", "amlogic,meson8b"; - - aliases { - serial0 = &uart_AO; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - device_type = "memory"; - reg = <0x40000000 0x40000000>; - }; - - iio-hwmon { - compatible = "iio-hwmon"; - io-channels = <&saradc 8>; - }; - - vcck: regulator-vcck { - compatible = "pwm-regulator"; - - regulator-name = "VCCK"; - regulator-min-microvolt = <860000>; - regulator-max-microvolt = <1140000>; - - pwms = <&pwm_cd 0 1148 0>; - pwm-dutycycle-range = <100 0>; - - regulator-boot-on; - regulator-always-on; - }; - - vcc_1v8: regulator-vcc1v8 { - compatible = "regulator-fixed"; - - regulator-name = "VCC1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - vin-supply = <&vcc_3v3>; - }; - - vcc_3v3: regulator-vcc3v3 { - compatible = "regulator-fixed"; - - regulator-name = "VCC3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - vin-supply = <&vcc_5v>; - }; - - vcc_5v: regulator-vcc5v { - compatible = "regulator-fixed"; - - regulator-name = "VCC5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - regulator-boot-on; - regulator-always-on; - }; - - vddee: regulator-vddee { - compatible = "pwm-regulator"; - - regulator-name = "VDDEE"; - regulator-min-microvolt = <860000>; - regulator-max-microvolt = <1140000>; - - vin-supply = <&vcc_5v>; - - pwms = <&pwm_cd 1 1148 0>; - pwm-dutycycle-range = <100 0>; - - regulator-boot-on; - regulator-always-on; - }; -}; - -&cpu0 { - cpu-supply = <&vcck>; -}; - -ðmac { - status = "okay"; - - pinctrl-0 = <ð_rmii_pins>; - pinctrl-names = "default"; - - phy-handle = <ð_phy0>; - phy-mode = "rmii"; - - mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - eth_phy0: ethernet-phy@0 { - /* IC Plus IP101A/G (0x02430c54) */ - reg = <0>; - - reset-assert-us = <10000>; - reset-deassert-us = <10000>; - reset-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_LOW>; - - icplus,select-interrupt; - interrupt-parent = <&gpio_intc>; - /* GPIOH_3 */ - interrupts = <17 IRQ_TYPE_LEVEL_LOW>; - }; - }; -}; - -&mali { - mali-supply = <&vddee>; -}; - -&saradc { - status = "okay"; - vref-supply = <&vcc_1v8>; -}; - -&sdio { - status = "okay"; - - pinctrl-0 = <&sd_b_pins>; - pinctrl-names = "default"; - - /* SD card */ - sd_card_slot: slot@1 { - compatible = "mmc-slot"; - reg = <1>; - status = "okay"; - - bus-width = <4>; - no-sdio; - cap-mmc-highspeed; - cap-sd-highspeed; - disable-wp; - - cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; - - vmmc-supply = <&vcc_3v3>; - }; -}; - -&pwm_cd { - status = "okay"; - pinctrl-0 = <&pwm_c1_pins>, <&pwm_d_pins>; - pinctrl-names = "default"; - clocks = <&xtal>, <&xtal>; - clock-names = "clkin0", "clkin1"; -}; - -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -&usb0 { - status = "okay"; -}; - -&usb0_phy { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; - -&usb1_phy { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/meson8b-odroidc1.dts b/sys/gnu/dts/arm/meson8b-odroidc1.dts deleted file mode 100644 index a2a47804fc4..00000000000 --- a/sys/gnu/dts/arm/meson8b-odroidc1.dts +++ /dev/null @@ -1,365 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT -/* - * Copyright 2015 Endless Mobile, Inc. - * Author: Carlo Caione - */ - -/dts-v1/; -#include "meson8b.dtsi" -#include - -/ { - model = "Hardkernel ODROID-C1"; - compatible = "hardkernel,odroid-c1", "amlogic,meson8b"; - - aliases { - serial0 = &uart_AO; - mmc0 = &sd_card_slot; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - device_type = "memory"; - reg = <0x40000000 0x40000000>; - }; - - leds { - compatible = "gpio-leds"; - blue { - label = "c1:blue:alive"; - gpios = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - }; - - p5v0: regulator-p5v0 { - compatible = "regulator-fixed"; - - regulator-name = "P5V0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - tflash_vdd: regulator-tflash_vdd { - /* - * signal name from schematics: TFLASH_VDD_EN - */ - compatible = "regulator-fixed"; - - regulator-name = "TFLASH_VDD"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - vin-supply = <&vcc_3v3>; - - gpio = <&gpio GPIOY_12 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - tf_io: gpio-regulator-tf_io { - compatible = "regulator-gpio"; - - regulator-name = "TF_IO"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - vin-supply = <&vcc_3v3>; - - /* - * signal name from schematics: TF_3V3N_1V8_EN - */ - gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>; - gpios-states = <0>; - - states = <3300000 0 - 1800000 1>; - }; - - iio-hwmon { - compatible = "iio-hwmon"; - io-channels = <&saradc 8>; - }; - - rtc32k_xtal: rtc32k-xtal-clk { - /* X3 in the schematics */ - compatible = "fixed-clock"; - clock-frequency = <32768>; - clock-output-names = "RTC32K"; - #clock-cells = <0>; - }; - - vcc_1v8: regulator-vcc-1v8 { - /* - * RICHTEK RT9179 configured for a fixed output voltage of - * 1.8V. This supplies not only VCC1V8 but also IOREF_1V8 and - * VDD1V8 according to the schematics. - */ - compatible = "regulator-fixed"; - - regulator-name = "VCC1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - vin-supply = <&p5v0>; - }; - - vcc_3v3: regulator-vcc-3v3 { - /* - * Monolithic Power Systems MP2161 configured for a fixed - * output voltage of 3.3V. This supplies not only VCC3V3 but - * also VDD3V3 and VDDIO_AO3V3 according to the schematics. - */ - compatible = "regulator-fixed"; - - regulator-name = "VCC3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - vin-supply = <&p5v0>; - }; - - vcck: regulator-vcck { - /* Monolithic Power Systems MP2161 */ - compatible = "pwm-regulator"; - - regulator-name = "VCCK"; - regulator-min-microvolt = <860000>; - regulator-max-microvolt = <1140000>; - - vin-supply = <&p5v0>; - - pwms = <&pwm_cd 0 12218 0>; - pwm-dutycycle-range = <91 0>; - - regulator-boot-on; - regulator-always-on; - }; - - vddc_ddr: regulator-vddc-ddr { - /* - * Monolithic Power Systems MP2161 configured for a fixed - * output voltage of 1.5V. This supplies not only DDR_VDDC but - * also DDR3_1V5 according to the schematics. - */ - compatible = "regulator-fixed"; - - regulator-name = "DDR_VDDC"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - - vin-supply = <&p5v0>; - }; - - vddee: regulator-vddee { - /* Monolithic Power Systems MP2161 */ - compatible = "pwm-regulator"; - - regulator-name = "VDDEE"; - regulator-min-microvolt = <860000>; - regulator-max-microvolt = <1140000>; - - vin-supply = <&p5v0>; - - pwms = <&pwm_cd 1 12218 0>; - pwm-dutycycle-range = <91 0>; - - regulator-boot-on; - regulator-always-on; - }; - - vdd_rtc: regulator-vdd-rtc { - /* - * Torex Semiconductor XC6215 configured for a fixed output of - * 0.9V. - */ - compatible = "regulator-fixed"; - - regulator-name = "VDD_RTC"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - - vin-supply = <&vcc_3v3>; - }; -}; - -&cpu0 { - cpu-supply = <&vcck>; -}; - -&efuse { - ethernet_mac_address: mac@1b4 { - reg = <0x1b4 0x6>; - }; -}; - -ðmac { - status = "okay"; - - pinctrl-0 = <ð_rgmii_pins>; - pinctrl-names = "default"; - - phy-mode = "rgmii"; - phy-handle = <ð_phy>; - amlogic,tx-delay-ns = <4>; - - nvmem-cells = <ðernet_mac_address>; - nvmem-cell-names = "mac-address"; - - mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - /* Realtek RTL8211F (0x001cc916) */ - eth_phy: ethernet-phy@0 { - reg = <0>; - - reset-assert-us = <10000>; - reset-deassert-us = <30000>; - reset-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_LOW>; - - interrupt-parent = <&gpio_intc>; - /* GPIOH_3 */ - interrupts = <17 IRQ_TYPE_LEVEL_LOW>; - }; - }; -}; - -&gpio { - gpio-line-names = /* Bank GPIOX */ - "J2 Header Pin 35", "J2 Header Pin 36", - "J2 Header Pin 32", "J2 Header Pin 31", - "J2 Header Pin 29", "J2 Header Pin 18", - "J2 Header Pin 22", "J2 Header Pin 16", - "J2 Header Pin 23", "J2 Header Pin 21", - "J2 Header Pin 19", "J2 Header Pin 33", - "J2 Header Pin 8", "J2 Header Pin 10", - "J2 Header Pin 15", "J2 Header Pin 13", - "J2 Header Pin 24", "J2 Header Pin 26", - /* Bank GPIOY */ - "Revision (upper)", "Revision (lower)", - "J2 Header Pin 7", "", "J2 Header Pin 12", - "J2 Header Pin 11", "", "", "", - "TFLASH_VDD_EN", "", "", - /* Bank GPIODV */ - "VCCK_PWM (PWM_C)", "I2CA_SDA", "I2CA_SCL", - "I2CB_SDA", "I2CB_SCL", "VDDEE_PWM (PWM_D)", - "", - /* Bank GPIOH */ - "HDMI_HPD", "HDMI_I2C_SDA", "HDMI_I2C_SCL", - "ETH_PHY_INTR", "ETH_PHY_NRST", "ETH_TXD1", - "ETH_TXD0", "ETH_TXD3", "ETH_TXD2", - "ETH_RGMII_TX_CLK", - /* Bank CARD */ - "SD_DATA1 (SDB_D1)", "SD_DATA0 (SDB_D0)", - "SD_CLK", "SD_CMD", "SD_DATA3 (SDB_D3)", - "SD_DATA2 (SDB_D2)", "SD_CDN (SD_DET_N)", - /* Bank BOOT */ - "SDC_D0 (EMMC)", "SDC_D1 (EMMC)", - "SDC_D2 (EMMC)", "SDC_D3 (EMMC)", - "SDC_D4 (EMMC)", "SDC_D5 (EMMC)", - "SDC_D6 (EMMC)", "SDC_D7 (EMMC)", - "SDC_CLK (EMMC)", "SDC_RSTn (EMMC)", - "SDC_CMD (EMMC)", "BOOT_SEL", "", "", "", - "", "", "", "", - /* Bank DIF */ - "ETH_RXD1", "ETH_RXD0", "ETH_RX_DV", - "RGMII_RX_CLK", "ETH_RXD3", "ETH_RXD2", - "ETH_TXEN", "ETH_PHY_REF_CLK_25MOUT", - "ETH_MDC", "ETH_MDIO"; -}; - -&gpio_ao { - gpio-line-names = "UART TX", "UART RX", "", - "TF_3V3N_1V8_EN", "USB_HUB_RST_N", - "USB_OTG_PWREN", "J7 Header Pin 2", - "IR_IN", "J7 Header Pin 4", - "J7 Header Pin 6", "J7 Header Pin 5", - "J7 Header Pin 7", "HDMI_CEC", - "SYS_LED", "", ""; - - /* - * WARNING: The USB Hub on the Odroid-C1/C1+ needs a reset signal - * to be turned high in order to be detected by the USB Controller. - * This signal should be handled by a USB specific power sequence - * in order to reset the Hub when USB bus is powered down. - */ - usb-hub { - gpio-hog; - gpios = ; - output-high; - line-name = "usb-hub-reset"; - }; -}; - -&ir_receiver { - status = "okay"; - pinctrl-0 = <&ir_recv_pins>; - pinctrl-names = "default"; -}; - -&mali { - mali-supply = <&vddee>; -}; - -&saradc { - status = "okay"; - vref-supply = <&vcc_1v8>; -}; - -&sdio { - status = "okay"; - - pinctrl-0 = <&sd_b_pins>; - pinctrl-names = "default"; - - /* SD card */ - sd_card_slot: slot@1 { - compatible = "mmc-slot"; - reg = <1>; - status = "okay"; - - bus-width = <4>; - no-sdio; - cap-mmc-highspeed; - cap-sd-highspeed; - disable-wp; - - cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; - - vmmc-supply = <&tflash_vdd>; - vqmmc-supply = <&tf_io>; - }; -}; - -&pwm_cd { - status = "okay"; - pinctrl-0 = <&pwm_c1_pins>, <&pwm_d_pins>; - pinctrl-names = "default"; - clocks = <&xtal>, <&xtal>; - clock-names = "clkin0", "clkin1"; -}; - -&rtc { - /* needs to be enabled manually when a battery is connected */ - clocks = <&rtc32k_xtal>; - vdd-supply = <&vdd_rtc>; -}; - -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -&usb1_phy { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/meson8b.dtsi b/sys/gnu/dts/arm/meson8b.dtsi deleted file mode 100644 index e34b039b935..00000000000 --- a/sys/gnu/dts/arm/meson8b.dtsi +++ /dev/null @@ -1,592 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT -/* - * Copyright 2015 Endless Mobile, Inc. - * Author: Carlo Caione - */ - -#include -#include -#include -#include -#include -#include "meson.dtsi" - -/ { - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@200 { - device_type = "cpu"; - compatible = "arm,cortex-a5"; - next-level-cache = <&L2>; - reg = <0x200>; - enable-method = "amlogic,meson8b-smp"; - resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPUCLK>; - }; - - cpu1: cpu@201 { - device_type = "cpu"; - compatible = "arm,cortex-a5"; - next-level-cache = <&L2>; - reg = <0x201>; - enable-method = "amlogic,meson8b-smp"; - resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPUCLK>; - }; - - cpu2: cpu@202 { - device_type = "cpu"; - compatible = "arm,cortex-a5"; - next-level-cache = <&L2>; - reg = <0x202>; - enable-method = "amlogic,meson8b-smp"; - resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPUCLK>; - }; - - cpu3: cpu@203 { - device_type = "cpu"; - compatible = "arm,cortex-a5"; - next-level-cache = <&L2>; - reg = <0x203>; - enable-method = "amlogic,meson8b-smp"; - resets = <&clkc CLKC_RESET_CPU3_SOFT_RESET>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPUCLK>; - }; - }; - - cpu_opp_table: opp-table { - compatible = "operating-points-v2"; - opp-shared; - - opp-96000000 { - opp-hz = /bits/ 64 <96000000>; - opp-microvolt = <860000>; - }; - opp-192000000 { - opp-hz = /bits/ 64 <192000000>; - opp-microvolt = <860000>; - }; - opp-312000000 { - opp-hz = /bits/ 64 <312000000>; - opp-microvolt = <860000>; - }; - opp-408000000 { - opp-hz = /bits/ 64 <408000000>; - opp-microvolt = <860000>; - }; - opp-504000000 { - opp-hz = /bits/ 64 <504000000>; - opp-microvolt = <860000>; - }; - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <860000>; - }; - opp-720000000 { - opp-hz = /bits/ 64 <720000000>; - opp-microvolt = <860000>; - }; - opp-816000000 { - opp-hz = /bits/ 64 <816000000>; - opp-microvolt = <900000>; - }; - opp-1008000000 { - opp-hz = /bits/ 64 <1008000000>; - opp-microvolt = <1140000>; - }; - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <1140000>; - }; - opp-1320000000 { - opp-hz = /bits/ 64 <1320000000>; - opp-microvolt = <1140000>; - }; - opp-1488000000 { - opp-hz = /bits/ 64 <1488000000>; - opp-microvolt = <1140000>; - }; - opp-1536000000 { - opp-hz = /bits/ 64 <1536000000>; - opp-microvolt = <1140000>; - }; - }; - - gpu_opp_table: gpu-opp-table { - compatible = "operating-points-v2"; - - opp-255000000 { - opp-hz = /bits/ 64 <255000000>; - opp-microvolt = <1100000>; - }; - opp-364285714 { - opp-hz = /bits/ 64 <364285714>; - opp-microvolt = <1100000>; - }; - opp-425000000 { - opp-hz = /bits/ 64 <425000000>; - opp-microvolt = <1100000>; - }; - opp-510000000 { - opp-hz = /bits/ 64 <510000000>; - opp-microvolt = <1100000>; - }; - opp-637500000 { - opp-hz = /bits/ 64 <637500000>; - opp-microvolt = <1100000>; - turbo-mode; - }; - }; - - pmu { - compatible = "arm,cortex-a5-pmu"; - interrupts = , - , - , - ; - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - /* 2 MiB reserved for Hardware ROM Firmware? */ - hwrom@0 { - reg = <0x0 0x200000>; - no-map; - }; - }; - - mmcbus: bus@c8000000 { - compatible = "simple-bus"; - reg = <0xc8000000 0x8000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xc8000000 0x8000>; - - ddr_clkc: clock-controller@400 { - compatible = "amlogic,meson8b-ddr-clkc"; - reg = <0x400 0x20>; - clocks = <&xtal>; - clock-names = "xtal"; - #clock-cells = <1>; - }; - - dmcbus: bus@6000 { - compatible = "simple-bus"; - reg = <0x6000 0x400>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x6000 0x400>; - - canvas: video-lut@48 { - compatible = "amlogic,meson8b-canvas", - "amlogic,canvas"; - reg = <0x48 0x14>; - }; - }; - }; - - apb: bus@d0000000 { - compatible = "simple-bus"; - reg = <0xd0000000 0x200000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xd0000000 0x200000>; - - mali: gpu@c0000 { - compatible = "amlogic,meson8b-mali", "arm,mali-450"; - reg = <0xc0000 0x40000>; - interrupts = , - , - , - , - , - , - , - ; - interrupt-names = "gp", "gpmmu", "pp", "pmu", - "pp0", "ppmmu0", "pp1", "ppmmu1"; - resets = <&reset RESET_MALI>; - clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>; - clock-names = "bus", "core"; - operating-points-v2 = <&gpu_opp_table>; - }; - }; -}; /* end of / */ - -&aobus { - pmu: pmu@e0 { - compatible = "amlogic,meson8b-pmu", "syscon"; - reg = <0xe0 0x18>; - }; - - pinctrl_aobus: pinctrl@84 { - compatible = "amlogic,meson8b-aobus-pinctrl"; - reg = <0x84 0xc>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gpio_ao: ao-bank@14 { - reg = <0x14 0x4>, - <0x2c 0x4>, - <0x24 0x8>; - reg-names = "mux", "pull", "gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl_aobus 0 0 16>; - }; - - uart_ao_a_pins: uart_ao_a { - mux { - groups = "uart_tx_ao_a", "uart_rx_ao_a"; - function = "uart_ao"; - bias-disable; - }; - }; - - ir_recv_pins: remote { - mux { - groups = "remote_input"; - function = "remote"; - bias-disable; - }; - }; - }; -}; - -&cbus { - reset: reset-controller@4404 { - compatible = "amlogic,meson8b-reset"; - reg = <0x4404 0x9c>; - #reset-cells = <1>; - }; - - analog_top: analog-top@81a8 { - compatible = "amlogic,meson8b-analog-top", "syscon"; - reg = <0x81a8 0x14>; - }; - - pwm_ef: pwm@86c0 { - compatible = "amlogic,meson8b-pwm"; - reg = <0x86c0 0x10>; - #pwm-cells = <3>; - status = "disabled"; - }; - - clock-measure@8758 { - compatible = "amlogic,meson8b-clk-measure"; - reg = <0x8758 0x1c>; - }; - - pinctrl_cbus: pinctrl@9880 { - compatible = "amlogic,meson8b-cbus-pinctrl"; - reg = <0x9880 0x10>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gpio: banks@80b0 { - reg = <0x80b0 0x28>, - <0x80e8 0x18>, - <0x8120 0x18>, - <0x8030 0x38>; - reg-names = "mux", "pull", "pull-enable", "gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl_cbus 0 0 83>; - }; - - eth_rgmii_pins: eth-rgmii { - mux { - groups = "eth_tx_clk", - "eth_tx_en", - "eth_txd1_0", - "eth_txd0_0", - "eth_rx_clk", - "eth_rx_dv", - "eth_rxd1", - "eth_rxd0", - "eth_mdio_en", - "eth_mdc", - "eth_ref_clk", - "eth_txd2", - "eth_txd3", - "eth_rxd3", - "eth_rxd2"; - function = "ethernet"; - bias-disable; - }; - }; - - eth_rmii_pins: eth-rmii { - mux { - groups = "eth_tx_en", - "eth_txd1_0", - "eth_txd0_0", - "eth_rx_clk", - "eth_rx_dv", - "eth_rxd1", - "eth_rxd0", - "eth_mdio_en", - "eth_mdc"; - function = "ethernet"; - bias-disable; - }; - }; - - i2c_a_pins: i2c-a { - mux { - groups = "i2c_sda_a", "i2c_sck_a"; - function = "i2c_a"; - bias-disable; - }; - }; - - sd_b_pins: sd-b { - mux { - groups = "sd_d0_b", "sd_d1_b", "sd_d2_b", - "sd_d3_b", "sd_clk_b", "sd_cmd_b"; - function = "sd_b"; - bias-disable; - }; - }; - - pwm_c1_pins: pwm-c1 { - mux { - groups = "pwm_c1"; - function = "pwm_c"; - bias-disable; - }; - }; - - pwm_d_pins: pwm-d { - mux { - groups = "pwm_d"; - function = "pwm_d"; - bias-disable; - }; - }; - - uart_b0_pins: uart-b0 { - mux { - groups = "uart_tx_b0", - "uart_rx_b0"; - function = "uart_b"; - bias-disable; - }; - }; - - uart_b0_cts_rts_pins: uart-b0-cts-rts { - mux { - groups = "uart_cts_b0", - "uart_rts_b0"; - function = "uart_b"; - bias-disable; - }; - }; - }; -}; - -&ahb_sram { - smp-sram@1ff80 { - compatible = "amlogic,meson8b-smp-sram"; - reg = <0x1ff80 0x8>; - }; -}; - - -&efuse { - compatible = "amlogic,meson8b-efuse"; - clocks = <&clkc CLKID_EFUSE>; - clock-names = "core"; - - temperature_calib: calib@1f4 { - /* only the upper two bytes are relevant */ - reg = <0x1f4 0x4>; - }; -}; - -ðmac { - compatible = "amlogic,meson8b-dwmac", "snps,dwmac-3.70a", "snps,dwmac"; - - reg = <0xc9410000 0x10000 - 0xc1108140 0x4>; - - clocks = <&clkc CLKID_ETH>, - <&clkc CLKID_MPLL2>, - <&clkc CLKID_MPLL2>; - clock-names = "stmmaceth", "clkin0", "clkin1"; - rx-fifo-depth = <4096>; - tx-fifo-depth = <2048>; - - resets = <&reset RESET_ETHERNET>; - reset-names = "stmmaceth"; -}; - -&gpio_intc { - compatible = "amlogic,meson-gpio-intc", - "amlogic,meson8b-gpio-intc"; - status = "okay"; -}; - -&hhi { - clkc: clock-controller { - compatible = "amlogic,meson8b-clkc"; - clocks = <&xtal>, <&ddr_clkc DDR_CLKID_DDR_PLL>; - clock-names = "xtal", "ddr_pll"; - #clock-cells = <1>; - #reset-cells = <1>; - }; -}; - -&hwrng { - compatible = "amlogic,meson8b-rng", "amlogic,meson-rng"; - clocks = <&clkc CLKID_RNG0>; - clock-names = "core"; -}; - -&i2c_AO { - clocks = <&clkc CLKID_CLK81>; -}; - -&i2c_A { - clocks = <&clkc CLKID_I2C>; -}; - -&i2c_B { - clocks = <&clkc CLKID_I2C>; -}; - -&L2 { - arm,data-latency = <3 3 3>; - arm,tag-latency = <2 2 2>; - arm,filter-ranges = <0x100000 0xc0000000>; - prefetch-data = <1>; - prefetch-instr = <1>; - arm,shared-override; -}; - -&periph { - scu@0 { - compatible = "arm,cortex-a5-scu"; - reg = <0x0 0x100>; - }; - - timer@200 { - compatible = "arm,cortex-a5-global-timer"; - reg = <0x200 0x20>; - interrupts = ; - clocks = <&clkc CLKID_PERIPH>; - - /* - * the arm_global_timer driver currently does not handle clock - * rate changes. Keep it disabled for now. - */ - status = "disabled"; - }; - - timer@600 { - compatible = "arm,cortex-a5-twd-timer"; - reg = <0x600 0x20>; - interrupts = ; - clocks = <&clkc CLKID_PERIPH>; - }; -}; - -&pwm_ab { - compatible = "amlogic,meson8b-pwm"; -}; - -&pwm_cd { - compatible = "amlogic,meson8b-pwm"; -}; - -&rtc { - compatible = "amlogic,meson8b-rtc"; - resets = <&reset RESET_RTC>; -}; - -&saradc { - compatible = "amlogic,meson8b-saradc", "amlogic,meson-saradc"; - clocks = <&xtal>, <&clkc CLKID_SAR_ADC>; - clock-names = "clkin", "core"; - amlogic,hhi-sysctrl = <&hhi>; - nvmem-cells = <&temperature_calib>; - nvmem-cell-names = "temperature_calib"; -}; - -&sdio { - compatible = "amlogic,meson8b-sdio", "amlogic,meson-mx-sdio"; - clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>; - clock-names = "core", "clkin"; -}; - -&timer_abcde { - clocks = <&xtal>, <&clkc CLKID_CLK81>; - clock-names = "xtal", "pclk"; -}; - -&uart_AO { - compatible = "amlogic,meson8b-uart", "amlogic,meson-uart"; - clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_CLK81>; - clock-names = "baud", "xtal", "pclk"; -}; - -&uart_A { - compatible = "amlogic,meson8b-uart", "amlogic,meson-uart"; - clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART0>; - clock-names = "baud", "xtal", "pclk"; -}; - -&uart_B { - compatible = "amlogic,meson8b-uart", "amlogic,meson-uart"; - clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART1>; - clock-names = "baud", "xtal", "pclk"; -}; - -&uart_C { - compatible = "amlogic,meson8b-uart", "amlogic,meson-uart"; - clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART2>; - clock-names = "baud", "xtal", "pclk"; -}; - -&usb0 { - compatible = "amlogic,meson8b-usb", "snps,dwc2"; - clocks = <&clkc CLKID_USB0_DDR_BRIDGE>; - clock-names = "otg"; -}; - -&usb1 { - compatible = "amlogic,meson8b-usb", "snps,dwc2"; - clocks = <&clkc CLKID_USB1_DDR_BRIDGE>; - clock-names = "otg"; -}; - -&usb0_phy { - compatible = "amlogic,meson8b-usb2-phy", "amlogic,meson-mx-usb2-phy"; - clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>; - clock-names = "usb_general", "usb"; - resets = <&reset RESET_USB_OTG>; -}; - -&usb1_phy { - compatible = "amlogic,meson8b-usb2-phy", "amlogic,meson-mx-usb2-phy"; - clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>; - clock-names = "usb_general", "usb"; - resets = <&reset RESET_USB_OTG>; -}; - -&wdt { - compatible = "amlogic,meson8b-wdt"; -}; diff --git a/sys/gnu/dts/arm/meson8m2-mxiii-plus.dts b/sys/gnu/dts/arm/meson8m2-mxiii-plus.dts deleted file mode 100644 index d54477b1001..00000000000 --- a/sys/gnu/dts/arm/meson8m2-mxiii-plus.dts +++ /dev/null @@ -1,254 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2018 Oleg Ivanov - * Copyright (c) 2018 Martin Blumenstingl - */ - -/dts-v1/; - -#include "meson8m2.dtsi" - -#include -#include - -/ { - model = "Tronsmart MXIII Plus"; - compatible = "tronsmart,mxiii-plus", "amlogic,meson8m2"; - - aliases { - ethernet0 = ðmac; - i2c0 = &i2c_AO; - serial0 = &uart_AO; - serial1 = &uart_A; - mmc0 = &sd_card_slot; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - device_type = "memory"; - reg = <0x40000000 0x80000000>; - }; - - adc-keys { - compatible = "adc-keys"; - io-channels = <&saradc 0>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1710000>; - - button-function { - label = "Function"; - linux,code = ; - press-threshold-microvolt = <10000>; - }; - }; - - iio-hwmon { - compatible = "iio-hwmon"; - io-channels = <&saradc 8>; - }; - - vcc_3v3: regulator-vcc3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&cpu0 { - cpu-supply = <&vcck>; -}; - -ðmac { - status = "okay"; - - pinctrl-0 = <ð_rgmii_pins>; - pinctrl-names = "default"; - - phy-handle = <ð_phy0>; - phy-mode = "rgmii"; - - amlogic,tx-delay-ns = <4>; - - mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - eth_phy0: ethernet-phy@0 { - /* Realtek RTL8211F (0x001cc916) */ - reg = <0>; - - reset-assert-us = <10000>; - reset-deassert-us = <30000>; - reset-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&ir_receiver { - status = "okay"; - pinctrl-0 = <&ir_recv_pins>; - pinctrl-names = "default"; -}; - -&i2c_AO { - status = "okay"; - pinctrl-0 = <&i2c_ao_pins>; - pinctrl-names = "default"; - - pmic@32 { - compatible = "ricoh,rn5t618"; - reg = <0x32>; - system-power-controller; - - regulators { - vcck: DCDC1 { - regulator-name = "VCCK"; - regulator-min-microvolt = <825000>; - regulator-max-microvolt = <1150000>; - regulator-boot-on; - regulator-always-on; - }; - - vddee: DCDC2 { - /* the output is also used as VDDAO */ - regulator-name = "VDD_EE"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1150000>; - regulator-boot-on; - regulator-always-on; - }; - - DCDC3 { - regulator-name = "VDD_DDR"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - regulator-always-on; - }; - - LDO1 { - regulator-name = "VDDIO_AO28"; - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - regulator-boot-on; - regulator-always-on; - }; - - vddio_ao1v8: LDO2 { - regulator-name = "VDDIO_AO18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - LDO3 { - regulator-name = "VCC1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - LDO4 { - regulator-name = "VCC2V8"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - regulator-boot-on; - regulator-always-on; - }; - - LDO5 { - regulator-name = "AVDD1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - LDORTC1 { - regulator-name = "VDD_LDO"; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - regulator-boot-on; - regulator-always-on; - }; - - LDORTC2 { - regulator-name = "RTC_0V9"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; -}; - -&mali { - mali-supply = <&vddee>; -}; - -&saradc { - status = "okay"; - vref-supply = <&vddio_ao1v8>; -}; - -&sdio { - status = "okay"; - - pinctrl-0 = <&sd_b_pins>; - pinctrl-names = "default"; - - /* SD card */ - sd_card_slot: slot@1 { - compatible = "mmc-slot"; - reg = <1>; - status = "okay"; - - bus-width = <4>; - no-sdio; - cap-mmc-highspeed; - cap-sd-highspeed; - disable-wp; - - cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; - - vmmc-supply = <&vcc_3v3>; - }; -}; - -/* connected to the Bluetooth module */ -&uart_A { - status = "okay"; - pinctrl-0 = <&uart_a1_pins>, <&uart_a1_cts_rts_pins>; - pinctrl-names = "default"; - uart-has-rtscts; -}; - -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; - -&usb0_phy { - status = "okay"; -}; - -&usb1_phy { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/meson8m2.dtsi b/sys/gnu/dts/arm/meson8m2.dtsi deleted file mode 100644 index 5bde7f50200..00000000000 --- a/sys/gnu/dts/arm/meson8m2.dtsi +++ /dev/null @@ -1,69 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 Martin Blumenstingl . - */ - -#include "meson8.dtsi" - -/ { - model = "Amlogic Meson8m2 SoC"; - compatible = "amlogic,meson8m2"; -}; /* end of / */ - -&clkc { - compatible = "amlogic,meson8m2-clkc", "amlogic,meson8-clkc"; -}; - -&dmcbus { - /* the offset of the canvas registers has changed compared to Meson8 */ - /delete-node/ video-lut@20; - - canvas: video-lut@48 { - compatible = "amlogic,meson8m2-canvas", "amlogic,canvas"; - reg = <0x48 0x14>; - }; -}; - -ðmac { - compatible = "amlogic,meson8m2-dwmac", "snps,dwmac"; - reg = <0xc9410000 0x10000 - 0xc1108140 0x8>; - clocks = <&clkc CLKID_ETH>, - <&clkc CLKID_MPLL2>, - <&clkc CLKID_MPLL2>; - clock-names = "stmmaceth", "clkin0", "clkin1"; - resets = <&reset RESET_ETHERNET>; - reset-names = "stmmaceth"; -}; - -&pinctrl_aobus { - compatible = "amlogic,meson8m2-aobus-pinctrl", - "amlogic,meson8-aobus-pinctrl"; -}; - -&pinctrl_cbus { - compatible = "amlogic,meson8m2-cbus-pinctrl", - "amlogic,meson8-cbus-pinctrl"; - - eth_rgmii_pins: ethernet { - mux { - groups = "eth_tx_clk_50m", "eth_tx_en", - "eth_txd3", "eth_txd2", - "eth_txd1", "eth_txd0", - "eth_rx_clk_in", "eth_rx_dv", - "eth_rxd3", "eth_rxd2", - "eth_rxd1", "eth_rxd0", - "eth_mdio", "eth_mdc"; - function = "ethernet"; - bias-disable; - }; - }; -}; - -&saradc { - compatible = "amlogic,meson8m2-saradc", "amlogic,meson-saradc"; -}; - -&wdt { - compatible = "amlogic,meson8m2-wdt", "amlogic,meson8b-wdt"; -}; diff --git a/sys/gnu/dts/arm/milbeaut-m10v-evb.dts b/sys/gnu/dts/arm/milbeaut-m10v-evb.dts deleted file mode 100644 index 614f60c6b0a..00000000000 --- a/sys/gnu/dts/arm/milbeaut-m10v-evb.dts +++ /dev/null @@ -1,32 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* Socionext Milbeaut M10V Evaluation Board */ -/dts-v1/; -#include "milbeaut-m10v.dtsi" - -/ { - model = "Socionext M10V EVB"; - compatible = "socionext,milbeaut-m10v-evb", "socionext,sc2000a"; - - aliases { - serial0 = &uart1; - }; - - chosen { - bootargs = "rootwait earlycon"; - stdout-path = "serial0:115200n8"; - }; - - clocks { - uclk40xi: uclk40xi { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <40000000>; - }; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x80000000>; - }; - -}; diff --git a/sys/gnu/dts/arm/milbeaut-m10v.dtsi b/sys/gnu/dts/arm/milbeaut-m10v.dtsi deleted file mode 100644 index aa7c6caeb75..00000000000 --- a/sys/gnu/dts/arm/milbeaut-m10v.dtsi +++ /dev/null @@ -1,95 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include -#include -#include -#include - -/ { - compatible = "socionext,sc2000a"; - interrupt-parent = <&gic>; - #address-cells = <1>; - #size-cells = <1>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "socionext,milbeaut-m10v-smp"; - cpu@f00 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0xf00>; - }; - cpu@f01 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0xf01>; - }; - cpu@f02 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0xf02>; - }; - cpu@f03 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0xf03>; - }; - }; - - timer { /* The Generic Timer */ - compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; - clock-frequency = <40000000>; - always-on; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - interrupt-parent = <&gic>; - - gic: interrupt-controller@1d000000 { - compatible = "arm,cortex-a7-gic"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0x1d001000 0x1000>, - <0x1d002000 0x1000>; /* CPU I/f base and size */ - }; - - timer@1e000050 { /* 32-bit Reload Timers */ - compatible = "socionext,milbeaut-timer"; - reg = <0x1e000050 0x20>; - interrupts = <0 91 4>; - }; - - uart1: serial@1e700010 { /* PE4, PE5 */ - /* Enable this as ttyUSI0 */ - compatible = "socionext,milbeaut-usio-uart"; - reg = <0x1e700010 0x10>; - interrupts = <0 141 0x4>, <0 149 0x4>; - interrupt-names = "rx", "tx"; - }; - - }; - - sram@0 { - compatible = "mmio-sram"; - reg = <0x0 0x10000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x0 0x10000>; - smp-sram@f100 { - compatible = "socionext,milbeaut-smp-sram"; - reg = <0xf100 0x20>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/mmp2-brownstone.dts b/sys/gnu/dts/arm/mmp2-brownstone.dts deleted file mode 100644 index aaedc4c742e..00000000000 --- a/sys/gnu/dts/arm/mmp2-brownstone.dts +++ /dev/null @@ -1,194 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Marvell Technology Group Ltd. - * Author: Haojian Zhuang - */ - -/dts-v1/; -#include "mmp2.dtsi" - -/ { - model = "Marvell MMP2 Brownstone Development Board"; - compatible = "mrvl,mmp2-brownstone", "mrvl,mmp2"; - - chosen { - bootargs = "console=ttyS2,38400 root=/dev/nfs nfsroot=192.168.1.100:/nfsroot/ ip=192.168.1.101:192.168.1.100::255.255.255.0::eth0:on"; - }; - - memory { - device_type = "memory"; - reg = <0x00000000 0x08000000>; - }; - - soc { - apb@d4000000 { - uart3: uart@d4018000 { - status = "okay"; - }; - twsi1: i2c@d4011000 { - status = "okay"; - pmic: max8925@3c { - compatible = "maxium,max8925"; - reg = <0x3c>; - interrupts = <1>; - interrupt-parent = <&intcmux4>; - interrupt-controller; - #interrupt-cells = <1>; - maxim,tsc-irq = <0>; - - regulators { - SDV1 { - regulator-min-microvolt = <637500>; - regulator-max-microvolt = <1425000>; - regulator-boot-on; - regulator-always-on; - }; - SDV2 { - regulator-min-microvolt = <650000>; - regulator-max-microvolt = <2225000>; - regulator-boot-on; - regulator-always-on; - }; - SDV3 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3900000>; - regulator-boot-on; - regulator-always-on; - }; - LDO1 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3900000>; - regulator-boot-on; - regulator-always-on; - }; - LDO2 { - regulator-min-microvolt = <650000>; - regulator-max-microvolt = <2250000>; - regulator-boot-on; - regulator-always-on; - }; - LDO3 { - regulator-min-microvolt = <650000>; - regulator-max-microvolt = <2250000>; - regulator-boot-on; - regulator-always-on; - }; - LDO4 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3900000>; - regulator-boot-on; - regulator-always-on; - }; - LDO5 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3900000>; - regulator-boot-on; - regulator-always-on; - }; - LDO6 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3900000>; - regulator-boot-on; - regulator-always-on; - }; - LDO7 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3900000>; - regulator-boot-on; - regulator-always-on; - }; - LDO8 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3900000>; - regulator-boot-on; - regulator-always-on; - }; - LDO9 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3900000>; - regulator-boot-on; - regulator-always-on; - }; - LDO10 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3900000>; - }; - LDO11 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3900000>; - regulator-boot-on; - regulator-always-on; - }; - LDO12 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3900000>; - regulator-boot-on; - regulator-always-on; - }; - LDO13 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3900000>; - regulator-boot-on; - regulator-always-on; - }; - LDO14 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3900000>; - regulator-boot-on; - regulator-always-on; - }; - LDO15 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3900000>; - regulator-boot-on; - regulator-always-on; - }; - LDO16 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3900000>; - regulator-boot-on; - regulator-always-on; - }; - LDO17 { - regulator-min-microvolt = <650000>; - regulator-max-microvolt = <2250000>; - regulator-boot-on; - regulator-always-on; - }; - LDO18 { - regulator-min-microvolt = <650000>; - regulator-max-microvolt = <2250000>; - regulator-boot-on; - regulator-always-on; - }; - LDO19 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3900000>; - regulator-boot-on; - regulator-always-on; - }; - LDO20 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3900000>; - regulator-boot-on; - regulator-always-on; - }; - }; - backlight { - maxim,max8925-dual-string = <0>; - }; - charger { - batt-detect = <0>; - topoff-threshold = <1>; - fast-charge = <7>; - no-temp-support = <0>; - no-insert-detect = <0>; - }; - }; - }; - rtc: rtc@d4010000 { - status = "okay"; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/mmp2-olpc-xo-1-75.dts b/sys/gnu/dts/arm/mmp2-olpc-xo-1-75.dts deleted file mode 100644 index 6cfa0d4a188..00000000000 --- a/sys/gnu/dts/arm/mmp2-olpc-xo-1-75.dts +++ /dev/null @@ -1,244 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * OLPC XO 1.75 Laptop. - * - * Copyright (C) 2018,2019 Lubomir Rintel - */ - -/dts-v1/; -#include "mmp2.dtsi" -#include -#include -#include - -/ { - model = "OLPC XO-1.75"; - compatible = "olpc,xo-1.75", "mrvl,mmp2"; - - chosen { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - framebuffer@1fc00000 { - compatible = "simple-framebuffer"; - reg = <0x1fc00000 (1200 * 900 * 2)>; - width = <1200>; - height = <900>; - stride = <(1200 * 2)>; - format = "r5g6b5"; - clocks = <&soc_clocks MMP2_CLK_DISP0_LCDC>, - <&soc_clocks MMP2_CLK_DISP0>; - }; - }; - - memory { - linux,usable-memory = <0x0 0x1f800000>; - available = <0xcf000 0x1ef31000 0x1000 0xbf000>; - reg = <0x0 0x20000000>; - device_type = "memory"; - }; - - gpio-keys { - compatible = "gpio-keys"; - - lid { - label = "Lid"; - gpios = <&gpio 129 GPIO_ACTIVE_LOW>; - linux,input-type = ; - linux,code = ; - wakeup-source; - }; - - tablet_mode { - label = "E-Book Mode"; - gpios = <&gpio 128 GPIO_ACTIVE_LOW>; - linux,input-type = ; - linux,code = ; - wakeup-source; - }; - - microphone_insert { - label = "Microphone Plug"; - gpios = <&gpio 96 GPIO_ACTIVE_HIGH>; - linux,input-type = ; - linux,code = ; - debounce-interval = <100>; - wakeup-source; - }; - - headphone_insert { - label = "Headphone Plug"; - gpios = <&gpio 97 GPIO_ACTIVE_HIGH>; - linux,input-type = ; - linux,code = ; - debounce-interval = <100>; - wakeup-source; - }; - }; - - camera_i2c { - compatible = "i2c-gpio"; - gpios = <&gpio 109 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>, - <&gpio 108 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - #address-cells = <1>; - #size-cells = <0>; - i2c-gpio,timeout-ms = <1000>; - status = "okay"; - - camera@21 { - compatible = "ovti,ov7670"; - reg = <0x21>; - reset-gpios = <&gpio 102 GPIO_ACTIVE_LOW>; - powerdown-gpios = <&gpio 150 GPIO_ACTIVE_LOW>; - clocks = <&camera0>; - clock-names = "xclk"; - - port { - ov7670_0: endpoint { - hsync-active = <1>; - vsync-active = <1>; - remote-endpoint = <&camera0_0>; - }; - }; - }; - }; - - battery { - compatible = "olpc,xo1.5-battery", "olpc,xo1-battery"; - }; - - wlan_reg: fixedregulator0 { - compatible = "regulator-fixed"; - regulator-name = "wlan"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio 34 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - wlan_pwrseq: pwrseq0 { - compatible = "mmc-pwrseq-sd8787"; - powerdown-gpios = <&gpio 57 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio 58 GPIO_ACTIVE_HIGH>; - }; - - soc { - axi@d4200000 { - ap-sp@d4290000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "olpc,ap-sp"; - interrupts = <40>; - reg = <0xd4290000 0x1000>; - data-gpios = <&gpio 72 GPIO_ACTIVE_HIGH>; - clk-gpios = <&gpio 71 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - }; - }; -}; - -&uart3 { - status = "okay"; -}; - -&uart4 { - status = "okay"; -}; - -&rtc { - status = "okay"; -}; - -&usb_phy0 { - status = "okay"; -}; - -&usb_otg0 { - status = "okay"; -}; - -&mmc1 { - clock-frequency = <50000000>; - no-1-8-v; - mrvl,clk-delay-cycles = <31>; - broken-cd; - status = "okay"; -}; - -&mmc2 { - clock-frequency = <50000000>; - no-1-8-v; - bus-width = <4>; - non-removable; - broken-cd; - wakeup-source; - keep-power-in-suspend; - mmc-pwrseq = <&wlan_pwrseq>; - vmmc-supply = <&wlan_reg>; - status = "okay"; -}; - -&mmc3 { - clock-frequency = <50000000>; - no-1-8-v; - bus-width = <8>; - non-removable; - broken-cd; - mrvl,clk-delay-cycles = <31>; - status = "okay"; -}; - -&twsi1 { - status = "okay"; - - audio-codec@1a { - compatible = "realtek,alc5631"; - reg = <0x1a>; - status = "okay"; - }; -}; - -&twsi2 { - status = "okay"; - - rtc@68 { - compatible = "dallas,ds1338"; - reg = <0x68>; - status = "okay"; - }; -}; - -&twsi6 { - status = "okay"; - - accelerometer@1d { - compatible = "st,lis331dlh", "st,lis3lv02d"; - reg = <0x1d>; - status = "okay"; - }; -}; - -&ssp3 { - #address-cells = <0>; - spi-slave; - status = "okay"; - ready-gpio = <&gpio 125 GPIO_ACTIVE_HIGH>; - - slave { - compatible = "olpc,xo1.75-ec"; - spi-cpha; - cmd-gpio = <&gpio 155 GPIO_ACTIVE_HIGH>; - }; -}; - -&camera0 { - status = "okay"; - - port { - camera0_0: endpoint { - remote-endpoint = <&ov7670_0>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/mmp2.dtsi b/sys/gnu/dts/arm/mmp2.dtsi deleted file mode 100644 index 6a2f072c1d0..00000000000 --- a/sys/gnu/dts/arm/mmp2.dtsi +++ /dev/null @@ -1,426 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Marvell Technology Group Ltd. - * Author: Haojian Zhuang - */ - -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - - aliases { - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - serial3 = &uart4; - i2c0 = &twsi1; - i2c1 = &twsi2; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&intc>; - ranges; - - L2: l2-cache { - compatible = "marvell,tauros2-cache"; - marvell,tauros2-cache-features = <0x3>; - }; - - axi@d4200000 { /* AXI */ - compatible = "mrvl,axi-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0xd4200000 0x00200000>; - ranges; - - intc: interrupt-controller@d4282000 { - compatible = "mrvl,mmp2-intc"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0xd4282000 0x1000>; - mrvl,intc-nr-irqs = <64>; - }; - - intcmux4: interrupt-controller@d4282150 { - compatible = "mrvl,mmp2-mux-intc"; - interrupts = <4>; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x150 0x4>, <0x168 0x4>; - reg-names = "mux status", "mux mask"; - mrvl,intc-nr-irqs = <2>; - }; - - intcmux5: interrupt-controller@d4282154 { - compatible = "mrvl,mmp2-mux-intc"; - interrupts = <5>; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x154 0x4>, <0x16c 0x4>; - reg-names = "mux status", "mux mask"; - mrvl,intc-nr-irqs = <2>; - mrvl,clr-mfp-irq = <1>; - }; - - intcmux9: interrupt-controller@d4282180 { - compatible = "mrvl,mmp2-mux-intc"; - interrupts = <9>; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x180 0x4>, <0x17c 0x4>; - reg-names = "mux status", "mux mask"; - mrvl,intc-nr-irqs = <3>; - }; - - intcmux17: interrupt-controller@d4282158 { - compatible = "mrvl,mmp2-mux-intc"; - interrupts = <17>; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x158 0x4>, <0x170 0x4>; - reg-names = "mux status", "mux mask"; - mrvl,intc-nr-irqs = <5>; - }; - - intcmux35: interrupt-controller@d428215c { - compatible = "mrvl,mmp2-mux-intc"; - interrupts = <35>; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x15c 0x4>, <0x174 0x4>; - reg-names = "mux status", "mux mask"; - mrvl,intc-nr-irqs = <15>; - }; - - intcmux51: interrupt-controller@d4282160 { - compatible = "mrvl,mmp2-mux-intc"; - interrupts = <51>; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x160 0x4>, <0x178 0x4>; - reg-names = "mux status", "mux mask"; - mrvl,intc-nr-irqs = <2>; - }; - - intcmux55: interrupt-controller@d4282188 { - compatible = "mrvl,mmp2-mux-intc"; - interrupts = <55>; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x188 0x4>, <0x184 0x4>; - reg-names = "mux status", "mux mask"; - mrvl,intc-nr-irqs = <2>; - }; - - usb_phy0: usb-phy@d4207000 { - compatible = "marvell,mmp2-usb-phy"; - reg = <0xd4207000 0x40>; - #phy-cells = <0>; - status = "disabled"; - }; - - usb_otg0: usb-otg@d4208000 { - compatible = "marvell,pxau2o-ehci"; - reg = <0xd4208000 0x200>; - interrupts = <44>; - clocks = <&soc_clocks MMP2_CLK_USB>; - clock-names = "USBCLK"; - phys = <&usb_phy0>; - phy-names = "usb"; - status = "disabled"; - }; - - mmc1: mmc@d4280000 { - compatible = "mrvl,pxav3-mmc"; - reg = <0xd4280000 0x120>; - clocks = <&soc_clocks MMP2_CLK_SDH0>; - clock-names = "io"; - interrupts = <39>; - status = "disabled"; - }; - - mmc2: mmc@d4280800 { - compatible = "mrvl,pxav3-mmc"; - reg = <0xd4280800 0x120>; - clocks = <&soc_clocks MMP2_CLK_SDH1>; - clock-names = "io"; - interrupts = <52>; - status = "disabled"; - }; - - mmc3: mmc@d4281000 { - compatible = "mrvl,pxav3-mmc"; - reg = <0xd4281000 0x120>; - clocks = <&soc_clocks MMP2_CLK_SDH2>; - clock-names = "io"; - interrupts = <53>; - status = "disabled"; - }; - - mmc4: mmc@d4281800 { - compatible = "mrvl,pxav3-mmc"; - reg = <0xd4281800 0x120>; - clocks = <&soc_clocks MMP2_CLK_SDH3>; - clock-names = "io"; - interrupts = <54>; - status = "disabled"; - }; - - camera0: camera@d420a000 { - compatible = "marvell,mmp2-ccic"; - reg = <0xd420a000 0x800>; - interrupts = <42>; - clocks = <&soc_clocks MMP2_CLK_CCIC0>; - clock-names = "axi"; - #clock-cells = <0>; - clock-output-names = "mclk"; - status = "disabled"; - }; - - camera1: camera@d420a800 { - compatible = "marvell,mmp2-ccic"; - reg = <0xd420a800 0x800>; - interrupts = <30>; - clocks = <&soc_clocks MMP2_CLK_CCIC1>; - clock-names = "axi"; - #clock-cells = <0>; - clock-output-names = "mclk"; - status = "disabled"; - }; - }; - - apb@d4000000 { /* APB */ - compatible = "mrvl,apb-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0xd4000000 0x00200000>; - ranges; - - timer0: timer@d4014000 { - compatible = "mrvl,mmp-timer"; - reg = <0xd4014000 0x100>; - interrupts = <13>; - clocks = <&soc_clocks MMP2_CLK_TIMER>; - }; - - uart1: uart@d4030000 { - compatible = "mrvl,mmp-uart"; - reg = <0xd4030000 0x1000>; - interrupts = <27>; - clocks = <&soc_clocks MMP2_CLK_UART0>; - resets = <&soc_clocks MMP2_CLK_UART0>; - reg-shift = <2>; - status = "disabled"; - }; - - uart2: uart@d4017000 { - compatible = "mrvl,mmp-uart"; - reg = <0xd4017000 0x1000>; - interrupts = <28>; - clocks = <&soc_clocks MMP2_CLK_UART1>; - resets = <&soc_clocks MMP2_CLK_UART1>; - reg-shift = <2>; - status = "disabled"; - }; - - uart3: uart@d4018000 { - compatible = "mrvl,mmp-uart"; - reg = <0xd4018000 0x1000>; - interrupts = <24>; - clocks = <&soc_clocks MMP2_CLK_UART2>; - resets = <&soc_clocks MMP2_CLK_UART2>; - reg-shift = <2>; - status = "disabled"; - }; - - uart4: uart@d4016000 { - compatible = "mrvl,mmp-uart"; - reg = <0xd4016000 0x1000>; - interrupts = <46>; - clocks = <&soc_clocks MMP2_CLK_UART3>; - resets = <&soc_clocks MMP2_CLK_UART3>; - reg-shift = <2>; - status = "disabled"; - }; - - gpio: gpio@d4019000 { - compatible = "marvell,mmp2-gpio"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0xd4019000 0x1000>; - gpio-controller; - #gpio-cells = <2>; - interrupts = <49>; - interrupt-names = "gpio_mux"; - clocks = <&soc_clocks MMP2_CLK_GPIO>; - resets = <&soc_clocks MMP2_CLK_GPIO>; - interrupt-controller; - #interrupt-cells = <2>; - ranges; - - gcb0: gpio@d4019000 { - reg = <0xd4019000 0x4>; - }; - - gcb1: gpio@d4019004 { - reg = <0xd4019004 0x4>; - }; - - gcb2: gpio@d4019008 { - reg = <0xd4019008 0x4>; - }; - - gcb3: gpio@d4019100 { - reg = <0xd4019100 0x4>; - }; - - gcb4: gpio@d4019104 { - reg = <0xd4019104 0x4>; - }; - - gcb5: gpio@d4019108 { - reg = <0xd4019108 0x4>; - }; - }; - - twsi1: i2c@d4011000 { - compatible = "mrvl,mmp-twsi"; - reg = <0xd4011000 0x1000>; - interrupts = <7>; - clocks = <&soc_clocks MMP2_CLK_TWSI0>; - resets = <&soc_clocks MMP2_CLK_TWSI0>; - #address-cells = <1>; - #size-cells = <0>; - mrvl,i2c-fast-mode; - status = "disabled"; - }; - - twsi2: i2c@d4031000 { - compatible = "mrvl,mmp-twsi"; - reg = <0xd4031000 0x1000>; - interrupt-parent = <&intcmux17>; - interrupts = <0>; - clocks = <&soc_clocks MMP2_CLK_TWSI1>; - resets = <&soc_clocks MMP2_CLK_TWSI1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - twsi3: i2c@d4032000 { - compatible = "mrvl,mmp-twsi"; - reg = <0xd4032000 0x1000>; - interrupt-parent = <&intcmux17>; - interrupts = <1>; - clocks = <&soc_clocks MMP2_CLK_TWSI2>; - resets = <&soc_clocks MMP2_CLK_TWSI2>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - twsi4: i2c@d4033000 { - compatible = "mrvl,mmp-twsi"; - reg = <0xd4033000 0x1000>; - interrupt-parent = <&intcmux17>; - interrupts = <2>; - clocks = <&soc_clocks MMP2_CLK_TWSI3>; - resets = <&soc_clocks MMP2_CLK_TWSI3>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - - twsi5: i2c@d4033800 { - compatible = "mrvl,mmp-twsi"; - reg = <0xd4033800 0x1000>; - interrupt-parent = <&intcmux17>; - interrupts = <3>; - clocks = <&soc_clocks MMP2_CLK_TWSI4>; - resets = <&soc_clocks MMP2_CLK_TWSI4>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - twsi6: i2c@d4034000 { - compatible = "mrvl,mmp-twsi"; - reg = <0xd4034000 0x1000>; - interrupt-parent = <&intcmux17>; - interrupts = <4>; - clocks = <&soc_clocks MMP2_CLK_TWSI5>; - resets = <&soc_clocks MMP2_CLK_TWSI5>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - rtc: rtc@d4010000 { - compatible = "mrvl,mmp-rtc"; - reg = <0xd4010000 0x1000>; - interrupts = <1 0>; - interrupt-names = "rtc 1Hz", "rtc alarm"; - interrupt-parent = <&intcmux5>; - clocks = <&soc_clocks MMP2_CLK_RTC>; - resets = <&soc_clocks MMP2_CLK_RTC>; - status = "disabled"; - }; - - ssp1: spi@d4035000 { - compatible = "marvell,mmp2-ssp"; - reg = <0xd4035000 0x1000>; - clocks = <&soc_clocks MMP2_CLK_SSP0>; - interrupts = <0>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - ssp2: spi@d4036000 { - compatible = "marvell,mmp2-ssp"; - reg = <0xd4036000 0x1000>; - clocks = <&soc_clocks MMP2_CLK_SSP1>; - interrupts = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - ssp3: spi@d4037000 { - compatible = "marvell,mmp2-ssp"; - reg = <0xd4037000 0x1000>; - clocks = <&soc_clocks MMP2_CLK_SSP2>; - interrupts = <20>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - ssp4: spi@d4039000 { - compatible = "marvell,mmp2-ssp"; - reg = <0xd4039000 0x1000>; - clocks = <&soc_clocks MMP2_CLK_SSP3>; - interrupts = <21>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - soc_clocks: clocks { - compatible = "marvell,mmp2-clock"; - reg = <0xd4050000 0x1000>, - <0xd4282800 0x400>, - <0xd4015000 0x1000>; - reg-names = "mpmu", "apmu", "apbc"; - #clock-cells = <1>; - #reset-cells = <1>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/mmp3-dell-ariel.dts b/sys/gnu/dts/arm/mmp3-dell-ariel.dts deleted file mode 100644 index 15449c72c04..00000000000 --- a/sys/gnu/dts/arm/mmp3-dell-ariel.dts +++ /dev/null @@ -1,116 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Dell Wyse 3020 a.k.a. "Ariel" a.k.a. Tx0D (T00D, T10D) - * - * Copyright (C) 2019 Lubomir Rintel - */ - -/dts-v1/; -#include "mmp3.dtsi" -#include -#include - -/ { - model = "Dell Ariel"; - compatible = "dell,wyse-ariel", "marvell,mmp3"; - - aliases { - serial2 = &uart3; - }; - - chosen { - #address-cells = <0x1>; - #size-cells = <0x1>; - ranges; - bootargs = "earlyprintk=ttyS2,115200 console=ttyS2,115200"; - }; - - memory@0 { - linux,usable-memory = <0x0 0x7f600000>; - available = <0x7f700000 0x7ff00000 0x00000000 0x7f600000>; - reg = <0x0 0x80000000>; - device_type = "memory"; - }; -}; - -&uart3 { - status = "okay"; -}; - -&rtc { - status = "okay"; -}; - -&usb_otg0 { - status = "okay"; -}; - -&usb_otg_phy0 { - status = "okay"; -}; - -&hsic0 { - status = "okay"; - - usb1@1 { - compatible = "usb424,2640"; - reg = <0x01>; - #address-cells = <0x01>; - #size-cells = <0x00>; - - mass-storage@1 { - compatible = "usb424,4040"; - reg = <0x01>; - status = "disabled"; - }; - }; -}; - -&hsic_phy0 { - status = "okay"; - reset-gpios = <&gpio 63 GPIO_ACTIVE_HIGH>; -}; - -&mmc3 { - status = "okay"; - max-frequency = <50000000>; - status = "okay"; - bus-width = <8>; - non-removable; - cap-mmc-highspeed; -}; - -&twsi1 { - status = "okay"; - - rtc@68 { - compatible = "dallas,ds1338"; - reg = <0x68>; - status = "okay"; - }; -}; - -&twsi3 { - status = "okay"; -}; - -&twsi4 { - status = "okay"; -}; - -&ssp3 { - status = "okay"; - cs-gpios = <&gpio 46 GPIO_ACTIVE_HIGH>; - - firmware-flash@0 { - compatible = "st,m25p80", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <40000000>; - m25p,fast-read; - }; -}; - -&ssp4 { - cs-gpios = <&gpio 56 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/mmp3.dtsi b/sys/gnu/dts/arm/mmp3.dtsi deleted file mode 100644 index 59a108e49b4..00000000000 --- a/sys/gnu/dts/arm/mmp3.dtsi +++ /dev/null @@ -1,571 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -/* - * Copyright (C) 2019 Lubomir Rintel - */ - -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "marvell,mmp3-smp"; - - cpu@0 { - compatible = "marvell,pj4b"; - device_type = "cpu"; - next-level-cache = <&l2>; - reg = <0>; - }; - - cpu@1 { - compatible = "marvell,pj4b"; - device_type = "cpu"; - next-level-cache = <&l2>; - reg = <1>; - }; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&gic>; - ranges; - - axi@d4200000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0xd4200000 0x00200000>; - ranges; - - interrupt-controller@d4282000 { - compatible = "marvell,mmp3-intc"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0xd4282000 0x1000>, - <0xd4284000 0x100>; - mrvl,intc-nr-irqs = <64>; - }; - - pmic_mux: interrupt-controller@d4282150 { - compatible = "mrvl,mmp2-mux-intc"; - interrupts = ; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x150 0x4>, <0x168 0x4>; - reg-names = "mux status", "mux mask"; - mrvl,intc-nr-irqs = <4>; - }; - - rtc_mux: interrupt-controller@d4282154 { - compatible = "mrvl,mmp2-mux-intc"; - interrupts = ; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x154 0x4>, <0x16c 0x4>; - reg-names = "mux status", "mux mask"; - mrvl,intc-nr-irqs = <2>; - }; - - hsi3_mux: interrupt-controller@d42821bc { - compatible = "mrvl,mmp2-mux-intc"; - interrupts = ; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x1bc 0x4>, <0x1a4 0x4>; - reg-names = "mux status", "mux mask"; - mrvl,intc-nr-irqs = <3>; - }; - - gpu_mux: interrupt-controller@d42821c0 { - compatible = "mrvl,mmp2-mux-intc"; - interrupts = ; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x1c0 0x4>, <0x1a8 0x4>; - reg-names = "mux status", "mux mask"; - mrvl,intc-nr-irqs = <3>; - }; - - twsi_mux: interrupt-controller@d4282158 { - compatible = "mrvl,mmp2-mux-intc"; - interrupts = ; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x158 0x4>, <0x170 0x4>; - reg-names = "mux status", "mux mask"; - mrvl,intc-nr-irqs = <5>; - }; - - hsi2_mux: interrupt-controller@d42821c4 { - compatible = "mrvl,mmp2-mux-intc"; - interrupts = ; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x1c4 0x4>, <0x1ac 0x4>; - reg-names = "mux status", "mux mask"; - mrvl,intc-nr-irqs = <2>; - }; - - dxo_mux: interrupt-controller@d42821c8 { - compatible = "mrvl,mmp2-mux-intc"; - interrupts = ; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x1c8 0x4>, <0x1b0 0x4>; - reg-names = "mux status", "mux mask"; - mrvl,intc-nr-irqs = <2>; - }; - - misc1_mux: interrupt-controller@d428215c { - compatible = "mrvl,mmp2-mux-intc"; - interrupts = ; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x15c 0x4>, <0x174 0x4>; - reg-names = "mux status", "mux mask"; - mrvl,intc-nr-irqs = <31>; - }; - - ci_mux: interrupt-controller@d42821cc { - compatible = "mrvl,mmp2-mux-intc"; - interrupts = ; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x1cc 0x4>, <0x1b4 0x4>; - reg-names = "mux status", "mux mask"; - mrvl,intc-nr-irqs = <2>; - }; - - ssp_mux: interrupt-controller@d4282160 { - compatible = "mrvl,mmp2-mux-intc"; - interrupts = ; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x160 0x4>, <0x178 0x4>; - reg-names = "mux status", "mux mask"; - mrvl,intc-nr-irqs = <2>; - }; - - hsi1_mux: interrupt-controller@d4282184 { - compatible = "mrvl,mmp2-mux-intc"; - interrupts = ; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x184 0x4>, <0x17c 0x4>; - reg-names = "mux status", "mux mask"; - mrvl,intc-nr-irqs = <4>; - }; - - misc2_mux: interrupt-controller@d4282188 { - compatible = "mrvl,mmp2-mux-intc"; - interrupts = ; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x188 0x4>, <0x180 0x4>; - reg-names = "mux status", "mux mask"; - mrvl,intc-nr-irqs = <20>; - }; - - hsi0_mux: interrupt-controller@d42821d0 { - compatible = "mrvl,mmp2-mux-intc"; - interrupts = ; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x1d0 0x4>, <0x1b8 0x4>; - reg-names = "mux status", "mux mask"; - mrvl,intc-nr-irqs = <5>; - }; - - usb_otg_phy0: usb-otg-phy@d4207000 { - compatible = "marvell,mmp3-usb-phy"; - reg = <0xd4207000 0x40>; - #phy-cells = <0>; - status = "disabled"; - }; - - usb_otg0: usb-otg@d4208000 { - compatible = "marvell,pxau2o-ehci"; - reg = <0xd4208000 0x200>; - interrupts = ; - clocks = <&soc_clocks MMP2_CLK_USB>; - clock-names = "USBCLK"; - phys = <&usb_otg_phy0>; - phy-names = "usb"; - status = "disabled"; - }; - - hsic_phy0: hsic-phy@f0001800 { - compatible = "marvell,mmp3-hsic-phy", - "usb-nop-xceiv"; - reg = <0xf0001800 0x40>; - #phy-cells = <0>; - status = "disabled"; - }; - - hsic0: hsic@f0001000 { - compatible = "marvell,pxau2o-ehci"; - reg = <0xf0001000 0x200>; - interrupts = ; - clocks = <&soc_clocks MMP2_CLK_USBHSIC0>; - clock-names = "USBCLK"; - phys = <&hsic_phy0>; - phy-names = "usb"; - phy_type = "hsic"; - #address-cells = <0x01>; - #size-cells = <0x00>; - status = "disabled"; - }; - - hsic_phy1: hsic-phy@f0002800 { - compatible = "marvell,mmp3-hsic-phy", - "usb-nop-xceiv"; - reg = <0xf0002800 0x40>; - #phy-cells = <0>; - status = "disabled"; - }; - - hsic1: hsic@f0002000 { - compatible = "marvell,pxau2o-ehci"; - reg = <0xf0002000 0x200>; - interrupts = ; - clocks = <&soc_clocks MMP2_CLK_USBHSIC1>; - clock-names = "USBCLK"; - phys = <&hsic_phy1>; - phy-names = "usb"; - phy_type = "hsic"; - #address-cells = <0x01>; - #size-cells = <0x00>; - status = "disabled"; - }; - - mmc1: mmc@d4280000 { - compatible = "mrvl,pxav3-mmc"; - reg = <0xd4280000 0x120>; - clocks = <&soc_clocks MMP2_CLK_SDH0>; - clock-names = "io"; - interrupts = ; - status = "disabled"; - }; - - mmc2: mmc@d4280800 { - compatible = "mrvl,pxav3-mmc"; - reg = <0xd4280800 0x120>; - clocks = <&soc_clocks MMP2_CLK_SDH1>; - clock-names = "io"; - interrupts = ; - status = "disabled"; - }; - - mmc3: mmc@d4281000 { - compatible = "mrvl,pxav3-mmc"; - reg = <0xd4281000 0x120>; - clocks = <&soc_clocks MMP2_CLK_SDH2>; - clock-names = "io"; - interrupts = ; - status = "disabled"; - }; - - mmc4: mmc@d4281800 { - compatible = "mrvl,pxav3-mmc"; - reg = <0xd4281800 0x120>; - clocks = <&soc_clocks MMP2_CLK_SDH3>; - clock-names = "io"; - interrupts = ; - status = "disabled"; - }; - - camera0: camera@d420a000 { - compatible = "marvell,mmp2-ccic"; - reg = <0xd420a000 0x800>; - interrupts = ; - clocks = <&soc_clocks MMP2_CLK_CCIC0>; - clock-names = "axi"; - #clock-cells = <0>; - clock-output-names = "mclk"; - status = "disabled"; - }; - - camera1: camera@d420a800 { - compatible = "marvell,mmp2-ccic"; - reg = <0xd420a800 0x800>; - interrupts = ; - clocks = <&soc_clocks MMP2_CLK_CCIC1>; - clock-names = "axi"; - #clock-cells = <0>; - clock-output-names = "mclk"; - status = "disabled"; - }; - }; - - apb@d4000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0xd4000000 0x00200000>; - ranges; - - timer: timer@d4014000 { - compatible = "mrvl,mmp-timer"; - reg = <0xd4014000 0x100>; - interrupts = ; - clocks = <&soc_clocks MMP2_CLK_TIMER>; - }; - - uart1: uart@d4030000 { - compatible = "mrvl,mmp-uart"; - reg = <0xd4030000 0x1000>; - interrupts = ; - clocks = <&soc_clocks MMP2_CLK_UART0>; - resets = <&soc_clocks MMP2_CLK_UART0>; - reg-shift = <2>; - status = "disabled"; - }; - - uart2: uart@d4017000 { - compatible = "mrvl,mmp-uart"; - reg = <0xd4017000 0x1000>; - interrupts = ; - clocks = <&soc_clocks MMP2_CLK_UART1>; - resets = <&soc_clocks MMP2_CLK_UART1>; - reg-shift = <2>; - status = "disabled"; - }; - - uart3: uart@d4018000 { - compatible = "mrvl,mmp-uart"; - reg = <0xd4018000 0x1000>; - interrupts = ; - clocks = <&soc_clocks MMP2_CLK_UART2>; - resets = <&soc_clocks MMP2_CLK_UART2>; - reg-shift = <2>; - status = "disabled"; - }; - - uart4: uart@d4016000 { - compatible = "mrvl,mmp-uart"; - reg = <0xd4016000 0x1000>; - interrupts = ; - clocks = <&soc_clocks MMP2_CLK_UART3>; - resets = <&soc_clocks MMP2_CLK_UART3>; - reg-shift = <2>; - status = "disabled"; - }; - - gpio: gpio@d4019000 { - compatible = "marvell,mmp2-gpio"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0xd4019000 0x1000>; - gpio-controller; - #gpio-cells = <2>; - interrupts = ; - interrupt-names = "gpio_mux"; - clocks = <&soc_clocks MMP2_CLK_GPIO>; - resets = <&soc_clocks MMP2_CLK_GPIO>; - interrupt-controller; - #interrupt-cells = <2>; - ranges; - - gcb0: gpio@d4019000 { - reg = <0xd4019000 0x4>; - }; - - gcb1: gpio@d4019004 { - reg = <0xd4019004 0x4>; - }; - - gcb2: gpio@d4019008 { - reg = <0xd4019008 0x4>; - }; - - gcb3: gpio@d4019100 { - reg = <0xd4019100 0x4>; - }; - - gcb4: gpio@d4019104 { - reg = <0xd4019104 0x4>; - }; - - gcb5: gpio@d4019108 { - reg = <0xd4019108 0x4>; - }; - }; - - twsi1: i2c@d4011000 { - compatible = "mrvl,mmp-twsi"; - reg = <0xd4011000 0x70>; - interrupts = ; - clocks = <&soc_clocks MMP2_CLK_TWSI0>; - resets = <&soc_clocks MMP2_CLK_TWSI0>; - #address-cells = <1>; - #size-cells = <0>; - mrvl,i2c-fast-mode; - status = "disabled"; - }; - - twsi2: i2c@d4031000 { - compatible = "mrvl,mmp-twsi"; - reg = <0xd4031000 0x70>; - interrupt-parent = <&twsi_mux>; - interrupts = <0>; - clocks = <&soc_clocks MMP2_CLK_TWSI1>; - resets = <&soc_clocks MMP2_CLK_TWSI1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - twsi3: i2c@d4032000 { - compatible = "mrvl,mmp-twsi"; - reg = <0xd4032000 0x70>; - interrupt-parent = <&twsi_mux>; - interrupts = <1>; - clocks = <&soc_clocks MMP2_CLK_TWSI2>; - resets = <&soc_clocks MMP2_CLK_TWSI2>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - twsi4: i2c@d4033000 { - compatible = "mrvl,mmp-twsi"; - reg = <0xd4033000 0x70>; - interrupt-parent = <&twsi_mux>; - interrupts = <2>; - clocks = <&soc_clocks MMP2_CLK_TWSI3>; - resets = <&soc_clocks MMP2_CLK_TWSI3>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - - twsi5: i2c@d4033800 { - compatible = "mrvl,mmp-twsi"; - reg = <0xd4033800 0x70>; - interrupt-parent = <&twsi_mux>; - interrupts = <3>; - clocks = <&soc_clocks MMP2_CLK_TWSI4>; - resets = <&soc_clocks MMP2_CLK_TWSI4>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - twsi6: i2c@d4034000 { - compatible = "mrvl,mmp-twsi"; - reg = <0xd4034000 0x70>; - interrupt-parent = <&twsi_mux>; - interrupts = <4>; - clocks = <&soc_clocks MMP2_CLK_TWSI5>; - resets = <&soc_clocks MMP2_CLK_TWSI5>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - rtc: rtc@d4010000 { - compatible = "mrvl,mmp-rtc"; - reg = <0xd4010000 0x1000>; - interrupts = <1 0>; - interrupt-names = "rtc 1Hz", "rtc alarm"; - interrupt-parent = <&rtc_mux>; - clocks = <&soc_clocks MMP2_CLK_RTC>; - resets = <&soc_clocks MMP2_CLK_RTC>; - status = "disabled"; - }; - - ssp1: spi@d4035000 { - compatible = "marvell,mmp2-ssp"; - reg = <0xd4035000 0x1000>; - clocks = <&soc_clocks MMP2_CLK_SSP0>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - ssp2: spi@d4036000 { - compatible = "marvell,mmp2-ssp"; - reg = <0xd4036000 0x1000>; - clocks = <&soc_clocks MMP2_CLK_SSP1>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - ssp3: spi@d4037000 { - compatible = "marvell,mmp2-ssp"; - reg = <0xd4037000 0x1000>; - clocks = <&soc_clocks MMP2_CLK_SSP2>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - ssp4: spi@d4039000 { - compatible = "marvell,mmp2-ssp"; - reg = <0xd4039000 0x1000>; - clocks = <&soc_clocks MMP2_CLK_SSP3>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - l2: l2-cache-controller@d0020000 { - compatible = "marvell,tauros3-cache", "arm,pl310-cache"; - reg = <0xd0020000 0x1000>; - cache-unified; - cache-level = <2>; - }; - - soc_clocks: clocks@d4050000 { - compatible = "marvell,mmp2-clock"; - reg = <0xd4050000 0x1000>, - <0xd4282800 0x400>, - <0xd4015000 0x1000>; - reg-names = "mpmu", "apmu", "apbc"; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - }; - - snoop-control-unit@e0000000 { - compatible = "arm,arm11mp-scu"; - reg = <0xe0000000 0x100>; - }; - - gic: interrupt-controller@e0001000 { - compatible = "arm,arm11mp-gic"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0xe0001000 0x1000>, - <0xe0000100 0x100>; - }; - - local-timer@e0000600 { - compatible = "arm,arm11mp-twd-timer"; - interrupts = ; - reg = <0xe0000600 0x20>; - }; - - watchdog@e0000620 { - compatible = "arm,arm11mp-twd-wdt"; - reg = <0xe0000620 0x20>; - interrupts = ; - }; - }; -}; diff --git a/sys/gnu/dts/arm/motorola-cpcap-mapphone.dtsi b/sys/gnu/dts/arm/motorola-cpcap-mapphone.dtsi deleted file mode 100644 index e39eee628af..00000000000 --- a/sys/gnu/dts/arm/motorola-cpcap-mapphone.dtsi +++ /dev/null @@ -1,273 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Common CPCAP configuration used on Motorola phones - */ - -&mcspi1 { - cpcap: pmic@0 { - compatible = "motorola,cpcap", "st,6556002"; - reg = <0>; /* cs0 */ - interrupt-parent = <&gpio1>; - interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - #interrupt-cells = <2>; - #address-cells = <1>; - #size-cells = <0>; - spi-max-frequency = <3000000>; - spi-cs-high; - - cpcap_adc: adc { - compatible = "motorola,mapphone-cpcap-adc"; - interrupts-extended = <&cpcap 8 0>; - interrupt-names = "adcdone"; - #io-channel-cells = <1>; - }; - - cpcap_battery: battery { - compatible = "motorola,cpcap-battery"; - interrupts-extended = < - &cpcap 6 0 &cpcap 5 0 &cpcap 3 0 - &cpcap 20 0 &cpcap 54 0 &cpcap 57 0 - >; - interrupt-names = - "eol", "lowbph", "lowbpl", - "chrgcurr1", "battdetb", - "cccal"; - io-channels = <&cpcap_adc 0 &cpcap_adc 1 - &cpcap_adc 5 &cpcap_adc 6>; - io-channel-names = "battdetb", "battp", - "chg_isense", "batti"; - power-supplies = <&cpcap_charger>; - }; - - cpcap_charger: charger { - compatible = "motorola,mapphone-cpcap-charger"; - interrupts-extended = < - &cpcap 13 0 &cpcap 12 0 &cpcap 29 0 &cpcap 28 0 - &cpcap 22 0 &cpcap 21 0 &cpcap 20 0 &cpcap 19 0 - &cpcap 54 0 - >; - interrupt-names = - "chrg_det", "rvrs_chrg", "chrg_se1b", "se0conn", - "rvrs_mode", "chrgcurr2", "chrgcurr1", "vbusvld", - "battdetb"; - mode-gpios = <&gpio3 29 GPIO_ACTIVE_LOW - &gpio3 23 GPIO_ACTIVE_LOW>; - io-channels = <&cpcap_adc 0 &cpcap_adc 1 - &cpcap_adc 2 &cpcap_adc 5 - &cpcap_adc 6>; - io-channel-names = "battdetb", "battp", - "vbus", "chg_isense", - "batti"; - }; - - cpcap_regulator: regulator { - compatible = "motorola,mapphone-cpcap-regulator"; - - cpcap_regulators: regulators { - }; - }; - - cpcap_audio: audio-codec { - #sound-dai-cells = <1>; - - port@0 { - cpcap_audio_codec0: endpoint { - }; - }; - port@1 { - cpcap_audio_codec1: endpoint { - }; - }; - }; - - cpcap_rtc: rtc { - compatible = "motorola,cpcap-rtc"; - - interrupt-parent = <&cpcap>; - interrupts = <39 IRQ_TYPE_NONE>, <26 IRQ_TYPE_NONE>; - }; - - power_button: button { - compatible = "motorola,cpcap-pwrbutton"; - - interrupts = <23 IRQ_TYPE_NONE>; - }; - - cpcap_usb2_phy: phy { - compatible = "motorola,mapphone-cpcap-usb-phy"; - pinctrl-0 = <&usb_gpio_mux_sel1 &usb_gpio_mux_sel2>; - pinctrl-1 = <&usb_ulpi_pins>; - pinctrl-2 = <&usb_utmi_pins>; - pinctrl-3 = <&uart3_pins>; - pinctrl-names = "default", "ulpi", "utmi", "uart"; - #phy-cells = <0>; - interrupts-extended = < - &cpcap 15 0 &cpcap 14 0 &cpcap 28 0 &cpcap 19 0 - &cpcap 18 0 &cpcap 17 0 &cpcap 16 0 &cpcap 49 0 - &cpcap 48 0 - >; - interrupt-names = - "id_ground", "id_float", "se0conn", "vbusvld", - "sessvld", "sessend", "se1", "dm", "dp"; - mode-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH - &gpio1 0 GPIO_ACTIVE_HIGH>; - io-channels = <&cpcap_adc 2>, <&cpcap_adc 7>; - io-channel-names = "vbus", "id"; - vusb-supply = <&vusb>; - }; - - led_red: led-red { - compatible = "motorola,cpcap-led-red"; - vdd-supply = <&sw5>; - label = "status-led:red"; - }; - - led_green: led-green { - compatible = "motorola,cpcap-led-green"; - vdd-supply = <&sw5>; - label = "status-led:green"; - }; - - led_blue: led-blue { - compatible = "motorola,cpcap-led-blue"; - vdd-supply = <&sw5>; - label = "status-led:blue"; - }; - - led_adl: led-adl { - compatible = "motorola,cpcap-led-adl"; - vdd-supply = <&sw5>; - label = "button-backlight"; - }; - - led_cp: led-cp { - compatible = "motorola,cpcap-led-cp"; - vdd-supply = <&sw5>; - label = "shift-key-light"; - }; - }; -}; - -&cpcap_regulators { - sw5: SW5 { - regulator-min-microvolt = <5050000>; - regulator-max-microvolt = <5050000>; - regulator-enable-ramp-delay = <50000>; - regulator-boot-on; - }; - - vcam: VCAM { - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - regulator-enable-ramp-delay = <1000>; - }; - - /* Used by DSS and is the "zerov_regulator" trigger for SoC off mode */ - vcsi: VCSI { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-enable-ramp-delay = <1000>; - regulator-always-on; - }; - - vdac: VDAC { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-enable-ramp-delay = <1000>; - }; - - vdig: VDIG { - regulator-min-microvolt = <1875000>; - regulator-max-microvolt = <1875000>; - regulator-enable-ramp-delay = <1000>; - }; - - vfuse: VFUSE { - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <3150000>; - regulator-enable-ramp-delay = <1000>; - }; - - vhvio: VHVIO { - regulator-min-microvolt = <2775000>; - regulator-max-microvolt = <2775000>; - regulator-enable-ramp-delay = <1000>; - regulator-always-on; - }; - - /* Used by eMMC at mmc2 */ - vsdio: VSDIO { - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - regulator-enable-ramp-delay = <1000>; - }; - - vpll: VPLL { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1800000>; - regulator-enable-ramp-delay = <100>; - }; - - vrf1: VRF1 { - regulator-min-microvolt = <2775000>; - regulator-max-microvolt = <2775000>; - regulator-enable-ramp-delay = <1000>; - }; - - vrf2: VRF2 { - regulator-min-microvolt = <2775000>; - regulator-max-microvolt = <2775000>; - regulator-enable-ramp-delay = <1000>; - }; - - vrfref: VRFREF { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2775000>; - regulator-enable-ramp-delay = <100>; - }; - - vwlan1: VWLAN1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1900000>; - regulator-enable-ramp-delay = <1000>; - }; - - /* Used by micro-SDIO at mmc1 */ - vwlan2: VWLAN2 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-enable-ramp-delay = <1000>; - }; - - vsim: VSIM { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2900000>; - regulator-enable-ramp-delay = <1000>; - }; - - vsimcard: VSIMCARD { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2900000>; - regulator-enable-ramp-delay = <1000>; - }; - - vvib: VVIB { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <3000000>; - regulator-enable-ramp-delay = <500>; - }; - - vusb: VUSB { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <1000>; - }; - - vaudio: VAUDIO { - regulator-min-microvolt = <2775000>; - regulator-max-microvolt = <2775000>; - regulator-enable-ramp-delay = <1000>; - regulator-initial-mode = <0x00>; /* NORMAL */ - }; -}; diff --git a/sys/gnu/dts/arm/motorola-mapphone-common.dtsi b/sys/gnu/dts/arm/motorola-mapphone-common.dtsi deleted file mode 100644 index 9067e0ef424..00000000000 --- a/sys/gnu/dts/arm/motorola-mapphone-common.dtsi +++ /dev/null @@ -1,814 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/dts-v1/; - -#include -#include "omap443x.dtsi" -#include "motorola-cpcap-mapphone.dtsi" - -/ { - chosen { - stdout-path = &uart3; - }; - - aliases { - display0 = &lcd0; - display1 = &hdmi0; - }; - - /* - * We seem to have only 1021 MB accessible, 1021 - 1022 is locked, - * then 1023 - 1024 seems to contain mbm. - */ - memory { - device_type = "memory"; - reg = <0x80000000 0x3fd00000>; /* 1021 MB */ - }; - - /* Poweroff GPIO probably connected to CPCAP */ - gpio-poweroff { - compatible = "gpio-poweroff"; - pinctrl-0 = <&poweroff_gpio>; - pinctrl-names = "default"; - gpios = <&gpio2 18 GPIO_ACTIVE_LOW>; /* gpio50 */ - }; - - hdmi0: connector { - compatible = "hdmi-connector"; - pinctrl-0 = <&hdmi_hpd_gpio>; - pinctrl-names = "default"; - label = "hdmi"; - type = "d"; - - hpd-gpios = <&gpio2 31 GPIO_ACTIVE_HIGH>; /* gpio63 */ - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_out>; - }; - }; - }; - - /* - * HDMI 5V regulator probably sourced from battery. Let's keep - * keep this as always enabled for HDMI to work until we've - * figured what the encoder chip is. - */ - hdmi_regulator: regulator-hdmi { - compatible = "regulator-fixed"; - regulator-name = "hdmi"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio2 27 GPIO_ACTIVE_HIGH>; /* gpio59 */ - enable-active-high; - regulator-always-on; - }; - - /* FS USB Host PHY on port 1 for mdm6600 */ - fsusb1_phy: usb-phy@1 { - compatible = "motorola,mapphone-mdm6600"; - pinctrl-0 = <&usb_mdm6600_pins>; - pinctrl-names = "default"; - enable-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; /* gpio_95 */ - power-gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; /* gpio_54 */ - reset-gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>; /* gpio_49 */ - /* mode: gpio_148 gpio_149 */ - motorola,mode-gpios = <&gpio5 20 GPIO_ACTIVE_HIGH>, - <&gpio5 21 GPIO_ACTIVE_HIGH>; - /* cmd: gpio_103 gpio_104 gpio_142 */ - motorola,cmd-gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>, - <&gpio4 8 GPIO_ACTIVE_HIGH>, - <&gpio5 14 GPIO_ACTIVE_HIGH>; - /* status: gpio_52 gpio_53 gpio_55 */ - motorola,status-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>, - <&gpio2 21 GPIO_ACTIVE_HIGH>, - <&gpio2 23 GPIO_ACTIVE_HIGH>; - #phy-cells = <0>; - }; - - /* HS USB host TLL nop-phy on port 2 for w3glte */ - hsusb2_phy: usb-phy@2 { - compatible = "usb-nop-xceiv"; - #phy-cells = <0>; - }; - - /* LCD regulator from sw5 source */ - lcd_regulator: regulator-lcd { - compatible = "regulator-fixed"; - regulator-name = "lcd"; - regulator-min-microvolt = <5050000>; - regulator-max-microvolt = <5050000>; - gpio = <&gpio4 0 GPIO_ACTIVE_HIGH>; /* gpio96 */ - enable-active-high; - vin-supply = <&sw5>; - }; - - /* This is probably coming straight from the battery.. */ - wl12xx_vmmc: regulator-wl12xx { - compatible = "regulator-fixed"; - regulator-name = "vwl1271"; - regulator-min-microvolt = <1650000>; - regulator-max-microvolt = <1650000>; - gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>; /* gpio94 */ - startup-delay-us = <70000>; - enable-active-high; - }; - - gpio_keys { - compatible = "gpio-keys"; - - volume_down { - label = "Volume Down"; - gpios = <&gpio5 26 GPIO_ACTIVE_LOW>; /* gpio154 */ - linux,code = ; - linux,can-disable; - /* Value above 7.95ms for no GPIO hardware debounce */ - debounce-interval = <10>; - }; - - slider { - label = "Keypad Slide"; - gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>; /* gpio122 */ - linux,input-type = ; - linux,code = ; - linux,can-disable; - /* Value above 7.95ms for no GPIO hardware debounce */ - debounce-interval = <10>; - }; - }; - - soundcard { - compatible = "audio-graph-card"; - label = "Droid 4 Audio"; - - simple-graph-card,widgets = - "Speaker", "Earpiece", - "Speaker", "Loudspeaker", - "Headphone", "Headphone Jack", - "Microphone", "Internal Mic"; - - simple-graph-card,routing = - "Earpiece", "EP", - "Loudspeaker", "SPKR", - "Headphone Jack", "HSL", - "Headphone Jack", "HSR", - "MICR", "Internal Mic"; - - dais = <&mcbsp2_port>, <&mcbsp3_port>; - }; - - pwm8: dmtimer-pwm-8 { - pinctrl-names = "default"; - pinctrl-0 = <&vibrator_direction_pin>; - - compatible = "ti,omap-dmtimer-pwm"; - #pwm-cells = <3>; - ti,timers = <&timer8>; - ti,clock-source = <0x01>; - }; - - pwm9: dmtimer-pwm-9 { - pinctrl-names = "default"; - pinctrl-0 = <&vibrator_enable_pin>; - - compatible = "ti,omap-dmtimer-pwm"; - #pwm-cells = <3>; - ti,timers = <&timer9>; - ti,clock-source = <0x01>; - }; - - vibrator { - compatible = "pwm-vibrator"; - pwms = <&pwm9 0 10000000 0>, <&pwm8 0 10000000 0>; - pwm-names = "enable", "direction"; - direction-duty-cycle-ns = <10000000>; - }; - - backlight: backlight { - compatible = "led-backlight"; - - leds = <&backlight_led>; - brightness-levels = <31 63 95 127 159 191 223 255>; - default-brightness-level = <6>; - }; -}; - -&dss { - status = "okay"; -}; - -&dsi1 { - status = "okay"; - vdd-supply = <&vcsi>; - - port { - dsi1_out_ep: endpoint { - remote-endpoint = <&lcd0_in>; - lanes = <0 1 2 3 4 5>; - }; - }; - - lcd0: display { - compatible = "panel-dsi-cm"; - label = "lcd0"; - vddi-supply = <&lcd_regulator>; - reset-gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; /* gpio101 */ - - backlight = <&backlight>; - - width-mm = <50>; - height-mm = <89>; - - panel-timing { - clock-frequency = <0>; /* Calculated by dsi */ - - hback-porch = <2>; - hactive = <540>; - hfront-porch = <0>; - hsync-len = <2>; - - vback-porch = <1>; - vactive = <960>; - vfront-porch = <0>; - vsync-len = <1>; - - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - - port { - lcd0_in: endpoint { - remote-endpoint = <&dsi1_out_ep>; - }; - }; - }; -}; - -&hdmi { - status = "okay"; - pinctrl-0 = <&dss_hdmi_pins>; - pinctrl-names = "default"; - vdda-supply = <&vdac>; - - port { - hdmi_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - lanes = <1 0 3 2 5 4 7 6>; - }; - }; -}; - -/* Battery NVRAM on 1-wire handled by w1_ds250x driver */ -&hdqw1w { - pinctrl-0 = <&hdq_pins>; - pinctrl-names = "default"; - ti,mode = "1w"; -}; - -&i2c1 { - tmp105@48 { - compatible = "ti,tmp105"; - reg = <0x48>; - pinctrl-0 = <&tmp105_irq>; - pinctrl-names = "default"; - /* kpd_row0.gpio_178 */ - interrupts-extended = <&gpio6 18 IRQ_TYPE_EDGE_FALLING - &omap4_pmx_core 0x14e>; - interrupt-names = "irq", "wakeup"; - wakeup-source; - }; -}; - -&keypad { - keypad,num-rows = <8>; - keypad,num-columns = <8>; - linux,keymap = < - - /* Row 1 */ - MATRIX_KEY(0, 2, KEY_1) - MATRIX_KEY(0, 6, KEY_2) - MATRIX_KEY(2, 3, KEY_3) - MATRIX_KEY(0, 7, KEY_4) - MATRIX_KEY(0, 4, KEY_5) - MATRIX_KEY(5, 5, KEY_6) - MATRIX_KEY(0, 1, KEY_7) - MATRIX_KEY(0, 5, KEY_8) - MATRIX_KEY(0, 0, KEY_9) - MATRIX_KEY(1, 6, KEY_0) - - /* Row 2 */ - MATRIX_KEY(3, 4, KEY_APOSTROPHE) - MATRIX_KEY(7, 6, KEY_Q) - MATRIX_KEY(7, 7, KEY_W) - MATRIX_KEY(7, 2, KEY_E) - MATRIX_KEY(1, 0, KEY_R) - MATRIX_KEY(4, 4, KEY_T) - MATRIX_KEY(1, 2, KEY_Y) - MATRIX_KEY(6, 7, KEY_U) - MATRIX_KEY(2, 2, KEY_I) - MATRIX_KEY(5, 6, KEY_O) - MATRIX_KEY(3, 7, KEY_P) - MATRIX_KEY(6, 5, KEY_BACKSPACE) - - /* Row 3 */ - MATRIX_KEY(5, 4, KEY_TAB) - MATRIX_KEY(5, 7, KEY_A) - MATRIX_KEY(2, 7, KEY_S) - MATRIX_KEY(7, 0, KEY_D) - MATRIX_KEY(2, 6, KEY_F) - MATRIX_KEY(6, 2, KEY_G) - MATRIX_KEY(6, 6, KEY_H) - MATRIX_KEY(1, 4, KEY_J) - MATRIX_KEY(3, 1, KEY_K) - MATRIX_KEY(2, 1, KEY_L) - MATRIX_KEY(4, 6, KEY_ENTER) - - /* Row 4 */ - MATRIX_KEY(3, 6, KEY_LEFTSHIFT) /* KEY_CAPSLOCK */ - MATRIX_KEY(6, 1, KEY_Z) - MATRIX_KEY(7, 4, KEY_X) - MATRIX_KEY(5, 1, KEY_C) - MATRIX_KEY(1, 7, KEY_V) - MATRIX_KEY(2, 4, KEY_B) - MATRIX_KEY(4, 1, KEY_N) - MATRIX_KEY(1, 1, KEY_M) - MATRIX_KEY(3, 5, KEY_COMMA) - MATRIX_KEY(5, 2, KEY_DOT) - MATRIX_KEY(6, 3, KEY_UP) - MATRIX_KEY(7, 3, KEY_OK) - - /* Row 5 */ - MATRIX_KEY(2, 5, KEY_LEFTCTRL) /* KEY_LEFTSHIFT */ - MATRIX_KEY(4, 5, KEY_LEFTALT) /* SYM */ - MATRIX_KEY(6, 0, KEY_MINUS) - MATRIX_KEY(4, 7, KEY_EQUAL) - MATRIX_KEY(1, 5, KEY_SPACE) - MATRIX_KEY(3, 2, KEY_SLASH) - MATRIX_KEY(4, 3, KEY_LEFT) - MATRIX_KEY(5, 3, KEY_DOWN) - MATRIX_KEY(3, 3, KEY_RIGHT) - - /* Side buttons, KEY_VOLUMEDOWN and KEY_PWER are on CPCAP? */ - MATRIX_KEY(5, 0, KEY_VOLUMEUP) - >; -}; - -&mmc1 { - vmmc-supply = <&vwlan2>; - bus-width = <4>; - cd-gpios = <&gpio6 16 GPIO_ACTIVE_LOW>; /* gpio176 */ -}; - -&mmc2 { - vmmc-supply = <&vsdio>; - bus-width = <8>; - ti,non-removable; -}; - -&mmc3 { - vmmc-supply = <&wl12xx_vmmc>; - /* uart2_tx.sdmmc3_dat1 pad as wakeirq */ - interrupts-extended = <&wakeupgen GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH - &omap4_pmx_core 0xde>; - interrupt-names = "irq", "wakeup"; - non-removable; - bus-width = <4>; - cap-power-off-card; - keep-power-in-suspend; - - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@2 { - compatible = "ti,wl1285", "ti,wl1283"; - reg = <2>; - /* gpio_100 with gpmc_wait2 pad as wakeirq */ - interrupts-extended = <&gpio4 4 IRQ_TYPE_LEVEL_HIGH>, - <&omap4_pmx_core 0x4e>; - interrupt-names = "irq", "wakeup"; - ref-clock-frequency = <26000000>; - tcxo-clock-frequency = <26000000>; - }; -}; - -&i2c1 { - led-controller@38 { - compatible = "ti,lm3532"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x38>; - - enable-gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>; - - ramp-up-us = <1024>; - ramp-down-us = <8193>; - - backlight_led: led@0 { - reg = <0>; - led-sources = <2>; - ti,led-mode = <0>; - label = ":backlight"; - }; - - led@1 { - reg = <1>; - led-sources = <1>; - ti,led-mode = <0>; - label = ":kbd_backlight"; - }; - }; -}; - -&i2c2 { - touchscreen@4a { - compatible = "atmel,maxtouch"; - reg = <0x4a>; - pinctrl-names = "default"; - pinctrl-0 = <&touchscreen_pins>; - - reset-gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>; /* gpio173 */ - - /* gpio_183 with sys_nirq2 pad as wakeup */ - interrupts-extended = <&gpio6 23 IRQ_TYPE_LEVEL_LOW>, - <&omap4_pmx_core 0x160>; - interrupt-names = "irq", "wakeup"; - wakeup-source; - }; - - isl29030@44 { - compatible = "isil,isl29030"; - reg = <0x44>; - - pinctrl-names = "default"; - pinctrl-0 = <&als_proximity_pins>; - - interrupt-parent = <&gpio6>; - interrupts = <17 IRQ_TYPE_LEVEL_LOW>; /* gpio177 */ - }; -}; - -&omap4_pmx_core { - - /* hdmi_hpd.gpio_63 */ - hdmi_hpd_gpio: pinmux_hdmi_hpd_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x098, PIN_INPUT | MUX_MODE3) - >; - }; - - hdq_pins: pinmux_hdq_pins { - pinctrl-single,pins = < - /* 0x4a100120 hdq_sio.hdq_sio aa27 */ - OMAP4_IOPAD(0x120, PIN_INPUT | MUX_MODE0) - >; - }; - - /* hdmi_cec.hdmi_cec, hdmi_scl.hdmi_scl, hdmi_sda.hdmi_sda */ - dss_hdmi_pins: pinmux_dss_hdmi_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x09a, PIN_INPUT | MUX_MODE0) - OMAP4_IOPAD(0x09c, PIN_INPUT | MUX_MODE0) - OMAP4_IOPAD(0x09e, PIN_INPUT | MUX_MODE0) - >; - }; - - /* gpmc_ncs0.gpio_50 */ - poweroff_gpio: pinmux_poweroff_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x074, PIN_OUTPUT_PULLUP | MUX_MODE3) - >; - }; - - /* kpd_row0.gpio_178 */ - tmp105_irq: pinmux_tmp105_irq { - pinctrl-single,pins = < - OMAP4_IOPAD(0x18e, PIN_INPUT_PULLUP | MUX_MODE3) - >; - }; - - usb_gpio_mux_sel1: pinmux_usb_gpio_mux_sel1_pins { - /* gpio_60 */ - pinctrl-single,pins = < - OMAP4_IOPAD(0x088, PIN_OUTPUT | MUX_MODE3) - >; - }; - - touchscreen_pins: pinmux_touchscreen_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x180, PIN_OUTPUT | MUX_MODE3) - OMAP4_IOPAD(0x1a0, PIN_INPUT_PULLUP | MUX_MODE3) - >; - }; - - als_proximity_pins: pinmux_als_proximity_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x18c, PIN_INPUT_PULLUP | MUX_MODE3) - >; - }; - - usb_mdm6600_pins: pinmux_usb_mdm6600_pins { - pinctrl-single,pins = < - /* enable 0x4a1000d8 usbb1_ulpitll_dat7.gpio_95 ag16 */ - OMAP4_IOPAD(0x0d8, PIN_INPUT | MUX_MODE3) - - /* power 0x4a10007c gpmc_nwp.gpio_54 c25 */ - OMAP4_IOPAD(0x07c, PIN_OUTPUT | MUX_MODE3) - - /* reset 0x4a100072 gpmc_a25.gpio_49 d20 */ - OMAP4_IOPAD(0x072, PIN_OUTPUT | MUX_MODE3) - - /* mode0/bpwake 0x4a10014e sdmmc5_dat1.gpio_148 af4 */ - OMAP4_IOPAD(0x14e, PIN_OUTPUT | MUX_MODE3) - - /* mode1/apwake 0x4a100150 sdmmc5_dat2.gpio_149 ag3 */ - OMAP4_IOPAD(0x150, PIN_OFF_OUTPUT_LOW | PIN_INPUT | MUX_MODE3) - - /* status0 0x4a10007e gpmc_clk.gpio_55 b22 */ - OMAP4_IOPAD(0x07e, PIN_INPUT | MUX_MODE3) - - /* status1 0x4a10007a gpmc_ncs3.gpio_53 c22 */ - OMAP4_IOPAD(0x07a, PIN_INPUT | MUX_MODE3) - - /* status2 0x4a100078 gpmc_ncs2.gpio_52 d21 */ - OMAP4_IOPAD(0x078, PIN_INPUT | MUX_MODE3) - - /* cmd0 0x4a100094 gpmc_ncs6.gpio_103 c24 */ - OMAP4_IOPAD(0x094, PIN_OUTPUT | MUX_MODE3) - - /* cmd1 0x4a100096 gpmc_ncs7.gpio_104 d24 */ - OMAP4_IOPAD(0x096, PIN_OUTPUT | MUX_MODE3) - - /* cmd2 0x4a100142 uart3_rts_sd.gpio_142 f28 */ - OMAP4_IOPAD(0x142, PIN_OUTPUT | MUX_MODE3) - >; - }; - - usb_ulpi_pins: pinmux_usb_ulpi_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x196, MUX_MODE7) - OMAP4_IOPAD(0x198, MUX_MODE7) - OMAP4_IOPAD(0x1b2, PIN_INPUT_PULLUP | MUX_MODE0) - OMAP4_IOPAD(0x1b4, PIN_INPUT_PULLUP | MUX_MODE0) - OMAP4_IOPAD(0x1b6, PIN_INPUT_PULLUP | MUX_MODE0) - OMAP4_IOPAD(0x1b8, PIN_INPUT_PULLUP | MUX_MODE0) - OMAP4_IOPAD(0x1ba, PIN_INPUT_PULLUP | MUX_MODE0) - OMAP4_IOPAD(0x1bc, PIN_INPUT_PULLUP | MUX_MODE0) - OMAP4_IOPAD(0x1be, PIN_INPUT_PULLUP | MUX_MODE0) - OMAP4_IOPAD(0x1c0, PIN_INPUT_PULLUP | MUX_MODE0) - OMAP4_IOPAD(0x1c2, PIN_INPUT_PULLUP | MUX_MODE0) - OMAP4_IOPAD(0x1c4, PIN_INPUT_PULLUP | MUX_MODE0) - OMAP4_IOPAD(0x1c6, PIN_INPUT_PULLUP | MUX_MODE0) - OMAP4_IOPAD(0x1c8, PIN_INPUT_PULLUP | MUX_MODE0) - >; - }; - - /* usb0_otg_dp and usb0_otg_dm */ - usb_utmi_pins: pinmux_usb_utmi_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x196, PIN_INPUT | MUX_MODE0) - OMAP4_IOPAD(0x198, PIN_INPUT | MUX_MODE0) - OMAP4_IOPAD(0x1b2, PIN_INPUT_PULLUP | MUX_MODE7) - OMAP4_IOPAD(0x1b4, PIN_INPUT_PULLUP | MUX_MODE7) - OMAP4_IOPAD(0x1b6, PIN_INPUT_PULLUP | MUX_MODE7) - OMAP4_IOPAD(0x1b8, PIN_INPUT_PULLUP | MUX_MODE7) - OMAP4_IOPAD(0x1ba, PIN_INPUT_PULLUP | MUX_MODE7) - OMAP4_IOPAD(0x1bc, PIN_INPUT_PULLUP | MUX_MODE7) - OMAP4_IOPAD(0x1be, PIN_INPUT_PULLUP | MUX_MODE7) - OMAP4_IOPAD(0x1c0, PIN_INPUT_PULLUP | MUX_MODE7) - OMAP4_IOPAD(0x1c2, PIN_INPUT_PULLUP | MUX_MODE7) - OMAP4_IOPAD(0x1c4, PIN_INPUT_PULLUP | MUX_MODE7) - OMAP4_IOPAD(0x1c6, PIN_INPUT_PULLUP | MUX_MODE7) - OMAP4_IOPAD(0x1c8, PIN_INPUT_PULLUP | MUX_MODE7) - >; - }; - - /* - * Note that the v3.0.8 stock userspace dynamically remuxes uart1 - * rts pin probably for PM purposes to PIN_INPUT_PULLUP | MUX_MODE7 - * when not used. If needed, we can add rts pin remux later based - * on power measurements. - */ - uart1_pins: pinmux_uart1_pins { - pinctrl-single,pins = < - /* 0x4a10013c mcspi1_cs2.uart1_cts ag23 */ - OMAP4_IOPAD(0x13c, PIN_INPUT_PULLUP | MUX_MODE1) - - /* 0x4a10013e mcspi1_cs3.uart1_rts ah23 */ - OMAP4_IOPAD(0x13e, MUX_MODE1) - - /* 0x4a100140 uart3_cts_rctx.uart1_tx f27 */ - OMAP4_IOPAD(0x140, PIN_OUTPUT | MUX_MODE1) - - /* 0x4a1001ca dpm_emu14.uart1_rx aa3 */ - OMAP4_IOPAD(0x1ca, PIN_INPUT_PULLUP | MUX_MODE2) - >; - }; - - /* uart3_tx_irtx and uart3_rx_irrx */ - uart3_pins: pinmux_uart3_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x196, MUX_MODE7) - OMAP4_IOPAD(0x198, MUX_MODE7) - OMAP4_IOPAD(0x1b2, PIN_INPUT_PULLUP | MUX_MODE7) - OMAP4_IOPAD(0x1b4, PIN_INPUT_PULLUP | MUX_MODE7) - OMAP4_IOPAD(0x1b6, PIN_INPUT_PULLUP | MUX_MODE7) - OMAP4_IOPAD(0x1b8, PIN_INPUT_PULLUP | MUX_MODE7) - OMAP4_IOPAD(0x1ba, MUX_MODE2) - OMAP4_IOPAD(0x1bc, PIN_INPUT | MUX_MODE2) - OMAP4_IOPAD(0x1be, PIN_INPUT_PULLUP | MUX_MODE7) - OMAP4_IOPAD(0x1c0, PIN_INPUT_PULLUP | MUX_MODE7) - OMAP4_IOPAD(0x1c2, PIN_INPUT_PULLUP | MUX_MODE7) - OMAP4_IOPAD(0x1c4, PIN_INPUT_PULLUP | MUX_MODE7) - OMAP4_IOPAD(0x1c6, PIN_INPUT_PULLUP | MUX_MODE7) - OMAP4_IOPAD(0x1c8, PIN_INPUT_PULLUP | MUX_MODE7) - >; - }; - - uart4_pins: pinmux_uart4_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x15c, PIN_INPUT | MUX_MODE0) /* uart4_rx */ - OMAP4_IOPAD(0x15e, PIN_OUTPUT | MUX_MODE0) /* uart4_tx */ - OMAP4_IOPAD(0x110, PIN_INPUT_PULLUP | MUX_MODE5) /* uart4_cts */ - OMAP4_IOPAD(0x112, PIN_OUTPUT_PULLUP | MUX_MODE5) /* uart4_rts */ - >; - }; - - mcbsp2_pins: pinmux_mcbsp2_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x0f6, PIN_INPUT | MUX_MODE0) /* abe_mcbsp2_clkx */ - OMAP4_IOPAD(0x0f8, PIN_INPUT | MUX_MODE0) /* abe_mcbsp2_dr */ - OMAP4_IOPAD(0x0fa, PIN_OUTPUT | MUX_MODE0) /* abe_mcbsp2_dx */ - OMAP4_IOPAD(0x0fc, PIN_INPUT | MUX_MODE0) /* abe_mcbsp2_fsx */ - >; - }; - - mcbsp3_pins: pinmux_mcbsp3_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x106, PIN_INPUT | MUX_MODE1) /* abe_mcbsp3_dr */ - OMAP4_IOPAD(0x108, PIN_OUTPUT | MUX_MODE1) /* abe_mcbsp3_dx */ - OMAP4_IOPAD(0x10a, PIN_INPUT | MUX_MODE1) /* abe_mcbsp3_clkx */ - OMAP4_IOPAD(0x10c, PIN_INPUT | MUX_MODE1) /* abe_mcbsp3_fsx */ - >; - }; - - vibrator_direction_pin: pinmux_vibrator_direction_pin { - pinctrl-single,pins = < - OMAP4_IOPAD(0x1ce, PIN_OUTPUT | MUX_MODE1) /* dmtimer8_pwm_evt (gpio_27) */ - >; - }; - - vibrator_enable_pin: pinmux_vibrator_enable_pin { - pinctrl-single,pins = < - OMAP4_IOPAD(0X1d0, PIN_OUTPUT | MUX_MODE1) /* dmtimer9_pwm_evt (gpio_28) */ - >; - }; -}; - -&omap4_pmx_wkup { - usb_gpio_mux_sel2: pinmux_usb_gpio_mux_sel2_pins { - /* gpio_wk0 */ - pinctrl-single,pins = < - OMAP4_IOPAD(0x040, PIN_OUTPUT_PULLDOWN | MUX_MODE3) - >; - }; -}; - -/* RNG is used by secure mode and not accessible */ -&rng_target { - status = "disabled"; -}; - -/* Configure pwm clock source for timers 8 & 9 */ -&timer8 { - assigned-clocks = <&abe_clkctrl OMAP4_TIMER8_CLKCTRL 24>; - assigned-clock-parents = <&sys_clkin_ck>; -}; - -&timer9 { - assigned-clocks = <&l4_per_clkctrl OMAP4_TIMER9_CLKCTRL 24>; - assigned-clock-parents = <&sys_clkin_ck>; -}; - -/* - * As uart1 is wired to mdm6600 with rts and cts, we can use the cts pin for - * uart1 wakeirq. - */ -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; - interrupts-extended = <&wakeupgen GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH - &omap4_pmx_core 0xfc>; -}; - -&uart3 { - interrupts-extended = <&wakeupgen GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH - &omap4_pmx_core 0x17c>; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&uart4_pins>; - - bluetooth { - compatible = "ti,wl1285-st"; - enable-gpios = <&gpio6 14 GPIO_ACTIVE_HIGH>; /* gpio 174 */ - max-speed = <3686400>; - }; -}; - -&usbhsohci { - phys = <&fsusb1_phy>; - phy-names = "usb"; -}; - -&usbhsehci { - phys = <&hsusb2_phy>; -}; - -&usbhshost { - port1-mode = "ohci-phy-4pin-dpdm"; - port2-mode = "ehci-tll"; -}; - -/* Internal UTMI+ PHY used for OTG, CPCAP ULPI PHY for detection and charger */ -&usb_otg_hs { - interface-type = <1>; - mode = <3>; - - /* - * Max 300 mA steps based on similar PMIC MC13783UG.pdf "Table 10-4. - * VBUS Regulator Main Characteristics". Binding uses 2 mA units. - */ - power = <150>; -}; - -&i2c4 { - ak8975: magnetometer@c { - compatible = "asahi-kasei,ak8975"; - reg = <0x0c>; - - vdd-supply = <&vhvio>; - - interrupt-parent = <&gpio6>; - interrupts = <15 IRQ_TYPE_EDGE_RISING>; /* gpio175 */ - - rotation-matrix = "-1", "0", "0", - "0", "1", "0", - "0", "0", "-1"; - - }; - - lis3dh: accelerometer@18 { - compatible = "st,lis3dh-accel"; - reg = <0x18>; - - vdd-supply = <&vhvio>; - - interrupt-parent = <&gpio2>; - interrupts = <2 IRQ_TYPE_EDGE_BOTH>; /* gpio34 */ - - rotation-matrix = "0", "-1", "0", - "1", "0", "0", - "0", "0", "1"; - }; -}; - -&mcbsp2 { - #sound-dai-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&mcbsp2_pins>; - status = "okay"; - - mcbsp2_port: port { - cpu_dai2: endpoint { - dai-format = "i2s"; - remote-endpoint = <&cpcap_audio_codec0>; - frame-master = <&cpcap_audio_codec0>; - bitclock-master = <&cpcap_audio_codec0>; - }; - }; -}; - -&mcbsp3 { - #sound-dai-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&mcbsp3_pins>; - status = "okay"; - - mcbsp3_port: port { - cpu_dai3: endpoint { - dai-format = "dsp_a"; - frame-master = <&cpcap_audio_codec1>; - bitclock-master = <&cpcap_audio_codec1>; - remote-endpoint = <&cpcap_audio_codec1>; - }; - }; -}; - -&cpcap_audio_codec0 { - remote-endpoint = <&cpu_dai2>; -}; - -&cpcap_audio_codec1 { - remote-endpoint = <&cpu_dai3>; -}; diff --git a/sys/gnu/dts/arm/moxart-uc7112lx.dts b/sys/gnu/dts/arm/moxart-uc7112lx.dts deleted file mode 100644 index eb5291b0ee3..00000000000 --- a/sys/gnu/dts/arm/moxart-uc7112lx.dts +++ /dev/null @@ -1,116 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* moxart-uc7112lx.dts - Device Tree file for MOXA UC-7112-LX - * - * Copyright (C) 2013 Jonas Jensen - */ - -/dts-v1/; -#include "moxart.dtsi" - -/ { - model = "MOXA UC-7112-LX"; - compatible = "moxa,moxart-uc-7112-lx", "moxa,moxart"; - - memory { - device_type = "memory"; - reg = <0x0 0x2000000>; - }; - - clocks { - ref12: ref12M { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <12000000>; - }; - }; - - flash@80000000,0 { - compatible = "numonyx,js28f128", "cfi-flash"; - reg = <0x80000000 0x1000000>; - bank-width = <2>; - #address-cells = <1>; - #size-cells = <1>; - partition@0 { - label = "bootloader"; - reg = <0x0 0x40000>; - }; - partition@40000 { - label = "linux kernel"; - reg = <0x40000 0x1C0000>; - }; - partition@200000 { - label = "root filesystem"; - reg = <0x200000 0x800000>; - }; - partition@a00000 { - label = "user filesystem"; - reg = <0xa00000 0x600000>; - }; - }; - - leds { - compatible = "gpio-leds"; - user-led { - label = "ready-led"; - gpios = <&gpio 27 0x1>; - default-state = "on"; - linux,default-trigger = "default-on"; - }; - }; - - gpio_keys_polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <500>; - button@25 { - label = "GPIO Reset"; - linux,code = <116>; - gpios = <&gpio 25 1>; - }; - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk root=/dev/mmcblk0p1 rw rootwait"; - }; -}; - -&clk_pll { - clocks = <&ref12>; -}; - -&sdhci { - status = "okay"; -}; - -&mdio0 { - status = "okay"; - - ethphy0: ethernet-phy@1 { - device_type = "ethernet-phy"; - compatible = "moxa,moxart-rtl8201cp", "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; -}; - -&mdio1 { - status = "okay"; - - ethphy1: ethernet-phy@1 { - device_type = "ethernet-phy"; - compatible = "moxa,moxart-rtl8201cp", "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; -}; - -&mac0 { - status = "okay"; -}; - -&mac1 { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/moxart.dtsi b/sys/gnu/dts/arm/moxart.dtsi deleted file mode 100644 index f5f070a8748..00000000000 --- a/sys/gnu/dts/arm/moxart.dtsi +++ /dev/null @@ -1,151 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* moxart.dtsi - Device Tree Include file for MOXA ART family SoC - * - * Copyright (C) 2013 Jonas Jensen - */ - -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - compatible = "moxa,moxart"; - model = "MOXART"; - interrupt-parent = <&intc>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "faraday,fa526"; - reg = <0>; - }; - }; - - clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x90000000 0x10000000>; - ranges; - - intc: interrupt-controller@98800000 { - compatible = "moxa,moxart-ic", "faraday,ftintc010"; - reg = <0x98800000 0x100>; - interrupt-controller; - #interrupt-cells = <2>; - interrupt-mask = <0x00080000>; - }; - - clk_pll: clk_pll@98100000 { - compatible = "moxa,moxart-pll-clock"; - #clock-cells = <0>; - reg = <0x98100000 0x34>; - }; - - clk_apb: clk_apb@98100000 { - compatible = "moxa,moxart-apb-clock"; - #clock-cells = <0>; - reg = <0x98100000 0x34>; - clocks = <&clk_pll>; - }; - - timer: timer@98400000 { - compatible = "moxa,moxart-timer", "faraday,fttmr010"; - reg = <0x98400000 0x42>; - interrupts = <19 IRQ_TYPE_EDGE_FALLING>; - clocks = <&clk_apb>; - clock-names = "PCLK"; - }; - - gpio: gpio@98700000 { - gpio-controller; - #gpio-cells = <2>; - compatible = "moxa,moxart-gpio", "faraday,ftgpio010"; - reg = <0x98700000 0x100>; - }; - - rtc: rtc { - compatible = "moxa,moxart-rtc"; - gpio-rtc-sclk = <&gpio 5 0>; - gpio-rtc-data = <&gpio 6 0>; - gpio-rtc-reset = <&gpio 7 0>; - }; - - dma: dma@90500000 { - compatible = "moxa,moxart-dma"; - reg = <0x90500080 0x40>; - interrupts = <24 IRQ_TYPE_LEVEL_HIGH>; - #dma-cells = <1>; - }; - - watchdog: watchdog@98500000 { - compatible = "moxa,moxart-watchdog", "faraday,ftwdt010"; - reg = <0x98500000 0x10>; - clocks = <&clk_apb>; - clock-names = "PCLK"; - }; - - sdhci: sdhci@98e00000 { - compatible = "moxa,moxart-sdhci"; - reg = <0x98e00000 0x5C>; - interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk_apb>; - dmas = <&dma 5>, - <&dma 5>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - mdio0: mdio@90900090 { - compatible = "moxa,moxart-mdio"; - reg = <0x90900090 0x8>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - mdio1: mdio@92000090 { - compatible = "moxa,moxart-mdio"; - reg = <0x92000090 0x8>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - mac0: mac@90900000 { - compatible = "moxa,moxart-mac"; - reg = <0x90900000 0x90>; - interrupts = <25 IRQ_TYPE_LEVEL_HIGH>; - phy-handle = <ðphy0>; - phy-mode = "mii"; - status = "disabled"; - }; - - mac1: mac@92000000 { - compatible = "moxa,moxart-mac"; - reg = <0x92000000 0x90>; - interrupts = <27 IRQ_TYPE_LEVEL_HIGH>; - phy-handle = <ðphy1>; - phy-mode = "mii"; - status = "disabled"; - }; - - uart0: uart@98200000 { - compatible = "ns16550a"; - reg = <0x98200000 0x20>; - interrupts = <31 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <14745600>; - status = "disabled"; - }; - }; -}; diff --git a/sys/gnu/dts/arm/mpa1600.dts b/sys/gnu/dts/arm/mpa1600.dts deleted file mode 100644 index a5c91c240db..00000000000 --- a/sys/gnu/dts/arm/mpa1600.dts +++ /dev/null @@ -1,79 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * mpa1600.dts - Device Tree file for Phontech MPA 1600 - * - * Copyright (C) 2013 Joachim Eastwood - */ -/dts-v1/; -#include "at91rm9200.dtsi" - -/ { - model = "Phontech MPA 1600"; - compatible = "phontech,mpa1600", "atmel,at91rm9200"; - - memory { - reg = <0x20000000 0x4000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <18432000>; - }; - }; - - ahb { - apb { - dbgu: serial@fffff200 { - status = "okay"; - }; - - tcb0: timer@fffa0000 { - timer@0 { - compatible = "atmel,tcb-timer"; - reg = <0>, <1>; - }; - - timer@2 { - compatible = "atmel,tcb-timer"; - reg = <2>; - }; - }; - - macb0: ethernet@fffbc000 { - phy-mode = "rmii"; - status = "okay"; - }; - - ssc0: ssc@fffd0000 { - status = "okay"; - }; - - ssc1: ssc@fffd4000 { - status = "okay"; - }; - }; - - usb0: ohci@300000 { - num-ports = <1>; - status = "okay"; - }; - }; - - i2c-gpio-0 { - status = "okay"; - }; - - gpio_keys { - compatible = "gpio-keys"; - - monitor_mute { - label = "Monitor mute"; - gpios = <&pioC 1 GPIO_ACTIVE_LOW>; - linux,code = <113>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/mps2-an385.dts b/sys/gnu/dts/arm/mps2-an385.dts deleted file mode 100644 index aebbebfc25d..00000000000 --- a/sys/gnu/dts/arm/mps2-an385.dts +++ /dev/null @@ -1,92 +0,0 @@ -/* - * Copyright (C) 2015 ARM Limited - * - * Author: Vladimir Murzin - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include "mps2.dtsi" - -/ { - model = "ARM MPS2 Application Note 385/386"; - compatible = "arm,mps2"; - - aliases { - serial0 = &uart0; - }; - - chosen { - bootargs = "earlycon"; - stdout-path = "serial0:9600n8"; - }; - - memory@21000000 { - device_type = "memory"; - reg = <0x21000000 0x1000000>; - }; - - smb { - ethernet@0,0 { - compatible = "smsc,lan9220", "smsc,lan9115"; - reg = <0 0x0 0x10000>; - interrupts = <13>; - interrupt-parent = <&nvic>; - smsc,irq-active-high; - }; - }; -}; - -&uart0 { - status = "okay"; -}; - -&timer0 { - status = "okay"; -}; - -&timer1 { - status = "okay"; -}; - -&wdt { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/mps2-an399.dts b/sys/gnu/dts/arm/mps2-an399.dts deleted file mode 100644 index 349abf70b2a..00000000000 --- a/sys/gnu/dts/arm/mps2-an399.dts +++ /dev/null @@ -1,92 +0,0 @@ -/* - * Copyright (C) 2015 ARM Limited - * - * Author: Vladimir Murzin - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include "mps2.dtsi" - -/ { - model = "ARM MPS2 Application Note 399/400"; - compatible = "arm,mps2"; - - aliases { - serial0 = &uart0; - }; - - chosen { - bootargs = "earlycon"; - stdout-path = "serial0:9600n8"; - }; - - memory@60000000 { - device_type = "memory"; - reg = <0x60000000 0x1000000>; - }; - - smb { - ethernet@1,0 { - compatible = "smsc,lan9220", "smsc,lan9115"; - reg = <1 0x0 0x10000>; - interrupts = <13>; - interrupt-parent = <&nvic>; - smsc,irq-active-high; - }; - }; -}; - -&uart0 { - status = "okay"; -}; - -&timer0 { - status = "okay"; -}; - -&timer1 { - status = "okay"; -}; - -&wdt { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/mps2.dtsi b/sys/gnu/dts/arm/mps2.dtsi deleted file mode 100644 index 96fb5a5cf4d..00000000000 --- a/sys/gnu/dts/arm/mps2.dtsi +++ /dev/null @@ -1,244 +0,0 @@ -/* - * Copyright (C) 2015 ARM Limited - * - * Author: Vladimir Murzin - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "armv7-m.dtsi" - -/ { - #address-cells = <1>; - #size-cells = <1>; - - oscclk0: clk-osc0 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <50000000>; - }; - - oscclk1: clk-osc1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24576000>; - }; - - oscclk2: clk-osc2 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - - cfgclk: clk-cfg { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <5000000>; - }; - - spicfgclk: clk-spicfg { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <75000000>; - }; - - sysclk: clk-sys { - compatible = "fixed-factor-clock"; - clocks = <&oscclk0>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - - audmclk: clk-audm { - compatible = "fixed-factor-clock"; - clocks = <&oscclk1>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - - audsclk: clk-auds { - compatible = "fixed-factor-clock"; - clocks = <&oscclk1>; - #clock-cells = <0>; - clock-div = <8>; - clock-mult = <1>; - }; - - spiclcd: clk-cpiclcd { - compatible = "fixed-factor-clock"; - clocks = <&oscclk0>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - - spicon: clk-spicon { - compatible = "fixed-factor-clock"; - clocks = <&oscclk0>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - - i2cclcd: clk-i2cclcd { - compatible = "fixed-factor-clock"; - clocks = <&oscclk0>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - - i2caud: clk-i2caud { - compatible = "fixed-factor-clock"; - clocks = <&oscclk0>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - - soc { - compatible = "simple-bus"; - ranges; - - apb@40000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x40000000 0x10000>; - - timer0: mps2-timer0@0 { - compatible = "arm,mps2-timer"; - reg = <0x0 0x1000>; - interrupts = <8>; - clocks = <&sysclk>; - status = "disabled"; - }; - - timer1: mps2-timer1@1000 { - compatible = "arm,mps2-timer"; - reg = <0x1000 0x1000>; - interrupts = <9>; - clocks = <&sysclk>; - status = "disabled"; - }; - - timer2: dual-timer@2000 { - compatible = "arm,sp804"; - reg = <0x2000 0x1000>; - clocks = <&sysclk>; - interrupts = <10>; - status = "disabled"; - }; - - uart0: serial@4000 { - compatible = "arm,mps2-uart"; - reg = <0x4000 0x1000>; - interrupts = <0>, <1>, <12>; - clocks = <&sysclk>; - status = "disabled"; - }; - - uart1: serial@5000 { - compatible = "arm,mps2-uart"; - reg = <0x5000 0x1000>; - interrupts = <2>, <3>, <12>; - clocks = <&sysclk>; - status = "disabled"; - }; - - uart2: serial@6000 { - compatible = "arm,mps2-uart"; - reg = <0x6000 0x1000>; - interrupts = <4>, <5>, <12>; - clocks = <&sysclk>; - status = "disabled"; - }; - - wdt: watchdog@8000 { - compatible = "arm,sp805", "arm,primecell"; - arm,primecell-periphid = <0x00141805>; - reg = <0x8000 0x1000>; - interrupts = <0>; - clocks = <&sysclk>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - }; - }; - - fpga@40020000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x40020000 0x10000>; - - fpgaio@8000 { - compatible = "syscon", "simple-mfd"; - reg = <0x8000 0x10>; - - led0 { - compatible = "register-bit-led"; - offset = <0x0>; - mask = <0x01>; - label = "userled:0"; - linux,default-trigger = "heartbeat"; - default-state = "on"; - }; - - led1 { - compatible = "register-bit-led"; - offset = <0x0>; - mask = <0x02>; - label = "userled:1"; - linux,default-trigger = "usr"; - default-state = "off"; - }; - }; - }; - - smb { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0x40200000 0x10000>, - <1 0 0xa0000000 0x10000>; - }; -}; diff --git a/sys/gnu/dts/arm/mt2701-evb.dts b/sys/gnu/dts/arm/mt2701-evb.dts deleted file mode 100644 index 88f8fd22302..00000000000 --- a/sys/gnu/dts/arm/mt2701-evb.dts +++ /dev/null @@ -1,232 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2015 MediaTek Inc. - * Author: Erin Lo - * - */ - -/dts-v1/; -#include "mt2701.dtsi" - -/ { - model = "MediaTek MT2701 evaluation board"; - compatible = "mediatek,mt2701-evb", "mediatek,mt2701"; - - memory { - device_type = "memory"; - reg = <0 0x80000000 0 0x40000000>; - }; - - sound:sound { - compatible = "mediatek,mt2701-cs42448-machine"; - mediatek,platform = <&afe>; - /* CS42448 Machine name */ - audio-routing = - "Line Out Jack", "AOUT1L", - "Line Out Jack", "AOUT1R", - "Line Out Jack", "AOUT2L", - "Line Out Jack", "AOUT2R", - "Line Out Jack", "AOUT3L", - "Line Out Jack", "AOUT3R", - "Line Out Jack", "AOUT4L", - "Line Out Jack", "AOUT4R", - "AIN1L", "AMIC", - "AIN1R", "AMIC", - "AIN2L", "Tuner In", - "AIN2R", "Tuner In", - "AIN3L", "Satellite Tuner In", - "AIN3R", "Satellite Tuner In", - "AIN3L", "AUX In", - "AIN3R", "AUX In"; - mediatek,audio-codec = <&cs42448>; - mediatek,audio-codec-bt-mrg = <&bt_sco_codec>; - pinctrl-names = "default"; - pinctrl-0 = <&aud_pins_default>; - i2s1-in-sel-gpio1 = <&pio 53 0>; - i2s1-in-sel-gpio2 = <&pio 54 0>; - status = "okay"; - }; - - bt_sco_codec:bt_sco_codec { - compatible = "linux,bt-sco"; - }; - - backlight_lcd: backlight_lcd { - compatible = "pwm-backlight"; - pwms = <&bls 0 100000>; - brightness-levels = < - 0 16 32 48 64 80 96 112 - 128 144 160 176 192 208 224 240 - 255 - >; - default-brightness-level = <9>; - }; -}; - -&auxadc { - status = "okay"; -}; - -&bls { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm_bls_gpio>; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; - status = "okay"; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; - status = "okay"; - cs42448: cs42448@48 { - compatible = "cirrus,cs42448"; - reg = <0x48>; - clocks = <&topckgen CLK_TOP_AUD_I2S1_MCLK>; - clock-names = "mclk"; - }; -}; - -&pio { - i2c0_pins_a: i2c0@0 { - pins1 { - pinmux = , - ; - bias-disable; - }; - }; - - i2c1_pins_a: i2c1@0 { - pins1 { - pinmux = , - ; - bias-disable; - }; - }; - - i2c2_pins_a: i2c2@0 { - pins1 { - pinmux = , - ; - bias-disable; - }; - }; - - pwm_bls_gpio: pwm_bls_gpio { - pins_cmd_dat { - pinmux = ; - }; - }; - - spi_pins_a: spi0@0 { - pins_spi { - pinmux = , - , - , - ; - bias-disable; - }; - }; - - aud_pins_default: audiodefault { - pins_cmd_dat { - pinmux = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - drive-strength = ; - bias-pull-down; - }; - }; - - spi_pins_b: spi1@0 { - pins_spi { - pinmux = , - , - , - ; - bias-disable; - }; - }; - - spi_pins_c: spi2@0 { - pins_spi { - pinmux = , - , - , - ; - bias-disable; - }; - }; -}; - -&spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi_pins_a>; - status = "disabled"; -}; - -&spi1 { - pinctrl-names = "default"; - pinctrl-0 = <&spi_pins_b>; - status = "disabled"; -}; - -&spi2 { - pinctrl-names = "default"; - pinctrl-0 = <&spi_pins_c>; - status = "disabled"; -}; - -&nor_flash { - pinctrl-names = "default"; - pinctrl-0 = <&nor_pins_default>; - status = "okay"; - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - }; -}; - -&pio { - nor_pins_default: nor { - pins1 { - pinmux = , - , - , - , - , - ; - drive-strength = ; - bias-pull-up; - }; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/mt2701-pinfunc.h b/sys/gnu/dts/arm/mt2701-pinfunc.h deleted file mode 100644 index 136a25a0ae2..00000000000 --- a/sys/gnu/dts/arm/mt2701-pinfunc.h +++ /dev/null @@ -1,727 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2015 MediaTek Inc. - * Author: Biao Huang - */ - -#ifndef __DTS_MT2701_PINFUNC_H -#define __DTS_MT2701_PINFUNC_H - -#include - -#define MT2701_PIN_0_PWRAP_SPI0_MI__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) -#define MT2701_PIN_0_PWRAP_SPI0_MI__FUNC_PWRAP_SPIDO (MTK_PIN_NO(0) | 1) -#define MT2701_PIN_0_PWRAP_SPI0_MI__FUNC_PWRAP_SPIDI (MTK_PIN_NO(0) | 2) - -#define MT2701_PIN_1_PWRAP_SPI0_MO__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) -#define MT2701_PIN_1_PWRAP_SPI0_MO__FUNC_PWRAP_SPIDI (MTK_PIN_NO(1) | 1) -#define MT2701_PIN_1_PWRAP_SPI0_MO__FUNC_PWRAP_SPIDO (MTK_PIN_NO(1) | 2) - -#define MT2701_PIN_2_PWRAP_INT__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) -#define MT2701_PIN_2_PWRAP_INT__FUNC_PWRAP_INT (MTK_PIN_NO(2) | 1) - -#define MT2701_PIN_3_PWRAP_SPI0_CK__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) -#define MT2701_PIN_3_PWRAP_SPI0_CK__FUNC_PWRAP_SPICK_I (MTK_PIN_NO(3) | 1) - -#define MT2701_PIN_4_PWRAP_SPI0_CSN__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) -#define MT2701_PIN_4_PWRAP_SPI0_CSN__FUNC_PWRAP_SPICS_B_I (MTK_PIN_NO(4) | 1) - -#define MT2701_PIN_5_PWRAP_SPI0_CK2__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) -#define MT2701_PIN_5_PWRAP_SPI0_CK2__FUNC_PWRAP_SPICK2_I (MTK_PIN_NO(5) | 1) -#define MT2701_PIN_5_PWRAP_SPI0_CK2__FUNC_ANT_SEL1 (MTK_PIN_NO(5) | 5) - -#define MT2701_PIN_6_PWRAP_SPI0_CSN2__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) -#define MT2701_PIN_6_PWRAP_SPI0_CSN2__FUNC_PWRAP_SPICS2_B_I (MTK_PIN_NO(6) | 1) -#define MT2701_PIN_6_PWRAP_SPI0_CSN2__FUNC_ANT_SEL0 (MTK_PIN_NO(6) | 5) -#define MT2701_PIN_6_PWRAP_SPI0_CSN2__FUNC_DBG_MON_A_0 (MTK_PIN_NO(6) | 7) - -#define MT2701_PIN_7_SPI1_CSN__FUNC_GPIO7 (MTK_PIN_NO(7) | 0) -#define MT2701_PIN_7_SPI1_CSN__FUNC_SPI1_CS (MTK_PIN_NO(7) | 1) -#define MT2701_PIN_7_SPI1_CSN__FUNC_KCOL0 (MTK_PIN_NO(7) | 4) -#define MT2701_PIN_7_SPI1_CSN__FUNC_DBG_MON_B_12 (MTK_PIN_NO(7) | 7) - -#define MT2701_PIN_8_SPI1_MI__FUNC_GPIO8 (MTK_PIN_NO(8) | 0) -#define MT2701_PIN_8_SPI1_MI__FUNC_SPI1_MI (MTK_PIN_NO(8) | 1) -#define MT2701_PIN_8_SPI1_MI__FUNC_SPI1_MO (MTK_PIN_NO(8) | 2) -#define MT2701_PIN_8_SPI1_MI__FUNC_KCOL1 (MTK_PIN_NO(8) | 4) -#define MT2701_PIN_8_SPI1_MI__FUNC_DBG_MON_B_13 (MTK_PIN_NO(8) | 7) - -#define MT2701_PIN_9_SPI1_MO__FUNC_GPIO9 (MTK_PIN_NO(9) | 0) -#define MT2701_PIN_9_SPI1_MO__FUNC_SPI1_MO (MTK_PIN_NO(9) | 1) -#define MT2701_PIN_9_SPI1_MO__FUNC_SPI1_MI (MTK_PIN_NO(9) | 2) -#define MT2701_PIN_9_SPI1_MO__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(9) | 3) -#define MT2701_PIN_9_SPI1_MO__FUNC_KCOL2 (MTK_PIN_NO(9) | 4) -#define MT2701_PIN_9_SPI1_MO__FUNC_DBG_MON_B_14 (MTK_PIN_NO(9) | 7) - -#define MT2701_PIN_10_RTC32K_CK__FUNC_GPIO10 (MTK_PIN_NO(10) | 0) -#define MT2701_PIN_10_RTC32K_CK__FUNC_RTC32K_CK (MTK_PIN_NO(10) | 1) - -#define MT2701_PIN_11_WATCHDOG__FUNC_GPIO11 (MTK_PIN_NO(11) | 0) -#define MT2701_PIN_11_WATCHDOG__FUNC_WATCHDOG (MTK_PIN_NO(11) | 1) - -#define MT2701_PIN_12_SRCLKENA__FUNC_GPIO12 (MTK_PIN_NO(12) | 0) -#define MT2701_PIN_12_SRCLKENA__FUNC_SRCLKENA (MTK_PIN_NO(12) | 1) - -#define MT2701_PIN_13_SRCLKENAI__FUNC_GPIO13 (MTK_PIN_NO(13) | 0) -#define MT2701_PIN_13_SRCLKENAI__FUNC_SRCLKENAI (MTK_PIN_NO(13) | 1) - -#define MT2701_PIN_14_URXD2__FUNC_GPIO14 (MTK_PIN_NO(14) | 0) -#define MT2701_PIN_14_URXD2__FUNC_URXD2 (MTK_PIN_NO(14) | 1) -#define MT2701_PIN_14_URXD2__FUNC_UTXD2 (MTK_PIN_NO(14) | 2) -#define MT2701_PIN_14_URXD2__FUNC_SRCCLKENAI2 (MTK_PIN_NO(14) | 5) -#define MT2701_PIN_14_URXD2__FUNC_DBG_MON_B_30 (MTK_PIN_NO(14) | 7) - -#define MT2701_PIN_15_UTXD2__FUNC_GPIO15 (MTK_PIN_NO(15) | 0) -#define MT2701_PIN_15_UTXD2__FUNC_UTXD2 (MTK_PIN_NO(15) | 1) -#define MT2701_PIN_15_UTXD2__FUNC_URXD2 (MTK_PIN_NO(15) | 2) -#define MT2701_PIN_15_UTXD2__FUNC_DBG_MON_B_31 (MTK_PIN_NO(15) | 7) - -#define MT2701_PIN_18_PCM_CLK__FUNC_GPIO18 (MTK_PIN_NO(18) | 0) -#define MT2701_PIN_18_PCM_CLK__FUNC_PCM_CLK0 (MTK_PIN_NO(18) | 1) -#define MT2701_PIN_18_PCM_CLK__FUNC_MRG_CLK (MTK_PIN_NO(18) | 2) -#define MT2701_PIN_18_PCM_CLK__FUNC_MM_TEST_CK (MTK_PIN_NO(18) | 4) -#define MT2701_PIN_18_PCM_CLK__FUNC_CONN_DSP_JCK (MTK_PIN_NO(18) | 5) -#define MT2701_PIN_18_PCM_CLK__FUNC_WCN_PCM_CLKO (MTK_PIN_NO(18) | 6) -#define MT2701_PIN_18_PCM_CLK__FUNC_DBG_MON_A_3 (MTK_PIN_NO(18) | 7) - -#define MT2701_PIN_19_PCM_SYNC__FUNC_GPIO19 (MTK_PIN_NO(19) | 0) -#define MT2701_PIN_19_PCM_SYNC__FUNC_PCM_SYNC (MTK_PIN_NO(19) | 1) -#define MT2701_PIN_19_PCM_SYNC__FUNC_MRG_SYNC (MTK_PIN_NO(19) | 2) -#define MT2701_PIN_19_PCM_SYNC__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(19) | 5) -#define MT2701_PIN_19_PCM_SYNC__FUNC_WCN_PCM_SYNC (MTK_PIN_NO(19) | 6) -#define MT2701_PIN_19_PCM_SYNC__FUNC_DBG_MON_A_5 (MTK_PIN_NO(19) | 7) - -#define MT2701_PIN_20_PCM_RX__FUNC_GPIO20 (MTK_PIN_NO(20) | 0) -#define MT2701_PIN_20_PCM_RX__FUNC_PCM_RX (MTK_PIN_NO(20) | 1) -#define MT2701_PIN_20_PCM_RX__FUNC_MRG_RX (MTK_PIN_NO(20) | 2) -#define MT2701_PIN_20_PCM_RX__FUNC_MRG_TX (MTK_PIN_NO(20) | 3) -#define MT2701_PIN_20_PCM_RX__FUNC_PCM_TX (MTK_PIN_NO(20) | 4) -#define MT2701_PIN_20_PCM_RX__FUNC_CONN_DSP_JDI (MTK_PIN_NO(20) | 5) -#define MT2701_PIN_20_PCM_RX__FUNC_WCN_PCM_RX (MTK_PIN_NO(20) | 6) -#define MT2701_PIN_20_PCM_RX__FUNC_DBG_MON_A_4 (MTK_PIN_NO(20) | 7) - -#define MT2701_PIN_21_PCM_TX__FUNC_GPIO21 (MTK_PIN_NO(21) | 0) -#define MT2701_PIN_21_PCM_TX__FUNC_PCM_TX (MTK_PIN_NO(21) | 1) -#define MT2701_PIN_21_PCM_TX__FUNC_MRG_TX (MTK_PIN_NO(21) | 2) -#define MT2701_PIN_21_PCM_TX__FUNC_MRG_RX (MTK_PIN_NO(21) | 3) -#define MT2701_PIN_21_PCM_TX__FUNC_PCM_RX (MTK_PIN_NO(21) | 4) -#define MT2701_PIN_21_PCM_TX__FUNC_CONN_DSP_JMS (MTK_PIN_NO(21) | 5) -#define MT2701_PIN_21_PCM_TX__FUNC_WCN_PCM_TX (MTK_PIN_NO(21) | 6) -#define MT2701_PIN_21_PCM_TX__FUNC_DBG_MON_A_2 (MTK_PIN_NO(21) | 7) - -#define MT2701_PIN_22_EINT0__FUNC_GPIO22 (MTK_PIN_NO(22) | 0) -#define MT2701_PIN_22_EINT0__FUNC_UCTS0 (MTK_PIN_NO(22) | 1) -#define MT2701_PIN_22_EINT0__FUNC_KCOL3 (MTK_PIN_NO(22) | 3) -#define MT2701_PIN_22_EINT0__FUNC_CONN_DSP_JDO (MTK_PIN_NO(22) | 4) -#define MT2701_PIN_22_EINT0__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(22) | 5) -#define MT2701_PIN_22_EINT0__FUNC_DBG_MON_A_30 (MTK_PIN_NO(22) | 7) -#define MT2701_PIN_22_EINT0__FUNC_PCIE0_PERST_N (MTK_PIN_NO(22) | 10) - -#define MT2701_PIN_23_EINT1__FUNC_GPIO23 (MTK_PIN_NO(23) | 0) -#define MT2701_PIN_23_EINT1__FUNC_URTS0 (MTK_PIN_NO(23) | 1) -#define MT2701_PIN_23_EINT1__FUNC_KCOL2 (MTK_PIN_NO(23) | 3) -#define MT2701_PIN_23_EINT1__FUNC_CONN_MCU_TDO (MTK_PIN_NO(23) | 4) -#define MT2701_PIN_23_EINT1__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(23) | 5) -#define MT2701_PIN_23_EINT1__FUNC_DBG_MON_A_29 (MTK_PIN_NO(23) | 7) -#define MT2701_PIN_23_EINT1__FUNC_PCIE1_PERST_N (MTK_PIN_NO(23) | 10) - -#define MT2701_PIN_24_EINT2__FUNC_GPIO24 (MTK_PIN_NO(24) | 0) -#define MT2701_PIN_24_EINT2__FUNC_UCTS1 (MTK_PIN_NO(24) | 1) -#define MT2701_PIN_24_EINT2__FUNC_KCOL1 (MTK_PIN_NO(24) | 3) -#define MT2701_PIN_24_EINT2__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(24) | 4) -#define MT2701_PIN_24_EINT2__FUNC_DBG_MON_A_28 (MTK_PIN_NO(24) | 7) -#define MT2701_PIN_24_EINT2__FUNC_PCIE2_PERST_N (MTK_PIN_NO(24) | 10) - -#define MT2701_PIN_25_EINT3__FUNC_GPIO25 (MTK_PIN_NO(25) | 0) -#define MT2701_PIN_25_EINT3__FUNC_URTS1 (MTK_PIN_NO(25) | 1) -#define MT2701_PIN_25_EINT3__FUNC_KCOL0 (MTK_PIN_NO(25) | 3) -#define MT2701_PIN_25_EINT3__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(25) | 4) -#define MT2701_PIN_25_EINT3__FUNC_DBG_MON_A_27 (MTK_PIN_NO(25) | 7) - -#define MT2701_PIN_26_EINT4__FUNC_GPIO26 (MTK_PIN_NO(26) | 0) -#define MT2701_PIN_26_EINT4__FUNC_UCTS3 (MTK_PIN_NO(26) | 1) -#define MT2701_PIN_26_EINT4__FUNC_DRV_VBUS_P1 (MTK_PIN_NO(26) | 2) -#define MT2701_PIN_26_EINT4__FUNC_KROW3 (MTK_PIN_NO(26) | 3) -#define MT2701_PIN_26_EINT4__FUNC_CONN_MCU_TCK0 (MTK_PIN_NO(26) | 4) -#define MT2701_PIN_26_EINT4__FUNC_CONN_MCU_AICE_JCKC (MTK_PIN_NO(26) | 5) -#define MT2701_PIN_26_EINT4__FUNC_PCIE2_WAKE_N (MTK_PIN_NO(26) | 6) -#define MT2701_PIN_26_EINT4__FUNC_DBG_MON_A_26 (MTK_PIN_NO(26) | 7) - -#define MT2701_PIN_27_EINT5__FUNC_GPIO27 (MTK_PIN_NO(27) | 0) -#define MT2701_PIN_27_EINT5__FUNC_URTS3 (MTK_PIN_NO(27) | 1) -#define MT2701_PIN_27_EINT5__FUNC_IDDIG_P1 (MTK_PIN_NO(27) | 2) -#define MT2701_PIN_27_EINT5__FUNC_KROW2 (MTK_PIN_NO(27) | 3) -#define MT2701_PIN_27_EINT5__FUNC_CONN_MCU_TDI (MTK_PIN_NO(27) | 4) -#define MT2701_PIN_27_EINT5__FUNC_PCIE1_WAKE_N (MTK_PIN_NO(27) | 6) -#define MT2701_PIN_27_EINT5__FUNC_DBG_MON_A_25 (MTK_PIN_NO(27) | 7) - -#define MT2701_PIN_28_EINT6__FUNC_GPIO28 (MTK_PIN_NO(28) | 0) -#define MT2701_PIN_28_EINT6__FUNC_DRV_VBUS (MTK_PIN_NO(28) | 1) -#define MT2701_PIN_28_EINT6__FUNC_KROW1 (MTK_PIN_NO(28) | 3) -#define MT2701_PIN_28_EINT6__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(28) | 4) -#define MT2701_PIN_28_EINT6__FUNC_PCIE0_WAKE_N (MTK_PIN_NO(28) | 6) -#define MT2701_PIN_28_EINT6__FUNC_DBG_MON_A_24 (MTK_PIN_NO(28) | 7) - -#define MT2701_PIN_29_EINT7__FUNC_GPIO29 (MTK_PIN_NO(29) | 0) -#define MT2701_PIN_29_EINT7__FUNC_IDDIG (MTK_PIN_NO(29) | 1) -#define MT2701_PIN_29_EINT7__FUNC_MSDC1_WP (MTK_PIN_NO(29) | 2) -#define MT2701_PIN_29_EINT7__FUNC_KROW0 (MTK_PIN_NO(29) | 3) -#define MT2701_PIN_29_EINT7__FUNC_CONN_MCU_TMS (MTK_PIN_NO(29) | 4) -#define MT2701_PIN_29_EINT7__FUNC_CONN_MCU_AICE_JMSC (MTK_PIN_NO(29) | 5) -#define MT2701_PIN_29_EINT7__FUNC_DBG_MON_A_23 (MTK_PIN_NO(29) | 7) -#define MT2701_PIN_29_EINT7__FUNC_PCIE2_PERST_N (MTK_PIN_NO(29) | 14) - -#define MT2701_PIN_33_I2S1_DATA__FUNC_GPIO33 (MTK_PIN_NO(33) | 0) -#define MT2701_PIN_33_I2S1_DATA__FUNC_I2S1_DATA (MTK_PIN_NO(33) | 1) -#define MT2701_PIN_33_I2S1_DATA__FUNC_I2S1_DATA_BYPS (MTK_PIN_NO(33) | 2) -#define MT2701_PIN_33_I2S1_DATA__FUNC_PCM_TX (MTK_PIN_NO(33) | 3) -#define MT2701_PIN_33_I2S1_DATA__FUNC_IMG_TEST_CK (MTK_PIN_NO(33) | 4) -#define MT2701_PIN_33_I2S1_DATA__FUNC_G1_RXD0 (MTK_PIN_NO(33) | 5) -#define MT2701_PIN_33_I2S1_DATA__FUNC_WCN_PCM_TX (MTK_PIN_NO(33) | 6) -#define MT2701_PIN_33_I2S1_DATA__FUNC_DBG_MON_B_8 (MTK_PIN_NO(33) | 7) - -#define MT2701_PIN_34_I2S1_DATA_IN__FUNC_GPIO34 (MTK_PIN_NO(34) | 0) -#define MT2701_PIN_34_I2S1_DATA_IN__FUNC_I2S1_DATA_IN (MTK_PIN_NO(34) | 1) -#define MT2701_PIN_34_I2S1_DATA_IN__FUNC_PCM_RX (MTK_PIN_NO(34) | 3) -#define MT2701_PIN_34_I2S1_DATA_IN__FUNC_VDEC_TEST_CK (MTK_PIN_NO(34) | 4) -#define MT2701_PIN_34_I2S1_DATA_IN__FUNC_G1_RXD1 (MTK_PIN_NO(34) | 5) -#define MT2701_PIN_34_I2S1_DATA_IN__FUNC_WCN_PCM_RX (MTK_PIN_NO(34) | 6) -#define MT2701_PIN_34_I2S1_DATA_IN__FUNC_DBG_MON_B_7 (MTK_PIN_NO(34) | 7) - -#define MT2701_PIN_35_I2S1_BCK__FUNC_GPIO35 (MTK_PIN_NO(35) | 0) -#define MT2701_PIN_35_I2S1_BCK__FUNC_I2S1_BCK (MTK_PIN_NO(35) | 1) -#define MT2701_PIN_35_I2S1_BCK__FUNC_PCM_CLK0 (MTK_PIN_NO(35) | 3) -#define MT2701_PIN_35_I2S1_BCK__FUNC_G1_RXD2 (MTK_PIN_NO(35) | 5) -#define MT2701_PIN_35_I2S1_BCK__FUNC_WCN_PCM_CLKO (MTK_PIN_NO(35) | 6) -#define MT2701_PIN_35_I2S1_BCK__FUNC_DBG_MON_B_9 (MTK_PIN_NO(35) | 7) - -#define MT2701_PIN_36_I2S1_LRCK__FUNC_GPIO36 (MTK_PIN_NO(36) | 0) -#define MT2701_PIN_36_I2S1_LRCK__FUNC_I2S1_LRCK (MTK_PIN_NO(36) | 1) -#define MT2701_PIN_36_I2S1_LRCK__FUNC_PCM_SYNC (MTK_PIN_NO(36) | 3) -#define MT2701_PIN_36_I2S1_LRCK__FUNC_G1_RXD3 (MTK_PIN_NO(36) | 5) -#define MT2701_PIN_36_I2S1_LRCK__FUNC_WCN_PCM_SYNC (MTK_PIN_NO(36) | 6) -#define MT2701_PIN_36_I2S1_LRCK__FUNC_DBG_MON_B_10 (MTK_PIN_NO(36) | 7) - -#define MT2701_PIN_37_I2S1_MCLK__FUNC_GPIO37 (MTK_PIN_NO(37) | 0) -#define MT2701_PIN_37_I2S1_MCLK__FUNC_I2S1_MCLK (MTK_PIN_NO(37) | 1) -#define MT2701_PIN_37_I2S1_MCLK__FUNC_G1_RXDV (MTK_PIN_NO(37) | 5) -#define MT2701_PIN_37_I2S1_MCLK__FUNC_DBG_MON_B_11 (MTK_PIN_NO(37) | 7) - -#define MT2701_PIN_39_JTMS__FUNC_GPIO39 (MTK_PIN_NO(39) | 0) -#define MT2701_PIN_39_JTMS__FUNC_JTMS (MTK_PIN_NO(39) | 1) -#define MT2701_PIN_39_JTMS__FUNC_CONN_MCU_TMS (MTK_PIN_NO(39) | 2) -#define MT2701_PIN_39_JTMS__FUNC_CONN_MCU_AICE_JMSC (MTK_PIN_NO(39) | 3) -#define MT2701_PIN_39_JTMS__FUNC_DFD_TMS_XI (MTK_PIN_NO(39) | 4) - -#define MT2701_PIN_40_JTCK__FUNC_GPIO40 (MTK_PIN_NO(40) | 0) -#define MT2701_PIN_40_JTCK__FUNC_JTCK (MTK_PIN_NO(40) | 1) -#define MT2701_PIN_40_JTCK__FUNC_CONN_MCU_TCK1 (MTK_PIN_NO(40) | 2) -#define MT2701_PIN_40_JTCK__FUNC_CONN_MCU_AICE_JCKC (MTK_PIN_NO(40) | 3) -#define MT2701_PIN_40_JTCK__FUNC_DFD_TCK_XI (MTK_PIN_NO(40) | 4) - -#define MT2701_PIN_41_JTDI__FUNC_GPIO41 (MTK_PIN_NO(41) | 0) -#define MT2701_PIN_41_JTDI__FUNC_JTDI (MTK_PIN_NO(41) | 1) -#define MT2701_PIN_41_JTDI__FUNC_CONN_MCU_TDI (MTK_PIN_NO(41) | 2) -#define MT2701_PIN_41_JTDI__FUNC_DFD_TDI_XI (MTK_PIN_NO(41) | 4) - -#define MT2701_PIN_42_JTDO__FUNC_GPIO42 (MTK_PIN_NO(42) | 0) -#define MT2701_PIN_42_JTDO__FUNC_JTDO (MTK_PIN_NO(42) | 1) -#define MT2701_PIN_42_JTDO__FUNC_CONN_MCU_TDO (MTK_PIN_NO(42) | 2) -#define MT2701_PIN_42_JTDO__FUNC_DFD_TDO (MTK_PIN_NO(42) | 4) - -#define MT2701_PIN_43_NCLE__FUNC_GPIO43 (MTK_PIN_NO(43) | 0) -#define MT2701_PIN_43_NCLE__FUNC_NCLE (MTK_PIN_NO(43) | 1) -#define MT2701_PIN_43_NCLE__FUNC_EXT_XCS2 (MTK_PIN_NO(43) | 2) - -#define MT2701_PIN_44_NCEB1__FUNC_GPIO44 (MTK_PIN_NO(44) | 0) -#define MT2701_PIN_44_NCEB1__FUNC_NCEB1 (MTK_PIN_NO(44) | 1) -#define MT2701_PIN_44_NCEB1__FUNC_IDDIG (MTK_PIN_NO(44) | 2) - -#define MT2701_PIN_45_NCEB0__FUNC_GPIO45 (MTK_PIN_NO(45) | 0) -#define MT2701_PIN_45_NCEB0__FUNC_NCEB0 (MTK_PIN_NO(45) | 1) -#define MT2701_PIN_45_NCEB0__FUNC_DRV_VBUS (MTK_PIN_NO(45) | 2) - -#define MT2701_PIN_46_IR__FUNC_GPIO46 (MTK_PIN_NO(46) | 0) -#define MT2701_PIN_46_IR__FUNC_IR (MTK_PIN_NO(46) | 1) - -#define MT2701_PIN_47_NREB__FUNC_GPIO47 (MTK_PIN_NO(47) | 0) -#define MT2701_PIN_47_NREB__FUNC_NREB (MTK_PIN_NO(47) | 1) -#define MT2701_PIN_47_NREB__FUNC_IDDIG_P1 (MTK_PIN_NO(47) | 2) - -#define MT2701_PIN_48_NRNB__FUNC_GPIO48 (MTK_PIN_NO(48) | 0) -#define MT2701_PIN_48_NRNB__FUNC_NRNB (MTK_PIN_NO(48) | 1) -#define MT2701_PIN_48_NRNB__FUNC_DRV_VBUS_P1 (MTK_PIN_NO(48) | 2) - -#define MT2701_PIN_49_I2S0_DATA__FUNC_GPIO49 (MTK_PIN_NO(49) | 0) -#define MT2701_PIN_49_I2S0_DATA__FUNC_I2S0_DATA (MTK_PIN_NO(49) | 1) -#define MT2701_PIN_49_I2S0_DATA__FUNC_I2S0_DATA_BYPS (MTK_PIN_NO(49) | 2) -#define MT2701_PIN_49_I2S0_DATA__FUNC_PCM_TX (MTK_PIN_NO(49) | 3) -#define MT2701_PIN_49_I2S0_DATA__FUNC_WCN_I2S_DO (MTK_PIN_NO(49) | 6) -#define MT2701_PIN_49_I2S0_DATA__FUNC_DBG_MON_B_3 (MTK_PIN_NO(49) | 7) - -#define MT2701_PIN_53_SPI0_CSN__FUNC_GPIO53 (MTK_PIN_NO(53) | 0) -#define MT2701_PIN_53_SPI0_CSN__FUNC_SPI0_CS (MTK_PIN_NO(53) | 1) -#define MT2701_PIN_53_SPI0_CSN__FUNC_SPDIF (MTK_PIN_NO(53) | 3) -#define MT2701_PIN_53_SPI0_CSN__FUNC_ADC_CK (MTK_PIN_NO(53) | 4) -#define MT2701_PIN_53_SPI0_CSN__FUNC_PWM1 (MTK_PIN_NO(53) | 5) -#define MT2701_PIN_53_SPI0_CSN__FUNC_DBG_MON_A_7 (MTK_PIN_NO(53) | 7) - -#define MT2701_PIN_54_SPI0_CK__FUNC_GPIO54 (MTK_PIN_NO(54) | 0) -#define MT2701_PIN_54_SPI0_CK__FUNC_SPI0_CK (MTK_PIN_NO(54) | 1) -#define MT2701_PIN_54_SPI0_CK__FUNC_SPDIF_IN1 (MTK_PIN_NO(54) | 3) -#define MT2701_PIN_54_SPI0_CK__FUNC_ADC_DAT_IN (MTK_PIN_NO(54) | 4) -#define MT2701_PIN_54_SPI0_CK__FUNC_DBG_MON_A_10 (MTK_PIN_NO(54) | 7) - -#define MT2701_PIN_55_SPI0_MI__FUNC_GPIO55 (MTK_PIN_NO(55) | 0) -#define MT2701_PIN_55_SPI0_MI__FUNC_SPI0_MI (MTK_PIN_NO(55) | 1) -#define MT2701_PIN_55_SPI0_MI__FUNC_SPI0_MO (MTK_PIN_NO(55) | 2) -#define MT2701_PIN_55_SPI0_MI__FUNC_MSDC1_WP (MTK_PIN_NO(55) | 3) -#define MT2701_PIN_55_SPI0_MI__FUNC_ADC_WS (MTK_PIN_NO(55) | 4) -#define MT2701_PIN_55_SPI0_MI__FUNC_PWM2 (MTK_PIN_NO(55) | 5) -#define MT2701_PIN_55_SPI0_MI__FUNC_DBG_MON_A_8 (MTK_PIN_NO(55) | 7) - -#define MT2701_PIN_56_SPI0_MO__FUNC_GPIO56 (MTK_PIN_NO(56) | 0) -#define MT2701_PIN_56_SPI0_MO__FUNC_SPI0_MO (MTK_PIN_NO(56) | 1) -#define MT2701_PIN_56_SPI0_MO__FUNC_SPI0_MI (MTK_PIN_NO(56) | 2) -#define MT2701_PIN_56_SPI0_MO__FUNC_SPDIF_IN0 (MTK_PIN_NO(56) | 3) -#define MT2701_PIN_56_SPI0_MO__FUNC_DBG_MON_A_9 (MTK_PIN_NO(56) | 7) - -#define MT2701_PIN_57_SDA1__FUNC_GPIO57 (MTK_PIN_NO(57) | 0) -#define MT2701_PIN_57_SDA1__FUNC_SDA1 (MTK_PIN_NO(57) | 1) - -#define MT2701_PIN_58_SCL1__FUNC_GPIO58 (MTK_PIN_NO(58) | 0) -#define MT2701_PIN_58_SCL1__FUNC_SCL1 (MTK_PIN_NO(58) | 1) - -#define MT2701_PIN_72_I2S0_DATA_IN__FUNC_GPIO72 (MTK_PIN_NO(72) | 0) -#define MT2701_PIN_72_I2S0_DATA_IN__FUNC_I2S0_DATA_IN (MTK_PIN_NO(72) | 1) -#define MT2701_PIN_72_I2S0_DATA_IN__FUNC_PCM_RX (MTK_PIN_NO(72) | 3) -#define MT2701_PIN_72_I2S0_DATA_IN__FUNC_PWM0 (MTK_PIN_NO(72) | 4) -#define MT2701_PIN_72_I2S0_DATA_IN__FUNC_DISP_PWM (MTK_PIN_NO(72) | 5) -#define MT2701_PIN_72_I2S0_DATA_IN__FUNC_WCN_I2S_DI (MTK_PIN_NO(72) | 6) -#define MT2701_PIN_72_I2S0_DATA_IN__FUNC_DBG_MON_B_2 (MTK_PIN_NO(72) | 7) - -#define MT2701_PIN_73_I2S0_LRCK__FUNC_GPIO73 (MTK_PIN_NO(73) | 0) -#define MT2701_PIN_73_I2S0_LRCK__FUNC_I2S0_LRCK (MTK_PIN_NO(73) | 1) -#define MT2701_PIN_73_I2S0_LRCK__FUNC_PCM_SYNC (MTK_PIN_NO(73) | 3) -#define MT2701_PIN_73_I2S0_LRCK__FUNC_WCN_I2S_LRCK (MTK_PIN_NO(73) | 6) -#define MT2701_PIN_73_I2S0_LRCK__FUNC_DBG_MON_B_5 (MTK_PIN_NO(73) | 7) - -#define MT2701_PIN_74_I2S0_BCK__FUNC_GPIO74 (MTK_PIN_NO(74) | 0) -#define MT2701_PIN_74_I2S0_BCK__FUNC_I2S0_BCK (MTK_PIN_NO(74) | 1) -#define MT2701_PIN_74_I2S0_BCK__FUNC_PCM_CLK0 (MTK_PIN_NO(74) | 3) -#define MT2701_PIN_74_I2S0_BCK__FUNC_WCN_I2S_BCK (MTK_PIN_NO(74) | 6) -#define MT2701_PIN_74_I2S0_BCK__FUNC_DBG_MON_B_4 (MTK_PIN_NO(74) | 7) - -#define MT2701_PIN_75_SDA0__FUNC_GPIO75 (MTK_PIN_NO(75) | 0) -#define MT2701_PIN_75_SDA0__FUNC_SDA0 (MTK_PIN_NO(75) | 1) - -#define MT2701_PIN_76_SCL0__FUNC_GPIO76 (MTK_PIN_NO(76) | 0) -#define MT2701_PIN_76_SCL0__FUNC_SCL0 (MTK_PIN_NO(76) | 1) - -#define MT2701_PIN_77_SDA2__FUNC_GPIO77 (MTK_PIN_NO(77) | 0) -#define MT2701_PIN_77_SDA2__FUNC_SDA2 (MTK_PIN_NO(77) | 1) - -#define MT2701_PIN_78_SCL2__FUNC_GPIO78 (MTK_PIN_NO(78) | 0) -#define MT2701_PIN_78_SCL2__FUNC_SCL2 (MTK_PIN_NO(78) | 1) - -#define MT2701_PIN_79_URXD0__FUNC_GPIO79 (MTK_PIN_NO(79) | 0) -#define MT2701_PIN_79_URXD0__FUNC_URXD0 (MTK_PIN_NO(79) | 1) -#define MT2701_PIN_79_URXD0__FUNC_UTXD0 (MTK_PIN_NO(79) | 2) -#define MT2701_PIN_79_URXD0__FUNC_ (MTK_PIN_NO(79) | 5) - -#define MT2701_PIN_80_UTXD0__FUNC_GPIO80 (MTK_PIN_NO(80) | 0) -#define MT2701_PIN_80_UTXD0__FUNC_UTXD0 (MTK_PIN_NO(80) | 1) -#define MT2701_PIN_80_UTXD0__FUNC_URXD0 (MTK_PIN_NO(80) | 2) - -#define MT2701_PIN_81_URXD1__FUNC_GPIO81 (MTK_PIN_NO(81) | 0) -#define MT2701_PIN_81_URXD1__FUNC_URXD1 (MTK_PIN_NO(81) | 1) -#define MT2701_PIN_81_URXD1__FUNC_UTXD1 (MTK_PIN_NO(81) | 2) - -#define MT2701_PIN_82_UTXD1__FUNC_GPIO82 (MTK_PIN_NO(82) | 0) -#define MT2701_PIN_82_UTXD1__FUNC_UTXD1 (MTK_PIN_NO(82) | 1) -#define MT2701_PIN_82_UTXD1__FUNC_URXD1 (MTK_PIN_NO(82) | 2) - -#define MT2701_PIN_83_LCM_RST__FUNC_GPIO83 (MTK_PIN_NO(83) | 0) -#define MT2701_PIN_83_LCM_RST__FUNC_LCM_RST (MTK_PIN_NO(83) | 1) -#define MT2701_PIN_83_LCM_RST__FUNC_VDAC_CK_XI (MTK_PIN_NO(83) | 2) -#define MT2701_PIN_83_LCM_RST__FUNC_DBG_MON_B_1 (MTK_PIN_NO(83) | 7) - -#define MT2701_PIN_84_DSI_TE__FUNC_GPIO84 (MTK_PIN_NO(84) | 0) -#define MT2701_PIN_84_DSI_TE__FUNC_DSI_TE (MTK_PIN_NO(84) | 1) -#define MT2701_PIN_84_DSI_TE__FUNC_DBG_MON_B_0 (MTK_PIN_NO(84) | 7) - -#define MT2701_PIN_91_TDN3__FUNC_GPI91 (MTK_PIN_NO(91) | 0) -#define MT2701_PIN_91_TDN3__FUNC_TDN3 (MTK_PIN_NO(91) | 1) - -#define MT2701_PIN_92_TDP3__FUNC_GPI92 (MTK_PIN_NO(92) | 0) -#define MT2701_PIN_92_TDP3__FUNC_TDP3 (MTK_PIN_NO(92) | 1) - -#define MT2701_PIN_93_TDN2__FUNC_GPI93 (MTK_PIN_NO(93) | 0) -#define MT2701_PIN_93_TDN2__FUNC_TDN2 (MTK_PIN_NO(93) | 1) - -#define MT2701_PIN_94_TDP2__FUNC_GPI94 (MTK_PIN_NO(94) | 0) -#define MT2701_PIN_94_TDP2__FUNC_TDP2 (MTK_PIN_NO(94) | 1) - -#define MT2701_PIN_95_TCN__FUNC_GPI95 (MTK_PIN_NO(95) | 0) -#define MT2701_PIN_95_TCN__FUNC_TCN (MTK_PIN_NO(95) | 1) - -#define MT2701_PIN_96_TCP__FUNC_GPI96 (MTK_PIN_NO(96) | 0) -#define MT2701_PIN_96_TCP__FUNC_TCP (MTK_PIN_NO(96) | 1) - -#define MT2701_PIN_97_TDN1__FUNC_GPI97 (MTK_PIN_NO(97) | 0) -#define MT2701_PIN_97_TDN1__FUNC_TDN1 (MTK_PIN_NO(97) | 1) - -#define MT2701_PIN_98_TDP1__FUNC_GPI98 (MTK_PIN_NO(98) | 0) -#define MT2701_PIN_98_TDP1__FUNC_TDP1 (MTK_PIN_NO(98) | 1) - -#define MT2701_PIN_99_TDN0__FUNC_GPI99 (MTK_PIN_NO(99) | 0) -#define MT2701_PIN_99_TDN0__FUNC_TDN0 (MTK_PIN_NO(99) | 1) - -#define MT2701_PIN_100_TDP0__FUNC_GPI100 (MTK_PIN_NO(100) | 0) -#define MT2701_PIN_100_TDP0__FUNC_TDP0 (MTK_PIN_NO(100) | 1) - -#define MT2701_PIN_101_SPI2_CSN__FUNC_GPIO101 (MTK_PIN_NO(101) | 0) -#define MT2701_PIN_101_SPI2_CSN__FUNC_SPI2_CS (MTK_PIN_NO(101) | 1) -#define MT2701_PIN_101_SPI2_CSN__FUNC_SCL3 (MTK_PIN_NO(101) | 3) -#define MT2701_PIN_101_SPI2_CSN__FUNC_KROW0 (MTK_PIN_NO(101) | 4) - -#define MT2701_PIN_102_SPI2_MI__FUNC_GPIO102 (MTK_PIN_NO(102) | 0) -#define MT2701_PIN_102_SPI2_MI__FUNC_SPI2_MI (MTK_PIN_NO(102) | 1) -#define MT2701_PIN_102_SPI2_MI__FUNC_SPI2_MO (MTK_PIN_NO(102) | 2) -#define MT2701_PIN_102_SPI2_MI__FUNC_SDA3 (MTK_PIN_NO(102) | 3) -#define MT2701_PIN_102_SPI2_MI__FUNC_KROW1 (MTK_PIN_NO(102) | 4) - -#define MT2701_PIN_103_SPI2_MO__FUNC_GPIO103 (MTK_PIN_NO(103) | 0) -#define MT2701_PIN_103_SPI2_MO__FUNC_SPI2_MO (MTK_PIN_NO(103) | 1) -#define MT2701_PIN_103_SPI2_MO__FUNC_SPI2_MI (MTK_PIN_NO(103) | 2) -#define MT2701_PIN_103_SPI2_MO__FUNC_SCL3 (MTK_PIN_NO(103) | 3) -#define MT2701_PIN_103_SPI2_MO__FUNC_KROW2 (MTK_PIN_NO(103) | 4) - -#define MT2701_PIN_104_SPI2_CLK__FUNC_GPIO104 (MTK_PIN_NO(104) | 0) -#define MT2701_PIN_104_SPI2_CLK__FUNC_SPI2_CK (MTK_PIN_NO(104) | 1) -#define MT2701_PIN_104_SPI2_CLK__FUNC_SDA3 (MTK_PIN_NO(104) | 3) -#define MT2701_PIN_104_SPI2_CLK__FUNC_KROW3 (MTK_PIN_NO(104) | 4) - -#define MT2701_PIN_105_MSDC1_CMD__FUNC_GPIO105 (MTK_PIN_NO(105) | 0) -#define MT2701_PIN_105_MSDC1_CMD__FUNC_MSDC1_CMD (MTK_PIN_NO(105) | 1) -#define MT2701_PIN_105_MSDC1_CMD__FUNC_ANT_SEL0 (MTK_PIN_NO(105) | 2) -#define MT2701_PIN_105_MSDC1_CMD__FUNC_SDA1 (MTK_PIN_NO(105) | 3) -#define MT2701_PIN_105_MSDC1_CMD__FUNC_I2SOUT_BCK (MTK_PIN_NO(105) | 6) -#define MT2701_PIN_105_MSDC1_CMD__FUNC_DBG_MON_B_27 (MTK_PIN_NO(105) | 7) - -#define MT2701_PIN_106_MSDC1_CLK__FUNC_GPIO106 (MTK_PIN_NO(106) | 0) -#define MT2701_PIN_106_MSDC1_CLK__FUNC_MSDC1_CLK (MTK_PIN_NO(106) | 1) -#define MT2701_PIN_106_MSDC1_CLK__FUNC_ANT_SEL1 (MTK_PIN_NO(106) | 2) -#define MT2701_PIN_106_MSDC1_CLK__FUNC_SCL1 (MTK_PIN_NO(106) | 3) -#define MT2701_PIN_106_MSDC1_CLK__FUNC_I2SOUT_LRCK (MTK_PIN_NO(106) | 6) -#define MT2701_PIN_106_MSDC1_CLK__FUNC_DBG_MON_B_28 (MTK_PIN_NO(106) | 7) - -#define MT2701_PIN_107_MSDC1_DAT0__FUNC_GPIO107 (MTK_PIN_NO(107) | 0) -#define MT2701_PIN_107_MSDC1_DAT0__FUNC_MSDC1_DAT0 (MTK_PIN_NO(107) | 1) -#define MT2701_PIN_107_MSDC1_DAT0__FUNC_ANT_SEL2 (MTK_PIN_NO(107) | 2) -#define MT2701_PIN_107_MSDC1_DAT0__FUNC_UTXD0 (MTK_PIN_NO(107) | 5) -#define MT2701_PIN_107_MSDC1_DAT0__FUNC_I2SOUT_DATA_OUT (MTK_PIN_NO(107) | 6) -#define MT2701_PIN_107_MSDC1_DAT0__FUNC_DBG_MON_B_26 (MTK_PIN_NO(107) | 7) - -#define MT2701_PIN_108_MSDC1_DAT1__FUNC_GPIO108 (MTK_PIN_NO(108) | 0) -#define MT2701_PIN_108_MSDC1_DAT1__FUNC_MSDC1_DAT1 (MTK_PIN_NO(108) | 1) -#define MT2701_PIN_108_MSDC1_DAT1__FUNC_ANT_SEL3 (MTK_PIN_NO(108) | 2) -#define MT2701_PIN_108_MSDC1_DAT1__FUNC_PWM0 (MTK_PIN_NO(108) | 3) -#define MT2701_PIN_108_MSDC1_DAT1__FUNC_URXD0 (MTK_PIN_NO(108) | 5) -#define MT2701_PIN_108_MSDC1_DAT1__FUNC_PWM1 (MTK_PIN_NO(108) | 6) -#define MT2701_PIN_108_MSDC1_DAT1__FUNC_DBG_MON_B_25 (MTK_PIN_NO(108) | 7) - -#define MT2701_PIN_109_MSDC1_DAT2__FUNC_GPIO109 (MTK_PIN_NO(109) | 0) -#define MT2701_PIN_109_MSDC1_DAT2__FUNC_MSDC1_DAT2 (MTK_PIN_NO(109) | 1) -#define MT2701_PIN_109_MSDC1_DAT2__FUNC_ANT_SEL4 (MTK_PIN_NO(109) | 2) -#define MT2701_PIN_109_MSDC1_DAT2__FUNC_SDA2 (MTK_PIN_NO(109) | 3) -#define MT2701_PIN_109_MSDC1_DAT2__FUNC_UTXD1 (MTK_PIN_NO(109) | 5) -#define MT2701_PIN_109_MSDC1_DAT2__FUNC_PWM2 (MTK_PIN_NO(109) | 6) -#define MT2701_PIN_109_MSDC1_DAT2__FUNC_DBG_MON_B_24 (MTK_PIN_NO(109) | 7) - -#define MT2701_PIN_110_MSDC1_DAT3__FUNC_GPIO110 (MTK_PIN_NO(110) | 0) -#define MT2701_PIN_110_MSDC1_DAT3__FUNC_MSDC1_DAT3 (MTK_PIN_NO(110) | 1) -#define MT2701_PIN_110_MSDC1_DAT3__FUNC_ANT_SEL5 (MTK_PIN_NO(110) | 2) -#define MT2701_PIN_110_MSDC1_DAT3__FUNC_SCL2 (MTK_PIN_NO(110) | 3) -#define MT2701_PIN_110_MSDC1_DAT3__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(110) | 4) -#define MT2701_PIN_110_MSDC1_DAT3__FUNC_URXD1 (MTK_PIN_NO(110) | 5) -#define MT2701_PIN_110_MSDC1_DAT3__FUNC_PWM3 (MTK_PIN_NO(110) | 6) -#define MT2701_PIN_110_MSDC1_DAT3__FUNC_DBG_MON_B_23 (MTK_PIN_NO(110) | 7) - -#define MT2701_PIN_111_MSDC0_DAT7__FUNC_GPIO111 (MTK_PIN_NO(111) | 0) -#define MT2701_PIN_111_MSDC0_DAT7__FUNC_MSDC0_DAT7 (MTK_PIN_NO(111) | 1) -#define MT2701_PIN_111_MSDC0_DAT7__FUNC_NLD7 (MTK_PIN_NO(111) | 4) - -#define MT2701_PIN_112_MSDC0_DAT6__FUNC_GPIO112 (MTK_PIN_NO(112) | 0) -#define MT2701_PIN_112_MSDC0_DAT6__FUNC_MSDC0_DAT6 (MTK_PIN_NO(112) | 1) -#define MT2701_PIN_112_MSDC0_DAT6__FUNC_NLD6 (MTK_PIN_NO(112) | 4) - -#define MT2701_PIN_113_MSDC0_DAT5__FUNC_GPIO113 (MTK_PIN_NO(113) | 0) -#define MT2701_PIN_113_MSDC0_DAT5__FUNC_MSDC0_DAT5 (MTK_PIN_NO(113) | 1) -#define MT2701_PIN_113_MSDC0_DAT5__FUNC_NLD5 (MTK_PIN_NO(113) | 4) - -#define MT2701_PIN_114_MSDC0_DAT4__FUNC_GPIO114 (MTK_PIN_NO(114) | 0) -#define MT2701_PIN_114_MSDC0_DAT4__FUNC_MSDC0_DAT4 (MTK_PIN_NO(114) | 1) -#define MT2701_PIN_114_MSDC0_DAT4__FUNC_NLD4 (MTK_PIN_NO(114) | 4) - -#define MT2701_PIN_115_MSDC0_RSTB__FUNC_GPIO115 (MTK_PIN_NO(115) | 0) -#define MT2701_PIN_115_MSDC0_RSTB__FUNC_MSDC0_RSTB (MTK_PIN_NO(115) | 1) -#define MT2701_PIN_115_MSDC0_RSTB__FUNC_NLD8 (MTK_PIN_NO(115) | 4) - -#define MT2701_PIN_116_MSDC0_CMD__FUNC_GPIO116 (MTK_PIN_NO(116) | 0) -#define MT2701_PIN_116_MSDC0_CMD__FUNC_MSDC0_CMD (MTK_PIN_NO(116) | 1) -#define MT2701_PIN_116_MSDC0_CMD__FUNC_NALE (MTK_PIN_NO(116) | 4) - -#define MT2701_PIN_117_MSDC0_CLK__FUNC_GPIO117 (MTK_PIN_NO(117) | 0) -#define MT2701_PIN_117_MSDC0_CLK__FUNC_MSDC0_CLK (MTK_PIN_NO(117) | 1) -#define MT2701_PIN_117_MSDC0_CLK__FUNC_NWEB (MTK_PIN_NO(117) | 4) - -#define MT2701_PIN_118_MSDC0_DAT3__FUNC_GPIO118 (MTK_PIN_NO(118) | 0) -#define MT2701_PIN_118_MSDC0_DAT3__FUNC_MSDC0_DAT3 (MTK_PIN_NO(118) | 1) -#define MT2701_PIN_118_MSDC0_DAT3__FUNC_NLD3 (MTK_PIN_NO(118) | 4) - -#define MT2701_PIN_119_MSDC0_DAT2__FUNC_GPIO119 (MTK_PIN_NO(119) | 0) -#define MT2701_PIN_119_MSDC0_DAT2__FUNC_MSDC0_DAT2 (MTK_PIN_NO(119) | 1) -#define MT2701_PIN_119_MSDC0_DAT2__FUNC_NLD2 (MTK_PIN_NO(119) | 4) - -#define MT2701_PIN_120_MSDC0_DAT1__FUNC_GPIO120 (MTK_PIN_NO(120) | 0) -#define MT2701_PIN_120_MSDC0_DAT1__FUNC_MSDC0_DAT1 (MTK_PIN_NO(120) | 1) -#define MT2701_PIN_120_MSDC0_DAT1__FUNC_NLD1 (MTK_PIN_NO(120) | 4) - -#define MT2701_PIN_121_MSDC0_DAT0__FUNC_GPIO121 (MTK_PIN_NO(121) | 0) -#define MT2701_PIN_121_MSDC0_DAT0__FUNC_MSDC0_DAT0 (MTK_PIN_NO(121) | 1) -#define MT2701_PIN_121_MSDC0_DAT0__FUNC_NLD0 (MTK_PIN_NO(121) | 4) -#define MT2701_PIN_121_MSDC0_DAT0__FUNC_WATCHDOG (MTK_PIN_NO(121) | 5) - -#define MT2701_PIN_122_CEC__FUNC_GPIO122 (MTK_PIN_NO(122) | 0) -#define MT2701_PIN_122_CEC__FUNC_CEC (MTK_PIN_NO(122) | 1) -#define MT2701_PIN_122_CEC__FUNC_SDA2 (MTK_PIN_NO(122) | 4) -#define MT2701_PIN_122_CEC__FUNC_URXD0 (MTK_PIN_NO(122) | 5) - -#define MT2701_PIN_123_HTPLG__FUNC_GPIO123 (MTK_PIN_NO(123) | 0) -#define MT2701_PIN_123_HTPLG__FUNC_HTPLG (MTK_PIN_NO(123) | 1) -#define MT2701_PIN_123_HTPLG__FUNC_SCL2 (MTK_PIN_NO(123) | 4) -#define MT2701_PIN_123_HTPLG__FUNC_UTXD0 (MTK_PIN_NO(123) | 5) - -#define MT2701_PIN_124_HDMISCK__FUNC_GPIO124 (MTK_PIN_NO(124) | 0) -#define MT2701_PIN_124_HDMISCK__FUNC_HDMISCK (MTK_PIN_NO(124) | 1) -#define MT2701_PIN_124_HDMISCK__FUNC_SDA1 (MTK_PIN_NO(124) | 4) -#define MT2701_PIN_124_HDMISCK__FUNC_PWM3 (MTK_PIN_NO(124) | 5) - -#define MT2701_PIN_125_HDMISD__FUNC_GPIO125 (MTK_PIN_NO(125) | 0) -#define MT2701_PIN_125_HDMISD__FUNC_HDMISD (MTK_PIN_NO(125) | 1) -#define MT2701_PIN_125_HDMISD__FUNC_SCL1 (MTK_PIN_NO(125) | 4) -#define MT2701_PIN_125_HDMISD__FUNC_PWM4 (MTK_PIN_NO(125) | 5) - -#define MT2701_PIN_126_I2S0_MCLK__FUNC_GPIO126 (MTK_PIN_NO(126) | 0) -#define MT2701_PIN_126_I2S0_MCLK__FUNC_I2S0_MCLK (MTK_PIN_NO(126) | 1) -#define MT2701_PIN_126_I2S0_MCLK__FUNC_WCN_I2S_MCLK (MTK_PIN_NO(126) | 6) -#define MT2701_PIN_126_I2S0_MCLK__FUNC_DBG_MON_B_6 (MTK_PIN_NO(126) | 7) - -#define MT2701_PIN_199_SPI1_CLK__FUNC_GPIO199 (MTK_PIN_NO(199) | 0) -#define MT2701_PIN_199_SPI1_CLK__FUNC_SPI1_CK (MTK_PIN_NO(199) | 1) -#define MT2701_PIN_199_SPI1_CLK__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(199) | 3) -#define MT2701_PIN_199_SPI1_CLK__FUNC_KCOL3 (MTK_PIN_NO(199) | 4) -#define MT2701_PIN_199_SPI1_CLK__FUNC_DBG_MON_B_15 (MTK_PIN_NO(199) | 7) - -#define MT2701_PIN_200_SPDIF_OUT__FUNC_GPIO200 (MTK_PIN_NO(200) | 0) -#define MT2701_PIN_200_SPDIF_OUT__FUNC_SPDIF_OUT (MTK_PIN_NO(200) | 1) -#define MT2701_PIN_200_SPDIF_OUT__FUNC_G1_TXD3 (MTK_PIN_NO(200) | 5) -#define MT2701_PIN_200_SPDIF_OUT__FUNC_URXD2 (MTK_PIN_NO(200) | 6) -#define MT2701_PIN_200_SPDIF_OUT__FUNC_DBG_MON_B_16 (MTK_PIN_NO(200) | 7) - -#define MT2701_PIN_201_SPDIF_IN0__FUNC_GPIO201 (MTK_PIN_NO(201) | 0) -#define MT2701_PIN_201_SPDIF_IN0__FUNC_SPDIF_IN0 (MTK_PIN_NO(201) | 1) -#define MT2701_PIN_201_SPDIF_IN0__FUNC_G1_TXEN (MTK_PIN_NO(201) | 5) -#define MT2701_PIN_201_SPDIF_IN0__FUNC_UTXD2 (MTK_PIN_NO(201) | 6) -#define MT2701_PIN_201_SPDIF_IN0__FUNC_DBG_MON_B_17 (MTK_PIN_NO(201) | 7) - -#define MT2701_PIN_202_SPDIF_IN1__FUNC_GPIO202 (MTK_PIN_NO(202) | 0) -#define MT2701_PIN_202_SPDIF_IN1__FUNC_SPDIF_IN1 (MTK_PIN_NO(202) | 1) - -#define MT2701_PIN_203_PWM0__FUNC_GPIO203 (MTK_PIN_NO(203) | 0) -#define MT2701_PIN_203_PWM0__FUNC_PWM0 (MTK_PIN_NO(203) | 1) -#define MT2701_PIN_203_PWM0__FUNC_DISP_PWM (MTK_PIN_NO(203) | 2) -#define MT2701_PIN_203_PWM0__FUNC_G1_TXD2 (MTK_PIN_NO(203) | 5) -#define MT2701_PIN_203_PWM0__FUNC_DBG_MON_B_18 (MTK_PIN_NO(203) | 7) -#define MT2701_PIN_203_PWM0__FUNC_I2S2_DATA (MTK_PIN_NO(203) | 9) - -#define MT2701_PIN_204_PWM1__FUNC_GPIO204 (MTK_PIN_NO(204) | 0) -#define MT2701_PIN_204_PWM1__FUNC_PWM1 (MTK_PIN_NO(204) | 1) -#define MT2701_PIN_204_PWM1__FUNC_CLKM3 (MTK_PIN_NO(204) | 2) -#define MT2701_PIN_204_PWM1__FUNC_G1_TXD1 (MTK_PIN_NO(204) | 5) -#define MT2701_PIN_204_PWM1__FUNC_DBG_MON_B_19 (MTK_PIN_NO(204) | 7) -#define MT2701_PIN_204_PWM1__FUNC_I2S3_DATA (MTK_PIN_NO(204) | 9) - -#define MT2701_PIN_205_PWM2__FUNC_GPIO205 (MTK_PIN_NO(205) | 0) -#define MT2701_PIN_205_PWM2__FUNC_PWM2 (MTK_PIN_NO(205) | 1) -#define MT2701_PIN_205_PWM2__FUNC_CLKM2 (MTK_PIN_NO(205) | 2) -#define MT2701_PIN_205_PWM2__FUNC_G1_TXD0 (MTK_PIN_NO(205) | 5) -#define MT2701_PIN_205_PWM2__FUNC_DBG_MON_B_20 (MTK_PIN_NO(205) | 7) - -#define MT2701_PIN_206_PWM3__FUNC_GPIO206 (MTK_PIN_NO(206) | 0) -#define MT2701_PIN_206_PWM3__FUNC_PWM3 (MTK_PIN_NO(206) | 1) -#define MT2701_PIN_206_PWM3__FUNC_CLKM1 (MTK_PIN_NO(206) | 2) -#define MT2701_PIN_206_PWM3__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(206) | 3) -#define MT2701_PIN_206_PWM3__FUNC_G1_TXC (MTK_PIN_NO(206) | 5) -#define MT2701_PIN_206_PWM3__FUNC_DBG_MON_B_21 (MTK_PIN_NO(206) | 7) - -#define MT2701_PIN_207_PWM4__FUNC_GPIO207 (MTK_PIN_NO(207) | 0) -#define MT2701_PIN_207_PWM4__FUNC_PWM4 (MTK_PIN_NO(207) | 1) -#define MT2701_PIN_207_PWM4__FUNC_CLKM0 (MTK_PIN_NO(207) | 2) -#define MT2701_PIN_207_PWM4__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(207) | 3) -#define MT2701_PIN_207_PWM4__FUNC_G1_RXC (MTK_PIN_NO(207) | 5) -#define MT2701_PIN_207_PWM4__FUNC_DBG_MON_B_22 (MTK_PIN_NO(207) | 7) - -#define MT2701_PIN_208_AUD_EXT_CK1__FUNC_GPIO208 (MTK_PIN_NO(208) | 0) -#define MT2701_PIN_208_AUD_EXT_CK1__FUNC_AUD_EXT_CK1 (MTK_PIN_NO(208) | 1) -#define MT2701_PIN_208_AUD_EXT_CK1__FUNC_PWM0 (MTK_PIN_NO(208) | 2) -#define MT2701_PIN_208_AUD_EXT_CK1__FUNC_ANT_SEL5 (MTK_PIN_NO(208) | 4) -#define MT2701_PIN_208_AUD_EXT_CK1__FUNC_DISP_PWM (MTK_PIN_NO(208) | 5) -#define MT2701_PIN_208_AUD_EXT_CK1__FUNC_DBG_MON_A_31 (MTK_PIN_NO(208) | 7) -#define MT2701_PIN_208_AUD_EXT_CK1__FUNC_PCIE0_PERST_N (MTK_PIN_NO(208) | 11) - -#define MT2701_PIN_209_AUD_EXT_CK2__FUNC_GPIO209 (MTK_PIN_NO(209) | 0) -#define MT2701_PIN_209_AUD_EXT_CK2__FUNC_AUD_EXT_CK2 (MTK_PIN_NO(209) | 1) -#define MT2701_PIN_209_AUD_EXT_CK2__FUNC_MSDC1_WP (MTK_PIN_NO(209) | 2) -#define MT2701_PIN_209_AUD_EXT_CK2__FUNC_PWM1 (MTK_PIN_NO(209) | 5) -#define MT2701_PIN_209_AUD_EXT_CK2__FUNC_DBG_MON_A_32 (MTK_PIN_NO(209) | 7) -#define MT2701_PIN_209_AUD_EXT_CK2__FUNC_PCIE1_PERST_N (MTK_PIN_NO(209) | 11) - -#define MT2701_PIN_236_EXT_SDIO3__FUNC_GPIO236 (MTK_PIN_NO(236) | 0) -#define MT2701_PIN_236_EXT_SDIO3__FUNC_EXT_SDIO3 (MTK_PIN_NO(236) | 1) -#define MT2701_PIN_236_EXT_SDIO3__FUNC_IDDIG (MTK_PIN_NO(236) | 2) -#define MT2701_PIN_236_EXT_SDIO3__FUNC_DBG_MON_A_1 (MTK_PIN_NO(236) | 7) - -#define MT2701_PIN_237_EXT_SDIO2__FUNC_GPIO237 (MTK_PIN_NO(237) | 0) -#define MT2701_PIN_237_EXT_SDIO2__FUNC_EXT_SDIO2 (MTK_PIN_NO(237) | 1) -#define MT2701_PIN_237_EXT_SDIO2__FUNC_DRV_VBUS (MTK_PIN_NO(237) | 2) - -#define MT2701_PIN_238_EXT_SDIO1__FUNC_GPIO238 (MTK_PIN_NO(238) | 0) -#define MT2701_PIN_238_EXT_SDIO1__FUNC_EXT_SDIO1 (MTK_PIN_NO(238) | 1) -#define MT2701_PIN_238_EXT_SDIO1__FUNC_IDDIG_P1 (MTK_PIN_NO(238) | 2) - -#define MT2701_PIN_239_EXT_SDIO0__FUNC_GPIO239 (MTK_PIN_NO(239) | 0) -#define MT2701_PIN_239_EXT_SDIO0__FUNC_EXT_SDIO0 (MTK_PIN_NO(239) | 1) -#define MT2701_PIN_239_EXT_SDIO0__FUNC_DRV_VBUS_P1 (MTK_PIN_NO(239) | 2) - -#define MT2701_PIN_240_EXT_XCS__FUNC_GPIO240 (MTK_PIN_NO(240) | 0) -#define MT2701_PIN_240_EXT_XCS__FUNC_EXT_XCS (MTK_PIN_NO(240) | 1) - -#define MT2701_PIN_241_EXT_SCK__FUNC_GPIO241 (MTK_PIN_NO(241) | 0) -#define MT2701_PIN_241_EXT_SCK__FUNC_EXT_SCK (MTK_PIN_NO(241) | 1) - -#define MT2701_PIN_242_URTS2__FUNC_GPIO242 (MTK_PIN_NO(242) | 0) -#define MT2701_PIN_242_URTS2__FUNC_URTS2 (MTK_PIN_NO(242) | 1) -#define MT2701_PIN_242_URTS2__FUNC_UTXD3 (MTK_PIN_NO(242) | 2) -#define MT2701_PIN_242_URTS2__FUNC_URXD3 (MTK_PIN_NO(242) | 3) -#define MT2701_PIN_242_URTS2__FUNC_SCL1 (MTK_PIN_NO(242) | 4) -#define MT2701_PIN_242_URTS2__FUNC_DBG_MON_B_32 (MTK_PIN_NO(242) | 7) - -#define MT2701_PIN_243_UCTS2__FUNC_GPIO243 (MTK_PIN_NO(243) | 0) -#define MT2701_PIN_243_UCTS2__FUNC_UCTS2 (MTK_PIN_NO(243) | 1) -#define MT2701_PIN_243_UCTS2__FUNC_URXD3 (MTK_PIN_NO(243) | 2) -#define MT2701_PIN_243_UCTS2__FUNC_UTXD3 (MTK_PIN_NO(243) | 3) -#define MT2701_PIN_243_UCTS2__FUNC_SDA1 (MTK_PIN_NO(243) | 4) -#define MT2701_PIN_243_UCTS2__FUNC_DBG_MON_A_6 (MTK_PIN_NO(243) | 7) - -#define MT2701_PIN_244_HDMI_SDA_RX__FUNC_GPIO244 (MTK_PIN_NO(244) | 0) -#define MT2701_PIN_244_HDMI_SDA_RX__FUNC_HDMI_SDA_RX (MTK_PIN_NO(244) | 1) - -#define MT2701_PIN_245_HDMI_SCL_RX__FUNC_GPIO245 (MTK_PIN_NO(245) | 0) -#define MT2701_PIN_245_HDMI_SCL_RX__FUNC_HDMI_SCL_RX (MTK_PIN_NO(245) | 1) - -#define MT2701_PIN_246_MHL_SENCE__FUNC_GPIO246 (MTK_PIN_NO(246) | 0) - -#define MT2701_PIN_247_HDMI_HPD_CBUS_RX__FUNC_GPIO247 (MTK_PIN_NO(247) | 0) -#define MT2701_PIN_247_HDMI_HPD_CBUS_RX__FUNC_HDMI_HPD_RX (MTK_PIN_NO(247) | 1) - -#define MT2701_PIN_248_HDMI_TESTOUTP_RX__FUNC_GPIO248 (MTK_PIN_NO(248) | 0) -#define MT2701_PIN_248_HDMI_TESTOUTP_RX__FUNC_HDMI_TESTOUTP_RX (MTK_PIN_NO(248) | 1) - -#define MT2701_PIN_249_MSDC0E_RSTB__FUNC_MSDC0E_RSTB (MTK_PIN_NO(249) | 9) - -#define MT2701_PIN_250_MSDC0E_DAT7__FUNC_MSDC3_DAT7 (MTK_PIN_NO(250) | 9) -#define MT2701_PIN_250_MSDC0E_DAT7__FUNC_PCIE0_CLKREQ_N (MTK_PIN_NO(250) | 14) - -#define MT2701_PIN_251_MSDC0E_DAT6__FUNC_MSDC3_DAT6 (MTK_PIN_NO(251) | 9) -#define MT2701_PIN_251_MSDC0E_DAT6__FUNC_PCIE0_WAKE_N (MTK_PIN_NO(251) | 14) - -#define MT2701_PIN_252_MSDC0E_DAT5__FUNC_MSDC3_DAT5 (MTK_PIN_NO(252) | 9) -#define MT2701_PIN_252_MSDC0E_DAT5__FUNC_PCIE1_CLKREQ_N (MTK_PIN_NO(252) | 14) - -#define MT2701_PIN_253_MSDC0E_DAT4__FUNC_MSDC3_DAT4 (MTK_PIN_NO(253) | 9) -#define MT2701_PIN_253_MSDC0E_DAT4__FUNC_PCIE1_WAKE_N (MTK_PIN_NO(253) | 14) - -#define MT2701_PIN_254_MSDC0E_DAT3__FUNC_MSDC3_DAT3 (MTK_PIN_NO(254) | 9) -#define MT2701_PIN_254_MSDC0E_DAT3__FUNC_PCIE2_CLKREQ_N (MTK_PIN_NO(254) | 14) - -#define MT2701_PIN_255_MSDC0E_DAT2__FUNC_MSDC3_DAT2 (MTK_PIN_NO(255) | 9) -#define MT2701_PIN_255_MSDC0E_DAT2__FUNC_PCIE2_WAKE_N (MTK_PIN_NO(255) | 14) - -#define MT2701_PIN_256_MSDC0E_DAT1__FUNC_MSDC3_DAT1 (MTK_PIN_NO(256) | 9) - -#define MT2701_PIN_257_MSDC0E_DAT0__FUNC_MSDC3_DAT0 (MTK_PIN_NO(257) | 9) - -#define MT2701_PIN_258_MSDC0E_CMD__FUNC_MSDC3_CMD (MTK_PIN_NO(258) | 9) - -#define MT2701_PIN_259_MSDC0E_CLK__FUNC_MSDC3_CLK (MTK_PIN_NO(259) | 9) - -#define MT2701_PIN_260_MSDC0E_DSL__FUNC_MSDC3_DSL (MTK_PIN_NO(260) | 9) - -#define MT2701_PIN_261_MSDC1_INS__FUNC_GPIO261 (MTK_PIN_NO(261) | 0) -#define MT2701_PIN_261_MSDC1_INS__FUNC_MSDC1_INS (MTK_PIN_NO(261) | 1) -#define MT2701_PIN_261_MSDC1_INS__FUNC_DBG_MON_B_29 (MTK_PIN_NO(261) | 7) - -#define MT2701_PIN_262_G2_TXEN__FUNC_GPIO262 (MTK_PIN_NO(262) | 0) -#define MT2701_PIN_262_G2_TXEN__FUNC_G2_TXEN (MTK_PIN_NO(262) | 1) - -#define MT2701_PIN_263_G2_TXD3__FUNC_GPIO263 (MTK_PIN_NO(263) | 0) -#define MT2701_PIN_263_G2_TXD3__FUNC_G2_TXD3 (MTK_PIN_NO(263) | 1) -#define MT2701_PIN_263_G2_TXD3__FUNC_ANT_SEL5 (MTK_PIN_NO(263) | 6) - -#define MT2701_PIN_264_G2_TXD2__FUNC_GPIO264 (MTK_PIN_NO(264) | 0) -#define MT2701_PIN_264_G2_TXD2__FUNC_G2_TXD2 (MTK_PIN_NO(264) | 1) -#define MT2701_PIN_264_G2_TXD2__FUNC_ANT_SEL4 (MTK_PIN_NO(264) | 6) - -#define MT2701_PIN_265_G2_TXD1__FUNC_GPIO265 (MTK_PIN_NO(265) | 0) -#define MT2701_PIN_265_G2_TXD1__FUNC_G2_TXD1 (MTK_PIN_NO(265) | 1) -#define MT2701_PIN_265_G2_TXD1__FUNC_ANT_SEL3 (MTK_PIN_NO(265) | 6) - -#define MT2701_PIN_266_G2_TXD0__FUNC_GPIO266 (MTK_PIN_NO(266) | 0) -#define MT2701_PIN_266_G2_TXD0__FUNC_G2_TXD0 (MTK_PIN_NO(266) | 1) -#define MT2701_PIN_266_G2_TXD0__FUNC_ANT_SEL2 (MTK_PIN_NO(266) | 6) - -#define MT2701_PIN_267_G2_TXC__FUNC_GPIO267 (MTK_PIN_NO(267) | 0) -#define MT2701_PIN_267_G2_TXC__FUNC_G2_TXC (MTK_PIN_NO(267) | 1) - -#define MT2701_PIN_268_G2_RXC__FUNC_GPIO268 (MTK_PIN_NO(268) | 0) -#define MT2701_PIN_268_G2_RXC__FUNC_G2_RXC (MTK_PIN_NO(268) | 1) - -#define MT2701_PIN_269_G2_RXD0__FUNC_GPIO269 (MTK_PIN_NO(269) | 0) -#define MT2701_PIN_269_G2_RXD0__FUNC_G2_RXD0 (MTK_PIN_NO(269) | 1) - -#define MT2701_PIN_270_G2_RXD1__FUNC_GPIO270 (MTK_PIN_NO(270) | 0) -#define MT2701_PIN_270_G2_RXD1__FUNC_G2_RXD1 (MTK_PIN_NO(270) | 1) - -#define MT2701_PIN_271_G2_RXD2__FUNC_GPIO271 (MTK_PIN_NO(271) | 0) -#define MT2701_PIN_271_G2_RXD2__FUNC_G2_RXD2 (MTK_PIN_NO(271) | 1) - -#define MT2701_PIN_272_G2_RXD3__FUNC_GPIO272 (MTK_PIN_NO(272) | 0) -#define MT2701_PIN_272_G2_RXD3__FUNC_G2_RXD3 (MTK_PIN_NO(272) | 1) - -#define MT2701_PIN_274_G2_RXDV__FUNC_GPIO274 (MTK_PIN_NO(274) | 0) -#define MT2701_PIN_274_G2_RXDV__FUNC_G2_RXDV (MTK_PIN_NO(274) | 1) - -#define MT2701_PIN_275_MDC__FUNC_GPIO275 (MTK_PIN_NO(275) | 0) -#define MT2701_PIN_275_MDC__FUNC_MDC (MTK_PIN_NO(275) | 1) -#define MT2701_PIN_275_MDC__FUNC_ANT_SEL0 (MTK_PIN_NO(275) | 6) - -#define MT2701_PIN_276_MDIO__FUNC_GPIO276 (MTK_PIN_NO(276) | 0) -#define MT2701_PIN_276_MDIO__FUNC_MDIO (MTK_PIN_NO(276) | 1) -#define MT2701_PIN_276_MDIO__FUNC_ANT_SEL1 (MTK_PIN_NO(276) | 6) - -#define MT2701_PIN_278_JTAG_RESET__FUNC_GPIO278 (MTK_PIN_NO(278) | 0) -#define MT2701_PIN_278_JTAG_RESET__FUNC_JTAG_RESET (MTK_PIN_NO(278) | 1) - -#endif /* __DTS_MT2701_PINFUNC_H */ diff --git a/sys/gnu/dts/arm/mt2701.dtsi b/sys/gnu/dts/arm/mt2701.dtsi deleted file mode 100644 index 51e1305c647..00000000000 --- a/sys/gnu/dts/arm/mt2701.dtsi +++ /dev/null @@ -1,710 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2015 MediaTek Inc. - * Author: Erin.Lo - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include "mt2701-pinfunc.h" - -/ { - #address-cells = <2>; - #size-cells = <2>; - compatible = "mediatek,mt2701"; - interrupt-parent = <&cirq>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "mediatek,mt81xx-tz-smp"; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x0>; - }; - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x1>; - }; - cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x2>; - }; - cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x3>; - }; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - trustzone-bootinfo@80002000 { - compatible = "mediatek,trustzone-bootinfo"; - reg = <0 0x80002000 0 0x1000>; - }; - }; - - system_clk: dummy13m { - compatible = "fixed-clock"; - clock-frequency = <13000000>; - #clock-cells = <0>; - }; - - rtc_clk: dummy32k { - compatible = "fixed-clock"; - clock-frequency = <32000>; - #clock-cells = <0>; - }; - - clk26m: oscillator@0 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <26000000>; - clock-output-names = "clk26m"; - }; - - rtc32k: oscillator@1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32000>; - clock-output-names = "rtc32k"; - }; - - thermal-zones { - cpu_thermal: cpu_thermal { - polling-delay-passive = <1000>; /* milliseconds */ - polling-delay = <1000>; /* milliseconds */ - - thermal-sensors = <&thermal 0>; - sustainable-power = <1000>; - - trips { - threshold: trip-point@0 { - temperature = <68000>; - hysteresis = <2000>; - type = "passive"; - }; - - target: trip-point@1 { - temperature = <85000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu_crit: cpu_crit@0 { - temperature = <115000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupt-parent = <&gic>; - interrupts = , - , - , - ; - }; - - topckgen: syscon@10000000 { - compatible = "mediatek,mt2701-topckgen", "syscon"; - reg = <0 0x10000000 0 0x1000>; - #clock-cells = <1>; - }; - - infracfg: syscon@10001000 { - compatible = "mediatek,mt2701-infracfg", "syscon"; - reg = <0 0x10001000 0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - pericfg: syscon@10003000 { - compatible = "mediatek,mt2701-pericfg", "syscon"; - reg = <0 0x10003000 0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - syscfg_pctl_a: syscfg@10005000 { - compatible = "mediatek,mt2701-pctl-a-syscfg", "syscon"; - reg = <0 0x10005000 0 0x1000>; - }; - - scpsys: scpsys@10006000 { - compatible = "mediatek,mt2701-scpsys", "syscon"; - #power-domain-cells = <1>; - reg = <0 0x10006000 0 0x1000>; - infracfg = <&infracfg>; - clocks = <&topckgen CLK_TOP_MM_SEL>, - <&topckgen CLK_TOP_MFG_SEL>, - <&topckgen CLK_TOP_ETHIF_SEL>; - clock-names = "mm", "mfg", "ethif"; - }; - - watchdog: watchdog@10007000 { - compatible = "mediatek,mt2701-wdt", - "mediatek,mt6589-wdt"; - reg = <0 0x10007000 0 0x100>; - }; - - timer: timer@10008000 { - compatible = "mediatek,mt2701-timer", - "mediatek,mt6577-timer"; - reg = <0 0x10008000 0 0x80>; - interrupts = ; - clocks = <&system_clk>, <&rtc_clk>; - clock-names = "system-clk", "rtc-clk"; - }; - - pio: pinctrl@1000b000 { - compatible = "mediatek,mt2701-pinctrl"; - reg = <0 0x1000b000 0 0x1000>; - mediatek,pctl-regmap = <&syscfg_pctl_a>; - pins-are-numbered; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = , - ; - }; - - smi_common: smi@1000c000 { - compatible = "mediatek,mt2701-smi-common"; - reg = <0 0x1000c000 0 0x1000>; - clocks = <&infracfg CLK_INFRA_SMI>, - <&mmsys CLK_MM_SMI_COMMON>, - <&infracfg CLK_INFRA_SMI>; - clock-names = "apb", "smi", "async"; - power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>; - }; - - sysirq: interrupt-controller@10200100 { - compatible = "mediatek,mt2701-sysirq", - "mediatek,mt6577-sysirq"; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - reg = <0 0x10200100 0 0x1c>; - }; - - cirq: interrupt-controller@10204000 { - compatible = "mediatek,mt2701-cirq", - "mediatek,mtk-cirq"; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&sysirq>; - reg = <0 0x10204000 0 0x400>; - mediatek,ext-irq-range = <32 200>; - }; - - iommu: mmsys_iommu@10205000 { - compatible = "mediatek,mt2701-m4u"; - reg = <0 0x10205000 0 0x1000>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_M4U>; - clock-names = "bclk"; - mediatek,larbs = <&larb0 &larb1 &larb2>; - #iommu-cells = <1>; - }; - - apmixedsys: syscon@10209000 { - compatible = "mediatek,mt2701-apmixedsys", "syscon"; - reg = <0 0x10209000 0 0x1000>; - #clock-cells = <1>; - }; - - gic: interrupt-controller@10211000 { - compatible = "arm,cortex-a7-gic"; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - reg = <0 0x10211000 0 0x1000>, - <0 0x10212000 0 0x2000>, - <0 0x10214000 0 0x2000>, - <0 0x10216000 0 0x2000>; - }; - - auxadc: adc@11001000 { - compatible = "mediatek,mt2701-auxadc"; - reg = <0 0x11001000 0 0x1000>; - clocks = <&pericfg CLK_PERI_AUXADC>; - clock-names = "main"; - #io-channel-cells = <1>; - status = "disabled"; - }; - - uart0: serial@11002000 { - compatible = "mediatek,mt2701-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11002000 0 0x400>; - interrupts = ; - clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>; - clock-names = "baud", "bus"; - status = "disabled"; - }; - - uart1: serial@11003000 { - compatible = "mediatek,mt2701-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11003000 0 0x400>; - interrupts = ; - clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>; - clock-names = "baud", "bus"; - status = "disabled"; - }; - - uart2: serial@11004000 { - compatible = "mediatek,mt2701-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11004000 0 0x400>; - interrupts = ; - clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>; - clock-names = "baud", "bus"; - status = "disabled"; - }; - - uart3: serial@11005000 { - compatible = "mediatek,mt2701-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11005000 0 0x400>; - interrupts = ; - clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>; - clock-names = "baud", "bus"; - status = "disabled"; - }; - - i2c0: i2c@11007000 { - compatible = "mediatek,mt2701-i2c", - "mediatek,mt6577-i2c"; - reg = <0 0x11007000 0 0x70>, - <0 0x11000200 0 0x80>; - interrupts = ; - clock-div = <16>; - clocks = <&pericfg CLK_PERI_I2C0>, <&pericfg CLK_PERI_AP_DMA>; - clock-names = "main", "dma"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c1: i2c@11008000 { - compatible = "mediatek,mt2701-i2c", - "mediatek,mt6577-i2c"; - reg = <0 0x11008000 0 0x70>, - <0 0x11000280 0 0x80>; - interrupts = ; - clock-div = <16>; - clocks = <&pericfg CLK_PERI_I2C1>, <&pericfg CLK_PERI_AP_DMA>; - clock-names = "main", "dma"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@11009000 { - compatible = "mediatek,mt2701-i2c", - "mediatek,mt6577-i2c"; - reg = <0 0x11009000 0 0x70>, - <0 0x11000300 0 0x80>; - interrupts = ; - clock-div = <16>; - clocks = <&pericfg CLK_PERI_I2C2>, <&pericfg CLK_PERI_AP_DMA>; - clock-names = "main", "dma"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi0: spi@1100a000 { - compatible = "mediatek,mt2701-spi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0 0x1100a000 0 0x100>; - interrupts = ; - clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, - <&topckgen CLK_TOP_SPI0_SEL>, - <&pericfg CLK_PERI_SPI0>; - clock-names = "parent-clk", "sel-clk", "spi-clk"; - status = "disabled"; - }; - - thermal: thermal@1100b000 { - #thermal-sensor-cells = <0>; - compatible = "mediatek,mt2701-thermal"; - reg = <0 0x1100b000 0 0x1000>; - interrupts = ; - clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>; - clock-names = "therm", "auxadc"; - resets = <&pericfg MT2701_PERI_THERM_SW_RST>; - reset-names = "therm"; - mediatek,auxadc = <&auxadc>; - mediatek,apmixedsys = <&apmixedsys>; - }; - - nandc: nfi@1100d000 { - compatible = "mediatek,mt2701-nfc"; - reg = <0 0x1100d000 0 0x1000>; - interrupts = ; - clocks = <&pericfg CLK_PERI_NFI>, - <&pericfg CLK_PERI_NFI_PAD>; - clock-names = "nfi_clk", "pad_clk"; - status = "disabled"; - ecc-engine = <&bch>; - #address-cells = <1>; - #size-cells = <0>; - }; - - bch: ecc@1100e000 { - compatible = "mediatek,mt2701-ecc"; - reg = <0 0x1100e000 0 0x1000>; - interrupts = ; - clocks = <&pericfg CLK_PERI_NFI_ECC>; - clock-names = "nfiecc_clk"; - status = "disabled"; - }; - - nor_flash: spi@11014000 { - compatible = "mediatek,mt2701-nor", - "mediatek,mt8173-nor"; - reg = <0 0x11014000 0 0xe0>; - clocks = <&pericfg CLK_PERI_FLASH>, - <&topckgen CLK_TOP_FLASH_SEL>; - clock-names = "spi", "sf"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi1: spi@11016000 { - compatible = "mediatek,mt2701-spi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0 0x11016000 0 0x100>; - interrupts = ; - clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, - <&topckgen CLK_TOP_SPI1_SEL>, - <&pericfg CLK_PERI_SPI1>; - clock-names = "parent-clk", "sel-clk", "spi-clk"; - status = "disabled"; - }; - - spi2: spi@11017000 { - compatible = "mediatek,mt2701-spi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0 0x11017000 0 0x1000>; - interrupts = ; - clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, - <&topckgen CLK_TOP_SPI2_SEL>, - <&pericfg CLK_PERI_SPI2>; - clock-names = "parent-clk", "sel-clk", "spi-clk"; - status = "disabled"; - }; - - audsys: clock-controller@11220000 { - compatible = "mediatek,mt2701-audsys", "syscon"; - reg = <0 0x11220000 0 0x2000>; - #clock-cells = <1>; - - afe: audio-controller { - compatible = "mediatek,mt2701-audio"; - interrupts = , - ; - interrupt-names = "afe", "asys"; - power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>; - - clocks = <&infracfg CLK_INFRA_AUDIO>, - <&topckgen CLK_TOP_AUD_MUX1_SEL>, - <&topckgen CLK_TOP_AUD_MUX2_SEL>, - <&topckgen CLK_TOP_AUD_48K_TIMING>, - <&topckgen CLK_TOP_AUD_44K_TIMING>, - <&topckgen CLK_TOP_AUD_K1_SRC_SEL>, - <&topckgen CLK_TOP_AUD_K2_SRC_SEL>, - <&topckgen CLK_TOP_AUD_K3_SRC_SEL>, - <&topckgen CLK_TOP_AUD_K4_SRC_SEL>, - <&topckgen CLK_TOP_AUD_K1_SRC_DIV>, - <&topckgen CLK_TOP_AUD_K2_SRC_DIV>, - <&topckgen CLK_TOP_AUD_K3_SRC_DIV>, - <&topckgen CLK_TOP_AUD_K4_SRC_DIV>, - <&topckgen CLK_TOP_AUD_I2S1_MCLK>, - <&topckgen CLK_TOP_AUD_I2S2_MCLK>, - <&topckgen CLK_TOP_AUD_I2S3_MCLK>, - <&topckgen CLK_TOP_AUD_I2S4_MCLK>, - <&audsys CLK_AUD_I2SO1>, - <&audsys CLK_AUD_I2SO2>, - <&audsys CLK_AUD_I2SO3>, - <&audsys CLK_AUD_I2SO4>, - <&audsys CLK_AUD_I2SIN1>, - <&audsys CLK_AUD_I2SIN2>, - <&audsys CLK_AUD_I2SIN3>, - <&audsys CLK_AUD_I2SIN4>, - <&audsys CLK_AUD_ASRCO1>, - <&audsys CLK_AUD_ASRCO2>, - <&audsys CLK_AUD_ASRCO3>, - <&audsys CLK_AUD_ASRCO4>, - <&audsys CLK_AUD_AFE>, - <&audsys CLK_AUD_AFE_CONN>, - <&audsys CLK_AUD_A1SYS>, - <&audsys CLK_AUD_A2SYS>, - <&audsys CLK_AUD_AFE_MRGIF>; - - clock-names = "infra_sys_audio_clk", - "top_audio_mux1_sel", - "top_audio_mux2_sel", - "top_audio_a1sys_hp", - "top_audio_a2sys_hp", - "i2s0_src_sel", - "i2s1_src_sel", - "i2s2_src_sel", - "i2s3_src_sel", - "i2s0_src_div", - "i2s1_src_div", - "i2s2_src_div", - "i2s3_src_div", - "i2s0_mclk_en", - "i2s1_mclk_en", - "i2s2_mclk_en", - "i2s3_mclk_en", - "i2so0_hop_ck", - "i2so1_hop_ck", - "i2so2_hop_ck", - "i2so3_hop_ck", - "i2si0_hop_ck", - "i2si1_hop_ck", - "i2si2_hop_ck", - "i2si3_hop_ck", - "asrc0_out_ck", - "asrc1_out_ck", - "asrc2_out_ck", - "asrc3_out_ck", - "audio_afe_pd", - "audio_afe_conn_pd", - "audio_a1sys_pd", - "audio_a2sys_pd", - "audio_mrgif_pd"; - - assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>, - <&topckgen CLK_TOP_AUD_MUX2_SEL>, - <&topckgen CLK_TOP_AUD_MUX1_DIV>, - <&topckgen CLK_TOP_AUD_MUX2_DIV>; - assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>, - <&topckgen CLK_TOP_AUD2PLL_90M>; - assigned-clock-rates = <0>, <0>, <49152000>, <45158400>; - }; - }; - - mmsys: syscon@14000000 { - compatible = "mediatek,mt2701-mmsys", "syscon"; - reg = <0 0x14000000 0 0x1000>; - #clock-cells = <1>; - }; - - bls: pwm@1400a000 { - compatible = "mediatek,mt2701-disp-pwm"; - reg = <0 0x1400a000 0 0x1000>; - #pwm-cells = <2>; - clocks = <&mmsys CLK_MM_MDP_BLS_26M>, <&mmsys CLK_MM_DISP_BLS>; - clock-names = "main", "mm"; - status = "disabled"; - }; - - larb0: larb@14010000 { - compatible = "mediatek,mt2701-smi-larb"; - reg = <0 0x14010000 0 0x1000>; - mediatek,smi = <&smi_common>; - mediatek,larb-id = <0>; - clocks = <&mmsys CLK_MM_SMI_LARB0>, - <&mmsys CLK_MM_SMI_LARB0>; - clock-names = "apb", "smi"; - power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>; - }; - - imgsys: syscon@15000000 { - compatible = "mediatek,mt2701-imgsys", "syscon"; - reg = <0 0x15000000 0 0x1000>; - #clock-cells = <1>; - }; - - larb2: larb@15001000 { - compatible = "mediatek,mt2701-smi-larb"; - reg = <0 0x15001000 0 0x1000>; - mediatek,smi = <&smi_common>; - mediatek,larb-id = <2>; - clocks = <&imgsys CLK_IMG_SMI_COMM>, - <&imgsys CLK_IMG_SMI_COMM>; - clock-names = "apb", "smi"; - power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>; - }; - - jpegdec: jpegdec@15004000 { - compatible = "mediatek,mt2701-jpgdec"; - reg = <0 0x15004000 0 0x1000>; - interrupts = ; - clocks = <&imgsys CLK_IMG_JPGDEC_SMI>, - <&imgsys CLK_IMG_JPGDEC>; - clock-names = "jpgdec-smi", - "jpgdec"; - power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>; - mediatek,larb = <&larb2>; - iommus = <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>, - <&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>; - }; - - vdecsys: syscon@16000000 { - compatible = "mediatek,mt2701-vdecsys", "syscon"; - reg = <0 0x16000000 0 0x1000>; - #clock-cells = <1>; - }; - - larb1: larb@16010000 { - compatible = "mediatek,mt2701-smi-larb"; - reg = <0 0x16010000 0 0x1000>; - mediatek,smi = <&smi_common>; - mediatek,larb-id = <1>; - clocks = <&vdecsys CLK_VDEC_CKGEN>, - <&vdecsys CLK_VDEC_LARB>; - clock-names = "apb", "smi"; - power-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>; - }; - - hifsys: syscon@1a000000 { - compatible = "mediatek,mt2701-hifsys", "syscon"; - reg = <0 0x1a000000 0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - usb0: usb@1a1c0000 { - compatible = "mediatek,mt8173-xhci"; - reg = <0 0x1a1c0000 0 0x1000>, - <0 0x1a1c4700 0 0x0100>; - reg-names = "mac", "ippc"; - interrupts = ; - clocks = <&hifsys CLK_HIFSYS_USB0PHY>, - <&topckgen CLK_TOP_ETHIF_SEL>; - clock-names = "sys_ck", "ref_ck"; - power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>; - phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>; - status = "disabled"; - }; - - u3phy0: usb-phy@1a1c4000 { - compatible = "mediatek,mt2701-u3phy"; - reg = <0 0x1a1c4000 0 0x0700>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - status = "disabled"; - - u2port0: usb-phy@1a1c4800 { - reg = <0 0x1a1c4800 0 0x0100>; - clocks = <&topckgen CLK_TOP_USB_PHY48M>; - clock-names = "ref"; - #phy-cells = <1>; - status = "okay"; - }; - - u3port0: usb-phy@1a1c4900 { - reg = <0 0x1a1c4900 0 0x0700>; - clocks = <&clk26m>; - clock-names = "ref"; - #phy-cells = <1>; - status = "okay"; - }; - }; - - usb1: usb@1a240000 { - compatible = "mediatek,mt8173-xhci"; - reg = <0 0x1a240000 0 0x1000>, - <0 0x1a244700 0 0x0100>; - reg-names = "mac", "ippc"; - interrupts = ; - clocks = <&hifsys CLK_HIFSYS_USB1PHY>, - <&topckgen CLK_TOP_ETHIF_SEL>; - clock-names = "sys_ck", "ref_ck"; - power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>; - phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>; - status = "disabled"; - }; - - u3phy1: usb-phy@1a244000 { - compatible = "mediatek,mt2701-u3phy"; - reg = <0 0x1a244000 0 0x0700>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - status = "disabled"; - - u2port1: usb-phy@1a244800 { - reg = <0 0x1a244800 0 0x0100>; - clocks = <&topckgen CLK_TOP_USB_PHY48M>; - clock-names = "ref"; - #phy-cells = <1>; - status = "okay"; - }; - - u3port1: usb-phy@1a244900 { - reg = <0 0x1a244900 0 0x0700>; - clocks = <&clk26m>; - clock-names = "ref"; - #phy-cells = <1>; - status = "okay"; - }; - }; - - ethsys: syscon@1b000000 { - compatible = "mediatek,mt2701-ethsys", "syscon"; - reg = <0 0x1b000000 0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - eth: ethernet@1b100000 { - compatible = "mediatek,mt2701-eth", "syscon"; - reg = <0 0x1b100000 0 0x20000>; - interrupts = , - , - ; - clocks = <&topckgen CLK_TOP_ETHIF_SEL>, - <ðsys CLK_ETHSYS_ESW>, - <ðsys CLK_ETHSYS_GP1>, - <ðsys CLK_ETHSYS_GP2>, - <&apmixedsys CLK_APMIXED_TRGPLL>; - clock-names = "ethif", "esw", "gp1", "gp2", "trgpll"; - resets = <ðsys MT2701_ETHSYS_FE_RST>, - <ðsys MT2701_ETHSYS_GMAC_RST>, - <ðsys MT2701_ETHSYS_PPE_RST>; - reset-names = "fe", "gmac", "ppe"; - power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>; - mediatek,ethsys = <ðsys>; - mediatek,pctl = <&syscfg_pctl_a>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - bdpsys: syscon@1c000000 { - compatible = "mediatek,mt2701-bdpsys", "syscon"; - reg = <0 0x1c000000 0 0x1000>; - #clock-cells = <1>; - }; -}; diff --git a/sys/gnu/dts/arm/mt6323.dtsi b/sys/gnu/dts/arm/mt6323.dtsi deleted file mode 100644 index 7fda40ab5fe..00000000000 --- a/sys/gnu/dts/arm/mt6323.dtsi +++ /dev/null @@ -1,269 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2017-2018 MediaTek Inc. - * Author: John Crispin - * Sean Wang - * - */ - -&pwrap { - pmic: mt6323 { - compatible = "mediatek,mt6323"; - interrupt-parent = <&pio>; - interrupts = <150 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - #interrupt-cells = <2>; - - mt6323_leds: leds { - compatible = "mediatek,mt6323-led"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - mt6323regulator: mt6323regulator{ - compatible = "mediatek,mt6323-regulator"; - - mt6323_vproc_reg: buck_vproc{ - regulator-name = "vproc"; - regulator-min-microvolt = < 700000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <12500>; - regulator-always-on; - regulator-boot-on; - }; - - mt6323_vsys_reg: buck_vsys{ - regulator-name = "vsys"; - regulator-min-microvolt = <1400000>; - regulator-max-microvolt = <2987500>; - regulator-ramp-delay = <25000>; - regulator-always-on; - regulator-boot-on; - }; - - mt6323_vpa_reg: buck_vpa{ - regulator-name = "vpa"; - regulator-min-microvolt = < 500000>; - regulator-max-microvolt = <3650000>; - }; - - mt6323_vtcxo_reg: ldo_vtcxo{ - regulator-name = "vtcxo"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-enable-ramp-delay = <90>; - regulator-always-on; - regulator-boot-on; - }; - - mt6323_vcn28_reg: ldo_vcn28{ - regulator-name = "vcn28"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-enable-ramp-delay = <185>; - }; - - mt6323_vcn33_bt_reg: ldo_vcn33_bt{ - regulator-name = "vcn33_bt"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3600000>; - regulator-enable-ramp-delay = <185>; - }; - - mt6323_vcn33_wifi_reg: ldo_vcn33_wifi{ - regulator-name = "vcn33_wifi"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3600000>; - regulator-enable-ramp-delay = <185>; - }; - - mt6323_va_reg: ldo_va{ - regulator-name = "va"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-enable-ramp-delay = <216>; - regulator-always-on; - regulator-boot-on; - }; - - mt6323_vcama_reg: ldo_vcama{ - regulator-name = "vcama"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <2800000>; - regulator-enable-ramp-delay = <216>; - }; - - mt6323_vio28_reg: ldo_vio28{ - regulator-name = "vio28"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-enable-ramp-delay = <216>; - regulator-always-on; - regulator-boot-on; - }; - - mt6323_vusb_reg: ldo_vusb{ - regulator-name = "vusb"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <216>; - regulator-boot-on; - }; - - mt6323_vmc_reg: ldo_vmc{ - regulator-name = "vmc"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <36>; - regulator-boot-on; - }; - - mt6323_vmch_reg: ldo_vmch{ - regulator-name = "vmch"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <36>; - regulator-boot-on; - }; - - mt6323_vemc3v3_reg: ldo_vemc3v3{ - regulator-name = "vemc3v3"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <36>; - regulator-boot-on; - }; - - mt6323_vgp1_reg: ldo_vgp1{ - regulator-name = "vgp1"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <216>; - }; - - mt6323_vgp2_reg: ldo_vgp2{ - regulator-name = "vgp2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3000000>; - regulator-enable-ramp-delay = <216>; - }; - - mt6323_vgp3_reg: ldo_vgp3{ - regulator-name = "vgp3"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1800000>; - regulator-enable-ramp-delay = <216>; - }; - - mt6323_vcn18_reg: ldo_vcn18{ - regulator-name = "vcn18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-enable-ramp-delay = <216>; - }; - - mt6323_vsim1_reg: ldo_vsim1{ - regulator-name = "vsim1"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3000000>; - regulator-enable-ramp-delay = <216>; - }; - - mt6323_vsim2_reg: ldo_vsim2{ - regulator-name = "vsim2"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3000000>; - regulator-enable-ramp-delay = <216>; - }; - - mt6323_vrtc_reg: ldo_vrtc{ - regulator-name = "vrtc"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - regulator-boot-on; - }; - - mt6323_vcamaf_reg: ldo_vcamaf{ - regulator-name = "vcamaf"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <216>; - }; - - mt6323_vibr_reg: ldo_vibr{ - regulator-name = "vibr"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <36>; - }; - - mt6323_vrf18_reg: ldo_vrf18{ - regulator-name = "vrf18"; - regulator-min-microvolt = <1825000>; - regulator-max-microvolt = <1825000>; - regulator-enable-ramp-delay = <187>; - }; - - mt6323_vm_reg: ldo_vm{ - regulator-name = "vm"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1800000>; - regulator-enable-ramp-delay = <216>; - regulator-always-on; - regulator-boot-on; - }; - - mt6323_vio18_reg: ldo_vio18{ - regulator-name = "vio18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-enable-ramp-delay = <216>; - regulator-always-on; - regulator-boot-on; - }; - - mt6323_vcamd_reg: ldo_vcamd{ - regulator-name = "vcamd"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1800000>; - regulator-enable-ramp-delay = <216>; - }; - - mt6323_vcamio_reg: ldo_vcamio{ - regulator-name = "vcamio"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-enable-ramp-delay = <216>; - }; - }; - - mt6323keys: mt6323keys { - compatible = "mediatek,mt6323-keys"; - mediatek,long-press-mode = <1>; - power-off-time-sec = <0>; - - power { - linux,keycodes = <116>; - wakeup-source; - }; - - home { - linux,keycodes = <114>; - }; - }; - - codec: mt6397codec { - compatible = "mediatek,mt6397-codec"; - }; - - power-controller { - compatible = "mediatek,mt6323-pwrc"; - }; - - rtc { - compatible = "mediatek,mt6323-rtc"; - }; - }; -}; diff --git a/sys/gnu/dts/arm/mt6580-evbp1.dts b/sys/gnu/dts/arm/mt6580-evbp1.dts deleted file mode 100644 index 755a0774a8e..00000000000 --- a/sys/gnu/dts/arm/mt6580-evbp1.dts +++ /dev/null @@ -1,32 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2015 MediaTek Inc. - * Author: Mars.C - * - */ - -/dts-v1/; -#include "mt6580.dtsi" - -/ { - model = "MediaTek MT6580 evaluation board"; - compatible = "mediatek,mt6580-evbp1", "mediatek,mt6580"; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - }; - - chosen { - stdout-path = "serial0:921600n8"; - }; - - memory { - device_type = "memory"; - reg = <0x80000000 0x20000000>; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/mt6580.dtsi b/sys/gnu/dts/arm/mt6580.dtsi deleted file mode 100644 index 9e17698c060..00000000000 --- a/sys/gnu/dts/arm/mt6580.dtsi +++ /dev/null @@ -1,108 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2015 MediaTek Inc. - * Author: Mars.C - * - */ - -#include -#include - -/ { - compatible = "mediatek,mt6580"; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&sysirq>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x0>; - }; - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x1>; - }; - cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x2>; - }; - cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x3>; - }; - - }; - - system_clk: dummy13m { - compatible = "fixed-clock"; - clock-frequency = <13000000>; - #clock-cells = <0>; - }; - - rtc_clk: dummy32k { - compatible = "fixed-clock"; - clock-frequency = <32000>; - #clock-cells = <0>; - }; - - uart_clk: dummy26m { - compatible = "fixed-clock"; - clock-frequency = <26000000>; - #clock-cells = <0>; - }; - - timer: timer@10008000 { - compatible = "mediatek,mt6580-timer", - "mediatek,mt6577-timer"; - reg = <0x10008000 0x80>; - interrupts = ; - clocks = <&system_clk>, <&rtc_clk>; - clock-names = "system-clk", "rtc-clk"; - }; - - sysirq: interrupt-controller@10200100 { - compatible = "mediatek,mt6580-sysirq", - "mediatek,mt6577-sysirq"; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - reg = <0x10200100 0x1c>; - }; - - gic: interrupt-controller@10211000 { - compatible = "arm,cortex-a7-gic"; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - reg = <0x10211000 0x1000>, - <0x10212000 0x2000>, - <0x10214000 0x2000>, - <0x10216000 0x2000>; - }; - - uart0: serial@11005000 { - compatible = "mediatek,mt6580-uart", - "mediatek,mt6577-uart"; - reg = <0x11005000 0x400>; - interrupts = ; - clocks = <&uart_clk>; - status = "disabled"; - }; - - uart1: serial@11006000 { - compatible = "mediatek,mt6580-uart", - "mediatek,mt6577-uart"; - reg = <0x11006000 0x400>; - interrupts = ; - clocks = <&uart_clk>; - status = "disabled"; - }; -}; diff --git a/sys/gnu/dts/arm/mt6589-aquaris5.dts b/sys/gnu/dts/arm/mt6589-aquaris5.dts deleted file mode 100644 index 1e7079a3b44..00000000000 --- a/sys/gnu/dts/arm/mt6589-aquaris5.dts +++ /dev/null @@ -1,33 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (c) 2014 MundoReader S.L. - * Author: Matthias Brugger - * - */ - -/dts-v1/; -#include "mt6589.dtsi" - -/ { - model = "bq Aquaris5"; - compatible = "mundoreader,bq-aquaris5", "mediatek,mt6589"; - - chosen { - bootargs = "console=ttyS0,921600n8 earlyprintk"; - stdout-path = &uart0; - }; - - memory { - device_type = "memory"; - reg = <0x80000000 0x40000000>; - }; - -}; - -&uart0 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/mt6589.dtsi b/sys/gnu/dts/arm/mt6589.dtsi deleted file mode 100644 index f3ccb70c077..00000000000 --- a/sys/gnu/dts/arm/mt6589.dtsi +++ /dev/null @@ -1,140 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (c) 2014 MundoReader S.L. - * Author: Matthias Brugger - * -*/ - -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - compatible = "mediatek,mt6589"; - interrupt-parent = <&sysirq>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x0>; - }; - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x1>; - }; - cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x2>; - }; - cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x3>; - }; - - }; - - clocks { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges; - - system_clk: dummy13m { - compatible = "fixed-clock"; - clock-frequency = <13000000>; - #clock-cells = <0>; - }; - - rtc_clk: dummy32k { - compatible = "fixed-clock"; - clock-frequency = <32000>; - #clock-cells = <0>; - }; - - uart_clk: dummy26m { - compatible = "fixed-clock"; - clock-frequency = <26000000>; - #clock-cells = <0>; - }; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges; - - timer: timer@10008000 { - compatible = "mediatek,mt6577-timer"; - reg = <0x10008000 0x80>; - interrupts = ; - clocks = <&system_clk>, <&rtc_clk>; - clock-names = "system-clk", "rtc-clk"; - }; - - sysirq: interrupt-controller@10200100 { - compatible = "mediatek,mt6589-sysirq", - "mediatek,mt6577-sysirq"; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - reg = <0x10200100 0x1c>; - }; - - gic: interrupt-controller@10211000 { - compatible = "arm,cortex-a7-gic"; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - reg = <0x10211000 0x1000>, - <0x10212000 0x2000>, - <0x10214000 0x2000>, - <0x10216000 0x2000>; - }; - - uart0: serial@11006000 { - compatible = "mediatek,mt6577-uart"; - reg = <0x11006000 0x400>; - interrupts = ; - clocks = <&uart_clk>; - status = "disabled"; - }; - - uart1: serial@11007000 { - compatible = "mediatek,mt6577-uart"; - reg = <0x11007000 0x400>; - interrupts = ; - clocks = <&uart_clk>; - status = "disabled"; - }; - - uart2: serial@11008000 { - compatible = "mediatek,mt6577-uart"; - reg = <0x11008000 0x400>; - interrupts = ; - clocks = <&uart_clk>; - status = "disabled"; - }; - - uart3: serial@11009000 { - compatible = "mediatek,mt6577-uart"; - reg = <0x11009000 0x400>; - interrupts = ; - clocks = <&uart_clk>; - status = "disabled"; - }; - - wdt: watchdog@10000000 { - compatible = "mediatek,mt6589-wdt"; - reg = <0x10000000 0x44>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/mt6592-evb.dts b/sys/gnu/dts/arm/mt6592-evb.dts deleted file mode 100644 index 5e00c1cca2d..00000000000 --- a/sys/gnu/dts/arm/mt6592-evb.dts +++ /dev/null @@ -1,19 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2014 MediaTek Inc. - * Author: Howard Chen - * - */ - -/dts-v1/; -#include "mt6592.dtsi" - -/ { - model = "mt6592 evb"; - compatible = "mediatek,mt6592-evb", "mediatek,mt6592"; - - memory { - device_type = "memory"; - reg = <0x80000000 0x40000000>; - }; -}; diff --git a/sys/gnu/dts/arm/mt6592.dtsi b/sys/gnu/dts/arm/mt6592.dtsi deleted file mode 100644 index 3716f8db951..00000000000 --- a/sys/gnu/dts/arm/mt6592.dtsi +++ /dev/null @@ -1,137 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2014 MediaTek Inc. - * Author: Howard Chen - * - */ - -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - compatible = "mediatek,mt6592"; - interrupt-parent = <&sysirq>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x0>; - }; - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x1>; - }; - cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x2>; - }; - cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x3>; - }; - cpu@4 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x4>; - }; - cpu@5 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x5>; - }; - cpu@6 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x6>; - }; - cpu@7 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x7>; - }; - }; - - system_clk: dummy13m { - compatible = "fixed-clock"; - clock-frequency = <13000000>; - #clock-cells = <0>; - }; - - rtc_clk: dummy32k { - compatible = "fixed-clock"; - clock-frequency = <32000>; - #clock-cells = <0>; - }; - - uart_clk: dummy26m { - compatible = "fixed-clock"; - clock-frequency = <26000000>; - #clock-cells = <0>; - }; - - timer: timer@10008000 { - compatible = "mediatek,mt6577-timer"; - reg = <0x10008000 0x80>; - interrupts = ; - clocks = <&system_clk>, <&rtc_clk>; - clock-names = "system-clk", "rtc-clk"; - }; - - sysirq: interrupt-controller@10200220 { - compatible = "mediatek,mt6592-sysirq", "mediatek,mt6577-sysirq"; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - reg = <0x10200220 0x1c>; - }; - - gic: interrupt-controller@10211000 { - compatible = "arm,cortex-a7-gic"; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - reg = <0x10211000 0x1000>, - <0x10212000 0x1000>; - }; - - uart0: serial@11002000 { - compatible = "mediatek,mt6577-uart"; - reg = <0x11002000 0x400>; - interrupts = ; - clocks = <&uart_clk>; - status = "disabled"; - }; - - uart1: serial@11003000 { - compatible = "mediatek,mt6577-uart"; - reg = <0x11003000 0x400>; - interrupts = ; - clocks = <&uart_clk>; - status = "disabled"; - }; - - uart2: serial@11004000 { - compatible = "mediatek,mt6577-uart"; - reg = <0x11004000 0x400>; - interrupts = ; - clocks = <&uart_clk>; - status = "disabled"; - }; - - uart3: serial@11005000 { - compatible = "mediatek,mt6577-uart"; - reg = <0x11005000 0x400>; - interrupts = ; - clocks = <&uart_clk>; - status = "disabled"; - }; -}; diff --git a/sys/gnu/dts/arm/mt7623.dtsi b/sys/gnu/dts/arm/mt7623.dtsi deleted file mode 100644 index a79f0b6c342..00000000000 --- a/sys/gnu/dts/arm/mt7623.dtsi +++ /dev/null @@ -1,1365 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2017-2018 MediaTek Inc. - * Author: John Crispin - * Sean Wang - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/ { - compatible = "mediatek,mt7623"; - interrupt-parent = <&sysirq>; - #address-cells = <2>; - #size-cells = <2>; - - cpu_opp_table: opp-table { - compatible = "operating-points-v2"; - opp-shared; - - opp-98000000 { - opp-hz = /bits/ 64 <98000000>; - opp-microvolt = <1050000>; - }; - - opp-198000000 { - opp-hz = /bits/ 64 <198000000>; - opp-microvolt = <1050000>; - }; - - opp-398000000 { - opp-hz = /bits/ 64 <398000000>; - opp-microvolt = <1050000>; - }; - - opp-598000000 { - opp-hz = /bits/ 64 <598000000>; - opp-microvolt = <1050000>; - }; - - opp-747500000 { - opp-hz = /bits/ 64 <747500000>; - opp-microvolt = <1050000>; - }; - - opp-1040000000 { - opp-hz = /bits/ 64 <1040000000>; - opp-microvolt = <1150000>; - }; - - opp-1196000000 { - opp-hz = /bits/ 64 <1196000000>; - opp-microvolt = <1200000>; - }; - - opp-1300000000 { - opp-hz = /bits/ 64 <1300000000>; - opp-microvolt = <1300000>; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "mediatek,mt6589-smp"; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x0>; - clocks = <&infracfg CLK_INFRA_CPUSEL>, - <&apmixedsys CLK_APMIXED_MAINPLL>; - clock-names = "cpu", "intermediate"; - operating-points-v2 = <&cpu_opp_table>; - #cooling-cells = <2>; - clock-frequency = <1300000000>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x1>; - clocks = <&infracfg CLK_INFRA_CPUSEL>, - <&apmixedsys CLK_APMIXED_MAINPLL>; - clock-names = "cpu", "intermediate"; - operating-points-v2 = <&cpu_opp_table>; - #cooling-cells = <2>; - clock-frequency = <1300000000>; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x2>; - clocks = <&infracfg CLK_INFRA_CPUSEL>, - <&apmixedsys CLK_APMIXED_MAINPLL>; - clock-names = "cpu", "intermediate"; - operating-points-v2 = <&cpu_opp_table>; - #cooling-cells = <2>; - clock-frequency = <1300000000>; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x3>; - clocks = <&infracfg CLK_INFRA_CPUSEL>, - <&apmixedsys CLK_APMIXED_MAINPLL>; - clock-names = "cpu", "intermediate"; - operating-points-v2 = <&cpu_opp_table>; - #cooling-cells = <2>; - clock-frequency = <1300000000>; - }; - }; - - pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts = , - , - , - ; - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; - }; - - system_clk: dummy13m { - compatible = "fixed-clock"; - clock-frequency = <13000000>; - #clock-cells = <0>; - }; - - rtc32k: oscillator-1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32000>; - clock-output-names = "rtc32k"; - }; - - clk26m: oscillator-0 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <26000000>; - clock-output-names = "clk26m"; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <1000>; - polling-delay = <1000>; - - thermal-sensors = <&thermal 0>; - - trips { - cpu_passive: cpu-passive { - temperature = <47000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu_active: cpu-active { - temperature = <67000>; - hysteresis = <2000>; - type = "active"; - }; - - cpu_hot: cpu-hot { - temperature = <87000>; - hysteresis = <2000>; - type = "hot"; - }; - - cpu-crit { - temperature = <107000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu_passive>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - - map1 { - trip = <&cpu_active>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - - map2 { - trip = <&cpu_hot>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupt-parent = <&gic>; - interrupts = , - , - , - ; - clock-frequency = <13000000>; - arm,cpu-registers-not-fw-configured; - }; - - topckgen: syscon@10000000 { - compatible = "mediatek,mt7623-topckgen", - "mediatek,mt2701-topckgen", - "syscon"; - reg = <0 0x10000000 0 0x1000>; - #clock-cells = <1>; - }; - - infracfg: syscon@10001000 { - compatible = "mediatek,mt7623-infracfg", - "mediatek,mt2701-infracfg", - "syscon"; - reg = <0 0x10001000 0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - pericfg: syscon@10003000 { - compatible = "mediatek,mt7623-pericfg", - "mediatek,mt2701-pericfg", - "syscon"; - reg = <0 0x10003000 0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - pio: pinctrl@10005000 { - compatible = "mediatek,mt7623-pinctrl"; - reg = <0 0x1000b000 0 0x1000>; - mediatek,pctl-regmap = <&syscfg_pctl_a>; - pins-are-numbered; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - interrupt-parent = <&gic>; - #interrupt-cells = <2>; - interrupts = , - ; - }; - - syscfg_pctl_a: syscfg@10005000 { - compatible = "mediatek,mt7623-pctl-a-syscfg", "syscon"; - reg = <0 0x10005000 0 0x1000>; - }; - - scpsys: scpsys@10006000 { - compatible = "mediatek,mt7623-scpsys", - "mediatek,mt2701-scpsys", - "syscon"; - #power-domain-cells = <1>; - reg = <0 0x10006000 0 0x1000>; - infracfg = <&infracfg>; - clocks = <&topckgen CLK_TOP_MM_SEL>, - <&topckgen CLK_TOP_MFG_SEL>, - <&topckgen CLK_TOP_ETHIF_SEL>; - clock-names = "mm", "mfg", "ethif"; - }; - - watchdog: watchdog@10007000 { - compatible = "mediatek,mt7623-wdt", - "mediatek,mt6589-wdt"; - reg = <0 0x10007000 0 0x100>; - }; - - timer: timer@10008000 { - compatible = "mediatek,mt7623-timer", - "mediatek,mt6577-timer"; - reg = <0 0x10008000 0 0x80>; - interrupts = ; - clocks = <&system_clk>, <&rtc32k>; - clock-names = "system-clk", "rtc-clk"; - }; - - smi_common: smi@1000c000 { - compatible = "mediatek,mt7623-smi-common", - "mediatek,mt2701-smi-common"; - reg = <0 0x1000c000 0 0x1000>; - clocks = <&infracfg CLK_INFRA_SMI>, - <&mmsys CLK_MM_SMI_COMMON>, - <&infracfg CLK_INFRA_SMI>; - clock-names = "apb", "smi", "async"; - power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>; - }; - - pwrap: pwrap@1000d000 { - compatible = "mediatek,mt7623-pwrap", - "mediatek,mt2701-pwrap"; - reg = <0 0x1000d000 0 0x1000>; - reg-names = "pwrap"; - interrupts = ; - resets = <&infracfg MT2701_INFRA_PMIC_WRAP_RST>; - reset-names = "pwrap"; - clocks = <&infracfg CLK_INFRA_PMICSPI>, - <&infracfg CLK_INFRA_PMICWRAP>; - clock-names = "spi", "wrap"; - }; - - cir: cir@10013000 { - compatible = "mediatek,mt7623-cir"; - reg = <0 0x10013000 0 0x1000>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_IRRX>; - clock-names = "clk"; - status = "disabled"; - }; - - sysirq: interrupt-controller@10200100 { - compatible = "mediatek,mt7623-sysirq", - "mediatek,mt6577-sysirq"; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - reg = <0 0x10200100 0 0x1c>; - }; - - iommu: mmsys_iommu@10205000 { - compatible = "mediatek,mt7623-m4u", - "mediatek,mt2701-m4u"; - reg = <0 0x10205000 0 0x1000>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_M4U>; - clock-names = "bclk"; - mediatek,larbs = <&larb0 &larb1 &larb2>; - #iommu-cells = <1>; - }; - - efuse: efuse@10206000 { - compatible = "mediatek,mt7623-efuse", - "mediatek,mt8173-efuse"; - reg = <0 0x10206000 0 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - thermal_calibration_data: calib@424 { - reg = <0x424 0xc>; - }; - }; - - apmixedsys: syscon@10209000 { - compatible = "mediatek,mt7623-apmixedsys", - "mediatek,mt2701-apmixedsys", - "syscon"; - reg = <0 0x10209000 0 0x1000>; - #clock-cells = <1>; - }; - - rng: rng@1020f000 { - compatible = "mediatek,mt7623-rng"; - reg = <0 0x1020f000 0 0x1000>; - clocks = <&infracfg CLK_INFRA_TRNG>; - clock-names = "rng"; - }; - - gic: interrupt-controller@10211000 { - compatible = "arm,cortex-a7-gic"; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - reg = <0 0x10211000 0 0x1000>, - <0 0x10212000 0 0x2000>, - <0 0x10214000 0 0x2000>, - <0 0x10216000 0 0x2000>; - }; - - auxadc: adc@11001000 { - compatible = "mediatek,mt7623-auxadc", - "mediatek,mt2701-auxadc"; - reg = <0 0x11001000 0 0x1000>; - clocks = <&pericfg CLK_PERI_AUXADC>; - clock-names = "main"; - #io-channel-cells = <1>; - }; - - uart0: serial@11002000 { - compatible = "mediatek,mt7623-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11002000 0 0x400>; - interrupts = ; - clocks = <&pericfg CLK_PERI_UART0_SEL>, - <&pericfg CLK_PERI_UART0>; - clock-names = "baud", "bus"; - status = "disabled"; - }; - - uart1: serial@11003000 { - compatible = "mediatek,mt7623-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11003000 0 0x400>; - interrupts = ; - clocks = <&pericfg CLK_PERI_UART1_SEL>, - <&pericfg CLK_PERI_UART1>; - clock-names = "baud", "bus"; - status = "disabled"; - }; - - uart2: serial@11004000 { - compatible = "mediatek,mt7623-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11004000 0 0x400>; - interrupts = ; - clocks = <&pericfg CLK_PERI_UART2_SEL>, - <&pericfg CLK_PERI_UART2>; - clock-names = "baud", "bus"; - status = "disabled"; - }; - - uart3: serial@11005000 { - compatible = "mediatek,mt7623-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11005000 0 0x400>; - interrupts = ; - clocks = <&pericfg CLK_PERI_UART3_SEL>, - <&pericfg CLK_PERI_UART3>; - clock-names = "baud", "bus"; - status = "disabled"; - }; - - pwm: pwm@11006000 { - compatible = "mediatek,mt7623-pwm"; - reg = <0 0x11006000 0 0x1000>; - #pwm-cells = <2>; - clocks = <&topckgen CLK_TOP_PWM_SEL>, - <&pericfg CLK_PERI_PWM>, - <&pericfg CLK_PERI_PWM1>, - <&pericfg CLK_PERI_PWM2>, - <&pericfg CLK_PERI_PWM3>, - <&pericfg CLK_PERI_PWM4>, - <&pericfg CLK_PERI_PWM5>; - clock-names = "top", "main", "pwm1", "pwm2", - "pwm3", "pwm4", "pwm5"; - status = "disabled"; - }; - - i2c0: i2c@11007000 { - compatible = "mediatek,mt7623-i2c", - "mediatek,mt6577-i2c"; - reg = <0 0x11007000 0 0x70>, - <0 0x11000200 0 0x80>; - interrupts = ; - clock-div = <16>; - clocks = <&pericfg CLK_PERI_I2C0>, - <&pericfg CLK_PERI_AP_DMA>; - clock-names = "main", "dma"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c1: i2c@11008000 { - compatible = "mediatek,mt7623-i2c", - "mediatek,mt6577-i2c"; - reg = <0 0x11008000 0 0x70>, - <0 0x11000280 0 0x80>; - interrupts = ; - clock-div = <16>; - clocks = <&pericfg CLK_PERI_I2C1>, - <&pericfg CLK_PERI_AP_DMA>; - clock-names = "main", "dma"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@11009000 { - compatible = "mediatek,mt7623-i2c", - "mediatek,mt6577-i2c"; - reg = <0 0x11009000 0 0x70>, - <0 0x11000300 0 0x80>; - interrupts = ; - clock-div = <16>; - clocks = <&pericfg CLK_PERI_I2C2>, - <&pericfg CLK_PERI_AP_DMA>; - clock-names = "main", "dma"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi0: spi@1100a000 { - compatible = "mediatek,mt7623-spi", - "mediatek,mt2701-spi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0 0x1100a000 0 0x100>; - interrupts = ; - clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, - <&topckgen CLK_TOP_SPI0_SEL>, - <&pericfg CLK_PERI_SPI0>; - clock-names = "parent-clk", "sel-clk", "spi-clk"; - status = "disabled"; - }; - - thermal: thermal@1100b000 { - #thermal-sensor-cells = <1>; - compatible = "mediatek,mt7623-thermal", - "mediatek,mt2701-thermal"; - reg = <0 0x1100b000 0 0x1000>; - interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>; - clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>; - clock-names = "therm", "auxadc"; - resets = <&pericfg MT2701_PERI_THERM_SW_RST>; - reset-names = "therm"; - mediatek,auxadc = <&auxadc>; - mediatek,apmixedsys = <&apmixedsys>; - nvmem-cells = <&thermal_calibration_data>; - nvmem-cell-names = "calibration-data"; - }; - - btif: serial@1100c000 { - compatible = "mediatek,mt7623-btif", - "mediatek,mtk-btif"; - reg = <0 0x1100c000 0 0x1000>; - interrupts = ; - clocks = <&pericfg CLK_PERI_BTIF>; - clock-names = "main"; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - nandc: nfi@1100d000 { - compatible = "mediatek,mt7623-nfc", - "mediatek,mt2701-nfc"; - reg = <0 0x1100d000 0 0x1000>; - interrupts = ; - power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>; - clocks = <&pericfg CLK_PERI_NFI>, - <&pericfg CLK_PERI_NFI_PAD>; - clock-names = "nfi_clk", "pad_clk"; - status = "disabled"; - ecc-engine = <&bch>; - #address-cells = <1>; - #size-cells = <0>; - }; - - bch: ecc@1100e000 { - compatible = "mediatek,mt7623-ecc", - "mediatek,mt2701-ecc"; - reg = <0 0x1100e000 0 0x1000>; - interrupts = ; - clocks = <&pericfg CLK_PERI_NFI_ECC>; - clock-names = "nfiecc_clk"; - status = "disabled"; - }; - - nor_flash: spi@11014000 { - compatible = "mediatek,mt7623-nor", - "mediatek,mt8173-nor"; - reg = <0 0x11014000 0 0x1000>; - clocks = <&pericfg CLK_PERI_FLASH>, - <&topckgen CLK_TOP_FLASH_SEL>; - clock-names = "spi", "sf"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi1: spi@11016000 { - compatible = "mediatek,mt7623-spi", - "mediatek,mt2701-spi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0 0x11016000 0 0x100>; - interrupts = ; - clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, - <&topckgen CLK_TOP_SPI1_SEL>, - <&pericfg CLK_PERI_SPI1>; - clock-names = "parent-clk", "sel-clk", "spi-clk"; - status = "disabled"; - }; - - spi2: spi@11017000 { - compatible = "mediatek,mt7623-spi", - "mediatek,mt2701-spi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0 0x11017000 0 0x1000>; - interrupts = ; - clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, - <&topckgen CLK_TOP_SPI2_SEL>, - <&pericfg CLK_PERI_SPI2>; - clock-names = "parent-clk", "sel-clk", "spi-clk"; - status = "disabled"; - }; - - audsys: clock-controller@11220000 { - compatible = "mediatek,mt7623-audsys", - "mediatek,mt2701-audsys", - "syscon"; - reg = <0 0x11220000 0 0x2000>; - #clock-cells = <1>; - - afe: audio-controller { - compatible = "mediatek,mt7623-audio", - "mediatek,mt2701-audio"; - interrupts = , - ; - interrupt-names = "afe", "asys"; - power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>; - - clocks = <&infracfg CLK_INFRA_AUDIO>, - <&topckgen CLK_TOP_AUD_MUX1_SEL>, - <&topckgen CLK_TOP_AUD_MUX2_SEL>, - <&topckgen CLK_TOP_AUD_48K_TIMING>, - <&topckgen CLK_TOP_AUD_44K_TIMING>, - <&topckgen CLK_TOP_AUD_K1_SRC_SEL>, - <&topckgen CLK_TOP_AUD_K2_SRC_SEL>, - <&topckgen CLK_TOP_AUD_K3_SRC_SEL>, - <&topckgen CLK_TOP_AUD_K4_SRC_SEL>, - <&topckgen CLK_TOP_AUD_K1_SRC_DIV>, - <&topckgen CLK_TOP_AUD_K2_SRC_DIV>, - <&topckgen CLK_TOP_AUD_K3_SRC_DIV>, - <&topckgen CLK_TOP_AUD_K4_SRC_DIV>, - <&topckgen CLK_TOP_AUD_I2S1_MCLK>, - <&topckgen CLK_TOP_AUD_I2S2_MCLK>, - <&topckgen CLK_TOP_AUD_I2S3_MCLK>, - <&topckgen CLK_TOP_AUD_I2S4_MCLK>, - <&audsys CLK_AUD_I2SO1>, - <&audsys CLK_AUD_I2SO2>, - <&audsys CLK_AUD_I2SO3>, - <&audsys CLK_AUD_I2SO4>, - <&audsys CLK_AUD_I2SIN1>, - <&audsys CLK_AUD_I2SIN2>, - <&audsys CLK_AUD_I2SIN3>, - <&audsys CLK_AUD_I2SIN4>, - <&audsys CLK_AUD_ASRCO1>, - <&audsys CLK_AUD_ASRCO2>, - <&audsys CLK_AUD_ASRCO3>, - <&audsys CLK_AUD_ASRCO4>, - <&audsys CLK_AUD_AFE>, - <&audsys CLK_AUD_AFE_CONN>, - <&audsys CLK_AUD_A1SYS>, - <&audsys CLK_AUD_A2SYS>, - <&audsys CLK_AUD_AFE_MRGIF>; - - clock-names = "infra_sys_audio_clk", - "top_audio_mux1_sel", - "top_audio_mux2_sel", - "top_audio_a1sys_hp", - "top_audio_a2sys_hp", - "i2s0_src_sel", - "i2s1_src_sel", - "i2s2_src_sel", - "i2s3_src_sel", - "i2s0_src_div", - "i2s1_src_div", - "i2s2_src_div", - "i2s3_src_div", - "i2s0_mclk_en", - "i2s1_mclk_en", - "i2s2_mclk_en", - "i2s3_mclk_en", - "i2so0_hop_ck", - "i2so1_hop_ck", - "i2so2_hop_ck", - "i2so3_hop_ck", - "i2si0_hop_ck", - "i2si1_hop_ck", - "i2si2_hop_ck", - "i2si3_hop_ck", - "asrc0_out_ck", - "asrc1_out_ck", - "asrc2_out_ck", - "asrc3_out_ck", - "audio_afe_pd", - "audio_afe_conn_pd", - "audio_a1sys_pd", - "audio_a2sys_pd", - "audio_mrgif_pd"; - - assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>, - <&topckgen CLK_TOP_AUD_MUX2_SEL>, - <&topckgen CLK_TOP_AUD_MUX1_DIV>, - <&topckgen CLK_TOP_AUD_MUX2_DIV>; - assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>, - <&topckgen CLK_TOP_AUD2PLL_90M>; - assigned-clock-rates = <0>, <0>, <49152000>, <45158400>; - }; - }; - - mmc0: mmc@11230000 { - compatible = "mediatek,mt7623-mmc", - "mediatek,mt2701-mmc"; - reg = <0 0x11230000 0 0x1000>; - interrupts = ; - clocks = <&pericfg CLK_PERI_MSDC30_0>, - <&topckgen CLK_TOP_MSDC30_0_SEL>; - clock-names = "source", "hclk"; - status = "disabled"; - }; - - mmc1: mmc@11240000 { - compatible = "mediatek,mt7623-mmc", - "mediatek,mt2701-mmc"; - reg = <0 0x11240000 0 0x1000>; - interrupts = ; - clocks = <&pericfg CLK_PERI_MSDC30_1>, - <&topckgen CLK_TOP_MSDC30_1_SEL>; - clock-names = "source", "hclk"; - status = "disabled"; - }; - - g3dsys: syscon@13000000 { - compatible = "mediatek,mt7623-g3dsys", - "mediatek,mt2701-g3dsys", - "syscon"; - reg = <0 0x13000000 0 0x200>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - mmsys: syscon@14000000 { - compatible = "mediatek,mt7623-mmsys", - "mediatek,mt2701-mmsys", - "syscon"; - reg = <0 0x14000000 0 0x1000>; - #clock-cells = <1>; - }; - - larb0: larb@14010000 { - compatible = "mediatek,mt7623-smi-larb", - "mediatek,mt2701-smi-larb"; - reg = <0 0x14010000 0 0x1000>; - mediatek,smi = <&smi_common>; - mediatek,larb-id = <0>; - clocks = <&mmsys CLK_MM_SMI_LARB0>, - <&mmsys CLK_MM_SMI_LARB0>; - clock-names = "apb", "smi"; - power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>; - }; - - imgsys: syscon@15000000 { - compatible = "mediatek,mt7623-imgsys", - "mediatek,mt2701-imgsys", - "syscon"; - reg = <0 0x15000000 0 0x1000>; - #clock-cells = <1>; - }; - - larb2: larb@15001000 { - compatible = "mediatek,mt7623-smi-larb", - "mediatek,mt2701-smi-larb"; - reg = <0 0x15001000 0 0x1000>; - mediatek,smi = <&smi_common>; - mediatek,larb-id = <2>; - clocks = <&imgsys CLK_IMG_SMI_COMM>, - <&imgsys CLK_IMG_SMI_COMM>; - clock-names = "apb", "smi"; - power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>; - }; - - jpegdec: jpegdec@15004000 { - compatible = "mediatek,mt7623-jpgdec", - "mediatek,mt2701-jpgdec"; - reg = <0 0x15004000 0 0x1000>; - interrupts = ; - clocks = <&imgsys CLK_IMG_JPGDEC_SMI>, - <&imgsys CLK_IMG_JPGDEC>; - clock-names = "jpgdec-smi", - "jpgdec"; - power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>; - mediatek,larb = <&larb2>; - iommus = <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>, - <&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>; - }; - - vdecsys: syscon@16000000 { - compatible = "mediatek,mt7623-vdecsys", - "mediatek,mt2701-vdecsys", - "syscon"; - reg = <0 0x16000000 0 0x1000>; - #clock-cells = <1>; - }; - - larb1: larb@16010000 { - compatible = "mediatek,mt7623-smi-larb", - "mediatek,mt2701-smi-larb"; - reg = <0 0x16010000 0 0x1000>; - mediatek,smi = <&smi_common>; - mediatek,larb-id = <1>; - clocks = <&vdecsys CLK_VDEC_CKGEN>, - <&vdecsys CLK_VDEC_LARB>; - clock-names = "apb", "smi"; - power-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>; - }; - - hifsys: syscon@1a000000 { - compatible = "mediatek,mt7623-hifsys", - "mediatek,mt2701-hifsys", - "syscon"; - reg = <0 0x1a000000 0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - pcie: pcie@1a140000 { - compatible = "mediatek,mt7623-pcie"; - device_type = "pci"; - reg = <0 0x1a140000 0 0x1000>, /* PCIe shared registers */ - <0 0x1a142000 0 0x1000>, /* Port0 registers */ - <0 0x1a143000 0 0x1000>, /* Port1 registers */ - <0 0x1a144000 0 0x1000>; /* Port2 registers */ - reg-names = "subsys", "port0", "port1", "port2"; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - interrupt-map-mask = <0xf800 0 0 0>; - interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>, - <0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>, - <0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>; - clocks = <&topckgen CLK_TOP_ETHIF_SEL>, - <&hifsys CLK_HIFSYS_PCIE0>, - <&hifsys CLK_HIFSYS_PCIE1>, - <&hifsys CLK_HIFSYS_PCIE2>; - clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2"; - resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>, - <&hifsys MT2701_HIFSYS_PCIE1_RST>, - <&hifsys MT2701_HIFSYS_PCIE2_RST>; - reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2"; - phys = <&pcie0_port PHY_TYPE_PCIE>, - <&pcie1_port PHY_TYPE_PCIE>, - <&u3port1 PHY_TYPE_PCIE>; - phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2"; - power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>; - bus-range = <0x00 0xff>; - status = "disabled"; - ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000 - 0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>; - - pcie@0,0 { - reg = <0x0000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>; - ranges; - status = "disabled"; - }; - - pcie@1,0 { - reg = <0x0800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>; - ranges; - status = "disabled"; - }; - - pcie@2,0 { - reg = <0x1000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>; - ranges; - status = "disabled"; - }; - }; - - pcie0_phy: pcie-phy@1a149000 { - compatible = "mediatek,generic-tphy-v1"; - reg = <0 0x1a149000 0 0x0700>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - status = "disabled"; - - pcie0_port: pcie-phy@1a149900 { - reg = <0 0x1a149900 0 0x0700>; - clocks = <&clk26m>; - clock-names = "ref"; - #phy-cells = <1>; - status = "okay"; - }; - }; - - pcie1_phy: pcie-phy@1a14a000 { - compatible = "mediatek,generic-tphy-v1"; - reg = <0 0x1a14a000 0 0x0700>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - status = "disabled"; - - pcie1_port: pcie-phy@1a14a900 { - reg = <0 0x1a14a900 0 0x0700>; - clocks = <&clk26m>; - clock-names = "ref"; - #phy-cells = <1>; - status = "okay"; - }; - }; - - usb1: usb@1a1c0000 { - compatible = "mediatek,mt7623-xhci", - "mediatek,mt8173-xhci"; - reg = <0 0x1a1c0000 0 0x1000>, - <0 0x1a1c4700 0 0x0100>; - reg-names = "mac", "ippc"; - interrupts = ; - clocks = <&hifsys CLK_HIFSYS_USB0PHY>, - <&topckgen CLK_TOP_ETHIF_SEL>; - clock-names = "sys_ck", "ref_ck"; - power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>; - phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>; - status = "disabled"; - }; - - u3phy1: usb-phy@1a1c4000 { - compatible = "mediatek,mt7623-u3phy", - "mediatek,mt2701-u3phy"; - reg = <0 0x1a1c4000 0 0x0700>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - status = "disabled"; - - u2port0: usb-phy@1a1c4800 { - reg = <0 0x1a1c4800 0 0x0100>; - clocks = <&topckgen CLK_TOP_USB_PHY48M>; - clock-names = "ref"; - #phy-cells = <1>; - status = "okay"; - }; - - u3port0: usb-phy@1a1c4900 { - reg = <0 0x1a1c4900 0 0x0700>; - clocks = <&clk26m>; - clock-names = "ref"; - #phy-cells = <1>; - status = "okay"; - }; - }; - - usb2: usb@1a240000 { - compatible = "mediatek,mt7623-xhci", - "mediatek,mt8173-xhci"; - reg = <0 0x1a240000 0 0x1000>, - <0 0x1a244700 0 0x0100>; - reg-names = "mac", "ippc"; - interrupts = ; - clocks = <&hifsys CLK_HIFSYS_USB1PHY>, - <&topckgen CLK_TOP_ETHIF_SEL>; - clock-names = "sys_ck", "ref_ck"; - power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>; - phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>; - status = "disabled"; - }; - - u3phy2: usb-phy@1a244000 { - compatible = "mediatek,mt7623-u3phy", - "mediatek,mt2701-u3phy"; - reg = <0 0x1a244000 0 0x0700>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - status = "disabled"; - - u2port1: usb-phy@1a244800 { - reg = <0 0x1a244800 0 0x0100>; - clocks = <&topckgen CLK_TOP_USB_PHY48M>; - clock-names = "ref"; - #phy-cells = <1>; - status = "okay"; - }; - - u3port1: usb-phy@1a244900 { - reg = <0 0x1a244900 0 0x0700>; - clocks = <&clk26m>; - clock-names = "ref"; - #phy-cells = <1>; - status = "okay"; - }; - }; - - ethsys: syscon@1b000000 { - compatible = "mediatek,mt7623-ethsys", - "mediatek,mt2701-ethsys", - "syscon"; - reg = <0 0x1b000000 0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - hsdma: dma-controller@1b007000 { - compatible = "mediatek,mt7623-hsdma"; - reg = <0 0x1b007000 0 0x1000>; - interrupts = ; - clocks = <ðsys CLK_ETHSYS_HSDMA>; - clock-names = "hsdma"; - power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>; - #dma-cells = <1>; - }; - - eth: ethernet@1b100000 { - compatible = "mediatek,mt7623-eth", - "mediatek,mt2701-eth", - "syscon"; - reg = <0 0x1b100000 0 0x20000>; - interrupts = , - , - ; - clocks = <&topckgen CLK_TOP_ETHIF_SEL>, - <ðsys CLK_ETHSYS_ESW>, - <ðsys CLK_ETHSYS_GP1>, - <ðsys CLK_ETHSYS_GP2>, - <&apmixedsys CLK_APMIXED_TRGPLL>; - clock-names = "ethif", "esw", "gp1", "gp2", "trgpll"; - resets = <ðsys MT2701_ETHSYS_FE_RST>, - <ðsys MT2701_ETHSYS_GMAC_RST>, - <ðsys MT2701_ETHSYS_PPE_RST>; - reset-names = "fe", "gmac", "ppe"; - power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>; - mediatek,ethsys = <ðsys>; - mediatek,pctl = <&syscfg_pctl_a>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - crypto: crypto@1b240000 { - compatible = "mediatek,eip97-crypto"; - reg = <0 0x1b240000 0 0x20000>; - interrupts = , - , - , - , - ; - clocks = <ðsys CLK_ETHSYS_CRYPTO>; - clock-names = "cryp"; - power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>; - status = "disabled"; - }; - - bdpsys: syscon@1c000000 { - compatible = "mediatek,mt7623-bdpsys", - "mediatek,mt2701-bdpsys", - "syscon"; - reg = <0 0x1c000000 0 0x1000>; - #clock-cells = <1>; - }; -}; - -&pio { - cir_pins_a:cir-default { - pins-cir { - pinmux = ; - bias-disable; - }; - }; - - i2c0_pins_a: i2c0-default { - pins-i2c0 { - pinmux = , - ; - bias-disable; - }; - }; - - i2c1_pins_a: i2c1-default { - pin-i2c1 { - pinmux = , - ; - bias-disable; - }; - }; - - i2c1_pins_b: i2c1-alt { - pin-i2c1 { - pinmux = , - ; - bias-disable; - }; - }; - - i2c2_pins_a: i2c2-default { - pin-i2c2 { - pinmux = , - ; - bias-disable; - }; - }; - - i2c2_pins_b: i2c2-alt { - pin-i2c2 { - pinmux = , - ; - bias-disable; - }; - }; - - i2s0_pins_a: i2s0-default { - pin-i2s0 { - pinmux = , - , - , - , - ; - drive-strength = ; - bias-pull-down; - }; - }; - - i2s1_pins_a: i2s1-default { - pin-i2s1 { - pinmux = , - , - , - , - ; - drive-strength = ; - bias-pull-down; - }; - }; - - key_pins_a: keys-alt { - pins-keys { - pinmux = , - ; - input-enable; - }; - }; - - led_pins_a: leds-alt { - pins-leds { - pinmux = , - , - ; - }; - }; - - mmc0_pins_default: mmc0default { - pins-cmd-dat { - pinmux = , - , - , - , - , - , - , - , - ; - input-enable; - bias-pull-up; - }; - - pins-clk { - pinmux = ; - bias-pull-down; - }; - - pins-rst { - pinmux = ; - bias-pull-up; - }; - }; - - mmc0_pins_uhs: mmc0 { - pins-cmd-dat { - pinmux = , - , - , - , - , - , - , - , - ; - input-enable; - drive-strength = ; - bias-pull-up = ; - }; - - pins-clk { - pinmux = ; - drive-strength = ; - bias-pull-down = ; - }; - - pins-rst { - pinmux = ; - bias-pull-up; - }; - }; - - mmc1_pins_default: mmc1default { - pins-cmd-dat { - pinmux = , - , - , - , - ; - input-enable; - drive-strength = ; - bias-pull-up = ; - }; - - pins-clk { - pinmux = ; - bias-pull-down; - drive-strength = ; - }; - - pins-wp { - pinmux = ; - input-enable; - bias-pull-up; - }; - - pins-insert { - pinmux = ; - bias-pull-up; - }; - }; - - mmc1_pins_uhs: mmc1 { - pins-cmd-dat { - pinmux = , - , - , - , - ; - input-enable; - drive-strength = ; - bias-pull-up = ; - }; - - pins-clk { - pinmux = ; - drive-strength = ; - bias-pull-down = ; - }; - }; - - nand_pins_default: nanddefault { - pins-ale { - pinmux = ; - drive-strength = ; - bias-pull-down = ; - }; - - pins-dat { - pinmux = , - , - , - , - , - , - , - , - ; - input-enable; - drive-strength = ; - bias-pull-up; - }; - - pins-we { - pinmux = ; - drive-strength = ; - bias-pull-up = ; - }; - }; - - pcie_default: pcie_pin_default { - pins_cmd_dat { - pinmux = , - ; - bias-disable; - }; - }; - - pwm_pins_a: pwm-default { - pins-pwm { - pinmux = , - , - , - , - ; - }; - }; - - spi0_pins_a: spi0-default { - pins-spi { - pinmux = , - , - , - ; - bias-disable; - }; - }; - - spi1_pins_a: spi1-default { - pins-spi { - pinmux = , - , - , - ; - }; - }; - - spi2_pins_a: spi2-default { - pins-spi { - pinmux = , - , - , - ; - }; - }; - - uart0_pins_a: uart0-default { - pins-dat { - pinmux = , - ; - }; - }; - - uart1_pins_a: uart1-default { - pins-dat { - pinmux = , - ; - }; - }; - - uart2_pins_a: uart2-default { - pins-dat { - pinmux = , - ; - }; - }; - - uart2_pins_b: uart2-alt { - pins-dat { - pinmux = , - ; - }; - }; -}; diff --git a/sys/gnu/dts/arm/mt7623a-rfb-emmc.dts b/sys/gnu/dts/arm/mt7623a-rfb-emmc.dts deleted file mode 100644 index 13c86936d1c..00000000000 --- a/sys/gnu/dts/arm/mt7623a-rfb-emmc.dts +++ /dev/null @@ -1,291 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2017-2018 MediaTek Inc. - * Author: Sean Wang - * - */ - -/dts-v1/; -#include -#include "mt7623a.dtsi" -#include "mt6323.dtsi" - -/ { - model = "MediaTek MT7623A with eMMC reference board"; - compatible = "mediatek,mt7623a-rfb-emmc", "mediatek,mt7623"; - - aliases { - serial2 = &uart2; - }; - - chosen { - stdout-path = "serial2:115200n8"; - }; - - cpus { - cpu@0 { - proc-supply = <&mt6323_vproc_reg>; - }; - - cpu@1 { - proc-supply = <&mt6323_vproc_reg>; - }; - - cpu@2 { - proc-supply = <&mt6323_vproc_reg>; - }; - - cpu@3 { - proc-supply = <&mt6323_vproc_reg>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&key_pins_a>; - - factory { - label = "factory"; - linux,code = ; - gpios = <&pio 256 GPIO_ACTIVE_LOW>; - }; - - wps { - label = "wps"; - linux,code = ; - gpios = <&pio 257 GPIO_ACTIVE_HIGH>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0 0x80000000 0 0x20000000>; - }; - - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-name = "fixed-1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_5v: regulator-5v { - compatible = "regulator-fixed"; - regulator-name = "fixed-5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - regulator-always-on; - }; - - sound { - compatible = "mediatek,mt2701-wm8960-machine"; - mediatek,platform = <&afe>; - audio-routing = - "Headphone", "HP_L", - "Headphone", "HP_R", - "LINPUT1", "AMIC", - "RINPUT1", "AMIC"; - mediatek,audio-codec = <&wm8960>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_pins_a>; - }; -}; - -&btif { - status = "okay"; -}; - -&crypto { - status = "okay"; -}; - -ð { - status = "okay"; - - gmac0: mac@0 { - compatible = "mediatek,eth-mac"; - reg = <0>; - phy-mode = "trgmii"; - - fixed-link { - speed = <1000>; - full-duplex; - pause; - }; - }; - - mdio-bus { - #address-cells = <1>; - #size-cells = <0>; - - switch@0 { - compatible = "mediatek,mt7530"; - reg = <0>; - mediatek,mcm; - resets = <ðsys MT2701_ETHSYS_MCM_RST>; - reset-names = "mcm"; - core-supply = <&mt6323_vpa_reg>; - io-supply = <&mt6323_vemc3v3_reg>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "lan0"; - }; - - port@1 { - reg = <1>; - label = "lan1"; - }; - - port@2 { - reg = <2>; - label = "lan2"; - }; - - port@3 { - reg = <3>; - label = "lan3"; - }; - - port@4 { - reg = <4>; - label = "wan"; - }; - - port@6 { - reg = <6>; - label = "cpu"; - ethernet = <&gmac0>; - phy-mode = "trgmii"; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; - }; - }; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_b>; - status = "okay"; - - wm8960: wm8960@1a { - compatible = "wlf,wm8960"; - reg = <0x1a>; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_b>; - status = "okay"; -}; - -&mmc0 { - pinctrl-names = "default", "state_uhs"; - pinctrl-0 = <&mmc0_pins_default>; - pinctrl-1 = <&mmc0_pins_uhs>; - status = "okay"; - bus-width = <8>; - max-frequency = <50000000>; - cap-mmc-highspeed; - vmmc-supply = <®_3p3v>; - vqmmc-supply = <®_1p8v>; - non-removable; -}; - -&mmc1 { - pinctrl-names = "default", "state_uhs"; - pinctrl-0 = <&mmc1_pins_default>; - pinctrl-1 = <&mmc1_pins_uhs>; - status = "okay"; - bus-width = <4>; - max-frequency = <50000000>; - cap-sd-highspeed; - cd-gpios = <&pio 261 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_3p3v>; - vqmmc-supply = <®_3p3v>; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pcie_default>; - status = "okay"; - - pcie@0,0 { - status = "okay"; - }; - - pcie@1,0 { - status = "okay"; - }; -}; - -&pcie0_phy { - status = "okay"; -}; - -&pcie1_phy { - status = "okay"; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm_pins_a>; - status = "okay"; -}; - -&spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins_a>; - status = "okay"; -}; - -&spi1 { - pinctrl-names = "default"; - pinctrl-0 = <&spi1_pins_a>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins_b>; - status = "okay"; -}; - -&usb1 { - vusb33-supply = <®_3p3v>; - vbus-supply = <®_5v>; - status = "okay"; -}; - -&u3phy1 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/mt7623a-rfb-nand.dts b/sys/gnu/dts/arm/mt7623a-rfb-nand.dts deleted file mode 100644 index 88d8f0b2f4c..00000000000 --- a/sys/gnu/dts/arm/mt7623a-rfb-nand.dts +++ /dev/null @@ -1,337 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2017-2018 MediaTek Inc. - * Author: Sean Wang - * - */ - -/dts-v1/; -#include -#include "mt7623a.dtsi" -#include "mt6323.dtsi" - -/ { - model = "MediaTek MT7623A with NAND reference board"; - compatible = "mediatek,mt7623a-rfb-nand", "mediatek,mt7623"; - - aliases { - serial2 = &uart2; - }; - - chosen { - stdout-path = "serial2:115200n8"; - }; - - cpus { - cpu@0 { - proc-supply = <&mt6323_vproc_reg>; - }; - - cpu@1 { - proc-supply = <&mt6323_vproc_reg>; - }; - - cpu@2 { - proc-supply = <&mt6323_vproc_reg>; - }; - - cpu@3 { - proc-supply = <&mt6323_vproc_reg>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&key_pins_a>; - - factory { - label = "factory"; - linux,code = ; - gpios = <&pio 256 GPIO_ACTIVE_LOW>; - }; - - wps { - label = "wps"; - linux,code = ; - gpios = <&pio 257 GPIO_ACTIVE_HIGH>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0 0x80000000 0 0x20000000>; - }; - - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-name = "fixed-1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_5v: regulator-5v { - compatible = "regulator-fixed"; - regulator-name = "fixed-5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - regulator-always-on; - }; - - sound { - compatible = "mediatek,mt2701-wm8960-machine"; - mediatek,platform = <&afe>; - audio-routing = - "Headphone", "HP_L", - "Headphone", "HP_R", - "LINPUT1", "AMIC", - "RINPUT1", "AMIC"; - mediatek,audio-codec = <&wm8960>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_pins_a>; - }; -}; - -&bch { - status = "okay"; -}; - -&btif { - status = "okay"; -}; - -&crypto { - status = "okay"; -}; - -ð { - status = "okay"; - - gmac0: mac@0 { - compatible = "mediatek,eth-mac"; - reg = <0>; - phy-mode = "trgmii"; - - fixed-link { - speed = <1000>; - full-duplex; - pause; - }; - }; - - mdio-bus { - #address-cells = <1>; - #size-cells = <0>; - - switch@0 { - compatible = "mediatek,mt7530"; - reg = <0>; - mediatek,mcm; - resets = <ðsys MT2701_ETHSYS_MCM_RST>; - reset-names = "mcm"; - core-supply = <&mt6323_vpa_reg>; - io-supply = <&mt6323_vemc3v3_reg>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "lan0"; - }; - - port@1 { - reg = <1>; - label = "lan1"; - }; - - port@2 { - reg = <2>; - label = "lan2"; - }; - - port@3 { - reg = <3>; - label = "lan3"; - }; - - port@4 { - reg = <4>; - label = "wan"; - }; - - port@6 { - reg = <6>; - label = "cpu"; - ethernet = <&gmac0>; - phy-mode = "trgmii"; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; - }; - }; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_b>; - status = "okay"; - - wm8960: wm8960@1a { - compatible = "wlf,wm8960"; - reg = <0x1a>; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_b>; - status = "okay"; -}; - -&mmc1 { - pinctrl-names = "default", "state_uhs"; - pinctrl-0 = <&mmc1_pins_default>; - pinctrl-1 = <&mmc1_pins_uhs>; - status = "okay"; - bus-width = <4>; - max-frequency = <50000000>; - cap-sd-highspeed; - cd-gpios = <&pio 261 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_3p3v>; - vqmmc-supply = <®_3p3v>; -}; - -&nandc { - pinctrl-names = "default"; - pinctrl-0 = <&nand_pins_default>; - status = "okay"; - - nand@0 { - reg = <0>; - spare_per_sector = <64>; - nand-ecc-mode = "hw"; - nand-ecc-strength = <12>; - nand-ecc-step-size = <1024>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "preloader"; - reg = <0x0 0x40000>; - }; - - partition@40000 { - label = "uboot"; - reg = <0x40000 0x80000>; - }; - - partition@c0000 { - label = "uboot-env"; - reg = <0xC0000 0x40000>; - }; - - partition@140000 { - label = "bootimg"; - reg = <0x140000 0x2000000>; - }; - - partition@2140000 { - label = "recovery"; - reg = <0x2140000 0x2000000>; - }; - - partition@4140000 { - label = "rootfs"; - reg = <0x4140000 0x1000000>; - }; - - partition@5140000 { - label = "usrdata"; - reg = <0x5140000 0x1000000>; - }; - }; - }; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pcie_default>; - status = "okay"; - - pcie@0,0 { - status = "okay"; - }; - - pcie@1,0 { - status = "okay"; - }; -}; - -&pcie0_phy { - status = "okay"; -}; - -&pcie1_phy { - status = "okay"; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm_pins_a>; - status = "okay"; -}; - -&spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins_a>; - status = "okay"; -}; - -&spi1 { - pinctrl-names = "default"; - pinctrl-0 = <&spi1_pins_a>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins_b>; - status = "okay"; -}; - -&usb1 { - vusb33-supply = <®_3p3v>; - vbus-supply = <®_5v>; - status = "okay"; -}; - -&u3phy1 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/mt7623a.dtsi b/sys/gnu/dts/arm/mt7623a.dtsi deleted file mode 100644 index 0735a1fb8ad..00000000000 --- a/sys/gnu/dts/arm/mt7623a.dtsi +++ /dev/null @@ -1,44 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2017-2018 MediaTek Inc. - * Author: Sean Wang - * - */ - -/dts-v1/; -#include -#include "mt7623.dtsi" - -&afe { - power-domains = <&scpsys MT7623A_POWER_DOMAIN_IFR_MSC>; -}; - -&crypto { - power-domains = <&scpsys MT7623A_POWER_DOMAIN_ETH>; -}; - -ð { - power-domains = <&scpsys MT7623A_POWER_DOMAIN_ETH>; -}; - -&nandc { - power-domains = <&scpsys MT7623A_POWER_DOMAIN_IFR_MSC>; -}; - -&pcie { - power-domains = <&scpsys MT7623A_POWER_DOMAIN_HIF>; -}; - -&scpsys { - compatible = "mediatek,mt7623a-scpsys"; - clocks = <&topckgen CLK_TOP_ETHIF_SEL>; - clock-names = "ethif"; -}; - -&usb1 { - power-domains = <&scpsys MT7623A_POWER_DOMAIN_HIF>; -}; - -&usb2 { - power-domains = <&scpsys MT7623A_POWER_DOMAIN_HIF>; -}; diff --git a/sys/gnu/dts/arm/mt7623n-bananapi-bpi-r2.dts b/sys/gnu/dts/arm/mt7623n-bananapi-bpi-r2.dts deleted file mode 100644 index 2b760f90f38..00000000000 --- a/sys/gnu/dts/arm/mt7623n-bananapi-bpi-r2.dts +++ /dev/null @@ -1,333 +0,0 @@ -/* - * Copyright 2017-2018 Sean Wang - * - * SPDX-License-Identifier: (GPL-2.0+ OR MIT) - */ - -/dts-v1/; -#include -#include "mt7623.dtsi" -#include "mt6323.dtsi" - -/ { - model = "Bananapi BPI-R2"; - compatible = "bananapi,bpi-r2", "mediatek,mt7623"; - - aliases { - serial2 = &uart2; - }; - - chosen { - stdout-path = "serial2:115200n8"; - }; - - cpus { - cpu@0 { - proc-supply = <&mt6323_vproc_reg>; - }; - - cpu@1 { - proc-supply = <&mt6323_vproc_reg>; - }; - - cpu@2 { - proc-supply = <&mt6323_vproc_reg>; - }; - - cpu@3 { - proc-supply = <&mt6323_vproc_reg>; - }; - }; - - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-name = "fixed-1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_5v: regulator-5v { - compatible = "regulator-fixed"; - regulator-name = "fixed-5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - regulator-always-on; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&key_pins_a>; - - factory { - label = "factory"; - linux,code = ; - gpios = <&pio 256 GPIO_ACTIVE_LOW>; - }; - - wps { - label = "wps"; - linux,code = ; - gpios = <&pio 257 GPIO_ACTIVE_HIGH>; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_a>; - - blue { - label = "bpi-r2:pio:blue"; - gpios = <&pio 240 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - green { - label = "bpi-r2:pio:green"; - gpios = <&pio 241 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - red { - label = "bpi-r2:pio:red"; - gpios = <&pio 239 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0 0x80000000 0 0x80000000>; - }; -}; - -&btif { - status = "okay"; -}; - -&cir { - pinctrl-names = "default"; - pinctrl-0 = <&cir_pins_a>; - status = "okay"; -}; - -&crypto { - status = "okay"; -}; - -ð { - status = "okay"; - - gmac0: mac@0 { - compatible = "mediatek,eth-mac"; - reg = <0>; - phy-mode = "trgmii"; - - fixed-link { - speed = <1000>; - full-duplex; - pause; - }; - }; - - mdio: mdio-bus { - #address-cells = <1>; - #size-cells = <0>; - - switch@0 { - compatible = "mediatek,mt7530"; - reg = <0>; - reset-gpios = <&pio 33 0>; - core-supply = <&mt6323_vpa_reg>; - io-supply = <&mt6323_vemc3v3_reg>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "wan"; - }; - - port@1 { - reg = <1>; - label = "lan0"; - }; - - port@2 { - reg = <2>; - label = "lan1"; - }; - - port@3 { - reg = <3>; - label = "lan2"; - }; - - port@4 { - reg = <4>; - label = "lan3"; - }; - - port@6 { - reg = <6>; - label = "cpu"; - ethernet = <&gmac0>; - phy-mode = "trgmii"; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; - }; - }; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; - status = "okay"; -}; - -&mmc0 { - pinctrl-names = "default", "state_uhs"; - pinctrl-0 = <&mmc0_pins_default>; - pinctrl-1 = <&mmc0_pins_uhs>; - status = "okay"; - bus-width = <8>; - max-frequency = <50000000>; - cap-mmc-highspeed; - vmmc-supply = <®_3p3v>; - vqmmc-supply = <®_1p8v>; - non-removable; -}; - -&mmc1 { - pinctrl-names = "default", "state_uhs"; - pinctrl-0 = <&mmc1_pins_default>; - pinctrl-1 = <&mmc1_pins_uhs>; - status = "okay"; - bus-width = <4>; - max-frequency = <50000000>; - cap-sd-highspeed; - cd-gpios = <&pio 261 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_3p3v>; - vqmmc-supply = <®_3p3v>; -}; - -&mt6323_leds { - status = "okay"; - - led@0 { - reg = <0>; - label = "bpi-r2:isink:green"; - default-state = "off"; - }; - - led@1 { - reg = <1>; - label = "bpi-r2:isink:red"; - default-state = "off"; - }; - - led@2 { - reg = <2>; - label = "bpi-r2:isink:blue"; - default-state = "off"; - }; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pcie_default>; - status = "okay"; - - pcie@0,0 { - status = "okay"; - }; - - pcie@1,0 { - status = "okay"; - }; -}; - -&pcie0_phy { - status = "okay"; -}; - -&pcie1_phy { - status = "okay"; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm_pins_a>; - status = "okay"; -}; - -&spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins_a>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins_a>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins_a>; - status = "okay"; -}; - -&usb1 { - vusb33-supply = <®_3p3v>; - vbus-supply = <®_5v>; - status = "okay"; -}; - -&usb2 { - vusb33-supply = <®_3p3v>; - vbus-supply = <®_5v>; - status = "okay"; -}; - -&u3phy1 { - status = "okay"; -}; - -&u3phy2 { - status = "okay"; -}; - diff --git a/sys/gnu/dts/arm/mt7623n-rfb-emmc.dts b/sys/gnu/dts/arm/mt7623n-rfb-emmc.dts deleted file mode 100644 index b7606130ade..00000000000 --- a/sys/gnu/dts/arm/mt7623n-rfb-emmc.dts +++ /dev/null @@ -1,326 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2017-2018 MediaTek Inc. - * Author: Sean Wang - * - */ - -/dts-v1/; -#include -#include "mt7623.dtsi" -#include "mt6323.dtsi" - -/ { - model = "MediaTek MT7623N with eMMC reference board"; - compatible = "mediatek,mt7623n-rfb-emmc", "mediatek,mt7623"; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - }; - - chosen { - stdout-path = "serial2:115200n8"; - }; - - cpus { - cpu@0 { - proc-supply = <&mt6323_vproc_reg>; - }; - - cpu@1 { - proc-supply = <&mt6323_vproc_reg>; - }; - - cpu@2 { - proc-supply = <&mt6323_vproc_reg>; - }; - - cpu@3 { - proc-supply = <&mt6323_vproc_reg>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&key_pins_a>; - - factory { - label = "factory"; - linux,code = ; - gpios = <&pio 256 GPIO_ACTIVE_LOW>; - }; - - wps { - label = "wps"; - linux,code = ; - gpios = <&pio 257 GPIO_ACTIVE_HIGH>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0 0x80000000 0 0x40000000>; - }; - - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-name = "fixed-1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_5v: regulator-5v { - compatible = "regulator-fixed"; - regulator-name = "fixed-5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - regulator-always-on; - }; - - sound { - compatible = "mediatek,mt2701-wm8960-machine"; - mediatek,platform = <&afe>; - audio-routing = - "Headphone", "HP_L", - "Headphone", "HP_R", - "LINPUT1", "AMIC", - "RINPUT1", "AMIC"; - mediatek,audio-codec = <&wm8960>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_pins_a>; - }; -}; - -&btif { - status = "okay"; -}; - -&cir { - pinctrl-names = "default"; - pinctrl-0 = <&cir_pins_a>; - status = "okay"; -}; - -&crypto { - status = "okay"; -}; - -ð { - status = "okay"; - - gmac0: mac@0 { - compatible = "mediatek,eth-mac"; - reg = <0>; - phy-mode = "trgmii"; - - fixed-link { - speed = <1000>; - full-duplex; - pause; - }; - }; - - mac@1 { - compatible = "mediatek,eth-mac"; - reg = <1>; - phy-handle = <&phy5>; - }; - - mdio-bus { - #address-cells = <1>; - #size-cells = <0>; - - phy5: ethernet-phy@5 { - reg = <5>; - phy-mode = "rgmii-rxid"; - }; - - switch@0 { - compatible = "mediatek,mt7530"; - reg = <0>; - reset-gpios = <&pio 33 0>; - core-supply = <&mt6323_vpa_reg>; - io-supply = <&mt6323_vemc3v3_reg>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "lan0"; - }; - - port@1 { - reg = <1>; - label = "lan1"; - }; - - port@2 { - reg = <2>; - label = "lan2"; - }; - - port@3 { - reg = <3>; - label = "lan3"; - }; - - port@4 { - reg = <4>; - label = "wan"; - }; - - port@6 { - reg = <6>; - label = "cpu"; - ethernet = <&gmac0>; - phy-mode = "trgmii"; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; - }; - }; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_b>; - status = "okay"; - - wm8960: wm8960@1a { - compatible = "wlf,wm8960"; - reg = <0x1a>; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; - status = "okay"; -}; - -&mmc0 { - pinctrl-names = "default", "state_uhs"; - pinctrl-0 = <&mmc0_pins_default>; - pinctrl-1 = <&mmc0_pins_uhs>; - status = "okay"; - bus-width = <8>; - max-frequency = <50000000>; - cap-mmc-highspeed; - vmmc-supply = <®_3p3v>; - vqmmc-supply = <®_1p8v>; - non-removable; -}; - -&mmc1 { - pinctrl-names = "default", "state_uhs"; - pinctrl-0 = <&mmc1_pins_default>; - pinctrl-1 = <&mmc1_pins_uhs>; - status = "okay"; - bus-width = <4>; - max-frequency = <50000000>; - cap-sd-highspeed; - cd-gpios = <&pio 261 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_3p3v>; - vqmmc-supply = <®_3p3v>; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pcie_default>; - status = "okay"; - - pcie@0,0 { - status = "okay"; - }; - - pcie@1,0 { - status = "okay"; - }; -}; - -&pcie0_phy { - status = "okay"; -}; - -&pcie1_phy { - status = "okay"; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm_pins_a>; - status = "okay"; -}; - -&spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins_a>; - status = "okay"; -}; - -&spi1 { - pinctrl-names = "default"; - pinctrl-0 = <&spi1_pins_a>; - status = "okay"; -}; - -&spi2 { - pinctrl-names = "default"; - pinctrl-0 = <&spi2_pins_a>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins_a>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins_a>; - status = "okay"; -}; - -&usb1 { - vusb33-supply = <®_3p3v>; - vbus-supply = <®_5v>; - status = "okay"; -}; - -&u3phy1 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/mt7629-rfb.dts b/sys/gnu/dts/arm/mt7629-rfb.dts deleted file mode 100644 index 9980c10c6e2..00000000000 --- a/sys/gnu/dts/arm/mt7629-rfb.dts +++ /dev/null @@ -1,274 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2019 MediaTek Inc. - * Author: Ryder Lee - */ - -/dts-v1/; -#include -#include "mt7629.dtsi" - -/ { - model = "MediaTek MT7629 reference board"; - compatible = "mediatek,mt7629-rfb", "mediatek,mt7629"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - gpio-keys { - compatible = "gpio-keys"; - - reset { - label = "factory"; - linux,code = ; - gpios = <&pio 60 GPIO_ACTIVE_LOW>; - }; - - wps { - label = "wps"; - linux,code = ; - gpios = <&pio 58 GPIO_ACTIVE_LOW>; - }; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x10000000>; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_5v: regulator-5v { - compatible = "regulator-fixed"; - regulator-name = "fixed-5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - regulator-always-on; - }; -}; - -ð { - pinctrl-names = "default"; - pinctrl-0 = <ð_pins>; - pinctrl-1 = <&ephy_leds_pins>; - status = "okay"; - - gmac0: mac@0 { - compatible = "mediatek,eth-mac"; - reg = <0>; - phy-mode = "2500base-x"; - fixed-link { - speed = <2500>; - full-duplex; - pause; - }; - }; - - gmac1: mac@1 { - compatible = "mediatek,eth-mac"; - reg = <1>; - phy-mode = "gmii"; - phy-handle = <&phy0>; - }; - - mdio: mdio-bus { - #address-cells = <1>; - #size-cells = <0>; - - phy0: ethernet-phy@0 { - reg = <0>; - }; - }; -}; - -&i2c { - pinctrl-names = "default"; - pinctrl-0 = <&i2c_pins>; - status = "okay"; -}; - -&qspi { - pinctrl-names = "default"; - pinctrl-0 = <&qspi_pins>; - status = "okay"; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x00000 0x60000>; - read-only; - }; - - partition@60000 { - label = "u-boot-env"; - reg = <0x60000 0x10000>; - read-only; - }; - - factory: partition@70000 { - label = "factory"; - reg = <0x70000 0x40000>; - read-only; - }; - - partition@b0000 { - label = "kernel"; - reg = <0xb0000 0xb50000>; - }; - }; - }; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pcie_pins>; -}; - -&pciephy1 { - status = "okay"; -}; - -&pio { - eth_pins: eth-pins { - mux { - function = "eth"; - groups = "mdc_mdio"; - }; - }; - - ephy_leds_pins: ephy-leds-pins { - mux { - function = "led"; - groups = "gphy_leds_0", "ephy_leds"; - }; - }; - - i2c_pins: i2c-pins { - mux { - function = "i2c"; - groups = "i2c_0"; - }; - - conf { - pins = "I2C_SDA", "I2C_SCL"; - drive-strength = <4>; - bias-disable; - }; - }; - - pcie_pins: pcie-pins { - mux { - function = "pcie"; - groups = "pcie_clkreq", - "pcie_pereset", - "pcie_wake"; - }; - }; - - pwm_pins: pwm-pins { - mux { - function = "pwm"; - groups = "pwm_0"; - }; - }; - - /* SPI-NOR is shared pin with serial NAND */ - qspi_pins: qspi-pins { - mux { - function = "flash"; - groups = "spi_nor"; - }; - }; - - /* Serial NAND is shared pin with SPI-NOR */ - serial_nand_pins: serial-nand-pins { - mux { - function = "flash"; - groups = "snfi"; - }; - }; - - spi_pins: spi-pins { - mux { - function = "spi"; - groups = "spi_0"; - }; - }; - - uart0_pins: uart0-pins { - mux { - function = "uart"; - groups = "uart0_txd_rxd" ; - }; - }; - - uart1_pins: uart1-pins { - mux { - function = "uart"; - groups = "uart1_0_tx_rx" ; - }; - }; - - uart2_pins: uart2-pins { - mux { - function = "uart"; - groups = "uart2_0_txd_rxd" ; - }; - }; - - watchdog_pins: watchdog-pins { - mux { - function = "watchdog"; - groups = "watchdog"; - }; - }; -}; - -&spi { - pinctrl-names = "default"; - pinctrl-0 = <&spi_pins>; - status = "okay"; -}; - -&ssusb { - vusb33-supply = <®_3p3v>; - vbus-supply = <®_5v>; - status = "okay"; -}; - -&u3phy0 { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - status = "okay"; -}; - -&watchdog { - pinctrl-names = "default"; - pinctrl-0 = <&watchdog_pins>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/mt7629.dtsi b/sys/gnu/dts/arm/mt7629.dtsi deleted file mode 100644 index 867b88103b9..00000000000 --- a/sys/gnu/dts/arm/mt7629.dtsi +++ /dev/null @@ -1,479 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2019 MediaTek Inc. - * - * Author: Ryder Lee - */ - -#include -#include -#include -#include -#include -#include -#include - -/ { - compatible = "mediatek,mt7629"; - interrupt-parent = <&sysirq>; - #address-cells = <1>; - #size-cells = <1>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "mediatek,mt6589-smp"; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x0>; - clock-frequency = <1250000000>; - cci-control-port = <&cci_control2>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x1>; - clock-frequency = <1250000000>; - cci-control-port = <&cci_control2>; - }; - }; - - pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts = , - ; - interrupt-affinity = <&cpu0>, <&cpu1>; - }; - - clk20m: oscillator-0 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <20000000>; - clock-output-names = "clk20m"; - }; - - clk40m: oscillator-1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <40000000>; - clock-output-names = "clkxtal"; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupt-parent = <&gic>; - interrupts = , - , - , - ; - clock-frequency = <20000000>; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - infracfg: syscon@10000000 { - compatible = "mediatek,mt7629-infracfg", "syscon"; - reg = <0x10000000 0x1000>; - #clock-cells = <1>; - }; - - pericfg: syscon@10002000 { - compatible = "mediatek,mt7629-pericfg", "syscon"; - reg = <0x10002000 0x1000>; - #clock-cells = <1>; - }; - - scpsys: scpsys@10006000 { - compatible = "mediatek,mt7629-scpsys", - "mediatek,mt7622-scpsys"; - #power-domain-cells = <1>; - reg = <0x10006000 0x1000>; - clocks = <&topckgen CLK_TOP_HIF_SEL>; - clock-names = "hif_sel"; - assigned-clocks = <&topckgen CLK_TOP_HIF_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>; - infracfg = <&infracfg>; - }; - - timer: timer@10009000 { - compatible = "mediatek,mt7629-timer", - "mediatek,mt6765-timer"; - reg = <0x10009000 0x60>; - interrupts = , - ; - clocks = <&clk20m>; - clock-names = "clk20m"; - }; - - sysirq: interrupt-controller@10200a80 { - compatible = "mediatek,mt7629-sysirq", - "mediatek,mt6577-sysirq"; - reg = <0x10200a80 0x20>; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - }; - - apmixedsys: syscon@10209000 { - compatible = "mediatek,mt7629-apmixedsys", "syscon"; - reg = <0x10209000 0x1000>; - #clock-cells = <1>; - }; - - rng: rng@1020f000 { - compatible = "mediatek,mt7629-rng", - "mediatek,mt7623-rng"; - reg = <0x1020f000 0x100>; - clocks = <&infracfg CLK_INFRA_TRNG_PD>; - clock-names = "rng"; - }; - - topckgen: syscon@10210000 { - compatible = "mediatek,mt7629-topckgen", "syscon"; - reg = <0x10210000 0x1000>; - #clock-cells = <1>; - }; - - watchdog: watchdog@10212000 { - compatible = "mediatek,mt7629-wdt", - "mediatek,mt6589-wdt"; - reg = <0x10212000 0x100>; - }; - - pio: pinctrl@10217000 { - compatible = "mediatek,mt7629-pinctrl"; - reg = <0x10217000 0x8000>, - <0x10005000 0x1000>; - reg-names = "base", "eint"; - gpio-controller; - gpio-ranges = <&pio 0 0 79>; - #gpio-cells = <2>; - #interrupt-cells = <2>; - interrupt-controller; - interrupts = ; - interrupt-parent = <&gic>; - }; - - gic: interrupt-controller@10300000 { - compatible = "arm,gic-400"; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - reg = <0x10310000 0x1000>, - <0x10320000 0x1000>, - <0x10340000 0x2000>, - <0x10360000 0x2000>; - }; - - cci: cci@10390000 { - compatible = "arm,cci-400"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x10390000 0x1000>; - ranges = <0 0x10390000 0x10000>; - - cci_control0: slave-if@1000 { - compatible = "arm,cci-400-ctrl-if"; - interface-type = "ace-lite"; - reg = <0x1000 0x1000>; - }; - - cci_control1: slave-if@4000 { - compatible = "arm,cci-400-ctrl-if"; - interface-type = "ace"; - reg = <0x4000 0x1000>; - }; - - cci_control2: slave-if@5000 { - compatible = "arm,cci-400-ctrl-if"; - interface-type = "ace"; - reg = <0x5000 0x1000>; - }; - - pmu@9000 { - compatible = "arm,cci-400-pmu,r1"; - reg = <0x9000 0x5000>; - interrupts = , - , - , - , - ; - }; - }; - - uart0: serial@11002000 { - compatible = "mediatek,mt7629-uart", - "mediatek,mt6577-uart"; - reg = <0x11002000 0x400>; - interrupts = ; - clocks = <&topckgen CLK_TOP_UART_SEL>, - <&pericfg CLK_PERI_UART0_PD>; - clock-names = "baud", "bus"; - status = "disabled"; - }; - - uart1: serial@11003000 { - compatible = "mediatek,mt7629-uart", - "mediatek,mt6577-uart"; - reg = <0x11003000 0x400>; - interrupts = ; - clocks = <&topckgen CLK_TOP_UART_SEL>, - <&pericfg CLK_PERI_UART1_PD>; - clock-names = "baud", "bus"; - status = "disabled"; - }; - - uart2: serial@11004000 { - compatible = "mediatek,mt7629-uart", - "mediatek,mt6577-uart"; - reg = <0x11004000 0x400>; - interrupts = ; - clocks = <&topckgen CLK_TOP_UART_SEL>, - <&pericfg CLK_PERI_UART2_PD>; - clock-names = "baud", "bus"; - status = "disabled"; - }; - - i2c: i2c@11007000 { - compatible = "mediatek,mt7629-i2c", - "mediatek,mt2712-i2c"; - reg = <0x11007000 0x90>, - <0x11000100 0x80>; - interrupts = ; - clock-div = <4>; - clocks = <&pericfg CLK_PERI_I2C0_PD>, - <&pericfg CLK_PERI_AP_DMA_PD>; - clock-names = "main", "dma"; - assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi: spi@1100a000 { - compatible = "mediatek,mt7629-spi", - "mediatek,mt7622-spi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x1100a000 0x100>; - interrupts = ; - clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, - <&topckgen CLK_TOP_SPI0_SEL>, - <&pericfg CLK_PERI_SPI0_PD>; - clock-names = "parent-clk", "sel-clk", "spi-clk"; - status = "disabled"; - }; - - qspi: spi@11014000 { - compatible = "mediatek,mt7629-nor", - "mediatek,mt8173-nor"; - reg = <0x11014000 0xe0>; - clocks = <&pericfg CLK_PERI_FLASH_PD>, - <&topckgen CLK_TOP_FLASH_SEL>; - clock-names = "spi", "sf"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - ssusbsys: syscon@1a000000 { - compatible = "mediatek,mt7629-ssusbsys", "syscon"; - reg = <0x1a000000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - ssusb: usb@1a0c0000 { - compatible = "mediatek,mt7629-xhci", - "mediatek,mtk-xhci"; - reg = <0x1a0c0000 0x01000>, - <0x1a0c3e00 0x0100>; - reg-names = "mac", "ippc"; - interrupts = ; - clocks = <&ssusbsys CLK_SSUSB_SYS_EN>, - <&ssusbsys CLK_SSUSB_REF_EN>, - <&ssusbsys CLK_SSUSB_MCU_EN>, - <&ssusbsys CLK_SSUSB_DMA_EN>; - clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck"; - assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>, - <&topckgen CLK_TOP_SATA_SEL>, - <&topckgen CLK_TOP_HIF_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>, - <&topckgen CLK_TOP_UNIVPLL2_D4>, - <&topckgen CLK_TOP_UNIVPLL1_D2>; - power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF1>; - phys = <&u2port0 PHY_TYPE_USB2>, - <&u3port0 PHY_TYPE_USB3>; - status = "disabled"; - }; - - u3phy0: usb-phy@1a0c4000 { - compatible = "mediatek,generic-tphy-v2"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1a0c4000 0xe00>; - status = "disabled"; - - u2port0: usb-phy@0 { - reg = <0 0x700>; - clocks = <&ssusbsys CLK_SSUSB_U2_PHY_EN>; - clock-names = "ref"; - #phy-cells = <1>; - status = "okay"; - }; - - u3port0: usb-phy@700 { - reg = <0x700 0x700>; - clocks = <&clk20m>; - clock-names = "ref"; - #phy-cells = <1>; - status = "okay"; - }; - }; - - pciesys: syscon@1a100800 { - compatible = "mediatek,mt7629-pciesys", "syscon"; - reg = <0x1a100800 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - pcie: pcie@1a140000 { - compatible = "mediatek,mt7629-pcie"; - device_type = "pci"; - reg = <0x1a140000 0x1000>, - <0x1a145000 0x1000>; - reg-names = "subsys","port1"; - #address-cells = <3>; - #size-cells = <2>; - interrupts = , - ; - clocks = <&pciesys CLK_PCIE_P1_MAC_EN>, - <&pciesys CLK_PCIE_P0_AHB_EN>, - <&pciesys CLK_PCIE_P1_AUX_EN>, - <&pciesys CLK_PCIE_P1_AXI_EN>, - <&pciesys CLK_PCIE_P1_OBFF_EN>, - <&pciesys CLK_PCIE_P1_PIPE_EN>; - clock-names = "sys_ck1", "ahb_ck1", - "aux_ck1", "axi_ck1", - "obff_ck1", "pipe_ck1"; - assigned-clocks = <&topckgen CLK_TOP_SATA_SEL>, - <&topckgen CLK_TOP_AXI_SEL>, - <&topckgen CLK_TOP_HIF_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL2_D4>, - <&topckgen CLK_TOP_SYSPLL1_D2>, - <&topckgen CLK_TOP_UNIVPLL1_D2>; - phys = <&pcieport1 PHY_TYPE_PCIE>; - phy-names = "pcie-phy1"; - power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>; - bus-range = <0x00 0xff>; - ranges = <0x82000000 0 0x20000000 0x20000000 0 0x10000000>; - - pcie1: pcie@1,0 { - device_type = "pci"; - reg = <0x0800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges; - num-lanes = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie_intc1 0>, - <0 0 0 2 &pcie_intc1 1>, - <0 0 0 3 &pcie_intc1 2>, - <0 0 0 4 &pcie_intc1 3>; - - pcie_intc1: interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - }; - }; - }; - - pciephy1: pcie-phy@1a14a000 { - compatible = "mediatek,generic-tphy-v2"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1a14a000 0x1000>; - status = "disabled"; - - pcieport1: port1phy@0 { - reg = <0 0x1000>; - clocks = <&clk20m>; - clock-names = "ref"; - #phy-cells = <1>; - status = "okay"; - }; - }; - - ethsys: syscon@1b000000 { - compatible = "mediatek,mt7629-ethsys", "syscon"; - reg = <0x1b000000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - eth: ethernet@1b100000 { - compatible = "mediatek,mt7629-eth","syscon"; - reg = <0x1b100000 0x20000>; - interrupts = , - , - ; - clocks = <&topckgen CLK_TOP_ETH_SEL>, - <&topckgen CLK_TOP_F10M_REF_SEL>, - <ðsys CLK_ETH_ESW_EN>, - <ðsys CLK_ETH_GP0_EN>, - <ðsys CLK_ETH_GP1_EN>, - <ðsys CLK_ETH_GP2_EN>, - <ðsys CLK_ETH_FE_EN>, - <&sgmiisys0 CLK_SGMII_TX_EN>, - <&sgmiisys0 CLK_SGMII_RX_EN>, - <&sgmiisys0 CLK_SGMII_CDR_REF>, - <&sgmiisys0 CLK_SGMII_CDR_FB>, - <&sgmiisys1 CLK_SGMII_TX_EN>, - <&sgmiisys1 CLK_SGMII_RX_EN>, - <&sgmiisys1 CLK_SGMII_CDR_REF>, - <&sgmiisys1 CLK_SGMII_CDR_FB>, - <&apmixedsys CLK_APMIXED_SGMIPLL>, - <&apmixedsys CLK_APMIXED_ETH2PLL>; - clock-names = "ethif", "sgmiitop", "esw", "gp0", "gp1", - "gp2", "fe", "sgmii_tx250m", "sgmii_rx250m", - "sgmii_cdr_ref", "sgmii_cdr_fb", - "sgmii2_tx250m", "sgmii2_rx250m", - "sgmii2_cdr_ref", "sgmii2_cdr_fb", - "sgmii_ck", "eth2pll"; - assigned-clocks = <&topckgen CLK_TOP_ETH_SEL>, - <&topckgen CLK_TOP_F10M_REF_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>, - <&topckgen CLK_TOP_SGMIIPLL_D2>; - power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>; - mediatek,ethsys = <ðsys>; - mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>; - mediatek,infracfg = <&infracfg>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - sgmiisys0: syscon@1b128000 { - compatible = "mediatek,mt7629-sgmiisys", "syscon"; - reg = <0x1b128000 0x3000>; - #clock-cells = <1>; - }; - - sgmiisys1: syscon@1b130000 { - compatible = "mediatek,mt7629-sgmiisys", "syscon"; - reg = <0x1b130000 0x3000>; - #clock-cells = <1>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/mt8127-moose.dts b/sys/gnu/dts/arm/mt8127-moose.dts deleted file mode 100644 index 560687af87d..00000000000 --- a/sys/gnu/dts/arm/mt8127-moose.dts +++ /dev/null @@ -1,23 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2014 MediaTek Inc. - * Author: Joe.C - * - */ - -/dts-v1/; -#include "mt8127.dtsi" - -/ { - model = "MediaTek MT8127 Moose Board"; - compatible = "mediatek,mt8127-moose", "mediatek,mt8127"; - - memory { - device_type = "memory"; - reg = <0 0x80000000 0 0x40000000>; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/mt8127.dtsi b/sys/gnu/dts/arm/mt8127.dtsi deleted file mode 100644 index aced173c2a5..00000000000 --- a/sys/gnu/dts/arm/mt8127.dtsi +++ /dev/null @@ -1,163 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2014 MediaTek Inc. - * Author: Joe.C - * - */ - -#include -#include - -/ { - #address-cells = <2>; - #size-cells = <2>; - compatible = "mediatek,mt8127"; - interrupt-parent = <&sysirq>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "mediatek,mt81xx-tz-smp"; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x0>; - }; - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x1>; - }; - cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x2>; - }; - cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x3>; - }; - - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - trustzone-bootinfo@80002000 { - compatible = "mediatek,trustzone-bootinfo"; - reg = <0 0x80002000 0 0x1000>; - }; - }; - - clocks { - #address-cells = <2>; - #size-cells = <2>; - compatible = "simple-bus"; - ranges; - - system_clk: dummy13m { - compatible = "fixed-clock"; - clock-frequency = <13000000>; - #clock-cells = <0>; - }; - - rtc_clk: dummy32k { - compatible = "fixed-clock"; - clock-frequency = <32000>; - #clock-cells = <0>; - }; - - uart_clk: dummy26m { - compatible = "fixed-clock"; - clock-frequency = <26000000>; - #clock-cells = <0>; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupt-parent = <&gic>; - interrupts = , - , - , - ; - clock-frequency = <13000000>; - arm,cpu-registers-not-fw-configured; - }; - - soc { - #address-cells = <2>; - #size-cells = <2>; - compatible = "simple-bus"; - ranges; - - timer: timer@10008000 { - compatible = "mediatek,mt8127-timer", - "mediatek,mt6577-timer"; - reg = <0 0x10008000 0 0x80>; - interrupts = ; - clocks = <&system_clk>, <&rtc_clk>; - clock-names = "system-clk", "rtc-clk"; - }; - - sysirq: interrupt-controller@10200100 { - compatible = "mediatek,mt8127-sysirq", - "mediatek,mt6577-sysirq"; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - reg = <0 0x10200100 0 0x1c>; - }; - - gic: interrupt-controller@10211000 { - compatible = "arm,cortex-a7-gic"; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - reg = <0 0x10211000 0 0x1000>, - <0 0x10212000 0 0x2000>, - <0 0x10214000 0 0x2000>, - <0 0x10216000 0 0x2000>; - }; - - uart0: serial@11002000 { - compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart"; - reg = <0 0x11002000 0 0x400>; - interrupts = ; - clocks = <&uart_clk>; - status = "disabled"; - }; - - uart1: serial@11003000 { - compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart"; - reg = <0 0x11003000 0 0x400>; - interrupts = ; - clocks = <&uart_clk>; - status = "disabled"; - }; - - uart2: serial@11004000 { - compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart"; - reg = <0 0x11004000 0 0x400>; - interrupts = ; - clocks = <&uart_clk>; - status = "disabled"; - }; - - uart3: serial@11005000 { - compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart"; - reg = <0 0x11005000 0 0x400>; - interrupts = ; - clocks = <&uart_clk>; - status = "disabled"; - }; - }; -}; diff --git a/sys/gnu/dts/arm/mt8135-evbp1.dts b/sys/gnu/dts/arm/mt8135-evbp1.dts deleted file mode 100644 index f6147fe62f4..00000000000 --- a/sys/gnu/dts/arm/mt8135-evbp1.dts +++ /dev/null @@ -1,193 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2014 MediaTek Inc. - * Author: Joe.C - * - */ - -/dts-v1/; -#include "mt8135.dtsi" - -/ { - model = "MediaTek MT8135 evaluation board"; - compatible = "mediatek,mt8135-evbp1", "mediatek,mt8135"; - - memory { - device_type = "memory"; - reg = <0 0x80000000 0 0x40000000>; - }; -}; - -&pwrap { - pmic: mt6397 { - compatible = "mediatek,mt6397"; - - mt6397regulator: mt6397regulator { - compatible = "mediatek,mt6397-regulator"; - - mt6397_vpca15_reg: buck_vpca15 { - regulator-name = "vpca15"; - regulator-min-microvolt = < 850000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <12500>; - regulator-always-on; - }; - - mt6397_vpca7_reg: buck_vpca7 { - regulator-name = "vpca7"; - regulator-min-microvolt = < 850000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <12500>; - regulator-always-on; - }; - - mt6397_vsramca15_reg: buck_vsramca15 { - regulator-name = "vsramca15"; - regulator-min-microvolt = < 850000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <12500>; - regulator-always-on; - }; - - mt6397_vsramca7_reg: buck_vsramca7 { - regulator-name = "vsramca7"; - regulator-min-microvolt = < 850000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <12500>; - regulator-always-on; - }; - - mt6397_vcore_reg: buck_vcore { - regulator-name = "vcore"; - regulator-min-microvolt = < 850000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <12500>; - regulator-always-on; - }; - - mt6397_vgpu_reg: buck_vgpu { - regulator-name = "vgpu"; - regulator-min-microvolt = < 700000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <12500>; - regulator-enable-ramp-delay = <115>; - }; - - mt6397_vdrm_reg: buck_vdrm { - regulator-name = "vdrm"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1400000>; - regulator-ramp-delay = <12500>; - regulator-always-on; - }; - - mt6397_vio18_reg: buck_vio18 { - regulator-name = "vio18"; - regulator-min-microvolt = <1620000>; - regulator-max-microvolt = <1980000>; - regulator-ramp-delay = <12500>; - regulator-always-on; - }; - - mt6397_vtcxo_reg: ldo_vtcxo { - regulator-name = "vtcxo"; - regulator-always-on; - }; - - mt6397_va28_reg: ldo_va28 { - regulator-name = "va28"; - regulator-always-on; - }; - - mt6397_vcama_reg: ldo_vcama { - regulator-name = "vcama"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <2800000>; - regulator-enable-ramp-delay = <218>; - }; - - mt6397_vio28_reg: ldo_vio28 { - regulator-name = "vio28"; - regulator-always-on; - }; - - mt6397_vusb_reg: ldo_vusb { - regulator-name = "vusb"; - }; - - mt6397_vmc_reg: ldo_vmc { - regulator-name = "vmc"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <218>; - }; - - mt6397_vmch_reg: ldo_vmch { - regulator-name = "vmch"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <218>; - }; - - mt6397_vemc_3v3_reg: ldo_vemc3v3 { - regulator-name = "vemc_3v3"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <218>; - }; - - mt6397_vgp1_reg: ldo_vgp1 { - regulator-name = "vcamd"; - regulator-min-microvolt = <1220000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <240>; - }; - - mt6397_vgp2_reg: ldo_vgp2 { - regulator-name = "vcamio"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <218>; - }; - - mt6397_vgp3_reg: ldo_vgp3 { - regulator-name = "vcamaf"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <218>; - }; - - mt6397_vgp4_reg: ldo_vgp4 { - regulator-name = "vgp4"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <218>; - }; - - mt6397_vgp5_reg: ldo_vgp5 { - regulator-name = "vgp5"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3000000>; - regulator-enable-ramp-delay = <218>; - }; - - mt6397_vgp6_reg: ldo_vgp6 { - regulator-name = "vgp6"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <218>; - }; - - mt6397_vibr_reg: ldo_vibr { - regulator-name = "vibr"; - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <218>; - }; - }; - }; -}; - -&uart3 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/mt8135-pinfunc.h b/sys/gnu/dts/arm/mt8135-pinfunc.h deleted file mode 100644 index ce0cb5a440e..00000000000 --- a/sys/gnu/dts/arm/mt8135-pinfunc.h +++ /dev/null @@ -1,1294 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2014 MediaTek Inc. - * Author: Hongzhou.Yang - */ - -#ifndef __DTS_MT8135_PINFUNC_H -#define __DTS_MT8135_PINFUNC_H - -#include - -#define MT8135_PIN_0_MSDC0_DAT7__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) -#define MT8135_PIN_0_MSDC0_DAT7__FUNC_MSDC0_DAT7 (MTK_PIN_NO(0) | 1) -#define MT8135_PIN_0_MSDC0_DAT7__FUNC_EINT49 (MTK_PIN_NO(0) | 2) -#define MT8135_PIN_0_MSDC0_DAT7__FUNC_I2SOUT_DAT (MTK_PIN_NO(0) | 3) -#define MT8135_PIN_0_MSDC0_DAT7__FUNC_DAC_DAT_OUT (MTK_PIN_NO(0) | 4) -#define MT8135_PIN_0_MSDC0_DAT7__FUNC_PCM1_DO (MTK_PIN_NO(0) | 5) -#define MT8135_PIN_0_MSDC0_DAT7__FUNC_SPI1_MO (MTK_PIN_NO(0) | 6) -#define MT8135_PIN_0_MSDC0_DAT7__FUNC_NALE (MTK_PIN_NO(0) | 7) - -#define MT8135_PIN_1_MSDC0_DAT6__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) -#define MT8135_PIN_1_MSDC0_DAT6__FUNC_MSDC0_DAT6 (MTK_PIN_NO(1) | 1) -#define MT8135_PIN_1_MSDC0_DAT6__FUNC_EINT48 (MTK_PIN_NO(1) | 2) -#define MT8135_PIN_1_MSDC0_DAT6__FUNC_I2SIN_WS (MTK_PIN_NO(1) | 3) -#define MT8135_PIN_1_MSDC0_DAT6__FUNC_DAC_WS (MTK_PIN_NO(1) | 4) -#define MT8135_PIN_1_MSDC0_DAT6__FUNC_PCM1_WS (MTK_PIN_NO(1) | 5) -#define MT8135_PIN_1_MSDC0_DAT6__FUNC_SPI1_CSN (MTK_PIN_NO(1) | 6) -#define MT8135_PIN_1_MSDC0_DAT6__FUNC_NCLE (MTK_PIN_NO(1) | 7) - -#define MT8135_PIN_2_MSDC0_DAT5__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) -#define MT8135_PIN_2_MSDC0_DAT5__FUNC_MSDC0_DAT5 (MTK_PIN_NO(2) | 1) -#define MT8135_PIN_2_MSDC0_DAT5__FUNC_EINT47 (MTK_PIN_NO(2) | 2) -#define MT8135_PIN_2_MSDC0_DAT5__FUNC_I2SIN_CK (MTK_PIN_NO(2) | 3) -#define MT8135_PIN_2_MSDC0_DAT5__FUNC_DAC_CK (MTK_PIN_NO(2) | 4) -#define MT8135_PIN_2_MSDC0_DAT5__FUNC_PCM1_CK (MTK_PIN_NO(2) | 5) -#define MT8135_PIN_2_MSDC0_DAT5__FUNC_SPI1_CLK (MTK_PIN_NO(2) | 6) -#define MT8135_PIN_2_MSDC0_DAT5__FUNC_NLD4 (MTK_PIN_NO(2) | 7) - -#define MT8135_PIN_3_MSDC0_DAT4__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) -#define MT8135_PIN_3_MSDC0_DAT4__FUNC_MSDC0_DAT4 (MTK_PIN_NO(3) | 1) -#define MT8135_PIN_3_MSDC0_DAT4__FUNC_EINT46 (MTK_PIN_NO(3) | 2) -#define MT8135_PIN_3_MSDC0_DAT4__FUNC_A_FUNC_CK (MTK_PIN_NO(3) | 3) -#define MT8135_PIN_3_MSDC0_DAT4__FUNC_LSCE1B_2X (MTK_PIN_NO(3) | 6) -#define MT8135_PIN_3_MSDC0_DAT4__FUNC_NLD5 (MTK_PIN_NO(3) | 7) - -#define MT8135_PIN_4_MSDC0_CMD__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) -#define MT8135_PIN_4_MSDC0_CMD__FUNC_MSDC0_CMD (MTK_PIN_NO(4) | 1) -#define MT8135_PIN_4_MSDC0_CMD__FUNC_EINT41 (MTK_PIN_NO(4) | 2) -#define MT8135_PIN_4_MSDC0_CMD__FUNC_A_FUNC_DOUT_0 (MTK_PIN_NO(4) | 3) -#define MT8135_PIN_4_MSDC0_CMD__FUNC_USB_TEST_IO_0 (MTK_PIN_NO(4) | 5) -#define MT8135_PIN_4_MSDC0_CMD__FUNC_LRSTB_2X (MTK_PIN_NO(4) | 6) -#define MT8135_PIN_4_MSDC0_CMD__FUNC_NRNB (MTK_PIN_NO(4) | 7) - -#define MT8135_PIN_5_MSDC0_CLK__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) -#define MT8135_PIN_5_MSDC0_CLK__FUNC_MSDC0_CLK (MTK_PIN_NO(5) | 1) -#define MT8135_PIN_5_MSDC0_CLK__FUNC_EINT40 (MTK_PIN_NO(5) | 2) -#define MT8135_PIN_5_MSDC0_CLK__FUNC_A_FUNC_DOUT_1 (MTK_PIN_NO(5) | 3) -#define MT8135_PIN_5_MSDC0_CLK__FUNC_USB_TEST_IO_1 (MTK_PIN_NO(5) | 5) -#define MT8135_PIN_5_MSDC0_CLK__FUNC_LPTE (MTK_PIN_NO(5) | 6) -#define MT8135_PIN_5_MSDC0_CLK__FUNC_NREB (MTK_PIN_NO(5) | 7) - -#define MT8135_PIN_6_MSDC0_DAT3__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) -#define MT8135_PIN_6_MSDC0_DAT3__FUNC_MSDC0_DAT3 (MTK_PIN_NO(6) | 1) -#define MT8135_PIN_6_MSDC0_DAT3__FUNC_EINT45 (MTK_PIN_NO(6) | 2) -#define MT8135_PIN_6_MSDC0_DAT3__FUNC_A_FUNC_DOUT_2 (MTK_PIN_NO(6) | 3) -#define MT8135_PIN_6_MSDC0_DAT3__FUNC_USB_TEST_IO_2 (MTK_PIN_NO(6) | 5) -#define MT8135_PIN_6_MSDC0_DAT3__FUNC_LSCE0B_2X (MTK_PIN_NO(6) | 6) -#define MT8135_PIN_6_MSDC0_DAT3__FUNC_NLD7 (MTK_PIN_NO(6) | 7) - -#define MT8135_PIN_7_MSDC0_DAT2__FUNC_GPIO7 (MTK_PIN_NO(7) | 0) -#define MT8135_PIN_7_MSDC0_DAT2__FUNC_MSDC0_DAT2 (MTK_PIN_NO(7) | 1) -#define MT8135_PIN_7_MSDC0_DAT2__FUNC_EINT44 (MTK_PIN_NO(7) | 2) -#define MT8135_PIN_7_MSDC0_DAT2__FUNC_A_FUNC_DOUT_3 (MTK_PIN_NO(7) | 3) -#define MT8135_PIN_7_MSDC0_DAT2__FUNC_USB_TEST_IO_3 (MTK_PIN_NO(7) | 5) -#define MT8135_PIN_7_MSDC0_DAT2__FUNC_LSA0_2X (MTK_PIN_NO(7) | 6) -#define MT8135_PIN_7_MSDC0_DAT2__FUNC_NLD14 (MTK_PIN_NO(7) | 7) - -#define MT8135_PIN_8_MSDC0_DAT1__FUNC_GPIO8 (MTK_PIN_NO(8) | 0) -#define MT8135_PIN_8_MSDC0_DAT1__FUNC_MSDC0_DAT1 (MTK_PIN_NO(8) | 1) -#define MT8135_PIN_8_MSDC0_DAT1__FUNC_EINT43 (MTK_PIN_NO(8) | 2) -#define MT8135_PIN_8_MSDC0_DAT1__FUNC_USB_TEST_IO_4 (MTK_PIN_NO(8) | 5) -#define MT8135_PIN_8_MSDC0_DAT1__FUNC_LSCK_2X (MTK_PIN_NO(8) | 6) -#define MT8135_PIN_8_MSDC0_DAT1__FUNC_NLD11 (MTK_PIN_NO(8) | 7) - -#define MT8135_PIN_9_MSDC0_DAT0__FUNC_GPIO9 (MTK_PIN_NO(9) | 0) -#define MT8135_PIN_9_MSDC0_DAT0__FUNC_MSDC0_DAT0 (MTK_PIN_NO(9) | 1) -#define MT8135_PIN_9_MSDC0_DAT0__FUNC_EINT42 (MTK_PIN_NO(9) | 2) -#define MT8135_PIN_9_MSDC0_DAT0__FUNC_USB_TEST_IO_5 (MTK_PIN_NO(9) | 5) -#define MT8135_PIN_9_MSDC0_DAT0__FUNC_LSDA_2X (MTK_PIN_NO(9) | 6) - -#define MT8135_PIN_10_NCEB0__FUNC_GPIO10 (MTK_PIN_NO(10) | 0) -#define MT8135_PIN_10_NCEB0__FUNC_NCEB0 (MTK_PIN_NO(10) | 1) -#define MT8135_PIN_10_NCEB0__FUNC_EINT139 (MTK_PIN_NO(10) | 2) -#define MT8135_PIN_10_NCEB0__FUNC_TESTA_OUT4 (MTK_PIN_NO(10) | 7) - -#define MT8135_PIN_11_NCEB1__FUNC_GPIO11 (MTK_PIN_NO(11) | 0) -#define MT8135_PIN_11_NCEB1__FUNC_NCEB1 (MTK_PIN_NO(11) | 1) -#define MT8135_PIN_11_NCEB1__FUNC_EINT140 (MTK_PIN_NO(11) | 2) -#define MT8135_PIN_11_NCEB1__FUNC_USB_DRVVBUS (MTK_PIN_NO(11) | 6) -#define MT8135_PIN_11_NCEB1__FUNC_TESTA_OUT5 (MTK_PIN_NO(11) | 7) - -#define MT8135_PIN_12_NRNB__FUNC_GPIO12 (MTK_PIN_NO(12) | 0) -#define MT8135_PIN_12_NRNB__FUNC_NRNB (MTK_PIN_NO(12) | 1) -#define MT8135_PIN_12_NRNB__FUNC_EINT141 (MTK_PIN_NO(12) | 2) -#define MT8135_PIN_12_NRNB__FUNC_A_FUNC_DOUT_4 (MTK_PIN_NO(12) | 3) -#define MT8135_PIN_12_NRNB__FUNC_TESTA_OUT6 (MTK_PIN_NO(12) | 7) - -#define MT8135_PIN_13_NCLE__FUNC_GPIO13 (MTK_PIN_NO(13) | 0) -#define MT8135_PIN_13_NCLE__FUNC_NCLE (MTK_PIN_NO(13) | 1) -#define MT8135_PIN_13_NCLE__FUNC_EINT142 (MTK_PIN_NO(13) | 2) -#define MT8135_PIN_13_NCLE__FUNC_A_FUNC_DOUT_5 (MTK_PIN_NO(13) | 3) -#define MT8135_PIN_13_NCLE__FUNC_CM2PDN_1X (MTK_PIN_NO(13) | 4) -#define MT8135_PIN_13_NCLE__FUNC_NALE (MTK_PIN_NO(13) | 6) -#define MT8135_PIN_13_NCLE__FUNC_TESTA_OUT7 (MTK_PIN_NO(13) | 7) - -#define MT8135_PIN_14_NALE__FUNC_GPIO14 (MTK_PIN_NO(14) | 0) -#define MT8135_PIN_14_NALE__FUNC_NALE (MTK_PIN_NO(14) | 1) -#define MT8135_PIN_14_NALE__FUNC_EINT143 (MTK_PIN_NO(14) | 2) -#define MT8135_PIN_14_NALE__FUNC_A_FUNC_DOUT_6 (MTK_PIN_NO(14) | 3) -#define MT8135_PIN_14_NALE__FUNC_CM2MCLK_1X (MTK_PIN_NO(14) | 4) -#define MT8135_PIN_14_NALE__FUNC_IRDA_RXD (MTK_PIN_NO(14) | 5) -#define MT8135_PIN_14_NALE__FUNC_NCLE (MTK_PIN_NO(14) | 6) -#define MT8135_PIN_14_NALE__FUNC_TESTA_OUT8 (MTK_PIN_NO(14) | 7) - -#define MT8135_PIN_15_NREB__FUNC_GPIO15 (MTK_PIN_NO(15) | 0) -#define MT8135_PIN_15_NREB__FUNC_NREB (MTK_PIN_NO(15) | 1) -#define MT8135_PIN_15_NREB__FUNC_EINT144 (MTK_PIN_NO(15) | 2) -#define MT8135_PIN_15_NREB__FUNC_A_FUNC_DOUT_7 (MTK_PIN_NO(15) | 3) -#define MT8135_PIN_15_NREB__FUNC_CM2RST_1X (MTK_PIN_NO(15) | 4) -#define MT8135_PIN_15_NREB__FUNC_IRDA_TXD (MTK_PIN_NO(15) | 5) -#define MT8135_PIN_15_NREB__FUNC_TESTA_OUT9 (MTK_PIN_NO(15) | 7) - -#define MT8135_PIN_16_NWEB__FUNC_GPIO16 (MTK_PIN_NO(16) | 0) -#define MT8135_PIN_16_NWEB__FUNC_NWEB (MTK_PIN_NO(16) | 1) -#define MT8135_PIN_16_NWEB__FUNC_EINT145 (MTK_PIN_NO(16) | 2) -#define MT8135_PIN_16_NWEB__FUNC_A_FUNC_DIN_0 (MTK_PIN_NO(16) | 3) -#define MT8135_PIN_16_NWEB__FUNC_CM2PCLK_1X (MTK_PIN_NO(16) | 4) -#define MT8135_PIN_16_NWEB__FUNC_IRDA_PDN (MTK_PIN_NO(16) | 5) -#define MT8135_PIN_16_NWEB__FUNC_TESTA_OUT10 (MTK_PIN_NO(16) | 7) - -#define MT8135_PIN_17_NLD0__FUNC_GPIO17 (MTK_PIN_NO(17) | 0) -#define MT8135_PIN_17_NLD0__FUNC_NLD0 (MTK_PIN_NO(17) | 1) -#define MT8135_PIN_17_NLD0__FUNC_EINT146 (MTK_PIN_NO(17) | 2) -#define MT8135_PIN_17_NLD0__FUNC_A_FUNC_DIN_1 (MTK_PIN_NO(17) | 3) -#define MT8135_PIN_17_NLD0__FUNC_CM2DAT_1X_0 (MTK_PIN_NO(17) | 4) -#define MT8135_PIN_17_NLD0__FUNC_I2SIN_CK (MTK_PIN_NO(17) | 5) -#define MT8135_PIN_17_NLD0__FUNC_DAC_CK (MTK_PIN_NO(17) | 6) -#define MT8135_PIN_17_NLD0__FUNC_TESTA_OUT11 (MTK_PIN_NO(17) | 7) - -#define MT8135_PIN_18_NLD1__FUNC_GPIO18 (MTK_PIN_NO(18) | 0) -#define MT8135_PIN_18_NLD1__FUNC_NLD1 (MTK_PIN_NO(18) | 1) -#define MT8135_PIN_18_NLD1__FUNC_EINT147 (MTK_PIN_NO(18) | 2) -#define MT8135_PIN_18_NLD1__FUNC_A_FUNC_DIN_2 (MTK_PIN_NO(18) | 3) -#define MT8135_PIN_18_NLD1__FUNC_CM2DAT_1X_1 (MTK_PIN_NO(18) | 4) -#define MT8135_PIN_18_NLD1__FUNC_I2SIN_WS (MTK_PIN_NO(18) | 5) -#define MT8135_PIN_18_NLD1__FUNC_DAC_WS (MTK_PIN_NO(18) | 6) -#define MT8135_PIN_18_NLD1__FUNC_TESTA_OUT12 (MTK_PIN_NO(18) | 7) - -#define MT8135_PIN_19_NLD2__FUNC_GPIO19 (MTK_PIN_NO(19) | 0) -#define MT8135_PIN_19_NLD2__FUNC_NLD2 (MTK_PIN_NO(19) | 1) -#define MT8135_PIN_19_NLD2__FUNC_EINT148 (MTK_PIN_NO(19) | 2) -#define MT8135_PIN_19_NLD2__FUNC_A_FUNC_DIN_3 (MTK_PIN_NO(19) | 3) -#define MT8135_PIN_19_NLD2__FUNC_CM2DAT_1X_2 (MTK_PIN_NO(19) | 4) -#define MT8135_PIN_19_NLD2__FUNC_I2SOUT_DAT (MTK_PIN_NO(19) | 5) -#define MT8135_PIN_19_NLD2__FUNC_DAC_DAT_OUT (MTK_PIN_NO(19) | 6) -#define MT8135_PIN_19_NLD2__FUNC_TESTA_OUT13 (MTK_PIN_NO(19) | 7) - -#define MT8135_PIN_20_NLD3__FUNC_GPIO20 (MTK_PIN_NO(20) | 0) -#define MT8135_PIN_20_NLD3__FUNC_NLD3 (MTK_PIN_NO(20) | 1) -#define MT8135_PIN_20_NLD3__FUNC_EINT149 (MTK_PIN_NO(20) | 2) -#define MT8135_PIN_20_NLD3__FUNC_A_FUNC_DIN_4 (MTK_PIN_NO(20) | 3) -#define MT8135_PIN_20_NLD3__FUNC_CM2DAT_1X_3 (MTK_PIN_NO(20) | 4) -#define MT8135_PIN_20_NLD3__FUNC_TESTA_OUT14 (MTK_PIN_NO(20) | 7) - -#define MT8135_PIN_21_NLD4__FUNC_GPIO21 (MTK_PIN_NO(21) | 0) -#define MT8135_PIN_21_NLD4__FUNC_NLD4 (MTK_PIN_NO(21) | 1) -#define MT8135_PIN_21_NLD4__FUNC_EINT150 (MTK_PIN_NO(21) | 2) -#define MT8135_PIN_21_NLD4__FUNC_A_FUNC_DIN_5 (MTK_PIN_NO(21) | 3) -#define MT8135_PIN_21_NLD4__FUNC_CM2DAT_1X_4 (MTK_PIN_NO(21) | 4) -#define MT8135_PIN_21_NLD4__FUNC_TESTA_OUT15 (MTK_PIN_NO(21) | 7) - -#define MT8135_PIN_22_NLD5__FUNC_GPIO22 (MTK_PIN_NO(22) | 0) -#define MT8135_PIN_22_NLD5__FUNC_NLD5 (MTK_PIN_NO(22) | 1) -#define MT8135_PIN_22_NLD5__FUNC_EINT151 (MTK_PIN_NO(22) | 2) -#define MT8135_PIN_22_NLD5__FUNC_A_FUNC_DIN_6 (MTK_PIN_NO(22) | 3) -#define MT8135_PIN_22_NLD5__FUNC_CM2DAT_1X_5 (MTK_PIN_NO(22) | 4) -#define MT8135_PIN_22_NLD5__FUNC_TESTA_OUT16 (MTK_PIN_NO(22) | 7) - -#define MT8135_PIN_23_NLD6__FUNC_GPIO23 (MTK_PIN_NO(23) | 0) -#define MT8135_PIN_23_NLD6__FUNC_NLD6 (MTK_PIN_NO(23) | 1) -#define MT8135_PIN_23_NLD6__FUNC_EINT152 (MTK_PIN_NO(23) | 2) -#define MT8135_PIN_23_NLD6__FUNC_A_FUNC_DIN_7 (MTK_PIN_NO(23) | 3) -#define MT8135_PIN_23_NLD6__FUNC_CM2DAT_1X_6 (MTK_PIN_NO(23) | 4) -#define MT8135_PIN_23_NLD6__FUNC_TESTA_OUT17 (MTK_PIN_NO(23) | 7) - -#define MT8135_PIN_24_NLD7__FUNC_GPIO24 (MTK_PIN_NO(24) | 0) -#define MT8135_PIN_24_NLD7__FUNC_NLD7 (MTK_PIN_NO(24) | 1) -#define MT8135_PIN_24_NLD7__FUNC_EINT153 (MTK_PIN_NO(24) | 2) -#define MT8135_PIN_24_NLD7__FUNC_A_FUNC_DIN_8 (MTK_PIN_NO(24) | 3) -#define MT8135_PIN_24_NLD7__FUNC_CM2DAT_1X_7 (MTK_PIN_NO(24) | 4) -#define MT8135_PIN_24_NLD7__FUNC_TESTA_OUT18 (MTK_PIN_NO(24) | 7) - -#define MT8135_PIN_25_NLD8__FUNC_GPIO25 (MTK_PIN_NO(25) | 0) -#define MT8135_PIN_25_NLD8__FUNC_NLD8 (MTK_PIN_NO(25) | 1) -#define MT8135_PIN_25_NLD8__FUNC_EINT154 (MTK_PIN_NO(25) | 2) -#define MT8135_PIN_25_NLD8__FUNC_CM2DAT_1X_8 (MTK_PIN_NO(25) | 4) - -#define MT8135_PIN_26_NLD9__FUNC_GPIO26 (MTK_PIN_NO(26) | 0) -#define MT8135_PIN_26_NLD9__FUNC_NLD9 (MTK_PIN_NO(26) | 1) -#define MT8135_PIN_26_NLD9__FUNC_EINT155 (MTK_PIN_NO(26) | 2) -#define MT8135_PIN_26_NLD9__FUNC_CM2DAT_1X_9 (MTK_PIN_NO(26) | 4) -#define MT8135_PIN_26_NLD9__FUNC_PWM1 (MTK_PIN_NO(26) | 5) - -#define MT8135_PIN_27_NLD10__FUNC_GPIO27 (MTK_PIN_NO(27) | 0) -#define MT8135_PIN_27_NLD10__FUNC_NLD10 (MTK_PIN_NO(27) | 1) -#define MT8135_PIN_27_NLD10__FUNC_EINT156 (MTK_PIN_NO(27) | 2) -#define MT8135_PIN_27_NLD10__FUNC_CM2VSYNC_1X (MTK_PIN_NO(27) | 4) -#define MT8135_PIN_27_NLD10__FUNC_PWM2 (MTK_PIN_NO(27) | 5) - -#define MT8135_PIN_28_NLD11__FUNC_GPIO28 (MTK_PIN_NO(28) | 0) -#define MT8135_PIN_28_NLD11__FUNC_NLD11 (MTK_PIN_NO(28) | 1) -#define MT8135_PIN_28_NLD11__FUNC_EINT157 (MTK_PIN_NO(28) | 2) -#define MT8135_PIN_28_NLD11__FUNC_CM2HSYNC_1X (MTK_PIN_NO(28) | 4) -#define MT8135_PIN_28_NLD11__FUNC_PWM3 (MTK_PIN_NO(28) | 5) - -#define MT8135_PIN_29_NLD12__FUNC_GPIO29 (MTK_PIN_NO(29) | 0) -#define MT8135_PIN_29_NLD12__FUNC_NLD12 (MTK_PIN_NO(29) | 1) -#define MT8135_PIN_29_NLD12__FUNC_EINT158 (MTK_PIN_NO(29) | 2) -#define MT8135_PIN_29_NLD12__FUNC_I2SIN_CK (MTK_PIN_NO(29) | 3) -#define MT8135_PIN_29_NLD12__FUNC_DAC_CK (MTK_PIN_NO(29) | 4) -#define MT8135_PIN_29_NLD12__FUNC_PCM1_CK (MTK_PIN_NO(29) | 5) - -#define MT8135_PIN_30_NLD13__FUNC_GPIO30 (MTK_PIN_NO(30) | 0) -#define MT8135_PIN_30_NLD13__FUNC_NLD13 (MTK_PIN_NO(30) | 1) -#define MT8135_PIN_30_NLD13__FUNC_EINT159 (MTK_PIN_NO(30) | 2) -#define MT8135_PIN_30_NLD13__FUNC_I2SIN_WS (MTK_PIN_NO(30) | 3) -#define MT8135_PIN_30_NLD13__FUNC_DAC_WS (MTK_PIN_NO(30) | 4) -#define MT8135_PIN_30_NLD13__FUNC_PCM1_WS (MTK_PIN_NO(30) | 5) - -#define MT8135_PIN_31_NLD14__FUNC_GPIO31 (MTK_PIN_NO(31) | 0) -#define MT8135_PIN_31_NLD14__FUNC_NLD14 (MTK_PIN_NO(31) | 1) -#define MT8135_PIN_31_NLD14__FUNC_EINT160 (MTK_PIN_NO(31) | 2) -#define MT8135_PIN_31_NLD14__FUNC_I2SOUT_DAT (MTK_PIN_NO(31) | 3) -#define MT8135_PIN_31_NLD14__FUNC_DAC_DAT_OUT (MTK_PIN_NO(31) | 4) -#define MT8135_PIN_31_NLD14__FUNC_PCM1_DO (MTK_PIN_NO(31) | 5) - -#define MT8135_PIN_32_NLD15__FUNC_GPIO32 (MTK_PIN_NO(32) | 0) -#define MT8135_PIN_32_NLD15__FUNC_NLD15 (MTK_PIN_NO(32) | 1) -#define MT8135_PIN_32_NLD15__FUNC_EINT161 (MTK_PIN_NO(32) | 2) -#define MT8135_PIN_32_NLD15__FUNC_DISP_PWM (MTK_PIN_NO(32) | 3) -#define MT8135_PIN_32_NLD15__FUNC_PWM4 (MTK_PIN_NO(32) | 4) -#define MT8135_PIN_32_NLD15__FUNC_PCM1_DI (MTK_PIN_NO(32) | 5) - -#define MT8135_PIN_33_MSDC0_RSTB__FUNC_GPIO33 (MTK_PIN_NO(33) | 0) -#define MT8135_PIN_33_MSDC0_RSTB__FUNC_MSDC0_RSTB (MTK_PIN_NO(33) | 1) -#define MT8135_PIN_33_MSDC0_RSTB__FUNC_EINT50 (MTK_PIN_NO(33) | 2) -#define MT8135_PIN_33_MSDC0_RSTB__FUNC_I2SIN_DAT (MTK_PIN_NO(33) | 3) -#define MT8135_PIN_33_MSDC0_RSTB__FUNC_PCM1_DI (MTK_PIN_NO(33) | 5) -#define MT8135_PIN_33_MSDC0_RSTB__FUNC_SPI1_MI (MTK_PIN_NO(33) | 6) -#define MT8135_PIN_33_MSDC0_RSTB__FUNC_NLD10 (MTK_PIN_NO(33) | 7) - -#define MT8135_PIN_34_IDDIG__FUNC_GPIO34 (MTK_PIN_NO(34) | 0) -#define MT8135_PIN_34_IDDIG__FUNC_IDDIG (MTK_PIN_NO(34) | 1) -#define MT8135_PIN_34_IDDIG__FUNC_EINT34 (MTK_PIN_NO(34) | 2) - -#define MT8135_PIN_35_SCL3__FUNC_GPIO35 (MTK_PIN_NO(35) | 0) -#define MT8135_PIN_35_SCL3__FUNC_SCL3 (MTK_PIN_NO(35) | 1) -#define MT8135_PIN_35_SCL3__FUNC_EINT96 (MTK_PIN_NO(35) | 2) -#define MT8135_PIN_35_SCL3__FUNC_CLKM6 (MTK_PIN_NO(35) | 3) -#define MT8135_PIN_35_SCL3__FUNC_PWM6 (MTK_PIN_NO(35) | 4) - -#define MT8135_PIN_36_SDA3__FUNC_GPIO36 (MTK_PIN_NO(36) | 0) -#define MT8135_PIN_36_SDA3__FUNC_SDA3 (MTK_PIN_NO(36) | 1) -#define MT8135_PIN_36_SDA3__FUNC_EINT97 (MTK_PIN_NO(36) | 2) - -#define MT8135_PIN_37_AUD_CLK_MOSI__FUNC_GPIO37 (MTK_PIN_NO(37) | 0) -#define MT8135_PIN_37_AUD_CLK_MOSI__FUNC_AUD_CLK (MTK_PIN_NO(37) | 1) -#define MT8135_PIN_37_AUD_CLK_MOSI__FUNC_ADC_CK (MTK_PIN_NO(37) | 2) -#define MT8135_PIN_37_AUD_CLK_MOSI__FUNC_HDMI_SDATA0 (MTK_PIN_NO(37) | 3) -#define MT8135_PIN_37_AUD_CLK_MOSI__FUNC_EINT19 (MTK_PIN_NO(37) | 4) -#define MT8135_PIN_37_AUD_CLK_MOSI__FUNC_USB_TEST_IO_6 (MTK_PIN_NO(37) | 5) -#define MT8135_PIN_37_AUD_CLK_MOSI__FUNC_TESTA_OUT19 (MTK_PIN_NO(37) | 7) - -#define MT8135_PIN_38_AUD_DAT_MOSI__FUNC_GPIO38 (MTK_PIN_NO(38) | 0) -#define MT8135_PIN_38_AUD_DAT_MOSI__FUNC_AUD_DAT_MOSI (MTK_PIN_NO(38) | 1) -#define MT8135_PIN_38_AUD_DAT_MOSI__FUNC_ADC_WS (MTK_PIN_NO(38) | 2) -#define MT8135_PIN_38_AUD_DAT_MOSI__FUNC_AUD_DAT_MISO (MTK_PIN_NO(38) | 3) -#define MT8135_PIN_38_AUD_DAT_MOSI__FUNC_EINT21 (MTK_PIN_NO(38) | 4) -#define MT8135_PIN_38_AUD_DAT_MOSI__FUNC_USB_TEST_IO_7 (MTK_PIN_NO(38) | 5) -#define MT8135_PIN_38_AUD_DAT_MOSI__FUNC_TESTA_OUT20 (MTK_PIN_NO(38) | 7) - -#define MT8135_PIN_39_AUD_DAT_MISO__FUNC_GPIO39 (MTK_PIN_NO(39) | 0) -#define MT8135_PIN_39_AUD_DAT_MISO__FUNC_AUD_DAT_MISO (MTK_PIN_NO(39) | 1) -#define MT8135_PIN_39_AUD_DAT_MISO__FUNC_ADC_DAT_IN (MTK_PIN_NO(39) | 2) -#define MT8135_PIN_39_AUD_DAT_MISO__FUNC_AUD_DAT_MOSI (MTK_PIN_NO(39) | 3) -#define MT8135_PIN_39_AUD_DAT_MISO__FUNC_EINT20 (MTK_PIN_NO(39) | 4) -#define MT8135_PIN_39_AUD_DAT_MISO__FUNC_USB_TEST_IO_8 (MTK_PIN_NO(39) | 5) -#define MT8135_PIN_39_AUD_DAT_MISO__FUNC_TESTA_OUT21 (MTK_PIN_NO(39) | 7) - -#define MT8135_PIN_40_DAC_CLK__FUNC_GPIO40 (MTK_PIN_NO(40) | 0) -#define MT8135_PIN_40_DAC_CLK__FUNC_DAC_CK (MTK_PIN_NO(40) | 1) -#define MT8135_PIN_40_DAC_CLK__FUNC_EINT22 (MTK_PIN_NO(40) | 2) -#define MT8135_PIN_40_DAC_CLK__FUNC_HDMI_SDATA1 (MTK_PIN_NO(40) | 3) -#define MT8135_PIN_40_DAC_CLK__FUNC_USB_TEST_IO_9 (MTK_PIN_NO(40) | 5) -#define MT8135_PIN_40_DAC_CLK__FUNC_TESTA_OUT22 (MTK_PIN_NO(40) | 7) - -#define MT8135_PIN_41_DAC_WS__FUNC_GPIO41 (MTK_PIN_NO(41) | 0) -#define MT8135_PIN_41_DAC_WS__FUNC_DAC_WS (MTK_PIN_NO(41) | 1) -#define MT8135_PIN_41_DAC_WS__FUNC_EINT24 (MTK_PIN_NO(41) | 2) -#define MT8135_PIN_41_DAC_WS__FUNC_HDMI_SDATA2 (MTK_PIN_NO(41) | 3) -#define MT8135_PIN_41_DAC_WS__FUNC_USB_TEST_IO_10 (MTK_PIN_NO(41) | 5) -#define MT8135_PIN_41_DAC_WS__FUNC_TESTA_OUT23 (MTK_PIN_NO(41) | 7) - -#define MT8135_PIN_42_DAC_DAT_OUT__FUNC_GPIO42 (MTK_PIN_NO(42) | 0) -#define MT8135_PIN_42_DAC_DAT_OUT__FUNC_DAC_DAT_OUT (MTK_PIN_NO(42) | 1) -#define MT8135_PIN_42_DAC_DAT_OUT__FUNC_EINT23 (MTK_PIN_NO(42) | 2) -#define MT8135_PIN_42_DAC_DAT_OUT__FUNC_HDMI_SDATA3 (MTK_PIN_NO(42) | 3) -#define MT8135_PIN_42_DAC_DAT_OUT__FUNC_USB_TEST_IO_11 (MTK_PIN_NO(42) | 5) -#define MT8135_PIN_42_DAC_DAT_OUT__FUNC_TESTA_OUT24 (MTK_PIN_NO(42) | 7) - -#define MT8135_PIN_43_PWRAP_SPI0_MO__FUNC_GPIO43 (MTK_PIN_NO(43) | 0) -#define MT8135_PIN_43_PWRAP_SPI0_MO__FUNC_PWRAP_SPIDI (MTK_PIN_NO(43) | 1) -#define MT8135_PIN_43_PWRAP_SPI0_MO__FUNC_EINT29 (MTK_PIN_NO(43) | 2) - -#define MT8135_PIN_44_PWRAP_SPI0_MI__FUNC_GPIO44 (MTK_PIN_NO(44) | 0) -#define MT8135_PIN_44_PWRAP_SPI0_MI__FUNC_PWRAP_SPIDO (MTK_PIN_NO(44) | 1) -#define MT8135_PIN_44_PWRAP_SPI0_MI__FUNC_EINT28 (MTK_PIN_NO(44) | 2) - -#define MT8135_PIN_45_PWRAP_SPI0_CSN__FUNC_GPIO45 (MTK_PIN_NO(45) | 0) -#define MT8135_PIN_45_PWRAP_SPI0_CSN__FUNC_PWRAP_SPICS_B_I (MTK_PIN_NO(45) | 1) -#define MT8135_PIN_45_PWRAP_SPI0_CSN__FUNC_EINT27 (MTK_PIN_NO(45) | 2) - -#define MT8135_PIN_46_PWRAP_SPI0_CLK__FUNC_GPIO46 (MTK_PIN_NO(46) | 0) -#define MT8135_PIN_46_PWRAP_SPI0_CLK__FUNC_PWRAP_SPICK_I (MTK_PIN_NO(46) | 1) -#define MT8135_PIN_46_PWRAP_SPI0_CLK__FUNC_EINT26 (MTK_PIN_NO(46) | 2) - -#define MT8135_PIN_47_PWRAP_EVENT__FUNC_GPIO47 (MTK_PIN_NO(47) | 0) -#define MT8135_PIN_47_PWRAP_EVENT__FUNC_PWRAP_EVENT_IN (MTK_PIN_NO(47) | 1) -#define MT8135_PIN_47_PWRAP_EVENT__FUNC_EINT25 (MTK_PIN_NO(47) | 2) -#define MT8135_PIN_47_PWRAP_EVENT__FUNC_TESTA_OUT2 (MTK_PIN_NO(47) | 7) - -#define MT8135_PIN_48_RTC32K_CK__FUNC_GPIO48 (MTK_PIN_NO(48) | 0) -#define MT8135_PIN_48_RTC32K_CK__FUNC_RTC32K_CK (MTK_PIN_NO(48) | 1) - -#define MT8135_PIN_49_WATCHDOG__FUNC_GPIO49 (MTK_PIN_NO(49) | 0) -#define MT8135_PIN_49_WATCHDOG__FUNC_WATCHDOG (MTK_PIN_NO(49) | 1) -#define MT8135_PIN_49_WATCHDOG__FUNC_EINT36 (MTK_PIN_NO(49) | 2) - -#define MT8135_PIN_50_SRCLKENA__FUNC_GPIO50 (MTK_PIN_NO(50) | 0) -#define MT8135_PIN_50_SRCLKENA__FUNC_SRCLKENA (MTK_PIN_NO(50) | 1) -#define MT8135_PIN_50_SRCLKENA__FUNC_EINT38 (MTK_PIN_NO(50) | 2) - -#define MT8135_PIN_51_SRCVOLTEN__FUNC_GPIO51 (MTK_PIN_NO(51) | 0) -#define MT8135_PIN_51_SRCVOLTEN__FUNC_SRCVOLTEN (MTK_PIN_NO(51) | 1) -#define MT8135_PIN_51_SRCVOLTEN__FUNC_EINT37 (MTK_PIN_NO(51) | 2) - -#define MT8135_PIN_52_EINT0__FUNC_GPIO52 (MTK_PIN_NO(52) | 0) -#define MT8135_PIN_52_EINT0__FUNC_EINT0 (MTK_PIN_NO(52) | 1) -#define MT8135_PIN_52_EINT0__FUNC_PWM1 (MTK_PIN_NO(52) | 2) -#define MT8135_PIN_52_EINT0__FUNC_CLKM0 (MTK_PIN_NO(52) | 3) -#define MT8135_PIN_52_EINT0__FUNC_SPDIF_OUT (MTK_PIN_NO(52) | 4) -#define MT8135_PIN_52_EINT0__FUNC_USB_TEST_IO_12 (MTK_PIN_NO(52) | 5) -#define MT8135_PIN_52_EINT0__FUNC_USB_SCL (MTK_PIN_NO(52) | 7) - -#define MT8135_PIN_53_URXD2__FUNC_GPIO53 (MTK_PIN_NO(53) | 0) -#define MT8135_PIN_53_URXD2__FUNC_URXD2 (MTK_PIN_NO(53) | 1) -#define MT8135_PIN_53_URXD2__FUNC_EINT83 (MTK_PIN_NO(53) | 2) -#define MT8135_PIN_53_URXD2__FUNC_HDMI_LRCK (MTK_PIN_NO(53) | 4) -#define MT8135_PIN_53_URXD2__FUNC_CLKM3 (MTK_PIN_NO(53) | 5) -#define MT8135_PIN_53_URXD2__FUNC_UTXD2 (MTK_PIN_NO(53) | 7) - -#define MT8135_PIN_54_UTXD2__FUNC_GPIO54 (MTK_PIN_NO(54) | 0) -#define MT8135_PIN_54_UTXD2__FUNC_UTXD2 (MTK_PIN_NO(54) | 1) -#define MT8135_PIN_54_UTXD2__FUNC_EINT82 (MTK_PIN_NO(54) | 2) -#define MT8135_PIN_54_UTXD2__FUNC_HDMI_BCK_OUT (MTK_PIN_NO(54) | 4) -#define MT8135_PIN_54_UTXD2__FUNC_CLKM2 (MTK_PIN_NO(54) | 5) -#define MT8135_PIN_54_UTXD2__FUNC_URXD2 (MTK_PIN_NO(54) | 7) - -#define MT8135_PIN_55_UCTS2__FUNC_GPIO55 (MTK_PIN_NO(55) | 0) -#define MT8135_PIN_55_UCTS2__FUNC_UCTS2 (MTK_PIN_NO(55) | 1) -#define MT8135_PIN_55_UCTS2__FUNC_EINT84 (MTK_PIN_NO(55) | 2) -#define MT8135_PIN_55_UCTS2__FUNC_PWM1 (MTK_PIN_NO(55) | 5) -#define MT8135_PIN_55_UCTS2__FUNC_URTS2 (MTK_PIN_NO(55) | 7) - -#define MT8135_PIN_56_URTS2__FUNC_GPIO56 (MTK_PIN_NO(56) | 0) -#define MT8135_PIN_56_URTS2__FUNC_URTS2 (MTK_PIN_NO(56) | 1) -#define MT8135_PIN_56_URTS2__FUNC_EINT85 (MTK_PIN_NO(56) | 2) -#define MT8135_PIN_56_URTS2__FUNC_PWM2 (MTK_PIN_NO(56) | 5) -#define MT8135_PIN_56_URTS2__FUNC_UCTS2 (MTK_PIN_NO(56) | 7) - -#define MT8135_PIN_57_JTCK__FUNC_GPIO57 (MTK_PIN_NO(57) | 0) -#define MT8135_PIN_57_JTCK__FUNC_JTCK (MTK_PIN_NO(57) | 1) -#define MT8135_PIN_57_JTCK__FUNC_EINT188 (MTK_PIN_NO(57) | 2) -#define MT8135_PIN_57_JTCK__FUNC_DSP1_ICK (MTK_PIN_NO(57) | 3) - -#define MT8135_PIN_58_JTDO__FUNC_GPIO58 (MTK_PIN_NO(58) | 0) -#define MT8135_PIN_58_JTDO__FUNC_JTDO (MTK_PIN_NO(58) | 1) -#define MT8135_PIN_58_JTDO__FUNC_EINT190 (MTK_PIN_NO(58) | 2) -#define MT8135_PIN_58_JTDO__FUNC_DSP2_IMS (MTK_PIN_NO(58) | 3) - -#define MT8135_PIN_59_JTRST_B__FUNC_GPIO59 (MTK_PIN_NO(59) | 0) -#define MT8135_PIN_59_JTRST_B__FUNC_JTRST_B (MTK_PIN_NO(59) | 1) -#define MT8135_PIN_59_JTRST_B__FUNC_EINT0 (MTK_PIN_NO(59) | 2) -#define MT8135_PIN_59_JTRST_B__FUNC_DSP2_ICK (MTK_PIN_NO(59) | 3) - -#define MT8135_PIN_60_JTDI__FUNC_GPIO60 (MTK_PIN_NO(60) | 0) -#define MT8135_PIN_60_JTDI__FUNC_JTDI (MTK_PIN_NO(60) | 1) -#define MT8135_PIN_60_JTDI__FUNC_EINT189 (MTK_PIN_NO(60) | 2) -#define MT8135_PIN_60_JTDI__FUNC_DSP1_IMS (MTK_PIN_NO(60) | 3) - -#define MT8135_PIN_61_JRTCK__FUNC_GPIO61 (MTK_PIN_NO(61) | 0) -#define MT8135_PIN_61_JRTCK__FUNC_JRTCK (MTK_PIN_NO(61) | 1) -#define MT8135_PIN_61_JRTCK__FUNC_EINT187 (MTK_PIN_NO(61) | 2) -#define MT8135_PIN_61_JRTCK__FUNC_DSP1_ID (MTK_PIN_NO(61) | 3) - -#define MT8135_PIN_62_JTMS__FUNC_GPIO62 (MTK_PIN_NO(62) | 0) -#define MT8135_PIN_62_JTMS__FUNC_JTMS (MTK_PIN_NO(62) | 1) -#define MT8135_PIN_62_JTMS__FUNC_EINT191 (MTK_PIN_NO(62) | 2) -#define MT8135_PIN_62_JTMS__FUNC_DSP2_ID (MTK_PIN_NO(62) | 3) - -#define MT8135_PIN_63_MSDC1_INSI__FUNC_GPIO63 (MTK_PIN_NO(63) | 0) -#define MT8135_PIN_63_MSDC1_INSI__FUNC_MSDC1_INSI (MTK_PIN_NO(63) | 1) -#define MT8135_PIN_63_MSDC1_INSI__FUNC_SCL5 (MTK_PIN_NO(63) | 3) -#define MT8135_PIN_63_MSDC1_INSI__FUNC_PWM6 (MTK_PIN_NO(63) | 4) -#define MT8135_PIN_63_MSDC1_INSI__FUNC_CLKM5 (MTK_PIN_NO(63) | 5) -#define MT8135_PIN_63_MSDC1_INSI__FUNC_TESTB_OUT6 (MTK_PIN_NO(63) | 7) - -#define MT8135_PIN_64_MSDC1_SDWPI__FUNC_GPIO64 (MTK_PIN_NO(64) | 0) -#define MT8135_PIN_64_MSDC1_SDWPI__FUNC_MSDC1_SDWPI (MTK_PIN_NO(64) | 1) -#define MT8135_PIN_64_MSDC1_SDWPI__FUNC_EINT58 (MTK_PIN_NO(64) | 2) -#define MT8135_PIN_64_MSDC1_SDWPI__FUNC_SDA5 (MTK_PIN_NO(64) | 3) -#define MT8135_PIN_64_MSDC1_SDWPI__FUNC_PWM7 (MTK_PIN_NO(64) | 4) -#define MT8135_PIN_64_MSDC1_SDWPI__FUNC_CLKM6 (MTK_PIN_NO(64) | 5) -#define MT8135_PIN_64_MSDC1_SDWPI__FUNC_TESTB_OUT7 (MTK_PIN_NO(64) | 7) - -#define MT8135_PIN_65_MSDC2_INSI__FUNC_GPIO65 (MTK_PIN_NO(65) | 0) -#define MT8135_PIN_65_MSDC2_INSI__FUNC_MSDC2_INSI (MTK_PIN_NO(65) | 1) -#define MT8135_PIN_65_MSDC2_INSI__FUNC_USB_TEST_IO_27 (MTK_PIN_NO(65) | 5) -#define MT8135_PIN_65_MSDC2_INSI__FUNC_TESTA_OUT3 (MTK_PIN_NO(65) | 7) - -#define MT8135_PIN_66_MSDC2_SDWPI__FUNC_GPIO66 (MTK_PIN_NO(66) | 0) -#define MT8135_PIN_66_MSDC2_SDWPI__FUNC_MSDC2_SDWPI (MTK_PIN_NO(66) | 1) -#define MT8135_PIN_66_MSDC2_SDWPI__FUNC_EINT66 (MTK_PIN_NO(66) | 2) -#define MT8135_PIN_66_MSDC2_SDWPI__FUNC_USB_TEST_IO_28 (MTK_PIN_NO(66) | 5) - -#define MT8135_PIN_67_URXD4__FUNC_GPIO67 (MTK_PIN_NO(67) | 0) -#define MT8135_PIN_67_URXD4__FUNC_URXD4 (MTK_PIN_NO(67) | 1) -#define MT8135_PIN_67_URXD4__FUNC_EINT89 (MTK_PIN_NO(67) | 2) -#define MT8135_PIN_67_URXD4__FUNC_URXD1 (MTK_PIN_NO(67) | 3) -#define MT8135_PIN_67_URXD4__FUNC_UTXD4 (MTK_PIN_NO(67) | 6) -#define MT8135_PIN_67_URXD4__FUNC_TESTB_OUT10 (MTK_PIN_NO(67) | 7) - -#define MT8135_PIN_68_UTXD4__FUNC_GPIO68 (MTK_PIN_NO(68) | 0) -#define MT8135_PIN_68_UTXD4__FUNC_UTXD4 (MTK_PIN_NO(68) | 1) -#define MT8135_PIN_68_UTXD4__FUNC_EINT88 (MTK_PIN_NO(68) | 2) -#define MT8135_PIN_68_UTXD4__FUNC_UTXD1 (MTK_PIN_NO(68) | 3) -#define MT8135_PIN_68_UTXD4__FUNC_URXD4 (MTK_PIN_NO(68) | 6) -#define MT8135_PIN_68_UTXD4__FUNC_TESTB_OUT11 (MTK_PIN_NO(68) | 7) - -#define MT8135_PIN_69_URXD1__FUNC_GPIO69 (MTK_PIN_NO(69) | 0) -#define MT8135_PIN_69_URXD1__FUNC_URXD1 (MTK_PIN_NO(69) | 1) -#define MT8135_PIN_69_URXD1__FUNC_EINT79 (MTK_PIN_NO(69) | 2) -#define MT8135_PIN_69_URXD1__FUNC_URXD4 (MTK_PIN_NO(69) | 3) -#define MT8135_PIN_69_URXD1__FUNC_UTXD1 (MTK_PIN_NO(69) | 6) -#define MT8135_PIN_69_URXD1__FUNC_TESTB_OUT24 (MTK_PIN_NO(69) | 7) - -#define MT8135_PIN_70_UTXD1__FUNC_GPIO70 (MTK_PIN_NO(70) | 0) -#define MT8135_PIN_70_UTXD1__FUNC_UTXD1 (MTK_PIN_NO(70) | 1) -#define MT8135_PIN_70_UTXD1__FUNC_EINT78 (MTK_PIN_NO(70) | 2) -#define MT8135_PIN_70_UTXD1__FUNC_UTXD4 (MTK_PIN_NO(70) | 3) -#define MT8135_PIN_70_UTXD1__FUNC_URXD1 (MTK_PIN_NO(70) | 6) -#define MT8135_PIN_70_UTXD1__FUNC_TESTB_OUT25 (MTK_PIN_NO(70) | 7) - -#define MT8135_PIN_71_UCTS1__FUNC_GPIO71 (MTK_PIN_NO(71) | 0) -#define MT8135_PIN_71_UCTS1__FUNC_UCTS1 (MTK_PIN_NO(71) | 1) -#define MT8135_PIN_71_UCTS1__FUNC_EINT80 (MTK_PIN_NO(71) | 2) -#define MT8135_PIN_71_UCTS1__FUNC_CLKM0 (MTK_PIN_NO(71) | 5) -#define MT8135_PIN_71_UCTS1__FUNC_URTS1 (MTK_PIN_NO(71) | 6) -#define MT8135_PIN_71_UCTS1__FUNC_TESTB_OUT31 (MTK_PIN_NO(71) | 7) - -#define MT8135_PIN_72_URTS1__FUNC_GPIO72 (MTK_PIN_NO(72) | 0) -#define MT8135_PIN_72_URTS1__FUNC_URTS1 (MTK_PIN_NO(72) | 1) -#define MT8135_PIN_72_URTS1__FUNC_EINT81 (MTK_PIN_NO(72) | 2) -#define MT8135_PIN_72_URTS1__FUNC_CLKM1 (MTK_PIN_NO(72) | 5) -#define MT8135_PIN_72_URTS1__FUNC_UCTS1 (MTK_PIN_NO(72) | 6) -#define MT8135_PIN_72_URTS1__FUNC_TESTB_OUT21 (MTK_PIN_NO(72) | 7) - -#define MT8135_PIN_73_PWM1__FUNC_GPIO73 (MTK_PIN_NO(73) | 0) -#define MT8135_PIN_73_PWM1__FUNC_PWM1 (MTK_PIN_NO(73) | 1) -#define MT8135_PIN_73_PWM1__FUNC_EINT73 (MTK_PIN_NO(73) | 2) -#define MT8135_PIN_73_PWM1__FUNC_USB_DRVVBUS (MTK_PIN_NO(73) | 5) -#define MT8135_PIN_73_PWM1__FUNC_DISP_PWM (MTK_PIN_NO(73) | 6) -#define MT8135_PIN_73_PWM1__FUNC_TESTB_OUT8 (MTK_PIN_NO(73) | 7) - -#define MT8135_PIN_74_PWM2__FUNC_GPIO74 (MTK_PIN_NO(74) | 0) -#define MT8135_PIN_74_PWM2__FUNC_PWM2 (MTK_PIN_NO(74) | 1) -#define MT8135_PIN_74_PWM2__FUNC_EINT74 (MTK_PIN_NO(74) | 2) -#define MT8135_PIN_74_PWM2__FUNC_DPI33_CK (MTK_PIN_NO(74) | 3) -#define MT8135_PIN_74_PWM2__FUNC_PWM5 (MTK_PIN_NO(74) | 4) -#define MT8135_PIN_74_PWM2__FUNC_URXD2 (MTK_PIN_NO(74) | 5) -#define MT8135_PIN_74_PWM2__FUNC_DISP_PWM (MTK_PIN_NO(74) | 6) -#define MT8135_PIN_74_PWM2__FUNC_TESTB_OUT9 (MTK_PIN_NO(74) | 7) - -#define MT8135_PIN_75_PWM3__FUNC_GPIO75 (MTK_PIN_NO(75) | 0) -#define MT8135_PIN_75_PWM3__FUNC_PWM3 (MTK_PIN_NO(75) | 1) -#define MT8135_PIN_75_PWM3__FUNC_EINT75 (MTK_PIN_NO(75) | 2) -#define MT8135_PIN_75_PWM3__FUNC_DPI33_D0 (MTK_PIN_NO(75) | 3) -#define MT8135_PIN_75_PWM3__FUNC_PWM6 (MTK_PIN_NO(75) | 4) -#define MT8135_PIN_75_PWM3__FUNC_UTXD2 (MTK_PIN_NO(75) | 5) -#define MT8135_PIN_75_PWM3__FUNC_DISP_PWM (MTK_PIN_NO(75) | 6) -#define MT8135_PIN_75_PWM3__FUNC_TESTB_OUT12 (MTK_PIN_NO(75) | 7) - -#define MT8135_PIN_76_PWM4__FUNC_GPIO76 (MTK_PIN_NO(76) | 0) -#define MT8135_PIN_76_PWM4__FUNC_PWM4 (MTK_PIN_NO(76) | 1) -#define MT8135_PIN_76_PWM4__FUNC_EINT76 (MTK_PIN_NO(76) | 2) -#define MT8135_PIN_76_PWM4__FUNC_DPI33_D1 (MTK_PIN_NO(76) | 3) -#define MT8135_PIN_76_PWM4__FUNC_PWM7 (MTK_PIN_NO(76) | 4) -#define MT8135_PIN_76_PWM4__FUNC_DISP_PWM (MTK_PIN_NO(76) | 6) -#define MT8135_PIN_76_PWM4__FUNC_TESTB_OUT13 (MTK_PIN_NO(76) | 7) - -#define MT8135_PIN_77_MSDC2_DAT2__FUNC_GPIO77 (MTK_PIN_NO(77) | 0) -#define MT8135_PIN_77_MSDC2_DAT2__FUNC_MSDC2_DAT2 (MTK_PIN_NO(77) | 1) -#define MT8135_PIN_77_MSDC2_DAT2__FUNC_EINT63 (MTK_PIN_NO(77) | 2) -#define MT8135_PIN_77_MSDC2_DAT2__FUNC_DSP2_IMS (MTK_PIN_NO(77) | 4) -#define MT8135_PIN_77_MSDC2_DAT2__FUNC_DPI33_D6 (MTK_PIN_NO(77) | 6) -#define MT8135_PIN_77_MSDC2_DAT2__FUNC_TESTA_OUT25 (MTK_PIN_NO(77) | 7) - -#define MT8135_PIN_78_MSDC2_DAT3__FUNC_GPIO78 (MTK_PIN_NO(78) | 0) -#define MT8135_PIN_78_MSDC2_DAT3__FUNC_MSDC2_DAT3 (MTK_PIN_NO(78) | 1) -#define MT8135_PIN_78_MSDC2_DAT3__FUNC_EINT64 (MTK_PIN_NO(78) | 2) -#define MT8135_PIN_78_MSDC2_DAT3__FUNC_DSP2_ID (MTK_PIN_NO(78) | 4) -#define MT8135_PIN_78_MSDC2_DAT3__FUNC_DPI33_D7 (MTK_PIN_NO(78) | 6) -#define MT8135_PIN_78_MSDC2_DAT3__FUNC_TESTA_OUT26 (MTK_PIN_NO(78) | 7) - -#define MT8135_PIN_79_MSDC2_CMD__FUNC_GPIO79 (MTK_PIN_NO(79) | 0) -#define MT8135_PIN_79_MSDC2_CMD__FUNC_MSDC2_CMD (MTK_PIN_NO(79) | 1) -#define MT8135_PIN_79_MSDC2_CMD__FUNC_EINT60 (MTK_PIN_NO(79) | 2) -#define MT8135_PIN_79_MSDC2_CMD__FUNC_DSP1_IMS (MTK_PIN_NO(79) | 4) -#define MT8135_PIN_79_MSDC2_CMD__FUNC_PCM1_WS (MTK_PIN_NO(79) | 5) -#define MT8135_PIN_79_MSDC2_CMD__FUNC_DPI33_D3 (MTK_PIN_NO(79) | 6) -#define MT8135_PIN_79_MSDC2_CMD__FUNC_TESTA_OUT0 (MTK_PIN_NO(79) | 7) - -#define MT8135_PIN_80_MSDC2_CLK__FUNC_GPIO80 (MTK_PIN_NO(80) | 0) -#define MT8135_PIN_80_MSDC2_CLK__FUNC_MSDC2_CLK (MTK_PIN_NO(80) | 1) -#define MT8135_PIN_80_MSDC2_CLK__FUNC_EINT59 (MTK_PIN_NO(80) | 2) -#define MT8135_PIN_80_MSDC2_CLK__FUNC_DSP1_ICK (MTK_PIN_NO(80) | 4) -#define MT8135_PIN_80_MSDC2_CLK__FUNC_PCM1_CK (MTK_PIN_NO(80) | 5) -#define MT8135_PIN_80_MSDC2_CLK__FUNC_DPI33_D2 (MTK_PIN_NO(80) | 6) -#define MT8135_PIN_80_MSDC2_CLK__FUNC_TESTA_OUT1 (MTK_PIN_NO(80) | 7) - -#define MT8135_PIN_81_MSDC2_DAT1__FUNC_GPIO81 (MTK_PIN_NO(81) | 0) -#define MT8135_PIN_81_MSDC2_DAT1__FUNC_MSDC2_DAT1 (MTK_PIN_NO(81) | 1) -#define MT8135_PIN_81_MSDC2_DAT1__FUNC_EINT62 (MTK_PIN_NO(81) | 2) -#define MT8135_PIN_81_MSDC2_DAT1__FUNC_DSP2_ICK (MTK_PIN_NO(81) | 4) -#define MT8135_PIN_81_MSDC2_DAT1__FUNC_PCM1_DO (MTK_PIN_NO(81) | 5) -#define MT8135_PIN_81_MSDC2_DAT1__FUNC_DPI33_D5 (MTK_PIN_NO(81) | 6) - -#define MT8135_PIN_82_MSDC2_DAT0__FUNC_GPIO82 (MTK_PIN_NO(82) | 0) -#define MT8135_PIN_82_MSDC2_DAT0__FUNC_MSDC2_DAT0 (MTK_PIN_NO(82) | 1) -#define MT8135_PIN_82_MSDC2_DAT0__FUNC_EINT61 (MTK_PIN_NO(82) | 2) -#define MT8135_PIN_82_MSDC2_DAT0__FUNC_DSP1_ID (MTK_PIN_NO(82) | 4) -#define MT8135_PIN_82_MSDC2_DAT0__FUNC_PCM1_DI (MTK_PIN_NO(82) | 5) -#define MT8135_PIN_82_MSDC2_DAT0__FUNC_DPI33_D4 (MTK_PIN_NO(82) | 6) - -#define MT8135_PIN_83_MSDC1_DAT0__FUNC_GPIO83 (MTK_PIN_NO(83) | 0) -#define MT8135_PIN_83_MSDC1_DAT0__FUNC_MSDC1_DAT0 (MTK_PIN_NO(83) | 1) -#define MT8135_PIN_83_MSDC1_DAT0__FUNC_EINT53 (MTK_PIN_NO(83) | 2) -#define MT8135_PIN_83_MSDC1_DAT0__FUNC_SCL1 (MTK_PIN_NO(83) | 3) -#define MT8135_PIN_83_MSDC1_DAT0__FUNC_PWM2 (MTK_PIN_NO(83) | 4) -#define MT8135_PIN_83_MSDC1_DAT0__FUNC_CLKM1 (MTK_PIN_NO(83) | 5) -#define MT8135_PIN_83_MSDC1_DAT0__FUNC_TESTB_OUT2 (MTK_PIN_NO(83) | 7) - -#define MT8135_PIN_84_MSDC1_DAT1__FUNC_GPIO84 (MTK_PIN_NO(84) | 0) -#define MT8135_PIN_84_MSDC1_DAT1__FUNC_MSDC1_DAT1 (MTK_PIN_NO(84) | 1) -#define MT8135_PIN_84_MSDC1_DAT1__FUNC_EINT54 (MTK_PIN_NO(84) | 2) -#define MT8135_PIN_84_MSDC1_DAT1__FUNC_SDA1 (MTK_PIN_NO(84) | 3) -#define MT8135_PIN_84_MSDC1_DAT1__FUNC_PWM3 (MTK_PIN_NO(84) | 4) -#define MT8135_PIN_84_MSDC1_DAT1__FUNC_CLKM2 (MTK_PIN_NO(84) | 5) -#define MT8135_PIN_84_MSDC1_DAT1__FUNC_TESTB_OUT3 (MTK_PIN_NO(84) | 7) - -#define MT8135_PIN_85_MSDC1_CMD__FUNC_GPIO85 (MTK_PIN_NO(85) | 0) -#define MT8135_PIN_85_MSDC1_CMD__FUNC_MSDC1_CMD (MTK_PIN_NO(85) | 1) -#define MT8135_PIN_85_MSDC1_CMD__FUNC_EINT52 (MTK_PIN_NO(85) | 2) -#define MT8135_PIN_85_MSDC1_CMD__FUNC_SDA0 (MTK_PIN_NO(85) | 3) -#define MT8135_PIN_85_MSDC1_CMD__FUNC_PWM1 (MTK_PIN_NO(85) | 4) -#define MT8135_PIN_85_MSDC1_CMD__FUNC_CLKM0 (MTK_PIN_NO(85) | 5) -#define MT8135_PIN_85_MSDC1_CMD__FUNC_TESTB_OUT1 (MTK_PIN_NO(85) | 7) - -#define MT8135_PIN_86_MSDC1_CLK__FUNC_GPIO86 (MTK_PIN_NO(86) | 0) -#define MT8135_PIN_86_MSDC1_CLK__FUNC_MSDC1_CLK (MTK_PIN_NO(86) | 1) -#define MT8135_PIN_86_MSDC1_CLK__FUNC_EINT51 (MTK_PIN_NO(86) | 2) -#define MT8135_PIN_86_MSDC1_CLK__FUNC_SCL0 (MTK_PIN_NO(86) | 3) -#define MT8135_PIN_86_MSDC1_CLK__FUNC_DISP_PWM (MTK_PIN_NO(86) | 4) -#define MT8135_PIN_86_MSDC1_CLK__FUNC_TESTB_OUT0 (MTK_PIN_NO(86) | 7) - -#define MT8135_PIN_87_MSDC1_DAT2__FUNC_GPIO87 (MTK_PIN_NO(87) | 0) -#define MT8135_PIN_87_MSDC1_DAT2__FUNC_MSDC1_DAT2 (MTK_PIN_NO(87) | 1) -#define MT8135_PIN_87_MSDC1_DAT2__FUNC_EINT55 (MTK_PIN_NO(87) | 2) -#define MT8135_PIN_87_MSDC1_DAT2__FUNC_SCL4 (MTK_PIN_NO(87) | 3) -#define MT8135_PIN_87_MSDC1_DAT2__FUNC_PWM4 (MTK_PIN_NO(87) | 4) -#define MT8135_PIN_87_MSDC1_DAT2__FUNC_CLKM3 (MTK_PIN_NO(87) | 5) -#define MT8135_PIN_87_MSDC1_DAT2__FUNC_TESTB_OUT4 (MTK_PIN_NO(87) | 7) - -#define MT8135_PIN_88_MSDC1_DAT3__FUNC_GPIO88 (MTK_PIN_NO(88) | 0) -#define MT8135_PIN_88_MSDC1_DAT3__FUNC_MSDC1_DAT3 (MTK_PIN_NO(88) | 1) -#define MT8135_PIN_88_MSDC1_DAT3__FUNC_EINT56 (MTK_PIN_NO(88) | 2) -#define MT8135_PIN_88_MSDC1_DAT3__FUNC_SDA4 (MTK_PIN_NO(88) | 3) -#define MT8135_PIN_88_MSDC1_DAT3__FUNC_PWM5 (MTK_PIN_NO(88) | 4) -#define MT8135_PIN_88_MSDC1_DAT3__FUNC_CLKM4 (MTK_PIN_NO(88) | 5) -#define MT8135_PIN_88_MSDC1_DAT3__FUNC_TESTB_OUT5 (MTK_PIN_NO(88) | 7) - -#define MT8135_PIN_89_MSDC4_DAT0__FUNC_GPIO89 (MTK_PIN_NO(89) | 0) -#define MT8135_PIN_89_MSDC4_DAT0__FUNC_MSDC4_DAT0 (MTK_PIN_NO(89) | 1) -#define MT8135_PIN_89_MSDC4_DAT0__FUNC_EINT133 (MTK_PIN_NO(89) | 2) -#define MT8135_PIN_89_MSDC4_DAT0__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(89) | 4) -#define MT8135_PIN_89_MSDC4_DAT0__FUNC_USB_DRVVBUS (MTK_PIN_NO(89) | 5) -#define MT8135_PIN_89_MSDC4_DAT0__FUNC_A_FUNC_DIN_9 (MTK_PIN_NO(89) | 6) -#define MT8135_PIN_89_MSDC4_DAT0__FUNC_LPTE (MTK_PIN_NO(89) | 7) - -#define MT8135_PIN_90_MSDC4_DAT1__FUNC_GPIO90 (MTK_PIN_NO(90) | 0) -#define MT8135_PIN_90_MSDC4_DAT1__FUNC_MSDC4_DAT1 (MTK_PIN_NO(90) | 1) -#define MT8135_PIN_90_MSDC4_DAT1__FUNC_EINT134 (MTK_PIN_NO(90) | 2) -#define MT8135_PIN_90_MSDC4_DAT1__FUNC_A_FUNC_DIN_10 (MTK_PIN_NO(90) | 6) -#define MT8135_PIN_90_MSDC4_DAT1__FUNC_LRSTB_1X (MTK_PIN_NO(90) | 7) - -#define MT8135_PIN_91_MSDC4_DAT5__FUNC_GPIO91 (MTK_PIN_NO(91) | 0) -#define MT8135_PIN_91_MSDC4_DAT5__FUNC_MSDC4_DAT5 (MTK_PIN_NO(91) | 1) -#define MT8135_PIN_91_MSDC4_DAT5__FUNC_EINT136 (MTK_PIN_NO(91) | 2) -#define MT8135_PIN_91_MSDC4_DAT5__FUNC_I2SIN_WS (MTK_PIN_NO(91) | 3) -#define MT8135_PIN_91_MSDC4_DAT5__FUNC_DAC_WS (MTK_PIN_NO(91) | 4) -#define MT8135_PIN_91_MSDC4_DAT5__FUNC_PCM1_WS (MTK_PIN_NO(91) | 5) -#define MT8135_PIN_91_MSDC4_DAT5__FUNC_A_FUNC_DIN_11 (MTK_PIN_NO(91) | 6) -#define MT8135_PIN_91_MSDC4_DAT5__FUNC_SPI1_CSN (MTK_PIN_NO(91) | 7) - -#define MT8135_PIN_92_MSDC4_DAT6__FUNC_GPIO92 (MTK_PIN_NO(92) | 0) -#define MT8135_PIN_92_MSDC4_DAT6__FUNC_MSDC4_DAT6 (MTK_PIN_NO(92) | 1) -#define MT8135_PIN_92_MSDC4_DAT6__FUNC_EINT137 (MTK_PIN_NO(92) | 2) -#define MT8135_PIN_92_MSDC4_DAT6__FUNC_I2SOUT_DAT (MTK_PIN_NO(92) | 3) -#define MT8135_PIN_92_MSDC4_DAT6__FUNC_DAC_DAT_OUT (MTK_PIN_NO(92) | 4) -#define MT8135_PIN_92_MSDC4_DAT6__FUNC_PCM1_DO (MTK_PIN_NO(92) | 5) -#define MT8135_PIN_92_MSDC4_DAT6__FUNC_A_FUNC_DIN_12 (MTK_PIN_NO(92) | 6) -#define MT8135_PIN_92_MSDC4_DAT6__FUNC_SPI1_MO (MTK_PIN_NO(92) | 7) - -#define MT8135_PIN_93_MSDC4_DAT7__FUNC_GPIO93 (MTK_PIN_NO(93) | 0) -#define MT8135_PIN_93_MSDC4_DAT7__FUNC_MSDC4_DAT7 (MTK_PIN_NO(93) | 1) -#define MT8135_PIN_93_MSDC4_DAT7__FUNC_EINT138 (MTK_PIN_NO(93) | 2) -#define MT8135_PIN_93_MSDC4_DAT7__FUNC_I2SIN_DAT (MTK_PIN_NO(93) | 3) -#define MT8135_PIN_93_MSDC4_DAT7__FUNC_PCM1_DI (MTK_PIN_NO(93) | 5) -#define MT8135_PIN_93_MSDC4_DAT7__FUNC_A_FUNC_DIN_13 (MTK_PIN_NO(93) | 6) -#define MT8135_PIN_93_MSDC4_DAT7__FUNC_SPI1_MI (MTK_PIN_NO(93) | 7) - -#define MT8135_PIN_94_MSDC4_DAT4__FUNC_GPIO94 (MTK_PIN_NO(94) | 0) -#define MT8135_PIN_94_MSDC4_DAT4__FUNC_MSDC4_DAT4 (MTK_PIN_NO(94) | 1) -#define MT8135_PIN_94_MSDC4_DAT4__FUNC_EINT135 (MTK_PIN_NO(94) | 2) -#define MT8135_PIN_94_MSDC4_DAT4__FUNC_I2SIN_CK (MTK_PIN_NO(94) | 3) -#define MT8135_PIN_94_MSDC4_DAT4__FUNC_DAC_CK (MTK_PIN_NO(94) | 4) -#define MT8135_PIN_94_MSDC4_DAT4__FUNC_PCM1_CK (MTK_PIN_NO(94) | 5) -#define MT8135_PIN_94_MSDC4_DAT4__FUNC_A_FUNC_DIN_14 (MTK_PIN_NO(94) | 6) -#define MT8135_PIN_94_MSDC4_DAT4__FUNC_SPI1_CLK (MTK_PIN_NO(94) | 7) - -#define MT8135_PIN_95_MSDC4_DAT2__FUNC_GPIO95 (MTK_PIN_NO(95) | 0) -#define MT8135_PIN_95_MSDC4_DAT2__FUNC_MSDC4_DAT2 (MTK_PIN_NO(95) | 1) -#define MT8135_PIN_95_MSDC4_DAT2__FUNC_EINT131 (MTK_PIN_NO(95) | 2) -#define MT8135_PIN_95_MSDC4_DAT2__FUNC_I2SIN_WS (MTK_PIN_NO(95) | 3) -#define MT8135_PIN_95_MSDC4_DAT2__FUNC_CM2PDN_2X (MTK_PIN_NO(95) | 4) -#define MT8135_PIN_95_MSDC4_DAT2__FUNC_DAC_WS (MTK_PIN_NO(95) | 5) -#define MT8135_PIN_95_MSDC4_DAT2__FUNC_PCM1_WS (MTK_PIN_NO(95) | 6) -#define MT8135_PIN_95_MSDC4_DAT2__FUNC_LSCE0B_1X (MTK_PIN_NO(95) | 7) - -#define MT8135_PIN_96_MSDC4_CLK__FUNC_GPIO96 (MTK_PIN_NO(96) | 0) -#define MT8135_PIN_96_MSDC4_CLK__FUNC_MSDC4_CLK (MTK_PIN_NO(96) | 1) -#define MT8135_PIN_96_MSDC4_CLK__FUNC_EINT129 (MTK_PIN_NO(96) | 2) -#define MT8135_PIN_96_MSDC4_CLK__FUNC_DPI1_CK_2X (MTK_PIN_NO(96) | 3) -#define MT8135_PIN_96_MSDC4_CLK__FUNC_CM2PCLK_2X (MTK_PIN_NO(96) | 4) -#define MT8135_PIN_96_MSDC4_CLK__FUNC_PWM4 (MTK_PIN_NO(96) | 5) -#define MT8135_PIN_96_MSDC4_CLK__FUNC_PCM1_DI (MTK_PIN_NO(96) | 6) -#define MT8135_PIN_96_MSDC4_CLK__FUNC_LSCK_1X (MTK_PIN_NO(96) | 7) - -#define MT8135_PIN_97_MSDC4_DAT3__FUNC_GPIO97 (MTK_PIN_NO(97) | 0) -#define MT8135_PIN_97_MSDC4_DAT3__FUNC_MSDC4_DAT3 (MTK_PIN_NO(97) | 1) -#define MT8135_PIN_97_MSDC4_DAT3__FUNC_EINT132 (MTK_PIN_NO(97) | 2) -#define MT8135_PIN_97_MSDC4_DAT3__FUNC_I2SOUT_DAT (MTK_PIN_NO(97) | 3) -#define MT8135_PIN_97_MSDC4_DAT3__FUNC_CM2RST_2X (MTK_PIN_NO(97) | 4) -#define MT8135_PIN_97_MSDC4_DAT3__FUNC_DAC_DAT_OUT (MTK_PIN_NO(97) | 5) -#define MT8135_PIN_97_MSDC4_DAT3__FUNC_PCM1_DO (MTK_PIN_NO(97) | 6) -#define MT8135_PIN_97_MSDC4_DAT3__FUNC_LSCE1B_1X (MTK_PIN_NO(97) | 7) - -#define MT8135_PIN_98_MSDC4_CMD__FUNC_GPIO98 (MTK_PIN_NO(98) | 0) -#define MT8135_PIN_98_MSDC4_CMD__FUNC_MSDC4_CMD (MTK_PIN_NO(98) | 1) -#define MT8135_PIN_98_MSDC4_CMD__FUNC_EINT128 (MTK_PIN_NO(98) | 2) -#define MT8135_PIN_98_MSDC4_CMD__FUNC_DPI1_DE_2X (MTK_PIN_NO(98) | 3) -#define MT8135_PIN_98_MSDC4_CMD__FUNC_PWM3 (MTK_PIN_NO(98) | 5) -#define MT8135_PIN_98_MSDC4_CMD__FUNC_LSDA_1X (MTK_PIN_NO(98) | 7) - -#define MT8135_PIN_99_MSDC4_RSTB__FUNC_GPIO99 (MTK_PIN_NO(99) | 0) -#define MT8135_PIN_99_MSDC4_RSTB__FUNC_MSDC4_RSTB (MTK_PIN_NO(99) | 1) -#define MT8135_PIN_99_MSDC4_RSTB__FUNC_EINT130 (MTK_PIN_NO(99) | 2) -#define MT8135_PIN_99_MSDC4_RSTB__FUNC_I2SIN_CK (MTK_PIN_NO(99) | 3) -#define MT8135_PIN_99_MSDC4_RSTB__FUNC_CM2MCLK_2X (MTK_PIN_NO(99) | 4) -#define MT8135_PIN_99_MSDC4_RSTB__FUNC_DAC_CK (MTK_PIN_NO(99) | 5) -#define MT8135_PIN_99_MSDC4_RSTB__FUNC_PCM1_CK (MTK_PIN_NO(99) | 6) -#define MT8135_PIN_99_MSDC4_RSTB__FUNC_LSA0_1X (MTK_PIN_NO(99) | 7) - -#define MT8135_PIN_100_SDA0__FUNC_GPIO100 (MTK_PIN_NO(100) | 0) -#define MT8135_PIN_100_SDA0__FUNC_SDA0 (MTK_PIN_NO(100) | 1) -#define MT8135_PIN_100_SDA0__FUNC_EINT91 (MTK_PIN_NO(100) | 2) -#define MT8135_PIN_100_SDA0__FUNC_CLKM1 (MTK_PIN_NO(100) | 3) -#define MT8135_PIN_100_SDA0__FUNC_PWM1 (MTK_PIN_NO(100) | 4) -#define MT8135_PIN_100_SDA0__FUNC_A_FUNC_DIN_15 (MTK_PIN_NO(100) | 7) - -#define MT8135_PIN_101_SCL0__FUNC_GPIO101 (MTK_PIN_NO(101) | 0) -#define MT8135_PIN_101_SCL0__FUNC_SCL0 (MTK_PIN_NO(101) | 1) -#define MT8135_PIN_101_SCL0__FUNC_EINT90 (MTK_PIN_NO(101) | 2) -#define MT8135_PIN_101_SCL0__FUNC_CLKM0 (MTK_PIN_NO(101) | 3) -#define MT8135_PIN_101_SCL0__FUNC_DISP_PWM (MTK_PIN_NO(101) | 4) -#define MT8135_PIN_101_SCL0__FUNC_A_FUNC_DIN_16 (MTK_PIN_NO(101) | 7) - -#define MT8135_PIN_102_EINT10_AUXIN2__FUNC_GPIO102 (MTK_PIN_NO(102) | 0) -#define MT8135_PIN_102_EINT10_AUXIN2__FUNC_EINT10 (MTK_PIN_NO(102) | 1) -#define MT8135_PIN_102_EINT10_AUXIN2__FUNC_USB_TEST_IO_16 (MTK_PIN_NO(102) | 5) -#define MT8135_PIN_102_EINT10_AUXIN2__FUNC_TESTB_OUT16 (MTK_PIN_NO(102) | 6) -#define MT8135_PIN_102_EINT10_AUXIN2__FUNC_A_FUNC_DIN_17 (MTK_PIN_NO(102) | 7) - -#define MT8135_PIN_103_EINT11_AUXIN3__FUNC_GPIO103 (MTK_PIN_NO(103) | 0) -#define MT8135_PIN_103_EINT11_AUXIN3__FUNC_EINT11 (MTK_PIN_NO(103) | 1) -#define MT8135_PIN_103_EINT11_AUXIN3__FUNC_USB_TEST_IO_17 (MTK_PIN_NO(103) | 5) -#define MT8135_PIN_103_EINT11_AUXIN3__FUNC_TESTB_OUT17 (MTK_PIN_NO(103) | 6) -#define MT8135_PIN_103_EINT11_AUXIN3__FUNC_A_FUNC_DIN_18 (MTK_PIN_NO(103) | 7) - -#define MT8135_PIN_104_EINT16_AUXIN4__FUNC_GPIO104 (MTK_PIN_NO(104) | 0) -#define MT8135_PIN_104_EINT16_AUXIN4__FUNC_EINT16 (MTK_PIN_NO(104) | 1) -#define MT8135_PIN_104_EINT16_AUXIN4__FUNC_USB_TEST_IO_18 (MTK_PIN_NO(104) | 5) -#define MT8135_PIN_104_EINT16_AUXIN4__FUNC_TESTB_OUT18 (MTK_PIN_NO(104) | 6) -#define MT8135_PIN_104_EINT16_AUXIN4__FUNC_A_FUNC_DIN_19 (MTK_PIN_NO(104) | 7) - -#define MT8135_PIN_105_I2S_CLK__FUNC_GPIO105 (MTK_PIN_NO(105) | 0) -#define MT8135_PIN_105_I2S_CLK__FUNC_I2SIN_CK (MTK_PIN_NO(105) | 1) -#define MT8135_PIN_105_I2S_CLK__FUNC_EINT10 (MTK_PIN_NO(105) | 2) -#define MT8135_PIN_105_I2S_CLK__FUNC_DAC_CK (MTK_PIN_NO(105) | 3) -#define MT8135_PIN_105_I2S_CLK__FUNC_PCM1_CK (MTK_PIN_NO(105) | 4) -#define MT8135_PIN_105_I2S_CLK__FUNC_USB_TEST_IO_19 (MTK_PIN_NO(105) | 5) -#define MT8135_PIN_105_I2S_CLK__FUNC_TESTB_OUT19 (MTK_PIN_NO(105) | 6) -#define MT8135_PIN_105_I2S_CLK__FUNC_A_FUNC_DIN_20 (MTK_PIN_NO(105) | 7) - -#define MT8135_PIN_106_I2S_WS__FUNC_GPIO106 (MTK_PIN_NO(106) | 0) -#define MT8135_PIN_106_I2S_WS__FUNC_I2SIN_WS (MTK_PIN_NO(106) | 1) -#define MT8135_PIN_106_I2S_WS__FUNC_EINT13 (MTK_PIN_NO(106) | 2) -#define MT8135_PIN_106_I2S_WS__FUNC_DAC_WS (MTK_PIN_NO(106) | 3) -#define MT8135_PIN_106_I2S_WS__FUNC_PCM1_WS (MTK_PIN_NO(106) | 4) -#define MT8135_PIN_106_I2S_WS__FUNC_USB_TEST_IO_20 (MTK_PIN_NO(106) | 5) -#define MT8135_PIN_106_I2S_WS__FUNC_TESTB_OUT20 (MTK_PIN_NO(106) | 6) -#define MT8135_PIN_106_I2S_WS__FUNC_A_FUNC_DIN_21 (MTK_PIN_NO(106) | 7) - -#define MT8135_PIN_107_I2S_DATA_IN__FUNC_GPIO107 (MTK_PIN_NO(107) | 0) -#define MT8135_PIN_107_I2S_DATA_IN__FUNC_I2SIN_DAT (MTK_PIN_NO(107) | 1) -#define MT8135_PIN_107_I2S_DATA_IN__FUNC_EINT11 (MTK_PIN_NO(107) | 2) -#define MT8135_PIN_107_I2S_DATA_IN__FUNC_PCM1_DI (MTK_PIN_NO(107) | 4) -#define MT8135_PIN_107_I2S_DATA_IN__FUNC_USB_TEST_IO_21 (MTK_PIN_NO(107) | 5) -#define MT8135_PIN_107_I2S_DATA_IN__FUNC_TESTB_OUT22 (MTK_PIN_NO(107) | 6) -#define MT8135_PIN_107_I2S_DATA_IN__FUNC_A_FUNC_DIN_22 (MTK_PIN_NO(107) | 7) - -#define MT8135_PIN_108_I2S_DATA_OUT__FUNC_GPIO108 (MTK_PIN_NO(108) | 0) -#define MT8135_PIN_108_I2S_DATA_OUT__FUNC_I2SOUT_DAT (MTK_PIN_NO(108) | 1) -#define MT8135_PIN_108_I2S_DATA_OUT__FUNC_EINT12 (MTK_PIN_NO(108) | 2) -#define MT8135_PIN_108_I2S_DATA_OUT__FUNC_DAC_DAT_OUT (MTK_PIN_NO(108) | 3) -#define MT8135_PIN_108_I2S_DATA_OUT__FUNC_PCM1_DO (MTK_PIN_NO(108) | 4) -#define MT8135_PIN_108_I2S_DATA_OUT__FUNC_USB_TEST_IO_22 (MTK_PIN_NO(108) | 5) -#define MT8135_PIN_108_I2S_DATA_OUT__FUNC_TESTB_OUT23 (MTK_PIN_NO(108) | 6) -#define MT8135_PIN_108_I2S_DATA_OUT__FUNC_A_FUNC_DIN_23 (MTK_PIN_NO(108) | 7) - -#define MT8135_PIN_109_EINT5__FUNC_GPIO109 (MTK_PIN_NO(109) | 0) -#define MT8135_PIN_109_EINT5__FUNC_EINT5 (MTK_PIN_NO(109) | 1) -#define MT8135_PIN_109_EINT5__FUNC_PWM5 (MTK_PIN_NO(109) | 2) -#define MT8135_PIN_109_EINT5__FUNC_CLKM3 (MTK_PIN_NO(109) | 3) -#define MT8135_PIN_109_EINT5__FUNC_GPU_JTRSTB (MTK_PIN_NO(109) | 4) -#define MT8135_PIN_109_EINT5__FUNC_USB_TEST_IO_23 (MTK_PIN_NO(109) | 5) -#define MT8135_PIN_109_EINT5__FUNC_TESTB_OUT26 (MTK_PIN_NO(109) | 6) -#define MT8135_PIN_109_EINT5__FUNC_A_FUNC_DIN_24 (MTK_PIN_NO(109) | 7) - -#define MT8135_PIN_110_EINT6__FUNC_GPIO110 (MTK_PIN_NO(110) | 0) -#define MT8135_PIN_110_EINT6__FUNC_EINT6 (MTK_PIN_NO(110) | 1) -#define MT8135_PIN_110_EINT6__FUNC_PWM6 (MTK_PIN_NO(110) | 2) -#define MT8135_PIN_110_EINT6__FUNC_CLKM4 (MTK_PIN_NO(110) | 3) -#define MT8135_PIN_110_EINT6__FUNC_GPU_JTMS (MTK_PIN_NO(110) | 4) -#define MT8135_PIN_110_EINT6__FUNC_USB_TEST_IO_24 (MTK_PIN_NO(110) | 5) -#define MT8135_PIN_110_EINT6__FUNC_TESTB_OUT27 (MTK_PIN_NO(110) | 6) -#define MT8135_PIN_110_EINT6__FUNC_A_FUNC_DIN_25 (MTK_PIN_NO(110) | 7) - -#define MT8135_PIN_111_EINT7__FUNC_GPIO111 (MTK_PIN_NO(111) | 0) -#define MT8135_PIN_111_EINT7__FUNC_EINT7 (MTK_PIN_NO(111) | 1) -#define MT8135_PIN_111_EINT7__FUNC_PWM7 (MTK_PIN_NO(111) | 2) -#define MT8135_PIN_111_EINT7__FUNC_CLKM5 (MTK_PIN_NO(111) | 3) -#define MT8135_PIN_111_EINT7__FUNC_GPU_JTDO (MTK_PIN_NO(111) | 4) -#define MT8135_PIN_111_EINT7__FUNC_USB_TEST_IO_25 (MTK_PIN_NO(111) | 5) -#define MT8135_PIN_111_EINT7__FUNC_TESTB_OUT28 (MTK_PIN_NO(111) | 6) -#define MT8135_PIN_111_EINT7__FUNC_A_FUNC_DIN_26 (MTK_PIN_NO(111) | 7) - -#define MT8135_PIN_112_EINT8__FUNC_GPIO112 (MTK_PIN_NO(112) | 0) -#define MT8135_PIN_112_EINT8__FUNC_EINT8 (MTK_PIN_NO(112) | 1) -#define MT8135_PIN_112_EINT8__FUNC_DISP_PWM (MTK_PIN_NO(112) | 2) -#define MT8135_PIN_112_EINT8__FUNC_CLKM6 (MTK_PIN_NO(112) | 3) -#define MT8135_PIN_112_EINT8__FUNC_GPU_JTDI (MTK_PIN_NO(112) | 4) -#define MT8135_PIN_112_EINT8__FUNC_USB_TEST_IO_26 (MTK_PIN_NO(112) | 5) -#define MT8135_PIN_112_EINT8__FUNC_TESTB_OUT29 (MTK_PIN_NO(112) | 6) -#define MT8135_PIN_112_EINT8__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(112) | 7) - -#define MT8135_PIN_113_EINT9__FUNC_GPIO113 (MTK_PIN_NO(113) | 0) -#define MT8135_PIN_113_EINT9__FUNC_EINT9 (MTK_PIN_NO(113) | 1) -#define MT8135_PIN_113_EINT9__FUNC_GPU_JTCK (MTK_PIN_NO(113) | 4) -#define MT8135_PIN_113_EINT9__FUNC_USB_DRVVBUS (MTK_PIN_NO(113) | 5) -#define MT8135_PIN_113_EINT9__FUNC_TESTB_OUT30 (MTK_PIN_NO(113) | 6) -#define MT8135_PIN_113_EINT9__FUNC_A_FUNC_DIN_27 (MTK_PIN_NO(113) | 7) - -#define MT8135_PIN_114_LPCE1B__FUNC_GPIO114 (MTK_PIN_NO(114) | 0) -#define MT8135_PIN_114_LPCE1B__FUNC_LPCE1B (MTK_PIN_NO(114) | 1) -#define MT8135_PIN_114_LPCE1B__FUNC_EINT127 (MTK_PIN_NO(114) | 2) -#define MT8135_PIN_114_LPCE1B__FUNC_PWM2 (MTK_PIN_NO(114) | 5) -#define MT8135_PIN_114_LPCE1B__FUNC_TESTB_OUT14 (MTK_PIN_NO(114) | 6) -#define MT8135_PIN_114_LPCE1B__FUNC_A_FUNC_DIN_28 (MTK_PIN_NO(114) | 7) - -#define MT8135_PIN_115_LPCE0B__FUNC_GPIO115 (MTK_PIN_NO(115) | 0) -#define MT8135_PIN_115_LPCE0B__FUNC_LPCE0B (MTK_PIN_NO(115) | 1) -#define MT8135_PIN_115_LPCE0B__FUNC_EINT126 (MTK_PIN_NO(115) | 2) -#define MT8135_PIN_115_LPCE0B__FUNC_PWM1 (MTK_PIN_NO(115) | 5) -#define MT8135_PIN_115_LPCE0B__FUNC_TESTB_OUT15 (MTK_PIN_NO(115) | 6) -#define MT8135_PIN_115_LPCE0B__FUNC_A_FUNC_DIN_29 (MTK_PIN_NO(115) | 7) - -#define MT8135_PIN_116_DISP_PWM__FUNC_GPIO116 (MTK_PIN_NO(116) | 0) -#define MT8135_PIN_116_DISP_PWM__FUNC_DISP_PWM (MTK_PIN_NO(116) | 1) -#define MT8135_PIN_116_DISP_PWM__FUNC_EINT77 (MTK_PIN_NO(116) | 2) -#define MT8135_PIN_116_DISP_PWM__FUNC_LSDI (MTK_PIN_NO(116) | 3) -#define MT8135_PIN_116_DISP_PWM__FUNC_PWM1 (MTK_PIN_NO(116) | 4) -#define MT8135_PIN_116_DISP_PWM__FUNC_PWM2 (MTK_PIN_NO(116) | 5) -#define MT8135_PIN_116_DISP_PWM__FUNC_PWM3 (MTK_PIN_NO(116) | 7) - -#define MT8135_PIN_117_EINT1__FUNC_GPIO117 (MTK_PIN_NO(117) | 0) -#define MT8135_PIN_117_EINT1__FUNC_EINT1 (MTK_PIN_NO(117) | 1) -#define MT8135_PIN_117_EINT1__FUNC_PWM2 (MTK_PIN_NO(117) | 2) -#define MT8135_PIN_117_EINT1__FUNC_CLKM1 (MTK_PIN_NO(117) | 3) -#define MT8135_PIN_117_EINT1__FUNC_USB_TEST_IO_13 (MTK_PIN_NO(117) | 5) -#define MT8135_PIN_117_EINT1__FUNC_USB_SDA (MTK_PIN_NO(117) | 7) - -#define MT8135_PIN_118_EINT2__FUNC_GPIO118 (MTK_PIN_NO(118) | 0) -#define MT8135_PIN_118_EINT2__FUNC_EINT2 (MTK_PIN_NO(118) | 1) -#define MT8135_PIN_118_EINT2__FUNC_PWM3 (MTK_PIN_NO(118) | 2) -#define MT8135_PIN_118_EINT2__FUNC_CLKM2 (MTK_PIN_NO(118) | 3) -#define MT8135_PIN_118_EINT2__FUNC_USB_TEST_IO_14 (MTK_PIN_NO(118) | 5) -#define MT8135_PIN_118_EINT2__FUNC_SRCLKENAI2 (MTK_PIN_NO(118) | 6) -#define MT8135_PIN_118_EINT2__FUNC_A_FUNC_DIN_30 (MTK_PIN_NO(118) | 7) - -#define MT8135_PIN_119_EINT3__FUNC_GPIO119 (MTK_PIN_NO(119) | 0) -#define MT8135_PIN_119_EINT3__FUNC_EINT3 (MTK_PIN_NO(119) | 1) -#define MT8135_PIN_119_EINT3__FUNC_USB_TEST_IO_15 (MTK_PIN_NO(119) | 5) -#define MT8135_PIN_119_EINT3__FUNC_SRCLKENAI1 (MTK_PIN_NO(119) | 6) -#define MT8135_PIN_119_EINT3__FUNC_EXT_26M_CK (MTK_PIN_NO(119) | 7) - -#define MT8135_PIN_120_EINT4__FUNC_GPIO120 (MTK_PIN_NO(120) | 0) -#define MT8135_PIN_120_EINT4__FUNC_EINT4 (MTK_PIN_NO(120) | 1) -#define MT8135_PIN_120_EINT4__FUNC_PWM4 (MTK_PIN_NO(120) | 2) -#define MT8135_PIN_120_EINT4__FUNC_USB_DRVVBUS (MTK_PIN_NO(120) | 5) -#define MT8135_PIN_120_EINT4__FUNC_A_FUNC_DIN_31 (MTK_PIN_NO(120) | 7) - -#define MT8135_PIN_121_DPIDE__FUNC_GPIO121 (MTK_PIN_NO(121) | 0) -#define MT8135_PIN_121_DPIDE__FUNC_DPI0_DE (MTK_PIN_NO(121) | 1) -#define MT8135_PIN_121_DPIDE__FUNC_EINT100 (MTK_PIN_NO(121) | 2) -#define MT8135_PIN_121_DPIDE__FUNC_I2SOUT_DAT (MTK_PIN_NO(121) | 3) -#define MT8135_PIN_121_DPIDE__FUNC_DAC_DAT_OUT (MTK_PIN_NO(121) | 4) -#define MT8135_PIN_121_DPIDE__FUNC_PCM1_DO (MTK_PIN_NO(121) | 5) -#define MT8135_PIN_121_DPIDE__FUNC_IRDA_TXD (MTK_PIN_NO(121) | 6) - -#define MT8135_PIN_122_DPICK__FUNC_GPIO122 (MTK_PIN_NO(122) | 0) -#define MT8135_PIN_122_DPICK__FUNC_DPI0_CK (MTK_PIN_NO(122) | 1) -#define MT8135_PIN_122_DPICK__FUNC_EINT101 (MTK_PIN_NO(122) | 2) -#define MT8135_PIN_122_DPICK__FUNC_I2SIN_DAT (MTK_PIN_NO(122) | 3) -#define MT8135_PIN_122_DPICK__FUNC_PCM1_DI (MTK_PIN_NO(122) | 5) -#define MT8135_PIN_122_DPICK__FUNC_IRDA_PDN (MTK_PIN_NO(122) | 6) - -#define MT8135_PIN_123_DPIG4__FUNC_GPIO123 (MTK_PIN_NO(123) | 0) -#define MT8135_PIN_123_DPIG4__FUNC_DPI0_G4 (MTK_PIN_NO(123) | 1) -#define MT8135_PIN_123_DPIG4__FUNC_EINT114 (MTK_PIN_NO(123) | 2) -#define MT8135_PIN_123_DPIG4__FUNC_CM2DAT_2X_0 (MTK_PIN_NO(123) | 4) -#define MT8135_PIN_123_DPIG4__FUNC_DSP2_ID (MTK_PIN_NO(123) | 5) - -#define MT8135_PIN_124_DPIG5__FUNC_GPIO124 (MTK_PIN_NO(124) | 0) -#define MT8135_PIN_124_DPIG5__FUNC_DPI0_G5 (MTK_PIN_NO(124) | 1) -#define MT8135_PIN_124_DPIG5__FUNC_EINT115 (MTK_PIN_NO(124) | 2) -#define MT8135_PIN_124_DPIG5__FUNC_CM2DAT_2X_1 (MTK_PIN_NO(124) | 4) -#define MT8135_PIN_124_DPIG5__FUNC_DSP2_ICK (MTK_PIN_NO(124) | 5) - -#define MT8135_PIN_125_DPIR3__FUNC_GPIO125 (MTK_PIN_NO(125) | 0) -#define MT8135_PIN_125_DPIR3__FUNC_DPI0_R3 (MTK_PIN_NO(125) | 1) -#define MT8135_PIN_125_DPIR3__FUNC_EINT121 (MTK_PIN_NO(125) | 2) -#define MT8135_PIN_125_DPIR3__FUNC_CM2DAT_2X_7 (MTK_PIN_NO(125) | 4) - -#define MT8135_PIN_126_DPIG1__FUNC_GPIO126 (MTK_PIN_NO(126) | 0) -#define MT8135_PIN_126_DPIG1__FUNC_DPI0_G1 (MTK_PIN_NO(126) | 1) -#define MT8135_PIN_126_DPIG1__FUNC_EINT111 (MTK_PIN_NO(126) | 2) -#define MT8135_PIN_126_DPIG1__FUNC_DSP1_ICK (MTK_PIN_NO(126) | 5) - -#define MT8135_PIN_127_DPIVSYNC__FUNC_GPIO127 (MTK_PIN_NO(127) | 0) -#define MT8135_PIN_127_DPIVSYNC__FUNC_DPI0_VSYNC (MTK_PIN_NO(127) | 1) -#define MT8135_PIN_127_DPIVSYNC__FUNC_EINT98 (MTK_PIN_NO(127) | 2) -#define MT8135_PIN_127_DPIVSYNC__FUNC_I2SIN_CK (MTK_PIN_NO(127) | 3) -#define MT8135_PIN_127_DPIVSYNC__FUNC_DAC_CK (MTK_PIN_NO(127) | 4) -#define MT8135_PIN_127_DPIVSYNC__FUNC_PCM1_CK (MTK_PIN_NO(127) | 5) - -#define MT8135_PIN_128_DPIHSYNC__FUNC_GPIO128 (MTK_PIN_NO(128) | 0) -#define MT8135_PIN_128_DPIHSYNC__FUNC_DPI0_HSYNC (MTK_PIN_NO(128) | 1) -#define MT8135_PIN_128_DPIHSYNC__FUNC_EINT99 (MTK_PIN_NO(128) | 2) -#define MT8135_PIN_128_DPIHSYNC__FUNC_I2SIN_WS (MTK_PIN_NO(128) | 3) -#define MT8135_PIN_128_DPIHSYNC__FUNC_DAC_WS (MTK_PIN_NO(128) | 4) -#define MT8135_PIN_128_DPIHSYNC__FUNC_PCM1_WS (MTK_PIN_NO(128) | 5) -#define MT8135_PIN_128_DPIHSYNC__FUNC_IRDA_RXD (MTK_PIN_NO(128) | 6) - -#define MT8135_PIN_129_DPIB0__FUNC_GPIO129 (MTK_PIN_NO(129) | 0) -#define MT8135_PIN_129_DPIB0__FUNC_DPI0_B0 (MTK_PIN_NO(129) | 1) -#define MT8135_PIN_129_DPIB0__FUNC_EINT102 (MTK_PIN_NO(129) | 2) -#define MT8135_PIN_129_DPIB0__FUNC_SCL0 (MTK_PIN_NO(129) | 4) -#define MT8135_PIN_129_DPIB0__FUNC_DISP_PWM (MTK_PIN_NO(129) | 5) - -#define MT8135_PIN_130_DPIB1__FUNC_GPIO130 (MTK_PIN_NO(130) | 0) -#define MT8135_PIN_130_DPIB1__FUNC_DPI0_B1 (MTK_PIN_NO(130) | 1) -#define MT8135_PIN_130_DPIB1__FUNC_EINT103 (MTK_PIN_NO(130) | 2) -#define MT8135_PIN_130_DPIB1__FUNC_CLKM0 (MTK_PIN_NO(130) | 3) -#define MT8135_PIN_130_DPIB1__FUNC_SDA0 (MTK_PIN_NO(130) | 4) -#define MT8135_PIN_130_DPIB1__FUNC_PWM1 (MTK_PIN_NO(130) | 5) - -#define MT8135_PIN_131_DPIB2__FUNC_GPIO131 (MTK_PIN_NO(131) | 0) -#define MT8135_PIN_131_DPIB2__FUNC_DPI0_B2 (MTK_PIN_NO(131) | 1) -#define MT8135_PIN_131_DPIB2__FUNC_EINT104 (MTK_PIN_NO(131) | 2) -#define MT8135_PIN_131_DPIB2__FUNC_CLKM1 (MTK_PIN_NO(131) | 3) -#define MT8135_PIN_131_DPIB2__FUNC_SCL1 (MTK_PIN_NO(131) | 4) -#define MT8135_PIN_131_DPIB2__FUNC_PWM2 (MTK_PIN_NO(131) | 5) - -#define MT8135_PIN_132_DPIB3__FUNC_GPIO132 (MTK_PIN_NO(132) | 0) -#define MT8135_PIN_132_DPIB3__FUNC_DPI0_B3 (MTK_PIN_NO(132) | 1) -#define MT8135_PIN_132_DPIB3__FUNC_EINT105 (MTK_PIN_NO(132) | 2) -#define MT8135_PIN_132_DPIB3__FUNC_CLKM2 (MTK_PIN_NO(132) | 3) -#define MT8135_PIN_132_DPIB3__FUNC_SDA1 (MTK_PIN_NO(132) | 4) -#define MT8135_PIN_132_DPIB3__FUNC_PWM3 (MTK_PIN_NO(132) | 5) - -#define MT8135_PIN_133_DPIB4__FUNC_GPIO133 (MTK_PIN_NO(133) | 0) -#define MT8135_PIN_133_DPIB4__FUNC_DPI0_B4 (MTK_PIN_NO(133) | 1) -#define MT8135_PIN_133_DPIB4__FUNC_EINT106 (MTK_PIN_NO(133) | 2) -#define MT8135_PIN_133_DPIB4__FUNC_CLKM3 (MTK_PIN_NO(133) | 3) -#define MT8135_PIN_133_DPIB4__FUNC_SCL2 (MTK_PIN_NO(133) | 4) -#define MT8135_PIN_133_DPIB4__FUNC_PWM4 (MTK_PIN_NO(133) | 5) - -#define MT8135_PIN_134_DPIB5__FUNC_GPIO134 (MTK_PIN_NO(134) | 0) -#define MT8135_PIN_134_DPIB5__FUNC_DPI0_B5 (MTK_PIN_NO(134) | 1) -#define MT8135_PIN_134_DPIB5__FUNC_EINT107 (MTK_PIN_NO(134) | 2) -#define MT8135_PIN_134_DPIB5__FUNC_CLKM4 (MTK_PIN_NO(134) | 3) -#define MT8135_PIN_134_DPIB5__FUNC_SDA2 (MTK_PIN_NO(134) | 4) -#define MT8135_PIN_134_DPIB5__FUNC_PWM5 (MTK_PIN_NO(134) | 5) - -#define MT8135_PIN_135_DPIB6__FUNC_GPIO135 (MTK_PIN_NO(135) | 0) -#define MT8135_PIN_135_DPIB6__FUNC_DPI0_B6 (MTK_PIN_NO(135) | 1) -#define MT8135_PIN_135_DPIB6__FUNC_EINT108 (MTK_PIN_NO(135) | 2) -#define MT8135_PIN_135_DPIB6__FUNC_CLKM5 (MTK_PIN_NO(135) | 3) -#define MT8135_PIN_135_DPIB6__FUNC_SCL3 (MTK_PIN_NO(135) | 4) -#define MT8135_PIN_135_DPIB6__FUNC_PWM6 (MTK_PIN_NO(135) | 5) - -#define MT8135_PIN_136_DPIB7__FUNC_GPIO136 (MTK_PIN_NO(136) | 0) -#define MT8135_PIN_136_DPIB7__FUNC_DPI0_B7 (MTK_PIN_NO(136) | 1) -#define MT8135_PIN_136_DPIB7__FUNC_EINT109 (MTK_PIN_NO(136) | 2) -#define MT8135_PIN_136_DPIB7__FUNC_CLKM6 (MTK_PIN_NO(136) | 3) -#define MT8135_PIN_136_DPIB7__FUNC_SDA3 (MTK_PIN_NO(136) | 4) -#define MT8135_PIN_136_DPIB7__FUNC_PWM7 (MTK_PIN_NO(136) | 5) - -#define MT8135_PIN_137_DPIG0__FUNC_GPIO137 (MTK_PIN_NO(137) | 0) -#define MT8135_PIN_137_DPIG0__FUNC_DPI0_G0 (MTK_PIN_NO(137) | 1) -#define MT8135_PIN_137_DPIG0__FUNC_EINT110 (MTK_PIN_NO(137) | 2) -#define MT8135_PIN_137_DPIG0__FUNC_DSP1_ID (MTK_PIN_NO(137) | 5) - -#define MT8135_PIN_138_DPIG2__FUNC_GPIO138 (MTK_PIN_NO(138) | 0) -#define MT8135_PIN_138_DPIG2__FUNC_DPI0_G2 (MTK_PIN_NO(138) | 1) -#define MT8135_PIN_138_DPIG2__FUNC_EINT112 (MTK_PIN_NO(138) | 2) -#define MT8135_PIN_138_DPIG2__FUNC_DSP1_IMS (MTK_PIN_NO(138) | 5) - -#define MT8135_PIN_139_DPIG3__FUNC_GPIO139 (MTK_PIN_NO(139) | 0) -#define MT8135_PIN_139_DPIG3__FUNC_DPI0_G3 (MTK_PIN_NO(139) | 1) -#define MT8135_PIN_139_DPIG3__FUNC_EINT113 (MTK_PIN_NO(139) | 2) -#define MT8135_PIN_139_DPIG3__FUNC_DSP2_IMS (MTK_PIN_NO(139) | 5) - -#define MT8135_PIN_140_DPIG6__FUNC_GPIO140 (MTK_PIN_NO(140) | 0) -#define MT8135_PIN_140_DPIG6__FUNC_DPI0_G6 (MTK_PIN_NO(140) | 1) -#define MT8135_PIN_140_DPIG6__FUNC_EINT116 (MTK_PIN_NO(140) | 2) -#define MT8135_PIN_140_DPIG6__FUNC_CM2DAT_2X_2 (MTK_PIN_NO(140) | 4) - -#define MT8135_PIN_141_DPIG7__FUNC_GPIO141 (MTK_PIN_NO(141) | 0) -#define MT8135_PIN_141_DPIG7__FUNC_DPI0_G7 (MTK_PIN_NO(141) | 1) -#define MT8135_PIN_141_DPIG7__FUNC_EINT117 (MTK_PIN_NO(141) | 2) -#define MT8135_PIN_141_DPIG7__FUNC_CM2DAT_2X_3 (MTK_PIN_NO(141) | 4) - -#define MT8135_PIN_142_DPIR0__FUNC_GPIO142 (MTK_PIN_NO(142) | 0) -#define MT8135_PIN_142_DPIR0__FUNC_DPI0_R0 (MTK_PIN_NO(142) | 1) -#define MT8135_PIN_142_DPIR0__FUNC_EINT118 (MTK_PIN_NO(142) | 2) -#define MT8135_PIN_142_DPIR0__FUNC_CM2DAT_2X_4 (MTK_PIN_NO(142) | 4) - -#define MT8135_PIN_143_DPIR1__FUNC_GPIO143 (MTK_PIN_NO(143) | 0) -#define MT8135_PIN_143_DPIR1__FUNC_DPI0_R1 (MTK_PIN_NO(143) | 1) -#define MT8135_PIN_143_DPIR1__FUNC_EINT119 (MTK_PIN_NO(143) | 2) -#define MT8135_PIN_143_DPIR1__FUNC_CM2DAT_2X_5 (MTK_PIN_NO(143) | 4) - -#define MT8135_PIN_144_DPIR2__FUNC_GPIO144 (MTK_PIN_NO(144) | 0) -#define MT8135_PIN_144_DPIR2__FUNC_DPI0_R2 (MTK_PIN_NO(144) | 1) -#define MT8135_PIN_144_DPIR2__FUNC_EINT120 (MTK_PIN_NO(144) | 2) -#define MT8135_PIN_144_DPIR2__FUNC_CM2DAT_2X_6 (MTK_PIN_NO(144) | 4) - -#define MT8135_PIN_145_DPIR4__FUNC_GPIO145 (MTK_PIN_NO(145) | 0) -#define MT8135_PIN_145_DPIR4__FUNC_DPI0_R4 (MTK_PIN_NO(145) | 1) -#define MT8135_PIN_145_DPIR4__FUNC_EINT122 (MTK_PIN_NO(145) | 2) -#define MT8135_PIN_145_DPIR4__FUNC_CM2DAT_2X_8 (MTK_PIN_NO(145) | 4) - -#define MT8135_PIN_146_DPIR5__FUNC_GPIO146 (MTK_PIN_NO(146) | 0) -#define MT8135_PIN_146_DPIR5__FUNC_DPI0_R5 (MTK_PIN_NO(146) | 1) -#define MT8135_PIN_146_DPIR5__FUNC_EINT123 (MTK_PIN_NO(146) | 2) -#define MT8135_PIN_146_DPIR5__FUNC_CM2DAT_2X_9 (MTK_PIN_NO(146) | 4) - -#define MT8135_PIN_147_DPIR6__FUNC_GPIO147 (MTK_PIN_NO(147) | 0) -#define MT8135_PIN_147_DPIR6__FUNC_DPI0_R6 (MTK_PIN_NO(147) | 1) -#define MT8135_PIN_147_DPIR6__FUNC_EINT124 (MTK_PIN_NO(147) | 2) -#define MT8135_PIN_147_DPIR6__FUNC_CM2VSYNC_2X (MTK_PIN_NO(147) | 4) - -#define MT8135_PIN_148_DPIR7__FUNC_GPIO148 (MTK_PIN_NO(148) | 0) -#define MT8135_PIN_148_DPIR7__FUNC_DPI0_R7 (MTK_PIN_NO(148) | 1) -#define MT8135_PIN_148_DPIR7__FUNC_EINT125 (MTK_PIN_NO(148) | 2) -#define MT8135_PIN_148_DPIR7__FUNC_CM2HSYNC_2X (MTK_PIN_NO(148) | 4) - -#define MT8135_PIN_149_TDN3__FUNC_GPIO149 (MTK_PIN_NO(149) | 0) -#define MT8135_PIN_149_TDN3__FUNC_EINT36 (MTK_PIN_NO(149) | 2) - -#define MT8135_PIN_150_TDP3__FUNC_GPIO150 (MTK_PIN_NO(150) | 0) -#define MT8135_PIN_150_TDP3__FUNC_EINT35 (MTK_PIN_NO(150) | 2) - -#define MT8135_PIN_151_TDN2__FUNC_GPIO151 (MTK_PIN_NO(151) | 0) -#define MT8135_PIN_151_TDN2__FUNC_EINT169 (MTK_PIN_NO(151) | 2) - -#define MT8135_PIN_152_TDP2__FUNC_GPIO152 (MTK_PIN_NO(152) | 0) -#define MT8135_PIN_152_TDP2__FUNC_EINT168 (MTK_PIN_NO(152) | 2) - -#define MT8135_PIN_153_TCN__FUNC_GPIO153 (MTK_PIN_NO(153) | 0) -#define MT8135_PIN_153_TCN__FUNC_EINT163 (MTK_PIN_NO(153) | 2) - -#define MT8135_PIN_154_TCP__FUNC_GPIO154 (MTK_PIN_NO(154) | 0) -#define MT8135_PIN_154_TCP__FUNC_EINT162 (MTK_PIN_NO(154) | 2) - -#define MT8135_PIN_155_TDN1__FUNC_GPIO155 (MTK_PIN_NO(155) | 0) -#define MT8135_PIN_155_TDN1__FUNC_EINT167 (MTK_PIN_NO(155) | 2) - -#define MT8135_PIN_156_TDP1__FUNC_GPIO156 (MTK_PIN_NO(156) | 0) -#define MT8135_PIN_156_TDP1__FUNC_EINT166 (MTK_PIN_NO(156) | 2) - -#define MT8135_PIN_157_TDN0__FUNC_GPIO157 (MTK_PIN_NO(157) | 0) -#define MT8135_PIN_157_TDN0__FUNC_EINT165 (MTK_PIN_NO(157) | 2) - -#define MT8135_PIN_158_TDP0__FUNC_GPIO158 (MTK_PIN_NO(158) | 0) -#define MT8135_PIN_158_TDP0__FUNC_EINT164 (MTK_PIN_NO(158) | 2) - -#define MT8135_PIN_159_RDN3__FUNC_GPIO159 (MTK_PIN_NO(159) | 0) -#define MT8135_PIN_159_RDN3__FUNC_EINT18 (MTK_PIN_NO(159) | 2) - -#define MT8135_PIN_160_RDP3__FUNC_GPIO160 (MTK_PIN_NO(160) | 0) -#define MT8135_PIN_160_RDP3__FUNC_EINT30 (MTK_PIN_NO(160) | 2) - -#define MT8135_PIN_161_RDN2__FUNC_GPIO161 (MTK_PIN_NO(161) | 0) -#define MT8135_PIN_161_RDN2__FUNC_EINT31 (MTK_PIN_NO(161) | 2) - -#define MT8135_PIN_162_RDP2__FUNC_GPIO162 (MTK_PIN_NO(162) | 0) -#define MT8135_PIN_162_RDP2__FUNC_EINT32 (MTK_PIN_NO(162) | 2) - -#define MT8135_PIN_163_RCN__FUNC_GPIO163 (MTK_PIN_NO(163) | 0) -#define MT8135_PIN_163_RCN__FUNC_EINT33 (MTK_PIN_NO(163) | 2) - -#define MT8135_PIN_164_RCP__FUNC_GPIO164 (MTK_PIN_NO(164) | 0) -#define MT8135_PIN_164_RCP__FUNC_EINT39 (MTK_PIN_NO(164) | 2) - -#define MT8135_PIN_165_RDN1__FUNC_GPIO165 (MTK_PIN_NO(165) | 0) - -#define MT8135_PIN_166_RDP1__FUNC_GPIO166 (MTK_PIN_NO(166) | 0) - -#define MT8135_PIN_167_RDN0__FUNC_GPIO167 (MTK_PIN_NO(167) | 0) - -#define MT8135_PIN_168_RDP0__FUNC_GPIO168 (MTK_PIN_NO(168) | 0) - -#define MT8135_PIN_169_RDN1_A__FUNC_GPIO169 (MTK_PIN_NO(169) | 0) -#define MT8135_PIN_169_RDN1_A__FUNC_CMDAT6 (MTK_PIN_NO(169) | 1) -#define MT8135_PIN_169_RDN1_A__FUNC_EINT175 (MTK_PIN_NO(169) | 2) - -#define MT8135_PIN_170_RDP1_A__FUNC_GPIO170 (MTK_PIN_NO(170) | 0) -#define MT8135_PIN_170_RDP1_A__FUNC_CMDAT7 (MTK_PIN_NO(170) | 1) -#define MT8135_PIN_170_RDP1_A__FUNC_EINT174 (MTK_PIN_NO(170) | 2) - -#define MT8135_PIN_171_RCN_A__FUNC_GPIO171 (MTK_PIN_NO(171) | 0) -#define MT8135_PIN_171_RCN_A__FUNC_CMDAT8 (MTK_PIN_NO(171) | 1) -#define MT8135_PIN_171_RCN_A__FUNC_EINT171 (MTK_PIN_NO(171) | 2) - -#define MT8135_PIN_172_RCP_A__FUNC_GPIO172 (MTK_PIN_NO(172) | 0) -#define MT8135_PIN_172_RCP_A__FUNC_CMDAT9 (MTK_PIN_NO(172) | 1) -#define MT8135_PIN_172_RCP_A__FUNC_EINT170 (MTK_PIN_NO(172) | 2) - -#define MT8135_PIN_173_RDN0_A__FUNC_GPIO173 (MTK_PIN_NO(173) | 0) -#define MT8135_PIN_173_RDN0_A__FUNC_CMHSYNC (MTK_PIN_NO(173) | 1) -#define MT8135_PIN_173_RDN0_A__FUNC_EINT173 (MTK_PIN_NO(173) | 2) - -#define MT8135_PIN_174_RDP0_A__FUNC_GPIO174 (MTK_PIN_NO(174) | 0) -#define MT8135_PIN_174_RDP0_A__FUNC_CMVSYNC (MTK_PIN_NO(174) | 1) -#define MT8135_PIN_174_RDP0_A__FUNC_EINT172 (MTK_PIN_NO(174) | 2) - -#define MT8135_PIN_175_RDN1_B__FUNC_GPIO175 (MTK_PIN_NO(175) | 0) -#define MT8135_PIN_175_RDN1_B__FUNC_CMDAT2 (MTK_PIN_NO(175) | 1) -#define MT8135_PIN_175_RDN1_B__FUNC_EINT181 (MTK_PIN_NO(175) | 2) -#define MT8135_PIN_175_RDN1_B__FUNC_CMCSD2 (MTK_PIN_NO(175) | 3) - -#define MT8135_PIN_176_RDP1_B__FUNC_GPIO176 (MTK_PIN_NO(176) | 0) -#define MT8135_PIN_176_RDP1_B__FUNC_CMDAT3 (MTK_PIN_NO(176) | 1) -#define MT8135_PIN_176_RDP1_B__FUNC_EINT180 (MTK_PIN_NO(176) | 2) -#define MT8135_PIN_176_RDP1_B__FUNC_CMCSD3 (MTK_PIN_NO(176) | 3) - -#define MT8135_PIN_177_RCN_B__FUNC_GPIO177 (MTK_PIN_NO(177) | 0) -#define MT8135_PIN_177_RCN_B__FUNC_CMDAT4 (MTK_PIN_NO(177) | 1) -#define MT8135_PIN_177_RCN_B__FUNC_EINT177 (MTK_PIN_NO(177) | 2) - -#define MT8135_PIN_178_RCP_B__FUNC_GPIO178 (MTK_PIN_NO(178) | 0) -#define MT8135_PIN_178_RCP_B__FUNC_CMDAT5 (MTK_PIN_NO(178) | 1) -#define MT8135_PIN_178_RCP_B__FUNC_EINT176 (MTK_PIN_NO(178) | 2) - -#define MT8135_PIN_179_RDN0_B__FUNC_GPIO179 (MTK_PIN_NO(179) | 0) -#define MT8135_PIN_179_RDN0_B__FUNC_CMDAT0 (MTK_PIN_NO(179) | 1) -#define MT8135_PIN_179_RDN0_B__FUNC_EINT179 (MTK_PIN_NO(179) | 2) -#define MT8135_PIN_179_RDN0_B__FUNC_CMCSD0 (MTK_PIN_NO(179) | 3) - -#define MT8135_PIN_180_RDP0_B__FUNC_GPIO180 (MTK_PIN_NO(180) | 0) -#define MT8135_PIN_180_RDP0_B__FUNC_CMDAT1 (MTK_PIN_NO(180) | 1) -#define MT8135_PIN_180_RDP0_B__FUNC_EINT178 (MTK_PIN_NO(180) | 2) -#define MT8135_PIN_180_RDP0_B__FUNC_CMCSD1 (MTK_PIN_NO(180) | 3) - -#define MT8135_PIN_181_CMPCLK__FUNC_GPIO181 (MTK_PIN_NO(181) | 0) -#define MT8135_PIN_181_CMPCLK__FUNC_CMPCLK (MTK_PIN_NO(181) | 1) -#define MT8135_PIN_181_CMPCLK__FUNC_EINT182 (MTK_PIN_NO(181) | 2) -#define MT8135_PIN_181_CMPCLK__FUNC_CMCSK (MTK_PIN_NO(181) | 3) -#define MT8135_PIN_181_CMPCLK__FUNC_CM2MCLK_4X (MTK_PIN_NO(181) | 4) -#define MT8135_PIN_181_CMPCLK__FUNC_TS_AUXADC_SEL_3 (MTK_PIN_NO(181) | 5) -#define MT8135_PIN_181_CMPCLK__FUNC_VENC_TEST_CK (MTK_PIN_NO(181) | 6) -#define MT8135_PIN_181_CMPCLK__FUNC_TESTA_OUT27 (MTK_PIN_NO(181) | 7) - -#define MT8135_PIN_182_CMMCLK__FUNC_GPIO182 (MTK_PIN_NO(182) | 0) -#define MT8135_PIN_182_CMMCLK__FUNC_CMMCLK (MTK_PIN_NO(182) | 1) -#define MT8135_PIN_182_CMMCLK__FUNC_EINT183 (MTK_PIN_NO(182) | 2) -#define MT8135_PIN_182_CMMCLK__FUNC_TS_AUXADC_SEL_2 (MTK_PIN_NO(182) | 5) -#define MT8135_PIN_182_CMMCLK__FUNC_TESTA_OUT28 (MTK_PIN_NO(182) | 7) - -#define MT8135_PIN_183_CMRST__FUNC_GPIO183 (MTK_PIN_NO(183) | 0) -#define MT8135_PIN_183_CMRST__FUNC_CMRST (MTK_PIN_NO(183) | 1) -#define MT8135_PIN_183_CMRST__FUNC_EINT185 (MTK_PIN_NO(183) | 2) -#define MT8135_PIN_183_CMRST__FUNC_TS_AUXADC_SEL_1 (MTK_PIN_NO(183) | 5) -#define MT8135_PIN_183_CMRST__FUNC_TESTA_OUT30 (MTK_PIN_NO(183) | 7) - -#define MT8135_PIN_184_CMPDN__FUNC_GPIO184 (MTK_PIN_NO(184) | 0) -#define MT8135_PIN_184_CMPDN__FUNC_CMPDN (MTK_PIN_NO(184) | 1) -#define MT8135_PIN_184_CMPDN__FUNC_EINT184 (MTK_PIN_NO(184) | 2) -#define MT8135_PIN_184_CMPDN__FUNC_TS_AUXADC_SEL_0 (MTK_PIN_NO(184) | 5) -#define MT8135_PIN_184_CMPDN__FUNC_TESTA_OUT29 (MTK_PIN_NO(184) | 7) - -#define MT8135_PIN_185_CMFLASH__FUNC_GPIO185 (MTK_PIN_NO(185) | 0) -#define MT8135_PIN_185_CMFLASH__FUNC_CMFLASH (MTK_PIN_NO(185) | 1) -#define MT8135_PIN_185_CMFLASH__FUNC_EINT186 (MTK_PIN_NO(185) | 2) -#define MT8135_PIN_185_CMFLASH__FUNC_CM2MCLK_3X (MTK_PIN_NO(185) | 3) -#define MT8135_PIN_185_CMFLASH__FUNC_MFG_TEST_CK_1 (MTK_PIN_NO(185) | 6) -#define MT8135_PIN_185_CMFLASH__FUNC_TESTA_OUT31 (MTK_PIN_NO(185) | 7) - -#define MT8135_PIN_186_MRG_I2S_PCM_CLK__FUNC_GPIO186 (MTK_PIN_NO(186) | 0) -#define MT8135_PIN_186_MRG_I2S_PCM_CLK__FUNC_MRG_I2S_P_CLK (MTK_PIN_NO(186) | 1) -#define MT8135_PIN_186_MRG_I2S_PCM_CLK__FUNC_EINT14 (MTK_PIN_NO(186) | 2) -#define MT8135_PIN_186_MRG_I2S_PCM_CLK__FUNC_I2SIN_CK (MTK_PIN_NO(186) | 3) -#define MT8135_PIN_186_MRG_I2S_PCM_CLK__FUNC_PCM0_CK (MTK_PIN_NO(186) | 4) -#define MT8135_PIN_186_MRG_I2S_PCM_CLK__FUNC_DSP2_ICK (MTK_PIN_NO(186) | 5) -#define MT8135_PIN_186_MRG_I2S_PCM_CLK__FUNC_IMG_TEST_CK (MTK_PIN_NO(186) | 6) -#define MT8135_PIN_186_MRG_I2S_PCM_CLK__FUNC_USB_SCL (MTK_PIN_NO(186) | 7) - -#define MT8135_PIN_187_MRG_I2S_PCM_SYNC__FUNC_GPIO187 (MTK_PIN_NO(187) | 0) -#define MT8135_PIN_187_MRG_I2S_PCM_SYNC__FUNC_MRG_I2S_SYNC (MTK_PIN_NO(187) | 1) -#define MT8135_PIN_187_MRG_I2S_PCM_SYNC__FUNC_EINT16 (MTK_PIN_NO(187) | 2) -#define MT8135_PIN_187_MRG_I2S_PCM_SYNC__FUNC_I2SIN_WS (MTK_PIN_NO(187) | 3) -#define MT8135_PIN_187_MRG_I2S_PCM_SYNC__FUNC_PCM0_WS (MTK_PIN_NO(187) | 4) -#define MT8135_PIN_187_MRG_I2S_PCM_SYNC__FUNC_DISP_TEST_CK (MTK_PIN_NO(187) | 6) - -#define MT8135_PIN_188_MRG_I2S_PCM_RX__FUNC_GPIO188 (MTK_PIN_NO(188) | 0) -#define MT8135_PIN_188_MRG_I2S_PCM_RX__FUNC_MRG_I2S_PCM_RX (MTK_PIN_NO(188) | 1) -#define MT8135_PIN_188_MRG_I2S_PCM_RX__FUNC_EINT15 (MTK_PIN_NO(188) | 2) -#define MT8135_PIN_188_MRG_I2S_PCM_RX__FUNC_I2SIN_DAT (MTK_PIN_NO(188) | 3) -#define MT8135_PIN_188_MRG_I2S_PCM_RX__FUNC_PCM0_DI (MTK_PIN_NO(188) | 4) -#define MT8135_PIN_188_MRG_I2S_PCM_RX__FUNC_DSP2_ID (MTK_PIN_NO(188) | 5) -#define MT8135_PIN_188_MRG_I2S_PCM_RX__FUNC_MFG_TEST_CK (MTK_PIN_NO(188) | 6) -#define MT8135_PIN_188_MRG_I2S_PCM_RX__FUNC_USB_SDA (MTK_PIN_NO(188) | 7) - -#define MT8135_PIN_189_MRG_I2S_PCM_TX__FUNC_GPIO189 (MTK_PIN_NO(189) | 0) -#define MT8135_PIN_189_MRG_I2S_PCM_TX__FUNC_MRG_I2S_PCM_TX (MTK_PIN_NO(189) | 1) -#define MT8135_PIN_189_MRG_I2S_PCM_TX__FUNC_EINT17 (MTK_PIN_NO(189) | 2) -#define MT8135_PIN_189_MRG_I2S_PCM_TX__FUNC_I2SOUT_DAT (MTK_PIN_NO(189) | 3) -#define MT8135_PIN_189_MRG_I2S_PCM_TX__FUNC_PCM0_DO (MTK_PIN_NO(189) | 4) -#define MT8135_PIN_189_MRG_I2S_PCM_TX__FUNC_VDEC_TEST_CK (MTK_PIN_NO(189) | 6) - -#define MT8135_PIN_190_SRCLKENAI__FUNC_GPIO190 (MTK_PIN_NO(190) | 0) -#define MT8135_PIN_190_SRCLKENAI__FUNC_SRCLKENAI (MTK_PIN_NO(190) | 1) - -#define MT8135_PIN_191_URXD3__FUNC_GPIO191 (MTK_PIN_NO(191) | 0) -#define MT8135_PIN_191_URXD3__FUNC_URXD3 (MTK_PIN_NO(191) | 1) -#define MT8135_PIN_191_URXD3__FUNC_EINT87 (MTK_PIN_NO(191) | 2) -#define MT8135_PIN_191_URXD3__FUNC_UTXD3 (MTK_PIN_NO(191) | 3) -#define MT8135_PIN_191_URXD3__FUNC_TS_AUX_ST (MTK_PIN_NO(191) | 5) -#define MT8135_PIN_191_URXD3__FUNC_PWM4 (MTK_PIN_NO(191) | 6) - -#define MT8135_PIN_192_UTXD3__FUNC_GPIO192 (MTK_PIN_NO(192) | 0) -#define MT8135_PIN_192_UTXD3__FUNC_UTXD3 (MTK_PIN_NO(192) | 1) -#define MT8135_PIN_192_UTXD3__FUNC_EINT86 (MTK_PIN_NO(192) | 2) -#define MT8135_PIN_192_UTXD3__FUNC_URXD3 (MTK_PIN_NO(192) | 3) -#define MT8135_PIN_192_UTXD3__FUNC_TS_AUX_CS_B (MTK_PIN_NO(192) | 5) -#define MT8135_PIN_192_UTXD3__FUNC_PWM3 (MTK_PIN_NO(192) | 6) - -#define MT8135_PIN_193_SDA2__FUNC_GPIO193 (MTK_PIN_NO(193) | 0) -#define MT8135_PIN_193_SDA2__FUNC_SDA2 (MTK_PIN_NO(193) | 1) -#define MT8135_PIN_193_SDA2__FUNC_EINT95 (MTK_PIN_NO(193) | 2) -#define MT8135_PIN_193_SDA2__FUNC_CLKM5 (MTK_PIN_NO(193) | 3) -#define MT8135_PIN_193_SDA2__FUNC_PWM5 (MTK_PIN_NO(193) | 4) -#define MT8135_PIN_193_SDA2__FUNC_TS_AUX_PWDB (MTK_PIN_NO(193) | 5) - -#define MT8135_PIN_194_SCL2__FUNC_GPIO194 (MTK_PIN_NO(194) | 0) -#define MT8135_PIN_194_SCL2__FUNC_SCL2 (MTK_PIN_NO(194) | 1) -#define MT8135_PIN_194_SCL2__FUNC_EINT94 (MTK_PIN_NO(194) | 2) -#define MT8135_PIN_194_SCL2__FUNC_CLKM4 (MTK_PIN_NO(194) | 3) -#define MT8135_PIN_194_SCL2__FUNC_PWM4 (MTK_PIN_NO(194) | 4) -#define MT8135_PIN_194_SCL2__FUNC_TS_AUXADC_TEST_CK (MTK_PIN_NO(194) | 5) - -#define MT8135_PIN_195_SDA1__FUNC_GPIO195 (MTK_PIN_NO(195) | 0) -#define MT8135_PIN_195_SDA1__FUNC_SDA1 (MTK_PIN_NO(195) | 1) -#define MT8135_PIN_195_SDA1__FUNC_EINT93 (MTK_PIN_NO(195) | 2) -#define MT8135_PIN_195_SDA1__FUNC_CLKM3 (MTK_PIN_NO(195) | 3) -#define MT8135_PIN_195_SDA1__FUNC_PWM3 (MTK_PIN_NO(195) | 4) -#define MT8135_PIN_195_SDA1__FUNC_TS_AUX_SCLK_PWDB (MTK_PIN_NO(195) | 5) - -#define MT8135_PIN_196_SCL1__FUNC_GPIO196 (MTK_PIN_NO(196) | 0) -#define MT8135_PIN_196_SCL1__FUNC_SCL1 (MTK_PIN_NO(196) | 1) -#define MT8135_PIN_196_SCL1__FUNC_EINT92 (MTK_PIN_NO(196) | 2) -#define MT8135_PIN_196_SCL1__FUNC_CLKM2 (MTK_PIN_NO(196) | 3) -#define MT8135_PIN_196_SCL1__FUNC_PWM2 (MTK_PIN_NO(196) | 4) -#define MT8135_PIN_196_SCL1__FUNC_TS_AUX_DIN (MTK_PIN_NO(196) | 5) - -#define MT8135_PIN_197_MSDC3_DAT2__FUNC_GPIO197 (MTK_PIN_NO(197) | 0) -#define MT8135_PIN_197_MSDC3_DAT2__FUNC_MSDC3_DAT2 (MTK_PIN_NO(197) | 1) -#define MT8135_PIN_197_MSDC3_DAT2__FUNC_EINT71 (MTK_PIN_NO(197) | 2) -#define MT8135_PIN_197_MSDC3_DAT2__FUNC_SCL6 (MTK_PIN_NO(197) | 3) -#define MT8135_PIN_197_MSDC3_DAT2__FUNC_PWM5 (MTK_PIN_NO(197) | 4) -#define MT8135_PIN_197_MSDC3_DAT2__FUNC_CLKM4 (MTK_PIN_NO(197) | 5) -#define MT8135_PIN_197_MSDC3_DAT2__FUNC_MFG_TEST_CK_2 (MTK_PIN_NO(197) | 6) - -#define MT8135_PIN_198_MSDC3_DAT3__FUNC_GPIO198 (MTK_PIN_NO(198) | 0) -#define MT8135_PIN_198_MSDC3_DAT3__FUNC_MSDC3_DAT3 (MTK_PIN_NO(198) | 1) -#define MT8135_PIN_198_MSDC3_DAT3__FUNC_EINT72 (MTK_PIN_NO(198) | 2) -#define MT8135_PIN_198_MSDC3_DAT3__FUNC_SDA6 (MTK_PIN_NO(198) | 3) -#define MT8135_PIN_198_MSDC3_DAT3__FUNC_PWM6 (MTK_PIN_NO(198) | 4) -#define MT8135_PIN_198_MSDC3_DAT3__FUNC_CLKM5 (MTK_PIN_NO(198) | 5) -#define MT8135_PIN_198_MSDC3_DAT3__FUNC_MFG_TEST_CK_3 (MTK_PIN_NO(198) | 6) - -#define MT8135_PIN_199_MSDC3_CMD__FUNC_GPIO199 (MTK_PIN_NO(199) | 0) -#define MT8135_PIN_199_MSDC3_CMD__FUNC_MSDC3_CMD (MTK_PIN_NO(199) | 1) -#define MT8135_PIN_199_MSDC3_CMD__FUNC_EINT68 (MTK_PIN_NO(199) | 2) -#define MT8135_PIN_199_MSDC3_CMD__FUNC_SDA2 (MTK_PIN_NO(199) | 3) -#define MT8135_PIN_199_MSDC3_CMD__FUNC_PWM2 (MTK_PIN_NO(199) | 4) -#define MT8135_PIN_199_MSDC3_CMD__FUNC_CLKM1 (MTK_PIN_NO(199) | 5) -#define MT8135_PIN_199_MSDC3_CMD__FUNC_MFG_TEST_CK_4 (MTK_PIN_NO(199) | 6) - -#define MT8135_PIN_200_MSDC3_CLK__FUNC_GPIO200 (MTK_PIN_NO(200) | 0) -#define MT8135_PIN_200_MSDC3_CLK__FUNC_MSDC3_CLK (MTK_PIN_NO(200) | 1) -#define MT8135_PIN_200_MSDC3_CLK__FUNC_EINT67 (MTK_PIN_NO(200) | 2) -#define MT8135_PIN_200_MSDC3_CLK__FUNC_SCL2 (MTK_PIN_NO(200) | 3) -#define MT8135_PIN_200_MSDC3_CLK__FUNC_PWM1 (MTK_PIN_NO(200) | 4) -#define MT8135_PIN_200_MSDC3_CLK__FUNC_CLKM0 (MTK_PIN_NO(200) | 5) - -#define MT8135_PIN_201_MSDC3_DAT1__FUNC_GPIO201 (MTK_PIN_NO(201) | 0) -#define MT8135_PIN_201_MSDC3_DAT1__FUNC_MSDC3_DAT1 (MTK_PIN_NO(201) | 1) -#define MT8135_PIN_201_MSDC3_DAT1__FUNC_EINT70 (MTK_PIN_NO(201) | 2) -#define MT8135_PIN_201_MSDC3_DAT1__FUNC_SDA3 (MTK_PIN_NO(201) | 3) -#define MT8135_PIN_201_MSDC3_DAT1__FUNC_PWM4 (MTK_PIN_NO(201) | 4) -#define MT8135_PIN_201_MSDC3_DAT1__FUNC_CLKM3 (MTK_PIN_NO(201) | 5) - -#define MT8135_PIN_202_MSDC3_DAT0__FUNC_GPIO202 (MTK_PIN_NO(202) | 0) -#define MT8135_PIN_202_MSDC3_DAT0__FUNC_MSDC3_DAT0 (MTK_PIN_NO(202) | 1) -#define MT8135_PIN_202_MSDC3_DAT0__FUNC_EINT69 (MTK_PIN_NO(202) | 2) -#define MT8135_PIN_202_MSDC3_DAT0__FUNC_SCL3 (MTK_PIN_NO(202) | 3) -#define MT8135_PIN_202_MSDC3_DAT0__FUNC_PWM3 (MTK_PIN_NO(202) | 4) -#define MT8135_PIN_202_MSDC3_DAT0__FUNC_CLKM2 (MTK_PIN_NO(202) | 5) - -#endif /* __DTS_MT8135_PINFUNC_H */ diff --git a/sys/gnu/dts/arm/mt8135.dtsi b/sys/gnu/dts/arm/mt8135.dtsi deleted file mode 100644 index 0e4e835026d..00000000000 --- a/sys/gnu/dts/arm/mt8135.dtsi +++ /dev/null @@ -1,260 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2014 MediaTek Inc. - * Author: Joe.C - * - */ - -#include -#include -#include -#include -#include "mt8135-pinfunc.h" - -/ { - #address-cells = <2>; - #size-cells = <2>; - compatible = "mediatek,mt8135"; - interrupt-parent = <&sysirq>; - - cpu-map { - cluster0 { - core0 { - cpu = <&cpu0>; - }; - core1 { - cpu = <&cpu1>; - }; - }; - - cluster1 { - core0 { - cpu = <&cpu2>; - }; - core1 { - cpu = <&cpu3>; - }; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "mediatek,mt81xx-tz-smp"; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x000>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x001>; - }; - - cpu2: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x100>; - }; - - cpu3: cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x101>; - }; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - trustzone-bootinfo@80002000 { - compatible = "mediatek,trustzone-bootinfo"; - reg = <0 0x80002000 0 0x1000>; - }; - }; - - clocks { - #address-cells = <2>; - #size-cells = <2>; - compatible = "simple-bus"; - ranges; - - system_clk: dummy13m { - compatible = "fixed-clock"; - clock-frequency = <13000000>; - #clock-cells = <0>; - }; - - rtc_clk: dummy32k { - compatible = "fixed-clock"; - clock-frequency = <32000>; - #clock-cells = <0>; - }; - - clk26m: clk26m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <26000000>; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupt-parent = <&gic>; - interrupts = , - , - , - ; - clock-frequency = <13000000>; - arm,cpu-registers-not-fw-configured; - }; - - soc { - #address-cells = <2>; - #size-cells = <2>; - compatible = "simple-bus"; - ranges; - - topckgen: topckgen@10000000 { - compatible = "mediatek,mt8135-topckgen"; - reg = <0 0x10000000 0 0x1000>; - #clock-cells = <1>; - }; - - infracfg: infracfg@10001000 { - #reset-cells = <1>; - #clock-cells = <1>; - compatible = "mediatek,mt8135-infracfg", "syscon"; - reg = <0 0x10001000 0 0x1000>; - }; - - pericfg: pericfg@10003000 { - #reset-cells = <1>; - #clock-cells = <1>; - compatible = "mediatek,mt8135-pericfg", "syscon"; - reg = <0 0x10003000 0 0x1000>; - }; - - /* - * Pinctrl access register at 0x10005000 and 0x1020c000 through - * regmap. Register 0x1000b000 is used by EINT. - */ - pio: pinctrl@10005000 { - compatible = "mediatek,mt8135-pinctrl"; - reg = <0 0x1000b000 0 0x1000>; - mediatek,pctl-regmap = <&syscfg_pctl_a &syscfg_pctl_b>; - pins-are-numbered; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = , - , - ; - }; - - syscfg_pctl_a: syscfg_pctl_a@10005000 { - compatible = "mediatek,mt8135-pctl-a-syscfg", "syscon"; - reg = <0 0x10005000 0 0x1000>; - }; - - timer: timer@10008000 { - compatible = "mediatek,mt8135-timer", - "mediatek,mt6577-timer"; - reg = <0 0x10008000 0 0x80>; - interrupts = ; - clocks = <&system_clk>, <&rtc_clk>; - clock-names = "system-clk", "rtc-clk"; - }; - - pwrap: pwrap@1000f000 { - compatible = "mediatek,mt8135-pwrap"; - reg = <0 0x1000f000 0 0x1000>, - <0 0x11017000 0 0x1000>; - reg-names = "pwrap", "pwrap-bridge"; - interrupts = ; - resets = <&infracfg MT8135_INFRA_PMIC_WRAP_RST>, - <&pericfg MT8135_PERI_PWRAP_BRIDGE_SW_RST>; - reset-names = "pwrap", "pwrap-bridge"; - clocks = <&clk26m>, <&clk26m>; - clock-names = "spi", "wrap"; - }; - - sysirq: interrupt-controller@10200030 { - compatible = "mediatek,mt8135-sysirq", - "mediatek,mt6577-sysirq"; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - reg = <0 0x10200030 0 0x1c>; - }; - - apmixedsys: apmixedsys@10209000 { - compatible = "mediatek,mt8135-apmixedsys"; - reg = <0 0x10209000 0 0x1000>; - #clock-cells = <1>; - }; - - syscfg_pctl_b: syscfg_pctl_b@1020c000 { - compatible = "mediatek,mt8135-pctl-b-syscfg", "syscon"; - reg = <0 0x1020c000 0 0x1000>; - }; - - gic: interrupt-controller@10211000 { - compatible = "arm,cortex-a15-gic"; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - reg = <0 0x10211000 0 0x1000>, - <0 0x10212000 0 0x2000>, - <0 0x10214000 0 0x2000>, - <0 0x10216000 0 0x2000>; - }; - - uart0: serial@11006000 { - compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart"; - reg = <0 0x11006000 0 0x400>; - interrupts = ; - clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>; - clock-names = "baud", "bus"; - status = "disabled"; - }; - - uart1: serial@11007000 { - compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart"; - reg = <0 0x11007000 0 0x400>; - interrupts = ; - clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>; - clock-names = "baud", "bus"; - status = "disabled"; - }; - - uart2: serial@11008000 { - compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart"; - reg = <0 0x11008000 0 0x400>; - interrupts = ; - clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>; - clock-names = "baud", "bus"; - status = "disabled"; - }; - - uart3: serial@11009000 { - compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart"; - reg = <0 0x11009000 0 0x400>; - interrupts = ; - clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>; - clock-names = "baud", "bus"; - status = "disabled"; - }; - - }; -}; diff --git a/sys/gnu/dts/arm/mvebu-linkstation-fan.dtsi b/sys/gnu/dts/arm/mvebu-linkstation-fan.dtsi deleted file mode 100644 index e172029a0c4..00000000000 --- a/sys/gnu/dts/arm/mvebu-linkstation-fan.dtsi +++ /dev/null @@ -1,72 +0,0 @@ -/* - * Device Tree common file for gpio-fan on Buffalo Linkstation - * - * Copyright (C) 2015, 2016 - * Roger Shimizu - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/ { - gpio_fan { - compatible = "gpio-fan"; - pinctrl-0 = <&pmx_fan_low &pmx_fan_high &pmx_fan_lock>; - pinctrl-names = "default"; - - gpio-fan,speed-map = - <0 3 - 1500 2 - 3250 1 - 5000 0>; - }; -}; - -&pinctrl { - pmx_fan_low: pmx-fan-low { - marvell,function = "gpio"; - }; - - pmx_fan_high: pmx-fan-high { - marvell,function = "gpio"; - }; - - pmx_fan_lock: pmx-fan-lock { - marvell,function = "gpio"; - }; -}; diff --git a/sys/gnu/dts/arm/mvebu-linkstation-gpio-simple.dtsi b/sys/gnu/dts/arm/mvebu-linkstation-gpio-simple.dtsi deleted file mode 100644 index c2d87ba6190..00000000000 --- a/sys/gnu/dts/arm/mvebu-linkstation-gpio-simple.dtsi +++ /dev/null @@ -1,105 +0,0 @@ -/* - * Device Tree common file for gpio-{keys,leds} on Buffalo Linkstation - * - * Copyright (C) 2015, 2016 - * Roger Shimizu - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include - -/ { - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_power_switch>; - pinctrl-names = "default"; - - power-on-switch { - label = "Power-on Switch"; - linux,code = ; - linux,input-type = <5>; - }; - - power-auto-switch { - label = "Power-auto Switch"; - linux,code = ; - linux,input-type = <5>; - }; - }; - - gpio_leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_led_power &pmx_led_alarm &pmx_led_info>; - pinctrl-names = "default"; - - blue-power-led { - label = "linkstation:blue:power"; - default-state = "keep"; - }; - - red-alarm-led { - label = "linkstation:red:alarm"; - }; - - amber-info-led { - label = "linkstation:amber:info"; - }; - }; -}; - -&pinctrl { - pmx_power_switch: pmx-power-switch { - marvell,function = "gpio"; - }; - - pmx_led_power: pmx-leds { - marvell,function = "gpio"; - }; - - pmx_led_alarm: pmx-leds { - marvell,function = "gpio"; - }; - - pmx_led_info: pmx-leds { - marvell,function = "gpio"; - }; -}; diff --git a/sys/gnu/dts/arm/mxs-pinfunc.h b/sys/gnu/dts/arm/mxs-pinfunc.h deleted file mode 100644 index c6da987b20c..00000000000 --- a/sys/gnu/dts/arm/mxs-pinfunc.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * Header providing constants for i.MX28 pinctrl bindings. - * - * Copyright (C) 2013 Lothar Waßmann - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#ifndef __DT_BINDINGS_MXS_PINCTRL_H__ -#define __DT_BINDINGS_MXS_PINCTRL_H__ - -/* fsl,drive-strength property */ -#define MXS_DRIVE_4mA 0 -#define MXS_DRIVE_8mA 1 -#define MXS_DRIVE_12mA 2 -#define MXS_DRIVE_16mA 3 - -/* fsl,voltage property */ -#define MXS_VOLTAGE_LOW 0 -#define MXS_VOLTAGE_HIGH 1 - -/* fsl,pull-up property */ -#define MXS_PULL_DISABLE 0 -#define MXS_PULL_ENABLE 1 - -#endif /* __DT_BINDINGS_MXS_PINCTRL_H__ */ diff --git a/sys/gnu/dts/arm/nspire-classic.dtsi b/sys/gnu/dts/arm/nspire-classic.dtsi deleted file mode 100644 index 41744cc2bc7..00000000000 --- a/sys/gnu/dts/arm/nspire-classic.dtsi +++ /dev/null @@ -1,88 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * linux/arch/arm/boot/nspire-classic.dts - * - * Copyright (C) 2013 Daniel Tang - */ - -/include/ "nspire.dtsi" - -&lcd { - port { - clcd_pads: endpoint { - remote-endpoint = <&panel_in>; - }; - }; -}; - -&fast_timer { - /* compatible = "lsi,zevio-timer"; */ - reg = <0x90010000 0x1000>, <0x900A0010 0x8>; -}; - -&uart { - compatible = "ns16550"; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&apb_pclk>; - no-loopback-test; -}; - -&timer0 { - /* compatible = "lsi,zevio-timer"; */ - reg = <0x900C0000 0x1000>, <0x900A0018 0x8>; -}; - -&timer1 { - compatible = "lsi,zevio-timer"; - reg = <0x900D0000 0x1000>, <0x900A0020 0x8>; -}; - -&keypad { - active-low; - -}; - -&base_clk { - compatible = "lsi,nspire-classic-clock"; -}; - -&ahb_clk { - compatible = "lsi,nspire-classic-ahb-divider"; -}; - - -&vbus_reg { - gpio = <&gpio 5 0>; -}; - -/ { - memory { - device_type = "memory"; - reg = <0x10000000 0x2000000>; /* 32 MB */ - }; - - ahb { - #address-cells = <1>; - #size-cells = <1>; - - intc: interrupt-controller@DC000000 { - compatible = "lsi,zevio-intc"; - interrupt-controller; - reg = <0xDC000000 0x1000>; - #interrupt-cells = <1>; - }; - }; - - panel { - compatible = "ti,nspire-classic-lcd-panel"; - port { - panel_in: endpoint { - remote-endpoint = <&clcd_pads>; - }; - }; - }; - chosen { - bootargs = "debug earlyprintk console=tty0 console=ttyS0,115200n8 root=/dev/ram0"; - }; -}; diff --git a/sys/gnu/dts/arm/nspire-clp.dts b/sys/gnu/dts/arm/nspire-clp.dts deleted file mode 100644 index f52f38c6158..00000000000 --- a/sys/gnu/dts/arm/nspire-clp.dts +++ /dev/null @@ -1,41 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * linux/arch/arm/boot/nspire-clp.dts - * - * Copyright (C) 2013 Daniel Tang - */ -/dts-v1/; - -/include/ "nspire-classic.dtsi" - -&keypad { - linux,keymap = < - 0x0000001c 0x0001001c 0x00020039 - 0x0004002c 0x00050034 0x00060015 - 0x0007000b 0x0008002d 0x01000033 - 0x0101004e 0x01020011 0x01030004 - 0x0104002f 0x01050003 0x01060016 - 0x01070002 0x01080014 0x02000062 - 0x0201000c 0x0202001f 0x02030007 - 0x02040013 0x02050006 0x02060010 - 0x02070005 0x02080019 0x03000027 - 0x03010037 0x03020018 0x0303000a - 0x03040031 0x03050009 0x03060032 - 0x03070008 0x03080026 0x04000028 - 0x04010035 0x04020025 0x04040024 - 0x04060017 0x04080023 0x05000028 - 0x05020022 0x0503001b 0x05040021 - 0x0505001a 0x05060012 0x0507006f - 0x05080020 0x0509002a 0x0601001c - 0x0602002e 0x06030068 0x06040030 - 0x0605006d 0x0606001e 0x06070001 - 0x0608002b 0x0609000f 0x07000067 - 0x0702006a 0x0704006c 0x07060069 - 0x0707000e 0x0708001d 0x070a000d - >; -}; - -/ { - model = "TI-NSPIRE Clickpad"; - compatible = "ti,nspire-clp"; -}; diff --git a/sys/gnu/dts/arm/nspire-cx.dts b/sys/gnu/dts/arm/nspire-cx.dts deleted file mode 100644 index 0c16b04e274..00000000000 --- a/sys/gnu/dts/arm/nspire-cx.dts +++ /dev/null @@ -1,125 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * linux/arch/arm/boot/nspire-cx.dts - * - * Copyright (C) 2013 Daniel Tang - */ -/dts-v1/; - -/include/ "nspire.dtsi" - -&lcd { - port { - clcd_pads: endpoint { - remote-endpoint = <&panel_in>; - }; - }; -}; - -&fast_timer { - /* compatible = "arm,sp804", "arm,primecell"; */ -}; - -&uart { - compatible = "arm,pl011", "arm,primecell"; - - clocks = <&uart_clk>, <&apb_pclk>; - clock-names = "uart_clk", "apb_pclk"; -}; - -&timer0 { - compatible = "arm,sp804", "arm,primecell"; -}; - -&timer1 { - compatible = "arm,sp804", "arm,primecell"; -}; - -&base_clk { - compatible = "lsi,nspire-cx-clock"; -}; - -&ahb_clk { - compatible = "lsi,nspire-cx-ahb-divider"; -}; - -&keypad { - linux,keymap = < - 0x0000001c 0x0001001c 0x00040039 - 0x0005002c 0x00060015 0x0007000b - 0x0008000f 0x0100002d 0x01010011 - 0x0102002f 0x01030004 0x01040016 - 0x01050014 0x0106001f 0x01070002 - 0x010a006a 0x02000013 0x02010010 - 0x02020019 0x02030007 0x02040018 - 0x02050031 0x02060032 0x02070005 - 0x02080028 0x0209006c 0x03000026 - 0x03010025 0x03020024 0x0303000a - 0x03040017 0x03050023 0x03060022 - 0x03070008 0x03080035 0x03090069 - 0x04000021 0x04010012 0x04020020 - 0x0404002e 0x04050030 0x0406001e - 0x0407000d 0x04080037 0x04090067 - 0x05010038 0x0502000c 0x0503001b - 0x05040034 0x0505001a 0x05060006 - 0x05080027 0x0509000e 0x050a006f - 0x0600002b 0x0602004e 0x06030068 - 0x06040003 0x0605006d 0x06060009 - 0x06070001 0x0609000f 0x0708002a - 0x0709001d 0x070a0033 >; -}; - -&vbus_reg { - gpio = <&gpio 2 0>; -}; - -/ { - model = "TI-NSPIRE CX"; - compatible = "ti,nspire-cx"; - - memory { - device_type = "memory"; - reg = <0x10000000 0x4000000>; /* 64 MB */ - }; - - uart_clk: uart_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <12000000>; - }; - - ahb { - #address-cells = <1>; - #size-cells = <1>; - - intc: interrupt-controller@DC000000 { - compatible = "arm,pl190-vic"; - interrupt-controller; - reg = <0xDC000000 0x1000>; - #interrupt-cells = <1>; - }; - - apb@90000000 { - #address-cells = <1>; - #size-cells = <1>; - - i2c@90050000 { - compatible = "snps,designware-i2c"; - reg = <0x90050000 0x1000>; - interrupts = <20>; - }; - }; - }; - - panel { - compatible = "ti,nspire-cx-lcd-panel"; - port { - panel_in: endpoint { - remote-endpoint = <&clcd_pads>; - }; - }; - }; - chosen { - bootargs = "debug earlyprintk console=tty0 console=ttyAMA0,115200n8 root=/dev/ram0"; - }; -}; diff --git a/sys/gnu/dts/arm/nspire-tp.dts b/sys/gnu/dts/arm/nspire-tp.dts deleted file mode 100644 index f7d0faacd4c..00000000000 --- a/sys/gnu/dts/arm/nspire-tp.dts +++ /dev/null @@ -1,40 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * linux/arch/arm/boot/nspire-tp.dts - * - * Copyright (C) 2013 Daniel Tang - */ -/dts-v1/; - -/include/ "nspire-classic.dtsi" - -&keypad { - linux,keymap = < - 0x0000001c 0x0001001c 0x00040039 - 0x0005002c 0x00060015 0x0007000b - 0x0008000f 0x0100002d 0x01010011 - 0x0102002f 0x01030004 0x01040016 - 0x01050014 0x0106001f 0x01070002 - 0x010a006a 0x02000013 0x02010010 - 0x02020019 0x02030007 0x02040018 - 0x02050031 0x02060032 0x02070005 - 0x02080028 0x0209006c 0x03000026 - 0x03010025 0x03020024 0x0303000a - 0x03040017 0x03050023 0x03060022 - 0x03070008 0x03080035 0x03090069 - 0x04000021 0x04010012 0x04020020 - 0x0404002e 0x04050030 0x0406001e - 0x0407000d 0x04080037 0x04090067 - 0x05010038 0x0502000c 0x0503001b - 0x05040034 0x0505001a 0x05060006 - 0x05080027 0x0509000e 0x050a006f - 0x0600002b 0x0602004e 0x06030068 - 0x06040003 0x0605006d 0x06060009 - 0x06070001 0x0609000f 0x0708002a - 0x0709001d 0x070a0033 >; -}; - -/ { - model = "TI-NSPIRE Touchpad"; - compatible = "ti,nspire-tp"; -}; diff --git a/sys/gnu/dts/arm/nspire.dtsi b/sys/gnu/dts/arm/nspire.dtsi deleted file mode 100644 index d9a0fd7524d..00000000000 --- a/sys/gnu/dts/arm/nspire.dtsi +++ /dev/null @@ -1,199 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * linux/arch/arm/boot/nspire.dtsi - * - * Copyright (C) 2013 Daniel Tang - */ - -/ { - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&intc>; - - cpus { - cpu@0 { - compatible = "arm,arm926ej-s"; - }; - }; - - bootrom: bootrom@0 { - reg = <0x00000000 0x80000>; - }; - - sram: sram@A4000000 { - device = "memory"; - reg = <0xA4000000 0x20000>; - }; - - timer_clk: timer_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - base_clk: base_clk { - #clock-cells = <0>; - reg = <0x900B0024 0x4>; - }; - - ahb_clk: ahb_clk { - #clock-cells = <0>; - reg = <0x900B0024 0x4>; - clocks = <&base_clk>; - }; - - apb_pclk: apb_pclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <2>; - clock-mult = <1>; - clocks = <&ahb_clk>; - }; - - usb_phy: usb_phy { - compatible = "usb-nop-xceiv"; - #phy-cells = <0>; - }; - - vbus_reg: vbus_reg { - compatible = "regulator-fixed"; - - regulator-name = "USB VBUS output"; - regulator-type = "voltage"; - - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - ahb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - spi: spi@A9000000 { - reg = <0xA9000000 0x1000>; - }; - - usb0: usb@B0000000 { - compatible = "lsi,zevio-usb"; - reg = <0xB0000000 0x1000>; - interrupts = <8>; - - usb-phy = <&usb_phy>; - vbus-supply = <&vbus_reg>; - }; - - usb1: usb@B4000000 { - reg = <0xB4000000 0x1000>; - interrupts = <9>; - status = "disabled"; - }; - - lcd: lcd@C0000000 { - compatible = "arm,pl111", "arm,primecell"; - reg = <0xC0000000 0x1000>; - interrupts = <21>; - - /* - * We assume the same clock is fed to APB and CLCDCLK. - * There is some code to scale the clock down by a factor - * 48 for the display so likely the frequency to the - * display is 1MHz and the CLCDCLK is 48 MHz. - */ - clocks = <&apb_pclk>, <&apb_pclk>; - clock-names = "clcdclk", "apb_pclk"; - }; - - adc: adc@C4000000 { - reg = <0xC4000000 0x1000>; - interrupts = <11>; - }; - - tdes: crypto@C8010000 { - reg = <0xC8010000 0x1000>; - }; - - sha256: crypto@CC000000 { - reg = <0xCC000000 0x1000>; - }; - - apb@90000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - clock-ranges; - ranges; - - gpio: gpio@90000000 { - compatible = "lsi,zevio-gpio"; - reg = <0x90000000 0x1000>; - interrupts = <7>; - gpio-controller; - #gpio-cells = <2>; - }; - - fast_timer: timer@90010000 { - reg = <0x90010000 0x1000>; - interrupts = <17>; - }; - - uart: serial@90020000 { - reg = <0x90020000 0x1000>; - interrupts = <1>; - }; - - timer0: timer@900C0000 { - reg = <0x900C0000 0x1000>; - - clocks = <&timer_clk>; - }; - - timer1: timer@900D0000 { - reg = <0x900D0000 0x1000>; - interrupts = <19>; - - clocks = <&timer_clk>; - }; - - watchdog: watchdog@90060000 { - compatible = "arm,amba-primecell"; - reg = <0x90060000 0x1000>; - interrupts = <3>; - }; - - rtc: rtc@90090000 { - reg = <0x90090000 0x1000>; - interrupts = <4>; - }; - - misc: misc@900A0000 { - reg = <0x900A0000 0x1000>; - }; - - pwr: pwr@900B0000 { - reg = <0x900B0000 0x1000>; - interrupts = <15>; - }; - - keypad: input@900E0000 { - compatible = "ti,nspire-keypad"; - reg = <0x900E0000 0x1000>; - interrupts = <16>; - - scan-interval = <1000>; - row-delay = <200>; - - clocks = <&apb_pclk>; - }; - - contrast: contrast@900F0000 { - reg = <0x900F0000 0x1000>; - }; - - led: led@90110000 { - reg = <0x90110000 0x1000>; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/nuvoton-common-npcm7xx.dtsi b/sys/gnu/dts/arm/nuvoton-common-npcm7xx.dtsi deleted file mode 100644 index d2d0761295a..00000000000 --- a/sys/gnu/dts/arm/nuvoton-common-npcm7xx.dtsi +++ /dev/null @@ -1,187 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (c) 2018 Nuvoton Technology tomer.maimon@nuvoton.com -// Copyright 2018 Google, Inc. - -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&gic>; - - /* external reference clock */ - clk_refclk: clk_refclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - clock-output-names = "refclk"; - }; - - /* external reference clock for cpu. float in normal operation */ - clk_sysbypck: clk_sysbypck { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <800000000>; - clock-output-names = "sysbypck"; - }; - - /* external reference clock for MC. float in normal operation */ - clk_mcbypck: clk_mcbypck { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <800000000>; - clock-output-names = "mcbypck"; - }; - - /* external clock signal rg1refck, supplied by the phy */ - clk_rg1refck: clk_rg1refck { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <125000000>; - clock-output-names = "clk_rg1refck"; - }; - - /* external clock signal rg2refck, supplied by the phy */ - clk_rg2refck: clk_rg2refck { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <125000000>; - clock-output-names = "clk_rg2refck"; - }; - - clk_xin: clk_xin { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <50000000>; - clock-output-names = "clk_xin"; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&gic>; - ranges = <0x0 0xf0000000 0x00900000>; - - gcr: gcr@800000 { - compatible = "nuvoton,npcm750-gcr", "syscon", - "simple-mfd"; - reg = <0x800000 0x1000>; - }; - - scu: scu@3fe000 { - compatible = "arm,cortex-a9-scu"; - reg = <0x3fe000 0x1000>; - }; - - l2: cache-controller@3fc000 { - compatible = "arm,pl310-cache"; - reg = <0x3fc000 0x1000>; - interrupts = ; - cache-unified; - cache-level = <2>; - clocks = <&clk 10>; - arm,shared-override; - }; - - gic: interrupt-controller@3ff000 { - compatible = "arm,cortex-a9-gic"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0x3ff000 0x1000>, - <0x3fe100 0x100>; - }; - }; - - ahb { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&gic>; - ranges; - - clk: clock-controller@f0801000 { - compatible = "nuvoton,npcm750-clk", "syscon"; - #clock-cells = <1>; - clock-controller; - reg = <0xf0801000 0x1000>; - clock-names = "refclk", "sysbypck", "mcbypck"; - clocks = <&clk_refclk>, <&clk_sysbypck>, <&clk_mcbypck>; - }; - - apb { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&gic>; - ranges = <0x0 0xf0000000 0x00300000>; - - timer0: timer@8000 { - compatible = "nuvoton,npcm750-timer"; - interrupts = ; - reg = <0x8000 0x50>; - clocks = <&clk 5>; - }; - - watchdog0: watchdog@801C { - compatible = "nuvoton,npcm750-wdt"; - interrupts = ; - reg = <0x801C 0x4>; - status = "disabled"; - clocks = <&clk 5>; - }; - - watchdog1: watchdog@901C { - compatible = "nuvoton,npcm750-wdt"; - interrupts = ; - reg = <0x901C 0x4>; - status = "disabled"; - clocks = <&clk 5>; - }; - - watchdog2: watchdog@a01C { - compatible = "nuvoton,npcm750-wdt"; - interrupts = ; - reg = <0xa01C 0x4>; - status = "disabled"; - clocks = <&clk 5>; - }; - - serial0: serial@1000 { - compatible = "nuvoton,npcm750-uart"; - reg = <0x1000 0x1000>; - clocks = <&clk 6>; - interrupts = ; - reg-shift = <2>; - status = "disabled"; - }; - - serial1: serial@2000 { - compatible = "nuvoton,npcm750-uart"; - reg = <0x2000 0x1000>; - clocks = <&clk 6>; - interrupts = ; - reg-shift = <2>; - status = "disabled"; - }; - - serial2: serial@3000 { - compatible = "nuvoton,npcm750-uart"; - reg = <0x3000 0x1000>; - clocks = <&clk 6>; - interrupts = ; - reg-shift = <2>; - status = "disabled"; - }; - - serial3: serial@4000 { - compatible = "nuvoton,npcm750-uart"; - reg = <0x4000 0x1000>; - clocks = <&clk 6>; - interrupts = ; - reg-shift = <2>; - status = "disabled"; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/nuvoton-npcm750-evb.dts b/sys/gnu/dts/arm/nuvoton-npcm750-evb.dts deleted file mode 100644 index 15f744f1bee..00000000000 --- a/sys/gnu/dts/arm/nuvoton-npcm750-evb.dts +++ /dev/null @@ -1,39 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (c) 2018 Nuvoton Technology tomer.maimon@nuvoton.com -// Copyright 2018 Google, Inc. - -/dts-v1/; -#include "nuvoton-npcm750.dtsi" - -/ { - model = "Nuvoton npcm750 Development Board (Device Tree)"; - compatible = "nuvoton,npcm750"; - - chosen { - stdout-path = &serial3; - }; - - memory { - reg = <0 0x40000000>; - }; -}; - -&watchdog1 { - status = "okay"; -}; - -&serial0 { - status = "okay"; -}; - -&serial1 { - status = "okay"; -}; - -&serial2 { - status = "okay"; -}; - -&serial3 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/nuvoton-npcm750.dtsi b/sys/gnu/dts/arm/nuvoton-npcm750.dtsi deleted file mode 100644 index 6ac34053358..00000000000 --- a/sys/gnu/dts/arm/nuvoton-npcm750.dtsi +++ /dev/null @@ -1,44 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (c) 2018 Nuvoton Technology tomer.maimon@nuvoton.com -// Copyright 2018 Google, Inc. - -#include "nuvoton-common-npcm7xx.dtsi" - -/ { - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&gic>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "nuvoton,npcm750-smp"; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - clocks = <&clk 0>; - clock-names = "clk_cpu"; - reg = <0>; - next-level-cache = <&l2>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - clocks = <&clk 0>; - clock-names = "clk_cpu"; - reg = <1>; - next-level-cache = <&l2>; - }; - }; - soc { - timer@3fe600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0x3fe600 0x20>; - interrupts = ; - clocks = <&clk 5>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/omap-gpmc-smsc911x.dtsi b/sys/gnu/dts/arm/omap-gpmc-smsc911x.dtsi deleted file mode 100644 index ded7e8fec9e..00000000000 --- a/sys/gnu/dts/arm/omap-gpmc-smsc911x.dtsi +++ /dev/null @@ -1,55 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Common file for GPMC connected smsc911x on omaps - * - * Note that the board specifc DTS file needs to specify - * ranges, pinctrl, reg, interrupt parent and interrupts. - */ - -/ { - vddvario: regulator-vddvario { - compatible = "regulator-fixed"; - regulator-name = "vddvario"; - regulator-always-on; - }; - - vdd33a: regulator-vdd33a { - compatible = "regulator-fixed"; - regulator-name = "vdd33a"; - regulator-always-on; - }; -}; - -&gpmc { - ethernet@gpmc { - compatible = "smsc,lan9221", "smsc,lan9115"; - bank-width = <2>; - gpmc,device-width = <1>; - gpmc,cycle2cycle-samecsen = <1>; - gpmc,cycle2cycle-diffcsen = <1>; - gpmc,cs-on-ns = <5>; - gpmc,cs-rd-off-ns = <150>; - gpmc,cs-wr-off-ns = <150>; - gpmc,adv-on-ns = <0>; - gpmc,adv-rd-off-ns = <15>; - gpmc,adv-wr-off-ns = <40>; - gpmc,oe-on-ns = <45>; - gpmc,oe-off-ns = <140>; - gpmc,we-on-ns = <45>; - gpmc,we-off-ns = <140>; - gpmc,rd-cycle-ns = <155>; - gpmc,wr-cycle-ns = <155>; - gpmc,access-ns = <120>; - gpmc,page-burst-access-ns = <20>; - gpmc,bus-turnaround-ns = <75>; - gpmc,cycle2cycle-delay-ns = <75>; - gpmc,wait-monitoring-ns = <0>; - gpmc,clk-activation-ns = <0>; - gpmc,wr-data-mux-bus-ns = <0>; - gpmc,wr-access-ns = <0>; - vddvario-supply = <&vddvario>; - vdd33a-supply = <&vdd33a>; - reg-io-width = <4>; - smsc,save-mac-address; - }; -}; diff --git a/sys/gnu/dts/arm/omap-gpmc-smsc9221.dtsi b/sys/gnu/dts/arm/omap-gpmc-smsc9221.dtsi deleted file mode 100644 index 7f6aefd1345..00000000000 --- a/sys/gnu/dts/arm/omap-gpmc-smsc9221.dtsi +++ /dev/null @@ -1,59 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Common file for GPMC connected smsc9221 on omaps - * - * Compared to smsc911x, smsc9221 (and others like smsc9217 - * or smsc 9218) has faster timings, leading to higher - * bandwidth. - * - * Note that the board specifc DTS file needs to specify - * ranges, pinctrl, reg, interrupt parent and interrupts. - */ - -/ { - vddvario: regulator-vddvario { - compatible = "regulator-fixed"; - regulator-name = "vddvario"; - regulator-always-on; - }; - - vdd33a: regulator-vdd33a { - compatible = "regulator-fixed"; - regulator-name = "vdd33a"; - regulator-always-on; - }; -}; - -&gpmc { - ethernet@gpmc { - compatible = "smsc,lan9221","smsc,lan9115"; - bank-width = <2>; - - gpmc,mux-add-data; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <42>; - gpmc,cs-wr-off-ns = <36>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <12>; - gpmc,adv-wr-off-ns = <12>; - gpmc,oe-on-ns = <0>; - gpmc,oe-off-ns = <42>; - gpmc,we-on-ns = <0>; - gpmc,we-off-ns = <36>; - gpmc,rd-cycle-ns = <60>; - gpmc,wr-cycle-ns = <54>; - gpmc,access-ns = <36>; - gpmc,page-burst-access-ns = <0>; - gpmc,bus-turnaround-ns = <0>; - gpmc,cycle2cycle-delay-ns = <0>; - gpmc,wr-data-mux-bus-ns = <18>; - gpmc,wr-access-ns = <42>; - gpmc,cycle2cycle-samecsen; - gpmc,cycle2cycle-diffcsen; - - vddvario-supply = <&vddvario>; - vdd33a-supply = <&vdd33a>; - reg-io-width = <4>; - smsc,save-mac-address; - }; -}; diff --git a/sys/gnu/dts/arm/omap-zoom-common.dtsi b/sys/gnu/dts/arm/omap-zoom-common.dtsi deleted file mode 100644 index d4ad9e58b19..00000000000 --- a/sys/gnu/dts/arm/omap-zoom-common.dtsi +++ /dev/null @@ -1,92 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Common features on the Zoom debug board - */ - -#include "omap-gpmc-smsc911x.dtsi" - -&gpmc { - ranges = <3 0 0x10000000 0x1000000>, /* CS3: 16MB for UART */ - <7 0 0x2c000000 0x01000000>; - - /* - * Four port TL16CP754C serial port on GPMC, - * they probably share the same GPIO IRQ - * REVISIT: Add timing support from slls644g.pdf - */ - uart@3,0 { - compatible = "ns16550a"; - reg = <3 0 8>; /* CS3, offset 0, IO size 8 */ - bank-width = <2>; - reg-shift = <1>; - reg-io-width = <1>; - interrupt-parent = <&gpio4>; - interrupts = <6 IRQ_TYPE_EDGE_RISING>; /* gpio102 */ - clock-frequency = <1843200>; - current-speed = <115200>; - gpmc,mux-add-data = <0>; - gpmc,device-width = <1>; - gpmc,wait-pin = <1>; - gpmc,cycle2cycle-samecsen = <1>; - gpmc,cycle2cycle-diffcsen = <1>; - gpmc,cs-on-ns = <5>; - gpmc,cs-rd-off-ns = <155>; - gpmc,cs-wr-off-ns = <155>; - gpmc,adv-on-ns = <15>; - gpmc,adv-rd-off-ns = <40>; - gpmc,adv-wr-off-ns = <40>; - gpmc,oe-on-ns = <45>; - gpmc,oe-off-ns = <145>; - gpmc,we-on-ns = <45>; - gpmc,we-off-ns = <145>; - gpmc,rd-cycle-ns = <155>; - gpmc,wr-cycle-ns = <155>; - gpmc,access-ns = <145>; - gpmc,page-burst-access-ns = <20>; - gpmc,bus-turnaround-ns = <20>; - gpmc,cycle2cycle-delay-ns = <20>; - gpmc,wait-monitoring-ns = <0>; - gpmc,clk-activation-ns = <0>; - gpmc,wr-data-mux-bus-ns = <45>; - gpmc,wr-access-ns = <145>; - }; - uart@3,1 { - compatible = "ns16550a"; - reg = <3 0x100 8>; /* CS3, offset 0x100, IO size 8 */ - bank-width = <2>; - reg-shift = <1>; - reg-io-width = <1>; - interrupt-parent = <&gpio4>; - interrupts = <6 IRQ_TYPE_EDGE_RISING>; /* gpio102 */ - clock-frequency = <1843200>; - current-speed = <115200>; - }; - uart@3,2 { - compatible = "ns16550a"; - reg = <3 0x200 8>; /* CS3, offset 0x200, IO size 8 */ - bank-width = <2>; - reg-shift = <1>; - reg-io-width = <1>; - interrupt-parent = <&gpio4>; - interrupts = <6 IRQ_TYPE_EDGE_RISING>; /* gpio102 */ - clock-frequency = <1843200>; - current-speed = <115200>; - }; - uart@3,3 { - compatible = "ns16550a"; - reg = <3 0x300 8>; /* CS3, offset 0x300, IO size 8 */ - bank-width = <2>; - reg-shift = <1>; - reg-io-width = <1>; - interrupt-parent = <&gpio4>; - interrupts = <6 IRQ_TYPE_EDGE_RISING>; /* gpio102 */ - clock-frequency = <1843200>; - current-speed = <115200>; - }; - - ethernet@gpmc { - reg = <7 0 0xff>; - interrupt-parent = <&gpio5>; - interrupts = <30 IRQ_TYPE_LEVEL_LOW>; /* gpio158 */ - }; -}; diff --git a/sys/gnu/dts/arm/omap2.dtsi b/sys/gnu/dts/arm/omap2.dtsi deleted file mode 100644 index 000bf16de65..00000000000 --- a/sys/gnu/dts/arm/omap2.dtsi +++ /dev/null @@ -1,299 +0,0 @@ -/* - * Device Tree Source for OMAP2 SoC - * - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -#include -#include -#include - -/ { - compatible = "ti,omap2430", "ti,omap2420", "ti,omap2"; - interrupt-parent = <&intc>; - #address-cells = <1>; - #size-cells = <1>; - chosen { }; - - aliases { - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - i2c0 = &i2c1; - i2c1 = &i2c2; - }; - - cpus { - #address-cells = <0>; - #size-cells = <0>; - - cpu { - compatible = "arm,arm1136jf-s"; - device_type = "cpu"; - }; - }; - - pmu { - compatible = "arm,arm1136-pmu"; - interrupts = <3>; - }; - - soc { - compatible = "ti,omap-infra"; - mpu { - compatible = "ti,omap2-mpu"; - ti,hwmods = "mpu"; - }; - }; - - ocp { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - ti,hwmods = "l3_main"; - - aes: aes@480a6000 { - compatible = "ti,omap2-aes"; - ti,hwmods = "aes"; - reg = <0x480a6000 0x50>; - dmas = <&sdma 9 &sdma 10>; - dma-names = "tx", "rx"; - }; - - hdq1w: 1w@480b2000 { - compatible = "ti,omap2420-1w"; - ti,hwmods = "hdq1w"; - reg = <0x480b2000 0x1000>; - interrupts = <58>; - }; - - intc: interrupt-controller@1 { - compatible = "ti,omap2-intc"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x480FE000 0x1000>; - }; - - sdma: dma-controller@48056000 { - compatible = "ti,omap2430-sdma", "ti,omap2420-sdma"; - ti,hwmods = "dma"; - reg = <0x48056000 0x1000>; - interrupts = <12>, - <13>, - <14>, - <15>; - #dma-cells = <1>; - dma-channels = <32>; - dma-requests = <64>; - }; - - i2c1: i2c@48070000 { - compatible = "ti,omap2-i2c"; - ti,hwmods = "i2c1"; - reg = <0x48070000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <56>; - dmas = <&sdma 27 &sdma 28>; - dma-names = "tx", "rx"; - }; - - i2c2: i2c@48072000 { - compatible = "ti,omap2-i2c"; - ti,hwmods = "i2c2"; - reg = <0x48072000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <57>; - dmas = <&sdma 29 &sdma 30>; - dma-names = "tx", "rx"; - }; - - mcspi1: spi@48098000 { - compatible = "ti,omap2-mcspi"; - ti,hwmods = "mcspi1"; - reg = <0x48098000 0x100>; - interrupts = <65>; - dmas = <&sdma 35 &sdma 36 &sdma 37 &sdma 38 - &sdma 39 &sdma 40 &sdma 41 &sdma 42>; - dma-names = "tx0", "rx0", "tx1", "rx1", - "tx2", "rx2", "tx3", "rx3"; - }; - - mcspi2: spi@4809a000 { - compatible = "ti,omap2-mcspi"; - ti,hwmods = "mcspi2"; - reg = <0x4809a000 0x100>; - interrupts = <66>; - dmas = <&sdma 43 &sdma 44 &sdma 45 &sdma 46>; - dma-names = "tx0", "rx0", "tx1", "rx1"; - }; - - rng: rng@480a0000 { - compatible = "ti,omap2-rng"; - ti,hwmods = "rng"; - reg = <0x480a0000 0x50>; - interrupts = <52>; - }; - - sham: sham@480a4000 { - compatible = "ti,omap2-sham"; - ti,hwmods = "sham"; - reg = <0x480a4000 0x64>; - interrupts = <51>; - dmas = <&sdma 13>; - dma-names = "rx"; - }; - - uart1: serial@4806a000 { - compatible = "ti,omap2-uart"; - ti,hwmods = "uart1"; - reg = <0x4806a000 0x2000>; - interrupts = <72>; - dmas = <&sdma 49 &sdma 50>; - dma-names = "tx", "rx"; - clock-frequency = <48000000>; - }; - - uart2: serial@4806c000 { - compatible = "ti,omap2-uart"; - ti,hwmods = "uart2"; - reg = <0x4806c000 0x400>; - interrupts = <73>; - dmas = <&sdma 51 &sdma 52>; - dma-names = "tx", "rx"; - clock-frequency = <48000000>; - }; - - uart3: serial@4806e000 { - compatible = "ti,omap2-uart"; - ti,hwmods = "uart3"; - reg = <0x4806e000 0x400>; - interrupts = <74>; - dmas = <&sdma 53 &sdma 54>; - dma-names = "tx", "rx"; - clock-frequency = <48000000>; - }; - - timer2: timer@4802a000 { - compatible = "ti,omap2420-timer"; - reg = <0x4802a000 0x400>; - interrupts = <38>; - ti,hwmods = "timer2"; - }; - - timer3: timer@48078000 { - compatible = "ti,omap2420-timer"; - reg = <0x48078000 0x400>; - interrupts = <39>; - ti,hwmods = "timer3"; - }; - - timer4: timer@4807a000 { - compatible = "ti,omap2420-timer"; - reg = <0x4807a000 0x400>; - interrupts = <40>; - ti,hwmods = "timer4"; - }; - - timer5: timer@4807c000 { - compatible = "ti,omap2420-timer"; - reg = <0x4807c000 0x400>; - interrupts = <41>; - ti,hwmods = "timer5"; - ti,timer-dsp; - }; - - timer6: timer@4807e000 { - compatible = "ti,omap2420-timer"; - reg = <0x4807e000 0x400>; - interrupts = <42>; - ti,hwmods = "timer6"; - ti,timer-dsp; - }; - - timer7: timer@48080000 { - compatible = "ti,omap2420-timer"; - reg = <0x48080000 0x400>; - interrupts = <43>; - ti,hwmods = "timer7"; - ti,timer-dsp; - }; - - timer8: timer@48082000 { - compatible = "ti,omap2420-timer"; - reg = <0x48082000 0x400>; - interrupts = <44>; - ti,hwmods = "timer8"; - ti,timer-dsp; - }; - - timer9: timer@48084000 { - compatible = "ti,omap2420-timer"; - reg = <0x48084000 0x400>; - interrupts = <45>; - ti,hwmods = "timer9"; - ti,timer-pwm; - }; - - timer10: timer@48086000 { - compatible = "ti,omap2420-timer"; - reg = <0x48086000 0x400>; - interrupts = <46>; - ti,hwmods = "timer10"; - ti,timer-pwm; - }; - - timer11: timer@48088000 { - compatible = "ti,omap2420-timer"; - reg = <0x48088000 0x400>; - interrupts = <47>; - ti,hwmods = "timer11"; - ti,timer-pwm; - }; - - timer12: timer@4808a000 { - compatible = "ti,omap2420-timer"; - reg = <0x4808a000 0x400>; - interrupts = <48>; - ti,hwmods = "timer12"; - ti,timer-pwm; - }; - - dss: dss@48050000 { - compatible = "ti,omap2-dss"; - reg = <0x48050000 0x400>; - status = "disabled"; - ti,hwmods = "dss_core"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - dispc@48050400 { - compatible = "ti,omap2-dispc"; - reg = <0x48050400 0x400>; - interrupts = <25>; - ti,hwmods = "dss_dispc"; - }; - - rfbi: encoder@48050800 { - compatible = "ti,omap2-rfbi"; - reg = <0x48050800 0x400>; - status = "disabled"; - ti,hwmods = "dss_rfbi"; - }; - - venc: encoder@48050c00 { - compatible = "ti,omap2-venc"; - reg = <0x48050c00 0x400>; - status = "disabled"; - ti,hwmods = "dss_venc"; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/omap2420-clocks.dtsi b/sys/gnu/dts/arm/omap2420-clocks.dtsi deleted file mode 100644 index 00a7a199a91..00000000000 --- a/sys/gnu/dts/arm/omap2420-clocks.dtsi +++ /dev/null @@ -1,267 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Device Tree Source for OMAP2420 clock data - * - * Copyright (C) 2014 Texas Instruments, Inc. - */ - -&prcm_clocks { - sys_clkout2_src_gate: sys_clkout2_src_gate@70 { - #clock-cells = <0>; - compatible = "ti,composite-no-wait-gate-clock"; - clocks = <&core_ck>; - ti,bit-shift = <15>; - reg = <0x0070>; - }; - - sys_clkout2_src_mux: sys_clkout2_src_mux@70 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&core_ck>, <&sys_ck>, <&func_96m_ck>, <&func_54m_ck>; - ti,bit-shift = <8>; - reg = <0x0070>; - }; - - sys_clkout2_src: sys_clkout2_src { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&sys_clkout2_src_gate>, <&sys_clkout2_src_mux>; - }; - - sys_clkout2: sys_clkout2@70 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&sys_clkout2_src>; - ti,bit-shift = <11>; - ti,max-div = <64>; - reg = <0x0070>; - ti,index-power-of-two; - }; - - dsp_gate_ick: dsp_gate_ick@810 { - #clock-cells = <0>; - compatible = "ti,composite-interface-clock"; - clocks = <&dsp_fck>; - ti,bit-shift = <1>; - reg = <0x0810>; - }; - - dsp_div_ick: dsp_div_ick@840 { - #clock-cells = <0>; - compatible = "ti,composite-divider-clock"; - clocks = <&dsp_fck>; - ti,bit-shift = <5>; - ti,max-div = <3>; - reg = <0x0840>; - ti,index-starts-at-one; - }; - - dsp_ick: dsp_ick { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&dsp_gate_ick>, <&dsp_div_ick>; - }; - - iva1_gate_ifck: iva1_gate_ifck@800 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&core_ck>; - ti,bit-shift = <10>; - reg = <0x0800>; - }; - - iva1_div_ifck: iva1_div_ifck@840 { - #clock-cells = <0>; - compatible = "ti,composite-divider-clock"; - clocks = <&core_ck>; - ti,bit-shift = <8>; - reg = <0x0840>; - ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>, <0>, <0>, <0>, <12>; - }; - - iva1_ifck: iva1_ifck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&iva1_gate_ifck>, <&iva1_div_ifck>; - }; - - iva1_ifck_div: iva1_ifck_div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&iva1_ifck>; - clock-mult = <1>; - clock-div = <2>; - }; - - iva1_mpu_int_ifck: iva1_mpu_int_ifck@800 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&iva1_ifck_div>; - ti,bit-shift = <8>; - reg = <0x0800>; - }; - - wdt3_ick: wdt3_ick@210 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <28>; - reg = <0x0210>; - }; - - wdt3_fck: wdt3_fck@200 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&func_32k_ck>; - ti,bit-shift = <28>; - reg = <0x0200>; - }; - - mmc_ick: mmc_ick@210 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <26>; - reg = <0x0210>; - }; - - mmc_fck: mmc_fck@200 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&func_96m_ck>; - ti,bit-shift = <26>; - reg = <0x0200>; - }; - - eac_ick: eac_ick@210 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <24>; - reg = <0x0210>; - }; - - eac_fck: eac_fck@200 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&func_96m_ck>; - ti,bit-shift = <24>; - reg = <0x0200>; - }; - - i2c1_fck: i2c1_fck@200 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&func_12m_ck>; - ti,bit-shift = <19>; - reg = <0x0200>; - }; - - i2c2_fck: i2c2_fck@200 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&func_12m_ck>; - ti,bit-shift = <20>; - reg = <0x0200>; - }; - - vlynq_ick: vlynq_ick@210 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l3_ck>; - ti,bit-shift = <3>; - reg = <0x0210>; - }; - - vlynq_gate_fck: vlynq_gate_fck@200 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&core_ck>; - ti,bit-shift = <3>; - reg = <0x0200>; - }; - - core_d18_ck: core_d18_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&core_ck>; - clock-mult = <1>; - clock-div = <18>; - }; - - vlynq_mux_fck: vlynq_mux_fck@240 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&func_96m_ck>, <&core_ck>, <&core_d2_ck>, <&core_d3_ck>, <&core_d4_ck>, <&dummy_ck>, <&core_d6_ck>, <&dummy_ck>, <&core_d8_ck>, <&core_d9_ck>, <&dummy_ck>, <&dummy_ck>, <&core_d12_ck>, <&dummy_ck>, <&dummy_ck>, <&dummy_ck>, <&core_d16_ck>, <&dummy_ck>, <&core_d18_ck>; - ti,bit-shift = <15>; - reg = <0x0240>; - }; - - vlynq_fck: vlynq_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&vlynq_gate_fck>, <&vlynq_mux_fck>; - }; -}; - -&prcm_clockdomains { - gfx_clkdm: gfx_clkdm { - compatible = "ti,clockdomain"; - clocks = <&gfx_ick>; - }; - - core_l3_clkdm: core_l3_clkdm { - compatible = "ti,clockdomain"; - clocks = <&cam_fck>, <&vlynq_ick>, <&usb_fck>; - }; - - wkup_clkdm: wkup_clkdm { - compatible = "ti,clockdomain"; - clocks = <&dpll_ck>, <&emul_ck>, <&gpt1_ick>, <&gpios_ick>, - <&gpios_fck>, <&mpu_wdt_ick>, <&mpu_wdt_fck>, - <&sync_32k_ick>, <&wdt1_ick>, <&omapctrl_ick>; - }; - - iva1_clkdm: iva1_clkdm { - compatible = "ti,clockdomain"; - clocks = <&iva1_mpu_int_ifck>; - }; - - dss_clkdm: dss_clkdm { - compatible = "ti,clockdomain"; - clocks = <&dss_ick>, <&dss_54m_fck>; - }; - - core_l4_clkdm: core_l4_clkdm { - compatible = "ti,clockdomain"; - clocks = <&ssi_l4_ick>, <&gpt2_ick>, <&gpt3_ick>, <&gpt4_ick>, - <&gpt5_ick>, <&gpt6_ick>, <&gpt7_ick>, <&gpt8_ick>, - <&gpt9_ick>, <&gpt10_ick>, <&gpt11_ick>, <&gpt12_ick>, - <&mcbsp1_ick>, <&mcbsp2_ick>, <&mcspi1_ick>, - <&mcspi1_fck>, <&mcspi2_ick>, <&mcspi2_fck>, - <&uart1_ick>, <&uart1_fck>, <&uart2_ick>, <&uart2_fck>, - <&uart3_ick>, <&uart3_fck>, <&cam_ick>, - <&mailboxes_ick>, <&wdt4_ick>, <&wdt4_fck>, - <&wdt3_ick>, <&wdt3_fck>, <&mspro_ick>, <&mspro_fck>, - <&mmc_ick>, <&mmc_fck>, <&fac_ick>, <&fac_fck>, - <&eac_ick>, <&eac_fck>, <&hdq_ick>, <&hdq_fck>, - <&i2c1_ick>, <&i2c1_fck>, <&i2c2_ick>, <&i2c2_fck>, - <&des_ick>, <&sha_ick>, <&rng_ick>, <&aes_ick>, - <&pka_ick>; - }; -}; - -&func_96m_ck { - compatible = "fixed-factor-clock"; - clocks = <&apll96_ck>; - clock-mult = <1>; - clock-div = <1>; -}; - -&dsp_div_fck { - ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>, <0>, <0>, <0>, <12>; -}; - -&ssi_ssr_sst_div_fck { - ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>; -}; diff --git a/sys/gnu/dts/arm/omap2420-h4.dts b/sys/gnu/dts/arm/omap2420-h4.dts deleted file mode 100644 index 7d660271400..00000000000 --- a/sys/gnu/dts/arm/omap2420-h4.dts +++ /dev/null @@ -1,63 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ - */ -/dts-v1/; - -#include "omap2420.dtsi" - -/ { - model = "TI OMAP2420 H4 board"; - compatible = "ti,omap2420-h4", "ti,omap2420", "ti,omap2"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x4000000>; /* 64 MB */ - }; -}; - -&gpmc { - ranges = <0 0 0x08000000 0x04000000>; - - nor@0,0 { - compatible = "cfi-flash"; - linux,mtd-name= "intel,ge28f256l18b85"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0 0 0x04000000>; - bank-width = <2>; - - gpmc,mux-add-data = <2>; - gpmc,cs-on-ns = <10>; - gpmc,cs-rd-off-ns = <160>; - gpmc,cs-wr-off-ns = <160>; - gpmc,adv-on-ns = <20>; - gpmc,adv-rd-off-ns = <50>; - gpmc,adv-wr-off-ns = <50>; - gpmc,oe-on-ns = <60>; - gpmc,oe-off-ns = <120>; - gpmc,we-on-ns = <60>; - gpmc,we-off-ns = <120>; - gpmc,rd-cycle-ns = <170>; - gpmc,wr-cycle-ns = <170>; - gpmc,access-ns = <150>; - gpmc,page-burst-access-ns = <10>; - - partition@0 { - label = "bootloader"; - reg = <0 0x20000>; - }; - partition@20000 { - label = "params"; - reg = <0x20000 0x20000>; - }; - partition@40000 { - label = "kernel"; - reg = <0x40000 0x200000>; - }; - partition@240000 { - label = "file-system"; - reg = <0x240000 0x3dc0000>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/omap2420-n800.dts b/sys/gnu/dts/arm/omap2420-n800.dts deleted file mode 100644 index f06d767e818..00000000000 --- a/sys/gnu/dts/arm/omap2420-n800.dts +++ /dev/null @@ -1,9 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "omap2420-n8x0-common.dtsi" - -/ { - model = "Nokia N800"; - compatible = "nokia,n800", "nokia,n8x0", "ti,omap2420", "ti,omap2"; -}; diff --git a/sys/gnu/dts/arm/omap2420-n810-wimax.dts b/sys/gnu/dts/arm/omap2420-n810-wimax.dts deleted file mode 100644 index ac9acbd609b..00000000000 --- a/sys/gnu/dts/arm/omap2420-n810-wimax.dts +++ /dev/null @@ -1,9 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "omap2420-n8x0-common.dtsi" - -/ { - model = "Nokia N810 WiMax"; - compatible = "nokia,n810-wimax", "nokia,n8x0", "ti,omap2420", "ti,omap2"; -}; diff --git a/sys/gnu/dts/arm/omap2420-n810.dts b/sys/gnu/dts/arm/omap2420-n810.dts deleted file mode 100644 index 09c1dbc0bb6..00000000000 --- a/sys/gnu/dts/arm/omap2420-n810.dts +++ /dev/null @@ -1,75 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "omap2420-n8x0-common.dtsi" - -/ { - model = "Nokia N810"; - compatible = "nokia,n810", "nokia,n8x0", "ti,omap2420", "ti,omap2"; - - vio_ape: vio_ape { - compatible = "regulator-fixed"; - regulator-name = "vio_ape"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - v28_aic: v28_aic { - compatible = "regulator-fixed"; - regulator-name = "v28_aic"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; -}; - -&omap2420_pmx { - mcbsp2_pins: mcbsp2_pins { - pinctrl-single,pins = < - OMAP2420_CORE_IOPAD(0x0124, PIN_INPUT | MUX_MODE1) /* eac_ac_sclk.mcbsp2_clkx */ - OMAP2420_CORE_IOPAD(0x0125, PIN_INPUT | MUX_MODE1) /* eac_ac_fs.mcbsp2_fsx */ - OMAP2420_CORE_IOPAD(0x0126, PIN_INPUT | MUX_MODE1) /* eac_ac_din.mcbsp2_dr */ - OMAP2420_CORE_IOPAD(0x0127, PIN_OUTPUT | MUX_MODE1) /* eac_ac_dout.mcbsp2_dx */ - >; - }; - - aic33_pins: aic33_pins { - pinctrl-single,pins = < - OMAP2420_CORE_IOPAD(0x0129, PIN_OUTPUT | MUX_MODE3) /* eac_ac_rst.gpio118 */ - OMAP2420_CORE_IOPAD(0x00e8, PIN_OUTPUT | MUX_MODE2) /* vlynq_tx1.sys_clkout2 */ - >; - }; -}; - -&i2c2 { - aic33@18 { - compatible = "ti,tlv320aic33"; - reg = <0x18>; - - pinctrl-names = "default"; - pinctrl-0 = <&aic33_pins>; - - reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; /* gpio118 */ - - ai3x-gpio-func = < - 10 /* AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK */ - 5 /* AIC3X_GPIO2_FUNC_DIGITAL_MIC_INPUT */ - >; - ai3x-micbias-vg = <1>; /* 2V */ - - AVDD-supply = <&v28_aic>; - DRVDD-supply = <&v28_aic>; - IOVDD-supply = <&vio_ape>; - DVDD-supply = <&vio_ape>; - - assigned-clocks = <&sys_clkout2_src>, <&sys_clkout2>; - assigned-clock-parents = <&func_96m_ck>; - assigned-clock-rates = <0>, <12000000>; - }; -}; - -&mcbsp2 { - pinctrl-names = "default"; - pinctrl-0 = <&mcbsp2_pins>; - - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/omap2420-n8x0-common.dtsi b/sys/gnu/dts/arm/omap2420-n8x0-common.dtsi deleted file mode 100644 index 63b0b4921e4..00000000000 --- a/sys/gnu/dts/arm/omap2420-n8x0-common.dtsi +++ /dev/null @@ -1,111 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "omap2420.dtsi" - -/ { - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x8000000>; /* 128 MB */ - }; - - chosen { - stdout-path = &uart3; - }; - - ocp { - i2c0 { - compatible = "i2c-cbus-gpio"; - gpios = <&gpio3 2 GPIO_ACTIVE_HIGH /* gpio66 clk */ - &gpio3 1 GPIO_ACTIVE_HIGH /* gpio65 dat */ - &gpio3 0 GPIO_ACTIVE_HIGH /* gpio64 sel */ - >; - #address-cells = <1>; - #size-cells = <0>; - retu: retu@1 { - compatible = "nokia,retu"; - interrupt-parent = <&gpio4>; - interrupts = <12 IRQ_TYPE_EDGE_RISING>; - reg = <0x1>; - }; - }; - }; -}; - -&i2c1 { - clock-frequency = <400000>; - - pmic@72 { - compatible = "menelaus"; - reg = <0x72>; - interrupts = <7 IRQ_TYPE_EDGE_RISING>; - }; -}; - -&i2c2 { - clock-frequency = <400000>; -}; - -&gpmc { - ranges = <0 0 0x04000000 0x1000000>; /* CS0: 16MB for OneNAND */ - - /* gpio-irq for dma: 26 */ - - onenand@0,0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "ti,omap2-onenand"; - reg = <0 0 0x20000>; /* CS0, offset 0, IO size 128K */ - - gpmc,sync-read; - gpmc,burst-length = <16>; - gpmc,burst-read; - gpmc,burst-wrap; - gpmc,device-width = <2>; - gpmc,mux-add-data = <2>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <127>; - gpmc,cs-wr-off-ns = <109>; - gpmc,adv-on-ns = <0>; - gpmc,adv-rd-off-ns = <18>; - gpmc,adv-wr-off-ns = <18>; - gpmc,oe-on-ns = <27>; - gpmc,oe-off-ns = <127>; - gpmc,we-on-ns = <27>; - gpmc,we-off-ns = <72>; - gpmc,rd-cycle-ns = <145>; - gpmc,wr-cycle-ns = <136>; - gpmc,access-ns = <118>; - gpmc,page-burst-access-ns = <27>; - gpmc,bus-turnaround-ns = <0>; - gpmc,cycle2cycle-delay-ns = <0>; - gpmc,wait-monitoring-ns = <0>; - gpmc,clk-activation-ns = <9>; - gpmc,sync-clk-ps = <27000>; - - /* MTD partition table corresponding to old board-n8x0 file. */ - partition@0 { - label = "bootloader"; - reg = <0x00000000 0x00020000>; - read-only; - }; - partition@1 { - label = "config"; - reg = <0x00020000 0x00060000>; - }; - partition@2 { - label = "kernel"; - reg = <0x00080000 0x00200000>; - }; - partition@3 { - label = "initfs"; - reg = <0x00280000 0x00400000>; - }; - partition@4 { - label = "rootfs"; - reg = <0x00680000 0x0f980000>; - }; - partition@5 { - label = "omap2-onenand"; - reg = <0x00000000 0x10000000>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/omap2420.dtsi b/sys/gnu/dts/arm/omap2420.dtsi deleted file mode 100644 index aba542d63d6..00000000000 --- a/sys/gnu/dts/arm/omap2420.dtsi +++ /dev/null @@ -1,222 +0,0 @@ -/* - * Device Tree Source for OMAP2420 SoC - * - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -#include "omap2.dtsi" - -/ { - compatible = "ti,omap2420", "ti,omap2"; - - ocp { - l4: l4@48000000 { - compatible = "ti,omap2-l4", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x48000000 0x100000>; - - prcm: prcm@8000 { - compatible = "ti,omap2-prcm"; - reg = <0x8000 0x1000>; - - prcm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - prcm_clockdomains: clockdomains { - }; - }; - - scm: scm@0 { - compatible = "ti,omap2-scm", "simple-bus"; - reg = <0x0 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - #pinctrl-cells = <1>; - ranges = <0 0x0 0x1000>; - - omap2420_pmx: pinmux@30 { - compatible = "ti,omap2420-padconf", - "pinctrl-single"; - reg = <0x30 0x0113>; - #address-cells = <1>; - #size-cells = <0>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <8>; - pinctrl-single,function-mask = <0x3f>; - }; - - scm_conf: scm_conf@270 { - compatible = "syscon"; - reg = <0x270 0x100>; - #address-cells = <1>; - #size-cells = <1>; - - scm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - scm_clockdomains: clockdomains { - }; - }; - - counter32k: counter@4000 { - compatible = "ti,omap-counter32k"; - reg = <0x4000 0x20>; - ti,hwmods = "counter_32k"; - }; - }; - - gpio1: gpio@48018000 { - compatible = "ti,omap2-gpio"; - reg = <0x48018000 0x200>; - interrupts = <29>; - ti,hwmods = "gpio1"; - ti,gpio-always-on; - #gpio-cells = <2>; - gpio-controller; - #interrupt-cells = <2>; - interrupt-controller; - }; - - gpio2: gpio@4801a000 { - compatible = "ti,omap2-gpio"; - reg = <0x4801a000 0x200>; - interrupts = <30>; - ti,hwmods = "gpio2"; - ti,gpio-always-on; - #gpio-cells = <2>; - gpio-controller; - #interrupt-cells = <2>; - interrupt-controller; - }; - - gpio3: gpio@4801c000 { - compatible = "ti,omap2-gpio"; - reg = <0x4801c000 0x200>; - interrupts = <31>; - ti,hwmods = "gpio3"; - ti,gpio-always-on; - #gpio-cells = <2>; - gpio-controller; - #interrupt-cells = <2>; - interrupt-controller; - }; - - gpio4: gpio@4801e000 { - compatible = "ti,omap2-gpio"; - reg = <0x4801e000 0x200>; - interrupts = <32>; - ti,hwmods = "gpio4"; - ti,gpio-always-on; - #gpio-cells = <2>; - gpio-controller; - #interrupt-cells = <2>; - interrupt-controller; - }; - - gpmc: gpmc@6800a000 { - compatible = "ti,omap2420-gpmc"; - reg = <0x6800a000 0x1000>; - #address-cells = <2>; - #size-cells = <1>; - interrupts = <20>; - gpmc,num-cs = <8>; - gpmc,num-waitpins = <4>; - ti,hwmods = "gpmc"; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - }; - - mcbsp1: mcbsp@48074000 { - compatible = "ti,omap2420-mcbsp"; - reg = <0x48074000 0xff>; - reg-names = "mpu"; - interrupts = <59>, /* TX interrupt */ - <60>; /* RX interrupt */ - interrupt-names = "tx", "rx"; - ti,hwmods = "mcbsp1"; - dmas = <&sdma 31>, - <&sdma 32>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - mcbsp2: mcbsp@48076000 { - compatible = "ti,omap2420-mcbsp"; - reg = <0x48076000 0xff>; - reg-names = "mpu"; - interrupts = <62>, /* TX interrupt */ - <63>; /* RX interrupt */ - interrupt-names = "tx", "rx"; - ti,hwmods = "mcbsp2"; - dmas = <&sdma 33>, - <&sdma 34>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - msdi1: mmc@4809c000 { - compatible = "ti,omap2420-mmc"; - ti,hwmods = "msdi1"; - reg = <0x4809c000 0x80>; - interrupts = <83>; - dmas = <&sdma 61 &sdma 62>; - dma-names = "tx", "rx"; - }; - - mailbox: mailbox@48094000 { - compatible = "ti,omap2-mailbox"; - reg = <0x48094000 0x200>; - interrupts = <26>, <34>; - interrupt-names = "dsp", "iva"; - ti,hwmods = "mailbox"; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <6>; - mbox_dsp: dsp { - ti,mbox-tx = <0 0 0>; - ti,mbox-rx = <1 0 0>; - }; - mbox_iva: iva { - ti,mbox-tx = <2 1 3>; - ti,mbox-rx = <3 1 3>; - }; - }; - - timer1: timer@48028000 { - compatible = "ti,omap2420-timer"; - reg = <0x48028000 0x400>; - interrupts = <37>; - ti,hwmods = "timer1"; - ti,timer-alwon; - }; - - wd_timer2: wdt@48022000 { - compatible = "ti,omap2-wdt"; - ti,hwmods = "wd_timer2"; - reg = <0x48022000 0x80>; - }; - }; -}; - -&i2c1 { - compatible = "ti,omap2420-i2c"; -}; - -&i2c2 { - compatible = "ti,omap2420-i2c"; -}; - -/include/ "omap24xx-clocks.dtsi" -/include/ "omap2420-clocks.dtsi" diff --git a/sys/gnu/dts/arm/omap2430-clocks.dtsi b/sys/gnu/dts/arm/omap2430-clocks.dtsi deleted file mode 100644 index 4e5ab518947..00000000000 --- a/sys/gnu/dts/arm/omap2430-clocks.dtsi +++ /dev/null @@ -1,341 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Device Tree Source for OMAP2430 clock data - * - * Copyright (C) 2014 Texas Instruments, Inc. - */ - -&scm_clocks { - mcbsp3_mux_fck: mcbsp3_mux_fck@78 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&func_96m_ck>, <&mcbsp_clks>; - reg = <0x78>; - }; - - mcbsp3_fck: mcbsp3_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&mcbsp3_gate_fck>, <&mcbsp3_mux_fck>; - }; - - mcbsp4_mux_fck: mcbsp4_mux_fck@78 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&func_96m_ck>, <&mcbsp_clks>; - ti,bit-shift = <2>; - reg = <0x78>; - }; - - mcbsp4_fck: mcbsp4_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&mcbsp4_gate_fck>, <&mcbsp4_mux_fck>; - }; - - mcbsp5_mux_fck: mcbsp5_mux_fck@78 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&func_96m_ck>, <&mcbsp_clks>; - ti,bit-shift = <4>; - reg = <0x78>; - }; - - mcbsp5_fck: mcbsp5_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&mcbsp5_gate_fck>, <&mcbsp5_mux_fck>; - }; -}; - -&prcm_clocks { - iva2_1_gate_ick: iva2_1_gate_ick@800 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&dsp_fck>; - ti,bit-shift = <0>; - reg = <0x0800>; - }; - - iva2_1_div_ick: iva2_1_div_ick@840 { - #clock-cells = <0>; - compatible = "ti,composite-divider-clock"; - clocks = <&dsp_fck>; - ti,bit-shift = <5>; - ti,max-div = <3>; - reg = <0x0840>; - ti,index-starts-at-one; - }; - - iva2_1_ick: iva2_1_ick { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&iva2_1_gate_ick>, <&iva2_1_div_ick>; - }; - - mdm_gate_ick: mdm_gate_ick@c10 { - #clock-cells = <0>; - compatible = "ti,composite-interface-clock"; - clocks = <&core_ck>; - ti,bit-shift = <0>; - reg = <0x0c10>; - }; - - mdm_div_ick: mdm_div_ick@c40 { - #clock-cells = <0>; - compatible = "ti,composite-divider-clock"; - clocks = <&core_ck>; - reg = <0x0c40>; - ti,dividers = <0>, <1>, <0>, <0>, <4>, <0>, <6>, <0>, <0>, <9>; - }; - - mdm_ick: mdm_ick { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&mdm_gate_ick>, <&mdm_div_ick>; - }; - - mdm_osc_ck: mdm_osc_ck@c00 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&osc_ck>; - ti,bit-shift = <1>; - reg = <0x0c00>; - }; - - mcbsp3_ick: mcbsp3_ick@214 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <3>; - reg = <0x0214>; - }; - - mcbsp3_gate_fck: mcbsp3_gate_fck@204 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&mcbsp_clks>; - ti,bit-shift = <3>; - reg = <0x0204>; - }; - - mcbsp4_ick: mcbsp4_ick@214 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <4>; - reg = <0x0214>; - }; - - mcbsp4_gate_fck: mcbsp4_gate_fck@204 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&mcbsp_clks>; - ti,bit-shift = <4>; - reg = <0x0204>; - }; - - mcbsp5_ick: mcbsp5_ick@214 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <5>; - reg = <0x0214>; - }; - - mcbsp5_gate_fck: mcbsp5_gate_fck@204 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&mcbsp_clks>; - ti,bit-shift = <5>; - reg = <0x0204>; - }; - - mcspi3_ick: mcspi3_ick@214 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <9>; - reg = <0x0214>; - }; - - mcspi3_fck: mcspi3_fck@204 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&func_48m_ck>; - ti,bit-shift = <9>; - reg = <0x0204>; - }; - - icr_ick: icr_ick@410 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&sys_ck>; - ti,bit-shift = <6>; - reg = <0x0410>; - }; - - i2chs1_fck: i2chs1_fck@204 { - #clock-cells = <0>; - compatible = "ti,omap2430-interface-clock"; - clocks = <&func_96m_ck>; - ti,bit-shift = <19>; - reg = <0x0204>; - }; - - i2chs2_fck: i2chs2_fck@204 { - #clock-cells = <0>; - compatible = "ti,omap2430-interface-clock"; - clocks = <&func_96m_ck>; - ti,bit-shift = <20>; - reg = <0x0204>; - }; - - usbhs_ick: usbhs_ick@214 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l3_ck>; - ti,bit-shift = <6>; - reg = <0x0214>; - }; - - mmchs1_ick: mmchs1_ick@214 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <7>; - reg = <0x0214>; - }; - - mmchs1_fck: mmchs1_fck@204 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&func_96m_ck>; - ti,bit-shift = <7>; - reg = <0x0204>; - }; - - mmchs2_ick: mmchs2_ick@214 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <8>; - reg = <0x0214>; - }; - - mmchs2_fck: mmchs2_fck@204 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&func_96m_ck>; - ti,bit-shift = <8>; - reg = <0x0204>; - }; - - gpio5_ick: gpio5_ick@214 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <10>; - reg = <0x0214>; - }; - - gpio5_fck: gpio5_fck@204 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&func_32k_ck>; - ti,bit-shift = <10>; - reg = <0x0204>; - }; - - mdm_intc_ick: mdm_intc_ick@214 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <11>; - reg = <0x0214>; - }; - - mmchsdb1_fck: mmchsdb1_fck@204 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&func_32k_ck>; - ti,bit-shift = <16>; - reg = <0x0204>; - }; - - mmchsdb2_fck: mmchsdb2_fck@204 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&func_32k_ck>; - ti,bit-shift = <17>; - reg = <0x0204>; - }; -}; - -&prcm_clockdomains { - gfx_clkdm: gfx_clkdm { - compatible = "ti,clockdomain"; - clocks = <&gfx_ick>; - }; - - core_l3_clkdm: core_l3_clkdm { - compatible = "ti,clockdomain"; - clocks = <&cam_fck>, <&usb_fck>, <&usbhs_ick>; - }; - - wkup_clkdm: wkup_clkdm { - compatible = "ti,clockdomain"; - clocks = <&dpll_ck>, <&emul_ck>, <&gpt1_ick>, <&gpios_ick>, - <&gpios_fck>, <&mpu_wdt_ick>, <&mpu_wdt_fck>, - <&sync_32k_ick>, <&wdt1_ick>, <&omapctrl_ick>, - <&icr_ick>; - }; - - dss_clkdm: dss_clkdm { - compatible = "ti,clockdomain"; - clocks = <&dss_ick>, <&dss_54m_fck>; - }; - - core_l4_clkdm: core_l4_clkdm { - compatible = "ti,clockdomain"; - clocks = <&ssi_l4_ick>, <&gpt2_ick>, <&gpt3_ick>, <&gpt4_ick>, - <&gpt5_ick>, <&gpt6_ick>, <&gpt7_ick>, <&gpt8_ick>, - <&gpt9_ick>, <&gpt10_ick>, <&gpt11_ick>, <&gpt12_ick>, - <&mcbsp1_ick>, <&mcbsp2_ick>, <&mcbsp3_ick>, - <&mcbsp4_ick>, <&mcbsp5_ick>, <&mcspi1_ick>, - <&mcspi1_fck>, <&mcspi2_ick>, <&mcspi2_fck>, - <&mcspi3_ick>, <&mcspi3_fck>, <&uart1_ick>, - <&uart1_fck>, <&uart2_ick>, <&uart2_fck>, <&uart3_ick>, - <&uart3_fck>, <&cam_ick>, <&mailboxes_ick>, - <&wdt4_ick>, <&wdt4_fck>, <&mspro_ick>, <&mspro_fck>, - <&fac_ick>, <&fac_fck>, <&hdq_ick>, <&hdq_fck>, - <&i2c1_ick>, <&i2chs1_fck>, <&i2c2_ick>, <&i2chs2_fck>, - <&des_ick>, <&sha_ick>, <&rng_ick>, <&aes_ick>, - <&pka_ick>, <&mmchs1_ick>, <&mmchs1_fck>, - <&mmchs2_ick>, <&mmchs2_fck>, <&gpio5_ick>, - <&gpio5_fck>, <&mdm_intc_ick>, <&mmchsdb1_fck>, - <&mmchsdb2_fck>; - }; - - mdm_clkdm: mdm_clkdm { - compatible = "ti,clockdomain"; - clocks = <&mdm_osc_ck>; - }; -}; - -&func_96m_ck { - compatible = "ti,mux-clock"; - clocks = <&apll96_ck>, <&alt_ck>; - ti,bit-shift = <4>; - reg = <0x0540>; -}; - -&dsp_div_fck { - ti,max-div = <4>; - ti,index-starts-at-one; -}; - -&ssi_ssr_sst_div_fck { - ti,max-div = <5>; - ti,index-starts-at-one; -}; diff --git a/sys/gnu/dts/arm/omap2430-sdp.dts b/sys/gnu/dts/arm/omap2430-sdp.dts deleted file mode 100644 index f7e32488664..00000000000 --- a/sys/gnu/dts/arm/omap2430-sdp.dts +++ /dev/null @@ -1,70 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ - */ -/dts-v1/; - -#include "omap2430.dtsi" - -/ { - model = "TI OMAP2430 SDP"; - compatible = "ti,omap2430-sdp", "ti,omap2430", "ti,omap2"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x8000000>; /* 128 MB */ - }; -}; - -&i2c2 { - clock-frequency = <100000>; - - twl: twl@48 { - reg = <0x48>; - interrupts = <7>; /* SYS_NIRQ cascaded to intc */ - }; -}; - -#include "twl4030.dtsi" - -&mmc1 { - vmmc-supply = <&vmmc1>; - bus-width = <4>; -}; - -&gpmc { - ranges = <5 0 0x08000000 0x01000000>; - ethernet@gpmc { - compatible = "smsc,lan91c94"; - interrupt-parent = <&gpio5>; - interrupts = <21 IRQ_TYPE_LEVEL_LOW>; /* gpio149 */ - reg = <5 0x300 0xf>; - bank-width = <2>; - gpmc,sync-clk-ps = <0>; - gpmc,mux-add-data = <2>; - gpmc,device-width = <1>; - gpmc,cycle2cycle-samecsen = <1>; - gpmc,cycle2cycle-diffcsen = <1>; - gpmc,cs-on-ns = <6>; - gpmc,cs-rd-off-ns = <187>; - gpmc,cs-wr-off-ns = <187>; - gpmc,adv-on-ns = <18>; - gpmc,adv-rd-off-ns = <48>; - gpmc,adv-wr-off-ns = <48>; - gpmc,oe-on-ns = <60>; - gpmc,oe-off-ns = <169>; - gpmc,we-on-ns = <66>; - gpmc,we-off-ns = <169>; - gpmc,rd-cycle-ns = <187>; - gpmc,wr-cycle-ns = <187>; - gpmc,access-ns = <187>; - gpmc,page-burst-access-ns = <24>; - gpmc,bus-turnaround-ns = <24>; - gpmc,cycle2cycle-delay-ns = <24>; - gpmc,wait-monitoring-ns = <0>; - gpmc,clk-activation-ns = <0>; - gpmc,wr-data-mux-bus-ns = <0>; - gpmc,wr-access-ns = <0>; - }; -}; - diff --git a/sys/gnu/dts/arm/omap2430.dtsi b/sys/gnu/dts/arm/omap2430.dtsi deleted file mode 100644 index 7f57af2f10a..00000000000 --- a/sys/gnu/dts/arm/omap2430.dtsi +++ /dev/null @@ -1,321 +0,0 @@ -/* - * Device Tree Source for OMAP243x SoC - * - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -#include "omap2.dtsi" - -/ { - compatible = "ti,omap2430", "ti,omap2"; - - ocp { - l4_wkup: l4_wkup@49000000 { - compatible = "ti,omap2-l4-wkup", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x49000000 0x31000>; - - prcm: prcm@6000 { - compatible = "ti,omap2-prcm"; - reg = <0x6000 0x1000>; - - prcm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - prcm_clockdomains: clockdomains { - }; - }; - - scm: scm@2000 { - compatible = "ti,omap2-scm", "simple-bus"; - reg = <0x2000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - #pinctrl-cells = <1>; - ranges = <0 0x2000 0x1000>; - - omap2430_pmx: pinmux@30 { - compatible = "ti,omap2430-padconf", - "pinctrl-single"; - reg = <0x30 0x0154>; - #address-cells = <1>; - #size-cells = <0>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <8>; - pinctrl-single,function-mask = <0x3f>; - }; - - scm_conf: scm_conf@270 { - compatible = "syscon", - "simple-bus"; - reg = <0x270 0x240>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x270 0x240>; - - scm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - pbias_regulator: pbias_regulator@230 { - compatible = "ti,pbias-omap2", "ti,pbias-omap"; - reg = <0x230 0x4>; - syscon = <&scm_conf>; - pbias_mmc_reg: pbias_mmc_omap2430 { - regulator-name = "pbias_mmc_omap2430"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3000000>; - }; - }; - }; - - scm_clockdomains: clockdomains { - }; - }; - - counter32k: counter@20000 { - compatible = "ti,omap-counter32k"; - reg = <0x20000 0x20>; - ti,hwmods = "counter_32k"; - }; - }; - - gpio1: gpio@4900c000 { - compatible = "ti,omap2-gpio"; - reg = <0x4900c000 0x200>; - interrupts = <29>; - ti,hwmods = "gpio1"; - ti,gpio-always-on; - #gpio-cells = <2>; - gpio-controller; - #interrupt-cells = <2>; - interrupt-controller; - }; - - gpio2: gpio@4900e000 { - compatible = "ti,omap2-gpio"; - reg = <0x4900e000 0x200>; - interrupts = <30>; - ti,hwmods = "gpio2"; - ti,gpio-always-on; - #gpio-cells = <2>; - gpio-controller; - #interrupt-cells = <2>; - interrupt-controller; - }; - - gpio3: gpio@49010000 { - compatible = "ti,omap2-gpio"; - reg = <0x49010000 0x200>; - interrupts = <31>; - ti,hwmods = "gpio3"; - ti,gpio-always-on; - #gpio-cells = <2>; - gpio-controller; - #interrupt-cells = <2>; - interrupt-controller; - }; - - gpio4: gpio@49012000 { - compatible = "ti,omap2-gpio"; - reg = <0x49012000 0x200>; - interrupts = <32>; - ti,hwmods = "gpio4"; - ti,gpio-always-on; - #gpio-cells = <2>; - gpio-controller; - #interrupt-cells = <2>; - interrupt-controller; - }; - - gpio5: gpio@480b6000 { - compatible = "ti,omap2-gpio"; - reg = <0x480b6000 0x200>; - interrupts = <33>; - ti,hwmods = "gpio5"; - #gpio-cells = <2>; - gpio-controller; - #interrupt-cells = <2>; - interrupt-controller; - }; - - gpmc: gpmc@6e000000 { - compatible = "ti,omap2430-gpmc"; - reg = <0x6e000000 0x1000>; - #address-cells = <2>; - #size-cells = <1>; - interrupts = <20>; - gpmc,num-cs = <8>; - gpmc,num-waitpins = <4>; - ti,hwmods = "gpmc"; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - }; - - mcbsp1: mcbsp@48074000 { - compatible = "ti,omap2430-mcbsp"; - reg = <0x48074000 0xff>; - reg-names = "mpu"; - interrupts = <64>, /* OCP compliant interrupt */ - <59>, /* TX interrupt */ - <60>, /* RX interrupt */ - <61>; /* RX overflow interrupt */ - interrupt-names = "common", "tx", "rx", "rx_overflow"; - ti,buffer-size = <128>; - ti,hwmods = "mcbsp1"; - dmas = <&sdma 31>, - <&sdma 32>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - mcbsp2: mcbsp@48076000 { - compatible = "ti,omap2430-mcbsp"; - reg = <0x48076000 0xff>; - reg-names = "mpu"; - interrupts = <16>, /* OCP compliant interrupt */ - <62>, /* TX interrupt */ - <63>; /* RX interrupt */ - interrupt-names = "common", "tx", "rx"; - ti,buffer-size = <128>; - ti,hwmods = "mcbsp2"; - dmas = <&sdma 33>, - <&sdma 34>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - mcbsp3: mcbsp@4808c000 { - compatible = "ti,omap2430-mcbsp"; - reg = <0x4808c000 0xff>; - reg-names = "mpu"; - interrupts = <17>, /* OCP compliant interrupt */ - <89>, /* TX interrupt */ - <90>; /* RX interrupt */ - interrupt-names = "common", "tx", "rx"; - ti,buffer-size = <128>; - ti,hwmods = "mcbsp3"; - dmas = <&sdma 17>, - <&sdma 18>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - mcbsp4: mcbsp@4808e000 { - compatible = "ti,omap2430-mcbsp"; - reg = <0x4808e000 0xff>; - reg-names = "mpu"; - interrupts = <18>, /* OCP compliant interrupt */ - <54>, /* TX interrupt */ - <55>; /* RX interrupt */ - interrupt-names = "common", "tx", "rx"; - ti,buffer-size = <128>; - ti,hwmods = "mcbsp4"; - dmas = <&sdma 19>, - <&sdma 20>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - mcbsp5: mcbsp@48096000 { - compatible = "ti,omap2430-mcbsp"; - reg = <0x48096000 0xff>; - reg-names = "mpu"; - interrupts = <19>, /* OCP compliant interrupt */ - <81>, /* TX interrupt */ - <82>; /* RX interrupt */ - interrupt-names = "common", "tx", "rx"; - ti,buffer-size = <128>; - ti,hwmods = "mcbsp5"; - dmas = <&sdma 21>, - <&sdma 22>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - mmc1: mmc@4809c000 { - compatible = "ti,omap2-hsmmc"; - reg = <0x4809c000 0x200>; - interrupts = <83>; - ti,hwmods = "mmc1"; - ti,dual-volt; - dmas = <&sdma 61>, <&sdma 62>; - dma-names = "tx", "rx"; - pbias-supply = <&pbias_mmc_reg>; - }; - - mmc2: mmc@480b4000 { - compatible = "ti,omap2-hsmmc"; - reg = <0x480b4000 0x200>; - interrupts = <86>; - ti,hwmods = "mmc2"; - dmas = <&sdma 47>, <&sdma 48>; - dma-names = "tx", "rx"; - }; - - mailbox: mailbox@48094000 { - compatible = "ti,omap2-mailbox"; - reg = <0x48094000 0x200>; - interrupts = <26>; - ti,hwmods = "mailbox"; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <6>; - mbox_dsp: dsp { - ti,mbox-tx = <0 0 0>; - ti,mbox-rx = <1 0 0>; - }; - }; - - timer1: timer@49018000 { - compatible = "ti,omap2420-timer"; - reg = <0x49018000 0x400>; - interrupts = <37>; - ti,hwmods = "timer1"; - ti,timer-alwon; - }; - - mcspi3: spi@480b8000 { - compatible = "ti,omap2-mcspi"; - ti,hwmods = "mcspi3"; - reg = <0x480b8000 0x100>; - interrupts = <91>; - dmas = <&sdma 15 &sdma 16 &sdma 23 &sdma 24>; - dma-names = "tx0", "rx0", "tx1", "rx1"; - }; - - usb_otg_hs: usb_otg_hs@480ac000 { - compatible = "ti,omap2-musb"; - ti,hwmods = "usb_otg_hs"; - reg = <0x480ac000 0x1000>; - interrupts = <93>; - }; - - wd_timer2: wdt@49016000 { - compatible = "ti,omap2-wdt"; - ti,hwmods = "wd_timer2"; - reg = <0x49016000 0x80>; - }; - }; -}; - -&i2c1 { - compatible = "ti,omap2430-i2c"; -}; - -&i2c2 { - compatible = "ti,omap2430-i2c"; -}; - -/include/ "omap24xx-clocks.dtsi" -/include/ "omap2430-clocks.dtsi" diff --git a/sys/gnu/dts/arm/omap24xx-clocks.dtsi b/sys/gnu/dts/arm/omap24xx-clocks.dtsi deleted file mode 100644 index 07af87edf0e..00000000000 --- a/sys/gnu/dts/arm/omap24xx-clocks.dtsi +++ /dev/null @@ -1,1241 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Device Tree Source for OMAP24xx clock data - * - * Copyright (C) 2014 Texas Instruments, Inc. - */ -&scm_clocks { - mcbsp1_mux_fck: mcbsp1_mux_fck@4 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&func_96m_ck>, <&mcbsp_clks>; - ti,bit-shift = <2>; - reg = <0x4>; - }; - - mcbsp1_fck: mcbsp1_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&mcbsp1_gate_fck>, <&mcbsp1_mux_fck>; - }; - - mcbsp2_mux_fck: mcbsp2_mux_fck@4 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&func_96m_ck>, <&mcbsp_clks>; - ti,bit-shift = <6>; - reg = <0x4>; - }; - - mcbsp2_fck: mcbsp2_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&mcbsp2_gate_fck>, <&mcbsp2_mux_fck>; - }; -}; - -&prcm_clocks { - func_32k_ck: func_32k_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - secure_32k_ck: secure_32k_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - virt_12m_ck: virt_12m_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <12000000>; - }; - - virt_13m_ck: virt_13m_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <13000000>; - }; - - virt_19200000_ck: virt_19200000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <19200000>; - }; - - virt_26m_ck: virt_26m_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <26000000>; - }; - - aplls_clkin_ck: aplls_clkin_ck@540 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&virt_19200000_ck>, <&virt_26m_ck>, <&virt_13m_ck>, <&virt_12m_ck>; - ti,bit-shift = <23>; - reg = <0x0540>; - }; - - aplls_clkin_x2_ck: aplls_clkin_x2_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&aplls_clkin_ck>; - clock-mult = <2>; - clock-div = <1>; - }; - - osc_ck: osc_ck@60 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&aplls_clkin_ck>, <&aplls_clkin_x2_ck>; - ti,bit-shift = <6>; - reg = <0x0060>; - ti,index-starts-at-one; - }; - - sys_ck: sys_ck@60 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&osc_ck>; - ti,bit-shift = <6>; - ti,max-div = <3>; - reg = <0x0060>; - ti,index-starts-at-one; - }; - - alt_ck: alt_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <54000000>; - }; - - mcbsp_clks: mcbsp_clks { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0x0>; - }; - - dpll_ck: dpll_ck@500 { - #clock-cells = <0>; - compatible = "ti,omap2-dpll-core-clock"; - clocks = <&sys_ck>, <&sys_ck>; - reg = <0x0500>, <0x0540>; - }; - - apll96_ck: apll96_ck@500 { - #clock-cells = <0>; - compatible = "ti,omap2-apll-clock"; - clocks = <&sys_ck>; - ti,bit-shift = <2>; - ti,idlest-shift = <8>; - ti,clock-frequency = <96000000>; - reg = <0x0500>, <0x0530>, <0x0520>; - }; - - apll54_ck: apll54_ck@500 { - #clock-cells = <0>; - compatible = "ti,omap2-apll-clock"; - clocks = <&sys_ck>; - ti,bit-shift = <6>; - ti,idlest-shift = <9>; - ti,clock-frequency = <54000000>; - reg = <0x0500>, <0x0530>, <0x0520>; - }; - - func_54m_ck: func_54m_ck@540 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&apll54_ck>, <&alt_ck>; - ti,bit-shift = <5>; - reg = <0x0540>; - }; - - core_ck: core_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - func_96m_ck: func_96m_ck@540 { - #clock-cells = <0>; - }; - - apll96_d2_ck: apll96_d2_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&apll96_ck>; - clock-mult = <1>; - clock-div = <2>; - }; - - func_48m_ck: func_48m_ck@540 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&apll96_d2_ck>, <&alt_ck>; - ti,bit-shift = <3>; - reg = <0x0540>; - }; - - func_12m_ck: func_12m_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&func_48m_ck>; - clock-mult = <1>; - clock-div = <4>; - }; - - sys_clkout_src_gate: sys_clkout_src_gate@70 { - #clock-cells = <0>; - compatible = "ti,composite-no-wait-gate-clock"; - clocks = <&core_ck>; - ti,bit-shift = <7>; - reg = <0x0070>; - }; - - sys_clkout_src_mux: sys_clkout_src_mux@70 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&core_ck>, <&sys_ck>, <&func_96m_ck>, <&func_54m_ck>; - reg = <0x0070>; - }; - - sys_clkout_src: sys_clkout_src { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&sys_clkout_src_gate>, <&sys_clkout_src_mux>; - }; - - sys_clkout: sys_clkout@70 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&sys_clkout_src>; - ti,bit-shift = <3>; - ti,max-div = <64>; - reg = <0x0070>; - ti,index-power-of-two; - }; - - emul_ck: emul_ck@78 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&func_54m_ck>; - ti,bit-shift = <0>; - reg = <0x0078>; - }; - - mpu_ck: mpu_ck@140 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&core_ck>; - ti,max-div = <31>; - reg = <0x0140>; - ti,index-starts-at-one; - }; - - dsp_gate_fck: dsp_gate_fck@800 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&core_ck>; - ti,bit-shift = <0>; - reg = <0x0800>; - }; - - dsp_div_fck: dsp_div_fck@840 { - #clock-cells = <0>; - compatible = "ti,composite-divider-clock"; - clocks = <&core_ck>; - reg = <0x0840>; - }; - - dsp_fck: dsp_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&dsp_gate_fck>, <&dsp_div_fck>; - }; - - core_l3_ck: core_l3_ck@240 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&core_ck>; - ti,max-div = <31>; - reg = <0x0240>; - ti,index-starts-at-one; - }; - - gfx_3d_gate_fck: gfx_3d_gate_fck@300 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&core_l3_ck>; - ti,bit-shift = <2>; - reg = <0x0300>; - }; - - gfx_3d_div_fck: gfx_3d_div_fck@340 { - #clock-cells = <0>; - compatible = "ti,composite-divider-clock"; - clocks = <&core_l3_ck>; - ti,max-div = <4>; - reg = <0x0340>; - ti,index-starts-at-one; - }; - - gfx_3d_fck: gfx_3d_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&gfx_3d_gate_fck>, <&gfx_3d_div_fck>; - }; - - gfx_2d_gate_fck: gfx_2d_gate_fck@300 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&core_l3_ck>; - ti,bit-shift = <1>; - reg = <0x0300>; - }; - - gfx_2d_div_fck: gfx_2d_div_fck@340 { - #clock-cells = <0>; - compatible = "ti,composite-divider-clock"; - clocks = <&core_l3_ck>; - ti,max-div = <4>; - reg = <0x0340>; - ti,index-starts-at-one; - }; - - gfx_2d_fck: gfx_2d_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&gfx_2d_gate_fck>, <&gfx_2d_div_fck>; - }; - - gfx_ick: gfx_ick@310 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_l3_ck>; - ti,bit-shift = <0>; - reg = <0x0310>; - }; - - l4_ck: l4_ck@240 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&core_l3_ck>; - ti,bit-shift = <5>; - ti,max-div = <3>; - reg = <0x0240>; - ti,index-starts-at-one; - }; - - dss_ick: dss_ick@210 { - #clock-cells = <0>; - compatible = "ti,omap3-no-wait-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <0>; - reg = <0x0210>; - }; - - dss1_gate_fck: dss1_gate_fck@200 { - #clock-cells = <0>; - compatible = "ti,composite-no-wait-gate-clock"; - clocks = <&core_ck>; - ti,bit-shift = <0>; - reg = <0x0200>; - }; - - core_d2_ck: core_d2_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&core_ck>; - clock-mult = <1>; - clock-div = <2>; - }; - - core_d3_ck: core_d3_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&core_ck>; - clock-mult = <1>; - clock-div = <3>; - }; - - core_d4_ck: core_d4_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&core_ck>; - clock-mult = <1>; - clock-div = <4>; - }; - - core_d5_ck: core_d5_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&core_ck>; - clock-mult = <1>; - clock-div = <5>; - }; - - core_d6_ck: core_d6_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&core_ck>; - clock-mult = <1>; - clock-div = <6>; - }; - - dummy_ck: dummy_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - core_d8_ck: core_d8_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&core_ck>; - clock-mult = <1>; - clock-div = <8>; - }; - - core_d9_ck: core_d9_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&core_ck>; - clock-mult = <1>; - clock-div = <9>; - }; - - core_d12_ck: core_d12_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&core_ck>; - clock-mult = <1>; - clock-div = <12>; - }; - - core_d16_ck: core_d16_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&core_ck>; - clock-mult = <1>; - clock-div = <16>; - }; - - dss1_mux_fck: dss1_mux_fck@240 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&sys_ck>, <&core_ck>, <&core_d2_ck>, <&core_d3_ck>, <&core_d4_ck>, <&core_d5_ck>, <&core_d6_ck>, <&core_d8_ck>, <&core_d9_ck>, <&core_d12_ck>, <&core_d16_ck>; - ti,bit-shift = <8>; - reg = <0x0240>; - }; - - dss1_fck: dss1_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&dss1_gate_fck>, <&dss1_mux_fck>; - }; - - dss2_gate_fck: dss2_gate_fck@200 { - #clock-cells = <0>; - compatible = "ti,composite-no-wait-gate-clock"; - clocks = <&func_48m_ck>; - ti,bit-shift = <1>; - reg = <0x0200>; - }; - - dss2_mux_fck: dss2_mux_fck@240 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&sys_ck>, <&func_48m_ck>; - ti,bit-shift = <13>; - reg = <0x0240>; - }; - - dss2_fck: dss2_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&dss2_gate_fck>, <&dss2_mux_fck>; - }; - - dss_54m_fck: dss_54m_fck@200 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&func_54m_ck>; - ti,bit-shift = <2>; - reg = <0x0200>; - }; - - ssi_ssr_sst_gate_fck: ssi_ssr_sst_gate_fck@204 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&core_ck>; - ti,bit-shift = <1>; - reg = <0x0204>; - }; - - ssi_ssr_sst_div_fck: ssi_ssr_sst_div_fck@240 { - #clock-cells = <0>; - compatible = "ti,composite-divider-clock"; - clocks = <&core_ck>; - ti,bit-shift = <20>; - reg = <0x0240>; - }; - - ssi_ssr_sst_fck: ssi_ssr_sst_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&ssi_ssr_sst_gate_fck>, <&ssi_ssr_sst_div_fck>; - }; - - usb_l4_gate_ick: usb_l4_gate_ick@214 { - #clock-cells = <0>; - compatible = "ti,composite-interface-clock"; - clocks = <&core_l3_ck>; - ti,bit-shift = <0>; - reg = <0x0214>; - }; - - usb_l4_div_ick: usb_l4_div_ick@240 { - #clock-cells = <0>; - compatible = "ti,composite-divider-clock"; - clocks = <&core_l3_ck>; - ti,bit-shift = <25>; - reg = <0x0240>; - ti,dividers = <0>, <1>, <2>, <0>, <4>; - }; - - usb_l4_ick: usb_l4_ick { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&usb_l4_gate_ick>, <&usb_l4_div_ick>; - }; - - ssi_l4_ick: ssi_l4_ick@214 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <1>; - reg = <0x0214>; - }; - - gpt1_ick: gpt1_ick@410 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&sys_ck>; - ti,bit-shift = <0>; - reg = <0x0410>; - }; - - gpt1_gate_fck: gpt1_gate_fck@400 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&func_32k_ck>; - ti,bit-shift = <0>; - reg = <0x0400>; - }; - - gpt1_mux_fck: gpt1_mux_fck@440 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>; - reg = <0x0440>; - }; - - gpt1_fck: gpt1_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&gpt1_gate_fck>, <&gpt1_mux_fck>; - }; - - gpt2_ick: gpt2_ick@210 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <4>; - reg = <0x0210>; - }; - - gpt2_gate_fck: gpt2_gate_fck@200 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&func_32k_ck>; - ti,bit-shift = <4>; - reg = <0x0200>; - }; - - gpt2_mux_fck: gpt2_mux_fck@244 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>; - ti,bit-shift = <2>; - reg = <0x0244>; - }; - - gpt2_fck: gpt2_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&gpt2_gate_fck>, <&gpt2_mux_fck>; - }; - - gpt3_ick: gpt3_ick@210 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <5>; - reg = <0x0210>; - }; - - gpt3_gate_fck: gpt3_gate_fck@200 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&func_32k_ck>; - ti,bit-shift = <5>; - reg = <0x0200>; - }; - - gpt3_mux_fck: gpt3_mux_fck@244 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>; - ti,bit-shift = <4>; - reg = <0x0244>; - }; - - gpt3_fck: gpt3_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&gpt3_gate_fck>, <&gpt3_mux_fck>; - }; - - gpt4_ick: gpt4_ick@210 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <6>; - reg = <0x0210>; - }; - - gpt4_gate_fck: gpt4_gate_fck@200 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&func_32k_ck>; - ti,bit-shift = <6>; - reg = <0x0200>; - }; - - gpt4_mux_fck: gpt4_mux_fck@244 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>; - ti,bit-shift = <6>; - reg = <0x0244>; - }; - - gpt4_fck: gpt4_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&gpt4_gate_fck>, <&gpt4_mux_fck>; - }; - - gpt5_ick: gpt5_ick@210 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <7>; - reg = <0x0210>; - }; - - gpt5_gate_fck: gpt5_gate_fck@200 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&func_32k_ck>; - ti,bit-shift = <7>; - reg = <0x0200>; - }; - - gpt5_mux_fck: gpt5_mux_fck@244 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>; - ti,bit-shift = <8>; - reg = <0x0244>; - }; - - gpt5_fck: gpt5_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&gpt5_gate_fck>, <&gpt5_mux_fck>; - }; - - gpt6_ick: gpt6_ick@210 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <8>; - reg = <0x0210>; - }; - - gpt6_gate_fck: gpt6_gate_fck@200 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&func_32k_ck>; - ti,bit-shift = <8>; - reg = <0x0200>; - }; - - gpt6_mux_fck: gpt6_mux_fck@244 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>; - ti,bit-shift = <10>; - reg = <0x0244>; - }; - - gpt6_fck: gpt6_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&gpt6_gate_fck>, <&gpt6_mux_fck>; - }; - - gpt7_ick: gpt7_ick@210 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <9>; - reg = <0x0210>; - }; - - gpt7_gate_fck: gpt7_gate_fck@200 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&func_32k_ck>; - ti,bit-shift = <9>; - reg = <0x0200>; - }; - - gpt7_mux_fck: gpt7_mux_fck@244 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>; - ti,bit-shift = <12>; - reg = <0x0244>; - }; - - gpt7_fck: gpt7_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&gpt7_gate_fck>, <&gpt7_mux_fck>; - }; - - gpt8_ick: gpt8_ick@210 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <10>; - reg = <0x0210>; - }; - - gpt8_gate_fck: gpt8_gate_fck@200 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&func_32k_ck>; - ti,bit-shift = <10>; - reg = <0x0200>; - }; - - gpt8_mux_fck: gpt8_mux_fck@244 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>; - ti,bit-shift = <14>; - reg = <0x0244>; - }; - - gpt8_fck: gpt8_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&gpt8_gate_fck>, <&gpt8_mux_fck>; - }; - - gpt9_ick: gpt9_ick@210 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <11>; - reg = <0x0210>; - }; - - gpt9_gate_fck: gpt9_gate_fck@200 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&func_32k_ck>; - ti,bit-shift = <11>; - reg = <0x0200>; - }; - - gpt9_mux_fck: gpt9_mux_fck@244 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>; - ti,bit-shift = <16>; - reg = <0x0244>; - }; - - gpt9_fck: gpt9_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&gpt9_gate_fck>, <&gpt9_mux_fck>; - }; - - gpt10_ick: gpt10_ick@210 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <12>; - reg = <0x0210>; - }; - - gpt10_gate_fck: gpt10_gate_fck@200 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&func_32k_ck>; - ti,bit-shift = <12>; - reg = <0x0200>; - }; - - gpt10_mux_fck: gpt10_mux_fck@244 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>; - ti,bit-shift = <18>; - reg = <0x0244>; - }; - - gpt10_fck: gpt10_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&gpt10_gate_fck>, <&gpt10_mux_fck>; - }; - - gpt11_ick: gpt11_ick@210 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <13>; - reg = <0x0210>; - }; - - gpt11_gate_fck: gpt11_gate_fck@200 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&func_32k_ck>; - ti,bit-shift = <13>; - reg = <0x0200>; - }; - - gpt11_mux_fck: gpt11_mux_fck@244 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>; - ti,bit-shift = <20>; - reg = <0x0244>; - }; - - gpt11_fck: gpt11_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&gpt11_gate_fck>, <&gpt11_mux_fck>; - }; - - gpt12_ick: gpt12_ick@210 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <14>; - reg = <0x0210>; - }; - - gpt12_gate_fck: gpt12_gate_fck@200 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&func_32k_ck>; - ti,bit-shift = <14>; - reg = <0x0200>; - }; - - gpt12_mux_fck: gpt12_mux_fck@244 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>; - ti,bit-shift = <22>; - reg = <0x0244>; - }; - - gpt12_fck: gpt12_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&gpt12_gate_fck>, <&gpt12_mux_fck>; - }; - - mcbsp1_ick: mcbsp1_ick@210 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <15>; - reg = <0x0210>; - }; - - mcbsp1_gate_fck: mcbsp1_gate_fck@200 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&mcbsp_clks>; - ti,bit-shift = <15>; - reg = <0x0200>; - }; - - mcbsp2_ick: mcbsp2_ick@210 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <16>; - reg = <0x0210>; - }; - - mcbsp2_gate_fck: mcbsp2_gate_fck@200 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&mcbsp_clks>; - ti,bit-shift = <16>; - reg = <0x0200>; - }; - - mcspi1_ick: mcspi1_ick@210 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <17>; - reg = <0x0210>; - }; - - mcspi1_fck: mcspi1_fck@200 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&func_48m_ck>; - ti,bit-shift = <17>; - reg = <0x0200>; - }; - - mcspi2_ick: mcspi2_ick@210 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <18>; - reg = <0x0210>; - }; - - mcspi2_fck: mcspi2_fck@200 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&func_48m_ck>; - ti,bit-shift = <18>; - reg = <0x0200>; - }; - - uart1_ick: uart1_ick@210 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <21>; - reg = <0x0210>; - }; - - uart1_fck: uart1_fck@200 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&func_48m_ck>; - ti,bit-shift = <21>; - reg = <0x0200>; - }; - - uart2_ick: uart2_ick@210 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <22>; - reg = <0x0210>; - }; - - uart2_fck: uart2_fck@200 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&func_48m_ck>; - ti,bit-shift = <22>; - reg = <0x0200>; - }; - - uart3_ick: uart3_ick@214 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <2>; - reg = <0x0214>; - }; - - uart3_fck: uart3_fck@204 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&func_48m_ck>; - ti,bit-shift = <2>; - reg = <0x0204>; - }; - - gpios_ick: gpios_ick@410 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&sys_ck>; - ti,bit-shift = <2>; - reg = <0x0410>; - }; - - gpios_fck: gpios_fck@400 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&func_32k_ck>; - ti,bit-shift = <2>; - reg = <0x0400>; - }; - - mpu_wdt_ick: mpu_wdt_ick@410 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&sys_ck>; - ti,bit-shift = <3>; - reg = <0x0410>; - }; - - mpu_wdt_fck: mpu_wdt_fck@400 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&func_32k_ck>; - ti,bit-shift = <3>; - reg = <0x0400>; - }; - - sync_32k_ick: sync_32k_ick@410 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&sys_ck>; - ti,bit-shift = <1>; - reg = <0x0410>; - }; - - wdt1_ick: wdt1_ick@410 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&sys_ck>; - ti,bit-shift = <4>; - reg = <0x0410>; - }; - - omapctrl_ick: omapctrl_ick@410 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&sys_ck>; - ti,bit-shift = <5>; - reg = <0x0410>; - }; - - cam_fck: cam_fck@200 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&func_96m_ck>; - ti,bit-shift = <31>; - reg = <0x0200>; - }; - - cam_ick: cam_ick@210 { - #clock-cells = <0>; - compatible = "ti,omap3-no-wait-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <31>; - reg = <0x0210>; - }; - - mailboxes_ick: mailboxes_ick@210 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <30>; - reg = <0x0210>; - }; - - wdt4_ick: wdt4_ick@210 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <29>; - reg = <0x0210>; - }; - - wdt4_fck: wdt4_fck@200 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&func_32k_ck>; - ti,bit-shift = <29>; - reg = <0x0200>; - }; - - mspro_ick: mspro_ick@210 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <27>; - reg = <0x0210>; - }; - - mspro_fck: mspro_fck@200 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&func_96m_ck>; - ti,bit-shift = <27>; - reg = <0x0200>; - }; - - fac_ick: fac_ick@210 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <25>; - reg = <0x0210>; - }; - - fac_fck: fac_fck@200 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&func_12m_ck>; - ti,bit-shift = <25>; - reg = <0x0200>; - }; - - hdq_ick: hdq_ick@210 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <23>; - reg = <0x0210>; - }; - - hdq_fck: hdq_fck@200 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&func_12m_ck>; - ti,bit-shift = <23>; - reg = <0x0200>; - }; - - i2c1_ick: i2c1_ick@210 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <19>; - reg = <0x0210>; - }; - - i2c2_ick: i2c2_ick@210 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <20>; - reg = <0x0210>; - }; - - gpmc_fck: gpmc_fck@238 { - #clock-cells = <0>; - compatible = "ti,fixed-factor-clock"; - clocks = <&core_l3_ck>; - ti,clock-div = <1>; - ti,autoidle-shift = <1>; - reg = <0x0238>; - ti,clock-mult = <1>; - }; - - sdma_fck: sdma_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&core_l3_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - sdma_ick: sdma_ick@238 { - #clock-cells = <0>; - compatible = "ti,fixed-factor-clock"; - clocks = <&core_l3_ck>; - ti,clock-div = <1>; - ti,autoidle-shift = <0>; - reg = <0x0238>; - ti,clock-mult = <1>; - }; - - sdrc_ick: sdrc_ick@238 { - #clock-cells = <0>; - compatible = "ti,fixed-factor-clock"; - clocks = <&core_l3_ck>; - ti,clock-div = <1>; - ti,autoidle-shift = <2>; - reg = <0x0238>; - ti,clock-mult = <1>; - }; - - des_ick: des_ick@21c { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <0>; - reg = <0x021c>; - }; - - sha_ick: sha_ick@21c { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <1>; - reg = <0x021c>; - }; - - rng_ick: rng_ick@21c { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <2>; - reg = <0x021c>; - }; - - aes_ick: aes_ick@21c { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <3>; - reg = <0x021c>; - }; - - pka_ick: pka_ick@21c { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <4>; - reg = <0x021c>; - }; - - usb_fck: usb_fck@204 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&func_48m_ck>; - ti,bit-shift = <0>; - reg = <0x0204>; - }; -}; diff --git a/sys/gnu/dts/arm/omap3-beagle-xm-ab.dts b/sys/gnu/dts/arm/omap3-beagle-xm-ab.dts deleted file mode 100644 index e498495b846..00000000000 --- a/sys/gnu/dts/arm/omap3-beagle-xm-ab.dts +++ /dev/null @@ -1,13 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ - */ - -#include "omap3-beagle-xm.dts" - -/ { - /* HS USB Port 2 Power enable was inverted with the xM C */ - hsusb2_power: hsusb2_power_reg { - enable-active-high; - }; -}; diff --git a/sys/gnu/dts/arm/omap3-beagle-xm.dts b/sys/gnu/dts/arm/omap3-beagle-xm.dts deleted file mode 100644 index 1aa99fc1487..00000000000 --- a/sys/gnu/dts/arm/omap3-beagle-xm.dts +++ /dev/null @@ -1,419 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ - */ -/dts-v1/; - -#include "omap36xx.dtsi" - -/ { - model = "TI OMAP3 BeagleBoard xM"; - compatible = "ti,omap3-beagle-xm", "ti,omap36xx", "ti,omap3"; - - cpus { - cpu@0 { - cpu0-supply = <&vcc>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000>; /* 512 MB */ - }; - - aliases { - display0 = &dvi0; - display1 = &tv0; - ethernet = ðernet; - }; - - /* fixed 26MHz oscillator */ - hfclk_26m: oscillator { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <26000000>; - }; - - leds { - compatible = "gpio-leds"; - - heartbeat { - label = "beagleboard::usr0"; - gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>; /* 150 -> D6 LED */ - linux,default-trigger = "heartbeat"; - }; - - mmc { - label = "beagleboard::usr1"; - gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; /* 149 -> D7 LED */ - linux,default-trigger = "mmc0"; - }; - }; - - pwmleds { - compatible = "pwm-leds"; - - pmu_stat { - label = "beagleboard::pmu_stat"; - pwms = <&twl_pwmled 1 7812500>; - max-brightness = <127>; - }; - }; - - sound { - compatible = "ti,omap-twl4030"; - ti,model = "omap3beagle"; - - ti,mcbsp = <&mcbsp2>; - }; - - gpio_keys { - compatible = "gpio-keys"; - - user { - label = "user"; - gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; - linux,code = <0x114>; - wakeup-source; - }; - - }; - - /* HS USB Port 2 Power */ - hsusb2_power: hsusb2_power_reg { - compatible = "regulator-fixed"; - regulator-name = "hsusb2_vbus"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&twl_gpio 18 GPIO_ACTIVE_HIGH>; /* GPIO LEDA */ - startup-delay-us = <70000>; - }; - - /* HS USB Host PHY on PORT 2 */ - hsusb2_phy: hsusb2_phy { - compatible = "usb-nop-xceiv"; - reset-gpios = <&gpio5 19 GPIO_ACTIVE_LOW>; /* gpio_147 */ - vcc-supply = <&hsusb2_power>; - #phy-cells = <0>; - }; - - tfp410: encoder0 { - compatible = "ti,tfp410"; - powerdown-gpios = <&twl_gpio 2 GPIO_ACTIVE_LOW>; - - /* XXX pinctrl from twl */ - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - tfp410_in: endpoint { - remote-endpoint = <&dpi_out>; - }; - }; - - port@1 { - reg = <1>; - - tfp410_out: endpoint { - remote-endpoint = <&dvi_connector_in>; - }; - }; - }; - }; - - dvi0: connector0 { - compatible = "dvi-connector"; - label = "dvi"; - - digital; - - ddc-i2c-bus = <&i2c3>; - - port { - dvi_connector_in: endpoint { - remote-endpoint = <&tfp410_out>; - }; - }; - }; - - tv0: connector1 { - compatible = "svideo-connector"; - label = "tv"; - - port { - tv_connector_in: endpoint { - remote-endpoint = <&venc_out>; - }; - }; - }; - - etb@5401b000 { - compatible = "arm,coresight-etb10", "arm,primecell"; - reg = <0x5401b000 0x1000>; - - clocks = <&emu_src_ck>; - clock-names = "apb_pclk"; - in-ports { - port { - etb_in: endpoint { - remote-endpoint = <&etm_out>; - }; - }; - }; - }; - - etm@54010000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0x54010000 0x1000>; - - clocks = <&emu_src_ck>; - clock-names = "apb_pclk"; - out-ports { - port { - etm_out: endpoint { - remote-endpoint = <&etb_in>; - }; - }; - }; - }; -}; - -&omap3_pmx_wkup { - gpio1_pins: pinmux_gpio1_pins { - pinctrl-single,pins = < - OMAP3_WKUP_IOPAD(0x2a0e, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE4) /* sys_boot2.gpio_4 */ - >; - }; - - dss_dpi_pins2: pinmux_dss_dpi_pins1 { - pinctrl-single,pins = < - OMAP3_WKUP_IOPAD(0x2a0a, PIN_OUTPUT | MUX_MODE3) /* sys_boot0.dss_data18 */ - OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE3) /* sys_boot1.dss_data19 */ - OMAP3_WKUP_IOPAD(0x2a10, PIN_OUTPUT | MUX_MODE3) /* sys_boot3.dss_data20 */ - OMAP3_WKUP_IOPAD(0x2a12, PIN_OUTPUT | MUX_MODE3) /* sys_boot4.dss_data21 */ - OMAP3_WKUP_IOPAD(0x2a14, PIN_OUTPUT | MUX_MODE3) /* sys_boot5.dss_data22 */ - OMAP3_WKUP_IOPAD(0x2a16, PIN_OUTPUT | MUX_MODE3) /* sys_boot6.dss_data23 */ - >; - }; -}; - -&omap3_pmx_core { - pinctrl-names = "default"; - pinctrl-0 = < - &hsusb2_pins - >; - - uart3_pins: pinmux_uart3_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ - OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx OUTPUT | MODE0 */ - >; - }; - - hsusb2_pins: pinmux_hsusb2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */ - OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */ - OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */ - OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */ - OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */ - OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */ - >; - }; - - dss_dpi_pins1: pinmux_dss_dpi_pins2 { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ - OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ - OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ - OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ - - OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ - OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ - OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ - OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ - OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ - OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ - OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ - OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ - OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ - OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ - OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ - OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ - - OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE3) /* dss_data18.dss_data0 */ - OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE3) /* dss_data19.dss_data1 */ - OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE3) /* dss_data20.dss_data2 */ - OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE3) /* dss_data21.dss_data3 */ - OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE3) /* dss_data22.dss_data4 */ - OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE3) /* dss_data23.dss_data5 */ - >; - }; -}; - -&omap3_pmx_core2 { - pinctrl-names = "default"; - pinctrl-0 = < - &hsusb2_2_pins - >; - - hsusb2_2_pins: pinmux_hsusb2_2_pins { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ - OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ - OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ - OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ - OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ - OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ - >; - }; -}; - -&i2c1 { - clock-frequency = <2600000>; - - twl: twl@48 { - reg = <0x48>; - interrupts = <7>; /* SYS_NIRQ cascaded to intc */ - interrupt-parent = <&intc>; - - clocks = <&hfclk_26m>; - clock-names = "fck"; - - twl_audio: audio { - compatible = "ti,twl4030-audio"; - codec { - }; - }; - - twl_power: power { - compatible = "ti,twl4030-power-beagleboard-xm", "ti,twl4030-power-idle-osc-off"; - ti,use_poweroff; - }; - }; -}; - -#include "twl4030.dtsi" -#include "twl4030_omap3.dtsi" - -&i2c2 { - clock-frequency = <400000>; -}; - -&i2c3 { - clock-frequency = <100000>; -}; - -&mmc1 { - vmmc-supply = <&vmmc1>; - vqmmc-supply = <&vsim>; - bus-width = <8>; -}; - -&mmc2 { - status = "disabled"; -}; - -&mmc3 { - status = "disabled"; -}; - -&twl_gpio { - ti,use-leds; - /* pullups: BIT(1) */ - ti,pullups = <0x000002>; - /* - * pulldowns: - * BIT(2), BIT(6), BIT(7), BIT(8), BIT(13) - * BIT(15), BIT(16), BIT(17) - */ - ti,pulldowns = <0x03a1c4>; -}; - -&usb_otg_hs { - interface-type = <0>; - usb-phy = <&usb2_phy>; - phys = <&usb2_phy>; - phy-names = "usb2-phy"; - mode = <3>; - power = <50>; -}; - -&uart3 { - interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>; - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; -}; - -&gpio1 { - pinctrl-names = "default"; - pinctrl-0 = <&gpio1_pins>; -}; - -&usbhshost { - port2-mode = "ehci-phy"; -}; - -&usbhsehci { - phys = <0 &hsusb2_phy>; - - #address-cells = <1>; - #size-cells = <0>; - - hub@2 { - compatible = "usb424,9514"; - reg = <2>; - #address-cells = <1>; - #size-cells = <0>; - - ethernet: usbether@1 { - compatible = "usb424,ec00"; - reg = <1>; - }; - }; -}; - -&vaux2 { - regulator-name = "usb_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; -}; - -&mcbsp2 { - status = "okay"; -}; - -&dss { - status = "ok"; - - pinctrl-names = "default"; - pinctrl-0 = < - &dss_dpi_pins1 - &dss_dpi_pins2 - >; - - port { - dpi_out: endpoint { - remote-endpoint = <&tfp410_in>; - data-lines = <24>; - }; - }; -}; - -&venc { - status = "ok"; - - vdda-supply = <&vdac>; - - port { - venc_out: endpoint { - remote-endpoint = <&tv_connector_in>; - ti,channels = <2>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/omap3-beagle.dts b/sys/gnu/dts/arm/omap3-beagle.dts deleted file mode 100644 index e3df3c16690..00000000000 --- a/sys/gnu/dts/arm/omap3-beagle.dts +++ /dev/null @@ -1,436 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ - */ -/dts-v1/; - -#include "omap34xx.dtsi" - -/ { - model = "TI OMAP3 BeagleBoard"; - compatible = "ti,omap3-beagle", "ti,omap3"; - - cpus { - cpu@0 { - cpu0-supply = <&vcc>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x10000000>; /* 256 MB */ - }; - - aliases { - display0 = &dvi0; - display1 = &tv0; - }; - - leds { - compatible = "gpio-leds"; - pmu_stat { - label = "beagleboard::pmu_stat"; - gpios = <&twl_gpio 19 GPIO_ACTIVE_HIGH>; /* LEDB */ - }; - - heartbeat { - label = "beagleboard::usr0"; - gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>; /* 150 -> D6 LED */ - linux,default-trigger = "heartbeat"; - }; - - mmc { - label = "beagleboard::usr1"; - gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; /* 149 -> D7 LED */ - linux,default-trigger = "mmc0"; - }; - }; - - /* HS USB Port 2 Power */ - hsusb2_power: hsusb2_power_reg { - compatible = "regulator-fixed"; - regulator-name = "hsusb2_vbus"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&twl_gpio 18 GPIO_ACTIVE_HIGH>; /* GPIO LEDA */ - startup-delay-us = <70000>; - }; - - /* HS USB Host PHY on PORT 2 */ - hsusb2_phy: hsusb2_phy { - compatible = "usb-nop-xceiv"; - reset-gpios = <&gpio5 19 GPIO_ACTIVE_LOW>; /* gpio_147 */ - vcc-supply = <&hsusb2_power>; - #phy-cells = <0>; - }; - - sound { - compatible = "ti,omap-twl4030"; - ti,model = "omap3beagle"; - - ti,mcbsp = <&mcbsp2>; - }; - - gpio_keys { - compatible = "gpio-keys"; - - user { - label = "user"; - gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; - linux,code = <0x114>; - wakeup-source; - }; - - }; - - tfp410: encoder0 { - compatible = "ti,tfp410"; - powerdown-gpios = <&gpio6 10 GPIO_ACTIVE_LOW>; /* gpio_170 */ - - pinctrl-names = "default"; - pinctrl-0 = <&tfp410_pins>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - tfp410_in: endpoint { - remote-endpoint = <&dpi_out>; - }; - }; - - port@1 { - reg = <1>; - - tfp410_out: endpoint { - remote-endpoint = <&dvi_connector_in>; - }; - }; - }; - }; - - dvi0: connector0 { - compatible = "dvi-connector"; - label = "dvi"; - - digital; - - ddc-i2c-bus = <&i2c3>; - - port { - dvi_connector_in: endpoint { - remote-endpoint = <&tfp410_out>; - }; - }; - }; - - tv0: connector1 { - compatible = "svideo-connector"; - label = "tv"; - - port { - tv_connector_in: endpoint { - remote-endpoint = <&venc_out>; - }; - }; - }; - - etb@540000000 { - compatible = "arm,coresight-etb10", "arm,primecell"; - reg = <0x5401b000 0x1000>; - - clocks = <&emu_src_ck>; - clock-names = "apb_pclk"; - in-ports { - port { - etb_in: endpoint { - remote-endpoint = <&etm_out>; - }; - }; - }; - }; - - etm@54010000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0x54010000 0x1000>; - - clocks = <&emu_src_ck>; - clock-names = "apb_pclk"; - out-ports { - port { - etm_out: endpoint { - remote-endpoint = <&etb_in>; - }; - }; - }; - }; -}; - -&omap3_pmx_wkup { - gpio1_pins: pinmux_gpio1_pins { - pinctrl-single,pins = < - OMAP3_WKUP_IOPAD(0x2a14, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE4) /* sys_boot5.gpio_7 */ - >; - }; -}; - -&omap3_pmx_core { - pinctrl-names = "default"; - pinctrl-0 = < - &hsusb2_pins - >; - - hsusb2_pins: pinmux_hsusb2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */ - OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */ - OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */ - OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */ - OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */ - OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */ - >; - }; - - uart3_pins: pinmux_uart3_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ - OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ - >; - }; - - tfp410_pins: pinmux_tfp410_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21c6, PIN_OUTPUT | MUX_MODE4) /* hdq_sio.gpio_170 */ - >; - }; - - dss_dpi_pins: pinmux_dss_dpi_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ - OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ - OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ - OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ - OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ - OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ - OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ - OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ - OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ - OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ - OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ - OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ - OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ - OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ - OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ - OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ - OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ - OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ - OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ - OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ - OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ - OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ - OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */ - OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */ - OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */ - OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */ - OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ - OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ - >; - }; -}; - -&omap3_pmx_core2 { - pinctrl-names = "default"; - pinctrl-0 = < - &hsusb2_2_pins - >; - - hsusb2_2_pins: pinmux_hsusb2_2_pins { - pinctrl-single,pins = < - OMAP3430_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ - OMAP3430_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ - OMAP3430_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ - OMAP3430_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ - OMAP3430_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ - OMAP3430_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ - >; - }; -}; - -&i2c1 { - clock-frequency = <2600000>; - - twl: twl@48 { - reg = <0x48>; - interrupts = <7>; /* SYS_NIRQ cascaded to intc */ - interrupt-parent = <&intc>; - - twl_audio: audio { - compatible = "ti,twl4030-audio"; - codec { - }; - }; - }; -}; - -#include "twl4030.dtsi" -#include "twl4030_omap3.dtsi" - -&i2c3 { - clock-frequency = <100000>; -}; - -&mmc1 { - vmmc-supply = <&vmmc1>; - vqmmc-supply = <&vsim>; - bus-width = <8>; -}; - -&mmc2 { - status = "disabled"; -}; - -&mmc3 { - status = "disabled"; -}; - -&usbhshost { - port2-mode = "ehci-phy"; -}; - -&usbhsehci { - phys = <0 &hsusb2_phy>; -}; - -&twl_gpio { - ti,use-leds; - /* pullups: BIT(1) */ - ti,pullups = <0x000002>; - /* - * pulldowns: - * BIT(2), BIT(6), BIT(7), BIT(8), BIT(13) - * BIT(15), BIT(16), BIT(17) - */ - ti,pulldowns = <0x03a1c4>; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; - interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>; -}; - -&gpio1 { - pinctrl-names = "default"; - pinctrl-0 = <&gpio1_pins>; -}; - -&usb_otg_hs { - interface-type = <0>; - usb-phy = <&usb2_phy>; - phys = <&usb2_phy>; - phy-names = "usb2-phy"; - mode = <3>; - power = <50>; -}; - -&vaux2 { - regulator-name = "vdd_ehci"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; -}; - -&mcbsp2 { - status = "okay"; -}; - -/* Needed to power the DPI pins */ -&vpll2 { - regulator-always-on; -}; - -&dss { - status = "ok"; - - pinctrl-names = "default"; - pinctrl-0 = <&dss_dpi_pins>; - - port { - dpi_out: endpoint { - remote-endpoint = <&tfp410_in>; - data-lines = <24>; - }; - }; -}; - -&venc { - status = "ok"; - - vdda-supply = <&vdac>; - - port { - venc_out: endpoint { - remote-endpoint = <&tv_connector_in>; - ti,channels = <2>; - }; - }; -}; - -&gpmc { - status = "ok"; - ranges = <0 0 0x30000000 0x1000000>; /* CS0 space, 16MB */ - - /* Chip select 0 */ - nand@0,0 { - compatible = "ti,omap2-nand"; - reg = <0 0 4>; /* NAND I/O window, 4 bytes */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ - <1 IRQ_TYPE_NONE>; /* termcount */ - ti,nand-ecc-opt = "ham1"; - rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ - nand-bus-width = <16>; - #address-cells = <1>; - #size-cells = <1>; - - gpmc,device-width = <2>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <36>; - gpmc,cs-wr-off-ns = <36>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <24>; - gpmc,adv-wr-off-ns = <36>; - gpmc,oe-on-ns = <6>; - gpmc,oe-off-ns = <48>; - gpmc,we-on-ns = <6>; - gpmc,we-off-ns = <30>; - gpmc,rd-cycle-ns = <72>; - gpmc,wr-cycle-ns = <72>; - gpmc,access-ns = <54>; - gpmc,wr-access-ns = <30>; - - partition@0 { - label = "X-Loader"; - reg = <0 0x80000>; - }; - partition@80000 { - label = "U-Boot"; - reg = <0x80000 0x1e0000>; - }; - partition@1c0000 { - label = "U-Boot Env"; - reg = <0x260000 0x20000>; - }; - partition@280000 { - label = "Kernel"; - reg = <0x280000 0x400000>; - }; - partition@780000 { - label = "Filesystem"; - reg = <0x680000 0xf980000>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/omap3-cm-t3517.dts b/sys/gnu/dts/arm/omap3-cm-t3517.dts deleted file mode 100644 index 632f52efdf9..00000000000 --- a/sys/gnu/dts/arm/omap3-cm-t3517.dts +++ /dev/null @@ -1,158 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Support for CompuLab CM-T3517 - */ -/dts-v1/; - -#include "am3517.dtsi" -#include "omap3-cm-t3x.dtsi" - -/ { - model = "CompuLab CM-T3517"; - compatible = "compulab,omap3-cm-t3517", "ti,am3517", "ti,omap3"; - - vmmc: regulator-vmmc { - compatible = "regulator-fixed"; - regulator-name = "vmmc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - wl12xx_vmmc2: wl12xx_vmmc2 { - compatible = "regulator-fixed"; - regulator-name = "vw1271"; - pinctrl-names = "default"; - pinctrl-0 = < - &wl12xx_wkup_pins - &wl12xx_core_pins - >; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio1 6 GPIO_ACTIVE_HIGH >; /* gpio6 */ - startup-delay-us = <20000>; - enable-active-high; - }; - - wl12xx_vaux2: wl12xx_vaux2 { - compatible = "regulator-fixed"; - regulator-name = "vwl1271_vaux2"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; -}; - -&omap3_pmx_wkup { - - wl12xx_wkup_pins: pinmux_wl12xx_wkup_pins { - pinctrl-single,pins = < - OMAP3_WKUP_IOPAD(0x2a0e, PIN_OUTPUT | MUX_MODE4) /* sys_boot2.gpio_4 */ - OMAP3_WKUP_IOPAD(0x2a12, PIN_OUTPUT | MUX_MODE4) /* sys_boot4.gpio_6 */ - >; - }; -}; - -&omap3_pmx_core { - - phy1_reset_pins: pinmux_hsusb1_phy_reset_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE4) /* uart2_tx.gpio_146 */ - >; - }; - - phy2_reset_pins: pinmux_hsusb2_phy_reset_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x217a, PIN_OUTPUT | MUX_MODE4) /* uart2_rx.gpio_147 */ - >; - }; - - otg_drv_vbus: pinmux_otg_drv_vbus { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2210, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii_50MHz_clk.usb0_drvvbus */ - >; - }; - - mmc2_pins: pinmux_mmc2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ - OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ - OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ - OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ - OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ - OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ - >; - }; - - wl12xx_core_pins: pinmux_wl12xx_core_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20b8, PIN_OUTPUT | MUX_MODE4) /* gpmc_ncs5.gpio_56 */ - OMAP3_CORE1_IOPAD(0x2176, PIN_INPUT_PULLUP | MUX_MODE4) /* uart2_rts.gpio_145 */ - >; - }; - - usb_hub_pins: pinmux_usb_hub_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2184, PIN_OUTPUT | MUX_MODE4) /* mcbsp4_clkx.gpio_152 - USB HUB RST */ - >; - }; -}; - -&hsusb1_phy { - pinctrl-names = "default"; - pinctrl-0 = <&phy1_reset_pins>; - reset-gpios = <&gpio5 18 GPIO_ACTIVE_LOW>; -}; - -&hsusb2_phy { - pinctrl-names = "default"; - pinctrl-0 = <&phy2_reset_pins>; - reset-gpios = <&gpio5 19 GPIO_ACTIVE_LOW>; -}; - -&davinci_emac { - status = "okay"; -}; - -&davinci_mdio { - status = "okay"; -}; - -&am35x_otg_hs { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&otg_drv_vbus>; -}; - -&mmc1 { - vmmc-supply = <&vmmc>; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; - vmmc-supply = <&wl12xx_vmmc2>; - vqmmc-supply = <&wl12xx_vaux2>; - non-removable; - bus-width = <4>; - cap-power-off-card; - - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@2 { - compatible = "ti,wl1271"; - reg = <2>; - interrupt-parent = <&gpio5>; - interrupts = <17 IRQ_TYPE_EDGE_RISING>; /* gpio 145 */ - ref-clock-frequency = <38400000>; - }; -}; - -&dss { - status = "ok"; - - pinctrl-names = "default"; - pinctrl-0 = < - &dss_dpi_pins_common - &dss_dpi_pins_cm_t35x - >; -}; - diff --git a/sys/gnu/dts/arm/omap3-cm-t3530.dts b/sys/gnu/dts/arm/omap3-cm-t3530.dts deleted file mode 100644 index 76e52c78cbb..00000000000 --- a/sys/gnu/dts/arm/omap3-cm-t3530.dts +++ /dev/null @@ -1,60 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Support for CompuLab CM-T3530 - */ -/dts-v1/; - -#include "omap34xx.dtsi" -#include "omap3-cm-t3x30.dtsi" - -/ { - model = "CompuLab CM-T3530"; - compatible = "compulab,omap3-cm-t3530", "ti,omap34xx", "ti,omap3"; - - /* Regulator to trigger the reset signal of the Wifi module */ - mmc2_sdio_reset: regulator-mmc2-sdio-reset { - compatible = "regulator-fixed"; - regulator-name = "regulator-mmc2-sdio-reset"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&twl_gpio 2 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&omap3_pmx_core { - mmc2_pins: pinmux_mmc2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ - OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ - OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ - OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ - OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ - OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ - OMAP3_CORE1_IOPAD(0x2164, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat4.sdmmc2_dir_dat0 */ - OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat5.sdmmc2_dir_dat1 */ - OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat6.sdmmc2_dir_cmd */ - OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT | MUX_MODE1) /* sdmmc2_dat7.sdmmc2_clkin */ - >; - }; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; - vmmc-supply = <&mmc2_sdio_reset>; - non-removable; - bus-width = <4>; - cap-power-off-card; -}; - -&dss { - status = "ok"; - - pinctrl-names = "default"; - pinctrl-0 = < - &dss_dpi_pins_common - &dss_dpi_pins_cm_t35x - >; -}; - diff --git a/sys/gnu/dts/arm/omap3-cm-t3730.dts b/sys/gnu/dts/arm/omap3-cm-t3730.dts deleted file mode 100644 index 6e944dfa0f3..00000000000 --- a/sys/gnu/dts/arm/omap3-cm-t3730.dts +++ /dev/null @@ -1,98 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Support for CompuLab CM-T3730 - */ -/dts-v1/; - -#include "omap36xx.dtsi" -#include "omap3-cm-t3x30.dtsi" - -/ { - model = "CompuLab CM-T3730"; - compatible = "compulab,omap3-cm-t3730", "ti,omap36xx", "ti,omap3"; - - wl12xx_vmmc2: wl12xx_vmmc2 { - compatible = "regulator-fixed"; - regulator-name = "vw1271"; - pinctrl-names = "default"; - pinctrl-0 = <&wl12xx_gpio>; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio3 9 GPIO_ACTIVE_HIGH>; /* gpio73 */ - startup-delay-us = <20000>; - enable-active-high; - }; - - wl12xx_vaux2: wl12xx_vaux2 { - compatible = "regulator-fixed"; - regulator-name = "vwl1271_vaux2"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vaux2>; - }; -}; - -&omap3_pmx_wkup { - dss_dpi_pins_cm_t3730: pinmux_dss_dpi_pins_cm_t3730 { - pinctrl-single,pins = < - OMAP3_WKUP_IOPAD(0x2a08, PIN_OUTPUT | MUX_MODE3) /* sys_boot0.dss_data18 */ - OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE3) /* sys_boot1.dss_data19 */ - OMAP3_WKUP_IOPAD(0x2a10, PIN_OUTPUT | MUX_MODE3) /* sys_boot3.dss_data20 */ - OMAP3_WKUP_IOPAD(0x2a12, PIN_OUTPUT | MUX_MODE3) /* sys_boot4.dss_data21 */ - OMAP3_WKUP_IOPAD(0x2a14, PIN_OUTPUT | MUX_MODE3) /* sys_boot5.dss_data22 */ - OMAP3_WKUP_IOPAD(0x2a16, PIN_OUTPUT | MUX_MODE3) /* sys_boot6.dss_data23 */ - >; - }; -}; - -&omap3_pmx_core { - - mmc2_pins: pinmux_mmc2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ - OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ - OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ - OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ - OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ - OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ - >; - }; - - wl12xx_gpio: pinmux_wl12xx_gpio { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE4) /* dss_data3.gpio_73 */ - OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT | MUX_MODE4) /* sdmmc2_dat4.gpio_136 */ - >; - }; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; - vmmc-supply = <&wl12xx_vmmc2>; - vqmmc-supply = <&wl12xx_vaux2>; - non-removable; - bus-width = <4>; - cap-power-off-card; - - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@2 { - compatible = "ti,wl1271"; - reg = <2>; - interrupt-parent = <&gpio5>; - interrupts = <8 IRQ_TYPE_EDGE_RISING>; /* gpio 136 */ - ref-clock-frequency = <38400000>; - }; -}; - -&dss { - status = "ok"; - - pinctrl-names = "default"; - pinctrl-0 = < - &dss_dpi_pins_common - &dss_dpi_pins_cm_t3730 - >; -}; - diff --git a/sys/gnu/dts/arm/omap3-cm-t3x.dtsi b/sys/gnu/dts/arm/omap3-cm-t3x.dtsi deleted file mode 100644 index cdb632df152..00000000000 --- a/sys/gnu/dts/arm/omap3-cm-t3x.dtsi +++ /dev/null @@ -1,326 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Common support for CompuLab CM-T3x CoMs - */ - -/ { - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x10000000>; /* 256 MB */ - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&green_led_pins>; - ledb { - label = "cm-t3x:green"; - gpios = <&gpio6 26 GPIO_ACTIVE_HIGH>; /* gpio186 */ - linux,default-trigger = "heartbeat"; - }; - }; - - /* HS USB Port 1 Power */ - hsusb1_power: hsusb1_power_reg { - compatible = "regulator-fixed"; - regulator-name = "hsusb1_vbus"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <70000>; - }; - - /* HS USB Port 2 Power */ - hsusb2_power: hsusb2_power_reg { - compatible = "regulator-fixed"; - regulator-name = "hsusb2_vbus"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <70000>; - }; - - /* HS USB Host PHY on PORT 1 */ - hsusb1_phy: hsusb1_phy { - compatible = "usb-nop-xceiv"; - vcc-supply = <&hsusb1_power>; - #phy-cells = <0>; - }; - - /* HS USB Host PHY on PORT 2 */ - hsusb2_phy: hsusb2_phy { - compatible = "usb-nop-xceiv"; - vcc-supply = <&hsusb2_power>; - #phy-cells = <0>; - }; - - ads7846reg: ads7846-reg { - compatible = "regulator-fixed"; - regulator-name = "ads7846-reg"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - tv0: svideo-connector { - compatible = "svideo-connector"; - label = "tv"; - - port { - tv_connector_in: endpoint { - remote-endpoint = <&venc_out>; - }; - }; - }; -}; - -&omap3_pmx_core { - - uart3_pins: pinmux_uart3_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ - OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ - >; - }; - - mmc1_pins: pinmux_mmc1_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ - OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ - OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ - OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ - OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ - OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ - >; - }; - - green_led_pins: pinmux_green_led_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21e2, PIN_OUTPUT | MUX_MODE4) /* sys_clkout2.gpio_186 */ - >; - }; - - dss_dpi_pins_common: pinmux_dss_dpi_pins_common { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ - OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ - OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ - OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ - - OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ - OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ - OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ - OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ - OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ - OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ - OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ - OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ - OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ - OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ - OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ - OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ - OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */ - OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */ - OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */ - OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */ - OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ - OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ - >; - }; - - dss_dpi_pins_cm_t35x: pinmux_dss_dpi_pins_cm_t35x { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ - OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ - OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ - OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ - OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ - OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ - >; - }; - - ads7846_pins: pinmux_ads7846_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20ba, PIN_INPUT_PULLUP | MUX_MODE4) /* gpmc_ncs6.gpio_57 */ - >; - }; - - mcspi1_pins: pinmux_mcspi1_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0) /* mcspi1_clk */ - OMAP3_CORE1_IOPAD(0x21ca, PIN_INPUT | MUX_MODE0) /* mcspi1_simo */ - OMAP3_CORE1_IOPAD(0x21cc, PIN_INPUT | MUX_MODE0) /* mcspi1_somi */ - OMAP3_CORE1_IOPAD(0x21ce, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcspi1_cs0 */ - >; - }; - - i2c1_pins: pinmux_i2c1_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */ - OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */ - >; - }; - - mcbsp2_pins: pinmux_mcbsp2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx */ - OMAP3_CORE1_IOPAD(0x213e, PIN_INPUT | MUX_MODE0) /* mcbsp2_clkx */ - OMAP3_CORE1_IOPAD(0x2140, PIN_INPUT | MUX_MODE0) /* mcbsp2_dr */ - OMAP3_CORE1_IOPAD(0x2142, PIN_OUTPUT | MUX_MODE0) /* mcbsp2_dx */ - >; - }; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - bus-width = <4>; -}; - -&mmc3 { - status = "disabled"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - - clock-frequency = <400000>; - - at24@50 { - compatible = "atmel,24c02"; - pagesize = <16>; - reg = <0x50>; - }; -}; - -&i2c3 { - clock-frequency = <400000>; -}; - -&usbhshost { - port1-mode = "ehci-phy"; - port2-mode = "ehci-phy"; -}; - -&usbhsehci { - phys = <&hsusb1_phy &hsusb2_phy>; -}; - -&mcspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&mcspi1_pins>; - - /* touch controller */ - ads7846@0 { - pinctrl-names = "default"; - pinctrl-0 = <&ads7846_pins>; - - compatible = "ti,ads7846"; - vcc-supply = <&ads7846reg>; - - reg = <0>; /* CS0 */ - spi-max-frequency = <1500000>; - - interrupt-parent = <&gpio2>; - interrupts = <25 0>; /* gpio_57 */ - pendown-gpio = <&gpio2 25 GPIO_ACTIVE_HIGH>; - - ti,x-min = /bits/ 16 <0x0>; - ti,x-max = /bits/ 16 <0x0fff>; - ti,y-min = /bits/ 16 <0x0>; - ti,y-max = /bits/ 16 <0x0fff>; - - ti,x-plate-ohms = /bits/ 16 <180>; - ti,pressure-max = /bits/ 16 <255>; - - ti,debounce-max = /bits/ 16 <30>; - ti,debounce-tol = /bits/ 16 <10>; - ti,debounce-rep = /bits/ 16 <1>; - - wakeup-source; - }; -}; - -&venc { - status = "ok"; - - port { - venc_out: endpoint { - remote-endpoint = <&tv_connector_in>; - ti,channels = <2>; - }; - }; -}; - -&mcbsp2 { - status = "ok"; - - pinctrl-names = "default"; - pinctrl-0 = <&mcbsp2_pins>; -}; - -&gpmc { - ranges = <0 0 0x30000000 0x01000000>; /* CS0: 16MB for NAND */ - - nand@0,0 { - compatible = "ti,omap2-nand"; - reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ - <1 IRQ_TYPE_NONE>; /* termcount */ - nand-bus-width = <8>; - gpmc,device-width = <1>; - ti,nand-ecc-opt = "sw"; - - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <120>; - gpmc,cs-wr-off-ns = <120>; - - gpmc,adv-on-ns = <0>; - gpmc,adv-rd-off-ns = <120>; - gpmc,adv-wr-off-ns = <120>; - - gpmc,we-on-ns = <6>; - gpmc,we-off-ns = <90>; - - gpmc,oe-on-ns = <6>; - gpmc,oe-off-ns = <90>; - - gpmc,page-burst-access-ns = <6>; - gpmc,access-ns = <72>; - gpmc,cycle2cycle-delay-ns = <60>; - - gpmc,rd-cycle-ns = <120>; - gpmc,wr-cycle-ns = <120>; - gpmc,wr-access-ns = <186>; - gpmc,wr-data-mux-bus-ns = <90>; - - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "xloader"; - reg = <0 0x80000>; - }; - partition@80000 { - label = "uboot"; - reg = <0x80000 0x1e0000>; - }; - partition@260000 { - label = "uboot environment"; - reg = <0x260000 0x40000>; - }; - partition@2a0000 { - label = "linux"; - reg = <0x2a0000 0x400000>; - }; - partition@6a0000 { - label = "rootfs"; - reg = <0x6a0000 0x1f880000>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/omap3-cm-t3x30.dtsi b/sys/gnu/dts/arm/omap3-cm-t3x30.dtsi deleted file mode 100644 index 5e8943539fc..00000000000 --- a/sys/gnu/dts/arm/omap3-cm-t3x30.dtsi +++ /dev/null @@ -1,131 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Common support for CompuLab CM-T3x30 CoMs - */ - -#include "omap3-cm-t3x.dtsi" - -/ { - cpus { - cpu@0 { - cpu0-supply = <&vcc>; - }; - }; - - sound { - compatible = "ti,omap-twl4030"; - ti,model = "cm-t35"; - - ti,mcbsp = <&mcbsp2>; - }; -}; - -&omap3_pmx_core { - - smsc1_pins: pinmux_smsc1_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20b8, PIN_OUTPUT | MUX_MODE0) /* gpmc_ncs5.gpmc_ncs5 */ - OMAP3_CORE1_IOPAD(0x219a, PIN_INPUT_PULLUP | MUX_MODE4) /* uart3_cts_rctx.gpio_163 */ - >; - }; - - hsusb0_pins: pinmux_hsusb0_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21a2, PIN_OUTPUT | MUX_MODE0) /* hsusb0_clk.hsusb0_clk */ - OMAP3_CORE1_IOPAD(0x21a4, PIN_OUTPUT | MUX_MODE0) /* hsusb0_stp.hsusb0_stp */ - OMAP3_CORE1_IOPAD(0x21a6, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_dir.hsusb0_dir */ - OMAP3_CORE1_IOPAD(0x21a8, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_nxt.hsusb0_nxt */ - OMAP3_CORE1_IOPAD(0x21aa, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data0.hsusb2_data0 */ - OMAP3_CORE1_IOPAD(0x21ac, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data1.hsusb0_data1 */ - OMAP3_CORE1_IOPAD(0x21ae, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data2.hsusb0_data2 */ - OMAP3_CORE1_IOPAD(0x21b0, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data7.hsusb0_data3 */ - OMAP3_CORE1_IOPAD(0x21b2, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data7.hsusb0_data4 */ - OMAP3_CORE1_IOPAD(0x21b4, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data7.hsusb0_data5 */ - OMAP3_CORE1_IOPAD(0x21b6, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data7.hsusb0_data6 */ - OMAP3_CORE1_IOPAD(0x21b8, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data7.hsusb0_data7 */ - >; - }; -}; - -#include "omap-gpmc-smsc911x.dtsi" - -&gpmc { - ranges = <5 0 0x2c000000 0x01000000>, /* CM-T3x30 SMSC9x Eth */ - <0 0 0x00000000 0x01000000>; /* CM-T3x NAND */ - - smsc1: ethernet@gpmc { - compatible = "smsc,lan9221", "smsc,lan9115"; - pinctrl-names = "default"; - pinctrl-0 = <&smsc1_pins>; - interrupt-parent = <&gpio6>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - reg = <5 0 0xff>; - }; -}; - -&i2c1 { - twl: twl@48 { - reg = <0x48>; - interrupts = <7>; /* SYS_NIRQ cascaded to intc */ - interrupt-parent = <&intc>; - - twl_audio: audio { - compatible = "ti,twl4030-audio"; - codec { - }; - }; - }; -}; - -#include "twl4030.dtsi" -#include "twl4030_omap3.dtsi" -#include - -&venc { - vdda-supply = <&vdac>; -}; - -&mmc1 { - vmmc-supply = <&vmmc1>; -}; - -&twl_gpio { - ti,use-leds; - /* pullups: BIT(0) */ - ti,pullups = <0x000001>; -}; - -&twl_keypad { - linux,keymap = < - MATRIX_KEY(0x00, 0x01, KEY_A) - MATRIX_KEY(0x00, 0x02, KEY_B) - MATRIX_KEY(0x00, 0x03, KEY_LEFT) - - MATRIX_KEY(0x01, 0x01, KEY_UP) - MATRIX_KEY(0x01, 0x02, KEY_ENTER) - MATRIX_KEY(0x01, 0x03, KEY_DOWN) - - MATRIX_KEY(0x02, 0x01, KEY_RIGHT) - MATRIX_KEY(0x02, 0x02, KEY_C) - MATRIX_KEY(0x02, 0x03, KEY_D) - >; -}; - -&hsusb1_phy { - reset-gpios = <&twl_gpio 6 GPIO_ACTIVE_LOW>; -}; - -&hsusb2_phy { - reset-gpios = <&twl_gpio 7 GPIO_ACTIVE_LOW>; -}; - -&usb_otg_hs { - pinctrl-names = "default"; - pinctrl-0 = <&hsusb0_pins>; - interface-type = <0>; - usb-phy = <&usb2_phy>; - phys = <&usb2_phy>; - phy-names = "usb2-phy"; - mode = <3>; - power = <50>; -}; diff --git a/sys/gnu/dts/arm/omap3-cpu-thermal.dtsi b/sys/gnu/dts/arm/omap3-cpu-thermal.dtsi deleted file mode 100644 index 235ecfd61e2..00000000000 --- a/sys/gnu/dts/arm/omap3-cpu-thermal.dtsi +++ /dev/null @@ -1,20 +0,0 @@ -/* - * Device Tree Source for OMAP3 SoC CPU thermal - * - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -#include - -cpu_thermal: cpu_thermal { - polling-delay-passive = <250>; /* milliseconds */ - polling-delay = <1000>; /* milliseconds */ - coefficients = <0 20000>; - - /* sensor ID */ - thermal-sensors = <&bandgap 0>; -}; diff --git a/sys/gnu/dts/arm/omap3-devkit8000-common.dtsi b/sys/gnu/dts/arm/omap3-devkit8000-common.dtsi deleted file mode 100644 index ac3d996cec5..00000000000 --- a/sys/gnu/dts/arm/omap3-devkit8000-common.dtsi +++ /dev/null @@ -1,374 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Author: Anil Kumar - */ - -#include - -#include "omap34xx.dtsi" -/ { - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x10000000>; /* 256 MB */ - }; - - leds { - compatible = "gpio-leds"; - - heartbeat { - label = "devkit8000::led1"; - gpios = <&gpio6 26 GPIO_ACTIVE_HIGH>; /* 186 -> LED1 */ - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - - mmc { - label = "devkit8000::led2"; - gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>; /* 163 -> LED2 */ - default-state = "on"; - linux,default-trigger = "none"; - }; - - usr { - label = "devkit8000::led3"; - gpios = <&gpio6 4 GPIO_ACTIVE_HIGH>; /* 164 -> LED3 */ - default-state = "on"; - linux,default-trigger = "usr"; - }; - - pmu_stat { - label = "devkit8000::pmu_stat"; - gpios = <&twl_gpio 19 GPIO_ACTIVE_HIGH>; /* LEDB */ - }; - }; - - sound { - compatible = "ti,omap-twl4030"; - ti,model = "devkit8000"; - - ti,mcbsp = <&mcbsp2>; - ti,audio-routing = - "Ext Spk", "PREDRIVEL", - "Ext Spk", "PREDRIVER", - "MAINMIC", "Main Mic", - "Main Mic", "Mic Bias 1"; - }; - - gpio_keys { - compatible = "gpio-keys"; - - user { - label = "user"; - gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; - linux,code = ; - wakeup-source; - }; - }; - - tfp410: encoder0 { - compatible = "ti,tfp410"; - powerdown-gpios = <&twl_gpio 7 GPIO_ACTIVE_LOW>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - tfp410_in: endpoint { - remote-endpoint = <&dpi_dvi_out>; - }; - }; - - port@1 { - reg = <1>; - - tfp410_out: endpoint { - remote-endpoint = <&dvi_connector_in>; - }; - }; - }; - }; - - dvi0: connector0 { - compatible = "dvi-connector"; - label = "dvi"; - - digital; - - ddc-i2c-bus = <&i2c2>; - - port { - dvi_connector_in: endpoint { - remote-endpoint = <&tfp410_out>; - }; - }; - }; - - tv0: connector1 { - compatible = "svideo-connector"; - label = "tv"; - - port { - tv_connector_in: endpoint { - remote-endpoint = <&venc_out>; - }; - }; - }; -}; - -&i2c1 { - clock-frequency = <2600000>; - - twl: twl@48 { - reg = <0x48>; - interrupts = <7>; /* SYS_NIRQ cascaded to intc */ - - twl_audio: audio { - compatible = "ti,twl4030-audio"; - codec { - }; - }; - }; -}; - -&i2c2 { - clock-frequency = <400000>; -}; - -&i2c3 { - status = "disabled"; -}; - -#include "twl4030.dtsi" -#include "twl4030_omap3.dtsi" - -&mmc1 { - vmmc-supply = <&vmmc1>; - vqmmc-supply = <&vsim>; - bus-width = <8>; -}; - -&mmc2 { - status = "disabled"; -}; - -&mmc3 { - status = "disabled"; -}; - -&twl_gpio { - ti,use-leds; - /* - * pulldowns: - * BIT(1), BIT(2), BIT(6), BIT(7), BIT(8), BIT(13) - * BIT(15), BIT(16), BIT(17) - */ - ti,pulldowns = <0x03a1c6>; -}; - -&twl_keypad { - linux,keymap = ; -}; - -&wdt2 { - status = "disabled"; -}; - -&mcbsp2 { - status = "okay"; -}; - -&gpmc { - ranges = <0 0 0x30000000 0x1000000 /* CS0: 16MB for NAND */ - 6 0 0x2c000000 0x1000000>; /* CS6: 16MB for DM9000 */ - - nand@0,0 { - compatible = "ti,omap2-nand"; - reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ - <1 IRQ_TYPE_NONE>; /* termcount */ - nand-bus-width = <16>; - gpmc,device-width = <2>; - ti,nand-ecc-opt = "sw"; - - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <44>; - gpmc,cs-wr-off-ns = <44>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <34>; - gpmc,adv-wr-off-ns = <44>; - gpmc,we-off-ns = <40>; - gpmc,oe-off-ns = <54>; - gpmc,access-ns = <64>; - gpmc,rd-cycle-ns = <82>; - gpmc,wr-cycle-ns = <82>; - gpmc,wr-access-ns = <40>; - gpmc,wr-data-mux-bus-ns = <0>; - - #address-cells = <1>; - #size-cells = <1>; - - x-loader@0 { - label = "X-Loader"; - reg = <0 0x80000>; - }; - - bootloaders@80000 { - label = "U-Boot"; - reg = <0x80000 0x1e0000>; - }; - - bootloaders_env@260000 { - label = "U-Boot Env"; - reg = <0x260000 0x20000>; - }; - - kernel@280000 { - label = "Kernel"; - reg = <0x280000 0x400000>; - }; - - filesystem@680000 { - label = "File System"; - reg = <0x680000 0xf980000>; - }; - }; - - ethernet@6,0 { - compatible = "davicom,dm9000"; - reg = <6 0x000 2 - 6 0x400 2>; /* CS6, offset 0 and 0x400, IO size 2 */ - bank-width = <2>; - interrupt-parent = <&gpio1>; - interrupts = <25 IRQ_TYPE_LEVEL_LOW>; - davicom,no-eeprom; - - gpmc,mux-add-data = <0>; - gpmc,device-width = <1>; - gpmc,wait-pin = <0>; - gpmc,cycle2cycle-samecsen = <1>; - gpmc,cycle2cycle-diffcsen = <1>; - - gpmc,cs-on-ns = <6>; - gpmc,cs-rd-off-ns = <180>; - gpmc,cs-wr-off-ns = <180>; - gpmc,adv-on-ns = <0>; - gpmc,adv-rd-off-ns = <18>; - gpmc,adv-wr-off-ns = <48>; - gpmc,oe-on-ns = <54>; - gpmc,oe-off-ns = <168>; - gpmc,we-on-ns = <54>; - gpmc,we-off-ns = <168>; - gpmc,rd-cycle-ns = <186>; - gpmc,wr-cycle-ns = <186>; - gpmc,access-ns = <144>; - gpmc,page-burst-access-ns = <24>; - gpmc,bus-turnaround-ns = <90>; - gpmc,cycle2cycle-delay-ns = <90>; - gpmc,wait-monitoring-ns = <0>; - gpmc,clk-activation-ns = <0>; - gpmc,wr-data-mux-bus-ns = <0>; - gpmc,wr-access-ns = <0>; - }; -}; - -&omap3_pmx_core { - dss_dpi_pins: pinmux_dss_dpi_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ - OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ - OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ - OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ - OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ - OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ - OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ - OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ - OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ - OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ - OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ - OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ - OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ - OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ - OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ - OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ - OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ - OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ - OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ - OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ - OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ - OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ - OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */ - OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */ - OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */ - OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */ - OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ - OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ - >; - }; -}; - -&vpll1 { - /* Needed for DSS */ - regulator-name = "vdds_dsi"; - - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; -}; - -&dss { - status = "ok"; - - pinctrl-names = "default"; - pinctrl-0 = <&dss_dpi_pins>; - - vdds_dsi-supply = <&vpll1>; - vdda_dac-supply = <&vdac>; - - port { - #address-cells = <1>; - #size-cells = <0>; - dpi_dvi_out: endpoint@0 { - reg = <0>; - remote-endpoint = <&tfp410_in>; - data-lines = <24>; - }; - - endpoint@1 { - reg = <1>; - }; - }; -}; - -&venc { - status = "ok"; - - vdda-supply = <&vdac>; - - port { - venc_out: endpoint { - remote-endpoint = <&tv_connector_in>; - ti,channels = <2>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/omap3-devkit8000-lcd-common.dtsi b/sys/gnu/dts/arm/omap3-devkit8000-lcd-common.dtsi deleted file mode 100644 index 3decc2d78a6..00000000000 --- a/sys/gnu/dts/arm/omap3-devkit8000-lcd-common.dtsi +++ /dev/null @@ -1,73 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Author: Anthoine Bourgeois - */ - -#include "omap3-devkit8000-common.dtsi" -/ { - aliases { - display0 = &lcd0; - display1 = &dvi0; - display2 = &tv0; - }; - - lcd0: display { - compatible = "panel-dpi"; - label = "lcd"; - - enable-gpios = <&twl_gpio 18 GPIO_ACTIVE_HIGH>; - - port { - lcd_in: endpoint { - remote-endpoint = <&dpi_lcd_out>; - }; - }; - }; -}; - -&dss { - port { - #address-cells = <1>; - #size-cells = <0>; - dpi_lcd_out: endpoint@1 { - reg = <1>; - remote-endpoint = <&lcd_in>; - data-lines = <24>; - }; - }; -}; - -&vio { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; -}; - -&mcspi2 { - - /* touch controller */ - ads7846@0 { - compatible = "ti,ads7846"; - vcc-supply = <&vio>; - - reg = <0>; /* CS0 */ - spi-max-frequency = <1500000>; - - interrupt-parent = <&gpio1>; - interrupts = <27 0>; /* gpio_27 */ - pendown-gpio = <&gpio1 27 GPIO_ACTIVE_HIGH>; - - ti,x-min = /bits/ 16 <0x0>; - ti,x-max = /bits/ 16 <0x0fff>; - ti,y-min = /bits/ 16 <0x0>; - ti,y-max = /bits/ 16 <0x0fff>; - ti,x-plate-ohms = /bits/ 16 <180>; - ti,pressure-max = /bits/ 16 <255>; - ti,debounce-max = /bits/ 16 <10>; - ti,debounce-tol = /bits/ 16 <5>; - ti,debounce-rep = /bits/ 16 <1>; - ti,keep-vref-on = <1>; - ti,settle-delay-usec = /bits/ 16 <150>; - - wakeup-source; - }; -}; diff --git a/sys/gnu/dts/arm/omap3-devkit8000-lcd43.dts b/sys/gnu/dts/arm/omap3-devkit8000-lcd43.dts deleted file mode 100644 index a80fc60bc77..00000000000 --- a/sys/gnu/dts/arm/omap3-devkit8000-lcd43.dts +++ /dev/null @@ -1,34 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Author: Anthoine Bourgeois - */ -/dts-v1/; - -/* - * 4.3'' LCD panel sold with devkit8000 board - */ - -#include "omap3-devkit8000-lcd-common.dtsi" -/ { - model = "TimLL OMAP3 Devkit8000 with 4.3'' LCD panel"; - compatible = "timll,omap3-devkit8000", "ti,omap3"; - - lcd0: display { - panel-timing { - clock-frequency = <10164705>; - hactive = <480>; - vactive = <272>; - hfront-porch = <2>; - hback-porch = <2>; - hsync-len = <41>; - vback-porch = <2>; - vfront-porch = <2>; - vsync-len = <10>; - - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/omap3-devkit8000-lcd70.dts b/sys/gnu/dts/arm/omap3-devkit8000-lcd70.dts deleted file mode 100644 index 0753776071f..00000000000 --- a/sys/gnu/dts/arm/omap3-devkit8000-lcd70.dts +++ /dev/null @@ -1,34 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Author: Anthoine Bourgeois - */ -/dts-v1/; - -/* - * 7.0'' LCD panel sold with some devkit8000 board - */ - -#include "omap3-devkit8000-lcd-common.dtsi" -/ { - model = "TimLL OMAP3 Devkit8000 with 7.0'' LCD panel"; - compatible = "timll,omap3-devkit8000", "ti,omap3"; - - lcd0: display { - panel-timing { - clock-frequency = <40000000>; - hactive = <800>; - vactive = <480>; - hfront-porch = <1>; - hback-porch = <1>; - hsync-len = <48>; - vback-porch = <25>; - vfront-porch = <12>; - vsync-len = <3>; - - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/omap3-devkit8000.dts b/sys/gnu/dts/arm/omap3-devkit8000.dts deleted file mode 100644 index faafc48d8f6..00000000000 --- a/sys/gnu/dts/arm/omap3-devkit8000.dts +++ /dev/null @@ -1,16 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Author: Anthoine Bourgeois - */ -/dts-v1/; - -#include "omap3-devkit8000-common.dtsi" -/ { - model = "TimLL OMAP3 Devkit8000"; - compatible = "timll,omap3-devkit8000", "ti,omap3"; - - aliases { - display1 = &dvi0; - display2 = &tv0; - }; -}; diff --git a/sys/gnu/dts/arm/omap3-echo.dts b/sys/gnu/dts/arm/omap3-echo.dts deleted file mode 100644 index e69de29bb2d..00000000000 diff --git a/sys/gnu/dts/arm/omap3-evm-37xx.dts b/sys/gnu/dts/arm/omap3-evm-37xx.dts deleted file mode 100644 index e0c0382388f..00000000000 --- a/sys/gnu/dts/arm/omap3-evm-37xx.dts +++ /dev/null @@ -1,107 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ - */ -/dts-v1/; - -#include "omap36xx.dtsi" -#include "omap3-evm-common.dtsi" -#include "omap3-evm-processor-common.dtsi" - -/ { - model = "TI OMAP37XX EVM (TMDSEVM3730)"; - compatible = "ti,omap3-evm-37xx", "ti,omap3630", "ti,omap3"; -}; - -&omap3_pmx_core2 { - pinctrl-names = "default"; - pinctrl-0 = <&hsusb2_2_pins>; - - ehci_phy_pins: pinmux_ehci_phy_pins { - pinctrl-single,pins = < - - /* EHCI PHY reset GPIO etk_d7.gpio_21 */ - OMAP3630_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) - - /* EHCI VBUS etk_d8.gpio_22 */ - OMAP3630_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) - >; - }; - - /* Used by OHCI and EHCI. OHCI won't work without external phy */ - hsusb2_2_pins: pinmux_hsusb2_2_pins { - pinctrl-single,pins = < - - /* etk_d10.hsusb2_clk */ - OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) - - /* etk_d11.hsusb2_stp */ - OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) - - /* etk_d12.hsusb2_dir */ - OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) - - /* etk_d13.hsusb2_nxt */ - OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) - - /* etk_d14.hsusb2_data0 */ - OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) - - /* etk_d15.hsusb2_data1 */ - OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) - >; - }; -}; - -&gpmc { - nand@0,0 { - compatible = "ti,omap2-nand"; - reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ - <1 IRQ_TYPE_NONE>; /* termcount */ - linux,mtd-name= "hynix,h8kds0un0mer-4em"; - nand-bus-width = <16>; - gpmc,device-width = <2>; - ti,nand-ecc-opt = "bch8"; - - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <44>; - gpmc,cs-wr-off-ns = <44>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <34>; - gpmc,adv-wr-off-ns = <44>; - gpmc,we-off-ns = <40>; - gpmc,oe-off-ns = <54>; - gpmc,access-ns = <64>; - gpmc,rd-cycle-ns = <82>; - gpmc,wr-cycle-ns = <82>; - gpmc,wr-access-ns = <40>; - gpmc,wr-data-mux-bus-ns = <0>; - - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "X-Loader"; - reg = <0 0x80000>; - }; - partition@80000 { - label = "U-Boot"; - reg = <0x80000 0x1c0000>; - }; - partition@1c0000 { - label = "Environment"; - reg = <0x240000 0x40000>; - }; - partition@280000 { - label = "Kernel"; - reg = <0x280000 0x500000>; - }; - partition@780000 { - label = "Filesystem"; - reg = <0x780000 0x1f880000>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/omap3-evm-common.dtsi b/sys/gnu/dts/arm/omap3-evm-common.dtsi deleted file mode 100644 index 17c89df6ce6..00000000000 --- a/sys/gnu/dts/arm/omap3-evm-common.dtsi +++ /dev/null @@ -1,198 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Common support for omap3 EVM boards - */ - -#include -#include "omap-gpmc-smsc911x.dtsi" - -/ { - cpus { - cpu@0 { - cpu0-supply = <&vcc>; - }; - }; - - /* HS USB Port 2 Power */ - hsusb2_power: hsusb2_power_reg { - compatible = "regulator-fixed"; - regulator-name = "hsusb2_vbus"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>; /* gpio_22 */ - startup-delay-us = <70000>; - enable-active-high; - }; - - /* HS USB Host PHY on PORT 2 */ - hsusb2_phy: hsusb2_phy { - compatible = "usb-nop-xceiv"; - reset-gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; /* gpio_21 */ - vcc-supply = <&hsusb2_power>; - #phy-cells = <0>; - }; - - leds { - compatible = "gpio-leds"; - ledb { - label = "omap3evm::ledb"; - gpios = <&twl_gpio 19 GPIO_ACTIVE_HIGH>; /* LEDB */ - linux,default-trigger = "default-on"; - }; - }; - - wl12xx_vmmc: wl12xx_vmmc { - compatible = "regulator-fixed"; - regulator-name = "vwl1271"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio5 22 GPIO_ACTIVE_HIGH>; /* gpio150 */ - startup-delay-us = <70000>; - enable-active-high; - vin-supply = <&vmmc2>; - }; -}; - -&i2c1 { - clock-frequency = <2600000>; - - twl: twl@48 { - reg = <0x48>; - interrupts = <7>; /* SYS_NIRQ cascaded to intc */ - interrupt-parent = <&intc>; - }; -}; - -#include "twl4030.dtsi" -#include "twl4030_omap3.dtsi" -#include "omap3-panel-sharp-ls037v7dw01.dtsi" - -&backlight0 { - gpios = <&twl_gpio 18 GPIO_ACTIVE_LOW>; -}; - -&twl { - twl_power: power { - compatible = "ti,twl4030-power-omap3-evm", "ti,twl4030-power-idle"; - ti,use_poweroff; - }; -}; - -&i2c2 { - clock-frequency = <400000>; -}; - -&i2c3 { - clock-frequency = <400000>; - - /* - * TVP5146 Video decoder-in for analog input support. - */ - tvp5146@5c { - compatible = "ti,tvp5146m2"; - reg = <0x5c>; - }; -}; - -&lcd_3v3 { - gpio = <&gpio5 25 GPIO_ACTIVE_LOW>; /* gpio153 */ -}; - -&lcd0 { - enable-gpios = <&gpio5 24 GPIO_ACTIVE_HIGH>; /* gpio152, lcd INI */ - reset-gpios = <&gpio5 27 GPIO_ACTIVE_HIGH>; /* gpio155, lcd RESB */ - mode-gpios = <&gpio5 26 GPIO_ACTIVE_HIGH /* gpio154, lcd MO */ - &gpio1 2 GPIO_ACTIVE_HIGH /* gpio2, lcd LR */ - &gpio1 3 GPIO_ACTIVE_HIGH>; /* gpio3, lcd UD */ -}; - -&mcspi1 { - tsc2046@0 { - interrupt-parent = <&gpio6>; - interrupts = <15 0>; /* gpio175 */ - pendown-gpio = <&gpio6 15 GPIO_ACTIVE_HIGH>; - }; -}; - -&mmc1 { - interrupts-extended = <&intc 83 &omap3_pmx_core 0x11a>; - vmmc-supply = <&vmmc1>; - vqmmc-supply = <&vsim>; - bus-width = <8>; -}; - -&mmc2 { - interrupts-extended = <&intc 86 &omap3_pmx_core 0x12e>; - vmmc-supply = <&wl12xx_vmmc>; - non-removable; - bus-width = <4>; - cap-power-off-card; - - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@2 { - compatible = "ti,wl1271"; - reg = <2>; - /* gpio_149 with uart1_rts pad as wakeirq */ - interrupts-extended = <&gpio5 21 IRQ_TYPE_EDGE_RISING>, - <&omap3_pmx_core 0x14e>; - interrupt-names = "irq", "wakeup"; - ref-clock-frequency = <38400000>; - }; -}; - -&twl_gpio { - ti,use-leds; -}; - -&twl_keypad { - linux,keymap = < - MATRIX_KEY(2, 2, KEY_1) - MATRIX_KEY(1, 1, KEY_2) - MATRIX_KEY(0, 0, KEY_3) - MATRIX_KEY(3, 2, KEY_4) - MATRIX_KEY(2, 1, KEY_5) - MATRIX_KEY(1, 0, KEY_6) - MATRIX_KEY(1, 3, KEY_7) - MATRIX_KEY(3, 1, KEY_8) - MATRIX_KEY(2, 0, KEY_9) - MATRIX_KEY(2, 3, KEY_KPASTERISK) - MATRIX_KEY(0, 2, KEY_0) - MATRIX_KEY(3, 0, KEY_KPDOT) - /* s4 not wired */ - MATRIX_KEY(1, 2, KEY_BACKSPACE) - MATRIX_KEY(0, 1, KEY_ENTER) - >; -}; - -&usbhshost { - port2-mode = "ehci-phy"; -}; - -&usbhsehci { - phys = <0 &hsusb2_phy>; -}; - -&usb_otg_hs { - interface-type = <0>; - usb-phy = <&usb2_phy>; - phys = <&usb2_phy>; - phy-names = "usb2-phy"; - mode = <3>; - power = <50>; -}; - -&gpmc { - ethernet@gpmc { - interrupt-parent = <&gpio6>; - interrupts = <16 8>; - reg = <5 0 0xff>; - }; -}; - -&vaux2 { - regulator-name = "usb_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; -}; diff --git a/sys/gnu/dts/arm/omap3-evm-processor-common.dtsi b/sys/gnu/dts/arm/omap3-evm-processor-common.dtsi deleted file mode 100644 index b4109f48ec1..00000000000 --- a/sys/gnu/dts/arm/omap3-evm-processor-common.dtsi +++ /dev/null @@ -1,224 +0,0 @@ -/* - * Common support for omap3 EVM 35xx/37xx processor modules - */ - -/ { - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x10000000>; /* 256 MB */ - }; - - wl12xx_vmmc: wl12xx_vmmc { - pinctrl-names = "default"; - pinctrl-0 = <&wl12xx_gpio>; - }; -}; - -&dss { - vdds_dsi-supply = <&vpll2>; - vdda_video-supply = <&lcd_3v3>; - pinctrl-names = "default"; - pinctrl-0 = < - &dss_dpi_pins1 - &dss_dpi_pins2 - >; -}; - -&hsusb2_phy { - pinctrl-names = "default"; - pinctrl-0 = <&ehci_phy_pins>; -}; - -&omap3_pmx_core { - pinctrl-names = "default"; - pinctrl-0 = <&on_board_gpio_61 &hsusb2_pins>; - - dss_dpi_pins1: pinmux_dss_dpi_pins2 { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ - OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ - OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ - OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ - - OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ - OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ - OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ - OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ - OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ - OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ - OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ - OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ - OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ - OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ - OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ - OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ - - OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE3) /* dss_data18.dss_data0 */ - OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE3) /* dss_data19.dss_data1 */ - OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE3) /* dss_data20.dss_data2 */ - OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE3) /* dss_data21.dss_data3 */ - OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE3) /* dss_data22.dss_data4 */ - OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE3) /* dss_data23.dss_data5 */ - >; - }; - - mmc1_pins: pinmux_mmc1_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2144, PIN_OUTPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ - OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ - OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ - OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ - OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ - OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ - OMAP3_CORE1_IOPAD(0x2150, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat4.sdmmc1_dat4 */ - OMAP3_CORE1_IOPAD(0x2152, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat5.sdmmc1_dat5 */ - OMAP3_CORE1_IOPAD(0x2154, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat6.sdmmc1_dat6 */ - OMAP3_CORE1_IOPAD(0x2156, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat7.sdmmc1_dat7 */ - >; - }; - - /* NOTE: Clocked externally, needs INPUT also for sdmmc2_clk.sdmmc2_clk */ - mmc2_pins: pinmux_mmc2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ - OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ - OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ - OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ - OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ - OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ - OMAP3_CORE1_IOPAD(0x2164, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat4.sdmmc2_dir_dat0 */ - OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat5.sdmmc2_dir_dat1 */ - OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat6.sdmmc2_dir_cmd */ - OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT | MUX_MODE1) /* sdmmc2_dat7.sdmmc2_clkin */ - >; - }; - - uart3_pins: pinmux_uart3_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x219e, WAKEUP_EN | PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ - OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ - >; - }; - - /* Devices are routed with gpmc_nbe1.gpio_61 to on-board devices */ - on_board_gpio_61: pinmux_ehci_port_select_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20c8, PIN_OUTPUT | MUX_MODE4) - >; - }; - - /* Used by OHCI and EHCI. OHCI won't work without external phy */ - hsusb2_pins: pinmux_hsusb2_pins { - pinctrl-single,pins = < - - /* mcspi1_cs3.hsusb2_data2 */ - OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) - - /* mcspi2_clk.hsusb2_data7 */ - OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) - - /* mcspi2_simo.hsusb2_data4 */ - OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) - - /* mcspi2_somi.hsusb2_data5 */ - OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) - - /* mcspi2_cs0.hsusb2_data6 */ - OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) - - /* mcspi2_cs1.hsusb2_data3 */ - OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) - >; - }; - - /* - * Note that gpio_150 pulled high with internal pull to prevent wlcore - * reset on return from off mode in idle. - */ - wl12xx_gpio: pinmux_wl12xx_gpio { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT_PULLUP | MUX_MODE7) /* uart1_cts.gpio_150 */ - OMAP3_CORE1_IOPAD(0x217e, PIN_INPUT | MUX_MODE4) /* uart1_rts.gpio_149 */ - >; - }; - - smsc911x_pins: pinmux_smsc911x_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21d2, PIN_INPUT | MUX_MODE4) /* mcspi1_cs2.gpio_176 */ - >; - }; -}; - -&omap3_pmx_wkup { - dss_dpi_pins2: pinmux_dss_dpi_pins1 { - pinctrl-single,pins = < - OMAP3_WKUP_IOPAD(0x2a0a, PIN_OUTPUT | MUX_MODE3) /* sys_boot0.dss_data18 */ - OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE3) /* sys_boot1.dss_data19 */ - OMAP3_WKUP_IOPAD(0x2a10, PIN_OUTPUT | MUX_MODE3) /* sys_boot3.dss_data20 */ - OMAP3_WKUP_IOPAD(0x2a12, PIN_OUTPUT | MUX_MODE3) /* sys_boot4.dss_data21 */ - OMAP3_WKUP_IOPAD(0x2a14, PIN_OUTPUT | MUX_MODE3) /* sys_boot5.dss_data22 */ - OMAP3_WKUP_IOPAD(0x2a16, PIN_OUTPUT | MUX_MODE3) /* sys_boot6.dss_data23 */ - >; - }; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; -}; - -&mmc3 { - status = "disabled"; -}; - -&uart1 { - interrupts-extended = <&intc 72 &omap3_pmx_core OMAP3_UART1_RX>; -}; - -&uart2 { - interrupts-extended = <&intc 73 &omap3_pmx_core OMAP3_UART2_RX>; -}; - -&uart3 { - interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>; - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; -}; - -/* - * GPIO_61 (nUSB2_EN_1V8) must be low to enable on-board EHCI USB2 interface - * for bus switch SN74CB3Q3384A, level-shifter SN74AVC16T245DGGR, and 1.8V. - */ -&gpio2 { - en_usb2_port { - gpio-hog; - gpios = <29 GPIO_ACTIVE_HIGH>; /* gpio_61 */ - output-low; - line-name = "enable usb2 port"; - }; -}; - -/* T2_GPIO_2 low to route GPIO_61 to on-board devices */ -&twl_gpio { - en_on_board_gpio_61 { - gpio-hog; - gpios = <2 GPIO_ACTIVE_HIGH>; - output-low; - line-name = "en_hsusb2_clk"; - }; -}; - -&gpmc { - ranges = <0 0 0x30000000 0x1000000>, /* CS0: 16MB for NAND */ - <5 0 0x2c000000 0x01000000>; /* CS5: 16MB for LAN9220 */ - - ethernet@gpmc { - pinctrl-names = "default"; - pinctrl-0 = <&smsc911x_pins>; - }; -}; diff --git a/sys/gnu/dts/arm/omap3-evm.dts b/sys/gnu/dts/arm/omap3-evm.dts deleted file mode 100644 index 6a94815feb7..00000000000 --- a/sys/gnu/dts/arm/omap3-evm.dts +++ /dev/null @@ -1,86 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ - */ -/dts-v1/; - -#include "omap34xx.dtsi" -#include "omap3-evm-common.dtsi" -#include "omap3-evm-processor-common.dtsi" - -/ { - model = "TI OMAP35XX EVM (TMDSEVM3530)"; - compatible = "ti,omap3-evm", "ti,omap3430", "ti,omap3"; -}; - -&omap3_pmx_core2 { - pinctrl-names = "default"; - pinctrl-0 = <&hsusb2_2_pins>; - - ehci_phy_pins: pinmux_ehci_phy_pins { - pinctrl-single,pins = < - - /* EHCI PHY reset GPIO etk_d7.gpio_21 */ - OMAP3430_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) - - /* EHCI VBUS etk_d8.gpio_22 */ - OMAP3430_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) - >; - }; - - /* Used by OHCI and EHCI. OHCI won't work without external phy */ - hsusb2_2_pins: pinmux_hsusb2_2_pins { - pinctrl-single,pins = < - - /* etk_d10.hsusb2_clk */ - OMAP3430_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) - - /* etk_d11.hsusb2_stp */ - OMAP3430_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) - - /* etk_d12.hsusb2_dir */ - OMAP3430_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) - - /* etk_d13.hsusb2_nxt */ - OMAP3430_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) - - /* etk_d14.hsusb2_data0 */ - OMAP3430_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) - - /* etk_d15.hsusb2_data1 */ - OMAP3430_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) - >; - }; -}; - -&gpmc { - nand@0,0 { - compatible = "ti,omap2-nand"; - reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ - <1 IRQ_TYPE_NONE>; /* termcount */ - linux,mtd-name= "micron,mt29f2g16abdhc"; - nand-bus-width = <16>; - gpmc,device-width = <2>; - ti,nand-ecc-opt = "bch8"; - - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <44>; - gpmc,cs-wr-off-ns = <44>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <34>; - gpmc,adv-wr-off-ns = <44>; - gpmc,we-off-ns = <40>; - gpmc,oe-off-ns = <54>; - gpmc,access-ns = <64>; - gpmc,rd-cycle-ns = <82>; - gpmc,wr-cycle-ns = <82>; - gpmc,wr-access-ns = <40>; - gpmc,wr-data-mux-bus-ns = <0>; - - #address-cells = <1>; - #size-cells = <1>; - }; -}; diff --git a/sys/gnu/dts/arm/omap3-gta04.dtsi b/sys/gnu/dts/arm/omap3-gta04.dtsi deleted file mode 100644 index b6ef1a7ac8a..00000000000 --- a/sys/gnu/dts/arm/omap3-gta04.dtsi +++ /dev/null @@ -1,873 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2013 Marek Belisko - * - * Based on omap3-beagle-xm.dts - */ -/dts-v1/; - -#include "omap36xx.dtsi" -#include - -/ { - model = "OMAP3 GTA04"; - compatible = "ti,omap3-gta04", "ti,omap36xx", "ti,omap3"; - - cpus { - cpu@0 { - cpu0-supply = <&vcc>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000>; /* 512 MB */ - }; - - chosen { - stdout-path = &uart3; - }; - - aliases { - display0 = &lcd; - display1 = &tv0; - }; - - ldo_3v3: fixedregulator { - compatible = "regulator-fixed"; - regulator-name = "ldo_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - /* fixed 26MHz oscillator */ - hfclk_26m: oscillator { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <26000000>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - aux-button { - label = "aux"; - linux,code = ; - gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; - wakeup-source; - }; - }; - - antenna-detect { - compatible = "gpio-keys"; - - gps_antenna_button: gps-antenna-button { - label = "GPS_EXT_ANT"; - linux,input-type = ; - linux,code = ; - gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>; /* GPIO144 */ - interrupt-parent = <&gpio5>; - interrupts = <16 IRQ_TYPE_EDGE_BOTH>; - debounce-interval = <10>; - wakeup-source; - }; - }; - - sound { - compatible = "ti,omap-twl4030"; - ti,model = "gta04"; - - ti,mcbsp = <&mcbsp2>; - }; - - /* GSM audio */ - sound_telephony { - compatible = "simple-audio-card"; - simple-audio-card,name = "GTA04 voice"; - simple-audio-card,bitclock-master = <&telephony_link_master>; - simple-audio-card,frame-master = <&telephony_link_master>; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-inversion; - simple-audio-card,frame-inversion; - simple-audio-card,cpu { - sound-dai = <&mcbsp4>; - }; - - telephony_link_master: simple-audio-card,codec { - sound-dai = <>m601_codec>; - }; - }; - - gtm601_codec: gsm_codec { - compatible = "option,gtm601"; - #sound-dai-cells = <0>; - }; - - spi_lcd: spi_lcd { - compatible = "spi-gpio"; - #address-cells = <0x1>; - #size-cells = <0x0>; - pinctrl-names = "default"; - pinctrl-0 = <&spi_gpio_pins>; - - gpio-sck = <&gpio1 12 GPIO_ACTIVE_HIGH>; - gpio-miso = <&gpio1 18 GPIO_ACTIVE_HIGH>; - gpio-mosi = <&gpio1 20 GPIO_ACTIVE_HIGH>; - cs-gpios = <&gpio1 19 GPIO_ACTIVE_HIGH>; - num-chipselects = <1>; - - /* lcd panel */ - lcd: td028ttec1@0 { - compatible = "tpo,td028ttec1"; - reg = <0>; - spi-max-frequency = <100000>; - spi-cpol; - spi-cpha; - spi-cs-high; - - backlight= <&backlight>; - label = "lcd"; - port { - lcd_in: endpoint { - remote-endpoint = <&dpi_out>; - }; - }; - }; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm11 0 12000000 0>; - pwm-names = "backlight"; - brightness-levels = <0 11 20 30 40 50 60 70 80 90 100>; - default-brightness-level = <9>; /* => 90 */ - pinctrl-names = "default"; - pinctrl-0 = <&backlight_pins>; - }; - - pwm11: dmtimer-pwm { - compatible = "ti,omap-dmtimer-pwm"; - ti,timers = <&timer11>; - #pwm-cells = <3>; - }; - - hsusb2_phy: hsusb2_phy { - compatible = "usb-nop-xceiv"; - reset-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; - #phy-cells = <0>; - }; - - tv0: connector { - compatible = "composite-video-connector"; - label = "tv"; - - port { - tv_connector_in: endpoint { - remote-endpoint = <&opa_out>; - }; - }; - }; - - tv_amp: opa362 { - compatible = "ti,opa362"; - enable-gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>; /* GPIO_23 to enable video out amplifier */ - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - opa_in: endpoint { - remote-endpoint = <&venc_out>; - }; - }; - - port@1 { - reg = <1>; - opa_out: endpoint { - remote-endpoint = <&tv_connector_in>; - }; - }; - }; - }; - - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&tca6507 0 GPIO_ACTIVE_LOW>; /* W2CBW003 reset through tca6507 */ - }; - - /* devconf0 setup for mcbsp1 clock pins */ - pinmux_mcbsp1@48002274 { - compatible = "pinctrl-single"; - reg = <0x48002274 4>; /* CONTROL_DEVCONF0 */ - #address-cells = <1>; - #size-cells = <0>; - pinctrl-single,bit-per-mux; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0x7>; /* MCBSP1 CLK pinmux */ - #pinctrl-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&mcbsp1_devconf0_pins>; - mcbsp1_devconf0_pins: pinmux_mcbsp1_devconf0_pins { - /* offset bits mask */ - pinctrl-single,bits = <0x00 0x08 0x1c>; /* set MCBSP1_CLKR */ - }; - }; - - /* devconf1 setup for tvout pins */ - pinmux_tv_out@480022d8 { - compatible = "pinctrl-single"; - reg = <0x480022d8 4>; /* CONTROL_DEVCONF1 */ - #address-cells = <1>; - #size-cells = <0>; - pinctrl-single,bit-per-mux; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0x81>; /* TV out pin control */ - #pinctrl-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&tv_acbias_devconf1_pins>; - tv_acbias_devconf1_pins: pinmux_tv_acbias_devconf1_pins { - /* offset bits mask */ - pinctrl-single,bits = <0x00 0x40800 0x40800>; /* set TVOUTBYPASS and TVOUTACEN */ - }; - }; -}; - -&omap3_pmx_wkup { - gpio1_pins: pinmux_gpio1_pins { - pinctrl-single,pins = < - OMAP3_WKUP_IOPAD(0x2a14, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE4) /* sys_boot5.gpio_7 */ - OMAP3_WKUP_IOPAD(0x2a1a, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE4) /* sys_clkout.gpio_10 */ - >; - }; -}; - -&omap3_pmx_core { - pinctrl-names = "default"; - pinctrl-0 = < - &hsusb2_pins - >; - - hsusb2_pins: pinmux_hsusb2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */ - OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */ - OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */ - OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */ - OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */ - OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */ - >; - }; - - uart1_pins: pinmux_uart1_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE0) /* uart1_rx.uart1_rx */ - OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE0) /* uart1_tx.uart1_tx */ - >; - }; - - uart2_pins: pinmux_uart2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */ - OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ - >; - }; - - uart3_pins: pinmux_uart3_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx.uart3_rx */ - OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx.uart3_tx */ - >; - }; - - mmc1_pins: pinmux_mmc1_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ - OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ - OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ - OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ - OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ - OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ - >; - }; - - backlight_pins: backlight_pins_pinmux { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20ba, MUX_MODE3) /* gpt11/gpio57 */ - >; - }; - - dss_dpi_pins: pinmux_dss_dpi_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ - OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ - OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ - OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ - OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ - OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ - OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ - OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ - OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ - OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ - OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ - OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ - OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ - OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ - OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ - OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ - OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ - OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ - OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ - OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ - OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ - OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ - OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */ - OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */ - OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */ - OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */ - OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ - OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ - >; - }; - - gps_pins: pinmux_gps_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* gpio145 */ - >; - }; - - hdq_pins: hdq_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21c6, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda.hdq */ - >; - }; - - bmp085_pins: pinmux_bmp085_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2136, PIN_INPUT_PULLUP | MUX_MODE4) /* gpio113 */ - >; - }; - - bma180_pins: pinmux_bma180_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x213a, PIN_INPUT_PULLUP | MUX_MODE4) /* gpio115 */ - >; - }; - - itg3200_pins: pinmux_itg3200_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20b8, PIN_INPUT_PULLUP | MUX_MODE4) /* gpio56 */ - >; - }; - - hmc5843_pins: pinmux_hmc5843_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2134, PIN_INPUT_PULLUP | MUX_MODE4) /* gpio112 */ - >; - }; - - penirq_pins: pinmux_penirq_pins { - pinctrl-single,pins = < - /* here we could enable to wakeup the cpu from suspend by a pen touch */ - OMAP3_CORE1_IOPAD(0x2194, PIN_INPUT_PULLUP | MUX_MODE4) /* gpio160 */ - >; - }; - - camera_pins: pinmux_camera_pins { - pinctrl-single,pins = < - /* set up parallel camera interface */ - OMAP3_CORE1_IOPAD(0x210c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* cam_hs */ - OMAP3_CORE1_IOPAD(0x210e, PIN_INPUT_PULLDOWN | MUX_MODE0) /* cam_vs */ - OMAP3_CORE1_IOPAD(0x2110, PIN_OUTPUT | MUX_MODE0) /* cam_xclka */ - OMAP3_CORE1_IOPAD(0x2112, PIN_INPUT_PULLDOWN | MUX_MODE0) /* cam_pclk */ - OMAP3_CORE1_IOPAD(0x2114, PIN_OUTPUT | MUX_MODE4) /* cam_fld = gpio_98 */ - OMAP3_CORE1_IOPAD(0x2116, PIN_INPUT_PULLDOWN | MUX_MODE0) /* cam_d0 */ - OMAP3_CORE1_IOPAD(0x2118, PIN_INPUT_PULLDOWN | MUX_MODE0) /* cam_d1 */ - OMAP3_CORE1_IOPAD(0x211a, PIN_INPUT_PULLDOWN | MUX_MODE0) /* cam_d2 */ - OMAP3_CORE1_IOPAD(0x211c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* cam_d3 */ - OMAP3_CORE1_IOPAD(0x211e, PIN_INPUT_PULLDOWN | MUX_MODE0) /* cam_d4 */ - OMAP3_CORE1_IOPAD(0x2120, PIN_INPUT_PULLDOWN | MUX_MODE0) /* cam_d5 */ - OMAP3_CORE1_IOPAD(0x2122, PIN_INPUT_PULLDOWN | MUX_MODE0) /* cam_d6 */ - OMAP3_CORE1_IOPAD(0x2124, PIN_INPUT_PULLDOWN | MUX_MODE0) /* cam_d7 */ - OMAP3_CORE1_IOPAD(0x2126, PIN_INPUT_PULLDOWN | MUX_MODE0) /* cam_d8 */ - OMAP3_CORE1_IOPAD(0x2128, PIN_INPUT_PULLDOWN | MUX_MODE0) /* cam_d9 */ - OMAP3_CORE1_IOPAD(0x212a, PIN_INPUT_PULLDOWN | MUX_MODE0) /* cam_d10 */ - OMAP3_CORE1_IOPAD(0x212c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* cam_d10 */ - OMAP3_CORE1_IOPAD(0x212e, PIN_OUTPUT | MUX_MODE0) /* cam_xclkb */ - OMAP3_CORE1_IOPAD(0x2130, PIN_OUTPUT | MUX_MODE4) /* cam_wen = gpio_167 */ - OMAP3_CORE1_IOPAD(0x2132, PIN_INPUT_PULLDOWN | MUX_MODE4) /* cam_strobe */ - >; - }; - - mcbsp1_pins: pinmux_mcbsp1_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x218c, PIN_INPUT | MUX_MODE4) /* mcbsp1_clkr.mcbsp1_clkr - gpio_156 FM interrupt */ - OMAP3_CORE1_IOPAD(0x218e, PIN_OUTPUT | MUX_MODE0) /* mcbsp1_clkr.mcbsp1_fsr */ - OMAP3_CORE1_IOPAD(0x2190, PIN_OUTPUT | MUX_MODE0) /* mcbsp1_dx.mcbsp1_dx */ - OMAP3_CORE1_IOPAD(0x2192, PIN_INPUT | MUX_MODE0) /* mcbsp1_dx.mcbsp1_dr */ - /* mcbsp_clks is used as PENIRQ */ - /* OMAP3_CORE1_IOPAD(0x2194, PIN_INPUT | MUX_MODE0) mcbsp_clks.mcbsp_clks */ - OMAP3_CORE1_IOPAD(0x2196, PIN_INPUT | MUX_MODE0) /* mcbsp_clks.mcbsp1_fsx */ - OMAP3_CORE1_IOPAD(0x2198, PIN_INPUT | MUX_MODE0) /* mcbsp1_clkx.mcbsp1_clkx */ - >; - }; - - mcbsp2_pins: pinmux_mcbsp2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx.mcbsp2_fsx */ - OMAP3_CORE1_IOPAD(0x213e, PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx.mcbsp2_clkx */ - OMAP3_CORE1_IOPAD(0x2140, PIN_INPUT | MUX_MODE0) /* mcbsp2_dr.mcbsp2_dr */ - OMAP3_CORE1_IOPAD(0x2142, PIN_OUTPUT | MUX_MODE0) /* mcbsp2_dr.mcbsp2_dx */ - >; - }; - - mcbsp3_pins: pinmux_mcbsp3_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x216c, PIN_OUTPUT | MUX_MODE0) /* mcbsp3_dx.mcbsp3_dx */ - OMAP3_CORE1_IOPAD(0x216e, PIN_INPUT | MUX_MODE0) /* mcbsp3_dx.mcbsp3_dr */ - OMAP3_CORE1_IOPAD(0x2170, PIN_INPUT | MUX_MODE0) /* mcbsp3_clkx.mcbsp3_clkx */ - OMAP3_CORE1_IOPAD(0x2172, PIN_INPUT | MUX_MODE0) /* mcbsp3_clkx.mcbsp3_fsx */ - >; - }; - - mcbsp4_pins: pinmux_mcbsp4_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcbsp4_clkx.mcbsp4_clkx */ - OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcbsp4_clkx.mcbsp4_dr */ - OMAP3_CORE1_IOPAD(0x218a, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcbsp4_dx.mcbsp4_fsx */ - >; - }; -}; - -&omap3_pmx_core2 { - pinctrl-names = "default"; - pinctrl-0 = < - &hsusb2_2_pins - >; - - hsusb2_2_pins: pinmux_hsusb2_2_pins { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ - OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ - OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ - OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ - OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ - OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ - >; - }; - - spi_gpio_pins: spi_gpio_pinmux { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25d8, PIN_OUTPUT | MUX_MODE4) /* clk */ - OMAP3630_CORE2_IOPAD(0x25e6, PIN_OUTPUT | MUX_MODE4) /* cs */ - OMAP3630_CORE2_IOPAD(0x25e8, PIN_OUTPUT | MUX_MODE4) /* tx */ - OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT | MUX_MODE4) /* rx */ - >; - }; -}; - -&i2c1 { - clock-frequency = <2600000>; - - twl: twl@48 { - reg = <0x48>; - interrupts = <7>; /* SYS_NIRQ cascaded to intc */ - interrupt-parent = <&intc>; - - clocks = <&hfclk_26m>; - clock-names = "fck"; - - twl_audio: audio { - compatible = "ti,twl4030-audio"; - ti,enable-vibra = <1>; - codec { - ti,ramp_delay_value = <3>; - }; - }; - - twl_power: power { - compatible = "ti,twl4030-power"; - ti,use_poweroff; - }; - }; -}; - -#include "twl4030.dtsi" -#include "twl4030_omap3.dtsi" - -&i2c2 { - clock-frequency = <400000>; - - /* pressure sensor */ - bmp085@77 { - compatible = "bosch,bmp085"; - reg = <0x77>; - pinctrl-names = "default"; - pinctrl-0 = <&bmp085_pins>; - interrupt-parent = <&gpio4>; - interrupts = <17 IRQ_TYPE_EDGE_RISING>; /* GPIO_113 */ - }; - - /* accelerometer */ - bma180@41 { - compatible = "bosch,bma180"; - reg = <0x41>; - pinctrl-names = "default"; - pintcrl-0 = <&bma180_pins>; - interrupt-parent = <&gpio4>; - interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; /* GPIO_115 */ - }; - - /* gyroscope */ - itg3200@68 { - compatible = "invensense,itg3200"; - reg = <0x68>; - pinctrl-names = "default"; - pinctrl-0 = <&itg3200_pins>; - interrupt-parent = <&gpio2>; - interrupts = <24 IRQ_TYPE_EDGE_FALLING>; /* GPIO_56 */ - }; - - /* leds + gpios */ - tca6507: tca6507@45 { - compatible = "ti,tca6507"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x45>; - - gpio-controller; - #gpio-cells = <2>; - - gta04_led0: red_aux@0 { - label = "gta04:red:aux"; - reg = <0x0>; - }; - - gta04_led1: green_aux@1 { - label = "gta04:green:aux"; - reg = <0x1>; - }; - - gta04_led3: red_power@3 { - label = "gta04:red:power"; - reg = <0x3>; - linux,default-trigger = "default-on"; - }; - - gta04_led4: green_power@4 { - label = "gta04:green:power"; - reg = <0x4>; - }; - - wifi_reset: wifi_reset@6 { /* reference as <&tca_gpios 0 0> since it is currently the only GPIO */ - reg = <0x6>; - compatible = "gpio"; - }; - }; - - /* compass aka magnetometer */ - hmc5843@1e { - compatible = "honeywell,hmc5883l"; - reg = <0x1e>; - pinctrl-names = "default"; - pinctrl-0 = <&hmc5843_pins>; - interrupt-parent = <&gpio4>; - interrupts = <16 IRQ_TYPE_EDGE_FALLING>; /* gpio112 */ - }; - - /* touchscreen */ - tsc2007@48 { - compatible = "ti,tsc2007"; - reg = <0x48>; - pinctrl-names = "default"; - pinctrl-0 = <&penirq_pins>; - interrupt-parent = <&gpio6>; - interrupts = <0 IRQ_TYPE_EDGE_FALLING>; /* GPIO_160 */ - gpios = <&gpio6 0 GPIO_ACTIVE_LOW>; /* GPIO_160 */ - ti,x-plate-ohms = <600>; - touchscreen-size-x = <480>; - touchscreen-size-y = <640>; - touchscreen-max-pressure = <1000>; - touchscreen-fuzz-x = <3>; - touchscreen-fuzz-y = <8>; - touchscreen-fuzz-pressure = <10>; - touchscreen-inverted-y; - }; - - /* RFID EEPROM */ - m24lr64@50 { - compatible = "atmel,24c64"; - reg = <0x50>; - }; -}; - -&i2c3 { - clock-frequency = <100000>; -}; - -&usb_otg_hs { - interface-type = <0>; - usb-phy = <&usb2_phy>; - phys = <&usb2_phy>; - phy-names = "usb2-phy"; - mode = <3>; - power = <50>; -}; - -&usbhshost { - port2-mode = "ehci-phy"; -}; - -&usbhsehci { - phys = <0 &hsusb2_phy>; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - vmmc-supply = <&vmmc1>; - bus-width = <4>; - ti,non-removable; - broken-cd; /* hardware has no CD */ -}; - -&mmc2 { - vmmc-supply = <&vaux4>; - bus-width = <4>; - ti,non-removable; - cap-power-off-card; - mmc-pwrseq = <&wifi_pwrseq>; -}; - -&mmc3 { - status = "disabled"; -}; - -#define BIT(x) (1 << (x)) -&twl_gpio { - /* pullups: BIT(2) */ - ti,pullups = ; - /* - * pulldowns: - * BIT(0), BIT(1), BIT(6), BIT(7), BIT(8), BIT(13) - * BIT(15), BIT(16), BIT(17) - */ - ti,pulldowns = <(BIT(0) | BIT(1) | BIT(6) | BIT(7) | BIT(8) | - BIT(13) | BIT(15) | BIT(16) | BIT(17))>; -}; - -&twl_keypad { - status = "disabled"; -}; - -&gpio1 { - pinctrl-names = "default"; - pinctrl-0 = <&gpio1_pins>; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; - gnss: gnss { - compatible = "wi2wi,w2sg0004"; - pinctrl-names = "default"; - pinctrl-0 = <&gps_pins>; - sirf,onoff-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>; - lna-supply = <&vsim>; - vcc-supply = <&ldo_3v3>; - }; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; - interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>; -}; - -&charger { - ti,bb-uvolt = <3200000>; - ti,bb-uamp = <150>; -}; - -/* spare */ -&vaux1 { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <3000000>; -}; - -/* sensors */ -&vaux2 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; /* we should never switch off while vio is on! */ -}; - -/* camera */ -&vaux3 { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; -}; - -/* WLAN/BT */ -&vaux4 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <3150000>; -}; - -/* GPS LNA */ -&vsim { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <3150000>; -}; - -/* Needed to power the DPI pins */ - -&vpll2 { - regulator-always-on; -}; - -&dss { - pinctrl-names = "default"; - pinctrl-0 = < &dss_dpi_pins >; - - status = "okay"; - vdds_dsi-supply = <&vpll2>; - - port { - dpi_out: endpoint { - remote-endpoint = <&lcd_in>; - data-lines = <24>; - }; - }; -}; - -&venc { - status = "okay"; - - vdda-supply = <&vdac>; - - port { - venc_out: endpoint { - remote-endpoint = <&opa_in>; - ti,channels = <1>; - ti,invert-polarity; - }; - }; -}; - -&gpmc { - ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */ - - nand@0,0 { - compatible = "ti,omap2-nand"; - reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ - <1 IRQ_TYPE_NONE>; /* termcount */ - ti,nand-ecc-opt = "ham1"; - rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ - nand-bus-width = <16>; - #address-cells = <1>; - #size-cells = <1>; - - gpmc,device-width = <2>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <44>; - gpmc,cs-wr-off-ns = <44>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <34>; - gpmc,adv-wr-off-ns = <44>; - gpmc,oe-off-ns = <54>; - gpmc,we-off-ns = <40>; - gpmc,access-ns = <64>; - gpmc,rd-cycle-ns = <82>; - gpmc,wr-cycle-ns = <82>; - gpmc,wr-access-ns = <40>; - gpmc,wr-data-mux-bus-ns = <0>; - gpmc,sync-clk-ps = <0>; - - x-loader@0 { - label = "X-Loader"; - reg = <0 0x80000>; - }; - - bootloaders@80000 { - label = "U-Boot"; - reg = <0x80000 0x1c0000>; - }; - - bootloaders_env@240000 { - label = "U-Boot Env"; - reg = <0x240000 0x40000>; - }; - - kernel@280000 { - label = "Kernel"; - reg = <0x280000 0x600000>; - }; - - filesystem@880000 { - label = "File System"; - reg = <0x880000 0>; /* 0 = MTDPART_SIZ_FULL */ - }; - }; -}; - -&mcbsp1 { /* FM Transceiver PCM */ - status = "ok"; - #sound-dai-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&mcbsp1_pins>; -}; - -&mcbsp2 { /* TPS65950 I2S */ - status = "ok"; - pinctrl-names = "default"; - pinctrl-0 = <&mcbsp2_pins>; -}; - -&mcbsp3 { /* Bluetooth PCM */ - status = "ok"; - #sound-dai-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&mcbsp3_pins>; -}; - -&mcbsp4 { /* GSM voice PCM */ - status = "ok"; - #sound-dai-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&mcbsp4_pins>; -}; - -&hdqw1w { - pinctrl-names = "default"; - pinctrl-0 = <&hdq_pins>; -}; - -/* image signal processor within OMAP3 SoC */ -&isp { - ports { - port@0 { - reg = <0>; - parallel_ep: endpoint { - ti,isp-clock-divisor = <1>; - ti,strobe-mode; - bus-width = <8>;/* Used data lines */ - data-shift = <2>; /* Lines 9:2 are used */ - hsync-active = <0>; /* Active low */ - vsync-active = <1>; /* Active high */ - data-active = <1>;/* Active high */ - pclk-sample = <1>;/* Falling */ - }; - }; - /* port@1 and port@2 are not used by GTA04 */ - }; -}; diff --git a/sys/gnu/dts/arm/omap3-gta04a3.dts b/sys/gnu/dts/arm/omap3-gta04a3.dts deleted file mode 100644 index bfae1a9ceea..00000000000 --- a/sys/gnu/dts/arm/omap3-gta04a3.dts +++ /dev/null @@ -1,45 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 H. Nikolaus Schaller - */ - -#include "omap3-gta04.dtsi" - -/ { - model = "Goldelico GTA04A3/Letux 2804"; -}; - -&i2c2 { - - /* alternate accelerometer that might be installed on some GTA04A3 boards */ - lis302@1d { - compatible = "st,lis331dlh", "st,lis3lv02d"; - reg = <0x1d>; - interrupt-parent = <&gpio3>; - interrupts = <18 (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_EDGE_RISING)>; - Vdd-supply = <&vaux2>; - Vdd_IO-supply = <&vaux2>; - - st,click-single-x; - st,click-single-y; - st,click-single-z; - st,click-thresh-x = <8>; - st,click-thresh-y = <8>; - st,click-thresh-z = <10>; - st,click-click-time-limit = <9>; - st,click-latency = <50>; - st,irq1-click; - st,wakeup-x-lo; - st,wakeup-x-hi; - st,wakeup-y-lo; - st,wakeup-y-hi; - st,wakeup-z-lo; - st,wakeup-z-hi; - st,min-limit-x = <32>; - st,min-limit-y = <3>; - st,min-limit-z = <3>; - st,max-limit-x = <3>; - st,max-limit-y = <32>; - st,max-limit-z = <32>; - }; -}; diff --git a/sys/gnu/dts/arm/omap3-gta04a4.dts b/sys/gnu/dts/arm/omap3-gta04a4.dts deleted file mode 100644 index f1cf24d55e6..00000000000 --- a/sys/gnu/dts/arm/omap3-gta04a4.dts +++ /dev/null @@ -1,10 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 Marek Belisko - */ - -#include "omap3-gta04.dtsi" - -/ { - model = "Goldelico GTA04A4/Letux 2804"; -}; diff --git a/sys/gnu/dts/arm/omap3-gta04a5.dts b/sys/gnu/dts/arm/omap3-gta04a5.dts deleted file mode 100644 index fd84bbf3b9c..00000000000 --- a/sys/gnu/dts/arm/omap3-gta04a5.dts +++ /dev/null @@ -1,137 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014-18 H. Nikolaus Schaller - */ - -#include "omap3-gta04.dtsi" - -/ { - model = "Goldelico GTA04A5/Letux 2804"; - - sound { - ti,jack-det-gpio = <&twl_gpio 2 GPIO_ACTIVE_HIGH>; /* GTA04A5 only */ - }; - - wlan_en: wlan_en_regulator { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&wlan_pins>; - regulator-name = "wlan-en-regulator"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - gpio = <&gpio5 10 GPIO_ACTIVE_HIGH>; /* GPIO_138 */ - - startup-delay-us = <70000>; - enable-active-high; - }; - - pps { - compatible = "pps-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pps_pins>; - - gpios = <&gpio4 18 GPIO_ACTIVE_HIGH>; /* GPIN_114 */ - }; - -}; - -&gpio5 { - irda_en { - gpio-hog; - gpios = <(175-160) GPIO_ACTIVE_HIGH>; - output-high; /* activate gpio_175 to disable IrDA receiver */ - }; -}; - -&omap3_pmx_core { - bt_pins: pinmux_bt_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE4) /* mmc2_dat5 = mmc3_dat1 = gpio137 */ - >; - }; - - wlan_pins: pinmux_wlan_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE4) /* mmc2_dat6 = mmc3_dat2 = gpio138 */ - >; - }; - - wlan_irq_pin: pinmux_wlan_irq_pin { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT_PULLUP | MUX_MODE4) /* mmc2_dat7 = mmc3_dat3 = gpio139 */ - >; - }; - - irda_pins: pinmux_irda { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21d0, PIN_OUTPUT_PULLUP | MUX_MODE4) /* mcspi1_cs1 = gpio175 */ - >; - }; - - pps_pins: pinmux_pps_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2138, PIN_INPUT | MUX_MODE4) /* gpin114 */ - >; - }; - -}; - -/* - * for WL183x module see - * Documentation/devicetree/bindings/net/wireless/ti,wlcore.txt - */ - -&wifi_pwrseq { - /delete-property/ reset-gpios; -}; - -&mmc2 { - vmmc-supply = <&wlan_en>; - bus-width = <4>; - cap-power-off-card; - non-removable; - - pinctrl-names = "default"; - pinctrl-0 = <&wlan_irq_pin>; - - #address-cells = <1>; - #size-cells = <0>; - - /delete-property/ mmc-pwrseq; - - wlcore: wlcore@2 { - compatible = "ti,wl1837"; - reg = <2>; - interrupt-parent = <&gpio5>; - interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; /* GPIO_139 */ - ref-clock-frequency = <26000000>; - }; -}; - -&i2c2 { - /delete-node/ bmp085@77; - /delete-node/ bma180@41; - /delete-node/ itg3200@68; - /delete-node/ hmc5843@1e; - - bmg160@69 { - compatible = "bosch,bmg160"; - reg = <0x69>; - }; - - bmc150@10 { - compatible = "bosch,bmc150_accel"; - reg = <0x10>; - }; - - bmc150@12 { - compatible = "bosch,bmc150_magn"; - reg = <0x12>; - }; - - bme280@76 { - compatible = "bosch,bme280"; - reg = <0x76>; - }; -}; diff --git a/sys/gnu/dts/arm/omap3-gta04a5one.dts b/sys/gnu/dts/arm/omap3-gta04a5one.dts deleted file mode 100644 index 9db9fe67cd6..00000000000 --- a/sys/gnu/dts/arm/omap3-gta04a5one.dts +++ /dev/null @@ -1,111 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014-18 H. Nikolaus Schaller - */ - -#include "omap3-gta04a5.dts" - -&omap3_pmx_core { - model = "Goldelico GTA04A5/Letux 2804 with OneNAND"; - - gpmc_pins: pinmux_gpmc_pins { - pinctrl-single,pins = < - - /* address lines */ - OMAP3_CORE1_IOPAD(0x207a, PIN_OUTPUT | MUX_MODE0) /* gpmc_a1.gpmc_a1 */ - OMAP3_CORE1_IOPAD(0x207c, PIN_OUTPUT | MUX_MODE0) /* gpmc_a2.gpmc_a2 */ - OMAP3_CORE1_IOPAD(0x207e, PIN_OUTPUT | MUX_MODE0) /* gpmc_a3.gpmc_a3 */ - - /* data lines, gpmc_d0..d7 not muxable according to TRM */ - OMAP3_CORE1_IOPAD(0x209e, PIN_INPUT | MUX_MODE0) /* gpmc_d8.gpmc_d8 */ - OMAP3_CORE1_IOPAD(0x20a0, PIN_INPUT | MUX_MODE0) /* gpmc_d9.gpmc_d9 */ - OMAP3_CORE1_IOPAD(0x20a2, PIN_INPUT | MUX_MODE0) /* gpmc_d10.gpmc_d10 */ - OMAP3_CORE1_IOPAD(0x20a4, PIN_INPUT | MUX_MODE0) /* gpmc_d11.gpmc_d11 */ - OMAP3_CORE1_IOPAD(0x20a6, PIN_INPUT | MUX_MODE0) /* gpmc_d12.gpmc_d12 */ - OMAP3_CORE1_IOPAD(0x20a8, PIN_INPUT | MUX_MODE0) /* gpmc_d13.gpmc_d13 */ - OMAP3_CORE1_IOPAD(0x20aa, PIN_INPUT | MUX_MODE0) /* gpmc_d14.gpmc_d14 */ - OMAP3_CORE1_IOPAD(0x20ac, PIN_INPUT | MUX_MODE0) /* gpmc_d15.gpmc_d15 */ - - /* - * gpmc_ncs0, gpmc_nadv_ale, gpmc_noe, gpmc_nwe, gpmc_wait0 not muxable - * according to TRM. OneNAND seems to require PIN_INPUT on clock. - */ - OMAP3_CORE1_IOPAD(0x20b0, PIN_OUTPUT | MUX_MODE0) /* gpmc_ncs1.gpmc_ncs1 */ - OMAP3_CORE1_IOPAD(0x20be, PIN_INPUT | MUX_MODE0) /* gpmc_clk.gpmc_clk */ - >; - }; -}; - -&gpmc { - /* switch inherited setup to OneNAND */ - - ranges = <0 0 0x04000000 0x1000000>; /* CS0: 16MB for OneNAND */ - pinctrl-names = "default"; - pinctrl-0 = <&gpmc_pins>; - - /delete-node/ nand@0,0; - - onenand@0,0 { - - #address-cells = <1>; - #size-cells = <1>; - compatible = "ti,omap2-onenand"; - reg = <0 0 0x20000>; /* CS0, offset 0, IO size 128K */ - - gpmc,sync-read; - gpmc,sync-write; - gpmc,burst-length = <16>; - gpmc,burst-read; - gpmc,burst-wrap; - gpmc,burst-write; - gpmc,device-width = <2>; - gpmc,mux-add-data = <2>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <87>; - gpmc,cs-wr-off-ns = <87>; - gpmc,adv-on-ns = <0>; - gpmc,adv-rd-off-ns = <10>; - gpmc,adv-wr-off-ns = <10>; - gpmc,oe-on-ns = <15>; - gpmc,oe-off-ns = <87>; - gpmc,we-on-ns = <0>; - gpmc,we-off-ns = <87>; - gpmc,rd-cycle-ns = <112>; - gpmc,wr-cycle-ns = <112>; - gpmc,access-ns = <81>; - gpmc,page-burst-access-ns = <15>; - gpmc,bus-turnaround-ns = <0>; - gpmc,cycle2cycle-delay-ns = <0>; - gpmc,wait-monitoring-ns = <0>; - gpmc,clk-activation-ns = <5>; - gpmc,wr-data-mux-bus-ns = <30>; - gpmc,wr-access-ns = <81>; - gpmc,sync-clk-ps = <15000>; - - x-loader@0 { - label = "X-Loader"; - reg = <0 0x80000>; - }; - - bootloaders@80000 { - label = "U-Boot"; - reg = <0x80000 0x1c0000>; - }; - - bootloaders_env@240000 { - label = "U-Boot Env"; - reg = <0x240000 0x40000>; - }; - - kernel@280000 { - label = "Kernel"; - reg = <0x280000 0x600000>; - }; - - filesystem@880000 { - label = "File System"; - reg = <0x880000 0>; /* 0 = MTDPART_SIZ_FULL */ - }; - - }; -}; diff --git a/sys/gnu/dts/arm/omap3-ha-common.dtsi b/sys/gnu/dts/arm/omap3-ha-common.dtsi deleted file mode 100644 index 33132855d51..00000000000 --- a/sys/gnu/dts/arm/omap3-ha-common.dtsi +++ /dev/null @@ -1,85 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ - * Copyright (C) 2014 Stefan Roese - */ - -#include "omap3-tao3530.dtsi" - -/ { - gpio_poweroff { - pinctrl-names = "default"; - pinctrl-0 = <&poweroff_pins>; - - compatible = "gpio-poweroff"; - gpios = <&gpio6 8 GPIO_ACTIVE_LOW>; /* GPIO 168 */ - }; -}; - -&omap3_pmx_core { - sound2_pins: pinmux_sound2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x209e, PIN_OUTPUT | MUX_MODE4) /* gpmc_d8 gpio_44 */ - >; - }; - - led_blue_pins: pinmux_led_blue_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2110, PIN_OUTPUT | MUX_MODE4) /* cam_xclka gpio_96, LED blue */ - >; - }; - - led_green_pins: pinmux_led_green_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2126, PIN_OUTPUT | MUX_MODE4) /* cam_d8 gpio_107, LED green */ - >; - }; - - led_red_pins: pinmux_led_red_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x212e, PIN_OUTPUT_PULLUP | MUX_MODE4) /* cam_xclkb gpio_111, LED red */ - >; - }; - - poweroff_pins: pinmux_poweroff_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21be, PIN_OUTPUT_PULLUP | MUX_MODE4) /* i2c2_scl gpio_168 */ - >; - }; - - powerdown_input_pins: pinmux_powerdown_input_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT_PULLUP | MUX_MODE4) /* i2c2_sda gpio_183 */ - >; - }; - - fpga_boot0_pins: fpga_boot0_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x211a, PIN_INPUT | MUX_MODE4) /* cam_d2 gpio_101 */ - OMAP3_CORE1_IOPAD(0x211c, PIN_OUTPUT | MUX_MODE4) /* cam_d3 gpio_102 */ - OMAP3_CORE1_IOPAD(0x211e, PIN_OUTPUT | MUX_MODE4) /* cam_d4 gpio_103 */ - OMAP3_CORE1_IOPAD(0x2120, PIN_INPUT_PULLUP | MUX_MODE4) /* cam_d5 gpio_104 */ - >; - }; - - fpga_boot1_pins: fpga_boot1_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20a2, PIN_INPUT | MUX_MODE4) /* gpmc_d10 gpio_46 */ - OMAP3_CORE1_IOPAD(0x20a4, PIN_OUTPUT | MUX_MODE4) /* gpmc_d11 gpio_47 */ - OMAP3_CORE1_IOPAD(0x20a6, PIN_OUTPUT | MUX_MODE4) /* gpmc_d12 gpio_48 */ - OMAP3_CORE1_IOPAD(0x20a8, PIN_INPUT_PULLUP | MUX_MODE4) /* gpmc_d13 gpio_49 */ - >; - }; -}; - -/* I2C2: mux'ed with GPIO168 which is connected to nKILL_POWER */ -&i2c2 { - status = "disabled"; -}; - -&i2c3 { - clock-frequency = <100000>; - - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_pins>; -}; diff --git a/sys/gnu/dts/arm/omap3-ha-lcd.dts b/sys/gnu/dts/arm/omap3-ha-lcd.dts deleted file mode 100644 index badb9b3c889..00000000000 --- a/sys/gnu/dts/arm/omap3-ha-lcd.dts +++ /dev/null @@ -1,162 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ - * Copyright (C) 2014 Stefan Roese - */ - -#include "omap3-ha-common.dtsi" - -/ { - model = "TI OMAP3 HEAD acoustics LCD-baseboard with TAO3530 SOM"; - compatible = "headacoustics,omap3-ha-lcd", "technexion,omap3-tao3530", "ti,omap34xx", "ti,omap3"; -}; - -&omap3_pmx_core { - pinctrl-names = "default"; - pinctrl-0 = < - &hsusbb2_pins - &powerdown_input_pins - &fpga_boot0_pins - &fpga_boot1_pins - &led_blue_pins - &led_green_pins - &led_red_pins - &touchscreen_wake_pins - >; - - touchscreen_irq_pins: pinmux_touchscreen_irq_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT_PULLUP | MUX_MODE4) /* gpio_136, Touchscreen IRQ */ - >; - }; - - touchscreen_wake_pins: pinmux_touchscreen_wake_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x212c, PIN_OUTPUT_PULLUP | MUX_MODE4) /* gpio_110, Touchscreen Wake */ - >; - }; - - dss_dpi_pins: pinmux_dss_dpi_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ - OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ - OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ - OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ - OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ - OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ - OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ - OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ - OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ - OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ - OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ - OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ - OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ - OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ - OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ - OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ - OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ - OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ - OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ - OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ - OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ - OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ - OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */ - OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */ - OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */ - OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */ - OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ - OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ - >; - }; - - lte430_pins: pinmux_lte430_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat6.gpio_138 */ - >; - }; - - backlight_pins: pinmux_backlight_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x216a, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat7.gpio_139 */ - >; - }; -}; - -/* I2C2: mux'ed with GPIO168 which is connected to nKILL_POWER */ -&i2c2 { - status = "disabled"; -}; - -&i2c3 { - clock-frequency = <100000>; - - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_pins>; -}; - -/* Needed to power the DPI pins */ -&vpll2 { - regulator-always-on; -}; - -&dss { - status = "ok"; - - pinctrl-names = "default"; - pinctrl-0 = <&dss_dpi_pins>; - - port { - dpi_out: endpoint { - remote-endpoint = <&lcd_in>; - data-lines = <24>; - }; - }; -}; - -/ { - aliases { - display0 = &lcd0; - }; - - lcd0: display { - compatible = "panel-dpi"; - label = "lcd"; - - pinctrl-names = "default"; - pinctrl-0 = <<e430_pins>; - enable-gpios = <&gpio5 10 GPIO_ACTIVE_LOW>; /* gpio_138 */ - - port { - lcd_in: endpoint { - remote-endpoint = <&dpi_out>; - }; - }; - - panel-timing { - clock-frequency = <31250000>; - hactive = <800>; - vactive = <480>; - hfront-porch = <40>; - hback-porch = <86>; - hsync-len = <1>; - vback-porch = <30>; - vfront-porch = <13>; - vsync-len = <3>; - - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - - backlight { - compatible = "gpio-backlight"; - - pinctrl-names = "default"; - pinctrl-0 = <&backlight_pins>; - gpios = <&gpio5 11 GPIO_ACTIVE_HIGH>; /* gpio_139 */ - - default-on; - }; -}; diff --git a/sys/gnu/dts/arm/omap3-ha.dts b/sys/gnu/dts/arm/omap3-ha.dts deleted file mode 100644 index a5365252bfb..00000000000 --- a/sys/gnu/dts/arm/omap3-ha.dts +++ /dev/null @@ -1,25 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ - * Copyright (C) 2014 Stefan Roese - */ - -#include "omap3-ha-common.dtsi" - -/ { - model = "TI OMAP3 HEAD acoustics baseboard with TAO3530 SOM"; - compatible = "headacoustics,omap3-ha", "technexion,omap3-tao3530", "ti,omap34xx", "ti,omap3"; -}; - -&omap3_pmx_core { - pinctrl-names = "default"; - pinctrl-0 = < - &hsusbb2_pins - &powerdown_input_pins - &fpga_boot0_pins - &fpga_boot1_pins - &led_blue_pins - &led_green_pins - &led_red_pins - >; -}; diff --git a/sys/gnu/dts/arm/omap3-igep.dtsi b/sys/gnu/dts/arm/omap3-igep.dtsi deleted file mode 100644 index 5de2be9bbe6..00000000000 --- a/sys/gnu/dts/arm/omap3-igep.dtsi +++ /dev/null @@ -1,247 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Common device tree for IGEP boards based on AM/DM37x - * - * Copyright (C) 2012 Javier Martinez Canillas - * Copyright (C) 2012 Enric Balletbo i Serra - */ -/dts-v1/; - -#include "omap36xx.dtsi" - -/ { - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000>; /* 512 MB */ - }; - - chosen { - stdout-path = &uart3; - }; - - sound { - compatible = "ti,omap-twl4030"; - ti,model = "igep2"; - ti,mcbsp = <&mcbsp2>; - }; - - vdd33: regulator-vdd33 { - compatible = "regulator-fixed"; - regulator-name = "vdd33"; - regulator-always-on; - }; - -}; - -&omap3_pmx_core { - gpmc_pins: pinmux_gpmc_pins { - pinctrl-single,pins = < - /* OneNAND seems to require PIN_INPUT on clock. */ - OMAP3_CORE1_IOPAD(0x20be, PIN_INPUT | MUX_MODE0) /* gpmc_clk.gpmc_clk */ - >; - }; - - uart1_pins: pinmux_uart1_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE0) /* uart1_rx.uart1_rx */ - OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE0) /* uart1_tx.uart1_tx */ - >; - }; - - uart3_pins: pinmux_uart3_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx.uart3_rx */ - OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx.uart3_tx */ - >; - }; - - mcbsp2_pins: pinmux_mcbsp2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx.mcbsp2_fsx */ - OMAP3_CORE1_IOPAD(0x213e, PIN_INPUT | MUX_MODE0) /* mcbsp2_clkx.mcbsp2_clkx */ - OMAP3_CORE1_IOPAD(0x2140, PIN_INPUT | MUX_MODE0) /* mcbsp2_dr.mcbsp2.dr */ - OMAP3_CORE1_IOPAD(0x2142, PIN_OUTPUT | MUX_MODE0) /* mcbsp2_dx.mcbsp2_dx */ - >; - }; - - mmc1_pins: pinmux_mmc1_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ - OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ - OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ - OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ - OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ - OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ - >; - }; - - mmc2_pins: pinmux_mmc2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ - OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ - OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ - OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ - OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ - OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ - >; - }; - - i2c1_pins: pinmux_i2c1_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */ - OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */ - >; - }; - - i2c3_pins: pinmux_i2c3_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl.i2c3_scl */ - OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda.i2c3_sda */ - >; - }; -}; - -&gpmc { - pinctrl-names = "default"; - pinctrl-0 = <&gpmc_pins>; - - nand@0,0 { - compatible = "ti,omap2-nand"; - reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ - <1 IRQ_TYPE_NONE>; /* termcount */ - linux,mtd-name= "micron,mt29c4g96maz"; - nand-bus-width = <16>; - gpmc,device-width = <2>; - ti,nand-ecc-opt = "bch8"; - - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <44>; - gpmc,cs-wr-off-ns = <44>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <34>; - gpmc,adv-wr-off-ns = <44>; - gpmc,we-off-ns = <40>; - gpmc,oe-off-ns = <54>; - gpmc,access-ns = <64>; - gpmc,rd-cycle-ns = <82>; - gpmc,wr-cycle-ns = <82>; - gpmc,wr-access-ns = <40>; - gpmc,wr-data-mux-bus-ns = <0>; - - #address-cells = <1>; - #size-cells = <1>; - - status = "okay"; - }; - - onenand@0,0 { - compatible = "ti,omap2-onenand"; - reg = <0 0 0x20000>; /* CS0, offset 0, IO size 128K */ - - gpmc,sync-read; - gpmc,sync-write; - gpmc,burst-length = <16>; - gpmc,burst-wrap; - gpmc,burst-read; - gpmc,burst-write; - gpmc,device-width = <2>; /* GPMC_DEVWIDTH_16BIT */ - gpmc,mux-add-data = <2>; /* GPMC_MUX_AD */ - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <96>; - gpmc,cs-wr-off-ns = <96>; - gpmc,adv-on-ns = <0>; - gpmc,adv-rd-off-ns = <12>; - gpmc,adv-wr-off-ns = <12>; - gpmc,oe-on-ns = <18>; - gpmc,oe-off-ns = <96>; - gpmc,we-on-ns = <0>; - gpmc,we-off-ns = <96>; - gpmc,rd-cycle-ns = <114>; - gpmc,wr-cycle-ns = <114>; - gpmc,access-ns = <90>; - gpmc,page-burst-access-ns = <12>; - gpmc,bus-turnaround-ns = <0>; - gpmc,cycle2cycle-delay-ns = <0>; - gpmc,wait-monitoring-ns = <0>; - gpmc,clk-activation-ns = <6>; - gpmc,wr-data-mux-bus-ns = <30>; - gpmc,wr-access-ns = <90>; - gpmc,sync-clk-ps = <12000>; - - #address-cells = <1>; - #size-cells = <1>; - - status = "disabled"; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - clock-frequency = <2600000>; - - twl: twl@48 { - reg = <0x48>; - interrupts = <7>; /* SYS_NIRQ cascaded to intc */ - interrupt-parent = <&intc>; - - twl_audio: audio { - compatible = "ti,twl4030-audio"; - codec { - }; - }; - }; -}; - -#include "twl4030.dtsi" -#include "twl4030_omap3.dtsi" - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_pins>; -}; - -&mcbsp2 { - pinctrl-names = "default"; - pinctrl-0 = <&mcbsp2_pins>; - status = "okay"; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - vmmc-supply = <&vmmc1>; - vmmc_aux-supply = <&vsim>; - bus-width = <4>; - cd-gpios = <&twl_gpio 0 GPIO_ACTIVE_LOW>; -}; - -&mmc3 { - status = "disabled"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; -}; - -&twl_gpio { - ti,use-leds; -}; - -&usb_otg_hs { - interface-type = <0>; - usb-phy = <&usb2_phy>; - phys = <&usb2_phy>; - phy-names = "usb2-phy"; - mode = <3>; - power = <50>; -}; diff --git a/sys/gnu/dts/arm/omap3-igep0020-common.dtsi b/sys/gnu/dts/arm/omap3-igep0020-common.dtsi deleted file mode 100644 index 91caa50b74c..00000000000 --- a/sys/gnu/dts/arm/omap3-igep0020-common.dtsi +++ /dev/null @@ -1,261 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Common Device Tree Source for IGEPv2 - * - * Copyright (C) 2014 Javier Martinez Canillas - * Copyright (C) 2014 Enric Balletbo i Serra - */ - -#include "omap3-igep.dtsi" -#include "omap-gpmc-smsc9221.dtsi" - -/ { - - leds { - pinctrl-names = "default"; - pinctrl-0 = <&leds_pins>; - compatible = "gpio-leds"; - - boot { - label = "omap3:green:boot"; - gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - user0 { - label = "omap3:red:user0"; - gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - user1 { - label = "omap3:red:user1"; - gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - user2 { - label = "omap3:green:user1"; - gpios = <&twl_gpio 19 GPIO_ACTIVE_LOW>; - }; - }; - - /* HS USB Port 1 Power */ - hsusb1_power: hsusb1_power_reg { - compatible = "regulator-fixed"; - regulator-name = "hsusb1_vbus"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&twl_gpio 18 GPIO_ACTIVE_LOW>; /* GPIO LEDA */ - startup-delay-us = <70000>; - }; - - /* HS USB Host PHY on PORT 1 */ - hsusb1_phy: hsusb1_phy { - compatible = "usb-nop-xceiv"; - reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; /* gpio_24 */ - vcc-supply = <&hsusb1_power>; - #phy-cells = <0>; - }; - - tfp410: encoder { - compatible = "ti,tfp410"; - powerdown-gpios = <&gpio6 10 GPIO_ACTIVE_LOW>; /* gpio_170 */ - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - tfp410_in: endpoint { - remote-endpoint = <&dpi_out>; - }; - }; - - port@1 { - reg = <1>; - - tfp410_out: endpoint { - remote-endpoint = <&dvi_connector_in>; - }; - }; - }; - }; - - dvi0: connector { - compatible = "dvi-connector"; - label = "dvi"; - - digital; - - ddc-i2c-bus = <&i2c3>; - - port { - dvi_connector_in: endpoint { - remote-endpoint = <&tfp410_out>; - }; - }; - }; -}; - -&omap3_pmx_core { - pinctrl-names = "default"; - pinctrl-0 = < - &tfp410_pins - &dss_dpi_pins - >; - - tfp410_pins: pinmux_tfp410_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21c6, PIN_OUTPUT | MUX_MODE4) /* hdq_sio.gpio_170 */ - >; - }; - - dss_dpi_pins: pinmux_dss_dpi_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ - OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ - OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ - OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ - OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ - OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ - OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ - OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ - OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ - OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ - OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ - OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ - OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ - OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ - OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ - OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ - OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ - OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ - OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ - OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ - OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ - OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ - OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */ - OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */ - OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */ - OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */ - OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ - OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ - >; - }; - - uart2_pins: pinmux_uart2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT | MUX_MODE0) /* uart2_cts.uart2_cts */ - OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts .uart2_rts*/ - OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ - OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */ - >; - }; - - smsc9221_pins: pinmux_smsc9221_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21d2, PIN_INPUT | MUX_MODE4) /* mcspi1_cs2.gpio_176 */ - >; - }; -}; - -&omap3_pmx_core2 { - pinctrl-names = "default"; - pinctrl-0 = < - &hsusbb1_pins - >; - - hsusbb1_pins: pinmux_hsusbb1_pins { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25da, PIN_OUTPUT | MUX_MODE3) /* etk_ctl.hsusb1_clk */ - OMAP3630_CORE2_IOPAD(0x25d8, PIN_OUTPUT | MUX_MODE3) /* etk_clk.hsusb1_stp */ - OMAP3630_CORE2_IOPAD(0x25ec, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d8.hsusb1_dir */ - OMAP3630_CORE2_IOPAD(0x25ee, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d9.hsusb1_nxt */ - OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d0.hsusb1_data0 */ - OMAP3630_CORE2_IOPAD(0x25de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d1.hsusb1_data1 */ - OMAP3630_CORE2_IOPAD(0x25e0, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d2.hsusb1_data2 */ - OMAP3630_CORE2_IOPAD(0x25e2, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d3.hsusb1_data7 */ - OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d4.hsusb1_data4 */ - OMAP3630_CORE2_IOPAD(0x25e6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d5.hsusb1_data5 */ - OMAP3630_CORE2_IOPAD(0x25e8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d6.hsusb1_data6 */ - OMAP3630_CORE2_IOPAD(0x25ea, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d7.hsusb1_data3 */ - >; - }; - - leds_pins: pinmux_leds_pins { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25f4, PIN_OUTPUT | MUX_MODE4) /* etk_d12.gpio_26 */ - OMAP3630_CORE2_IOPAD(0x25f6, PIN_OUTPUT | MUX_MODE4) /* etk_d13.gpio_27 */ - OMAP3630_CORE2_IOPAD(0x25f8, PIN_OUTPUT | MUX_MODE4) /* etk_d14.gpio_28 */ - >; - }; - - mmc1_wp_pins: pinmux_mmc1_cd_pins { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT | MUX_MODE4) /* etk_d15.gpio_29 */ - >; - }; -}; - -&i2c3 { - clock-frequency = <100000>; - - /* - * Display monitor features are burnt in the EEPROM - * as EDID data. - */ - eeprom@50 { - compatible = "ti,eeprom"; - reg = <0x50>; - }; -}; - -&gpmc { - ranges = <0 0 0x30000000 0x01000000>, /* CS0: 16MB for NAND */ - <5 0 0x2c000000 0x01000000>; /* CS5: 16MB for ethernet */ - - ethernet@gpmc { - pinctrl-names = "default"; - pinctrl-0 = <&smsc9221_pins>; - reg = <5 0 0xff>; - interrupt-parent = <&gpio6>; - interrupts = <16 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; -}; - -&usbhshost { - port1-mode = "ehci-phy"; -}; - -&usbhsehci { - phys = <&hsusb1_phy>; -}; - -&vpll2 { - /* Needed for DSS */ - regulator-name = "vdds_dsi"; -}; - -&dss { - status = "ok"; - - port { - dpi_out: endpoint { - remote-endpoint = <&tfp410_in>; - data-lines = <24>; - }; - }; -}; - -&mmc1 { - pinctrl-0 = <&mmc1_pins &mmc1_wp_pins>; - wp-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; /* gpio_29 */ -}; diff --git a/sys/gnu/dts/arm/omap3-igep0020-rev-f.dts b/sys/gnu/dts/arm/omap3-igep0020-rev-f.dts deleted file mode 100644 index 03dcd05fb8a..00000000000 --- a/sys/gnu/dts/arm/omap3-igep0020-rev-f.dts +++ /dev/null @@ -1,51 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Device Tree Source for IGEPv2 Rev. F (TI OMAP AM/DM37x) - * - * Copyright (C) 2012 Javier Martinez Canillas - * Copyright (C) 2012 Enric Balletbo i Serra - */ - -#include "omap3-igep0020-common.dtsi" - -/ { - model = "IGEPv2 Rev. F (TI OMAP AM/DM37x)"; - compatible = "isee,omap3-igep0020-rev-f", "ti,omap36xx", "ti,omap3"; - - /* Regulator to trigger the WL_EN signal of the Wifi module */ - lbep5clwmc_wlen: regulator-lbep5clwmc-wlen { - compatible = "regulator-fixed"; - regulator-name = "regulator-lbep5clwmc-wlen"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio5 11 GPIO_ACTIVE_HIGH>; /* gpio_139 - WL_EN */ - enable-active-high; - }; -}; - -&omap3_pmx_core { - lbep5clwmc_pins: pinmux_lbep5clwmc_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT | MUX_MODE4) /* mcspi1_cs3.gpio_177 - W_IRQ */ - OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat5.gpio_137 - BT_EN */ - OMAP3_CORE1_IOPAD(0x216a, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat7.gpio_139 - WL_EN */ - >; - }; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins &lbep5clwmc_pins>; - vmmc-supply = <&lbep5clwmc_wlen>; - bus-width = <4>; - non-removable; - - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@2 { - compatible = "ti,wl1835"; - reg = <2>; - interrupt-parent = <&gpio6>; - interrupts = <17 IRQ_TYPE_EDGE_RISING>; /* gpio 177 */ - }; -}; diff --git a/sys/gnu/dts/arm/omap3-igep0020.dts b/sys/gnu/dts/arm/omap3-igep0020.dts deleted file mode 100644 index 6d0519e3dfd..00000000000 --- a/sys/gnu/dts/arm/omap3-igep0020.dts +++ /dev/null @@ -1,47 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Device Tree Source for IGEPv2 Rev. C (TI OMAP AM/DM37x) - * - * Copyright (C) 2012 Javier Martinez Canillas - * Copyright (C) 2012 Enric Balletbo i Serra - */ - -#include "omap3-igep0020-common.dtsi" - -/ { - model = "IGEPv2 Rev. C (TI OMAP AM/DM37x)"; - compatible = "isee,omap3-igep0020", "ti,omap36xx", "ti,omap3"; - - vmmcsdio_fixed: fixedregulator-mmcsdio { - compatible = "regulator-fixed"; - regulator-name = "vmmcsdio_fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - mmc2_pwrseq: mmc2_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>, /* gpio_139 - RESET_N_W */ - <&gpio5 10 GPIO_ACTIVE_LOW>; /* gpio_138 - WIFI_PDN */ - }; -}; - -&omap3_pmx_core { - lbee1usjyc_pins: pinmux_lbee1usjyc_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat5.gpio_137 - RESET_N_W */ - OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat6.gpio_138 - WIFI_PDN */ - OMAP3_CORE1_IOPAD(0x216a, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat7.gpio_139 - RST_N_B */ - >; - }; -}; - -/* On board Wifi module */ -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins &lbee1usjyc_pins>; - vmmc-supply = <&vmmcsdio_fixed>; - mmc-pwrseq = <&mmc2_pwrseq>; - bus-width = <4>; - non-removable; -}; diff --git a/sys/gnu/dts/arm/omap3-igep0030-common.dtsi b/sys/gnu/dts/arm/omap3-igep0030-common.dtsi deleted file mode 100644 index 71b0ae807ec..00000000000 --- a/sys/gnu/dts/arm/omap3-igep0030-common.dtsi +++ /dev/null @@ -1,103 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Common Device Tree Source for IGEP COM MODULE - * - * Copyright (C) 2014 Javier Martinez Canillas - * Copyright (C) 2014 Enric Balletbo i Serra - */ - -#include "omap3-igep.dtsi" - -/ { - leds: gpio_leds { - compatible = "gpio-leds"; - - user0 { - label = "omap3:red:user0"; - gpios = <&twl_gpio 18 GPIO_ACTIVE_LOW>; /* LEDA */ - default-state = "off"; - }; - - user1 { - label = "omap3:green:user1"; - gpios = <&twl_gpio 19 GPIO_ACTIVE_LOW>; /* LEDB */ - default-state = "off"; - }; - - user2 { - label = "omap3:red:user1"; - gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; /* gpio_16 */ - default-state = "off"; - }; - }; - - hsusb2_phy: hsusb2_phy { - compatible = "usb-nop-xceiv"; - reset-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>; /* gpio_54 */ - #phy-cells = <0>; - }; -}; - -&omap3_pmx_core { - pinctrl-names = "default"; - pinctrl-0 = <&hsusb2_pins>; - - hsusb2_pins: pinmux_hsusb2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */ - OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */ - OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */ - OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */ - OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */ - OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */ - >; - }; - - uart2_pins: pinmux_uart2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x216c, PIN_INPUT | MUX_MODE1) /* mcbsp3_dx.uart2_cts */ - OMAP3_CORE1_IOPAD(0x216e, PIN_OUTPUT | MUX_MODE1) /* mcbsp3_dr.uart2_rts */ - OMAP3_CORE1_IOPAD(0x2170, PIN_OUTPUT | MUX_MODE1) /* mcbsp3_clk.uart2_tx */ - OMAP3_CORE1_IOPAD(0x2172, PIN_INPUT | MUX_MODE1) /* mcbsp3_fsx.uart2_rx */ - >; - }; -}; - -&omap3_pmx_core2 { - pinctrl-names = "default"; - pinctrl-0 = <&hsusb2_core2_pins>; - - hsusb2_core2_pins: pinmux_hsusb2_core2_pins { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ - OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ - OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ - OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ - OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ - OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ - >; - }; - - leds_core2_pins: pinmux_leds_core2_pins { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE4) /* etk_d2.gpio_16 */ - >; - }; -}; - -&usbhshost { - port2-mode = "ehci-phy"; -}; - -&usbhsehci { - phys = <0 &hsusb2_phy>; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; -}; - -&gpmc { - ranges = <0 0 0x30000000 0x01000000>; /* CS0: 16MB for NAND */ -}; diff --git a/sys/gnu/dts/arm/omap3-igep0030-rev-g.dts b/sys/gnu/dts/arm/omap3-igep0030-rev-g.dts deleted file mode 100644 index 060acd1e803..00000000000 --- a/sys/gnu/dts/arm/omap3-igep0030-rev-g.dts +++ /dev/null @@ -1,73 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Device Tree Source for IGEP COM MODULE Rev. G (TI OMAP AM/DM37x) - * - * Copyright (C) 2014 Javier Martinez Canillas - * Copyright (C) 2014 Enric Balletbo i Serra - */ - -#include "omap3-igep0030-common.dtsi" - -/ { - model = "IGEP COM MODULE Rev. G (TI OMAP AM/DM37x)"; - compatible = "isee,omap3-igep0030-rev-g", "ti,omap36xx", "ti,omap3"; - - /* Regulator to trigger the WL_EN signal of the Wifi module */ - lbep5clwmc_wlen: regulator-lbep5clwmc-wlen { - compatible = "regulator-fixed"; - regulator-name = "regulator-lbep5clwmc-wlen"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio5 11 GPIO_ACTIVE_HIGH>; /* gpio_139 - WL_EN */ - enable-active-high; - }; -}; - -&omap3_pmx_core { - lbep5clwmc_pins: pinmux_lbep5clwmc_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT | MUX_MODE4) /* sdmmc2_dat4.gpio_136 - W_IRQ */ - OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat5.gpio_137 - BT_EN */ - OMAP3_CORE1_IOPAD(0x216a, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat7.gpio_139 - WL_EN */ - >; - }; - - leds_pins: pinmux_leds_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21be, PIN_OUTPUT | MUX_MODE4) /* i2c2_scl.gpio_168 */ - >; - }; - -}; - -&i2c2 { - status = "disabled"; -}; - -&leds { - pinctrl-names = "default"; - pinctrl-0 = <&leds_pins &leds_core2_pins>; - - boot { - label = "omap3:green:boot"; - gpios = <&gpio6 8 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins &lbep5clwmc_pins>; - vmmc-supply = <&lbep5clwmc_wlen>; - bus-width = <4>; - non-removable; - - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@2 { - compatible = "ti,wl1835"; - reg = <2>; - interrupt-parent = <&gpio5>; - interrupts = <8 IRQ_TYPE_EDGE_RISING>; /* gpio 136 */ - }; -}; diff --git a/sys/gnu/dts/arm/omap3-igep0030.dts b/sys/gnu/dts/arm/omap3-igep0030.dts deleted file mode 100644 index 25170bd3c57..00000000000 --- a/sys/gnu/dts/arm/omap3-igep0030.dts +++ /dev/null @@ -1,59 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Device Tree Source for IGEP COM MODULE Rev. E (TI OMAP AM/DM37x) - * - * Copyright (C) 2012 Javier Martinez Canillas - * Copyright (C) 2012 Enric Balletbo i Serra - */ - -#include "omap3-igep0030-common.dtsi" - -/ { - model = "IGEP COM MODULE Rev. E (TI OMAP AM/DM37x)"; - compatible = "isee,omap3-igep0030", "ti,omap36xx", "ti,omap3"; - - vmmcsdio_fixed: fixedregulator-mmcsdio { - compatible = "regulator-fixed"; - regulator-name = "vmmcsdio_fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - mmc2_pwrseq: mmc2_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>, /* gpio_139 - RESET_N_W */ - <&gpio5 10 GPIO_ACTIVE_LOW>; /* gpio_138 - WIFI_PDN */ - }; -}; - -&omap3_pmx_core { - lbee1usjyc_pins: pinmux_lbee1usjyc_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat5.gpio_137 - RESET_N_W */ - OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat6.gpio_138 - WIFI_PDN */ - OMAP3_CORE1_IOPAD(0x216a, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat7.gpio_139 - RST_N_B */ - >; - }; -}; - -&leds { - pinctrl-names = "default"; - pinctrl-0 = <&leds_core2_pins>; - - boot { - label = "omap3:green:boot"; - gpios = <&twl_gpio 13 GPIO_ACTIVE_LOW>; /* LEDSYNC */ - default-state = "on"; - }; -}; - -/* On board Wifi module */ -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins &lbee1usjyc_pins>; - vmmc-supply = <&vmmcsdio_fixed>; - mmc-pwrseq = <&mmc2_pwrseq>; - bus-width = <4>; - non-removable; -}; - diff --git a/sys/gnu/dts/arm/omap3-ldp.dts b/sys/gnu/dts/arm/omap3-ldp.dts deleted file mode 100644 index 9a5fde2d9bc..00000000000 --- a/sys/gnu/dts/arm/omap3-ldp.dts +++ /dev/null @@ -1,305 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ - */ -/dts-v1/; - -#include -#include "omap34xx.dtsi" -#include "omap-gpmc-smsc911x.dtsi" - -/ { - model = "TI OMAP3430 LDP (Zoom1 Labrador)"; - compatible = "ti,omap3-ldp", "ti,omap3"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x8000000>; /* 128 MB */ - }; - - cpus { - cpu@0 { - cpu0-supply = <&vcc>; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&gpio_key_pins>; - - key_enter { - label = "enter"; - gpios = <&gpio4 5 GPIO_ACTIVE_LOW>; /* gpio101 */ - linux,code = ; - wakeup-source; - }; - - key_f1 { - label = "f1"; - gpios = <&gpio4 6 GPIO_ACTIVE_LOW>; /* gpio102 */ - linux,code = ; - wakeup-source; - }; - - key_f2 { - label = "f2"; - gpios = <&gpio4 7 GPIO_ACTIVE_LOW>; /* gpio103 */ - linux,code = ; - wakeup-source; - }; - - key_f3 { - label = "f3"; - gpios = <&gpio4 8 GPIO_ACTIVE_LOW>; /* gpio104 */ - linux,code = ; - wakeup-source; - }; - - key_f4 { - label = "f4"; - gpios = <&gpio4 9 GPIO_ACTIVE_LOW>; /* gpio105 */ - linux,code = ; - wakeup-source; - }; - - key_left { - label = "left"; - gpios = <&gpio4 10 GPIO_ACTIVE_LOW>; /* gpio106 */ - linux,code = ; - wakeup-source; - }; - - key_right { - label = "right"; - gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; /* gpio107 */ - linux,code = ; - wakeup-source; - }; - - key_up { - label = "up"; - gpios = <&gpio4 12 GPIO_ACTIVE_LOW>; /* gpio108 */ - linux,code = ; - wakeup-source; - }; - - key_down { - label = "down"; - gpios = <&gpio4 13 GPIO_ACTIVE_LOW>; /* gpio109 */ - linux,code = ; - wakeup-source; - }; - }; -}; - -&gpmc { - ranges = <0 0 0x30000000 0x1000000>, /* CS0 space, 16MB */ - <1 0 0x08000000 0x1000000>; /* CS1 space, 16MB */ - - nand@0,0 { - compatible = "ti,omap2-nand"; - reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ - <1 IRQ_TYPE_NONE>; /* termcount */ - linux,mtd-name= "micron,nand"; - nand-bus-width = <16>; - gpmc,device-width = <2>; - ti,nand-ecc-opt = "bch8"; - - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <44>; - gpmc,cs-wr-off-ns = <44>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <34>; - gpmc,adv-wr-off-ns = <44>; - gpmc,we-off-ns = <40>; - gpmc,oe-off-ns = <54>; - gpmc,access-ns = <64>; - gpmc,rd-cycle-ns = <82>; - gpmc,wr-cycle-ns = <82>; - gpmc,wr-access-ns = <40>; - gpmc,wr-data-mux-bus-ns = <0>; - - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "X-Loader"; - reg = <0 0x80000>; - }; - partition@80000 { - label = "U-Boot"; - reg = <0x80000 0x140000>; - }; - partition@1c0000 { - label = "Environment"; - reg = <0x1c0000 0x40000>; - }; - partition@200000 { - label = "Kernel"; - reg = <0x200000 0x1e00000>; - }; - partition@2000000 { - label = "Filesystem"; - reg = <0x2000000 0x6000000>; - }; - }; - - ethernet@gpmc { - interrupt-parent = <&gpio5>; - interrupts = <24 IRQ_TYPE_LEVEL_LOW>; - reg = <1 0 0xff>; - }; -}; - -&i2c1 { - clock-frequency = <2600000>; - - twl: twl@48 { - reg = <0x48>; - interrupts = <7>; /* SYS_NIRQ cascaded to intc */ - interrupt-parent = <&intc>; - - twl_power: power { - compatible = "ti,twl4030-power-idle"; - ti,use_poweroff; - }; - }; -}; - -#include "twl4030.dtsi" -#include "twl4030_omap3.dtsi" -#include "omap3-panel-sharp-ls037v7dw01.dtsi" - -&backlight0 { - gpios = <&twl_gpio 7 GPIO_ACTIVE_HIGH>; -}; - -&i2c2 { - clock-frequency = <400000>; -}; - -&i2c3 { - clock-frequency = <400000>; -}; - -/* tps61130rsa enabled by twl4030 regen */ -&lcd_3v3 { - regulator-always-on; -}; - -&lcd0 { - enable-gpios = <&twl_gpio 15 GPIO_ACTIVE_HIGH>; /* lcd INI */ - reset-gpios = <&gpio2 23 GPIO_ACTIVE_HIGH>; /* gpio55, lcd RESB */ - mode-gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>; /* gpio56, lcd MO */ -}; - -&mcspi1 { - tsc2046@0 { - interrupt-parent = <&gpio2>; - interrupts = <22 0>; /* gpio54 */ - pendown-gpio = <&gpio2 22 GPIO_ACTIVE_HIGH>; - }; -}; - -&mmc1 { - /* See 35xx errata 2.1.1.128 in SPRZ278F */ - compatible = "ti,omap3-pre-es3-hsmmc"; - vmmc-supply = <&vmmc1>; - bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; -}; - -&mmc2 { - status="disabled"; -}; - -&mmc3 { - status="disabled"; -}; - -&omap3_pmx_core { - gpio_key_pins: pinmux_gpio_key_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x211a, PIN_INPUT | MUX_MODE4) /* cam_d2.gpio_101 */ - OMAP3_CORE1_IOPAD(0x211c, PIN_INPUT | MUX_MODE4) /* cam_d3.gpio_102 */ - OMAP3_CORE1_IOPAD(0x211e, PIN_INPUT | MUX_MODE4) /* cam_d4.gpio_103 */ - OMAP3_CORE1_IOPAD(0x2120, PIN_INPUT | MUX_MODE4) /* cam_d5.gpio_104 */ - OMAP3_CORE1_IOPAD(0x2122, PIN_INPUT | MUX_MODE4) /* cam_d6.gpio_105 */ - OMAP3_CORE1_IOPAD(0x2124, PIN_INPUT | MUX_MODE4) /* cam_d7.gpio_106 */ - OMAP3_CORE1_IOPAD(0x2126, PIN_INPUT | MUX_MODE4) /* cam_d8.gpio_107 */ - OMAP3_CORE1_IOPAD(0x2128, PIN_INPUT | MUX_MODE4) /* cam_d9.gpio_108 */ - OMAP3_CORE1_IOPAD(0x212a, PIN_INPUT | MUX_MODE4) /* cam_d10.gpio_109 */ - >; - }; - - musb_pins: pinmux_musb_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21a2, PIN_INPUT | MUX_MODE0) /* hsusb0_clk.hsusb0_clk */ - OMAP3_CORE1_IOPAD(0x21aa, PIN_INPUT | MUX_MODE0) /* hsusb0_data0.hsusb0_data0 */ - OMAP3_CORE1_IOPAD(0x21ac, PIN_INPUT | MUX_MODE0) /* hsusb0_data1.hsusb0_data1 */ - OMAP3_CORE1_IOPAD(0x21ae, PIN_INPUT | MUX_MODE0) /* hsusb0_data2.hsusb0_data2 */ - OMAP3_CORE1_IOPAD(0x21b0, PIN_INPUT | MUX_MODE0) /* hsusb0_data3.hsusb0_data3 */ - OMAP3_CORE1_IOPAD(0x21b2, PIN_INPUT | MUX_MODE0) /* hsusb0_data4.hsusb0_data4 */ - OMAP3_CORE1_IOPAD(0x21b4, PIN_INPUT | MUX_MODE0) /* hsusb0_data5.hsusb0_data5 */ - OMAP3_CORE1_IOPAD(0x21b6, PIN_INPUT | MUX_MODE0) /* hsusb0_data6.hsusb0_data6 */ - OMAP3_CORE1_IOPAD(0x21b8, PIN_INPUT | MUX_MODE0) /* hsusb0_data7.hsusb0_data7 */ - OMAP3_CORE1_IOPAD(0x21a6, PIN_INPUT | MUX_MODE0) /* hsusb0_dir.hsusb0_dir */ - OMAP3_CORE1_IOPAD(0x21a8, PIN_INPUT | MUX_MODE0) /* hsusb0_nxt.hsusb0_nxt */ - OMAP3_CORE1_IOPAD(0x21a4, PIN_OUTPUT | MUX_MODE0) /* hsusb0_stp.hsusb0_stp */ - >; - }; - - mmc1_pins: pinmux_mmc1_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.mmc1_clk */ - OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.mmc1_cmd */ - OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.mmc1_dat0 */ - OMAP3_CORE1_IOPAD(0x214A, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.mmc1_dat1 */ - OMAP3_CORE1_IOPAD(0x214C, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.mmc1_dat2 */ - OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.mmc1_dat3 */ - >; - }; -}; - -&twl_keypad { - linux,keymap = ; -}; - -&uart3 { - interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>; -}; - -&usb_otg_hs { - pinctrl-names = "default"; - pinctrl-0 = <&musb_pins>; - interface-type = <0>; - usb-phy = <&usb2_phy>; - mode = <3>; - power = <50>; -}; - -&vaux1 { - /* Needed for ads7846 */ - regulator-name = "vcc"; -}; diff --git a/sys/gnu/dts/arm/omap3-lilly-a83x.dtsi b/sys/gnu/dts/arm/omap3-lilly-a83x.dtsi deleted file mode 100644 index c22833d4e56..00000000000 --- a/sys/gnu/dts/arm/omap3-lilly-a83x.dtsi +++ /dev/null @@ -1,459 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (C) 2014 Christoph Fritz - */ - -#include "omap36xx.dtsi" - -/ { - model = "INCOstartec LILLY-A83X module (DM3730)"; - compatible = "incostartec,omap3-lilly-a83x", "ti,omap36xx", "ti,omap3"; - - chosen { - bootargs = "console=ttyO0,115200n8 vt.global_cursor_default=0 consoleblank=0"; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x8000000>; /* 128 MB */ - }; - - leds { - compatible = "gpio-leds"; - - led1 { - label = "lilly-a83x::led1"; - gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-on"; - }; - - }; - - sound { - compatible = "ti,omap-twl4030"; - ti,model = "lilly-a83x"; - - ti,mcbsp = <&mcbsp2>; - }; - - reg_vcc3: vcc3 { - compatible = "regulator-fixed"; - regulator-name = "VCC3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - hsusb1_phy: hsusb1_phy { - compatible = "usb-nop-xceiv"; - vcc-supply = <®_vcc3>; - #phy-cells = <0>; - }; -}; - -&omap3_pmx_wkup { - pinctrl-names = "default"; - - lan9221_pins: pinmux_lan9221_pins { - pinctrl-single,pins = < - OMAP3_WKUP_IOPAD(0x2a5a, PIN_INPUT | MUX_MODE4) /* reserved.gpio_129 */ - >; - }; - - tsc2048_pins: pinmux_tsc2048_pins { - pinctrl-single,pins = < - OMAP3_WKUP_IOPAD(0x2a16, PIN_INPUT_PULLUP | MUX_MODE4) /* sys_boot6.gpio_8 */ - >; - }; - - mmc1cd_pins: pinmux_mmc1cd_pins { - pinctrl-single,pins = < - OMAP3_WKUP_IOPAD(0x2a56, PIN_INPUT | MUX_MODE4) /* reserved.gpio_126 */ - >; - }; -}; - -&omap3_pmx_core { - pinctrl-names = "default"; - - uart1_pins: pinmux_uart1_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE0) /* uart1_tx.uart1_tx */ - OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE0) /* uart1_rts.uart1_rts */ - OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT | MUX_MODE0) /* uart1_cts.uart1_cts */ - OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE0) /* uart1_rx.uart1_rx */ - >; - }; - - uart2_pins: pinmux_uart2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2170, PIN_OUTPUT | MUX_MODE1) /* mcbsp3_clkx.uart2_tx */ - OMAP3_CORE1_IOPAD(0x2172, PIN_INPUT | MUX_MODE1) /* mcbsp3_fsx.uart2_rx */ - >; - }; - - uart3_pins: pinmux_uart3_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ - OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ - >; - }; - - i2c1_pins: pinmux_i2c1_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21ba ,PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl.i2c1_scl */ - OMAP3_CORE1_IOPAD(0x21bc ,PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda.i2c1_sda */ - >; - }; - - i2c2_pins: pinmux_i2c2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT | MUX_MODE0) /* i2c2_scl.i2c2_scl */ - OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT | MUX_MODE0) /* i2c2_sda.i2c2_sda */ - >; - }; - - i2c3_pins: pinmux_i2c3_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl.i2c3_scl */ - OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda.i2c3_sda */ - >; - }; - - hsusb1_pins: pinmux_hsusb1_pins { - pinctrl-single,pins = < - - /* GPIO 182 controls USB-Hub reset. But USB-Phy its - * reset can't be controlled. So we clamp this GPIO to - * high (PIN_OFF_OUTPUT_HIGH) to always enable USB-Hub. - */ - - OMAP3_CORE1_IOPAD(0x21de, PIN_OUTPUT_PULLUP | PIN_OFF_OUTPUT_HIGH | MUX_MODE4) /* mcspi2_cs1.gpio_182 */ - >; - }; - - hsusb_otg_pins: pinmux_hsusb_otg_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21a2, PIN_INPUT | MUX_MODE0) /* hsusb0_clk.hsusb0_clk */ - OMAP3_CORE1_IOPAD(0x21a4, PIN_OUTPUT | MUX_MODE0) /* hsusb0_stp.hsusb0_stp */ - OMAP3_CORE1_IOPAD(0x21a6, PIN_INPUT | MUX_MODE0) /* hsusb0_dir.hsusb0_dir */ - OMAP3_CORE1_IOPAD(0x21a8, PIN_INPUT | MUX_MODE0) /* hsusb0_nxt.hsusb0_nxt */ - OMAP3_CORE1_IOPAD(0x21aa, PIN_INPUT | MUX_MODE0) /* hsusb0_data0.hsusb0_data0 */ - OMAP3_CORE1_IOPAD(0x21ac, PIN_INPUT | MUX_MODE0) /* hsusb0_data1.hsusb0_data1 */ - OMAP3_CORE1_IOPAD(0x21ae, PIN_INPUT | MUX_MODE0) /* hsusb0_data2.hsusb0_data2 */ - OMAP3_CORE1_IOPAD(0x21b0, PIN_INPUT | MUX_MODE0) /* hsusb0_data3.hsusb0_data3 */ - OMAP3_CORE1_IOPAD(0x21b2, PIN_INPUT | MUX_MODE0) /* hsusb0_data4.hsusb0_data4 */ - OMAP3_CORE1_IOPAD(0x21b4, PIN_INPUT | MUX_MODE0) /* hsusb0_data5.hsusb0_data5 */ - OMAP3_CORE1_IOPAD(0x21b6, PIN_INPUT | MUX_MODE0) /* hsusb0_data6.hsusb0_data6 */ - OMAP3_CORE1_IOPAD(0x21b8, PIN_INPUT | MUX_MODE0) /* hsusb0_data7.hsusb0_data7 */ - >; - }; - - mmc1_pins: pinmux_mmc1_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ - OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ - OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ - OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ - OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ - OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ - >; - }; - - spi2_pins: pinmux_spi2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcspi2_clk.mcspi2_clk */ - OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcspi2_simo.mcspi2_simo */ - OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcspi2_somi.mcspi2_somi */ - OMAP3_CORE1_IOPAD(0x21dc, PIN_OUTPUT | MUX_MODE0) /* mcspi2_cs0.mcspi2_cs0 */ - >; - }; -}; - -&omap3_pmx_core2 { - pinctrl-names = "default"; - - hsusb1_2_pins: pinmux_hsusb1_2_pins { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25d8, PIN_OUTPUT | MUX_MODE3) /* etk_clk.hsusb1_stp */ - OMAP3630_CORE2_IOPAD(0x25da, PIN_INPUT | MUX_MODE3) /* etk_ctl.hsusb1_clk */ - OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE3) /* etk_d0.hsusb1_data0 */ - OMAP3630_CORE2_IOPAD(0x25de, PIN_INPUT | MUX_MODE3) /* etk_d1.hsusb1_data1 */ - OMAP3630_CORE2_IOPAD(0x25e0, PIN_INPUT | MUX_MODE3) /* etk_d2.hsusb1_data2 */ - OMAP3630_CORE2_IOPAD(0x25e2, PIN_INPUT | MUX_MODE3) /* etk_d3.hsusb1_data7 */ - OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT | MUX_MODE3) /* etk_d4.hsusb1_data4 */ - OMAP3630_CORE2_IOPAD(0x25e6, PIN_INPUT | MUX_MODE3) /* etk_d5.hsusb1_data5 */ - OMAP3630_CORE2_IOPAD(0x25e8, PIN_INPUT | MUX_MODE3) /* etk_d6.hsusb1_data6 */ - OMAP3630_CORE2_IOPAD(0x25ea, PIN_INPUT | MUX_MODE3) /* etk_d7.hsusb1_data3 */ - OMAP3630_CORE2_IOPAD(0x25ec, PIN_INPUT | MUX_MODE3) /* etk_d8.hsusb1_dir */ - OMAP3630_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE3) /* etk_d9.hsusb1_nxt */ - >; - }; - - gpio1_pins: pinmux_gpio1_pins { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25fa, PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* etk_d15.gpio_29 */ - >; - }; - -}; - -&gpio1 { - pinctrl-names = "default"; - pinctrl-0 = <&gpio1_pins>; -}; - -&gpio6 { - pinctrl-names = "default"; - pinctrl-0 = <&hsusb1_pins>; -}; - -&i2c1 { - clock-frequency = <2600000>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - - twl: twl@48 { - reg = <0x48>; - interrupts = <7>; /* SYS_NIRQ cascaded to intc */ - interrupt-parent = <&intc>; - - twl_audio: audio { - compatible = "ti,twl4030-audio"; - codec { - }; - }; - }; -}; - -#include "twl4030.dtsi" -#include "twl4030_omap3.dtsi" - -&twl { - vmmc1: regulator-vmmc1 { - regulator-always-on; - }; - - vdd1: regulator-vdd1 { - regulator-always-on; - }; - - vdd2: regulator-vdd2 { - regulator-always-on; - }; -}; - -&i2c2 { - clock-frequency = <2600000>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; -}; - -&i2c3 { - clock-frequency = <2600000>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_pins>; - gpiom1: gpio@20 { - compatible = "microchip,mcp23017"; - gpio-controller; - #gpio-cells = <2>; - reg = <0x20>; - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; -}; - -&uart4 { - status = "disabled"; -}; - -&mmc1 { - cd-gpios = <&gpio4 30 GPIO_ACTIVE_LOW>; - cd-inverted; - vmmc-supply = <&vmmc1>; - bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins &mmc1cd_pins>; - cap-sdio-irq; - cap-sd-highspeed; - cap-mmc-highspeed; -}; - -&mmc2 { - status = "disabled"; -}; - -&mmc3 { - status = "disabled"; -}; - -&mcspi2 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&spi2_pins>; - - tsc2046@0 { - reg = <0>; /* CS0 */ - compatible = "ti,tsc2046"; - interrupt-parent = <&gpio1>; - interrupts = <8 0>; /* boot6 / gpio_8 */ - spi-max-frequency = <1000000>; - pendown-gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>; - vcc-supply = <®_vcc3>; - pinctrl-names = "default"; - pinctrl-0 = <&tsc2048_pins>; - - ti,x-min = /bits/ 16 <300>; - ti,x-max = /bits/ 16 <3000>; - ti,y-min = /bits/ 16 <600>; - ti,y-max = /bits/ 16 <3600>; - ti,x-plate-ohms = /bits/ 16 <80>; - ti,pressure-max = /bits/ 16 <255>; - ti,swap-xy; - - wakeup-source; - }; -}; - -&usbhsehci { - phys = <&hsusb1_phy>; -}; - -&usbhshost { - pinctrl-names = "default"; - pinctrl-0 = <&hsusb1_2_pins>; - num-ports = <2>; - port1-mode = "ehci-phy"; -}; - -&usb_otg_hs { - pinctrl-names = "default"; - pinctrl-0 = <&hsusb_otg_pins>; - interface-type = <0>; - usb-phy = <&usb2_phy>; - phys = <&usb2_phy>; - phy-names = "usb2-phy"; - mode = <3>; - power = <50>; -}; - -&mcbsp2 { - status = "okay"; -}; - -&gpmc { - ranges = <0 0 0x30000000 0x1000000>, - <7 0 0x15000000 0x01000000>; - - nand@0,0 { - compatible = "ti,omap2-nand"; - reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ - <1 IRQ_TYPE_NONE>; /* termcount */ - nand-bus-width = <16>; - ti,nand-ecc-opt = "bch8"; - /* no elm on omap3 */ - - gpmc,mux-add-data = <0>; - gpmc,device-width = <2>; - gpmc,wait-pin = <0>; - gpmc,wait-monitoring-ns = <0>; - gpmc,burst-length= <4>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <100>; - gpmc,cs-wr-off-ns = <100>; - gpmc,adv-on-ns = <0>; - gpmc,adv-rd-off-ns = <100>; - gpmc,adv-wr-off-ns = <100>; - gpmc,oe-on-ns = <5>; - gpmc,oe-off-ns = <75>; - gpmc,we-on-ns = <5>; - gpmc,we-off-ns = <75>; - gpmc,rd-cycle-ns = <100>; - gpmc,wr-cycle-ns = <100>; - gpmc,access-ns = <60>; - gpmc,page-burst-access-ns = <5>; - gpmc,bus-turnaround-ns = <0>; - gpmc,cycle2cycle-samecsen; - gpmc,cycle2cycle-delay-ns = <50>; - gpmc,wr-data-mux-bus-ns = <75>; - gpmc,wr-access-ns = <155>; - - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "MLO"; - reg = <0 0x80000>; - }; - - partition@80000 { - label = "u-boot"; - reg = <0x80000 0x1e0000>; - }; - - partition@260000 { - label = "u-boot-environment"; - reg = <0x260000 0x20000>; - }; - - partition@280000 { - label = "kernel"; - reg = <0x280000 0x500000>; - }; - - partition@780000 { - label = "filesystem"; - reg = <0x780000 0xf880000>; - }; - }; - - ethernet@7,0 { - compatible = "smsc,lan9221", "smsc,lan9115"; - bank-width = <2>; - gpmc,mux-add-data = <2>; - gpmc,cs-on-ns = <10>; - gpmc,cs-rd-off-ns = <60>; - gpmc,cs-wr-off-ns = <60>; - gpmc,adv-on-ns = <0>; - gpmc,adv-rd-off-ns = <10>; - gpmc,adv-wr-off-ns = <10>; - gpmc,oe-on-ns = <10>; - gpmc,oe-off-ns = <60>; - gpmc,we-on-ns = <10>; - gpmc,we-off-ns = <60>; - gpmc,rd-cycle-ns = <100>; - gpmc,wr-cycle-ns = <100>; - gpmc,access-ns = <50>; - gpmc,page-burst-access-ns = <5>; - gpmc,bus-turnaround-ns = <0>; - gpmc,cycle2cycle-delay-ns = <75>; - gpmc,wr-data-mux-bus-ns = <15>; - gpmc,wr-access-ns = <75>; - gpmc,cycle2cycle-samecsen; - gpmc,cycle2cycle-diffcsen; - vddvario-supply = <®_vcc3>; - vdd33a-supply = <®_vcc3>; - reg-io-width = <4>; - interrupt-parent = <&gpio5>; - interrupts = <1 0x2>; - reg = <7 0 0xff>; - pinctrl-names = "default"; - pinctrl-0 = <&lan9221_pins>; - phy-mode = "mii"; - }; -}; diff --git a/sys/gnu/dts/arm/omap3-lilly-dbb056.dts b/sys/gnu/dts/arm/omap3-lilly-dbb056.dts deleted file mode 100644 index fec33540007..00000000000 --- a/sys/gnu/dts/arm/omap3-lilly-dbb056.dts +++ /dev/null @@ -1,166 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (C) 2014 Christoph Fritz - */ -/dts-v1/; - -#include "omap3-lilly-a83x.dtsi" - -/ { - model = "INCOstartec LILLY-DBB056 (DM3730)"; - compatible = "incostartec,omap3-lilly-dbb056", "incostartec,omap3-lilly-a83x", "ti,omap36xx", "ti,omap3"; -}; - -&twl { - vaux2: regulator-vaux2 { - compatible = "ti,twl4030-vaux2"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; -}; - -&omap3_pmx_core { - pinctrl-names = "default"; - pinctrl-0 = <&lcd_pins>; - - lan9117_pins: pinmux_lan9117_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2114, PIN_INPUT | MUX_MODE4) /* cam_fld.gpio_98 */ - >; - }; - - gpio4_pins: pinmux_gpio4_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x212e, PIN_INPUT | MUX_MODE4) /* cam_xclkb.gpio_111 -> sja1000 IRQ */ - >; - }; - - gpio5_pins: pinmux_gpio5_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x218c, PIN_OUTPUT | PIN_OFF_OUTPUT_HIGH | MUX_MODE4) /* mcbsp1_clk.gpio_156 -> enable DSS */ - >; - }; - - lcd_pins: pinmux_lcd_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ - OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ - OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ - OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ - OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ - OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ - OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ - OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ - OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ - OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ - OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ - OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ - OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ - OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ - OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ - OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ - OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ - OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ - OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ - OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ - OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ - OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ - >; - }; - - mmc2_pins: pinmux_mmc2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ - OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ - OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ - OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ - OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ - OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ - OMAP3_CORE1_IOPAD(0x2164, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat4.sdmmc2_dir_dat0 */ - OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat5.sdmmc2_dir_dat1 */ - OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat6.sdmmc2_dir_cmd */ - OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT | MUX_MODE1) /* sdmmc2_dat7.sdmmc2_clkin */ - OMAP3_CORE1_IOPAD(0x219a, PIN_INPUT_PULLUP | MUX_MODE4) /* uart3_cts_rctx.gpio_163 -> wp */ - OMAP3_CORE1_IOPAD(0x219c, PIN_INPUT_PULLUP | MUX_MODE4) /* uart3_rts_sd.gpio_164 -> cd */ - >; - }; - - spi1_pins: pinmux_spi1_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */ - OMAP3_CORE1_IOPAD(0x21ca, PIN_INPUT | MUX_MODE0) /* mcspi1_simo.mcspi1_simo */ - OMAP3_CORE1_IOPAD(0x21cc, PIN_INPUT | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */ - OMAP3_CORE1_IOPAD(0x21ce, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcspi1_cs0.mcspi1_cs0 */ - >; - }; -}; - -&gpio4 { - pinctrl-names = "default"; - pinctrl-0 = <&gpio4_pins>; -}; - -&gpio5 { - pinctrl-names = "default"; - pinctrl-0 = <&gpio5_pins>; -}; - -&mmc2 { - status = "okay"; - bus-width = <4>; - vmmc-supply = <&vmmc1>; - cd-gpios = <&gpio6 4 GPIO_ACTIVE_HIGH>; /* gpio_164 */ - wp-gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>; /* gpio_163 */ - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; - ti,dual-volt; -}; - -&mcspi1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&spi1_pins>; -}; - -&gpmc { - ranges = <0 0 0x30000000 0x1000000>, /* nand assigned by COM a83x */ - <4 0 0x20000000 0x01000000>, - <7 0 0x15000000 0x01000000>; /* eth assigend by COM a83x */ - - ethernet@4,0 { - compatible = "smsc,lan9117", "smsc,lan9115"; - bank-width = <2>; - gpmc,mux-add-data = <2>; - gpmc,cs-on-ns = <10>; - gpmc,cs-rd-off-ns = <65>; - gpmc,cs-wr-off-ns = <65>; - gpmc,adv-on-ns = <0>; - gpmc,adv-rd-off-ns = <10>; - gpmc,adv-wr-off-ns = <10>; - gpmc,oe-on-ns = <10>; - gpmc,oe-off-ns = <65>; - gpmc,we-on-ns = <10>; - gpmc,we-off-ns = <65>; - gpmc,rd-cycle-ns = <100>; - gpmc,wr-cycle-ns = <100>; - gpmc,access-ns = <60>; - gpmc,page-burst-access-ns = <5>; - gpmc,bus-turnaround-ns = <0>; - gpmc,cycle2cycle-delay-ns = <75>; - gpmc,wr-data-mux-bus-ns = <15>; - gpmc,wr-access-ns = <75>; - gpmc,cycle2cycle-samecsen; - gpmc,cycle2cycle-diffcsen; - vddvario-supply = <®_vcc3>; - vdd33a-supply = <®_vcc3>; - reg-io-width = <4>; - interrupt-parent = <&gpio4>; - interrupts = <2 0x2>; - reg = <4 0 0xff>; - pinctrl-names = "default"; - pinctrl-0 = <&lan9117_pins>; - phy-mode = "mii"; - smsc,force-internal-phy; - }; -}; diff --git a/sys/gnu/dts/arm/omap3-n9.dts b/sys/gnu/dts/arm/omap3-n9.dts deleted file mode 100644 index 74c0ff2350d..00000000000 --- a/sys/gnu/dts/arm/omap3-n9.dts +++ /dev/null @@ -1,85 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * omap3-n9.dts - Device Tree file for Nokia N9 - * - * Written by: Aaro Koskinen - */ - -/dts-v1/; - -#include "omap3-n950-n9.dtsi" -#include - -/ { - model = "Nokia N9"; - compatible = "nokia,omap3-n9", "ti,omap36xx", "ti,omap3"; -}; - -&i2c2 { - smia_1: camera@10 { - compatible = "nokia,smia"; - reg = <0x10>; - /* No reset gpio */ - vana-supply = <&vaux3>; - clocks = <&isp 0>; - clock-frequency = <9600000>; - nokia,nvm-size = <(16 * 64)>; - flash-leds = <&as3645a_flash &as3645a_indicator>; - port { - smia_1_1: endpoint { - link-frequencies = /bits/ 64 <199200000 210000000 499200000>; - clock-lanes = <0>; - data-lanes = <1 2>; - remote-endpoint = <&csi2a_ep>; - }; - }; - }; -}; - -&i2c3 { - ak8975@f { - compatible = "asahi-kasei,ak8975"; - reg = <0x0f>; - }; -}; - -&isp { - vdd-csiphy1-supply = <&vaux2>; - vdd-csiphy2-supply = <&vaux2>; - ports { - port@2 { - reg = <2>; - csi2a_ep: endpoint { - remote-endpoint = <&smia_1_1>; - clock-lanes = <2>; - data-lanes = <1 3>; - crc = <1>; - lane-polarities = <1 1 1>; - }; - }; - }; -}; - -&modem { - compatible = "nokia,n9-modem"; -}; - -&lis302 { - st,axis-x = <1>; /* LIS3_DEV_X */ - st,axis-y = <(-2)>; /* LIS3_INV_DEV_Y */ - st,axis-z = <(-3)>; /* LIS3_INV_DEV_Z */ - - st,min-limit-x = <(-46)>; - st,min-limit-y = <3>; - st,min-limit-z = <3>; - - st,max-limit-x = <(-3)>; - st,max-limit-y = <46>; - st,max-limit-z = <46>; -}; - -&twl_keypad { - linux,keymap = < MATRIX_KEY(6, 8, KEY_VOLUMEUP) - MATRIX_KEY(7, 8, KEY_VOLUMEDOWN) - >; -}; diff --git a/sys/gnu/dts/arm/omap3-n900.dts b/sys/gnu/dts/arm/omap3-n900.dts deleted file mode 100644 index 84a5ade1e86..00000000000 --- a/sys/gnu/dts/arm/omap3-n900.dts +++ /dev/null @@ -1,1128 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (C) 2013 Pavel Machek - * Copyright (C) 2013-2014 Aaro Koskinen - */ - -/dts-v1/; - -#include "omap34xx.dtsi" -#include - -/* - * Default secure signed bootloader (Nokia X-Loader) does not enable L3 firewall - * for omap AES HW crypto support. When linux kernel try to access memory of AES - * blocks then kernel receive "Unhandled fault: external abort on non-linefetch" - * and crash. Until somebody fix omap-aes.c and omap_hwmod_3xxx_data.c code (no - * crash anymore) omap AES support will be disabled for all Nokia N900 devices. - * There is "unofficial" version of bootloader which enables AES in L3 firewall - * but it is not widely used and to prevent kernel crash rather AES is disabled. - * There is also no runtime detection code if AES is disabled in L3 firewall... - */ -&aes { - status = "disabled"; -}; - -/ { - model = "Nokia N900"; - compatible = "nokia,omap3-n900", "ti,omap3430", "ti,omap3"; - - aliases { - i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - display0 = &lcd; - display1 = &tv; - }; - - cpus { - cpu@0 { - cpu0-supply = <&vcc>; - }; - }; - - leds { - compatible = "gpio-leds"; - heartbeat { - label = "debug::sleep"; - gpios = <&gpio6 2 GPIO_ACTIVE_HIGH>; /* 162 */ - linux,default-trigger = "default-on"; - pinctrl-names = "default"; - pinctrl-0 = <&debug_leds>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x10000000>; /* 256 MB */ - }; - - gpio_keys { - compatible = "gpio-keys"; - - camera_lens_cover { - label = "Camera Lens Cover"; - gpios = <&gpio4 14 GPIO_ACTIVE_LOW>; /* 110 */ - linux,input-type = ; - linux,code = ; - linux,can-disable; - }; - - camera_focus { - label = "Camera Focus"; - gpios = <&gpio3 4 GPIO_ACTIVE_LOW>; /* 68 */ - linux,code = ; - linux,can-disable; - }; - - camera_capture { - label = "Camera Capture"; - gpios = <&gpio3 5 GPIO_ACTIVE_LOW>; /* 69 */ - linux,code = ; - linux,can-disable; - }; - - lock_button { - label = "Lock Button"; - gpios = <&gpio4 17 GPIO_ACTIVE_LOW>; /* 113 */ - linux,code = ; - linux,can-disable; - }; - - keypad_slide { - label = "Keypad Slide"; - gpios = <&gpio3 7 GPIO_ACTIVE_LOW>; /* 71 */ - linux,input-type = ; - linux,code = ; - linux,can-disable; - }; - - proximity_sensor { - label = "Proximity Sensor"; - gpios = <&gpio3 25 GPIO_ACTIVE_HIGH>; /* 89 */ - linux,input-type = ; - linux,code = ; - linux,can-disable; - }; - }; - - isp1707: isp1707 { - compatible = "nxp,isp1707"; - nxp,enable-gpio = <&gpio3 3 GPIO_ACTIVE_HIGH>; - usb-phy = <&usb2_phy>; - }; - - tv: connector { - compatible = "composite-video-connector"; - label = "tv"; - - port { - tv_connector_in: endpoint { - remote-endpoint = <&venc_out>; - }; - }; - }; - - sound: n900-audio { - compatible = "nokia,n900-audio"; - - nokia,cpu-dai = <&mcbsp2>; - nokia,audio-codec = <&tlv320aic3x>, <&tlv320aic3x_aux>; - nokia,headphone-amplifier = <&tpa6130a2>; - - tvout-selection-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; /* 40 */ - jack-detection-gpios = <&gpio6 17 GPIO_ACTIVE_HIGH>; /* 177 */ - eci-switch-gpios = <&gpio6 22 GPIO_ACTIVE_HIGH>; /* 182 */ - speaker-amplifier-gpios = <&twl_gpio 7 GPIO_ACTIVE_HIGH>; - }; - - battery: n900-battery { - compatible = "nokia,n900-battery"; - io-channels = <&twl_madc 0>, <&twl_madc 4>, <&twl_madc 12>; - io-channel-names = "temp", "bsi", "vbat"; - }; - - pwm9: dmtimer-pwm { - compatible = "ti,omap-dmtimer-pwm"; - #pwm-cells = <3>; - ti,timers = <&timer9>; - ti,clock-source = <0x00>; /* timer_sys_ck */ - }; - - ir: n900-ir { - compatible = "nokia,n900-ir"; - pwms = <&pwm9 0 26316 0>; /* 38000 Hz */ - }; - - /* controlled (enabled/disabled) directly by bcm2048 and wl1251 */ - vctcxo: vctcxo { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <38400000>; - }; -}; - -&isp { - vdds_csib-supply = <&vaux2>; - - pinctrl-names = "default"; - pinctrl-0 = <&camera_pins>; - - ports { - port@1 { - reg = <1>; - - csi_isp: endpoint { - remote-endpoint = <&csi_cam1>; - bus-type = <3>; /* CCP2 */ - clock-lanes = <1>; - data-lanes = <0>; - lane-polarity = <0 0>; - /* Select strobe = <1> for back camera, <0> for front camera */ - strobe = <1>; - }; - }; - }; -}; - -&omap3_pmx_core { - pinctrl-names = "default"; - - uart2_pins: pinmux_uart2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts */ - OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts */ - OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx */ - OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx */ - >; - }; - - uart3_pins: pinmux_uart3_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx */ - OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx */ - >; - }; - - ethernet_pins: pinmux_ethernet_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20b4, PIN_INPUT_PULLDOWN | MUX_MODE4) /* gpmc_ncs3.gpio_54 */ - OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE4) /* dss_data16.gpio_86 */ - OMAP3_CORE1_IOPAD(0x219c, PIN_OUTPUT | MUX_MODE4) /* uart3_rts_sd.gpio_164 */ - >; - }; - - gpmc_pins: pinmux_gpmc_pins { - pinctrl-single,pins = < - - /* address lines */ - OMAP3_CORE1_IOPAD(0x207a, PIN_OUTPUT | MUX_MODE0) /* gpmc_a1.gpmc_a1 */ - OMAP3_CORE1_IOPAD(0x207c, PIN_OUTPUT | MUX_MODE0) /* gpmc_a2.gpmc_a2 */ - OMAP3_CORE1_IOPAD(0x207e, PIN_OUTPUT | MUX_MODE0) /* gpmc_a3.gpmc_a3 */ - - /* data lines, gpmc_d0..d7 not muxable according to TRM */ - OMAP3_CORE1_IOPAD(0x209e, PIN_INPUT | MUX_MODE0) /* gpmc_d8.gpmc_d8 */ - OMAP3_CORE1_IOPAD(0x20a0, PIN_INPUT | MUX_MODE0) /* gpmc_d9.gpmc_d9 */ - OMAP3_CORE1_IOPAD(0x20a2, PIN_INPUT | MUX_MODE0) /* gpmc_d10.gpmc_d10 */ - OMAP3_CORE1_IOPAD(0x20a4, PIN_INPUT | MUX_MODE0) /* gpmc_d11.gpmc_d11 */ - OMAP3_CORE1_IOPAD(0x20a6, PIN_INPUT | MUX_MODE0) /* gpmc_d12.gpmc_d12 */ - OMAP3_CORE1_IOPAD(0x20a8, PIN_INPUT | MUX_MODE0) /* gpmc_d13.gpmc_d13 */ - OMAP3_CORE1_IOPAD(0x20aa, PIN_INPUT | MUX_MODE0) /* gpmc_d14.gpmc_d14 */ - OMAP3_CORE1_IOPAD(0x20ac, PIN_INPUT | MUX_MODE0) /* gpmc_d15.gpmc_d15 */ - - /* - * gpmc_ncs0, gpmc_nadv_ale, gpmc_noe, gpmc_nwe, gpmc_wait0 not muxable - * according to TRM. OneNAND seems to require PIN_INPUT on clock. - */ - OMAP3_CORE1_IOPAD(0x20b0, PIN_OUTPUT | MUX_MODE0) /* gpmc_ncs1.gpmc_ncs1 */ - OMAP3_CORE1_IOPAD(0x20be, PIN_INPUT | MUX_MODE0) /* gpmc_clk.gpmc_clk */ - >; - }; - - i2c1_pins: pinmux_i2c1_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0) /* i2c1_scl */ - OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0) /* i2c1_sda */ - >; - }; - - i2c2_pins: pinmux_i2c2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT | MUX_MODE0) /* i2c2_scl */ - OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT | MUX_MODE0) /* i2c2_sda */ - >; - }; - - i2c3_pins: pinmux_i2c3_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl */ - OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda */ - >; - }; - - debug_leds: pinmux_debug_led_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2198, PIN_OUTPUT | MUX_MODE4) /* mcbsp1_clkx.gpio_162 */ - >; - }; - - mcspi4_pins: pinmux_mcspi4_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x218c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mcspi4_clk */ - OMAP3_CORE1_IOPAD(0x2192, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mcspi4_somi */ - OMAP3_CORE1_IOPAD(0x2190, PIN_OUTPUT | MUX_MODE1) /* mcspi4_simo */ - OMAP3_CORE1_IOPAD(0x2196, PIN_OUTPUT | MUX_MODE1) /* mcspi4_cs0 */ - >; - }; - - mmc1_pins: pinmux_mmc1_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk */ - OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd */ - OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0 */ - OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1 */ - OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2 */ - OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3 */ - >; - }; - - mmc2_pins: pinmux_mmc2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk */ - OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd */ - OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0 */ - OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1 */ - OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2 */ - OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3 */ - OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat4 */ - OMAP3_CORE1_IOPAD(0x2166, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat5 */ - OMAP3_CORE1_IOPAD(0x2168, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat6 */ - OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat7 */ - >; - }; - - acx565akm_pins: pinmux_acx565akm_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE4) /* RX51_LCD_RESET_GPIO */ - >; - }; - - dss_sdi_pins: pinmux_dss_sdi_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE1) /* dss_data10.sdi_dat1n */ - OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE1) /* dss_data11.sdi_dat1p */ - OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE1) /* dss_data12.sdi_dat2n */ - OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE1) /* dss_data13.sdi_dat2p */ - - OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE1) /* dss_data22.sdi_clkp */ - OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE1) /* dss_data23.sdi_clkn */ - >; - }; - - wl1251_pins: pinmux_wl1251 { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE4) /* gpio 87 => wl1251 enable */ - OMAP3_CORE1_IOPAD(0x208a, PIN_INPUT | MUX_MODE4) /* gpio 42 => wl1251 irq */ - >; - }; - - ssi_pins: pinmux_ssi { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT_PULLUP | MUX_MODE1) /* ssi1_rdy_tx */ - OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE1) /* ssi1_flag_tx */ - OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE4) /* ssi1_wake_tx (cawake) */ - OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE1) /* ssi1_dat_tx */ - OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT | MUX_MODE1) /* ssi1_dat_rx */ - OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT | MUX_MODE1) /* ssi1_flag_rx */ - OMAP3_CORE1_IOPAD(0x2188, PIN_OUTPUT | MUX_MODE1) /* ssi1_rdy_rx */ - OMAP3_CORE1_IOPAD(0x218a, PIN_OUTPUT | MUX_MODE1) /* ssi1_wake */ - >; - }; - - modem_pins: pinmux_modem { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE4) /* gpio 70 => cmt_apeslpx */ - OMAP3_CORE1_IOPAD(0x20e0, PIN_INPUT | MUX_MODE4) /* gpio 72 => ape_rst_rq */ - OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE4) /* gpio 73 => cmt_rst_rq */ - OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE4) /* gpio 74 => cmt_en */ - OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE4) /* gpio 75 => cmt_rst */ - OMAP3_CORE1_IOPAD(0x218e, PIN_OUTPUT | MUX_MODE4) /* gpio 157 => cmt_bsi */ - >; - }; - - camera_pins: pinmux_camera { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x210c, PIN_OUTPUT | MUX_MODE7) /* cam_hs */ - OMAP3_CORE1_IOPAD(0x210e, PIN_OUTPUT | MUX_MODE7) /* cam_vs */ - OMAP3_CORE1_IOPAD(0x2110, PIN_OUTPUT | MUX_MODE0) /* cam_xclka */ - OMAP3_CORE1_IOPAD(0x211e, PIN_OUTPUT | MUX_MODE7) /* cam_d4 */ - OMAP3_CORE1_IOPAD(0x2122, PIN_INPUT | MUX_MODE0) /* cam_d6 */ - OMAP3_CORE1_IOPAD(0x2124, PIN_INPUT | MUX_MODE0) /* cam_d7 */ - OMAP3_CORE1_IOPAD(0x2126, PIN_INPUT | MUX_MODE0) /* cam_d8 */ - OMAP3_CORE1_IOPAD(0x2128, PIN_INPUT | MUX_MODE0) /* cam_d9 */ - OMAP3_CORE1_IOPAD(0x212a, PIN_OUTPUT | MUX_MODE7) /* cam_d10 */ - OMAP3_CORE1_IOPAD(0x212e, PIN_OUTPUT | MUX_MODE7) /* cam_xclkb */ - OMAP3_CORE1_IOPAD(0x2132, PIN_OUTPUT | MUX_MODE0) /* cam_strobe */ - >; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - - clock-frequency = <2200000>; - - twl: twl@48 { - reg = <0x48>; - interrupts = <7>; /* SYS_NIRQ cascaded to intc */ - interrupt-parent = <&intc>; - }; -}; - -#include "twl4030.dtsi" -#include "twl4030_omap3.dtsi" - -&vaux1 { - regulator-name = "V28"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */ - regulator-always-on; /* due to battery cover sensor */ -}; - -&vaux2 { - regulator-name = "VCSI"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */ -}; - -&vaux3 { - regulator-name = "VMMC2_30"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <3000000>; - regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */ -}; - -&vaux4 { - regulator-name = "VCAM_ANA_28"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */ -}; - -&vmmc1 { - regulator-name = "VMMC1"; - regulator-min-microvolt = <1850000>; - regulator-max-microvolt = <3150000>; - regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */ -}; - -&vmmc2 { - regulator-name = "V28_A"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <3000000>; - regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */ - regulator-always-on; /* due VIO leak to AIC34 VDDs */ -}; - -&vpll1 { - regulator-name = "VPLL"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */ - regulator-always-on; -}; - -&vpll2 { - regulator-name = "VSDI_CSI"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */ - regulator-always-on; -}; - -&vsim { - regulator-name = "VMMC2_IO_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */ -}; - -&vio { - regulator-name = "VIO"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; -}; - -&vintana1 { - regulator-name = "VINTANA1"; - /* fixed to 1500000 */ - regulator-always-on; -}; - -&vintana2 { - regulator-name = "VINTANA2"; - regulator-min-microvolt = <2750000>; - regulator-max-microvolt = <2750000>; - regulator-always-on; -}; - -&vintdig { - regulator-name = "VINTDIG"; - /* fixed to 1500000 */ - regulator-always-on; -}; - -&twl { - twl_audio: audio { - compatible = "ti,twl4030-audio"; - ti,enable-vibra = <1>; - }; - - twl_power: power { - compatible = "ti,twl4030-power-n900", "ti,twl4030-power-idle-osc-off"; - ti,use_poweroff; - }; -}; - -&twl_keypad { - linux,keymap = < MATRIX_KEY(0x00, 0x00, KEY_Q) - MATRIX_KEY(0x00, 0x01, KEY_O) - MATRIX_KEY(0x00, 0x02, KEY_P) - MATRIX_KEY(0x00, 0x03, KEY_COMMA) - MATRIX_KEY(0x00, 0x04, KEY_BACKSPACE) - MATRIX_KEY(0x00, 0x06, KEY_A) - MATRIX_KEY(0x00, 0x07, KEY_S) - - MATRIX_KEY(0x01, 0x00, KEY_W) - MATRIX_KEY(0x01, 0x01, KEY_D) - MATRIX_KEY(0x01, 0x02, KEY_F) - MATRIX_KEY(0x01, 0x03, KEY_G) - MATRIX_KEY(0x01, 0x04, KEY_H) - MATRIX_KEY(0x01, 0x05, KEY_J) - MATRIX_KEY(0x01, 0x06, KEY_K) - MATRIX_KEY(0x01, 0x07, KEY_L) - - MATRIX_KEY(0x02, 0x00, KEY_E) - MATRIX_KEY(0x02, 0x01, KEY_DOT) - MATRIX_KEY(0x02, 0x02, KEY_UP) - MATRIX_KEY(0x02, 0x03, KEY_ENTER) - MATRIX_KEY(0x02, 0x05, KEY_Z) - MATRIX_KEY(0x02, 0x06, KEY_X) - MATRIX_KEY(0x02, 0x07, KEY_C) - MATRIX_KEY(0x02, 0x08, KEY_F9) - - MATRIX_KEY(0x03, 0x00, KEY_R) - MATRIX_KEY(0x03, 0x01, KEY_V) - MATRIX_KEY(0x03, 0x02, KEY_B) - MATRIX_KEY(0x03, 0x03, KEY_N) - MATRIX_KEY(0x03, 0x04, KEY_M) - MATRIX_KEY(0x03, 0x05, KEY_SPACE) - MATRIX_KEY(0x03, 0x06, KEY_SPACE) - MATRIX_KEY(0x03, 0x07, KEY_LEFT) - - MATRIX_KEY(0x04, 0x00, KEY_T) - MATRIX_KEY(0x04, 0x01, KEY_DOWN) - MATRIX_KEY(0x04, 0x02, KEY_RIGHT) - MATRIX_KEY(0x04, 0x04, KEY_LEFTCTRL) - MATRIX_KEY(0x04, 0x05, KEY_RIGHTALT) - MATRIX_KEY(0x04, 0x06, KEY_LEFTSHIFT) - MATRIX_KEY(0x04, 0x08, KEY_F10) - - MATRIX_KEY(0x05, 0x00, KEY_Y) - MATRIX_KEY(0x05, 0x08, KEY_F11) - - MATRIX_KEY(0x06, 0x00, KEY_U) - - MATRIX_KEY(0x07, 0x00, KEY_I) - MATRIX_KEY(0x07, 0x01, KEY_F7) - MATRIX_KEY(0x07, 0x02, KEY_F8) - >; -}; - -&twl_gpio { - ti,pullups = <0x0>; - ti,pulldowns = <0x03ff3f>; /* BIT(0..5) | BIT(8..17) */ -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - - clock-frequency = <100000>; - - tlv320aic3x: tlv320aic3x@18 { - compatible = "ti,tlv320aic3x"; - reg = <0x18>; - reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; /* 60 */ - ai3x-gpio-func = < - 0 /* AIC3X_GPIO1_FUNC_DISABLED */ - 5 /* AIC3X_GPIO2_FUNC_DIGITAL_MIC_INPUT */ - >; - - AVDD-supply = <&vmmc2>; - DRVDD-supply = <&vmmc2>; - IOVDD-supply = <&vio>; - DVDD-supply = <&vio>; - - ai3x-micbias-vg = <1>; - }; - - tlv320aic3x_aux: tlv320aic3x@19 { - compatible = "ti,tlv320aic3x"; - reg = <0x19>; - reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; /* 60 */ - - AVDD-supply = <&vmmc2>; - DRVDD-supply = <&vmmc2>; - IOVDD-supply = <&vio>; - DVDD-supply = <&vio>; - - ai3x-micbias-vg = <2>; - }; - - tsl2563: tsl2563@29 { - compatible = "amstaos,tsl2563"; - reg = <0x29>; - - amstaos,cover-comp-gain = <16>; - }; - - adp1653: led-controller@30 { - compatible = "adi,adp1653"; - reg = <0x30>; - enable-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>; /* 88 */ - - flash { - flash-timeout-us = <500000>; - flash-max-microamp = <320000>; - led-max-microamp = <50000>; - }; - indicator { - led-max-microamp = <17500>; - }; - }; - - lp5523: lp5523@32 { - compatible = "national,lp5523"; - reg = <0x32>; - clock-mode = /bits/ 8 <0>; /* LP55XX_CLOCK_AUTO */ - enable-gpio = <&gpio2 9 GPIO_ACTIVE_HIGH>; /* 41 */ - - chan0 { - chan-name = "lp5523:kb1"; - led-cur = /bits/ 8 <50>; - max-cur = /bits/ 8 <100>; - }; - - chan1 { - chan-name = "lp5523:kb2"; - led-cur = /bits/ 8 <50>; - max-cur = /bits/ 8 <100>; - }; - - chan2 { - chan-name = "lp5523:kb3"; - led-cur = /bits/ 8 <50>; - max-cur = /bits/ 8 <100>; - }; - - chan3 { - chan-name = "lp5523:kb4"; - led-cur = /bits/ 8 <50>; - max-cur = /bits/ 8 <100>; - }; - - chan4 { - chan-name = "lp5523:b"; - led-cur = /bits/ 8 <50>; - max-cur = /bits/ 8 <100>; - }; - - chan5 { - chan-name = "lp5523:g"; - led-cur = /bits/ 8 <50>; - max-cur = /bits/ 8 <100>; - }; - - chan6 { - chan-name = "lp5523:r"; - led-cur = /bits/ 8 <50>; - max-cur = /bits/ 8 <100>; - }; - - chan7 { - chan-name = "lp5523:kb5"; - led-cur = /bits/ 8 <50>; - max-cur = /bits/ 8 <100>; - }; - - chan8 { - chan-name = "lp5523:kb6"; - led-cur = /bits/ 8 <50>; - max-cur = /bits/ 8 <100>; - }; - }; - - bq27200: bq27200@55 { - compatible = "ti,bq27200"; - reg = <0x55>; - power-supplies = <&bq24150a>; - }; - - /* Stereo headphone amplifier */ - tpa6130a2: tpa6130a2@60 { - compatible = "ti,tpa6130a2"; - reg = <0x60>; - - Vdd-supply = <&vmmc2>; - - power-gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>; /* 98 */ - }; - - si4713: si4713@63 { - compatible = "silabs,si4713"; - reg = <0x63>; - - interrupts-extended = <&gpio2 21 IRQ_TYPE_EDGE_FALLING>; /* 53 */ - reset-gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>; /* 163 */ - vio-supply = <&vio>; - vdd-supply = <&vaux1>; - }; - - bq24150a: bq24150a@6b { - compatible = "ti,bq24150a"; - reg = <0x6b>; - - ti,current-limit = <100>; - ti,weak-battery-voltage = <3400>; - ti,battery-regulation-voltage = <4200>; - ti,charge-current = <650>; - ti,termination-current = <100>; - ti,resistor-sense = <68>; - - ti,usb-charger-detection = <&isp1707>; - }; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_pins>; - - clock-frequency = <400000>; - - lis302dl: lis3lv02d@1d { - compatible = "st,lis3lv02d"; - reg = <0x1d>; - - Vdd-supply = <&vaux1>; - Vdd_IO-supply = <&vio>; - - interrupt-parent = <&gpio6>; - interrupts = <21 20>; /* 181 and 180 */ - - /* click flags */ - st,click-single-x; - st,click-single-y; - st,click-single-z; - - /* Limits are 0.5g * value */ - st,click-threshold-x = <8>; - st,click-threshold-y = <8>; - st,click-threshold-z = <10>; - - /* Click must be longer than time limit */ - st,click-time-limit = <9>; - - /* Kind of debounce filter */ - st,click-latency = <50>; - - /* Interrupt line 2 for click detection */ - st,irq2-click; - - st,wakeup-x-hi; - st,wakeup-y-hi; - st,wakeup-threshold = <(800/18)>; /* millig-value / 18 to get HW values */ - - st,wakeup2-z-hi; - st,wakeup2-threshold = <(900/18)>; /* millig-value / 18 to get HW values */ - - st,hipass1-disable; - st,hipass2-disable; - - st,axis-x = <1>; /* LIS3_DEV_X */ - st,axis-y = <(-2)>; /* LIS3_INV_DEV_Y */ - st,axis-z = <(-3)>; /* LIS3_INV_DEV_Z */ - - st,min-limit-x = <(-32)>; - st,min-limit-y = <3>; - st,min-limit-z = <3>; - - st,max-limit-x = <(-3)>; - st,max-limit-y = <32>; - st,max-limit-z = <32>; - }; - - cam1: camera@3e { - compatible = "toshiba,et8ek8"; - reg = <0x3e>; - - vana-supply = <&vaux4>; - - clocks = <&isp 0>; - clock-names = "extclk"; - clock-frequency = <9600000>; - - reset-gpio = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* 102 */ - - lens-focus = <&ad5820>; - - port { - csi_cam1: endpoint { - bus-type = <3>; /* CCP2 */ - strobe = <1>; - clock-inv = <0>; - crc = <1>; - - remote-endpoint = <&csi_isp>; - }; - }; - }; - - /* D/A converter for auto-focus */ - ad5820: dac@c { - compatible = "adi,ad5820"; - reg = <0x0c>; - - VANA-supply = <&vaux4>; - - #io-channel-cells = <0>; - }; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - vmmc-supply = <&vmmc1>; - bus-width = <4>; - /* For debugging, it is often good idea to remove this GPIO. - It means you can remove back cover (to reboot by removing - battery) and still use the MMC card. */ - cd-gpios = <&gpio6 0 GPIO_ACTIVE_LOW>; /* 160 */ -}; - -/* most boards use vaux3, only some old versions use vmmc2 instead */ -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; - vmmc-supply = <&vaux3>; - vqmmc-supply = <&vsim>; - bus-width = <8>; - non-removable; - no-sdio; - no-sd; -}; - -&mmc3 { - status = "disabled"; -}; - -&gpmc { - ranges = <0 0 0x01000000 0x01000000>, /* 16 MB for OneNAND */ - <1 0 0x02000000 0x01000000>; /* 16 MB for smc91c96 */ - pinctrl-names = "default"; - pinctrl-0 = <&gpmc_pins>; - - /* sys_ndmareq1 could be used by the driver, not as gpio65 though */ - onenand@0,0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "ti,omap2-onenand"; - reg = <0 0 0x20000>; /* CS0, offset 0, IO size 128K */ - - gpmc,sync-read; - gpmc,sync-write; - gpmc,burst-length = <16>; - gpmc,burst-read; - gpmc,burst-wrap; - gpmc,burst-write; - gpmc,device-width = <2>; /* GPMC_DEVWIDTH_16BIT */ - gpmc,mux-add-data = <2>; /* GPMC_MUX_AD */ - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <87>; - gpmc,cs-wr-off-ns = <87>; - gpmc,adv-on-ns = <0>; - gpmc,adv-rd-off-ns = <10>; - gpmc,adv-wr-off-ns = <10>; - gpmc,oe-on-ns = <15>; - gpmc,oe-off-ns = <87>; - gpmc,we-on-ns = <0>; - gpmc,we-off-ns = <87>; - gpmc,rd-cycle-ns = <112>; - gpmc,wr-cycle-ns = <112>; - gpmc,access-ns = <81>; - gpmc,page-burst-access-ns = <15>; - gpmc,bus-turnaround-ns = <0>; - gpmc,cycle2cycle-delay-ns = <0>; - gpmc,wait-monitoring-ns = <0>; - gpmc,clk-activation-ns = <5>; - gpmc,wr-data-mux-bus-ns = <30>; - gpmc,wr-access-ns = <81>; - gpmc,sync-clk-ps = <15000>; - - /* - * MTD partition table corresponding to Nokia's - * Maemo 5 (Fremantle) release. - */ - partition@0 { - label = "bootloader"; - reg = <0x00000000 0x00020000>; - read-only; - }; - partition@1 { - label = "config"; - reg = <0x00020000 0x00060000>; - }; - partition@2 { - label = "log"; - reg = <0x00080000 0x00040000>; - }; - partition@3 { - label = "kernel"; - reg = <0x000c0000 0x00200000>; - }; - partition@4 { - label = "initfs"; - reg = <0x002c0000 0x00200000>; - }; - partition@5 { - label = "rootfs"; - reg = <0x004c0000 0x0fb40000>; - }; - }; - - /* Ethernet is on some early development boards and qemu */ - ethernet@gpmc { - compatible = "smsc,lan91c94"; - interrupt-parent = <&gpio2>; - interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; /* gpio54 */ - reg = <1 0 0xf>; /* 16 byte IO range */ - bank-width = <2>; - pinctrl-names = "default"; - pinctrl-0 = <ðernet_pins>; - power-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; /* gpio86 */ - reset-gpios = <&gpio6 4 GPIO_ACTIVE_HIGH>; /* gpio164 */ - gpmc,device-width = <2>; - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <48>; - gpmc,cs-wr-off-ns = <24>; - gpmc,adv-on-ns = <0>; - gpmc,adv-rd-off-ns = <0>; - gpmc,adv-wr-off-ns = <0>; - gpmc,we-on-ns = <12>; - gpmc,we-off-ns = <18>; - gpmc,oe-on-ns = <12>; - gpmc,oe-off-ns = <48>; - gpmc,page-burst-access-ns = <0>; - gpmc,access-ns = <42>; - gpmc,rd-cycle-ns = <180>; - gpmc,wr-cycle-ns = <180>; - gpmc,bus-turnaround-ns = <0>; - gpmc,cycle2cycle-delay-ns = <0>; - gpmc,wait-monitoring-ns = <0>; - gpmc,clk-activation-ns = <0>; - gpmc,wr-access-ns = <0>; - gpmc,wr-data-mux-bus-ns = <12>; - }; -}; - -&mcspi1 { - /* - * For some reason, touchscreen is necessary for screen to work at - * all on real hw. It works well without it on emulator. - * - * Also... order in the device tree actually matters here. - */ - tsc2005@0 { - compatible = "ti,tsc2005"; - spi-max-frequency = <6000000>; - reg = <0>; - - vio-supply = <&vio>; - - reset-gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; /* 104 */ - interrupts-extended = <&gpio4 4 IRQ_TYPE_EDGE_RISING>; /* 100 */ - - touchscreen-fuzz-x = <4>; - touchscreen-fuzz-y = <7>; - touchscreen-fuzz-pressure = <2>; - touchscreen-size-x = <4096>; - touchscreen-size-y = <4096>; - touchscreen-max-pressure = <2048>; - - ti,x-plate-ohms = <280>; - ti,esd-recovery-timeout-ms = <8000>; - }; - - lcd: acx565akm@2 { - compatible = "sony,acx565akm"; - spi-max-frequency = <6000000>; - reg = <2>; - - pinctrl-names = "default"; - pinctrl-0 = <&acx565akm_pins>; - - label = "lcd"; - reset-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>; /* 90 */ - - port { - lcd_in: endpoint { - remote-endpoint = <&sdi_out>; - }; - }; - }; -}; - -&mcspi4 { - pinctrl-names = "default"; - pinctrl-0 = <&mcspi4_pins>; - - wl1251@0 { - pinctrl-names = "default"; - pinctrl-0 = <&wl1251_pins>; - - vio-supply = <&vio>; - - compatible = "ti,wl1251"; - reg = <0>; - spi-max-frequency = <48000000>; - - spi-cpol; - spi-cpha; - - ti,power-gpio = <&gpio3 23 GPIO_ACTIVE_HIGH>; /* 87 */ - - interrupt-parent = <&gpio2>; - interrupts = <10 IRQ_TYPE_NONE>; /* gpio line 42 */ - - clocks = <&vctcxo>; - }; -}; - -&usb_otg_hs { - interface-type = <0>; - usb-phy = <&usb2_phy>; - phys = <&usb2_phy>; - phy-names = "usb2-phy"; - mode = <2>; - power = <50>; -}; - -&uart1 { - status = "disabled"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; - - bcm2048: bluetooth { - compatible = "brcm,bcm2048-nokia", "nokia,h4p-bluetooth"; - reset-gpios = <&gpio3 27 GPIO_ACTIVE_LOW>; /* 91 */ - host-wakeup-gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; /* 101 */ - bluetooth-wakeup-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; /* 37 */ - clocks = <&vctcxo>; - clock-names = "sysclk"; - }; -}; - -&uart3 { - interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>; - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; -}; - -&dss { - status = "ok"; - - pinctrl-names = "default"; - pinctrl-0 = <&dss_sdi_pins>; - - vdds_sdi-supply = <&vaux1>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - - sdi_out: endpoint { - remote-endpoint = <&lcd_in>; - datapairs = <2>; - }; - }; - }; -}; - -&venc { - status = "ok"; - - vdda-supply = <&vdac>; - - port { - venc_out: endpoint { - remote-endpoint = <&tv_connector_in>; - ti,channels = <1>; - }; - }; -}; - -&mcbsp2 { - status = "ok"; -}; - -&ssi_port1 { - pinctrl-names = "default"; - pinctrl-0 = <&ssi_pins>; - - ti,ssi-cawake-gpio = <&gpio5 23 GPIO_ACTIVE_HIGH>; /* 151 */ - - modem: hsi-client { - compatible = "nokia,n900-modem"; - - pinctrl-names = "default"; - pinctrl-0 = <&modem_pins>; - - hsi-channel-ids = <0>, <1>, <2>, <3>; - hsi-channel-names = "mcsaab-control", - "speech-control", - "speech-data", - "mcsaab-data"; - hsi-speed-kbps = <55000>; - hsi-mode = "frame"; - hsi-flow = "synchronized"; - hsi-arb-mode = "round-robin"; - - interrupts-extended = <&gpio3 8 IRQ_TYPE_EDGE_FALLING>; /* 72 */ - - gpios = <&gpio3 6 GPIO_ACTIVE_HIGH>, /* 70 */ - <&gpio3 9 GPIO_ACTIVE_HIGH>, /* 73 */ - <&gpio3 10 GPIO_ACTIVE_HIGH>, /* 74 */ - <&gpio3 11 GPIO_ACTIVE_HIGH>, /* 75 */ - <&gpio5 29 GPIO_ACTIVE_HIGH>; /* 157 */ - gpio-names = "cmt_apeslpx", - "cmt_rst_rq", - "cmt_en", - "cmt_rst", - "cmt_bsi"; - }; -}; - -&ssi_port2 { - status = "disabled"; -}; diff --git a/sys/gnu/dts/arm/omap3-n950-n9.dtsi b/sys/gnu/dts/arm/omap3-n950-n9.dtsi deleted file mode 100644 index 6681d4519e9..00000000000 --- a/sys/gnu/dts/arm/omap3-n950-n9.dtsi +++ /dev/null @@ -1,498 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * omap3-n950-n9.dtsi - Device Tree file for Nokia N950 & N9 (common stuff) - * - * Written by: Aaro Koskinen - */ - -#include "omap36xx.dtsi" - -/ { - cpus { - cpu@0 { - cpu0-supply = <&vcc>; - operating-points = < - /* kHz uV */ - 300000 1012500 - 600000 1200000 - 800000 1325000 - 1000000 1375000 - >; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x40000000>; /* 1 GB */ - }; - - vemmc: fixedregulator0 { - compatible = "regulator-fixed"; - regulator-name = "VEMMC"; - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - gpio = <&gpio5 29 GPIO_ACTIVE_HIGH>; /* gpio line 157 */ - startup-delay-us = <150>; - enable-active-high; - }; - - vwlan_fixed: fixedregulator2 { - compatible = "regulator-fixed"; - regulator-name = "VWLAN"; - gpio = <&gpio2 3 GPIO_ACTIVE_HIGH>; /* gpio 35 */ - enable-active-high; - }; - - leds { - compatible = "gpio-leds"; - - heartbeat { - label = "debug::sleep"; - gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>; /* gpio92 */ - linux,default-trigger = "default-on"; - pinctrl-names = "default"; - pinctrl-0 = <&debug_leds>; - }; - }; - - /* controlled (enabled/disabled) directly by wl1271 */ - vctcxo: vctcxo { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <38400000>; - }; -}; - -&omap3_pmx_core { - accelerator_pins: pinmux_accelerator_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT | MUX_MODE4) /* mcspi2_somi.gpio_180 -> LIS302 INT1 */ - OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT | MUX_MODE4) /* mcspi2_cs0.gpio_181 -> LIS302 INT2 */ - >; - }; - - debug_leds: pinmux_debug_led_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE4) /* dss_data22.gpio_92 */ - >; - }; - - mmc2_pins: pinmux_mmc2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk */ - OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd */ - OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0 */ - OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1 */ - OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2 */ - OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3 */ - >; - }; - - wlan_pins: pinmux_wlan_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x207c, PIN_OUTPUT | MUX_MODE4) /* gpio 35 - wlan enable */ - OMAP3_CORE1_IOPAD(0x208a, PIN_INPUT | MUX_MODE4) /* gpio 42 - wlan irq */ - >; - }; - - ssi_pins: pinmux_ssi_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE1) /* ssi1_dat_tx */ - OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE1) /* ssi1_flag_tx */ - OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT_PULLUP | MUX_MODE1) /* ssi1_rdy_tx */ - OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE4) /* ssi1_wake_tx (cawake) */ - OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT | MUX_MODE1) /* ssi1_dat_rx */ - OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT | MUX_MODE1) /* ssi1_flag_rx */ - OMAP3_CORE1_IOPAD(0x2188, PIN_OUTPUT | MUX_MODE1) /* ssi1_rdy_rx */ - OMAP3_CORE1_IOPAD(0x218a, PIN_OUTPUT | MUX_MODE1) /* ssi1_wake */ - >; - }; - - ssi_pins_idle: pinmux_ssi_pins_idle { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE7) /* ssi1_dat_tx */ - OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE7) /* ssi1_flag_tx */ - OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT_PULLDOWN | MUX_MODE7) /* ssi1_rdy_tx */ - OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE4) /* ssi1_wake_tx (cawake) */ - OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT | MUX_MODE7) /* ssi1_dat_rx */ - OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT | MUX_MODE7) /* ssi1_flag_rx */ - OMAP3_CORE1_IOPAD(0x2188, PIN_OUTPUT | MUX_MODE4) /* ssi1_rdy_rx */ - OMAP3_CORE1_IOPAD(0x218a, PIN_OUTPUT | MUX_MODE7) /* ssi1_wake */ - >; - }; - - modem_pins1: pinmux_modem_core1_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x207a, PIN_INPUT | MUX_MODE4) /* gpio_34 (ape_rst_rq) */ - OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE4) /* gpio_88 (cmt_rst_rq) */ - OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE4) /* gpio_93 (cmt_apeslpx) */ - >; - }; - - uart2_pins: pinmux_uart2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts */ - OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts */ - OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx */ - OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx */ - >; - }; -}; - -&omap3_pmx_core2 { - modem_pins2: pinmux_modem_core2_pins { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* gpio_23 (cmt_en) */ - >; - }; -}; - -&i2c1 { - clock-frequency = <2900000>; - - twl: twl@48 { - reg = <0x48>; - interrupts = <7>; /* SYS_NIRQ cascaded to intc */ - interrupt-parent = <&intc>; - }; -}; - -/include/ "twl4030.dtsi" - -&twl { - compatible = "ti,twl5031"; - - twl_power: power { - compatible = "ti,twl4030-power"; - ti,use_poweroff; - }; -}; - -&twl_gpio { - ti,pullups = <0x000001>; /* BIT(0) */ - ti,pulldowns = <0x008106>; /* BIT(1) | BIT(2) | BIT(8) | BIT(15) */ -}; - -&vdac { - regulator-name = "vdac"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; -}; - -&vpll1 { - regulator-name = "vpll1"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; -}; - -&vpll2 { - regulator-name = "vpll2"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; -}; - -&vaux1 { - regulator-name = "vaux1"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; -}; - -/* CSI-2 receiver */ -&vaux2 { - regulator-name = "vaux2"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; -}; - -/* Cameras */ -&vaux3 { - regulator-name = "vaux3"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; -}; - -&vaux4 { - regulator-name = "vaux4"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; -}; - -&vmmc1 { - regulator-name = "vmmc1"; - regulator-min-microvolt = <1850000>; - regulator-max-microvolt = <3150000>; -}; - -&vmmc2 { - regulator-name = "vmmc2"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; -}; - -&vintana1 { - regulator-name = "vintana1"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; -}; - -&vintana2 { - regulator-name = "vintana2"; - regulator-min-microvolt = <2750000>; - regulator-max-microvolt = <2750000>; -}; - -&vintdig { - regulator-name = "vintdig"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; -}; - -&vsim { - regulator-name = "vsim"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; -}; - -&vio { - regulator-name = "vio"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; -}; - -&i2c2 { - clock-frequency = <400000>; - - as3645a@30 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x30>; - compatible = "ams,as3645a"; - as3645a_flash: flash@0 { - reg = <0x0>; - flash-timeout-us = <150000>; - flash-max-microamp = <320000>; - led-max-microamp = <60000>; - ams,input-max-microamp = <1750000>; - }; - as3645a_indicator: indicator@1 { - reg = <0x1>; - led-max-microamp = <10000>; - }; - }; -}; - -&i2c3 { - clock-frequency = <400000>; - - lis302: lis302@1d { - compatible = "st,lis3lv02d"; - reg = <0x1d>; - - Vdd-supply = <&vaux1>; - Vdd_IO-supply = <&vio>; - - pinctrl-names = "default"; - pinctrl-0 = <&accelerator_pins>; - - interrupts-extended = <&gpio6 20 IRQ_TYPE_EDGE_FALLING>, <&gpio6 21 IRQ_TYPE_EDGE_FALLING>; /* 180, 181 */ - - /* click flags */ - st,click-single-x; - st,click-single-y; - st,click-single-z; - - /* Limits are 0.5g * value */ - st,click-threshold-x = <8>; - st,click-threshold-y = <8>; - st,click-threshold-z = <10>; - - /* Click must be longer than time limit */ - st,click-time-limit = <9>; - - /* Kind of debounce filter */ - st,click-latency = <50>; - - st,wakeup-x-hi; - st,wakeup-y-hi; - st,wakeup-threshold = <(800/18)>; /* millig-value / 18 to get HW values */ - - st,wakeup2-z-hi; - st,wakeup2-threshold = <(1000/18)>; /* millig-value / 18 to get HW values */ - - st,highpass-cutoff-hz = <2>; - - /* Interrupt line 1 for thresholds */ - st,irq1-ff-wu-1; - st,irq1-ff-wu-2; - /* Interrupt line 2 for click detection */ - st,irq2-click; - - st,wu-duration-1 = <8>; - st,wu-duration-2 = <8>; - }; -}; - -&mmc1 { - status = "disabled"; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; - vmmc-supply = <&vemmc>; - bus-width = <4>; - ti,non-removable; -}; - -&mmc3 { - status = "disabled"; -}; - -&usb_otg_hs { - interface-type = <0>; - usb-phy = <&usb2_phy>; - phys = <&usb2_phy>; - phy-names = "usb2-phy"; - mode = <3>; - power = <50>; -}; - -&gpmc { - ranges = <0 0 0x04000000 0x1000000>; /* CS0: 16MB for OneNAND */ - - onenand@0,0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "ti,omap2-onenand"; - reg = <0 0 0x20000>; /* CS0, offset 0, IO size 128K */ - - /* - * These timings are based on CONFIG_OMAP_GPMC_DEBUG=y reported - * bootloader set values when booted with v4.19 using both N950 - * and N9 devices (OneNAND Manufacturer: Samsung): - * - * gpmc cs0 before gpmc_cs_program_settings: - * cs0 GPMC_CS_CONFIG1: 0xfd001202 - * cs0 GPMC_CS_CONFIG2: 0x00181800 - * cs0 GPMC_CS_CONFIG3: 0x00030300 - * cs0 GPMC_CS_CONFIG4: 0x18001804 - * cs0 GPMC_CS_CONFIG5: 0x03171d1d - * cs0 GPMC_CS_CONFIG6: 0x97080000 - */ - gpmc,sync-read; - gpmc,sync-write; - gpmc,burst-length = <16>; - gpmc,burst-read; - gpmc,burst-wrap; - gpmc,burst-write; - gpmc,device-width = <2>; - gpmc,mux-add-data = <2>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <122>; - gpmc,cs-wr-off-ns = <122>; - gpmc,adv-on-ns = <0>; - gpmc,adv-rd-off-ns = <15>; - gpmc,adv-wr-off-ns = <15>; - gpmc,oe-on-ns = <20>; - gpmc,oe-off-ns = <122>; - gpmc,we-on-ns = <0>; - gpmc,we-off-ns = <122>; - gpmc,rd-cycle-ns = <148>; - gpmc,wr-cycle-ns = <148>; - gpmc,access-ns = <117>; - gpmc,page-burst-access-ns = <15>; - gpmc,bus-turnaround-ns = <0>; - gpmc,cycle2cycle-delay-ns = <0>; - gpmc,wait-monitoring-ns = <0>; - gpmc,clk-activation-ns = <10>; - gpmc,wr-data-mux-bus-ns = <40>; - gpmc,wr-access-ns = <117>; - - gpmc,sync-clk-ps = <15000>; /* TBC; Where this value came? */ - - /* - * MTD partition table corresponding to Nokia's MeeGo 1.2 - * Harmattan release. - */ - partition@0 { - label = "bootloader"; - reg = <0x00000000 0x00100000>; - }; - partition@1 { - label = "config"; - reg = <0x00100000 0x002c0000>; - }; - partition@2 { - label = "kernel"; - reg = <0x003c0000 0x01000000>; - }; - partition@3 { - label = "log"; - reg = <0x013c0000 0x00200000>; - }; - partition@4 { - label = "var"; - reg = <0x015c0000 0x1ca40000>; - }; - partition@5 { - label = "moslo"; - reg = <0x1e000000 0x02000000>; - }; - partition@6 { - label = "omap2-onenand"; - reg = <0x00000000 0x20000000>; - }; - }; -}; - -&ssi_port1 { - pinctrl-names = "default", "idle"; - pinctrl-0 = <&ssi_pins>; - pinctrl-1 = <&ssi_pins_idle>; - - ti,ssi-cawake-gpio = <&gpio5 23 GPIO_ACTIVE_HIGH>; /* 151 */ - - modem: hsi-client { - pinctrl-names = "default"; - pinctrl-0 = <&modem_pins1 &modem_pins2>; - - hsi-channel-ids = <0>, <1>, <2>, <3>; - hsi-channel-names = "mcsaab-control", - "speech-control", - "speech-data", - "mcsaab-data"; - hsi-speed-kbps = <96000>; - hsi-mode = "frame"; - hsi-flow = "synchronized"; - hsi-arb-mode = "round-robin"; - - interrupts-extended = <&gpio2 2 IRQ_TYPE_EDGE_RISING>; /* gpio 34 */ - - gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>, /* gpio 93 */ - <&gpio3 24 GPIO_ACTIVE_HIGH>, /* gpio 88 */ - <&gpio1 23 GPIO_ACTIVE_HIGH>; /* gpio 23 */ - gpio-names = "cmt_apeslpx", - "cmt_rst_rq", - "cmt_en"; - }; -}; - -&ssi_port2 { - status = "disabled"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; - - bluetooth { - compatible = "ti,wl1271-bluetooth-nokia", "nokia,h4p-bluetooth"; - - reset-gpios = <&gpio1 26 GPIO_ACTIVE_LOW>; /* 26 */ - host-wakeup-gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; /* 101 */ - bluetooth-wakeup-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; /* 37 */ - - clocks = <&vctcxo>; - clock-names = "sysclk"; - }; -}; diff --git a/sys/gnu/dts/arm/omap3-n950.dts b/sys/gnu/dts/arm/omap3-n950.dts deleted file mode 100644 index 9886bf8b90a..00000000000 --- a/sys/gnu/dts/arm/omap3-n950.dts +++ /dev/null @@ -1,273 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * omap3-n950.dts - Device Tree file for Nokia N950 - * - * Written by: Aaro Koskinen - */ - -/dts-v1/; - -#include "omap3-n950-n9.dtsi" -#include - -/ { - model = "Nokia N950"; - compatible = "nokia,omap3-n950", "ti,omap36xx", "ti,omap3"; - - keys { - compatible = "gpio-keys"; - - keypad_slide { - label = "Keypad Slide"; - gpios = <&gpio4 13 GPIO_ACTIVE_LOW>; /* 109 */ - linux,input-type = ; - linux,code = ; - wakeup-source; - pinctrl-names = "default"; - pinctrl-0 = <&keypad_slide_pins>; - }; - }; -}; - -&omap3_pmx_core { - keypad_slide_pins: pinmux_debug_led_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x212a, PIN_INPUT | MUX_MODE4) /* cam_d10.gpio_109 */ - >; - }; -}; - -&omap3_pmx_core { - spi4_pins: pinmux_spi4_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x218c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mcspi4_clk */ - OMAP3_CORE1_IOPAD(0x2190, PIN_OUTPUT | MUX_MODE1) /* mcspi4_simo */ - OMAP3_CORE1_IOPAD(0x2192, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mcspi4_somi */ - OMAP3_CORE1_IOPAD(0x2196, PIN_OUTPUT | MUX_MODE1) /* mcspi4_cs0 */ - >; - }; -}; - -&omap3_pmx_core { - dsi_pins: pinmux_dsi_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE1) /* dsi_dx0 - data0+ */ - OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE1) /* dsi_dy0 - data0- */ - OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE1) /* dsi_dx1 - clk+ */ - OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE1) /* dsi_dy1 - clk- */ - OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE1) /* dsi_dx2 - data1+ */ - OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE1) /* dsi_dy2 - data1- */ - >; - }; - - display_pins: pinmux_display_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20ca, PIN_INPUT | MUX_MODE4) /* gpio 62 - display te */ - OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE4) /* gpio 87 - display reset */ - >; - }; -}; - -&i2c2 { - smia_1: camera@10 { - compatible = "nokia,smia"; - reg = <0x10>; - /* No reset gpio */ - vana-supply = <&vaux3>; - clocks = <&isp 0>; - clock-frequency = <9600000>; - nokia,nvm-size = <(16 * 64)>; - flash-leds = <&as3645a_flash &as3645a_indicator>; - port { - smia_1_1: endpoint { - link-frequencies = /bits/ 64 <210000000 333600000 398400000>; - clock-lanes = <0>; - data-lanes = <1 2>; - remote-endpoint = <&csi2a_ep>; - }; - }; - }; -}; - -&isp { - vdd-csiphy1-supply = <&vaux2>; - vdd-csiphy2-supply = <&vaux2>; - ports { - port@2 { - reg = <2>; - csi2a_ep: endpoint { - remote-endpoint = <&smia_1_1>; - clock-lanes = <2>; - data-lanes = <3 1>; - crc = <1>; - lane-polarities = <1 1 1>; - }; - }; - }; -}; - -&mcspi4 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&spi4_pins>; - - wlcore: wlcore@0 { - compatible = "ti,wl1271"; - pinctrl-names = "default"; - pinctrl-0 = <&wlan_pins>; - reg = <0>; - spi-max-frequency = <48000000>; - clock-xtal; - ref-clock-frequency = <38400000>; - interrupts-extended = <&gpio2 10 IRQ_TYPE_LEVEL_HIGH>; /* gpio 42 */ - vwlan-supply = <&vwlan_fixed>; - }; -}; - -&modem { - compatible = "nokia,n950-modem"; -}; - -&twl { - twl_audio: audio { - compatible = "ti,twl4030-audio"; - ti,enable-vibra = <1>; - }; -}; - -&twl_keypad { - linux,keymap = < MATRIX_KEY(0x00, 0x00, KEY_BACKSLASH) - MATRIX_KEY(0x01, 0x00, KEY_LEFTSHIFT) - MATRIX_KEY(0x02, 0x00, KEY_COMPOSE) - MATRIX_KEY(0x03, 0x00, KEY_LEFTMETA) - MATRIX_KEY(0x04, 0x00, KEY_RIGHTCTRL) - MATRIX_KEY(0x05, 0x00, KEY_BACKSPACE) - MATRIX_KEY(0x06, 0x00, KEY_VOLUMEDOWN) - MATRIX_KEY(0x07, 0x00, KEY_VOLUMEUP) - - MATRIX_KEY(0x03, 0x01, KEY_Z) - MATRIX_KEY(0x04, 0x01, KEY_A) - MATRIX_KEY(0x05, 0x01, KEY_Q) - MATRIX_KEY(0x06, 0x01, KEY_W) - MATRIX_KEY(0x07, 0x01, KEY_E) - - MATRIX_KEY(0x03, 0x02, KEY_X) - MATRIX_KEY(0x04, 0x02, KEY_S) - MATRIX_KEY(0x05, 0x02, KEY_D) - MATRIX_KEY(0x06, 0x02, KEY_C) - MATRIX_KEY(0x07, 0x02, KEY_V) - - MATRIX_KEY(0x03, 0x03, KEY_O) - MATRIX_KEY(0x04, 0x03, KEY_I) - MATRIX_KEY(0x05, 0x03, KEY_U) - MATRIX_KEY(0x06, 0x03, KEY_L) - MATRIX_KEY(0x07, 0x03, KEY_APOSTROPHE) - - MATRIX_KEY(0x03, 0x04, KEY_Y) - MATRIX_KEY(0x04, 0x04, KEY_K) - MATRIX_KEY(0x05, 0x04, KEY_J) - MATRIX_KEY(0x06, 0x04, KEY_H) - MATRIX_KEY(0x07, 0x04, KEY_G) - - MATRIX_KEY(0x03, 0x05, KEY_B) - MATRIX_KEY(0x04, 0x05, KEY_COMMA) - MATRIX_KEY(0x05, 0x05, KEY_M) - MATRIX_KEY(0x06, 0x05, KEY_N) - MATRIX_KEY(0x07, 0x05, KEY_DOT) - - MATRIX_KEY(0x00, 0x06, KEY_SPACE) - MATRIX_KEY(0x03, 0x06, KEY_T) - MATRIX_KEY(0x04, 0x06, KEY_UP) - MATRIX_KEY(0x05, 0x06, KEY_LEFT) - MATRIX_KEY(0x06, 0x06, KEY_RIGHT) - MATRIX_KEY(0x07, 0x06, KEY_DOWN) - - MATRIX_KEY(0x03, 0x07, KEY_P) - MATRIX_KEY(0x04, 0x07, KEY_ENTER) - MATRIX_KEY(0x05, 0x07, KEY_SLASH) - MATRIX_KEY(0x06, 0x07, KEY_F) - MATRIX_KEY(0x07, 0x07, KEY_R) - >; -}; - -&lis302 { - st,axis-x = <(-2)>; /* LIS3_INV_DEV_Y */ - st,axis-y = <(-1)>; /* LIS3_INV_DEV_X */ - st,axis-z = <(-3)>; /* LIS3_INV_DEV_Z */ - - st,min-limit-x = <(-32)>; - st,min-limit-y = <3>; - st,min-limit-z = <3>; - - st,max-limit-x = <(-3)>; - st,max-limit-y = <32>; - st,max-limit-z = <32>; -}; - -&dss { - status = "ok"; - - vdda_video-supply = <&vdac>; -}; - -&dsi { - status = "ok"; - - pinctrl-names = "default"; - pinctrl-0 = <&dsi_pins>; - - vdd-supply = <&vpll2>; - - port { - dsi_out_ep: endpoint { - remote-endpoint = <&lcd0_in>; - lanes = <2 3 0 1 4 5>; - }; - }; - - lcd0: display { - compatible = "nokia,himalaya", "panel-dsi-cm"; - label = "lcd0"; - - pinctrl-names = "default"; - pinctrl-0 = <&display_pins>; - - vpnl-supply = <&vmmc2>; - vddi-supply = <&vio>; - - reset-gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>; /* 87 */ - te-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>; /* 62 */ - - width-mm = <49>; /* 48.960 mm */ - height-mm = <88>; /* 88.128 mm */ - - /* TODO: - * - panel is upside-down - * - top + bottom 5px are not visible - */ - panel-timing { - clock-frequency = <0>; /* Calculated by dsi */ - - hback-porch = <2>; - hactive = <480>; - hfront-porch = <0>; - hsync-len = <2>; - - vback-porch = <1>; - vactive = <864>; - vfront-porch = <0>; - vsync-len = <1>; - - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - - port { - lcd0_in: endpoint { - remote-endpoint = <&dsi_out_ep>; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/omap3-overo-alto35-common.dtsi b/sys/gnu/dts/arm/omap3-overo-alto35-common.dtsi deleted file mode 100644 index bb932913c9e..00000000000 --- a/sys/gnu/dts/arm/omap3-overo-alto35-common.dtsi +++ /dev/null @@ -1,75 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group - */ - -/* - * Alto35 expansion board is manufactured by Gumstix Inc. - */ - -#include "omap3-overo-common-peripherals.dtsi" -#include "omap3-overo-common-lcd35.dtsi" - -#include - -/ { - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins>; - gpio148 { - label = "overo:red:gpio148"; - gpios = <&gpio5 20 GPIO_ACTIVE_HIGH>; /* gpio 148 */ - }; - gpio150 { - label = "overo:yellow:gpio150"; - gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>; /* gpio 150 */ - }; - gpio151 { - label = "overo:blue:gpio151"; - gpios = <&gpio5 23 GPIO_ACTIVE_HIGH>; /* gpio 151 */ - }; - gpio170 { - label = "overo:green:gpio170"; - gpios = <&gpio6 10 GPIO_ACTIVE_HIGH>; /* gpio 170 */ - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&button_pins>; - button0 { - label = "button0"; - linux,code = ; - gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; /* gpio_10 */ - wakeup-source; - }; - }; -}; - -&omap3_pmx_core { - led_pins: pinmux_led_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE4) /* uart1_tx.gpio_148 */ - OMAP3_CORE1_IOPAD(0x2180, PIN_OUTPUT | MUX_MODE4) /* uart1_cts.gpio_150 */ - OMAP3_CORE1_IOPAD(0x2182, PIN_OUTPUT | MUX_MODE4) /* uart1_rx.gpio_151 */ - OMAP3_CORE1_IOPAD(0x21c6, PIN_OUTPUT | MUX_MODE4) /* hdq_sio.gpio_170 */ - >; - }; -}; - -&omap3_pmx_wkup { - button_pins: pinmux_button_pins { - pinctrl-single,pins = < - OMAP3_WKUP_IOPAD(0x2a18, PIN_INPUT | MUX_MODE4) /* sys_clkout1.gpio_10 */ - >; - }; -}; - -&usbhshost { - status = "disabled"; -}; - diff --git a/sys/gnu/dts/arm/omap3-overo-alto35.dts b/sys/gnu/dts/arm/omap3-overo-alto35.dts deleted file mode 100644 index 37c64dd5f67..00000000000 --- a/sys/gnu/dts/arm/omap3-overo-alto35.dts +++ /dev/null @@ -1,19 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group - */ - -/* - * Alto35 expansion board is manufactured by Gumstix Inc. - */ - -/dts-v1/; - -#include "omap3-overo.dtsi" -#include "omap3-overo-alto35-common.dtsi" - -/ { - model = "OMAP35xx Gumstix Overo on Alto35"; - compatible = "gumstix,omap3-overo-alto35", "gumstix,omap3-overo", "ti,omap3430", "ti,omap3"; -}; - diff --git a/sys/gnu/dts/arm/omap3-overo-base.dtsi b/sys/gnu/dts/arm/omap3-overo-base.dtsi deleted file mode 100644 index 971d3e25051..00000000000 --- a/sys/gnu/dts/arm/omap3-overo-base.dtsi +++ /dev/null @@ -1,274 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Florian Vaussard, EPFL Mobots group - */ - -/* - * The Gumstix Overo must be combined with an expansion board. - */ - -/ { - - memory@0 { - device_type = "memory"; - reg = <0 0>; - }; - - pwmleds { - compatible = "pwm-leds"; - - overo { - label = "overo:blue:COM"; - pwms = <&twl_pwmled 1 7812500>; - max-brightness = <127>; - linux,default-trigger = "mmc0"; - }; - }; - - sound { - compatible = "ti,omap-twl4030"; - ti,model = "overo"; - - ti,mcbsp = <&mcbsp2>; - }; - - /* HS USB Port 2 Power */ - hsusb2_power: hsusb2_power_reg { - compatible = "regulator-fixed"; - regulator-name = "hsusb2_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio6 8 GPIO_ACTIVE_HIGH>; /* gpio_168: vbus enable */ - startup-delay-us = <70000>; - enable-active-high; - }; - - /* HS USB Host PHY on PORT 2 */ - hsusb2_phy: hsusb2_phy { - compatible = "usb-nop-xceiv"; - reset-gpios = <&gpio6 23 GPIO_ACTIVE_LOW>; /* gpio_183 */ - vcc-supply = <&hsusb2_power>; - #phy-cells = <0>; - }; - - /* Regulator to trigger the nPoweron signal of the Wifi module */ - w3cbw003c_npoweron: regulator-w3cbw003c-npoweron { - compatible = "regulator-fixed"; - regulator-name = "regulator-w3cbw003c-npoweron"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 22 GPIO_ACTIVE_HIGH>; /* gpio_54: nPoweron */ - enable-active-high; - }; - - /* Regulator to trigger the nReset signal of the Wifi module */ - w3cbw003c_wifi_nreset: regulator-w3cbw003c-wifi-nreset { - pinctrl-names = "default"; - pinctrl-0 = <&w3cbw003c_pins &w3cbw003c_2_pins>; - compatible = "regulator-fixed"; - regulator-name = "regulator-w3cbw003c-wifi-nreset"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio1 16 GPIO_ACTIVE_HIGH>; /* gpio_16: WiFi nReset */ - startup-delay-us = <10000>; - }; -}; - -&omap3_pmx_core { - pinctrl-names = "default"; - pinctrl-0 = < - &hsusb2_pins - >; - - uart2_pins: pinmux_uart2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x216c, PIN_INPUT | MUX_MODE1) /* mcbsp3_dx.uart2_cts */ - OMAP3_CORE1_IOPAD(0x216e, PIN_OUTPUT | MUX_MODE1) /* mcbsp3_dr.uart2_rts */ - OMAP3_CORE1_IOPAD(0x2170, PIN_OUTPUT | MUX_MODE1) /* mcbsp3_clk.uart2_tx */ - OMAP3_CORE1_IOPAD(0x2172, PIN_INPUT | MUX_MODE1) /* mcbsp3_fsx.uart2_rx */ - >; - }; - - i2c1_pins: pinmux_i2c1_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */ - OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */ - >; - }; - - mmc1_pins: pinmux_mmc1_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ - OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ - OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ - OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ - OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ - OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ - >; - }; - - mmc2_pins: pinmux_mmc2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ - OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ - OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ - OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ - OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ - OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ - >; - }; - - /* WiFi/BT combo */ - w3cbw003c_pins: pinmux_w3cbw003c_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20b4, PIN_OUTPUT | MUX_MODE4) /* gpmc_ncs3.gpio_54 */ - OMAP3_CORE1_IOPAD(0x219c, PIN_OUTPUT | MUX_MODE4) /* uart3_rts_sd.gpio_164 */ - >; - }; - - hsusb2_pins: pinmux_hsusb2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */ - OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */ - OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */ - OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */ - OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */ - OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */ - OMAP3_CORE1_IOPAD(0x21be, PIN_OUTPUT | MUX_MODE4) /* i2c2_scl.gpio_168 */ - OMAP3_CORE1_IOPAD(0x21c0, PIN_OUTPUT | MUX_MODE4) /* i2c2_sda.gpio_183 */ - >; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - clock-frequency = <2600000>; - - twl: twl@48 { - reg = <0x48>; - interrupts = <7>; /* SYS_NIRQ cascaded to intc */ - interrupt-parent = <&intc>; - - twl_audio: audio { - compatible = "ti,twl4030-audio"; - codec { - }; - }; - }; -}; - -#include "twl4030.dtsi" -#include "twl4030_omap3.dtsi" - -/* i2c2 pins are used for gpio */ -&i2c2 { - status = "disabled"; -}; - -/* on board microSD slot */ -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - vmmc-supply = <&vmmc1>; - bus-width = <4>; -}; - -/* optional on board WiFi */ -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; - vmmc-supply = <&w3cbw003c_npoweron>; - vqmmc-supply = <&w3cbw003c_wifi_nreset>; - bus-width = <4>; - cap-sdio-irq; - non-removable; -}; - -&twl_gpio { - ti,use-leds; -}; - -&usb_otg_hs { - interface-type = <0>; - usb-phy = <&usb2_phy>; - phys = <&usb2_phy>; - phy-names = "usb2-phy"; - mode = <3>; - power = <50>; -}; - -&usbhshost { - port2-mode = "ehci-phy"; -}; - -&usbhsehci { - phys = <0 &hsusb2_phy>; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; -}; - -&mcbsp2 { - status = "okay"; -}; - -&gpmc { - ranges = <0 0 0x30000000 0x1000000>, /* CS0 */ - <4 0 0x2b000000 0x1000000>, /* CS4 */ - <5 0 0x2c000000 0x1000000>; /* CS5 */ - - nand@0,0 { - compatible = "ti,omap2-nand"; - linux,mtd-name= "micron,mt29c4g96maz"; - reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ - <1 IRQ_TYPE_NONE>; /* termcount */ - nand-bus-width = <16>; - gpmc,device-width = <2>; - ti,nand-ecc-opt = "bch8"; - - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <44>; - gpmc,cs-wr-off-ns = <44>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <34>; - gpmc,adv-wr-off-ns = <44>; - gpmc,we-off-ns = <40>; - gpmc,oe-off-ns = <54>; - gpmc,access-ns = <64>; - gpmc,rd-cycle-ns = <82>; - gpmc,wr-cycle-ns = <82>; - gpmc,wr-access-ns = <40>; - gpmc,wr-data-mux-bus-ns = <0>; - - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "SPL"; - reg = <0 0x80000>; /* 512KiB */ - }; - partition@80000 { - label = "U-Boot"; - reg = <0x80000 0x1C0000>; /* 1792KiB */ - }; - partition@1c0000 { - label = "Environment"; - reg = <0x240000 0x40000>; /* 256KiB */ - }; - partition@280000 { - label = "Kernel"; - reg = <0x280000 0x800000>; /* 8192KiB */ - }; - partition@780000 { - label = "Filesystem"; - reg = <0xA80000 0>; - /* HACK: MTDPART_SIZ_FULL=0 so fill to end */ - }; - }; -}; diff --git a/sys/gnu/dts/arm/omap3-overo-chestnut43-common.dtsi b/sys/gnu/dts/arm/omap3-overo-chestnut43-common.dtsi deleted file mode 100644 index 2d2c61d7aa8..00000000000 --- a/sys/gnu/dts/arm/omap3-overo-chestnut43-common.dtsi +++ /dev/null @@ -1,65 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group - */ - -/* - * Chestnut43 expansion board is manufactured by Gumstix Inc. - */ - -#include "omap3-overo-common-peripherals.dtsi" -#include "omap3-overo-common-lcd43.dtsi" - -#include - -/ { - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins>; - heartbeat { - label = "overo:red:gpio21"; - gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; /* gpio_21 */ - linux,default-trigger = "heartbeat"; - }; - gpio22 { - label = "overo:blue:gpio22"; - gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; /* gpio_22 */ - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&button_pins>; - #address-cells = <1>; - #size-cells = <0>; - button0 { - label = "button0"; - linux,code = ; - gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; /* gpio_23 */ - wakeup-source; - }; - button1 { - label = "button1"; - linux,code = ; - gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; /* gpio_14 */ - wakeup-source; - }; - }; -}; - -#include "omap-gpmc-smsc9221.dtsi" - -&gpmc { - ethernet@gpmc { - reg = <5 0 0xff>; - interrupt-parent = <&gpio6>; - interrupts = <16 IRQ_TYPE_LEVEL_LOW>; /* GPIO 176 */ - }; -}; - -&lis33de { - status = "disabled"; -}; - diff --git a/sys/gnu/dts/arm/omap3-overo-chestnut43.dts b/sys/gnu/dts/arm/omap3-overo-chestnut43.dts deleted file mode 100644 index d147d704b89..00000000000 --- a/sys/gnu/dts/arm/omap3-overo-chestnut43.dts +++ /dev/null @@ -1,35 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group - */ - -/* - * Chestnut43 expansion board is manufactured by Gumstix Inc. - */ - -/dts-v1/; - -#include "omap3-overo.dtsi" -#include "omap3-overo-chestnut43-common.dtsi" - -/ { - model = "OMAP35xx Gumstix Overo on Chestnut43"; - compatible = "gumstix,omap3-overo-chestnut43", "gumstix,omap3-overo", "ti,omap3430", "ti,omap3"; -}; - -&omap3_pmx_core2 { - led_pins: pinmux_led_pins { - pinctrl-single,pins = < - OMAP3430_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) /* etk_d7.gpio_21 */ - OMAP3430_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* etk_d8.gpio_22 */ - >; - }; - - button_pins: pinmux_button_pins { - pinctrl-single,pins = < - OMAP3430_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE4) /* etk_d9.gpio_23 */ - OMAP3430_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE4) /* etk_d0.gpio_14 */ - >; - }; -}; - diff --git a/sys/gnu/dts/arm/omap3-overo-common-dvi.dtsi b/sys/gnu/dts/arm/omap3-overo-common-dvi.dtsi deleted file mode 100644 index c9e62e414ab..00000000000 --- a/sys/gnu/dts/arm/omap3-overo-common-dvi.dtsi +++ /dev/null @@ -1,108 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group - */ - -/* - * DVI output for some Gumstix Overo boards (Tobi and Summit) - */ - -&omap3_pmx_core { - dss_dpi_pins: pinmux_dss_dpi_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ - OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ - OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ - OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ - OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ - OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ - OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ - OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ - OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ - OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ - OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ - OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ - OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ - OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ - OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ - OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ - OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ - OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ - OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ - OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ - OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ - OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ - OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */ - OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */ - OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */ - OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */ - OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ - OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ - >; - }; -}; - -/* Needed to power the DPI pins */ -&vpll2 { - regulator-always-on; -}; - -&dss { - status = "ok"; - - pinctrl-names = "default"; - pinctrl-0 = <&dss_dpi_pins>; - - port { - dpi_out: endpoint { - remote-endpoint = <&tfp410_in>; - data-lines = <24>; - }; - }; -}; - -/ { - aliases { - display0 = &dvi0; - }; - - tfp410: encoder { - compatible = "ti,tfp410"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - tfp410_in: endpoint { - remote-endpoint = <&dpi_out>; - }; - }; - - port@1 { - reg = <1>; - - tfp410_out: endpoint { - remote-endpoint = <&dvi_connector_in>; - }; - }; - }; - }; - - dvi0: connector { - compatible = "dvi-connector"; - label = "dvi"; - - digital; - ddc-i2c-bus = <&i2c3>; - - port { - dvi_connector_in: endpoint { - remote-endpoint = <&tfp410_out>; - }; - }; - }; -}; - diff --git a/sys/gnu/dts/arm/omap3-overo-common-lcd35.dtsi b/sys/gnu/dts/arm/omap3-overo-common-lcd35.dtsi deleted file mode 100644 index 185ce53de0e..00000000000 --- a/sys/gnu/dts/arm/omap3-overo-common-lcd35.dtsi +++ /dev/null @@ -1,163 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group - */ - -/* - * 4.3'' LCD panel output for some Gumstix Overo boards (Gallop43, Chestnut43) - */ - -&omap3_pmx_core { - dss_dpi_pins: pinmux_dss_dpi_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ - OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ - OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ - OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ - OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ - OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ - OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ - OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ - OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ - OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ - OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ - OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ - OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ - OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ - OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ - OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ - OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ - OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ - OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ - OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ - OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ - OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ - OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */ - OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */ - OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */ - OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */ - OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ - OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ - >; - }; - - lb035_pins: pinmux_lb035_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2174, PIN_OUTPUT | MUX_MODE4) /* uart2_cts.gpio_144 */ - >; - }; - - backlight_pins: pinmux_backlight_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE4) /* uart2_rts.gpio_145 */ - >; - }; - - mcspi1_pins: pinmux_mcspi1_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */ - OMAP3_CORE1_IOPAD(0x21ca, PIN_INPUT | MUX_MODE0) /* mcspi1_simo.mcspi1_simo */ - OMAP3_CORE1_IOPAD(0x21cc, PIN_INPUT | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */ - OMAP3_CORE1_IOPAD(0x21ce, PIN_INPUT | MUX_MODE0) /* mcspi1_cs0.mcspi1_cs0 */ - OMAP3_CORE1_IOPAD(0x21d0, PIN_INPUT | MUX_MODE0) /* mcspi1_cs1.mcspi1_cs1 */ - >; - }; - - ads7846_pins: pinmux_ads7846_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2138, PIN_INPUT_PULLDOWN | MUX_MODE4) /* csi2_dx1.gpio_114 */ - >; - }; -}; - -/* Needed to power the DPI pins */ -&vpll2 { - regulator-always-on; -}; - -&dss { - status = "ok"; - - pinctrl-names = "default"; - pinctrl-0 = <&dss_dpi_pins>; - - port { - dpi_out: endpoint { - remote-endpoint = <&lcd_in>; - data-lines = <24>; - }; - }; -}; - -/ { - aliases { - display0 = &lcd0; - }; - - ads7846reg: ads7846-reg { - compatible = "regulator-fixed"; - regulator-name = "ads7846-reg"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - backlight { - compatible = "gpio-backlight"; - - pinctrl-names = "default"; - pinctrl-0 = <&backlight_pins>; - gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>; /* gpio_145 */ - - default-on; - }; -}; - -&mcspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&mcspi1_pins>; - - lcd0: display@1 { - compatible = "lgphilips,lb035q02"; - label = "lcd35"; - - reg = <1>; /* CS1 */ - spi-max-frequency = <500000>; - spi-cpol; - spi-cpha; - - pinctrl-names = "default"; - pinctrl-0 = <&lb035_pins>; - enable-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>; /* gpio_144 */ - - port { - lcd_in: endpoint { - remote-endpoint = <&dpi_out>; - }; - }; - }; - - /* touch controller */ - ads7846@0 { - pinctrl-names = "default"; - pinctrl-0 = <&ads7846_pins>; - - compatible = "ti,ads7846"; - vcc-supply = <&ads7846reg>; - - reg = <0>; /* CS0 */ - spi-max-frequency = <1500000>; - - interrupt-parent = <&gpio4>; - interrupts = <18 0>; /* gpio_114 */ - pendown-gpio = <&gpio4 18 GPIO_ACTIVE_HIGH>; - - ti,x-min = /bits/ 16 <0x0>; - ti,x-max = /bits/ 16 <0x0fff>; - ti,y-min = /bits/ 16 <0x0>; - ti,y-max = /bits/ 16 <0x0fff>; - ti,x-plate-ohms = /bits/ 16 <180>; - ti,pressure-max = /bits/ 16 <255>; - - wakeup-source; - }; -}; diff --git a/sys/gnu/dts/arm/omap3-overo-common-lcd43.dtsi b/sys/gnu/dts/arm/omap3-overo-common-lcd43.dtsi deleted file mode 100644 index 7fe0f914823..00000000000 --- a/sys/gnu/dts/arm/omap3-overo-common-lcd43.dtsi +++ /dev/null @@ -1,175 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group - */ - -/* - * 4.3'' LCD panel output for some Gumstix Overo boards (Gallop43, Chestnut43) - */ - -&omap3_pmx_core { - dss_dpi_pins: pinmux_dss_dpi_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ - OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ - OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ - OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ - OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ - OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ - OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ - OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ - OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ - OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ - OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ - OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ - OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ - OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ - OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ - OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ - OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ - OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ - OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ - OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ - OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ - OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ - OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */ - OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */ - OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */ - OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */ - OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ - OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ - >; - }; - - lte430_pins: pinmux_lte430_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2174, PIN_OUTPUT | MUX_MODE4) /* uart2_cts.gpio_144 */ - >; - }; - - backlight_pins: pinmux_backlight_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE4) /* uart2_rts.gpio_145 */ - >; - }; - - mcspi1_pins: pinmux_mcspi1_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */ - OMAP3_CORE1_IOPAD(0x21ca, PIN_INPUT | MUX_MODE0) /* mcspi1_simo.mcspi1_simo */ - OMAP3_CORE1_IOPAD(0x21cc, PIN_INPUT | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */ - OMAP3_CORE1_IOPAD(0x21ce, PIN_INPUT | MUX_MODE0) /* mcspi1_cs0.mcspi1_cs0 */ - >; - }; - - ads7846_pins: pinmux_ads7846_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2138, PIN_INPUT_PULLDOWN | MUX_MODE4) /* csi2_dx1.gpio_114 */ - >; - }; -}; - -/* Needed to power the DPI pins */ -&vpll2 { - regulator-always-on; -}; - -&dss { - status = "ok"; - - pinctrl-names = "default"; - pinctrl-0 = <&dss_dpi_pins>; - - port { - dpi_out: endpoint { - remote-endpoint = <&lcd_in>; - data-lines = <24>; - }; - }; -}; - -/ { - aliases { - display0 = &lcd0; - }; - - lcd0: display { - compatible = "samsung,lte430wq-f0c", "panel-dpi"; - label = "lcd43"; - - pinctrl-names = "default"; - pinctrl-0 = <<e430_pins>; - enable-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>; /* gpio_144 */ - - port { - lcd_in: endpoint { - remote-endpoint = <&dpi_out>; - }; - }; - - panel-timing { - clock-frequency = <9200000>; - hactive = <480>; - vactive = <272>; - hfront-porch = <8>; - hback-porch = <4>; - hsync-len = <41>; - vback-porch = <2>; - vfront-porch = <4>; - vsync-len = <10>; - - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - - ads7846reg: ads7846-reg { - compatible = "regulator-fixed"; - regulator-name = "ads7846-reg"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - backlight { - compatible = "gpio-backlight"; - - pinctrl-names = "default"; - pinctrl-0 = <&backlight_pins>; - gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>; /* gpio_145 */ - - default-on; - }; -}; - -&mcspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&mcspi1_pins>; - - /* touch controller */ - ads7846@0 { - pinctrl-names = "default"; - pinctrl-0 = <&ads7846_pins>; - - compatible = "ti,ads7846"; - vcc-supply = <&ads7846reg>; - - reg = <0>; /* CS0 */ - spi-max-frequency = <1500000>; - - interrupt-parent = <&gpio4>; - interrupts = <18 0>; /* gpio_114 */ - pendown-gpio = <&gpio4 18 GPIO_ACTIVE_HIGH>; - - ti,x-min = /bits/ 16 <0x0>; - ti,x-max = /bits/ 16 <0x0fff>; - ti,y-min = /bits/ 16 <0x0>; - ti,y-max = /bits/ 16 <0x0fff>; - ti,x-plate-ohms = /bits/ 16 <180>; - ti,pressure-max = /bits/ 16 <255>; - - wakeup-source; - }; -}; - diff --git a/sys/gnu/dts/arm/omap3-overo-common-peripherals.dtsi b/sys/gnu/dts/arm/omap3-overo-common-peripherals.dtsi deleted file mode 100644 index 8a4a02472c9..00000000000 --- a/sys/gnu/dts/arm/omap3-overo-common-peripherals.dtsi +++ /dev/null @@ -1,92 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group - */ - -/* - * Peripherals common to all Gumstix Overo boards (Tobi, Summit, Palo43,...) - */ - -/ { - lis33_3v3: lis33-3v3-reg { - compatible = "regulator-fixed"; - regulator-name = "lis33-3v3-reg"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - lis33_1v8: lis33-1v8-reg { - compatible = "regulator-fixed"; - regulator-name = "lis33-1v8-reg"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; -}; - -&omap3_pmx_core { - i2c3_pins: pinmux_i2c3_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl.i2c3_scl */ - OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda.i2c3_sda */ - >; - }; - - uart3_pins: pinmux_uart3_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ - OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ - >; - }; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_pins>; - clock-frequency = <100000>; - - /* optional 1K EEPROM with revision information */ - eeprom@51 { - compatible = "atmel,24c01"; - reg = <0x51>; - pagesize = <8>; - }; - - lis33de: lis33de@1d { - compatible = "st,lis33de", "st,lis3lv02d"; - reg = <0x1d>; - Vdd-supply = <&lis33_1v8>; - Vdd_IO-supply = <&lis33_3v3>; - - st,click-single-x; - st,click-single-y; - st,click-single-z; - st,click-thresh-x = <10>; - st,click-thresh-y = <10>; - st,click-thresh-z = <10>; - st,irq1-click; - st,irq2-click; - st,wakeup-x-lo; - st,wakeup-x-hi; - st,wakeup-y-lo; - st,wakeup-y-hi; - st,wakeup-z-lo; - st,wakeup-z-hi; - st,min-limit-x = <120>; - st,min-limit-y = <120>; - st,min-limit-z = <140>; - st,max-limit-x = <550>; - st,max-limit-y = <550>; - st,max-limit-z = <750>; - }; -}; - -&mmc3 { - status = "disabled"; -}; - -&uart3 { - interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>; - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; -}; - diff --git a/sys/gnu/dts/arm/omap3-overo-gallop43-common.dtsi b/sys/gnu/dts/arm/omap3-overo-gallop43-common.dtsi deleted file mode 100644 index 155aec12140..00000000000 --- a/sys/gnu/dts/arm/omap3-overo-gallop43-common.dtsi +++ /dev/null @@ -1,55 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group - */ - -/* - * Gallop43 expansion board is manufactured by Gumstix Inc. - */ - -#include "omap3-overo-common-peripherals.dtsi" -#include "omap3-overo-common-lcd43.dtsi" - -#include - -/ { - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins>; - heartbeat { - label = "overo:red:gpio21"; - gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; /* gpio_21 */ - linux,default-trigger = "heartbeat"; - }; - gpio22 { - label = "overo:blue:gpio22"; - gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; /* gpio_22 */ - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&button_pins>; - #address-cells = <1>; - #size-cells = <0>; - button0 { - label = "button0"; - linux,code = ; - gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; /* gpio_23 */ - wakeup-source; - }; - button1 { - label = "button1"; - linux,code = ; - gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; /* gpio_14 */ - wakeup-source; - }; - }; -}; - -&usbhshost { - status = "disabled"; -}; - diff --git a/sys/gnu/dts/arm/omap3-overo-gallop43.dts b/sys/gnu/dts/arm/omap3-overo-gallop43.dts deleted file mode 100644 index 24b40bdf7ea..00000000000 --- a/sys/gnu/dts/arm/omap3-overo-gallop43.dts +++ /dev/null @@ -1,35 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group - */ - -/* - * Gallop43 expansion board is manufactured by Gumstix Inc. - */ - -/dts-v1/; - -#include "omap3-overo.dtsi" -#include "omap3-overo-gallop43-common.dtsi" - -/ { - model = "OMAP35xx Gumstix Overo on Gallop43"; - compatible = "gumstix,omap3-overo-gallop43", "gumstix,omap3-overo", "ti,omap3430", "ti,omap3"; -}; - -&omap3_pmx_core2 { - led_pins: pinmux_led_pins { - pinctrl-single,pins = < - OMAP3430_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) /* etk_d7.gpio_21 */ - OMAP3430_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* etk_d8.gpio_22 */ - >; - }; - - button_pins: pinmux_button_pins { - pinctrl-single,pins = < - OMAP3430_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE4) /* etk_d9.gpio_23 */ - OMAP3430_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE4) /* etk_d0.gpio_14 */ - >; - }; -}; - diff --git a/sys/gnu/dts/arm/omap3-overo-palo35-common.dtsi b/sys/gnu/dts/arm/omap3-overo-palo35-common.dtsi deleted file mode 100644 index 82a04466747..00000000000 --- a/sys/gnu/dts/arm/omap3-overo-palo35-common.dtsi +++ /dev/null @@ -1,50 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2015 Ash Charles, Gumstix Inc. - */ - -/* - * Palo35 expansion board is manufactured by Gumstix Inc. - */ - -#include "omap3-overo-common-peripherals.dtsi" -#include "omap3-overo-common-lcd35.dtsi" - -#include - -/ { - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins>; - heartbeat { - label = "overo:red:gpio21"; - gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; /* gpio_21 */ - linux,default-trigger = "heartbeat"; - }; - gpio22 { - label = "overo:blue:gpio22"; - gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; /* gpio_22 */ - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&button_pins>; - #address-cells = <1>; - #size-cells = <0>; - button0 { - label = "button0"; - linux,code = ; - gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; /* gpio_23 */ - wakeup-source; - }; - button1 { - label = "button1"; - linux,code = ; - gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; /* gpio_14 */ - wakeup-source; - }; - }; -}; diff --git a/sys/gnu/dts/arm/omap3-overo-palo35.dts b/sys/gnu/dts/arm/omap3-overo-palo35.dts deleted file mode 100644 index 55e08d56b18..00000000000 --- a/sys/gnu/dts/arm/omap3-overo-palo35.dts +++ /dev/null @@ -1,34 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2015 Ash Charles, Gumstix Inc. - */ - -/* - * Palo35 expansion board is manufactured by Gumstix Inc. - */ - -/dts-v1/; - -#include "omap3-overo.dtsi" -#include "omap3-overo-palo35-common.dtsi" - -/ { - model = "OMAP35xx Gumstix Overo on Palo35"; - compatible = "gumstix,omap3-overo-palo35", "gumstix,omap3-overo", "ti,omap3430", "ti,omap3"; -}; - -&omap3_pmx_core2 { - led_pins: pinmux_led_pins { - pinctrl-single,pins = < - OMAP3430_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) /* etk_d7.gpio_21 */ - OMAP3430_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* etk_d8.gpio_22 */ - >; - }; - - button_pins: pinmux_button_pins { - pinctrl-single,pins = < - OMAP3430_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE4) /* etk_d9.gpio_23 */ - OMAP3430_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE4) /* etk_d0.gpio_14 */ - >; - }; -}; diff --git a/sys/gnu/dts/arm/omap3-overo-palo43-common.dtsi b/sys/gnu/dts/arm/omap3-overo-palo43-common.dtsi deleted file mode 100644 index 453a55324fa..00000000000 --- a/sys/gnu/dts/arm/omap3-overo-palo43-common.dtsi +++ /dev/null @@ -1,51 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group - */ - -/* - * Palo43 expansion board is manufactured by Gumstix Inc. - */ - -#include "omap3-overo-common-peripherals.dtsi" -#include "omap3-overo-common-lcd43.dtsi" - -#include - -/ { - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins>; - heartbeat { - label = "overo:red:gpio21"; - gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; /* gpio_21 */ - linux,default-trigger = "heartbeat"; - }; - gpio22 { - label = "overo:blue:gpio22"; - gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; /* gpio_22 */ - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&button_pins>; - #address-cells = <1>; - #size-cells = <0>; - button0 { - label = "button0"; - linux,code = ; - gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; /* gpio_23 */ - wakeup-source; - }; - button1 { - label = "button1"; - linux,code = ; - gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; /* gpio_14 */ - wakeup-source; - }; - }; -}; - diff --git a/sys/gnu/dts/arm/omap3-overo-palo43.dts b/sys/gnu/dts/arm/omap3-overo-palo43.dts deleted file mode 100644 index 092c8325a13..00000000000 --- a/sys/gnu/dts/arm/omap3-overo-palo43.dts +++ /dev/null @@ -1,35 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group - */ - -/* - * Palo43 expansion board is manufactured by Gumstix Inc. - */ - -/dts-v1/; - -#include "omap3-overo.dtsi" -#include "omap3-overo-palo43-common.dtsi" - -/ { - model = "OMAP35xx Gumstix Overo on Palo43"; - compatible = "gumstix,omap3-overo-palo43", "gumstix,omap3-overo", "ti,omap3430", "ti,omap3"; -}; - -&omap3_pmx_core2 { - led_pins: pinmux_led_pins { - pinctrl-single,pins = < - OMAP3430_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) /* etk_d7.gpio_21 */ - OMAP3430_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* etk_d8.gpio_22 */ - >; - }; - - button_pins: pinmux_button_pins { - pinctrl-single,pins = < - OMAP3430_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE4) /* etk_d9.gpio_23 */ - OMAP3430_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE4) /* etk_d0.gpio_14 */ - >; - }; -}; - diff --git a/sys/gnu/dts/arm/omap3-overo-storm-alto35.dts b/sys/gnu/dts/arm/omap3-overo-storm-alto35.dts deleted file mode 100644 index 18338576c41..00000000000 --- a/sys/gnu/dts/arm/omap3-overo-storm-alto35.dts +++ /dev/null @@ -1,18 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group - */ - -/* - * Alto35 expansion board is manufactured by Gumstix Inc. - */ - -/dts-v1/; - -#include "omap3-overo-storm.dtsi" -#include "omap3-overo-alto35-common.dtsi" - -/ { - model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on Alto35"; - compatible = "gumstix,omap3-overo-alto35", "gumstix,omap3-overo", "ti,omap36xx", "ti,omap3"; -}; diff --git a/sys/gnu/dts/arm/omap3-overo-storm-chestnut43.dts b/sys/gnu/dts/arm/omap3-overo-storm-chestnut43.dts deleted file mode 100644 index f204c8af828..00000000000 --- a/sys/gnu/dts/arm/omap3-overo-storm-chestnut43.dts +++ /dev/null @@ -1,35 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group - */ - -/* - * Chestnut43 expansion board is manufactured by Gumstix Inc. - */ - -/dts-v1/; - -#include "omap3-overo-storm.dtsi" -#include "omap3-overo-chestnut43-common.dtsi" - -/ { - model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on Chestnut43"; - compatible = "gumstix,omap3-overo-chestnut43", "gumstix,omap3-overo", "ti,omap36xx", "ti,omap3"; -}; - -&omap3_pmx_core2 { - led_pins: pinmux_led_pins { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) /* etk_d7.gpio_21 */ - OMAP3630_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* etk_d8.gpio_22 */ - >; - }; - - button_pins: pinmux_button_pins { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE4) /* etk_d9.gpio_23 */ - OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE4) /* etk_d0.gpio_14 */ - >; - }; -}; - diff --git a/sys/gnu/dts/arm/omap3-overo-storm-gallop43.dts b/sys/gnu/dts/arm/omap3-overo-storm-gallop43.dts deleted file mode 100644 index c633f7cee68..00000000000 --- a/sys/gnu/dts/arm/omap3-overo-storm-gallop43.dts +++ /dev/null @@ -1,35 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group - */ - -/* - * Gallop43 expansion board is manufactured by Gumstix Inc. - */ - -/dts-v1/; - -#include "omap3-overo-storm.dtsi" -#include "omap3-overo-gallop43-common.dtsi" - -/ { - model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on Gallop43"; - compatible = "gumstix,omap3-overo-gallop43", "gumstix,omap3-overo", "ti,omap36xx", "ti,omap3"; -}; - -&omap3_pmx_core2 { - led_pins: pinmux_led_pins { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) /* etk_d7.gpio_21 */ - OMAP3630_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* etk_d8.gpio_22 */ - >; - }; - - button_pins: pinmux_button_pins { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE4) /* etk_d9.gpio_23 */ - OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE4) /* etk_d0.gpio_14 */ - >; - }; -}; - diff --git a/sys/gnu/dts/arm/omap3-overo-storm-palo35.dts b/sys/gnu/dts/arm/omap3-overo-storm-palo35.dts deleted file mode 100644 index fb88ebc9858..00000000000 --- a/sys/gnu/dts/arm/omap3-overo-storm-palo35.dts +++ /dev/null @@ -1,34 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2015 Ash Charles, Gumstix, Inc. - */ - -/* - * Palo35 expansion board is manufactured by Gumstix Inc. - */ - -/dts-v1/; - -#include "omap3-overo-storm.dtsi" -#include "omap3-overo-palo35-common.dtsi" - -/ { - model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on Palo35"; - compatible = "gumstix,omap3-overo-palo35", "gumstix,omap3-overo", "ti,omap36xx", "ti,omap3"; -}; - -&omap3_pmx_core2 { - led_pins: pinmux_led_pins { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) /* etk_d7.gpio_21 */ - OMAP3630_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* etk_d8.gpio_22 */ - >; - }; - - button_pins: pinmux_button_pins { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE4) /* etk_d9.gpio_23 */ - OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE4) /* etk_d0.gpio_14 */ - >; - }; -}; diff --git a/sys/gnu/dts/arm/omap3-overo-storm-palo43.dts b/sys/gnu/dts/arm/omap3-overo-storm-palo43.dts deleted file mode 100644 index 76cca00d97b..00000000000 --- a/sys/gnu/dts/arm/omap3-overo-storm-palo43.dts +++ /dev/null @@ -1,35 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group - */ - -/* - * Palo43 expansion board is manufactured by Gumstix Inc. - */ - -/dts-v1/; - -#include "omap3-overo-storm.dtsi" -#include "omap3-overo-palo43-common.dtsi" - -/ { - model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on Palo43"; - compatible = "gumstix,omap3-overo-palo43", "gumstix,omap3-overo", "ti,omap36xx", "ti,omap3"; -}; - -&omap3_pmx_core2 { - led_pins: pinmux_led_pins { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) /* etk_d7.gpio_21 */ - OMAP3630_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* etk_d8.gpio_22 */ - >; - }; - - button_pins: pinmux_button_pins { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE4) /* etk_d9.gpio_23 */ - OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE4) /* etk_d0.gpio_14 */ - >; - }; -}; - diff --git a/sys/gnu/dts/arm/omap3-overo-storm-summit.dts b/sys/gnu/dts/arm/omap3-overo-storm-summit.dts deleted file mode 100644 index cc081a9e4c1..00000000000 --- a/sys/gnu/dts/arm/omap3-overo-storm-summit.dts +++ /dev/null @@ -1,27 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group - */ - -/* - * Summit expansion board is manufactured by Gumstix Inc. - */ - -/dts-v1/; - -#include "omap3-overo-storm.dtsi" -#include "omap3-overo-summit-common.dtsi" - -/ { - model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on Summit"; - compatible = "gumstix,omap3-overo-summit", "gumstix,omap3-overo", "ti,omap36xx", "ti,omap3"; -}; - -&omap3_pmx_core2 { - led_pins: pinmux_led_pins { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) /* etk_d7.gpio_21 */ - >; - }; -}; - diff --git a/sys/gnu/dts/arm/omap3-overo-storm-tobi.dts b/sys/gnu/dts/arm/omap3-overo-storm-tobi.dts deleted file mode 100644 index 1de41c0826e..00000000000 --- a/sys/gnu/dts/arm/omap3-overo-storm-tobi.dts +++ /dev/null @@ -1,19 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Florian Vaussard, EPFL Mobots group - */ - -/* - * Tobi expansion board is manufactured by Gumstix Inc. - */ - -/dts-v1/; - -#include "omap3-overo-storm.dtsi" -#include "omap3-overo-tobi-common.dtsi" - -/ { - model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on Tobi"; - compatible = "gumstix,omap3-overo-tobi", "gumstix,omap3-overo", "ti,omap36xx", "ti,omap3"; -}; - diff --git a/sys/gnu/dts/arm/omap3-overo-storm-tobiduo.dts b/sys/gnu/dts/arm/omap3-overo-storm-tobiduo.dts deleted file mode 100644 index 9ed13118ed8..00000000000 --- a/sys/gnu/dts/arm/omap3-overo-storm-tobiduo.dts +++ /dev/null @@ -1,18 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2015 Ash Charles, Gumstix, Inc. - */ - -/* - * TobiDuo expansion board is manufactured by Gumstix Inc. - */ - -/dts-v1/; - -#include "omap3-overo-storm.dtsi" -#include "omap3-overo-tobiduo-common.dtsi" - -/ { - model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on TobiDuo"; - compatible = "gumstix,omap3-overo-tobiduo", "gumstix,omap3-overo", "ti,omap36xx", "ti,omap3"; -}; diff --git a/sys/gnu/dts/arm/omap3-overo-storm.dtsi b/sys/gnu/dts/arm/omap3-overo-storm.dtsi deleted file mode 100644 index 2af15d5f61f..00000000000 --- a/sys/gnu/dts/arm/omap3-overo-storm.dtsi +++ /dev/null @@ -1,32 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group - */ - -#include "omap36xx.dtsi" -#include "omap3-overo-base.dtsi" - -&omap3_pmx_core2 { - pinctrl-names = "default"; - pinctrl-0 = < - &hsusb2_2_pins - >; - - hsusb2_2_pins: pinmux_hsusb2_2_pins { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ - OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ - OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ - OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ - OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ - OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ - >; - }; - - w3cbw003c_2_pins: pinmux_w3cbw003c_2_pins { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE4) /* etk_d2.gpio_16 */ - >; - }; -}; - diff --git a/sys/gnu/dts/arm/omap3-overo-summit-common.dtsi b/sys/gnu/dts/arm/omap3-overo-summit-common.dtsi deleted file mode 100644 index df7450f17ff..00000000000 --- a/sys/gnu/dts/arm/omap3-overo-summit-common.dtsi +++ /dev/null @@ -1,29 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group - */ - -/* - * Summit expansion board is manufactured by Gumstix Inc. - */ - -#include "omap3-overo-common-peripherals.dtsi" -#include "omap3-overo-common-dvi.dtsi" - -/ { - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins>; - heartbeat { - label = "overo:red:gpio21"; - gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; /* gpio_21 */ - linux,default-trigger = "heartbeat"; - }; - }; -}; - -&lis33de { - status = "disabled"; -}; - diff --git a/sys/gnu/dts/arm/omap3-overo-summit.dts b/sys/gnu/dts/arm/omap3-overo-summit.dts deleted file mode 100644 index a6c9799fe49..00000000000 --- a/sys/gnu/dts/arm/omap3-overo-summit.dts +++ /dev/null @@ -1,27 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group - */ - -/* - * Summit expansion board is manufactured by Gumstix Inc. - */ - -/dts-v1/; - -#include "omap3-overo.dtsi" -#include "omap3-overo-summit-common.dtsi" - -/ { - model = "OMAP35xx Gumstix Overo on Summit"; - compatible = "gumstix,omap3-overo-summit", "gumstix,omap3-overo", "ti,omap3430", "ti,omap3"; -}; - -&omap3_pmx_core2 { - led_pins: pinmux_led_pins { - pinctrl-single,pins = < - OMAP3430_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) /* etk_d7.gpio_21 */ - >; - }; -}; - diff --git a/sys/gnu/dts/arm/omap3-overo-tobi-common.dtsi b/sys/gnu/dts/arm/omap3-overo-tobi-common.dtsi deleted file mode 100644 index 9bf4b88a4b5..00000000000 --- a/sys/gnu/dts/arm/omap3-overo-tobi-common.dtsi +++ /dev/null @@ -1,37 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Florian Vaussard, EPFL Mobots group - */ - -/* - * Tobi expansion board is manufactured by Gumstix Inc. - */ - -#include "omap3-overo-common-peripherals.dtsi" -#include "omap3-overo-common-dvi.dtsi" - -/ { - leds { - compatible = "gpio-leds"; - heartbeat { - label = "overo:red:gpio21"; - gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - }; - }; -}; - -#include "omap-gpmc-smsc9221.dtsi" - -&gpmc { - ethernet@gpmc { - reg = <5 0 0xff>; - interrupt-parent = <&gpio6>; - interrupts = <16 IRQ_TYPE_LEVEL_LOW>; /* GPIO 176 */ - }; -}; - -&lis33de { - status = "disabled"; -}; - diff --git a/sys/gnu/dts/arm/omap3-overo-tobi.dts b/sys/gnu/dts/arm/omap3-overo-tobi.dts deleted file mode 100644 index ce3f2404f32..00000000000 --- a/sys/gnu/dts/arm/omap3-overo-tobi.dts +++ /dev/null @@ -1,19 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Florian Vaussard, EPFL Mobots group - */ - -/* - * Tobi expansion board is manufactured by Gumstix Inc. - */ - -/dts-v1/; - -#include "omap3-overo.dtsi" -#include "omap3-overo-tobi-common.dtsi" - -/ { - model = "OMAP35xx Gumstix Overo on Tobi"; - compatible = "gumstix,omap3-overo-tobi", "gumstix,omap3-overo", "ti,omap3430", "ti,omap3"; -}; - diff --git a/sys/gnu/dts/arm/omap3-overo-tobiduo-common.dtsi b/sys/gnu/dts/arm/omap3-overo-tobiduo-common.dtsi deleted file mode 100644 index e5da3bc6f10..00000000000 --- a/sys/gnu/dts/arm/omap3-overo-tobiduo-common.dtsi +++ /dev/null @@ -1,59 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2015 Ash Charles, Gumstix, Inc. - */ - -/* - * TobiDuo expansion board is manufactured by Gumstix Inc. - */ - -#include "omap3-overo-common-peripherals.dtsi" - -#include "omap-gpmc-smsc9221.dtsi" - -&gpmc { - smsc1: ethernet@gpmc { - reg = <5 0 0xff>; - interrupt-parent = <&gpio6>; - interrupts = <16 IRQ_TYPE_LEVEL_LOW>; /* GPIO 176 */ - }; - - smsc2: ethernet@4,0 { - compatible = "smsc,lan9221","smsc,lan9115"; - bank-width = <2>; - - gpmc,mux-add-data; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <42>; - gpmc,cs-wr-off-ns = <36>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <12>; - gpmc,adv-wr-off-ns = <12>; - gpmc,oe-on-ns = <0>; - gpmc,oe-off-ns = <42>; - gpmc,we-on-ns = <0>; - gpmc,we-off-ns = <36>; - gpmc,rd-cycle-ns = <60>; - gpmc,wr-cycle-ns = <54>; - gpmc,access-ns = <36>; - gpmc,page-burst-access-ns = <0>; - gpmc,bus-turnaround-ns = <0>; - gpmc,cycle2cycle-delay-ns = <0>; - gpmc,wr-data-mux-bus-ns = <18>; - gpmc,wr-access-ns = <42>; - gpmc,cycle2cycle-samecsen; - gpmc,cycle2cycle-diffcsen; - vddvario-supply = <&vddvario>; - vdd33a-supply = <&vdd33a>; - reg-io-width = <4>; - smsc,save-mac-address; - - reg = <4 0 0xff>; - interrupt-parent = <&gpio3>; - interrupts = <1 IRQ_TYPE_LEVEL_LOW>; /* GPIO 65 */ - }; -}; - -&lis33de { - status = "disabled"; -}; diff --git a/sys/gnu/dts/arm/omap3-overo-tobiduo.dts b/sys/gnu/dts/arm/omap3-overo-tobiduo.dts deleted file mode 100644 index fc6163eae45..00000000000 --- a/sys/gnu/dts/arm/omap3-overo-tobiduo.dts +++ /dev/null @@ -1,18 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2015 Ash Charles, Gumstix, Inc. - */ - -/* - * TobiDuo expansion board is manufactured by Gumstix Inc. - */ - -/dts-v1/; - -#include "omap3-overo.dtsi" -#include "omap3-overo-tobiduo-common.dtsi" - -/ { - model = "OMAP35xx Gumstix Overo on TobiDuo"; - compatible = "gumstix,omap3-overo-tobiduo", "gumstix,omap3-overo", "ti,omap3430", "ti,omap3"; -}; diff --git a/sys/gnu/dts/arm/omap3-overo.dtsi b/sys/gnu/dts/arm/omap3-overo.dtsi deleted file mode 100644 index cc9263e9925..00000000000 --- a/sys/gnu/dts/arm/omap3-overo.dtsi +++ /dev/null @@ -1,31 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group - */ - -#include "omap34xx.dtsi" -#include "omap3-overo-base.dtsi" - -&omap3_pmx_core2 { - pinctrl-names = "default"; - pinctrl-0 = < - &hsusb2_2_pins - >; - - hsusb2_2_pins: pinmux_hsusb2_2_pins { - pinctrl-single,pins = < - OMAP3430_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ - OMAP3430_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ - OMAP3430_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ - OMAP3430_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ - OMAP3430_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ - OMAP3430_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ - >; - }; - - w3cbw003c_2_pins: pinmux_w3cbw003c_2_pins { - pinctrl-single,pins = < - OMAP3430_CORE2_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE4) /* etk_d2.gpio_16 */ - >; - }; -}; diff --git a/sys/gnu/dts/arm/omap3-pandora-1ghz.dts b/sys/gnu/dts/arm/omap3-pandora-1ghz.dts deleted file mode 100644 index 81b957f33c9..00000000000 --- a/sys/gnu/dts/arm/omap3-pandora-1ghz.dts +++ /dev/null @@ -1,67 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2015 - * Nikolaus Schaller - */ - -/* - * device tree for OpenPandora 1GHz with DM3730 - */ - -/dts-v1/; - -#include "omap36xx.dtsi" -#include "omap3-pandora-common.dtsi" - -/ { - model = "Pandora Handheld Console 1GHz"; - - compatible = "openpandora,omap3-pandora-1ghz", "ti,omap36xx", "ti,omap3"; -}; - -&omap3_pmx_core2 { - - pinctrl-names = "default"; - pinctrl-0 = < - &hsusb2_2_pins - &control_pins - >; - - hsusb2_2_pins: pinmux_hsusb2_2_pins { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ - OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ - OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ - OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ - OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ - OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ - >; - }; - - mmc3_pins: pinmux_mmc3_pins { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25d8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_clk.sdmmc3_clk */ - OMAP3630_CORE2_IOPAD(0x25da, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_ctl.sdmmc3_cmd */ - OMAP3630_CORE2_IOPAD(0x25e2, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d3.sdmmc3_dat3 */ - OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d4.sdmmc3_dat0 */ - OMAP3630_CORE2_IOPAD(0x25e6, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d5.sdmmc3_dat1 */ - OMAP3630_CORE2_IOPAD(0x25e8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d6.sdmmc3_dat2 */ - >; - }; - - control_pins: pinmux_control_pins { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT_PULLDOWN | MUX_MODE4) /* etk_d0.gpio_14 = HP_SHUTDOWN */ - OMAP3630_CORE2_IOPAD(0x25de, PIN_OUTPUT | MUX_MODE4) /* etk_d1.gpio_15 = BT_SHUTDOWN */ - OMAP3630_CORE2_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE4) /* etk_d2.gpio_16 = RESET_USB_HOST */ - OMAP3630_CORE2_IOPAD(0x25ea, PIN_INPUT | MUX_MODE4) /* etk_d7.gpio_21 = WIFI IRQ */ - OMAP3630_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* etk_d8.gpio_22 = MSECURE */ - OMAP3630_CORE2_IOPAD(0x25ee, PIN_OUTPUT | MUX_MODE4) /* etk_d9.gpio_23 = WIFI_POWER */ - OMAP3_WKUP_IOPAD(0x2a54, PIN_INPUT | MUX_MODE4) /* reserved.gpio_127 = MMC2_WP */ - OMAP3_WKUP_IOPAD(0x2a56, PIN_INPUT | MUX_MODE4) /* reserved.gpio_126 = MMC1_WP */ - OMAP3_WKUP_IOPAD(0x2a58, PIN_OUTPUT | MUX_MODE4) /* reserved.gpio_128 = LED_MMC1 */ - OMAP3_WKUP_IOPAD(0x2a5a, PIN_OUTPUT | MUX_MODE4) /* reserved.gpio_129 = LED_MMC2 */ - - >; - }; -}; diff --git a/sys/gnu/dts/arm/omap3-pandora-600mhz.dts b/sys/gnu/dts/arm/omap3-pandora-600mhz.dts deleted file mode 100644 index 6bd9041942f..00000000000 --- a/sys/gnu/dts/arm/omap3-pandora-600mhz.dts +++ /dev/null @@ -1,62 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2015 - * Nikolaus Schaller - */ - -/* - * device tree for OpenPandora with OMAP3530 - */ - -/dts-v1/; - -#include "omap34xx.dtsi" -#include "omap3-pandora-common.dtsi" - -/ { - model = "Pandora Handheld Console"; - - compatible = "openpandora,omap3-pandora-600mhz", "ti,omap3430", "ti,omap3"; -}; - -&omap3_pmx_core2 { - - pinctrl-names = "default"; - pinctrl-0 = < - &hsusb2_2_pins - &control_pins - >; - - hsusb2_2_pins: pinmux_hsusb2_2_pins { - pinctrl-single,pins = < - OMAP3430_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ - OMAP3430_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ - OMAP3430_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ - OMAP3430_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ - OMAP3430_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ - OMAP3430_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ - >; - }; - - mmc3_pins: pinmux_mmc3_pins { - pinctrl-single,pins = < - OMAP3430_CORE2_IOPAD(0x25d8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_clk.sdmmc3_clk */ - OMAP3430_CORE2_IOPAD(0x25da, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_ctl.sdmmc3_cmd */ - OMAP3430_CORE2_IOPAD(0x25e2, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d3.sdmmc3_dat3 */ - OMAP3430_CORE2_IOPAD(0x25e4, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d4.sdmmc3_dat0 */ - OMAP3430_CORE2_IOPAD(0x25e6, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d5.sdmmc3_dat1 */ - OMAP3430_CORE2_IOPAD(0x25e8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d6.sdmmc3_dat2 */ - >; - }; - - control_pins: pinmux_control_pins { - pinctrl-single,pins = < - OMAP3430_CORE2_IOPAD(0x25dc, PIN_INPUT_PULLDOWN | MUX_MODE4) /* etk_d0.gpio_14 = HP_SHUTDOWN */ - OMAP3430_CORE2_IOPAD(0x25de, PIN_OUTPUT | MUX_MODE4) /* etk_d1.gpio_15 = BT_SHUTDOWN */ - OMAP3430_CORE2_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE4) /* etk_d2.gpio_16 = RESET_USB_HOST */ - OMAP3430_CORE2_IOPAD(0x25ea, PIN_INPUT | MUX_MODE4) /* etk_d7.gpio_21 = WIFI IRQ */ - OMAP3430_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* etk_d8.gpio_22 = MSECURE */ - OMAP3430_CORE2_IOPAD(0x25ee, PIN_OUTPUT | MUX_MODE4) /* etk_d9.gpio_23 = WIFI_POWER */ - >; - }; -}; diff --git a/sys/gnu/dts/arm/omap3-pandora-common.dtsi b/sys/gnu/dts/arm/omap3-pandora-common.dtsi deleted file mode 100644 index ec5891718ae..00000000000 --- a/sys/gnu/dts/arm/omap3-pandora-common.dtsi +++ /dev/null @@ -1,698 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2015 - * Nikolaus Schaller - * - * Common device tree include for OpenPandora devices. - */ - -#include - -/ { - cpus { - cpu@0 { - cpu0-supply = <&vcc>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000>; /* 512 MB */ - }; - - aliases { - display0 = &lcd; - }; - - /* fixed 26MHz oscillator */ - hfclk_26m: oscillator { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <26000000>; - }; - - tv: connector { - compatible = "connector-analog-tv"; - label = "tv"; - - port { - tv_connector_in: endpoint { - remote-endpoint = <&venc_out>; - }; - }; - }; - - gpio-leds { - - compatible = "gpio-leds"; - - pinctrl-names = "default"; - pinctrl-0 = <&led_pins>; - - led1 { - label = "pandora::sd1"; - gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>; /* GPIO_128 */ - linux,default-trigger = "mmc0"; - default-state = "off"; - }; - - led2 { - label = "pandora::sd2"; - gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; /* GPIO_129 */ - linux,default-trigger = "mmc1"; - default-state = "off"; - }; - - led3 { - label = "pandora::bluetooth"; - gpios = <&gpio5 30 GPIO_ACTIVE_HIGH>; /* GPIO_158 */ - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - - led4 { - label = "pandora::wifi"; - gpios = <&gpio5 31 GPIO_ACTIVE_HIGH>; /* GPIO_159 */ - linux,default-trigger = "mmc2"; - default-state = "off"; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - pinctrl-names = "default"; - pinctrl-0 = <&button_pins>; - - up-button { - label = "up"; - linux,code = ; - gpios = <&gpio4 14 GPIO_ACTIVE_LOW>; /* GPIO_110 */ - wakeup-source; - }; - - down-button { - label = "down"; - linux,code = ; - gpios = <&gpio4 7 GPIO_ACTIVE_LOW>; /* GPIO_103 */ - wakeup-source; - }; - - left-button { - label = "left"; - linux,code = ; - gpios = <&gpio4 0 GPIO_ACTIVE_LOW>; /* GPIO_96 */ - wakeup-source; - }; - - right-button { - label = "right"; - linux,code = ; - gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; /* GPIO_98 */ - wakeup-source; - }; - - pageup-button { - label = "game 1"; - linux,code = ; - gpios = <&gpio4 13 GPIO_ACTIVE_LOW>; /* GPIO_109 */ - wakeup-source; - }; - - pagedown-button { - label = "game 3"; - linux,code = ; - gpios = <&gpio4 10 GPIO_ACTIVE_LOW>; /* GPIO_106 */ - wakeup-source; - }; - - home-button { - label = "game 4"; - linux,code = ; - gpios = <&gpio4 5 GPIO_ACTIVE_LOW>; /* GPIO_101 */ - wakeup-source; - }; - - end-button { - label = "game 2"; - linux,code = ; - gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* GPIO_111 */ - wakeup-source; - }; - - right-shift { - label = "l"; - linux,code = ; - gpios = <&gpio4 6 GPIO_ACTIVE_LOW>; /* GPIO_102 */ - wakeup-source; - }; - - kp-plus { - label = "l2"; - linux,code = ; - gpios = <&gpio4 1 GPIO_ACTIVE_LOW>; /* GPIO_97 */ - wakeup-source; - }; - - right-ctrl { - label = "r"; - linux,code = ; - gpios = <&gpio4 9 GPIO_ACTIVE_LOW>; /* GPIO_105 */ - wakeup-source; - }; - - kp-minus { - label = "r2"; - linux,code = ; - gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; /* GPIO_107 */ - wakeup-source; - }; - - left-ctrl { - label = "ctrl"; - linux,code = ; - gpios = <&gpio4 8 GPIO_ACTIVE_LOW>; /* GPIO_104 */ - wakeup-source; - }; - - menu { - label = "menu"; - linux,code = ; - gpios = <&gpio4 3 GPIO_ACTIVE_LOW>; /* GPIO_99 */ - wakeup-source; - }; - - hold { - label = "hold"; - linux,code = ; - gpios = <&gpio6 16 GPIO_ACTIVE_LOW>; /* GPIO_176 */ - wakeup-source; - }; - - left-alt { - label = "alt"; - linux,code = ; - gpios = <&gpio4 4 GPIO_ACTIVE_HIGH>; /* GPIO_100 */ - wakeup-source; - }; - - lid { - label = "lid"; - linux,code = <0x00>; /* SW_LID lid shut */ - linux,input-type = <0x05>; /* EV_SW */ - gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>; /* GPIO_108 */ - }; - }; - - /* HS USB Host PHY on PORT 2 */ - hsusb2_phy: hsusb2_phy { - compatible = "usb-nop-xceiv"; - reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; /* GPIO_16 */ - vcc-supply = <&vaux2>; - #phy-cells = <0>; - }; - - /* HS USB Host VBUS supply - * disabling this regulator causes current leakage, and LCD flicker - * on earlier (CC) board revisions, so keep it always on */ - usb_host_5v: fixed-regulator-usb_host_5v { - compatible = "regulator-fixed"; - regulator-name = "usb_host_5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&gpio6 4 GPIO_ACTIVE_HIGH>; /* GPIO_164 */ - }; - - /* wg7210 (wifi+bt module) 32k clock buffer */ - wg7210_32k: fixed-regulator-wg7210_32k { - compatible = "regulator-fixed"; - regulator-name = "wg7210_32k"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - enable-active-high; - gpio = <&twl_gpio 13 GPIO_ACTIVE_HIGH>; - }; -}; - -&omap3_pmx_core { - - mmc1_pins: pinmux_mmc1_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ - OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ - OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ - OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ - OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ - OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ - >; - }; - - mmc2_pins: pinmux_mmc2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ - OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ - OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ - OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ - OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ - OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ - OMAP3_CORE1_IOPAD(0x2164, PIN_OUTPUT_PULLUP | MUX_MODE1) /* sdmmc2_dat4.sdmmc2_dirdat0 */ - OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT_PULLUP | MUX_MODE1) /* sdmmc2_dat5.sdmmc2_dirdat1 */ - OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT_PULLUP | MUX_MODE1) /* sdmmc2_dat6.sdmmc2_dircmd */ - OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT_PULLUP | MUX_MODE1) /* sdmmc2_dat7.sdmmc2_clkin */ - >; - }; - - dss_dpi_pins: pinmux_dss_dpi_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ - OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ - OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ - OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ - OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ - OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ - OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ - OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ - OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ - OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ - OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ - OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ - OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ - OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ - OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ - OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ - OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ - OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ - OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ - OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ - OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ - OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ - OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */ - OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */ - OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */ - OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */ - OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ - OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ - OMAP3_CORE1_IOPAD(0x218e, PIN_OUTPUT | MUX_MODE4) /* GPIO_157 = lcd reset */ - >; - }; - - uart3_pins: pinmux_uart3_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ - OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ - >; - }; - - led_pins: pinmux_leds_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2154, PIN_OUTPUT | MUX_MODE4) /* GPIO_128 */ - OMAP3_CORE1_IOPAD(0x2156, PIN_OUTPUT | MUX_MODE4) /* GPIO_129 */ - OMAP3_CORE1_IOPAD(0x2190, PIN_OUTPUT | MUX_MODE4) /* GPIO_158 */ - OMAP3_CORE1_IOPAD(0x2192, PIN_OUTPUT | MUX_MODE4) /* GPIO_159 */ - >; - }; - - button_pins: pinmux_button_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2110, PIN_INPUT | MUX_MODE4) /* GPIO_96 */ - OMAP3_CORE1_IOPAD(0x2112, PIN_INPUT | MUX_MODE4) /* GPIO_97 */ - OMAP3_CORE1_IOPAD(0x2114, PIN_INPUT | MUX_MODE4) /* GPIO_98 */ - OMAP3_CORE1_IOPAD(0x2116, PIN_INPUT | MUX_MODE4) /* GPIO_99 */ - OMAP3_CORE1_IOPAD(0x2118, PIN_INPUT | MUX_MODE4) /* GPIO_100 */ - OMAP3_CORE1_IOPAD(0x211a, PIN_INPUT | MUX_MODE4) /* GPIO_101 */ - OMAP3_CORE1_IOPAD(0x211c, PIN_INPUT | MUX_MODE4) /* GPIO_102 */ - OMAP3_CORE1_IOPAD(0x211e, PIN_INPUT | MUX_MODE4) /* GPIO_103 */ - OMAP3_CORE1_IOPAD(0x2120, PIN_INPUT | MUX_MODE4) /* GPIO_104 */ - OMAP3_CORE1_IOPAD(0x2122, PIN_INPUT | MUX_MODE4) /* GPIO_105 */ - OMAP3_CORE1_IOPAD(0x2124, PIN_INPUT | MUX_MODE4) /* GPIO_106 */ - OMAP3_CORE1_IOPAD(0x2126, PIN_INPUT | MUX_MODE4) /* GPIO_107 */ - OMAP3_CORE1_IOPAD(0x2128, PIN_INPUT | MUX_MODE4) /* GPIO_108 */ - OMAP3_CORE1_IOPAD(0x212a, PIN_INPUT | MUX_MODE4) /* GPIO_109 */ - OMAP3_CORE1_IOPAD(0x212c, PIN_INPUT | MUX_MODE4) /* GPIO_110 */ - OMAP3_CORE1_IOPAD(0x212e, PIN_INPUT | MUX_MODE4) /* GPIO_111 */ - OMAP3_CORE1_IOPAD(0x21d2, PIN_INPUT | MUX_MODE4) /* GPIO_176 */ - >; - }; - - penirq_pins: pinmux_penirq_pins { - pinctrl-single,pins = < - /* here we could enable to wakeup the cpu from suspend by a pen touch */ - OMAP3_CORE1_IOPAD(0x210c, PIN_INPUT | MUX_MODE4) /* GPIO_94 */ - >; - }; - -}; - -&omap3_pmx_core2 { - /* define in CPU specific file that includes this one - * use either OMAP3430_CORE2_IOPAD() or OMAP3630_CORE2_IOPAD() - */ -}; - -&i2c1 { - clock-frequency = <2600000>; - - twl: twl@48 { - reg = <0x48>; - interrupts = <7>; /* SYS_NIRQ cascaded to intc */ - interrupt-parent = <&intc>; - - clocks = <&hfclk_26m>; - clock-names = "fck"; - - twl_power: power { - compatible = "ti,twl4030-power-reset"; - ti,use_poweroff; - }; - - twl_audio: audio { - compatible = "ti,twl4030-audio"; - - codec { - ti,ramp_delay_value = <3>; - }; - }; - }; -}; - -#include "twl4030.dtsi" -#include "twl4030_omap3.dtsi" - -&twl_keypad { - keypad,num-rows = <8>; - keypad,num-columns = <6>; - linux,keymap = < - MATRIX_KEY(0, 0, KEY_9) - MATRIX_KEY(0, 1, KEY_8) - MATRIX_KEY(0, 2, KEY_I) - MATRIX_KEY(0, 3, KEY_J) - MATRIX_KEY(0, 4, KEY_N) - MATRIX_KEY(0, 5, KEY_M) - MATRIX_KEY(1, 0, KEY_0) - MATRIX_KEY(1, 1, KEY_7) - MATRIX_KEY(1, 2, KEY_U) - MATRIX_KEY(1, 3, KEY_H) - MATRIX_KEY(1, 4, KEY_B) - MATRIX_KEY(1, 5, KEY_SPACE) - MATRIX_KEY(2, 0, KEY_BACKSPACE) - MATRIX_KEY(2, 1, KEY_6) - MATRIX_KEY(2, 2, KEY_Y) - MATRIX_KEY(2, 3, KEY_G) - MATRIX_KEY(2, 4, KEY_V) - MATRIX_KEY(2, 5, KEY_FN) - MATRIX_KEY(3, 0, KEY_O) - MATRIX_KEY(3, 1, KEY_5) - MATRIX_KEY(3, 2, KEY_T) - MATRIX_KEY(3, 3, KEY_F) - MATRIX_KEY(3, 4, KEY_C) - MATRIX_KEY(4, 0, KEY_P) - MATRIX_KEY(4, 1, KEY_4) - MATRIX_KEY(4, 2, KEY_R) - MATRIX_KEY(4, 3, KEY_D) - MATRIX_KEY(4, 4, KEY_X) - MATRIX_KEY(5, 0, KEY_K) - MATRIX_KEY(5, 1, KEY_3) - MATRIX_KEY(5, 2, KEY_E) - MATRIX_KEY(5, 3, KEY_S) - MATRIX_KEY(5, 4, KEY_Z) - MATRIX_KEY(6, 0, KEY_L) - MATRIX_KEY(6, 1, KEY_2) - MATRIX_KEY(6, 2, KEY_W) - MATRIX_KEY(6, 3, KEY_A) - MATRIX_KEY(6, 4, KEY_RIGHTBRACE) - MATRIX_KEY(7, 0, KEY_ENTER) - MATRIX_KEY(7, 1, KEY_1) - MATRIX_KEY(7, 2, KEY_Q) - MATRIX_KEY(7, 3, KEY_LEFTSHIFT) - MATRIX_KEY(7, 4, KEY_LEFTBRACE ) - >; -}; - -/* backup battery charger */ -&charger { - ti,bb-uvolt = <3200000>; - ti,bb-uamp = <150>; -}; - -/* MMC2 */ -&vmmc2 { - regulator-min-microvolt = <1850000>; - regulator-max-microvolt = <3150000>; -}; - -/* LCD */ -&vaux1 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; -}; - -/* USB Host PHY */ -&vaux2 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; -}; - -/* available on expansion connector */ -&vaux3 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; -}; - -/* ADS7846 and nubs */ -&vaux4 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; -}; - -/* power audio DAC and LID sensor */ -&vsim { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; -}; - -&i2c2 { - clock-frequency = <100000>; - /* no clients so we should disable clock */ -}; - -&i2c3 { - clock-frequency = <100000>; - - bq27500@55 { - compatible = "ti,bq27500"; - reg = <0x55>; - }; - -}; - -&usb_otg_hs { - interface-type = <0>; - usb-phy = <&usb2_phy>; - phys = <&usb2_phy>; - phy-names = "usb2-phy"; - mode = <3>; - power = <50>; -}; - -/* - * Many pandora boards have been produced with defective write-protect switches - * on either slot, so it was decided not to use this feature. If you know - * your board has good switches, feel free to uncomment wp-gpios below. - */ -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - vmmc-supply = <&vmmc1>; - bus-width = <4>; - cd-gpios = <&twl_gpio 0 GPIO_ACTIVE_LOW>; - /*wp-gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>;*/ /* GPIO_126 */ -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; - vmmc-supply = <&vmmc2>; - bus-width = <4>; - cd-gpios = <&twl_gpio 1 GPIO_ACTIVE_LOW>; - /*wp-gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>;*/ /* GPIO_127 */ -}; - -/* mmc3 is probed using pdata-quirks to pass wl1251 card data */ -&mmc3 { - status = "disabled"; -}; - -/* bluetooth*/ -&uart1 { -}; - -/* spare (expansion connector) */ -&uart2 { -}; - -/* console (expansion connector) */ -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; - interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>; -}; - -&usbhshost { - port2-mode = "ehci-phy"; -}; - -&usbhsehci { - phys = <0 &hsusb2_phy>; -}; - -&gpmc { - ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */ - - nand@0,0 { - compatible = "ti,omap2-nand"; - reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ - <1 IRQ_TYPE_NONE>; /* termcount */ - nand-bus-width = <16>; - ti,nand-ecc-opt = "sw"; - - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <44>; - gpmc,cs-wr-off-ns = <44>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <34>; - gpmc,adv-wr-off-ns = <44>; - gpmc,we-off-ns = <40>; - gpmc,oe-off-ns = <54>; - gpmc,access-ns = <64>; - gpmc,rd-cycle-ns = <82>; - gpmc,wr-cycle-ns = <82>; - gpmc,wr-access-ns = <40>; - gpmc,wr-data-mux-bus-ns = <0>; - gpmc,device-width = <2>; - - #address-cells = <1>; - #size-cells = <1>; - - /* u-boot uses mtdparts=nand:512k(xloader),1920k(uboot),128k(uboot-env),10m(boot),-(rootfs) */ - - x-loader@0 { - label = "xloader"; - reg = <0 0x80000>; - }; - - bootloaders@80000 { - label = "uboot"; - reg = <0x80000 0x1e0000>; - }; - - bootloaders_env@260000 { - label = "uboot-env"; - reg = <0x260000 0x20000>; - }; - - kernel@280000 { - label = "boot"; - reg = <0x280000 0xa00000>; - }; - - filesystem@c80000 { - label = "rootfs"; - reg = <0xc80000 0>; /* 0 = MTDPART_SIZ_FULL */ - }; - }; -}; - -&mcspi1 { - tsc2046@0 { - reg = <0>; /* CS0 */ - compatible = "ti,tsc2046"; - spi-max-frequency = <1000000>; - pinctrl-names = "default"; - pinctrl-0 = <&penirq_pins>; - interrupt-parent = <&gpio3>; - interrupts = <30 IRQ_TYPE_NONE>; /* GPIO_94 */ - pendown-gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>; - vcc-supply = <&vaux4>; - - ti,x-min = /bits/ 16 <0>; - ti,x-max = /bits/ 16 <8000>; - ti,y-min = /bits/ 16 <0>; - ti,y-max = /bits/ 16 <4800>; - ti,x-plate-ohms = /bits/ 16 <40>; - ti,pressure-max = /bits/ 16 <255>; - - wakeup-source; - }; - - lcd: lcd@1 { - reg = <1>; /* CS1 */ - compatible = "tpo,td043mtea1"; - spi-max-frequency = <100000>; - spi-cpol; - spi-cpha; - - label = "lcd"; - reset-gpios = <&gpio5 29 GPIO_ACTIVE_LOW>; /* GPIO_157 */ - vcc-supply = <&vaux1>; - - port { - lcd_in: endpoint { - remote-endpoint = <&dpi_out>; - }; - }; - }; - - -}; - -/* n/a - used as GPIOs */ -&mcbsp1 { -}; - -/* audio DAC */ -&mcbsp2 { -}; - -/* bluetooth */ -&mcbsp3 { -}; - -/* to twl4030*/ -&mcbsp4 { -}; - -&venc { - status = "ok"; - - vdda-supply = <&vdac>; - - port { - venc_out: endpoint { - remote-endpoint = <&tv_connector_in>; - ti,channels = <2>; - }; - }; -}; - -&dss { - pinctrl-names = "default"; - pinctrl-0 = < &dss_dpi_pins >; - - status = "ok"; - vdds_dsi-supply = <&vpll2>; - - port { - dpi_out: endpoint { - remote-endpoint = <&lcd_in>; - data-lines = <24>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/omap3-panel-sharp-ls037v7dw01.dtsi b/sys/gnu/dts/arm/omap3-panel-sharp-ls037v7dw01.dtsi deleted file mode 100644 index b8b9fcc41ef..00000000000 --- a/sys/gnu/dts/arm/omap3-panel-sharp-ls037v7dw01.dtsi +++ /dev/null @@ -1,73 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Common file for omap dpi panels with QVGA and reset pins - * - * Note that the board specifc DTS file needs to specify - * at minimum the GPIO enable-gpios for display, and - * gpios for gpio-backlight. - */ - -/ { - aliases { - display0 = &lcd0; - }; - - backlight0: backlight { - compatible = "gpio-backlight"; - default-on; - }; - - /* 3.3V GPIO controlled regulator for LCD_ENVDD */ - lcd_3v3: regulator-lcd-3v3 { - compatible = "regulator-fixed"; - regulator-name = "lcd_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <70000>; - }; - - lcd0: display { - compatible = "sharp,ls037v7dw01"; - label = "lcd"; - power-supply = <&lcd_3v3>; - envdd-supply = <&lcd_3v3>; - - port { - lcd_in: endpoint { - remote-endpoint = <&dpi_out>; - }; - }; - }; -}; - -/* Needed to power the DPI pins */ -&vpll2 { - regulator-always-on; -}; - -&dss { - status = "ok"; - port { - dpi_out: endpoint { - remote-endpoint = <&lcd_in>; - data-lines = <18>; - }; - }; -}; - -&mcspi1 { - tsc2046@0 { - reg = <0>; /* CS0 */ - compatible = "ti,tsc2046"; - spi-max-frequency = <1000000>; - vcc-supply = <&lcd_3v3>; - ti,x-min = /bits/ 16 <0>; - ti,x-max = /bits/ 16 <8000>; - ti,y-min = /bits/ 16 <0>; - ti,y-max = /bits/ 16 <4800>; - ti,x-plate-ohms = /bits/ 16 <40>; - ti,pressure-max = /bits/ 16 <255>; - ti,swap-xy; - wakeup-source; - }; -}; diff --git a/sys/gnu/dts/arm/omap3-sb-t35.dtsi b/sys/gnu/dts/arm/omap3-sb-t35.dtsi deleted file mode 100644 index fb9842fa922..00000000000 --- a/sys/gnu/dts/arm/omap3-sb-t35.dtsi +++ /dev/null @@ -1,138 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Common support for CompuLab SB-T35 used on SBC-T3530, SBC-T3517 and SBC-T3730 - */ - -/ { - tfp410: encoder { - compatible = "ti,tfp410"; - - powerdown-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>; /* gpio_54 */ - - pinctrl-names = "default"; - pinctrl-0 = <&tfp410_pins>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - tfp410_in: endpoint { - remote-endpoint = <&dpi_out>; - }; - }; - - port@1 { - reg = <1>; - - tfp410_out: endpoint { - remote-endpoint = <&dvi_connector_in>; - }; - }; - }; - }; - - dvi0: dvi-connector { - compatible = "dvi-connector"; - label = "dvi"; - - port { - dvi_connector_in: endpoint { - remote-endpoint = <&tfp410_out>; - }; - }; - }; - - audio_amp: audio_amp { - compatible = "regulator-fixed"; - regulator-name = "audio_amp"; - pinctrl-names = "default"; - pinctrl-0 = <&sb_t35_audio_amp>; - gpio = <&gpio2 29 GPIO_ACTIVE_LOW>; /* gpio_61 */ - regulator-always-on; - }; -}; - -&omap3_pmx_core { - smsc2_pins: pinmux_smsc2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20b6, PIN_OUTPUT | MUX_MODE0) /* gpmc_ncs4.gpmc_ncs4 */ - OMAP3_CORE1_IOPAD(0x20d2, PIN_INPUT_PULLUP | MUX_MODE4) /* gpmc_wait3.gpio_65 */ - >; - }; - - tfp410_pins: pinmux_tfp410_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20b4, PIN_OUTPUT | MUX_MODE4) /* gpmc_ncs3.gpio_54 */ - >; - }; - - i2c3_pins: pinmux_i2c3_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl */ - OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda */ - >; - }; - - sb_t35_audio_amp: pinmux_sb_t35_audio_amp { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20c8, PIN_OUTPUT | MUX_MODE4) /* gpmc_nbe1.gpio_61 */ - >; - }; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_pins>; - - clock-frequency = <400000>; - - at24@50 { - compatible = "atmel,24c02"; - pagesize = <16>; - reg = <0x50>; - }; -}; - -&gpmc { - ranges = <4 0 0x2d000000 0x01000000>; - - smsc2: ethernet@4,0 { - compatible = "smsc,lan9221", "smsc,lan9115"; - pinctrl-names = "default"; - pinctrl-0 = <&smsc2_pins>; - interrupt-parent = <&gpio3>; - interrupts = <1 IRQ_TYPE_LEVEL_LOW>; - reg = <4 0 0xff>; - bank-width = <2>; - gpmc,device-width = <1>; - gpmc,cycle2cycle-samecsen = <1>; - gpmc,cycle2cycle-diffcsen = <1>; - gpmc,cs-on-ns = <5>; - gpmc,cs-rd-off-ns = <150>; - gpmc,cs-wr-off-ns = <150>; - gpmc,adv-on-ns = <0>; - gpmc,adv-rd-off-ns = <15>; - gpmc,adv-wr-off-ns = <40>; - gpmc,oe-on-ns = <45>; - gpmc,oe-off-ns = <140>; - gpmc,we-on-ns = <45>; - gpmc,we-off-ns = <140>; - gpmc,rd-cycle-ns = <155>; - gpmc,wr-cycle-ns = <155>; - gpmc,access-ns = <120>; - gpmc,page-burst-access-ns = <20>; - gpmc,bus-turnaround-ns = <75>; - gpmc,cycle2cycle-delay-ns = <75>; - gpmc,wait-monitoring-ns = <0>; - gpmc,clk-activation-ns = <0>; - gpmc,wr-data-mux-bus-ns = <0>; - gpmc,wr-access-ns = <0>; - vddvario-supply = <&vddvario>; - vdd33a-supply = <&vdd33a>; - reg-io-width = <4>; - smsc,save-mac-address; - }; -}; diff --git a/sys/gnu/dts/arm/omap3-sbc-t3517.dts b/sys/gnu/dts/arm/omap3-sbc-t3517.dts deleted file mode 100644 index a69d3286042..00000000000 --- a/sys/gnu/dts/arm/omap3-sbc-t3517.dts +++ /dev/null @@ -1,76 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Suppport for CompuLab SBC-T3517 with CM-T3517 - */ - -#include "omap3-cm-t3517.dts" -#include "omap3-sb-t35.dtsi" - -/ { - model = "CompuLab SBC-T3517 with CM-T3517"; - compatible = "compulab,omap3-sbc-t3517", "compulab,omap3-cm-t3517", "ti,am3517", "ti,omap3"; - - aliases { - display0 = &dvi0; - display1 = &tv0; - }; - - /* Only one GPMC smsc9220 on SBC-T3517, CM-T3517 uses am35x Ethernet */ - vddvario: regulator-vddvario-sb-t35 { - compatible = "regulator-fixed"; - regulator-name = "vddvario"; - regulator-always-on; - }; - - vdd33a: regulator-vdd33a-sb-t35 { - compatible = "regulator-fixed"; - regulator-name = "vdd33a"; - regulator-always-on; - }; -}; - -&omap3_pmx_core { - pinctrl-names = "default"; - pinctrl-0 = < - &sb_t35_usb_hub_pins - &usb_hub_pins - >; - - mmc1_aux_pins: pinmux_mmc1_aux_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20c0, PIN_INPUT_PULLUP | MUX_MODE4) /* gpmc_clk.gpio_59 */ - OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT_PULLUP | MUX_MODE4) /* uart2_cts.gpio_144 */ - >; - }; - - sb_t35_usb_hub_pins: pinmux_sb_t35_usb_hub_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21ec, PIN_OUTPUT | MUX_MODE4) /* ccdc_wen.gpio_98 - SB-T35 USB HUB RST */ - >; - }; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = < - &mmc1_pins - &mmc1_aux_pins - >; - - wp-gpios = <&gpio2 27 GPIO_ACTIVE_HIGH>; /* gpio_59 */ - cd-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>; /* gpio_144 */ -}; - -&dss { - port { - dpi_out: endpoint { - remote-endpoint = <&tfp410_in>; - data-lines = <24>; - }; - }; -}; - -&gpmc { - ranges = <4 0 0x2d000000 0x01000000>, /* SB-T35 SMSC9x Eth */ - <0 0 0x00000000 0x01000000>; /* CM-T3x NAND */ -}; diff --git a/sys/gnu/dts/arm/omap3-sbc-t3530.dts b/sys/gnu/dts/arm/omap3-sbc-t3530.dts deleted file mode 100644 index ae96002abb3..00000000000 --- a/sys/gnu/dts/arm/omap3-sbc-t3530.dts +++ /dev/null @@ -1,48 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Suppport for CompuLab SBC-T3530 with CM-T3530 - */ - -#include "omap3-cm-t3530.dts" -#include "omap3-sb-t35.dtsi" - -/ { - model = "CompuLab SBC-T3530 with CM-T3530"; - compatible = "compulab,omap3-sbc-t3530", "compulab,omap3-cm-t3530", "ti,omap34xx", "ti,omap3"; - - aliases { - display0 = &dvi0; - display1 = &tv0; - }; -}; - -&omap3_pmx_core { - pinctrl-names = "default"; - pinctrl-0 = <&sb_t35_usb_hub_pins>; - - sb_t35_usb_hub_pins: pinmux_sb_t35_usb_hub_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2130, PIN_OUTPUT | MUX_MODE4) /* ccdc_wen.gpio_167 - SB-T35 USB HUB RST */ - >; - }; -}; - -&gpmc { - ranges = <5 0 0x2c000000 0x01000000>, /* CM-T3x30 SMSC9x Eth */ - <4 0 0x2d000000 0x01000000>, /* SB-T35 SMSC9x Eth */ - <0 0 0x00000000 0x01000000>; /* CM-T3x NAND */ -}; - -&mmc1 { - cd-gpios = <&twl_gpio 0 GPIO_ACTIVE_HIGH>; -}; - -&dss { - port { - dpi_out: endpoint { - remote-endpoint = <&tfp410_in>; - data-lines = <24>; - }; - }; -}; - diff --git a/sys/gnu/dts/arm/omap3-sbc-t3730.dts b/sys/gnu/dts/arm/omap3-sbc-t3730.dts deleted file mode 100644 index 7de6df16fc1..00000000000 --- a/sys/gnu/dts/arm/omap3-sbc-t3730.dts +++ /dev/null @@ -1,44 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Suppport for CompuLab SBC-T3730 with CM-T3730 - */ - -#include "omap3-cm-t3730.dts" -#include "omap3-sb-t35.dtsi" - -/ { - model = "CompuLab SBC-T3730 with CM-T3730"; - compatible = "compulab,omap3-sbc-t3730", "compulab,omap3-cm-t3730", "ti,omap36xx", "ti,omap3"; - - aliases { - display0 = &dvi0; - display1 = &tv0; - }; -}; - -&omap3_pmx_core { - pinctrl-names = "default"; - pinctrl-0 = <&sb_t35_usb_hub_pins>; - - sb_t35_usb_hub_pins: pinmux_sb_t35_usb_hub_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2130, PIN_OUTPUT | MUX_MODE4) /* ccdc_wen.gpio_167 - SB-T35 USB HUB RST */ - >; - }; -}; - -&gpmc { - ranges = <5 0 0x2c000000 0x01000000>, /* CM-T3x30 SMSC9x Eth */ - <4 0 0x2d000000 0x01000000>, /* SB-T35 SMSC9x Eth */ - <0 0 0x00000000 0x01000000>; /* CM-T3x NAND */ -}; - -&dss { - port { - dpi_out: endpoint { - remote-endpoint = <&tfp410_in>; - data-lines = <24>; - }; - }; -}; - diff --git a/sys/gnu/dts/arm/omap3-sniper.dts b/sys/gnu/dts/arm/omap3-sniper.dts deleted file mode 100644 index 40a87330e8c..00000000000 --- a/sys/gnu/dts/arm/omap3-sniper.dts +++ /dev/null @@ -1,251 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2015-2016 Paul Kocialkowski - */ -/dts-v1/; - -#include "omap36xx.dtsi" -#include - -/ { - model = "LG Optimus Black"; - compatible = "lg,omap3-sniper", "ti,omap36xx", "ti,omap3"; - - cpus { - cpu@0 { - cpu0-supply = <&vcc>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000>; /* 512 MB */ - }; -}; - -&omap3_pmx_core { - pinctrl-names = "default"; - - uart3_pins: pinmux_uart3_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx */ - OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx */ - >; - }; - - dp3t_sel_pins: pinmux_dp3t_sel_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2196, PIN_OUTPUT | MUX_MODE4) /* gpio_161 */ - OMAP3_CORE1_IOPAD(0x2198, PIN_OUTPUT | MUX_MODE4) /* gpio_162 */ - >; - }; - - i2c1_pins: pinmux_i2c1_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0) /* i2c1_scl */ - OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0) /* i2c1_sda */ - >; - }; - - i2c2_pins: pinmux_i2c2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT | MUX_MODE0) /* i2c2_scl */ - OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT | MUX_MODE0) /* i2c2_sda */ - >; - }; - - i2c3_pins: pinmux_i2c3_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl */ - OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda */ - >; - }; - - lp8720_en_pin: pinmux_lp8720_en_pin { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2080, PIN_OUTPUT | MUX_MODE4) /* gpio_37 */ - >; - }; - - mmc1_pins: pinmux_mmc1_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT | MUX_MODE0) /* sdmmc1_clk */ - OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT | MUX_MODE0) /* sdmmc1_cmd */ - OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat0 */ - OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat1 */ - OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat2 */ - OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat3 */ - >; - }; - - mmc2_pins: pinmux_mmc2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT | MUX_MODE0) /* sdmmc2_clk */ - OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT | MUX_MODE0) /* sdmmc2_cmd */ - OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat0 */ - OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat1 */ - OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat2 */ - OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat3 */ - OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat4 */ - OMAP3_CORE1_IOPAD(0x2166, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat5 */ - OMAP3_CORE1_IOPAD(0x2168, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat6 */ - OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat7 */ - >; - }; - - usb_otg_hs_pins: pinmux_usb_otg_hs_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21a2, PIN_INPUT | MUX_MODE0) /* hsusb0_clk */ - OMAP3_CORE1_IOPAD(0x21a4, PIN_OUTPUT | MUX_MODE0) /* hsusb0_stp */ - OMAP3_CORE1_IOPAD(0x21a6, PIN_INPUT | MUX_MODE0) /* hsusb0_dir */ - OMAP3_CORE1_IOPAD(0x21a8, PIN_INPUT | MUX_MODE0) /* hsusb0_nxt */ - OMAP3_CORE1_IOPAD(0x21aa, PIN_INPUT | MUX_MODE0) /* hsusb0_data0 */ - OMAP3_CORE1_IOPAD(0x21ac, PIN_INPUT | MUX_MODE0) /* hsusb0_data1 */ - OMAP3_CORE1_IOPAD(0x21ae, PIN_INPUT | MUX_MODE0) /* hsusb0_data2 */ - OMAP3_CORE1_IOPAD(0x21b0, PIN_INPUT | MUX_MODE0) /* hsusb0_data3 */ - OMAP3_CORE1_IOPAD(0x21b2, PIN_INPUT | MUX_MODE0) /* hsusb0_data4 */ - OMAP3_CORE1_IOPAD(0x21b4, PIN_INPUT | MUX_MODE0) /* hsusb0_data5 */ - OMAP3_CORE1_IOPAD(0x21b6, PIN_INPUT | MUX_MODE0) /* hsusb0_data6 */ - OMAP3_CORE1_IOPAD(0x21b8, PIN_INPUT | MUX_MODE0) /* hsusb0_data7 */ - >; - }; -}; - -&omap3_pmx_wkup { - pinctrl-names = "default"; - - mmc1_cd_pin: pinmux_mmc1_cd_pin { - pinctrl-single,pins = < - OMAP3_WKUP_IOPAD(0x2a1a, PIN_INPUT | MUX_MODE4) /* gpio_10 */ - >; - }; -}; - -&gpio2 { - ti,no-reset-on-init; -}; - -&gpio5 { - ti,no-reset-on-init; -}; - -&gpio6 { - ti,no-reset-on-init; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins &dp3t_sel_pins>; - - interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - - clock-frequency = <2600000>; - - twl: twl@48 { - reg = <0x48>; - interrupts = <7>; /* SYS_NIRQ cascaded to intc */ - interrupt-parent = <&intc>; - - power { - compatible = "ti,twl4030-power"; - ti,use_poweroff; - }; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - - clock-frequency = <400000>; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_pins>; - - clock-frequency = <400000>; - - lp8720@7d { - pinctrl-names = "default"; - pinctrl-0 = <&lp8720_en_pin>; - - compatible = "ti,lp8720"; - reg = <0x7d>; - - enable-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; /* gpio_37 */ - - lp8720_ldo1: ldo1 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - }; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins &mmc1_cd_pin>; - - vmmc-supply = <&lp8720_ldo1>; - cd-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; /* gpio 10 */ - bus-width = <4>; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; - - vmmc-supply = <&vmmc2>; - ti,non-removable; - bus-width = <8>; -}; - -&mmc3 { - status = "disabled"; -}; - -&usb_otg_hs { - pinctrl-names = "default"; - pinctrl-0 = <&usb_otg_hs_pins>; - - interface-type = <0>; - usb-phy = <&usb2_phy>; - phys = <&usb2_phy>; - phy-names = "usb2-phy"; - mode = <3>; - power = <50>; -}; - -#include "twl4030.dtsi" -#include "twl4030_omap3.dtsi" - -&twl_keypad { - linux,keymap = < - MATRIX_KEY(0x00, 0x00, KEY_VOLUMEUP) - MATRIX_KEY(0x01, 0x00, KEY_VOLUMEDOWN) - MATRIX_KEY(0x02, 0x00, KEY_SELECT) - >; -}; - -/* - * The TWL4030 VAUX2 and VDAC regulators power sensors that are slaves on I2C3. - * When not powered, these sensors cause the I2C3 clock to stay low at all times, - * making it impossible to reach other devices on I2C3. - */ - -&vaux2 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; -}; - -&vdac { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; -}; diff --git a/sys/gnu/dts/arm/omap3-tao3530.dtsi b/sys/gnu/dts/arm/omap3-tao3530.dtsi deleted file mode 100644 index a7a04d78dee..00000000000 --- a/sys/gnu/dts/arm/omap3-tao3530.dtsi +++ /dev/null @@ -1,346 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ - * Copyright (C) 2014 Stefan Roese - */ -/dts-v1/; - -#include "omap34xx.dtsi" - -/* Secure omaps have some devices inaccessible depending on the firmware */ -&aes { - status = "disabled"; -}; - -&sham { - status = "disabled"; -}; - -/ { - cpus { - cpu@0 { - cpu0-supply = <&vcc>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x10000000>; /* 256 MB */ - }; - - /* HS USB Port 2 Power */ - hsusb2_power: hsusb2_power_reg { - compatible = "regulator-fixed"; - regulator-name = "hsusb2_vbus"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&twl_gpio 18 GPIO_ACTIVE_HIGH>; /* GPIO LEDA */ - startup-delay-us = <70000>; - }; - - /* HS USB Host PHY on PORT 2 */ - hsusb2_phy: hsusb2_phy { - compatible = "usb-nop-xceiv"; - reset-gpios = <&gpio6 2 GPIO_ACTIVE_LOW>; /* gpio_162 */ - vcc-supply = <&hsusb2_power>; - #phy-cells = <0>; - }; - - sound { - compatible = "ti,omap-twl4030"; - ti,model = "omap3beagle"; - - /* McBSP2 is used for onboard sound, same as on beagle */ - ti,mcbsp = <&mcbsp2>; - }; - - /* Regulator to enable/switch the vcc of the Wifi module */ - mmc2_sdio_poweron: regulator-mmc2-sdio-poweron { - compatible = "regulator-fixed"; - regulator-name = "regulator-mmc2-sdio-poweron"; - regulator-min-microvolt = <3150000>; - regulator-max-microvolt = <3150000>; - gpio = <&gpio5 29 GPIO_ACTIVE_LOW>; /* gpio_157 */ - startup-delay-us = <10000>; - }; -}; - -&omap3_pmx_core { - hsusbb2_pins: pinmux_hsusbb2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ - OMAP3_CORE1_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ - OMAP3_CORE1_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ - OMAP3_CORE1_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ - OMAP3_CORE1_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ - OMAP3_CORE1_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ - OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */ - OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */ - OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */ - OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */ - OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */ - OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */ - >; - }; - - mmc1_pins: pinmux_mmc1_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ - OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ - OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ - OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ - OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ - OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ - OMAP3_CORE1_IOPAD(0x2150, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat4.sdmmc1_dat4 */ - OMAP3_CORE1_IOPAD(0x2152, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat5.sdmmc1_dat5 */ - OMAP3_CORE1_IOPAD(0x2154, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat6.sdmmc1_dat6 */ - OMAP3_CORE1_IOPAD(0x2156, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat7.sdmmc1_dat7 */ - >; - }; - - mmc2_pins: pinmux_mmc2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ - OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ - OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ - OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ - OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ - OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ - >; - }; - - /* wlan GPIO output for WLAN_EN */ - wlan_gpio: pinmux_wlan_gpio { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x218e, PIN_OUTPUT | MUX_MODE4) /* mcbsp1_fsr gpio_157 */ - >; - }; - - uart3_pins: pinmux_uart3_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ - OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ - >; - }; - - i2c3_pins: pinmux_i2c3_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl.i2c3_scl */ - OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda.i2c3_sda */ - >; - }; - - mcspi1_pins: pinmux_mcspi1_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */ - OMAP3_CORE1_IOPAD(0x21ca, PIN_OUTPUT | MUX_MODE0) /* mcspi1_simo.mcspi1_simo */ - OMAP3_CORE1_IOPAD(0x21cc, PIN_INPUT_PULLUP | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */ - OMAP3_CORE1_IOPAD(0x21ce, PIN_OUTPUT | MUX_MODE0) /* mcspi1_cs0.mcspi1_cs0 */ - >; - }; - - mcspi3_pins: pinmux_mcspi3_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x25dc, PIN_OUTPUT | MUX_MODE1) /* etk_d0.mcspi3_simo gpio14 INPUT | MODE1 */ - OMAP3_CORE1_IOPAD(0x25de, PIN_INPUT_PULLUP | MUX_MODE1) /* etk_d1.mcspi3_somi gpio15 INPUT | MODE1 */ - OMAP3_CORE1_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE1) /* etk_d2.mcspi3_cs0 gpio16 INPUT | MODE1 */ - OMAP3_CORE1_IOPAD(0x25e2, PIN_INPUT | MUX_MODE1) /* etk_d3.mcspi3_clk gpio17 INPUT | MODE1 */ - >; - }; - - mcbsp3_pins: pinmux_mcbsp3_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x216c, PIN_OUTPUT | MUX_MODE0) /* mcbsp3_dx.uart2_cts */ - OMAP3_CORE1_IOPAD(0x216e, PIN_INPUT | MUX_MODE0) /* mcbsp3_dr.uart2_rts */ - OMAP3_CORE1_IOPAD(0x2170, PIN_INPUT | MUX_MODE0) /* mcbsp3_clk.uart2_tx */ - OMAP3_CORE1_IOPAD(0x2172, PIN_INPUT | MUX_MODE0) /* mcbsp3_fsx.uart2_rx */ - >; - }; -}; - -/* McBSP1: mux'ed with GPIO158 as clock for HA-DSP */ -&mcbsp1 { - status = "disabled"; -}; - -&mcbsp2 { - status = "okay"; -}; - -&i2c1 { - clock-frequency = <2600000>; - - twl: twl@48 { - reg = <0x48>; - interrupts = <7>; /* SYS_NIRQ cascaded to intc */ - interrupt-parent = <&intc>; - - twl_audio: audio { - compatible = "ti,twl4030-audio"; - codec { - }; - }; - }; -}; - -&i2c3 { - clock-frequency = <100000>; - - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_pins>; -}; - -&mcspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&mcspi1_pins>; - - spidev@0 { - compatible = "spidev"; - spi-max-frequency = <48000000>; - reg = <0>; - spi-cpha; - }; -}; - -&mcspi3 { - pinctrl-names = "default"; - pinctrl-0 = <&mcspi3_pins>; - - spidev@0 { - compatible = "spidev"; - spi-max-frequency = <48000000>; - reg = <0>; - spi-cpha; - }; -}; - -#include "twl4030.dtsi" -#include "twl4030_omap3.dtsi" - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - vmmc-supply = <&vmmc1>; - vqmmc-supply = <&vsim>; - cd-gpios = <&twl_gpio 0 GPIO_ACTIVE_HIGH>; - bus-width = <8>; -}; - -// WiFi (Marvell 88W8686) on MMC2/SDIO -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; - vmmc-supply = <&mmc2_sdio_poweron>; - non-removable; - bus-width = <4>; - cap-power-off-card; -}; - -&mmc3 { - status = "disabled"; -}; - -&usbhshost { - port2-mode = "ehci-phy"; -}; - -&usbhsehci { - phys = <0 &hsusb2_phy>; -}; - -&twl_gpio { - ti,use-leds; - /* pullups: BIT(1) */ - ti,pullups = <0x000002>; - /* - * pulldowns: - * BIT(2), BIT(6), BIT(7), BIT(8), BIT(13) - * BIT(15), BIT(16), BIT(17) - */ - ti,pulldowns = <0x03a1c4>; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; -}; - -&mcbsp3 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mcbsp3_pins>; -}; - -&gpmc { - ranges = <0 0 0x30000000 0x01000000>; /* CS0: 16MB for NAND */ - - nand@0,0 { - compatible = "ti,omap2-nand"; - reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ - <1 IRQ_TYPE_NONE>; /* termcount */ - nand-bus-width = <16>; - gpmc,device-width = <2>; /* GPMC_DEVWIDTH_16BIT */ - ti,nand-ecc-opt = "sw"; - - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <36>; - gpmc,cs-wr-off-ns = <36>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <24>; - gpmc,adv-wr-off-ns = <36>; - gpmc,oe-on-ns = <6>; - gpmc,oe-off-ns = <48>; - gpmc,we-on-ns = <6>; - gpmc,we-off-ns = <30>; - gpmc,rd-cycle-ns = <72>; - gpmc,wr-cycle-ns = <72>; - gpmc,access-ns = <54>; - gpmc,wr-access-ns = <30>; - - #address-cells = <1>; - #size-cells = <1>; - - x-loader@0 { - label = "X-Loader"; - reg = <0 0x80000>; - }; - - bootloaders@80000 { - label = "U-Boot"; - reg = <0x80000 0x1e0000>; - }; - - bootloaders_env@260000 { - label = "U-Boot Env"; - reg = <0x260000 0x20000>; - }; - - kernel@280000 { - label = "Kernel"; - reg = <0x280000 0x400000>; - }; - - filesystem@680000 { - label = "File System"; - reg = <0x680000 0xf980000>; - }; - }; -}; - -&usb_otg_hs { - interface-type = <0>; - usb-phy = <&usb2_phy>; - phys = <&usb2_phy>; - phy-names = "usb2-phy"; - mode = <3>; - power = <50>; -}; - -&vaux2 { - regulator-name = "vdd_ehci"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; -}; diff --git a/sys/gnu/dts/arm/omap3-thunder.dts b/sys/gnu/dts/arm/omap3-thunder.dts deleted file mode 100644 index 6276e7079b3..00000000000 --- a/sys/gnu/dts/arm/omap3-thunder.dts +++ /dev/null @@ -1,126 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ - * Copyright (C) 2014 Stefan Roese - */ - -#include "omap3-tao3530.dtsi" - -/ { - model = "TI OMAP3 Thunder baseboard with TAO3530 SOM"; - compatible = "technexion,omap3-thunder", "technexion,omap3-tao3530", "ti,omap34xx", "ti,omap3"; -}; - -&omap3_pmx_core { - dss_dpi_pins: pinmux_dss_dpi_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ - OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ - OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ - OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ - OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ - OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ - OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ - OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ - OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ - OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ - OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ - OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ - OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ - OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ - OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ - OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ - OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ - OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ - OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ - OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ - OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ - OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ - OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */ - OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */ - OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */ - OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */ - OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ - OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ - >; - }; - - lte430_pins: pinmux_lte430_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat6.gpio_138 */ - >; - }; - - backlight_pins: pinmux_backlight_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x216a, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat7.gpio_139 */ - >; - }; -}; - -/* Needed to power the DPI pins */ -&vpll2 { - regulator-always-on; -}; - -&dss { - status = "ok"; - - pinctrl-names = "default"; - pinctrl-0 = <&dss_dpi_pins>; - - port { - dpi_out: endpoint { - remote-endpoint = <&lcd_in>; - data-lines = <24>; - }; - }; -}; - -/ { - aliases { - display0 = &lcd0; - }; - - lcd0: display { - compatible = "samsung,lte430wq-f0c", "panel-dpi"; - label = "lcd"; - - pinctrl-names = "default"; - pinctrl-0 = <<e430_pins>; - enable-gpios = <&gpio5 10 GPIO_ACTIVE_LOW>; /* gpio_138 */ - - port { - lcd_in: endpoint { - remote-endpoint = <&dpi_out>; - }; - }; - - panel-timing { - clock-frequency = <9000000>; - hactive = <480>; - vactive = <272>; - hfront-porch = <3>; - hback-porch = <2>; - hsync-len = <42>; - vback-porch = <2>; - vfront-porch = <3>; - vsync-len = <11>; - - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - - backlight { - compatible = "gpio-backlight"; - - pinctrl-names = "default"; - pinctrl-0 = <&backlight_pins>; - gpios = <&gpio5 11 GPIO_ACTIVE_HIGH>; /* gpio_139 */ - - default-on; - }; -}; diff --git a/sys/gnu/dts/arm/omap3-zoom3.dts b/sys/gnu/dts/arm/omap3-zoom3.dts deleted file mode 100644 index db3a2fe84e9..00000000000 --- a/sys/gnu/dts/arm/omap3-zoom3.dts +++ /dev/null @@ -1,231 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ - */ -/dts-v1/; - -#include "omap36xx.dtsi" -#include "omap-zoom-common.dtsi" - -/ { - model = "TI Zoom3"; - compatible = "ti,omap3-zoom3", "ti,omap36xx", "ti,omap3"; - - cpus { - cpu@0 { - cpu0-supply = <&vcc>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000>; /* 512 MB */ - }; - - vddvario: regulator-vddvario { - compatible = "regulator-fixed"; - regulator-name = "vddvario"; - regulator-always-on; - }; - - vdd33a: regulator-vdd33a { - compatible = "regulator-fixed"; - regulator-name = "vdd33a"; - regulator-always-on; - }; - - wl12xx_vmmc: wl12xx_vmmc { - pinctrl-names = "default"; - pinctrl-0 = <&wl12xx_gpio>; - compatible = "regulator-fixed"; - regulator-name = "vwl1271"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio4 5 GPIO_ACTIVE_HIGH>; /* gpio101 */ - startup-delay-us = <70000>; - enable-active-high; - }; -}; - -&omap3_pmx_core { - /* REVISIT: twl gpio0 is mmc0_cd */ - mmc1_pins: pinmux_mmc1_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2144, PIN_OUTPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ - OMAP3_CORE1_IOPAD(0x2146, PIN_OUTPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ - OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ - OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ - OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ - OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ - >; - }; - - mmc2_pins: pinmux_mmc2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ - OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ - OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ - OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ - OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ - OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ - OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat4.sdmmc2_dat4 */ - OMAP3_CORE1_IOPAD(0x2166, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat5.sdmmc2_dat5 */ - OMAP3_CORE1_IOPAD(0x2168, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat6.sdmmc2_dat6 */ - OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat7.sdmmc2_dat7 */ - >; - }; - - mmc3_pins: pinmux_mmc3_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2198, PIN_INPUT | MUX_MODE4) /* mcbsp1_clkx.gpio_162 WLAN IRQ */ - OMAP3_CORE1_IOPAD(0x21d0, PIN_INPUT_PULLUP | MUX_MODE3) /* mcspi1_cs1.sdmmc3_cmd */ - >; - }; - - uart1_pins: pinmux_uart1_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT | MUX_MODE0) /* uart1_cts.uart1_cts */ - OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE0) /* uart1_rts.uart1_rts */ - OMAP3_CORE1_IOPAD(0x2182, WAKEUP_EN | PIN_INPUT | MUX_MODE0) /* uart1_rx.uart1_rx */ - OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE0) /* uart1_tx.uart1_tx */ - >; - }; - - uart2_pins: pinmux_uart2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts.uart2_cts */ - OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts.uart2_rts */ - OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */ - OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ - >; - }; - - uart3_pins: pinmux_uart3_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x219a, PIN_INPUT_PULLDOWN | MUX_MODE0) /* uart3_cts_rctx.uart3_cts_rctx */ - OMAP3_CORE1_IOPAD(0x219c, PIN_OUTPUT | MUX_MODE0) /* uart3_rts_sd.uart3_rts_sd */ - OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ - OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ - >; - }; - - /* wl12xx GPIO output for WLAN_EN */ - wl12xx_gpio: pinmux_wl12xx_gpio { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x211a, PIN_OUTPUT| MUX_MODE4) /* cam_d2.gpio_101 */ - >; - }; -}; - -&omap3_pmx_core2 { - mmc3_2_pins: pinmux_mmc3_2_pins { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25d8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_clk.sdmmc3_clk */ - OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d4.sdmmc3_dat0 */ - OMAP3630_CORE2_IOPAD(0x25e6, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d5.sdmmc3_dat1 */ - OMAP3630_CORE2_IOPAD(0x25e8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d6.sdmmc3_dat2 */ - OMAP3630_CORE2_IOPAD(0x25e2, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d3.sdmmc3_dat3 */ - >; - }; -}; - -&omap3_pmx_wkup { - wlan_host_wkup: pinmux_wlan_host_wkup_pins { - pinctrl-single,pins = < - OMAP3_WKUP_IOPAD(0x2a1a, PIN_INPUT_PULLUP | MUX_MODE4) /* sys_clkout1.gpio_10 WLAN_HOST_WKUP */ - >; - }; -}; - -&i2c1 { - clock-frequency = <2600000>; - - twl: twl@48 { - reg = <0x48>; - interrupts = <7>; /* SYS_NIRQ cascaded to intc */ - interrupt-parent = <&intc>; - }; -}; - -#include "twl4030.dtsi" - -&i2c2 { - clock-frequency = <400000>; -}; - -&i2c3 { - clock-frequency = <400000>; - - /* - * TVP5146 Video decoder-in for analog input support. - */ - tvp5146@5c { - compatible = "ti,tvp5146m2"; - reg = <0x5c>; - }; -}; - -&twl_gpio { - ti,use-leds; -}; - -&mmc1 { - vmmc-supply = <&vmmc1>; - vqmmc-supply = <&vsim>; - bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; -}; -/* -&mmc2 { - vmmc-supply = <&vmmc2>; - ti,non-removable; - bus-width = <8>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; -}; -*/ -&mmc3 { - vmmc-supply = <&wl12xx_vmmc>; - non-removable; - bus-width = <4>; - cap-power-off-card; - pinctrl-names = "default"; - pinctrl-0 = <&mmc3_pins &mmc3_2_pins>; - - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@2 { - compatible = "ti,wl1271"; - reg = <2>; - interrupt-parent = <&gpio6>; - interrupts = <2 IRQ_TYPE_EDGE_RISING>; /* gpio 162 */ - ref-clock-frequency = <26000000>; - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; -}; - -&uart4 { - status = "disabled"; -}; - -&usb_otg_hs { - interface-type = <0>; - usb-phy = <&usb2_phy>; - mode = <3>; - power = <50>; -}; diff --git a/sys/gnu/dts/arm/omap3.dtsi b/sys/gnu/dts/arm/omap3.dtsi deleted file mode 100644 index 4043ecb3801..00000000000 --- a/sys/gnu/dts/arm/omap3.dtsi +++ /dev/null @@ -1,840 +0,0 @@ -/* - * Device Tree Source for OMAP3 SoC - * - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -#include -#include -#include - -/ { - compatible = "ti,omap3430", "ti,omap3"; - interrupt-parent = <&intc>; - #address-cells = <1>; - #size-cells = <1>; - chosen { }; - - aliases { - i2c0 = &i2c1; - i2c1 = &i2c2; - i2c2 = &i2c3; - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "arm,cortex-a8"; - device_type = "cpu"; - reg = <0x0>; - - clocks = <&dpll1_ck>; - clock-names = "cpu"; - - clock-latency = <300000>; /* From omap-cpufreq driver */ - }; - }; - - pmu@54000000 { - compatible = "arm,cortex-a8-pmu"; - reg = <0x54000000 0x800000>; - interrupts = <3>; - ti,hwmods = "debugss"; - }; - - /* - * The soc node represents the soc top level view. It is used for IPs - * that are not memory mapped in the MPU view or for the MPU itself. - */ - soc { - compatible = "ti,omap-infra"; - mpu { - compatible = "ti,omap3-mpu"; - ti,hwmods = "mpu"; - }; - - iva: iva { - compatible = "ti,iva2.2"; - ti,hwmods = "iva"; - - dsp { - compatible = "ti,omap3-c64"; - }; - }; - }; - - /* - * XXX: Use a flat representation of the OMAP3 interconnect. - * The real OMAP interconnect network is quite complex. - * Since it will not bring real advantage to represent that in DT for - * the moment, just use a fake OCP bus entry to represent the whole bus - * hierarchy. - */ - ocp@68000000 { - compatible = "ti,omap3-l3-smx", "simple-bus"; - reg = <0x68000000 0x10000>; - interrupts = <9 10>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - ti,hwmods = "l3_main"; - - l4_core: l4@48000000 { - compatible = "ti,omap3-l4-core", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x48000000 0x1000000>; - - scm: scm@2000 { - compatible = "ti,omap3-scm", "simple-bus"; - reg = <0x2000 0x2000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x2000 0x2000>; - - omap3_pmx_core: pinmux@30 { - compatible = "ti,omap3-padconf", - "pinctrl-single"; - reg = <0x30 0x238>; - #address-cells = <1>; - #size-cells = <0>; - #pinctrl-cells = <1>; - #interrupt-cells = <1>; - interrupt-controller; - pinctrl-single,register-width = <16>; - pinctrl-single,function-mask = <0xff1f>; - }; - - scm_conf: scm_conf@270 { - compatible = "syscon", "simple-bus"; - reg = <0x270 0x330>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x270 0x330>; - - pbias_regulator: pbias_regulator@2b0 { - compatible = "ti,pbias-omap3", "ti,pbias-omap"; - reg = <0x2b0 0x4>; - syscon = <&scm_conf>; - pbias_mmc_reg: pbias_mmc_omap2430 { - regulator-name = "pbias_mmc_omap2430"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3000000>; - }; - }; - - scm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - scm_clockdomains: clockdomains { - }; - - omap3_pmx_wkup: pinmux@a00 { - compatible = "ti,omap3-padconf", - "pinctrl-single"; - reg = <0xa00 0x5c>; - #address-cells = <1>; - #size-cells = <0>; - #pinctrl-cells = <1>; - #interrupt-cells = <1>; - interrupt-controller; - pinctrl-single,register-width = <16>; - pinctrl-single,function-mask = <0xff1f>; - }; - }; - }; - - aes: aes@480c5000 { - compatible = "ti,omap3-aes"; - ti,hwmods = "aes"; - reg = <0x480c5000 0x50>; - interrupts = <0>; - dmas = <&sdma 65 &sdma 66>; - dma-names = "tx", "rx"; - }; - - prm: prm@48306000 { - compatible = "ti,omap3-prm"; - reg = <0x48306000 0x4000>; - interrupts = <11>; - - prm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - prm_clockdomains: clockdomains { - }; - }; - - cm: cm@48004000 { - compatible = "ti,omap3-cm"; - reg = <0x48004000 0x4000>; - - cm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - cm_clockdomains: clockdomains { - }; - }; - - counter32k: counter@48320000 { - compatible = "ti,omap-counter32k"; - reg = <0x48320000 0x20>; - ti,hwmods = "counter_32k"; - }; - - intc: interrupt-controller@48200000 { - compatible = "ti,omap3-intc"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x48200000 0x1000>; - }; - - sdma: dma-controller@48056000 { - compatible = "ti,omap3630-sdma", "ti,omap3430-sdma"; - reg = <0x48056000 0x1000>; - interrupts = <12>, - <13>, - <14>, - <15>; - #dma-cells = <1>; - dma-channels = <32>; - dma-requests = <96>; - ti,hwmods = "dma"; - }; - - gpio1: gpio@48310000 { - compatible = "ti,omap3-gpio"; - reg = <0x48310000 0x200>; - interrupts = <29>; - ti,hwmods = "gpio1"; - ti,gpio-always-on; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@49050000 { - compatible = "ti,omap3-gpio"; - reg = <0x49050000 0x200>; - interrupts = <30>; - ti,hwmods = "gpio2"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio@49052000 { - compatible = "ti,omap3-gpio"; - reg = <0x49052000 0x200>; - interrupts = <31>; - ti,hwmods = "gpio3"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio4: gpio@49054000 { - compatible = "ti,omap3-gpio"; - reg = <0x49054000 0x200>; - interrupts = <32>; - ti,hwmods = "gpio4"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio5: gpio@49056000 { - compatible = "ti,omap3-gpio"; - reg = <0x49056000 0x200>; - interrupts = <33>; - ti,hwmods = "gpio5"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio6: gpio@49058000 { - compatible = "ti,omap3-gpio"; - reg = <0x49058000 0x200>; - interrupts = <34>; - ti,hwmods = "gpio6"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - uart1: serial@4806a000 { - compatible = "ti,omap3-uart"; - reg = <0x4806a000 0x2000>; - interrupts-extended = <&intc 72>; - dmas = <&sdma 49 &sdma 50>; - dma-names = "tx", "rx"; - ti,hwmods = "uart1"; - clock-frequency = <48000000>; - }; - - uart2: serial@4806c000 { - compatible = "ti,omap3-uart"; - reg = <0x4806c000 0x400>; - interrupts-extended = <&intc 73>; - dmas = <&sdma 51 &sdma 52>; - dma-names = "tx", "rx"; - ti,hwmods = "uart2"; - clock-frequency = <48000000>; - }; - - uart3: serial@49020000 { - compatible = "ti,omap3-uart"; - reg = <0x49020000 0x400>; - interrupts-extended = <&intc 74>; - dmas = <&sdma 53 &sdma 54>; - dma-names = "tx", "rx"; - ti,hwmods = "uart3"; - clock-frequency = <48000000>; - }; - - i2c1: i2c@48070000 { - compatible = "ti,omap3-i2c"; - reg = <0x48070000 0x80>; - interrupts = <56>; - dmas = <&sdma 27 &sdma 28>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "i2c1"; - }; - - i2c2: i2c@48072000 { - compatible = "ti,omap3-i2c"; - reg = <0x48072000 0x80>; - interrupts = <57>; - dmas = <&sdma 29 &sdma 30>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "i2c2"; - }; - - i2c3: i2c@48060000 { - compatible = "ti,omap3-i2c"; - reg = <0x48060000 0x80>; - interrupts = <61>; - dmas = <&sdma 25 &sdma 26>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "i2c3"; - }; - - mailbox: mailbox@48094000 { - compatible = "ti,omap3-mailbox"; - ti,hwmods = "mailbox"; - reg = <0x48094000 0x200>; - interrupts = <26>; - #mbox-cells = <1>; - ti,mbox-num-users = <2>; - ti,mbox-num-fifos = <2>; - mbox_dsp: dsp { - ti,mbox-tx = <0 0 0>; - ti,mbox-rx = <1 0 0>; - }; - }; - - mcspi1: spi@48098000 { - compatible = "ti,omap2-mcspi"; - reg = <0x48098000 0x100>; - interrupts = <65>; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "mcspi1"; - ti,spi-num-cs = <4>; - dmas = <&sdma 35>, - <&sdma 36>, - <&sdma 37>, - <&sdma 38>, - <&sdma 39>, - <&sdma 40>, - <&sdma 41>, - <&sdma 42>; - dma-names = "tx0", "rx0", "tx1", "rx1", - "tx2", "rx2", "tx3", "rx3"; - }; - - mcspi2: spi@4809a000 { - compatible = "ti,omap2-mcspi"; - reg = <0x4809a000 0x100>; - interrupts = <66>; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "mcspi2"; - ti,spi-num-cs = <2>; - dmas = <&sdma 43>, - <&sdma 44>, - <&sdma 45>, - <&sdma 46>; - dma-names = "tx0", "rx0", "tx1", "rx1"; - }; - - mcspi3: spi@480b8000 { - compatible = "ti,omap2-mcspi"; - reg = <0x480b8000 0x100>; - interrupts = <91>; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "mcspi3"; - ti,spi-num-cs = <2>; - dmas = <&sdma 15>, - <&sdma 16>, - <&sdma 23>, - <&sdma 24>; - dma-names = "tx0", "rx0", "tx1", "rx1"; - }; - - mcspi4: spi@480ba000 { - compatible = "ti,omap2-mcspi"; - reg = <0x480ba000 0x100>; - interrupts = <48>; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "mcspi4"; - ti,spi-num-cs = <1>; - dmas = <&sdma 70>, <&sdma 71>; - dma-names = "tx0", "rx0"; - }; - - hdqw1w: 1w@480b2000 { - compatible = "ti,omap3-1w"; - reg = <0x480b2000 0x1000>; - interrupts = <58>; - ti,hwmods = "hdq1w"; - }; - - mmc1: mmc@4809c000 { - compatible = "ti,omap3-hsmmc"; - reg = <0x4809c000 0x200>; - interrupts = <83>; - ti,hwmods = "mmc1"; - ti,dual-volt; - dmas = <&sdma 61>, <&sdma 62>; - dma-names = "tx", "rx"; - pbias-supply = <&pbias_mmc_reg>; - }; - - mmc2: mmc@480b4000 { - compatible = "ti,omap3-hsmmc"; - reg = <0x480b4000 0x200>; - interrupts = <86>; - ti,hwmods = "mmc2"; - dmas = <&sdma 47>, <&sdma 48>; - dma-names = "tx", "rx"; - }; - - mmc3: mmc@480ad000 { - compatible = "ti,omap3-hsmmc"; - reg = <0x480ad000 0x200>; - interrupts = <94>; - ti,hwmods = "mmc3"; - dmas = <&sdma 77>, <&sdma 78>; - dma-names = "tx", "rx"; - }; - - mmu_isp: mmu@480bd400 { - #iommu-cells = <0>; - compatible = "ti,omap2-iommu"; - reg = <0x480bd400 0x80>; - interrupts = <24>; - ti,hwmods = "mmu_isp"; - ti,#tlb-entries = <8>; - }; - - mmu_iva: mmu@5d000000 { - #iommu-cells = <0>; - compatible = "ti,omap2-iommu"; - reg = <0x5d000000 0x80>; - interrupts = <28>; - ti,hwmods = "mmu_iva"; - status = "disabled"; - }; - - wdt2: wdt@48314000 { - compatible = "ti,omap3-wdt"; - reg = <0x48314000 0x80>; - ti,hwmods = "wd_timer2"; - }; - - mcbsp1: mcbsp@48074000 { - compatible = "ti,omap3-mcbsp"; - reg = <0x48074000 0xff>; - reg-names = "mpu"; - interrupts = <16>, /* OCP compliant interrupt */ - <59>, /* TX interrupt */ - <60>; /* RX interrupt */ - interrupt-names = "common", "tx", "rx"; - ti,buffer-size = <128>; - ti,hwmods = "mcbsp1"; - dmas = <&sdma 31>, - <&sdma 32>; - dma-names = "tx", "rx"; - clocks = <&mcbsp1_fck>; - clock-names = "fck"; - status = "disabled"; - }; - - mcbsp2: mcbsp@49022000 { - compatible = "ti,omap3-mcbsp"; - reg = <0x49022000 0xff>, - <0x49028000 0xff>; - reg-names = "mpu", "sidetone"; - interrupts = <17>, /* OCP compliant interrupt */ - <62>, /* TX interrupt */ - <63>, /* RX interrupt */ - <4>; /* Sidetone */ - interrupt-names = "common", "tx", "rx", "sidetone"; - ti,buffer-size = <1280>; - ti,hwmods = "mcbsp2", "mcbsp2_sidetone"; - dmas = <&sdma 33>, - <&sdma 34>; - dma-names = "tx", "rx"; - clocks = <&mcbsp2_fck>, <&mcbsp2_ick>; - clock-names = "fck", "ick"; - status = "disabled"; - }; - - mcbsp3: mcbsp@49024000 { - compatible = "ti,omap3-mcbsp"; - reg = <0x49024000 0xff>, - <0x4902a000 0xff>; - reg-names = "mpu", "sidetone"; - interrupts = <22>, /* OCP compliant interrupt */ - <89>, /* TX interrupt */ - <90>, /* RX interrupt */ - <5>; /* Sidetone */ - interrupt-names = "common", "tx", "rx", "sidetone"; - ti,buffer-size = <128>; - ti,hwmods = "mcbsp3", "mcbsp3_sidetone"; - dmas = <&sdma 17>, - <&sdma 18>; - dma-names = "tx", "rx"; - clocks = <&mcbsp3_fck>, <&mcbsp3_ick>; - clock-names = "fck", "ick"; - status = "disabled"; - }; - - mcbsp4: mcbsp@49026000 { - compatible = "ti,omap3-mcbsp"; - reg = <0x49026000 0xff>; - reg-names = "mpu"; - interrupts = <23>, /* OCP compliant interrupt */ - <54>, /* TX interrupt */ - <55>; /* RX interrupt */ - interrupt-names = "common", "tx", "rx"; - ti,buffer-size = <128>; - ti,hwmods = "mcbsp4"; - dmas = <&sdma 19>, - <&sdma 20>; - dma-names = "tx", "rx"; - clocks = <&mcbsp4_fck>; - clock-names = "fck"; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - mcbsp5: mcbsp@48096000 { - compatible = "ti,omap3-mcbsp"; - reg = <0x48096000 0xff>; - reg-names = "mpu"; - interrupts = <27>, /* OCP compliant interrupt */ - <81>, /* TX interrupt */ - <82>; /* RX interrupt */ - interrupt-names = "common", "tx", "rx"; - ti,buffer-size = <128>; - ti,hwmods = "mcbsp5"; - dmas = <&sdma 21>, - <&sdma 22>; - dma-names = "tx", "rx"; - clocks = <&mcbsp5_fck>; - clock-names = "fck"; - status = "disabled"; - }; - - sham: sham@480c3000 { - compatible = "ti,omap3-sham"; - ti,hwmods = "sham"; - reg = <0x480c3000 0x64>; - interrupts = <49>; - dmas = <&sdma 69>; - dma-names = "rx"; - }; - - timer1: timer@48318000 { - compatible = "ti,omap3430-timer"; - reg = <0x48318000 0x400>; - interrupts = <37>; - ti,hwmods = "timer1"; - ti,timer-alwon; - }; - - timer2: timer@49032000 { - compatible = "ti,omap3430-timer"; - reg = <0x49032000 0x400>; - interrupts = <38>; - ti,hwmods = "timer2"; - }; - - timer3: timer@49034000 { - compatible = "ti,omap3430-timer"; - reg = <0x49034000 0x400>; - interrupts = <39>; - ti,hwmods = "timer3"; - }; - - timer4: timer@49036000 { - compatible = "ti,omap3430-timer"; - reg = <0x49036000 0x400>; - interrupts = <40>; - ti,hwmods = "timer4"; - }; - - timer5: timer@49038000 { - compatible = "ti,omap3430-timer"; - reg = <0x49038000 0x400>; - interrupts = <41>; - ti,hwmods = "timer5"; - ti,timer-dsp; - }; - - timer6: timer@4903a000 { - compatible = "ti,omap3430-timer"; - reg = <0x4903a000 0x400>; - interrupts = <42>; - ti,hwmods = "timer6"; - ti,timer-dsp; - }; - - timer7: timer@4903c000 { - compatible = "ti,omap3430-timer"; - reg = <0x4903c000 0x400>; - interrupts = <43>; - ti,hwmods = "timer7"; - ti,timer-dsp; - }; - - timer8: timer@4903e000 { - compatible = "ti,omap3430-timer"; - reg = <0x4903e000 0x400>; - interrupts = <44>; - ti,hwmods = "timer8"; - ti,timer-pwm; - ti,timer-dsp; - }; - - timer9: timer@49040000 { - compatible = "ti,omap3430-timer"; - reg = <0x49040000 0x400>; - interrupts = <45>; - ti,hwmods = "timer9"; - ti,timer-pwm; - }; - - timer10: timer@48086000 { - compatible = "ti,omap3430-timer"; - reg = <0x48086000 0x400>; - interrupts = <46>; - ti,hwmods = "timer10"; - ti,timer-pwm; - }; - - timer11: timer@48088000 { - compatible = "ti,omap3430-timer"; - reg = <0x48088000 0x400>; - interrupts = <47>; - ti,hwmods = "timer11"; - ti,timer-pwm; - }; - - timer12: timer@48304000 { - compatible = "ti,omap3430-timer"; - reg = <0x48304000 0x400>; - interrupts = <95>; - ti,hwmods = "timer12"; - ti,timer-alwon; - ti,timer-secure; - }; - - usbhstll: usbhstll@48062000 { - compatible = "ti,usbhs-tll"; - reg = <0x48062000 0x1000>; - interrupts = <78>; - ti,hwmods = "usb_tll_hs"; - }; - - usbhshost: usbhshost@48064000 { - compatible = "ti,usbhs-host"; - reg = <0x48064000 0x400>; - ti,hwmods = "usb_host_hs"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - usbhsohci: ohci@48064400 { - compatible = "ti,ohci-omap3"; - reg = <0x48064400 0x400>; - interrupts = <76>; - remote-wakeup-connected; - }; - - usbhsehci: ehci@48064800 { - compatible = "ti,ehci-omap"; - reg = <0x48064800 0x400>; - interrupts = <77>; - }; - }; - - gpmc: gpmc@6e000000 { - compatible = "ti,omap3430-gpmc"; - ti,hwmods = "gpmc"; - reg = <0x6e000000 0x02d0>; - interrupts = <20>; - dmas = <&sdma 4>; - dma-names = "rxtx"; - gpmc,num-cs = <8>; - gpmc,num-waitpins = <4>; - #address-cells = <2>; - #size-cells = <1>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - }; - - usb_otg_hs: usb_otg_hs@480ab000 { - compatible = "ti,omap3-musb"; - reg = <0x480ab000 0x1000>; - interrupts = <92>, <93>; - interrupt-names = "mc", "dma"; - ti,hwmods = "usb_otg_hs"; - multipoint = <1>; - num-eps = <16>; - ram-bits = <12>; - }; - - dss: dss@48050000 { - compatible = "ti,omap3-dss"; - reg = <0x48050000 0x200>; - status = "disabled"; - ti,hwmods = "dss_core"; - clocks = <&dss1_alwon_fck>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - dispc@48050400 { - compatible = "ti,omap3-dispc"; - reg = <0x48050400 0x400>; - interrupts = <25>; - ti,hwmods = "dss_dispc"; - clocks = <&dss1_alwon_fck>; - clock-names = "fck"; - }; - - dsi: encoder@4804fc00 { - compatible = "ti,omap3-dsi"; - reg = <0x4804fc00 0x200>, - <0x4804fe00 0x40>, - <0x4804ff00 0x20>; - reg-names = "proto", "phy", "pll"; - interrupts = <25>; - status = "disabled"; - ti,hwmods = "dss_dsi1"; - clocks = <&dss1_alwon_fck>, <&dss2_alwon_fck>; - clock-names = "fck", "sys_clk"; - }; - - rfbi: encoder@48050800 { - compatible = "ti,omap3-rfbi"; - reg = <0x48050800 0x100>; - status = "disabled"; - ti,hwmods = "dss_rfbi"; - clocks = <&dss1_alwon_fck>, <&dss_ick>; - clock-names = "fck", "ick"; - }; - - venc: encoder@48050c00 { - compatible = "ti,omap3-venc"; - reg = <0x48050c00 0x100>; - status = "disabled"; - ti,hwmods = "dss_venc"; - clocks = <&dss_tv_fck>; - clock-names = "fck"; - }; - }; - - ssi: ssi-controller@48058000 { - compatible = "ti,omap3-ssi"; - ti,hwmods = "ssi"; - - status = "disabled"; - - reg = <0x48058000 0x1000>, - <0x48059000 0x1000>; - reg-names = "sys", - "gdd"; - - interrupts = <71>; - interrupt-names = "gdd_mpu"; - - #address-cells = <1>; - #size-cells = <1>; - ranges; - - ssi_port1: ssi-port@4805a000 { - compatible = "ti,omap3-ssi-port"; - - reg = <0x4805a000 0x800>, - <0x4805a800 0x800>; - reg-names = "tx", - "rx"; - - interrupts = <67>, - <68>; - }; - - ssi_port2: ssi-port@4805b000 { - compatible = "ti,omap3-ssi-port"; - - reg = <0x4805b000 0x800>, - <0x4805b800 0x800>; - reg-names = "tx", - "rx"; - - interrupts = <69>, - <70>; - }; - }; - }; -}; - -/include/ "omap3xxx-clocks.dtsi" diff --git a/sys/gnu/dts/arm/omap3430-sdp.dts b/sys/gnu/dts/arm/omap3430-sdp.dts deleted file mode 100644 index 0abd61108a5..00000000000 --- a/sys/gnu/dts/arm/omap3430-sdp.dts +++ /dev/null @@ -1,195 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ - */ -/dts-v1/; - -#include "omap34xx.dtsi" - -/ { - model = "TI OMAP3430 SDP"; - compatible = "ti,omap3430-sdp", "ti,omap3"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x10000000>; /* 256 MB */ - }; -}; - -&i2c1 { - clock-frequency = <2600000>; - - twl: twl@48 { - reg = <0x48>; - interrupts = <7>; /* SYS_NIRQ cascaded to intc */ - }; -}; - -#include "twl4030.dtsi" -#include "twl4030_omap3.dtsi" - -&mmc1 { - vmmc-supply = <&vmmc1>; - vqmmc-supply = <&vsim>; - /* - * S6-3 must be in ON position for 8 bit mode to function - * Else, use 4 bit mode - */ - bus-width = <8>; -}; - -&mmc2 { - status = "disabled"; -}; - -&mmc3 { - status = "disabled"; -}; - -&gpmc { - ranges = <0 0 0x10000000 0x08000000>, - <1 0 0x28000000 0x1000000>, /* CS1: 16MB for NAND */ - <2 0 0x20000000 0x1000000>; /* CS2: 16MB for OneNAND */ - - nor@0,0 { - compatible = "cfi-flash"; - linux,mtd-name= "intel,pf48f6000m0y1be"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0 0 0x08000000>; - bank-width = <2>; - - gpmc,mux-add-data = <2>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <186>; - gpmc,cs-wr-off-ns = <186>; - gpmc,adv-on-ns = <12>; - gpmc,adv-rd-off-ns = <48>; - gpmc,adv-wr-off-ns = <48>; - gpmc,oe-on-ns = <54>; - gpmc,oe-off-ns = <168>; - gpmc,we-on-ns = <54>; - gpmc,we-off-ns = <168>; - gpmc,rd-cycle-ns = <186>; - gpmc,wr-cycle-ns = <186>; - gpmc,access-ns = <114>; - gpmc,page-burst-access-ns = <6>; - gpmc,bus-turnaround-ns = <12>; - gpmc,cycle2cycle-delay-ns = <18>; - gpmc,wr-data-mux-bus-ns = <90>; - gpmc,wr-access-ns = <186>; - gpmc,cycle2cycle-samecsen; - gpmc,cycle2cycle-diffcsen; - - partition@0 { - label = "bootloader-nor"; - reg = <0 0x40000>; - }; - partition@40000 { - label = "params-nor"; - reg = <0x40000 0x40000>; - }; - partition@80000 { - label = "kernel-nor"; - reg = <0x80000 0x200000>; - }; - partition@280000 { - label = "filesystem-nor"; - reg = <0x240000 0x7d80000>; - }; - }; - - nand@1,0 { - compatible = "ti,omap2-nand"; - reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ - <1 IRQ_TYPE_NONE>; /* termcount */ - linux,mtd-name= "micron,mt29f1g08abb"; - #address-cells = <1>; - #size-cells = <1>; - ti,nand-ecc-opt = "sw"; - nand-bus-width = <8>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <36>; - gpmc,cs-wr-off-ns = <36>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <24>; - gpmc,adv-wr-off-ns = <36>; - gpmc,oe-on-ns = <6>; - gpmc,oe-off-ns = <48>; - gpmc,we-on-ns = <6>; - gpmc,we-off-ns = <30>; - gpmc,rd-cycle-ns = <72>; - gpmc,wr-cycle-ns = <72>; - gpmc,access-ns = <54>; - gpmc,wr-access-ns = <30>; - - partition@0 { - label = "xloader-nand"; - reg = <0 0x80000>; - }; - partition@80000 { - label = "bootloader-nand"; - reg = <0x80000 0x140000>; - }; - partition@1c0000 { - label = "params-nand"; - reg = <0x1c0000 0xc0000>; - }; - partition@280000 { - label = "kernel-nand"; - reg = <0x280000 0x500000>; - }; - partition@780000 { - label = "filesystem-nand"; - reg = <0x780000 0x7880000>; - }; - }; - - onenand@2,0 { - linux,mtd-name= "samsung,kfm2g16q2m-deb8"; - #address-cells = <1>; - #size-cells = <1>; - compatible = "ti,omap2-onenand"; - reg = <2 0 0x20000>; /* CS2, offset 0, IO size 4 */ - - gpmc,device-width = <2>; - gpmc,mux-add-data = <2>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <84>; - gpmc,cs-wr-off-ns = <72>; - gpmc,adv-on-ns = <0>; - gpmc,adv-rd-off-ns = <18>; - gpmc,adv-wr-off-ns = <18>; - gpmc,oe-on-ns = <30>; - gpmc,oe-off-ns = <84>; - gpmc,we-on-ns = <0>; - gpmc,we-off-ns = <42>; - gpmc,rd-cycle-ns = <108>; - gpmc,wr-cycle-ns = <96>; - gpmc,access-ns = <78>; - gpmc,wr-data-mux-bus-ns = <30>; - - partition@0 { - label = "xloader-onenand"; - reg = <0 0x80000>; - }; - partition@80000 { - label = "bootloader-onenand"; - reg = <0x80000 0x40000>; - }; - partition@c0000 { - label = "params-onenand"; - reg = <0xc0000 0x20000>; - }; - partition@e0000 { - label = "kernel-onenand"; - reg = <0xe0000 0x200000>; - }; - partition@2e0000 { - label = "filesystem-onenand"; - reg = <0x2e0000 0xfd20000>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/omap3430es1-clocks.dtsi b/sys/gnu/dts/arm/omap3430es1-clocks.dtsi deleted file mode 100644 index 2ec3628d331..00000000000 --- a/sys/gnu/dts/arm/omap3430es1-clocks.dtsi +++ /dev/null @@ -1,205 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Device Tree Source for OMAP3430 ES1 clock data - * - * Copyright (C) 2013 Texas Instruments, Inc. - */ -&cm_clocks { - gfx_l3_ck: gfx_l3_ck@b10 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&l3_ick>; - reg = <0x0b10>; - ti,bit-shift = <0>; - }; - - gfx_l3_fck: gfx_l3_fck@b40 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&l3_ick>; - ti,max-div = <7>; - reg = <0x0b40>; - ti,index-starts-at-one; - }; - - gfx_l3_ick: gfx_l3_ick { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&gfx_l3_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - gfx_cg1_ck: gfx_cg1_ck@b00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&gfx_l3_fck>; - reg = <0x0b00>; - ti,bit-shift = <1>; - }; - - gfx_cg2_ck: gfx_cg2_ck@b00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&gfx_l3_fck>; - reg = <0x0b00>; - ti,bit-shift = <2>; - }; - - d2d_26m_fck: d2d_26m_fck@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&sys_ck>; - reg = <0x0a00>; - ti,bit-shift = <3>; - }; - - fshostusb_fck: fshostusb_fck@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_48m_fck>; - reg = <0x0a00>; - ti,bit-shift = <5>; - }; - - ssi_ssr_gate_fck_3430es1: ssi_ssr_gate_fck_3430es1@a00 { - #clock-cells = <0>; - compatible = "ti,composite-no-wait-gate-clock"; - clocks = <&corex2_fck>; - ti,bit-shift = <0>; - reg = <0x0a00>; - }; - - ssi_ssr_div_fck_3430es1: ssi_ssr_div_fck_3430es1@a40 { - #clock-cells = <0>; - compatible = "ti,composite-divider-clock"; - clocks = <&corex2_fck>; - ti,bit-shift = <8>; - reg = <0x0a40>; - ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>; - }; - - ssi_ssr_fck: ssi_ssr_fck_3430es1 { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&ssi_ssr_gate_fck_3430es1>, <&ssi_ssr_div_fck_3430es1>; - }; - - ssi_sst_fck: ssi_sst_fck_3430es1 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&ssi_ssr_fck>; - clock-mult = <1>; - clock-div = <2>; - }; - - hsotgusb_ick_3430es1: hsotgusb_ick_3430es1@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-no-wait-interface-clock"; - clocks = <&core_l3_ick>; - reg = <0x0a10>; - ti,bit-shift = <4>; - }; - - fac_ick: fac_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <8>; - }; - - ssi_l4_ick: ssi_l4_ick { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&l4_ick>; - clock-mult = <1>; - clock-div = <1>; - }; - - ssi_ick: ssi_ick_3430es1@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-no-wait-interface-clock"; - clocks = <&ssi_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <0>; - }; - - usb_l4_gate_ick: usb_l4_gate_ick@a10 { - #clock-cells = <0>; - compatible = "ti,composite-interface-clock"; - clocks = <&l4_ick>; - ti,bit-shift = <5>; - reg = <0x0a10>; - }; - - usb_l4_div_ick: usb_l4_div_ick@a40 { - #clock-cells = <0>; - compatible = "ti,composite-divider-clock"; - clocks = <&l4_ick>; - ti,bit-shift = <4>; - ti,max-div = <1>; - reg = <0x0a40>; - ti,index-starts-at-one; - }; - - usb_l4_ick: usb_l4_ick { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&usb_l4_gate_ick>, <&usb_l4_div_ick>; - }; - - dss1_alwon_fck: dss1_alwon_fck_3430es1@e00 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&dpll4_m4x2_ck>; - ti,bit-shift = <0>; - reg = <0x0e00>; - ti,set-rate-parent; - }; - - dss_ick: dss_ick_3430es1@e10 { - #clock-cells = <0>; - compatible = "ti,omap3-no-wait-interface-clock"; - clocks = <&l4_ick>; - reg = <0x0e10>; - ti,bit-shift = <0>; - }; -}; - -&cm_clockdomains { - core_l3_clkdm: core_l3_clkdm { - compatible = "ti,clockdomain"; - clocks = <&sdrc_ick>, <&hsotgusb_ick_3430es1>; - }; - - gfx_3430es1_clkdm: gfx_3430es1_clkdm { - compatible = "ti,clockdomain"; - clocks = <&gfx_l3_ck>, <&gfx_cg1_ck>, <&gfx_cg2_ck>; - }; - - dss_clkdm: dss_clkdm { - compatible = "ti,clockdomain"; - clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>, - <&dss1_alwon_fck>, <&dss_ick>; - }; - - d2d_clkdm: d2d_clkdm { - compatible = "ti,clockdomain"; - clocks = <&d2d_26m_fck>; - }; - - core_l4_clkdm: core_l4_clkdm { - compatible = "ti,clockdomain"; - clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>, - <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>, - <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>, - <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>, - <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>, - <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>, - <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>, - <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>, - <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>, - <&fshostusb_fck>, <&fac_ick>, <&ssi_ick>; - }; -}; diff --git a/sys/gnu/dts/arm/omap34xx-omap36xx-clocks.dtsi b/sys/gnu/dts/arm/omap34xx-omap36xx-clocks.dtsi deleted file mode 100644 index 5e9d1afcd42..00000000000 --- a/sys/gnu/dts/arm/omap34xx-omap36xx-clocks.dtsi +++ /dev/null @@ -1,265 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Device Tree Source for OMAP34XX/OMAP36XX clock data - * - * Copyright (C) 2013 Texas Instruments, Inc. - */ -&cm_clocks { - security_l4_ick2: security_l4_ick2 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&l4_ick>; - clock-mult = <1>; - clock-div = <1>; - }; - - aes1_ick: aes1_ick@a14 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&security_l4_ick2>; - ti,bit-shift = <3>; - reg = <0x0a14>; - }; - - rng_ick: rng_ick@a14 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&security_l4_ick2>; - reg = <0x0a14>; - ti,bit-shift = <2>; - }; - - sha11_ick: sha11_ick@a14 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&security_l4_ick2>; - reg = <0x0a14>; - ti,bit-shift = <1>; - }; - - des1_ick: des1_ick@a14 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&security_l4_ick2>; - reg = <0x0a14>; - ti,bit-shift = <0>; - }; - - cam_mclk: cam_mclk@f00 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&dpll4_m5x2_ck>; - ti,bit-shift = <0>; - reg = <0x0f00>; - ti,set-rate-parent; - }; - - cam_ick: cam_ick@f10 { - #clock-cells = <0>; - compatible = "ti,omap3-no-wait-interface-clock"; - clocks = <&l4_ick>; - reg = <0x0f10>; - ti,bit-shift = <0>; - }; - - csi2_96m_fck: csi2_96m_fck@f00 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&core_96m_fck>; - reg = <0x0f00>; - ti,bit-shift = <1>; - }; - - security_l3_ick: security_l3_ick { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&l3_ick>; - clock-mult = <1>; - clock-div = <1>; - }; - - pka_ick: pka_ick@a14 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&security_l3_ick>; - reg = <0x0a14>; - ti,bit-shift = <4>; - }; - - icr_ick: icr_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <29>; - }; - - des2_ick: des2_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <26>; - }; - - mspro_ick: mspro_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <23>; - }; - - mailboxes_ick: mailboxes_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <7>; - }; - - ssi_l4_ick: ssi_l4_ick { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&l4_ick>; - clock-mult = <1>; - clock-div = <1>; - }; - - sr1_fck: sr1_fck@c00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&sys_ck>; - reg = <0x0c00>; - ti,bit-shift = <6>; - }; - - sr2_fck: sr2_fck@c00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&sys_ck>; - reg = <0x0c00>; - ti,bit-shift = <7>; - }; - - sr_l4_ick: sr_l4_ick { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&l4_ick>; - clock-mult = <1>; - clock-div = <1>; - }; - - dpll2_fck: dpll2_fck@40 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&core_ck>; - ti,bit-shift = <19>; - ti,max-div = <7>; - reg = <0x0040>; - ti,index-starts-at-one; - }; - - dpll2_ck: dpll2_ck@4 { - #clock-cells = <0>; - compatible = "ti,omap3-dpll-clock"; - clocks = <&sys_ck>, <&dpll2_fck>; - reg = <0x0004>, <0x0024>, <0x0040>, <0x0034>; - ti,low-power-stop; - ti,lock; - ti,low-power-bypass; - }; - - dpll2_m2_ck: dpll2_m2_ck@44 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll2_ck>; - ti,max-div = <31>; - reg = <0x0044>; - ti,index-starts-at-one; - }; - - iva2_ck: iva2_ck@0 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&dpll2_m2_ck>; - reg = <0x0000>; - ti,bit-shift = <0>; - }; - - modem_fck: modem_fck@a00 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&sys_ck>; - reg = <0x0a00>; - ti,bit-shift = <31>; - }; - - sad2d_ick: sad2d_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l3_ick>; - reg = <0x0a10>; - ti,bit-shift = <3>; - }; - - mad2d_ick: mad2d_ick@a18 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l3_ick>; - reg = <0x0a18>; - ti,bit-shift = <3>; - }; - - mspro_fck: mspro_fck@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_96m_fck>; - reg = <0x0a00>; - ti,bit-shift = <23>; - }; -}; - -&cm_clockdomains { - cam_clkdm: cam_clkdm { - compatible = "ti,clockdomain"; - clocks = <&cam_ick>, <&csi2_96m_fck>; - }; - - iva2_clkdm: iva2_clkdm { - compatible = "ti,clockdomain"; - clocks = <&iva2_ck>; - }; - - dpll2_clkdm: dpll2_clkdm { - compatible = "ti,clockdomain"; - clocks = <&dpll2_ck>; - }; - - wkup_clkdm: wkup_clkdm { - compatible = "ti,clockdomain"; - clocks = <&gpio1_dbck>, <&wdt2_fck>, <&wdt2_ick>, <&wdt1_ick>, - <&gpio1_ick>, <&omap_32ksync_ick>, <&gpt12_ick>, - <&gpt1_ick>, <&sr1_fck>, <&sr2_fck>; - }; - - d2d_clkdm: d2d_clkdm { - compatible = "ti,clockdomain"; - clocks = <&modem_fck>, <&sad2d_ick>, <&mad2d_ick>; - }; - - core_l4_clkdm: core_l4_clkdm { - compatible = "ti,clockdomain"; - clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>, - <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>, - <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>, - <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>, - <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>, - <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>, - <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>, - <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>, - <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>, <&icr_ick>, - <&des2_ick>, <&mspro_ick>, <&mailboxes_ick>, - <&mspro_fck>; - }; -}; diff --git a/sys/gnu/dts/arm/omap34xx.dtsi b/sys/gnu/dts/arm/omap34xx.dtsi deleted file mode 100644 index 7b09cbee8bb..00000000000 --- a/sys/gnu/dts/arm/omap34xx.dtsi +++ /dev/null @@ -1,149 +0,0 @@ -/* - * Device Tree Source for OMAP34xx/OMAP35xx SoC - * - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -#include -#include - -#include "omap3.dtsi" - -/ { - cpus { - cpu: cpu@0 { - /* OMAP343x/OMAP35xx variants OPP1-5 */ - operating-points = < - /* kHz uV */ - 125000 975000 - 250000 1075000 - 500000 1200000 - 550000 1270000 - 600000 1350000 - >; - clock-latency = <300000>; /* From legacy driver */ - }; - }; - - ocp@68000000 { - omap3_pmx_core2: pinmux@480025d8 { - compatible = "ti,omap3-padconf", "pinctrl-single"; - reg = <0x480025d8 0x24>; - #address-cells = <1>; - #size-cells = <0>; - #pinctrl-cells = <1>; - #interrupt-cells = <1>; - interrupt-controller; - pinctrl-single,register-width = <16>; - pinctrl-single,function-mask = <0xff1f>; - }; - - isp: isp@480bc000 { - compatible = "ti,omap3-isp"; - reg = <0x480bc000 0x12fc - 0x480bd800 0x017c>; - interrupts = <24>; - iommus = <&mmu_isp>; - syscon = <&scm_conf 0x6c>; - ti,phy-type = ; - #clock-cells = <1>; - ports { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - bandgap: bandgap@48002524 { - reg = <0x48002524 0x4>; - compatible = "ti,omap34xx-bandgap"; - #thermal-sensor-cells = <0>; - }; - - target-module@480cb000 { - compatible = "ti,sysc-omap3430-sr", "ti,sysc"; - ti,hwmods = "smartreflex_core"; - reg = <0x480cb024 0x4>; - reg-names = "sysc"; - ti,sysc-mask = ; - clocks = <&sr2_fck>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x480cb000 0x001000>; - - smartreflex_core: smartreflex@0 { - compatible = "ti,omap3-smartreflex-core"; - reg = <0 0x400>; - interrupts = <19>; - }; - }; - - target-module@480c9000 { - compatible = "ti,sysc-omap3430-sr", "ti,sysc"; - ti,hwmods = "smartreflex_mpu_iva"; - reg = <0x480c9024 0x4>; - reg-names = "sysc"; - ti,sysc-mask = ; - clocks = <&sr1_fck>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x480c9000 0x001000>; - - smartreflex_mpu_iva: smartreflex@480c9000 { - compatible = "ti,omap3-smartreflex-mpu-iva"; - reg = <0 0x400>; - interrupts = <18>; - }; - }; - - /* - * On omap34xx the OCP registers do not seem to be accessible - * at all unlike on 36xx. Maybe SGX is permanently set to - * "OCP bypass mode", or maybe there is OCP_SYSCONFIG that is - * write-only at 0x50000e10. We detect SGX based on the SGX - * revision register instead of the unreadable OCP revision - * register. Also note that on early 34xx es1 revision there - * are also different clocks, but we do not have any dts users - * for it. - */ - sgx_module: target-module@50000000 { - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x50000014 0x4>; - reg-names = "rev"; - clocks = <&sgx_fck>, <&sgx_ick>; - clock-names = "fck", "ick"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x50000000 0x4000>; - - /* - * Closed source PowerVR driver, no child device - * binding or driver in mainline - */ - }; - }; - - thermal_zones: thermal-zones { - #include "omap3-cpu-thermal.dtsi" - }; -}; - -&ssi { - status = "ok"; - - clocks = <&ssi_ssr_fck>, - <&ssi_sst_fck>, - <&ssi_ick>; - clock-names = "ssi_ssr_fck", - "ssi_sst_fck", - "ssi_ick"; -}; - -/include/ "omap34xx-omap36xx-clocks.dtsi" -/include/ "omap36xx-omap3430es2plus-clocks.dtsi" -/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi" diff --git a/sys/gnu/dts/arm/omap36xx-am35xx-omap3430es2plus-clocks.dtsi b/sys/gnu/dts/arm/omap36xx-am35xx-omap3430es2plus-clocks.dtsi deleted file mode 100644 index 9974d522697..00000000000 --- a/sys/gnu/dts/arm/omap36xx-am35xx-omap3430es2plus-clocks.dtsi +++ /dev/null @@ -1,239 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Device Tree Source for OMAP36xx/AM35xx/OMAP34xx clock data - * - * Copyright (C) 2013 Texas Instruments, Inc. - */ -&prm_clocks { - corex2_d3_fck: corex2_d3_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&corex2_fck>; - clock-mult = <1>; - clock-div = <3>; - }; - - corex2_d5_fck: corex2_d5_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&corex2_fck>; - clock-mult = <1>; - clock-div = <5>; - }; -}; -&cm_clocks { - dpll5_ck: dpll5_ck@d04 { - #clock-cells = <0>; - compatible = "ti,omap3-dpll-clock"; - clocks = <&sys_ck>, <&sys_ck>; - reg = <0x0d04>, <0x0d24>, <0x0d4c>, <0x0d34>; - ti,low-power-stop; - ti,lock; - }; - - dpll5_m2_ck: dpll5_m2_ck@d50 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll5_ck>; - ti,max-div = <31>; - reg = <0x0d50>; - ti,index-starts-at-one; - }; - - sgx_gate_fck: sgx_gate_fck@b00 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&core_ck>; - ti,bit-shift = <1>; - reg = <0x0b00>; - }; - - core_d3_ck: core_d3_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&core_ck>; - clock-mult = <1>; - clock-div = <3>; - }; - - core_d4_ck: core_d4_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&core_ck>; - clock-mult = <1>; - clock-div = <4>; - }; - - core_d6_ck: core_d6_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&core_ck>; - clock-mult = <1>; - clock-div = <6>; - }; - - omap_192m_alwon_fck: omap_192m_alwon_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll4_m2x2_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - core_d2_ck: core_d2_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&core_ck>; - clock-mult = <1>; - clock-div = <2>; - }; - - sgx_mux_fck: sgx_mux_fck@b40 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&core_d3_ck>, <&core_d4_ck>, <&core_d6_ck>, <&cm_96m_fck>, <&omap_192m_alwon_fck>, <&core_d2_ck>, <&corex2_d3_fck>, <&corex2_d5_fck>; - reg = <0x0b40>; - }; - - sgx_fck: sgx_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&sgx_gate_fck>, <&sgx_mux_fck>; - }; - - sgx_ick: sgx_ick@b10 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&l3_ick>; - reg = <0x0b10>; - ti,bit-shift = <0>; - }; - - cpefuse_fck: cpefuse_fck@a08 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_ck>; - reg = <0x0a08>; - ti,bit-shift = <0>; - }; - - ts_fck: ts_fck@a08 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&omap_32k_fck>; - reg = <0x0a08>; - ti,bit-shift = <1>; - }; - - usbtll_fck: usbtll_fck@a08 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&dpll5_m2_ck>; - reg = <0x0a08>; - ti,bit-shift = <2>; - }; - - usbtll_ick: usbtll_ick@a18 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a18>; - ti,bit-shift = <2>; - }; - - mmchs3_ick: mmchs3_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <30>; - }; - - mmchs3_fck: mmchs3_fck@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_96m_fck>; - reg = <0x0a00>; - ti,bit-shift = <30>; - }; - - dss1_alwon_fck: dss1_alwon_fck_3430es2@e00 { - #clock-cells = <0>; - compatible = "ti,dss-gate-clock"; - clocks = <&dpll4_m4x2_ck>; - ti,bit-shift = <0>; - reg = <0x0e00>; - ti,set-rate-parent; - }; - - dss_ick: dss_ick_3430es2@e10 { - #clock-cells = <0>; - compatible = "ti,omap3-dss-interface-clock"; - clocks = <&l4_ick>; - reg = <0x0e10>; - ti,bit-shift = <0>; - }; - - usbhost_120m_fck: usbhost_120m_fck@1400 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&dpll5_m2_ck>; - reg = <0x1400>; - ti,bit-shift = <1>; - }; - - usbhost_48m_fck: usbhost_48m_fck@1400 { - #clock-cells = <0>; - compatible = "ti,dss-gate-clock"; - clocks = <&omap_48m_fck>; - reg = <0x1400>; - ti,bit-shift = <0>; - }; - - usbhost_ick: usbhost_ick@1410 { - #clock-cells = <0>; - compatible = "ti,omap3-dss-interface-clock"; - clocks = <&l4_ick>; - reg = <0x1410>; - ti,bit-shift = <0>; - }; -}; - -&cm_clockdomains { - dpll5_clkdm: dpll5_clkdm { - compatible = "ti,clockdomain"; - clocks = <&dpll5_ck>; - }; - - sgx_clkdm: sgx_clkdm { - compatible = "ti,clockdomain"; - clocks = <&sgx_ick>; - }; - - dss_clkdm: dss_clkdm { - compatible = "ti,clockdomain"; - clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>, - <&dss1_alwon_fck>, <&dss_ick>; - }; - - core_l4_clkdm: core_l4_clkdm { - compatible = "ti,clockdomain"; - clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>, - <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>, - <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>, - <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>, - <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>, - <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>, - <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>, - <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>, - <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>, - <&cpefuse_fck>, <&ts_fck>, <&usbtll_fck>, - <&usbtll_ick>, <&mmchs3_ick>, <&mmchs3_fck>; - }; - - usbhost_clkdm: usbhost_clkdm { - compatible = "ti,clockdomain"; - clocks = <&usbhost_120m_fck>, <&usbhost_48m_fck>, - <&usbhost_ick>; - }; -}; diff --git a/sys/gnu/dts/arm/omap36xx-clocks.dtsi b/sys/gnu/dts/arm/omap36xx-clocks.dtsi deleted file mode 100644 index e66fc57ec35..00000000000 --- a/sys/gnu/dts/arm/omap36xx-clocks.dtsi +++ /dev/null @@ -1,107 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Device Tree Source for OMAP36xx clock data - * - * Copyright (C) 2013 Texas Instruments, Inc. - */ -&cm_clocks { - dpll4_ck: dpll4_ck@d00 { - #clock-cells = <0>; - compatible = "ti,omap3-dpll-per-j-type-clock"; - clocks = <&sys_ck>, <&sys_ck>; - reg = <0x0d00>, <0x0d20>, <0x0d44>, <0x0d30>; - }; - - dpll4_m5x2_ck: dpll4_m5x2_ck@d00 { - #clock-cells = <0>; - compatible = "ti,hsdiv-gate-clock"; - clocks = <&dpll4_m5x2_mul_ck>; - ti,bit-shift = <0x1e>; - reg = <0x0d00>; - ti,set-rate-parent; - ti,set-bit-to-disable; - }; - - dpll4_m2x2_ck: dpll4_m2x2_ck@d00 { - #clock-cells = <0>; - compatible = "ti,hsdiv-gate-clock"; - clocks = <&dpll4_m2x2_mul_ck>; - ti,bit-shift = <0x1b>; - reg = <0x0d00>; - ti,set-bit-to-disable; - }; - - dpll3_m3x2_ck: dpll3_m3x2_ck@d00 { - #clock-cells = <0>; - compatible = "ti,hsdiv-gate-clock"; - clocks = <&dpll3_m3x2_mul_ck>; - ti,bit-shift = <0xc>; - reg = <0x0d00>; - ti,set-bit-to-disable; - }; - - dpll4_m3x2_ck: dpll4_m3x2_ck@d00 { - #clock-cells = <0>; - compatible = "ti,hsdiv-gate-clock"; - clocks = <&dpll4_m3x2_mul_ck>; - ti,bit-shift = <0x1c>; - reg = <0x0d00>; - ti,set-bit-to-disable; - }; - - dpll4_m6x2_ck: dpll4_m6x2_ck@d00 { - #clock-cells = <0>; - compatible = "ti,hsdiv-gate-clock"; - clocks = <&dpll4_m6x2_mul_ck>; - ti,bit-shift = <0x1f>; - reg = <0x0d00>; - ti,set-bit-to-disable; - }; - - uart4_fck: uart4_fck@1000 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&per_48m_fck>; - reg = <0x1000>; - ti,bit-shift = <18>; - }; -}; - -&dpll4_m2x2_mul_ck { - clock-mult = <1>; -}; - -&dpll4_m3x2_mul_ck { - clock-mult = <1>; -}; - -&dpll4_m4x2_mul_ck { - ti,clock-mult = <1>; -}; - -&dpll4_m5x2_mul_ck { - ti,clock-mult = <1>; -}; - -&dpll4_m6x2_mul_ck { - clock-mult = <1>; -}; - -&cm_clockdomains { - dpll4_clkdm: dpll4_clkdm { - compatible = "ti,clockdomain"; - clocks = <&dpll4_ck>; - }; - - per_clkdm: per_clkdm { - compatible = "ti,clockdomain"; - clocks = <&uart3_fck>, <&gpio6_dbck>, <&gpio5_dbck>, - <&gpio4_dbck>, <&gpio3_dbck>, <&gpio2_dbck>, - <&wdt3_fck>, <&gpio6_ick>, <&gpio5_ick>, <&gpio4_ick>, - <&gpio3_ick>, <&gpio2_ick>, <&wdt3_ick>, <&uart3_ick>, - <&uart4_ick>, <&gpt9_ick>, <&gpt8_ick>, <&gpt7_ick>, - <&gpt6_ick>, <&gpt5_ick>, <&gpt4_ick>, <&gpt3_ick>, - <&gpt2_ick>, <&mcbsp2_ick>, <&mcbsp3_ick>, - <&mcbsp4_ick>, <&uart4_fck>; - }; -}; diff --git a/sys/gnu/dts/arm/omap36xx-omap3430es2plus-clocks.dtsi b/sys/gnu/dts/arm/omap36xx-omap3430es2plus-clocks.dtsi deleted file mode 100644 index 945537aee3c..00000000000 --- a/sys/gnu/dts/arm/omap36xx-omap3430es2plus-clocks.dtsi +++ /dev/null @@ -1,195 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Device Tree Source for OMAP34xx/OMAP36xx clock data - * - * Copyright (C) 2013 Texas Instruments, Inc. - */ -&cm_clocks { - ssi_ssr_gate_fck_3430es2: ssi_ssr_gate_fck_3430es2@a00 { - #clock-cells = <0>; - compatible = "ti,composite-no-wait-gate-clock"; - clocks = <&corex2_fck>; - ti,bit-shift = <0>; - reg = <0x0a00>; - }; - - ssi_ssr_div_fck_3430es2: ssi_ssr_div_fck_3430es2@a40 { - #clock-cells = <0>; - compatible = "ti,composite-divider-clock"; - clocks = <&corex2_fck>; - ti,bit-shift = <8>; - reg = <0x0a40>; - ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>; - }; - - ssi_ssr_fck: ssi_ssr_fck_3430es2 { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&ssi_ssr_gate_fck_3430es2>, <&ssi_ssr_div_fck_3430es2>; - }; - - ssi_sst_fck: ssi_sst_fck_3430es2 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&ssi_ssr_fck>; - clock-mult = <1>; - clock-div = <2>; - }; - - hsotgusb_ick_3430es2: hsotgusb_ick_3430es2@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-hsotgusb-interface-clock"; - clocks = <&core_l3_ick>; - reg = <0x0a10>; - ti,bit-shift = <4>; - }; - - ssi_l4_ick: ssi_l4_ick { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&l4_ick>; - clock-mult = <1>; - clock-div = <1>; - }; - - ssi_ick: ssi_ick_3430es2@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-ssi-interface-clock"; - clocks = <&ssi_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <0>; - }; - - usim_gate_fck: usim_gate_fck@c00 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&omap_96m_fck>; - ti,bit-shift = <9>; - reg = <0x0c00>; - }; - - sys_d2_ck: sys_d2_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&sys_ck>; - clock-mult = <1>; - clock-div = <2>; - }; - - omap_96m_d2_fck: omap_96m_d2_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&omap_96m_fck>; - clock-mult = <1>; - clock-div = <2>; - }; - - omap_96m_d4_fck: omap_96m_d4_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&omap_96m_fck>; - clock-mult = <1>; - clock-div = <4>; - }; - - omap_96m_d8_fck: omap_96m_d8_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&omap_96m_fck>; - clock-mult = <1>; - clock-div = <8>; - }; - - omap_96m_d10_fck: omap_96m_d10_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&omap_96m_fck>; - clock-mult = <1>; - clock-div = <10>; - }; - - dpll5_m2_d4_ck: dpll5_m2_d4_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll5_m2_ck>; - clock-mult = <1>; - clock-div = <4>; - }; - - dpll5_m2_d8_ck: dpll5_m2_d8_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll5_m2_ck>; - clock-mult = <1>; - clock-div = <8>; - }; - - dpll5_m2_d16_ck: dpll5_m2_d16_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll5_m2_ck>; - clock-mult = <1>; - clock-div = <16>; - }; - - dpll5_m2_d20_ck: dpll5_m2_d20_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll5_m2_ck>; - clock-mult = <1>; - clock-div = <20>; - }; - - usim_mux_fck: usim_mux_fck@c40 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&sys_ck>, <&sys_d2_ck>, <&omap_96m_d2_fck>, <&omap_96m_d4_fck>, <&omap_96m_d8_fck>, <&omap_96m_d10_fck>, <&dpll5_m2_d4_ck>, <&dpll5_m2_d8_ck>, <&dpll5_m2_d16_ck>, <&dpll5_m2_d20_ck>; - ti,bit-shift = <3>; - reg = <0x0c40>; - ti,index-starts-at-one; - }; - - usim_fck: usim_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&usim_gate_fck>, <&usim_mux_fck>; - }; - - usim_ick: usim_ick@c10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&wkup_l4_ick>; - reg = <0x0c10>; - ti,bit-shift = <9>; - }; -}; - -&cm_clockdomains { - core_l3_clkdm: core_l3_clkdm { - compatible = "ti,clockdomain"; - clocks = <&sdrc_ick>, <&hsotgusb_ick_3430es2>; - }; - - wkup_clkdm: wkup_clkdm { - compatible = "ti,clockdomain"; - clocks = <&gpio1_dbck>, <&wdt2_fck>, <&wdt2_ick>, <&wdt1_ick>, - <&gpio1_ick>, <&omap_32ksync_ick>, <&gpt12_ick>, - <&gpt1_ick>, <&usim_ick>; - }; - - core_l4_clkdm: core_l4_clkdm { - compatible = "ti,clockdomain"; - clocks = <&cpefuse_fck>, <&ts_fck>, <&usbtll_fck>, - <&usbtll_ick>, <&mmchs3_ick>, <&mmchs3_fck>, - <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>, - <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>, - <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>, - <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>, - <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>, - <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>, - <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>, - <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>, - <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>, - <&ssi_ick>; - }; -}; diff --git a/sys/gnu/dts/arm/omap36xx.dtsi b/sys/gnu/dts/arm/omap36xx.dtsi deleted file mode 100644 index 1e552f08f12..00000000000 --- a/sys/gnu/dts/arm/omap36xx.dtsi +++ /dev/null @@ -1,197 +0,0 @@ -/* - * Device Tree Source for OMAP3 SoC - * - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -#include -#include - -#include "omap3.dtsi" - -/ { - aliases { - serial3 = &uart4; - }; - - cpus { - /* OMAP3630/OMAP37xx 'standard device' variants OPP50 to OPP130 */ - cpu: cpu@0 { - operating-points = < - /* kHz uV */ - 300000 1012500 - 600000 1200000 - 800000 1325000 - >; - clock-latency = <300000>; /* From legacy driver */ - }; - }; - - ocp@68000000 { - uart4: serial@49042000 { - compatible = "ti,omap3-uart"; - reg = <0x49042000 0x400>; - interrupts = <80>; - dmas = <&sdma 81 &sdma 82>; - dma-names = "tx", "rx"; - ti,hwmods = "uart4"; - clock-frequency = <48000000>; - }; - - abb_mpu_iva: regulator-abb-mpu { - compatible = "ti,abb-v1"; - regulator-name = "abb_mpu_iva"; - #address-cells = <0>; - #size-cells = <0>; - reg = <0x483072f0 0x8>, <0x48306818 0x4>; - reg-names = "base-address", "int-address"; - ti,tranxdone-status-mask = <0x4000000>; - clocks = <&sys_ck>; - ti,settling-time = <30>; - ti,clock-cycles = <8>; - ti,abb_info = < - /*uV ABB efuse rbb_m fbb_m vset_m*/ - 1012500 0 0 0 0 0 - 1200000 0 0 0 0 0 - 1325000 0 0 0 0 0 - 1375000 1 0 0 0 0 - >; - }; - - omap3_pmx_core2: pinmux@480025a0 { - compatible = "ti,omap3-padconf", "pinctrl-single"; - reg = <0x480025a0 0x5c>; - #address-cells = <1>; - #size-cells = <0>; - #pinctrl-cells = <1>; - #interrupt-cells = <1>; - interrupt-controller; - pinctrl-single,register-width = <16>; - pinctrl-single,function-mask = <0xff1f>; - }; - - isp: isp@480bc000 { - compatible = "ti,omap3-isp"; - reg = <0x480bc000 0x12fc - 0x480bd800 0x0600>; - interrupts = <24>; - iommus = <&mmu_isp>; - syscon = <&scm_conf 0x2f0>; - ti,phy-type = ; - #clock-cells = <1>; - ports { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - bandgap: bandgap@48002524 { - reg = <0x48002524 0x4>; - compatible = "ti,omap36xx-bandgap"; - #thermal-sensor-cells = <0>; - }; - - target-module@480cb000 { - compatible = "ti,sysc-omap3630-sr", "ti,sysc"; - ti,hwmods = "smartreflex_core"; - reg = <0x480cb038 0x4>; - reg-names = "sysc"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - ; - clocks = <&sr2_fck>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x480cb000 0x001000>; - - smartreflex_core: smartreflex@0 { - compatible = "ti,omap3-smartreflex-core"; - reg = <0 0x400>; - interrupts = <19>; - }; - }; - - target-module@480c9000 { - compatible = "ti,sysc-omap3630-sr", "ti,sysc"; - ti,hwmods = "smartreflex_mpu_iva"; - reg = <0x480c9038 0x4>; - reg-names = "sysc"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - ; - clocks = <&sr1_fck>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x480c9000 0x001000>; - - - smartreflex_mpu_iva: smartreflex@480c9000 { - compatible = "ti,omap3-smartreflex-mpu-iva"; - reg = <0 0x400>; - interrupts = <18>; - }; - }; - - /* - * Note that the sysconfig register layout is a subset of the - * "ti,sysc-omap4" type register with just sidle and midle bits - * available while omap34xx has "ti,sysc-omap2" type sysconfig. - */ - sgx_module: target-module@50000000 { - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x5000fe00 0x4>, - <0x5000fe10 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-midle = , - , - ; - ti,sysc-sidle = , - , - ; - clocks = <&sgx_fck>, <&sgx_ick>; - clock-names = "fck", "ick"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x50000000 0x2000000>; - - /* - * Closed source PowerVR driver, no child device - * binding or driver in mainline - */ - }; - }; - - thermal_zones: thermal-zones { - #include "omap3-cpu-thermal.dtsi" - }; -}; - -/* OMAP3630 needs dss_96m_fck for VENC */ -&venc { - clocks = <&dss_tv_fck>, <&dss_96m_fck>; - clock-names = "fck", "tv_dac_clk"; -}; - -&ssi { - status = "ok"; - - clocks = <&ssi_ssr_fck>, - <&ssi_sst_fck>, - <&ssi_ick>; - clock-names = "ssi_ssr_fck", - "ssi_sst_fck", - "ssi_ick"; -}; - -/include/ "omap34xx-omap36xx-clocks.dtsi" -/include/ "omap36xx-omap3430es2plus-clocks.dtsi" -/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi" -/include/ "omap36xx-clocks.dtsi" diff --git a/sys/gnu/dts/arm/omap3xxx-clocks.dtsi b/sys/gnu/dts/arm/omap3xxx-clocks.dtsi deleted file mode 100644 index 685c82a9d03..00000000000 --- a/sys/gnu/dts/arm/omap3xxx-clocks.dtsi +++ /dev/null @@ -1,1662 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Device Tree Source for OMAP3 clock data - * - * Copyright (C) 2013 Texas Instruments, Inc. - */ -&prm_clocks { - virt_16_8m_ck: virt_16_8m_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <16800000>; - }; - - osc_sys_ck: osc_sys_ck@d40 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&virt_12m_ck>, <&virt_13m_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_38_4m_ck>, <&virt_16_8m_ck>; - reg = <0x0d40>; - }; - - sys_ck: sys_ck@1270 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&osc_sys_ck>; - ti,bit-shift = <6>; - ti,max-div = <3>; - reg = <0x1270>; - ti,index-starts-at-one; - }; - - sys_clkout1: sys_clkout1@d70 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&osc_sys_ck>; - reg = <0x0d70>; - ti,bit-shift = <7>; - }; - - dpll3_x2_ck: dpll3_x2_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll3_ck>; - clock-mult = <2>; - clock-div = <1>; - }; - - dpll3_m2x2_ck: dpll3_m2x2_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll3_m2_ck>; - clock-mult = <2>; - clock-div = <1>; - }; - - dpll4_x2_ck: dpll4_x2_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll4_ck>; - clock-mult = <2>; - clock-div = <1>; - }; - - corex2_fck: corex2_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll3_m2x2_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - wkup_l4_ick: wkup_l4_ick { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&sys_ck>; - clock-mult = <1>; - clock-div = <1>; - }; -}; - -&scm_clocks { - mcbsp5_mux_fck: mcbsp5_mux_fck@68 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&core_96m_fck>, <&mcbsp_clks>; - ti,bit-shift = <4>; - reg = <0x68>; - }; - - mcbsp5_fck: mcbsp5_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&mcbsp5_gate_fck>, <&mcbsp5_mux_fck>; - }; - - mcbsp1_mux_fck: mcbsp1_mux_fck@4 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&core_96m_fck>, <&mcbsp_clks>; - ti,bit-shift = <2>; - reg = <0x04>; - }; - - mcbsp1_fck: mcbsp1_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&mcbsp1_gate_fck>, <&mcbsp1_mux_fck>; - }; - - mcbsp2_mux_fck: mcbsp2_mux_fck@4 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&per_96m_fck>, <&mcbsp_clks>; - ti,bit-shift = <6>; - reg = <0x04>; - }; - - mcbsp2_fck: mcbsp2_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&mcbsp2_gate_fck>, <&mcbsp2_mux_fck>; - }; - - mcbsp3_mux_fck: mcbsp3_mux_fck@68 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&per_96m_fck>, <&mcbsp_clks>; - reg = <0x68>; - }; - - mcbsp3_fck: mcbsp3_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&mcbsp3_gate_fck>, <&mcbsp3_mux_fck>; - }; - - mcbsp4_mux_fck: mcbsp4_mux_fck@68 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&per_96m_fck>, <&mcbsp_clks>; - ti,bit-shift = <2>; - reg = <0x68>; - }; - - mcbsp4_fck: mcbsp4_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&mcbsp4_gate_fck>, <&mcbsp4_mux_fck>; - }; -}; -&cm_clocks { - dummy_apb_pclk: dummy_apb_pclk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0x0>; - }; - - omap_32k_fck: omap_32k_fck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - virt_12m_ck: virt_12m_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <12000000>; - }; - - virt_13m_ck: virt_13m_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <13000000>; - }; - - virt_19200000_ck: virt_19200000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <19200000>; - }; - - virt_26000000_ck: virt_26000000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <26000000>; - }; - - virt_38_4m_ck: virt_38_4m_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <38400000>; - }; - - dpll4_ck: dpll4_ck@d00 { - #clock-cells = <0>; - compatible = "ti,omap3-dpll-per-clock"; - clocks = <&sys_ck>, <&sys_ck>; - reg = <0x0d00>, <0x0d20>, <0x0d44>, <0x0d30>; - }; - - dpll4_m2_ck: dpll4_m2_ck@d48 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll4_ck>; - ti,max-div = <63>; - reg = <0x0d48>; - ti,index-starts-at-one; - }; - - dpll4_m2x2_mul_ck: dpll4_m2x2_mul_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll4_m2_ck>; - clock-mult = <2>; - clock-div = <1>; - }; - - dpll4_m2x2_ck: dpll4_m2x2_ck@d00 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&dpll4_m2x2_mul_ck>; - ti,bit-shift = <0x1b>; - reg = <0x0d00>; - ti,set-bit-to-disable; - }; - - omap_96m_alwon_fck: omap_96m_alwon_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll4_m2x2_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - dpll3_ck: dpll3_ck@d00 { - #clock-cells = <0>; - compatible = "ti,omap3-dpll-core-clock"; - clocks = <&sys_ck>, <&sys_ck>; - reg = <0x0d00>, <0x0d20>, <0x0d40>, <0x0d30>; - }; - - dpll3_m3_ck: dpll3_m3_ck@1140 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll3_ck>; - ti,bit-shift = <16>; - ti,max-div = <31>; - reg = <0x1140>; - ti,index-starts-at-one; - }; - - dpll3_m3x2_mul_ck: dpll3_m3x2_mul_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll3_m3_ck>; - clock-mult = <2>; - clock-div = <1>; - }; - - dpll3_m3x2_ck: dpll3_m3x2_ck@d00 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&dpll3_m3x2_mul_ck>; - ti,bit-shift = <0xc>; - reg = <0x0d00>; - ti,set-bit-to-disable; - }; - - emu_core_alwon_ck: emu_core_alwon_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll3_m3x2_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - sys_altclk: sys_altclk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0x0>; - }; - - mcbsp_clks: mcbsp_clks { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0x0>; - }; - - dpll3_m2_ck: dpll3_m2_ck@d40 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll3_ck>; - ti,bit-shift = <27>; - ti,max-div = <31>; - reg = <0x0d40>; - ti,index-starts-at-one; - }; - - core_ck: core_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll3_m2_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - dpll1_fck: dpll1_fck@940 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&core_ck>; - ti,bit-shift = <19>; - ti,max-div = <7>; - reg = <0x0940>; - ti,index-starts-at-one; - }; - - dpll1_ck: dpll1_ck@904 { - #clock-cells = <0>; - compatible = "ti,omap3-dpll-clock"; - clocks = <&sys_ck>, <&dpll1_fck>; - reg = <0x0904>, <0x0924>, <0x0940>, <0x0934>; - }; - - dpll1_x2_ck: dpll1_x2_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll1_ck>; - clock-mult = <2>; - clock-div = <1>; - }; - - dpll1_x2m2_ck: dpll1_x2m2_ck@944 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll1_x2_ck>; - ti,max-div = <31>; - reg = <0x0944>; - ti,index-starts-at-one; - }; - - cm_96m_fck: cm_96m_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&omap_96m_alwon_fck>; - clock-mult = <1>; - clock-div = <1>; - }; - - omap_96m_fck: omap_96m_fck@d40 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&cm_96m_fck>, <&sys_ck>; - ti,bit-shift = <6>; - reg = <0x0d40>; - }; - - dpll4_m3_ck: dpll4_m3_ck@e40 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll4_ck>; - ti,bit-shift = <8>; - ti,max-div = <32>; - reg = <0x0e40>; - ti,index-starts-at-one; - }; - - dpll4_m3x2_mul_ck: dpll4_m3x2_mul_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll4_m3_ck>; - clock-mult = <2>; - clock-div = <1>; - }; - - dpll4_m3x2_ck: dpll4_m3x2_ck@d00 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&dpll4_m3x2_mul_ck>; - ti,bit-shift = <0x1c>; - reg = <0x0d00>; - ti,set-bit-to-disable; - }; - - omap_54m_fck: omap_54m_fck@d40 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&dpll4_m3x2_ck>, <&sys_altclk>; - ti,bit-shift = <5>; - reg = <0x0d40>; - }; - - cm_96m_d2_fck: cm_96m_d2_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&cm_96m_fck>; - clock-mult = <1>; - clock-div = <2>; - }; - - omap_48m_fck: omap_48m_fck@d40 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&cm_96m_d2_fck>, <&sys_altclk>; - ti,bit-shift = <3>; - reg = <0x0d40>; - }; - - omap_12m_fck: omap_12m_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&omap_48m_fck>; - clock-mult = <1>; - clock-div = <4>; - }; - - dpll4_m4_ck: dpll4_m4_ck@e40 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll4_ck>; - ti,max-div = <32>; - reg = <0x0e40>; - ti,index-starts-at-one; - }; - - dpll4_m4x2_mul_ck: dpll4_m4x2_mul_ck { - #clock-cells = <0>; - compatible = "ti,fixed-factor-clock"; - clocks = <&dpll4_m4_ck>; - ti,clock-mult = <2>; - ti,clock-div = <1>; - ti,set-rate-parent; - }; - - dpll4_m4x2_ck: dpll4_m4x2_ck@d00 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&dpll4_m4x2_mul_ck>; - ti,bit-shift = <0x1d>; - reg = <0x0d00>; - ti,set-bit-to-disable; - ti,set-rate-parent; - }; - - dpll4_m5_ck: dpll4_m5_ck@f40 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll4_ck>; - ti,max-div = <63>; - reg = <0x0f40>; - ti,index-starts-at-one; - }; - - dpll4_m5x2_mul_ck: dpll4_m5x2_mul_ck { - #clock-cells = <0>; - compatible = "ti,fixed-factor-clock"; - clocks = <&dpll4_m5_ck>; - ti,clock-mult = <2>; - ti,clock-div = <1>; - ti,set-rate-parent; - }; - - dpll4_m5x2_ck: dpll4_m5x2_ck@d00 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&dpll4_m5x2_mul_ck>; - ti,bit-shift = <0x1e>; - reg = <0x0d00>; - ti,set-bit-to-disable; - ti,set-rate-parent; - }; - - dpll4_m6_ck: dpll4_m6_ck@1140 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll4_ck>; - ti,bit-shift = <24>; - ti,max-div = <63>; - reg = <0x1140>; - ti,index-starts-at-one; - }; - - dpll4_m6x2_mul_ck: dpll4_m6x2_mul_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll4_m6_ck>; - clock-mult = <2>; - clock-div = <1>; - }; - - dpll4_m6x2_ck: dpll4_m6x2_ck@d00 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&dpll4_m6x2_mul_ck>; - ti,bit-shift = <0x1f>; - reg = <0x0d00>; - ti,set-bit-to-disable; - }; - - emu_per_alwon_ck: emu_per_alwon_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll4_m6x2_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - clkout2_src_gate_ck: clkout2_src_gate_ck@d70 { - #clock-cells = <0>; - compatible = "ti,composite-no-wait-gate-clock"; - clocks = <&core_ck>; - ti,bit-shift = <7>; - reg = <0x0d70>; - }; - - clkout2_src_mux_ck: clkout2_src_mux_ck@d70 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&core_ck>, <&sys_ck>, <&cm_96m_fck>, <&omap_54m_fck>; - reg = <0x0d70>; - }; - - clkout2_src_ck: clkout2_src_ck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&clkout2_src_gate_ck>, <&clkout2_src_mux_ck>; - }; - - sys_clkout2: sys_clkout2@d70 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&clkout2_src_ck>; - ti,bit-shift = <3>; - ti,max-div = <64>; - reg = <0x0d70>; - ti,index-power-of-two; - }; - - mpu_ck: mpu_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll1_x2m2_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - arm_fck: arm_fck@924 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&mpu_ck>; - reg = <0x0924>; - ti,max-div = <2>; - }; - - emu_mpu_alwon_ck: emu_mpu_alwon_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&mpu_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - l3_ick: l3_ick@a40 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&core_ck>; - ti,max-div = <3>; - reg = <0x0a40>; - ti,index-starts-at-one; - }; - - l4_ick: l4_ick@a40 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&l3_ick>; - ti,bit-shift = <2>; - ti,max-div = <3>; - reg = <0x0a40>; - ti,index-starts-at-one; - }; - - rm_ick: rm_ick@c40 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&l4_ick>; - ti,bit-shift = <1>; - ti,max-div = <3>; - reg = <0x0c40>; - ti,index-starts-at-one; - }; - - gpt10_gate_fck: gpt10_gate_fck@a00 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&sys_ck>; - ti,bit-shift = <11>; - reg = <0x0a00>; - }; - - gpt10_mux_fck: gpt10_mux_fck@a40 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&omap_32k_fck>, <&sys_ck>; - ti,bit-shift = <6>; - reg = <0x0a40>; - }; - - gpt10_fck: gpt10_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&gpt10_gate_fck>, <&gpt10_mux_fck>; - }; - - gpt11_gate_fck: gpt11_gate_fck@a00 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&sys_ck>; - ti,bit-shift = <12>; - reg = <0x0a00>; - }; - - gpt11_mux_fck: gpt11_mux_fck@a40 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&omap_32k_fck>, <&sys_ck>; - ti,bit-shift = <7>; - reg = <0x0a40>; - }; - - gpt11_fck: gpt11_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&gpt11_gate_fck>, <&gpt11_mux_fck>; - }; - - core_96m_fck: core_96m_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&omap_96m_fck>; - clock-mult = <1>; - clock-div = <1>; - }; - - mmchs2_fck: mmchs2_fck@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_96m_fck>; - reg = <0x0a00>; - ti,bit-shift = <25>; - }; - - mmchs1_fck: mmchs1_fck@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_96m_fck>; - reg = <0x0a00>; - ti,bit-shift = <24>; - }; - - i2c3_fck: i2c3_fck@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_96m_fck>; - reg = <0x0a00>; - ti,bit-shift = <17>; - }; - - i2c2_fck: i2c2_fck@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_96m_fck>; - reg = <0x0a00>; - ti,bit-shift = <16>; - }; - - i2c1_fck: i2c1_fck@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_96m_fck>; - reg = <0x0a00>; - ti,bit-shift = <15>; - }; - - mcbsp5_gate_fck: mcbsp5_gate_fck@a00 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&mcbsp_clks>; - ti,bit-shift = <10>; - reg = <0x0a00>; - }; - - mcbsp1_gate_fck: mcbsp1_gate_fck@a00 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&mcbsp_clks>; - ti,bit-shift = <9>; - reg = <0x0a00>; - }; - - core_48m_fck: core_48m_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&omap_48m_fck>; - clock-mult = <1>; - clock-div = <1>; - }; - - mcspi4_fck: mcspi4_fck@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_48m_fck>; - reg = <0x0a00>; - ti,bit-shift = <21>; - }; - - mcspi3_fck: mcspi3_fck@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_48m_fck>; - reg = <0x0a00>; - ti,bit-shift = <20>; - }; - - mcspi2_fck: mcspi2_fck@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_48m_fck>; - reg = <0x0a00>; - ti,bit-shift = <19>; - }; - - mcspi1_fck: mcspi1_fck@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_48m_fck>; - reg = <0x0a00>; - ti,bit-shift = <18>; - }; - - uart2_fck: uart2_fck@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_48m_fck>; - reg = <0x0a00>; - ti,bit-shift = <14>; - }; - - uart1_fck: uart1_fck@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_48m_fck>; - reg = <0x0a00>; - ti,bit-shift = <13>; - }; - - core_12m_fck: core_12m_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&omap_12m_fck>; - clock-mult = <1>; - clock-div = <1>; - }; - - hdq_fck: hdq_fck@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_12m_fck>; - reg = <0x0a00>; - ti,bit-shift = <22>; - }; - - core_l3_ick: core_l3_ick { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&l3_ick>; - clock-mult = <1>; - clock-div = <1>; - }; - - sdrc_ick: sdrc_ick@a10 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_l3_ick>; - reg = <0x0a10>; - ti,bit-shift = <1>; - }; - - gpmc_fck: gpmc_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&core_l3_ick>; - clock-mult = <1>; - clock-div = <1>; - }; - - core_l4_ick: core_l4_ick { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&l4_ick>; - clock-mult = <1>; - clock-div = <1>; - }; - - mmchs2_ick: mmchs2_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <25>; - }; - - mmchs1_ick: mmchs1_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <24>; - }; - - hdq_ick: hdq_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <22>; - }; - - mcspi4_ick: mcspi4_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <21>; - }; - - mcspi3_ick: mcspi3_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <20>; - }; - - mcspi2_ick: mcspi2_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <19>; - }; - - mcspi1_ick: mcspi1_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <18>; - }; - - i2c3_ick: i2c3_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <17>; - }; - - i2c2_ick: i2c2_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <16>; - }; - - i2c1_ick: i2c1_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <15>; - }; - - uart2_ick: uart2_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <14>; - }; - - uart1_ick: uart1_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <13>; - }; - - gpt11_ick: gpt11_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <12>; - }; - - gpt10_ick: gpt10_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <11>; - }; - - mcbsp5_ick: mcbsp5_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <10>; - }; - - mcbsp1_ick: mcbsp1_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <9>; - }; - - omapctrl_ick: omapctrl_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <6>; - }; - - dss_tv_fck: dss_tv_fck@e00 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&omap_54m_fck>; - reg = <0x0e00>; - ti,bit-shift = <2>; - }; - - dss_96m_fck: dss_96m_fck@e00 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&omap_96m_fck>; - reg = <0x0e00>; - ti,bit-shift = <2>; - }; - - dss2_alwon_fck: dss2_alwon_fck@e00 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_ck>; - reg = <0x0e00>; - ti,bit-shift = <1>; - }; - - dummy_ck: dummy_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - gpt1_gate_fck: gpt1_gate_fck@c00 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&sys_ck>; - ti,bit-shift = <0>; - reg = <0x0c00>; - }; - - gpt1_mux_fck: gpt1_mux_fck@c40 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&omap_32k_fck>, <&sys_ck>; - reg = <0x0c40>; - }; - - gpt1_fck: gpt1_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&gpt1_gate_fck>, <&gpt1_mux_fck>; - }; - - aes2_ick: aes2_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - ti,bit-shift = <28>; - reg = <0x0a10>; - }; - - wkup_32k_fck: wkup_32k_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&omap_32k_fck>; - clock-mult = <1>; - clock-div = <1>; - }; - - gpio1_dbck: gpio1_dbck@c00 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&wkup_32k_fck>; - reg = <0x0c00>; - ti,bit-shift = <3>; - }; - - sha12_ick: sha12_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <27>; - }; - - wdt2_fck: wdt2_fck@c00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&wkup_32k_fck>; - reg = <0x0c00>; - ti,bit-shift = <5>; - }; - - wdt2_ick: wdt2_ick@c10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&wkup_l4_ick>; - reg = <0x0c10>; - ti,bit-shift = <5>; - }; - - wdt1_ick: wdt1_ick@c10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&wkup_l4_ick>; - reg = <0x0c10>; - ti,bit-shift = <4>; - }; - - gpio1_ick: gpio1_ick@c10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&wkup_l4_ick>; - reg = <0x0c10>; - ti,bit-shift = <3>; - }; - - omap_32ksync_ick: omap_32ksync_ick@c10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&wkup_l4_ick>; - reg = <0x0c10>; - ti,bit-shift = <2>; - }; - - gpt12_ick: gpt12_ick@c10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&wkup_l4_ick>; - reg = <0x0c10>; - ti,bit-shift = <1>; - }; - - gpt1_ick: gpt1_ick@c10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&wkup_l4_ick>; - reg = <0x0c10>; - ti,bit-shift = <0>; - }; - - per_96m_fck: per_96m_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&omap_96m_alwon_fck>; - clock-mult = <1>; - clock-div = <1>; - }; - - per_48m_fck: per_48m_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&omap_48m_fck>; - clock-mult = <1>; - clock-div = <1>; - }; - - uart3_fck: uart3_fck@1000 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&per_48m_fck>; - reg = <0x1000>; - ti,bit-shift = <11>; - }; - - gpt2_gate_fck: gpt2_gate_fck@1000 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&sys_ck>; - ti,bit-shift = <3>; - reg = <0x1000>; - }; - - gpt2_mux_fck: gpt2_mux_fck@1040 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&omap_32k_fck>, <&sys_ck>; - reg = <0x1040>; - }; - - gpt2_fck: gpt2_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&gpt2_gate_fck>, <&gpt2_mux_fck>; - }; - - gpt3_gate_fck: gpt3_gate_fck@1000 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&sys_ck>; - ti,bit-shift = <4>; - reg = <0x1000>; - }; - - gpt3_mux_fck: gpt3_mux_fck@1040 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&omap_32k_fck>, <&sys_ck>; - ti,bit-shift = <1>; - reg = <0x1040>; - }; - - gpt3_fck: gpt3_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&gpt3_gate_fck>, <&gpt3_mux_fck>; - }; - - gpt4_gate_fck: gpt4_gate_fck@1000 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&sys_ck>; - ti,bit-shift = <5>; - reg = <0x1000>; - }; - - gpt4_mux_fck: gpt4_mux_fck@1040 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&omap_32k_fck>, <&sys_ck>; - ti,bit-shift = <2>; - reg = <0x1040>; - }; - - gpt4_fck: gpt4_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&gpt4_gate_fck>, <&gpt4_mux_fck>; - }; - - gpt5_gate_fck: gpt5_gate_fck@1000 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&sys_ck>; - ti,bit-shift = <6>; - reg = <0x1000>; - }; - - gpt5_mux_fck: gpt5_mux_fck@1040 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&omap_32k_fck>, <&sys_ck>; - ti,bit-shift = <3>; - reg = <0x1040>; - }; - - gpt5_fck: gpt5_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&gpt5_gate_fck>, <&gpt5_mux_fck>; - }; - - gpt6_gate_fck: gpt6_gate_fck@1000 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&sys_ck>; - ti,bit-shift = <7>; - reg = <0x1000>; - }; - - gpt6_mux_fck: gpt6_mux_fck@1040 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&omap_32k_fck>, <&sys_ck>; - ti,bit-shift = <4>; - reg = <0x1040>; - }; - - gpt6_fck: gpt6_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&gpt6_gate_fck>, <&gpt6_mux_fck>; - }; - - gpt7_gate_fck: gpt7_gate_fck@1000 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&sys_ck>; - ti,bit-shift = <8>; - reg = <0x1000>; - }; - - gpt7_mux_fck: gpt7_mux_fck@1040 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&omap_32k_fck>, <&sys_ck>; - ti,bit-shift = <5>; - reg = <0x1040>; - }; - - gpt7_fck: gpt7_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&gpt7_gate_fck>, <&gpt7_mux_fck>; - }; - - gpt8_gate_fck: gpt8_gate_fck@1000 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&sys_ck>; - ti,bit-shift = <9>; - reg = <0x1000>; - }; - - gpt8_mux_fck: gpt8_mux_fck@1040 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&omap_32k_fck>, <&sys_ck>; - ti,bit-shift = <6>; - reg = <0x1040>; - }; - - gpt8_fck: gpt8_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&gpt8_gate_fck>, <&gpt8_mux_fck>; - }; - - gpt9_gate_fck: gpt9_gate_fck@1000 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&sys_ck>; - ti,bit-shift = <10>; - reg = <0x1000>; - }; - - gpt9_mux_fck: gpt9_mux_fck@1040 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&omap_32k_fck>, <&sys_ck>; - ti,bit-shift = <7>; - reg = <0x1040>; - }; - - gpt9_fck: gpt9_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&gpt9_gate_fck>, <&gpt9_mux_fck>; - }; - - per_32k_alwon_fck: per_32k_alwon_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&omap_32k_fck>; - clock-mult = <1>; - clock-div = <1>; - }; - - gpio6_dbck: gpio6_dbck@1000 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&per_32k_alwon_fck>; - reg = <0x1000>; - ti,bit-shift = <17>; - }; - - gpio5_dbck: gpio5_dbck@1000 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&per_32k_alwon_fck>; - reg = <0x1000>; - ti,bit-shift = <16>; - }; - - gpio4_dbck: gpio4_dbck@1000 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&per_32k_alwon_fck>; - reg = <0x1000>; - ti,bit-shift = <15>; - }; - - gpio3_dbck: gpio3_dbck@1000 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&per_32k_alwon_fck>; - reg = <0x1000>; - ti,bit-shift = <14>; - }; - - gpio2_dbck: gpio2_dbck@1000 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&per_32k_alwon_fck>; - reg = <0x1000>; - ti,bit-shift = <13>; - }; - - wdt3_fck: wdt3_fck@1000 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&per_32k_alwon_fck>; - reg = <0x1000>; - ti,bit-shift = <12>; - }; - - per_l4_ick: per_l4_ick { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&l4_ick>; - clock-mult = <1>; - clock-div = <1>; - }; - - gpio6_ick: gpio6_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <17>; - }; - - gpio5_ick: gpio5_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <16>; - }; - - gpio4_ick: gpio4_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <15>; - }; - - gpio3_ick: gpio3_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <14>; - }; - - gpio2_ick: gpio2_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <13>; - }; - - wdt3_ick: wdt3_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <12>; - }; - - uart3_ick: uart3_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <11>; - }; - - uart4_ick: uart4_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <18>; - }; - - gpt9_ick: gpt9_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <10>; - }; - - gpt8_ick: gpt8_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <9>; - }; - - gpt7_ick: gpt7_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <8>; - }; - - gpt6_ick: gpt6_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <7>; - }; - - gpt5_ick: gpt5_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <6>; - }; - - gpt4_ick: gpt4_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <5>; - }; - - gpt3_ick: gpt3_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <4>; - }; - - gpt2_ick: gpt2_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <3>; - }; - - mcbsp2_ick: mcbsp2_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <0>; - }; - - mcbsp3_ick: mcbsp3_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <1>; - }; - - mcbsp4_ick: mcbsp4_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <2>; - }; - - mcbsp2_gate_fck: mcbsp2_gate_fck@1000 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&mcbsp_clks>; - ti,bit-shift = <0>; - reg = <0x1000>; - }; - - mcbsp3_gate_fck: mcbsp3_gate_fck@1000 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&mcbsp_clks>; - ti,bit-shift = <1>; - reg = <0x1000>; - }; - - mcbsp4_gate_fck: mcbsp4_gate_fck@1000 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&mcbsp_clks>; - ti,bit-shift = <2>; - reg = <0x1000>; - }; - - emu_src_mux_ck: emu_src_mux_ck@1140 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>; - reg = <0x1140>; - }; - - emu_src_ck: emu_src_ck { - #clock-cells = <0>; - compatible = "ti,clkdm-gate-clock"; - clocks = <&emu_src_mux_ck>; - }; - - pclk_fck: pclk_fck@1140 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&emu_src_ck>; - ti,bit-shift = <8>; - ti,max-div = <7>; - reg = <0x1140>; - ti,index-starts-at-one; - }; - - pclkx2_fck: pclkx2_fck@1140 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&emu_src_ck>; - ti,bit-shift = <6>; - ti,max-div = <3>; - reg = <0x1140>; - ti,index-starts-at-one; - }; - - atclk_fck: atclk_fck@1140 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&emu_src_ck>; - ti,bit-shift = <4>; - ti,max-div = <3>; - reg = <0x1140>; - ti,index-starts-at-one; - }; - - traceclk_src_fck: traceclk_src_fck@1140 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>; - ti,bit-shift = <2>; - reg = <0x1140>; - }; - - traceclk_fck: traceclk_fck@1140 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&traceclk_src_fck>; - ti,bit-shift = <11>; - ti,max-div = <7>; - reg = <0x1140>; - ti,index-starts-at-one; - }; - - secure_32k_fck: secure_32k_fck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - gpt12_fck: gpt12_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&secure_32k_fck>; - clock-mult = <1>; - clock-div = <1>; - }; - - wdt1_fck: wdt1_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&secure_32k_fck>; - clock-mult = <1>; - clock-div = <1>; - }; -}; - -&cm_clockdomains { - core_l3_clkdm: core_l3_clkdm { - compatible = "ti,clockdomain"; - clocks = <&sdrc_ick>; - }; - - dpll3_clkdm: dpll3_clkdm { - compatible = "ti,clockdomain"; - clocks = <&dpll3_ck>; - }; - - dpll1_clkdm: dpll1_clkdm { - compatible = "ti,clockdomain"; - clocks = <&dpll1_ck>; - }; - - per_clkdm: per_clkdm { - compatible = "ti,clockdomain"; - clocks = <&uart3_fck>, <&gpio6_dbck>, <&gpio5_dbck>, - <&gpio4_dbck>, <&gpio3_dbck>, <&gpio2_dbck>, - <&wdt3_fck>, <&gpio6_ick>, <&gpio5_ick>, <&gpio4_ick>, - <&gpio3_ick>, <&gpio2_ick>, <&wdt3_ick>, <&uart3_ick>, - <&uart4_ick>, <&gpt9_ick>, <&gpt8_ick>, <&gpt7_ick>, - <&gpt6_ick>, <&gpt5_ick>, <&gpt4_ick>, <&gpt3_ick>, - <&gpt2_ick>, <&mcbsp2_ick>, <&mcbsp3_ick>, - <&mcbsp4_ick>; - }; - - emu_clkdm: emu_clkdm { - compatible = "ti,clockdomain"; - clocks = <&emu_src_ck>; - }; - - dpll4_clkdm: dpll4_clkdm { - compatible = "ti,clockdomain"; - clocks = <&dpll4_ck>; - }; - - wkup_clkdm: wkup_clkdm { - compatible = "ti,clockdomain"; - clocks = <&gpio1_dbck>, <&wdt2_fck>, <&wdt2_ick>, <&wdt1_ick>, - <&gpio1_ick>, <&omap_32ksync_ick>, <&gpt12_ick>, - <&gpt1_ick>; - }; - - dss_clkdm: dss_clkdm { - compatible = "ti,clockdomain"; - clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>; - }; - - core_l4_clkdm: core_l4_clkdm { - compatible = "ti,clockdomain"; - clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>, - <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>, - <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>, - <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>, - <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>, - <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>, - <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>, - <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>, - <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>; - }; -}; diff --git a/sys/gnu/dts/arm/omap4-cpu-thermal.dtsi b/sys/gnu/dts/arm/omap4-cpu-thermal.dtsi deleted file mode 100644 index ab7f87ae96f..00000000000 --- a/sys/gnu/dts/arm/omap4-cpu-thermal.dtsi +++ /dev/null @@ -1,41 +0,0 @@ -/* - * Device Tree Source for OMAP4/5 SoC CPU thermal - * - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ - * Contact: Eduardo Valentin - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -#include - -cpu_thermal: cpu_thermal { - polling-delay-passive = <250>; /* milliseconds */ - polling-delay = <1000>; /* milliseconds */ - - /* sensor ID */ - thermal-sensors = <&bandgap 0>; - - cpu_trips: trips { - cpu_alert0: cpu_alert { - temperature = <100000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - cpu_crit: cpu_crit { - temperature = <125000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "critical"; - }; - }; - - cpu_cooling_maps: cooling-maps { - map0 { - trip = <&cpu_alert0>; - cooling-device = - <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/omap4-droid-bionic-xt875.dts b/sys/gnu/dts/arm/omap4-droid-bionic-xt875.dts deleted file mode 100644 index e69de29bb2d..00000000000 diff --git a/sys/gnu/dts/arm/omap4-droid4-xt894.dts b/sys/gnu/dts/arm/omap4-droid4-xt894.dts deleted file mode 100644 index a40fe8d49da..00000000000 --- a/sys/gnu/dts/arm/omap4-droid4-xt894.dts +++ /dev/null @@ -1,784 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/dts-v1/; - -#include -#include "omap443x.dtsi" -#include "motorola-cpcap-mapphone.dtsi" - -/ { - model = "Motorola Droid 4 XT894"; - compatible = "motorola,droid4", "ti,omap4430", "ti,omap4"; - - chosen { - stdout-path = &uart3; - }; - - aliases { - display0 = &lcd0; - display1 = &hdmi0; - }; - - /* - * We seem to have only 1021 MB accessible, 1021 - 1022 is locked, - * then 1023 - 1024 seems to contain mbm. - */ - memory { - device_type = "memory"; - reg = <0x80000000 0x3fd00000>; /* 1021 MB */ - }; - - /* Poweroff GPIO probably connected to CPCAP */ - gpio-poweroff { - compatible = "gpio-poweroff"; - pinctrl-0 = <&poweroff_gpio>; - pinctrl-names = "default"; - gpios = <&gpio2 18 GPIO_ACTIVE_LOW>; /* gpio50 */ - }; - - hdmi0: connector { - compatible = "hdmi-connector"; - pinctrl-0 = <&hdmi_hpd_gpio>; - pinctrl-names = "default"; - label = "hdmi"; - type = "d"; - - hpd-gpios = <&gpio2 31 GPIO_ACTIVE_HIGH>; /* gpio63 */ - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_out>; - }; - }; - }; - - /* - * HDMI 5V regulator probably sourced from battery. Let's keep - * keep this as always enabled for HDMI to work until we've - * figured what the encoder chip is. - */ - hdmi_regulator: regulator-hdmi { - compatible = "regulator-fixed"; - regulator-name = "hdmi"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio2 27 GPIO_ACTIVE_HIGH>; /* gpio59 */ - enable-active-high; - regulator-always-on; - }; - - /* FS USB Host PHY on port 1 for mdm6600 */ - fsusb1_phy: usb-phy@1 { - compatible = "motorola,mapphone-mdm6600"; - pinctrl-0 = <&usb_mdm6600_pins>; - pinctrl-names = "default"; - enable-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; /* gpio_95 */ - power-gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; /* gpio_54 */ - reset-gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>; /* gpio_49 */ - /* mode: gpio_148 gpio_149 */ - motorola,mode-gpios = <&gpio5 20 GPIO_ACTIVE_HIGH>, - <&gpio5 21 GPIO_ACTIVE_HIGH>; - /* cmd: gpio_103 gpio_104 gpio_142 */ - motorola,cmd-gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>, - <&gpio4 8 GPIO_ACTIVE_HIGH>, - <&gpio5 14 GPIO_ACTIVE_HIGH>; - /* status: gpio_52 gpio_53 gpio_55 */ - motorola,status-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>, - <&gpio2 21 GPIO_ACTIVE_HIGH>, - <&gpio2 23 GPIO_ACTIVE_HIGH>; - #phy-cells = <0>; - }; - - /* HS USB host TLL nop-phy on port 2 for w3glte */ - hsusb2_phy: usb-phy@2 { - compatible = "usb-nop-xceiv"; - #phy-cells = <0>; - }; - - /* LCD regulator from sw5 source */ - lcd_regulator: regulator-lcd { - compatible = "regulator-fixed"; - regulator-name = "lcd"; - regulator-min-microvolt = <5050000>; - regulator-max-microvolt = <5050000>; - gpio = <&gpio4 0 GPIO_ACTIVE_HIGH>; /* gpio96 */ - enable-active-high; - vin-supply = <&sw5>; - }; - - /* This is probably coming straight from the battery.. */ - wl12xx_vmmc: regulator-wl12xx { - compatible = "regulator-fixed"; - regulator-name = "vwl1271"; - regulator-min-microvolt = <1650000>; - regulator-max-microvolt = <1650000>; - gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>; /* gpio94 */ - startup-delay-us = <70000>; - enable-active-high; - }; - - gpio_keys { - compatible = "gpio-keys"; - - volume_down { - label = "Volume Down"; - gpios = <&gpio5 26 GPIO_ACTIVE_LOW>; /* gpio154 */ - linux,code = ; - linux,can-disable; - /* Value above 7.95ms for no GPIO hardware debounce */ - debounce-interval = <10>; - }; - - slider { - label = "Keypad Slide"; - gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>; /* gpio122 */ - linux,input-type = ; - linux,code = ; - linux,can-disable; - /* Value above 7.95ms for no GPIO hardware debounce */ - debounce-interval = <10>; - }; - }; - - soundcard { - compatible = "audio-graph-card"; - label = "Droid 4 Audio"; - - simple-graph-card,widgets = - "Speaker", "Earpiece", - "Speaker", "Loudspeaker", - "Headphone", "Headphone Jack", - "Microphone", "Internal Mic"; - - simple-graph-card,routing = - "Earpiece", "EP", - "Loudspeaker", "SPKR", - "Headphone Jack", "HSL", - "Headphone Jack", "HSR", - "MICR", "Internal Mic"; - - dais = <&mcbsp2_port>, <&mcbsp3_port>; - }; - - pwm8: dmtimer-pwm-8 { - pinctrl-names = "default"; - pinctrl-0 = <&vibrator_direction_pin>; - - compatible = "ti,omap-dmtimer-pwm"; - #pwm-cells = <3>; - ti,timers = <&timer8>; - ti,clock-source = <0x01>; - }; - - pwm9: dmtimer-pwm-9 { - pinctrl-names = "default"; - pinctrl-0 = <&vibrator_enable_pin>; - - compatible = "ti,omap-dmtimer-pwm"; - #pwm-cells = <3>; - ti,timers = <&timer9>; - ti,clock-source = <0x01>; - }; - - vibrator { - compatible = "pwm-vibrator"; - pwms = <&pwm9 0 10000000 0>, <&pwm8 0 10000000 0>; - pwm-names = "enable", "direction"; - direction-duty-cycle-ns = <10000000>; - }; -}; - -&dss { - status = "okay"; -}; - -&dsi1 { - status = "okay"; - vdd-supply = <&vcsi>; - - port { - dsi1_out_ep: endpoint { - remote-endpoint = <&lcd0_in>; - lanes = <0 1 2 3 4 5>; - }; - }; - - lcd0: display { - compatible = "panel-dsi-cm"; - label = "lcd0"; - vddi-supply = <&lcd_regulator>; - reset-gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; /* gpio101 */ - - width-mm = <50>; - height-mm = <89>; - - panel-timing { - clock-frequency = <0>; /* Calculated by dsi */ - - hback-porch = <2>; - hactive = <540>; - hfront-porch = <0>; - hsync-len = <2>; - - vback-porch = <1>; - vactive = <960>; - vfront-porch = <0>; - vsync-len = <1>; - - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - - port { - lcd0_in: endpoint { - remote-endpoint = <&dsi1_out_ep>; - }; - }; - }; -}; - -&hdmi { - status = "okay"; - pinctrl-0 = <&dss_hdmi_pins>; - pinctrl-names = "default"; - vdda-supply = <&vdac>; - - port { - hdmi_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - lanes = <1 0 3 2 5 4 7 6>; - }; - }; -}; - -&i2c1 { - tmp105@48 { - compatible = "ti,tmp105"; - reg = <0x48>; - pinctrl-0 = <&tmp105_irq>; - pinctrl-names = "default"; - /* kpd_row0.gpio_178 */ - interrupts-extended = <&gpio6 18 IRQ_TYPE_EDGE_FALLING - &omap4_pmx_core 0x14e>; - interrupt-names = "irq", "wakeup"; - wakeup-source; - }; -}; - -&keypad { - keypad,num-rows = <8>; - keypad,num-columns = <8>; - linux,keymap = < - - /* Row 1 */ - MATRIX_KEY(0, 2, KEY_1) - MATRIX_KEY(0, 6, KEY_2) - MATRIX_KEY(2, 3, KEY_3) - MATRIX_KEY(0, 7, KEY_4) - MATRIX_KEY(0, 4, KEY_5) - MATRIX_KEY(5, 5, KEY_6) - MATRIX_KEY(0, 1, KEY_7) - MATRIX_KEY(0, 5, KEY_8) - MATRIX_KEY(0, 0, KEY_9) - MATRIX_KEY(1, 6, KEY_0) - - /* Row 2 */ - MATRIX_KEY(3, 4, KEY_APOSTROPHE) - MATRIX_KEY(7, 6, KEY_Q) - MATRIX_KEY(7, 7, KEY_W) - MATRIX_KEY(7, 2, KEY_E) - MATRIX_KEY(1, 0, KEY_R) - MATRIX_KEY(4, 4, KEY_T) - MATRIX_KEY(1, 2, KEY_Y) - MATRIX_KEY(6, 7, KEY_U) - MATRIX_KEY(2, 2, KEY_I) - MATRIX_KEY(5, 6, KEY_O) - MATRIX_KEY(3, 7, KEY_P) - MATRIX_KEY(6, 5, KEY_BACKSPACE) - - /* Row 3 */ - MATRIX_KEY(5, 4, KEY_TAB) - MATRIX_KEY(5, 7, KEY_A) - MATRIX_KEY(2, 7, KEY_S) - MATRIX_KEY(7, 0, KEY_D) - MATRIX_KEY(2, 6, KEY_F) - MATRIX_KEY(6, 2, KEY_G) - MATRIX_KEY(6, 6, KEY_H) - MATRIX_KEY(1, 4, KEY_J) - MATRIX_KEY(3, 1, KEY_K) - MATRIX_KEY(2, 1, KEY_L) - MATRIX_KEY(4, 6, KEY_ENTER) - - /* Row 4 */ - MATRIX_KEY(3, 6, KEY_LEFTSHIFT) /* KEY_CAPSLOCK */ - MATRIX_KEY(6, 1, KEY_Z) - MATRIX_KEY(7, 4, KEY_X) - MATRIX_KEY(5, 1, KEY_C) - MATRIX_KEY(1, 7, KEY_V) - MATRIX_KEY(2, 4, KEY_B) - MATRIX_KEY(4, 1, KEY_N) - MATRIX_KEY(1, 1, KEY_M) - MATRIX_KEY(3, 5, KEY_COMMA) - MATRIX_KEY(5, 2, KEY_DOT) - MATRIX_KEY(6, 3, KEY_UP) - MATRIX_KEY(7, 3, KEY_OK) - - /* Row 5 */ - MATRIX_KEY(2, 5, KEY_LEFTCTRL) /* KEY_LEFTSHIFT */ - MATRIX_KEY(4, 5, KEY_LEFTALT) /* SYM */ - MATRIX_KEY(6, 0, KEY_MINUS) - MATRIX_KEY(4, 7, KEY_EQUAL) - MATRIX_KEY(1, 5, KEY_SPACE) - MATRIX_KEY(3, 2, KEY_SLASH) - MATRIX_KEY(4, 3, KEY_LEFT) - MATRIX_KEY(5, 3, KEY_DOWN) - MATRIX_KEY(3, 3, KEY_RIGHT) - - /* Side buttons, KEY_VOLUMEDOWN and KEY_PWER are on CPCAP? */ - MATRIX_KEY(5, 0, KEY_VOLUMEUP) - >; -}; - -&mmc1 { - vmmc-supply = <&vwlan2>; - bus-width = <4>; - cd-gpios = <&gpio6 16 GPIO_ACTIVE_LOW>; /* gpio176 */ -}; - -&mmc2 { - vmmc-supply = <&vsdio>; - bus-width = <8>; - ti,non-removable; -}; - -&mmc3 { - vmmc-supply = <&wl12xx_vmmc>; - /* uart2_tx.sdmmc3_dat1 pad as wakeirq */ - interrupts-extended = <&wakeupgen GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH - &omap4_pmx_core 0xde>; - interrupt-names = "irq", "wakeup"; - non-removable; - bus-width = <4>; - cap-power-off-card; - keep-power-in-suspend; - - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@2 { - compatible = "ti,wl1285", "ti,wl1283"; - reg = <2>; - /* gpio_100 with gpmc_wait2 pad as wakeirq */ - interrupts-extended = <&gpio4 4 IRQ_TYPE_LEVEL_HIGH>, - <&omap4_pmx_core 0x4e>; - interrupt-names = "irq", "wakeup"; - ref-clock-frequency = <26000000>; - tcxo-clock-frequency = <26000000>; - }; -}; - -&i2c1 { - led-controller@38 { - compatible = "ti,lm3532"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x38>; - - enable-gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>; - - ramp-up-us = <1024>; - ramp-down-us = <8193>; - - led@0 { - reg = <0>; - led-sources = <2>; - ti,led-mode = <0>; - label = ":backlight"; - linux,default-trigger = "backlight"; - }; - - led@1 { - reg = <1>; - led-sources = <1>; - ti,led-mode = <0>; - label = ":kbd_backlight"; - }; - }; -}; - -&i2c2 { - touchscreen@4a { - compatible = "atmel,maxtouch"; - reg = <0x4a>; - pinctrl-names = "default"; - pinctrl-0 = <&touchscreen_pins>; - - reset-gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>; /* gpio173 */ - - /* gpio_183 with sys_nirq2 pad as wakeup */ - interrupts-extended = <&gpio6 23 IRQ_TYPE_EDGE_FALLING>, - <&omap4_pmx_core 0x160>; - interrupt-names = "irq", "wakeup"; - wakeup-source; - }; - - isl29030@44 { - compatible = "isil,isl29030"; - reg = <0x44>; - - pinctrl-names = "default"; - pinctrl-0 = <&als_proximity_pins>; - - interrupt-parent = <&gpio6>; - interrupts = <17 IRQ_TYPE_LEVEL_LOW>; /* gpio177 */ - }; -}; - -&omap4_pmx_core { - - /* hdmi_hpd.gpio_63 */ - hdmi_hpd_gpio: pinmux_hdmi_hpd_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x098, PIN_INPUT | MUX_MODE3) - >; - }; - - /* hdmi_cec.hdmi_cec, hdmi_scl.hdmi_scl, hdmi_sda.hdmi_sda */ - dss_hdmi_pins: pinmux_dss_hdmi_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x09a, PIN_INPUT | MUX_MODE0) - OMAP4_IOPAD(0x09c, PIN_INPUT | MUX_MODE0) - OMAP4_IOPAD(0x09e, PIN_INPUT | MUX_MODE0) - >; - }; - - /* gpmc_ncs0.gpio_50 */ - poweroff_gpio: pinmux_poweroff_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x074, PIN_OUTPUT_PULLUP | MUX_MODE3) - >; - }; - - /* kpd_row0.gpio_178 */ - tmp105_irq: pinmux_tmp105_irq { - pinctrl-single,pins = < - OMAP4_IOPAD(0x18e, PIN_INPUT_PULLUP | MUX_MODE3) - >; - }; - - usb_gpio_mux_sel1: pinmux_usb_gpio_mux_sel1_pins { - /* gpio_60 */ - pinctrl-single,pins = < - OMAP4_IOPAD(0x088, PIN_OUTPUT | MUX_MODE3) - >; - }; - - touchscreen_pins: pinmux_touchscreen_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x180, PIN_OUTPUT | MUX_MODE3) - OMAP4_IOPAD(0x1a0, PIN_INPUT_PULLUP | MUX_MODE3) - >; - }; - - als_proximity_pins: pinmux_als_proximity_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x18c, PIN_INPUT_PULLUP | MUX_MODE3) - >; - }; - - usb_mdm6600_pins: pinmux_usb_mdm6600_pins { - pinctrl-single,pins = < - /* enable 0x4a1000d8 usbb1_ulpitll_dat7.gpio_95 ag16 */ - OMAP4_IOPAD(0x0d8, PIN_INPUT | MUX_MODE3) - - /* power 0x4a10007c gpmc_nwp.gpio_54 c25 */ - OMAP4_IOPAD(0x07c, PIN_OUTPUT | MUX_MODE3) - - /* reset 0x4a100072 gpmc_a25.gpio_49 d20 */ - OMAP4_IOPAD(0x072, PIN_OUTPUT | MUX_MODE3) - - /* mode0/bpwake 0x4a10014e sdmmc5_dat1.gpio_148 af4 */ - OMAP4_IOPAD(0x14e, PIN_OUTPUT | MUX_MODE3) - - /* mode1/apwake 0x4a100150 sdmmc5_dat2.gpio_149 ag3 */ - OMAP4_IOPAD(0x150, PIN_OFF_OUTPUT_LOW | PIN_INPUT | MUX_MODE3) - - /* status0 0x4a10007e gpmc_clk.gpio_55 b22 */ - OMAP4_IOPAD(0x07e, PIN_INPUT | MUX_MODE3) - - /* status1 0x4a10007a gpmc_ncs3.gpio_53 c22 */ - OMAP4_IOPAD(0x07a, PIN_INPUT | MUX_MODE3) - - /* status2 0x4a100078 gpmc_ncs2.gpio_52 d21 */ - OMAP4_IOPAD(0x078, PIN_INPUT | MUX_MODE3) - - /* cmd0 0x4a100094 gpmc_ncs6.gpio_103 c24 */ - OMAP4_IOPAD(0x094, PIN_OUTPUT | MUX_MODE3) - - /* cmd1 0x4a100096 gpmc_ncs7.gpio_104 d24 */ - OMAP4_IOPAD(0x096, PIN_OUTPUT | MUX_MODE3) - - /* cmd2 0x4a100142 uart3_rts_sd.gpio_142 f28 */ - OMAP4_IOPAD(0x142, PIN_OUTPUT | MUX_MODE3) - >; - }; - - usb_ulpi_pins: pinmux_usb_ulpi_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x196, MUX_MODE7) - OMAP4_IOPAD(0x198, MUX_MODE7) - OMAP4_IOPAD(0x1b2, PIN_INPUT_PULLUP | MUX_MODE0) - OMAP4_IOPAD(0x1b4, PIN_INPUT_PULLUP | MUX_MODE0) - OMAP4_IOPAD(0x1b6, PIN_INPUT_PULLUP | MUX_MODE0) - OMAP4_IOPAD(0x1b8, PIN_INPUT_PULLUP | MUX_MODE0) - OMAP4_IOPAD(0x1ba, PIN_INPUT_PULLUP | MUX_MODE0) - OMAP4_IOPAD(0x1bc, PIN_INPUT_PULLUP | MUX_MODE0) - OMAP4_IOPAD(0x1be, PIN_INPUT_PULLUP | MUX_MODE0) - OMAP4_IOPAD(0x1c0, PIN_INPUT_PULLUP | MUX_MODE0) - OMAP4_IOPAD(0x1c2, PIN_INPUT_PULLUP | MUX_MODE0) - OMAP4_IOPAD(0x1c4, PIN_INPUT_PULLUP | MUX_MODE0) - OMAP4_IOPAD(0x1c6, PIN_INPUT_PULLUP | MUX_MODE0) - OMAP4_IOPAD(0x1c8, PIN_INPUT_PULLUP | MUX_MODE0) - >; - }; - - /* usb0_otg_dp and usb0_otg_dm */ - usb_utmi_pins: pinmux_usb_utmi_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x196, PIN_INPUT | MUX_MODE0) - OMAP4_IOPAD(0x198, PIN_INPUT | MUX_MODE0) - OMAP4_IOPAD(0x1b2, PIN_INPUT_PULLUP | MUX_MODE7) - OMAP4_IOPAD(0x1b4, PIN_INPUT_PULLUP | MUX_MODE7) - OMAP4_IOPAD(0x1b6, PIN_INPUT_PULLUP | MUX_MODE7) - OMAP4_IOPAD(0x1b8, PIN_INPUT_PULLUP | MUX_MODE7) - OMAP4_IOPAD(0x1ba, PIN_INPUT_PULLUP | MUX_MODE7) - OMAP4_IOPAD(0x1bc, PIN_INPUT_PULLUP | MUX_MODE7) - OMAP4_IOPAD(0x1be, PIN_INPUT_PULLUP | MUX_MODE7) - OMAP4_IOPAD(0x1c0, PIN_INPUT_PULLUP | MUX_MODE7) - OMAP4_IOPAD(0x1c2, PIN_INPUT_PULLUP | MUX_MODE7) - OMAP4_IOPAD(0x1c4, PIN_INPUT_PULLUP | MUX_MODE7) - OMAP4_IOPAD(0x1c6, PIN_INPUT_PULLUP | MUX_MODE7) - OMAP4_IOPAD(0x1c8, PIN_INPUT_PULLUP | MUX_MODE7) - >; - }; - - /* - * Note that the v3.0.8 stock userspace dynamically remuxes uart1 - * rts pin probably for PM purposes to PIN_INPUT_PULLUP | MUX_MODE7 - * when not used. If needed, we can add rts pin remux later based - * on power measurements. - */ - uart1_pins: pinmux_uart1_pins { - pinctrl-single,pins = < - /* 0x4a10013c mcspi1_cs2.uart1_cts ag23 */ - OMAP4_IOPAD(0x13c, PIN_INPUT_PULLUP | MUX_MODE1) - - /* 0x4a10013e mcspi1_cs3.uart1_rts ah23 */ - OMAP4_IOPAD(0x13e, MUX_MODE1) - - /* 0x4a100140 uart3_cts_rctx.uart1_tx f27 */ - OMAP4_IOPAD(0x140, PIN_OUTPUT | MUX_MODE1) - - /* 0x4a1001ca dpm_emu14.uart1_rx aa3 */ - OMAP4_IOPAD(0x1ca, PIN_INPUT_PULLUP | MUX_MODE2) - >; - }; - - /* uart3_tx_irtx and uart3_rx_irrx */ - uart3_pins: pinmux_uart3_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x196, MUX_MODE7) - OMAP4_IOPAD(0x198, MUX_MODE7) - OMAP4_IOPAD(0x1b2, PIN_INPUT_PULLUP | MUX_MODE7) - OMAP4_IOPAD(0x1b4, PIN_INPUT_PULLUP | MUX_MODE7) - OMAP4_IOPAD(0x1b6, PIN_INPUT_PULLUP | MUX_MODE7) - OMAP4_IOPAD(0x1b8, PIN_INPUT_PULLUP | MUX_MODE7) - OMAP4_IOPAD(0x1ba, MUX_MODE2) - OMAP4_IOPAD(0x1bc, PIN_INPUT | MUX_MODE2) - OMAP4_IOPAD(0x1be, PIN_INPUT_PULLUP | MUX_MODE7) - OMAP4_IOPAD(0x1c0, PIN_INPUT_PULLUP | MUX_MODE7) - OMAP4_IOPAD(0x1c2, PIN_INPUT_PULLUP | MUX_MODE7) - OMAP4_IOPAD(0x1c4, PIN_INPUT_PULLUP | MUX_MODE7) - OMAP4_IOPAD(0x1c6, PIN_INPUT_PULLUP | MUX_MODE7) - OMAP4_IOPAD(0x1c8, PIN_INPUT_PULLUP | MUX_MODE7) - >; - }; - - uart4_pins: pinmux_uart4_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x15c, PIN_INPUT | MUX_MODE0) /* uart4_rx */ - OMAP4_IOPAD(0x15e, PIN_OUTPUT | MUX_MODE0) /* uart4_tx */ - OMAP4_IOPAD(0x110, PIN_INPUT_PULLUP | MUX_MODE5) /* uart4_cts */ - OMAP4_IOPAD(0x112, PIN_OUTPUT_PULLUP | MUX_MODE5) /* uart4_rts */ - >; - }; - - mcbsp2_pins: pinmux_mcbsp2_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x0f6, PIN_INPUT | MUX_MODE0) /* abe_mcbsp2_clkx */ - OMAP4_IOPAD(0x0f8, PIN_INPUT | MUX_MODE0) /* abe_mcbsp2_dr */ - OMAP4_IOPAD(0x0fa, PIN_OUTPUT | MUX_MODE0) /* abe_mcbsp2_dx */ - OMAP4_IOPAD(0x0fc, PIN_INPUT | MUX_MODE0) /* abe_mcbsp2_fsx */ - >; - }; - - mcbsp3_pins: pinmux_mcbsp3_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x106, PIN_INPUT | MUX_MODE1) /* abe_mcbsp3_dr */ - OMAP4_IOPAD(0x108, PIN_OUTPUT | MUX_MODE1) /* abe_mcbsp3_dx */ - OMAP4_IOPAD(0x10a, PIN_INPUT | MUX_MODE1) /* abe_mcbsp3_clkx */ - OMAP4_IOPAD(0x10c, PIN_INPUT | MUX_MODE1) /* abe_mcbsp3_fsx */ - >; - }; - - vibrator_direction_pin: pinmux_vibrator_direction_pin { - pinctrl-single,pins = < - OMAP4_IOPAD(0x1ce, PIN_OUTPUT | MUX_MODE1) /* dmtimer8_pwm_evt (gpio_27) */ - >; - }; - - vibrator_enable_pin: pinmux_vibrator_enable_pin { - pinctrl-single,pins = < - OMAP4_IOPAD(0X1d0, PIN_OUTPUT | MUX_MODE1) /* dmtimer9_pwm_evt (gpio_28) */ - >; - }; -}; - -&omap4_pmx_wkup { - usb_gpio_mux_sel2: pinmux_usb_gpio_mux_sel2_pins { - /* gpio_wk0 */ - pinctrl-single,pins = < - OMAP4_IOPAD(0x040, PIN_OUTPUT_PULLDOWN | MUX_MODE3) - >; - }; -}; - -/* Configure pwm clock source for timers 8 & 9 */ -&timer8 { - assigned-clocks = <&abe_clkctrl OMAP4_TIMER8_CLKCTRL 24>; - assigned-clock-parents = <&sys_clkin_ck>; -}; - -&timer9 { - assigned-clocks = <&l4_per_clkctrl OMAP4_TIMER9_CLKCTRL 24>; - assigned-clock-parents = <&sys_clkin_ck>; -}; - -/* - * As uart1 is wired to mdm6600 with rts and cts, we can use the cts pin for - * uart1 wakeirq. - */ -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; - interrupts-extended = <&wakeupgen GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH - &omap4_pmx_core 0xfc>; -}; - -&uart3 { - interrupts-extended = <&wakeupgen GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH - &omap4_pmx_core 0x17c>; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&uart4_pins>; - - bluetooth { - compatible = "ti,wl1285-st"; - enable-gpios = <&gpio6 14 GPIO_ACTIVE_HIGH>; /* gpio 174 */ - max-speed = <3686400>; - }; -}; - -&usbhsohci { - phys = <&fsusb1_phy>; - phy-names = "usb"; -}; - -&usbhsehci { - phys = <&hsusb2_phy>; -}; - -&usbhshost { - port1-mode = "ohci-phy-4pin-dpdm"; - port2-mode = "ehci-tll"; -}; - -/* Internal UTMI+ PHY used for OTG, CPCAP ULPI PHY for detection and charger */ -&usb_otg_hs { - interface-type = <1>; - mode = <3>; - power = <50>; -}; - -&i2c4 { - ak8975: magnetometer@c { - compatible = "asahi-kasei,ak8975"; - reg = <0x0c>; - - vdd-supply = <&vhvio>; - - interrupt-parent = <&gpio6>; - interrupts = <15 IRQ_TYPE_EDGE_RISING>; /* gpio175 */ - - rotation-matrix = "-1", "0", "0", - "0", "1", "0", - "0", "0", "-1"; - - }; - - lis3dh: accelerometer@18 { - compatible = "st,lis3dh-accel"; - reg = <0x18>; - - vdd-supply = <&vhvio>; - - interrupt-parent = <&gpio2>; - interrupts = <2 IRQ_TYPE_EDGE_BOTH>; /* gpio34 */ - - rotation-matrix = "0", "-1", "0", - "1", "0", "0", - "0", "0", "1"; - }; -}; - -&mcbsp2 { - #sound-dai-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&mcbsp2_pins>; - status = "okay"; - - mcbsp2_port: port { - cpu_dai2: endpoint { - dai-format = "i2s"; - remote-endpoint = <&cpcap_audio_codec0>; - frame-master = <&cpcap_audio_codec0>; - bitclock-master = <&cpcap_audio_codec0>; - }; - }; -}; - -&mcbsp3 { - #sound-dai-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&mcbsp3_pins>; - status = "okay"; - - mcbsp3_port: port { - cpu_dai3: endpoint { - dai-format = "dsp_a"; - frame-master = <&cpcap_audio_codec1>; - bitclock-master = <&cpcap_audio_codec1>; - remote-endpoint = <&cpcap_audio_codec1>; - }; - }; -}; - -&cpcap_audio_codec0 { - remote-endpoint = <&cpu_dai2>; -}; - -&cpcap_audio_codec1 { - remote-endpoint = <&cpu_dai3>; -}; diff --git a/sys/gnu/dts/arm/omap4-duovero-parlor.dts b/sys/gnu/dts/arm/omap4-duovero-parlor.dts deleted file mode 100644 index 8047e8cdb3a..00000000000 --- a/sys/gnu/dts/arm/omap4-duovero-parlor.dts +++ /dev/null @@ -1,194 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group - */ -/dts-v1/; - -#include "omap4-duovero.dtsi" - -#include - -/ { - model = "OMAP4430 Gumstix Duovero on Parlor"; - compatible = "gumstix,omap4-duovero-parlor", "gumstix,omap4-duovero", "ti,omap4430", "ti,omap4"; - - aliases { - display0 = &hdmi0; - }; - - leds { - compatible = "gpio-leds"; - led0 { - label = "duovero:blue:led0"; - gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>; /* gpio_122 */ - linux,default-trigger = "heartbeat"; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - button0 { - label = "button0"; - linux,code = ; - gpios = <&gpio4 25 GPIO_ACTIVE_LOW>; /* gpio_121 */ - /* Value above 7.95ms for no GPIO hardware debounce */ - debounce-interval = <10>; - wakeup-source; - }; - }; - - hdmi0: connector { - compatible = "hdmi-connector"; - label = "hdmi"; - - type = "d"; - - hpd-gpios = <&gpio2 31 GPIO_ACTIVE_HIGH>; /* gpio_63 */ - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_out>; - }; - }; - }; -}; - -&omap4_pmx_core { - pinctrl-0 = < - &led_pins - &button_pins - &smsc_pins - >; - - led_pins: pinmux_led_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x116, PIN_OUTPUT | MUX_MODE3) /* abe_dmic_din3.gpio_122 */ - >; - }; - - button_pins: pinmux_button_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x114, PIN_INPUT_PULLUP | MUX_MODE3) /* abe_dmic_din2.gpio_121 */ - >; - }; - - i2c2_pins: pinmux_i2c2_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x126, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_scl */ - OMAP4_IOPAD(0x128, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_sda */ - >; - }; - - i2c3_pins: pinmux_i2c3_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x12a, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl */ - OMAP4_IOPAD(0x12c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda */ - >; - }; - - smsc_pins: pinmux_smsc_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x068, PIN_INPUT | MUX_MODE3) /* gpmc_a20.gpio_44: IRQ */ - OMAP4_IOPAD(0x06a, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a21.gpio_45: nReset */ - OMAP4_IOPAD(0x070, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a24.gpio_48: amdix enabled */ - >; - }; - - dss_hdmi_pins: pinmux_dss_hdmi_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x098, PIN_INPUT | MUX_MODE3) /* hdmi_hpd.gpio_63 */ - OMAP4_IOPAD(0x09a, PIN_INPUT | MUX_MODE0) /* hdmi_cec.hdmi_cec */ - OMAP4_IOPAD(0x09c, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_ddc_scl.hdmi_ddc_scl */ - OMAP4_IOPAD(0x09e, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_ddc_sda.hdmi_ddc_sda */ - >; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - - clock-frequency = <400000>; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_pins>; - - clock-frequency = <100000>; - - /* optional 1K EEPROM with revision information */ - eeprom@51 { - compatible = "atmel,24c01"; - reg = <0x51>; - pagesize = <8>; - }; -}; - -&mmc3 { - status = "disabled"; -}; - -#include "omap-gpmc-smsc911x.dtsi" - -&gpmc { - ranges = <5 0 0x2c000000 0x1000000>; /* CS5 */ - - ethernet@gpmc { - reg = <5 0 0xff>; - interrupt-parent = <&gpio2>; - interrupts = <12 IRQ_TYPE_EDGE_FALLING>; /* gpio_44 */ - - phy-mode = "mii"; - - gpmc,cs-on-ns = <10>; - gpmc,cs-rd-off-ns = <50>; - gpmc,cs-wr-off-ns = <50>; - gpmc,adv-on-ns = <0>; - gpmc,adv-rd-off-ns = <10>; - gpmc,adv-wr-off-ns = <10>; - gpmc,oe-on-ns = <15>; - gpmc,oe-off-ns = <50>; - gpmc,we-on-ns = <15>; - gpmc,we-off-ns = <50>; - gpmc,rd-cycle-ns = <50>; - gpmc,wr-cycle-ns = <50>; - gpmc,access-ns = <50>; - gpmc,page-burst-access-ns = <0>; - gpmc,bus-turnaround-ns = <35>; - gpmc,cycle2cycle-delay-ns = <35>; - gpmc,wr-data-mux-bus-ns = <35>; - gpmc,wr-access-ns = <50>; - - gpmc,mux-add-data = <2>; - gpmc,sync-read; - gpmc,sync-write; - gpmc,clk-activation-ns = <5>; - gpmc,sync-clk-ps = <20000>; - }; -}; - -&dss { - status = "ok"; -}; - -&hdmi { - status = "ok"; - vdda-supply = <&vdac>; - - pinctrl-names = "default"; - pinctrl-0 = <&dss_hdmi_pins>; - - port { - hdmi_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; - }; -}; - -&uart3 { - interrupts-extended = <&wakeupgen GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH - &omap4_pmx_core OMAP4_UART3_RX>; -}; diff --git a/sys/gnu/dts/arm/omap4-duovero.dtsi b/sys/gnu/dts/arm/omap4-duovero.dtsi deleted file mode 100644 index 805dfd40030..00000000000 --- a/sys/gnu/dts/arm/omap4-duovero.dtsi +++ /dev/null @@ -1,249 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group - */ - -#include "omap443x.dtsi" -#include "omap4-mcpdm.dtsi" - -/ { - model = "Gumstix Duovero"; - compatible = "gumstix,omap4-duovero", "ti,omap4430", "ti,omap4"; - - chosen { - stdout-path = &uart3; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x40000000>; /* 1 GB */ - }; - - sound { - compatible = "ti,abe-twl6040"; - ti,model = "DuoVero"; - - ti,mclk-freq = <38400000>; - - ti,mcpdm = <&mcpdm>; - - ti,twl6040 = <&twl6040>; - - /* Audio routing */ - ti,audio-routing = - "Headset Stereophone", "HSOL", - "Headset Stereophone", "HSOR", - "HSMIC", "Headset Mic", - "Headset Mic", "Headset Mic Bias"; - }; - - /* HS USB Host PHY on PORT 1 */ - hsusb1_phy: hsusb1_phy { - compatible = "usb-nop-xceiv"; - reset-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>; /* gpio_62 */ - #phy-cells = <0>; - - pinctrl-names = "default"; - pinctrl-0 = <&hsusb1phy_pins>; - - clocks = <&auxclk3_ck>; - clock-names = "main_clk"; - clock-frequency = <19200000>; - }; - - /* regulator for w2cbw0015 on sdio5 */ - w2cbw0015_vmmc: w2cbw0015_vmmc { - pinctrl-names = "default"; - pinctrl-0 = <&w2cbw0015_pins>; - compatible = "regulator-fixed"; - regulator-name = "w2cbw0015"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - gpio = <&gpio2 11 GPIO_ACTIVE_LOW>; /* gpio_43 */ - startup-delay-us = <70000>; - enable-active-high; - regulator-boot-on; - }; -}; - -&omap4_pmx_core { - pinctrl-names = "default"; - pinctrl-0 = < - &twl6040_pins - &hsusbb1_pins - >; - - twl6040_pins: pinmux_twl6040_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x166, PIN_OUTPUT | MUX_MODE3) /* usbb2_ulpitll_nxt.gpio_160 */ - OMAP4_IOPAD(0x1a0, PIN_INPUT | MUX_MODE0) /* sys_nirq2.sys_nirq2 */ - >; - }; - - mcbsp1_pins: pinmux_mcbsp1_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x0fe, PIN_INPUT | MUX_MODE0) /* abe_mcbsp1_clkx.abe_mcbsp1_clkx */ - OMAP4_IOPAD(0x100, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp1_dr.abe_mcbsp1_dr */ - OMAP4_IOPAD(0x102, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp1_dx.abe_mcbsp1_dx */ - OMAP4_IOPAD(0x104, PIN_INPUT | MUX_MODE0) /* abe_mcbsp1_fsx.abe_mcbsp1_fsx */ - >; - }; - - hsusbb1_pins: pinmux_hsusbb1_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x0c2, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_clk.usbb1_ulpiphy_clk */ - OMAP4_IOPAD(0x0c4, PIN_OUTPUT | MUX_MODE4) /* usbb1_ulpitll_stp.usbb1_ulpiphy_stp */ - OMAP4_IOPAD(0x0c6, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dir.usbb1_ulpiphy_dir */ - OMAP4_IOPAD(0x0c8, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_nxt.usbb1_ulpiphy_nxt */ - OMAP4_IOPAD(0x0ca, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat0.usbb1_ulpiphy_dat0 */ - OMAP4_IOPAD(0x0cc, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat1.usbb1_ulpiphy_dat1 */ - OMAP4_IOPAD(0x0ce, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat2.usbb1_ulpiphy_dat2 */ - OMAP4_IOPAD(0x0d0, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat3.usbb1_ulpiphy_dat3 */ - OMAP4_IOPAD(0x0d2, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat4.usbb1_ulpiphy_dat4 */ - OMAP4_IOPAD(0x0d4, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat5.usbb1_ulpiphy_dat5 */ - OMAP4_IOPAD(0x0d6, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat6.usbb1_ulpiphy_dat6 */ - OMAP4_IOPAD(0x0d8, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat7.usbb1_ulpiphy_dat7 */ - >; - }; - - hsusb1phy_pins: pinmux_hsusb1phy_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x08c, PIN_OUTPUT | MUX_MODE3) /* gpmc_wait1.gpio_62 */ - >; - }; - - w2cbw0015_pins: pinmux_w2cbw0015_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x066, PIN_OUTPUT | MUX_MODE3) /* gpmc_a19.gpio_43 */ - OMAP4_IOPAD(0x07a, PIN_INPUT | MUX_MODE3) /* gpmc_ncs3.gpio_53 */ - >; - }; - - i2c1_pins: pinmux_i2c1_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x122, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */ - OMAP4_IOPAD(0x124, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */ - >; - }; - - i2c4_pins: pinmux_i2c4_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x12e, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_scl */ - OMAP4_IOPAD(0x130, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_sda */ - >; - }; - - mmc1_pins: pinmux_mmc1_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x0e2, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk */ - OMAP4_IOPAD(0x0e4, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmcc1_cmd */ - OMAP4_IOPAD(0x0e6, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmcc1_dat0 */ - OMAP4_IOPAD(0x0e8, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1 */ - OMAP4_IOPAD(0x0ea, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2 */ - OMAP4_IOPAD(0x0ec, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3 */ - >; - }; - - mmc5_pins: pinmux_mmc5_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_clk */ - OMAP4_IOPAD(0x14a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmcc5_cmd */ - OMAP4_IOPAD(0x14c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmcc5_dat0 */ - OMAP4_IOPAD(0x14e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat1 */ - OMAP4_IOPAD(0x150, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat2 */ - OMAP4_IOPAD(0x152, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat3 */ - >; - }; -}; - -/* PMIC */ -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - - clock-frequency = <400000>; - - twl: twl@48 { - reg = <0x48>; - interrupts = ; /* IRQ_SYS_1N cascaded to gic */ - }; - - twl6040: twl@4b { - compatible = "ti,twl6040"; - #clock-cells = <0>; - reg = <0x4b>; - interrupts = ; /* IRQ_SYS_2N cascaded to gic */ - ti,audpwron-gpio = <&gpio6 0 GPIO_ACTIVE_HIGH>; /* gpio_160 */ - - vio-supply = <&v1v8>; - v2v1-supply = <&v2v1>; - enable-active-high; - }; -}; - -#include "twl6030.dtsi" -#include "twl6030_omap4.dtsi" - -/* on-board bluetooth / WiFi module */ -&i2c4 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_pins>; - - clock-frequency = <400000>; -}; - -&mcbsp1 { - pinctrl-names = "default"; - pinctrl-0 = <&mcbsp1_pins>; - status = "okay"; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - - vmmc-supply = <&vmmc>; - ti,bus-width = <4>; - ti,non-removable; /* FIXME: use PMIC_MMC detect */ -}; - -&mmc2 { - status = "disabled"; -}; - -/* mmc3 is available to the expansion board */ - -&mmc4 { - status = "disabled"; -}; - -/* on-board WiFi module */ -&mmc5 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc5_pins>; - - vmmc-supply = <&w2cbw0015_vmmc>; - ti,bus-width = <4>; - ti,non-removable; - cap-power-off-card; - keep-power-in-suspend; -}; - -&twl_usb_comparator { - usb-supply = <&vusb>; -}; - -&usb_otg_hs { - interface-type = <1>; - mode = <3>; - power = <50>; -}; - -&usbhshost { - port1-mode = "ehci-phy"; -}; - -&usbhsehci { - phys = <&hsusb1_phy>; -}; - diff --git a/sys/gnu/dts/arm/omap4-kc1.dts b/sys/gnu/dts/arm/omap4-kc1.dts deleted file mode 100644 index 31d856b58f8..00000000000 --- a/sys/gnu/dts/arm/omap4-kc1.dts +++ /dev/null @@ -1,179 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2016 Paul Kocialkowski - */ -/dts-v1/; - -#include "omap443x.dtsi" - -/ { - model = "Amazon Kindle Fire (first generation)"; - compatible = "amazon,omap4-kc1", "ti,omap4430", "ti,omap4"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000>; /* 512 MB */ - }; - - pwmleds { - compatible = "pwm-leds"; - - green { - label = "green"; - pwms = <&twl_pwm 0 7812500>; - max-brightness = <127>; - }; - - orange { - label = "orange"; - pwms = <&twl_pwm 1 7812500>; - max-brightness = <127>; - }; - }; -}; - -&omap4_pmx_core { - pinctrl-names = "default"; - - uart3_pins: pinmux_uart3_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x144, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx */ - OMAP4_IOPAD(0x146, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx */ - >; - }; - - i2c1_pins: pinmux_i2c1_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x122, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */ - OMAP4_IOPAD(0x124, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */ - >; - }; - - i2c2_pins: pinmux_i2c2_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x126, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_scl */ - OMAP4_IOPAD(0x128, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_sda */ - >; - }; - - i2c3_pins: pinmux_i2c3_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x12a, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl */ - OMAP4_IOPAD(0x12c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda */ - >; - }; - - i2c4_pins: pinmux_i2c4_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x12e, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_scl */ - OMAP4_IOPAD(0x130, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_sda */ - >; - }; - - mmc2_pins: pinmux_mmc2_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x040, PIN_INPUT_PULLUP | MUX_MODE1) /* sdmmc2_dat0 */ - OMAP4_IOPAD(0x042, PIN_INPUT_PULLUP | MUX_MODE1) /* sdmmc2_dat1 */ - OMAP4_IOPAD(0x044, PIN_INPUT_PULLUP | MUX_MODE1) /* sdmmc2_dat2 */ - OMAP4_IOPAD(0x046, PIN_INPUT_PULLUP | MUX_MODE1) /* sdmmc2_dat3 */ - OMAP4_IOPAD(0x048, PIN_INPUT_PULLUP | MUX_MODE1) /* sdmmc2_dat4 */ - OMAP4_IOPAD(0x04a, PIN_INPUT_PULLUP | MUX_MODE1) /* sdmmc2_dat5 */ - OMAP4_IOPAD(0x04c, PIN_INPUT_PULLUP | MUX_MODE1) /* sdmmc2_dat6 */ - OMAP4_IOPAD(0x04e, PIN_INPUT_PULLUP | MUX_MODE1) /* sdmmc2_dat7 */ - OMAP4_IOPAD(0x082, PIN_INPUT_PULLUP | MUX_MODE1) /* sdmmc2_clk */ - OMAP4_IOPAD(0x084, PIN_INPUT_PULLUP | MUX_MODE1) /* sdmmc2_cmd */ - >; - }; - - usb_otg_hs_pins: pinmux_usb_otg_hs_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x194, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* usba0_otg_ce */ - OMAP4_IOPAD(0x196, PIN_INPUT | MUX_MODE0) /* usba0_otg_dp */ - OMAP4_IOPAD(0x198, PIN_INPUT | MUX_MODE0) /* usba0_otg_dm */ - >; - }; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; - - interrupts-extended = <&wakeupgen GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH - &omap4_pmx_core OMAP4_UART3_RX>; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - - clock-frequency = <400000>; - - twl: twl@48 { - reg = <0x48>; - /* IRQ# = 7 */ - interrupts = ; /* IRQ_SYS_1N cascaded to gic */ - - twl_power: power { - compatible = "ti,twl6030-power"; - ti,system-power-controller; - }; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - - clock-frequency = <400000>; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_pins>; - - clock-frequency = <400000>; -}; - -&i2c4 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_pins>; - - clock-frequency = <400000>; -}; - -&mmc1 { - status = "disabled"; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; - - vmmc-supply = <&vaux1>; - ti,non-removable; - bus-width = <8>; -}; - -&mmc3 { - status = "disabled"; -}; - -&mmc4 { - status = "disabled"; -}; - -&usb_otg_hs { - pinctrl-names = "default"; - pinctrl-0 = <&usb_otg_hs_pins>; - - interface-type = <1>; - mode = <3>; - power = <50>; -}; - -#include "twl6030.dtsi" -#include "twl6030_omap4.dtsi" - -&twl_usb_comparator { - usb-supply = <&vusb>; -}; diff --git a/sys/gnu/dts/arm/omap4-l4-abe.dtsi b/sys/gnu/dts/arm/omap4-l4-abe.dtsi deleted file mode 100644 index 8e6662bb9e8..00000000000 --- a/sys/gnu/dts/arm/omap4-l4-abe.dtsi +++ /dev/null @@ -1,500 +0,0 @@ -&l4_abe { /* 0x40100000 */ - compatible = "ti,omap4-l4-abe", "simple-bus"; - reg = <0x40100000 0x400>, - <0x40100400 0x400>; - reg-names = "la", "ap"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x40100000 0x100000>, /* segment 0 */ - <0x49000000 0x49000000 0x100000>; - segment@0 { /* 0x40100000 */ - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = - /* CPU to L4 ABE mapping */ - <0x00000000 0x00000000 0x000400>, /* ap 0 */ - <0x00000400 0x00000400 0x000400>, /* ap 1 */ - <0x00022000 0x00022000 0x001000>, /* ap 2 */ - <0x00023000 0x00023000 0x001000>, /* ap 3 */ - <0x00024000 0x00024000 0x001000>, /* ap 4 */ - <0x00025000 0x00025000 0x001000>, /* ap 5 */ - <0x00026000 0x00026000 0x001000>, /* ap 6 */ - <0x00027000 0x00027000 0x001000>, /* ap 7 */ - <0x00028000 0x00028000 0x001000>, /* ap 8 */ - <0x00029000 0x00029000 0x001000>, /* ap 9 */ - <0x0002a000 0x0002a000 0x001000>, /* ap 10 */ - <0x0002b000 0x0002b000 0x001000>, /* ap 11 */ - <0x0002e000 0x0002e000 0x001000>, /* ap 12 */ - <0x0002f000 0x0002f000 0x001000>, /* ap 13 */ - <0x00030000 0x00030000 0x001000>, /* ap 14 */ - <0x00031000 0x00031000 0x001000>, /* ap 15 */ - <0x00032000 0x00032000 0x001000>, /* ap 16 */ - <0x00033000 0x00033000 0x001000>, /* ap 17 */ - <0x00038000 0x00038000 0x001000>, /* ap 18 */ - <0x00039000 0x00039000 0x001000>, /* ap 19 */ - <0x0003a000 0x0003a000 0x001000>, /* ap 20 */ - <0x0003b000 0x0003b000 0x001000>, /* ap 21 */ - <0x0003c000 0x0003c000 0x001000>, /* ap 22 */ - <0x0003d000 0x0003d000 0x001000>, /* ap 23 */ - <0x0003e000 0x0003e000 0x001000>, /* ap 24 */ - <0x0003f000 0x0003f000 0x001000>, /* ap 25 */ - <0x00080000 0x00080000 0x010000>, /* ap 26 */ - <0x00080000 0x00080000 0x001000>, /* ap 27 */ - <0x000a0000 0x000a0000 0x010000>, /* ap 28 */ - <0x000a0000 0x000a0000 0x001000>, /* ap 29 */ - <0x000c0000 0x000c0000 0x010000>, /* ap 30 */ - <0x000c0000 0x000c0000 0x001000>, /* ap 31 */ - <0x000f1000 0x000f1000 0x001000>, /* ap 32 */ - <0x000f2000 0x000f2000 0x001000>, /* ap 33 */ - - /* L3 to L4 ABE mapping */ - <0x49000000 0x49000000 0x000400>, /* ap 0 */ - <0x49000400 0x49000400 0x000400>, /* ap 1 */ - <0x49022000 0x49022000 0x001000>, /* ap 2 */ - <0x49023000 0x49023000 0x001000>, /* ap 3 */ - <0x49024000 0x49024000 0x001000>, /* ap 4 */ - <0x49025000 0x49025000 0x001000>, /* ap 5 */ - <0x49026000 0x49026000 0x001000>, /* ap 6 */ - <0x49027000 0x49027000 0x001000>, /* ap 7 */ - <0x49028000 0x49028000 0x001000>, /* ap 8 */ - <0x49029000 0x49029000 0x001000>, /* ap 9 */ - <0x4902a000 0x4902a000 0x001000>, /* ap 10 */ - <0x4902b000 0x4902b000 0x001000>, /* ap 11 */ - <0x4902e000 0x4902e000 0x001000>, /* ap 12 */ - <0x4902f000 0x4902f000 0x001000>, /* ap 13 */ - <0x49030000 0x49030000 0x001000>, /* ap 14 */ - <0x49031000 0x49031000 0x001000>, /* ap 15 */ - <0x49032000 0x49032000 0x001000>, /* ap 16 */ - <0x49033000 0x49033000 0x001000>, /* ap 17 */ - <0x49038000 0x49038000 0x001000>, /* ap 18 */ - <0x49039000 0x49039000 0x001000>, /* ap 19 */ - <0x4903a000 0x4903a000 0x001000>, /* ap 20 */ - <0x4903b000 0x4903b000 0x001000>, /* ap 21 */ - <0x4903c000 0x4903c000 0x001000>, /* ap 22 */ - <0x4903d000 0x4903d000 0x001000>, /* ap 23 */ - <0x4903e000 0x4903e000 0x001000>, /* ap 24 */ - <0x4903f000 0x4903f000 0x001000>, /* ap 25 */ - <0x49080000 0x49080000 0x010000>, /* ap 26 */ - <0x49080000 0x49080000 0x001000>, /* ap 27 */ - <0x490a0000 0x490a0000 0x010000>, /* ap 28 */ - <0x490a0000 0x490a0000 0x001000>, /* ap 29 */ - <0x490c0000 0x490c0000 0x010000>, /* ap 30 */ - <0x490c0000 0x490c0000 0x001000>, /* ap 31 */ - <0x490f1000 0x490f1000 0x001000>, /* ap 32 */ - <0x490f2000 0x490f2000 0x001000>; /* ap 33 */ - - target-module@22000 { /* 0x40122000, ap 2 02.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "mcbsp1"; - reg = <0x2208c 0x4>; - reg-names = "sysc"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET)>; - ti,sysc-sidle = , - , - ; - /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ - clocks = <&abe_clkctrl OMAP4_MCBSP1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x22000 0x1000>, - <0x49022000 0x49022000 0x1000>; - - mcbsp1: mcbsp@0 { - compatible = "ti,omap4-mcbsp"; - reg = <0x0 0xff>, /* MPU private access */ - <0x49022000 0xff>; /* L3 Interconnect */ - reg-names = "mpu", "dma"; - interrupts = ; - interrupt-names = "common"; - ti,buffer-size = <128>; - dmas = <&sdma 33>, - <&sdma 34>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - }; - - target-module@24000 { /* 0x40124000, ap 4 04.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "mcbsp2"; - reg = <0x2408c 0x4>; - reg-names = "sysc"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET)>; - ti,sysc-sidle = , - , - ; - /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ - clocks = <&abe_clkctrl OMAP4_MCBSP2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x24000 0x1000>, - <0x49024000 0x49024000 0x1000>; - - mcbsp2: mcbsp@0 { - compatible = "ti,omap4-mcbsp"; - reg = <0x0 0xff>, /* MPU private access */ - <0x49024000 0xff>; /* L3 Interconnect */ - reg-names = "mpu", "dma"; - interrupts = ; - interrupt-names = "common"; - ti,buffer-size = <128>; - dmas = <&sdma 17>, - <&sdma 18>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - }; - - target-module@26000 { /* 0x40126000, ap 6 06.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "mcbsp3"; - reg = <0x2608c 0x4>; - reg-names = "sysc"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET)>; - ti,sysc-sidle = , - , - ; - /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ - clocks = <&abe_clkctrl OMAP4_MCBSP3_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x26000 0x1000>, - <0x49026000 0x49026000 0x1000>; - - mcbsp3: mcbsp@0 { - compatible = "ti,omap4-mcbsp"; - reg = <0x0 0xff>, /* MPU private access */ - <0x49026000 0xff>; /* L3 Interconnect */ - reg-names = "mpu", "dma"; - interrupts = ; - interrupt-names = "common"; - ti,buffer-size = <128>; - dmas = <&sdma 19>, - <&sdma 20>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - }; - - target-module@28000 { /* 0x40128000, ap 8 08.0 */ - compatible = "ti,sysc-mcasp", "ti,sysc"; - ti,hwmods = "mcasp"; - reg = <0x28000 0x4>, - <0x28004 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ - clocks = <&abe_clkctrl OMAP4_MCASP_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x28000 0x1000>, - <0x49028000 0x49028000 0x1000>; - - /* - * Child device unsupported by davinci-mcasp. At least - * RX path is disabled for omap4, and only DIT mode - * works with no I2S. See also old Android kernel - * omap-mcasp driver for more information. - */ - }; - - target-module@2a000 { /* 0x4012a000, ap 10 0a.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2a000 0x1000>, - <0x4902a000 0x4902a000 0x1000>; - }; - - target-module@2e000 { /* 0x4012e000, ap 12 0c.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - ti,hwmods = "dmic"; - reg = <0x2e000 0x4>, - <0x2e010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ - clocks = <&abe_clkctrl OMAP4_DMIC_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2e000 0x1000>, - <0x4902e000 0x4902e000 0x1000>; - - dmic: dmic@0 { - compatible = "ti,omap4-dmic"; - reg = <0x0 0x7f>, /* MPU private access */ - <0x4902e000 0x7f>; /* L3 Interconnect */ - reg-names = "mpu", "dma"; - interrupts = ; - dmas = <&sdma 67>; - dma-names = "up_link"; - status = "disabled"; - }; - }; - - target-module@30000 { /* 0x40130000, ap 14 0e.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x30000 0x4>, - <0x30010 0x4>, - <0x30014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_EMUFREE | - SYSC_OMAP2_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ - clocks = <&abe_clkctrl OMAP4_WD_TIMER3_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x30000 0x1000>, - <0x49030000 0x49030000 0x1000>; - - wdt3: wdt@0 { - compatible = "ti,omap4-wdt", "ti,omap3-wdt"; - reg = <0x0 0x80>; - interrupts = ; - }; - }; - - mcpdm_module: target-module@32000 { /* 0x40132000, ap 16 10.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - ti,hwmods = "mcpdm"; - reg = <0x32000 0x4>, - <0x32010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ - clocks = <&abe_clkctrl OMAP4_MCPDM_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x32000 0x1000>, - <0x49032000 0x49032000 0x1000>; - - /* Must be only enabled for boards with pdmclk wired */ - status = "disabled"; - - mcpdm: mcpdm@0 { - compatible = "ti,omap4-mcpdm"; - reg = <0x0 0x7f>, /* MPU private access */ - <0x49032000 0x7f>; /* L3 Interconnect */ - reg-names = "mpu", "dma"; - interrupts = ; - dmas = <&sdma 65>, - <&sdma 66>; - dma-names = "up_link", "dn_link"; - }; - }; - - target-module@38000 { /* 0x40138000, ap 18 12.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - ti,hwmods = "timer5"; - reg = <0x38000 0x4>, - <0x38010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ - clocks = <&abe_clkctrl OMAP4_TIMER5_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x38000 0x1000>, - <0x49038000 0x49038000 0x1000>; - - timer5: timer@0 { - compatible = "ti,omap4430-timer"; - reg = <0x00000000 0x80>, - <0x49038000 0x80>; - clocks = <&abe_clkctrl OMAP4_TIMER5_CLKCTRL 24>; - clock-names = "fck"; - interrupts = ; - ti,timer-dsp; - }; - }; - - target-module@3a000 { /* 0x4013a000, ap 20 14.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - ti,hwmods = "timer6"; - reg = <0x3a000 0x4>, - <0x3a010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ - clocks = <&abe_clkctrl OMAP4_TIMER6_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x3a000 0x1000>, - <0x4903a000 0x4903a000 0x1000>; - - timer6: timer@0 { - compatible = "ti,omap4430-timer"; - reg = <0x00000000 0x80>, - <0x4903a000 0x80>; - clocks = <&abe_clkctrl OMAP4_TIMER6_CLKCTRL 24>; - clock-names = "fck"; - interrupts = ; - ti,timer-dsp; - }; - }; - - target-module@3c000 { /* 0x4013c000, ap 22 16.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - ti,hwmods = "timer7"; - reg = <0x3c000 0x4>, - <0x3c010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ - clocks = <&abe_clkctrl OMAP4_TIMER7_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x3c000 0x1000>, - <0x4903c000 0x4903c000 0x1000>; - - timer7: timer@0 { - compatible = "ti,omap4430-timer"; - reg = <0x00000000 0x80>, - <0x4903c000 0x80>; - clocks = <&abe_clkctrl OMAP4_TIMER7_CLKCTRL 24>; - clock-names = "fck"; - interrupts = ; - ti,timer-dsp; - }; - }; - - target-module@3e000 { /* 0x4013e000, ap 24 18.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - ti,hwmods = "timer8"; - reg = <0x3e000 0x4>, - <0x3e010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ - clocks = <&abe_clkctrl OMAP4_TIMER8_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x3e000 0x1000>, - <0x4903e000 0x4903e000 0x1000>; - - timer8: timer@0 { - compatible = "ti,omap4430-timer"; - reg = <0x00000000 0x80>, - <0x4903e000 0x80>; - clocks = <&abe_clkctrl OMAP4_TIMER8_CLKCTRL 24>; - clock-names = "fck"; - interrupts = ; - ti,timer-pwm; - ti,timer-dsp; - }; - }; - - target-module@80000 { /* 0x40180000, ap 26 1a.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x80000 0x10000>, - <0x49080000 0x49080000 0x10000>; - }; - - target-module@a0000 { /* 0x401a0000, ap 28 1c.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xa0000 0x10000>, - <0x490a0000 0x490a0000 0x10000>; - }; - - target-module@c0000 { /* 0x401c0000, ap 30 1e.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xc0000 0x10000>, - <0x490c0000 0x490c0000 0x10000>; - }; - - target-module@f1000 { /* 0x401f1000, ap 32 20.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - ti,hwmods = "aess"; - reg = <0xf1000 0x4>, - <0xf1010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-midle = , - , - , - ; - ti,sysc-sidle = , - , - ; - /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ - clocks = <&abe_clkctrl OMAP4_AESS_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xf1000 0x1000>, - <0x490f1000 0x490f1000 0x1000>; - - /* - * No child device binding or driver in mainline. - * See Android tree and related upstreaming efforts - * for the old driver. - */ - }; - }; -}; - diff --git a/sys/gnu/dts/arm/omap4-l4.dtsi b/sys/gnu/dts/arm/omap4-l4.dtsi deleted file mode 100644 index d60d5e0ecc4..00000000000 --- a/sys/gnu/dts/arm/omap4-l4.dtsi +++ /dev/null @@ -1,2456 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -&l4_cfg { /* 0x4a000000 */ - compatible = "ti,omap4-l4-cfg", "simple-bus"; - reg = <0x4a000000 0x800>, - <0x4a000800 0x800>, - <0x4a001000 0x1000>; - reg-names = "ap", "la", "ia0"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x4a000000 0x080000>, /* segment 0 */ - <0x00080000 0x4a080000 0x080000>, /* segment 1 */ - <0x00100000 0x4a100000 0x080000>, /* segment 2 */ - <0x00180000 0x4a180000 0x080000>, /* segment 3 */ - <0x00200000 0x4a200000 0x080000>, /* segment 4 */ - <0x00280000 0x4a280000 0x080000>, /* segment 5 */ - <0x00300000 0x4a300000 0x080000>; /* segment 6 */ - - segment@0 { /* 0x4a000000 */ - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ - <0x00001000 0x00001000 0x001000>, /* ap 1 */ - <0x00000800 0x00000800 0x000800>, /* ap 2 */ - <0x00002000 0x00002000 0x001000>, /* ap 3 */ - <0x00003000 0x00003000 0x001000>, /* ap 4 */ - <0x00004000 0x00004000 0x001000>, /* ap 5 */ - <0x00005000 0x00005000 0x001000>, /* ap 6 */ - <0x00056000 0x00056000 0x001000>, /* ap 7 */ - <0x00057000 0x00057000 0x001000>, /* ap 8 */ - <0x0005c000 0x0005c000 0x001000>, /* ap 9 */ - <0x00058000 0x00058000 0x004000>, /* ap 10 */ - <0x00062000 0x00062000 0x001000>, /* ap 11 */ - <0x00063000 0x00063000 0x001000>, /* ap 12 */ - <0x00008000 0x00008000 0x002000>, /* ap 23 */ - <0x0000a000 0x0000a000 0x001000>, /* ap 24 */ - <0x00066000 0x00066000 0x001000>, /* ap 25 */ - <0x00067000 0x00067000 0x001000>, /* ap 26 */ - <0x0005e000 0x0005e000 0x002000>, /* ap 80 */ - <0x00060000 0x00060000 0x001000>, /* ap 81 */ - <0x00064000 0x00064000 0x001000>, /* ap 86 */ - <0x00065000 0x00065000 0x001000>; /* ap 87 */ - - target-module@2000 { /* 0x4a002000, ap 3 06.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - ti,hwmods = "ctrl_module_core"; - reg = <0x2000 0x4>, - <0x2010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): core, core_pwrdm, l4_cfg_clkdm */ - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2000 0x1000>; - - omap4_scm_core: scm@0 { - compatible = "ti,omap4-scm-core", "simple-bus"; - reg = <0x0 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x1000>; - - scm_conf: scm_conf@0 { - compatible = "syscon"; - reg = <0x0 0x800>; - #address-cells = <1>; - #size-cells = <1>; - }; - - omap_control_usb2phy: control-phy@300 { - compatible = "ti,control-phy-usb2"; - reg = <0x300 0x4>; - reg-names = "power"; - }; - - omap_control_usbotg: control-phy@33c { - compatible = "ti,control-phy-otghs"; - reg = <0x33c 0x4>; - reg-names = "otghs_control"; - }; - }; - }; - - target-module@4000 { /* 0x4a004000, ap 5 02.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x4000 0x4>; - reg-names = "rev"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x4000 0x1000>; - - cm1: cm1@0 { - compatible = "ti,omap4-cm1", "simple-bus"; - reg = <0x0 0x2000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x2000>; - - cm1_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - cm1_clockdomains: clockdomains { - }; - }; - }; - - target-module@8000 { /* 0x4a008000, ap 23 32.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x8000 0x4>; - reg-names = "rev"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x8000 0x2000>; - - cm2: cm2@0 { - compatible = "ti,omap4-cm2", "simple-bus"; - reg = <0x0 0x2000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x2000>; - - cm2_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - cm2_clockdomains: clockdomains { - }; - }; - }; - - target-module@56000 { /* 0x4a056000, ap 7 0a.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "dma_system"; - reg = <0x56000 0x4>, - <0x5602c 0x4>, - <0x56028 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_EMUFREE | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-midle = , - , - ; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, core_pwrdm, l3_dma_clkdm */ - clocks = <&l3_dma_clkctrl OMAP4_DMA_SYSTEM_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x56000 0x1000>; - - sdma: dma-controller@0 { - compatible = "ti,omap4430-sdma"; - reg = <0x0 0x1000>; - interrupts = , - , - , - ; - #dma-cells = <1>; - dma-channels = <32>; - dma-requests = <127>; - }; - }; - - target-module@58000 { /* 0x4a058000, ap 10 0e.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "hsi"; - reg = <0x58000 0x4>, - <0x58010 0x4>, - <0x58014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_EMUFREE | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-midle = , - , - , - ; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */ - clocks = <&l3_init_clkctrl OMAP4_HSI_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x58000 0x5000>; - - hsi: hsi@0 { - compatible = "ti,omap4-hsi"; - reg = <0x0 0x4000>, - <0x5000 0x1000>; - reg-names = "sys", "gdd"; - - clocks = <&l3_init_clkctrl OMAP4_HSI_CLKCTRL 0>; - clock-names = "hsi_fck"; - - interrupts = ; - interrupt-names = "gdd_mpu"; - - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x4000>; - - hsi_port1: hsi-port@2000 { - compatible = "ti,omap4-hsi-port"; - reg = <0x2000 0x800>, - <0x2800 0x800>; - reg-names = "tx", "rx"; - interrupts = ; - }; - - hsi_port2: hsi-port@3000 { - compatible = "ti,omap4-hsi-port"; - reg = <0x3000 0x800>, - <0x3800 0x800>; - reg-names = "tx", "rx"; - interrupts = ; - }; - }; - }; - - target-module@5e000 { /* 0x4a05e000, ap 80 68.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x5e000 0x2000>; - }; - - target-module@62000 { /* 0x4a062000, ap 11 16.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "usb_tll_hs"; - reg = <0x62000 0x4>, - <0x62010 0x4>, - <0x62014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - ; - /* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */ - clocks = <&l3_init_clkctrl OMAP4_USB_TLL_HS_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x62000 0x1000>; - - usbhstll: usbhstll@0 { - compatible = "ti,usbhs-tll"; - reg = <0x0 0x1000>; - interrupts = ; - }; - }; - - target-module@64000 { /* 0x4a064000, ap 86 1e.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - ti,hwmods = "usb_host_hs"; - reg = <0x64000 0x4>, - <0x64010 0x4>, - <0x64014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = ; - ti,sysc-midle = , - , - , - ; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */ - clocks = <&l3_init_clkctrl OMAP4_USB_HOST_HS_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x64000 0x1000>; - - usbhshost: usbhshost@0 { - compatible = "ti,usbhs-host"; - reg = <0x0 0x800>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x1000>; - clocks = <&init_60m_fclk>, - <&xclk60mhsp1_ck>, - <&xclk60mhsp2_ck>; - clock-names = "refclk_60m_int", - "refclk_60m_ext_p1", - "refclk_60m_ext_p2"; - - usbhsohci: ohci@800 { - compatible = "ti,ohci-omap3"; - reg = <0x800 0x400>; - interrupts = ; - remote-wakeup-connected; - }; - - usbhsehci: ehci@c00 { - compatible = "ti,ehci-omap"; - reg = <0xc00 0x400>; - interrupts = ; - }; - }; - }; - - target-module@66000 { /* 0x4a066000, ap 25 26.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "mmu_dsp"; - reg = <0x66000 0x4>, - <0x66010 0x4>, - <0x66014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - ; - /* Domains (V, P, C): iva, tesla_pwrdm, tesla_clkdm */ - clocks = <&tesla_clkctrl OMAP4_DSP_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x66000 0x1000>; - - /* mmu_dsp cannot be moved before reset driver */ - status = "disabled"; - }; - }; - - segment@80000 { /* 0x4a080000 */ - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00059000 0x000d9000 0x001000>, /* ap 13 */ - <0x0005a000 0x000da000 0x001000>, /* ap 14 */ - <0x0005b000 0x000db000 0x001000>, /* ap 15 */ - <0x0005c000 0x000dc000 0x001000>, /* ap 16 */ - <0x0005d000 0x000dd000 0x001000>, /* ap 17 */ - <0x0005e000 0x000de000 0x001000>, /* ap 18 */ - <0x00060000 0x000e0000 0x001000>, /* ap 19 */ - <0x00061000 0x000e1000 0x001000>, /* ap 20 */ - <0x00074000 0x000f4000 0x001000>, /* ap 27 */ - <0x00075000 0x000f5000 0x001000>, /* ap 28 */ - <0x00076000 0x000f6000 0x001000>, /* ap 29 */ - <0x00077000 0x000f7000 0x001000>, /* ap 30 */ - <0x00036000 0x000b6000 0x001000>, /* ap 69 */ - <0x00037000 0x000b7000 0x001000>, /* ap 70 */ - <0x0004d000 0x000cd000 0x001000>, /* ap 78 */ - <0x0004e000 0x000ce000 0x001000>, /* ap 79 */ - <0x00029000 0x000a9000 0x001000>, /* ap 82 */ - <0x0002a000 0x000aa000 0x001000>, /* ap 83 */ - <0x0002b000 0x000ab000 0x001000>, /* ap 84 */ - <0x0002c000 0x000ac000 0x001000>, /* ap 85 */ - <0x0002d000 0x000ad000 0x001000>, /* ap 88 */ - <0x0002e000 0x000ae000 0x001000>; /* ap 89 */ - - target-module@29000 { /* 0x4a0a9000, ap 82 04.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x29000 0x1000>; - }; - - target-module@2b000 { /* 0x4a0ab000, ap 84 12.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "usb_otg_hs"; - reg = <0x2b400 0x4>, - <0x2b404 0x4>, - <0x2b408 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-midle = , - , - ; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */ - clocks = <&l3_init_clkctrl OMAP4_USB_OTG_HS_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2b000 0x1000>; - - usb_otg_hs: usb_otg_hs@0 { - compatible = "ti,omap4-musb"; - reg = <0x0 0x7ff>; - interrupts = , ; - interrupt-names = "mc", "dma"; - usb-phy = <&usb2_phy>; - phys = <&usb2_phy>; - phy-names = "usb2-phy"; - multipoint = <1>; - num-eps = <16>; - ram-bits = <12>; - ctrl-module = <&omap_control_usbotg>; - }; - }; - - target-module@2d000 { /* 0x4a0ad000, ap 88 0c.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "ocp2scp_usb_phy"; - reg = <0x2d000 0x4>, - <0x2d010 0x4>, - <0x2d014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */ - clocks = <&l3_init_clkctrl OMAP4_OCP2SCP_USB_PHY_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2d000 0x1000>; - - ocp2scp@0 { - compatible = "ti,omap-ocp2scp"; - reg = <0x0 0x1f>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x1000>; - usb2_phy: usb2phy@80 { - compatible = "ti,omap-usb2"; - reg = <0x80 0x58>; - ctrl-module = <&omap_control_usb2phy>; - clocks = <&usb_phy_cm_clk32k>; - clock-names = "wkupclk"; - #phy-cells = <0>; - }; - }; - }; - - /* d2d mdm */ - target-module@36000 { /* 0x4a0b6000, ap 69 60.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x36000 0x4>, - <0x36010 0x4>, - <0x36014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, core_pwrdm, d2d_clkdm */ - clocks = <&d2d_clkctrl OMAP4_C2C_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x36000 0x1000>; - }; - - /* d2d mpu */ - target-module@4d000 { /* 0x4a0cd000, ap 78 58.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x4d000 0x4>, - <0x4d010 0x4>, - <0x4d014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, core_pwrdm, d2d_clkdm */ - clocks = <&d2d_clkctrl OMAP4_C2C_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x4d000 0x1000>; - }; - - target-module@59000 { /* 0x4a0d9000, ap 13 1a.0 */ - compatible = "ti,sysc-omap4-sr", "ti,sysc"; - ti,hwmods = "smartreflex_mpu"; - reg = <0x59038 0x4>; - reg-names = "sysc"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): core, always_on_core_pwrdm, l4_ao_clkdm */ - clocks = <&l4_ao_clkctrl OMAP4_SMARTREFLEX_MPU_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x59000 0x1000>; - - smartreflex_mpu: smartreflex@0 { - compatible = "ti,omap4-smartreflex-mpu"; - reg = <0x0 0x80>; - interrupts = ; - }; - }; - - target-module@5b000 { /* 0x4a0db000, ap 15 08.0 */ - compatible = "ti,sysc-omap4-sr", "ti,sysc"; - ti,hwmods = "smartreflex_iva"; - reg = <0x5b038 0x4>; - reg-names = "sysc"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): core, always_on_core_pwrdm, l4_ao_clkdm */ - clocks = <&l4_ao_clkctrl OMAP4_SMARTREFLEX_IVA_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x5b000 0x1000>; - - smartreflex_iva: smartreflex@0 { - compatible = "ti,omap4-smartreflex-iva"; - reg = <0x0 0x80>; - interrupts = ; - }; - }; - - target-module@5d000 { /* 0x4a0dd000, ap 17 22.0 */ - compatible = "ti,sysc-omap4-sr", "ti,sysc"; - ti,hwmods = "smartreflex_core"; - reg = <0x5d038 0x4>; - reg-names = "sysc"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): core, always_on_core_pwrdm, l4_ao_clkdm */ - clocks = <&l4_ao_clkctrl OMAP4_SMARTREFLEX_CORE_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x5d000 0x1000>; - - smartreflex_core: smartreflex@0 { - compatible = "ti,omap4-smartreflex-core"; - reg = <0x0 0x80>; - interrupts = ; - }; - }; - - target-module@60000 { /* 0x4a0e0000, ap 19 1c.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x60000 0x1000>; - }; - - target-module@74000 { /* 0x4a0f4000, ap 27 24.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - ti,hwmods = "mailbox"; - reg = <0x74000 0x4>, - <0x74010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - ; - /* Domains (V, P, C): core, core_pwrdm, l4_cfg_clkdm */ - clocks = <&l4_cfg_clkctrl OMAP4_MAILBOX_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x74000 0x1000>; - - mailbox: mailbox@0 { - compatible = "ti,omap4-mailbox"; - reg = <0x0 0x200>; - interrupts = ; - #mbox-cells = <1>; - ti,mbox-num-users = <3>; - ti,mbox-num-fifos = <8>; - mbox_ipu: mbox_ipu { - ti,mbox-tx = <0 0 0>; - ti,mbox-rx = <1 0 0>; - }; - mbox_dsp: mbox_dsp { - ti,mbox-tx = <3 0 0>; - ti,mbox-rx = <2 0 0>; - }; - }; - }; - - target-module@76000 { /* 0x4a0f6000, ap 29 3a.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "spinlock"; - reg = <0x76000 0x4>, - <0x76010 0x4>, - <0x76014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, core_pwrdm, l4_cfg_clkdm */ - clocks = <&l4_cfg_clkctrl OMAP4_SPINLOCK_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x76000 0x1000>; - - hwspinlock: spinlock@0 { - compatible = "ti,omap4-hwspinlock"; - reg = <0x0 0x1000>; - #hwlock-cells = <1>; - }; - }; - }; - - segment@100000 { /* 0x4a100000 */ - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00100000 0x001000>, /* ap 21 */ - <0x00001000 0x00101000 0x001000>, /* ap 22 */ - <0x00002000 0x00102000 0x001000>, /* ap 61 */ - <0x00003000 0x00103000 0x001000>, /* ap 62 */ - <0x00008000 0x00108000 0x001000>, /* ap 63 */ - <0x00009000 0x00109000 0x001000>, /* ap 64 */ - <0x0000a000 0x0010a000 0x001000>, /* ap 65 */ - <0x0000b000 0x0010b000 0x001000>; /* ap 66 */ - - target-module@0 { /* 0x4a100000, ap 21 2a.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - ti,hwmods = "ctrl_module_pad_core"; - reg = <0x0 0x4>, - <0x10 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): core, core_pwrdm, l4_cfg_clkdm */ - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x1000>; - - omap4_pmx_core: pinmux@40 { - compatible = "ti,omap4-padconf", - "pinctrl-single"; - reg = <0x40 0x0196>; - #address-cells = <1>; - #size-cells = <0>; - #pinctrl-cells = <1>; - #interrupt-cells = <1>; - interrupt-controller; - pinctrl-single,register-width = <16>; - pinctrl-single,function-mask = <0x7fff>; - }; - - omap4_padconf_global: omap4_padconf_global@5a0 { - compatible = "syscon", - "simple-bus"; - reg = <0x5a0 0x170>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x5a0 0x170>; - - pbias_regulator: pbias_regulator@60 { - compatible = "ti,pbias-omap4", "ti,pbias-omap"; - reg = <0x60 0x4>; - syscon = <&omap4_padconf_global>; - pbias_mmc_reg: pbias_mmc_omap4 { - regulator-name = "pbias_mmc_omap4"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3000000>; - }; - }; - }; - }; - - target-module@2000 { /* 0x4a102000, ap 61 3c.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2000 0x1000>; - }; - - target-module@8000 { /* 0x4a108000, ap 63 62.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x8000 0x1000>; - }; - - target-module@a000 { /* 0x4a10a000, ap 65 50.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - ti,hwmods = "fdif"; - reg = <0xa000 0x4>, - <0xa010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = ; - ti,sysc-midle = , - , - ; - ti,sysc-sidle = , - , - ; - ti,sysc-delay-us = <2>; - /* Domains (V, P, C): core, cam_pwrdm, iss_clkdm */ - clocks = <&iss_clkctrl OMAP4_FDIF_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xa000 0x1000>; - - /* No child device binding or driver in mainline */ - }; - }; - - segment@180000 { /* 0x4a180000 */ - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - }; - - segment@200000 { /* 0x4a200000 */ - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0001e000 0x0021e000 0x001000>, /* ap 31 */ - <0x0001f000 0x0021f000 0x001000>, /* ap 32 */ - <0x0000a000 0x0020a000 0x001000>, /* ap 33 */ - <0x0000b000 0x0020b000 0x001000>, /* ap 34 */ - <0x00004000 0x00204000 0x001000>, /* ap 35 */ - <0x00005000 0x00205000 0x001000>, /* ap 36 */ - <0x00006000 0x00206000 0x001000>, /* ap 37 */ - <0x00007000 0x00207000 0x001000>, /* ap 38 */ - <0x00012000 0x00212000 0x001000>, /* ap 39 */ - <0x00013000 0x00213000 0x001000>, /* ap 40 */ - <0x0000c000 0x0020c000 0x001000>, /* ap 41 */ - <0x0000d000 0x0020d000 0x001000>, /* ap 42 */ - <0x00010000 0x00210000 0x001000>, /* ap 43 */ - <0x00011000 0x00211000 0x001000>, /* ap 44 */ - <0x00016000 0x00216000 0x001000>, /* ap 45 */ - <0x00017000 0x00217000 0x001000>, /* ap 46 */ - <0x00014000 0x00214000 0x001000>, /* ap 47 */ - <0x00015000 0x00215000 0x001000>, /* ap 48 */ - <0x00018000 0x00218000 0x001000>, /* ap 49 */ - <0x00019000 0x00219000 0x001000>, /* ap 50 */ - <0x00020000 0x00220000 0x001000>, /* ap 51 */ - <0x00021000 0x00221000 0x001000>, /* ap 52 */ - <0x00026000 0x00226000 0x001000>, /* ap 53 */ - <0x00027000 0x00227000 0x001000>, /* ap 54 */ - <0x00028000 0x00228000 0x001000>, /* ap 55 */ - <0x00029000 0x00229000 0x001000>, /* ap 56 */ - <0x0002a000 0x0022a000 0x001000>, /* ap 57 */ - <0x0002b000 0x0022b000 0x001000>, /* ap 58 */ - <0x0001c000 0x0021c000 0x001000>, /* ap 59 */ - <0x0001d000 0x0021d000 0x001000>; /* ap 60 */ - - target-module@4000 { /* 0x4a204000, ap 35 42.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x4000 0x1000>; - }; - - target-module@6000 { /* 0x4a206000, ap 37 4a.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x6000 0x1000>; - }; - - target-module@a000 { /* 0x4a20a000, ap 33 2c.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xa000 0x1000>; - }; - - target-module@c000 { /* 0x4a20c000, ap 41 20.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xc000 0x1000>; - }; - - target-module@10000 { /* 0x4a210000, ap 43 52.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x10000 0x1000>; - }; - - target-module@12000 { /* 0x4a212000, ap 39 18.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x12000 0x1000>; - }; - - target-module@14000 { /* 0x4a214000, ap 47 30.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x14000 0x1000>; - }; - - target-module@16000 { /* 0x4a216000, ap 45 28.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x16000 0x1000>; - }; - - target-module@18000 { /* 0x4a218000, ap 49 38.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x18000 0x1000>; - }; - - target-module@1c000 { /* 0x4a21c000, ap 59 5a.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x1c000 0x1000>; - }; - - target-module@1e000 { /* 0x4a21e000, ap 31 10.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x1e000 0x1000>; - }; - - target-module@20000 { /* 0x4a220000, ap 51 40.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x20000 0x1000>; - }; - - target-module@26000 { /* 0x4a226000, ap 53 34.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x26000 0x1000>; - }; - - target-module@28000 { /* 0x4a228000, ap 55 2e.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x28000 0x1000>; - }; - - target-module@2a000 { /* 0x4a22a000, ap 57 48.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2a000 0x1000>; - }; - }; - - segment@280000 { /* 0x4a280000 */ - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - }; - - l4_cfg_segment_300000: segment@300000 { /* 0x4a300000 */ - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00300000 0x020000>, /* ap 67 */ - <0x00040000 0x00340000 0x001000>, /* ap 68 */ - <0x00020000 0x00320000 0x004000>, /* ap 71 */ - <0x00024000 0x00324000 0x002000>, /* ap 72 */ - <0x00026000 0x00326000 0x001000>, /* ap 73 */ - <0x00027000 0x00327000 0x001000>, /* ap 74 */ - <0x00028000 0x00328000 0x001000>, /* ap 75 */ - <0x00029000 0x00329000 0x001000>, /* ap 76 */ - <0x00030000 0x00330000 0x010000>, /* ap 77 */ - <0x0002a000 0x0032a000 0x002000>, /* ap 90 */ - <0x0002c000 0x0032c000 0x004000>; /* ap 91 */ - - l4_cfg_target_0: target-module@0 { /* 0x4a300000, ap 67 14.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00000000 0x00020000>, - <0x00020000 0x00020000 0x00004000>, - <0x00024000 0x00024000 0x00002000>, - <0x00026000 0x00026000 0x00001000>, - <0x00027000 0x00027000 0x00001000>, - <0x00028000 0x00028000 0x00001000>, - <0x00029000 0x00029000 0x00001000>, - <0x0002a000 0x0002a000 0x00002000>, - <0x0002c000 0x0002c000 0x00004000>, - <0x00030000 0x00030000 0x00010000>; - }; - }; -}; - -&l4_wkup { /* 0x4a300000 */ - compatible = "ti,omap4-l4-wkup", "simple-bus"; - reg = <0x4a300000 0x800>, - <0x4a300800 0x800>, - <0x4a301000 0x1000>; - reg-names = "ap", "la", "ia0"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x4a300000 0x010000>, /* segment 0 */ - <0x00010000 0x4a310000 0x010000>, /* segment 1 */ - <0x00020000 0x4a320000 0x010000>; /* segment 2 */ - - segment@0 { /* 0x4a300000 */ - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ - <0x00001000 0x00001000 0x001000>, /* ap 1 */ - <0x00000800 0x00000800 0x000800>, /* ap 2 */ - <0x00006000 0x00006000 0x002000>, /* ap 3 */ - <0x00008000 0x00008000 0x001000>, /* ap 4 */ - <0x0000a000 0x0000a000 0x001000>, /* ap 15 */ - <0x0000b000 0x0000b000 0x001000>, /* ap 16 */ - <0x00004000 0x00004000 0x001000>, /* ap 17 */ - <0x00005000 0x00005000 0x001000>, /* ap 18 */ - <0x0000c000 0x0000c000 0x001000>, /* ap 19 */ - <0x0000d000 0x0000d000 0x001000>; /* ap 20 */ - - target-module@4000 { /* 0x4a304000, ap 17 24.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "counter_32k"; - reg = <0x4000 0x4>, - <0x4004 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-sidle = , - ; - /* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */ - clocks = <&l4_wkup_clkctrl OMAP4_COUNTER_32K_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x4000 0x1000>; - - counter32k: counter@0 { - compatible = "ti,omap-counter32k"; - reg = <0x0 0x20>; - }; - }; - - target-module@6000 { /* 0x4a306000, ap 3 08.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x6000 0x4>; - reg-names = "rev"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x6000 0x2000>; - - prm: prm@0 { - compatible = "ti,omap4-prm"; - reg = <0x0 0x2000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x2000>; - - prm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - prm_clockdomains: clockdomains { - }; - }; - }; - - target-module@a000 { /* 0x4a30a000, ap 15 34.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0xa000 0x4>; - reg-names = "rev"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xa000 0x1000>; - - scrm: scrm@0 { - compatible = "ti,omap4-scrm"; - reg = <0x0 0x2000>; - - scrm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - scrm_clockdomains: clockdomains { - }; - }; - }; - - target-module@c000 { /* 0x4a30c000, ap 19 2c.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - ti,hwmods = "ctrl_module_wkup"; - reg = <0xc000 0x4>, - <0xc010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */ - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xc000 0x1000>; - - omap4_scm_wkup: scm@c000 { - compatible = "ti,omap4-scm-wkup"; - reg = <0xc000 0x1000>; - }; - }; - }; - - segment@10000 { /* 0x4a310000 */ - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00010000 0x001000>, /* ap 5 */ - <0x00001000 0x00011000 0x001000>, /* ap 6 */ - <0x00004000 0x00014000 0x001000>, /* ap 7 */ - <0x00005000 0x00015000 0x001000>, /* ap 8 */ - <0x00008000 0x00018000 0x001000>, /* ap 9 */ - <0x00009000 0x00019000 0x001000>, /* ap 10 */ - <0x0000c000 0x0001c000 0x001000>, /* ap 11 */ - <0x0000d000 0x0001d000 0x001000>, /* ap 12 */ - <0x0000e000 0x0001e000 0x001000>, /* ap 21 */ - <0x0000f000 0x0001f000 0x001000>; /* ap 22 */ - - gpio1_target: target-module@0 { /* 0x4a310000, ap 5 14.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "gpio1"; - reg = <0x0 0x4>, - <0x10 0x4>, - <0x114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */ - clocks = <&l4_wkup_clkctrl OMAP4_GPIO1_CLKCTRL 0>, - <&l4_wkup_clkctrl OMAP4_GPIO1_CLKCTRL 8>; - clock-names = "fck", "dbclk"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x1000>; - - gpio1: gpio@0 { - compatible = "ti,omap4-gpio"; - reg = <0x0 0x200>; - interrupts = ; - ti,gpio-always-on; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - target-module@4000 { /* 0x4a314000, ap 7 18.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x4000 0x4>, - <0x4010 0x4>, - <0x4014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_EMUFREE | - SYSC_OMAP2_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */ - clocks = <&l4_wkup_clkctrl OMAP4_WD_TIMER2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x4000 0x1000>; - - wdt2: wdt@0 { - compatible = "ti,omap4-wdt", "ti,omap3-wdt"; - reg = <0x0 0x80>; - interrupts = ; - }; - }; - - target-module@8000 { /* 0x4a318000, ap 9 1c.0 */ - compatible = "ti,sysc-omap2-timer", "ti,sysc"; - ti,hwmods = "timer1"; - reg = <0x8000 0x4>, - <0x8010 0x4>, - <0x8014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_EMUFREE | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */ - clocks = <&l4_wkup_clkctrl OMAP4_TIMER1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x8000 0x1000>; - - timer1: timer@0 { - compatible = "ti,omap3430-timer"; - reg = <0x0 0x80>; - clocks = <&l4_wkup_clkctrl OMAP4_TIMER1_CLKCTRL 24>; - clock-names = "fck"; - interrupts = ; - ti,timer-alwon; - }; - }; - - target-module@c000 { /* 0x4a31c000, ap 11 20.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "kbd"; - reg = <0xc000 0x4>, - <0xc010 0x4>, - <0xc014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_EMUFREE | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */ - clocks = <&l4_wkup_clkctrl OMAP4_KBD_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xc000 0x1000>; - - keypad: keypad@0 { - compatible = "ti,omap4-keypad"; - reg = <0x0 0x80>; - interrupts = ; - reg-names = "mpu"; - }; - }; - - target-module@e000 { /* 0x4a31e000, ap 21 30.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - ti,hwmods = "ctrl_module_pad_wkup"; - reg = <0xe000 0x4>, - <0xe010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */ - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xe000 0x1000>; - - omap4_pmx_wkup: pinmux@40 { - compatible = "ti,omap4-padconf", - "pinctrl-single"; - reg = <0x40 0x0038>; - #address-cells = <1>; - #size-cells = <0>; - #pinctrl-cells = <1>; - #interrupt-cells = <1>; - interrupt-controller; - pinctrl-single,register-width = <16>; - pinctrl-single,function-mask = <0x7fff>; - }; - }; - }; - - segment@20000 { /* 0x4a320000 */ - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00006000 0x00026000 0x001000>, /* ap 13 */ - <0x0000a000 0x0002a000 0x001000>, /* ap 14 */ - <0x00000000 0x00020000 0x001000>, /* ap 23 */ - <0x00001000 0x00021000 0x001000>, /* ap 24 */ - <0x00002000 0x00022000 0x001000>, /* ap 25 */ - <0x00003000 0x00023000 0x001000>, /* ap 26 */ - <0x00004000 0x00024000 0x001000>, /* ap 27 */ - <0x00005000 0x00025000 0x001000>, /* ap 28 */ - <0x00007000 0x00027000 0x000400>, /* ap 29 */ - <0x00008000 0x00028000 0x000800>, /* ap 30 */ - <0x00009000 0x00029000 0x000400>; /* ap 31 */ - - target-module@0 { /* 0x4a320000, ap 23 04.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x1000>; - }; - - target-module@2000 { /* 0x4a322000, ap 25 0c.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2000 0x1000>; - }; - - target-module@4000 { /* 0x4a324000, ap 27 10.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x4000 0x1000>; - }; - - target-module@6000 { /* 0x4a326000, ap 13 28.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00006000 0x00001000>, - <0x00001000 0x00007000 0x00000400>, - <0x00002000 0x00008000 0x00000800>, - <0x00003000 0x00009000 0x00000400>; - }; - }; -}; - -&l4_per { /* 0x48000000 */ - compatible = "ti,omap4-l4-per", "simple-bus"; - reg = <0x48000000 0x800>, - <0x48000800 0x800>, - <0x48001000 0x400>, - <0x48001400 0x400>, - <0x48001800 0x400>, - <0x48001c00 0x400>; - reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x48000000 0x200000>, /* segment 0 */ - <0x00200000 0x48200000 0x200000>; /* segment 1 */ - - segment@0 { /* 0x48000000 */ - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ - <0x00001000 0x00001000 0x000400>, /* ap 1 */ - <0x00000800 0x00000800 0x000800>, /* ap 2 */ - <0x00020000 0x00020000 0x001000>, /* ap 3 */ - <0x00021000 0x00021000 0x001000>, /* ap 4 */ - <0x00032000 0x00032000 0x001000>, /* ap 5 */ - <0x00033000 0x00033000 0x001000>, /* ap 6 */ - <0x00034000 0x00034000 0x001000>, /* ap 7 */ - <0x00035000 0x00035000 0x001000>, /* ap 8 */ - <0x00036000 0x00036000 0x001000>, /* ap 9 */ - <0x00037000 0x00037000 0x001000>, /* ap 10 */ - <0x0003e000 0x0003e000 0x001000>, /* ap 11 */ - <0x0003f000 0x0003f000 0x001000>, /* ap 12 */ - <0x00040000 0x00040000 0x010000>, /* ap 13 */ - <0x00050000 0x00050000 0x001000>, /* ap 14 */ - <0x00055000 0x00055000 0x001000>, /* ap 15 */ - <0x00056000 0x00056000 0x001000>, /* ap 16 */ - <0x00057000 0x00057000 0x001000>, /* ap 17 */ - <0x00058000 0x00058000 0x001000>, /* ap 18 */ - <0x00059000 0x00059000 0x001000>, /* ap 19 */ - <0x0005a000 0x0005a000 0x001000>, /* ap 20 */ - <0x0005b000 0x0005b000 0x001000>, /* ap 21 */ - <0x0005c000 0x0005c000 0x001000>, /* ap 22 */ - <0x0005d000 0x0005d000 0x001000>, /* ap 23 */ - <0x0005e000 0x0005e000 0x001000>, /* ap 24 */ - <0x00060000 0x00060000 0x001000>, /* ap 25 */ - <0x0006a000 0x0006a000 0x001000>, /* ap 26 */ - <0x0006b000 0x0006b000 0x001000>, /* ap 27 */ - <0x0006c000 0x0006c000 0x001000>, /* ap 28 */ - <0x0006d000 0x0006d000 0x001000>, /* ap 29 */ - <0x0006e000 0x0006e000 0x001000>, /* ap 30 */ - <0x0006f000 0x0006f000 0x001000>, /* ap 31 */ - <0x00070000 0x00070000 0x001000>, /* ap 32 */ - <0x00071000 0x00071000 0x001000>, /* ap 33 */ - <0x00072000 0x00072000 0x001000>, /* ap 34 */ - <0x00073000 0x00073000 0x001000>, /* ap 35 */ - <0x00061000 0x00061000 0x001000>, /* ap 36 */ - <0x00096000 0x00096000 0x001000>, /* ap 37 */ - <0x00097000 0x00097000 0x001000>, /* ap 38 */ - <0x00076000 0x00076000 0x001000>, /* ap 39 */ - <0x00077000 0x00077000 0x001000>, /* ap 40 */ - <0x00078000 0x00078000 0x001000>, /* ap 41 */ - <0x00079000 0x00079000 0x001000>, /* ap 42 */ - <0x00086000 0x00086000 0x001000>, /* ap 43 */ - <0x00087000 0x00087000 0x001000>, /* ap 44 */ - <0x00088000 0x00088000 0x001000>, /* ap 45 */ - <0x00089000 0x00089000 0x001000>, /* ap 46 */ - <0x000b0000 0x000b0000 0x001000>, /* ap 47 */ - <0x000b1000 0x000b1000 0x001000>, /* ap 48 */ - <0x00098000 0x00098000 0x001000>, /* ap 49 */ - <0x00099000 0x00099000 0x001000>, /* ap 50 */ - <0x0009a000 0x0009a000 0x001000>, /* ap 51 */ - <0x0009b000 0x0009b000 0x001000>, /* ap 52 */ - <0x0009c000 0x0009c000 0x001000>, /* ap 53 */ - <0x0009d000 0x0009d000 0x001000>, /* ap 54 */ - <0x0009e000 0x0009e000 0x001000>, /* ap 55 */ - <0x0009f000 0x0009f000 0x001000>, /* ap 56 */ - <0x00090000 0x00090000 0x002000>, /* ap 57 */ - <0x00092000 0x00092000 0x001000>, /* ap 58 */ - <0x000a4000 0x000a4000 0x001000>, /* ap 59 */ - <0x000a6000 0x000a6000 0x001000>, /* ap 60 */ - <0x000a8000 0x000a8000 0x004000>, /* ap 61 */ - <0x000ac000 0x000ac000 0x001000>, /* ap 62 */ - <0x000ad000 0x000ad000 0x001000>, /* ap 63 */ - <0x000ae000 0x000ae000 0x001000>, /* ap 64 */ - <0x000b2000 0x000b2000 0x001000>, /* ap 65 */ - <0x000b3000 0x000b3000 0x001000>, /* ap 66 */ - <0x000b4000 0x000b4000 0x001000>, /* ap 67 */ - <0x000b5000 0x000b5000 0x001000>, /* ap 68 */ - <0x000b8000 0x000b8000 0x001000>, /* ap 69 */ - <0x000b9000 0x000b9000 0x001000>, /* ap 70 */ - <0x000ba000 0x000ba000 0x001000>, /* ap 71 */ - <0x000bb000 0x000bb000 0x001000>, /* ap 72 */ - <0x000d1000 0x000d1000 0x001000>, /* ap 73 */ - <0x000d2000 0x000d2000 0x001000>, /* ap 74 */ - <0x000d5000 0x000d5000 0x001000>, /* ap 75 */ - <0x000d6000 0x000d6000 0x001000>, /* ap 76 */ - <0x000a2000 0x000a2000 0x001000>, /* ap 79 */ - <0x000a3000 0x000a3000 0x001000>, /* ap 80 */ - <0x00001400 0x00001400 0x000400>, /* ap 81 */ - <0x00001800 0x00001800 0x000400>, /* ap 82 */ - <0x00001c00 0x00001c00 0x000400>, /* ap 83 */ - <0x000a5000 0x000a5000 0x001000>; /* ap 84 */ - - target-module@20000 { /* 0x48020000, ap 3 06.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x20050 0x4>, - <0x20054 0x4>, - <0x20058 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ - clocks = <&l4_per_clkctrl OMAP4_UART3_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x20000 0x1000>; - - uart3: serial@0 { - compatible = "ti,omap4-uart"; - reg = <0x0 0x100>; - interrupts = ; - clock-frequency = <48000000>; - }; - }; - - target-module@32000 { /* 0x48032000, ap 5 02.0 */ - compatible = "ti,sysc-omap2-timer", "ti,sysc"; - ti,hwmods = "timer2"; - reg = <0x32000 0x4>, - <0x32010 0x4>, - <0x32014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_EMUFREE | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ - clocks = <&l4_per_clkctrl OMAP4_TIMER2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x32000 0x1000>; - - timer2: timer@0 { - compatible = "ti,omap3430-timer"; - reg = <0x0 0x80>; - clocks = <&l4_per_clkctrl OMAP4_TIMER2_CLKCTRL 24>; - clock-names = "fck"; - interrupts = ; - }; - }; - - target-module@34000 { /* 0x48034000, ap 7 04.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - ti,hwmods = "timer3"; - reg = <0x34000 0x4>, - <0x34010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ - clocks = <&l4_per_clkctrl OMAP4_TIMER3_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x34000 0x1000>; - - timer3: timer@0 { - compatible = "ti,omap4430-timer"; - reg = <0x0 0x80>; - clocks = <&l4_per_clkctrl OMAP4_TIMER3_CLKCTRL 24>; - clock-names = "fck"; - interrupts = ; - }; - }; - - target-module@36000 { /* 0x48036000, ap 9 0e.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - ti,hwmods = "timer4"; - reg = <0x36000 0x4>, - <0x36010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ - clocks = <&l4_per_clkctrl OMAP4_TIMER4_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x36000 0x1000>; - - timer4: timer@0 { - compatible = "ti,omap4430-timer"; - reg = <0x0 0x80>; - clocks = <&l4_per_clkctrl OMAP4_TIMER4_CLKCTRL 24>; - clock-names = "fck"; - interrupts = ; - }; - }; - - target-module@3e000 { /* 0x4803e000, ap 11 08.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - ti,hwmods = "timer9"; - reg = <0x3e000 0x4>, - <0x3e010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ - clocks = <&l4_per_clkctrl OMAP4_TIMER9_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x3e000 0x1000>; - - timer9: timer@0 { - compatible = "ti,omap4430-timer"; - reg = <0x0 0x80>; - clocks = <&l4_per_clkctrl OMAP4_TIMER9_CLKCTRL 24>; - clock-names = "fck"; - interrupts = ; - ti,timer-pwm; - }; - }; - - target-module@40000 { /* 0x48040000, ap 13 0a.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x40000 0x10000>; - }; - - target-module@55000 { /* 0x48055000, ap 15 0c.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "gpio2"; - reg = <0x55000 0x4>, - <0x55010 0x4>, - <0x55114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ - clocks = <&l4_per_clkctrl OMAP4_GPIO2_CLKCTRL 0>, - <&l4_per_clkctrl OMAP4_GPIO2_CLKCTRL 8>; - clock-names = "fck", "dbclk"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x55000 0x1000>; - - gpio2: gpio@0 { - compatible = "ti,omap4-gpio"; - reg = <0x0 0x200>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - target-module@57000 { /* 0x48057000, ap 17 16.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "gpio3"; - reg = <0x57000 0x4>, - <0x57010 0x4>, - <0x57114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ - clocks = <&l4_per_clkctrl OMAP4_GPIO3_CLKCTRL 0>, - <&l4_per_clkctrl OMAP4_GPIO3_CLKCTRL 8>; - clock-names = "fck", "dbclk"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x57000 0x1000>; - - gpio3: gpio@0 { - compatible = "ti,omap4-gpio"; - reg = <0x0 0x200>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - target-module@59000 { /* 0x48059000, ap 19 10.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "gpio4"; - reg = <0x59000 0x4>, - <0x59010 0x4>, - <0x59114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ - clocks = <&l4_per_clkctrl OMAP4_GPIO4_CLKCTRL 0>, - <&l4_per_clkctrl OMAP4_GPIO4_CLKCTRL 8>; - clock-names = "fck", "dbclk"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x59000 0x1000>; - - gpio4: gpio@0 { - compatible = "ti,omap4-gpio"; - reg = <0x0 0x200>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - target-module@5b000 { /* 0x4805b000, ap 21 12.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "gpio5"; - reg = <0x5b000 0x4>, - <0x5b010 0x4>, - <0x5b114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ - clocks = <&l4_per_clkctrl OMAP4_GPIO5_CLKCTRL 0>, - <&l4_per_clkctrl OMAP4_GPIO5_CLKCTRL 8>; - clock-names = "fck", "dbclk"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x5b000 0x1000>; - - gpio5: gpio@0 { - compatible = "ti,omap4-gpio"; - reg = <0x0 0x200>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - target-module@5d000 { /* 0x4805d000, ap 23 14.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "gpio6"; - reg = <0x5d000 0x4>, - <0x5d010 0x4>, - <0x5d114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ - clocks = <&l4_per_clkctrl OMAP4_GPIO6_CLKCTRL 0>, - <&l4_per_clkctrl OMAP4_GPIO6_CLKCTRL 8>; - clock-names = "fck", "dbclk"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x5d000 0x1000>; - - gpio6: gpio@0 { - compatible = "ti,omap4-gpio"; - reg = <0x0 0x200>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - target-module@60000 { /* 0x48060000, ap 25 1e.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x60000 0x8>, - <0x60010 0x8>, - <0x60090 0x8>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ - clocks = <&l4_per_clkctrl OMAP4_I2C3_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x60000 0x1000>; - - i2c3: i2c@0 { - compatible = "ti,omap4-i2c"; - reg = <0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - target-module@6a000 { /* 0x4806a000, ap 26 18.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x6a050 0x4>, - <0x6a054 0x4>, - <0x6a058 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ - clocks = <&l4_per_clkctrl OMAP4_UART1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x6a000 0x1000>; - - uart1: serial@0 { - compatible = "ti,omap4-uart"; - reg = <0x0 0x100>; - interrupts = ; - clock-frequency = <48000000>; - }; - }; - - target-module@6c000 { /* 0x4806c000, ap 28 20.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x6c050 0x4>, - <0x6c054 0x4>, - <0x6c058 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ - clocks = <&l4_per_clkctrl OMAP4_UART2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x6c000 0x1000>; - - uart2: serial@0 { - compatible = "ti,omap4-uart"; - reg = <0x0 0x100>; - interrupts = ; - clock-frequency = <48000000>; - }; - }; - - target-module@6e000 { /* 0x4806e000, ap 30 1c.1 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x6e050 0x4>, - <0x6e054 0x4>, - <0x6e058 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ - clocks = <&l4_per_clkctrl OMAP4_UART4_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x6e000 0x1000>; - - uart4: serial@0 { - compatible = "ti,omap4-uart"; - reg = <0x0 0x100>; - interrupts = ; - clock-frequency = <48000000>; - }; - }; - - target-module@70000 { /* 0x48070000, ap 32 28.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x70000 0x8>, - <0x70010 0x8>, - <0x70090 0x8>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ - clocks = <&l4_per_clkctrl OMAP4_I2C1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x70000 0x1000>; - - i2c1: i2c@0 { - compatible = "ti,omap4-i2c"; - reg = <0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - target-module@72000 { /* 0x48072000, ap 34 30.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x72000 0x8>, - <0x72010 0x8>, - <0x72090 0x8>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ - clocks = <&l4_per_clkctrl OMAP4_I2C2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x72000 0x1000>; - - i2c2: i2c@0 { - compatible = "ti,omap4-i2c"; - reg = <0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - target-module@76000 { /* 0x48076000, ap 39 38.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - ti,hwmods = "slimbus2"; - reg = <0x76000 0x4>, - <0x76010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ - clocks = <&l4_per_clkctrl OMAP4_SLIMBUS2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x76000 0x1000>; - - /* No child device binding or driver in mainline */ - }; - - target-module@78000 { /* 0x48078000, ap 41 1a.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "elm"; - reg = <0x78000 0x4>, - <0x78010 0x4>, - <0x78014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ - clocks = <&l4_per_clkctrl OMAP4_ELM_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x78000 0x1000>; - - elm: elm@0 { - compatible = "ti,am3352-elm"; - reg = <0x0 0x2000>; - interrupts = ; - status = "disabled"; - }; - }; - - target-module@86000 { /* 0x48086000, ap 43 24.0 */ - compatible = "ti,sysc-omap2-timer", "ti,sysc"; - ti,hwmods = "timer10"; - reg = <0x86000 0x4>, - <0x86010 0x4>, - <0x86014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_EMUFREE | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ - clocks = <&l4_per_clkctrl OMAP4_TIMER10_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x86000 0x1000>; - - timer10: timer@0 { - compatible = "ti,omap3430-timer"; - reg = <0x0 0x80>; - clocks = <&l4_per_clkctrl OMAP4_TIMER10_CLKCTRL 24>; - clock-names = "fck"; - interrupts = ; - ti,timer-pwm; - }; - }; - - target-module@88000 { /* 0x48088000, ap 45 2e.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - ti,hwmods = "timer11"; - reg = <0x88000 0x4>, - <0x88010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ - clocks = <&l4_per_clkctrl OMAP4_TIMER11_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x88000 0x1000>; - - timer11: timer@0 { - compatible = "ti,omap4430-timer"; - reg = <0x0 0x80>; - clocks = <&l4_per_clkctrl OMAP4_TIMER11_CLKCTRL 24>; - clock-names = "fck"; - interrupts = ; - ti,timer-pwm; - }; - }; - - target-module@90000 { /* 0x48090000, ap 57 2a.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x90000 0x2000>; - }; - - target-module@96000 { /* 0x48096000, ap 37 26.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "mcbsp4"; - reg = <0x9608c 0x4>; - reg-names = "sysc"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET)>; - ti,sysc-sidle = , - , - ; - /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ - clocks = <&l4_per_clkctrl OMAP4_MCBSP4_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x96000 0x1000>; - - mcbsp4: mcbsp@0 { - compatible = "ti,omap4-mcbsp"; - reg = <0x0 0xff>; /* L4 Interconnect */ - reg-names = "mpu"; - interrupts = ; - interrupt-names = "common"; - ti,buffer-size = <128>; - dmas = <&sdma 31>, - <&sdma 32>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - }; - - target-module@98000 { /* 0x48098000, ap 49 22.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - ti,hwmods = "mcspi1"; - reg = <0x98000 0x4>, - <0x98010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ - clocks = <&l4_per_clkctrl OMAP4_MCSPI1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x98000 0x1000>; - - mcspi1: spi@0 { - compatible = "ti,omap4-mcspi"; - reg = <0x0 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - ti,spi-num-cs = <4>; - dmas = <&sdma 35>, - <&sdma 36>, - <&sdma 37>, - <&sdma 38>, - <&sdma 39>, - <&sdma 40>, - <&sdma 41>, - <&sdma 42>; - dma-names = "tx0", "rx0", "tx1", "rx1", - "tx2", "rx2", "tx3", "rx3"; - }; - }; - - target-module@9a000 { /* 0x4809a000, ap 51 2c.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - ti,hwmods = "mcspi2"; - reg = <0x9a000 0x4>, - <0x9a010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ - clocks = <&l4_per_clkctrl OMAP4_MCSPI2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x9a000 0x1000>; - - mcspi2: spi@0 { - compatible = "ti,omap4-mcspi"; - reg = <0x0 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - ti,spi-num-cs = <2>; - dmas = <&sdma 43>, - <&sdma 44>, - <&sdma 45>, - <&sdma 46>; - dma-names = "tx0", "rx0", "tx1", "rx1"; - }; - }; - - target-module@9c000 { /* 0x4809c000, ap 53 36.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x9c000 0x4>, - <0x9c010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-midle = , - , - , - ; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */ - clocks = <&l3_init_clkctrl OMAP4_MMC1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x9c000 0x1000>; - - mmc1: mmc@0 { - compatible = "ti,omap4-hsmmc"; - reg = <0x0 0x400>; - interrupts = ; - ti,dual-volt; - ti,needs-special-reset; - dmas = <&sdma 61>, <&sdma 62>; - dma-names = "tx", "rx"; - pbias-supply = <&pbias_mmc_reg>; - }; - }; - - target-module@9e000 { /* 0x4809e000, ap 55 48.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x9e000 0x1000>; - }; - - target-module@a2000 { /* 0x480a2000, ap 79 3a.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xa2000 0x1000>; - }; - - target-module@a4000 { /* 0x480a4000, ap 59 34.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x000a4000 0x00001000>, - <0x00001000 0x000a5000 0x00001000>; - }; - - target-module@a8000 { /* 0x480a8000, ap 61 3e.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xa8000 0x4000>; - }; - - target-module@ad000 { /* 0x480ad000, ap 63 50.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0xad000 0x4>, - <0xad010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-midle = , - , - , - ; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ - clocks = <&l4_per_clkctrl OMAP4_MMC3_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xad000 0x1000>; - - mmc3: mmc@0 { - compatible = "ti,omap4-hsmmc"; - reg = <0x0 0x400>; - interrupts = ; - ti,needs-special-reset; - dmas = <&sdma 77>, <&sdma 78>; - dma-names = "tx", "rx"; - }; - }; - - target-module@b0000 { /* 0x480b0000, ap 47 40.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xb0000 0x1000>; - }; - - target-module@b2000 { /* 0x480b2000, ap 65 3c.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "hdq1w"; - reg = <0xb2000 0x4>, - <0xb2014 0x4>, - <0xb2018 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,syss-mask = <1>; - ti,no-reset-on-init; - /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ - clocks = <&l4_per_clkctrl OMAP4_HDQ1W_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xb2000 0x1000>; - - hdqw1w: 1w@0 { - compatible = "ti,omap3-1w"; - reg = <0x0 0x1000>; - interrupts = ; - }; - }; - - target-module@b4000 { /* 0x480b4000, ap 67 46.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0xb4000 0x4>, - <0xb4010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-midle = , - , - , - ; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */ - clocks = <&l3_init_clkctrl OMAP4_MMC2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xb4000 0x1000>; - - mmc2: mmc@0 { - compatible = "ti,omap4-hsmmc"; - reg = <0x0 0x400>; - interrupts = ; - ti,needs-special-reset; - dmas = <&sdma 47>, <&sdma 48>; - dma-names = "tx", "rx"; - }; - }; - - target-module@b8000 { /* 0x480b8000, ap 69 58.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - ti,hwmods = "mcspi3"; - reg = <0xb8000 0x4>, - <0xb8010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ - clocks = <&l4_per_clkctrl OMAP4_MCSPI3_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xb8000 0x1000>; - - mcspi3: spi@0 { - compatible = "ti,omap4-mcspi"; - reg = <0x0 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - ti,spi-num-cs = <2>; - dmas = <&sdma 15>, <&sdma 16>; - dma-names = "tx0", "rx0"; - }; - }; - - target-module@ba000 { /* 0x480ba000, ap 71 32.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - ti,hwmods = "mcspi4"; - reg = <0xba000 0x4>, - <0xba010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ - clocks = <&l4_per_clkctrl OMAP4_MCSPI4_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xba000 0x1000>; - - mcspi4: spi@0 { - compatible = "ti,omap4-mcspi"; - reg = <0x0 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - ti,spi-num-cs = <1>; - dmas = <&sdma 70>, <&sdma 71>; - dma-names = "tx0", "rx0"; - }; - }; - - target-module@d1000 { /* 0x480d1000, ap 73 44.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0xd1000 0x4>, - <0xd1010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-midle = , - , - , - ; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ - clocks = <&l4_per_clkctrl OMAP4_MMC4_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xd1000 0x1000>; - - mmc4: mmc@0 { - compatible = "ti,omap4-hsmmc"; - reg = <0x0 0x400>; - interrupts = ; - ti,needs-special-reset; - dmas = <&sdma 57>, <&sdma 58>; - dma-names = "tx", "rx"; - }; - }; - - target-module@d5000 { /* 0x480d5000, ap 75 4e.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0xd5000 0x4>, - <0xd5010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-midle = , - , - , - ; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ - clocks = <&l4_per_clkctrl OMAP4_MMC5_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xd5000 0x1000>; - - mmc5: mmc@0 { - compatible = "ti,omap4-hsmmc"; - reg = <0x0 0x400>; - interrupts = ; - ti,needs-special-reset; - dmas = <&sdma 59>, <&sdma 60>; - dma-names = "tx", "rx"; - }; - }; - }; - - segment@200000 { /* 0x48200000 */ - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00150000 0x00350000 0x001000>, /* ap 77 */ - <0x00151000 0x00351000 0x001000>; /* ap 78 */ - - target-module@150000 { /* 0x48350000, ap 77 4c.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x150000 0x8>, - <0x150010 0x8>, - <0x150090 0x8>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ - clocks = <&l4_per_clkctrl OMAP4_I2C4_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x150000 0x1000>; - - i2c4: i2c@0 { - compatible = "ti,omap4-i2c"; - reg = <0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - }; -}; - diff --git a/sys/gnu/dts/arm/omap4-mcpdm.dtsi b/sys/gnu/dts/arm/omap4-mcpdm.dtsi deleted file mode 100644 index 915a9b31a33..00000000000 --- a/sys/gnu/dts/arm/omap4-mcpdm.dtsi +++ /dev/null @@ -1,44 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Common omap4 mcpdm configuration - * - * Only include this file if your board has pdmclk wired from the - * pmic to ABE as mcpdm uses an external clock for the module. - */ - -&omap4_pmx_core { - mcpdm_pins: pinmux_mcpdm_pins { - pinctrl-single,pins = < - /* 0x4a100106 abe_pdm_ul_data.abe_pdm_ul_data ag25 */ - OMAP4_IOPAD(0x106, PIN_INPUT_PULLDOWN | MUX_MODE0) - - /* 0x4a100108 abe_pdm_dl_data.abe_pdm_dl_data af25 */ - OMAP4_IOPAD(0x108, PIN_INPUT_PULLDOWN | MUX_MODE0) - - /* 0x4a10010a abe_pdm_frame.abe_pdm_frame ae25 */ - OMAP4_IOPAD(0x10a, PIN_INPUT_PULLUP | MUX_MODE0) - - /* 0x4a10010c abe_pdm_lb_clk.abe_pdm_lb_clk af26 */ - OMAP4_IOPAD(0x10c, PIN_INPUT_PULLDOWN | MUX_MODE0) - - /* 0x4a10010e abe_clks.abe_clks ah26 */ - OMAP4_IOPAD(0x10e, PIN_INPUT_PULLDOWN | MUX_MODE0) - >; - }; -}; - -&mcpdm_module { - /* - * McPDM pads must be muxed at the interconnect target module - * level as the module on the SoC needs external clock from - * the PMIC - */ - pinctrl-names = "default"; - pinctrl-0 = <&mcpdm_pins>; - status = "okay"; -}; - -&mcpdm { - clocks = <&twl6040>; - clock-names = "pdmclk"; -}; diff --git a/sys/gnu/dts/arm/omap4-panda-a4.dts b/sys/gnu/dts/arm/omap4-panda-a4.dts deleted file mode 100644 index 64083075dd5..00000000000 --- a/sys/gnu/dts/arm/omap4-panda-a4.dts +++ /dev/null @@ -1,17 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ - */ -/dts-v1/; - -#include "omap443x.dtsi" -#include "omap4-panda-common.dtsi" - -/* Pandaboard Rev A4+ have external pullups on SCL & SDA */ -&dss_hdmi_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x09a, PIN_INPUT | MUX_MODE0) /* hdmi_cec.hdmi_cec */ - OMAP4_IOPAD(0x09c, PIN_INPUT | MUX_MODE0) /* hdmi_scl.hdmi_scl */ - OMAP4_IOPAD(0x09e, PIN_INPUT | MUX_MODE0) /* hdmi_sda.hdmi_sda */ - >; -}; diff --git a/sys/gnu/dts/arm/omap4-panda-common.dtsi b/sys/gnu/dts/arm/omap4-panda-common.dtsi deleted file mode 100644 index 55ea8b6189a..00000000000 --- a/sys/gnu/dts/arm/omap4-panda-common.dtsi +++ /dev/null @@ -1,573 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2011-2013 Texas Instruments Incorporated - http://www.ti.com/ - */ -#include -#include "elpida_ecb240abacn.dtsi" -#include "omap4-mcpdm.dtsi" - -/ { - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x40000000>; /* 1 GB */ - }; - - chosen { - stdout-path = &uart3; - }; - - aliases { - display0 = &dvi0; - display1 = &hdmi0; - ethernet = ðernet; - }; - - leds: leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = < - &led_wkgpio_pins - >; - - heartbeat { - label = "pandaboard::status1"; - gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - - mmc { - label = "pandaboard::status2"; - gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc0"; - }; - }; - - gpio_keys: gpio_keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = < - &button_pins - >; - - buttonS2 { - label = "button S2"; - gpios = <&gpio4 25 GPIO_ACTIVE_LOW>; /* gpio_121 */ - linux,code = ; - wakeup-source; - }; - }; - - sound: sound { - compatible = "ti,abe-twl6040"; - ti,model = "PandaBoard"; - - ti,mclk-freq = <38400000>; - - ti,mcpdm = <&mcpdm>; - - ti,twl6040 = <&twl6040>; - - /* Audio routing */ - ti,audio-routing = - "Headset Stereophone", "HSOL", - "Headset Stereophone", "HSOR", - "Ext Spk", "HFL", - "Ext Spk", "HFR", - "Line Out", "AUXL", - "Line Out", "AUXR", - "HSMIC", "Headset Mic", - "Headset Mic", "Headset Mic Bias", - "AFML", "Line In", - "AFMR", "Line In"; - }; - - /* HS USB Port 1 Power */ - hsusb1_power: hsusb1_power_reg { - compatible = "regulator-fixed"; - regulator-name = "hsusb1_vbus"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>; /* gpio_1 */ - startup-delay-us = <70000>; - enable-active-high; - /* - * boot-on is required along with always-on as the - * regulator framework doesn't enable the regulator - * if boot-on is not there. - */ - regulator-always-on; - regulator-boot-on; - }; - - /* HS USB Host PHY on PORT 1 */ - hsusb1_phy: hsusb1_phy { - compatible = "usb-nop-xceiv"; - reset-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>; /* gpio_62 */ - #phy-cells = <0>; - vcc-supply = <&hsusb1_power>; - clocks = <&auxclk3_ck>; - clock-names = "main_clk"; - clock-frequency = <19200000>; - }; - - /* regulator for wl12xx on sdio5 */ - wl12xx_vmmc: wl12xx_vmmc { - pinctrl-names = "default"; - pinctrl-0 = <&wl12xx_gpio>; - compatible = "regulator-fixed"; - regulator-name = "vwl1271"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>; - startup-delay-us = <70000>; - enable-active-high; - }; - - tfp410: encoder0 { - compatible = "ti,tfp410"; - powerdown-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; /* gpio_0 */ - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - tfp410_in: endpoint { - remote-endpoint = <&dpi_out>; - }; - }; - - port@1 { - reg = <1>; - - tfp410_out: endpoint { - remote-endpoint = <&dvi_connector_in>; - }; - }; - }; - }; - - dvi0: connector0 { - compatible = "dvi-connector"; - label = "dvi"; - - digital; - - ddc-i2c-bus = <&i2c3>; - - port { - dvi_connector_in: endpoint { - remote-endpoint = <&tfp410_out>; - }; - }; - }; - - tpd12s015: encoder1 { - compatible = "ti,tpd12s015"; - - gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>, /* 60, CT CP HPD */ - <&gpio2 9 GPIO_ACTIVE_HIGH>, /* 41, LS OE */ - <&gpio2 31 GPIO_ACTIVE_HIGH>; /* 63, HPD */ - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - tpd12s015_in: endpoint { - remote-endpoint = <&hdmi_out>; - }; - }; - - port@1 { - reg = <1>; - - tpd12s015_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; - }; - }; - }; - - hdmi0: connector1 { - compatible = "hdmi-connector"; - label = "hdmi"; - - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&tpd12s015_out>; - }; - }; - }; -}; - -&omap4_pmx_core { - pinctrl-names = "default"; - pinctrl-0 = < - &dss_dpi_pins - &tfp410_pins - &dss_hdmi_pins - &tpd12s015_pins - &hsusbb1_pins - >; - - twl6040_pins: pinmux_twl6040_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x120, PIN_OUTPUT | MUX_MODE3) /* hdq_sio.gpio_127 */ - OMAP4_IOPAD(0x1a0, PIN_INPUT | MUX_MODE0) /* sys_nirq2.sys_nirq2 */ - >; - }; - - mcbsp1_pins: pinmux_mcbsp1_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x0fe, PIN_INPUT | MUX_MODE0) /* abe_mcbsp1_clkx.abe_mcbsp1_clkx */ - OMAP4_IOPAD(0x100, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp1_dr.abe_mcbsp1_dr */ - OMAP4_IOPAD(0x102, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp1_dx.abe_mcbsp1_dx */ - OMAP4_IOPAD(0x104, PIN_INPUT | MUX_MODE0) /* abe_mcbsp1_fsx.abe_mcbsp1_fsx */ - >; - }; - - dss_dpi_pins: pinmux_dss_dpi_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x162, PIN_OUTPUT | MUX_MODE5) /* dispc2_data23 */ - OMAP4_IOPAD(0x164, PIN_OUTPUT | MUX_MODE5) /* dispc2_data22 */ - OMAP4_IOPAD(0x166, PIN_OUTPUT | MUX_MODE5) /* dispc2_data21 */ - OMAP4_IOPAD(0x168, PIN_OUTPUT | MUX_MODE5) /* dispc2_data20 */ - OMAP4_IOPAD(0x16a, PIN_OUTPUT | MUX_MODE5) /* dispc2_data19 */ - OMAP4_IOPAD(0x16c, PIN_OUTPUT | MUX_MODE5) /* dispc2_data18 */ - OMAP4_IOPAD(0x16e, PIN_OUTPUT | MUX_MODE5) /* dispc2_data15 */ - OMAP4_IOPAD(0x170, PIN_OUTPUT | MUX_MODE5) /* dispc2_data14 */ - OMAP4_IOPAD(0x172, PIN_OUTPUT | MUX_MODE5) /* dispc2_data13 */ - OMAP4_IOPAD(0x174, PIN_OUTPUT | MUX_MODE5) /* dispc2_data12 */ - OMAP4_IOPAD(0x176, PIN_OUTPUT | MUX_MODE5) /* dispc2_data11 */ - - OMAP4_IOPAD(0x1b4, PIN_OUTPUT | MUX_MODE5) /* dispc2_data10 */ - OMAP4_IOPAD(0x1b6, PIN_OUTPUT | MUX_MODE5) /* dispc2_data9 */ - OMAP4_IOPAD(0x1b8, PIN_OUTPUT | MUX_MODE5) /* dispc2_data16 */ - OMAP4_IOPAD(0x1ba, PIN_OUTPUT | MUX_MODE5) /* dispc2_data17 */ - OMAP4_IOPAD(0x1bc, PIN_OUTPUT | MUX_MODE5) /* dispc2_hsync */ - OMAP4_IOPAD(0x1be, PIN_OUTPUT | MUX_MODE5) /* dispc2_pclk */ - OMAP4_IOPAD(0x1c0, PIN_OUTPUT | MUX_MODE5) /* dispc2_vsync */ - OMAP4_IOPAD(0x1c2, PIN_OUTPUT | MUX_MODE5) /* dispc2_de */ - OMAP4_IOPAD(0x1c4, PIN_OUTPUT | MUX_MODE5) /* dispc2_data8 */ - OMAP4_IOPAD(0x1c6, PIN_OUTPUT | MUX_MODE5) /* dispc2_data7 */ - OMAP4_IOPAD(0x1c8, PIN_OUTPUT | MUX_MODE5) /* dispc2_data6 */ - OMAP4_IOPAD(0x1ca, PIN_OUTPUT | MUX_MODE5) /* dispc2_data5 */ - OMAP4_IOPAD(0x1cc, PIN_OUTPUT | MUX_MODE5) /* dispc2_data4 */ - OMAP4_IOPAD(0x1ce, PIN_OUTPUT | MUX_MODE5) /* dispc2_data3 */ - - OMAP4_IOPAD(0x1d0, PIN_OUTPUT | MUX_MODE5) /* dispc2_data2 */ - OMAP4_IOPAD(0x1d2, PIN_OUTPUT | MUX_MODE5) /* dispc2_data1 */ - OMAP4_IOPAD(0x1d4, PIN_OUTPUT | MUX_MODE5) /* dispc2_data0 */ - >; - }; - - tfp410_pins: pinmux_tfp410_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x184, PIN_OUTPUT | MUX_MODE3) /* gpio_0 */ - >; - }; - - dss_hdmi_pins: pinmux_dss_hdmi_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x09a, PIN_INPUT | MUX_MODE0) /* hdmi_cec.hdmi_cec */ - OMAP4_IOPAD(0x09c, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_scl.hdmi_scl */ - OMAP4_IOPAD(0x09e, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_sda.hdmi_sda */ - >; - }; - - tpd12s015_pins: pinmux_tpd12s015_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x062, PIN_OUTPUT | MUX_MODE3) /* gpmc_a17.gpio_41 */ - OMAP4_IOPAD(0x088, PIN_OUTPUT | MUX_MODE3) /* gpmc_nbe1.gpio_60 */ - OMAP4_IOPAD(0x098, PIN_INPUT_PULLDOWN | MUX_MODE3) /* hdmi_hpd.gpio_63 */ - >; - }; - - hsusbb1_pins: pinmux_hsusbb1_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x0c2, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_clk.usbb1_ulpiphy_clk */ - OMAP4_IOPAD(0x0c4, PIN_OUTPUT | MUX_MODE4) /* usbb1_ulpitll_stp.usbb1_ulpiphy_stp */ - OMAP4_IOPAD(0x0c6, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dir.usbb1_ulpiphy_dir */ - OMAP4_IOPAD(0x0c8, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_nxt.usbb1_ulpiphy_nxt */ - OMAP4_IOPAD(0x0ca, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat0.usbb1_ulpiphy_dat0 */ - OMAP4_IOPAD(0x0cc, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat1.usbb1_ulpiphy_dat1 */ - OMAP4_IOPAD(0x0ce, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat2.usbb1_ulpiphy_dat2 */ - OMAP4_IOPAD(0x0d0, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat3.usbb1_ulpiphy_dat3 */ - OMAP4_IOPAD(0x0d2, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat4.usbb1_ulpiphy_dat4 */ - OMAP4_IOPAD(0x0d4, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat5.usbb1_ulpiphy_dat5 */ - OMAP4_IOPAD(0x0d6, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat6.usbb1_ulpiphy_dat6 */ - OMAP4_IOPAD(0x0d8, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat7.usbb1_ulpiphy_dat7 */ - >; - }; - - i2c1_pins: pinmux_i2c1_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x122, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */ - OMAP4_IOPAD(0x124, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */ - >; - }; - - i2c2_pins: pinmux_i2c2_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x126, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_scl */ - OMAP4_IOPAD(0x128, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_sda */ - >; - }; - - i2c3_pins: pinmux_i2c3_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x12a, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl */ - OMAP4_IOPAD(0x12c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda */ - >; - }; - - i2c4_pins: pinmux_i2c4_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x12e, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_scl */ - OMAP4_IOPAD(0x130, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_sda */ - >; - }; - - /* - * wl12xx GPIO outputs for WLAN_EN, BT_EN, FM_EN, BT_WAKEUP - * REVISIT: Are the pull-ups needed for GPIO 48 and 49? - */ - wl12xx_gpio: pinmux_wl12xx_gpio { - pinctrl-single,pins = < - OMAP4_IOPAD(0x066, PIN_OUTPUT | MUX_MODE3) /* gpmc_a19.gpio_43 */ - OMAP4_IOPAD(0x06c, PIN_OUTPUT | MUX_MODE3) /* gpmc_a22.gpio_46 */ - OMAP4_IOPAD(0x070, PIN_OUTPUT_PULLUP | MUX_MODE3) /* gpmc_a24.gpio_48 */ - OMAP4_IOPAD(0x072, PIN_OUTPUT_PULLUP | MUX_MODE3) /* gpmc_a25.gpio_49 */ - >; - }; - - /* wl12xx GPIO inputs and SDIO pins */ - wl12xx_pins: pinmux_wl12xx_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x078, PIN_INPUT | MUX_MODE3) /* gpmc_ncs2.gpio_52 */ - OMAP4_IOPAD(0x07a, PIN_INPUT | MUX_MODE3) /* gpmc_ncs3.gpio_53 */ - OMAP4_IOPAD(0x148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_clk.sdmmc5_clk */ - OMAP4_IOPAD(0x14a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_cmd.sdmmc5_cmd */ - OMAP4_IOPAD(0x14c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat0.sdmmc5_dat0 */ - OMAP4_IOPAD(0x14e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat1.sdmmc5_dat1 */ - OMAP4_IOPAD(0x150, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat2.sdmmc5_dat2 */ - OMAP4_IOPAD(0x152, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat3.sdmmc5_dat3 */ - >; - }; - - button_pins: pinmux_button_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x114, PIN_INPUT_PULLUP | MUX_MODE3) /* gpio_121 */ - >; - }; -}; - -&omap4_pmx_wkup { - led_wkgpio_pins: pinmux_leds_wkpins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x05a, PIN_OUTPUT | MUX_MODE3) /* gpio_wk7 */ - OMAP4_IOPAD(0x05c, PIN_OUTPUT | MUX_MODE3) /* gpio_wk8 */ - >; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - - clock-frequency = <400000>; - - twl: twl@48 { - reg = <0x48>; - /* IRQ# = 7 */ - interrupts = ; /* IRQ_SYS_1N cascaded to gic */ - }; - - twl6040: twl@4b { - compatible = "ti,twl6040"; - #clock-cells = <0>; - reg = <0x4b>; - - pinctrl-names = "default"; - pinctrl-0 = <&twl6040_pins>; - - /* IRQ# = 119 */ - interrupts = ; /* IRQ_SYS_2N cascaded to gic */ - ti,audpwron-gpio = <&gpio4 31 GPIO_ACTIVE_HIGH>; /* gpio line 127 */ - - vio-supply = <&v1v8>; - v2v1-supply = <&v2v1>; - enable-active-high; - }; -}; - -#include "twl6030.dtsi" -#include "twl6030_omap4.dtsi" - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - - clock-frequency = <400000>; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_pins>; - - clock-frequency = <100000>; - - /* - * Display monitor features are burnt in their EEPROM as EDID data. - * The EEPROM is connected as I2C slave device. - */ - eeprom@50 { - compatible = "ti,eeprom"; - reg = <0x50>; - }; -}; - -&i2c4 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_pins>; - - clock-frequency = <400000>; -}; - -&mmc1 { - vmmc-supply = <&vmmc>; - bus-width = <8>; -}; - -&mmc2 { - status = "disabled"; -}; - -&mmc3 { - status = "disabled"; -}; - -&mmc4 { - status = "disabled"; -}; - -&mmc5 { - pinctrl-names = "default"; - pinctrl-0 = <&wl12xx_pins>; - vmmc-supply = <&wl12xx_vmmc>; - interrupts-extended = <&wakeupgen GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH - &omap4_pmx_core 0x10e>; - non-removable; - bus-width = <4>; - cap-power-off-card; - - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@2 { - compatible = "ti,wl1271"; - reg = <2>; - /* gpio_53 with gpmc_ncs3 pad as wakeup */ - interrupts-extended = <&gpio2 21 IRQ_TYPE_LEVEL_HIGH>, - <&omap4_pmx_core 0x3a>; - interrupt-names = "irq", "wakeup"; - ref-clock-frequency = <38400000>; - }; -}; - -&emif1 { - cs1-used; - device-handle = <&elpida_ECB240ABACN>; -}; - -&emif2 { - cs1-used; - device-handle = <&elpida_ECB240ABACN>; -}; - -&mcbsp1 { - pinctrl-names = "default"; - pinctrl-0 = <&mcbsp1_pins>; - status = "okay"; -}; - -&twl_usb_comparator { - usb-supply = <&vusb>; -}; - -&uart2 { - interrupts-extended = <&wakeupgen GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH - &omap4_pmx_core OMAP4_UART2_RX>; -}; - -&uart3 { - interrupts-extended = <&wakeupgen GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH - &omap4_pmx_core OMAP4_UART3_RX>; -}; - -&uart4 { - interrupts-extended = <&wakeupgen GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH - &omap4_pmx_core OMAP4_UART4_RX>; -}; - -&usb_otg_hs { - interface-type = <1>; - mode = <3>; - power = <50>; -}; - -&usbhshost { - port1-mode = "ehci-phy"; -}; - -&usbhsehci { - phys = <&hsusb1_phy>; - - #address-cells = <1>; - #size-cells = <0>; - - hub@1 { - compatible = "usb424,9514"; - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - ethernet: usbether@1 { - compatible = "usb424,ec00"; - reg = <1>; - }; - }; -}; - -&dss { - status = "ok"; - - port { - dpi_out: endpoint { - remote-endpoint = <&tfp410_in>; - data-lines = <24>; - }; - }; -}; - -&dsi2 { - status = "ok"; - vdd-supply = <&vcxio>; -}; - -&hdmi { - status = "ok"; - vdda-supply = <&vdac>; - - port { - hdmi_out: endpoint { - remote-endpoint = <&tpd12s015_in>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/omap4-panda-es.dts b/sys/gnu/dts/arm/omap4-panda-es.dts deleted file mode 100644 index 9dd307b5260..00000000000 --- a/sys/gnu/dts/arm/omap4-panda-es.dts +++ /dev/null @@ -1,82 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ - */ -/dts-v1/; - -#include "omap4460.dtsi" -#include "omap4-panda-common.dtsi" - -/ { - model = "TI OMAP4 PandaBoard-ES"; - compatible = "ti,omap4-panda-es", "ti,omap4-panda", "ti,omap4460", "ti,omap4430", "ti,omap4"; -}; - -/* Audio routing is differnet between PandaBoard4430 and PandaBoardES */ -&sound { - ti,model = "PandaBoardES"; - - /* Audio routing */ - ti,audio-routing = - "Headset Stereophone", "HSOL", - "Headset Stereophone", "HSOR", - "Ext Spk", "HFL", - "Ext Spk", "HFR", - "Line Out", "AUXL", - "Line Out", "AUXR", - "AFML", "Line In", - "AFMR", "Line In"; -}; - -/* PandaboardES has external pullups on SCL & SDA */ -&dss_hdmi_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x09a, PIN_INPUT | MUX_MODE0) /* hdmi_cec.hdmi_cec */ - OMAP4_IOPAD(0x09c, PIN_INPUT | MUX_MODE0) /* hdmi_scl.hdmi_scl */ - OMAP4_IOPAD(0x09e, PIN_INPUT | MUX_MODE0) /* hdmi_sda.hdmi_sda */ - >; -}; - -&omap4_pmx_core { - led_gpio_pins: gpio_led_pmx { - pinctrl-single,pins = < - OMAP4_IOPAD(0x0f6, PIN_OUTPUT | MUX_MODE3) /* gpio_110 */ - >; - }; - - button_pins: pinmux_button_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x11b, PIN_INPUT_PULLUP | MUX_MODE3) /* gpio_113 */ - >; - }; -}; - -&led_wkgpio_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x05c, PIN_OUTPUT | MUX_MODE3) /* gpio_wk8 */ - >; -}; - -&leds { - pinctrl-0 = < - &led_gpio_pins - &led_wkgpio_pins - >; - - heartbeat { - gpios = <&gpio4 14 GPIO_ACTIVE_HIGH>; - }; - mmc { - gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; - }; -}; - -&gpio_keys { - buttonS2 { - gpios = <&gpio4 17 GPIO_ACTIVE_LOW>; /* gpio_113 */ - }; -}; - -&gpio1_target { - ti,no-reset-on-init; -}; diff --git a/sys/gnu/dts/arm/omap4-panda.dts b/sys/gnu/dts/arm/omap4-panda.dts deleted file mode 100644 index fb2f47717b4..00000000000 --- a/sys/gnu/dts/arm/omap4-panda.dts +++ /dev/null @@ -1,13 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ - */ -/dts-v1/; - -#include "omap443x.dtsi" -#include "omap4-panda-common.dtsi" - -/ { - model = "TI OMAP4 PandaBoard"; - compatible = "ti,omap4-panda", "ti,omap4430", "ti,omap4"; -}; diff --git a/sys/gnu/dts/arm/omap4-sdp-es23plus.dts b/sys/gnu/dts/arm/omap4-sdp-es23plus.dts deleted file mode 100644 index 42154520d38..00000000000 --- a/sys/gnu/dts/arm/omap4-sdp-es23plus.dts +++ /dev/null @@ -1,14 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ - */ -#include "omap4-sdp.dts" - -/* SDP boards with 4430 ES2.3+ or 4460 have external pullups on SCL & SDA */ -&dss_hdmi_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x09a, PIN_INPUT | MUX_MODE0) /* hdmi_cec.hdmi_cec */ - OMAP4_IOPAD(0x09c, PIN_INPUT | MUX_MODE0) /* hdmi_scl.hdmi_scl */ - OMAP4_IOPAD(0x09e, PIN_INPUT | MUX_MODE0) /* hdmi_sda.hdmi_sda */ - >; -}; diff --git a/sys/gnu/dts/arm/omap4-sdp.dts b/sys/gnu/dts/arm/omap4-sdp.dts deleted file mode 100644 index 91480ac1f32..00000000000 --- a/sys/gnu/dts/arm/omap4-sdp.dts +++ /dev/null @@ -1,713 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ - */ -/dts-v1/; - -#include "omap443x.dtsi" -#include "elpida_ecb240abacn.dtsi" -#include "omap4-mcpdm.dtsi" - -/ { - model = "TI OMAP4 SDP board"; - compatible = "ti,omap4-sdp", "ti,omap4430", "ti,omap4"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x40000000>; /* 1 GB */ - }; - - aliases { - display0 = &lcd0; - display1 = &lcd1; - display2 = &hdmi0; - }; - - vdd_eth: fixedregulator-vdd-eth { - pinctrl-names = "default"; - pinctrl-0 = <&enet_enable_gpio>; - - compatible = "regulator-fixed"; - regulator-name = "VDD_ETH"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 16 GPIO_ACTIVE_HIGH>; /* gpio line 48 */ - enable-active-high; - regulator-boot-on; - startup-delay-us = <25000>; - }; - - vbat: fixedregulator-vbat { - compatible = "regulator-fixed"; - regulator-name = "VBAT"; - regulator-min-microvolt = <3750000>; - regulator-max-microvolt = <3750000>; - regulator-boot-on; - }; - - leds { - compatible = "gpio-leds"; - debug0 { - label = "omap4:green:debug0"; - gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>; /* 61 */ - }; - - debug1 { - label = "omap4:green:debug1"; - gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; /* 30 */ - }; - - debug2 { - label = "omap4:green:debug2"; - gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; /* 7 */ - }; - - debug3 { - label = "omap4:green:debug3"; - gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; /* 8 */ - }; - - debug4 { - label = "omap4:green:debug4"; - gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>; /* 50 */ - }; - - user1 { - label = "omap4:blue:user"; - gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; /* 169 */ - }; - - user2 { - label = "omap4:red:user"; - gpios = <&gpio6 10 GPIO_ACTIVE_HIGH>; /* 170 */ - }; - - user3 { - label = "omap4:green:user"; - gpios = <&gpio5 11 GPIO_ACTIVE_HIGH>; /* 139 */ - }; - }; - - pwmleds { - compatible = "pwm-leds"; - kpad { - label = "omap4::keypad"; - pwms = <&twl_pwm 0 7812500>; - max-brightness = <127>; - }; - - charging { - label = "omap4:green:chrg"; - pwms = <&twl_pwmled 0 7812500>; - max-brightness = <255>; - }; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&twl_pwm 1 7812500>; - brightness-levels = < - 0 10 20 30 40 - 50 60 70 80 90 - 100 110 120 127 - >; - default-brightness-level = <13>; - }; - - sound { - compatible = "ti,abe-twl6040"; - ti,model = "SDP4430"; - - ti,jack-detection = <1>; - ti,mclk-freq = <38400000>; - - ti,mcpdm = <&mcpdm>; - ti,dmic = <&dmic>; - - ti,twl6040 = <&twl6040>; - - /* Audio routing */ - ti,audio-routing = - "Headset Stereophone", "HSOL", - "Headset Stereophone", "HSOR", - "Earphone Spk", "EP", - "Ext Spk", "HFL", - "Ext Spk", "HFR", - "Line Out", "AUXL", - "Line Out", "AUXR", - "Vibrator", "VIBRAL", - "Vibrator", "VIBRAR", - "HSMIC", "Headset Mic", - "Headset Mic", "Headset Mic Bias", - "MAINMIC", "Main Handset Mic", - "Main Handset Mic", "Main Mic Bias", - "SUBMIC", "Sub Handset Mic", - "Sub Handset Mic", "Main Mic Bias", - "AFML", "Line In", - "AFMR", "Line In", - "DMic", "Digital Mic", - "Digital Mic", "Digital Mic1 Bias"; - }; - - /* regulator for wl12xx on sdio5 */ - wl12xx_vmmc: wl12xx_vmmc { - pinctrl-names = "default"; - pinctrl-0 = <&wl12xx_gpio>; - compatible = "regulator-fixed"; - regulator-name = "vwl1271"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio2 22 GPIO_ACTIVE_HIGH>; - startup-delay-us = <70000>; - enable-active-high; - }; - - tpd12s015: encoder { - compatible = "ti,tpd12s015"; - - gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>, /* 60, CT CP HPD */ - <&gpio2 9 GPIO_ACTIVE_HIGH>, /* 41, LS OE */ - <&gpio2 31 GPIO_ACTIVE_HIGH>; /* 63, HPD */ - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - tpd12s015_in: endpoint { - remote-endpoint = <&hdmi_out>; - }; - }; - - port@1 { - reg = <1>; - - tpd12s015_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; - }; - }; - }; - - hdmi0: connector { - compatible = "hdmi-connector"; - label = "hdmi"; - - type = "c"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&tpd12s015_out>; - }; - }; - }; -}; - -&omap4_pmx_core { - pinctrl-names = "default"; - pinctrl-0 = < - &dss_hdmi_pins - &tpd12s015_pins - >; - - uart2_pins: pinmux_uart2_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x118, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts.uart2_cts */ - OMAP4_IOPAD(0x11a, PIN_OUTPUT | MUX_MODE0) /* uart2_rts.uart2_rts */ - OMAP4_IOPAD(0x11c, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_rx.uart2_rx */ - OMAP4_IOPAD(0x11e, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ - >; - }; - - uart3_pins: pinmux_uart3_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x140, PIN_INPUT_PULLUP | MUX_MODE0) /* uart3_cts_rctx.uart3_cts_rctx */ - OMAP4_IOPAD(0x142, PIN_OUTPUT | MUX_MODE0) /* uart3_rts_sd.uart3_rts_sd */ - OMAP4_IOPAD(0x144, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ - OMAP4_IOPAD(0x146, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ - >; - }; - - uart4_pins: pinmux_uart4_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x15c, PIN_INPUT | MUX_MODE0) /* uart4_rx.uart4_rx */ - OMAP4_IOPAD(0x15e, PIN_OUTPUT | MUX_MODE0) /* uart4_tx.uart4_tx */ - >; - }; - - twl6040_pins: pinmux_twl6040_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x120, PIN_OUTPUT | MUX_MODE3) /* hdq_sio.gpio_127 */ - OMAP4_IOPAD(0x1a0, PIN_INPUT | MUX_MODE0) /* sys_nirq2.sys_nirq2 */ - >; - }; - - dmic_pins: pinmux_dmic_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x110, PIN_OUTPUT | MUX_MODE0) /* abe_dmic_clk1.abe_dmic_clk1 */ - OMAP4_IOPAD(0x112, PIN_INPUT | MUX_MODE0) /* abe_dmic_din1.abe_dmic_din1 */ - OMAP4_IOPAD(0x114, PIN_INPUT | MUX_MODE0) /* abe_dmic_din2.abe_dmic_din2 */ - OMAP4_IOPAD(0x116, PIN_INPUT | MUX_MODE0) /* abe_dmic_din3.abe_dmic_din3 */ - >; - }; - - mcbsp1_pins: pinmux_mcbsp1_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x0fe, PIN_INPUT | MUX_MODE0) /* abe_mcbsp1_clkx.abe_mcbsp1_clkx */ - OMAP4_IOPAD(0x100, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp1_dr.abe_mcbsp1_dr */ - OMAP4_IOPAD(0x102, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp1_dx.abe_mcbsp1_dx */ - OMAP4_IOPAD(0x104, PIN_INPUT | MUX_MODE0) /* abe_mcbsp1_fsx.abe_mcbsp1_fsx */ - >; - }; - - mcbsp2_pins: pinmux_mcbsp2_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x0f6, PIN_INPUT | MUX_MODE0) /* abe_mcbsp2_clkx.abe_mcbsp2_clkx */ - OMAP4_IOPAD(0x0f8, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp2_dr.abe_mcbsp2_dr */ - OMAP4_IOPAD(0x0fa, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp2_dx.abe_mcbsp2_dx */ - OMAP4_IOPAD(0x0fc, PIN_INPUT | MUX_MODE0) /* abe_mcbsp2_fsx.abe_mcbsp2_fsx */ - >; - }; - - mcspi1_pins: pinmux_mcspi1_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x132, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */ - OMAP4_IOPAD(0x134, PIN_INPUT | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */ - OMAP4_IOPAD(0x136, PIN_INPUT | MUX_MODE0) /* mcspi1_simo.mcspi1_simo */ - OMAP4_IOPAD(0x138, PIN_INPUT | MUX_MODE0) /* mcspi1_cs0.mcspi1_cs0 */ - >; - }; - - dss_hdmi_pins: pinmux_dss_hdmi_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x09a, PIN_INPUT | MUX_MODE0) /* hdmi_cec.hdmi_cec */ - OMAP4_IOPAD(0x09c, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_scl.hdmi_scl */ - OMAP4_IOPAD(0x09e, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_sda.hdmi_sda */ - >; - }; - - tpd12s015_pins: pinmux_tpd12s015_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x062, PIN_OUTPUT | MUX_MODE3) /* gpmc_a17.gpio_41 */ - OMAP4_IOPAD(0x088, PIN_OUTPUT | MUX_MODE3) /* gpmc_nbe1.gpio_60 */ - OMAP4_IOPAD(0x098, PIN_INPUT_PULLDOWN | MUX_MODE3) /* hdmi_hpd.gpio_63 */ - >; - }; - - i2c1_pins: pinmux_i2c1_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x122, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */ - OMAP4_IOPAD(0x124, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */ - >; - }; - - i2c2_pins: pinmux_i2c2_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x126, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_scl */ - OMAP4_IOPAD(0x128, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_sda */ - >; - }; - - i2c3_pins: pinmux_i2c3_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x12a, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl */ - OMAP4_IOPAD(0x12c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda */ - >; - }; - - i2c4_pins: pinmux_i2c4_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x12e, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_scl */ - OMAP4_IOPAD(0x130, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_sda */ - >; - }; - - /* wl12xx GPIO output for WLAN_EN */ - wl12xx_gpio: pinmux_wl12xx_gpio { - pinctrl-single,pins = < - OMAP4_IOPAD(0x07c, PIN_OUTPUT | MUX_MODE3) /* gpmc_nwp.gpio_54 */ - >; - }; - - /* wl12xx GPIO inputs and SDIO pins */ - wl12xx_pins: pinmux_wl12xx_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x07a, PIN_INPUT | MUX_MODE3) /* gpmc_ncs3.gpio_53 */ - OMAP4_IOPAD(0x148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_clk.sdmmc5_clk */ - OMAP4_IOPAD(0x14a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_cmd.sdmmc5_cmd */ - OMAP4_IOPAD(0x14c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat0.sdmmc5_dat0 */ - OMAP4_IOPAD(0x14e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat1.sdmmc5_dat1 */ - OMAP4_IOPAD(0x150, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat2.sdmmc5_dat2 */ - OMAP4_IOPAD(0x152, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat3.sdmmc5_dat3 */ - >; - }; - - /* gpio_48 for ENET_ENABLE */ - enet_enable_gpio: pinmux_enet_enable_gpio { - pinctrl-single,pins = < - OMAP4_IOPAD(0x070, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* gpmc_a24.gpio_48 */ - >; - }; - - ks8851_pins: pinmux_ks8851_pins { - pinctrl-single,pins = < - /* ENET_INT */ - OMAP4_IOPAD(0x054, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_ad10.gpio_34 */ - /* - * Misterious pin which makes the ethernet working - * The legacy board file requested this pin on boot - * (ETH_KS8851_QUART) and set it to high, similarly to - * the ENET_ENABLE pin. - * We could use gpio-hog to keep it high, but let's use - * it as a reset GPIO for ks8851. - */ - OMAP4_IOPAD(0x13a, PIN_OUTPUT_PULLUP | MUX_MODE3) /* mcspi1_cs1.gpio_138 */ - >; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - - clock-frequency = <400000>; - - twl: twl@48 { - reg = <0x48>; - /* SPI = 0, IRQ# = 7, 4 = active high level-sensitive */ - interrupts = ; /* IRQ_SYS_1N cascaded to gic */ - }; - - twl6040: twl@4b { - compatible = "ti,twl6040"; - #clock-cells = <0>; - reg = <0x4b>; - - pinctrl-names = "default"; - pinctrl-0 = <&twl6040_pins>; - - /* SPI = 0, IRQ# = 119, 4 = active high level-sensitive */ - interrupts = ; /* IRQ_SYS_2N cascaded to gic */ - ti,audpwron-gpio = <&gpio4 31 GPIO_ACTIVE_HIGH>; /* gpio line 127 */ - - vio-supply = <&v1v8>; - v2v1-supply = <&v2v1>; - enable-active-high; - - /* regulators for vibra motor */ - vddvibl-supply = <&vbat>; - vddvibr-supply = <&vbat>; - - vibra { - /* Vibra driver, motor resistance parameters */ - ti,vibldrv-res = <8>; - ti,vibrdrv-res = <3>; - ti,viblmotor-res = <10>; - ti,vibrmotor-res = <10>; - }; - }; -}; - -#include "twl6030.dtsi" -#include "twl6030_omap4.dtsi" - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - - clock-frequency = <400000>; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_pins>; - - clock-frequency = <400000>; - - /* - * Temperature Sensor - * http://www.ti.com/lit/ds/symlink/tmp105.pdf - */ - tmp105@48 { - compatible = "ti,tmp105"; - reg = <0x48>; - }; - - /* - * Ambient Light Sensor - * http://www.rohm.com/products/databook/sensor/pdf/bh1780gli-e.pdf - */ - bh1780@29 { - compatible = "rohm,bh1780"; - reg = <0x29>; - }; -}; - -&i2c4 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_pins>; - - clock-frequency = <400000>; - - /* - * 3-Axis Digital Compass - * http://www.sparkfun.com/datasheets/Sensors/Magneto/HMC5843.pdf - */ - hmc5843@1e { - compatible = "honeywell,hmc5843"; - reg = <0x1e>; - }; -}; - -&mcspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&mcspi1_pins>; - - eth@0 { - pinctrl-names = "default"; - pinctrl-0 = <&ks8851_pins>; - - compatible = "ks8851"; - spi-max-frequency = <24000000>; - reg = <0>; - interrupt-parent = <&gpio2>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; /* gpio line 34 */ - vdd-supply = <&vdd_eth>; - reset-gpios = <&gpio5 10 GPIO_ACTIVE_HIGH>; - }; -}; - -&mmc1 { - vmmc-supply = <&vmmc>; - bus-width = <8>; -}; - -&mmc2 { - vmmc-supply = <&vaux1>; - bus-width = <8>; - ti,non-removable; -}; - -&mmc3 { - status = "disabled"; -}; - -&mmc4 { - status = "disabled"; -}; - -&mmc5 { - pinctrl-names = "default"; - pinctrl-0 = <&wl12xx_pins>; - vmmc-supply = <&wl12xx_vmmc>; - non-removable; - bus-width = <4>; - cap-power-off-card; - - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@2 { - compatible = "ti,wl1281"; - reg = <2>; - interrupt-parent = <&gpio1>; - interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; /* gpio 53 */ - ref-clock-frequency = <26000000>; - tcxo-clock-frequency = <26000000>; - }; -}; - -&emif1 { - cs1-used; - device-handle = <&elpida_ECB240ABACN>; -}; - -&emif2 { - cs1-used; - device-handle = <&elpida_ECB240ABACN>; -}; - -&keypad { - keypad,num-rows = <8>; - keypad,num-columns = <8>; - linux,keymap = <0x00000012 /* KEY_E */ - 0x00010013 /* KEY_R */ - 0x00020014 /* KEY_T */ - 0x00030066 /* KEY_HOME */ - 0x0004003f /* KEY_F5 */ - 0x000500f0 /* KEY_UNKNOWN */ - 0x00060017 /* KEY_I */ - 0x0007002a /* KEY_LEFTSHIFT */ - 0x01000020 /* KEY_D*/ - 0x01010021 /* KEY_F */ - 0x01020022 /* KEY_G */ - 0x010300e7 /* KEY_SEND */ - 0x01040040 /* KEY_F6 */ - 0x010500f0 /* KEY_UNKNOWN */ - 0x01060025 /* KEY_K */ - 0x0107001c /* KEY_ENTER */ - 0x0200002d /* KEY_X */ - 0x0201002e /* KEY_C */ - 0x0202002f /* KEY_V */ - 0x0203006b /* KEY_END */ - 0x02040041 /* KEY_F7 */ - 0x020500f0 /* KEY_UNKNOWN */ - 0x02060034 /* KEY_DOT */ - 0x0207003a /* KEY_CAPSLOCK */ - 0x0300002c /* KEY_Z */ - 0x0301004e /* KEY_KPLUS */ - 0x03020030 /* KEY_B */ - 0x0303003b /* KEY_F1 */ - 0x03040042 /* KEY_F8 */ - 0x030500f0 /* KEY_UNKNOWN */ - 0x03060018 /* KEY_O */ - 0x03070039 /* KEY_SPACE */ - 0x04000011 /* KEY_W */ - 0x04010015 /* KEY_Y */ - 0x04020016 /* KEY_U */ - 0x0403003c /* KEY_F2 */ - 0x04040073 /* KEY_VOLUMEUP */ - 0x040500f0 /* KEY_UNKNOWN */ - 0x04060026 /* KEY_L */ - 0x04070069 /* KEY_LEFT */ - 0x0500001f /* KEY_S */ - 0x05010023 /* KEY_H */ - 0x05020024 /* KEY_J */ - 0x0503003d /* KEY_F3 */ - 0x05040043 /* KEY_F9 */ - 0x05050072 /* KEY_VOLUMEDOWN */ - 0x05060032 /* KEY_M */ - 0x0507006a /* KEY_RIGHT */ - 0x06000010 /* KEY_Q */ - 0x0601001e /* KEY_A */ - 0x06020031 /* KEY_N */ - 0x0603009e /* KEY_BACK */ - 0x0604000e /* KEY_BACKSPACE */ - 0x060500f0 /* KEY_UNKNOWN */ - 0x06060019 /* KEY_P */ - 0x06070067 /* KEY_UP */ - 0x07000094 /* KEY_PROG1 */ - 0x07010095 /* KEY_PROG2 */ - 0x070200ca /* KEY_PROG3 */ - 0x070300cb /* KEY_PROG4 */ - 0x0704003e /* KEY_F4 */ - 0x070500f0 /* KEY_UNKNOWN */ - 0x07060160 /* KEY_OK */ - 0x0707006c>; /* KEY_DOWN */ - linux,input-no-autorepeat; -}; - -&uart2 { - interrupts-extended = <&wakeupgen GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH - &omap4_pmx_core OMAP4_UART2_RX>; - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; -}; - -&uart3 { - interrupts-extended = <&wakeupgen GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH - &omap4_pmx_core OMAP4_UART3_RX>; - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; -}; - -&uart4 { - interrupts-extended = <&wakeupgen GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH - &omap4_pmx_core OMAP4_UART4_RX>; - pinctrl-names = "default"; - pinctrl-0 = <&uart4_pins>; -}; - -&mcbsp1 { - pinctrl-names = "default"; - pinctrl-0 = <&mcbsp1_pins>; - status = "okay"; -}; - -&mcbsp2 { - pinctrl-names = "default"; - pinctrl-0 = <&mcbsp2_pins>; - status = "okay"; -}; - -&dmic { - pinctrl-names = "default"; - pinctrl-0 = <&dmic_pins>; - status = "okay"; -}; - -&twl_usb_comparator { - usb-supply = <&vusb>; -}; - -&usb_otg_hs { - interface-type = <1>; - mode = <3>; - power = <50>; -}; - -&dss { - status = "ok"; -}; - -&dsi1 { - status = "ok"; - vdd-supply = <&vcxio>; - - port { - dsi1_out_ep: endpoint { - remote-endpoint = <&lcd0_in>; - lanes = <0 1 2 3 4 5>; - }; - }; - - lcd0: display { - compatible = "tpo,taal", "panel-dsi-cm"; - label = "lcd0"; - - reset-gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* 102 */ - - port { - lcd0_in: endpoint { - remote-endpoint = <&dsi1_out_ep>; - }; - }; - }; -}; - -&dsi2 { - status = "ok"; - vdd-supply = <&vcxio>; - - port { - dsi2_out_ep: endpoint { - remote-endpoint = <&lcd1_in>; - lanes = <0 1 2 3 4 5>; - }; - }; - - lcd1: display { - compatible = "tpo,taal", "panel-dsi-cm"; - label = "lcd1"; - - reset-gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; /* 104 */ - - port { - lcd1_in: endpoint { - remote-endpoint = <&dsi2_out_ep>; - }; - }; - }; -}; - -&hdmi { - status = "ok"; - vdda-supply = <&vdac>; - - port { - hdmi_out: endpoint { - remote-endpoint = <&tpd12s015_in>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/omap4-var-dvk-om44.dts b/sys/gnu/dts/arm/omap4-var-dvk-om44.dts deleted file mode 100644 index 84fd17fb082..00000000000 --- a/sys/gnu/dts/arm/omap4-var-dvk-om44.dts +++ /dev/null @@ -1,68 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 Joachim Eastwood - */ -/dts-v1/; - -#include "omap4-var-som-om44.dtsi" -#include "omap4-var-som-om44-wlan.dtsi" -#include "omap4-var-om44customboard.dtsi" - -/ { - model = "Variscite VAR-DVK-OM44"; - compatible = "variscite,var-dvk-om44", "variscite,var-som-om44", "ti,omap4460", "ti,omap4"; - - aliases { - display0 = &lcd0; - display1 = &hdmi0; - }; - - lcd0: display { - compatible = "innolux,at070tn83", "panel-dpi"; - label = "lcd"; - panel-timing { - clock-frequency = <33333333>; - - hback-porch = <40>; - hactive = <800>; - hfront-porch = <40>; - hsync-len = <48>; - - vback-porch = <29>; - vactive = <480>; - vfront-porch = <13>; - vsync-len = <3>; - }; - - port { - lcd_in: endpoint { - remote-endpoint = <&dpi_out>; - }; - }; - }; - - backlight { - compatible = "gpio-backlight"; - pinctrl-names = "default"; - pinctrl-0 = <&backlight_pins>; - - gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>; /* gpio 122 */ - }; -}; - -&dss { - pinctrl-names = "default"; - pinctrl-0 = <&dss_dpi_pins>; - - port { - dpi_out: endpoint { - remote-endpoint = <&lcd_in>; - data-lines = <24>; - }; - }; -}; - -&dsi2 { - status = "okay"; - vdd-supply = <&vcxio>; -}; diff --git a/sys/gnu/dts/arm/omap4-var-om44customboard.dtsi b/sys/gnu/dts/arm/omap4-var-om44customboard.dtsi deleted file mode 100644 index 458cb53dd3d..00000000000 --- a/sys/gnu/dts/arm/omap4-var-om44customboard.dtsi +++ /dev/null @@ -1,232 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 Joachim Eastwood - */ - -#include - -/ { - aliases { - display0 = &hdmi0; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&gpio_led_pins>; - - led0 { - label = "var:green:led0"; - gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>; /* gpio 173 */ - linux,default-trigger = "heartbeat"; - }; - - led1 { - label = "var:green:led1"; - gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>; /* gpio 172 */ - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&gpio_key_pins>; - #address-cells = <1>; - #size-cells = <0>; - - user-key@184 { - label = "user"; - gpios = <&gpio6 24 GPIO_ACTIVE_HIGH>; /* gpio 184 */ - linux,code = ; - wakeup-source; - }; - }; - - hdmi0: connector { - compatible = "hdmi-connector"; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_hpd_pins>; - label = "hdmi"; - type = "a"; - - hpd-gpios = <&gpio2 31 GPIO_ACTIVE_HIGH>; /* gpio_63 */ - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_out>; - }; - }; - }; -}; - -&omap4_pmx_core { - uart1_pins: pinmux_uart1_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x13c, PIN_INPUT_PULLUP | MUX_MODE1) /* mcspi1_cs2.uart1_cts */ - OMAP4_IOPAD(0x13e, PIN_OUTPUT | MUX_MODE1) /* mcspi1_cs3.uart1_rts */ - OMAP4_IOPAD(0x126, PIN_INPUT_PULLUP | MUX_MODE1) /* i2c2_scl.uart1_rx */ - OMAP4_IOPAD(0x128, PIN_OUTPUT | MUX_MODE1) /* i2c2_sda.uart1_tx */ - >; - }; - - mcspi1_pins: pinmux_mcspi1_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x132, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */ - OMAP4_IOPAD(0x134, PIN_INPUT | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */ - OMAP4_IOPAD(0x136, PIN_INPUT | MUX_MODE0) /* mcspi1_simo.mcspi1_simo */ - OMAP4_IOPAD(0x138, PIN_INPUT | MUX_MODE0) /* mcspi1_cs0.mcspi1_cs0 */ - >; - }; - - mcasp_pins: pinmux_mcsasp_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x0f8, PIN_OUTPUT | MUX_MODE2) /* mcbsp2_dr.abe_mcasp_axr */ - >; - }; - - dss_dpi_pins: pinmux_dss_dpi_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x162, PIN_OUTPUT | MUX_MODE5) /* dispc2_data23 */ - OMAP4_IOPAD(0x164, PIN_OUTPUT | MUX_MODE5) /* dispc2_data22 */ - OMAP4_IOPAD(0x166, PIN_OUTPUT | MUX_MODE5) /* dispc2_data21 */ - OMAP4_IOPAD(0x168, PIN_OUTPUT | MUX_MODE5) /* dispc2_data20 */ - OMAP4_IOPAD(0x16a, PIN_OUTPUT | MUX_MODE5) /* dispc2_data19 */ - OMAP4_IOPAD(0x16c, PIN_OUTPUT | MUX_MODE5) /* dispc2_data18 */ - OMAP4_IOPAD(0x16e, PIN_OUTPUT | MUX_MODE5) /* dispc2_data15 */ - OMAP4_IOPAD(0x170, PIN_OUTPUT | MUX_MODE5) /* dispc2_data14 */ - OMAP4_IOPAD(0x172, PIN_OUTPUT | MUX_MODE5) /* dispc2_data13 */ - OMAP4_IOPAD(0x174, PIN_OUTPUT | MUX_MODE5) /* dispc2_data12 */ - OMAP4_IOPAD(0x176, PIN_OUTPUT | MUX_MODE5) /* dispc2_data11 */ - OMAP4_IOPAD(0x1b4, PIN_OUTPUT | MUX_MODE5) /* dispc2_data10 */ - OMAP4_IOPAD(0x1b6, PIN_OUTPUT | MUX_MODE5) /* dispc2_data9 */ - OMAP4_IOPAD(0x1b8, PIN_OUTPUT | MUX_MODE5) /* dispc2_data16 */ - OMAP4_IOPAD(0x1ba, PIN_OUTPUT | MUX_MODE5) /* dispc2_data17 */ - OMAP4_IOPAD(0x1bc, PIN_OUTPUT | MUX_MODE5) /* dispc2_hsync */ - OMAP4_IOPAD(0x1be, PIN_OUTPUT | MUX_MODE5) /* dispc2_pclk */ - OMAP4_IOPAD(0x1c0, PIN_OUTPUT | MUX_MODE5) /* dispc2_vsync */ - OMAP4_IOPAD(0x1c2, PIN_OUTPUT | MUX_MODE5) /* dispc2_de */ - OMAP4_IOPAD(0x1c4, PIN_OUTPUT | MUX_MODE5) /* dispc2_data8 */ - OMAP4_IOPAD(0x1c6, PIN_OUTPUT | MUX_MODE5) /* dispc2_data7 */ - OMAP4_IOPAD(0x1c8, PIN_OUTPUT | MUX_MODE5) /* dispc2_data6 */ - OMAP4_IOPAD(0x1ca, PIN_OUTPUT | MUX_MODE5) /* dispc2_data5 */ - OMAP4_IOPAD(0x1cc, PIN_OUTPUT | MUX_MODE5) /* dispc2_data4 */ - OMAP4_IOPAD(0x1ce, PIN_OUTPUT | MUX_MODE5) /* dispc2_data3 */ - OMAP4_IOPAD(0x1d0, PIN_OUTPUT | MUX_MODE5) /* dispc2_data2 */ - OMAP4_IOPAD(0x1d2, PIN_OUTPUT | MUX_MODE5) /* dispc2_data1 */ - OMAP4_IOPAD(0x1d4, PIN_OUTPUT | MUX_MODE5) /* dispc2_data0 */ - >; - }; - - dss_hdmi_pins: pinmux_dss_hdmi_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x09a, PIN_INPUT | MUX_MODE0) /* hdmi_cec.hdmi_cec */ - OMAP4_IOPAD(0x09c, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_scl.hdmi_scl */ - OMAP4_IOPAD(0x09e, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_sda.hdmi_sda */ - >; - }; - - i2c4_pins: pinmux_i2c4_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x12e, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_scl */ - OMAP4_IOPAD(0x130, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_sda */ - >; - }; - - mmc5_pins: pinmux_mmc5_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x0f6, PIN_INPUT | MUX_MODE3) /* abe_mcbsp2_clkx.gpio_110 */ - OMAP4_IOPAD(0x148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_clk.sdmmc5_clk */ - OMAP4_IOPAD(0x14a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_cmd.sdmmc5_cmd */ - OMAP4_IOPAD(0x14c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat0.sdmmc5_dat0 */ - OMAP4_IOPAD(0x14e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat1.sdmmc5_dat1 */ - OMAP4_IOPAD(0x150, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat2.sdmmc5_dat2 */ - OMAP4_IOPAD(0x152, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat3.sdmmc5_dat3 */ - >; - }; - - gpio_led_pins: pinmux_gpio_led_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x17e, PIN_OUTPUT | MUX_MODE3) /* kpd_col4.gpio_172 */ - OMAP4_IOPAD(0x180, PIN_OUTPUT | MUX_MODE3) /* kpd_col5.gpio_173 */ - >; - }; - - gpio_key_pins: pinmux_gpio_key_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x1a2, PIN_INPUT | MUX_MODE3) /* sys_boot0.gpio_184 */ - >; - }; - - ks8851_irq_pins: pinmux_ks8851_irq_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x17c, PIN_INPUT_PULLUP | MUX_MODE3) /* kpd_col3.gpio_171 */ - >; - }; - - hdmi_hpd_pins: pinmux_hdmi_hpd_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x098, PIN_INPUT_PULLDOWN | MUX_MODE3) /* hdmi_hpd.gpio_63 */ - >; - }; - - backlight_pins: pinmux_backlight_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x116, PIN_OUTPUT | MUX_MODE3) /* abe_dmic_din3.gpio_122 */ - >; - }; -}; - -&i2c4 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_pins>; - clock-frequency = <400000>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; - status = "okay"; -}; - -&mcspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&mcspi1_pins>; - status = "okay"; - - eth@0 { - compatible = "ks8851"; - pinctrl-names = "default"; - pinctrl-0 = <&ks8851_irq_pins>; - spi-max-frequency = <24000000>; - reg = <0>; - interrupt-parent = <&gpio6>; - interrupts = <11 IRQ_TYPE_LEVEL_LOW>; /* gpio 171 */ - }; -}; - -&mmc5 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc5_pins>; - vmmc-supply = <&vbat>; - bus-width = <4>; - cd-gpios = <&gpio4 14 GPIO_ACTIVE_HIGH>; /* gpio 110 */ - status = "okay"; -}; - -&dss { - status = "okay"; -}; - -&hdmi { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&dss_hdmi_pins>; - vdda-supply = <&vdac>; - - port { - hdmi_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/omap4-var-som-om44-wlan.dtsi b/sys/gnu/dts/arm/omap4-var-som-om44-wlan.dtsi deleted file mode 100644 index d0032213101..00000000000 --- a/sys/gnu/dts/arm/omap4-var-som-om44-wlan.dtsi +++ /dev/null @@ -1,75 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 Joachim Eastwood - */ - -/ { - /* regulator for wl12xx on sdio4 */ - wl12xx_vmmc: wl12xx_vmmc { - pinctrl-names = "default"; - pinctrl-0 = <&wl12xx_ctrl_pins>; - compatible = "regulator-fixed"; - regulator-name = "vwl1271"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>; /* gpio 43 */ - startup-delay-us = <70000>; - enable-active-high; - }; -}; - -&omap4_pmx_core { - uart2_pins: pinmux_uart2_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x118, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts.uart2_cts */ - OMAP4_IOPAD(0x11a, PIN_OUTPUT | MUX_MODE0) /* uart2_rts.uart2_rts */ - OMAP4_IOPAD(0x11c, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_rx.uart2_rx */ - OMAP4_IOPAD(0x11e, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ - >; - }; - - wl12xx_ctrl_pins: pinmux_wl12xx_ctrl_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x062, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a17.gpio_41 (WLAN_IRQ) */ - OMAP4_IOPAD(0x064, PIN_OUTPUT | MUX_MODE3) /* gpmc_a18.gpio_42 (BT_EN) */ - OMAP4_IOPAD(0x066, PIN_OUTPUT | MUX_MODE3) /* gpmc_a19.gpio_43 (WLAN_EN) */ - >; - }; - - mmc4_pins: pinmux_mmc4_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x154, PIN_INPUT_PULLUP | MUX_MODE1) /* mcspi4_clk.sdmmc4_clk */ - OMAP4_IOPAD(0x156, PIN_INPUT_PULLUP | MUX_MODE1) /* mcspi4_simo.sdmmc4_cmd */ - OMAP4_IOPAD(0x158, PIN_INPUT_PULLUP | MUX_MODE1) /* mcspi4_somi.sdmmc4_dat0 */ - OMAP4_IOPAD(0x15e, PIN_INPUT_PULLUP | MUX_MODE1) /* uart4_tx.sdmmc4_dat1 */ - OMAP4_IOPAD(0x15c, PIN_INPUT_PULLUP | MUX_MODE1) /* uart4_rx.sdmmc4_dat2 */ - OMAP4_IOPAD(0x15a, PIN_INPUT_PULLUP | MUX_MODE1) /* mcspi4_cs0.sdmmc4_dat3 */ - >; - }; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; - status = "okay"; -}; - -&mmc4 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc4_pins>; - vmmc-supply = <&wl12xx_vmmc>; - non-removable; - bus-width = <4>; - cap-power-off-card; - status = "okay"; - - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@2 { - compatible = "ti,wl1271"; - reg = <2>; - interrupt-parent = <&gpio2>; - interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; /* gpio 41 */ - ref-clock-frequency = <38400000>; - }; -}; diff --git a/sys/gnu/dts/arm/omap4-var-som-om44.dtsi b/sys/gnu/dts/arm/omap4-var-som-om44.dtsi deleted file mode 100644 index 41de32bcf18..00000000000 --- a/sys/gnu/dts/arm/omap4-var-som-om44.dtsi +++ /dev/null @@ -1,325 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 Joachim Eastwood - * Copyright (C) 2012 Variscite Ltd. - http://www.variscite.com - */ -#include "omap4460.dtsi" -#include "omap4-mcpdm.dtsi" - -/ { - model = "Variscite VAR-SOM-OM44"; - compatible = "variscite,var-som-om44", "ti,omap4460", "ti,omap4"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x40000000>; /* 1 GB */ - }; - - sound: sound { - compatible = "ti,abe-twl6040"; - ti,model = "VAR-SOM-OM44"; - - ti,mclk-freq = <38400000>; - ti,mcpdm = <&mcpdm>; - ti,twl6040 = <&twl6040>; - - /* Audio routing */ - ti,audio-routing = - "Headset Stereophone", "HSOL", - "Headset Stereophone", "HSOR", - "AFML", "Line In", - "AFMR", "Line In"; - }; - - /* HS USB Host PHY on PORT 1 */ - hsusb1_phy: hsusb1_phy { - compatible = "usb-nop-xceiv"; - pinctrl-names = "default"; - pinctrl-0 = < - &hsusbb1_phy_clk_pins - &hsusbb1_phy_rst_pins - >; - - reset-gpios = <&gpio6 17 GPIO_ACTIVE_LOW>; /* gpio 177 */ - vcc-supply = <&vbat>; - #phy-cells = <0>; - - clocks = <&auxclk3_ck>; - clock-names = "main_clk"; - clock-frequency = <19200000>; - }; - - vbat: fixedregulator-vbat { - compatible = "regulator-fixed"; - regulator-name = "VBAT"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; -}; - -&omap4_pmx_core { - pinctrl-names = "default"; - pinctrl-0 = < - &hsusbb1_pins - >; - - twl6040_pins: pinmux_twl6040_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x19c, PIN_OUTPUT | MUX_MODE3) /* fref_clk2_out.gpio_182 */ - OMAP4_IOPAD(0x1a0, PIN_INPUT | MUX_MODE0) /* sys_nirq2.sys_nirq2 */ - >; - }; - - tsc2004_pins: pinmux_tsc2004_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x090, PIN_INPUT | MUX_MODE3) /* gpmc_ncs4.gpio_101 (irq) */ - OMAP4_IOPAD(0x092, PIN_OUTPUT | MUX_MODE3) /* gpmc_ncs5.gpio_102 (rst) */ - >; - }; - - uart3_pins: pinmux_uart3_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x140, PIN_INPUT_PULLUP | MUX_MODE0) /* uart3_cts_rctx.uart3_cts_rctx */ - OMAP4_IOPAD(0x142, PIN_OUTPUT | MUX_MODE0) /* uart3_rts_sd.uart3_rts_sd */ - OMAP4_IOPAD(0x144, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ - OMAP4_IOPAD(0x146, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ - >; - }; - - hsusbb1_pins: pinmux_hsusbb1_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x0c2, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_clk.usbb1_ulpiphy_clk */ - OMAP4_IOPAD(0x0c4, PIN_OUTPUT | MUX_MODE4) /* usbb1_ulpitll_stp.usbb1_ulpiphy_stp */ - OMAP4_IOPAD(0x0c6, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dir.usbb1_ulpiphy_dir */ - OMAP4_IOPAD(0x0c8, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_nxt.usbb1_ulpiphy_nxt */ - OMAP4_IOPAD(0x0ca, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat0.usbb1_ulpiphy_dat0 */ - OMAP4_IOPAD(0x0cc, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat1.usbb1_ulpiphy_dat1 */ - OMAP4_IOPAD(0x0ce, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat2.usbb1_ulpiphy_dat2 */ - OMAP4_IOPAD(0x0d0, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat3.usbb1_ulpiphy_dat3 */ - OMAP4_IOPAD(0x0d2, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat4.usbb1_ulpiphy_dat4 */ - OMAP4_IOPAD(0x0d4, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat5.usbb1_ulpiphy_dat5 */ - OMAP4_IOPAD(0x0d6, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat6.usbb1_ulpiphy_dat6 */ - OMAP4_IOPAD(0x0d8, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat7.usbb1_ulpiphy_dat7 */ - >; - }; - - hsusbb1_phy_rst_pins: pinmux_hsusbb1_phy_rst_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x18c, PIN_OUTPUT | MUX_MODE3) /* kpd_row2.gpio_177 */ - >; - }; - - i2c1_pins: pinmux_i2c1_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x122, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */ - OMAP4_IOPAD(0x124, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */ - >; - }; - - i2c3_pins: pinmux_i2c3_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x12a, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl */ - OMAP4_IOPAD(0x12c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda */ - >; - }; - - mmc1_pins: pinmux_mmc1_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x0e2, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ - OMAP4_IOPAD(0x0e4, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ - OMAP4_IOPAD(0x0e6, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ - OMAP4_IOPAD(0x0e8, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ - OMAP4_IOPAD(0x0ea, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ - OMAP4_IOPAD(0x0ec, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ - >; - }; -}; - -&omap4_pmx_wkup { - pinctrl-names = "default"; - pinctrl-0 = < - &hsusbb1_hub_rst_pins - &lan7500_rst_pins - >; - - hsusbb1_phy_clk_pins: pinmux_hsusbb1_phy_clk_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x058, PIN_OUTPUT | MUX_MODE0) /* fref_clk3_out */ - >; - }; - - hsusbb1_hub_rst_pins: pinmux_hsusbb1_hub_rst_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x042, PIN_OUTPUT | MUX_MODE3) /* gpio_wk1 */ - >; - }; - - lan7500_rst_pins: pinmux_lan7500_rst_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x040, PIN_OUTPUT | MUX_MODE3) /* gpio_wk0 */ - >; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - status = "okay"; - - clock-frequency = <400000>; - - twl: twl@48 { - reg = <0x48>; - /* SPI = 0, IRQ# = 7, 4 = active high level-sensitive */ - interrupts = ; /* IRQ_SYS_1N cascaded to gic */ - }; - - twl6040: twl@4b { - compatible = "ti,twl6040"; - #clock-cells = <0>; - reg = <0x4b>; - - pinctrl-names = "default"; - pinctrl-0 = <&twl6040_pins>; - - /* SPI = 0, IRQ# = 119, 4 = active high level-sensitive */ - interrupts = ; /* IRQ_SYS_2N cascaded to gic */ - ti,audpwron-gpio = <&gpio6 22 GPIO_ACTIVE_HIGH>; /* gpio 182 */ - - vio-supply = <&v1v8>; - v2v1-supply = <&v2v1>; - enable-active-high; - }; -}; - -#include "twl6030.dtsi" -#include "twl6030_omap4.dtsi" - -&vusim { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; -}; - -&i2c2 { - status = "disabled"; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_pins>; - status = "okay"; - - clock-frequency = <400000>; - - touchscreen: tsc2004@48 { - compatible = "ti,tsc2004"; - reg = <0x48>; - pinctrl-names = "default"; - pinctrl-0 = <&tsc2004_pins>; - interrupt-parent = <&gpio4>; - interrupts = <5 IRQ_TYPE_LEVEL_LOW>; /* gpio 101 */ - status = "disabled"; - }; - - tmp105@49 { - compatible = "ti,tmp105"; - reg = <0x49>; - }; - - eeprom@50 { - compatible = "microchip,24c32", "atmel,24c32"; - reg = <0x50>; - }; -}; - -&i2c4 { - status = "disabled"; -}; - -&gpmc { - status = "disabled"; -}; - -&mcspi1 { - status = "disabled"; -}; - -&mcspi2 { - status = "disabled"; -}; - -&mcspi3 { - status = "disabled"; -}; - -&mcspi4 { - status = "disabled"; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - vmmc-supply = <&vmmc>; - bus-width = <4>; - ti,non-removable; - status = "okay"; -}; - -&mmc2 { - status = "disabled"; -}; - -&mmc3 { - status = "disabled"; -}; - -&mmc4 { - status = "disabled"; -}; - -&mmc5 { - status = "disabled"; -}; - -&uart1 { - status = "disabled"; -}; - -&uart2 { - status = "disabled"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; - status = "okay"; -}; - -&uart4 { - status = "disabled"; -}; - -&keypad { - status = "disabled"; -}; - -&twl_usb_comparator { - usb-supply = <&vusb>; -}; - -&usb_otg_hs { - interface-type = <1>; - mode = <3>; - power = <50>; -}; - -&usbhshost { - port1-mode = "ehci-phy"; -}; - -&usbhsehci { - phys = <&hsusb1_phy>; -}; diff --git a/sys/gnu/dts/arm/omap4-var-stk-om44.dts b/sys/gnu/dts/arm/omap4-var-stk-om44.dts deleted file mode 100644 index 656fb29c2a1..00000000000 --- a/sys/gnu/dts/arm/omap4-var-stk-om44.dts +++ /dev/null @@ -1,14 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 Joachim Eastwood - */ -/dts-v1/; - -#include "omap4-var-som-om44.dtsi" -#include "omap4-var-som-om44-wlan.dtsi" -#include "omap4-var-om44customboard.dtsi" - -/ { - model = "Variscite VAR-STK-OM44"; - compatible = "variscite,var-stk-om44", "variscite,var-som-om44", "ti,omap4460", "ti,omap4"; -}; diff --git a/sys/gnu/dts/arm/omap4.dtsi b/sys/gnu/dts/arm/omap4.dtsi deleted file mode 100644 index 7cc95bc1598..00000000000 --- a/sys/gnu/dts/arm/omap4.dtsi +++ /dev/null @@ -1,444 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ - */ - -#include -#include -#include -#include -#include -#include - -/ { - compatible = "ti,omap4430", "ti,omap4"; - interrupt-parent = <&wakeupgen>; - #address-cells = <1>; - #size-cells = <1>; - chosen { }; - - aliases { - i2c0 = &i2c1; - i2c1 = &i2c2; - i2c2 = &i2c3; - i2c3 = &i2c4; - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - serial3 = &uart4; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - next-level-cache = <&L2>; - reg = <0x0>; - - clocks = <&dpll_mpu_ck>; - clock-names = "cpu"; - - clock-latency = <300000>; /* From omap-cpufreq driver */ - }; - cpu@1 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - next-level-cache = <&L2>; - reg = <0x1>; - }; - }; - - /* - * Note that 4430 needs cross trigger interface (CTI) supported - * before we can configure the interrupts. This means sampling - * events are not supported for pmu. Note that 4460 does not use - * CTI, see also 4460.dtsi. - */ - pmu { - compatible = "arm,cortex-a9-pmu"; - ti,hwmods = "debugss"; - }; - - gic: interrupt-controller@48241000 { - compatible = "arm,cortex-a9-gic"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0x48241000 0x1000>, - <0x48240100 0x0100>; - interrupt-parent = <&gic>; - }; - - L2: l2-cache-controller@48242000 { - compatible = "arm,pl310-cache"; - reg = <0x48242000 0x1000>; - cache-unified; - cache-level = <2>; - }; - - local-timer@48240600 { - compatible = "arm,cortex-a9-twd-timer"; - clocks = <&mpu_periphclk>; - reg = <0x48240600 0x20>; - interrupts = ; - interrupt-parent = <&gic>; - }; - - wakeupgen: interrupt-controller@48281000 { - compatible = "ti,omap4-wugen-mpu"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0x48281000 0x1000>; - interrupt-parent = <&gic>; - }; - - /* - * The soc node represents the soc top level view. It is used for IPs - * that are not memory mapped in the MPU view or for the MPU itself. - */ - soc { - compatible = "ti,omap-infra"; - mpu { - compatible = "ti,omap4-mpu"; - ti,hwmods = "mpu"; - sram = <&ocmcram>; - }; - - dsp { - compatible = "ti,omap3-c64"; - ti,hwmods = "dsp"; - }; - - iva { - compatible = "ti,ivahd"; - ti,hwmods = "iva"; - }; - }; - - /* - * XXX: Use a flat representation of the OMAP4 interconnect. - * The real OMAP interconnect network is quite complex. - * Since it will not bring real advantage to represent that in DT for - * the moment, just use a fake OCP bus entry to represent the whole bus - * hierarchy. - */ - ocp { - compatible = "ti,omap4-l3-noc", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3"; - reg = <0x44000000 0x1000>, - <0x44800000 0x2000>, - <0x45000000 0x1000>; - interrupts = , - ; - - l4_wkup: interconnect@4a300000 { - }; - - l4_cfg: interconnect@4a000000 { - }; - - l4_per: interconnect@48000000 { - }; - - l4_abe: interconnect@40100000 { - }; - - ocmcram: ocmcram@40304000 { - compatible = "mmio-sram"; - reg = <0x40304000 0xa000>; /* 40k */ - }; - - gpmc: gpmc@50000000 { - compatible = "ti,omap4430-gpmc"; - reg = <0x50000000 0x1000>; - #address-cells = <2>; - #size-cells = <1>; - interrupts = ; - dmas = <&sdma 4>; - dma-names = "rxtx"; - gpmc,num-cs = <8>; - gpmc,num-waitpins = <4>; - ti,hwmods = "gpmc"; - ti,no-idle-on-init; - clocks = <&l3_div_ck>; - clock-names = "fck"; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - }; - - mmu_dsp: mmu@4a066000 { - compatible = "ti,omap4-iommu"; - reg = <0x4a066000 0x100>; - interrupts = ; - ti,hwmods = "mmu_dsp"; - #iommu-cells = <0>; - }; - - target-module@52000000 { - compatible = "ti,sysc-omap4", "ti,sysc"; - ti,hwmods = "iss"; - reg = <0x52000000 0x4>, - <0x52000010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = ; - ti,sysc-midle = , - , - , - ; - ti,sysc-sidle = , - , - , - ; - ti,sysc-delay-us = <2>; - clocks = <&iss_clkctrl OMAP4_ISS_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x52000000 0x1000000>; - - /* No child device binding, driver in staging */ - }; - - mmu_ipu: mmu@55082000 { - compatible = "ti,omap4-iommu"; - reg = <0x55082000 0x100>; - interrupts = ; - ti,hwmods = "mmu_ipu"; - #iommu-cells = <0>; - ti,iommu-bus-err-back; - }; - target-module@4012c000 { - compatible = "ti,sysc-omap4", "ti,sysc"; - ti,hwmods = "slimbus1"; - reg = <0x4012c000 0x4>, - <0x4012c010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - , - ; - clocks = <&abe_clkctrl OMAP4_SLIMBUS1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x4012c000 0x1000>, /* MPU */ - <0x4902c000 0x4902c000 0x1000>; /* L3 */ - - /* No child device binding or driver in mainline */ - }; - - dmm@4e000000 { - compatible = "ti,omap4-dmm"; - reg = <0x4e000000 0x800>; - interrupts = <0 113 0x4>; - ti,hwmods = "dmm"; - }; - - emif1: emif@4c000000 { - compatible = "ti,emif-4d"; - reg = <0x4c000000 0x100>; - interrupts = ; - ti,hwmods = "emif1"; - ti,no-idle-on-init; - phy-type = <1>; - hw-caps-read-idle-ctrl; - hw-caps-ll-interface; - hw-caps-temp-alert; - }; - - emif2: emif@4d000000 { - compatible = "ti,emif-4d"; - reg = <0x4d000000 0x100>; - interrupts = ; - ti,hwmods = "emif2"; - ti,no-idle-on-init; - phy-type = <1>; - hw-caps-read-idle-ctrl; - hw-caps-ll-interface; - hw-caps-temp-alert; - }; - - aes1: aes@4b501000 { - compatible = "ti,omap4-aes"; - ti,hwmods = "aes1"; - reg = <0x4b501000 0xa0>; - interrupts = ; - dmas = <&sdma 111>, <&sdma 110>; - dma-names = "tx", "rx"; - }; - - aes2: aes@4b701000 { - compatible = "ti,omap4-aes"; - ti,hwmods = "aes2"; - reg = <0x4b701000 0xa0>; - interrupts = ; - dmas = <&sdma 114>, <&sdma 113>; - dma-names = "tx", "rx"; - }; - - des: des@480a5000 { - compatible = "ti,omap4-des"; - ti,hwmods = "des"; - reg = <0x480a5000 0xa0>; - interrupts = ; - dmas = <&sdma 117>, <&sdma 116>; - dma-names = "tx", "rx"; - }; - - sham: sham@4b100000 { - compatible = "ti,omap4-sham"; - ti,hwmods = "sham"; - reg = <0x4b100000 0x300>; - interrupts = ; - dmas = <&sdma 119>; - dma-names = "rx"; - }; - - abb_mpu: regulator-abb-mpu { - compatible = "ti,abb-v2"; - regulator-name = "abb_mpu"; - #address-cells = <0>; - #size-cells = <0>; - ti,tranxdone-status-mask = <0x80>; - clocks = <&sys_clkin_ck>; - ti,settling-time = <50>; - ti,clock-cycles = <16>; - - status = "disabled"; - }; - - abb_iva: regulator-abb-iva { - compatible = "ti,abb-v2"; - regulator-name = "abb_iva"; - #address-cells = <0>; - #size-cells = <0>; - ti,tranxdone-status-mask = <0x80000000>; - clocks = <&sys_clkin_ck>; - ti,settling-time = <50>; - ti,clock-cycles = <16>; - - status = "disabled"; - }; - - target-module@56000000 { - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x5601fc00 0x4>, - <0x5601fc10 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-midle = , - , - , - ; - ti,sysc-sidle = , - , - , - ; - clocks = <&l3_gfx_clkctrl OMAP4_GPU_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x56000000 0x2000000>; - - /* - * Closed source PowerVR driver, no child device - * binding or driver in mainline - */ - }; - - dss: dss@58000000 { - compatible = "ti,omap4-dss"; - reg = <0x58000000 0x80>; - status = "disabled"; - ti,hwmods = "dss_core"; - clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - dispc@58001000 { - compatible = "ti,omap4-dispc"; - reg = <0x58001000 0x1000>; - interrupts = ; - ti,hwmods = "dss_dispc"; - clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>; - clock-names = "fck"; - }; - - rfbi: encoder@58002000 { - compatible = "ti,omap4-rfbi"; - reg = <0x58002000 0x1000>; - status = "disabled"; - ti,hwmods = "dss_rfbi"; - clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>, <&l3_div_ck>; - clock-names = "fck", "ick"; - }; - - venc: encoder@58003000 { - compatible = "ti,omap4-venc"; - reg = <0x58003000 0x1000>; - status = "disabled"; - ti,hwmods = "dss_venc"; - clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 11>; - clock-names = "fck"; - }; - - dsi1: encoder@58004000 { - compatible = "ti,omap4-dsi"; - reg = <0x58004000 0x200>, - <0x58004200 0x40>, - <0x58004300 0x20>; - reg-names = "proto", "phy", "pll"; - interrupts = ; - status = "disabled"; - ti,hwmods = "dss_dsi1"; - clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>, - <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>; - clock-names = "fck", "sys_clk"; - }; - - dsi2: encoder@58005000 { - compatible = "ti,omap4-dsi"; - reg = <0x58005000 0x200>, - <0x58005200 0x40>, - <0x58005300 0x20>; - reg-names = "proto", "phy", "pll"; - interrupts = ; - status = "disabled"; - ti,hwmods = "dss_dsi2"; - clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>, - <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>; - clock-names = "fck", "sys_clk"; - }; - - hdmi: encoder@58006000 { - compatible = "ti,omap4-hdmi"; - reg = <0x58006000 0x200>, - <0x58006200 0x100>, - <0x58006300 0x100>, - <0x58006400 0x1000>; - reg-names = "wp", "pll", "phy", "core"; - interrupts = ; - status = "disabled"; - ti,hwmods = "dss_hdmi"; - clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>, - <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>; - clock-names = "fck", "sys_clk"; - dmas = <&sdma 76>; - dma-names = "audio_tx"; - }; - }; - }; -}; - -#include "omap4-l4.dtsi" -#include "omap4-l4-abe.dtsi" -#include "omap44xx-clocks.dtsi" diff --git a/sys/gnu/dts/arm/omap443x-clocks.dtsi b/sys/gnu/dts/arm/omap443x-clocks.dtsi deleted file mode 100644 index 39297868ec8..00000000000 --- a/sys/gnu/dts/arm/omap443x-clocks.dtsi +++ /dev/null @@ -1,15 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Device Tree Source for OMAP4 clock data - * - * Copyright (C) 2013 Texas Instruments, Inc. - */ -&prm_clocks { - bandgap_fclk: bandgap_fclk@1888 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_32k_ck>; - ti,bit-shift = <8>; - reg = <0x1888>; - }; -}; diff --git a/sys/gnu/dts/arm/omap443x.dtsi b/sys/gnu/dts/arm/omap443x.dtsi deleted file mode 100644 index cbcdcb4e7d1..00000000000 --- a/sys/gnu/dts/arm/omap443x.dtsi +++ /dev/null @@ -1,76 +0,0 @@ -/* - * Device Tree Source for OMAP443x SoC - * - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -#include "omap4.dtsi" - -/ { - cpus { - cpu0: cpu@0 { - /* OMAP443x variants OPP50-OPPNT */ - operating-points = < - /* kHz uV */ - 300000 1025000 - 600000 1200000 - 800000 1313000 - 1008000 1375000 - >; - clock-latency = <300000>; /* From legacy driver */ - - /* cooling options */ - #cooling-cells = <2>; /* min followed by max */ - }; - }; - - thermal-zones { - #include "omap4-cpu-thermal.dtsi" - }; - - ocp { - bandgap: bandgap@4a002260 { - reg = <0x4a002260 0x4 - 0x4a00232C 0x4>; - compatible = "ti,omap4430-bandgap"; - - #thermal-sensor-cells = <0>; - }; - }; - - ocp { - abb_mpu: regulator-abb-mpu { - status = "okay"; - - reg = <0x4a307bd0 0x8>, <0x4a306014 0x4>; - reg-names = "base-address", "int-address"; - - ti,abb_info = < - /*uV ABB efuse rbb_m fbb_m vset_m*/ - 1025000 0 0 0 0 0 - 1200000 0 0 0 0 0 - 1313000 0 0 0 0 0 - 1375000 1 0 0 0 0 - 1389000 1 0 0 0 0 - >; - }; - - /* Default unused, just provide register info for record */ - abb_iva: regulator-abb-iva { - reg = <0x4a307bd8 0x8>, <0x4a306010 0x4>; - reg-names = "base-address", "int-address"; - }; - - }; - -}; - -&cpu_thermal { - coefficients = <0 20000>; -}; - -/include/ "omap443x-clocks.dtsi" diff --git a/sys/gnu/dts/arm/omap4460.dtsi b/sys/gnu/dts/arm/omap4460.dtsi deleted file mode 100644 index 2223dc0d63c..00000000000 --- a/sys/gnu/dts/arm/omap4460.dtsi +++ /dev/null @@ -1,131 +0,0 @@ -/* - * Device Tree Source for OMAP4460 SoC - * - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ -#include "omap4.dtsi" - -/ { - cpus { - /* OMAP446x 'standard device' variants OPP50 to OPPTurbo */ - cpu0: cpu@0 { - operating-points = < - /* kHz uV */ - 350000 1025000 - 700000 1200000 - 920000 1313000 - >; - clock-latency = <300000>; /* From legacy driver */ - - /* cooling options */ - #cooling-cells = <2>; /* min followed by max */ - }; - }; - - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts = , - ; - ti,hwmods = "debugss"; - }; - - thermal-zones { - #include "omap4-cpu-thermal.dtsi" - }; - - ocp { - bandgap: bandgap@4a002260 { - reg = <0x4a002260 0x4 - 0x4a00232C 0x4 - 0x4a002378 0x18>; - compatible = "ti,omap4460-bandgap"; - interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>; /* talert */ - gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; /* tshut */ - - #thermal-sensor-cells = <0>; - }; - - abb_mpu: regulator-abb-mpu { - status = "okay"; - - reg = <0x4a307bd0 0x8>, <0x4a306014 0x4>, - <0x4A002268 0x4>; - reg-names = "base-address", "int-address", - "efuse-address"; - - ti,abb_info = < - /*uV ABB efuse rbb_m fbb_m vset_m*/ - 1025000 0 0 0 0 0 - 1200000 0 0 0 0 0 - 1313000 0 0 0x100000 0x40000 0 - 1375000 1 0 0 0 0 - 1389000 1 0 0 0 0 - >; - }; - - abb_iva: regulator-abb-iva { - status = "okay"; - - reg = <0x4a307bd8 0x8>, <0x4a306010 0x4>, - <0x4A002268 0x4>; - reg-names = "base-address", "int-address", - "efuse-address"; - - ti,abb_info = < - /*uV ABB efuse rbb_m fbb_m vset_m*/ - 950000 0 0 0 0 0 - 1140000 0 0 0 0 0 - 1291000 0 0 0x200000 0 0 - 1375000 1 0 0 0 0 - 1376000 1 0 0 0 0 - >; - }; - }; - -}; - -&cpu_thermal { - coefficients = <348 (-9301)>; -}; - -/* Only some L4 CFG interconnect ranges are different on 4460 */ -&l4_cfg_segment_300000 { - ranges = <0x00000000 0x00300000 0x020000>, /* ap 67 */ - <0x00040000 0x00340000 0x001000>, /* ap 68 */ - <0x00020000 0x00320000 0x004000>, /* ap 71 */ - <0x00024000 0x00324000 0x002000>, /* ap 72 */ - <0x00026000 0x00326000 0x001000>, /* ap 73 */ - <0x00027000 0x00327000 0x001000>, /* ap 74 */ - <0x00028000 0x00328000 0x001000>, /* ap 75 */ - <0x00029000 0x00329000 0x001000>, /* ap 76 */ - <0x00030000 0x00330000 0x010000>, /* ap 77 */ - <0x0002a000 0x0032a000 0x002000>, /* ap 90 */ - <0x0002c000 0x0032c000 0x004000>, /* ap 91 */ - <0x00010000 0x00310000 0x008000>, /* ap 92 */ - <0x00018000 0x00318000 0x004000>, /* ap 93 */ - <0x0001c000 0x0031c000 0x002000>, /* ap 94 */ - <0x0001e000 0x0031e000 0x002000>; /* ap 95 */ -}; - -&l4_cfg_target_0 { - ranges = <0x00000000 0x00000000 0x00010000>, - <0x00010000 0x00010000 0x00008000>, - <0x00018000 0x00018000 0x00004000>, - <0x0001c000 0x0001c000 0x00002000>, - <0x0001e000 0x0001e000 0x00002000>, - <0x00020000 0x00020000 0x00004000>, - <0x00024000 0x00024000 0x00002000>, - <0x00026000 0x00026000 0x00001000>, - <0x00027000 0x00027000 0x00001000>, - <0x00028000 0x00028000 0x00001000>, - <0x00029000 0x00029000 0x00001000>, - <0x0002a000 0x0002a000 0x00002000>, - <0x0002c000 0x0002c000 0x00004000>, - <0x00030000 0x00030000 0x00010000>; -}; - -/include/ "omap446x-clocks.dtsi" diff --git a/sys/gnu/dts/arm/omap446x-clocks.dtsi b/sys/gnu/dts/arm/omap446x-clocks.dtsi deleted file mode 100644 index 0f41714cffb..00000000000 --- a/sys/gnu/dts/arm/omap446x-clocks.dtsi +++ /dev/null @@ -1,24 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Device Tree Source for OMAP4 clock data - * - * Copyright (C) 2013 Texas Instruments, Inc. - */ -&prm_clocks { - div_ts_ck: div_ts_ck@1888 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&l4_wkup_clk_mux_ck>; - ti,bit-shift = <24>; - reg = <0x1888>; - ti,dividers = <8>, <16>, <32>; - }; - - bandgap_ts_fclk: bandgap_ts_fclk@1888 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&div_ts_ck>; - ti,bit-shift = <8>; - reg = <0x1888>; - }; -}; diff --git a/sys/gnu/dts/arm/omap44xx-clocks.dtsi b/sys/gnu/dts/arm/omap44xx-clocks.dtsi deleted file mode 100644 index e9d9c846068..00000000000 --- a/sys/gnu/dts/arm/omap44xx-clocks.dtsi +++ /dev/null @@ -1,1319 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Device Tree Source for OMAP4 clock data - * - * Copyright (C) 2013 Texas Instruments, Inc. - */ -&cm1_clocks { - extalt_clkin_ck: extalt_clkin_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <59000000>; - }; - - pad_clks_src_ck: pad_clks_src_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <12000000>; - }; - - pad_clks_ck: pad_clks_ck@108 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&pad_clks_src_ck>; - ti,bit-shift = <8>; - reg = <0x0108>; - }; - - pad_slimbus_core_clks_ck: pad_slimbus_core_clks_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <12000000>; - }; - - secure_32k_clk_src_ck: secure_32k_clk_src_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - slimbus_src_clk: slimbus_src_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <12000000>; - }; - - slimbus_clk: slimbus_clk@108 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&slimbus_src_clk>; - ti,bit-shift = <10>; - reg = <0x0108>; - }; - - sys_32k_ck: sys_32k_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - virt_12000000_ck: virt_12000000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <12000000>; - }; - - virt_13000000_ck: virt_13000000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <13000000>; - }; - - virt_16800000_ck: virt_16800000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <16800000>; - }; - - virt_19200000_ck: virt_19200000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <19200000>; - }; - - virt_26000000_ck: virt_26000000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <26000000>; - }; - - virt_27000000_ck: virt_27000000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <27000000>; - }; - - virt_38400000_ck: virt_38400000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <38400000>; - }; - - tie_low_clock_ck: tie_low_clock_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - utmi_phy_clkout_ck: utmi_phy_clkout_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <60000000>; - }; - - xclk60mhsp1_ck: xclk60mhsp1_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <60000000>; - }; - - xclk60mhsp2_ck: xclk60mhsp2_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <60000000>; - }; - - xclk60motg_ck: xclk60motg_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <60000000>; - }; - - dpll_abe_ck: dpll_abe_ck@1e0 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-m4xen-clock"; - clocks = <&abe_dpll_refclk_mux_ck>, <&abe_dpll_bypass_clk_mux_ck>; - reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>; - }; - - dpll_abe_x2_ck: dpll_abe_x2_ck@1f0 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-x2-clock"; - clocks = <&dpll_abe_ck>; - reg = <0x01f0>; - }; - - dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@1f0 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_abe_x2_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x01f0>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - abe_24m_fclk: abe_24m_fclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_abe_m2x2_ck>; - clock-mult = <1>; - clock-div = <8>; - }; - - abe_clk: abe_clk@108 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_abe_m2x2_ck>; - ti,max-div = <4>; - reg = <0x0108>; - ti,index-power-of-two; - }; - - - dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_abe_x2_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x01f4>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - core_hsd_byp_clk_mux_ck: core_hsd_byp_clk_mux_ck@12c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin_ck>, <&dpll_abe_m3x2_ck>; - ti,bit-shift = <23>; - reg = <0x012c>; - }; - - dpll_core_ck: dpll_core_ck@120 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-core-clock"; - clocks = <&sys_clkin_ck>, <&core_hsd_byp_clk_mux_ck>; - reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>; - }; - - dpll_core_x2_ck: dpll_core_x2_ck { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-x2-clock"; - clocks = <&dpll_core_ck>; - }; - - dpll_core_m6x2_ck: dpll_core_m6x2_ck@140 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x0140>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_core_m2_ck: dpll_core_m2_ck@130 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_core_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x0130>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - ddrphy_ck: ddrphy_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_core_m2_ck>; - clock-mult = <1>; - clock-div = <2>; - }; - - dpll_core_m5x2_ck: dpll_core_m5x2_ck@13c { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x013c>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - div_core_ck: div_core_ck@100 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_core_m5x2_ck>; - reg = <0x0100>; - ti,max-div = <2>; - }; - - div_iva_hs_clk: div_iva_hs_clk@1dc { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_core_m5x2_ck>; - ti,max-div = <4>; - reg = <0x01dc>; - ti,index-power-of-two; - }; - - div_mpu_hs_clk: div_mpu_hs_clk@19c { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_core_m5x2_ck>; - ti,max-div = <4>; - reg = <0x019c>; - ti,index-power-of-two; - }; - - dpll_core_m4x2_ck: dpll_core_m4x2_ck@138 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x0138>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dll_clk_div_ck: dll_clk_div_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_core_m4x2_ck>; - clock-mult = <1>; - clock-div = <2>; - }; - - dpll_abe_m2_ck: dpll_abe_m2_ck@1f0 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_abe_ck>; - ti,max-div = <31>; - reg = <0x01f0>; - ti,index-starts-at-one; - }; - - dpll_core_m3x2_gate_ck: dpll_core_m3x2_gate_ck@134 { - #clock-cells = <0>; - compatible = "ti,composite-no-wait-gate-clock"; - clocks = <&dpll_core_x2_ck>; - ti,bit-shift = <8>; - reg = <0x0134>; - }; - - dpll_core_m3x2_div_ck: dpll_core_m3x2_div_ck@134 { - #clock-cells = <0>; - compatible = "ti,composite-divider-clock"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <31>; - reg = <0x0134>; - ti,index-starts-at-one; - }; - - dpll_core_m3x2_ck: dpll_core_m3x2_ck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&dpll_core_m3x2_gate_ck>, <&dpll_core_m3x2_div_ck>; - }; - - dpll_core_m7x2_ck: dpll_core_m7x2_ck@144 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x0144>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - iva_hsd_byp_clk_mux_ck: iva_hsd_byp_clk_mux_ck@1ac { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin_ck>, <&div_iva_hs_clk>; - ti,bit-shift = <23>; - reg = <0x01ac>; - }; - - dpll_iva_ck: dpll_iva_ck@1a0 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-clock"; - clocks = <&sys_clkin_ck>, <&iva_hsd_byp_clk_mux_ck>; - reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>; - assigned-clocks = <&dpll_iva_ck>; - assigned-clock-rates = <931200000>; - }; - - dpll_iva_x2_ck: dpll_iva_x2_ck { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-x2-clock"; - clocks = <&dpll_iva_ck>; - }; - - dpll_iva_m4x2_ck: dpll_iva_m4x2_ck@1b8 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_iva_x2_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x01b8>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - assigned-clocks = <&dpll_iva_m4x2_ck>; - assigned-clock-rates = <465600000>; - }; - - dpll_iva_m5x2_ck: dpll_iva_m5x2_ck@1bc { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_iva_x2_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x01bc>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - assigned-clocks = <&dpll_iva_m5x2_ck>; - assigned-clock-rates = <266100000>; - }; - - dpll_mpu_ck: dpll_mpu_ck@160 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-clock"; - clocks = <&sys_clkin_ck>, <&div_mpu_hs_clk>; - reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>; - }; - - dpll_mpu_m2_ck: dpll_mpu_m2_ck@170 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_mpu_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x0170>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - per_hs_clk_div_ck: per_hs_clk_div_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_abe_m3x2_ck>; - clock-mult = <1>; - clock-div = <2>; - }; - - usb_hs_clk_div_ck: usb_hs_clk_div_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_abe_m3x2_ck>; - clock-mult = <1>; - clock-div = <3>; - }; - - l3_div_ck: l3_div_ck@100 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&div_core_ck>; - ti,bit-shift = <4>; - ti,max-div = <2>; - reg = <0x0100>; - }; - - l4_div_ck: l4_div_ck@100 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&l3_div_ck>; - ti,bit-shift = <8>; - ti,max-div = <2>; - reg = <0x0100>; - }; - - lp_clk_div_ck: lp_clk_div_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_abe_m2x2_ck>; - clock-mult = <1>; - clock-div = <16>; - }; - - mpu_periphclk: mpu_periphclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_mpu_ck>; - clock-mult = <1>; - clock-div = <2>; - }; - - ocp_abe_iclk: ocp_abe_iclk@528 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&abe_clkctrl OMAP4_AESS_CLKCTRL 24>; - ti,bit-shift = <24>; - reg = <0x0528>; - ti,dividers = <2>, <1>; - }; - - per_abe_24m_fclk: per_abe_24m_fclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_abe_m2_ck>; - clock-mult = <1>; - clock-div = <4>; - }; - - dummy_ck: dummy_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; -}; - -&prm_clocks { - sys_clkin_ck: sys_clkin_ck@110 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>; - reg = <0x0110>; - ti,index-starts-at-one; - }; - - abe_dpll_bypass_clk_mux_ck: abe_dpll_bypass_clk_mux_ck@108 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin_ck>, <&sys_32k_ck>; - ti,bit-shift = <24>; - reg = <0x0108>; - }; - - abe_dpll_refclk_mux_ck: abe_dpll_refclk_mux_ck@10c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin_ck>, <&sys_32k_ck>; - reg = <0x010c>; - }; - - dbgclk_mux_ck: dbgclk_mux_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&sys_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - l4_wkup_clk_mux_ck: l4_wkup_clk_mux_ck@108 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin_ck>, <&lp_clk_div_ck>; - reg = <0x0108>; - }; - - syc_clk_div_ck: syc_clk_div_ck@100 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&sys_clkin_ck>; - reg = <0x0100>; - ti,max-div = <2>; - }; - - usim_ck: usim_ck@1858 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_per_m4x2_ck>; - ti,bit-shift = <24>; - reg = <0x1858>; - ti,dividers = <14>, <18>; - }; - - usim_fclk: usim_fclk@1858 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&usim_ck>; - ti,bit-shift = <8>; - reg = <0x1858>; - }; - - trace_clk_div_ck: trace_clk_div_ck { - #clock-cells = <0>; - compatible = "ti,clkdm-gate-clock"; - clocks = <&emu_sys_clkctrl OMAP4_DEBUGSS_CLKCTRL 24>; - }; -}; - -&prm_clockdomains { - emu_sys_clkdm: emu_sys_clkdm { - compatible = "ti,clockdomain"; - clocks = <&trace_clk_div_ck>; - }; -}; - -&cm2_clocks { - per_hsd_byp_clk_mux_ck: per_hsd_byp_clk_mux_ck@14c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin_ck>, <&per_hs_clk_div_ck>; - ti,bit-shift = <23>; - reg = <0x014c>; - }; - - dpll_per_ck: dpll_per_ck@140 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-clock"; - clocks = <&sys_clkin_ck>, <&per_hsd_byp_clk_mux_ck>; - reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>; - }; - - dpll_per_m2_ck: dpll_per_m2_ck@150 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_per_ck>; - ti,max-div = <31>; - reg = <0x0150>; - ti,index-starts-at-one; - }; - - dpll_per_x2_ck: dpll_per_x2_ck@150 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-x2-clock"; - clocks = <&dpll_per_ck>; - reg = <0x0150>; - }; - - dpll_per_m2x2_ck: dpll_per_m2x2_ck@150 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_per_x2_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x0150>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_per_m3x2_gate_ck: dpll_per_m3x2_gate_ck@154 { - #clock-cells = <0>; - compatible = "ti,composite-no-wait-gate-clock"; - clocks = <&dpll_per_x2_ck>; - ti,bit-shift = <8>; - reg = <0x0154>; - }; - - dpll_per_m3x2_div_ck: dpll_per_m3x2_div_ck@154 { - #clock-cells = <0>; - compatible = "ti,composite-divider-clock"; - clocks = <&dpll_per_x2_ck>; - ti,max-div = <31>; - reg = <0x0154>; - ti,index-starts-at-one; - }; - - dpll_per_m3x2_ck: dpll_per_m3x2_ck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&dpll_per_m3x2_gate_ck>, <&dpll_per_m3x2_div_ck>; - }; - - dpll_per_m4x2_ck: dpll_per_m4x2_ck@158 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_per_x2_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x0158>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_per_m5x2_ck: dpll_per_m5x2_ck@15c { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_per_x2_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x015c>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_per_m6x2_ck: dpll_per_m6x2_ck@160 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_per_x2_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x0160>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_per_m7x2_ck: dpll_per_m7x2_ck@164 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_per_x2_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x0164>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_usb_ck: dpll_usb_ck@180 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-j-type-clock"; - clocks = <&sys_clkin_ck>, <&usb_hs_clk_div_ck>; - reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>; - }; - - dpll_usb_clkdcoldo_ck: dpll_usb_clkdcoldo_ck@1b4 { - #clock-cells = <0>; - compatible = "ti,fixed-factor-clock"; - clocks = <&dpll_usb_ck>; - ti,clock-div = <1>; - ti,autoidle-shift = <8>; - reg = <0x01b4>; - ti,clock-mult = <1>; - ti,invert-autoidle-bit; - }; - - dpll_usb_m2_ck: dpll_usb_m2_ck@190 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_usb_ck>; - ti,max-div = <127>; - ti,autoidle-shift = <8>; - reg = <0x0190>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - ducati_clk_mux_ck: ducati_clk_mux_ck@100 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&div_core_ck>, <&dpll_per_m6x2_ck>; - reg = <0x0100>; - }; - - func_12m_fclk: func_12m_fclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_per_m2x2_ck>; - clock-mult = <1>; - clock-div = <16>; - }; - - func_24m_clk: func_24m_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_per_m2_ck>; - clock-mult = <1>; - clock-div = <4>; - }; - - func_24mc_fclk: func_24mc_fclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_per_m2x2_ck>; - clock-mult = <1>; - clock-div = <8>; - }; - - func_48m_fclk: func_48m_fclk@108 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_per_m2x2_ck>; - reg = <0x0108>; - ti,dividers = <4>, <8>; - }; - - func_48mc_fclk: func_48mc_fclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_per_m2x2_ck>; - clock-mult = <1>; - clock-div = <4>; - }; - - func_64m_fclk: func_64m_fclk@108 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_per_m4x2_ck>; - reg = <0x0108>; - ti,dividers = <2>, <4>; - }; - - func_96m_fclk: func_96m_fclk@108 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_per_m2x2_ck>; - reg = <0x0108>; - ti,dividers = <2>, <4>; - }; - - init_60m_fclk: init_60m_fclk@104 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_usb_m2_ck>; - reg = <0x0104>; - ti,dividers = <1>, <8>; - }; - - per_abe_nc_fclk: per_abe_nc_fclk@108 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_abe_m2_ck>; - reg = <0x0108>; - ti,max-div = <2>; - }; - - sha2md5_fck: sha2md5_fck@15c8 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&l3_div_ck>; - ti,bit-shift = <1>; - reg = <0x15c8>; - }; - - usb_phy_cm_clk32k: usb_phy_cm_clk32k@640 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_32k_ck>; - ti,bit-shift = <8>; - reg = <0x0640>; - }; -}; - -&cm2_clockdomains { - l3_init_clkdm: l3_init_clkdm { - compatible = "ti,clockdomain"; - clocks = <&dpll_usb_ck>; - }; -}; - -&scrm_clocks { - auxclk0_src_gate_ck: auxclk0_src_gate_ck@310 { - #clock-cells = <0>; - compatible = "ti,composite-no-wait-gate-clock"; - clocks = <&dpll_core_m3x2_ck>; - ti,bit-shift = <8>; - reg = <0x0310>; - }; - - auxclk0_src_mux_ck: auxclk0_src_mux_ck@310 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; - ti,bit-shift = <1>; - reg = <0x0310>; - }; - - auxclk0_src_ck: auxclk0_src_ck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&auxclk0_src_gate_ck>, <&auxclk0_src_mux_ck>; - }; - - auxclk0_ck: auxclk0_ck@310 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&auxclk0_src_ck>; - ti,bit-shift = <16>; - ti,max-div = <16>; - reg = <0x0310>; - }; - - auxclk1_src_gate_ck: auxclk1_src_gate_ck@314 { - #clock-cells = <0>; - compatible = "ti,composite-no-wait-gate-clock"; - clocks = <&dpll_core_m3x2_ck>; - ti,bit-shift = <8>; - reg = <0x0314>; - }; - - auxclk1_src_mux_ck: auxclk1_src_mux_ck@314 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; - ti,bit-shift = <1>; - reg = <0x0314>; - }; - - auxclk1_src_ck: auxclk1_src_ck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&auxclk1_src_gate_ck>, <&auxclk1_src_mux_ck>; - }; - - auxclk1_ck: auxclk1_ck@314 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&auxclk1_src_ck>; - ti,bit-shift = <16>; - ti,max-div = <16>; - reg = <0x0314>; - }; - - auxclk2_src_gate_ck: auxclk2_src_gate_ck@318 { - #clock-cells = <0>; - compatible = "ti,composite-no-wait-gate-clock"; - clocks = <&dpll_core_m3x2_ck>; - ti,bit-shift = <8>; - reg = <0x0318>; - }; - - auxclk2_src_mux_ck: auxclk2_src_mux_ck@318 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; - ti,bit-shift = <1>; - reg = <0x0318>; - }; - - auxclk2_src_ck: auxclk2_src_ck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&auxclk2_src_gate_ck>, <&auxclk2_src_mux_ck>; - }; - - auxclk2_ck: auxclk2_ck@318 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&auxclk2_src_ck>; - ti,bit-shift = <16>; - ti,max-div = <16>; - reg = <0x0318>; - }; - - auxclk3_src_gate_ck: auxclk3_src_gate_ck@31c { - #clock-cells = <0>; - compatible = "ti,composite-no-wait-gate-clock"; - clocks = <&dpll_core_m3x2_ck>; - ti,bit-shift = <8>; - reg = <0x031c>; - }; - - auxclk3_src_mux_ck: auxclk3_src_mux_ck@31c { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; - ti,bit-shift = <1>; - reg = <0x031c>; - }; - - auxclk3_src_ck: auxclk3_src_ck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&auxclk3_src_gate_ck>, <&auxclk3_src_mux_ck>; - }; - - auxclk3_ck: auxclk3_ck@31c { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&auxclk3_src_ck>; - ti,bit-shift = <16>; - ti,max-div = <16>; - reg = <0x031c>; - }; - - auxclk4_src_gate_ck: auxclk4_src_gate_ck@320 { - #clock-cells = <0>; - compatible = "ti,composite-no-wait-gate-clock"; - clocks = <&dpll_core_m3x2_ck>; - ti,bit-shift = <8>; - reg = <0x0320>; - }; - - auxclk4_src_mux_ck: auxclk4_src_mux_ck@320 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; - ti,bit-shift = <1>; - reg = <0x0320>; - }; - - auxclk4_src_ck: auxclk4_src_ck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&auxclk4_src_gate_ck>, <&auxclk4_src_mux_ck>; - }; - - auxclk4_ck: auxclk4_ck@320 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&auxclk4_src_ck>; - ti,bit-shift = <16>; - ti,max-div = <16>; - reg = <0x0320>; - }; - - auxclk5_src_gate_ck: auxclk5_src_gate_ck@324 { - #clock-cells = <0>; - compatible = "ti,composite-no-wait-gate-clock"; - clocks = <&dpll_core_m3x2_ck>; - ti,bit-shift = <8>; - reg = <0x0324>; - }; - - auxclk5_src_mux_ck: auxclk5_src_mux_ck@324 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; - ti,bit-shift = <1>; - reg = <0x0324>; - }; - - auxclk5_src_ck: auxclk5_src_ck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&auxclk5_src_gate_ck>, <&auxclk5_src_mux_ck>; - }; - - auxclk5_ck: auxclk5_ck@324 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&auxclk5_src_ck>; - ti,bit-shift = <16>; - ti,max-div = <16>; - reg = <0x0324>; - }; - - auxclkreq0_ck: auxclkreq0_ck@210 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>; - ti,bit-shift = <2>; - reg = <0x0210>; - }; - - auxclkreq1_ck: auxclkreq1_ck@214 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>; - ti,bit-shift = <2>; - reg = <0x0214>; - }; - - auxclkreq2_ck: auxclkreq2_ck@218 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>; - ti,bit-shift = <2>; - reg = <0x0218>; - }; - - auxclkreq3_ck: auxclkreq3_ck@21c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>; - ti,bit-shift = <2>; - reg = <0x021c>; - }; - - auxclkreq4_ck: auxclkreq4_ck@220 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>; - ti,bit-shift = <2>; - reg = <0x0220>; - }; - - auxclkreq5_ck: auxclkreq5_ck@224 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>; - ti,bit-shift = <2>; - reg = <0x0224>; - }; -}; - -&cm1 { - mpuss_cm: mpuss_cm@300 { - compatible = "ti,omap4-cm"; - reg = <0x300 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x300 0x100>; - - mpuss_clkctrl: clk@20 { - compatible = "ti,clkctrl"; - reg = <0x20 0x4>; - #clock-cells = <2>; - }; - }; - - tesla_cm: tesla_cm@400 { - compatible = "ti,omap4-cm"; - reg = <0x400 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x400 0x100>; - - tesla_clkctrl: clk@20 { - compatible = "ti,clkctrl"; - reg = <0x20 0x4>; - #clock-cells = <2>; - }; - }; - - abe_cm: abe_cm@500 { - compatible = "ti,omap4-cm"; - reg = <0x500 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x500 0x100>; - - abe_clkctrl: clk@20 { - compatible = "ti,clkctrl"; - reg = <0x20 0x6c>; - #clock-cells = <2>; - }; - }; - -}; - -&cm2 { - l4_ao_cm: l4_ao_cm@600 { - compatible = "ti,omap4-cm"; - reg = <0x600 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x600 0x100>; - - l4_ao_clkctrl: clk@20 { - compatible = "ti,clkctrl"; - reg = <0x20 0x1c>; - #clock-cells = <2>; - }; - }; - - l3_1_cm: l3_1_cm@700 { - compatible = "ti,omap4-cm"; - reg = <0x700 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x700 0x100>; - - l3_1_clkctrl: clk@20 { - compatible = "ti,clkctrl"; - reg = <0x20 0x4>; - #clock-cells = <2>; - }; - }; - - l3_2_cm: l3_2_cm@800 { - compatible = "ti,omap4-cm"; - reg = <0x800 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x800 0x100>; - - l3_2_clkctrl: clk@20 { - compatible = "ti,clkctrl"; - reg = <0x20 0x14>; - #clock-cells = <2>; - }; - }; - - ducati_cm: ducati_cm@900 { - compatible = "ti,omap4-cm"; - reg = <0x900 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x900 0x100>; - - ducati_clkctrl: clk@20 { - compatible = "ti,clkctrl"; - reg = <0x20 0x4>; - #clock-cells = <2>; - }; - }; - - l3_dma_cm: l3_dma_cm@a00 { - compatible = "ti,omap4-cm"; - reg = <0xa00 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0xa00 0x100>; - - l3_dma_clkctrl: clk@20 { - compatible = "ti,clkctrl"; - reg = <0x20 0x4>; - #clock-cells = <2>; - }; - }; - - l3_emif_cm: l3_emif_cm@b00 { - compatible = "ti,omap4-cm"; - reg = <0xb00 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0xb00 0x100>; - - l3_emif_clkctrl: clk@20 { - compatible = "ti,clkctrl"; - reg = <0x20 0x1c>; - #clock-cells = <2>; - }; - }; - - d2d_cm: d2d_cm@c00 { - compatible = "ti,omap4-cm"; - reg = <0xc00 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0xc00 0x100>; - - d2d_clkctrl: clk@20 { - compatible = "ti,clkctrl"; - reg = <0x20 0x4>; - #clock-cells = <2>; - }; - }; - - l4_cfg_cm: l4_cfg_cm@d00 { - compatible = "ti,omap4-cm"; - reg = <0xd00 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0xd00 0x100>; - - l4_cfg_clkctrl: clk@20 { - compatible = "ti,clkctrl"; - reg = <0x20 0x14>; - #clock-cells = <2>; - }; - }; - - l3_instr_cm: l3_instr_cm@e00 { - compatible = "ti,omap4-cm"; - reg = <0xe00 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0xe00 0x100>; - - l3_instr_clkctrl: clk@20 { - compatible = "ti,clkctrl"; - reg = <0x20 0x24>; - #clock-cells = <2>; - }; - }; - - ivahd_cm: ivahd_cm@f00 { - compatible = "ti,omap4-cm"; - reg = <0xf00 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0xf00 0x100>; - - ivahd_clkctrl: clk@20 { - compatible = "ti,clkctrl"; - reg = <0x20 0xc>; - #clock-cells = <2>; - }; - }; - - iss_cm: iss_cm@1000 { - compatible = "ti,omap4-cm"; - reg = <0x1000 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1000 0x100>; - - iss_clkctrl: clk@20 { - compatible = "ti,clkctrl"; - reg = <0x20 0xc>; - #clock-cells = <2>; - }; - }; - - l3_dss_cm: l3_dss_cm@1100 { - compatible = "ti,omap4-cm"; - reg = <0x1100 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1100 0x100>; - - l3_dss_clkctrl: clk@20 { - compatible = "ti,clkctrl"; - reg = <0x20 0x4>; - #clock-cells = <2>; - }; - }; - - l3_gfx_cm: l3_gfx_cm@1200 { - compatible = "ti,omap4-cm"; - reg = <0x1200 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1200 0x100>; - - l3_gfx_clkctrl: clk@20 { - compatible = "ti,clkctrl"; - reg = <0x20 0x4>; - #clock-cells = <2>; - }; - }; - - l3_init_cm: l3_init_cm@1300 { - compatible = "ti,omap4-cm"; - reg = <0x1300 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1300 0x100>; - - l3_init_clkctrl: clk@20 { - compatible = "ti,clkctrl"; - reg = <0x20 0xc4>; - #clock-cells = <2>; - }; - }; - - l4_per_cm: l4_per_cm@1400 { - compatible = "ti,omap4-cm"; - reg = <0x1400 0x200>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1400 0x200>; - - l4_per_clkctrl: clk@20 { - compatible = "ti,clkctrl"; - reg = <0x20 0x144>; - #clock-cells = <2>; - }; - }; - -}; - -&prm { - l4_wkup_cm: l4_wkup_cm@1800 { - compatible = "ti,omap4-cm"; - reg = <0x1800 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1800 0x100>; - - l4_wkup_clkctrl: clk@20 { - compatible = "ti,clkctrl"; - reg = <0x20 0x5c>; - #clock-cells = <2>; - }; - }; - - emu_sys_cm: emu_sys_cm@1a00 { - compatible = "ti,omap4-cm"; - reg = <0x1a00 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1a00 0x100>; - - emu_sys_clkctrl: clk@20 { - compatible = "ti,clkctrl"; - reg = <0x20 0x4>; - #clock-cells = <2>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/omap5-board-common.dtsi b/sys/gnu/dts/arm/omap5-board-common.dtsi deleted file mode 100644 index 68ac04641bd..00000000000 --- a/sys/gnu/dts/arm/omap5-board-common.dtsi +++ /dev/null @@ -1,762 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ - */ -#include "omap5.dtsi" -#include -#include - -/ { - aliases { - display0 = &hdmi0; - }; - - chosen { - stdout-path = &uart3; - }; - - vmain: fixedregulator-vmain { - compatible = "regulator-fixed"; - regulator-name = "vmain"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - vsys_cobra: fixedregulator-vsys_cobra { - compatible = "regulator-fixed"; - regulator-name = "vsys_cobra"; - vin-supply = <&vmain>; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - vdds_1v8_main: fixedregulator-vdds_1v8_main { - compatible = "regulator-fixed"; - regulator-name = "vdds_1v8_main"; - vin-supply = <&smps7_reg>; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vmmcsd_fixed: fixedregulator-mmcsd { - compatible = "regulator-fixed"; - regulator-name = "vmmcsd_fixed"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - mmc3_pwrseq: sdhci0_pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&clk32kgaudio>; - clock-names = "ext_clock"; - }; - - vmmcsdio_fixed: fixedregulator-mmcsdio { - compatible = "regulator-fixed"; - regulator-name = "vmmcsdio_fixed"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio5 12 GPIO_ACTIVE_HIGH>; /* gpio140 WLAN_EN */ - enable-active-high; - startup-delay-us = <70000>; - pinctrl-names = "default"; - pinctrl-0 = <&wlan_pins>; - }; - - /* HS USB Host PHY on PORT 2 */ - hsusb2_phy: hsusb2_phy { - compatible = "usb-nop-xceiv"; - reset-gpios = <&gpio3 16 GPIO_ACTIVE_LOW>; /* gpio3_80 HUB_NRESET */ - clocks = <&auxclk1_ck>; - clock-names = "main_clk"; - clock-frequency = <19200000>; - #phy-cells = <0>; - }; - - /* HS USB Host PHY on PORT 3 */ - hsusb3_phy: hsusb3_phy { - compatible = "usb-nop-xceiv"; - reset-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>; /* gpio3_79 ETH_NRESET */ - #phy-cells = <0>; - }; - - tpd12s015: encoder { - compatible = "ti,tpd12s015"; - - pinctrl-names = "default"; - pinctrl-0 = <&tpd12s015_pins>; - - /* gpios defined in the board specific dts */ - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - tpd12s015_in: endpoint { - remote-endpoint = <&hdmi_out>; - }; - }; - - port@1 { - reg = <1>; - - tpd12s015_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; - }; - }; - }; - - hdmi0: connector { - compatible = "hdmi-connector"; - label = "hdmi"; - - type = "b"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&tpd12s015_out>; - }; - }; - }; - - sound: sound { - compatible = "ti,abe-twl6040"; - ti,model = "omap5-uevm"; - - ti,jack-detection; - ti,mclk-freq = <19200000>; - - ti,mcpdm = <&mcpdm>; - - ti,twl6040 = <&twl6040>; - - /* Audio routing */ - ti,audio-routing = - "Headset Stereophone", "HSOL", - "Headset Stereophone", "HSOR", - "Line Out", "AUXL", - "Line Out", "AUXR", - "HSMIC", "Headset Mic", - "Headset Mic", "Headset Mic Bias", - "AFML", "Line In", - "AFMR", "Line In"; - }; -}; - -&gpio8 { - /* TI trees use GPIO instead of msecure, see also muxing */ - p234 { - gpio-hog; - gpios = <10 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "gpio8_234/msecure"; - }; -}; - -&omap5_pmx_core { - pinctrl-names = "default"; - pinctrl-0 = < - &usbhost_pins - &led_gpio_pins - >; - - twl6040_pins: pinmux_twl6040_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x1be, PIN_OUTPUT | MUX_MODE6) /* mcspi1_somi.gpio5_141 */ - >; - }; - - mcpdm_pins: pinmux_mcpdm_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x182, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_clks.abe_clks */ - OMAP5_IOPAD(0x19c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abemcpdm_ul_data.abemcpdm_ul_data */ - OMAP5_IOPAD(0x19e, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abemcpdm_dl_data.abemcpdm_dl_data */ - OMAP5_IOPAD(0x1a0, PIN_INPUT_PULLUP | MUX_MODE0) /* abemcpdm_frame.abemcpdm_frame */ - OMAP5_IOPAD(0x1a2, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abemcpdm_lb_clk.abemcpdm_lb_clk */ - >; - }; - - mcbsp1_pins: pinmux_mcbsp1_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x18c, PIN_INPUT | MUX_MODE1) /* abedmic_clk2.abemcbsp1_fsx */ - OMAP5_IOPAD(0x18e, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* abedmic_clk3.abemcbsp1_dx */ - OMAP5_IOPAD(0x190, PIN_INPUT | MUX_MODE1) /* abeslimbus1_clock.abemcbsp1_clkx */ - OMAP5_IOPAD(0x192, PIN_INPUT_PULLDOWN | MUX_MODE1) /* abeslimbus1_data.abemcbsp1_dr */ - >; - }; - - mcbsp2_pins: pinmux_mcbsp2_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x194, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abemcbsp2_dr.abemcbsp2_dr */ - OMAP5_IOPAD(0x196, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* abemcbsp2_dx.abemcbsp2_dx */ - OMAP5_IOPAD(0x198, PIN_INPUT | MUX_MODE0) /* abemcbsp2_fsx.abemcbsp2_fsx */ - OMAP5_IOPAD(0x19a, PIN_INPUT | MUX_MODE0) /* abemcbsp2_clkx.abemcbsp2_clkx */ - >; - }; - - i2c1_pins: pinmux_i2c1_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x1f2, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */ - OMAP5_IOPAD(0x1f4, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */ - >; - }; - - mcspi2_pins: pinmux_mcspi2_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x0fc, PIN_INPUT | MUX_MODE0) /* mcspi2_clk */ - OMAP5_IOPAD(0x0fe, PIN_INPUT | MUX_MODE0) /* mcspi2_simo */ - OMAP5_IOPAD(0x100, PIN_INPUT_PULLUP | MUX_MODE0) /* mcspi2_somi */ - OMAP5_IOPAD(0x102, PIN_OUTPUT | MUX_MODE0) /* mcspi2_cs0 */ - >; - }; - - mcspi3_pins: pinmux_mcspi3_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x0b8, PIN_INPUT | MUX_MODE1) /* mcspi3_somi */ - OMAP5_IOPAD(0x0ba, PIN_INPUT | MUX_MODE1) /* mcspi3_cs0 */ - OMAP5_IOPAD(0x0bc, PIN_INPUT | MUX_MODE1) /* mcspi3_simo */ - OMAP5_IOPAD(0x0be, PIN_INPUT | MUX_MODE1) /* mcspi3_clk */ - >; - }; - - mmc3_pins: pinmux_mmc3_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x01a4, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_clk */ - OMAP5_IOPAD(0x01a6, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_cmd */ - OMAP5_IOPAD(0x01a8, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data0 */ - OMAP5_IOPAD(0x01aa, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data1 */ - OMAP5_IOPAD(0x01ac, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data2 */ - OMAP5_IOPAD(0x01ae, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data3 */ - >; - }; - - wlan_pins: pinmux_wlan_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x1bc, PIN_OUTPUT | MUX_MODE6) /* mcspi1_clk.gpio5_140 */ - >; - }; - - /* TI trees use GPIO mode; msecure mode does not work reliably? */ - palmas_msecure_pins: palmas_msecure_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x180, PIN_OUTPUT | MUX_MODE6) /* gpio8_234 */ - >; - }; - - usbhost_pins: pinmux_usbhost_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x0c4, PIN_INPUT | MUX_MODE0) /* usbb2_hsic_strobe */ - OMAP5_IOPAD(0x0c6, PIN_INPUT | MUX_MODE0) /* usbb2_hsic_data */ - - OMAP5_IOPAD(0x1de, PIN_INPUT | MUX_MODE0) /* usbb3_hsic_strobe */ - OMAP5_IOPAD(0x1e0, PIN_INPUT | MUX_MODE0) /* usbb3_hsic_data */ - - OMAP5_IOPAD(0x0b0, PIN_OUTPUT | MUX_MODE6) /* gpio3_80 HUB_NRESET */ - OMAP5_IOPAD(0x0ae, PIN_OUTPUT | MUX_MODE6) /* gpio3_79 ETH_NRESET */ - >; - }; - - led_gpio_pins: pinmux_led_gpio_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x1d6, PIN_OUTPUT | MUX_MODE6) /* uart3_cts_rctx.gpio5_153 */ - >; - }; - - uart1_pins: pinmux_uart1_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x0a0, PIN_OUTPUT | MUX_MODE0) /* uart1_tx.uart1_cts */ - OMAP5_IOPAD(0x0a2, PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_tx.uart1_cts */ - OMAP5_IOPAD(0x0a4, PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rx.uart1_rts */ - OMAP5_IOPAD(0x0a6, PIN_OUTPUT | MUX_MODE0) /* uart1_rx.uart1_rts */ - >; - }; - - uart3_pins: pinmux_uart3_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x1da, PIN_OUTPUT | MUX_MODE0) /* uart3_rts_irsd.uart3_tx_irtx */ - OMAP5_IOPAD(0x1dc, PIN_INPUT_PULLUP | MUX_MODE0) /* uart3_rx_irrx.uart3_usbb3_hsic */ - >; - }; - - uart5_pins: pinmux_uart5_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x1b0, PIN_INPUT_PULLUP | MUX_MODE0) /* uart5_rx.uart5_rx */ - OMAP5_IOPAD(0x1b2, PIN_OUTPUT | MUX_MODE0) /* uart5_tx.uart5_tx */ - OMAP5_IOPAD(0x1b4, PIN_INPUT_PULLUP | MUX_MODE0) /* uart5_cts.uart5_rts */ - OMAP5_IOPAD(0x1b6, PIN_OUTPUT | MUX_MODE0) /* uart5_cts.uart5_rts */ - >; - }; - - dss_hdmi_pins: pinmux_dss_hdmi_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x13c, PIN_INPUT | MUX_MODE0) /* hdmi_cec.hdmi_cec */ - OMAP5_IOPAD(0x140, PIN_INPUT | MUX_MODE0) /* hdmi_ddc_scl.hdmi_ddc_scl */ - OMAP5_IOPAD(0x142, PIN_INPUT | MUX_MODE0) /* hdmi_ddc_sda.hdmi_ddc_sda */ - >; - }; - - tpd12s015_pins: pinmux_tpd12s015_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x13e, PIN_INPUT_PULLDOWN | MUX_MODE6) /* hdmi_hpd.gpio7_193 */ - >; - }; -}; - -&omap5_pmx_wkup { - pinctrl-names = "default"; - pinctrl-0 = < - &usbhost_wkup_pins - >; - - palmas_sys_nirq_pins: pinmux_palmas_sys_nirq_pins { - pinctrl-single,pins = < - /* sys_nirq1 is pulled down as the SoC is inverting it for GIC */ - OMAP5_IOPAD(0x068, PIN_INPUT_PULLUP | MUX_MODE0) - >; - }; - - usbhost_wkup_pins: pinmux_usbhost_wkup_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x05a, PIN_OUTPUT | MUX_MODE0) /* fref_clk1_out, USB hub clk */ - >; - }; - - wlcore_irq_pin: pinmux_wlcore_irq_pin { - pinctrl-single,pins = < - OMAP5_IOPAD(0x40, PIN_INPUT | MUX_MODE6) /* llia_wakereqin.gpio1_wk14 */ - >; - }; -}; - -&mmc1 { - vmmc-supply = <&ldo9_reg>; - bus-width = <4>; -}; - -&mmc2 { - vmmc-supply = <&vmmcsd_fixed>; - bus-width = <8>; - ti,non-removable; -}; - -&mmc3 { - vmmc-supply = <&vmmcsdio_fixed>; - mmc-pwrseq = <&mmc3_pwrseq>; - bus-width = <4>; - non-removable; - cap-power-off-card; - pinctrl-names = "default"; - pinctrl-0 = <&mmc3_pins>; - interrupts-extended = <&wakeupgen GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH - &omap5_pmx_core 0x16a>; - - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@2 { - compatible = "ti,wl1271"; - reg = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&wlcore_irq_pin>; - interrupt-parent = <&gpio1>; - interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; /* gpio 14 */ - ref-clock-frequency = <26000000>; - }; -}; - -&mmc4 { - status = "disabled"; -}; - -&mmc5 { - status = "disabled"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - - clock-frequency = <400000>; - - palmas: palmas@48 { - compatible = "ti,palmas"; - /* sys_nirq/ext_sys_irq pins get inverted at mpuss wakeupgen */ - interrupts = ; - reg = <0x48>; - interrupt-controller; - #interrupt-cells = <2>; - ti,system-power-controller; - ti,mux-pad1 = <0xa1>; - ti,mux-pad2 = <0x1b>; - pinctrl-names = "default"; - pinctrl-0 = <&palmas_sys_nirq_pins &palmas_msecure_pins>; - - palmas_gpio: gpio { - compatible = "ti,palmas-gpio"; - gpio-controller; - #gpio-cells = <2>; - }; - - extcon_usb3: palmas_usb { - compatible = "ti,palmas-usb-vid"; - ti,enable-vbus-detection; - ti,enable-id-detection; - ti,wakeup; - id-gpios = <&palmas_gpio 0 GPIO_ACTIVE_HIGH>; - }; - - clk32kgaudio: palmas_clk32k@1 { - compatible = "ti,palmas-clk32kgaudio"; - #clock-cells = <0>; - }; - - rtc { - compatible = "ti,palmas-rtc"; - interrupt-parent = <&palmas>; - interrupts = <8 IRQ_TYPE_NONE>; - ti,backup-battery-chargeable; - ti,backup-battery-charge-high-current; - }; - - gpadc: gpadc { - compatible = "ti,palmas-gpadc"; - interrupts = <18 0 - 16 0 - 17 0>; - #io-channel-cells = <1>; - ti,channel0-current-microamp = <5>; - ti,channel3-current-microamp = <10>; - }; - - palmas_pmic { - compatible = "ti,palmas-pmic"; - interrupt-parent = <&palmas>; - interrupts = <14 IRQ_TYPE_NONE>; - interrupt-names = "short-irq"; - - ti,ldo6-vibrator; - - smps123-in-supply = <&vsys_cobra>; - smps45-in-supply = <&vsys_cobra>; - smps6-in-supply = <&vsys_cobra>; - smps7-in-supply = <&vsys_cobra>; - smps8-in-supply = <&vsys_cobra>; - smps9-in-supply = <&vsys_cobra>; - smps10_out2-in-supply = <&vsys_cobra>; - smps10_out1-in-supply = <&vsys_cobra>; - ldo1-in-supply = <&vsys_cobra>; - ldo2-in-supply = <&vsys_cobra>; - ldo3-in-supply = <&vdds_1v8_main>; - ldo4-in-supply = <&vdds_1v8_main>; - ldo5-in-supply = <&vsys_cobra>; - ldo6-in-supply = <&vdds_1v8_main>; - ldo7-in-supply = <&vsys_cobra>; - ldo8-in-supply = <&vsys_cobra>; - ldo9-in-supply = <&vmmcsd_fixed>; - ldoln-in-supply = <&vsys_cobra>; - ldousb-in-supply = <&vsys_cobra>; - - regulators { - smps123_reg: smps123 { - /* VDD_OPP_MPU */ - regulator-name = "smps123"; - regulator-min-microvolt = < 600000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - }; - - smps45_reg: smps45 { - /* VDD_OPP_MM */ - regulator-name = "smps45"; - regulator-min-microvolt = < 600000>; - regulator-max-microvolt = <1310000>; - regulator-always-on; - regulator-boot-on; - }; - - smps6_reg: smps6 { - /* VDD_DDR3 - over VDD_SMPS6 */ - regulator-name = "smps6"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - - smps7_reg: smps7 { - /* VDDS_1v8_OMAP over VDDS_1v8_MAIN */ - regulator-name = "smps7"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - smps8_reg: smps8 { - /* VDD_OPP_CORE */ - regulator-name = "smps8"; - regulator-min-microvolt = < 600000>; - regulator-max-microvolt = <1310000>; - regulator-always-on; - regulator-boot-on; - }; - - smps9_reg: smps9 { - /* VDDA_2v1_AUD over VDD_2v1 */ - regulator-name = "smps9"; - regulator-min-microvolt = <2100000>; - regulator-max-microvolt = <2100000>; - ti,smps-range = <0x80>; - }; - - smps10_out2_reg: smps10_out2 { - /* VBUS_5V_OTG */ - regulator-name = "smps10_out2"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - smps10_out1_reg: smps10_out1 { - /* VBUS_5V_OTG */ - regulator-name = "smps10_out1"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - ldo1_reg: ldo1 { - /* VDDAPHY_CAM: vdda_csiport */ - regulator-name = "ldo1"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo2_reg: ldo2 { - /* VCC_2V8_DISP: Does not go anywhere */ - regulator-name = "ldo2"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - /* Unused */ - status = "disabled"; - }; - - ldo3_reg: ldo3 { - /* VDDAPHY_MDM: vdda_lli */ - regulator-name = "ldo3"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - /* Only if Modem is used */ - status = "disabled"; - }; - - ldo4_reg: ldo4 { - /* VDDAPHY_DISP: vdda_dsiport/hdmi */ - regulator-name = "ldo4"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo5_reg: ldo5 { - /* VDDA_1V8_PHY: usb/sata/hdmi.. */ - regulator-name = "ldo5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo6_reg: ldo6 { - /* VDDS_1V2_WKUP: hsic/ldo_emu_wkup */ - regulator-name = "ldo6"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo7_reg: ldo7 { - /* VDD_VPP: vpp1 */ - regulator-name = "ldo7"; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - /* Only for efuse reprograming! */ - status = "disabled"; - }; - - ldo8_reg: ldo8 { - /* VDD_3v0: Does not go anywhere */ - regulator-name = "ldo8"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - /* Unused */ - status = "disabled"; - }; - - ldo9_reg: ldo9 { - /* VCC_DV_SDIO: vdds_sdcard */ - regulator-name = "ldo9"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - }; - - ldoln_reg: ldoln { - /* VDDA_1v8_REF: vdds_osc/mm_l4per.. */ - regulator-name = "ldoln"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldousb_reg: ldousb { - /* VDDA_3V_USB: VDDA_USBHS33 */ - regulator-name = "ldousb"; - regulator-min-microvolt = <3250000>; - regulator-max-microvolt = <3250000>; - regulator-always-on; - regulator-boot-on; - }; - - regen3_reg: regen3 { - /* REGEN3 controls LDO9 supply to card */ - regulator-name = "regen3"; - regulator-always-on; - regulator-boot-on; - }; - }; - }; - - palmas_power_button: palmas_power_button { - compatible = "ti,palmas-pwrbutton"; - interrupt-parent = <&palmas>; - interrupts = <1 IRQ_TYPE_EDGE_FALLING>; - wakeup-source; - }; - }; - - twl6040: twl@4b { - compatible = "ti,twl6040"; - #clock-cells = <0>; - reg = <0x4b>; - - pinctrl-names = "default"; - pinctrl-0 = <&twl6040_pins>; - - /* sys_nirq/ext_sys_irq pins get inverted at mpuss wakeupgen */ - interrupts = ; - - /* audpwron gpio defined in the board specific dts */ - - vio-supply = <&smps7_reg>; - v2v1-supply = <&smps9_reg>; - enable-active-high; - - clocks = <&clk32kgaudio>, <&fref_xtal_ck>; - clock-names = "clk32k", "mclk"; - }; -}; - -&mcpdm_module { - /* Module on the SoC needs external clock from the PMIC */ - pinctrl-names = "default"; - pinctrl-0 = <&mcpdm_pins>; - status = "okay"; -}; - -&mcpdm { - clocks = <&twl6040>; - clock-names = "pdmclk"; -}; - -&mcbsp1 { - pinctrl-names = "default"; - pinctrl-0 = <&mcbsp1_pins>; - status = "okay"; -}; - -&mcbsp2 { - pinctrl-names = "default"; - pinctrl-0 = <&mcbsp2_pins>; - status = "okay"; -}; - -&usbhshost { - port2-mode = "ehci-hsic"; - port3-mode = "ehci-hsic"; -}; - -&usbhsehci { - phys = <0 &hsusb2_phy &hsusb3_phy>; -}; - -&usb3 { - extcon = <&extcon_usb3>; - vbus-supply = <&smps10_out1_reg>; -}; - -&dwc3 { - extcon = <&extcon_usb3>; - dr_mode = "otg"; -}; - -&mcspi1 { - -}; - -&mcspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&mcspi2_pins>; -}; - -&mcspi3 { - pinctrl-names = "default"; - pinctrl-0 = <&mcspi3_pins>; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; - interrupts-extended = <&wakeupgen GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, - <&omap5_pmx_core 0x19c>; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&uart5_pins>; -}; - -&cpu0 { - cpu0-supply = <&smps123_reg>; -}; - -&dss { - status = "ok"; -}; - -&hdmi { - status = "ok"; - - /* vdda-supply populated in board specific dts file */ - - pinctrl-names = "default"; - pinctrl-0 = <&dss_hdmi_pins>; - - port { - hdmi_out: endpoint { - remote-endpoint = <&tpd12s015_in>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/omap5-cm-t54.dts b/sys/gnu/dts/arm/omap5-cm-t54.dts deleted file mode 100644 index e78d3718f14..00000000000 --- a/sys/gnu/dts/arm/omap5-cm-t54.dts +++ /dev/null @@ -1,697 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Support for CompuLab CM-T54 - */ -/dts-v1/; - -#include "omap5.dtsi" -#include -#include - -/ { - model = "CompuLab CM-T54"; - compatible = "compulab,omap5-cm-t54", "ti,omap5"; - - memory@80000000 { - device_type = "memory"; - reg = <0 0x80000000 0 0x7f000000>; /* 2048 MB */ - }; - - aliases { - display0 = &hdmi0; - display1 = &dvi0; - display2 = &lcd0; - }; - - vmmcsd_fixed: fixed-regulator-mmcsd { - compatible = "regulator-fixed"; - regulator-name = "vmmcsd_fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vwlan_pdn_fixed: fixed-regulator-vwlan-pdn { - compatible = "regulator-fixed"; - regulator-name = "vwlan_pdn_fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&ldo2_reg>; - gpio = <&gpio4 13 GPIO_ACTIVE_HIGH>; /* gpio4_109 */ - startup-delay-us = <1000>; - enable-active-high; - }; - - vwlan_fixed: fixed-regulator-vwlan { - compatible = "regulator-fixed"; - regulator-name = "vwlan_fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vwlan_pdn_fixed>; - gpio = <&gpio4 14 GPIO_ACTIVE_HIGH>; /* gpio4_110 */ - startup-delay-us = <1000>; - enable-active-high; - }; - - ads7846reg: ads7846-reg { - compatible = "regulator-fixed"; - regulator-name = "ads7846-reg"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - /* HS USB Host PHY on PORT 2 */ - hsusb2_phy: hsusb2_phy { - compatible = "usb-nop-xceiv"; - reset-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; /* gpio3_76 HUB_RESET */ - #phy-cells = <0>; - }; - - /* HS USB Host PHY on PORT 3 */ - hsusb3_phy: hsusb3_phy { - compatible = "usb-nop-xceiv"; - reset-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; /* gpio3_83 ETH_RESET */ - #phy-cells = <0>; - }; - - leds { - compatible = "gpio-leds"; - led1 { - label = "Heartbeat"; - gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; /* gpio3_80 ACT_LED */ - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - }; - - lcd0: display { - compatible = "startek,startek-kd050c", "panel-dpi"; - label = "lcd"; - - pinctrl-names = "default"; - pinctrl-0 = <&lcd_pins>; - - enable-gpios = <&gpio8 3 GPIO_ACTIVE_HIGH>; - - panel-timing { - clock-frequency = <33000000>; - hactive = <800>; - vactive = <480>; - hfront-porch = <40>; - hback-porch = <40>; - hsync-len = <43>; - vback-porch = <29>; - vfront-porch = <13>; - vsync-len = <3>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - - port { - lcd_in: endpoint { - remote-endpoint = <&dpi_lcd_out>; - }; - }; - }; - - hdmi0: connector0 { - compatible = "hdmi-connector"; - label = "hdmi"; - - type = "a"; - - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_conn_pins>; - - hpd-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; /* GPIO 193, HPD */ - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_out>; - }; - }; - }; - - tfp410: encoder0 { - compatible = "ti,tfp410"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - tfp410_in: endpoint { - remote-endpoint = <&dpi_dvi_out>; - }; - }; - - port@1 { - reg = <1>; - - tfp410_out: endpoint { - remote-endpoint = <&dvi_connector_in>; - }; - }; - }; - }; - - dvi0: connector1 { - compatible = "dvi-connector"; - label = "dvi"; - - digital; - - ddc-i2c-bus = <&i2c2>; - - port { - dvi_connector_in: endpoint { - remote-endpoint = <&tfp410_out>; - }; - }; - }; -}; - -&omap5_pmx_wkup { - - ads7846_pins: pinmux_ads7846_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x0042, PIN_INPUT_PULLDOWN | MUX_MODE6) /* llib_wakereqin.gpio1_wk15 */ - >; - }; - - palmas_sys_nirq_pins: pinmux_palmas_sys_nirq_pins { - pinctrl-single,pins = < - /* sys_nirq1 is pulled down as the SoC is inverting it for GIC */ - OMAP5_IOPAD(0x068, PIN_INPUT_PULLUP | MUX_MODE0) - >; - }; -}; - -&omap5_pmx_core { - pinctrl-names = "default"; - pinctrl-0 = < - &led_gpio_pins - &usbhost_pins - >; - - led_gpio_pins: pinmux_led_gpio_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x00b0, PIN_OUTPUT | MUX_MODE6) /* hsi2_caflag.gpio3_80 */ - >; - }; - - i2c1_pins: pinmux_i2c1_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x01f2, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_pmic_scl */ - OMAP5_IOPAD(0x01f4, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_pmic_sda */ - >; - }; - - i2c2_pins: pinmux_i2c2_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x01b8, PIN_INPUT | MUX_MODE0) /* i2c2_scl */ - OMAP5_IOPAD(0x01ba, PIN_INPUT | MUX_MODE0) /* i2c2_sda */ - >; - }; - - mmc1_pins: pinmux_mmc1_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x01e2, PIN_INPUT_PULLUP | MUX_MODE0) /* sdcard_clk */ - OMAP5_IOPAD(0x01e4, PIN_INPUT_PULLUP | MUX_MODE0) /* sdcard_cmd */ - OMAP5_IOPAD(0x01e6, PIN_INPUT_PULLUP | MUX_MODE0) /* sdcard_data2 */ - OMAP5_IOPAD(0x01e8, PIN_INPUT_PULLUP | MUX_MODE0) /* sdcard_data3 */ - OMAP5_IOPAD(0x01ea, PIN_INPUT_PULLUP | MUX_MODE0) /* sdcard_data0 */ - OMAP5_IOPAD(0x01ec, PIN_INPUT_PULLUP | MUX_MODE0) /* sdcard_data1 */ - >; - }; - - mmc2_pins: pinmux_mmc2_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x0040, PIN_INPUT_PULLUP | MUX_MODE0) /* emmc_clk */ - OMAP5_IOPAD(0x0042, PIN_INPUT_PULLUP | MUX_MODE0) /* emmc_cmd */ - OMAP5_IOPAD(0x0044, PIN_INPUT_PULLUP | MUX_MODE0) /* emmc_data0 */ - OMAP5_IOPAD(0x0046, PIN_INPUT_PULLUP | MUX_MODE0) /* emmc_data1 */ - OMAP5_IOPAD(0x0048, PIN_INPUT_PULLUP | MUX_MODE0) /* emmc_data2 */ - OMAP5_IOPAD(0x004a, PIN_INPUT_PULLUP | MUX_MODE0) /* emmc_data3 */ - OMAP5_IOPAD(0x004c, PIN_INPUT_PULLUP | MUX_MODE0) /* emmc_data4 */ - OMAP5_IOPAD(0x004e, PIN_INPUT_PULLUP | MUX_MODE0) /* emmc_data5 */ - OMAP5_IOPAD(0x0050, PIN_INPUT_PULLUP | MUX_MODE0) /* emmc_data6 */ - OMAP5_IOPAD(0x0052, PIN_INPUT_PULLUP | MUX_MODE0) /* emmc_data7 */ - >; - }; - - mmc3_pins: pinmux_mmc3_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x01a4, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_clk */ - OMAP5_IOPAD(0x01a6, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_cmd */ - OMAP5_IOPAD(0x01a8, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data0 */ - OMAP5_IOPAD(0x01aa, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data1 */ - OMAP5_IOPAD(0x01ac, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data2 */ - OMAP5_IOPAD(0x01ae, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data3 */ - >; - }; - - wlan_gpios_pins: pinmux_wlan_gpios_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x019c, PIN_OUTPUT_PULLDOWN | MUX_MODE6) /* abemcpdm_ul_data.gpio4_109 */ - OMAP5_IOPAD(0x019e, PIN_OUTPUT_PULLDOWN | MUX_MODE6) /* abemcpdm_dl_data.gpio4_110 */ - >; - }; - - usbhost_pins: pinmux_usbhost_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x00c4, PIN_INPUT | MUX_MODE0) /* usbb2_hsic_strobe */ - OMAP5_IOPAD(0x00c6, PIN_INPUT | MUX_MODE0) /* usbb2_hsic_data */ - - OMAP5_IOPAD(0x01dc, PIN_INPUT | MUX_MODE0) /* usbb3_hsic_strobe */ - OMAP5_IOPAD(0x01de, PIN_INPUT | MUX_MODE0) /* usbb3_hsic_data */ - - OMAP5_IOPAD(0x00a8, PIN_OUTPUT | MUX_MODE6) /* hsi2_caready.gpio3_76 */ - OMAP5_IOPAD(0x00b6, PIN_OUTPUT | MUX_MODE6) /* hsi2_acdata.gpio3_83 */ - >; - }; - - dss_hdmi_pins: pinmux_dss_hdmi_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x013c, PIN_INPUT | MUX_MODE0) /* hdmi_cec */ - OMAP5_IOPAD(0x0140, PIN_INPUT | MUX_MODE0) /* hdmi_ddc_scl */ - OMAP5_IOPAD(0x0142, PIN_INPUT | MUX_MODE0) /* hdmi_ddc_sda */ - >; - }; - - lcd_pins: pinmux_lcd_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x0172, PIN_OUTPUT_PULLDOWN | MUX_MODE6) /* timer11_pwm_evt.gpio8_227 */ - >; - }; - - hdmi_conn_pins: pinmux_hdmi_conn_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x013e, PIN_INPUT | MUX_MODE6) /* hdmi_hpd.gpio7_193 */ - >; - }; - - dss_dpi_pins: pinmux_dss_dpi_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x0104, PIN_OUTPUT | MUX_MODE3) /* rfbi_data15.dispc_data15 */ - OMAP5_IOPAD(0x0106, PIN_OUTPUT | MUX_MODE3) /* rfbi_data14.dispc_data14 */ - OMAP5_IOPAD(0x0108, PIN_OUTPUT | MUX_MODE3) /* rfbi_data13.dispc_data13 */ - OMAP5_IOPAD(0x010a, PIN_OUTPUT | MUX_MODE3) /* rfbi_data12.dispc_data12 */ - OMAP5_IOPAD(0x010c, PIN_OUTPUT | MUX_MODE3) /* rfbi_data11.dispc_data11 */ - OMAP5_IOPAD(0x010e, PIN_OUTPUT | MUX_MODE3) /* rfbi_data10.dispc_data10 */ - OMAP5_IOPAD(0x0110, PIN_OUTPUT | MUX_MODE3) /* rfbi_data9.dispc_data9 */ - OMAP5_IOPAD(0x0112, PIN_OUTPUT | MUX_MODE3) /* rfbi_data8.dispc_data8 */ - OMAP5_IOPAD(0x0114, PIN_OUTPUT | MUX_MODE3) /* rfbi_data7.dispc_data7 */ - OMAP5_IOPAD(0x0116, PIN_OUTPUT | MUX_MODE3) /* rfbi_data6.dispc_data6 */ - OMAP5_IOPAD(0x0118, PIN_OUTPUT | MUX_MODE3) /* rfbi_data5.dispc_data5 */ - OMAP5_IOPAD(0x011a, PIN_OUTPUT | MUX_MODE3) /* rfbi_data4.dispc_data4 */ - OMAP5_IOPAD(0x011c, PIN_OUTPUT | MUX_MODE3) /* rfbi_data3.dispc_data3 */ - OMAP5_IOPAD(0x011e, PIN_OUTPUT | MUX_MODE3) /* rfbi_data2.dispc_data2 */ - OMAP5_IOPAD(0x0120, PIN_OUTPUT | MUX_MODE3) /* rfbi_data1.dispc_data1 */ - OMAP5_IOPAD(0x0122, PIN_OUTPUT | MUX_MODE3) /* rfbi_data0.dispc_data0 */ - OMAP5_IOPAD(0x0124, PIN_OUTPUT | MUX_MODE3) /* rfbi_we.dispc_vsync */ - OMAP5_IOPAD(0x0126, PIN_OUTPUT | MUX_MODE3) /* rfbi_cs0.dispc_hsync */ - OMAP5_IOPAD(0x0128, PIN_OUTPUT | MUX_MODE3) /* rfbi_a0.dispc_de */ - OMAP5_IOPAD(0x012a, PIN_OUTPUT | MUX_MODE3) /* rfbi_re.dispc_pclk */ - OMAP5_IOPAD(0x012c, PIN_OUTPUT | MUX_MODE3) /* rfbi_hsync0.dispc_data17 */ - OMAP5_IOPAD(0x012e, PIN_OUTPUT | MUX_MODE3) /* rfbi_te_vsync0.dispc_data16 */ - OMAP5_IOPAD(0x0130, PIN_OUTPUT | MUX_MODE3) /* gpio6_182.dispc_data18 */ - OMAP5_IOPAD(0x0132, PIN_OUTPUT | MUX_MODE3) /* gpio6_183.dispc_data19 */ - OMAP5_IOPAD(0x0134, PIN_OUTPUT | MUX_MODE3) /* gpio6_184.dispc_data20 */ - OMAP5_IOPAD(0x0136, PIN_OUTPUT | MUX_MODE3) /* gpio6_185.dispc_data21 */ - OMAP5_IOPAD(0x0138, PIN_OUTPUT | MUX_MODE3) /* gpio6_186.dispc_data22 */ - OMAP5_IOPAD(0x013a, PIN_OUTPUT | MUX_MODE3) /* gpio6_187.dispc_data23 */ - >; - }; - - mcspi2_pins: pinmux_mcspi1_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x00fc, PIN_INPUT | MUX_MODE0) /* mcspi2_clk */ - OMAP5_IOPAD(0x00fe, PIN_INPUT | MUX_MODE0) /* mcspi2_simo */ - OMAP5_IOPAD(0x0100, PIN_INPUT | MUX_MODE0) /* mcspi2_somi */ - OMAP5_IOPAD(0x0102, PIN_INPUT | MUX_MODE0) /* mcspi2_cs0 */ - >; - }; -}; - -&mcspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&mcspi2_pins>; - - /* touch controller */ - ads7846@0 { - pinctrl-names = "default"; - pinctrl-0 = <&ads7846_pins>; - - compatible = "ti,ads7846"; - vcc-supply = <&ads7846reg>; - - reg = <0>; /* CS0 */ - spi-max-frequency = <1500000>; - - interrupt-parent = <&gpio1>; - interrupts = <15 0>; /* gpio1_wk15 */ - pendown-gpio = <&gpio1 15 GPIO_ACTIVE_HIGH>; - - - ti,x-min = /bits/ 16 <0x0>; - ti,x-max = /bits/ 16 <0x0fff>; - ti,y-min = /bits/ 16 <0x0>; - ti,y-max = /bits/ 16 <0x0fff>; - - ti,x-plate-ohms = /bits/ 16 <180>; - ti,pressure-max = /bits/ 16 <255>; - - ti,debounce-max = /bits/ 16 <30>; - ti,debounce-tol = /bits/ 16 <10>; - ti,debounce-rep = /bits/ 16 <1>; - - wakeup-source; - }; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - vmmc-supply = <&ldo9_reg>; - bus-width = <4>; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; - vmmc-supply = <&vmmcsd_fixed>; - bus-width = <8>; - ti,non-removable; -}; - -&mmc3 { - pinctrl-names = "default"; - pinctrl-0 = < - &mmc3_pins - &wlan_gpios_pins - >; - vmmc-supply = <&vwlan_fixed>; - bus-width = <4>; - ti,non-removable; -}; - -&mmc4 { - status = "disabled"; -}; - -&mmc5 { - status = "disabled"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - - clock-frequency = <400000>; - - at24@50 { - compatible = "atmel,24c02"; - pagesize = <16>; - reg = <0x50>; - }; - - palmas: palmas@48 { - compatible = "ti,palmas"; - reg = <0x48>; - pinctrl-0 = <&palmas_sys_nirq_pins>; - pinctrl-names = "default"; - /* sys_nirq/ext_sys_irq pins get inverted at mpuss wakeupgen */ - interrupts = ; - interrupt-controller; - #interrupt-cells = <2>; - ti,system-power-controller; - - extcon_usb3: palmas_usb { - compatible = "ti,palmas-usb-vid"; - ti,enable-vbus-detection; - ti,enable-id-detection; - ti,wakeup; - }; - - rtc { - compatible = "ti,palmas-rtc"; - interrupt-parent = <&palmas>; - interrupts = <8 IRQ_TYPE_NONE>; - }; - - palmas_pmic { - compatible = "ti,palmas-pmic"; - interrupt-parent = <&palmas>; - interrupts = <14 IRQ_TYPE_NONE>; - interrupt-names = "short-irq"; - - ti,ldo6-vibrator; - - regulators { - smps123_reg: smps123 { - /* VDD_OPP_MPU */ - regulator-name = "smps123"; - regulator-min-microvolt = < 600000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - }; - - smps45_reg: smps45 { - /* VDD_OPP_MM */ - regulator-name = "smps45"; - regulator-min-microvolt = < 600000>; - regulator-max-microvolt = <1310000>; - regulator-always-on; - regulator-boot-on; - }; - - smps6_reg: smps6 { - /* VDD_DDR3 - over VDD_SMPS6 */ - regulator-name = "smps6"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - }; - - smps7_reg: smps7 { - /* VDDS_1v8_OMAP over VDDS_1v8_MAIN */ - regulator-name = "smps7"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - smps8_reg: smps8 { - /* VDD_OPP_CORE */ - regulator-name = "smps8"; - regulator-min-microvolt = < 600000>; - regulator-max-microvolt = <1310000>; - regulator-always-on; - regulator-boot-on; - }; - - smps9_reg: smps9 { - /* VDDA_2v1_AUD over VDD_2v1 */ - regulator-name = "smps9"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - ti,smps-range = <0x80>; - regulator-always-on; - regulator-boot-on; - }; - - smps10_out2_reg: smps10_out2 { - /* VBUS_5V_OTG */ - regulator-name = "smps10_out2"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - smps10_out1_reg: smps10_out1 { - /* VBUS_5V_OTG */ - regulator-name = "smps10_out1"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - ldo1_reg: ldo1 { - /* VDDAPHY_CAM: vdda_csiport */ - regulator-name = "ldo1"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo2_reg: ldo2 { - /* VDD_3V3_WLAN */ - regulator-name = "ldo2"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <1000>; - }; - - ldo3_reg: ldo3 { - /* VCC_1V5_AUD */ - regulator-name = "ldo3"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo4_reg: ldo4 { - /* VDDAPHY_DISP: vdda_dsiport/hdmi */ - regulator-name = "ldo4"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo5_reg: ldo5 { - /* VDDA_1V8_PHY: usb/sata/hdmi.. */ - regulator-name = "ldo5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo6_reg: ldo6 { - /* VDDS_1V2_WKUP: hsic/ldo_emu_wkup */ - regulator-name = "ldo6"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo7_reg: ldo7 { - /* VDD_VPP: vpp1 */ - regulator-name = "ldo7"; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - /* Only for efuse reprograming! */ - status = "disabled"; - }; - - ldo8_reg: ldo8 { - /* VDD_3V_GP: act led/serial console */ - regulator-name = "ldo8"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo9_reg: ldo9 { - /* VCC_DV_SDIO: vdds_sdcard */ - regulator-name = "ldo9"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - }; - - ldoln_reg: ldoln { - /* VDDA_1v8_REF: vdds_osc/mm_l4per.. */ - regulator-name = "ldoln"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldousb_reg: ldousb { - /* VDDA_3V_USB: VDDA_USBHS33 */ - regulator-name = "ldousb"; - regulator-min-microvolt = <3250000>; - regulator-max-microvolt = <3250000>; - regulator-always-on; - regulator-boot-on; - }; - - regen3_reg: regen3 { - /* REGEN3 controls LDO9 supply to card */ - regulator-name = "regen3"; - regulator-always-on; - regulator-boot-on; - }; - }; - }; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - - clock-frequency = <100000>; -}; - -&usbhshost { - port2-mode = "ehci-hsic"; - port3-mode = "ehci-hsic"; -}; - -&usbhsehci { - phys = <0 &hsusb2_phy &hsusb3_phy>; -}; - -&usb3 { - extcon = <&extcon_usb3>; - vbus-supply = <&smps10_out1_reg>; -}; - -&cpu0 { - cpu0-supply = <&smps123_reg>; -}; - -&dss { - status = "ok"; - - pinctrl-names = "default"; - pinctrl-0 = <&dss_dpi_pins>; - - port { - #address-cells = <1>; - #size-cells = <0>; - - dpi_dvi_out: endpoint@0 { - reg = <0>; - remote-endpoint = <&tfp410_in>; - data-lines = <24>; - }; - - dpi_lcd_out: endpoint@1 { - reg = <1>; - remote-endpoint = <&lcd_in>; - data-lines = <24>; - }; - }; -}; - -&dsi2 { - status = "ok"; - vdd-supply = <&ldo4_reg>; -}; - -&hdmi { - status = "ok"; - vdda-supply = <&ldo4_reg>; - - pinctrl-names = "default"; - pinctrl-0 = <&dss_hdmi_pins>; - - port { - hdmi_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - lanes = <1 0 3 2 5 4 7 6>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/omap5-core-thermal.dtsi b/sys/gnu/dts/arm/omap5-core-thermal.dtsi deleted file mode 100644 index de8a3d456cf..00000000000 --- a/sys/gnu/dts/arm/omap5-core-thermal.dtsi +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Device Tree Source for OMAP543x SoC CORE thermal - * - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ - * Contact: Eduardo Valentin - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -#include - -core_thermal: core_thermal { - polling-delay-passive = <250>; /* milliseconds */ - polling-delay = <500>; /* milliseconds */ - - /* sensor ID */ - thermal-sensors = <&bandgap 2>; - - trips { - core_crit: core_crit { - temperature = <125000>; /* milliCelsius */ - hysteresis = <2000>; /* milliCelsius */ - type = "critical"; - }; - }; -}; diff --git a/sys/gnu/dts/arm/omap5-gpu-thermal.dtsi b/sys/gnu/dts/arm/omap5-gpu-thermal.dtsi deleted file mode 100644 index bc3090f2e84..00000000000 --- a/sys/gnu/dts/arm/omap5-gpu-thermal.dtsi +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Device Tree Source for OMAP543x SoC GPU thermal - * - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ - * Contact: Eduardo Valentin - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -#include - -gpu_thermal: gpu_thermal { - polling-delay-passive = <250>; /* milliseconds */ - polling-delay = <500>; /* milliseconds */ - - /* sensor ID */ - thermal-sensors = <&bandgap 1>; - - trips { - gpu_crit: gpu_crit { - temperature = <125000>; /* milliCelsius */ - hysteresis = <2000>; /* milliCelsius */ - type = "critical"; - }; - }; -}; diff --git a/sys/gnu/dts/arm/omap5-igep0050.dts b/sys/gnu/dts/arm/omap5-igep0050.dts deleted file mode 100644 index 76e499d89d2..00000000000 --- a/sys/gnu/dts/arm/omap5-igep0050.dts +++ /dev/null @@ -1,136 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2013 ISEE 2007 SL - http://www.isee.biz/ - */ -/dts-v1/; - -#include -#include "omap5-board-common.dtsi" - -/ { - model = "IGEPv5"; - compatible = "isee,omap5-igep0050", "ti,omap5"; - - memory@80000000 { - device_type = "memory"; - reg = <0x0 0x80000000 0 0x7f000000>; /* 2032 MB */ - }; - - aliases { - ethernet = ðernet; - }; - - gpio_keys { - compatible = "gpio-keys"; - pinctrl-0 = <&power_button_pin>; - pinctrl-names = "default"; - - power-button { - label = "Power Button"; - linux,code = ; - gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; - }; - }; - - leds { - compatible = "gpio-leds"; - led@1 { - label = "board:green:usr0"; - gpios = <&tca6416 1 0>; - default-state = "off"; - }; - led@2 { - label = "board:red:usr1"; - gpios = <&tca6416 2 0>; - default-state = "off"; - }; - led@3 { - label = "board:blue:usr1"; - gpios = <&tca6416 3 0>; - default-state = "off"; - }; - }; -}; - -&hdmi { - vdda-supply = <&ldo7_reg>; -}; - -&i2c4 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_pins>; - - tca6416: tca6416@21 { - compatible = "ti,tca6416"; - reg = <0x21>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -/* LDO4 is VPP1 - ball AD9 */ -&ldo4_reg { - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; -}; - -/* - * LDO7 is used for HDMI: VDDA_DSIPORTA - ball AA33, VDDA_DSIPORTC - ball AE33, - * VDDA_HDMI - ball AN25 - */ -&ldo7_reg { - status = "okay"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; -}; - -&omap5_pmx_core { - i2c4_pins: pinmux_i2c4_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x0f8, PIN_INPUT | MUX_MODE0) /* i2c4_scl */ - OMAP5_IOPAD(0x0fa, PIN_INPUT | MUX_MODE0) /* i2c4_sda */ - >; - }; - - power_button_pin: pinctrl_power_button_pin { - pinctrl-single,pins = < - OMAP5_IOPAD(0x086, PIN_INPUT | MUX_MODE6) /* gpio4_118 */ - >; - }; -}; - -&tpd12s015 { - gpios = <&tca6416 11 0>, /* TCA6416 P01, CT_CP_HDP */ - <&tca6416 12 0>, /* TCA6416 P00, LS_OE*/ - <&gpio7 1 0>, /* 193, HPD */ - <&gpio7 2 0>, /* 194, SCL */ - <&gpio7 3 0>; /* 195, SDA */ -}; - -&twl6040 { - ti,audpwron-gpio = <&gpio5 16 GPIO_ACTIVE_HIGH>; /* gpio line 144 */ -}; - -&twl6040_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x1c4, PIN_OUTPUT | MUX_MODE6) /* mcspi1_somi.gpio5_144 */ - OMAP5_IOPAD(0x1ca, PIN_OUTPUT | MUX_MODE6) /* perslimbus2_clock.gpio5_145 */ - >; -}; - -&usbhsehci { - #address-cells = <1>; - #size-cells = <0>; - - hub@2 { - compatible = "usb424,3503"; - reg = <2>; - #address-cells = <1>; - #size-cells = <0>; - - ethernet: usbether@3 { - compatible = "usb424,7500"; - reg = <3>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/omap5-l4-abe.dtsi b/sys/gnu/dts/arm/omap5-l4-abe.dtsi deleted file mode 100644 index dc9d0532f4c..00000000000 --- a/sys/gnu/dts/arm/omap5-l4-abe.dtsi +++ /dev/null @@ -1,447 +0,0 @@ -&l4_abe { /* 0x40100000 */ - compatible = "ti,omap5-l4-abe", "simple-bus"; - reg = <0x40100000 0x400>, - <0x40100400 0x400>; - reg-names = "la", "ap"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x40100000 0x100000>, /* segment 0 */ - <0x49000000 0x49000000 0x100000>; - segment@0 { /* 0x40100000 */ - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = - /* CPU to L4 ABE mapping */ - <0x00000000 0x00000000 0x000400>, /* ap 0 */ - <0x00000400 0x00000400 0x000400>, /* ap 1 */ - <0x00022000 0x00022000 0x001000>, /* ap 2 */ - <0x00023000 0x00023000 0x001000>, /* ap 3 */ - <0x00024000 0x00024000 0x001000>, /* ap 4 */ - <0x00025000 0x00025000 0x001000>, /* ap 5 */ - <0x00026000 0x00026000 0x001000>, /* ap 6 */ - <0x00027000 0x00027000 0x001000>, /* ap 7 */ - <0x00028000 0x00028000 0x001000>, /* ap 8 */ - <0x00029000 0x00029000 0x001000>, /* ap 9 */ - <0x0002a000 0x0002a000 0x001000>, /* ap 10 */ - <0x0002b000 0x0002b000 0x001000>, /* ap 11 */ - <0x0002e000 0x0002e000 0x001000>, /* ap 12 */ - <0x0002f000 0x0002f000 0x001000>, /* ap 13 */ - <0x00030000 0x00030000 0x001000>, /* ap 14 */ - <0x00031000 0x00031000 0x001000>, /* ap 15 */ - <0x00032000 0x00032000 0x001000>, /* ap 16 */ - <0x00033000 0x00033000 0x001000>, /* ap 17 */ - <0x00038000 0x00038000 0x001000>, /* ap 18 */ - <0x00039000 0x00039000 0x001000>, /* ap 19 */ - <0x0003a000 0x0003a000 0x001000>, /* ap 20 */ - <0x0003b000 0x0003b000 0x001000>, /* ap 21 */ - <0x0003c000 0x0003c000 0x001000>, /* ap 22 */ - <0x0003d000 0x0003d000 0x001000>, /* ap 23 */ - <0x0003e000 0x0003e000 0x001000>, /* ap 24 */ - <0x0003f000 0x0003f000 0x001000>, /* ap 25 */ - <0x00080000 0x00080000 0x010000>, /* ap 26 */ - <0x00080000 0x00080000 0x001000>, /* ap 27 */ - <0x000a0000 0x000a0000 0x010000>, /* ap 28 */ - <0x000a0000 0x000a0000 0x001000>, /* ap 29 */ - <0x000c0000 0x000c0000 0x010000>, /* ap 30 */ - <0x000c0000 0x000c0000 0x001000>, /* ap 31 */ - <0x000f1000 0x000f1000 0x001000>, /* ap 32 */ - <0x000f2000 0x000f2000 0x001000>, /* ap 33 */ - - /* L3 to L4 ABE mapping */ - <0x49000000 0x49000000 0x000400>, /* ap 0 */ - <0x49000400 0x49000400 0x000400>, /* ap 1 */ - <0x49022000 0x49022000 0x001000>, /* ap 2 */ - <0x49023000 0x49023000 0x001000>, /* ap 3 */ - <0x49024000 0x49024000 0x001000>, /* ap 4 */ - <0x49025000 0x49025000 0x001000>, /* ap 5 */ - <0x49026000 0x49026000 0x001000>, /* ap 6 */ - <0x49027000 0x49027000 0x001000>, /* ap 7 */ - <0x49028000 0x49028000 0x001000>, /* ap 8 */ - <0x49029000 0x49029000 0x001000>, /* ap 9 */ - <0x4902a000 0x4902a000 0x001000>, /* ap 10 */ - <0x4902b000 0x4902b000 0x001000>, /* ap 11 */ - <0x4902e000 0x4902e000 0x001000>, /* ap 12 */ - <0x4902f000 0x4902f000 0x001000>, /* ap 13 */ - <0x49030000 0x49030000 0x001000>, /* ap 14 */ - <0x49031000 0x49031000 0x001000>, /* ap 15 */ - <0x49032000 0x49032000 0x001000>, /* ap 16 */ - <0x49033000 0x49033000 0x001000>, /* ap 17 */ - <0x49038000 0x49038000 0x001000>, /* ap 18 */ - <0x49039000 0x49039000 0x001000>, /* ap 19 */ - <0x4903a000 0x4903a000 0x001000>, /* ap 20 */ - <0x4903b000 0x4903b000 0x001000>, /* ap 21 */ - <0x4903c000 0x4903c000 0x001000>, /* ap 22 */ - <0x4903d000 0x4903d000 0x001000>, /* ap 23 */ - <0x4903e000 0x4903e000 0x001000>, /* ap 24 */ - <0x4903f000 0x4903f000 0x001000>, /* ap 25 */ - <0x49080000 0x49080000 0x010000>, /* ap 26 */ - <0x49080000 0x49080000 0x001000>, /* ap 27 */ - <0x490a0000 0x490a0000 0x010000>, /* ap 28 */ - <0x490a0000 0x490a0000 0x001000>, /* ap 29 */ - <0x490c0000 0x490c0000 0x010000>, /* ap 30 */ - <0x490c0000 0x490c0000 0x001000>, /* ap 31 */ - <0x490f1000 0x490f1000 0x001000>, /* ap 32 */ - <0x490f2000 0x490f2000 0x001000>; /* ap 33 */ - - target-module@22000 { /* 0x40122000, ap 2 02.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "mcbsp1"; - reg = <0x2208c 0x4>; - reg-names = "sysc"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET)>; - ti,sysc-sidle = , - , - ; - /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */ - clocks = <&abe_clkctrl OMAP5_MCBSP1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x22000 0x1000>, - <0x49022000 0x49022000 0x1000>; - - mcbsp1: mcbsp@0 { - compatible = "ti,omap4-mcbsp"; - reg = <0x0 0xff>, /* MPU private access */ - <0x49022000 0xff>; /* L3 Interconnect */ - reg-names = "mpu", "dma"; - interrupts = ; - interrupt-names = "common"; - ti,buffer-size = <128>; - dmas = <&sdma 33>, - <&sdma 34>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - }; - - target-module@24000 { /* 0x40124000, ap 4 04.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "mcbsp2"; - reg = <0x2408c 0x4>; - reg-names = "sysc"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET)>; - ti,sysc-sidle = , - , - ; - /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */ - clocks = <&abe_clkctrl OMAP5_MCBSP2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x24000 0x1000>, - <0x49024000 0x49024000 0x1000>; - - mcbsp2: mcbsp@0 { - compatible = "ti,omap4-mcbsp"; - reg = <0x0 0xff>, /* MPU private access */ - <0x49024000 0xff>; /* L3 Interconnect */ - reg-names = "mpu", "dma"; - interrupts = ; - interrupt-names = "common"; - ti,buffer-size = <128>; - dmas = <&sdma 17>, - <&sdma 18>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - }; - - target-module@26000 { /* 0x40126000, ap 6 06.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "mcbsp3"; - reg = <0x2608c 0x4>; - reg-names = "sysc"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET)>; - ti,sysc-sidle = , - , - ; - /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */ - clocks = <&abe_clkctrl OMAP5_MCBSP3_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x26000 0x1000>, - <0x49026000 0x49026000 0x1000>; - - mcbsp3: mcbsp@0 { - compatible = "ti,omap4-mcbsp"; - reg = <0x0 0xff>, /* MPU private access */ - <0x49026000 0xff>; /* L3 Interconnect */ - reg-names = "mpu", "dma"; - interrupts = ; - interrupt-names = "common"; - ti,buffer-size = <128>; - dmas = <&sdma 19>, - <&sdma 20>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - }; - - target-module@28000 { /* 0x40128000, ap 8 08.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x28000 0x1000>, - <0x49028000 0x49028000 0x1000>; - }; - - target-module@2a000 { /* 0x4012a000, ap 10 0a.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2a000 0x1000>, - <0x4902a000 0x4902a000 0x1000>; - }; - - target-module@2e000 { /* 0x4012e000, ap 12 0c.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - ti,hwmods = "dmic"; - reg = <0x2e000 0x4>, - <0x2e010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */ - clocks = <&abe_clkctrl OMAP5_DMIC_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2e000 0x1000>, - <0x4902e000 0x4902e000 0x1000>; - - dmic: dmic@0 { - compatible = "ti,omap4-dmic"; - reg = <0x0 0x7f>, /* MPU private access */ - <0x4902e000 0x7f>; /* L3 Interconnect */ - reg-names = "mpu", "dma"; - interrupts = ; - dmas = <&sdma 67>; - dma-names = "up_link"; - status = "disabled"; - }; - }; - - target-module@30000 { /* 0x40130000, ap 14 0e.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x30000 0x1000>, - <0x49030000 0x49030000 0x1000>; - }; - - mcpdm_module: target-module@32000 { /* 0x40132000, ap 16 10.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - ti,hwmods = "mcpdm"; - reg = <0x32000 0x4>, - <0x32010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */ - clocks = <&abe_clkctrl OMAP5_MCPDM_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x32000 0x1000>, - <0x49032000 0x49032000 0x1000>; - - /* Must be only enabled for boards with pdmclk wired */ - status = "disabled"; - - mcpdm: mcpdm@0 { - compatible = "ti,omap4-mcpdm"; - reg = <0x0 0x7f>, /* MPU private access */ - <0x49032000 0x7f>; /* L3 Interconnect */ - reg-names = "mpu", "dma"; - interrupts = ; - dmas = <&sdma 65>, - <&sdma 66>; - dma-names = "up_link", "dn_link"; - }; - }; - - target-module@38000 { /* 0x40138000, ap 18 12.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - ti,hwmods = "timer5"; - reg = <0x38000 0x4>, - <0x38010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */ - clocks = <&abe_clkctrl OMAP5_TIMER5_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x38000 0x1000>, - <0x49038000 0x49038000 0x1000>; - - timer5: timer@0 { - compatible = "ti,omap5430-timer"; - reg = <0x0 0x80>, - <0x49038000 0x80>; - clocks = <&abe_clkctrl OMAP5_TIMER5_CLKCTRL 24>; - clock-names = "fck"; - interrupts = ; - ti,timer-dsp; - ti,timer-pwm; - }; - }; - - target-module@3a000 { /* 0x4013a000, ap 20 14.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - ti,hwmods = "timer6"; - reg = <0x3a000 0x4>, - <0x3a010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */ - clocks = <&abe_clkctrl OMAP5_TIMER6_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x3a000 0x1000>, - <0x4903a000 0x4903a000 0x1000>; - - timer6: timer@0 { - compatible = "ti,omap5430-timer"; - reg = <0x0 0x80>, - <0x4903a000 0x80>; - clocks = <&abe_clkctrl OMAP5_TIMER6_CLKCTRL 24>; - clock-names = "fck"; - interrupts = ; - ti,timer-dsp; - ti,timer-pwm; - }; - }; - - target-module@3c000 { /* 0x4013c000, ap 22 16.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - ti,hwmods = "timer7"; - reg = <0x3c000 0x4>, - <0x3c010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */ - clocks = <&abe_clkctrl OMAP5_TIMER7_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x3c000 0x1000>, - <0x4903c000 0x4903c000 0x1000>; - - timer7: timer@0 { - compatible = "ti,omap5430-timer"; - reg = <0x0 0x80>, - <0x4903c000 0x80>; - clocks = <&abe_clkctrl OMAP5_TIMER7_CLKCTRL 24>; - clock-names = "fck"; - interrupts = ; - ti,timer-dsp; - }; - }; - - target-module@3e000 { /* 0x4013e000, ap 24 18.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - ti,hwmods = "timer8"; - reg = <0x3e000 0x4>, - <0x3e010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */ - clocks = <&abe_clkctrl OMAP5_TIMER8_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x3e000 0x1000>, - <0x4903e000 0x4903e000 0x1000>; - - timer8: timer@0 { - compatible = "ti,omap5430-timer"; - reg = <0x0 0x80>, - <0x4903e000 0x80>; - clocks = <&abe_clkctrl OMAP5_TIMER8_CLKCTRL 24>; - clock-names = "fck"; - interrupts = ; - ti,timer-dsp; - ti,timer-pwm; - }; - }; - - target-module@80000 { /* 0x40180000, ap 26 1a.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x80000 0x10000>, - <0x49080000 0x49080000 0x10000>; - }; - - target-module@a0000 { /* 0x401a0000, ap 28 1c.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xa0000 0x10000>, - <0x490a0000 0x490a0000 0x10000>; - }; - - target-module@c0000 { /* 0x401c0000, ap 30 1e.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xc0000 0x10000>, - <0x490c0000 0x490c0000 0x10000>; - }; - - target-module@f1000 { /* 0x401f1000, ap 32 20.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xf1000 0x1000>, - <0x490f1000 0x490f1000 0x1000>; - }; - }; -}; - diff --git a/sys/gnu/dts/arm/omap5-l4.dtsi b/sys/gnu/dts/arm/omap5-l4.dtsi deleted file mode 100644 index 0960348002a..00000000000 --- a/sys/gnu/dts/arm/omap5-l4.dtsi +++ /dev/null @@ -1,2460 +0,0 @@ -&l4_cfg { /* 0x4a000000 */ - compatible = "ti,omap5-l4-cfg", "simple-bus"; - reg = <0x4a000000 0x800>, - <0x4a000800 0x800>, - <0x4a001000 0x1000>; - reg-names = "ap", "la", "ia0"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x4a000000 0x080000>, /* segment 0 */ - <0x00080000 0x4a080000 0x080000>, /* segment 1 */ - <0x00100000 0x4a100000 0x080000>, /* segment 2 */ - <0x00180000 0x4a180000 0x080000>, /* segment 3 */ - <0x00200000 0x4a200000 0x080000>, /* segment 4 */ - <0x00280000 0x4a280000 0x080000>, /* segment 5 */ - <0x00300000 0x4a300000 0x080000>; /* segment 6 */ - - segment@0 { /* 0x4a000000 */ - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ - <0x00001000 0x00001000 0x001000>, /* ap 1 */ - <0x00000800 0x00000800 0x000800>, /* ap 2 */ - <0x00002000 0x00002000 0x001000>, /* ap 3 */ - <0x00003000 0x00003000 0x001000>, /* ap 4 */ - <0x00004000 0x00004000 0x001000>, /* ap 5 */ - <0x00005000 0x00005000 0x001000>, /* ap 6 */ - <0x00056000 0x00056000 0x001000>, /* ap 7 */ - <0x00057000 0x00057000 0x001000>, /* ap 8 */ - <0x0005c000 0x0005c000 0x001000>, /* ap 9 */ - <0x00058000 0x00058000 0x001000>, /* ap 10 */ - <0x00062000 0x00062000 0x001000>, /* ap 11 */ - <0x00063000 0x00063000 0x001000>, /* ap 12 */ - <0x00008000 0x00008000 0x002000>, /* ap 21 */ - <0x0000a000 0x0000a000 0x001000>, /* ap 22 */ - <0x00066000 0x00066000 0x001000>, /* ap 23 */ - <0x00067000 0x00067000 0x001000>, /* ap 24 */ - <0x0005e000 0x0005e000 0x002000>, /* ap 69 */ - <0x00060000 0x00060000 0x001000>, /* ap 70 */ - <0x00064000 0x00064000 0x001000>, /* ap 71 */ - <0x00065000 0x00065000 0x001000>, /* ap 72 */ - <0x0005a000 0x0005a000 0x001000>, /* ap 77 */ - <0x0005b000 0x0005b000 0x001000>, /* ap 78 */ - <0x00070000 0x00070000 0x004000>, /* ap 79 */ - <0x00074000 0x00074000 0x001000>, /* ap 80 */ - <0x00075000 0x00075000 0x001000>, /* ap 81 */ - <0x00076000 0x00076000 0x001000>, /* ap 82 */ - <0x00020000 0x00020000 0x020000>, /* ap 109 */ - <0x00040000 0x00040000 0x001000>, /* ap 110 */ - <0x00059000 0x00059000 0x001000>; /* ap 111 */ - - target-module@2000 { /* 0x4a002000, ap 3 44.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x2000 0x4>; - reg-names = "rev"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2000 0x1000>; - - scm_core: scm@0 { - compatible = "ti,omap5-scm-core", "simple-bus"; - reg = <0x0 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x800>; - - scm_conf: scm_conf@0 { - compatible = "syscon"; - reg = <0x0 0x800>; - #address-cells = <1>; - #size-cells = <1>; - }; - }; - - scm_padconf_core: scm@800 { - compatible = "ti,omap5-scm-padconf-core", - "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x800 0x800>; - - omap5_pmx_core: pinmux@40 { - compatible = "ti,omap5-padconf", - "pinctrl-single"; - reg = <0x40 0x01b6>; - #address-cells = <1>; - #size-cells = <0>; - #pinctrl-cells = <1>; - #interrupt-cells = <1>; - interrupt-controller; - pinctrl-single,register-width = <16>; - pinctrl-single,function-mask = <0x7fff>; - }; - - omap5_padconf_global: omap5_padconf_global@5a0 { - compatible = "syscon", - "simple-bus"; - reg = <0x5a0 0xec>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x5a0 0xec>; - - pbias_regulator: pbias_regulator@60 { - compatible = "ti,pbias-omap5", "ti,pbias-omap"; - reg = <0x60 0x4>; - syscon = <&omap5_padconf_global>; - pbias_mmc_reg: pbias_mmc_omap5 { - regulator-name = "pbias_mmc_omap5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - }; - }; - }; - }; - - target-module@4000 { /* 0x4a004000, ap 5 5c.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x4000 0x4>; - reg-names = "rev"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x4000 0x1000>; - - cm_core_aon: cm_core_aon@0 { - compatible = "ti,omap5-cm-core-aon", - "simple-bus"; - reg = <0x0 0x2000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x1000>; - - cm_core_aon_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - cm_core_aon_clockdomains: clockdomains { - }; - }; - }; - - target-module@8000 { /* 0x4a008000, ap 21 4c.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x8000 0x4>; - reg-names = "rev"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x8000 0x2000>; - - cm_core: cm_core@0 { - compatible = "ti,omap5-cm-core", "simple-bus"; - reg = <0x0 0x2000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x2000>; - - cm_core_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - cm_core_clockdomains: clockdomains { - }; - }; - }; - - target-module@20000 { /* 0x4a020000, ap 109 08.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - ti,hwmods = "usb_otg_ss"; - reg = <0x20000 0x4>, - <0x20010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = ; - ti,sysc-midle = , - , - , - ; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */ - clocks = <&l3init_clkctrl OMAP5_USB_OTG_SS_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x20000 0x20000>; - - usb3: omap_dwc3@0 { - compatible = "ti,dwc3"; - reg = <0x0 0x10000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <1>; - utmi-mode = <2>; - ranges = <0 0 0x20000>; - dwc3: dwc3@10000 { - compatible = "snps,dwc3"; - reg = <0x10000 0x10000>; - interrupts = , - , - ; - interrupt-names = "peripheral", - "host", - "otg"; - phys = <&usb2_phy>, <&usb3_phy>; - phy-names = "usb2-phy", "usb3-phy"; - dr_mode = "peripheral"; - }; - }; - }; - - target-module@56000 { /* 0x4a056000, ap 7 02.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "dma_system"; - reg = <0x56000 0x4>, - <0x5602c 0x4>, - <0x56028 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_EMUFREE | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-midle = , - , - ; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, core_pwrdm, dma_clkdm */ - clocks = <&dma_clkctrl OMAP5_DMA_SYSTEM_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x56000 0x1000>; - - sdma: dma-controller@0 { - compatible = "ti,omap4430-sdma"; - reg = <0x0 0x1000>; - interrupts = , - , - , - ; - #dma-cells = <1>; - dma-channels = <32>; - dma-requests = <127>; - }; - }; - - target-module@58000 { /* 0x4a058000, ap 10 06.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00058000 0x00001000>, - <0x00001000 0x00059000 0x00001000>, - <0x00002000 0x0005a000 0x00001000>, - <0x00003000 0x0005b000 0x00001000>; - }; - - target-module@5e000 { /* 0x4a05e000, ap 69 2a.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x5e000 0x2000>; - }; - - target-module@62000 { /* 0x4a062000, ap 11 0e.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "usb_tll_hs"; - reg = <0x62000 0x4>, - <0x62010 0x4>, - <0x62014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */ - clocks = <&l3init_clkctrl OMAP5_USB_TLL_HS_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x62000 0x1000>; - - usbhstll: usbhstll@0 { - compatible = "ti,usbhs-tll"; - reg = <0x0 0x1000>; - interrupts = ; - }; - }; - - target-module@64000 { /* 0x4a064000, ap 71 1e.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - ti,hwmods = "usb_host_hs"; - reg = <0x64000 0x4>, - <0x64010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = ; - ti,sysc-midle = , - , - , - ; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */ - clocks = <&l3init_clkctrl OMAP5_USB_HOST_HS_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x64000 0x1000>; - - usbhshost: usbhshost@0 { - compatible = "ti,usbhs-host"; - reg = <0x0 0x800>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x1000>; - clocks = <&l3init_60m_fclk>, - <&xclk60mhsp1_ck>, - <&xclk60mhsp2_ck>; - clock-names = "refclk_60m_int", - "refclk_60m_ext_p1", - "refclk_60m_ext_p2"; - - usbhsohci: ohci@800 { - compatible = "ti,ohci-omap3"; - reg = <0x800 0x400>; - interrupts = ; - remote-wakeup-connected; - }; - - usbhsehci: ehci@c00 { - compatible = "ti,ehci-omap"; - reg = <0xc00 0x400>; - interrupts = ; - }; - }; - }; - - target-module@66000 { /* 0x4a066000, ap 23 0a.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "mmu_dsp"; - reg = <0x66000 0x4>, - <0x66010 0x4>, - <0x66014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): mm, dsp_pwrdm, dsp_clkdm */ - clocks = <&dsp_clkctrl OMAP5_MMU_DSP_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x66000 0x1000>; - - /* mmu_dsp cannot be moved before reset driver */ - status = "disabled"; - }; - - target-module@70000 { /* 0x4a070000, ap 79 2e.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x70000 0x4000>; - }; - - target-module@75000 { /* 0x4a075000, ap 81 32.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x75000 0x1000>; - }; - }; - - segment@80000 { /* 0x4a080000 */ - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00059000 0x000d9000 0x001000>, /* ap 13 */ - <0x0005a000 0x000da000 0x001000>, /* ap 14 */ - <0x0005b000 0x000db000 0x001000>, /* ap 15 */ - <0x0005c000 0x000dc000 0x001000>, /* ap 16 */ - <0x0005d000 0x000dd000 0x001000>, /* ap 17 */ - <0x0005e000 0x000de000 0x001000>, /* ap 18 */ - <0x00060000 0x000e0000 0x001000>, /* ap 19 */ - <0x00061000 0x000e1000 0x001000>, /* ap 20 */ - <0x00074000 0x000f4000 0x001000>, /* ap 25 */ - <0x00075000 0x000f5000 0x001000>, /* ap 26 */ - <0x00076000 0x000f6000 0x001000>, /* ap 27 */ - <0x00077000 0x000f7000 0x001000>, /* ap 28 */ - <0x00036000 0x000b6000 0x001000>, /* ap 65 */ - <0x00037000 0x000b7000 0x001000>, /* ap 66 */ - <0x0004d000 0x000cd000 0x001000>, /* ap 67 */ - <0x0004e000 0x000ce000 0x001000>, /* ap 68 */ - <0x00000000 0x00080000 0x004000>, /* ap 83 */ - <0x00004000 0x00084000 0x001000>, /* ap 84 */ - <0x00005000 0x00085000 0x001000>, /* ap 85 */ - <0x00006000 0x00086000 0x001000>, /* ap 86 */ - <0x00007000 0x00087000 0x001000>, /* ap 87 */ - <0x00008000 0x00088000 0x001000>, /* ap 88 */ - <0x00010000 0x00090000 0x004000>, /* ap 89 */ - <0x00014000 0x00094000 0x001000>, /* ap 90 */ - <0x00015000 0x00095000 0x001000>, /* ap 91 */ - <0x00016000 0x00096000 0x001000>, /* ap 92 */ - <0x00017000 0x00097000 0x001000>, /* ap 93 */ - <0x00018000 0x00098000 0x001000>, /* ap 94 */ - <0x00020000 0x000a0000 0x004000>, /* ap 95 */ - <0x00024000 0x000a4000 0x001000>, /* ap 96 */ - <0x00025000 0x000a5000 0x001000>, /* ap 97 */ - <0x00026000 0x000a6000 0x001000>, /* ap 98 */ - <0x00027000 0x000a7000 0x001000>, /* ap 99 */ - <0x00028000 0x000a8000 0x001000>; /* ap 100 */ - - target-module@0 { /* 0x4a080000, ap 83 28.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "ocp2scp1"; - reg = <0x0 0x4>, - <0x10 0x4>, - <0x14 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */ - clocks = <&l3init_clkctrl OMAP5_OCP2SCP1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00000000 0x00004000>, - <0x00004000 0x00004000 0x00001000>, - <0x00005000 0x00005000 0x00001000>, - <0x00006000 0x00006000 0x00001000>, - <0x00007000 0x00007000 0x00001000>; - - ocp2scp@0 { - compatible = "ti,omap-ocp2scp"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0 0x20>; - }; - - usb2_phy: usb2phy@4000 { - compatible = "ti,omap-usb2"; - reg = <0x4000 0x7c>; - syscon-phy-power = <&scm_conf 0x300>; - clocks = <&usb_phy_cm_clk32k>, - <&l3init_clkctrl OMAP5_USB_OTG_SS_CLKCTRL 8>; - clock-names = "wkupclk", "refclk"; - #phy-cells = <0>; - }; - - usb3_phy: usb3phy@4400 { - compatible = "ti,omap-usb3"; - reg = <0x4400 0x80>, - <0x4800 0x64>, - <0x4c00 0x40>; - reg-names = "phy_rx", "phy_tx", "pll_ctrl"; - syscon-phy-power = <&scm_conf 0x370>; - clocks = <&usb_phy_cm_clk32k>, - <&sys_clkin>, - <&l3init_clkctrl OMAP5_USB_OTG_SS_CLKCTRL 8>; - clock-names = "wkupclk", - "sysclk", - "refclk"; - #phy-cells = <0>; - }; - }; - - target-module@10000 { /* 0x4a090000, ap 89 36.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "ocp2scp3"; - reg = <0x10000 0x4>, - <0x10010 0x4>, - <0x10014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */ - clocks = <&l3init_clkctrl OMAP5_OCP2SCP3_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00010000 0x00004000>, - <0x00004000 0x00014000 0x00001000>, - <0x00005000 0x00015000 0x00001000>, - <0x00006000 0x00016000 0x00001000>, - <0x00007000 0x00017000 0x00001000>; - - ocp2scp@0 { - compatible = "ti,omap-ocp2scp"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x0 0x20>; - }; - - sata_phy: phy@6000 { - compatible = "ti,phy-pipe3-sata"; - reg = <0x6000 0x80>, /* phy_rx */ - <0x6400 0x64>, /* phy_tx */ - <0x6800 0x40>; /* pll_ctrl */ - reg-names = "phy_rx", "phy_tx", "pll_ctrl"; - syscon-phy-power = <&scm_conf 0x374>; - clocks = <&sys_clkin>, - <&l3init_clkctrl OMAP5_SATA_CLKCTRL 8>; - clock-names = "sysclk", "refclk"; - #phy-cells = <0>; - }; - }; - - target-module@20000 { /* 0x4a0a0000, ap 95 50.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00020000 0x00004000>, - <0x00004000 0x00024000 0x00001000>, - <0x00005000 0x00025000 0x00001000>, - <0x00006000 0x00026000 0x00001000>, - <0x00007000 0x00027000 0x00001000>; - }; - - target-module@36000 { /* 0x4a0b6000, ap 65 6c.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x36000 0x1000>; - }; - - target-module@4d000 { /* 0x4a0cd000, ap 67 64.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x4d000 0x1000>; - }; - - target-module@59000 { /* 0x4a0d9000, ap 13 20.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x59000 0x1000>; - }; - - target-module@5b000 { /* 0x4a0db000, ap 15 10.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x5b000 0x1000>; - }; - - target-module@5d000 { /* 0x4a0dd000, ap 17 18.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x5d000 0x1000>; - }; - - target-module@60000 { /* 0x4a0e0000, ap 19 54.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x60000 0x1000>; - }; - - target-module@74000 { /* 0x4a0f4000, ap 25 04.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - ti,hwmods = "mailbox"; - reg = <0x74000 0x4>, - <0x74010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - ; - /* Domains (V, P, C): core, core_pwrdm, l4cfg_clkdm */ - clocks = <&l4cfg_clkctrl OMAP5_MAILBOX_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x74000 0x1000>; - - mailbox: mailbox@0 { - compatible = "ti,omap4-mailbox"; - reg = <0x0 0x200>; - interrupts = ; - #mbox-cells = <1>; - ti,mbox-num-users = <3>; - ti,mbox-num-fifos = <8>; - mbox_ipu: mbox_ipu { - ti,mbox-tx = <0 0 0>; - ti,mbox-rx = <1 0 0>; - }; - mbox_dsp: mbox_dsp { - ti,mbox-tx = <3 0 0>; - ti,mbox-rx = <2 0 0>; - }; - }; - }; - - target-module@76000 { /* 0x4a0f6000, ap 27 0c.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "spinlock"; - reg = <0x76000 0x4>, - <0x76010 0x4>, - <0x76014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, core_pwrdm, l4cfg_clkdm */ - clocks = <&l4cfg_clkctrl OMAP5_SPINLOCK_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x76000 0x1000>; - - hwspinlock: spinlock@0 { - compatible = "ti,omap4-hwspinlock"; - reg = <0x0 0x1000>; - #hwlock-cells = <1>; - }; - }; - }; - - segment@100000 { /* 0x4a100000 */ - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00002000 0x00102000 0x001000>, /* ap 59 */ - <0x00003000 0x00103000 0x001000>, /* ap 60 */ - <0x00008000 0x00108000 0x001000>, /* ap 61 */ - <0x00009000 0x00109000 0x001000>, /* ap 62 */ - <0x0000a000 0x0010a000 0x001000>, /* ap 63 */ - <0x0000b000 0x0010b000 0x001000>, /* ap 64 */ - <0x00040000 0x00140000 0x010000>, /* ap 101 */ - <0x00050000 0x00150000 0x001000>; /* ap 102 */ - - target-module@2000 { /* 0x4a102000, ap 59 2c.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2000 0x1000>; - }; - - target-module@8000 { /* 0x4a108000, ap 61 26.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x8000 0x1000>; - }; - - target-module@a000 { /* 0x4a10a000, ap 63 22.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xa000 0x1000>; - }; - - target-module@40000 { /* 0x4a140000, ap 101 16.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x40000 0x10000>; - }; - }; - - segment@180000 { /* 0x4a180000 */ - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - }; - - segment@200000 { /* 0x4a200000 */ - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0001e000 0x0021e000 0x001000>, /* ap 29 */ - <0x0001f000 0x0021f000 0x001000>, /* ap 30 */ - <0x0000a000 0x0020a000 0x001000>, /* ap 31 */ - <0x0000b000 0x0020b000 0x001000>, /* ap 32 */ - <0x00006000 0x00206000 0x001000>, /* ap 33 */ - <0x00007000 0x00207000 0x001000>, /* ap 34 */ - <0x00004000 0x00204000 0x001000>, /* ap 35 */ - <0x00005000 0x00205000 0x001000>, /* ap 36 */ - <0x00012000 0x00212000 0x001000>, /* ap 37 */ - <0x00013000 0x00213000 0x001000>, /* ap 38 */ - <0x0000c000 0x0020c000 0x001000>, /* ap 39 */ - <0x0000d000 0x0020d000 0x001000>, /* ap 40 */ - <0x00010000 0x00210000 0x001000>, /* ap 41 */ - <0x00011000 0x00211000 0x001000>, /* ap 42 */ - <0x00016000 0x00216000 0x001000>, /* ap 43 */ - <0x00017000 0x00217000 0x001000>, /* ap 44 */ - <0x00014000 0x00214000 0x001000>, /* ap 45 */ - <0x00015000 0x00215000 0x001000>, /* ap 46 */ - <0x00018000 0x00218000 0x001000>, /* ap 47 */ - <0x00019000 0x00219000 0x001000>, /* ap 48 */ - <0x00020000 0x00220000 0x001000>, /* ap 49 */ - <0x00021000 0x00221000 0x001000>, /* ap 50 */ - <0x00026000 0x00226000 0x001000>, /* ap 51 */ - <0x00027000 0x00227000 0x001000>, /* ap 52 */ - <0x00028000 0x00228000 0x001000>, /* ap 53 */ - <0x00029000 0x00229000 0x001000>, /* ap 54 */ - <0x0002a000 0x0022a000 0x001000>, /* ap 55 */ - <0x0002b000 0x0022b000 0x001000>, /* ap 56 */ - <0x0001c000 0x0021c000 0x001000>, /* ap 57 */ - <0x0001d000 0x0021d000 0x001000>, /* ap 58 */ - <0x0001a000 0x0021a000 0x001000>, /* ap 73 */ - <0x0001b000 0x0021b000 0x001000>, /* ap 74 */ - <0x00024000 0x00224000 0x001000>, /* ap 75 */ - <0x00025000 0x00225000 0x001000>, /* ap 76 */ - <0x00002000 0x00202000 0x001000>, /* ap 103 */ - <0x00003000 0x00203000 0x001000>, /* ap 104 */ - <0x00008000 0x00208000 0x001000>, /* ap 105 */ - <0x00009000 0x00209000 0x001000>, /* ap 106 */ - <0x00022000 0x00222000 0x001000>, /* ap 107 */ - <0x00023000 0x00223000 0x001000>; /* ap 108 */ - - target-module@2000 { /* 0x4a202000, ap 103 3c.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2000 0x1000>; - }; - - target-module@4000 { /* 0x4a204000, ap 35 46.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x4000 0x1000>; - }; - - target-module@6000 { /* 0x4a206000, ap 33 4e.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x6000 0x1000>; - }; - - target-module@8000 { /* 0x4a208000, ap 105 34.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x8000 0x1000>; - }; - - target-module@a000 { /* 0x4a20a000, ap 31 30.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xa000 0x1000>; - }; - - target-module@c000 { /* 0x4a20c000, ap 39 14.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xc000 0x1000>; - }; - - target-module@10000 { /* 0x4a210000, ap 41 56.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x10000 0x1000>; - }; - - target-module@12000 { /* 0x4a212000, ap 37 52.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x12000 0x1000>; - }; - - target-module@14000 { /* 0x4a214000, ap 45 1c.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x14000 0x1000>; - }; - - target-module@16000 { /* 0x4a216000, ap 43 42.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x16000 0x1000>; - }; - - target-module@18000 { /* 0x4a218000, ap 47 1a.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x18000 0x1000>; - }; - - target-module@1a000 { /* 0x4a21a000, ap 73 3e.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x1a000 0x1000>; - }; - - target-module@1c000 { /* 0x4a21c000, ap 57 40.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x1c000 0x1000>; - }; - - target-module@1e000 { /* 0x4a21e000, ap 29 12.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x1e000 0x1000>; - }; - - target-module@20000 { /* 0x4a220000, ap 49 4a.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x20000 0x1000>; - }; - - target-module@22000 { /* 0x4a222000, ap 107 3a.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x22000 0x1000>; - }; - - target-module@24000 { /* 0x4a224000, ap 75 48.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x24000 0x1000>; - }; - - target-module@26000 { /* 0x4a226000, ap 51 24.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x26000 0x1000>; - }; - - target-module@28000 { /* 0x4a228000, ap 53 38.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x28000 0x1000>; - }; - - target-module@2a000 { /* 0x4a22a000, ap 55 5a.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2a000 0x1000>; - }; - }; - - segment@280000 { /* 0x4a280000 */ - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - }; - - segment@300000 { /* 0x4a300000 */ - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - }; -}; - -&l4_per { /* 0x48000000 */ - compatible = "ti,omap5-l4-per", "simple-bus"; - reg = <0x48000000 0x800>, - <0x48000800 0x800>, - <0x48001000 0x400>, - <0x48001400 0x400>, - <0x48001800 0x400>, - <0x48001c00 0x400>; - reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x48000000 0x200000>, /* segment 0 */ - <0x00200000 0x48200000 0x200000>; /* segment 1 */ - - segment@0 { /* 0x48000000 */ - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ - <0x00001000 0x00001000 0x000400>, /* ap 1 */ - <0x00000800 0x00000800 0x000800>, /* ap 2 */ - <0x00020000 0x00020000 0x001000>, /* ap 3 */ - <0x00021000 0x00021000 0x001000>, /* ap 4 */ - <0x00032000 0x00032000 0x001000>, /* ap 5 */ - <0x00033000 0x00033000 0x001000>, /* ap 6 */ - <0x00034000 0x00034000 0x001000>, /* ap 7 */ - <0x00035000 0x00035000 0x001000>, /* ap 8 */ - <0x00036000 0x00036000 0x001000>, /* ap 9 */ - <0x00037000 0x00037000 0x001000>, /* ap 10 */ - <0x0003e000 0x0003e000 0x001000>, /* ap 11 */ - <0x0003f000 0x0003f000 0x001000>, /* ap 12 */ - <0x00055000 0x00055000 0x001000>, /* ap 13 */ - <0x00056000 0x00056000 0x001000>, /* ap 14 */ - <0x00057000 0x00057000 0x001000>, /* ap 15 */ - <0x00058000 0x00058000 0x001000>, /* ap 16 */ - <0x00059000 0x00059000 0x001000>, /* ap 17 */ - <0x0005a000 0x0005a000 0x001000>, /* ap 18 */ - <0x0005b000 0x0005b000 0x001000>, /* ap 19 */ - <0x0005c000 0x0005c000 0x001000>, /* ap 20 */ - <0x0005d000 0x0005d000 0x001000>, /* ap 21 */ - <0x0005e000 0x0005e000 0x001000>, /* ap 22 */ - <0x00060000 0x00060000 0x001000>, /* ap 23 */ - <0x0006a000 0x0006a000 0x001000>, /* ap 24 */ - <0x0006b000 0x0006b000 0x001000>, /* ap 25 */ - <0x0006c000 0x0006c000 0x001000>, /* ap 26 */ - <0x0006d000 0x0006d000 0x001000>, /* ap 27 */ - <0x0006e000 0x0006e000 0x001000>, /* ap 28 */ - <0x0006f000 0x0006f000 0x001000>, /* ap 29 */ - <0x00070000 0x00070000 0x001000>, /* ap 30 */ - <0x00071000 0x00071000 0x001000>, /* ap 31 */ - <0x00072000 0x00072000 0x001000>, /* ap 32 */ - <0x00073000 0x00073000 0x001000>, /* ap 33 */ - <0x00061000 0x00061000 0x001000>, /* ap 34 */ - <0x00053000 0x00053000 0x001000>, /* ap 35 */ - <0x00054000 0x00054000 0x001000>, /* ap 36 */ - <0x000b2000 0x000b2000 0x001000>, /* ap 37 */ - <0x000b3000 0x000b3000 0x001000>, /* ap 38 */ - <0x00078000 0x00078000 0x001000>, /* ap 39 */ - <0x00079000 0x00079000 0x001000>, /* ap 40 */ - <0x00086000 0x00086000 0x001000>, /* ap 41 */ - <0x00087000 0x00087000 0x001000>, /* ap 42 */ - <0x00088000 0x00088000 0x001000>, /* ap 43 */ - <0x00089000 0x00089000 0x001000>, /* ap 44 */ - <0x00051000 0x00051000 0x001000>, /* ap 45 */ - <0x00052000 0x00052000 0x001000>, /* ap 46 */ - <0x00098000 0x00098000 0x001000>, /* ap 47 */ - <0x00099000 0x00099000 0x001000>, /* ap 48 */ - <0x0009a000 0x0009a000 0x001000>, /* ap 49 */ - <0x0009b000 0x0009b000 0x001000>, /* ap 50 */ - <0x0009c000 0x0009c000 0x001000>, /* ap 51 */ - <0x0009d000 0x0009d000 0x001000>, /* ap 52 */ - <0x00068000 0x00068000 0x001000>, /* ap 53 */ - <0x00069000 0x00069000 0x001000>, /* ap 54 */ - <0x00090000 0x00090000 0x002000>, /* ap 55 */ - <0x00092000 0x00092000 0x001000>, /* ap 56 */ - <0x000a4000 0x000a4000 0x001000>, /* ap 57 */ - <0x000a6000 0x000a6000 0x001000>, /* ap 58 */ - <0x000a8000 0x000a8000 0x004000>, /* ap 59 */ - <0x000ac000 0x000ac000 0x001000>, /* ap 60 */ - <0x000ad000 0x000ad000 0x001000>, /* ap 61 */ - <0x000ae000 0x000ae000 0x001000>, /* ap 62 */ - <0x00066000 0x00066000 0x001000>, /* ap 63 */ - <0x00067000 0x00067000 0x001000>, /* ap 64 */ - <0x000b4000 0x000b4000 0x001000>, /* ap 65 */ - <0x000b5000 0x000b5000 0x001000>, /* ap 66 */ - <0x000b8000 0x000b8000 0x001000>, /* ap 67 */ - <0x000b9000 0x000b9000 0x001000>, /* ap 68 */ - <0x000ba000 0x000ba000 0x001000>, /* ap 69 */ - <0x000bb000 0x000bb000 0x001000>, /* ap 70 */ - <0x000d1000 0x000d1000 0x001000>, /* ap 71 */ - <0x000d2000 0x000d2000 0x001000>, /* ap 72 */ - <0x000d5000 0x000d5000 0x001000>, /* ap 73 */ - <0x000d6000 0x000d6000 0x001000>, /* ap 74 */ - <0x000a2000 0x000a2000 0x001000>, /* ap 75 */ - <0x000a3000 0x000a3000 0x001000>, /* ap 76 */ - <0x00001400 0x00001400 0x000400>, /* ap 77 */ - <0x00001800 0x00001800 0x000400>, /* ap 78 */ - <0x00001c00 0x00001c00 0x000400>, /* ap 79 */ - <0x000a5000 0x000a5000 0x001000>, /* ap 80 */ - <0x0007a000 0x0007a000 0x001000>, /* ap 81 */ - <0x0007b000 0x0007b000 0x001000>, /* ap 82 */ - <0x0007c000 0x0007c000 0x001000>, /* ap 83 */ - <0x0007d000 0x0007d000 0x001000>; /* ap 84 */ - - target-module@20000 { /* 0x48020000, ap 3 04.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "uart3"; - reg = <0x20050 0x4>, - <0x20054 0x4>, - <0x20058 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_UART3_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x20000 0x1000>; - - uart3: serial@0 { - compatible = "ti,omap4-uart"; - reg = <0x0 0x100>; - interrupts = ; - clock-frequency = <48000000>; - }; - }; - - target-module@32000 { /* 0x48032000, ap 5 3e.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - ti,hwmods = "timer2"; - reg = <0x32000 0x4>, - <0x32010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_TIMER2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x32000 0x1000>; - - timer2: timer@0 { - compatible = "ti,omap5430-timer"; - reg = <0x0 0x80>; - clocks = <&l4per_clkctrl OMAP5_TIMER2_CLKCTRL 24>; - clock-names = "fck"; - interrupts = ; - }; - }; - - target-module@34000 { /* 0x48034000, ap 7 46.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - ti,hwmods = "timer3"; - reg = <0x34000 0x4>, - <0x34010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_TIMER3_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x34000 0x1000>; - - timer3: timer@0 { - compatible = "ti,omap5430-timer"; - reg = <0x0 0x80>; - clocks = <&l4per_clkctrl OMAP5_TIMER3_CLKCTRL 24>; - clock-names = "fck"; - interrupts = ; - }; - }; - - target-module@36000 { /* 0x48036000, ap 9 4e.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - ti,hwmods = "timer4"; - reg = <0x36000 0x4>, - <0x36010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_TIMER4_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x36000 0x1000>; - - timer4: timer@0 { - compatible = "ti,omap5430-timer"; - reg = <0x0 0x80>; - clocks = <&l4per_clkctrl OMAP5_TIMER4_CLKCTRL 24>; - clock-names = "fck"; - interrupts = ; - }; - }; - - target-module@3e000 { /* 0x4803e000, ap 11 56.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - ti,hwmods = "timer9"; - reg = <0x3e000 0x4>, - <0x3e010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_TIMER9_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x3e000 0x1000>; - - timer9: timer@0 { - compatible = "ti,omap5430-timer"; - reg = <0x0 0x80>; - clocks = <&l4per_clkctrl OMAP5_TIMER9_CLKCTRL 24>; - clock-names = "fck"; - interrupts = ; - ti,timer-pwm; - }; - }; - - target-module@51000 { /* 0x48051000, ap 45 2e.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "gpio7"; - reg = <0x51000 0x4>, - <0x51010 0x4>, - <0x51114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_GPIO7_CLKCTRL 0>, - <&l4per_clkctrl OMAP5_GPIO7_CLKCTRL 8>; - clock-names = "fck", "dbclk"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x51000 0x1000>; - - gpio7: gpio@0 { - compatible = "ti,omap4-gpio"; - reg = <0x0 0x200>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - target-module@53000 { /* 0x48053000, ap 35 36.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "gpio8"; - reg = <0x53000 0x4>, - <0x53010 0x4>, - <0x53114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_GPIO8_CLKCTRL 0>, - <&l4per_clkctrl OMAP5_GPIO8_CLKCTRL 8>; - clock-names = "fck", "dbclk"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x53000 0x1000>; - - gpio8: gpio@0 { - compatible = "ti,omap4-gpio"; - reg = <0x0 0x200>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - target-module@55000 { /* 0x48055000, ap 13 0e.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "gpio2"; - reg = <0x55000 0x4>, - <0x55010 0x4>, - <0x55114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_GPIO2_CLKCTRL 0>, - <&l4per_clkctrl OMAP5_GPIO2_CLKCTRL 8>; - clock-names = "fck", "dbclk"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x55000 0x1000>; - - gpio2: gpio@0 { - compatible = "ti,omap4-gpio"; - reg = <0x0 0x200>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - target-module@57000 { /* 0x48057000, ap 15 06.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "gpio3"; - reg = <0x57000 0x4>, - <0x57010 0x4>, - <0x57114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_GPIO3_CLKCTRL 0>, - <&l4per_clkctrl OMAP5_GPIO3_CLKCTRL 8>; - clock-names = "fck", "dbclk"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x57000 0x1000>; - - gpio3: gpio@0 { - compatible = "ti,omap4-gpio"; - reg = <0x0 0x200>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - target-module@59000 { /* 0x48059000, ap 17 16.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "gpio4"; - reg = <0x59000 0x4>, - <0x59010 0x4>, - <0x59114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_GPIO4_CLKCTRL 0>, - <&l4per_clkctrl OMAP5_GPIO4_CLKCTRL 8>; - clock-names = "fck", "dbclk"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x59000 0x1000>; - - gpio4: gpio@0 { - compatible = "ti,omap4-gpio"; - reg = <0x0 0x200>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - target-module@5b000 { /* 0x4805b000, ap 19 1e.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "gpio5"; - reg = <0x5b000 0x4>, - <0x5b010 0x4>, - <0x5b114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_GPIO5_CLKCTRL 0>, - <&l4per_clkctrl OMAP5_GPIO5_CLKCTRL 8>; - clock-names = "fck", "dbclk"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x5b000 0x1000>; - - gpio5: gpio@0 { - compatible = "ti,omap4-gpio"; - reg = <0x0 0x200>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - target-module@5d000 { /* 0x4805d000, ap 21 26.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "gpio6"; - reg = <0x5d000 0x4>, - <0x5d010 0x4>, - <0x5d114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_GPIO6_CLKCTRL 0>, - <&l4per_clkctrl OMAP5_GPIO6_CLKCTRL 8>; - clock-names = "fck", "dbclk"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x5d000 0x1000>; - - gpio6: gpio@0 { - compatible = "ti,omap4-gpio"; - reg = <0x0 0x200>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - target-module@60000 { /* 0x48060000, ap 23 24.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "i2c3"; - reg = <0x60000 0x8>, - <0x60010 0x8>, - <0x60090 0x8>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_I2C3_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x60000 0x1000>; - - i2c3: i2c@0 { - compatible = "ti,omap4-i2c"; - reg = <0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - target-module@66000 { /* 0x48066000, ap 63 4c.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "uart5"; - reg = <0x66050 0x4>, - <0x66054 0x4>, - <0x66058 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_UART5_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x66000 0x1000>; - - uart5: serial@0 { - compatible = "ti,omap4-uart"; - reg = <0x0 0x100>; - interrupts = ; - clock-frequency = <48000000>; - }; - }; - - target-module@68000 { /* 0x48068000, ap 53 54.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "uart6"; - reg = <0x68050 0x4>, - <0x68054 0x4>, - <0x68058 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_UART6_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x68000 0x1000>; - - uart6: serial@0 { - compatible = "ti,omap4-uart"; - reg = <0x0 0x100>; - interrupts = ; - clock-frequency = <48000000>; - }; - }; - - target-module@6a000 { /* 0x4806a000, ap 24 0a.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "uart1"; - reg = <0x6a050 0x4>, - <0x6a054 0x4>, - <0x6a058 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_UART1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x6a000 0x1000>; - - uart1: serial@0 { - compatible = "ti,omap4-uart"; - reg = <0x0 0x100>; - interrupts = ; - clock-frequency = <48000000>; - }; - }; - - target-module@6c000 { /* 0x4806c000, ap 26 22.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "uart2"; - reg = <0x6c050 0x4>, - <0x6c054 0x4>, - <0x6c058 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_UART2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x6c000 0x1000>; - - uart2: serial@0 { - compatible = "ti,omap4-uart"; - reg = <0x0 0x100>; - interrupts = ; - clock-frequency = <48000000>; - }; - }; - - target-module@6e000 { /* 0x4806e000, ap 28 44.1 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "uart4"; - reg = <0x6e050 0x4>, - <0x6e054 0x4>, - <0x6e058 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_UART4_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x6e000 0x1000>; - - uart4: serial@0 { - compatible = "ti,omap4-uart"; - reg = <0x0 0x100>; - interrupts = ; - clock-frequency = <48000000>; - }; - }; - - target-module@70000 { /* 0x48070000, ap 30 14.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "i2c1"; - reg = <0x70000 0x8>, - <0x70010 0x8>, - <0x70090 0x8>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_I2C1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x70000 0x1000>; - - i2c1: i2c@0 { - compatible = "ti,omap4-i2c"; - reg = <0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - target-module@72000 { /* 0x48072000, ap 32 1c.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "i2c2"; - reg = <0x72000 0x8>, - <0x72010 0x8>, - <0x72090 0x8>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_I2C2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x72000 0x1000>; - - i2c2: i2c@0 { - compatible = "ti,omap4-i2c"; - reg = <0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - target-module@78000 { /* 0x48078000, ap 39 12.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x78000 0x1000>; - }; - - target-module@7a000 { /* 0x4807a000, ap 81 2c.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "i2c4"; - reg = <0x7a000 0x8>, - <0x7a010 0x8>, - <0x7a090 0x8>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_I2C4_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x7a000 0x1000>; - - i2c4: i2c@0 { - compatible = "ti,omap4-i2c"; - reg = <0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - target-module@7c000 { /* 0x4807c000, ap 83 34.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "i2c5"; - reg = <0x7c000 0x8>, - <0x7c010 0x8>, - <0x7c090 0x8>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_I2C5_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x7c000 0x1000>; - - i2c5: i2c@0 { - compatible = "ti,omap4-i2c"; - reg = <0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - target-module@86000 { /* 0x48086000, ap 41 5e.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - ti,hwmods = "timer10"; - reg = <0x86000 0x4>, - <0x86010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_TIMER10_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x86000 0x1000>; - - timer10: timer@0 { - compatible = "ti,omap5430-timer"; - reg = <0x0 0x80>; - clocks = <&l4per_clkctrl OMAP5_TIMER10_CLKCTRL 24>; - clock-names = "fck"; - interrupts = ; - ti,timer-pwm; - }; - }; - - target-module@88000 { /* 0x48088000, ap 43 66.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - ti,hwmods = "timer11"; - reg = <0x88000 0x4>, - <0x88010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_TIMER11_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x88000 0x1000>; - - timer11: timer@0 { - compatible = "ti,omap5430-timer"; - reg = <0x0 0x80>; - clocks = <&l4per_clkctrl OMAP5_TIMER11_CLKCTRL 24>; - clock-names = "fck"; - interrupts = ; - ti,timer-pwm; - }; - }; - - target-module@90000 { /* 0x48090000, ap 55 1a.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x90000 0x2000>; - }; - - target-module@98000 { /* 0x48098000, ap 47 08.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - ti,hwmods = "mcspi1"; - reg = <0x98000 0x4>, - <0x98010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_MCSPI1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x98000 0x1000>; - - mcspi1: spi@0 { - compatible = "ti,omap4-mcspi"; - reg = <0x0 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - ti,spi-num-cs = <4>; - dmas = <&sdma 35>, - <&sdma 36>, - <&sdma 37>, - <&sdma 38>, - <&sdma 39>, - <&sdma 40>, - <&sdma 41>, - <&sdma 42>; - dma-names = "tx0", "rx0", "tx1", "rx1", - "tx2", "rx2", "tx3", "rx3"; - }; - }; - - target-module@9a000 { /* 0x4809a000, ap 49 10.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - ti,hwmods = "mcspi2"; - reg = <0x9a000 0x4>, - <0x9a010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_MCSPI2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x9a000 0x1000>; - - mcspi2: spi@0 { - compatible = "ti,omap4-mcspi"; - reg = <0x0 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - ti,spi-num-cs = <2>; - dmas = <&sdma 43>, - <&sdma 44>, - <&sdma 45>, - <&sdma 46>; - dma-names = "tx0", "rx0", "tx1", "rx1"; - }; - }; - - target-module@9c000 { /* 0x4809c000, ap 51 3a.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - ti,hwmods = "mmc1"; - reg = <0x9c000 0x4>, - <0x9c010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-midle = , - , - , - ; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */ - clocks = <&l3init_clkctrl OMAP5_MMC1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x9c000 0x1000>; - - mmc1: mmc@0 { - compatible = "ti,omap4-hsmmc"; - reg = <0x0 0x400>; - interrupts = ; - ti,dual-volt; - ti,needs-special-reset; - dmas = <&sdma 61>, <&sdma 62>; - dma-names = "tx", "rx"; - pbias-supply = <&pbias_mmc_reg>; - }; - }; - - target-module@a2000 { /* 0x480a2000, ap 75 02.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xa2000 0x1000>; - }; - - target-module@a4000 { /* 0x480a4000, ap 57 3c.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x000a4000 0x00001000>, - <0x00001000 0x000a5000 0x00001000>; - }; - - target-module@a8000 { /* 0x480a8000, ap 59 2a.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xa8000 0x4000>; - }; - - target-module@ad000 { /* 0x480ad000, ap 61 20.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - ti,hwmods = "mmc3"; - reg = <0xad000 0x4>, - <0xad010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-midle = , - , - , - ; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_MMC3_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xad000 0x1000>; - - mmc3: mmc@0 { - compatible = "ti,omap4-hsmmc"; - reg = <0x0 0x400>; - interrupts = ; - ti,needs-special-reset; - dmas = <&sdma 77>, <&sdma 78>; - dma-names = "tx", "rx"; - }; - }; - - target-module@b2000 { /* 0x480b2000, ap 37 0c.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xb2000 0x1000>; - }; - - target-module@b4000 { /* 0x480b4000, ap 65 42.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - ti,hwmods = "mmc2"; - reg = <0xb4000 0x4>, - <0xb4010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-midle = , - , - , - ; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */ - clocks = <&l3init_clkctrl OMAP5_MMC2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xb4000 0x1000>; - - mmc2: mmc@0 { - compatible = "ti,omap4-hsmmc"; - reg = <0x0 0x400>; - interrupts = ; - ti,needs-special-reset; - dmas = <&sdma 47>, <&sdma 48>; - dma-names = "tx", "rx"; - }; - }; - - target-module@b8000 { /* 0x480b8000, ap 67 32.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - ti,hwmods = "mcspi3"; - reg = <0xb8000 0x4>, - <0xb8010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_MCSPI3_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xb8000 0x1000>; - - mcspi3: spi@0 { - compatible = "ti,omap4-mcspi"; - reg = <0x0 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - ti,spi-num-cs = <2>; - dmas = <&sdma 15>, <&sdma 16>; - dma-names = "tx0", "rx0"; - }; - }; - - target-module@ba000 { /* 0x480ba000, ap 69 18.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - ti,hwmods = "mcspi4"; - reg = <0xba000 0x4>, - <0xba010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_MCSPI4_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xba000 0x1000>; - - mcspi4: spi@0 { - compatible = "ti,omap4-mcspi"; - reg = <0x0 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - ti,spi-num-cs = <1>; - dmas = <&sdma 70>, <&sdma 71>; - dma-names = "tx0", "rx0"; - }; - }; - - target-module@d1000 { /* 0x480d1000, ap 71 28.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - ti,hwmods = "mmc4"; - reg = <0xd1000 0x4>, - <0xd1010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-midle = , - , - , - ; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_MMC4_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xd1000 0x1000>; - - mmc4: mmc@0 { - compatible = "ti,omap4-hsmmc"; - reg = <0x0 0x400>; - interrupts = ; - ti,needs-special-reset; - dmas = <&sdma 57>, <&sdma 58>; - dma-names = "tx", "rx"; - }; - }; - - target-module@d5000 { /* 0x480d5000, ap 73 30.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - ti,hwmods = "mmc5"; - reg = <0xd5000 0x4>, - <0xd5010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-midle = , - , - , - ; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_MMC5_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xd5000 0x1000>; - - mmc5: mmc@0 { - compatible = "ti,omap4-hsmmc"; - reg = <0x0 0x400>; - interrupts = ; - ti,needs-special-reset; - dmas = <&sdma 59>, <&sdma 60>; - dma-names = "tx", "rx"; - }; - }; - }; - - segment@200000 { /* 0x48200000 */ - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - }; -}; - -&l4_wkup { /* 0x4ae00000 */ - compatible = "ti,omap5-l4-wkup", "simple-bus"; - reg = <0x4ae00000 0x800>, - <0x4ae00800 0x800>, - <0x4ae01000 0x1000>; - reg-names = "ap", "la", "ia0"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x4ae00000 0x010000>, /* segment 0 */ - <0x00010000 0x4ae10000 0x010000>, /* segment 1 */ - <0x00020000 0x4ae20000 0x010000>; /* segment 2 */ - - segment@0 { /* 0x4ae00000 */ - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ - <0x00001000 0x00001000 0x001000>, /* ap 1 */ - <0x00000800 0x00000800 0x000800>, /* ap 2 */ - <0x00006000 0x00006000 0x002000>, /* ap 3 */ - <0x00008000 0x00008000 0x001000>, /* ap 4 */ - <0x0000a000 0x0000a000 0x001000>, /* ap 15 */ - <0x0000b000 0x0000b000 0x001000>, /* ap 16 */ - <0x00004000 0x00004000 0x001000>, /* ap 17 */ - <0x00005000 0x00005000 0x001000>, /* ap 18 */ - <0x0000c000 0x0000c000 0x001000>, /* ap 19 */ - <0x0000d000 0x0000d000 0x001000>; /* ap 20 */ - - target-module@4000 { /* 0x4ae04000, ap 17 20.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "counter_32k"; - reg = <0x4000 0x4>, - <0x4010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-sidle = , - ; - /* Domains (V, P, C): wkup, wkupaon_pwrdm, wkupaon_clkdm */ - clocks = <&wkupaon_clkctrl OMAP5_COUNTER_32K_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x4000 0x1000>; - - counter32k: counter@0 { - compatible = "ti,omap-counter32k"; - reg = <0x0 0x40>; - }; - }; - - target-module@6000 { /* 0x4ae06000, ap 3 08.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x6000 0x4>; - reg-names = "rev"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x6000 0x2000>; - - prm: prm@0 { - compatible = "ti,omap5-prm", "simple-bus"; - reg = <0x0 0x2000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x2000>; - - prm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - prm_clockdomains: clockdomains { - }; - }; - }; - - target-module@a000 { /* 0x4ae0a000, ap 15 2c.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0xa000 0x4>; - reg-names = "rev"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xa000 0x1000>; - - scrm: scrm@0 { - compatible = "ti,omap5-scrm"; - reg = <0x0 0x1000>; - - scrm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - scrm_clockdomains: clockdomains { - }; - }; - }; - - target-module@c000 { /* 0x4ae0c000, ap 19 28.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0xc000 0x4>; - reg-names = "rev"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xc000 0x1000>; - - omap5_pmx_wkup: pinmux@840 { - compatible = "ti,omap5-padconf", - "pinctrl-single"; - reg = <0x840 0x003c>; - #address-cells = <1>; - #size-cells = <0>; - #pinctrl-cells = <1>; - #interrupt-cells = <1>; - interrupt-controller; - pinctrl-single,register-width = <16>; - pinctrl-single,function-mask = <0x7fff>; - }; - - omap5_scm_wkup_pad_conf: omap5_scm_wkup_pad_conf@da0 { - compatible = "ti,omap5-scm-wkup-pad-conf", - "simple-bus"; - reg = <0xda0 0x60>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x60>; - - scm_wkup_pad_conf: scm_conf@0 { - compatible = "syscon", "simple-bus"; - reg = <0x0 0x60>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x0 0x60>; - - scm_wkup_pad_conf_clocks: clocks@0 { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - }; - }; - }; - - segment@10000 { /* 0x4ae10000 */ - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00010000 0x001000>, /* ap 5 */ - <0x00001000 0x00011000 0x001000>, /* ap 6 */ - <0x00004000 0x00014000 0x001000>, /* ap 7 */ - <0x00005000 0x00015000 0x001000>, /* ap 8 */ - <0x00008000 0x00018000 0x001000>, /* ap 9 */ - <0x00009000 0x00019000 0x001000>, /* ap 10 */ - <0x0000c000 0x0001c000 0x001000>, /* ap 11 */ - <0x0000d000 0x0001d000 0x001000>; /* ap 12 */ - - target-module@0 { /* 0x4ae10000, ap 5 10.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "gpio1"; - reg = <0x0 0x4>, - <0x10 0x4>, - <0x114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): wkup, wkupaon_pwrdm, wkupaon_clkdm */ - clocks = <&wkupaon_clkctrl OMAP5_GPIO1_CLKCTRL 0>, - <&wkupaon_clkctrl OMAP5_GPIO1_CLKCTRL 8>; - clock-names = "fck", "dbclk"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x1000>; - - gpio1: gpio@0 { - compatible = "ti,omap4-gpio"; - reg = <0x0 0x200>; - interrupts = ; - ti,gpio-always-on; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - target-module@4000 { /* 0x4ae14000, ap 7 14.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "wd_timer2"; - reg = <0x4000 0x4>, - <0x4010 0x4>, - <0x4014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_EMUFREE | - SYSC_OMAP2_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - /* Domains (V, P, C): wkup, wkupaon_pwrdm, wkupaon_clkdm */ - clocks = <&wkupaon_clkctrl OMAP5_WD_TIMER2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x4000 0x1000>; - - wdt2: wdt@0 { - compatible = "ti,omap5-wdt", "ti,omap3-wdt"; - reg = <0x0 0x80>; - interrupts = ; - }; - }; - - target-module@8000 { /* 0x4ae18000, ap 9 18.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - ti,hwmods = "timer1"; - reg = <0x8000 0x4>, - <0x8010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = , - , - , - ; - /* Domains (V, P, C): wkup, wkupaon_pwrdm, wkupaon_clkdm */ - clocks = <&wkupaon_clkctrl OMAP5_TIMER1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x8000 0x1000>; - - timer1: timer@0 { - compatible = "ti,omap5430-timer"; - reg = <0x0 0x80>; - clocks = <&wkupaon_clkctrl OMAP5_TIMER1_CLKCTRL 24>; - clock-names = "fck"; - interrupts = ; - ti,timer-alwon; - }; - }; - - target-module@c000 { /* 0x4ae1c000, ap 11 1c.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "kbd"; - reg = <0xc000 0x4>, - <0xc010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP2_EMUFREE | - SYSC_OMAP2_SOFTRESET)>; - ti,sysc-sidle = , - , - ; - /* Domains (V, P, C): wkup, wkupaon_pwrdm, wkupaon_clkdm */ - clocks = <&wkupaon_clkctrl OMAP5_KBD_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xc000 0x1000>; - - keypad: keypad@0 { - compatible = "ti,omap4-keypad"; - reg = <0x0 0x400>; - }; - }; - }; - - segment@20000 { /* 0x4ae20000 */ - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00006000 0x00026000 0x001000>, /* ap 13 */ - <0x0000a000 0x0002a000 0x001000>, /* ap 14 */ - <0x00000000 0x00020000 0x001000>, /* ap 21 */ - <0x00001000 0x00021000 0x001000>, /* ap 22 */ - <0x00002000 0x00022000 0x001000>, /* ap 23 */ - <0x00003000 0x00023000 0x001000>, /* ap 24 */ - <0x00007000 0x00027000 0x000400>, /* ap 25 */ - <0x00008000 0x00028000 0x000800>, /* ap 26 */ - <0x00009000 0x00029000 0x000100>, /* ap 27 */ - <0x00008800 0x00028800 0x000200>, /* ap 28 */ - <0x00008a00 0x00028a00 0x000100>; /* ap 29 */ - - target-module@0 { /* 0x4ae20000, ap 21 04.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x1000>; - }; - - target-module@2000 { /* 0x4ae22000, ap 23 0c.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2000 0x1000>; - }; - - target-module@6000 { /* 0x4ae26000, ap 13 24.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00006000 0x00001000>, - <0x00001000 0x00007000 0x00000400>, - <0x00002000 0x00008000 0x00000800>, - <0x00002800 0x00008800 0x00000200>, - <0x00002a00 0x00008a00 0x00000100>, - <0x00003000 0x00009000 0x00000100>; - }; - }; -}; - diff --git a/sys/gnu/dts/arm/omap5-sbc-t54.dts b/sys/gnu/dts/arm/omap5-sbc-t54.dts deleted file mode 100644 index 657df46251c..00000000000 --- a/sys/gnu/dts/arm/omap5-sbc-t54.dts +++ /dev/null @@ -1,52 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Suppport for CompuLab CM-T54 on SB-T54 baseboard - */ - -#include "omap5-cm-t54.dts" - -/ { - model = "CompuLab CM-T54 on SB-T54"; - compatible = "compulab,omap5-sbc-t54", "compulab,omap5-cm-t54", "ti,omap5"; -}; - -&omap5_pmx_core { - i2c4_pins: pinmux_i2c4_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x00f8, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_scl */ - OMAP5_IOPAD(0x00fa, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_sda */ - >; - }; - - mmc1_aux_pins: pinmux_mmc1_aux_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x0174, PIN_INPUT_PULLUP | MUX_MODE6) /* timer5_pwm_evt.gpio8_228 */ - OMAP5_IOPAD(0x0176, PIN_INPUT_PULLUP | MUX_MODE6) /* timer6_pwm_evt.gpio8_229 */ - >; - }; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = < - &mmc1_pins - &mmc1_aux_pins - >; - cd-inverted; - wp-inverted; - cd-gpios = <&gpio8 4 GPIO_ACTIVE_LOW>; /* gpio8_228 */ - wp-gpios = <&gpio8 5 GPIO_ACTIVE_LOW>; /* gpio8_229 */ -}; - -&i2c4 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_pins>; - - clock-frequency = <400000>; - - at24@50 { - compatible = "atmel,24c02"; - pagesize = <16>; - reg = <0x50>; - }; -}; diff --git a/sys/gnu/dts/arm/omap5-uevm.dts b/sys/gnu/dts/arm/omap5-uevm.dts deleted file mode 100644 index 9441e9a572a..00000000000 --- a/sys/gnu/dts/arm/omap5-uevm.dts +++ /dev/null @@ -1,200 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ - */ -/dts-v1/; - -#include "omap5-board-common.dtsi" - -/ { - model = "TI OMAP5 uEVM board"; - compatible = "ti,omap5-uevm", "ti,omap5"; - - memory@80000000 { - device_type = "memory"; - reg = <0 0x80000000 0 0x7f000000>; /* 2032 MB */ - }; - - aliases { - ethernet = ðernet; - }; - - leds { - compatible = "gpio-leds"; - led1 { - label = "omap5:blue:usr1"; - gpios = <&gpio5 25 GPIO_ACTIVE_HIGH>; /* gpio5_153 D1 LED */ - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - }; - - evm_keys { - compatible = "gpio-keys"; - - pinctrl-names = "default"; - pinctrl-0 = <&evm_keys_pins>; - - #address-cells = <7>; - #size-cells = <0>; - - btn1 { - label = "BTN1"; - linux,code = <169>; - gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; /* gpio3_83 */ - wakeup-source; - autorepeat; - debounce-interval = <50>; - }; - }; - - evm_leds { - compatible = "gpio-leds"; - - led1 { - label = "omap5:red:led"; - gpios = <&gpio9 17 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc0"; - default-state = "off"; - }; - - led2 { - label = "omap5:green:led"; - gpios = <&gpio9 18 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc1"; - default-state = "off"; - }; - - led3 { - label = "omap5:blue:led"; - gpios = <&gpio9 19 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc2"; - default-state = "off"; - }; - - led4 { - label = "omap5:green:led1"; - gpios = <&gpio9 2 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - - led5 { - label = "omap5:green:led2"; - gpios = <&gpio9 3 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - default-state = "off"; - }; - - led6 { - label = "omap5:green:led3"; - gpios = <&gpio9 4 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - - led7 { - label = "omap5:green:led4"; - gpios = <&gpio9 5 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - default-state = "off"; - }; - - led8 { - label = "omap5:green:led5"; - gpios = <&gpio9 6 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - }; -}; - -&hdmi { - vdda-supply = <&ldo4_reg>; -}; - -&i2c1 { - eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - }; -}; - -&i2c5 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c5_pins>; - - clock-frequency = <400000>; - - gpio9: gpio@22 { - compatible = "ti,tca6424"; - reg = <0x22>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - - cd-gpios = <&gpio5 24 GPIO_ACTIVE_LOW>; /* gpio5_152 */ -}; - -&omap5_pmx_core { - evm_keys_pins: pinmux_evm_keys_gpio_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x0b6, PIN_INPUT | MUX_MODE6) /* gpio3_83 */ - >; - }; - - i2c5_pins: pinmux_i2c5_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x1c6, PIN_INPUT | MUX_MODE0) /* i2c5_scl */ - OMAP5_IOPAD(0x1c8, PIN_INPUT | MUX_MODE0) /* i2c5_sda */ - >; - }; - - mmc1_pins: pinmux_mmc1_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x1d4, PIN_INPUT_PULLUP | MUX_MODE6) /* gpio5_152 */ - >; - }; -}; - -&tpd12s015 { - gpios = <&gpio9 0 GPIO_ACTIVE_HIGH>, /* TCA6424A P01, CT CP HPD */ - <&gpio9 1 GPIO_ACTIVE_HIGH>, /* TCA6424A P00, LS OE */ - <&gpio7 1 GPIO_ACTIVE_HIGH>; /* GPIO 193, HPD */ -}; - -&twl6040 { - ti,audpwron-gpio = <&gpio5 13 GPIO_ACTIVE_HIGH>; /* gpio line 141 */ -}; - -&twl6040_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x1be, PIN_OUTPUT | MUX_MODE6) /* mcspi1_somi.gpio5_141 */ - >; -}; - -&usbhsehci { - #address-cells = <1>; - #size-cells = <0>; - - hub@2 { - compatible = "usb424,3503"; - reg = <2>; - #address-cells = <1>; - #size-cells = <0>; - }; - - ethernet: usbether@3 { - compatible = "usb424,9730"; - reg = <3>; - }; -}; - -&wlcore { - compatible = "ti,wl1837"; -}; diff --git a/sys/gnu/dts/arm/omap5.dtsi b/sys/gnu/dts/arm/omap5.dtsi deleted file mode 100644 index 1fb7937638f..00000000000 --- a/sys/gnu/dts/arm/omap5.dtsi +++ /dev/null @@ -1,437 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ - * - * Based on "omap4.dtsi" - */ - -#include -#include -#include -#include -#include - -/ { - #address-cells = <2>; - #size-cells = <2>; - - compatible = "ti,omap5"; - interrupt-parent = <&wakeupgen>; - chosen { }; - - aliases { - i2c0 = &i2c1; - i2c1 = &i2c2; - i2c2 = &i2c3; - i2c3 = &i2c4; - i2c4 = &i2c5; - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - serial3 = &uart4; - serial4 = &uart5; - serial5 = &uart6; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x0>; - - operating-points = < - /* kHz uV */ - 1000000 1060000 - 1500000 1250000 - >; - - clocks = <&dpll_mpu_ck>; - clock-names = "cpu"; - - clock-latency = <300000>; /* From omap-cpufreq driver */ - - /* cooling options */ - #cooling-cells = <2>; /* min followed by max */ - }; - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x1>; - - operating-points = < - /* kHz uV */ - 1000000 1060000 - 1500000 1250000 - >; - - clocks = <&dpll_mpu_ck>; - clock-names = "cpu"; - - clock-latency = <300000>; /* From omap-cpufreq driver */ - - /* cooling options */ - #cooling-cells = <2>; /* min followed by max */ - }; - }; - - thermal-zones { - #include "omap4-cpu-thermal.dtsi" - #include "omap5-gpu-thermal.dtsi" - #include "omap5-core-thermal.dtsi" - }; - - timer { - compatible = "arm,armv7-timer"; - /* PPI secure/nonsecure IRQ */ - interrupts = , - , - , - ; - interrupt-parent = <&gic>; - }; - - pmu { - compatible = "arm,cortex-a15-pmu"; - interrupts = , - ; - }; - - gic: interrupt-controller@48211000 { - compatible = "arm,cortex-a15-gic"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0 0x48211000 0 0x1000>, - <0 0x48212000 0 0x2000>, - <0 0x48214000 0 0x2000>, - <0 0x48216000 0 0x2000>; - interrupt-parent = <&gic>; - }; - - wakeupgen: interrupt-controller@48281000 { - compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0 0x48281000 0 0x1000>; - interrupt-parent = <&gic>; - }; - - /* - * The soc node represents the soc top level view. It is used for IPs - * that are not memory mapped in the MPU view or for the MPU itself. - */ - soc { - compatible = "ti,omap-infra"; - mpu { - compatible = "ti,omap4-mpu"; - ti,hwmods = "mpu"; - sram = <&ocmcram>; - }; - }; - - /* - * XXX: Use a flat representation of the OMAP3 interconnect. - * The real OMAP interconnect network is quite complex. - * Since it will not bring real advantage to represent that in DT for - * the moment, just use a fake OCP bus entry to represent the whole bus - * hierarchy. - */ - ocp { - compatible = "ti,omap5-l3-noc", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0 0xc0000000>; - ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3"; - reg = <0 0x44000000 0 0x2000>, - <0 0x44800000 0 0x3000>, - <0 0x45000000 0 0x4000>; - interrupts = , - ; - - l4_wkup: interconnect@4ae00000 { - }; - - l4_cfg: interconnect@4a000000 { - }; - - l4_per: interconnect@48000000 { - }; - - l4_abe: interconnect@40100000 { - }; - - ocmcram: ocmcram@40300000 { - compatible = "mmio-sram"; - reg = <0x40300000 0x20000>; /* 128k */ - }; - - gpmc: gpmc@50000000 { - compatible = "ti,omap4430-gpmc"; - reg = <0x50000000 0x1000>; - #address-cells = <2>; - #size-cells = <1>; - interrupts = ; - dmas = <&sdma 4>; - dma-names = "rxtx"; - gpmc,num-cs = <8>; - gpmc,num-waitpins = <4>; - ti,hwmods = "gpmc"; - clocks = <&l3_iclk_div>; - clock-names = "fck"; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - }; - - mmu_dsp: mmu@4a066000 { - compatible = "ti,omap4-iommu"; - reg = <0x4a066000 0x100>; - interrupts = ; - ti,hwmods = "mmu_dsp"; - #iommu-cells = <0>; - }; - - mmu_ipu: mmu@55082000 { - compatible = "ti,omap4-iommu"; - reg = <0x55082000 0x100>; - interrupts = ; - ti,hwmods = "mmu_ipu"; - #iommu-cells = <0>; - ti,iommu-bus-err-back; - }; - - dmm@4e000000 { - compatible = "ti,omap5-dmm"; - reg = <0x4e000000 0x800>; - interrupts = <0 113 0x4>; - ti,hwmods = "dmm"; - }; - - emif1: emif@4c000000 { - compatible = "ti,emif-4d5"; - ti,hwmods = "emif1"; - ti,no-idle-on-init; - phy-type = <2>; /* DDR PHY type: Intelli PHY */ - reg = <0x4c000000 0x400>; - interrupts = ; - hw-caps-read-idle-ctrl; - hw-caps-ll-interface; - hw-caps-temp-alert; - }; - - emif2: emif@4d000000 { - compatible = "ti,emif-4d5"; - ti,hwmods = "emif2"; - ti,no-idle-on-init; - phy-type = <2>; /* DDR PHY type: Intelli PHY */ - reg = <0x4d000000 0x400>; - interrupts = ; - hw-caps-read-idle-ctrl; - hw-caps-ll-interface; - hw-caps-temp-alert; - }; - - bandgap: bandgap@4a0021e0 { - reg = <0x4a0021e0 0xc - 0x4a00232c 0xc - 0x4a002380 0x2c - 0x4a0023C0 0x3c>; - interrupts = ; - compatible = "ti,omap5430-bandgap"; - - #thermal-sensor-cells = <1>; - }; - - /* OCP2SCP3 */ - sata: sata@4a141100 { - compatible = "snps,dwc-ahci"; - reg = <0x4a140000 0x1100>, <0x4a141100 0x7>; - interrupts = ; - phys = <&sata_phy>; - phy-names = "sata-phy"; - clocks = <&l3init_clkctrl OMAP5_SATA_CLKCTRL 8>; - ti,hwmods = "sata"; - ports-implemented = <0x1>; - }; - - target-module@56000000 { - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x5600fe00 0x4>, - <0x5600fe10 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-midle = , - , - ; - ti,sysc-sidle = , - , - ; - clocks = <&gpu_clkctrl OMAP5_GPU_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x56000000 0x2000000>; - - /* - * Closed source PowerVR driver, no child device - * binding or driver in mainline - */ - }; - - dss: dss@58000000 { - compatible = "ti,omap5-dss"; - reg = <0x58000000 0x80>; - status = "disabled"; - ti,hwmods = "dss_core"; - clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - dispc@58001000 { - compatible = "ti,omap5-dispc"; - reg = <0x58001000 0x1000>; - interrupts = ; - ti,hwmods = "dss_dispc"; - clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>; - clock-names = "fck"; - }; - - rfbi: encoder@58002000 { - compatible = "ti,omap5-rfbi"; - reg = <0x58002000 0x100>; - status = "disabled"; - ti,hwmods = "dss_rfbi"; - clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>, <&l3_iclk_div>; - clock-names = "fck", "ick"; - }; - - dsi1: encoder@58004000 { - compatible = "ti,omap5-dsi"; - reg = <0x58004000 0x200>, - <0x58004200 0x40>, - <0x58004300 0x40>; - reg-names = "proto", "phy", "pll"; - interrupts = ; - status = "disabled"; - ti,hwmods = "dss_dsi1"; - clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>, - <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>; - clock-names = "fck", "sys_clk"; - }; - - dsi2: encoder@58005000 { - compatible = "ti,omap5-dsi"; - reg = <0x58009000 0x200>, - <0x58009200 0x40>, - <0x58009300 0x40>; - reg-names = "proto", "phy", "pll"; - interrupts = ; - status = "disabled"; - ti,hwmods = "dss_dsi2"; - clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>, - <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>; - clock-names = "fck", "sys_clk"; - }; - - hdmi: encoder@58060000 { - compatible = "ti,omap5-hdmi"; - reg = <0x58040000 0x200>, - <0x58040200 0x80>, - <0x58040300 0x80>, - <0x58060000 0x19000>; - reg-names = "wp", "pll", "phy", "core"; - interrupts = ; - status = "disabled"; - ti,hwmods = "dss_hdmi"; - clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>, - <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>; - clock-names = "fck", "sys_clk"; - dmas = <&sdma 76>; - dma-names = "audio_tx"; - }; - }; - - abb_mpu: regulator-abb-mpu { - compatible = "ti,abb-v2"; - regulator-name = "abb_mpu"; - #address-cells = <0>; - #size-cells = <0>; - clocks = <&sys_clkin>; - ti,settling-time = <50>; - ti,clock-cycles = <16>; - - reg = <0x4ae07cdc 0x8>, <0x4ae06014 0x4>, - <0x4a0021c4 0x8>, <0x4ae0c318 0x4>; - reg-names = "base-address", "int-address", - "efuse-address", "ldo-address"; - ti,tranxdone-status-mask = <0x80>; - /* LDOVBBMPU_MUX_CTRL */ - ti,ldovbb-override-mask = <0x400>; - /* LDOVBBMPU_VSET_OUT */ - ti,ldovbb-vset-mask = <0x1F>; - - /* - * NOTE: only FBB mode used but actual vset will - * determine final biasing - */ - ti,abb_info = < - /*uV ABB efuse rbb_m fbb_m vset_m*/ - 1060000 0 0x0 0 0x02000000 0x01F00000 - 1250000 0 0x4 0 0x02000000 0x01F00000 - >; - }; - - abb_mm: regulator-abb-mm { - compatible = "ti,abb-v2"; - regulator-name = "abb_mm"; - #address-cells = <0>; - #size-cells = <0>; - clocks = <&sys_clkin>; - ti,settling-time = <50>; - ti,clock-cycles = <16>; - - reg = <0x4ae07ce4 0x8>, <0x4ae06010 0x4>, - <0x4a0021a4 0x8>, <0x4ae0c314 0x4>; - reg-names = "base-address", "int-address", - "efuse-address", "ldo-address"; - ti,tranxdone-status-mask = <0x80000000>; - /* LDOVBBMM_MUX_CTRL */ - ti,ldovbb-override-mask = <0x400>; - /* LDOVBBMM_VSET_OUT */ - ti,ldovbb-vset-mask = <0x1F>; - - /* - * NOTE: only FBB mode used but actual vset will - * determine final biasing - */ - ti,abb_info = < - /*uV ABB efuse rbb_m fbb_m vset_m*/ - 1025000 0 0x0 0 0x02000000 0x01F00000 - 1120000 0 0x4 0 0x02000000 0x01F00000 - >; - }; - }; -}; - -&cpu_thermal { - polling-delay = <500>; /* milliseconds */ - coefficients = <65 (-1791)>; -}; - -#include "omap5-l4.dtsi" -#include "omap54xx-clocks.dtsi" - -&gpu_thermal { - coefficients = <117 (-2992)>; -}; - -&core_thermal { - coefficients = <0 2000>; -}; - -#include "omap5-l4-abe.dtsi" -#include "omap54xx-clocks.dtsi" diff --git a/sys/gnu/dts/arm/omap54xx-clocks.dtsi b/sys/gnu/dts/arm/omap54xx-clocks.dtsi deleted file mode 100644 index 4791834dacb..00000000000 --- a/sys/gnu/dts/arm/omap54xx-clocks.dtsi +++ /dev/null @@ -1,1202 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Device Tree Source for OMAP5 clock data - * - * Copyright (C) 2013 Texas Instruments, Inc. - */ -&cm_core_aon_clocks { - pad_clks_src_ck: pad_clks_src_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <12000000>; - }; - - pad_clks_ck: pad_clks_ck@108 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&pad_clks_src_ck>; - ti,bit-shift = <8>; - reg = <0x0108>; - }; - - secure_32k_clk_src_ck: secure_32k_clk_src_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - slimbus_src_clk: slimbus_src_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <12000000>; - }; - - slimbus_clk: slimbus_clk@108 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&slimbus_src_clk>; - ti,bit-shift = <10>; - reg = <0x0108>; - }; - - sys_32k_ck: sys_32k_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - virt_12000000_ck: virt_12000000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <12000000>; - }; - - virt_13000000_ck: virt_13000000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <13000000>; - }; - - virt_16800000_ck: virt_16800000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <16800000>; - }; - - virt_19200000_ck: virt_19200000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <19200000>; - }; - - virt_26000000_ck: virt_26000000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <26000000>; - }; - - virt_27000000_ck: virt_27000000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <27000000>; - }; - - virt_38400000_ck: virt_38400000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <38400000>; - }; - - xclk60mhsp1_ck: xclk60mhsp1_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <60000000>; - }; - - xclk60mhsp2_ck: xclk60mhsp2_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <60000000>; - }; - - dpll_abe_ck: dpll_abe_ck@1e0 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-m4xen-clock"; - clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>; - reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>; - }; - - dpll_abe_x2_ck: dpll_abe_x2_ck { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-x2-clock"; - clocks = <&dpll_abe_ck>; - }; - - dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@1f0 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_abe_x2_ck>; - ti,max-div = <31>; - reg = <0x01f0>; - ti,index-starts-at-one; - }; - - abe_24m_fclk: abe_24m_fclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_abe_m2x2_ck>; - clock-mult = <1>; - clock-div = <8>; - }; - - abe_clk: abe_clk@108 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_abe_m2x2_ck>; - ti,max-div = <4>; - reg = <0x0108>; - ti,index-power-of-two; - }; - - abe_iclk: abe_iclk@528 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&aess_fclk>; - ti,bit-shift = <24>; - reg = <0x0528>; - ti,dividers = <2>, <1>; - }; - - abe_lp_clk_div: abe_lp_clk_div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_abe_m2x2_ck>; - clock-mult = <1>; - clock-div = <16>; - }; - - dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_abe_x2_ck>; - ti,max-div = <31>; - reg = <0x01f4>; - ti,index-starts-at-one; - }; - - dpll_core_byp_mux: dpll_core_byp_mux@12c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin>, <&dpll_abe_m3x2_ck>; - ti,bit-shift = <23>; - reg = <0x012c>; - }; - - dpll_core_ck: dpll_core_ck@120 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-core-clock"; - clocks = <&sys_clkin>, <&dpll_core_byp_mux>; - reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>; - }; - - dpll_core_x2_ck: dpll_core_x2_ck { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-x2-clock"; - clocks = <&dpll_core_ck>; - }; - - dpll_core_h21x2_ck: dpll_core_h21x2_ck@150 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <63>; - reg = <0x0150>; - ti,index-starts-at-one; - }; - - c2c_fclk: c2c_fclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_core_h21x2_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - c2c_iclk: c2c_iclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&c2c_fclk>; - clock-mult = <1>; - clock-div = <2>; - }; - - dpll_core_h11x2_ck: dpll_core_h11x2_ck@138 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <63>; - reg = <0x0138>; - ti,index-starts-at-one; - }; - - dpll_core_h12x2_ck: dpll_core_h12x2_ck@13c { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <63>; - reg = <0x013c>; - ti,index-starts-at-one; - }; - - dpll_core_h13x2_ck: dpll_core_h13x2_ck@140 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <63>; - reg = <0x0140>; - ti,index-starts-at-one; - }; - - dpll_core_h14x2_ck: dpll_core_h14x2_ck@144 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <63>; - reg = <0x0144>; - ti,index-starts-at-one; - }; - - dpll_core_h22x2_ck: dpll_core_h22x2_ck@154 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <63>; - reg = <0x0154>; - ti,index-starts-at-one; - }; - - dpll_core_h23x2_ck: dpll_core_h23x2_ck@158 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <63>; - reg = <0x0158>; - ti,index-starts-at-one; - }; - - dpll_core_h24x2_ck: dpll_core_h24x2_ck@15c { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <63>; - reg = <0x015c>; - ti,index-starts-at-one; - }; - - dpll_core_m2_ck: dpll_core_m2_ck@130 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_core_ck>; - ti,max-div = <31>; - reg = <0x0130>; - ti,index-starts-at-one; - }; - - dpll_core_m3x2_ck: dpll_core_m3x2_ck@134 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <31>; - reg = <0x0134>; - ti,index-starts-at-one; - }; - - iva_dpll_hs_clk_div: iva_dpll_hs_clk_div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_core_h12x2_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - dpll_iva_byp_mux: dpll_iva_byp_mux@1ac { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin>, <&iva_dpll_hs_clk_div>; - ti,bit-shift = <23>; - reg = <0x01ac>; - }; - - dpll_iva_ck: dpll_iva_ck@1a0 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-clock"; - clocks = <&sys_clkin>, <&dpll_iva_byp_mux>; - reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>; - assigned-clocks = <&dpll_iva_ck>; - assigned-clock-rates = <1165000000>; - }; - - dpll_iva_x2_ck: dpll_iva_x2_ck { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-x2-clock"; - clocks = <&dpll_iva_ck>; - }; - - dpll_iva_h11x2_ck: dpll_iva_h11x2_ck@1b8 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_iva_x2_ck>; - ti,max-div = <63>; - reg = <0x01b8>; - ti,index-starts-at-one; - assigned-clocks = <&dpll_iva_h11x2_ck>; - assigned-clock-rates = <465920000>; - }; - - dpll_iva_h12x2_ck: dpll_iva_h12x2_ck@1bc { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_iva_x2_ck>; - ti,max-div = <63>; - reg = <0x01bc>; - ti,index-starts-at-one; - assigned-clocks = <&dpll_iva_h12x2_ck>; - assigned-clock-rates = <388300000>; - }; - - mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_core_h12x2_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - dpll_mpu_ck: dpll_mpu_ck@160 { - #clock-cells = <0>; - compatible = "ti,omap5-mpu-dpll-clock"; - clocks = <&sys_clkin>, <&mpu_dpll_hs_clk_div>; - reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>; - }; - - dpll_mpu_m2_ck: dpll_mpu_m2_ck@170 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_mpu_ck>; - ti,max-div = <31>; - reg = <0x0170>; - ti,index-starts-at-one; - }; - - per_dpll_hs_clk_div: per_dpll_hs_clk_div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_abe_m3x2_ck>; - clock-mult = <1>; - clock-div = <2>; - }; - - usb_dpll_hs_clk_div: usb_dpll_hs_clk_div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_abe_m3x2_ck>; - clock-mult = <1>; - clock-div = <3>; - }; - - l3_iclk_div: l3_iclk_div@100 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - ti,max-div = <2>; - ti,bit-shift = <4>; - reg = <0x100>; - clocks = <&dpll_core_h12x2_ck>; - ti,index-power-of-two; - }; - - gpu_l3_iclk: gpu_l3_iclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&l3_iclk_div>; - clock-mult = <1>; - clock-div = <1>; - }; - - l4_root_clk_div: l4_root_clk_div@100 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - ti,max-div = <2>; - ti,bit-shift = <8>; - reg = <0x100>; - clocks = <&l3_iclk_div>; - ti,index-power-of-two; - }; - - slimbus1_slimbus_clk: slimbus1_slimbus_clk@560 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&slimbus_clk>; - ti,bit-shift = <11>; - reg = <0x0560>; - }; - - aess_fclk: aess_fclk@528 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&abe_clk>; - ti,bit-shift = <24>; - ti,max-div = <2>; - reg = <0x0528>; - }; - - mcasp_sync_mux_ck: mcasp_sync_mux_ck@540 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>; - ti,bit-shift = <26>; - reg = <0x0540>; - }; - - mcasp_gfclk: mcasp_gfclk@540 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&mcasp_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>; - ti,bit-shift = <24>; - reg = <0x0540>; - }; - - dummy_ck: dummy_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; -}; -&prm_clocks { - sys_clkin: sys_clkin@110 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>; - reg = <0x0110>; - ti,index-starts-at-one; - }; - - abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux@108 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin>, <&sys_32k_ck>; - reg = <0x0108>; - }; - - abe_dpll_clk_mux: abe_dpll_clk_mux@10c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin>, <&sys_32k_ck>; - reg = <0x010c>; - }; - - custefuse_sys_gfclk_div: custefuse_sys_gfclk_div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&sys_clkin>; - clock-mult = <1>; - clock-div = <2>; - }; - - dss_syc_gfclk_div: dss_syc_gfclk_div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&sys_clkin>; - clock-mult = <1>; - clock-div = <1>; - }; - - wkupaon_iclk_mux: wkupaon_iclk_mux@108 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin>, <&abe_lp_clk_div>; - reg = <0x0108>; - }; - - l3instr_ts_gclk_div: l3instr_ts_gclk_div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&wkupaon_iclk_mux>; - clock-mult = <1>; - clock-div = <1>; - }; -}; - -&cm_core_clocks { - - dpll_per_byp_mux: dpll_per_byp_mux@14c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin>, <&per_dpll_hs_clk_div>; - ti,bit-shift = <23>; - reg = <0x014c>; - }; - - dpll_per_ck: dpll_per_ck@140 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-clock"; - clocks = <&sys_clkin>, <&dpll_per_byp_mux>; - reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>; - }; - - dpll_per_x2_ck: dpll_per_x2_ck { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-x2-clock"; - clocks = <&dpll_per_ck>; - }; - - dpll_per_h11x2_ck: dpll_per_h11x2_ck@158 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_per_x2_ck>; - ti,max-div = <63>; - reg = <0x0158>; - ti,index-starts-at-one; - }; - - dpll_per_h12x2_ck: dpll_per_h12x2_ck@15c { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_per_x2_ck>; - ti,max-div = <63>; - reg = <0x015c>; - ti,index-starts-at-one; - }; - - dpll_per_h14x2_ck: dpll_per_h14x2_ck@164 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_per_x2_ck>; - ti,max-div = <63>; - reg = <0x0164>; - ti,index-starts-at-one; - }; - - dpll_per_m2_ck: dpll_per_m2_ck@150 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_per_ck>; - ti,max-div = <31>; - reg = <0x0150>; - ti,index-starts-at-one; - }; - - dpll_per_m2x2_ck: dpll_per_m2x2_ck@150 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_per_x2_ck>; - ti,max-div = <31>; - reg = <0x0150>; - ti,index-starts-at-one; - }; - - dpll_per_m3x2_ck: dpll_per_m3x2_ck@154 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_per_x2_ck>; - ti,max-div = <31>; - reg = <0x0154>; - ti,index-starts-at-one; - }; - - dpll_unipro1_ck: dpll_unipro1_ck@200 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-clock"; - clocks = <&sys_clkin>, <&sys_clkin>; - reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>; - }; - - dpll_unipro1_clkdcoldo: dpll_unipro1_clkdcoldo { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_unipro1_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - dpll_unipro1_m2_ck: dpll_unipro1_m2_ck@210 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_unipro1_ck>; - ti,max-div = <127>; - reg = <0x0210>; - ti,index-starts-at-one; - }; - - dpll_unipro2_ck: dpll_unipro2_ck@1c0 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-clock"; - clocks = <&sys_clkin>, <&sys_clkin>; - reg = <0x01c0>, <0x01c4>, <0x01cc>, <0x01c8>; - }; - - dpll_unipro2_clkdcoldo: dpll_unipro2_clkdcoldo { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_unipro2_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - dpll_unipro2_m2_ck: dpll_unipro2_m2_ck@1d0 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_unipro2_ck>; - ti,max-div = <127>; - reg = <0x01d0>; - ti,index-starts-at-one; - }; - - dpll_usb_byp_mux: dpll_usb_byp_mux@18c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin>, <&usb_dpll_hs_clk_div>; - ti,bit-shift = <23>; - reg = <0x018c>; - }; - - dpll_usb_ck: dpll_usb_ck@180 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-j-type-clock"; - clocks = <&sys_clkin>, <&dpll_usb_byp_mux>; - reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>; - }; - - dpll_usb_clkdcoldo: dpll_usb_clkdcoldo { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_usb_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - dpll_usb_m2_ck: dpll_usb_m2_ck@190 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_usb_ck>; - ti,max-div = <127>; - reg = <0x0190>; - ti,index-starts-at-one; - }; - - func_128m_clk: func_128m_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_per_h11x2_ck>; - clock-mult = <1>; - clock-div = <2>; - }; - - func_12m_fclk: func_12m_fclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_per_m2x2_ck>; - clock-mult = <1>; - clock-div = <16>; - }; - - func_24m_clk: func_24m_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_per_m2_ck>; - clock-mult = <1>; - clock-div = <4>; - }; - - func_48m_fclk: func_48m_fclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_per_m2x2_ck>; - clock-mult = <1>; - clock-div = <4>; - }; - - func_96m_fclk: func_96m_fclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_per_m2x2_ck>; - clock-mult = <1>; - clock-div = <2>; - }; - - l3init_60m_fclk: l3init_60m_fclk@104 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_usb_m2_ck>; - reg = <0x0104>; - ti,dividers = <1>, <8>; - }; - - iss_ctrlclk: iss_ctrlclk@1320 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&func_96m_fclk>; - ti,bit-shift = <8>; - reg = <0x1320>; - }; - - lli_txphy_clk: lli_txphy_clk@f20 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&dpll_unipro1_clkdcoldo>; - ti,bit-shift = <8>; - reg = <0x0f20>; - }; - - lli_txphy_ls_clk: lli_txphy_ls_clk@f20 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&dpll_unipro1_m2_ck>; - ti,bit-shift = <9>; - reg = <0x0f20>; - }; - - usb_phy_cm_clk32k: usb_phy_cm_clk32k@640 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_32k_ck>; - ti,bit-shift = <8>; - reg = <0x0640>; - }; - - fdif_fclk: fdif_fclk@1328 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_per_h11x2_ck>; - ti,bit-shift = <24>; - ti,max-div = <2>; - reg = <0x1328>; - }; - - gpu_core_gclk_mux: gpu_core_gclk_mux@1520 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>; - ti,bit-shift = <24>; - reg = <0x1520>; - }; - - gpu_hyd_gclk_mux: gpu_hyd_gclk_mux@1520 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>; - ti,bit-shift = <25>; - reg = <0x1520>; - }; - - hsi_fclk: hsi_fclk@1638 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_per_m2x2_ck>; - ti,bit-shift = <24>; - ti,max-div = <2>; - reg = <0x1638>; - }; -}; - -&cm_core_clockdomains { - l3init_clkdm: l3init_clkdm { - compatible = "ti,clockdomain"; - clocks = <&dpll_usb_ck>; - }; -}; - -&scrm_clocks { - auxclk0_src_gate_ck: auxclk0_src_gate_ck@310 { - #clock-cells = <0>; - compatible = "ti,composite-no-wait-gate-clock"; - clocks = <&dpll_core_m3x2_ck>; - ti,bit-shift = <8>; - reg = <0x0310>; - }; - - auxclk0_src_mux_ck: auxclk0_src_mux_ck@310 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; - ti,bit-shift = <1>; - reg = <0x0310>; - }; - - auxclk0_src_ck: auxclk0_src_ck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&auxclk0_src_gate_ck>, <&auxclk0_src_mux_ck>; - }; - - auxclk0_ck: auxclk0_ck@310 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&auxclk0_src_ck>; - ti,bit-shift = <16>; - ti,max-div = <16>; - reg = <0x0310>; - }; - - auxclk1_src_gate_ck: auxclk1_src_gate_ck@314 { - #clock-cells = <0>; - compatible = "ti,composite-no-wait-gate-clock"; - clocks = <&dpll_core_m3x2_ck>; - ti,bit-shift = <8>; - reg = <0x0314>; - }; - - auxclk1_src_mux_ck: auxclk1_src_mux_ck@314 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; - ti,bit-shift = <1>; - reg = <0x0314>; - }; - - auxclk1_src_ck: auxclk1_src_ck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&auxclk1_src_gate_ck>, <&auxclk1_src_mux_ck>; - }; - - auxclk1_ck: auxclk1_ck@314 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&auxclk1_src_ck>; - ti,bit-shift = <16>; - ti,max-div = <16>; - reg = <0x0314>; - }; - - auxclk2_src_gate_ck: auxclk2_src_gate_ck@318 { - #clock-cells = <0>; - compatible = "ti,composite-no-wait-gate-clock"; - clocks = <&dpll_core_m3x2_ck>; - ti,bit-shift = <8>; - reg = <0x0318>; - }; - - auxclk2_src_mux_ck: auxclk2_src_mux_ck@318 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; - ti,bit-shift = <1>; - reg = <0x0318>; - }; - - auxclk2_src_ck: auxclk2_src_ck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&auxclk2_src_gate_ck>, <&auxclk2_src_mux_ck>; - }; - - auxclk2_ck: auxclk2_ck@318 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&auxclk2_src_ck>; - ti,bit-shift = <16>; - ti,max-div = <16>; - reg = <0x0318>; - }; - - auxclk3_src_gate_ck: auxclk3_src_gate_ck@31c { - #clock-cells = <0>; - compatible = "ti,composite-no-wait-gate-clock"; - clocks = <&dpll_core_m3x2_ck>; - ti,bit-shift = <8>; - reg = <0x031c>; - }; - - auxclk3_src_mux_ck: auxclk3_src_mux_ck@31c { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; - ti,bit-shift = <1>; - reg = <0x031c>; - }; - - auxclk3_src_ck: auxclk3_src_ck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&auxclk3_src_gate_ck>, <&auxclk3_src_mux_ck>; - }; - - auxclk3_ck: auxclk3_ck@31c { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&auxclk3_src_ck>; - ti,bit-shift = <16>; - ti,max-div = <16>; - reg = <0x031c>; - }; - - auxclk4_src_gate_ck: auxclk4_src_gate_ck@320 { - #clock-cells = <0>; - compatible = "ti,composite-no-wait-gate-clock"; - clocks = <&dpll_core_m3x2_ck>; - ti,bit-shift = <8>; - reg = <0x0320>; - }; - - auxclk4_src_mux_ck: auxclk4_src_mux_ck@320 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; - ti,bit-shift = <1>; - reg = <0x0320>; - }; - - auxclk4_src_ck: auxclk4_src_ck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&auxclk4_src_gate_ck>, <&auxclk4_src_mux_ck>; - }; - - auxclk4_ck: auxclk4_ck@320 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&auxclk4_src_ck>; - ti,bit-shift = <16>; - ti,max-div = <16>; - reg = <0x0320>; - }; - - auxclkreq0_ck: auxclkreq0_ck@210 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>; - ti,bit-shift = <2>; - reg = <0x0210>; - }; - - auxclkreq1_ck: auxclkreq1_ck@214 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>; - ti,bit-shift = <2>; - reg = <0x0214>; - }; - - auxclkreq2_ck: auxclkreq2_ck@218 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>; - ti,bit-shift = <2>; - reg = <0x0218>; - }; - - auxclkreq3_ck: auxclkreq3_ck@21c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>; - ti,bit-shift = <2>; - reg = <0x021c>; - }; -}; - -&cm_core_aon { - mpu_cm: mpu_cm@300 { - compatible = "ti,omap4-cm"; - reg = <0x300 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x300 0x100>; - - mpu_clkctrl: clk@20 { - compatible = "ti,clkctrl"; - reg = <0x20 0x4>; - #clock-cells = <2>; - }; - }; - - dsp_cm: dsp_cm@400 { - compatible = "ti,omap4-cm"; - reg = <0x400 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x400 0x100>; - - dsp_clkctrl: clk@20 { - compatible = "ti,clkctrl"; - reg = <0x20 0x4>; - #clock-cells = <2>; - }; - }; - - abe_cm: abe_cm@500 { - compatible = "ti,omap4-cm"; - reg = <0x500 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x500 0x100>; - - abe_clkctrl: clk@20 { - compatible = "ti,clkctrl"; - reg = <0x20 0x64>; - #clock-cells = <2>; - }; - }; - -}; - -&cm_core { - l3main1_cm: l3main1_cm@700 { - compatible = "ti,omap4-cm"; - reg = <0x700 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x700 0x100>; - - l3main1_clkctrl: clk@20 { - compatible = "ti,clkctrl"; - reg = <0x20 0x4>; - #clock-cells = <2>; - }; - }; - - l3main2_cm: l3main2_cm@800 { - compatible = "ti,omap4-cm"; - reg = <0x800 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x800 0x100>; - - l3main2_clkctrl: clk@20 { - compatible = "ti,clkctrl"; - reg = <0x20 0x4>; - #clock-cells = <2>; - }; - }; - - ipu_cm: ipu_cm@900 { - compatible = "ti,omap4-cm"; - reg = <0x900 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x900 0x100>; - - ipu_clkctrl: clk@20 { - compatible = "ti,clkctrl"; - reg = <0x20 0x4>; - #clock-cells = <2>; - }; - }; - - dma_cm: dma_cm@a00 { - compatible = "ti,omap4-cm"; - reg = <0xa00 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0xa00 0x100>; - - dma_clkctrl: clk@20 { - compatible = "ti,clkctrl"; - reg = <0x20 0x4>; - #clock-cells = <2>; - }; - }; - - emif_cm: emif_cm@b00 { - compatible = "ti,omap4-cm"; - reg = <0xb00 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0xb00 0x100>; - - emif_clkctrl: clk@20 { - compatible = "ti,clkctrl"; - reg = <0x20 0x1c>; - #clock-cells = <2>; - }; - }; - - l4cfg_cm: l4cfg_cm@d00 { - compatible = "ti,omap4-cm"; - reg = <0xd00 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0xd00 0x100>; - - l4cfg_clkctrl: clk@20 { - compatible = "ti,clkctrl"; - reg = <0x20 0x14>; - #clock-cells = <2>; - }; - }; - - l3instr_cm: l3instr_cm@e00 { - compatible = "ti,omap4-cm"; - reg = <0xe00 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0xe00 0x100>; - - l3instr_clkctrl: clk@20 { - compatible = "ti,clkctrl"; - reg = <0x20 0xc>; - #clock-cells = <2>; - }; - }; - - l4per_cm: l4per_cm@1000 { - compatible = "ti,omap4-cm"; - reg = <0x1000 0x200>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1000 0x200>; - - l4per_clkctrl: clk@20 { - compatible = "ti,clkctrl"; - reg = <0x20 0x15c>; - #clock-cells = <2>; - }; - }; - - dss_cm: dss_cm@1400 { - compatible = "ti,omap4-cm"; - reg = <0x1400 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1400 0x100>; - - dss_clkctrl: clk@20 { - compatible = "ti,clkctrl"; - reg = <0x20 0x4>; - #clock-cells = <2>; - }; - }; - - gpu_cm: gpu_cm@1500 { - compatible = "ti,omap4-cm"; - reg = <0x1500 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1500 0x100>; - - gpu_clkctrl: clk@20 { - compatible = "ti,clkctrl"; - reg = <0x20 0x4>; - #clock-cells = <2>; - }; - }; - - l3init_cm: l3init_cm@1600 { - compatible = "ti,omap4-cm"; - reg = <0x1600 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1600 0x100>; - - l3init_clkctrl: clk@20 { - compatible = "ti,clkctrl"; - reg = <0x20 0xd4>; - #clock-cells = <2>; - }; - }; -}; - -&prm { - wkupaon_cm: wkupaon_cm@1900 { - compatible = "ti,omap4-cm"; - reg = <0x1900 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1900 0x100>; - - wkupaon_clkctrl: clk@20 { - compatible = "ti,clkctrl"; - reg = <0x20 0x5c>; - #clock-cells = <2>; - }; - }; -}; - -&scm_wkup_pad_conf_clocks { - fref_xtal_ck: fref_xtal_ck { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_clkin>; - ti,bit-shift = <28>; - reg = <0x14>; - }; -}; diff --git a/sys/gnu/dts/arm/openbmc-flash-layout-128.dtsi b/sys/gnu/dts/arm/openbmc-flash-layout-128.dtsi deleted file mode 100644 index 05101a38c5b..00000000000 --- a/sys/gnu/dts/arm/openbmc-flash-layout-128.dtsi +++ /dev/null @@ -1,32 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ - -partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - u-boot@0 { - reg = <0x0 0xe0000>; // 896KB - label = "u-boot"; - }; - - u-boot-env@e0000 { - reg = <0xe0000 0x20000>; // 128KB - label = "u-boot-env"; - }; - - kernel@100000 { - reg = <0x100000 0x900000>; // 9MB - label = "kernel"; - }; - - rofs@a00000 { - reg = <0xa00000 0x5600000>; // 86MB - label = "rofs"; - }; - - rwfs@6000000 { - reg = <0x6000000 0x2000000>; // 32MB - label = "rwfs"; - }; -}; diff --git a/sys/gnu/dts/arm/openbmc-flash-layout.dtsi b/sys/gnu/dts/arm/openbmc-flash-layout.dtsi deleted file mode 100644 index 6c26524e93e..00000000000 --- a/sys/gnu/dts/arm/openbmc-flash-layout.dtsi +++ /dev/null @@ -1,32 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ - -partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - u-boot@0 { - reg = <0x0 0x60000>; - label = "u-boot"; - }; - - u-boot-env@60000 { - reg = <0x60000 0x20000>; - label = "u-boot-env"; - }; - - kernel@80000 { - reg = <0x80000 0x440000>; - label = "kernel"; - }; - - rofs@c0000 { - reg = <0x4c0000 0x1740000>; - label = "rofs"; - }; - - rwfs@1c00000 { - reg = <0x1c00000 0x400000>; - label = "rwfs"; - }; -}; diff --git a/sys/gnu/dts/arm/orion5x-kuroboxpro.dts b/sys/gnu/dts/arm/orion5x-kuroboxpro.dts deleted file mode 100644 index e28b568e741..00000000000 --- a/sys/gnu/dts/arm/orion5x-kuroboxpro.dts +++ /dev/null @@ -1,127 +0,0 @@ -/* - * Device Tree file for Buffalo/Revogear Kurobox Pro - * - * Copyright (C) 2016 - * Roger Shimizu - * - * Based on the board file arch/arm/mach-orion5x/kurobox_pro-setup.c - * Copyright (C) Ronen Shitrit - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include "orion5x-linkstation.dtsi" -#include - -/ { - model = "Buffalo/Revogear Kurobox Pro"; - compatible = "buffalo,kurobox-pro", "marvell,orion5x-88f5182", "marvell,orion5x"; - - soc { - ranges = , - , - , - ; - }; - - memory { /* 128 MB */ - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; -}; - -&pinctrl { - pmx_power_hdd: pmx-power-hdd { - marvell,pins = "mpp1"; - marvell,function = "gpio"; - }; - - pmx_power_usb: pmx-power-usb { - marvell,pins = "mpp9"; - marvell,function = "gpio"; - }; -}; - -&devbus_cs0 { - status = "okay"; - compatible = "marvell,orion-nand"; - reg = ; - cle = <0>; - ale = <1>; - bank-width = <1>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - uImage@0 { /* 4 MB */ - reg = <0 0x400000>; - read-only; - }; - - rootfs@400000 { /* 64 MB */ - reg = <0x400000 0x4000000>; - read-only; - }; - - extra@4400000 { /* 188 MB */ - reg = <0x4400000 0xBC00000>; - read-only; - }; - }; -}; - -&hdd_power { - gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; -}; - -&usb_power { - gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>; -}; - -&sata { - nr-ports = <2>; -}; - -&ehci1 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/orion5x-lacie-d2-network.dts b/sys/gnu/dts/arm/orion5x-lacie-d2-network.dts deleted file mode 100644 index 422958d13d4..00000000000 --- a/sys/gnu/dts/arm/orion5x-lacie-d2-network.dts +++ /dev/null @@ -1,237 +0,0 @@ -/* - * Copyright (C) 2014 Thomas Petazzoni - * Copyright (C) 2009 Simon Guinot - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -/dts-v1/; - -#include -#include -#include -#include "orion5x-mv88f5182.dtsi" - -/ { - model = "LaCie d2 Network"; - compatible = "lacie,d2-network", "marvell,orion5x-88f5182", "marvell,orion5x"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x4000000>; /* 64 MB */ - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; - }; - - soc { - ranges = , - , - ; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-0 = <&pmx_buttons>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - front_button { - label = "Front Push Button"; - linux,code = ; - gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>; - }; - - power_rocker_sw_on { - label = "Power rocker switch (on|auto)"; - linux,input-type = <5>; /* EV_SW */ - linux,code = <1>; /* D2NET_SWITCH_POWER_ON */ - gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>; - }; - - power_rocker_sw_off { - label = "Power rocker switch (auto|off)"; - linux,input-type = <5>; /* EV_SW */ - linux,code = <2>; /* D2NET_SWITCH_POWER_OFF */ - gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_sata0_power &pmx_sata1_power>; - pinctrl-names = "default"; - - sata0_power: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "SATA0 Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 3 GPIO_ACTIVE_HIGH>; - }; - - sata1_power: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "SATA1 Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&devbus_bootcs { - status = "okay"; - - devbus,keep-config; - - /* - * Currently the MTD code does not recognize the MX29LV400CBCT - * as a bottom-type device. This could cause risks of - * accidentally erasing critical flash sectors. We thus define - * a single, write-protected partition covering the whole - * flash. TODO: once the flash part TOP/BOTTOM detection - * issue is sorted out in the MTD code, break this into at - * least three partitions: 'u-boot code', 'u-boot environment' - * and 'whatever is left'. - */ - flash@0 { - compatible = "cfi-flash"; - reg = <0 0x80000>; - bank-width = <1>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "Full512Kb"; - reg = <0 0x80000>; - read-only; - }; - }; -}; - -&mdio { - status = "okay"; - - ethphy: ethernet-phy { - reg = <8>; - }; -}; - -&ehci0 { - status = "okay"; -}; - -ð { - status = "okay"; - - ethernet-port@0 { - phy-handle = <ðphy>; - }; -}; - -&i2c { - status = "okay"; - clock-frequency = <100000>; - #address-cells = <1>; - - rtc@32 { - compatible = "ricoh,rs5c372b"; - reg = <0x32>; - }; - - fan@3e { - compatible = "gmt,g762"; - reg = <0x3e>; - - /* Not enough HW info */ - status = "disabled"; - }; - - eeprom@50 { - compatible = "atmel,24c08"; - reg = <0x50>; - }; -}; - -&pinctrl { - pinctrl-0 = <&pmx_leds &pmx_board_id &pmx_fan_fail>; - pinctrl-names = "default"; - - pmx_board_id: pmx-board-id { - marvell,pins = "mpp0", "mpp1", "mpp2"; - marvell,function = "gpio"; - }; - - pmx_buttons: pmx-buttons { - marvell,pins = "mpp8", "mpp9", "mpp18"; - marvell,function = "gpio"; - }; - - pmx_fan_fail: pmx-fan-fail { - marvell,pins = "mpp5"; - marvell,function = "gpio"; - }; - - /* - * MPP6: Red front LED - * MPP16: Blue front LED blink control - */ - pmx_leds: pmx-leds { - marvell,pins = "mpp6", "mpp16"; - marvell,function = "gpio"; - }; - - pmx_sata0_led_active: pmx-sata0-led-active { - marvell,pins = "mpp14"; - marvell,function = "sata0"; - }; - - pmx_sata0_power: pmx-sata0-power { - marvell,pins = "mpp3"; - marvell,function = "gpio"; - }; - - pmx_sata1_led_active: pmx-sata1-led-active { - marvell,pins = "mpp15"; - marvell,function = "sata1"; - }; - - pmx_sata1_power: pmx-sata1-power { - marvell,pins = "mpp12"; - marvell,function = "gpio"; - }; - - /* - * Non MPP GPIOs: - * GPIO 22: USB port 1 fuse (0 = Fail, 1 = Ok) - * GPIO 23: Blue front LED off - * GPIO 24: Inhibit board power off (0 = Disabled, 1 = Enabled) - */ -}; - -&sata { - pinctrl-0 = <&pmx_sata0_led_active - &pmx_sata1_led_active>; - pinctrl-names = "default"; - status = "okay"; - nr-ports = <2>; -}; - -&uart0 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/orion5x-lacie-ethernet-disk-mini-v2.dts b/sys/gnu/dts/arm/orion5x-lacie-ethernet-disk-mini-v2.dts deleted file mode 100644 index 0043e004015..00000000000 --- a/sys/gnu/dts/arm/orion5x-lacie-ethernet-disk-mini-v2.dts +++ /dev/null @@ -1,175 +0,0 @@ -/* - * Copyright (C) 2012 Thomas Petazzoni - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -/* - * TODO: add Orion USB device port init when kernel.org support is added. - * TODO: add flash write support: see below. - * TODO: add power-off support. - * TODO: add I2C EEPROM support. - */ - -/dts-v1/; - -#include -#include -#include -#include "orion5x-mv88f5182.dtsi" - -/ { - model = "LaCie Ethernet Disk mini V2"; - compatible = "lacie,ethernet-disk-mini-v2", "marvell,orion5x-88f5182", "marvell,orion5x"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x4000000>; /* 64 MB */ - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; - }; - - soc { - ranges = , - , - ; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-0 = <&pmx_power_button>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - button@1 { - label = "Power-on Switch"; - linux,code = ; - gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_power_led>; - pinctrl-names = "default"; - - led@1 { - label = "power:blue"; - gpios = <&gpio0 16 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&devbus_bootcs { - status = "okay"; - - /* Read parameters */ - devbus,bus-width = <8>; - devbus,turn-off-ps = <90000>; - devbus,badr-skew-ps = <0>; - devbus,acc-first-ps = <186000>; - devbus,acc-next-ps = <186000>; - - /* Write parameters */ - devbus,wr-high-ps = <90000>; - devbus,wr-low-ps = <90000>; - devbus,ale-wr-ps = <90000>; - - /* - * Currently the MTD code does not recognize the MX29LV400CBCT - * as a bottom-type device. This could cause risks of - * accidentally erasing critical flash sectors. We thus define - * a single, write-protected partition covering the whole - * flash. TODO: once the flash part TOP/BOTTOM detection - * issue is sorted out in the MTD code, break this into at - * least three partitions: 'u-boot code', 'u-boot environment' - * and 'whatever is left'. - */ - flash@0 { - compatible = "cfi-flash"; - reg = <0 0x80000>; - bank-width = <1>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "Full512Kb"; - reg = <0 0x80000>; - read-only; - }; - }; -}; - -&ehci0 { - status = "okay"; -}; - -ð { - status = "okay"; - - ethernet-port@0 { - phy-handle = <ðphy>; - }; -}; - -&i2c { - status = "okay"; - clock-frequency = <100000>; - #address-cells = <1>; - - rtc@32 { - compatible = "ricoh,rs5c372a"; - reg = <0x32>; - interrupt-parent = <&gpio0>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&mdio { - status = "okay"; - - ethphy: ethernet-phy { - reg = <8>; - }; -}; - -&pinctrl { - pinctrl-0 = <&pmx_rtc &pmx_power_led_ctrl>; - pinctrl-names = "default"; - - pmx_power_button: pmx-power-button { - marvell,pins = "mpp18"; - marvell,function = "gpio"; - }; - - pmx_power_led: pmx-power-led { - marvell,pins = "mpp16"; - marvell,function = "gpio"; - }; - - pmx_power_led_ctrl: pmx-power-led-ctrl { - marvell,pins = "mpp17"; - marvell,function = "gpio"; - }; - - pmx_rtc: pmx-rtc { - marvell,pins = "mpp3"; - marvell,function = "gpio"; - }; -}; - -&sata { - pinctrl-0 = <&pmx_sata0 &pmx_sata1>; - pinctrl-names = "default"; - status = "okay"; - nr-ports = <2>; -}; - -&uart0 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/orion5x-linkstation-lschl.dts b/sys/gnu/dts/arm/orion5x-linkstation-lschl.dts deleted file mode 100644 index ee751995c8d..00000000000 --- a/sys/gnu/dts/arm/orion5x-linkstation-lschl.dts +++ /dev/null @@ -1,171 +0,0 @@ -/* - * Device Tree file for Buffalo Linkstation LS-CHLv3 - * - * Copyright (C) 2016 Ash Hughes - * Copyright (C) 2015-2017 - * Roger Shimizu - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include "orion5x-linkstation.dtsi" -#include "mvebu-linkstation-gpio-simple.dtsi" -#include "mvebu-linkstation-fan.dtsi" -#include - -/ { - model = "Buffalo Linkstation LiveV3 (LS-CHL)"; - compatible = "buffalo,lschl", "marvell,orion5x-88f5182", "marvell,orion5x"; - - memory { /* 128 MB */ - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - gpio_keys { - func { - label = "Function Button"; - linux,code = ; - gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; - }; - - power-on-switch { - gpios = <&gpio0 8 GPIO_ACTIVE_LOW>; - }; - - power-auto-switch { - gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; - }; - }; - - gpio_leds { - pinctrl-0 = <&pmx_led_power &pmx_led_alarm &pmx_led_info &pmx_led_func>; - blue-power-led { - gpios = <&gpio0 0 GPIO_ACTIVE_LOW>; - }; - - red-alarm-led { - gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; - }; - - amber-info-led { - gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; - }; - - func { - label = "lschl:func:blue:top"; - gpios = <&gpio0 17 GPIO_ACTIVE_LOW>; - }; - }; - - gpio_fan { - gpios = <&gpio0 14 GPIO_ACTIVE_LOW - &gpio0 16 GPIO_ACTIVE_LOW>; - - alarm-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; - }; -}; - -&pinctrl { - pmx_led_power: pmx-leds { - marvell,pins = "mpp0"; - marvell,function = "gpio"; - }; - - pmx_power_hdd: pmx-power-hdd { - marvell,pins = "mpp1"; - marvell,function = "gpio"; - }; - - pmx_led_alarm: pmx-leds { - marvell,pins = "mpp2"; - marvell,function = "gpio"; - }; - - pmx_led_info: pmx-leds { - marvell,pins = "mpp3"; - marvell,function = "gpio"; - }; - - pmx_fan_lock: pmx-fan-lock { - marvell,pins = "mpp6"; - marvell,function = "gpio"; - }; - - pmx_power_switch: pmx-power-switch { - marvell,pins = "mpp8", "mpp10", "mpp15"; - marvell,function = "gpio"; - }; - - pmx_power_usb: pmx-power-usb { - marvell,pins = "mpp9"; - marvell,function = "gpio"; - }; - - pmx_fan_high: pmx-fan-high { - marvell,pins = "mpp14"; - marvell,function = "gpio"; - }; - - pmx_fan_low: pmx-fan-low { - marvell,pins = "mpp16"; - marvell,function = "gpio"; - }; - - pmx_led_func: pmx-leds { - marvell,pins = "mpp17"; - marvell,function = "gpio"; - }; - - pmx_sw_init: pmx-sw-init { - marvell,pins = "mpp7"; - marvell,function = "gpio"; - }; -}; - -&hdd_power { - gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; -}; - -&usb_power { - gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>; -}; - diff --git a/sys/gnu/dts/arm/orion5x-linkstation-lsgl.dts b/sys/gnu/dts/arm/orion5x-linkstation-lsgl.dts deleted file mode 100644 index 9f6fedd3917..00000000000 --- a/sys/gnu/dts/arm/orion5x-linkstation-lsgl.dts +++ /dev/null @@ -1,91 +0,0 @@ -/* - * Device Tree file for Buffalo Linkstation LS-GL - * (also known as Buffalo Linkstation Pro/Live) - * - * Copyright (C) 2016 - * Roger Shimizu - * - * Based on the board file arch/arm/mach-orion5x/kurobox_pro-setup.c - * Copyright (C) Ronen Shitrit - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include "orion5x-linkstation.dtsi" -#include - -/ { - model = "Buffalo Linkstation Pro/Live"; - compatible = "buffalo,lsgl", "marvell,orion5x-88f5182", "marvell,orion5x"; - - memory { /* 128 MB */ - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; -}; - -&pinctrl { - pmx_power_hdd: pmx-power-hdd { - marvell,pins = "mpp1"; - marvell,function = "gpio"; - }; - - pmx_power_usb: pmx-power-usb { - marvell,pins = "mpp9"; - marvell,function = "gpio"; - }; -}; - -&hdd_power { - gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; -}; - -&usb_power { - gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>; -}; - -&sata { - nr-ports = <2>; -}; - -&ehci1 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/orion5x-linkstation-lswtgl.dts b/sys/gnu/dts/arm/orion5x-linkstation-lswtgl.dts deleted file mode 100644 index 7f77ce8cc1f..00000000000 --- a/sys/gnu/dts/arm/orion5x-linkstation-lswtgl.dts +++ /dev/null @@ -1,151 +0,0 @@ -/* - * Device Tree file for Buffalo Linkstation LS-WTGL - * - * Copyright (C) 2015, 2016 - * Roger Shimizu - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include "orion5x-linkstation.dtsi" -#include "mvebu-linkstation-gpio-simple.dtsi" -#include "mvebu-linkstation-fan.dtsi" -#include - -/ { - model = "Buffalo Linkstation LS-WTGL"; - compatible = "buffalo,lswtgl", "marvell,orion5x-88f5182", "marvell,orion5x"; - - memory { /* 64 MB */ - device_type = "memory"; - reg = <0x00000000 0x4000000>; - }; - - gpio_keys { - power-on-switch { - gpios = <&gpio0 8 GPIO_ACTIVE_LOW>; - }; - - power-auto-switch { - gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; - }; - }; - - gpio_leds { - blue-power-led { - gpios = <&gpio0 0 GPIO_ACTIVE_LOW>; - }; - - red-alarm-led { - gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; - }; - - amber-info-led { - gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; - }; - }; - - gpio_fan { - gpios = <&gpio0 14 GPIO_ACTIVE_LOW - &gpio0 17 GPIO_ACTIVE_LOW>; - - alarm-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; - }; -}; - -&pinctrl { - pmx_led_power: pmx-leds { - marvell,pins = "mpp0"; - marvell,function = "gpio"; - }; - - pmx_power_hdd: pmx-power-hdd { - marvell,pins = "mpp1"; - marvell,function = "gpio"; - }; - - pmx_led_alarm: pmx-leds { - marvell,pins = "mpp2"; - marvell,function = "gpio"; - }; - - pmx_led_info: pmx-leds { - marvell,pins = "mpp3"; - marvell,function = "gpio"; - }; - - pmx_fan_lock: pmx-fan-lock { - marvell,pins = "mpp6"; - marvell,function = "gpio"; - }; - - pmx_power_switch: pmx-power-switch { - marvell,pins = "mpp8", "mpp10"; - marvell,function = "gpio"; - }; - - pmx_power_usb: pmx-power-usb { - marvell,pins = "mpp9"; - marvell,function = "gpio"; - }; - - pmx_fan_high: pmx-fan-high { - marvell,pins = "mpp14"; - marvell,function = "gpio"; - }; - - pmx_fan_low: pmx-fan-low { - marvell,pins = "mpp17"; - marvell,function = "gpio"; - }; -}; - -&hdd_power { - gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; -}; - -&usb_power { - gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>; -}; - -&sata { - nr-ports = <2>; -}; diff --git a/sys/gnu/dts/arm/orion5x-linkstation.dtsi b/sys/gnu/dts/arm/orion5x-linkstation.dtsi deleted file mode 100644 index b6c9b85951e..00000000000 --- a/sys/gnu/dts/arm/orion5x-linkstation.dtsi +++ /dev/null @@ -1,180 +0,0 @@ -/* - * Device Tree common file for orion5x based Buffalo Linkstation - * - * Copyright (C) 2015, 2016 - * Roger Shimizu - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "orion5x-mv88f5182.dtsi" - -/ { - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; - }; - - soc { - ranges = , - , - ; - }; - - restart_poweroff { - compatible = "restart-poweroff"; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_power_usb &pmx_power_hdd>; - pinctrl-names = "default"; - - usb_power: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "USB Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - }; - - hdd_power: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "HDD Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - }; - }; -}; - -&pinctrl { - pmx_power_hdd: pmx-power-hdd { - marvell,function = "gpio"; - }; - - pmx_power_usb: pmx-power-usb { - marvell,function = "gpio"; - }; -}; - -&devbus_bootcs { - status = "okay"; - devbus,keep-config; - - flash@0 { - compatible = "jedec-flash"; - reg = <0 0x40000>; - bank-width = <1>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - header@0 { - reg = <0 0x30000>; - read-only; - }; - - uboot@30000 { - reg = <0x30000 0xF000>; - read-only; - }; - - uboot_env@3F000 { - reg = <0x3F000 0x1000>; - }; - }; - }; -}; - -&mdio { - status = "okay"; - - ethphy: ethernet-phy { - reg = <8>; - }; -}; - -ð { - status = "okay"; - - ethernet-port@0 { - phy-handle = <ðphy>; - }; -}; - -&ehci0 { - status = "okay"; -}; - -&i2c { - status = "okay"; - - rtc@32 { - compatible = "ricoh,rs5c372a"; - reg = <0x32>; - }; -}; - -&wdt { - status = "disabled"; -}; - -&sata { - status = "okay"; - nr-ports = <1>; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/orion5x-lswsgl.dts b/sys/gnu/dts/arm/orion5x-lswsgl.dts deleted file mode 100644 index 2fbc17d6dfa..00000000000 --- a/sys/gnu/dts/arm/orion5x-lswsgl.dts +++ /dev/null @@ -1,277 +0,0 @@ -/* - * Copyright (C) 2015 Benjamin Cama - * Copyright (C) 2014 Thomas Petazzoni - * Based on the board file arch/arm/mach-orion5x/lsmini-setup.c, - * Copyright (C) 2008 Alexey Kopytko - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include -#include -#include -#include "orion5x-mv88f5182.dtsi" - -/ { - model = "Buffalo Linkstation Mini (LS-WSGL)"; - compatible = "buffalo,lswsgl", "marvell,orion5x-88f5182", "marvell,orion5x"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x8000000>; /* 128 MB */ - }; - - chosen { - bootargs = "console=ttyS0,115200 earlyprintk"; - stdout-path = &uart0; - }; - - soc { - ranges = , - , - ; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-0 = <&pmx_buttons>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - func { - label = "Function Button"; - linux,code = ; - gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; - }; - - power { - label = "Power-on Switch"; - linux,input-type = <5>; /* EV_SW */ - linux,code = ; /* LSMINI_SW_POWER */ - gpios = <&gpio0 18 GPIO_ACTIVE_LOW>; - }; - - autopower { - label = "Power-auto Switch"; - linux,input-type = <5>; /* EV_SW */ - linux,code = ; /* LSMINI_SW_AUTOPOWER */ - gpios = <&gpio0 17 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_led_alarm &pmx_led_info &pmx_led_func - &pmx_led_power>; - pinctrl-names = "default"; - - alarm { - label = "lswsgl:alarm:red"; - gpio = <&gpio0 2 GPIO_ACTIVE_LOW>; - }; - - info { - label = "lswsgl:info:amber"; - gpio = <&gpio0 3 GPIO_ACTIVE_LOW>; - }; - - func { - label = "lswsgl:func:blue:top"; - gpio = <&gpio0 9 GPIO_ACTIVE_LOW>; - }; - - power { - label = "lswsgl:power:blue:bottom"; - gpio = <&gpio0 14 GPIO_ACTIVE_LOW>; - default-state = "on"; - }; - }; - - restart_poweroff { - compatible = "restart-poweroff"; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_sata0_power &pmx_sata1_power &pmx_usb_power>; - pinctrl-names = "default"; - - sata0_power: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "SATA0 Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 1 GPIO_ACTIVE_HIGH>; - }; - - sata1_power: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "SATA1 Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 19 GPIO_ACTIVE_HIGH>; - }; - - usb_power: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "USB Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 16 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&devbus_bootcs { - status = "okay"; - - devbus,keep-config; - - flash@0 { - compatible = "cfi-flash"; - reg = <0 0x40000>; - bank-width = <1>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "Full256Kb"; - reg = <0 0x40000>; - read-only; - }; - }; -}; - -&mdio { - status = "okay"; - - ethphy: ethernet-phy { - reg = <8>; - }; -}; - -&ehci0 { - status = "okay"; -}; - -ð { - status = "okay"; - - ethernet-port@0 { - phy-handle = <ðphy>; - }; -}; - -&i2c { - status = "okay"; - clock-frequency = <100000>; - #address-cells = <1>; - - rtc@32 { - compatible = "ricoh,rs5c372a"; - reg = <0x32>; - }; -}; - -&pinctrl { - pmx_buttons: pmx-buttons { - marvell,pins = "mpp15", "mpp17", "mpp18"; - marvell,function = "gpio"; - }; - - pmx_led_alarm: pmx-leds { - marvell,pins = "mpp2"; - marvell,function = "gpio"; - }; - - pmx_led_info: pmx-leds { - marvell,pins = "mpp3"; - marvell,function = "gpio"; - }; - - pmx_led_func: pmx-leds { - marvell,pins = "mpp9"; - marvell,function = "gpio"; - }; - - pmx_led_power: pmx-leds { - marvell,pins = "mpp14"; - marvell,function = "gpio"; - }; - - pmx_sata0_power: pmx-sata0-power { - marvell,pins = "mpp1"; - marvell,function = "gpio"; - }; - - pmx_sata1_power: pmx-sata1-power { - marvell,pins = "mpp19"; - marvell,function = "gpio"; - }; - - pmx_usb_power: pmx-usb-power { - marvell,pins = "mpp16"; - marvell,function = "gpio"; - }; -}; - -&sata { - status = "okay"; - nr-ports = <2>; -}; - -&uart0 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/orion5x-maxtor-shared-storage-2.dts b/sys/gnu/dts/arm/orion5x-maxtor-shared-storage-2.dts deleted file mode 100644 index 0ca6208a267..00000000000 --- a/sys/gnu/dts/arm/orion5x-maxtor-shared-storage-2.dts +++ /dev/null @@ -1,179 +0,0 @@ -/* - * Copyright (C) 2014 Thomas Petazzoni - * Copyright (C) Sylver Bruneau - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -/dts-v1/; - -#include -#include -#include -#include "orion5x-mv88f5182.dtsi" - -/ { - model = "Maxtor Shared Storage II"; - compatible = "maxtor,shared-storage-2", "marvell,orion5x-88f5182", "marvell,orion5x"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x4000000>; /* 64 MB */ - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; - }; - - soc { - ranges = , - , - ; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-0 = <&pmx_buttons>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - power { - label = "Power"; - linux,code = ; - gpios = <&gpio0 11 GPIO_ACTIVE_LOW>; - }; - - reset { - label = "Reset"; - linux,code = ; - gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&devbus_bootcs { - status = "okay"; - - devbus,keep-config; - - /* - * Currently the MTD code does not recognize the MX29LV400CBCT - * as a bottom-type device. This could cause risks of - * accidentally erasing critical flash sectors. We thus define - * a single, write-protected partition covering the whole - * flash. TODO: once the flash part TOP/BOTTOM detection - * issue is sorted out in the MTD code, break this into at - * least three partitions: 'u-boot code', 'u-boot environment' - * and 'whatever is left'. - */ - flash@0 { - compatible = "cfi-flash"; - reg = <0 0x40000>; - bank-width = <1>; - #address-cells = <1>; - #size-cells = <1>; - }; -}; - -&mdio { - status = "okay"; - - ethphy: ethernet-phy { - reg = <8>; - }; -}; - -&ehci0 { - status = "okay"; -}; - -ð { - status = "okay"; - - ethernet-port@0 { - phy-handle = <ðphy>; - }; -}; - -&i2c { - status = "okay"; - clock-frequency = <100000>; - #address-cells = <1>; - - rtc@68 { - compatible = "st,m41t81"; - reg = <0x68>; - pinctrl-0 = <&pmx_rtc>; - pinctrl-names = "default"; - interrupt-parent = <&gpio0>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&pinctrl { - pinctrl-0 = <&pmx_leds &pmx_misc>; - pinctrl-names = "default"; - - pmx_buttons: pmx-buttons { - marvell,pins = "mpp11", "mpp12"; - marvell,function = "gpio"; - }; - - /* - * MPP0: Power LED - * MPP1: Error LED - */ - pmx_leds: pmx-leds { - marvell,pins = "mpp0", "mpp1"; - marvell,function = "gpio"; - }; - - /* - * MPP4: HDD ind. (Single/Dual) - * MPP5: HD0 5V control - * MPP6: HD0 12V control - * MPP7: HD1 5V control - * MPP8: HD1 12V control - */ - pmx_misc: pmx-misc { - marvell,pins = "mpp4", "mpp5", "mpp6", "mpp7", "mpp8", "mpp10"; - marvell,function = "gpio"; - }; - - pmx_rtc: pmx-rtc { - marvell,pins = "mpp3"; - marvell,function = "gpio"; - }; - - pmx_sata0_led_active: pmx-sata0-led-active { - marvell,pins = "mpp14"; - marvell,function = "sata0"; - }; - - pmx_sata1_led_active: pmx-sata1-led-active { - marvell,pins = "mpp15"; - marvell,function = "sata1"; - }; - - /* - * Non MPP GPIOs: - * GPIO 22: USB port 1 fuse (0 = Fail, 1 = Ok) - * GPIO 23: Blue front LED off - * GPIO 24: Inhibit board power off (0 = Disabled, 1 = Enabled) - */ -}; - -&sata { - pinctrl-0 = <&pmx_sata0_led_active - &pmx_sata1_led_active>; - pinctrl-names = "default"; - status = "okay"; - nr-ports = <2>; -}; - -&uart0 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/orion5x-mv88f5181.dtsi b/sys/gnu/dts/arm/orion5x-mv88f5181.dtsi deleted file mode 100644 index f667012b26c..00000000000 --- a/sys/gnu/dts/arm/orion5x-mv88f5181.dtsi +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright (C) 2016 Jamie Lentin - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include "orion5x.dtsi" - -/ { - compatible = "marvell,orion5x-88f5181", "marvell,orion5x"; - - soc { - compatible = "marvell,orion5x-88f5181-mbus", "simple-bus"; - - internal-regs { - pinctrl: pinctrl@10000 { - compatible = "marvell,88f5181-pinctrl"; - reg = <0x10000 0x8>, <0x10050 0x4>; - }; - - core_clk: core-clocks@10030 { - compatible = "marvell,mv88f5181-core-clock"; - reg = <0x10010 0x4>; - #clock-cells = <1>; - }; - - mbusc: mbus-controller@20000 { - compatible = "marvell,mbus-controller"; - reg = <0x20000 0x100>, <0x1500 0x20>; - }; - }; - }; -}; - -&pinctrl { - pmx_ge: pmx-ge { - marvell,pins = "mpp8", "mpp9", "mpp10", "mpp11", - "mpp12", "mpp13", "mpp14", "mpp15", - "mpp16", "mpp17", "mpp18", "mpp19"; - marvell,function = "ge"; - }; -}; - -ð { - pinctrl-0 = <&pmx_ge>; - pinctrl-names = "default"; -}; diff --git a/sys/gnu/dts/arm/orion5x-mv88f5182.dtsi b/sys/gnu/dts/arm/orion5x-mv88f5182.dtsi deleted file mode 100644 index d1ed71c6020..00000000000 --- a/sys/gnu/dts/arm/orion5x-mv88f5182.dtsi +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright (C) 2014 Thomas Petazzoni - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include "orion5x.dtsi" - -/ { - compatible = "marvell,orion5x-88f5182", "marvell,orion5x"; - - soc { - compatible = "marvell,orion5x-88f5182-mbus", "simple-bus"; - - internal-regs { - pinctrl: pinctrl@10000 { - compatible = "marvell,88f5182-pinctrl"; - reg = <0x10000 0x8>, <0x10050 0x4>; - - pmx_sata0: pmx-sata0 { - marvell,pins = "mpp12", "mpp14"; - marvell,function = "sata0"; - }; - - pmx_sata1: pmx-sata1 { - marvell,pins = "mpp13", "mpp15"; - marvell,function = "sata1"; - }; - }; - - core_clk: core-clocks@10030 { - compatible = "marvell,mv88f5182-core-clock"; - reg = <0x10010 0x4>; - #clock-cells = <1>; - }; - - mbusc: mbus-controller@20000 { - compatible = "marvell,mbus-controller"; - reg = <0x20000 0x100>, <0x1500 0x20>; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/orion5x-netgear-wnr854t.dts b/sys/gnu/dts/arm/orion5x-netgear-wnr854t.dts deleted file mode 100644 index ea081afa469..00000000000 --- a/sys/gnu/dts/arm/orion5x-netgear-wnr854t.dts +++ /dev/null @@ -1,252 +0,0 @@ -/* - * Copyright (C) 2016 Jamie Lentin - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -/dts-v1/; - -#include -#include -#include "orion5x-mv88f5181.dtsi" - -/ { - model = "Netgear WNR854-t"; - compatible = "netgear,wnr854t", "marvell,orion5x-88f5181", - "marvell,orion5x"; - aliases { - serial0 = &uart0; - }; - - memory { - device_type = "memory"; - reg = <0x00000000 0x2000000>; /* 32 MB */ - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - soc { - ranges = , - , - ; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-0 = <&pmx_reset_button>; - pinctrl-names = "default"; - - reset { - label = "Reset Button"; - linux,code = ; - gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_power_led &pmx_power_led_blink &pmx_wan_led>; - pinctrl-names = "default"; - - led@0 { - label = "wnr854t:green:power"; - gpios = <&gpio0 0 GPIO_ACTIVE_LOW>; - }; - - led@1 { - label = "wnr854t:blink:power"; - gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; - }; - - led@2 { - label = "wnr854t:green:wan"; - gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&devbus_bootcs { - status = "okay"; - - devbus,keep-config; - - flash@0 { - compatible = "cfi-flash"; - reg = <0 0x800000>; - bank-width = <2>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "kernel"; - reg = <0x0 0x100000>; - }; - - partition@100000 { - label = "rootfs"; - reg = <0x100000 0x660000>; - }; - - partition@760000 { - label = "uboot_env"; - reg = <0x760000 0x20000>; - }; - - partition@780000 { - label = "uboot"; - reg = <0x780000 0x80000>; - read-only; - }; - }; - }; -}; - -&mdio { - status = "okay"; - - switch: switch@0 { - compatible = "marvell,mv88e6085"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - dsa,member = <0 0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "lan3"; - phy-handle = <&lan3phy>; - }; - - port@1 { - reg = <1>; - label = "lan4"; - phy-handle = <&lan4phy>; - }; - - port@2 { - reg = <2>; - label = "wan"; - phy-handle = <&wanphy>; - }; - - port@3 { - reg = <3>; - label = "cpu"; - ethernet = <ðport>; - }; - - port@5 { - reg = <5>; - label = "lan1"; - phy-handle = <&lan1phy>; - }; - - port@7 { - reg = <7>; - label = "lan2"; - phy-handle = <&lan2phy>; - }; - }; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - lan3phy: ethernet-phy@0 { - /* Marvell 88E1121R (port 1) */ - compatible = "ethernet-phy-id0141.0cb0", - "ethernet-phy-ieee802.3-c22"; - reg = <0>; - marvell,reg-init = <3 16 0 0x1777 3 17 0 0x15>; - }; - - lan4phy: ethernet-phy@1 { - /* Marvell 88E1121R (port 2) */ - compatible = "ethernet-phy-id0141.0cb0", - "ethernet-phy-ieee802.3-c22"; - reg = <1>; - marvell,reg-init = <3 16 0 0x1777 3 17 0 0x15>; - }; - - wanphy: ethernet-phy@2 { - /* Marvell 88E1121R (port 1) */ - compatible = "ethernet-phy-id0141.0cb0", - "ethernet-phy-ieee802.3-c22"; - reg = <2>; - marvell,reg-init = <3 16 0 0x1777 3 17 0 0x15>; - }; - - lan1phy: ethernet-phy@5 { - /* Marvell 88E1112 */ - compatible = "ethernet-phy-id0141.0cb0", - "ethernet-phy-ieee802.3-c22"; - reg = <5>; - marvell,reg-init = <3 16 0 0x1777 3 17 0 0x15>; - }; - - lan2phy: ethernet-phy@7 { - /* Marvell 88E1112 */ - compatible = "ethernet-phy-id0141.0cb0", - "ethernet-phy-ieee802.3-c22"; - reg = <7>; - marvell,reg-init = <3 16 0 0x1777 3 17 0 0x15>; - }; - }; - }; -}; - -ð { - status = "okay"; - - ethernet-port@0 { - /* Hardwired to DSA switch */ - speed = <1000>; - duplex = <1>; - }; -}; - -&pinctrl { - pinctrl-0 = <&pmx_pci_gpios>; - pinctrl-names = "default"; - - pmx_power_led: pmx-power-led { - marvell,pins = "mpp0"; - marvell,function = "gpio"; - }; - - pmx_reset_button: pmx-reset-button { - marvell,pins = "mpp1"; - marvell,function = "gpio"; - }; - - pmx_power_led_blink: pmx-power-led-blink { - marvell,pins = "mpp2"; - marvell,function = "gpio"; - }; - - pmx_wan_led: pmx-wan-led { - marvell,pins = "mpp3"; - marvell,function = "gpio"; - }; - - pmx_pci_gpios: pmx-pci-gpios { - marvell,pins = "mpp4"; - marvell,function = "gpio"; - }; -}; - -&uart0 { - /* Pin 1: Tx, Pin 7: Rx, Pin 8: Gnd */ - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/orion5x-rd88f5182-nas.dts b/sys/gnu/dts/arm/orion5x-rd88f5182-nas.dts deleted file mode 100644 index 487324f7c54..00000000000 --- a/sys/gnu/dts/arm/orion5x-rd88f5182-nas.dts +++ /dev/null @@ -1,178 +0,0 @@ -/* - * Copyright (C) 2014 Thomas Petazzoni - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -/dts-v1/; - -#include -#include "orion5x-mv88f5182.dtsi" - -/ { - model = "Marvell Reference Design 88F5182 NAS"; - compatible = "marvell,rd-88f5182-nas", "marvell,orion5x-88f5182", "marvell,orion5x"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x4000000>; /* 64 MB */ - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; - }; - - soc { - ranges = , - , - , - ; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_debug_led>; - pinctrl-names = "default"; - - led@0 { - label = "rd88f5182:cpu"; - linux,default-trigger = "heartbeat"; - gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&devbus_bootcs { - status = "okay"; - - /* Read parameters */ - devbus,bus-width = <8>; - devbus,turn-off-ps = <90000>; - devbus,badr-skew-ps = <0>; - devbus,acc-first-ps = <186000>; - devbus,acc-next-ps = <186000>; - - /* Write parameters */ - devbus,wr-high-ps = <90000>; - devbus,wr-low-ps = <90000>; - devbus,ale-wr-ps = <90000>; - - flash@0 { - compatible = "cfi-flash"; - reg = <0 0x80000>; - bank-width = <1>; - }; -}; - -&devbus_cs1 { - status = "okay"; - - /* Read parameters */ - devbus,bus-width = <8>; - devbus,turn-off-ps = <90000>; - devbus,badr-skew-ps = <0>; - devbus,acc-first-ps = <186000>; - devbus,acc-next-ps = <186000>; - - /* Write parameters */ - devbus,wr-high-ps = <90000>; - devbus,wr-low-ps = <90000>; - devbus,ale-wr-ps = <90000>; - - flash@0 { - compatible = "cfi-flash"; - reg = <0 0x1000000>; - bank-width = <1>; - }; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -ð { - status = "okay"; - - ethernet-port@0 { - phy-handle = <ðphy>; - }; -}; - -&i2c { - status = "okay"; - clock-frequency = <100000>; - #address-cells = <1>; - - rtc@68 { - pinctrl-0 = <&pmx_rtc>; - pinctrl-names = "default"; - compatible = "dallas,ds1338"; - reg = <0x68>; - }; -}; - -&mdio { - status = "okay"; - - ethphy: ethernet-phy { - reg = <8>; - }; -}; - -&pinctrl { - pinctrl-0 = <&pmx_reset_switch &pmx_misc_gpios - &pmx_pci_gpios>; - pinctrl-names = "default"; - - /* - * MPP[20] PCI Clock to MV88F5182 - * MPP[21] PCI Clock to mini PCI CON11 - * MPP[22] USB 0 over current indication - * MPP[23] USB 1 over current indication - * MPP[24] USB 1 over current enable - * MPP[25] USB 0 over current enable - */ - - pmx_debug_led: pmx-debug_led { - marvell,pins = "mpp0"; - marvell,function = "gpio"; - }; - - pmx_reset_switch: pmx-reset-switch { - marvell,pins = "mpp1"; - marvell,function = "gpio"; - }; - - pmx_rtc: pmx-rtc { - marvell,pins = "mpp3"; - marvell,function = "gpio"; - }; - - pmx_misc_gpios: pmx-misc-gpios { - marvell,pins = "mpp4", "mpp5"; - marvell,function = "gpio"; - }; - - pmx_pci_gpios: pmx-pci-gpios { - marvell,pins = "mpp6", "mpp7"; - marvell,function = "gpio"; - }; -}; - -&sata { - pinctrl-0 = <&pmx_sata0 &pmx_sata1>; - pinctrl-names = "default"; - status = "okay"; - nr-ports = <2>; -}; - -&uart0 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/orion5x.dtsi b/sys/gnu/dts/arm/orion5x.dtsi deleted file mode 100644 index 61e631b3fd8..00000000000 --- a/sys/gnu/dts/arm/orion5x.dtsi +++ /dev/null @@ -1,241 +0,0 @@ -/* - * Copyright (C) 2012 Thomas Petazzoni - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) - -/ { - #address-cells = <1>; - #size-cells = <1>; - model = "Marvell Orion5x SoC"; - compatible = "marvell,orion5x"; - interrupt-parent = <&intc>; - - aliases { - gpio0 = &gpio0; - }; - - soc { - #address-cells = <2>; - #size-cells = <1>; - controller = <&mbusc>; - - devbus_bootcs: devbus-bootcs { - compatible = "marvell,orion-devbus"; - reg = ; - ranges = <0 MBUS_ID(0x01, 0x0f) 0 0xffffffff>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&core_clk 0>; - status = "disabled"; - }; - - devbus_cs0: devbus-cs0 { - compatible = "marvell,orion-devbus"; - reg = ; - ranges = <0 MBUS_ID(0x01, 0x1e) 0 0xffffffff>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&core_clk 0>; - status = "disabled"; - }; - - devbus_cs1: devbus-cs1 { - compatible = "marvell,orion-devbus"; - reg = ; - ranges = <0 MBUS_ID(0x01, 0x1d) 0 0xffffffff>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&core_clk 0>; - status = "disabled"; - }; - - devbus_cs2: devbus-cs2 { - compatible = "marvell,orion-devbus"; - reg = ; - ranges = <0 MBUS_ID(0x01, 0x1b) 0 0xffffffff>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&core_clk 0>; - status = "disabled"; - }; - - internal-regs { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>; - - gpio0: gpio@10100 { - compatible = "marvell,orion-gpio"; - #gpio-cells = <2>; - gpio-controller; - reg = <0x10100 0x40>; - ngpios = <32>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <6>, <7>, <8>, <9>; - }; - - spi: spi@10600 { - compatible = "marvell,orion-spi"; - #address-cells = <1>; - #size-cells = <0>; - cell-index = <0>; - reg = <0x10600 0x28>; - status = "disabled"; - }; - - i2c: i2c@11000 { - compatible = "marvell,mv64xxx-i2c"; - reg = <0x11000 0x20>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <5>; - clocks = <&core_clk 0>; - status = "disabled"; - }; - - uart0: serial@12000 { - compatible = "ns16550a"; - reg = <0x12000 0x100>; - reg-shift = <2>; - interrupts = <3>; - clocks = <&core_clk 0>; - status = "disabled"; - }; - - uart1: serial@12100 { - compatible = "ns16550a"; - reg = <0x12100 0x100>; - reg-shift = <2>; - interrupts = <4>; - clocks = <&core_clk 0>; - status = "disabled"; - }; - - bridge_intc: bridge-interrupt-ctrl@20110 { - compatible = "marvell,orion-bridge-intc"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x20110 0x8>; - interrupts = <0>; - marvell,#interrupts = <4>; - }; - - intc: interrupt-controller@20200 { - compatible = "marvell,orion-intc"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x20200 0x08>; - }; - - timer: timer@20300 { - compatible = "marvell,orion-timer"; - reg = <0x20300 0x20>; - interrupt-parent = <&bridge_intc>; - interrupts = <1>, <2>; - clocks = <&core_clk 0>; - }; - - wdt: wdt@20300 { - compatible = "marvell,orion-wdt"; - reg = <0x20300 0x28>, <0x20108 0x4>; - interrupt-parent = <&bridge_intc>; - interrupts = <3>; - clocks = <&core_clk 0>; - status = "okay"; - }; - - ehci0: ehci@50000 { - compatible = "marvell,orion-ehci"; - reg = <0x50000 0x1000>; - interrupts = <17>; - status = "disabled"; - }; - - xor: dma-controller@60900 { - compatible = "marvell,orion-xor"; - reg = <0x60900 0x100 - 0x60b00 0x100>; - status = "okay"; - - xor00 { - interrupts = <30>; - dmacap,memcpy; - dmacap,xor; - }; - xor01 { - interrupts = <31>; - dmacap,memcpy; - dmacap,xor; - dmacap,memset; - }; - }; - - eth: ethernet-controller@72000 { - compatible = "marvell,orion-eth"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x72000 0x4000>; - marvell,tx-checksum-limit = <1600>; - status = "disabled"; - - ethport: ethernet-port@0 { - compatible = "marvell,orion-eth-port"; - reg = <0>; - interrupts = <21>; - /* overwrite MAC address in bootloader */ - local-mac-address = [00 00 00 00 00 00]; - /* set phy-handle property in board file */ - }; - }; - - mdio: mdio-bus@72004 { - compatible = "marvell,orion-mdio"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x72004 0x84>; - interrupts = <22>; - status = "disabled"; - - /* add phy nodes in board file */ - }; - - sata: sata@80000 { - compatible = "marvell,orion-sata"; - reg = <0x80000 0x5000>; - interrupts = <29>; - status = "disabled"; - }; - - cesa: crypto@90000 { - compatible = "marvell,orion-crypto"; - reg = <0x90000 0x10000>; - reg-names = "regs"; - interrupts = <28>; - marvell,crypto-srams = <&crypto_sram>; - marvell,crypto-sram-size = <0x800>; - status = "okay"; - }; - - ehci1: ehci@a0000 { - compatible = "marvell,orion-ehci"; - reg = <0xa0000 0x1000>; - interrupts = <12>; - status = "disabled"; - }; - }; - - crypto_sram: sa-sram { - compatible = "mmio-sram"; - reg = ; - #address-cells = <1>; - #size-cells = <1>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/owl-s500-cubieboard6.dts b/sys/gnu/dts/arm/owl-s500-cubieboard6.dts deleted file mode 100644 index 7c96c59b610..00000000000 --- a/sys/gnu/dts/arm/owl-s500-cubieboard6.dts +++ /dev/null @@ -1,43 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Cubietech CubieBoard6 - * - * Copyright (c) 2017 Andreas Färber - */ - -/dts-v1/; - -#include "owl-s500.dtsi" - -/ { - compatible = "cubietech,cubieboard6", "actions,s500"; - model = "CubieBoard6"; - - aliases { - serial3 = &uart3; - }; - - chosen { - stdout-path = "serial3:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x80000000>; - }; - - uart3_clk: uart3-clk { - compatible = "fixed-clock"; - clock-frequency = <921600>; - #clock-cells = <0>; - }; -}; - -&timer { - clocks = <&hosc>; -}; - -&uart3 { - status = "okay"; - clocks = <&uart3_clk>; -}; diff --git a/sys/gnu/dts/arm/owl-s500-guitar-bb-rev-b.dts b/sys/gnu/dts/arm/owl-s500-guitar-bb-rev-b.dts deleted file mode 100644 index e610d49395d..00000000000 --- a/sys/gnu/dts/arm/owl-s500-guitar-bb-rev-b.dts +++ /dev/null @@ -1,32 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016-2017 Andreas Färber - */ - -/dts-v1/; - -#include "owl-s500-guitar.dtsi" - -/ { - compatible = "lemaker,guitar-bb-rev-b", "lemaker,guitar", "actions,s500"; - model = "LeMaker Guitar Base Board rev. B"; - - aliases { - serial3 = &uart3; - }; - - chosen { - stdout-path = "serial3:115200n8"; - }; - - uart3_clk: uart3-clk { - compatible = "fixed-clock"; - clock-frequency = <921600>; - #clock-cells = <0>; - }; -}; - -&uart3 { - status = "okay"; - clocks = <&uart3_clk>; -}; diff --git a/sys/gnu/dts/arm/owl-s500-guitar.dtsi b/sys/gnu/dts/arm/owl-s500-guitar.dtsi deleted file mode 100644 index 81cc39871f1..00000000000 --- a/sys/gnu/dts/arm/owl-s500-guitar.dtsi +++ /dev/null @@ -1,21 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * LeMaker Guitar SoM - * - * Copyright (c) 2016-2017 Andreas Färber - */ - -#include "owl-s500.dtsi" - -/ { - compatible = "lemaker,guitar", "actions,s500"; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x40000000>; - }; -}; - -&timer { - clocks = <&hosc>; -}; diff --git a/sys/gnu/dts/arm/owl-s500-sparky.dts b/sys/gnu/dts/arm/owl-s500-sparky.dts deleted file mode 100644 index c665ce8b88b..00000000000 --- a/sys/gnu/dts/arm/owl-s500-sparky.dts +++ /dev/null @@ -1,43 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Allo.com Sparky - * - * Copyright (c) 2017 Andreas Färber - */ - -/dts-v1/; - -#include "owl-s500.dtsi" - -/ { - compatible = "allo,sparky", "actions,s500"; - model = "Allo.com Sparky"; - - aliases { - serial3 = &uart3; - }; - - chosen { - stdout-path = "serial3:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x40000000>; /* 1 or 2 GiB */ - }; - - uart3_clk: uart3-clk { - compatible = "fixed-clock"; - clock-frequency = <921600>; - #clock-cells = <0>; - }; -}; - -&timer { - clocks = <&hosc>; -}; - -&uart3 { - status = "okay"; - clocks = <&uart3_clk>; -}; diff --git a/sys/gnu/dts/arm/owl-s500.dtsi b/sys/gnu/dts/arm/owl-s500.dtsi deleted file mode 100644 index 5ceb6cc4451..00000000000 --- a/sys/gnu/dts/arm/owl-s500.dtsi +++ /dev/null @@ -1,188 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Actions Semi S500 SoC - * - * Copyright (c) 2016-2017 Andreas Färber - */ - -#include -#include - -/ { - compatible = "actions,s500"; - interrupt-parent = <&gic>; - #address-cells = <1>; - #size-cells = <1>; - - aliases { - }; - - chosen { - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0x0>; - enable-method = "actions,s500-smp"; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0x1>; - enable-method = "actions,s500-smp"; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0x2>; - enable-method = "actions,s500-smp"; - power-domains = <&sps S500_PD_CPU2>; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0x3>; - enable-method = "actions,s500-smp"; - power-domains = <&sps S500_PD_CPU3>; - }; - }; - - arm-pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts = , - , - , - ; - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; - }; - - hosc: hosc { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - #clock-cells = <0>; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - scu: scu@b0020000 { - compatible = "arm,cortex-a9-scu"; - reg = <0xb0020000 0x100>; - }; - - global_timer: timer@b0020200 { - compatible = "arm,cortex-a9-global-timer"; - reg = <0xb0020200 0x100>; - interrupts = ; - status = "disabled"; - }; - - twd_timer: timer@b0020600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0xb0020600 0x20>; - interrupts = ; - status = "disabled"; - }; - - twd_wdt: wdt@b0020620 { - compatible = "arm,cortex-a9-twd-wdt"; - reg = <0xb0020620 0xe0>; - interrupts = ; - status = "disabled"; - }; - - gic: interrupt-controller@b0021000 { - compatible = "arm,cortex-a9-gic"; - reg = <0xb0021000 0x1000>, - <0xb0020100 0x0100>; - interrupt-controller; - #interrupt-cells = <3>; - }; - - l2: cache-controller@b0022000 { - compatible = "arm,pl310-cache"; - reg = <0xb0022000 0x1000>; - cache-unified; - cache-level = <2>; - interrupts = ; - arm,tag-latency = <3 3 2>; - arm,data-latency = <5 3 3>; - }; - - uart0: serial@b0120000 { - compatible = "actions,s500-uart", "actions,owl-uart"; - reg = <0xb0120000 0x2000>; - interrupts = ; - status = "disabled"; - }; - - uart1: serial@b0122000 { - compatible = "actions,s500-uart", "actions,owl-uart"; - reg = <0xb0122000 0x2000>; - interrupts = ; - status = "disabled"; - }; - - uart2: serial@b0124000 { - compatible = "actions,s500-uart", "actions,owl-uart"; - reg = <0xb0124000 0x2000>; - interrupts = ; - status = "disabled"; - }; - - uart3: serial@b0126000 { - compatible = "actions,s500-uart", "actions,owl-uart"; - reg = <0xb0126000 0x2000>; - interrupts = ; - status = "disabled"; - }; - - uart4: serial@b0128000 { - compatible = "actions,s500-uart", "actions,owl-uart"; - reg = <0xb0128000 0x2000>; - interrupts = ; - status = "disabled"; - }; - - uart5: serial@b012a000 { - compatible = "actions,s500-uart", "actions,owl-uart"; - reg = <0xb012a000 0x2000>; - interrupts = ; - status = "disabled"; - }; - - uart6: serial@b012c000 { - compatible = "actions,s500-uart", "actions,owl-uart"; - reg = <0xb012c000 0x2000>; - interrupts = ; - status = "disabled"; - }; - - timer: timer@b0168000 { - compatible = "actions,s500-timer"; - reg = <0xb0168000 0x8000>; - interrupts = , - , - , - ; - interrupt-names = "2hz0", "2hz1", "timer0", "timer1"; - }; - - sps: power-controller@b01b0100 { - compatible = "actions,s500-sps"; - reg = <0xb01b0100 0x100>; - #power-domain-cells = <1>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/ox810se-wd-mbwe.dts b/sys/gnu/dts/arm/ox810se-wd-mbwe.dts deleted file mode 100644 index 7e2fcb220ae..00000000000 --- a/sys/gnu/dts/arm/ox810se-wd-mbwe.dts +++ /dev/null @@ -1,111 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * wd-mbwe.dtsi - Device tree file for Western Digital My Book World Edition - * - * Copyright (C) 2016 Neil Armstrong - */ - -/dts-v1/; -#include "ox810se.dtsi" - -/ { - model = "Western Digital My Book World Edition"; - - compatible = "wd,mbwe", "oxsemi,ox810se"; - - chosen { - bootargs = "console=ttyS1,115200n8 earlyprintk=serial"; - }; - - memory { - /* 128Mbytes DDR */ - reg = <0x48000000 0x8000000>; - }; - - aliases { - serial1 = &uart1; - gpio0 = &gpio0; - gpio1 = &gpio1; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <100>; - - power { - label = "power"; - gpios = <&gpio0 0 1>; - linux,code = <0x198>; - }; - - recovery { - label = "recovery"; - gpios = <&gpio0 4 1>; - linux,code = <0xab>; - }; - }; - - leds { - compatible = "gpio-leds"; - - a0 { - label = "activity0"; - gpios = <&gpio0 25 0>; - default-state = "keep"; - }; - - a1 { - label = "activity1"; - gpios = <&gpio0 26 0>; - default-state = "keep"; - }; - - a2 { - label = "activity2"; - gpios = <&gpio0 5 0>; - default-state = "keep"; - }; - - a3 { - label = "activity3"; - gpios = <&gpio0 6 0>; - default-state = "keep"; - }; - - a4 { - label = "activity4"; - gpios = <&gpio0 7 0>; - default-state = "keep"; - }; - - a5 { - label = "activity5"; - gpios = <&gpio1 2 0>; - default-state = "keep"; - }; - }; - - i2c-gpio { - compatible = "i2c-gpio"; - gpios = <&gpio0 3 0 /* sda */ - &gpio0 2 0 /* scl */ - >; - i2c-gpio,delay-us = <2>; /* ~100 kHz */ - #address-cells = <1>; - #size-cells = <0>; - - rtc0: rtc@48 { - compatible = "st,m41t00"; - reg = <0x68>; - }; - }; -}; - -&uart1 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; -}; diff --git a/sys/gnu/dts/arm/ox810se.dtsi b/sys/gnu/dts/arm/ox810se.dtsi deleted file mode 100644 index 0755e5864c4..00000000000 --- a/sys/gnu/dts/arm/ox810se.dtsi +++ /dev/null @@ -1,339 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * ox810se.dtsi - Device tree file for Oxford Semiconductor OX810SE SoC - * - * Copyright (C) 2016 Neil Armstrong - */ - -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - compatible = "oxsemi,ox810se"; - - cpus { - #address-cells = <0>; - #size-cells = <0>; - - cpu { - device_type = "cpu"; - compatible = "arm,arm926ej-s"; - clocks = <&armclk>; - }; - }; - - memory { - device_type = "memory"; - /* Max 256MB @ 0x48000000 */ - reg = <0x48000000 0x10000000>; - }; - - clocks { - osc: oscillator { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - - gmacclk: gmacclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <125000000>; - }; - - rpsclk: rpsclk { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clock-div = <1>; - clock-mult = <1>; - clocks = <&osc>; - }; - - pll400: pll400 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <733333333>; - }; - - sysclk: sysclk { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clock-div = <4>; - clock-mult = <1>; - clocks = <&pll400>; - }; - - armclk: armclk { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - clocks = <&pll400>; - }; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges; - interrupt-parent = <&intc>; - - apb-bridge@44000000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0 0x44000000 0x1000000>; - - pinctrl: pinctrl { - compatible = "oxsemi,ox810se-pinctrl"; - - /* Regmap for sys registers */ - oxsemi,sys-ctrl = <&sys>; - - pinctrl_uart0: uart0 { - uart0a { - pins = "gpio31"; - function = "fct3"; - }; - uart0b { - pins = "gpio32"; - function = "fct3"; - }; - }; - - pinctrl_uart0_modem: uart0_modem { - uart0c { - pins = "gpio27"; - function = "fct3"; - }; - uart0d { - pins = "gpio28"; - function = "fct3"; - }; - uart0e { - pins = "gpio29"; - function = "fct3"; - }; - uart0f { - pins = "gpio30"; - function = "fct3"; - }; - uart0g { - pins = "gpio33"; - function = "fct3"; - }; - uart0h { - pins = "gpio34"; - function = "fct3"; - }; - }; - - pinctrl_uart1: uart1 { - uart1a { - pins = "gpio20"; - function = "fct3"; - }; - uart1b { - pins = "gpio22"; - function = "fct3"; - }; - }; - - pinctrl_uart1_modem: uart1_modem { - uart1c { - pins = "gpio8"; - function = "fct3"; - }; - uart1d { - pins = "gpio9"; - function = "fct3"; - }; - uart1e { - pins = "gpio23"; - function = "fct3"; - }; - uart1f { - pins = "gpio24"; - function = "fct3"; - }; - uart1g { - pins = "gpio25"; - function = "fct3"; - }; - uart1h { - pins = "gpio26"; - function = "fct3"; - }; - }; - - pinctrl_uart2: uart2 { - uart2a { - pins = "gpio6"; - function = "fct3"; - }; - uart2b { - pins = "gpio7"; - function = "fct3"; - }; - }; - - pinctrl_uart2_modem: uart2_modem { - uart2c { - pins = "gpio0"; - function = "fct3"; - }; - uart2d { - pins = "gpio1"; - function = "fct3"; - }; - uart2e { - pins = "gpio2"; - function = "fct3"; - }; - uart2f { - pins = "gpio3"; - function = "fct3"; - }; - uart2g { - pins = "gpio4"; - function = "fct3"; - }; - uart2h { - pins = "gpio5"; - function = "fct3"; - }; - }; - }; - - gpio0: gpio@0 { - compatible = "oxsemi,ox810se-gpio"; - reg = <0x000000 0x100000>; - interrupts = <21>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - ngpios = <32>; - oxsemi,gpio-bank = <0>; - gpio-ranges = <&pinctrl 0 0 32>; - }; - - gpio1: gpio@100000 { - compatible = "oxsemi,ox810se-gpio"; - reg = <0x100000 0x100000>; - interrupts = <22>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - ngpios = <3>; - oxsemi,gpio-bank = <1>; - gpio-ranges = <&pinctrl 0 32 3>; - }; - - uart0: serial@200000 { - compatible = "ns16550a"; - reg = <0x200000 0x100000>; - clocks = <&sysclk>; - interrupts = <23>; - reg-shift = <0>; - fifo-size = <16>; - reg-io-width = <1>; - current-speed = <115200>; - no-loopback-test; - status = "disabled"; - resets = <&reset RESET_UART1>; - }; - - uart1: serial@300000 { - compatible = "ns16550a"; - reg = <0x300000 0x100000>; - clocks = <&sysclk>; - interrupts = <24>; - reg-shift = <0>; - fifo-size = <16>; - reg-io-width = <1>; - current-speed = <115200>; - no-loopback-test; - status = "disabled"; - resets = <&reset RESET_UART2>; - }; - - uart2: serial@900000 { - compatible = "ns16550a"; - reg = <0x900000 0x100000>; - clocks = <&sysclk>; - interrupts = <29>; - reg-shift = <0>; - fifo-size = <16>; - reg-io-width = <1>; - current-speed = <115200>; - no-loopback-test; - status = "disabled"; - resets = <&reset RESET_UART3>; - }; - - uart3: serial@a00000 { - compatible = "ns16550a"; - reg = <0xa00000 0x100000>; - clocks = <&sysclk>; - interrupts = <30>; - reg-shift = <0>; - fifo-size = <16>; - reg-io-width = <1>; - current-speed = <115200>; - no-loopback-test; - status = "disabled"; - resets = <&reset RESET_UART4>; - }; - }; - - apb-bridge@45000000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0 0x45000000 0x1000000>; - - sys: sys-ctrl@0 { - compatible = "oxsemi,ox810se-sys-ctrl", "syscon", "simple-mfd"; - reg = <0x000000 0x100000>; - - reset: reset-controller { - compatible = "oxsemi,ox810se-reset"; - #reset-cells = <1>; - }; - - stdclk: stdclk { - compatible = "oxsemi,ox810se-stdclk"; - #clock-cells = <1>; - }; - }; - - rps@300000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0 0x300000 0x100000>; - - intc: interrupt-controller@0 { - compatible = "oxsemi,ox810se-rps-irq"; - interrupt-controller; - reg = <0 0x200>; - #interrupt-cells = <1>; - valid-mask = <0xffffffff>; - clear-mask = <0xffffffff>; - }; - - timer0: timer@200 { - compatible = "oxsemi,ox810se-rps-timer"; - reg = <0x200 0x40>; - clocks = <&rpsclk>; - interrupts = <4 5>; - }; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/ox820-cloudengines-pogoplug-series-3.dts b/sys/gnu/dts/arm/ox820-cloudengines-pogoplug-series-3.dts deleted file mode 100644 index c3daceccde5..00000000000 --- a/sys/gnu/dts/arm/ox820-cloudengines-pogoplug-series-3.dts +++ /dev/null @@ -1,93 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * cloudengines-pogoplug-series-3.dtsi - Device tree file for Cloud Engines PogoPlug Series 3 - * - * Copyright (C) 2016 Neil Armstrong - */ - -/dts-v1/; -#include "ox820.dtsi" - -/ { - model = "Cloud Engines PogoPlug Series 3"; - - compatible = "cloudengines,pogoplugv3", "oxsemi,ox820"; - - chosen { - bootargs = "earlyprintk"; - stdout-path = "serial0:115200n8"; - }; - - memory { - /* 128Mbytes DDR */ - reg = <0x60000000 0x8000000>; - }; - - aliases { - serial0 = &uart0; - gpio0 = &gpio0; - gpio1 = &gpio1; - }; - - leds { - compatible = "gpio-leds"; - - blue { - label = "pogoplug:blue"; - gpios = <&gpio0 2 0>; - default-state = "keep"; - }; - - orange { - label = "pogoplug:orange"; - gpios = <&gpio1 16 1>; - default-state = "keep"; - }; - - green { - label = "pogoplug:green"; - gpios = <&gpio1 17 1>; - default-state = "keep"; - }; - }; -}; - -&uart0 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0>; -}; - -&nandc { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nand>; - - nand@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; - nand-ecc-mode = "soft"; - nand-ecc-algo = "hamming"; - - partition@0 { - label = "boot"; - reg = <0x00000000 0x00e00000>; - read-only; - }; - - partition@e00000 { - label = "ubi"; - reg = <0x00e00000 0x07200000>; - }; - }; -}; - -ða { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_etha_mdio>; -}; diff --git a/sys/gnu/dts/arm/ox820.dtsi b/sys/gnu/dts/arm/ox820.dtsi deleted file mode 100644 index 90846a7655b..00000000000 --- a/sys/gnu/dts/arm/ox820.dtsi +++ /dev/null @@ -1,299 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * ox820.dtsi - Device tree file for Oxford Semiconductor OX820 SoC - * - * Copyright (C) 2016 Neil Armstrong - */ - -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - compatible = "oxsemi,ox820"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "oxsemi,ox820-smp"; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,arm11mpcore"; - clocks = <&armclk>; - reg = <0>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arm,arm11mpcore"; - clocks = <&armclk>; - reg = <1>; - }; - }; - - memory { - device_type = "memory"; - /* Max 512MB @ 0x60000000 */ - reg = <0x60000000 0x20000000>; - }; - - clocks { - osc: oscillator { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - - gmacclk: gmacclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <125000000>; - }; - - sysclk: sysclk { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clock-div = <4>; - clock-mult = <1>; - clocks = <&osc>; - }; - - plla: plla { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <850000000>; - }; - - armclk: armclk { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - clocks = <&plla>; - }; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges; - interrupt-parent = <&gic>; - - nandc: nand-controller@41000000 { - compatible = "oxsemi,ox820-nand"; - reg = <0x41000000 0x100000>; - clocks = <&stdclk CLK_820_NAND>; - resets = <&reset RESET_NAND>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - etha: ethernet@40400000 { - compatible = "oxsemi,ox820-dwmac", "snps,dwmac"; - reg = <0x40400000 0x2000>; - interrupts = , - ; - interrupt-names = "macirq", "eth_wake_irq"; - mac-address = [000000000000]; /* Filled in by U-Boot */ - phy-mode = "rgmii"; - - clocks = <&stdclk CLK_820_ETHA>, <&gmacclk>; - clock-names = "gmac", "stmmaceth"; - resets = <&reset RESET_MAC>; - - /* Regmap for sys registers */ - oxsemi,sys-ctrl = <&sys>; - - status = "disabled"; - }; - - apb-bridge@44000000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0 0x44000000 0x1000000>; - - pinctrl: pinctrl { - compatible = "oxsemi,ox820-pinctrl"; - - /* Regmap for sys registers */ - oxsemi,sys-ctrl = <&sys>; - - pinctrl_uart0: uart0 { - uart0 { - pins = "gpio30", "gpio31"; - function = "fct5"; - }; - }; - - pinctrl_uart0_modem: uart0_modem { - uart0_modem_a { - pins = "gpio24", "gpio24", "gpio26", "gpio27"; - function = "fct4"; - }; - uart0_modem_b { - pins = "gpio28", "gpio29"; - function = "fct5"; - }; - }; - - pinctrl_uart1: uart1 { - uart1 { - pins = "gpio7", "gpio8"; - function = "fct4"; - }; - }; - - pinctrl_uart1_modem: uart1_modem { - uart1_modem { - pins = "gpio5", "gpio6", "gpio40", "gpio41", "gpio42", "gpio43"; - function = "fct4"; - }; - }; - - pinctrl_etha_mdio: etha_mdio { - etha_mdio { - pins = "gpio3", "gpio4"; - function = "fct1"; - }; - }; - - pinctrl_nand: nand { - nand { - pins = "gpio12", "gpio13", "gpio14", "gpio15", - "gpio16", "gpio17", "gpio18", "gpio19", - "gpio20", "gpio21", "gpio22", "gpio23", - "gpio24"; - function = "fct1"; - }; - }; - }; - - gpio0: gpio@0 { - compatible = "oxsemi,ox820-gpio"; - reg = <0x000000 0x100000>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - ngpios = <32>; - oxsemi,gpio-bank = <0>; - gpio-ranges = <&pinctrl 0 0 32>; - }; - - gpio1: gpio@100000 { - compatible = "oxsemi,ox820-gpio"; - reg = <0x100000 0x100000>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - ngpios = <18>; - oxsemi,gpio-bank = <1>; - gpio-ranges = <&pinctrl 0 32 18>; - }; - - uart0: serial@200000 { - compatible = "ns16550a"; - reg = <0x200000 0x100000>; - interrupts = ; - reg-shift = <0>; - fifo-size = <16>; - reg-io-width = <1>; - current-speed = <115200>; - no-loopback-test; - status = "disabled"; - clocks = <&sysclk>; - resets = <&reset RESET_UART1>; - }; - - uart1: serial@300000 { - compatible = "ns16550a"; - reg = <0x200000 0x100000>; - interrupts = ; - reg-shift = <0>; - fifo-size = <16>; - reg-io-width = <1>; - current-speed = <115200>; - no-loopback-test; - status = "disabled"; - clocks = <&sysclk>; - resets = <&reset RESET_UART2>; - }; - - rps@400000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0 0x400000 0x100000>; - - intc: interrupt-controller@0 { - compatible = "oxsemi,ox820-rps-irq", "oxsemi,ox810se-rps-irq"; - interrupt-controller; - reg = <0 0x200>; - interrupts = ; - #interrupt-cells = <1>; - valid-mask = <0xffffffff>; - clear-mask = <0xffffffff>; - }; - - timer0: timer@200 { - compatible = "oxsemi,ox820-rps-timer"; - reg = <0x200 0x40>; - clocks = <&sysclk>; - interrupt-parent = <&intc>; - interrupts = <4>; - }; - }; - - sys: sys-ctrl@e00000 { - compatible = "oxsemi,ox820-sys-ctrl", "syscon", "simple-mfd"; - reg = <0xe00000 0x200000>; - - reset: reset-controller { - compatible = "oxsemi,ox820-reset", "oxsemi,ox810se-reset"; - #reset-cells = <1>; - }; - - stdclk: stdclk { - compatible = "oxsemi,ox820-stdclk", "oxsemi,ox810se-stdclk"; - #clock-cells = <1>; - }; - }; - }; - - apb-bridge@47000000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0 0x47000000 0x1000000>; - - scu: scu@0 { - compatible = "arm,arm11mp-scu"; - reg = <0x0 0x100>; - }; - - local-timer@600 { - compatible = "arm,arm11mp-twd-timer"; - reg = <0x600 0x20>; - interrupts = ; - clocks = <&armclk>; - }; - - gic: gic@1000 { - compatible = "arm,arm11mp-gic"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0x1000 0x1000>, - <0x100 0x500>; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/phy3250.dts b/sys/gnu/dts/arm/phy3250.dts deleted file mode 100644 index 7d253bb6265..00000000000 --- a/sys/gnu/dts/arm/phy3250.dts +++ /dev/null @@ -1,195 +0,0 @@ -/* - * PHYTEC phyCORE-LPC3250 board - * - * Copyright 2012 Roland Stigge - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; -#include "lpc32xx.dtsi" - -/ { - model = "PHYTEC phyCORE-LPC3250 board based on NXP LPC3250"; - compatible = "phytec,phy3250", "nxp,lpc3250"; - #address-cells = <1>; - #size-cells = <1>; - - memory { - device_type = "memory"; - reg = <0x80000000 0x4000000>; - }; - - ahb { - mac: ethernet@31060000 { - phy-mode = "rmii"; - use-iram; - }; - - clcd@31040000 { - status = "okay"; - }; - - /* 64MB Flash via SLC NAND controller */ - slc: flash@20020000 { - status = "okay"; - #address-cells = <1>; - #size-cells = <1>; - - nxp,wdr-clks = <14>; - nxp,wwidth = <40000000>; - nxp,whold = <100000000>; - nxp,wsetup = <100000000>; - nxp,rdr-clks = <14>; - nxp,rwidth = <40000000>; - nxp,rhold = <66666666>; - nxp,rsetup = <100000000>; - nand-on-flash-bbt; - gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */ - - mtd0@00000000 { - label = "phy3250-boot"; - reg = <0x00000000 0x00064000>; - read-only; - }; - - mtd1@00064000 { - label = "phy3250-uboot"; - reg = <0x00064000 0x00190000>; - read-only; - }; - - mtd2@001f4000 { - label = "phy3250-ubt-prms"; - reg = <0x001f4000 0x00010000>; - }; - - mtd3@00204000 { - label = "phy3250-kernel"; - reg = <0x00204000 0x00400000>; - }; - - mtd4@00604000 { - label = "phy3250-rootfs"; - reg = <0x00604000 0x039fc000>; - }; - }; - - apb { - uart5: serial@40090000 { - status = "okay"; - }; - - uart3: serial@40080000 { - status = "okay"; - }; - - i2c1: i2c@400A0000 { - clock-frequency = <100000>; - - pcf8563: rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; - - uda1380: uda1380@18 { - compatible = "nxp,uda1380"; - reg = <0x18>; - power-gpio = <&gpio 0x59 0>; - reset-gpio = <&gpio 0x51 0>; - dac-clk = "wspll"; - }; - }; - - i2c2: i2c@400A8000 { - clock-frequency = <100000>; - }; - - ssp0: ssp@20084000 { - #address-cells = <1>; - #size-cells = <0>; - num-cs = <1>; - cs-gpios = <&gpio 3 5 0>; - - eeprom: at25@0 { - pl022,interface = <0>; - pl022,com-mode = <0>; - pl022,rx-level-trig = <1>; - pl022,tx-level-trig = <1>; - pl022,ctrl-len = <11>; - pl022,wait-state = <0>; - pl022,duplex = <0>; - - at25,byte-len = <0x8000>; - at25,addr-mode = <2>; - at25,page-size = <64>; - - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <5000000>; - }; - }; - - sd@20098000 { - wp-gpios = <&gpio 3 0 0>; - cd-gpios = <&gpio 3 1 0>; - cd-inverted; - bus-width = <4>; - status = "okay"; - }; - }; - - fab { - uart2: serial@40018000 { - status = "okay"; - }; - - tsc@40048000 { - status = "okay"; - }; - - key@40050000 { - status = "okay"; - keypad,num-rows = <1>; - keypad,num-columns = <1>; - nxp,debounce-delay-ms = <3>; - nxp,scan-delay-ms = <34>; - linux,keymap = <0x00000002>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - led0 { /* red */ - gpios = <&gpio 5 1 0>; /* GPO_P3 1, GPIO 80, active high */ - default-state = "off"; - }; - - led1 { /* green */ - gpios = <&gpio 5 14 0>; /* GPO_P3 14, GPIO 93, active high */ - linux,default-trigger = "heartbeat"; - }; - }; -}; - -/* Here, choose exactly one from: ohci, usbd */ -&ohci /* &usbd */ { - transceiver = <&isp1301>; - status = "okay"; -}; - -&i2cusb { - clock-frequency = <100000>; - - isp1301: usb-transceiver@2c { - compatible = "nxp,isp1301"; - reg = <0x2c>; - }; -}; diff --git a/sys/gnu/dts/arm/picoxcell-pc3x2.dtsi b/sys/gnu/dts/arm/picoxcell-pc3x2.dtsi deleted file mode 100644 index 5ae86078833..00000000000 --- a/sys/gnu/dts/arm/picoxcell-pc3x2.dtsi +++ /dev/null @@ -1,240 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2011 Picochip, Jamie Iles - */ -/ { - model = "Picochip picoXcell PC3X2"; - compatible = "picochip,pc3x2"; - #address-cells = <1>; - #size-cells = <1>; - - cpus { - #address-cells = <0>; - #size-cells = <0>; - - cpu { - compatible = "arm,arm1176jz-s"; - device_type = "cpu"; - clock-frequency = <400000000>; - d-cache-line-size = <32>; - d-cache-size = <32768>; - i-cache-line-size = <32>; - i-cache-size = <32768>; - }; - }; - - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - pclk: clock@0 { - compatible = "fixed-clock"; - clock-outputs = "bus", "pclk"; - clock-frequency = <200000000>; - ref-clock = <&ref_clk>, "ref"; - }; - }; - - paxi { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x80000000 0x400000>; - - emac: gem@30000 { - compatible = "cadence,gem"; - reg = <0x30000 0x10000>; - interrupts = <31>; - }; - - dmac1: dmac@40000 { - compatible = "snps,dw-dmac"; - reg = <0x40000 0x10000>; - interrupts = <25>; - }; - - dmac2: dmac@50000 { - compatible = "snps,dw-dmac"; - reg = <0x50000 0x10000>; - interrupts = <26>; - }; - - vic0: interrupt-controller@60000 { - compatible = "arm,pl192-vic"; - interrupt-controller; - reg = <0x60000 0x1000>; - #interrupt-cells = <1>; - }; - - vic1: interrupt-controller@64000 { - compatible = "arm,pl192-vic"; - interrupt-controller; - reg = <0x64000 0x1000>; - #interrupt-cells = <1>; - }; - - fuse: picoxcell-fuse@80000 { - compatible = "picoxcell,fuse-pc3x2"; - reg = <0x80000 0x10000>; - }; - - ssi: picoxcell-spi@90000 { - compatible = "picoxcell,spi"; - reg = <0x90000 0x10000>; - interrupt-parent = <&vic0>; - interrupts = <10>; - }; - - ipsec: spacc@100000 { - compatible = "picochip,spacc-ipsec"; - reg = <0x100000 0x10000>; - interrupt-parent = <&vic0>; - interrupts = <24>; - ref-clock = <&pclk>, "ref"; - }; - - srtp: spacc@140000 { - compatible = "picochip,spacc-srtp"; - reg = <0x140000 0x10000>; - interrupt-parent = <&vic0>; - interrupts = <23>; - }; - - l2_engine: spacc@180000 { - compatible = "picochip,spacc-l2"; - reg = <0x180000 0x10000>; - interrupt-parent = <&vic0>; - interrupts = <22>; - ref-clock = <&pclk>, "ref"; - }; - - apb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x200000 0x80000>; - - rtc0: rtc@0 { - compatible = "picochip,pc3x2-rtc"; - clock-freq = <200000000>; - reg = <0x00000 0xf>; - interrupt-parent = <&vic1>; - interrupts = <8>; - }; - - timer0: timer@10000 { - compatible = "picochip,pc3x2-timer"; - interrupt-parent = <&vic0>; - interrupts = <4>; - clock-freq = <200000000>; - reg = <0x10000 0x14>; - }; - - timer1: timer@10014 { - compatible = "picochip,pc3x2-timer"; - interrupt-parent = <&vic0>; - interrupts = <5>; - clock-freq = <200000000>; - reg = <0x10014 0x14>; - }; - - timer2: timer@10028 { - compatible = "picochip,pc3x2-timer"; - interrupt-parent = <&vic0>; - interrupts = <6>; - clock-freq = <200000000>; - reg = <0x10028 0x14>; - }; - - timer3: timer@1003c { - compatible = "picochip,pc3x2-timer"; - interrupt-parent = <&vic0>; - interrupts = <7>; - clock-freq = <200000000>; - reg = <0x1003c 0x14>; - }; - - gpio: gpio@20000 { - compatible = "snps,dw-apb-gpio"; - reg = <0x20000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - reg-io-width = <4>; - - banka: gpio-controller@0 { - compatible = "snps,dw-apb-gpio-bank"; - gpio-controller; - #gpio-cells = <2>; - gpio-generic,nr-gpio = <8>; - - regoffset-dat = <0x50>; - regoffset-set = <0x00>; - regoffset-dirout = <0x04>; - }; - - bankb: gpio-controller@1 { - compatible = "snps,dw-apb-gpio-bank"; - gpio-controller; - #gpio-cells = <2>; - gpio-generic,nr-gpio = <8>; - - regoffset-dat = <0x54>; - regoffset-set = <0x0c>; - regoffset-dirout = <0x10>; - }; - }; - - uart0: uart@30000 { - compatible = "snps,dw-apb-uart"; - reg = <0x30000 0x1000>; - interrupt-parent = <&vic1>; - interrupts = <10>; - clock-frequency = <3686400>; - reg-shift = <2>; - reg-io-width = <4>; - }; - - uart1: uart@40000 { - compatible = "snps,dw-apb-uart"; - reg = <0x40000 0x1000>; - interrupt-parent = <&vic1>; - interrupts = <9>; - clock-frequency = <3686400>; - reg-shift = <2>; - reg-io-width = <4>; - }; - - wdog: watchdog@50000 { - compatible = "snps,dw-apb-wdg"; - reg = <0x50000 0x10000>; - interrupt-parent = <&vic0>; - interrupts = <11>; - bus-clock = <&pclk>, "bus"; - }; - }; - }; - - rwid-axi { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges; - - ebi@50000000 { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0x40000000 0x08000000 - 1 0 0x48000000 0x08000000 - 2 0 0x50000000 0x08000000 - 3 0 0x58000000 0x08000000>; - }; - - axi2pico@c0000000 { - compatible = "picochip,axi2pico-pc3x2"; - reg = <0xc0000000 0x10000>; - interrupts = <13 14 15 16 17 18 19 20 21>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/picoxcell-pc3x3.dtsi b/sys/gnu/dts/arm/picoxcell-pc3x3.dtsi deleted file mode 100644 index fa93155fadb..00000000000 --- a/sys/gnu/dts/arm/picoxcell-pc3x3.dtsi +++ /dev/null @@ -1,356 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2011 Picochip, Jamie Iles - */ -/ { - model = "Picochip picoXcell PC3X3"; - compatible = "picochip,pc3x3"; - #address-cells = <1>; - #size-cells = <1>; - - cpus { - #address-cells = <0>; - #size-cells = <0>; - - cpu { - compatible = "arm,arm1176jz-s"; - device_type = "cpu"; - cpu-clock = <&arm_clk>, "cpu"; - d-cache-line-size = <32>; - d-cache-size = <32768>; - i-cache-line-size = <32>; - i-cache-size = <32768>; - }; - }; - - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - clkgate: clkgate@800a0048 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x800a0048 4>; - compatible = "picochip,pc3x3-clk-gate"; - - tzprot_clk: clock@0 { - compatible = "picochip,pc3x3-gated-clk"; - clock-outputs = "bus"; - picochip,clk-disable-bit = <0>; - clock-frequency = <200000000>; - ref-clock = <&ref_clk>, "ref"; - }; - - spi_clk: clock@1 { - compatible = "picochip,pc3x3-gated-clk"; - clock-outputs = "bus"; - picochip,clk-disable-bit = <1>; - clock-frequency = <200000000>; - ref-clock = <&ref_clk>, "ref"; - }; - - dmac0_clk: clock@2 { - compatible = "picochip,pc3x3-gated-clk"; - clock-outputs = "bus"; - picochip,clk-disable-bit = <2>; - clock-frequency = <200000000>; - ref-clock = <&ref_clk>, "ref"; - }; - - dmac1_clk: clock@3 { - compatible = "picochip,pc3x3-gated-clk"; - clock-outputs = "bus"; - picochip,clk-disable-bit = <3>; - clock-frequency = <200000000>; - ref-clock = <&ref_clk>, "ref"; - }; - - ebi_clk: clock@4 { - compatible = "picochip,pc3x3-gated-clk"; - clock-outputs = "bus"; - picochip,clk-disable-bit = <4>; - clock-frequency = <200000000>; - ref-clock = <&ref_clk>, "ref"; - }; - - ipsec_clk: clock@5 { - compatible = "picochip,pc3x3-gated-clk"; - clock-outputs = "bus"; - picochip,clk-disable-bit = <5>; - clock-frequency = <200000000>; - ref-clock = <&ref_clk>, "ref"; - }; - - l2_clk: clock@6 { - compatible = "picochip,pc3x3-gated-clk"; - clock-outputs = "bus"; - picochip,clk-disable-bit = <6>; - clock-frequency = <200000000>; - ref-clock = <&ref_clk>, "ref"; - }; - - trng_clk: clock@7 { - compatible = "picochip,pc3x3-gated-clk"; - clock-outputs = "bus"; - picochip,clk-disable-bit = <7>; - clock-frequency = <200000000>; - ref-clock = <&ref_clk>, "ref"; - }; - - fuse_clk: clock@8 { - compatible = "picochip,pc3x3-gated-clk"; - clock-outputs = "bus"; - picochip,clk-disable-bit = <8>; - clock-frequency = <200000000>; - ref-clock = <&ref_clk>, "ref"; - }; - - otp_clk: clock@9 { - compatible = "picochip,pc3x3-gated-clk"; - clock-outputs = "bus"; - picochip,clk-disable-bit = <9>; - clock-frequency = <200000000>; - ref-clock = <&ref_clk>, "ref"; - }; - }; - - arm_clk: clock@11 { - compatible = "picochip,pc3x3-pll"; - reg = <0x800a0050 0x8>; - picochip,min-freq = <140000000>; - picochip,max-freq = <700000000>; - ref-clock = <&ref_clk>, "ref"; - clock-outputs = "cpu"; - }; - - pclk: clock@12 { - compatible = "fixed-clock"; - clock-outputs = "bus", "pclk"; - clock-frequency = <200000000>; - ref-clock = <&ref_clk>, "ref"; - }; - }; - - paxi { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x80000000 0x400000>; - - emac: gem@30000 { - compatible = "cadence,gem"; - reg = <0x30000 0x10000>; - interrupt-parent = <&vic0>; - interrupts = <31>; - }; - - dmac1: dmac@40000 { - compatible = "snps,dw-dmac"; - reg = <0x40000 0x10000>; - interrupt-parent = <&vic0>; - interrupts = <25>; - }; - - dmac2: dmac@50000 { - compatible = "snps,dw-dmac"; - reg = <0x50000 0x10000>; - interrupt-parent = <&vic0>; - interrupts = <26>; - }; - - vic0: interrupt-controller@60000 { - compatible = "arm,pl192-vic"; - interrupt-controller; - reg = <0x60000 0x1000>; - #interrupt-cells = <1>; - }; - - vic1: interrupt-controller@64000 { - compatible = "arm,pl192-vic"; - interrupt-controller; - reg = <0x64000 0x1000>; - #interrupt-cells = <1>; - }; - - fuse: picoxcell-fuse@80000 { - compatible = "picoxcell,fuse-pc3x3"; - reg = <0x80000 0x10000>; - }; - - ssi: picoxcell-spi@90000 { - compatible = "picoxcell,spi"; - reg = <0x90000 0x10000>; - interrupt-parent = <&vic0>; - interrupts = <10>; - }; - - ipsec: spacc@100000 { - compatible = "picochip,spacc-ipsec"; - reg = <0x100000 0x10000>; - interrupt-parent = <&vic0>; - interrupts = <24>; - ref-clock = <&ipsec_clk>, "ref"; - }; - - srtp: spacc@140000 { - compatible = "picochip,spacc-srtp"; - reg = <0x140000 0x10000>; - interrupt-parent = <&vic0>; - interrupts = <23>; - }; - - l2_engine: spacc@180000 { - compatible = "picochip,spacc-l2"; - reg = <0x180000 0x10000>; - interrupt-parent = <&vic0>; - interrupts = <22>; - ref-clock = <&l2_clk>, "ref"; - }; - - apb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x200000 0x80000>; - - rtc0: rtc@0 { - compatible = "picochip,pc3x2-rtc"; - clock-freq = <200000000>; - reg = <0x00000 0xf>; - interrupt-parent = <&vic0>; - interrupts = <8>; - }; - - timer0: timer@10000 { - compatible = "picochip,pc3x2-timer"; - interrupt-parent = <&vic0>; - interrupts = <4>; - clock-freq = <200000000>; - reg = <0x10000 0x14>; - }; - - timer1: timer@10014 { - compatible = "picochip,pc3x2-timer"; - interrupt-parent = <&vic0>; - interrupts = <5>; - clock-freq = <200000000>; - reg = <0x10014 0x14>; - }; - - gpio: gpio@20000 { - compatible = "snps,dw-apb-gpio"; - reg = <0x20000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - reg-io-width = <4>; - - banka: gpio-controller@0 { - compatible = "snps,dw-apb-gpio-bank"; - gpio-controller; - #gpio-cells = <2>; - gpio-generic,nr-gpio = <8>; - - regoffset-dat = <0x50>; - regoffset-set = <0x00>; - regoffset-dirout = <0x04>; - }; - - bankb: gpio-controller@1 { - compatible = "snps,dw-apb-gpio-bank"; - gpio-controller; - #gpio-cells = <2>; - gpio-generic,nr-gpio = <16>; - - regoffset-dat = <0x54>; - regoffset-set = <0x0c>; - regoffset-dirout = <0x10>; - }; - - bankd: gpio-controller@2 { - compatible = "snps,dw-apb-gpio-bank"; - gpio-controller; - #gpio-cells = <2>; - gpio-generic,nr-gpio = <30>; - - regoffset-dat = <0x5c>; - regoffset-set = <0x24>; - regoffset-dirout = <0x28>; - }; - }; - - uart0: uart@30000 { - compatible = "snps,dw-apb-uart"; - reg = <0x30000 0x1000>; - interrupt-parent = <&vic1>; - interrupts = <10>; - clock-frequency = <3686400>; - reg-shift = <2>; - reg-io-width = <4>; - }; - - uart1: uart@40000 { - compatible = "snps,dw-apb-uart"; - reg = <0x40000 0x1000>; - interrupt-parent = <&vic1>; - interrupts = <9>; - clock-frequency = <3686400>; - reg-shift = <2>; - reg-io-width = <4>; - }; - - wdog: watchdog@50000 { - compatible = "snps,dw-apb-wdg"; - reg = <0x50000 0x10000>; - interrupt-parent = <&vic0>; - interrupts = <11>; - bus-clock = <&pclk>, "bus"; - }; - - timer2: timer@60000 { - compatible = "picochip,pc3x2-timer"; - interrupt-parent = <&vic0>; - interrupts = <6>; - clock-freq = <200000000>; - reg = <0x60000 0x14>; - }; - - timer3: timer@60014 { - compatible = "picochip,pc3x2-timer"; - interrupt-parent = <&vic0>; - interrupts = <7>; - clock-freq = <200000000>; - reg = <0x60014 0x14>; - }; - }; - }; - - rwid-axi { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges; - - ebi@50000000 { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0x40000000 0x08000000 - 1 0 0x48000000 0x08000000 - 2 0 0x50000000 0x08000000 - 3 0 0x58000000 0x08000000>; - }; - - axi2pico@c0000000 { - compatible = "picochip,axi2pico-pc3x3"; - reg = <0xc0000000 0x10000>; - interrupt-parent = <&vic0>; - interrupts = <13 14 15 16 17 18 19 20 21>; - }; - - otp@ffff8000 { - compatible = "picochip,otp-pc3x3"; - reg = <0xffff8000 0x8000>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/picoxcell-pc7302-pc3x2.dts b/sys/gnu/dts/arm/picoxcell-pc7302-pc3x2.dts deleted file mode 100644 index 3626e538068..00000000000 --- a/sys/gnu/dts/arm/picoxcell-pc7302-pc3x2.dts +++ /dev/null @@ -1,78 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2011 Picochip, Jamie Iles - */ - -/dts-v1/; -/include/ "picoxcell-pc3x2.dtsi" -/ { - model = "Picochip PC7302 (PC3X2)"; - compatible = "picochip,pc7302-pc3x2", "picochip,pc3x2"; - - memory { - device_type = "memory"; - reg = <0x0 0x08000000>; - }; - - chosen { - stdout-path = &uart0; - }; - - clocks { - ref_clk: clock@1 { - compatible = "fixed-clock"; - clock-outputs = "ref"; - clock-frequency = <20000000>; - }; - }; - - rwid-axi { - ebi@50000000 { - nand: gpio-nand@2,0 { - compatible = "gpio-control-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <2 0x0000 0x1000>; - bus-clock = <&pclk>, "bus"; - gpio-control-nand,io-sync-reg = - <0x00000000 0x80220000>; - - gpios = <&banka 1 0 /* rdy */ - &banka 2 0 /* nce */ - &banka 3 0 /* ale */ - &banka 4 0 /* cle */ - 0 /* nwp */>; - - boot@100000 { - label = "Boot"; - reg = <0x100000 0x80000>; - }; - - redundant-boot@200000 { - label = "Redundant Boot"; - reg = <0x200000 0x80000>; - }; - - boot-env@300000 { - label = "Boot Evironment"; - reg = <0x300000 0x20000>; - }; - - redundant-boot-env@320000 { - label = "Redundant Boot Environment"; - reg = <0x300000 0x20000>; - }; - - kernel@380000 { - label = "Kernel"; - reg = <0x380000 0x800000>; - }; - - fs@b80000 { - label = "File System"; - reg = <0xb80000 0xf480000>; - }; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/picoxcell-pc7302-pc3x3.dts b/sys/gnu/dts/arm/picoxcell-pc7302-pc3x3.dts deleted file mode 100644 index 3eca65e8ee0..00000000000 --- a/sys/gnu/dts/arm/picoxcell-pc7302-pc3x3.dts +++ /dev/null @@ -1,84 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2011 Picochip, Jamie Iles - */ - -/dts-v1/; -/include/ "picoxcell-pc3x3.dtsi" -/ { - model = "Picochip PC7302 (PC3X3)"; - compatible = "picochip,pc7302-pc3x3", "picochip,pc3x3"; - - memory { - device_type = "memory"; - reg = <0x0 0x08000000>; - }; - - chosen { - stdout-path = &uart0; - }; - - clocks { - ref_clk: clock@10 { - compatible = "fixed-clock"; - clock-outputs = "ref"; - clock-frequency = <20000000>; - }; - - clkgate: clkgate@800a0048 { - clock@4 { - picochip,clk-no-disable; - }; - }; - }; - - rwid-axi { - ebi@50000000 { - nand: gpio-nand@2,0 { - compatible = "gpio-control-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <2 0x0000 0x1000>; - bus-clock = <&ebi_clk>, "bus"; - gpio-control-nand,io-sync-reg = - <0x00000000 0x80220000>; - - gpios = <&banka 1 0 /* rdy */ - &banka 2 0 /* nce */ - &banka 3 0 /* ale */ - &banka 4 0 /* cle */ - 0 /* nwp */>; - - boot@100000 { - label = "Boot"; - reg = <0x100000 0x80000>; - }; - - redundant-boot@200000 { - label = "Redundant Boot"; - reg = <0x200000 0x80000>; - }; - - boot-env@300000 { - label = "Boot Evironment"; - reg = <0x300000 0x20000>; - }; - - redundant-boot-env@320000 { - label = "Redundant Boot Environment"; - reg = <0x300000 0x20000>; - }; - - kernel@380000 { - label = "Kernel"; - reg = <0x380000 0x800000>; - }; - - fs@b80000 { - label = "File System"; - reg = <0xb80000 0xf480000>; - }; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/pm9g45.dts b/sys/gnu/dts/arm/pm9g45.dts deleted file mode 100644 index 4dfe0f15d7b..00000000000 --- a/sys/gnu/dts/arm/pm9g45.dts +++ /dev/null @@ -1,184 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * pm9g45.dts - Device Tree file for Ronetix pm9g45 board - * - * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD - */ -/dts-v1/; -#include "at91sam9g45.dtsi" - -/ { - model = "Ronetix pm9g45"; - compatible = "ronetix,pm9g45", "atmel,at91sam9g45", "atmel,at91sam9"; - - chosen { - bootargs = "console=ttyS0,115200"; - }; - - memory { - reg = <0x70000000 0x8000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <12000000>; - }; - }; - - ahb { - apb { - dbgu: serial@ffffee00 { - status = "okay"; - }; - - pinctrl@fffff200 { - nand { - pinctrl_nand_rb: nand-rb-0 { - atmel,pins = - ; - }; - }; - - mmc { - pinctrl_board_mmc: mmc0-board { - atmel,pins = - ; /* PD6 gpio CD pin pull_up and deglitch */ - }; - }; - }; - - tcb0: timer@fff7c000 { - timer@0 { - compatible = "atmel,tcb-timer"; - reg = <0>, <1>; - }; - - timer@2 { - compatible = "atmel,tcb-timer"; - reg = <2>; - }; - }; - - mmc0: mmc@fff80000 { - pinctrl-0 = < - &pinctrl_board_mmc - &pinctrl_mmc0_slot0_clk_cmd_dat0 - &pinctrl_mmc0_slot0_dat1_3>; - status = "okay"; - slot@0 { - reg = <0>; - bus-width = <4>; - cd-gpios = <&pioD 6 GPIO_ACTIVE_HIGH>; - }; - }; - - macb0: ethernet@fffbc000 { - phy-mode = "rmii"; - status = "okay"; - }; - }; - - ebi: ebi@10000000 { - status = "okay"; - - nand_controller: nand-controller { - status = "okay"; - pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>; - pinctrl-names = "default"; - - nand@3 { - reg = <0x3 0x0 0x800000>; - rb-gpios = <&pioD 3 GPIO_ACTIVE_HIGH>; - cs-gpios = <&pioC 14 GPIO_ACTIVE_HIGH>; - nand-bus-width = <8>; - nand-ecc-mode = "soft"; - nand-on-flash-bbt; - label = "atmel_nand"; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - at91bootstrap@0 { - label = "at91bootstrap"; - reg = <0x0 0x20000>; - }; - - barebox@20000 { - label = "barebox"; - reg = <0x20000 0x40000>; - }; - - bareboxenv@60000 { - label = "bareboxenv"; - reg = <0x60000 0x1A0000>; - }; - - kernel@200000 { - label = "bareboxenv2"; - reg = <0x200000 0x300000>; - }; - - kernel@500000 { - label = "root"; - reg = <0x500000 0x400000>; - }; - - data@900000 { - label = "data"; - reg = <0x900000 0x8340000>; - }; - }; - }; - }; - }; - - usb0: ohci@700000 { - status = "okay"; - num-ports = <2>; - }; - - usb1: ehci@800000 { - status = "okay"; - }; - }; - - leds { - compatible = "gpio-leds"; - - led0 { - label = "led0"; - gpios = <&pioD 0 GPIO_ACTIVE_LOW>; - linux,default-trigger = "nand-disk"; - }; - - led1 { - label = "led1"; - gpios = <&pioD 31 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - right { - label = "SW4"; - gpios = <&pioE 7 GPIO_ACTIVE_LOW>; - linux,code = <106>; - }; - - up { - label = "SW3"; - gpios = <&pioE 8 GPIO_ACTIVE_LOW>; - linux,code = <103>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/prima2-evb.dts b/sys/gnu/dts/arm/prima2-evb.dts deleted file mode 100644 index 7394f764df6..00000000000 --- a/sys/gnu/dts/arm/prima2-evb.dts +++ /dev/null @@ -1,37 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * DTS file for CSR SiRFprimaII Evaluation Board - * - * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company. - */ - -/dts-v1/; - -/include/ "prima2.dtsi" - -/ { - model = "CSR SiRFprimaII Evaluation Board"; - compatible = "sirf,prima2", "sirf,prima2-cb"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x20000000>; - }; - - axi { - peri-iobg { - uart@b0060000 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins_a>; - }; - spi@b00d0000 { - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins_a>; - }; - spi@b0170000 { - pinctrl-names = "default"; - pinctrl-0 = <&spi1_pins_a>; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/prima2.dtsi b/sys/gnu/dts/arm/prima2.dtsi deleted file mode 100644 index 9c7b46b90c3..00000000000 --- a/sys/gnu/dts/arm/prima2.dtsi +++ /dev/null @@ -1,838 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * DTS file for CSR SiRFprimaII SoC - * - * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company. - */ - -/ { - compatible = "sirf,prima2"; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&intc>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - reg = <0x0>; - d-cache-line-size = <32>; - i-cache-line-size = <32>; - d-cache-size = <32768>; - i-cache-size = <32768>; - /* from bootloader */ - timebase-frequency = <0>; - bus-frequency = <0>; - clock-frequency = <0>; - clocks = <&clks 12>; - operating-points = < - /* kHz uV */ - 200000 1025000 - 400000 1025000 - 664000 1050000 - 800000 1100000 - >; - clock-latency = <150000>; - }; - }; - - arm-pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts = <29>; - }; - - axi { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x40000000 0x40000000 0x80000000>; - - l2-cache-controller@80040000 { - compatible = "arm,pl310-cache"; - reg = <0x80040000 0x1000>; - interrupts = <59>; - arm,tag-latency = <1 1 1>; - arm,data-latency = <1 1 1>; - arm,filter-ranges = <0 0x40000000>; - }; - - intc: interrupt-controller@80020000 { - #interrupt-cells = <1>; - interrupt-controller; - compatible = "sirf,prima2-intc"; - reg = <0x80020000 0x1000>; - }; - - sys-iobg { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x88000000 0x88000000 0x40000>; - - clks: clock-controller@88000000 { - compatible = "sirf,prima2-clkc"; - reg = <0x88000000 0x1000>; - interrupts = <3>; - #clock-cells = <1>; - }; - - rstc: reset-controller@88010000 { - compatible = "sirf,prima2-rstc"; - reg = <0x88010000 0x1000>; - #reset-cells = <1>; - }; - - rsc-controller@88020000 { - compatible = "sirf,prima2-rsc"; - reg = <0x88020000 0x1000>; - }; - - cphifbg@88030000 { - compatible = "sirf,prima2-cphifbg"; - reg = <0x88030000 0x1000>; - clocks = <&clks 42>; - }; - }; - - mem-iobg { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x90000000 0x90000000 0x10000>; - - memory-controller@90000000 { - compatible = "sirf,prima2-memc"; - reg = <0x90000000 0x2000>; - interrupts = <27>; - clocks = <&clks 5>; - }; - - memc-monitor { - compatible = "sirf,prima2-memcmon"; - reg = <0x90002000 0x200>; - interrupts = <4>; - clocks = <&clks 32>; - }; - }; - - disp-iobg { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x90010000 0x90010000 0x30000>; - - display@90010000 { - compatible = "sirf,prima2-lcd"; - reg = <0x90010000 0x20000>; - interrupts = <30>; - }; - - vpp@90020000 { - compatible = "sirf,prima2-vpp"; - reg = <0x90020000 0x10000>; - interrupts = <31>; - clocks = <&clks 35>; - resets = <&rstc 6>; - }; - }; - - graphics-iobg { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x98000000 0x98000000 0x8000000>; - - graphics@98000000 { - compatible = "powervr,sgx531"; - reg = <0x98000000 0x8000000>; - interrupts = <6>; - clocks = <&clks 32>; - }; - }; - - multimedia-iobg { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0xa0000000 0xa0000000 0x8000000>; - - multimedia@a0000000 { - compatible = "sirf,prima2-video-codec"; - reg = <0xa0000000 0x8000000>; - interrupts = <5>; - clocks = <&clks 33>; - }; - }; - - dsp-iobg { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0xa8000000 0xa8000000 0x2000000>; - - dspif@a8000000 { - compatible = "sirf,prima2-dspif"; - reg = <0xa8000000 0x10000>; - interrupts = <9>; - resets = <&rstc 1>; - }; - - gps@a8010000 { - compatible = "sirf,prima2-gps"; - reg = <0xa8010000 0x10000>; - interrupts = <7>; - clocks = <&clks 9>; - resets = <&rstc 2>; - }; - - dsp@a9000000 { - compatible = "sirf,prima2-dsp"; - reg = <0xa9000000 0x1000000>; - interrupts = <8>; - clocks = <&clks 8>; - resets = <&rstc 0>; - }; - }; - - peri-iobg { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0xb0000000 0xb0000000 0x180000>, - <0x56000000 0x56000000 0x1b00000>; - - timer@b0020000 { - compatible = "sirf,prima2-tick"; - reg = <0xb0020000 0x1000>; - interrupts = <0>; - clocks = <&clks 11>; - }; - - nand@b0030000 { - compatible = "sirf,prima2-nand"; - reg = <0xb0030000 0x10000>; - interrupts = <41>; - clocks = <&clks 26>; - }; - - audio@b0040000 { - compatible = "sirf,prima2-audio"; - reg = <0xb0040000 0x10000>; - interrupts = <35>; - clocks = <&clks 27>; - }; - - uart0: uart@b0050000 { - cell-index = <0>; - compatible = "sirf,prima2-uart"; - reg = <0xb0050000 0x1000>; - interrupts = <17>; - fifosize = <128>; - clocks = <&clks 13>; - dmas = <&dmac1 5>, <&dmac0 2>; - dma-names = "rx", "tx"; - }; - - uart1: uart@b0060000 { - cell-index = <1>; - compatible = "sirf,prima2-uart"; - reg = <0xb0060000 0x1000>; - interrupts = <18>; - fifosize = <32>; - clocks = <&clks 14>; - }; - - uart2: uart@b0070000 { - cell-index = <2>; - compatible = "sirf,prima2-uart"; - reg = <0xb0070000 0x1000>; - interrupts = <19>; - fifosize = <128>; - clocks = <&clks 15>; - dmas = <&dmac0 6>, <&dmac0 7>; - dma-names = "rx", "tx"; - }; - - usp0: usp@b0080000 { - cell-index = <0>; - compatible = "sirf,prima2-usp"; - reg = <0xb0080000 0x10000>; - interrupts = <20>; - fifosize = <128>; - clocks = <&clks 28>; - dmas = <&dmac1 1>, <&dmac1 2>; - dma-names = "rx", "tx"; - }; - - usp1: usp@b0090000 { - cell-index = <1>; - compatible = "sirf,prima2-usp"; - reg = <0xb0090000 0x10000>; - interrupts = <21>; - fifosize = <128>; - clocks = <&clks 29>; - dmas = <&dmac0 14>, <&dmac0 15>; - dma-names = "rx", "tx"; - }; - - usp2: usp@b00a0000 { - cell-index = <2>; - compatible = "sirf,prima2-usp"; - reg = <0xb00a0000 0x10000>; - interrupts = <22>; - fifosize = <128>; - clocks = <&clks 30>; - dmas = <&dmac0 10>, <&dmac0 11>; - dma-names = "rx", "tx"; - }; - - dmac0: dma-controller@b00b0000 { - cell-index = <0>; - compatible = "sirf,prima2-dmac"; - reg = <0xb00b0000 0x10000>; - interrupts = <12>; - clocks = <&clks 24>; - #dma-cells = <1>; - }; - - dmac1: dma-controller@b0160000 { - cell-index = <1>; - compatible = "sirf,prima2-dmac"; - reg = <0xb0160000 0x10000>; - interrupts = <13>; - clocks = <&clks 25>; - #dma-cells = <1>; - }; - - vip@b00C0000 { - compatible = "sirf,prima2-vip"; - reg = <0xb00C0000 0x10000>; - clocks = <&clks 31>; - interrupts = <14>; - sirf,vip-dma-rx-channel = <16>; - }; - - spi0: spi@b00d0000 { - cell-index = <0>; - compatible = "sirf,prima2-spi"; - reg = <0xb00d0000 0x10000>; - interrupts = <15>; - sirf,spi-num-chipselects = <1>; - dmas = <&dmac1 9>, - <&dmac1 4>; - dma-names = "rx", "tx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clks 19>; - status = "disabled"; - }; - - spi1: spi@b0170000 { - cell-index = <1>; - compatible = "sirf,prima2-spi"; - reg = <0xb0170000 0x10000>; - interrupts = <16>; - sirf,spi-num-chipselects = <1>; - dmas = <&dmac0 12>, - <&dmac0 13>; - dma-names = "rx", "tx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clks 20>; - status = "disabled"; - }; - - i2c0: i2c@b00e0000 { - cell-index = <0>; - compatible = "sirf,prima2-i2c"; - reg = <0xb00e0000 0x10000>; - interrupts = <24>; - clocks = <&clks 17>; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c1: i2c@b00f0000 { - cell-index = <1>; - compatible = "sirf,prima2-i2c"; - reg = <0xb00f0000 0x10000>; - interrupts = <25>; - clocks = <&clks 18>; - #address-cells = <1>; - #size-cells = <0>; - }; - - tsc@b0110000 { - compatible = "sirf,prima2-tsc"; - reg = <0xb0110000 0x10000>; - interrupts = <33>; - clocks = <&clks 16>; - }; - - gpio: pinctrl@b0120000 { - #gpio-cells = <2>; - #interrupt-cells = <2>; - compatible = "sirf,prima2-pinctrl"; - reg = <0xb0120000 0x10000>; - interrupts = <43 44 45 46 47>; - gpio-controller; - interrupt-controller; - - lcd_16pins_a: lcd0@0 { - lcd { - sirf,pins = "lcd_16bitsgrp"; - sirf,function = "lcd_16bits"; - }; - }; - lcd_18pins_a: lcd0@1 { - lcd { - sirf,pins = "lcd_18bitsgrp"; - sirf,function = "lcd_18bits"; - }; - }; - lcd_24pins_a: lcd0@2 { - lcd { - sirf,pins = "lcd_24bitsgrp"; - sirf,function = "lcd_24bits"; - }; - }; - lcdrom_pins_a: lcdrom0@0 { - lcd { - sirf,pins = "lcdromgrp"; - sirf,function = "lcdrom"; - }; - }; - uart0_pins_a: uart0@0 { - uart { - sirf,pins = "uart0grp"; - sirf,function = "uart0"; - }; - }; - uart0_noflow_pins_a: uart0@1 { - uart { - sirf,pins = "uart0_nostreamctrlgrp"; - sirf,function = "uart0_nostreamctrl"; - }; - }; - uart1_pins_a: uart1@0 { - uart { - sirf,pins = "uart1grp"; - sirf,function = "uart1"; - }; - }; - uart2_pins_a: uart2@0 { - uart { - sirf,pins = "uart2grp"; - sirf,function = "uart2"; - }; - }; - uart2_noflow_pins_a: uart2@1 { - uart { - sirf,pins = "uart2_nostreamctrlgrp"; - sirf,function = "uart2_nostreamctrl"; - }; - }; - spi0_pins_a: spi0@0 { - spi { - sirf,pins = "spi0grp"; - sirf,function = "spi0"; - }; - }; - spi1_pins_a: spi1@0 { - spi { - sirf,pins = "spi1grp"; - sirf,function = "spi1"; - }; - }; - i2c0_pins_a: i2c0@0 { - i2c { - sirf,pins = "i2c0grp"; - sirf,function = "i2c0"; - }; - }; - i2c1_pins_a: i2c1@0 { - i2c { - sirf,pins = "i2c1grp"; - sirf,function = "i2c1"; - }; - }; - pwm0_pins_a: pwm0@0 { - pwm { - sirf,pins = "pwm0grp"; - sirf,function = "pwm0"; - }; - }; - pwm1_pins_a: pwm1@0 { - pwm { - sirf,pins = "pwm1grp"; - sirf,function = "pwm1"; - }; - }; - pwm2_pins_a: pwm2@0 { - pwm { - sirf,pins = "pwm2grp"; - sirf,function = "pwm2"; - }; - }; - pwm3_pins_a: pwm3@0 { - pwm { - sirf,pins = "pwm3grp"; - sirf,function = "pwm3"; - }; - }; - gps_pins_a: gps@0 { - gps { - sirf,pins = "gpsgrp"; - sirf,function = "gps"; - }; - }; - vip_pins_a: vip@0 { - vip { - sirf,pins = "vipgrp"; - sirf,function = "vip"; - }; - }; - sdmmc0_pins_a: sdmmc0@0 { - sdmmc0 { - sirf,pins = "sdmmc0grp"; - sirf,function = "sdmmc0"; - }; - }; - sdmmc1_pins_a: sdmmc1@0 { - sdmmc1 { - sirf,pins = "sdmmc1grp"; - sirf,function = "sdmmc1"; - }; - }; - sdmmc2_pins_a: sdmmc2@0 { - sdmmc2 { - sirf,pins = "sdmmc2grp"; - sirf,function = "sdmmc2"; - }; - }; - sdmmc3_pins_a: sdmmc3@0 { - sdmmc3 { - sirf,pins = "sdmmc3grp"; - sirf,function = "sdmmc3"; - }; - }; - sdmmc4_pins_a: sdmmc4@0 { - sdmmc4 { - sirf,pins = "sdmmc4grp"; - sirf,function = "sdmmc4"; - }; - }; - sdmmc5_pins_a: sdmmc5@0 { - sdmmc5 { - sirf,pins = "sdmmc5grp"; - sirf,function = "sdmmc5"; - }; - }; - i2s_mclk_pins_a: i2s_mclk@0 { - i2s_mclk { - sirf,pins = "i2smclkgrp"; - sirf,function = "i2s_mclk"; - }; - }; - i2s_ext_clk_input_pins_a: i2s_ext_clk_input@0 { - i2s_ext_clk_input { - sirf,pins = "i2s_ext_clk_inputgrp"; - sirf,function = "i2s_ext_clk_input"; - }; - }; - i2s_pins_a: i2s@0 { - i2s { - sirf,pins = "i2sgrp"; - sirf,function = "i2s"; - }; - }; - i2s_no_din_pins_a: i2s_no_din@0 { - i2s_no_din { - sirf,pins = "i2s_no_dingrp"; - sirf,function = "i2s_no_din"; - }; - }; - i2s_6chn_pins_a: i2s_6chn@0 { - i2s_6chn { - sirf,pins = "i2s_6chngrp"; - sirf,function = "i2s_6chn"; - }; - }; - ac97_pins_a: ac97@0 { - ac97 { - sirf,pins = "ac97grp"; - sirf,function = "ac97"; - }; - }; - nand_pins_a: nand@0 { - nand { - sirf,pins = "nandgrp"; - sirf,function = "nand"; - }; - }; - usp0_pins_a: usp0@0 { - usp0 { - sirf,pins = "usp0grp"; - sirf,function = "usp0"; - }; - }; - usp0_uart_nostreamctrl_pins_a: usp0@1 { - usp0 { - sirf,pins = - "usp0_uart_nostreamctrl_grp"; - sirf,function = - "usp0_uart_nostreamctrl"; - }; - }; - usp0_only_utfs_pins_a: usp0@2 { - usp0 { - sirf,pins = "usp0_only_utfs_grp"; - sirf,function = "usp0_only_utfs"; - }; - }; - usp0_only_urfs_pins_a: usp0@3 { - usp0 { - sirf,pins = "usp0_only_urfs_grp"; - sirf,function = "usp0_only_urfs"; - }; - }; - usp1_pins_a: usp1@0 { - usp1 { - sirf,pins = "usp1grp"; - sirf,function = "usp1"; - }; - }; - usp1_uart_nostreamctrl_pins_a: usp1@1 { - usp1 { - sirf,pins = - "usp1_uart_nostreamctrl_grp"; - sirf,function = - "usp1_uart_nostreamctrl"; - }; - }; - usp2_pins_a: usp2@0 { - usp2 { - sirf,pins = "usp2grp"; - sirf,function = "usp2"; - }; - }; - usp2_uart_nostreamctrl_pins_a: usp2@1 { - usp2 { - sirf,pins = - "usp2_uart_nostreamctrl_grp"; - sirf,function = - "usp2_uart_nostreamctrl"; - }; - }; - usb0_utmi_drvbus_pins_a: usb0_utmi_drvbus@0 { - usb0_utmi_drvbus { - sirf,pins = "usb0_utmi_drvbusgrp"; - sirf,function = "usb0_utmi_drvbus"; - }; - }; - usb1_utmi_drvbus_pins_a: usb1_utmi_drvbus@0 { - usb1_utmi_drvbus { - sirf,pins = "usb1_utmi_drvbusgrp"; - sirf,function = "usb1_utmi_drvbus"; - }; - }; - usb1_dp_dn_pins_a: usb1_dp_dn@0 { - usb1_dp_dn { - sirf,pins = "usb1_dp_dngrp"; - sirf,function = "usb1_dp_dn"; - }; - }; - uart1_route_io_usb1_pins_a: uart1_route_io_usb1@0 { - uart1_route_io_usb1 { - sirf,pins = "uart1_route_io_usb1grp"; - sirf,function = "uart1_route_io_usb1"; - }; - }; - warm_rst_pins_a: warm_rst@0 { - warm_rst { - sirf,pins = "warm_rstgrp"; - sirf,function = "warm_rst"; - }; - }; - pulse_count_pins_a: pulse_count@0 { - pulse_count { - sirf,pins = "pulse_countgrp"; - sirf,function = "pulse_count"; - }; - }; - cko0_pins_a: cko0@0 { - cko0 { - sirf,pins = "cko0grp"; - sirf,function = "cko0"; - }; - }; - cko1_pins_a: cko1@0 { - cko1 { - sirf,pins = "cko1grp"; - sirf,function = "cko1"; - }; - }; - }; - - pwm@b0130000 { - compatible = "sirf,prima2-pwm"; - reg = <0xb0130000 0x10000>; - clocks = <&clks 21>; - }; - - efusesys@b0140000 { - compatible = "sirf,prima2-efuse"; - reg = <0xb0140000 0x10000>; - clocks = <&clks 22>; - }; - - pulsec@b0150000 { - compatible = "sirf,prima2-pulsec"; - reg = <0xb0150000 0x10000>; - interrupts = <48>; - clocks = <&clks 23>; - }; - - pci-iobg { - compatible = "sirf,prima2-pciiobg", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x56000000 0x56000000 0x1b00000>; - - sd0: sdhci@56000000 { - cell-index = <0>; - compatible = "sirf,prima2-sdhc"; - reg = <0x56000000 0x100000>; - interrupts = <38>; - status = "disabled"; - bus-width = <8>; - clocks = <&clks 36>; - }; - - sd1: sdhci@56100000 { - cell-index = <1>; - compatible = "sirf,prima2-sdhc"; - reg = <0x56100000 0x100000>; - interrupts = <38>; - status = "disabled"; - bus-width = <4>; - clocks = <&clks 36>; - }; - - sd2: sdhci@56200000 { - cell-index = <2>; - compatible = "sirf,prima2-sdhc"; - reg = <0x56200000 0x100000>; - interrupts = <23>; - status = "disabled"; - clocks = <&clks 37>; - }; - - sd3: sdhci@56300000 { - cell-index = <3>; - compatible = "sirf,prima2-sdhc"; - reg = <0x56300000 0x100000>; - interrupts = <23>; - status = "disabled"; - clocks = <&clks 37>; - }; - - sd4: sdhci@56400000 { - cell-index = <4>; - compatible = "sirf,prima2-sdhc"; - reg = <0x56400000 0x100000>; - interrupts = <39>; - status = "disabled"; - clocks = <&clks 38>; - }; - - sd5: sdhci@56500000 { - cell-index = <5>; - compatible = "sirf,prima2-sdhc"; - reg = <0x56500000 0x100000>; - interrupts = <39>; - clocks = <&clks 38>; - }; - - pci-copy@57900000 { - compatible = "sirf,prima2-pcicp"; - reg = <0x57900000 0x100000>; - interrupts = <40>; - }; - - rom-interface@57a00000 { - compatible = "sirf,prima2-romif"; - reg = <0x57a00000 0x100000>; - }; - }; - }; - - rtc-iobg { - compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x80030000 0x10000>; - - gpsrtc@1000 { - compatible = "sirf,prima2-gpsrtc"; - reg = <0x1000 0x1000>; - interrupts = <55 56 57>; - }; - - sysrtc@2000 { - compatible = "sirf,prima2-sysrtc"; - reg = <0x2000 0x1000>; - interrupts = <52 53 54>; - }; - - minigpsrtc@2000 { - compatible = "sirf,prima2-minigpsrtc"; - reg = <0x2000 0x1000>; - interrupts = <54>; - }; - - pwrc@3000 { - compatible = "sirf,prima2-pwrc"; - reg = <0x3000 0x1000>; - interrupts = <32>; - }; - }; - - uus-iobg { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0xb8000000 0xb8000000 0x40000>; - - usb0: usb@b00e0000 { - compatible = "chipidea,ci13611a-prima2"; - reg = <0xb8000000 0x10000>; - interrupts = <10>; - clocks = <&clks 40>; - }; - - usb1: usb@b00f0000 { - compatible = "chipidea,ci13611a-prima2"; - reg = <0xb8010000 0x10000>; - interrupts = <11>; - clocks = <&clks 41>; - }; - - sata@b00f0000 { - compatible = "synopsys,dwc-ahsata"; - reg = <0xb8020000 0x10000>; - interrupts = <37>; - }; - - security@b00f0000 { - compatible = "sirf,prima2-security"; - reg = <0xb8030000 0x10000>; - interrupts = <42>; - clocks = <&clks 7>; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/pxa168-aspenite.dts b/sys/gnu/dts/arm/pxa168-aspenite.dts deleted file mode 100644 index 2ad40e37319..00000000000 --- a/sys/gnu/dts/arm/pxa168-aspenite.dts +++ /dev/null @@ -1,35 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Marvell Technology Group Ltd. - * Author: Haojian Zhuang - */ - -/dts-v1/; -#include "pxa168.dtsi" - -/ { - model = "Marvell PXA168 Aspenite Development Board"; - compatible = "mrvl,pxa168-aspenite", "mrvl,pxa168"; - - chosen { - bootargs = "console=ttyS0,115200 root=/dev/nfs nfsroot=192.168.1.100:/nfsroot/ ip=192.168.1.101:192.168.1.100::255.255.255.0::eth0:on"; - }; - - memory { - reg = <0x00000000 0x04000000>; - }; - - soc { - apb@d4000000 { - uart1: uart@d4017000 { - status = "okay"; - }; - twsi1: i2c@d4011000 { - status = "okay"; - }; - rtc: rtc@d4010000 { - status = "okay"; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/pxa168.dtsi b/sys/gnu/dts/arm/pxa168.dtsi deleted file mode 100644 index 72f8cb60cb5..00000000000 --- a/sys/gnu/dts/arm/pxa168.dtsi +++ /dev/null @@ -1,157 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Marvell Technology Group Ltd. - * Author: Haojian Zhuang - */ - -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - - aliases { - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - i2c0 = &twsi1; - i2c1 = &twsi2; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&intc>; - ranges; - - axi@d4200000 { /* AXI */ - compatible = "mrvl,axi-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0xd4200000 0x00200000>; - ranges; - - intc: interrupt-controller@d4282000 { - compatible = "mrvl,mmp-intc"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0xd4282000 0x1000>; - mrvl,intc-nr-irqs = <64>; - }; - - }; - - apb@d4000000 { /* APB */ - compatible = "mrvl,apb-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0xd4000000 0x00200000>; - ranges; - - timer0: timer@d4014000 { - compatible = "mrvl,mmp-timer"; - reg = <0xd4014000 0x100>; - interrupts = <13>; - }; - - uart1: uart@d4017000 { - compatible = "mrvl,mmp-uart"; - reg = <0xd4017000 0x1000>; - interrupts = <27>; - clocks = <&soc_clocks PXA168_CLK_UART0>; - resets = <&soc_clocks PXA168_CLK_UART0>; - status = "disabled"; - }; - - uart2: uart@d4018000 { - compatible = "mrvl,mmp-uart"; - reg = <0xd4018000 0x1000>; - interrupts = <28>; - clocks = <&soc_clocks PXA168_CLK_UART1>; - resets = <&soc_clocks PXA168_CLK_UART1>; - status = "disabled"; - }; - - uart3: uart@d4026000 { - compatible = "mrvl,mmp-uart"; - reg = <0xd4026000 0x1000>; - interrupts = <29>; - clocks = <&soc_clocks PXA168_CLK_UART2>; - resets = <&soc_clocks PXA168_CLK_UART2>; - status = "disabled"; - }; - - gpio@d4019000 { - compatible = "marvell,mmp-gpio"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0xd4019000 0x1000>; - gpio-controller; - #gpio-cells = <2>; - interrupts = <49>; - clocks = <&soc_clocks PXA168_CLK_GPIO>; - resets = <&soc_clocks PXA168_CLK_GPIO>; - interrupt-names = "gpio_mux"; - interrupt-controller; - #interrupt-cells = <1>; - ranges; - - gcb0: gpio@d4019000 { - reg = <0xd4019000 0x4>; - }; - - gcb1: gpio@d4019004 { - reg = <0xd4019004 0x4>; - }; - - gcb2: gpio@d4019008 { - reg = <0xd4019008 0x4>; - }; - - gcb3: gpio@d4019100 { - reg = <0xd4019100 0x4>; - }; - }; - - twsi1: i2c@d4011000 { - compatible = "mrvl,mmp-twsi"; - reg = <0xd4011000 0x1000>; - interrupts = <7>; - clocks = <&soc_clocks PXA168_CLK_TWSI0>; - resets = <&soc_clocks PXA168_CLK_TWSI0>; - mrvl,i2c-fast-mode; - status = "disabled"; - }; - - twsi2: i2c@d4025000 { - compatible = "mrvl,mmp-twsi"; - reg = <0xd4025000 0x1000>; - interrupts = <58>; - clocks = <&soc_clocks PXA168_CLK_TWSI1>; - resets = <&soc_clocks PXA168_CLK_TWSI1>; - status = "disabled"; - }; - - rtc: rtc@d4010000 { - compatible = "mrvl,mmp-rtc"; - reg = <0xd4010000 0x1000>; - interrupts = <5 6>; - interrupt-names = "rtc 1Hz", "rtc alarm"; - clocks = <&soc_clocks PXA168_CLK_RTC>; - resets = <&soc_clocks PXA168_CLK_RTC>; - status = "disabled"; - }; - }; - - soc_clocks: clocks{ - compatible = "marvell,pxa168-clock"; - reg = <0xd4050000 0x1000>, - <0xd4282800 0x400>, - <0xd4015000 0x1000>; - reg-names = "mpmu", "apmu", "apbc"; - #clock-cells = <1>; - #reset-cells = <1>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/pxa25x.dtsi b/sys/gnu/dts/arm/pxa25x.dtsi deleted file mode 100644 index a248bf03803..00000000000 --- a/sys/gnu/dts/arm/pxa25x.dtsi +++ /dev/null @@ -1,115 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (C) 2016 Robert Jarzmik - */ -#include "pxa2xx.dtsi" -#include "dt-bindings/clock/pxa-clock.h" - -/ { - model = "Marvell PXA25x family SoC"; - compatible = "marvell,pxa250"; - - clocks { - /* - * The muxing of external clocks/internal dividers for osc* clock - * sources has been hidden under the carpet by now. - */ - #address-cells = <1>; - #size-cells = <1>; - ranges; - - clks: pxa2xx_clks@41300004 { - compatible = "marvell,pxa250-core-clocks"; - #clock-cells = <1>; - status = "okay"; - }; - - /* timer oscillator */ - clktimer: oscillator { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <3686400>; - clock-output-names = "ostimer"; - }; - }; - - pxabus { - pdma: dma-controller@40000000 { - compatible = "marvell,pdma-1.0"; - reg = <0x40000000 0x10000>; - interrupts = <25>; - #dma-channels = <16>; - #dma-cells = <2>; - #dma-requests = <40>; - status = "okay"; - }; - - pxairq: interrupt-controller@40d00000 { - marvell,intc-priority; - marvell,intc-nr-irqs = <32>; - }; - - pinctrl: pinctrl@40e00000 { - reg = <0x40e00054 0x20 0x40e0000c 0xc 0x40e0010c 4 - 0x40f00020 0x10>; - compatible = "marvell,pxa25x-pinctrl"; - }; - - gpio: gpio@40e00000 { - compatible = "intel,pxa25x-gpio"; - gpio-ranges = <&pinctrl 0 0 84>; - clocks = <&clks CLK_NONE>; - }; - - pwm0: pwm@40b00000 { - compatible = "marvell,pxa250-pwm"; - reg = <0x40b00000 0x10>; - #pwm-cells = <1>; - clocks = <&clks CLK_PWM0>; - }; - - pwm1: pwm@40b00010 { - compatible = "marvell,pxa250-pwm"; - reg = <0x40b00010 0x10>; - #pwm-cells = <1>; - clocks = <&clks CLK_PWM1>; - }; - - rtc@40900000 { - clocks = <&clks CLK_OSC32k768>; - }; - }; - - timer@40a00000 { - compatible = "marvell,pxa-timer"; - reg = <0x40a00000 0x20>; - interrupts = <26>; - clocks = <&clktimer>; - status = "okay"; - }; - - pxa250_opp_table: opp_table0 { - compatible = "operating-points-v2"; - - opp-99532800 { - opp-hz = /bits/ 64 <99532800>; - opp-microvolt = <1000000 950000 1650000>; - clock-latency-ns = <20>; - }; - opp-199065600 { - opp-hz = /bits/ 64 <199065600>; - opp-microvolt = <1000000 950000 1650000>; - clock-latency-ns = <20>; - }; - opp-298598400 { - opp-hz = /bits/ 64 <298598400>; - opp-microvolt = <1100000 1045000 1650000>; - clock-latency-ns = <20>; - }; - opp-398131200 { - opp-hz = /bits/ 64 <398131200>; - opp-microvolt = <1300000 1235000 1650000>; - clock-latency-ns = <20>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/pxa27x.dtsi b/sys/gnu/dts/arm/pxa27x.dtsi deleted file mode 100644 index ccbecad9c5c..00000000000 --- a/sys/gnu/dts/arm/pxa27x.dtsi +++ /dev/null @@ -1,185 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* The pxa3xx skeleton simply augments the 2xx version */ -#include "pxa2xx.dtsi" -#include "dt-bindings/clock/pxa-clock.h" - -/ { - model = "Marvell PXA27x familiy SoC"; - compatible = "marvell,pxa27x"; - - pxabus { - pdma: dma-controller@40000000 { - compatible = "marvell,pdma-1.0"; - reg = <0x40000000 0x10000>; - interrupts = <25>; - #dma-channels = <32>; - #dma-cells = <2>; - #dma-requests = <75>; - status = "okay"; - }; - - pxairq: interrupt-controller@40d00000 { - marvell,intc-priority; - marvell,intc-nr-irqs = <34>; - }; - - pinctrl: pinctrl@40e00000 { - reg = <0x40e00054 0x20 0x40e0000c 0xc 0x40e0010c 4 - 0x40f00020 0x10>; - compatible = "marvell,pxa27x-pinctrl"; - }; - - gpio: gpio@40e00000 { - compatible = "intel,pxa27x-gpio"; - gpio-ranges = <&pinctrl 0 0 128>; - clocks = <&clks CLK_NONE>; - }; - - usb0: usb@4c000000 { - compatible = "marvell,pxa-ohci"; - reg = <0x4c000000 0x10000>; - interrupts = <3>; - clocks = <&clks CLK_USBHOST>; - status = "disabled"; - }; - - pwm0: pwm@40b00000 { - compatible = "marvell,pxa270-pwm", "marvell,pxa250-pwm"; - reg = <0x40b00000 0x10>; - #pwm-cells = <1>; - clocks = <&clks CLK_PWM0>; - }; - - pwm1: pwm@40b00010 { - compatible = "marvell,pxa270-pwm", "marvell,pxa250-pwm"; - reg = <0x40b00010 0x10>; - #pwm-cells = <1>; - clocks = <&clks CLK_PWM1>; - }; - - pwm2: pwm@40c00000 { - compatible = "marvell,pxa270-pwm", "marvell,pxa250-pwm"; - reg = <0x40c00000 0x10>; - #pwm-cells = <1>; - clocks = <&clks CLK_PWM0>; - }; - - pwm3: pwm@40c00010 { - compatible = "marvell,pxa270-pwm", "marvell,pxa250-pwm"; - reg = <0x40c00010 0x10>; - #pwm-cells = <1>; - clocks = <&clks CLK_PWM1>; - }; - - pwri2c: i2c@40f00180 { - compatible = "mrvl,pxa-i2c"; - reg = <0x40f00180 0x24>; - interrupts = <6>; - clocks = <&clks CLK_PWRI2C>; - #address-cells = <0x1>; - #size-cells = <0>; - status = "disabled"; - }; - - pxa27x_udc: udc@40600000 { - compatible = "marvell,pxa270-udc"; - reg = <0x40600000 0x10000>; - interrupts = <11>; - clocks = <&clks CLK_USB>; - status = "disabled"; - }; - - keypad: keypad@41500000 { - compatible = "marvell,pxa27x-keypad"; - reg = <0x41500000 0x4c>; - interrupts = <4>; - clocks = <&clks CLK_KEYPAD>; - status = "disabled"; - }; - - pxa_camera: imaging@50000000 { - compatible = "marvell,pxa270-qci"; - reg = <0x50000000 0x1000>; - interrupts = <33>; - dmas = <&pdma 68 0 /* Y channel */ - &pdma 69 0 /* U channel */ - &pdma 70 0>; /* V channel */ - dma-names = "CI_Y", "CI_U", "CI_V"; - - clocks = <&clks CLK_CAMERA>; - clock-names = "ciclk"; - clock-frequency = <5000000>; - clock-output-names = "qci_mclk"; - - status = "disabled"; - }; - - rtc@40900000 { - clocks = <&clks CLK_OSC32k768>; - }; - }; - - clocks { - /* - * The muxing of external clocks/internal dividers for osc* clock - * sources has been hidden under the carpet by now. - */ - #address-cells = <1>; - #size-cells = <1>; - ranges; - - clks: pxa2xx_clks@41300004 { - compatible = "marvell,pxa270-clocks"; - #clock-cells = <1>; - status = "okay"; - }; - }; - - timer@40a00000 { - compatible = "marvell,pxa-timer"; - reg = <0x40a00000 0x20>; - interrupts = <26>; - clocks = <&clks CLK_OSTIMER>; - status = "okay"; - }; - - pxa270_opp_table: opp_table0 { - compatible = "operating-points-v2"; - - opp-104000000 { - opp-hz = /bits/ 64 <104000000>; - opp-microvolt = <900000 900000 1705000>; - clock-latency-ns = <20>; - }; - opp-156000000 { - opp-hz = /bits/ 64 <156000000>; - opp-microvolt = <1000000 1000000 1705000>; - clock-latency-ns = <20>; - }; - opp-208000000 { - opp-hz = /bits/ 64 <208000000>; - opp-microvolt = <1180000 1180000 1705000>; - clock-latency-ns = <20>; - }; - opp-312000000 { - opp-hz = /bits/ 64 <312000000>; - opp-microvolt = <1250000 1250000 1705000>; - clock-latency-ns = <20>; - }; - opp-416000000 { - opp-hz = /bits/ 64 <416000000>; - opp-microvolt = <1350000 1350000 1705000>; - clock-latency-ns = <20>; - }; - opp-520000000 { - opp-hz = /bits/ 64 <520000000>; - opp-microvolt = <1450000 1450000 1705000>; - clock-latency-ns = <20>; - }; - opp-624000000 { - opp-hz = /bits/ 64 <624000000>; - opp-microvolt = <1550000 1550000 1705000>; - clock-latency-ns = <20>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/pxa2xx.dtsi b/sys/gnu/dts/arm/pxa2xx.dtsi deleted file mode 100644 index 84154c43fe6..00000000000 --- a/sys/gnu/dts/arm/pxa2xx.dtsi +++ /dev/null @@ -1,162 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * pxa2xx.dtsi - Device Tree Include file for Marvell PXA2xx family SoC - * - * Copyright (C) 2011 Marek Vasut - */ - -#include "dt-bindings/clock/pxa-clock.h" - -#define PMGROUP(pin) #pin -#define PMMUX(func, pin, af) \ - mux- ## func { \ - groups = PMGROUP(P ## pin); \ - function = #af; \ - } -#define PMMUX_LPM_LOW(func, pin, af) \ - mux- ## func { \ - groups = PMGROUP(P ## pin); \ - function = #af; \ - low-power-disable; \ - } -#define PMMUX_LPM_HIGH(func, pin, af) \ - mux- ## func { \ - groups = PMGROUP(P ## pin); \ - function = #af; \ - low-power-enable; \ - } - -/ { - #address-cells = <1>; - #size-cells = <1>; - model = "Marvell PXA2xx family SoC"; - compatible = "marvell,pxa2xx"; - interrupt-parent = <&pxairq>; - - aliases { - serial0 = &ffuart; - serial1 = &btuart; - serial2 = &stuart; - serial3 = &hwuart; - i2c0 = &pwri2c; - i2c1 = &pxai2c1; - }; - - cpus { - cpu { - compatible = "marvell,xscale"; - device_type = "cpu"; - }; - }; - - pxabus { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - pxairq: interrupt-controller@40d00000 { - #interrupt-cells = <1>; - compatible = "marvell,pxa-intc"; - interrupt-controller; - interrupt-parent; - marvell,intc-nr-irqs = <32>; - reg = <0x40d00000 0xd0>; - }; - - gpio: gpio@40e00000 { - compatible = "mrvl,pxa-gpio"; - #address-cells = <0x1>; - #size-cells = <0x1>; - reg = <0x40e00000 0x10000>; - gpio-controller; - #gpio-cells = <0x2>; - interrupts = <8>, <9>, <10>; - interrupt-names = "gpio0", "gpio1", "gpio_mux"; - interrupt-controller; - #interrupt-cells = <0x2>; - ranges; - - gcb0: gpio@40e00000 { - reg = <0x40e00000 0x4>; - }; - - gcb1: gpio@40e00004 { - reg = <0x40e00004 0x4>; - }; - - gcb2: gpio@40e00008 { - reg = <0x40e00008 0x4>; - }; - gcb3: gpio@40e0000c { - reg = <0x40e0000c 0x4>; - }; - }; - - ffuart: serial@40100000 { - compatible = "mrvl,pxa-uart"; - reg = <0x40100000 0x30>; - interrupts = <22>; - clocks = <&clks CLK_FFUART>; - status = "disabled"; - }; - - btuart: serial@40200000 { - compatible = "mrvl,pxa-uart"; - reg = <0x40200000 0x30>; - interrupts = <21>; - clocks = <&clks CLK_BTUART>; - status = "disabled"; - }; - - stuart: serial@40700000 { - compatible = "mrvl,pxa-uart"; - reg = <0x40700000 0x30>; - interrupts = <20>; - clocks = <&clks CLK_STUART>; - status = "disabled"; - }; - - hwuart: serial@41600000 { - compatible = "mrvl,pxa-uart"; - reg = <0x41600000 0x30>; - interrupts = <7>; - status = "disabled"; - }; - - pxai2c1: i2c@40301680 { - compatible = "mrvl,pxa-i2c"; - reg = <0x40301680 0x30>; - interrupts = <18>; - clocks = <&clks CLK_I2C>; - #address-cells = <0x1>; - #size-cells = <0>; - status = "disabled"; - }; - - mmc0: mmc@41100000 { - compatible = "marvell,pxa-mmc"; - reg = <0x41100000 0x1000>; - interrupts = <23>; - clocks = <&clks CLK_MMC>; - dmas = <&pdma 21 3 - &pdma 22 3>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - rtc@40900000 { - compatible = "marvell,pxa-rtc"; - reg = <0x40900000 0x3c>; - interrupts = <30 31>; - }; - - lcdc: lcd-controller@40500000 { - compatible = "marvell,pxa2xx-lcdc"; - reg = <0x44000000 0x10000>; - interrupts = <17>; - clocks = <&clks CLK_LCD>; - status = "disabled"; - }; - }; -}; diff --git a/sys/gnu/dts/arm/pxa300-raumfeld-common.dtsi b/sys/gnu/dts/arm/pxa300-raumfeld-common.dtsi deleted file mode 100644 index 8a6721d436b..00000000000 --- a/sys/gnu/dts/arm/pxa300-raumfeld-common.dtsi +++ /dev/null @@ -1,405 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -#include "pxa3xx.dtsi" -#include -#include -#include - -/ { - /* Will be overridden by bootloader */ - hw-revision = <0>; - - chosen { - bootargs = "root=ubi0:RootFS rootfstype=ubifs rw ubi.mtd=3"; - stdout-path = &ffuart; - }; - - memory { - device_type = "memory"; - reg = <0xa0000000 0x8000000>; /* 128 MB */ - }; - - reg_3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "3v3-fixed-supply"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_1v8: regulator-1v8 { - compatible = "regulator-fixed"; - regulator-name = "1v8-fixed-supply"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - reg_va_5v0: regulator-va-5v0 { - compatible = "regulator-fixed"; - regulator-name = "va-5v0-fixed-supply"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio 124 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - ssp_dai0: ssp-dai0 { - compatible = "mrvl,pxa-ssp-dai"; - pinctrl-names = "default"; - pinctrl-0 = <&ssp0_dai_pins>; - port = <&ssp1>; - #sound-dai-cells = <0>; - dmas = <&pdma 13 3 - &pdma 14 3>; - dma-names = "rx", "tx"; - clock-names = "extclk"; - }; - - ssp_dai1: ssp-dai1 { - compatible = "mrvl,pxa-ssp-dai"; - pinctrl-names = "default"; - pinctrl-0 = <&ssp1_dai_pins>; - port = <&ssp2>; - #sound-dai-cells = <0>; - dmas = <&pdma 15 3 - &pdma 16 3>; - dma-names = "rx", "tx"; - clock-names = "extclk"; - }; - - spi: spi { - compatible = "spi-gpio"; - #address-cells = <0x1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&spi_pins>; - gpio-sck = <&gpio 95 GPIO_ACTIVE_HIGH>; - gpio-miso = <&gpio 98 GPIO_ACTIVE_HIGH>; - gpio-mosi = <&gpio 97 GPIO_ACTIVE_HIGH>; - cs-gpios = < - &gpio 34 GPIO_ACTIVE_HIGH - &gpio 125 GPIO_ACTIVE_HIGH - &gpio 96 GPIO_ACTIVE_HIGH - >; - num-chipselects = <3>; - - dac: dac@2 { - compatible = "ti,dac7512"; - reg = <2>; - spi-max-frequency = <1000000>; - vcc-supply = <®_3v3>; - }; - }; - - keys: gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&gpio_keys_pins>; - - on-off { - label = "on_off button"; - gpios = <&gpio 14 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - rescue-boot { - label = "rescue boot button"; - gpios = <&gpio 115 GPIO_ACTIVE_HIGH>; - linux,code = ; - }; - - setup { - label = "setup"; - gpios = <&gpio 119 GPIO_ACTIVE_HIGH>; - linux,code = ; - }; - }; - - rotary: rotary-encoder { - compatible = "rotary-encoder"; - gpios = < - &gpio 19 GPIO_ACTIVE_LOW - &gpio 20 GPIO_ACTIVE_HIGH - >; - linux,axis = ; - rotary-encoder,relative-axis; - }; - - leds: leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_a &led_pins_b>; - - left { - label = "raumfeld:1"; - gpios = <&gpio 36 GPIO_ACTIVE_LOW>; - }; - - right { - label = "raumfeld:2"; - gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; - }; - }; - - poweroff { - compatible = "gpio-poweroff"; - pinctrl-names = "default"; - pinctrl-0 = <&poweroff_pins>; - gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; - }; - - mmc0_pwrseq: mmc-pwrseq { - compatible = "mmc-pwrseq-simple"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pwrseq_pins>; - reset-gpios = < - &gpio 113 GPIO_ACTIVE_LOW /* W2W_RESET */ - &gpio 114 GPIO_ACTIVE_LOW /* W2W_PDN */ - >; - }; - - ethernet: ethernet@10000000 { - compatible = "smsc,lan9115"; - pinctrl-names = "default"; - pinctrl-0 = <&smsc_pins &smsc_bus_pins>; - reg = <0x10000000 0x100000>; - phy-mode = "mii"; - interrupt-parent = <&gpio>; - interrupts = <40 IRQ_TYPE_EDGE_FALLING>; - vdd33a-supply = <®_3v3>; - vddvario-supply = <®_1v8>; - reset-gpios = <&gpio 39 GPIO_ACTIVE_LOW>; - reg-io-width = <4>; - smsc,save-mac-address; - smsc,irq-push-pull; - }; -}; - -&ffuart { - status = "okay"; -}; - -&pwri2c { - status = "okay"; - - max8660: regulator@34 { - compatible = "maxim,max8660"; - reg = <0x34>; - - regulators { - regulator-v3 { - regulator-compatible= "V3(DCDC)"; - regulator-min-microvolt = <725000>; - regulator-max-microvolt = <1800000>; - }; - - regulator-v4 { - regulator-compatible= "V4(DCDC)"; - regulator-min-microvolt = <725000>; - regulator-max-microvolt = <1800000>; - }; - - regulator-v5 { - regulator-compatible= "V5(LDO)"; - regulator-min-microvolt = <1700000>; - regulator-max-microvolt = <2000000>; - }; - - reg_vcc_sdio: regulator-v6 { - regulator-compatible= "V6(LDO)"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - regulator-v7 { - regulator-compatible= "V7(LDO)"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - }; - }; -}; - -&pxai2c1 { - status = "okay"; - mrvl,i2c-fast-mode; - pinctrl-names = "default"; - pinctrl-0 = <&pxai2c1_pins>; -}; - -&ssp1 { - status = "okay"; -}; - -&ssp2 { - status = "okay"; -}; - -&nand_controller { - status = "okay"; - - nand@0 { - reg = <0>; - nand-rb = <0>; - nand-ecc-mode = "hw"; - marvell,nand-keep-config; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "Bootloader"; - reg = <0x0000000 0xa0000>; - read-only; - }; - - partition@a0000 { - label = "BootloaderEnvironment"; - reg = <0x0a0000 0x20000>; - }; - - partition@c0000 { - label = "BootloaderSplashScreen"; - reg = <0x0c0000 0x60000>; - }; - - partition@120000 { - label = "UBI"; - reg = <0x120000 0x7ee0000>; - }; - }; - }; -}; - -&usb0 { - status = "okay"; - marvell,enable-port1; - marvell,port-mode = <2>; /* PMM_GLOBAL_MODE */ - pinctrl-names = "default"; - pinctrl-0 = <&pxa3xx_ohci_pins>; -}; - -&mmc0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; - pxa-mmc,detect-delay-ms = <200>; - vmmc-supply = <®_vcc_sdio>; - mmc-pwrseq = <&mmc0_pwrseq>; - non-removable; - bus-width = <4>; -}; - -&pinctrl { - poweroff_pins: poweroff-pins { - pinctrl-single,pins = ; - pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_FLOAT); - }; - - led_pins_a: led-pins-a { - pinctrl-single,pins = ; - pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_LOW); - }; - - led_pins_b: led-pins-b { - pinctrl-single,pins = ; - pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_DRIVE_HIGH); - }; - - pxai2c1_pins: pxai2c1-pins { - pinctrl-single,pins = < - MFP_PIN_PXA300(21) MFP_AF1 /* I2C_SCL */ - MFP_PIN_PXA300(22) MFP_AF1 /* I2C_SDA */ - >; - pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_HIGH); - }; - - gpio_keys_pins: gpio-keys-pins { - pinctrl-single,pins = < - MFP_PIN_PXA300(14) MFP_AF0 /* on-off */ - MFP_PIN_PXA300(115) MFP_AF0 /* rescue boot */ - MFP_PIN_PXA300(119) MFP_AF0 /* setup */ - >; - pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_FLOAT); - }; - - spi_pins: spi-pins { - pinctrl-single,pins = < - MFP_PIN_PXA300(95) MFP_AF0 /* SCK */ - MFP_PIN_PXA300(97) MFP_AF0 /* MOSI */ - MFP_PIN_PXA300(98) MFP_AF0 /* MISO */ - MFP_PIN_PXA300(34) MFP_AF0 /* CS#0 */ - MFP_PIN_PXA300(125) MFP_AF0 /* CS#1 */ - MFP_PIN_PXA300(96) MFP_AF0 /* CS#2 */ - >; - pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_LOW); - }; - - pxa3xx_ohci_pins: pxa3xx-ohci-pins { - pinctrl-single,pins = < - MFP_PIN_PXA300_2(0) MFP_AF1 /* USBHPEN */ - MFP_PIN_PXA300_2(1) MFP_AF1 /* USBHPWR */ - >; - pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_LOW); - }; - - smsc_pins: smsc-pins { - pinctrl-single,pins = < - MFP_PIN_PXA300(39) MFP_AF0 /* RESET */ - MFP_PIN_PXA300(40) MFP_AF0 /* IRQ */ - >; - pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_LOW); - }; - - smsc_bus_pins: smsc-bus-pins { - pinctrl-single,pins = < - MFP_PIN_PXA300(1) MFP_AF1 /* nCS2 */ - >; - pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_FLOAT); - }; - - mmc0_pins: mmc0-pins { - pinctrl-single,pins = < - MFP_PIN_PXA300(3) MFP_AF4 /* MMC1_DAT0 */ - MFP_PIN_PXA300(4) MFP_AF4 /* MMC1_DAT1 */ - MFP_PIN_PXA300(5) MFP_AF4 /* MMC1_DAT2 */ - MFP_PIN_PXA300(6) MFP_AF4 /* MMC1_DAT3 */ - MFP_PIN_PXA300(7) MFP_AF4 /* MMC1_CLK */ - MFP_PIN_PXA300(8) MFP_AF4 /* MMC1_CMD */ - >; - pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_DRIVE_HIGH); - }; - - mmc0_pwrseq_pins: mmc0-pwrseq-pins { - pinctrl-single,pins = < - MFP_PIN_PXA300(113) MFP_AF0 /* W2W_RESET */ - MFP_PIN_PXA300(114) MFP_AF0 /* W2W_PDN */ - >; - pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_FLOAT); - }; - - ssp0_dai_pins: ssp0-dai-pins { - pinctrl-single,pins = < - MFP_PIN_PXA300(85) MFP_AF1 /* SSP1_SCLK */ - MFP_PIN_PXA300(86) MFP_AF1 /* SSP1_FRM */ - MFP_PIN_PXA300(87) MFP_AF1 /* SSP1_TXD */ - MFP_PIN_PXA300(88) MFP_AF1 /* SSP1_RXD */ - MFP_PIN_PXA300(89) MFP_AF1 /* SSP1_EXTCLK */ - MFP_PIN_PXA300(90) MFP_AF1 /* SSP1_SYSCLK */ - >; - pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_LOW); - }; - - ssp1_dai_pins: ssp1-dai-pins { - pinctrl-single,pins = < - MFP_PIN_PXA300(25) MFP_AF2 /* SSP2_SCLK */ - MFP_PIN_PXA300(26) MFP_AF2 /* SSP2_FRM */ - MFP_PIN_PXA300(27) MFP_AF2 /* SSP2_TXD */ - MFP_PIN_PXA300(29) MFP_AF2 /* SSP2_EXTCLK */ - >; - pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_LOW); - }; -}; diff --git a/sys/gnu/dts/arm/pxa300-raumfeld-connector.dts b/sys/gnu/dts/arm/pxa300-raumfeld-connector.dts deleted file mode 100644 index 3e9445419e3..00000000000 --- a/sys/gnu/dts/arm/pxa300-raumfeld-connector.dts +++ /dev/null @@ -1,73 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -/dts-v1/; - -#include "pxa300-raumfeld-common.dtsi" -#include "pxa300-raumfeld-tuneable-clock.dtsi" - -/ { - model = "Raumfeld Connector (PXA3xx)"; - compatible = "raumfeld,raumfeld-connector-pxa303", "marvell,pxa300"; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "Raumfeld Connector"; - #address-cells = <1>; - #size-cells = <0>; - - simple-audio-card,dai-link@0 { - reg = <0>; - format = "i2s"; - bitclock-master = <&dailink_master_analog>; - frame-master = <&dailink_master_analog>; - mclk-fs = <256>; - - dailink_master_analog: cpu { - sound-dai = <&ssp_dai0>; - }; - - codec { - sound-dai = <&cs4270>; - }; - }; - - simple-audio-card,dai-link@1 { - reg = <1>; - format = "i2s"; - bitclock-master = <&dailink_master_digital>; - frame-master = <&dailink_master_digital>; - mclk-fs = <256>; - - dailink_master_digital: cpu { - sound-dai = <&ssp_dai1>; - }; - - codec { - sound-dai = <&ak4104>; - }; - }; - }; -}; - -&ssp1 { - status = "okay"; -}; - -&ssp2 { - status = "okay"; -}; - -&spi { - ak4104: optical-transmitter@0 { - compatible = "asahi-kasei,ak4104"; - reg = <0>; - vdd-supply = <®_3v3>; - spi-max-frequency = <5000000>; - reset-gpios = <&gpio 38 GPIO_ACTIVE_HIGH>; - #sound-dai-cells = <0>; - }; -}; - -&rotary { - status = "disabled"; -}; diff --git a/sys/gnu/dts/arm/pxa300-raumfeld-controller.dts b/sys/gnu/dts/arm/pxa300-raumfeld-controller.dts deleted file mode 100644 index 12b15945ac6..00000000000 --- a/sys/gnu/dts/arm/pxa300-raumfeld-controller.dts +++ /dev/null @@ -1,285 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -/dts-v1/; - -#include "pxa300-raumfeld-common.dtsi" - -/ { - model = "Raumfeld Controller (PXA3xx)"; - compatible = "raumfeld,raumfeld-controller-pxa303", "marvell,pxa300"; - - reg_vbatt: regulator-vbatt { - compatible = "regulator-fixed"; - regulator-name = "vbatt-fixed-supply"; - regulator-min-microvolt = <3700000>; - regulator-max-microvolt = <3700000>; - regulator-always-on; - }; - - lcd_supply: regulator-va-tft { - compatible = "regulator-fixed"; - regulator-name = "va-tft-fixed-supply"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio 33 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - onewire { - compatible = "w1-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&w1_pins>; - gpios = < - &gpio 126 GPIO_OPEN_DRAIN /* W1 I/O */ - &gpio 105 GPIO_ACTIVE_HIGH /* pullup */ - >; - - w1_ds2760: slave-ds2760 { - compatible = "maxim,ds2760"; - power-supplies = <&charger>; - }; - }; - - charger: charger { - pinctrl-names = "default"; - pinctrl-0 = <&charger_pins>; - compatible = "gpio-charger"; - charger-type = "mains"; - gpios = <&gpio 101 GPIO_ACTIVE_LOW>; - }; - - /* - * One of the following two will be set to "okay" by the bootloader, - * depending on the hardware revision. - */ - backlight-controller-pwm { - compatible = "pwm-backlight"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pins>; - pwms = <&pwm0 10000>; - power-supply = <®_vbatt>; - status = "disabled"; - - brightness-levels = < - 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100 - >; - default-brightness-level = <100>; - }; - - backlight-controller { - compatible = "lltc,lt3593"; - pinctrl-names = "default"; - pinctrl-0 = <<3593_pins>; - lltc,ctrl-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; - status = "disabled"; - - led { - label = "backlight"; - default-state = "on"; - }; - }; -}; - -®_va_5v0 { - status = "disabled"; -}; - -ðernet { - status = "disabled"; -}; - -&leds { - status = "disabled"; -}; - -&dac { - status = "disabled"; -}; - -&pwm0 { - status = "okay"; -}; - -&keys { - pinctrl-0 = <&gpio_keys_pins &dock_detect_pins>; - dock-detect { - label = "dock detect"; - gpios = <&gpio 116 GPIO_ACTIVE_LOW>; - linux,code = ; - }; -}; - -&spi { - accelerometer@1 { - compatible = "st,lis302dl-spi"; - pinctrl-names = "default"; - pinctrl-0 = <&lis302_pins>; - reg = <1>; - spi-max-frequency = <1000000>; - interrupt-parent = <&gpio>; - interrupts = <104 IRQ_TYPE_EDGE_FALLING>; - - st,click-single-x; - st,click-single-y; - st,click-single-z; - st,click-thresh-x = <10>; - st,click-thresh-y = <10>; - st,click-thresh-z = <10>; - st,irq1-click; - st,irq2-click; - st,wakeup-x-lo; - st,wakeup-x-hi; - st,wakeup-y-lo; - st,wakeup-y-hi; - st,wakeup-z-lo; - st,wakeup-z-hi; - }; -}; - -&lcdc { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&lcdc_pins>; - lcd-supply = <&lcd_supply>; - - port { - lcdc_out: endpoint { - remote-endpoint = <&panel_in>; - bus-width = <16>; - }; - }; - - panel { - compatible = "sharp,lq043t3dx0-panel"; - display-timings { - native-mode = <&timing0>; - timing0: timing { - clock-frequency = <9009000>; - pixelclk-active = <0>; /* negative edge */ - hactive = <480>; - vactive = <272>; - hsync-len = <41>; - hback-porch = <2>; - hfront-porch = <1>; - vsync-len = <10>; - vback-porch = <3>; - vfront-porch = <1>; - }; - }; - - port { - panel_in: endpoint { - remote-endpoint = <&lcdc_out>; - }; - }; - }; -}; - -&gcu { - status = "okay"; -}; - -&pxai2c1 { - touchscreen@a { - compatible = "eeti,exc3000-i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&eeti_ts_pins>; - reg = <0xa>; - interrupt-parent = <&gpio>; - interrupts = <32 IRQ_TYPE_EDGE_RISING>; - attn-gpios = <&gpio 32 GPIO_ACTIVE_HIGH>; - touchscreen-inverted-y; - }; -}; - -&pinctrl { - lis302_pins: lis302-pins { - pinctrl-single,pins = < - MFP_PIN_PXA300(104) MFP_AF0 /* IRQ */ - >; - pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_LOW); - }; - - eeti_ts_pins: eeti-ts-pins { - pinctrl-single,pins = < - MFP_PIN_PXA300(32) MFP_AF0 /* IRQ */ - >; - pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_FLOAT); - }; - - lt3593_pins: lt3593-pins { - pinctrl-single,pins = < - MFP_PIN_PXA300(17) MFP_AF0 /* Backlight */ - >; - pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_LOW); - }; - - pwm0_pins: pwm0-pins { - pinctrl-single,pins = < - MFP_PIN_PXA300(17) MFP_AF1 /* PWM */ - >; - pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_LOW); - }; - - w1_pins: w1-pins { - pinctrl-single,pins = < - MFP_PIN_PXA300(126) MFP_AF0 /* PWM */ - MFP_PIN_PXA300(105) MFP_AF0 /* PWM */ - >; - pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_FLOAT); - }; - - charger_pins: charger_pins { - pinctrl-single,pins = < - MFP_PIN_PXA300(31) MFP_AF0 /* PEN2 */ - >; - pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_HIGH); - pinctrl-single,bias-pullup = MPF_PULL_UP; - }; - - dock_detect_pins: dock_detect_pins { - pinctrl-single,pins = < - MFP_PIN_PXA300(116) MFP_AF0 /* DOCK_DETECT */ - >; - pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_HIGH); - pinctrl-single,bias-pullup = MPF_PULL_UP; - }; - - lcdc_pins: lcdc-pins { - pinctrl-single,pins = < - MFP_PIN_PXA300(54) MFP_AF1 /* LDD_0 */ - MFP_PIN_PXA300(55) MFP_AF1 /* LDD_1 */ - MFP_PIN_PXA300(56) MFP_AF1 /* LDD_2 */ - MFP_PIN_PXA300(57) MFP_AF1 /* LDD_3 */ - MFP_PIN_PXA300(58) MFP_AF1 /* LDD_4 */ - MFP_PIN_PXA300(59) MFP_AF1 /* LDD_5 */ - MFP_PIN_PXA300(60) MFP_AF1 /* LDD_6 */ - MFP_PIN_PXA300(61) MFP_AF1 /* LDD_7 */ - MFP_PIN_PXA300(62) MFP_AF1 /* LDD_8 */ - MFP_PIN_PXA300(63) MFP_AF1 /* LDD_9 */ - MFP_PIN_PXA300(64) MFP_AF1 /* LDD_10 */ - MFP_PIN_PXA300(65) MFP_AF1 /* LDD_11 */ - MFP_PIN_PXA300(66) MFP_AF1 /* LDD_12 */ - MFP_PIN_PXA300(67) MFP_AF1 /* LDD_13 */ - MFP_PIN_PXA300(68) MFP_AF1 /* LDD_14 */ - MFP_PIN_PXA300(69) MFP_AF1 /* LDD_15 */ - MFP_PIN_PXA300(70) MFP_AF1 /* LDD_16 */ - MFP_PIN_PXA300(71) MFP_AF1 /* LDD_17 */ - MFP_PIN_PXA300(72) MFP_AF1 /* LCD_FCLK */ - MFP_PIN_PXA300(73) MFP_AF1 /* LCD_LCLK */ - MFP_PIN_PXA300(74) MFP_AF1 /* LCD_PCLK */ - MFP_PIN_PXA300(75) MFP_AF1 /* LCD_BIAS */ - >; - pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_LOW); - }; -}; diff --git a/sys/gnu/dts/arm/pxa300-raumfeld-speaker-l.dts b/sys/gnu/dts/arm/pxa300-raumfeld-speaker-l.dts deleted file mode 100644 index 5a0f7f17856..00000000000 --- a/sys/gnu/dts/arm/pxa300-raumfeld-speaker-l.dts +++ /dev/null @@ -1,11 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -/dts-v1/; - -#include "pxa300-raumfeld-common.dtsi" -#include "pxa300-raumfeld-tuneable-clock.dtsi" - -/ { - model = "Raumfeld Speaker L (PXA3xx)"; - compatible = "raumfeld,raumfeld-speaker-l-pxa303", "marvell,pxa300"; -}; diff --git a/sys/gnu/dts/arm/pxa300-raumfeld-speaker-m.dts b/sys/gnu/dts/arm/pxa300-raumfeld-speaker-m.dts deleted file mode 100644 index fa10d896282..00000000000 --- a/sys/gnu/dts/arm/pxa300-raumfeld-speaker-m.dts +++ /dev/null @@ -1,11 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -/dts-v1/; - -#include "pxa300-raumfeld-common.dtsi" -#include "pxa300-raumfeld-tuneable-clock.dtsi" - -/ { - model = "Raumfeld Speaker M (PXA3xx)"; - compatible = "raumfeld,raumfeld-speaker-m-pxa303", "marvell,pxa300"; -}; diff --git a/sys/gnu/dts/arm/pxa300-raumfeld-speaker-one.dts b/sys/gnu/dts/arm/pxa300-raumfeld-speaker-one.dts deleted file mode 100644 index a70560a8ea9..00000000000 --- a/sys/gnu/dts/arm/pxa300-raumfeld-speaker-one.dts +++ /dev/null @@ -1,140 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -/dts-v1/; - -#include "pxa300-raumfeld-common.dtsi" - -/ { - model = "Raumfeld Speaker One (PXA3xx)"; - compatible = "raumfeld,raumfeld-speaker-one-pxa303", "marvell,pxa300"; - - wm8782: wm8782 { - compatible = "wm8782"; - #sound-dai-cells = <0>; - Vdd-supply = <®_3v3>; - Vdda-supply = <®_va_5v0>; - }; - - xo_11mhz: oscillator-11mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <11289600>; - clock-accuracy = <100>; - }; - - xo_audio: clock-gate { - compatible = "gpio-gate-clock"; - pinctrlnames = "default"; - pinctrl-0 = <&xo_audio_pins>; - clocks = <&xo_11mhz>; - #clock-cells = <0>; - enable-gpios = <&gpio 111 GPIO_ACTIVE_HIGH>; - }; - - reg_va_30v0: regulator-va-30v0 { - compatible = "regulator-fixed"; - regulator-name = "va-30v0-fixed-supply"; - regulator-min-microvolt = <30000000>; - regulator-max-microvolt = <30000000>; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "Raumfeld Speaker"; - #address-cells = <1>; - #size-cells = <0>; - - simple-audio-card,dai-link@0 { - reg = <0>; - format = "i2s"; - bitclock-master = <&dailink_master_analog_out>; - frame-master = <&dailink_master_analog_out>; - mclk-fs = <256>; - - dailink_master_analog_out: cpu { - sound-dai = <&ssp_dai0>; - }; - - codec { - sound-dai = <&sta320>; - }; - }; - - simple-audio-card,dai-link@1 { - reg = <1>; - format = "i2s"; - bitclock-master = <&dailink_master_analog_in>; - frame-master = <&dailink_master_analog_in>; - mclk-fs = <256>; - - dailink_master_analog_in: cpu { - sound-dai = <&ssp_dai0>; - }; - - codec { - sound-dai = <&wm8782>; - }; - }; - }; -}; - -&ssp_dai0 { - clocks = <&xo_audio>; -}; - -&spi { - dac@2 { - compatible = "ti,dac7512"; - reg = <2>; - spi-max-frequency = <1000000>; - vcc-supply = <®_3v3>; - }; -}; - -&rotary { - status = "okay"; -}; - -&pxai2c1 { - sta320: codec@1a { - compatible = "st,sta32x"; - reg = <0x1a>; - pinctrl-names = "default"; - pinctrl-0 = <&sta320_pins>; - clocks = <&xo_audio>; - clock-names = "xti"; - reset-gpios = <&gpio 120 GPIO_ACTIVE_HIGH>; - Vdda-supply = <®_3v3>; - Vdd3-supply = <®_3v3>; - Vcc-supply = <®_va_30v0>; - #sound-dai-cells = <0>; - st,thermal-warning-adjustment; - st,thermal-warning-recovery; - st,fault-detect-recovery; - st,drop-compensation-ns = <80>; - st,max-power-use-mpcc; - st,invalid-input-detect-mute; - /* 2 (half-bridge) and 1 (full-bridge) on-board power */ - st,output-conf = /bits/ 8 <0x1>; - st,ch1-output-mapping = /bits/ 8 <0>; - st,ch2-output-mapping = /bits/ 8 <1>; - st,ch3-output-mapping = /bits/ 8 <2>; - st,needs_esd_watchdog; - }; -}; - -&pinctrl { - xo_audio_pins: xo-audio-pins { - pinctrl-single,pins = < - MFP_PIN_PXA300(111) MFP_AF0 /* ENABLE */ - >; - pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_LOW); - }; - - sta320_pins: sta320-pins { - pinctrl-single,pins = < - MFP_PIN_PXA300(120) MFP_AF0 /* CODEC_RESET */ - >; - pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_FLOAT); - }; -}; diff --git a/sys/gnu/dts/arm/pxa300-raumfeld-speaker-s.dts b/sys/gnu/dts/arm/pxa300-raumfeld-speaker-s.dts deleted file mode 100644 index 36e20cbf870..00000000000 --- a/sys/gnu/dts/arm/pxa300-raumfeld-speaker-s.dts +++ /dev/null @@ -1,11 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -/dts-v1/; - -#include "pxa300-raumfeld-common.dtsi" -#include "pxa300-raumfeld-tuneable-clock.dtsi" - -/ { - model = "Raumfeld Speaker S (PXA3xx)"; - compatible = "raumfeld,raumfeld-speaker-s-pxa303", "marvell,pxa300"; -}; diff --git a/sys/gnu/dts/arm/pxa300-raumfeld-tuneable-clock.dtsi b/sys/gnu/dts/arm/pxa300-raumfeld-tuneable-clock.dtsi deleted file mode 100644 index 561483b9398..00000000000 --- a/sys/gnu/dts/arm/pxa300-raumfeld-tuneable-clock.dtsi +++ /dev/null @@ -1,85 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -#include - -/ { - xo_27mhz: oscillator-27mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <27000000>; - clock-accuracy = <100>; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "Raumfeld Speaker"; - #address-cells = <1>; - #size-cells = <0>; - - simple-audio-card,dai-link@0 { - reg = <0>; - format = "i2s"; - bitclock-master = <&dailink_master_analog>; - frame-master = <&dailink_master_analog>; - mclk-fs = <256>; - - dailink_master_analog: cpu { - sound-dai = <&ssp_dai0>; - }; - - codec { - sound-dai = <&cs4270>; - }; - }; - }; -}; - -&ssp_dai0 { - clocks = <&max9485 MAX9485_CLKOUT1>; -}; - -&ssp_dai1 { - clocks = <&max9485 MAX9485_CLKOUT1>; -}; - -&pxai2c1 { - cs4270: codec@48 { - compatible = "cirrus,cs4270"; - pinctrl-names = "default"; - pinctrl-0 = <&cs4270_pins>; - reg = <0x48>; - va-supply = <®_va_5v0>; - vd-supply = <®_3v3>; - vlc-supply = <®_3v3>; - reset-gpios = <&gpio 120 GPIO_ACTIVE_HIGH>; - #sound-dai-cells = <0>; - }; - - max9485: clock-generator@63 { - compatible = "maxim,max9485"; - pinctrl-names = "default"; - pinctrl-0 = <&max9485_pins>; - reg = <0x63>; - vdd-supply = <®_3v3>; - clock-names = "xclk"; - clocks = <&xo_27mhz>; - reset-gpios = <&gpio 111 GPIO_ACTIVE_HIGH>; - #clock-cells = <1>; - }; -}; - -&pinctrl { - cs4270_pins: cs4270-pins { - pinctrl-single,pins = < - MFP_PIN_PXA300(120) MFP_AF0 /* RESET */ - >; - pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_LOW); - }; - - max9485_pins: max9485-pins { - pinctrl-single,pins = < - MFP_PIN_PXA300(111) MFP_AF0 /* RESET */ - >; - pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_LOW); - }; -}; diff --git a/sys/gnu/dts/arm/pxa3xx.dtsi b/sys/gnu/dts/arm/pxa3xx.dtsi deleted file mode 100644 index c237a0e4b12..00000000000 --- a/sys/gnu/dts/arm/pxa3xx.dtsi +++ /dev/null @@ -1,317 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* The pxa3xx skeleton simply augments the 2xx version */ -#include "pxa2xx.dtsi" - -#define MFP_PIN_PXA300(gpio) \ - ((gpio <= 2) ? (0x00b4 + 4 * gpio) : \ - (gpio <= 26) ? (0x027c + 4 * (gpio - 3)) : \ - (gpio <= 98) ? (0x0400 + 4 * (gpio - 27)) : \ - (gpio <= 127) ? (0x0600 + 4 * (gpio - 99)) : \ - 0) -#define MFP_PIN_PXA300_2(gpio) \ - ((gpio <= 1) ? (0x674 + 4 * gpio) : \ - (gpio <= 6) ? (0x2dc + 4 * gpio) : \ - 0) - -#define MFP_PIN_PXA310(gpio) \ - ((gpio <= 2) ? (0x00b4 + 4 * gpio) : \ - (gpio <= 26) ? (0x027c + 4 * (gpio - 3)) : \ - (gpio <= 29) ? (0x0400 + 4 * (gpio - 27)) : \ - (gpio <= 98) ? (0x0418 + 4 * (gpio - 30)) : \ - (gpio <= 127) ? (0x0600 + 4 * (gpio - 99)) : \ - (gpio <= 262) ? 0 : \ - (gpio <= 268) ? (0x052c + 4 * (gpio - 263)) : \ - 0) -#define MFP_PIN_PXA310_2(gpio) \ - ((gpio <= 1) ? (0x674 + 4 * gpio) : \ - (gpio <= 6) ? (0x2dc + 4 * gpio) : \ - (gpio <= 10) ? (0x52c + 4 * gpio) : \ - 0) - -#define MFP_PIN_PXA320(gpio) \ - ((gpio <= 4) ? (0x0124 + 4 * gpio) : \ - (gpio <= 9) ? (0x028c + 4 * (gpio - 5)) : \ - (gpio <= 10) ? (0x0458 + 4 * (gpio - 10)) : \ - (gpio <= 26) ? (0x02a0 + 4 * (gpio - 11)) : \ - (gpio <= 48) ? (0x0400 + 4 * (gpio - 27)) : \ - (gpio <= 62) ? (0x045c + 4 * (gpio - 49)) : \ - (gpio <= 73) ? (0x04b4 + 4 * (gpio - 63)) : \ - (gpio <= 98) ? (0x04f0 + 4 * (gpio - 74)) : \ - (gpio <= 127) ? (0x0600 + 4 * (gpio - 99)) : \ - 0) -#define MFP_PIN_PXA320_2(gpio) \ - ((gpio <= 3) ? (0x674 + 4 * gpio) : \ - (gpio <= 5) ? (0x284 + 4 * gpio) : \ - 0) - -/* - * MFP Alternate functions for pins having a gpio. - * Example of use: pinctrl-single,pins = < MFP_PIN_PXA310(21) MFP_AF1 > - */ -#define MFP_AF0 (0 << 0) -#define MFP_AF1 (1 << 0) -#define MFP_AF2 (2 << 0) -#define MFP_AF3 (3 << 0) -#define MFP_AF4 (4 << 0) -#define MFP_AF5 (5 << 0) -#define MFP_AF6 (6 << 0) - -/* - * MFP drive strength functions for pins. - * Example of use: pinctrl-single,drive-strength = MFP_DS03X; - */ -#define MFP_DSMSK (0x7 << 10) -#define MFP_DS01X < (0x0 << 10) MFP_DSMSK > -#define MFP_DS02X < (0x1 << 10) MFP_DSMSK > -#define MFP_DS03X < (0x2 << 10) MFP_DSMSK > -#define MFP_DS04X < (0x3 << 10) MFP_DSMSK > -#define MFP_DS06X < (0x4 << 10) MFP_DSMSK > -#define MFP_DS08X < (0x5 << 10) MFP_DSMSK > -#define MFP_DS10X < (0x6 << 10) MFP_DSMSK > -#define MFP_DS13X < (0x7 << 10) MFP_DSMSK > - -/* - * MFP bias pull mode for pins. - * Example of use: pinctrl-single,bias-pullup = MPF_PULL_UP; - */ -#define MPF_PULL_MSK (0x7 << 13) -#define MPF_PULL_DOWN < (0x5 << 13) (0x5 << 13) 0 MPF_PULL_MSK > -#define MPF_PULL_UP < (0x6 << 13) (0x6 << 13) 0 MPF_PULL_MSK > - -/* - * MFP low power mode for pins. - * Example of use: - * pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_LOW|MFP_LPM_EDGE_FALL); - * - * Table that determines the low power modes outputs, with actual settings - * used in parentheses for don't-care values. Except for the float output, - * the configured driven and pulled levels match, so if there is a need for - * non-LPM pulled output, the same configuration could probably be used. - * - * Output value sleep_oe_n sleep_data pullup_en pulldown_en pull_sel - * (bit 7) (bit 8) (bit 14) (bit 13) (bit 15) - * - * Input 0 X(0) X(0) X(0) 0 - * Drive 0 0 0 0 X(1) 0 - * Drive 1 0 1 X(1) 0 0 - * Pull hi (1) 1 X(1) 1 0 0 - * Pull lo (0) 1 X(0) 0 1 0 - * Z (float) 1 X(0) 0 0 0 - */ -#define MFP_LPM(x) < (x) MFP_LPM_MSK > - -#define MFP_LPM_MSK 0xe1f0 -#define MFP_LPM_INPUT 0x0000 -#define MFP_LPM_DRIVE_LOW 0x2000 -#define MFP_LPM_DRIVE_HIGH 0x4100 -#define MFP_LPM_PULL_LOW 0x2080 -#define MFP_LPM_PULL_HIGH 0x4180 -#define MFP_LPM_FLOAT 0x0080 - -#define MFP_LPM_EDGE_NONE 0x0000 -#define MFP_LPM_EDGE_RISE 0x0010 -#define MFP_LPM_EDGE_FALL 0x0020 -#define MFP_LPM_EDGE_BOTH 0x0030 - -/ { - model = "Marvell PXA3xx familiy SoC"; - compatible = "marvell,pxa3xx"; - - pxabus { - pdma: dma-controller@40000000 { - compatible = "marvell,pdma-1.0"; - reg = <0x40000000 0x10000>; - interrupts = <25>; - #dma-channels = <32>; - #dma-cells = <2>; - #dma-requests = <100>; - status = "okay"; - }; - - pwri2c: i2c@40f500c0 { - compatible = "mrvl,pwri2c"; - reg = <0x40f500c0 0x30>; - interrupts = <6>; - clocks = <&clks CLK_PWRI2C>; - #address-cells = <0x1>; - #size-cells = <0>; - status = "disabled"; - }; - - nand_controller: nand-controller@43100000 { - compatible = "marvell,pxa3xx-nand-controller"; - reg = <0x43100000 90>; - interrupts = <45>; - clocks = <&clks CLK_NAND>; - clock-names = "core"; - dmas = <&pdma 97 3>; - dma-names = "data"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - pxairq: interrupt-controller@40d00000 { - marvell,intc-priority; - marvell,intc-nr-irqs = <56>; - }; - - pinctrl: pinctrl@40e10000 { - compatible = "pinconf-single"; - reg = <0x40e10000 0xffff>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0x7>; - }; - - gpio: gpio@40e00000 { - compatible = "intel,pxa3xx-gpio"; - reg = <0x40e00000 0x10000>; - clocks = <&clks CLK_GPIO>; - gpio-ranges = <&pinctrl 0 0 128>; - interrupt-names = "gpio0", "gpio1", "gpio_mux"; - interrupts = <8 9 10>; - gpio-controller; - #gpio-cells = <0x2>; - interrupt-controller; - #interrupt-cells = <0x2>; - }; - - mmc0: mmc@41100000 { - compatible = "marvell,pxa-mmc"; - reg = <0x41100000 0x1000>; - interrupts = <23>; - clocks = <&clks CLK_MMC1>; - dmas = <&pdma 21 3 - &pdma 22 3>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - mmc1: mmc@42000000 { - compatible = "marvell,pxa-mmc"; - reg = <0x42000000 0x1000>; - interrupts = <41>; - clocks = <&clks CLK_MMC2>; - dmas = <&pdma 93 3 - &pdma 94 3>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - mmc2: mmc@42500000 { - compatible = "marvell,pxa-mmc"; - reg = <0x42500000 0x1000>; - interrupts = <55>; - clocks = <&clks CLK_MMC3>; - dmas = <&pdma 46 3 - &pdma 47 3>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - usb0: usb@4c000000 { - compatible = "marvell,pxa-ohci"; - reg = <0x4c000000 0x10000>; - interrupts = <3>; - clocks = <&clks CLK_USBH>; - status = "disabled"; - }; - - pwm0: pwm@40b00000 { - compatible = "marvell,pxa270-pwm"; - reg = <0x40b00000 0x10>; - #pwm-cells = <1>; - clocks = <&clks CLK_PWM0>; - status = "disabled"; - }; - - pwm1: pwm@40b00010 { - compatible = "marvell,pxa270-pwm"; - reg = <0x40b00010 0x10>; - #pwm-cells = <1>; - clocks = <&clks CLK_PWM1>; - status = "disabled"; - }; - - pwm2: pwm@40c00000 { - compatible = "marvell,pxa270-pwm"; - reg = <0x40c00000 0x10>; - #pwm-cells = <1>; - clocks = <&clks CLK_PWM0>; - status = "disabled"; - }; - - pwm3: pwm@40c00010 { - compatible = "marvell,pxa270-pwm"; - reg = <0x40c00010 0x10>; - #pwm-cells = <1>; - clocks = <&clks CLK_PWM1>; - status = "disabled"; - }; - - ssp1: ssp@41000000 { - compatible = "mrvl,pxa3xx-ssp"; - reg = <0x41000000 0x40>; - interrupts = <24>; - clocks = <&clks CLK_SSP1>; - status = "disabled"; - }; - - ssp2: ssp@41700000 { - compatible = "mrvl,pxa3xx-ssp"; - reg = <0x41700000 0x40>; - interrupts = <16>; - clocks = <&clks CLK_SSP2>; - status = "disabled"; - }; - - ssp3: ssp@41900000 { - compatible = "mrvl,pxa3xx-ssp"; - reg = <0x41900000 0x40>; - interrupts = <0>; - clocks = <&clks CLK_SSP3>; - status = "disabled"; - }; - - ssp4: ssp@41a00000 { - compatible = "mrvl,pxa3xx-ssp"; - reg = <0x41a00000 0x40>; - interrupts = <13>; - clocks = <&clks CLK_SSP4>; - status = "disabled"; - }; - - timer@40a00000 { - compatible = "marvell,pxa-timer"; - reg = <0x40a00000 0x20>; - interrupts = <26>; - clocks = <&clks CLK_OSTIMER>; - status = "okay"; - }; - - gcu: display-controller@54000000 { - compatible = "marvell,pxa300-gcu"; - reg = <0x54000000 0x1000>; - interrupts = <39>; - clocks = <&clks CLK_PXA300_GCU>; - status = "disabled"; - }; - }; - - clocks { - /* - * The muxing of external clocks/internal dividers for osc* clock - * sources has been hidden under the carpet by now. - */ - #address-cells = <1>; - #size-cells = <1>; - ranges; - - clks: clocks { - compatible = "marvell,pxa300-clocks"; - #clock-cells = <1>; - status = "okay"; - }; - }; -}; diff --git a/sys/gnu/dts/arm/pxa910-dkb.dts b/sys/gnu/dts/arm/pxa910-dkb.dts deleted file mode 100644 index 0f899e672e8..00000000000 --- a/sys/gnu/dts/arm/pxa910-dkb.dts +++ /dev/null @@ -1,172 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Marvell Technology Group Ltd. - * Author: Haojian Zhuang - */ - -/dts-v1/; -#include "pxa910.dtsi" - -/ { - model = "Marvell PXA910 DKB Development Board"; - compatible = "mrvl,pxa910-dkb", "mrvl,pxa910"; - - chosen { - bootargs = "console=ttyS0,115200 root=/dev/nfs nfsroot=192.168.1.100:/nfsroot/ ip=192.168.1.101:192.168.1.100::255.255.255.0::eth0:on"; - }; - - memory { - reg = <0x00000000 0x10000000>; - }; - - soc { - apb@d4000000 { - uart1: uart@d4017000 { - status = "okay"; - }; - twsi1: i2c@d4011000 { - status = "okay"; - - pmic: 88pm860x@34 { - compatible = "marvell,88pm860x"; - reg = <0x34>; - interrupts = <4>; - interrupt-parent = <&intc>; - interrupt-controller; - #interrupt-cells = <1>; - - marvell,88pm860x-irq-read-clr; - marvell,88pm860x-slave-addr = <0x11>; - - regulators { - BUCK1 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - regulator-always-on; - }; - BUCK2 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - regulator-always-on; - }; - BUCK3 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - LDO1 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <2800000>; - regulator-boot-on; - regulator-always-on; - }; - LDO2 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - LDO3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - LDO4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - LDO5 { - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - LDO6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - LDO7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2900000>; - regulator-boot-on; - regulator-always-on; - }; - LDO8 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2900000>; - regulator-boot-on; - regulator-always-on; - }; - LDO9 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - LDO10 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - LDO12 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - LDO13 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - LDO14 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - rtc { - marvell,88pm860x-vrtc = <1>; - }; - touch { - marvell,88pm860x-gpadc-prebias = <1>; - marvell,88pm860x-gpadc-slot-cycle = <1>; - marvell,88pm860x-tsi-prebias = <6>; - marvell,88pm860x-pen-prebias = <16>; - marvell,88pm860x-pen-prechg = <2>; - marvell,88pm860x-resistor-X = <300>; - }; - backlights { - backlight-0 { - marvell,88pm860x-iset = <4>; - marvell,88pm860x-pwm = <3>; - }; - backlight-2 { - }; - }; - leds { - led0-red { - marvell,88pm860x-iset = <12>; - }; - led0-green { - marvell,88pm860x-iset = <12>; - }; - led0-blue { - marvell,88pm860x-iset = <12>; - }; - }; - }; - }; - rtc: rtc@d4010000 { - status = "okay"; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/pxa910.dtsi b/sys/gnu/dts/arm/pxa910.dtsi deleted file mode 100644 index b3d6182d4de..00000000000 --- a/sys/gnu/dts/arm/pxa910.dtsi +++ /dev/null @@ -1,174 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Marvell Technology Group Ltd. - * Author: Haojian Zhuang - */ - -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - - aliases { - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - i2c0 = &twsi1; - i2c1 = &twsi2; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&intc>; - ranges; - - L2: l2-cache { - compatible = "marvell,tauros2-cache"; - marvell,tauros2-cache-features = <0x3>; - }; - - axi@d4200000 { /* AXI */ - compatible = "mrvl,axi-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0xd4200000 0x00200000>; - ranges; - - intc: interrupt-controller@d4282000 { - compatible = "mrvl,mmp-intc"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0xd4282000 0x1000>; - mrvl,intc-nr-irqs = <64>; - }; - - }; - - apb@d4000000 { /* APB */ - compatible = "mrvl,apb-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0xd4000000 0x00200000>; - ranges; - - timer0: timer@d4014000 { - compatible = "mrvl,mmp-timer"; - reg = <0xd4014000 0x100>; - interrupts = <13>; - }; - - timer1: timer@d4016000 { - compatible = "mrvl,mmp-timer"; - reg = <0xd4016000 0x100>; - interrupts = <29>; - status = "disabled"; - }; - - uart1: uart@d4017000 { - compatible = "mrvl,mmp-uart"; - reg = <0xd4017000 0x1000>; - interrupts = <27>; - clocks = <&soc_clocks PXA910_CLK_UART0>; - resets = <&soc_clocks PXA910_CLK_UART0>; - status = "disabled"; - }; - - uart2: uart@d4018000 { - compatible = "mrvl,mmp-uart"; - reg = <0xd4018000 0x1000>; - interrupts = <28>; - clocks = <&soc_clocks PXA910_CLK_UART1>; - resets = <&soc_clocks PXA910_CLK_UART1>; - status = "disabled"; - }; - - uart3: uart@d4036000 { - compatible = "mrvl,mmp-uart"; - reg = <0xd4036000 0x1000>; - interrupts = <59>; - clocks = <&soc_clocks PXA910_CLK_UART2>; - resets = <&soc_clocks PXA910_CLK_UART2>; - status = "disabled"; - }; - - gpio@d4019000 { - compatible = "marvell,mmp-gpio"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0xd4019000 0x1000>; - gpio-controller; - #gpio-cells = <2>; - interrupts = <49>; - interrupt-names = "gpio_mux"; - clocks = <&soc_clocks PXA910_CLK_GPIO>; - resets = <&soc_clocks PXA910_CLK_GPIO>; - interrupt-controller; - #interrupt-cells = <1>; - ranges; - - gcb0: gpio@d4019000 { - reg = <0xd4019000 0x4>; - }; - - gcb1: gpio@d4019004 { - reg = <0xd4019004 0x4>; - }; - - gcb2: gpio@d4019008 { - reg = <0xd4019008 0x4>; - }; - - gcb3: gpio@d4019100 { - reg = <0xd4019100 0x4>; - }; - }; - - twsi1: i2c@d4011000 { - compatible = "mrvl,mmp-twsi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xd4011000 0x1000>; - interrupts = <7>; - clocks = <&soc_clocks PXA910_CLK_TWSI0>; - resets = <&soc_clocks PXA910_CLK_TWSI0>; - mrvl,i2c-fast-mode; - status = "disabled"; - }; - - twsi2: i2c@d4037000 { - compatible = "mrvl,mmp-twsi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xd4037000 0x1000>; - interrupts = <54>; - clocks = <&soc_clocks PXA910_CLK_TWSI1>; - resets = <&soc_clocks PXA910_CLK_TWSI1>; - status = "disabled"; - }; - - rtc: rtc@d4010000 { - compatible = "mrvl,mmp-rtc"; - reg = <0xd4010000 0x1000>; - interrupts = <5 6>; - interrupt-names = "rtc 1Hz", "rtc alarm"; - clocks = <&soc_clocks PXA910_CLK_RTC>; - resets = <&soc_clocks PXA910_CLK_RTC>; - status = "disabled"; - }; - }; - - soc_clocks: clocks{ - compatible = "marvell,pxa910-clock"; - reg = <0xd4050000 0x1000>, - <0xd4282800 0x400>, - <0xd4015000 0x1000>, - <0xd403b000 0x1000>; - reg-names = "mpmu", "apmu", "apbc", "apbcp"; - #clock-cells = <1>; - #reset-cells = <1>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/qcom-apq8060-dragonboard.dts b/sys/gnu/dts/arm/qcom-apq8060-dragonboard.dts deleted file mode 100644 index 4e6c50d45cb..00000000000 --- a/sys/gnu/dts/arm/qcom-apq8060-dragonboard.dts +++ /dev/null @@ -1,960 +0,0 @@ -/* - * Copyright 2016 Linaro Ltd - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include -#include -#include -#include -#include "qcom-msm8660.dtsi" - -/ { - model = "Qualcomm APQ8060 Dragonboard"; - compatible = "qcom,apq8060-dragonboard", "qcom,msm8660"; - - aliases { - serial0 = &gsbi12_serial; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - regulators { - compatible = "simple-bus"; - - /* Main power of the board: 3.7V */ - vph: regulator-fixed { - compatible = "regulator-fixed"; - regulator-min-microvolt = <3700000>; - regulator-max-microvolt = <3700000>; - regulator-name = "VPH"; - regulator-type = "voltage"; - regulator-always-on; - regulator-boot-on; - }; - - /* GPIO controlled ethernet power regulator */ - dragon_veth: xc622a331mrg { - compatible = "regulator-fixed"; - regulator-name = "XC6222A331MR-G"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vph>; - gpio = <&pm8058_gpio 40 GPIO_ACTIVE_HIGH>; - enable-active-high; - pinctrl-names = "default"; - pinctrl-0 = <&dragon_veth_gpios>; - regulator-always-on; - }; - - /* VDDvario fixed regulator */ - dragon_vario: nds332p { - compatible = "regulator-fixed"; - regulator-name = "NDS332P"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&pm8058_s3>; - }; - - /* This is a levelshifter for SDCC5 */ - dragon_vio_txb: txb0104rgyr { - compatible = "regulator-fixed"; - regulator-name = "Dragon SDCC levelshifter"; - vin-supply = <&pm8058_l14>; - regulator-always-on; - }; - }; - - /* - * Capella CM3605 light and proximity sensor mounted directly - * on the sensor board. - */ - cm3605 { - compatible = "capella,cm3605"; - vdd-supply = <&pm8058_l14>; // 2.85V - aset-gpios = <&pm8058_gpio 35 GPIO_ACTIVE_LOW>; - capella,aset-resistance-ohms = <100000>; - /* Trig on both edges - getting close or far away */ - interrupts-extended = <&pm8058_gpio 34 IRQ_TYPE_EDGE_BOTH>; - /* MPP05 analog input to the XOADC */ - io-channels = <&xoadc 0x00 0x05>; - io-channel-names = "aout"; - pinctrl-names = "default"; - pinctrl-0 = <&dragon_cm3605_gpios>, <&dragon_cm3605_mpps>; - }; - - soc { - pinctrl@800000 { - /* eMMMC pins, all 8 data lines connected */ - dragon_sdcc1_pins: sdcc1 { - mux { - pins = "gpio159", "gpio160", "gpio161", - "gpio162", "gpio163", "gpio164", - "gpio165", "gpio166", "gpio167", - "gpio168"; - function = "sdc1"; - }; - clk { - pins = "gpio167"; /* SDC1 CLK */ - drive-strength = <16>; - bias-disable; - }; - cmd { - pins = "gpio168"; /* SDC1 CMD */ - drive-strength = <10>; - bias-pull-up; - }; - data { - /* SDC1 D0 to D7 */ - pins = "gpio159", "gpio160", "gpio161", "gpio162", - "gpio163", "gpio164", "gpio165", "gpio166"; - drive-strength = <10>; - bias-pull-up; - }; - }; - - /* - * The SDCC3 pins are hardcoded (non-muxable) but need some pin - * configuration. - */ - dragon_sdcc3_pins: sdcc3 { - clk { - pins = "sdc3_clk"; - drive-strength = <8>; - bias-disable; - }; - cmd { - pins = "sdc3_cmd"; - drive-strength = <8>; - bias-pull-up; - }; - data { - pins = "sdc3_data"; - drive-strength = <8>; - bias-pull-up; - }; - }; - - /* Second SD card slot pins */ - dragon_sdcc5_pins: sdcc5 { - mux { - pins = "gpio95", "gpio96", "gpio97", - "gpio98", "gpio99", "gpio100"; - function = "sdc5"; - }; - clk { - pins = "gpio97"; /* SDC5 CLK */ - drive-strength = <16>; - bias-disable; - }; - cmd { - pins = "gpio95"; /* SDC5 CMD */ - drive-strength = <10>; - bias-pull-up; - }; - data { - /* SDC5 D0 to D3 */ - pins = "gpio96", "gpio98", "gpio99", "gpio100"; - drive-strength = <10>; - bias-pull-up; - }; - }; - - dragon_gsbi8_i2c_pins: gsbi8_i2c { - mux { - pins = "gpio64", "gpio65"; - function = "gsbi8"; - }; - pinconf { - pins = "gpio64", "gpio65"; - drive-strength = <16>; - /* These have external pull-up 2.2kOhm to 1.8V */ - bias-disable; - }; - }; - - dragon_gsbi12_i2c_pins: gsbi12_i2c { - mux { - pins = "gpio115", "gpio116"; - function = "gsbi12"; - }; - pinconf { - pins = "gpio115", "gpio116"; - drive-strength = <16>; - /* These have external pull-up 4.7kOhm to 1.8V */ - bias-disable; - }; - }; - - /* Primary serial port uart 0 pins */ - dragon_gsbi12_serial_pins: gsbi12_serial { - mux { - pins = "gpio117", "gpio118"; - function = "gsbi12"; - }; - tx { - pins = "gpio117"; - drive-strength = <8>; - bias-disable; - }; - rx { - pins = "gpio118"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - dragon_ebi2_pins: ebi2 { - /* - * Pins used by EBI2 on the Dragonboard, actually only - * CS2 is used by a real peripheral. CS0 is just - * routed to a test point. - */ - mux0 { - pins = - /* "gpio39", CS1A_N this is not good to mux */ - "gpio40", /* CS2A_N */ - "gpio134"; /* CS0_N testpoint TP29 */ - function = "ebi2cs"; - }; - mux1 { - pins = - /* EBI2_ADDR_7 downto EBI2_ADDR_0 address bus */ - "gpio123", "gpio124", "gpio125", "gpio126", - "gpio127", "gpio128", "gpio129", "gpio130", - /* EBI2_DATA_15 downto EBI2_DATA_0 data bus */ - "gpio135", "gpio136", "gpio137", "gpio138", - "gpio139", "gpio140", "gpio141", "gpio142", - "gpio143", "gpio144", "gpio145", "gpio146", - "gpio147", "gpio148", "gpio149", "gpio150", - "gpio151", /* EBI2_OE_N */ - "gpio153", /* EBI2_ADV */ - "gpio157"; /* EBI2_WE_N */ - function = "ebi2"; - }; - }; - - /* Interrupt line for the KXSD9 accelerometer */ - dragon_kxsd9_gpios: kxsd9 { - irq { - pins = "gpio57"; /* IRQ line */ - bias-pull-up; - }; - }; - }; - - qcom,ssbi@500000 { - pmic@0 { - keypad@148 { - linux,keymap = < - MATRIX_KEY(0, 0, KEY_MENU) - MATRIX_KEY(0, 2, KEY_1) - MATRIX_KEY(0, 3, KEY_4) - MATRIX_KEY(0, 4, KEY_7) - MATRIX_KEY(1, 0, KEY_UP) - MATRIX_KEY(1, 1, KEY_LEFT) - MATRIX_KEY(1, 2, KEY_DOWN) - MATRIX_KEY(1, 3, KEY_5) - MATRIX_KEY(1, 3, KEY_8) - MATRIX_KEY(2, 0, KEY_HOME) - MATRIX_KEY(2, 1, KEY_REPLY) - MATRIX_KEY(2, 2, KEY_2) - MATRIX_KEY(2, 3, KEY_6) - MATRIX_KEY(3, 0, KEY_VOLUMEUP) - MATRIX_KEY(3, 1, KEY_RIGHT) - MATRIX_KEY(3, 2, KEY_3) - MATRIX_KEY(3, 3, KEY_9) - MATRIX_KEY(3, 4, KEY_SWITCHVIDEOMODE) - MATRIX_KEY(4, 0, KEY_VOLUMEDOWN) - MATRIX_KEY(4, 1, KEY_BACK) - MATRIX_KEY(4, 2, KEY_CAMERA) - MATRIX_KEY(4, 3, KEY_KBDILLUMTOGGLE) - >; - keypad,num-rows = <6>; - keypad,num-columns = <5>; - }; - - gpio@150 { - dragon_ethernet_gpios: ethernet-gpios { - pinconf { - pins = "gpio7"; - function = "normal"; - input-enable; - bias-disable; - power-source = ; - }; - }; - dragon_bmp085_gpios: bmp085-gpios { - pinconf { - pins = "gpio16"; - function = "normal"; - input-enable; - bias-disable; - power-source = ; - }; - }; - dragon_mpu3050_gpios: mpu3050-gpios { - pinconf { - pins = "gpio17"; - function = "normal"; - input-enable; - bias-disable; - power-source = ; - }; - }; - dragon_sdcc3_gpios: sdcc3-gpios { - pinconf { - pins = "gpio22"; - function = "normal"; - input-enable; - bias-disable; - power-source = ; - }; - }; - dragon_sdcc5_gpios: sdcc5-gpios { - pinconf { - pins = "gpio26"; - function = "normal"; - input-enable; - bias-pull-up; - qcom,pull-up-strength = ; - power-source = ; - }; - }; - dragon_ak8975_gpios: ak8975-gpios { - pinconf { - pins = "gpio33"; - function = "normal"; - input-enable; - bias-disable; - power-source = ; - }; - }; - dragon_cm3605_gpios: cm3605-gpios { - /* Pin 34 connected to the proxy IRQ */ - pinconf_gpio34 { - pins = "gpio34"; - function = "normal"; - input-enable; - bias-disable; - power-source = ; - }; - /* Pin 35 connected to ASET */ - pinconf_gpio35 { - pins = "gpio35"; - function = "normal"; - output-high; - bias-disable; - power-source = ; - }; - }; - dragon_veth_gpios: veth-gpios { - pinconf { - pins = "gpio40"; - function = "normal"; - bias-disable; - drive-push-pull; - }; - }; - }; - - mpps@50 { - dragon_cm3605_mpps: cm3605-mpps { - pinconf { - pins = "mpp5"; - function = "analog"; - input-enable; - bias-high-impedance; - /* Let's use channel 5 */ - qcom,amux-route = ; - power-source = ; - }; - }; - }; - - xoadc@197 { - /* Reference voltage 2.2 V */ - xoadc-ref-supply = <&pm8058_l18>; - - /* Board-specific channels */ - mpp5@5 { - /* Connected to AOUT of ALS sensor */ - reg = <0x00 0x05>; - }; - mpp6@6 { - /* Connected to test point TP43 */ - reg = <0x00 0x06>; - }; - mpp7@7 { - /* Connected to battery thermistor */ - reg = <0x00 0x07>; - }; - mpp8@8 { - /* Connected to battery ID detector */ - reg = <0x00 0x08>; - }; - mpp9@9 { - /* Connected to XO thermistor */ - reg = <0x00 0x09>; - }; - }; - - led@48 { - /* - * The keypad LED @0x48 is routed to - * the sensor board where it is - * connected to an infrared LED - * SFH4650 (60mW, @850nm) next to the - * ambient light and proximity sensor - * Capella Microsystems CM3605. - */ - compatible = "qcom,pm8058-keypad-led"; - reg = <0x48>; - label = "pm8058:infrared:proximitysensor"; - default-state = "off"; - linux,default-trigger = "cm3605"; - }; - led@131 { - compatible = "qcom,pm8058-led"; - reg = <0x131>; - label = "pm8058:red"; - default-state = "off"; - }; - led@132 { - /* - * This is actually green too on my - * board, but documented as yellow. - */ - compatible = "qcom,pm8058-led"; - reg = <0x132>; - label = "pm8058:yellow"; - default-state = "off"; - linux,default-trigger = "mmc0"; - }; - led@133 { - compatible = "qcom,pm8058-led"; - reg = <0x133>; - label = "pm8058:green"; - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - }; - }; - - gsbi@19800000 { - status = "ok"; - qcom,mode = ; - - i2c@19880000 { - status = "ok"; - pinctrl-names = "default"; - pinctrl-0 = <&dragon_gsbi8_i2c_pins>; - - eeprom@52 { - /* A 16KiB Platform ID EEPROM on the CPU carrier board */ - compatible = "atmel,24c128"; - reg = <0x52>; - vcc-supply = <&pm8058_s3>; - pagesize = <64>; - }; - wm8903: wm8903@1a { - /* This Woolfson Micro device has an unrouted interrupt line */ - compatible = "wlf,wm8903"; - reg = <0x1a>; - - AVDD-supply = <&pm8058_l16>; - CPVDD-supply = <&pm8058_l16>; - DBVDD-supply = <&pm8058_s3>; - DCVDD-supply = <&pm8058_l0>; - - gpio-controller; - #gpio-cells = <2>; - - micdet-cfg = <0>; - micdet-delay = <100>; - gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>; - }; - }; - }; - - gsbi@19c00000 { - status = "ok"; - qcom,mode = ; - - serial@19c40000 { - status = "ok"; - pinctrl-names = "default"; - pinctrl-0 = <&dragon_gsbi12_serial_pins>; - }; - - i2c@19c80000 { - status = "ok"; - pinctrl-names = "default"; - pinctrl-0 = <&dragon_gsbi12_i2c_pins>; - - ak8975@c { - compatible = "asahi-kasei,ak8975"; - reg = <0x0c>; - interrupt-parent = <&pm8058_gpio>; - interrupts = <33 IRQ_TYPE_EDGE_RISING>; - pinctrl-names = "default"; - pinctrl-0 = <&dragon_ak8975_gpios>; - vid-supply = <&pm8058_lvs0>; // 1.8V - vdd-supply = <&pm8058_l14>; // 2.85V - }; - bmp085@77 { - compatible = "bosch,bmp085"; - reg = <0x77>; - interrupt-parent = <&pm8058_gpio>; - interrupts = <16 IRQ_TYPE_EDGE_RISING>; - reset-gpios = <&tlmm 86 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&dragon_bmp085_gpios>; - vddd-supply = <&pm8058_lvs0>; // 1.8V - vdda-supply = <&pm8058_l14>; // 2.85V - }; - mpu3050@68 { - compatible = "invensense,mpu3050"; - reg = <0x68>; - /* - * GPIO17 is pulled high by a 10k - * resistor to VLOGIC so needs to be - * active low/falling edge. - */ - interrupts-extended = <&pm8058_gpio 17 IRQ_TYPE_EDGE_FALLING>; - pinctrl-names = "default"; - pinctrl-0 = <&dragon_mpu3050_gpios>; - vlogic-supply = <&pm8058_lvs0>; // 1.8V - vdd-supply = <&pm8058_l14>; // 2.85V - - /* - * The MPU-3050 acts as a hub for the - * accelerometer. - */ - i2c-gate { - #address-cells = <1>; - #size-cells = <0>; - - kxsd9@18 { - compatible = "kionix,kxsd9"; - reg = <0x18>; - interrupt-parent = <&tlmm>; - interrupts = <57 IRQ_TYPE_EDGE_FALLING>; - pinctrl-names = "default"; - pinctrl-0 = <&dragon_kxsd9_gpios>; - iovdd-supply = <&pm8058_lvs0>; // 1.8V - vdd-supply = <&pm8058_l14>; // 2.85V - }; - }; - }; - }; - }; - - external-bus@1a100000 { - /* The EBI2 will instantiate first, then populate its children */ - status = "ok"; - pinctrl-names = "default"; - pinctrl-0 = <&dragon_ebi2_pins>; - - /* - * An on-board SMSC LAN9221 chip for "debug ethernet", - * which is actually just an ordinary ethernet on the - * EBI2. This has a 25MHz chrystal next to it, so no - * clocking is needed. - */ - ethernet-ebi2@2,0 { - compatible = "smsc,lan9221", "smsc,lan9115"; - reg = <2 0x0 0x100>; - /* - * The second interrupt is the PME interrupt - * for network wakeup, connected to the TLMM. - */ - interrupts-extended = <&pm8058_gpio 7 IRQ_TYPE_EDGE_FALLING>, - <&tlmm 29 IRQ_TYPE_EDGE_RISING>; - reset-gpios = <&tlmm 30 GPIO_ACTIVE_LOW>; - vdd33a-supply = <&dragon_veth>; - vddvario-supply = <&dragon_vario>; - pinctrl-names = "default"; - pinctrl-0 = <&dragon_ethernet_gpios>; - phy-mode = "mii"; - reg-io-width = <2>; - smsc,force-external-phy; - /* IRQ on edge falling = active low */ - smsc,irq-active-low; - smsc,irq-push-pull; - - /* - * SLOW chipselect config - * Delay 9 cycles (140ns@64MHz) between SMSC - * LAN9221 Ethernet controller reads and writes - * on CS2. - */ - qcom,xmem-recovery-cycles = <0>; - qcom,xmem-write-hold-cycles = <3>; - qcom,xmem-write-delta-cycles = <31>; - qcom,xmem-read-delta-cycles = <28>; - qcom,xmem-write-wait-cycles = <9>; - qcom,xmem-read-wait-cycles = <9>; - }; - }; - - rpm@104000 { - /* - * Set up of the PMIC RPM regulators for this board - * PM8901 supplies "preliminary regulators" whatever - * that means - */ - pm8901-regulators { - vdd_l0-supply = <&pm8901_s4>; - vdd_l1-supply = <&vph>; - vdd_l2-supply = <&vph>; - vdd_l3-supply = <&vph>; - vdd_l4-supply = <&vph>; - vdd_l5-supply = <&vph>; - vdd_l6-supply = <&vph>; - /* vdd_s0-supply, vdd_s1-supply: SAW regulators */ - vdd_s2-supply = <&vph>; - vdd_s3-supply = <&vph>; - vdd_s4-supply = <&vph>; - lvs0_in-supply = <&pm8058_s3>; - lvs1_in-supply = <&pm8901_s4>; - lvs2_in-supply = <&pm8058_l0>; - lvs3_in-supply = <&pm8058_s2>; - mvs_in-supply = <&pm8058_s3>; - - l0 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - bias-pull-down; - }; - l1 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - bias-pull-down; - }; - l2 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <3300000>; - bias-pull-down; - }; - l3 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - bias-pull-down; - }; - l4 { - regulator-min-microvolt = <2600000>; - regulator-max-microvolt = <2600000>; - bias-pull-down; - }; - l5 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - bias-pull-down; - }; - l6 { - regulator-min-microvolt = <2200000>; - regulator-max-microvolt = <2200000>; - bias-pull-down; - }; - - /* s0 and s1 are SAW regulators controlled over SPM */ - s2 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - qcom,switch-mode-frequency = <1600000>; - bias-pull-down; - }; - s3 { - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - qcom,switch-mode-frequency = <1600000>; - bias-pull-down; - }; - s4 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - qcom,switch-mode-frequency = <1600000>; - bias-pull-down; - }; - - /* LVS0 thru 3 and mvs0 are just switches */ - lvs0 { - regulator-always-on; - }; - lvs1 { }; - lvs2 { }; - lvs3 { }; - mvs0 {}; - - }; - - pm8058-regulators { - vdd_l0_l1_lvs-supply = <&pm8058_s3>; - vdd_l2_l11_l12-supply = <&vph>; - vdd_l3_l4_l5-supply = <&vph>; - vdd_l6_l7-supply = <&vph>; - vdd_l8-supply = <&vph>; - vdd_l9-supply = <&vph>; - vdd_l10-supply = <&vph>; - vdd_l13_l16-supply = <&pm8058_s4>; - vdd_l14_l15-supply = <&vph>; - vdd_l17_l18-supply = <&vph>; - vdd_l19_l20-supply = <&vph>; - vdd_l21-supply = <&pm8058_s3>; - vdd_l22-supply = <&pm8058_s3>; - vdd_l23_l24_l25-supply = <&pm8058_s3>; - vdd_s0-supply = <&vph>; - vdd_s1-supply = <&vph>; - vdd_s2-supply = <&vph>; - vdd_s3-supply = <&vph>; - vdd_s4-supply = <&vph>; - vdd_ncp-supply = <&vph>; - - l0 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - bias-pull-down; - }; - l1 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - bias-pull-down; - }; - l2 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2600000>; - bias-pull-down; - }; - l3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - bias-pull-down; - }; - l4 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - bias-pull-down; - }; - l5 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - bias-pull-down; - }; - l6 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3600000>; - bias-pull-down; - }; - l7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - bias-pull-down; - }; - l8 { - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <3050000>; - bias-pull-down; - }; - l9 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - bias-pull-down; - }; - l10 { - regulator-min-microvolt = <2600000>; - regulator-max-microvolt = <2600000>; - bias-pull-down; - }; - l11 { - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - bias-pull-down; - }; - l12 { - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - bias-pull-down; - }; - l13 { - regulator-min-microvolt = <2050000>; - regulator-max-microvolt = <2050000>; - bias-pull-down; - }; - l14 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - l15 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - bias-pull-down; - }; - l16 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - bias-pull-down; - regulator-always-on; - }; - l17 { - // 1.5V according to schematic - regulator-min-microvolt = <2600000>; - regulator-max-microvolt = <2600000>; - bias-pull-down; - }; - l18 { - regulator-min-microvolt = <2200000>; - regulator-max-microvolt = <2200000>; - bias-pull-down; - }; - l19 { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - bias-pull-down; - }; - l20 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - bias-pull-down; - }; - l21 { - // 1.1 V according to schematic - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - bias-pull-down; - regulator-always-on; - }; - l22 { - // 1.2 V according to schematic - regulator-min-microvolt = <1150000>; - regulator-max-microvolt = <1150000>; - bias-pull-down; - }; - l23 { - // Unused - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - bias-pull-down; - }; - l24 { - // Unused - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - bias-pull-down; - }; - l25 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - bias-pull-down; - }; - - s0 { - // regulator-min-microvolt = <500000>; - // regulator-max-microvolt = <1325000>; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - qcom,switch-mode-frequency = <1600000>; - bias-pull-down; - }; - s1 { - // regulator-min-microvolt = <500000>; - // regulator-max-microvolt = <1250000>; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - qcom,switch-mode-frequency = <1600000>; - bias-pull-down; - }; - s2 { - // 1.3 V according to schematic - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1400000>; - qcom,switch-mode-frequency = <1600000>; - bias-pull-down; - }; - s3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - qcom,switch-mode-frequency = <1600000>; - regulator-always-on; - bias-pull-down; - }; - s4 { - regulator-min-microvolt = <2200000>; - regulator-max-microvolt = <2200000>; - qcom,switch-mode-frequency = <1600000>; - regulator-always-on; - bias-pull-down; - }; - - /* LVS0 and LVS1 are just switches */ - lvs0 { - bias-pull-down; - }; - lvs1 { - bias-pull-down; - }; - - ncp { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - qcom,switch-mode-frequency = <1600000>; - }; - }; - }; - amba { - /* Internal 3.69 GiB eMMC */ - sdcc@12400000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&dragon_sdcc1_pins>; - vmmc-supply = <&pm8901_l5>; - vqmmc-supply = <&pm8901_lvs0>; - }; - - /* External micro SD card, directly connected, pulled up to 2.85 V */ - sdcc@12180000 { - status = "okay"; - /* Enable SSBI GPIO 22 as input, use for card detect */ - pinctrl-names = "default"; - pinctrl-0 = <&dragon_sdcc3_pins>, <&dragon_sdcc3_gpios>; - cd-gpios = <&pm8058_gpio 22 GPIO_ACTIVE_LOW>; - wp-gpios = <&tlmm 110 GPIO_ACTIVE_HIGH>; - vmmc-supply = <&pm8058_l14>; - }; - - /* - * Second external micro SD card, using two TXB104RGYR levelshifters - * to lift from 1.8 V to 2.85 V - */ - sdcc@12200000 { - status = "okay"; - /* Enable SSBI GPIO 26 as input, use for card detect */ - pinctrl-names = "default"; - pinctrl-0 = <&dragon_sdcc5_pins>, <&dragon_sdcc5_gpios>; - cd-gpios = <&pm8058_gpio 26 GPIO_ACTIVE_LOW>; - wp-gpios = <&tlmm 106 GPIO_ACTIVE_HIGH>; - vmmc-supply = <&pm8058_l14>; - vqmmc-supply = <&dragon_vio_txb>; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/qcom-apq8064-arrow-db600c-pins.dtsi b/sys/gnu/dts/arm/qcom-apq8064-arrow-db600c-pins.dtsi deleted file mode 100644 index a3efb9704fc..00000000000 --- a/sys/gnu/dts/arm/qcom-apq8064-arrow-db600c-pins.dtsi +++ /dev/null @@ -1,52 +0,0 @@ -&tlmm_pinmux { - card_detect: card-detect { - mux { - pins = "gpio26"; - function = "gpio"; - bias-disable; - }; - }; - - pcie_pins: pcie-pinmux { - mux { - pins = "gpio27"; - function = "gpio"; - }; - conf { - pins = "gpio27"; - drive-strength = <12>; - bias-disable; - }; - }; - - user_leds: user-leds { - mux { - pins = "gpio3", "gpio7", "gpio10", "gpio11"; - function = "gpio"; - }; - - conf { - pins = "gpio3", "gpio7", "gpio10", "gpio11"; - function = "gpio"; - output-low; - }; - }; - - magneto_pins: magneto-pins { - mux { - pins = "gpio31", "gpio48"; - function = "gpio"; - bias-disable; - }; - }; -}; - -&pm8921_mpps { - mpp_leds: mpp-leds { - pinconf { - pins = "mpp7", "mpp8"; - function = "digital"; - output-low; - }; - }; -}; diff --git a/sys/gnu/dts/arm/qcom-apq8064-arrow-db600c.dts b/sys/gnu/dts/arm/qcom-apq8064-arrow-db600c.dts deleted file mode 100644 index e01b27ea7fb..00000000000 --- a/sys/gnu/dts/arm/qcom-apq8064-arrow-db600c.dts +++ /dev/null @@ -1,349 +0,0 @@ -#include "qcom-apq8064-v2.0.dtsi" -#include "qcom-apq8064-arrow-db600c-pins.dtsi" -#include - -/ { - model = "Arrow Electronics, APQ8064 DB600c"; - compatible = "arrow,db600c", "qcom,apq8064"; - - aliases { - serial0 = &gsbi7_serial; - serial1 = &gsbi1_serial; - i2c0 = &gsbi2_i2c; - i2c1 = &gsbi3_i2c; - i2c2 = &gsbi4_i2c; - i2c3 = &gsbi7_i2c; - spi0 = &gsbi5_spi; - }; - - regulators { - compatible = "simple-bus"; - vph: regulator-fixed@1 { - compatible = "regulator-fixed"; - regulator-min-microvolt = <4500000>; - regulator-max-microvolt = <4500000>; - regulator-name = "VPH"; - regulator-type = "voltage"; - regulator-boot-on; - }; - - /* on board fixed 3.3v supply */ - vcc3v3: vcc3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - }; - - soc { - rpm@108000 { - regulators { - vdd_s1-supply = <&vph>; - vdd_s2-supply = <&vph>; - vdd_s3-supply = <&vph>; - vdd_s4-supply = <&vph>; - vdd_s5-supply = <&vph>; - vdd_s6-supply = <&vph>; - vdd_s7-supply = <&vph>; - vdd_l1_l2_l12_l18-supply = <&pm8921_s4>; - vdd_l3_l15_l17-supply = <&vph>; - vdd_l4_l14-supply = <&vph>; - vdd_l5_l8_l16-supply = <&vph>; - vdd_l6_l7-supply = <&vph>; - vdd_l9_l11-supply = <&vph>; - vdd_l10_l22-supply = <&vph>; - vdd_l21_l23_l29-supply = <&vph>; - vdd_l24-supply = <&pm8921_s1>; - vdd_l25-supply = <&pm8921_s1>; - vdd_l26-supply = <&pm8921_s7>; - vdd_l27-supply = <&pm8921_s7>; - vdd_l28-supply = <&pm8921_s7>; - vin_lvs1_3_6-supply = <&pm8921_s4>; - vin_lvs2-supply = <&pm8921_s1>; - vin_lvs4_5_7-supply = <&pm8921_s4>; - - s1 { - regulator-always-on; - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - qcom,switch-mode-frequency = <3200000>; - bias-pull-down; - }; - - s3 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - qcom,switch-mode-frequency = <4800000>; - }; - - s4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - qcom,switch-mode-frequency = <3200000>; - bias-pull-down; - regulator-always-on; - }; - - s7 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - qcom,switch-mode-frequency = <3200000>; - }; - - l3 { - regulator-min-microvolt = <3050000>; - regulator-max-microvolt = <3300000>; - bias-pull-down; - }; - - l4 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1800000>; - bias-pull-down; - }; - - l5 { - regulator-min-microvolt = <2750000>; - regulator-max-microvolt = <3000000>; - bias-pull-down; - regulator-boot-on; - regulator-always-on; - }; - - l6 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - bias-pull-down; - }; - - l23 { - regulator-min-microvolt = <1700000>; - regulator-max-microvolt = <1900000>; - bias-pull-down; - }; - - lvs6 { - bias-pull-down; - }; - - lvs7 { - bias-pull-down; - }; - }; - }; - - gsbi@12440000 { - status = "okay"; - qcom,mode = ; - serial@12450000 { - label = "LS-UART1"; - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&gsbi1_uart_4pins>; - }; - }; - - gsbi@12480000 { - status = "okay"; - qcom,mode = ; - i2c@124a0000 { - /* On Low speed expansion and Sensors */ - label = "LS-I2C0"; - status = "okay"; - lis3mdl_mag@1e { - compatible = "st,lis3mdl-magn"; - reg = <0x1e>; - vdd-supply = <&vcc3v3>; - vddio-supply = <&pm8921_s4>; - pinctrl-names = "default"; - pinctrl-0 = <&magneto_pins>; - interrupt-parent = <&tlmm_pinmux>; - - st,drdy-int-pin = <2>; - interrupts = <48 IRQ_TYPE_EDGE_RISING>, /* DRDY line */ - <31 IRQ_TYPE_EDGE_RISING>; /* INT */ - }; - }; - }; - - gsbi@16200000 { - status = "okay"; - qcom,mode = ; - i2c@16280000 { - /* On Low speed expansion */ - status = "okay"; - label = "LS-I2C1"; - clock-frequency = <200000>; - eeprom@52 { - compatible = "atmel,24c128"; - reg = <0x52>; - pagesize = <64>; - }; - }; - }; - - gsbi@16300000 { - status = "okay"; - qcom,mode = ; - i2c@16380000 { - /* On High speed expansion */ - label = "HS-CAM-I2C3"; - status = "okay"; - }; - }; - - gsbi@1a200000 { - status = "okay"; - spi@1a280000 { - /* On Low speed expansion */ - label = "LS-SPI0"; - status = "okay"; - }; - }; - - /* DEBUG UART */ - gsbi@16600000 { - status = "okay"; - qcom,mode = ; - serial@16640000 { - label = "LS-UART0"; - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&gsbi7_uart_2pins>; - }; - - i2c@16680000 { - /* On High speed expansion */ - status = "okay"; - label = "HS-CAM-I2C2"; - }; - }; - - leds { - pinctrl-names = "default"; - pinctrl-0 = <&user_leds>, <&mpp_leds>; - - compatible = "gpio-leds"; - - user-led0 { - label = "user0-led"; - gpios = <&tlmm_pinmux 3 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - - user-led1 { - label = "user1-led"; - gpios = <&tlmm_pinmux 7 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc0"; - default-state = "off"; - }; - - user-led2 { - label = "user2-led"; - gpios = <&tlmm_pinmux 10 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc1"; - default-state = "off"; - }; - - user-led3 { - label = "user3-led"; - gpios = <&tlmm_pinmux 11 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "none"; - default-state = "off"; - }; - - wifi-led { - label = "WiFi-led"; - gpios = <&pm8921_mpps 7 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - bt-led { - label = "BT-led"; - gpios = <&pm8921_mpps 8 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - - pci@1b500000 { - status = "okay"; - vdda-supply = <&pm8921_s3>; - vdda_phy-supply = <&pm8921_lvs6>; - vdda_refclk-supply = <&vcc3v3>; - pinctrl-0 = <&pcie_pins>; - pinctrl-names = "default"; - perst-gpio = <&tlmm_pinmux 27 GPIO_ACTIVE_LOW>; - }; - - phy@1b400000 { - status = "okay"; - }; - - sata@29000000 { - status = "okay"; - target-supply = <&pm8921_lvs7>; - }; - - /* OTG */ - phy@12500000 { - status = "okay"; - dr_mode = "peripheral"; - vddcx-supply = <&pm8921_s3>; - v3p3-supply = <&pm8921_l3>; - v1p8-supply = <&pm8921_l4>; - }; - - phy@12520000 { - status = "okay"; - vddcx-supply = <&pm8921_s3>; - v3p3-supply = <&pm8921_l3>; - v1p8-supply = <&pm8921_l23>; - }; - - phy@12530000 { - status = "okay"; - vddcx-supply = <&pm8921_s3>; - v3p3-supply = <&pm8921_l3>; - v1p8-supply = <&pm8921_l23>; - }; - - gadget@12500000 { - status = "okay"; - }; - - /* OTG */ - usb@12500000 { - status = "okay"; - }; - - usb@12520000 { - status = "okay"; - }; - - usb@12530000 { - status = "okay"; - }; - - amba { - /* eMMC */ - sdcc@12400000 { - status = "okay"; - vmmc-supply = <&pm8921_l5>; - vqmmc-supply = <&pm8921_s4>; - }; - - /* External micro SD card */ - sdcc@12180000 { - status = "okay"; - vmmc-supply = <&pm8921_l6>; - pinctrl-names = "default"; - pinctrl-0 = <&card_detect>; - cd-gpios = <&tlmm_pinmux 26 GPIO_ACTIVE_HIGH>; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/qcom-apq8064-asus-nexus7-flo.dts b/sys/gnu/dts/arm/qcom-apq8064-asus-nexus7-flo.dts deleted file mode 100644 index a701d4bac32..00000000000 --- a/sys/gnu/dts/arm/qcom-apq8064-asus-nexus7-flo.dts +++ /dev/null @@ -1,359 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "qcom-apq8064-v2.0.dtsi" -#include -#include -#include -/ { - model = "Asus Nexus7(flo)"; - compatible = "asus,nexus7-flo", "qcom,apq8064"; - - aliases { - serial0 = &gsbi7_serial; - serial1 = &gsbi6_serial; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - ramoops@88d00000{ - compatible = "ramoops"; - reg = <0x88d00000 0x100000>; - record-size = <0x00020000>; - console-size = <0x00020000>; - ftrace-size = <0x00020000>; - }; - }; - - ext_3p3v: regulator-fixed@1 { - compatible = "regulator-fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "ext_3p3v"; - regulator-type = "voltage"; - startup-delay-us = <0>; - gpio = <&tlmm_pinmux 77 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-boot-on; - }; - - gpio-keys { - compatible = "gpio-keys"; - volume_up { - label = "Volume Up"; - gpios = <&pm8921_gpio 4 GPIO_ACTIVE_HIGH>; - linux,code = ; - }; - volume_down { - label = "Volume Down"; - gpios = <&pm8921_gpio 38 GPIO_ACTIVE_HIGH>; - linux,code = ; - }; - }; - - soc { - rpm@108000 { - regulators { - vdd_l1_l2_l12_l18-supply = <&pm8921_s4>; - vin_lvs1_3_6-supply = <&pm8921_s4>; - vin_lvs4_5_7-supply = <&pm8921_s4>; - - - vdd_l24-supply = <&pm8921_s1>; - vdd_l25-supply = <&pm8921_s1>; - vin_lvs2-supply = <&pm8921_s1>; - - vdd_l26-supply = <&pm8921_s7>; - vdd_l27-supply = <&pm8921_s7>; - vdd_l28-supply = <&pm8921_s7>; - - vdd_ncp-supply = <&pm8921_l6>; - - /* Buck SMPS */ - s1 { - regulator-always-on; - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - qcom,switch-mode-frequency = <3200000>; - bias-pull-down; - }; - - /* msm otg HSUSB_VDDCX */ - s3 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1150000>; - qcom,switch-mode-frequency = <4800000>; - }; - - /* - * msm_sdcc.1-sdc-vdd_io - * tabla2x-slim-CDC_VDDA_RX - * tabla2x-slim-CDC_VDDA_TX - * tabla2x-slim-CDC_VDD_CP - * tabla2x-slim-VDDIO_CDC - */ - s4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - qcom,switch-mode-frequency = <3200000>; - regulator-always-on; - }; - - s7 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - qcom,switch-mode-frequency = <3200000>; - }; - - /* mipi_dsi.1-dsi1_pll_vdda */ - l2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - /* msm_otg-HSUSB_3p3 */ - l3 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3075000>; - bias-pull-down; - }; - - /* msm_otg-HSUSB_1p8 */ - l4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - bias-pull-down; - }; - - /* msm_sdcc.1-sdc_vdd */ - l5 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - regulator-always-on; - bias-pull-down; - }; - - l6 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - }; - - /* mipi_dsi.1-dsi1_avdd */ - l11 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - bias-pull-down; - regulator-always-on; - }; - - /* pwm_power for backlight */ - l17 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - }; - - /* camera, qdsp6 */ - l23 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - bias-pull-down; - }; - - /* - * tabla2x-slim-CDC_VDDA_A_1P2V - * tabla2x-slim-VDDD_CDC_D - */ - l25 { - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1250000>; - bias-pull-down; - }; - - lvs1 { - bias-pull-down; - }; - - lvs4 { - bias-pull-down; - }; - - lvs5 { - bias-pull-down; - }; - - lvs6 { - bias-pull-down; - }; - /* - * mipi_dsi.1-dsi1_vddio - * pil_riva-pll_vdd - */ - lvs7 { - bias-pull-down; - }; - }; - }; - - mdp@5100000 { - status = "okay"; - ports { - port@1 { - mdp_dsi1_out: endpoint { - remote-endpoint = <&dsi0_in>; - }; - }; - }; - }; - - dsi0: mdss_dsi@4700000 { - status = "okay"; - vdda-supply = <&pm8921_l2>;/*VDD_MIPI1 to 4*/ - vdd-supply = <&pm8921_l8>; - vddio-supply = <&pm8921_lvs7>; - avdd-supply = <&pm8921_l11>; - vcss-supply = <&ext_3p3v>; - - panel@0 { - reg = <0>; - compatible = "jdi,lt070me05000"; - - vddp-supply = <&pm8921_l17>; - iovcc-supply = <&pm8921_lvs7>; - - enable-gpios = <&pm8921_gpio 36 GPIO_ACTIVE_HIGH>; - reset-gpios = <&tlmm_pinmux 54 GPIO_ACTIVE_LOW>; - dcdc-en-gpios = <&pm8921_gpio 23 GPIO_ACTIVE_HIGH>; - - port { - panel_in: endpoint { - remote-endpoint = <&dsi0_out>; - }; - }; - }; - ports { - port@0 { - dsi0_in: endpoint { - remote-endpoint = <&mdp_dsi1_out>; - }; - }; - - port@1 { - dsi0_out: endpoint { - remote-endpoint = <&panel_in>; - data-lanes = <0 1 2 3>; - }; - }; - }; - }; - - dsi-phy@4700200 { - status = "okay"; - vddio-supply = <&pm8921_lvs7>;/*VDD_PLL2_1 to 7*/ - }; - - gsbi@16200000 { - status = "okay"; - qcom,mode = ; - i2c@16280000 { - status = "okay"; - clock-frequency = <200000>; - pinctrl-0 = <&i2c3_pins>; - pinctrl-names = "default"; - - trackpad@10 { - compatible = "elan,ekth3500"; - reg = <0x10>; - interrupt-parent = <&tlmm_pinmux>; - interrupts = <6 IRQ_TYPE_EDGE_FALLING>; - }; - }; - }; - - - gsbi@12440000 { - status = "okay"; - qcom,mode = ; - - i2c@12460000 { - status = "okay"; - clock-frequency = <200000>; - pinctrl-0 = <&i2c1_pins>; - pinctrl-names = "default"; - - eeprom@52 { - compatible = "atmel,24c128"; - reg = <0x52>; - pagesize = <32>; - }; - - bq27541@55 { - compatible = "ti,bq27541"; - reg = <0x55>; - }; - - }; - }; - - gsbi@16500000 { - status = "ok"; - qcom,mode = ; - - serial@16540000 { - status = "ok"; - - pinctrl-names = "default"; - pinctrl-0 = <&gsbi6_uart_4pins>; - }; - }; - - gsbi@16600000 { - status = "ok"; - qcom,mode = ; - serial@16640000 { - status = "ok"; - }; - }; - - /* OTG */ - usb@12500000 { - status = "okay"; - dr_mode = "otg"; - ulpi { - phy { - v3p3-supply = <&pm8921_l3>; - v1p8-supply = <&pm8921_l4>; - }; - }; - }; - - amba { - /* eMMC */ - sdcc@12400000 { - status = "okay"; - vmmc-supply = <&pm8921_l5>; - vqmmc-supply = <&pm8921_s4>; - }; - }; - - imem@2a03f000 { - compatible = "syscon", "simple-mfd"; - reg = <0x2a03f000 0x1000>; - - reboot-mode { - compatible = "syscon-reboot-mode"; - offset = <0x65c>; - - mode-normal = <0x77665501>; - mode-bootloader = <0x77665500>; - mode-recovery = <0x77665502>; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/qcom-apq8064-cm-qs600.dts b/sys/gnu/dts/arm/qcom-apq8064-cm-qs600.dts deleted file mode 100644 index 209eb21cea0..00000000000 --- a/sys/gnu/dts/arm/qcom-apq8064-cm-qs600.dts +++ /dev/null @@ -1,246 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "qcom-apq8064-v2.0.dtsi" -#include -#include - -/ { - model = "CompuLab CM-QS600"; - compatible = "qcom,apq8064-cm-qs600", "qcom,apq8064"; - - aliases { - serial0 = &gsbi7_serial; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - pwrseq { - #address-cells = <1>; - #size-cells = <1>; - ranges; - compatible = "simple-bus"; - - sdcc4_pwrseq: sdcc4_pwrseq { - pinctrl-names = "default"; - pinctrl-0 = <&wlan_default_gpios>; - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&pm8921_gpio 43 GPIO_ACTIVE_LOW>; - }; - }; - - soc { - pinctrl@800000 { - card_detect: card_detect { - mux { - pins = "gpio26"; - function = "gpio"; - bias-disable; - }; - }; - - pcie_pins: pcie_pinmux { - mux { - pins = "gpio27"; - function = "gpio"; - }; - conf { - pins = "gpio27"; - drive-strength = <12>; - bias-disable; - }; - }; - }; - - rpm@108000 { - regulators { - vin_lvs1_3_6-supply = <&pm8921_s4>; - vin_lvs2-supply = <&pm8921_s1>; - vin_lvs4_5_7-supply = <&pm8921_s4>; - - vdd_l1_l2_l12_l18-supply = <&pm8921_s4>; - vdd_l24-supply = <&pm8921_s1>; - vdd_l25-supply = <&pm8921_s1>; - vdd_l26-supply = <&pm8921_s7>; - vdd_l27-supply = <&pm8921_s7>; - vdd_l28-supply = <&pm8921_s7>; - - - /* Buck SMPS */ - s1 { - regulator-always-on; - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - qcom,switch-mode-frequency = <3200000>; - bias-pull-down; - }; - - s3 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - qcom,switch-mode-frequency = <4800000>; - }; - - s4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - qcom,switch-mode-frequency = <3200000>; - }; - - s7 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - qcom,switch-mode-frequency = <3200000>; - }; - - l3 { - regulator-min-microvolt = <3050000>; - regulator-max-microvolt = <3300000>; - bias-pull-down; - }; - - l4 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1800000>; - bias-pull-down; - }; - - l5 { - regulator-min-microvolt = <2750000>; - regulator-max-microvolt = <3000000>; - bias-pull-down; - }; - - l23 { - regulator-min-microvolt = <1700000>; - regulator-max-microvolt = <1900000>; - bias-pull-down; - }; - - pm8921_lvs6: lvs6 { - bias-pull-down; - }; - - }; - }; - - gsbi@12440000 { - status = "okay"; - qcom,mode = ; - - i2c@12460000 { - status = "okay"; - clock-frequency = <200000>; - - eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - pagesize = <32>; - }; - }; - }; - - gsbi@16600000 { - status = "ok"; - qcom,mode = ; - serial@16640000 { - status = "ok"; - pinctrl-names = "default"; - pinctrl-0 = <&gsbi7_uart_2pins>; - }; - }; - - /* OTG */ - usb@12500000 { - status = "ok"; - dr_mode = "otg"; - ulpi { - phy { - v3p3-supply = <&pm8921_l3>; - v1p8-supply = <&pm8921_l4>; - }; - }; - }; - - usb@12520000 { - status = "okay"; - dr_mode = "host"; - ulpi { - phy { - v3p3-supply = <&pm8921_l3>; - v1p8-supply = <&pm8921_l23>; - }; - }; - }; - - usb@12530000 { - status = "okay"; - dr_mode = "host"; - ulpi { - phy { - v3p3-supply = <&pm8921_l3>; - v1p8-supply = <&pm8921_l23>; - }; - }; - }; - - /* on board fixed 3.3v supply */ - v3p3_fixed: v3p3 { - compatible = "regulator-fixed"; - regulator-name = "PCIE V3P3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - qcom,ssbi@500000 { - pmic@0 { - gpio@150 { - wlan_default_gpios: wlan-gpios { - pios { - pins = "gpio43"; - function = "normal"; - bias-disable; - power-source = ; - }; - }; - }; - }; - }; - - pci@1b500000 { - status = "ok"; - vdda-supply = <&pm8921_s3>; - vdda_phy-supply = <&pm8921_lvs6>; - vdda_refclk-supply = <&v3p3_fixed>; - pinctrl-0 = <&pcie_pins>; - pinctrl-names = "default"; - perst-gpio = <&tlmm_pinmux 27 GPIO_ACTIVE_LOW>; - }; - - amba { - /* eMMC */ - sdcc1: sdcc@12400000 { - status = "okay"; - vmmc-supply = <&pm8921_l5>; - vqmmc-supply = <&pm8921_s4>; - }; - - /* External micro SD card */ - sdcc3: sdcc@12180000 { - status = "okay"; - vmmc-supply = <&v3p3_fixed>; - pinctrl-names = "default"; - pinctrl-0 = <&card_detect>; - cd-gpios = <&tlmm_pinmux 26 GPIO_ACTIVE_LOW>; - }; - /* WLAN */ - sdcc4: sdcc@121c0000 { - status = "okay"; - vmmc-supply = <&v3p3_fixed>; - vqmmc-supply = <&v3p3_fixed>; - mmc-pwrseq = <&sdcc4_pwrseq>; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/qcom-apq8064-ifc6410.dts b/sys/gnu/dts/arm/qcom-apq8064-ifc6410.dts deleted file mode 100644 index 83aaf4a7439..00000000000 --- a/sys/gnu/dts/arm/qcom-apq8064-ifc6410.dts +++ /dev/null @@ -1,381 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "qcom-apq8064-v2.0.dtsi" -#include -#include - -/ { - model = "Qualcomm APQ8064/IFC6410"; - compatible = "qcom,apq8064-ifc6410", "qcom,apq8064"; - - aliases { - serial0 = &gsbi7_serial; - serial1 = &gsbi6_serial; - i2c0 = &gsbi1_i2c; - i2c1 = &gsbi2_i2c; - i2c2 = &gsbi3_i2c; - i2c3 = &gsbi4_i2c; - spi0 = &gsbi5_spi; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - pwrseq { - compatible = "simple-bus"; - - sdcc4_pwrseq: sdcc4_pwrseq { - pinctrl-names = "default"; - pinctrl-0 = <&wlan_default_gpios>; - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&pm8921_gpio 43 GPIO_ACTIVE_LOW>; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <¬ify_led>; - - led@1 { - label = "apq8064:green:user1"; - gpios = <&pm8921_gpio 18 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; - - hdmi-out { - compatible = "hdmi-connector"; - type = "d"; - - port { - hdmi_con: endpoint { - remote-endpoint = <&hdmi_out>; - }; - }; - }; - - soc { - pinctrl@800000 { - card_detect: card_detect { - mux { - pins = "gpio26"; - function = "gpio"; - bias-disable; - }; - }; - - pcie_pins: pcie_pinmux { - mux { - pins = "gpio27"; - function = "gpio"; - }; - conf { - pins = "gpio27"; - drive-strength = <12>; - bias-disable; - }; - }; - }; - - rpm@108000 { - regulators { - vin_lvs1_3_6-supply = <&pm8921_s4>; - vin_lvs2-supply = <&pm8921_s1>; - vin_lvs4_5_7-supply = <&pm8921_s4>; - - vdd_l1_l2_l12_l18-supply = <&pm8921_s4>; - vdd_l24-supply = <&pm8921_s1>; - vdd_l25-supply = <&pm8921_s1>; - vdd_l26-supply = <&pm8921_s7>; - vdd_l27-supply = <&pm8921_s7>; - vdd_l28-supply = <&pm8921_s7>; - - - /* Buck SMPS */ - s1 { - regulator-always-on; - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - qcom,switch-mode-frequency = <3200000>; - bias-pull-down; - }; - - s3 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - qcom,switch-mode-frequency = <4800000>; - }; - - s4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - qcom,switch-mode-frequency = <3200000>; - }; - - s7 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - qcom,switch-mode-frequency = <3200000>; - }; - - l3 { - regulator-min-microvolt = <3050000>; - regulator-max-microvolt = <3300000>; - bias-pull-down; - }; - - l4 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1800000>; - bias-pull-down; - }; - - l5 { - regulator-min-microvolt = <2750000>; - regulator-max-microvolt = <3000000>; - bias-pull-down; - }; - - l6 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - bias-pull-down; - }; - - l23 { - regulator-min-microvolt = <1700000>; - regulator-max-microvolt = <1900000>; - bias-pull-down; - }; - - lvs1 { - bias-pull-down; - }; - - lvs6 { - bias-pull-down; - }; - }; - }; - - ext_3p3v: regulator-fixed@1 { - compatible = "regulator-fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "ext_3p3v"; - regulator-type = "voltage"; - startup-delay-us = <0>; - gpio = <&tlmm_pinmux 77 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-boot-on; - }; - - gsbi3: gsbi@16200000 { - status = "okay"; - qcom,mode = ; - i2c@16280000 { - status = "okay"; - }; - }; - - gsbi@16300000 { - status = "okay"; - qcom,mode = ; - /* CAM I2C MIPI-CSI connector */ - i2c@16380000 { - status = "okay"; - }; - }; - - gsbi@12440000 { - status = "okay"; - qcom,mode = ; - - i2c@12460000 { - status = "okay"; - clock-frequency = <200000>; - - eeprom@52 { - compatible = "atmel,24c128"; - reg = <0x52>; - pagesize = <32>; - }; - }; - }; - - gsbi@1a200000 { - qcom,mode = ; - status = "okay"; - spi4: spi@1a280000 { - status = "okay"; - num-cs = <1>; - cs-gpios = <&tlmm_pinmux 53 0>; - }; - }; - - gsbi@16500000 { - status = "ok"; - qcom,mode = ; - - serial@16540000 { - status = "ok"; - pinctrl-names = "default"; - pinctrl-0 = <&gsbi6_uart_4pins>; - }; - }; - - gsbi@16600000 { - status = "ok"; - qcom,mode = ; - serial@16640000 { - status = "ok"; - pinctrl-names = "default"; - pinctrl-0 = <&gsbi7_uart_2pins>; - }; - }; - - sata_phy0: phy@1b400000 { - status = "okay"; - }; - - sata0: sata@29000000 { - status = "okay"; - target-supply = <&pm8921_s4>; - }; - - /* OTG */ - usb@12500000 { - status = "okay"; - dr_mode = "otg"; - ulpi { - phy { - v3p3-supply = <&pm8921_l3>; - v1p8-supply = <&pm8921_l4>; - }; - }; - }; - - usb@12520000 { - status = "okay"; - dr_mode = "host"; - ulpi { - phy { - v3p3-supply = <&pm8921_l3>; - v1p8-supply = <&pm8921_l23>; - }; - }; - }; - - usb@12530000 { - status = "okay"; - dr_mode = "host"; - ulpi { - phy { - v3p3-supply = <&pm8921_l3>; - v1p8-supply = <&pm8921_l23>; - }; - }; - }; - - pci@1b500000 { - status = "ok"; - vdda-supply = <&pm8921_s3>; - vdda_phy-supply = <&pm8921_lvs6>; - vdda_refclk-supply = <&ext_3p3v>; - pinctrl-0 = <&pcie_pins>; - pinctrl-names = "default"; - perst-gpio = <&tlmm_pinmux 27 GPIO_ACTIVE_LOW>; - }; - - qcom,ssbi@500000 { - pmic@0 { - gpio@150 { - wlan_default_gpios: wlan-gpios { - pios { - pins = "gpio43"; - function = "normal"; - bias-disable; - power-source = ; - }; - }; - - notify_led: nled { - pios { - pins = "gpio18"; - function = "normal"; - bias-disable; - power-source = ; - }; - }; - }; - }; - }; - - amba { - /* eMMC */ - sdcc1: sdcc@12400000 { - status = "okay"; - vmmc-supply = <&pm8921_l5>; - vqmmc-supply = <&pm8921_s4>; - }; - - /* External micro SD card */ - sdcc3: sdcc@12180000 { - status = "okay"; - vmmc-supply = <&pm8921_l6>; - pinctrl-names = "default"; - pinctrl-0 = <&card_detect>; - cd-gpios = <&tlmm_pinmux 26 GPIO_ACTIVE_LOW>; - }; - /* WLAN */ - sdcc4: sdcc@121c0000 { - status = "okay"; - vmmc-supply = <&ext_3p3v>; - vqmmc-supply = <&pm8921_lvs1>; - mmc-pwrseq = <&sdcc4_pwrseq>; - }; - }; - - hdmi-tx@4a00000 { - status = "okay"; - - core-vdda-supply = <&pm8921_hdmi_switch>; - hdmi-mux-supply = <&ext_3p3v>; - - hpd-gpios = <&tlmm_pinmux 72 GPIO_ACTIVE_HIGH>; - - ports { - port@0 { - endpoint { - remote-endpoint = <&mdp_dtv_out>; - }; - }; - - port@1 { - endpoint { - remote-endpoint = <&hdmi_con>; - }; - }; - }; - }; - - hdmi-phy@4a00400 { - status = "okay"; - - core-vdda-supply = <&pm8921_hdmi_switch>; - }; - - mdp@5100000 { - status = "okay"; - - ports { - port@3 { - endpoint { - remote-endpoint = <&hdmi_in>; - }; - }; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/qcom-apq8064-pins.dtsi b/sys/gnu/dts/arm/qcom-apq8064-pins.dtsi deleted file mode 100644 index cbe42c4153a..00000000000 --- a/sys/gnu/dts/arm/qcom-apq8064-pins.dtsi +++ /dev/null @@ -1,325 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -&tlmm_pinmux { - sdc4_gpios: sdc4-gpios { - pios { - pins = "gpio63", "gpio64", "gpio65", "gpio66", "gpio67", "gpio68"; - function = "sdc4"; - }; - }; - - sdcc1_pins: sdcc1-pin-active { - clk { - pins = "sdc1_clk"; - drive-strengh = <16>; - bias-disable; - }; - - cmd { - pins = "sdc1_cmd"; - drive-strengh = <10>; - bias-pull-up; - }; - - data { - pins = "sdc1_data"; - drive-strengh = <10>; - bias-pull-up; - }; - }; - - sdcc3_pins: sdcc3-pin-active { - clk { - pins = "sdc3_clk"; - drive-strengh = <8>; - bias-disable; - }; - - cmd { - pins = "sdc3_cmd"; - drive-strengh = <8>; - bias-pull-up; - }; - - data { - pins = "sdc3_data"; - drive-strengh = <8>; - bias-pull-up; - }; - }; - - ps_hold: ps_hold { - mux { - pins = "gpio78"; - function = "ps_hold"; - }; - }; - - i2c1_pins: i2c1 { - mux { - pins = "gpio20", "gpio21"; - function = "gsbi1"; - }; - - pinconf { - pins = "gpio20", "gpio21"; - drive-strength = <16>; - bias-disable; - }; - }; - - i2c1_pins_sleep: i2c1_pins_sleep { - mux { - pins = "gpio20", "gpio21"; - function = "gpio"; - }; - pinconf { - pins = "gpio20", "gpio21"; - drive-strength = <2>; - bias-disable = <0>; - }; - }; - - gsbi1_uart_2pins: gsbi1_uart_2pins { - mux { - pins = "gpio18", "gpio19"; - function = "gsbi1"; - }; - }; - - gsbi1_uart_4pins: gsbi1_uart_4pins { - mux { - pins = "gpio18", "gpio19", "gpio20", "gpio21"; - function = "gsbi1"; - }; - }; - - i2c2_pins: i2c2 { - mux { - pins = "gpio24", "gpio25"; - function = "gsbi2"; - }; - - pinconf { - pins = "gpio24", "gpio25"; - drive-strength = <16>; - bias-disable; - }; - }; - - i2c2_pins_sleep: i2c2_pins_sleep { - mux { - pins = "gpio24", "gpio25"; - function = "gpio"; - }; - - pinconf { - pins = "gpio24", "gpio25"; - drive-strength = <2>; - bias-disable = <0>; - }; - }; - - i2c3_pins: i2c3 { - mux { - pins = "gpio8", "gpio9"; - function = "gsbi3"; - }; - - pinconf { - pins = "gpio8", "gpio9"; - drive-strength = <16>; - bias-disable; - }; - }; - - i2c3_pins_sleep: i2c3_pins_sleep { - mux { - pins = "gpio8", "gpio9"; - function = "gpio"; - }; - pinconf { - pins = "gpio8", "gpio9"; - drive-strength = <2>; - bias-disable = <0>; - }; - }; - - i2c4_pins: i2c4 { - mux { - pins = "gpio12", "gpio13"; - function = "gsbi4"; - }; - - pinconf { - pins = "gpio12", "gpio13"; - drive-strength = <16>; - bias-disable; - }; - }; - - i2c4_pins_sleep: i2c4_pins_sleep { - mux { - pins = "gpio12", "gpio13"; - function = "gpio"; - }; - pinconf { - pins = "gpio12", "gpio13"; - drive-strength = <2>; - bias-disable = <0>; - }; - }; - - spi5_default: spi5_default { - pinmux { - pins = "gpio51", "gpio52", "gpio54"; - function = "gsbi5"; - }; - - pinmux_cs { - function = "gpio"; - pins = "gpio53"; - }; - - pinconf { - pins = "gpio51", "gpio52", "gpio54"; - drive-strength = <16>; - bias-disable; - }; - - pinconf_cs { - pins = "gpio53"; - drive-strength = <16>; - bias-disable; - output-high; - }; - }; - - spi5_sleep: spi5_sleep { - pinmux { - function = "gpio"; - pins = "gpio51", "gpio52", "gpio53", "gpio54"; - }; - - pinconf { - pins = "gpio51", "gpio52", "gpio53", "gpio54"; - drive-strength = <2>; - bias-pull-down; - }; - }; - - i2c6_pins: i2c6 { - mux { - pins = "gpio16", "gpio17"; - function = "gsbi6"; - }; - - pinconf { - pins = "gpio16", "gpio17"; - drive-strength = <16>; - bias-disable; - }; - }; - - i2c6_pins_sleep: i2c6_pins_sleep { - mux { - pins = "gpio16", "gpio17"; - function = "gpio"; - }; - pinconf { - pins = "gpio16", "gpio17"; - drive-strength = <2>; - bias-disable = <0>; - }; - }; - - gsbi6_uart_2pins: gsbi6_uart_2pins { - mux { - pins = "gpio14", "gpio15"; - function = "gsbi6"; - }; - }; - - gsbi6_uart_4pins: gsbi6_uart_4pins { - mux { - pins = "gpio14", "gpio15", "gpio16", "gpio17"; - function = "gsbi6"; - }; - }; - - gsbi7_uart_2pins: gsbi7_uart_2pins { - mux { - pins = "gpio82", "gpio83"; - function = "gsbi7"; - }; - }; - - gsbi7_uart_4pins: gsbi7_uart_4pins { - mux { - pins = "gpio82", "gpio83", "gpio84", "gpio85"; - function = "gsbi7"; - }; - }; - - i2c7_pins: i2c7 { - mux { - pins = "gpio84", "gpio85"; - function = "gsbi7"; - }; - - pinconf { - pins = "gpio84", "gpio85"; - drive-strength = <16>; - bias-disable; - }; - }; - - i2c7_pins_sleep: i2c7_pins_sleep { - mux { - pins = "gpio84", "gpio85"; - function = "gpio"; - }; - pinconf { - pins = "gpio84", "gpio85"; - drive-strength = <2>; - bias-disable = <0>; - }; - }; - - riva_fm_pin_a: riva-fm-active { - pins = "gpio14", "gpio15"; - function = "riva_fm"; - }; - - riva_bt_pin_a: riva-bt-active { - pins = "gpio16", "gpio17"; - function = "riva_bt"; - }; - - riva_wlan_pin_a: riva-wlan-active { - pins = "gpio64", "gpio65", "gpio66", "gpio67", "gpio68"; - function = "riva_wlan"; - - drive-strength = <6>; - bias-pull-down; - }; - - hdmi_pinctrl: hdmi-pinctrl { - mux { - pins = "gpio70", "gpio71", "gpio72"; - function = "hdmi"; - }; - - pinconf_ddc { - pins = "gpio70", "gpio71"; - bias-pull-up; - drive-strength = <2>; - }; - - pinconf_hpd { - pins = "gpio72"; - bias-pull-down; - drive-strength = <16>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/qcom-apq8064-sony-xperia-yuga.dts b/sys/gnu/dts/arm/qcom-apq8064-sony-xperia-yuga.dts deleted file mode 100644 index 8bf488fb86a..00000000000 --- a/sys/gnu/dts/arm/qcom-apq8064-sony-xperia-yuga.dts +++ /dev/null @@ -1,402 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "qcom-apq8064-v2.0.dtsi" -#include -#include -#include -#include - -/ { - model = "Sony Xperia Z"; - compatible = "sony,xperia-yuga", "qcom,apq8064"; - - aliases { - serial0 = &gsbi5_serial; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - gpio-keys { - compatible = "gpio-keys"; - input-name = "gpio-keys"; - - pinctrl-names = "default"; - pinctrl-0 = <&gpio_keys_pin_a>; - - camera-focus { - label = "camera_focus"; - gpios = <&pm8921_gpio 3 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - linux,code = ; - }; - - camera-snapshot { - label = "camera_snapshot"; - gpios = <&pm8921_gpio 4 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - linux,code = ; - }; - - volume-down { - label = "volume_down"; - gpios = <&pm8921_gpio 29 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - linux,code = ; - }; - - volume-up { - label = "volume_up"; - gpios = <&pm8921_gpio 35 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - linux,code = ; - }; - }; - - soc { - pinctrl@800000 { - gsbi5_uart_pin_a: gsbi5-uart-pin-active { - rx { - pins = "gpio52"; - function = "gsbi5"; - drive-strength = <2>; - bias-pull-up; - }; - - tx { - pins = "gpio51"; - function = "gsbi5"; - drive-strength = <4>; - bias-disable; - }; - }; - - - sdcc3_cd_pin_a: sdcc3-cd-pin-active { - pins = "gpio26"; - function = "gpio"; - - drive-strength = <2>; - bias-disable; - }; - }; - - - rpm@108000 { - regulators { - vin_l1_l2_l12_l18-supply = <&pm8921_s4>; - vin_lvs_1_3_6-supply = <&pm8921_s4>; - vin_lvs_4_5_7-supply = <&pm8921_s4>; - vin_ncp-supply = <&pm8921_l6>; - vin_lvs2-supply = <&pm8921_s4>; - vin_l24-supply = <&pm8921_s1>; - vin_l25-supply = <&pm8921_s1>; - vin_l27-supply = <&pm8921_s7>; - vin_l28-supply = <&pm8921_s7>; - - /* Buck SMPS */ - s1 { - regulator-always-on; - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - qcom,switch-mode-frequency = <3200000>; - bias-pull-down; - }; - - s2 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - qcom,switch-mode-frequency = <1600000>; - bias-pull-down; - }; - - s3 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1150000>; - qcom,switch-mode-frequency = <4800000>; - bias-pull-down; - }; - - s4 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - qcom,switch-mode-frequency = <1600000>; - bias-pull-down; - qcom,force-mode = ; - }; - - s7 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - qcom,switch-mode-frequency = <3200000>; - }; - - s8 { - regulator-min-microvolt = <2200000>; - regulator-max-microvolt = <2200000>; - qcom,switch-mode-frequency = <1600000>; - }; - - /* PMOS LDO */ - l1 { - regulator-always-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - bias-pull-down; - }; - - l2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - bias-pull-down; - }; - - l3 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3075000>; - bias-pull-down; - }; - - l4 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - bias-pull-down; - }; - - l5 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - bias-pull-down; - }; - - l6 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - bias-pull-down; - }; - - l7 { - regulator-min-microvolt = <1850000>; - regulator-max-microvolt = <2950000>; - bias-pull-down; - }; - - l8 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - bias-pull-down; - }; - - l9 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - bias-pull-down; - }; - - l10 { - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - bias-pull-down; - }; - - l11 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - bias-pull-down; - }; - - l12 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - bias-pull-down; - }; - - l14 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - bias-pull-down; - }; - - l15 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - bias-pull-down; - }; - - l16 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - bias-pull-down; - }; - - l17 { - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - bias-pull-down; - }; - - l18 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - bias-pull-down; - }; - - l21 { - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - bias-pull-down; - }; - - l22 { - regulator-min-microvolt = <2600000>; - regulator-max-microvolt = <2600000>; - bias-pull-down; - }; - - l23 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - bias-pull-down; - }; - - l24 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1150000>; - bias-pull-down; - }; - - l25 { - regulator-always-on; - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1250000>; - bias-pull-down; - }; - - l27 { - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - }; - - l28 { - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - bias-pull-down; - }; - - l29 { - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - bias-pull-down; - }; - - /* Low Voltage Switch */ - lvs1 { - bias-pull-down; - }; - - lvs2 { - bias-pull-down; - }; - - lvs3 { - bias-pull-down; - }; - - lvs4 { - bias-pull-down; - }; - - lvs5 { - bias-pull-down; - }; - - lvs6 { - bias-pull-down; - }; - - lvs7 { - bias-pull-down; - }; - - usb-switch {}; - - hdmi-switch {}; - - ncp { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - qcom,switch-mode-frequency = <1600000>; - }; - }; - }; - - qcom,ssbi@500000 { - pmic@0 { - gpio@150 { - gpio_keys_pin_a: gpio-keys-pin-active { - pins = "gpio3", "gpio4", "gpio29", "gpio35"; - function = "normal"; - - bias-pull-up; - drive-push-pull; - input-enable; - power-source = <2>; - qcom,drive-strength = ; - qcom,pull-up-strength = <0>; - }; - }; - }; - }; - - usb@12500000 { - status = "okay"; - dr_mode = "otg"; - ulpi { - phy { - v3p3-supply = <&pm8921_l3>; - v1p8-supply = <&pm8921_l4>; - }; - }; - }; - - gsbi@1a200000 { - status = "ok"; - qcom,mode = ; - - serial@1a240000 { - status = "ok"; - - pinctrl-names = "default"; - pinctrl-0 = <&gsbi5_uart_pin_a>; - }; - }; - - amba { - sdcc1: sdcc@12400000 { - status = "okay"; - - vmmc-supply = <&pm8921_l5>; - vqmmc-supply = <&pm8921_s4>; - }; - - sdcc3: sdcc@12180000 { - status = "okay"; - - vmmc-supply = <&pm8921_l6>; - cd-gpios = <&tlmm_pinmux 26 GPIO_ACTIVE_LOW>; - - pinctrl-names = "default"; - pinctrl-0 = <&sdcc3_pins>, <&sdcc3_cd_pin_a>; - }; - }; - - riva-pil@3204000 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&riva_wlan_pin_a>, <&riva_bt_pin_a>, <&riva_fm_pin_a>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/qcom-apq8064-v2.0.dtsi b/sys/gnu/dts/arm/qcom-apq8064-v2.0.dtsi deleted file mode 100644 index 46ed48f0244..00000000000 --- a/sys/gnu/dts/arm/qcom-apq8064-v2.0.dtsi +++ /dev/null @@ -1,2 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "qcom-apq8064.dtsi" diff --git a/sys/gnu/dts/arm/qcom-apq8064.dtsi b/sys/gnu/dts/arm/qcom-apq8064.dtsi deleted file mode 100644 index 8b79b4112ee..00000000000 --- a/sys/gnu/dts/arm/qcom-apq8064.dtsi +++ /dev/null @@ -1,1764 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include -#include -#include -#include -#include -#include -#include -/ { - #address-cells = <1>; - #size-cells = <1>; - model = "Qualcomm APQ8064"; - compatible = "qcom,apq8064"; - interrupt-parent = <&intc>; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - smem_region: smem@80000000 { - reg = <0x80000000 0x200000>; - no-map; - }; - - wcnss_mem: wcnss@8f000000 { - reg = <0x8f000000 0x700000>; - no-map; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - CPU0: cpu@0 { - compatible = "qcom,krait"; - enable-method = "qcom,kpss-acc-v1"; - device_type = "cpu"; - reg = <0>; - next-level-cache = <&L2>; - qcom,acc = <&acc0>; - qcom,saw = <&saw0>; - cpu-idle-states = <&CPU_SPC>; - }; - - CPU1: cpu@1 { - compatible = "qcom,krait"; - enable-method = "qcom,kpss-acc-v1"; - device_type = "cpu"; - reg = <1>; - next-level-cache = <&L2>; - qcom,acc = <&acc1>; - qcom,saw = <&saw1>; - cpu-idle-states = <&CPU_SPC>; - }; - - CPU2: cpu@2 { - compatible = "qcom,krait"; - enable-method = "qcom,kpss-acc-v1"; - device_type = "cpu"; - reg = <2>; - next-level-cache = <&L2>; - qcom,acc = <&acc2>; - qcom,saw = <&saw2>; - cpu-idle-states = <&CPU_SPC>; - }; - - CPU3: cpu@3 { - compatible = "qcom,krait"; - enable-method = "qcom,kpss-acc-v1"; - device_type = "cpu"; - reg = <3>; - next-level-cache = <&L2>; - qcom,acc = <&acc3>; - qcom,saw = <&saw3>; - cpu-idle-states = <&CPU_SPC>; - }; - - L2: l2-cache { - compatible = "cache"; - cache-level = <2>; - }; - - idle-states { - CPU_SPC: spc { - compatible = "qcom,idle-state-spc", - "arm,idle-state"; - entry-latency-us = <400>; - exit-latency-us = <900>; - min-residency-us = <3000>; - }; - }; - }; - - memory { - device_type = "memory"; - reg = <0x0 0x0>; - }; - - thermal-zones { - cpu-thermal0 { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&gcc 7>; - coefficients = <1199 0>; - - trips { - cpu_alert0: trip0 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu_crit0: trip1 { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - cpu-thermal1 { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&gcc 8>; - coefficients = <1132 0>; - - trips { - cpu_alert1: trip0 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu_crit1: trip1 { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - cpu-thermal2 { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&gcc 9>; - coefficients = <1199 0>; - - trips { - cpu_alert2: trip0 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu_crit2: trip1 { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - cpu-thermal3 { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&gcc 10>; - coefficients = <1132 0>; - - trips { - cpu_alert3: trip0 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu_crit3: trip1 { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - }; - - cpu-pmu { - compatible = "qcom,krait-pmu"; - interrupts = <1 10 0x304>; - }; - - clocks { - cxo_board: cxo_board { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <19200000>; - }; - - pxo_board { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <27000000>; - }; - - sleep_clk: sleep_clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - sfpb_mutex: hwmutex { - compatible = "qcom,sfpb-mutex"; - syscon = <&sfpb_wrapper_mutex 0x604 0x4>; - #hwlock-cells = <1>; - }; - - smem { - compatible = "qcom,smem"; - memory-region = <&smem_region>; - - hwlocks = <&sfpb_mutex 3>; - }; - - smd { - compatible = "qcom,smd"; - - modem@0 { - interrupts = <0 37 IRQ_TYPE_EDGE_RISING>; - - qcom,ipc = <&l2cc 8 3>; - qcom,smd-edge = <0>; - - status = "disabled"; - }; - - q6@1 { - interrupts = <0 90 IRQ_TYPE_EDGE_RISING>; - - qcom,ipc = <&l2cc 8 15>; - qcom,smd-edge = <1>; - - status = "disabled"; - }; - - dsps@3 { - interrupts = <0 138 IRQ_TYPE_EDGE_RISING>; - - qcom,ipc = <&sps_sic_non_secure 0x4080 0>; - qcom,smd-edge = <3>; - - status = "disabled"; - }; - - riva@6 { - interrupts = <0 198 IRQ_TYPE_EDGE_RISING>; - - qcom,ipc = <&l2cc 8 25>; - qcom,smd-edge = <6>; - - status = "disabled"; - }; - }; - - smsm { - compatible = "qcom,smsm"; - - #address-cells = <1>; - #size-cells = <0>; - - qcom,ipc-1 = <&l2cc 8 4>; - qcom,ipc-2 = <&l2cc 8 14>; - qcom,ipc-3 = <&l2cc 8 23>; - qcom,ipc-4 = <&sps_sic_non_secure 0x4094 0>; - - apps_smsm: apps@0 { - reg = <0>; - #qcom,smem-state-cells = <1>; - }; - - modem_smsm: modem@1 { - reg = <1>; - interrupts = <0 38 IRQ_TYPE_EDGE_RISING>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - q6_smsm: q6@2 { - reg = <2>; - interrupts = <0 89 IRQ_TYPE_EDGE_RISING>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - wcnss_smsm: wcnss@3 { - reg = <3>; - interrupts = <0 204 IRQ_TYPE_EDGE_RISING>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - dsps_smsm: dsps@4 { - reg = <4>; - interrupts = <0 137 IRQ_TYPE_EDGE_RISING>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - firmware { - scm { - compatible = "qcom,scm-apq8064"; - - clocks = <&rpmcc RPM_DAYTONA_FABRIC_CLK>; - clock-names = "core"; - }; - }; - - - /* - * These channels from the ADC are simply hardware monitors. - * That is why the ADC is referred to as "HKADC" - HouseKeeping - * ADC. - */ - iio-hwmon { - compatible = "iio-hwmon"; - io-channels = <&xoadc 0x00 0x01>, /* Battery */ - <&xoadc 0x00 0x02>, /* DC in (charger) */ - <&xoadc 0x00 0x04>, /* VPH the main system voltage */ - <&xoadc 0x00 0x0b>, /* Die temperature */ - <&xoadc 0x00 0x0c>, /* Reference voltage 1.25V */ - <&xoadc 0x00 0x0d>, /* Reference voltage 0.625V */ - <&xoadc 0x00 0x0e>; /* Charger temperature */ - }; - - soc: soc { - #address-cells = <1>; - #size-cells = <1>; - ranges; - compatible = "simple-bus"; - - tlmm_pinmux: pinctrl@800000 { - compatible = "qcom,apq8064-pinctrl"; - reg = <0x800000 0x4000>; - - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>; - - pinctrl-names = "default"; - pinctrl-0 = <&ps_hold>; - }; - - sfpb_wrapper_mutex: syscon@1200000 { - compatible = "syscon"; - reg = <0x01200000 0x8000>; - }; - - intc: interrupt-controller@2000000 { - compatible = "qcom,msm-qgic2"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0x02000000 0x1000>, - <0x02002000 0x1000>; - }; - - timer@200a000 { - compatible = "qcom,kpss-timer", - "qcom,kpss-wdt-apq8064", "qcom,msm-timer"; - interrupts = <1 1 0x301>, - <1 2 0x301>, - <1 3 0x301>; - reg = <0x0200a000 0x100>; - clock-frequency = <27000000>, - <32768>; - cpu-offset = <0x80000>; - }; - - acc0: clock-controller@2088000 { - compatible = "qcom,kpss-acc-v1"; - reg = <0x02088000 0x1000>, <0x02008000 0x1000>; - }; - - acc1: clock-controller@2098000 { - compatible = "qcom,kpss-acc-v1"; - reg = <0x02098000 0x1000>, <0x02008000 0x1000>; - }; - - acc2: clock-controller@20a8000 { - compatible = "qcom,kpss-acc-v1"; - reg = <0x020a8000 0x1000>, <0x02008000 0x1000>; - }; - - acc3: clock-controller@20b8000 { - compatible = "qcom,kpss-acc-v1"; - reg = <0x020b8000 0x1000>, <0x02008000 0x1000>; - }; - - saw0: power-controller@2089000 { - compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; - reg = <0x02089000 0x1000>, <0x02009000 0x1000>; - regulator; - }; - - saw1: power-controller@2099000 { - compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; - reg = <0x02099000 0x1000>, <0x02009000 0x1000>; - regulator; - }; - - saw2: power-controller@20a9000 { - compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; - reg = <0x020a9000 0x1000>, <0x02009000 0x1000>; - regulator; - }; - - saw3: power-controller@20b9000 { - compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; - reg = <0x020b9000 0x1000>, <0x02009000 0x1000>; - regulator; - }; - - sps_sic_non_secure: sps-sic-non-secure@12100000 { - compatible = "syscon"; - reg = <0x12100000 0x10000>; - }; - - gsbi1: gsbi@12440000 { - status = "disabled"; - compatible = "qcom,gsbi-v1.0.0"; - cell-index = <1>; - reg = <0x12440000 0x100>; - clocks = <&gcc GSBI1_H_CLK>; - clock-names = "iface"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - syscon-tcsr = <&tcsr>; - - gsbi1_serial: serial@12450000 { - compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; - reg = <0x12450000 0x100>, - <0x12400000 0x03>; - interrupts = <0 193 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - - gsbi1_i2c: i2c@12460000 { - compatible = "qcom,i2c-qup-v1.1.1"; - pinctrl-0 = <&i2c1_pins>; - pinctrl-1 = <&i2c1_pins_sleep>; - pinctrl-names = "default", "sleep"; - reg = <0x12460000 0x1000>; - interrupts = <0 194 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>; - clock-names = "core", "iface"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - }; - - gsbi2: gsbi@12480000 { - status = "disabled"; - compatible = "qcom,gsbi-v1.0.0"; - cell-index = <2>; - reg = <0x12480000 0x100>; - clocks = <&gcc GSBI2_H_CLK>; - clock-names = "iface"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - syscon-tcsr = <&tcsr>; - - gsbi2_i2c: i2c@124a0000 { - compatible = "qcom,i2c-qup-v1.1.1"; - reg = <0x124a0000 0x1000>; - pinctrl-0 = <&i2c2_pins>; - pinctrl-1 = <&i2c2_pins_sleep>; - pinctrl-names = "default", "sleep"; - interrupts = <0 196 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>; - clock-names = "core", "iface"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - gsbi3: gsbi@16200000 { - status = "disabled"; - compatible = "qcom,gsbi-v1.0.0"; - cell-index = <3>; - reg = <0x16200000 0x100>; - clocks = <&gcc GSBI3_H_CLK>; - clock-names = "iface"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - gsbi3_i2c: i2c@16280000 { - compatible = "qcom,i2c-qup-v1.1.1"; - pinctrl-0 = <&i2c3_pins>; - pinctrl-1 = <&i2c3_pins_sleep>; - pinctrl-names = "default", "sleep"; - reg = <0x16280000 0x1000>; - interrupts = ; - clocks = <&gcc GSBI3_QUP_CLK>, - <&gcc GSBI3_H_CLK>; - clock-names = "core", "iface"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - gsbi4: gsbi@16300000 { - status = "disabled"; - compatible = "qcom,gsbi-v1.0.0"; - cell-index = <4>; - reg = <0x16300000 0x03>; - clocks = <&gcc GSBI4_H_CLK>; - clock-names = "iface"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gsbi4_i2c: i2c@16380000 { - compatible = "qcom,i2c-qup-v1.1.1"; - pinctrl-0 = <&i2c4_pins>; - pinctrl-1 = <&i2c4_pins_sleep>; - pinctrl-names = "default", "sleep"; - reg = <0x16380000 0x1000>; - interrupts = ; - clocks = <&gcc GSBI4_QUP_CLK>, - <&gcc GSBI4_H_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - }; - - gsbi5: gsbi@1a200000 { - status = "disabled"; - compatible = "qcom,gsbi-v1.0.0"; - cell-index = <5>; - reg = <0x1a200000 0x03>; - clocks = <&gcc GSBI5_H_CLK>; - clock-names = "iface"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gsbi5_serial: serial@1a240000 { - compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; - reg = <0x1a240000 0x100>, - <0x1a200000 0x03>; - interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - - gsbi5_spi: spi@1a280000 { - compatible = "qcom,spi-qup-v1.1.1"; - reg = <0x1a280000 0x1000>; - interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>; - pinctrl-0 = <&spi5_default>; - pinctrl-1 = <&spi5_sleep>; - pinctrl-names = "default", "sleep"; - clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - gsbi6: gsbi@16500000 { - status = "disabled"; - compatible = "qcom,gsbi-v1.0.0"; - cell-index = <6>; - reg = <0x16500000 0x03>; - clocks = <&gcc GSBI6_H_CLK>; - clock-names = "iface"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gsbi6_serial: serial@16540000 { - compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; - reg = <0x16540000 0x100>, - <0x16500000 0x03>; - interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - - gsbi6_i2c: i2c@16580000 { - compatible = "qcom,i2c-qup-v1.1.1"; - pinctrl-0 = <&i2c6_pins>; - pinctrl-1 = <&i2c6_pins_sleep>; - pinctrl-names = "default", "sleep"; - reg = <0x16580000 0x1000>; - interrupts = ; - clocks = <&gcc GSBI6_QUP_CLK>, - <&gcc GSBI6_H_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - }; - - gsbi7: gsbi@16600000 { - status = "disabled"; - compatible = "qcom,gsbi-v1.0.0"; - cell-index = <7>; - reg = <0x16600000 0x100>; - clocks = <&gcc GSBI7_H_CLK>; - clock-names = "iface"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - syscon-tcsr = <&tcsr>; - - gsbi7_serial: serial@16640000 { - compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; - reg = <0x16640000 0x1000>, - <0x16600000 0x1000>; - interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - - gsbi7_i2c: i2c@16680000 { - compatible = "qcom,i2c-qup-v1.1.1"; - pinctrl-0 = <&i2c7_pins>; - pinctrl-1 = <&i2c7_pins_sleep>; - pinctrl-names = "default", "sleep"; - reg = <0x16680000 0x1000>; - interrupts = ; - clocks = <&gcc GSBI7_QUP_CLK>, - <&gcc GSBI7_H_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - }; - - rng@1a500000 { - compatible = "qcom,prng"; - reg = <0x1a500000 0x200>; - clocks = <&gcc PRNG_CLK>; - clock-names = "core"; - }; - - ssbi@c00000 { - compatible = "qcom,ssbi"; - reg = <0x00c00000 0x1000>; - qcom,controller-type = "pmic-arbiter"; - - pm8821: pmic@1 { - compatible = "qcom,pm8821"; - interrupt-parent = <&tlmm_pinmux>; - interrupts = <76 IRQ_TYPE_LEVEL_LOW>; - #interrupt-cells = <2>; - interrupt-controller; - #address-cells = <1>; - #size-cells = <0>; - - pm8821_mpps: mpps@50 { - compatible = "qcom,pm8821-mpp", "qcom,ssbi-mpp"; - reg = <0x50>; - interrupts = <24 IRQ_TYPE_NONE>, - <25 IRQ_TYPE_NONE>, - <26 IRQ_TYPE_NONE>, - <27 IRQ_TYPE_NONE>; - gpio-controller; - #gpio-cells = <2>; - }; - }; - }; - - qcom,ssbi@500000 { - compatible = "qcom,ssbi"; - reg = <0x00500000 0x1000>; - qcom,controller-type = "pmic-arbiter"; - - pmicintc: pmic@0 { - compatible = "qcom,pm8921"; - interrupt-parent = <&tlmm_pinmux>; - interrupts = <74 8>; - #interrupt-cells = <2>; - interrupt-controller; - #address-cells = <1>; - #size-cells = <0>; - - pm8921_gpio: gpio@150 { - - compatible = "qcom,pm8921-gpio", - "qcom,ssbi-gpio"; - reg = <0x150>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - gpio-ranges = <&pm8921_gpio 0 0 44>; - #gpio-cells = <2>; - - }; - - pm8921_mpps: mpps@50 { - compatible = "qcom,pm8921-mpp", - "qcom,ssbi-mpp"; - reg = <0x50>; - gpio-controller; - #gpio-cells = <2>; - interrupts = - <128 IRQ_TYPE_NONE>, - <129 IRQ_TYPE_NONE>, - <130 IRQ_TYPE_NONE>, - <131 IRQ_TYPE_NONE>, - <132 IRQ_TYPE_NONE>, - <133 IRQ_TYPE_NONE>, - <134 IRQ_TYPE_NONE>, - <135 IRQ_TYPE_NONE>, - <136 IRQ_TYPE_NONE>, - <137 IRQ_TYPE_NONE>, - <138 IRQ_TYPE_NONE>, - <139 IRQ_TYPE_NONE>; - }; - - rtc@11d { - compatible = "qcom,pm8921-rtc"; - interrupt-parent = <&pmicintc>; - interrupts = <39 1>; - reg = <0x11d>; - allow-set-time; - }; - - pwrkey@1c { - compatible = "qcom,pm8921-pwrkey"; - reg = <0x1c>; - interrupt-parent = <&pmicintc>; - interrupts = <50 1>, <51 1>; - debounce = <15625>; - pull-up; - }; - - xoadc: xoadc@197 { - compatible = "qcom,pm8921-adc"; - reg = <197>; - interrupts-extended = <&pmicintc 78 IRQ_TYPE_EDGE_RISING>; - #address-cells = <2>; - #size-cells = <0>; - #io-channel-cells = <2>; - - vcoin: adc-channel@00 { - reg = <0x00 0x00>; - }; - vbat: adc-channel@01 { - reg = <0x00 0x01>; - }; - dcin: adc-channel@02 { - reg = <0x00 0x02>; - }; - vph_pwr: adc-channel@04 { - reg = <0x00 0x04>; - }; - batt_therm: adc-channel@08 { - reg = <0x00 0x08>; - }; - batt_id: adc-channel@09 { - reg = <0x00 0x09>; - }; - usb_vbus: adc-channel@0a { - reg = <0x00 0x0a>; - }; - die_temp: adc-channel@0b { - reg = <0x00 0x0b>; - }; - ref_625mv: adc-channel@0c { - reg = <0x00 0x0c>; - }; - ref_1250mv: adc-channel@0d { - reg = <0x00 0x0d>; - }; - chg_temp: adc-channel@0e { - reg = <0x00 0x0e>; - }; - ref_muxoff: adc-channel@0f { - reg = <0x00 0x0f>; - }; - }; - }; - }; - - qfprom: qfprom@700000 { - compatible = "qcom,qfprom"; - reg = <0x00700000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - tsens_calib: calib { - reg = <0x404 0x10>; - }; - tsens_backup: backup_calib { - reg = <0x414 0x10>; - }; - }; - - gcc: clock-controller@900000 { - compatible = "qcom,gcc-apq8064"; - reg = <0x00900000 0x4000>; - nvmem-cells = <&tsens_calib>, <&tsens_backup>; - nvmem-cell-names = "calib", "calib_backup"; - #clock-cells = <1>; - #reset-cells = <1>; - #thermal-sensor-cells = <1>; - }; - - lcc: clock-controller@28000000 { - compatible = "qcom,lcc-apq8064"; - reg = <0x28000000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - mmcc: clock-controller@4000000 { - compatible = "qcom,mmcc-apq8064"; - reg = <0x4000000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - l2cc: clock-controller@2011000 { - compatible = "syscon"; - reg = <0x2011000 0x1000>; - }; - - rpm@108000 { - compatible = "qcom,rpm-apq8064"; - reg = <0x108000 0x1000>; - qcom,ipc = <&l2cc 0x8 2>; - - interrupts = , - , - ; - interrupt-names = "ack", "err", "wakeup"; - - rpmcc: clock-controller { - compatible = "qcom,rpmcc-apq8064", "qcom,rpmcc"; - #clock-cells = <1>; - }; - - regulators { - compatible = "qcom,rpm-pm8921-regulators"; - - pm8921_s1: s1 {}; - pm8921_s2: s2 {}; - pm8921_s3: s3 {}; - pm8921_s4: s4 {}; - pm8921_s7: s7 {}; - pm8921_s8: s8 {}; - - pm8921_l1: l1 {}; - pm8921_l2: l2 {}; - pm8921_l3: l3 {}; - pm8921_l4: l4 {}; - pm8921_l5: l5 {}; - pm8921_l6: l6 {}; - pm8921_l7: l7 {}; - pm8921_l8: l8 {}; - pm8921_l9: l9 {}; - pm8921_l10: l10 {}; - pm8921_l11: l11 {}; - pm8921_l12: l12 {}; - pm8921_l14: l14 {}; - pm8921_l15: l15 {}; - pm8921_l16: l16 {}; - pm8921_l17: l17 {}; - pm8921_l18: l18 {}; - pm8921_l21: l21 {}; - pm8921_l22: l22 {}; - pm8921_l23: l23 {}; - pm8921_l24: l24 {}; - pm8921_l25: l25 {}; - pm8921_l26: l26 {}; - pm8921_l27: l27 {}; - pm8921_l28: l28 {}; - pm8921_l29: l29 {}; - - pm8921_lvs1: lvs1 {}; - pm8921_lvs2: lvs2 {}; - pm8921_lvs3: lvs3 {}; - pm8921_lvs4: lvs4 {}; - pm8921_lvs5: lvs5 {}; - pm8921_lvs6: lvs6 {}; - pm8921_lvs7: lvs7 {}; - - pm8921_usb_switch: usb-switch {}; - - pm8921_hdmi_switch: hdmi-switch { - bias-pull-down; - }; - - pm8921_ncp: ncp {}; - }; - }; - - usb1: usb@12500000 { - compatible = "qcom,ci-hdrc"; - reg = <0x12500000 0x200>, - <0x12500200 0x200>; - interrupts = ; - clocks = <&gcc USB_HS1_XCVR_CLK>, <&gcc USB_HS1_H_CLK>; - clock-names = "core", "iface"; - assigned-clocks = <&gcc USB_HS1_XCVR_CLK>; - assigned-clock-rates = <60000000>; - resets = <&gcc USB_HS1_RESET>; - reset-names = "core"; - phy_type = "ulpi"; - ahb-burst-config = <0>; - phys = <&usb_hs1_phy>; - phy-names = "usb-phy"; - status = "disabled"; - #reset-cells = <1>; - - ulpi { - usb_hs1_phy: phy { - compatible = "qcom,usb-hs-phy-apq8064", - "qcom,usb-hs-phy"; - clocks = <&sleep_clk>, <&cxo_board>; - clock-names = "sleep", "ref"; - resets = <&usb1 0>; - reset-names = "por"; - #phy-cells = <0>; - }; - }; - }; - - usb3: usb@12520000 { - compatible = "qcom,ci-hdrc"; - reg = <0x12520000 0x200>, - <0x12520200 0x200>; - interrupts = ; - clocks = <&gcc USB_HS3_XCVR_CLK>, <&gcc USB_HS3_H_CLK>; - clock-names = "core", "iface"; - assigned-clocks = <&gcc USB_HS3_XCVR_CLK>; - assigned-clock-rates = <60000000>; - resets = <&gcc USB_HS3_RESET>; - reset-names = "core"; - phy_type = "ulpi"; - ahb-burst-config = <0>; - phys = <&usb_hs3_phy>; - phy-names = "usb-phy"; - status = "disabled"; - #reset-cells = <1>; - - ulpi { - usb_hs3_phy: phy { - compatible = "qcom,usb-hs-phy-apq8064", - "qcom,usb-hs-phy"; - #phy-cells = <0>; - clocks = <&sleep_clk>, <&cxo_board>; - clock-names = "sleep", "ref"; - resets = <&usb3 0>; - reset-names = "por"; - }; - }; - }; - - usb4: usb@12530000 { - compatible = "qcom,ci-hdrc"; - reg = <0x12530000 0x200>, - <0x12530200 0x200>; - interrupts = ; - clocks = <&gcc USB_HS4_XCVR_CLK>, <&gcc USB_HS4_H_CLK>; - clock-names = "core", "iface"; - assigned-clocks = <&gcc USB_HS4_XCVR_CLK>; - assigned-clock-rates = <60000000>; - resets = <&gcc USB_HS4_RESET>; - reset-names = "core"; - phy_type = "ulpi"; - ahb-burst-config = <0>; - phys = <&usb_hs4_phy>; - phy-names = "usb-phy"; - status = "disabled"; - #reset-cells = <1>; - - ulpi { - usb_hs4_phy: phy { - compatible = "qcom,usb-hs-phy-apq8064", - "qcom,usb-hs-phy"; - #phy-cells = <0>; - clocks = <&sleep_clk>, <&cxo_board>; - clock-names = "sleep", "ref"; - resets = <&usb4 0>; - reset-names = "por"; - }; - }; - }; - - sata_phy0: phy@1b400000 { - compatible = "qcom,apq8064-sata-phy"; - status = "disabled"; - reg = <0x1b400000 0x200>; - reg-names = "phy_mem"; - clocks = <&gcc SATA_PHY_CFG_CLK>; - clock-names = "cfg"; - #phy-cells = <0>; - }; - - sata0: sata@29000000 { - compatible = "qcom,apq8064-ahci", "generic-ahci"; - status = "disabled"; - reg = <0x29000000 0x180>; - interrupts = ; - - clocks = <&gcc SFAB_SATA_S_H_CLK>, - <&gcc SATA_H_CLK>, - <&gcc SATA_A_CLK>, - <&gcc SATA_RXOOB_CLK>, - <&gcc SATA_PMALIVE_CLK>; - clock-names = "slave_iface", - "iface", - "bus", - "rxoob", - "core_pmalive"; - - assigned-clocks = <&gcc SATA_RXOOB_CLK>, - <&gcc SATA_PMALIVE_CLK>; - assigned-clock-rates = <100000000>, <100000000>; - - phys = <&sata_phy0>; - phy-names = "sata-phy"; - ports-implemented = <0x1>; - }; - - /* Temporary fixed regulator */ - sdcc1bam:dma@12402000{ - compatible = "qcom,bam-v1.3.0"; - reg = <0x12402000 0x8000>; - interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc SDC1_H_CLK>; - clock-names = "bam_clk"; - #dma-cells = <1>; - qcom,ee = <0>; - }; - - sdcc3bam:dma@12182000{ - compatible = "qcom,bam-v1.3.0"; - reg = <0x12182000 0x8000>; - interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc SDC3_H_CLK>; - clock-names = "bam_clk"; - #dma-cells = <1>; - qcom,ee = <0>; - }; - - sdcc4bam:dma@121c2000{ - compatible = "qcom,bam-v1.3.0"; - reg = <0x121c2000 0x8000>; - interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc SDC4_H_CLK>; - clock-names = "bam_clk"; - #dma-cells = <1>; - qcom,ee = <0>; - }; - - amba { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - sdcc1: sdcc@12400000 { - status = "disabled"; - compatible = "arm,pl18x", "arm,primecell"; - pinctrl-names = "default"; - pinctrl-0 = <&sdcc1_pins>; - arm,primecell-periphid = <0x00051180>; - reg = <0x12400000 0x2000>; - interrupts = ; - interrupt-names = "cmd_irq"; - clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <8>; - max-frequency = <96000000>; - non-removable; - cap-sd-highspeed; - cap-mmc-highspeed; - dmas = <&sdcc1bam 2>, <&sdcc1bam 1>; - dma-names = "tx", "rx"; - }; - - sdcc3: sdcc@12180000 { - compatible = "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x00051180>; - status = "disabled"; - reg = <0x12180000 0x2000>; - interrupts = ; - interrupt-names = "cmd_irq"; - clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <4>; - cap-sd-highspeed; - cap-mmc-highspeed; - max-frequency = <192000000>; - no-1-8-v; - dmas = <&sdcc3bam 2>, <&sdcc3bam 1>; - dma-names = "tx", "rx"; - }; - - sdcc4: sdcc@121c0000 { - compatible = "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x00051180>; - status = "disabled"; - reg = <0x121c0000 0x2000>; - interrupts = ; - interrupt-names = "cmd_irq"; - clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <4>; - cap-sd-highspeed; - cap-mmc-highspeed; - max-frequency = <48000000>; - dmas = <&sdcc4bam 2>, <&sdcc4bam 1>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&sdc4_gpios>; - }; - }; - - tcsr: syscon@1a400000 { - compatible = "qcom,tcsr-apq8064", "syscon"; - reg = <0x1a400000 0x100>; - }; - - gpu: adreno-3xx@4300000 { - compatible = "qcom,adreno-3xx"; - reg = <0x04300000 0x20000>; - reg-names = "kgsl_3d0_reg_memory"; - interrupts = ; - interrupt-names = "kgsl_3d0_irq"; - clock-names = - "core_clk", - "iface_clk", - "mem_clk", - "mem_iface_clk"; - clocks = - <&mmcc GFX3D_CLK>, - <&mmcc GFX3D_AHB_CLK>, - <&mmcc GFX3D_AXI_CLK>, - <&mmcc MMSS_IMEM_AHB_CLK>; - qcom,chipid = <0x03020002>; - - iommus = <&gfx3d 0 - &gfx3d 1 - &gfx3d 2 - &gfx3d 3 - &gfx3d 4 - &gfx3d 5 - &gfx3d 6 - &gfx3d 7 - &gfx3d 8 - &gfx3d 9 - &gfx3d 10 - &gfx3d 11 - &gfx3d 12 - &gfx3d 13 - &gfx3d 14 - &gfx3d 15 - &gfx3d 16 - &gfx3d 17 - &gfx3d 18 - &gfx3d 19 - &gfx3d 20 - &gfx3d 21 - &gfx3d 22 - &gfx3d 23 - &gfx3d 24 - &gfx3d 25 - &gfx3d 26 - &gfx3d 27 - &gfx3d 28 - &gfx3d 29 - &gfx3d 30 - &gfx3d 31 - &gfx3d1 0 - &gfx3d1 1 - &gfx3d1 2 - &gfx3d1 3 - &gfx3d1 4 - &gfx3d1 5 - &gfx3d1 6 - &gfx3d1 7 - &gfx3d1 8 - &gfx3d1 9 - &gfx3d1 10 - &gfx3d1 11 - &gfx3d1 12 - &gfx3d1 13 - &gfx3d1 14 - &gfx3d1 15 - &gfx3d1 16 - &gfx3d1 17 - &gfx3d1 18 - &gfx3d1 19 - &gfx3d1 20 - &gfx3d1 21 - &gfx3d1 22 - &gfx3d1 23 - &gfx3d1 24 - &gfx3d1 25 - &gfx3d1 26 - &gfx3d1 27 - &gfx3d1 28 - &gfx3d1 29 - &gfx3d1 30 - &gfx3d1 31>; - - qcom,gpu-pwrlevels { - compatible = "qcom,gpu-pwrlevels"; - qcom,gpu-pwrlevel@0 { - qcom,gpu-freq = <450000000>; - }; - qcom,gpu-pwrlevel@1 { - qcom,gpu-freq = <27000000>; - }; - }; - }; - - mmss_sfpb: syscon@5700000 { - compatible = "syscon"; - reg = <0x5700000 0x70>; - }; - - dsi0: mdss_dsi@4700000 { - compatible = "qcom,mdss-dsi-ctrl"; - label = "MDSS DSI CTRL->0"; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - reg = <0x04700000 0x200>; - reg-names = "dsi_ctrl"; - - clocks = <&mmcc DSI_M_AHB_CLK>, - <&mmcc DSI_S_AHB_CLK>, - <&mmcc AMP_AHB_CLK>, - <&mmcc DSI_CLK>, - <&mmcc DSI1_BYTE_CLK>, - <&mmcc DSI_PIXEL_CLK>, - <&mmcc DSI1_ESC_CLK>; - clock-names = "iface_clk", "bus_clk", "core_mmss_clk", - "src_clk", "byte_clk", "pixel_clk", - "core_clk"; - - assigned-clocks = <&mmcc DSI1_BYTE_SRC>, - <&mmcc DSI1_ESC_SRC>, - <&mmcc DSI_SRC>, - <&mmcc DSI_PIXEL_SRC>; - assigned-clock-parents = <&dsi0_phy 0>, - <&dsi0_phy 0>, - <&dsi0_phy 1>, - <&dsi0_phy 1>; - syscon-sfpb = <&mmss_sfpb>; - phys = <&dsi0_phy>; - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dsi0_in: endpoint { - }; - }; - - port@1 { - reg = <1>; - dsi0_out: endpoint { - }; - }; - }; - }; - - - dsi0_phy: dsi-phy@4700200 { - compatible = "qcom,dsi-phy-28nm-8960"; - #clock-cells = <1>; - #phy-cells = <0>; - - reg = <0x04700200 0x100>, - <0x04700300 0x200>, - <0x04700500 0x5c>; - reg-names = "dsi_pll", "dsi_phy", "dsi_phy_regulator"; - clock-names = "iface_clk", "ref"; - clocks = <&mmcc DSI_M_AHB_CLK>, - <&cxo_board>; - }; - - - mdp_port0: iommu@7500000 { - compatible = "qcom,apq8064-iommu"; - #iommu-cells = <1>; - clock-names = - "smmu_pclk", - "iommu_clk"; - clocks = - <&mmcc SMMU_AHB_CLK>, - <&mmcc MDP_AXI_CLK>; - reg = <0x07500000 0x100000>; - interrupts = - , - ; - qcom,ncb = <2>; - }; - - mdp_port1: iommu@7600000 { - compatible = "qcom,apq8064-iommu"; - #iommu-cells = <1>; - clock-names = - "smmu_pclk", - "iommu_clk"; - clocks = - <&mmcc SMMU_AHB_CLK>, - <&mmcc MDP_AXI_CLK>; - reg = <0x07600000 0x100000>; - interrupts = - , - ; - qcom,ncb = <2>; - }; - - gfx3d: iommu@7c00000 { - compatible = "qcom,apq8064-iommu"; - #iommu-cells = <1>; - clock-names = - "smmu_pclk", - "iommu_clk"; - clocks = - <&mmcc SMMU_AHB_CLK>, - <&mmcc GFX3D_AXI_CLK>; - reg = <0x07c00000 0x100000>; - interrupts = - , - ; - qcom,ncb = <3>; - }; - - gfx3d1: iommu@7d00000 { - compatible = "qcom,apq8064-iommu"; - #iommu-cells = <1>; - clock-names = - "smmu_pclk", - "iommu_clk"; - clocks = - <&mmcc SMMU_AHB_CLK>, - <&mmcc GFX3D_AXI_CLK>; - reg = <0x07d00000 0x100000>; - interrupts = - , - ; - qcom,ncb = <3>; - }; - - pcie: pci@1b500000 { - compatible = "qcom,pcie-apq8064", "snps,dw-pcie"; - reg = <0x1b500000 0x1000 - 0x1b502000 0x80 - 0x1b600000 0x100 - 0x0ff00000 0x100000>; - reg-names = "dbi", "elbi", "parf", "config"; - device_type = "pci"; - linux,pci-domain = <0>; - bus-range = <0x00 0xff>; - num-lanes = <1>; - #address-cells = <3>; - #size-cells = <2>; - ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000 /* I/O */ - 0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* memory */ - interrupts = ; - interrupt-names = "msi"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ - clocks = <&gcc PCIE_A_CLK>, - <&gcc PCIE_H_CLK>, - <&gcc PCIE_PHY_REF_CLK>; - clock-names = "core", "iface", "phy"; - resets = <&gcc PCIE_ACLK_RESET>, - <&gcc PCIE_HCLK_RESET>, - <&gcc PCIE_POR_RESET>, - <&gcc PCIE_PCI_RESET>, - <&gcc PCIE_PHY_RESET>; - reset-names = "axi", "ahb", "por", "pci", "phy"; - status = "disabled"; - }; - - hdmi: hdmi-tx@4a00000 { - compatible = "qcom,hdmi-tx-8960"; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_pinctrl>; - reg = <0x04a00000 0x2f0>; - reg-names = "core_physical"; - interrupts = ; - clocks = <&mmcc HDMI_APP_CLK>, - <&mmcc HDMI_M_AHB_CLK>, - <&mmcc HDMI_S_AHB_CLK>; - clock-names = "core_clk", - "master_iface_clk", - "slave_iface_clk"; - - phys = <&hdmi_phy>; - phy-names = "hdmi-phy"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - hdmi_in: endpoint { - }; - }; - - port@1 { - reg = <1>; - hdmi_out: endpoint { - }; - }; - }; - }; - - hdmi_phy: hdmi-phy@4a00400 { - compatible = "qcom,hdmi-phy-8960"; - reg = <0x4a00400 0x60>, - <0x4a00500 0x100>; - reg-names = "hdmi_phy", - "hdmi_pll"; - - clocks = <&mmcc HDMI_S_AHB_CLK>; - clock-names = "slave_iface_clk"; - #phy-cells = <0>; - }; - - mdp: mdp@5100000 { - compatible = "qcom,mdp4"; - reg = <0x05100000 0xf0000>; - interrupts = ; - clocks = <&mmcc MDP_CLK>, - <&mmcc MDP_AHB_CLK>, - <&mmcc MDP_AXI_CLK>, - <&mmcc MDP_LUT_CLK>, - <&mmcc HDMI_TV_CLK>, - <&mmcc MDP_TV_CLK>; - clock-names = "core_clk", - "iface_clk", - "bus_clk", - "lut_clk", - "hdmi_clk", - "tv_clk"; - - iommus = <&mdp_port0 0 - &mdp_port0 2 - &mdp_port1 0 - &mdp_port1 2>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - mdp_lvds_out: endpoint { - }; - }; - - port@1 { - reg = <1>; - mdp_dsi1_out: endpoint { - }; - }; - - port@2 { - reg = <2>; - mdp_dsi2_out: endpoint { - }; - }; - - port@3 { - reg = <3>; - mdp_dtv_out: endpoint { - }; - }; - }; - }; - - riva: riva-pil@3204000 { - compatible = "qcom,riva-pil"; - - reg = <0x03200800 0x1000>, <0x03202000 0x2000>, <0x03204000 0x100>; - reg-names = "ccu", "dxe", "pmu"; - - interrupts-extended = <&intc GIC_SPI 199 IRQ_TYPE_EDGE_RISING>, - <&wcnss_smsm 6 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal"; - - memory-region = <&wcnss_mem>; - - vddcx-supply = <&pm8921_s3>; - vddmx-supply = <&pm8921_l24>; - vddpx-supply = <&pm8921_s4>; - - status = "disabled"; - - iris { - compatible = "qcom,wcn3660"; - - clocks = <&cxo_board>; - clock-names = "xo"; - - vddxo-supply = <&pm8921_l4>; - vddrfa-supply = <&pm8921_s2>; - vddpa-supply = <&pm8921_l10>; - vdddig-supply = <&pm8921_lvs2>; - }; - - smd-edge { - interrupts = ; - - qcom,ipc = <&l2cc 8 25>; - qcom,smd-edge = <6>; - - label = "riva"; - - wcnss { - compatible = "qcom,wcnss"; - qcom,smd-channels = "WCNSS_CTRL"; - - qcom,mmio = <&riva>; - - bt { - compatible = "qcom,wcnss-bt"; - }; - - wifi { - compatible = "qcom,wcnss-wlan"; - - interrupts = , - ; - interrupt-names = "tx", "rx"; - - qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>; - qcom,smem-state-names = "tx-enable", "tx-rings-empty"; - }; - }; - }; - }; - - etb@1a01000 { - compatible = "coresight-etb10", "arm,primecell"; - reg = <0x1a01000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>; - clock-names = "apb_pclk"; - - in-ports { - port { - etb_in: endpoint { - remote-endpoint = <&replicator_out0>; - }; - }; - }; - }; - - tpiu@1a03000 { - compatible = "arm,coresight-tpiu", "arm,primecell"; - reg = <0x1a03000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>; - clock-names = "apb_pclk"; - - in-ports { - port { - tpiu_in: endpoint { - remote-endpoint = <&replicator_out1>; - }; - }; - }; - }; - - replicator { - compatible = "arm,coresight-static-replicator"; - - clocks = <&rpmcc RPM_QDSS_CLK>; - clock-names = "apb_pclk"; - - out-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - replicator_out0: endpoint { - remote-endpoint = <&etb_in>; - }; - }; - port@1 { - reg = <1>; - replicator_out1: endpoint { - remote-endpoint = <&tpiu_in>; - }; - }; - }; - - in-ports { - port { - replicator_in: endpoint { - remote-endpoint = <&funnel_out>; - }; - }; - }; - }; - - funnel@1a04000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0x1a04000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>; - clock-names = "apb_pclk"; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - /* - * Not described input ports: - * 2 - connected to STM component - * 3 - not-connected - * 6 - not-connected - * 7 - not-connected - */ - port@0 { - reg = <0>; - funnel_in0: endpoint { - remote-endpoint = <&etm0_out>; - }; - }; - port@1 { - reg = <1>; - funnel_in1: endpoint { - remote-endpoint = <&etm1_out>; - }; - }; - port@4 { - reg = <4>; - funnel_in4: endpoint { - remote-endpoint = <&etm2_out>; - }; - }; - port@5 { - reg = <5>; - funnel_in5: endpoint { - remote-endpoint = <&etm3_out>; - }; - }; - }; - - out-ports { - port { - funnel_out: endpoint { - remote-endpoint = <&replicator_in>; - }; - }; - }; - }; - - etm@1a1c000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0x1a1c000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>; - clock-names = "apb_pclk"; - - cpu = <&CPU0>; - - out-ports { - port { - etm0_out: endpoint { - remote-endpoint = <&funnel_in0>; - }; - }; - }; - }; - - etm@1a1d000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0x1a1d000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>; - clock-names = "apb_pclk"; - - cpu = <&CPU1>; - - out-ports { - port { - etm1_out: endpoint { - remote-endpoint = <&funnel_in1>; - }; - }; - }; - }; - - etm@1a1e000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0x1a1e000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>; - clock-names = "apb_pclk"; - - cpu = <&CPU2>; - - out-ports { - port { - etm2_out: endpoint { - remote-endpoint = <&funnel_in4>; - }; - }; - }; - }; - - etm@1a1f000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0x1a1f000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>; - clock-names = "apb_pclk"; - - cpu = <&CPU3>; - - out-ports { - port { - etm3_out: endpoint { - remote-endpoint = <&funnel_in5>; - }; - }; - }; - }; - }; -}; -#include "qcom-apq8064-pins.dtsi" diff --git a/sys/gnu/dts/arm/qcom-apq8074-dragonboard.dts b/sys/gnu/dts/arm/qcom-apq8074-dragonboard.dts deleted file mode 100644 index 244f04e19c9..00000000000 --- a/sys/gnu/dts/arm/qcom-apq8074-dragonboard.dts +++ /dev/null @@ -1,346 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "qcom-msm8974.dtsi" -#include "qcom-pm8841.dtsi" -#include "qcom-pm8941.dtsi" - -/ { - model = "Qualcomm APQ8074 Dragonboard"; - compatible = "qcom,apq8074-dragonboard", "qcom,apq8074"; - - aliases { - serial0 = &blsp1_uart2; - usid0 = &pm8941_0; - usid4 = &pm8841_0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - soc { - serial@f991e000 { - status = "ok"; - }; - - sdhci@f9824900 { - bus-width = <8>; - non-removable; - status = "ok"; - - vmmc-supply = <&pm8941_l20>; - vqmmc-supply = <&pm8941_s3>; - - pinctrl-names = "default"; - pinctrl-0 = <&sdhc1_pin_a>; - }; - - sdhci@f98a4900 { - cd-gpios = <&msmgpio 62 0x1>; - pinctrl-names = "default"; - pinctrl-0 = <&sdhc2_pin_a>, <&sdhc2_cd_pin_a>; - bus-width = <4>; - status = "ok"; - - vmmc-supply = <&pm8941_l21>; - vqmmc-supply = <&pm8941_l13>; - }; - - usb@f9a55000 { - status = "ok"; - phys = <&usb_hs2_phy>; - phy-select = <&tcsr 0xb000 1>; - extcon = <&smbb>, <&usb_id>; - vbus-supply = <&chg_otg>; - hnp-disable; - srp-disable; - adp-disable; - ulpi { - phy@b { - status = "ok"; - v3p3-supply = <&pm8941_l24>; - v1p8-supply = <&pm8941_l6>; - extcon = <&smbb>; - qcom,init-seq = /bits/ 8 <0x1 0x63>; - }; - }; - }; - - - pinctrl@fd510000 { - i2c11_pins: i2c11 { - mux { - pins = "gpio83", "gpio84"; - function = "blsp_i2c11"; - }; - }; - - spi8_default: spi8_default { - mosi { - pins = "gpio45"; - function = "blsp_spi8"; - }; - miso { - pins = "gpio46"; - function = "blsp_spi8"; - }; - cs { - pins = "gpio47"; - function = "blsp_spi8"; - }; - clk { - pins = "gpio48"; - function = "blsp_spi8"; - }; - }; - - sdhc1_pin_a: sdhc1-pin-active { - clk { - pins = "sdc1_clk"; - drive-strength = <16>; - bias-disable; - }; - - cmd-data { - pins = "sdc1_cmd", "sdc1_data"; - drive-strength = <10>; - bias-pull-up; - }; - }; - - sdhc2_cd_pin_a: sdhc2-cd-pin-active { - pins = "gpio62"; - function = "gpio"; - - drive-strength = <2>; - bias-disable; - }; - - sdhc2_pin_a: sdhc2-pin-active { - clk { - pins = "sdc2_clk"; - drive-strength = <10>; - bias-disable; - }; - - cmd-data { - pins = "sdc2_cmd", "sdc2_data"; - drive-strength = <6>; - bias-pull-up; - }; - }; - }; - - i2c@f9967000 { - status = "okay"; - clock-frequency = <200000>; - pinctrl-0 = <&i2c11_pins>; - pinctrl-names = "default"; - - eeprom: eeprom@52 { - compatible = "atmel,24c128"; - reg = <0x52>; - pagesize = <32>; - read-only; - }; - }; - }; - - smd { - rpm { - rpm_requests { - pm8841-regulators { - s1 { - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <1050000>; - }; - - s2 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1050000>; - }; - - s3 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1050000>; - }; - - s4 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1050000>; - }; - }; - - pm8941-regulators { - vdd_l1_l3-supply = <&pm8941_s1>; - vdd_l2_lvs1_2_3-supply = <&pm8941_s3>; - vdd_l4_l11-supply = <&pm8941_s1>; - vdd_l5_l7-supply = <&pm8941_s2>; - vdd_l6_l12_l14_l15-supply = <&pm8941_s2>; - vin_5vs-supply = <&pm8941_5v>; - - s1 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - }; - - s2 { - regulator-min-microvolt = <2150000>; - regulator-max-microvolt = <2150000>; - regulator-boot-on; - }; - - s3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - l1 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - - regulator-always-on; - regulator-boot-on; - }; - - l2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - l3 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - - l4 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - - l5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-boot-on; - }; - - l7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-boot-on; - }; - - l8 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l9 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - l10 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - l11 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - }; - - l12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-always-on; - regulator-boot-on; - }; - - l13 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - - regulator-boot-on; - }; - - l14 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l15 { - regulator-min-microvolt = <2050000>; - regulator-max-microvolt = <2050000>; - }; - - l16 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; - - l17 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; - - l18 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - l19 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - l20 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - - regulator-allow-set-load; - regulator-boot-on; - regulator-system-load = <200000>; - }; - - l21 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - - regulator-boot-on; - }; - - l22 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - l23 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - l24 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3075000>; - - regulator-boot-on; - }; - }; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/qcom-apq8084-ifc6540.dts b/sys/gnu/dts/arm/qcom-apq8084-ifc6540.dts deleted file mode 100644 index 44cd72f1b1b..00000000000 --- a/sys/gnu/dts/arm/qcom-apq8084-ifc6540.dts +++ /dev/null @@ -1,34 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "qcom-apq8084.dtsi" -#include "qcom-pma8084.dtsi" - -/ { - model = "Qualcomm APQ8084/IFC6540"; - compatible = "qcom,apq8084-sbc", "qcom,apq8084"; - - aliases { - serial0 = &blsp2_uart2; - usid0 = &pma8084_0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - soc { - serial@f995e000 { - status = "okay"; - }; - - sdhci@f9824900 { - bus-width = <8>; - non-removable; - status = "okay"; - }; - - sdhci@f98a4900 { - cd-gpios = <&tlmm 122 GPIO_ACTIVE_LOW>; - bus-width = <4>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/qcom-apq8084-mtp.dts b/sys/gnu/dts/arm/qcom-apq8084-mtp.dts deleted file mode 100644 index c6b6680248a..00000000000 --- a/sys/gnu/dts/arm/qcom-apq8084-mtp.dts +++ /dev/null @@ -1,23 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "qcom-apq8084.dtsi" -#include "qcom-pma8084.dtsi" - -/ { - model = "Qualcomm APQ 8084-MTP"; - compatible = "qcom,apq8084-mtp", "qcom,apq8084"; - - aliases { - serial0 = &blsp2_uart2; - usid0 = &pma8084_0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - soc { - serial@f995e000 { - status = "okay"; - }; - }; -}; diff --git a/sys/gnu/dts/arm/qcom-apq8084.dtsi b/sys/gnu/dts/arm/qcom-apq8084.dtsi deleted file mode 100644 index fa1852eed37..00000000000 --- a/sys/gnu/dts/arm/qcom-apq8084.dtsi +++ /dev/null @@ -1,530 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - model = "Qualcomm APQ 8084"; - compatible = "qcom,apq8084"; - interrupt-parent = <&intc>; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - smem_mem: smem_region@fa00000 { - reg = <0xfa00000 0x200000>; - no-map; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "qcom,krait"; - reg = <0>; - enable-method = "qcom,kpss-acc-v2"; - next-level-cache = <&L2>; - qcom,acc = <&acc0>; - qcom,saw = <&saw0>; - cpu-idle-states = <&CPU_SPC>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "qcom,krait"; - reg = <1>; - enable-method = "qcom,kpss-acc-v2"; - next-level-cache = <&L2>; - qcom,acc = <&acc1>; - qcom,saw = <&saw1>; - cpu-idle-states = <&CPU_SPC>; - }; - - cpu@2 { - device_type = "cpu"; - compatible = "qcom,krait"; - reg = <2>; - enable-method = "qcom,kpss-acc-v2"; - next-level-cache = <&L2>; - qcom,acc = <&acc2>; - qcom,saw = <&saw2>; - cpu-idle-states = <&CPU_SPC>; - }; - - cpu@3 { - device_type = "cpu"; - compatible = "qcom,krait"; - reg = <3>; - enable-method = "qcom,kpss-acc-v2"; - next-level-cache = <&L2>; - qcom,acc = <&acc3>; - qcom,saw = <&saw3>; - cpu-idle-states = <&CPU_SPC>; - }; - - L2: l2-cache { - compatible = "qcom,arch-cache"; - cache-level = <2>; - qcom,saw = <&saw_l2>; - }; - - idle-states { - CPU_SPC: spc { - compatible = "qcom,idle-state-spc", - "arm,idle-state"; - entry-latency-us = <150>; - exit-latency-us = <200>; - min-residency-us = <2000>; - }; - }; - }; - - memory { - device_type = "memory"; - reg = <0x0 0x0>; - }; - - firmware { - scm { - compatible = "qcom,scm"; - clocks = <&gcc GCC_CE1_CLK> , <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>; - clock-names = "core", "bus", "iface"; - }; - }; - - thermal-zones { - cpu-thermal0 { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 5>; - - trips { - cpu_alert0: trip0 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu_crit0: trip1 { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - cpu-thermal1 { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 6>; - - trips { - cpu_alert1: trip0 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu_crit1: trip1 { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - cpu-thermal2 { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 7>; - - trips { - cpu_alert2: trip0 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu_crit2: trip1 { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - cpu-thermal3 { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 8>; - - trips { - cpu_alert3: trip0 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu_crit3: trip1 { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - }; - - cpu-pmu { - compatible = "qcom,krait-pmu"; - interrupts = ; - }; - - clocks { - xo_board: xo_board { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <19200000>; - }; - - sleep_clk: sleep_clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; - clock-frequency = <19200000>; - }; - - smem { - compatible = "qcom,smem"; - - qcom,rpm-msg-ram = <&rpm_msg_ram>; - memory-region = <&smem_mem>; - - hwlocks = <&tcsr_mutex 3>; - }; - - soc: soc { - #address-cells = <1>; - #size-cells = <1>; - ranges; - compatible = "simple-bus"; - - intc: interrupt-controller@f9000000 { - compatible = "qcom,msm-qgic2"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0xf9000000 0x1000>, - <0xf9002000 0x1000>; - }; - - apcs: syscon@f9011000 { - compatible = "syscon"; - reg = <0xf9011000 0x1000>; - }; - - qfprom: qfprom@fc4bc000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "qcom,qfprom"; - reg = <0xfc4bc000 0x1000>; - tsens_calib: calib@d0 { - reg = <0xd0 0x18>; - }; - tsens_backup: backup@440 { - reg = <0x440 0x10>; - }; - }; - - tsens: thermal-sensor@fc4a8000 { - compatible = "qcom,msm8974-tsens"; - reg = <0xfc4a9000 0x1000>, /* TM */ - <0xfc4a8000 0x1000>; /* SROT */ - nvmem-cells = <&tsens_calib>, <&tsens_backup>; - nvmem-cell-names = "calib", "calib_backup"; - #qcom,sensors = <11>; - #thermal-sensor-cells = <1>; - }; - timer@f9020000 { - #address-cells = <1>; - #size-cells = <1>; - ranges; - compatible = "arm,armv7-timer-mem"; - reg = <0xf9020000 0x1000>; - clock-frequency = <19200000>; - - frame@f9021000 { - frame-number = <0>; - interrupts = , - ; - reg = <0xf9021000 0x1000>, - <0xf9022000 0x1000>; - }; - - frame@f9023000 { - frame-number = <1>; - interrupts = ; - reg = <0xf9023000 0x1000>; - status = "disabled"; - }; - - frame@f9024000 { - frame-number = <2>; - interrupts = ; - reg = <0xf9024000 0x1000>; - status = "disabled"; - }; - - frame@f9025000 { - frame-number = <3>; - interrupts = ; - reg = <0xf9025000 0x1000>; - status = "disabled"; - }; - - frame@f9026000 { - frame-number = <4>; - interrupts = ; - reg = <0xf9026000 0x1000>; - status = "disabled"; - }; - - frame@f9027000 { - frame-number = <5>; - interrupts = ; - reg = <0xf9027000 0x1000>; - status = "disabled"; - }; - - frame@f9028000 { - frame-number = <6>; - interrupts = ; - reg = <0xf9028000 0x1000>; - status = "disabled"; - }; - }; - - saw0: power-controller@f9089000 { - compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2"; - reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>; - }; - - saw1: power-controller@f9099000 { - compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2"; - reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>; - }; - - saw2: power-controller@f90a9000 { - compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2"; - reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>; - }; - - saw3: power-controller@f90b9000 { - compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2"; - reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>; - }; - - saw_l2: power-controller@f9012000 { - compatible = "qcom,saw2"; - reg = <0xf9012000 0x1000>; - regulator; - }; - - acc0: clock-controller@f9088000 { - compatible = "qcom,kpss-acc-v2"; - reg = <0xf9088000 0x1000>, - <0xf9008000 0x1000>; - }; - - acc1: clock-controller@f9098000 { - compatible = "qcom,kpss-acc-v2"; - reg = <0xf9098000 0x1000>, - <0xf9008000 0x1000>; - }; - - acc2: clock-controller@f90a8000 { - compatible = "qcom,kpss-acc-v2"; - reg = <0xf90a8000 0x1000>, - <0xf9008000 0x1000>; - }; - - acc3: clock-controller@f90b8000 { - compatible = "qcom,kpss-acc-v2"; - reg = <0xf90b8000 0x1000>, - <0xf9008000 0x1000>; - }; - - restart@fc4ab000 { - compatible = "qcom,pshold"; - reg = <0xfc4ab000 0x4>; - }; - - gcc: clock-controller@fc400000 { - compatible = "qcom,gcc-apq8084"; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - reg = <0xfc400000 0x4000>; - }; - - tcsr_mutex_regs: syscon@fd484000 { - compatible = "syscon"; - reg = <0xfd484000 0x2000>; - }; - - tcsr_mutex: hwlock { - compatible = "qcom,tcsr-mutex"; - syscon = <&tcsr_mutex_regs 0 0x80>; - #hwlock-cells = <1>; - }; - - rpm_msg_ram: memory@fc428000 { - compatible = "qcom,rpm-msg-ram"; - reg = <0xfc428000 0x4000>; - }; - - tlmm: pinctrl@fd510000 { - compatible = "qcom,apq8084-pinctrl"; - reg = <0xfd510000 0x4000>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = ; - }; - - blsp2_uart2: serial@f995e000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0xf995e000 0x1000>; - interrupts = ; - clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - - sdhci@f9824900 { - compatible = "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4"; - reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; - reg-names = "hc_mem", "core_mem"; - interrupts = , ; - interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC1_APPS_CLK>, - <&gcc GCC_SDCC1_AHB_CLK>, - <&xo_board>; - clock-names = "core", "iface", "xo"; - status = "disabled"; - }; - - sdhci@f98a4900 { - compatible = "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4"; - reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; - reg-names = "hc_mem", "core_mem"; - interrupts = , ; - interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC2_APPS_CLK>, - <&gcc GCC_SDCC2_AHB_CLK>, - <&xo_board>; - clock-names = "core", "iface", "xo"; - status = "disabled"; - }; - - spmi_bus: spmi@fc4cf000 { - compatible = "qcom,spmi-pmic-arb"; - reg-names = "core", "intr", "cnfg"; - reg = <0xfc4cf000 0x1000>, - <0xfc4cb000 0x1000>, - <0xfc4ca000 0x1000>; - interrupt-names = "periph_irq"; - interrupts = ; - qcom,ee = <0>; - qcom,channel = <0>; - #address-cells = <2>; - #size-cells = <0>; - interrupt-controller; - #interrupt-cells = <4>; - }; - }; - - smd { - compatible = "qcom,smd"; - - rpm { - interrupts = ; - qcom,ipc = <&apcs 8 0>; - qcom,smd-edge = <15>; - - rpm_requests { - compatible = "qcom,rpm-apq8084"; - qcom,smd-channels = "rpm_requests"; - - pma8084-regulators { - compatible = "qcom,rpm-pma8084-regulators"; - - pma8084_s1: s1 {}; - pma8084_s2: s2 {}; - pma8084_s3: s3 {}; - pma8084_s4: s4 {}; - pma8084_s5: s5 {}; - pma8084_s6: s6 {}; - pma8084_s7: s7 {}; - pma8084_s8: s8 {}; - pma8084_s9: s9 {}; - pma8084_s10: s10 {}; - pma8084_s11: s11 {}; - pma8084_s12: s12 {}; - - pma8084_l1: l1 {}; - pma8084_l2: l2 {}; - pma8084_l3: l3 {}; - pma8084_l4: l4 {}; - pma8084_l5: l5 {}; - pma8084_l6: l6 {}; - pma8084_l7: l7 {}; - pma8084_l8: l8 {}; - pma8084_l9: l9 {}; - pma8084_l10: l10 {}; - pma8084_l11: l11 {}; - pma8084_l12: l12 {}; - pma8084_l13: l13 {}; - pma8084_l14: l14 {}; - pma8084_l15: l15 {}; - pma8084_l16: l16 {}; - pma8084_l17: l17 {}; - pma8084_l18: l18 {}; - pma8084_l19: l19 {}; - pma8084_l20: l20 {}; - pma8084_l21: l21 {}; - pma8084_l22: l22 {}; - pma8084_l23: l23 {}; - pma8084_l24: l24 {}; - pma8084_l25: l25 {}; - pma8084_l26: l26 {}; - pma8084_l27: l27 {}; - - pma8084_lvs1: lvs1 {}; - pma8084_lvs2: lvs2 {}; - pma8084_lvs3: lvs3 {}; - pma8084_lvs4: lvs4 {}; - - pma8084_5vs1: 5vs1 {}; - }; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/qcom-ipq4019-ap.dk01.1-c1.dts b/sys/gnu/dts/arm/qcom-ipq4019-ap.dk01.1-c1.dts deleted file mode 100644 index 0d92f1bc3a1..00000000000 --- a/sys/gnu/dts/arm/qcom-ipq4019-ap.dk01.1-c1.dts +++ /dev/null @@ -1,22 +0,0 @@ -/* Copyright (c) 2015, The Linux Foundation. All rights reserved. - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - */ - -#include "qcom-ipq4019-ap.dk01.1.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. IPQ40xx/AP-DK01.1-C1"; - -}; diff --git a/sys/gnu/dts/arm/qcom-ipq4019-ap.dk01.1.dtsi b/sys/gnu/dts/arm/qcom-ipq4019-ap.dk01.1.dtsi deleted file mode 100644 index 418f9a02233..00000000000 --- a/sys/gnu/dts/arm/qcom-ipq4019-ap.dk01.1.dtsi +++ /dev/null @@ -1,113 +0,0 @@ -/* Copyright (c) 2015, The Linux Foundation. All rights reserved. - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - */ - -#include "qcom-ipq4019.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK01.1"; - compatible = "qcom,ipq4019"; - - aliases { - serial0 = &blsp1_uart1; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - soc { - rng@22000 { - status = "ok"; - }; - - pinctrl@1000000 { - serial_pins: serial_pinmux { - mux { - pins = "gpio60", "gpio61"; - function = "blsp_uart0"; - bias-disable; - }; - }; - - spi_0_pins: spi_0_pinmux { - pinmux { - function = "blsp_spi0"; - pins = "gpio55", "gpio56", "gpio57"; - }; - pinmux_cs { - function = "gpio"; - pins = "gpio54"; - }; - pinconf { - pins = "gpio55", "gpio56", "gpio57"; - drive-strength = <12>; - bias-disable; - }; - pinconf_cs { - pins = "gpio54"; - drive-strength = <2>; - bias-disable; - output-high; - }; - }; - }; - - blsp_dma: dma@7884000 { - status = "ok"; - }; - - spi@78b5000 { - pinctrl-0 = <&spi_0_pins>; - pinctrl-names = "default"; - status = "ok"; - cs-gpios = <&tlmm 54 0>; - - mx25l25635e@0 { - #address-cells = <1>; - #size-cells = <1>; - reg = <0>; - compatible = "mx25l25635e"; - spi-max-frequency = <24000000>; - }; - }; - - serial@78af000 { - pinctrl-0 = <&serial_pins>; - pinctrl-names = "default"; - status = "ok"; - }; - - cryptobam: dma@8e04000 { - status = "ok"; - }; - - crypto@8e3a000 { - status = "ok"; - }; - - watchdog@b017000 { - status = "ok"; - }; - - wifi@a000000 { - status = "ok"; - }; - - wifi@a800000 { - status = "ok"; - }; - }; -}; diff --git a/sys/gnu/dts/arm/qcom-ipq4019-ap.dk04.1-c1.dts b/sys/gnu/dts/arm/qcom-ipq4019-ap.dk04.1-c1.dts deleted file mode 100644 index 7a96f300bc8..00000000000 --- a/sys/gnu/dts/arm/qcom-ipq4019-ap.dk04.1-c1.dts +++ /dev/null @@ -1,19 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (c) 2018, The Linux Foundation. All rights reserved. - -#include "qcom-ipq4019-ap.dk04.1.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1-C1"; - compatible = "qcom,ipq4019-dk04.1-c1"; - - soc { - dma@7984000 { - status = "ok"; - }; - - qpic-nand@79b0000 { - status = "ok"; - }; - }; -}; diff --git a/sys/gnu/dts/arm/qcom-ipq4019-ap.dk04.1-c3.dts b/sys/gnu/dts/arm/qcom-ipq4019-ap.dk04.1-c3.dts deleted file mode 100644 index 2d1c4c6e42f..00000000000 --- a/sys/gnu/dts/arm/qcom-ipq4019-ap.dk04.1-c3.dts +++ /dev/null @@ -1,9 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (c) 2018, The Linux Foundation. All rights reserved. - -#include "qcom-ipq4019-ap.dk04.1.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1-C3"; - compatible = "qcom,ipq4019-ap-dk04.1-c3"; -}; diff --git a/sys/gnu/dts/arm/qcom-ipq4019-ap.dk04.1.dtsi b/sys/gnu/dts/arm/qcom-ipq4019-ap.dk04.1.dtsi deleted file mode 100644 index 7c1eb1963c6..00000000000 --- a/sys/gnu/dts/arm/qcom-ipq4019-ap.dk04.1.dtsi +++ /dev/null @@ -1,111 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (c) 2018, The Linux Foundation. All rights reserved. - -#include "qcom-ipq4019.dtsi" -#include -#include - -/ { - model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1"; - - aliases { - serial0 = &blsp1_uart1; - serial1 = &blsp1_uart2; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - device_type = "memory"; - reg = <0x80000000 0x10000000>; /* 256MB */ - }; - - soc { - pinctrl@1000000 { - serial_0_pins: serial0-pinmux { - pins = "gpio16", "gpio17"; - function = "blsp_uart0"; - bias-disable; - }; - - serial_1_pins: serial1-pinmux { - pins = "gpio8", "gpio9", - "gpio10", "gpio11"; - function = "blsp_uart1"; - bias-disable; - }; - - spi_0_pins: spi-0-pinmux { - pinmux { - function = "blsp_spi0"; - pins = "gpio13", "gpio14", "gpio15"; - bias-disable; - }; - pinmux_cs { - function = "gpio"; - pins = "gpio12"; - bias-disable; - output-high; - }; - }; - - i2c_0_pins: i2c-0-pinmux { - pins = "gpio20", "gpio21"; - function = "blsp_i2c0"; - bias-disable; - }; - - nand_pins: nand-pins { - pins = "gpio53", "gpio55", "gpio56", - "gpio57", "gpio58", "gpio59", - "gpio60", "gpio62", "gpio63", - "gpio64", "gpio65", "gpio66", - "gpio67", "gpio68", "gpio69"; - function = "qpic"; - }; - }; - - serial@78af000 { - pinctrl-0 = <&serial_0_pins>; - pinctrl-names = "default"; - status = "ok"; - }; - - serial@78b0000 { - pinctrl-0 = <&serial_1_pins>; - pinctrl-names = "default"; - status = "ok"; - }; - - dma@7884000 { - status = "ok"; - }; - - spi@78b5000 { /* BLSP1 QUP1 */ - pinctrl-0 = <&spi_0_pins>; - pinctrl-names = "default"; - status = "ok"; - cs-gpios = <&tlmm 12 0>; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - reg = <0>; - compatible = "n25q128a11"; - spi-max-frequency = <24000000>; - }; - }; - - pci@40000000 { - status = "ok"; - perst-gpio = <&tlmm 38 0x1>; - }; - - qpic-nand@79b0000 { - pinctrl-0 = <&nand_pins>; - pinctrl-names = "default"; - }; - }; -}; diff --git a/sys/gnu/dts/arm/qcom-ipq4019-ap.dk07.1-c1.dts b/sys/gnu/dts/arm/qcom-ipq4019-ap.dk07.1-c1.dts deleted file mode 100644 index 8c7ef6537ae..00000000000 --- a/sys/gnu/dts/arm/qcom-ipq4019-ap.dk07.1-c1.dts +++ /dev/null @@ -1,64 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (c) 2018, The Linux Foundation. All rights reserved. - -#include "qcom-ipq4019-ap.dk07.1.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK07.1-C1"; - compatible = "qcom,ipq4019-ap-dk07.1-c1"; - - soc { - pci@40000000 { - status = "ok"; - perst-gpio = <&tlmm 38 0x1>; - }; - - spi@78b6000 { - status = "ok"; - }; - - pinctrl@1000000 { - serial_1_pins: serial1-pinmux { - pins = "gpio8", "gpio9", - "gpio10", "gpio11"; - function = "blsp_uart1"; - bias-disable; - }; - - spi_0_pins: spi-0-pinmux { - pinmux { - function = "blsp_spi0"; - pins = "gpio13", "gpio14", "gpio15"; - bias-disable; - }; - pinmux_cs { - function = "gpio"; - pins = "gpio12"; - bias-disable; - output-high; - }; - }; - }; - - serial@78b0000 { - pinctrl-0 = <&serial_1_pins>; - pinctrl-names = "default"; - status = "ok"; - }; - - spi@78b5000 { - pinctrl-0 = <&spi_0_pins>; - pinctrl-names = "default"; - status = "ok"; - cs-gpios = <&tlmm 12 0>; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - reg = <0>; - compatible = "n25q128a11"; - spi-max-frequency = <24000000>; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/qcom-ipq4019-ap.dk07.1-c2.dts b/sys/gnu/dts/arm/qcom-ipq4019-ap.dk07.1-c2.dts deleted file mode 100644 index af7a9028d49..00000000000 --- a/sys/gnu/dts/arm/qcom-ipq4019-ap.dk07.1-c2.dts +++ /dev/null @@ -1,25 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (c) 2018, The Linux Foundation. All rights reserved. - -#include "qcom-ipq4019-ap.dk07.1.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK07.1-C2"; - compatible = "qcom,ipq4019-ap-dk07.1-c2"; - - soc { - pinctrl@1000000 { - serial_1_pins: serial1-pinmux { - pins = "gpio8", "gpio9"; - function = "blsp_uart1"; - bias-disable; - }; - }; - - serial@78b0000 { - pinctrl-0 = <&serial_1_pins>; - pinctrl-names = "default"; - status = "ok"; - }; - }; -}; diff --git a/sys/gnu/dts/arm/qcom-ipq4019-ap.dk07.1.dtsi b/sys/gnu/dts/arm/qcom-ipq4019-ap.dk07.1.dtsi deleted file mode 100644 index 9f1a5a66877..00000000000 --- a/sys/gnu/dts/arm/qcom-ipq4019-ap.dk07.1.dtsi +++ /dev/null @@ -1,75 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (c) 2018, The Linux Foundation. All rights reserved. - -#include "qcom-ipq4019.dtsi" -#include -#include - -/ { - model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK07.1"; - - memory { - device_type = "memory"; - reg = <0x80000000 0x20000000>; /* 512MB */ - }; - - aliases { - serial0 = &blsp1_uart1; - serial1 = &blsp1_uart2; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - soc { - pinctrl@1000000 { - serial_0_pins: serial0-pinmux { - pins = "gpio16", "gpio17"; - function = "blsp_uart0"; - bias-disable; - }; - - i2c_0_pins: i2c-0-pinmux { - pins = "gpio20", "gpio21"; - function = "blsp_i2c0"; - bias-disable; - }; - - nand_pins: nand-pins { - pins = "gpio53", "gpio55", "gpio56", - "gpio57", "gpio58", "gpio59", - "gpio60", "gpio62", "gpio63", - "gpio64", "gpio65", "gpio66", - "gpio67", "gpio68", "gpio69"; - function = "qpic"; - }; - }; - - serial@78af000 { - pinctrl-0 = <&serial_0_pins>; - pinctrl-names = "default"; - status = "ok"; - }; - - dma@7884000 { - status = "ok"; - }; - - i2c@78b7000 { /* BLSP1 QUP2 */ - pinctrl-0 = <&i2c_0_pins>; - pinctrl-names = "default"; - status = "ok"; - }; - - dma@7984000 { - status = "ok"; - }; - - qpic-nand@79b0000 { - pinctrl-0 = <&nand_pins>; - pinctrl-names = "default"; - status = "ok"; - }; - }; -}; diff --git a/sys/gnu/dts/arm/qcom-ipq4019.dtsi b/sys/gnu/dts/arm/qcom-ipq4019.dtsi deleted file mode 100644 index 71bb25a8afc..00000000000 --- a/sys/gnu/dts/arm/qcom-ipq4019.dtsi +++ /dev/null @@ -1,579 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2015, The Linux Foundation. All rights reserved. - */ - -/dts-v1/; - -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - - model = "Qualcomm Technologies, Inc. IPQ4019"; - compatible = "qcom,ipq4019"; - interrupt-parent = <&intc>; - - reserved-memory { - #address-cells = <0x1>; - #size-cells = <0x1>; - ranges; - - smem_region: smem@87e00000 { - reg = <0x87e00000 0x080000>; - no-map; - }; - - tz@87e80000 { - reg = <0x87e80000 0x180000>; - no-map; - }; - }; - - aliases { - spi0 = &blsp1_spi1; - spi1 = &blsp1_spi2; - i2c0 = &blsp1_i2c3; - i2c1 = &blsp1_i2c4; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - enable-method = "qcom,kpss-acc-v2"; - next-level-cache = <&L2>; - qcom,acc = <&acc0>; - qcom,saw = <&saw0>; - reg = <0x0>; - clocks = <&gcc GCC_APPS_CLK_SRC>; - clock-frequency = <0>; - clock-latency = <256000>; - operating-points-v2 = <&cpu0_opp_table>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - enable-method = "qcom,kpss-acc-v2"; - next-level-cache = <&L2>; - qcom,acc = <&acc1>; - qcom,saw = <&saw1>; - reg = <0x1>; - clocks = <&gcc GCC_APPS_CLK_SRC>; - clock-frequency = <0>; - clock-latency = <256000>; - operating-points-v2 = <&cpu0_opp_table>; - }; - - cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - enable-method = "qcom,kpss-acc-v2"; - next-level-cache = <&L2>; - qcom,acc = <&acc2>; - qcom,saw = <&saw2>; - reg = <0x2>; - clocks = <&gcc GCC_APPS_CLK_SRC>; - clock-frequency = <0>; - clock-latency = <256000>; - operating-points-v2 = <&cpu0_opp_table>; - }; - - cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - enable-method = "qcom,kpss-acc-v2"; - next-level-cache = <&L2>; - qcom,acc = <&acc3>; - qcom,saw = <&saw3>; - reg = <0x3>; - clocks = <&gcc GCC_APPS_CLK_SRC>; - clock-frequency = <0>; - clock-latency = <256000>; - operating-points-v2 = <&cpu0_opp_table>; - }; - - L2: l2-cache { - compatible = "cache"; - cache-level = <2>; - qcom,saw = <&saw_l2>; - }; - }; - - cpu0_opp_table: opp_table0 { - compatible = "operating-points-v2"; - opp-shared; - - opp-48000000 { - opp-hz = /bits/ 64 <48000000>; - clock-latency-ns = <256000>; - }; - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - clock-latency-ns = <256000>; - }; - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - clock-latency-ns = <256000>; - }; - opp-716000000 { - opp-hz = /bits/ 64 <716000000>; - clock-latency-ns = <256000>; - }; - }; - - memory { - device_type = "memory"; - reg = <0x0 0x0>; - }; - - pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts = ; - }; - - clocks { - sleep_clk: sleep_clk { - compatible = "fixed-clock"; - clock-frequency = <32768>; - #clock-cells = <0>; - }; - - xo: xo { - compatible = "fixed-clock"; - clock-frequency = <48000000>; - #clock-cells = <0>; - }; - }; - - firmware { - scm { - compatible = "qcom,scm-ipq4019"; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = <1 2 0xf08>, - <1 3 0xf08>, - <1 4 0xf08>, - <1 1 0xf08>; - clock-frequency = <48000000>; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - ranges; - compatible = "simple-bus"; - - intc: interrupt-controller@b000000 { - compatible = "qcom,msm-qgic2"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0x0b000000 0x1000>, - <0x0b002000 0x1000>; - }; - - gcc: clock-controller@1800000 { - compatible = "qcom,gcc-ipq4019"; - #clock-cells = <1>; - #reset-cells = <1>; - reg = <0x1800000 0x60000>; - }; - - rng@22000 { - compatible = "qcom,prng"; - reg = <0x22000 0x140>; - clocks = <&gcc GCC_PRNG_AHB_CLK>; - clock-names = "core"; - status = "disabled"; - }; - - tlmm: pinctrl@1000000 { - compatible = "qcom,ipq4019-pinctrl"; - reg = <0x01000000 0x300000>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = ; - }; - - sdhci: sdhci@7824900 { - compatible = "qcom,sdhci-msm-v4"; - reg = <0x7824900 0x11c>, <0x7824000 0x800>; - interrupts = , ; - interrupt-names = "hc_irq", "pwr_irq"; - bus-width = <8>; - clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>, - <&gcc GCC_DCD_XO_CLK>; - clock-names = "core", "iface", "xo"; - status = "disabled"; - }; - - blsp_dma: dma@7884000 { - compatible = "qcom,bam-v1.7.0"; - reg = <0x07884000 0x23000>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "bam_clk"; - #dma-cells = <1>; - qcom,ee = <0>; - status = "disabled"; - }; - - blsp1_spi1: spi@78b5000 { /* BLSP1 QUP1 */ - compatible = "qcom,spi-qup-v2.2.1"; - reg = <0x78b5000 0x600>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - #address-cells = <1>; - #size-cells = <0>; - dmas = <&blsp_dma 5>, <&blsp_dma 4>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - blsp1_spi2: spi@78b6000 { /* BLSP1 QUP2 */ - compatible = "qcom,spi-qup-v2.2.1"; - reg = <0x78b6000 0x600>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - #address-cells = <1>; - #size-cells = <0>; - dmas = <&blsp_dma 7>, <&blsp_dma 6>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - blsp1_i2c3: i2c@78b7000 { /* BLSP1 QUP3 */ - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x78b7000 0x600>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>; - clock-names = "iface", "core"; - #address-cells = <1>; - #size-cells = <0>; - dmas = <&blsp_dma 9>, <&blsp_dma 8>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - blsp1_i2c4: i2c@78b8000 { /* BLSP1 QUP4 */ - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x78b8000 0x600>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; - clock-names = "iface", "core"; - #address-cells = <1>; - #size-cells = <0>; - dmas = <&blsp_dma 11>, <&blsp_dma 10>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - cryptobam: dma@8e04000 { - compatible = "qcom,bam-v1.7.0"; - reg = <0x08e04000 0x20000>; - interrupts = ; - clocks = <&gcc GCC_CRYPTO_AHB_CLK>; - clock-names = "bam_clk"; - #dma-cells = <1>; - qcom,ee = <1>; - qcom,controlled-remotely; - status = "disabled"; - }; - - crypto@8e3a000 { - compatible = "qcom,crypto-v5.1"; - reg = <0x08e3a000 0x6000>; - clocks = <&gcc GCC_CRYPTO_AHB_CLK>, - <&gcc GCC_CRYPTO_AXI_CLK>, - <&gcc GCC_CRYPTO_CLK>; - clock-names = "iface", "bus", "core"; - dmas = <&cryptobam 2>, <&cryptobam 3>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - acc0: clock-controller@b088000 { - compatible = "qcom,kpss-acc-v2"; - reg = <0x0b088000 0x1000>, <0xb008000 0x1000>; - }; - - acc1: clock-controller@b098000 { - compatible = "qcom,kpss-acc-v2"; - reg = <0x0b098000 0x1000>, <0xb008000 0x1000>; - }; - - acc2: clock-controller@b0a8000 { - compatible = "qcom,kpss-acc-v2"; - reg = <0x0b0a8000 0x1000>, <0xb008000 0x1000>; - }; - - acc3: clock-controller@b0b8000 { - compatible = "qcom,kpss-acc-v2"; - reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>; - }; - - saw0: regulator@b089000 { - compatible = "qcom,saw2"; - reg = <0x0b089000 0x1000>, <0x0b009000 0x1000>; - regulator; - }; - - saw1: regulator@b099000 { - compatible = "qcom,saw2"; - reg = <0x0b099000 0x1000>, <0x0b009000 0x1000>; - regulator; - }; - - saw2: regulator@b0a9000 { - compatible = "qcom,saw2"; - reg = <0x0b0a9000 0x1000>, <0x0b009000 0x1000>; - regulator; - }; - - saw3: regulator@b0b9000 { - compatible = "qcom,saw2"; - reg = <0x0b0b9000 0x1000>, <0x0b009000 0x1000>; - regulator; - }; - - saw_l2: regulator@b012000 { - compatible = "qcom,saw2"; - reg = <0xb012000 0x1000>; - regulator; - }; - - blsp1_uart1: serial@78af000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0x78af000 0x200>; - interrupts = ; - status = "disabled"; - clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - dmas = <&blsp_dma 1>, <&blsp_dma 0>; - dma-names = "rx", "tx"; - }; - - blsp1_uart2: serial@78b0000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0x78b0000 0x200>; - interrupts = ; - status = "disabled"; - clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - dmas = <&blsp_dma 3>, <&blsp_dma 2>; - dma-names = "rx", "tx"; - }; - - watchdog@b017000 { - compatible = "qcom,kpss-wdt", "qcom,kpss-wdt-ipq4019"; - reg = <0xb017000 0x40>; - clocks = <&sleep_clk>; - timeout-sec = <10>; - status = "disabled"; - }; - - restart@4ab000 { - compatible = "qcom,pshold"; - reg = <0x4ab000 0x4>; - }; - - pcie0: pci@40000000 { - compatible = "qcom,pcie-ipq4019", "snps,dw-pcie"; - reg = <0x40000000 0xf1d - 0x40000f20 0xa8 - 0x80000 0x2000 - 0x40100000 0x1000>; - reg-names = "dbi", "elbi", "parf", "config"; - device_type = "pci"; - linux,pci-domain = <0>; - bus-range = <0x00 0xff>; - num-lanes = <1>; - #address-cells = <3>; - #size-cells = <2>; - - ranges = <0x81000000 0 0x40200000 0x40200000 0 0x00100000>, - <0x82000000 0 0x40300000 0x40300000 0 0x00d00000>; - - interrupts = ; - interrupt-names = "msi"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ - clocks = <&gcc GCC_PCIE_AHB_CLK>, - <&gcc GCC_PCIE_AXI_M_CLK>, - <&gcc GCC_PCIE_AXI_S_CLK>; - clock-names = "aux", - "master_bus", - "slave_bus"; - - resets = <&gcc PCIE_AXI_M_ARES>, - <&gcc PCIE_AXI_S_ARES>, - <&gcc PCIE_PIPE_ARES>, - <&gcc PCIE_AXI_M_VMIDMT_ARES>, - <&gcc PCIE_AXI_S_XPU_ARES>, - <&gcc PCIE_PARF_XPU_ARES>, - <&gcc PCIE_PHY_ARES>, - <&gcc PCIE_AXI_M_STICKY_ARES>, - <&gcc PCIE_PIPE_STICKY_ARES>, - <&gcc PCIE_PWR_ARES>, - <&gcc PCIE_AHB_ARES>, - <&gcc PCIE_PHY_AHB_ARES>; - reset-names = "axi_m", - "axi_s", - "pipe", - "axi_m_vmid", - "axi_s_xpu", - "parf", - "phy", - "axi_m_sticky", - "pipe_sticky", - "pwr", - "ahb", - "phy_ahb"; - - status = "disabled"; - }; - - qpic_bam: dma@7984000 { - compatible = "qcom,bam-v1.7.0"; - reg = <0x7984000 0x1a000>; - interrupts = ; - clocks = <&gcc GCC_QPIC_CLK>; - clock-names = "bam_clk"; - #dma-cells = <1>; - qcom,ee = <0>; - status = "disabled"; - }; - - nand: qpic-nand@79b0000 { - compatible = "qcom,ipq4019-nand"; - reg = <0x79b0000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&gcc GCC_QPIC_CLK>, - <&gcc GCC_QPIC_AHB_CLK>; - clock-names = "core", "aon"; - - dmas = <&qpic_bam 0>, - <&qpic_bam 1>, - <&qpic_bam 2>; - dma-names = "tx", "rx", "cmd"; - status = "disabled"; - - nand@0 { - reg = <0>; - - nand-ecc-strength = <4>; - nand-ecc-step-size = <512>; - nand-bus-width = <8>; - }; - }; - - wifi0: wifi@a000000 { - compatible = "qcom,ipq4019-wifi"; - reg = <0xa000000 0x200000>; - resets = <&gcc WIFI0_CPU_INIT_RESET>, - <&gcc WIFI0_RADIO_SRIF_RESET>, - <&gcc WIFI0_RADIO_WARM_RESET>, - <&gcc WIFI0_RADIO_COLD_RESET>, - <&gcc WIFI0_CORE_WARM_RESET>, - <&gcc WIFI0_CORE_COLD_RESET>; - reset-names = "wifi_cpu_init", "wifi_radio_srif", - "wifi_radio_warm", "wifi_radio_cold", - "wifi_core_warm", "wifi_core_cold"; - clocks = <&gcc GCC_WCSS2G_CLK>, - <&gcc GCC_WCSS2G_REF_CLK>, - <&gcc GCC_WCSS2G_RTC_CLK>; - clock-names = "wifi_wcss_cmd", "wifi_wcss_ref", - "wifi_wcss_rtc"; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "msi0", "msi1", "msi2", "msi3", - "msi4", "msi5", "msi6", "msi7", - "msi8", "msi9", "msi10", "msi11", - "msi12", "msi13", "msi14", "msi15", - "legacy"; - status = "disabled"; - }; - - wifi1: wifi@a800000 { - compatible = "qcom,ipq4019-wifi"; - reg = <0xa800000 0x200000>; - resets = <&gcc WIFI1_CPU_INIT_RESET>, - <&gcc WIFI1_RADIO_SRIF_RESET>, - <&gcc WIFI1_RADIO_WARM_RESET>, - <&gcc WIFI1_RADIO_COLD_RESET>, - <&gcc WIFI1_CORE_WARM_RESET>, - <&gcc WIFI1_CORE_COLD_RESET>; - reset-names = "wifi_cpu_init", "wifi_radio_srif", - "wifi_radio_warm", "wifi_radio_cold", - "wifi_core_warm", "wifi_core_cold"; - clocks = <&gcc GCC_WCSS5G_CLK>, - <&gcc GCC_WCSS5G_REF_CLK>, - <&gcc GCC_WCSS5G_RTC_CLK>; - clock-names = "wifi_wcss_cmd", "wifi_wcss_ref", - "wifi_wcss_rtc"; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "msi0", "msi1", "msi2", "msi3", - "msi4", "msi5", "msi6", "msi7", - "msi8", "msi9", "msi10", "msi11", - "msi12", "msi13", "msi14", "msi15", - "legacy"; - status = "disabled"; - }; - }; -}; diff --git a/sys/gnu/dts/arm/qcom-ipq8064-ap148.dts b/sys/gnu/dts/arm/qcom-ipq8064-ap148.dts deleted file mode 100644 index 554c65e7aa0..00000000000 --- a/sys/gnu/dts/arm/qcom-ipq8064-ap148.dts +++ /dev/null @@ -1,34 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "qcom-ipq8064-v1.0.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. IPQ8064/AP-148"; - compatible = "qcom,ipq8064-ap148"; - - soc { - pinmux@800000 { - i2c4_pins: i2c4_pinmux { - pins = "gpio12", "gpio13"; - function = "gsbi4"; - bias-disable; - }; - - buttons_pins: buttons_pins { - mux { - pins = "gpio54", "gpio65"; - drive-strength = <2>; - bias-pull-up; - }; - }; - }; - - gsbi@16300000 { - i2c@16380000 { - status = "ok"; - clock-frequency = <200000>; - pinctrl-0 = <&i2c4_pins>; - pinctrl-names = "default"; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/qcom-ipq8064-v1.0.dtsi b/sys/gnu/dts/arm/qcom-ipq8064-v1.0.dtsi deleted file mode 100644 index e239a048693..00000000000 --- a/sys/gnu/dts/arm/qcom-ipq8064-v1.0.dtsi +++ /dev/null @@ -1,127 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "qcom-ipq8064.dtsi" -#include - -/ { - model = "Qualcomm Technologies, Inc. IPQ8064-v1.0"; - - aliases { - serial0 = &gsbi4_serial; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - soc { - gsbi@16300000 { - qcom,mode = ; - status = "ok"; - - serial@16340000 { - status = "ok"; - }; - }; - - gsbi5: gsbi@1a200000 { - qcom,mode = ; - status = "ok"; - - spi4: spi@1a280000 { - status = "ok"; - spi-max-frequency = <50000000>; - - pinctrl-0 = <&spi_pins>; - pinctrl-names = "default"; - - cs-gpios = <&qcom_pinmux 20 0>; - - flash: m25p80@0 { - compatible = "s25fl256s1"; - #address-cells = <1>; - #size-cells = <1>; - spi-max-frequency = <50000000>; - reg = <0>; - - partition@0 { - label = "rootfs"; - reg = <0x0 0x1000000>; - }; - - partition@1 { - label = "scratch"; - reg = <0x1000000 0x1000000>; - }; - }; - }; - }; - - sata-phy@1b400000 { - status = "ok"; - }; - - sata@29000000 { - ports-implemented = <0x1>; - status = "ok"; - }; - - gpio_keys { - compatible = "gpio-keys"; - pinctrl-0 = <&buttons_pins>; - pinctrl-names = "default"; - - button@1 { - label = "reset"; - linux,code = ; - gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - debounce-interval = <60>; - }; - button@2 { - label = "wps"; - linux,code = ; - gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - debounce-interval = <60>; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-0 = <&leds_pins>; - pinctrl-names = "default"; - - led@7 { - label = "led_usb1"; - gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "usbdev"; - default-state = "off"; - }; - - led@8 { - label = "led_usb3"; - gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "usbdev"; - default-state = "off"; - }; - - led@9 { - label = "status_led_fail"; - gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led@26 { - label = "sata_led"; - gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led@53 { - label = "status_led_pass"; - gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/qcom-ipq8064.dtsi b/sys/gnu/dts/arm/qcom-ipq8064.dtsi deleted file mode 100644 index 16c0da97932..00000000000 --- a/sys/gnu/dts/arm/qcom-ipq8064.dtsi +++ /dev/null @@ -1,669 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include -#include -#include -#include -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - model = "Qualcomm IPQ8064"; - compatible = "qcom,ipq8064"; - interrupt-parent = <&intc>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "qcom,krait"; - enable-method = "qcom,kpss-acc-v1"; - device_type = "cpu"; - reg = <0>; - next-level-cache = <&L2>; - qcom,acc = <&acc0>; - qcom,saw = <&saw0>; - }; - - cpu@1 { - compatible = "qcom,krait"; - enable-method = "qcom,kpss-acc-v1"; - device_type = "cpu"; - reg = <1>; - next-level-cache = <&L2>; - qcom,acc = <&acc1>; - qcom,saw = <&saw1>; - }; - - L2: l2-cache { - compatible = "cache"; - cache-level = <2>; - }; - }; - - memory { - device_type = "memory"; - reg = <0x0 0x0>; - }; - - cpu-pmu { - compatible = "qcom,krait-pmu"; - interrupts = ; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - nss@40000000 { - reg = <0x40000000 0x1000000>; - no-map; - }; - - smem@41000000 { - reg = <0x41000000 0x200000>; - no-map; - }; - }; - - clocks { - cxo_board { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - - pxo_board { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - - sleep_clk: sleep_clk { - compatible = "fixed-clock"; - clock-frequency = <32768>; - #clock-cells = <0>; - }; - }; - - soc: soc { - #address-cells = <1>; - #size-cells = <1>; - ranges; - compatible = "simple-bus"; - - lpass@28100000 { - compatible = "qcom,lpass-cpu"; - status = "disabled"; - clocks = <&lcc AHBIX_CLK>, - <&lcc MI2S_OSR_CLK>, - <&lcc MI2S_BIT_CLK>; - clock-names = "ahbix-clk", - "mi2s-osr-clk", - "mi2s-bit-clk"; - interrupts = ; - interrupt-names = "lpass-irq-lpaif"; - reg = <0x28100000 0x10000>; - reg-names = "lpass-lpaif"; - }; - - qcom_pinmux: pinmux@800000 { - compatible = "qcom,ipq8064-pinctrl"; - reg = <0x800000 0x4000>; - - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = ; - - pcie0_pins: pcie0_pinmux { - mux { - pins = "gpio3"; - function = "pcie1_rst"; - drive-strength = <12>; - bias-disable; - }; - }; - - pcie1_pins: pcie1_pinmux { - mux { - pins = "gpio48"; - function = "pcie2_rst"; - drive-strength = <12>; - bias-disable; - }; - }; - - pcie2_pins: pcie2_pinmux { - mux { - pins = "gpio63"; - function = "pcie3_rst"; - drive-strength = <12>; - bias-disable; - }; - }; - - spi_pins: spi_pins { - mux { - pins = "gpio18", "gpio19", "gpio21"; - function = "gsbi5"; - drive-strength = <10>; - bias-none; - }; - }; - - leds_pins: leds_pins { - mux { - pins = "gpio7", "gpio8", "gpio9", - "gpio26", "gpio53"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - output-low; - }; - }; - - buttons_pins: buttons_pins { - mux { - pins = "gpio54"; - drive-strength = <2>; - bias-pull-up; - }; - }; - }; - - intc: interrupt-controller@2000000 { - compatible = "qcom,msm-qgic2"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0x02000000 0x1000>, - <0x02002000 0x1000>; - }; - - timer@200a000 { - compatible = "qcom,kpss-timer", - "qcom,kpss-wdt-ipq8064", "qcom,msm-timer"; - interrupts = , - , - , - , - ; - reg = <0x0200a000 0x100>; - clock-frequency = <25000000>, - <32768>; - clocks = <&sleep_clk>; - clock-names = "sleep"; - cpu-offset = <0x80000>; - }; - - acc0: clock-controller@2088000 { - compatible = "qcom,kpss-acc-v1"; - reg = <0x02088000 0x1000>, <0x02008000 0x1000>; - }; - - acc1: clock-controller@2098000 { - compatible = "qcom,kpss-acc-v1"; - reg = <0x02098000 0x1000>, <0x02008000 0x1000>; - }; - - saw0: regulator@2089000 { - compatible = "qcom,saw2"; - reg = <0x02089000 0x1000>, <0x02009000 0x1000>; - regulator; - }; - - saw1: regulator@2099000 { - compatible = "qcom,saw2"; - reg = <0x02099000 0x1000>, <0x02009000 0x1000>; - regulator; - }; - - gsbi2: gsbi@12480000 { - compatible = "qcom,gsbi-v1.0.0"; - cell-index = <2>; - reg = <0x12480000 0x100>; - clocks = <&gcc GSBI2_H_CLK>; - clock-names = "iface"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - status = "disabled"; - - syscon-tcsr = <&tcsr>; - - serial@12490000 { - compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; - reg = <0x12490000 0x1000>, - <0x12480000 0x1000>; - interrupts = ; - clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - - i2c@124a0000 { - compatible = "qcom,i2c-qup-v1.1.1"; - reg = <0x124a0000 0x1000>; - interrupts = ; - - clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - - #address-cells = <1>; - #size-cells = <0>; - }; - - }; - - gsbi4: gsbi@16300000 { - compatible = "qcom,gsbi-v1.0.0"; - cell-index = <4>; - reg = <0x16300000 0x100>; - clocks = <&gcc GSBI4_H_CLK>; - clock-names = "iface"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - status = "disabled"; - - syscon-tcsr = <&tcsr>; - - gsbi4_serial: serial@16340000 { - compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; - reg = <0x16340000 0x1000>, - <0x16300000 0x1000>; - interrupts = ; - clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - - i2c@16380000 { - compatible = "qcom,i2c-qup-v1.1.1"; - reg = <0x16380000 0x1000>; - interrupts = ; - - clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - gsbi5: gsbi@1a200000 { - compatible = "qcom,gsbi-v1.0.0"; - cell-index = <5>; - reg = <0x1a200000 0x100>; - clocks = <&gcc GSBI5_H_CLK>; - clock-names = "iface"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - status = "disabled"; - - syscon-tcsr = <&tcsr>; - - serial@1a240000 { - compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; - reg = <0x1a240000 0x1000>, - <0x1a200000 0x1000>; - interrupts = ; - clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - - i2c@1a280000 { - compatible = "qcom,i2c-qup-v1.1.1"; - reg = <0x1a280000 0x1000>; - interrupts = ; - - clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - - #address-cells = <1>; - #size-cells = <0>; - }; - - spi@1a280000 { - compatible = "qcom,spi-qup-v1.1.1"; - reg = <0x1a280000 0x1000>; - interrupts = ; - - clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - gsbi7: gsbi@16600000 { - status = "disabled"; - compatible = "qcom,gsbi-v1.0.0"; - cell-index = <7>; - reg = <0x16600000 0x100>; - clocks = <&gcc GSBI7_H_CLK>; - clock-names = "iface"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - syscon-tcsr = <&tcsr>; - - gsbi7_serial: serial@16640000 { - compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; - reg = <0x16640000 0x1000>, - <0x16600000 0x1000>; - interrupts = ; - clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - }; - - sata_phy: sata-phy@1b400000 { - compatible = "qcom,ipq806x-sata-phy"; - reg = <0x1b400000 0x200>; - - clocks = <&gcc SATA_PHY_CFG_CLK>; - clock-names = "cfg"; - - #phy-cells = <0>; - status = "disabled"; - }; - - sata@29000000 { - compatible = "qcom,ipq806x-ahci", "generic-ahci"; - reg = <0x29000000 0x180>; - - interrupts = ; - - clocks = <&gcc SFAB_SATA_S_H_CLK>, - <&gcc SATA_H_CLK>, - <&gcc SATA_A_CLK>, - <&gcc SATA_RXOOB_CLK>, - <&gcc SATA_PMALIVE_CLK>; - clock-names = "slave_face", "iface", "core", - "rxoob", "pmalive"; - - assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>; - assigned-clock-rates = <100000000>, <100000000>; - - phys = <&sata_phy>; - phy-names = "sata-phy"; - status = "disabled"; - }; - - qcom,ssbi@500000 { - compatible = "qcom,ssbi"; - reg = <0x00500000 0x1000>; - qcom,controller-type = "pmic-arbiter"; - }; - - gcc: clock-controller@900000 { - compatible = "qcom,gcc-ipq8064"; - reg = <0x00900000 0x4000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - tcsr: syscon@1a400000 { - compatible = "qcom,tcsr-ipq8064", "syscon"; - reg = <0x1a400000 0x100>; - }; - - lcc: clock-controller@28000000 { - compatible = "qcom,lcc-ipq8064"; - reg = <0x28000000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - pcie0: pci@1b500000 { - compatible = "qcom,pcie-ipq8064"; - reg = <0x1b500000 0x1000 - 0x1b502000 0x80 - 0x1b600000 0x100 - 0x0ff00000 0x100000>; - reg-names = "dbi", "elbi", "parf", "config"; - device_type = "pci"; - linux,pci-domain = <0>; - bus-range = <0x00 0xff>; - num-lanes = <1>; - #address-cells = <3>; - #size-cells = <2>; - - ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00100000 /* downstream I/O */ - 0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */ - - interrupts = ; - interrupt-names = "msi"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ - - clocks = <&gcc PCIE_A_CLK>, - <&gcc PCIE_H_CLK>, - <&gcc PCIE_PHY_CLK>, - <&gcc PCIE_AUX_CLK>, - <&gcc PCIE_ALT_REF_CLK>; - clock-names = "core", "iface", "phy", "aux", "ref"; - - assigned-clocks = <&gcc PCIE_ALT_REF_CLK>; - assigned-clock-rates = <100000000>; - - resets = <&gcc PCIE_ACLK_RESET>, - <&gcc PCIE_HCLK_RESET>, - <&gcc PCIE_POR_RESET>, - <&gcc PCIE_PCI_RESET>, - <&gcc PCIE_PHY_RESET>, - <&gcc PCIE_EXT_RESET>; - reset-names = "axi", "ahb", "por", "pci", "phy", "ext"; - - pinctrl-0 = <&pcie0_pins>; - pinctrl-names = "default"; - - status = "disabled"; - perst-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>; - }; - - pcie1: pci@1b700000 { - compatible = "qcom,pcie-ipq8064"; - reg = <0x1b700000 0x1000 - 0x1b702000 0x80 - 0x1b800000 0x100 - 0x31f00000 0x100000>; - reg-names = "dbi", "elbi", "parf", "config"; - device_type = "pci"; - linux,pci-domain = <1>; - bus-range = <0x00 0xff>; - num-lanes = <1>; - #address-cells = <3>; - #size-cells = <2>; - - ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00100000 /* downstream I/O */ - 0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */ - - interrupts = ; - interrupt-names = "msi"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 59 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 60 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 61 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ - - clocks = <&gcc PCIE_1_A_CLK>, - <&gcc PCIE_1_H_CLK>, - <&gcc PCIE_1_PHY_CLK>, - <&gcc PCIE_1_AUX_CLK>, - <&gcc PCIE_1_ALT_REF_CLK>; - clock-names = "core", "iface", "phy", "aux", "ref"; - - assigned-clocks = <&gcc PCIE_1_ALT_REF_CLK>; - assigned-clock-rates = <100000000>; - - resets = <&gcc PCIE_1_ACLK_RESET>, - <&gcc PCIE_1_HCLK_RESET>, - <&gcc PCIE_1_POR_RESET>, - <&gcc PCIE_1_PCI_RESET>, - <&gcc PCIE_1_PHY_RESET>, - <&gcc PCIE_1_EXT_RESET>; - reset-names = "axi", "ahb", "por", "pci", "phy", "ext"; - - pinctrl-0 = <&pcie1_pins>; - pinctrl-names = "default"; - - status = "disabled"; - perst-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>; - }; - - pcie2: pci@1b900000 { - compatible = "qcom,pcie-ipq8064"; - reg = <0x1b900000 0x1000 - 0x1b902000 0x80 - 0x1ba00000 0x100 - 0x35f00000 0x100000>; - reg-names = "dbi", "elbi", "parf", "config"; - device_type = "pci"; - linux,pci-domain = <2>; - bus-range = <0x00 0xff>; - num-lanes = <1>; - #address-cells = <3>; - #size-cells = <2>; - - ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00100000 /* downstream I/O */ - 0x82000000 0 0x32000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */ - - interrupts = ; - interrupt-names = "msi"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 72 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 73 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 74 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ - - clocks = <&gcc PCIE_2_A_CLK>, - <&gcc PCIE_2_H_CLK>, - <&gcc PCIE_2_PHY_CLK>, - <&gcc PCIE_2_AUX_CLK>, - <&gcc PCIE_2_ALT_REF_CLK>; - clock-names = "core", "iface", "phy", "aux", "ref"; - - assigned-clocks = <&gcc PCIE_2_ALT_REF_CLK>; - assigned-clock-rates = <100000000>; - - resets = <&gcc PCIE_2_ACLK_RESET>, - <&gcc PCIE_2_HCLK_RESET>, - <&gcc PCIE_2_POR_RESET>, - <&gcc PCIE_2_PCI_RESET>, - <&gcc PCIE_2_PHY_RESET>, - <&gcc PCIE_2_EXT_RESET>; - reset-names = "axi", "ahb", "por", "pci", "phy", "ext"; - - pinctrl-0 = <&pcie2_pins>; - pinctrl-names = "default"; - - status = "disabled"; - perst-gpio = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>; - }; - - vsdcc_fixed: vsdcc-regulator { - compatible = "regulator-fixed"; - regulator-name = "SDCC Power"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - sdcc1bam:dma@12402000 { - compatible = "qcom,bam-v1.3.0"; - reg = <0x12402000 0x8000>; - interrupts = ; - clocks = <&gcc SDC1_H_CLK>; - clock-names = "bam_clk"; - #dma-cells = <1>; - qcom,ee = <0>; - }; - - sdcc3bam:dma@12182000 { - compatible = "qcom,bam-v1.3.0"; - reg = <0x12182000 0x8000>; - interrupts = ; - clocks = <&gcc SDC3_H_CLK>; - clock-names = "bam_clk"; - #dma-cells = <1>; - qcom,ee = <0>; - }; - - amba { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - sdcc@12400000 { - status = "disabled"; - compatible = "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x00051180>; - reg = <0x12400000 0x2000>; - interrupts = ; - interrupt-names = "cmd_irq"; - clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <8>; - max-frequency = <96000000>; - non-removable; - cap-sd-highspeed; - cap-mmc-highspeed; - mmc-ddr-1_8v; - vmmc-supply = <&vsdcc_fixed>; - dmas = <&sdcc1bam 2>, <&sdcc1bam 1>; - dma-names = "tx", "rx"; - }; - - sdcc@12180000 { - compatible = "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x00051180>; - status = "disabled"; - reg = <0x12180000 0x2000>; - interrupts = ; - interrupt-names = "cmd_irq"; - clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <8>; - cap-sd-highspeed; - cap-mmc-highspeed; - max-frequency = <192000000>; - #mmc-ddr-1_8v; - sd-uhs-sdr104; - sd-uhs-ddr50; - vqmmc-supply = <&vsdcc_fixed>; - dmas = <&sdcc3bam 2>, <&sdcc3bam 1>; - dma-names = "tx", "rx"; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/qcom-mdm9615-wp8548-mangoh-green.dts b/sys/gnu/dts/arm/qcom-mdm9615-wp8548-mangoh-green.dts deleted file mode 100644 index 942e3a2cac3..00000000000 --- a/sys/gnu/dts/arm/qcom-mdm9615-wp8548-mangoh-green.dts +++ /dev/null @@ -1,281 +0,0 @@ -/* - * Device Tree Source for mangOH Green Board with WP8548 Module - * - * Copyright (C) 2016 BayLibre, SAS. - * Author : Neil Armstrong - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include - -#include "qcom-mdm9615-wp8548.dtsi" -#include -#include - -/ { - model = "MangOH Green with WP8548 Module"; - compatible = "swir,mangoh-green-wp8548", "swir,wp8548", "qcom,mdm9615"; - - aliases { - spi0 = &gsbi3_spi; - serial0 = &gsbi4_serial; - serial1 = &gsbi5_serial; - i2c0 = &gsbi5_i2c; - mmc0 = &sdcc1; - }; - - chosen { - stdout-path = "serial1:115200n8"; - }; -}; - -&msmgpio { - /* MangOH GPIO Mapping : - * - 2 : GPIOEXP_INT2 - * - 7 : IOT1_GPIO2 - * - 8 : IOT0_GPIO4 - * - 13: IOT0_GPIO3 - * - 21: IOT1_GPIO4 - * - 22: IOT2_GPIO1 - * - 23: IOT2_GPIO2 - * - 24: IOT2_GPIO3 - * - 25: IOT1_GPIO1 - * - 32: IOT1_GPIO3 - * - 33: IOT0_GPIO2 - * - 42: IOT0_GPIO1 and SD Card Detect - */ - - gpioext1_pins: gpioext1_pins { - pins { - pins = "gpio2"; - function = "gpio"; - input-enable; - bias-disable; - }; - }; - - sdc_cd_pins: sdc_cd_pins { - pins { - pins = "gpio42"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; -}; - -&gsbi3_spi { - spi@0 { - compatible = "swir,mangoh-iotport-spi", "spidev"; - spi-max-frequency = <24000000>; - reg = <0>; - }; -}; - -&gsbi5_i2c { - mux@71 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x71>; - - i2c_iot0: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - i2c_iot1: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - i2c_iot2: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - - usbhub: hub@8 { - compatible = "smsc,usb3503a"; - reg = <0x8>; - connect-gpios = <&gpioext2 1 GPIO_ACTIVE_HIGH>; - intn-gpios = <&gpioext2 0 GPIO_ACTIVE_HIGH>; - initial-mode = <1>; - }; - }; - - i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - - gpioext0: gpio@3e { - /* GPIO Expander 0 Mapping : - * - 0: ARDUINO_RESET_Level shift - * - 1: BattChrgr_PG_N - * - 2: BattGauge_GPIO - * - 3: LED_ON (out active high) - * - 4: ATmega_reset_GPIO - * - 5: X - * - 6: PCM_ANALOG_SELECT (out active high) - * - 7: X - * - 8: Board_rev_res1 (in) - * - 9: Board_rev_res2 (in) - * - 10: UART_EXP1_ENn (out active low / pull-down) - * - 11: UART_EXP1_IN (out pull-down) - * - 12: UART_EXP2_IN (out pull-down) - * - 13: SDIO_SEL (out pull-down) - * - 14: SPI_EXP1_ENn (out active low / pull-down) - * - 15: SPI_EXP1_IN (out pull-down) - */ - #gpio-cells = <2>; - #interrupt-cells = <2>; - compatible = "semtech,sx1509q"; - reg = <0x3e>; - interrupt-parent = <&gpioext1>; - interrupts = <0 IRQ_TYPE_EDGE_FALLING>; - - probe-reset; - - gpio-controller; - interrupt-controller; - }; - }; - - i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - - gpioext1: gpio@3f { - /* GPIO Expander 1 Mapping : - * - 0: GPIOEXP_INT1 - * - 1: Battery detect - * - 2: GPIO_SCF3_RESET - * - 3: LED_CARD_DETECT_IOT0 (in) - * - 4: LED_CARD_DETECT_IOT1 (in) - * - 5: LED_CARD_DETECT_IOT2 (in) - * - 6: UIM2_PWM_SELECT - * - 7: UIM2_M2_S_SELECT - * - 8: TP900 - * - 9: SENSOR_INT1 (in) - * - 10: SENSOR_INT2 (in) - * - 11: CARD_DETECT_IOT0 (in pull-up) - * - 12: CARD_DETECT_IOT2 (in pull-up) - * - 13: CARD_DETECT_IOT1 (in pull-up) - * - 14: GPIOEXP_INT3 (in active low / pull-up) - * - 15: BattChrgr_INT_N - */ - pinctrl-0 = <&gpioext1_pins>; - pinctrl-names = "default"; - - #gpio-cells = <2>; - #interrupt-cells = <2>; - compatible = "semtech,sx1509q"; - reg = <0x3f>; - interrupt-parent = <&msmgpio>; - interrupts = <0 IRQ_TYPE_EDGE_FALLING>; - - probe-reset; - - gpio-controller; - interrupt-controller; - }; - }; - - i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - - gpioext2: gpio@70 { - /* GPIO Expander 2 Mapping : - * - 0: USB_HUB_INTn - * - 1: HUB_CONNECT - * - 2: GPIO_IOT2_RESET (out active low / pull-up) - * - 3: GPIO_IOT1_RESET (out active low / pull-up) - * - 4: GPIO_IOT0_RESET (out active low / pull-up) - * - 5: TP901 - * - 6: TP902 - * - 7: TP903 - * - 8: UART_EXP2_ENn (out active low / pull-down) - * - 9: PCM_EXP1_ENn (out active low) - * - 10: PCM_EXP1_SEL (out) - * - 11: ARD_FTDI - * - 12: TP904 - * - 13: TP905 - * - 14: TP906 - * - 15: RS232_Enable (out active high / pull-up) - */ - #gpio-cells = <2>; - #interrupt-cells = <2>; - compatible = "semtech,sx1509q"; - reg = <0x70>; - interrupt-parent = <&gpioext1>; - interrupts = <14 IRQ_TYPE_EDGE_FALLING>; - - probe-reset; - - gpio-controller; - interrupt-controller; - }; - }; - - i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - }; -}; - -&sdcc1 { - pinctrl-0 = <&sdc_cd_pins>; - pinctrl-names = "default"; - disable-wp; - cd-gpios = <&msmgpio 42 GPIO_ACTIVE_LOW>; /* Active low CD */ -}; diff --git a/sys/gnu/dts/arm/qcom-mdm9615-wp8548.dtsi b/sys/gnu/dts/arm/qcom-mdm9615-wp8548.dtsi deleted file mode 100644 index 26b034bd19d..00000000000 --- a/sys/gnu/dts/arm/qcom-mdm9615-wp8548.dtsi +++ /dev/null @@ -1,171 +0,0 @@ -/* - * Device Tree Source for Sierra Wireless WP8548 Module - * - * Copyright (C) 2016 BayLibre, SAS. - * Author : Neil Armstrong - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "qcom-mdm9615.dtsi" - -/ { - model = "Sierra Wireless WP8548 Module"; - compatible = "swir,wp8548", "qcom,mdm9615"; - - memory { - device_type = "memory"; - reg = <0x48000000 0x7F00000>; - }; -}; - -&msmgpio { - pinctrl-0 = <&reset_out_pins>; - pinctrl-names = "default"; - - gsbi3_pins: gsbi3_pins { - mux { - pins = "gpio8", "gpio9", "gpio10", "gpio11"; - function = "gsbi3"; - drive-strength = <8>; - bias-disable; - }; - }; - - gsbi4_pins: gsbi4_pins { - mux { - pins = "gpio12", "gpio13", "gpio14", "gpio15"; - function = "gsbi4"; - drive-strength = <8>; - bias-disable; - }; - }; - - gsbi5_i2c_pins: gsbi5_i2c_pins { - pin16 { - pins = "gpio16"; - function = "gsbi5_i2c"; - drive-strength = <8>; - bias-disable; - }; - - pin17 { - pins = "gpio17"; - function = "gsbi5_i2c"; - drive-strength = <2>; - bias-disable; - }; - }; - - gsbi5_uart_pins: gsbi5_uart_pins { - mux { - pins = "gpio18", "gpio19"; - function = "gsbi5_uart"; - drive-strength = <8>; - bias-disable; - }; - }; - - reset_out_pins: reset_out_pins { - pins { - pins = "gpio66"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - output-high; - }; - }; -}; - -&pmicgpio { - usb_vbus_5v_pins: usb_vbus_5v_pins { - pins = "gpio4"; - function = "normal"; - output-high; - bias-disable; - qcom,drive-strength = <1>; - power-source = <2>; - }; -}; - -&gsbi3 { - status = "ok"; - qcom,mode = ; -}; - -&gsbi3_spi { - status = "ok"; - pinctrl-0 = <&gsbi3_pins>; - pinctrl-names = "default"; - assigned-clocks = <&gcc GSBI3_QUP_CLK>; - assigned-clock-rates = <24000000>; -}; - -&gsbi4 { - status = "ok"; - qcom,mode = ; -}; - -&gsbi4_serial { - status = "ok"; - pinctrl-0 = <&gsbi4_pins>; - pinctrl-names = "default"; -}; - -&gsbi5 { - status = "ok"; - qcom,mode = ; -}; - -&gsbi5_i2c { - status = "ok"; - clock-frequency = <200000>; - pinctrl-0 = <&gsbi5_i2c_pins>; - pinctrl-names = "default"; -}; - -&gsbi5_serial { - status = "ok"; - pinctrl-0 = <&gsbi5_uart_pins>; - pinctrl-names = "default"; -}; - -&sdcc1 { - status = "ok"; -}; diff --git a/sys/gnu/dts/arm/qcom-mdm9615.dtsi b/sys/gnu/dts/arm/qcom-mdm9615.dtsi deleted file mode 100644 index 356e9535f7a..00000000000 --- a/sys/gnu/dts/arm/qcom-mdm9615.dtsi +++ /dev/null @@ -1,553 +0,0 @@ -/* - * Device Tree Source for Qualcomm MDM9615 SoC - * - * Copyright (C) 2016 BayLibre, SAS. - * Author : Neil Armstrong - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include -#include -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - model = "Qualcomm MDM9615"; - compatible = "qcom,mdm9615"; - interrupt-parent = <&intc>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "arm,cortex-a5"; - device_type = "cpu"; - next-level-cache = <&L2>; - }; - }; - - cpu-pmu { - compatible = "arm,cortex-a5-pmu"; - interrupts = ; - }; - - clocks { - cxo_board { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <19200000>; - }; - }; - - regulators { - vsdcc_fixed: vsdcc-regulator { - compatible = "regulator-fixed"; - regulator-name = "SDCC Power"; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - regulator-always-on; - }; - }; - - soc: soc { - #address-cells = <1>; - #size-cells = <1>; - ranges; - compatible = "simple-bus"; - - L2: l2-cache@2040000 { - compatible = "arm,pl310-cache"; - reg = <0x02040000 0x1000>; - arm,data-latency = <2 2 0>; - cache-unified; - cache-level = <2>; - }; - - intc: interrupt-controller@2000000 { - compatible = "qcom,msm-qgic2"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0x02000000 0x1000>, - <0x02002000 0x1000>; - }; - - timer@200a000 { - compatible = "qcom,kpss-timer", "qcom,msm-timer"; - interrupts = , - , - ; - reg = <0x0200a000 0x100>; - clock-frequency = <27000000>, - <32768>; - cpu-offset = <0x80000>; - }; - - msmgpio: pinctrl@800000 { - compatible = "qcom,mdm9615-pinctrl"; - gpio-controller; - #gpio-cells = <2>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x800000 0x4000>; - }; - - gcc: clock-controller@900000 { - compatible = "qcom,gcc-mdm9615"; - #clock-cells = <1>; - #reset-cells = <1>; - reg = <0x900000 0x4000>; - }; - - lcc: clock-controller@28000000 { - compatible = "qcom,lcc-mdm9615"; - reg = <0x28000000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - l2cc: clock-controller@2011000 { - compatible = "syscon"; - reg = <0x02011000 0x1000>; - }; - - rng@1a500000 { - compatible = "qcom,prng"; - reg = <0x1a500000 0x200>; - clocks = <&gcc PRNG_CLK>; - clock-names = "core"; - assigned-clocks = <&gcc PRNG_CLK>; - assigned-clock-rates = <32000000>; - }; - - gsbi2: gsbi@16100000 { - compatible = "qcom,gsbi-v1.0.0"; - cell-index = <2>; - reg = <0x16100000 0x100>; - clocks = <&gcc GSBI2_H_CLK>; - clock-names = "iface"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gsbi2_i2c: i2c@16180000 { - compatible = "qcom,i2c-qup-v1.1.1"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x16180000 0x1000>; - interrupts = ; - - clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - }; - - gsbi3: gsbi@16200000 { - compatible = "qcom,gsbi-v1.0.0"; - cell-index = <3>; - reg = <0x16200000 0x100>; - clocks = <&gcc GSBI3_H_CLK>; - clock-names = "iface"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gsbi3_spi: spi@16280000 { - compatible = "qcom,spi-qup-v1.1.1"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x16280000 0x1000>; - interrupts = ; - spi-max-frequency = <24000000>; - - clocks = <&gcc GSBI3_QUP_CLK>, <&gcc GSBI3_H_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - }; - - gsbi4: gsbi@16300000 { - compatible = "qcom,gsbi-v1.0.0"; - cell-index = <4>; - reg = <0x16300000 0x100>; - clocks = <&gcc GSBI4_H_CLK>; - clock-names = "iface"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - syscon-tcsr = <&tcsr>; - - gsbi4_serial: serial@16340000 { - compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; - reg = <0x16340000 0x1000>, - <0x16300000 0x1000>; - interrupts = ; - clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - }; - - gsbi5: gsbi@16400000 { - compatible = "qcom,gsbi-v1.0.0"; - cell-index = <5>; - reg = <0x16400000 0x100>; - clocks = <&gcc GSBI5_H_CLK>; - clock-names = "iface"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - syscon-tcsr = <&tcsr>; - - gsbi5_i2c: i2c@16480000 { - compatible = "qcom,i2c-qup-v1.1.1"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x16480000 0x1000>; - interrupts = ; - - /* QUP clock is not initialized, set rate */ - assigned-clocks = <&gcc GSBI5_QUP_CLK>; - assigned-clock-rates = <24000000>; - - clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - - gsbi5_serial: serial@16440000 { - compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; - reg = <0x16440000 0x1000>, - <0x16400000 0x1000>; - interrupts = ; - clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - }; - - qcom,ssbi@500000 { - compatible = "qcom,ssbi"; - reg = <0x500000 0x1000>; - qcom,controller-type = "pmic-arbiter"; - - pmicintc: pmic@0 { - compatible = "qcom,pm8018", "qcom,pm8921"; - interrupts = ; - #interrupt-cells = <2>; - interrupt-controller; - #address-cells = <1>; - #size-cells = <0>; - - pwrkey@1c { - compatible = "qcom,pm8018-pwrkey", "qcom,pm8921-pwrkey"; - reg = <0x1c>; - interrupt-parent = <&pmicintc>; - interrupts = <50 IRQ_TYPE_EDGE_RISING>, - <51 IRQ_TYPE_EDGE_RISING>; - debounce = <15625>; - pull-up; - }; - - pmicmpp: mpp@50 { - compatible = "qcom,pm8018-mpp", "qcom,ssbi-mpp"; - interrupt-parent = <&pmicintc>; - interrupts = <24 IRQ_TYPE_NONE>, - <25 IRQ_TYPE_NONE>, - <26 IRQ_TYPE_NONE>, - <27 IRQ_TYPE_NONE>, - <28 IRQ_TYPE_NONE>, - <29 IRQ_TYPE_NONE>; - reg = <0x50>; - gpio-controller; - #gpio-cells = <2>; - }; - - rtc@11d { - compatible = "qcom,pm8018-rtc", "qcom,pm8921-rtc"; - interrupt-parent = <&pmicintc>; - interrupts = <39 IRQ_TYPE_EDGE_RISING>; - reg = <0x11d>; - allow-set-time; - }; - - pmicgpio: gpio@150 { - compatible = "qcom,pm8018-gpio", "qcom,ssbi-gpio"; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - gpio-ranges = <&pmicgpio 0 0 6>; - #gpio-cells = <2>; - }; - }; - }; - - sdcc1bam: dma@12182000{ - compatible = "qcom,bam-v1.3.0"; - reg = <0x12182000 0x8000>; - interrupts = ; - clocks = <&gcc SDC1_H_CLK>; - clock-names = "bam_clk"; - #dma-cells = <1>; - qcom,ee = <0>; - }; - - sdcc2bam: dma@12142000{ - compatible = "qcom,bam-v1.3.0"; - reg = <0x12142000 0x8000>; - interrupts = ; - clocks = <&gcc SDC2_H_CLK>; - clock-names = "bam_clk"; - #dma-cells = <1>; - qcom,ee = <0>; - }; - - amba { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - sdcc1: sdcc@12180000 { - status = "disabled"; - compatible = "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x00051180>; - reg = <0x12180000 0x2000>; - interrupts = ; - interrupt-names = "cmd_irq"; - clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <8>; - max-frequency = <48000000>; - cap-sd-highspeed; - cap-mmc-highspeed; - vmmc-supply = <&vsdcc_fixed>; - dmas = <&sdcc1bam 2>, <&sdcc1bam 1>; - dma-names = "tx", "rx"; - assigned-clocks = <&gcc SDC1_CLK>; - assigned-clock-rates = <400000>; - }; - - sdcc2: sdcc@12140000 { - compatible = "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x00051180>; - status = "disabled"; - reg = <0x12140000 0x2000>; - interrupts = ; - interrupt-names = "cmd_irq"; - clocks = <&gcc SDC2_CLK>, <&gcc SDC2_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <4>; - cap-sd-highspeed; - cap-mmc-highspeed; - max-frequency = <48000000>; - no-1-8-v; - vmmc-supply = <&vsdcc_fixed>; - dmas = <&sdcc2bam 2>, <&sdcc2bam 1>; - dma-names = "tx", "rx"; - assigned-clocks = <&gcc SDC2_CLK>; - assigned-clock-rates = <400000>; - }; - }; - - tcsr: syscon@1a400000 { - compatible = "qcom,tcsr-mdm9615", "syscon"; - reg = <0x1a400000 0x100>; - }; - - rpm: rpm@108000 { - compatible = "qcom,rpm-mdm9615"; - reg = <0x108000 0x1000>; - - qcom,ipc = <&l2cc 0x8 2>; - - interrupts = , - , - ; - interrupt-names = "ack", "err", "wakeup"; - - regulators { - compatible = "qcom,rpm-pm8018-regulators"; - - vin_lvs1-supply = <&pm8018_s3>; - - vdd_l7-supply = <&pm8018_s4>; - vdd_l8-supply = <&pm8018_s3>; - vdd_l9_l10_l11_l12-supply = <&pm8018_s5>; - - /* Buck SMPS */ - pm8018_s1: s1 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1150000>; - qcom,switch-mode-frequency = <1600000>; - bias-pull-down; - }; - - pm8018_s2: s2 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1300000>; - qcom,switch-mode-frequency = <1600000>; - bias-pull-down; - }; - - pm8018_s3: s3 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - qcom,switch-mode-frequency = <1600000>; - bias-pull-down; - }; - - pm8018_s4: s4 { - regulator-min-microvolt = <2100000>; - regulator-max-microvolt = <2200000>; - qcom,switch-mode-frequency = <1600000>; - bias-pull-down; - }; - - pm8018_s5: s5 { - regulator-always-on; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - qcom,switch-mode-frequency = <1600000>; - bias-pull-down; - }; - - /* PMOS LDO */ - pm8018_l2: l2 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - bias-pull-down; - }; - - pm8018_l3: l3 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - bias-pull-down; - }; - - pm8018_l4: l4 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - bias-pull-down; - }; - - pm8018_l5: l5 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - bias-pull-down; - }; - - pm8018_l6: l6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2850000>; - bias-pull-down; - }; - - pm8018_l7: l7 { - regulator-min-microvolt = <1850000>; - regulator-max-microvolt = <1900000>; - bias-pull-down; - }; - - pm8018_l8: l8 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - bias-pull-down; - }; - - pm8018_l9: l9 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1150000>; - bias-pull-down; - }; - - pm8018_l10: l10 { - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - bias-pull-down; - }; - - pm8018_l11: l11 { - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - bias-pull-down; - }; - - pm8018_l12: l12 { - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - bias-pull-down; - }; - - pm8018_l13: l13 { - regulator-min-microvolt = <1850000>; - regulator-max-microvolt = <2950000>; - bias-pull-down; - }; - - pm8018_l14: l14 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - bias-pull-down; - }; - - /* Low Voltage Switch */ - pm8018_lvs1: lvs1 { - bias-pull-down; - }; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/qcom-msm8660-surf.dts b/sys/gnu/dts/arm/qcom-msm8660-surf.dts deleted file mode 100644 index f01a11b18d6..00000000000 --- a/sys/gnu/dts/arm/qcom-msm8660-surf.dts +++ /dev/null @@ -1,78 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include - -#include "qcom-msm8660.dtsi" - -/ { - model = "Qualcomm MSM8660 SURF"; - compatible = "qcom,msm8660-surf", "qcom,msm8660"; - - aliases { - serial0 = &gsbi12_serial; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - soc { - gsbi@19c00000 { - status = "ok"; - qcom,mode = ; - serial@19c40000 { - status = "ok"; - }; - }; - - /* Temporary fixed regulator */ - vsdcc_fixed: vsdcc-regulator { - compatible = "regulator-fixed"; - regulator-name = "SDCC Power"; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - regulator-always-on; - }; - - amba { - /* eMMC */ - sdcc1: sdcc@12400000 { - status = "okay"; - vmmc-supply = <&vsdcc_fixed>; - }; - - /* External micro SD card */ - sdcc3: sdcc@12180000 { - status = "okay"; - vmmc-supply = <&vsdcc_fixed>; - }; - }; - }; -}; - -&pm8058 { - keypad@148 { - linux,keymap = < - MATRIX_KEY(0, 0, KEY_FN_F1) - MATRIX_KEY(0, 1, KEY_UP) - MATRIX_KEY(0, 2, KEY_LEFT) - MATRIX_KEY(0, 3, KEY_VOLUMEUP) - MATRIX_KEY(1, 0, KEY_FN_F2) - MATRIX_KEY(1, 1, KEY_RIGHT) - MATRIX_KEY(1, 2, KEY_DOWN) - MATRIX_KEY(1, 3, KEY_VOLUMEDOWN) - MATRIX_KEY(2, 3, KEY_ENTER) - MATRIX_KEY(4, 0, KEY_CAMERA_FOCUS) - MATRIX_KEY(4, 1, KEY_UP) - MATRIX_KEY(4, 2, KEY_LEFT) - MATRIX_KEY(4, 3, KEY_HOME) - MATRIX_KEY(4, 4, KEY_FN_F3) - MATRIX_KEY(5, 0, KEY_CAMERA) - MATRIX_KEY(5, 1, KEY_RIGHT) - MATRIX_KEY(5, 2, KEY_DOWN) - MATRIX_KEY(5, 3, KEY_BACK) - MATRIX_KEY(5, 4, KEY_MENU) - >; - keypad,num-rows = <6>; - keypad,num-columns = <5>; - }; -}; diff --git a/sys/gnu/dts/arm/qcom-msm8660.dtsi b/sys/gnu/dts/arm/qcom-msm8660.dtsi deleted file mode 100644 index ec5cbc468bd..00000000000 --- a/sys/gnu/dts/arm/qcom-msm8660.dtsi +++ /dev/null @@ -1,580 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - model = "Qualcomm MSM8660"; - compatible = "qcom,msm8660"; - interrupt-parent = <&intc>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "qcom,scorpion"; - enable-method = "qcom,gcc-msm8660"; - device_type = "cpu"; - reg = <0>; - next-level-cache = <&L2>; - }; - - cpu@1 { - compatible = "qcom,scorpion"; - enable-method = "qcom,gcc-msm8660"; - device_type = "cpu"; - reg = <1>; - next-level-cache = <&L2>; - }; - - L2: l2-cache { - compatible = "cache"; - cache-level = <2>; - }; - }; - - memory { - device_type = "memory"; - reg = <0x0 0x0>; - }; - - cpu-pmu { - compatible = "qcom,scorpion-mp-pmu"; - interrupts = <1 9 0x304>; - }; - - clocks { - cxo_board { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <19200000>; - }; - - pxo_board { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <27000000>; - }; - - sleep_clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - /* - * These channels from the ADC are simply hardware monitors. - * That is why the ADC is referred to as "HKADC" - HouseKeeping - * ADC. - */ - iio-hwmon { - compatible = "iio-hwmon"; - io-channels = <&xoadc 0x00 0x01>, /* Battery */ - <&xoadc 0x00 0x02>, /* DC in (charger) */ - <&xoadc 0x00 0x04>, /* VPH the main system voltage */ - <&xoadc 0x00 0x0b>, /* Die temperature */ - <&xoadc 0x00 0x0c>, /* Reference voltage 1.25V */ - <&xoadc 0x00 0x0d>, /* Reference voltage 0.625V */ - <&xoadc 0x00 0x0e>; /* Reference voltage 0.325V */ - }; - - soc: soc { - #address-cells = <1>; - #size-cells = <1>; - ranges; - compatible = "simple-bus"; - - intc: interrupt-controller@2080000 { - compatible = "qcom,msm-8660-qgic"; - interrupt-controller; - #interrupt-cells = <3>; - reg = < 0x02080000 0x1000 >, - < 0x02081000 0x1000 >; - }; - - timer@2000000 { - compatible = "qcom,scss-timer", "qcom,msm-timer"; - interrupts = <1 0 0x301>, - <1 1 0x301>, - <1 2 0x301>; - reg = <0x02000000 0x100>; - clock-frequency = <27000000>, - <32768>; - cpu-offset = <0x40000>; - }; - - tlmm: pinctrl@800000 { - compatible = "qcom,msm8660-pinctrl"; - reg = <0x800000 0x4000>; - - gpio-controller; - #gpio-cells = <2>; - interrupts = <0 16 0x4>; - interrupt-controller; - #interrupt-cells = <2>; - - }; - - gcc: clock-controller@900000 { - compatible = "qcom,gcc-msm8660"; - #clock-cells = <1>; - #reset-cells = <1>; - reg = <0x900000 0x4000>; - }; - - gsbi6: gsbi@16500000 { - compatible = "qcom,gsbi-v1.0.0"; - cell-index = <12>; - reg = <0x16500000 0x100>; - clocks = <&gcc GSBI6_H_CLK>; - clock-names = "iface"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - status = "disabled"; - - syscon-tcsr = <&tcsr>; - - gsbi6_serial: serial@16540000 { - compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; - reg = <0x16540000 0x1000>, - <0x16500000 0x1000>; - interrupts = ; - clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - - gsbi6_i2c: i2c@16580000 { - compatible = "qcom,i2c-qup-v1.1.1"; - reg = <0x16580000 0x1000>; - interrupts = ; - clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>; - clock-names = "core", "iface"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - gsbi7: gsbi@16600000 { - compatible = "qcom,gsbi-v1.0.0"; - cell-index = <12>; - reg = <0x16600000 0x100>; - clocks = <&gcc GSBI7_H_CLK>; - clock-names = "iface"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - status = "disabled"; - - syscon-tcsr = <&tcsr>; - - gsbi7_serial: serial@16640000 { - compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; - reg = <0x16640000 0x1000>, - <0x16600000 0x1000>; - interrupts = ; - clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - - gsbi7_i2c: i2c@16680000 { - compatible = "qcom,i2c-qup-v1.1.1"; - reg = <0x16680000 0x1000>; - interrupts = ; - clocks = <&gcc GSBI7_QUP_CLK>, <&gcc GSBI7_H_CLK>; - clock-names = "core", "iface"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - gsbi8: gsbi@19800000 { - compatible = "qcom,gsbi-v1.0.0"; - cell-index = <12>; - reg = <0x19800000 0x100>; - clocks = <&gcc GSBI8_H_CLK>; - clock-names = "iface"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - syscon-tcsr = <&tcsr>; - - gsbi8_i2c: i2c@19880000 { - compatible = "qcom,i2c-qup-v1.1.1"; - reg = <0x19880000 0x1000>; - interrupts = ; - clocks = <&gcc GSBI8_QUP_CLK>, <&gcc GSBI8_H_CLK>; - clock-names = "core", "iface"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - gsbi12: gsbi@19c00000 { - compatible = "qcom,gsbi-v1.0.0"; - cell-index = <12>; - reg = <0x19c00000 0x100>; - clocks = <&gcc GSBI12_H_CLK>; - clock-names = "iface"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - syscon-tcsr = <&tcsr>; - - gsbi12_serial: serial@19c40000 { - compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; - reg = <0x19c40000 0x1000>, - <0x19c00000 0x1000>; - interrupts = <0 195 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - - gsbi12_i2c: i2c@19c80000 { - compatible = "qcom,i2c-qup-v1.1.1"; - reg = <0x19c80000 0x1000>; - interrupts = <0 196 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GSBI12_QUP_CLK>, <&gcc GSBI12_H_CLK>; - clock-names = "core", "iface"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - external-bus@1a100000 { - compatible = "qcom,msm8660-ebi2"; - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0x0 0x1a800000 0x00800000>, - <1 0x0 0x1b000000 0x00800000>, - <2 0x0 0x1b800000 0x00800000>, - <3 0x0 0x1d000000 0x08000000>, - <4 0x0 0x1c800000 0x00800000>, - <5 0x0 0x1c000000 0x00800000>; - reg = <0x1a100000 0x1000>, <0x1a110000 0x1000>; - reg-names = "ebi2", "xmem"; - clocks = <&gcc EBI2_2X_CLK>, <&gcc EBI2_CLK>; - clock-names = "ebi2x", "ebi2"; - status = "disabled"; - }; - - qcom,ssbi@500000 { - compatible = "qcom,ssbi"; - reg = <0x500000 0x1000>; - qcom,controller-type = "pmic-arbiter"; - - pm8058: pmic@0 { - compatible = "qcom,pm8058"; - interrupt-parent = <&tlmm>; - interrupts = <88 8>; - #interrupt-cells = <2>; - interrupt-controller; - #address-cells = <1>; - #size-cells = <0>; - - pm8058_gpio: gpio@150 { - compatible = "qcom,pm8058-gpio", - "qcom,ssbi-gpio"; - reg = <0x150>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - gpio-ranges = <&pm8058_gpio 0 0 44>; - #gpio-cells = <2>; - - }; - - pm8058_mpps: mpps@50 { - compatible = "qcom,pm8058-mpp", - "qcom,ssbi-mpp"; - reg = <0x50>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&pm8058>; - interrupts = - <128 IRQ_TYPE_NONE>, - <129 IRQ_TYPE_NONE>, - <130 IRQ_TYPE_NONE>, - <131 IRQ_TYPE_NONE>, - <132 IRQ_TYPE_NONE>, - <133 IRQ_TYPE_NONE>, - <134 IRQ_TYPE_NONE>, - <135 IRQ_TYPE_NONE>, - <136 IRQ_TYPE_NONE>, - <137 IRQ_TYPE_NONE>, - <138 IRQ_TYPE_NONE>, - <139 IRQ_TYPE_NONE>; - }; - - pwrkey@1c { - compatible = "qcom,pm8058-pwrkey"; - reg = <0x1c>; - interrupt-parent = <&pm8058>; - interrupts = <50 1>, <51 1>; - debounce = <15625>; - pull-up; - }; - - keypad@148 { - compatible = "qcom,pm8058-keypad"; - reg = <0x148>; - interrupt-parent = <&pm8058>; - interrupts = <74 1>, <75 1>; - debounce = <15>; - scan-delay = <32>; - row-hold = <91500>; - }; - - xoadc: xoadc@197 { - compatible = "qcom,pm8058-adc"; - reg = <0x197>; - interrupts-extended = <&pm8058 76 IRQ_TYPE_EDGE_RISING>; - #address-cells = <2>; - #size-cells = <0>; - #io-channel-cells = <2>; - - vcoin: adc-channel@0 { - reg = <0x00 0x00>; - }; - vbat: adc-channel@1 { - reg = <0x00 0x01>; - }; - dcin: adc-channel@2 { - reg = <0x00 0x02>; - }; - ichg: adc-channel@3 { - reg = <0x00 0x03>; - }; - vph_pwr: adc-channel@4 { - reg = <0x00 0x04>; - }; - usb_vbus: adc-channel@a { - reg = <0x00 0x0a>; - }; - die_temp: adc-channel@b { - reg = <0x00 0x0b>; - }; - ref_625mv: adc-channel@c { - reg = <0x00 0x0c>; - }; - ref_1250mv: adc-channel@d { - reg = <0x00 0x0d>; - }; - ref_325mv: adc-channel@e { - reg = <0x00 0x0e>; - }; - ref_muxoff: adc-channel@f { - reg = <0x00 0x0f>; - }; - }; - - rtc@1e8 { - compatible = "qcom,pm8058-rtc"; - reg = <0x1e8>; - interrupt-parent = <&pm8058>; - interrupts = <39 1>; - allow-set-time; - }; - - vibrator@4a { - compatible = "qcom,pm8058-vib"; - reg = <0x4a>; - }; - }; - }; - - l2cc: clock-controller@2082000 { - compatible = "syscon"; - reg = <0x02082000 0x1000>; - }; - - rpm: rpm@104000 { - compatible = "qcom,rpm-msm8660"; - reg = <0x00104000 0x1000>; - qcom,ipc = <&l2cc 0x8 2>; - - interrupts = , - , - ; - interrupt-names = "ack", "err", "wakeup"; - clocks = <&gcc RPM_MSG_RAM_H_CLK>; - clock-names = "ram"; - - rpmcc: clock-controller { - compatible = "qcom,rpmcc-msm8660", "qcom,rpmcc"; - #clock-cells = <1>; - }; - - pm8901-regulators { - compatible = "qcom,rpm-pm8901-regulators"; - - pm8901_l0: l0 {}; - pm8901_l1: l1 {}; - pm8901_l2: l2 {}; - pm8901_l3: l3 {}; - pm8901_l4: l4 {}; - pm8901_l5: l5 {}; - pm8901_l6: l6 {}; - - /* S0 and S1 Handled as SAW regulators by SPM */ - pm8901_s2: s2 {}; - pm8901_s3: s3 {}; - pm8901_s4: s4 {}; - - pm8901_lvs0: lvs0 {}; - pm8901_lvs1: lvs1 {}; - pm8901_lvs2: lvs2 {}; - pm8901_lvs3: lvs3 {}; - - pm8901_mvs: mvs {}; - }; - - pm8058-regulators { - compatible = "qcom,rpm-pm8058-regulators"; - - pm8058_l0: l0 {}; - pm8058_l1: l1 {}; - pm8058_l2: l2 {}; - pm8058_l3: l3 {}; - pm8058_l4: l4 {}; - pm8058_l5: l5 {}; - pm8058_l6: l6 {}; - pm8058_l7: l7 {}; - pm8058_l8: l8 {}; - pm8058_l9: l9 {}; - pm8058_l10: l10 {}; - pm8058_l11: l11 {}; - pm8058_l12: l12 {}; - pm8058_l13: l13 {}; - pm8058_l14: l14 {}; - pm8058_l15: l15 {}; - pm8058_l16: l16 {}; - pm8058_l17: l17 {}; - pm8058_l18: l18 {}; - pm8058_l19: l19 {}; - pm8058_l20: l20 {}; - pm8058_l21: l21 {}; - pm8058_l22: l22 {}; - pm8058_l23: l23 {}; - pm8058_l24: l24 {}; - pm8058_l25: l25 {}; - - pm8058_s0: s0 {}; - pm8058_s1: s1 {}; - pm8058_s2: s2 {}; - pm8058_s3: s3 {}; - pm8058_s4: s4 {}; - - pm8058_lvs0: lvs0 {}; - pm8058_lvs1: lvs1 {}; - - pm8058_ncp: ncp {}; - }; - }; - - amba { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - sdcc1: sdcc@12400000 { - status = "disabled"; - compatible = "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x00051180>; - reg = <0x12400000 0x8000>; - interrupts = ; - interrupt-names = "cmd_irq"; - clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <8>; - max-frequency = <48000000>; - non-removable; - cap-sd-highspeed; - cap-mmc-highspeed; - }; - - sdcc2: sdcc@12140000 { - status = "disabled"; - compatible = "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x00051180>; - reg = <0x12140000 0x8000>; - interrupts = ; - interrupt-names = "cmd_irq"; - clocks = <&gcc SDC2_CLK>, <&gcc SDC2_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <8>; - max-frequency = <48000000>; - cap-sd-highspeed; - cap-mmc-highspeed; - }; - - sdcc3: sdcc@12180000 { - compatible = "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x00051180>; - status = "disabled"; - reg = <0x12180000 0x8000>; - interrupts = ; - interrupt-names = "cmd_irq"; - clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <4>; - cap-sd-highspeed; - cap-mmc-highspeed; - max-frequency = <48000000>; - no-1-8-v; - }; - - sdcc4: sdcc@121c0000 { - compatible = "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x00051180>; - status = "disabled"; - reg = <0x121c0000 0x8000>; - interrupts = ; - interrupt-names = "cmd_irq"; - clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <4>; - max-frequency = <48000000>; - cap-sd-highspeed; - cap-mmc-highspeed; - }; - - sdcc5: sdcc@12200000 { - compatible = "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x00051180>; - status = "disabled"; - reg = <0x12200000 0x8000>; - interrupts = ; - interrupt-names = "cmd_irq"; - clocks = <&gcc SDC5_CLK>, <&gcc SDC5_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <4>; - cap-sd-highspeed; - cap-mmc-highspeed; - max-frequency = <48000000>; - }; - }; - - tcsr: syscon@1a400000 { - compatible = "qcom,tcsr-msm8660", "syscon"; - reg = <0x1a400000 0x100>; - }; - }; - -}; diff --git a/sys/gnu/dts/arm/qcom-msm8960-cdp.dts b/sys/gnu/dts/arm/qcom-msm8960-cdp.dts deleted file mode 100644 index 82d5d8267ad..00000000000 --- a/sys/gnu/dts/arm/qcom-msm8960-cdp.dts +++ /dev/null @@ -1,354 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include - -#include "qcom-msm8960.dtsi" - -/ { - model = "Qualcomm MSM8960 CDP"; - compatible = "qcom,msm8960-cdp", "qcom,msm8960"; - - aliases { - serial0 = &gsbi5_serial; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - soc { - gsbi@16400000 { - status = "ok"; - qcom,mode = ; - serial@16440000 { - status = "ok"; - }; - }; - - amba { - /* eMMC */ - sdcc1: sdcc@12400000 { - status = "okay"; - }; - - /* External micro SD card */ - sdcc3: sdcc@12180000 { - status = "okay"; - }; - }; - - rpm@108000 { - regulators { - compatible = "qcom,rpm-pm8921-regulators"; - vin_lvs1_3_6-supply = <&pm8921_s4>; - vin_lvs2-supply = <&pm8921_s4>; - vin_lvs4_5_7-supply = <&pm8921_s4>; - vdd_ncp-supply = <&pm8921_l6>; - vdd_l1_l2_l12_l18-supply = <&pm8921_s4>; - vdd_l21_l23_l29-supply = <&pm8921_s8>; - vdd_l24-supply = <&pm8921_s1>; - vdd_l25-supply = <&pm8921_s1>; - vdd_l27-supply = <&pm8921_s7>; - vdd_l28-supply = <&pm8921_s7>; - - /* Buck SMPS */ - pm8921_s1: s1 { - regulator-always-on; - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - qcom,switch-mode-frequency = <3200000>; - bias-pull-down; - }; - - pm8921_s2: s2 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - qcom,switch-mode-frequency = <1600000>; - bias-pull-down; - }; - - pm8921_s3: s3 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1150000>; - qcom,switch-mode-frequency = <4800000>; - bias-pull-down; - }; - - pm8921_s4: s4 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - qcom,switch-mode-frequency = <1600000>; - bias-pull-down; - qcom,force-mode = ; - }; - - pm8921_s7: s7 { - regulator-min-microvolt = <1150000>; - regulator-max-microvolt = <1150000>; - qcom,switch-mode-frequency = <3200000>; - bias-pull-down; - }; - - pm8921_s8: s8 { - regulator-always-on; - regulator-min-microvolt = <2050000>; - regulator-max-microvolt = <2050000>; - qcom,switch-mode-frequency = <1600000>; - bias-pull-down; - }; - - /* PMOS LDO */ - pm8921_l1: l1 { - regulator-always-on; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - bias-pull-down; - }; - - pm8921_l2: l2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - bias-pull-down; - }; - - pm8921_l3: l3 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3075000>; - bias-pull-down; - }; - - pm8921_l4: l4 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - bias-pull-down; - }; - - pm8921_l5: l5 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - bias-pull-down; - }; - - pm8921_l6: l6 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - bias-pull-down; - }; - - pm8921_l7: l7 { - regulator-always-on; - regulator-min-microvolt = <1850000>; - regulator-max-microvolt = <2950000>; - bias-pull-down; - }; - - pm8921_l8: l8 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <3000000>; - bias-pull-down; - }; - - pm8921_l9: l9 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - bias-pull-down; - }; - - pm8921_l10: l10 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - bias-pull-down; - }; - - pm8921_l11: l11 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - bias-pull-down; - }; - - pm8921_l12: l12 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - bias-pull-down; - }; - - pm8921_l14: l14 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - bias-pull-down; - }; - - pm8921_l15: l15 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - bias-pull-down; - }; - - pm8921_l16: l16 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - bias-pull-down; - }; - - pm8921_l17: l17 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - bias-pull-down; - }; - - pm8921_l18: l18 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - bias-pull-down; - }; - - pm8921_l21: l21 { - regulator-min-microvolt = <1900000>; - regulator-max-microvolt = <1900000>; - bias-pull-down; - }; - - pm8921_l22: l22 { - regulator-min-microvolt = <2750000>; - regulator-max-microvolt = <2750000>; - bias-pull-down; - }; - - pm8921_l23: l23 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - bias-pull-down; - }; - - pm8921_l24: l24 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1150000>; - bias-pull-down; - }; - - pm8921_l25: l25 { - regulator-always-on; - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1250000>; - bias-pull-down; - }; - - /* Low Voltage Switch */ - pm8921_lvs1: lvs1 { - bias-pull-down; - }; - - pm8921_lvs2: lvs2 { - bias-pull-down; - }; - - pm8921_lvs3: lvs3 { - bias-pull-down; - }; - - pm8921_lvs4: lvs4 { - bias-pull-down; - }; - - pm8921_lvs5: lvs5 { - bias-pull-down; - }; - - pm8921_lvs6: lvs6 { - bias-pull-down; - }; - - pm8921_lvs7: lvs7 { - bias-pull-down; - }; - - pm8921_ncp: ncp { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - qcom,switch-mode-frequency = <1600000>; - }; - }; - }; - - gsbi@16000000 { - status = "ok"; - qcom,mode = ; - pinctrl-names = "default"; - pinctrl-0 = <&spi1_default>; - spi@16080000 { - status = "ok"; - eth@0 { - compatible = "micrel,ks8851"; - reg = <0>; - interrupt-parent = <&msmgpio>; - interrupts = <90 8>; - spi-max-frequency = <5400000>; - vdd-supply = <&ext_l2>; - vdd-io-supply = <&pm8921_lvs6>; - reset-gpios = <&msmgpio 89 0>; - }; - }; - }; - - pinctrl@800000 { - spi1_default: spi1_default { - mux { - pins = "gpio6", "gpio7", "gpio9"; - function = "gsbi1"; - }; - - mosi { - pins = "gpio6"; - drive-strength = <12>; - bias-disable; - }; - - miso { - pins = "gpio7"; - drive-strength = <12>; - bias-disable; - }; - - cs { - pins = "gpio8"; - drive-strength = <12>; - bias-disable; - output-low; - }; - - clk { - pins = "gpio9"; - drive-strength = <12>; - bias-disable; - }; - }; - }; - }; - - regulators { - compatible = "simple-bus"; - - ext_l2: gpio-regulator@91 { - compatible = "regulator-fixed"; - regulator-name = "ext_l2"; - gpio = <&msmgpio 91 0>; - startup-delay-us = <10000>; - enable-active-high; - }; - }; -}; - -&pmicintc { - keypad@148 { - linux,keymap = < - MATRIX_KEY(0, 0, KEY_VOLUMEUP) - MATRIX_KEY(0, 1, KEY_VOLUMEDOWN) - MATRIX_KEY(0, 2, KEY_CAMERA_FOCUS) - MATRIX_KEY(0, 3, KEY_CAMERA) - >; - keypad,num-rows = <1>; - keypad,num-columns = <5>; - }; -}; diff --git a/sys/gnu/dts/arm/qcom-msm8960.dtsi b/sys/gnu/dts/arm/qcom-msm8960.dtsi deleted file mode 100644 index f2aeaccdc1a..00000000000 --- a/sys/gnu/dts/arm/qcom-msm8960.dtsi +++ /dev/null @@ -1,330 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - model = "Qualcomm MSM8960"; - compatible = "qcom,msm8960"; - interrupt-parent = <&intc>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - interrupts = <1 14 0x304>; - - cpu@0 { - compatible = "qcom,krait"; - enable-method = "qcom,kpss-acc-v1"; - device_type = "cpu"; - reg = <0>; - next-level-cache = <&L2>; - qcom,acc = <&acc0>; - qcom,saw = <&saw0>; - }; - - cpu@1 { - compatible = "qcom,krait"; - enable-method = "qcom,kpss-acc-v1"; - device_type = "cpu"; - reg = <1>; - next-level-cache = <&L2>; - qcom,acc = <&acc1>; - qcom,saw = <&saw1>; - }; - - L2: l2-cache { - compatible = "cache"; - cache-level = <2>; - }; - }; - - memory { - device_type = "memory"; - reg = <0x0 0x0>; - }; - - cpu-pmu { - compatible = "qcom,krait-pmu"; - interrupts = <1 10 0x304>; - qcom,no-pc-write; - }; - - clocks { - cxo_board { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <19200000>; - clock-output-names = "cxo_board"; - }; - - pxo_board { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <27000000>; - clock-output-names = "pxo_board"; - }; - - sleep_clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "sleep_clk"; - }; - }; - - soc: soc { - #address-cells = <1>; - #size-cells = <1>; - ranges; - compatible = "simple-bus"; - - intc: interrupt-controller@2000000 { - compatible = "qcom,msm-qgic2"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0x02000000 0x1000>, - <0x02002000 0x1000>; - }; - - timer@200a000 { - compatible = "qcom,kpss-timer", - "qcom,kpss-wdt-msm8960", "qcom,msm-timer"; - interrupts = <1 1 0x301>, - <1 2 0x301>, - <1 3 0x301>; - reg = <0x0200a000 0x100>; - clock-frequency = <27000000>, - <32768>; - cpu-offset = <0x80000>; - }; - - msmgpio: pinctrl@800000 { - compatible = "qcom,msm8960-pinctrl"; - gpio-controller; - #gpio-cells = <2>; - interrupts = <0 16 0x4>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x800000 0x4000>; - }; - - gcc: clock-controller@900000 { - compatible = "qcom,gcc-msm8960"; - #clock-cells = <1>; - #reset-cells = <1>; - reg = <0x900000 0x4000>; - }; - - lcc: clock-controller@28000000 { - compatible = "qcom,lcc-msm8960"; - reg = <0x28000000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - clock-controller@4000000 { - compatible = "qcom,mmcc-msm8960"; - reg = <0x4000000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - l2cc: clock-controller@2011000 { - compatible = "syscon"; - reg = <0x2011000 0x1000>; - }; - - rpm@108000 { - compatible = "qcom,rpm-msm8960"; - reg = <0x108000 0x1000>; - qcom,ipc = <&l2cc 0x8 2>; - - interrupts = <0 19 0>, <0 21 0>, <0 22 0>; - interrupt-names = "ack", "err", "wakeup"; - - regulators { - compatible = "qcom,rpm-pm8921-regulators"; - }; - }; - - acc0: clock-controller@2088000 { - compatible = "qcom,kpss-acc-v1"; - reg = <0x02088000 0x1000>, <0x02008000 0x1000>; - }; - - acc1: clock-controller@2098000 { - compatible = "qcom,kpss-acc-v1"; - reg = <0x02098000 0x1000>, <0x02008000 0x1000>; - }; - - saw0: regulator@2089000 { - compatible = "qcom,saw2"; - reg = <0x02089000 0x1000>, <0x02009000 0x1000>; - regulator; - }; - - saw1: regulator@2099000 { - compatible = "qcom,saw2"; - reg = <0x02099000 0x1000>, <0x02009000 0x1000>; - regulator; - }; - - gsbi5: gsbi@16400000 { - compatible = "qcom,gsbi-v1.0.0"; - cell-index = <5>; - reg = <0x16400000 0x100>; - clocks = <&gcc GSBI5_H_CLK>; - clock-names = "iface"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - syscon-tcsr = <&tcsr>; - - gsbi5_serial: serial@16440000 { - compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; - reg = <0x16440000 0x1000>, - <0x16400000 0x1000>; - interrupts = <0 154 0x0>; - clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - }; - - qcom,ssbi@500000 { - compatible = "qcom,ssbi"; - reg = <0x500000 0x1000>; - qcom,controller-type = "pmic-arbiter"; - - pmicintc: pmic@0 { - compatible = "qcom,pm8921"; - interrupt-parent = <&msmgpio>; - interrupts = <104 8>; - #interrupt-cells = <2>; - interrupt-controller; - #address-cells = <1>; - #size-cells = <0>; - - pwrkey@1c { - compatible = "qcom,pm8921-pwrkey"; - reg = <0x1c>; - interrupt-parent = <&pmicintc>; - interrupts = <50 1>, <51 1>; - debounce = <15625>; - pull-up; - }; - - keypad@148 { - compatible = "qcom,pm8921-keypad"; - reg = <0x148>; - interrupt-parent = <&pmicintc>; - interrupts = <74 1>, <75 1>; - debounce = <15>; - scan-delay = <32>; - row-hold = <91500>; - }; - - rtc@11d { - compatible = "qcom,pm8921-rtc"; - interrupt-parent = <&pmicintc>; - interrupts = <39 1>; - reg = <0x11d>; - allow-set-time; - }; - }; - }; - - rng@1a500000 { - compatible = "qcom,prng"; - reg = <0x1a500000 0x200>; - clocks = <&gcc PRNG_CLK>; - clock-names = "core"; - }; - - /* Temporary fixed regulator */ - vsdcc_fixed: vsdcc-regulator { - compatible = "regulator-fixed"; - regulator-name = "SDCC Power"; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - regulator-always-on; - }; - - amba { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - sdcc1: sdcc@12400000 { - status = "disabled"; - compatible = "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x00051180>; - reg = <0x12400000 0x8000>; - interrupts = ; - interrupt-names = "cmd_irq"; - clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <8>; - max-frequency = <96000000>; - non-removable; - cap-sd-highspeed; - cap-mmc-highspeed; - vmmc-supply = <&vsdcc_fixed>; - }; - - sdcc3: sdcc@12180000 { - compatible = "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x00051180>; - status = "disabled"; - reg = <0x12180000 0x8000>; - interrupts = ; - interrupt-names = "cmd_irq"; - clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <4>; - cap-sd-highspeed; - cap-mmc-highspeed; - max-frequency = <192000000>; - no-1-8-v; - vmmc-supply = <&vsdcc_fixed>; - }; - }; - - tcsr: syscon@1a400000 { - compatible = "qcom,tcsr-msm8960", "syscon"; - reg = <0x1a400000 0x100>; - }; - - gsbi@16000000 { - compatible = "qcom,gsbi-v1.0.0"; - cell-index = <1>; - reg = <0x16000000 0x100>; - clocks = <&gcc GSBI1_H_CLK>; - clock-names = "iface"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - spi@16080000 { - compatible = "qcom,spi-qup-v1.1.1"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x16080000 0x1000>; - interrupts = <0 147 0>; - spi-max-frequency = <24000000>; - cs-gpios = <&msmgpio 8 0>; - - clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/qcom-msm8974-fairphone-fp2.dts b/sys/gnu/dts/arm/qcom-msm8974-fairphone-fp2.dts deleted file mode 100644 index d2d48770ec0..00000000000 --- a/sys/gnu/dts/arm/qcom-msm8974-fairphone-fp2.dts +++ /dev/null @@ -1,410 +0,0 @@ -#include "qcom-msm8974.dtsi" -#include "qcom-pm8841.dtsi" -#include "qcom-pm8941.dtsi" -#include -#include -#include - - -/ { - model = "Fairphone 2"; - compatible = "fairphone,fp2", "qcom,msm8974"; - - aliases { - serial0 = &blsp1_uart2; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - gpio-keys { - compatible = "gpio-keys"; - input-name = "gpio-keys"; - - pinctrl-names = "default"; - pinctrl-0 = <&gpio_keys_pin_a>; - - camera-snapshot { - label = "camera_snapshot"; - gpios = <&pm8941_gpios 1 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - debounce-interval = <15>; - }; - - volume-down { - label = "volume_down"; - gpios = <&pm8941_gpios 2 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - debounce-interval = <15>; - }; - - volume-up { - label = "volume_up"; - gpios = <&pm8941_gpios 5 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - debounce-interval = <15>; - }; - }; - - vibrator { - compatible = "gpio-vibrator"; - enable-gpios = <&msmgpio 86 GPIO_ACTIVE_HIGH>; - vcc-supply = <&pm8941_l18>; - }; - - smd { - rpm { - rpm_requests { - pm8841-regulators { - s1 { - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <1050000>; - }; - - s2 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1050000>; - }; - - s3 { - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - }; - }; - - pm8941-regulators { - vdd_l1_l3-supply = <&pm8941_s1>; - vdd_l2_lvs1_2_3-supply = <&pm8941_s3>; - vdd_l4_l11-supply = <&pm8941_s1>; - vdd_l5_l7-supply = <&pm8941_s2>; - vdd_l6_l12_l14_l15-supply = <&pm8941_s2>; - vdd_l9_l10_l17_l22-supply = <&vreg_boost>; - vdd_l13_l20_l23_l24-supply = <&vreg_boost>; - vdd_l21-supply = <&vreg_boost>; - - s1 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - - regulator-always-on; - regulator-boot-on; - }; - - s2 { - regulator-min-microvolt = <2150000>; - regulator-max-microvolt = <2150000>; - - regulator-boot-on; - }; - - s3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-always-on; - regulator-boot-on; - }; - - l1 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - - regulator-always-on; - regulator-boot-on; - }; - - l2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - l3 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - - l4 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - - l5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-boot-on; - }; - - l7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-boot-on; - }; - - l8 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l9 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - l10 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - l11 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1350000>; - }; - - l12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-always-on; - regulator-boot-on; - }; - - l13 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - - regulator-boot-on; - }; - - l14 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l15 { - regulator-min-microvolt = <2050000>; - regulator-max-microvolt = <2050000>; - }; - - l16 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; - - l17 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - l18 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - l19 { - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <3350000>; - }; - - l20 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - - regulator-boot-on; - regulator-system-load = <200000>; - regulator-allow-set-load; - }; - - l21 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - - regulator-boot-on; - }; - - l22 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - }; - - l23 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - l24 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3075000>; - - regulator-boot-on; - }; - }; - }; - }; - }; -}; - -&soc { - serial@f991e000 { - status = "ok"; - }; - - remoteproc@fb21b000 { - status = "ok"; - - vddmx-supply = <&pm8841_s1>; - vddcx-supply = <&pm8841_s2>; - - pinctrl-names = "default"; - pinctrl-0 = <&wcnss_pin_a>; - - smd-edge { - qcom,remote-pid = <4>; - label = "pronto"; - - wcnss { - status = "ok"; - }; - }; - }; - - pinctrl@fd510000 { - sdhc1_pin_a: sdhc1-pin-active { - clk { - pins = "sdc1_clk"; - drive-strength = <16>; - bias-disable; - }; - - cmd-data { - pins = "sdc1_cmd", "sdc1_data"; - drive-strength = <10>; - bias-pull-up; - }; - }; - - sdhc2_pin_a: sdhc2-pin-active { - clk { - pins = "sdc2_clk"; - drive-strength = <10>; - bias-disable; - }; - - cmd-data { - pins = "sdc2_cmd", "sdc2_data"; - drive-strength = <6>; - bias-pull-up; - }; - }; - - wcnss_pin_a: wcnss-pin-active { - wlan { - pins = "gpio36", "gpio37", "gpio38", "gpio39", "gpio40"; - function = "wlan"; - - drive-strength = <6>; - bias-pull-down; - }; - - bt { - pins = "gpio35", "gpio43", "gpio44"; - function = "bt"; - - drive-strength = <2>; - bias-pull-down; - }; - - fm { - pins = "gpio41", "gpio42"; - function = "fm"; - - drive-strength = <2>; - bias-pull-down; - }; - }; - }; - - sdhci@f9824900 { - status = "ok"; - - vmmc-supply = <&pm8941_l20>; - vqmmc-supply = <&pm8941_s3>; - - bus-width = <8>; - non-removable; - - pinctrl-names = "default"; - pinctrl-0 = <&sdhc1_pin_a>; - }; - - sdhci@f98a4900 { - status = "ok"; - - vmmc-supply = <&pm8941_l21>; - vqmmc-supply = <&pm8941_l13>; - - bus-width = <4>; - - pinctrl-names = "default"; - pinctrl-0 = <&sdhc2_pin_a>; - }; - - usb@f9a55000 { - status = "ok"; - - phys = <&usb_hs1_phy>; - phy-select = <&tcsr 0xb000 0>; - extcon = <&smbb>, <&usb_id>; - vbus-supply = <&chg_otg>; - - hnp-disable; - srp-disable; - adp-disable; - - ulpi { - phy@a { - status = "ok"; - - v1p8-supply = <&pm8941_l6>; - v3p3-supply = <&pm8941_l24>; - - extcon = <&smbb>; - qcom,init-seq = /bits/ 8 <0x1 0x64>; - }; - }; - }; - - imem@fe805000 { - status = "okay"; - - reboot-mode { - mode-normal = <0x77665501>; - mode-bootloader = <0x77665500>; - mode-recovery = <0x77665502>; - }; - }; -}; - -&spmi_bus { - pm8941@0 { - gpios@c000 { - gpio_keys_pin_a: gpio-keys-active { - pins = "gpio1", "gpio2", "gpio5"; - function = "normal"; - - bias-pull-up; - power-source = ; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/qcom-msm8974-lge-nexus5-hammerhead.dts b/sys/gnu/dts/arm/qcom-msm8974-lge-nexus5-hammerhead.dts deleted file mode 100644 index 3487daf98e8..00000000000 --- a/sys/gnu/dts/arm/qcom-msm8974-lge-nexus5-hammerhead.dts +++ /dev/null @@ -1,662 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "qcom-msm8974.dtsi" -#include "qcom-pm8841.dtsi" -#include "qcom-pm8941.dtsi" -#include -#include -#include - -/ { - model = "LGE MSM 8974 HAMMERHEAD"; - compatible = "lge,hammerhead", "qcom,msm8974"; - - aliases { - serial0 = &blsp1_uart1; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - smd { - rpm { - rpm_requests { - pm8841-regulators { - s1 { - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <1050000>; - }; - - s2 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1050000>; - }; - - s3 { - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - }; - - s4 { - regulator-min-microvolt = <815000>; - regulator-max-microvolt = <900000>; - }; - }; - - pm8941-regulators { - vdd_l1_l3-supply = <&pm8941_s1>; - vdd_l2_lvs1_2_3-supply = <&pm8941_s3>; - vdd_l4_l11-supply = <&pm8941_s1>; - vdd_l5_l7-supply = <&pm8941_s2>; - vdd_l6_l12_l14_l15-supply = <&pm8941_s2>; - vdd_l8_l16_l18_l19-supply = <&vreg_vph_pwr>; - vdd_l9_l10_l17_l22-supply = <&vreg_boost>; - vdd_l13_l20_l23_l24-supply = <&vreg_boost>; - vdd_l21-supply = <&vreg_boost>; - - s1 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - - regulator-always-on; - regulator-boot-on; - }; - - s2 { - regulator-min-microvolt = <2150000>; - regulator-max-microvolt = <2150000>; - - regulator-boot-on; - }; - - s3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-always-on; - regulator-boot-on; - }; - - l1 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - - regulator-always-on; - regulator-boot-on; - }; - - l2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - l3 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - - l4 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - - l5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-boot-on; - }; - - l7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-boot-on; - }; - - l8 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l9 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - l10 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - l11 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - }; - - l12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-always-on; - regulator-boot-on; - }; - - l13 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - - regulator-boot-on; - }; - - l14 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l15 { - regulator-min-microvolt = <2050000>; - regulator-max-microvolt = <2050000>; - }; - - l16 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; - - l17 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - l18 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - l19 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - }; - - l20 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - - regulator-boot-on; - regulator-system-load = <200000>; - regulator-allow-set-load; - }; - - l21 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - - regulator-boot-on; - }; - - l22 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - }; - - l23 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - l24 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3075000>; - - regulator-boot-on; - }; - }; - }; - }; - }; - - vreg_wlan: wlan-regulator { - compatible = "regulator-fixed"; - - regulator-name = "wl-reg"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&msmgpio 26 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-names = "default"; - pinctrl-0 = <&wlan_regulator_pin>; - }; -}; - -&soc { - serial@f991d000 { - status = "ok"; - }; - - pinctrl@fd510000 { - sdhc1_pin_a: sdhc1-pin-active { - clk { - pins = "sdc1_clk"; - drive-strength = <16>; - bias-disable; - }; - - cmd-data { - pins = "sdc1_cmd", "sdc1_data"; - drive-strength = <10>; - bias-pull-up; - }; - }; - - sdhc2_pin_a: sdhc2-pin-active { - clk { - pins = "sdc2_clk"; - drive-strength = <6>; - bias-disable; - }; - - cmd-data { - pins = "sdc2_cmd", "sdc2_data"; - drive-strength = <6>; - bias-pull-up; - }; - }; - - i2c1_pins: i2c1 { - mux { - pins = "gpio2", "gpio3"; - function = "blsp_i2c1"; - - drive-strength = <2>; - bias-disable; - }; - }; - - i2c2_pins: i2c2 { - mux { - pins = "gpio6", "gpio7"; - function = "blsp_i2c2"; - - drive-strength = <2>; - bias-disable; - }; - }; - - i2c3_pins: i2c3 { - mux { - pins = "gpio10", "gpio11"; - function = "blsp_i2c3"; - drive-strength = <2>; - bias-disable; - }; - }; - - i2c11_pins: i2c11 { - mux { - pins = "gpio83", "gpio84"; - function = "blsp_i2c11"; - - drive-strength = <2>; - bias-disable; - }; - }; - - i2c12_pins: i2c12 { - mux { - pins = "gpio87", "gpio88"; - function = "blsp_i2c12"; - drive-strength = <2>; - bias-disable; - }; - }; - - mpu6515_pin: mpu6515 { - irq { - pins = "gpio73"; - function = "gpio"; - bias-disable; - input-enable; - }; - }; - - touch_pin: touch { - int { - pins = "gpio5"; - function = "gpio"; - - drive-strength = <2>; - bias-disable; - input-enable; - }; - - reset { - pins = "gpio8"; - function = "gpio"; - - drive-strength = <2>; - bias-pull-up; - }; - }; - - panel_pin: panel { - te { - pins = "gpio12"; - function = "mdp_vsync"; - - drive-strength = <2>; - bias-disable; - }; - }; - }; - - sdhci@f9824900 { - status = "ok"; - - vmmc-supply = <&pm8941_l20>; - vqmmc-supply = <&pm8941_s3>; - - bus-width = <8>; - non-removable; - - pinctrl-names = "default"; - pinctrl-0 = <&sdhc1_pin_a>; - }; - - sdhci@f98a4900 { - status = "ok"; - - max-frequency = <100000000>; - bus-width = <4>; - non-removable; - vmmc-supply = <&vreg_wlan>; - vqmmc-supply = <&pm8941_s3>; - - pinctrl-names = "default"; - pinctrl-0 = <&sdhc2_pin_a>; - - #address-cells = <1>; - #size-cells = <0>; - - bcrmf@1 { - compatible = "brcm,bcm4339-fmac", "brcm,bcm4329-fmac"; - reg = <1>; - - brcm,drive-strength = <10>; - - pinctrl-names = "default"; - pinctrl-0 = <&wlan_sleep_clk_pin>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - input-name = "gpio-keys"; - - pinctrl-names = "default"; - pinctrl-0 = <&gpio_keys_pin_a>; - - volume-up { - label = "volume_up"; - gpios = <&pm8941_gpios 2 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - linux,code = ; - }; - - volume-down { - label = "volume_down"; - gpios = <&pm8941_gpios 3 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - linux,code = ; - }; - }; - - i2c@f9967000 { - status = "ok"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c11_pins>; - clock-frequency = <355000>; - qcom,src-freq = <50000000>; - - led-controller@38 { - compatible = "ti,lm3630a"; - status = "ok"; - reg = <0x38>; - - #address-cells = <1>; - #size-cells = <0>; - - led@0 { - reg = <0>; - led-sources = <0 1>; - label = "lcd-backlight"; - default-brightness = <200>; - }; - }; - }; - - i2c@f9968000 { - status = "ok"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c12_pins>; - clock-frequency = <100000>; - qcom,src-freq = <50000000>; - - mpu6515@68 { - compatible = "invensense,mpu6515"; - reg = <0x68>; - interrupts-extended = <&msmgpio 73 IRQ_TYPE_EDGE_FALLING>; - vddio-supply = <&pm8941_lvs1>; - - pinctrl-names = "default"; - pinctrl-0 = <&mpu6515_pin>; - - i2c-gate { - #address-cells = <1>; - #size-cells = <0>; - ak8963@f { - compatible = "asahi-kasei,ak8963"; - reg = <0x0f>; - gpios = <&msmgpio 67 0>; - vid-supply = <&pm8941_lvs1>; - vdd-supply = <&pm8941_l17>; - }; - - bmp280@76 { - compatible = "bosch,bmp280"; - reg = <0x76>; - vdda-supply = <&pm8941_lvs1>; - vddd-supply = <&pm8941_l17>; - }; - }; - }; - }; - - i2c@f9923000 { - status = "ok"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - clock-frequency = <100000>; - qcom,src-freq = <50000000>; - - charger: bq24192@6b { - compatible = "ti,bq24192"; - reg = <0x6b>; - interrupts-extended = <&spmi_bus 0 0xd5 0 IRQ_TYPE_EDGE_FALLING>; - - omit-battery-class; - - usb_otg_vbus: usb-otg-vbus { }; - }; - }; - - i2c@f9924000 { - status = "ok"; - - clock-frequency = <355000>; - qcom,src-freq = <50000000>; - - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - - synaptics@70 { - compatible = "syna,rmi4-i2c"; - reg = <0x70>; - - interrupts-extended = <&msmgpio 5 IRQ_TYPE_EDGE_FALLING>; - vdd-supply = <&pm8941_l22>; - vio-supply = <&pm8941_lvs3>; - - pinctrl-names = "default"; - pinctrl-0 = <&touch_pin>; - - #address-cells = <1>; - #size-cells = <0>; - - rmi4-f01@1 { - reg = <0x1>; - syna,nosleep-mode = <1>; - }; - - rmi4-f12@12 { - reg = <0x12>; - syna,sensor-type = <1>; - }; - }; - }; - - i2c@f9925000 { - status = "ok"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_pins>; - clock-frequency = <100000>; - qcom,src-freq = <50000000>; - - avago_apds993@39 { - compatible = "avago,apds9930"; - reg = <0x39>; - interrupts-extended = <&msmgpio 61 IRQ_TYPE_EDGE_FALLING>; - vdd-supply = <&pm8941_l17>; - vddio-supply = <&pm8941_lvs1>; - led-max-microamp = <100000>; - amstaos,proximity-diodes = <0>; - }; - }; - - usb@f9a55000 { - status = "ok"; - - phys = <&usb_hs1_phy>; - phy-select = <&tcsr 0xb000 0>; - - extcon = <&charger>, <&usb_id>; - vbus-supply = <&usb_otg_vbus>; - - hnp-disable; - srp-disable; - adp-disable; - - ulpi { - phy@a { - status = "ok"; - - v1p8-supply = <&pm8941_l6>; - v3p3-supply = <&pm8941_l24>; - - qcom,init-seq = /bits/ 8 <0x1 0x64>; - }; - }; - }; - - mdss@fd900000 { - status = "ok"; - - mdp@fd900000 { - status = "ok"; - }; - - dsi@fd922800 { - status = "ok"; - - vdda-supply = <&pm8941_l2>; - vdd-supply = <&pm8941_lvs3>; - vddio-supply = <&pm8941_l12>; - - #address-cells = <1>; - #size-cells = <0>; - - ports { - port@1 { - endpoint { - remote-endpoint = <&panel_in>; - data-lanes = <0 1 2 3>; - }; - }; - }; - - panel: panel@0 { - reg = <0>; - compatible = "lg,acx467akm-7"; - - pinctrl-names = "default"; - pinctrl-0 = <&panel_pin>; - - port { - panel_in: endpoint { - remote-endpoint = <&dsi0_out>; - }; - }; - }; - }; - - dsi-phy@fd922a00 { - status = "ok"; - - vddio-supply = <&pm8941_l12>; - }; - }; -}; - -&spmi_bus { - pm8941@0 { - gpios@c000 { - gpio_keys_pin_a: gpio-keys-active { - pins = "gpio2", "gpio3"; - function = "normal"; - - bias-pull-up; - power-source = ; - }; - - wlan_sleep_clk_pin: wl-sleep-clk { - pins = "gpio16"; - function = "func2"; - - output-high; - power-source = ; - }; - - wlan_regulator_pin: wl-reg-active { - pins = "gpio17"; - function = "normal"; - - bias-disable; - power-source = ; - }; - - otg { - gpio-hog; - gpios = <35 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "otg-gpio"; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/qcom-msm8974-samsung-klte.dts b/sys/gnu/dts/arm/qcom-msm8974-samsung-klte.dts deleted file mode 100644 index eaa1001d0a4..00000000000 --- a/sys/gnu/dts/arm/qcom-msm8974-samsung-klte.dts +++ /dev/null @@ -1,24 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "qcom-msm8974pro.dtsi" -#include "qcom-pm8841.dtsi" -#include "qcom-pm8941.dtsi" - -/ { - model = "Samsung Galaxy S5"; - compatible = "samsung,klte", "qcom,msm8974"; - - aliases { - serial0 = &blsp1_uart1; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&soc { - serial@f991e000 { - status = "ok"; - }; - -}; diff --git a/sys/gnu/dts/arm/qcom-msm8974-sony-xperia-amami.dts b/sys/gnu/dts/arm/qcom-msm8974-sony-xperia-amami.dts deleted file mode 100644 index 5669f5f58a8..00000000000 --- a/sys/gnu/dts/arm/qcom-msm8974-sony-xperia-amami.dts +++ /dev/null @@ -1,436 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "qcom-msm8974.dtsi" -#include "qcom-pm8841.dtsi" -#include "qcom-pm8941.dtsi" -#include -#include -#include - -/ { - model = "Sony Xperia Z1 Compact"; - compatible = "sony,xperia-amami", "qcom,msm8974"; - - aliases { - serial0 = &blsp1_uart2; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - gpio-keys { - compatible = "gpio-keys"; - input-name = "gpio-keys"; - - pinctrl-names = "default"; - pinctrl-0 = <&gpio_keys_pin_a>; - - volume-down { - label = "volume_down"; - gpios = <&pm8941_gpios 2 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - linux,code = ; - }; - - camera-snapshot { - label = "camera_snapshot"; - gpios = <&pm8941_gpios 3 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - linux,code = ; - }; - - camera-focus { - label = "camera_focus"; - gpios = <&pm8941_gpios 4 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - linux,code = ; - }; - - volume-up { - label = "volume_up"; - gpios = <&pm8941_gpios 5 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - linux,code = ; - }; - }; - - memory@0 { - reg = <0 0x40000000>, <0x40000000 0x40000000>; - device_type = "memory"; - }; - - smd { - rpm { - rpm_requests { - pm8841-regulators { - s1 { - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <1050000>; - }; - - s2 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1050000>; - }; - - s3 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1050000>; - }; - - s4 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1050000>; - }; - }; - - pm8941-regulators { - vdd_l1_l3-supply = <&pm8941_s1>; - vdd_l2_lvs1_2_3-supply = <&pm8941_s3>; - vdd_l4_l11-supply = <&pm8941_s1>; - vdd_l5_l7-supply = <&pm8941_s2>; - vdd_l6_l12_l14_l15-supply = <&pm8941_s2>; - vdd_l9_l10_l17_l22-supply = <&vreg_boost>; - vdd_l13_l20_l23_l24-supply = <&vreg_boost>; - vdd_l21-supply = <&vreg_boost>; - - s1 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - }; - - s2 { - regulator-min-microvolt = <2150000>; - regulator-max-microvolt = <2150000>; - regulator-boot-on; - }; - - s3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - s4 { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - l1 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - - regulator-always-on; - regulator-boot-on; - }; - - l2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - l3 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - l4 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - - l5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-boot-on; - }; - - l7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-boot-on; - }; - - l8 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l9 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - l11 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1350000>; - }; - - l12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-always-on; - regulator-boot-on; - }; - - l13 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - - regulator-boot-on; - }; - - l14 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l15 { - regulator-min-microvolt = <2050000>; - regulator-max-microvolt = <2050000>; - }; - - l16 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; - - l17 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; - - l18 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - l19 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - l20 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - - regulator-allow-set-load; - regulator-boot-on; - regulator-system-load = <200000>; - }; - - l21 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - - regulator-boot-on; - }; - - l22 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - l23 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - l24 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3075000>; - - regulator-boot-on; - }; - }; - }; - }; - }; -}; - -&soc { - sdhci@f9824900 { - status = "ok"; - - vmmc-supply = <&pm8941_l20>; - vqmmc-supply = <&pm8941_s3>; - - bus-width = <8>; - non-removable; - - pinctrl-names = "default"; - pinctrl-0 = <&sdhc1_pin_a>; - }; - - sdhci@f98a4900 { - status = "ok"; - - bus-width = <4>; - - vmmc-supply = <&pm8941_l21>; - vqmmc-supply = <&pm8941_l13>; - - cd-gpios = <&msmgpio 62 GPIO_ACTIVE_LOW>; - - pinctrl-names = "default"; - pinctrl-0 = <&sdhc2_pin_a>, <&sdhc2_cd_pin_a>; - }; - - serial@f991e000 { - status = "ok"; - - pinctrl-names = "default"; - pinctrl-0 = <&blsp1_uart2_pin_a>; - }; - - - pinctrl@fd510000 { - blsp1_uart2_pin_a: blsp1-uart2-pin-active { - rx { - pins = "gpio5"; - function = "blsp_uart2"; - - drive-strength = <2>; - bias-pull-up; - }; - - tx { - pins = "gpio4"; - function = "blsp_uart2"; - - drive-strength = <4>; - bias-disable; - }; - }; - - i2c2_pins: i2c2 { - mux { - pins = "gpio6", "gpio7"; - function = "blsp_i2c2"; - - drive-strength = <2>; - bias-disable; - }; - }; - - sdhc1_pin_a: sdhc1-pin-active { - clk { - pins = "sdc1_clk"; - drive-strength = <16>; - bias-disable; - }; - - cmd-data { - pins = "sdc1_cmd", "sdc1_data"; - drive-strength = <10>; - bias-pull-up; - }; - }; - - sdhc2_cd_pin_a: sdhc2-cd-pin-active { - pins = "gpio62"; - function = "gpio"; - - drive-strength = <2>; - bias-disable; - }; - - sdhc2_pin_a: sdhc2-pin-active { - clk { - pins = "sdc2_clk"; - drive-strength = <10>; - bias-disable; - }; - - cmd-data { - pins = "sdc2_cmd", "sdc2_data"; - drive-strength = <6>; - bias-pull-up; - }; - }; - }; - - dma-controller@f9944000 { - qcom,controlled-remotely; - }; - - usb@f9a55000 { - status = "ok"; - - phys = <&usb_hs1_phy>; - phy-select = <&tcsr 0xb000 0>; - extcon = <&smbb>, <&usb_id>; - vbus-supply = <&chg_otg>; - - hnp-disable; - srp-disable; - adp-disable; - - ulpi { - phy@a { - status = "ok"; - - v1p8-supply = <&pm8941_l6>; - v3p3-supply = <&pm8941_l24>; - - extcon = <&smbb>; - qcom,init-seq = /bits/ 8 <0x1 0x64>; - }; - }; - }; -}; - -&spmi_bus { - pm8941@0 { - charger@1000 { - qcom,fast-charge-safe-current = <1300000>; - qcom,fast-charge-current-limit = <1300000>; - qcom,dc-current-limit = <1300000>; - qcom,fast-charge-safe-voltage = <4400000>; - qcom,fast-charge-high-threshold-voltage = <4350000>; - qcom,fast-charge-low-threshold-voltage = <3400000>; - qcom,auto-recharge-threshold-voltage = <4200000>; - qcom,minimum-input-voltage = <4300000>; - }; - - gpios@c000 { - gpio_keys_pin_a: gpio-keys-active { - pins = "gpio2", "gpio3", "gpio4", "gpio5"; - function = "normal"; - - bias-pull-up; - power-source = ; - }; - }; - - coincell@2800 { - status = "ok"; - qcom,rset-ohms = <2100>; - qcom,vset-millivolts = <3000>; - }; - }; - - pm8941@1 { - wled@d800 { - status = "ok"; - - qcom,cs-out; - qcom,current-limit = <20>; - qcom,current-boost-limit = <805>; - qcom,switching-freq = <1600>; - qcom,ovp = <29>; - qcom,num-strings = <2>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/qcom-msm8974-sony-xperia-castor.dts b/sys/gnu/dts/arm/qcom-msm8974-sony-xperia-castor.dts deleted file mode 100644 index 701b396719c..00000000000 --- a/sys/gnu/dts/arm/qcom-msm8974-sony-xperia-castor.dts +++ /dev/null @@ -1,643 +0,0 @@ -#include "qcom-msm8974pro.dtsi" -#include "qcom-pm8841.dtsi" -#include "qcom-pm8941.dtsi" -#include -#include -#include - -/ { - model = "Sony Xperia Z2 Tablet"; - compatible = "sony,xperia-castor", "qcom,msm8974"; - - aliases { - serial0 = &blsp1_uart2; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - gpio-keys { - compatible = "gpio-keys"; - input-name = "gpio-keys"; - - pinctrl-names = "default"; - pinctrl-0 = <&gpio_keys_pin_a>; - - volume-down { - label = "volume_down"; - gpios = <&pm8941_gpios 2 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - linux,code = ; - }; - - camera-snapshot { - label = "camera_snapshot"; - gpios = <&pm8941_gpios 3 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - linux,code = ; - }; - - camera-focus { - label = "camera_focus"; - gpios = <&pm8941_gpios 4 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - linux,code = ; - }; - - volume-up { - label = "volume_up"; - gpios = <&pm8941_gpios 5 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - linux,code = ; - }; - }; - - smd { - rpm { - rpm_requests { - pm8941-regulators { - vdd_l1_l3-supply = <&pm8941_s1>; - vdd_l2_lvs1_2_3-supply = <&pm8941_s3>; - vdd_l4_l11-supply = <&pm8941_s1>; - vdd_l5_l7-supply = <&pm8941_s2>; - vdd_l6_l12_l14_l15-supply = <&pm8941_s2>; - vdd_l9_l10_l17_l22-supply = <&vreg_boost>; - vdd_l13_l20_l23_l24-supply = <&vreg_boost>; - vdd_l21-supply = <&vreg_boost>; - - s1 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - }; - - s2 { - regulator-min-microvolt = <2150000>; - regulator-max-microvolt = <2150000>; - regulator-boot-on; - }; - - s3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - - regulator-system-load = <154000>; - }; - - s4 { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - l1 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - - regulator-always-on; - regulator-boot-on; - }; - - l2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - l3 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - l4 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - - l5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-boot-on; - }; - - l7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-boot-on; - }; - - l8 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l9 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - l11 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1350000>; - }; - - l12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-always-on; - regulator-boot-on; - }; - - l13 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - - regulator-boot-on; - }; - - l14 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l15 { - regulator-min-microvolt = <2050000>; - regulator-max-microvolt = <2050000>; - }; - - l16 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; - - l17 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; - - l18 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - l19 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - l20 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - - regulator-allow-set-load; - regulator-boot-on; - regulator-allow-set-load; - regulator-system-load = <500000>; - }; - - l21 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - - regulator-boot-on; - }; - - l22 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - l23 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - l24 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3075000>; - - regulator-boot-on; - }; - }; - }; - }; - }; - - vreg_bl_vddio: lcd-backlight-vddio { - compatible = "regulator-fixed"; - regulator-name = "vreg_bl_vddio"; - regulator-min-microvolt = <3150000>; - regulator-max-microvolt = <3150000>; - - gpio = <&msmgpio 69 0>; - enable-active-high; - - vin-supply = <&pm8941_s3>; - startup-delay-us = <70000>; - - pinctrl-names = "default"; - pinctrl-0 = <&lcd_backlight_en_pin_a>; - }; - - vreg_vsp: lcd-dcdc-regulator { - compatible = "regulator-fixed"; - regulator-name = "vreg_vsp"; - regulator-min-microvolt = <5600000>; - regulator-max-microvolt = <5600000>; - - gpio = <&pm8941_gpios 20 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-names = "default"; - pinctrl-0 = <&lcd_dcdc_en_pin_a>; - }; - - vreg_wlan: wlan-regulator { - compatible = "regulator-fixed"; - - regulator-name = "wl-reg"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&pm8941_gpios 18 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-names = "default"; - pinctrl-0 = <&wlan_regulator_pin>; - }; -}; - -&soc { - sdhci@f9824900 { - status = "ok"; - - vmmc-supply = <&pm8941_l20>; - vqmmc-supply = <&pm8941_s3>; - - bus-width = <8>; - non-removable; - - pinctrl-names = "default"; - pinctrl-0 = <&sdhc1_pin_a>; - }; - - sdhci@f9864900 { - status = "ok"; - - max-frequency = <100000000>; - non-removable; - vmmc-supply = <&vreg_wlan>; - - pinctrl-names = "default"; - pinctrl-0 = <&sdhc3_pin_a>; - - #address-cells = <1>; - #size-cells = <0>; - - bcrmf@1 { - compatible = "brcm,bcm4339-fmac", "brcm,bcm4329-fmac"; - reg = <1>; - - brcm,drive-strength = <10>; - - pinctrl-names = "default"; - pinctrl-0 = <&wlan_sleep_clk_pin>; - }; - }; - - sdhci@f98a4900 { - status = "ok"; - - bus-width = <4>; - - vmmc-supply = <&pm8941_l21>; - vqmmc-supply = <&pm8941_l13>; - - cd-gpios = <&msmgpio 62 GPIO_ACTIVE_LOW>; - - pinctrl-names = "default"; - pinctrl-0 = <&sdhc2_pin_a>, <&sdhc2_cd_pin_a>; - }; - - serial@f991e000 { - status = "ok"; - - pinctrl-names = "default"; - pinctrl-0 = <&blsp1_uart2_pin_a>; - }; - - usb@f9a55000 { - status = "ok"; - - phys = <&usb_hs1_phy>; - phy-select = <&tcsr 0xb000 0>; - extcon = <&smbb>, <&usb_id>; - vbus-supply = <&chg_otg>; - - hnp-disable; - srp-disable; - adp-disable; - - ulpi { - phy@a { - status = "ok"; - - v1p8-supply = <&pm8941_l6>; - v3p3-supply = <&pm8941_l24>; - - extcon = <&smbb>; - qcom,init-seq = /bits/ 8 <0x1 0x64>; - }; - }; - }; - - pinctrl@fd510000 { - blsp1_uart2_pin_a: blsp1-uart2-pin-active { - rx { - pins = "gpio5"; - function = "blsp_uart2"; - - drive-strength = <2>; - bias-pull-up; - }; - - tx { - pins = "gpio4"; - function = "blsp_uart2"; - - drive-strength = <4>; - bias-disable; - }; - }; - - i2c8_pins: i2c8 { - mux { - pins = "gpio47", "gpio48"; - function = "blsp_i2c8"; - - drive-strength = <2>; - bias-disable; - }; - }; - - i2c11_pins: i2c11 { - mux { - pins = "gpio83", "gpio84"; - function = "blsp_i2c11"; - - drive-strength = <2>; - bias-disable; - }; - }; - - lcd_backlight_en_pin_a: lcd-backlight-vddio { - pins = "gpio69"; - drive-strength = <10>; - output-low; - bias-disable; - }; - - sdhc1_pin_a: sdhc1-pin-active { - clk { - pins = "sdc1_clk"; - drive-strength = <16>; - bias-disable; - }; - - cmd-data { - pins = "sdc1_cmd", "sdc1_data"; - drive-strength = <10>; - bias-pull-up; - }; - }; - - sdhc2_cd_pin_a: sdhc2-cd-pin-active { - pins = "gpio62"; - function = "gpio"; - - drive-strength = <2>; - bias-disable; - }; - - sdhc2_pin_a: sdhc2-pin-active { - clk { - pins = "sdc2_clk"; - drive-strength = <6>; - bias-disable; - }; - - cmd-data { - pins = "sdc2_cmd", "sdc2_data"; - drive-strength = <6>; - bias-pull-up; - }; - }; - - sdhc3_pin_a: sdhc3-pin-active { - clk { - pins = "gpio40"; - function = "sdc3"; - - drive-strength = <10>; - bias-disable; - }; - - cmd { - pins = "gpio39"; - function = "sdc3"; - - drive-strength = <10>; - bias-pull-up; - }; - - data { - pins = "gpio35", "gpio36", "gpio37", "gpio38"; - function = "sdc3"; - - drive-strength = <10>; - bias-pull-up; - }; - }; - - ts_int_pin: synaptics { - pin { - pins = "gpio86"; - function = "gpio"; - - drive-strength = <2>; - bias-disable; - input-enable; - }; - }; - }; - - i2c@f9964000 { - status = "ok"; - - clock-frequency = <355000>; - qcom,src-freq = <50000000>; - - pinctrl-names = "default"; - pinctrl-0 = <&i2c8_pins>; - - synaptics@2c { - compatible = "syna,rmi4-i2c"; - reg = <0x2c>; - - interrupt-parent = <&msmgpio>; - interrupts = <86 IRQ_TYPE_EDGE_FALLING>; - - #address-cells = <1>; - #size-cells = <0>; - - vdd-supply = <&pm8941_l22>; - vio-supply = <&pm8941_lvs3>; - - pinctrl-names = "default"; - pinctrl-0 = <&ts_int_pin>; - - syna,startup-delay-ms = <10>; - - rmi-f01@1 { - reg = <0x1>; - syna,nosleep = <1>; - }; - - rmi-f11@11 { - reg = <0x11>; - syna,f11-flip-x = <1>; - syna,sensor-type = <1>; - }; - }; - }; - - i2c@f9967000 { - status = "ok"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c11_pins>; - clock-frequency = <355000>; - qcom,src-freq = <50000000>; - - lp8566_wled: backlight@2c { - compatible = "ti,lp8556"; - reg = <0x2c>; - power-supply = <&vreg_bl_vddio>; - - bl-name = "backlight"; - dev-ctrl = /bits/ 8 <0x05>; - init-brt = /bits/ 8 <0x3f>; - rom_a0h { - rom-addr = /bits/ 8 <0xa0>; - rom-val = /bits/ 8 <0xff>; - }; - rom_a1h { - rom-addr = /bits/ 8 <0xa1>; - rom-val = /bits/ 8 <0x3f>; - }; - rom_a2h { - rom-addr = /bits/ 8 <0xa2>; - rom-val = /bits/ 8 <0x20>; - }; - rom_a3h { - rom-addr = /bits/ 8 <0xa3>; - rom-val = /bits/ 8 <0x5e>; - }; - rom_a4h { - rom-addr = /bits/ 8 <0xa4>; - rom-val = /bits/ 8 <0x02>; - }; - rom_a5h { - rom-addr = /bits/ 8 <0xa5>; - rom-val = /bits/ 8 <0x04>; - }; - rom_a6h { - rom-addr = /bits/ 8 <0xa6>; - rom-val = /bits/ 8 <0x80>; - }; - rom_a7h { - rom-addr = /bits/ 8 <0xa7>; - rom-val = /bits/ 8 <0xf7>; - }; - rom_a9h { - rom-addr = /bits/ 8 <0xa9>; - rom-val = /bits/ 8 <0x80>; - }; - rom_aah { - rom-addr = /bits/ 8 <0xaa>; - rom-val = /bits/ 8 <0x0f>; - }; - rom_aeh { - rom-addr = /bits/ 8 <0xae>; - rom-val = /bits/ 8 <0x0f>; - }; - }; - }; -}; - -&spmi_bus { - pm8941@0 { - charger@1000 { - qcom,fast-charge-safe-current = <1500000>; - qcom,fast-charge-current-limit = <1500000>; - qcom,dc-current-limit = <1800000>; - qcom,fast-charge-safe-voltage = <4400000>; - qcom,fast-charge-high-threshold-voltage = <4350000>; - qcom,fast-charge-low-threshold-voltage = <3400000>; - qcom,auto-recharge-threshold-voltage = <4200000>; - qcom,minimum-input-voltage = <4300000>; - }; - - gpios@c000 { - gpio_keys_pin_a: gpio-keys-active { - pins = "gpio2", "gpio5"; - function = "normal"; - - bias-pull-up; - power-source = ; - }; - - wlan_sleep_clk_pin: wl-sleep-clk { - pins = "gpio17"; - function = "func2"; - - output-high; - power-source = ; - }; - - wlan_regulator_pin: wl-reg-active { - pins = "gpio18"; - function = "normal"; - - bias-disable; - power-source = ; - }; - - lcd_dcdc_en_pin_a: lcd-dcdc-en-active { - pins = "gpio20"; - function = "normal"; - - bias-disable; - power-source = ; - input-disable; - output-low; - }; - - }; - - coincell@2800 { - status = "ok"; - qcom,rset-ohms = <2100>; - qcom,vset-millivolts = <3000>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/qcom-msm8974-sony-xperia-honami.dts b/sys/gnu/dts/arm/qcom-msm8974-sony-xperia-honami.dts deleted file mode 100644 index 450b8321e0a..00000000000 --- a/sys/gnu/dts/arm/qcom-msm8974-sony-xperia-honami.dts +++ /dev/null @@ -1,460 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "qcom-msm8974.dtsi" -#include "qcom-pm8841.dtsi" -#include "qcom-pm8941.dtsi" -#include -#include -#include - -/ { - model = "Sony Xperia Z1"; - compatible = "sony,xperia-honami", "qcom,msm8974"; - - aliases { - serial0 = &blsp1_uart2; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - gpio-keys { - compatible = "gpio-keys"; - input-name = "gpio-keys"; - - pinctrl-names = "default"; - pinctrl-0 = <&gpio_keys_pin_a>; - - volume-down { - label = "volume_down"; - gpios = <&pm8941_gpios 2 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - linux,code = ; - }; - - camera-snapshot { - label = "camera_snapshot"; - gpios = <&pm8941_gpios 3 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - linux,code = ; - }; - - camera-focus { - label = "camera_focus"; - gpios = <&pm8941_gpios 4 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - linux,code = ; - }; - - volume-up { - label = "volume_up"; - gpios = <&pm8941_gpios 5 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - linux,code = ; - }; - }; - - memory@0 { - reg = <0 0x40000000>, <0x40000000 0x40000000>; - device_type = "memory"; - }; - - smd { - rpm { - rpm_requests { - pm8841-regulators { - s1 { - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <1050000>; - }; - - s2 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1050000>; - }; - - s3 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1050000>; - }; - - s4 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1050000>; - }; - }; - - pm8941-regulators { - vdd_l1_l3-supply = <&pm8941_s1>; - vdd_l2_lvs1_2_3-supply = <&pm8941_s3>; - vdd_l4_l11-supply = <&pm8941_s1>; - vdd_l5_l7-supply = <&pm8941_s2>; - vdd_l6_l12_l14_l15-supply = <&pm8941_s2>; - vdd_l9_l10_l17_l22-supply = <&vreg_boost>; - vdd_l13_l20_l23_l24-supply = <&vreg_boost>; - vdd_l21-supply = <&vreg_boost>; - - s1 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - }; - - s2 { - regulator-min-microvolt = <2150000>; - regulator-max-microvolt = <2150000>; - regulator-boot-on; - }; - - s3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - s4 { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - l1 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - - regulator-always-on; - regulator-boot-on; - }; - - l2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - l3 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - l4 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - - l5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-boot-on; - }; - - l7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-boot-on; - }; - - l8 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l9 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - l11 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1350000>; - }; - - l12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-always-on; - regulator-boot-on; - }; - - l13 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - - regulator-boot-on; - }; - - l14 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l15 { - regulator-min-microvolt = <2050000>; - regulator-max-microvolt = <2050000>; - }; - - l16 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; - - l17 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; - - l18 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - l19 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - l20 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - - regulator-allow-set-load; - regulator-boot-on; - regulator-system-load = <200000>; - }; - - l21 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - - regulator-boot-on; - }; - - l22 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - l23 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - l24 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3075000>; - - regulator-boot-on; - }; - }; - }; - }; - }; -}; - -&soc { - sdhci@f9824900 { - status = "ok"; - - vmmc-supply = <&pm8941_l20>; - vqmmc-supply = <&pm8941_s3>; - - bus-width = <8>; - non-removable; - - pinctrl-names = "default"; - pinctrl-0 = <&sdhc1_pin_a>; - }; - - sdhci@f98a4900 { - status = "ok"; - - bus-width = <4>; - - vmmc-supply = <&pm8941_l21>; - vqmmc-supply = <&pm8941_l13>; - - cd-gpios = <&msmgpio 62 GPIO_ACTIVE_LOW>; - - pinctrl-names = "default"; - pinctrl-0 = <&sdhc2_pin_a>, <&sdhc2_cd_pin_a>; - }; - - serial@f991e000 { - status = "ok"; - - pinctrl-names = "default"; - pinctrl-0 = <&blsp1_uart2_pin_a>; - }; - - i2c@f9924000 { - status = "ok"; - - clock-frequency = <355000>; - qcom,src-freq = <50000000>; - - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - - synaptics@2c { - compatible = "syna,rmi4-i2c"; - reg = <0x2c>; - - interrupts-extended = <&msmgpio 61 IRQ_TYPE_EDGE_FALLING>; - - #address-cells = <1>; - #size-cells = <0>; - - vdd-supply = <&pm8941_l22>; - vio-supply = <&pm8941_lvs3>; - - pinctrl-names = "default"; - pinctrl-0 = <&ts_int_pin>; - - syna,startup-delay-ms = <10>; - - rmi4-f01@1 { - reg = <0x1>; - syna,nosleep-mode = <1>; - }; - - rmi4-f11@11 { - reg = <0x11>; - touchscreen-inverted-x; - syna,sensor-type = <1>; - }; - }; - }; - - pinctrl@fd510000 { - blsp1_uart2_pin_a: blsp1-uart2-pin-active { - rx { - pins = "gpio5"; - function = "blsp_uart2"; - - drive-strength = <2>; - bias-pull-up; - }; - - tx { - pins = "gpio4"; - function = "blsp_uart2"; - - drive-strength = <4>; - bias-disable; - }; - }; - - i2c2_pins: i2c2 { - mux { - pins = "gpio6", "gpio7"; - function = "blsp_i2c2"; - - drive-strength = <2>; - bias-disable; - }; - }; - - sdhc1_pin_a: sdhc1-pin-active { - clk { - pins = "sdc1_clk"; - drive-strength = <16>; - bias-disable; - }; - - cmd-data { - pins = "sdc1_cmd", "sdc1_data"; - drive-strength = <10>; - bias-pull-up; - }; - }; - - sdhc2_cd_pin_a: sdhc2-cd-pin-active { - pins = "gpio62"; - function = "gpio"; - - drive-strength = <2>; - bias-disable; - }; - - sdhc2_pin_a: sdhc2-pin-active { - clk { - pins = "sdc2_clk"; - drive-strength = <10>; - bias-disable; - }; - - cmd-data { - pins = "sdc2_cmd", "sdc2_data"; - drive-strength = <6>; - bias-pull-up; - }; - }; - - ts_int_pin: touch-int { - pin { - pins = "gpio61"; - function = "gpio"; - - drive-strength = <2>; - bias-disable; - input-enable; - }; - }; - }; - - dma-controller@f9944000 { - qcom,controlled-remotely; - }; -}; - -&spmi_bus { - pm8941@0 { - charger@1000 { - qcom,fast-charge-safe-current = <1500000>; - qcom,fast-charge-current-limit = <1500000>; - qcom,dc-current-limit = <1800000>; - qcom,fast-charge-safe-voltage = <4400000>; - qcom,fast-charge-high-threshold-voltage = <4350000>; - qcom,fast-charge-low-threshold-voltage = <3400000>; - qcom,auto-recharge-threshold-voltage = <4200000>; - qcom,minimum-input-voltage = <4300000>; - }; - - gpios@c000 { - gpio_keys_pin_a: gpio-keys-active { - pins = "gpio2", "gpio3", "gpio4", "gpio5"; - function = "normal"; - - bias-pull-up; - power-source = ; - }; - }; - - coincell@2800 { - status = "ok"; - qcom,rset-ohms = <2100>; - qcom,vset-millivolts = <3000>; - }; - }; - - pm8941@1 { - wled@d800 { - status = "ok"; - - qcom,cs-out; - qcom,current-limit = <20>; - qcom,current-boost-limit = <805>; - qcom,switching-freq = <1600>; - qcom,ovp = <29>; - qcom,num-strings = <2>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/qcom-msm8974.dtsi b/sys/gnu/dts/arm/qcom-msm8974.dtsi deleted file mode 100644 index 4b161b809dd..00000000000 --- a/sys/gnu/dts/arm/qcom-msm8974.dtsi +++ /dev/null @@ -1,1622 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include -#include -#include -#include -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - model = "Qualcomm MSM8974"; - compatible = "qcom,msm8974"; - interrupt-parent = <&intc>; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - mpss_region: mpss@8000000 { - reg = <0x08000000 0x5100000>; - no-map; - }; - - mba_region: mba@d100000 { - reg = <0x0d100000 0x100000>; - no-map; - }; - - wcnss_region: wcnss@d200000 { - reg = <0x0d200000 0xa00000>; - no-map; - }; - - adsp_region: adsp@dc00000 { - reg = <0x0dc00000 0x1900000>; - no-map; - }; - - venus@f500000 { - reg = <0x0f500000 0x500000>; - no-map; - }; - - smem_region: smem@fa00000 { - reg = <0xfa00000 0x200000>; - no-map; - }; - - tz@fc00000 { - reg = <0x0fc00000 0x160000>; - no-map; - }; - - rfsa@fd60000 { - reg = <0x0fd60000 0x20000>; - no-map; - }; - - rmtfs@fd80000 { - compatible = "qcom,rmtfs-mem"; - reg = <0x0fd80000 0x180000>; - no-map; - - qcom,client-id = <1>; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - - CPU0: cpu@0 { - compatible = "qcom,krait"; - enable-method = "qcom,kpss-acc-v2"; - device_type = "cpu"; - reg = <0>; - next-level-cache = <&L2>; - qcom,acc = <&acc0>; - qcom,saw = <&saw0>; - cpu-idle-states = <&CPU_SPC>; - }; - - CPU1: cpu@1 { - compatible = "qcom,krait"; - enable-method = "qcom,kpss-acc-v2"; - device_type = "cpu"; - reg = <1>; - next-level-cache = <&L2>; - qcom,acc = <&acc1>; - qcom,saw = <&saw1>; - cpu-idle-states = <&CPU_SPC>; - }; - - CPU2: cpu@2 { - compatible = "qcom,krait"; - enable-method = "qcom,kpss-acc-v2"; - device_type = "cpu"; - reg = <2>; - next-level-cache = <&L2>; - qcom,acc = <&acc2>; - qcom,saw = <&saw2>; - cpu-idle-states = <&CPU_SPC>; - }; - - CPU3: cpu@3 { - compatible = "qcom,krait"; - enable-method = "qcom,kpss-acc-v2"; - device_type = "cpu"; - reg = <3>; - next-level-cache = <&L2>; - qcom,acc = <&acc3>; - qcom,saw = <&saw3>; - cpu-idle-states = <&CPU_SPC>; - }; - - L2: l2-cache { - compatible = "cache"; - cache-level = <2>; - qcom,saw = <&saw_l2>; - }; - - idle-states { - CPU_SPC: spc { - compatible = "qcom,idle-state-spc", - "arm,idle-state"; - entry-latency-us = <150>; - exit-latency-us = <200>; - min-residency-us = <2000>; - }; - }; - }; - - memory { - device_type = "memory"; - reg = <0x0 0x0>; - }; - - thermal-zones { - cpu-thermal0 { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 5>; - - trips { - cpu_alert0: trip0 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu_crit0: trip1 { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - cpu-thermal1 { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 6>; - - trips { - cpu_alert1: trip0 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu_crit1: trip1 { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - cpu-thermal2 { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 7>; - - trips { - cpu_alert2: trip0 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu_crit2: trip1 { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - cpu-thermal3 { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 8>; - - trips { - cpu_alert3: trip0 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu_crit3: trip1 { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - q6-dsp-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 1>; - - trips { - q6_dsp_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - modemtx-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 2>; - - trips { - modemtx_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - video-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 3>; - - trips { - video_alert0: trip-point0 { - temperature = <95000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - wlan-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 4>; - - trips { - wlan_alert0: trip-point0 { - temperature = <105000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - gpu-thermal-top { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 9>; - - trips { - gpu1_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - gpu-thermal-bottom { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 10>; - - trips { - gpu2_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - }; - - cpu-pmu { - compatible = "qcom,krait-pmu"; - interrupts = ; - }; - - clocks { - xo_board: xo_board { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <19200000>; - }; - - sleep_clk: sleep_clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; - clock-frequency = <19200000>; - }; - - adsp-pil { - compatible = "qcom,msm8974-adsp-pil"; - - interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; - - cx-supply = <&pm8841_s2>; - - clocks = <&xo_board>; - clock-names = "xo"; - - memory-region = <&adsp_region>; - - qcom,smem-states = <&adsp_smp2p_out 0>; - qcom,smem-state-names = "stop"; - - smd-edge { - interrupts = ; - - qcom,ipc = <&apcs 8 8>; - qcom,smd-edge = <1>; - - label = "lpass"; - }; - }; - - smem { - compatible = "qcom,smem"; - - memory-region = <&smem_region>; - qcom,rpm-msg-ram = <&rpm_msg_ram>; - - hwlocks = <&tcsr_mutex 3>; - }; - - smp2p-adsp { - compatible = "qcom,smp2p"; - qcom,smem = <443>, <429>; - - interrupt-parent = <&intc>; - interrupts = ; - - qcom,ipc = <&apcs 8 10>; - - qcom,local-pid = <0>; - qcom,remote-pid = <2>; - - adsp_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - adsp_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - smp2p-modem { - compatible = "qcom,smp2p"; - qcom,smem = <435>, <428>; - - interrupt-parent = <&intc>; - interrupts = ; - - qcom,ipc = <&apcs 8 14>; - - qcom,local-pid = <0>; - qcom,remote-pid = <1>; - - modem_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - modem_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - smp2p-wcnss { - compatible = "qcom,smp2p"; - qcom,smem = <451>, <431>; - - interrupt-parent = <&intc>; - interrupts = ; - - qcom,ipc = <&apcs 8 18>; - - qcom,local-pid = <0>; - qcom,remote-pid = <4>; - - wcnss_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; - - #qcom,smem-state-cells = <1>; - }; - - wcnss_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - smsm { - compatible = "qcom,smsm"; - - #address-cells = <1>; - #size-cells = <0>; - - qcom,ipc-1 = <&apcs 8 13>; - qcom,ipc-2 = <&apcs 8 9>; - qcom,ipc-3 = <&apcs 8 19>; - - apps_smsm: apps@0 { - reg = <0>; - - #qcom,smem-state-cells = <1>; - }; - - modem_smsm: modem@1 { - reg = <1>; - interrupts = ; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - adsp_smsm: adsp@2 { - reg = <2>; - interrupts = ; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - wcnss_smsm: wcnss@7 { - reg = <7>; - interrupts = ; - - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - firmware { - scm { - compatible = "qcom,scm"; - clocks = <&gcc GCC_CE1_CLK>, <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>; - clock-names = "core", "bus", "iface"; - }; - }; - - soc: soc { - #address-cells = <1>; - #size-cells = <1>; - ranges; - compatible = "simple-bus"; - - intc: interrupt-controller@f9000000 { - compatible = "qcom,msm-qgic2"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0xf9000000 0x1000>, - <0xf9002000 0x1000>; - }; - - apcs: syscon@f9011000 { - compatible = "syscon"; - reg = <0xf9011000 0x1000>; - }; - - qfprom: qfprom@fc4bc000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "qcom,qfprom"; - reg = <0xfc4bc000 0x1000>; - tsens_calib: calib@d0 { - reg = <0xd0 0x18>; - }; - tsens_backup: backup@440 { - reg = <0x440 0x10>; - }; - }; - - tsens: thermal-sensor@fc4a9000 { - compatible = "qcom,msm8974-tsens"; - reg = <0xfc4a9000 0x1000>, /* TM */ - <0xfc4a8000 0x1000>; /* SROT */ - nvmem-cells = <&tsens_calib>, <&tsens_backup>; - nvmem-cell-names = "calib", "calib_backup"; - #qcom,sensors = <11>; - interrupts = ; - interrupt-names = "uplow"; - #thermal-sensor-cells = <1>; - }; - - timer@f9020000 { - #address-cells = <1>; - #size-cells = <1>; - ranges; - compatible = "arm,armv7-timer-mem"; - reg = <0xf9020000 0x1000>; - clock-frequency = <19200000>; - - frame@f9021000 { - frame-number = <0>; - interrupts = , - ; - reg = <0xf9021000 0x1000>, - <0xf9022000 0x1000>; - }; - - frame@f9023000 { - frame-number = <1>; - interrupts = ; - reg = <0xf9023000 0x1000>; - status = "disabled"; - }; - - frame@f9024000 { - frame-number = <2>; - interrupts = ; - reg = <0xf9024000 0x1000>; - status = "disabled"; - }; - - frame@f9025000 { - frame-number = <3>; - interrupts = ; - reg = <0xf9025000 0x1000>; - status = "disabled"; - }; - - frame@f9026000 { - frame-number = <4>; - interrupts = ; - reg = <0xf9026000 0x1000>; - status = "disabled"; - }; - - frame@f9027000 { - frame-number = <5>; - interrupts = ; - reg = <0xf9027000 0x1000>; - status = "disabled"; - }; - - frame@f9028000 { - frame-number = <6>; - interrupts = ; - reg = <0xf9028000 0x1000>; - status = "disabled"; - }; - }; - - saw0: power-controller@f9089000 { - compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; - reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>; - }; - - saw1: power-controller@f9099000 { - compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; - reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>; - }; - - saw2: power-controller@f90a9000 { - compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; - reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>; - }; - - saw3: power-controller@f90b9000 { - compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; - reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>; - }; - - saw_l2: power-controller@f9012000 { - compatible = "qcom,saw2"; - reg = <0xf9012000 0x1000>; - regulator; - }; - - acc0: clock-controller@f9088000 { - compatible = "qcom,kpss-acc-v2"; - reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>; - }; - - acc1: clock-controller@f9098000 { - compatible = "qcom,kpss-acc-v2"; - reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>; - }; - - acc2: clock-controller@f90a8000 { - compatible = "qcom,kpss-acc-v2"; - reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>; - }; - - acc3: clock-controller@f90b8000 { - compatible = "qcom,kpss-acc-v2"; - reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>; - }; - - restart@fc4ab000 { - compatible = "qcom,pshold"; - reg = <0xfc4ab000 0x4>; - }; - - gcc: clock-controller@fc400000 { - compatible = "qcom,gcc-msm8974"; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - reg = <0xfc400000 0x4000>; - }; - - tcsr: syscon@fd4a0000 { - compatible = "syscon"; - reg = <0xfd4a0000 0x10000>; - }; - - tcsr_mutex_block: syscon@fd484000 { - compatible = "syscon"; - reg = <0xfd484000 0x2000>; - }; - - mmcc: clock-controller@fd8c0000 { - compatible = "qcom,mmcc-msm8974"; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - reg = <0xfd8c0000 0x6000>; - }; - - tcsr_mutex: tcsr-mutex { - compatible = "qcom,tcsr-mutex"; - syscon = <&tcsr_mutex_block 0 0x80>; - - #hwlock-cells = <1>; - }; - - rpm_msg_ram: memory@fc428000 { - compatible = "qcom,rpm-msg-ram"; - reg = <0xfc428000 0x4000>; - }; - - blsp1_uart1: serial@f991d000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0xf991d000 0x1000>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - - blsp1_uart2: serial@f991e000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0xf991e000 0x1000>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - - sdhci@f9824900 { - compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; - reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; - reg-names = "hc_mem", "core_mem"; - interrupts = , - ; - interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC1_APPS_CLK>, - <&gcc GCC_SDCC1_AHB_CLK>, - <&xo_board>; - clock-names = "core", "iface", "xo"; - status = "disabled"; - }; - - sdhci@f9864900 { - compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; - reg = <0xf9864900 0x11c>, <0xf9864000 0x800>; - reg-names = "hc_mem", "core_mem"; - interrupts = , - ; - interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC3_APPS_CLK>, - <&gcc GCC_SDCC3_AHB_CLK>, - <&xo_board>; - clock-names = "core", "iface", "xo"; - status = "disabled"; - }; - - sdhci@f98a4900 { - compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; - reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; - reg-names = "hc_mem", "core_mem"; - interrupts = , - ; - interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC2_APPS_CLK>, - <&gcc GCC_SDCC2_AHB_CLK>, - <&xo_board>; - clock-names = "core", "iface", "xo"; - status = "disabled"; - }; - - otg: usb@f9a55000 { - compatible = "qcom,ci-hdrc"; - reg = <0xf9a55000 0x200>, - <0xf9a55200 0x200>; - interrupts = ; - clocks = <&gcc GCC_USB_HS_AHB_CLK>, - <&gcc GCC_USB_HS_SYSTEM_CLK>; - clock-names = "iface", "core"; - assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>; - assigned-clock-rates = <75000000>; - resets = <&gcc GCC_USB_HS_BCR>; - reset-names = "core"; - phy_type = "ulpi"; - dr_mode = "otg"; - ahb-burst-config = <0>; - phy-names = "usb-phy"; - status = "disabled"; - #reset-cells = <1>; - - ulpi { - usb_hs1_phy: phy@a { - compatible = "qcom,usb-hs-phy-msm8974", - "qcom,usb-hs-phy"; - #phy-cells = <0>; - clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>; - clock-names = "ref", "sleep"; - resets = <&gcc GCC_USB2A_PHY_BCR>, <&otg 0>; - reset-names = "phy", "por"; - status = "disabled"; - }; - - usb_hs2_phy: phy@b { - compatible = "qcom,usb-hs-phy-msm8974", - "qcom,usb-hs-phy"; - #phy-cells = <0>; - clocks = <&xo_board>, <&gcc GCC_USB2B_PHY_SLEEP_CLK>; - clock-names = "ref", "sleep"; - resets = <&gcc GCC_USB2B_PHY_BCR>, <&otg 1>; - reset-names = "phy", "por"; - status = "disabled"; - }; - }; - }; - - rng@f9bff000 { - compatible = "qcom,prng"; - reg = <0xf9bff000 0x200>; - clocks = <&gcc GCC_PRNG_AHB_CLK>; - clock-names = "core"; - }; - - remoteproc@fc880000 { - compatible = "qcom,msm8974-mss-pil"; - reg = <0xfc880000 0x100>, <0xfc820000 0x020>; - reg-names = "qdsp6", "rmb"; - - interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; - - clocks = <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, - <&gcc GCC_MSS_CFG_AHB_CLK>, - <&gcc GCC_BOOT_ROM_AHB_CLK>, - <&xo_board>; - clock-names = "iface", "bus", "mem", "xo"; - - resets = <&gcc GCC_MSS_RESTART>; - reset-names = "mss_restart"; - - cx-supply = <&pm8841_s2>; - mss-supply = <&pm8841_s3>; - mx-supply = <&pm8841_s1>; - pll-supply = <&pm8941_l12>; - - qcom,halt-regs = <&tcsr_mutex_block 0x1180 0x1200 0x1280>; - - qcom,smem-states = <&modem_smp2p_out 0>; - qcom,smem-state-names = "stop"; - - mba { - memory-region = <&mba_region>; - }; - - mpss { - memory-region = <&mpss_region>; - }; - - smd-edge { - interrupts = ; - - qcom,ipc = <&apcs 8 12>; - qcom,smd-edge = <0>; - - label = "modem"; - }; - }; - - pronto: remoteproc@fb21b000 { - compatible = "qcom,pronto-v2-pil", "qcom,pronto"; - reg = <0xfb204000 0x2000>, <0xfb202000 0x1000>, <0xfb21b000 0x3000>; - reg-names = "ccu", "dxe", "pmu"; - - memory-region = <&wcnss_region>; - - interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>, - <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, - <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, - <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; - - vddpx-supply = <&pm8941_s3>; - - qcom,smem-states = <&wcnss_smp2p_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - iris { - compatible = "qcom,wcn3680"; - - clocks = <&rpmcc RPM_SMD_CXO_A2>; - clock-names = "xo"; - - vddxo-supply = <&pm8941_l6>; - vddrfa-supply = <&pm8941_l11>; - vddpa-supply = <&pm8941_l19>; - vdddig-supply = <&pm8941_s3>; - }; - - smd-edge { - interrupts = ; - - qcom,ipc = <&apcs 8 17>; - qcom,smd-edge = <6>; - - wcnss { - compatible = "qcom,wcnss"; - qcom,smd-channels = "WCNSS_CTRL"; - status = "disabled"; - - qcom,mmio = <&pronto>; - - bt { - compatible = "qcom,wcnss-bt"; - }; - - wifi { - compatible = "qcom,wcnss-wlan"; - - interrupts = , - ; - interrupt-names = "tx", "rx"; - - qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>; - qcom,smem-state-names = "tx-enable", "tx-rings-empty"; - }; - }; - }; - }; - - msmgpio: pinctrl@fd510000 { - compatible = "qcom,msm8974-pinctrl"; - reg = <0xfd510000 0x4000>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = ; - }; - - i2c@f9923000 { - status = "disabled"; - compatible = "qcom,i2c-qup-v2.1.1"; - reg = <0xf9923000 0x1000>; - interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c@f9924000 { - status = "disabled"; - compatible = "qcom,i2c-qup-v2.1.1"; - reg = <0xf9924000 0x1000>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - #address-cells = <1>; - #size-cells = <0>; - }; - - blsp_i2c3: i2c@f9925000 { - status = "disabled"; - compatible = "qcom,i2c-qup-v2.1.1"; - reg = <0xf9925000 0x1000>; - interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - #address-cells = <1>; - #size-cells = <0>; - }; - - blsp_i2c8: i2c@f9964000 { - status = "disabled"; - compatible = "qcom,i2c-qup-v2.1.1"; - reg = <0xf9964000 0x1000>; - interrupts = ; - clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; - clock-names = "core", "iface"; - #address-cells = <1>; - #size-cells = <0>; - }; - - blsp_i2c11: i2c@f9967000 { - status = "disabled"; - compatible = "qcom,i2c-qup-v2.1.1"; - reg = <0xf9967000 0x1000>; - interrupts = ; - clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; - clock-names = "core", "iface"; - #address-cells = <1>; - #size-cells = <0>; - dmas = <&blsp2_dma 20>, <&blsp2_dma 21>; - dma-names = "tx", "rx"; - }; - - blsp_i2c12: i2c@f9968000 { - status = "disabled"; - compatible = "qcom,i2c-qup-v2.1.1"; - reg = <0xf9968000 0x1000>; - interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; - clock-names = "core", "iface"; - #address-cells = <1>; - #size-cells = <0>; - }; - - spmi_bus: spmi@fc4cf000 { - compatible = "qcom,spmi-pmic-arb"; - reg-names = "core", "intr", "cnfg"; - reg = <0xfc4cf000 0x1000>, - <0xfc4cb000 0x1000>, - <0xfc4ca000 0x1000>; - interrupt-names = "periph_irq"; - interrupts = ; - qcom,ee = <0>; - qcom,channel = <0>; - #address-cells = <2>; - #size-cells = <0>; - interrupt-controller; - #interrupt-cells = <4>; - }; - - blsp2_dma: dma-controller@f9944000 { - compatible = "qcom,bam-v1.4.0"; - reg = <0xf9944000 0x19000>; - interrupts = ; - clocks = <&gcc GCC_BLSP2_AHB_CLK>; - clock-names = "bam_clk"; - #dma-cells = <1>; - qcom,ee = <0>; - }; - - etr@fc322000 { - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0xfc322000 0x1000>; - - clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - in-ports { - port { - etr_in: endpoint { - remote-endpoint = <&replicator_out0>; - }; - }; - }; - }; - - tpiu@fc318000 { - compatible = "arm,coresight-tpiu", "arm,primecell"; - reg = <0xfc318000 0x1000>; - - clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - in-ports { - port { - tpiu_in: endpoint { - remote-endpoint = <&replicator_out1>; - }; - }; - }; - }; - - replicator@fc31c000 { - compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; - reg = <0xfc31c000 0x1000>; - - clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - out-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - replicator_out0: endpoint { - remote-endpoint = <&etr_in>; - }; - }; - port@1 { - reg = <1>; - replicator_out1: endpoint { - remote-endpoint = <&tpiu_in>; - }; - }; - }; - - in-ports { - port { - replicator_in: endpoint { - remote-endpoint = <&etf_out>; - }; - }; - }; - }; - - etf@fc307000 { - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0xfc307000 0x1000>; - - clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - out-ports { - port { - etf_out: endpoint { - remote-endpoint = <&replicator_in>; - }; - }; - }; - - in-ports { - port { - etf_in: endpoint { - remote-endpoint = <&merger_out>; - }; - }; - }; - }; - - funnel@fc31b000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0xfc31b000 0x1000>; - - clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - /* - * Not described input ports: - * 0 - connected trought funnel to Audio, Modem and - * Resource and Power Manager CPU's - * 2...7 - not-connected - */ - port@1 { - reg = <1>; - merger_in1: endpoint { - remote-endpoint = <&funnel1_out>; - }; - }; - }; - - out-ports { - port { - merger_out: endpoint { - remote-endpoint = <&etf_in>; - }; - }; - }; - }; - - funnel@fc31a000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0xfc31a000 0x1000>; - - clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - /* - * Not described input ports: - * 0 - not-connected - * 1 - connected trought funnel to Multimedia CPU - * 2 - connected to Wireless CPU - * 3 - not-connected - * 4 - not-connected - * 6 - not-connected - * 7 - connected to STM - */ - port@5 { - reg = <5>; - funnel1_in5: endpoint { - remote-endpoint = <&kpss_out>; - }; - }; - }; - - out-ports { - port { - funnel1_out: endpoint { - remote-endpoint = <&merger_in1>; - }; - }; - }; - }; - - funnel@fc345000 { /* KPSS funnel only 4 inputs are used */ - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0xfc345000 0x1000>; - - clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - kpss_in0: endpoint { - remote-endpoint = <&etm0_out>; - }; - }; - port@1 { - reg = <1>; - kpss_in1: endpoint { - remote-endpoint = <&etm1_out>; - }; - }; - port@2 { - reg = <2>; - kpss_in2: endpoint { - remote-endpoint = <&etm2_out>; - }; - }; - port@3 { - reg = <3>; - kpss_in3: endpoint { - remote-endpoint = <&etm3_out>; - }; - }; - }; - - out-ports { - port { - kpss_out: endpoint { - remote-endpoint = <&funnel1_in5>; - }; - }; - }; - }; - - etm@fc33c000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0xfc33c000 0x1000>; - - clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - cpu = <&CPU0>; - - out-ports { - port { - etm0_out: endpoint { - remote-endpoint = <&kpss_in0>; - }; - }; - }; - }; - - etm@fc33d000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0xfc33d000 0x1000>; - - clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - cpu = <&CPU1>; - - out-ports { - port { - etm1_out: endpoint { - remote-endpoint = <&kpss_in1>; - }; - }; - }; - }; - - etm@fc33e000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0xfc33e000 0x1000>; - - clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - cpu = <&CPU2>; - - out-ports { - port { - etm2_out: endpoint { - remote-endpoint = <&kpss_in2>; - }; - }; - }; - }; - - etm@fc33f000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0xfc33f000 0x1000>; - - clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - cpu = <&CPU3>; - - out-ports { - port { - etm3_out: endpoint { - remote-endpoint = <&kpss_in3>; - }; - }; - }; - }; - - ocmem@fdd00000 { - compatible = "qcom,msm8974-ocmem"; - reg = <0xfdd00000 0x2000>, - <0xfec00000 0x180000>; - reg-names = "ctrl", - "mem"; - clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>, - <&mmcc OCMEMCX_OCMEMNOC_CLK>; - clock-names = "core", - "iface"; - - #address-cells = <1>; - #size-cells = <1>; - - gmu_sram: gmu-sram@0 { - reg = <0x0 0x100000>; - }; - }; - - bimc: interconnect@fc380000 { - reg = <0xfc380000 0x6a000>; - compatible = "qcom,msm8974-bimc"; - #interconnect-cells = <1>; - clock-names = "bus", "bus_a"; - clocks = <&rpmcc RPM_SMD_BIMC_CLK>, - <&rpmcc RPM_SMD_BIMC_A_CLK>; - }; - - snoc: interconnect@fc460000 { - reg = <0xfc460000 0x4000>; - compatible = "qcom,msm8974-snoc"; - #interconnect-cells = <1>; - clock-names = "bus", "bus_a"; - clocks = <&rpmcc RPM_SMD_SNOC_CLK>, - <&rpmcc RPM_SMD_SNOC_A_CLK>; - }; - - pnoc: interconnect@fc468000 { - reg = <0xfc468000 0x4000>; - compatible = "qcom,msm8974-pnoc"; - #interconnect-cells = <1>; - clock-names = "bus", "bus_a"; - clocks = <&rpmcc RPM_SMD_PNOC_CLK>, - <&rpmcc RPM_SMD_PNOC_A_CLK>; - }; - - ocmemnoc: interconnect@fc470000 { - reg = <0xfc470000 0x4000>; - compatible = "qcom,msm8974-ocmemnoc"; - #interconnect-cells = <1>; - clock-names = "bus", "bus_a"; - clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>, - <&rpmcc RPM_SMD_OCMEMGX_A_CLK>; - }; - - mmssnoc: interconnect@fc478000 { - reg = <0xfc478000 0x4000>; - compatible = "qcom,msm8974-mmssnoc"; - #interconnect-cells = <1>; - clock-names = "bus", "bus_a"; - clocks = <&mmcc MMSS_S0_AXI_CLK>, - <&mmcc MMSS_S0_AXI_CLK>; - }; - - cnoc: interconnect@fc480000 { - reg = <0xfc480000 0x4000>; - compatible = "qcom,msm8974-cnoc"; - #interconnect-cells = <1>; - clock-names = "bus", "bus_a"; - clocks = <&rpmcc RPM_SMD_CNOC_CLK>, - <&rpmcc RPM_SMD_CNOC_A_CLK>; - }; - - mdss: mdss@fd900000 { - status = "disabled"; - - compatible = "qcom,mdss"; - reg = <0xfd900000 0x100>, - <0xfd924000 0x1000>; - reg-names = "mdss_phys", - "vbif_phys"; - - power-domains = <&mmcc MDSS_GDSC>; - - clocks = <&mmcc MDSS_AHB_CLK>, - <&mmcc MDSS_AXI_CLK>, - <&mmcc MDSS_VSYNC_CLK>; - clock-names = "iface", - "bus", - "vsync"; - - interrupts = ; - - interrupt-controller; - #interrupt-cells = <1>; - - #address-cells = <1>; - #size-cells = <1>; - ranges; - - mdp: mdp@fd900000 { - status = "disabled"; - - compatible = "qcom,mdp5"; - reg = <0xfd900100 0x22000>; - reg-names = "mdp_phys"; - - interrupt-parent = <&mdss>; - interrupts = <0 0>; - - clocks = <&mmcc MDSS_AHB_CLK>, - <&mmcc MDSS_AXI_CLK>, - <&mmcc MDSS_MDP_CLK>, - <&mmcc MDSS_VSYNC_CLK>; - clock-names = "iface", - "bus", - "core", - "vsync"; - - interconnects = <&mmssnoc MNOC_MAS_MDP_PORT0 &bimc BIMC_SLV_EBI_CH0>; - interconnect-names = "mdp0-mem"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - mdp5_intf1_out: endpoint { - remote-endpoint = <&dsi0_in>; - }; - }; - }; - }; - - dsi0: dsi@fd922800 { - status = "disabled"; - - compatible = "qcom,mdss-dsi-ctrl"; - reg = <0xfd922800 0x1f8>; - reg-names = "dsi_ctrl"; - - interrupt-parent = <&mdss>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; - - assigned-clocks = <&mmcc BYTE0_CLK_SRC>, - <&mmcc PCLK0_CLK_SRC>; - assigned-clock-parents = <&dsi_phy0 0>, - <&dsi_phy0 1>; - - clocks = <&mmcc MDSS_MDP_CLK>, - <&mmcc MDSS_AHB_CLK>, - <&mmcc MDSS_AXI_CLK>, - <&mmcc MDSS_BYTE0_CLK>, - <&mmcc MDSS_PCLK0_CLK>, - <&mmcc MDSS_ESC0_CLK>, - <&mmcc MMSS_MISC_AHB_CLK>; - clock-names = "mdp_core", - "iface", - "bus", - "byte", - "pixel", - "core", - "core_mmss"; - - phys = <&dsi_phy0>; - phy-names = "dsi-phy"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dsi0_in: endpoint { - remote-endpoint = <&mdp5_intf1_out>; - }; - }; - - port@1 { - reg = <1>; - dsi0_out: endpoint { - }; - }; - }; - }; - - dsi_phy0: dsi-phy@fd922a00 { - status = "disabled"; - - compatible = "qcom,dsi-phy-28nm-hpm"; - reg = <0xfd922a00 0xd4>, - <0xfd922b00 0x280>, - <0xfd922d80 0x30>; - reg-names = "dsi_pll", - "dsi_phy", - "dsi_phy_regulator"; - - #clock-cells = <1>; - #phy-cells = <0>; - qcom,dsi-phy-index = <0>; - - clocks = <&mmcc MDSS_AHB_CLK>; - clock-names = "iface"; - }; - }; - - imem@fe805000 { - status = "disabled"; - compatible = "syscon", "simple-mfd"; - reg = <0xfe805000 0x1000>; - - reboot-mode { - compatible = "syscon-reboot-mode"; - offset = <0x65c>; - }; - }; - }; - - smd { - compatible = "qcom,smd"; - - rpm { - interrupts = ; - qcom,ipc = <&apcs 8 0>; - qcom,smd-edge = <15>; - - rpm_requests { - compatible = "qcom,rpm-msm8974"; - qcom,smd-channels = "rpm_requests"; - - rpmcc: clock-controller { - compatible = "qcom,rpmcc-msm8974", "qcom,rpmcc"; - #clock-cells = <1>; - }; - - pm8841-regulators { - compatible = "qcom,rpm-pm8841-regulators"; - - pm8841_s1: s1 {}; - pm8841_s2: s2 {}; - pm8841_s3: s3 {}; - pm8841_s4: s4 {}; - pm8841_s5: s5 {}; - pm8841_s6: s6 {}; - pm8841_s7: s7 {}; - pm8841_s8: s8 {}; - }; - - pm8941-regulators { - compatible = "qcom,rpm-pm8941-regulators"; - - pm8941_s1: s1 {}; - pm8941_s2: s2 {}; - pm8941_s3: s3 {}; - - pm8941_l1: l1 {}; - pm8941_l2: l2 {}; - pm8941_l3: l3 {}; - pm8941_l4: l4 {}; - pm8941_l5: l5 {}; - pm8941_l6: l6 {}; - pm8941_l7: l7 {}; - pm8941_l8: l8 {}; - pm8941_l9: l9 {}; - pm8941_l10: l10 {}; - pm8941_l11: l11 {}; - pm8941_l12: l12 {}; - pm8941_l13: l13 {}; - pm8941_l14: l14 {}; - pm8941_l15: l15 {}; - pm8941_l16: l16 {}; - pm8941_l17: l17 {}; - pm8941_l18: l18 {}; - pm8941_l19: l19 {}; - pm8941_l20: l20 {}; - pm8941_l21: l21 {}; - pm8941_l22: l22 {}; - pm8941_l23: l23 {}; - pm8941_l24: l24 {}; - - pm8941_lvs1: lvs1 {}; - pm8941_lvs2: lvs2 {}; - pm8941_lvs3: lvs3 {}; - }; - }; - }; - }; - - vreg_boost: vreg-boost { - compatible = "regulator-fixed"; - - regulator-name = "vreg-boost"; - regulator-min-microvolt = <3150000>; - regulator-max-microvolt = <3150000>; - - regulator-always-on; - regulator-boot-on; - - gpio = <&pm8941_gpios 21 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-names = "default"; - pinctrl-0 = <&boost_bypass_n_pin>; - }; - vreg_vph_pwr: vreg-vph-pwr { - compatible = "regulator-fixed"; - regulator-name = "vph-pwr"; - - regulator-min-microvolt = <3600000>; - regulator-max-microvolt = <3600000>; - - regulator-always-on; - }; -}; diff --git a/sys/gnu/dts/arm/qcom-msm8974pro.dtsi b/sys/gnu/dts/arm/qcom-msm8974pro.dtsi deleted file mode 100644 index 6740a4cb7da..00000000000 --- a/sys/gnu/dts/arm/qcom-msm8974pro.dtsi +++ /dev/null @@ -1,18 +0,0 @@ -#include "qcom-msm8974.dtsi" - -/ { - soc { - sdhci@f9824900 { - clocks = <&gcc GCC_SDCC1_APPS_CLK>, - <&gcc GCC_SDCC1_AHB_CLK>, - <&xo_board>, - <&gcc GCC_SDCC1_CDCCAL_FF_CLK>, - <&gcc GCC_SDCC1_CDCCAL_SLEEP_CLK>; - clock-names = "core", "iface", "xo", "cal", "sleep"; - }; - - clock-controller@fc400000 { - compatible = "qcom,gcc-msm8974pro"; - }; - }; -}; diff --git a/sys/gnu/dts/arm/qcom-pm8841.dtsi b/sys/gnu/dts/arm/qcom-pm8841.dtsi deleted file mode 100644 index 2fd59c44090..00000000000 --- a/sys/gnu/dts/arm/qcom-pm8841.dtsi +++ /dev/null @@ -1,37 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include -#include - -&spmi_bus { - - pm8841_0: pm8841@4 { - compatible = "qcom,pm8841", "qcom,spmi-pmic"; - reg = <0x4 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - - pm8841_mpps: mpps@a000 { - compatible = "qcom,pm8841-mpp", "qcom,spmi-mpp"; - reg = <0xa000>; - gpio-controller; - #gpio-cells = <2>; - interrupts = <4 0xa0 0 IRQ_TYPE_NONE>, - <4 0xa1 0 IRQ_TYPE_NONE>, - <4 0xa2 0 IRQ_TYPE_NONE>, - <4 0xa3 0 IRQ_TYPE_NONE>; - }; - - temp-alarm@2400 { - compatible = "qcom,spmi-temp-alarm"; - reg = <0x2400>; - interrupts = <4 0x24 0 IRQ_TYPE_EDGE_RISING>; - }; - }; - - pm8841_1: pm8841@5 { - compatible = "qcom,pm8841", "qcom,spmi-pmic"; - reg = <0x5 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - }; -}; diff --git a/sys/gnu/dts/arm/qcom-pm8941.dtsi b/sys/gnu/dts/arm/qcom-pm8941.dtsi deleted file mode 100644 index c1f2012d1c8..00000000000 --- a/sys/gnu/dts/arm/qcom-pm8941.dtsi +++ /dev/null @@ -1,193 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include -#include -#include - -&spmi_bus { - - pm8941_0: pm8941@0 { - compatible = "qcom,pm8941", "qcom,spmi-pmic"; - reg = <0x0 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - - rtc@6000 { - compatible = "qcom,pm8941-rtc"; - reg = <0x6000>, - <0x6100>; - reg-names = "rtc", "alarm"; - interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>; - }; - - pwrkey@800 { - compatible = "qcom,pm8941-pwrkey"; - reg = <0x800>; - interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>; - debounce = <15625>; - bias-pull-up; - }; - - usb_id: misc@900 { - compatible = "qcom,pm8941-misc"; - reg = <0x900>; - interrupts = <0x0 0x9 0 IRQ_TYPE_EDGE_BOTH>; - interrupt-names = "usb_id"; - }; - - smbb: charger@1000 { - compatible = "qcom,pm8941-charger"; - reg = <0x1000>; - interrupts = <0x0 0x10 7 IRQ_TYPE_EDGE_BOTH>, - <0x0 0x10 5 IRQ_TYPE_EDGE_BOTH>, - <0x0 0x10 4 IRQ_TYPE_EDGE_BOTH>, - <0x0 0x12 1 IRQ_TYPE_EDGE_BOTH>, - <0x0 0x12 0 IRQ_TYPE_EDGE_BOTH>, - <0x0 0x13 2 IRQ_TYPE_EDGE_BOTH>, - <0x0 0x13 1 IRQ_TYPE_EDGE_BOTH>, - <0x0 0x14 1 IRQ_TYPE_EDGE_BOTH>; - interrupt-names = "chg-done", - "chg-fast", - "chg-trkl", - "bat-temp-ok", - "bat-present", - "chg-gone", - "usb-valid", - "dc-valid"; - - usb-otg-in-supply = <&pm8941_5vs1>; - - chg_otg: otg-vbus { }; - }; - - pm8941_gpios: gpios@c000 { - compatible = "qcom,pm8941-gpio", "qcom,spmi-gpio"; - reg = <0xc000>; - gpio-controller; - gpio-ranges = <&pm8941_gpios 0 0 36>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - - boost_bypass_n_pin: boost-bypass { - pins = "gpio21"; - function = "normal"; - }; - }; - - pm8941_mpps: mpps@a000 { - compatible = "qcom,pm8941-mpp", "qcom,spmi-mpp"; - reg = <0xa000>; - gpio-controller; - #gpio-cells = <2>; - interrupts = <0 0xa0 0 IRQ_TYPE_NONE>, - <0 0xa1 0 IRQ_TYPE_NONE>, - <0 0xa2 0 IRQ_TYPE_NONE>, - <0 0xa3 0 IRQ_TYPE_NONE>, - <0 0xa4 0 IRQ_TYPE_NONE>, - <0 0xa5 0 IRQ_TYPE_NONE>, - <0 0xa6 0 IRQ_TYPE_NONE>, - <0 0xa7 0 IRQ_TYPE_NONE>; - }; - - pm8941_temp: temp-alarm@2400 { - compatible = "qcom,spmi-temp-alarm"; - reg = <0x2400>; - interrupts = <0 0x24 0 IRQ_TYPE_EDGE_RISING>; - io-channels = <&pm8941_vadc VADC_DIE_TEMP>; - io-channel-names = "thermal"; - #thermal-sensor-cells = <0>; - }; - - pm8941_vadc: vadc@3100 { - compatible = "qcom,spmi-vadc"; - reg = <0x3100>; - interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; - #address-cells = <1>; - #size-cells = <0>; - #io-channel-cells = <1>; - - bat_temp { - reg = ; - }; - die_temp { - reg = ; - }; - ref_625mv { - reg = ; - }; - ref_1250v { - reg = ; - }; - ref_gnd { - reg = ; - }; - ref_vdd { - reg = ; - }; - vbat_sns { - reg = ; - }; - }; - - pm8941_iadc: iadc@3600 { - compatible = "qcom,pm8941-iadc", "qcom,spmi-iadc"; - reg = <0x3600>; - interrupts = <0x0 0x36 0x0 IRQ_TYPE_EDGE_RISING>; - qcom,external-resistor-micro-ohms = <10000>; - }; - - coincell@2800 { - compatible = "qcom,pm8941-coincell"; - reg = <0x2800>; - status = "disabled"; - }; - }; - - pm8941_1: pm8941@1 { - compatible = "qcom,pm8941", "qcom,spmi-pmic"; - reg = <0x1 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - - pm8941_wled: wled@d800 { - compatible = "qcom,pm8941-wled"; - reg = <0xd800>; - label = "backlight"; - - status = "disabled"; - }; - - regulators { - compatible = "qcom,pm8941-regulators"; - interrupts = <0x1 0x83 0x2 0>, <0x1 0x84 0x2 0>; - interrupt-names = "ocp-5vs1", "ocp-5vs2"; - vin_5vs-supply = <&pm8941_5v>; - - pm8941_5v: s4 { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-enable-ramp-delay = <500>; - }; - - pm8941_5vs1: 5vs1 { - regulator-enable-ramp-delay = <1000>; - regulator-pull-down; - regulator-over-current-protection; - qcom,ocp-max-retries = <10>; - qcom,ocp-retry-delay = <30>; - qcom,vs-soft-start-strength = <0>; - regulator-initial-mode = <1>; - }; - - pm8941_5vs2: 5vs2 { - regulator-enable-ramp-delay = <1000>; - regulator-pull-down; - regulator-over-current-protection; - qcom,ocp-max-retries = <10>; - qcom,ocp-retry-delay = <30>; - qcom,vs-soft-start-strength = <0>; - regulator-initial-mode = <1>; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/qcom-pma8084.dtsi b/sys/gnu/dts/arm/qcom-pma8084.dtsi deleted file mode 100644 index ea1ca166165..00000000000 --- a/sys/gnu/dts/arm/qcom-pma8084.dtsi +++ /dev/null @@ -1,100 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include -#include -#include - -&spmi_bus { - - pma8084_0: pma8084@0 { - compatible = "qcom,pma8084", "qcom,spmi-pmic"; - reg = <0x0 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - - rtc@6000 { - compatible = "qcom,pm8941-rtc"; - reg = <0x6000>, - <0x6100>; - reg-names = "rtc", "alarm"; - interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>; - }; - - pwrkey@800 { - compatible = "qcom,pm8941-pwrkey"; - reg = <0x800>; - interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>; - debounce = <15625>; - bias-pull-up; - }; - - pma8084_gpios: gpios@c000 { - compatible = "qcom,pma8084-gpio", "qcom,spmi-gpio"; - reg = <0xc000>; - gpio-controller; - gpio-ranges = <&pma8084_gpios 0 0 22>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - pma8084_mpps: mpps@a000 { - compatible = "qcom,pma8084-mpp", "qcom,spmi-mpp"; - reg = <0xa000>; - gpio-controller; - #gpio-cells = <2>; - interrupts = <0 0xa0 0 IRQ_TYPE_NONE>, - <0 0xa1 0 IRQ_TYPE_NONE>, - <0 0xa2 0 IRQ_TYPE_NONE>, - <0 0xa3 0 IRQ_TYPE_NONE>, - <0 0xa4 0 IRQ_TYPE_NONE>, - <0 0xa5 0 IRQ_TYPE_NONE>, - <0 0xa6 0 IRQ_TYPE_NONE>, - <0 0xa7 0 IRQ_TYPE_NONE>; - }; - - pma8084_temp: temp-alarm@2400 { - compatible = "qcom,spmi-temp-alarm"; - reg = <0x2400>; - interrupts = <0 0x24 0 IRQ_TYPE_EDGE_RISING>; - #thermal-sensor-cells = <0>; - io-channels = <&pma8084_vadc VADC_DIE_TEMP>; - io-channel-names = "thermal"; - }; - - pma8084_vadc: vadc@3100 { - compatible = "qcom,spmi-vadc"; - reg = <0x3100>; - interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; - #address-cells = <1>; - #size-cells = <0>; - #io-channel-cells = <1>; - io-channel-ranges; - - die_temp { - reg = ; - }; - ref_625mv { - reg = ; - }; - ref_1250v { - reg = ; - }; - ref_buf_625mv { - reg = ; - }; - ref_gnd { - reg = ; - }; - ref_vdd { - reg = ; - }; - }; - }; - - pma8084_1: pma8084@1 { - compatible = "qcom,pma8084", "qcom,spmi-pmic"; - reg = <0x1 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - }; -}; diff --git a/sys/gnu/dts/arm/r7s72100-genmai.dts b/sys/gnu/dts/arm/r7s72100-genmai.dts deleted file mode 100644 index 07d611d2b7b..00000000000 --- a/sys/gnu/dts/arm/r7s72100-genmai.dts +++ /dev/null @@ -1,148 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the Genmai board - * - * Copyright (C) 2013-14 Renesas Solutions Corp. - * Copyright (C) 2014 Wolfram Sang, Sang Engineering - */ - -/dts-v1/; -#include "r7s72100.dtsi" -#include -#include - -/ { - model = "Genmai"; - compatible = "renesas,genmai", "renesas,r7s72100"; - - aliases { - serial0 = &scif2; - }; - - chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; - stdout-path = "serial0:115200n8"; - }; - - memory@8000000 { - device_type = "memory"; - reg = <0x08000000 0x08000000>; - }; - - lbsc { - #address-cells = <1>; - #size-cells = <1>; - }; - - leds { - status = "okay"; - compatible = "gpio-leds"; - - led1 { - gpios = <&port4 10 GPIO_ACTIVE_LOW>; - }; - - led2 { - gpios = <&port4 11 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&pinctrl { - - scif2_pins: serial2 { - /* P3_0 as TxD2; P3_2 as RxD2 */ - pinmux = , ; - }; - - i2c2_pins: i2c2 { - /* RIIC2: P1_4 as SCL, P1_5 as SDA */ - pinmux = , ; - }; - - ether_pins: ether { - /* Ethernet on Ports 1,2,3,5 */ - pinmux = ,/* P1_14 = ET_COL */ - , /* P5_9 = ET_MDC */ - , /* P3_3 = ET_MDIO */ - , /* P3_4 = ET_RXCLK */ - , /* P3_5 = ET_RXER */ - , /* P3_6 = ET_RXDV */ - , /* P2_0 = ET_TXCLK */ - , /* P2_1 = ET_TXER */ - , /* P2_2 = ET_TXEN */ - , /* P2_3 = ET_CRS */ - , /* P2_4 = ET_TXD0 */ - , /* P2_5 = ET_TXD1 */ - , /* P2_6 = ET_TXD2 */ - , /* P2_7 = ET_TXD3 */ - , /* P2_8 = ET_RXD0 */ - , /* P2_9 = ET_RXD1 */ - ,/* P2_10 = ET_RXD2 */ - ;/* P2_11 = ET_RXD3 */ - }; -}; - -&extal_clk { - clock-frequency = <13330000>; -}; - -&usb_x1_clk { - clock-frequency = <48000000>; -}; - -&rtc_x1_clk { - clock-frequency = <32768>; -}; - -&mtu2 { - status = "okay"; -}; - -ðer { - pinctrl-names = "default"; - pinctrl-0 = <ðer_pins>; - - status = "okay"; - - renesas,no-ether-link; - phy-handle = <&phy0>; - phy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -&i2c2 { - status = "okay"; - clock-frequency = <400000>; - - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - - eeprom@50 { - compatible = "renesas,r1ex24128", "atmel,24c128"; - reg = <0x50>; - pagesize = <64>; - }; -}; - -&rtc { - status = "okay"; -}; - -&scif2 { - pinctrl-names = "default"; - pinctrl-0 = <&scif2_pins>; - - status = "okay"; -}; - -&spi4 { - status = "okay"; - - codec: codec@0 { - compatible = "wlf,wm8978"; - reg = <0>; - spi-max-frequency = <5000000>; - }; -}; diff --git a/sys/gnu/dts/arm/r7s72100-gr-peach.dts b/sys/gnu/dts/arm/r7s72100-gr-peach.dts deleted file mode 100644 index fe1a4aa4d7c..00000000000 --- a/sys/gnu/dts/arm/r7s72100-gr-peach.dts +++ /dev/null @@ -1,134 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the GR-Peach board - * - * Copyright (C) 2017 Jacopo Mondi - * Copyright (C) 2016 Renesas Electronics - */ - -/dts-v1/; -#include "r7s72100.dtsi" -#include -#include - -/ { - model = "GR-Peach"; - compatible = "renesas,gr-peach", "renesas,r7s72100"; - - aliases { - serial0 = &scif2; - }; - - chosen { - bootargs = "ignore_loglevel rw root=/dev/mtdblock0"; - stdout-path = "serial0:115200n8"; - }; - - memory@20000000 { - device_type = "memory"; - reg = <0x20000000 0x00a00000>; - }; - - lbsc { - #address-cells = <1>; - #size-cells = <1>; - }; - - flash@18000000 { - compatible = "mtd-rom"; - probe-type = "map_rom"; - reg = <0x18000000 0x00800000>; - bank-width = <4>; - device-width = <1>; - - #address-cells = <1>; - #size-cells = <1>; - - rootfs@600000 { - label = "rootfs"; - reg = <0x00600000 0x00200000>; - }; - }; - - leds { - status = "okay"; - compatible = "gpio-leds"; - - led1 { - gpios = <&port6 12 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&pinctrl { - scif2_pins: serial2 { - /* P6_2 as RxD2; P6_3 as TxD2 */ - pinmux = , ; - }; - - ether_pins: ether { - /* Ethernet on Ports 1,3,5,10 */ - pinmux = , /* P1_14 = ET_COL */ - , /* P3_0 = ET_TXCLK */ - , /* P3_3 = ET_MDIO */ - , /* P3_4 = ET_RXCLK */ - , /* P3_5 = ET_RXER */ - , /* P3_6 = ET_RXDV */ - , /* P5_9 = ET_MDC */ - , /* P10_1 = ET_TXER */ - , /* P10_2 = ET_TXEN */ - , /* P10_3 = ET_CRS */ - , /* P10_4 = ET_TXD0 */ - , /* P10_5 = ET_TXD1 */ - , /* P10_6 = ET_TXD2 */ - , /* P10_7 = ET_TXD3 */ - , /* P10_8 = ET_RXD0 */ - , /* P10_9 = ET_RXD1 */ - ,/* P10_10 = ET_RXD2 */ - ;/* P10_11 = ET_RXD3 */ - }; -}; - -&extal_clk { - clock-frequency = <13333000>; -}; - -&usb_x1_clk { - clock-frequency = <48000000>; -}; - -&mtu2 { - status = "okay"; -}; - -&ostm0 { - status = "okay"; -}; - -&ostm1 { - status = "okay"; -}; - -&scif2 { - pinctrl-names = "default"; - pinctrl-0 = <&scif2_pins>; - - status = "okay"; -}; - -ðer { - pinctrl-names = "default"; - pinctrl-0 = <ðer_pins>; - - status = "okay"; - - renesas,no-ether-link; - phy-handle = <&phy0>; - - phy0: ethernet-phy@0 { - reg = <0>; - - reset-gpios = <&port4 2 GPIO_ACTIVE_LOW>; - reset-delay-us = <5>; - }; -}; diff --git a/sys/gnu/dts/arm/r7s72100-rskrza1.dts b/sys/gnu/dts/arm/r7s72100-rskrza1.dts deleted file mode 100644 index 99acfe4fe11..00000000000 --- a/sys/gnu/dts/arm/r7s72100-rskrza1.dts +++ /dev/null @@ -1,222 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the RZ/A1H RSK board - * - * Copyright (C) 2016 Renesas Electronics - */ - -/dts-v1/; -#include "r7s72100.dtsi" -#include -#include -#include - -/ { - model = "RSKRZA1"; - compatible = "renesas,rskrza1", "renesas,r7s72100"; - - aliases { - serial0 = &scif2; - }; - - chosen { - bootargs = "ignore_loglevel"; - stdout-path = "serial0:115200n8"; - }; - - memory@8000000 { - device_type = "memory"; - reg = <0x08000000 0x02000000>; - }; - - keyboard { - compatible = "gpio-keys"; - - pinctrl-names = "default"; - pinctrl-0 = <&keyboard_pins>; - - key-1 { - interrupt-parent = <&irqc>; - interrupts = <3 IRQ_TYPE_EDGE_BOTH>; - linux,code = ; - label = "SW1"; - wakeup-source; - }; - - key-2 { - interrupt-parent = <&irqc>; - interrupts = <2 IRQ_TYPE_EDGE_BOTH>; - linux,code = ; - label = "SW2"; - wakeup-source; - }; - - key-3 { - interrupt-parent = <&irqc>; - interrupts = <5 IRQ_TYPE_EDGE_BOTH>; - linux,code = ; - label = "SW3"; - wakeup-source; - }; - }; - - lbsc { - #address-cells = <1>; - #size-cells = <1>; - }; - - leds { - compatible = "gpio-leds"; - - led0 { - gpios = <&port7 1 GPIO_ACTIVE_LOW>; - }; - - led1 { - gpios = <&io_expander1 0 GPIO_ACTIVE_LOW>; - }; - - led2 { - gpios = <&io_expander1 1 GPIO_ACTIVE_LOW>; - }; - - led3 { - gpios = <&io_expander1 2 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&extal_clk { - clock-frequency = <13330000>; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_pins>; - status = "okay"; - - clock-frequency = <400000>; - - io_expander1: gpio@20 { - compatible = "onnn,cat9554"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - }; - - io_expander2: gpio@21 { - compatible = "onnn,cat9554"; - reg = <0x21>; - gpio-controller; - #gpio-cells = <2>; - }; - - eeprom@50 { - compatible = "renesas,r1ex24016", "atmel,24c16"; - reg = <0x50>; - pagesize = <16>; - }; -}; - -&usb_x1_clk { - clock-frequency = <48000000>; -}; - -&rtc_x1_clk { - clock-frequency = <32768>; -}; - -&pinctrl { - /* RIIC ch3 (Port Expander, EEPROM (MAC Addr), Audio Codec) */ - i2c3_pins: i2c3 { - pinmux = , /* RIIC3SCL */ - ; /* RIIC3SDA */ - }; - - keyboard_pins: keyboard { - pinmux = , /* IRQ3 */ - , /* IRQ2 */ - ; /* IRQ5 */ - }; - - /* Serial Console */ - scif2_pins: serial2 { - pinmux = , /* TxD2 */ - ; /* RxD2 */ - }; - - /* Ethernet */ - ether_pins: ether { - /* Ethernet on Ports 1,2,3,5 */ - pinmux = , /* ET_COL */ - , /* ET_MDC */ - , /* ET_MDIO */ - , /* ET_RXCLK */ - , /* ET_RXER */ - , /* ET_RXDV */ - , /* ET_TXCLK */ - , /* ET_TXER */ - , /* ET_TXEN */ - , /* ET_CRS */ - , /* ET_TXD0 */ - , /* ET_TXD1 */ - , /* ET_TXD2 */ - , /* ET_TXD3 */ - , /* ET_RXD0 */ - , /* ET_RXD1 */ - , /* ET_RXD2 */ - ; /* ET_RXD3 */ - }; - - /* SDHI ch1 on CN1 */ - sdhi1_pins: sdhi1 { - pinmux = , /* SD_CD_1 */ - , /* SD_WP_1 */ - , /* SD_D1_1 */ - , /* SD_D0_1 */ - , /* SD_CLK_1 */ - , /* SD_CMD_1 */ - , /* SD_D3_1 */ - ; /* SD_D2_1 */ - }; -}; - -&mtu2 { - status = "okay"; -}; - -ðer { - pinctrl-names = "default"; - pinctrl-0 = <ðer_pins>; - status = "okay"; - renesas,no-ether-link; - phy-handle = <&phy0>; - phy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -&sdhi1 { - pinctrl-names = "default"; - pinctrl-0 = <&sdhi1_pins>; - bus-width = <4>; - status = "okay"; -}; - -&ostm0 { - status = "okay"; -}; - -&ostm1 { - status = "okay"; -}; - -&rtc { - status = "okay"; -}; - -&scif2 { - pinctrl-names = "default"; - pinctrl-0 = <&scif2_pins>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/r7s72100.dtsi b/sys/gnu/dts/arm/r7s72100.dtsi deleted file mode 100644 index 75b2796ebfc..00000000000 --- a/sys/gnu/dts/arm/r7s72100.dtsi +++ /dev/null @@ -1,724 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the r7s72100 SoC - * - * Copyright (C) 2013-14 Renesas Solutions Corp. - * Copyright (C) 2014 Wolfram Sang, Sang Engineering - */ - -#include -#include -#include - -/ { - compatible = "renesas,r7s72100"; - #address-cells = <1>; - #size-cells = <1>; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - spi0 = &spi0; - spi1 = &spi1; - spi2 = &spi2; - spi3 = &spi3; - spi4 = &spi4; - }; - - /* Fixed factor clocks */ - b_clk: b { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R7S72100_CLK_PLL>; - clock-mult = <1>; - clock-div = <3>; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - clock-frequency = <400000000>; - clocks = <&cpg_clocks R7S72100_CLK_I>; - next-level-cache = <&L2>; - }; - }; - - /* External clocks */ - extal_clk: extal { - #clock-cells = <0>; - compatible = "fixed-clock"; - /* If clk present, value must be set by board */ - clock-frequency = <0>; - }; - - p0_clk: p0 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R7S72100_CLK_PLL>; - clock-mult = <1>; - clock-div = <12>; - }; - - p1_clk: p1 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R7S72100_CLK_PLL>; - clock-mult = <1>; - clock-div = <6>; - }; - - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts-extended = <&gic GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>; - }; - - rtc_x1_clk: rtc_x1 { - #clock-cells = <0>; - compatible = "fixed-clock"; - /* If clk present, value must be set by board to 32678 */ - clock-frequency = <0>; - }; - - rtc_x3_clk: rtc_x3 { - #clock-cells = <0>; - compatible = "fixed-clock"; - /* If clk present, value must be set by board to 4000000 */ - clock-frequency = <0>; - }; - - soc { - compatible = "simple-bus"; - interrupt-parent = <&gic>; - - #address-cells = <1>; - #size-cells = <1>; - ranges; - - L2: cache-controller@3ffff000 { - compatible = "arm,pl310-cache"; - reg = <0x3ffff000 0x1000>; - interrupts = ; - arm,early-bresp-disable; - arm,full-line-zero-disable; - cache-unified; - cache-level = <2>; - }; - - scif0: serial@e8007000 { - compatible = "renesas,scif-r7s72100", "renesas,scif"; - reg = <0xe8007000 64>; - interrupts = , - , - , - ; - clocks = <&mstp4_clks R7S72100_CLK_SCIF0>; - clock-names = "fck"; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - scif1: serial@e8007800 { - compatible = "renesas,scif-r7s72100", "renesas,scif"; - reg = <0xe8007800 64>; - interrupts = , - , - , - ; - clocks = <&mstp4_clks R7S72100_CLK_SCIF1>; - clock-names = "fck"; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - scif2: serial@e8008000 { - compatible = "renesas,scif-r7s72100", "renesas,scif"; - reg = <0xe8008000 64>; - interrupts = , - , - , - ; - clocks = <&mstp4_clks R7S72100_CLK_SCIF2>; - clock-names = "fck"; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - scif3: serial@e8008800 { - compatible = "renesas,scif-r7s72100", "renesas,scif"; - reg = <0xe8008800 64>; - interrupts = , - , - , - ; - clocks = <&mstp4_clks R7S72100_CLK_SCIF3>; - clock-names = "fck"; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - scif4: serial@e8009000 { - compatible = "renesas,scif-r7s72100", "renesas,scif"; - reg = <0xe8009000 64>; - interrupts = , - , - , - ; - clocks = <&mstp4_clks R7S72100_CLK_SCIF4>; - clock-names = "fck"; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - scif5: serial@e8009800 { - compatible = "renesas,scif-r7s72100", "renesas,scif"; - reg = <0xe8009800 64>; - interrupts = , - , - , - ; - clocks = <&mstp4_clks R7S72100_CLK_SCIF5>; - clock-names = "fck"; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - scif6: serial@e800a000 { - compatible = "renesas,scif-r7s72100", "renesas,scif"; - reg = <0xe800a000 64>; - interrupts = , - , - , - ; - clocks = <&mstp4_clks R7S72100_CLK_SCIF6>; - clock-names = "fck"; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - scif7: serial@e800a800 { - compatible = "renesas,scif-r7s72100", "renesas,scif"; - reg = <0xe800a800 64>; - interrupts = , - , - , - ; - clocks = <&mstp4_clks R7S72100_CLK_SCIF7>; - clock-names = "fck"; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - spi0: spi@e800c800 { - compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz"; - reg = <0xe800c800 0x24>; - interrupts = , - , - ; - interrupt-names = "error", "rx", "tx"; - clocks = <&mstp10_clks R7S72100_CLK_SPI0>; - power-domains = <&cpg_clocks>; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi1: spi@e800d000 { - compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz"; - reg = <0xe800d000 0x24>; - interrupts = , - , - ; - interrupt-names = "error", "rx", "tx"; - clocks = <&mstp10_clks R7S72100_CLK_SPI1>; - power-domains = <&cpg_clocks>; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi2: spi@e800d800 { - compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz"; - reg = <0xe800d800 0x24>; - interrupts = , - , - ; - interrupt-names = "error", "rx", "tx"; - clocks = <&mstp10_clks R7S72100_CLK_SPI2>; - power-domains = <&cpg_clocks>; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi3: spi@e800e000 { - compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz"; - reg = <0xe800e000 0x24>; - interrupts = , - , - ; - interrupt-names = "error", "rx", "tx"; - clocks = <&mstp10_clks R7S72100_CLK_SPI3>; - power-domains = <&cpg_clocks>; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi4: spi@e800e800 { - compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz"; - reg = <0xe800e800 0x24>; - interrupts = , - , - ; - interrupt-names = "error", "rx", "tx"; - clocks = <&mstp10_clks R7S72100_CLK_SPI4>; - power-domains = <&cpg_clocks>; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - usbhs0: usb@e8010000 { - compatible = "renesas,usbhs-r7s72100", "renesas,rza1-usbhs"; - reg = <0xe8010000 0x1a0>; - interrupts = ; - clocks = <&mstp7_clks R7S72100_CLK_USB0>; - renesas,buswait = <4>; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - usbhs1: usb@e8207000 { - compatible = "renesas,usbhs-r7s72100", "renesas,rza1-usbhs"; - reg = <0xe8207000 0x1a0>; - interrupts = ; - clocks = <&mstp7_clks R7S72100_CLK_USB1>; - renesas,buswait = <4>; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - mmcif: mmc@e804c800 { - compatible = "renesas,mmcif-r7s72100", "renesas,sh-mmcif"; - reg = <0xe804c800 0x80>; - interrupts = , - , - ; - clocks = <&mstp8_clks R7S72100_CLK_MMCIF>; - power-domains = <&cpg_clocks>; - reg-io-width = <4>; - bus-width = <8>; - status = "disabled"; - }; - - sdhi0: sd@e804e000 { - compatible = "renesas,sdhi-r7s72100"; - reg = <0xe804e000 0x100>; - interrupts = , - , - ; - - clocks = <&mstp12_clks R7S72100_CLK_SDHI00>, - <&mstp12_clks R7S72100_CLK_SDHI01>; - clock-names = "core", "cd"; - power-domains = <&cpg_clocks>; - cap-sd-highspeed; - cap-sdio-irq; - status = "disabled"; - }; - - sdhi1: sd@e804e800 { - compatible = "renesas,sdhi-r7s72100"; - reg = <0xe804e800 0x100>; - interrupts = , - , - ; - - clocks = <&mstp12_clks R7S72100_CLK_SDHI10>, - <&mstp12_clks R7S72100_CLK_SDHI11>; - clock-names = "core", "cd"; - power-domains = <&cpg_clocks>; - cap-sd-highspeed; - cap-sdio-irq; - status = "disabled"; - }; - - gic: interrupt-controller@e8201000 { - compatible = "arm,pl390"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0xe8201000 0x1000>, - <0xe8202000 0x1000>; - }; - - ether: ethernet@e8203000 { - compatible = "renesas,ether-r7s72100"; - reg = <0xe8203000 0x800>, - <0xe8204800 0x200>; - interrupts = ; - clocks = <&mstp7_clks R7S72100_CLK_ETHER>; - power-domains = <&cpg_clocks>; - phy-mode = "mii"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - ceu: camera@e8210000 { - reg = <0xe8210000 0x3000>; - compatible = "renesas,r7s72100-ceu"; - interrupts = ; - clocks = <&mstp6_clks R7S72100_CLK_CEU>; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - wdt: watchdog@fcfe0000 { - compatible = "renesas,r7s72100-wdt", "renesas,rza-wdt"; - reg = <0xfcfe0000 0x6>; - interrupts = ; - clocks = <&p0_clk>; - }; - - /* Special CPG clocks */ - cpg_clocks: cpg_clocks@fcfe0000 { - #clock-cells = <1>; - compatible = "renesas,r7s72100-cpg-clocks", - "renesas,rz-cpg-clocks"; - reg = <0xfcfe0000 0x18>; - clocks = <&extal_clk>, <&usb_x1_clk>; - clock-output-names = "pll", "i", "g"; - #power-domain-cells = <0>; - }; - - /* MSTP clocks */ - mstp3_clks: mstp3_clks@fcfe0420 { - #clock-cells = <1>; - compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0xfcfe0420 4>; - clocks = <&p0_clk>; - clock-indices = ; - clock-output-names = "mtu2"; - }; - - mstp4_clks: mstp4_clks@fcfe0424 { - #clock-cells = <1>; - compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0xfcfe0424 4>; - clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>, - <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>; - clock-indices = < - R7S72100_CLK_SCIF0 R7S72100_CLK_SCIF1 R7S72100_CLK_SCIF2 R7S72100_CLK_SCIF3 - R7S72100_CLK_SCIF4 R7S72100_CLK_SCIF5 R7S72100_CLK_SCIF6 R7S72100_CLK_SCIF7 - >; - clock-output-names = "scif0", "scif1", "scif2", "scif3", "scif4", "scif5", "scif6", "scif7"; - }; - - mstp5_clks: mstp5_clks@fcfe0428 { - #clock-cells = <1>; - compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0xfcfe0428 4>; - clocks = <&p0_clk>, <&p0_clk>; - clock-indices = ; - clock-output-names = "ostm0", "ostm1"; - }; - - mstp6_clks: mstp6_clks@fcfe042c { - #clock-cells = <1>; - compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0xfcfe042c 4>; - clocks = <&b_clk>, <&p0_clk>; - clock-indices = ; - clock-output-names = "ceu", "rtc"; - }; - - mstp7_clks: mstp7_clks@fcfe0430 { - #clock-cells = <1>; - compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0xfcfe0430 4>; - clocks = <&b_clk>, <&p1_clk>, <&p1_clk>; - clock-indices = ; - clock-output-names = "ether", "usb0", "usb1"; - }; - - mstp8_clks: mstp8_clks@fcfe0434 { - #clock-cells = <1>; - compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0xfcfe0434 4>; - clocks = <&p1_clk>; - clock-indices = ; - clock-output-names = "mmcif"; - }; - - mstp9_clks: mstp9_clks@fcfe0438 { - #clock-cells = <1>; - compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0xfcfe0438 4>; - clocks = <&p0_clk>, <&p0_clk>, <&p0_clk>, <&p0_clk>; - clock-indices = < - R7S72100_CLK_I2C0 R7S72100_CLK_I2C1 R7S72100_CLK_I2C2 R7S72100_CLK_I2C3 - >; - clock-output-names = "i2c0", "i2c1", "i2c2", "i2c3"; - }; - - mstp10_clks: mstp10_clks@fcfe043c { - #clock-cells = <1>; - compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0xfcfe043c 4>; - clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>, - <&p1_clk>; - clock-indices = < - R7S72100_CLK_SPI0 R7S72100_CLK_SPI1 R7S72100_CLK_SPI2 R7S72100_CLK_SPI3 - R7S72100_CLK_SPI4 - >; - clock-output-names = "spi0", "spi1", "spi2", "spi3", "spi4"; - }; - mstp12_clks: mstp12_clks@fcfe0444 { - #clock-cells = <1>; - compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0xfcfe0444 4>; - clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>; - clock-indices = < - R7S72100_CLK_SDHI00 R7S72100_CLK_SDHI01 - R7S72100_CLK_SDHI10 R7S72100_CLK_SDHI11 - >; - clock-output-names = "sdhi00", "sdhi01", "sdhi10", "sdhi11"; - }; - - pinctrl: pin-controller@fcfe3000 { - compatible = "renesas,r7s72100-ports"; - - reg = <0xfcfe3000 0x4230>; - - port0: gpio-0 { - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl 0 0 6>; - }; - - port1: gpio-1 { - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl 0 16 16>; - }; - - port2: gpio-2 { - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl 0 32 16>; - }; - - port3: gpio-3 { - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl 0 48 16>; - }; - - port4: gpio-4 { - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl 0 64 16>; - }; - - port5: gpio-5 { - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl 0 80 11>; - }; - - port6: gpio-6 { - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl 0 96 16>; - }; - - port7: gpio-7 { - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl 0 112 16>; - }; - - port8: gpio-8 { - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl 0 128 16>; - }; - - port9: gpio-9 { - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl 0 144 8>; - }; - - port10: gpio-10 { - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl 0 160 16>; - }; - - port11: gpio-11 { - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl 0 176 16>; - }; - }; - - ostm0: timer@fcfec000 { - compatible = "renesas,r7s72100-ostm", "renesas,ostm"; - reg = <0xfcfec000 0x30>; - interrupts = ; - clocks = <&mstp5_clks R7S72100_CLK_OSTM0>; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - ostm1: timer@fcfec400 { - compatible = "renesas,r7s72100-ostm", "renesas,ostm"; - reg = <0xfcfec400 0x30>; - interrupts = ; - clocks = <&mstp5_clks R7S72100_CLK_OSTM1>; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - i2c0: i2c@fcfee000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,riic-r7s72100", "renesas,riic-rz"; - reg = <0xfcfee000 0x44>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&mstp9_clks R7S72100_CLK_I2C0>; - clock-frequency = <100000>; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - i2c1: i2c@fcfee400 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,riic-r7s72100", "renesas,riic-rz"; - reg = <0xfcfee400 0x44>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&mstp9_clks R7S72100_CLK_I2C1>; - clock-frequency = <100000>; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - i2c2: i2c@fcfee800 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,riic-r7s72100", "renesas,riic-rz"; - reg = <0xfcfee800 0x44>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&mstp9_clks R7S72100_CLK_I2C2>; - clock-frequency = <100000>; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - i2c3: i2c@fcfeec00 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,riic-r7s72100", "renesas,riic-rz"; - reg = <0xfcfeec00 0x44>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&mstp9_clks R7S72100_CLK_I2C3>; - clock-frequency = <100000>; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - irqc: interrupt-controller@fcfef800 { - compatible = "renesas,r7s72100-irqc", - "renesas,rza1-irqc"; - #interrupt-cells = <2>; - #address-cells = <0>; - interrupt-controller; - reg = <0xfcfef800 0x6>; - interrupt-map = - <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, - <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, - <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, - <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, - <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, - <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, - <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, - <7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; - interrupt-map-mask = <7 0>; - }; - - mtu2: timer@fcff0000 { - compatible = "renesas,mtu2-r7s72100", "renesas,mtu2"; - reg = <0xfcff0000 0x400>; - interrupts = ; - interrupt-names = "tgi0a"; - clocks = <&mstp3_clks R7S72100_CLK_MTU2>; - clock-names = "fck"; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - rtc: rtc@fcff1000 { - compatible = "renesas,r7s72100-rtc", "renesas,sh-rtc"; - reg = <0xfcff1000 0x2e>; - interrupts = , - , - ; - interrupt-names = "alarm", "period", "carry"; - clocks = <&mstp6_clks R7S72100_CLK_RTC>, <&rtc_x1_clk>, - <&rtc_x3_clk>, <&extal_clk>; - clock-names = "fck", "rtc_x1", "rtc_x3", "extal"; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - }; - - usb_x1_clk: usb_x1 { - #clock-cells = <0>; - compatible = "fixed-clock"; - /* If clk present, value must be set by board */ - clock-frequency = <0>; - }; -}; diff --git a/sys/gnu/dts/arm/r7s9210-rza2mevb.dts b/sys/gnu/dts/arm/r7s9210-rza2mevb.dts deleted file mode 100644 index d062d02865e..00000000000 --- a/sys/gnu/dts/arm/r7s9210-rza2mevb.dts +++ /dev/null @@ -1,219 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the RZA2MEVB board - * - * Copyright (C) 2018 Renesas Electronics - * - */ - -/dts-v1/; -#include "r7s9210.dtsi" -#include -#include -#include - -/ { - model = "RZA2MEVB"; - compatible = "renesas,rza2mevb", "renesas,r7s9210"; - - aliases { - serial0 = &scif4; - ethernet0 = ðer0; - ethernet1 = ðer1; - }; - - chosen { - bootargs = "ignore_loglevel"; - stdout-path = "serial0:115200n8"; - }; - - keyboard { - compatible = "gpio-keys"; - - pinctrl-names = "default"; - pinctrl-0 = <&keyboard_pins>; - - key-3 { - interrupt-parent = <&irqc>; - interrupts = <0 IRQ_TYPE_EDGE_BOTH>; - linux,code = ; - label = "SW3"; - wakeup-source; - }; - }; - - lbsc { - #address-cells = <1>; - #size-cells = <1>; - }; - - leds { - compatible = "gpio-leds"; - - red { - gpios = <&pinctrl RZA2_PIN(PORT6, 0) GPIO_ACTIVE_HIGH>; - }; - green { - gpios = <&pinctrl RZA2_PIN(PORTC, 1) GPIO_ACTIVE_HIGH>; - }; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x00800000>; /* HyperRAM */ - }; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -ðer0 { - pinctrl-names = "default"; - pinctrl-0 = <ð0_pins>; - status = "okay"; - renesas,no-ether-link; - phy-handle = <&phy0>; - phy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -ðer1 { - pinctrl-names = "default"; - pinctrl-0 = <ð1_pins>; - status = "okay"; - renesas,no-ether-link; - phy-handle = <&phy1>; - phy1: ethernet-phy@1 { - reg = <0>; - }; -}; - -/* EXTAL */ -&extal_clk { - clock-frequency = <24000000>; /* 24MHz */ -}; - -/* High resolution System tick timers */ -&ostm0 { - status = "okay"; -}; - -&ostm1 { - status = "okay"; -}; - -&pinctrl { - eth0_pins: eth0 { - pinmux = , /* REF50CK0 */ - , /* RMMI0_TXDEN */ - , /* RMII0_TXD0 */ - , /* RMII0_TXD1 */ - , /* RMII0_CRSDV */ - , /* RMII0_RXD0 */ - , /* RMII0_RXD1 */ - , /* RMII0_RXER */ - , /* ET0_MDC */ - , /* ET0_MDIO */ - ; /* IRQ4 */ - }; - - eth1_pins: eth1 { - pinmux = , /* REF50CK1 */ - , /* RMMI1_TXDEN */ - , /* RMII1_TXD0 */ - , /* RMII1_TXD1 */ - , /* RMII1_CRSDV */ - , /* RMII1_RXD0 */ - , /* RMII1_RXD1 */ - , /* RMII1_RXER */ - , /* ET1_MDC */ - , /* ET1_MDIO */ - ; /* IRQ5 */ - }; - - keyboard_pins: keyboard { - pinmux = ; /* IRQ0 */ - }; - - /* Serial Console */ - scif4_pins: serial4 { - pinmux = , /* TxD4 */ - ; /* RxD4 */ - }; - - sdhi0_pins: sdhi0 { - pinmux = , /* SD0_CD */ - ; /* SD0_WP */ - }; - - sdhi1_pins: sdhi1 { - pinmux = , /* SD1_CD */ - ; /* SD1_WP */ - }; - - usb0_pins: usb0 { - pinmux = , /* VBUSIN0 */ - , /* VBUSEN0 */ - ; /* OVRCUR0 */ - }; - - usb1_pins: usb1 { - pinmux = , /* VBUSIN1 */ - , /* VBUSEN1 */ - ; /* OVRCUR1 */ - }; -}; - -/* RTC_X1 */ -&rtc_x1_clk { - clock-frequency = <32768>; -}; - -/* Serial Console */ -&scif4 { - pinctrl-names = "default"; - pinctrl-0 = <&scif4_pins>; - - status = "okay"; -}; - -&sdhi0 { - pinctrl-names = "default"; - pinctrl-0 = <&sdhi0_pins>; - bus-width = <4>; - status = "okay"; -}; - -&sdhi1 { - pinctrl-names = "default"; - pinctrl-0 = <&sdhi1_pins>; - bus-width = <4>; - status = "okay"; -}; - -/* USB-0 as Host */ -&usb2_phy0 { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_pins>; - dr_mode = "host"; /* Requires JP3 to be fitted */ - status = "okay"; -}; - -/* USB-1 as Host */ -&usb2_phy1 { - pinctrl-names = "default"; - pinctrl-0 = <&usb1_pins>; - dr_mode = "host"; - status = "okay"; -}; - -/* USB_X1 */ -&usb_x1_clk { - clock-frequency = <48000000>; -}; diff --git a/sys/gnu/dts/arm/r7s9210.dtsi b/sys/gnu/dts/arm/r7s9210.dtsi deleted file mode 100644 index 72b79770e33..00000000000 --- a/sys/gnu/dts/arm/r7s9210.dtsi +++ /dev/null @@ -1,504 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the R7S9210 SoC - * - * Copyright (C) 2018 Renesas Electronics Corporation - * - */ - -#include -#include - -/ { - compatible = "renesas,r7s9210"; - interrupt-parent = <&gic>; - #address-cells = <1>; - #size-cells = <1>; - - /* External clocks */ - extal_clk: extal { - #clock-cells = <0>; - compatible = "fixed-clock"; - /* Value must be set by board */ - clock-frequency = <0>; - }; - - rtc_x1_clk: rtc_x1 { - #clock-cells = <0>; - compatible = "fixed-clock"; - /* If clk present, value (32678) must be set by board */ - clock-frequency = <0>; - }; - - usb_x1_clk: usb_x1 { - #clock-cells = <0>; - compatible = "fixed-clock"; - /* If clk present, value (48000000) must be set by board */ - clock-frequency = <0>; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - clock-frequency = <528000000>; - next-level-cache = <&L2>; - }; - }; - - soc { - compatible = "simple-bus"; - interrupt-parent = <&gic>; - - #address-cells = <1>; - #size-cells = <1>; - ranges; - - L2: cache-controller@1f003000 { - compatible = "arm,pl310-cache"; - reg = <0x1f003000 0x1000>; - interrupts = ; - arm,early-bresp-disable; - arm,full-line-zero-disable; - cache-unified; - cache-level = <2>; - }; - - scif0: serial@e8007000 { - compatible = "renesas,scif-r7s9210"; - reg = <0xe8007000 0x18>; - interrupts = , - , - , - , - , - ; - interrupt-names = "eri", "rxi", "txi", - "bri", "dri", "tei"; - clocks = <&cpg CPG_MOD 47>; - clock-names = "fck"; - power-domains = <&cpg>; - status = "disabled"; - }; - - scif1: serial@e8007800 { - compatible = "renesas,scif-r7s9210"; - reg = <0xe8007800 0x18>; - interrupts = , - , - , - , - , - ; - interrupt-names = "eri", "rxi", "txi", - "bri", "dri", "tei"; - clocks = <&cpg CPG_MOD 46>; - clock-names = "fck"; - power-domains = <&cpg>; - status = "disabled"; - }; - - scif2: serial@e8008000 { - compatible = "renesas,scif-r7s9210"; - reg = <0xe8008000 0x18>; - interrupts = , - , - , - , - , - ; - interrupt-names = "eri", "rxi", "txi", - "bri", "dri", "tei"; - clocks = <&cpg CPG_MOD 45>; - clock-names = "fck"; - power-domains = <&cpg>; - status = "disabled"; - }; - - scif3: serial@e8008800 { - compatible = "renesas,scif-r7s9210"; - reg = <0xe8008800 0x18>; - interrupts = , - , - , - , - , - ; - interrupt-names = "eri", "rxi", "txi", - "bri", "dri", "tei"; - clocks = <&cpg CPG_MOD 44>; - clock-names = "fck"; - power-domains = <&cpg>; - status = "disabled"; - }; - - scif4: serial@e8009000 { - compatible = "renesas,scif-r7s9210"; - reg = <0xe8009000 0x18>; - interrupts = , - , - , - , - , - ; - interrupt-names = "eri", "rxi", "txi", - "bri", "dri", "tei"; - clocks = <&cpg CPG_MOD 43>; - clock-names = "fck"; - power-domains = <&cpg>; - status = "disabled"; - }; - - spi0: spi@e800c800 { - compatible = "renesas,rspi-r7s9210", "renesas,rspi-rz"; - reg = <0xe800c800 0x24>; - interrupts = , - , - ; - interrupt-names = "error", "rx", "tx"; - clocks = <&cpg CPG_MOD 97>; - power-domains = <&cpg>; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi1: spi@e800d000 { - compatible = "renesas,rspi-r7s9210", "renesas,rspi-rz"; - reg = <0xe800d000 0x24>; - interrupts = , - , - ; - interrupt-names = "error", "rx", "tx"; - clocks = <&cpg CPG_MOD 96>; - power-domains = <&cpg>; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi2: spi@e800d800 { - compatible = "renesas,rspi-r7s9210", "renesas,rspi-rz"; - reg = <0xe800d800 0x24>; - interrupts = , - , - ; - interrupt-names = "error", "rx", "tx"; - clocks = <&cpg CPG_MOD 95>; - power-domains = <&cpg>; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - ether0: ethernet@e8204000 { - compatible = "renesas,ether-r7s9210"; - reg = <0xe8204000 0x200>; - interrupts = ; - clocks = <&cpg CPG_MOD 65>; - power-domains = <&cpg>; - - phy-mode = "rmii"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - ether1: ethernet@e8204200 { - compatible = "renesas,ether-r7s9210"; - reg = <0xe8204200 0x200>; - interrupts = ; - clocks = <&cpg CPG_MOD 64>; - power-domains = <&cpg>; - phy-mode = "rmii"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c0: i2c@e803a000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,riic-r7s9210", "renesas,riic-rz"; - reg = <0xe803a000 0x44>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 87>; - power-domains = <&cpg>; - clock-frequency = <100000>; - status = "disabled"; - }; - - i2c1: i2c@e803a400 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,riic-r7s9210", "renesas,riic-rz"; - reg = <0xe803a400 0x44>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 86>; - power-domains = <&cpg>; - clock-frequency = <100000>; - status = "disabled"; - }; - - i2c2: i2c@e803a800 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,riic-r7s9210", "renesas,riic-rz"; - reg = <0xe803a800 0x44>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 85>; - power-domains = <&cpg>; - clock-frequency = <100000>; - status = "disabled"; - }; - - i2c3: i2c@e803ac00 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,riic-r7s9210", "renesas,riic-rz"; - reg = <0xe803ac00 0x44>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 84>; - power-domains = <&cpg>; - clock-frequency = <100000>; - status = "disabled"; - }; - - ostm0: timer@e803b000 { - compatible = "renesas,r7s9210-ostm", "renesas,ostm"; - reg = <0xe803b000 0x30>; - interrupts = ; - clocks = <&cpg CPG_MOD 36>; - clock-names = "ostm0"; - power-domains = <&cpg>; - status = "disabled"; - }; - - ostm1: timer@e803c000 { - compatible = "renesas,r7s9210-ostm", "renesas,ostm"; - reg = <0xe803c000 0x30>; - interrupts = ; - clocks = <&cpg CPG_MOD 35>; - clock-names = "ostm1"; - power-domains = <&cpg>; - status = "disabled"; - }; - - ostm2: timer@e803d000 { - compatible = "renesas,r7s9210-ostm", "renesas,ostm"; - reg = <0xe803d000 0x30>; - interrupts = ; - clocks = <&cpg CPG_MOD 34>; - clock-names = "ostm2"; - power-domains = <&cpg>; - status = "disabled"; - }; - - ohci0: usb@e8218000 { - compatible = "generic-ohci"; - reg = <0xe8218000 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 61>; - phys = <&usb2_phy0>; - phy-names = "usb"; - power-domains = <&cpg>; - status = "disabled"; - }; - - ehci0: usb@e8218100 { - compatible = "generic-ehci"; - reg = <0xe8218100 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 61>; - phys = <&usb2_phy0>; - phy-names = "usb"; - power-domains = <&cpg>; - status = "disabled"; - }; - - usb2_phy0: usb-phy@e8218200 { - compatible = "renesas,usb2-phy-r7s9210", "renesas,rcar-gen3-usb2-phy"; - reg = <0xe8218200 0x700>; - interrupts = ; - clocks = <&cpg CPG_MOD 61>, <&usb_x1_clk>; - clock-names = "fck", "usb_x1"; - power-domains = <&cpg>; - #phy-cells = <0>; - status = "disabled"; - }; - - usbhs0: usb@e8219000 { - compatible = "renesas,usbhs-r7s9210", "renesas,rza2-usbhs"; - reg = <0xe8219000 0x724>; - interrupts = ; - clocks = <&cpg CPG_MOD 61>; - renesas,buswait = <7>; - phys = <&usb2_phy0>; - phy-names = "usb"; - power-domains = <&cpg>; - status = "disabled"; - }; - - ohci1: usb@e821a000 { - compatible = "generic-ohci"; - reg = <0xe821a000 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 60>; - phys = <&usb2_phy1>; - phy-names = "usb"; - power-domains = <&cpg>; - status = "disabled"; - }; - - ehci1: usb@e821a100 { - compatible = "generic-ehci"; - reg = <0xe821a100 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 60>; - phys = <&usb2_phy1>; - phy-names = "usb"; - power-domains = <&cpg>; - status = "disabled"; - }; - - usb2_phy1: usb-phy@e821a200 { - compatible = "renesas,usb2-phy-r7s9210", "renesas,rcar-gen3-usb2-phy"; - reg = <0xe821a200 0x700>; - interrupts = ; - clocks = <&cpg CPG_MOD 60>, <&usb_x1_clk>; - clock-names = "fck", "usb_x1"; - power-domains = <&cpg>; - #phy-cells = <0>; - status = "disabled"; - }; - - usbhs1: usb@e821b000 { - compatible = "renesas,usbhs-r7s9210", "renesas,rza2-usbhs"; - reg = <0xe821b000 0x724>; - interrupts = ; - clocks = <&cpg CPG_MOD 60>; - renesas,buswait = <7>; - phys = <&usb2_phy1>; - phy-names = "usb"; - power-domains = <&cpg>; - status = "disabled"; - }; - - sdhi0: sd@e8228000 { - compatible = "renesas,sdhi-r7s9210"; - reg = <0xe8228000 0x8c0>; - interrupts = ; - clocks = <&cpg CPG_MOD 103>, <&cpg CPG_MOD 102>; - clock-names = "core", "cd"; - power-domains = <&cpg>; - cap-sd-highspeed; - cap-sdio-irq; - status = "disabled"; - }; - - sdhi1: sd@e822a000 { - compatible = "renesas,sdhi-r7s9210"; - reg = <0xe822a000 0x8c0>; - interrupts = ; - clocks = <&cpg CPG_MOD 101>, <&cpg CPG_MOD 100>; - clock-names = "core", "cd"; - power-domains = <&cpg>; - cap-sd-highspeed; - cap-sdio-irq; - status = "disabled"; - }; - - gic: interrupt-controller@e8221000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0xe8221000 0x1000>, - <0xe8222000 0x1000>; - }; - - cpg: clock-controller@fcfe0010 { - compatible = "renesas,r7s9210-cpg-mssr"; - reg = <0xfcfe0010 0x455>; - clocks = <&extal_clk>; - clock-names = "extal"; - #clock-cells = <2>; - #power-domain-cells = <0>; - }; - - wdt: watchdog@fcfe7000 { - compatible = "renesas,r7s9210-wdt", "renesas,rza-wdt"; - reg = <0xfcfe7000 0x26>; - interrupts = ; - clocks = <&cpg CPG_CORE R7S9210_CLK_P0>; - }; - - bsid: chipid@fcfe8004 { - compatible = "renesas,bsid"; - reg = <0xfcfe8004 4>; - }; - - irqc: interrupt-controller@fcfef800 { - compatible = "renesas,r7s9210-irqc", - "renesas,rza1-irqc"; - #interrupt-cells = <2>; - #address-cells = <0>; - interrupt-controller; - reg = <0xfcfef800 0x6>; - interrupt-map = - <0 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, - <1 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, - <2 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, - <3 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, - <4 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, - <5 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, - <6 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, - <7 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; - interrupt-map-mask = <7 0>; - }; - - pinctrl: pin-controller@fcffe000 { - compatible = "renesas,r7s9210-pinctrl"; - reg = <0xfcffe000 0x1000>; - - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl 0 0 176>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/r8a73a4-ape6evm.dts b/sys/gnu/dts/arm/r8a73a4-ape6evm.dts deleted file mode 100644 index a5351ddbf50..00000000000 --- a/sys/gnu/dts/arm/r8a73a4-ape6evm.dts +++ /dev/null @@ -1,275 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the APE6EVM board - * - * Copyright (C) 2013 Renesas Solutions Corp. - */ - -/dts-v1/; -#include "r8a73a4.dtsi" -#include -#include - -/ { - model = "APE6EVM"; - compatible = "renesas,ape6evm", "renesas,r8a73a4"; - - aliases { - serial0 = &scifa0; - }; - - chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; - stdout-path = "serial0:115200n8"; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0 0x40000000 0 0x40000000>; - }; - - memory@200000000 { - device_type = "memory"; - reg = <2 0x00000000 0 0x40000000>; - }; - - vcc_mmc0: regulator-mmc0 { - compatible = "regulator-fixed"; - regulator-name = "MMC0 Vcc"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - vcc_sdhi0: regulator-sdhi0 { - compatible = "regulator-fixed"; - - regulator-name = "SDHI0 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&pfc 76 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - /* Common 1.8V and 3.3V rails, used by several devices on APE6EVM */ - ape6evm_fixed_1v8: regulator-1v8 { - compatible = "regulator-fixed"; - regulator-name = "1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ape6evm_fixed_3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - leds { - compatible = "gpio-leds"; - led1 { - gpios = <&pfc 28 GPIO_ACTIVE_HIGH>; - label = "GNSS_EN"; - }; - led2 { - gpios = <&pfc 126 GPIO_ACTIVE_HIGH>; - label = "NFC_NRST"; - }; - led3 { - gpios = <&pfc 132 GPIO_ACTIVE_HIGH>; - label = "GNSS_NRST"; - }; - led4 { - gpios = <&pfc 232 GPIO_ACTIVE_HIGH>; - label = "BT_WAKEUP"; - }; - led5 { - gpios = <&pfc 250 GPIO_ACTIVE_HIGH>; - label = "STROBE"; - }; - led6 { - gpios = <&pfc 288 GPIO_ACTIVE_HIGH>; - label = "BBRESETOUT"; - }; - }; - - keyboard { - compatible = "gpio-keys"; - - pinctrl-names = "default"; - pinctrl-0 = <&keyboard_pins>; - - zero-key { - gpios = <&pfc 324 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "S16"; - wakeup-source; - }; - - menu-key { - gpios = <&pfc 325 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "S17"; - }; - - home-key { - gpios = <&pfc 326 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "S18"; - }; - - back-key { - gpios = <&pfc 327 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "S19"; - }; - - volup-key { - gpios = <&pfc 328 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "S20"; - }; - - voldown-key { - gpios = <&pfc 329 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "S21"; - }; - }; -}; - -&i2c5 { - status = "okay"; - vdd_dvfs: regulator@1b { - compatible = "maxim,max8973"; - reg = <0x1b>; - - regulator-min-microvolt = <935000>; - regulator-max-microvolt = <1200000>; - regulator-boot-on; - regulator-always-on; - }; -}; - -&cpu0 { - cpu0-supply = <&vdd_dvfs>; - operating-points = < - /* kHz uV */ - 1950000 1115000 - 1462500 995000 - >; - voltage-tolerance = <1>; /* 1% */ -}; - -&bsc { - flash@0 { - compatible = "cfi-flash", "mtd-rom"; - reg = <0x0 0x08000000>; - bank-width = <2>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "uboot"; - reg = <0x00000000 0x00040000>; - read-only; - }; - partition@40000 { - label = "uboot-env"; - reg = <0x00040000 0x00040000>; - read-only; - }; - partition@80000 { - label = "flash"; - reg = <0x00080000 0x07f80000>; - }; - }; - }; - - ethernet@8000000 { - compatible = "smsc,lan9220", "smsc,lan9115"; - reg = <0x08000000 0x1000>; - interrupt-parent = <&irqc1>; - interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; - phy-mode = "mii"; - reg-io-width = <4>; - smsc,irq-active-high; - smsc,irq-push-pull; - vdd33a-supply = <&ape6evm_fixed_3v3>; - vddvario-supply = <&ape6evm_fixed_1v8>; - }; -}; - -&cmt1 { - status = "okay"; -}; - -&pfc { - scifa0_pins: scifa0 { - groups = "scifa0_data"; - function = "scifa0"; - }; - - mmc0_pins: mmc0 { - groups = "mmc0_data8", "mmc0_ctrl"; - function = "mmc0"; - }; - - sdhi0_pins: sd0 { - groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd"; - function = "sdhi0"; - }; - - sdhi1_pins: sd1 { - groups = "sdhi1_data4", "sdhi1_ctrl"; - function = "sdhi1"; - }; - - keyboard_pins: keyboard { - pins = "PORT324", "PORT325", "PORT326", "PORT327", "PORT328", - "PORT329"; - bias-pull-up; - }; -}; - -&mmcif0 { - vmmc-supply = <&vcc_mmc0>; - bus-width = <8>; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; - status = "okay"; -}; - -&scifa0 { - pinctrl-0 = <&scifa0_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&sdhi0 { - vmmc-supply = <&vcc_sdhi0>; - bus-width = <4>; - disable-wp; - pinctrl-names = "default"; - pinctrl-0 = <&sdhi0_pins>; - status = "okay"; -}; - -&sdhi1 { - vmmc-supply = <&ape6evm_fixed_3v3>; - bus-width = <4>; - broken-cd; - disable-wp; - pinctrl-names = "default"; - pinctrl-0 = <&sdhi1_pins>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/r8a73a4.dtsi b/sys/gnu/dts/arm/r8a73a4.dtsi deleted file mode 100644 index a5cd31229fb..00000000000 --- a/sys/gnu/dts/arm/r8a73a4.dtsi +++ /dev/null @@ -1,898 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the r8a73a4 SoC - * - * Copyright (C) 2013 Renesas Solutions Corp. - * Copyright (C) 2013 Magnus Damm - */ - -#include -#include -#include - -/ { - compatible = "renesas,r8a73a4"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0>; - clocks = <&cpg_clocks R8A73A4_CLK_Z>; - clock-frequency = <1500000000>; - power-domains = <&pd_a2sl>; - next-level-cache = <&L2_CA15>; - }; - - L2_CA15: cache-controller-0 { - compatible = "cache"; - clocks = <&cpg_clocks R8A73A4_CLK_Z>; - power-domains = <&pd_a3sm>; - cache-unified; - cache-level = <2>; - }; - - L2_CA7: cache-controller-1 { - compatible = "cache"; - clocks = <&cpg_clocks R8A73A4_CLK_Z2>; - power-domains = <&pd_a3km>; - cache-unified; - cache-level = <2>; - }; - }; - - ptm { - compatible = "arm,coresight-etm3x"; - power-domains = <&pd_d4>; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; - }; - - dbsc1: memory-controller@e6790000 { - compatible = "renesas,dbsc-r8a73a4"; - reg = <0 0xe6790000 0 0x10000>; - power-domains = <&pd_a3bc>; - }; - - dbsc2: memory-controller@e67a0000 { - compatible = "renesas,dbsc-r8a73a4"; - reg = <0 0xe67a0000 0 0x10000>; - power-domains = <&pd_a3bc>; - }; - - dmac: dma-multiplexer { - compatible = "renesas,shdma-mux"; - #dma-cells = <1>; - dma-channels = <20>; - dma-requests = <256>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - dma0: dma-controller@e6700020 { - compatible = "renesas,shdma-r8a73a4"; - reg = <0 0xe6700020 0 0x89e0>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15", - "ch16", "ch17", "ch18", "ch19"; - clocks = <&mstp2_clks R8A73A4_CLK_DMAC>; - power-domains = <&pd_a3sp>; - }; - }; - - i2c5: i2c@e60b0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; - reg = <0 0xe60b0000 0 0x428>; - interrupts = ; - clocks = <&mstp4_clks R8A73A4_CLK_IIC5>; - power-domains = <&pd_a3sp>; - - status = "disabled"; - }; - - cmt1: timer@e6130000 { - compatible = "renesas,r8a73a4-cmt1", "renesas,rcar-gen2-cmt1"; - reg = <0 0xe6130000 0 0x1004>; - interrupts = ; - clocks = <&mstp3_clks R8A73A4_CLK_CMT1>; - clock-names = "fck"; - power-domains = <&pd_c5>; - status = "disabled"; - }; - - irqc0: interrupt-controller@e61c0000 { - compatible = "renesas,irqc-r8a73a4", "renesas,irqc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0 0xe61c0000 0 0x200>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - clocks = <&mstp4_clks R8A73A4_CLK_IRQC>; - power-domains = <&pd_c4>; - }; - - irqc1: interrupt-controller@e61c0200 { - compatible = "renesas,irqc-r8a73a4", "renesas,irqc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0 0xe61c0200 0 0x200>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - clocks = <&mstp4_clks R8A73A4_CLK_IRQC>; - power-domains = <&pd_c4>; - }; - - pfc: pin-controller@e6050000 { - compatible = "renesas,pfc-r8a73a4"; - reg = <0 0xe6050000 0 0x9000>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = - <&pfc 0 0 31>, <&pfc 32 32 9>, - <&pfc 64 64 22>, <&pfc 96 96 31>, - <&pfc 128 128 7>, <&pfc 160 160 19>, - <&pfc 192 192 31>, <&pfc 224 224 27>, - <&pfc 256 256 28>, <&pfc 288 288 21>, - <&pfc 320 320 10>; - interrupts-extended = - <&irqc0 0 0>, <&irqc0 1 0>, <&irqc0 2 0>, <&irqc0 3 0>, - <&irqc0 4 0>, <&irqc0 5 0>, <&irqc0 6 0>, <&irqc0 7 0>, - <&irqc0 8 0>, <&irqc0 9 0>, <&irqc0 10 0>, <&irqc0 11 0>, - <&irqc0 12 0>, <&irqc0 13 0>, <&irqc0 14 0>, <&irqc0 15 0>, - <&irqc0 16 0>, <&irqc0 17 0>, <&irqc0 18 0>, <&irqc0 19 0>, - <&irqc0 20 0>, <&irqc0 21 0>, <&irqc0 22 0>, <&irqc0 23 0>, - <&irqc0 24 0>, <&irqc0 25 0>, <&irqc0 26 0>, <&irqc0 27 0>, - <&irqc0 28 0>, <&irqc0 29 0>, <&irqc0 30 0>, <&irqc0 31 0>, - <&irqc1 0 0>, <&irqc1 1 0>, <&irqc1 2 0>, <&irqc1 3 0>, - <&irqc1 4 0>, <&irqc1 5 0>, <&irqc1 6 0>, <&irqc1 7 0>, - <&irqc1 8 0>, <&irqc1 9 0>, <&irqc1 10 0>, <&irqc1 11 0>, - <&irqc1 12 0>, <&irqc1 13 0>, <&irqc1 14 0>, <&irqc1 15 0>, - <&irqc1 16 0>, <&irqc1 17 0>, <&irqc1 18 0>, <&irqc1 19 0>, - <&irqc1 20 0>, <&irqc1 21 0>, <&irqc1 22 0>, <&irqc1 23 0>, - <&irqc1 24 0>, <&irqc1 25 0>; - power-domains = <&pd_c5>; - }; - - thermal@e61f0000 { - compatible = "renesas,thermal-r8a73a4", "renesas,rcar-thermal"; - reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>, - <0 0xe61f0200 0 0x38>, <0 0xe61f0300 0 0x38>; - interrupts = ; - clocks = <&mstp5_clks R8A73A4_CLK_THERMAL>; - power-domains = <&pd_c5>; - }; - - i2c0: i2c@e6500000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; - reg = <0 0xe6500000 0 0x428>; - interrupts = ; - clocks = <&mstp3_clks R8A73A4_CLK_IIC0>; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - i2c1: i2c@e6510000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; - reg = <0 0xe6510000 0 0x428>; - interrupts = ; - clocks = <&mstp3_clks R8A73A4_CLK_IIC1>; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - i2c2: i2c@e6520000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; - reg = <0 0xe6520000 0 0x428>; - interrupts = ; - clocks = <&mstp3_clks R8A73A4_CLK_IIC2>; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - i2c3: i2c@e6530000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; - reg = <0 0xe6530000 0 0x428>; - interrupts = ; - clocks = <&mstp4_clks R8A73A4_CLK_IIC3>; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - i2c4: i2c@e6540000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; - reg = <0 0xe6540000 0 0x428>; - interrupts = ; - clocks = <&mstp4_clks R8A73A4_CLK_IIC4>; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - i2c6: i2c@e6550000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; - reg = <0 0xe6550000 0 0x428>; - interrupts = ; - clocks = <&mstp3_clks R8A73A4_CLK_IIC6>; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - i2c7: i2c@e6560000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; - reg = <0 0xe6560000 0 0x428>; - interrupts = ; - clocks = <&mstp3_clks R8A73A4_CLK_IIC7>; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - i2c8: i2c@e6570000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; - reg = <0 0xe6570000 0 0x428>; - interrupts = ; - clocks = <&mstp5_clks R8A73A4_CLK_IIC8>; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - scifb0: serial@e6c20000 { - compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; - reg = <0 0xe6c20000 0 0x100>; - interrupts = ; - clocks = <&mstp2_clks R8A73A4_CLK_SCIFB0>; - clock-names = "fck"; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - scifb1: serial@e6c30000 { - compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; - reg = <0 0xe6c30000 0 0x100>; - interrupts = ; - clocks = <&mstp2_clks R8A73A4_CLK_SCIFB1>; - clock-names = "fck"; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - scifa0: serial@e6c40000 { - compatible = "renesas,scifa-r8a73a4", "renesas,scifa"; - reg = <0 0xe6c40000 0 0x100>; - interrupts = ; - clocks = <&mstp2_clks R8A73A4_CLK_SCIFA0>; - clock-names = "fck"; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - scifa1: serial@e6c50000 { - compatible = "renesas,scifa-r8a73a4", "renesas,scifa"; - reg = <0 0xe6c50000 0 0x100>; - interrupts = ; - clocks = <&mstp2_clks R8A73A4_CLK_SCIFA1>; - clock-names = "fck"; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - scifb2: serial@e6ce0000 { - compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; - reg = <0 0xe6ce0000 0 0x100>; - interrupts = ; - clocks = <&mstp2_clks R8A73A4_CLK_SCIFB2>; - clock-names = "fck"; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - scifb3: serial@e6cf0000 { - compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; - reg = <0 0xe6cf0000 0 0x100>; - interrupts = ; - clocks = <&mstp2_clks R8A73A4_CLK_SCIFB3>; - clock-names = "fck"; - power-domains = <&pd_c4>; - status = "disabled"; - }; - - sdhi0: sd@ee100000 { - compatible = "renesas,sdhi-r8a73a4"; - reg = <0 0xee100000 0 0x100>; - interrupts = ; - clocks = <&mstp3_clks R8A73A4_CLK_SDHI0>; - power-domains = <&pd_a3sp>; - cap-sd-highspeed; - status = "disabled"; - }; - - sdhi1: sd@ee120000 { - compatible = "renesas,sdhi-r8a73a4"; - reg = <0 0xee120000 0 0x100>; - interrupts = ; - clocks = <&mstp3_clks R8A73A4_CLK_SDHI1>; - power-domains = <&pd_a3sp>; - cap-sd-highspeed; - status = "disabled"; - }; - - sdhi2: sd@ee140000 { - compatible = "renesas,sdhi-r8a73a4"; - reg = <0 0xee140000 0 0x100>; - interrupts = ; - clocks = <&mstp3_clks R8A73A4_CLK_SDHI2>; - power-domains = <&pd_a3sp>; - cap-sd-highspeed; - status = "disabled"; - }; - - mmcif0: mmc@ee200000 { - compatible = "renesas,mmcif-r8a73a4", "renesas,sh-mmcif"; - reg = <0 0xee200000 0 0x80>; - interrupts = ; - clocks = <&mstp3_clks R8A73A4_CLK_MMCIF0>; - power-domains = <&pd_a3sp>; - reg-io-width = <4>; - status = "disabled"; - }; - - mmcif1: mmc@ee220000 { - compatible = "renesas,mmcif-r8a73a4", "renesas,sh-mmcif"; - reg = <0 0xee220000 0 0x80>; - interrupts = ; - clocks = <&mstp3_clks R8A73A4_CLK_MMCIF1>; - power-domains = <&pd_a3sp>; - reg-io-width = <4>; - status = "disabled"; - }; - - gic: interrupt-controller@f1001000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0 0xf1001000 0 0x1000>, - <0 0xf1002000 0 0x2000>, - <0 0xf1004000 0 0x2000>, - <0 0xf1006000 0 0x2000>; - interrupts = ; - clocks = <&mstp4_clks R8A73A4_CLK_INTC_SYS>; - clock-names = "clk"; - power-domains = <&pd_c4>; - }; - - bsc: bus@fec10000 { - compatible = "renesas,bsc-r8a73a4", "renesas,bsc", - "simple-pm-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0 0x20000000>; - reg = <0 0xfec10000 0 0x400>; - clocks = <&zb_clk>; - power-domains = <&pd_c4>; - }; - - clocks { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - /* External root clocks */ - extalr_clk: extalr { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - extal1_clk: extal1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - extal2_clk: extal2 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <48000000>; - }; - fsiack_clk: fsiack { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - fsibck_clk: fsibck { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - /* Special CPG clocks */ - cpg_clocks: cpg_clocks@e6150000 { - compatible = "renesas,r8a73a4-cpg-clocks"; - reg = <0 0xe6150000 0 0x10000>; - clocks = <&extal1_clk>, <&extal2_clk>; - #clock-cells = <1>; - clock-output-names = "main", "pll0", "pll1", "pll2", - "pll2s", "pll2h", "z", "z2", - "i", "m3", "b", "m1", "m2", - "zx", "zs", "hp"; - }; - - /* Variable factor clocks (DIV6) */ - zb_clk: zb_clk@e6150010 { - compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe6150010 0 4>; - clocks = <&pll1_div2_clk>, <0>, - <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>; - #clock-cells = <0>; - clock-output-names = "zb"; - }; - sdhi0_clk: sdhi0ck@e6150074 { - compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe6150074 0 4>; - clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, - <0>, <&extal2_clk>; - #clock-cells = <0>; - }; - sdhi1_clk: sdhi1ck@e6150078 { - compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe6150078 0 4>; - clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, - <0>, <&extal2_clk>; - #clock-cells = <0>; - }; - sdhi2_clk: sdhi2ck@e615007c { - compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe615007c 0 4>; - clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, - <0>, <&extal2_clk>; - #clock-cells = <0>; - }; - mmc0_clk: mmc0@e6150240 { - compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe6150240 0 4>; - clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, - <0>, <&extal2_clk>; - #clock-cells = <0>; - }; - mmc1_clk: mmc1@e6150244 { - compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe6150244 0 4>; - clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, - <0>, <&extal2_clk>; - #clock-cells = <0>; - }; - vclk1_clk: vclk1@e6150008 { - compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe6150008 0 4>; - clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, - <0>, <&extal2_clk>, <&main_div2_clk>, - <&extalr_clk>, <0>, <0>; - #clock-cells = <0>; - }; - vclk2_clk: vclk2@e615000c { - compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe615000c 0 4>; - clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, - <0>, <&extal2_clk>, <&main_div2_clk>, - <&extalr_clk>, <0>, <0>; - #clock-cells = <0>; - }; - vclk3_clk: vclk3@e615001c { - compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe615001c 0 4>; - clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, - <0>, <&extal2_clk>, <&main_div2_clk>, - <&extalr_clk>, <0>, <0>; - #clock-cells = <0>; - }; - vclk4_clk: vclk4@e6150014 { - compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe6150014 0 4>; - clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, - <0>, <&extal2_clk>, <&main_div2_clk>, - <&extalr_clk>, <0>, <0>; - #clock-cells = <0>; - }; - vclk5_clk: vclk5@e6150034 { - compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe6150034 0 4>; - clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, - <0>, <&extal2_clk>, <&main_div2_clk>, - <&extalr_clk>, <0>, <0>; - #clock-cells = <0>; - }; - fsia_clk: fsia@e6150018 { - compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe6150018 0 4>; - clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, - <&fsiack_clk>, <0>; - #clock-cells = <0>; - }; - fsib_clk: fsib@e6150090 { - compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe6150090 0 4>; - clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, - <&fsibck_clk>, <0>; - #clock-cells = <0>; - }; - mp_clk: mp@e6150080 { - compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe6150080 0 4>; - clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, - <&extal2_clk>, <&extal2_clk>; - #clock-cells = <0>; - }; - m4_clk: m4@e6150098 { - compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe6150098 0 4>; - clocks = <&cpg_clocks R8A73A4_CLK_PLL2S>; - #clock-cells = <0>; - }; - hsi_clk: hsi@e615026c { - compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe615026c 0 4>; - clocks = <&cpg_clocks R8A73A4_CLK_PLL2H>, <&pll1_div2_clk>, - <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>; - #clock-cells = <0>; - }; - spuv_clk: spuv@e6150094 { - compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe6150094 0 4>; - clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, - <&extal2_clk>, <&extal2_clk>; - #clock-cells = <0>; - }; - - /* Fixed factor clocks */ - main_div2_clk: main_div2 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A73A4_CLK_MAIN>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - pll0_div2_clk: pll0_div2 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A73A4_CLK_PLL0>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - pll1_div2_clk: pll1_div2 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A73A4_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - extal1_div2_clk: extal1_div2 { - compatible = "fixed-factor-clock"; - clocks = <&extal1_clk>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - - /* Gate clocks */ - mstp2_clks: mstp2_clks@e6150138 { - compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; - clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, - <&mp_clk>, <&mp_clk>, <&cpg_clocks R8A73A4_CLK_HP>; - #clock-cells = <1>; - clock-indices = < - R8A73A4_CLK_SCIFA0 R8A73A4_CLK_SCIFA1 - R8A73A4_CLK_SCIFB0 R8A73A4_CLK_SCIFB1 - R8A73A4_CLK_SCIFB2 R8A73A4_CLK_SCIFB3 - R8A73A4_CLK_DMAC - >; - clock-output-names = - "scifa0", "scifa1", "scifb0", "scifb1", - "scifb2", "scifb3", "dmac"; - }; - mstp3_clks: mstp3_clks@e615013c { - compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; - clocks = <&cpg_clocks R8A73A4_CLK_HP>, <&mmc1_clk>, - <&sdhi2_clk>, <&sdhi1_clk>, <&sdhi0_clk>, - <&mmc0_clk>, <&cpg_clocks R8A73A4_CLK_HP>, - <&cpg_clocks R8A73A4_CLK_HP>, <&cpg_clocks - R8A73A4_CLK_HP>, <&cpg_clocks - R8A73A4_CLK_HP>, <&extalr_clk>; - #clock-cells = <1>; - clock-indices = < - R8A73A4_CLK_IIC2 R8A73A4_CLK_MMCIF1 - R8A73A4_CLK_SDHI2 R8A73A4_CLK_SDHI1 - R8A73A4_CLK_SDHI0 R8A73A4_CLK_MMCIF0 - R8A73A4_CLK_IIC6 R8A73A4_CLK_IIC7 - R8A73A4_CLK_IIC0 R8A73A4_CLK_IIC1 - R8A73A4_CLK_CMT1 - >; - clock-output-names = - "iic2", "mmcif1", "sdhi2", "sdhi1", "sdhi0", - "mmcif0", "iic6", "iic7", "iic0", "iic1", - "cmt1"; - }; - mstp4_clks: mstp4_clks@e6150140 { - compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>; - clocks = <&main_div2_clk>, <&cpg_clocks R8A73A4_CLK_ZS>, - <&main_div2_clk>, - <&cpg_clocks R8A73A4_CLK_HP>, - <&cpg_clocks R8A73A4_CLK_HP>; - #clock-cells = <1>; - clock-indices = < - R8A73A4_CLK_IRQC R8A73A4_CLK_INTC_SYS - R8A73A4_CLK_IIC5 R8A73A4_CLK_IIC4 - R8A73A4_CLK_IIC3 - >; - clock-output-names = - "irqc", "intc-sys", "iic5", "iic4", "iic3"; - }; - mstp5_clks: mstp5_clks@e6150144 { - compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; - clocks = <&extal2_clk>, <&cpg_clocks R8A73A4_CLK_HP>; - #clock-cells = <1>; - clock-indices = < - R8A73A4_CLK_THERMAL R8A73A4_CLK_IIC8 - >; - clock-output-names = - "thermal", "iic8"; - }; - }; - - prr: chipid@ff000044 { - compatible = "renesas,prr"; - reg = <0 0xff000044 0 4>; - }; - - sysc: system-controller@e6180000 { - compatible = "renesas,sysc-r8a73a4", "renesas,sysc-rmobile"; - reg = <0 0xe6180000 0 0x8000>, <0 0xe6188000 0 0x8000>; - - pm-domains { - pd_c5: c5 { - #address-cells = <1>; - #size-cells = <0>; - #power-domain-cells = <0>; - - pd_c4: c4@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - #power-domain-cells = <0>; - - pd_a3sg: a3sg@16 { - reg = <16>; - #power-domain-cells = <0>; - }; - - pd_a3ex: a3ex@17 { - reg = <17>; - #power-domain-cells = <0>; - }; - - pd_a3sp: a3sp@18 { - reg = <18>; - #address-cells = <1>; - #size-cells = <0>; - #power-domain-cells = <0>; - - pd_a2us: a2us@19 { - reg = <19>; - #power-domain-cells = <0>; - }; - }; - - pd_a3sm: a3sm@20 { - reg = <20>; - #address-cells = <1>; - #size-cells = <0>; - #power-domain-cells = <0>; - - pd_a2sl: a2sl@21 { - reg = <21>; - #power-domain-cells = <0>; - }; - }; - - pd_a3km: a3km@22 { - reg = <22>; - #address-cells = <1>; - #size-cells = <0>; - #power-domain-cells = <0>; - - pd_a2kl: a2kl@23 { - reg = <23>; - #power-domain-cells = <0>; - }; - }; - }; - - pd_c4ma: c4ma@1 { - reg = <1>; - #power-domain-cells = <0>; - }; - - pd_c4cl: c4cl@2 { - reg = <2>; - #power-domain-cells = <0>; - }; - - pd_d4: d4@3 { - reg = <3>; - #power-domain-cells = <0>; - }; - - pd_a4bc: a4bc@4 { - reg = <4>; - #address-cells = <1>; - #size-cells = <0>; - #power-domain-cells = <0>; - - pd_a3bc: a3bc@5 { - reg = <5>; - #power-domain-cells = <0>; - }; - }; - - pd_a4l: a4l@6 { - reg = <6>; - #power-domain-cells = <0>; - }; - - pd_a4lc: a4lc@7 { - reg = <7>; - #power-domain-cells = <0>; - }; - - pd_a4mp: a4mp@8 { - reg = <8>; - #address-cells = <1>; - #size-cells = <0>; - #power-domain-cells = <0>; - - pd_a3mp: a3mp@9 { - reg = <9>; - #power-domain-cells = <0>; - }; - - pd_a3vc: a3vc@10 { - reg = <10>; - #power-domain-cells = <0>; - }; - }; - - pd_a4sf: a4sf@11 { - reg = <11>; - #power-domain-cells = <0>; - }; - - pd_a3r: a3r@12 { - reg = <12>; - #address-cells = <1>; - #size-cells = <0>; - #power-domain-cells = <0>; - - pd_a2rv: a2rv@13 { - reg = <13>; - #power-domain-cells = <0>; - }; - - pd_a2is: a2is@14 { - reg = <14>; - #power-domain-cells = <0>; - }; - }; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/r8a7740-armadillo800eva.dts b/sys/gnu/dts/arm/r8a7740-armadillo800eva.dts deleted file mode 100644 index d960c2767f6..00000000000 --- a/sys/gnu/dts/arm/r8a7740-armadillo800eva.dts +++ /dev/null @@ -1,315 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the armadillo 800 eva board - * - * Copyright (C) 2012 Renesas Solutions Corp. - */ - -/dts-v1/; -#include "r8a7740.dtsi" -#include -#include -#include -#include - -/ { - model = "armadillo 800 eva"; - compatible = "renesas,armadillo800eva", "renesas,r8a7740"; - - aliases { - serial0 = &scifa1; - }; - - chosen { - bootargs = "earlyprintk ignore_loglevel root=/dev/nfs ip=on rw"; - stdout-path = "serial0:115200n8"; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x20000000>; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - vcc_sdhi0: regulator-vcc-sdhi0 { - compatible = "regulator-fixed"; - - regulator-name = "SDHI0 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&pfc 75 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vccq_sdhi0: regulator-vccq-sdhi0 { - compatible = "regulator-gpio"; - - regulator-name = "SDHI0 VccQ"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_sdhi0>; - - enable-gpio = <&pfc 74 GPIO_ACTIVE_HIGH>; - gpios = <&pfc 17 GPIO_ACTIVE_HIGH>; - states = <3300000 0>, <1800000 1>; - - enable-active-high; - }; - - reg_5p0v: regulator-5p0v { - compatible = "regulator-fixed"; - regulator-name = "fixed-5.0V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - keyboard { - compatible = "gpio-keys"; - - power-key { - gpios = <&pfc 99 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW3"; - wakeup-source; - }; - - back-key { - gpios = <&pfc 100 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW4"; - }; - - menu-key { - gpios = <&pfc 97 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW5"; - }; - - home-key { - gpios = <&pfc 98 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW6"; - }; - }; - - leds { - compatible = "gpio-leds"; - led3 { - gpios = <&pfc 102 GPIO_ACTIVE_HIGH>; - label = "LED3"; - }; - led4 { - gpios = <&pfc 111 GPIO_ACTIVE_HIGH>; - label = "LED4"; - }; - led5 { - gpios = <&pfc 110 GPIO_ACTIVE_HIGH>; - label = "LED5"; - }; - led6 { - gpios = <&pfc 177 GPIO_ACTIVE_HIGH>; - label = "LED6"; - }; - }; - - i2c2: i2c-2 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "i2c-gpio"; - sda-gpios = <&pfc 208 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - scl-gpios = <&pfc 91 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <5>; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&tpu 2 33333 PWM_POLARITY_INVERTED>; - brightness-levels = <0 1 2 4 8 16 32 64 128 255>; - default-brightness-level = <9>; - pinctrl-0 = <&backlight_pins>; - pinctrl-names = "default"; - power-supply = <®_5p0v>; - enable-gpios = <&pfc 61 GPIO_ACTIVE_HIGH>; - }; - - sound { - compatible = "simple-audio-card"; - - simple-audio-card,format = "i2s"; - - simple-audio-card,cpu { - sound-dai = <&sh_fsi2 0>; - bitclock-inversion; - }; - - simple-audio-card,codec { - sound-dai = <&wm8978>; - bitclock-master; - frame-master; - system-clock-frequency = <12288000>; - }; - }; -}; - -ðer { - pinctrl-0 = <ðer_pins>; - pinctrl-names = "default"; - - phy-handle = <&phy0>; - status = "okay"; - - phy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -&extal1_clk { - clock-frequency = <24000000>; -}; -&extal2_clk { - clock-frequency = <48000000>; -}; -&fsibck_clk { - clock-frequency = <12288000>; -}; -&cpg_clocks { - renesas,mode = <0x05>; /* MD_CK0 | MD_CK2 */ -}; - -&cmt1 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - touchscreen@55 { - compatible = "sitronix,st1232"; - reg = <0x55>; - interrupt-parent = <&irqpin1>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - pinctrl-0 = <&st1232_pins>; - pinctrl-names = "default"; - gpios = <&pfc 166 GPIO_ACTIVE_LOW>; - }; - - wm8978: codec@1a { - #sound-dai-cells = <0>; - compatible = "wlf,wm8978"; - reg = <0x1a>; - }; -}; - -&i2c2 { - status = "okay"; - rtc@30 { - compatible = "sii,s35390a"; - reg = <0x30>; - }; -}; - -&pfc { - pinctrl-0 = <&lcd0_pins>; - pinctrl-names = "default"; - - ether_pins: ether { - groups = "gether_mii", "gether_int"; - function = "gether"; - }; - - scifa1_pins: scifa1 { - groups = "scifa1_data"; - function = "scifa1"; - }; - - st1232_pins: touchscreen { - groups = "intc_irq10"; - function = "intc"; - }; - - backlight_pins: backlight { - groups = "tpu0_to2_1"; - function = "tpu0"; - }; - - mmc0_pins: mmc0 { - groups = "mmc0_data8_1", "mmc0_ctrl_1"; - function = "mmc0"; - }; - - sdhi0_pins: sd0 { - groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_wp"; - function = "sdhi0"; - }; - - fsia_pins: sounda { - groups = "fsia_sclk_in", "fsia_mclk_out", - "fsia_data_in_1", "fsia_data_out_0"; - function = "fsia"; - }; - - lcd0_pins: lcd0 { - groups = "lcd0_data24_0", "lcd0_lclk_1", "lcd0_sync"; - function = "lcd0"; - }; - - lcd0_mux { - /* DBGMD/LCDC0/FSIA MUX */ - gpio-hog; - gpios = <176 0>; - output-high; - }; -}; - -&tpu { - status = "okay"; -}; - -&mmcif0 { - pinctrl-0 = <&mmc0_pins>; - pinctrl-names = "default"; - - vmmc-supply = <®_3p3v>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&scifa1 { - pinctrl-0 = <&scifa1_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&sdhi0 { - pinctrl-0 = <&sdhi0_pins>; - pinctrl-names = "default"; - - vmmc-supply = <&vcc_sdhi0>; - vqmmc-supply = <&vccq_sdhi0>; - bus-width = <4>; - cd-gpios = <&pfc 167 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&sh_fsi2 { - pinctrl-0 = <&fsia_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&tmu0 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/r8a7740.dtsi b/sys/gnu/dts/arm/r8a7740.dtsi deleted file mode 100644 index ebc1ff64f53..00000000000 --- a/sys/gnu/dts/arm/r8a7740.dtsi +++ /dev/null @@ -1,736 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the R-Mobile A1 (R8A77400) SoC - * - * Copyright (C) 2012 Renesas Solutions Corp. - */ - -#include -#include -#include - -/ { - compatible = "renesas,r8a7740"; - interrupt-parent = <&gic>; - #address-cells = <1>; - #size-cells = <1>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu@0 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - reg = <0x0>; - clock-frequency = <800000000>; - power-domains = <&pd_a3sm>; - next-level-cache = <&L2>; - }; - }; - - gic: interrupt-controller@c2800000 { - compatible = "arm,pl390"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0xc2800000 0x1000>, - <0xc2000000 0x1000>; - }; - - L2: cache-controller@f0100000 { - compatible = "arm,pl310-cache"; - reg = <0xf0100000 0x1000>; - interrupts = ; - power-domains = <&pd_a3sm>; - arm,data-latency = <3 3 3>; - arm,tag-latency = <2 2 2>; - arm,shared-override; - cache-unified; - cache-level = <2>; - }; - - dbsc3: memory-controller@fe400000 { - compatible = "renesas,dbsc3-r8a7740"; - reg = <0xfe400000 0x400>; - power-domains = <&pd_a4s>; - }; - - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts = ; - }; - - ptm { - compatible = "arm,coresight-etm3x"; - power-domains = <&pd_d4>; - }; - - ceu0: ceu@fe910000 { - reg = <0xfe910000 0x3000>; - compatible = "renesas,r8a7740-ceu"; - interrupts = ; - clocks = <&mstp1_clks R8A7740_CLK_CEU20>; - power-domains = <&pd_a4r>; - status = "disabled"; - }; - - ceu1: ceu@fe914000 { - reg = <0xfe914000 0x3000>; - compatible = "renesas,r8a7740-ceu"; - interrupts = ; - clocks = <&mstp1_clks R8A7740_CLK_CEU21>; - power-domains = <&pd_a4r>; - status = "disabled"; - }; - - cmt1: timer@e6138000 { - compatible = "renesas,cmt-48-r8a7740", "renesas,cmt-48"; - reg = <0xe6138000 0x170>; - interrupts = ; - clocks = <&mstp3_clks R8A7740_CLK_CMT1>; - clock-names = "fck"; - power-domains = <&pd_c5>; - status = "disabled"; - }; - - /* irqpin0: IRQ0 - IRQ7 */ - irqpin0: interrupt-controller@e6900000 { - compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0xe6900000 4>, - <0xe6900010 4>, - <0xe6900020 1>, - <0xe6900040 1>, - <0xe6900060 1>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&mstp2_clks R8A7740_CLK_INTCA>; - power-domains = <&pd_a4s>; - }; - - /* irqpin1: IRQ8 - IRQ15 */ - irqpin1: interrupt-controller@e6900004 { - compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0xe6900004 4>, - <0xe6900014 4>, - <0xe6900024 1>, - <0xe6900044 1>, - <0xe6900064 1>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&mstp2_clks R8A7740_CLK_INTCA>; - power-domains = <&pd_a4s>; - }; - - /* irqpin2: IRQ16 - IRQ23 */ - irqpin2: interrupt-controller@e6900008 { - compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0xe6900008 4>, - <0xe6900018 4>, - <0xe6900028 1>, - <0xe6900048 1>, - <0xe6900068 1>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&mstp2_clks R8A7740_CLK_INTCA>; - power-domains = <&pd_a4s>; - }; - - /* irqpin3: IRQ24 - IRQ31 */ - irqpin3: interrupt-controller@e690000c { - compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0xe690000c 4>, - <0xe690001c 4>, - <0xe690002c 1>, - <0xe690004c 1>, - <0xe690006c 1>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&mstp2_clks R8A7740_CLK_INTCA>; - power-domains = <&pd_a4s>; - }; - - ether: ethernet@e9a00000 { - compatible = "renesas,gether-r8a7740"; - reg = <0xe9a00000 0x800>, - <0xe9a01800 0x800>; - interrupts = ; - clocks = <&mstp3_clks R8A7740_CLK_GETHER>; - power-domains = <&pd_a4s>; - phy-mode = "mii"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c0: i2c@fff20000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7740", "renesas,rmobile-iic"; - reg = <0xfff20000 0x425>; - interrupts = , - , - , - ; - clocks = <&mstp1_clks R8A7740_CLK_IIC0>; - power-domains = <&pd_a4r>; - status = "disabled"; - }; - - i2c1: i2c@e6c20000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7740", "renesas,rmobile-iic"; - reg = <0xe6c20000 0x425>; - interrupts = , - , - , - ; - clocks = <&mstp3_clks R8A7740_CLK_IIC1>; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - scifa0: serial@e6c40000 { - compatible = "renesas,scifa-r8a7740", "renesas,scifa"; - reg = <0xe6c40000 0x100>; - interrupts = ; - clocks = <&mstp2_clks R8A7740_CLK_SCIFA0>; - clock-names = "fck"; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - scifa1: serial@e6c50000 { - compatible = "renesas,scifa-r8a7740", "renesas,scifa"; - reg = <0xe6c50000 0x100>; - interrupts = ; - clocks = <&mstp2_clks R8A7740_CLK_SCIFA1>; - clock-names = "fck"; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - scifa2: serial@e6c60000 { - compatible = "renesas,scifa-r8a7740", "renesas,scifa"; - reg = <0xe6c60000 0x100>; - interrupts = ; - clocks = <&mstp2_clks R8A7740_CLK_SCIFA2>; - clock-names = "fck"; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - scifa3: serial@e6c70000 { - compatible = "renesas,scifa-r8a7740", "renesas,scifa"; - reg = <0xe6c70000 0x100>; - interrupts = ; - clocks = <&mstp2_clks R8A7740_CLK_SCIFA3>; - clock-names = "fck"; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - scifa4: serial@e6c80000 { - compatible = "renesas,scifa-r8a7740", "renesas,scifa"; - reg = <0xe6c80000 0x100>; - interrupts = ; - clocks = <&mstp2_clks R8A7740_CLK_SCIFA4>; - clock-names = "fck"; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - scifa5: serial@e6cb0000 { - compatible = "renesas,scifa-r8a7740", "renesas,scifa"; - reg = <0xe6cb0000 0x100>; - interrupts = ; - clocks = <&mstp2_clks R8A7740_CLK_SCIFA5>; - clock-names = "fck"; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - scifa6: serial@e6cc0000 { - compatible = "renesas,scifa-r8a7740", "renesas,scifa"; - reg = <0xe6cc0000 0x100>; - interrupts = ; - clocks = <&mstp2_clks R8A7740_CLK_SCIFA6>; - clock-names = "fck"; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - scifa7: serial@e6cd0000 { - compatible = "renesas,scifa-r8a7740", "renesas,scifa"; - reg = <0xe6cd0000 0x100>; - interrupts = ; - clocks = <&mstp2_clks R8A7740_CLK_SCIFA7>; - clock-names = "fck"; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - scifb: serial@e6c30000 { - compatible = "renesas,scifb-r8a7740", "renesas,scifb"; - reg = <0xe6c30000 0x100>; - interrupts = ; - clocks = <&mstp2_clks R8A7740_CLK_SCIFB>; - clock-names = "fck"; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - pfc: pin-controller@e6050000 { - compatible = "renesas,pfc-r8a7740"; - reg = <0xe6050000 0x8000>, - <0xe605800c 0x20>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pfc 0 0 212>; - interrupts-extended = - <&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>, - <&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>, - <&irqpin1 0 0>, <&irqpin1 1 0>, <&irqpin1 2 0>, <&irqpin1 3 0>, - <&irqpin1 4 0>, <&irqpin1 5 0>, <&irqpin1 6 0>, <&irqpin1 7 0>, - <&irqpin2 0 0>, <&irqpin2 1 0>, <&irqpin2 2 0>, <&irqpin2 3 0>, - <&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>, - <&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>, - <&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>; - power-domains = <&pd_c5>; - }; - - tpu: pwm@e6600000 { - compatible = "renesas,tpu-r8a7740", "renesas,tpu"; - reg = <0xe6600000 0x148>; - clocks = <&mstp3_clks R8A7740_CLK_TPU0>; - power-domains = <&pd_a3sp>; - status = "disabled"; - #pwm-cells = <3>; - }; - - mmcif0: mmc@e6bd0000 { - compatible = "renesas,mmcif-r8a7740", "renesas,sh-mmcif"; - reg = <0xe6bd0000 0x100>; - interrupts = , - ; - clocks = <&mstp3_clks R8A7740_CLK_MMC>; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - sdhi0: sd@e6850000 { - compatible = "renesas,sdhi-r8a7740"; - reg = <0xe6850000 0x100>; - interrupts = , - , - ; - clocks = <&mstp3_clks R8A7740_CLK_SDHI0>; - power-domains = <&pd_a3sp>; - cap-sd-highspeed; - cap-sdio-irq; - status = "disabled"; - }; - - sdhi1: sd@e6860000 { - compatible = "renesas,sdhi-r8a7740"; - reg = <0xe6860000 0x100>; - interrupts = , - , - ; - clocks = <&mstp3_clks R8A7740_CLK_SDHI1>; - power-domains = <&pd_a3sp>; - cap-sd-highspeed; - cap-sdio-irq; - status = "disabled"; - }; - - sdhi2: sd@e6870000 { - compatible = "renesas,sdhi-r8a7740"; - reg = <0xe6870000 0x100>; - interrupts = , - , - ; - clocks = <&mstp4_clks R8A7740_CLK_SDHI2>; - power-domains = <&pd_a3sp>; - cap-sd-highspeed; - cap-sdio-irq; - status = "disabled"; - }; - - sh_fsi2: sound@fe1f0000 { - #sound-dai-cells = <1>; - compatible = "renesas,fsi2-r8a7740", "renesas,sh_fsi2"; - reg = <0xfe1f0000 0x400>; - interrupts = ; - clocks = <&mstp3_clks R8A7740_CLK_FSI>; - power-domains = <&pd_a4mp>; - status = "disabled"; - }; - - tmu0: timer@fff80000 { - compatible = "renesas,tmu-r8a7740", "renesas,tmu"; - reg = <0xfff80000 0x2c>; - interrupts = , - , - ; - clocks = <&mstp1_clks R8A7740_CLK_TMU0>; - clock-names = "fck"; - power-domains = <&pd_a4r>; - - #renesas,channels = <3>; - - status = "disabled"; - }; - - tmu1: timer@fff90000 { - compatible = "renesas,tmu-r8a7740", "renesas,tmu"; - reg = <0xfff90000 0x2c>; - interrupts = , - , - ; - clocks = <&mstp1_clks R8A7740_CLK_TMU1>; - clock-names = "fck"; - power-domains = <&pd_a4r>; - - #renesas,channels = <3>; - - status = "disabled"; - }; - - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - /* External root clock */ - extalr_clk: extalr { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - extal1_clk: extal1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - extal2_clk: extal2 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - dv_clk: dv { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <27000000>; - }; - fmsick_clk: fmsick { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - fmsock_clk: fmsock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - fsiack_clk: fsiack { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - fsibck_clk: fsibck { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - /* Special CPG clocks */ - cpg_clocks: cpg_clocks@e6150000 { - compatible = "renesas,r8a7740-cpg-clocks"; - reg = <0xe6150000 0x10000>; - clocks = <&extal1_clk>, <&extalr_clk>; - #clock-cells = <1>; - clock-output-names = "system", "pllc0", "pllc1", - "pllc2", "r", - "usb24s", - "i", "zg", "b", "m1", "hp", - "hpp", "usbp", "s", "zb", "m3", - "cp"; - }; - - /* Variable factor clocks (DIV6) */ - vclk1_clk: vclk1@e6150008 { - compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; - reg = <0xe6150008 4>; - clocks = <&pllc1_div2_clk>, <0>, <&dv_clk>, - <&cpg_clocks R8A7740_CLK_USB24S>, - <&extal1_div2_clk>, <&extalr_clk>, <0>, - <0>; - #clock-cells = <0>; - }; - vclk2_clk: vclk2@e615000c { - compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; - reg = <0xe615000c 4>; - clocks = <&pllc1_div2_clk>, <0>, <&dv_clk>, - <&cpg_clocks R8A7740_CLK_USB24S>, - <&extal1_div2_clk>, <&extalr_clk>, <0>, - <0>; - #clock-cells = <0>; - }; - fmsi_clk: fmsi@e6150010 { - compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; - reg = <0xe6150010 4>; - clocks = <&pllc1_div2_clk>, <&fmsick_clk>, <0>, <0>; - #clock-cells = <0>; - }; - fmso_clk: fmso@e6150014 { - compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; - reg = <0xe6150014 4>; - clocks = <&pllc1_div2_clk>, <&fmsock_clk>, <0>, <0>; - #clock-cells = <0>; - }; - fsia_clk: fsia@e6150018 { - compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; - reg = <0xe6150018 4>; - clocks = <&pllc1_div2_clk>, <&fsiack_clk>, <0>, <0>; - #clock-cells = <0>; - }; - sub_clk: sub@e6150080 { - compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; - reg = <0xe6150080 4>; - clocks = <&pllc1_div2_clk>, - <&cpg_clocks R8A7740_CLK_USB24S>, <0>, <0>; - #clock-cells = <0>; - }; - spu_clk: spu@e6150084 { - compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; - reg = <0xe6150084 4>; - clocks = <&pllc1_div2_clk>, - <&cpg_clocks R8A7740_CLK_USB24S>, <0>, <0>; - #clock-cells = <0>; - }; - vou_clk: vou@e6150088 { - compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; - reg = <0xe6150088 4>; - clocks = <&pllc1_div2_clk>, <&extal1_clk>, <&dv_clk>, - <0>; - #clock-cells = <0>; - }; - stpro_clk: stpro@e615009c { - compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; - reg = <0xe615009c 4>; - clocks = <&cpg_clocks R8A7740_CLK_PLLC0>; - #clock-cells = <0>; - }; - - /* Fixed factor clocks */ - pllc1_div2_clk: pllc1_div2 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7740_CLK_PLLC1>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - extal1_div2_clk: extal1_div2 { - compatible = "fixed-factor-clock"; - clocks = <&extal1_clk>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - - /* Gate clocks */ - subck_clks: subck_clks@e6150080 { - compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0xe6150080 4>; - clocks = <&sub_clk>, <&sub_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7740_CLK_SUBCK R8A7740_CLK_SUBCK2 - >; - clock-output-names = - "subck", "subck2"; - }; - mstp1_clks: mstp1_clks@e6150134 { - compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0xe6150134 4>, <0xe6150038 4>; - clocks = <&cpg_clocks R8A7740_CLK_S>, - <&cpg_clocks R8A7740_CLK_S>, <&sub_clk>, - <&cpg_clocks R8A7740_CLK_B>, - <&cpg_clocks R8A7740_CLK_HPP>, <&sub_clk>, - <&cpg_clocks R8A7740_CLK_B>; - #clock-cells = <1>; - clock-indices = < - R8A7740_CLK_CEU21 R8A7740_CLK_CEU20 R8A7740_CLK_TMU0 - R8A7740_CLK_LCDC1 R8A7740_CLK_IIC0 R8A7740_CLK_TMU1 - R8A7740_CLK_LCDC0 - >; - clock-output-names = - "ceu21", "ceu20", "tmu0", "lcdc1", "iic0", - "tmu1", "lcdc0"; - }; - mstp2_clks: mstp2_clks@e6150138 { - compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0xe6150138 4>, <0xe6150040 4>; - clocks = <&sub_clk>, <&cpg_clocks R8A7740_CLK_HP>, - <&sub_clk>, <&cpg_clocks R8A7740_CLK_HP>, - <&cpg_clocks R8A7740_CLK_HP>, - <&cpg_clocks R8A7740_CLK_HP>, - <&cpg_clocks R8A7740_CLK_HP>, - <&sub_clk>, <&sub_clk>, <&sub_clk>, - <&sub_clk>, <&sub_clk>, <&sub_clk>, - <&sub_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7740_CLK_SCIFA6 R8A7740_CLK_INTCA - R8A7740_CLK_SCIFA7 - R8A7740_CLK_DMAC1 R8A7740_CLK_DMAC2 - R8A7740_CLK_DMAC3 R8A7740_CLK_USBDMAC - R8A7740_CLK_SCIFA5 R8A7740_CLK_SCIFB - R8A7740_CLK_SCIFA0 R8A7740_CLK_SCIFA1 - R8A7740_CLK_SCIFA2 R8A7740_CLK_SCIFA3 - R8A7740_CLK_SCIFA4 - >; - clock-output-names = - "scifa6", "intca", - "scifa7", "dmac1", "dmac2", "dmac3", - "usbdmac", "scifa5", "scifb", "scifa0", "scifa1", - "scifa2", "scifa3", "scifa4"; - }; - mstp3_clks: mstp3_clks@e615013c { - compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0xe615013c 4>, <0xe6150048 4>; - clocks = <&cpg_clocks R8A7740_CLK_R>, - <&cpg_clocks R8A7740_CLK_HP>, - <&sub_clk>, - <&cpg_clocks R8A7740_CLK_HP>, - <&cpg_clocks R8A7740_CLK_HP>, - <&cpg_clocks R8A7740_CLK_HP>, - <&cpg_clocks R8A7740_CLK_HP>, - <&cpg_clocks R8A7740_CLK_HP>, - <&cpg_clocks R8A7740_CLK_HP>; - #clock-cells = <1>; - clock-indices = < - R8A7740_CLK_CMT1 R8A7740_CLK_FSI R8A7740_CLK_IIC1 - R8A7740_CLK_USBF R8A7740_CLK_SDHI0 R8A7740_CLK_SDHI1 - R8A7740_CLK_MMC R8A7740_CLK_GETHER R8A7740_CLK_TPU0 - >; - clock-output-names = - "cmt1", "fsi", "iic1", "usbf", "sdhi0", "sdhi1", - "mmc", "gether", "tpu0"; - }; - mstp4_clks: mstp4_clks@e6150140 { - compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0xe6150140 4>, <0xe615004c 4>; - clocks = <&cpg_clocks R8A7740_CLK_HP>, - <&cpg_clocks R8A7740_CLK_HP>, - <&cpg_clocks R8A7740_CLK_HP>, - <&cpg_clocks R8A7740_CLK_HP>; - #clock-cells = <1>; - clock-indices = < - R8A7740_CLK_USBH R8A7740_CLK_SDHI2 - R8A7740_CLK_USBFUNC R8A7740_CLK_USBPHY - >; - clock-output-names = - "usbhost", "sdhi2", "usbfunc", "usphy"; - }; - }; - - sysc: system-controller@e6180000 { - compatible = "renesas,sysc-r8a7740", "renesas,sysc-rmobile"; - reg = <0xe6180000 0x8000>, <0xe6188000 0x8000>; - - pm-domains { - pd_c5: c5 { - #address-cells = <1>; - #size-cells = <0>; - #power-domain-cells = <0>; - - pd_a4lc: a4lc@1 { - reg = <1>; - #power-domain-cells = <0>; - }; - - pd_a4mp: a4mp@2 { - reg = <2>; - #power-domain-cells = <0>; - }; - - pd_d4: d4@3 { - reg = <3>; - #power-domain-cells = <0>; - }; - - pd_a4r: a4r@5 { - reg = <5>; - #address-cells = <1>; - #size-cells = <0>; - #power-domain-cells = <0>; - - pd_a3rv: a3rv@6 { - reg = <6>; - #power-domain-cells = <0>; - }; - }; - - pd_a4s: a4s@10 { - reg = <10>; - #address-cells = <1>; - #size-cells = <0>; - #power-domain-cells = <0>; - - pd_a3sp: a3sp@11 { - reg = <11>; - #power-domain-cells = <0>; - }; - - pd_a3sm: a3sm@12 { - reg = <12>; - #power-domain-cells = <0>; - }; - - pd_a3sg: a3sg@13 { - reg = <13>; - #power-domain-cells = <0>; - }; - }; - - pd_a4su: a4su@20 { - reg = <20>; - #power-domain-cells = <0>; - }; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/r8a7743-iwg20d-q7-dbcm-ca.dts b/sys/gnu/dts/arm/r8a7743-iwg20d-q7-dbcm-ca.dts deleted file mode 100644 index 0d006aea99d..00000000000 --- a/sys/gnu/dts/arm/r8a7743-iwg20d-q7-dbcm-ca.dts +++ /dev/null @@ -1,20 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the iWave-RZ/G1M Qseven board + camera daughter board - * - * Copyright (C) 2017 Renesas Electronics Corp. - */ - -/dts-v1/; -#include "r8a7743-iwg20m.dtsi" -#include "iwg20d-q7-common.dtsi" -#include "iwg20d-q7-dbcm-ca.dtsi" - -/ { - model = "iW-RainboW-G20D-Q7 RZ/G1M based plus camera daughter board"; - compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7743"; -}; - -&pciec { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/r8a7743-iwg20d-q7.dts b/sys/gnu/dts/arm/r8a7743-iwg20d-q7.dts deleted file mode 100644 index 498e223a5f9..00000000000 --- a/sys/gnu/dts/arm/r8a7743-iwg20d-q7.dts +++ /dev/null @@ -1,19 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the iWave-RZ/G1M Qseven board - * - * Copyright (C) 2017 Renesas Electronics Corp. - */ - -/dts-v1/; -#include "r8a7743-iwg20m.dtsi" -#include "iwg20d-q7-common.dtsi" - -/ { - model = "iWave Systems RainboW-G20D-Qseven board based on RZ/G1M"; - compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7743"; -}; - -&pciec { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/r8a7743-iwg20m.dtsi b/sys/gnu/dts/arm/r8a7743-iwg20m.dtsi deleted file mode 100644 index b3fee1d61c8..00000000000 --- a/sys/gnu/dts/arm/r8a7743-iwg20m.dtsi +++ /dev/null @@ -1,95 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the iWave-RZG1M-20M Qseven SOM - * - * Copyright (C) 2017 Renesas Electronics Corp. - */ - -#include "r8a7743.dtsi" -#include - -/ { - compatible = "iwave,g20m", "renesas,r8a7743"; - - memory@40000000 { - device_type = "memory"; - reg = <0 0x40000000 0 0x20000000>; - }; - - memory@200000000 { - device_type = "memory"; - reg = <2 0x00000000 0 0x20000000>; - }; - - reg_3p3v: 3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; -}; - -&extal_clk { - clock-frequency = <20000000>; -}; - -&pfc { - mmcif0_pins: mmc { - groups = "mmc_data8_b", "mmc_ctrl"; - function = "mmc"; - }; - - qspi_pins: qspi { - groups = "qspi_ctrl", "qspi_data2"; - function = "qspi"; - }; - - sdhi0_pins: sd0 { - groups = "sdhi0_data4", "sdhi0_ctrl"; - function = "sdhi0"; - power-source = <3300>; - }; -}; - -&mmcif0 { - pinctrl-0 = <&mmcif0_pins>; - pinctrl-names = "default"; - - vmmc-supply = <®_3p3v>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&qspi { - pinctrl-0 = <&qspi_pins>; - pinctrl-names = "default"; - - status = "okay"; - - /* WARNING - This device contains the bootloader. Handle with care. */ - flash: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "sst,sst25vf016b", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <50000000>; - spi-tx-bus-width = <1>; - spi-rx-bus-width = <1>; - m25p,fast-read; - spi-cpol; - spi-cpha; - }; -}; - -&sdhi0 { - pinctrl-0 = <&sdhi0_pins>; - pinctrl-names = "default"; - - vmmc-supply = <®_3p3v>; - vqmmc-supply = <®_3p3v>; - cd-gpios = <&gpio7 11 GPIO_ACTIVE_LOW>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/r8a7743-sk-rzg1m.dts b/sys/gnu/dts/arm/r8a7743-sk-rzg1m.dts deleted file mode 100644 index 807e7d0d6b6..00000000000 --- a/sys/gnu/dts/arm/r8a7743-sk-rzg1m.dts +++ /dev/null @@ -1,77 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the SK-RZG1M board - * - * Copyright (C) 2016-2017 Cogent Embedded, Inc. - */ - -/dts-v1/; -#include "r8a7743.dtsi" - -/ { - model = "SK-RZG1M"; - compatible = "renesas,sk-rzg1m", "renesas,r8a7743"; - - aliases { - serial0 = &scif0; - }; - - chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; - stdout-path = "serial0:115200n8"; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0 0x40000000 0 0x40000000>; - }; - - memory@200000000 { - device_type = "memory"; - reg = <2 0x00000000 0 0x40000000>; - }; -}; - -&extal_clk { - clock-frequency = <20000000>; -}; - -&pfc { - scif0_pins: scif0 { - groups = "scif0_data_d"; - function = "scif0"; - }; - - ether_pins: ether { - groups = "eth_link", "eth_mdio", "eth_rmii"; - function = "eth"; - }; - - phy1_pins: phy1 { - groups = "intc_irq0"; - function = "intc"; - }; -}; - -&scif0 { - pinctrl-0 = <&scif0_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -ðer { - pinctrl-0 = <ðer_pins &phy1_pins>; - pinctrl-names = "default"; - - phy-handle = <&phy1>; - renesas,ether-link-active-low; - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - interrupt-parent = <&irqc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - micrel,led-mode = <1>; - }; -}; diff --git a/sys/gnu/dts/arm/r8a7743.dtsi b/sys/gnu/dts/arm/r8a7743.dtsi deleted file mode 100644 index 1cd19a569bd..00000000000 --- a/sys/gnu/dts/arm/r8a7743.dtsi +++ /dev/null @@ -1,1793 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the r8a7743 SoC - * - * Copyright (C) 2016-2017 Cogent Embedded Inc. - */ - -#include -#include -#include -#include - -/ { - compatible = "renesas,r8a7743"; - #address-cells = <2>; - #size-cells = <2>; - - /* - * The external audio clocks are configured as 0 Hz fixed frequency - * clocks by default. - * Boards that provide audio clocks should override them. - */ - audio_clk_a: audio_clk_a { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - audio_clk_b: audio_clk_b { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - audio_clk_c: audio_clk_c { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - /* External CAN clock */ - can_clk: can { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "renesas,apmu"; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0>; - clock-frequency = <1500000000>; - clocks = <&cpg CPG_CORE R8A7743_CLK_Z>; - clock-latency = <300000>; /* 300 us */ - power-domains = <&sysc R8A7743_PD_CA15_CPU0>; - next-level-cache = <&L2_CA15>; - - /* kHz - uV - OPPs unknown yet */ - operating-points = <1500000 1000000>, - <1312500 1000000>, - <1125000 1000000>, - < 937500 1000000>, - < 750000 1000000>, - < 375000 1000000>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <1>; - clock-frequency = <1500000000>; - clocks = <&cpg CPG_CORE R8A7743_CLK_Z>; - clock-latency = <300000>; /* 300 us */ - power-domains = <&sysc R8A7743_PD_CA15_CPU1>; - next-level-cache = <&L2_CA15>; - - /* kHz - uV - OPPs unknown yet */ - operating-points = <1500000 1000000>, - <1312500 1000000>, - <1125000 1000000>, - < 937500 1000000>, - < 750000 1000000>, - < 375000 1000000>; - }; - - L2_CA15: cache-controller-0 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - power-domains = <&sysc R8A7743_PD_CA15_SCU>; - }; - }; - - /* External root clock */ - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - /* External PCIe clock - can be overridden by the board */ - pcie_bus_clk: pcie_bus { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - pmu { - compatible = "arm,cortex-a15-pmu"; - interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&cpu0>, <&cpu1>; - }; - - /* External SCIF clock */ - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - soc { - compatible = "simple-bus"; - interrupt-parent = <&gic>; - - #address-cells = <2>; - #size-cells = <2>; - ranges; - - rwdt: watchdog@e6020000 { - compatible = "renesas,r8a7743-wdt", - "renesas,rcar-gen2-wdt"; - reg = <0 0xe6020000 0 0x0c>; - clocks = <&cpg CPG_MOD 402>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 402>; - status = "disabled"; - }; - - gpio0: gpio@e6050000 { - compatible = "renesas,gpio-r8a7743", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6050000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 0 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 912>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 912>; - }; - - gpio1: gpio@e6051000 { - compatible = "renesas,gpio-r8a7743", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6051000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 32 26>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 911>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 911>; - }; - - gpio2: gpio@e6052000 { - compatible = "renesas,gpio-r8a7743", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6052000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 64 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 910>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 910>; - }; - - gpio3: gpio@e6053000 { - compatible = "renesas,gpio-r8a7743", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6053000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 96 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 909>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 909>; - }; - - gpio4: gpio@e6054000 { - compatible = "renesas,gpio-r8a7743", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6054000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 128 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 908>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 908>; - }; - - gpio5: gpio@e6055000 { - compatible = "renesas,gpio-r8a7743", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6055000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 160 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 907>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 907>; - }; - - gpio6: gpio@e6055400 { - compatible = "renesas,gpio-r8a7743", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6055400 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 192 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 905>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 905>; - }; - - gpio7: gpio@e6055800 { - compatible = "renesas,gpio-r8a7743", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6055800 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 224 26>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 904>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 904>; - }; - - pfc: pin-controller@e6060000 { - compatible = "renesas,pfc-r8a7743"; - reg = <0 0xe6060000 0 0x250>; - }; - - tpu: pwm@e60f0000 { - compatible = "renesas,tpu-r8a7743", "renesas,tpu"; - reg = <0 0xe60f0000 0 0x148>; - clocks = <&cpg CPG_MOD 304>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 304>; - #pwm-cells = <3>; - status = "disabled"; - }; - - cpg: clock-controller@e6150000 { - compatible = "renesas,r8a7743-cpg-mssr"; - reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk>, <&usb_extal_clk>; - clock-names = "extal", "usb_extal"; - #clock-cells = <2>; - #power-domain-cells = <0>; - #reset-cells = <1>; - }; - - apmu@e6152000 { - compatible = "renesas,r8a7743-apmu", "renesas,apmu"; - reg = <0 0xe6152000 0 0x188>; - cpus = <&cpu0 &cpu1>; - }; - - rst: reset-controller@e6160000 { - compatible = "renesas,r8a7743-rst"; - reg = <0 0xe6160000 0 0x100>; - }; - - sysc: system-controller@e6180000 { - compatible = "renesas,r8a7743-sysc"; - reg = <0 0xe6180000 0 0x200>; - #power-domain-cells = <1>; - }; - - irqc: interrupt-controller@e61c0000 { - compatible = "renesas,irqc-r8a7743", "renesas,irqc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0 0xe61c0000 0 0x200>; - interrupts = , - , - , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 407>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 407>; - }; - - thermal: thermal@e61f0000 { - compatible = "renesas,thermal-r8a7743", - "renesas,rcar-gen2-thermal"; - reg = <0 0xe61f0000 0 0x10>, <0 0xe61f0100 0 0x38>; - interrupts = ; - clocks = <&cpg CPG_MOD 522>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 522>; - #thermal-sensor-cells = <0>; - }; - - ipmmu_sy0: mmu@e6280000 { - compatible = "renesas,ipmmu-r8a7743", - "renesas,ipmmu-vmsa"; - reg = <0 0xe6280000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_sy1: mmu@e6290000 { - compatible = "renesas,ipmmu-r8a7743", - "renesas,ipmmu-vmsa"; - reg = <0 0xe6290000 0 0x1000>; - interrupts = ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_ds: mmu@e6740000 { - compatible = "renesas,ipmmu-r8a7743", - "renesas,ipmmu-vmsa"; - reg = <0 0xe6740000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_mp: mmu@ec680000 { - compatible = "renesas,ipmmu-r8a7743", - "renesas,ipmmu-vmsa"; - reg = <0 0xec680000 0 0x1000>; - interrupts = ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_mx: mmu@fe951000 { - compatible = "renesas,ipmmu-r8a7743", - "renesas,ipmmu-vmsa"; - reg = <0 0xfe951000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_gp: mmu@e62a0000 { - compatible = "renesas,ipmmu-r8a7743", - "renesas,ipmmu-vmsa"; - reg = <0 0xe62a0000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; - - icram0: sram@e63a0000 { - compatible = "mmio-sram"; - reg = <0 0xe63a0000 0 0x12000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0xe63a0000 0x12000>; - }; - - icram1: sram@e63c0000 { - compatible = "mmio-sram"; - reg = <0 0xe63c0000 0 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0xe63c0000 0x1000>; - - smp-sram@0 { - compatible = "renesas,smp-sram"; - reg = <0 0x100>; - }; - }; - - icram2: sram@e6300000 { - compatible = "mmio-sram"; - reg = <0 0xe6300000 0 0x40000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0xe6300000 0x40000>; - }; - - /* The memory map in the User's Manual maps the cores to - * bus numbers - */ - i2c0: i2c@e6508000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7743", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6508000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 931>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 931>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c1: i2c@e6518000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7743", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6518000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 930>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 930>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c2: i2c@e6530000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7743", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6530000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 929>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 929>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c3: i2c@e6540000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7743", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6540000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 928>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 928>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c4: i2c@e6520000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7743", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6520000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 927>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 927>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c5: i2c@e6528000 { - /* doesn't need pinmux */ - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7743", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6528000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 925>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 925>; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - iic0: i2c@e6500000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7743", - "renesas,rcar-gen2-iic", - "renesas,rmobile-iic"; - reg = <0 0xe6500000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 318>; - dmas = <&dmac0 0x61>, <&dmac0 0x62>, - <&dmac1 0x61>, <&dmac1 0x62>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 318>; - status = "disabled"; - }; - - iic1: i2c@e6510000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7743", - "renesas,rcar-gen2-iic", - "renesas,rmobile-iic"; - reg = <0 0xe6510000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 323>; - dmas = <&dmac0 0x65>, <&dmac0 0x66>, - <&dmac1 0x65>, <&dmac1 0x66>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 323>; - status = "disabled"; - }; - - iic3: i2c@e60b0000 { - /* doesn't need pinmux */ - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7743"; - reg = <0 0xe60b0000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 926>; - dmas = <&dmac0 0x77>, <&dmac0 0x78>, - <&dmac1 0x77>, <&dmac1 0x78>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 926>; - status = "disabled"; - }; - - hsusb: usb@e6590000 { - compatible = "renesas,usbhs-r8a7743", - "renesas,rcar-gen2-usbhs"; - reg = <0 0xe6590000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 704>; - dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, - <&usb_dmac1 0>, <&usb_dmac1 1>; - dma-names = "ch0", "ch1", "ch2", "ch3"; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 704>; - renesas,buswait = <4>; - phys = <&usb0 1>; - phy-names = "usb"; - status = "disabled"; - }; - - usbphy: usb-phy@e6590100 { - compatible = "renesas,usb-phy-r8a7743", - "renesas,rcar-gen2-usb-phy"; - reg = <0 0xe6590100 0 0x100>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cpg CPG_MOD 704>; - clock-names = "usbhs"; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 704>; - status = "disabled"; - - usb0: usb-channel@0 { - reg = <0>; - #phy-cells = <1>; - }; - usb2: usb-channel@2 { - reg = <2>; - #phy-cells = <1>; - }; - }; - - usb_dmac0: dma-controller@e65a0000 { - compatible = "renesas,r8a7743-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65a0000 0 0x100>; - interrupts = , - ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 330>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 330>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - usb_dmac1: dma-controller@e65b0000 { - compatible = "renesas,r8a7743-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65b0000 0 0x100>; - interrupts = , - ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 331>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 331>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - dmac0: dma-controller@e6700000 { - compatible = "renesas,dmac-r8a7743", - "renesas,rcar-dmac"; - reg = <0 0xe6700000 0 0x20000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14"; - clocks = <&cpg CPG_MOD 219>; - clock-names = "fck"; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 219>; - #dma-cells = <1>; - dma-channels = <15>; - }; - - dmac1: dma-controller@e6720000 { - compatible = "renesas,dmac-r8a7743", - "renesas,rcar-dmac"; - reg = <0 0xe6720000 0 0x20000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14"; - clocks = <&cpg CPG_MOD 218>; - clock-names = "fck"; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 218>; - #dma-cells = <1>; - dma-channels = <15>; - }; - - avb: ethernet@e6800000 { - compatible = "renesas,etheravb-r8a7743", - "renesas,etheravb-rcar-gen2"; - reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; - interrupts = ; - clocks = <&cpg CPG_MOD 812>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 812>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - qspi: spi@e6b10000 { - compatible = "renesas,qspi-r8a7743", "renesas,qspi"; - reg = <0 0xe6b10000 0 0x2c>; - interrupts = ; - clocks = <&cpg CPG_MOD 917>; - dmas = <&dmac0 0x17>, <&dmac0 0x18>, - <&dmac1 0x17>, <&dmac1 0x18>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - resets = <&cpg 917>; - status = "disabled"; - }; - - scifa0: serial@e6c40000 { - compatible = "renesas,scifa-r8a7743", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c40000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 204>; - clock-names = "fck"; - dmas = <&dmac0 0x21>, <&dmac0 0x22>, - <&dmac1 0x21>, <&dmac1 0x22>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 204>; - status = "disabled"; - }; - - scifa1: serial@e6c50000 { - compatible = "renesas,scifa-r8a7743", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c50000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 203>; - clock-names = "fck"; - dmas = <&dmac0 0x25>, <&dmac0 0x26>, - <&dmac1 0x25>, <&dmac1 0x26>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 203>; - status = "disabled"; - }; - - scifa2: serial@e6c60000 { - compatible = "renesas,scifa-r8a7743", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c60000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 202>; - clock-names = "fck"; - dmas = <&dmac0 0x27>, <&dmac0 0x28>, - <&dmac1 0x27>, <&dmac1 0x28>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 202>; - status = "disabled"; - }; - - scifa3: serial@e6c70000 { - compatible = "renesas,scifa-r8a7743", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c70000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 1106>; - clock-names = "fck"; - dmas = <&dmac0 0x1b>, <&dmac0 0x1c>, - <&dmac1 0x1b>, <&dmac1 0x1c>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 1106>; - status = "disabled"; - }; - - scifa4: serial@e6c78000 { - compatible = "renesas,scifa-r8a7743", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c78000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 1107>; - clock-names = "fck"; - dmas = <&dmac0 0x1f>, <&dmac0 0x20>, - <&dmac1 0x1f>, <&dmac1 0x20>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 1107>; - status = "disabled"; - }; - - scifa5: serial@e6c80000 { - compatible = "renesas,scifa-r8a7743", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c80000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 1108>; - clock-names = "fck"; - dmas = <&dmac0 0x23>, <&dmac0 0x24>, - <&dmac1 0x23>, <&dmac1 0x24>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 1108>; - status = "disabled"; - }; - - scifb0: serial@e6c20000 { - compatible = "renesas,scifb-r8a7743", - "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6c20000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 206>; - clock-names = "fck"; - dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, - <&dmac1 0x3d>, <&dmac1 0x3e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 206>; - status = "disabled"; - }; - - scifb1: serial@e6c30000 { - compatible = "renesas,scifb-r8a7743", - "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6c30000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 207>; - clock-names = "fck"; - dmas = <&dmac0 0x19>, <&dmac0 0x1a>, - <&dmac1 0x19>, <&dmac1 0x1a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 207>; - status = "disabled"; - }; - - scifb2: serial@e6ce0000 { - compatible = "renesas,scifb-r8a7743", - "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6ce0000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 216>; - clock-names = "fck"; - dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, - <&dmac1 0x1d>, <&dmac1 0x1e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 216>; - status = "disabled"; - }; - - scif0: serial@e6e60000 { - compatible = "renesas,scif-r8a7743", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6e60000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 721>, - <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x29>, <&dmac0 0x2a>, - <&dmac1 0x29>, <&dmac1 0x2a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 721>; - status = "disabled"; - }; - - scif1: serial@e6e68000 { - compatible = "renesas,scif-r8a7743", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6e68000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 720>, - <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, - <&dmac1 0x2d>, <&dmac1 0x2e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 720>; - status = "disabled"; - }; - - scif2: serial@e6e58000 { - compatible = "renesas,scif-r8a7743", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6e58000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 719>, - <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, - <&dmac1 0x2b>, <&dmac1 0x2c>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 719>; - status = "disabled"; - }; - - scif3: serial@e6ea8000 { - compatible = "renesas,scif-r8a7743", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6ea8000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 718>, - <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2f>, <&dmac0 0x30>, - <&dmac1 0x2f>, <&dmac1 0x30>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 718>; - status = "disabled"; - }; - - scif4: serial@e6ee0000 { - compatible = "renesas,scif-r8a7743", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6ee0000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 715>, - <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0xfb>, <&dmac0 0xfc>, - <&dmac1 0xfb>, <&dmac1 0xfc>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 715>; - status = "disabled"; - }; - - scif5: serial@e6ee8000 { - compatible = "renesas,scif-r8a7743", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6ee8000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 714>, - <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0xfd>, <&dmac0 0xfe>, - <&dmac1 0xfd>, <&dmac1 0xfe>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 714>; - status = "disabled"; - }; - - hscif0: serial@e62c0000 { - compatible = "renesas,hscif-r8a7743", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62c0000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 717>, - <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x39>, <&dmac0 0x3a>, - <&dmac1 0x39>, <&dmac1 0x3a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 717>; - status = "disabled"; - }; - - hscif1: serial@e62c8000 { - compatible = "renesas,hscif-r8a7743", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62c8000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 716>, - <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, - <&dmac1 0x4d>, <&dmac1 0x4e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 716>; - status = "disabled"; - }; - - hscif2: serial@e62d0000 { - compatible = "renesas,hscif-r8a7743", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62d0000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 713>, - <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x3b>, <&dmac0 0x3c>, - <&dmac1 0x3b>, <&dmac1 0x3c>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 713>; - status = "disabled"; - }; - - msiof0: spi@e6e20000 { - compatible = "renesas,msiof-r8a7743", - "renesas,rcar-gen2-msiof"; - reg = <0 0xe6e20000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 000>; - dmas = <&dmac0 0x51>, <&dmac0 0x52>, - <&dmac1 0x51>, <&dmac1 0x52>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - #address-cells = <1>; - #size-cells = <0>; - resets = <&cpg 000>; - status = "disabled"; - }; - - msiof1: spi@e6e10000 { - compatible = "renesas,msiof-r8a7743", - "renesas,rcar-gen2-msiof"; - reg = <0 0xe6e10000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 208>; - dmas = <&dmac0 0x55>, <&dmac0 0x56>, - <&dmac1 0x55>, <&dmac1 0x56>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - #address-cells = <1>; - #size-cells = <0>; - resets = <&cpg 208>; - status = "disabled"; - }; - - msiof2: spi@e6e00000 { - compatible = "renesas,msiof-r8a7743", - "renesas,rcar-gen2-msiof"; - reg = <0 0xe6e00000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 205>; - dmas = <&dmac0 0x41>, <&dmac0 0x42>, - <&dmac1 0x41>, <&dmac1 0x42>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - #address-cells = <1>; - #size-cells = <0>; - resets = <&cpg 205>; - status = "disabled"; - }; - - pwm0: pwm@e6e30000 { - compatible = "renesas,pwm-r8a7743", "renesas,pwm-rcar"; - reg = <0 0xe6e30000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm1: pwm@e6e31000 { - compatible = "renesas,pwm-r8a7743", "renesas,pwm-rcar"; - reg = <0 0xe6e31000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm2: pwm@e6e32000 { - compatible = "renesas,pwm-r8a7743", "renesas,pwm-rcar"; - reg = <0 0xe6e32000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm3: pwm@e6e33000 { - compatible = "renesas,pwm-r8a7743", "renesas,pwm-rcar"; - reg = <0 0xe6e33000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm4: pwm@e6e34000 { - compatible = "renesas,pwm-r8a7743", "renesas,pwm-rcar"; - reg = <0 0xe6e34000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm5: pwm@e6e35000 { - compatible = "renesas,pwm-r8a7743", "renesas,pwm-rcar"; - reg = <0 0xe6e35000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm6: pwm@e6e36000 { - compatible = "renesas,pwm-r8a7743", "renesas,pwm-rcar"; - reg = <0 0xe6e36000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - can0: can@e6e80000 { - compatible = "renesas,can-r8a7743", - "renesas,rcar-gen2-can"; - reg = <0 0xe6e80000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 916>, - <&cpg CPG_CORE R8A7743_CLK_RCAN>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 916>; - status = "disabled"; - }; - - can1: can@e6e88000 { - compatible = "renesas,can-r8a7743", - "renesas,rcar-gen2-can"; - reg = <0 0xe6e88000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 915>, - <&cpg CPG_CORE R8A7743_CLK_RCAN>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 915>; - status = "disabled"; - }; - - vin0: video@e6ef0000 { - compatible = "renesas,vin-r8a7743", - "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef0000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 811>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 811>; - status = "disabled"; - }; - - vin1: video@e6ef1000 { - compatible = "renesas,vin-r8a7743", - "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef1000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 810>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 810>; - status = "disabled"; - }; - - vin2: video@e6ef2000 { - compatible = "renesas,vin-r8a7743", - "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef2000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 809>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 809>; - status = "disabled"; - }; - - rcar_sound: sound@ec500000 { - /* - * #sound-dai-cells is required - * - * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; - * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; - */ - compatible = "renesas,rcar_sound-r8a7743", - "renesas,rcar_sound-gen2"; - reg = <0 0xec500000 0 0x1000>, /* SCU */ - <0 0xec5a0000 0 0x100>, /* ADG */ - <0 0xec540000 0 0x1000>, /* SSIU */ - <0 0xec541000 0 0x280>, /* SSI */ - <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ - reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; - - clocks = <&cpg CPG_MOD 1005>, - <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, - <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, - <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, - <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, - <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, - <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, - <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, - <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, - <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, - <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, - <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, - <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, - <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, - <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, - <&cpg CPG_CORE R8A7743_CLK_M2>; - clock-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", - "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0", - "src.9", "src.8", "src.7", "src.6", "src.5", - "src.4", "src.3", "src.2", "src.1", "src.0", - "ctu.0", "ctu.1", - "mix.0", "mix.1", - "dvc.0", "dvc.1", - "clk_a", "clk_b", "clk_c", "clk_i"; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 1005>, - <&cpg 1006>, <&cpg 1007>, <&cpg 1008>, <&cpg 1009>, - <&cpg 1010>, <&cpg 1011>, <&cpg 1012>, <&cpg 1013>, - <&cpg 1014>, <&cpg 1015>; - reset-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", - "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0"; - status = "disabled"; - - rcar_sound,dvc { - dvc0: dvc-0 { - dmas = <&audma1 0xbc>; - dma-names = "tx"; - }; - dvc1: dvc-1 { - dmas = <&audma1 0xbe>; - dma-names = "tx"; - }; - }; - - rcar_sound,mix { - mix0: mix-0 { }; - mix1: mix-1 { }; - }; - - rcar_sound,ctu { - ctu00: ctu-0 { }; - ctu01: ctu-1 { }; - ctu02: ctu-2 { }; - ctu03: ctu-3 { }; - ctu10: ctu-4 { }; - ctu11: ctu-5 { }; - ctu12: ctu-6 { }; - ctu13: ctu-7 { }; - }; - - rcar_sound,src { - src0: src-0 { - interrupts = ; - dmas = <&audma0 0x85>, <&audma1 0x9a>; - dma-names = "rx", "tx"; - }; - src1: src-1 { - interrupts = ; - dmas = <&audma0 0x87>, <&audma1 0x9c>; - dma-names = "rx", "tx"; - }; - src2: src-2 { - interrupts = ; - dmas = <&audma0 0x89>, <&audma1 0x9e>; - dma-names = "rx", "tx"; - }; - src3: src-3 { - interrupts = ; - dmas = <&audma0 0x8b>, <&audma1 0xa0>; - dma-names = "rx", "tx"; - }; - src4: src-4 { - interrupts = ; - dmas = <&audma0 0x8d>, <&audma1 0xb0>; - dma-names = "rx", "tx"; - }; - src5: src-5 { - interrupts = ; - dmas = <&audma0 0x8f>, <&audma1 0xb2>; - dma-names = "rx", "tx"; - }; - src6: src-6 { - interrupts = ; - dmas = <&audma0 0x91>, <&audma1 0xb4>; - dma-names = "rx", "tx"; - }; - src7: src-7 { - interrupts = ; - dmas = <&audma0 0x93>, <&audma1 0xb6>; - dma-names = "rx", "tx"; - }; - src8: src-8 { - interrupts = ; - dmas = <&audma0 0x95>, <&audma1 0xb8>; - dma-names = "rx", "tx"; - }; - src9: src-9 { - interrupts = ; - dmas = <&audma0 0x97>, <&audma1 0xba>; - dma-names = "rx", "tx"; - }; - }; - - rcar_sound,ssi { - ssi0: ssi-0 { - interrupts = ; - dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi1: ssi-1 { - interrupts = ; - dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi2: ssi-2 { - interrupts = ; - dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi3: ssi-3 { - interrupts = ; - dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi4: ssi-4 { - interrupts = ; - dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi5: ssi-5 { - interrupts = ; - dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi6: ssi-6 { - interrupts = ; - dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi7: ssi-7 { - interrupts = ; - dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi8: ssi-8 { - interrupts = ; - dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi9: ssi-9 { - interrupts = ; - dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - }; - }; - - audma0: dma-controller@ec700000 { - compatible = "renesas,dmac-r8a7743", - "renesas,rcar-dmac"; - reg = <0 0xec700000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12"; - clocks = <&cpg CPG_MOD 502>; - clock-names = "fck"; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 502>; - #dma-cells = <1>; - dma-channels = <13>; - }; - - audma1: dma-controller@ec720000 { - compatible = "renesas,dmac-r8a7743", - "renesas,rcar-dmac"; - reg = <0 0xec720000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12"; - clocks = <&cpg CPG_MOD 501>; - clock-names = "fck"; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 501>; - #dma-cells = <1>; - dma-channels = <13>; - }; - - /* - * pci1 and xhci share the same phy, therefore only one of them - * can be active at any one time. If both of them are enabled, - * a race condition will determine who'll control the phy. - * A firmware file is needed by the xhci driver in order for - * USB 3.0 to work properly. - */ - xhci: usb@ee000000 { - compatible = "renesas,xhci-r8a7743", - "renesas,rcar-gen2-xhci"; - reg = <0 0xee000000 0 0xc00>; - interrupts = ; - clocks = <&cpg CPG_MOD 328>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 328>; - phys = <&usb2 1>; - phy-names = "usb"; - status = "disabled"; - }; - - pci0: pci@ee090000 { - compatible = "renesas,pci-r8a7743", - "renesas,pci-rcar-gen2"; - device_type = "pci"; - reg = <0 0xee090000 0 0xc00>, - <0 0xee080000 0 0x1100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 703>; - status = "disabled"; - - bus-range = <0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>; - interrupt-map-mask = <0xf800 0 0 0x7>; - interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, - <0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, - <0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; - - usb@1,0 { - reg = <0x800 0 0 0 0>; - phys = <&usb0 0>; - phy-names = "usb"; - }; - - usb@2,0 { - reg = <0x1000 0 0 0 0>; - phys = <&usb0 0>; - phy-names = "usb"; - }; - }; - - pci1: pci@ee0d0000 { - compatible = "renesas,pci-r8a7743", - "renesas,pci-rcar-gen2"; - device_type = "pci"; - reg = <0 0xee0d0000 0 0xc00>, - <0 0xee0c0000 0 0x1100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 703>; - status = "disabled"; - - bus-range = <1 1>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>; - interrupt-map-mask = <0xf800 0 0 0x7>; - interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, - <0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, - <0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; - - usb@1,0 { - reg = <0x10800 0 0 0 0>; - phys = <&usb2 0>; - phy-names = "usb"; - }; - - usb@2,0 { - reg = <0x11000 0 0 0 0>; - phys = <&usb2 0>; - phy-names = "usb"; - }; - }; - - sdhi0: sd@ee100000 { - compatible = "renesas,sdhi-r8a7743", - "renesas,rcar-gen2-sdhi"; - reg = <0 0xee100000 0 0x328>; - interrupts = ; - clocks = <&cpg CPG_MOD 314>; - dmas = <&dmac0 0xcd>, <&dmac0 0xce>, - <&dmac1 0xcd>, <&dmac1 0xce>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <195000000>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 314>; - status = "disabled"; - }; - - sdhi1: sd@ee140000 { - compatible = "renesas,sdhi-r8a7743", - "renesas,rcar-gen2-sdhi"; - reg = <0 0xee140000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 312>; - dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, - <&dmac1 0xc1>, <&dmac1 0xc2>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <97500000>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 312>; - status = "disabled"; - }; - - sdhi2: sd@ee160000 { - compatible = "renesas,sdhi-r8a7743", - "renesas,rcar-gen2-sdhi"; - reg = <0 0xee160000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 311>; - dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, - <&dmac1 0xd3>, <&dmac1 0xd4>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <97500000>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 311>; - status = "disabled"; - }; - - mmcif0: mmc@ee200000 { - compatible = "renesas,mmcif-r8a7743", - "renesas,sh-mmcif"; - reg = <0 0xee200000 0 0x80>; - interrupts = ; - clocks = <&cpg CPG_MOD 315>; - dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, - <&dmac1 0xd1>, <&dmac1 0xd2>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 315>; - reg-io-width = <4>; - max-frequency = <97500000>; - status = "disabled"; - }; - - ether: ethernet@ee700000 { - compatible = "renesas,ether-r8a7743", - "renesas,rcar-gen2-ether"; - reg = <0 0xee700000 0 0x400>; - interrupts = ; - clocks = <&cpg CPG_MOD 813>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 813>; - phy-mode = "rmii"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - gic: interrupt-controller@f1001000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>, - <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 408>; - clock-names = "clk"; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 408>; - }; - - pciec: pcie@fe000000 { - compatible = "renesas,pcie-r8a7743", - "renesas,pcie-rcar-gen2"; - reg = <0 0xfe000000 0 0x80000>; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x00 0xff>; - device_type = "pci"; - ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, - <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, - <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, - <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>, - <0x43000000 2 0x00000000 2 0x00000000 1 0x00000000>; - interrupts = , - , - ; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; - clock-names = "pcie", "pcie_bus"; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 319>; - status = "disabled"; - }; - - vsp@fe928000 { - compatible = "renesas,vsp1"; - reg = <0 0xfe928000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 131>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 131>; - }; - - vsp@fe930000 { - compatible = "renesas,vsp1"; - reg = <0 0xfe930000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 128>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 128>; - }; - - vsp@fe938000 { - compatible = "renesas,vsp1"; - reg = <0 0xfe938000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 127>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 127>; - }; - - du: display@feb00000 { - compatible = "renesas,du-r8a7743"; - reg = <0 0xfeb00000 0 0x40000>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>; - clock-names = "du.0", "du.1"; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - du_out_rgb: endpoint { - }; - }; - port@1 { - reg = <1>; - du_out_lvds0: endpoint { - remote-endpoint = <&lvds0_in>; - }; - }; - }; - }; - - lvds0: lvds@feb90000 { - compatible = "renesas,r8a7743-lvds"; - reg = <0 0xfeb90000 0 0x1c>; - clocks = <&cpg CPG_MOD 726>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 726>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - lvds0_in: endpoint { - remote-endpoint = <&du_out_lvds0>; - }; - }; - port@1 { - reg = <1>; - lvds0_out: endpoint { - }; - }; - }; - }; - - prr: chipid@ff000044 { - compatible = "renesas,prr"; - reg = <0 0xff000044 0 4>; - }; - - cmt0: timer@ffca0000 { - compatible = "renesas,r8a7743-cmt0", - "renesas,rcar-gen2-cmt0"; - reg = <0 0xffca0000 0 0x1004>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 124>; - clock-names = "fck"; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 124>; - status = "disabled"; - }; - - cmt1: timer@e6130000 { - compatible = "renesas,r8a7743-cmt1", - "renesas,rcar-gen2-cmt1"; - reg = <0 0xe6130000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 329>; - clock-names = "fck"; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 329>; - status = "disabled"; - }; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - - thermal-sensors = <&thermal>; - - trips { - cpu-crit { - temperature = <95000>; - hysteresis = <0>; - type = "critical"; - }; - }; - - cooling-maps { - }; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; - }; - - /* External USB clock - can be overridden by the board */ - usb_extal_clk: usb_extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <48000000>; - }; -}; diff --git a/sys/gnu/dts/arm/r8a7744-iwg20d-q7-dbcm-ca.dts b/sys/gnu/dts/arm/r8a7744-iwg20d-q7-dbcm-ca.dts deleted file mode 100644 index 3e58c2e92e0..00000000000 --- a/sys/gnu/dts/arm/r8a7744-iwg20d-q7-dbcm-ca.dts +++ /dev/null @@ -1,17 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the iWave Systems RZ/G1N Qseven board development - * platform with camera daughter board - * - * Copyright (C) 2018 Renesas Electronics Corp. - */ - -/dts-v1/; -#include "r8a7744-iwg20m.dtsi" -#include "iwg20d-q7-common.dtsi" -#include "iwg20d-q7-dbcm-ca.dtsi" - -/ { - model = "iWave Systems RZ/G1N Qseven development platform with camera add-on"; - compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7744"; -}; diff --git a/sys/gnu/dts/arm/r8a7744-iwg20d-q7.dts b/sys/gnu/dts/arm/r8a7744-iwg20d-q7.dts deleted file mode 100644 index 1fdac528f27..00000000000 --- a/sys/gnu/dts/arm/r8a7744-iwg20d-q7.dts +++ /dev/null @@ -1,15 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the iWave-RZ/G1N Qseven board - * - * Copyright (C) 2018 Renesas Electronics Corp. - */ - -/dts-v1/; -#include "r8a7744-iwg20m.dtsi" -#include "iwg20d-q7-common.dtsi" - -/ { - model = "iWave Systems RainboW-G20D-Qseven board based on RZ/G1N"; - compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7744"; -}; diff --git a/sys/gnu/dts/arm/r8a7744-iwg20m.dtsi b/sys/gnu/dts/arm/r8a7744-iwg20m.dtsi deleted file mode 100644 index 82ee3c1140e..00000000000 --- a/sys/gnu/dts/arm/r8a7744-iwg20m.dtsi +++ /dev/null @@ -1,90 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the iWave RZ/G1N Qseven SOM - * - * Copyright (C) 2018 Renesas Electronics Corp. - */ - -#include "r8a7744.dtsi" -#include - -/ { - compatible = "iwave,g20m", "renesas,r8a7744"; - - memory@40000000 { - device_type = "memory"; - reg = <0 0x40000000 0 0x40000000>; - }; - - reg_3p3v: 3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; -}; - -&extal_clk { - clock-frequency = <20000000>; -}; - -&pfc { - mmcif0_pins: mmc { - groups = "mmc_data8_b", "mmc_ctrl"; - function = "mmc"; - }; - - qspi_pins: qspi { - groups = "qspi_ctrl", "qspi_data2"; - function = "qspi"; - }; - - sdhi0_pins: sd0 { - groups = "sdhi0_data4", "sdhi0_ctrl"; - function = "sdhi0"; - power-source = <3300>; - }; -}; - -&mmcif0 { - pinctrl-0 = <&mmcif0_pins>; - pinctrl-names = "default"; - - vmmc-supply = <®_3p3v>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&qspi { - pinctrl-0 = <&qspi_pins>; - pinctrl-names = "default"; - - status = "okay"; - - /* WARNING - This device contains the bootloader. Handle with care. */ - flash: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <50000000>; - spi-tx-bus-width = <2>; - spi-rx-bus-width = <2>; - m25p,fast-read; - spi-cpol; - spi-cpha; - }; -}; - -&sdhi0 { - pinctrl-0 = <&sdhi0_pins>; - pinctrl-names = "default"; - - vmmc-supply = <®_3p3v>; - vqmmc-supply = <®_3p3v>; - cd-gpios = <&gpio7 11 GPIO_ACTIVE_LOW>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/r8a7744.dtsi b/sys/gnu/dts/arm/r8a7744.dtsi deleted file mode 100644 index 1c82dd0abd7..00000000000 --- a/sys/gnu/dts/arm/r8a7744.dtsi +++ /dev/null @@ -1,1779 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the r8a7744 SoC - * - * Copyright (C) 2018 Renesas Electronics Corp. - */ - -#include -#include -#include -#include - -/ { - compatible = "renesas,r8a7744"; - #address-cells = <2>; - #size-cells = <2>; - - /* - * The external audio clocks are configured as 0 Hz fixed frequency - * clocks by default. - * Boards that provide audio clocks should override them. - */ - audio_clk_a: audio_clk_a { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - audio_clk_b: audio_clk_b { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - audio_clk_c: audio_clk_c { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - /* External CAN clock */ - can_clk: can { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "renesas,apmu"; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0>; - clock-frequency = <1500000000>; - clocks = <&cpg CPG_CORE R8A7744_CLK_Z>; - clock-latency = <300000>; /* 300 us */ - power-domains = <&sysc R8A7744_PD_CA15_CPU0>; - next-level-cache = <&L2_CA15>; - - /* kHz - uV - OPPs unknown yet */ - operating-points = <1500000 1000000>, - <1312500 1000000>, - <1125000 1000000>, - < 937500 1000000>, - < 750000 1000000>, - < 375000 1000000>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <1>; - clock-frequency = <1500000000>; - clocks = <&cpg CPG_CORE R8A7744_CLK_Z>; - clock-latency = <300000>; /* 300 us */ - power-domains = <&sysc R8A7744_PD_CA15_CPU1>; - next-level-cache = <&L2_CA15>; - - /* kHz - uV - OPPs unknown yet */ - operating-points = <1500000 1000000>, - <1312500 1000000>, - <1125000 1000000>, - < 937500 1000000>, - < 750000 1000000>, - < 375000 1000000>; - }; - - L2_CA15: cache-controller-0 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - power-domains = <&sysc R8A7744_PD_CA15_SCU>; - }; - }; - - /* External root clock */ - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - /* External PCIe clock - can be overridden by the board */ - pcie_bus_clk: pcie_bus { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - pmu { - compatible = "arm,cortex-a15-pmu"; - interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&cpu0>, <&cpu1>; - }; - - /* External SCIF clock */ - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - soc { - compatible = "simple-bus"; - interrupt-parent = <&gic>; - - #address-cells = <2>; - #size-cells = <2>; - ranges; - - rwdt: watchdog@e6020000 { - compatible = "renesas,r8a7744-wdt", - "renesas,rcar-gen2-wdt"; - reg = <0 0xe6020000 0 0x0c>; - clocks = <&cpg CPG_MOD 402>; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 402>; - status = "disabled"; - }; - - gpio0: gpio@e6050000 { - compatible = "renesas,gpio-r8a7744", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6050000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 0 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 912>; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 912>; - }; - - gpio1: gpio@e6051000 { - compatible = "renesas,gpio-r8a7744", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6051000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 32 26>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 911>; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 911>; - }; - - gpio2: gpio@e6052000 { - compatible = "renesas,gpio-r8a7744", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6052000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 64 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 910>; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 910>; - }; - - gpio3: gpio@e6053000 { - compatible = "renesas,gpio-r8a7744", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6053000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 96 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 909>; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 909>; - }; - - gpio4: gpio@e6054000 { - compatible = "renesas,gpio-r8a7744", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6054000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 128 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 908>; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 908>; - }; - - gpio5: gpio@e6055000 { - compatible = "renesas,gpio-r8a7744", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6055000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 160 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 907>; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 907>; - }; - - gpio6: gpio@e6055400 { - compatible = "renesas,gpio-r8a7744", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6055400 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 192 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 905>; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 905>; - }; - - gpio7: gpio@e6055800 { - compatible = "renesas,gpio-r8a7744", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6055800 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 224 26>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 904>; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 904>; - }; - - pfc: pin-controller@e6060000 { - compatible = "renesas,pfc-r8a7744"; - reg = <0 0xe6060000 0 0x250>; - }; - - tpu: pwm@e60f0000 { - compatible = "renesas,tpu-r8a7744", "renesas,tpu"; - reg = <0 0xe60f0000 0 0x148>; - clocks = <&cpg CPG_MOD 304>; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 304>; - #pwm-cells = <3>; - status = "disabled"; - }; - - cpg: clock-controller@e6150000 { - compatible = "renesas,r8a7744-cpg-mssr"; - reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk>, <&usb_extal_clk>; - clock-names = "extal", "usb_extal"; - #clock-cells = <2>; - #power-domain-cells = <0>; - #reset-cells = <1>; - }; - - apmu@e6152000 { - compatible = "renesas,r8a7744-apmu", "renesas,apmu"; - reg = <0 0xe6152000 0 0x188>; - cpus = <&cpu0 &cpu1>; - }; - - rst: reset-controller@e6160000 { - compatible = "renesas,r8a7744-rst"; - reg = <0 0xe6160000 0 0x100>; - }; - - sysc: system-controller@e6180000 { - compatible = "renesas,r8a7744-sysc"; - reg = <0 0xe6180000 0 0x200>; - #power-domain-cells = <1>; - }; - - irqc: interrupt-controller@e61c0000 { - compatible = "renesas,irqc-r8a7744", "renesas,irqc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0 0xe61c0000 0 0x200>; - interrupts = , - , - , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 407>; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 407>; - }; - - thermal: thermal@e61f0000 { - compatible = "renesas,thermal-r8a7744", - "renesas,rcar-gen2-thermal"; - reg = <0 0xe61f0000 0 0x10>, <0 0xe61f0100 0 0x38>; - interrupts = ; - clocks = <&cpg CPG_MOD 522>; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 522>; - #thermal-sensor-cells = <0>; - }; - - ipmmu_sy0: mmu@e6280000 { - compatible = "renesas,ipmmu-r8a7744", - "renesas,ipmmu-vmsa"; - reg = <0 0xe6280000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_sy1: mmu@e6290000 { - compatible = "renesas,ipmmu-r8a7744", - "renesas,ipmmu-vmsa"; - reg = <0 0xe6290000 0 0x1000>; - interrupts = ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_ds: mmu@e6740000 { - compatible = "renesas,ipmmu-r8a7744", - "renesas,ipmmu-vmsa"; - reg = <0 0xe6740000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_mp: mmu@ec680000 { - compatible = "renesas,ipmmu-r8a7744", - "renesas,ipmmu-vmsa"; - reg = <0 0xec680000 0 0x1000>; - interrupts = ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_mx: mmu@fe951000 { - compatible = "renesas,ipmmu-r8a7744", - "renesas,ipmmu-vmsa"; - reg = <0 0xfe951000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_gp: mmu@e62a0000 { - compatible = "renesas,ipmmu-r8a7744", - "renesas,ipmmu-vmsa"; - reg = <0 0xe62a0000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; - - icram0: sram@e63a0000 { - compatible = "mmio-sram"; - reg = <0 0xe63a0000 0 0x12000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0xe63a0000 0x12000>; - }; - - icram1: sram@e63c0000 { - compatible = "mmio-sram"; - reg = <0 0xe63c0000 0 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0xe63c0000 0x1000>; - - smp-sram@0 { - compatible = "renesas,smp-sram"; - reg = <0 0x100>; - }; - }; - - icram2: sram@e6300000 { - compatible = "mmio-sram"; - reg = <0 0xe6300000 0 0x40000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0xe6300000 0x40000>; - }; - - /* The memory map in the User's Manual maps the cores to - * bus numbers - */ - i2c0: i2c@e6508000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7744", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6508000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 931>; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 931>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c1: i2c@e6518000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7744", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6518000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 930>; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 930>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c2: i2c@e6530000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7744", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6530000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 929>; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 929>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c3: i2c@e6540000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7744", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6540000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 928>; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 928>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c4: i2c@e6520000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7744", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6520000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 927>; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 927>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c5: i2c@e6528000 { - /* doesn't need pinmux */ - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7744", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6528000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 925>; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 925>; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - iic0: i2c@e6500000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7744", - "renesas,rcar-gen2-iic", - "renesas,rmobile-iic"; - reg = <0 0xe6500000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 318>; - dmas = <&dmac0 0x61>, <&dmac0 0x62>, - <&dmac1 0x61>, <&dmac1 0x62>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 318>; - status = "disabled"; - }; - - iic1: i2c@e6510000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7744", - "renesas,rcar-gen2-iic", - "renesas,rmobile-iic"; - reg = <0 0xe6510000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 323>; - dmas = <&dmac0 0x65>, <&dmac0 0x66>, - <&dmac1 0x65>, <&dmac1 0x66>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 323>; - status = "disabled"; - }; - - iic3: i2c@e60b0000 { - /* doesn't need pinmux */ - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7744"; - reg = <0 0xe60b0000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 926>; - dmas = <&dmac0 0x77>, <&dmac0 0x78>, - <&dmac1 0x77>, <&dmac1 0x78>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 926>; - status = "disabled"; - }; - - hsusb: usb@e6590000 { - compatible = "renesas,usbhs-r8a7744", - "renesas,rcar-gen2-usbhs"; - reg = <0 0xe6590000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 704>; - dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, - <&usb_dmac1 0>, <&usb_dmac1 1>; - dma-names = "ch0", "ch1", "ch2", "ch3"; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 704>; - renesas,buswait = <4>; - phys = <&usb0 1>; - phy-names = "usb"; - status = "disabled"; - }; - - usbphy: usb-phy@e6590100 { - compatible = "renesas,usb-phy-r8a7744", - "renesas,rcar-gen2-usb-phy"; - reg = <0 0xe6590100 0 0x100>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cpg CPG_MOD 704>; - clock-names = "usbhs"; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 704>; - status = "disabled"; - - usb0: usb-channel@0 { - reg = <0>; - #phy-cells = <1>; - }; - usb2: usb-channel@2 { - reg = <2>; - #phy-cells = <1>; - }; - }; - - usb_dmac0: dma-controller@e65a0000 { - compatible = "renesas,r8a7744-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65a0000 0 0x100>; - interrupts = , - ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 330>; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 330>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - usb_dmac1: dma-controller@e65b0000 { - compatible = "renesas,r8a7744-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65b0000 0 0x100>; - interrupts = , - ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 331>; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 331>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - dmac0: dma-controller@e6700000 { - compatible = "renesas,dmac-r8a7744", - "renesas,rcar-dmac"; - reg = <0 0xe6700000 0 0x20000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14"; - clocks = <&cpg CPG_MOD 219>; - clock-names = "fck"; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 219>; - #dma-cells = <1>; - dma-channels = <15>; - }; - - dmac1: dma-controller@e6720000 { - compatible = "renesas,dmac-r8a7744", - "renesas,rcar-dmac"; - reg = <0 0xe6720000 0 0x20000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14"; - clocks = <&cpg CPG_MOD 218>; - clock-names = "fck"; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 218>; - #dma-cells = <1>; - dma-channels = <15>; - }; - - avb: ethernet@e6800000 { - compatible = "renesas,etheravb-r8a7744", - "renesas,etheravb-rcar-gen2"; - reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; - interrupts = ; - clocks = <&cpg CPG_MOD 812>; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 812>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - qspi: spi@e6b10000 { - compatible = "renesas,qspi-r8a7744", "renesas,qspi"; - reg = <0 0xe6b10000 0 0x2c>; - interrupts = ; - clocks = <&cpg CPG_MOD 917>; - dmas = <&dmac0 0x17>, <&dmac0 0x18>, - <&dmac1 0x17>, <&dmac1 0x18>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - resets = <&cpg 917>; - status = "disabled"; - }; - - scifa0: serial@e6c40000 { - compatible = "renesas,scifa-r8a7744", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c40000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 204>; - clock-names = "fck"; - dmas = <&dmac0 0x21>, <&dmac0 0x22>, - <&dmac1 0x21>, <&dmac1 0x22>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 204>; - status = "disabled"; - }; - - scifa1: serial@e6c50000 { - compatible = "renesas,scifa-r8a7744", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c50000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 203>; - clock-names = "fck"; - dmas = <&dmac0 0x25>, <&dmac0 0x26>, - <&dmac1 0x25>, <&dmac1 0x26>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 203>; - status = "disabled"; - }; - - scifa2: serial@e6c60000 { - compatible = "renesas,scifa-r8a7744", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c60000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 202>; - clock-names = "fck"; - dmas = <&dmac0 0x27>, <&dmac0 0x28>, - <&dmac1 0x27>, <&dmac1 0x28>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 202>; - status = "disabled"; - }; - - scifa3: serial@e6c70000 { - compatible = "renesas,scifa-r8a7744", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c70000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 1106>; - clock-names = "fck"; - dmas = <&dmac0 0x1b>, <&dmac0 0x1c>, - <&dmac1 0x1b>, <&dmac1 0x1c>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 1106>; - status = "disabled"; - }; - - scifa4: serial@e6c78000 { - compatible = "renesas,scifa-r8a7744", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c78000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 1107>; - clock-names = "fck"; - dmas = <&dmac0 0x1f>, <&dmac0 0x20>, - <&dmac1 0x1f>, <&dmac1 0x20>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 1107>; - status = "disabled"; - }; - - scifa5: serial@e6c80000 { - compatible = "renesas,scifa-r8a7744", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c80000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 1108>; - clock-names = "fck"; - dmas = <&dmac0 0x23>, <&dmac0 0x24>, - <&dmac1 0x23>, <&dmac1 0x24>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 1108>; - status = "disabled"; - }; - - scifb0: serial@e6c20000 { - compatible = "renesas,scifb-r8a7744", - "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6c20000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 206>; - clock-names = "fck"; - dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, - <&dmac1 0x3d>, <&dmac1 0x3e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 206>; - status = "disabled"; - }; - - scifb1: serial@e6c30000 { - compatible = "renesas,scifb-r8a7744", - "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6c30000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 207>; - clock-names = "fck"; - dmas = <&dmac0 0x19>, <&dmac0 0x1a>, - <&dmac1 0x19>, <&dmac1 0x1a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 207>; - status = "disabled"; - }; - - scifb2: serial@e6ce0000 { - compatible = "renesas,scifb-r8a7744", - "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6ce0000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 216>; - clock-names = "fck"; - dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, - <&dmac1 0x1d>, <&dmac1 0x1e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 216>; - status = "disabled"; - }; - - scif0: serial@e6e60000 { - compatible = "renesas,scif-r8a7744", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6e60000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 721>, - <&cpg CPG_CORE R8A7744_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x29>, <&dmac0 0x2a>, - <&dmac1 0x29>, <&dmac1 0x2a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 721>; - status = "disabled"; - }; - - scif1: serial@e6e68000 { - compatible = "renesas,scif-r8a7744", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6e68000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 720>, - <&cpg CPG_CORE R8A7744_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, - <&dmac1 0x2d>, <&dmac1 0x2e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 720>; - status = "disabled"; - }; - - scif2: serial@e6e58000 { - compatible = "renesas,scif-r8a7744", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6e58000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 719>, - <&cpg CPG_CORE R8A7744_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, - <&dmac1 0x2b>, <&dmac1 0x2c>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 719>; - status = "disabled"; - }; - - scif3: serial@e6ea8000 { - compatible = "renesas,scif-r8a7744", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6ea8000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 718>, - <&cpg CPG_CORE R8A7744_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2f>, <&dmac0 0x30>, - <&dmac1 0x2f>, <&dmac1 0x30>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 718>; - status = "disabled"; - }; - - scif4: serial@e6ee0000 { - compatible = "renesas,scif-r8a7744", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6ee0000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 715>, - <&cpg CPG_CORE R8A7744_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0xfb>, <&dmac0 0xfc>, - <&dmac1 0xfb>, <&dmac1 0xfc>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 715>; - status = "disabled"; - }; - - scif5: serial@e6ee8000 { - compatible = "renesas,scif-r8a7744", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6ee8000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 714>, - <&cpg CPG_CORE R8A7744_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0xfd>, <&dmac0 0xfe>, - <&dmac1 0xfd>, <&dmac1 0xfe>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 714>; - status = "disabled"; - }; - - hscif0: serial@e62c0000 { - compatible = "renesas,hscif-r8a7744", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62c0000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 717>, - <&cpg CPG_CORE R8A7744_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x39>, <&dmac0 0x3a>, - <&dmac1 0x39>, <&dmac1 0x3a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 717>; - status = "disabled"; - }; - - hscif1: serial@e62c8000 { - compatible = "renesas,hscif-r8a7744", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62c8000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 716>, - <&cpg CPG_CORE R8A7744_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, - <&dmac1 0x4d>, <&dmac1 0x4e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 716>; - status = "disabled"; - }; - - hscif2: serial@e62d0000 { - compatible = "renesas,hscif-r8a7744", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62d0000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 713>, - <&cpg CPG_CORE R8A7744_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x3b>, <&dmac0 0x3c>, - <&dmac1 0x3b>, <&dmac1 0x3c>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 713>; - status = "disabled"; - }; - - msiof0: spi@e6e20000 { - compatible = "renesas,msiof-r8a7744", - "renesas,rcar-gen2-msiof"; - reg = <0 0xe6e20000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 000>; - dmas = <&dmac0 0x51>, <&dmac0 0x52>, - <&dmac1 0x51>, <&dmac1 0x52>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - #address-cells = <1>; - #size-cells = <0>; - resets = <&cpg 000>; - status = "disabled"; - }; - - msiof1: spi@e6e10000 { - compatible = "renesas,msiof-r8a7744", - "renesas,rcar-gen2-msiof"; - reg = <0 0xe6e10000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 208>; - dmas = <&dmac0 0x55>, <&dmac0 0x56>, - <&dmac1 0x55>, <&dmac1 0x56>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - #address-cells = <1>; - #size-cells = <0>; - resets = <&cpg 208>; - status = "disabled"; - }; - - msiof2: spi@e6e00000 { - compatible = "renesas,msiof-r8a7744", - "renesas,rcar-gen2-msiof"; - reg = <0 0xe6e00000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 205>; - dmas = <&dmac0 0x41>, <&dmac0 0x42>, - <&dmac1 0x41>, <&dmac1 0x42>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - #address-cells = <1>; - #size-cells = <0>; - resets = <&cpg 205>; - status = "disabled"; - }; - - pwm0: pwm@e6e30000 { - compatible = "renesas,pwm-r8a7744", "renesas,pwm-rcar"; - reg = <0 0xe6e30000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm1: pwm@e6e31000 { - compatible = "renesas,pwm-r8a7744", "renesas,pwm-rcar"; - reg = <0 0xe6e31000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm2: pwm@e6e32000 { - compatible = "renesas,pwm-r8a7744", "renesas,pwm-rcar"; - reg = <0 0xe6e32000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm3: pwm@e6e33000 { - compatible = "renesas,pwm-r8a7744", "renesas,pwm-rcar"; - reg = <0 0xe6e33000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm4: pwm@e6e34000 { - compatible = "renesas,pwm-r8a7744", "renesas,pwm-rcar"; - reg = <0 0xe6e34000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm5: pwm@e6e35000 { - compatible = "renesas,pwm-r8a7744", "renesas,pwm-rcar"; - reg = <0 0xe6e35000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm6: pwm@e6e36000 { - compatible = "renesas,pwm-r8a7744", "renesas,pwm-rcar"; - reg = <0 0xe6e36000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - can0: can@e6e80000 { - compatible = "renesas,can-r8a7744", - "renesas,rcar-gen2-can"; - reg = <0 0xe6e80000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 916>, - <&cpg CPG_CORE R8A7744_CLK_RCAN>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 916>; - status = "disabled"; - }; - - can1: can@e6e88000 { - compatible = "renesas,can-r8a7744", - "renesas,rcar-gen2-can"; - reg = <0 0xe6e88000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 915>, - <&cpg CPG_CORE R8A7744_CLK_RCAN>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 915>; - status = "disabled"; - }; - - vin0: video@e6ef0000 { - compatible = "renesas,vin-r8a7744", - "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef0000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 811>; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 811>; - status = "disabled"; - }; - - vin1: video@e6ef1000 { - compatible = "renesas,vin-r8a7744", - "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef1000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 810>; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 810>; - status = "disabled"; - }; - - vin2: video@e6ef2000 { - compatible = "renesas,vin-r8a7744", - "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef2000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 809>; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 809>; - status = "disabled"; - }; - - rcar_sound: sound@ec500000 { - /* - * #sound-dai-cells is required - * - * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; - * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; - */ - compatible = "renesas,rcar_sound-r8a7744", - "renesas,rcar_sound-gen2"; - reg = <0 0xec500000 0 0x1000>, /* SCU */ - <0 0xec5a0000 0 0x100>, /* ADG */ - <0 0xec540000 0 0x1000>, /* SSIU */ - <0 0xec541000 0 0x280>, /* SSI */ - <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ - reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; - - clocks = <&cpg CPG_MOD 1005>, - <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, - <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, - <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, - <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, - <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, - <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, - <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, - <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, - <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, - <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, - <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, - <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, - <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, - <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, - <&cpg CPG_CORE R8A7744_CLK_M2>; - clock-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", - "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0", - "src.9", "src.8", "src.7", "src.6", "src.5", - "src.4", "src.3", "src.2", "src.1", "src.0", - "ctu.0", "ctu.1", - "mix.0", "mix.1", - "dvc.0", "dvc.1", - "clk_a", "clk_b", "clk_c", "clk_i"; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 1005>, - <&cpg 1006>, <&cpg 1007>, <&cpg 1008>, <&cpg 1009>, - <&cpg 1010>, <&cpg 1011>, <&cpg 1012>, <&cpg 1013>, - <&cpg 1014>, <&cpg 1015>; - reset-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", - "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0"; - status = "disabled"; - - rcar_sound,dvc { - dvc0: dvc-0 { - dmas = <&audma1 0xbc>; - dma-names = "tx"; - }; - dvc1: dvc-1 { - dmas = <&audma1 0xbe>; - dma-names = "tx"; - }; - }; - - rcar_sound,mix { - mix0: mix-0 { }; - mix1: mix-1 { }; - }; - - rcar_sound,ctu { - ctu00: ctu-0 { }; - ctu01: ctu-1 { }; - ctu02: ctu-2 { }; - ctu03: ctu-3 { }; - ctu10: ctu-4 { }; - ctu11: ctu-5 { }; - ctu12: ctu-6 { }; - ctu13: ctu-7 { }; - }; - - rcar_sound,src { - src0: src-0 { - interrupts = ; - dmas = <&audma0 0x85>, <&audma1 0x9a>; - dma-names = "rx", "tx"; - }; - src1: src-1 { - interrupts = ; - dmas = <&audma0 0x87>, <&audma1 0x9c>; - dma-names = "rx", "tx"; - }; - src2: src-2 { - interrupts = ; - dmas = <&audma0 0x89>, <&audma1 0x9e>; - dma-names = "rx", "tx"; - }; - src3: src-3 { - interrupts = ; - dmas = <&audma0 0x8b>, <&audma1 0xa0>; - dma-names = "rx", "tx"; - }; - src4: src-4 { - interrupts = ; - dmas = <&audma0 0x8d>, <&audma1 0xb0>; - dma-names = "rx", "tx"; - }; - src5: src-5 { - interrupts = ; - dmas = <&audma0 0x8f>, <&audma1 0xb2>; - dma-names = "rx", "tx"; - }; - src6: src-6 { - interrupts = ; - dmas = <&audma0 0x91>, <&audma1 0xb4>; - dma-names = "rx", "tx"; - }; - src7: src-7 { - interrupts = ; - dmas = <&audma0 0x93>, <&audma1 0xb6>; - dma-names = "rx", "tx"; - }; - src8: src-8 { - interrupts = ; - dmas = <&audma0 0x95>, <&audma1 0xb8>; - dma-names = "rx", "tx"; - }; - src9: src-9 { - interrupts = ; - dmas = <&audma0 0x97>, <&audma1 0xba>; - dma-names = "rx", "tx"; - }; - }; - - rcar_sound,ssi { - ssi0: ssi-0 { - interrupts = ; - dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi1: ssi-1 { - interrupts = ; - dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi2: ssi-2 { - interrupts = ; - dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi3: ssi-3 { - interrupts = ; - dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi4: ssi-4 { - interrupts = ; - dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi5: ssi-5 { - interrupts = ; - dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi6: ssi-6 { - interrupts = ; - dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi7: ssi-7 { - interrupts = ; - dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi8: ssi-8 { - interrupts = ; - dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi9: ssi-9 { - interrupts = ; - dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - }; - }; - - audma0: dma-controller@ec700000 { - compatible = "renesas,dmac-r8a7744", - "renesas,rcar-dmac"; - reg = <0 0xec700000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12"; - clocks = <&cpg CPG_MOD 502>; - clock-names = "fck"; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 502>; - #dma-cells = <1>; - dma-channels = <13>; - }; - - audma1: dma-controller@ec720000 { - compatible = "renesas,dmac-r8a7744", - "renesas,rcar-dmac"; - reg = <0 0xec720000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12"; - clocks = <&cpg CPG_MOD 501>; - clock-names = "fck"; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 501>; - #dma-cells = <1>; - dma-channels = <13>; - }; - - /* - * pci1 and xhci share the same phy, therefore only one of them - * can be active at any one time. If both of them are enabled, - * a race condition will determine who'll control the phy. - * A firmware file is needed by the xhci driver in order for - * USB 3.0 to work properly. - */ - xhci: usb@ee000000 { - compatible = "renesas,xhci-r8a7744", - "renesas,rcar-gen2-xhci"; - reg = <0 0xee000000 0 0xc00>; - interrupts = ; - clocks = <&cpg CPG_MOD 328>; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 328>; - phys = <&usb2 1>; - phy-names = "usb"; - status = "disabled"; - }; - - pci0: pci@ee090000 { - compatible = "renesas,pci-r8a7744", - "renesas,pci-rcar-gen2"; - device_type = "pci"; - reg = <0 0xee090000 0 0xc00>, - <0 0xee080000 0 0x1100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 703>; - status = "disabled"; - - bus-range = <0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>; - interrupt-map-mask = <0xf800 0 0 0x7>; - interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, - <0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, - <0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; - - usb@1,0 { - reg = <0x800 0 0 0 0>; - phys = <&usb0 0>; - phy-names = "usb"; - }; - - usb@2,0 { - reg = <0x1000 0 0 0 0>; - phys = <&usb0 0>; - phy-names = "usb"; - }; - }; - - pci1: pci@ee0d0000 { - compatible = "renesas,pci-r8a7744", - "renesas,pci-rcar-gen2"; - device_type = "pci"; - reg = <0 0xee0d0000 0 0xc00>, - <0 0xee0c0000 0 0x1100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 703>; - status = "disabled"; - - bus-range = <1 1>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>; - interrupt-map-mask = <0xf800 0 0 0x7>; - interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, - <0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, - <0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; - - usb@1,0 { - reg = <0x10800 0 0 0 0>; - phys = <&usb2 0>; - phy-names = "usb"; - }; - - usb@2,0 { - reg = <0x11000 0 0 0 0>; - phys = <&usb2 0>; - phy-names = "usb"; - }; - }; - - sdhi0: sd@ee100000 { - compatible = "renesas,sdhi-r8a7744", - "renesas,rcar-gen2-sdhi"; - reg = <0 0xee100000 0 0x328>; - interrupts = ; - clocks = <&cpg CPG_MOD 314>; - dmas = <&dmac0 0xcd>, <&dmac0 0xce>, - <&dmac1 0xcd>, <&dmac1 0xce>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <195000000>; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 314>; - status = "disabled"; - }; - - sdhi1: sd@ee140000 { - compatible = "renesas,sdhi-r8a7744", - "renesas,rcar-gen2-sdhi"; - reg = <0 0xee140000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 312>; - dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, - <&dmac1 0xc1>, <&dmac1 0xc2>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <97500000>; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 312>; - status = "disabled"; - }; - - sdhi2: sd@ee160000 { - compatible = "renesas,sdhi-r8a7744", - "renesas,rcar-gen2-sdhi"; - reg = <0 0xee160000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 311>; - dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, - <&dmac1 0xd3>, <&dmac1 0xd4>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <97500000>; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 311>; - status = "disabled"; - }; - - mmcif0: mmc@ee200000 { - compatible = "renesas,mmcif-r8a7744", - "renesas,sh-mmcif"; - reg = <0 0xee200000 0 0x80>; - interrupts = ; - clocks = <&cpg CPG_MOD 315>; - dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, - <&dmac1 0xd1>, <&dmac1 0xd2>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 315>; - reg-io-width = <4>; - max-frequency = <97500000>; - status = "disabled"; - }; - - gic: interrupt-controller@f1001000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>, - <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 408>; - clock-names = "clk"; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 408>; - }; - - pciec: pcie@fe000000 { - compatible = "renesas,pcie-r8a7744", - "renesas,pcie-rcar-gen2"; - reg = <0 0xfe000000 0 0x80000>; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x00 0xff>; - device_type = "pci"; - ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, - <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, - <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, - <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>, - <0x43000000 2 0x00000000 2 0x00000000 1 0x00000000>; - interrupts = , - , - ; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; - clock-names = "pcie", "pcie_bus"; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 319>; - status = "disabled"; - }; - - vsp@fe928000 { - compatible = "renesas,vsp1"; - reg = <0 0xfe928000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 131>; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 131>; - }; - - vsp@fe930000 { - compatible = "renesas,vsp1"; - reg = <0 0xfe930000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 128>; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 128>; - }; - - vsp@fe938000 { - compatible = "renesas,vsp1"; - reg = <0 0xfe938000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 127>; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 127>; - }; - - du: display@feb00000 { - compatible = "renesas,du-r8a7744"; - reg = <0 0xfeb00000 0 0x40000>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>; - clock-names = "du.0", "du.1"; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - du_out_rgb: endpoint { - }; - }; - port@1 { - reg = <1>; - du_out_lvds0: endpoint { - remote-endpoint = <&lvds0_in>; - }; - }; - }; - }; - - lvds0: lvds@feb90000 { - compatible = "renesas,r8a7744-lvds"; - reg = <0 0xfeb90000 0 0x1c>; - clocks = <&cpg CPG_MOD 726>; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 726>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - lvds0_in: endpoint { - remote-endpoint = <&du_out_lvds0>; - }; - }; - port@1 { - reg = <1>; - lvds0_out: endpoint { - }; - }; - }; - }; - - prr: chipid@ff000044 { - compatible = "renesas,prr"; - reg = <0 0xff000044 0 4>; - }; - - cmt0: timer@ffca0000 { - compatible = "renesas,r8a7744-cmt0", - "renesas,rcar-gen2-cmt0"; - reg = <0 0xffca0000 0 0x1004>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 124>; - clock-names = "fck"; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 124>; - status = "disabled"; - }; - - cmt1: timer@e6130000 { - compatible = "renesas,r8a7744-cmt1", - "renesas,rcar-gen2-cmt1"; - reg = <0 0xe6130000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 329>; - clock-names = "fck"; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 329>; - status = "disabled"; - }; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - - thermal-sensors = <&thermal>; - - trips { - cpu-crit { - temperature = <95000>; - hysteresis = <0>; - type = "critical"; - }; - }; - - cooling-maps { - }; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; - }; - - /* External USB clock - can be overridden by the board */ - usb_extal_clk: usb_extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <48000000>; - }; -}; diff --git a/sys/gnu/dts/arm/r8a7745-iwg22d-sodimm-dbhd-ca.dts b/sys/gnu/dts/arm/r8a7745-iwg22d-sodimm-dbhd-ca.dts deleted file mode 100644 index 2aeebfc9e4f..00000000000 --- a/sys/gnu/dts/arm/r8a7745-iwg22d-sodimm-dbhd-ca.dts +++ /dev/null @@ -1,155 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the iWave-RZG1E SODIMM carrier board + HDMI daughter - * board - * - * Copyright (C) 2017 Renesas Electronics Corp. - */ - -#include "r8a7745-iwg22d-sodimm.dts" - -/ { - model = "iWave RainboW-G22D-SODIMM RZ/G1E based board with HDMI add-on"; - compatible = "iwave,g22d", "iwave,g22m", "renesas,r8a7745"; - - aliases { - serial0 = &scif1; - serial4 = &scif5; - serial6 = &hscif2; - }; - - cec_clock: cec-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <12000000>; - }; - - hdmi-out { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con: endpoint { - remote-endpoint = <&adv7511_out>; - }; - }; - }; -}; - -&du { - pinctrl-0 = <&du0_pins>; - pinctrl-names = "default"; - - status = "okay"; - - ports { - port@0 { - endpoint { - remote-endpoint = <&adv7511_in>; - }; - }; - }; -}; - -&can1 { - pinctrl-0 = <&can1_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&hscif2 { - pinctrl-0 = <&hscif2_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&i2c1 { - pinctrl-0 = <&i2c1_pins>; - pinctrl-names = "default"; - - status = "okay"; - clock-frequency = <400000>; - - hdmi@39 { - compatible = "adi,adv7511w"; - reg = <0x39>; - interrupt-parent = <&gpio1>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - clocks = <&cec_clock>; - clock-names = "cec"; - pd-gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>; - - adi,input-depth = <8>; - adi,input-colorspace = "rgb"; - adi,input-clock = "1x"; - adi,input-style = <1>; - adi,input-justification = "evenly"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7511_in: endpoint { - remote-endpoint = <&du_out_rgb0>; - }; - }; - - port@1 { - reg = <1>; - adv7511_out: endpoint { - remote-endpoint = <&hdmi_con>; - }; - }; - }; - }; -}; - -&pfc { - can1_pins: can1 { - groups = "can1_data_b"; - function = "can1"; - }; - - du0_pins: du0 { - groups = "du0_rgb888", "du0_sync", "du0_disp", "du0_clk0_out"; - function = "du0"; - }; - - hscif2_pins: hscif2 { - groups = "hscif2_data"; - function = "hscif2"; - }; - - i2c1_pins: i2c1 { - groups = "i2c1_d"; - function = "i2c1"; - }; - - scif1_pins: scif1 { - groups = "scif1_data"; - function = "scif1"; - }; - - scif5_pins: scif5 { - groups = "scif5_data_d"; - function = "scif5"; - }; -}; - -&scif1 { - pinctrl-0 = <&scif1_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&scif5 { - pinctrl-0 = <&scif5_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/r8a7745-iwg22d-sodimm.dts b/sys/gnu/dts/arm/r8a7745-iwg22d-sodimm.dts deleted file mode 100644 index 58d369ad827..00000000000 --- a/sys/gnu/dts/arm/r8a7745-iwg22d-sodimm.dts +++ /dev/null @@ -1,234 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the iWave-RZG1E SODIMM carrier board - * - * Copyright (C) 2017 Renesas Electronics Corp. - */ - -/* - * SSI-SGTL5000 - * - * This command is required when Playback/Capture - * - * amixer set "DVC Out" 100% - * amixer set "DVC In" 100% - * - * You can use Mute - * - * amixer set "DVC Out Mute" on - * amixer set "DVC In Mute" on - * - * You can use Volume Ramp - * - * amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps" - * amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps" - * amixer set "DVC Out Ramp" on - * aplay xxx.wav & - * amixer set "DVC Out" 80% // Volume Down - * amixer set "DVC Out" 100% // Volume Up - */ - -/dts-v1/; -#include "r8a7745-iwg22m.dtsi" - -/ { - model = "iWave Systems RainboW-G22D-SODIMM board based on RZ/G1E"; - compatible = "iwave,g22d", "iwave,g22m", "renesas,r8a7745"; - - aliases { - ethernet0 = &avb; - serial3 = &scif4; - serial5 = &hscif1; - }; - - chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; - stdout-path = "serial3:115200n8"; - }; - - audio_clock: audio_clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <26000000>; - }; - - rsnd_sgtl5000: sound { - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&sndcodec>; - simple-audio-card,frame-master = <&sndcodec>; - - sndcpu: simple-audio-card,cpu { - sound-dai = <&rcar_sound>; - }; - - sndcodec: simple-audio-card,codec { - sound-dai = <&sgtl5000>; - }; - }; - - vccq_sdhi0: regulator-vccq-sdhi0 { - compatible = "regulator-gpio"; - - regulator-name = "SDHI0 VccQ"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; - gpios-states = <1>; - states = <3300000 1>, <1800000 0>; - }; -}; - -&avb { - pinctrl-0 = <&avb_pins>; - pinctrl-names = "default"; - - phy-handle = <&phy3>; - phy-mode = "gmii"; - renesas,no-ether-link; - status = "okay"; - - phy3: ethernet-phy@3 { - /* - * On some older versions of the platform (before R4.0) the phy address - * may be 1 or 3. The address is fixed to 3 for R4.0 onwards. - */ - reg = <3>; - micrel,led-mode = <1>; - }; -}; - -&can0 { - pinctrl-0 = <&can0_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&hscif1 { - pinctrl-0 = <&hscif1_pins>; - pinctrl-names = "default"; - - uart-has-rtscts; - status = "okay"; -}; - -&hsusb { - status = "okay"; - pinctrl-0 = <&usb0_pins>; - pinctrl-names = "default"; -}; - -&i2c5 { - pinctrl-0 = <&i2c5_pins>; - pinctrl-names = "default"; - - status = "okay"; - clock-frequency = <400000>; - - sgtl5000: codec@a { - compatible = "fsl,sgtl5000"; - #sound-dai-cells = <0>; - reg = <0x0a>; - clocks = <&audio_clock>; - VDDA-supply = <®_3p3v>; - VDDIO-supply = <®_3p3v>; - }; -}; - -&pci1 { - status = "okay"; - pinctrl-0 = <&usb1_pins>; - pinctrl-names = "default"; -}; - -&pfc { - avb_pins: avb { - groups = "avb_mdio", "avb_gmii"; - function = "avb"; - }; - - can0_pins: can0 { - groups = "can0_data"; - function = "can0"; - }; - - hscif1_pins: hscif1 { - groups = "hscif1_data", "hscif1_ctrl"; - function = "hscif1"; - }; - - i2c5_pins: i2c5 { - groups = "i2c5_b"; - function = "i2c5"; - }; - - scif4_pins: scif4 { - groups = "scif4_data_b"; - function = "scif4"; - }; - - sdhi0_pins: sd0 { - groups = "sdhi0_data4", "sdhi0_ctrl"; - function = "sdhi0"; - power-source = <3300>; - }; - - sound_pins: sound { - groups = "ssi34_ctrl", "ssi3_data", "ssi4_data"; - function = "ssi"; - }; - - usb0_pins: usb0 { - groups = "usb0"; - function = "usb0"; - }; - - usb1_pins: usb1 { - groups = "usb1"; - function = "usb1"; - }; -}; - -&rcar_sound { - pinctrl-0 = <&sound_pins>; - pinctrl-names = "default"; - status = "okay"; - - /* Single DAI */ - - #sound-dai-cells = <0>; - - rcar_sound,dai { - dai0 { - playback = <&ssi3 &src3 &dvc0>; - capture = <&ssi4 &src4 &dvc1>; - }; - }; -}; - -&scif4 { - pinctrl-0 = <&scif4_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&sdhi0 { - pinctrl-0 = <&sdhi0_pins>; - pinctrl-names = "default"; - - vmmc-supply = <®_3p3v>; - vqmmc-supply = <&vccq_sdhi0>; - cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&ssi4 { - shared-pin; -}; - -&usbphy { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/r8a7745-iwg22m.dtsi b/sys/gnu/dts/arm/r8a7745-iwg22m.dtsi deleted file mode 100644 index 41f111b99a7..00000000000 --- a/sys/gnu/dts/arm/r8a7745-iwg22m.dtsi +++ /dev/null @@ -1,117 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the iWave-RZG1E-G22M SODIMM SOM - * - * Copyright (C) 2017 Renesas Electronics Corp. - */ - -#include "r8a7745.dtsi" -#include - -/ { - compatible = "iwave,g22m", "renesas,r8a7745"; - - memory@40000000 { - device_type = "memory"; - reg = <0 0x40000000 0 0x20000000>; - }; - - reg_3p3v: 3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; -}; - -&cmt0 { - status = "okay"; -}; - -&extal_clk { - clock-frequency = <20000000>; -}; - -&pfc { - mmcif0_pins: mmc { - groups = "mmc_data8", "mmc_ctrl"; - function = "mmc"; - }; - - qspi_pins: qspi { - groups = "qspi_ctrl", "qspi_data2"; - function = "qspi"; - }; - - sdhi1_pins: sd1 { - groups = "sdhi1_data4", "sdhi1_ctrl"; - function = "sdhi1"; - power-source = <3300>; - }; - - i2c3_pins: i2c3 { - groups = "i2c3_b"; - function = "i2c3"; - }; -}; - -&mmcif0 { - pinctrl-0 = <&mmcif0_pins>; - pinctrl-names = "default"; - - vmmc-supply = <®_3p3v>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&qspi { - pinctrl-0 = <&qspi_pins>; - pinctrl-names = "default"; - - status = "okay"; - - /* WARNING - This device contains the bootloader. Handle with care. */ - flash: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "sst,sst25vf016b", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <50000000>; - spi-tx-bus-width = <1>; - spi-rx-bus-width = <1>; - m25p,fast-read; - spi-cpol; - spi-cpha; - }; -}; - -&rwdt { - timeout-sec = <60>; - status = "okay"; -}; - -&sdhi1 { - pinctrl-0 = <&sdhi1_pins>; - pinctrl-names = "default"; - - vmmc-supply = <®_3p3v>; - vqmmc-supply = <®_3p3v>; - cd-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&i2c3 { - pinctrl-0 = <&i2c3_pins>; - pinctrl-names = "default"; - - status = "okay"; - clock-frequency = <400000>; - - rtc@68 { - compatible = "ti,bq32000"; - reg = <0x68>; - }; -}; diff --git a/sys/gnu/dts/arm/r8a7745-sk-rzg1e.dts b/sys/gnu/dts/arm/r8a7745-sk-rzg1e.dts deleted file mode 100644 index db72a801abe..00000000000 --- a/sys/gnu/dts/arm/r8a7745-sk-rzg1e.dts +++ /dev/null @@ -1,72 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the SK-RZG1E board - * - * Copyright (C) 2016-2017 Cogent Embedded, Inc. - */ - -/dts-v1/; -#include "r8a7745.dtsi" - -/ { - model = "SK-RZG1E"; - compatible = "renesas,sk-rzg1e", "renesas,r8a7745"; - - aliases { - serial0 = &scif2; - }; - - chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; - stdout-path = "serial0:115200n8"; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0 0x40000000 0 0x40000000>; - }; -}; - -&extal_clk { - clock-frequency = <20000000>; -}; - -&pfc { - scif2_pins: scif2 { - groups = "scif2_data"; - function = "scif2"; - }; - - ether_pins: ether { - groups = "eth_link", "eth_mdio", "eth_rmii"; - function = "eth"; - }; - - phy1_pins: phy1 { - groups = "intc_irq8"; - function = "intc"; - }; -}; - -&scif2 { - pinctrl-0 = <&scif2_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -ðer { - pinctrl-0 = <ðer_pins &phy1_pins>; - pinctrl-names = "default"; - - phy-handle = <&phy1>; - renesas,ether-link-active-low; - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - interrupt-parent = <&irqc>; - interrupts = <8 IRQ_TYPE_LEVEL_LOW>; - micrel,led-mode = <1>; - }; -}; diff --git a/sys/gnu/dts/arm/r8a7745.dtsi b/sys/gnu/dts/arm/r8a7745.dtsi deleted file mode 100644 index 3f88a7e34af..00000000000 --- a/sys/gnu/dts/arm/r8a7745.dtsi +++ /dev/null @@ -1,1585 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the r8a7745 SoC - * - * Copyright (C) 2016-2017 Cogent Embedded Inc. - */ - -#include -#include -#include -#include - -/ { - compatible = "renesas,r8a7745"; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - i2c6 = &iic0; - i2c7 = &iic1; - spi0 = &qspi; - spi1 = &msiof0; - spi2 = &msiof1; - spi3 = &msiof2; - vin0 = &vin0; - vin1 = &vin1; - }; - - /* - * The external audio clocks are configured as 0 Hz fixed - * frequency clocks by default. Boards that provide audio - * clocks should override them. - */ - audio_clka: audio_clka { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - audio_clkb: audio_clkb { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - audio_clkc: audio_clkc { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - /* External CAN clock */ - can_clk: can { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "renesas,apmu"; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0>; - clock-frequency = <1000000000>; - clocks = <&cpg CPG_CORE R8A7745_CLK_Z2>; - power-domains = <&sysc R8A7745_PD_CA7_CPU0>; - next-level-cache = <&L2_CA7>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <1>; - clock-frequency = <1000000000>; - clocks = <&cpg CPG_CORE R8A7745_CLK_Z2>; - power-domains = <&sysc R8A7745_PD_CA7_CPU1>; - next-level-cache = <&L2_CA7>; - }; - - L2_CA7: cache-controller-0 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - power-domains = <&sysc R8A7745_PD_CA7_SCU>; - }; - }; - - /* External root clock */ - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts-extended = <&gic GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&cpu0>, <&cpu1>; - }; - - /* External SCIF clock */ - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - soc { - compatible = "simple-bus"; - interrupt-parent = <&gic>; - - #address-cells = <2>; - #size-cells = <2>; - ranges; - - gpio0: gpio@e6050000 { - compatible = "renesas,gpio-r8a7745", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6050000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 0 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 912>; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 912>; - }; - - gpio1: gpio@e6051000 { - compatible = "renesas,gpio-r8a7745", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6051000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 32 26>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 911>; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 911>; - }; - - gpio2: gpio@e6052000 { - compatible = "renesas,gpio-r8a7745", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6052000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 64 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 910>; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 910>; - }; - - gpio3: gpio@e6053000 { - compatible = "renesas,gpio-r8a7745", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6053000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 96 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 909>; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 909>; - }; - - gpio4: gpio@e6054000 { - compatible = "renesas,gpio-r8a7745", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6054000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 128 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 908>; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 908>; - }; - - gpio5: gpio@e6055000 { - compatible = "renesas,gpio-r8a7745", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6055000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 160 28>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 907>; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 907>; - }; - - gpio6: gpio@e6055400 { - compatible = "renesas,gpio-r8a7745", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6055400 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 192 26>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 905>; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 905>; - }; - - pfc: pin-controller@e6060000 { - compatible = "renesas,pfc-r8a7745"; - reg = <0 0xe6060000 0 0x11c>; - }; - - tpu: pwm@e60f0000 { - compatible = "renesas,tpu-r8a7745", "renesas,tpu"; - reg = <0 0xe60f0000 0 0x148>; - clocks = <&cpg CPG_MOD 304>; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 304>; - #pwm-cells = <3>; - status = "disabled"; - }; - - cpg: clock-controller@e6150000 { - compatible = "renesas,r8a7745-cpg-mssr"; - reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk>, <&usb_extal_clk>; - clock-names = "extal", "usb_extal"; - #clock-cells = <2>; - #power-domain-cells = <0>; - #reset-cells = <1>; - }; - - apmu@e6151000 { - compatible = "renesas,r8a7745-apmu", "renesas,apmu"; - reg = <0 0xe6151000 0 0x188>; - cpus = <&cpu0 &cpu1>; - }; - - rst: reset-controller@e6160000 { - compatible = "renesas,r8a7745-rst"; - reg = <0 0xe6160000 0 0x100>; - }; - - rwdt: watchdog@e6020000 { - compatible = "renesas,r8a7745-wdt", - "renesas,rcar-gen2-wdt"; - reg = <0 0xe6020000 0 0x0c>; - clocks = <&cpg CPG_MOD 402>; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 402>; - status = "disabled"; - }; - - sysc: system-controller@e6180000 { - compatible = "renesas,r8a7745-sysc"; - reg = <0 0xe6180000 0 0x200>; - #power-domain-cells = <1>; - }; - - irqc: interrupt-controller@e61c0000 { - compatible = "renesas,irqc-r8a7745", "renesas,irqc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0 0xe61c0000 0 0x200>; - interrupts = , - , - , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 407>; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 407>; - }; - - ipmmu_sy0: mmu@e6280000 { - compatible = "renesas,ipmmu-r8a7745", - "renesas,ipmmu-vmsa"; - reg = <0 0xe6280000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_sy1: mmu@e6290000 { - compatible = "renesas,ipmmu-r8a7745", - "renesas,ipmmu-vmsa"; - reg = <0 0xe6290000 0 0x1000>; - interrupts = ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_ds: mmu@e6740000 { - compatible = "renesas,ipmmu-r8a7745", - "renesas,ipmmu-vmsa"; - reg = <0 0xe6740000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_mp: mmu@ec680000 { - compatible = "renesas,ipmmu-r8a7745", - "renesas,ipmmu-vmsa"; - reg = <0 0xec680000 0 0x1000>; - interrupts = ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_mx: mmu@fe951000 { - compatible = "renesas,ipmmu-r8a7745", - "renesas,ipmmu-vmsa"; - reg = <0 0xfe951000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_gp: mmu@e62a0000 { - compatible = "renesas,ipmmu-r8a7745", - "renesas,ipmmu-vmsa"; - reg = <0 0xe62a0000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; - - icram0: sram@e63a0000 { - compatible = "mmio-sram"; - reg = <0 0xe63a0000 0 0x12000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0xe63a0000 0x12000>; - }; - - icram1: sram@e63c0000 { - compatible = "mmio-sram"; - reg = <0 0xe63c0000 0 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0xe63c0000 0x1000>; - - smp-sram@0 { - compatible = "renesas,smp-sram"; - reg = <0 0x100>; - }; - }; - - icram2: sram@e6300000 { - compatible = "mmio-sram"; - reg = <0 0xe6300000 0 0x40000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0xe6300000 0x40000>; - }; - i2c0: i2c@e6508000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7745", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6508000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 931>; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 931>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c1: i2c@e6518000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7745", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6518000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 930>; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 930>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c2: i2c@e6530000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7745", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6530000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 929>; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 929>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c3: i2c@e6540000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7745", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6540000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 928>; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 928>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c4: i2c@e6520000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7745", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6520000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 927>; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 927>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c5: i2c@e6528000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7745", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6528000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 925>; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 925>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - iic0: i2c@e6500000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7745", - "renesas,rcar-gen2-iic", - "renesas,rmobile-iic"; - reg = <0 0xe6500000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 318>; - dmas = <&dmac0 0x61>, <&dmac0 0x62>, - <&dmac1 0x61>, <&dmac1 0x62>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 318>; - status = "disabled"; - }; - - iic1: i2c@e6510000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7745", - "renesas,rcar-gen2-iic", - "renesas,rmobile-iic"; - reg = <0 0xe6510000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 323>; - dmas = <&dmac0 0x65>, <&dmac0 0x66>, - <&dmac1 0x65>, <&dmac1 0x66>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 323>; - status = "disabled"; - }; - - hsusb: usb@e6590000 { - compatible = "renesas,usbhs-r8a7745", - "renesas,rcar-gen2-usbhs"; - reg = <0 0xe6590000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 704>; - dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, - <&usb_dmac1 0>, <&usb_dmac1 1>; - dma-names = "ch0", "ch1", "ch2", "ch3"; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 704>; - renesas,buswait = <4>; - phys = <&usb0 1>; - phy-names = "usb"; - status = "disabled"; - }; - - usbphy: usb-phy@e6590100 { - compatible = "renesas,usb-phy-r8a7745", - "renesas,rcar-gen2-usb-phy"; - reg = <0 0xe6590100 0 0x100>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cpg CPG_MOD 704>; - clock-names = "usbhs"; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 704>; - status = "disabled"; - - usb0: usb-channel@0 { - reg = <0>; - #phy-cells = <1>; - }; - usb2: usb-channel@2 { - reg = <2>; - #phy-cells = <1>; - }; - }; - - usb_dmac0: dma-controller@e65a0000 { - compatible = "renesas,r8a7745-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65a0000 0 0x100>; - interrupts = , - ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 330>; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 330>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - usb_dmac1: dma-controller@e65b0000 { - compatible = "renesas,r8a7745-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65b0000 0 0x100>; - interrupts = , - ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 331>; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 331>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - dmac0: dma-controller@e6700000 { - compatible = "renesas,dmac-r8a7745", - "renesas,rcar-dmac"; - reg = <0 0xe6700000 0 0x20000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14"; - clocks = <&cpg CPG_MOD 219>; - clock-names = "fck"; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 219>; - #dma-cells = <1>; - dma-channels = <15>; - }; - - dmac1: dma-controller@e6720000 { - compatible = "renesas,dmac-r8a7745", - "renesas,rcar-dmac"; - reg = <0 0xe6720000 0 0x20000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14"; - clocks = <&cpg CPG_MOD 218>; - clock-names = "fck"; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 218>; - #dma-cells = <1>; - dma-channels = <15>; - }; - - avb: ethernet@e6800000 { - compatible = "renesas,etheravb-r8a7745", - "renesas,etheravb-rcar-gen2"; - reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; - interrupts = ; - clocks = <&cpg CPG_MOD 812>; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 812>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - qspi: spi@e6b10000 { - compatible = "renesas,qspi-r8a7745", "renesas,qspi"; - reg = <0 0xe6b10000 0 0x2c>; - interrupts = ; - clocks = <&cpg CPG_MOD 917>; - dmas = <&dmac0 0x17>, <&dmac0 0x18>, - <&dmac1 0x17>, <&dmac1 0x18>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - resets = <&cpg 917>; - status = "disabled"; - }; - - scifa0: serial@e6c40000 { - compatible = "renesas,scifa-r8a7745", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c40000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 204>; - clock-names = "fck"; - dmas = <&dmac0 0x21>, <&dmac0 0x22>, - <&dmac1 0x21>, <&dmac1 0x22>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 204>; - status = "disabled"; - }; - - scifa1: serial@e6c50000 { - compatible = "renesas,scifa-r8a7745", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c50000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 203>; - clock-names = "fck"; - dmas = <&dmac0 0x25>, <&dmac0 0x26>, - <&dmac1 0x25>, <&dmac1 0x26>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 203>; - status = "disabled"; - }; - - scifa2: serial@e6c60000 { - compatible = "renesas,scifa-r8a7745", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c60000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 202>; - clock-names = "fck"; - dmas = <&dmac0 0x27>, <&dmac0 0x28>, - <&dmac1 0x27>, <&dmac1 0x28>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 202>; - status = "disabled"; - }; - - scifa3: serial@e6c70000 { - compatible = "renesas,scifa-r8a7745", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c70000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 1106>; - clock-names = "fck"; - dmas = <&dmac0 0x1b>, <&dmac0 0x1c>, - <&dmac1 0x1b>, <&dmac1 0x1c>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 1106>; - status = "disabled"; - }; - - scifa4: serial@e6c78000 { - compatible = "renesas,scifa-r8a7745", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c78000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 1107>; - clock-names = "fck"; - dmas = <&dmac0 0x1f>, <&dmac0 0x20>, - <&dmac1 0x1f>, <&dmac1 0x20>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 1107>; - status = "disabled"; - }; - - scifa5: serial@e6c80000 { - compatible = "renesas,scifa-r8a7745", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c80000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 1108>; - clock-names = "fck"; - dmas = <&dmac0 0x23>, <&dmac0 0x24>, - <&dmac1 0x23>, <&dmac1 0x24>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 1108>; - status = "disabled"; - }; - - scifb0: serial@e6c20000 { - compatible = "renesas,scifb-r8a7745", - "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6c20000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 206>; - clock-names = "fck"; - dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, - <&dmac1 0x3d>, <&dmac1 0x3e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 206>; - status = "disabled"; - }; - - scifb1: serial@e6c30000 { - compatible = "renesas,scifb-r8a7745", - "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6c30000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 207>; - clock-names = "fck"; - dmas = <&dmac0 0x19>, <&dmac0 0x1a>, - <&dmac1 0x19>, <&dmac1 0x1a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 207>; - status = "disabled"; - }; - - scifb2: serial@e6ce0000 { - compatible = "renesas,scifb-r8a7745", - "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6ce0000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 216>; - clock-names = "fck"; - dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, - <&dmac1 0x1d>, <&dmac1 0x1e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 216>; - status = "disabled"; - }; - - scif0: serial@e6e60000 { - compatible = "renesas,scif-r8a7745", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6e60000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 721>, - <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x29>, <&dmac0 0x2a>, - <&dmac1 0x29>, <&dmac1 0x2a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 721>; - status = "disabled"; - }; - - scif1: serial@e6e68000 { - compatible = "renesas,scif-r8a7745", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6e68000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 720>, - <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, - <&dmac1 0x2d>, <&dmac1 0x2e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 720>; - status = "disabled"; - }; - - scif2: serial@e6e58000 { - compatible = "renesas,scif-r8a7745", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6e58000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 719>, - <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, - <&dmac1 0x2b>, <&dmac1 0x2c>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 719>; - status = "disabled"; - }; - - scif3: serial@e6ea8000 { - compatible = "renesas,scif-r8a7745", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6ea8000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 718>, - <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2f>, <&dmac0 0x30>, - <&dmac1 0x2f>, <&dmac1 0x30>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 718>; - status = "disabled"; - }; - - scif4: serial@e6ee0000 { - compatible = "renesas,scif-r8a7745", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6ee0000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 715>, - <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0xfb>, <&dmac0 0xfc>, - <&dmac1 0xfb>, <&dmac1 0xfc>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 715>; - status = "disabled"; - }; - - scif5: serial@e6ee8000 { - compatible = "renesas,scif-r8a7745", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6ee8000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 714>, - <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0xfd>, <&dmac0 0xfe>, - <&dmac1 0xfd>, <&dmac1 0xfe>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 714>; - status = "disabled"; - }; - - hscif0: serial@e62c0000 { - compatible = "renesas,hscif-r8a7745", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62c0000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 717>, - <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x39>, <&dmac0 0x3a>, - <&dmac1 0x39>, <&dmac1 0x3a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 717>; - status = "disabled"; - }; - - hscif1: serial@e62c8000 { - compatible = "renesas,hscif-r8a7745", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62c8000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 716>, - <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, - <&dmac1 0x4d>, <&dmac1 0x4e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 716>; - status = "disabled"; - }; - - hscif2: serial@e62d0000 { - compatible = "renesas,hscif-r8a7745", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62d0000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 713>, - <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x3b>, <&dmac0 0x3c>, - <&dmac1 0x3b>, <&dmac1 0x3c>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 713>; - status = "disabled"; - }; - - msiof0: spi@e6e20000 { - compatible = "renesas,msiof-r8a7745", - "renesas,rcar-gen2-msiof"; - reg = <0 0xe6e20000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 000>; - dmas = <&dmac0 0x51>, <&dmac0 0x52>, - <&dmac1 0x51>, <&dmac1 0x52>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - #address-cells = <1>; - #size-cells = <0>; - resets = <&cpg 000>; - status = "disabled"; - }; - - msiof1: spi@e6e10000 { - compatible = "renesas,msiof-r8a7745", - "renesas,rcar-gen2-msiof"; - reg = <0 0xe6e10000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 208>; - dmas = <&dmac0 0x55>, <&dmac0 0x56>, - <&dmac1 0x55>, <&dmac1 0x56>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - #address-cells = <1>; - #size-cells = <0>; - resets = <&cpg 208>; - status = "disabled"; - }; - - msiof2: spi@e6e00000 { - compatible = "renesas,msiof-r8a7745", - "renesas,rcar-gen2-msiof"; - reg = <0 0xe6e00000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 205>; - dmas = <&dmac0 0x41>, <&dmac0 0x42>, - <&dmac1 0x41>, <&dmac1 0x42>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - #address-cells = <1>; - #size-cells = <0>; - resets = <&cpg 205>; - status = "disabled"; - }; - - pwm0: pwm@e6e30000 { - compatible = "renesas,pwm-r8a7745", "renesas,pwm-rcar"; - reg = <0 0xe6e30000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm1: pwm@e6e31000 { - compatible = "renesas,pwm-r8a7745", "renesas,pwm-rcar"; - reg = <0 0xe6e31000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm2: pwm@e6e32000 { - compatible = "renesas,pwm-r8a7745", "renesas,pwm-rcar"; - reg = <0 0xe6e32000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm3: pwm@e6e33000 { - compatible = "renesas,pwm-r8a7745", "renesas,pwm-rcar"; - reg = <0 0xe6e33000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm4: pwm@e6e34000 { - compatible = "renesas,pwm-r8a7745", "renesas,pwm-rcar"; - reg = <0 0xe6e34000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm5: pwm@e6e35000 { - compatible = "renesas,pwm-r8a7745", "renesas,pwm-rcar"; - reg = <0 0xe6e35000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm6: pwm@e6e36000 { - compatible = "renesas,pwm-r8a7745", "renesas,pwm-rcar"; - reg = <0 0xe6e36000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - can0: can@e6e80000 { - compatible = "renesas,can-r8a7745", - "renesas,rcar-gen2-can"; - reg = <0 0xe6e80000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 916>, - <&cpg CPG_CORE R8A7745_CLK_RCAN>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 916>; - status = "disabled"; - }; - - can1: can@e6e88000 { - compatible = "renesas,can-r8a7745", - "renesas,rcar-gen2-can"; - reg = <0 0xe6e88000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 915>, - <&cpg CPG_CORE R8A7745_CLK_RCAN>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 915>; - status = "disabled"; - }; - - vin0: video@e6ef0000 { - compatible = "renesas,vin-r8a7745", - "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef0000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 811>; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 811>; - status = "disabled"; - }; - - vin1: video@e6ef1000 { - compatible = "renesas,vin-r8a7745", - "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef1000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 810>; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 810>; - status = "disabled"; - }; - - rcar_sound: sound@ec500000 { - /* - * #sound-dai-cells is required - * - * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; - * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; - */ - compatible = "renesas,rcar_sound-r8a7745", - "renesas,rcar_sound-gen2"; - reg = <0 0xec500000 0 0x1000>, /* SCU */ - <0 0xec5a0000 0 0x100>, /* ADG */ - <0 0xec540000 0 0x1000>, /* SSIU */ - <0 0xec541000 0 0x280>, /* SSI */ - <0 0xec740000 0 0x200>; /* Audio DMAC peri peri */ - reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; - - clocks = <&cpg CPG_MOD 1005>, - <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, - <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, - <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, - <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, - <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, - <&cpg CPG_MOD 1025>, <&cpg CPG_MOD 1026>, - <&cpg CPG_MOD 1027>, <&cpg CPG_MOD 1028>, - <&cpg CPG_MOD 1029>, <&cpg CPG_MOD 1030>, - <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, - <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, - <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, - <&audio_clka>, <&audio_clkb>, <&audio_clkc>, - <&cpg CPG_CORE R8A7745_CLK_M2>; - clock-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", - "ssi.5", "ssi.4", "ssi.3", "ssi.2", - "ssi.1", "ssi.0", - "src.6", "src.5", "src.4", "src.3", - "src.2", "src.1", - "ctu.0", "ctu.1", - "mix.0", "mix.1", - "dvc.0", "dvc.1", - "clk_a", "clk_b", "clk_c", "clk_i"; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 1005>, - <&cpg 1006>, <&cpg 1007>, <&cpg 1008>, - <&cpg 1009>, <&cpg 1010>, <&cpg 1011>, - <&cpg 1012>, <&cpg 1013>, <&cpg 1014>, - <&cpg 1015>; - reset-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", - "ssi.5", "ssi.4", "ssi.3", "ssi.2", - "ssi.1", "ssi.0"; - - status = "disabled"; - - rcar_sound,dvc { - dvc0: dvc-0 { - dmas = <&audma0 0xbc>; - dma-names = "tx"; - }; - dvc1: dvc-1 { - dmas = <&audma0 0xbe>; - dma-names = "tx"; - }; - }; - - rcar_sound,mix { - mix0: mix-0 { }; - mix1: mix-1 { }; - }; - - rcar_sound,ctu { - ctu00: ctu-0 { }; - ctu01: ctu-1 { }; - ctu02: ctu-2 { }; - ctu03: ctu-3 { }; - ctu10: ctu-4 { }; - ctu11: ctu-5 { }; - ctu12: ctu-6 { }; - ctu13: ctu-7 { }; - }; - - rcar_sound,src { - src-0 { - status = "disabled"; - }; - src1: src-1 { - interrupts = ; - dmas = <&audma0 0x87>, <&audma0 0x9c>; - dma-names = "rx", "tx"; - }; - src2: src-2 { - interrupts = ; - dmas = <&audma0 0x89>, <&audma0 0x9e>; - dma-names = "rx", "tx"; - }; - src3: src-3 { - interrupts = ; - dmas = <&audma0 0x8b>, <&audma0 0xa0>; - dma-names = "rx", "tx"; - }; - src4: src-4 { - interrupts = ; - dmas = <&audma0 0x8d>, <&audma0 0xb0>; - dma-names = "rx", "tx"; - }; - src5: src-5 { - interrupts = ; - dmas = <&audma0 0x8f>, <&audma0 0xb2>; - dma-names = "rx", "tx"; - }; - src6: src-6 { - interrupts = ; - dmas = <&audma0 0x91>, <&audma0 0xb4>; - dma-names = "rx", "tx"; - }; - }; - - rcar_sound,ssi { - ssi0: ssi-0 { - interrupts = ; - dmas = <&audma0 0x01>, <&audma0 0x02>, - <&audma0 0x15>, <&audma0 0x16>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi1: ssi-1 { - interrupts = ; - dmas = <&audma0 0x03>, <&audma0 0x04>, - <&audma0 0x49>, <&audma0 0x4a>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi2: ssi-2 { - interrupts = ; - dmas = <&audma0 0x05>, <&audma0 0x06>, - <&audma0 0x63>, <&audma0 0x64>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi3: ssi-3 { - interrupts = ; - dmas = <&audma0 0x07>, <&audma0 0x08>, - <&audma0 0x6f>, <&audma0 0x70>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi4: ssi-4 { - interrupts = ; - dmas = <&audma0 0x09>, <&audma0 0x0a>, - <&audma0 0x71>, <&audma0 0x72>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi5: ssi-5 { - interrupts = ; - dmas = <&audma0 0x0b>, <&audma0 0x0c>, - <&audma0 0x73>, <&audma0 0x74>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi6: ssi-6 { - interrupts = ; - dmas = <&audma0 0x0d>, <&audma0 0x0e>, - <&audma0 0x75>, <&audma0 0x76>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi7: ssi-7 { - interrupts = ; - dmas = <&audma0 0x0f>, <&audma0 0x10>, - <&audma0 0x79>, <&audma0 0x7a>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi8: ssi-8 { - interrupts = ; - dmas = <&audma0 0x11>, <&audma0 0x12>, - <&audma0 0x7b>, <&audma0 0x7c>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi9: ssi-9 { - interrupts = ; - dmas = <&audma0 0x13>, <&audma0 0x14>, - <&audma0 0x7d>, <&audma0 0x7e>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - }; - }; - - audma0: dma-controller@ec700000 { - compatible = "renesas,dmac-r8a7745", - "renesas,rcar-dmac"; - reg = <0 0xec700000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12"; - clocks = <&cpg CPG_MOD 502>; - clock-names = "fck"; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 502>; - #dma-cells = <1>; - dma-channels = <13>; - }; - - pci0: pci@ee090000 { - compatible = "renesas,pci-r8a7745", - "renesas,pci-rcar-gen2"; - device_type = "pci"; - reg = <0 0xee090000 0 0xc00>, - <0 0xee080000 0 0x1100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 703>; - status = "disabled"; - - bus-range = <0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>; - interrupt-map-mask = <0xf800 0 0 0x7>; - interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, - <0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, - <0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; - - usb@1,0 { - reg = <0x800 0 0 0 0>; - phys = <&usb0 0>; - phy-names = "usb"; - }; - - usb@2,0 { - reg = <0x1000 0 0 0 0>; - phys = <&usb0 0>; - phy-names = "usb"; - }; - }; - - pci1: pci@ee0d0000 { - compatible = "renesas,pci-r8a7745", - "renesas,pci-rcar-gen2"; - device_type = "pci"; - reg = <0 0xee0d0000 0 0xc00>, - <0 0xee0c0000 0 0x1100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 703>; - status = "disabled"; - - bus-range = <1 1>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>; - interrupt-map-mask = <0xf800 0 0 0x7>; - interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, - <0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, - <0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; - - usb@1,0 { - reg = <0x10800 0 0 0 0>; - phys = <&usb2 0>; - phy-names = "usb"; - }; - - usb@2,0 { - reg = <0x11000 0 0 0 0>; - phys = <&usb2 0>; - phy-names = "usb"; - }; - }; - - sdhi0: sd@ee100000 { - compatible = "renesas,sdhi-r8a7745", - "renesas,rcar-gen2-sdhi"; - reg = <0 0xee100000 0 0x328>; - interrupts = ; - clocks = <&cpg CPG_MOD 314>; - dmas = <&dmac0 0xcd>, <&dmac0 0xce>, - <&dmac1 0xcd>, <&dmac1 0xce>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <195000000>; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 314>; - status = "disabled"; - }; - - sdhi1: sd@ee140000 { - compatible = "renesas,sdhi-r8a7745", - "renesas,rcar-gen2-sdhi"; - reg = <0 0xee140000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 312>; - dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, - <&dmac1 0xc1>, <&dmac1 0xc2>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <97500000>; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 312>; - status = "disabled"; - }; - - sdhi2: sd@ee160000 { - compatible = "renesas,sdhi-r8a7745", - "renesas,rcar-gen2-sdhi"; - reg = <0 0xee160000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 311>; - dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, - <&dmac1 0xd3>, <&dmac1 0xd4>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <97500000>; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 311>; - status = "disabled"; - }; - - mmcif0: mmc@ee200000 { - compatible = "renesas,mmcif-r8a7745", - "renesas,sh-mmcif"; - reg = <0 0xee200000 0 0x80>; - interrupts = ; - clocks = <&cpg CPG_MOD 315>; - dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, - <&dmac1 0xd1>, <&dmac1 0xd2>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 315>; - reg-io-width = <4>; - max-frequency = <97500000>; - status = "disabled"; - }; - - ether: ethernet@ee700000 { - compatible = "renesas,ether-r8a7745", - "renesas,rcar-gen2-ether"; - reg = <0 0xee700000 0 0x400>; - interrupts = ; - clocks = <&cpg CPG_MOD 813>; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 813>; - phy-mode = "rmii"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - gic: interrupt-controller@f1001000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>, - <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 408>; - clock-names = "clk"; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 408>; - }; - - vsp@fe928000 { - compatible = "renesas,vsp1"; - reg = <0 0xfe928000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 131>; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 131>; - }; - - vsp@fe930000 { - compatible = "renesas,vsp1"; - reg = <0 0xfe930000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 128>; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 128>; - }; - - du: display@feb00000 { - compatible = "renesas,du-r8a7745"; - reg = <0 0xfeb00000 0 0x40000>; - reg-names = "du"; - interrupts = , - ; - clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; - clock-names = "du.0", "du.1"; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - du_out_rgb0: endpoint { - }; - }; - port@1 { - reg = <1>; - du_out_rgb1: endpoint { - }; - }; - }; - }; - - prr: chipid@ff000044 { - compatible = "renesas,prr"; - reg = <0 0xff000044 0 4>; - }; - - cmt0: timer@ffca0000 { - compatible = "renesas,r8a7745-cmt0", - "renesas,rcar-gen2-cmt0"; - reg = <0 0xffca0000 0 0x1004>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 124>; - clock-names = "fck"; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 124>; - status = "disabled"; - }; - - cmt1: timer@e6130000 { - compatible = "renesas,r8a7745-cmt1", - "renesas,rcar-gen2-cmt1"; - reg = <0 0xe6130000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 329>; - clock-names = "fck"; - power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; - resets = <&cpg 329>; - status = "disabled"; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; - }; - - /* External USB clock - can be overridden by the board */ - usb_extal_clk: usb_extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <48000000>; - }; -}; diff --git a/sys/gnu/dts/arm/r8a77470-iwg23s-sbc.dts b/sys/gnu/dts/arm/r8a77470-iwg23s-sbc.dts deleted file mode 100644 index 8ac61b50aec..00000000000 --- a/sys/gnu/dts/arm/r8a77470-iwg23s-sbc.dts +++ /dev/null @@ -1,319 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the iWave-RZ/G1C single board computer - * - * Copyright (C) 2018 Renesas Electronics Corp. - */ - -/dts-v1/; -#include -#include "r8a77470.dtsi" -/ { - model = "iWave iW-RainboW-G23S single board computer based on RZ/G1C"; - compatible = "iwave,g23s", "renesas,r8a77470"; - - aliases { - ethernet0 = &avb; - serial1 = &scif1; - }; - - chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; - stdout-path = "serial1:115200n8"; - }; - - hdmi-out { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con: endpoint { - remote-endpoint = <&bridge_out>; - }; - }; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0 0x40000000 0 0x20000000>; - }; - - reg_1p8v: reg-1p8v { - compatible = "regulator-fixed"; - regulator-name = "fixed-1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_3p3v: reg-3p3v { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - vccq_sdhi2: regulator-vccq-sdhi2 { - compatible = "regulator-gpio"; - - regulator-name = "SDHI2 VccQ"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>; - gpios-states = <1>; - states = <3300000 1>, <1800000 0>; - }; -}; - -&avb { - pinctrl-0 = <&avb_pins>; - pinctrl-names = "default"; - - phy-handle = <&phy3>; - phy-mode = "gmii"; - renesas,no-ether-link; - status = "okay"; - - phy3: ethernet-phy@3 { - reg = <3>; - interrupt-parent = <&gpio5>; - interrupts = <16 IRQ_TYPE_LEVEL_LOW>; - micrel,led-mode = <1>; - }; -}; - -&cmt0 { - status = "okay"; -}; - -&du { - pinctrl-0 = <&du0_pins>; - pinctrl-names = "default"; - - status = "okay"; - - ports { - port@0 { - endpoint { - remote-endpoint = <&bridge_in>; - }; - }; - }; -}; - -&ehci1 { - status = "okay"; -}; - -&extal_clk { - clock-frequency = <20000000>; -}; - -&gpio2 { - interrupt-fixup { - gpio-hog; - gpios = <29 GPIO_ACTIVE_HIGH>; - line-name = "hdmi-hpd-int"; - input; - }; -}; - -&hsusb0 { - status = "okay"; -}; - -&i2c3 { - pinctrl-0 = <&i2c3_pins>; - pinctrl-names = "default"; - - status = "okay"; - clock-frequency = <400000>; - - rtc@51 { - compatible = "nxp,pcf85263"; - reg = <0x51>; - }; -}; - -&i2c4 { - pinctrl-0 = <&i2c4_pins>; - pinctrl-names = "default"; - - status = "okay"; - clock-frequency = <100000>; - - hdmi@39 { - compatible = "sil,sii9022"; - reg = <0x39>; - interrupt-parent = <&gpio2>; - interrupts = <29 IRQ_TYPE_LEVEL_LOW>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - bridge_in: endpoint { - remote-endpoint = <&du_out_rgb0>; - }; - }; - - port@1 { - reg = <1>; - bridge_out: endpoint { - remote-endpoint = <&hdmi_con>; - }; - }; - }; - }; -}; - -&ohci1 { - status = "okay"; -}; - -&pfc { - avb_pins: avb { - groups = "avb_mdio", "avb_gmii_tx_rx"; - function = "avb"; - }; - - du0_pins: du0 { - groups = "du0_rgb888", "du0_sync", "du0_disp", "du0_clk0_out"; - function = "du0"; - }; - - i2c4_pins: i2c4 { - groups = "i2c4_e"; - function = "i2c4"; - }; - - i2c3_pins: i2c3 { - groups = "i2c3_c"; - function = "i2c3"; - }; - - mmc_pins_uhs: mmc_uhs { - groups = "mmc_data8", "mmc_ctrl"; - function = "mmc"; - power-source = <1800>; - }; - - qspi0_pins: qspi0 { - groups = "qspi0_ctrl", "qspi0_data2"; - function = "qspi0"; - }; - - scif1_pins: scif1 { - groups = "scif1_data_b"; - function = "scif1"; - }; - - sdhi2_pins: sd2 { - groups = "sdhi2_data4", "sdhi2_ctrl"; - function = "sdhi2"; - power-source = <3300>; - }; - - sdhi2_pins_uhs: sd2_uhs { - groups = "sdhi2_data4", "sdhi2_ctrl"; - function = "sdhi2"; - power-source = <1800>; - }; - - usb0_pins: usb0 { - groups = "usb0"; - function = "usb0"; - }; - - usb1_pins: usb1 { - groups = "usb1"; - function = "usb1"; - }; -}; - -&qspi0 { - pinctrl-0 = <&qspi0_pins>; - pinctrl-names = "default"; - - status = "okay"; - - /* WARNING - This device contains the bootloader. Handle with care. */ - flash: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "issi,is25lp016d", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <133000000>; - spi-tx-bus-width = <1>; - spi-rx-bus-width = <1>; - m25p,fast-read; - spi-cpol; - spi-cpha; - }; -}; - -&rwdt { - timeout-sec = <60>; - status = "okay"; -}; - -&scif1 { - pinctrl-0 = <&scif1_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&sdhi1 { - pinctrl-0 = <&mmc_pins_uhs>; - pinctrl-names = "state_uhs"; - - vmmc-supply = <®_3p3v>; - vqmmc-supply = <®_1p8v>; - bus-width = <8>; - mmc-hs200-1_8v; - non-removable; - fixed-emmc-driver-type = <1>; - status = "okay"; -}; - -&sdhi2 { - pinctrl-0 = <&sdhi2_pins>; - pinctrl-1 = <&sdhi2_pins_uhs>; - pinctrl-names = "default", "state_uhs"; - - vmmc-supply = <®_3p3v>; - vqmmc-supply = <&vccq_sdhi2>; - bus-width = <4>; - cd-gpios = <&gpio4 20 GPIO_ACTIVE_LOW>; - sd-uhs-sdr50; - status = "okay"; -}; - -&usb2_phy0 { - status = "okay"; -}; - -&usb2_phy1 { - status = "okay"; -}; - -&usbphy0 { - pinctrl-0 = <&usb0_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&usbphy1 { - pinctrl-0 = <&usb1_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/r8a77470.dtsi b/sys/gnu/dts/arm/r8a77470.dtsi deleted file mode 100644 index 6efcef1670e..00000000000 --- a/sys/gnu/dts/arm/r8a77470.dtsi +++ /dev/null @@ -1,1024 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the r8a77470 SoC - * - * Copyright (C) 2018 Renesas Electronics Corp. - */ - -#include -#include -#include -#include -/ { - compatible = "renesas,r8a77470"; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "renesas,apmu"; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0>; - clock-frequency = <1000000000>; - clocks = <&cpg CPG_CORE R8A77470_CLK_Z2>; - power-domains = <&sysc R8A77470_PD_CA7_CPU0>; - next-level-cache = <&L2_CA7>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <1>; - clock-frequency = <1000000000>; - clocks = <&cpg CPG_CORE R8A77470_CLK_Z2>; - power-domains = <&sysc R8A77470_PD_CA7_CPU1>; - next-level-cache = <&L2_CA7>; - }; - - L2_CA7: cache-controller-0 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - power-domains = <&sysc R8A77470_PD_CA7_SCU>; - }; - }; - - /* External root clock */ - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts-extended = <&gic GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&cpu0>, <&cpu1>; - }; - - /* External SCIF clock */ - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - soc { - compatible = "simple-bus"; - interrupt-parent = <&gic>; - - #address-cells = <2>; - #size-cells = <2>; - ranges; - - rwdt: watchdog@e6020000 { - compatible = "renesas,r8a77470-wdt", - "renesas,rcar-gen2-wdt"; - reg = <0 0xe6020000 0 0x0c>; - clocks = <&cpg CPG_MOD 402>; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 402>; - status = "disabled"; - }; - - gpio0: gpio@e6050000 { - compatible = "renesas,gpio-r8a77470", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6050000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 0 23>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 912>; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 912>; - }; - - gpio1: gpio@e6051000 { - compatible = "renesas,gpio-r8a77470", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6051000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 32 23>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 911>; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 911>; - }; - - gpio2: gpio@e6052000 { - compatible = "renesas,gpio-r8a77470", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6052000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 64 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 910>; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 910>; - }; - - gpio3: gpio@e6053000 { - compatible = "renesas,gpio-r8a77470", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6053000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 96 30>; - gpio-reserved-ranges = <17 10>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 909>; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 909>; - }; - - gpio4: gpio@e6054000 { - compatible = "renesas,gpio-r8a77470", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6054000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 128 26>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 908>; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 908>; - }; - - gpio5: gpio@e6055000 { - compatible = "renesas,gpio-r8a77470", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6055000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 160 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 907>; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 907>; - }; - - pfc: pin-controller@e6060000 { - compatible = "renesas,pfc-r8a77470"; - reg = <0 0xe6060000 0 0x118>; - }; - - cpg: clock-controller@e6150000 { - compatible = "renesas,r8a77470-cpg-mssr"; - reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk>, <&usb_extal_clk>; - clock-names = "extal", "usb_extal"; - #clock-cells = <2>; - #power-domain-cells = <0>; - #reset-cells = <1>; - }; - - apmu@e6151000 { - compatible = "renesas,r8a77470-apmu", "renesas,apmu"; - reg = <0 0xe6151000 0 0x188>; - cpus = <&cpu0 &cpu1>; - }; - - rst: reset-controller@e6160000 { - compatible = "renesas,r8a77470-rst"; - reg = <0 0xe6160000 0 0x100>; - }; - - sysc: system-controller@e6180000 { - compatible = "renesas,r8a77470-sysc"; - reg = <0 0xe6180000 0 0x200>; - #power-domain-cells = <1>; - }; - - irqc: interrupt-controller@e61c0000 { - compatible = "renesas,irqc-r8a77470", "renesas,irqc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0 0xe61c0000 0 0x200>; - interrupts = , - , - , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 407>; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 407>; - }; - - icram0: sram@e63a0000 { - compatible = "mmio-sram"; - reg = <0 0xe63a0000 0 0x12000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0xe63a0000 0x12000>; - }; - - icram1: sram@e63c0000 { - compatible = "mmio-sram"; - reg = <0 0xe63c0000 0 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0xe63c0000 0x1000>; - - smp-sram@0 { - compatible = "renesas,smp-sram"; - reg = <0 0x100>; - }; - }; - - icram2: sram@e6300000 { - compatible = "mmio-sram"; - reg = <0 0xe6300000 0 0x20000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0xe6300000 0x20000>; - }; - - i2c0: i2c@e6508000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a77470", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6508000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 931>; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 931>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c1: i2c@e6518000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a77470", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6518000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 930>; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 930>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c2: i2c@e6530000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a77470", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6530000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 929>; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 929>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c3: i2c@e6540000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a77470", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6540000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 928>; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 928>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c4: i2c@e6520000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a77470", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6520000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 927>; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 927>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - hsusb0: hsusb@e6590000 { - compatible = "renesas,usbhs-r8a77470", - "renesas,rcar-gen2-usbhs"; - reg = <0 0xe6590000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 704>; - dmas = <&usb_dmac00 0>, <&usb_dmac00 1>, - <&usb_dmac10 0>, <&usb_dmac10 1>; - dma-names = "ch0", "ch1", "ch2", "ch3"; - renesas,buswait = <4>; - phys = <&usb0 1>; - phy-names = "usb"; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 704>; - status = "disabled"; - }; - - usbphy0: usb-phy@e6590100 { - compatible = "renesas,usb-phy-r8a77470", - "renesas,rcar-gen2-usb-phy"; - reg = <0 0xe6590100 0 0x100>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cpg CPG_MOD 704>; - clock-names = "usbhs"; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 704>; - status = "disabled"; - - usb0: usb-channel@0 { - reg = <0>; - #phy-cells = <1>; - }; - }; - - hsusb1: hsusb@e6598000 { - compatible = "renesas,usbhs-r8a77470", - "renesas,rcar-gen2-usbhs"; - reg = <0 0xe6598000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 706>; - dmas = <&usb_dmac01 0>, <&usb_dmac01 1>, - <&usb_dmac11 0>, <&usb_dmac11 1>; - dma-names = "ch0", "ch1", "ch2", "ch3"; - renesas,buswait = <4>; - /* We need to turn on usbphy0 to make usbphy1 to work */ - phys = <&usb1 1>; - phy-names = "usb"; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 706>; - status = "disabled"; - }; - - usbphy1: usb-phy@e6598100 { - compatible = "renesas,usb-phy-r8a77470", - "renesas,rcar-gen2-usb-phy"; - reg = <0 0xe6598100 0 0x100>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cpg CPG_MOD 706>; - clock-names = "usbhs"; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 706>; - status = "disabled"; - - usb1: usb-channel@0 { - reg = <0>; - #phy-cells = <1>; - }; - }; - - usb_dmac00: dma-controller@e65a0000 { - compatible = "renesas,r8a77470-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65a0000 0 0x100>; - interrupts = , - ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 330>; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 330>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - usb_dmac10: dma-controller@e65b0000 { - compatible = "renesas,r8a77470-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65b0000 0 0x100>; - interrupts = , - ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 331>; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 331>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - usb_dmac01: dma-controller@e65a8000 { - compatible = "renesas,r8a77470-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65a8000 0 0x100>; - interrupts = , - ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 326>; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 326>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - usb_dmac11: dma-controller@e65b8000 { - compatible = "renesas,r8a77470-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65b8000 0 0x100>; - interrupts = , - ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 327>; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 327>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - dmac0: dma-controller@e6700000 { - compatible = "renesas,dmac-r8a77470", - "renesas,rcar-dmac"; - reg = <0 0xe6700000 0 0x20000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14"; - clocks = <&cpg CPG_MOD 219>; - clock-names = "fck"; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 219>; - #dma-cells = <1>; - dma-channels = <15>; - }; - - dmac1: dma-controller@e6720000 { - compatible = "renesas,dmac-r8a77470", - "renesas,rcar-dmac"; - reg = <0 0xe6720000 0 0x20000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14"; - clocks = <&cpg CPG_MOD 218>; - clock-names = "fck"; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 218>; - #dma-cells = <1>; - dma-channels = <15>; - }; - - avb: ethernet@e6800000 { - compatible = "renesas,etheravb-r8a77470", - "renesas,etheravb-rcar-gen2"; - reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; - interrupts = ; - clocks = <&cpg CPG_MOD 812>; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 812>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - qspi0: spi@e6b10000 { - compatible = "renesas,qspi-r8a77470", "renesas,qspi"; - reg = <0 0xe6b10000 0 0x2c>; - interrupts = ; - clocks = <&cpg CPG_MOD 918>; - dmas = <&dmac0 0x17>, <&dmac0 0x18>, - <&dmac1 0x17>, <&dmac1 0x18>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - resets = <&cpg 918>; - status = "disabled"; - }; - - qspi1: spi@ee200000 { - compatible = "renesas,qspi-r8a77470", "renesas,qspi"; - reg = <0 0xee200000 0 0x2c>; - interrupts = ; - clocks = <&cpg CPG_MOD 917>; - dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, - <&dmac1 0xd1>, <&dmac1 0xd2>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - resets = <&cpg 917>; - status = "disabled"; - }; - - scif0: serial@e6e60000 { - compatible = "renesas,scif-r8a77470", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6e60000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 721>, - <&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x29>, <&dmac0 0x2a>, - <&dmac1 0x29>, <&dmac1 0x2a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 721>; - status = "disabled"; - }; - - scif1: serial@e6e68000 { - compatible = "renesas,scif-r8a77470", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6e68000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 720>, - <&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, - <&dmac1 0x2d>, <&dmac1 0x2e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 720>; - status = "disabled"; - }; - - scif2: serial@e6e58000 { - compatible = "renesas,scif-r8a77470", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6e58000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 719>, - <&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, - <&dmac1 0x2b>, <&dmac1 0x2c>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 719>; - status = "disabled"; - }; - - scif3: serial@e6ea8000 { - compatible = "renesas,scif-r8a77470", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6ea8000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 718>, - <&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2f>, <&dmac0 0x30>, - <&dmac1 0x2f>, <&dmac1 0x30>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 718>; - status = "disabled"; - }; - - scif4: serial@e6ee0000 { - compatible = "renesas,scif-r8a77470", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6ee0000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 715>, - <&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0xfb>, <&dmac0 0xfc>, - <&dmac1 0xfb>, <&dmac1 0xfc>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 715>; - status = "disabled"; - }; - - scif5: serial@e6ee8000 { - compatible = "renesas,scif-r8a77470", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6ee8000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 714>, - <&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0xfd>, <&dmac0 0xfe>, - <&dmac1 0xfd>, <&dmac1 0xfe>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 714>; - status = "disabled"; - }; - - hscif0: serial@e62c0000 { - compatible = "renesas,hscif-r8a77470", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62c0000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 717>, - <&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x39>, <&dmac0 0x3a>, - <&dmac1 0x39>, <&dmac1 0x3a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 717>; - status = "disabled"; - }; - - hscif1: serial@e62c8000 { - compatible = "renesas,hscif-r8a77470", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62c8000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 716>, - <&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, - <&dmac1 0x4d>, <&dmac1 0x4e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 716>; - status = "disabled"; - }; - - hscif2: serial@e62d0000 { - compatible = "renesas,hscif-r8a77470", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62d0000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 713>, - <&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x3b>, <&dmac0 0x3c>, - <&dmac1 0x3b>, <&dmac1 0x3c>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 713>; - status = "disabled"; - }; - - pwm0: pwm@e6e30000 { - compatible = "renesas,pwm-r8a77470", "renesas,pwm-rcar"; - reg = <0 0xe6e30000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm1: pwm@e6e31000 { - compatible = "renesas,pwm-r8a77470", "renesas,pwm-rcar"; - reg = <0 0xe6e31000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm2: pwm@e6e32000 { - compatible = "renesas,pwm-r8a77470", "renesas,pwm-rcar"; - reg = <0 0xe6e32000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm3: pwm@e6e33000 { - compatible = "renesas,pwm-r8a77470", "renesas,pwm-rcar"; - reg = <0 0xe6e33000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm4: pwm@e6e34000 { - compatible = "renesas,pwm-r8a77470", "renesas,pwm-rcar"; - reg = <0 0xe6e34000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm5: pwm@e6e35000 { - compatible = "renesas,pwm-r8a77470", "renesas,pwm-rcar"; - reg = <0 0xe6e35000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm6: pwm@e6e36000 { - compatible = "renesas,pwm-r8a77470", "renesas,pwm-rcar"; - reg = <0 0xe6e36000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - vin0: video@e6ef0000 { - compatible = "renesas,vin-r8a77470", - "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef0000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 811>; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 811>; - status = "disabled"; - }; - - vin1: video@e6ef1000 { - compatible = "renesas,vin-r8a77470", - "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef1000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 810>; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 810>; - status = "disabled"; - }; - - ohci0: usb@ee080000 { - compatible = "generic-ohci"; - reg = <0 0xee080000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>; - phys = <&usb0 0>, <&usb2_phy0>; - phy-names = "usb"; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 703>; - status = "disabled"; - }; - - ehci0: usb@ee080100 { - compatible = "generic-ehci"; - reg = <0 0xee080100 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>; - phys = <&usb0 0>, <&usb2_phy0>; - phy-names = "usb"; - companion = <&ohci0>; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 703>; - status = "disabled"; - }; - - usb2_phy0: usb-phy@ee080200 { - compatible = "renesas,usb2-phy-r8a77470"; - reg = <0 0xee080200 0 0x700>; - clocks = <&cpg CPG_MOD 703>; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 703>; - #phy-cells = <0>; - status = "disabled"; - }; - - ohci1: usb@ee0c0000 { - compatible = "generic-ohci"; - reg = <0 0xee0c0000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 705>; - phys = <&usb0 1>, <&usb2_phy1>, <&usb1 0>; - phy-names = "usb"; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 705>; - status = "disabled"; - }; - - ehci1: usb@ee0c0100 { - compatible = "generic-ehci"; - reg = <0 0xee0c0100 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 705>; - phys = <&usb0 1>, <&usb2_phy1>, <&usb1 0>; - phy-names = "usb"; - companion = <&ohci1>; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 705>; - status = "disabled"; - }; - - usb2_phy1: usb-phy@ee0c0200 { - compatible = "renesas,usb2-phy-r8a77470"; - reg = <0 0xee0c0200 0 0x700>; - clocks = <&cpg CPG_MOD 705>; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 705>; - #phy-cells = <0>; - status = "disabled"; - }; - - sdhi0: sd@ee100000 { - compatible = "renesas,sdhi-r8a77470", - "renesas,rcar-gen2-sdhi"; - reg = <0 0xee100000 0 0x328>; - interrupts = ; - clocks = <&cpg CPG_MOD 314>; - dmas = <&dmac0 0xcd>, <&dmac0 0xce>, - <&dmac1 0xcd>, <&dmac1 0xce>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <156000000>; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 314>; - status = "disabled"; - }; - - sdhi1: sd@ee300000 { - compatible = "renesas,sdhi-mmc-r8a77470"; - reg = <0 0xee300000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 313>; - max-frequency = <156000000>; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 313>; - status = "disabled"; - }; - - sdhi2: sd@ee160000 { - compatible = "renesas,sdhi-r8a77470", - "renesas,rcar-gen2-sdhi"; - reg = <0 0xee160000 0 0x328>; - interrupts = ; - clocks = <&cpg CPG_MOD 312>; - dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, - <&dmac1 0xd3>, <&dmac1 0xd4>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <78000000>; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 312>; - status = "disabled"; - }; - - gic: interrupt-controller@f1001000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>, - <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 408>; - clock-names = "clk"; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 408>; - }; - - du: display@feb00000 { - compatible = "renesas,du-r8a77470"; - reg = <0 0xfeb00000 0 0x40000>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>; - clock-names = "du.0", "du.1"; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - du_out_rgb0: endpoint { - }; - }; - port@1 { - reg = <1>; - du_out_rgb1: endpoint { - }; - }; - port@2 { - reg = <2>; - du_out_lvds0: endpoint { - }; - }; - }; - }; - - prr: chipid@ff000044 { - compatible = "renesas,prr"; - reg = <0 0xff000044 0 4>; - }; - - cmt0: timer@ffca0000 { - compatible = "renesas,r8a77470-cmt0", - "renesas,rcar-gen2-cmt0"; - reg = <0 0xffca0000 0 0x1004>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 124>; - clock-names = "fck"; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 124>; - status = "disabled"; - }; - - cmt1: timer@e6130000 { - compatible = "renesas,r8a77470-cmt1", - "renesas,rcar-gen2-cmt1"; - reg = <0 0xe6130000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 329>; - clock-names = "fck"; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 329>; - status = "disabled"; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; - }; - - /* External USB clock - can be overridden by the board */ - usb_extal_clk: usb_extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <48000000>; - }; -}; diff --git a/sys/gnu/dts/arm/r8a7778-bockw.dts b/sys/gnu/dts/arm/r8a7778-bockw.dts deleted file mode 100644 index 6c7b07c4b9d..00000000000 --- a/sys/gnu/dts/arm/r8a7778-bockw.dts +++ /dev/null @@ -1,229 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Reference Device Tree Source for the R-Car M1A (R8A77781) Bock-W board - * - * Copyright (C) 2013 Renesas Solutions Corp. - * Copyright (C) 2013 Kuninori Morimoto - * - * based on r8a7779 - * - * Copyright (C) 2013 Renesas Solutions Corp. - * Copyright (C) 2013 Simon Horman - */ - -/dts-v1/; -#include "r8a7778.dtsi" -#include -#include - -/ { - model = "bockw"; - compatible = "renesas,bockw", "renesas,r8a7778"; - - aliases { - serial0 = &scif0; - }; - - chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; - stdout-path = "serial0:115200n8"; - }; - - memory@60000000 { - device_type = "memory"; - reg = <0x60000000 0x10000000>; - }; - - fixedregulator3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - sound { - compatible = "simple-audio-card"; - - simple-audio-card,format = "left_j"; - simple-audio-card,bitclock-master = <&sndcodec>; - simple-audio-card,frame-master = <&sndcodec>; - - sndcpu: simple-audio-card,cpu { - sound-dai = <&rcar_sound>; - }; - - sndcodec: simple-audio-card,codec { - sound-dai = <&ak4643>; - system-clock-frequency = <11289600>; - }; - }; -}; - -&bsc { - ethernet@18300000 { - compatible = "smsc,lan9220", "smsc,lan9115"; - reg = <0x18300000 0x1000>; - - phy-mode = "mii"; - interrupt-parent = <&irqpin>; - interrupts = <0 IRQ_TYPE_EDGE_FALLING>; - reg-io-width = <4>; - vddvario-supply = <&fixedregulator3v3>; - vdd33a-supply = <&fixedregulator3v3>; - }; -}; - -&extal_clk { - clock-frequency = <33333333>; -}; - -&i2c0 { - status = "okay"; - - ak4643: codec@12 { - compatible = "asahi-kasei,ak4643"; - #sound-dai-cells = <0>; - reg = <0x12>; - }; - - camera@41 { - compatible = "oki,ml86v7667"; - reg = <0x41>; - }; - - camera@43 { - compatible = "oki,ml86v7667"; - reg = <0x43>; - }; - - rx8581: rtc@51 { - compatible = "epson,rx8581"; - reg = <0x51>; - }; -}; - -&mmcif { - pinctrl-0 = <&mmc_pins>; - pinctrl-names = "default"; - - vmmc-supply = <&fixedregulator3v3>; - bus-width = <8>; - broken-cd; - status = "okay"; -}; - -&irqpin { - status = "okay"; -}; - -&tmu0 { - status = "okay"; -}; - -&pfc { - pinctrl-0 = <&scif_clk_pins>; - pinctrl-names = "default"; - - scif0_pins: scif0 { - groups = "scif0_data_a", "scif0_ctrl"; - function = "scif0"; - }; - - scif_clk_pins: scif_clk { - groups = "scif_clk"; - function = "scif_clk"; - }; - - mmc_pins: mmc { - groups = "mmc_data8", "mmc_ctrl"; - function = "mmc"; - }; - - sdhi0_pins: sd0 { - groups = "sdhi0_data4", "sdhi0_ctrl"; - function = "sdhi0"; - }; - sdhi0_pup_pins: sd0_pup { - groups = "sdhi0_cd", "sdhi0_wp"; - function = "sdhi0"; - bias-pull-up; - }; - - hspi0_pins: hspi0 { - groups = "hspi0_a"; - function = "hspi0"; - }; - - usb0_pins: usb0 { - groups = "usb0"; - function = "usb0"; - }; - - usb1_pins: usb1 { - groups = "usb1"; - function = "usb1"; - }; - - vin0_pins: vin0 { - groups = "vin0_data8", "vin0_clk"; - function = "vin0"; - }; - - vin1_pins: vin1 { - groups = "vin1_data8", "vin1_clk"; - function = "vin1"; - }; -}; - -&rcar_sound { - /* Single DAI */ - #sound-dai-cells = <0>; -}; - -&sdhi0 { - pinctrl-0 = <&sdhi0_pins>, <&sdhi0_pup_pins>; - pinctrl-names = "default"; - - vmmc-supply = <&fixedregulator3v3>; - bus-width = <4>; - status = "okay"; - wp-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>; -}; - -&hspi0 { - pinctrl-0 = <&hspi0_pins>; - pinctrl-names = "default"; - status = "okay"; - - flash: flash@0 { - compatible = "spansion,s25fl008k", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <104000000>; - m25p,fast-read; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "data(spi)"; - reg = <0x00000000 0x00100000>; - }; - }; - }; -}; - -&scif0 { - pinctrl-0 = <&scif0_pins>; - pinctrl-names = "default"; - - uart-has-rtscts; - status = "okay"; -}; - -&scif_clk { - clock-frequency = <14745600>; -}; diff --git a/sys/gnu/dts/arm/r8a7778.dtsi b/sys/gnu/dts/arm/r8a7778.dtsi deleted file mode 100644 index 593c6df9030..00000000000 --- a/sys/gnu/dts/arm/r8a7778.dtsi +++ /dev/null @@ -1,667 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the R-Car M1A (R8A77781) SoC - * - * Copyright (C) 2013 Renesas Solutions Corp. - * Copyright (C) 2013 Kuninori Morimoto - * - * based on r8a7779 - * - * Copyright (C) 2013 Renesas Solutions Corp. - * Copyright (C) 2013 Simon Horman - */ - -#include -#include -#include - -/ { - compatible = "renesas,r8a7778"; - interrupt-parent = <&gic>; - #address-cells = <1>; - #size-cells = <1>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - clock-frequency = <800000000>; - clocks = <&z_clk>; - }; - }; - - aliases { - spi0 = &hspi0; - spi1 = &hspi1; - spi2 = &hspi2; - }; - - bsc: bus@1c000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x1c000000>; - }; - - ether: ethernet@fde00000 { - compatible = "renesas,ether-r8a7778", - "renesas,rcar-gen1-ether"; - reg = <0xfde00000 0x400>; - interrupts = ; - clocks = <&mstp1_clks R8A7778_CLK_ETHER>; - power-domains = <&cpg_clocks>; - phy-mode = "rmii"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - gic: interrupt-controller@fe438000 { - compatible = "arm,pl390"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0xfe438000 0x1000>, - <0xfe430000 0x100>; - }; - - /* irqpin: IRQ0 - IRQ3 */ - irqpin: interrupt-controller@fe78001c { - compatible = "renesas,intc-irqpin-r8a7778", "renesas,intc-irqpin"; - #interrupt-cells = <2>; - interrupt-controller; - status = "disabled"; /* default off */ - reg = <0xfe78001c 4>, - <0xfe780010 4>, - <0xfe780024 4>, - <0xfe780044 4>, - <0xfe780064 4>; - interrupts = , - , - , - ; - sense-bitfield-width = <2>; - }; - - gpio0: gpio@ffc40000 { - compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio"; - reg = <0xffc40000 0x2c>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 0 32>; - #interrupt-cells = <2>; - interrupt-controller; - }; - - gpio1: gpio@ffc41000 { - compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio"; - reg = <0xffc41000 0x2c>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 32 32>; - #interrupt-cells = <2>; - interrupt-controller; - }; - - gpio2: gpio@ffc42000 { - compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio"; - reg = <0xffc42000 0x2c>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 64 32>; - #interrupt-cells = <2>; - interrupt-controller; - }; - - gpio3: gpio@ffc43000 { - compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio"; - reg = <0xffc43000 0x2c>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 96 32>; - #interrupt-cells = <2>; - interrupt-controller; - }; - - gpio4: gpio@ffc44000 { - compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio"; - reg = <0xffc44000 0x2c>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 128 27>; - #interrupt-cells = <2>; - interrupt-controller; - }; - - pfc: pin-controller@fffc0000 { - compatible = "renesas,pfc-r8a7778"; - reg = <0xfffc0000 0x118>; - }; - - i2c0: i2c@ffc70000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7778", "renesas,rcar-gen1-i2c"; - reg = <0xffc70000 0x1000>; - interrupts = ; - clocks = <&mstp0_clks R8A7778_CLK_I2C0>; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - i2c1: i2c@ffc71000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7778", "renesas,rcar-gen1-i2c"; - reg = <0xffc71000 0x1000>; - interrupts = ; - clocks = <&mstp0_clks R8A7778_CLK_I2C1>; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - i2c2: i2c@ffc72000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7778", "renesas,rcar-gen1-i2c"; - reg = <0xffc72000 0x1000>; - interrupts = ; - clocks = <&mstp0_clks R8A7778_CLK_I2C2>; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - i2c3: i2c@ffc73000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7778", "renesas,rcar-gen1-i2c"; - reg = <0xffc73000 0x1000>; - interrupts = ; - clocks = <&mstp0_clks R8A7778_CLK_I2C3>; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - tmu0: timer@ffd80000 { - compatible = "renesas,tmu-r8a7778", "renesas,tmu"; - reg = <0xffd80000 0x30>; - interrupts = , - , - ; - clocks = <&mstp0_clks R8A7778_CLK_TMU0>; - clock-names = "fck"; - power-domains = <&cpg_clocks>; - - #renesas,channels = <3>; - - status = "disabled"; - }; - - tmu1: timer@ffd81000 { - compatible = "renesas,tmu-r8a7778", "renesas,tmu"; - reg = <0xffd81000 0x30>; - interrupts = , - , - ; - clocks = <&mstp0_clks R8A7778_CLK_TMU1>; - clock-names = "fck"; - power-domains = <&cpg_clocks>; - - #renesas,channels = <3>; - - status = "disabled"; - }; - - tmu2: timer@ffd82000 { - compatible = "renesas,tmu-r8a7778", "renesas,tmu"; - reg = <0xffd82000 0x30>; - interrupts = , - , - ; - clocks = <&mstp0_clks R8A7778_CLK_TMU2>; - clock-names = "fck"; - power-domains = <&cpg_clocks>; - - #renesas,channels = <3>; - - status = "disabled"; - }; - - rcar_sound: sound@ffd90000 { - /* - * #sound-dai-cells is required - * - * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; - * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; - */ - compatible = "renesas,rcar_sound-r8a7778", "renesas,rcar_sound-gen1"; - reg = <0xffd90000 0x1000>, /* SRU */ - <0xffd91000 0x240>, /* SSI */ - <0xfffe0000 0x24>; /* ADG */ - clocks = <&mstp3_clks R8A7778_CLK_SSI8>, - <&mstp3_clks R8A7778_CLK_SSI7>, - <&mstp3_clks R8A7778_CLK_SSI6>, - <&mstp3_clks R8A7778_CLK_SSI5>, - <&mstp3_clks R8A7778_CLK_SSI4>, - <&mstp0_clks R8A7778_CLK_SSI3>, - <&mstp0_clks R8A7778_CLK_SSI2>, - <&mstp0_clks R8A7778_CLK_SSI1>, - <&mstp0_clks R8A7778_CLK_SSI0>, - <&mstp5_clks R8A7778_CLK_SRU_SRC8>, - <&mstp5_clks R8A7778_CLK_SRU_SRC7>, - <&mstp5_clks R8A7778_CLK_SRU_SRC6>, - <&mstp5_clks R8A7778_CLK_SRU_SRC5>, - <&mstp5_clks R8A7778_CLK_SRU_SRC4>, - <&mstp5_clks R8A7778_CLK_SRU_SRC3>, - <&mstp5_clks R8A7778_CLK_SRU_SRC2>, - <&mstp5_clks R8A7778_CLK_SRU_SRC1>, - <&mstp5_clks R8A7778_CLK_SRU_SRC0>, - <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, - <&cpg_clocks R8A7778_CLK_S1>; - clock-names = "ssi.8", "ssi.7", "ssi.6", "ssi.5", "ssi.4", - "ssi.3", "ssi.2", "ssi.1", "ssi.0", - "src.8", "src.7", "src.6", "src.5", "src.4", - "src.3", "src.2", "src.1", "src.0", - "clk_a", "clk_b", "clk_c", "clk_i"; - - status = "disabled"; - - rcar_sound,src { - src3: src-3 { }; - src4: src-4 { }; - src5: src-5 { }; - src6: src-6 { }; - src7: src-7 { }; - src8: src-8 { }; - src9: src-9 { }; - }; - - rcar_sound,ssi { - ssi3: ssi-3 { interrupts = ; }; - ssi4: ssi-4 { interrupts = ; }; - ssi5: ssi-5 { interrupts = ; }; - ssi6: ssi-6 { interrupts = ; }; - ssi7: ssi-7 { interrupts = ; }; - ssi8: ssi-8 { interrupts = ; }; - ssi9: ssi-9 { interrupts = ; }; - }; - }; - - scif0: serial@ffe40000 { - compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif", - "renesas,scif"; - reg = <0xffe40000 0x100>; - interrupts = ; - clocks = <&mstp0_clks R8A7778_CLK_SCIF0>, - <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - scif1: serial@ffe41000 { - compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif", - "renesas,scif"; - reg = <0xffe41000 0x100>; - interrupts = ; - clocks = <&mstp0_clks R8A7778_CLK_SCIF1>, - <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - scif2: serial@ffe42000 { - compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif", - "renesas,scif"; - reg = <0xffe42000 0x100>; - interrupts = ; - clocks = <&mstp0_clks R8A7778_CLK_SCIF2>, - <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - scif3: serial@ffe43000 { - compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif", - "renesas,scif"; - reg = <0xffe43000 0x100>; - interrupts = ; - clocks = <&mstp0_clks R8A7778_CLK_SCIF3>, - <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - scif4: serial@ffe44000 { - compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif", - "renesas,scif"; - reg = <0xffe44000 0x100>; - interrupts = ; - clocks = <&mstp0_clks R8A7778_CLK_SCIF4>, - <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - scif5: serial@ffe45000 { - compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif", - "renesas,scif"; - reg = <0xffe45000 0x100>; - interrupts = ; - clocks = <&mstp0_clks R8A7778_CLK_SCIF5>, - <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - hscif0: serial@ffe48000 { - compatible = "renesas,hscif-r8a7778", - "renesas,rcar-gen1-hscif", "renesas,hscif"; - reg = <0xffe48000 96>; - interrupts = ; - clocks = <&mstp0_clks R8A7778_CLK_HSCIF0>, - <&cpg_clocks R8A7778_CLK_S>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - hscif1: serial@ffe49000 { - compatible = "renesas,hscif-r8a7778", - "renesas,rcar-gen1-hscif", "renesas,hscif"; - reg = <0xffe49000 96>; - interrupts = ; - clocks = <&mstp0_clks R8A7778_CLK_HSCIF1>, - <&cpg_clocks R8A7778_CLK_S>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - mmcif: mmc@ffe4e000 { - compatible = "renesas,mmcif-r8a7778", "renesas,sh-mmcif"; - reg = <0xffe4e000 0x100>; - interrupts = ; - clocks = <&mstp3_clks R8A7778_CLK_MMC>; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - sdhi0: sd@ffe4c000 { - compatible = "renesas,sdhi-r8a7778", - "renesas,rcar-gen1-sdhi"; - reg = <0xffe4c000 0x100>; - interrupts = ; - clocks = <&mstp3_clks R8A7778_CLK_SDHI0>; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - sdhi1: sd@ffe4d000 { - compatible = "renesas,sdhi-r8a7778", - "renesas,rcar-gen1-sdhi"; - reg = <0xffe4d000 0x100>; - interrupts = ; - clocks = <&mstp3_clks R8A7778_CLK_SDHI1>; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - sdhi2: sd@ffe4f000 { - compatible = "renesas,sdhi-r8a7778", - "renesas,rcar-gen1-sdhi"; - reg = <0xffe4f000 0x100>; - interrupts = ; - clocks = <&mstp3_clks R8A7778_CLK_SDHI2>; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - hspi0: spi@fffc7000 { - compatible = "renesas,hspi-r8a7778", "renesas,hspi"; - reg = <0xfffc7000 0x18>; - interrupts = ; - clocks = <&mstp0_clks R8A7778_CLK_HSPI>; - power-domains = <&cpg_clocks>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - hspi1: spi@fffc8000 { - compatible = "renesas,hspi-r8a7778", "renesas,hspi"; - reg = <0xfffc8000 0x18>; - interrupts = ; - clocks = <&mstp0_clks R8A7778_CLK_HSPI>; - power-domains = <&cpg_clocks>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - hspi2: spi@fffc6000 { - compatible = "renesas,hspi-r8a7778", "renesas,hspi"; - reg = <0xfffc6000 0x18>; - interrupts = ; - clocks = <&mstp0_clks R8A7778_CLK_HSPI>; - power-domains = <&cpg_clocks>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - /* External input clock */ - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - /* External SCIF clock */ - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - /* Special CPG clocks */ - cpg_clocks: cpg_clocks@ffc80000 { - compatible = "renesas,r8a7778-cpg-clocks"; - reg = <0xffc80000 0x80>; - #clock-cells = <1>; - clocks = <&extal_clk>; - clock-output-names = "plla", "pllb", "b", - "out", "p", "s", "s1"; - #power-domain-cells = <0>; - }; - - /* Audio clocks; frequencies are set by boards if applicable. */ - audio_clk_a: audio_clk_a { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - audio_clk_b: audio_clk_b { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - audio_clk_c: audio_clk_c { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - /* Fixed ratio clocks */ - g_clk: g { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7778_CLK_PLLA>; - #clock-cells = <0>; - clock-div = <12>; - clock-mult = <1>; - }; - i_clk: i { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7778_CLK_PLLA>; - #clock-cells = <0>; - clock-div = <1>; - clock-mult = <1>; - }; - s3_clk: s3 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7778_CLK_PLLA>; - #clock-cells = <0>; - clock-div = <4>; - clock-mult = <1>; - }; - s4_clk: s4 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7778_CLK_PLLA>; - #clock-cells = <0>; - clock-div = <8>; - clock-mult = <1>; - }; - z_clk: z { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7778_CLK_PLLB>; - #clock-cells = <0>; - clock-div = <1>; - clock-mult = <1>; - }; - - /* Gate clocks */ - mstp0_clks: mstp0_clks@ffc80030 { - compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0xffc80030 4>; - clocks = <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_S>, - <&cpg_clocks R8A7778_CLK_S>, - <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_S>; - #clock-cells = <1>; - clock-indices = < - R8A7778_CLK_I2C0 R8A7778_CLK_I2C1 - R8A7778_CLK_I2C2 R8A7778_CLK_I2C3 - R8A7778_CLK_SCIF0 R8A7778_CLK_SCIF1 - R8A7778_CLK_SCIF2 R8A7778_CLK_SCIF3 - R8A7778_CLK_SCIF4 R8A7778_CLK_SCIF5 - R8A7778_CLK_HSCIF0 R8A7778_CLK_HSCIF1 - R8A7778_CLK_TMU0 R8A7778_CLK_TMU1 - R8A7778_CLK_TMU2 R8A7778_CLK_SSI0 - R8A7778_CLK_SSI1 R8A7778_CLK_SSI2 - R8A7778_CLK_SSI3 R8A7778_CLK_SRU - R8A7778_CLK_HSPI - >; - clock-output-names = - "i2c0", "i2c1", "i2c2", "i2c3", "scif0", - "scif1", "scif2", "scif3", "scif4", "scif5", - "hscif0", "hscif1", - "tmu0", "tmu1", "tmu2", "ssi0", "ssi1", - "ssi2", "ssi3", "sru", "hspi"; - }; - mstp1_clks: mstp1_clks@ffc80034 { - compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0xffc80034 4>, <0xffc80044 4>; - clocks = <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_S>, - <&cpg_clocks R8A7778_CLK_S>, - <&cpg_clocks R8A7778_CLK_P>; - #clock-cells = <1>; - clock-indices = < - R8A7778_CLK_ETHER R8A7778_CLK_VIN0 - R8A7778_CLK_VIN1 R8A7778_CLK_USB - >; - clock-output-names = - "ether", "vin0", "vin1", "usb"; - }; - mstp3_clks: mstp3_clks@ffc8003c { - compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0xffc8003c 4>; - clocks = <&s4_clk>, - <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_P>; - #clock-cells = <1>; - clock-indices = < - R8A7778_CLK_MMC R8A7778_CLK_SDHI0 - R8A7778_CLK_SDHI1 R8A7778_CLK_SDHI2 - R8A7778_CLK_SSI4 R8A7778_CLK_SSI5 - R8A7778_CLK_SSI6 R8A7778_CLK_SSI7 - R8A7778_CLK_SSI8 - >; - clock-output-names = - "mmc", "sdhi0", "sdhi1", "sdhi2", "ssi4", - "ssi5", "ssi6", "ssi7", "ssi8"; - }; - mstp5_clks: mstp5_clks@ffc80054 { - compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0xffc80054 4>; - clocks = <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_P>; - #clock-cells = <1>; - clock-indices = < - R8A7778_CLK_SRU_SRC0 R8A7778_CLK_SRU_SRC1 - R8A7778_CLK_SRU_SRC2 R8A7778_CLK_SRU_SRC3 - R8A7778_CLK_SRU_SRC4 R8A7778_CLK_SRU_SRC5 - R8A7778_CLK_SRU_SRC6 R8A7778_CLK_SRU_SRC7 - R8A7778_CLK_SRU_SRC8 - >; - clock-output-names = - "sru-src0", "sru-src1", "sru-src2", - "sru-src3", "sru-src4", "sru-src5", - "sru-src6", "sru-src7", "sru-src8"; - }; - }; - - rst: reset-controller@ffcc0000 { - compatible = "renesas,r8a7778-reset-wdt"; - reg = <0xffcc0000 0x40>; - }; -}; diff --git a/sys/gnu/dts/arm/r8a7779-marzen.dts b/sys/gnu/dts/arm/r8a7779-marzen.dts deleted file mode 100644 index d2240b89ee5..00000000000 --- a/sys/gnu/dts/arm/r8a7779-marzen.dts +++ /dev/null @@ -1,264 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the R-Car H1 (R8A77790) Marzen board - * - * Copyright (C) 2013 Renesas Solutions Corp. - * Copyright (C) 2013 Simon Horman - */ - -/dts-v1/; -#include "r8a7779.dtsi" -#include -#include - -/ { - model = "marzen"; - compatible = "renesas,marzen", "renesas,r8a7779"; - - aliases { - serial0 = &scif2; - serial1 = &scif4; - }; - - chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; - stdout-path = "serial0:115200n8"; - }; - - memory@60000000 { - device_type = "memory"; - reg = <0x60000000 0x40000000>; - }; - - fixedregulator3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - vccq_sdhi0: regulator-vccq-sdhi0 { - compatible = "regulator-gpio"; - - regulator-name = "SDHI0 VccQ"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>; - gpios-states = <1>; - states = <3300000 1>, <1800000 0>; - }; - - ethernet@18000000 { - compatible = "smsc,lan9220", "smsc,lan9115"; - reg = <0x18000000 0x100>; - pinctrl-0 = <ðernet_pins>; - pinctrl-names = "default"; - - phy-mode = "mii"; - interrupt-parent = <&irqpin0>; - interrupts = <1 IRQ_TYPE_EDGE_FALLING>; - smsc,irq-push-pull; - reg-io-width = <4>; - vddvario-supply = <&fixedregulator3v3>; - vdd33a-supply = <&fixedregulator3v3>; - }; - - leds { - compatible = "gpio-leds"; - led2 { - gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>; - }; - led3 { - gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>; - }; - led4 { - gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>; - }; - }; - - vga-encoder { - compatible = "adi,adv7123"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - vga_enc_in: endpoint { - remote-endpoint = <&du_out_rgb0>; - }; - }; - port@1 { - reg = <1>; - vga_enc_out: endpoint { - remote-endpoint = <&vga_in>; - }; - }; - }; - }; - - vga { - compatible = "vga-connector"; - - port { - vga_in: endpoint { - remote-endpoint = <&vga_enc_out>; - }; - }; - }; - - lvds-encoder { - compatible = "thine,thc63lvdm83d"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - lvds_enc_in: endpoint { - remote-endpoint = <&du_out_rgb1>; - }; - }; - port@1 { - reg = <1>; - lvds_connector: endpoint { - }; - }; - }; - }; - - x3_clk: x3-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <65000000>; - }; -}; - -&du { - pinctrl-0 = <&du_pins>; - pinctrl-names = "default"; - status = "okay"; - - clocks = <&mstp1_clks R8A7779_CLK_DU>, <&x3_clk>; - clock-names = "du", "dclkin.0"; - - ports { - port@0 { - endpoint { - remote-endpoint = <&vga_enc_in>; - }; - }; - port@1 { - endpoint { - remote-endpoint = <&lvds_enc_in>; - }; - }; - }; -}; - -&irqpin0 { - status = "okay"; -}; - -&extal_clk { - clock-frequency = <31250000>; -}; - -&tmu0 { - status = "okay"; -}; - -&pfc { - pinctrl-0 = <&scif_clk_pins>; - pinctrl-names = "default"; - - du_pins: du { - du0 { - groups = "du0_rgb888", "du0_sync_1", "du0_clk_out_0", "du0_clk_in"; - function = "du0"; - }; - du1 { - groups = "du1_rgb666", "du1_sync_1", "du1_clk_out"; - function = "du1"; - }; - }; - - scif_clk_pins: scif_clk { - groups = "scif_clk_b"; - function = "scif_clk"; - }; - - ethernet_pins: ethernet { - intc { - groups = "intc_irq1_b"; - function = "intc"; - }; - lbsc { - groups = "lbsc_ex_cs0"; - function = "lbsc"; - }; - }; - - scif2_pins: scif2 { - groups = "scif2_data_c"; - function = "scif2"; - }; - - scif4_pins: scif4 { - groups = "scif4_data"; - function = "scif4"; - }; - - sdhi0_pins: sd0 { - groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd"; - function = "sdhi0"; - }; - - hspi0_pins: hspi0 { - groups = "hspi0"; - function = "hspi0"; - }; -}; - -&sata { - status = "okay"; -}; - -&scif2 { - pinctrl-0 = <&scif2_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&scif4 { - pinctrl-0 = <&scif4_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&scif_clk { - clock-frequency = <14745600>; -}; - -&sdhi0 { - pinctrl-0 = <&sdhi0_pins>; - pinctrl-names = "default"; - - vmmc-supply = <&fixedregulator3v3>; - vqmmc-supply = <&vccq_sdhi0>; - bus-width = <4>; - status = "okay"; -}; - -&hspi0 { - pinctrl-0 = <&hspi0_pins>; - pinctrl-names = "default"; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/r8a7779.dtsi b/sys/gnu/dts/arm/r8a7779.dtsi deleted file mode 100644 index c0999e27e9b..00000000000 --- a/sys/gnu/dts/arm/r8a7779.dtsi +++ /dev/null @@ -1,648 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the R-Car H1 (R8A77790) SoC - * - * Copyright (C) 2013 Renesas Solutions Corp. - * Copyright (C) 2013 Simon Horman - */ - -#include -#include -#include -#include - -/ { - compatible = "renesas,r8a7779"; - interrupt-parent = <&gic>; - #address-cells = <1>; - #size-cells = <1>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - clock-frequency = <1000000000>; - clocks = <&cpg_clocks R8A7779_CLK_Z>; - }; - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <1>; - clock-frequency = <1000000000>; - clocks = <&cpg_clocks R8A7779_CLK_Z>; - power-domains = <&sysc R8A7779_PD_ARM1>; - }; - cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <2>; - clock-frequency = <1000000000>; - clocks = <&cpg_clocks R8A7779_CLK_Z>; - power-domains = <&sysc R8A7779_PD_ARM2>; - }; - cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <3>; - clock-frequency = <1000000000>; - clocks = <&cpg_clocks R8A7779_CLK_Z>; - power-domains = <&sysc R8A7779_PD_ARM3>; - }; - }; - - aliases { - spi0 = &hspi0; - spi1 = &hspi1; - spi2 = &hspi2; - }; - - gic: interrupt-controller@f0001000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0xf0001000 0x1000>, - <0xf0000100 0x100>; - }; - - timer@f0000200 { - compatible = "arm,cortex-a9-global-timer"; - reg = <0xf0000200 0x100>; - interrupts = ; - clocks = <&cpg_clocks R8A7779_CLK_ZS>; - }; - - timer@f0000600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0xf0000600 0x20>; - interrupts = ; - clocks = <&cpg_clocks R8A7779_CLK_ZS>; - }; - - gpio0: gpio@ffc40000 { - compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio"; - reg = <0xffc40000 0x2c>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 0 32>; - #interrupt-cells = <2>; - interrupt-controller; - }; - - gpio1: gpio@ffc41000 { - compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio"; - reg = <0xffc41000 0x2c>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 32 32>; - #interrupt-cells = <2>; - interrupt-controller; - }; - - gpio2: gpio@ffc42000 { - compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio"; - reg = <0xffc42000 0x2c>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 64 32>; - #interrupt-cells = <2>; - interrupt-controller; - }; - - gpio3: gpio@ffc43000 { - compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio"; - reg = <0xffc43000 0x2c>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 96 32>; - #interrupt-cells = <2>; - interrupt-controller; - }; - - gpio4: gpio@ffc44000 { - compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio"; - reg = <0xffc44000 0x2c>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 128 32>; - #interrupt-cells = <2>; - interrupt-controller; - }; - - gpio5: gpio@ffc45000 { - compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio"; - reg = <0xffc45000 0x2c>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 160 32>; - #interrupt-cells = <2>; - interrupt-controller; - }; - - gpio6: gpio@ffc46000 { - compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio"; - reg = <0xffc46000 0x2c>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 192 9>; - #interrupt-cells = <2>; - interrupt-controller; - }; - - irqpin0: interrupt-controller@fe78001c { - compatible = "renesas,intc-irqpin-r8a7779", "renesas,intc-irqpin"; - #interrupt-cells = <2>; - status = "disabled"; - interrupt-controller; - reg = <0xfe78001c 4>, - <0xfe780010 4>, - <0xfe780024 4>, - <0xfe780044 4>, - <0xfe780064 4>, - <0xfe780000 4>; - interrupts = , - , - , - ; - sense-bitfield-width = <2>; - }; - - i2c0: i2c@ffc70000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7779", "renesas,rcar-gen1-i2c"; - reg = <0xffc70000 0x1000>; - interrupts = ; - clocks = <&mstp0_clks R8A7779_CLK_I2C0>; - power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; - status = "disabled"; - }; - - i2c1: i2c@ffc71000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7779", "renesas,rcar-gen1-i2c"; - reg = <0xffc71000 0x1000>; - interrupts = ; - clocks = <&mstp0_clks R8A7779_CLK_I2C1>; - power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; - status = "disabled"; - }; - - i2c2: i2c@ffc72000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7779", "renesas,rcar-gen1-i2c"; - reg = <0xffc72000 0x1000>; - interrupts = ; - clocks = <&mstp0_clks R8A7779_CLK_I2C2>; - power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; - status = "disabled"; - }; - - i2c3: i2c@ffc73000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7779", "renesas,rcar-gen1-i2c"; - reg = <0xffc73000 0x1000>; - interrupts = ; - clocks = <&mstp0_clks R8A7779_CLK_I2C3>; - power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; - status = "disabled"; - }; - - scif0: serial@ffe40000 { - compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif", - "renesas,scif"; - reg = <0xffe40000 0x100>; - interrupts = ; - clocks = <&mstp0_clks R8A7779_CLK_SCIF0>, - <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; - status = "disabled"; - }; - - scif1: serial@ffe41000 { - compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif", - "renesas,scif"; - reg = <0xffe41000 0x100>; - interrupts = ; - clocks = <&mstp0_clks R8A7779_CLK_SCIF1>, - <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; - status = "disabled"; - }; - - scif2: serial@ffe42000 { - compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif", - "renesas,scif"; - reg = <0xffe42000 0x100>; - interrupts = ; - clocks = <&mstp0_clks R8A7779_CLK_SCIF2>, - <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; - status = "disabled"; - }; - - scif3: serial@ffe43000 { - compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif", - "renesas,scif"; - reg = <0xffe43000 0x100>; - interrupts = ; - clocks = <&mstp0_clks R8A7779_CLK_SCIF3>, - <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; - status = "disabled"; - }; - - scif4: serial@ffe44000 { - compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif", - "renesas,scif"; - reg = <0xffe44000 0x100>; - interrupts = ; - clocks = <&mstp0_clks R8A7779_CLK_SCIF4>, - <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; - status = "disabled"; - }; - - scif5: serial@ffe45000 { - compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif", - "renesas,scif"; - reg = <0xffe45000 0x100>; - interrupts = ; - clocks = <&mstp0_clks R8A7779_CLK_SCIF5>, - <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; - status = "disabled"; - }; - - hscif0: serial@ffe48000 { - compatible = "renesas,hscif-r8a7779", - "renesas,rcar-gen1-hscif", "renesas,hscif"; - reg = <0xffe48000 96>; - interrupts = ; - clocks = <&mstp0_clks R8A7779_CLK_HSCIF0>, - <&cpg_clocks R8A7779_CLK_S>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; - status = "disabled"; - }; - - hscif1: serial@ffe49000 { - compatible = "renesas,hscif-r8a7779", - "renesas,rcar-gen1-hscif", "renesas,hscif"; - reg = <0xffe49000 96>; - interrupts = ; - clocks = <&mstp0_clks R8A7779_CLK_HSCIF1>, - <&cpg_clocks R8A7779_CLK_S>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pfc: pin-controller@fffc0000 { - compatible = "renesas,pfc-r8a7779"; - reg = <0xfffc0000 0x23c>; - }; - - thermal@ffc48000 { - compatible = "renesas,thermal-r8a7779", "renesas,rcar-thermal"; - reg = <0xffc48000 0x38>; - }; - - tmu0: timer@ffd80000 { - compatible = "renesas,tmu-r8a7779", "renesas,tmu"; - reg = <0xffd80000 0x30>; - interrupts = , - , - ; - clocks = <&mstp0_clks R8A7779_CLK_TMU0>; - clock-names = "fck"; - power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; - - #renesas,channels = <3>; - - status = "disabled"; - }; - - tmu1: timer@ffd81000 { - compatible = "renesas,tmu-r8a7779", "renesas,tmu"; - reg = <0xffd81000 0x30>; - interrupts = , - , - ; - clocks = <&mstp0_clks R8A7779_CLK_TMU1>; - clock-names = "fck"; - power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; - - #renesas,channels = <3>; - - status = "disabled"; - }; - - tmu2: timer@ffd82000 { - compatible = "renesas,tmu-r8a7779", "renesas,tmu"; - reg = <0xffd82000 0x30>; - interrupts = , - , - ; - clocks = <&mstp0_clks R8A7779_CLK_TMU2>; - clock-names = "fck"; - power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; - - #renesas,channels = <3>; - - status = "disabled"; - }; - - sata: sata@fc600000 { - compatible = "renesas,sata-r8a7779"; - reg = <0xfc600000 0x200000>; - interrupts = ; - clocks = <&mstp1_clks R8A7779_CLK_SATA>; - power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; - status = "disabled"; - }; - - sdhi0: sd@ffe4c000 { - compatible = "renesas,sdhi-r8a7779", - "renesas,rcar-gen1-sdhi"; - reg = <0xffe4c000 0x100>; - interrupts = ; - clocks = <&mstp3_clks R8A7779_CLK_SDHI0>; - power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; - status = "disabled"; - }; - - sdhi1: sd@ffe4d000 { - compatible = "renesas,sdhi-r8a7779", - "renesas,rcar-gen1-sdhi"; - reg = <0xffe4d000 0x100>; - interrupts = ; - clocks = <&mstp3_clks R8A7779_CLK_SDHI1>; - power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; - status = "disabled"; - }; - - sdhi2: sd@ffe4e000 { - compatible = "renesas,sdhi-r8a7779", - "renesas,rcar-gen1-sdhi"; - reg = <0xffe4e000 0x100>; - interrupts = ; - clocks = <&mstp3_clks R8A7779_CLK_SDHI2>; - power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; - status = "disabled"; - }; - - sdhi3: sd@ffe4f000 { - compatible = "renesas,sdhi-r8a7779", - "renesas,rcar-gen1-sdhi"; - reg = <0xffe4f000 0x100>; - interrupts = ; - clocks = <&mstp3_clks R8A7779_CLK_SDHI3>; - power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; - status = "disabled"; - }; - - hspi0: spi@fffc7000 { - compatible = "renesas,hspi-r8a7779", "renesas,hspi"; - reg = <0xfffc7000 0x18>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&mstp0_clks R8A7779_CLK_HSPI>; - power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; - status = "disabled"; - }; - - hspi1: spi@fffc8000 { - compatible = "renesas,hspi-r8a7779", "renesas,hspi"; - reg = <0xfffc8000 0x18>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&mstp0_clks R8A7779_CLK_HSPI>; - power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; - status = "disabled"; - }; - - hspi2: spi@fffc6000 { - compatible = "renesas,hspi-r8a7779", "renesas,hspi"; - reg = <0xfffc6000 0x18>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&mstp0_clks R8A7779_CLK_HSPI>; - power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; - status = "disabled"; - }; - - du: display@fff80000 { - compatible = "renesas,du-r8a7779"; - reg = <0xfff80000 0x40000>; - interrupts = ; - clocks = <&mstp1_clks R8A7779_CLK_DU>; - power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - du_out_rgb0: endpoint { - }; - }; - port@1 { - reg = <1>; - du_out_rgb1: endpoint { - }; - }; - }; - }; - - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - /* External root clock */ - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overriden by the board. */ - clock-frequency = <0>; - }; - - /* External SCIF clock */ - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - /* Special CPG clocks */ - cpg_clocks: clocks@ffc80000 { - compatible = "renesas,r8a7779-cpg-clocks"; - reg = <0xffc80000 0x30>; - clocks = <&extal_clk>; - #clock-cells = <1>; - clock-output-names = "plla", "z", "zs", "s", - "s1", "p", "b", "out"; - #power-domain-cells = <0>; - }; - - /* Fixed factor clocks */ - i_clk: i { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7779_CLK_PLLA>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - s3_clk: s3 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7779_CLK_PLLA>; - #clock-cells = <0>; - clock-div = <8>; - clock-mult = <1>; - }; - s4_clk: s4 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7779_CLK_PLLA>; - #clock-cells = <0>; - clock-div = <16>; - clock-mult = <1>; - }; - g_clk: g { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7779_CLK_PLLA>; - #clock-cells = <0>; - clock-div = <24>; - clock-mult = <1>; - }; - - /* Gate clocks */ - mstp0_clks: clocks@ffc80030 { - compatible = "renesas,r8a7779-mstp-clocks", - "renesas,cpg-mstp-clocks"; - reg = <0xffc80030 4>; - clocks = <&cpg_clocks R8A7779_CLK_S>, - <&cpg_clocks R8A7779_CLK_P>, - <&cpg_clocks R8A7779_CLK_P>, - <&cpg_clocks R8A7779_CLK_P>, - <&cpg_clocks R8A7779_CLK_S>, - <&cpg_clocks R8A7779_CLK_S>, - <&cpg_clocks R8A7779_CLK_P>, - <&cpg_clocks R8A7779_CLK_P>, - <&cpg_clocks R8A7779_CLK_P>, - <&cpg_clocks R8A7779_CLK_P>, - <&cpg_clocks R8A7779_CLK_P>, - <&cpg_clocks R8A7779_CLK_P>, - <&cpg_clocks R8A7779_CLK_P>, - <&cpg_clocks R8A7779_CLK_P>, - <&cpg_clocks R8A7779_CLK_P>, - <&cpg_clocks R8A7779_CLK_P>; - #clock-cells = <1>; - clock-indices = < - R8A7779_CLK_HSPI R8A7779_CLK_TMU2 - R8A7779_CLK_TMU1 R8A7779_CLK_TMU0 - R8A7779_CLK_HSCIF1 R8A7779_CLK_HSCIF0 - R8A7779_CLK_SCIF5 R8A7779_CLK_SCIF4 - R8A7779_CLK_SCIF3 R8A7779_CLK_SCIF2 - R8A7779_CLK_SCIF1 R8A7779_CLK_SCIF0 - R8A7779_CLK_I2C3 R8A7779_CLK_I2C2 - R8A7779_CLK_I2C1 R8A7779_CLK_I2C0 - >; - clock-output-names = - "hspi", "tmu2", "tmu1", "tmu0", "hscif1", - "hscif0", "scif5", "scif4", "scif3", "scif2", - "scif1", "scif0", "i2c3", "i2c2", "i2c1", - "i2c0"; - }; - mstp1_clks: clocks@ffc80034 { - compatible = "renesas,r8a7779-mstp-clocks", - "renesas,cpg-mstp-clocks"; - reg = <0xffc80034 4>, <0xffc80044 4>; - clocks = <&cpg_clocks R8A7779_CLK_P>, - <&cpg_clocks R8A7779_CLK_P>, - <&cpg_clocks R8A7779_CLK_S>, - <&cpg_clocks R8A7779_CLK_S>, - <&cpg_clocks R8A7779_CLK_S>, - <&cpg_clocks R8A7779_CLK_S>, - <&cpg_clocks R8A7779_CLK_P>, - <&cpg_clocks R8A7779_CLK_P>, - <&cpg_clocks R8A7779_CLK_P>, - <&cpg_clocks R8A7779_CLK_S>; - #clock-cells = <1>; - clock-indices = < - R8A7779_CLK_USB01 R8A7779_CLK_USB2 - R8A7779_CLK_DU R8A7779_CLK_VIN2 - R8A7779_CLK_VIN1 R8A7779_CLK_VIN0 - R8A7779_CLK_ETHER R8A7779_CLK_SATA - R8A7779_CLK_PCIE R8A7779_CLK_VIN3 - >; - clock-output-names = - "usb01", "usb2", - "du", "vin2", - "vin1", "vin0", - "ether", "sata", - "pcie", "vin3"; - }; - mstp3_clks: clocks@ffc8003c { - compatible = "renesas,r8a7779-mstp-clocks", - "renesas,cpg-mstp-clocks"; - reg = <0xffc8003c 4>; - clocks = <&s4_clk>, <&s4_clk>, <&s4_clk>, <&s4_clk>, - <&s4_clk>, <&s4_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7779_CLK_SDHI3 R8A7779_CLK_SDHI2 - R8A7779_CLK_SDHI1 R8A7779_CLK_SDHI0 - R8A7779_CLK_MMC1 R8A7779_CLK_MMC0 - >; - clock-output-names = - "sdhi3", "sdhi2", "sdhi1", "sdhi0", - "mmc1", "mmc0"; - }; - }; - - prr: chipid@ff000044 { - compatible = "renesas,prr"; - reg = <0xff000044 4>; - }; - - rst: reset-controller@ffcc0000 { - compatible = "renesas,r8a7779-reset-wdt"; - reg = <0xffcc0000 0x48>; - }; - - sysc: system-controller@ffd85000 { - compatible = "renesas,r8a7779-sysc"; - reg = <0xffd85000 0x0200>; - #power-domain-cells = <1>; - }; -}; diff --git a/sys/gnu/dts/arm/r8a7790-lager.dts b/sys/gnu/dts/arm/r8a7790-lager.dts deleted file mode 100644 index 097fd9317c6..00000000000 --- a/sys/gnu/dts/arm/r8a7790-lager.dts +++ /dev/null @@ -1,936 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the Lager board - * - * Copyright (C) 2013-2014 Renesas Solutions Corp. - * Copyright (C) 2014 Cogent Embedded, Inc. - * Copyright (C) 2015-2016 Renesas Electronics Corporation - */ - -/* - * SSI-AK4643 - * - * SW1: 1: AK4643 - * 2: CN22 - * 3: ADV7511 - * - * This command is required when Playback/Capture - * - * amixer set "LINEOUT Mixer DACL" on - * amixer set "DVC Out" 100% - * amixer set "DVC In" 100% - * - * You can use Mute - * - * amixer set "DVC Out Mute" on - * amixer set "DVC In Mute" on - * - * You can use Volume Ramp - * - * amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps" - * amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps" - * amixer set "DVC Out Ramp" on - * aplay xxx.wav & - * amixer set "DVC Out" 80% // Volume Down - * amixer set "DVC Out" 100% // Volume Up - */ - -/dts-v1/; -#include "r8a7790.dtsi" -#include -#include - -/ { - model = "Lager"; - compatible = "renesas,lager", "renesas,r8a7790"; - - aliases { - serial0 = &scif0; - serial1 = &scifa1; - i2c8 = &gpioi2c1; - i2c9 = &gpioi2c2; - i2c10 = &i2cexio0; - i2c11 = &i2cexio1; - i2c12 = &i2chdmi; - i2c13 = &i2cpwr; - }; - - chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; - stdout-path = "serial0:115200n8"; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0 0x40000000 0 0x40000000>; - }; - - memory@140000000 { - device_type = "memory"; - reg = <1 0x40000000 0 0xc0000000>; - }; - - lbsc { - #address-cells = <1>; - #size-cells = <1>; - }; - - keyboard { - compatible = "gpio-keys"; - - one { - linux,code = ; - label = "SW2-1"; - wakeup-source; - debounce-interval = <20>; - gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; - }; - two { - linux,code = ; - label = "SW2-2"; - wakeup-source; - debounce-interval = <20>; - gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; - }; - three { - linux,code = ; - label = "SW2-3"; - wakeup-source; - debounce-interval = <20>; - gpios = <&gpio1 26 GPIO_ACTIVE_LOW>; - }; - four { - linux,code = ; - label = "SW2-4"; - wakeup-source; - debounce-interval = <20>; - gpios = <&gpio1 28 GPIO_ACTIVE_LOW>; - }; - }; - - leds { - compatible = "gpio-leds"; - led6 { - gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>; - }; - led7 { - gpios = <&gpio4 23 GPIO_ACTIVE_HIGH>; - }; - led8 { - gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>; - }; - }; - - fixedregulator3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - vcc_sdhi0: regulator-vcc-sdhi0 { - compatible = "regulator-fixed"; - - regulator-name = "SDHI0 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&gpio5 24 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vccq_sdhi0: regulator-vccq-sdhi0 { - compatible = "regulator-gpio"; - - regulator-name = "SDHI0 VccQ"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>; - gpios-states = <1>; - states = <3300000 1>, <1800000 0>; - }; - - vcc_sdhi2: regulator-vcc-sdhi2 { - compatible = "regulator-fixed"; - - regulator-name = "SDHI2 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&gpio5 25 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vccq_sdhi2: regulator-vccq-sdhi2 { - compatible = "regulator-gpio"; - - regulator-name = "SDHI2 VccQ"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio5 30 GPIO_ACTIVE_HIGH>; - gpios-states = <1>; - states = <3300000 1>, <1800000 0>; - }; - - audio_clock: audio_clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <11289600>; - }; - - rsnd_ak4643: sound { - compatible = "simple-audio-card"; - - simple-audio-card,format = "left_j"; - simple-audio-card,bitclock-master = <&sndcodec>; - simple-audio-card,frame-master = <&sndcodec>; - - sndcpu: simple-audio-card,cpu { - sound-dai = <&rcar_sound>; - }; - - sndcodec: simple-audio-card,codec { - sound-dai = <&ak4643>; - clocks = <&audio_clock>; - }; - }; - - vga-encoder { - compatible = "adi,adv7123"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7123_in: endpoint { - remote-endpoint = <&du_out_rgb>; - }; - }; - port@1 { - reg = <1>; - adv7123_out: endpoint { - remote-endpoint = <&vga_in>; - }; - }; - }; - }; - - vga { - compatible = "vga-connector"; - - port { - vga_in: endpoint { - remote-endpoint = <&adv7123_out>; - }; - }; - }; - - hdmi-in { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&adv7612_in>; - }; - }; - }; - - cec_clock: cec-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <12000000>; - }; - - hdmi-out { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_out: endpoint { - remote-endpoint = <&adv7511_out>; - }; - }; - }; - - x2_clk: x2-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <148500000>; - }; - - x13_clk: x13-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <148500000>; - }; - - gpioi2c1: i2c-8 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "i2c-gpio"; - status = "disabled"; - scl-gpios = <&gpio1 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio1 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <5>; - }; - - gpioi2c2: i2c-9 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "i2c-gpio"; - status = "disabled"; - scl-gpios = <&gpio5 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <5>; - }; - - /* - * IIC0/I2C0 is routed to EXIO connector A, pins 114 (SCL) + 116 (SDA) only. - * We use the I2C demuxer, so the desired IP core can be selected at runtime - * depending on the use case (e.g. DMA with IIC0 or slave support with I2C0). - * Note: For testing the I2C slave feature, it is convenient to connect this - * bus with IIC3 on pins 110 (SCL) + 112 (SDA), select I2C0 at runtime, and - * instantiate the slave device at runtime according to the documentation. - * You can then communicate with the slave via IIC3. - * - * IIC0/I2C0 does not appear to support fallback to GPIO. - */ - i2cexio0: i2c-10 { - compatible = "i2c-demux-pinctrl"; - i2c-parent = <&iic0>, <&i2c0>; - i2c-bus-name = "i2c-exio0"; - #address-cells = <1>; - #size-cells = <0>; - }; - - /* - * IIC1/I2C1 is routed to EXIO connector A, pins 78 (SCL) + 80 (SDA). - * This is similar to the arangement described for i2cexio0 (above) - * with a fallback to GPIO also provided. - */ - i2cexio1: i2c-11 { - compatible = "i2c-demux-pinctrl"; - i2c-parent = <&iic1>, <&i2c1>, <&gpioi2c1>; - i2c-bus-name = "i2c-exio1"; - #address-cells = <1>; - #size-cells = <0>; - }; - - /* - * IIC2 and I2C2 may be switched using pinmux. - * A fallback to GPIO is also provided. - */ - i2chdmi: i2c-12 { - compatible = "i2c-demux-pinctrl"; - i2c-parent = <&iic2>, <&i2c2>, <&gpioi2c2>; - i2c-bus-name = "i2c-hdmi"; - #address-cells = <1>; - #size-cells = <0>; - - ak4643: codec@12 { - compatible = "asahi-kasei,ak4643"; - #sound-dai-cells = <0>; - reg = <0x12>; - }; - - composite-in@20 { - compatible = "adi,adv7180"; - reg = <0x20>; - remote = <&vin1>; - - port { - adv7180: endpoint { - bus-width = <8>; - remote-endpoint = <&vin1ep0>; - }; - }; - }; - - hdmi@39 { - compatible = "adi,adv7511w"; - reg = <0x39>; - interrupt-parent = <&gpio1>; - interrupts = <15 IRQ_TYPE_LEVEL_LOW>; - clocks = <&cec_clock>; - clock-names = "cec"; - - adi,input-depth = <8>; - adi,input-colorspace = "rgb"; - adi,input-clock = "1x"; - adi,input-style = <1>; - adi,input-justification = "evenly"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7511_in: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - - port@1 { - reg = <1>; - adv7511_out: endpoint { - remote-endpoint = <&hdmi_con_out>; - }; - }; - }; - }; - - hdmi-in@4c { - compatible = "adi,adv7612"; - reg = <0x4c>; - interrupt-parent = <&gpio1>; - interrupts = <20 IRQ_TYPE_LEVEL_LOW>; - default-input = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7612_in: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; - }; - - port@2 { - reg = <2>; - adv7612_out: endpoint { - remote-endpoint = <&vin0ep2>; - }; - }; - }; - }; - }; - - /* - * IIC3 and I2C3 may be switched using pinmux. - * IIC3/I2C3 does not appear to support fallback to GPIO. - */ - i2cpwr: i2c-13 { - compatible = "i2c-demux-pinctrl"; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_irq_pins>; - i2c-parent = <&iic3>, <&i2c3>; - i2c-bus-name = "i2c-pwr"; - #address-cells = <1>; - #size-cells = <0>; - - pmic@58 { - compatible = "dlg,da9063"; - reg = <0x58>; - interrupt-parent = <&irqc0>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - - rtc { - compatible = "dlg,da9063-rtc"; - }; - - wdt { - compatible = "dlg,da9063-watchdog"; - }; - }; - - vdd_dvfs: regulator@68 { - compatible = "dlg,da9210"; - reg = <0x68>; - interrupt-parent = <&irqc0>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-boot-on; - regulator-always-on; - }; - }; -}; - -&du { - pinctrl-0 = <&du_pins>; - pinctrl-names = "default"; - status = "okay"; - - clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 722>, - <&x13_clk>, <&x2_clk>; - clock-names = "du.0", "du.1", "du.2", "dclkin.0", "dclkin.1"; - - ports { - port@0 { - endpoint { - remote-endpoint = <&adv7123_in>; - }; - }; - }; -}; - -&lvds0 { - status = "okay"; - - ports { - port@1 { - endpoint { - remote-endpoint = <&adv7511_in>; - }; - }; - }; -}; - -&lvds1 { - ports { - port@1 { - lvds_connector: endpoint { - }; - }; - }; -}; - -&extal_clk { - clock-frequency = <20000000>; -}; - -&pfc { - pinctrl-0 = <&scif_clk_pins>; - pinctrl-names = "default"; - - du_pins: du { - groups = "du_rgb666", "du_sync_1", "du_clk_out_0"; - function = "du"; - }; - - scif0_pins: scif0 { - groups = "scif0_data"; - function = "scif0"; - }; - - scif_clk_pins: scif_clk { - groups = "scif_clk"; - function = "scif_clk"; - }; - - ether_pins: ether { - groups = "eth_link", "eth_mdio", "eth_rmii"; - function = "eth"; - }; - - phy1_pins: phy1 { - groups = "intc_irq0"; - function = "intc"; - }; - - scifa1_pins: scifa1 { - groups = "scifa1_data"; - function = "scifa1"; - }; - - sdhi0_pins: sd0 { - groups = "sdhi0_data4", "sdhi0_ctrl"; - function = "sdhi0"; - power-source = <3300>; - }; - - sdhi0_pins_uhs: sd0_uhs { - groups = "sdhi0_data4", "sdhi0_ctrl"; - function = "sdhi0"; - power-source = <1800>; - }; - - sdhi2_pins: sd2 { - groups = "sdhi2_data4", "sdhi2_ctrl"; - function = "sdhi2"; - power-source = <3300>; - }; - - sdhi2_pins_uhs: sd2_uhs { - groups = "sdhi2_data4", "sdhi2_ctrl"; - function = "sdhi2"; - power-source = <1800>; - }; - - mmc1_pins: mmc1 { - groups = "mmc1_data8", "mmc1_ctrl"; - function = "mmc1"; - }; - - qspi_pins: qspi { - groups = "qspi_ctrl", "qspi_data4"; - function = "qspi"; - }; - - msiof1_pins: msiof1 { - groups = "msiof1_clk", "msiof1_sync", "msiof1_rx", - "msiof1_tx"; - function = "msiof1"; - }; - - i2c0_pins: i2c0 { - groups = "i2c0"; - function = "i2c0"; - }; - - iic0_pins: iic0 { - groups = "iic0"; - function = "iic0"; - }; - - i2c1_pins: i2c1 { - groups = "i2c1"; - function = "i2c1"; - }; - - iic1_pins: iic1 { - groups = "iic1"; - function = "iic1"; - }; - - i2c2_pins: i2c2 { - groups = "i2c2"; - function = "i2c2"; - }; - - iic2_pins: iic2 { - groups = "iic2"; - function = "iic2"; - }; - - i2c3_pins: i2c3 { - groups = "i2c3"; - function = "i2c3"; - }; - - iic3_pins: iic3 { - groups = "iic3"; - function = "iic3"; - }; - - pmic_irq_pins: pmicirq { - groups = "intc_irq2"; - function = "intc"; - }; - - hsusb_pins: hsusb { - groups = "usb0_ovc_vbus"; - function = "usb0"; - }; - - usb0_pins: usb0 { - groups = "usb0"; - function = "usb0"; - }; - - usb1_pins: usb1 { - groups = "usb1"; - function = "usb1"; - }; - - usb2_pins: usb2 { - groups = "usb2"; - function = "usb2"; - }; - - vin0_pins: vin0 { - groups = "vin0_data24", "vin0_sync", "vin0_clkenb", "vin0_clk"; - function = "vin0"; - }; - - vin1_pins: vin1 { - groups = "vin1_data8", "vin1_clk"; - function = "vin1"; - }; - - sound_pins: sound { - groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data"; - function = "ssi"; - }; - - sound_clk_pins: sound_clk { - groups = "audio_clk_a"; - function = "audio_clk"; - }; -}; - -ðer { - pinctrl-0 = <ðer_pins &phy1_pins>; - pinctrl-names = "default"; - - phy-handle = <&phy1>; - renesas,ether-link-active-low; - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - interrupt-parent = <&irqc0>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - micrel,led-mode = <1>; - }; -}; - -&cmt0 { - status = "okay"; -}; - -&mmcif1 { - pinctrl-0 = <&mmc1_pins>; - pinctrl-names = "default"; - - vmmc-supply = <&fixedregulator3v3>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&sata1 { - status = "okay"; -}; - -&qspi { - pinctrl-0 = <&qspi_pins>; - pinctrl-names = "default"; - - status = "okay"; - - flash: flash@0 { - compatible = "spansion,s25fl512s", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <30000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - spi-cpha; - spi-cpol; - m25p,fast-read; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "loader"; - reg = <0x00000000 0x00040000>; - read-only; - }; - partition@40000 { - label = "user"; - reg = <0x00040000 0x00400000>; - read-only; - }; - partition@440000 { - label = "flash"; - reg = <0x00440000 0x03bc0000>; - }; - }; - }; -}; - -&scif0 { - pinctrl-0 = <&scif0_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&scifa1 { - pinctrl-0 = <&scifa1_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&scif_clk { - clock-frequency = <14745600>; -}; - -&msiof1 { - pinctrl-0 = <&msiof1_pins>; - pinctrl-names = "default"; - - status = "okay"; - - pmic: pmic@0 { - compatible = "renesas,r2a11302ft"; - reg = <0>; - spi-max-frequency = <6000000>; - spi-cpol; - spi-cpha; - }; -}; - -&sdhi0 { - pinctrl-0 = <&sdhi0_pins>; - pinctrl-1 = <&sdhi0_pins_uhs>; - pinctrl-names = "default", "state_uhs"; - - vmmc-supply = <&vcc_sdhi0>; - vqmmc-supply = <&vccq_sdhi0>; - cd-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>; - sd-uhs-sdr50; - sd-uhs-sdr104; - status = "okay"; -}; - -&sdhi2 { - pinctrl-0 = <&sdhi2_pins>; - pinctrl-1 = <&sdhi2_pins_uhs>; - pinctrl-names = "default", "state_uhs"; - - vmmc-supply = <&vcc_sdhi2>; - vqmmc-supply = <&vccq_sdhi2>; - cd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>; - sd-uhs-sdr50; - status = "okay"; -}; - -&cpu0 { - cpu0-supply = <&vdd_dvfs>; -}; - -&i2c0 { - pinctrl-0 = <&i2c0_pins>; - pinctrl-names = "i2c-exio0"; -}; - -&iic0 { - pinctrl-0 = <&iic0_pins>; - pinctrl-names = "i2c-exio0"; -}; - -&i2c1 { - pinctrl-0 = <&i2c1_pins>; - pinctrl-names = "i2c-exio1"; -}; - -&iic1 { - pinctrl-0 = <&iic1_pins>; - pinctrl-names = "i2c-exio1"; -}; - -&i2c2 { - pinctrl-0 = <&i2c2_pins>; - pinctrl-names = "i2c-hdmi"; - - clock-frequency = <100000>; -}; - -&iic2 { - pinctrl-0 = <&iic2_pins>; - pinctrl-names = "i2c-hdmi"; - - clock-frequency = <100000>; -}; - -&i2c3 { - pinctrl-0 = <&i2c3_pins>; - pinctrl-names = "i2c-pwr"; -}; - -&iic3 { - pinctrl-0 = <&iic3_pins>; - pinctrl-names = "i2c-pwr"; -}; - -&pci0 { - status = "okay"; - pinctrl-0 = <&usb0_pins>; - pinctrl-names = "default"; -}; - -&pci1 { - status = "okay"; - pinctrl-0 = <&usb1_pins>; - pinctrl-names = "default"; -}; - -&xhci { - status = "okay"; - pinctrl-0 = <&usb2_pins>; - pinctrl-names = "default"; -}; - -&pci2 { - status = "okay"; - pinctrl-0 = <&usb2_pins>; - pinctrl-names = "default"; -}; - -&hsusb { - status = "okay"; - pinctrl-0 = <&hsusb_pins>; - pinctrl-names = "default"; - renesas,enable-gpio = <&gpio5 18 GPIO_ACTIVE_HIGH>; -}; - -&usbphy { - status = "okay"; -}; - -/* HDMI video input */ -&vin0 { - pinctrl-0 = <&vin0_pins>; - pinctrl-names = "default"; - - status = "okay"; - - port { - vin0ep2: endpoint { - remote-endpoint = <&adv7612_out>; - bus-width = <24>; - hsync-active = <0>; - vsync-active = <0>; - pclk-sample = <1>; - data-active = <1>; - }; - }; -}; - -/* composite video input */ -&vin1 { - pinctrl-0 = <&vin1_pins>; - pinctrl-names = "default"; - - status = "okay"; - - port { - vin1ep0: endpoint { - remote-endpoint = <&adv7180>; - bus-width = <8>; - }; - }; -}; - -&rcar_sound { - pinctrl-0 = <&sound_pins &sound_clk_pins>; - pinctrl-names = "default"; - - /* Single DAI */ - #sound-dai-cells = <0>; - - status = "okay"; - - rcar_sound,dai { - dai0 { - playback = <&ssi0 &src2 &dvc0>; - capture = <&ssi1 &src3 &dvc1>; - }; - }; -}; - -&rwdt { - timeout-sec = <60>; - status = "okay"; -}; - -&ssi1 { - shared-pin; -}; diff --git a/sys/gnu/dts/arm/r8a7790-stout.dts b/sys/gnu/dts/arm/r8a7790-stout.dts deleted file mode 100644 index a315ba749aa..00000000000 --- a/sys/gnu/dts/arm/r8a7790-stout.dts +++ /dev/null @@ -1,381 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the Stout board - * - * Copyright (C) 2018 Marek Vasut - */ - -/dts-v1/; -#include "r8a7790.dtsi" -#include -#include - -/ { - model = "Stout"; - compatible = "renesas,stout", "renesas,r8a7790"; - - aliases { - serial0 = &scifa0; - }; - - chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; - stdout-path = "serial0:115200n8"; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0 0x40000000 0 0x40000000>; - }; - - leds { - compatible = "gpio-leds"; - led1 { - gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; - }; - led2 { - gpios = <&gpio4 23 GPIO_ACTIVE_LOW>; - }; - led3 { - gpios = <&gpio5 17 GPIO_ACTIVE_LOW>; - }; - led5 { - gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; - }; - }; - - fixedregulator3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - vcc_sdhi0: regulator-vcc-sdhi0 { - compatible = "regulator-fixed"; - - regulator-name = "SDHI0 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&gpio5 24 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - hdmi-out { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_out: endpoint { - remote-endpoint = <&adv7511_out>; - }; - }; - }; - - osc1_clk: osc1-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <148500000>; - }; - - osc4_clk: osc4-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <12000000>; - }; -}; - -&du { - pinctrl-0 = <&du_pins>; - pinctrl-names = "default"; - status = "okay"; - - clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 722>, - <&osc1_clk>; - clock-names = "du.0", "du.1", "du.2", "dclkin.0"; - - ports { - port@0 { - endpoint { - remote-endpoint = <&adv7511_in>; - }; - }; - }; -}; - -&lvds0 { - ports { - port@1 { - lvds_connector0: endpoint { - }; - }; - }; -}; - -&lvds1 { - ports { - port@1 { - lvds_connector1: endpoint { - }; - }; - }; -}; - -&extal_clk { - clock-frequency = <20000000>; -}; - -&pfc { - - pinctrl-0 = <&scif_clk_pins>; - pinctrl-names = "default"; - - du_pins: du { - groups = "du_rgb888", "du_sync_1", "du_clk_out_0"; - function = "du"; - }; - - scifa0_pins: scifa0 { - groups = "scifa0_data_b"; - function = "scifa0"; - }; - - scif_clk_pins: scif_clk { - groups = "scif_clk"; - function = "scif_clk"; - }; - - ether_pins: ether { - groups = "eth_link", "eth_mdio", "eth_rmii"; - function = "eth"; - }; - - phy1_pins: phy1 { - groups = "intc_irq1"; - function = "intc"; - }; - - sdhi0_pins: sd0 { - groups = "sdhi0_data4", "sdhi0_ctrl"; - function = "sdhi0"; - power-source = <3300>; - }; - - qspi_pins: qspi { - groups = "qspi_ctrl", "qspi_data4"; - function = "qspi"; - }; - - iic2_pins: iic2 { - groups = "iic2_b"; - function = "iic2"; - }; - - iic3_pins: iic3 { - groups = "iic3"; - function = "iic3"; - }; - - pmic_irq_pins: pmicirq { - groups = "intc_irq2"; - function = "intc"; - }; - - usb0_pins: usb0 { - groups = "usb0"; - function = "usb0"; - }; -}; - -ðer { - pinctrl-0 = <ðer_pins &phy1_pins>; - pinctrl-names = "default"; - - phy-handle = <&phy1>; - renesas,ether-link-active-low; - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - interrupt-parent = <&irqc0>; - interrupts = <1 IRQ_TYPE_LEVEL_LOW>; - micrel,led-mode = <1>; - }; -}; - -&cmt0 { - status = "okay"; -}; - -&qspi { - pinctrl-0 = <&qspi_pins>; - pinctrl-names = "default"; - - status = "okay"; - - flash: flash@0 { - compatible = "spansion,s25fl512s", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <30000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - spi-cpha; - spi-cpol; - m25p,fast-read; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "loader"; - reg = <0x00000000 0x00080000>; - read-only; - }; - partition@80000 { - label = "uboot"; - reg = <0x00080000 0x00040000>; - read-only; - }; - partition@c0000 { - label = "uboot-env"; - reg = <0x000c0000 0x00040000>; - read-only; - }; - partition@100000 { - label = "flash"; - reg = <0x00100000 0x03f00000>; - }; - }; - }; -}; - -&scifa0 { - pinctrl-0 = <&scifa0_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&scif_clk { - clock-frequency = <14745600>; -}; - -&sdhi0 { - pinctrl-0 = <&sdhi0_pins>; - pinctrl-names = "default"; - - vmmc-supply = <&vcc_sdhi0>; - cd-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&cpu0 { - cpu0-supply = <&vdd_dvfs>; -}; - -&iic2 { - status = "okay"; - pinctrl-0 = <&iic2_pins>; - pinctrl-names = "default"; - - clock-frequency = <100000>; - - hdmi@39 { - compatible = "adi,adv7511w"; - reg = <0x39>; - interrupt-parent = <&gpio1>; - interrupts = <15 IRQ_TYPE_LEVEL_LOW>; - clocks = <&osc4_clk>; - clock-names = "cec"; - - adi,input-depth = <8>; - adi,input-colorspace = "rgb"; - adi,input-clock = "1x"; - adi,input-style = <1>; - adi,input-justification = "evenly"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7511_in: endpoint { - remote-endpoint = <&du_out_rgb>; - }; - }; - - port@1 { - reg = <1>; - adv7511_out: endpoint { - remote-endpoint = <&hdmi_con_out>; - }; - }; - }; - }; -}; - -&iic3 { - pinctrl-names = "default"; - pinctrl-0 = <&iic3_pins &pmic_irq_pins>; - status = "okay"; - - pmic@58 { - compatible = "dlg,da9063"; - reg = <0x58>; - interrupt-parent = <&irqc0>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - - onkey { - compatible = "dlg,da9063-onkey"; - }; - - rtc { - compatible = "dlg,da9063-rtc"; - }; - - wdt { - compatible = "dlg,da9063-watchdog"; - }; - }; - - vdd_dvfs: regulator@68 { - compatible = "dlg,da9210"; - reg = <0x68>; - interrupt-parent = <&irqc0>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-boot-on; - regulator-always-on; - }; - - vdd: regulator@70 { - compatible = "dlg,da9210"; - reg = <0x70>; - interrupt-parent = <&irqc0>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-boot-on; - regulator-always-on; - }; -}; - -&pci0 { - status = "okay"; - pinctrl-0 = <&usb0_pins>; - pinctrl-names = "default"; -}; - -&usbphy { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/r8a7790.dtsi b/sys/gnu/dts/arm/r8a7790.dtsi deleted file mode 100644 index 334ba19769b..00000000000 --- a/sys/gnu/dts/arm/r8a7790.dtsi +++ /dev/null @@ -1,1873 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the R-Car H2 (R8A77900) SoC - * - * Copyright (C) 2015 Renesas Electronics Corporation - * Copyright (C) 2013-2014 Renesas Solutions Corp. - * Copyright (C) 2014 Cogent Embedded Inc. - */ - -#include -#include -#include -#include - -/ { - compatible = "renesas,r8a7790"; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &iic0; - i2c5 = &iic1; - i2c6 = &iic2; - i2c7 = &iic3; - spi0 = &qspi; - spi1 = &msiof0; - spi2 = &msiof1; - spi3 = &msiof2; - spi4 = &msiof3; - vin0 = &vin0; - vin1 = &vin1; - vin2 = &vin2; - vin3 = &vin3; - }; - - /* - * The external audio clocks are configured as 0 Hz fixed frequency - * clocks by default. - * Boards that provide audio clocks should override them. - */ - audio_clk_a: audio_clk_a { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - audio_clk_b: audio_clk_b { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - audio_clk_c: audio_clk_c { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - /* External CAN clock */ - can_clk: can { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "renesas,apmu"; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0>; - clock-frequency = <1300000000>; - clocks = <&cpg CPG_CORE R8A7790_CLK_Z>; - power-domains = <&sysc R8A7790_PD_CA15_CPU0>; - next-level-cache = <&L2_CA15>; - capacity-dmips-mhz = <1024>; - voltage-tolerance = <1>; /* 1% */ - clock-latency = <300000>; /* 300 us */ - - /* kHz - uV - OPPs unknown yet */ - operating-points = <1400000 1000000>, - <1225000 1000000>, - <1050000 1000000>, - < 875000 1000000>, - < 700000 1000000>, - < 350000 1000000>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <1>; - clock-frequency = <1300000000>; - clocks = <&cpg CPG_CORE R8A7790_CLK_Z>; - power-domains = <&sysc R8A7790_PD_CA15_CPU1>; - next-level-cache = <&L2_CA15>; - capacity-dmips-mhz = <1024>; - voltage-tolerance = <1>; /* 1% */ - clock-latency = <300000>; /* 300 us */ - - /* kHz - uV - OPPs unknown yet */ - operating-points = <1400000 1000000>, - <1225000 1000000>, - <1050000 1000000>, - < 875000 1000000>, - < 700000 1000000>, - < 350000 1000000>; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <2>; - clock-frequency = <1300000000>; - clocks = <&cpg CPG_CORE R8A7790_CLK_Z>; - power-domains = <&sysc R8A7790_PD_CA15_CPU2>; - next-level-cache = <&L2_CA15>; - capacity-dmips-mhz = <1024>; - voltage-tolerance = <1>; /* 1% */ - clock-latency = <300000>; /* 300 us */ - - /* kHz - uV - OPPs unknown yet */ - operating-points = <1400000 1000000>, - <1225000 1000000>, - <1050000 1000000>, - < 875000 1000000>, - < 700000 1000000>, - < 350000 1000000>; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <3>; - clock-frequency = <1300000000>; - clocks = <&cpg CPG_CORE R8A7790_CLK_Z>; - power-domains = <&sysc R8A7790_PD_CA15_CPU3>; - next-level-cache = <&L2_CA15>; - capacity-dmips-mhz = <1024>; - voltage-tolerance = <1>; /* 1% */ - clock-latency = <300000>; /* 300 us */ - - /* kHz - uV - OPPs unknown yet */ - operating-points = <1400000 1000000>, - <1225000 1000000>, - <1050000 1000000>, - < 875000 1000000>, - < 700000 1000000>, - < 350000 1000000>; - }; - - cpu4: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x100>; - clock-frequency = <780000000>; - clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>; - power-domains = <&sysc R8A7790_PD_CA7_CPU0>; - next-level-cache = <&L2_CA7>; - capacity-dmips-mhz = <539>; - }; - - cpu5: cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x101>; - clock-frequency = <780000000>; - clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>; - power-domains = <&sysc R8A7790_PD_CA7_CPU1>; - next-level-cache = <&L2_CA7>; - capacity-dmips-mhz = <539>; - }; - - cpu6: cpu@102 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x102>; - clock-frequency = <780000000>; - clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>; - power-domains = <&sysc R8A7790_PD_CA7_CPU2>; - next-level-cache = <&L2_CA7>; - capacity-dmips-mhz = <539>; - }; - - cpu7: cpu@103 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x103>; - clock-frequency = <780000000>; - clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>; - power-domains = <&sysc R8A7790_PD_CA7_CPU3>; - next-level-cache = <&L2_CA7>; - capacity-dmips-mhz = <539>; - }; - - L2_CA15: cache-controller-0 { - compatible = "cache"; - power-domains = <&sysc R8A7790_PD_CA15_SCU>; - cache-unified; - cache-level = <2>; - }; - - L2_CA7: cache-controller-1 { - compatible = "cache"; - power-domains = <&sysc R8A7790_PD_CA7_SCU>; - cache-unified; - cache-level = <2>; - }; - }; - - /* External root clock */ - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - /* External PCIe clock - can be overridden by the board */ - pcie_bus_clk: pcie_bus { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - pmu-0 { - compatible = "arm,cortex-a15-pmu"; - interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; - }; - - pmu-1 { - compatible = "arm,cortex-a7-pmu"; - interrupts-extended = <&gic GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; - }; - - /* External SCIF clock */ - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - soc { - compatible = "simple-bus"; - interrupt-parent = <&gic>; - - #address-cells = <2>; - #size-cells = <2>; - ranges; - - rwdt: watchdog@e6020000 { - compatible = "renesas,r8a7790-wdt", - "renesas,rcar-gen2-wdt"; - reg = <0 0xe6020000 0 0x0c>; - clocks = <&cpg CPG_MOD 402>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 402>; - status = "disabled"; - }; - - gpio0: gpio@e6050000 { - compatible = "renesas,gpio-r8a7790", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6050000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 0 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 912>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 912>; - }; - - gpio1: gpio@e6051000 { - compatible = "renesas,gpio-r8a7790", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6051000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 32 30>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 911>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 911>; - }; - - gpio2: gpio@e6052000 { - compatible = "renesas,gpio-r8a7790", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6052000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 64 30>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 910>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 910>; - }; - - gpio3: gpio@e6053000 { - compatible = "renesas,gpio-r8a7790", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6053000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 96 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 909>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 909>; - }; - - gpio4: gpio@e6054000 { - compatible = "renesas,gpio-r8a7790", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6054000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 128 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 908>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 908>; - }; - - gpio5: gpio@e6055000 { - compatible = "renesas,gpio-r8a7790", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6055000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 160 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 907>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 907>; - }; - - pfc: pin-controller@e6060000 { - compatible = "renesas,pfc-r8a7790"; - reg = <0 0xe6060000 0 0x250>; - }; - - cpg: clock-controller@e6150000 { - compatible = "renesas,r8a7790-cpg-mssr"; - reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk>, <&usb_extal_clk>; - clock-names = "extal", "usb_extal"; - #clock-cells = <2>; - #power-domain-cells = <0>; - #reset-cells = <1>; - }; - - apmu@e6151000 { - compatible = "renesas,r8a7790-apmu", "renesas,apmu"; - reg = <0 0xe6151000 0 0x188>; - cpus = <&cpu4 &cpu5 &cpu6 &cpu7>; - }; - - apmu@e6152000 { - compatible = "renesas,r8a7790-apmu", "renesas,apmu"; - reg = <0 0xe6152000 0 0x188>; - cpus = <&cpu0 &cpu1 &cpu2 &cpu3>; - }; - - rst: reset-controller@e6160000 { - compatible = "renesas,r8a7790-rst"; - reg = <0 0xe6160000 0 0x0100>; - }; - - sysc: system-controller@e6180000 { - compatible = "renesas,r8a7790-sysc"; - reg = <0 0xe6180000 0 0x0200>; - #power-domain-cells = <1>; - }; - - irqc0: interrupt-controller@e61c0000 { - compatible = "renesas,irqc-r8a7790", "renesas,irqc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0 0xe61c0000 0 0x200>; - interrupts = , - , - , - ; - clocks = <&cpg CPG_MOD 407>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 407>; - }; - - thermal: thermal@e61f0000 { - compatible = "renesas,thermal-r8a7790", - "renesas,rcar-gen2-thermal", - "renesas,rcar-thermal"; - reg = <0 0xe61f0000 0 0x10>, <0 0xe61f0100 0 0x38>; - interrupts = ; - clocks = <&cpg CPG_MOD 522>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 522>; - #thermal-sensor-cells = <0>; - }; - - ipmmu_sy0: mmu@e6280000 { - compatible = "renesas,ipmmu-r8a7790", - "renesas,ipmmu-vmsa"; - reg = <0 0xe6280000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_sy1: mmu@e6290000 { - compatible = "renesas,ipmmu-r8a7790", - "renesas,ipmmu-vmsa"; - reg = <0 0xe6290000 0 0x1000>; - interrupts = ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_ds: mmu@e6740000 { - compatible = "renesas,ipmmu-r8a7790", - "renesas,ipmmu-vmsa"; - reg = <0 0xe6740000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_mp: mmu@ec680000 { - compatible = "renesas,ipmmu-r8a7790", - "renesas,ipmmu-vmsa"; - reg = <0 0xec680000 0 0x1000>; - interrupts = ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_mx: mmu@fe951000 { - compatible = "renesas,ipmmu-r8a7790", - "renesas,ipmmu-vmsa"; - reg = <0 0xfe951000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_rt: mmu@ffc80000 { - compatible = "renesas,ipmmu-r8a7790", - "renesas,ipmmu-vmsa"; - reg = <0 0xffc80000 0 0x1000>; - interrupts = ; - #iommu-cells = <1>; - status = "disabled"; - }; - - icram0: sram@e63a0000 { - compatible = "mmio-sram"; - reg = <0 0xe63a0000 0 0x12000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0xe63a0000 0x12000>; - }; - - icram1: sram@e63c0000 { - compatible = "mmio-sram"; - reg = <0 0xe63c0000 0 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0xe63c0000 0x1000>; - - smp-sram@0 { - compatible = "renesas,smp-sram"; - reg = <0 0x100>; - }; - }; - - i2c0: i2c@e6508000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7790", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6508000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 931>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 931>; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c1: i2c@e6518000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7790", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6518000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 930>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 930>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c2: i2c@e6530000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7790", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6530000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 929>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 929>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c3: i2c@e6540000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7790", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6540000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 928>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 928>; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - iic0: i2c@e6500000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7790", - "renesas,rcar-gen2-iic", - "renesas,rmobile-iic"; - reg = <0 0xe6500000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 318>; - dmas = <&dmac0 0x61>, <&dmac0 0x62>, - <&dmac1 0x61>, <&dmac1 0x62>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 318>; - status = "disabled"; - }; - - iic1: i2c@e6510000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7790", - "renesas,rcar-gen2-iic", - "renesas,rmobile-iic"; - reg = <0 0xe6510000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 323>; - dmas = <&dmac0 0x65>, <&dmac0 0x66>, - <&dmac1 0x65>, <&dmac1 0x66>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 323>; - status = "disabled"; - }; - - iic2: i2c@e6520000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7790", - "renesas,rcar-gen2-iic", - "renesas,rmobile-iic"; - reg = <0 0xe6520000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 300>; - dmas = <&dmac0 0x69>, <&dmac0 0x6a>, - <&dmac1 0x69>, <&dmac1 0x6a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 300>; - status = "disabled"; - }; - - iic3: i2c@e60b0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7790", - "renesas,rcar-gen2-iic", - "renesas,rmobile-iic"; - reg = <0 0xe60b0000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 926>; - dmas = <&dmac0 0x77>, <&dmac0 0x78>, - <&dmac1 0x77>, <&dmac1 0x78>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 926>; - status = "disabled"; - }; - - hsusb: usb@e6590000 { - compatible = "renesas,usbhs-r8a7790", - "renesas,rcar-gen2-usbhs"; - reg = <0 0xe6590000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 704>; - dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, - <&usb_dmac1 0>, <&usb_dmac1 1>; - dma-names = "ch0", "ch1", "ch2", "ch3"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 704>; - renesas,buswait = <4>; - phys = <&usb0 1>; - phy-names = "usb"; - status = "disabled"; - }; - - usbphy: usb-phy@e6590100 { - compatible = "renesas,usb-phy-r8a7790", - "renesas,rcar-gen2-usb-phy"; - reg = <0 0xe6590100 0 0x100>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cpg CPG_MOD 704>; - clock-names = "usbhs"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 704>; - status = "disabled"; - - usb0: usb-channel@0 { - reg = <0>; - #phy-cells = <1>; - }; - usb2: usb-channel@2 { - reg = <2>; - #phy-cells = <1>; - }; - }; - - usb_dmac0: dma-controller@e65a0000 { - compatible = "renesas,r8a7790-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65a0000 0 0x100>; - interrupts = , - ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 330>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 330>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - usb_dmac1: dma-controller@e65b0000 { - compatible = "renesas,r8a7790-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65b0000 0 0x100>; - interrupts = , - ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 331>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 331>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - dmac0: dma-controller@e6700000 { - compatible = "renesas,dmac-r8a7790", - "renesas,rcar-dmac"; - reg = <0 0xe6700000 0 0x20000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14"; - clocks = <&cpg CPG_MOD 219>; - clock-names = "fck"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 219>; - #dma-cells = <1>; - dma-channels = <15>; - }; - - dmac1: dma-controller@e6720000 { - compatible = "renesas,dmac-r8a7790", - "renesas,rcar-dmac"; - reg = <0 0xe6720000 0 0x20000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14"; - clocks = <&cpg CPG_MOD 218>; - clock-names = "fck"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 218>; - #dma-cells = <1>; - dma-channels = <15>; - }; - - avb: ethernet@e6800000 { - compatible = "renesas,etheravb-r8a7790", - "renesas,etheravb-rcar-gen2"; - reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; - interrupts = ; - clocks = <&cpg CPG_MOD 812>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 812>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - qspi: spi@e6b10000 { - compatible = "renesas,qspi-r8a7790", "renesas,qspi"; - reg = <0 0xe6b10000 0 0x2c>; - interrupts = ; - clocks = <&cpg CPG_MOD 917>; - dmas = <&dmac0 0x17>, <&dmac0 0x18>, - <&dmac1 0x17>, <&dmac1 0x18>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 917>; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - scifa0: serial@e6c40000 { - compatible = "renesas,scifa-r8a7790", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c40000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 204>; - clock-names = "fck"; - dmas = <&dmac0 0x21>, <&dmac0 0x22>, - <&dmac1 0x21>, <&dmac1 0x22>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 204>; - status = "disabled"; - }; - - scifa1: serial@e6c50000 { - compatible = "renesas,scifa-r8a7790", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c50000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 203>; - clock-names = "fck"; - dmas = <&dmac0 0x25>, <&dmac0 0x26>, - <&dmac1 0x25>, <&dmac1 0x26>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 203>; - status = "disabled"; - }; - - scifa2: serial@e6c60000 { - compatible = "renesas,scifa-r8a7790", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c60000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 202>; - clock-names = "fck"; - dmas = <&dmac0 0x27>, <&dmac0 0x28>, - <&dmac1 0x27>, <&dmac1 0x28>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 202>; - status = "disabled"; - }; - - scifb0: serial@e6c20000 { - compatible = "renesas,scifb-r8a7790", - "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6c20000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 206>; - clock-names = "fck"; - dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, - <&dmac1 0x3d>, <&dmac1 0x3e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 206>; - status = "disabled"; - }; - - scifb1: serial@e6c30000 { - compatible = "renesas,scifb-r8a7790", - "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6c30000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 207>; - clock-names = "fck"; - dmas = <&dmac0 0x19>, <&dmac0 0x1a>, - <&dmac1 0x19>, <&dmac1 0x1a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 207>; - status = "disabled"; - }; - - scifb2: serial@e6ce0000 { - compatible = "renesas,scifb-r8a7790", - "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6ce0000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 216>; - clock-names = "fck"; - dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, - <&dmac1 0x1d>, <&dmac1 0x1e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 216>; - status = "disabled"; - }; - - scif0: serial@e6e60000 { - compatible = "renesas,scif-r8a7790", - "renesas,rcar-gen2-scif", - "renesas,scif"; - reg = <0 0xe6e60000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 721>, - <&cpg CPG_CORE R8A7790_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x29>, <&dmac0 0x2a>, - <&dmac1 0x29>, <&dmac1 0x2a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 721>; - status = "disabled"; - }; - - scif1: serial@e6e68000 { - compatible = "renesas,scif-r8a7790", - "renesas,rcar-gen2-scif", - "renesas,scif"; - reg = <0 0xe6e68000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 720>, - <&cpg CPG_CORE R8A7790_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, - <&dmac1 0x2d>, <&dmac1 0x2e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 720>; - status = "disabled"; - }; - - scif2: serial@e6e56000 { - compatible = "renesas,scif-r8a7790", - "renesas,rcar-gen2-scif", - "renesas,scif"; - reg = <0 0xe6e56000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 310>, - <&cpg CPG_CORE R8A7790_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, - <&dmac1 0x2b>, <&dmac1 0x2c>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 310>; - status = "disabled"; - }; - - hscif0: serial@e62c0000 { - compatible = "renesas,hscif-r8a7790", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62c0000 0 96>; - interrupts = ; - clocks = <&cpg CPG_MOD 717>, - <&cpg CPG_CORE R8A7790_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x39>, <&dmac0 0x3a>, - <&dmac1 0x39>, <&dmac1 0x3a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 717>; - status = "disabled"; - }; - - hscif1: serial@e62c8000 { - compatible = "renesas,hscif-r8a7790", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62c8000 0 96>; - interrupts = ; - clocks = <&cpg CPG_MOD 716>, - <&cpg CPG_CORE R8A7790_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, - <&dmac1 0x4d>, <&dmac1 0x4e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 716>; - status = "disabled"; - }; - - msiof0: spi@e6e20000 { - compatible = "renesas,msiof-r8a7790", - "renesas,rcar-gen2-msiof"; - reg = <0 0xe6e20000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 0>; - dmas = <&dmac0 0x51>, <&dmac0 0x52>, - <&dmac1 0x51>, <&dmac1 0x52>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 0>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof1: spi@e6e10000 { - compatible = "renesas,msiof-r8a7790", - "renesas,rcar-gen2-msiof"; - reg = <0 0xe6e10000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 208>; - dmas = <&dmac0 0x55>, <&dmac0 0x56>, - <&dmac1 0x55>, <&dmac1 0x56>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 208>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof2: spi@e6e00000 { - compatible = "renesas,msiof-r8a7790", - "renesas,rcar-gen2-msiof"; - reg = <0 0xe6e00000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 205>; - dmas = <&dmac0 0x41>, <&dmac0 0x42>, - <&dmac1 0x41>, <&dmac1 0x42>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 205>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof3: spi@e6c90000 { - compatible = "renesas,msiof-r8a7790", - "renesas,rcar-gen2-msiof"; - reg = <0 0xe6c90000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 215>; - dmas = <&dmac0 0x45>, <&dmac0 0x46>, - <&dmac1 0x45>, <&dmac1 0x46>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 215>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - can0: can@e6e80000 { - compatible = "renesas,can-r8a7790", - "renesas,rcar-gen2-can"; - reg = <0 0xe6e80000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 916>, - <&cpg CPG_CORE R8A7790_CLK_RCAN>, <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 916>; - status = "disabled"; - }; - - can1: can@e6e88000 { - compatible = "renesas,can-r8a7790", - "renesas,rcar-gen2-can"; - reg = <0 0xe6e88000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 915>, - <&cpg CPG_CORE R8A7790_CLK_RCAN>, <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 915>; - status = "disabled"; - }; - - vin0: video@e6ef0000 { - compatible = "renesas,vin-r8a7790", - "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef0000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 811>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 811>; - status = "disabled"; - }; - - vin1: video@e6ef1000 { - compatible = "renesas,vin-r8a7790", - "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef1000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 810>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 810>; - status = "disabled"; - }; - - vin2: video@e6ef2000 { - compatible = "renesas,vin-r8a7790", - "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef2000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 809>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 809>; - status = "disabled"; - }; - - vin3: video@e6ef3000 { - compatible = "renesas,vin-r8a7790", - "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef3000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 808>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 808>; - status = "disabled"; - }; - - rcar_sound: sound@ec500000 { - /* - * #sound-dai-cells is required - * - * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; - * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; - */ - compatible = "renesas,rcar_sound-r8a7790", - "renesas,rcar_sound-gen2"; - reg = <0 0xec500000 0 0x1000>, /* SCU */ - <0 0xec5a0000 0 0x100>, /* ADG */ - <0 0xec540000 0 0x1000>, /* SSIU */ - <0 0xec541000 0 0x280>, /* SSI */ - <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ - reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; - - clocks = <&cpg CPG_MOD 1005>, - <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, - <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, - <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, - <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, - <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, - <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, - <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, - <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, - <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, - <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, - <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, - <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, - <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, - <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, - <&cpg CPG_CORE R8A7790_CLK_M2>; - clock-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", - "ssi.5", "ssi.4", "ssi.3", "ssi.2", - "ssi.1", "ssi.0", - "src.9", "src.8", "src.7", "src.6", - "src.5", "src.4", "src.3", "src.2", - "src.1", "src.0", - "ctu.0", "ctu.1", - "mix.0", "mix.1", - "dvc.0", "dvc.1", - "clk_a", "clk_b", "clk_c", "clk_i"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 1005>, - <&cpg 1006>, <&cpg 1007>, - <&cpg 1008>, <&cpg 1009>, - <&cpg 1010>, <&cpg 1011>, - <&cpg 1012>, <&cpg 1013>, - <&cpg 1014>, <&cpg 1015>; - reset-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", - "ssi.5", "ssi.4", "ssi.3", "ssi.2", - "ssi.1", "ssi.0"; - - status = "disabled"; - - rcar_sound,dvc { - dvc0: dvc-0 { - dmas = <&audma1 0xbc>; - dma-names = "tx"; - }; - dvc1: dvc-1 { - dmas = <&audma1 0xbe>; - dma-names = "tx"; - }; - }; - - rcar_sound,mix { - mix0: mix-0 { }; - mix1: mix-1 { }; - }; - - rcar_sound,ctu { - ctu00: ctu-0 { }; - ctu01: ctu-1 { }; - ctu02: ctu-2 { }; - ctu03: ctu-3 { }; - ctu10: ctu-4 { }; - ctu11: ctu-5 { }; - ctu12: ctu-6 { }; - ctu13: ctu-7 { }; - }; - - rcar_sound,src { - src0: src-0 { - interrupts = ; - dmas = <&audma0 0x85>, <&audma1 0x9a>; - dma-names = "rx", "tx"; - }; - src1: src-1 { - interrupts = ; - dmas = <&audma0 0x87>, <&audma1 0x9c>; - dma-names = "rx", "tx"; - }; - src2: src-2 { - interrupts = ; - dmas = <&audma0 0x89>, <&audma1 0x9e>; - dma-names = "rx", "tx"; - }; - src3: src-3 { - interrupts = ; - dmas = <&audma0 0x8b>, <&audma1 0xa0>; - dma-names = "rx", "tx"; - }; - src4: src-4 { - interrupts = ; - dmas = <&audma0 0x8d>, <&audma1 0xb0>; - dma-names = "rx", "tx"; - }; - src5: src-5 { - interrupts = ; - dmas = <&audma0 0x8f>, <&audma1 0xb2>; - dma-names = "rx", "tx"; - }; - src6: src-6 { - interrupts = ; - dmas = <&audma0 0x91>, <&audma1 0xb4>; - dma-names = "rx", "tx"; - }; - src7: src-7 { - interrupts = ; - dmas = <&audma0 0x93>, <&audma1 0xb6>; - dma-names = "rx", "tx"; - }; - src8: src-8 { - interrupts = ; - dmas = <&audma0 0x95>, <&audma1 0xb8>; - dma-names = "rx", "tx"; - }; - src9: src-9 { - interrupts = ; - dmas = <&audma0 0x97>, <&audma1 0xba>; - dma-names = "rx", "tx"; - }; - }; - - rcar_sound,ssi { - ssi0: ssi-0 { - interrupts = ; - dmas = <&audma0 0x01>, <&audma1 0x02>, - <&audma0 0x15>, <&audma1 0x16>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi1: ssi-1 { - interrupts = ; - dmas = <&audma0 0x03>, <&audma1 0x04>, - <&audma0 0x49>, <&audma1 0x4a>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi2: ssi-2 { - interrupts = ; - dmas = <&audma0 0x05>, <&audma1 0x06>, - <&audma0 0x63>, <&audma1 0x64>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi3: ssi-3 { - interrupts = ; - dmas = <&audma0 0x07>, <&audma1 0x08>, - <&audma0 0x6f>, <&audma1 0x70>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi4: ssi-4 { - interrupts = ; - dmas = <&audma0 0x09>, <&audma1 0x0a>, - <&audma0 0x71>, <&audma1 0x72>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi5: ssi-5 { - interrupts = ; - dmas = <&audma0 0x0b>, <&audma1 0x0c>, - <&audma0 0x73>, <&audma1 0x74>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi6: ssi-6 { - interrupts = ; - dmas = <&audma0 0x0d>, <&audma1 0x0e>, - <&audma0 0x75>, <&audma1 0x76>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi7: ssi-7 { - interrupts = ; - dmas = <&audma0 0x0f>, <&audma1 0x10>, - <&audma0 0x79>, <&audma1 0x7a>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi8: ssi-8 { - interrupts = ; - dmas = <&audma0 0x11>, <&audma1 0x12>, - <&audma0 0x7b>, <&audma1 0x7c>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi9: ssi-9 { - interrupts = ; - dmas = <&audma0 0x13>, <&audma1 0x14>, - <&audma0 0x7d>, <&audma1 0x7e>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - }; - }; - - audma0: dma-controller@ec700000 { - compatible = "renesas,dmac-r8a7790", - "renesas,rcar-dmac"; - reg = <0 0xec700000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12"; - clocks = <&cpg CPG_MOD 502>; - clock-names = "fck"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 502>; - #dma-cells = <1>; - dma-channels = <13>; - }; - - audma1: dma-controller@ec720000 { - compatible = "renesas,dmac-r8a7790", - "renesas,rcar-dmac"; - reg = <0 0xec720000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12"; - clocks = <&cpg CPG_MOD 501>; - clock-names = "fck"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 501>; - #dma-cells = <1>; - dma-channels = <13>; - }; - - xhci: usb@ee000000 { - compatible = "renesas,xhci-r8a7790", - "renesas,rcar-gen2-xhci"; - reg = <0 0xee000000 0 0xc00>; - interrupts = ; - clocks = <&cpg CPG_MOD 328>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 328>; - phys = <&usb2 1>; - phy-names = "usb"; - status = "disabled"; - }; - - pci0: pci@ee090000 { - compatible = "renesas,pci-r8a7790", - "renesas,pci-rcar-gen2"; - device_type = "pci"; - reg = <0 0xee090000 0 0xc00>, - <0 0xee080000 0 0x1100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 703>; - status = "disabled"; - - bus-range = <0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>; - interrupt-map-mask = <0xf800 0 0 0x7>; - interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, - <0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, - <0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; - - usb@1,0 { - reg = <0x800 0 0 0 0>; - phys = <&usb0 0>; - phy-names = "usb"; - }; - - usb@2,0 { - reg = <0x1000 0 0 0 0>; - phys = <&usb0 0>; - phy-names = "usb"; - }; - }; - - pci1: pci@ee0b0000 { - compatible = "renesas,pci-r8a7790", - "renesas,pci-rcar-gen2"; - device_type = "pci"; - reg = <0 0xee0b0000 0 0xc00>, - <0 0xee0a0000 0 0x1100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 703>; - status = "disabled"; - - bus-range = <1 1>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x02000000 0 0xee0a0000 0 0xee0a0000 0 0x00010000>; - interrupt-map-mask = <0xf800 0 0 0x7>; - interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, - <0x0800 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, - <0x1000 0 0 2 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; - }; - - pci2: pci@ee0d0000 { - compatible = "renesas,pci-r8a7790", - "renesas,pci-rcar-gen2"; - device_type = "pci"; - clocks = <&cpg CPG_MOD 703>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 703>; - reg = <0 0xee0d0000 0 0xc00>, - <0 0xee0c0000 0 0x1100>; - interrupts = ; - status = "disabled"; - - bus-range = <2 2>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>; - interrupt-map-mask = <0xf800 0 0 0x7>; - interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, - <0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, - <0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; - - usb@1,0 { - reg = <0x20800 0 0 0 0>; - phys = <&usb2 0>; - phy-names = "usb"; - }; - - usb@2,0 { - reg = <0x21000 0 0 0 0>; - phys = <&usb2 0>; - phy-names = "usb"; - }; - }; - - sdhi0: sd@ee100000 { - compatible = "renesas,sdhi-r8a7790", - "renesas,rcar-gen2-sdhi"; - reg = <0 0xee100000 0 0x328>; - interrupts = ; - clocks = <&cpg CPG_MOD 314>; - dmas = <&dmac0 0xcd>, <&dmac0 0xce>, - <&dmac1 0xcd>, <&dmac1 0xce>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <195000000>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 314>; - status = "disabled"; - }; - - sdhi1: sd@ee120000 { - compatible = "renesas,sdhi-r8a7790", - "renesas,rcar-gen2-sdhi"; - reg = <0 0xee120000 0 0x328>; - interrupts = ; - clocks = <&cpg CPG_MOD 313>; - dmas = <&dmac0 0xc9>, <&dmac0 0xca>, - <&dmac1 0xc9>, <&dmac1 0xca>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <195000000>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 313>; - status = "disabled"; - }; - - sdhi2: sd@ee140000 { - compatible = "renesas,sdhi-r8a7790", - "renesas,rcar-gen2-sdhi"; - reg = <0 0xee140000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 312>; - dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, - <&dmac1 0xc1>, <&dmac1 0xc2>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <97500000>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 312>; - status = "disabled"; - }; - - sdhi3: sd@ee160000 { - compatible = "renesas,sdhi-r8a7790", - "renesas,rcar-gen2-sdhi"; - reg = <0 0xee160000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 311>; - dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, - <&dmac1 0xd3>, <&dmac1 0xd4>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <97500000>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 311>; - status = "disabled"; - }; - - mmcif0: mmc@ee200000 { - compatible = "renesas,mmcif-r8a7790", - "renesas,sh-mmcif"; - reg = <0 0xee200000 0 0x80>; - interrupts = ; - clocks = <&cpg CPG_MOD 315>; - dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, - <&dmac1 0xd1>, <&dmac1 0xd2>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 315>; - reg-io-width = <4>; - status = "disabled"; - max-frequency = <97500000>; - }; - - mmcif1: mmc@ee220000 { - compatible = "renesas,mmcif-r8a7790", - "renesas,sh-mmcif"; - reg = <0 0xee220000 0 0x80>; - interrupts = ; - clocks = <&cpg CPG_MOD 305>; - dmas = <&dmac0 0xe1>, <&dmac0 0xe2>, - <&dmac1 0xe1>, <&dmac1 0xe2>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 305>; - reg-io-width = <4>; - status = "disabled"; - max-frequency = <97500000>; - }; - - sata0: sata@ee300000 { - compatible = "renesas,sata-r8a7790", - "renesas,rcar-gen2-sata"; - reg = <0 0xee300000 0 0x200000>; - interrupts = ; - clocks = <&cpg CPG_MOD 815>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 815>; - status = "disabled"; - }; - - sata1: sata@ee500000 { - compatible = "renesas,sata-r8a7790", - "renesas,rcar-gen2-sata"; - reg = <0 0xee500000 0 0x200000>; - interrupts = ; - clocks = <&cpg CPG_MOD 814>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 814>; - status = "disabled"; - }; - - ether: ethernet@ee700000 { - compatible = "renesas,ether-r8a7790", - "renesas,rcar-gen2-ether"; - reg = <0 0xee700000 0 0x400>; - interrupts = ; - clocks = <&cpg CPG_MOD 813>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 813>; - phy-mode = "rmii"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - gic: interrupt-controller@f1001000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>, - <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 408>; - clock-names = "clk"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 408>; - }; - - pciec: pcie@fe000000 { - compatible = "renesas,pcie-r8a7790", - "renesas,pcie-rcar-gen2"; - reg = <0 0xfe000000 0 0x80000>; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x00 0xff>; - device_type = "pci"; - ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, - <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, - <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, - <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>, - <0x43000000 1 0x80000000 1 0x80000000 0 0x80000000>; - interrupts = , - , - ; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; - clock-names = "pcie", "pcie_bus"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 319>; - status = "disabled"; - }; - - vsp@fe920000 { - compatible = "renesas,vsp1"; - reg = <0 0xfe920000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 130>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 130>; - }; - - vsp@fe928000 { - compatible = "renesas,vsp1"; - reg = <0 0xfe928000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 131>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 131>; - }; - - vsp@fe930000 { - compatible = "renesas,vsp1"; - reg = <0 0xfe930000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 128>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 128>; - }; - - vsp@fe938000 { - compatible = "renesas,vsp1"; - reg = <0 0xfe938000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 127>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 127>; - }; - - fdp1@fe940000 { - compatible = "renesas,fdp1"; - reg = <0 0xfe940000 0 0x2400>; - interrupts = ; - clocks = <&cpg CPG_MOD 119>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 119>; - }; - - fdp1@fe944000 { - compatible = "renesas,fdp1"; - reg = <0 0xfe944000 0 0x2400>; - interrupts = ; - clocks = <&cpg CPG_MOD 118>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 118>; - }; - - fdp1@fe948000 { - compatible = "renesas,fdp1"; - reg = <0 0xfe948000 0 0x2400>; - interrupts = ; - clocks = <&cpg CPG_MOD 117>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 117>; - }; - - jpu: jpeg-codec@fe980000 { - compatible = "renesas,jpu-r8a7790", - "renesas,rcar-gen2-jpu"; - reg = <0 0xfe980000 0 0x10300>; - interrupts = ; - clocks = <&cpg CPG_MOD 106>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 106>; - }; - - du: display@feb00000 { - compatible = "renesas,du-r8a7790"; - reg = <0 0xfeb00000 0 0x70000>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, - <&cpg CPG_MOD 722>; - clock-names = "du.0", "du.1", "du.2"; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - du_out_rgb: endpoint { - }; - }; - port@1 { - reg = <1>; - du_out_lvds0: endpoint { - remote-endpoint = <&lvds0_in>; - }; - }; - port@2 { - reg = <2>; - du_out_lvds1: endpoint { - remote-endpoint = <&lvds1_in>; - }; - }; - }; - }; - - lvds0: lvds@feb90000 { - compatible = "renesas,r8a7790-lvds"; - reg = <0 0xfeb90000 0 0x1c>; - clocks = <&cpg CPG_MOD 726>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 726>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - lvds0_in: endpoint { - remote-endpoint = <&du_out_lvds0>; - }; - }; - port@1 { - reg = <1>; - lvds0_out: endpoint { - }; - }; - }; - }; - - lvds1: lvds@feb94000 { - compatible = "renesas,r8a7790-lvds"; - reg = <0 0xfeb94000 0 0x1c>; - clocks = <&cpg CPG_MOD 725>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 725>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - lvds1_in: endpoint { - remote-endpoint = <&du_out_lvds1>; - }; - }; - port@1 { - reg = <1>; - lvds1_out: endpoint { - }; - }; - }; - }; - - prr: chipid@ff000044 { - compatible = "renesas,prr"; - reg = <0 0xff000044 0 4>; - }; - - cmt0: timer@ffca0000 { - compatible = "renesas,r8a7790-cmt0", - "renesas,rcar-gen2-cmt0"; - reg = <0 0xffca0000 0 0x1004>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 124>; - clock-names = "fck"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 124>; - - status = "disabled"; - }; - - cmt1: timer@e6130000 { - compatible = "renesas,r8a7790-cmt1", - "renesas,rcar-gen2-cmt1"; - reg = <0 0xe6130000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 329>; - clock-names = "fck"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 329>; - - status = "disabled"; - }; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - - thermal-sensors = <&thermal>; - - trips { - cpu-crit { - temperature = <95000>; - hysteresis = <0>; - type = "critical"; - }; - }; - cooling-maps { - }; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; - }; - - /* External USB clock - can be overridden by the board */ - usb_extal_clk: usb_extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <48000000>; - }; -}; diff --git a/sys/gnu/dts/arm/r8a7791-koelsch.dts b/sys/gnu/dts/arm/r8a7791-koelsch.dts deleted file mode 100644 index 2b096d5e06f..00000000000 --- a/sys/gnu/dts/arm/r8a7791-koelsch.dts +++ /dev/null @@ -1,901 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the Koelsch board - * - * Copyright (C) 2013 Renesas Electronics Corporation - * Copyright (C) 2013-2014 Renesas Solutions Corp. - * Copyright (C) 2014 Cogent Embedded, Inc. - */ - -/* - * SSI-AK4643 - * - * SW1: 1: AK4643 - * 2: CN22 - * 3: ADV7511 - * - * This command is required when Playback/Capture - * - * amixer set "LINEOUT Mixer DACL" on - * amixer set "DVC Out" 100% - * amixer set "DVC In" 100% - * - * You can use Mute - * - * amixer set "DVC Out Mute" on - * amixer set "DVC In Mute" on - * - * You can use Volume Ramp - * - * amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps" - * amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps" - * amixer set "DVC Out Ramp" on - * aplay xxx.wav & - * amixer set "DVC Out" 80% // Volume Down - * amixer set "DVC Out" 100% // Volume Up - */ - -/dts-v1/; -#include "r8a7791.dtsi" -#include -#include - -/ { - model = "Koelsch"; - compatible = "renesas,koelsch", "renesas,r8a7791"; - - aliases { - serial0 = &scif0; - serial1 = &scif1; - i2c9 = &gpioi2c1; - i2c10 = &gpioi2c2; - i2c11 = &gpioi2c4; - i2c12 = &i2cexio1; - i2c13 = &i2chdmi; - i2c14 = &i2cexio4; - }; - - chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; - stdout-path = "serial0:115200n8"; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0 0x40000000 0 0x40000000>; - }; - - memory@200000000 { - device_type = "memory"; - reg = <2 0x00000000 0 0x40000000>; - }; - - lbsc { - #address-cells = <1>; - #size-cells = <1>; - }; - - keyboard { - compatible = "gpio-keys"; - - key-1 { - gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW2-1"; - wakeup-source; - debounce-interval = <20>; - }; - key-2 { - gpios = <&gpio5 1 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW2-2"; - wakeup-source; - debounce-interval = <20>; - }; - key-3 { - gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW2-3"; - wakeup-source; - debounce-interval = <20>; - }; - key-4 { - gpios = <&gpio5 3 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW2-4"; - wakeup-source; - debounce-interval = <20>; - }; - key-a { - gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW30"; - wakeup-source; - debounce-interval = <20>; - }; - key-b { - gpios = <&gpio7 1 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW31"; - wakeup-source; - debounce-interval = <20>; - }; - key-c { - gpios = <&gpio7 2 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW32"; - wakeup-source; - debounce-interval = <20>; - }; - key-d { - gpios = <&gpio7 3 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW33"; - wakeup-source; - debounce-interval = <20>; - }; - key-e { - gpios = <&gpio7 4 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW34"; - wakeup-source; - debounce-interval = <20>; - }; - key-f { - gpios = <&gpio7 5 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW35"; - wakeup-source; - debounce-interval = <20>; - }; - key-g { - gpios = <&gpio7 6 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW36"; - wakeup-source; - debounce-interval = <20>; - }; - }; - - leds { - compatible = "gpio-leds"; - led6 { - gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>; - label = "LED6"; - }; - led7 { - gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; - label = "LED7"; - }; - led8 { - gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>; - label = "LED8"; - }; - }; - - vcc_sdhi0: regulator-vcc-sdhi0 { - compatible = "regulator-fixed"; - - regulator-name = "SDHI0 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&gpio7 17 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vccq_sdhi0: regulator-vccq-sdhi0 { - compatible = "regulator-gpio"; - - regulator-name = "SDHI0 VccQ"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>; - gpios-states = <1>; - states = <3300000 1>, <1800000 0>; - }; - - vcc_sdhi1: regulator-vcc-sdhi1 { - compatible = "regulator-fixed"; - - regulator-name = "SDHI1 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&gpio7 18 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vccq_sdhi1: regulator-vccq-sdhi1 { - compatible = "regulator-gpio"; - - regulator-name = "SDHI1 VccQ"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>; - gpios-states = <1>; - states = <3300000 1>, <1800000 0>; - }; - - vcc_sdhi2: regulator-vcc-sdhi2 { - compatible = "regulator-fixed"; - - regulator-name = "SDHI2 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&gpio7 19 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vccq_sdhi2: regulator-vccq-sdhi2 { - compatible = "regulator-gpio"; - - regulator-name = "SDHI2 VccQ"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>; - gpios-states = <1>; - states = <3300000 1>, <1800000 0>; - }; - - audio_clock: audio_clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <11289600>; - }; - - rsnd_ak4643: sound { - compatible = "simple-audio-card"; - - simple-audio-card,format = "left_j"; - simple-audio-card,bitclock-master = <&sndcodec>; - simple-audio-card,frame-master = <&sndcodec>; - - sndcpu: simple-audio-card,cpu { - sound-dai = <&rcar_sound>; - }; - - sndcodec: simple-audio-card,codec { - sound-dai = <&ak4643>; - clocks = <&audio_clock>; - }; - }; - - hdmi-in { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&adv7612_in>; - }; - }; - }; - - cec_clock: cec-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <12000000>; - }; - - hdmi-out { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_out: endpoint { - remote-endpoint = <&adv7511_out>; - }; - }; - }; - - x2_clk: x2-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <74250000>; - }; - - x13_clk: x13-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <148500000>; - }; - - gpioi2c1: i2c-9 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "i2c-gpio"; - status = "disabled"; - scl-gpios = <&gpio7 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio7 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <5>; - }; - - gpioi2c2: i2c-10 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "i2c-gpio"; - status = "disabled"; - scl-gpios = <&gpio2 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio2 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <5>; - }; - - gpioi2c4: i2c-11 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "i2c-gpio"; - status = "disabled"; - scl-gpios = <&gpio7 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio7 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <5>; - }; - - /* - * I2C1 is routed to EXIO connector B, pins 64 (SCL) + 66 (SDA). - * A fallback to GPIO is provided. - */ - i2cexio1: i2c-12 { - compatible = "i2c-demux-pinctrl"; - i2c-parent = <&i2c1>, <&gpioi2c1>; - i2c-bus-name = "i2c-exio1"; - #address-cells = <1>; - #size-cells = <0>; - }; - - /* - * A fallback to GPIO is provided for I2C2. - */ - i2chdmi: i2c-13 { - compatible = "i2c-demux-pinctrl"; - i2c-parent = <&i2c2>, <&gpioi2c2>; - i2c-bus-name = "i2c-hdmi"; - #address-cells = <1>; - #size-cells = <0>; - - ak4643: codec@12 { - compatible = "asahi-kasei,ak4643"; - #sound-dai-cells = <0>; - reg = <0x12>; - }; - - composite-in@20 { - compatible = "adi,adv7180"; - reg = <0x20>; - remote = <&vin1>; - - port { - adv7180: endpoint { - bus-width = <8>; - remote-endpoint = <&vin1ep>; - }; - }; - }; - - hdmi@39 { - compatible = "adi,adv7511w"; - reg = <0x39>; - interrupt-parent = <&gpio3>; - interrupts = <29 IRQ_TYPE_LEVEL_LOW>; - clocks = <&cec_clock>; - clock-names = "cec"; - - adi,input-depth = <8>; - adi,input-colorspace = "rgb"; - adi,input-clock = "1x"; - adi,input-style = <1>; - adi,input-justification = "evenly"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7511_in: endpoint { - remote-endpoint = <&du_out_rgb>; - }; - }; - - port@1 { - reg = <1>; - adv7511_out: endpoint { - remote-endpoint = <&hdmi_con_out>; - }; - }; - }; - }; - - hdmi-in@4c { - compatible = "adi,adv7612"; - reg = <0x4c>; - interrupt-parent = <&gpio4>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - default-input = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7612_in: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; - }; - - port@2 { - reg = <2>; - adv7612_out: endpoint { - remote-endpoint = <&vin0ep2>; - }; - }; - }; - }; - - eeprom@50 { - compatible = "renesas,r1ex24002", "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; - }; - - /* - * I2C4 is routed to EXIO connector E, pins 37 (SCL) + 39 (SDA). - * A fallback to GPIO is provided. - */ - i2cexio4: i2c-14 { - compatible = "i2c-demux-pinctrl"; - i2c-parent = <&i2c4>, <&gpioi2c4>; - i2c-bus-name = "i2c-exio4"; - #address-cells = <1>; - #size-cells = <0>; - }; -}; - -&du { - pinctrl-0 = <&du_pins>; - pinctrl-names = "default"; - status = "okay"; - - clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, - <&x13_clk>, <&x2_clk>; - clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1"; - - ports { - port@0 { - endpoint { - remote-endpoint = <&adv7511_in>; - }; - }; - }; -}; - -&lvds0 { - ports { - port@1 { - lvds_connector: endpoint { - }; - }; - }; -}; - -&extal_clk { - clock-frequency = <20000000>; -}; - -&pfc { - pinctrl-0 = <&scif_clk_pins>; - pinctrl-names = "default"; - - i2c1_pins: i2c1 { - groups = "i2c1"; - function = "i2c1"; - }; - - i2c2_pins: i2c2 { - groups = "i2c2"; - function = "i2c2"; - }; - - i2c4_pins: i2c4 { - groups = "i2c4_c"; - function = "i2c4"; - }; - - du_pins: du { - groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0"; - function = "du"; - }; - - scif0_pins: scif0 { - groups = "scif0_data_d"; - function = "scif0"; - }; - - scif1_pins: scif1 { - groups = "scif1_data_d"; - function = "scif1"; - }; - - scif_clk_pins: scif_clk { - groups = "scif_clk"; - function = "scif_clk"; - }; - - ether_pins: ether { - groups = "eth_link", "eth_mdio", "eth_rmii"; - function = "eth"; - }; - - phy1_pins: phy1 { - groups = "intc_irq0"; - function = "intc"; - }; - - pmic_irq_pins: pmicirq { - groups = "intc_irq2"; - function = "intc"; - }; - - sdhi0_pins: sd0 { - groups = "sdhi0_data4", "sdhi0_ctrl"; - function = "sdhi0"; - power-source = <3300>; - }; - - sdhi0_pins_uhs: sd0_uhs { - groups = "sdhi0_data4", "sdhi0_ctrl"; - function = "sdhi0"; - power-source = <1800>; - }; - - sdhi1_pins: sd1 { - groups = "sdhi1_data4", "sdhi1_ctrl"; - function = "sdhi1"; - power-source = <3300>; - }; - - sdhi1_pins_uhs: sd1_uhs { - groups = "sdhi1_data4", "sdhi1_ctrl"; - function = "sdhi1"; - power-source = <1800>; - }; - - sdhi2_pins: sd2 { - groups = "sdhi2_data4", "sdhi2_ctrl"; - function = "sdhi2"; - power-source = <3300>; - }; - - sdhi2_pins_uhs: sd2_uhs { - groups = "sdhi2_data4", "sdhi2_ctrl"; - function = "sdhi2"; - power-source = <1800>; - }; - - qspi_pins: qspi { - groups = "qspi_ctrl", "qspi_data4"; - function = "qspi"; - }; - - msiof0_pins: msiof0 { - groups = "msiof0_clk", "msiof0_sync", "msiof0_rx", - "msiof0_tx"; - function = "msiof0"; - }; - - usb0_pins: usb0 { - groups = "usb0"; - function = "usb0"; - }; - - usb1_pins: usb1 { - groups = "usb1"; - function = "usb1"; - }; - - vin0_pins: vin0 { - groups = "vin0_data24", "vin0_sync", "vin0_clkenb", "vin0_clk"; - function = "vin0"; - }; - - vin1_pins: vin1 { - groups = "vin1_data8", "vin1_clk"; - function = "vin1"; - }; - - sound_pins: sound { - groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data"; - function = "ssi"; - }; - - sound_clk_pins: sound_clk { - groups = "audio_clk_a"; - function = "audio_clk"; - }; -}; - -ðer { - pinctrl-0 = <ðer_pins &phy1_pins>; - pinctrl-names = "default"; - - phy-handle = <&phy1>; - renesas,ether-link-active-low; - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - interrupt-parent = <&irqc0>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - micrel,led-mode = <1>; - }; -}; - -&cmt0 { - status = "okay"; -}; - -&rwdt { - timeout-sec = <60>; - status = "okay"; -}; - -&sata0 { - status = "okay"; -}; - -&scif0 { - pinctrl-0 = <&scif0_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&scif1 { - pinctrl-0 = <&scif1_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&scif_clk { - clock-frequency = <14745600>; -}; - -&sdhi0 { - pinctrl-0 = <&sdhi0_pins>; - pinctrl-1 = <&sdhi0_pins_uhs>; - pinctrl-names = "default", "state_uhs"; - - vmmc-supply = <&vcc_sdhi0>; - vqmmc-supply = <&vccq_sdhi0>; - cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; - sd-uhs-sdr50; - sd-uhs-sdr104; - status = "okay"; -}; - -&sdhi1 { - pinctrl-0 = <&sdhi1_pins>; - pinctrl-1 = <&sdhi1_pins_uhs>; - pinctrl-names = "default", "state_uhs"; - - vmmc-supply = <&vcc_sdhi1>; - vqmmc-supply = <&vccq_sdhi1>; - cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>; - sd-uhs-sdr50; - status = "okay"; -}; - -&sdhi2 { - pinctrl-0 = <&sdhi2_pins>; - pinctrl-1 = <&sdhi2_pins_uhs>; - pinctrl-names = "default", "state_uhs"; - - vmmc-supply = <&vcc_sdhi2>; - vqmmc-supply = <&vccq_sdhi2>; - cd-gpios = <&gpio6 22 GPIO_ACTIVE_LOW>; - sd-uhs-sdr50; - status = "okay"; -}; - -&qspi { - pinctrl-0 = <&qspi_pins>; - pinctrl-names = "default"; - - status = "okay"; - - flash: flash@0 { - compatible = "spansion,s25fl512s", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <30000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - spi-cpha; - spi-cpol; - m25p,fast-read; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "loader"; - reg = <0x00000000 0x00080000>; - read-only; - }; - partition@80000 { - label = "user"; - reg = <0x00080000 0x00580000>; - read-only; - }; - partition@600000 { - label = "flash"; - reg = <0x00600000 0x03a00000>; - }; - }; - }; -}; - -&msiof0 { - pinctrl-0 = <&msiof0_pins>; - pinctrl-names = "default"; - - status = "okay"; - - pmic: pmic@0 { - compatible = "renesas,r2a11302ft"; - reg = <0>; - spi-max-frequency = <6000000>; - spi-cpol; - spi-cpha; - }; -}; - -&i2c1 { - pinctrl-0 = <&i2c1_pins>; - pinctrl-names = "i2c-exio1"; -}; - -&i2c2 { - pinctrl-0 = <&i2c2_pins>; - pinctrl-names = "i2c-hdmi"; - - clock-frequency = <100000>; -}; - -&i2c4 { - pinctrl-0 = <&i2c4_pins>; - pinctrl-names = "i2c-exio4"; -}; - -&i2c6 { - pinctrl-names = "default"; - pinctrl-0 = <&pmic_irq_pins>; - status = "okay"; - clock-frequency = <100000>; - - pmic@58 { - compatible = "dlg,da9063"; - reg = <0x58>; - interrupt-parent = <&irqc0>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - - rtc { - compatible = "dlg,da9063-rtc"; - }; - - wdt { - compatible = "dlg,da9063-watchdog"; - }; - }; - - vdd_dvfs: regulator@68 { - compatible = "dlg,da9210"; - reg = <0x68>; - interrupt-parent = <&irqc0>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-boot-on; - regulator-always-on; - }; -}; - -&pci0 { - status = "okay"; - pinctrl-0 = <&usb0_pins>; - pinctrl-names = "default"; -}; - -&pci1 { - status = "okay"; - pinctrl-0 = <&usb1_pins>; - pinctrl-names = "default"; -}; - -&hsusb { - status = "okay"; - pinctrl-0 = <&usb0_pins>; - pinctrl-names = "default"; - renesas,enable-gpio = <&gpio5 31 GPIO_ACTIVE_HIGH>; -}; - -&usbphy { - status = "okay"; -}; - -&pcie_bus_clk { - clock-frequency = <100000000>; -}; - -&pciec { - status = "okay"; -}; - -&cpu0 { - cpu0-supply = <&vdd_dvfs>; -}; - -/* HDMI video input */ -&vin0 { - status = "okay"; - pinctrl-0 = <&vin0_pins>; - pinctrl-names = "default"; - - port { - vin0ep2: endpoint { - remote-endpoint = <&adv7612_out>; - bus-width = <24>; - hsync-active = <0>; - vsync-active = <0>; - pclk-sample = <1>; - data-active = <1>; - }; - }; -}; - -/* composite video input */ -&vin1 { - status = "okay"; - pinctrl-0 = <&vin1_pins>; - pinctrl-names = "default"; - - port { - vin1ep: endpoint { - remote-endpoint = <&adv7180>; - bus-width = <8>; - }; - }; -}; - -&rcar_sound { - pinctrl-0 = <&sound_pins &sound_clk_pins>; - pinctrl-names = "default"; - - /* Single DAI */ - #sound-dai-cells = <0>; - - status = "okay"; - - rcar_sound,dai { - dai0 { - playback = <&ssi0 &src2 &dvc0>; - capture = <&ssi1 &src3 &dvc1>; - }; - }; -}; - -&ssi1 { - shared-pin; -}; diff --git a/sys/gnu/dts/arm/r8a7791-porter.dts b/sys/gnu/dts/arm/r8a7791-porter.dts deleted file mode 100644 index f9ece7ab201..00000000000 --- a/sys/gnu/dts/arm/r8a7791-porter.dts +++ /dev/null @@ -1,521 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the Porter board - * - * Copyright (C) 2015 Cogent Embedded, Inc. - */ - -/* - * SSI-AK4642 - * - * JP3: 2-1: AK4642 - * 2-3: ADV7511 - * - * This command is required before playback/capture: - * - * amixer set "LINEOUT Mixer DACL" on - */ - -/dts-v1/; -#include "r8a7791.dtsi" -#include - -/ { - model = "Porter"; - compatible = "renesas,porter", "renesas,r8a7791"; - - aliases { - serial0 = &scif0; - i2c9 = &gpioi2c2; - i2c10 = &i2chdmi; - }; - - chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; - stdout-path = "serial0:115200n8"; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0 0x40000000 0 0x40000000>; - }; - - memory@200000000 { - device_type = "memory"; - reg = <2 0x00000000 0 0x40000000>; - }; - - vcc_sdhi0: regulator-vcc-sdhi0 { - compatible = "regulator-fixed"; - - regulator-name = "SDHI0 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vccq_sdhi0: regulator-vccq-sdhi0 { - compatible = "regulator-gpio"; - - regulator-name = "SDHI0 VccQ"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>; - gpios-states = <1>; - states = <3300000 1>, <1800000 0>; - }; - - vcc_sdhi2: regulator-vcc-sdhi2 { - compatible = "regulator-fixed"; - - regulator-name = "SDHI2 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vccq_sdhi2: regulator-vccq-sdhi2 { - compatible = "regulator-gpio"; - - regulator-name = "SDHI2 VccQ"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>; - gpios-states = <1>; - states = <3300000 1>, <1800000 0>; - }; - - hdmi-out { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con: endpoint { - remote-endpoint = <&adv7511_out>; - }; - }; - }; - - x3_clk: x3-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <148500000>; - }; - - x16_clk: x16-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <74250000>; - }; - - x14_clk: audio_clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <11289600>; - }; - - sound { - compatible = "simple-audio-card"; - - simple-audio-card,format = "left_j"; - simple-audio-card,bitclock-master = <&soundcodec>; - simple-audio-card,frame-master = <&soundcodec>; - - simple-audio-card,cpu { - sound-dai = <&rcar_sound>; - }; - - soundcodec: simple-audio-card,codec { - sound-dai = <&ak4642>; - clocks = <&x14_clk>; - }; - }; - - gpioi2c2: i2c-9 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "i2c-gpio"; - status = "disabled"; - scl-gpios = <&gpio2 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio2 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <5>; - }; - - /* - * A fallback to GPIO is provided for I2C2. - */ - i2chdmi: i2c-10 { - compatible = "i2c-demux-pinctrl"; - i2c-parent = <&i2c2>, <&gpioi2c2>; - i2c-bus-name = "i2c-hdmi"; - #address-cells = <1>; - #size-cells = <0>; - - ak4642: codec@12 { - compatible = "asahi-kasei,ak4642"; - #sound-dai-cells = <0>; - reg = <0x12>; - }; - - composite-in@20 { - compatible = "adi,adv7180"; - reg = <0x20>; - remote = <&vin0>; - - port { - adv7180: endpoint { - bus-width = <8>; - remote-endpoint = <&vin0ep>; - }; - }; - }; - - hdmi@39 { - compatible = "adi,adv7511w"; - reg = <0x39>; - interrupt-parent = <&gpio3>; - interrupts = <29 IRQ_TYPE_LEVEL_LOW>; - - adi,input-depth = <8>; - adi,input-colorspace = "rgb"; - adi,input-clock = "1x"; - adi,input-style = <1>; - adi,input-justification = "evenly"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7511_in: endpoint { - remote-endpoint = <&du_out_rgb>; - }; - }; - - port@1 { - reg = <1>; - adv7511_out: endpoint { - remote-endpoint = <&hdmi_con>; - }; - }; - }; - }; - }; -}; - -&extal_clk { - clock-frequency = <20000000>; -}; - -&pfc { - scif0_pins: scif0 { - groups = "scif0_data_d"; - function = "scif0"; - }; - - ether_pins: ether { - groups = "eth_link", "eth_mdio", "eth_rmii"; - function = "eth"; - }; - - phy1_pins: phy1 { - groups = "intc_irq0"; - function = "intc"; - }; - - pmic_irq_pins: pmicirq { - groups = "intc_irq2"; - function = "intc"; - }; - - sdhi0_pins: sd0 { - groups = "sdhi0_data4", "sdhi0_ctrl"; - function = "sdhi0"; - }; - - sdhi2_pins: sd2 { - groups = "sdhi2_data4", "sdhi2_ctrl"; - function = "sdhi2"; - }; - - qspi_pins: qspi { - groups = "qspi_ctrl", "qspi_data4"; - function = "qspi"; - }; - - i2c2_pins: i2c2 { - groups = "i2c2"; - function = "i2c2"; - }; - - usb0_pins: usb0 { - groups = "usb0"; - function = "usb0"; - }; - - usb1_pins: usb1 { - groups = "usb1"; - function = "usb1"; - }; - - vin0_pins: vin0 { - groups = "vin0_data8", "vin0_clk"; - function = "vin0"; - }; - - can0_pins: can0 { - groups = "can0_data"; - function = "can0"; - }; - - du_pins: du { - groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0"; - function = "du"; - }; - - ssi_pins: sound { - groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data"; - function = "ssi"; - }; - - audio_clk_pins: audio_clk { - groups = "audio_clk_a"; - function = "audio_clk"; - }; -}; - -&scif0 { - pinctrl-0 = <&scif0_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -ðer { - pinctrl-0 = <ðer_pins &phy1_pins>; - pinctrl-names = "default"; - - phy-handle = <&phy1>; - renesas,ether-link-active-low; - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - interrupt-parent = <&irqc0>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - micrel,led-mode = <1>; - }; -}; - -&sdhi0 { - pinctrl-0 = <&sdhi0_pins>; - pinctrl-names = "default"; - - vmmc-supply = <&vcc_sdhi0>; - vqmmc-supply = <&vccq_sdhi0>; - cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&sdhi2 { - pinctrl-0 = <&sdhi2_pins>; - pinctrl-names = "default"; - - vmmc-supply = <&vcc_sdhi2>; - vqmmc-supply = <&vccq_sdhi2>; - cd-gpios = <&gpio6 22 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&qspi { - pinctrl-0 = <&qspi_pins>; - pinctrl-names = "default"; - - status = "okay"; - - flash@0 { - compatible = "spansion,s25fl512s", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <30000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - m25p,fast-read; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "loader_prg"; - reg = <0x00000000 0x00040000>; - read-only; - }; - partition@40000 { - label = "user_prg"; - reg = <0x00040000 0x00400000>; - read-only; - }; - partition@440000 { - label = "flash_fs"; - reg = <0x00440000 0x03bc0000>; - }; - }; - }; -}; - -&i2c2 { - pinctrl-0 = <&i2c2_pins>; - pinctrl-names = "i2c-hdmi"; - - clock-frequency = <400000>; -}; - -&i2c6 { - pinctrl-names = "default"; - pinctrl-0 = <&pmic_irq_pins>; - status = "okay"; - clock-frequency = <100000>; - - pmic@5a { - compatible = "dlg,da9063l"; - reg = <0x5a>; - interrupt-parent = <&irqc0>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - - wdt { - compatible = "dlg,da9063-watchdog"; - }; - }; - - vdd_dvfs: regulator@68 { - compatible = "dlg,da9210"; - reg = <0x68>; - interrupt-parent = <&irqc0>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-boot-on; - regulator-always-on; - }; -}; - -&sata0 { - status = "okay"; -}; - -&cpu0 { - cpu0-supply = <&vdd_dvfs>; -}; - -/* composite video input */ -&vin0 { - status = "okay"; - pinctrl-0 = <&vin0_pins>; - pinctrl-names = "default"; - - port { - vin0ep: endpoint { - remote-endpoint = <&adv7180>; - bus-width = <8>; - }; - }; -}; - -&pci0 { - pinctrl-0 = <&usb0_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&pci1 { - pinctrl-0 = <&usb1_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&hsusb { - pinctrl-0 = <&usb0_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; - -&pcie_bus_clk { - clock-frequency = <100000000>; -}; - -&pciec { - status = "okay"; -}; - -&can0 { - pinctrl-0 = <&can0_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&du { - pinctrl-0 = <&du_pins>; - pinctrl-names = "default"; - status = "okay"; - - clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, - <&x3_clk>, <&x16_clk>; - clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1"; - - ports { - port@0 { - endpoint { - remote-endpoint = <&adv7511_in>; - }; - }; - }; -}; - -&lvds0 { - ports { - port@1 { - lvds_connector: endpoint { - }; - }; - }; -}; - -&rcar_sound { - pinctrl-0 = <&ssi_pins &audio_clk_pins>; - pinctrl-names = "default"; - status = "okay"; - - /* Single DAI */ - #sound-dai-cells = <0>; - - rcar_sound,dai { - dai0 { - playback = <&ssi0>; - capture = <&ssi1>; - }; - }; -}; - -&rwdt { - timeout-sec = <60>; - status = "okay"; -}; - -&ssi1 { - shared-pin; -}; diff --git a/sys/gnu/dts/arm/r8a7791.dtsi b/sys/gnu/dts/arm/r8a7791.dtsi deleted file mode 100644 index 59a55e87fcc..00000000000 --- a/sys/gnu/dts/arm/r8a7791.dtsi +++ /dev/null @@ -1,1806 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the R-Car M2-W (R8A77910) SoC - * - * Copyright (C) 2013-2015 Renesas Electronics Corporation - * Copyright (C) 2013-2014 Renesas Solutions Corp. - * Copyright (C) 2014 Cogent Embedded Inc. - */ - -#include -#include -#include -#include - -/ { - compatible = "renesas,r8a7791"; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - i2c6 = &i2c6; - i2c7 = &i2c7; - i2c8 = &i2c8; - spi0 = &qspi; - spi1 = &msiof0; - spi2 = &msiof1; - spi3 = &msiof2; - vin0 = &vin0; - vin1 = &vin1; - vin2 = &vin2; - }; - - /* - * The external audio clocks are configured as 0 Hz fixed frequency - * clocks by default. - * Boards that provide audio clocks should override them. - */ - audio_clk_a: audio_clk_a { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - audio_clk_b: audio_clk_b { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - audio_clk_c: audio_clk_c { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - /* External CAN clock */ - can_clk: can { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "renesas,apmu"; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0>; - clock-frequency = <1500000000>; - clocks = <&cpg CPG_CORE R8A7791_CLK_Z>; - power-domains = <&sysc R8A7791_PD_CA15_CPU0>; - next-level-cache = <&L2_CA15>; - voltage-tolerance = <1>; /* 1% */ - clock-latency = <300000>; /* 300 us */ - - /* kHz - uV - OPPs unknown yet */ - operating-points = <1500000 1000000>, - <1312500 1000000>, - <1125000 1000000>, - < 937500 1000000>, - < 750000 1000000>, - < 375000 1000000>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <1>; - clock-frequency = <1500000000>; - clocks = <&cpg CPG_CORE R8A7791_CLK_Z>; - power-domains = <&sysc R8A7791_PD_CA15_CPU1>; - next-level-cache = <&L2_CA15>; - voltage-tolerance = <1>; /* 1% */ - clock-latency = <300000>; /* 300 us */ - - /* kHz - uV - OPPs unknown yet */ - operating-points = <1500000 1000000>, - <1312500 1000000>, - <1125000 1000000>, - < 937500 1000000>, - < 750000 1000000>, - < 375000 1000000>; - }; - - L2_CA15: cache-controller-0 { - compatible = "cache"; - power-domains = <&sysc R8A7791_PD_CA15_SCU>; - cache-unified; - cache-level = <2>; - }; - }; - - /* External root clock */ - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - /* External PCIe clock - can be overridden by the board */ - pcie_bus_clk: pcie_bus { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - pmu { - compatible = "arm,cortex-a15-pmu"; - interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&cpu0>, <&cpu1>; - }; - - /* External SCIF clock */ - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - soc { - compatible = "simple-bus"; - interrupt-parent = <&gic>; - - #address-cells = <2>; - #size-cells = <2>; - ranges; - - rwdt: watchdog@e6020000 { - compatible = "renesas,r8a7791-wdt", - "renesas,rcar-gen2-wdt"; - reg = <0 0xe6020000 0 0x0c>; - clocks = <&cpg CPG_MOD 402>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 402>; - status = "disabled"; - }; - - gpio0: gpio@e6050000 { - compatible = "renesas,gpio-r8a7791", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6050000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 0 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 912>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 912>; - }; - - gpio1: gpio@e6051000 { - compatible = "renesas,gpio-r8a7791", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6051000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 32 26>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 911>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 911>; - }; - - gpio2: gpio@e6052000 { - compatible = "renesas,gpio-r8a7791", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6052000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 64 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 910>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 910>; - }; - - gpio3: gpio@e6053000 { - compatible = "renesas,gpio-r8a7791", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6053000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 96 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 909>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 909>; - }; - - gpio4: gpio@e6054000 { - compatible = "renesas,gpio-r8a7791", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6054000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 128 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 908>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 908>; - }; - - gpio5: gpio@e6055000 { - compatible = "renesas,gpio-r8a7791", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6055000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 160 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 907>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 907>; - }; - - gpio6: gpio@e6055400 { - compatible = "renesas,gpio-r8a7791", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6055400 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 192 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 905>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 905>; - }; - - gpio7: gpio@e6055800 { - compatible = "renesas,gpio-r8a7791", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6055800 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 224 26>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 904>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 904>; - }; - - pfc: pin-controller@e6060000 { - compatible = "renesas,pfc-r8a7791"; - reg = <0 0xe6060000 0 0x250>; - }; - - cpg: clock-controller@e6150000 { - compatible = "renesas,r8a7791-cpg-mssr"; - reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk>, <&usb_extal_clk>; - clock-names = "extal", "usb_extal"; - #clock-cells = <2>; - #power-domain-cells = <0>; - #reset-cells = <1>; - }; - - apmu@e6152000 { - compatible = "renesas,r8a7791-apmu", "renesas,apmu"; - reg = <0 0xe6152000 0 0x188>; - cpus = <&cpu0 &cpu1>; - }; - - rst: reset-controller@e6160000 { - compatible = "renesas,r8a7791-rst"; - reg = <0 0xe6160000 0 0x0100>; - }; - - sysc: system-controller@e6180000 { - compatible = "renesas,r8a7791-sysc"; - reg = <0 0xe6180000 0 0x0200>; - #power-domain-cells = <1>; - }; - - irqc0: interrupt-controller@e61c0000 { - compatible = "renesas,irqc-r8a7791", "renesas,irqc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0 0xe61c0000 0 0x200>; - interrupts = , - , - , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 407>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 407>; - }; - - thermal: thermal@e61f0000 { - compatible = "renesas,thermal-r8a7791", - "renesas,rcar-gen2-thermal", - "renesas,rcar-thermal"; - reg = <0 0xe61f0000 0 0x10>, <0 0xe61f0100 0 0x38>; - interrupts = ; - clocks = <&cpg CPG_MOD 522>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 522>; - #thermal-sensor-cells = <0>; - }; - - ipmmu_sy0: mmu@e6280000 { - compatible = "renesas,ipmmu-r8a7791", - "renesas,ipmmu-vmsa"; - reg = <0 0xe6280000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_sy1: mmu@e6290000 { - compatible = "renesas,ipmmu-r8a7791", - "renesas,ipmmu-vmsa"; - reg = <0 0xe6290000 0 0x1000>; - interrupts = ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_ds: mmu@e6740000 { - compatible = "renesas,ipmmu-r8a7791", - "renesas,ipmmu-vmsa"; - reg = <0 0xe6740000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_mp: mmu@ec680000 { - compatible = "renesas,ipmmu-r8a7791", - "renesas,ipmmu-vmsa"; - reg = <0 0xec680000 0 0x1000>; - interrupts = ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_mx: mmu@fe951000 { - compatible = "renesas,ipmmu-r8a7791", - "renesas,ipmmu-vmsa"; - reg = <0 0xfe951000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_rt: mmu@ffc80000 { - compatible = "renesas,ipmmu-r8a7791", - "renesas,ipmmu-vmsa"; - reg = <0 0xffc80000 0 0x1000>; - interrupts = ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_gp: mmu@e62a0000 { - compatible = "renesas,ipmmu-r8a7791", - "renesas,ipmmu-vmsa"; - reg = <0 0xe62a0000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; - - icram0: sram@e63a0000 { - compatible = "mmio-sram"; - reg = <0 0xe63a0000 0 0x12000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0xe63a0000 0x12000>; - }; - - icram1: sram@e63c0000 { - compatible = "mmio-sram"; - reg = <0 0xe63c0000 0 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0xe63c0000 0x1000>; - - smp-sram@0 { - compatible = "renesas,smp-sram"; - reg = <0 0x100>; - }; - }; - - /* The memory map in the User's Manual maps the cores to - * bus numbers - */ - i2c0: i2c@e6508000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7791", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6508000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 931>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 931>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c1: i2c@e6518000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7791", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6518000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 930>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 930>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c2: i2c@e6530000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7791", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6530000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 929>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 929>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c3: i2c@e6540000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7791", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6540000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 928>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 928>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c4: i2c@e6520000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7791", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6520000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 927>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 927>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c5: i2c@e6528000 { - /* doesn't need pinmux */ - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7791", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6528000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 925>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 925>; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c6: i2c@e60b0000 { - /* doesn't need pinmux */ - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7791", - "renesas,rcar-gen2-iic", - "renesas,rmobile-iic"; - reg = <0 0xe60b0000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 926>; - dmas = <&dmac0 0x77>, <&dmac0 0x78>, - <&dmac1 0x77>, <&dmac1 0x78>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 926>; - status = "disabled"; - }; - - i2c7: i2c@e6500000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7791", - "renesas,rcar-gen2-iic", - "renesas,rmobile-iic"; - reg = <0 0xe6500000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 318>; - dmas = <&dmac0 0x61>, <&dmac0 0x62>, - <&dmac1 0x61>, <&dmac1 0x62>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 318>; - status = "disabled"; - }; - - i2c8: i2c@e6510000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7791", - "renesas,rcar-gen2-iic", - "renesas,rmobile-iic"; - reg = <0 0xe6510000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 323>; - dmas = <&dmac0 0x65>, <&dmac0 0x66>, - <&dmac1 0x65>, <&dmac1 0x66>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 323>; - status = "disabled"; - }; - - hsusb: usb@e6590000 { - compatible = "renesas,usbhs-r8a7791", - "renesas,rcar-gen2-usbhs"; - reg = <0 0xe6590000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 704>; - dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, - <&usb_dmac1 0>, <&usb_dmac1 1>; - dma-names = "ch0", "ch1", "ch2", "ch3"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 704>; - renesas,buswait = <4>; - phys = <&usb0 1>; - phy-names = "usb"; - status = "disabled"; - }; - - usbphy: usb-phy@e6590100 { - compatible = "renesas,usb-phy-r8a7791", - "renesas,rcar-gen2-usb-phy"; - reg = <0 0xe6590100 0 0x100>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cpg CPG_MOD 704>; - clock-names = "usbhs"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 704>; - status = "disabled"; - - usb0: usb-channel@0 { - reg = <0>; - #phy-cells = <1>; - }; - usb2: usb-channel@2 { - reg = <2>; - #phy-cells = <1>; - }; - }; - - usb_dmac0: dma-controller@e65a0000 { - compatible = "renesas,r8a7791-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65a0000 0 0x100>; - interrupts = , - ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 330>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 330>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - usb_dmac1: dma-controller@e65b0000 { - compatible = "renesas,r8a7791-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65b0000 0 0x100>; - interrupts = , - ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 331>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 331>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - dmac0: dma-controller@e6700000 { - compatible = "renesas,dmac-r8a7791", - "renesas,rcar-dmac"; - reg = <0 0xe6700000 0 0x20000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14"; - clocks = <&cpg CPG_MOD 219>; - clock-names = "fck"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 219>; - #dma-cells = <1>; - dma-channels = <15>; - }; - - dmac1: dma-controller@e6720000 { - compatible = "renesas,dmac-r8a7791", - "renesas,rcar-dmac"; - reg = <0 0xe6720000 0 0x20000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14"; - clocks = <&cpg CPG_MOD 218>; - clock-names = "fck"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 218>; - #dma-cells = <1>; - dma-channels = <15>; - }; - - avb: ethernet@e6800000 { - compatible = "renesas,etheravb-r8a7791", - "renesas,etheravb-rcar-gen2"; - reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; - interrupts = ; - clocks = <&cpg CPG_MOD 812>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 812>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - qspi: spi@e6b10000 { - compatible = "renesas,qspi-r8a7791", "renesas,qspi"; - reg = <0 0xe6b10000 0 0x2c>; - interrupts = ; - clocks = <&cpg CPG_MOD 917>; - dmas = <&dmac0 0x17>, <&dmac0 0x18>, - <&dmac1 0x17>, <&dmac1 0x18>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 917>; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - scifa0: serial@e6c40000 { - compatible = "renesas,scifa-r8a7791", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c40000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 204>; - clock-names = "fck"; - dmas = <&dmac0 0x21>, <&dmac0 0x22>, - <&dmac1 0x21>, <&dmac1 0x22>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 204>; - status = "disabled"; - }; - - scifa1: serial@e6c50000 { - compatible = "renesas,scifa-r8a7791", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c50000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 203>; - clock-names = "fck"; - dmas = <&dmac0 0x25>, <&dmac0 0x26>, - <&dmac1 0x25>, <&dmac1 0x26>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 203>; - status = "disabled"; - }; - - scifa2: serial@e6c60000 { - compatible = "renesas,scifa-r8a7791", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c60000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 202>; - clock-names = "fck"; - dmas = <&dmac0 0x27>, <&dmac0 0x28>, - <&dmac1 0x27>, <&dmac1 0x28>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 202>; - status = "disabled"; - }; - - scifa3: serial@e6c70000 { - compatible = "renesas,scifa-r8a7791", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c70000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 1106>; - clock-names = "fck"; - dmas = <&dmac0 0x1b>, <&dmac0 0x1c>, - <&dmac1 0x1b>, <&dmac1 0x1c>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 1106>; - status = "disabled"; - }; - - scifa4: serial@e6c78000 { - compatible = "renesas,scifa-r8a7791", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c78000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 1107>; - clock-names = "fck"; - dmas = <&dmac0 0x1f>, <&dmac0 0x20>, - <&dmac1 0x1f>, <&dmac1 0x20>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 1107>; - status = "disabled"; - }; - - scifa5: serial@e6c80000 { - compatible = "renesas,scifa-r8a7791", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c80000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 1108>; - clock-names = "fck"; - dmas = <&dmac0 0x23>, <&dmac0 0x24>, - <&dmac1 0x23>, <&dmac1 0x24>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 1108>; - status = "disabled"; - }; - - scifb0: serial@e6c20000 { - compatible = "renesas,scifb-r8a7791", - "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6c20000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 206>; - clock-names = "fck"; - dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, - <&dmac1 0x3d>, <&dmac1 0x3e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 206>; - status = "disabled"; - }; - - scifb1: serial@e6c30000 { - compatible = "renesas,scifb-r8a7791", - "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6c30000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 207>; - clock-names = "fck"; - dmas = <&dmac0 0x19>, <&dmac0 0x1a>, - <&dmac1 0x19>, <&dmac1 0x1a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 207>; - status = "disabled"; - }; - - scifb2: serial@e6ce0000 { - compatible = "renesas,scifb-r8a7791", - "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6ce0000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 216>; - clock-names = "fck"; - dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, - <&dmac1 0x1d>, <&dmac1 0x1e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 216>; - status = "disabled"; - }; - - scif0: serial@e6e60000 { - compatible = "renesas,scif-r8a7791", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6e60000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7791_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x29>, <&dmac0 0x2a>, - <&dmac1 0x29>, <&dmac1 0x2a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 721>; - status = "disabled"; - }; - - scif1: serial@e6e68000 { - compatible = "renesas,scif-r8a7791", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6e68000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 720>, <&cpg CPG_CORE R8A7791_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, - <&dmac1 0x2d>, <&dmac1 0x2e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 720>; - status = "disabled"; - }; - - scif2: serial@e6e58000 { - compatible = "renesas,scif-r8a7791", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6e58000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 719>, <&cpg CPG_CORE R8A7791_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, - <&dmac1 0x2b>, <&dmac1 0x2c>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 719>; - status = "disabled"; - }; - - scif3: serial@e6ea8000 { - compatible = "renesas,scif-r8a7791", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6ea8000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 718>, <&cpg CPG_CORE R8A7791_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2f>, <&dmac0 0x30>, - <&dmac1 0x2f>, <&dmac1 0x30>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 718>; - status = "disabled"; - }; - - scif4: serial@e6ee0000 { - compatible = "renesas,scif-r8a7791", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6ee0000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 715>, <&cpg CPG_CORE R8A7791_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0xfb>, <&dmac0 0xfc>, - <&dmac1 0xfb>, <&dmac1 0xfc>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 715>; - status = "disabled"; - }; - - scif5: serial@e6ee8000 { - compatible = "renesas,scif-r8a7791", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6ee8000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 714>, <&cpg CPG_CORE R8A7791_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0xfd>, <&dmac0 0xfe>, - <&dmac1 0xfd>, <&dmac1 0xfe>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 714>; - status = "disabled"; - }; - - hscif0: serial@e62c0000 { - compatible = "renesas,hscif-r8a7791", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62c0000 0 96>; - interrupts = ; - clocks = <&cpg CPG_MOD 717>, <&cpg CPG_CORE R8A7791_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x39>, <&dmac0 0x3a>, - <&dmac1 0x39>, <&dmac1 0x3a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 717>; - status = "disabled"; - }; - - hscif1: serial@e62c8000 { - compatible = "renesas,hscif-r8a7791", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62c8000 0 96>; - interrupts = ; - clocks = <&cpg CPG_MOD 716>, <&cpg CPG_CORE R8A7791_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, - <&dmac1 0x4d>, <&dmac1 0x4e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 716>; - status = "disabled"; - }; - - hscif2: serial@e62d0000 { - compatible = "renesas,hscif-r8a7791", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62d0000 0 96>; - interrupts = ; - clocks = <&cpg CPG_MOD 713>, <&cpg CPG_CORE R8A7791_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x3b>, <&dmac0 0x3c>, - <&dmac1 0x3b>, <&dmac1 0x3c>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 713>; - status = "disabled"; - }; - - msiof0: spi@e6e20000 { - compatible = "renesas,msiof-r8a7791", - "renesas,rcar-gen2-msiof"; - reg = <0 0xe6e20000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 000>; - dmas = <&dmac0 0x51>, <&dmac0 0x52>, - <&dmac1 0x51>, <&dmac1 0x52>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 0>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof1: spi@e6e10000 { - compatible = "renesas,msiof-r8a7791", - "renesas,rcar-gen2-msiof"; - reg = <0 0xe6e10000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 208>; - dmas = <&dmac0 0x55>, <&dmac0 0x56>, - <&dmac1 0x55>, <&dmac1 0x56>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 208>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof2: spi@e6e00000 { - compatible = "renesas,msiof-r8a7791", - "renesas,rcar-gen2-msiof"; - reg = <0 0xe6e00000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 205>; - dmas = <&dmac0 0x41>, <&dmac0 0x42>, - <&dmac1 0x41>, <&dmac1 0x42>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 205>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - adc: adc@e6e54000 { - compatible = "renesas,r8a7791-gyroadc", - "renesas,rcar-gyroadc"; - reg = <0 0xe6e54000 0 64>; - clocks = <&cpg CPG_MOD 901>; - clock-names = "fck"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 901>; - status = "disabled"; - }; - - can0: can@e6e80000 { - compatible = "renesas,can-r8a7791", - "renesas,rcar-gen2-can"; - reg = <0 0xe6e80000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 916>, - <&cpg CPG_CORE R8A7791_CLK_RCAN>, <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 916>; - status = "disabled"; - }; - - can1: can@e6e88000 { - compatible = "renesas,can-r8a7791", - "renesas,rcar-gen2-can"; - reg = <0 0xe6e88000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 915>, - <&cpg CPG_CORE R8A7791_CLK_RCAN>, <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 915>; - status = "disabled"; - }; - - vin0: video@e6ef0000 { - compatible = "renesas,vin-r8a7791", - "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef0000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 811>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 811>; - status = "disabled"; - }; - - vin1: video@e6ef1000 { - compatible = "renesas,vin-r8a7791", - "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef1000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 810>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 810>; - status = "disabled"; - }; - - vin2: video@e6ef2000 { - compatible = "renesas,vin-r8a7791", - "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef2000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 809>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 809>; - status = "disabled"; - }; - - rcar_sound: sound@ec500000 { - /* - * #sound-dai-cells is required - * - * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; - * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; - */ - compatible = "renesas,rcar_sound-r8a7791", - "renesas,rcar_sound-gen2"; - reg = <0 0xec500000 0 0x1000>, /* SCU */ - <0 0xec5a0000 0 0x100>, /* ADG */ - <0 0xec540000 0 0x1000>, /* SSIU */ - <0 0xec541000 0 0x280>, /* SSI */ - <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ - reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; - - clocks = <&cpg CPG_MOD 1005>, - <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, - <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, - <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, - <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, - <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, - <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, - <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, - <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, - <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, - <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, - <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, - <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, - <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, - <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, - <&cpg CPG_CORE R8A7791_CLK_M2>; - clock-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", - "ssi.5", "ssi.4", "ssi.3", "ssi.2", - "ssi.1", "ssi.0", "src.9", "src.8", - "src.7", "src.6", "src.5", "src.4", - "src.3", "src.2", "src.1", "src.0", - "ctu.0", "ctu.1", - "mix.0", "mix.1", - "dvc.0", "dvc.1", - "clk_a", "clk_b", "clk_c", "clk_i"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 1005>, - <&cpg 1006>, <&cpg 1007>, - <&cpg 1008>, <&cpg 1009>, - <&cpg 1010>, <&cpg 1011>, - <&cpg 1012>, <&cpg 1013>, - <&cpg 1014>, <&cpg 1015>; - reset-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", - "ssi.5", "ssi.4", "ssi.3", "ssi.2", - "ssi.1", "ssi.0"; - - status = "disabled"; - - rcar_sound,dvc { - dvc0: dvc-0 { - dmas = <&audma1 0xbc>; - dma-names = "tx"; - }; - dvc1: dvc-1 { - dmas = <&audma1 0xbe>; - dma-names = "tx"; - }; - }; - - rcar_sound,mix { - mix0: mix-0 { }; - mix1: mix-1 { }; - }; - - rcar_sound,ctu { - ctu00: ctu-0 { }; - ctu01: ctu-1 { }; - ctu02: ctu-2 { }; - ctu03: ctu-3 { }; - ctu10: ctu-4 { }; - ctu11: ctu-5 { }; - ctu12: ctu-6 { }; - ctu13: ctu-7 { }; - }; - - rcar_sound,src { - src0: src-0 { - interrupts = ; - dmas = <&audma0 0x85>, <&audma1 0x9a>; - dma-names = "rx", "tx"; - }; - src1: src-1 { - interrupts = ; - dmas = <&audma0 0x87>, <&audma1 0x9c>; - dma-names = "rx", "tx"; - }; - src2: src-2 { - interrupts = ; - dmas = <&audma0 0x89>, <&audma1 0x9e>; - dma-names = "rx", "tx"; - }; - src3: src-3 { - interrupts = ; - dmas = <&audma0 0x8b>, <&audma1 0xa0>; - dma-names = "rx", "tx"; - }; - src4: src-4 { - interrupts = ; - dmas = <&audma0 0x8d>, <&audma1 0xb0>; - dma-names = "rx", "tx"; - }; - src5: src-5 { - interrupts = ; - dmas = <&audma0 0x8f>, <&audma1 0xb2>; - dma-names = "rx", "tx"; - }; - src6: src-6 { - interrupts = ; - dmas = <&audma0 0x91>, <&audma1 0xb4>; - dma-names = "rx", "tx"; - }; - src7: src-7 { - interrupts = ; - dmas = <&audma0 0x93>, <&audma1 0xb6>; - dma-names = "rx", "tx"; - }; - src8: src-8 { - interrupts = ; - dmas = <&audma0 0x95>, <&audma1 0xb8>; - dma-names = "rx", "tx"; - }; - src9: src-9 { - interrupts = ; - dmas = <&audma0 0x97>, <&audma1 0xba>; - dma-names = "rx", "tx"; - }; - }; - - rcar_sound,ssi { - ssi0: ssi-0 { - interrupts = ; - dmas = <&audma0 0x01>, <&audma1 0x02>, - <&audma0 0x15>, <&audma1 0x16>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi1: ssi-1 { - interrupts = ; - dmas = <&audma0 0x03>, <&audma1 0x04>, - <&audma0 0x49>, <&audma1 0x4a>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi2: ssi-2 { - interrupts = ; - dmas = <&audma0 0x05>, <&audma1 0x06>, - <&audma0 0x63>, <&audma1 0x64>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi3: ssi-3 { - interrupts = ; - dmas = <&audma0 0x07>, <&audma1 0x08>, - <&audma0 0x6f>, <&audma1 0x70>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi4: ssi-4 { - interrupts = ; - dmas = <&audma0 0x09>, <&audma1 0x0a>, - <&audma0 0x71>, <&audma1 0x72>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi5: ssi-5 { - interrupts = ; - dmas = <&audma0 0x0b>, <&audma1 0x0c>, - <&audma0 0x73>, <&audma1 0x74>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi6: ssi-6 { - interrupts = ; - dmas = <&audma0 0x0d>, <&audma1 0x0e>, - <&audma0 0x75>, <&audma1 0x76>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi7: ssi-7 { - interrupts = ; - dmas = <&audma0 0x0f>, <&audma1 0x10>, - <&audma0 0x79>, <&audma1 0x7a>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi8: ssi-8 { - interrupts = ; - dmas = <&audma0 0x11>, <&audma1 0x12>, - <&audma0 0x7b>, <&audma1 0x7c>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi9: ssi-9 { - interrupts = ; - dmas = <&audma0 0x13>, <&audma1 0x14>, - <&audma0 0x7d>, <&audma1 0x7e>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - }; - }; - - audma0: dma-controller@ec700000 { - compatible = "renesas,dmac-r8a7791", - "renesas,rcar-dmac"; - reg = <0 0xec700000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12"; - clocks = <&cpg CPG_MOD 502>; - clock-names = "fck"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 502>; - #dma-cells = <1>; - dma-channels = <13>; - }; - - audma1: dma-controller@ec720000 { - compatible = "renesas,dmac-r8a7791", - "renesas,rcar-dmac"; - reg = <0 0xec720000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12"; - clocks = <&cpg CPG_MOD 501>; - clock-names = "fck"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 501>; - #dma-cells = <1>; - dma-channels = <13>; - }; - - xhci: usb@ee000000 { - compatible = "renesas,xhci-r8a7791", - "renesas,rcar-gen2-xhci"; - reg = <0 0xee000000 0 0xc00>; - interrupts = ; - clocks = <&cpg CPG_MOD 328>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 328>; - phys = <&usb2 1>; - phy-names = "usb"; - status = "disabled"; - }; - - pci0: pci@ee090000 { - compatible = "renesas,pci-r8a7791", - "renesas,pci-rcar-gen2"; - device_type = "pci"; - reg = <0 0xee090000 0 0xc00>, - <0 0xee080000 0 0x1100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 703>; - status = "disabled"; - - bus-range = <0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>; - interrupt-map-mask = <0xf800 0 0 0x7>; - interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, - <0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, - <0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; - - usb@1,0 { - reg = <0x800 0 0 0 0>; - phys = <&usb0 0>; - phy-names = "usb"; - }; - - usb@2,0 { - reg = <0x1000 0 0 0 0>; - phys = <&usb0 0>; - phy-names = "usb"; - }; - }; - - pci1: pci@ee0d0000 { - compatible = "renesas,pci-r8a7791", - "renesas,pci-rcar-gen2"; - device_type = "pci"; - reg = <0 0xee0d0000 0 0xc00>, - <0 0xee0c0000 0 0x1100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 703>; - status = "disabled"; - - bus-range = <1 1>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>; - interrupt-map-mask = <0xf800 0 0 0x7>; - interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, - <0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, - <0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; - - usb@1,0 { - reg = <0x10800 0 0 0 0>; - phys = <&usb2 0>; - phy-names = "usb"; - }; - - usb@2,0 { - reg = <0x11000 0 0 0 0>; - phys = <&usb2 0>; - phy-names = "usb"; - }; - }; - - sdhi0: sd@ee100000 { - compatible = "renesas,sdhi-r8a7791", - "renesas,rcar-gen2-sdhi"; - reg = <0 0xee100000 0 0x328>; - interrupts = ; - clocks = <&cpg CPG_MOD 314>; - dmas = <&dmac0 0xcd>, <&dmac0 0xce>, - <&dmac1 0xcd>, <&dmac1 0xce>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <195000000>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 314>; - status = "disabled"; - }; - - sdhi1: sd@ee140000 { - compatible = "renesas,sdhi-r8a7791", - "renesas,rcar-gen2-sdhi"; - reg = <0 0xee140000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 312>; - dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, - <&dmac1 0xc1>, <&dmac1 0xc2>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <97500000>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 312>; - status = "disabled"; - }; - - sdhi2: sd@ee160000 { - compatible = "renesas,sdhi-r8a7791", - "renesas,rcar-gen2-sdhi"; - reg = <0 0xee160000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 311>; - dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, - <&dmac1 0xd3>, <&dmac1 0xd4>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <97500000>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 311>; - status = "disabled"; - }; - - mmcif0: mmc@ee200000 { - compatible = "renesas,mmcif-r8a7791", - "renesas,sh-mmcif"; - reg = <0 0xee200000 0 0x80>; - interrupts = ; - clocks = <&cpg CPG_MOD 315>; - dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, - <&dmac1 0xd1>, <&dmac1 0xd2>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 315>; - reg-io-width = <4>; - status = "disabled"; - max-frequency = <97500000>; - }; - - sata0: sata@ee300000 { - compatible = "renesas,sata-r8a7791", - "renesas,rcar-gen2-sata"; - reg = <0 0xee300000 0 0x200000>; - interrupts = ; - clocks = <&cpg CPG_MOD 815>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 815>; - status = "disabled"; - }; - - sata1: sata@ee500000 { - compatible = "renesas,sata-r8a7791", - "renesas,rcar-gen2-sata"; - reg = <0 0xee500000 0 0x200000>; - interrupts = ; - clocks = <&cpg CPG_MOD 814>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 814>; - status = "disabled"; - }; - - ether: ethernet@ee700000 { - compatible = "renesas,ether-r8a7791", - "renesas,rcar-gen2-ether"; - reg = <0 0xee700000 0 0x400>; - interrupts = ; - clocks = <&cpg CPG_MOD 813>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 813>; - phy-mode = "rmii"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - gic: interrupt-controller@f1001000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>, - <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 408>; - clock-names = "clk"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 408>; - }; - - pciec: pcie@fe000000 { - compatible = "renesas,pcie-r8a7791", - "renesas,pcie-rcar-gen2"; - reg = <0 0xfe000000 0 0x80000>; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x00 0xff>; - device_type = "pci"; - ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, - <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, - <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, - <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>, - <0x43000000 2 0x00000000 2 0x00000000 1 0x00000000>; - interrupts = , - , - ; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; - clock-names = "pcie", "pcie_bus"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 319>; - status = "disabled"; - }; - - vsp@fe928000 { - compatible = "renesas,vsp1"; - reg = <0 0xfe928000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 131>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 131>; - }; - - vsp@fe930000 { - compatible = "renesas,vsp1"; - reg = <0 0xfe930000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 128>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 128>; - }; - - vsp@fe938000 { - compatible = "renesas,vsp1"; - reg = <0 0xfe938000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 127>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 127>; - }; - - fdp1@fe940000 { - compatible = "renesas,fdp1"; - reg = <0 0xfe940000 0 0x2400>; - interrupts = ; - clocks = <&cpg CPG_MOD 119>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 119>; - }; - - fdp1@fe944000 { - compatible = "renesas,fdp1"; - reg = <0 0xfe944000 0 0x2400>; - interrupts = ; - clocks = <&cpg CPG_MOD 118>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 118>; - }; - - jpu: jpeg-codec@fe980000 { - compatible = "renesas,jpu-r8a7791", - "renesas,rcar-gen2-jpu"; - reg = <0 0xfe980000 0 0x10300>; - interrupts = ; - clocks = <&cpg CPG_MOD 106>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 106>; - }; - - du: display@feb00000 { - compatible = "renesas,du-r8a7791"; - reg = <0 0xfeb00000 0 0x40000>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>; - clock-names = "du.0", "du.1"; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - du_out_rgb: endpoint { - }; - }; - port@1 { - reg = <1>; - du_out_lvds0: endpoint { - remote-endpoint = <&lvds0_in>; - }; - }; - }; - }; - - lvds0: lvds@feb90000 { - compatible = "renesas,r8a7791-lvds"; - reg = <0 0xfeb90000 0 0x1c>; - clocks = <&cpg CPG_MOD 726>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 726>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - lvds0_in: endpoint { - remote-endpoint = <&du_out_lvds0>; - }; - }; - port@1 { - reg = <1>; - lvds0_out: endpoint { - }; - }; - }; - }; - - prr: chipid@ff000044 { - compatible = "renesas,prr"; - reg = <0 0xff000044 0 4>; - }; - - cmt0: timer@ffca0000 { - compatible = "renesas,r8a7791-cmt0", - "renesas,rcar-gen2-cmt0"; - reg = <0 0xffca0000 0 0x1004>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 124>; - clock-names = "fck"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 124>; - - status = "disabled"; - }; - - cmt1: timer@e6130000 { - compatible = "renesas,r8a7791-cmt1", - "renesas,rcar-gen2-cmt1"; - reg = <0 0xe6130000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 329>; - clock-names = "fck"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 329>; - - status = "disabled"; - }; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - - thermal-sensors = <&thermal>; - - trips { - cpu-crit { - temperature = <95000>; - hysteresis = <0>; - type = "critical"; - }; - }; - cooling-maps { - }; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; - }; - - /* External USB clock - can be overridden by the board */ - usb_extal_clk: usb_extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <48000000>; - }; -}; diff --git a/sys/gnu/dts/arm/r8a7792-blanche.dts b/sys/gnu/dts/arm/r8a7792-blanche.dts deleted file mode 100644 index 248eb717eb3..00000000000 --- a/sys/gnu/dts/arm/r8a7792-blanche.dts +++ /dev/null @@ -1,358 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the Blanche board - * - * Copyright (C) 2014 Renesas Electronics Corporation - * Copyright (C) 2016 Cogent Embedded, Inc. - */ - -/dts-v1/; -#include "r8a7792.dtsi" -#include -#include - -/ { - model = "Blanche"; - compatible = "renesas,blanche", "renesas,r8a7792"; - - aliases { - serial0 = &scif0; - serial1 = &scif3; - }; - - chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; - stdout-path = "serial0:115200n8"; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0 0x40000000 0 0x40000000>; - }; - - d3_3v: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "D3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ethernet@18000000 { - compatible = "smsc,lan89218", "smsc,lan9115"; - reg = <0 0x18000000 0 0x100>; - phy-mode = "mii"; - interrupt-parent = <&irqc>; - interrupts = <0 IRQ_TYPE_EDGE_FALLING>; - smsc,irq-push-pull; - reg-io-width = <4>; - vddvario-supply = <&d3_3v>; - vdd33a-supply = <&d3_3v>; - - pinctrl-0 = <&lan89218_pins>; - pinctrl-names = "default"; - }; - - vga-encoder { - compatible = "adi,adv7123"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7123_in: endpoint { - remote-endpoint = <&du_out_rgb1>; - }; - }; - port@1 { - reg = <1>; - adv7123_out: endpoint { - remote-endpoint = <&vga_in>; - }; - }; - }; - }; - - hdmi-out { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con: endpoint { - remote-endpoint = <&adv7511_out>; - }; - }; - }; - - vga { - compatible = "vga-connector"; - - port { - vga_in: endpoint { - remote-endpoint = <&adv7123_out>; - }; - }; - }; - - x1_clk: x1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <74250000>; - }; - - x2_clk: x2 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <65000000>; - }; - - keyboard { - compatible = "gpio-keys"; - - key-1 { - linux,code = ; - label = "SW2-1"; - wakeup-source; - debounce-interval = <20>; - gpios = <&gpio3 10 GPIO_ACTIVE_LOW>; - }; - key-2 { - linux,code = ; - label = "SW2-2"; - wakeup-source; - debounce-interval = <20>; - gpios = <&gpio3 11 GPIO_ACTIVE_LOW>; - }; - key-3 { - linux,code = ; - label = "SW2-3"; - wakeup-source; - debounce-interval = <20>; - gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; - }; - key-4 { - linux,code = ; - label = "SW2-4"; - wakeup-source; - debounce-interval = <20>; - gpios = <&gpio3 15 GPIO_ACTIVE_LOW>; - }; - key-a { - linux,code = ; - label = "SW24"; - wakeup-source; - debounce-interval = <20>; - gpios = <&gpio3 20 GPIO_ACTIVE_LOW>; - }; - key-b { - linux,code = ; - label = "SW25"; - wakeup-source; - debounce-interval = <20>; - gpios = <&gpio11 2 GPIO_ACTIVE_LOW>; - }; - }; - - leds { - compatible = "gpio-leds"; - - led17 { - gpios = <&gpio10 10 GPIO_ACTIVE_HIGH>; - }; - led18 { - gpios = <&gpio10 11 GPIO_ACTIVE_HIGH>; - }; - led19 { - gpios = <&gpio10 12 GPIO_ACTIVE_HIGH>; - }; - led20 { - gpios = <&gpio10 23 GPIO_ACTIVE_HIGH>; - }; - }; - - vcc_sdhi0: regulator-vcc-sdhi0 { - compatible = "regulator-fixed"; - - regulator-name = "SDHI0 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&gpio11 12 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&extal_clk { - clock-frequency = <20000000>; -}; - -&can_clk { - clock-frequency = <48000000>; -}; - -&pfc { - scif0_pins: scif0 { - groups = "scif0_data"; - function = "scif0"; - }; - - scif3_pins: scif3 { - groups = "scif3_data"; - function = "scif3"; - }; - - lan89218_pins: lan89218 { - intc { - groups = "intc_irq0"; - function = "intc"; - }; - lbsc { - groups = "lbsc_ex_cs0"; - function = "lbsc"; - }; - }; - - can0_pins: can0 { - groups = "can0_data", "can_clk"; - function = "can0"; - }; - - sdhi0_pins: sdhi0 { - groups = "sdhi0_data4", "sdhi0_ctrl"; - function = "sdhi0"; - }; - - du0_pins: du0 { - groups = "du0_rgb888", "du0_sync", "du0_disp"; - function = "du0"; - }; - - du1_pins: du1 { - groups = "du1_rgb666", "du1_sync", "du1_disp"; - function = "du1"; - }; - - pmic_irq_pins: pmicirq { - groups = "intc_irq2"; - function = "intc"; - }; -}; - -&rwdt { - timeout-sec = <60>; - status = "okay"; -}; - -&scif0 { - pinctrl-0 = <&scif0_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&scif3 { - pinctrl-0 = <&scif3_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&can0 { - pinctrl-0 = <&can0_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&sdhi0 { - pinctrl-0 = <&sdhi0_pins>; - pinctrl-names = "default"; - - vmmc-supply = <&vcc_sdhi0>; - cd-gpios = <&gpio11 11 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&i2c1 { - status = "okay"; - clock-frequency = <400000>; - - hdmi@39 { - compatible = "adi,adv7511w"; - reg = <0x39>; - interrupt-parent = <&irqc>; - interrupts = <3 IRQ_TYPE_EDGE_FALLING>; - - adi,input-depth = <8>; - adi,input-colorspace = "rgb"; - adi,input-clock = "1x"; - adi,input-style = <1>; - adi,input-justification = "evenly"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7511_in: endpoint { - remote-endpoint = <&du_out_rgb0>; - }; - }; - - port@1 { - reg = <1>; - adv7511_out: endpoint { - remote-endpoint = <&hdmi_con>; - }; - }; - }; - }; -}; - -&iic3 { - status = "okay"; - - pmic@58 { - compatible = "dlg,da9063"; - reg = <0x58>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_irq_pins>; - interrupt-parent = <&irqc>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - - rtc { - compatible = "dlg,da9063-rtc"; - }; - - wdt { - compatible = "dlg,da9063-watchdog"; - }; - }; -}; - -&du { - pinctrl-0 = <&du0_pins &du1_pins>; - pinctrl-names = "default"; - - clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&x1_clk>, <&x2_clk>; - clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1"; - status = "okay"; - - ports { - port@0 { - endpoint { - remote-endpoint = <&adv7511_in>; - }; - }; - port@1 { - endpoint { - remote-endpoint = <&adv7123_in>; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/r8a7792-wheat.dts b/sys/gnu/dts/arm/r8a7792-wheat.dts deleted file mode 100644 index bd2a63bdab3..00000000000 --- a/sys/gnu/dts/arm/r8a7792-wheat.dts +++ /dev/null @@ -1,333 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the Wheat board - * - * Copyright (C) 2016 Renesas Electronics Corporation - * Copyright (C) 2016 Cogent Embedded, Inc. - */ - -/dts-v1/; -#include "r8a7792.dtsi" -#include -#include - -/ { - model = "Wheat"; - compatible = "renesas,wheat", "renesas,r8a7792"; - - aliases { - serial0 = &scif0; - }; - - chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; - stdout-path = "serial0:115200n8"; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0 0x40000000 0 0x40000000>; - }; - - d3_3v: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "D3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ethernet@18000000 { - compatible = "smsc,lan89218", "smsc,lan9115"; - reg = <0 0x18000000 0 0x100>; - phy-mode = "mii"; - interrupt-parent = <&irqc>; - interrupts = <0 IRQ_TYPE_EDGE_FALLING>; - smsc,irq-push-pull; - smsc,save-mac-address; - reg-io-width = <4>; - vddvario-supply = <&d3_3v>; - vdd33a-supply = <&d3_3v>; - - pinctrl-0 = <&lan89218_pins>; - pinctrl-names = "default"; - }; - - keyboard { - compatible = "gpio-keys"; - - key-a { - linux,code = ; - label = "SW2"; - wakeup-source; - debounce-interval = <20>; - gpios = <&gpio3 20 GPIO_ACTIVE_LOW>; - }; - key-b { - linux,code = ; - label = "SW3"; - wakeup-source; - debounce-interval = <20>; - gpios = <&gpio11 2 GPIO_ACTIVE_LOW>; - }; - }; - - vcc_sdhi0: regulator-vcc-sdhi0 { - compatible = "regulator-fixed"; - - regulator-name = "SDHI0 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&gpio11 12 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - hdmi-out0 { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con0: endpoint { - remote-endpoint = <&adv7513_0_out>; - }; - }; - }; - - hdmi-out1 { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con1: endpoint { - remote-endpoint = <&adv7513_1_out>; - }; - }; - }; - - osc2_clk: osc2 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <74250000>; - }; -}; - -&extal_clk { - clock-frequency = <20000000>; -}; - -&pfc { - scif0_pins: scif0 { - groups = "scif0_data"; - function = "scif0"; - }; - - lan89218_pins: lan89218 { - intc { - groups = "intc_irq0"; - function = "intc"; - }; - lbsc { - groups = "lbsc_ex_cs0"; - function = "lbsc"; - }; - }; - - can0_pins: can0 { - groups = "can0_data"; - function = "can0"; - }; - - can1_pins: can1 { - groups = "can1_data"; - function = "can1"; - }; - - sdhi0_pins: sdhi0 { - groups = "sdhi0_data4", "sdhi0_ctrl"; - function = "sdhi0"; - }; - - qspi_pins: qspi { - groups = "qspi_ctrl", "qspi_data4"; - function = "qspi"; - }; - - du0_pins: du0 { - groups = "du0_rgb888", "du0_sync", "du0_disp"; - function = "du0"; - }; - - du1_pins: du1 { - groups = "du1_rgb666", "du1_sync", "du1_disp"; - function = "du1"; - }; -}; - -&rwdt { - timeout-sec = <60>; - status = "okay"; -}; - -&scif0 { - pinctrl-0 = <&scif0_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&can0 { - pinctrl-0 = <&can0_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&can1 { - pinctrl-0 = <&can1_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&sdhi0 { - pinctrl-0 = <&sdhi0_pins>; - pinctrl-names = "default"; - - vmmc-supply = <&vcc_sdhi0>; - cd-gpios = <&gpio11 11 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&qspi { - pinctrl-0 = <&qspi_pins>; - pinctrl-names = "default"; - status = "okay"; - - flash@0 { - compatible = "spansion,s25fl512s", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <30000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - spi-cpol; - spi-cpha; - m25p,fast-read; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "loader"; - reg = <0x00000000 0x00040000>; - read-only; - }; - partition@40000 { - label = "user"; - reg = <0x00040000 0x00400000>; - read-only; - }; - partition@440000 { - label = "flash"; - reg = <0x00440000 0x03bc0000>; - }; - }; - }; -}; - -&i2c4 { - status = "okay"; - clock-frequency = <400000>; - - /* - * The adv75xx resets its addresses to defaults during low power mode. - * Because we have two ADV7513 devices on the same bus, we must change - * both of them away from the defaults so that they do not conflict. - */ - hdmi@3d { - compatible = "adi,adv7513"; - reg = <0x3d>, <0x2d>, <0x4d>, <0x5d>; - reg-names = "main", "cec", "edid", "packet"; - - adi,input-depth = <8>; - adi,input-colorspace = "rgb"; - adi,input-clock = "1x"; - adi,input-style = <1>; - adi,input-justification = "evenly"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7513_0_in: endpoint { - remote-endpoint = <&du_out_rgb0>; - }; - }; - - port@1 { - reg = <1>; - adv7513_0_out: endpoint { - remote-endpoint = <&hdmi_con0>; - }; - }; - }; - }; - - hdmi@39 { - compatible = "adi,adv7513"; - reg = <0x39>, <0x29>, <0x49>, <0x59>; - reg-names = "main", "cec", "edid", "packet"; - - adi,input-depth = <8>; - adi,input-colorspace = "rgb"; - adi,input-clock = "1x"; - adi,input-style = <1>; - adi,input-justification = "evenly"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7513_1_in: endpoint { - remote-endpoint = <&du_out_rgb1>; - }; - }; - - port@1 { - reg = <1>; - adv7513_1_out: endpoint { - remote-endpoint = <&hdmi_con1>; - }; - }; - }; - }; -}; - -&du { - pinctrl-0 = <&du0_pins &du1_pins>; - pinctrl-names = "default"; - - clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&osc2_clk>; - clock-names = "du.0", "du.1", "dclkin.0"; - status = "okay"; - - ports { - port@0 { - endpoint { - remote-endpoint = <&adv7513_0_in>; - }; - }; - port@1 { - endpoint { - remote-endpoint = <&adv7513_1_in>; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/r8a7792.dtsi b/sys/gnu/dts/arm/r8a7792.dtsi deleted file mode 100644 index 39af16caa2a..00000000000 --- a/sys/gnu/dts/arm/r8a7792.dtsi +++ /dev/null @@ -1,924 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the R-Car V2H (R8A77920) SoC - * - * Copyright (C) 2016 Cogent Embedded Inc. - */ - -#include -#include -#include -#include - -/ { - compatible = "renesas,r8a7792"; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - i2c6 = &iic3; - spi0 = &qspi; - spi1 = &msiof0; - spi2 = &msiof1; - vin0 = &vin0; - vin1 = &vin1; - vin2 = &vin2; - vin3 = &vin3; - vin4 = &vin4; - vin5 = &vin5; - }; - - /* External CAN clock */ - can_clk: can { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "renesas,apmu"; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0>; - clock-frequency = <1000000000>; - clocks = <&cpg CPG_CORE R8A7792_CLK_Z>; - power-domains = <&sysc R8A7792_PD_CA15_CPU0>; - next-level-cache = <&L2_CA15>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <1>; - clock-frequency = <1000000000>; - clocks = <&cpg CPG_CORE R8A7792_CLK_Z>; - power-domains = <&sysc R8A7792_PD_CA15_CPU1>; - next-level-cache = <&L2_CA15>; - }; - - L2_CA15: cache-controller-0 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - power-domains = <&sysc R8A7792_PD_CA15_SCU>; - }; - }; - - /* External root clock */ - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - pmu { - compatible = "arm,cortex-a15-pmu"; - interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&cpu0>, <&cpu1>; - }; - - /* External SCIF clock */ - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - soc { - compatible = "simple-bus"; - interrupt-parent = <&gic>; - - #address-cells = <2>; - #size-cells = <2>; - ranges; - - rwdt: watchdog@e6020000 { - compatible = "renesas,r8a7792-wdt", - "renesas,rcar-gen2-wdt"; - reg = <0 0xe6020000 0 0x0c>; - clocks = <&cpg CPG_MOD 402>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 402>; - status = "disabled"; - }; - - gpio0: gpio@e6050000 { - compatible = "renesas,gpio-r8a7792", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6050000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 0 29>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 912>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 912>; - }; - - gpio1: gpio@e6051000 { - compatible = "renesas,gpio-r8a7792", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6051000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 32 23>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 911>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 911>; - }; - - gpio2: gpio@e6052000 { - compatible = "renesas,gpio-r8a7792", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6052000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 64 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 910>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 910>; - }; - - gpio3: gpio@e6053000 { - compatible = "renesas,gpio-r8a7792", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6053000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 96 28>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 909>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 909>; - }; - - gpio4: gpio@e6054000 { - compatible = "renesas,gpio-r8a7792", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6054000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 128 17>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 908>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 908>; - }; - - gpio5: gpio@e6055000 { - compatible = "renesas,gpio-r8a7792", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6055000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 160 17>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 907>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 907>; - }; - - gpio6: gpio@e6055100 { - compatible = "renesas,gpio-r8a7792", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6055100 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 192 17>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 905>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 905>; - }; - - gpio7: gpio@e6055200 { - compatible = "renesas,gpio-r8a7792", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6055200 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 224 17>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 904>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 904>; - }; - - gpio8: gpio@e6055300 { - compatible = "renesas,gpio-r8a7792", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6055300 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 256 17>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 921>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 921>; - }; - - gpio9: gpio@e6055400 { - compatible = "renesas,gpio-r8a7792", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6055400 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 288 17>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 919>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 919>; - }; - - gpio10: gpio@e6055500 { - compatible = "renesas,gpio-r8a7792", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6055500 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 320 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 914>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 914>; - }; - - gpio11: gpio@e6055600 { - compatible = "renesas,gpio-r8a7792", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6055600 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 352 30>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 913>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 913>; - }; - - pfc: pin-controller@e6060000 { - compatible = "renesas,pfc-r8a7792"; - reg = <0 0xe6060000 0 0x144>; - }; - - cpg: clock-controller@e6150000 { - compatible = "renesas,r8a7792-cpg-mssr"; - reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk>; - clock-names = "extal"; - #clock-cells = <2>; - #power-domain-cells = <0>; - #reset-cells = <1>; - }; - - apmu@e6152000 { - compatible = "renesas,r8a7792-apmu", "renesas,apmu"; - reg = <0 0xe6152000 0 0x188>; - cpus = <&cpu0 &cpu1>; - }; - - rst: reset-controller@e6160000 { - compatible = "renesas,r8a7792-rst"; - reg = <0 0xe6160000 0 0x0100>; - }; - - sysc: system-controller@e6180000 { - compatible = "renesas,r8a7792-sysc"; - reg = <0 0xe6180000 0 0x0200>; - #power-domain-cells = <1>; - }; - - irqc: interrupt-controller@e61c0000 { - compatible = "renesas,irqc-r8a7792", "renesas,irqc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0 0xe61c0000 0 0x200>; - interrupts = , - , - , - ; - clocks = <&cpg CPG_MOD 407>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 407>; - }; - - icram0: sram@e63a0000 { - compatible = "mmio-sram"; - reg = <0 0xe63a0000 0 0x12000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0xe63a0000 0x12000>; - }; - - icram1: sram@e63c0000 { - compatible = "mmio-sram"; - reg = <0 0xe63c0000 0 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0xe63c0000 0x1000>; - - smp-sram@0 { - compatible = "renesas,smp-sram"; - reg = <0 0x100>; - }; - }; - - /* I2C doesn't need pinmux */ - i2c0: i2c@e6508000 { - compatible = "renesas,i2c-r8a7792", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6508000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 931>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 931>; - i2c-scl-internal-delay-ns = <6>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c1: i2c@e6518000 { - compatible = "renesas,i2c-r8a7792", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6518000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 930>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 930>; - i2c-scl-internal-delay-ns = <6>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@e6530000 { - compatible = "renesas,i2c-r8a7792", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6530000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 929>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 929>; - i2c-scl-internal-delay-ns = <6>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c3: i2c@e6540000 { - compatible = "renesas,i2c-r8a7792", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6540000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 928>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 928>; - i2c-scl-internal-delay-ns = <6>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c4: i2c@e6520000 { - compatible = "renesas,i2c-r8a7792", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6520000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 927>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 927>; - i2c-scl-internal-delay-ns = <6>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c5: i2c@e6528000 { - compatible = "renesas,i2c-r8a7792", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6528000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 925>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 925>; - i2c-scl-internal-delay-ns = <110>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - iic3: i2c@e60b0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7792", - "renesas,rcar-gen2-iic", - "renesas,rmobile-iic"; - reg = <0 0xe60b0000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 926>; - dmas = <&dmac0 0x77>, <&dmac0 0x78>, - <&dmac1 0x77>, <&dmac1 0x78>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 926>; - status = "disabled"; - }; - - dmac0: dma-controller@e6700000 { - compatible = "renesas,dmac-r8a7792", - "renesas,rcar-dmac"; - reg = <0 0xe6700000 0 0x20000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14"; - clocks = <&cpg CPG_MOD 219>; - clock-names = "fck"; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 219>; - #dma-cells = <1>; - dma-channels = <15>; - }; - - dmac1: dma-controller@e6720000 { - compatible = "renesas,dmac-r8a7792", - "renesas,rcar-dmac"; - reg = <0 0xe6720000 0 0x20000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14"; - clocks = <&cpg CPG_MOD 218>; - clock-names = "fck"; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 218>; - #dma-cells = <1>; - dma-channels = <15>; - }; - - avb: ethernet@e6800000 { - compatible = "renesas,etheravb-r8a7792", - "renesas,etheravb-rcar-gen2"; - reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; - interrupts = ; - clocks = <&cpg CPG_MOD 812>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 812>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - qspi: spi@e6b10000 { - compatible = "renesas,qspi-r8a7792", "renesas,qspi"; - reg = <0 0xe6b10000 0 0x2c>; - interrupts = ; - clocks = <&cpg CPG_MOD 917>; - dmas = <&dmac0 0x17>, <&dmac0 0x18>, - <&dmac1 0x17>, <&dmac1 0x18>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 917>; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - scif0: serial@e6e60000 { - compatible = "renesas,scif-r8a7792", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6e60000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 721>, - <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x29>, <&dmac0 0x2a>, - <&dmac1 0x29>, <&dmac1 0x2a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 721>; - status = "disabled"; - }; - - scif1: serial@e6e68000 { - compatible = "renesas,scif-r8a7792", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6e68000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 720>, - <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, - <&dmac1 0x2d>, <&dmac1 0x2e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 720>; - status = "disabled"; - }; - - scif2: serial@e6e58000 { - compatible = "renesas,scif-r8a7792", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6e58000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 719>, - <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, - <&dmac1 0x2b>, <&dmac1 0x2c>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 719>; - status = "disabled"; - }; - - scif3: serial@e6ea8000 { - compatible = "renesas,scif-r8a7792", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6ea8000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 718>, - <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2f>, <&dmac0 0x30>, - <&dmac1 0x2f>, <&dmac1 0x30>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 718>; - status = "disabled"; - }; - - hscif0: serial@e62c0000 { - compatible = "renesas,hscif-r8a7792", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62c0000 0 96>; - interrupts = ; - clocks = <&cpg CPG_MOD 717>, - <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x39>, <&dmac0 0x3a>, - <&dmac1 0x39>, <&dmac1 0x3a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 717>; - status = "disabled"; - }; - - hscif1: serial@e62c8000 { - compatible = "renesas,hscif-r8a7792", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62c8000 0 96>; - interrupts = ; - clocks = <&cpg CPG_MOD 716>, - <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, - <&dmac1 0x4d>, <&dmac1 0x4e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 716>; - status = "disabled"; - }; - - msiof0: spi@e6e20000 { - compatible = "renesas,msiof-r8a7792", - "renesas,rcar-gen2-msiof"; - reg = <0 0xe6e20000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 000>; - dmas = <&dmac0 0x51>, <&dmac0 0x52>, - <&dmac1 0x51>, <&dmac1 0x52>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof1: spi@e6e10000 { - compatible = "renesas,msiof-r8a7792", - "renesas,rcar-gen2-msiof"; - reg = <0 0xe6e10000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 208>; - dmas = <&dmac0 0x55>, <&dmac0 0x56>, - <&dmac1 0x55>, <&dmac1 0x56>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 208>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - can0: can@e6e80000 { - compatible = "renesas,can-r8a7792", - "renesas,rcar-gen2-can"; - reg = <0 0xe6e80000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 916>, - <&cpg CPG_CORE R8A7792_CLK_RCAN>, <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 916>; - status = "disabled"; - }; - - can1: can@e6e88000 { - compatible = "renesas,can-r8a7792", - "renesas,rcar-gen2-can"; - reg = <0 0xe6e88000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 915>, - <&cpg CPG_CORE R8A7792_CLK_RCAN>, <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 915>; - status = "disabled"; - }; - - vin0: video@e6ef0000 { - compatible = "renesas,vin-r8a7792", - "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef0000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 811>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 811>; - status = "disabled"; - }; - - vin1: video@e6ef1000 { - compatible = "renesas,vin-r8a7792", - "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef1000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 810>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 810>; - status = "disabled"; - }; - - vin2: video@e6ef2000 { - compatible = "renesas,vin-r8a7792", - "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef2000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 809>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 809>; - status = "disabled"; - }; - - vin3: video@e6ef3000 { - compatible = "renesas,vin-r8a7792", - "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef3000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 808>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 808>; - status = "disabled"; - }; - - vin4: video@e6ef4000 { - compatible = "renesas,vin-r8a7792", - "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef4000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 805>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 805>; - status = "disabled"; - }; - - vin5: video@e6ef5000 { - compatible = "renesas,vin-r8a7792", - "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef5000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 804>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 804>; - status = "disabled"; - }; - - sdhi0: sd@ee100000 { - compatible = "renesas,sdhi-r8a7792", - "renesas,rcar-gen2-sdhi"; - reg = <0 0xee100000 0 0x328>; - interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&dmac0 0xcd>, <&dmac0 0xce>, - <&dmac1 0xcd>, <&dmac1 0xce>; - dma-names = "tx", "rx", "tx", "rx"; - clocks = <&cpg CPG_MOD 314>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 314>; - status = "disabled"; - }; - - gic: interrupt-controller@f1001000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0 0xf1001000 0 0x1000>, - <0 0xf1002000 0 0x2000>, - <0 0xf1004000 0 0x2000>, - <0 0xf1006000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 408>; - clock-names = "clk"; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 408>; - }; - - vsp@fe928000 { - compatible = "renesas,vsp1"; - reg = <0 0xfe928000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 131>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 131>; - }; - - vsp@fe930000 { - compatible = "renesas,vsp1"; - reg = <0 0xfe930000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 128>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 128>; - }; - - vsp@fe938000 { - compatible = "renesas,vsp1"; - reg = <0 0xfe938000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 127>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 127>; - }; - - jpu: jpeg-codec@fe980000 { - compatible = "renesas,jpu-r8a7792", - "renesas,rcar-gen2-jpu"; - reg = <0 0xfe980000 0 0x10300>; - interrupts = ; - clocks = <&cpg CPG_MOD 106>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 106>; - }; - - du: display@feb00000 { - compatible = "renesas,du-r8a7792"; - reg = <0 0xfeb00000 0 0x40000>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>; - clock-names = "du.0", "du.1"; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - du_out_rgb0: endpoint { - }; - }; - port@1 { - reg = <1>; - du_out_rgb1: endpoint { - }; - }; - }; - }; - - prr: chipid@ff000044 { - compatible = "renesas,prr"; - reg = <0 0xff000044 0 4>; - }; - - cmt0: timer@ffca0000 { - compatible = "renesas,r8a7792-cmt0", - "renesas,rcar-gen2-cmt0"; - reg = <0 0xffca0000 0 0x1004>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 124>; - clock-names = "fck"; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 124>; - - status = "disabled"; - }; - - cmt1: timer@e6130000 { - compatible = "renesas,r8a7792-cmt1", - "renesas,rcar-gen2-cmt1"; - reg = <0 0xe6130000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 329>; - clock-names = "fck"; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 329>; - - status = "disabled"; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; - }; -}; diff --git a/sys/gnu/dts/arm/r8a7793-gose.dts b/sys/gnu/dts/arm/r8a7793-gose.dts deleted file mode 100644 index 22ca7cd1e7d..00000000000 --- a/sys/gnu/dts/arm/r8a7793-gose.dts +++ /dev/null @@ -1,807 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the Gose board - * - * Copyright (C) 2014-2015 Renesas Electronics Corporation - */ - -/* - * SSI-AK4643 - * - * SW1: 1: AK4643 - * 2: CN22 - * 3: ADV7511 - * - * This command is required when Playback/Capture - * - * amixer set "LINEOUT Mixer DACL" on - * amixer set "DVC Out" 100% - * amixer set "DVC In" 100% - * - * You can use Mute - * - * amixer set "DVC Out Mute" on - * amixer set "DVC In Mute" on - * - * You can use Volume Ramp - * - * amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps" - * amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps" - * amixer set "DVC Out Ramp" on - * aplay xxx.wav & - * amixer set "DVC Out" 80% // Volume Down - * amixer set "DVC Out" 100% // Volume Up - */ - -/dts-v1/; -#include "r8a7793.dtsi" -#include -#include - -/ { - model = "Gose"; - compatible = "renesas,gose", "renesas,r8a7793"; - - aliases { - serial0 = &scif0; - serial1 = &scif1; - i2c9 = &gpioi2c2; - i2c10 = &gpioi2c4; - i2c11 = &i2chdmi; - i2c12 = &i2cexio4; - }; - - chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; - stdout-path = "serial0:115200n8"; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0 0x40000000 0 0x40000000>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - key-1 { - gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW2-1"; - wakeup-source; - debounce-interval = <20>; - }; - key-2 { - gpios = <&gpio5 1 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW2-2"; - wakeup-source; - debounce-interval = <20>; - }; - key-3 { - gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW2-3"; - wakeup-source; - debounce-interval = <20>; - }; - key-4 { - gpios = <&gpio5 3 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW2-4"; - wakeup-source; - debounce-interval = <20>; - }; - key-a { - gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW30"; - wakeup-source; - debounce-interval = <20>; - }; - key-b { - gpios = <&gpio7 1 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW31"; - wakeup-source; - debounce-interval = <20>; - }; - key-c { - gpios = <&gpio7 2 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW32"; - wakeup-source; - debounce-interval = <20>; - }; - key-d { - gpios = <&gpio7 3 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW33"; - wakeup-source; - debounce-interval = <20>; - }; - key-e { - gpios = <&gpio7 4 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW34"; - wakeup-source; - debounce-interval = <20>; - }; - key-f { - gpios = <&gpio7 5 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW35"; - wakeup-source; - debounce-interval = <20>; - }; - key-g { - gpios = <&gpio7 6 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW36"; - wakeup-source; - debounce-interval = <20>; - }; - }; - - leds { - compatible = "gpio-leds"; - led6 { - gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>; - label = "LED6"; - }; - led7 { - gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; - label = "LED7"; - }; - led8 { - gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>; - label = "LED8"; - }; - }; - - vcc_sdhi0: regulator-vcc-sdhi0 { - compatible = "regulator-fixed"; - - regulator-name = "SDHI0 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&gpio7 17 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vccq_sdhi0: regulator-vccq-sdhi0 { - compatible = "regulator-gpio"; - - regulator-name = "SDHI0 VccQ"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>; - gpios-states = <1>; - states = <3300000 1>, <1800000 0>; - }; - - vcc_sdhi1: regulator-vcc-sdhi1 { - compatible = "regulator-fixed"; - - regulator-name = "SDHI1 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&gpio7 18 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vccq_sdhi1: regulator-vccq-sdhi1 { - compatible = "regulator-gpio"; - - regulator-name = "SDHI1 VccQ"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>; - gpios-states = <1>; - states = <3300000 1>, <1800000 0>; - }; - - vcc_sdhi2: regulator-vcc-sdhi2 { - compatible = "regulator-fixed"; - - regulator-name = "SDHI2 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&gpio7 19 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vccq_sdhi2: regulator-vccq-sdhi2 { - compatible = "regulator-gpio"; - - regulator-name = "SDHI2 VccQ"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>; - gpios-states = <1>; - states = <3300000 1>, <1800000 0>; - }; - - audio_clock: audio_clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <11289600>; - }; - - rsnd_ak4643: sound { - compatible = "simple-audio-card"; - - simple-audio-card,format = "left_j"; - simple-audio-card,bitclock-master = <&sndcodec>; - simple-audio-card,frame-master = <&sndcodec>; - - sndcpu: simple-audio-card,cpu { - sound-dai = <&rcar_sound>; - }; - - sndcodec: simple-audio-card,codec { - sound-dai = <&ak4643>; - clocks = <&audio_clock>; - }; - }; - - hdmi-in { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&adv7612_in>; - }; - }; - }; - - hdmi-out { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_out: endpoint { - remote-endpoint = <&adv7511_out>; - }; - }; - }; - - composite-in { - compatible = "composite-video-connector"; - - port { - composite_con_in: endpoint { - remote-endpoint = <&adv7180_in>; - }; - }; - }; - - x2_clk: x2-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <74250000>; - }; - - x13_clk: x13-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <148500000>; - }; - - gpioi2c2: i2c-9 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "i2c-gpio"; - status = "disabled"; - scl-gpios = <&gpio2 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio2 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <5>; - }; - - gpioi2c4: i2c-10 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "i2c-gpio"; - status = "disabled"; - scl-gpios = <&gpio7 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio7 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <5>; - }; - - /* - * A fallback to GPIO is provided for I2C2. - */ - i2chdmi: i2c-11 { - compatible = "i2c-demux-pinctrl"; - i2c-parent = <&i2c2>, <&gpioi2c2>; - i2c-bus-name = "i2c-hdmi"; - #address-cells = <1>; - #size-cells = <0>; - - ak4643: codec@12 { - compatible = "asahi-kasei,ak4643"; - #sound-dai-cells = <0>; - reg = <0x12>; - }; - - composite-in@20 { - compatible = "adi,adv7180cp"; - reg = <0x20>; - remote = <&vin1>; - - port { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7180_in: endpoint { - remote-endpoint = <&composite_con_in>; - }; - }; - - port@3 { - reg = <3>; - adv7180_out: endpoint { - bus-width = <8>; - remote-endpoint = <&vin1ep>; - }; - }; - }; - }; - - hdmi@39 { - compatible = "adi,adv7511w"; - reg = <0x39>; - interrupt-parent = <&gpio3>; - interrupts = <29 IRQ_TYPE_LEVEL_LOW>; - - adi,input-depth = <8>; - adi,input-colorspace = "rgb"; - adi,input-clock = "1x"; - adi,input-style = <1>; - adi,input-justification = "evenly"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7511_in: endpoint { - remote-endpoint = <&du_out_rgb>; - }; - }; - - port@1 { - reg = <1>; - adv7511_out: endpoint { - remote-endpoint = <&hdmi_con_out>; - }; - }; - }; - }; - - hdmi-in@4c { - compatible = "adi,adv7612"; - reg = <0x4c>; - interrupt-parent = <&gpio4>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - default-input = <0>; - - port { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7612_in: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; - }; - - port@2 { - reg = <2>; - adv7612_out: endpoint { - remote-endpoint = <&vin0ep2>; - }; - }; - }; - }; - - eeprom@50 { - compatible = "renesas,r1ex24002", "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; - }; - - /* - * I2C4 is routed to EXIO connector E, pins 37 (SCL) + 39 (SDA). - * A fallback to GPIO is provided. - */ - i2cexio4: i2c-12 { - compatible = "i2c-demux-pinctrl"; - i2c-parent = <&i2c4>, <&gpioi2c4>; - i2c-bus-name = "i2c-exio4"; - #address-cells = <1>; - #size-cells = <0>; - }; -}; - -&du { - pinctrl-0 = <&du_pins>; - pinctrl-names = "default"; - status = "okay"; - - clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, - <&x13_clk>, <&x2_clk>; - clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1"; - - ports { - port@0 { - endpoint { - remote-endpoint = <&adv7511_in>; - }; - }; - }; -}; - -&lvds0 { - ports { - port@1 { - lvds_connector: endpoint { - }; - }; - }; -}; - -&extal_clk { - clock-frequency = <20000000>; -}; - -&pfc { - pinctrl-0 = <&scif_clk_pins>; - pinctrl-names = "default"; - - i2c2_pins: i2c2 { - groups = "i2c2"; - function = "i2c2"; - }; - - i2c4_pins: i2c4 { - groups = "i2c4_c"; - function = "i2c4"; - }; - - du_pins: du { - groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0"; - function = "du"; - }; - - scif0_pins: scif0 { - groups = "scif0_data_d"; - function = "scif0"; - }; - - scif1_pins: scif1 { - groups = "scif1_data_d"; - function = "scif1"; - }; - - scif_clk_pins: scif_clk { - groups = "scif_clk"; - function = "scif_clk"; - }; - - ether_pins: ether { - groups = "eth_link", "eth_mdio", "eth_rmii"; - function = "eth"; - }; - - phy1_pins: phy1 { - groups = "intc_irq0"; - function = "intc"; - }; - - pmic_irq_pins: pmicirq { - groups = "intc_irq2"; - function = "intc"; - }; - - sdhi0_pins: sd0 { - groups = "sdhi0_data4", "sdhi0_ctrl"; - function = "sdhi0"; - power-source = <3300>; - }; - - sdhi0_pins_uhs: sd0_uhs { - groups = "sdhi0_data4", "sdhi0_ctrl"; - function = "sdhi0"; - power-source = <1800>; - }; - - sdhi1_pins: sd1 { - groups = "sdhi1_data4", "sdhi1_ctrl"; - function = "sdhi1"; - power-source = <3300>; - }; - - sdhi1_pins_uhs: sd1_uhs { - groups = "sdhi1_data4", "sdhi1_ctrl"; - function = "sdhi1"; - power-source = <1800>; - }; - - sdhi2_pins: sd2 { - groups = "sdhi2_data4", "sdhi2_ctrl"; - function = "sdhi2"; - power-source = <3300>; - }; - - sdhi2_pins_uhs: sd2_uhs { - groups = "sdhi2_data4", "sdhi2_ctrl"; - function = "sdhi2"; - power-source = <1800>; - }; - - qspi_pins: qspi { - groups = "qspi_ctrl", "qspi_data4"; - function = "qspi"; - }; - - sound_pins: sound { - groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data"; - function = "ssi"; - }; - - sound_clk_pins: sound_clk { - groups = "audio_clk_a"; - function = "audio_clk"; - }; - - vin0_pins: vin0 { - groups = "vin0_data24", "vin0_sync", "vin0_clkenb", "vin0_clk"; - function = "vin0"; - }; - - vin1_pins: vin1 { - groups = "vin1_data8", "vin1_clk"; - function = "vin1"; - }; -}; - -ðer { - pinctrl-0 = <ðer_pins &phy1_pins>; - pinctrl-names = "default"; - - phy-handle = <&phy1>; - renesas,ether-link-active-low; - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - interrupt-parent = <&irqc0>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - micrel,led-mode = <1>; - }; -}; - -&cmt0 { - status = "okay"; -}; - -&cpu0 { - cpu0-supply = <&vdd_dvfs>; -}; - -&rwdt { - timeout-sec = <60>; - status = "okay"; -}; - -&scif0 { - pinctrl-0 = <&scif0_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&scif1 { - pinctrl-0 = <&scif1_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&scif_clk { - clock-frequency = <14745600>; -}; - -&sdhi0 { - pinctrl-0 = <&sdhi0_pins>; - pinctrl-1 = <&sdhi0_pins_uhs>; - pinctrl-names = "default", "state_uhs"; - - vmmc-supply = <&vcc_sdhi0>; - vqmmc-supply = <&vccq_sdhi0>; - cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; - sd-uhs-sdr50; - sd-uhs-sdr104; - status = "okay"; -}; - -&sdhi1 { - pinctrl-0 = <&sdhi1_pins>; - pinctrl-1 = <&sdhi1_pins_uhs>; - pinctrl-names = "default", "state_uhs"; - - vmmc-supply = <&vcc_sdhi1>; - vqmmc-supply = <&vccq_sdhi1>; - cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>; - sd-uhs-sdr50; - status = "okay"; -}; - -&sdhi2 { - pinctrl-0 = <&sdhi2_pins>; - pinctrl-1 = <&sdhi2_pins_uhs>; - pinctrl-names = "default", "state_uhs"; - - vmmc-supply = <&vcc_sdhi2>; - vqmmc-supply = <&vccq_sdhi2>; - cd-gpios = <&gpio6 22 GPIO_ACTIVE_LOW>; - sd-uhs-sdr50; - status = "okay"; -}; - -&qspi { - pinctrl-0 = <&qspi_pins>; - pinctrl-names = "default"; - - status = "okay"; - - flash@0 { - compatible = "spansion,s25fl512s", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <30000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - spi-cpol; - spi-cpha; - m25p,fast-read; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "loader"; - reg = <0x00000000 0x00040000>; - read-only; - }; - partition@40000 { - label = "user"; - reg = <0x00040000 0x00400000>; - read-only; - }; - partition@440000 { - label = "flash"; - reg = <0x00440000 0x03bc0000>; - }; - }; - }; -}; - -&i2c2 { - pinctrl-0 = <&i2c2_pins>; - pinctrl-names = "i2c-hdmi"; - - status = "okay"; - clock-frequency = <100000>; - -}; - -&i2c6 { - pinctrl-names = "default"; - pinctrl-0 = <&pmic_irq_pins>; - status = "okay"; - clock-frequency = <100000>; - - pmic@58 { - compatible = "dlg,da9063"; - reg = <0x58>; - interrupt-parent = <&irqc0>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - - rtc { - compatible = "dlg,da9063-rtc"; - }; - - wdt { - compatible = "dlg,da9063-watchdog"; - }; - }; - - vdd_dvfs: regulator@68 { - compatible = "dlg,da9210"; - reg = <0x68>; - interrupt-parent = <&irqc0>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-boot-on; - regulator-always-on; - }; -}; - -&i2c4 { - pinctrl-0 = <&i2c4_pins>; - pinctrl-names = "i2c-exio4"; -}; - -&rcar_sound { - pinctrl-0 = <&sound_pins &sound_clk_pins>; - pinctrl-names = "default"; - - /* Single DAI */ - #sound-dai-cells = <0>; - - status = "okay"; - - rcar_sound,dai { - dai0 { - playback = <&ssi0 &src2 &dvc0>; - capture = <&ssi1 &src3 &dvc1>; - }; - }; -}; - -&ssi1 { - shared-pin; -}; - -/* HDMI video input */ -&vin0 { - status = "okay"; - pinctrl-0 = <&vin0_pins>; - pinctrl-names = "default"; - - port { - vin0ep2: endpoint { - remote-endpoint = <&adv7612_out>; - bus-width = <24>; - hsync-active = <0>; - vsync-active = <0>; - pclk-sample = <1>; - data-active = <1>; - }; - }; -}; - -/* composite video input */ -&vin1 { - pinctrl-0 = <&vin1_pins>; - pinctrl-names = "default"; - - status = "okay"; - - port { - vin1ep: endpoint { - remote-endpoint = <&adv7180_out>; - bus-width = <8>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/r8a7793.dtsi b/sys/gnu/dts/arm/r8a7793.dtsi deleted file mode 100644 index eef035c4d98..00000000000 --- a/sys/gnu/dts/arm/r8a7793.dtsi +++ /dev/null @@ -1,1467 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the R-Car M2-N (R8A77930) SoC - * - * Copyright (C) 2014-2015 Renesas Electronics Corporation - */ - -#include -#include -#include -#include - -/ { - compatible = "renesas,r8a7793"; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - i2c6 = &i2c6; - i2c7 = &i2c7; - i2c8 = &i2c8; - spi0 = &qspi; - }; - - /* - * The external audio clocks are configured as 0 Hz fixed frequency - * clocks by default. - * Boards that provide audio clocks should override them. - */ - audio_clk_a: audio_clk_a { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - audio_clk_b: audio_clk_b { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - audio_clk_c: audio_clk_c { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - /* External CAN clock */ - can_clk: can { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "renesas,apmu"; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0>; - clock-frequency = <1500000000>; - clocks = <&cpg CPG_CORE R8A7793_CLK_Z>; - power-domains = <&sysc R8A7793_PD_CA15_CPU0>; - voltage-tolerance = <1>; /* 1% */ - clock-latency = <300000>; /* 300 us */ - - /* kHz - uV - OPPs unknown yet */ - operating-points = <1500000 1000000>, - <1312500 1000000>, - <1125000 1000000>, - < 937500 1000000>, - < 750000 1000000>, - < 375000 1000000>; - next-level-cache = <&L2_CA15>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <1>; - clock-frequency = <1500000000>; - clocks = <&cpg CPG_CORE R8A7793_CLK_Z>; - power-domains = <&sysc R8A7793_PD_CA15_CPU1>; - voltage-tolerance = <1>; /* 1% */ - clock-latency = <300000>; /* 300 us */ - - /* kHz - uV - OPPs unknown yet */ - operating-points = <1500000 1000000>, - <1312500 1000000>, - <1125000 1000000>, - < 937500 1000000>, - < 750000 1000000>, - < 375000 1000000>; - next-level-cache = <&L2_CA15>; - }; - - L2_CA15: cache-controller-0 { - compatible = "cache"; - power-domains = <&sysc R8A7793_PD_CA15_SCU>; - cache-unified; - cache-level = <2>; - }; - }; - - /* External root clock */ - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - pmu { - compatible = "arm,cortex-a15-pmu"; - interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&cpu0>, <&cpu1>; - }; - - /* External SCIF clock */ - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - soc { - compatible = "simple-bus"; - interrupt-parent = <&gic>; - - #address-cells = <2>; - #size-cells = <2>; - ranges; - - rwdt: watchdog@e6020000 { - compatible = "renesas,r8a7793-wdt", - "renesas,rcar-gen2-wdt"; - reg = <0 0xe6020000 0 0x0c>; - clocks = <&cpg CPG_MOD 402>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 402>; - status = "disabled"; - }; - - gpio0: gpio@e6050000 { - compatible = "renesas,gpio-r8a7793", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6050000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 0 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 912>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 912>; - }; - - gpio1: gpio@e6051000 { - compatible = "renesas,gpio-r8a7793", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6051000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 32 26>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 911>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 911>; - }; - - gpio2: gpio@e6052000 { - compatible = "renesas,gpio-r8a7793", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6052000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 64 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 910>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 910>; - }; - - gpio3: gpio@e6053000 { - compatible = "renesas,gpio-r8a7793", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6053000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 96 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 909>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 909>; - }; - - gpio4: gpio@e6054000 { - compatible = "renesas,gpio-r8a7793", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6054000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 128 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 908>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 908>; - }; - - gpio5: gpio@e6055000 { - compatible = "renesas,gpio-r8a7793", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6055000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 160 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 907>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 907>; - }; - - gpio6: gpio@e6055400 { - compatible = "renesas,gpio-r8a7793", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6055400 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 192 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 905>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 905>; - }; - - gpio7: gpio@e6055800 { - compatible = "renesas,gpio-r8a7793", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6055800 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 224 26>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 904>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 904>; - }; - - pfc: pin-controller@e6060000 { - compatible = "renesas,pfc-r8a7793"; - reg = <0 0xe6060000 0 0x250>; - }; - - /* Special CPG clocks */ - cpg: clock-controller@e6150000 { - compatible = "renesas,r8a7793-cpg-mssr"; - reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk>, <&usb_extal_clk>; - clock-names = "extal", "usb_extal"; - #clock-cells = <2>; - #power-domain-cells = <0>; - #reset-cells = <1>; - }; - - apmu@e6152000 { - compatible = "renesas,r8a7793-apmu", "renesas,apmu"; - reg = <0 0xe6152000 0 0x188>; - cpus = <&cpu0 &cpu1>; - }; - - rst: reset-controller@e6160000 { - compatible = "renesas,r8a7793-rst"; - reg = <0 0xe6160000 0 0x0100>; - }; - - sysc: system-controller@e6180000 { - compatible = "renesas,r8a7793-sysc"; - reg = <0 0xe6180000 0 0x0200>; - #power-domain-cells = <1>; - }; - - irqc0: interrupt-controller@e61c0000 { - compatible = "renesas,irqc-r8a7793", "renesas,irqc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0 0xe61c0000 0 0x200>; - interrupts = , - , - , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 407>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 407>; - }; - - thermal: thermal@e61f0000 { - compatible = "renesas,thermal-r8a7793", - "renesas,rcar-gen2-thermal", - "renesas,rcar-thermal"; - reg = <0 0xe61f0000 0 0x10>, <0 0xe61f0100 0 0x38>; - interrupts = ; - clocks = <&cpg CPG_MOD 522>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 522>; - #thermal-sensor-cells = <0>; - }; - - ipmmu_sy0: mmu@e6280000 { - compatible = "renesas,ipmmu-r8a7793", - "renesas,ipmmu-vmsa"; - reg = <0 0xe6280000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_sy1: mmu@e6290000 { - compatible = "renesas,ipmmu-r8a7793", - "renesas,ipmmu-vmsa"; - reg = <0 0xe6290000 0 0x1000>; - interrupts = ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_ds: mmu@e6740000 { - compatible = "renesas,ipmmu-r8a7793", - "renesas,ipmmu-vmsa"; - reg = <0 0xe6740000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_mp: mmu@ec680000 { - compatible = "renesas,ipmmu-r8a7793", - "renesas,ipmmu-vmsa"; - reg = <0 0xec680000 0 0x1000>; - interrupts = ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_mx: mmu@fe951000 { - compatible = "renesas,ipmmu-r8a7793", - "renesas,ipmmu-vmsa"; - reg = <0 0xfe951000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_rt: mmu@ffc80000 { - compatible = "renesas,ipmmu-r8a7793", - "renesas,ipmmu-vmsa"; - reg = <0 0xffc80000 0 0x1000>; - interrupts = ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_gp: mmu@e62a0000 { - compatible = "renesas,ipmmu-r8a7793", - "renesas,ipmmu-vmsa"; - reg = <0 0xe62a0000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; - - icram0: sram@e63a0000 { - compatible = "mmio-sram"; - reg = <0 0xe63a0000 0 0x12000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0xe63a0000 0x12000>; - }; - - icram1: sram@e63c0000 { - compatible = "mmio-sram"; - reg = <0 0xe63c0000 0 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0xe63c0000 0x1000>; - - smp-sram@0 { - compatible = "renesas,smp-sram"; - reg = <0 0x100>; - }; - }; - - /* The memory map in the User's Manual maps the cores to - * bus numbers - */ - i2c0: i2c@e6508000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7793", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6508000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 931>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 931>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c1: i2c@e6518000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7793", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6518000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 930>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 930>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c2: i2c@e6530000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7793", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6530000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 929>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 929>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c3: i2c@e6540000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7793", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6540000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 928>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 928>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c4: i2c@e6520000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7793", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6520000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 927>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 927>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c5: i2c@e6528000 { - /* doesn't need pinmux */ - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7793", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6528000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 925>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 925>; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c6: i2c@e60b0000 { - /* doesn't need pinmux */ - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7793", - "renesas,rcar-gen2-iic", - "renesas,rmobile-iic"; - reg = <0 0xe60b0000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 926>; - dmas = <&dmac0 0x77>, <&dmac0 0x78>, - <&dmac1 0x77>, <&dmac1 0x78>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 926>; - status = "disabled"; - }; - - i2c7: i2c@e6500000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7793", - "renesas,rcar-gen2-iic", - "renesas,rmobile-iic"; - reg = <0 0xe6500000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 318>; - dmas = <&dmac0 0x61>, <&dmac0 0x62>, - <&dmac1 0x61>, <&dmac1 0x62>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 318>; - status = "disabled"; - }; - - i2c8: i2c@e6510000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7793", - "renesas,rcar-gen2-iic", - "renesas,rmobile-iic"; - reg = <0 0xe6510000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 323>; - dmas = <&dmac0 0x65>, <&dmac0 0x66>, - <&dmac1 0x65>, <&dmac1 0x66>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 323>; - status = "disabled"; - }; - - dmac0: dma-controller@e6700000 { - compatible = "renesas,dmac-r8a7793", - "renesas,rcar-dmac"; - reg = <0 0xe6700000 0 0x20000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14"; - clocks = <&cpg CPG_MOD 219>; - clock-names = "fck"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 219>; - #dma-cells = <1>; - dma-channels = <15>; - }; - - dmac1: dma-controller@e6720000 { - compatible = "renesas,dmac-r8a7793", - "renesas,rcar-dmac"; - reg = <0 0xe6720000 0 0x20000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14"; - clocks = <&cpg CPG_MOD 218>; - clock-names = "fck"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 218>; - #dma-cells = <1>; - dma-channels = <15>; - }; - - qspi: spi@e6b10000 { - compatible = "renesas,qspi-r8a7793", "renesas,qspi"; - reg = <0 0xe6b10000 0 0x2c>; - interrupts = ; - clocks = <&cpg CPG_MOD 917>; - dmas = <&dmac0 0x17>, <&dmac0 0x18>, - <&dmac1 0x17>, <&dmac1 0x18>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 917>; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - scifa0: serial@e6c40000 { - compatible = "renesas,scifa-r8a7793", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c40000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 204>; - clock-names = "fck"; - dmas = <&dmac0 0x21>, <&dmac0 0x22>, - <&dmac1 0x21>, <&dmac1 0x22>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 204>; - status = "disabled"; - }; - - scifa1: serial@e6c50000 { - compatible = "renesas,scifa-r8a7793", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c50000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 203>; - clock-names = "fck"; - dmas = <&dmac0 0x25>, <&dmac0 0x26>, - <&dmac1 0x25>, <&dmac1 0x26>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 203>; - status = "disabled"; - }; - - scifa2: serial@e6c60000 { - compatible = "renesas,scifa-r8a7793", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c60000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 202>; - clock-names = "fck"; - dmas = <&dmac0 0x27>, <&dmac0 0x28>, - <&dmac1 0x27>, <&dmac1 0x28>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 202>; - status = "disabled"; - }; - - scifa3: serial@e6c70000 { - compatible = "renesas,scifa-r8a7793", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c70000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 1106>; - clock-names = "fck"; - dmas = <&dmac0 0x1b>, <&dmac0 0x1c>, - <&dmac1 0x1b>, <&dmac1 0x1c>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 1106>; - status = "disabled"; - }; - - scifa4: serial@e6c78000 { - compatible = "renesas,scifa-r8a7793", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c78000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 1107>; - clock-names = "fck"; - dmas = <&dmac0 0x1f>, <&dmac0 0x20>, - <&dmac1 0x1f>, <&dmac1 0x20>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 1107>; - status = "disabled"; - }; - - scifa5: serial@e6c80000 { - compatible = "renesas,scifa-r8a7793", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c80000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 1108>; - clock-names = "fck"; - dmas = <&dmac0 0x23>, <&dmac0 0x24>, - <&dmac1 0x23>, <&dmac1 0x24>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 1108>; - status = "disabled"; - }; - - scifb0: serial@e6c20000 { - compatible = "renesas,scifb-r8a7793", - "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6c20000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 206>; - clock-names = "fck"; - dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, - <&dmac1 0x3d>, <&dmac1 0x3e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 206>; - status = "disabled"; - }; - - scifb1: serial@e6c30000 { - compatible = "renesas,scifb-r8a7793", - "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6c30000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 207>; - clock-names = "fck"; - dmas = <&dmac0 0x19>, <&dmac0 0x1a>, - <&dmac1 0x19>, <&dmac1 0x1a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 207>; - status = "disabled"; - }; - - scifb2: serial@e6ce0000 { - compatible = "renesas,scifb-r8a7793", - "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6ce0000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 216>; - clock-names = "fck"; - dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, - <&dmac1 0x1d>, <&dmac1 0x1e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 216>; - status = "disabled"; - }; - - scif0: serial@e6e60000 { - compatible = "renesas,scif-r8a7793", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6e60000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7793_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x29>, <&dmac0 0x2a>, - <&dmac1 0x29>, <&dmac1 0x2a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 721>; - status = "disabled"; - }; - - scif1: serial@e6e68000 { - compatible = "renesas,scif-r8a7793", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6e68000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 720>, <&cpg CPG_CORE R8A7793_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, - <&dmac1 0x2d>, <&dmac1 0x2e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 720>; - status = "disabled"; - }; - - scif2: serial@e6e58000 { - compatible = "renesas,scif-r8a7793", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6e58000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 719>, <&cpg CPG_CORE R8A7793_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, - <&dmac1 0x2b>, <&dmac1 0x2c>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 719>; - status = "disabled"; - }; - - scif3: serial@e6ea8000 { - compatible = "renesas,scif-r8a7793", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6ea8000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 718>, <&cpg CPG_CORE R8A7793_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2f>, <&dmac0 0x30>, - <&dmac1 0x2f>, <&dmac1 0x30>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 718>; - status = "disabled"; - }; - - scif4: serial@e6ee0000 { - compatible = "renesas,scif-r8a7793", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6ee0000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 715>, <&cpg CPG_CORE R8A7793_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0xfb>, <&dmac0 0xfc>, - <&dmac1 0xfb>, <&dmac1 0xfc>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 715>; - status = "disabled"; - }; - - scif5: serial@e6ee8000 { - compatible = "renesas,scif-r8a7793", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6ee8000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 714>, <&cpg CPG_CORE R8A7793_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0xfd>, <&dmac0 0xfe>, - <&dmac1 0xfd>, <&dmac1 0xfe>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 714>; - status = "disabled"; - }; - - hscif0: serial@e62c0000 { - compatible = "renesas,hscif-r8a7793", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62c0000 0 96>; - interrupts = ; - clocks = <&cpg CPG_MOD 717>, <&cpg CPG_CORE R8A7793_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x39>, <&dmac0 0x3a>, - <&dmac1 0x39>, <&dmac1 0x3a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 717>; - status = "disabled"; - }; - - hscif1: serial@e62c8000 { - compatible = "renesas,hscif-r8a7793", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62c8000 0 96>; - interrupts = ; - clocks = <&cpg CPG_MOD 716>, <&cpg CPG_CORE R8A7793_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, - <&dmac1 0x4d>, <&dmac1 0x4e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 716>; - status = "disabled"; - }; - - hscif2: serial@e62d0000 { - compatible = "renesas,hscif-r8a7793", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62d0000 0 96>; - interrupts = ; - clocks = <&cpg CPG_MOD 713>, <&cpg CPG_CORE R8A7793_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x3b>, <&dmac0 0x3c>, - <&dmac1 0x3b>, <&dmac1 0x3c>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 713>; - status = "disabled"; - }; - - can0: can@e6e80000 { - compatible = "renesas,can-r8a7793", - "renesas,rcar-gen2-can"; - reg = <0 0xe6e80000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 916>, <&cpg CPG_CORE R8A7793_CLK_RCAN>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 916>; - status = "disabled"; - }; - - can1: can@e6e88000 { - compatible = "renesas,can-r8a7793", - "renesas,rcar-gen2-can"; - reg = <0 0xe6e88000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 915>, <&cpg CPG_CORE R8A7793_CLK_RCAN>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 915>; - status = "disabled"; - }; - - vin0: video@e6ef0000 { - compatible = "renesas,vin-r8a7793", - "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef0000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 811>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 811>; - status = "disabled"; - }; - - vin1: video@e6ef1000 { - compatible = "renesas,vin-r8a7793", - "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef1000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 810>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 810>; - status = "disabled"; - }; - - vin2: video@e6ef2000 { - compatible = "renesas,vin-r8a7793", - "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef2000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 809>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 809>; - status = "disabled"; - }; - - rcar_sound: sound@ec500000 { - /* - * #sound-dai-cells is required - * - * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; - * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; - */ - compatible = "renesas,rcar_sound-r8a7793", - "renesas,rcar_sound-gen2"; - reg = <0 0xec500000 0 0x1000>, /* SCU */ - <0 0xec5a0000 0 0x100>, /* ADG */ - <0 0xec540000 0 0x1000>, /* SSIU */ - <0 0xec541000 0 0x280>, /* SSI */ - <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ - reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; - - clocks = <&cpg CPG_MOD 1005>, - <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, - <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, - <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, - <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, - <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, - <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, - <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, - <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, - <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, - <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, - <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, - <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, - <&cpg CPG_CORE R8A7793_CLK_M2>; - clock-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", - "ssi.5", "ssi.4", "ssi.3", "ssi.2", - "ssi.1", "ssi.0", - "src.9", "src.8", "src.7", "src.6", - "src.5", "src.4", "src.3", "src.2", - "src.1", "src.0", - "dvc.0", "dvc.1", - "clk_a", "clk_b", "clk_c", "clk_i"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 1005>, - <&cpg 1006>, <&cpg 1007>, - <&cpg 1008>, <&cpg 1009>, - <&cpg 1010>, <&cpg 1011>, - <&cpg 1012>, <&cpg 1013>, - <&cpg 1014>, <&cpg 1015>; - reset-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", - "ssi.5", "ssi.4", "ssi.3", "ssi.2", - "ssi.1", "ssi.0"; - - status = "disabled"; - - rcar_sound,dvc { - dvc0: dvc-0 { - dmas = <&audma1 0xbc>; - dma-names = "tx"; - }; - dvc1: dvc-1 { - dmas = <&audma1 0xbe>; - dma-names = "tx"; - }; - }; - - rcar_sound,src { - src0: src-0 { - interrupts = ; - dmas = <&audma0 0x85>, <&audma1 0x9a>; - dma-names = "rx", "tx"; - }; - src1: src-1 { - interrupts = ; - dmas = <&audma0 0x87>, <&audma1 0x9c>; - dma-names = "rx", "tx"; - }; - src2: src-2 { - interrupts = ; - dmas = <&audma0 0x89>, <&audma1 0x9e>; - dma-names = "rx", "tx"; - }; - src3: src-3 { - interrupts = ; - dmas = <&audma0 0x8b>, <&audma1 0xa0>; - dma-names = "rx", "tx"; - }; - src4: src-4 { - interrupts = ; - dmas = <&audma0 0x8d>, <&audma1 0xb0>; - dma-names = "rx", "tx"; - }; - src5: src-5 { - interrupts = ; - dmas = <&audma0 0x8f>, <&audma1 0xb2>; - dma-names = "rx", "tx"; - }; - src6: src-6 { - interrupts = ; - dmas = <&audma0 0x91>, <&audma1 0xb4>; - dma-names = "rx", "tx"; - }; - src7: src-7 { - interrupts = ; - dmas = <&audma0 0x93>, <&audma1 0xb6>; - dma-names = "rx", "tx"; - }; - src8: src-8 { - interrupts = ; - dmas = <&audma0 0x95>, <&audma1 0xb8>; - dma-names = "rx", "tx"; - }; - src9: src-9 { - interrupts = ; - dmas = <&audma0 0x97>, <&audma1 0xba>; - dma-names = "rx", "tx"; - }; - }; - - rcar_sound,ssi { - ssi0: ssi-0 { - interrupts = ; - dmas = <&audma0 0x01>, <&audma1 0x02>, - <&audma0 0x15>, <&audma1 0x16>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi1: ssi-1 { - interrupts = ; - dmas = <&audma0 0x03>, <&audma1 0x04>, - <&audma0 0x49>, <&audma1 0x4a>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi2: ssi-2 { - interrupts = ; - dmas = <&audma0 0x05>, <&audma1 0x06>, - <&audma0 0x63>, <&audma1 0x64>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi3: ssi-3 { - interrupts = ; - dmas = <&audma0 0x07>, <&audma1 0x08>, - <&audma0 0x6f>, <&audma1 0x70>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi4: ssi-4 { - interrupts = ; - dmas = <&audma0 0x09>, <&audma1 0x0a>, - <&audma0 0x71>, <&audma1 0x72>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi5: ssi-5 { - interrupts = ; - dmas = <&audma0 0x0b>, <&audma1 0x0c>, - <&audma0 0x73>, <&audma1 0x74>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi6: ssi-6 { - interrupts = ; - dmas = <&audma0 0x0d>, <&audma1 0x0e>, - <&audma0 0x75>, <&audma1 0x76>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi7: ssi-7 { - interrupts = ; - dmas = <&audma0 0x0f>, <&audma1 0x10>, - <&audma0 0x79>, <&audma1 0x7a>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi8: ssi-8 { - interrupts = ; - dmas = <&audma0 0x11>, <&audma1 0x12>, - <&audma0 0x7b>, <&audma1 0x7c>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi9: ssi-9 { - interrupts = ; - dmas = <&audma0 0x13>, <&audma1 0x14>, - <&audma0 0x7d>, <&audma1 0x7e>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - }; - }; - - audma0: dma-controller@ec700000 { - compatible = "renesas,dmac-r8a7793", - "renesas,rcar-dmac"; - reg = <0 0xec700000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12"; - clocks = <&cpg CPG_MOD 502>; - clock-names = "fck"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 502>; - #dma-cells = <1>; - dma-channels = <13>; - }; - - audma1: dma-controller@ec720000 { - compatible = "renesas,dmac-r8a7793", - "renesas,rcar-dmac"; - reg = <0 0xec720000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12"; - clocks = <&cpg CPG_MOD 501>; - clock-names = "fck"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 501>; - #dma-cells = <1>; - dma-channels = <13>; - }; - - sdhi0: sd@ee100000 { - compatible = "renesas,sdhi-r8a7793", - "renesas,rcar-gen2-sdhi"; - reg = <0 0xee100000 0 0x328>; - interrupts = ; - clocks = <&cpg CPG_MOD 314>; - dmas = <&dmac0 0xcd>, <&dmac0 0xce>, - <&dmac1 0xcd>, <&dmac1 0xce>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <195000000>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 314>; - status = "disabled"; - }; - - sdhi1: sd@ee140000 { - compatible = "renesas,sdhi-r8a7793", - "renesas,rcar-gen2-sdhi"; - reg = <0 0xee140000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 312>; - dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, - <&dmac1 0xc1>, <&dmac1 0xc2>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <97500000>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 312>; - status = "disabled"; - }; - - sdhi2: sd@ee160000 { - compatible = "renesas,sdhi-r8a7793", - "renesas,rcar-gen2-sdhi"; - reg = <0 0xee160000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 311>; - dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, - <&dmac1 0xd3>, <&dmac1 0xd4>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <97500000>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 311>; - status = "disabled"; - }; - - mmcif0: mmc@ee200000 { - compatible = "renesas,mmcif-r8a7793", - "renesas,sh-mmcif"; - reg = <0 0xee200000 0 0x80>; - interrupts = ; - clocks = <&cpg CPG_MOD 315>; - dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, - <&dmac1 0xd1>, <&dmac1 0xd2>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 315>; - reg-io-width = <4>; - status = "disabled"; - max-frequency = <97500000>; - }; - - ether: ethernet@ee700000 { - compatible = "renesas,ether-r8a7793", - "renesas,rcar-gen2-ether"; - reg = <0 0xee700000 0 0x400>; - interrupts = ; - clocks = <&cpg CPG_MOD 813>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 813>; - phy-mode = "rmii"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - gic: interrupt-controller@f1001000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0 0xf1001000 0 0x1000>, - <0 0xf1002000 0 0x2000>, - <0 0xf1004000 0 0x2000>, - <0 0xf1006000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 408>; - clock-names = "clk"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 408>; - }; - - fdp1@fe940000 { - compatible = "renesas,fdp1"; - reg = <0 0xfe940000 0 0x2400>; - interrupts = ; - clocks = <&cpg CPG_MOD 119>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 119>; - }; - - fdp1@fe944000 { - compatible = "renesas,fdp1"; - reg = <0 0xfe944000 0 0x2400>; - interrupts = ; - clocks = <&cpg CPG_MOD 118>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 118>; - }; - - du: display@feb00000 { - compatible = "renesas,du-r8a7793"; - reg = <0 0xfeb00000 0 0x40000>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>; - clock-names = "du.0", "du.1"; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - du_out_rgb: endpoint { - }; - }; - port@1 { - reg = <1>; - du_out_lvds0: endpoint { - remote-endpoint = <&lvds0_in>; - }; - }; - }; - }; - - lvds0: lvds@feb90000 { - compatible = "renesas,r8a7793-lvds"; - reg = <0 0xfeb90000 0 0x1c>; - clocks = <&cpg CPG_MOD 726>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 726>; - - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - lvds0_in: endpoint { - remote-endpoint = <&du_out_lvds0>; - }; - }; - port@1 { - reg = <1>; - lvds0_out: endpoint { - }; - }; - }; - }; - - prr: chipid@ff000044 { - compatible = "renesas,prr"; - reg = <0 0xff000044 0 4>; - }; - - cmt0: timer@ffca0000 { - compatible = "renesas,r8a7793-cmt0", - "renesas,rcar-gen2-cmt0"; - reg = <0 0xffca0000 0 0x1004>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 124>; - clock-names = "fck"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 124>; - - status = "disabled"; - }; - - cmt1: timer@e6130000 { - compatible = "renesas,r8a7793-cmt1", - "renesas,rcar-gen2-cmt1"; - reg = <0 0xe6130000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 329>; - clock-names = "fck"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 329>; - - status = "disabled"; - }; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - - thermal-sensors = <&thermal>; - - trips { - cpu-crit { - temperature = <95000>; - hysteresis = <0>; - type = "critical"; - }; - }; - cooling-maps { - }; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; - }; - - /* External USB clock - can be overridden by the board */ - usb_extal_clk: usb_extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <48000000>; - }; -}; diff --git a/sys/gnu/dts/arm/r8a7794-alt.dts b/sys/gnu/dts/arm/r8a7794-alt.dts deleted file mode 100644 index f79fce74cd9..00000000000 --- a/sys/gnu/dts/arm/r8a7794-alt.dts +++ /dev/null @@ -1,486 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the Alt board - * - * Copyright (C) 2014 Renesas Electronics Corporation - */ - -/dts-v1/; -#include "r8a7794.dtsi" -#include - -/ { - model = "Alt"; - compatible = "renesas,alt", "renesas,r8a7794"; - - aliases { - serial0 = &scif2; - i2c9 = &gpioi2c1; - i2c10 = &gpioi2c4; - i2c11 = &i2chdmi; - i2c12 = &i2cexio4; - }; - - chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; - stdout-path = "serial0:115200n8"; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0 0x40000000 0 0x40000000>; - }; - - d3_3v: regulator-d3-3v { - compatible = "regulator-fixed"; - regulator-name = "D3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - vcc_sdhi0: regulator-vcc-sdhi0 { - compatible = "regulator-fixed"; - - regulator-name = "SDHI0 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&gpio2 26 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vccq_sdhi0: regulator-vccq-sdhi0 { - compatible = "regulator-gpio"; - - regulator-name = "SDHI0 VccQ"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>; - gpios-states = <1>; - states = <3300000 1>, <1800000 0>; - }; - - vcc_sdhi1: regulator-vcc-sdhi1 { - compatible = "regulator-fixed"; - - regulator-name = "SDHI1 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&gpio4 26 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vccq_sdhi1: regulator-vccq-sdhi1 { - compatible = "regulator-gpio"; - - regulator-name = "SDHI1 VccQ"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>; - gpios-states = <1>; - states = <3300000 1>, <1800000 0>; - }; - - lbsc { - #address-cells = <1>; - #size-cells = <1>; - }; - - vga-encoder { - compatible = "adi,adv7123"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7123_in: endpoint { - remote-endpoint = <&du_out_rgb1>; - }; - }; - port@1 { - reg = <1>; - adv7123_out: endpoint { - remote-endpoint = <&vga_in>; - }; - }; - }; - }; - - vga { - compatible = "vga-connector"; - - port { - vga_in: endpoint { - remote-endpoint = <&adv7123_out>; - }; - }; - }; - - x2_clk: x2-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <74250000>; - }; - - x13_clk: x13-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <148500000>; - }; - - gpioi2c1: i2c-9 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "i2c-gpio"; - status = "disabled"; - scl-gpios = <&gpio4 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio4 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - }; - - gpioi2c4: i2c-10 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "i2c-gpio"; - status = "disabled"; - scl-gpios = <&gpio4 8 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio4 9 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <5>; - }; - - /* - * A fallback to GPIO is provided for I2C1. - */ - i2chdmi: i2c-11 { - compatible = "i2c-demux-pinctrl"; - i2c-parent = <&i2c1>, <&gpioi2c1>; - i2c-bus-name = "i2c-hdmi"; - #address-cells = <1>; - #size-cells = <0>; - - composite-in@20 { - compatible = "adi,adv7180"; - reg = <0x20>; - remote = <&vin0>; - - port { - adv7180: endpoint { - bus-width = <8>; - remote-endpoint = <&vin0ep>; - }; - }; - }; - - eeprom@50 { - compatible = "renesas,r1ex24002", "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; - }; - - /* - * I2C4 is routed to EXIO connector B, pins 73 (SCL) + 74 (SDA). - * A fallback to GPIO is provided. - */ - i2cexio4: i2c-14 { - compatible = "i2c-demux-pinctrl"; - i2c-parent = <&i2c4>, <&gpioi2c4>; - i2c-bus-name = "i2c-exio4"; - #address-cells = <1>; - #size-cells = <0>; - }; -}; - -&pci0 { - status = "okay"; - pinctrl-0 = <&usb0_pins>; - pinctrl-names = "default"; -}; - -&pci1 { - status = "okay"; - pinctrl-0 = <&usb1_pins>; - pinctrl-names = "default"; -}; - -&usbphy { - status = "okay"; -}; - -&du { - pinctrl-0 = <&du_pins>; - pinctrl-names = "default"; - status = "okay"; - - clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, - <&x13_clk>, <&x2_clk>; - clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1"; - - ports { - port@1 { - endpoint { - remote-endpoint = <&adv7123_in>; - }; - }; - }; -}; - -&extal_clk { - clock-frequency = <20000000>; -}; - -&pfc { - pinctrl-0 = <&scif_clk_pins>; - pinctrl-names = "default"; - - du_pins: du { - groups = "du1_rgb666", "du1_sync", "du1_disp", "du1_clk0_out"; - function = "du1"; - }; - - scif2_pins: scif2 { - groups = "scif2_data"; - function = "scif2"; - }; - - scif_clk_pins: scif_clk { - groups = "scif_clk"; - function = "scif_clk"; - }; - - ether_pins: ether { - groups = "eth_link", "eth_mdio", "eth_rmii"; - function = "eth"; - }; - - phy1_pins: phy1 { - groups = "intc_irq8"; - function = "intc"; - }; - - i2c1_pins: i2c1 { - groups = "i2c1"; - function = "i2c1"; - }; - - i2c4_pins: i2c4 { - groups = "i2c4"; - function = "i2c4"; - }; - - vin0_pins: vin0 { - groups = "vin0_data8", "vin0_clk"; - function = "vin0"; - }; - - mmcif0_pins: mmcif0 { - groups = "mmc_data8", "mmc_ctrl"; - function = "mmc"; - }; - - sdhi0_pins: sd0 { - groups = "sdhi0_data4", "sdhi0_ctrl"; - function = "sdhi0"; - power-source = <3300>; - }; - - sdhi0_pins_uhs: sd0_uhs { - groups = "sdhi0_data4", "sdhi0_ctrl"; - function = "sdhi0"; - power-source = <1800>; - }; - - sdhi1_pins: sd1 { - groups = "sdhi1_data4", "sdhi1_ctrl"; - function = "sdhi1"; - power-source = <3300>; - }; - - sdhi1_pins_uhs: sd1_uhs { - groups = "sdhi1_data4", "sdhi1_ctrl"; - function = "sdhi1"; - power-source = <1800>; - }; - - usb0_pins: usb0 { - groups = "usb0"; - function = "usb0"; - }; - - usb1_pins: usb1 { - groups = "usb1"; - function = "usb1"; - }; -}; - -&cmt0 { - status = "okay"; -}; - -&pfc { - qspi_pins: qspi { - groups = "qspi_ctrl", "qspi_data4"; - function = "qspi"; - }; -}; - -ðer { - pinctrl-0 = <ðer_pins &phy1_pins>; - pinctrl-names = "default"; - - phy-handle = <&phy1>; - renesas,ether-link-active-low; - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - interrupt-parent = <&irqc0>; - interrupts = <8 IRQ_TYPE_LEVEL_LOW>; - micrel,led-mode = <1>; - }; -}; - -&mmcif0 { - pinctrl-0 = <&mmcif0_pins>; - pinctrl-names = "default"; - - vmmc-supply = <&d3_3v>; - vqmmc-supply = <&d3_3v>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&rwdt { - timeout-sec = <60>; - status = "okay"; -}; - -&sdhi0 { - pinctrl-0 = <&sdhi0_pins>; - pinctrl-1 = <&sdhi0_pins_uhs>; - pinctrl-names = "default", "state_uhs"; - - vmmc-supply = <&vcc_sdhi0>; - vqmmc-supply = <&vccq_sdhi0>; - cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; - sd-uhs-sdr50; - sd-uhs-sdr104; - status = "okay"; -}; - -&sdhi1 { - pinctrl-0 = <&sdhi1_pins>; - pinctrl-1 = <&sdhi1_pins_uhs>; - pinctrl-names = "default", "state_uhs"; - - vmmc-supply = <&vcc_sdhi1>; - vqmmc-supply = <&vccq_sdhi1>; - cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>; - sd-uhs-sdr50; - status = "okay"; -}; - -&i2c1 { - pinctrl-0 = <&i2c1_pins>; - pinctrl-names = "i2c-hdmi"; - - clock-frequency = <400000>; -}; - -&i2c4 { - pinctrl-0 = <&i2c4_pins>; - pinctrl-names = "i2c-exio4"; -}; - -&i2c7 { - status = "okay"; - clock-frequency = <100000>; - - pmic@58 { - compatible = "dlg,da9063"; - reg = <0x58>; - interrupt-parent = <&gpio3>; - interrupts = <31 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - - rtc { - compatible = "dlg,da9063-rtc"; - }; - - wdt { - compatible = "dlg,da9063-watchdog"; - }; - }; -}; - -&vin0 { - status = "okay"; - pinctrl-0 = <&vin0_pins>; - pinctrl-names = "default"; - - port { - vin0ep: endpoint { - remote-endpoint = <&adv7180>; - bus-width = <8>; - }; - }; -}; - -&scif2 { - pinctrl-0 = <&scif2_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&scif_clk { - clock-frequency = <14745600>; -}; - -&qspi { - pinctrl-0 = <&qspi_pins>; - pinctrl-names = "default"; - - status = "okay"; - - flash@0 { - compatible = "spansion,s25fl512s", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <30000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - spi-cpol; - spi-cpha; - m25p,fast-read; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "loader"; - reg = <0x00000000 0x00040000>; - read-only; - }; - partition@40000 { - label = "system"; - reg = <0x00040000 0x00040000>; - read-only; - }; - partition@80000 { - label = "user"; - reg = <0x00080000 0x03f80000>; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/r8a7794-silk.dts b/sys/gnu/dts/arm/r8a7794-silk.dts deleted file mode 100644 index 2c16ad85430..00000000000 --- a/sys/gnu/dts/arm/r8a7794-silk.dts +++ /dev/null @@ -1,568 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the SILK board - * - * Copyright (C) 2014 Renesas Electronics Corporation - * Copyright (C) 2014-2015 Renesas Solutions Corp. - * Copyright (C) 2014-2015 Cogent Embedded, Inc. - */ - -/* - * SSI-AK4643 - * - * SW1: 2-1: AK4643 - * 2-3: ADV7511 - * - * This command is required before playback/capture: - * - * amixer set "LINEOUT Mixer DACL" on - */ - -/dts-v1/; -#include "r8a7794.dtsi" -#include -#include - -/ { - model = "SILK"; - compatible = "renesas,silk", "renesas,r8a7794"; - - aliases { - serial0 = &scif2; - i2c9 = &gpioi2c1; - i2c10 = &i2chdmi; - }; - - chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; - stdout-path = "serial0:115200n8"; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0 0x40000000 0 0x40000000>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - key-3 { - gpios = <&gpio5 10 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW3"; - wakeup-source; - debounce-interval = <20>; - }; - key-4 { - gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW4"; - wakeup-source; - debounce-interval = <20>; - }; - key-6 { - gpios = <&gpio5 12 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW6"; - wakeup-source; - debounce-interval = <20>; - }; - key-a { - gpios = <&gpio3 9 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW12-1"; - wakeup-source; - debounce-interval = <20>; - }; - key-b { - gpios = <&gpio3 10 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW12-2"; - wakeup-source; - debounce-interval = <20>; - }; - key-c { - gpios = <&gpio3 11 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW12-3"; - wakeup-source; - debounce-interval = <20>; - }; - key-d { - gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW12-4"; - wakeup-source; - debounce-interval = <20>; - }; - }; - - d3_3v: regulator-d3-3v { - compatible = "regulator-fixed"; - regulator-name = "D3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - vcc_sdhi1: regulator-vcc-sdhi1 { - compatible = "regulator-fixed"; - - regulator-name = "SDHI1 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&gpio4 26 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vccq_sdhi1: regulator-vccq-sdhi1 { - compatible = "regulator-gpio"; - - regulator-name = "SDHI1 VccQ"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>; - gpios-states = <1>; - states = <3300000 1>, <1800000 0>; - }; - - vga-encoder { - compatible = "adi,adv7123"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7123_in: endpoint { - remote-endpoint = <&du_out_rgb1>; - }; - }; - port@1 { - reg = <1>; - adv7123_out: endpoint { - remote-endpoint = <&vga_in>; - }; - }; - }; - }; - - hdmi-out { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con: endpoint { - remote-endpoint = <&adv7511_out>; - }; - }; - }; - - vga { - compatible = "vga-connector"; - - port { - vga_in: endpoint { - remote-endpoint = <&adv7123_out>; - }; - }; - }; - - x2_clk: x2-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <148500000>; - }; - - x3_clk: x3-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <74250000>; - }; - - x9_clk: audio_clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <12288000>; - }; - - sound { - compatible = "simple-audio-card"; - - simple-audio-card,format = "left_j"; - simple-audio-card,bitclock-master = <&soundcodec>; - simple-audio-card,frame-master = <&soundcodec>; - - simple-audio-card,cpu { - sound-dai = <&rcar_sound>; - }; - - soundcodec: simple-audio-card,codec { - sound-dai = <&ak4643>; - clocks = <&x9_clk>; - }; - }; - - gpioi2c1: i2c-9 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "i2c-gpio"; - status = "disabled"; - scl-gpios = <&gpio4 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio4 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <5>; - }; - - /* - * A fallback to GPIO is provided for I2C1. - */ - i2chdmi: i2c-10 { - compatible = "i2c-demux-pinctrl"; - i2c-parent = <&i2c1>, <&gpioi2c1>; - i2c-bus-name = "i2c-hdmi"; - #address-cells = <1>; - #size-cells = <0>; - - ak4643: codec@12 { - compatible = "asahi-kasei,ak4643"; - #sound-dai-cells = <0>; - reg = <0x12>; - }; - - composite-in@20 { - compatible = "adi,adv7180"; - reg = <0x20>; - remote = <&vin0>; - - port { - adv7180: endpoint { - bus-width = <8>; - remote-endpoint = <&vin0ep>; - }; - }; - }; - - hdmi@39 { - compatible = "adi,adv7511w"; - reg = <0x39>; - interrupt-parent = <&gpio5>; - interrupts = <23 IRQ_TYPE_LEVEL_LOW>; - - adi,input-depth = <8>; - adi,input-colorspace = "rgb"; - adi,input-clock = "1x"; - adi,input-style = <1>; - adi,input-justification = "evenly"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7511_in: endpoint { - remote-endpoint = <&du_out_rgb0>; - }; - }; - - port@1 { - reg = <1>; - adv7511_out: endpoint { - remote-endpoint = <&hdmi_con>; - }; - }; - }; - }; - - eeprom@50 { - compatible = "renesas,r1ex24002", "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; - }; -}; - -&extal_clk { - clock-frequency = <20000000>; -}; - -&pfc { - pinctrl-0 = <&scif_clk_pins>; - pinctrl-names = "default"; - - scif2_pins: scif2 { - groups = "scif2_data"; - function = "scif2"; - }; - - scif_clk_pins: scif_clk { - groups = "scif_clk"; - function = "scif_clk"; - }; - - ether_pins: ether { - groups = "eth_link", "eth_mdio", "eth_rmii"; - function = "eth"; - }; - - phy1_pins: phy1 { - groups = "intc_irq8"; - function = "intc"; - }; - - i2c1_pins: i2c1 { - groups = "i2c1"; - function = "i2c1"; - }; - - mmcif0_pins: mmcif0 { - groups = "mmc_data8", "mmc_ctrl"; - function = "mmc"; - }; - - sdhi1_pins: sd1 { - groups = "sdhi1_data4", "sdhi1_ctrl"; - function = "sdhi1"; - }; - - qspi_pins: qspi { - groups = "qspi_ctrl", "qspi_data4"; - function = "qspi"; - }; - - vin0_pins: vin0 { - groups = "vin0_data8", "vin0_clk"; - function = "vin0"; - }; - - usb0_pins: usb0 { - groups = "usb0"; - function = "usb0"; - }; - - usb1_pins: usb1 { - groups = "usb1"; - function = "usb1"; - }; - - du0_pins: du0 { - groups = "du0_rgb888", "du0_sync", "du0_disp", "du0_clk0_out"; - function = "du0"; - }; - - du1_pins: du1 { - groups = "du1_rgb666", "du1_sync", "du1_disp", "du1_clk0_out"; - function = "du1"; - }; - - ssi_pins: sound { - groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data"; - function = "ssi"; - }; - - audio_clk_pins: audio_clk { - groups = "audio_clkc"; - function = "audio_clk"; - }; -}; - -&scif2 { - pinctrl-0 = <&scif2_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&scif_clk { - clock-frequency = <14745600>; -}; - -ðer { - pinctrl-0 = <ðer_pins &phy1_pins>; - pinctrl-names = "default"; - - phy-handle = <&phy1>; - renesas,ether-link-active-low; - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - interrupt-parent = <&irqc0>; - interrupts = <8 IRQ_TYPE_LEVEL_LOW>; - micrel,led-mode = <1>; - }; -}; - -&i2c1 { - pinctrl-0 = <&i2c1_pins>; - pinctrl-names = "i2c-hdmi"; - - clock-frequency = <400000>; -}; - -&i2c7 { - status = "okay"; - clock-frequency = <100000>; - - pmic@58 { - compatible = "dlg,da9063"; - reg = <0x58>; - interrupt-parent = <&gpio3>; - interrupts = <31 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - - onkey { - compatible = "dlg,da9063-onkey"; - }; - - rtc { - compatible = "dlg,da9063-rtc"; - }; - - wdt { - compatible = "dlg,da9063-watchdog"; - }; - }; -}; - -&mmcif0 { - pinctrl-0 = <&mmcif0_pins>; - pinctrl-names = "default"; - - vmmc-supply = <&d3_3v>; - vqmmc-supply = <&d3_3v>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&sdhi1 { - pinctrl-0 = <&sdhi1_pins>; - pinctrl-names = "default"; - - vmmc-supply = <&vcc_sdhi1>; - vqmmc-supply = <&vccq_sdhi1>; - cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&qspi { - pinctrl-0 = <&qspi_pins>; - pinctrl-names = "default"; - - status = "okay"; - - flash@0 { - compatible = "spansion,s25fl512s", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <30000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - spi-cpol; - spi-cpha; - m25p,fast-read; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "loader"; - reg = <0x00000000 0x00040000>; - read-only; - }; - partition@40000 { - label = "user"; - reg = <0x00040000 0x00400000>; - read-only; - }; - partition@440000 { - label = "flash"; - reg = <0x00440000 0x03bc0000>; - }; - }; - }; -}; - -/* composite video input */ -&vin0 { - status = "okay"; - pinctrl-0 = <&vin0_pins>; - pinctrl-names = "default"; - - port { - vin0ep: endpoint { - remote-endpoint = <&adv7180>; - bus-width = <8>; - }; - }; -}; - -&pci0 { - status = "okay"; - pinctrl-0 = <&usb0_pins>; - pinctrl-names = "default"; -}; - -&pci1 { - status = "okay"; - pinctrl-0 = <&usb1_pins>; - pinctrl-names = "default"; -}; - -&usbphy { - status = "okay"; -}; - -&du { - pinctrl-0 = <&du0_pins &du1_pins>; - pinctrl-names = "default"; - status = "okay"; - - clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, - <&x2_clk>, <&x3_clk>; - clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1"; - - ports { - port@0 { - endpoint { - remote-endpoint = <&adv7511_in>; - }; - }; - port@1 { - endpoint { - remote-endpoint = <&adv7123_in>; - }; - }; - }; -}; - -&rcar_sound { - pinctrl-0 = <&ssi_pins &audio_clk_pins>; - pinctrl-names = "default"; - status = "okay"; - - /* Single DAI */ - #sound-dai-cells = <0>; - - rcar_sound,dai { - dai0 { - playback = <&ssi0>; - capture = <&ssi1>; - }; - }; -}; - -&rwdt { - timeout-sec = <60>; - status = "okay"; -}; - -&ssi1 { - shared-pin; -}; diff --git a/sys/gnu/dts/arm/r8a7794.dtsi b/sys/gnu/dts/arm/r8a7794.dtsi deleted file mode 100644 index 05ef79c6ed7..00000000000 --- a/sys/gnu/dts/arm/r8a7794.dtsi +++ /dev/null @@ -1,1432 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the R-Car E2 (R8A77940) SoC - * - * Copyright (C) 2014 Renesas Electronics Corporation - * Copyright (C) 2014 Ulrich Hecht - */ - -#include -#include -#include -#include - -/ { - compatible = "renesas,r8a7794"; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - i2c6 = &i2c6; - i2c7 = &i2c7; - spi0 = &qspi; - vin0 = &vin0; - vin1 = &vin1; - }; - - /* - * The external audio clocks are configured as 0 Hz fixed frequency - * clocks by default. - * Boards that provide audio clocks should override them. - */ - audio_clka: audio_clka { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - audio_clkb: audio_clkb { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - audio_clkc: audio_clkc { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - /* External CAN clock */ - can_clk: can { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "renesas,apmu"; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0>; - clock-frequency = <1000000000>; - clocks = <&cpg CPG_CORE R8A7794_CLK_Z2>; - power-domains = <&sysc R8A7794_PD_CA7_CPU0>; - next-level-cache = <&L2_CA7>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <1>; - clock-frequency = <1000000000>; - clocks = <&cpg CPG_CORE R8A7794_CLK_Z2>; - power-domains = <&sysc R8A7794_PD_CA7_CPU1>; - next-level-cache = <&L2_CA7>; - }; - - L2_CA7: cache-controller-0 { - compatible = "cache"; - power-domains = <&sysc R8A7794_PD_CA7_SCU>; - cache-unified; - cache-level = <2>; - }; - }; - - /* External root clock */ - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts-extended = <&gic GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&cpu0>, <&cpu1>; - }; - - /* External SCIF clock */ - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - soc { - compatible = "simple-bus"; - interrupt-parent = <&gic>; - - #address-cells = <2>; - #size-cells = <2>; - ranges; - - rwdt: watchdog@e6020000 { - compatible = "renesas,r8a7794-wdt", - "renesas,rcar-gen2-wdt"; - reg = <0 0xe6020000 0 0x0c>; - clocks = <&cpg CPG_MOD 402>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 402>; - status = "disabled"; - }; - - gpio0: gpio@e6050000 { - compatible = "renesas,gpio-r8a7794", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6050000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 0 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 912>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 912>; - }; - - gpio1: gpio@e6051000 { - compatible = "renesas,gpio-r8a7794", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6051000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 32 26>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 911>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 911>; - }; - - gpio2: gpio@e6052000 { - compatible = "renesas,gpio-r8a7794", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6052000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 64 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 910>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 910>; - }; - - gpio3: gpio@e6053000 { - compatible = "renesas,gpio-r8a7794", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6053000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 96 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 909>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 909>; - }; - - gpio4: gpio@e6054000 { - compatible = "renesas,gpio-r8a7794", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6054000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 128 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 908>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 908>; - }; - - gpio5: gpio@e6055000 { - compatible = "renesas,gpio-r8a7794", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6055000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 160 28>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 907>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 907>; - }; - - gpio6: gpio@e6055400 { - compatible = "renesas,gpio-r8a7794", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6055400 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 192 26>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 905>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 905>; - }; - - pfc: pin-controller@e6060000 { - compatible = "renesas,pfc-r8a7794"; - reg = <0 0xe6060000 0 0x11c>; - }; - - cpg: clock-controller@e6150000 { - compatible = "renesas,r8a7794-cpg-mssr"; - reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk>, <&usb_extal_clk>; - clock-names = "extal", "usb_extal"; - #clock-cells = <2>; - #power-domain-cells = <0>; - #reset-cells = <1>; - }; - - apmu@e6151000 { - compatible = "renesas,r8a7794-apmu", "renesas,apmu"; - reg = <0 0xe6151000 0 0x188>; - cpus = <&cpu0 &cpu1>; - }; - - rst: reset-controller@e6160000 { - compatible = "renesas,r8a7794-rst"; - reg = <0 0xe6160000 0 0x0100>; - }; - - sysc: system-controller@e6180000 { - compatible = "renesas,r8a7794-sysc"; - reg = <0 0xe6180000 0 0x0200>; - #power-domain-cells = <1>; - }; - - irqc0: interrupt-controller@e61c0000 { - compatible = "renesas,irqc-r8a7794", "renesas,irqc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0 0xe61c0000 0 0x200>; - interrupts = , - , - , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 407>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 407>; - }; - - ipmmu_sy0: mmu@e6280000 { - compatible = "renesas,ipmmu-r8a7794", - "renesas,ipmmu-vmsa"; - reg = <0 0xe6280000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_sy1: mmu@e6290000 { - compatible = "renesas,ipmmu-r8a7794", - "renesas,ipmmu-vmsa"; - reg = <0 0xe6290000 0 0x1000>; - interrupts = ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_ds: mmu@e6740000 { - compatible = "renesas,ipmmu-r8a7794", - "renesas,ipmmu-vmsa"; - reg = <0 0xe6740000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_mp: mmu@ec680000 { - compatible = "renesas,ipmmu-r8a7794", - "renesas,ipmmu-vmsa"; - reg = <0 0xec680000 0 0x1000>; - interrupts = ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_mx: mmu@fe951000 { - compatible = "renesas,ipmmu-r8a7794", - "renesas,ipmmu-vmsa"; - reg = <0 0xfe951000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_gp: mmu@e62a0000 { - compatible = "renesas,ipmmu-r8a7794", - "renesas,ipmmu-vmsa"; - reg = <0 0xe62a0000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; - - icram0: sram@e63a0000 { - compatible = "mmio-sram"; - reg = <0 0xe63a0000 0 0x12000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0xe63a0000 0x12000>; - }; - - icram1: sram@e63c0000 { - compatible = "mmio-sram"; - reg = <0 0xe63c0000 0 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0xe63c0000 0x1000>; - - smp-sram@0 { - compatible = "renesas,smp-sram"; - reg = <0 0x100>; - }; - }; - - /* The memory map in the User's Manual maps the cores to - * bus numbers - */ - i2c0: i2c@e6508000 { - compatible = "renesas,i2c-r8a7794", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6508000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 931>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 931>; - #address-cells = <1>; - #size-cells = <0>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c1: i2c@e6518000 { - compatible = "renesas,i2c-r8a7794", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6518000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 930>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 930>; - #address-cells = <1>; - #size-cells = <0>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c2: i2c@e6530000 { - compatible = "renesas,i2c-r8a7794", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6530000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 929>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 929>; - #address-cells = <1>; - #size-cells = <0>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c3: i2c@e6540000 { - compatible = "renesas,i2c-r8a7794", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6540000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 928>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 928>; - #address-cells = <1>; - #size-cells = <0>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c4: i2c@e6520000 { - compatible = "renesas,i2c-r8a7794", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6520000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 927>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 927>; - #address-cells = <1>; - #size-cells = <0>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c5: i2c@e6528000 { - compatible = "renesas,i2c-r8a7794", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6528000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 925>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 925>; - #address-cells = <1>; - #size-cells = <0>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c6: i2c@e6500000 { - compatible = "renesas,iic-r8a7794", - "renesas,rcar-gen2-iic", - "renesas,rmobile-iic"; - reg = <0 0xe6500000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 318>; - dmas = <&dmac0 0x61>, <&dmac0 0x62>, - <&dmac1 0x61>, <&dmac1 0x62>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 318>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c7: i2c@e6510000 { - compatible = "renesas,iic-r8a7794", - "renesas,rcar-gen2-iic", - "renesas,rmobile-iic"; - reg = <0 0xe6510000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 323>; - dmas = <&dmac0 0x65>, <&dmac0 0x66>, - <&dmac1 0x65>, <&dmac1 0x66>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 323>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - hsusb: usb@e6590000 { - compatible = "renesas,usbhs-r8a7794", - "renesas,rcar-gen2-usbhs"; - reg = <0 0xe6590000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 704>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 704>; - renesas,buswait = <4>; - phys = <&usb0 1>; - phy-names = "usb"; - status = "disabled"; - }; - - usbphy: usb-phy@e6590100 { - compatible = "renesas,usb-phy-r8a7794", - "renesas,rcar-gen2-usb-phy"; - reg = <0 0xe6590100 0 0x100>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cpg CPG_MOD 704>; - clock-names = "usbhs"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 704>; - status = "disabled"; - - usb0: usb-channel@0 { - reg = <0>; - #phy-cells = <1>; - }; - usb2: usb-channel@2 { - reg = <2>; - #phy-cells = <1>; - }; - }; - - dmac0: dma-controller@e6700000 { - compatible = "renesas,dmac-r8a7794", - "renesas,rcar-dmac"; - reg = <0 0xe6700000 0 0x20000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14"; - clocks = <&cpg CPG_MOD 219>; - clock-names = "fck"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 219>; - #dma-cells = <1>; - dma-channels = <15>; - }; - - dmac1: dma-controller@e6720000 { - compatible = "renesas,dmac-r8a7794", - "renesas,rcar-dmac"; - reg = <0 0xe6720000 0 0x20000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14"; - clocks = <&cpg CPG_MOD 218>; - clock-names = "fck"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 218>; - #dma-cells = <1>; - dma-channels = <15>; - }; - - avb: ethernet@e6800000 { - compatible = "renesas,etheravb-r8a7794", - "renesas,etheravb-rcar-gen2"; - reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; - interrupts = ; - clocks = <&cpg CPG_MOD 812>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 812>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - qspi: spi@e6b10000 { - compatible = "renesas,qspi-r8a7794", "renesas,qspi"; - reg = <0 0xe6b10000 0 0x2c>; - interrupts = ; - clocks = <&cpg CPG_MOD 917>; - dmas = <&dmac0 0x17>, <&dmac0 0x18>, - <&dmac1 0x17>, <&dmac1 0x18>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 917>; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - scifa0: serial@e6c40000 { - compatible = "renesas,scifa-r8a7794", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c40000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 204>; - clock-names = "fck"; - dmas = <&dmac0 0x21>, <&dmac0 0x22>, - <&dmac1 0x21>, <&dmac1 0x22>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 204>; - status = "disabled"; - }; - - scifa1: serial@e6c50000 { - compatible = "renesas,scifa-r8a7794", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c50000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 203>; - clock-names = "fck"; - dmas = <&dmac0 0x25>, <&dmac0 0x26>, - <&dmac1 0x25>, <&dmac1 0x26>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 203>; - status = "disabled"; - }; - - scifa2: serial@e6c60000 { - compatible = "renesas,scifa-r8a7794", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c60000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 202>; - clock-names = "fck"; - dmas = <&dmac0 0x27>, <&dmac0 0x28>, - <&dmac1 0x27>, <&dmac1 0x28>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 202>; - status = "disabled"; - }; - - scifa3: serial@e6c70000 { - compatible = "renesas,scifa-r8a7794", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c70000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 1106>; - clock-names = "fck"; - dmas = <&dmac0 0x1b>, <&dmac0 0x1c>, - <&dmac1 0x1b>, <&dmac1 0x1c>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 1106>; - status = "disabled"; - }; - - scifa4: serial@e6c78000 { - compatible = "renesas,scifa-r8a7794", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c78000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 1107>; - clock-names = "fck"; - dmas = <&dmac0 0x1f>, <&dmac0 0x20>, - <&dmac1 0x1f>, <&dmac1 0x20>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 1107>; - status = "disabled"; - }; - - scifa5: serial@e6c80000 { - compatible = "renesas,scifa-r8a7794", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c80000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 1108>; - clock-names = "fck"; - dmas = <&dmac0 0x23>, <&dmac0 0x24>, - <&dmac1 0x23>, <&dmac1 0x24>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 1108>; - status = "disabled"; - }; - - scifb0: serial@e6c20000 { - compatible = "renesas,scifb-r8a7794", - "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6c20000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 206>; - clock-names = "fck"; - dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, - <&dmac1 0x3d>, <&dmac1 0x3e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 206>; - status = "disabled"; - }; - - scifb1: serial@e6c30000 { - compatible = "renesas,scifb-r8a7794", - "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6c30000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 207>; - clock-names = "fck"; - dmas = <&dmac0 0x19>, <&dmac0 0x1a>, - <&dmac1 0x19>, <&dmac1 0x1a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 207>; - status = "disabled"; - }; - - scifb2: serial@e6ce0000 { - compatible = "renesas,scifb-r8a7794", - "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6ce0000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 216>; - clock-names = "fck"; - dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, - <&dmac1 0x1d>, <&dmac1 0x1e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 216>; - status = "disabled"; - }; - - scif0: serial@e6e60000 { - compatible = "renesas,scif-r8a7794", - "renesas,rcar-gen2-scif", - "renesas,scif"; - reg = <0 0xe6e60000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7794_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x29>, <&dmac0 0x2a>, - <&dmac1 0x29>, <&dmac1 0x2a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 721>; - status = "disabled"; - }; - - scif1: serial@e6e68000 { - compatible = "renesas,scif-r8a7794", - "renesas,rcar-gen2-scif", - "renesas,scif"; - reg = <0 0xe6e68000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 720>, <&cpg CPG_CORE R8A7794_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, - <&dmac1 0x2d>, <&dmac1 0x2e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 720>; - status = "disabled"; - }; - - scif2: serial@e6e58000 { - compatible = "renesas,scif-r8a7794", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6e58000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 719>, <&cpg CPG_CORE R8A7794_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, - <&dmac1 0x2b>, <&dmac1 0x2c>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 719>; - status = "disabled"; - }; - - scif3: serial@e6ea8000 { - compatible = "renesas,scif-r8a7794", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6ea8000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 718>, <&cpg CPG_CORE R8A7794_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2f>, <&dmac0 0x30>, - <&dmac1 0x2f>, <&dmac1 0x30>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 718>; - status = "disabled"; - }; - - scif4: serial@e6ee0000 { - compatible = "renesas,scif-r8a7794", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6ee0000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 715>, <&cpg CPG_CORE R8A7794_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0xfb>, <&dmac0 0xfc>, - <&dmac1 0xfb>, <&dmac1 0xfc>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 715>; - status = "disabled"; - }; - - scif5: serial@e6ee8000 { - compatible = "renesas,scif-r8a7794", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6ee8000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 714>, <&cpg CPG_CORE R8A7794_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0xfd>, <&dmac0 0xfe>, - <&dmac1 0xfd>, <&dmac1 0xfe>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 714>; - status = "disabled"; - }; - - hscif0: serial@e62c0000 { - compatible = "renesas,hscif-r8a7794", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62c0000 0 96>; - interrupts = ; - clocks = <&cpg CPG_MOD 717>, - <&cpg CPG_CORE R8A7794_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x39>, <&dmac0 0x3a>, - <&dmac1 0x39>, <&dmac1 0x3a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 717>; - status = "disabled"; - }; - - hscif1: serial@e62c8000 { - compatible = "renesas,hscif-r8a7794", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62c8000 0 96>; - interrupts = ; - clocks = <&cpg CPG_MOD 716>, - <&cpg CPG_CORE R8A7794_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, - <&dmac1 0x4d>, <&dmac1 0x4e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 716>; - status = "disabled"; - }; - - hscif2: serial@e62d0000 { - compatible = "renesas,hscif-r8a7794", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62d0000 0 96>; - interrupts = ; - clocks = <&cpg CPG_MOD 713>, <&cpg CPG_CORE R8A7794_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x3b>, <&dmac0 0x3c>, - <&dmac1 0x3b>, <&dmac1 0x3c>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 713>; - status = "disabled"; - }; - - can0: can@e6e80000 { - compatible = "renesas,can-r8a7794", - "renesas,rcar-gen2-can"; - reg = <0 0xe6e80000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 916>, <&cpg CPG_CORE R8A7794_CLK_RCAN>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 916>; - status = "disabled"; - }; - - can1: can@e6e88000 { - compatible = "renesas,can-r8a7794", - "renesas,rcar-gen2-can"; - reg = <0 0xe6e88000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 915>, <&cpg CPG_CORE R8A7794_CLK_RCAN>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 915>; - status = "disabled"; - }; - - vin0: video@e6ef0000 { - compatible = "renesas,vin-r8a7794", - "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef0000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 811>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 811>; - status = "disabled"; - }; - - vin1: video@e6ef1000 { - compatible = "renesas,vin-r8a7794", - "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef1000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 810>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 810>; - status = "disabled"; - }; - - rcar_sound: sound@ec500000 { - /* - * #sound-dai-cells is required - * - * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; - * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; - */ - compatible = "renesas,rcar_sound-r8a7794", - "renesas,rcar_sound-gen2"; - reg = <0 0xec500000 0 0x1000>, /* SCU */ - <0 0xec5a0000 0 0x100>, /* ADG */ - <0 0xec540000 0 0x1000>, /* SSIU */ - <0 0xec541000 0 0x280>, /* SSI */ - <0 0xec740000 0 0x200>; /* Audio DMAC peri peri */ - reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; - - clocks = <&cpg CPG_MOD 1005>, - <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, - <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, - <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, - <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, - <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, - <&cpg CPG_MOD 1025>, <&cpg CPG_MOD 1026>, - <&cpg CPG_MOD 1027>, <&cpg CPG_MOD 1028>, - <&cpg CPG_MOD 1029>, <&cpg CPG_MOD 1030>, - <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, - <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, - <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, - <&audio_clka>, <&audio_clkb>, <&audio_clkc>, - <&cpg CPG_CORE R8A7794_CLK_M2>; - clock-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", - "ssi.5", "ssi.4", "ssi.3", "ssi.2", - "ssi.1", "ssi.0", - "src.6", "src.5", "src.4", "src.3", - "src.2", "src.1", - "ctu.0", "ctu.1", - "mix.0", "mix.1", - "dvc.0", "dvc.1", - "clk_a", "clk_b", "clk_c", "clk_i"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 1005>, - <&cpg 1006>, <&cpg 1007>, - <&cpg 1008>, <&cpg 1009>, - <&cpg 1010>, <&cpg 1011>, - <&cpg 1012>, <&cpg 1013>, - <&cpg 1014>, <&cpg 1015>; - reset-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", - "ssi.5", "ssi.4", "ssi.3", "ssi.2", - "ssi.1", "ssi.0"; - - status = "disabled"; - - rcar_sound,dvc { - dvc0: dvc-0 { - dmas = <&audma0 0xbc>; - dma-names = "tx"; - }; - dvc1: dvc-1 { - dmas = <&audma0 0xbe>; - dma-names = "tx"; - }; - }; - - rcar_sound,mix { - mix0: mix-0 { }; - mix1: mix-1 { }; - }; - - rcar_sound,ctu { - ctu00: ctu-0 { }; - ctu01: ctu-1 { }; - ctu02: ctu-2 { }; - ctu03: ctu-3 { }; - ctu10: ctu-4 { }; - ctu11: ctu-5 { }; - ctu12: ctu-6 { }; - ctu13: ctu-7 { }; - }; - - rcar_sound,src { - src-0 { - status = "disabled"; - }; - src1: src-1 { - interrupts = ; - dmas = <&audma0 0x87>, <&audma0 0x9c>; - dma-names = "rx", "tx"; - }; - src2: src-2 { - interrupts = ; - dmas = <&audma0 0x89>, <&audma0 0x9e>; - dma-names = "rx", "tx"; - }; - src3: src-3 { - interrupts = ; - dmas = <&audma0 0x8b>, <&audma0 0xa0>; - dma-names = "rx", "tx"; - }; - src4: src-4 { - interrupts = ; - dmas = <&audma0 0x8d>, <&audma0 0xb0>; - dma-names = "rx", "tx"; - }; - src5: src-5 { - interrupts = ; - dmas = <&audma0 0x8f>, <&audma0 0xb2>; - dma-names = "rx", "tx"; - }; - src6: src-6 { - interrupts = ; - dmas = <&audma0 0x91>, <&audma0 0xb4>; - dma-names = "rx", "tx"; - }; - }; - - rcar_sound,ssi { - ssi0: ssi-0 { - interrupts = ; - dmas = <&audma0 0x01>, <&audma0 0x02>, - <&audma0 0x15>, <&audma0 0x16>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi1: ssi-1 { - interrupts = ; - dmas = <&audma0 0x03>, <&audma0 0x04>, - <&audma0 0x49>, <&audma0 0x4a>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi2: ssi-2 { - interrupts = ; - dmas = <&audma0 0x05>, <&audma0 0x06>, - <&audma0 0x63>, <&audma0 0x64>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi3: ssi-3 { - interrupts = ; - dmas = <&audma0 0x07>, <&audma0 0x08>, - <&audma0 0x6f>, <&audma0 0x70>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi4: ssi-4 { - interrupts = ; - dmas = <&audma0 0x09>, <&audma0 0x0a>, - <&audma0 0x71>, <&audma0 0x72>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi5: ssi-5 { - interrupts = ; - dmas = <&audma0 0x0b>, <&audma0 0x0c>, - <&audma0 0x73>, <&audma0 0x74>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi6: ssi-6 { - interrupts = ; - dmas = <&audma0 0x0d>, <&audma0 0x0e>, - <&audma0 0x75>, <&audma0 0x76>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi7: ssi-7 { - interrupts = ; - dmas = <&audma0 0x0f>, <&audma0 0x10>, - <&audma0 0x79>, <&audma0 0x7a>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi8: ssi-8 { - interrupts = ; - dmas = <&audma0 0x11>, <&audma0 0x12>, - <&audma0 0x7b>, <&audma0 0x7c>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi9: ssi-9 { - interrupts = ; - dmas = <&audma0 0x13>, <&audma0 0x14>, - <&audma0 0x7d>, <&audma0 0x7e>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - }; - }; - - audma0: dma-controller@ec700000 { - compatible = "renesas,dmac-r8a7794", - "renesas,rcar-dmac"; - reg = <0 0xec700000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", "ch4", - "ch5", "ch6", "ch7", "ch8", "ch9", - "ch10", "ch11", - "ch12"; - clocks = <&cpg CPG_MOD 502>; - clock-names = "fck"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 502>; - #dma-cells = <1>; - dma-channels = <13>; - }; - - pci0: pci@ee090000 { - compatible = "renesas,pci-r8a7794", - "renesas,pci-rcar-gen2"; - device_type = "pci"; - reg = <0 0xee090000 0 0xc00>, - <0 0xee080000 0 0x1100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 703>; - status = "disabled"; - - bus-range = <0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>; - interrupt-map-mask = <0xf800 0 0 0x7>; - interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, - <0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, - <0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; - - usb@1,0 { - reg = <0x800 0 0 0 0>; - phys = <&usb0 0>; - phy-names = "usb"; - }; - - usb@2,0 { - reg = <0x1000 0 0 0 0>; - phys = <&usb0 0>; - phy-names = "usb"; - }; - }; - - pci1: pci@ee0d0000 { - compatible = "renesas,pci-r8a7794", - "renesas,pci-rcar-gen2"; - device_type = "pci"; - reg = <0 0xee0d0000 0 0xc00>, - <0 0xee0c0000 0 0x1100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 703>; - status = "disabled"; - - bus-range = <1 1>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>; - interrupt-map-mask = <0xf800 0 0 0x7>; - interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, - <0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, - <0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; - - usb@1,0 { - reg = <0x10800 0 0 0 0>; - phys = <&usb2 0>; - phy-names = "usb"; - }; - - usb@2,0 { - reg = <0x11000 0 0 0 0>; - phys = <&usb2 0>; - phy-names = "usb"; - }; - }; - - sdhi0: sd@ee100000 { - compatible = "renesas,sdhi-r8a7794", - "renesas,rcar-gen2-sdhi"; - reg = <0 0xee100000 0 0x328>; - interrupts = ; - clocks = <&cpg CPG_MOD 314>; - dmas = <&dmac0 0xcd>, <&dmac0 0xce>, - <&dmac1 0xcd>, <&dmac1 0xce>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <195000000>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 314>; - status = "disabled"; - }; - - sdhi1: sd@ee140000 { - compatible = "renesas,sdhi-r8a7794", - "renesas,rcar-gen2-sdhi"; - reg = <0 0xee140000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 312>; - dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, - <&dmac1 0xc1>, <&dmac1 0xc2>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <97500000>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 312>; - status = "disabled"; - }; - - sdhi2: sd@ee160000 { - compatible = "renesas,sdhi-r8a7794", - "renesas,rcar-gen2-sdhi"; - reg = <0 0xee160000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 311>; - dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, - <&dmac1 0xd3>, <&dmac1 0xd4>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <97500000>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 311>; - status = "disabled"; - }; - - mmcif0: mmc@ee200000 { - compatible = "renesas,mmcif-r8a7794", - "renesas,sh-mmcif"; - reg = <0 0xee200000 0 0x80>; - interrupts = ; - clocks = <&cpg CPG_MOD 315>; - dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, - <&dmac1 0xd1>, <&dmac1 0xd2>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 315>; - reg-io-width = <4>; - status = "disabled"; - }; - - ether: ethernet@ee700000 { - compatible = "renesas,ether-r8a7794", - "renesas,rcar-gen2-ether"; - reg = <0 0xee700000 0 0x400>; - interrupts = ; - clocks = <&cpg CPG_MOD 813>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 813>; - phy-mode = "rmii"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - gic: interrupt-controller@f1001000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0 0xf1001000 0 0x1000>, - <0 0xf1002000 0 0x2000>, - <0 0xf1004000 0 0x2000>, - <0 0xf1006000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 408>; - clock-names = "clk"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 408>; - }; - - vsp@fe928000 { - compatible = "renesas,vsp1"; - reg = <0 0xfe928000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 131>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 131>; - }; - - vsp@fe930000 { - compatible = "renesas,vsp1"; - reg = <0 0xfe930000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 128>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 128>; - }; - - fdp1@fe940000 { - compatible = "renesas,fdp1"; - reg = <0 0xfe940000 0 0x2400>; - interrupts = ; - clocks = <&cpg CPG_MOD 119>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 119>; - }; - - du: display@feb00000 { - compatible = "renesas,du-r8a7794"; - reg = <0 0xfeb00000 0 0x40000>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; - clock-names = "du.0", "du.1"; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - du_out_rgb0: endpoint { - }; - }; - port@1 { - reg = <1>; - du_out_rgb1: endpoint { - }; - }; - }; - }; - - prr: chipid@ff000044 { - compatible = "renesas,prr"; - reg = <0 0xff000044 0 4>; - }; - - cmt0: timer@ffca0000 { - compatible = "renesas,r8a7794-cmt0", - "renesas,rcar-gen2-cmt0"; - reg = <0 0xffca0000 0 0x1004>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 124>; - clock-names = "fck"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 124>; - - status = "disabled"; - }; - - cmt1: timer@e6130000 { - compatible = "renesas,r8a7794-cmt1", - "renesas,rcar-gen2-cmt1"; - reg = <0 0xe6130000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 329>; - clock-names = "fck"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 329>; - - status = "disabled"; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; - }; - - /* External USB clock - can be overridden by the board */ - usb_extal_clk: usb_extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <48000000>; - }; -}; diff --git a/sys/gnu/dts/arm/r8a77xx-aa104xd12-panel.dtsi b/sys/gnu/dts/arm/r8a77xx-aa104xd12-panel.dtsi deleted file mode 100644 index 79fce67ebb1..00000000000 --- a/sys/gnu/dts/arm/r8a77xx-aa104xd12-panel.dtsi +++ /dev/null @@ -1,39 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Common file for the AA104XD12 panel connected to Renesas R-Car boards - * - * Copyright (C) 2014 Renesas Electronics Corp. - */ - -/ { - panel { - compatible = "mitsubishi,aa104xd12", "panel-lvds"; - - width-mm = <210>; - height-mm = <158>; - data-mapping = "jeida-18"; - - panel-timing { - /* 1024x768 @65Hz */ - clock-frequency = <65000000>; - hactive = <1024>; - vactive = <768>; - hsync-len = <136>; - hfront-porch = <20>; - hback-porch = <160>; - vfront-porch = <3>; - vback-porch = <29>; - vsync-len = <6>; - }; - - port { - panel_in: endpoint { - remote-endpoint = <&lvds_connector>; - }; - }; - }; -}; - -&lvds_connector { - remote-endpoint = <&panel_in>; -}; diff --git a/sys/gnu/dts/arm/r8a77xx-aa121td01-panel.dtsi b/sys/gnu/dts/arm/r8a77xx-aa121td01-panel.dtsi deleted file mode 100644 index 6e7589ea756..00000000000 --- a/sys/gnu/dts/arm/r8a77xx-aa121td01-panel.dtsi +++ /dev/null @@ -1,39 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Common file for the AA121TD01 panel connected to Renesas R-Car boards - * - * Copyright (C) 2015 Renesas Electronics Corp. - */ - -/ { - panel { - compatible = "mitsubishi,aa121td01", "panel-lvds"; - - width-mm = <261>; - height-mm = <163>; - data-mapping = "jeida-18"; - - panel-timing { - /* 1280x800 @60Hz */ - clock-frequency = <71000000>; - hactive = <1280>; - vactive = <800>; - hsync-len = <70>; - hfront-porch = <20>; - hback-porch = <70>; - vsync-len = <5>; - vfront-porch = <3>; - vback-porch = <15>; - }; - - port { - panel_in: endpoint { - remote-endpoint = <&lvds_connector>; - }; - }; - }; -}; - -&lvds_connector { - remote-endpoint = <&panel_in>; -}; diff --git a/sys/gnu/dts/arm/r9a06g032-rzn1d400-db.dts b/sys/gnu/dts/arm/r9a06g032-rzn1d400-db.dts deleted file mode 100644 index 4e57ae2688f..00000000000 --- a/sys/gnu/dts/arm/r9a06g032-rzn1d400-db.dts +++ /dev/null @@ -1,28 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the RZN1D-DB Board - * - * Copyright (C) 2018 Renesas Electronics Europe Limited - * - */ - -/dts-v1/; - -#include "r9a06g032.dtsi" - -/ { - model = "RZN1D-DB Board"; - compatible = "renesas,rzn1d400-db", "renesas,r9a06g032"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - aliases { - serial0 = &uart0; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/r9a06g032.dtsi b/sys/gnu/dts/arm/r9a06g032.dtsi deleted file mode 100644 index 4c1ab49c7d3..00000000000 --- a/sys/gnu/dts/arm/r9a06g032.dtsi +++ /dev/null @@ -1,201 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Base Device Tree Source for the Renesas RZ/N1D (R9A06G032) - * - * Copyright (C) 2018 Renesas Electronics Europe Limited - * - */ - -#include -#include - -/ { - compatible = "renesas,r9a06g032"; - #address-cells = <1>; - #size-cells = <1>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0>; - clocks = <&sysctrl R9A06G032_CLK_A7MP>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <1>; - clocks = <&sysctrl R9A06G032_CLK_A7MP>; - enable-method = "renesas,r9a06g032-smp"; - cpu-release-addr = <0 0x4000c204>; - }; - }; - - ext_jtag_clk: extjtagclk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - ext_mclk: extmclk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <40000000>; - }; - - ext_rgmii_ref: extrgmiiref { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - ext_rtc_clk: extrtcclk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&gic>; - ranges; - - sysctrl: system-controller@4000c000 { - compatible = "renesas,r9a06g032-sysctrl"; - reg = <0x4000c000 0x1000>; - status = "okay"; - #clock-cells = <1>; - - clocks = <&ext_mclk>, <&ext_rtc_clk>, - <&ext_jtag_clk>, <&ext_rgmii_ref>; - clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext"; - }; - - uart0: serial@40060000 { - compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart"; - reg = <0x40060000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&sysctrl R9A06G032_CLK_UART0>, <&sysctrl R9A06G032_HCLK_UART0>; - clock-names = "baudclk", "apb_pclk"; - status = "disabled"; - }; - - uart1: serial@40061000 { - compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart"; - reg = <0x40061000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&sysctrl R9A06G032_CLK_UART1>, <&sysctrl R9A06G032_HCLK_UART1>; - clock-names = "baudclk", "apb_pclk"; - status = "disabled"; - }; - - uart2: serial@40062000 { - compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart"; - reg = <0x40062000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&sysctrl R9A06G032_CLK_UART2>, <&sysctrl R9A06G032_HCLK_UART2>; - clock-names = "baudclk", "apb_pclk"; - status = "disabled"; - }; - - uart3: serial@50000000 { - compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart"; - reg = <0x50000000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&sysctrl R9A06G032_CLK_UART3>, <&sysctrl R9A06G032_HCLK_UART3>; - clock-names = "baudclk", "apb_pclk"; - status = "disabled"; - }; - - uart4: serial@50001000 { - compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart"; - reg = <0x50001000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&sysctrl R9A06G032_CLK_UART4>, <&sysctrl R9A06G032_HCLK_UART4>; - clock-names = "baudclk", "apb_pclk"; - status = "disabled"; - }; - - uart5: serial@50002000 { - compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart"; - reg = <0x50002000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&sysctrl R9A06G032_CLK_UART5>, <&sysctrl R9A06G032_HCLK_UART5>; - clock-names = "baudclk", "apb_pclk"; - status = "disabled"; - }; - - uart6: serial@50003000 { - compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart"; - reg = <0x50003000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&sysctrl R9A06G032_CLK_UART6>, <&sysctrl R9A06G032_HCLK_UART6>; - clock-names = "baudclk", "apb_pclk"; - status = "disabled"; - }; - - uart7: serial@50004000 { - compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart"; - reg = <0x50004000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&sysctrl R9A06G032_CLK_UART7>, <&sysctrl R9A06G032_HCLK_UART7>; - clock-names = "baudclk", "apb_pclk"; - status = "disabled"; - }; - - pinctrl: pin-controller@40067000 { - compatible = "renesas,r9a06g032-pinctrl", "renesas,rzn1-pinctrl"; - reg = <0x40067000 0x1000>, <0x51000000 0x480>; - clocks = <&sysctrl R9A06G032_HCLK_PINCONFIG>; - clock-names = "bus"; - status = "okay"; - }; - - gic: interrupt-controller@44101000 { - compatible = "arm,cortex-a7-gic", "arm,gic-400"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0x44101000 0x1000>, /* Distributer */ - <0x44102000 0x2000>, /* CPU interface */ - <0x44104000 0x2000>, /* Virt interface control */ - <0x44106000 0x2000>; /* Virt CPU interface */ - interrupts = - ; - }; - }; - - timer { - compatible = "arm,cortex-a7-timer", - "arm,armv7-timer"; - interrupt-parent = <&gic>; - arm,cpu-registers-not-fw-configured; - always-on; - interrupts = - , - , - , - ; - }; -}; diff --git a/sys/gnu/dts/arm/rda8810pl-orangepi-2g-iot.dts b/sys/gnu/dts/arm/rda8810pl-orangepi-2g-iot.dts deleted file mode 100644 index 98e34248ae8..00000000000 --- a/sys/gnu/dts/arm/rda8810pl-orangepi-2g-iot.dts +++ /dev/null @@ -1,50 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 Andreas Färber - * Copyright (c) 2018 Manivannan Sadhasivam - */ - -/dts-v1/; - -#include "rda8810pl.dtsi" - -/ { - compatible = "xunlong,orangepi-2g-iot", "rda,8810pl"; - model = "Orange Pi 2G-IoT"; - - aliases { - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - }; - - chosen { - stdout-path = "serial2:921600n8"; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x10000000>; - }; - - uart_clk: uart-clk { - compatible = "fixed-clock"; - clock-frequency = <921600>; - #clock-cells = <0>; - }; -}; - -&uart1 { - status = "okay"; - clocks = <&uart_clk>; -}; - -&uart2 { - status = "okay"; - clocks = <&uart_clk>; -}; - -&uart3 { - status = "okay"; - clocks = <&uart_clk>; -}; diff --git a/sys/gnu/dts/arm/rda8810pl-orangepi-i96.dts b/sys/gnu/dts/arm/rda8810pl-orangepi-i96.dts deleted file mode 100644 index 728f76931b9..00000000000 --- a/sys/gnu/dts/arm/rda8810pl-orangepi-i96.dts +++ /dev/null @@ -1,50 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 Andreas Färber - * Copyright (c) 2018 Manivannan Sadhasivam - */ - -/dts-v1/; - -#include "rda8810pl.dtsi" - -/ { - compatible = "xunlong,orangepi-i96", "rda,8810pl"; - model = "Orange Pi i96"; - - aliases { - serial0 = &uart2; - serial1 = &uart1; - serial2 = &uart3; - }; - - chosen { - stdout-path = "serial2:921600n8"; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x10000000>; - }; - - uart_clk: uart-clk { - compatible = "fixed-clock"; - clock-frequency = <921600>; - #clock-cells = <0>; - }; -}; - -&uart1 { - status = "okay"; - clocks = <&uart_clk>; -}; - -&uart2 { - status = "okay"; - clocks = <&uart_clk>; -}; - -&uart3 { - status = "okay"; - clocks = <&uart_clk>; -}; diff --git a/sys/gnu/dts/arm/rda8810pl.dtsi b/sys/gnu/dts/arm/rda8810pl.dtsi deleted file mode 100644 index f30d6ece49f..00000000000 --- a/sys/gnu/dts/arm/rda8810pl.dtsi +++ /dev/null @@ -1,147 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * RDA8810PL SoC - * - * Copyright (c) 2017 Andreas Färber - * Copyright (c) 2018 Manivannan Sadhasivam - */ - -#include - -/ { - compatible = "rda,8810pl"; - interrupt-parent = <&intc>; - #address-cells = <1>; - #size-cells = <1>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a5"; - reg = <0x0>; - }; - }; - - sram@100000 { - compatible = "mmio-sram"; - reg = <0x100000 0x10000>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - }; - - modem@10000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x10000000 0xfffffff>; - - gpioc@1a08000 { - compatible = "rda,8810pl-gpio"; - reg = <0x1a08000 0x1000>; - gpio-controller; - #gpio-cells = <2>; - ngpios = <32>; - }; - }; - - apb@20800000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x20800000 0x100000>; - - intc: interrupt-controller@0 { - compatible = "rda,8810pl-intc"; - reg = <0x0 0x1000>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - apb@20900000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x20900000 0x100000>; - - timer@10000 { - compatible = "rda,8810pl-timer"; - reg = <0x10000 0x1000>; - interrupts = <16 IRQ_TYPE_LEVEL_HIGH>, - <17 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "hwtimer", "ostimer"; - }; - - gpioa@30000 { - compatible = "rda,8810pl-gpio"; - reg = <0x30000 0x1000>; - gpio-controller; - #gpio-cells = <2>; - ngpios = <32>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <12 IRQ_TYPE_LEVEL_HIGH>; - }; - - gpiob@31000 { - compatible = "rda,8810pl-gpio"; - reg = <0x31000 0x1000>; - gpio-controller; - #gpio-cells = <2>; - ngpios = <32>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <13 IRQ_TYPE_LEVEL_HIGH>; - }; - - gpiod@32000 { - compatible = "rda,8810pl-gpio"; - reg = <0x32000 0x1000>; - gpio-controller; - #gpio-cells = <2>; - ngpios = <32>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - - apb@20a00000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x20a00000 0x100000>; - - uart1: serial@0 { - compatible = "rda,8810pl-uart"; - reg = <0x0 0x1000>; - interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - uart2: serial@10000 { - compatible = "rda,8810pl-uart"; - reg = <0x10000 0x1000>; - interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - uart3: serial@90000 { - compatible = "rda,8810pl-uart"; - reg = <0x90000 0x1000>; - interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - }; - - l2: cache-controller@21100000 { - compatible = "arm,pl310-cache"; - reg = <0x21100000 0x1000>; - cache-unified; - cache-level = <2>; - }; -}; diff --git a/sys/gnu/dts/arm/rk1108-evb.dts b/sys/gnu/dts/arm/rk1108-evb.dts deleted file mode 100644 index 3956cff4ca7..00000000000 --- a/sys/gnu/dts/arm/rk1108-evb.dts +++ /dev/null @@ -1,69 +0,0 @@ -/* - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include "rk1108.dtsi" - -/ { - model = "Rockchip RK1108 Evaluation board"; - compatible = "rockchip,rk1108-evb", "rockchip,rk1108"; - - memory@60000000 { - device_type = "memory"; - reg = <0x60000000 0x08000000>; - }; - - chosen { - stdout-path = "serial2:1500000n8"; - }; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/rk1108.dtsi b/sys/gnu/dts/arm/rk1108.dtsi deleted file mode 100644 index 1297924db6a..00000000000 --- a/sys/gnu/dts/arm/rk1108.dtsi +++ /dev/null @@ -1,452 +0,0 @@ -/* - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include -#include -#include -#include -#include -/ { - #address-cells = <1>; - #size-cells = <1>; - - compatible = "rockchip,rk1108"; - - interrupt-parent = <&gic>; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@f00 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0xf00>; - }; - }; - - arm-pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts = ; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = , - ; - clock-frequency = <24000000>; - }; - - xin24m: oscillator { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "xin24m"; - #clock-cells = <0>; - }; - - amba { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - pdma: pdma@102a0000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x102a0000 0x4000>; - interrupts = ; - #dma-cells = <1>; - arm,pl330-broken-no-flushp; - clocks = <&cru ACLK_DMAC>; - clock-names = "apb_pclk"; - }; - }; - - bus_intmem@10080000 { - compatible = "mmio-sram"; - reg = <0x10080000 0x2000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x10080000 0x2000>; - }; - - uart2: serial@10210000 { - compatible = "rockchip,rk1108-uart", "snps,dw-apb-uart"; - reg = <0x10210000 0x100>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; - clock-names = "baudclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart2m0_xfer>; - status = "disabled"; - }; - - uart1: serial@10220000 { - compatible = "rockchip,rk1108-uart", "snps,dw-apb-uart"; - reg = <0x10220000 0x100>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; - clock-names = "baudclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart1_xfer>; - status = "disabled"; - }; - - uart0: serial@10230000 { - compatible = "rockchip,rk1108-uart", "snps,dw-apb-uart"; - reg = <0x10230000 0x100>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; - clock-names = "baudclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; - status = "disabled"; - }; - - grf: syscon@10300000 { - compatible = "rockchip,rk1108-grf", "syscon"; - reg = <0x10300000 0x1000>; - }; - - pmugrf: syscon@20060000 { - compatible = "rockchip,rk1108-pmugrf", "syscon"; - reg = <0x20060000 0x1000>; - }; - - cru: clock-controller@20200000 { - compatible = "rockchip,rk1108-cru"; - reg = <0x20200000 0x1000>; - rockchip,grf = <&grf>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - emmc: dwmmc@30110000 { - compatible = "rockchip,rk1108-dw-mshc", "rockchip,rk3288-dw-mshc"; - clock-freq-min-max = <400000 150000000>; - clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, - <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - interrupts = ; - reg = <0x30110000 0x4000>; - status = "disabled"; - }; - - sdio: dwmmc@30120000 { - compatible = "rockchip,rk1108-dw-mshc", "rockchip,rk3288-dw-mshc"; - clock-freq-min-max = <400000 150000000>; - clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, - <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - interrupts = ; - reg = <0x30120000 0x4000>; - status = "disabled"; - }; - - sdmmc: dwmmc@30130000 { - compatible = "rockchip,rk1108-dw-mshc", "rockchip,rk3288-dw-mshc"; - clock-freq-min-max = <400000 100000000>; - clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, - <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - interrupts = ; - reg = <0x30130000 0x4000>; - status = "disabled"; - }; - - gic: interrupt-controller@32010000 { - compatible = "arm,gic-400"; - interrupt-controller; - #interrupt-cells = <3>; - #address-cells = <0>; - - reg = <0x32011000 0x1000>, - <0x32012000 0x2000>, - <0x32014000 0x2000>, - <0x32016000 0x2000>; - interrupts = ; - }; - - pinctrl: pinctrl { - compatible = "rockchip,rv1108-pinctrl"; - rockchip,grf = <&grf>; - rockchip,pmu = <&pmugrf>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gpio0: gpio0@20030000 { - compatible = "rockchip,gpio-bank"; - reg = <0x20030000 0x100>; - interrupts = ; - clocks = <&xin24m>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio1@10310000 { - compatible = "rockchip,gpio-bank"; - reg = <0x10310000 0x100>; - interrupts = ; - clocks = <&xin24m>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio2@10320000 { - compatible = "rockchip,gpio-bank"; - reg = <0x10320000 0x100>; - interrupts = ; - clocks = <&xin24m>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio3@10330000 { - compatible = "rockchip,gpio-bank"; - reg = <0x10330000 0x100>; - interrupts = ; - clocks = <&xin24m>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - pcfg_pull_up: pcfg-pull-up { - bias-pull-up; - }; - - pcfg_pull_down: pcfg-pull-down { - bias-pull-down; - }; - - pcfg_pull_none: pcfg-pull-none { - bias-disable; - }; - - pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma { - drive-strength = <8>; - }; - - pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma { - drive-strength = <12>; - }; - - pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma { - bias-pull-up; - drive-strength = <8>; - }; - - pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma { - drive-strength = <4>; - }; - - pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma { - bias-pull-up; - drive-strength = <4>; - }; - - pcfg_output_high: pcfg-output-high { - output-high; - }; - - pcfg_output_low: pcfg-output-low { - output-low; - }; - - pcfg_input_high: pcfg-input-high { - bias-pull-up; - input-enable; - }; - - i2c1 { - i2c1_xfer: i2c1-xfer { - rockchip,pins = <2 RK_PD3 RK_FUNC_1 &pcfg_pull_up>, - <2 RK_PD4 RK_FUNC_1 &pcfg_pull_up>; - }; - }; - - i2c2m1 { - i2c2m1_xfer: i2c2m1-xfer { - rockchip,pins = <0 RK_PC2 RK_FUNC_2 &pcfg_pull_none>, - <0 RK_PC6 RK_FUNC_3 &pcfg_pull_none>; - }; - - i2c2m1_gpio: i2c2m1-gpio { - rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>, - <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - i2c2m05v { - i2c2m05v_xfer: i2c2m05v-xfer { - rockchip,pins = <1 RK_PD5 RK_FUNC_2 &pcfg_pull_none>, - <1 RK_PD4 RK_FUNC_2 &pcfg_pull_none>; - }; - - i2c2m05v_gpio: i2c2m05v-gpio { - rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>, - <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - i2c3 { - i2c3_xfer: i2c3-xfer { - rockchip,pins = <0 RK_PB6 RK_FUNC_1 &pcfg_pull_none>, - <0 RK_PC4 RK_FUNC_2 &pcfg_pull_none>; - }; - }; - - sdmmc { - sdmmc_clk: sdmmc-clk { - rockchip,pins = <3 RK_PC4 RK_FUNC_1 &pcfg_pull_none_drv_4ma>; - }; - - sdmmc_cmd: sdmmc-cmd { - rockchip,pins = <3 RK_PC5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>; - }; - - sdmmc_cd: sdmmc-cd { - rockchip,pins = <0 RK_PA1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>; - }; - - sdmmc_bus1: sdmmc-bus1 { - rockchip,pins = <3 RK_PC3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>; - }; - - sdmmc_bus4: sdmmc-bus4 { - rockchip,pins = <3 RK_PC3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>, - <3 RK_PC2 RK_FUNC_1 &pcfg_pull_up_drv_4ma>, - <3 RK_PC1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>, - <3 RK_PC0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>; - }; - }; - - uart0 { - uart0_xfer: uart0-xfer { - rockchip,pins = <3 RK_PA6 RK_FUNC_1 &pcfg_pull_up>, - <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none>; - }; - - uart0_cts: uart0-cts { - rockchip,pins = <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none>; - }; - - uart0_rts: uart0-rts { - rockchip,pins = <3 RK_PA3 RK_FUNC_1 &pcfg_pull_none>; - }; - - uart0_rts_gpio: uart0-rts-gpio { - rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - uart1 { - uart1_xfer: uart1-xfer { - rockchip,pins = <1 RK_PD3 RK_FUNC_1 &pcfg_pull_up>, - <1 RK_PD2 RK_FUNC_1 &pcfg_pull_none>; - }; - - uart1_cts: uart1-cts { - rockchip,pins = <1 RK_PD0 RK_FUNC_1 &pcfg_pull_none>; - }; - - uart1_rts: uart1-rts { - rockchip,pins = <1 RK_PD1 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - - uart2m0 { - uart2m0_xfer: uart2m0-xfer { - rockchip,pins = <2 RK_PD2 RK_FUNC_1 &pcfg_pull_up>, - <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - - uart2m1 { - uart2m1_xfer: uart2m1-xfer { - rockchip,pins = <3 RK_PC3 RK_FUNC_2 &pcfg_pull_up>, - <3 RK_PC2 RK_FUNC_2 &pcfg_pull_none>; - }; - }; - - uart2_5v { - uart2_5v_cts: uart2_5v-cts { - rockchip,pins = <1 RK_PD4 RK_FUNC_1 &pcfg_pull_none>; - }; - - uart2_5v_rts: uart2_5v-rts { - rockchip,pins = <1 RK_PD5 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/rk3036-evb.dts b/sys/gnu/dts/arm/rk3036-evb.dts deleted file mode 100644 index 2a7e6624efb..00000000000 --- a/sys/gnu/dts/arm/rk3036-evb.dts +++ /dev/null @@ -1,45 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -/dts-v1/; - -#include "rk3036.dtsi" - -/ { - model = "Rockchip RK3036 Evaluation board"; - compatible = "rockchip,rk3036-evb", "rockchip,rk3036"; - - memory@60000000 { - device_type = "memory"; - reg = <0x60000000 0x40000000>; - }; -}; - -&emac { - pinctrl-names = "default"; - pinctrl-0 = <&emac_xfer>, <&emac_mdio>; - phy = <&phy0>; - phy-reset-gpios = <&gpio2 RK_PC6 GPIO_ACTIVE_LOW>; /* PHY_RST */ - phy-reset-duration = <10>; /* millisecond */ - - status = "okay"; - - phy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -&i2c1 { - status = "okay"; - - hym8563: hym8563@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "xin32k"; - }; -}; - -&uart2 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/rk3036-kylin.dts b/sys/gnu/dts/arm/rk3036-kylin.dts deleted file mode 100644 index fb3cf005cc9..00000000000 --- a/sys/gnu/dts/arm/rk3036-kylin.dts +++ /dev/null @@ -1,398 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -/dts-v1/; - -#include "rk3036.dtsi" - -/ { - model = "Rockchip RK3036 KylinBoard"; - compatible = "rockchip,rk3036-kylin", "rockchip,rk3036"; - - memory@60000000 { - device_type = "memory"; - reg = <0x60000000 0x20000000>; - }; - - leds: gpio-leds { - compatible = "gpio-leds"; - - work { - gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; - label = "kylin:red:led"; - pinctrl-names = "default"; - pinctrl-0 = <&led_ctl>; - }; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - pinctrl-names = "default"; - pinctrl-0 = <&bt_wake_h>; - - /* - * On the module itself this is one of these (depending - * on the actual card populated): - * - SDIO_RESET_L_WL_REG_ON - * - SDIO_RESET_L_WL_RST - * - SDIO_RESET_L_BT_EN - */ - reset-gpios = <&gpio0 RK_PD2 GPIO_ACTIVE_LOW>, /* WL_REG_ON */ - <&gpio0 RK_PD3 GPIO_ACTIVE_LOW>, /* WL_RST */ - <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>; /* BT_EN */ - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,name = "rockchip,rt5616-codec"; - simple-audio-card,mclk-fs = <512>; - simple-audio-card,widgets = - "Microphone", "Microphone Jack", - "Headphone", "Headphone Jack"; - simple-audio-card,routing = - "MIC1", "Microphone Jack", - "MIC2", "Microphone Jack", - "Microphone Jack", "micbias1", - "Headphone Jack", "HPOL", - "Headphone Jack", "HPOR"; - - simple-audio-card,cpu { - sound-dai = <&i2s>; - }; - - simple-audio-card,codec { - sound-dai = <&rt5616>; - }; - }; - - vcc_sys: vsys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; -}; - -&acodec { - status = "okay"; -}; - -&emac { - pinctrl-names = "default"; - pinctrl-0 = <&emac_xfer>, <&emac_mdio>; - phy = <&phy0>; - phy-reset-gpios = <&gpio2 RK_PC6 GPIO_ACTIVE_LOW>; /* PHY_RST */ - phy-reset-duration = <10>; /* millisecond */ - - status = "okay"; - - phy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -&emmc { - status = "okay"; -}; - -&gpu { - mali-supply = <&vdd_gpu>; - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&i2c1 { - clock-frequency = <400000>; - - status = "okay"; - - rk808: pmic@1b { - compatible = "rockchip,rk808"; - reg = <0x1b>; - interrupt-parent = <&gpio2>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int &global_pwroff>; - rockchip,system-power-controller; - wakeup-source; - #clock-cells = <1>; - clock-output-names = "xin32k", "rk808-clkout2"; - - vcc1-supply = <&vcc_sys>; - vcc2-supply = <&vcc_sys>; - vcc3-supply = <&vcc_sys>; - vcc4-supply = <&vcc_sys>; - vcc6-supply = <&vcc_sys>; - vcc7-supply = <&vcc_sys>; - vcc8-supply = <&vcc_18>; - vcc9-supply = <&vcc_io>; - vcc10-supply = <&vcc_io>; - vcc11-supply = <&vcc_sys>; - vcc12-supply = <&vcc_io>; - vddio-supply = <&vccio_pmu>; - - regulators { - vdd_cpu: DCDC_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-name = "vdd_arm"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_gpu: DCDC_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1250000>; - regulator-name = "vdd_gpu"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc_ddr"; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_io: DCDC_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc_io"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vccio_pmu: LDO_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vccio_pmu"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc_tp: LDO_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc_tp"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_10: LDO_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-name = "vdd_10"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vcc18_lcd: LDO_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc18_lcd"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vccio_sd: LDO_REG5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vccio_sd"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vout5: LDO_REG6 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2500000>; - regulator-name = "vout5"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc_18: LDO_REG7 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc_18"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcca_codec: LDO_REG8 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcca_codec"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc_wl: SWITCH_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc_wl"; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_lcd: SWITCH_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc_lcd"; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - }; - }; -}; - -&i2c2 { - status = "okay"; - - rt5616: rt5616@1b { - compatible = "rt5616"; - reg = <0x1b>; - clocks = <&cru SCLK_I2S_OUT>; - clock-names = "mclk"; - #sound-dai-cells = <0>; - }; -}; - -&i2s { - status = "okay"; -}; - -&sdio { - status = "okay"; - - bus-width = <4>; - cap-sd-highspeed; - cap-sdio-irq; - default-sample-phase = <90>; - keep-power-in-suspend; - mmc-pwrseq = <&sdio_pwrseq>; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-sdr104; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - card-detect-delay = <200>; - disable-wp; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_cd>, <&sdmmc_bus4>; -}; - -&uart0 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&usb_host { - status = "okay"; -}; - -&usb_otg { - status = "okay"; -}; - -&vop { - status = "okay"; -}; - -&vop_mmu { - status = "okay"; -}; - -&pinctrl { - leds { - led_ctl: led-ctl { - rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - pmic_int: pmic-int { - rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_default>; - }; - }; - - sdio { - bt_wake_h: bt-wake-h { - rockchip,pins = <2 RK_PB0 RK_FUNC_GPIO &pcfg_pull_default>; - }; - }; - - sdmmc { - sdmmc_pwr: sdmmc-pwr { - rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - sleep { - global_pwroff: global-pwroff { - rockchip,pins = <2 RK_PA7 1 &pcfg_pull_none>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/rk3036.dtsi b/sys/gnu/dts/arm/rk3036.dtsi deleted file mode 100644 index cf36e25195b..00000000000 --- a/sys/gnu/dts/arm/rk3036.dtsi +++ /dev/null @@ -1,761 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -#include -#include -#include -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - - compatible = "rockchip,rk3036"; - - interrupt-parent = <&gic>; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - mshc0 = &emmc; - mshc1 = &sdmmc; - mshc2 = &sdio; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - spi = &spi; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "rockchip,rk3036-smp"; - - cpu0: cpu@f00 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0xf00>; - resets = <&cru SRST_CORE0>; - operating-points = < - /* KHz uV */ - 816000 1000000 - >; - clock-latency = <40000>; - clocks = <&cru ARMCLK>; - }; - - cpu1: cpu@f01 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0xf01>; - resets = <&cru SRST_CORE1>; - }; - }; - - amba { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - pdma: pdma@20078000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x20078000 0x4000>; - interrupts = , - ; - #dma-cells = <1>; - arm,pl330-broken-no-flushp; - clocks = <&cru ACLK_DMAC2>; - clock-names = "apb_pclk"; - }; - }; - - arm-pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts = , - ; - interrupt-affinity = <&cpu0>, <&cpu1>; - }; - - display-subsystem { - compatible = "rockchip,display-subsystem"; - ports = <&vop_out>; - }; - - timer { - compatible = "arm,armv7-timer"; - arm,cpu-registers-not-fw-configured; - interrupts = , - , - , - ; - clock-frequency = <24000000>; - }; - - xin24m: oscillator { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "xin24m"; - #clock-cells = <0>; - }; - - bus_intmem@10080000 { - compatible = "mmio-sram"; - reg = <0x10080000 0x2000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x10080000 0x2000>; - - smp-sram@0 { - compatible = "rockchip,rk3066-smp-sram"; - reg = <0x00 0x10>; - }; - }; - - gpu: gpu@10090000 { - compatible = "rockchip,rk3036-mali", "arm,mali-400"; - reg = <0x10090000 0x10000>; - interrupts = , - , - , - ; - interrupt-names = "gp", - "gpmmu", - "pp0", - "ppmmu0"; - assigned-clocks = <&cru SCLK_GPU>; - assigned-clock-rates = <100000000>; - clocks = <&cru SCLK_GPU>, <&cru SCLK_GPU>; - clock-names = "core", "bus"; - resets = <&cru SRST_GPU>; - status = "disabled"; - }; - - vop: vop@10118000 { - compatible = "rockchip,rk3036-vop"; - reg = <0x10118000 0x19c>; - interrupts = ; - clocks = <&cru ACLK_LCDC>, <&cru SCLK_LCDC>, <&cru HCLK_LCDC>; - clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; - resets = <&cru SRST_LCDC1_A>, <&cru SRST_LCDC1_H>, <&cru SRST_LCDC1_D>; - reset-names = "axi", "ahb", "dclk"; - iommus = <&vop_mmu>; - status = "disabled"; - - vop_out: port { - #address-cells = <1>; - #size-cells = <0>; - vop_out_hdmi: endpoint@0 { - reg = <0>; - remote-endpoint = <&hdmi_in_vop>; - }; - }; - }; - - vop_mmu: iommu@10118300 { - compatible = "rockchip,iommu"; - reg = <0x10118300 0x100>; - interrupts = ; - interrupt-names = "vop_mmu"; - clocks = <&cru ACLK_LCDC>, <&cru HCLK_LCDC>; - clock-names = "aclk", "iface"; - #iommu-cells = <0>; - status = "disabled"; - }; - - gic: interrupt-controller@10139000 { - compatible = "arm,gic-400"; - interrupt-controller; - #interrupt-cells = <3>; - #address-cells = <0>; - - reg = <0x10139000 0x1000>, - <0x1013a000 0x2000>, - <0x1013c000 0x2000>, - <0x1013e000 0x2000>; - interrupts = ; - }; - - usb_otg: usb@10180000 { - compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb", - "snps,dwc2"; - reg = <0x10180000 0x40000>; - interrupts = ; - clocks = <&cru HCLK_OTG0>; - clock-names = "otg"; - dr_mode = "otg"; - g-np-tx-fifo-size = <16>; - g-rx-fifo-size = <275>; - g-tx-fifo-size = <256 128 128 64 64 32>; - status = "disabled"; - }; - - usb_host: usb@101c0000 { - compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb", - "snps,dwc2"; - reg = <0x101c0000 0x40000>; - interrupts = ; - clocks = <&cru HCLK_OTG1>; - clock-names = "otg"; - dr_mode = "host"; - status = "disabled"; - }; - - emac: ethernet@10200000 { - compatible = "rockchip,rk3036-emac", "snps,arc-emac"; - reg = <0x10200000 0x4000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - rockchip,grf = <&grf>; - clocks = <&cru HCLK_MAC>, <&cru SCLK_MACREF>, <&cru SCLK_MAC>; - clock-names = "hclk", "macref", "macclk"; - /* - * Fix the emac parent clock is DPLL instead of APLL. - * since that will cause some unstable things if the cpufreq - * is working. (e.g: the accurate 50MHz what mac_ref need) - */ - assigned-clocks = <&cru SCLK_MACPLL>; - assigned-clock-parents = <&cru PLL_DPLL>; - max-speed = <100>; - phy-mode = "rmii"; - status = "disabled"; - }; - - sdmmc: mmc@10214000 { - compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x10214000 0x4000>; - clock-frequency = <37500000>; - max-frequency = <37500000>; - clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; - clock-names = "biu", "ciu"; - fifo-depth = <0x100>; - interrupts = ; - resets = <&cru SRST_MMC0>; - reset-names = "reset"; - status = "disabled"; - }; - - sdio: mmc@10218000 { - compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x10218000 0x4000>; - max-frequency = <37500000>; - clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, - <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - interrupts = ; - resets = <&cru SRST_SDIO>; - reset-names = "reset"; - status = "disabled"; - }; - - emmc: mmc@1021c000 { - compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x1021c000 0x4000>; - interrupts = ; - bus-width = <8>; - cap-mmc-highspeed; - clock-frequency = <37500000>; - max-frequency = <37500000>; - clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, - <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - default-sample-phase = <158>; - disable-wp; - dmas = <&pdma 12>; - dma-names = "rx-tx"; - fifo-depth = <0x100>; - mmc-ddr-1_8v; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; - resets = <&cru SRST_EMMC>; - reset-names = "reset"; - status = "disabled"; - }; - - i2s: i2s@10220000 { - compatible = "rockchip,rk3036-i2s", "rockchip,rk3066-i2s"; - reg = <0x10220000 0x4000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2s_clk", "i2s_hclk"; - clocks = <&cru SCLK_I2S>, <&cru HCLK_I2S>; - dmas = <&pdma 0>, <&pdma 1>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&i2s_bus>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - cru: clock-controller@20000000 { - compatible = "rockchip,rk3036-cru"; - reg = <0x20000000 0x1000>; - rockchip,grf = <&grf>; - #clock-cells = <1>; - #reset-cells = <1>; - assigned-clocks = <&cru PLL_GPLL>; - assigned-clock-rates = <594000000>; - }; - - grf: syscon@20008000 { - compatible = "rockchip,rk3036-grf", "syscon", "simple-mfd"; - reg = <0x20008000 0x1000>; - - reboot-mode { - compatible = "syscon-reboot-mode"; - offset = <0x1d8>; - mode-normal = ; - mode-recovery = ; - mode-bootloader = ; - mode-loader = ; - }; - }; - - acodec: acodec-ana@20030000 { - compatible = "rk3036-codec"; - reg = <0x20030000 0x4000>; - rockchip,grf = <&grf>; - clock-names = "acodec_pclk"; - clocks = <&cru PCLK_ACODEC>; - status = "disabled"; - }; - - hdmi: hdmi@20034000 { - compatible = "rockchip,rk3036-inno-hdmi"; - reg = <0x20034000 0x4000>; - interrupts = ; - clocks = <&cru PCLK_HDMI>; - clock-names = "pclk"; - rockchip,grf = <&grf>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_ctl>; - status = "disabled"; - - hdmi_in: port { - #address-cells = <1>; - #size-cells = <0>; - hdmi_in_vop: endpoint@0 { - reg = <0>; - remote-endpoint = <&vop_out_hdmi>; - }; - }; - }; - - timer: timer@20044000 { - compatible = "rockchip,rk3036-timer", "rockchip,rk3288-timer"; - reg = <0x20044000 0x20>; - interrupts = ; - clocks = <&xin24m>, <&cru PCLK_TIMER>; - clock-names = "timer", "pclk"; - }; - - pwm0: pwm@20050000 { - compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm"; - reg = <0x20050000 0x10>; - #pwm-cells = <3>; - clocks = <&cru PCLK_PWM>; - clock-names = "pwm"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pin>; - status = "disabled"; - }; - - pwm1: pwm@20050010 { - compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm"; - reg = <0x20050010 0x10>; - #pwm-cells = <3>; - clocks = <&cru PCLK_PWM>; - clock-names = "pwm"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm1_pin>; - status = "disabled"; - }; - - pwm2: pwm@20050020 { - compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm"; - reg = <0x20050020 0x10>; - #pwm-cells = <3>; - clocks = <&cru PCLK_PWM>; - clock-names = "pwm"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm2_pin>; - status = "disabled"; - }; - - pwm3: pwm@20050030 { - compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm"; - reg = <0x20050030 0x10>; - #pwm-cells = <2>; - clocks = <&cru PCLK_PWM>; - clock-names = "pwm"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm3_pin>; - status = "disabled"; - }; - - i2c1: i2c@20056000 { - compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c"; - reg = <0x20056000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C1>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_xfer>; - status = "disabled"; - }; - - i2c2: i2c@2005a000 { - compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c"; - reg = <0x2005a000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C2>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_xfer>; - status = "disabled"; - }; - - uart0: serial@20060000 { - compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart"; - reg = <0x20060000 0x100>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; - clock-names = "baudclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; - status = "disabled"; - }; - - uart1: serial@20064000 { - compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart"; - reg = <0x20064000 0x100>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; - clock-names = "baudclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart1_xfer>; - status = "disabled"; - }; - - uart2: serial@20068000 { - compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart"; - reg = <0x20068000 0x100>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; - clock-names = "baudclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart2_xfer>; - status = "disabled"; - }; - - i2c0: i2c@20072000 { - compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c"; - reg = <0x20072000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_xfer>; - status = "disabled"; - }; - - spi: spi@20074000 { - compatible = "rockchip,rockchip-spi"; - reg = <0x20074000 0x1000>; - interrupts = ; - clocks = <&cru PCLK_SPI>, <&cru SCLK_SPI>; - clock-names = "apb-pclk","spi_pclk"; - dmas = <&pdma 8>, <&pdma 9>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&spi_txd &spi_rxd &spi_clk &spi_cs0>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - pinctrl: pinctrl { - compatible = "rockchip,rk3036-pinctrl"; - rockchip,grf = <&grf>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gpio0: gpio0@2007c000 { - compatible = "rockchip,gpio-bank"; - reg = <0x2007c000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO0>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio1@20080000 { - compatible = "rockchip,gpio-bank"; - reg = <0x20080000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO1>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio2@20084000 { - compatible = "rockchip,gpio-bank"; - reg = <0x20084000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO2>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - pcfg_pull_default: pcfg_pull_default { - bias-pull-pin-default; - }; - - pcfg_pull_none: pcfg-pull-none { - bias-disable; - }; - - pwm0 { - pwm0_pin: pwm0-pin { - rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>; - }; - }; - - pwm1 { - pwm1_pin: pwm1-pin { - rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>; - }; - }; - - pwm2 { - pwm2_pin: pwm2-pin { - rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>; - }; - }; - - pwm3 { - pwm3_pin: pwm3-pin { - rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>; - }; - }; - - sdmmc { - sdmmc_clk: sdmmc-clk { - rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>; - }; - - sdmmc_cmd: sdmmc-cmd { - rockchip,pins = <1 RK_PB7 1 &pcfg_pull_default>; - }; - - sdmmc_cd: sdmmc-cd { - rockchip,pins = <1 RK_PC1 1 &pcfg_pull_default>; - }; - - sdmmc_bus1: sdmmc-bus1 { - rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>; - }; - - sdmmc_bus4: sdmmc-bus4 { - rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>, - <1 RK_PC3 1 &pcfg_pull_default>, - <1 RK_PC4 1 &pcfg_pull_default>, - <1 RK_PC5 1 &pcfg_pull_default>; - }; - }; - - sdio { - sdio_bus1: sdio-bus1 { - rockchip,pins = <0 RK_PB3 1 &pcfg_pull_default>; - }; - - sdio_bus4: sdio-bus4 { - rockchip,pins = <0 RK_PB3 1 &pcfg_pull_default>, - <0 RK_PB4 1 &pcfg_pull_default>, - <0 RK_PB5 1 &pcfg_pull_default>, - <0 RK_PB6 1 &pcfg_pull_default>; - }; - - sdio_cmd: sdio-cmd { - rockchip,pins = <0 RK_PB0 1 &pcfg_pull_default>; - }; - - sdio_clk: sdio-clk { - rockchip,pins = <0 RK_PB1 1 &pcfg_pull_none>; - }; - }; - - emmc { - /* - * We run eMMC at max speed; bump up drive strength. - * We also have external pulls, so disable the internal ones. - */ - emmc_clk: emmc-clk { - rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>; - }; - - emmc_cmd: emmc-cmd { - rockchip,pins = <2 RK_PA1 2 &pcfg_pull_default>; - }; - - emmc_bus8: emmc-bus8 { - rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>, - <1 RK_PD1 2 &pcfg_pull_default>, - <1 RK_PD2 2 &pcfg_pull_default>, - <1 RK_PD3 2 &pcfg_pull_default>, - <1 RK_PD4 2 &pcfg_pull_default>, - <1 RK_PD5 2 &pcfg_pull_default>, - <1 RK_PD6 2 &pcfg_pull_default>, - <1 RK_PD7 2 &pcfg_pull_default>; - }; - }; - - emac { - emac_xfer: emac-xfer { - rockchip,pins = <2 RK_PB2 1 &pcfg_pull_default>, /* crs_dvalid */ - <2 RK_PB5 1 &pcfg_pull_default>, /* tx_en */ - <2 RK_PB6 1 &pcfg_pull_default>, /* mac_clk */ - <2 RK_PB7 1 &pcfg_pull_default>, /* rx_err */ - <2 RK_PC0 1 &pcfg_pull_default>, /* rxd1 */ - <2 RK_PC1 1 &pcfg_pull_default>, /* rxd0 */ - <2 RK_PC2 1 &pcfg_pull_default>, /* txd1 */ - <2 RK_PC3 1 &pcfg_pull_default>; /* txd0 */ - }; - - emac_mdio: emac-mdio { - rockchip,pins = <2 RK_PB4 1 &pcfg_pull_default>, /* mac_md */ - <2 RK_PD1 1 &pcfg_pull_default>; /* mac_mdclk */ - }; - }; - - i2c0 { - i2c0_xfer: i2c0-xfer { - rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>, - <0 RK_PA1 1 &pcfg_pull_none>; - }; - }; - - i2c1 { - i2c1_xfer: i2c1-xfer { - rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>, - <0 RK_PA3 1 &pcfg_pull_none>; - }; - }; - - i2c2 { - i2c2_xfer: i2c2-xfer { - rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>, - <2 RK_PC5 1 &pcfg_pull_none>; - }; - }; - - i2s { - i2s_bus: i2s-bus { - rockchip,pins = <1 RK_PA0 1 &pcfg_pull_default>, - <1 RK_PA1 1 &pcfg_pull_default>, - <1 RK_PA2 1 &pcfg_pull_default>, - <1 RK_PA3 1 &pcfg_pull_default>, - <1 RK_PA4 1 &pcfg_pull_default>, - <1 RK_PA5 1 &pcfg_pull_default>; - }; - }; - - hdmi { - hdmi_ctl: hdmi-ctl { - rockchip,pins = <1 RK_PB0 1 &pcfg_pull_none>, - <1 RK_PB1 1 &pcfg_pull_none>, - <1 RK_PB2 1 &pcfg_pull_none>, - <1 RK_PB3 1 &pcfg_pull_none>; - }; - }; - - uart0 { - uart0_xfer: uart0-xfer { - rockchip,pins = <0 RK_PC0 1 &pcfg_pull_default>, - <0 RK_PC1 1 &pcfg_pull_none>; - }; - - uart0_cts: uart0-cts { - rockchip,pins = <0 RK_PC2 1 &pcfg_pull_default>; - }; - - uart0_rts: uart0-rts { - rockchip,pins = <0 RK_PC3 1 &pcfg_pull_none>; - }; - }; - - uart1 { - uart1_xfer: uart1-xfer { - rockchip,pins = <2 RK_PC6 1 &pcfg_pull_default>, - <2 RK_PC7 1 &pcfg_pull_none>; - }; - /* no rts / cts for uart1 */ - }; - - uart2 { - uart2_xfer: uart2-xfer { - rockchip,pins = <1 RK_PC2 2 &pcfg_pull_default>, - <1 RK_PC3 2 &pcfg_pull_none>; - }; - /* no rts / cts for uart2 */ - }; - - spi-pins { - spi_txd:spi-txd { - rockchip,pins = <1 RK_PD5 3 &pcfg_pull_default>; - }; - - spi_rxd:spi-rxd { - rockchip,pins = <1 RK_PD4 3 &pcfg_pull_default>; - }; - - spi_clk:spi-clk { - rockchip,pins = <2 RK_PA0 2 &pcfg_pull_default>; - }; - - spi_cs0:spi-cs0 { - rockchip,pins = <1 RK_PD6 3 &pcfg_pull_default>; - - }; - - spi_cs1:spi-cs1 { - rockchip,pins = <1 RK_PD7 3 &pcfg_pull_default>; - - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/rk3066a-bqcurie2.dts b/sys/gnu/dts/arm/rk3066a-bqcurie2.dts deleted file mode 100644 index 0a56a2f1bc4..00000000000 --- a/sys/gnu/dts/arm/rk3066a-bqcurie2.dts +++ /dev/null @@ -1,198 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2013 MundoReader S.L. - * Author: Heiko Stuebner - */ - -/dts-v1/; -#include -#include "rk3066a.dtsi" - -/ { - model = "bq Curie 2"; - compatible = "mundoreader,bq-curie2", "rockchip,rk3066a"; - - memory@60000000 { - device_type = "memory"; - reg = <0x60000000 0x40000000>; - }; - - vdd_log: vdd-log { - compatible = "pwm-regulator"; - pwms = <&pwm3 0 1000>; - regulator-name = "vdd_log"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - voltage-table = <1000000 100>, - <1200000 42>; - status = "okay"; - }; - - vcc_sd0: fixed-regulator { - compatible = "regulator-fixed"; - regulator-name = "sdmmc-supply"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_LOW>; - startup-delay-us = <100000>; - vin-supply = <&vcc_io>; - }; - - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - - power { - gpios = <&gpio6 RK_PA2 GPIO_ACTIVE_LOW>; /* GPIO6_A2 */ - linux,code = ; - label = "GPIO Key Power"; - linux,input-type = <1>; - wakeup-source; - debounce-interval = <100>; - }; - volume-down { - gpios = <&gpio4 RK_PC5 GPIO_ACTIVE_LOW>; /* GPIO4_C5 */ - linux,code = ; - label = "GPIO Key Vol-"; - linux,input-type = <1>; - debounce-interval = <100>; - }; - /* VOL+ comes somehow thru the ADC */ - }; -}; - -&cpu0 { - cpu0-supply = <&vdd_arm>; -}; - -&i2c1 { - status = "okay"; - clock-frequency = <400000>; - - tps: tps@2d { - reg = <0x2d>; - - interrupt-parent = <&gpio6>; - interrupts = ; - - vcc5-supply = <&vcc_io>; - vcc6-supply = <&vcc_io>; - - regulators { - vcc_rtc: regulator@0 { - regulator-name = "vcc_rtc"; - regulator-always-on; - }; - - vcc_io: regulator@1 { - regulator-name = "vcc_io"; - regulator-always-on; - }; - - vdd_arm: regulator@2 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - regulator-always-on; - }; - - vcc_ddr: regulator@3 { - regulator-name = "vcc_ddr"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - regulator-always-on; - }; - - vcc18_cif: regulator@5 { - regulator-name = "vcc18_cif"; - regulator-always-on; - }; - - vdd_11: regulator@6 { - regulator-name = "vdd_11"; - regulator-always-on; - }; - - vcc_25: regulator@7 { - regulator-name = "vcc_25"; - regulator-always-on; - }; - - vcc_18: regulator@8 { - regulator-name = "vcc_18"; - regulator-always-on; - }; - - vcc25_hdmi: regulator@9 { - regulator-name = "vcc25_hdmi"; - regulator-always-on; - }; - - vcca_33: regulator@10 { - regulator-name = "vcca_33"; - regulator-always-on; - }; - - vcc_tp: regulator@11 { - regulator-name = "vcc_tp"; - regulator-always-on; - }; - - vcc28_cif: regulator@12 { - regulator-name = "vcc28_cif"; - regulator-always-on; - }; - }; - }; -}; - -/* must be included after &tps gets defined */ -#include "tps65910.dtsi" - -&mmc0 { /* sdmmc */ - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>; - vmmc-supply = <&vcc_sd0>; - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - disable-wp; -}; - -&mmc1 { /* wifi */ - status = "okay"; - non-removable; - - pinctrl-names = "default"; - pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_bus4>; - - bus-width = <4>; -}; - -&pwm3 { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&wdt { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/rk3066a-marsboard.dts b/sys/gnu/dts/arm/rk3066a-marsboard.dts deleted file mode 100644 index 7e01f6406a8..00000000000 --- a/sys/gnu/dts/arm/rk3066a-marsboard.dts +++ /dev/null @@ -1,210 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2014 Romain Perier - */ - -/dts-v1/; -#include "rk3066a.dtsi" - -/ { - model = "MarsBoard RK3066"; - compatible = "haoyu,marsboard-rk3066", "rockchip,rk3066a"; - - memory@60000000 { - device_type = "memory"; - reg = <0x60000000 0x40000000>; - }; - - vdd_log: vdd-log { - compatible = "pwm-regulator"; - pwms = <&pwm3 0 1000>; - regulator-name = "vdd_log"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - voltage-table = <1000000 100>, - <1200000 42>; - status = "okay"; - }; - - vcc_sd0: sdmmc-regulator { - compatible = "regulator-fixed"; - regulator-name = "sdmmc-supply"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_LOW>; - startup-delay-us = <100000>; - vin-supply = <&vcc_io>; - }; - - vsys: vsys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vsys"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - }; -}; - -&cpu0 { - cpu0-supply = <&vdd_arm>; -}; - -&i2c1 { - status = "okay"; - clock-frequency = <400000>; - - tps: tps@2d { - reg = <0x2d>; - - interrupt-parent = <&gpio6>; - interrupts = ; - - vcc1-supply = <&vsys>; - vcc2-supply = <&vsys>; - vcc3-supply = <&vsys>; - vcc4-supply = <&vsys>; - vcc5-supply = <&vcc_io>; - vcc6-supply = <&vcc_io>; - vcc7-supply = <&vsys>; - vccio-supply = <&vsys>; - - regulators { - vcc_rtc: regulator@0 { - regulator-name = "vcc_rtc"; - regulator-always-on; - }; - - vcc_io: regulator@1 { - regulator-name = "vcc_io"; - regulator-always-on; - }; - - vdd_arm: regulator@2 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - regulator-always-on; - }; - - vcc_ddr: regulator@3 { - regulator-name = "vcc_ddr"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - regulator-always-on; - }; - - vcc18_cif: regulator@5 { - regulator-name = "vcc18_cif"; - regulator-always-on; - }; - - vdd_11: regulator@6 { - regulator-name = "vdd_11"; - regulator-always-on; - }; - - vcc_25: regulator@7 { - regulator-name = "vcc_25"; - regulator-always-on; - }; - - vcc_18: regulator@8 { - regulator-name = "vcc_18"; - regulator-always-on; - }; - - vcc25_hdmi: regulator@9 { - regulator-name = "vcc25_hdmi"; - regulator-always-on; - }; - - vcca_33: regulator@10 { - regulator-name = "vcca_33"; - regulator-always-on; - }; - - vcc_rmii: regulator@11 { - regulator-name = "vcc_rmii"; - }; - - vcc28_cif: regulator@12 { - regulator-name = "vcc28_cif"; - regulator-always-on; - }; - }; - }; -}; - -/* must be included after &tps gets defined */ -#include "tps65910.dtsi" - -&emac { - status = "okay"; - - phy = <&phy0>; - phy-supply = <&vcc_rmii>; - - pinctrl-names = "default"; - pinctrl-0 = <&emac_xfer>, <&emac_mdio>, <&phy_int>; - - phy0: ethernet-phy@0 { - reg = <0>; - interrupt-parent = <&gpio1>; - interrupts = ; - }; -}; - -&mmc0 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>; - vmmc-supply = <&vcc_sd0>; -}; - -&pinctrl { - lan8720a { - phy_int: phy-int { - rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&pwm3 { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; - -&usb_host { - status = "okay"; -}; - -&usb_otg { - status = "okay"; -}; - -&wdt { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/rk3066a-mk808.dts b/sys/gnu/dts/arm/rk3066a-mk808.dts deleted file mode 100644 index 365eff62111..00000000000 --- a/sys/gnu/dts/arm/rk3066a-mk808.dts +++ /dev/null @@ -1,184 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Paweł Jarosz - */ - -/dts-v1/; -#include "rk3066a.dtsi" - -/ { - model = "Rikomagic MK808"; - compatible = "rikomagic,mk808", "rockchip,rk3066a"; - - chosen { - stdout-path = "serial2:115200n8"; - }; - - memory@60000000 { - reg = <0x60000000 0x40000000>; - device_type = "memory"; - }; - - gpio-leds { - compatible = "gpio-leds"; - - blue { - label = "mk808:blue:power"; - gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>; - default-state = "off"; - linux,default-trigger = "default-on"; - }; - }; - - hdmi_con { - compatible = "hdmi-connector"; - type = "c"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - vcc_io: vcc-io { - compatible = "regulator-fixed"; - regulator-name = "vcc_io"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vcc_host: usb-host-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; - pinctrl-0 = <&host_drv>; - pinctrl-names = "default"; - regulator-always-on; - regulator-name = "host-pwr"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - startup-delay-us = <100000>; - vin-supply = <&vcc_io>; - }; - - vcc_otg: usb-otg-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; - pinctrl-0 = <&otg_drv>; - pinctrl-names = "default"; - regulator-always-on; - regulator-name = "vcc_otg"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - startup-delay-us = <100000>; - vin-supply = <&vcc_io>; - }; - - vcc_sd: sdmmc-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&sdmmc_pwr>; - pinctrl-names = "default"; - regulator-name = "vcc_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <100000>; - vin-supply = <&vcc_io>; - }; - - vcc_wifi: sdio-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio3 RK_PD0 GPIO_ACTIVE_HIGH>; - pinctrl-0 = <&wifi_pwr>; - pinctrl-names = "default"; - regulator-name = "vcc_wifi"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <100000>; - vin-supply = <&vcc_io>; - }; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_in_vop1 { - status = "disabled"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&mmc0 { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - vmmc-supply = <&vcc_sd>; - status = "okay"; -}; - -&mmc1 { - bus-width = <4>; - non-removable; - pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_bus4>; - pinctrl-names = "default"; - vmmc-supply = <&vcc_wifi>; - status = "okay"; -}; - -&pinctrl { - usb-host { - host_drv: host-drv { - rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_default>; - }; - }; - - usb-otg { - otg_drv: otg-drv { - rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_default>; - }; - }; - - sdmmc { - sdmmc_pwr: sdmmc-pwr { - rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_default>; - }; - }; - - sdio { - wifi_pwr: wifi-pwr { - rockchip,pins = <3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&uart2 { - status = "okay"; -}; - -&usb_host { - status = "okay"; -}; - -&usb_otg { - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; - -&vop0 { - status = "okay"; -}; - -&wdt { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/rk3066a-rayeager.dts b/sys/gnu/dts/arm/rk3066a-rayeager.dts deleted file mode 100644 index f9db6bb9fa1..00000000000 --- a/sys/gnu/dts/arm/rk3066a-rayeager.dts +++ /dev/null @@ -1,447 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2014, 2015 FUKAUMI Naoki - */ - -/dts-v1/; -#include -#include "rk3066a.dtsi" - -/ { - model = "Rayeager PX2"; - compatible = "chipspark,rayeager-px2", "rockchip,rk3066a"; - - memory@60000000 { - device_type = "memory"; - reg = <0x60000000 0x40000000>; - }; - - ir: ir-receiver { - compatible = "gpio-ir-receiver"; - gpios = <&gpio6 RK_PA1 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&ir_int>; - }; - - keys: gpio-keys { - compatible = "gpio-keys"; - - power { - wakeup-source; - gpios = <&gpio6 RK_PA2 GPIO_ACTIVE_LOW>; - label = "GPIO Power"; - linux,code = ; - pinctrl-names = "default"; - pinctrl-0 = <&pwr_key>; - }; - }; - - vdd_log: vdd-log { - compatible = "pwm-regulator"; - pwms = <&pwm3 0 1000>; - regulator-name = "vdd_log"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - voltage-table = <1000000 100>, - <1200000 42>; - status = "okay"; - }; - - vsys: vsys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vsys"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - /* input for 5V_STDBY is VSYS or DC5V, selectable by jumper J4 */ - vcc_stdby: 5v-stdby-regulator { - compatible = "regulator-fixed"; - regulator-name = "5v_stdby"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - vcc_emmc: emmc-regulator { - compatible = "regulator-fixed"; - regulator-name = "emmc_vccq"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - vin-supply = <&vsys>; - }; - - vcc_sata: sata-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&sata_pwr>; - regulator-name = "usb_5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - vin-supply = <&vcc_stdby>; - }; - - vcc_sd: sdmmc-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_pwr>; - regulator-name = "vcc_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <100000>; - vin-supply = <&vcc_io>; - }; - - vcc_host: usb-host-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&host_drv>; - regulator-name = "host-pwr"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - vin-supply = <&vcc_stdby>; - }; - - vcc_otg: usb-otg-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&otg_drv>; - regulator-name = "vcc_otg"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - vin-supply = <&vcc_stdby>; - }; -}; - -&cpu0 { - cpu0-supply = <&vdd_arm>; -}; - -&emac { - pinctrl-names = "default"; - pinctrl-0 = <&emac_xfer>, <&emac_mdio>, <&rmii_rst>; - phy = <&phy0>; - phy-supply = <&vcc_rmii>; - status = "okay"; - - phy0: ethernet-phy@0 { - reg = <0>; - reset-gpios = <&gpio1 RK_PD6 GPIO_ACTIVE_LOW>; - }; -}; - -&emmc { - bus-width = <8>; - cap-mmc-highspeed; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_rst>; - vmmc-supply = <&vcc_emmc>; - vqmmc-supply = <&vcc_emmc>; - status = "okay"; -}; - -&i2c0 { - clock-frequency = <400000>; - status = "okay"; - - ak8963: ak8963@d { - compatible = "asahi-kasei,ak8975"; - reg = <0x0d>; - interrupt-parent = <&gpio4>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&comp_int>; - }; - - mma8452: mma8452@1d { - compatible = "fsl,mma8452"; - reg = <0x1d>; - interrupt-parent = <&gpio4>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&gsensor_int>; - }; -}; - -&i2c1 { - clock-frequency = <400000>; - status = "okay"; - - tps: tps@2d { - reg = <0x2d>; - interrupt-parent = <&gpio6>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int>, <&pwr_hold>; - - vcc1-supply = <&vsys>; - vcc2-supply = <&vsys>; - vcc3-supply = <&vsys>; - vcc4-supply = <&vsys>; - vcc5-supply = <&vcc_io>; - vcc6-supply = <&vcc_io>; - vcc7-supply = <&vsys>; - vccio-supply = <&vsys>; - - regulators { - vcc_rtc: regulator@0 { - regulator-name = "vcc_rtc"; - regulator-always-on; - }; - - vcc_io: regulator@1 { - regulator-name = "vcc_io"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_arm: regulator@2 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - }; - - vcc_ddr: regulator@3 { - regulator-name = "vcc_ddr"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - }; - - vcc18: regulator@5 { - regulator-name = "vcc18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vdd_11: regulator@6 { - regulator-name = "vdd_11"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - vcc_25: regulator@7 { - regulator-name = "vcc_25"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - vccio_wl: regulator@8 { - regulator-name = "vccio_wl"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vcc25_hdmi: regulator@9 { - regulator-name = "vcc25_hdmi"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - }; - - vcca_33: regulator@10 { - regulator-name = "vcca_33"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vcc_rmii: regulator@11 { - regulator-name = "vcc_rmii"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vcc28_cif: regulator@12 { - regulator-name = "vcc28_cif"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - }; - }; -}; - -#include "tps65910.dtsi" - -&i2c2 { - status = "okay"; -}; - -&i2c3 { - status = "okay"; -}; - -&i2c4 { - status = "okay"; -}; - -&mmc0 { - bus-width = <4>; - disable-wp; - pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>; - vmmc-supply = <&vcc_sd>; - cap-mmc-highspeed; - cap-sd-highspeed; - status = "okay"; -}; - -&mmc1 { - bus-width = <4>; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&sd1_clk>, <&sd1_cmd>, <&sd1_bus4>; - vmmc-supply = <&vccio_wl>; - status = "okay"; -}; - -&pinctrl { - pcfg_output_high: pcfg-output-high { - output-high; - }; - - ak8963 { - comp_int: comp-int { - rockchip,pins = <4 RK_PC1 RK_FUNC_GPIO &pcfg_pull_default>; - }; - }; - - emac { - rmii_rst: rmii-rst { - rockchip,pins = <1 RK_PD6 RK_FUNC_GPIO &pcfg_output_high>; - }; - }; - - ir { - ir_int: ir-int { - rockchip,pins = <6 RK_PA1 RK_FUNC_GPIO &pcfg_pull_default>; - }; - }; - - keys { - pwr_key: pwr-key { - rockchip,pins = <6 RK_PA2 RK_FUNC_GPIO &pcfg_pull_default>; - }; - }; - - mma8452 { - gsensor_int: gsensor-int { - rockchip,pins = <4 RK_PC0 RK_FUNC_GPIO &pcfg_pull_default>; - }; - }; - - mmc { - sdmmc_pwr: sdmmc-pwr { - rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_default>; - }; - }; - - usb_host { - host_drv: host-drv { - rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_default>; - }; - - hub_rst: hub-rst { - rockchip,pins = <1 RK_PD7 RK_FUNC_GPIO &pcfg_output_high>; - }; - - sata_pwr: sata-pwr { - rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_default>; - }; - - sata_reset: sata-reset { - rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_output_high>; - }; - }; - - usb_otg { - otg_drv: otg-drv { - rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_default>; - }; - }; - - tps { - pmic_int: pmic-int { - rockchip,pins = <6 RK_PA4 RK_FUNC_GPIO &pcfg_pull_default>; - }; - - pwr_hold: pwr-hold { - rockchip,pins = <6 RK_PB0 RK_FUNC_GPIO &pcfg_output_high>; - }; - }; -}; - -&pwm1 { - status = "okay"; -}; - -&pwm2 { - status = "okay"; -}; - -&pwm3 { - status = "okay"; -}; - -&saradc { - vref-supply = <&vcc_25>; - status = "okay"; -}; - -&spi0 { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer>, <&uart0_cts>, <&uart0_rts>; - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_xfer>, <&uart3_cts>, <&uart3_rts>; - status = "okay"; -}; - -&usb_host { - pinctrl-names = "default"; - pinctrl-0 = <&hub_rst>, <&sata_reset>; - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; - -&usb_otg { - status = "okay"; -}; - -&wdt { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/rk3066a.dtsi b/sys/gnu/dts/arm/rk3066a.dtsi deleted file mode 100644 index 3d1b02f45ff..00000000000 --- a/sys/gnu/dts/arm/rk3066a.dtsi +++ /dev/null @@ -1,876 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2013 MundoReader S.L. - * Author: Heiko Stuebner - */ - -#include -#include -#include -#include -#include "rk3xxx.dtsi" - -/ { - compatible = "rockchip,rk3066a"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "rockchip,rk3066-smp"; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - next-level-cache = <&L2>; - reg = <0x0>; - operating-points = < - /* kHz uV */ - 1416000 1300000 - 1200000 1175000 - 1008000 1125000 - 816000 1125000 - 600000 1100000 - 504000 1100000 - 312000 1075000 - >; - clock-latency = <40000>; - clocks = <&cru ARMCLK>; - }; - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - next-level-cache = <&L2>; - reg = <0x1>; - }; - }; - - display-subsystem { - compatible = "rockchip,display-subsystem"; - ports = <&vop0_out>, <&vop1_out>; - }; - - sram: sram@10080000 { - compatible = "mmio-sram"; - reg = <0x10080000 0x10000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x10080000 0x10000>; - - smp-sram@0 { - compatible = "rockchip,rk3066-smp-sram"; - reg = <0x0 0x50>; - }; - }; - - vop0: vop@1010c000 { - compatible = "rockchip,rk3066-vop"; - reg = <0x1010c000 0x19c>; - interrupts = ; - clocks = <&cru ACLK_LCDC0>, - <&cru DCLK_LCDC0>, - <&cru HCLK_LCDC0>; - clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; - power-domains = <&power RK3066_PD_VIO>; - resets = <&cru SRST_LCDC0_AXI>, - <&cru SRST_LCDC0_AHB>, - <&cru SRST_LCDC0_DCLK>; - reset-names = "axi", "ahb", "dclk"; - status = "disabled"; - - vop0_out: port { - #address-cells = <1>; - #size-cells = <0>; - - vop0_out_hdmi: endpoint@0 { - reg = <0>; - remote-endpoint = <&hdmi_in_vop0>; - }; - }; - }; - - vop1: vop@1010e000 { - compatible = "rockchip,rk3066-vop"; - reg = <0x1010e000 0x19c>; - interrupts = ; - clocks = <&cru ACLK_LCDC1>, - <&cru DCLK_LCDC1>, - <&cru HCLK_LCDC1>; - clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; - power-domains = <&power RK3066_PD_VIO>; - resets = <&cru SRST_LCDC1_AXI>, - <&cru SRST_LCDC1_AHB>, - <&cru SRST_LCDC1_DCLK>; - reset-names = "axi", "ahb", "dclk"; - status = "disabled"; - - vop1_out: port { - #address-cells = <1>; - #size-cells = <0>; - - vop1_out_hdmi: endpoint@0 { - reg = <0>; - remote-endpoint = <&hdmi_in_vop1>; - }; - }; - }; - - hdmi: hdmi@10116000 { - compatible = "rockchip,rk3066-hdmi"; - reg = <0x10116000 0x2000>; - interrupts = ; - clocks = <&cru HCLK_HDMI>; - clock-names = "hclk"; - pinctrl-names = "default"; - pinctrl-0 = <&hdmii2c_xfer>, <&hdmi_hpd>; - power-domains = <&power RK3066_PD_VIO>; - rockchip,grf = <&grf>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - hdmi_in: port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - hdmi_in_vop0: endpoint@0 { - reg = <0>; - remote-endpoint = <&vop0_out_hdmi>; - }; - - hdmi_in_vop1: endpoint@1 { - reg = <1>; - remote-endpoint = <&vop1_out_hdmi>; - }; - }; - - hdmi_out: port@1 { - reg = <1>; - }; - }; - }; - - i2s0: i2s@10118000 { - compatible = "rockchip,rk3066-i2s"; - reg = <0x10118000 0x2000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_bus>; - dmas = <&dmac1_s 4>, <&dmac1_s 5>; - dma-names = "tx", "rx"; - clock-names = "i2s_hclk", "i2s_clk"; - clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>; - rockchip,playback-channels = <8>; - rockchip,capture-channels = <2>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - i2s1: i2s@1011a000 { - compatible = "rockchip,rk3066-i2s"; - reg = <0x1011a000 0x2000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s1_bus>; - dmas = <&dmac1_s 6>, <&dmac1_s 7>; - dma-names = "tx", "rx"; - clock-names = "i2s_hclk", "i2s_clk"; - clocks = <&cru HCLK_I2S1>, <&cru SCLK_I2S1>; - rockchip,playback-channels = <2>; - rockchip,capture-channels = <2>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - i2s2: i2s@1011c000 { - compatible = "rockchip,rk3066-i2s"; - reg = <0x1011c000 0x2000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s2_bus>; - dmas = <&dmac1_s 9>, <&dmac1_s 10>; - dma-names = "tx", "rx"; - clock-names = "i2s_hclk", "i2s_clk"; - clocks = <&cru HCLK_I2S2>, <&cru SCLK_I2S2>; - rockchip,playback-channels = <2>; - rockchip,capture-channels = <2>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - cru: clock-controller@20000000 { - compatible = "rockchip,rk3066a-cru"; - reg = <0x20000000 0x1000>; - rockchip,grf = <&grf>; - - #clock-cells = <1>; - #reset-cells = <1>; - assigned-clocks = <&cru PLL_CPLL>, <&cru PLL_GPLL>, - <&cru ACLK_CPU>, <&cru HCLK_CPU>, - <&cru PCLK_CPU>, <&cru ACLK_PERI>, - <&cru HCLK_PERI>, <&cru PCLK_PERI>; - assigned-clock-rates = <400000000>, <594000000>, - <300000000>, <150000000>, - <75000000>, <300000000>, - <150000000>, <75000000>; - }; - - timer@2000e000 { - compatible = "snps,dw-apb-timer-osc"; - reg = <0x2000e000 0x100>; - interrupts = ; - clocks = <&cru SCLK_TIMER2>, <&cru PCLK_TIMER2>; - clock-names = "timer", "pclk"; - }; - - efuse: efuse@20010000 { - compatible = "rockchip,rk3066a-efuse"; - reg = <0x20010000 0x4000>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&cru PCLK_EFUSE>; - clock-names = "pclk_efuse"; - - cpu_leakage: cpu_leakage@17 { - reg = <0x17 0x1>; - }; - }; - - timer@20038000 { - compatible = "snps,dw-apb-timer-osc"; - reg = <0x20038000 0x100>; - interrupts = ; - clocks = <&cru SCLK_TIMER0>, <&cru PCLK_TIMER0>; - clock-names = "timer", "pclk"; - }; - - timer@2003a000 { - compatible = "snps,dw-apb-timer-osc"; - reg = <0x2003a000 0x100>; - interrupts = ; - clocks = <&cru SCLK_TIMER1>, <&cru PCLK_TIMER1>; - clock-names = "timer", "pclk"; - }; - - tsadc: tsadc@20060000 { - compatible = "rockchip,rk3066-tsadc"; - reg = <0x20060000 0x100>; - clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; - clock-names = "saradc", "apb_pclk"; - interrupts = ; - #io-channel-cells = <1>; - resets = <&cru SRST_TSADC>; - reset-names = "saradc-apb"; - status = "disabled"; - }; - - usbphy: phy { - compatible = "rockchip,rk3066a-usb-phy", "rockchip,rk3288-usb-phy"; - rockchip,grf = <&grf>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - usbphy0: usb-phy@17c { - #phy-cells = <0>; - reg = <0x17c>; - clocks = <&cru SCLK_OTGPHY0>; - clock-names = "phyclk"; - #clock-cells = <0>; - }; - - usbphy1: usb-phy@188 { - #phy-cells = <0>; - reg = <0x188>; - clocks = <&cru SCLK_OTGPHY1>; - clock-names = "phyclk"; - #clock-cells = <0>; - }; - }; - - pinctrl: pinctrl { - compatible = "rockchip,rk3066a-pinctrl"; - rockchip,grf = <&grf>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gpio0: gpio0@20034000 { - compatible = "rockchip,gpio-bank"; - reg = <0x20034000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO0>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio1@2003c000 { - compatible = "rockchip,gpio-bank"; - reg = <0x2003c000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO1>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio2@2003e000 { - compatible = "rockchip,gpio-bank"; - reg = <0x2003e000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO2>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio3@20080000 { - compatible = "rockchip,gpio-bank"; - reg = <0x20080000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO3>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio4: gpio4@20084000 { - compatible = "rockchip,gpio-bank"; - reg = <0x20084000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO4>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio6: gpio6@2000a000 { - compatible = "rockchip,gpio-bank"; - reg = <0x2000a000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO6>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - pcfg_pull_default: pcfg_pull_default { - bias-pull-pin-default; - }; - - pcfg_pull_none: pcfg_pull_none { - bias-disable; - }; - - emac { - emac_xfer: emac-xfer { - rockchip,pins = <1 RK_PC0 2 &pcfg_pull_none>, /* mac_clk */ - <1 RK_PC1 2 &pcfg_pull_none>, /* tx_en */ - <1 RK_PC2 2 &pcfg_pull_none>, /* txd1 */ - <1 RK_PC3 2 &pcfg_pull_none>, /* txd0 */ - <1 RK_PC4 2 &pcfg_pull_none>, /* rx_err */ - <1 RK_PC5 2 &pcfg_pull_none>, /* crs_dvalid */ - <1 RK_PC6 2 &pcfg_pull_none>, /* rxd1 */ - <1 RK_PC7 2 &pcfg_pull_none>; /* rxd0 */ - }; - - emac_mdio: emac-mdio { - rockchip,pins = <1 RK_PD0 2 &pcfg_pull_none>, /* mac_md */ - <1 RK_PD1 2 &pcfg_pull_none>; /* mac_mdclk */ - }; - }; - - emmc { - emmc_clk: emmc-clk { - rockchip,pins = <3 RK_PD7 2 &pcfg_pull_default>; - }; - - emmc_cmd: emmc-cmd { - rockchip,pins = <4 RK_PB1 2 &pcfg_pull_default>; - }; - - emmc_rst: emmc-rst { - rockchip,pins = <4 RK_PB2 2 &pcfg_pull_default>; - }; - - /* - * The data pins are shared between nandc and emmc and - * not accessible through pinctrl. Also they should've - * been already set correctly by firmware, as - * flash/emmc is the boot-device. - */ - }; - - hdmi { - hdmi_hpd: hdmi-hpd { - rockchip,pins = <0 RK_PA0 1 &pcfg_pull_default>; - }; - - hdmii2c_xfer: hdmii2c-xfer { - rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>, - <0 RK_PA2 1 &pcfg_pull_none>; - }; - }; - - i2c0 { - i2c0_xfer: i2c0-xfer { - rockchip,pins = <2 RK_PD4 1 &pcfg_pull_none>, - <2 RK_PD5 1 &pcfg_pull_none>; - }; - }; - - i2c1 { - i2c1_xfer: i2c1-xfer { - rockchip,pins = <2 RK_PD6 1 &pcfg_pull_none>, - <2 RK_PD7 1 &pcfg_pull_none>; - }; - }; - - i2c2 { - i2c2_xfer: i2c2-xfer { - rockchip,pins = <3 RK_PA0 1 &pcfg_pull_none>, - <3 RK_PA1 1 &pcfg_pull_none>; - }; - }; - - i2c3 { - i2c3_xfer: i2c3-xfer { - rockchip,pins = <3 RK_PA2 2 &pcfg_pull_none>, - <3 RK_PA3 2 &pcfg_pull_none>; - }; - }; - - i2c4 { - i2c4_xfer: i2c4-xfer { - rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>, - <3 RK_PA5 1 &pcfg_pull_none>; - }; - }; - - pwm0 { - pwm0_out: pwm0-out { - rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>; - }; - }; - - pwm1 { - pwm1_out: pwm1-out { - rockchip,pins = <0 RK_PA4 1 &pcfg_pull_none>; - }; - }; - - pwm2 { - pwm2_out: pwm2-out { - rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>; - }; - }; - - pwm3 { - pwm3_out: pwm3-out { - rockchip,pins = <0 RK_PD7 1 &pcfg_pull_none>; - }; - }; - - spi0 { - spi0_clk: spi0-clk { - rockchip,pins = <1 RK_PA5 2 &pcfg_pull_default>; - }; - spi0_cs0: spi0-cs0 { - rockchip,pins = <1 RK_PA4 2 &pcfg_pull_default>; - }; - spi0_tx: spi0-tx { - rockchip,pins = <1 RK_PA7 2 &pcfg_pull_default>; - }; - spi0_rx: spi0-rx { - rockchip,pins = <1 RK_PA6 2 &pcfg_pull_default>; - }; - spi0_cs1: spi0-cs1 { - rockchip,pins = <4 RK_PB7 1 &pcfg_pull_default>; - }; - }; - - spi1 { - spi1_clk: spi1-clk { - rockchip,pins = <2 RK_PC3 2 &pcfg_pull_default>; - }; - spi1_cs0: spi1-cs0 { - rockchip,pins = <2 RK_PC4 2 &pcfg_pull_default>; - }; - spi1_rx: spi1-rx { - rockchip,pins = <2 RK_PC6 2 &pcfg_pull_default>; - }; - spi1_tx: spi1-tx { - rockchip,pins = <2 RK_PC5 2 &pcfg_pull_default>; - }; - spi1_cs1: spi1-cs1 { - rockchip,pins = <2 RK_PC7 2 &pcfg_pull_default>; - }; - }; - - uart0 { - uart0_xfer: uart0-xfer { - rockchip,pins = <1 RK_PA0 1 &pcfg_pull_default>, - <1 RK_PA1 1 &pcfg_pull_default>; - }; - - uart0_cts: uart0-cts { - rockchip,pins = <1 RK_PA2 1 &pcfg_pull_default>; - }; - - uart0_rts: uart0-rts { - rockchip,pins = <1 RK_PA3 1 &pcfg_pull_default>; - }; - }; - - uart1 { - uart1_xfer: uart1-xfer { - rockchip,pins = <1 RK_PA4 1 &pcfg_pull_default>, - <1 RK_PA5 1 &pcfg_pull_default>; - }; - - uart1_cts: uart1-cts { - rockchip,pins = <1 RK_PA6 1 &pcfg_pull_default>; - }; - - uart1_rts: uart1-rts { - rockchip,pins = <1 RK_PA7 1 &pcfg_pull_default>; - }; - }; - - uart2 { - uart2_xfer: uart2-xfer { - rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>, - <1 RK_PB1 1 &pcfg_pull_default>; - }; - /* no rts / cts for uart2 */ - }; - - uart3 { - uart3_xfer: uart3-xfer { - rockchip,pins = <3 RK_PD3 1 &pcfg_pull_default>, - <3 RK_PD4 1 &pcfg_pull_default>; - }; - - uart3_cts: uart3-cts { - rockchip,pins = <3 RK_PD5 1 &pcfg_pull_default>; - }; - - uart3_rts: uart3-rts { - rockchip,pins = <3 RK_PD6 1 &pcfg_pull_default>; - }; - }; - - sd0 { - sd0_clk: sd0-clk { - rockchip,pins = <3 RK_PB0 1 &pcfg_pull_default>; - }; - - sd0_cmd: sd0-cmd { - rockchip,pins = <3 RK_PB1 1 &pcfg_pull_default>; - }; - - sd0_cd: sd0-cd { - rockchip,pins = <3 RK_PB6 1 &pcfg_pull_default>; - }; - - sd0_wp: sd0-wp { - rockchip,pins = <3 RK_PB7 1 &pcfg_pull_default>; - }; - - sd0_bus1: sd0-bus-width1 { - rockchip,pins = <3 RK_PB2 1 &pcfg_pull_default>; - }; - - sd0_bus4: sd0-bus-width4 { - rockchip,pins = <3 RK_PB2 1 &pcfg_pull_default>, - <3 RK_PB3 1 &pcfg_pull_default>, - <3 RK_PB4 1 &pcfg_pull_default>, - <3 RK_PB5 1 &pcfg_pull_default>; - }; - }; - - sd1 { - sd1_clk: sd1-clk { - rockchip,pins = <3 RK_PC5 1 &pcfg_pull_default>; - }; - - sd1_cmd: sd1-cmd { - rockchip,pins = <3 RK_PC0 1 &pcfg_pull_default>; - }; - - sd1_cd: sd1-cd { - rockchip,pins = <3 RK_PC6 1 &pcfg_pull_default>; - }; - - sd1_wp: sd1-wp { - rockchip,pins = <3 RK_PC7 1 &pcfg_pull_default>; - }; - - sd1_bus1: sd1-bus-width1 { - rockchip,pins = <3 RK_PC1 1 &pcfg_pull_default>; - }; - - sd1_bus4: sd1-bus-width4 { - rockchip,pins = <3 RK_PC1 1 &pcfg_pull_default>, - <3 RK_PC2 1 &pcfg_pull_default>, - <3 RK_PC3 1 &pcfg_pull_default>, - <3 RK_PC4 1 &pcfg_pull_default>; - }; - }; - - i2s0 { - i2s0_bus: i2s0-bus { - rockchip,pins = <0 RK_PA7 1 &pcfg_pull_default>, - <0 RK_PB0 1 &pcfg_pull_default>, - <0 RK_PB1 1 &pcfg_pull_default>, - <0 RK_PB2 1 &pcfg_pull_default>, - <0 RK_PB3 1 &pcfg_pull_default>, - <0 RK_PB4 1 &pcfg_pull_default>, - <0 RK_PB5 1 &pcfg_pull_default>, - <0 RK_PB6 1 &pcfg_pull_default>, - <0 RK_PB7 1 &pcfg_pull_default>; - }; - }; - - i2s1 { - i2s1_bus: i2s1-bus { - rockchip,pins = <0 RK_PC0 1 &pcfg_pull_default>, - <0 RK_PC1 1 &pcfg_pull_default>, - <0 RK_PC2 1 &pcfg_pull_default>, - <0 RK_PC3 1 &pcfg_pull_default>, - <0 RK_PC4 1 &pcfg_pull_default>, - <0 RK_PC5 1 &pcfg_pull_default>; - }; - }; - - i2s2 { - i2s2_bus: i2s2-bus { - rockchip,pins = <0 RK_PD0 1 &pcfg_pull_default>, - <0 RK_PD1 1 &pcfg_pull_default>, - <0 RK_PD2 1 &pcfg_pull_default>, - <0 RK_PD3 1 &pcfg_pull_default>, - <0 RK_PD4 1 &pcfg_pull_default>, - <0 RK_PD5 1 &pcfg_pull_default>; - }; - }; - }; -}; - -&gpu { - compatible = "rockchip,rk3066-mali", "arm,mali-400"; - interrupts = , - , - , - , - , - , - , - , - , - ; - interrupt-names = "gp", - "gpmmu", - "pp0", - "ppmmu0", - "pp1", - "ppmmu1", - "pp2", - "ppmmu2", - "pp3", - "ppmmu3"; - power-domains = <&power RK3066_PD_GPU>; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_xfer>; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_xfer>; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_xfer>; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_xfer>; -}; - -&i2c4 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_xfer>; -}; - -&mmc0 { - clock-frequency = <50000000>; - dmas = <&dmac2 1>; - dma-names = "rx-tx"; - max-frequency = <50000000>; - pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4>; -}; - -&mmc1 { - dmas = <&dmac2 3>; - dma-names = "rx-tx"; - pinctrl-names = "default"; - pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus4>; -}; - -&emmc { - dmas = <&dmac2 4>; - dma-names = "rx-tx"; -}; - -&pmu { - power: power-controller { - compatible = "rockchip,rk3066-power-controller"; - #power-domain-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - - pd_vio@RK3066_PD_VIO { - reg = ; - clocks = <&cru ACLK_LCDC0>, - <&cru ACLK_LCDC1>, - <&cru DCLK_LCDC0>, - <&cru DCLK_LCDC1>, - <&cru HCLK_LCDC0>, - <&cru HCLK_LCDC1>, - <&cru SCLK_CIF1>, - <&cru ACLK_CIF1>, - <&cru HCLK_CIF1>, - <&cru SCLK_CIF0>, - <&cru ACLK_CIF0>, - <&cru HCLK_CIF0>, - <&cru HCLK_HDMI>, - <&cru ACLK_IPP>, - <&cru HCLK_IPP>, - <&cru ACLK_RGA>, - <&cru HCLK_RGA>; - pm_qos = <&qos_lcdc0>, - <&qos_lcdc1>, - <&qos_cif0>, - <&qos_cif1>, - <&qos_ipp>, - <&qos_rga>; - }; - - pd_video@RK3066_PD_VIDEO { - reg = ; - clocks = <&cru ACLK_VDPU>, - <&cru ACLK_VEPU>, - <&cru HCLK_VDPU>, - <&cru HCLK_VEPU>; - pm_qos = <&qos_vpu>; - }; - - pd_gpu@RK3066_PD_GPU { - reg = ; - clocks = <&cru ACLK_GPU>; - pm_qos = <&qos_gpu>; - }; - }; -}; - -&pwm0 { - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_out>; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pwm1_out>; -}; - -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pwm2_out>; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pwm3_out>; -}; - -&spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; -}; - -&spi1 { - pinctrl-names = "default"; - pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; -}; - -&uart0 { - compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart"; - dmas = <&dmac1_s 0>, <&dmac1_s 1>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer>; -}; - -&uart1 { - compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart"; - dmas = <&dmac1_s 2>, <&dmac1_s 3>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&uart1_xfer>; -}; - -&uart2 { - compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart"; - dmas = <&dmac2 6>, <&dmac2 7>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&uart2_xfer>; -}; - -&uart3 { - compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart"; - dmas = <&dmac2 8>, <&dmac2 9>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&uart3_xfer>; -}; - -&wdt { - compatible = "rockchip,rk3066-wdt", "snps,dw-wdt"; -}; - -&emac { - compatible = "rockchip,rk3066-emac"; -}; diff --git a/sys/gnu/dts/arm/rk3188-bqedison2qc.dts b/sys/gnu/dts/arm/rk3188-bqedison2qc.dts deleted file mode 100644 index ad1afd40305..00000000000 --- a/sys/gnu/dts/arm/rk3188-bqedison2qc.dts +++ /dev/null @@ -1,727 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2018 MundoReader S.L. - * Author: Heiko Stuebner - */ - -/dts-v1/; -#include -#include -#include "rk3188.dtsi" - -/ { - model = "BQ Edison2 Quad-Core"; - compatible = "mundoreader,bq-edison2qc", "rockchip,rk3188"; - - memory@60000000 { - device_type = "memory"; - reg = <0x60000000 0x80000000>; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - power-supply = <&vsys>; - pwms = <&pwm1 0 25000>; - }; - - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - pinctrl-names = "default"; - pinctrl-0 = <&pwr_key &usb_int>; - - power { - gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "GPIO Key Power"; - linux,input-type = <1>; - debounce-interval = <100>; - wakeup-source; - }; - - wake_on_usb: wake-on-usb { - label = "Wake-on-USB"; - gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - }; - - gpio-poweroff { - compatible = "gpio-poweroff"; - gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pwr_hold>; - /* only drive the pin low until device is off */ - active-delay-ms = <3000>; - }; - - lvds-encoder { - compatible = "ti,sn75lvds83", "lvds-encoder"; - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - lvds_in_vop0: endpoint { - remote-endpoint = <&vop0_out_lvds>; - }; - }; - - port@1 { - reg = <1>; - lvds_out_panel: endpoint { - remote-endpoint = <&panel_in_lvds>; - }; - }; - }; - - panel { - compatible = "innolux,ee101ia-01d", "panel-lvds"; - backlight = <&backlight>; - - /* pin LCD_CS, Nshtdn input of lvds-encoder */ - enable-gpios = <&gpio3 RK_PD6 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&lcd_cs>; - power-supply = <&vcc_lcd>; - - data-mapping = "vesa-24"; - height-mm = <163>; - width-mm = <261>; - - panel-timing { - clock-frequency = <72000000>; - hactive = <1280>; - vactive = <800>; - hback-porch = <160>; - hfront-porch = <16>; - hsync-len = <10>; - vback-porch = <23>; - vfront-porch = <12>; - vsync-len = <3>; - }; - - port { - panel_in_lvds: endpoint { - remote-endpoint = <&lvds_out_panel>; - }; - }; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&hym8563>; - clock-names = "ext_clock"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_reg_on>; - reset-gpios = <&gpio3 RK_PD0 GPIO_ACTIVE_LOW>; - }; - - avdd_cif: cif-avdd-regulator { - compatible = "regulator-fixed"; - regulator-name = "avdd-cif"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpio1 RK_PA6 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&cif_avdd_en>; - startup-delay-us = <100000>; - vin-supply = <&vcc28_cif>; - }; - - vcc_5v: vcc-5v-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc-5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&v5_drv>; - vin-supply = <&vsys>; - }; - - vcc_lcd: lcd-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc-lcd"; - gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&lcd_en>; - startup-delay-us = <50000>; - vin-supply = <&vcc_io>; - }; - - vcc_otg: usb-otg-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc-otg"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio3 RK_PB1 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&otg_drv>; - startup-delay-us = <100000>; - vin-supply = <&vcc_5v>; - }; - - vcc_sd: sdmmc-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc-sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_pwr>; - startup-delay-us = <100000>; - vin-supply = <&vcc_io>; - }; - - vccq_emmc: emmc-vccq-regulator { - compatible = "regulator-fixed"; - regulator-name = "vccq-emmc"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - vin-supply = <&vcc_io>; - }; - - /* supplied from the bq24196 */ - vsys: vsys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vsys"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - }; -}; - -&cpu0 { - cpu-supply = <&vdd_arm>; -}; - -&cpu1 { - cpu-supply = <&vdd_arm>; -}; - -&cpu2 { - cpu-supply = <&vdd_arm>; -}; - -&cpu3 { - cpu-supply = <&vdd_arm>; -}; - -&cru { - assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>, - <&cru ACLK_CPU>, - <&cru HCLK_CPU>, <&cru PCLK_CPU>, - <&cru ACLK_PERI>, <&cru HCLK_PERI>, - <&cru PCLK_PERI>; - assigned-clock-rates = <594000000>, <504000000>, - <300000000>, - <150000000>, <75000000>, - <300000000>, <150000000>, - <75000000>; -}; - -&emmc { - bus-width = <8>; - cap-mmc-highspeed; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk &emmc_cmd>; - vmmc-supply = <&vcc_io>; - vqmmc-supply = <&vccq_emmc>; - status = "okay"; -}; - -&gpu { - status = "okay"; -}; - -&i2c0 { - clock-frequency = <400000>; - status = "okay"; - - lis3de: accelerometer@29 { - compatible = "st,lis3de"; - reg = <0x29>; - interrupt-parent = <&gpio0>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&gsensor_int>; - rotation-matrix = "1", "0", "0", - "0", "-1", "0", - "0", "0", "1"; - vdd-supply = <&vcc_io>; - }; -}; - -&i2c1 { - clock-frequency = <400000>; - status = "okay"; - - tmp108@48 { - compatible = "ti,tmp108"; - reg = <0x48>; - interrupt-parent = <&gpio1>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&tmp_alrt>; - #thermal-sensor-cells = <0>; - }; - - hym8563: rtc@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - interrupt-parent = <&gpio0>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&rtc_int>; - #clock-cells = <0>; - clock-output-names = "xin32k"; - }; - - bat: battery@55 { - compatible = "ti,bq27541"; - reg = <0x55>; - power-supplies = <&bq24196>; - }; - - act8846: pmic@5a { - compatible = "active-semi,act8846"; - reg = <0x5a>; - pinctrl-names = "default"; - pinctrl-0 = <&dvs0_ctl &pmic_int>; - - vp1-supply = <&vsys>; - vp2-supply = <&vsys>; - vp3-supply = <&vsys>; - vp4-supply = <&vsys>; - inl1-supply = <&vcc_io>; - inl2-supply = <&vsys>; - inl3-supply = <&vsys>; - - regulators { - vcc_ddr: REG1 { - regulator-name = "VCC_DDR"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - vdd_log: REG2 { - regulator-name = "VDD_LOG"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - vdd_arm: REG3 { - regulator-name = "VDD_ARM"; - regulator-min-microvolt = <875000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - }; - - vcc_io: vcc_hdmi: REG4 { - regulator-name = "VCC_IO"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - }; - - vdd_10: REG5 { - regulator-name = "VDD_10"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - vdd_12: REG6 { - regulator-name = "VDD_12"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - vcc18_cif: REG7 { - regulator-name = "VCC18_CIF"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vcca_33: REG8 { - regulator-name = "VCCA_33"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vcc_tp: REG9 { - regulator-name = "VCC_TP"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vccio_wl: REG10 { - regulator-name = "VCCIO_WL"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - vcc_18: REG11 { - regulator-name = "VCC_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vcc28_cif: REG12 { - regulator-name = "VCC28_CIF"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - }; - }; - - bq24196: charger@6b { - compatible = "ti,bq24196"; - reg = <0x6b>; - interrupt-parent = <&gpio0>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&charger_int &chg_ctl &otg_en>; - ti,system-minimum-microvolt = <3200000>; - monitored-battery = <&bat>; - omit-battery-class; - - usb_otg_vbus: usb-otg-vbus { }; - }; -}; - -&i2c2 { - clock-frequency = <400000>; - status = "okay"; - - ft5606: touchscreen@3e { - compatible = "edt,edt-ft5506"; - reg = <0x3e>; - interrupt-parent = <&gpio1>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&tp_int &tp_rst>; - reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>; - touchscreen-inverted-y; - /* hw ts resolution does not match display */ - touchscreen-size-y = <1024>; - touchscreen-size-x = <768>; - touchscreen-swapped-x-y; - }; -}; - -&i2c3 { - clock-frequency = <400000>; - status = "okay"; -}; - -&i2c4 { - clock-frequency = <400000>; - status = "okay"; - - rt5616: codec@1b { - compatible = "realtek,rt5616"; - reg = <0x1b>; - clocks = <&cru SCLK_I2S0>; - clock-names = "mclk"; - #sound-dai-cells = <0>; - }; -}; - -&i2s0 { - status = "okay"; -}; - -&mmc0 { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - disable-wp; - pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>; - vmmc-supply = <&vcc_sd>; - status = "okay"; -}; - -&mmc1 { - bus-width = <4>; - cap-sd-highspeed; - keep-power-in-suspend; - mmc-pwrseq = <&sdio_pwrseq>; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&sd1_clk>, <&sd1_cmd>, <&sd1_bus4>; - vmmcq-supply = <&vccio_wl>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - interrupt-parent = <&gpio3>; - interrupts = ; - interrupt-names = "host-wake"; - brcm,drive-strength = <5>; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_host_wake>; - }; -}; - -&pwm1 { - status = "okay"; -}; - -&pinctrl { - pcfg_output_high: pcfg-output-high { - output-high; - }; - - pcfg_output_low: pcfg-output-low { - output-low; - }; - - act8846 { - dvs0_ctl: dvs0-ctl { - rockchip,pins = <3 RK_PD3 RK_FUNC_GPIO &pcfg_output_low>; - }; - - pmic_int: pmic-int { - rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - bq24196 { - charger_int: charger-int { - rockchip,pins = <0 RK_PD7 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - /* pin hog to make it select usb profile */ - chg_ctl: chg-ctl { - rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_output_high>; - }; - - /* low: charging, high: complete, fault: blinking */ - chg_det: chg-det { - rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - /* charging enabled when pin low and register set */ - chg_en: chg-en { - rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_output_low>; - }; - - /* bq29196 powergood (when low) signal */ - dc_det: dc-det { - rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - /* wire bq24196 otg pin to high, to enable 500mA charging */ - otg_en: otg-en { - rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_output_high>; - }; - }; - - camera { - cif0_pdn: cif0-pdn { - rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - cif1_pdn: cif1-pdn { - rockchip,pins = <3 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - cif_avdd_en: cif-avdd-en { - rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - display { - lcd_cs: lcd-cs { - rockchip,pins = <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - lcd_en: lcd-en { - rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - ft5606 { - tp_int: tp-int { - rockchip,pins = <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - tp_rst: tp-rst { - rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - hdmi { - hdmi_int: hdmi-int { - rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - hdmi_rst: hdmi-rst { - rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - hym8563 { - rtc_int: rtc-int { - rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - keys { - pwr_hold: pwr-hold { - rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - pwr_key: pwr-key { - rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - lis3de { - gsensor_int: gsensor-int { - rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - mmc { - sdmmc_pwr: sdmmc-pwr { - rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - tmp108 { - tmp_alrt: tmp-alrt { - rockchip,pins = <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb { - v5_drv: v5-drv { - rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - otg_drv: otg-drv { - rockchip,pins = <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - usb_int: usb-int { - rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - rk903 { - bt_host_wake: bt-host-wake { - rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - bt_reg_on: bt-reg-on { - rockchip,pins = <3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - /* pin hog to pull the reset high */ - bt_rst: bt-rst { - rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_output_high>; - }; - - bt_wake: bt-wake { - rockchip,pins = <3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - wifi_host_wake: wifi-host-wake { - rockchip,pins = <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - wifi_reg_on: wifi-reg-on { - rockchip,pins = <3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&saradc { - vref-supply = <&vcc_18>; - status = "okay"; -}; - -&spdif { - status = "okay"; -}; - -&uart0 { - pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - max-speed = <2000000>; - device-wakeup-gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>; - host-wakeup-gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; - shutdown-gpios = <&gpio3 RK_PC7 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&bt_host_wake &bt_reg_on &bt_rst &bt_wake>; - }; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>; - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; - -&usb_host { - status = "okay"; -}; - -&usb_otg { - status = "okay"; -}; - -&vop0 { - status = "okay"; -}; - -&vop0_out { - vop0_out_lvds: endpoint { - remote-endpoint = <&lvds_in_vop0>; - }; -}; - -&vop1 { - pinctrl-names = "default"; - pinctrl-0 = <&lcdc1_dclk &lcdc1_den &lcdc1_hsync - &lcdc1_vsync &lcdc1_rgb24>; - status = "okay"; -}; - -&wdt { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/rk3188-px3-evb.dts b/sys/gnu/dts/arm/rk3188-px3-evb.dts deleted file mode 100644 index c32e1d441cf..00000000000 --- a/sys/gnu/dts/arm/rk3188-px3-evb.dts +++ /dev/null @@ -1,300 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Andy Yan - */ - -/dts-v1/; -#include -#include "rk3188.dtsi" - -/ { - model = "Rockchip PX3-EVB"; - compatible = "rockchip,px3-evb", "rockchip,px3", "rockchip,rk3188"; - - chosen { - stdout-path = "serial2:115200n8"; - }; - - memory@60000000 { - reg = <0x60000000 0x80000000>; - device_type = "memory"; - }; - - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - - power { - gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "GPIO Key Power"; - linux,input-type = <1>; - wakeup-source; - debounce-interval = <100>; - }; - }; - - vcc_sys: vsys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vsys"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - }; -}; - -&cpu0 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu1 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu2 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu3 { - cpu-supply = <&vdd_cpu>; -}; - -&emmc { - bus-width = <8>; - cap-mmc-highspeed; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_rst>; - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - accelerometer@18 { - compatible = "bosch,bma250"; - reg = <0x18>; - interrupt-parent = <&gpio0>; - interrupts = ; - }; -}; - -&i2c1 { - status = "okay"; - clock-frequency = <400000>; - - rk808: pmic@1c { - compatible = "rockchip,rk818"; - reg = <0x1c>; - interrupt-parent = <&gpio0>; - interrupts = ; - rockchip,system-power-controller; - wakeup-source; - #clock-cells = <1>; - clock-output-names = "xin32k", "rk808-clkout2"; - - vcc1-supply = <&vcc_sys>; - vcc2-supply = <&vcc_sys>; - vcc3-supply = <&vcc_sys>; - vcc4-supply = <&vcc_sys>; - vcc6-supply = <&vcc_sys>; - vcc7-supply = <&vcc_sys>; - vcc8-supply = <&vcc_io>; - vcc9-supply = <&vcc_io>; - - regulators { - vdd_cpu: DCDC_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-name = "vdd_arm"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_gpu: DCDC_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1250000>; - regulator-name = "vdd_gpu"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc_ddr"; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_io: DCDC_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc_io"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc_cif: LDO_REG1 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc_cif"; - }; - - vcc_jetta33: LDO_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc_jetta33"; - }; - - vdd_10: LDO_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-name = "vdd_10"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - lvds_12: LDO_REG4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "lvds_12"; - }; - - lvds_25: LDO_REG5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-name = "lvds_25"; - }; - - cif_18: LDO_REG6 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-name = "cif_18"; - }; - - vcc_sd: LDO_REG7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc_sd"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - wl_18: LDO_REG8 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-name = "wl_18"; - }; - - lcd_33: SWITCH_REG1 { - regulator-name = "lcd_33"; - }; - }; - }; - -}; - -&i2c2 { - gsl1680: touchscreen@40 { - compatible = "silead,gsl1680"; - reg = <0x40>; - interrupt-parent = <&gpio1>; - interrupts = ; - power-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; - touchscreen-size-x = <800>; - touchscreen-size-y = <1280>; - silead,max-fingers = <5>; - }; -}; - -&mmc0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>; - vmmc-supply = <&vcc_sd>; - - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - disable-wp; -}; - -&pinctrl { - pcfg_output_low: pcfg-output-low { - output-low; - }; - - usb { - host_vbus_drv: host-vbus-drv { - rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - otg_vbus_drv: otg-vbus-drv { - rockchip,pins = <2 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&pwm1 { - status = "okay"; -}; - -&pwm2 { - status = "okay"; -}; - -&pwm3 { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; - -&usb_host { - status = "okay"; -}; - -&usb_otg { - status = "okay"; -}; - -&wdt { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/rk3188-radxarock.dts b/sys/gnu/dts/arm/rk3188-radxarock.dts deleted file mode 100644 index c9a7f540996..00000000000 --- a/sys/gnu/dts/arm/rk3188-radxarock.dts +++ /dev/null @@ -1,382 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2013 Heiko Stuebner - */ - -/dts-v1/; -#include -#include "rk3188.dtsi" - -/ { - model = "Radxa Rock"; - compatible = "radxa,rock", "rockchip,rk3188"; - - memory@60000000 { - device_type = "memory"; - reg = <0x60000000 0x80000000>; - }; - - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - - power { - gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "GPIO Key Power"; - linux,input-type = <1>; - wakeup-source; - debounce-interval = <100>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - green { - label = "rock:green:user1"; - gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - blue { - label = "rock:blue:user2"; - gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - sleep { - label = "rock:red:power"; - gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "SPDIF"; - - simple-audio-card,dai-link@1 { /* S/PDIF - S/PDIF */ - cpu { sound-dai = <&spdif>; }; - codec { sound-dai = <&spdif_out>; }; - }; - }; - - spdif_out: spdif-out { - compatible = "linux,spdif-dit"; - #sound-dai-cells = <0>; - }; - - ir_recv: gpio-ir-receiver { - compatible = "gpio-ir-receiver"; - gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&ir_recv_pin>; - }; - - vcc_otg: usb-otg-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio2 RK_PD7 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&otg_vbus_drv>; - regulator-name = "otg-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - vcc_sd0: sdmmc-regulator { - compatible = "regulator-fixed"; - regulator-name = "sdmmc-supply"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_pwr>; - startup-delay-us = <100000>; - vin-supply = <&vcc_io>; - }; - - vcc_host: usb-host-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&host_vbus_drv>; - regulator-name = "host-pwr"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - vsys: vsys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vsys"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - }; -}; - -&emac { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&emac_xfer>, <&emac_mdio>, <&phy_int>; - - phy = <&phy0>; - phy-supply = <&vcc_rmii>; - - phy0: ethernet-phy@0 { - reg = <0>; - interrupt-parent = <&gpio3>; - interrupts = ; - }; -}; - -&cpu0 { - cpu-supply = <&vdd_arm>; -}; - -&cpu1 { - cpu-supply = <&vdd_arm>; -}; - -&cpu2 { - cpu-supply = <&vdd_arm>; -}; - -&cpu3 { - cpu-supply = <&vdd_arm>; -}; - -&gpu { - status = "okay"; -}; - -&i2c1 { - status = "okay"; - clock-frequency = <400000>; - - rtc@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - interrupt-parent = <&gpio0>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&rtc_int>; - #clock-cells = <0>; - clock-output-names = "xin32k"; - }; - - act8846: act8846@5a { - compatible = "active-semi,act8846"; - reg = <0x5a>; - status = "okay"; - system-power-controller; - - pinctrl-names = "default"; - pinctrl-0 = <&act8846_dvs0_ctl>; - - vp1-supply = <&vsys>; - vp2-supply = <&vsys>; - vp3-supply = <&vsys>; - vp4-supply = <&vsys>; - inl1-supply = <&vcc_io>; - inl2-supply = <&vsys>; - inl3-supply = <&vsys>; - - regulators { - vcc_ddr: REG1 { - regulator-name = "VCC_DDR"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - vdd_log: REG2 { - regulator-name = "VDD_LOG"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - vdd_arm: REG3 { - regulator-name = "VDD_ARM"; - regulator-min-microvolt = <875000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - }; - - vcc_io: REG4 { - regulator-name = "VCC_IO"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_10: REG5 { - regulator-name = "VDD_10"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - vdd_hdmi: REG6 { - regulator-name = "VDD_HDMI"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - vcc18: REG7 { - regulator-name = "VCC_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vcca_33: REG8 { - regulator-name = "VCCA_33"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vcc_rmii: REG9 { - regulator-name = "VCC_RMII"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vccio_wl: REG10 { - regulator-name = "VCCIO_WL"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vcc_18: REG11 { - regulator-name = "VCC18_IO"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vcc28: REG12 { - regulator-name = "VCC_28"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - }; - }; -}; - -&mmc0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>; - vmmc-supply = <&vcc_sd0>; - - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - disable-wp; -}; - -&pwm1 { - status = "okay"; -}; - -&pwm2 { - status = "okay"; -}; - -&pwm3 { - status = "okay"; -}; - -&pinctrl { - pcfg_output_low: pcfg-output-low { - output-low; - }; - - act8846 { - act8846_dvs0_ctl: act8846-dvs0-ctl { - rockchip,pins = <3 RK_PD3 RK_FUNC_GPIO &pcfg_output_low>; - }; - }; - - hym8563 { - rtc_int: rtc-int { - rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - lan8720a { - phy_int: phy-int { - rockchip,pins = <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - ir-receiver { - ir_recv_pin: ir-recv-pin { - rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - sd0 { - sdmmc_pwr: sdmmc-pwr { - rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb { - host_vbus_drv: host-vbus-drv { - rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - otg_vbus_drv: otg-vbus-drv { - rockchip,pins = <2 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&spdif { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; - -&usb_host { - status = "okay"; -}; - -&usb_otg { - status = "okay"; -}; - -&wdt { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/rk3188.dtsi b/sys/gnu/dts/arm/rk3188.dtsi deleted file mode 100644 index 10ede65d90f..00000000000 --- a/sys/gnu/dts/arm/rk3188.dtsi +++ /dev/null @@ -1,801 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2013 MundoReader S.L. - * Author: Heiko Stuebner - */ - -#include -#include -#include -#include -#include "rk3xxx.dtsi" - -/ { - compatible = "rockchip,rk3188"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "rockchip,rk3066-smp"; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - next-level-cache = <&L2>; - reg = <0x0>; - clock-latency = <40000>; - clocks = <&cru ARMCLK>; - operating-points-v2 = <&cpu0_opp_table>; - resets = <&cru SRST_CORE0>; - }; - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - next-level-cache = <&L2>; - reg = <0x1>; - operating-points-v2 = <&cpu0_opp_table>; - resets = <&cru SRST_CORE1>; - }; - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - next-level-cache = <&L2>; - reg = <0x2>; - operating-points-v2 = <&cpu0_opp_table>; - resets = <&cru SRST_CORE2>; - }; - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - next-level-cache = <&L2>; - reg = <0x3>; - operating-points-v2 = <&cpu0_opp_table>; - resets = <&cru SRST_CORE3>; - }; - }; - - cpu0_opp_table: opp_table0 { - compatible = "operating-points-v2"; - opp-shared; - - opp-312000000 { - opp-hz = /bits/ 64 <312000000>; - opp-microvolt = <875000>; - clock-latency-ns = <40000>; - }; - opp-504000000 { - opp-hz = /bits/ 64 <504000000>; - opp-microvolt = <925000>; - }; - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <950000>; - opp-suspend; - }; - opp-816000000 { - opp-hz = /bits/ 64 <816000000>; - opp-microvolt = <975000>; - }; - opp-1008000000 { - opp-hz = /bits/ 64 <1008000000>; - opp-microvolt = <1075000>; - }; - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <1150000>; - }; - opp-1416000000 { - opp-hz = /bits/ 64 <1416000000>; - opp-microvolt = <1250000>; - }; - opp-1608000000 { - opp-hz = /bits/ 64 <1608000000>; - opp-microvolt = <1350000>; - }; - }; - - display-subsystem { - compatible = "rockchip,display-subsystem"; - ports = <&vop0_out>, <&vop1_out>; - }; - - sram: sram@10080000 { - compatible = "mmio-sram"; - reg = <0x10080000 0x8000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x10080000 0x8000>; - - smp-sram@0 { - compatible = "rockchip,rk3066-smp-sram"; - reg = <0x0 0x50>; - }; - }; - - vop0: vop@1010c000 { - compatible = "rockchip,rk3188-vop"; - reg = <0x1010c000 0x1000>; - interrupts = ; - clocks = <&cru ACLK_LCDC0>, <&cru DCLK_LCDC0>, <&cru HCLK_LCDC0>; - clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; - power-domains = <&power RK3188_PD_VIO>; - resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>; - reset-names = "axi", "ahb", "dclk"; - status = "disabled"; - - vop0_out: port { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - vop1: vop@1010e000 { - compatible = "rockchip,rk3188-vop"; - reg = <0x1010e000 0x1000>; - interrupts = ; - clocks = <&cru ACLK_LCDC1>, <&cru DCLK_LCDC1>, <&cru HCLK_LCDC1>; - clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; - power-domains = <&power RK3188_PD_VIO>; - resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>; - reset-names = "axi", "ahb", "dclk"; - status = "disabled"; - - vop1_out: port { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - timer3: timer@2000e000 { - compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer"; - reg = <0x2000e000 0x20>; - interrupts = ; - clocks = <&cru SCLK_TIMER3>, <&cru PCLK_TIMER3>; - clock-names = "timer", "pclk"; - }; - - timer6: timer@200380a0 { - compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer"; - reg = <0x200380a0 0x20>; - interrupts = ; - clocks = <&cru SCLK_TIMER6>, <&cru PCLK_TIMER0>; - clock-names = "timer", "pclk"; - }; - - i2s0: i2s@1011a000 { - compatible = "rockchip,rk3188-i2s", "rockchip,rk3066-i2s"; - reg = <0x1011a000 0x2000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_bus>; - dmas = <&dmac1_s 6>, <&dmac1_s 7>; - dma-names = "tx", "rx"; - clock-names = "i2s_hclk", "i2s_clk"; - clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>; - rockchip,playback-channels = <2>; - rockchip,capture-channels = <2>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - spdif: sound@1011e000 { - compatible = "rockchip,rk3188-spdif", "rockchip,rk3066-spdif"; - reg = <0x1011e000 0x2000>; - #sound-dai-cells = <0>; - clock-names = "hclk", "mclk"; - clocks = <&cru HCLK_SPDIF>, <&cru SCLK_SPDIF>; - dmas = <&dmac1_s 8>; - dma-names = "tx"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&spdif_tx>; - status = "disabled"; - }; - - cru: clock-controller@20000000 { - compatible = "rockchip,rk3188-cru"; - reg = <0x20000000 0x1000>; - rockchip,grf = <&grf>; - - #clock-cells = <1>; - #reset-cells = <1>; - }; - - efuse: efuse@20010000 { - compatible = "rockchip,rk3188-efuse"; - reg = <0x20010000 0x4000>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&cru PCLK_EFUSE>; - clock-names = "pclk_efuse"; - - cpu_leakage: cpu_leakage@17 { - reg = <0x17 0x1>; - }; - }; - - usbphy: phy { - compatible = "rockchip,rk3188-usb-phy", "rockchip,rk3288-usb-phy"; - rockchip,grf = <&grf>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - usbphy0: usb-phy@10c { - #phy-cells = <0>; - reg = <0x10c>; - clocks = <&cru SCLK_OTGPHY0>; - clock-names = "phyclk"; - #clock-cells = <0>; - }; - - usbphy1: usb-phy@11c { - #phy-cells = <0>; - reg = <0x11c>; - clocks = <&cru SCLK_OTGPHY1>; - clock-names = "phyclk"; - #clock-cells = <0>; - }; - }; - - pinctrl: pinctrl { - compatible = "rockchip,rk3188-pinctrl"; - rockchip,grf = <&grf>; - rockchip,pmu = <&pmu>; - - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gpio0: gpio0@2000a000 { - compatible = "rockchip,rk3188-gpio-bank0"; - reg = <0x2000a000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO0>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio1@2003c000 { - compatible = "rockchip,gpio-bank"; - reg = <0x2003c000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO1>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio2@2003e000 { - compatible = "rockchip,gpio-bank"; - reg = <0x2003e000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO2>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio3@20080000 { - compatible = "rockchip,gpio-bank"; - reg = <0x20080000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO3>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - pcfg_pull_up: pcfg_pull_up { - bias-pull-up; - }; - - pcfg_pull_down: pcfg_pull_down { - bias-pull-down; - }; - - pcfg_pull_none: pcfg_pull_none { - bias-disable; - }; - - emmc { - emmc_clk: emmc-clk { - rockchip,pins = <0 RK_PD0 2 &pcfg_pull_none>; - }; - - emmc_cmd: emmc-cmd { - rockchip,pins = <0 RK_PD2 2 &pcfg_pull_up>; - }; - - emmc_rst: emmc-rst { - rockchip,pins = <0 RK_PD3 2 &pcfg_pull_none>; - }; - - /* - * The data pins are shared between nandc and emmc and - * not accessible through pinctrl. Also they should've - * been already set correctly by firmware, as - * flash/emmc is the boot-device. - */ - }; - - emac { - emac_xfer: emac-xfer { - rockchip,pins = <3 RK_PC0 2 &pcfg_pull_none>, /* tx_en */ - <3 RK_PC1 2 &pcfg_pull_none>, /* txd1 */ - <3 RK_PC2 2 &pcfg_pull_none>, /* txd0 */ - <3 RK_PC3 2 &pcfg_pull_none>, /* rxd0 */ - <3 RK_PC4 2 &pcfg_pull_none>, /* rxd1 */ - <3 RK_PC5 2 &pcfg_pull_none>, /* mac_clk */ - <3 RK_PC6 2 &pcfg_pull_none>, /* rx_err */ - <3 RK_PC7 2 &pcfg_pull_none>; /* crs_dvalid */ - }; - - emac_mdio: emac-mdio { - rockchip,pins = <3 RK_PD0 2 &pcfg_pull_none>, - <3 RK_PD1 2 &pcfg_pull_none>; - }; - }; - - i2c0 { - i2c0_xfer: i2c0-xfer { - rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>, - <1 RK_PD1 1 &pcfg_pull_none>; - }; - }; - - i2c1 { - i2c1_xfer: i2c1-xfer { - rockchip,pins = <1 RK_PD2 1 &pcfg_pull_none>, - <1 RK_PD3 1 &pcfg_pull_none>; - }; - }; - - i2c2 { - i2c2_xfer: i2c2-xfer { - rockchip,pins = <1 RK_PD4 1 &pcfg_pull_none>, - <1 RK_PD5 1 &pcfg_pull_none>; - }; - }; - - i2c3 { - i2c3_xfer: i2c3-xfer { - rockchip,pins = <3 RK_PB6 2 &pcfg_pull_none>, - <3 RK_PB7 2 &pcfg_pull_none>; - }; - }; - - i2c4 { - i2c4_xfer: i2c4-xfer { - rockchip,pins = <1 RK_PD6 1 &pcfg_pull_none>, - <1 RK_PD7 1 &pcfg_pull_none>; - }; - }; - - lcdc1 { - lcdc1_dclk: lcdc1-dclk { - rockchip,pins = <2 RK_PD0 1 &pcfg_pull_none>; - }; - - lcdc1_den: lcdc1-den { - rockchip,pins = <2 RK_PD1 1 &pcfg_pull_none>; - }; - - lcdc1_hsync: lcdc1-hsync { - rockchip,pins = <2 RK_PD2 1 &pcfg_pull_none>; - }; - - lcdc1_vsync: lcdc1-vsync { - rockchip,pins = <2 RK_PD3 1 &pcfg_pull_none>; - }; - - lcdc1_rgb24: ldcd1-rgb24 { - rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>, - <2 RK_PA1 1 &pcfg_pull_none>, - <2 RK_PA2 1 &pcfg_pull_none>, - <2 RK_PA3 1 &pcfg_pull_none>, - <2 RK_PA4 1 &pcfg_pull_none>, - <2 RK_PA5 1 &pcfg_pull_none>, - <2 RK_PA6 1 &pcfg_pull_none>, - <2 RK_PA7 1 &pcfg_pull_none>, - <2 RK_PB0 1 &pcfg_pull_none>, - <2 RK_PB1 1 &pcfg_pull_none>, - <2 RK_PB2 1 &pcfg_pull_none>, - <2 RK_PB3 1 &pcfg_pull_none>, - <2 RK_PB4 1 &pcfg_pull_none>, - <2 RK_PB5 1 &pcfg_pull_none>, - <2 RK_PB6 1 &pcfg_pull_none>, - <2 RK_PB7 1 &pcfg_pull_none>, - <2 RK_PC0 1 &pcfg_pull_none>, - <2 RK_PC1 1 &pcfg_pull_none>, - <2 RK_PC2 1 &pcfg_pull_none>, - <2 RK_PC3 1 &pcfg_pull_none>, - <2 RK_PC4 1 &pcfg_pull_none>, - <2 RK_PC5 1 &pcfg_pull_none>, - <2 RK_PC6 1 &pcfg_pull_none>, - <2 RK_PC7 1 &pcfg_pull_none>; - }; - }; - - pwm0 { - pwm0_out: pwm0-out { - rockchip,pins = <3 RK_PD3 1 &pcfg_pull_none>; - }; - }; - - pwm1 { - pwm1_out: pwm1-out { - rockchip,pins = <3 RK_PD4 1 &pcfg_pull_none>; - }; - }; - - pwm2 { - pwm2_out: pwm2-out { - rockchip,pins = <3 RK_PD5 1 &pcfg_pull_none>; - }; - }; - - pwm3 { - pwm3_out: pwm3-out { - rockchip,pins = <3 RK_PD6 1 &pcfg_pull_none>; - }; - }; - - spi0 { - spi0_clk: spi0-clk { - rockchip,pins = <1 RK_PA6 2 &pcfg_pull_up>; - }; - spi0_cs0: spi0-cs0 { - rockchip,pins = <1 RK_PA7 2 &pcfg_pull_up>; - }; - spi0_tx: spi0-tx { - rockchip,pins = <1 RK_PA5 2 &pcfg_pull_up>; - }; - spi0_rx: spi0-rx { - rockchip,pins = <1 RK_PA4 2 &pcfg_pull_up>; - }; - spi0_cs1: spi0-cs1 { - rockchip,pins = <1 RK_PB7 1 &pcfg_pull_up>; - }; - }; - - spi1 { - spi1_clk: spi1-clk { - rockchip,pins = <0 RK_PD6 1 &pcfg_pull_up>; - }; - spi1_cs0: spi1-cs0 { - rockchip,pins = <0 RK_PD7 1 &pcfg_pull_up>; - }; - spi1_rx: spi1-rx { - rockchip,pins = <0 RK_PD4 1 &pcfg_pull_up>; - }; - spi1_tx: spi1-tx { - rockchip,pins = <0 RK_PD5 1 &pcfg_pull_up>; - }; - spi1_cs1: spi1-cs1 { - rockchip,pins = <1 RK_PB6 2 &pcfg_pull_up>; - }; - }; - - uart0 { - uart0_xfer: uart0-xfer { - rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up>, - <1 RK_PA1 1 &pcfg_pull_none>; - }; - - uart0_cts: uart0-cts { - rockchip,pins = <1 RK_PA2 1 &pcfg_pull_none>; - }; - - uart0_rts: uart0-rts { - rockchip,pins = <1 RK_PA3 1 &pcfg_pull_none>; - }; - }; - - uart1 { - uart1_xfer: uart1-xfer { - rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up>, - <1 RK_PA5 1 &pcfg_pull_none>; - }; - - uart1_cts: uart1-cts { - rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none>; - }; - - uart1_rts: uart1-rts { - rockchip,pins = <1 RK_PA7 1 &pcfg_pull_none>; - }; - }; - - uart2 { - uart2_xfer: uart2-xfer { - rockchip,pins = <1 RK_PB0 1 &pcfg_pull_up>, - <1 RK_PB1 1 &pcfg_pull_none>; - }; - /* no rts / cts for uart2 */ - }; - - uart3 { - uart3_xfer: uart3-xfer { - rockchip,pins = <1 RK_PB2 1 &pcfg_pull_up>, - <1 RK_PB3 1 &pcfg_pull_none>; - }; - - uart3_cts: uart3-cts { - rockchip,pins = <1 RK_PB4 1 &pcfg_pull_none>; - }; - - uart3_rts: uart3-rts { - rockchip,pins = <1 RK_PB5 1 &pcfg_pull_none>; - }; - }; - - sd0 { - sd0_clk: sd0-clk { - rockchip,pins = <3 RK_PA2 1 &pcfg_pull_none>; - }; - - sd0_cmd: sd0-cmd { - rockchip,pins = <3 RK_PA3 1 &pcfg_pull_none>; - }; - - sd0_cd: sd0-cd { - rockchip,pins = <3 RK_PB0 1 &pcfg_pull_none>; - }; - - sd0_wp: sd0-wp { - rockchip,pins = <3 RK_PB1 1 &pcfg_pull_none>; - }; - - sd0_pwr: sd0-pwr { - rockchip,pins = <3 RK_PA1 1 &pcfg_pull_none>; - }; - - sd0_bus1: sd0-bus-width1 { - rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>; - }; - - sd0_bus4: sd0-bus-width4 { - rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>, - <3 RK_PA5 1 &pcfg_pull_none>, - <3 RK_PA6 1 &pcfg_pull_none>, - <3 RK_PA7 1 &pcfg_pull_none>; - }; - }; - - sd1 { - sd1_clk: sd1-clk { - rockchip,pins = <3 RK_PC5 1 &pcfg_pull_none>; - }; - - sd1_cmd: sd1-cmd { - rockchip,pins = <3 RK_PC0 1 &pcfg_pull_none>; - }; - - sd1_cd: sd1-cd { - rockchip,pins = <3 RK_PC6 1 &pcfg_pull_none>; - }; - - sd1_wp: sd1-wp { - rockchip,pins = <3 RK_PC7 1 &pcfg_pull_none>; - }; - - sd1_bus1: sd1-bus-width1 { - rockchip,pins = <3 RK_PC1 1 &pcfg_pull_none>; - }; - - sd1_bus4: sd1-bus-width4 { - rockchip,pins = <3 RK_PC1 1 &pcfg_pull_none>, - <3 RK_PC2 1 &pcfg_pull_none>, - <3 RK_PC3 1 &pcfg_pull_none>, - <3 RK_PC4 1 &pcfg_pull_none>; - }; - }; - - i2s0 { - i2s0_bus: i2s0-bus { - rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>, - <1 RK_PC1 1 &pcfg_pull_none>, - <1 RK_PC2 1 &pcfg_pull_none>, - <1 RK_PC3 1 &pcfg_pull_none>, - <1 RK_PC4 1 &pcfg_pull_none>, - <1 RK_PC5 1 &pcfg_pull_none>; - }; - }; - - spdif { - spdif_tx: spdif-tx { - rockchip,pins = <1 RK_PB6 1 &pcfg_pull_none>; - }; - }; - }; -}; - -&emac { - compatible = "rockchip,rk3188-emac"; -}; - -&global_timer { - interrupts = ; - status = "disabled"; -}; - -&local_timer { - interrupts = ; -}; - -&gpu { - compatible = "rockchip,rk3188-mali", "arm,mali-400"; - interrupts = , - , - , - , - , - , - , - , - , - ; - interrupt-names = "gp", - "gpmmu", - "pp0", - "ppmmu0", - "pp1", - "ppmmu1", - "pp2", - "ppmmu2", - "pp3", - "ppmmu3"; - power-domains = <&power RK3188_PD_GPU>; -}; - -&i2c0 { - compatible = "rockchip,rk3188-i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_xfer>; -}; - -&i2c1 { - compatible = "rockchip,rk3188-i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_xfer>; -}; - -&i2c2 { - compatible = "rockchip,rk3188-i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_xfer>; -}; - -&i2c3 { - compatible = "rockchip,rk3188-i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_xfer>; -}; - -&i2c4 { - compatible = "rockchip,rk3188-i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_xfer>; -}; - -&pmu { - power: power-controller { - compatible = "rockchip,rk3188-power-controller"; - #power-domain-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - - pd_vio@RK3188_PD_VIO { - reg = ; - clocks = <&cru ACLK_LCDC0>, - <&cru ACLK_LCDC1>, - <&cru DCLK_LCDC0>, - <&cru DCLK_LCDC1>, - <&cru HCLK_LCDC0>, - <&cru HCLK_LCDC1>, - <&cru SCLK_CIF0>, - <&cru ACLK_CIF0>, - <&cru HCLK_CIF0>, - <&cru ACLK_IPP>, - <&cru HCLK_IPP>, - <&cru ACLK_RGA>, - <&cru HCLK_RGA>; - pm_qos = <&qos_lcdc0>, - <&qos_lcdc1>, - <&qos_cif0>, - <&qos_ipp>, - <&qos_rga>; - }; - - pd_video@RK3188_PD_VIDEO { - reg = ; - clocks = <&cru ACLK_VDPU>, - <&cru ACLK_VEPU>, - <&cru HCLK_VDPU>, - <&cru HCLK_VEPU>; - pm_qos = <&qos_vpu>; - }; - - pd_gpu@RK3188_PD_GPU { - reg = ; - clocks = <&cru ACLK_GPU>; - pm_qos = <&qos_gpu>; - }; - }; -}; - -&pwm0 { - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_out>; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pwm1_out>; -}; - -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pwm2_out>; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pwm3_out>; -}; - -&spi0 { - compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi"; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; -}; - -&spi1 { - compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi"; - pinctrl-names = "default"; - pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; -}; - -&uart0 { - compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart"; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer>; -}; - -&uart1 { - compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart"; - pinctrl-names = "default"; - pinctrl-0 = <&uart1_xfer>; -}; - -&uart2 { - compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart"; - pinctrl-names = "default"; - pinctrl-0 = <&uart2_xfer>; -}; - -&uart3 { - compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart"; - pinctrl-names = "default"; - pinctrl-0 = <&uart3_xfer>; -}; - -&wdt { - compatible = "rockchip,rk3188-wdt", "snps,dw-wdt"; -}; diff --git a/sys/gnu/dts/arm/rk3228-evb.dts b/sys/gnu/dts/arm/rk3228-evb.dts deleted file mode 100644 index 5670b33fd1b..00000000000 --- a/sys/gnu/dts/arm/rk3228-evb.dts +++ /dev/null @@ -1,68 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -/dts-v1/; - -#include "rk322x.dtsi" - -/ { - model = "Rockchip RK3228 Evaluation board"; - compatible = "rockchip,rk3228-evb", "rockchip,rk3228"; - - memory@60000000 { - device_type = "memory"; - reg = <0x60000000 0x40000000>; - }; - - vcc_phy: vcc-phy-regulator { - compatible = "regulator-fixed"; - enable-active-high; - regulator-name = "vcc_phy"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; -}; - -&emmc { - cap-mmc-highspeed; - mmc-ddr-1_8v; - disable-wp; - non-removable; - status = "okay"; -}; - -&gmac { - assigned-clocks = <&cru SCLK_MAC_SRC>; - assigned-clock-rates = <50000000>; - clock_in_out = "output"; - phy-supply = <&vcc_phy>; - phy-mode = "rmii"; - phy-handle = <&phy>; - status = "okay"; - - mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - phy: phy@0 { - compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22"; - reg = <0>; - clocks = <&cru SCLK_MAC_PHY>; - resets = <&cru SRST_MACPHY>; - phy-is-integrated; - }; - }; -}; - -&tsadc { - status = "okay"; - - rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ - rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */ -}; - -&uart2 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/rk3228.dtsi b/sys/gnu/dts/arm/rk3228.dtsi deleted file mode 100644 index e23a22e2915..00000000000 --- a/sys/gnu/dts/arm/rk3228.dtsi +++ /dev/null @@ -1,591 +0,0 @@ -/* - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include -#include -#include -#include -#include -#include -#include "skeleton.dtsi" - -/ { - compatible = "rockchip,rk3228"; - - interrupt-parent = <&gic>; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@f00 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0xf00>; - resets = <&cru SRST_CORE0>; - operating-points = < - /* KHz uV */ - 816000 1000000 - >; - #cooling-cells = <2>; /* min followed by max */ - clock-latency = <40000>; - clocks = <&cru ARMCLK>; - }; - - cpu1: cpu@f01 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0xf01>; - resets = <&cru SRST_CORE1>; - }; - - cpu2: cpu@f02 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0xf02>; - resets = <&cru SRST_CORE2>; - }; - - cpu3: cpu@f03 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0xf03>; - resets = <&cru SRST_CORE3>; - }; - }; - - amba { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - pdma: pdma@110f0000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x110f0000 0x4000>; - interrupts = , - ; - #dma-cells = <1>; - clocks = <&cru ACLK_DMAC>; - clock-names = "apb_pclk"; - }; - }; - - arm-pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts = , - , - , - ; - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; - }; - - timer { - compatible = "arm,armv7-timer"; - arm,cpu-registers-not-fw-configured; - interrupts = , - , - , - ; - clock-frequency = <24000000>; - }; - - xin24m: oscillator { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "xin24m"; - #clock-cells = <0>; - }; - - grf: syscon@11000000 { - compatible = "syscon"; - reg = <0x11000000 0x1000>; - }; - - uart0: serial@11010000 { - compatible = "snps,dw-apb-uart"; - reg = <0x11010000 0x100>; - interrupts = ; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; - clock-names = "baudclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uart1: serial@11020000 { - compatible = "snps,dw-apb-uart"; - reg = <0x11020000 0x100>; - interrupts = ; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; - clock-names = "baudclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart1_xfer>; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uart2: serial@11030000 { - compatible = "snps,dw-apb-uart"; - reg = <0x11030000 0x100>; - interrupts = ; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; - clock-names = "baudclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart2_xfer>; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - i2c0: i2c@11050000 { - compatible = "rockchip,rk3228-i2c"; - reg = <0x11050000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_xfer>; - status = "disabled"; - }; - - i2c1: i2c@11060000 { - compatible = "rockchip,rk3228-i2c"; - reg = <0x11060000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C1>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_xfer>; - status = "disabled"; - }; - - i2c2: i2c@11070000 { - compatible = "rockchip,rk3228-i2c"; - reg = <0x11070000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C2>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_xfer>; - status = "disabled"; - }; - - i2c3: i2c@11080000 { - compatible = "rockchip,rk3228-i2c"; - reg = <0x11080000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C3>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_xfer>; - status = "disabled"; - }; - - pwm0: pwm@110b0000 { - compatible = "rockchip,rk3288-pwm"; - reg = <0x110b0000 0x10>; - #pwm-cells = <3>; - clocks = <&cru PCLK_PWM>; - clock-names = "pwm"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pin>; - status = "disabled"; - }; - - pwm1: pwm@110b0010 { - compatible = "rockchip,rk3288-pwm"; - reg = <0x110b0010 0x10>; - #pwm-cells = <3>; - clocks = <&cru PCLK_PWM>; - clock-names = "pwm"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm1_pin>; - status = "disabled"; - }; - - pwm2: pwm@110b0020 { - compatible = "rockchip,rk3288-pwm"; - reg = <0x110b0020 0x10>; - #pwm-cells = <3>; - clocks = <&cru PCLK_PWM>; - clock-names = "pwm"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm2_pin>; - status = "disabled"; - }; - - pwm3: pwm@110b0030 { - compatible = "rockchip,rk3288-pwm"; - reg = <0x110b0030 0x10>; - #pwm-cells = <2>; - clocks = <&cru PCLK_PWM>; - clock-names = "pwm"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm3_pin>; - status = "disabled"; - }; - - timer: timer@110c0000 { - compatible = "rockchip,rk3288-timer"; - reg = <0x110c0000 0x20>; - interrupts = ; - clocks = <&xin24m>, <&cru PCLK_TIMER>; - clock-names = "timer", "pclk"; - }; - - cru: clock-controller@110e0000 { - compatible = "rockchip,rk3228-cru"; - reg = <0x110e0000 0x1000>; - rockchip,grf = <&grf>; - #clock-cells = <1>; - #reset-cells = <1>; - assigned-clocks = <&cru PLL_GPLL>; - assigned-clock-rates = <594000000>; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <100>; /* milliseconds */ - polling-delay = <5000>; /* milliseconds */ - - thermal-sensors = <&tsadc 0>; - - trips { - cpu_alert0: cpu_alert0 { - temperature = <70000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - cpu_alert1: cpu_alert1 { - temperature = <75000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - cpu_crit: cpu_crit { - temperature = <90000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu_alert0>; - cooling-device = - <&cpu0 THERMAL_NO_LIMIT 6>; - }; - map1 { - trip = <&cpu_alert1>; - cooling-device = - <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - }; - - tsadc: tsadc@11150000 { - compatible = "rockchip,rk3228-tsadc"; - reg = <0x11150000 0x100>; - interrupts = ; - clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; - clock-names = "tsadc", "apb_pclk"; - resets = <&cru SRST_TSADC>; - reset-names = "tsadc-apb"; - pinctrl-names = "init", "default", "sleep"; - pinctrl-0 = <&otp_gpio>; - pinctrl-1 = <&otp_out>; - pinctrl-2 = <&otp_gpio>; - #thermal-sensor-cells = <0>; - rockchip,hw-tshut-temp = <95000>; - status = "disabled"; - }; - - emmc: dwmmc@30020000 { - compatible = "rockchip,rk3288-dw-mshc"; - reg = <0x30020000 0x4000>; - interrupts = ; - clock-frequency = <37500000>; - clock-freq-min-max = <400000 37500000>; - clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, - <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; - bus-width = <8>; - default-sample-phase = <158>; - num-slots = <1>; - fifo-depth = <0x100>; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; - status = "disabled"; - }; - - gic: interrupt-controller@32010000 { - compatible = "arm,gic-400"; - interrupt-controller; - #interrupt-cells = <3>; - #address-cells = <0>; - - reg = <0x32011000 0x1000>, - <0x32012000 0x1000>, - <0x32014000 0x2000>, - <0x32016000 0x2000>; - interrupts = ; - }; - - pinctrl: pinctrl { - compatible = "rockchip,rk3228-pinctrl"; - rockchip,grf = <&grf>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gpio0: gpio0@11110000 { - compatible = "rockchip,gpio-bank"; - reg = <0x11110000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO0>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio1@11120000 { - compatible = "rockchip,gpio-bank"; - reg = <0x11120000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO1>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio2@11130000 { - compatible = "rockchip,gpio-bank"; - reg = <0x11130000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO2>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio3@11140000 { - compatible = "rockchip,gpio-bank"; - reg = <0x11140000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO3>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - pcfg_pull_up: pcfg-pull-up { - bias-pull-up; - }; - - pcfg_pull_down: pcfg-pull-down { - bias-pull-down; - }; - - pcfg_pull_none: pcfg-pull-none { - bias-disable; - }; - - emmc { - emmc_clk: emmc-clk { - rockchip,pins = <2 7 RK_FUNC_2 &pcfg_pull_none>; - }; - - emmc_cmd: emmc-cmd { - rockchip,pins = <1 22 RK_FUNC_2 &pcfg_pull_none>; - }; - - emmc_bus8: emmc-bus8 { - rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_none>, - <1 25 RK_FUNC_2 &pcfg_pull_none>, - <1 26 RK_FUNC_2 &pcfg_pull_none>, - <1 27 RK_FUNC_2 &pcfg_pull_none>, - <1 28 RK_FUNC_2 &pcfg_pull_none>, - <1 29 RK_FUNC_2 &pcfg_pull_none>, - <1 30 RK_FUNC_2 &pcfg_pull_none>, - <1 31 RK_FUNC_2 &pcfg_pull_none>; - }; - }; - - i2c0 { - i2c0_xfer: i2c0-xfer { - rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>, - <0 1 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - - i2c1 { - i2c1_xfer: i2c1-xfer { - rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>, - <0 3 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - - i2c2 { - i2c2_xfer: i2c2-xfer { - rockchip,pins = <2 20 RK_FUNC_1 &pcfg_pull_none>, - <2 21 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - - i2c3 { - i2c3_xfer: i2c3-xfer { - rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>, - <0 7 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - - pwm0 { - pwm0_pin: pwm0-pin { - rockchip,pins = <3 21 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - - pwm1 { - pwm1_pin: pwm1-pin { - rockchip,pins = <0 30 RK_FUNC_2 &pcfg_pull_none>; - }; - }; - - pwm2 { - pwm2_pin: pwm2-pin { - rockchip,pins = <1 12 RK_FUNC_2 &pcfg_pull_none>; - }; - }; - - pwm3 { - pwm3_pin: pwm3-pin { - rockchip,pins = <1 11 RK_FUNC_2 &pcfg_pull_none>; - }; - }; - - tsadc { - otp_gpio: otp-gpio { - rockchip,pins = <0 24 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - otp_out: otp-out { - rockchip,pins = <0 24 RK_FUNC_2 &pcfg_pull_none>; - }; - }; - - uart0 { - uart0_xfer: uart0-xfer { - rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>, - <2 27 RK_FUNC_1 &pcfg_pull_none>; - }; - - uart0_cts: uart0-cts { - rockchip,pins = <2 29 RK_FUNC_1 &pcfg_pull_none>; - }; - - uart0_rts: uart0-rts { - rockchip,pins = <0 17 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - - uart1 { - uart1_xfer: uart1-xfer { - rockchip,pins = <1 9 RK_FUNC_1 &pcfg_pull_none>, - <1 10 RK_FUNC_1 &pcfg_pull_none>; - }; - - uart1_cts: uart1-cts { - rockchip,pins = <1 8 RK_FUNC_1 &pcfg_pull_none>; - }; - - uart1_rts: uart1-rts { - rockchip,pins = <1 11 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - - uart2 { - uart2_xfer: uart2-xfer { - rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_none>, - <1 19 RK_FUNC_2 &pcfg_pull_none>; - }; - - uart2_cts: uart2-cts { - rockchip,pins = <0 25 RK_FUNC_1 &pcfg_pull_none>; - }; - - uart2_rts: uart2-rts { - rockchip,pins = <0 24 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/rk3229-evb.dts b/sys/gnu/dts/arm/rk3229-evb.dts deleted file mode 100644 index 350497a3ca8..00000000000 --- a/sys/gnu/dts/arm/rk3229-evb.dts +++ /dev/null @@ -1,252 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -/dts-v1/; - -#include -#include "rk3229.dtsi" - -/ { - model = "Rockchip RK3229 Evaluation board"; - compatible = "rockchip,rk3229-evb", "rockchip,rk3229"; - - memory@60000000 { - device_type = "memory"; - reg = <0x60000000 0x40000000>; - }; - - dc_12v: dc-12v-regulator { - compatible = "regulator-fixed"; - regulator-name = "dc_12v"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - ext_gmac: ext_gmac { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "ext_gmac"; - #clock-cells = <0>; - }; - - vcc_host: vcc-host-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&host_vbus_drv>; - regulator-name = "vcc_host"; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_sys>; - }; - - vcc_phy: vcc-phy-regulator { - compatible = "regulator-fixed"; - enable-active-high; - regulator-name = "vcc_phy"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vccio_1v8>; - }; - - vcc_sys: vcc-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&dc_12v>; - }; - - vccio_1v8: vccio-1v8-regulator { - compatible = "regulator-fixed"; - regulator-name = "vccio_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - vin-supply = <&vcc_sys>; - }; - - vccio_3v3: vccio-3v3-regulator { - compatible = "regulator-fixed"; - regulator-name = "vccio_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - vin-supply = <&vcc_sys>; - }; - - vdd_arm: vdd-arm-regulator { - compatible = "pwm-regulator"; - pwms = <&pwm1 0 25000 1>; - pwm-supply = <&vcc_sys>; - regulator-name = "vdd_arm"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_log: vdd-log-regulator { - compatible = "pwm-regulator"; - pwms = <&pwm2 0 25000 1>; - pwm-supply = <&vcc_sys>; - regulator-name = "vdd_log"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - }; - - gpio_keys { - compatible = "gpio-keys"; - autorepeat; - pinctrl-names = "default"; - pinctrl-0 = <&pwr_key>; - - power_key: power-key { - label = "GPIO Key Power"; - gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <100>; - wakeup-source; - }; - }; -}; - -&cpu0 { - cpu-supply = <&vdd_arm>; -}; - -&cpu1 { - cpu-supply = <&vdd_arm>; -}; - -&cpu2 { - cpu-supply = <&vdd_arm>; -}; - -&cpu3 { - cpu-supply = <&vdd_arm>; -}; - -&emmc { - cap-mmc-highspeed; - non-removable; - status = "okay"; -}; - -&gmac { - assigned-clocks = <&cru SCLK_MAC_EXTCLK>, <&cru SCLK_MAC>; - assigned-clock-parents = <&ext_gmac>, <&cru SCLK_MAC_EXTCLK>; - clock_in_out = "input"; - phy-supply = <&vcc_phy>; - phy-mode = "rgmii"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - snps,reset-gpio = <&gpio2 RK_PD0 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 1000000>; - tx_delay = <0x30>; - rx_delay = <0x10>; - status = "okay"; -}; - -&io_domains { - status = "okay"; - - vccio1-supply = <&vccio_3v3>; - vccio2-supply = <&vccio_1v8>; - vccio4-supply = <&vccio_3v3>; -}; - -&pinctrl { - keys { - pwr_key: pwr-key { - rockchip,pins = <3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - usb { - host_vbus_drv: host-vbus-drv { - rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&pwm1 { - status = "okay"; -}; - -&pwm2 { - status = "okay"; -}; - -&tsadc { - rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&u2phy0 { - status = "okay"; - - u2phy0_otg: otg-port { - status = "okay"; - }; - - u2phy0_host: host-port { - phy-supply = <&vcc_host>; - status = "okay"; - }; -}; - -&u2phy1 { - status = "okay"; - - u2phy1_otg: otg-port { - phy-supply = <&vcc_host>; - status = "okay"; - }; - - u2phy1_host: host-port { - phy-supply = <&vcc_host>; - status = "okay"; - }; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - -&usb_host2_ehci { - status = "okay"; -}; - -&usb_host2_ohci { - status = "okay"; -}; - -&usb_otg { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/rk3229-xms6.dts b/sys/gnu/dts/arm/rk3229-xms6.dts deleted file mode 100644 index 679fc2b00e5..00000000000 --- a/sys/gnu/dts/arm/rk3229-xms6.dts +++ /dev/null @@ -1,283 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -/dts-v1/; - -#include -#include "rk3229.dtsi" - -/ { - model = "Mecer Xtreme Mini S6"; - compatible = "mecer,xms6", "rockchip,rk3229"; - - memory@60000000 { - device_type = "memory"; - reg = <0x60000000 0x40000000>; - }; - - dc_12v: dc-12v-regulator { - compatible = "regulator-fixed"; - regulator-name = "dc_12v"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - ext_gmac: ext_gmac { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "ext_gmac"; - #clock-cells = <0>; - }; - - power-led { - compatible = "gpio-leds"; - - blue { - gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; - - vcc_host: vcc-host-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&host_vbus_drv>; - regulator-name = "vcc_host"; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_sys>; - }; - - vcc_phy: vcc-phy-regulator { - compatible = "regulator-fixed"; - enable-active-high; - regulator-name = "vcc_phy"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vccio_1v8>; - }; - - vcc_sys: vcc-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&dc_12v>; - }; - - vccio_1v8: vccio-1v8-regulator { - compatible = "regulator-fixed"; - regulator-name = "vccio_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - vin-supply = <&vcc_sys>; - }; - - vccio_3v3: vccio-3v3-regulator { - compatible = "regulator-fixed"; - regulator-name = "vccio_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - vin-supply = <&vcc_sys>; - }; - - vdd_arm: vdd-arm-regulator { - compatible = "pwm-regulator"; - pwms = <&pwm1 0 25000 1>; - pwm-supply = <&vcc_sys>; - regulator-name = "vdd_arm"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_log: vdd-log-regulator { - compatible = "pwm-regulator"; - pwms = <&pwm2 0 25000 1>; - pwm-supply = <&vcc_sys>; - regulator-name = "vdd_log"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - }; -}; - -&cpu0 { - cpu-supply = <&vdd_arm>; -}; - -&cpu1 { - cpu-supply = <&vdd_arm>; -}; - -&cpu2 { - cpu-supply = <&vdd_arm>; -}; - -&cpu3 { - cpu-supply = <&vdd_arm>; -}; - -&emmc { - cap-mmc-highspeed; - disable-wp; - non-removable; - status = "okay"; -}; - -&gmac { - assigned-clocks = <&cru SCLK_MAC_SRC>; - assigned-clock-rates = <50000000>; - clock_in_out = "output"; - phy-handle = <&phy>; - phy-mode = "rmii"; - phy-supply = <&vcc_phy>; - status = "okay"; - - mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - phy: phy@0 { - compatible = "ethernet-phy-id1234.d400", - "ethernet-phy-ieee802.3-c22"; - reg = <0>; - clocks = <&cru SCLK_MAC_PHY>; - phy-is-integrated; - resets = <&cru SRST_MACPHY>; - }; - }; -}; - -&gpu { - mali-supply = <&vdd_log>; - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_phy { - status = "okay"; -}; - -&iep_mmu { - status = "okay"; -}; - -&io_domains { - status = "okay"; - - vccio1-supply = <&vccio_3v3>; - vccio2-supply = <&vccio_1v8>; - vccio4-supply = <&vccio_3v3>; -}; - -&pinctrl { - usb { - host_vbus_drv: host-vbus-drv { - rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&pwm1 { - status = "okay"; -}; - -&pwm2 { - status = "okay"; -}; - -&sdmmc { - cap-mmc-highspeed; - disable-wp; - status = "okay"; -}; - -&tsadc { - rockchip,hw-tshut-mode = <0>; - status = "okay"; -}; - -&u2phy0 { - status = "okay"; - - u2phy0_host: host-port { - phy-supply = <&vcc_host>; - status = "okay"; - }; - - u2phy0_otg: otg-port { - phy-supply = <&vcc_host>; - status = "okay"; - }; -}; - -&u2phy1 { - status = "okay"; - - u2phy1_host: host-port { - phy-supply = <&vcc_host>; - status = "okay"; - }; - - u2phy1_otg: otg-port { - phy-supply = <&vcc_host>; - status = "okay"; - }; -}; - -&uart2 { - pinctrl-0 = <&uart21_xfer>; - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - -&usb_host2_ehci { - status = "okay"; -}; - -&usb_host2_ohci { - status = "okay"; -}; - -&usb_otg { - status = "okay"; -}; - -&vop { - status = "okay"; -}; - -&vop_mmu { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/rk3229.dtsi b/sys/gnu/dts/arm/rk3229.dtsi deleted file mode 100644 index cb7d3fad8e6..00000000000 --- a/sys/gnu/dts/arm/rk3229.dtsi +++ /dev/null @@ -1,52 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd - */ - -#include "rk322x.dtsi" - -/ { - compatible = "rockchip,rk3229"; - - /delete-node/ opp-table0; - - cpu0_opp_table: opp_table0 { - compatible = "operating-points-v2"; - opp-shared; - - opp-408000000 { - opp-hz = /bits/ 64 <408000000>; - opp-microvolt = <950000>; - clock-latency-ns = <40000>; - opp-suspend; - }; - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <975000>; - }; - opp-816000000 { - opp-hz = /bits/ 64 <816000000>; - opp-microvolt = <1000000>; - }; - opp-1008000000 { - opp-hz = /bits/ 64 <1008000000>; - opp-microvolt = <1175000>; - }; - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <1275000>; - }; - opp-1296000000 { - opp-hz = /bits/ 64 <1296000000>; - opp-microvolt = <1325000>; - }; - opp-1392000000 { - opp-hz = /bits/ 64 <1392000000>; - opp-microvolt = <1375000>; - }; - opp-1464000000 { - opp-hz = /bits/ 64 <1464000000>; - opp-microvolt = <1400000>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/rk322x.dtsi b/sys/gnu/dts/arm/rk322x.dtsi deleted file mode 100644 index 4e90efdc963..00000000000 --- a/sys/gnu/dts/arm/rk322x.dtsi +++ /dev/null @@ -1,1176 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -#include -#include -#include -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - - interrupt-parent = <&gic>; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - spi0 = &spi0; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@f00 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0xf00>; - resets = <&cru SRST_CORE0>; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - clock-latency = <40000>; - clocks = <&cru ARMCLK>; - enable-method = "psci"; - }; - - cpu1: cpu@f01 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0xf01>; - resets = <&cru SRST_CORE1>; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - enable-method = "psci"; - }; - - cpu2: cpu@f02 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0xf02>; - resets = <&cru SRST_CORE2>; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - enable-method = "psci"; - }; - - cpu3: cpu@f03 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0xf03>; - resets = <&cru SRST_CORE3>; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - enable-method = "psci"; - }; - }; - - cpu0_opp_table: opp_table0 { - compatible = "operating-points-v2"; - opp-shared; - - opp-408000000 { - opp-hz = /bits/ 64 <408000000>; - opp-microvolt = <950000>; - clock-latency-ns = <40000>; - opp-suspend; - }; - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <975000>; - }; - opp-816000000 { - opp-hz = /bits/ 64 <816000000>; - opp-microvolt = <1000000>; - }; - opp-1008000000 { - opp-hz = /bits/ 64 <1008000000>; - opp-microvolt = <1175000>; - }; - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <1275000>; - }; - }; - - amba { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - pdma: pdma@110f0000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x110f0000 0x4000>; - interrupts = , - ; - #dma-cells = <1>; - clocks = <&cru ACLK_DMAC>; - clock-names = "apb_pclk"; - }; - }; - - arm-pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts = , - , - , - ; - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; - }; - - psci { - compatible = "arm,psci-1.0", "arm,psci-0.2"; - method = "smc"; - }; - - timer { - compatible = "arm,armv7-timer"; - arm,cpu-registers-not-fw-configured; - interrupts = , - , - , - ; - clock-frequency = <24000000>; - }; - - xin24m: oscillator { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "xin24m"; - #clock-cells = <0>; - }; - - display_subsystem: display-subsystem { - compatible = "rockchip,display-subsystem"; - ports = <&vop_out>; - }; - - i2s1: i2s1@100b0000 { - compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; - reg = <0x100b0000 0x4000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2s_clk", "i2s_hclk"; - clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>; - dmas = <&pdma 14>, <&pdma 15>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&i2s1_bus>; - status = "disabled"; - }; - - i2s0: i2s0@100c0000 { - compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; - reg = <0x100c0000 0x4000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2s_clk", "i2s_hclk"; - clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>; - dmas = <&pdma 11>, <&pdma 12>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - spdif: spdif@100d0000 { - compatible = "rockchip,rk3228-spdif"; - reg = <0x100d0000 0x1000>; - interrupts = ; - clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>; - clock-names = "mclk", "hclk"; - dmas = <&pdma 10>; - dma-names = "tx"; - pinctrl-names = "default"; - pinctrl-0 = <&spdif_tx>; - status = "disabled"; - }; - - i2s2: i2s2@100e0000 { - compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; - reg = <0x100e0000 0x4000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2s_clk", "i2s_hclk"; - clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>; - dmas = <&pdma 0>, <&pdma 1>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - grf: syscon@11000000 { - compatible = "rockchip,rk3228-grf", "syscon", "simple-mfd"; - reg = <0x11000000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - - io_domains: io-domains { - compatible = "rockchip,rk3228-io-voltage-domain"; - status = "disabled"; - }; - - u2phy0: usb2-phy@760 { - compatible = "rockchip,rk3228-usb2phy"; - reg = <0x0760 0x0c>; - clocks = <&cru SCLK_OTGPHY0>; - clock-names = "phyclk"; - clock-output-names = "usb480m_phy0"; - #clock-cells = <0>; - status = "disabled"; - - u2phy0_otg: otg-port { - interrupts = , - , - ; - interrupt-names = "otg-bvalid", "otg-id", - "linestate"; - #phy-cells = <0>; - status = "disabled"; - }; - - u2phy0_host: host-port { - interrupts = ; - interrupt-names = "linestate"; - #phy-cells = <0>; - status = "disabled"; - }; - }; - - u2phy1: usb2-phy@800 { - compatible = "rockchip,rk3228-usb2phy"; - reg = <0x0800 0x0c>; - clocks = <&cru SCLK_OTGPHY1>; - clock-names = "phyclk"; - clock-output-names = "usb480m_phy1"; - #clock-cells = <0>; - status = "disabled"; - - u2phy1_otg: otg-port { - interrupts = ; - interrupt-names = "linestate"; - #phy-cells = <0>; - status = "disabled"; - }; - - u2phy1_host: host-port { - interrupts = ; - interrupt-names = "linestate"; - #phy-cells = <0>; - status = "disabled"; - }; - }; - }; - - uart0: serial@11010000 { - compatible = "snps,dw-apb-uart"; - reg = <0x11010000 0x100>; - interrupts = ; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; - clock-names = "baudclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uart1: serial@11020000 { - compatible = "snps,dw-apb-uart"; - reg = <0x11020000 0x100>; - interrupts = ; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; - clock-names = "baudclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart1_xfer>; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uart2: serial@11030000 { - compatible = "snps,dw-apb-uart"; - reg = <0x11030000 0x100>; - interrupts = ; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; - clock-names = "baudclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart2_xfer>; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - efuse: efuse@11040000 { - compatible = "rockchip,rk3228-efuse"; - reg = <0x11040000 0x20>; - clocks = <&cru PCLK_EFUSE_256>; - clock-names = "pclk_efuse"; - #address-cells = <1>; - #size-cells = <1>; - - /* Data cells */ - efuse_id: id@7 { - reg = <0x7 0x10>; - }; - cpu_leakage: cpu_leakage@17 { - reg = <0x17 0x1>; - }; - }; - - i2c0: i2c@11050000 { - compatible = "rockchip,rk3228-i2c"; - reg = <0x11050000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_xfer>; - status = "disabled"; - }; - - i2c1: i2c@11060000 { - compatible = "rockchip,rk3228-i2c"; - reg = <0x11060000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C1>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_xfer>; - status = "disabled"; - }; - - i2c2: i2c@11070000 { - compatible = "rockchip,rk3228-i2c"; - reg = <0x11070000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C2>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_xfer>; - status = "disabled"; - }; - - i2c3: i2c@11080000 { - compatible = "rockchip,rk3228-i2c"; - reg = <0x11080000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C3>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_xfer>; - status = "disabled"; - }; - - spi0: spi@11090000 { - compatible = "rockchip,rk3228-spi"; - reg = <0x11090000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; - clock-names = "spiclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0 &spi0_cs1>; - status = "disabled"; - }; - - wdt: watchdog@110a0000 { - compatible = "snps,dw-wdt"; - reg = <0x110a0000 0x100>; - interrupts = ; - clocks = <&cru PCLK_CPU>; - status = "disabled"; - }; - - pwm0: pwm@110b0000 { - compatible = "rockchip,rk3288-pwm"; - reg = <0x110b0000 0x10>; - #pwm-cells = <3>; - clocks = <&cru PCLK_PWM>; - clock-names = "pwm"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pin>; - status = "disabled"; - }; - - pwm1: pwm@110b0010 { - compatible = "rockchip,rk3288-pwm"; - reg = <0x110b0010 0x10>; - #pwm-cells = <3>; - clocks = <&cru PCLK_PWM>; - clock-names = "pwm"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm1_pin>; - status = "disabled"; - }; - - pwm2: pwm@110b0020 { - compatible = "rockchip,rk3288-pwm"; - reg = <0x110b0020 0x10>; - #pwm-cells = <3>; - clocks = <&cru PCLK_PWM>; - clock-names = "pwm"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm2_pin>; - status = "disabled"; - }; - - pwm3: pwm@110b0030 { - compatible = "rockchip,rk3288-pwm"; - reg = <0x110b0030 0x10>; - #pwm-cells = <2>; - clocks = <&cru PCLK_PWM>; - clock-names = "pwm"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm3_pin>; - status = "disabled"; - }; - - timer: timer@110c0000 { - compatible = "rockchip,rk3228-timer", "rockchip,rk3288-timer"; - reg = <0x110c0000 0x20>; - interrupts = ; - clocks = <&xin24m>, <&cru PCLK_TIMER>; - clock-names = "timer", "pclk"; - }; - - cru: clock-controller@110e0000 { - compatible = "rockchip,rk3228-cru"; - reg = <0x110e0000 0x1000>; - rockchip,grf = <&grf>; - #clock-cells = <1>; - #reset-cells = <1>; - assigned-clocks = - <&cru PLL_GPLL>, <&cru ARMCLK>, - <&cru PLL_CPLL>, <&cru ACLK_PERI>, - <&cru HCLK_PERI>, <&cru PCLK_PERI>, - <&cru ACLK_CPU>, <&cru HCLK_CPU>, - <&cru PCLK_CPU>; - assigned-clock-rates = - <594000000>, <816000000>, - <500000000>, <150000000>, - <150000000>, <75000000>, - <150000000>, <150000000>, - <75000000>; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <100>; /* milliseconds */ - polling-delay = <5000>; /* milliseconds */ - - thermal-sensors = <&tsadc 0>; - - trips { - cpu_alert0: cpu_alert0 { - temperature = <70000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - cpu_alert1: cpu_alert1 { - temperature = <75000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - cpu_crit: cpu_crit { - temperature = <90000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu_alert0>; - cooling-device = - <&cpu0 THERMAL_NO_LIMIT 6>, - <&cpu1 THERMAL_NO_LIMIT 6>, - <&cpu2 THERMAL_NO_LIMIT 6>, - <&cpu3 THERMAL_NO_LIMIT 6>; - }; - map1 { - trip = <&cpu_alert1>; - cooling-device = - <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - }; - - tsadc: tsadc@11150000 { - compatible = "rockchip,rk3228-tsadc"; - reg = <0x11150000 0x100>; - interrupts = ; - clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; - clock-names = "tsadc", "apb_pclk"; - assigned-clocks = <&cru SCLK_TSADC>; - assigned-clock-rates = <32768>; - resets = <&cru SRST_TSADC>; - reset-names = "tsadc-apb"; - pinctrl-names = "init", "default", "sleep"; - pinctrl-0 = <&otp_gpio>; - pinctrl-1 = <&otp_out>; - pinctrl-2 = <&otp_gpio>; - #thermal-sensor-cells = <0>; - rockchip,hw-tshut-temp = <95000>; - status = "disabled"; - }; - - hdmi_phy: hdmi-phy@12030000 { - compatible = "rockchip,rk3228-hdmi-phy"; - reg = <0x12030000 0x10000>; - clocks = <&cru PCLK_HDMI_PHY>, <&xin24m>, <&cru DCLK_HDMI_PHY>; - clock-names = "sysclk", "refoclk", "refpclk"; - #clock-cells = <0>; - clock-output-names = "hdmiphy_phy"; - #phy-cells = <0>; - status = "disabled"; - }; - - gpu: gpu@20000000 { - compatible = "rockchip,rk3228-mali", "arm,mali-400"; - reg = <0x20000000 0x10000>; - interrupts = , - , - , - , - , - ; - interrupt-names = "gp", - "gpmmu", - "pp0", - "ppmmu0", - "pp1", - "ppmmu1"; - clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>; - clock-names = "core", "bus"; - resets = <&cru SRST_GPU_A>; - status = "disabled"; - }; - - vpu_mmu: iommu@20020800 { - compatible = "rockchip,iommu"; - reg = <0x20020800 0x100>; - interrupts = ; - interrupt-names = "vpu_mmu"; - clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; - clock-names = "aclk", "iface"; - iommu-cells = <0>; - status = "disabled"; - }; - - vdec_mmu: iommu@20030480 { - compatible = "rockchip,iommu"; - reg = <0x20030480 0x40>, <0x200304c0 0x40>; - interrupts = ; - interrupt-names = "vdec_mmu"; - clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>; - clock-names = "aclk", "iface"; - iommu-cells = <0>; - status = "disabled"; - }; - - vop: vop@20050000 { - compatible = "rockchip,rk3228-vop"; - reg = <0x20050000 0x1ffc>; - interrupts = ; - clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>; - clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; - resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>; - reset-names = "axi", "ahb", "dclk"; - iommus = <&vop_mmu>; - status = "disabled"; - - vop_out: port { - #address-cells = <1>; - #size-cells = <0>; - - vop_out_hdmi: endpoint@0 { - reg = <0>; - remote-endpoint = <&hdmi_in_vop>; - }; - }; - }; - - vop_mmu: iommu@20053f00 { - compatible = "rockchip,iommu"; - reg = <0x20053f00 0x100>; - interrupts = ; - interrupt-names = "vop_mmu"; - clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; - clock-names = "aclk", "iface"; - #iommu-cells = <0>; - status = "disabled"; - }; - - iep_mmu: iommu@20070800 { - compatible = "rockchip,iommu"; - reg = <0x20070800 0x100>; - interrupts = ; - interrupt-names = "iep_mmu"; - clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; - clock-names = "aclk", "iface"; - iommu-cells = <0>; - status = "disabled"; - }; - - hdmi: hdmi@200a0000 { - compatible = "rockchip,rk3228-dw-hdmi"; - reg = <0x200a0000 0x20000>; - reg-io-width = <4>; - interrupts = ; - assigned-clocks = <&cru SCLK_HDMI_PHY>; - assigned-clock-parents = <&hdmi_phy>; - clocks = <&cru SCLK_HDMI_HDCP>, <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_CEC>; - clock-names = "isfr", "iahb", "cec"; - pinctrl-names = "default"; - pinctrl-0 = <&hdmii2c_xfer &hdmi_hpd &hdmi_cec>; - resets = <&cru SRST_HDMI_P>; - reset-names = "hdmi"; - phys = <&hdmi_phy>; - phy-names = "hdmi"; - rockchip,grf = <&grf>; - status = "disabled"; - - ports { - hdmi_in: port { - #address-cells = <1>; - #size-cells = <0>; - hdmi_in_vop: endpoint@0 { - reg = <0>; - remote-endpoint = <&vop_out_hdmi>; - }; - }; - }; - }; - - sdmmc: mmc@30000000 { - compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x30000000 0x4000>; - interrupts = ; - clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, - <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; - status = "disabled"; - }; - - sdio: mmc@30010000 { - compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x30010000 0x4000>; - interrupts = ; - clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, - <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - pinctrl-names = "default"; - pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>; - status = "disabled"; - }; - - emmc: mmc@30020000 { - compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x30020000 0x4000>; - interrupts = ; - clock-frequency = <37500000>; - max-frequency = <37500000>; - clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, - <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - bus-width = <8>; - default-sample-phase = <158>; - fifo-depth = <0x100>; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; - resets = <&cru SRST_EMMC>; - reset-names = "reset"; - status = "disabled"; - }; - - usb_otg: usb@30040000 { - compatible = "rockchip,rk3228-usb", "rockchip,rk3066-usb", - "snps,dwc2"; - reg = <0x30040000 0x40000>; - interrupts = ; - clocks = <&cru HCLK_OTG>; - clock-names = "otg"; - dr_mode = "otg"; - g-np-tx-fifo-size = <16>; - g-rx-fifo-size = <280>; - g-tx-fifo-size = <256 128 128 64 32 16>; - g-use-dma; - phys = <&u2phy0_otg>; - phy-names = "usb2-phy"; - status = "disabled"; - }; - - usb_host0_ehci: usb@30080000 { - compatible = "generic-ehci"; - reg = <0x30080000 0x20000>; - interrupts = ; - clocks = <&cru HCLK_HOST0>, <&u2phy0>; - clock-names = "usbhost", "utmi"; - phys = <&u2phy0_host>; - phy-names = "usb"; - status = "disabled"; - }; - - usb_host0_ohci: usb@300a0000 { - compatible = "generic-ohci"; - reg = <0x300a0000 0x20000>; - interrupts = ; - clocks = <&cru HCLK_HOST0>, <&u2phy0>; - clock-names = "usbhost", "utmi"; - phys = <&u2phy0_host>; - phy-names = "usb"; - status = "disabled"; - }; - - usb_host1_ehci: usb@300c0000 { - compatible = "generic-ehci"; - reg = <0x300c0000 0x20000>; - interrupts = ; - clocks = <&cru HCLK_HOST1>, <&u2phy1>; - clock-names = "usbhost", "utmi"; - phys = <&u2phy1_otg>; - phy-names = "usb"; - status = "disabled"; - }; - - usb_host1_ohci: usb@300e0000 { - compatible = "generic-ohci"; - reg = <0x300e0000 0x20000>; - interrupts = ; - clocks = <&cru HCLK_HOST1>, <&u2phy1>; - clock-names = "usbhost", "utmi"; - phys = <&u2phy1_otg>; - phy-names = "usb"; - status = "disabled"; - }; - - usb_host2_ehci: usb@30100000 { - compatible = "generic-ehci"; - reg = <0x30100000 0x20000>; - interrupts = ; - clocks = <&cru HCLK_HOST2>, <&u2phy1>; - phys = <&u2phy1_host>; - phy-names = "usb"; - clock-names = "usbhost", "utmi"; - status = "disabled"; - }; - - usb_host2_ohci: usb@30120000 { - compatible = "generic-ohci"; - reg = <0x30120000 0x20000>; - interrupts = ; - clocks = <&cru HCLK_HOST2>, <&u2phy1>; - clock-names = "usbhost", "utmi"; - phys = <&u2phy1_host>; - phy-names = "usb"; - status = "disabled"; - }; - - gmac: ethernet@30200000 { - compatible = "rockchip,rk3228-gmac"; - reg = <0x30200000 0x10000>; - interrupts = ; - interrupt-names = "macirq"; - clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>, - <&cru SCLK_MAC_TX>, <&cru SCLK_MAC_REF>, - <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>, - <&cru PCLK_GMAC>; - clock-names = "stmmaceth", "mac_clk_rx", - "mac_clk_tx", "clk_mac_ref", - "clk_mac_refout", "aclk_mac", - "pclk_mac"; - resets = <&cru SRST_GMAC>; - reset-names = "stmmaceth"; - rockchip,grf = <&grf>; - status = "disabled"; - }; - - gic: interrupt-controller@32010000 { - compatible = "arm,gic-400"; - interrupt-controller; - #interrupt-cells = <3>; - #address-cells = <0>; - - reg = <0x32011000 0x1000>, - <0x32012000 0x2000>, - <0x32014000 0x2000>, - <0x32016000 0x2000>; - interrupts = ; - }; - - pinctrl: pinctrl { - compatible = "rockchip,rk3228-pinctrl"; - rockchip,grf = <&grf>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gpio0: gpio0@11110000 { - compatible = "rockchip,gpio-bank"; - reg = <0x11110000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO0>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio1@11120000 { - compatible = "rockchip,gpio-bank"; - reg = <0x11120000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO1>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio2@11130000 { - compatible = "rockchip,gpio-bank"; - reg = <0x11130000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO2>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio3@11140000 { - compatible = "rockchip,gpio-bank"; - reg = <0x11140000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO3>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - pcfg_pull_up: pcfg-pull-up { - bias-pull-up; - }; - - pcfg_pull_down: pcfg-pull-down { - bias-pull-down; - }; - - pcfg_pull_none: pcfg-pull-none { - bias-disable; - }; - - pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma { - drive-strength = <12>; - }; - - sdmmc { - sdmmc_clk: sdmmc-clk { - rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none_drv_12ma>; - }; - - sdmmc_cmd: sdmmc-cmd { - rockchip,pins = <1 RK_PB7 1 &pcfg_pull_none_drv_12ma>; - }; - - sdmmc_bus4: sdmmc-bus4 { - rockchip,pins = <1 RK_PC2 1 &pcfg_pull_none_drv_12ma>, - <1 RK_PC3 1 &pcfg_pull_none_drv_12ma>, - <1 RK_PC4 1 &pcfg_pull_none_drv_12ma>, - <1 RK_PC5 1 &pcfg_pull_none_drv_12ma>; - }; - }; - - sdio { - sdio_clk: sdio-clk { - rockchip,pins = <3 RK_PA0 1 &pcfg_pull_none_drv_12ma>; - }; - - sdio_cmd: sdio-cmd { - rockchip,pins = <3 RK_PA1 1 &pcfg_pull_none_drv_12ma>; - }; - - sdio_bus4: sdio-bus4 { - rockchip,pins = <3 RK_PA2 1 &pcfg_pull_none_drv_12ma>, - <3 RK_PA3 1 &pcfg_pull_none_drv_12ma>, - <3 RK_PA4 1 &pcfg_pull_none_drv_12ma>, - <3 RK_PA5 1 &pcfg_pull_none_drv_12ma>; - }; - }; - - emmc { - emmc_clk: emmc-clk { - rockchip,pins = <2 RK_PA7 2 &pcfg_pull_none>; - }; - - emmc_cmd: emmc-cmd { - rockchip,pins = <1 RK_PC6 2 &pcfg_pull_none>; - }; - - emmc_bus8: emmc-bus8 { - rockchip,pins = <1 RK_PD0 2 &pcfg_pull_none>, - <1 RK_PD1 2 &pcfg_pull_none>, - <1 RK_PD2 2 &pcfg_pull_none>, - <1 RK_PD3 2 &pcfg_pull_none>, - <1 RK_PD4 2 &pcfg_pull_none>, - <1 RK_PD5 2 &pcfg_pull_none>, - <1 RK_PD6 2 &pcfg_pull_none>, - <1 RK_PD7 2 &pcfg_pull_none>; - }; - }; - - gmac { - rgmii_pins: rgmii-pins { - rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none>, - <2 RK_PB4 1 &pcfg_pull_none>, - <2 RK_PD1 1 &pcfg_pull_none>, - <2 RK_PC3 1 &pcfg_pull_none_drv_12ma>, - <2 RK_PC2 1 &pcfg_pull_none_drv_12ma>, - <2 RK_PC6 1 &pcfg_pull_none_drv_12ma>, - <2 RK_PC7 1 &pcfg_pull_none_drv_12ma>, - <2 RK_PB1 1 &pcfg_pull_none_drv_12ma>, - <2 RK_PB5 1 &pcfg_pull_none_drv_12ma>, - <2 RK_PC1 1 &pcfg_pull_none>, - <2 RK_PC0 1 &pcfg_pull_none>, - <2 RK_PC5 2 &pcfg_pull_none>, - <2 RK_PC4 2 &pcfg_pull_none>, - <2 RK_PB3 1 &pcfg_pull_none>, - <2 RK_PB0 1 &pcfg_pull_none>; - }; - - rmii_pins: rmii-pins { - rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none>, - <2 RK_PB4 1 &pcfg_pull_none>, - <2 RK_PD1 1 &pcfg_pull_none>, - <2 RK_PC3 1 &pcfg_pull_none_drv_12ma>, - <2 RK_PC2 1 &pcfg_pull_none_drv_12ma>, - <2 RK_PB5 1 &pcfg_pull_none_drv_12ma>, - <2 RK_PC1 1 &pcfg_pull_none>, - <2 RK_PC0 1 &pcfg_pull_none>, - <2 RK_PB0 1 &pcfg_pull_none>, - <2 RK_PB7 1 &pcfg_pull_none>; - }; - - phy_pins: phy-pins { - rockchip,pins = <2 RK_PB6 2 &pcfg_pull_none>, - <2 RK_PB0 2 &pcfg_pull_none>; - }; - }; - - hdmi { - hdmi_hpd: hdmi-hpd { - rockchip,pins = <0 RK_PB7 1 &pcfg_pull_down>; - }; - - hdmii2c_xfer: hdmii2c-xfer { - rockchip,pins = <0 RK_PA6 2 &pcfg_pull_none>, - <0 RK_PA7 2 &pcfg_pull_none>; - }; - - hdmi_cec: hdmi-cec { - rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>; - }; - }; - - i2c0 { - i2c0_xfer: i2c0-xfer { - rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>, - <0 RK_PA1 1 &pcfg_pull_none>; - }; - }; - - i2c1 { - i2c1_xfer: i2c1-xfer { - rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>, - <0 RK_PA3 1 &pcfg_pull_none>; - }; - }; - - i2c2 { - i2c2_xfer: i2c2-xfer { - rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>, - <2 RK_PC5 1 &pcfg_pull_none>; - }; - }; - - i2c3 { - i2c3_xfer: i2c3-xfer { - rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>, - <0 RK_PA7 1 &pcfg_pull_none>; - }; - }; - - spi-0 { - spi0_clk: spi0-clk { - rockchip,pins = <0 RK_PB1 2 &pcfg_pull_up>; - }; - spi0_cs0: spi0-cs0 { - rockchip,pins = <0 RK_PB6 2 &pcfg_pull_up>; - }; - spi0_tx: spi0-tx { - rockchip,pins = <0 RK_PB3 2 &pcfg_pull_up>; - }; - spi0_rx: spi0-rx { - rockchip,pins = <0 RK_PB5 2 &pcfg_pull_up>; - }; - spi0_cs1: spi0-cs1 { - rockchip,pins = <1 RK_PB4 1 &pcfg_pull_up>; - }; - }; - - spi-1 { - spi1_clk: spi1-clk { - rockchip,pins = <0 RK_PC7 2 &pcfg_pull_up>; - }; - spi1_cs0: spi1-cs0 { - rockchip,pins = <2 RK_PA2 2 &pcfg_pull_up>; - }; - spi1_rx: spi1-rx { - rockchip,pins = <2 RK_PA0 2 &pcfg_pull_up>; - }; - spi1_tx: spi1-tx { - rockchip,pins = <2 RK_PA1 2 &pcfg_pull_up>; - }; - spi1_cs1: spi1-cs1 { - rockchip,pins = <2 RK_PA3 2 &pcfg_pull_up>; - }; - }; - - i2s1 { - i2s1_bus: i2s1-bus { - rockchip,pins = <0 RK_PB0 1 &pcfg_pull_none>, - <0 RK_PB1 1 &pcfg_pull_none>, - <0 RK_PB3 1 &pcfg_pull_none>, - <0 RK_PB4 1 &pcfg_pull_none>, - <0 RK_PB5 1 &pcfg_pull_none>, - <0 RK_PB6 1 &pcfg_pull_none>, - <1 RK_PA2 2 &pcfg_pull_none>, - <1 RK_PA4 2 &pcfg_pull_none>, - <1 RK_PA5 2 &pcfg_pull_none>; - }; - }; - - pwm0 { - pwm0_pin: pwm0-pin { - rockchip,pins = <3 RK_PC5 1 &pcfg_pull_none>; - }; - }; - - pwm1 { - pwm1_pin: pwm1-pin { - rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>; - }; - }; - - pwm2 { - pwm2_pin: pwm2-pin { - rockchip,pins = <1 RK_PB4 2 &pcfg_pull_none>; - }; - }; - - pwm3 { - pwm3_pin: pwm3-pin { - rockchip,pins = <1 RK_PB3 2 &pcfg_pull_none>; - }; - }; - - spdif { - spdif_tx: spdif-tx { - rockchip,pins = <3 RK_PD7 2 &pcfg_pull_none>; - }; - }; - - tsadc { - otp_gpio: otp-gpio { - rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - otp_out: otp-out { - rockchip,pins = <0 RK_PD0 2 &pcfg_pull_none>; - }; - }; - - uart0 { - uart0_xfer: uart0-xfer { - rockchip,pins = <2 RK_PD2 1 &pcfg_pull_none>, - <2 RK_PD3 1 &pcfg_pull_none>; - }; - - uart0_cts: uart0-cts { - rockchip,pins = <2 RK_PD5 1 &pcfg_pull_none>; - }; - - uart0_rts: uart0-rts { - rockchip,pins = <0 RK_PC1 1 &pcfg_pull_none>; - }; - }; - - uart1 { - uart1_xfer: uart1-xfer { - rockchip,pins = <1 RK_PB1 1 &pcfg_pull_none>, - <1 RK_PB2 1 &pcfg_pull_none>; - }; - - uart1_cts: uart1-cts { - rockchip,pins = <1 RK_PB0 1 &pcfg_pull_none>; - }; - - uart1_rts: uart1-rts { - rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>; - }; - }; - - uart2 { - uart2_xfer: uart2-xfer { - rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>, - <1 RK_PC3 2 &pcfg_pull_none>; - }; - - uart21_xfer: uart21-xfer { - rockchip,pins = <1 RK_PB2 2 &pcfg_pull_up>, - <1 RK_PB1 2 &pcfg_pull_none>; - }; - - uart2_cts: uart2-cts { - rockchip,pins = <0 RK_PD1 1 &pcfg_pull_none>; - }; - - uart2_rts: uart2-rts { - rockchip,pins = <0 RK_PD0 1 &pcfg_pull_none>; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/rk3288-evb-act8846.dts b/sys/gnu/dts/arm/rk3288-evb-act8846.dts deleted file mode 100644 index 80080767c36..00000000000 --- a/sys/gnu/dts/arm/rk3288-evb-act8846.dts +++ /dev/null @@ -1,187 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -/dts-v1/; -#include "rk3288-evb.dtsi" - -/ { - compatible = "rockchip,rk3288-evb-act8846", "rockchip,rk3288"; - - vcc_lcd: vcc-lcd { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio7 RK_PA3 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&lcd_en>; - regulator-name = "vcc_lcd"; - vin-supply = <&vcc_io>; - }; - - vcc_wl: vcc-wl { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio7 RK_PB1 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_pwr>; - regulator-name = "vcc_wl"; - vin-supply = <&vcc_18>; - }; -}; - -&i2c0 { - clock-frequency = <400000>; - - vdd_cpu: syr827@40 { - compatible = "silergy,syr827"; - fcs,suspend-voltage-selector = <1>; - reg = <0x40>; - regulator-name = "vdd_cpu"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_sys>; - }; - - vdd_gpu: syr828@41 { - compatible = "silergy,syr828"; - fcs,suspend-voltage-selector = <1>; - reg = <0x41>; - regulator-name = "vdd_gpu"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - vin-supply = <&vcc_sys>; - }; - - hym8563@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - - interrupt-parent = <&gpio0>; - interrupts = ; - - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int>; - - #clock-cells = <0>; - clock-output-names = "xin32k"; - }; - - act8846: act8846@5a { - compatible = "active-semi,act8846"; - reg = <0x5a>; - status = "okay"; - - vp1-supply = <&vcc_sys>; - vp2-supply = <&vcc_sys>; - vp3-supply = <&vcc_sys>; - vp4-supply = <&vcc_sys>; - inl1-supply = <&vcc_io>; - inl2-supply = <&vcc_sys>; - inl3-supply = <&vcc_20>; - - regulators { - vcc_ddr: REG1 { - regulator-name = "VCC_DDR"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - vcc_io: REG2 { - regulator-name = "VCC_IO"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_log: REG3 { - regulator-name = "VDD_LOG"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - }; - - vcc_20: REG4 { - regulator-name = "VCC_20"; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - regulator-always-on; - }; - - vccio_sd: REG5 { - regulator-name = "VCCIO_SD"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd10_lcd: REG6 { - regulator-name = "VDD10_LCD"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - vcca_codec: REG7 { - regulator-name = "VCCA_CODEC"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vcc_tp: REG8 { - regulator-name = "VCCA_TP"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vccio_pmu: REG9 { - regulator-name = "VCCIO_PMU"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_10: REG10 { - regulator-name = "VDD_10"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - vcc_18: REG11 { - regulator-name = "VCC_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vcc18_lcd: REG12 { - regulator-name = "VCC18_LCD"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - }; - }; -}; - -&panel { - power-supply = <&vcc_lcd>; -}; - -&pinctrl { - lcd { - lcd_en: lcd-en { - rockchip,pins = <7 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - wifi { - wifi_pwr: wifi-pwr { - rockchip,pins = <7 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/rk3288-evb-rk808.dts b/sys/gnu/dts/arm/rk3288-evb-rk808.dts deleted file mode 100644 index 16788209625..00000000000 --- a/sys/gnu/dts/arm/rk3288-evb-rk808.dts +++ /dev/null @@ -1,201 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -/dts-v1/; -#include "rk3288-evb.dtsi" - -/ { - compatible = "rockchip,rk3288-evb-rk808", "rockchip,rk3288"; -}; - -&i2c0 { - clock-frequency = <400000>; - - rk808: pmic@1b { - compatible = "rockchip,rk808"; - reg = <0x1b>; - interrupt-parent = <&gpio0>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int &global_pwroff>; - rockchip,system-power-controller; - wakeup-source; - #clock-cells = <1>; - clock-output-names = "xin32k", "rk808-clkout2"; - - vcc1-supply = <&vcc_sys>; - vcc2-supply = <&vcc_sys>; - vcc3-supply = <&vcc_sys>; - vcc4-supply = <&vcc_sys>; - vcc6-supply = <&vcc_sys>; - vcc7-supply = <&vcc_sys>; - vcc8-supply = <&vcc_18>; - vcc9-supply = <&vcc_io>; - vcc10-supply = <&vcc_io>; - vcc11-supply = <&vcc_sys>; - vcc12-supply = <&vcc_io>; - vddio-supply = <&vccio_pmu>; - - regulators { - vdd_cpu: DCDC_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-name = "vdd_arm"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_gpu: DCDC_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1250000>; - regulator-name = "vdd_gpu"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc_ddr"; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_io: DCDC_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc_io"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vccio_pmu: LDO_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vccio_pmu"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc_tp: LDO_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc_tp"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_10: LDO_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-name = "vdd_10"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vcc18_lcd: LDO_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc18_lcd"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vccio_sd: LDO_REG5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vccio_sd"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vdd10_lcd: LDO_REG6 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-name = "vdd10_lcd"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vcc_18: LDO_REG7 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc_18"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcca_codec: LDO_REG8 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcca_codec"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc_wl: SWITCH_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc_wl"; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_lcd: SWITCH_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc_lcd"; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - }; - }; -}; - -&panel { - power-supply = <&vcc_lcd>; -}; diff --git a/sys/gnu/dts/arm/rk3288-evb.dtsi b/sys/gnu/dts/arm/rk3288-evb.dtsi deleted file mode 100644 index 018802df4c0..00000000000 --- a/sys/gnu/dts/arm/rk3288-evb.dtsi +++ /dev/null @@ -1,403 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -#include -#include -#include "rk3288.dtsi" - -/ { - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; - - adc-keys { - compatible = "adc-keys"; - io-channels = <&saradc 1>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1800000>; - - button-up { - label = "Volume Up"; - linux,code = ; - press-threshold-microvolt = <100000>; - }; - - button-down { - label = "Volume Down"; - linux,code = ; - press-threshold-microvolt = <300000>; - }; - - menu { - label = "Menu"; - linux,code = ; - press-threshold-microvolt = <640000>; - }; - - esc { - label = "Esc"; - linux,code = ; - press-threshold-microvolt = <1000000>; - }; - - home { - label = "Home"; - linux,code = ; - press-threshold-microvolt = <1300000>; - }; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - brightness-levels = < - 0 1 2 3 4 5 6 7 - 8 9 10 11 12 13 14 15 - 16 17 18 19 20 21 22 23 - 24 25 26 27 28 29 30 31 - 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 - 48 49 50 51 52 53 54 55 - 56 57 58 59 60 61 62 63 - 64 65 66 67 68 69 70 71 - 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 - 88 89 90 91 92 93 94 95 - 96 97 98 99 100 101 102 103 - 104 105 106 107 108 109 110 111 - 112 113 114 115 116 117 118 119 - 120 121 122 123 124 125 126 127 - 128 129 130 131 132 133 134 135 - 136 137 138 139 140 141 142 143 - 144 145 146 147 148 149 150 151 - 152 153 154 155 156 157 158 159 - 160 161 162 163 164 165 166 167 - 168 169 170 171 172 173 174 175 - 176 177 178 179 180 181 182 183 - 184 185 186 187 188 189 190 191 - 192 193 194 195 196 197 198 199 - 200 201 202 203 204 205 206 207 - 208 209 210 211 212 213 214 215 - 216 217 218 219 220 221 222 223 - 224 225 226 227 228 229 230 231 - 232 233 234 235 236 237 238 239 - 240 241 242 243 244 245 246 247 - 248 249 250 251 252 253 254 255>; - default-brightness-level = <128>; - enable-gpios = <&gpio7 RK_PA2 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&bl_en>; - pwms = <&pwm0 0 1000000 PWM_POLARITY_INVERTED>; - }; - - ext_gmac: external-gmac-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "ext_gmac"; - #clock-cells = <0>; - }; - - panel: panel { - compatible = "lg,lp079qx1-sp0v"; - backlight = <&backlight>; - enable-gpios = <&gpio7 RK_PA4 GPIO_ACTIVE_HIGH>; - pinctrl-0 = <&lcd_cs>; - - ports { - panel_in: port { - panel_in_edp: endpoint { - remote-endpoint = <&edp_out_panel>; - }; - }; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - - pinctrl-names = "default"; - pinctrl-0 = <&pwrbtn>; - - power { - gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "GPIO Key Power"; - linux,input-type = <1>; - wakeup-source; - debounce-interval = <100>; - }; - }; - - /* This turns on USB vbus for both host0 (ehci) and host1 (dwc2) */ - vcc_host: vcc-host-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&host_vbus_drv>; - regulator-name = "vcc_host"; - regulator-always-on; - regulator-boot-on; - }; - - vcc_phy: vcc-phy-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <ð_phy_pwr>; - regulator-name = "vcc_phy"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - vcc_sys: vsys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - /* - * NOTE: vcc_sd isn't hooked up on v1.0 boards where power comes from - * vcc_io directly. Those boards won't be able to power cycle SD cards - * but it shouldn't hurt to toggle this pin there anyway. - */ - vcc_sd: sdmmc-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio7 RK_PB3 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_pwr>; - regulator-name = "vcc_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <100000>; - vin-supply = <&vcc_io>; - }; -}; - -&cpu0 { - cpu0-supply = <&vdd_cpu>; -}; - -&edp { - force-hpd; - status = "okay"; - - ports { - edp_out: port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - edp_out_panel: endpoint@0 { - reg = <0>; - remote-endpoint = <&panel_in_edp>; - }; - }; - }; -}; - -&edp_phy { - status = "okay"; -}; - -&emmc { - bus-width = <8>; - cap-mmc-highspeed; - disable-wp; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>; - status = "okay"; -}; - -&saradc { - vref-supply = <&vcc_18>; - status = "okay"; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - card-detect-delay = <200>; - disable-wp; /* wp not hooked up */ - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; - status = "okay"; - vmmc-supply = <&vcc_sd>; - vqmmc-supply = <&vccio_sd>; -}; - -&gmac { - phy-supply = <&vcc_phy>; - phy-mode = "rgmii"; - clock_in_out = "input"; - snps,reset-gpio = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 1000000>; - assigned-clocks = <&cru SCLK_MAC>; - assigned-clock-parents = <&ext_gmac>; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - tx_delay = <0x30>; - rx_delay = <0x10>; - status = "ok"; -}; - -&gpu { - mali-supply = <&vdd_gpu>; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c5>; - status = "okay"; -}; - -&i2c0 { - status = "okay"; -}; - -&i2c5 { - status = "okay"; -}; - -&wdt { - status = "okay"; -}; - -&pwm0 { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&uart4 { - status = "okay"; -}; - -&tsadc { - rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ - rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ - status = "okay"; -}; - -&pinctrl { - pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma { - drive-strength = <8>; - }; - - pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma { - bias-pull-up; - drive-strength = <8>; - }; - - backlight { - bl_en: bl-en { - rockchip,pins = <7 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - buttons { - pwrbtn: pwrbtn { - rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - lcd { - lcd_cs: lcd-cs { - rockchip,pins = <7 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - pmic_int: pmic-int { - rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - sdmmc { - /* - * Default drive strength isn't enough to achieve even - * high-speed mode on EVB board so bump up to 8ma. - */ - sdmmc_bus4: sdmmc-bus4 { - rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up_drv_8ma>, - <6 RK_PC1 1 &pcfg_pull_up_drv_8ma>, - <6 RK_PC2 1 &pcfg_pull_up_drv_8ma>, - <6 RK_PC3 1 &pcfg_pull_up_drv_8ma>; - }; - - sdmmc_clk: sdmmc-clk { - rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none_drv_8ma>; - }; - - sdmmc_cmd: sdmmc-cmd { - rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up_drv_8ma>; - }; - - sdmmc_pwr: sdmmc-pwr { - rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb { - host_vbus_drv: host-vbus-drv { - rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - eth_phy { - eth_phy_pwr: eth-phy-pwr { - rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&usbphy { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host1 { - status = "okay"; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&vopl { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/rk3288-firefly-beta.dts b/sys/gnu/dts/arm/rk3288-firefly-beta.dts deleted file mode 100644 index 135e8832141..00000000000 --- a/sys/gnu/dts/arm/rk3288-firefly-beta.dts +++ /dev/null @@ -1,34 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2014, 2015 FUKAUMI Naoki - */ - -/dts-v1/; -#include "rk3288-firefly.dtsi" - -/ { - model = "Firefly-RK3288 Beta"; - compatible = "firefly,firefly-rk3288-beta", "rockchip,rk3288"; -}; - -&ir { - gpios = <&gpio7 RK_PA5 GPIO_ACTIVE_LOW>; -}; - -&pinctrl { - act8846 { - pmic_vsel: pmic-vsel { - rockchip,pins = <7 RK_PA1 RK_FUNC_GPIO &pcfg_output_low>; - }; - }; - - ir { - ir_int: ir-int { - rockchip,pins = <7 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; -}; - -&pwm0 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/rk3288-firefly-reload-core.dtsi b/sys/gnu/dts/arm/rk3288-firefly-reload-core.dtsi deleted file mode 100644 index 61435d8ee37..00000000000 --- a/sys/gnu/dts/arm/rk3288-firefly-reload-core.dtsi +++ /dev/null @@ -1,274 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device tree file for Firefly Rockchip RK3288 Core board - * Copyright (c) 2016 Randy Li - */ - -#include -#include "rk3288.dtsi" - -/ { - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; - - ext_gmac: external-gmac-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <125000000>; - clock-output-names = "ext_gmac"; - }; - - - vcc_flash: flash-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_flash"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_io>; - }; -}; - -&cpu0 { - cpu0-supply = <&vdd_cpu>; -}; - -&emmc { - bus-width = <8>; - cap-mmc-highspeed; - disable-wp; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_pwr>, <&emmc_bus8>; - vmmc-supply = <&vcc_io>; - vqmmc-supply = <&vcc_flash>; - status = "okay"; -}; - -&gmac { - assigned-clocks = <&cru SCLK_MAC>; - assigned-clock-parents = <&ext_gmac>; - clock_in_out = "input"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>, <&phy_rst>, <&phy_pmeb>, <&phy_int>; - phy-supply = <&vcc_lan>; - phy-mode = "rgmii"; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 1000000>; - snps,reset-gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_LOW>; - tx_delay = <0x30>; - rx_delay = <0x10>; - status = "ok"; -}; - -&i2c0 { - clock-frequency = <400000>; - status = "okay"; - - vdd_cpu: syr827@40 { - compatible = "silergy,syr827"; - fcs,suspend-voltage-selector = <1>; - reg = <0x40>; - regulator-name = "vdd_cpu"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - regulator-enable-ramp-delay = <300>; - regulator-ramp-delay = <8000>; - vin-supply = <&vcc_sys>; - }; - - vdd_gpu: syr828@41 { - compatible = "silergy,syr828"; - fcs,suspend-voltage-selector = <1>; - reg = <0x41>; - regulator-name = "vdd_gpu"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - vin-supply = <&vcc_sys>; - }; - - act8846: act8846@5a { - compatible = "active-semi,act8846"; - reg = <0x5a>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_vsel>, <&pwr_hold>; - system-power-controller; - - vp1-supply = <&vcc_sys>; - vp2-supply = <&vcc_sys>; - vp3-supply = <&vcc_sys>; - vp4-supply = <&vcc_sys>; - inl1-supply = <&vcc_sys>; - inl2-supply = <&vcc_sys>; - inl3-supply = <&vcc_20>; - - regulators { - vcc_ddr: REG1 { - regulator-name = "vcc_ddr"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - vcc_io: REG2 { - regulator-name = "vcc_io"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_log: REG3 { - regulator-name = "vdd_log"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - vcc_20: REG4 { - regulator-name = "vcc_20"; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - regulator-always-on; - }; - - vccio_sd: REG5 { - regulator-name = "vccio_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vdd10_lcd: REG6 { - regulator-name = "vdd10_lcd"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - vcca_18: REG7 { - regulator-name = "vcca_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vcca_33: REG8 { - regulator-name = "vcca_33"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vcc_lan: REG9 { - regulator-name = "vcca_lan"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vdd_10: REG10 { - regulator-name = "vdd_10"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - vccio_wl: vcc_18: REG11 { - regulator-name = "vcc_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vcc18_lcd: REG12 { - regulator-name = "vcc18_lcd"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - }; - }; -}; - -&io_domains { - status = "okay"; - - audio-supply = <&vccio_wl>; - bb-supply = <&vcc_io>; - dvp-supply = <&dovdd_1v8>; - flash0-supply = <&vcc_flash>; - flash1-supply = <&vcc_lan>; - gpio30-supply = <&vcc_io>; - gpio1830-supply = <&vcc_io>; - lcdc-supply = <&vcc_io>; - sdcard-supply = <&vccio_sd>; - wifi-supply = <&vccio_wl>; -}; - -&pinctrl { - pcfg_output_high: pcfg-output-high { - output-high; - }; - - pcfg_output_low: pcfg-output-low { - output-low; - }; - - pcfg_pull_up_drv_12ma: pcfg-pull-up-drv-12ma { - bias-pull-up; - drive-strength = <12>; - }; - - act8846 { - pwr_hold: pwr-hold { - rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_output_high>; - }; - - pmic_vsel: pmic-vsel { - rockchip,pins = <7 RK_PB6 RK_FUNC_GPIO &pcfg_output_low>; - }; - }; - - gmac { - phy_int: phy-int { - rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - phy_pmeb: phy-pmeb { - rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - phy_rst: phy-rst { - rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_output_high>; - }; - }; -}; - -&tsadc { - rockchip,hw-tshut-mode = <0>; - rockchip,hw-tshut-polarity = <0>; - status = "okay"; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&vopl { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; -}; - -&wdt { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/rk3288-firefly-reload.dts b/sys/gnu/dts/arm/rk3288-firefly-reload.dts deleted file mode 100644 index 1574383fd2d..00000000000 --- a/sys/gnu/dts/arm/rk3288-firefly-reload.dts +++ /dev/null @@ -1,391 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device tree file for Firefly Rockchip RK3288 Core board - * Copyright (c) 2016 Randy Li - */ - -/dts-v1/; -#include "rk3288-firefly-reload-core.dtsi" - -/ { - model = "Firefly-RK3288-reload"; - compatible = "firefly,firefly-rk3288-reload", "rockchip,rk3288"; - - adc-keys { - compatible = "adc-keys"; - io-channels = <&saradc 1>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1800000>; - - button-recovery { - label = "Recovery"; - linux,code = ; - press-threshold-microvolt = <0>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - power { - wakeup-source; - gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; - label = "GPIO Power"; - linux,code = ; - pinctrl-names = "default"; - pinctrl-0 = <&pwr_key>; - }; - }; - - ir-receiver { - compatible = "gpio-ir-receiver"; - gpios = <&gpio7 RK_PA0 GPIO_ACTIVE_LOW>; - }; - - leds { - compatible = "gpio-leds"; - - power { - gpios = <&gpio8 RK_PA2 GPIO_ACTIVE_LOW>; - label = "firefly:blue:power"; - pinctrl-names = "default"; - pinctrl-0 = <&power_led>; - panic-indicator; - }; - - work { - gpios = <&gpio8 RK_PA1 GPIO_ACTIVE_LOW>; - label = "firefly:blue:user"; - linux,default-trigger = "rc-feedback"; - pinctrl-names = "default"; - pinctrl-0 = <&work_led>; - }; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&hym8563>; - clock-names = "ext_clock"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_enable>; - reset-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "SPDIF"; - simple-audio-card,dai-link@1 { /* S/PDIF - S/PDIF */ - cpu { sound-dai = <&spdif>; }; - codec { sound-dai = <&spdif_out>; }; - }; - }; - - spdif_out: spdif-out { - compatible = "linux,spdif-dit"; - #sound-dai-cells = <0>; - }; - - vcc_host_5v: usb-host-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&host_vbus_drv>; - regulator-name = "vcc_host_5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - vin-supply = <&vcc_5v>; - }; - - vcc_5v: vcc_sys: vsys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - vcc_sd: sdmmc-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio7 RK_PB3 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_pwr>; - regulator-name = "vcc_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <100000>; - vin-supply = <&vcc_io>; - }; - - vcc_otg_5v: usb-otg-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&otg_vbus_drv>; - regulator-name = "vcc_otg_5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - vin-supply = <&vcc_5v>; - }; - - dovdd_1v8: dovdd-1v8-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&dvp_pwr>; - regulator-name = "dovdd_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_io>; - }; - - vcc28_dvp: vcc28-dvp-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&dvp_pwr>; - regulator-name = "vcc28_dvp"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - vin-supply = <&vcc_io>; - }; - - af_28: af_28-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&dvp_pwr>; - regulator-name = "af_28"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - vin-supply = <&vcc_io>; - }; - - dvdd_1v2: af_28-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio7 RK_PB4 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&cif_pwr>; - regulator-name = "dvdd_1v2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - vin-supply = <&vcc_io>; - }; - - vbat_wl: wifi-regulator { - compatible = "regulator-fixed"; - regulator-name = "vbat_wl"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_io>; - }; -}; - -&hdmi { - ddc-i2c-bus = <&i2c5>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_cec_c0>; - status = "okay"; -}; - -&i2c0 { - hym8563: hym8563@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "xin32k"; - interrupt-parent = <&gpio7>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&rtc_int>; - }; -}; - -&i2c2 { - status = "okay"; - - codec: es8328@10 { - compatible = "everest,es8328"; - DVDD-supply = <&vcca_33>; - AVDD-supply = <&vcca_33>; - PVDD-supply = <&vcca_33>; - HPVDD-supply = <&vcca_33>; - clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>; - clock-names = "i2s_hclk", "i2s_clk"; - reg = <0x10>; - }; -}; - -&i2c5 { - status = "okay"; -}; - -&i2s { - status = "okay"; -}; - -&saradc { - status = "okay"; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - card-detect-delay = <200>; - disable-wp; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_cd>, <&sdmmc_bus4>; - vmmc-supply = <&vcc_sd>; - vqmmc-supply = <&vccio_sd>; - status = "okay"; -}; - -&sdio0 { - bus-width = <4>; - cap-sd-highspeed; - cap-sdio-irq; - mmc-pwrseq = <&sdio_pwrseq>; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&sdio0_bus4>, <&sdio0_cmd>, <&sdio0_clk>, <&sdio0_int>; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-ddr50; - vmmc-supply = <&vbat_wl>; - vqmmc-supply = <&vccio_wl>; - status = "okay"; -}; - -&spdif { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer>, <&uart0_cts>, <&uart0_rts>; - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; - -&usb_host1 { - pinctrl-names = "default"; - pinctrl-0 = <&usbhub_rst>; - status = "okay"; -}; - -&usb_otg { - status = "okay"; -}; - -&pinctrl { - ir { - ir_int: ir-int { - rockchip,pins = <7 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - dvp { - dvp_pwr: dvp-pwr { - rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - cif_pwr: cif-pwr { - rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - hym8563 { - rtc_int: rtc-int { - rockchip,pins = <7 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - keys { - pwr_key: pwr-key { - rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - leds { - power_led: power-led { - rockchip,pins = <8 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - work_led: work-led { - rockchip,pins = <8 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - sdmmc { - /* - * Default drive strength isn't enough to achieve even - * high-speed mode on firefly board so bump up to 12ma. - */ - sdmmc_bus4: sdmmc-bus4 { - rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up_drv_12ma>, - <6 RK_PC1 1 &pcfg_pull_up_drv_12ma>, - <6 RK_PC2 1 &pcfg_pull_up_drv_12ma>, - <6 RK_PC3 1 &pcfg_pull_up_drv_12ma>; - }; - - sdmmc_clk: sdmmc-clk { - rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none_12ma>; - }; - - sdmmc_cmd: sdmmc-cmd { - rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up_drv_12ma>; - }; - - sdmmc_pwr: sdmmc-pwr { - rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - sdio { - wifi_enable: wifi-enable { - rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb_host { - host_vbus_drv: host-vbus-drv { - rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - usbhub_rst: usbhub-rst { - rockchip,pins = <8 RK_PA3 RK_FUNC_GPIO &pcfg_output_high>; - }; - }; - - usb_otg { - otg_vbus_drv: otg-vbus-drv { - rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/rk3288-firefly.dts b/sys/gnu/dts/arm/rk3288-firefly.dts deleted file mode 100644 index 313459dab2e..00000000000 --- a/sys/gnu/dts/arm/rk3288-firefly.dts +++ /dev/null @@ -1,34 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2014, 2015 FUKAUMI Naoki - */ - -/dts-v1/; -#include "rk3288-firefly.dtsi" - -/ { - model = "Firefly-RK3288"; - compatible = "firefly,firefly-rk3288", "rockchip,rk3288"; -}; - -&ir { - gpios = <&gpio7 RK_PA0 GPIO_ACTIVE_LOW>; -}; - -&pinctrl { - act8846 { - pmic_vsel: pmic-vsel { - rockchip,pins = <7 RK_PB6 RK_FUNC_GPIO &pcfg_output_low>; - }; - }; - - ir { - ir_int: ir-int { - rockchip,pins = <7 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; -}; - -&pwm1 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/rk3288-firefly.dtsi b/sys/gnu/dts/arm/rk3288-firefly.dtsi deleted file mode 100644 index 5e0a19004e4..00000000000 --- a/sys/gnu/dts/arm/rk3288-firefly.dtsi +++ /dev/null @@ -1,574 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2014, 2015 FUKAUMI Naoki - */ - -#include -#include "rk3288.dtsi" - -/ { - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; - - adc-keys { - compatible = "adc-keys"; - io-channels = <&saradc 1>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1800000>; - - button-recovery { - label = "Recovery"; - linux,code = ; - press-threshold-microvolt = <0>; - }; - }; - - dovdd_1v8: dovdd-1v8-regulator { - compatible = "regulator-fixed"; - regulator-name = "dovdd_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc28_dvp>; - }; - - ext_gmac: external-gmac-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <125000000>; - clock-output-names = "ext_gmac"; - }; - - ir: ir-receiver { - compatible = "gpio-ir-receiver"; - pinctrl-names = "default"; - pinctrl-0 = <&ir_int>; - }; - - keys: gpio-keys { - compatible = "gpio-keys"; - - power { - wakeup-source; - gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; - label = "GPIO Power"; - linux,code = ; - pinctrl-names = "default"; - pinctrl-0 = <&pwr_key>; - }; - }; - - leds { - compatible = "gpio-leds"; - - work { - gpios = <&gpio8 RK_PA1 GPIO_ACTIVE_LOW>; - label = "firefly:blue:user"; - linux,default-trigger = "rc-feedback"; - pinctrl-names = "default"; - pinctrl-0 = <&work_led>; - }; - - power { - gpios = <&gpio8 RK_PA2 GPIO_ACTIVE_LOW>; - label = "firefly:green:power"; - linux,default-trigger = "default-on"; - pinctrl-names = "default"; - pinctrl-0 = <&power_led>; - }; - }; - - vbat_wl: vcc_sys: vsys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - vcc_sd: sdmmc-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio7 RK_PB3 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_pwr>; - regulator-name = "vcc_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <100000>; - vin-supply = <&vcc_io>; - }; - - vcc_flash: flash-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_flash"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_io>; - }; - - vcc_5v: usb-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_sys>; - }; - - vcc_host_5v: usb-host-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&host_vbus_drv>; - regulator-name = "vcc_host_5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - vin-supply = <&vcc_5v>; - }; - - vcc_otg_5v: usb-otg-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&otg_vbus_drv>; - regulator-name = "vcc_otg_5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - vin-supply = <&vcc_5v>; - }; - - /* - * A TT8142 creates both dovdd_1v8 and vcc28_dvp, controlled - * by the dvp_pwr pin. - */ - vcc28_dvp: vcc28-dvp-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&dvp_pwr>; - regulator-name = "vcc28_dvp"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - vin-supply = <&vcc_io>; - }; -}; - -&cpu0 { - cpu0-supply = <&vdd_cpu>; -}; - -&emmc { - bus-width = <8>; - cap-mmc-highspeed; - disable-wp; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_pwr>, <&emmc_bus8>; - vmmc-supply = <&vcc_io>; - vqmmc-supply = <&vcc_flash>; - status = "okay"; -}; - -&gmac { - assigned-clocks = <&cru SCLK_MAC>; - assigned-clock-parents = <&ext_gmac>; - clock_in_out = "input"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>, <&phy_rst>, <&phy_pmeb>, <&phy_int>; - phy-supply = <&vcc_lan>; - phy-mode = "rgmii"; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 1000000>; - snps,reset-gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_LOW>; - tx_delay = <0x30>; - rx_delay = <0x10>; - status = "ok"; -}; - -&gpu { - mali-supply = <&vdd_gpu>; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c5>; - status = "okay"; -}; - -&i2c0 { - clock-frequency = <400000>; - status = "okay"; - - vdd_cpu: syr827@40 { - compatible = "silergy,syr827"; - fcs,suspend-voltage-selector = <1>; - reg = <0x40>; - regulator-name = "vdd_cpu"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - regulator-enable-ramp-delay = <300>; - regulator-ramp-delay = <8000>; - vin-supply = <&vcc_sys>; - }; - - vdd_gpu: syr828@41 { - compatible = "silergy,syr828"; - fcs,suspend-voltage-selector = <1>; - reg = <0x41>; - regulator-name = "vdd_gpu"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - vin-supply = <&vcc_sys>; - }; - - hym8563: hym8563@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "xin32k"; - interrupt-parent = <&gpio7>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&rtc_int>; - }; - - act8846: act8846@5a { - compatible = "active-semi,act8846"; - reg = <0x5a>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_vsel>, <&pwr_hold>; - system-power-controller; - - vp1-supply = <&vcc_sys>; - vp2-supply = <&vcc_sys>; - vp3-supply = <&vcc_sys>; - vp4-supply = <&vcc_sys>; - inl1-supply = <&vcc_sys>; - inl2-supply = <&vcc_sys>; - inl3-supply = <&vcc_20>; - - regulators { - vcc_ddr: REG1 { - regulator-name = "vcc_ddr"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - vcc_io: REG2 { - regulator-name = "vcc_io"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_log: REG3 { - regulator-name = "vdd_log"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - vcc_20: REG4 { - regulator-name = "vcc_20"; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - regulator-always-on; - }; - - vccio_sd: REG5 { - regulator-name = "vccio_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd10_lcd: REG6 { - regulator-name = "vdd10_lcd"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - vcca_18: REG7 { - regulator-name = "vcca_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vcca_33: REG8 { - regulator-name = "vcca_33"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vcc_lan: REG9 { - regulator-name = "vcc_lan"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vdd_10: REG10 { - regulator-name = "vdd_10"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - vccio_wl: vcc_18: REG11 { - regulator-name = "vcc_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vcc18_lcd: REG12 { - regulator-name = "vcc18_lcd"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - }; - }; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c4 { - status = "okay"; -}; - -&i2c5 { - status = "okay"; -}; - -&io_domains { - status = "okay"; - - audio-supply = <&vcca_33>; - bb-supply = <&vcc_io>; - dvp-supply = <&dovdd_1v8>; - flash0-supply = <&vcc_flash>; - flash1-supply = <&vcc_lan>; - gpio30-supply = <&vcc_io>; - gpio1830-supply = <&vcc_io>; - lcdc-supply = <&vcc_io>; - sdcard-supply = <&vccio_sd>; - wifi-supply = <&vccio_wl>; -}; - -&pinctrl { - pcfg_output_high: pcfg-output-high { - output-high; - }; - - pcfg_output_low: pcfg-output-low { - output-low; - }; - - pcfg_pull_up_drv_12ma: pcfg-pull-up-drv-12ma { - bias-pull-up; - drive-strength = <12>; - }; - - act8846 { - pwr_hold: pwr-hold { - rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_output_high>; - }; - }; - - dvp { - dvp_pwr: dvp-pwr { - rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - gmac { - phy_int: phy-int { - rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - phy_pmeb: phy-pmeb { - rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - phy_rst: phy-rst { - rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_output_high>; - }; - }; - - hym8563 { - rtc_int: rtc-int { - rockchip,pins = <7 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - keys { - pwr_key: pwr-key { - rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - leds { - power_led: power-led { - rockchip,pins = <8 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - work_led: work-led { - rockchip,pins = <8 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - sdmmc { - /* - * Default drive strength isn't enough to achieve even - * high-speed mode on firefly board so bump up to 12ma. - */ - sdmmc_bus4: sdmmc-bus4 { - rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up_drv_12ma>, - <6 RK_PC1 1 &pcfg_pull_up_drv_12ma>, - <6 RK_PC2 1 &pcfg_pull_up_drv_12ma>, - <6 RK_PC3 1 &pcfg_pull_up_drv_12ma>; - }; - - sdmmc_clk: sdmmc-clk { - rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none_12ma>; - }; - - sdmmc_cmd: sdmmc-cmd { - rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up_drv_12ma>; - }; - - sdmmc_pwr: sdmmc-pwr { - rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb_host { - host_vbus_drv: host-vbus-drv { - rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - usbhub_rst: usbhub-rst { - rockchip,pins = <8 RK_PA3 RK_FUNC_GPIO &pcfg_output_high>; - }; - }; - - usb_otg { - otg_vbus_drv: otg-vbus-drv { - rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&saradc { - vref-supply = <&vcc_18>; - status = "okay"; -}; - -&sdio0 { - bus-width = <4>; - disable-wp; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&sdio0_bus4>, <&sdio0_cmd>, <&sdio0_clk>; - vmmc-supply = <&vbat_wl>; - vqmmc-supply = <&vccio_wl>; - status = "okay"; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - card-detect-delay = <200>; - disable-wp; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_cd>, <&sdmmc_bus4>; - vmmc-supply = <&vcc_sd>; - vqmmc-supply = <&vccio_sd>; - status = "okay"; -}; - -&spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi0_clk>, <&spi0_cs0>, <&spi0_tx>, <&spi0_rx>, <&spi0_cs1>; - status = "okay"; -}; - -&tsadc { - rockchip,hw-tshut-mode = <0>; - rockchip,hw-tshut-polarity = <0>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer>, <&uart0_cts>, <&uart0_rts>; - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; - -&usb_host1 { - pinctrl-names = "default"; - pinctrl-0 = <&usbhub_rst>; - status = "okay"; -}; - -&usb_otg { - status = "okay"; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&vopl { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; -}; - -&wdt { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/rk3288-miqi.dts b/sys/gnu/dts/arm/rk3288-miqi.dts deleted file mode 100644 index c41d012c885..00000000000 --- a/sys/gnu/dts/arm/rk3288-miqi.dts +++ /dev/null @@ -1,424 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Heiko Stuebner - */ - -/dts-v1/; -#include -#include "rk3288.dtsi" - -/ { - model = "mqmaker MiQi"; - compatible = "mqmaker,miqi", "rockchip,rk3288"; - - chosen { - stdout-path = "serial2:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; - - ext_gmac: external-gmac-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <125000000>; - clock-output-names = "ext_gmac"; - }; - - leds { - compatible = "gpio-leds"; - - work { - gpios = <&gpio7 RK_PA2 GPIO_ACTIVE_HIGH>; - label = "miqi:green:user"; - linux,default-trigger = "timer"; - }; - }; - - vcc_flash: flash-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_flash"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_io>; - }; - - vcc_host: usb-host-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&host_vbus_drv>; - regulator-name = "vcc_host"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - vin-supply = <&vcc_sys>; - }; - - vcc_sd: sdmmc-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio7 RK_PB3 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_pwr>; - regulator-name = "vcc_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <100000>; - vin-supply = <&vcc_io>; - }; - - vcc_sys: vsys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; -}; - -&cpu0 { - cpu0-supply = <&vdd_cpu>; -}; - -&emmc { - bus-width = <8>; - cap-mmc-highspeed; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_pwr>, <&emmc_bus8>; - vmmc-supply = <&vcc_io>; - vqmmc-supply = <&vcc_flash>; - status = "okay"; -}; - -&gmac { - assigned-clocks = <&cru SCLK_MAC>; - assigned-clock-parents = <&ext_gmac>; - clock_in_out = "input"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>, <&phy_rst>, <&phy_pmeb>, <&phy_int>; - phy-supply = <&vcc_lan>; - phy-mode = "rgmii"; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 1000000>; - snps,reset-gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_LOW>; - tx_delay = <0x30>; - rx_delay = <0x10>; - status = "ok"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c5>; - status = "okay"; -}; - -&i2c0 { - clock-frequency = <400000>; - status = "okay"; - - vdd_cpu: syr827@40 { - compatible = "silergy,syr827"; - fcs,suspend-voltage-selector = <1>; - reg = <0x40>; - regulator-name = "vdd_cpu"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - regulator-enable-ramp-delay = <300>; - regulator-ramp-delay = <8000>; - vin-supply = <&vcc_sys>; - }; - - vdd_gpu: syr828@41 { - compatible = "silergy,syr828"; - fcs,suspend-voltage-selector = <1>; - reg = <0x41>; - regulator-name = "vdd_gpu"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - vin-supply = <&vcc_sys>; - }; - - hym8563: hym8563@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "xin32k"; - }; - - act8846: act8846@5a { - compatible = "active-semi,act8846"; - reg = <0x5a>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_vsel>; - system-power-controller; - - vp1-supply = <&vcc_sys>; - vp2-supply = <&vcc_sys>; - vp3-supply = <&vcc_sys>; - vp4-supply = <&vcc_sys>; - inl1-supply = <&vcc_sys>; - inl2-supply = <&vcc_sys>; - inl3-supply = <&vcc_20>; - - regulators { - vcc_ddr: REG1 { - regulator-name = "vcc_ddr"; - regulator-always-on; - }; - - vcc_io: REG2 { - regulator-name = "vcc_io"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_log: REG3 { - regulator-name = "vdd_log"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - vcc_20: REG4 { - regulator-name = "vcc_20"; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - regulator-always-on; - }; - - vccio_sd: REG5 { - regulator-name = "vccio_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd10_lcd: REG6 { - regulator-name = "vdd10_lcd"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - vcca_18: REG7 { - regulator-name = "vcca_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vcca_33: REG8 { - regulator-name = "vcca_33"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vcc_lan: REG9 { - regulator-name = "vcc_lan"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vdd_10: REG10 { - regulator-name = "vdd_10"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - vcc_18: REG11 { - regulator-name = "vcc_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vcc18_lcd: REG12 { - regulator-name = "vcc18_lcd"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - }; - }; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c4 { - status = "okay"; -}; - -&i2c5 { - status = "okay"; -}; - -&io_domains { - status = "okay"; - - audio-supply = <&vcca_33>; - flash0-supply = <&vcc_flash>; - flash1-supply = <&vcc_lan>; - gpio30-supply = <&vcc_io>; - gpio1830-supply = <&vcc_io>; - lcdc-supply = <&vcc_io>; - sdcard-supply = <&vccio_sd>; - wifi-supply = <&vcc_18>; -}; - -&pinctrl { - pcfg_output_high: pcfg-output-high { - output-high; - }; - - pcfg_output_low: pcfg-output-low { - output-low; - }; - - pcfg_pull_up_drv_12ma: pcfg-pull-up-drv-12ma { - bias-pull-up; - drive-strength = <12>; - }; - - act8846 { - pmic_int: pmic-int { - rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - pmic_sleep: pmic-sleep { - rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_output_low>; - }; - - pmic_vsel: pmic-vsel { - rockchip,pins = <7 RK_PA1 RK_FUNC_GPIO &pcfg_output_low>; - }; - }; - - gmac { - phy_int: phy-int { - rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - phy_pmeb: phy-pmeb { - rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - phy_rst: phy-rst { - rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_output_high>; - }; - }; - - sdmmc { - /* - * Default drive strength isn't enough to achieve even - * high-speed mode on firefly board so bump up to 12ma. - */ - sdmmc_bus4: sdmmc-bus4 { - rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up_drv_12ma>, - <6 RK_PC1 1 &pcfg_pull_up_drv_12ma>, - <6 RK_PC2 1 &pcfg_pull_up_drv_12ma>, - <6 RK_PC3 1 &pcfg_pull_up_drv_12ma>; - }; - - sdmmc_clk: sdmmc-clk { - rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none_12ma>; - }; - - sdmmc_cmd: sdmmc-cmd { - rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up_drv_12ma>; - }; - - sdmmc_pwr: sdmmc-pwr { - rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb_host { - host_vbus_drv: host-vbus-drv { - rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&saradc { - vref-supply = <&vcc_18>; - status = "okay"; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - card-detect-delay = <200>; - disable-wp; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_cd>, <&sdmmc_bus4>; - vmmc-supply = <&vcc_sd>; - vqmmc-supply = <&vccio_sd>; - status = "okay"; -}; - -&tsadc { - rockchip,hw-tshut-mode = <0>; - rockchip,hw-tshut-polarity = <0>; - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; - -&usb_host1 { - status = "okay"; -}; - -&usb_otg { - /* - * The otg controller is the only system power source, - * so needs to always stay in device mode. - */ - dr_mode = "peripheral"; - status = "okay"; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&vopl { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; -}; - -&wdt { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/rk3288-phycore-rdk.dts b/sys/gnu/dts/arm/rk3288-phycore-rdk.dts deleted file mode 100644 index 1e33859de48..00000000000 --- a/sys/gnu/dts/arm/rk3288-phycore-rdk.dts +++ /dev/null @@ -1,264 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device tree file for Phytec PCM-947 carrier board - * Copyright (C) 2017 PHYTEC Messtechnik GmbH - * Author: Wadim Egorov - */ - -/dts-v1/; - -#include -#include -#include "rk3288-phycore-som.dtsi" - -/ { - model = "Phytec RK3288 PCM-947"; - compatible = "phytec,rk3288-pcm-947", "phytec,rk3288-phycore-som", "rockchip,rk3288"; - - user_buttons: user-buttons { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&user_button_pins>; - - button@0 { - label = "home"; - linux,code = ; - gpios = <&gpio8 0 GPIO_ACTIVE_HIGH>; - wakeup-source; - }; - - button@1 { - label = "menu"; - linux,code = ; - gpios = <&gpio8 3 GPIO_ACTIVE_HIGH>; - wakeup-source; - }; - }; - - vcc_host0_5v: usb-host0-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio2 13 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&host0_vbus_drv>; - regulator-name = "vcc_host0_5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - vin-supply = <&vdd_in_otg_out>; - }; - - vcc_host1_5v: usb-host1-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio2 0 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&host1_vbus_drv>; - regulator-name = "vcc_host1_5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - vin-supply = <&vdd_in_otg_out>; - }; - - vcc_otg_5v: usb-otg-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio2 12 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&otg_vbus_drv>; - regulator-name = "vcc_otg_5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - vin-supply = <&vdd_in_otg_out>; - }; -}; - -&gmac { - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&i2c1 { - status = "okay"; - - touchscreen@44 { - compatible = "st,stmpe811"; - reg = <0x44>; - }; - - adc@64 { - compatible = "maxim,max1037"; - reg = <0x64>; - }; - - i2c_rtc: rtc@68 { - compatible = "rv4162"; - reg = <0x68>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c_rtc_int>; - interrupt-parent = <&gpio5>; - interrupts = <10 0>; - }; -}; - -&i2c3 { - status = "okay"; - - i2c_eeprom_cb: eeprom@51 { - compatible = "atmel,24c32"; - reg = <0x51>; - pagesize = <32>; - }; -}; - -&i2c4 { - status = "okay"; - - /* PCA9533 - 4-bit LED dimmer */ - leddim: leddimmer@62 { - compatible = "nxp,pca9533"; - reg = <0x62>; - - led1 { - label = "red:user1"; - linux,default-trigger = "none"; - type = ; - }; - - led2 { - label = "green:user2"; - linux,default-trigger = "none"; - type = ; - }; - - led3 { - label = "blue:user3"; - linux,default-trigger = "none"; - type = ; - }; - - led4 { - label = "red:user4"; - linux,default-trigger = "none"; - type = ; - }; - }; -}; - -&i2c5 { - status = "okay"; -}; - -&pinctrl { - pcfg_pull_up_drv_12ma: pcfg-pull-up-drv-12ma { - bias-pull-up; - drive-strength = <12>; - }; - - buttons { - user_button_pins: user-button-pins { - /* button 1 */ - rockchip,pins = <8 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>, - /* button 2 */ - <8 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - rv4162 { - i2c_rtc_int: i2c-rtc-int { - rockchip,pins = <5 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - sdmmc { - /* - * Default drive strength isn't enough to achieve even - * high-speed mode on pcm-947 board so bump up to 12 mA. - */ - sdmmc_bus4: sdmmc-bus4 { - rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up_drv_12ma>, - <6 RK_PC1 1 &pcfg_pull_up_drv_12ma>, - <6 RK_PC2 1 &pcfg_pull_up_drv_12ma>, - <6 RK_PC3 1 &pcfg_pull_up_drv_12ma>; - }; - - sdmmc_clk: sdmmc-clk { - rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none_12ma>; - }; - - sdmmc_cmd: sdmmc-cmd { - rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up_drv_12ma>; - }; - - sdmmc_pwr: sdmmc-pwr { - rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - touchscreen { - ts_irq_pin: ts-irq-pin { - rockchip,pins = <5 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb_host { - host0_vbus_drv: host0-vbus-drv { - rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - host1_vbus_drv: host1-vbus-drv { - rockchip,pins = <2 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb_otg { - otg_vbus_drv: otg-vbus-drv { - rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - card-detect-delay = <200>; - disable-wp; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-sdr104; - vmmc-supply = <&vdd_sd>; - vqmmc-supply = <&vdd_io_sd>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host1 { - status = "okay"; -}; - -&usb_otg { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/rk3288-phycore-som.dtsi b/sys/gnu/dts/arm/rk3288-phycore-som.dtsi deleted file mode 100644 index 77a47b9b756..00000000000 --- a/sys/gnu/dts/arm/rk3288-phycore-som.dtsi +++ /dev/null @@ -1,439 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device tree file for Phytec phyCORE-RK3288 SoM - * Copyright (C) 2017 PHYTEC Messtechnik GmbH - * Author: Wadim Egorov - */ - -#include -#include "rk3288.dtsi" - -/ { - model = "Phytec RK3288 phyCORE"; - compatible = "phytec,rk3288-phycore-som", "rockchip,rk3288"; - - /* - * Set the minimum memory size here and - * let the bootloader set the real size. - */ - memory { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x8000000>; - }; - - aliases { - rtc0 = &i2c_rtc; - rtc1 = &rk818; - }; - - ext_gmac: external-gmac-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <125000000>; - clock-output-names = "ext_gmac"; - }; - - leds: user-leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&user_led>; - - user { - label = "green_led"; - gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - default-state = "keep"; - }; - }; - - vdd_emmc_io: vdd-emmc-io { - compatible = "regulator-fixed"; - regulator-name = "vdd_emmc_io"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vdd_3v3_io>; - }; - - vdd_in_otg_out: vdd-in-otg-out { - compatible = "regulator-fixed"; - regulator-name = "vdd_in_otg_out"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - vdd_misc_1v8: vdd-misc-1v8 { - compatible = "regulator-fixed"; - regulator-name = "vdd_misc_1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; -}; - -&emmc { - status = "okay"; - bus-width = <8>; - cap-mmc-highspeed; - disable-wp; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>; - vmmc-supply = <&vdd_3v3_io>; - vqmmc-supply = <&vdd_emmc_io>; -}; - -&gmac { - assigned-clocks = <&cru SCLK_MAC>; - assigned-clock-parents = <&ext_gmac>; - clock_in_out = "input"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins &phy_rst &phy_int>; - phy-handle = <&phy0>; - phy-supply = <&vdd_eth_2v5>; - phy-mode = "rgmii-id"; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 1000000>; - snps,reset-gpio = <&gpio4 8 GPIO_ACTIVE_HIGH>; - tx_delay = <0x0>; - rx_delay = <0x0>; - - mdio0 { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - phy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - interrupt-parent = <&gpio4>; - interrupts = <2 IRQ_TYPE_EDGE_FALLING>; - ti,rx-internal-delay = ; - ti,tx-internal-delay = ; - ti,fifo-depth = ; - enet-phy-lane-no-swap; - ti,clk-output-sel = ; - }; - }; -}; - -&hdmi { - ddc-i2c-bus = <&i2c5>; -}; - -&io_domains { - status = "okay"; - sdcard-supply = <&vdd_io_sd>; - flash0-supply = <&vdd_emmc_io>; - flash1-supply = <&vdd_misc_1v8>; - gpio1830-supply = <&vdd_3v3_io>; - gpio30-supply = <&vdd_3v3_io>; - bb-supply = <&vdd_3v3_io>; - dvp-supply = <&vdd_3v3_io>; - lcdc-supply = <&vdd_3v3_io>; - wifi-supply = <&vdd_3v3_io>; - audio-supply = <&vdd_3v3_io>; -}; - -&i2c0 { - status = "okay"; - clock-frequency = <400000>; - - rk818: pmic@1c { - compatible = "rockchip,rk818"; - reg = <0x1c>; - interrupt-parent = <&gpio0>; - interrupts = <4 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int>; - rockchip,system-power-controller; - wakeup-source; - #clock-cells = <1>; - - vcc1-supply = <&vdd_sys>; - vcc2-supply = <&vdd_sys>; - vcc3-supply = <&vdd_sys>; - vcc4-supply = <&vdd_sys>; - boost-supply = <&vdd_in_otg_out>; - vcc6-supply = <&vdd_sys>; - vcc7-supply = <&vdd_misc_1v8>; - vcc8-supply = <&vdd_misc_1v8>; - vcc9-supply = <&vdd_3v3_io>; - vddio-supply = <&vdd_3v3_io>; - - regulators { - vdd_log: DCDC_REG1 { - regulator-name = "vdd_log"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_gpu: DCDC_REG2 { - regulator-name = "vdd_gpu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1250000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vdd_3v3_io: DCDC_REG4 { - regulator-name = "vdd_3v3_io"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vdd_sys: DCDC_BOOST { - regulator-name = "vdd_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <5000000>; - }; - }; - - /* vcc9 */ - vdd_sd: SWITCH_REG { - regulator-name = "vdd_sd"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - /* vcc6 */ - vdd_eth_2v5: LDO_REG2 { - regulator-name = "vdd_eth_2v5"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <2500000>; - }; - }; - - /* vcc7 */ - vdd_1v0: LDO_REG3 { - regulator-name = "vdd_1v0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - /* vcc8 */ - vdd_1v8_lcd_ldo: LDO_REG4 { - regulator-name = "vdd_1v8_lcd_ldo"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - /* vcc8 */ - vdd_1v0_lcd: LDO_REG6 { - regulator-name = "vdd_1v0_lcd"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - /* vcc7 */ - vdd_1v8_ldo: LDO_REG7 { - regulator-name = "vdd_1v8_ldo"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - /* vcc9 */ - vdd_io_sd: LDO_REG9 { - regulator-name = "vdd_io_sd"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; - - /* M24C32-D */ - i2c_eeprom: eeprom@50 { - compatible = "atmel,24c32"; - reg = <0x50>; - pagesize = <32>; - }; - - vdd_cpu: regulator@60 { - compatible = "fcs,fan53555"; - reg = <0x60>; - fcs,suspend-voltage-selector = <1>; - regulator-always-on; - regulator-boot-on; - regulator-enable-ramp-delay = <300>; - regulator-name = "vdd_cpu"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1430000>; - regulator-ramp-delay = <8000>; - vin-supply = <&vdd_sys>; - }; -}; - -&pinctrl { - pcfg_output_high: pcfg-output-high { - output-high; - }; - - emmc { - /* - * We run eMMC at max speed; bump up drive strength. - * We also have external pulls, so disable the internal ones. - */ - emmc_clk: emmc-clk { - rockchip,pins = <3 RK_PC2 2 &pcfg_pull_none_12ma>; - }; - - emmc_cmd: emmc-cmd { - rockchip,pins = <3 RK_PC0 2 &pcfg_pull_none_12ma>; - }; - - emmc_bus8: emmc-bus8 { - rockchip,pins = <3 RK_PA0 2 &pcfg_pull_none_12ma>, - <3 RK_PA1 2 &pcfg_pull_none_12ma>, - <3 RK_PA2 2 &pcfg_pull_none_12ma>, - <3 RK_PA3 2 &pcfg_pull_none_12ma>, - <3 RK_PA4 2 &pcfg_pull_none_12ma>, - <3 RK_PA5 2 &pcfg_pull_none_12ma>, - <3 RK_PA6 2 &pcfg_pull_none_12ma>, - <3 RK_PA7 2 &pcfg_pull_none_12ma>; - }; - }; - - gmac { - phy_int: phy-int { - rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - phy_rst: phy-rst { - rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_output_high>; - }; - }; - - leds { - user_led: user-led { - rockchip,pins = <7 RK_PA2 RK_FUNC_GPIO &pcfg_output_high>; - }; - }; - - pmic { - pmic_int: pmic-int { - rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - /* Pin for switching state between sleep and non-sleep state */ - pmic_sleep: pmic-sleep { - rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; -}; - -&pwm1 { - status = "okay"; -}; - -&saradc { - status = "okay"; - vref-supply = <&vdd_1v8_ldo>; -}; - -&spi2 { - status = "okay"; - - serial_flash: flash@0 { - compatible = "micron,n25q128a13", "jedec,spi-nor"; - reg = <0x0>; - spi-max-frequency = <50000000>; - m25p,fast-read; - #address-cells = <1>; - #size-cells = <1>; - status = "okay"; - }; -}; - -&tsadc { - status = "okay"; - rockchip,hw-tshut-mode = <0>; - rockchip,hw-tshut-polarity = <0>; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&vopl { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; -}; - -&wdt { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/rk3288-popmetal.dts b/sys/gnu/dts/arm/rk3288-popmetal.dts deleted file mode 100644 index 6a51940398b..00000000000 --- a/sys/gnu/dts/arm/rk3288-popmetal.dts +++ /dev/null @@ -1,501 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2014, 2015 Andy Yan - */ - -/dts-v1/; -#include -#include "rk3288.dtsi" - -/ { - model = "PopMetal-RK3288"; - compatible = "chipspark,popmetal-rk3288", "rockchip,rk3288"; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; - - ext_gmac: external-gmac-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "ext_gmac"; - #clock-cells = <0>; - }; - - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - - pinctrl-names = "default"; - pinctrl-0 = <&pwrbtn>; - - power { - gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "GPIO Key Power"; - linux,input-type = <1>; - wakeup-source; - debounce-interval = <100>; - }; - }; - - ir: ir-receiver { - compatible = "gpio-ir-receiver"; - gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&ir_int>; - }; - - vcc_flash: flash-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_flash"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_io>; - }; - - vcc_sd: sdmmc-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio7 RK_PB3 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_pwr>; - regulator-name = "vcc_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <100000>; - vin-supply = <&vcc_io>; - }; - - vcc_sys: vsys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - /* - * A PT5128 creates both dovdd_1v8 and vcc28_dvp, controlled - * by the dvp_pwr pin. - */ - vcc18_dvp: vcc18-dvp-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc18-dvp"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc28_dvp>; - }; - - vcc28_dvp: vcc28-dvp-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&dvp_pwr>; - regulator-name = "vcc28_dvp"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - vin-supply = <&vcc_io>; - }; -}; - -&cpu0 { - cpu0-supply = <&vdd_cpu>; -}; - -&emmc { - bus-width = <8>; - cap-mmc-highspeed; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>; - vmmc-supply = <&vcc_io>; - vqmmc-supply = <&vcc_flash>; - status = "okay"; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - card-detect-delay = <200>; - disable-wp; /* wp not hooked up */ - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-sdr104; - vmmc-supply = <&vcc_sd>; - vqmmc-supply = <&vccio_sd>; - status = "okay"; -}; - -&gmac { - phy-supply = <&vcc_lan>; - phy-mode = "rgmii"; - clock_in_out = "input"; - snps,reset-gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 1000000>; - assigned-clocks = <&cru SCLK_MAC>; - assigned-clock-parents = <&ext_gmac>; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - tx_delay = <0x30>; - rx_delay = <0x10>; - status = "ok"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c5>; - status = "okay"; -}; - -&i2c0 { - status = "okay"; - clock-frequency = <400000>; - - rk808: pmic@1b { - compatible = "rockchip,rk808"; - reg = <0x1b>; - interrupt-parent = <&gpio0>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int &global_pwroff>; - rockchip,system-power-controller; - wakeup-source; - #clock-cells = <1>; - clock-output-names = "xin32k", "rk808-clkout2"; - - vcc1-supply = <&vcc_sys>; - vcc2-supply = <&vcc_sys>; - vcc3-supply = <&vcc_sys>; - vcc4-supply = <&vcc_sys>; - vcc6-supply = <&vcc_sys>; - vcc7-supply = <&vcc_sys>; - vcc8-supply = <&vcc_18>; - vcc9-supply = <&vcc_io>; - vcc10-supply = <&vcc_io>; - vcc11-supply = <&vcc_sys>; - vcc12-supply = <&vcc_io>; - vddio-supply = <&vcc_io>; - - regulators { - vdd_cpu: DCDC_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-name = "vdd_arm"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_gpu: DCDC_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1250000>; - regulator-name = "vdd_gpu"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc_ddr"; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_io: DCDC_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc_io"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc_lan: LDO_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc_lan"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vccio_sd: LDO_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vccio_sd"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_10: LDO_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-name = "vdd_10"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vcc18_lcd: LDO_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc18_lcd"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - ldo5: LDO_REG5 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-name = "ldo5"; - }; - - vdd10_lcd: LDO_REG6 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-name = "vdd10_lcd"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vcc_18: LDO_REG7 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc_18"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcca_33: LDO_REG8 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcca_33"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vccio_wl: SWITCH_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vccio_wl"; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_lcd: SWITCH_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc_lcd"; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - }; - }; -}; - -&i2c1 { - status = "okay"; - clock-frequency = <400000>; - - ak8963: ak8963@d { - compatible = "asahi-kasei,ak8975"; - reg = <0x0d>; - interrupt-parent = <&gpio8>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&comp_int>; - vdd-supply = <&vcc_io>; - vid-supply = <&vcc_io>; - }; - - l3g4200d: l3g4200d@69 { - compatible = "st,l3g4200d-gyro"; - st,drdy-int-pin = <2>; - reg = <0x69>; - vdd-supply = <&vcc_io>; - vddio-supply = <&vcc_io>; - }; - - mma8452: mma8452@1d { - compatible = "fsl,mma8452"; - reg = <0x1d>; - interrupt-parent = <&gpio8>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&gsensor_int>; - }; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c3 { - status = "okay"; -}; - -&i2c4 { - status = "okay"; -}; - -&i2c5 { - status = "okay"; -}; - -&io_domains { - status = "okay"; - - audio-supply = <&vcca_33>; - bb-supply = <&vcc_io>; - dvp-supply = <&vcc18_dvp>; - flash0-supply = <&vcc_flash>; - flash1-supply = <&vcc_lan>; - gpio30-supply = <&vcc_io>; - gpio1830-supply = <&vcc_io>; - lcdc-supply = <&vcc_io>; - sdcard-supply = <&vccio_sd>; - wifi-supply = <&vccio_wl>; -}; - -&pinctrl { - ak8963 { - comp_int: comp-int { - rockchip,pins = <8 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - buttons { - pwrbtn: pwrbtn { - rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - dvp { - dvp_pwr: dvp-pwr { - rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - ir { - ir_int: ir-int { - rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - mma8452 { - gsensor_int: gsensor-int { - rockchip,pins = <8 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - pmic { - pmic_int: pmic-int { - rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - sdmmc { - sdmmc_pwr: sdmmc-pwr { - rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&tsadc { - rockchip,hw-tshut-mode = <0>; - rockchip,hw-tshut-polarity = <0>; - status = "okay"; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&vopl { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&uart4 { - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; - -&usb_otg { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/rk3288-r89.dts b/sys/gnu/dts/arm/rk3288-r89.dts deleted file mode 100644 index a6ffc381aba..00000000000 --- a/sys/gnu/dts/arm/rk3288-r89.dts +++ /dev/null @@ -1,387 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2015 Heiko Stuebner - */ - -/dts-v1/; -#include -#include -#include "rk3288.dtsi" - -/ { - compatible = "netxeon,r89", "rockchip,rk3288"; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; - - ext_gmac: external-gmac-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "ext_gmac"; - #clock-cells = <0>; - }; - - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - - pinctrl-names = "default"; - pinctrl-0 = <&pwrbtn>; - - power { - gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "GPIO Key Power"; - linux,input-type = <1>; - wakeup-source; - debounce-interval = <100>; - }; - }; - - ir: ir-receiver { - compatible = "gpio-ir-receiver"; - gpios = <&gpio7 RK_PA0 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&ir_int>; - }; - - vcc_host: vcc-host-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&host_vbus_drv>; - regulator-name = "vcc_host"; - regulator-always-on; - regulator-boot-on; - }; - - vcc_otg: vcc-otg-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&otg_vbus_drv>; - regulator-name = "vcc_otg"; - regulator-always-on; - regulator-boot-on; - }; - - vcc_sdmmc: sdmmc-regulator { - compatible = "regulator-fixed"; - regulator-name = "sdmmc-supply"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio7 RK_PB3 GPIO_ACTIVE_LOW>; - startup-delay-us = <100000>; - vin-supply = <&vcc_io>; - }; - - vcc_sys: sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "sys-supply"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; -}; - -&cpu0 { - cpu0-supply = <&vdd_cpu>; -}; - -&gmac { - phy-supply = <&vcc_lan>; - phy-mode = "rgmii"; - clock_in_out = "input"; - snps,reset-gpio = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 1000000>; - assigned-clocks = <&cru SCLK_MAC>; - assigned-clock-parents = <&ext_gmac>; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - tx_delay = <0x30>; - rx_delay = <0x10>; - status = "ok"; -}; - -&hdmi { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - vdd_cpu: pmic@40 { - compatible = "silergy,syr827"; - reg = <0x40>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "VDD_CPU"; - regulator-enable-ramp-delay = <300>; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <8000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_sys>; - }; - - vdd_gpu: pmic@41 { - compatible = "silergy,syr828"; - reg = <0x41>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "VDD_GPU"; - regulator-enable-ramp-delay = <300>; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <8000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_sys>; - }; - - rtc@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; - clock-output-names = "xin32k"; - interrupt-parent = <&gpio0>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int>; - }; - - act8846: pmic@5a { - compatible = "active-semi,act8846"; - reg = <0x5a>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_vsel>, <&pwr_hold>; - system-power-controller; - - regulators { - vcc_ddr: REG1 { - regulator-name = "VCC_DDR"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - vcc_io: REG2 { - regulator-name = "VCC_IO"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_log: REG3 { - regulator-name = "VDD_LOG"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - vcc_20: REG4 { - regulator-name = "VCC_20"; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - regulator-always-on; - }; - - vccio_sd: REG5 { - regulator-name = "VCCIO_SD"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd10_lcd: REG6 { - regulator-name = "VDD10_LCD"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - vcc_wl: REG7 { - regulator-name = "VCC_WL"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vcca_33: REG8 { - regulator-name = "VCCA_33"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vcc_lan: REG9 { - regulator-name = "VCC_LAN"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_10: REG10 { - regulator-name = "VDD_10"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - vcc_18: REG11 { - regulator-name = "VCC_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vcc18_lcd: REG12 { - regulator-name = "VCC18_LCD"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - }; - }; -}; - -&i2c5 { - status = "okay"; -}; - -&pinctrl { - pcfg_output_high: pcfg-output-high { - output-high; - }; - - pcfg_output_low: pcfg-output-low { - output-low; - }; - - act8846 { - pmic_vsel: pmic-vsel { - rockchip,pins = <7 RK_PA1 RK_FUNC_GPIO &pcfg_output_low>; - }; - - pwr_hold: pwr-hold { - rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_output_high>; - }; - }; - - buttons { - pwrbtn: pwrbtn { - rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - ir { - ir_int: ir-int { - rockchip,pins = <7 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - pmic { - pmic_int: pmic-int { - rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - usb { - host_vbus_drv: host-vbus-drv { - rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - otg_vbus_drv: otg-vbus-drv { - rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&pwm0 { - status = "okay"; -}; - -&saradc { - vref-supply = <&vcc_18>; - status = "okay"; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - card-detect-delay = <200>; - disable-wp; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; - vmmc-supply = <&vcc_sdmmc>; - vqmmc-supply = <&vccio_sd>; - status = "okay"; -}; - -&tsadc { - rockchip,hw-tshut-mode = <0>; - rockchip,hw-tshut-polarity = <0>; - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&uart4 { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host1 { - status = "okay"; -}; - -&usb_otg { - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&vopl { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; -}; - -&wdt { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/rk3288-rock2-som.dtsi b/sys/gnu/dts/arm/rk3288-rock2-som.dtsi deleted file mode 100644 index 44bb5e6f83b..00000000000 --- a/sys/gnu/dts/arm/rk3288-rock2-som.dtsi +++ /dev/null @@ -1,273 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -#include -#include "rk3288.dtsi" - -/ { - memory@0 { - reg = <0x0 0x0 0x0 0x80000000>; - device_type = "memory"; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - pinctrl-0 = <&emmc_reset>; - pinctrl-names = "default"; - reset-gpios = <&gpio3 RK_PB1 GPIO_ACTIVE_LOW>; - }; - - ext_gmac: external-gmac-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <125000000>; - clock-output-names = "ext_gmac"; - }; - - vcc_flash: flash-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_flash"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - startup-delay-us = <150>; - vin-supply = <&vcc_io>; - }; - - vcc_sys: vsys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; -}; - -&cpu0 { - cpu0-supply = <&vdd_cpu>; -}; - -&emmc { - bus-width = <8>; - cap-mmc-highspeed; - disable-wp; - non-removable; - mmc-pwrseq = <&emmc_pwrseq>; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; - vmmc-supply = <&vcc_io>; - vqmmc-supply = <&vcc_flash>; - status = "okay"; -}; - -&gmac { - assigned-clocks = <&cru SCLK_MAC>; - assigned-clock-parents = <&ext_gmac>; - clock_in_out = "input"; - phy-mode = "rgmii"; - phy-supply = <&vccio_pmu>; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins &phy_rst>; - snps,reset-gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 30000>; - rx_delay = <0x10>; - tx_delay = <0x30>; -}; - -&gpu { - mali-supply = <&vdd_gpu>; - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - act8846: act8846@5a { - compatible = "active-semi,act8846"; - reg = <0x5a>; - system-power-controller; - inl1-supply = <&vcc_io>; - inl2-supply = <&vcc_sys>; - inl3-supply = <&vcc_20>; - vp1-supply = <&vcc_sys>; - vp2-supply = <&vcc_sys>; - vp3-supply = <&vcc_sys>; - vp4-supply = <&vcc_sys>; - - regulators { - vcc_ddr: REG1 { - regulator-name = "VCC_DDR"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - vcc_io: vccio_codec: REG2 { - regulator-name = "VCC_IO"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_log: REG3 { - regulator-name = "VDD_LOG"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - vcc_20: REG4 { - regulator-name = "VCC_20"; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - regulator-always-on; - }; - - vccio_sd: REG5 { - regulator-name = "VCCIO_SD"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd10_lcd: REG6 { - regulator-name = "VDD10_LCD"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - vcca_codec: REG7 { - regulator-name = "VCCA_CODEC"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vcca_tp: REG8 { - regulator-name = "VCCA_TP"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vccio_pmu: REG9 { - regulator-name = "VCCIO_PMU"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_10: REG10 { - regulator-name = "VDD_10"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - vcc_18: REG11 { - regulator-name = "VCC_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vcc18_lcd: REG12 { - regulator-name = "VCC18_LCD"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - }; - }; - - vdd_cpu: syr827@40 { - compatible = "silergy,syr827"; - reg = <0x40>; - fcs,suspend-voltage-selector = <1>; - regulator-always-on; - regulator-boot-on; - regulator-enable-ramp-delay = <300>; - regulator-name = "vdd_cpu"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <8000>; - vin-supply = <&vcc_sys>; - }; - - vdd_gpu: syr828@41 { - compatible = "silergy,syr828"; - reg = <0x41>; - fcs,suspend-voltage-selector = <1>; - regulator-always-on; - regulator-enable-ramp-delay = <300>; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1350000>; - regulator-name = "vdd_gpu"; - regulator-ramp-delay = <8000>; - vin-supply = <&vcc_sys>; - }; -}; - -&io_domains { - status = "okay"; - - audio-supply = <&vcc_io>; - bb-supply = <&vcc_io>; - dvp-supply = <&vcc_18>; - flash0-supply = <&vcc_flash>; - flash1-supply = <&vccio_pmu>; - gpio30-supply = <&vccio_pmu>; - gpio1830 = <&vcc_io>; - lcdc-supply = <&vcc_io>; - sdcard-supply = <&vccio_sd>; - wifi-supply = <&vcc_18>; -}; - -&pinctrl { - pcfg_output_high: pcfg-output-high { - output-high; - }; - - emmc { - emmc_reset: emmc-reset { - rockchip,pins = <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - gmac { - phy_rst: phy-rst { - rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_output_high>; - }; - }; -}; - -&saradc { - vref-supply = <&vcc_18>; -}; - -&tsadc { - rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ - rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ - status = "okay"; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&vopl { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; -}; - -&wdt { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/rk3288-rock2-square.dts b/sys/gnu/dts/arm/rk3288-rock2-square.dts deleted file mode 100644 index cdcdc921ee0..00000000000 --- a/sys/gnu/dts/arm/rk3288-rock2-square.dts +++ /dev/null @@ -1,288 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -/dts-v1/; -#include -#include "rk3288-rock2-som.dtsi" - -/ { - model = "Radxa Rock 2 Square"; - compatible = "radxa,rock2-square", "rockchip,rk3288"; - - chosen { - stdout-path = "serial2:115200n8"; - }; - - adc-keys { - compatible = "adc-keys"; - io-channels = <&saradc 1>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1800000>; - - button-recovery { - label = "Recovery"; - linux,code = ; - press-threshold-microvolt = <0>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - power { - gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; - label = "GPIO Power"; - linux,code = ; - pinctrl-names = "default"; - pinctrl-0 = <&pwr_key>; - wakeup-source; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - heartbeat { - gpios = <&gpio7 RK_PB7 GPIO_ACTIVE_LOW>; - label = "rock2:green:state1"; - linux,default-trigger = "heartbeat"; - }; - - mmc { - gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_LOW>; - label = "rock2:blue:state2"; - linux,default-trigger = "mmc0"; - }; - }; - - ir: ir-receiver { - compatible = "gpio-ir-receiver"; - gpios = <&gpio8 RK_PA1 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&ir_int>; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "SPDIF"; - simple-audio-card,dai-link@1 { /* S/PDIF - S/PDIF */ - cpu { sound-dai = <&spdif>; }; - codec { sound-dai = <&spdif_out>; }; - }; - }; - - sata_pwr: sata-prw-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 13 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&sata_pwr_en>; - /* Always turn on the 5V sata power connector */ - regulator-always-on; - regulator-name = "sata_pwr"; - }; - - spdif_out: spdif-out { - compatible = "linux,spdif-dit"; - #sound-dai-cells = <0>; - }; - - sound-i2s { - compatible = "rockchip,rk3288-hdmi-analog"; - pinctrl-names = "default"; - pinctrl-0 = <&phone_ctl>, <&hp_det>; - rockchip,audio-codec = <&es8388>; - rockchip,hp-det-gpios = <&gpio7 7 GPIO_ACTIVE_HIGH>; - rockchip,hp-en-gpios = <&gpio8 0 GPIO_ACTIVE_HIGH>; - rockchip,i2s-controller = <&i2s>; - rockchip,model = "I2S"; - rockchip,routing = "Analog", "LOUT2", - "Analog", "ROUT2"; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&hym8563>; - clock-names = "ext_clock"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_enable>; - reset-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>; - }; - - vcc_usb_host: vcc-host-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&host_vbus_drv>; - regulator-name = "vcc_host"; - }; - - vcc_sd: sdmmc-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio7 RK_PB3 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_pwr>; - regulator-name = "vcc_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_io>; - }; -}; - -&sdio0 { - bus-width = <4>; - cap-sd-highspeed; - cap-sdio-irq; - mmc-pwrseq = <&sdio_pwrseq>; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk &sdio0_int>; - vmmc-supply = <&vcc_io>; - vqmmc-supply = <&vcc_18>; - status = "okay"; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - card-detect-delay = <200>; - disable-wp; /* wp not hooked up */ - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; - vmmc-supply = <&vcc_sd>; - vqmmc-supply = <&vccio_sd>; - status = "okay"; -}; - -&gmac { - status = "ok"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c5>; - status = "okay"; -}; - -&i2c0 { - hym8563: hym8563@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "xin32k"; - interrupt-parent = <&gpio0>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int>; - - }; -}; - -&i2c2 { - status = "okay"; - - es8388: es8388@10 { - compatible = "everest,es8388", "everest,es8328"; - reg = <0x10>; - AVDD-supply = <&vccio_codec>; - DVDD-supply = <&vccio_codec>; - HPVDD-supply = <&vccio_codec>; - PVDD-supply = <&vccio_codec>; - clocks = <&cru SCLK_I2S0_OUT>; - }; -}; - -&i2c5 { - status = "okay"; -}; - -&i2s { - status = "okay"; -}; - -&pinctrl { - ir { - ir_int: ir-int { - rockchip,pins = <8 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - keys { - pwr_key: pwr-key { - rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - pmic { - pmic_int: pmic-int { - rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - headphone { - hp_det: hp-det { - rockchip,pins = <7 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - phone_ctl: phone-ctl { - rockchip,pins = <8 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - usb { - host_vbus_drv: host-vbus-drv { - rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - sata { - sata_pwr_en: sata-pwr-en { - rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - sdmmc { - sdmmc_pwr: sdmmc-pwr { - rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - sdio { - wifi_enable: wifi-enable { - rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&saradc { - status = "okay"; -}; - -&spdif { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; - -&usbphy1 { - vbus-supply = <&vcc_usb_host>; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host1 { - status = "okay"; -}; - -&usb_otg { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/rk3288-thermal.dtsi b/sys/gnu/dts/arm/rk3288-thermal.dtsi deleted file mode 100644 index 651b962e3d5..00000000000 --- a/sys/gnu/dts/arm/rk3288-thermal.dtsi +++ /dev/null @@ -1,118 +0,0 @@ -/* - * Device Tree Source for RK3288 SoC thermal - * - * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include - -reserve_thermal: reserve_thermal { - polling-delay-passive = <1000>; /* milliseconds */ - polling-delay = <5000>; /* milliseconds */ - - thermal-sensors = <&tsadc 0>; -}; - -cpu_thermal: cpu_thermal { - polling-delay-passive = <100>; /* milliseconds */ - polling-delay = <5000>; /* milliseconds */ - - thermal-sensors = <&tsadc 1>; - - trips { - cpu_alert0: cpu_alert0 { - temperature = <70000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - cpu_alert1: cpu_alert1 { - temperature = <75000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - cpu_crit: cpu_crit { - temperature = <90000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu_alert0>; - cooling-device = - <&cpu0 THERMAL_NO_LIMIT 6>; - }; - map1 { - trip = <&cpu_alert1>; - cooling-device = - <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; -}; - -gpu_thermal: gpu_thermal { - polling-delay-passive = <100>; /* milliseconds */ - polling-delay = <5000>; /* milliseconds */ - - thermal-sensors = <&tsadc 2>; - - trips { - gpu_alert0: gpu_alert0 { - temperature = <70000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - gpu_crit: gpu_crit { - temperature = <90000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&gpu_alert0>; - cooling-device = - <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/rk3288-tinker-s.dts b/sys/gnu/dts/arm/rk3288-tinker-s.dts deleted file mode 100644 index 970e1385919..00000000000 --- a/sys/gnu/dts/arm/rk3288-tinker-s.dts +++ /dev/null @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd. - */ - -/dts-v1/; - -#include "rk3288-tinker.dtsi" - -/ { - model = "Rockchip RK3288 Asus Tinker Board S"; - compatible = "asus,rk3288-tinker-s", "rockchip,rk3288"; -}; - -&emmc { - bus-width = <8>; - cap-mmc-highspeed; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>; - max-frequency = <150000000>; - mmc-hs200-1_8v; - mmc-ddr-1_8v; - status = "okay"; -}; - -&hdmi { - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_cec_c0>; -}; diff --git a/sys/gnu/dts/arm/rk3288-tinker.dts b/sys/gnu/dts/arm/rk3288-tinker.dts deleted file mode 100644 index 1e43527aa19..00000000000 --- a/sys/gnu/dts/arm/rk3288-tinker.dts +++ /dev/null @@ -1,13 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd. - */ - -/dts-v1/; - -#include "rk3288-tinker.dtsi" - -/ { - model = "Rockchip RK3288 Asus Tinker Board"; - compatible = "asus,rk3288-tinker", "rockchip,rk3288"; -}; diff --git a/sys/gnu/dts/arm/rk3288-tinker.dtsi b/sys/gnu/dts/arm/rk3288-tinker.dtsi deleted file mode 100644 index 312582c1bd3..00000000000 --- a/sys/gnu/dts/arm/rk3288-tinker.dtsi +++ /dev/null @@ -1,547 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd. - */ - -#include "rk3288.dtsi" -#include -#include - -/ { - chosen { - stdout-path = "serial2:115200n8"; - }; - - memory { - reg = <0x0 0x0 0x0 0x80000000>; - device_type = "memory"; - }; - - ext_gmac: external-gmac-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <125000000>; - clock-output-names = "ext_gmac"; - }; - - gpio-keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - autorepeat; - - pinctrl-names = "default"; - pinctrl-0 = <&pwrbtn>; - - button@0 { - gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "GPIO Key Power"; - linux,input-type = <1>; - wakeup-source; - debounce-interval = <100>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - act-led { - gpios = <&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc0"; - }; - - heartbeat-led { - gpios = <&gpio1 RK_PD1 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - - pwr-led { - gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - }; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&rk808 RK808_CLKOUT1>; - clock-names = "ext_clock"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_enable>; - reset-gpios = <&gpio4 RK_PD3 GPIO_ACTIVE_LOW>, - <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,name = "rockchip,tinker-codec"; - simple-audio-card,mclk-fs = <512>; - - simple-audio-card,codec { - sound-dai = <&hdmi>; - }; - - simple-audio-card,cpu { - sound-dai = <&i2s>; - }; - }; - - vcc_sys: vsys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - vcc_sd: sdmmc-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio7 11 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_pwr>; - regulator-name = "vcc_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <100000>; - vin-supply = <&vcc_io>; - }; -}; - -&cpu0 { - cpu0-supply = <&vdd_cpu>; -}; - -&cpu_opp_table { - opp-1704000000 { - opp-hz = /bits/ 64 <1704000000>; - opp-microvolt = <1350000>; - }; - opp-1800000000 { - opp-hz = /bits/ 64 <1800000000>; - opp-microvolt = <1400000>; - }; -}; - -&gmac { - assigned-clocks = <&cru SCLK_MAC>; - assigned-clock-parents = <&ext_gmac>; - clock_in_out = "input"; - phy-mode = "rgmii"; - phy-supply = <&vcc33_lan>; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - snps,reset-gpio = <&gpio4 7 0>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 1000000>; - tx_delay = <0x30>; - rx_delay = <0x10>; - status = "ok"; -}; - -&gpu { - mali-supply = <&vdd_gpu>; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c5>; - status = "okay"; -}; - -&i2c0 { - clock-frequency = <400000>; - status = "okay"; - - rk808: pmic@1b { - compatible = "rockchip,rk808"; - reg = <0x1b>; - interrupt-parent = <&gpio0>; - interrupts = <4 IRQ_TYPE_LEVEL_LOW>; - #clock-cells = <1>; - clock-output-names = "xin32k", "rk808-clkout2"; - dvs-gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>, - <&gpio0 12 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int &global_pwroff &dvs_1 &dvs_2>; - rockchip,system-power-controller; - wakeup-source; - - vcc1-supply = <&vcc_sys>; - vcc2-supply = <&vcc_sys>; - vcc3-supply = <&vcc_sys>; - vcc4-supply = <&vcc_sys>; - vcc6-supply = <&vcc_sys>; - vcc7-supply = <&vcc_sys>; - vcc8-supply = <&vcc_io>; - vcc9-supply = <&vcc_io>; - vcc10-supply = <&vcc_io>; - vcc11-supply = <&vcc_sys>; - vcc12-supply = <&vcc_io>; - vddio-supply = <&vcc_io>; - - regulators { - vdd_cpu: DCDC_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd_arm"; - regulator-ramp-delay = <6000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_gpu: DCDC_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1250000>; - regulator-name = "vdd_gpu"; - regulator-ramp-delay = <6000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc_ddr"; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_io: DCDC_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc_io"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc18_ldo1: LDO_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc18_ldo1"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc33_mipi: LDO_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc33_mipi"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_10: LDO_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-name = "vdd_10"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vcc18_codec: LDO_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc18_codec"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vccio_sd: LDO_REG5 { - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vccio_sd"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vdd10_lcd: LDO_REG6 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-name = "vdd10_lcd"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vcc_18: LDO_REG7 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc_18"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc18_lcd: LDO_REG8 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc18_lcd"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc33_sd: SWITCH_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc33_sd"; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc33_lan: SWITCH_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc33_lan"; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - }; - }; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c5 { - status = "okay"; -}; - -&i2s { - #sound-dai-cells = <0>; - status = "okay"; -}; - -&io_domains { - status = "okay"; - - sdcard-supply = <&vccio_sd>; - wifi-supply = <&vcc_18>; -}; - -&pinctrl { - pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma { - drive-strength = <8>; - }; - - pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma { - bias-pull-up; - drive-strength = <8>; - }; - - backlight { - bl_en: bl-en { - rockchip,pins = <7 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - buttons { - pwrbtn: pwrbtn { - rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - eth_phy { - eth_phy_pwr: eth-phy-pwr { - rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - pmic_int: pmic-int { - rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - dvs_1: dvs-1 { - rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - dvs_2: dvs-2 { - rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; - - sdmmc { - sdmmc_bus4: sdmmc-bus4 { - rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up_drv_8ma>, - <6 RK_PC1 1 &pcfg_pull_up_drv_8ma>, - <6 RK_PC2 1 &pcfg_pull_up_drv_8ma>, - <6 RK_PC3 1 &pcfg_pull_up_drv_8ma>; - }; - - sdmmc_clk: sdmmc-clk { - rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none_drv_8ma>; - }; - - sdmmc_cmd: sdmmc-cmd { - rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up_drv_8ma>; - }; - - sdmmc_pwr: sdmmc-pwr { - rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb { - host_vbus_drv: host-vbus-drv { - rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - pwr_3g: pwr-3g { - rockchip,pins = <7 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - sdio { - wifi_enable: wifi-enable { - rockchip,pins = <4 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>, - <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&pwm0 { - status = "okay"; -}; - -&saradc { - vref-supply = <&vcc18_ldo1>; - status = "okay"; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - broken-cd; - disable-wp; /* wp not hooked up */ - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; - status = "okay"; - vmmc-supply = <&vcc33_sd>; - vqmmc-supply = <&vccio_sd>; -}; - -&sdio0 { - bus-width = <4>; - cap-sd-highspeed; - cap-sdio-irq; - keep-power-in-suspend; - max-frequency = <50000000>; - mmc-pwrseq = <&sdio_pwrseq>; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&sdio0_bus4>, <&sdio0_cmd>, <&sdio0_clk>, <&sdio0_int>; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - vmmc-supply = <&vcc_io>; - vqmmc-supply = <&vcc_18>; - status = "okay"; -}; - -&tsadc { - rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */ - rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */ - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&uart4 { - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host1 { - status = "okay"; -}; - -&usb_otg { - status = "okay"; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&vopl { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; -}; - -&wdt { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/rk3288-veyron-analog-audio.dtsi b/sys/gnu/dts/arm/rk3288-veyron-analog-audio.dtsi deleted file mode 100644 index 51208d161d6..00000000000 --- a/sys/gnu/dts/arm/rk3288-veyron-analog-audio.dtsi +++ /dev/null @@ -1,99 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Google Veyron (and derivatives) fragment for the max98090 audio - * codec and analog headphone jack. - * - * Copyright 2016 Google, Inc - */ - -/ { - sound { - compatible = "rockchip,rockchip-audio-max98090"; - pinctrl-names = "default"; - pinctrl-0 = <&mic_det>, <&hp_det>; - rockchip,model = "VEYRON-I2S"; - rockchip,i2s-controller = <&i2s>; - rockchip,audio-codec = <&max98090>; - rockchip,hp-det-gpios = <&gpio6 RK_PA5 GPIO_ACTIVE_HIGH>; - rockchip,mic-det-gpios = <&gpio6 RK_PB3 GPIO_ACTIVE_LOW>; - rockchip,headset-codec = <&headsetcodec>; - rockchip,hdmi-codec = <&hdmi>; - }; -}; - -&i2c2 { - max98090: max98090@10 { - compatible = "maxim,max98090"; - reg = <0x10>; - interrupt-parent = <&gpio6>; - interrupts = ; - clock-names = "mclk"; - clocks = <&cru SCLK_I2S0_OUT>; - pinctrl-names = "default"; - pinctrl-0 = <&int_codec>; - }; -}; - -&i2c4 { - headsetcodec: ts3a227e@3b { - compatible = "ti,ts3a227e"; - reg = <0x3b>; - interrupt-parent = <&gpio0>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&ts3a227e_int_l>; - ti,micbias = <7>; /* MICBIAS = 2.8V */ - }; -}; - -&i2s { - status = "okay"; -}; - -&io_domains { - audio-supply = <&vcc18_codec>; -}; - -&rk808 { - vcc10-supply = <&vcc33_sys>; - - regulators { - vcc18_codec: LDO_REG6 { - regulator-name = "vcc18_codec"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; -}; - -&pinctrl { - codec { - hp_det: hp-det { - rockchip,pins = <6 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - /* - * HACK: We're going to _pull down_ this _active low_ interrupt - * so that it never fires. We don't need this interrupt because - * we've got a ts3a227e chip but the driver requires it. - */ - int_codec: int-codec { - rockchip,pins = <6 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - mic_det: mic-det { - rockchip,pins = <6 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - headset { - ts3a227e_int_l: ts3a227e-int-l { - rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/rk3288-veyron-brain.dts b/sys/gnu/dts/arm/rk3288-veyron-brain.dts deleted file mode 100644 index aa33d09184a..00000000000 --- a/sys/gnu/dts/arm/rk3288-veyron-brain.dts +++ /dev/null @@ -1,111 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Veyron Brain Rev 0 board device tree source - * - * Copyright 2014 Google, Inc - */ - -/dts-v1/; -#include "rk3288-veyron.dtsi" -#include "rk3288-veyron-broadcom-bluetooth.dtsi" - -/ { - model = "Google Brain"; - compatible = "google,veyron-brain-rev0", "google,veyron-brain", - "google,veyron", "rockchip,rk3288"; - - vcc33_sys: vcc33-sys { - vin-supply = <&vcc_5v>; - }; - - vcc33_io: vcc33_io { - compatible = "regulator-fixed"; - regulator-name = "vcc33_io"; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc33_sys>; - /* This is gated by vcc_18 too */ - }; - - /* This turns on vbus for host2 and otg (dwc2) */ - vcc5_host2: vcc5-host2-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&usb2_pwr_en>; - regulator-name = "vcc5_host2"; - regulator-always-on; - regulator-boot-on; - }; -}; - -&pinctrl { - pinctrl-names = "default"; - pinctrl-0 = < - /* Common for sleep and wake, but no owners */ - &ddr0_retention - &ddrio_pwroff - &global_pwroff - >; - - hdmi { - vcc50_hdmi_en: vcc50-hdmi-en { - rockchip,pins = <7 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - dvs_1: dvs-1 { - rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - dvs_2: dvs-2 { - rockchip,pins = <7 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; - - usb-host { - usb2_pwr_en: usb2-pwr-en { - rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&rk808 { - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>; - dvs-gpios = <&gpio7 RK_PB3 GPIO_ACTIVE_HIGH>, - <&gpio7 RK_PB7 GPIO_ACTIVE_HIGH>; - - /delete-property/ vcc6-supply; - - regulators { - /* vcc33_io is sourced directly from vcc33_sys */ - /delete-node/ LDO_REG1; - - /* This is not a pwren anymore, but the real power supply */ - vdd10_lcd: LDO_REG7 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-name = "vdd10_lcd"; - regulator-suspend-mem-disabled; - }; - - vcc18_hdmi: SWITCH_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc18_hdmi"; - regulator-suspend-mem-disabled; - }; - }; -}; - -&vcc50_hdmi { - enable-active-high; - gpio = <&gpio7 RK_PA2 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc50_hdmi_en>; -}; diff --git a/sys/gnu/dts/arm/rk3288-veyron-broadcom-bluetooth.dtsi b/sys/gnu/dts/arm/rk3288-veyron-broadcom-bluetooth.dtsi deleted file mode 100644 index a10d25ac8f7..00000000000 --- a/sys/gnu/dts/arm/rk3288-veyron-broadcom-bluetooth.dtsi +++ /dev/null @@ -1,22 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Veyron (and derivatives) fragment for the Broadcom 43450 bluetooth - * chip. - * - * Copyright 2019 Google, Inc - */ - -&uart0 { - bluetooth { - pinctrl-names = "default"; - pinctrl-0 = <&bt_host_wake_l>, <&bt_enable_l>, - <&bt_dev_wake>; - - compatible = "brcm,bcm43540-bt"; - host-wakeup-gpios = <&gpio4 RK_PD7 GPIO_ACTIVE_HIGH>; - shutdown-gpios = <&gpio4 RK_PD5 GPIO_ACTIVE_HIGH>; - device-wakeup-gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; - max-speed = <3000000>; - brcm,bt-pcm-int-params = [01 02 00 01 01]; - }; -}; diff --git a/sys/gnu/dts/arm/rk3288-veyron-chromebook.dtsi b/sys/gnu/dts/arm/rk3288-veyron-chromebook.dtsi deleted file mode 100644 index 05112c25176..00000000000 --- a/sys/gnu/dts/arm/rk3288-veyron-chromebook.dtsi +++ /dev/null @@ -1,184 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Veyron (and derivatives) board device tree source - * Chromebook specific parts - * - * Copyright 2015 Google, Inc - */ - -#include -#include -#include "rk3288-veyron.dtsi" -#include "rk3288-veyron-analog-audio.dtsi" -#include "rk3288-veyron-edp.dtsi" -#include "rk3288-veyron-sdmmc.dtsi" - -/ { - aliases { - /* Assign 20 so we don't get confused w/ builtin ones */ - i2c20 = &i2c_tunnel; - }; - - gpio-charger { - compatible = "gpio-charger"; - charger-type = "mains"; - gpios = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&ac_present_ap>; - }; - - lid_switch: lid-switch { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&ap_lid_int_l>; - - lid { - label = "Lid"; - gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>; - wakeup-source; - linux,code = ; - linux,input-type = ; - debounce-interval = <1>; - }; - }; - - /* A non-regulated voltage from power supply or battery */ - vccsys: vccsys { - compatible = "regulator-fixed"; - regulator-name = "vccsys"; - regulator-boot-on; - regulator-always-on; - }; - - vcc33_sys: vcc33-sys { - vin-supply = <&vccsys>; - }; - - vcc_5v: vcc-5v { - vin-supply = <&vccsys>; - }; - - /* This turns on vbus for host1 (dwc2) */ - vcc5_host1: vcc5-host1-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&host1_pwr_en>; - regulator-name = "vcc5_host1"; - regulator-always-on; - regulator-boot-on; - }; - - /* This turns on vbus for otg for host mode (dwc2) */ - vcc5v_otg: vcc5v-otg-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&usbotg_pwren_h>; - regulator-name = "vcc5_host2"; - regulator-always-on; - regulator-boot-on; - }; -}; - -&rk808 { - vcc11-supply = <&vcc_5v>; - - regulators { - vcc33_ccd: LDO_REG8 { - regulator-name = "vcc33_ccd"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; -}; - -&spi0 { - status = "okay"; - - cros_ec: ec@0 { - compatible = "google,cros-ec-spi"; - reg = <0>; - google,cros-ec-spi-pre-delay = <30>; - interrupt-parent = <&gpio7>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&ec_int>; - spi-max-frequency = <3000000>; - - i2c_tunnel: i2c-tunnel { - compatible = "google,cros-ec-i2c-tunnel"; - google,remote-bus = <0>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; -}; - -&i2c4 { - trackpad@15 { - compatible = "elan,ekth3000"; - reg = <0x15>; - interrupt-parent = <&gpio7>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&trackpad_int>; - vcc-supply = <&vcc33_io>; - wakeup-source; - }; -}; - -&pinctrl { - buttons { - ap_lid_int_l: ap-lid-int-l { - rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - charger { - ac_present_ap: ac-present-ap { - rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - cros-ec { - ec_int: ec-int { - rockchip,pins = <7 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - suspend { - suspend_l_wake: suspend-l-wake { - rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_output_low>; - }; - - suspend_l_sleep: suspend-l-sleep { - rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_output_high>; - }; - }; - - trackpad { - trackpad_int: trackpad-int { - rockchip,pins = <7 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - usb-host { - host1_pwr_en: host1-pwr-en { - rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - usbotg_pwren_h: usbotg-pwren-h { - rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -#include "cros-ec-keyboard.dtsi" diff --git a/sys/gnu/dts/arm/rk3288-veyron-edp.dtsi b/sys/gnu/dts/arm/rk3288-veyron-edp.dtsi deleted file mode 100644 index 32c0f10765d..00000000000 --- a/sys/gnu/dts/arm/rk3288-veyron-edp.dtsi +++ /dev/null @@ -1,141 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Veyron (and derivatives) fragment for the edp displays - * - * Copyright 2019 Google LLC - */ - -/ { - backlight_regulator: backlight-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&bl_pwr_en>; - regulator-name = "backlight_regulator"; - vin-supply = <&vcc33_sys>; - startup-delay-us = <15000>; - }; - - panel_regulator: panel-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio7 RK_PB6 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&lcd_enable_h>; - regulator-name = "panel_regulator"; - vin-supply = <&vcc33_sys>; - }; - - vcc18_lcd: vcc18-lcd { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&avdd_1v8_disp_en>; - regulator-name = "vcc18_lcd"; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc18_wl>; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - brightness-levels = <0 255>; - num-interpolated-steps = <255>; - default-brightness-level = <128>; - enable-gpios = <&gpio7 RK_PA2 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&bl_en>; - pwms = <&pwm0 0 1000000 0>; - post-pwm-on-delay-ms = <10>; - pwm-off-delay-ms = <10>; - power-supply = <&backlight_regulator>; - }; - - panel: panel { - compatible = "innolux,n116bge"; - status = "okay"; - power-supply = <&panel_regulator>; - backlight = <&backlight>; - - panel-timing { - clock-frequency = <74250000>; - hactive = <1366>; - hfront-porch = <136>; - hback-porch = <60>; - hsync-len = <30>; - hsync-active = <0>; - vactive = <768>; - vfront-porch = <8>; - vback-porch = <12>; - vsync-len = <12>; - vsync-active = <0>; - }; - - ports { - panel_in: port { - panel_in_edp: endpoint { - remote-endpoint = <&edp_out_panel>; - }; - }; - }; - }; -}; - -&edp { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&edp_hpd>; - - ports { - edp_out: port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - edp_out_panel: endpoint@0 { - reg = <0>; - remote-endpoint = <&panel_in_edp>; - }; - }; - }; -}; - -&edp_phy { - status = "okay"; -}; - -&pwm0 { - status = "okay"; -}; - -&vopl { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; -}; - -&pinctrl { - backlight { - bl_pwr_en: bl_pwr_en { - rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bl_en: bl-en { - rockchip,pins = <7 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - lcd { - lcd_enable_h: lcd-en { - rockchip,pins = <7 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - avdd_1v8_disp_en: avdd-1v8-disp-en { - rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/rk3288-veyron-fievel.dts b/sys/gnu/dts/arm/rk3288-veyron-fievel.dts deleted file mode 100644 index 309b122b4d0..00000000000 --- a/sys/gnu/dts/arm/rk3288-veyron-fievel.dts +++ /dev/null @@ -1,528 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Veyron Fievel Rev 0+ board device tree source - * - * Copyright 2016 Google, Inc - */ - -/dts-v1/; -#include "rk3288-veyron.dtsi" -#include "rk3288-veyron-analog-audio.dtsi" - -/ { - model = "Google Fievel"; - compatible = "google,veyron-fievel-rev8", "google,veyron-fievel-rev7", - "google,veyron-fievel-rev6", "google,veyron-fievel-rev5", - "google,veyron-fievel-rev4", "google,veyron-fievel-rev3", - "google,veyron-fievel-rev2", "google,veyron-fievel-rev1", - "google,veyron-fievel-rev0", "google,veyron-fievel", - "google,veyron", "rockchip,rk3288"; - - vccsys: vccsys { - compatible = "regulator-fixed"; - regulator-name = "vccsys"; - regulator-boot-on; - regulator-always-on; - }; - - /* - * vcc33_pmuio and vcc33_io is sourced directly from vcc33_sys, - * enabled by vcc_18 - */ - vcc33_io: vcc33-io { - compatible = "regulator-fixed"; - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc33_io"; - }; - - vcc5_host1: vcc5-host1-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio5 RK_PC2 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&hub_usb1_pwr_en>; - regulator-name = "vcc5_host1"; - regulator-always-on; - regulator-boot-on; - }; - - vcc5_host2: vcc5-host2-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio5 RK_PB6 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&hub_usb2_pwr_en>; - regulator-name = "vcc5_host2"; - regulator-always-on; - regulator-boot-on; - }; - - vcc5v_otg: vcc5v-otg-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&usb_otg_pwr_en>; - regulator-name = "vcc5_otg"; - regulator-always-on; - regulator-boot-on; - }; - - ext_gmac: external-gmac-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <125000000>; - clock-output-names = "ext_gmac"; - }; -}; - -&gmac { - status = "okay"; - - assigned-clocks = <&cru SCLK_MAC>; - assigned-clock-parents = <&ext_gmac>; - clock_in_out = "input"; - phy-handle = <ðphy>; - phy-mode = "rgmii"; - phy-supply = <&vcc33_lan>; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>, <&phy_rst>, <&phy_pmeb>, <&phy_int>; - rx_delay = <0x10>; - tx_delay = <0x30>; - - /* - * Reset for the RTL8211 PHY which requires a 10-ms reset pulse (low) - * with a 30ms settling time. - */ - snps,reset-gpio = <&gpio4 RK_PB0 0>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 30000>; - wakeup-source; - - mdio0 { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - ethphy: ethernet-phy@1 { - reg = <1>; - }; - }; -}; - -&rk808 { - dvs-gpios = <&gpio7 RK_PB4 GPIO_ACTIVE_HIGH>, - <&gpio7 RK_PB7 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>; - - vcc6-supply = <&vcc33_sys>; - vcc10-supply = <&vcc33_sys>; - vcc11-supply = <&vcc_5v>; - vcc12-supply = <&vcc33_sys>; - - regulators { - /delete-node/ LDO_REG1; - - /* - * According to the schematic, vcc18_lcdt is for - * HDMI_AVDD_1V8 - */ - vcc18_lcdt: LDO_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vdd18_lcdt"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - /* - * This is not a pwren anymore, but the real power supply, - * vdd10_lcd for HDMI_AVDD_1V0 - */ - vdd10_lcd: LDO_REG7 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-name = "vdd10_lcd"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - /* for usb camera */ - vcc33_ccd: LDO_REG8 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc33_ccd"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc33_lan: SWITCH_REG2 { - regulator-name = "vcc33_lan"; - }; - }; -}; - -&sdio0 { - #address-cells = <1>; - #size-cells = <0>; - - btmrvl: btmrvl@2 { - compatible = "marvell,sd8897-bt"; - reg = <2>; - interrupt-parent = <&gpio4>; - interrupts = ; - marvell,wakeup-pin = /bits/ 16 <13>; - pinctrl-names = "default"; - pinctrl-0 = <&bt_host_wake_l>; - }; -}; - -&vcc50_hdmi { - enable-active-high; - gpio = <&gpio5 RK_PC3 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc50_hdmi_en>; -}; - -&vcc_5v { - enable-active-high; - gpio = <&gpio7 RK_PC5 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&drv_5v>; -}; - -&gpio0 { - gpio-line-names = "PMIC_SLEEP_AP", - "DDRIO_PWROFF", - "DDRIO_RETEN", - "TS3A227E_INT_L", - "PMIC_INT_L", - "PWR_KEY_L", - "HUB_USB1_nFALUT", - "PHY_PMEB", - - "PHY_INT", - /* - * RECOVERY_SW_L is Chrome OS ABI. Schematics call - * it REC_MODE_L. - */ - "RECOVERY_SW_L", - "OTP_OUT", - "", - "USB_OTG_POWER_EN", - "AP_WARM_RESET_H", - "USB_OTG_nFALUT", - "I2C0_SDA_PMIC", - - "I2C0_SCL_PMIC", - "DEVMODE_L", - "USB_INT"; -}; - -&gpio2 { - gpio-line-names = "CONFIG0", - "CONFIG1", - "CONFIG2", - "", - "", - "", - "", - "CONFIG3", - - "", - "EMMC_RST_L", - "", - "", - "BL_PWR_EN", - "", - "TOUCH_INT", - "TOUCH_RST", - - "I2C3_SCL_TP", - "I2C3_SDA_TP"; -}; - -&gpio3 { - gpio-line-names = "FLASH0_D0", - "FLASH0_D1", - "FLASH0_D2", - "FLASH0_D3", - "FLASH0_D4", - "FLASH0_D5", - "FLASH0_D6", - "FLASH0_D7", - - "VCC5V_GOOD_H", - "", - "", - "", - "", - "", - "", - "", - - "FLASH0_CS2/EMMC_CMD", - "", - "FLASH0_DQS/EMMC_CLKO", - "", - "", - "", - "", - "", - - "PHY_TXD2", - "PHY_TXD3", - "MAC_RXD2", - "MAC_RXD3", - "PHY_TXD0", - "PHY_TXD1", - "MAC_RXD0", - "MAC_RXD1"; -}; - -&gpio4 { - gpio-line-names = "MAC_MDC", - "MAC_RXDV", - "MAC_RXER", - "MAC_CLK", - "PHY_TXEN", - "MAC_MDIO", - "MAC_RXCLK", - "", - - "PHY_RST", - "PHY_TXCLK", - "", - "", - "", - "", - "", - "", - - "UART0_RXD", - "UART0_TXD", - "UART0_CTS_L", - "UART0_RTS_L", - "SDIO0_D0", - "SDIO0_D1", - "SDIO0_D2", - "SDIO0_D3", - - "SDIO0_CMD", - "SDIO0_CLK", - "BT_DEV_WAKE", - "", - "WIFI_ENABLE_H", - "BT_ENABLE_L", - "WIFI_HOST_WAKE", - "BT_HOST_WAKE"; -}; - -&gpio5 { - gpio-line-names = "", - "", - "", - "", - "", - "", - "", - "", - - "", - "", - "", - "", - "USB_OTG_CTL1", - "HUB_USB2_CTL1", - "HUB_USB2_PWR_EN", - "HUB_USB_ILIM_SEL", - - "USB_OTG_STATUS_L", - "HUB_USB1_CTL1", - "HUB_USB1_PWR_EN", - "VCC50_HDMI_EN"; -}; - -&gpio6 { - gpio-line-names = "I2S0_SCLK", - "I2S0_LRCK_RX", - "I2S0_LRCK_TX", - "I2S0_SDI", - "I2S0_SDO0", - "HP_DET_H", - "", - "INT_CODEC", - - "I2S0_CLK", - "I2C2_SDA", - "I2C2_SCL", - "MICDET", - "", - "", - "", - "", - - "HUB_USB2_nFALUT", - "USB_OTG_ILIM_SEL"; -}; - -&gpio7 { - gpio-line-names = "LCD_BL_PWM", - "PWM_LOG", - "BL_EN", - "PWR_LED1", - "TPM_INT_H", - "SPK_ON", - /* - * AP_FLASH_WP_L is Chrome OS ABI. Schematics call - * it FW_WP_AP. - */ - "AP_FLASH_WP_L", - "", - - "CPU_NMI", - "DVSOK", - "", - "EDP_HPD", - "DVS1", - "", - "LCD_EN", - "DVS2", - - "HDMI_CEC", - "I2C4_SDA", - "I2C4_SCL", - "I2C5_SDA_HDMI", - "I2C5_SCL_HDMI", - "5V_DRV", - "UART2_RXD", - "UART2_TXD"; -}; - -&gpio8 { - gpio-line-names = "RAM_ID0", - "RAM_ID1", - "RAM_ID2", - "RAM_ID3", - "I2C1_SDA_TPM", - "I2C1_SCL_TPM", - "SPI2_CLK", - "SPI2_CS0", - - "SPI2_RXD", - "SPI2_TXD"; -}; - -&pinctrl { - pinctrl-names = "default", "sleep"; - pinctrl-0 = < - /* Common for sleep and wake, but no owners */ - &ddr0_retention - &ddrio_pwroff - &global_pwroff - - /* For usb bc1.2 */ - &usb_otg_ilim_sel - &usb_usb_ilim_sel - - /* Wake only */ - &bt_dev_wake_awake - &pwr_led1_on - >; - - pinctrl-1 = < - /* Common for sleep and wake, but no owners */ - &ddr0_retention - &ddrio_pwroff - &global_pwroff - - /* For usb bc1.2 */ - &usb_otg_ilim_sel - &usb_usb_ilim_sel - - /* Sleep only */ - &bt_dev_wake_sleep - &pwr_led1_blink - >; - - buck-5v { - drv_5v: drv-5v { - rockchip,pins = <7 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - gmac { - phy_rst: phy-rst { - rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_output_high>; - }; - - phy_pmeb: phy-pmeb { - rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - phy_int: phy-int { - rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - hdmi { - vcc50_hdmi_en: vcc50-hdmi-en { - rockchip,pins = <5 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - leds { - pwr_led1_on: pwr-led1-on { - rockchip,pins = <7 RK_PA3 RK_FUNC_GPIO &pcfg_output_low>; - }; - - pwr_led1_blink: pwr-led1-blink { - rockchip,pins = <7 RK_PA3 RK_FUNC_GPIO &pcfg_output_high>; - }; - }; - - pmic { - dvs_1: dvs-1 { - rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - dvs_2: dvs-2 { - rockchip,pins = <7 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; - - usb-bc12 { - usb_otg_ilim_sel: usb-otg-ilim-sel { - rockchip,pins = <6 RK_PC1 RK_FUNC_GPIO &pcfg_output_low>; - }; - - usb_usb_ilim_sel: usb-usb-ilim-sel { - rockchip,pins = <5 RK_PB7 RK_FUNC_GPIO &pcfg_output_low>; - }; - }; - - usb-host { - hub_usb1_pwr_en: hub_usb1_pwr_en { - rockchip,pins = <5 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - hub_usb2_pwr_en: hub_usb2_pwr_en { - rockchip,pins = <5 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - usb_otg_pwr_en: usb_otg_pwr_en { - rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/rk3288-veyron-jaq.dts b/sys/gnu/dts/arm/rk3288-veyron-jaq.dts deleted file mode 100644 index 171ba6185b6..00000000000 --- a/sys/gnu/dts/arm/rk3288-veyron-jaq.dts +++ /dev/null @@ -1,319 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Veyron Jaq Rev 1+ board device tree source - * - * Copyright 2015 Google, Inc - */ - -/dts-v1/; - -#include "rk3288-veyron-chromebook.dtsi" -#include "cros-ec-sbs.dtsi" - -/ { - model = "Google Jaq"; - compatible = "google,veyron-jaq-rev5", "google,veyron-jaq-rev4", - "google,veyron-jaq-rev3", "google,veyron-jaq-rev2", - "google,veyron-jaq-rev1", "google,veyron-jaq", - "google,veyron", "rockchip,rk3288"; -}; - -&backlight { - /* Jaq panel PWM must be >= 3%, so start non-zero brightness at 8 */ - brightness-levels = <0 8 255>; - num-interpolated-steps = <247>; -}; - -&rk808 { - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>; - dvs-gpios = <&gpio7 RK_PB4 GPIO_ACTIVE_HIGH>, - <&gpio7 RK_PB7 GPIO_ACTIVE_HIGH>; - - regulators { - mic_vcc: LDO_REG2 { - regulator-name = "mic_vcc"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; -}; - -&sdmmc { - disable-wp; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio - &sdmmc_bus4>; -}; - -&vcc_5v { - enable-active-high; - gpio = <&gpio7 RK_PC5 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&drv_5v>; -}; - -&vcc50_hdmi { - enable-active-high; - gpio = <&gpio5 RK_PC3 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc50_hdmi_en>; -}; - -&gpio0 { - gpio-line-names = "PMIC_SLEEP_AP", - "DDRIO_PWROFF", - "DDRIO_RETEN", - "TS3A227E_INT_L", - "PMIC_INT_L", - "PWR_KEY_L", - "AP_LID_INT_L", - "EC_IN_RW", - - "AC_PRESENT_AP", - /* - * RECOVERY_SW_L is Chrome OS ABI. Schematics call - * it REC_MODE_L. - */ - "RECOVERY_SW_L", - "OTP_OUT", - "HOST1_PWR_EN", - "USBOTG_PWREN_H", - "AP_WARM_RESET_H", - "nFALUT2", - "I2C0_SDA_PMIC", - - "I2C0_SCL_PMIC", - "SUSPEND_L", - "USB_INT"; -}; - -&gpio2 { - gpio-line-names = "CONFIG0", - "CONFIG1", - "CONFIG2", - "", - "", - "", - "", - "CONFIG3", - - "", - "EMMC_RST_L", - "", - "", - "BL_PWR_EN", - "AVDD_1V8_DISP_EN"; -}; - -&gpio3 { - gpio-line-names = "FLASH0_D0", - "FLASH0_D1", - "FLASH0_D2", - "FLASH0_D3", - "FLASH0_D4", - "FLASH0_D5", - "FLASH0_D6", - "FLASH0_D7", - - "", - "", - "", - "", - "", - "", - "", - "", - - "FLASH0_CS2/EMMC_CMD", - "", - "FLASH0_DQS/EMMC_CLKO"; -}; - -&gpio4 { - gpio-line-names = "", - "", - "", - "", - "", - "", - "", - "", - - "", - "", - "", - "", - "", - "", - "", - "", - - "UART0_RXD", - "UART0_TXD", - "UART0_CTS", - "UART0_RTS", - "SDIO0_D0", - "SDIO0_D1", - "SDIO0_D2", - "SDIO0_D3", - - "SDIO0_CMD", - "SDIO0_CLK", - "BT_DEV_WAKE", /* Maybe missing from mighty? */ - "", - "WIFI_ENABLE_H", - "BT_ENABLE_L", - "WIFI_HOST_WAKE", - "BT_HOST_WAKE"; -}; - -&gpio5 { - gpio-line-names = "", - "", - "", - "", - "", - "", - "", - "", - - "", - "", - "", - "", - "SPI0_CLK", - "SPI0_CS0", - "SPI0_TXD", - "SPI0_RXD", - - "", - "", - "", - "VCC50_HDMI_EN"; -}; - -&gpio6 { - gpio-line-names = "I2S0_SCLK", - "I2S0_LRCK_RX", - "I2S0_LRCK_TX", - "I2S0_SDI", - "I2S0_SDO0", - "HP_DET_H", - "ALS_INT", - "INT_CODEC", - - "I2S0_CLK", - "I2C2_SDA", - "I2C2_SCL", - "MICDET", - "", - "", - "", - "", - - "SDMMC_D0", - "SDMMC_D1", - "SDMMC_D2", - "SDMMC_D3", - "SDMMC_CLK", - "SDMMC_CMD"; -}; - -&gpio7 { - gpio-line-names = "LCDC_BL", - "PWM_LOG", - "BL_EN", - "TRACKPAD_INT", - "TPM_INT_H", - "SDMMC_DET_L", - /* - * AP_FLASH_WP_L is Chrome OS ABI. Schematics call - * it FW_WP_AP. - */ - "AP_FLASH_WP_L", - "EC_INT", - - "CPU_NMI", - "DVSOK", - "SDMMC_WP", /* mighty only */ - "EDP_HPD", - "DVS1", - "nFALUT1", /* nFAULT1 on jaq */ - "LCD_EN", - "DVS2", - - "VCC5V_GOOD_H", - "I2C4_SDA_TP", - "I2C4_SCL_TP", - "I2C5_SDA_HDMI", - "I2C5_SCL_HDMI", - "5V_DRV", - "UART2_RXD", - "UART2_TXD"; -}; - -&gpio8 { - gpio-line-names = "RAM_ID0", - "RAM_ID1", - "RAM_ID2", - "RAM_ID3", - "I2C1_SDA_TPM", - "I2C1_SCL_TPM", - "SPI2_CLK", - "SPI2_CS0", - - "SPI2_RXD", - "SPI2_TXD"; -}; - -&pinctrl { - pinctrl-names = "default", "sleep"; - pinctrl-0 = < - /* Common for sleep and wake, but no owners */ - &ddr0_retention - &ddrio_pwroff - &global_pwroff - - /* Wake only */ - &suspend_l_wake - &bt_dev_wake_awake - >; - pinctrl-1 = < - /* Common for sleep and wake, but no owners */ - &ddr0_retention - &ddrio_pwroff - &global_pwroff - - /* Sleep only */ - &suspend_l_sleep - &bt_dev_wake_sleep - >; - - buck-5v { - drv_5v: drv-5v { - rockchip,pins = <7 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - hdmi { - vcc50_hdmi_en: vcc50-hdmi-en { - rockchip,pins = <5 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - dvs_1: dvs-1 { - rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - dvs_2: dvs-2 { - rockchip,pins = <7 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/rk3288-veyron-jerry.dts b/sys/gnu/dts/arm/rk3288-veyron-jerry.dts deleted file mode 100644 index 66f00d28801..00000000000 --- a/sys/gnu/dts/arm/rk3288-veyron-jerry.dts +++ /dev/null @@ -1,494 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Veyron Jerry Rev 3+ board device tree source - * - * Copyright 2015 Google, Inc - */ - -/dts-v1/; -#include "rk3288-veyron-chromebook.dtsi" -#include "cros-ec-sbs.dtsi" - -/ { - model = "Google Jerry"; - compatible = "google,veyron-jerry-rev15", "google,veyron-jerry-rev14", - "google,veyron-jerry-rev13", "google,veyron-jerry-rev12", - "google,veyron-jerry-rev11", "google,veyron-jerry-rev10", - "google,veyron-jerry-rev7", "google,veyron-jerry-rev6", - "google,veyron-jerry-rev5", "google,veyron-jerry-rev4", - "google,veyron-jerry-rev3", "google,veyron-jerry", - "google,veyron", "rockchip,rk3288"; -}; - -&rk808 { - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>; - dvs-gpios = <&gpio7 RK_PB4 GPIO_ACTIVE_HIGH>, - <&gpio7 RK_PB7 GPIO_ACTIVE_HIGH>; - - regulators { - mic_vcc: LDO_REG2 { - regulator-name = "mic_vcc"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; -}; - -&sdio0 { - #address-cells = <1>; - #size-cells = <0>; - - mwifiex: wifi@1 { - compatible = "marvell,sd8897"; - reg = <1>; - - marvell,caldata-txpwrlimit-2g = /bits/ 8 < -0x01 0x00 0x06 0x00 0x08 0x02 0x89 0x01 -0x24 0x00 0x67 0x09 0x14 0x01 0x00 0x0f 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c -0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c -0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 0x24 0x00 0x67 0x09 0x14 0x02 0x00 0x0f -0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c 0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 -0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 -0x24 0x00 0x67 0x09 0x14 0x03 0x00 0x0f 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c -0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c -0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 0x24 0x00 0x67 0x09 0x14 0x04 0x00 0x0f -0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c 0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 -0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 -0x24 0x00 0x67 0x09 0x14 0x05 0x00 0x0f 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c -0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c -0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 0x24 0x00 0x67 0x09 0x14 0x06 0x00 0x0f -0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c 0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 -0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 -0x24 0x00 0x67 0x09 0x14 0x07 0x00 0x0f 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c -0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c -0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 0x24 0x00 0x67 0x09 0x14 0x08 0x00 0x0f -0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c 0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 -0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 -0x24 0x00 0x67 0x09 0x14 0x09 0x00 0x0f 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c -0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c -0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 0x24 0x00 0x67 0x09 0x14 0x0a 0x00 0x0f -0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c 0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 -0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 -0x24 0x00 0x67 0x09 0x14 0x0b 0x00 0x0f 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c -0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c -0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 0x24 0x00 0x67 0x09 0x14 0x0c 0x00 0x0f -0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c 0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 -0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 -0x24 0x00 0x67 0x09 0x14 0x0d 0x00 0x0f 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c -0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c -0x0d 0x09 0x0e 0x09 0x0f 0x09>; - - marvell,caldata-txpwrlimit-5g-sub0 = /bits/ 8 < -0x01 0x00 0x06 0x00 0xf0 0x01 0x89 0x01 -0x3a 0x00 0x88 0x13 0x14 0x24 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a -0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 -0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 -0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 -0x88 0x13 0x14 0x28 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a -0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 -0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 -0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 -0x14 0x2c 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 -0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 -0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 -0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x30 -0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 -0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 -0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 -0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x34 0x01 0x0c -0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 -0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 -0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 -0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x38 0x01 0x0c 0x02 0x0c -0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a -0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 -0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 -0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x3c 0x01 0x0c 0x02 0x0c 0x03 0x0c -0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a -0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 -0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 -0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x40 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a -0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a -0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 -0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05>; - - marvell,caldata-txpwrlimit-5g-sub1 = /bits/ 8 < -0x01 0x00 0x06 0x00 0xaa 0x02 0x89 0x01 -0x3a 0x00 0x88 0x13 0x14 0x64 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a -0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 -0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 -0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 -0x88 0x13 0x14 0x68 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a -0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 -0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 -0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 -0x14 0x6c 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 -0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 -0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 -0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x70 -0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 -0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 -0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 -0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x74 0x01 0x0c -0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 -0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 -0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 -0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x78 0x01 0x0c 0x02 0x0c -0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a -0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 -0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 -0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x7c 0x01 0x0c 0x02 0x0c 0x03 0x0c -0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a -0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 -0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 -0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x80 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a -0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a -0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 -0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 -0x3a 0x00 0x88 0x13 0x14 0x84 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a -0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 -0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 -0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 -0x88 0x13 0x14 0x88 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a -0x07 0x08 0x08 0x08 0x09 0x08 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x08 0x0e 0x08 -0x0f 0x08 0x10 0x04 0x11 0x04 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x04 -0x17 0x04 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 -0x14 0x8c 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x08 -0x08 0x08 0x09 0x08 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x08 0x0e 0x08 0x0f 0x08 -0x10 0x04 0x11 0x04 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x04 0x17 0x04 -0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05>; - - marvell,caldata-txpwrlimit-5g-sub2 = /bits/ 8 < -0x01 0x00 0x06 0x00 0x36 0x01 0x89 0x01 -0x3a 0x00 0x88 0x13 0x14 0x95 0x01 0x0b 0x02 0x0b 0x03 0x0b 0x04 0x0a 0x05 0x0a -0x06 0x0a 0x07 0x08 0x08 0x08 0x09 0x08 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x08 -0x0e 0x08 0x0f 0x08 0x10 0x04 0x11 0x04 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 -0x16 0x04 0x17 0x04 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 -0x88 0x13 0x14 0x99 0x01 0x0b 0x02 0x0b 0x03 0x0b 0x04 0x0a 0x05 0x0a 0x06 0x0a -0x07 0x08 0x08 0x08 0x09 0x08 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x08 0x0e 0x08 -0x0f 0x08 0x10 0x04 0x11 0x04 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x04 -0x17 0x04 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 -0x14 0x9d 0x01 0x0b 0x02 0x0b 0x03 0x0b 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x08 -0x08 0x08 0x09 0x08 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x08 0x0e 0x08 0x0f 0x08 -0x10 0x04 0x11 0x04 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x04 0x17 0x04 -0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0xa1 -0x01 0x0b 0x02 0x0b 0x03 0x0b 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x08 0x08 0x08 -0x09 0x08 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x08 0x0e 0x08 0x0f 0x08 0x10 0x04 -0x11 0x04 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x04 0x17 0x04 0x18 0x05 -0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0xa5 0x01 0x0b -0x02 0x0b 0x03 0x0b 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x08 0x08 0x08 0x09 0x08 -0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x08 0x0e 0x08 0x0f 0x08 0x10 0x04 0x11 0x04 -0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x04 0x17 0x04 0x18 0x05 0x19 0x05 -0x1a 0x05 0x1b 0x05>; - }; -}; - -&sdmmc { - disable-wp; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio - &sdmmc_bus4>; -}; - -&vcc_5v { - enable-active-high; - gpio = <&gpio7 RK_PC5 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&drv_5v>; -}; - -&vcc50_hdmi { - enable-active-high; - gpio = <&gpio5 RK_PC3 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc50_hdmi_en>; -}; - -&gpio0 { - gpio-line-names = "PMIC_SLEEP_AP", - "DDRIO_PWROFF", - "DDRIO_RETEN", - "TS3A227E_INT_L", - "PMIC_INT_L", - "PWR_KEY_L", - "AP_LID_INT_L", - "EC_IN_RW", - - "AC_PRESENT_AP", - /* - * RECOVERY_SW_L is Chrome OS ABI. Schematics call - * it REC_MODE_L. - */ - "RECOVERY_SW_L", - "OTP_OUT", - "HOST1_PWR_EN", - "USBOTG_PWREN_H", - "AP_WARM_RESET_H", - "nFAULT2", - "I2C0_SDA_PMIC", - - "I2C0_SCL_PMIC", - "SUSPEND_L", - "USB_INT"; -}; - -&gpio2 { - gpio-line-names = "CONFIG0", - "CONFIG1", - "CONFIG2", - "", - "", - "", - "", - "CONFIG3", - - "", - "EMMC_RST_L", - "", - "", - "BL_PWR_EN", - "AVDD_1V8_DISP_EN"; -}; - -&gpio3 { - gpio-line-names = "FLASH0_D0", - "FLASH0_D1", - "FLASH0_D2", - "FLASH0_D3", - "FLASH0_D4", - "FLASH0_D5", - "FLASH0_D6", - "FLASH0_D7", - - "", - "", - "", - "", - "", - "", - "", - "", - - "FLASH0_CS2/EMMC_CMD", - "", - "FLASH0_DQS/EMMC_CLKO"; -}; - -&gpio4 { - gpio-line-names = "", - "", - "", - "", - "", - "", - "", - "", - - "", - "", - "", - "", - "", - "", - "", - "", - - "UART0_RXD", - "UART0_TXD", - "UART0_CTS", - "UART0_RTS", - "SDIO0_D0", - "SDIO0_D1", - "SDIO0_D2", - "SDIO0_D3", - - "SDIO0_CMD", - "SDIO0_CLK", - "BT_DEV_WAKE", - "", - "WIFI_ENABLE_H", - "BT_ENABLE_L", - "WIFI_HOST_WAKE", - "BT_HOST_WAKE"; -}; - -&gpio5 { - gpio-line-names = "", - "", - "", - "", - "", - "", - "", - "", - - "", - "", - "", - "", - "SPI0_CLK", - "SPI0_CS0", - "SPI0_TXD", - "SPI0_RXD", - - "", - "", - "", - "VCC50_HDMI_EN"; -}; - -&gpio6 { - gpio-line-names = "I2S0_SCLK", - "I2S0_LRCK_RX", - "I2S0_LRCK_TX", - "I2S0_SDI", - "I2S0_SDO0", - "HP_DET_H", - "", - "INT_CODEC", - - "I2S0_CLK", - "I2C2_SDA", - "I2C2_SCL", - "MICDET", - "", - "", - "", - "", - - "SDMMC_D0", - "SDMMC_D1", - "SDMMC_D2", - "SDMMC_D3", - "SDMMC_CLK", - "SDMMC_CMD"; -}; - -&gpio7 { - gpio-line-names = "LCDC_BL", - "PWM_LOG", - "BL_EN", - "TRACKPAD_INT", - "TPM_INT_H", - "SDMMC_DET_L", - /* - * AP_FLASH_WP_L is Chrome OS ABI. Schematics call - * it FW_WP_AP. - */ - "AP_FLASH_WP_L", - "EC_INT", - - "CPU_NMI", - "DVSOK", - "", - "EDP_HPD", - "DVS1", - "nFAULT1", - "LCD_EN", - "DVS2", - - "VCC5V_GOOD_H", - "I2C4_SDA_TP", - "I2C4_SCL_TP", - "I2C5_SDA_HDMI", - "I2C5_SCL_HDMI", - "5V_DRV", - "UART2_RXD", - "UART2_TXD"; -}; - -&gpio8 { - gpio-line-names = "RAM_ID0", - "RAM_ID1", - "RAM_ID2", - "RAM_ID3", - "I2C1_SDA_TPM", - "I2C1_SCL_TPM", - "SPI2_CLK", - "SPI2_CS0", - - "SPI2_RXD", - "SPI2_TXD"; -}; - -&pinctrl { - pinctrl-names = "default", "sleep"; - pinctrl-0 = < - /* Common for sleep and wake, but no owners */ - &ddr0_retention - &ddrio_pwroff - &global_pwroff - - /* Wake only */ - &suspend_l_wake - &bt_dev_wake_awake - >; - pinctrl-1 = < - /* Common for sleep and wake, but no owners */ - &ddr0_retention - &ddrio_pwroff - &global_pwroff - - /* Sleep only */ - &suspend_l_sleep - &bt_dev_wake_sleep - >; - - buck-5v { - drv_5v: drv-5v { - rockchip,pins = <7 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - hdmi { - vcc50_hdmi_en: vcc50-hdmi-en { - rockchip,pins = <5 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - dvs_1: dvs-1 { - rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - dvs_2: dvs-2 { - rockchip,pins = <7 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; -}; - -&i2c4 { - status = "okay"; - - /* - * Trackpad pin control is shared between Elan and Synaptics devices - * so we have to pull it up to the bus level. - */ - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_xfer &trackpad_int>; - - trackpad@15 { - /* - * Remove the inherited pinctrl settings to avoid clashing - * with bus-wide ones. - */ - /delete-property/pinctrl-names; - /delete-property/pinctrl-0; - }; - - trackpad@2c { - compatible = "hid-over-i2c"; - interrupt-parent = <&gpio7>; - interrupts = ; - reg = <0x2c>; - hid-descr-addr = <0x0020>; - vcc-supply = <&vcc33_io>; - wakeup-source; - }; -}; diff --git a/sys/gnu/dts/arm/rk3288-veyron-mickey.dts b/sys/gnu/dts/arm/rk3288-veyron-mickey.dts deleted file mode 100644 index ffd1121d19b..00000000000 --- a/sys/gnu/dts/arm/rk3288-veyron-mickey.dts +++ /dev/null @@ -1,453 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Veyron Mickey Rev 0 board device tree source - * - * Copyright 2015 Google, Inc - */ - -/dts-v1/; -#include "rk3288-veyron.dtsi" -#include "rk3288-veyron-broadcom-bluetooth.dtsi" - -/ { - model = "Google Mickey"; - compatible = "google,veyron-mickey-rev8", "google,veyron-mickey-rev7", - "google,veyron-mickey-rev6", "google,veyron-mickey-rev5", - "google,veyron-mickey-rev4", "google,veyron-mickey-rev3", - "google,veyron-mickey-rev2", "google,veyron-mickey-rev1", - "google,veyron-mickey-rev0", "google,veyron-mickey", - "google,veyron", "rockchip,rk3288"; - - vcc_5v: vcc-5v { - vin-supply = <&vcc33_sys>; - }; - - vcc33_io: vcc33_io { - compatible = "regulator-fixed"; - regulator-name = "vcc33_io"; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc33_sys>; - }; - - sound { - compatible = "rockchip,rockchip-audio-max98090"; - rockchip,model = "VEYRON-HDMI"; - rockchip,hdmi-codec = <&hdmi>; - rockchip,i2s-controller = <&i2s>; - }; -}; - -&cpu_thermal { - /delete-node/ trips; - /delete-node/ cooling-maps; - - trips { - cpu_alert_almost_warm: cpu_alert_almost_warm { - temperature = <63000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - cpu_alert_warm: cpu_alert_warm { - temperature = <65000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - cpu_alert_almost_hot: cpu_alert_almost_hot { - temperature = <80000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - cpu_alert_hot: cpu_alert_hot { - temperature = <82000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - cpu_alert_hotter: cpu_alert_hotter { - temperature = <84000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - cpu_alert_very_hot: cpu_alert_very_hot { - temperature = <85000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - cpu_crit: cpu_crit { - temperature = <90000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "critical"; - }; - }; - - cooling-maps { - /* - * After 1st level, throttle the CPU down to as low as 1.4 GHz - * and don't let the GPU go faster than 400 MHz. - */ - cpu_warm_limit_cpu { - trip = <&cpu_alert_warm>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT 4>, - <&cpu1 THERMAL_NO_LIMIT 4>, - <&cpu2 THERMAL_NO_LIMIT 4>, - <&cpu3 THERMAL_NO_LIMIT 4>; - }; - cpu_warm_limit_gpu { - trip = <&cpu_alert_warm>; - cooling-device = <&gpu 1 1>; - }; - - /* - * Add some discrete steps to help throttling system deal - * with the fact that there are two passive cooling devices: - * the CPU and the GPU. - * - * - 1.2 GHz - 1.0 GHz (almost hot) - * - 800 MHz (hot) - * - 800 MHz - 696 MHz (hotter) - * - 696 MHz - min (very hot) - * - * Note: - * - 800 MHz appears to be a "sweet spot" for me. I can run - * some pretty serious workload here and be happy. - * - After 696 MHz we stop lowering voltage, so throttling - * past there is less effective. - */ - cpu_almost_hot_limit_cpu { - trip = <&cpu_alert_almost_hot>; - cooling-device = <&cpu0 5 6>, <&cpu1 5 6>, <&cpu2 5 6>, - <&cpu3 5 6>; - }; - cpu_hot_limit_cpu { - trip = <&cpu_alert_hot>; - cooling-device = <&cpu0 7 7>, <&cpu1 7 7>, <&cpu2 7 7>, - <&cpu3 7 7>; - }; - cpu_hotter_limit_cpu { - trip = <&cpu_alert_hotter>; - cooling-device = <&cpu0 7 8>, <&cpu1 7 8>, <&cpu2 7 8>, - <&cpu3 7 8>; - }; - cpu_very_hot_limit_cpu { - trip = <&cpu_alert_very_hot>; - cooling-device = <&cpu0 8 THERMAL_NO_LIMIT>, - <&cpu1 8 THERMAL_NO_LIMIT>, - <&cpu2 8 THERMAL_NO_LIMIT>, - <&cpu3 8 THERMAL_NO_LIMIT>; - }; - - /* At very hot, don't let GPU go over 300 MHz */ - cpu_very_hot_limit_gpu { - trip = <&cpu_alert_very_hot>; - cooling-device = <&gpu 2 2>; - }; - }; -}; - -&gpu_thermal { - /delete-node/ trips; - /delete-node/ cooling-maps; - - trips { - gpu_alert_warmish: gpu_alert_warmish { - temperature = <60000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - gpu_alert_warm: gpu_alert_warm { - temperature = <65000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - gpu_alert_hotter: gpu_alert_hotter { - temperature = <84000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - gpu_alert_very_very_hot: gpu_alert_very_very_hot { - temperature = <86000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - gpu_crit: gpu_crit { - temperature = <90000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "critical"; - }; - }; - - cooling-maps { - /* After 1st level throttle the GPU down to as low as 400 MHz */ - gpu_warmish_limit_gpu { - trip = <&gpu_alert_warmish>; - cooling-device = <&gpu THERMAL_NO_LIMIT 1>; - }; - - /* - * Slightly after we throttle the GPU, we'll also make sure that - * the CPU can't go faster than 1.4 GHz. Note that we won't - * throttle the CPU lower than 1.4 GHz due to GPU heat--we'll - * let the CPU do the rest itself. - */ - gpu_warm_limit_cpu { - trip = <&gpu_alert_warm>; - cooling-device = <&cpu0 4 4>, - <&cpu1 4 4>, - <&cpu2 4 4>, - <&cpu3 4 4>; - }; - - /* When hot, GPU goes down to 300 MHz */ - gpu_hotter_limit_gpu { - trip = <&gpu_alert_hotter>; - cooling-device = <&gpu 2 2>; - }; - - /* When really hot, don't let GPU go _above_ 300 MHz */ - gpu_very_very_hot_limit_gpu { - trip = <&gpu_alert_very_very_hot>; - cooling-device = <&gpu 2 THERMAL_NO_LIMIT>; - }; - }; -}; - -&i2c2 { - status = "disabled"; -}; - -&i2c4 { - status = "disabled"; -}; - -&i2s { - status = "okay"; -}; - -&rk808 { - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>; - dvs-gpios = <&gpio7 RK_PB4 GPIO_ACTIVE_HIGH>, - <&gpio7 RK_PB7 GPIO_ACTIVE_HIGH>; - - /delete-property/ vcc6-supply; - /delete-property/ vcc12-supply; - - vcc11-supply = <&vcc33_sys>; - - regulators { - /* vcc33_io is sourced directly from vcc33_sys */ - /delete-node/ LDO_REG1; - /delete-node/ LDO_REG7; - - /* This is not a pwren anymore, but the real power supply */ - vdd10_lcd: LDO_REG7 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-name = "vdd10_lcd"; - regulator-suspend-mem-disabled; - }; - - vcc18_lcd: LDO_REG8 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc18_lcd"; - regulator-suspend-mem-disabled; - }; - }; -}; - -&gpio0 { - gpio-line-names = "PMIC_SLEEP_AP", - "", - "", - "", - "PMIC_INT_L", - "POWER_BUTTON_L", - "", - "", - - "", - /* - * RECOVERY_SW_L is Chrome OS ABI. Schematics call - * it REC_MODE_L. - */ - "RECOVERY_SW_L", - "OT_RESET", - "", - "", - "AP_WARM_RESET_H", - "", - "I2C0_SDA_PMIC", - - "I2C0_SCL_PMIC", - "", - "nFALUT"; -}; - -&gpio2 { - gpio-line-names = "CONFIG0", - "CONFIG1", - "CONFIG2", - "", - "", - "", - "", - "CONFIG3", - - "", - "EMMC_RST_L"; -}; - -&gpio3 { - gpio-line-names = "FLASH0_D0", - "FLASH0_D1", - "FLASH0_D2", - "FLASH0_D3", - "FLASH0_D4", - "FLASH0_D5", - "FLASH0_D6", - "FLASH0_D7", - - "", - "", - "", - "", - "", - "", - "", - "", - - "FLASH0_CS2/EMMC_CMD", - "", - "FLASH0_DQS/EMMC_CLKO"; -}; - -&gpio4 { - gpio-line-names = "", - "", - "", - "", - "", - "", - "", - "", - - "", - "", - "", - "", - "", - "", - "", - "", - - "UART0_RXD", - "UART0_TXD", - "UART0_CTS_L", - "UART0_RTS_L", - "SDIO0_D0", - "SDIO0_D1", - "SDIO0_D2", - "SDIO0_D3", - - "SDIO0_CMD", - "SDIO0_CLK", - "BT_DEV_WAKE", - "", - "WIFI_ENABLE_H", - "BT_ENABLE_L", - "WIFI_HOST_WAKE", - "BT_HOST_WAKE"; -}; - -&gpio7 { - gpio-line-names = "", - "PWM_LOG", - "", - "", - "TPM_INT_H", - "SDMMC_DET_L", - /* - * AP_FLASH_WP_L is Chrome OS ABI. Schematics call - * it FW_WP_AP. - */ - "AP_FLASH_WP_L", - "", - - "CPU_NMI", - "DVSOK", - "HDMI_WAKE", - "POWER_HDMI_ON", - "DVS1", - "", - "", - "DVS2", - - "HDMI_CEC", - "", - "", - "I2C5_SDA_HDMI", - "I2C5_SCL_HDMI", - "", - "UART2_RXD", - "UART2_TXD"; -}; - -&gpio8 { - gpio-line-names = "RAM_ID0", - "RAM_ID1", - "RAM_ID2", - "RAM_ID3", - "I2C1_SDA_TPM", - "I2C1_SCL_TPM", - "SPI2_CLK", - "SPI2_CS0", - - "SPI2_RXD", - "SPI2_TXD"; -}; - -&pinctrl { - pinctrl-names = "default"; - pinctrl-0 = < - /* Common for sleep and wake, but no owners */ - &ddr0_retention - &ddrio_pwroff - &global_pwroff - >; - - hdmi { - power_hdmi_on: power-hdmi-on { - rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - dvs_1: dvs-1 { - rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - dvs_2: dvs-2 { - rockchip,pins = <7 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; -}; - -&usb_host0_ehci { - status = "disabled"; -}; - -&usb_host1 { - status = "disabled"; -}; - -&vcc50_hdmi { - enable-active-high; - gpio = <&gpio7 RK_PB3 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&power_hdmi_on>; -}; diff --git a/sys/gnu/dts/arm/rk3288-veyron-mighty.dts b/sys/gnu/dts/arm/rk3288-veyron-mighty.dts deleted file mode 100644 index 27fbc07476d..00000000000 --- a/sys/gnu/dts/arm/rk3288-veyron-mighty.dts +++ /dev/null @@ -1,34 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Veyron Mighty Rev 1+ board device tree source - * - * Copyright 2015 Google, Inc - */ - -/dts-v1/; - -#include "rk3288-veyron-jaq.dts" - -/ { - model = "Google Mighty"; - compatible = "google,veyron-mighty-rev5", "google,veyron-mighty-rev4", - "google,veyron-mighty-rev3", "google,veyron-mighty-rev2", - "google,veyron-mighty-rev1", "google,veyron-mighty", - "google,veyron", "rockchip,rk3288"; -}; - -&sdmmc { - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio - &sdmmc_wp_gpio &sdmmc_bus4>; - wp-gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>; - - /delete-property/ disable-wp; -}; - -&pinctrl { - sdmmc { - sdmmc_wp_gpio: sdmmc-wp-gpio { - rockchip,pins = <7 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/rk3288-veyron-minnie.dts b/sys/gnu/dts/arm/rk3288-veyron-minnie.dts deleted file mode 100644 index 383fad1a88a..00000000000 --- a/sys/gnu/dts/arm/rk3288-veyron-minnie.dts +++ /dev/null @@ -1,415 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Veyron Minnie Rev 0+ board device tree source - * - * Copyright 2015 Google, Inc - */ - -/dts-v1/; -#include "rk3288-veyron-chromebook.dtsi" -#include "rk3288-veyron-broadcom-bluetooth.dtsi" - -/ { - model = "Google Minnie"; - compatible = "google,veyron-minnie-rev4", "google,veyron-minnie-rev3", - "google,veyron-minnie-rev2", "google,veyron-minnie-rev1", - "google,veyron-minnie-rev0", "google,veyron-minnie", - "google,veyron", "rockchip,rk3288"; - - volume_buttons: volume-buttons { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&volum_down_l &volum_up_l>; - - volum_down { - label = "Volum_down"; - gpios = <&gpio5 RK_PB3 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <100>; - }; - - volum_up { - label = "Volum_up"; - gpios = <&gpio5 RK_PB2 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <100>; - }; - }; -}; - -&backlight { - /* Minnie panel PWM must be >= 1%, so start non-zero brightness at 3 */ - brightness-levels = <0 3 255>; - num-interpolated-steps = <252>; -}; - -&i2c_tunnel { - battery: bq27500@55 { - compatible = "ti,bq27500"; - reg = <0x55>; - }; -}; - -&i2c3 { - status = "okay"; - - clock-frequency = <400000>; - i2c-scl-falling-time-ns = <50>; - i2c-scl-rising-time-ns = <300>; - - touchscreen@10 { - compatible = "elan,ekth3500"; - reg = <0x10>; - interrupt-parent = <&gpio2>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&touch_int &touch_rst>; - reset-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_LOW>; - vcc33-supply = <&vcc33_touch>; - vccio-supply = <&vcc33_touch>; - }; -}; - -&panel { - compatible = "auo,b101ean01"; - - /delete-node/ panel-timing; - - panel-timing { - clock-frequency = <66666667>; - hactive = <1280>; - hfront-porch = <18>; - hback-porch = <21>; - hsync-len = <32>; - vactive = <800>; - vfront-porch = <4>; - vback-porch = <8>; - vsync-len = <18>; - }; -}; - -&rk808 { - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>; - - regulators { - vcc33_touch: LDO_REG2 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc33_touch"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc5v_touch: SWITCH_REG2 { - regulator-name = "vcc5v_touch"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; -}; - -&sdmmc { - disable-wp; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio - &sdmmc_bus4>; -}; - -&vcc_5v { - enable-active-high; - gpio = <&gpio7 RK_PC5 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&drv_5v>; -}; - -&vcc50_hdmi { - enable-active-high; - gpio = <&gpio5 RK_PC3 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc50_hdmi_en>; -}; - -&gpio0 { - gpio-line-names = "PMIC_SLEEP_AP", - "DDRIO_PWROFF", - "DDRIO_RETEN", - "TS3A227E_INT_L", - "PMIC_INT_L", - "PWR_KEY_L", - "AP_LID_INT_L", - "EC_IN_RW", - - "AC_PRESENT_AP", - /* - * RECOVERY_SW_L is Chrome OS ABI. Schematics call - * it REC_MODE_L. - */ - "RECOVERY_SW_L", - "OTP_OUT", - "HOST1_PWR_EN", - "USBOTG_PWREN_H", - "AP_WARM_RESET_H", - "nFALUT2", - "I2C0_SDA_PMIC", - - "I2C0_SCL_PMIC", - "SUSPEND_L", - "USB_INT"; -}; - -&gpio2 { - gpio-line-names = "CONFIG0", - "CONFIG1", - "CONFIG2", - "", - "", - "", - "", - "CONFIG3", - - "PROCHOT#", - "EMMC_RST_L", - "", - "", - "BL_PWR_EN", - "AVDD_1V8_DISP_EN", - "TOUCH_INT", - "TOUCH_RST", - - "I2C3_SCL_TP", - "I2C3_SDA_TP"; -}; - -&gpio3 { - gpio-line-names = "FLASH0_D0", - "FLASH0_D1", - "FLASH0_D2", - "FLASH0_D3", - "FLASH0_D4", - "FLASH0_D5", - "FLASH0_D6", - "FLASH0_D7", - - "", - "", - "", - "", - "", - "", - "", - "", - - "FLASH0_CS2/EMMC_CMD", - "", - "FLASH0_DQS/EMMC_CLKO"; -}; - -&gpio4 { - gpio-line-names = "", - "", - "", - "", - "", - "", - "", - "", - - "", - "", - "", - "", - "", - "", - "", - "", - - "UART0_RXD", - "UART0_TXD", - "UART0_CTS", - "UART0_RTS", - "SDIO0_D0", - "SDIO0_D1", - "SDIO0_D2", - "SDIO0_D3", - - "SDIO0_CMD", - "SDIO0_CLK", - "dev_wake", - "", - "WIFI_ENABLE_H", - "BT_ENABLE_L", - "WIFI_HOST_WAKE", - "BT_HOST_WAKE"; -}; - -&gpio5 { - gpio-line-names = "", - "", - "", - "", - "", - "", - "", - "", - - "", - "", - "Volum_Up#", - "Volum_Down#", - "SPI0_CLK", - "SPI0_CS0", - "SPI0_TXD", - "SPI0_RXD", - - "", - "", - "", - "VCC50_HDMI_EN"; -}; - -&gpio6 { - gpio-line-names = "I2S0_SCLK", - "I2S0_LRCK_RX", - "I2S0_LRCK_TX", - "I2S0_SDI", - "I2S0_SDO0", - "HP_DET_H", - "", - "INT_CODEC", - - "I2S0_CLK", - "I2C2_SDA", - "I2C2_SCL", - "MICDET", - "", - "", - "", - "", - - "SDMMC_D0", - "SDMMC_D1", - "SDMMC_D2", - "SDMMC_D3", - "SDMMC_CLK", - "SDMMC_CMD"; -}; - -&gpio7 { - gpio-line-names = "LCDC_BL", - "PWM_LOG", - "BL_EN", - "TRACKPAD_INT", - "TPM_INT_H", - "SDMMC_DET_L", - /* - * AP_FLASH_WP_L is Chrome OS ABI. Schematics call - * it FW_WP_AP. - */ - "AP_FLASH_WP_L", - "EC_INT", - - "CPU_NMI", - "DVS_OK", - "SDMMC_WP", - "EDP_HPD", - "DVS1", - "nFALUT1", - "LCD_EN", - "DVS2", - - "VCC5V_GOOD_H", - "I2C4_SDA_TP", - "I2C4_SCL_TP", - "I2C5_SDA_HDMI", - "I2C5_SCL_HDMI", - "5V_DRV", - "UART2_RXD", - "UART2_TXD"; -}; - -&gpio8 { - gpio-line-names = "RAM_ID0", - "RAM_ID1", - "RAM_ID2", - "RAM_ID3", - "I2C1_SDA_TPM", - "I2C1_SCL_TPM", - "SPI2_CLK", - "SPI2_CS0", - - "SPI2_RXD", - "SPI2_TXD"; -}; - -&pinctrl { - pinctrl-names = "default", "sleep"; - pinctrl-0 = < - /* Common for sleep and wake, but no owners */ - &ddr0_retention - &ddrio_pwroff - &global_pwroff - - /* Wake only */ - &suspend_l_wake - >; - pinctrl-1 = < - /* Common for sleep and wake, but no owners */ - &ddr0_retention - &ddrio_pwroff - &global_pwroff - - /* Sleep only */ - &suspend_l_sleep - >; - - buck-5v { - drv_5v: drv-5v { - rockchip,pins = <7 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - buttons { - volum_down_l: volum-down-l { - rockchip,pins = <5 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - volum_up_l: volum-up-l { - rockchip,pins = <5 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - hdmi { - vcc50_hdmi_en: vcc50-hdmi-en { - rockchip,pins = <5 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - dvs_1: dvs-1 { - rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - dvs_2: dvs-2 { - rockchip,pins = <7 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; - - prochot { - gpio_prochot: gpio-prochot { - rockchip,pins = <2 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - touchscreen { - touch_int: touch-int { - rockchip,pins = <2 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - touch_rst: touch-rst { - rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/rk3288-veyron-pinky.dts b/sys/gnu/dts/arm/rk3288-veyron-pinky.dts deleted file mode 100644 index 71e6629cc20..00000000000 --- a/sys/gnu/dts/arm/rk3288-veyron-pinky.dts +++ /dev/null @@ -1,137 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Veyron Pinky Rev 2 board device tree source - * - * Copyright 2015 Google, Inc - */ - -/dts-v1/; -#include "rk3288-veyron-chromebook.dtsi" -#include "cros-ec-sbs.dtsi" - -/ { - model = "Google Pinky"; - compatible = "google,veyron-pinky-rev2", "google,veyron-pinky", - "google,veyron", "rockchip,rk3288"; - - /delete-node/backlight-regulator; - /delete-node/panel-regulator; - /delete-node/emmc-pwrseq; - /delete-node/vcc18-lcd; -}; - -&backlight { - /delete-property/power-supply; -}; - -&emmc { - /* - * Use a pullup instead of a drive since the output is 3.3V and - * really should be 1.8V (oops). The external pulldown will help - * bring the voltage down if we only drive with a pullup here. - * Therefore disable the powerseq (and actual reset) for pinky. - */ - /delete-property/mmc-pwrseq; - pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8 &emmc_reset>; -}; - -&edp { - /delete-property/pinctrl-names; - /delete-property/pinctrl-0; - - force-hpd; -}; - -&lid_switch { - pinctrl-0 = <&pwr_key_h &ap_lid_int_l>; - - power { - gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; - }; -}; - -/* Touchpad connector */ -&i2c3 { - status = "okay"; - - clock-frequency = <400000>; - i2c-scl-falling-time-ns = <50>; - i2c-scl-rising-time-ns = <300>; -}; - -&panel { - power-supply = <&vcc33_lcd>; -}; - -&pinctrl { - pinctrl-names = "default", "sleep"; - pinctrl-0 = < - /* Common for sleep and wake, but no owners */ - &ddr0_retention - &ddrio_pwroff - &global_pwroff - - /* Wake only */ - &suspend_l_wake - &bt_dev_wake_awake - >; - pinctrl-1 = < - /* Common for sleep and wake, but no owners */ - &ddr0_retention - &ddrio_pwroff - &global_pwroff - - /* Sleep only */ - &suspend_l_sleep - &bt_dev_wake_sleep - >; - - /delete-node/ lcd; - - backlight { - /delete-node/ bl_pwr_en; - }; - - buttons { - pwr_key_h: pwr-key-h { - rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - emmc { - emmc_reset: emmc-reset { - rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - sdmmc { - sdmmc_wp_gpio: sdmmc-wp-gpio { - rockchip,pins = <7 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; -}; - -&rk808 { - regulators { - vcc18_lcd: SWITCH_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc18_lcd"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; -}; - -&sdmmc { - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio - &sdmmc_wp_gpio &sdmmc_bus4>; - wp-gpios = <&gpio7 RK_PB2 GPIO_ACTIVE_HIGH>; -}; - -&tsadc { - /* Some connection is flaky making the tsadc hang the system */ - status = "disabled"; -}; diff --git a/sys/gnu/dts/arm/rk3288-veyron-sdmmc.dtsi b/sys/gnu/dts/arm/rk3288-veyron-sdmmc.dtsi deleted file mode 100644 index fe950f9863e..00000000000 --- a/sys/gnu/dts/arm/rk3288-veyron-sdmmc.dtsi +++ /dev/null @@ -1,89 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Veyron (and derivatives) fragment for sdmmc cards - * - * Copyright 2015 Google, Inc - */ - -&io_domains { - sdcard-supply = <&vccio_sd>; -}; - -&pinctrl { - sdmmc { - /* - * We run sdmmc at max speed; bump up drive strength. - * We also have external pulls, so disable the internal ones. - */ - sdmmc_bus4: sdmmc-bus4 { - rockchip,pins = <6 RK_PC0 1 &pcfg_pull_none_drv_8ma>, - <6 RK_PC1 1 &pcfg_pull_none_drv_8ma>, - <6 RK_PC2 1 &pcfg_pull_none_drv_8ma>, - <6 RK_PC3 1 &pcfg_pull_none_drv_8ma>; - }; - - sdmmc_clk: sdmmc-clk { - rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none_drv_8ma>; - }; - - sdmmc_cmd: sdmmc-cmd { - rockchip,pins = <6 RK_PC5 1 &pcfg_pull_none_drv_8ma>; - }; - - /* - * Builtin CD line is hooked to ground to prevent JTAG at boot - * (and also to get the voltage rail correct). - * Configure gpio6_C6 as GPIO so dw_mmc builtin CD doesn't - * think there's a card inserted - */ - sdmmc_cd_disabled: sdmmc-cd-disabled { - rockchip,pins = <6 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - /* This is where we actually hook up CD */ - sdmmc_cd_gpio: sdmmc-cd-gpio { - rockchip,pins = <7 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&rk808 { - vcc9-supply = <&vcc_5v>; - - regulators { - vccio_sd: LDO_REG4 { - regulator-name = "vccio_sd"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc33_sd: LDO_REG5 { - regulator-name = "vcc33_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; -}; - -&sdmmc { - status = "okay"; - - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - card-detect-delay = <200>; - cd-gpios = <&gpio7 RK_PA5 GPIO_ACTIVE_LOW>; - rockchip,default-sample-phase = <90>; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-sdr104; - vmmc-supply = <&vcc33_sd>; - vqmmc-supply = <&vccio_sd>; -}; diff --git a/sys/gnu/dts/arm/rk3288-veyron-speedy.dts b/sys/gnu/dts/arm/rk3288-veyron-speedy.dts deleted file mode 100644 index e354c61a45e..00000000000 --- a/sys/gnu/dts/arm/rk3288-veyron-speedy.dts +++ /dev/null @@ -1,324 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Veyron Speedy Rev 1+ board device tree source - * - * Copyright 2015 Google, Inc - */ - -/dts-v1/; -#include "rk3288-veyron-chromebook.dtsi" -#include "rk3288-veyron-broadcom-bluetooth.dtsi" -#include "cros-ec-sbs.dtsi" - -/ { - model = "Google Speedy"; - compatible = "google,veyron-speedy-rev9", "google,veyron-speedy-rev8", - "google,veyron-speedy-rev7", "google,veyron-speedy-rev6", - "google,veyron-speedy-rev5", "google,veyron-speedy-rev4", - "google,veyron-speedy-rev3", "google,veyron-speedy-rev2", - "google,veyron-speedy", "google,veyron", "rockchip,rk3288"; -}; - -&cpu_alert0 { - temperature = <65000>; -}; - -&cpu_alert1 { - temperature = <70000>; -}; - -&cpu_crit { - temperature = <90000>; -}; - -&edp { - /delete-property/pinctrl-names; - /delete-property/pinctrl-0; - - force-hpd; -}; - -&gpu_alert0 { - temperature = <80000>; -}; - -&gpu_crit { - temperature = <90000>; -}; - -&rk808 { - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l>; -}; - -&sdmmc { - disable-wp; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio - &sdmmc_bus4>; -}; - -&vcc_5v { - enable-active-high; - gpio = <&gpio7 RK_PC5 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&drv_5v>; -}; - -&vcc50_hdmi { - enable-active-high; - gpio = <&gpio5 RK_PC3 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc50_hdmi_en>; -}; - -&gpio0 { - gpio-line-names = "PMIC_SLEEP_AP", - "DDRIO_PWROFF", - "DDRIO_RETEN", - "TS3A227E_INT_L", - "PMIC_INT_L", - "PWR_KEY_L", - "AP_LID_INT_L", - "EC_IN_RW", - - "AC_PRESENT_AP", - /* - * RECOVERY_SW_L is Chrome OS ABI. Schematics call - * it REC_MODE_L. - */ - "RECOVERY_SW_L", - "OTP_OUT", - "HOST1_PWR_EN", - "USBOTG_PWREN_H", - "AP_WARM_RESET_H", - "nFALUT2", - "I2C0_SDA_PMIC", - - "I2C0_SCL_PMIC", - "SUSPEND_L", - "USB_INT"; -}; - -&gpio2 { - gpio-line-names = "CONFIG0", - "CONFIG1", - "CONFIG2", - "", - "", - "", - "", - "CONFIG3", - - "PWRLIMIT#_CPU", - "EMMC_RST_L", - "", - "", - "BL_PWR_EN", - "AVDD_1V8_DISP_EN"; -}; - -&gpio3 { - gpio-line-names = "FLASH0_D0", - "FLASH0_D1", - "FLASH0_D2", - "FLASH0_D3", - "FLASH0_D4", - "FLASH0_D5", - "FLASH0_D6", - "FLASH0_D7", - - "", - "", - "", - "", - "", - "", - "", - "", - - "FLASH0_CS2/EMMC_CMD", - "", - "FLASH0_DQS/EMMC_CLKO"; -}; - -&gpio4 { - gpio-line-names = "", - "", - "", - "", - "", - "", - "", - "", - - "", - "", - "", - "", - "", - "", - "", - "", - - "UART0_RXD", - "UART0_TXD", - "UART0_CTS", - "UART0_RTS", - "SDIO0_D0", - "SDIO0_D1", - "SDIO0_D2", - "SDIO0_D3", - - "SDIO0_CMD", - "SDIO0_CLK", - "BT_DEV_WAKE", - "", - "WIFI_ENABLE_H", - "BT_ENABLE_L", - "WIFI_HOST_WAKE", - "BT_HOST_WAKE"; -}; - -&gpio5 { - gpio-line-names = "", - "", - "", - "", - "", - "", - "", - "", - - "", - "", - "", - "", - "SPI0_CLK", - "SPI0_CS0", - "SPI0_TXD", - "SPI0_RXD", - - "", - "", - "", - "VCC50_HDMI_EN"; -}; - -&gpio6 { - gpio-line-names = "I2S0_SCLK", - "I2S0_LRCK_RX", - "I2S0_LRCK_TX", - "I2S0_SDI", - "I2S0_SDO0", - "HP_DET_H", - "ALS_INT", /* not connected */ - "INT_CODEC", - - "I2S0_CLK", - "I2C2_SDA", - "I2C2_SCL", - "MICDET", - "", - "", - "", - "", - - "SDMMC_D0", - "SDMMC_D1", - "SDMMC_D2", - "SDMMC_D3", - "SDMMC_CLK", - "SDMMC_CMD"; -}; - -&gpio7 { - gpio-line-names = "LCDC_BL", - "PWM_LOG", - "BL_EN", - "TRACKPAD_INT", - "TPM_INT_H", - "SDMMC_DET_L", - /* - * AP_FLASH_WP_L is Chrome OS ABI. Schematics call - * it FW_WP_AP. - */ - "AP_FLASH_WP_L", - "EC_INT", - - "CPU_NMI", - "DVS_OK", - "", - "EDP_HOTPLUG", - "DVS1", - "nFALUT1", - "LCD_EN", - "DVS2", - - "VCC5V_GOOD_H", - "I2C4_SDA_TP", - "I2C4_SCL_TP", - "I2C5_SDA_HDMI", - "I2C5_SCL_HDMI", - "5V_DRV", - "UART2_RXD", - "UART2_TXD"; -}; - -&gpio8 { - gpio-line-names = "RAM_ID0", - "RAM_ID1", - "RAM_ID2", - "RAM_ID3", - "I2C1_SDA_TPM", - "I2C1_SCL_TPM", - "SPI2_CLK", - "SPI2_CS0", - - "SPI2_RXD", - "SPI2_TXD"; -}; - -&pinctrl { - pinctrl-names = "default", "sleep"; - pinctrl-0 = < - /* Common for sleep and wake, but no owners */ - &ddr0_retention - &ddrio_pwroff - &global_pwroff - - /* Wake only */ - &suspend_l_wake - >; - pinctrl-1 = < - /* Common for sleep and wake, but no owners */ - &ddr0_retention - &ddrio_pwroff - &global_pwroff - - /* Sleep only */ - &suspend_l_sleep - >; - - buck-5v { - drv_5v: drv-5v { - rockchip,pins = <7 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - hdmi { - vcc50_hdmi_en: vcc50-hdmi-en { - rockchip,pins = <5 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - dvs_1: dvs-1 { - rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - dvs_2: dvs-2 { - rockchip,pins = <7 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/rk3288-veyron-tiger.dts b/sys/gnu/dts/arm/rk3288-veyron-tiger.dts deleted file mode 100644 index 069f0c2c1fd..00000000000 --- a/sys/gnu/dts/arm/rk3288-veyron-tiger.dts +++ /dev/null @@ -1,87 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Veyron Tiger Rev 0+ board device tree source - * - * Copyright 2016 Google, Inc - */ - -/dts-v1/; -#include "rk3288-veyron-fievel.dts" -#include "rk3288-veyron-edp.dtsi" - -/ { - model = "Google Tiger"; - compatible = "google,veyron-tiger-rev8", "google,veyron-tiger-rev7", - "google,veyron-tiger-rev6", "google,veyron-tiger-rev5", - "google,veyron-tiger-rev4", "google,veyron-tiger-rev3", - "google,veyron-tiger-rev2", "google,veyron-tiger-rev1", - "google,veyron-tiger-rev0", "google,veyron-tiger", - "google,veyron", "rockchip,rk3288"; - - /delete-node/ vcc18-lcd; -}; - -&backlight { - /* Tiger panel PWM must be >= 1%, so start non-zero brightness at 3 */ - brightness-levels = <0 3 255>; - num-interpolated-steps = <252>; -}; - -&backlight_regulator { - vin-supply = <&vccsys>; -}; - -&i2c3 { - status = "okay"; - - clock-frequency = <400000>; - i2c-scl-falling-time-ns = <50>; - i2c-scl-rising-time-ns = <300>; - - touchscreen@10 { - compatible = "elan,ekth3500"; - reg = <0x10>; - interrupt-parent = <&gpio2>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&touch_int &touch_rst>; - reset-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_LOW>; - vcc33-supply = <&vcc33_io>; - vccio-supply = <&vcc33_io>; - wakeup-source; - }; -}; - -&panel { - compatible = "auo,b101ean01"; - - /delete-node/ panel-timing; - - panel-timing { - clock-frequency = <66666667>; - hactive = <1280>; - hfront-porch = <18>; - hback-porch = <21>; - hsync-len = <32>; - vactive = <800>; - vfront-porch = <4>; - vback-porch = <8>; - vsync-len = <18>; - }; -}; - -&pinctrl { - lcd { - /delete-node/ avdd-1v8-disp-en; - }; - - touchscreen { - touch_int: touch-int { - rockchip,pins = <2 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - touch_rst: touch-rst { - rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/rk3288-veyron.dtsi b/sys/gnu/dts/arm/rk3288-veyron.dtsi deleted file mode 100644 index 54a6838d73f..00000000000 --- a/sys/gnu/dts/arm/rk3288-veyron.dtsi +++ /dev/null @@ -1,593 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Veyron (and derivatives) board device tree source - * - * Copyright 2015 Google, Inc - */ - -#include -#include -#include "rk3288.dtsi" - -/ { - chosen { - stdout-path = "serial2:115200n8"; - }; - - /* - * The default coreboot on veyron devices ignores memory@0 nodes - * and would instead create another memory node. - */ - memory { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; - - - power_button: power-button { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pwr_key_l>; - - power { - label = "Power"; - gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <100>; - wakeup-source; - }; - }; - - gpio-restart { - compatible = "gpio-restart"; - gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&ap_warm_reset_h>; - priority = <200>; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - pinctrl-0 = <&emmc_reset>; - pinctrl-names = "default"; - reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_HIGH>; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&rk808 RK808_CLKOUT1>; - clock-names = "ext_clock"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_enable_h>; - - /* - * Depending on the actual card populated GPIO4 D4 - * correspond to one of these signals on the module: - * - * D4: - * - SDIO_RESET_L_WL_REG_ON - * - PDN (power down when low) - */ - reset-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>; - }; - - vcc_5v: vcc-5v { - compatible = "regulator-fixed"; - regulator-name = "vcc_5v"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - vcc33_sys: vcc33-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc33_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vcc50_hdmi: vcc50-hdmi { - compatible = "regulator-fixed"; - regulator-name = "vcc50_hdmi"; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_5v>; - }; - - vdd_logic: vdd-logic { - compatible = "pwm-regulator"; - regulator-name = "vdd_logic"; - - pwms = <&pwm1 0 1994 0>; - pwm-supply = <&vcc33_sys>; - - pwm-dutycycle-range = <0x7b 0>; - pwm-dutycycle-unit = <0x94>; - - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <4000>; - }; -}; - -&cpu0 { - cpu0-supply = <&vdd_cpu>; -}; - -&cpu_crit { - temperature = <100000>; -}; - -/* rk3288-c used in Veyron Chrome-devices has slightly changed OPPs */ -&cpu_opp_table { - /delete-node/ opp-312000000; - - opp-1512000000 { - opp-microvolt = <1250000>; - }; - opp-1608000000 { - opp-microvolt = <1300000>; - }; - opp-1704000000 { - opp-hz = /bits/ 64 <1704000000>; - opp-microvolt = <1350000>; - }; - opp-1800000000 { - opp-hz = /bits/ 64 <1800000000>; - opp-microvolt = <1400000>; - }; -}; - -&emmc { - status = "okay"; - - bus-width = <8>; - cap-mmc-highspeed; - rockchip,default-sample-phase = <158>; - disable-wp; - mmc-hs200-1_8v; - mmc-pwrseq = <&emmc_pwrseq>; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; -}; - -&gpu { - mali-supply = <&vdd_gpu>; - status = "okay"; -}; - -&gpu_alert0 { - temperature = <72500>; -}; - -&gpu_crit { - temperature = <100000>; -}; - -&hdmi { - pinctrl-names = "default", "unwedge"; - pinctrl-0 = <&hdmi_ddc>; - pinctrl-1 = <&hdmi_ddc_unwedge>; - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - clock-frequency = <400000>; - i2c-scl-falling-time-ns = <50>; /* 2.5ns measured */ - i2c-scl-rising-time-ns = <100>; /* 45ns measured */ - - rk808: pmic@1b { - compatible = "rockchip,rk808"; - reg = <0x1b>; - clock-output-names = "xin32k", "wifibt_32kin"; - interrupt-parent = <&gpio0>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l>; - rockchip,system-power-controller; - wakeup-source; - #clock-cells = <1>; - - vcc1-supply = <&vcc33_sys>; - vcc2-supply = <&vcc33_sys>; - vcc3-supply = <&vcc33_sys>; - vcc4-supply = <&vcc33_sys>; - vcc6-supply = <&vcc_5v>; - vcc7-supply = <&vcc33_sys>; - vcc8-supply = <&vcc33_sys>; - vcc12-supply = <&vcc_18>; - vddio-supply = <&vcc33_io>; - - regulators { - vdd_cpu: DCDC_REG1 { - regulator-name = "vdd_arm"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1450000>; - regulator-ramp-delay = <6001>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_gpu: DCDC_REG2 { - regulator-name = "vdd_gpu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1250000>; - regulator-ramp-delay = <6001>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc135_ddr: DCDC_REG3 { - regulator-name = "vcc135_ddr"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - /* - * vcc_18 has several aliases. (vcc18_flashio and - * vcc18_wl). We'll add those aliases here just to - * make it easier to follow the schematic. The signals - * are actually hooked together and only separated for - * power measurement purposes). - */ - vcc18_wl: vcc18_flashio: vcc_18: DCDC_REG4 { - regulator-name = "vcc_18"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - /* - * Note that both vcc33_io and vcc33_pmuio are always - * powered together. To simplify the logic in the dts - * we just refer to vcc33_io every time something is - * powered from vcc33_pmuio. In fact, on later boards - * (such as danger) they're the same net. - */ - vcc33_io: LDO_REG1 { - regulator-name = "vcc33_io"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vdd_10: LDO_REG3 { - regulator-name = "vdd_10"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vdd10_lcd_pwren_h: LDO_REG7 { - regulator-name = "vdd10_lcd_pwren_h"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc33_lcd: SWITCH_REG1 { - regulator-name = "vcc33_lcd"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; -}; - -&i2c1 { - status = "okay"; - - clock-frequency = <400000>; - i2c-scl-falling-time-ns = <50>; /* 2.5ns measured */ - i2c-scl-rising-time-ns = <100>; /* 40ns measured */ - - tpm: tpm@20 { - compatible = "infineon,slb9645tt"; - reg = <0x20>; - powered-while-suspended; - }; -}; - -&i2c2 { - status = "okay"; - - /* 100kHz since 4.7k resistors don't rise fast enough */ - clock-frequency = <100000>; - i2c-scl-falling-time-ns = <50>; /* 10ns measured */ - i2c-scl-rising-time-ns = <800>; /* 600ns measured */ -}; - -&i2c4 { - status = "okay"; - - clock-frequency = <400000>; - i2c-scl-falling-time-ns = <50>; /* 11ns measured */ - i2c-scl-rising-time-ns = <300>; /* 225ns measured */ -}; - -&io_domains { - status = "okay"; - - bb-supply = <&vcc33_io>; - dvp-supply = <&vcc_18>; - flash0-supply = <&vcc18_flashio>; - gpio1830-supply = <&vcc33_io>; - gpio30-supply = <&vcc33_io>; - lcdc-supply = <&vcc33_lcd>; - wifi-supply = <&vcc18_wl>; -}; - -&pwm1 { - status = "okay"; -}; - -&sdio0 { - status = "okay"; - - bus-width = <4>; - cap-sd-highspeed; - cap-sdio-irq; - keep-power-in-suspend; - mmc-pwrseq = <&sdio_pwrseq>; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_bus4>; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-sdr104; - vmmc-supply = <&vcc33_sys>; - vqmmc-supply = <&vcc18_wl>; -}; - -&spi2 { - status = "okay"; - - rx-sample-delay-ns = <12>; - - flash@0 { - compatible = "jedec,spi-nor"; - spi-max-frequency = <50000000>; - reg = <0>; - }; -}; - -&tsadc { - status = "okay"; - - rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */ - rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */ - rockchip,hw-tshut-temp = <125000>; -}; - -&uart0 { - status = "okay"; - - /* Pins don't include flow control by default; add that in */ - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; - - needs-reset-on-resume; -}; - -&usb_host1 { - status = "okay"; - snps,need-phy-for-wake; -}; - -&usb_otg { - status = "okay"; - - assigned-clocks = <&cru SCLK_USBPHY480M_SRC>; - assigned-clock-parents = <&usbphy0>; - dr_mode = "host"; - snps,need-phy-for-wake; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&wdt { - status = "okay"; -}; - -&pinctrl { - pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma { - bias-disable; - drive-strength = <8>; - }; - - pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma { - bias-pull-up; - drive-strength = <8>; - }; - - pcfg_output_high: pcfg-output-high { - output-high; - }; - - pcfg_output_low: pcfg-output-low { - output-low; - }; - - buttons { - pwr_key_l: pwr-key-l { - rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - emmc { - emmc_reset: emmc-reset { - rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - /* - * We run eMMC at max speed; bump up drive strength. - * We also have external pulls, so disable the internal ones. - */ - emmc_clk: emmc-clk { - rockchip,pins = <3 RK_PC2 2 &pcfg_pull_none_drv_8ma>; - }; - - emmc_cmd: emmc-cmd { - rockchip,pins = <3 RK_PC0 2 &pcfg_pull_none_drv_8ma>; - }; - - emmc_bus8: emmc-bus8 { - rockchip,pins = <3 RK_PA0 2 &pcfg_pull_none_drv_8ma>, - <3 RK_PA1 2 &pcfg_pull_none_drv_8ma>, - <3 RK_PA2 2 &pcfg_pull_none_drv_8ma>, - <3 RK_PA3 2 &pcfg_pull_none_drv_8ma>, - <3 RK_PA4 2 &pcfg_pull_none_drv_8ma>, - <3 RK_PA5 2 &pcfg_pull_none_drv_8ma>, - <3 RK_PA6 2 &pcfg_pull_none_drv_8ma>, - <3 RK_PA7 2 &pcfg_pull_none_drv_8ma>; - }; - }; - - pmic { - pmic_int_l: pmic-int-l { - rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - reboot { - ap_warm_reset_h: ap-warm-reset-h { - rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - recovery-switch { - rec_mode_l: rec-mode-l { - rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - sdio0 { - wifi_enable_h: wifienable-h { - rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - /* NOTE: mislabelled on schematic; should be bt_enable_h */ - bt_enable_l: bt-enable-l { - rockchip,pins = <4 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_host_wake: bt-host-wake { - rockchip,pins = <4 RK_PD7 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - bt_host_wake_l: bt-host-wake-l { - rockchip,pins = <4 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - /* - * We run sdio0 at max speed; bump up drive strength. - * We also have external pulls, so disable the internal ones. - */ - sdio0_bus4: sdio0-bus4 { - rockchip,pins = <4 RK_PC4 1 &pcfg_pull_none_drv_8ma>, - <4 RK_PC5 1 &pcfg_pull_none_drv_8ma>, - <4 RK_PC6 1 &pcfg_pull_none_drv_8ma>, - <4 RK_PC7 1 &pcfg_pull_none_drv_8ma>; - }; - - sdio0_cmd: sdio0-cmd { - rockchip,pins = <4 RK_PD0 1 &pcfg_pull_none_drv_8ma>; - }; - - sdio0_clk: sdio0-clk { - rockchip,pins = <4 RK_PD1 1 &pcfg_pull_none_drv_8ma>; - }; - - /* - * These pins are only present on very new veyron boards; on - * older boards bt_dev_wake is simply always high. Note that - * gpio4_D2 is a NC on old veyron boards, so it doesn't hurt - * to map this pin everywhere - */ - bt_dev_wake_sleep: bt-dev-wake-sleep { - rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_output_low>; - }; - - bt_dev_wake_awake: bt-dev-wake-awake { - rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_output_high>; - }; - - bt_dev_wake: bt-dev-wake { - rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - tpm { - tpm_int_h: tpm-int-h { - rockchip,pins = <7 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - write-protect { - fw_wp_ap: fw-wp-ap { - rockchip,pins = <7 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/rk3288-vyasa.dts b/sys/gnu/dts/arm/rk3288-vyasa.dts deleted file mode 100644 index ba06e9f97dd..00000000000 --- a/sys/gnu/dts/arm/rk3288-vyasa.dts +++ /dev/null @@ -1,471 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2017 Jagan Teki - */ - -/dts-v1/; -#include "rk3288.dtsi" - -/ { - model = "Amarula Vyasa-RK3288"; - compatible = "amarula,vyasa-rk3288", "rockchip,rk3288"; - - chosen { - stdout-path = &uart2; - }; - - memory { - reg = <0x0 0x0 0x0 0x80000000>; - device_type = "memory"; - }; - - dc12_vbat: dc12-vbat { - compatible = "regulator-fixed"; - regulator-name = "dc12_vbat"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-always-on; - regulator-boot-on; - }; - - vboot_3v3: vboot-3v3 { - compatible = "regulator-fixed"; - regulator-name = "vboot_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&dc12_vbat>; - }; - - vcc_sys: vsys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; - regulator-min-microvolt = <3700000>; - regulator-max-microvolt = <3700000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&dc12_vbat>; - }; - - vboot_5v: vboot-5v { - compatible = "regulator-fixed"; - regulator-name = "vboot_sv"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&dc12_vbat>; - }; - - v3g_3v3: v3g-3v3 { - compatible = "regulator-fixed"; - regulator-name = "v3g_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&dc12_vbat>; - }; - - vsus_5v: vsus-5v { - compatible = "regulator-fixed"; - regulator-name = "vsus_5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_io>; - }; - - vusb1_5v: vusb1-5v { - compatible = "regulator-fixed"; - regulator-name = "vusb1_5v"; - enable-active-high; - gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; /* OTG_VBUS_DRV */ - pinctrl-names = "default"; - pinctrl-0 = <&otg_vbus_drv>; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vsus_5v>; - }; - - vusb2_5v: vusb2-5v { - compatible = "regulator-fixed"; - regulator-name = "vusb2_5v"; - enable-active-high; - gpio = <&gpio8 RK_PB1 GPIO_ACTIVE_HIGH>; /* USB2_PWR_EN */ - pinctrl-names = "default"; - pinctrl-0 = <&usb2_pwr_en>; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vsus_5v>; - }; - - ext_gmac: external-gmac-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <125000000>; - clock-output-names = "ext_gmac"; - }; -}; - -&cpu0 { - cpu0-supply = <&vdd_cpu>; -}; - -&emmc { - bus-width = <8>; - cap-mmc-highspeed; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>; - vmmc-supply = <&vcc_io>; - status = "okay"; -}; - -&gmac { - assigned-clocks = <&cru SCLK_MAC>; - assigned-clock-parents = <&ext_gmac>; - clock_in_out = "input"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>, <&phy_rst>, <&phy_pmeb>, <&phy_int>; - phy-supply = <&vcc_lan>; - phy-mode = "rgmii"; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 1000000>; - snps,reset-gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_LOW>; - tx_delay = <0x30>; - rx_delay = <0x10>; - status = "okay"; -}; - -&gpu { - mali-supply = <&vdd_gpu>; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c2>; - status = "okay"; -}; - -&i2c0 { - clock-frequency = <400000>; - status = "okay"; - - rk808: pmic@1b { - compatible = "rockchip,rk808"; - reg = <0x1b>; - interrupt-parent = <&gpio0>; - interrupts = ; - #clock-cells = <1>; - clock-output-names = "xin32k", "rk808-clkout2"; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int &global_pwroff>; - rockchip,system-power-controller; - wakeup-source; - - vcc1-supply = <&vcc_sys>; - vcc2-supply = <&vcc_sys>; - vcc3-supply = <&vcc_sys>; - vcc4-supply = <&vcc_sys>; - vcc6-supply = <&vcc_sys>; - vcc7-supply = <&vcc_sys>; - vcc8-supply = <&vcc_io>; - vcc9-supply = <&vcc_sys>; - vcc10-supply = <&vcc_sys>; - vcc11-supply = <&vcc_sys>; - vcc12-supply = <&vcc_io>; - - regulators { - vdd_cpu: DCDC_REG1 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_gpu: DCDC_REG2 { - regulator-name = "vdd_gpu"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1250000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_io: DCDC_REG4 { - regulator-name = "vcc_io"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcca_tp: LDO_REG1 { - regulator-name = "vcc_tp"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc_codec: LDO_REG2 { - regulator-name = "vcc_codec"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_10: LDO_REG3 { - regulator-name = "vdd_10"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vcc_gps: LDO_REG4 { - regulator-name = "vcc_gps"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vccio_sd: LDO_REG5 { - regulator-name = "vccio_sd"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc10_lcd: LDO_REG6 { - regulator-name = "vcc10_lcd"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc_18: LDO_REG7 { - regulator-name = "vcc_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc18_lcd: LDO_REG8 { - regulator-name = "vcc18_lcd"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc_sd: SWITCH_REG1 { - regulator-name = "vcc_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_lan: SWITCH_REG2 { - regulator-name = "vcc_lan"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - }; - }; -}; - -&i2c2 { - status = "okay"; -}; - -&io_domains { - status = "okay"; - - audio-supply = <&vcc_18>; - bb-supply = <&vcc_io>; - dvp-supply = <&vcc_io>; - flash0-suuply = <&vcc_18>; - flash1-supply = <&vcc_lan>; - gpio30-supply = <&vcc_io>; - gpio1830 = <&vcc_io>; - lcdc-supply = <&vcc_io>; - sdcard-supply = <&vccio_sd>; - wifi-supply = <&vcc_18>; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - card-detect-delay = <200>; - disable-wp; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_cd>, <&sdmmc_bus4>; - vmmc-supply = <&vcc_sd>; - vqmmc-supply = <&vccio_sd>; - status = "okay"; -}; - -&tsadc { - rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */ - rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */ - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host1 { - pinctrl-names = "default"; - pinctrl-0 = <&phy_pwr_en>; - status = "okay"; -}; - -&usb_otg { - status = "okay"; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&vopl { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; -}; - -&wdt { - status = "okay"; -}; - -&pinctrl { - pcfg_output_high: pcfg-output-high { - output-high; - }; - - gmac { - phy_int: phy-int { - rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - phy_pmeb: phy-pmeb { - rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - phy_rst: phy-rst { - rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_output_high>; - }; - }; - - pmic { - pmic_int: pmic-int { - rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - usb_host { - phy_pwr_en: phy-pwr-en { - rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_output_high>; - }; - - usb2_pwr_en: usb2-pwr-en { - rockchip,pins = <8 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb_otg { - otg_vbus_drv: otg-vbus-drv { - rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; - - }; - }; -}; diff --git a/sys/gnu/dts/arm/rk3288.dtsi b/sys/gnu/dts/arm/rk3288.dtsi deleted file mode 100644 index 9beb662166a..00000000000 --- a/sys/gnu/dts/arm/rk3288.dtsi +++ /dev/null @@ -1,2001 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/ { - #address-cells = <2>; - #size-cells = <2>; - - compatible = "rockchip,rk3288"; - - interrupt-parent = <&gic>; - - aliases { - ethernet0 = &gmac; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - mshc0 = &emmc; - mshc1 = &sdmmc; - mshc2 = &sdio0; - mshc3 = &sdio1; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - serial4 = &uart4; - spi0 = &spi0; - spi1 = &spi1; - spi2 = &spi2; - }; - - arm-pmu { - compatible = "arm,cortex-a12-pmu"; - interrupts = , - , - , - ; - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "rockchip,rk3066-smp"; - rockchip,pmu = <&pmu>; - - cpu0: cpu@500 { - device_type = "cpu"; - compatible = "arm,cortex-a12"; - reg = <0x500>; - resets = <&cru SRST_CORE0>; - operating-points-v2 = <&cpu_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - clock-latency = <40000>; - clocks = <&cru ARMCLK>; - dynamic-power-coefficient = <370>; - }; - cpu1: cpu@501 { - device_type = "cpu"; - compatible = "arm,cortex-a12"; - reg = <0x501>; - resets = <&cru SRST_CORE1>; - operating-points-v2 = <&cpu_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - clock-latency = <40000>; - clocks = <&cru ARMCLK>; - dynamic-power-coefficient = <370>; - }; - cpu2: cpu@502 { - device_type = "cpu"; - compatible = "arm,cortex-a12"; - reg = <0x502>; - resets = <&cru SRST_CORE2>; - operating-points-v2 = <&cpu_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - clock-latency = <40000>; - clocks = <&cru ARMCLK>; - dynamic-power-coefficient = <370>; - }; - cpu3: cpu@503 { - device_type = "cpu"; - compatible = "arm,cortex-a12"; - reg = <0x503>; - resets = <&cru SRST_CORE3>; - operating-points-v2 = <&cpu_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - clock-latency = <40000>; - clocks = <&cru ARMCLK>; - dynamic-power-coefficient = <370>; - }; - }; - - cpu_opp_table: cpu-opp-table { - compatible = "operating-points-v2"; - opp-shared; - - opp-126000000 { - opp-hz = /bits/ 64 <126000000>; - opp-microvolt = <900000>; - }; - opp-216000000 { - opp-hz = /bits/ 64 <216000000>; - opp-microvolt = <900000>; - }; - opp-312000000 { - opp-hz = /bits/ 64 <312000000>; - opp-microvolt = <900000>; - }; - opp-408000000 { - opp-hz = /bits/ 64 <408000000>; - opp-microvolt = <900000>; - }; - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <900000>; - }; - opp-696000000 { - opp-hz = /bits/ 64 <696000000>; - opp-microvolt = <950000>; - }; - opp-816000000 { - opp-hz = /bits/ 64 <816000000>; - opp-microvolt = <1000000>; - }; - opp-1008000000 { - opp-hz = /bits/ 64 <1008000000>; - opp-microvolt = <1050000>; - }; - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <1100000>; - }; - opp-1416000000 { - opp-hz = /bits/ 64 <1416000000>; - opp-microvolt = <1200000>; - }; - opp-1512000000 { - opp-hz = /bits/ 64 <1512000000>; - opp-microvolt = <1300000>; - }; - opp-1608000000 { - opp-hz = /bits/ 64 <1608000000>; - opp-microvolt = <1350000>; - }; - }; - - amba { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - dmac_peri: dma-controller@ff250000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x0 0xff250000 0x0 0x4000>; - interrupts = , - ; - #dma-cells = <1>; - arm,pl330-broken-no-flushp; - clocks = <&cru ACLK_DMAC2>; - clock-names = "apb_pclk"; - }; - - dmac_bus_ns: dma-controller@ff600000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x0 0xff600000 0x0 0x4000>; - interrupts = , - ; - #dma-cells = <1>; - arm,pl330-broken-no-flushp; - clocks = <&cru ACLK_DMAC1>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - dmac_bus_s: dma-controller@ffb20000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x0 0xffb20000 0x0 0x4000>; - interrupts = , - ; - #dma-cells = <1>; - arm,pl330-broken-no-flushp; - clocks = <&cru ACLK_DMAC1>; - clock-names = "apb_pclk"; - }; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - /* - * The rk3288 cannot use the memory area above 0xfe000000 - * for dma operations for some reason. While there is - * probably a better solution available somewhere, we - * haven't found it yet and while devices with 2GB of ram - * are not affected, this issue prevents 4GB from booting. - * So to make these devices at least bootable, block - * this area for the time being until the real solution - * is found. - */ - dma-unusable@fe000000 { - reg = <0x0 0xfe000000 0x0 0x1000000>; - }; - }; - - xin24m: oscillator { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "xin24m"; - #clock-cells = <0>; - }; - - timer { - compatible = "arm,armv7-timer"; - arm,cpu-registers-not-fw-configured; - interrupts = , - , - , - ; - clock-frequency = <24000000>; - arm,no-tick-in-suspend; - }; - - timer: timer@ff810000 { - compatible = "rockchip,rk3288-timer"; - reg = <0x0 0xff810000 0x0 0x20>; - interrupts = ; - clocks = <&xin24m>, <&cru PCLK_TIMER>; - clock-names = "timer", "pclk"; - }; - - display-subsystem { - compatible = "rockchip,display-subsystem"; - ports = <&vopl_out>, <&vopb_out>; - }; - - sdmmc: mmc@ff0c0000 { - compatible = "rockchip,rk3288-dw-mshc"; - max-frequency = <150000000>; - clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, - <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - interrupts = ; - reg = <0x0 0xff0c0000 0x0 0x4000>; - resets = <&cru SRST_MMC0>; - reset-names = "reset"; - status = "disabled"; - }; - - sdio0: mmc@ff0d0000 { - compatible = "rockchip,rk3288-dw-mshc"; - max-frequency = <150000000>; - clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>, - <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - interrupts = ; - reg = <0x0 0xff0d0000 0x0 0x4000>; - resets = <&cru SRST_SDIO0>; - reset-names = "reset"; - status = "disabled"; - }; - - sdio1: mmc@ff0e0000 { - compatible = "rockchip,rk3288-dw-mshc"; - max-frequency = <150000000>; - clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>, - <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - interrupts = ; - reg = <0x0 0xff0e0000 0x0 0x4000>; - resets = <&cru SRST_SDIO1>; - reset-names = "reset"; - status = "disabled"; - }; - - emmc: mmc@ff0f0000 { - compatible = "rockchip,rk3288-dw-mshc"; - max-frequency = <150000000>; - clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, - <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - interrupts = ; - reg = <0x0 0xff0f0000 0x0 0x4000>; - resets = <&cru SRST_EMMC>; - reset-names = "reset"; - status = "disabled"; - }; - - saradc: saradc@ff100000 { - compatible = "rockchip,saradc"; - reg = <0x0 0xff100000 0x0 0x100>; - interrupts = ; - #io-channel-cells = <1>; - clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; - clock-names = "saradc", "apb_pclk"; - resets = <&cru SRST_SARADC>; - reset-names = "saradc-apb"; - status = "disabled"; - }; - - spi0: spi@ff110000 { - compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; - clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; - clock-names = "spiclk", "apb_pclk"; - dmas = <&dmac_peri 11>, <&dmac_peri 12>; - dma-names = "tx", "rx"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; - reg = <0x0 0xff110000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi1: spi@ff120000 { - compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; - clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; - clock-names = "spiclk", "apb_pclk"; - dmas = <&dmac_peri 13>, <&dmac_peri 14>; - dma-names = "tx", "rx"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; - reg = <0x0 0xff120000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi2: spi@ff130000 { - compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; - clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; - clock-names = "spiclk", "apb_pclk"; - dmas = <&dmac_peri 15>, <&dmac_peri 16>; - dma-names = "tx", "rx"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; - reg = <0x0 0xff130000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c1: i2c@ff140000 { - compatible = "rockchip,rk3288-i2c"; - reg = <0x0 0xff140000 0x0 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C1>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_xfer>; - status = "disabled"; - }; - - i2c3: i2c@ff150000 { - compatible = "rockchip,rk3288-i2c"; - reg = <0x0 0xff150000 0x0 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C3>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_xfer>; - status = "disabled"; - }; - - i2c4: i2c@ff160000 { - compatible = "rockchip,rk3288-i2c"; - reg = <0x0 0xff160000 0x0 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C4>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_xfer>; - status = "disabled"; - }; - - i2c5: i2c@ff170000 { - compatible = "rockchip,rk3288-i2c"; - reg = <0x0 0xff170000 0x0 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C5>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c5_xfer>; - status = "disabled"; - }; - - uart0: serial@ff180000 { - compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; - reg = <0x0 0xff180000 0x0 0x100>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; - clock-names = "baudclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer>; - status = "disabled"; - }; - - uart1: serial@ff190000 { - compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; - reg = <0x0 0xff190000 0x0 0x100>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; - clock-names = "baudclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart1_xfer>; - status = "disabled"; - }; - - uart2: serial@ff690000 { - compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; - reg = <0x0 0xff690000 0x0 0x100>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; - clock-names = "baudclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart2_xfer>; - status = "disabled"; - }; - - uart3: serial@ff1b0000 { - compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; - reg = <0x0 0xff1b0000 0x0 0x100>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; - clock-names = "baudclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart3_xfer>; - status = "disabled"; - }; - - uart4: serial@ff1c0000 { - compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; - reg = <0x0 0xff1c0000 0x0 0x100>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; - clock-names = "baudclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart4_xfer>; - status = "disabled"; - }; - - thermal-zones { - reserve_thermal: reserve_thermal { - polling-delay-passive = <1000>; /* milliseconds */ - polling-delay = <5000>; /* milliseconds */ - - thermal-sensors = <&tsadc 0>; - }; - - cpu_thermal: cpu_thermal { - polling-delay-passive = <100>; /* milliseconds */ - polling-delay = <5000>; /* milliseconds */ - - thermal-sensors = <&tsadc 1>; - - trips { - cpu_alert0: cpu_alert0 { - temperature = <70000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - cpu_alert1: cpu_alert1 { - temperature = <75000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - cpu_crit: cpu_crit { - temperature = <90000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu_alert0>; - cooling-device = - <&cpu0 THERMAL_NO_LIMIT 6>, - <&cpu1 THERMAL_NO_LIMIT 6>, - <&cpu2 THERMAL_NO_LIMIT 6>, - <&cpu3 THERMAL_NO_LIMIT 6>; - }; - map1 { - trip = <&cpu_alert1>; - cooling-device = - <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - gpu_thermal: gpu_thermal { - polling-delay-passive = <100>; /* milliseconds */ - polling-delay = <5000>; /* milliseconds */ - - thermal-sensors = <&tsadc 2>; - - trips { - gpu_alert0: gpu_alert0 { - temperature = <70000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - gpu_crit: gpu_crit { - temperature = <90000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&gpu_alert0>; - cooling-device = - <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - }; - - tsadc: tsadc@ff280000 { - compatible = "rockchip,rk3288-tsadc"; - reg = <0x0 0xff280000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; - clock-names = "tsadc", "apb_pclk"; - resets = <&cru SRST_TSADC>; - reset-names = "tsadc-apb"; - pinctrl-names = "init", "default", "sleep"; - pinctrl-0 = <&otp_gpio>; - pinctrl-1 = <&otp_out>; - pinctrl-2 = <&otp_gpio>; - #thermal-sensor-cells = <1>; - rockchip,grf = <&grf>; - rockchip,hw-tshut-temp = <95000>; - status = "disabled"; - }; - - gmac: ethernet@ff290000 { - compatible = "rockchip,rk3288-gmac"; - reg = <0x0 0xff290000 0x0 0x10000>; - interrupts = , - ; - interrupt-names = "macirq", "eth_wake_irq"; - rockchip,grf = <&grf>; - clocks = <&cru SCLK_MAC>, - <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>, - <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>, - <&cru ACLK_GMAC>, <&cru PCLK_GMAC>; - clock-names = "stmmaceth", - "mac_clk_rx", "mac_clk_tx", - "clk_mac_ref", "clk_mac_refout", - "aclk_mac", "pclk_mac"; - resets = <&cru SRST_MAC>; - reset-names = "stmmaceth"; - status = "disabled"; - }; - - usb_host0_ehci: usb@ff500000 { - compatible = "generic-ehci"; - reg = <0x0 0xff500000 0x0 0x100>; - interrupts = ; - clocks = <&cru HCLK_USBHOST0>; - clock-names = "usbhost"; - phys = <&usbphy1>; - phy-names = "usb"; - status = "disabled"; - }; - - /* NOTE: ohci@ff520000 doesn't actually work on hardware */ - - usb_host1: usb@ff540000 { - compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb", - "snps,dwc2"; - reg = <0x0 0xff540000 0x0 0x40000>; - interrupts = ; - clocks = <&cru HCLK_USBHOST1>; - clock-names = "otg"; - dr_mode = "host"; - phys = <&usbphy2>; - phy-names = "usb2-phy"; - snps,reset-phy-on-wake; - status = "disabled"; - }; - - usb_otg: usb@ff580000 { - compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb", - "snps,dwc2"; - reg = <0x0 0xff580000 0x0 0x40000>; - interrupts = ; - clocks = <&cru HCLK_OTG0>; - clock-names = "otg"; - dr_mode = "otg"; - g-np-tx-fifo-size = <16>; - g-rx-fifo-size = <275>; - g-tx-fifo-size = <256 128 128 64 64 32>; - phys = <&usbphy0>; - phy-names = "usb2-phy"; - status = "disabled"; - }; - - usb_hsic: usb@ff5c0000 { - compatible = "generic-ehci"; - reg = <0x0 0xff5c0000 0x0 0x100>; - interrupts = ; - clocks = <&cru HCLK_HSIC>; - clock-names = "usbhost"; - status = "disabled"; - }; - - i2c0: i2c@ff650000 { - compatible = "rockchip,rk3288-i2c"; - reg = <0x0 0xff650000 0x0 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_xfer>; - status = "disabled"; - }; - - i2c2: i2c@ff660000 { - compatible = "rockchip,rk3288-i2c"; - reg = <0x0 0xff660000 0x0 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C2>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_xfer>; - status = "disabled"; - }; - - pwm0: pwm@ff680000 { - compatible = "rockchip,rk3288-pwm"; - reg = <0x0 0xff680000 0x0 0x10>; - #pwm-cells = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pin>; - clocks = <&cru PCLK_RKPWM>; - clock-names = "pwm"; - status = "disabled"; - }; - - pwm1: pwm@ff680010 { - compatible = "rockchip,rk3288-pwm"; - reg = <0x0 0xff680010 0x0 0x10>; - #pwm-cells = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm1_pin>; - clocks = <&cru PCLK_RKPWM>; - clock-names = "pwm"; - status = "disabled"; - }; - - pwm2: pwm@ff680020 { - compatible = "rockchip,rk3288-pwm"; - reg = <0x0 0xff680020 0x0 0x10>; - #pwm-cells = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm2_pin>; - clocks = <&cru PCLK_RKPWM>; - clock-names = "pwm"; - status = "disabled"; - }; - - pwm3: pwm@ff680030 { - compatible = "rockchip,rk3288-pwm"; - reg = <0x0 0xff680030 0x0 0x10>; - #pwm-cells = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm3_pin>; - clocks = <&cru PCLK_RKPWM>; - clock-names = "pwm"; - status = "disabled"; - }; - - bus_intmem@ff700000 { - compatible = "mmio-sram"; - reg = <0x0 0xff700000 0x0 0x18000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x0 0xff700000 0x18000>; - smp-sram@0 { - compatible = "rockchip,rk3066-smp-sram"; - reg = <0x00 0x10>; - }; - }; - - sram@ff720000 { - compatible = "rockchip,rk3288-pmu-sram", "mmio-sram"; - reg = <0x0 0xff720000 0x0 0x1000>; - }; - - pmu: power-management@ff730000 { - compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd"; - reg = <0x0 0xff730000 0x0 0x100>; - - power: power-controller { - compatible = "rockchip,rk3288-power-controller"; - #power-domain-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - - assigned-clocks = <&cru SCLK_EDP_24M>; - assigned-clock-parents = <&xin24m>; - - /* - * Note: Although SCLK_* are the working clocks - * of device without including on the NOC, needed for - * synchronous reset. - * - * The clocks on the which NOC: - * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU. - * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU. - * ACLK_RGA is on ACLK_RGA_NIU. - * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU. - * - * Which clock are device clocks: - * clocks devices - * *_IEP IEP:Image Enhancement Processor - * *_ISP ISP:Image Signal Processing - * *_VIP VIP:Video Input Processor - * *_VOP* VOP:Visual Output Processor - * *_RGA RGA - * *_EDP* EDP - * *_LVDS_* LVDS - * *_HDMI HDMI - * *_MIPI_* MIPI - */ - pd_vio@RK3288_PD_VIO { - reg = ; - clocks = <&cru ACLK_IEP>, - <&cru ACLK_ISP>, - <&cru ACLK_RGA>, - <&cru ACLK_VIP>, - <&cru ACLK_VOP0>, - <&cru ACLK_VOP1>, - <&cru DCLK_VOP0>, - <&cru DCLK_VOP1>, - <&cru HCLK_IEP>, - <&cru HCLK_ISP>, - <&cru HCLK_RGA>, - <&cru HCLK_VIP>, - <&cru HCLK_VOP0>, - <&cru HCLK_VOP1>, - <&cru PCLK_EDP_CTRL>, - <&cru PCLK_HDMI_CTRL>, - <&cru PCLK_LVDS_PHY>, - <&cru PCLK_MIPI_CSI>, - <&cru PCLK_MIPI_DSI0>, - <&cru PCLK_MIPI_DSI1>, - <&cru SCLK_EDP_24M>, - <&cru SCLK_EDP>, - <&cru SCLK_ISP_JPE>, - <&cru SCLK_ISP>, - <&cru SCLK_RGA>; - pm_qos = <&qos_vio0_iep>, - <&qos_vio1_vop>, - <&qos_vio1_isp_w0>, - <&qos_vio1_isp_w1>, - <&qos_vio0_vop>, - <&qos_vio0_vip>, - <&qos_vio2_rga_r>, - <&qos_vio2_rga_w>, - <&qos_vio1_isp_r>; - }; - - /* - * Note: The following 3 are HEVC(H.265) clocks, - * and on the ACLK_HEVC_NIU (NOC). - */ - pd_hevc@RK3288_PD_HEVC { - reg = ; - clocks = <&cru ACLK_HEVC>, - <&cru SCLK_HEVC_CABAC>, - <&cru SCLK_HEVC_CORE>; - pm_qos = <&qos_hevc_r>, - <&qos_hevc_w>; - }; - - /* - * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC - * (video endecoder & decoder) clocks that on the - * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC). - */ - pd_video@RK3288_PD_VIDEO { - reg = ; - clocks = <&cru ACLK_VCODEC>, - <&cru HCLK_VCODEC>; - pm_qos = <&qos_video>; - }; - - /* - * Note: ACLK_GPU is the GPU clock, - * and on the ACLK_GPU_NIU (NOC). - */ - pd_gpu@RK3288_PD_GPU { - reg = ; - clocks = <&cru ACLK_GPU>; - pm_qos = <&qos_gpu_r>, - <&qos_gpu_w>; - }; - }; - - reboot-mode { - compatible = "syscon-reboot-mode"; - offset = <0x94>; - mode-normal = ; - mode-recovery = ; - mode-bootloader = ; - mode-loader = ; - }; - }; - - sgrf: syscon@ff740000 { - compatible = "rockchip,rk3288-sgrf", "syscon"; - reg = <0x0 0xff740000 0x0 0x1000>; - }; - - cru: clock-controller@ff760000 { - compatible = "rockchip,rk3288-cru"; - reg = <0x0 0xff760000 0x0 0x1000>; - rockchip,grf = <&grf>; - #clock-cells = <1>; - #reset-cells = <1>; - assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>, - <&cru PLL_NPLL>, <&cru ACLK_CPU>, - <&cru HCLK_CPU>, <&cru PCLK_CPU>, - <&cru ACLK_PERI>, <&cru HCLK_PERI>, - <&cru PCLK_PERI>; - assigned-clock-rates = <594000000>, <400000000>, - <500000000>, <300000000>, - <150000000>, <75000000>, - <300000000>, <150000000>, - <75000000>; - }; - - grf: syscon@ff770000 { - compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd"; - reg = <0x0 0xff770000 0x0 0x1000>; - - edp_phy: edp-phy { - compatible = "rockchip,rk3288-dp-phy"; - clocks = <&cru SCLK_EDP_24M>; - clock-names = "24m"; - #phy-cells = <0>; - status = "disabled"; - }; - - io_domains: io-domains { - compatible = "rockchip,rk3288-io-voltage-domain"; - status = "disabled"; - }; - - usbphy: usbphy { - compatible = "rockchip,rk3288-usb-phy"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - usbphy0: usb-phy@320 { - #phy-cells = <0>; - reg = <0x320>; - clocks = <&cru SCLK_OTGPHY0>; - clock-names = "phyclk"; - #clock-cells = <0>; - resets = <&cru SRST_USBOTG_PHY>; - reset-names = "phy-reset"; - }; - - usbphy1: usb-phy@334 { - #phy-cells = <0>; - reg = <0x334>; - clocks = <&cru SCLK_OTGPHY1>; - clock-names = "phyclk"; - #clock-cells = <0>; - resets = <&cru SRST_USBHOST0_PHY>; - reset-names = "phy-reset"; - }; - - usbphy2: usb-phy@348 { - #phy-cells = <0>; - reg = <0x348>; - clocks = <&cru SCLK_OTGPHY2>; - clock-names = "phyclk"; - #clock-cells = <0>; - resets = <&cru SRST_USBHOST1_PHY>; - reset-names = "phy-reset"; - }; - }; - }; - - wdt: watchdog@ff800000 { - compatible = "rockchip,rk3288-wdt", "snps,dw-wdt"; - reg = <0x0 0xff800000 0x0 0x100>; - clocks = <&cru PCLK_WDT>; - interrupts = ; - status = "disabled"; - }; - - spdif: sound@ff88b0000 { - compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif"; - reg = <0x0 0xff8b0000 0x0 0x10000>; - #sound-dai-cells = <0>; - clock-names = "hclk", "mclk"; - clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>; - dmas = <&dmac_bus_s 3>; - dma-names = "tx"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&spdif_tx>; - rockchip,grf = <&grf>; - status = "disabled"; - }; - - i2s: i2s@ff890000 { - compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s"; - reg = <0x0 0xff890000 0x0 0x10000>; - #sound-dai-cells = <0>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>; - dma-names = "tx", "rx"; - clock-names = "i2s_hclk", "i2s_clk"; - clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_bus>; - rockchip,playback-channels = <8>; - rockchip,capture-channels = <2>; - status = "disabled"; - }; - - crypto: cypto-controller@ff8a0000 { - compatible = "rockchip,rk3288-crypto"; - reg = <0x0 0xff8a0000 0x0 0x4000>; - interrupts = ; - clocks = <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>, - <&cru SCLK_CRYPTO>, <&cru ACLK_DMAC1>; - clock-names = "aclk", "hclk", "sclk", "apb_pclk"; - resets = <&cru SRST_CRYPTO>; - reset-names = "crypto-rst"; - status = "okay"; - }; - - iep_mmu: iommu@ff900800 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff900800 0x0 0x40>; - interrupts = ; - interrupt-names = "iep_mmu"; - clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; - clock-names = "aclk", "iface"; - #iommu-cells = <0>; - status = "disabled"; - }; - - isp_mmu: iommu@ff914000 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>; - interrupts = ; - interrupt-names = "isp_mmu"; - clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>; - clock-names = "aclk", "iface"; - #iommu-cells = <0>; - rockchip,disable-mmu-reset; - status = "disabled"; - }; - - rga: rga@ff920000 { - compatible = "rockchip,rk3288-rga"; - reg = <0x0 0xff920000 0x0 0x180>; - interrupts = ; - clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>; - clock-names = "aclk", "hclk", "sclk"; - power-domains = <&power RK3288_PD_VIO>; - resets = <&cru SRST_RGA_CORE>, <&cru SRST_RGA_AXI>, <&cru SRST_RGA_AHB>; - reset-names = "core", "axi", "ahb"; - }; - - vopb: vop@ff930000 { - compatible = "rockchip,rk3288-vop"; - reg = <0x0 0xff930000 0x0 0x19c>, <0x0 0xff931000 0x0 0x1000>; - interrupts = ; - clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>; - clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; - power-domains = <&power RK3288_PD_VIO>; - resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>; - reset-names = "axi", "ahb", "dclk"; - iommus = <&vopb_mmu>; - status = "disabled"; - - vopb_out: port { - #address-cells = <1>; - #size-cells = <0>; - - vopb_out_hdmi: endpoint@0 { - reg = <0>; - remote-endpoint = <&hdmi_in_vopb>; - }; - - vopb_out_edp: endpoint@1 { - reg = <1>; - remote-endpoint = <&edp_in_vopb>; - }; - - vopb_out_mipi: endpoint@2 { - reg = <2>; - remote-endpoint = <&mipi_in_vopb>; - }; - - vopb_out_lvds: endpoint@3 { - reg = <3>; - remote-endpoint = <&lvds_in_vopb>; - }; - }; - }; - - vopb_mmu: iommu@ff930300 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff930300 0x0 0x100>; - interrupts = ; - interrupt-names = "vopb_mmu"; - clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; - clock-names = "aclk", "iface"; - power-domains = <&power RK3288_PD_VIO>; - #iommu-cells = <0>; - status = "disabled"; - }; - - vopl: vop@ff940000 { - compatible = "rockchip,rk3288-vop"; - reg = <0x0 0xff940000 0x0 0x19c>, <0x0 0xff941000 0x0 0x1000>; - interrupts = ; - clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>; - clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; - power-domains = <&power RK3288_PD_VIO>; - resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>; - reset-names = "axi", "ahb", "dclk"; - iommus = <&vopl_mmu>; - status = "disabled"; - - vopl_out: port { - #address-cells = <1>; - #size-cells = <0>; - - vopl_out_hdmi: endpoint@0 { - reg = <0>; - remote-endpoint = <&hdmi_in_vopl>; - }; - - vopl_out_edp: endpoint@1 { - reg = <1>; - remote-endpoint = <&edp_in_vopl>; - }; - - vopl_out_mipi: endpoint@2 { - reg = <2>; - remote-endpoint = <&mipi_in_vopl>; - }; - - vopl_out_lvds: endpoint@3 { - reg = <3>; - remote-endpoint = <&lvds_in_vopl>; - }; - }; - }; - - vopl_mmu: iommu@ff940300 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff940300 0x0 0x100>; - interrupts = ; - interrupt-names = "vopl_mmu"; - clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; - clock-names = "aclk", "iface"; - power-domains = <&power RK3288_PD_VIO>; - #iommu-cells = <0>; - status = "disabled"; - }; - - mipi_dsi: mipi@ff960000 { - compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi"; - reg = <0x0 0xff960000 0x0 0x4000>; - interrupts = ; - clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>; - clock-names = "ref", "pclk"; - power-domains = <&power RK3288_PD_VIO>; - rockchip,grf = <&grf>; - status = "disabled"; - - ports { - mipi_in: port { - #address-cells = <1>; - #size-cells = <0>; - mipi_in_vopb: endpoint@0 { - reg = <0>; - remote-endpoint = <&vopb_out_mipi>; - }; - mipi_in_vopl: endpoint@1 { - reg = <1>; - remote-endpoint = <&vopl_out_mipi>; - }; - }; - }; - }; - - lvds: lvds@ff96c000 { - compatible = "rockchip,rk3288-lvds"; - reg = <0x0 0xff96c000 0x0 0x4000>; - clocks = <&cru PCLK_LVDS_PHY>; - clock-names = "pclk_lvds"; - pinctrl-names = "lcdc"; - pinctrl-0 = <&lcdc_ctl>; - power-domains = <&power RK3288_PD_VIO>; - rockchip,grf = <&grf>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - lvds_in: port@0 { - reg = <0>; - - #address-cells = <1>; - #size-cells = <0>; - - lvds_in_vopb: endpoint@0 { - reg = <0>; - remote-endpoint = <&vopb_out_lvds>; - }; - lvds_in_vopl: endpoint@1 { - reg = <1>; - remote-endpoint = <&vopl_out_lvds>; - }; - }; - }; - }; - - edp: dp@ff970000 { - compatible = "rockchip,rk3288-dp"; - reg = <0x0 0xff970000 0x0 0x4000>; - interrupts = ; - clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>; - clock-names = "dp", "pclk"; - phys = <&edp_phy>; - phy-names = "dp"; - resets = <&cru SRST_EDP>; - reset-names = "dp"; - rockchip,grf = <&grf>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - edp_in: port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - edp_in_vopb: endpoint@0 { - reg = <0>; - remote-endpoint = <&vopb_out_edp>; - }; - edp_in_vopl: endpoint@1 { - reg = <1>; - remote-endpoint = <&vopl_out_edp>; - }; - }; - }; - }; - - hdmi: hdmi@ff980000 { - compatible = "rockchip,rk3288-dw-hdmi"; - reg = <0x0 0xff980000 0x0 0x20000>; - reg-io-width = <4>; - #sound-dai-cells = <0>; - rockchip,grf = <&grf>; - interrupts = ; - clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>, <&cru SCLK_HDMI_CEC>; - clock-names = "iahb", "isfr", "cec"; - power-domains = <&power RK3288_PD_VIO>; - status = "disabled"; - - ports { - hdmi_in: port { - #address-cells = <1>; - #size-cells = <0>; - hdmi_in_vopb: endpoint@0 { - reg = <0>; - remote-endpoint = <&vopb_out_hdmi>; - }; - hdmi_in_vopl: endpoint@1 { - reg = <1>; - remote-endpoint = <&vopl_out_hdmi>; - }; - }; - }; - }; - - vpu: video-codec@ff9a0000 { - compatible = "rockchip,rk3288-vpu"; - reg = <0x0 0xff9a0000 0x0 0x800>; - interrupts = , - ; - interrupt-names = "vepu", "vdpu"; - clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; - clock-names = "aclk", "hclk"; - iommus = <&vpu_mmu>; - power-domains = <&power RK3288_PD_VIDEO>; - }; - - vpu_mmu: iommu@ff9a0800 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff9a0800 0x0 0x100>; - interrupts = ; - interrupt-names = "vpu_mmu"; - clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; - clock-names = "aclk", "iface"; - #iommu-cells = <0>; - power-domains = <&power RK3288_PD_VIDEO>; - }; - - hevc_mmu: iommu@ff9c0440 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff9c0440 0x0 0x40>, <0x0 0xff9c0480 0x0 0x40>; - interrupts = ; - interrupt-names = "hevc_mmu"; - clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>; - clock-names = "aclk", "iface"; - #iommu-cells = <0>; - status = "disabled"; - }; - - gpu: gpu@ffa30000 { - compatible = "rockchip,rk3288-mali", "arm,mali-t760"; - reg = <0x0 0xffa30000 0x0 0x10000>; - interrupts = , - , - ; - interrupt-names = "job", "mmu", "gpu"; - clocks = <&cru ACLK_GPU>; - operating-points-v2 = <&gpu_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - power-domains = <&power RK3288_PD_GPU>; - status = "disabled"; - }; - - gpu_opp_table: gpu-opp-table { - compatible = "operating-points-v2"; - - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - opp-microvolt = <950000>; - }; - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - opp-microvolt = <950000>; - }; - opp-300000000 { - opp-hz = /bits/ 64 <300000000>; - opp-microvolt = <1000000>; - }; - opp-400000000 { - opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <1100000>; - }; - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <1250000>; - }; - }; - - qos_gpu_r: qos@ffaa0000 { - compatible = "syscon"; - reg = <0x0 0xffaa0000 0x0 0x20>; - }; - - qos_gpu_w: qos@ffaa0080 { - compatible = "syscon"; - reg = <0x0 0xffaa0080 0x0 0x20>; - }; - - qos_vio1_vop: qos@ffad0000 { - compatible = "syscon"; - reg = <0x0 0xffad0000 0x0 0x20>; - }; - - qos_vio1_isp_w0: qos@ffad0100 { - compatible = "syscon"; - reg = <0x0 0xffad0100 0x0 0x20>; - }; - - qos_vio1_isp_w1: qos@ffad0180 { - compatible = "syscon"; - reg = <0x0 0xffad0180 0x0 0x20>; - }; - - qos_vio0_vop: qos@ffad0400 { - compatible = "syscon"; - reg = <0x0 0xffad0400 0x0 0x20>; - }; - - qos_vio0_vip: qos@ffad0480 { - compatible = "syscon"; - reg = <0x0 0xffad0480 0x0 0x20>; - }; - - qos_vio0_iep: qos@ffad0500 { - compatible = "syscon"; - reg = <0x0 0xffad0500 0x0 0x20>; - }; - - qos_vio2_rga_r: qos@ffad0800 { - compatible = "syscon"; - reg = <0x0 0xffad0800 0x0 0x20>; - }; - - qos_vio2_rga_w: qos@ffad0880 { - compatible = "syscon"; - reg = <0x0 0xffad0880 0x0 0x20>; - }; - - qos_vio1_isp_r: qos@ffad0900 { - compatible = "syscon"; - reg = <0x0 0xffad0900 0x0 0x20>; - }; - - qos_video: qos@ffae0000 { - compatible = "syscon"; - reg = <0x0 0xffae0000 0x0 0x20>; - }; - - qos_hevc_r: qos@ffaf0000 { - compatible = "syscon"; - reg = <0x0 0xffaf0000 0x0 0x20>; - }; - - qos_hevc_w: qos@ffaf0080 { - compatible = "syscon"; - reg = <0x0 0xffaf0080 0x0 0x20>; - }; - - efuse: efuse@ffb40000 { - compatible = "rockchip,rk3288-efuse"; - reg = <0x0 0xffb40000 0x0 0x20>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&cru PCLK_EFUSE256>; - clock-names = "pclk_efuse"; - - cpu_id: cpu-id@7 { - reg = <0x07 0x10>; - }; - cpu_leakage: cpu_leakage@17 { - reg = <0x17 0x1>; - }; - }; - - gic: interrupt-controller@ffc01000 { - compatible = "arm,gic-400"; - interrupt-controller; - #interrupt-cells = <3>; - #address-cells = <0>; - - reg = <0x0 0xffc01000 0x0 0x1000>, - <0x0 0xffc02000 0x0 0x2000>, - <0x0 0xffc04000 0x0 0x2000>, - <0x0 0xffc06000 0x0 0x2000>; - interrupts = ; - }; - - pinctrl: pinctrl { - compatible = "rockchip,rk3288-pinctrl"; - rockchip,grf = <&grf>; - rockchip,pmu = <&pmu>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - gpio0: gpio0@ff750000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff750000 0x0 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO0>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio1@ff780000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff780000 0x0 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO1>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio2@ff790000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff790000 0x0 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO2>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio3@ff7a0000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff7a0000 0x0 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO3>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio4: gpio4@ff7b0000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff7b0000 0x0 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO4>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio5: gpio5@ff7c0000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff7c0000 0x0 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO5>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio6: gpio6@ff7d0000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff7d0000 0x0 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO6>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio7: gpio7@ff7e0000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff7e0000 0x0 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO7>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio8: gpio8@ff7f0000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff7f0000 0x0 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO8>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - hdmi { - hdmi_cec_c0: hdmi-cec-c0 { - rockchip,pins = <7 RK_PC0 2 &pcfg_pull_none>; - }; - - hdmi_cec_c7: hdmi-cec-c7 { - rockchip,pins = <7 RK_PC7 4 &pcfg_pull_none>; - }; - - hdmi_ddc: hdmi-ddc { - rockchip,pins = <7 RK_PC3 2 &pcfg_pull_none>, - <7 RK_PC4 2 &pcfg_pull_none>; - }; - - hdmi_ddc_unwedge: hdmi-ddc-unwedge { - rockchip,pins = <7 RK_PC3 RK_FUNC_GPIO &pcfg_output_low>, - <7 RK_PC4 2 &pcfg_pull_none>; - }; - }; - - pcfg_output_low: pcfg-output-low { - output-low; - }; - - pcfg_pull_up: pcfg-pull-up { - bias-pull-up; - }; - - pcfg_pull_down: pcfg-pull-down { - bias-pull-down; - }; - - pcfg_pull_none: pcfg-pull-none { - bias-disable; - }; - - pcfg_pull_none_12ma: pcfg-pull-none-12ma { - bias-disable; - drive-strength = <12>; - }; - - sleep { - global_pwroff: global-pwroff { - rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>; - }; - - ddrio_pwroff: ddrio-pwroff { - rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>; - }; - - ddr0_retention: ddr0-retention { - rockchip,pins = <0 RK_PA2 1 &pcfg_pull_up>; - }; - - ddr1_retention: ddr1-retention { - rockchip,pins = <0 RK_PA3 1 &pcfg_pull_up>; - }; - }; - - edp { - edp_hpd: edp-hpd { - rockchip,pins = <7 RK_PB3 2 &pcfg_pull_down>; - }; - }; - - i2c0 { - i2c0_xfer: i2c0-xfer { - rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>, - <0 RK_PC0 1 &pcfg_pull_none>; - }; - }; - - i2c1 { - i2c1_xfer: i2c1-xfer { - rockchip,pins = <8 RK_PA4 1 &pcfg_pull_none>, - <8 RK_PA5 1 &pcfg_pull_none>; - }; - }; - - i2c2 { - i2c2_xfer: i2c2-xfer { - rockchip,pins = <6 RK_PB1 1 &pcfg_pull_none>, - <6 RK_PB2 1 &pcfg_pull_none>; - }; - }; - - i2c3 { - i2c3_xfer: i2c3-xfer { - rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>, - <2 RK_PC1 1 &pcfg_pull_none>; - }; - }; - - i2c4 { - i2c4_xfer: i2c4-xfer { - rockchip,pins = <7 RK_PC1 1 &pcfg_pull_none>, - <7 RK_PC2 1 &pcfg_pull_none>; - }; - }; - - i2c5 { - i2c5_xfer: i2c5-xfer { - rockchip,pins = <7 RK_PC3 1 &pcfg_pull_none>, - <7 RK_PC4 1 &pcfg_pull_none>; - }; - }; - - i2s0 { - i2s0_bus: i2s0-bus { - rockchip,pins = <6 RK_PA0 1 &pcfg_pull_none>, - <6 RK_PA1 1 &pcfg_pull_none>, - <6 RK_PA2 1 &pcfg_pull_none>, - <6 RK_PA3 1 &pcfg_pull_none>, - <6 RK_PA4 1 &pcfg_pull_none>, - <6 RK_PB0 1 &pcfg_pull_none>; - }; - }; - - lcdc { - lcdc_ctl: lcdc-ctl { - rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>, - <1 RK_PD1 1 &pcfg_pull_none>, - <1 RK_PD2 1 &pcfg_pull_none>, - <1 RK_PD3 1 &pcfg_pull_none>; - }; - }; - - sdmmc { - sdmmc_clk: sdmmc-clk { - rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none>; - }; - - sdmmc_cmd: sdmmc-cmd { - rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up>; - }; - - sdmmc_cd: sdmmc-cd { - rockchip,pins = <6 RK_PC6 1 &pcfg_pull_up>; - }; - - sdmmc_bus1: sdmmc-bus1 { - rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up>; - }; - - sdmmc_bus4: sdmmc-bus4 { - rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up>, - <6 RK_PC1 1 &pcfg_pull_up>, - <6 RK_PC2 1 &pcfg_pull_up>, - <6 RK_PC3 1 &pcfg_pull_up>; - }; - }; - - sdio0 { - sdio0_bus1: sdio0-bus1 { - rockchip,pins = <4 RK_PC4 1 &pcfg_pull_up>; - }; - - sdio0_bus4: sdio0-bus4 { - rockchip,pins = <4 RK_PC4 1 &pcfg_pull_up>, - <4 RK_PC5 1 &pcfg_pull_up>, - <4 RK_PC6 1 &pcfg_pull_up>, - <4 RK_PC7 1 &pcfg_pull_up>; - }; - - sdio0_cmd: sdio0-cmd { - rockchip,pins = <4 RK_PD0 1 &pcfg_pull_up>; - }; - - sdio0_clk: sdio0-clk { - rockchip,pins = <4 RK_PD1 1 &pcfg_pull_none>; - }; - - sdio0_cd: sdio0-cd { - rockchip,pins = <4 RK_PD2 1 &pcfg_pull_up>; - }; - - sdio0_wp: sdio0-wp { - rockchip,pins = <4 RK_PD3 1 &pcfg_pull_up>; - }; - - sdio0_pwr: sdio0-pwr { - rockchip,pins = <4 RK_PD4 1 &pcfg_pull_up>; - }; - - sdio0_bkpwr: sdio0-bkpwr { - rockchip,pins = <4 RK_PD5 1 &pcfg_pull_up>; - }; - - sdio0_int: sdio0-int { - rockchip,pins = <4 RK_PD6 1 &pcfg_pull_up>; - }; - }; - - sdio1 { - sdio1_bus1: sdio1-bus1 { - rockchip,pins = <3 RK_PD0 4 &pcfg_pull_up>; - }; - - sdio1_bus4: sdio1-bus4 { - rockchip,pins = <3 RK_PD0 4 &pcfg_pull_up>, - <3 RK_PD1 4 &pcfg_pull_up>, - <3 RK_PD2 4 &pcfg_pull_up>, - <3 RK_PD3 4 &pcfg_pull_up>; - }; - - sdio1_cd: sdio1-cd { - rockchip,pins = <3 RK_PD4 4 &pcfg_pull_up>; - }; - - sdio1_wp: sdio1-wp { - rockchip,pins = <3 RK_PD5 4 &pcfg_pull_up>; - }; - - sdio1_bkpwr: sdio1-bkpwr { - rockchip,pins = <3 RK_PD6 4 &pcfg_pull_up>; - }; - - sdio1_int: sdio1-int { - rockchip,pins = <3 RK_PD7 4 &pcfg_pull_up>; - }; - - sdio1_cmd: sdio1-cmd { - rockchip,pins = <4 RK_PA6 4 &pcfg_pull_up>; - }; - - sdio1_clk: sdio1-clk { - rockchip,pins = <4 RK_PA7 4 &pcfg_pull_none>; - }; - - sdio1_pwr: sdio1-pwr { - rockchip,pins = <4 RK_PB1 4 &pcfg_pull_up>; - }; - }; - - emmc { - emmc_clk: emmc-clk { - rockchip,pins = <3 RK_PC2 2 &pcfg_pull_none>; - }; - - emmc_cmd: emmc-cmd { - rockchip,pins = <3 RK_PC0 2 &pcfg_pull_up>; - }; - - emmc_pwr: emmc-pwr { - rockchip,pins = <3 RK_PB1 2 &pcfg_pull_up>; - }; - - emmc_bus1: emmc-bus1 { - rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>; - }; - - emmc_bus4: emmc-bus4 { - rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>, - <3 RK_PA1 2 &pcfg_pull_up>, - <3 RK_PA2 2 &pcfg_pull_up>, - <3 RK_PA3 2 &pcfg_pull_up>; - }; - - emmc_bus8: emmc-bus8 { - rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>, - <3 RK_PA1 2 &pcfg_pull_up>, - <3 RK_PA2 2 &pcfg_pull_up>, - <3 RK_PA3 2 &pcfg_pull_up>, - <3 RK_PA4 2 &pcfg_pull_up>, - <3 RK_PA5 2 &pcfg_pull_up>, - <3 RK_PA6 2 &pcfg_pull_up>, - <3 RK_PA7 2 &pcfg_pull_up>; - }; - }; - - spi0 { - spi0_clk: spi0-clk { - rockchip,pins = <5 RK_PB4 1 &pcfg_pull_up>; - }; - spi0_cs0: spi0-cs0 { - rockchip,pins = <5 RK_PB5 1 &pcfg_pull_up>; - }; - spi0_tx: spi0-tx { - rockchip,pins = <5 RK_PB6 1 &pcfg_pull_up>; - }; - spi0_rx: spi0-rx { - rockchip,pins = <5 RK_PB7 1 &pcfg_pull_up>; - }; - spi0_cs1: spi0-cs1 { - rockchip,pins = <5 RK_PC0 1 &pcfg_pull_up>; - }; - }; - spi1 { - spi1_clk: spi1-clk { - rockchip,pins = <7 RK_PB4 2 &pcfg_pull_up>; - }; - spi1_cs0: spi1-cs0 { - rockchip,pins = <7 RK_PB5 2 &pcfg_pull_up>; - }; - spi1_rx: spi1-rx { - rockchip,pins = <7 RK_PB6 2 &pcfg_pull_up>; - }; - spi1_tx: spi1-tx { - rockchip,pins = <7 RK_PB7 2 &pcfg_pull_up>; - }; - }; - - spi2 { - spi2_cs1: spi2-cs1 { - rockchip,pins = <8 RK_PA3 1 &pcfg_pull_up>; - }; - spi2_clk: spi2-clk { - rockchip,pins = <8 RK_PA6 1 &pcfg_pull_up>; - }; - spi2_cs0: spi2-cs0 { - rockchip,pins = <8 RK_PA7 1 &pcfg_pull_up>; - }; - spi2_rx: spi2-rx { - rockchip,pins = <8 RK_PB0 1 &pcfg_pull_up>; - }; - spi2_tx: spi2-tx { - rockchip,pins = <8 RK_PB1 1 &pcfg_pull_up>; - }; - }; - - uart0 { - uart0_xfer: uart0-xfer { - rockchip,pins = <4 RK_PC0 1 &pcfg_pull_up>, - <4 RK_PC1 1 &pcfg_pull_none>; - }; - - uart0_cts: uart0-cts { - rockchip,pins = <4 RK_PC2 1 &pcfg_pull_up>; - }; - - uart0_rts: uart0-rts { - rockchip,pins = <4 RK_PC3 1 &pcfg_pull_none>; - }; - }; - - uart1 { - uart1_xfer: uart1-xfer { - rockchip,pins = <5 RK_PB0 1 &pcfg_pull_up>, - <5 RK_PB1 1 &pcfg_pull_none>; - }; - - uart1_cts: uart1-cts { - rockchip,pins = <5 RK_PB2 1 &pcfg_pull_up>; - }; - - uart1_rts: uart1-rts { - rockchip,pins = <5 RK_PB3 1 &pcfg_pull_none>; - }; - }; - - uart2 { - uart2_xfer: uart2-xfer { - rockchip,pins = <7 RK_PC6 1 &pcfg_pull_up>, - <7 RK_PC7 1 &pcfg_pull_none>; - }; - /* no rts / cts for uart2 */ - }; - - uart3 { - uart3_xfer: uart3-xfer { - rockchip,pins = <7 RK_PA7 1 &pcfg_pull_up>, - <7 RK_PB0 1 &pcfg_pull_none>; - }; - - uart3_cts: uart3-cts { - rockchip,pins = <7 RK_PB1 1 &pcfg_pull_up>; - }; - - uart3_rts: uart3-rts { - rockchip,pins = <7 RK_PB2 1 &pcfg_pull_none>; - }; - }; - - uart4 { - uart4_xfer: uart4-xfer { - rockchip,pins = <5 RK_PB7 3 &pcfg_pull_up>, - <5 RK_PB6 3 &pcfg_pull_none>; - }; - - uart4_cts: uart4-cts { - rockchip,pins = <5 RK_PB4 3 &pcfg_pull_up>; - }; - - uart4_rts: uart4-rts { - rockchip,pins = <5 RK_PB5 3 &pcfg_pull_none>; - }; - }; - - tsadc { - otp_gpio: otp-gpio { - rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - otp_out: otp-out { - rockchip,pins = <0 RK_PB2 1 &pcfg_pull_none>; - }; - }; - - pwm0 { - pwm0_pin: pwm0-pin { - rockchip,pins = <7 RK_PA0 1 &pcfg_pull_none>; - }; - }; - - pwm1 { - pwm1_pin: pwm1-pin { - rockchip,pins = <7 RK_PA1 1 &pcfg_pull_none>; - }; - }; - - pwm2 { - pwm2_pin: pwm2-pin { - rockchip,pins = <7 RK_PC6 3 &pcfg_pull_none>; - }; - }; - - pwm3 { - pwm3_pin: pwm3-pin { - rockchip,pins = <7 RK_PC7 3 &pcfg_pull_none>; - }; - }; - - gmac { - rgmii_pins: rgmii-pins { - rockchip,pins = <3 RK_PD6 3 &pcfg_pull_none>, - <3 RK_PD7 3 &pcfg_pull_none>, - <3 RK_PD2 3 &pcfg_pull_none>, - <3 RK_PD3 3 &pcfg_pull_none>, - <3 RK_PD4 3 &pcfg_pull_none_12ma>, - <3 RK_PD5 3 &pcfg_pull_none_12ma>, - <3 RK_PD0 3 &pcfg_pull_none_12ma>, - <3 RK_PD1 3 &pcfg_pull_none_12ma>, - <4 RK_PA0 3 &pcfg_pull_none>, - <4 RK_PA5 3 &pcfg_pull_none>, - <4 RK_PA6 3 &pcfg_pull_none>, - <4 RK_PB1 3 &pcfg_pull_none_12ma>, - <4 RK_PA4 3 &pcfg_pull_none_12ma>, - <4 RK_PA1 3 &pcfg_pull_none>, - <4 RK_PA3 3 &pcfg_pull_none>; - }; - - rmii_pins: rmii-pins { - rockchip,pins = <3 RK_PD6 3 &pcfg_pull_none>, - <3 RK_PD7 3 &pcfg_pull_none>, - <3 RK_PD4 3 &pcfg_pull_none>, - <3 RK_PD5 3 &pcfg_pull_none>, - <4 RK_PA0 3 &pcfg_pull_none>, - <4 RK_PA5 3 &pcfg_pull_none>, - <4 RK_PA4 3 &pcfg_pull_none>, - <4 RK_PA1 3 &pcfg_pull_none>, - <4 RK_PA2 3 &pcfg_pull_none>, - <4 RK_PA3 3 &pcfg_pull_none>; - }; - }; - - spdif { - spdif_tx: spdif-tx { - rockchip,pins = <6 RK_PB3 1 &pcfg_pull_none>; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/rk3xxx.dtsi b/sys/gnu/dts/arm/rk3xxx.dtsi deleted file mode 100644 index 241f43e29c7..00000000000 --- a/sys/gnu/dts/arm/rk3xxx.dtsi +++ /dev/null @@ -1,469 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2013 MundoReader S.L. - * Author: Heiko Stuebner - */ - -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - - interrupt-parent = <&gic>; - - aliases { - ethernet0 = &emac; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - mshc0 = &emmc; - mshc1 = &mmc0; - mshc2 = &mmc1; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - spi0 = &spi0; - spi1 = &spi1; - }; - - amba { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - dmac1_s: dma-controller@20018000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x20018000 0x4000>; - interrupts = , - ; - #dma-cells = <1>; - arm,pl330-broken-no-flushp; - clocks = <&cru ACLK_DMA1>; - clock-names = "apb_pclk"; - }; - - dmac1_ns: dma-controller@2001c000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x2001c000 0x4000>; - interrupts = , - ; - #dma-cells = <1>; - arm,pl330-broken-no-flushp; - clocks = <&cru ACLK_DMA1>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - dmac2: dma-controller@20078000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x20078000 0x4000>; - interrupts = , - ; - #dma-cells = <1>; - arm,pl330-broken-no-flushp; - clocks = <&cru ACLK_DMA2>; - clock-names = "apb_pclk"; - }; - }; - - xin24m: oscillator { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - #clock-cells = <0>; - clock-output-names = "xin24m"; - }; - - gpu: gpu@10090000 { - compatible = "arm,mali-400"; - reg = <0x10090000 0x10000>; - clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>; - clock-names = "core", "bus"; - assigned-clocks = <&cru ACLK_GPU>; - assigned-clock-rates = <100000000>; - resets = <&cru SRST_GPU>; - status = "disabled"; - }; - - L2: l2-cache-controller@10138000 { - compatible = "arm,pl310-cache"; - reg = <0x10138000 0x1000>; - cache-unified; - cache-level = <2>; - }; - - scu@1013c000 { - compatible = "arm,cortex-a9-scu"; - reg = <0x1013c000 0x100>; - }; - - global_timer: global-timer@1013c200 { - compatible = "arm,cortex-a9-global-timer"; - reg = <0x1013c200 0x20>; - interrupts = ; - clocks = <&cru CORE_PERI>; - }; - - local_timer: local-timer@1013c600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0x1013c600 0x20>; - interrupts = ; - clocks = <&cru CORE_PERI>; - }; - - gic: interrupt-controller@1013d000 { - compatible = "arm,cortex-a9-gic"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0x1013d000 0x1000>, - <0x1013c100 0x0100>; - }; - - uart0: serial@10124000 { - compatible = "snps,dw-apb-uart"; - reg = <0x10124000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <1>; - clock-names = "baudclk", "apb_pclk"; - clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; - status = "disabled"; - }; - - uart1: serial@10126000 { - compatible = "snps,dw-apb-uart"; - reg = <0x10126000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <1>; - clock-names = "baudclk", "apb_pclk"; - clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; - status = "disabled"; - }; - - qos_gpu: qos@1012d000 { - compatible = "syscon"; - reg = <0x1012d000 0x20>; - }; - - qos_vpu: qos@1012e000 { - compatible = "syscon"; - reg = <0x1012e000 0x20>; - }; - - qos_lcdc0: qos@1012f000 { - compatible = "syscon"; - reg = <0x1012f000 0x20>; - }; - - qos_cif0: qos@1012f080 { - compatible = "syscon"; - reg = <0x1012f080 0x20>; - }; - - qos_ipp: qos@1012f100 { - compatible = "syscon"; - reg = <0x1012f100 0x20>; - }; - - qos_lcdc1: qos@1012f180 { - compatible = "syscon"; - reg = <0x1012f180 0x20>; - }; - - qos_cif1: qos@1012f200 { - compatible = "syscon"; - reg = <0x1012f200 0x20>; - }; - - qos_rga: qos@1012f280 { - compatible = "syscon"; - reg = <0x1012f280 0x20>; - }; - - usb_otg: usb@10180000 { - compatible = "rockchip,rk3066-usb", "snps,dwc2"; - reg = <0x10180000 0x40000>; - interrupts = ; - clocks = <&cru HCLK_OTG0>; - clock-names = "otg"; - dr_mode = "otg"; - g-np-tx-fifo-size = <16>; - g-rx-fifo-size = <275>; - g-tx-fifo-size = <256 128 128 64 64 32>; - phys = <&usbphy0>; - phy-names = "usb2-phy"; - status = "disabled"; - }; - - usb_host: usb@101c0000 { - compatible = "snps,dwc2"; - reg = <0x101c0000 0x40000>; - interrupts = ; - clocks = <&cru HCLK_OTG1>; - clock-names = "otg"; - dr_mode = "host"; - phys = <&usbphy1>; - phy-names = "usb2-phy"; - status = "disabled"; - }; - - emac: ethernet@10204000 { - compatible = "snps,arc-emac"; - reg = <0x10204000 0x3c>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - - rockchip,grf = <&grf>; - - clocks = <&cru HCLK_EMAC>, <&cru SCLK_MAC>; - clock-names = "hclk", "macref"; - max-speed = <100>; - phy-mode = "rmii"; - - status = "disabled"; - }; - - mmc0: mmc@10214000 { - compatible = "rockchip,rk2928-dw-mshc"; - reg = <0x10214000 0x1000>; - interrupts = ; - clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; - clock-names = "biu", "ciu"; - dmas = <&dmac2 1>; - dma-names = "rx-tx"; - fifo-depth = <256>; - resets = <&cru SRST_SDMMC>; - reset-names = "reset"; - status = "disabled"; - }; - - mmc1: mmc@10218000 { - compatible = "rockchip,rk2928-dw-mshc"; - reg = <0x10218000 0x1000>; - interrupts = ; - clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>; - clock-names = "biu", "ciu"; - dmas = <&dmac2 3>; - dma-names = "rx-tx"; - fifo-depth = <256>; - resets = <&cru SRST_SDIO>; - reset-names = "reset"; - status = "disabled"; - }; - - emmc: mmc@1021c000 { - compatible = "rockchip,rk2928-dw-mshc"; - reg = <0x1021c000 0x1000>; - interrupts = ; - clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>; - clock-names = "biu", "ciu"; - dmas = <&dmac2 4>; - dma-names = "rx-tx"; - fifo-depth = <256>; - resets = <&cru SRST_EMMC>; - reset-names = "reset"; - status = "disabled"; - }; - - pmu: pmu@20004000 { - compatible = "rockchip,rk3066-pmu", "syscon", "simple-mfd"; - reg = <0x20004000 0x100>; - - reboot-mode { - compatible = "syscon-reboot-mode"; - offset = <0x40>; - mode-normal = ; - mode-recovery = ; - mode-bootloader = ; - mode-loader = ; - }; - }; - - grf: grf@20008000 { - compatible = "syscon"; - reg = <0x20008000 0x200>; - }; - - i2c0: i2c@2002d000 { - compatible = "rockchip,rk3066-i2c"; - reg = <0x2002d000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - - rockchip,grf = <&grf>; - - clock-names = "i2c"; - clocks = <&cru PCLK_I2C0>; - - status = "disabled"; - }; - - i2c1: i2c@2002f000 { - compatible = "rockchip,rk3066-i2c"; - reg = <0x2002f000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - - rockchip,grf = <&grf>; - - clocks = <&cru PCLK_I2C1>; - clock-names = "i2c"; - - status = "disabled"; - }; - - pwm0: pwm@20030000 { - compatible = "rockchip,rk2928-pwm"; - reg = <0x20030000 0x10>; - #pwm-cells = <2>; - clocks = <&cru PCLK_PWM01>; - status = "disabled"; - }; - - pwm1: pwm@20030010 { - compatible = "rockchip,rk2928-pwm"; - reg = <0x20030010 0x10>; - #pwm-cells = <2>; - clocks = <&cru PCLK_PWM01>; - status = "disabled"; - }; - - wdt: watchdog@2004c000 { - compatible = "snps,dw-wdt"; - reg = <0x2004c000 0x100>; - clocks = <&cru PCLK_WDT>; - interrupts = ; - status = "disabled"; - }; - - pwm2: pwm@20050020 { - compatible = "rockchip,rk2928-pwm"; - reg = <0x20050020 0x10>; - #pwm-cells = <2>; - clocks = <&cru PCLK_PWM23>; - status = "disabled"; - }; - - pwm3: pwm@20050030 { - compatible = "rockchip,rk2928-pwm"; - reg = <0x20050030 0x10>; - #pwm-cells = <2>; - clocks = <&cru PCLK_PWM23>; - status = "disabled"; - }; - - i2c2: i2c@20056000 { - compatible = "rockchip,rk3066-i2c"; - reg = <0x20056000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - - rockchip,grf = <&grf>; - - clocks = <&cru PCLK_I2C2>; - clock-names = "i2c"; - - status = "disabled"; - }; - - i2c3: i2c@2005a000 { - compatible = "rockchip,rk3066-i2c"; - reg = <0x2005a000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - - rockchip,grf = <&grf>; - - clocks = <&cru PCLK_I2C3>; - clock-names = "i2c"; - - status = "disabled"; - }; - - i2c4: i2c@2005e000 { - compatible = "rockchip,rk3066-i2c"; - reg = <0x2005e000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - - rockchip,grf = <&grf>; - - clocks = <&cru PCLK_I2C4>; - clock-names = "i2c"; - - status = "disabled"; - }; - - uart2: serial@20064000 { - compatible = "snps,dw-apb-uart"; - reg = <0x20064000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <1>; - clock-names = "baudclk", "apb_pclk"; - clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; - status = "disabled"; - }; - - uart3: serial@20068000 { - compatible = "snps,dw-apb-uart"; - reg = <0x20068000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <1>; - clock-names = "baudclk", "apb_pclk"; - clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; - status = "disabled"; - }; - - saradc: saradc@2006c000 { - compatible = "rockchip,saradc"; - reg = <0x2006c000 0x100>; - interrupts = ; - #io-channel-cells = <1>; - clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; - clock-names = "saradc", "apb_pclk"; - resets = <&cru SRST_SARADC>; - reset-names = "saradc-apb"; - status = "disabled"; - }; - - spi0: spi@20070000 { - compatible = "rockchip,rk3066-spi"; - clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; - clock-names = "spiclk", "apb_pclk"; - interrupts = ; - reg = <0x20070000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - dmas = <&dmac2 10>, <&dmac2 11>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - spi1: spi@20074000 { - compatible = "rockchip,rk3066-spi"; - clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; - clock-names = "spiclk", "apb_pclk"; - interrupts = ; - reg = <0x20074000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - dmas = <&dmac2 12>, <&dmac2 13>; - dma-names = "tx", "rx"; - status = "disabled"; - }; -}; diff --git a/sys/gnu/dts/arm/rockchip-radxa-dalang-carrier.dtsi b/sys/gnu/dts/arm/rockchip-radxa-dalang-carrier.dtsi deleted file mode 100644 index df3712aedf8..00000000000 --- a/sys/gnu/dts/arm/rockchip-radxa-dalang-carrier.dtsi +++ /dev/null @@ -1,81 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd - * Copyright (c) 2019 Radxa Limited - * Copyright (c) 2019 Amarula Solutions(India) - */ - -#include - -/ { - chosen { - stdout-path = "serial2:1500000n8"; - }; -}; - -&gmac { - status = "okay"; -}; - -&i2c1 { - status = "okay"; - i2c-scl-rising-time-ns = <140>; - i2c-scl-falling-time-ns = <30>; -}; - -&i2c2 { - status = "okay"; - clock-frequency = <400000>; - - hym8563: hym8563@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "hym8563"; - pinctrl-names = "default"; - pinctrl-0 = <&hym8563_int>; - interrupt-parent = <&gpio4>; - interrupts = <30 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&pwm0 { - status = "okay"; -}; - -&pwm2 { - status = "okay"; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; - disable-wp; - vqmmc-supply = <&vccio_sd>; - max-frequency = <150000000>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_cts>; - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&pinctrl { - hym8563 { - hym8563_int: hym8563-int { - rockchip,pins = - <4 RK_PD6 0 &pcfg_pull_up>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/rv1108-elgin-r1.dts b/sys/gnu/dts/arm/rv1108-elgin-r1.dts deleted file mode 100644 index b1db924710c..00000000000 --- a/sys/gnu/dts/arm/rv1108-elgin-r1.dts +++ /dev/null @@ -1,207 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -/* - * Copyright (C) 2018 O.S. Systems Software LTDA. - */ - -/dts-v1/; - -#include "rv1108.dtsi" - -/ { - model = "Elgin RV1108 R1 board"; - compatible = "elgin,rv1108-r1", "rockchip,rv1108"; - - memory@60000000 { - device_type = "memory"; - reg = <0x60000000 0x08000000>; - }; - - chosen { - stdout-path = "serial2:1500000n8"; - }; - - vcc_sys: vsys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vsys"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - }; -}; - -&cpu0 { - cpu-supply = <&vdd_core>; -}; - -&emmc { - bus-width = <8>; - cap-mmc-highspeed; - no-sd; - no-sdio; - non-removable; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; - status = "okay"; -}; - -&gmac { - clock_in_out = "output"; - pinctrl-names = "default"; - pinctrl-0 = <&rmii_pins>; - snps,reset-gpio = <&gpio1 RK_PC1 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - status = "okay"; -}; - -&i2c0 { - clock-frequency = <400000>; - i2c-scl-rising-time-ns = <275>; - i2c-scl-falling-time-ns = <16>; - status = "okay"; - - rk805: pmic@18 { - compatible = "rockchip,rk805"; - reg = <0x18>; - interrupt-parent = <&gpio0>; - interrupts = ; - rockchip,system-power-controller; - - vcc1-supply = <&vcc_sys>; - vcc2-supply = <&vcc_sys>; - vcc3-supply = <&vcc_sys>; - vcc4-supply = <&vcc_sys>; - vcc5-supply = <&vdd_buck2>; - vcc6-supply = <&vdd_buck2>; - - regulators { - vdd_core: DCDC_REG1 { - regulator-name= "vdd_core"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <900000>; - }; - }; - - vdd_buck2: DCDC_REG2 { - regulator-name= "vdd_buck2"; - regulator-min-microvolt = <2200000>; - regulator-max-microvolt = <2200000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name= "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_io: DCDC_REG4 { - regulator-name= "vcc_io"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vdd_10: LDO_REG1 { - regulator-name= "vdd_10"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_18: LDO_REG2 { - regulator-name= "vcc_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd10_pmu: LDO_REG3 { - regulator-name= "vdd10_pmu"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - }; - }; -}; - -&spi { - pinctrl-names = "default"; - pinctrl-0 = <&spim1_clk &spim1_cs0 &spim1_tx &spim1_rx>; - status = "okay"; - - dh2228fv: dac@0 { - compatible = "rohm,dh2228fv"; - reg = <0>; - spi-max-frequency = <24000000>; - spi-cpha; - spi-cpol; - }; -}; - -&u2phy { - status = "okay"; - - u2phy_host: host-port { - status = "okay"; - }; - - u2phy_otg: otg-port { - status = "okay"; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer>; - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&usb_host_ehci { - status = "okay"; -}; - -&usb_host_ohci { - status = "okay"; -}; - -&usb_otg { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/rv1108-evb.dts b/sys/gnu/dts/arm/rv1108-evb.dts deleted file mode 100644 index 30f3d0470ad..00000000000 --- a/sys/gnu/dts/arm/rv1108-evb.dts +++ /dev/null @@ -1,225 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -/dts-v1/; - -#include "rv1108.dtsi" - -/ { - model = "Rockchip RV1108 Evaluation board"; - compatible = "rockchip,rv1108-evb", "rockchip,rv1108"; - - memory@60000000 { - device_type = "memory"; - reg = <0x60000000 0x08000000>; - }; - - chosen { - stdout-path = "serial2:1500000n8"; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - brightness-levels = < - 0 1 2 3 4 5 6 7 - 8 9 10 11 12 13 14 15 - 16 17 18 19 20 21 22 23 - 24 25 26 27 28 29 30 31 - 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 - 48 49 50 51 52 53 54 55 - 56 57 58 59 60 61 62 63 - 64 65 66 67 68 69 70 71 - 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 - 88 89 90 91 92 93 94 95 - 96 97 98 99 100 101 102 103 - 104 105 106 107 108 109 110 111 - 112 113 114 115 116 117 118 119 - 120 121 122 123 124 125 126 127 - 128 129 130 131 132 133 134 135 - 136 137 138 139 140 141 142 143 - 144 145 146 147 148 149 150 151 - 152 153 154 155 156 157 158 159 - 160 161 162 163 164 165 166 167 - 168 169 170 171 172 173 174 175 - 176 177 178 179 180 181 182 183 - 184 185 186 187 188 189 190 191 - 192 193 194 195 196 197 198 199 - 200 201 202 203 204 205 206 207 - 208 209 210 211 212 213 214 215 - 216 217 218 219 220 221 222 223 - 224 225 226 227 228 229 230 231 - 232 233 234 235 236 237 238 239 - 240 241 242 243 244 245 246 247 - 248 249 250 251 252 253 254 255>; - default-brightness-level = <200>; - pwms = <&pwm0 0 25000 0>; - }; - - vcc_sys: vsys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vsys"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - }; -}; - -&cpu0 { - cpu-supply = <&vdd_core>; -}; - -&i2c0 { - status = "okay"; - i2c-scl-rising-time-ns = <275>; - i2c-scl-falling-time-ns = <16>; - clock-frequency = <400000>; - - rk805: pmic@18 { - compatible = "rockchip,rk805"; - reg = <0x18>; - interrupt-parent = <&gpio0>; - interrupts = ; - rockchip,system-power-controller; - - vcc1-supply = <&vcc_sys>; - vcc2-supply = <&vcc_sys>; - vcc3-supply = <&vcc_sys>; - vcc4-supply = <&vcc_sys>; - vcc5-supply = <&vcc_sys>; - vcc6-supply = <&vcc_sys>; - - regulators { - vdd_core: DCDC_REG1 { - regulator-name= "vdd_core"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <900000>; - }; - }; - - vdd_cam: DCDC_REG2 { - regulator-name= "vdd_cam"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <2000000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name= "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_io: DCDC_REG4 { - regulator-name= "vcc_io"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vdd_10: LDO_REG1 { - regulator-name= "vdd_10"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_18: LDO_REG2 { - regulator-name= "vcc_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd10_pmu: LDO_REG3 { - regulator-name= "vdd10_pmu"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - }; - }; - - bma250: accelerometer@19 { - compatible = "bosch,bma250e"; - reg = <0x19>; - interrupt-parent = <&gpio0>; - interrupts = ; - }; -}; - -&pwm0 { - status = "okay"; -}; - -&sdmmc { - status = "okay"; -}; - -&tsadc { - status = "okay"; -}; - -&u2phy { - status = "okay"; - - u2phy_host: host-port { - status = "okay"; - }; - - u2phy_otg: otg-port { - status = "okay"; - }; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&usb_host_ehci { - status = "okay"; -}; - -&usb_host_ohci { - status = "okay"; -}; - -&usb_otg { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/rv1108.dtsi b/sys/gnu/dts/arm/rv1108.dtsi deleted file mode 100644 index 1fd06e7cb98..00000000000 --- a/sys/gnu/dts/arm/rv1108.dtsi +++ /dev/null @@ -1,941 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -#include -#include -#include -#include -#include -#include -/ { - #address-cells = <1>; - #size-cells = <1>; - - compatible = "rockchip,rv1108"; - - interrupt-parent = <&gic>; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@f00 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0xf00>; - clock-latency = <40000>; - clocks = <&cru ARMCLK>; - #cooling-cells = <2>; /* min followed by max */ - dynamic-power-coefficient = <75>; - operating-points-v2 = <&cpu_opp_table>; - }; - }; - - cpu_opp_table: opp_table { - compatible = "operating-points-v2"; - - opp-408000000 { - opp-hz = /bits/ 64 <408000000>; - opp-microvolt = <975000>; - clock-latency-ns = <40000>; - }; - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <975000>; - clock-latency-ns = <40000>; - }; - opp-816000000 { - opp-hz = /bits/ 64 <816000000>; - opp-microvolt = <1025000>; - clock-latency-ns = <40000>; - }; - opp-1008000000 { - opp-hz = /bits/ 64 <1008000000>; - opp-microvolt = <1150000>; - clock-latency-ns = <40000>; - }; - }; - - arm-pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts = ; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = , - ; - arm,cpu-registers-not-fw-configured; - clock-frequency = <24000000>; - }; - - xin24m: oscillator { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "xin24m"; - #clock-cells = <0>; - }; - - amba { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - pdma: pdma@102a0000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x102a0000 0x4000>; - interrupts = ; - #dma-cells = <1>; - arm,pl330-broken-no-flushp; - clocks = <&cru ACLK_DMAC>; - clock-names = "apb_pclk"; - }; - }; - - bus_intmem@10080000 { - compatible = "mmio-sram"; - reg = <0x10080000 0x2000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x10080000 0x2000>; - }; - - uart2: serial@10210000 { - compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart"; - reg = <0x10210000 0x100>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&pdma 6>, <&pdma 7>; - #dma-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&uart2m0_xfer>; - status = "disabled"; - }; - - uart1: serial@10220000 { - compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart"; - reg = <0x10220000 0x100>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&pdma 4>, <&pdma 5>; - #dma-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&uart1_xfer>; - status = "disabled"; - }; - - uart0: serial@10230000 { - compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart"; - reg = <0x10230000 0x100>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&pdma 2>, <&pdma 3>; - #dma-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; - status = "disabled"; - }; - - i2c1: i2c@10240000 { - compatible = "rockchip,rv1108-i2c"; - reg = <0x10240000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; - clock-names = "i2c", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_xfer>; - rockchip,grf = <&grf>; - status = "disabled"; - }; - - i2c2: i2c@10250000 { - compatible = "rockchip,rv1108-i2c"; - reg = <0x10250000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; - clock-names = "i2c", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2m1_xfer>; - rockchip,grf = <&grf>; - status = "disabled"; - }; - - i2c3: i2c@10260000 { - compatible = "rockchip,rv1108-i2c"; - reg = <0x10260000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; - clock-names = "i2c", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_xfer>; - rockchip,grf = <&grf>; - status = "disabled"; - }; - - spi: spi@10270000 { - compatible = "rockchip,rv1108-spi"; - reg = <0x10270000 0x1000>; - interrupts = ; - clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>; - clock-names = "spiclk", "apb_pclk"; - dmas = <&pdma 8>, <&pdma 9>; - dma-names = "tx", "rx"; - #dma-cells = <2>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - pwm4: pwm@10280000 { - compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm"; - reg = <0x10280000 0x10>; - interrupts = ; - clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; - clock-names = "pwm", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm4_pin>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm5: pwm@10280010 { - compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm"; - reg = <0x10280010 0x10>; - interrupts = ; - clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; - clock-names = "pwm", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm5_pin>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm6: pwm@10280020 { - compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm"; - reg = <0x10280020 0x10>; - interrupts = ; - clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; - clock-names = "pwm", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm6_pin>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm7: pwm@10280030 { - compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm"; - reg = <0x10280030 0x10>; - interrupts = ; - clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; - clock-names = "pwm", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm7_pin>; - #pwm-cells = <3>; - status = "disabled"; - }; - - grf: syscon@10300000 { - compatible = "rockchip,rv1108-grf", "syscon", "simple-mfd"; - reg = <0x10300000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - - u2phy: usb2-phy@100 { - compatible = "rockchip,rv1108-usb2phy"; - reg = <0x100 0x0c>; - clocks = <&cru SCLK_USBPHY>; - clock-names = "phyclk"; - #clock-cells = <0>; - clock-output-names = "usbphy"; - rockchip,usbgrf = <&usbgrf>; - status = "disabled"; - - u2phy_otg: otg-port { - interrupts = ; - interrupt-names = "otg-mux"; - #phy-cells = <0>; - status = "disabled"; - }; - - u2phy_host: host-port { - interrupts = ; - interrupt-names = "linestate"; - #phy-cells = <0>; - status = "disabled"; - }; - }; - }; - - timer: timer@10350000 { - compatible = "rockchip,rv1108-timer", "rockchip,rk3288-timer"; - reg = <0x10350000 0x20>; - interrupts = ; - clocks = <&xin24m>, <&cru PCLK_TIMER>; - clock-names = "timer", "pclk"; - }; - - watchdog: wdt@10360000 { - compatible = "snps,dw-wdt"; - reg = <0x10360000 0x100>; - interrupts = ; - clocks = <&cru PCLK_WDT>; - clock-names = "pclk_wdt"; - status = "disabled"; - }; - - thermal-zones { - soc_thermal: soc-thermal { - polling-delay-passive = <20>; - polling-delay = <1000>; - sustainable-power = <50>; - thermal-sensors = <&tsadc 0>; - - trips { - threshold: trip-point0 { - temperature = <70000>; - hysteresis = <2000>; - type = "passive"; - }; - target: trip-point1 { - temperature = <85000>; - hysteresis = <2000>; - type = "passive"; - }; - soc_crit: soc-crit { - temperature = <95000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&target>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - contribution = <4096>; - }; - }; - }; - }; - - tsadc: tsadc@10370000 { - compatible = "rockchip,rv1108-tsadc"; - reg = <0x10370000 0x100>; - interrupts = ; - assigned-clocks = <&cru SCLK_TSADC>; - assigned-clock-rates = <750000>; - clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; - clock-names = "tsadc", "apb_pclk"; - pinctrl-names = "init", "default", "sleep"; - pinctrl-0 = <&otp_gpio>; - pinctrl-1 = <&otp_out>; - pinctrl-2 = <&otp_gpio>; - resets = <&cru SRST_TSADC>; - reset-names = "tsadc-apb"; - rockchip,hw-tshut-temp = <120000>; - #thermal-sensor-cells = <1>; - status = "disabled"; - }; - - adc: adc@1038c000 { - compatible = "rockchip,rv1108-saradc", "rockchip,rk3399-saradc"; - reg = <0x1038c000 0x100>; - interrupts = ; - #io-channel-cells = <1>; - clock-frequency = <1000000>; - clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; - clock-names = "saradc", "apb_pclk"; - status = "disabled"; - }; - - i2c0: i2c@20000000 { - compatible = "rockchip,rv1108-i2c"; - reg = <0x20000000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cru SCLK_I2C0_PMU>, <&cru PCLK_I2C0_PMU>; - clock-names = "i2c", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_xfer>; - rockchip,grf = <&grf>; - status = "disabled"; - }; - - pwm0: pwm@20040000 { - compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm"; - reg = <0x20040000 0x10>; - interrupts = ; - clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>; - clock-names = "pwm", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pin>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm1: pwm@20040010 { - compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm"; - reg = <0x20040010 0x10>; - interrupts = ; - clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>; - clock-names = "pwm", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm1_pin>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm2: pwm@20040020 { - compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm"; - reg = <0x20040020 0x10>; - interrupts = ; - clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>; - clock-names = "pwm", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm2_pin>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm3: pwm@20040030 { - compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm"; - reg = <0x20040030 0x10>; - interrupts = ; - clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>; - clock-names = "pwm", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm3_pin>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pmugrf: syscon@20060000 { - compatible = "rockchip,rv1108-pmugrf", "syscon"; - reg = <0x20060000 0x1000>; - }; - - usbgrf: syscon@202a0000 { - compatible = "rockchip,rv1108-usbgrf", "syscon"; - reg = <0x202a0000 0x1000>; - }; - - cru: clock-controller@20200000 { - compatible = "rockchip,rv1108-cru"; - reg = <0x20200000 0x1000>; - rockchip,grf = <&grf>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - emmc: mmc@30110000 { - compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x30110000 0x4000>; - interrupts = ; - clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, - <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - max-frequency = <150000000>; - status = "disabled"; - }; - - sdio: mmc@30120000 { - compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x30120000 0x4000>; - interrupts = ; - clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, - <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - max-frequency = <150000000>; - status = "disabled"; - }; - - sdmmc: mmc@30130000 { - compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x30130000 0x4000>; - interrupts = ; - clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, - <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - max-frequency = <100000000>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; - status = "disabled"; - }; - - usb_host_ehci: usb@30140000 { - compatible = "generic-ehci"; - reg = <0x30140000 0x20000>; - interrupts = ; - clocks = <&cru HCLK_HOST0>, <&u2phy>; - clock-names = "usbhost", "utmi"; - phys = <&u2phy_host>; - phy-names = "usb"; - status = "disabled"; - }; - - usb_host_ohci: usb@30160000 { - compatible = "generic-ohci"; - reg = <0x30160000 0x20000>; - interrupts = ; - clocks = <&cru HCLK_HOST0>, <&u2phy>; - clock-names = "usbhost", "utmi"; - phys = <&u2phy_host>; - phy-names = "usb"; - status = "disabled"; - }; - - usb_otg: usb@30180000 { - compatible = "rockchip,rv1108-usb", "rockchip,rk3066-usb", - "snps,dwc2"; - reg = <0x30180000 0x40000>; - interrupts = ; - clocks = <&cru HCLK_OTG>; - clock-names = "otg"; - dr_mode = "otg"; - g-np-tx-fifo-size = <16>; - g-rx-fifo-size = <280>; - g-tx-fifo-size = <256 128 128 64 32 16>; - g-use-dma; - phys = <&u2phy_otg>; - phy-names = "usb2-phy"; - status = "disabled"; - }; - - gmac: eth@30200000 { - compatible = "rockchip,rv1108-gmac"; - reg = <0x30200000 0x10000>; - interrupts = , - ; - interrupt-names = "macirq", "eth_wake_irq"; - clocks = <&cru SCLK_MAC>, - <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_RX>, - <&cru SCLK_MAC_REF>, <&cru SCLK_MAC_REFOUT>, - <&cru ACLK_GMAC>, <&cru PCLK_GMAC>; - clock-names = "stmmaceth", - "mac_clk_rx", "mac_clk_tx", - "clk_mac_ref", "clk_mac_refout", - "aclk_mac", "pclk_mac"; - /* rv1108 only supports an rmii interface */ - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&rmii_pins>; - rockchip,grf = <&grf>; - status = "disabled"; - }; - - gic: interrupt-controller@32010000 { - compatible = "arm,gic-400"; - interrupt-controller; - #interrupt-cells = <3>; - #address-cells = <0>; - - reg = <0x32011000 0x1000>, - <0x32012000 0x2000>, - <0x32014000 0x2000>, - <0x32016000 0x2000>; - interrupts = ; - }; - - pinctrl: pinctrl { - compatible = "rockchip,rv1108-pinctrl"; - rockchip,grf = <&grf>; - rockchip,pmu = <&pmugrf>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gpio0: gpio0@20030000 { - compatible = "rockchip,gpio-bank"; - reg = <0x20030000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO0_PMU>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio1@10310000 { - compatible = "rockchip,gpio-bank"; - reg = <0x10310000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO1>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio2@10320000 { - compatible = "rockchip,gpio-bank"; - reg = <0x10320000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO2>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio3@10330000 { - compatible = "rockchip,gpio-bank"; - reg = <0x10330000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO3>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - pcfg_pull_up: pcfg-pull-up { - bias-pull-up; - }; - - pcfg_pull_down: pcfg-pull-down { - bias-pull-down; - }; - - pcfg_pull_none: pcfg-pull-none { - bias-disable; - }; - - pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma { - drive-strength = <8>; - }; - - pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma { - drive-strength = <12>; - }; - - pcfg_pull_none_smt: pcfg-pull-none-smt { - bias-disable; - input-schmitt-enable; - }; - - pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma { - bias-pull-up; - drive-strength = <8>; - }; - - pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma { - drive-strength = <4>; - }; - - pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma { - bias-pull-up; - drive-strength = <4>; - }; - - pcfg_output_high: pcfg-output-high { - output-high; - }; - - pcfg_output_low: pcfg-output-low { - output-low; - }; - - pcfg_input_high: pcfg-input-high { - bias-pull-up; - input-enable; - }; - - emmc { - emmc_bus8: emmc-bus8 { - rockchip,pins = <2 RK_PA0 2 &pcfg_pull_up_drv_8ma>, - <2 RK_PA1 2 &pcfg_pull_up_drv_8ma>, - <2 RK_PA2 2 &pcfg_pull_up_drv_8ma>, - <2 RK_PA3 2 &pcfg_pull_up_drv_8ma>, - <2 RK_PA4 2 &pcfg_pull_up_drv_8ma>, - <2 RK_PA5 2 &pcfg_pull_up_drv_8ma>, - <2 RK_PA6 2 &pcfg_pull_up_drv_8ma>, - <2 RK_PA7 2 &pcfg_pull_up_drv_8ma>; - }; - - emmc_clk: emmc-clk { - rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none_drv_8ma>; - }; - - emmc_cmd: emmc-cmd { - rockchip,pins = <2 RK_PB4 2 &pcfg_pull_up_drv_8ma>; - }; - }; - - gmac { - rmii_pins: rmii-pins { - rockchip,pins = <1 RK_PC5 2 &pcfg_pull_none>, - <1 RK_PC3 2 &pcfg_pull_none>, - <1 RK_PC4 2 &pcfg_pull_none>, - <1 RK_PB2 3 &pcfg_pull_none_drv_12ma>, - <1 RK_PB3 3 &pcfg_pull_none_drv_12ma>, - <1 RK_PB4 3 &pcfg_pull_none_drv_12ma>, - <1 RK_PB5 3 &pcfg_pull_none>, - <1 RK_PB6 3 &pcfg_pull_none>, - <1 RK_PB7 3 &pcfg_pull_none>, - <1 RK_PC2 3 &pcfg_pull_none>; - }; - }; - - i2c0 { - i2c0_xfer: i2c0-xfer { - rockchip,pins = <0 RK_PB1 1 &pcfg_pull_none_smt>, - <0 RK_PB2 1 &pcfg_pull_none_smt>; - }; - }; - - i2c1 { - i2c1_xfer: i2c1-xfer { - rockchip,pins = <2 RK_PD3 1 &pcfg_pull_up>, - <2 RK_PD4 1 &pcfg_pull_up>; - }; - }; - - i2c2m1 { - i2c2m1_xfer: i2c2m1-xfer { - rockchip,pins = <0 RK_PC2 2 &pcfg_pull_none>, - <0 RK_PC6 3 &pcfg_pull_none>; - }; - - i2c2m1_gpio: i2c2m1-gpio { - rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>, - <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - i2c2m05v { - i2c2m05v_xfer: i2c2m05v-xfer { - rockchip,pins = <1 RK_PD5 2 &pcfg_pull_none>, - <1 RK_PD4 2 &pcfg_pull_none>; - }; - - i2c2m05v_gpio: i2c2m05v-gpio { - rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>, - <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - i2c3 { - i2c3_xfer: i2c3-xfer { - rockchip,pins = <0 RK_PB6 1 &pcfg_pull_none>, - <0 RK_PC4 2 &pcfg_pull_none>; - }; - }; - - pwm0 { - pwm0_pin: pwm0-pin { - rockchip,pins = <0 RK_PC5 1 &pcfg_pull_none>; - }; - }; - - pwm1 { - pwm1_pin: pwm1-pin { - rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>; - }; - }; - - pwm2 { - pwm2_pin: pwm2-pin { - rockchip,pins = <0 RK_PC6 1 &pcfg_pull_none>; - }; - }; - - pwm3 { - pwm3_pin: pwm3-pin { - rockchip,pins = <0 RK_PC0 1 &pcfg_pull_none>; - }; - }; - - pwm4 { - pwm4_pin: pwm4-pin { - rockchip,pins = <1 RK_PC1 3 &pcfg_pull_none>; - }; - }; - - pwm5 { - pwm5_pin: pwm5-pin { - rockchip,pins = <1 RK_PA7 2 &pcfg_pull_none>; - }; - }; - - pwm6 { - pwm6_pin: pwm6-pin { - rockchip,pins = <1 RK_PB0 2 &pcfg_pull_none>; - }; - }; - - pwm7 { - pwm7_pin: pwm7-pin { - rockchip,pins = <1 RK_PB1 2 &pcfg_pull_none>; - }; - }; - - sdmmc { - sdmmc_clk: sdmmc-clk { - rockchip,pins = <3 RK_PC4 1 &pcfg_pull_none_drv_4ma>; - }; - - sdmmc_cmd: sdmmc-cmd { - rockchip,pins = <3 RK_PC5 1 &pcfg_pull_up_drv_4ma>; - }; - - sdmmc_cd: sdmmc-cd { - rockchip,pins = <0 RK_PA1 1 &pcfg_pull_up_drv_4ma>; - }; - - sdmmc_bus1: sdmmc-bus1 { - rockchip,pins = <3 RK_PC3 1 &pcfg_pull_up_drv_4ma>; - }; - - sdmmc_bus4: sdmmc-bus4 { - rockchip,pins = <3 RK_PC3 1 &pcfg_pull_up_drv_4ma>, - <3 RK_PC2 1 &pcfg_pull_up_drv_4ma>, - <3 RK_PC1 1 &pcfg_pull_up_drv_4ma>, - <3 RK_PC0 1 &pcfg_pull_up_drv_4ma>; - }; - }; - - spim0 { - spim0_clk: spim0-clk { - rockchip,pins = <1 RK_PD0 2 &pcfg_pull_up>; - }; - - spim0_cs0: spim0-cs0 { - rockchip,pins = <1 RK_PD1 2 &pcfg_pull_up>; - }; - - spim0_tx: spim0-tx { - rockchip,pins = <1 RK_PD3 2 &pcfg_pull_up>; - }; - - spim0_rx: spim0-rx { - rockchip,pins = <1 RK_PD2 2 &pcfg_pull_up>; - }; - }; - - spim1 { - spim1_clk: spim1-clk { - rockchip,pins = <0 RK_PA3 1 &pcfg_pull_up>; - }; - - spim1_cs0: spim1-cs0 { - rockchip,pins = <0 RK_PA4 1 &pcfg_pull_up>; - }; - - spim1_rx: spim1-rx { - rockchip,pins = <0 RK_PB0 1 &pcfg_pull_up>; - }; - - spim1_tx: spim1-tx { - rockchip,pins = <0 RK_PA7 1 &pcfg_pull_up>; - }; - }; - - tsadc { - otp_out: otp-out { - rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>; - }; - - otp_gpio: otp-gpio { - rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - uart0 { - uart0_xfer: uart0-xfer { - rockchip,pins = <3 RK_PA6 1 &pcfg_pull_up>, - <3 RK_PA5 1 &pcfg_pull_none>; - }; - - uart0_cts: uart0-cts { - rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>; - }; - - uart0_rts: uart0-rts { - rockchip,pins = <3 RK_PA3 1 &pcfg_pull_none>; - }; - - uart0_rts_gpio: uart0-rts-gpio { - rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - uart1 { - uart1_xfer: uart1-xfer { - rockchip,pins = <1 RK_PD3 1 &pcfg_pull_up>, - <1 RK_PD2 1 &pcfg_pull_none>; - }; - - uart1_cts: uart1-cts { - rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>; - }; - - uart1_rts: uart1-rts { - rockchip,pins = <1 RK_PD1 1 &pcfg_pull_none>; - }; - }; - - uart2m0 { - uart2m0_xfer: uart2m0-xfer { - rockchip,pins = <2 RK_PD2 1 &pcfg_pull_up>, - <2 RK_PD1 1 &pcfg_pull_none>; - }; - }; - - uart2m1 { - uart2m1_xfer: uart2m1-xfer { - rockchip,pins = <3 RK_PC3 2 &pcfg_pull_up>, - <3 RK_PC2 2 &pcfg_pull_none>; - }; - }; - - uart2_5v { - uart2_5v_cts: uart2_5v-cts { - rockchip,pins = <1 RK_PD4 1 &pcfg_pull_none>; - }; - - uart2_5v_rts: uart2_5v-rts { - rockchip,pins = <1 RK_PD5 1 &pcfg_pull_none>; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/s3c2416-pinctrl.dtsi b/sys/gnu/dts/arm/s3c2416-pinctrl.dtsi deleted file mode 100644 index 92439ee5d7d..00000000000 --- a/sys/gnu/dts/arm/s3c2416-pinctrl.dtsi +++ /dev/null @@ -1,172 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung S3C2416 pinctrl settings - * - * Copyright (c) 2013 Heiko Stuebner - */ - -#include - -&pinctrl_0 { - /* - * Pin banks - */ - - gpa: gpa { - gpio-controller; - #gpio-cells = <2>; - }; - - gpb: gpb { - gpio-controller; - #gpio-cells = <2>; - }; - - gpc: gpc { - gpio-controller; - #gpio-cells = <2>; - }; - - gpd: gpd { - gpio-controller; - #gpio-cells = <2>; - }; - - gpe: gpe { - gpio-controller; - #gpio-cells = <2>; - }; - - gpf: gpf { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpg: gpg { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gph: gph { - gpio-controller; - #gpio-cells = <2>; - }; - - gpj: gpj { - gpio-controller; - #gpio-cells = <2>; - }; - - gpk: gpk { - gpio-controller; - #gpio-cells = <2>; - }; - - gpl: gpl { - gpio-controller; - #gpio-cells = <2>; - }; - - gpm: gpm { - gpio-controller; - #gpio-cells = <2>; - }; - - /* - * Pin groups - */ - - uart0_data: uart0-data { - samsung,pins = "gph-0", "gph-1"; - samsung,pin-function = ; - }; - - uart0_fctl: uart0-fctl { - samsung,pins = "gph-8", "gph-9"; - samsung,pin-function = ; - }; - - uart1_data: uart1-data { - samsung,pins = "gph-2", "gph-3"; - samsung,pin-function = ; - }; - - uart1_fctl: uart1-fctl { - samsung,pins = "gph-10", "gph-11"; - samsung,pin-function = ; - }; - - uart2_data: uart2-data { - samsung,pins = "gph-4", "gph-5"; - samsung,pin-function = ; - }; - - uart2_fctl: uart2-fctl { - samsung,pins = "gph-6", "gph-7"; - samsung,pin-function = ; - }; - - uart3_data: uart3-data { - samsung,pins = "gph-6", "gph-7"; - samsung,pin-function = ; - }; - - extuart_clk: extuart-clk { - samsung,pins = "gph-12"; - samsung,pin-function = ; - }; - - i2c0_bus: i2c0-bus { - samsung,pins = "gpe-14", "gpe-15"; - samsung,pin-function = ; - }; - - spi0_bus: spi0-bus { - samsung,pins = "gpe-11", "gpe-12", "gpe-13"; - samsung,pin-function = ; - }; - - sd0_clk: sd0-clk { - samsung,pins = "gpe-5"; - samsung,pin-function = ; - }; - - sd0_cmd: sd0-cmd { - samsung,pins = "gpe-6"; - samsung,pin-function = ; - }; - - sd0_bus1: sd0-bus1 { - samsung,pins = "gpe-7"; - samsung,pin-function = ; - }; - - sd0_bus4: sd0-bus4 { - samsung,pins = "gpe-8", "gpe-9", "gpe-10"; - samsung,pin-function = ; - }; - - sd1_cmd: sd1-cmd { - samsung,pins = "gpl-8"; - samsung,pin-function = ; - }; - - sd1_clk: sd1-clk { - samsung,pins = "gpl-9"; - samsung,pin-function = ; - }; - - sd1_bus1: sd1-bus1 { - samsung,pins = "gpl-0"; - samsung,pin-function = ; - }; - - sd1_bus4: sd1-bus4 { - samsung,pins = "gpl-1", "gpl-2", "gpl-3"; - samsung,pin-function = ; - }; -}; diff --git a/sys/gnu/dts/arm/s3c2416-smdk2416.dts b/sys/gnu/dts/arm/s3c2416-smdk2416.dts deleted file mode 100644 index 811bfdef4e9..00000000000 --- a/sys/gnu/dts/arm/s3c2416-smdk2416.dts +++ /dev/null @@ -1,84 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung SMDK2416 board device tree source - * - * Copyright (c) 2013 Heiko Stuebner - */ - -/dts-v1/; -#include "s3c2416.dtsi" - -/ { - model = "SMDK2416"; - compatible = "samsung,s3c2416"; - - memory@30000000 { - device_type = "memory"; - reg = <0x30000000 0x4000000>; - }; - - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - xti: xti@0 { - compatible = "fixed-clock"; - reg = <0>; - clock-frequency = <12000000>; - clock-output-names = "xti"; - #clock-cells = <0>; - }; - }; -}; - -&rtc { - status = "okay"; -}; - -&sdhci_0 { - pinctrl-names = "default"; - pinctrl-0 = <&sd1_clk>, <&sd1_cmd>, - <&sd1_bus1>, <&sd1_bus4>; - bus-width = <4>; - broken-cd; - status = "okay"; -}; - -&sdhci_1 { - pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, - <&sd0_bus1>, <&sd0_bus4>; - bus-width = <4>; - cd-gpios = <&gpf 1 0>; - cd-inverted; - status = "okay"; -}; - -&uart_0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_data>, <&uart0_fctl>; -}; - -&uart_1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart1_data>, <&uart1_fctl>; -}; - -&uart_2 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart2_data>; -}; - -&uart_3 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart3_data>; -}; - -&watchdog { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/s3c2416.dtsi b/sys/gnu/dts/arm/s3c2416.dtsi deleted file mode 100644 index 6adf64ea3ff..00000000000 --- a/sys/gnu/dts/arm/s3c2416.dtsi +++ /dev/null @@ -1,119 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's S3C2416 SoC device tree source - * - * Copyright (c) 2013 Heiko Stuebner - */ - -#include -#include "s3c24xx.dtsi" -#include "s3c2416-pinctrl.dtsi" - -/ { - model = "Samsung S3C2416 SoC"; - compatible = "samsung,s3c2416"; - - aliases { - serial3 = &uart_3; - }; - - cpus { - cpu { - compatible = "arm,arm926ej-s"; - }; - }; - - interrupt-controller@4a000000 { - compatible = "samsung,s3c2416-irq"; - }; - - clocks: clock-controller@4c000000 { - compatible = "samsung,s3c2416-clock"; - reg = <0x4c000000 0x40>; - #clock-cells = <1>; - }; - - pinctrl@56000000 { - compatible = "samsung,s3c2416-pinctrl"; - }; - - timer@51000000 { - clocks = <&clocks PCLK_PWM>; - clock-names = "timers"; - }; - - uart_0: serial@50000000 { - compatible = "samsung,s3c2440-uart"; - clock-names = "uart", "clk_uart_baud2", - "clk_uart_baud3"; - clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>, - <&clocks SCLK_UART>; - }; - - uart_1: serial@50004000 { - compatible = "samsung,s3c2440-uart"; - clock-names = "uart", "clk_uart_baud2", - "clk_uart_baud3"; - clocks = <&clocks PCLK_UART1>, <&clocks PCLK_UART1>, - <&clocks SCLK_UART>; - }; - - uart_2: serial@50008000 { - compatible = "samsung,s3c2440-uart"; - clock-names = "uart", "clk_uart_baud2", - "clk_uart_baud3"; - clocks = <&clocks PCLK_UART2>, <&clocks PCLK_UART2>, - <&clocks SCLK_UART>; - }; - - uart_3: serial@5000c000 { - compatible = "samsung,s3c2440-uart"; - reg = <0x5000C000 0x4000>; - interrupts = <1 18 24 4>, <1 18 25 4>; - clock-names = "uart", "clk_uart_baud2", - "clk_uart_baud3"; - clocks = <&clocks PCLK_UART3>, <&clocks PCLK_UART3>, - <&clocks SCLK_UART>; - status = "disabled"; - }; - - sdhci_1: sdhci@4ac00000 { - compatible = "samsung,s3c6410-sdhci"; - reg = <0x4AC00000 0x100>; - interrupts = <0 0 21 3>; - clock-names = "hsmmc", "mmc_busclk.0", - "mmc_busclk.2"; - clocks = <&clocks HCLK_HSMMC0>, <&clocks HCLK_HSMMC0>, - <&clocks MUX_HSMMC0>; - status = "disabled"; - }; - - sdhci_0: sdhci@4a800000 { - compatible = "samsung,s3c6410-sdhci"; - reg = <0x4A800000 0x100>; - interrupts = <0 0 20 3>; - clock-names = "hsmmc", "mmc_busclk.0", - "mmc_busclk.2"; - clocks = <&clocks HCLK_HSMMC1>, <&clocks HCLK_HSMMC1>, - <&clocks MUX_HSMMC1>; - status = "disabled"; - }; - - watchdog: watchdog@53000000 { - interrupts = <1 9 27 3>; - clocks = <&clocks PCLK_WDT>; - clock-names = "watchdog"; - }; - - rtc: rtc@57000000 { - compatible = "samsung,s3c2416-rtc"; - clocks = <&clocks PCLK_RTC>; - clock-names = "rtc"; - }; - - i2c@54000000 { - compatible = "samsung,s3c2440-i2c"; - clocks = <&clocks PCLK_I2C0>; - clock-names = "i2c"; - }; -}; diff --git a/sys/gnu/dts/arm/s3c24xx.dtsi b/sys/gnu/dts/arm/s3c24xx.dtsi deleted file mode 100644 index 6d8dd3cdd3c..00000000000 --- a/sys/gnu/dts/arm/s3c24xx.dtsi +++ /dev/null @@ -1,92 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's S3C24XX family device tree source - * - * Copyright (c) 2013 Heiko Stuebner - */ - -/ { - compatible = "samsung,s3c24xx"; - interrupt-parent = <&intc>; - #address-cells = <1>; - #size-cells = <1>; - - aliases { - pinctrl0 = &pinctrl_0; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - }; - - intc:interrupt-controller@4a000000 { - compatible = "samsung,s3c2410-irq"; - reg = <0x4a000000 0x100>; - interrupt-controller; - #interrupt-cells = <4>; - }; - - pinctrl_0: pinctrl@56000000 { - reg = <0x56000000 0x1000>; - - wakeup-interrupt-controller { - compatible = "samsung,s3c2410-wakeup-eint"; - interrupts = <0 0 0 3>, - <0 0 1 3>, - <0 0 2 3>, - <0 0 3 3>, - <0 0 4 4>, - <0 0 5 4>; - }; - }; - - timer@51000000 { - compatible = "samsung,s3c2410-pwm"; - reg = <0x51000000 0x1000>; - interrupts = <0 0 10 3>, <0 0 11 3>, <0 0 12 3>, <0 0 13 3>, <0 0 14 3>; - #pwm-cells = <4>; - }; - - uart0: serial@50000000 { - compatible = "samsung,s3c2410-uart"; - reg = <0x50000000 0x4000>; - interrupts = <1 28 0 4>, <1 28 1 4>; - status = "disabled"; - }; - - uart1: serial@50004000 { - compatible = "samsung,s3c2410-uart"; - reg = <0x50004000 0x4000>; - interrupts = <1 23 3 4>, <1 23 4 4>; - status = "disabled"; - }; - - uart2: serial@50008000 { - compatible = "samsung,s3c2410-uart"; - reg = <0x50008000 0x4000>; - interrupts = <1 15 6 4>, <1 15 7 4>; - status = "disabled"; - }; - - watchdog@53000000 { - compatible = "samsung,s3c2410-wdt"; - reg = <0x53000000 0x100>; - interrupts = <0 0 9 3>; - status = "disabled"; - }; - - rtc@57000000 { - compatible = "samsung,s3c2410-rtc"; - reg = <0x57000000 0x100>; - interrupts = <0 0 30 3>, <0 0 8 3>; - status = "disabled"; - }; - - i2c@54000000 { - compatible = "samsung,s3c2410-i2c"; - reg = <0x54000000 0x100>; - interrupts = <0 0 27 3>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; -}; diff --git a/sys/gnu/dts/arm/s3c6400.dtsi b/sys/gnu/dts/arm/s3c6400.dtsi deleted file mode 100644 index 8c28e8a0c82..00000000000 --- a/sys/gnu/dts/arm/s3c6400.dtsi +++ /dev/null @@ -1,38 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's S3C6400 SoC device tree source - * - * Copyright (c) 2013 Tomasz Figa - * - * Samsung's S3C6400 SoC device nodes are listed in this file. S3C6400 - * based board files can include this file and provide values for board specfic - * bindings. - * - * Note: This file does not include device nodes for all the controllers in - * S3C6400 SoC. As device tree coverage for S3C6400 increases, additional - * nodes can be added to this file. - */ - -#include "s3c64xx.dtsi" - -/ { - compatible = "samsung,s3c6400"; -}; - -&vic0 { - valid-mask = <0xfffffe1f>; - valid-wakeup-mask = <0x00200004>; -}; - -&vic1 { - valid-mask = <0xffffffff>; - valid-wakeup-mask = <0x53020000>; -}; - -&soc { - clocks: clock-controller@7e00f000 { - compatible = "samsung,s3c6400-clock"; - reg = <0x7e00f000 0x1000>; - #clock-cells = <1>; - }; -}; diff --git a/sys/gnu/dts/arm/s3c6410-mini6410.dts b/sys/gnu/dts/arm/s3c6410-mini6410.dts deleted file mode 100644 index 1aeac33b0d3..00000000000 --- a/sys/gnu/dts/arm/s3c6410-mini6410.dts +++ /dev/null @@ -1,226 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's S3C6410 based Mini6410 board device tree source - * - * Copyright (c) 2013 Tomasz Figa - * - * Device tree source file for FriendlyARM Mini6410 board which is based on - * Samsung's S3C6410 SoC. - */ - -/dts-v1/; - -#include -#include - -#include "s3c6410.dtsi" - -/ { - model = "FriendlyARM Mini6410 board based on S3C6410"; - compatible = "friendlyarm,mini6410", "samsung,s3c6410"; - - memory@50000000 { - device_type = "memory"; - reg = <0x50000000 0x10000000>; - }; - - chosen { - bootargs = "console=ttySAC0,115200n8 earlyprintk rootwait root=/dev/mmcblk0p1"; - }; - - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - fin_pll: oscillator@0 { - compatible = "fixed-clock"; - reg = <0>; - clock-frequency = <12000000>; - clock-output-names = "fin_pll"; - #clock-cells = <0>; - }; - - xusbxti: oscillator@1 { - compatible = "fixed-clock"; - reg = <1>; - clock-output-names = "xusbxti"; - clock-frequency = <48000000>; - #clock-cells = <0>; - }; - }; - - srom-cs1@18000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x18000000 0x8000000>; - ranges; - - ethernet@18000000 { - compatible = "davicom,dm9000"; - reg = <0x18000000 0x2 0x18000004 0x2>; - interrupt-parent = <&gpn>; - interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; - davicom,no-eeprom; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&gpio_keys>; - autorepeat; - - button-k1 { - label = "K1"; - gpios = <&gpn 0 GPIO_ACTIVE_LOW>; - linux,code = <2>; - debounce-interval = <20>; - }; - - button-k2 { - label = "K2"; - gpios = <&gpn 1 GPIO_ACTIVE_LOW>; - linux,code = <3>; - debounce-interval = <20>; - }; - - button-k3 { - label = "K3"; - gpios = <&gpn 2 GPIO_ACTIVE_LOW>; - linux,code = <4>; - debounce-interval = <20>; - }; - - button-k4 { - label = "K4"; - gpios = <&gpn 3 GPIO_ACTIVE_LOW>; - linux,code = <5>; - debounce-interval = <20>; - }; - - button-k5 { - label = "K5"; - gpios = <&gpn 4 GPIO_ACTIVE_LOW>; - linux,code = <6>; - debounce-interval = <20>; - }; - - button-k6 { - label = "K6"; - gpios = <&gpn 5 GPIO_ACTIVE_LOW>; - linux,code = <7>; - debounce-interval = <20>; - }; - - button-k7 { - label = "K7"; - gpios = <&gpl 11 GPIO_ACTIVE_LOW>; - linux,code = <8>; - debounce-interval = <20>; - }; - - button-k8 { - label = "K8"; - gpios = <&gpl 12 GPIO_ACTIVE_LOW>; - linux,code = <9>; - debounce-interval = <20>; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&gpio_leds>; - - led-1 { - label = "LED1"; - gpios = <&gpk 4 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - }; - - led-2 { - label = "LED2"; - gpios = <&gpk 5 GPIO_ACTIVE_LOW>; - linux,default-trigger = "mmc0"; - }; - - led-3 { - label = "LED3"; - gpios = <&gpk 6 GPIO_ACTIVE_LOW>; - }; - - led-4 { - label = "LED4"; - gpios = <&gpk 7 GPIO_ACTIVE_LOW>; - }; - }; - - buzzer { - compatible = "pwm-beeper"; - pwms = <&pwm 0 1000000 0>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_out>; - }; -}; - -&clocks { - clocks = <&fin_pll>; -}; - -&sdhci0 { - pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>; - bus-width = <4>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_data>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_data>, <&uart1_fctl>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_data>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_data>; - status = "okay"; -}; - -&pinctrl0 { - gpio_leds: gpio-leds { - samsung,pins = "gpk-4", "gpk-5", "gpk-6", "gpk-7"; - samsung,pin-pud = ; - }; - - gpio_keys: gpio-keys { - samsung,pins = "gpn-0", "gpn-1", "gpn-2", "gpn-3", - "gpn-4", "gpn-5", "gpl-11", "gpl-12"; - samsung,pin-pud = ; - }; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_bus>; - status = "okay"; - - eeprom@50 { - compatible = "atmel,24c08"; - reg = <0x50>; - pagesize = <16>; - }; -}; diff --git a/sys/gnu/dts/arm/s3c6410-smdk6410.dts b/sys/gnu/dts/arm/s3c6410-smdk6410.dts deleted file mode 100644 index 96267f5f02a..00000000000 --- a/sys/gnu/dts/arm/s3c6410-smdk6410.dts +++ /dev/null @@ -1,105 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung S3C6410 based SMDK6410 board device tree source. - * - * Copyright (c) 2013 Tomasz Figa - * - * Device tree source file for Samsung SMDK6410 board which is based on - * Samsung's S3C6410 SoC. - */ - -/dts-v1/; - -#include -#include - -#include "s3c6410.dtsi" - -/ { - model = "Samsung SMDK6410 board based on S3C6410"; - compatible = "samsung,mini6410", "samsung,s3c6410"; - - memory@50000000 { - device_type = "memory"; - reg = <0x50000000 0x8000000>; - }; - - chosen { - bootargs = "console=ttySAC0,115200n8 earlyprintk rootwait root=/dev/mmcblk0p1"; - }; - - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - fin_pll: oscillator@0 { - compatible = "fixed-clock"; - reg = <0>; - clock-frequency = <12000000>; - clock-output-names = "fin_pll"; - #clock-cells = <0>; - }; - - xusbxti: oscillator@1 { - compatible = "fixed-clock"; - reg = <1>; - clock-output-names = "xusbxti"; - clock-frequency = <48000000>; - #clock-cells = <0>; - }; - }; - - srom-cs1@18000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x18000000 0x8000000>; - ranges; - - ethernet@18000000 { - compatible = "smsc,lan9115"; - reg = <0x18000000 0x10000>; - interrupt-parent = <&gpn>; - interrupts = <10 IRQ_TYPE_LEVEL_LOW>; - phy-mode = "mii"; - reg-io-width = <4>; - smsc,force-internal-phy; - }; - }; -}; - -&clocks { - clocks = <&fin_pll>; -}; - -&sdhci0 { - pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>; - bus-width = <4>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_data>, <&uart0_fctl>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_data>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_data>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_data>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/s3c6410.dtsi b/sys/gnu/dts/arm/s3c6410.dtsi deleted file mode 100644 index a766d6de696..00000000000 --- a/sys/gnu/dts/arm/s3c6410.dtsi +++ /dev/null @@ -1,54 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's S3C6410 SoC device tree source - * - * Copyright (c) 2013 Tomasz Figa - * - * Samsung's S3C6410 SoC device nodes are listed in this file. S3C6410 - * based board files can include this file and provide values for board specfic - * bindings. - * - * Note: This file does not include device nodes for all the controllers in - * S3C6410 SoC. As device tree coverage for S3C6410 increases, additional - * nodes can be added to this file. - */ - -#include "s3c64xx.dtsi" - -/ { - compatible = "samsung,s3c6410"; - - aliases { - i2c1 = &i2c1; - }; -}; - -&vic0 { - valid-mask = <0xffffff7f>; - valid-wakeup-mask = <0x00200004>; -}; - -&vic1 { - valid-mask = <0xffffffff>; - valid-wakeup-mask = <0x53020000>; -}; - -&soc { - clocks: clock-controller@7e00f000 { - compatible = "samsung,s3c6410-clock"; - reg = <0x7e00f000 0x1000>; - #clock-cells = <1>; - }; - - i2c1: i2c@7f00f000 { - compatible = "samsung,s3c2440-i2c"; - reg = <0x7f00f000 0x1000>; - interrupt-parent = <&vic0>; - interrupts = <5>; - clock-names = "i2c"; - clocks = <&clocks PCLK_IIC1>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; -}; diff --git a/sys/gnu/dts/arm/s3c64xx-pinctrl.dtsi b/sys/gnu/dts/arm/s3c64xx-pinctrl.dtsi deleted file mode 100644 index 8e9594d64b5..00000000000 --- a/sys/gnu/dts/arm/s3c64xx-pinctrl.dtsi +++ /dev/null @@ -1,682 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's S3C64xx SoC series common device tree source - * - pin control-related definitions - * - * Copyright (c) 2013 Tomasz Figa - * - * Samsung's S3C64xx SoCs pin banks, pin-mux and pin-config options are - * listed as device tree nodes in this file. - */ - -#include - -&pinctrl0 { - /* - * Pin banks - */ - - gpa: gpa { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpb: gpb { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc: gpc { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpd: gpd { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpe: gpe { - gpio-controller; - #gpio-cells = <2>; - }; - - gpf: gpf { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpg: gpg { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gph: gph { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpi: gpi { - gpio-controller; - #gpio-cells = <2>; - }; - - gpj: gpj { - gpio-controller; - #gpio-cells = <2>; - }; - - gpk: gpk { - gpio-controller; - #gpio-cells = <2>; - }; - - gpl: gpl { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpm: gpm { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpn: gpn { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpo: gpo { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpp: gpp { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpq: gpq { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - /* - * Pin groups - */ - - uart0_data: uart0-data { - samsung,pins = "gpa-0", "gpa-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - uart0_fctl: uart0-fctl { - samsung,pins = "gpa-2", "gpa-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - uart1_data: uart1-data { - samsung,pins = "gpa-4", "gpa-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - uart1_fctl: uart1-fctl { - samsung,pins = "gpa-6", "gpa-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - uart2_data: uart2-data { - samsung,pins = "gpb-0", "gpb-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - uart3_data: uart3-data { - samsung,pins = "gpb-2", "gpb-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - ext_dma_0: ext-dma-0 { - samsung,pins = "gpb-0", "gpb-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - ext_dma_1: ext-dma-1 { - samsung,pins = "gpb-2", "gpb-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - irda_data_0: irda-data-0 { - samsung,pins = "gpb-0", "gpb-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - irda_data_1: irda-data-1 { - samsung,pins = "gpb-2", "gpb-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - irda_sdbw: irda-sdbw { - samsung,pins = "gpb-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - i2c0_bus: i2c0-bus { - samsung,pins = "gpb-5", "gpb-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - i2c1_bus: i2c1-bus { - /* S3C6410-only */ - samsung,pins = "gpb-2", "gpb-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - spi0_bus: spi0-bus { - samsung,pins = "gpc-0", "gpc-1", "gpc-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - spi0_cs: spi0-cs { - samsung,pins = "gpc-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - spi1_bus: spi1-bus { - samsung,pins = "gpc-4", "gpc-5", "gpc-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - spi1_cs: spi1-cs { - samsung,pins = "gpc-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - sd0_cmd: sd0-cmd { - samsung,pins = "gpg-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - sd0_clk: sd0-clk { - samsung,pins = "gpg-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - sd0_bus1: sd0-bus1 { - samsung,pins = "gpg-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - sd0_bus4: sd0-bus4 { - samsung,pins = "gpg-2", "gpg-3", "gpg-4", "gpg-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - sd0_cd: sd0-cd { - samsung,pins = "gpg-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - sd1_cmd: sd1-cmd { - samsung,pins = "gph-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - sd1_clk: sd1-clk { - samsung,pins = "gph-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - sd1_bus1: sd1-bus1 { - samsung,pins = "gph-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - sd1_bus4: sd1-bus4 { - samsung,pins = "gph-2", "gph-3", "gph-4", "gph-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - sd1_bus8: sd1-bus8 { - samsung,pins = "gph-2", "gph-3", "gph-4", "gph-5", - "gph-6", "gph-7", "gph-8", "gph-9"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - sd1_cd: sd1-cd { - samsung,pins = "gpg-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - sd2_cmd: sd2-cmd { - samsung,pins = "gpc-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - sd2_clk: sd2-clk { - samsung,pins = "gpc-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - sd2_bus1: sd2-bus1 { - samsung,pins = "gph-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - sd2_bus4: sd2-bus4 { - samsung,pins = "gph-6", "gph-7", "gph-8", "gph-9"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - i2s0_bus: i2s0-bus { - samsung,pins = "gpd-0", "gpd-2", "gpd-3", "gpd-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - i2s0_cdclk: i2s0-cdclk { - samsung,pins = "gpd-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - i2s1_bus: i2s1-bus { - samsung,pins = "gpe-0", "gpe-2", "gpe-3", "gpe-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - i2s1_cdclk: i2s1-cdclk { - samsung,pins = "gpe-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - i2s2_bus: i2s2-bus { - /* S3C6410-only */ - samsung,pins = "gpc-4", "gpc-5", "gpc-6", "gph-6", - "gph-8", "gph-9"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - i2s2_cdclk: i2s2-cdclk { - /* S3C6410-only */ - samsung,pins = "gph-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - pcm0_bus: pcm0-bus { - samsung,pins = "gpd-0", "gpd-2", "gpd-3", "gpd-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - pcm0_extclk: pcm0-extclk { - samsung,pins = "gpd-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - pcm1_bus: pcm1-bus { - samsung,pins = "gpe-0", "gpe-2", "gpe-3", "gpe-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - pcm1_extclk: pcm1-extclk { - samsung,pins = "gpe-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - ac97_bus_0: ac97-bus-0 { - samsung,pins = "gpd-0", "gpd-1", "gpd-2", "gpd-3", "gpd-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - ac97_bus_1: ac97-bus-1 { - samsung,pins = "gpe-0", "gpe-1", "gpe-2", "gpe-3", "gpe-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - cam_port: cam-port { - samsung,pins = "gpf-0", "gpf-1", "gpf-2", "gpf-4", - "gpf-5", "gpf-6", "gpf-7", "gpf-8", - "gpf-9", "gpf-10", "gpf-11", "gpf-12"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - cam_rst: cam-rst { - samsung,pins = "gpf-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - cam_field: cam-field { - /* S3C6410-only */ - samsung,pins = "gpb-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - pwm_extclk: pwm-extclk { - samsung,pins = "gpf-13"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - pwm0_out: pwm0-out { - samsung,pins = "gpf-14"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - pwm1_out: pwm1-out { - samsung,pins = "gpf-15"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - clkout0: clkout-0 { - samsung,pins = "gpf-14"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - keypad_col0_0: keypad-col0-0 { - samsung,pins = "gph-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - keypad_col1_0: keypad-col1-0 { - samsung,pins = "gph-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - keypad_col2_0: keypad-col2-0 { - samsung,pins = "gph-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - keypad_col3_0: keypad-col3-0 { - samsung,pins = "gph-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - keypad_col4_0: keypad-col4-0 { - samsung,pins = "gph-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - keypad_col5_0: keypad-col5-0 { - samsung,pins = "gph-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - keypad_col6_0: keypad-col6-0 { - samsung,pins = "gph-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - keypad_col7_0: keypad-col7-0 { - samsung,pins = "gph-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - keypad_col0_1: keypad-col0-1 { - samsung,pins = "gpl-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - keypad_col1_1: keypad-col1-1 { - samsung,pins = "gpl-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - keypad_col2_1: keypad-col2-1 { - samsung,pins = "gpl-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - keypad_col3_1: keypad-col3-1 { - samsung,pins = "gpl-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - keypad_col4_1: keypad-col4-1 { - samsung,pins = "gpl-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - keypad_col5_1: keypad-col5-1 { - samsung,pins = "gpl-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - keypad_col6_1: keypad-col6-1 { - samsung,pins = "gpl-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - keypad_col7_1: keypad-col7-1 { - samsung,pins = "gpl-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - keypad_row0_0: keypad-row0-0 { - samsung,pins = "gpk-8"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - keypad_row1_0: keypad-row1-0 { - samsung,pins = "gpk-9"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - keypad_row2_0: keypad-row2-0 { - samsung,pins = "gpk-10"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - keypad_row3_0: keypad-row3-0 { - samsung,pins = "gpk-11"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - keypad_row4_0: keypad-row4-0 { - samsung,pins = "gpk-12"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - keypad_row5_0: keypad-row5-0 { - samsung,pins = "gpk-13"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - keypad_row6_0: keypad-row6-0 { - samsung,pins = "gpk-14"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - keypad_row7_0: keypad-row7-0 { - samsung,pins = "gpk-15"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - keypad_row0_1: keypad-row0-1 { - samsung,pins = "gpn-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - keypad_row1_1: keypad-row1-1 { - samsung,pins = "gpn-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - keypad_row2_1: keypad-row2-1 { - samsung,pins = "gpn-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - keypad_row3_1: keypad-row3-1 { - samsung,pins = "gpn-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - keypad_row4_1: keypad-row4-1 { - samsung,pins = "gpn-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - keypad_row5_1: keypad-row5-1 { - samsung,pins = "gpn-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - keypad_row6_1: keypad-row6-1 { - samsung,pins = "gpn-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - keypad_row7_1: keypad-row7-1 { - samsung,pins = "gpn-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - lcd_ctrl: lcd-ctrl { - samsung,pins = "gpj-8", "gpj-9", "gpj-10", "gpj-11"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - lcd_data16: lcd-data-width16 { - samsung,pins = "gpi-3", "gpi-4", "gpi-5", "gpi-6", - "gpi-7", "gpi-10", "gpi-11", "gpi-12", - "gpi-13", "gpi-14", "gpi-15", "gpj-3", - "gpj-4", "gpj-5", "gpj-6", "gpj-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - lcd_data18: lcd-data-width18 { - samsung,pins = "gpi-2", "gpi-3", "gpi-4", "gpi-5", - "gpi-6", "gpi-7", "gpi-10", "gpi-11", - "gpi-12", "gpi-13", "gpi-14", "gpi-15", - "gpj-2", "gpj-3", "gpj-4", "gpj-5", - "gpj-6", "gpj-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - lcd_data24: lcd-data-width24 { - samsung,pins = "gpi-0", "gpi-1", "gpi-2", "gpi-3", - "gpi-4", "gpi-5", "gpi-6", "gpi-7", - "gpi-8", "gpi-9", "gpi-10", "gpi-11", - "gpi-12", "gpi-13", "gpi-14", "gpi-15", - "gpj-0", "gpj-1", "gpj-2", "gpj-3", - "gpj-4", "gpj-5", "gpj-6", "gpj-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - hsi_bus: hsi-bus { - samsung,pins = "gpk-0", "gpk-1", "gpk-2", "gpk-3", - "gpk-4", "gpk-5", "gpk-6", "gpk-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; -}; diff --git a/sys/gnu/dts/arm/s3c64xx.dtsi b/sys/gnu/dts/arm/s3c64xx.dtsi deleted file mode 100644 index 2e611df3791..00000000000 --- a/sys/gnu/dts/arm/s3c64xx.dtsi +++ /dev/null @@ -1,200 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's S3C64xx SoC series common device tree source - * - * Copyright (c) 2013 Tomasz Figa - * - * Samsung's S3C64xx SoC series device nodes are listed in this file. - * Particular SoCs from S3C64xx series can include this file and provide - * values for SoCs specfic bindings. - * - * Note: This file does not include device nodes for all the controllers in - * S3C64xx SoCs. As device tree coverage for S3C64xx increases, additional - * nodes can be added to this file. - */ - -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - - aliases { - i2c0 = &i2c0; - pinctrl0 = &pinctrl0; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,arm1176jzf-s", "arm,arm1176"; - reg = <0x0>; - }; - }; - - soc: soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - vic0: interrupt-controller@71200000 { - compatible = "arm,pl192-vic"; - interrupt-controller; - reg = <0x71200000 0x1000>; - #interrupt-cells = <1>; - }; - - vic1: interrupt-controller@71300000 { - compatible = "arm,pl192-vic"; - interrupt-controller; - reg = <0x71300000 0x1000>; - #interrupt-cells = <1>; - }; - - sdhci0: sdhci@7c200000 { - compatible = "samsung,s3c6410-sdhci"; - reg = <0x7c200000 0x100>; - interrupt-parent = <&vic1>; - interrupts = <24>; - clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.2"; - clocks = <&clocks HCLK_HSMMC0>, <&clocks HCLK_HSMMC0>, - <&clocks SCLK_MMC0>; - status = "disabled"; - }; - - sdhci1: sdhci@7c300000 { - compatible = "samsung,s3c6410-sdhci"; - reg = <0x7c300000 0x100>; - interrupt-parent = <&vic1>; - interrupts = <25>; - clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.2"; - clocks = <&clocks HCLK_HSMMC1>, <&clocks HCLK_HSMMC1>, - <&clocks SCLK_MMC1>; - status = "disabled"; - }; - - sdhci2: sdhci@7c400000 { - compatible = "samsung,s3c6410-sdhci"; - reg = <0x7c400000 0x100>; - interrupt-parent = <&vic1>; - interrupts = <17>; - clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.2"; - clocks = <&clocks HCLK_HSMMC2>, <&clocks HCLK_HSMMC2>, - <&clocks SCLK_MMC2>; - status = "disabled"; - }; - - watchdog: watchdog@7e004000 { - compatible = "samsung,s3c6410-wdt"; - reg = <0x7e004000 0x1000>; - interrupt-parent = <&vic0>; - interrupts = <26>; - clock-names = "watchdog"; - clocks = <&clocks PCLK_WDT>; - }; - - i2c0: i2c@7f004000 { - compatible = "samsung,s3c2440-i2c"; - reg = <0x7f004000 0x1000>; - interrupt-parent = <&vic1>; - interrupts = <18>; - clock-names = "i2c"; - clocks = <&clocks PCLK_IIC0>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - uart0: serial@7f005000 { - compatible = "samsung,s3c6400-uart"; - reg = <0x7f005000 0x100>; - interrupt-parent = <&vic1>; - interrupts = <5>; - clock-names = "uart", "clk_uart_baud2", - "clk_uart_baud3"; - clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>, - <&clocks SCLK_UART>; - status = "disabled"; - }; - - uart1: serial@7f005400 { - compatible = "samsung,s3c6400-uart"; - reg = <0x7f005400 0x100>; - interrupt-parent = <&vic1>; - interrupts = <6>; - clock-names = "uart", "clk_uart_baud2", - "clk_uart_baud3"; - clocks = <&clocks PCLK_UART1>, <&clocks PCLK_UART1>, - <&clocks SCLK_UART>; - status = "disabled"; - }; - - uart2: serial@7f005800 { - compatible = "samsung,s3c6400-uart"; - reg = <0x7f005800 0x100>; - interrupt-parent = <&vic1>; - interrupts = <7>; - clock-names = "uart", "clk_uart_baud2", - "clk_uart_baud3"; - clocks = <&clocks PCLK_UART2>, <&clocks PCLK_UART2>, - <&clocks SCLK_UART>; - status = "disabled"; - }; - - uart3: serial@7f005c00 { - compatible = "samsung,s3c6400-uart"; - reg = <0x7f005c00 0x100>; - interrupt-parent = <&vic1>; - interrupts = <8>; - clock-names = "uart", "clk_uart_baud2", - "clk_uart_baud3"; - clocks = <&clocks PCLK_UART3>, <&clocks PCLK_UART3>, - <&clocks SCLK_UART>; - status = "disabled"; - }; - - pwm: pwm@7f006000 { - compatible = "samsung,s3c6400-pwm"; - reg = <0x7f006000 0x1000>; - interrupt-parent = <&vic0>; - interrupts = <23>, <24>, <25>, <27>, <28>; - clock-names = "timers"; - clocks = <&clocks PCLK_PWM>; - samsung,pwm-outputs = <0>, <1>; - #pwm-cells = <3>; - }; - - pinctrl0: pinctrl@7f008000 { - compatible = "samsung,s3c64xx-pinctrl"; - reg = <0x7f008000 0x1000>; - interrupt-parent = <&vic1>; - interrupts = <21>; - - pctrl_int_map: pinctrl-interrupt-map { - interrupt-map = <0 &vic0 0>, - <1 &vic0 1>, - <2 &vic1 0>, - <3 &vic1 1>; - #address-cells = <0>; - #size-cells = <0>; - #interrupt-cells = <1>; - }; - - wakeup-interrupt-controller { - compatible = "samsung,s3c64xx-wakeup-eint"; - interrupts = <0>, <1>, <2>, <3>; - interrupt-parent = <&pctrl_int_map>; - }; - }; - }; -}; - -#include "s3c64xx-pinctrl.dtsi" diff --git a/sys/gnu/dts/arm/s5pv210-aquila.dts b/sys/gnu/dts/arm/s5pv210-aquila.dts deleted file mode 100644 index 14969b6529e..00000000000 --- a/sys/gnu/dts/arm/s5pv210-aquila.dts +++ /dev/null @@ -1,390 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's S5PV210 SoC device tree source - * - * Copyright (c) 2013-2014 Samsung Electronics, Co. Ltd. - * - * Mateusz Krawczuk - * Tomasz Figa - * - * Board device tree source for Samsung Aquila board. - */ - -/dts-v1/; -#include -#include "s5pv210.dtsi" - -/ { - model = "Samsung Aquila based on S5PC110"; - compatible = "samsung,aquila", "samsung,s5pv210"; - - aliases { - i2c3 = &i2c_pmic; - }; - - chosen { - bootargs = "console=ttySAC2,115200n8 root=/dev/mmcblk1p5 rw rootwait ignore_loglevel earlyprintk"; - }; - - memory@30000000 { - device_type = "memory"; - reg = <0x30000000 0x05000000 - 0x40000000 0x18000000>; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - vtf_reg: fixed-regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "V_TF_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&mp05 4 0>; - enable-active-high; - }; - - pda_reg: fixed-regulator@1 { - compatible = "regulator-fixed"; - regulator-name = "VCC_1.8V_PDA"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - reg = <1>; - }; - - bat_reg: fixed-regulator@2 { - compatible = "regulator-fixed"; - regulator-name = "V_BAT"; - regulator-min-microvolt = <3700000>; - regulator-max-microvolt = <3700000>; - reg = <2>; - }; - }; - - i2c_pmic: i2c-pmic { - compatible = "i2c-gpio"; - gpios = <&gpj4 0 0>, /* sda */ - <&gpj4 3 0>; /* scl */ - i2c-gpio,delay-us = <2>; /* ~100 kHz */ - #address-cells = <1>; - #size-cells = <0>; - - pmic@66 { - compatible = "national,lp3974"; - reg = <0x66>; - - max8998,pmic-buck1-default-dvs-idx = <0>; - max8998,pmic-buck1-dvs-gpios = <&gph0 3 0>, - <&gph0 4 0>; - max8998,pmic-buck1-dvs-voltage = <1200000>, <1200000>, - <1200000>, <1200000>; - - max8998,pmic-buck2-default-dvs-idx = <0>; - max8998,pmic-buck2-dvs-gpio = <&gph0 5 0>; - max8998,pmic-buck2-dvs-voltage = <1200000>, <1200000>; - - regulators { - ldo2_reg: LDO2 { - regulator-name = "VALIVE_1.1V"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - ldo3_reg: LDO3 { - regulator-name = "VUSB+MIPI_1.1V"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - ldo4_reg: LDO4 { - regulator-name = "VADC_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo5_reg: LDO5 { - regulator-name = "VTF_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - ldo6_reg: LDO6 { - regulator-name = "VCC_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo7_reg: LDO7 { - regulator-name = "VCC_3.0V"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo8_reg: LDO8 { - regulator-name = "VUSB+VDAC_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo9_reg: LDO9 { - regulator-name = "VCC+VCAM_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - ldo10_reg: LDO10 { - regulator-name = "VPLL_1.1V"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo11_reg: LDO11 { - regulator-name = "CAM_IO_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - ldo12_reg: LDO12 { - regulator-name = "CAM_ISP_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - ldo13_reg: LDO13 { - regulator-name = "CAM_A_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - ldo14_reg: LDO14 { - regulator-name = "CAM_CIF_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo15_reg: LDO15 { - regulator-name = "CAM_AF_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo16_reg: LDO16 { - regulator-name = "VMIPI_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo17_reg: LDO17 { - regulator-name = "CAM_8M_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - buck1_reg: BUCK1 { - regulator-name = "VARM_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - buck2_reg: BUCK2 { - regulator-name = "VINT_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - buck3_reg: BUCK3 { - regulator-name = "VCC_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - buck4_reg: BUCK4 { - regulator-name = "CAM_CORE_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - vichg_reg: ENVICHG { - regulator-name = "VICHG"; - }; - - safeout1_reg: ESAFEOUT1 { - regulator-name = "SAFEOUT1"; - regulator-always-on; - }; - - safeout2_reg: ESAFEOUT2 { - regulator-name = "SAFEOUT2"; - regulator-boot-on; - }; - }; - }; - - }; - - gpio-keys { - compatible = "gpio-keys"; - - power-key { - gpios = <&gph2 6 1>; - linux,code = ; - label = "power"; - debounce-interval = <1>; - wakeup-source; - }; - }; -}; - -&xusbxti { - clock-frequency = <24000000>; -}; - -&keypad { - linux,input-no-autorepeat; - wakeup-source; - samsung,keypad-num-rows = <3>; - samsung,keypad-num-columns = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&keypad_row0>, <&keypad_row1>, <&keypad_row2>, - <&keypad_col0>, <&keypad_col1>, <&keypad_col2>; - status = "okay"; - - key_1 { - keypad,row = <0>; - keypad,column = <1>; - linux,code = ; - }; - - key_2 { - keypad,row = <0>; - keypad,column = <2>; - linux,code = ; - }; - - key_3 { - keypad,row = <1>; - keypad,column = <1>; - linux,code = ; - }; - - key_4 { - keypad,row = <1>; - keypad,column = <2>; - linux,code = ; - }; - - key_5 { - keypad,row = <2>; - keypad,column = <1>; - linux,code = ; - }; - - key_6 { - keypad,row = <2>; - keypad,column = <2>; - linux,code = ; - }; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&sdhci0 { - bus-width = <4>; - non-removable; - status = "okay"; - vmmc-supply = <&ldo5_reg>; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4>; - pinctrl-names = "default"; -}; - -&sdhci2 { - bus-width = <4>; - cd-gpios = <&gph3 4 1>; - vmmc-supply = <&vtf_reg>; - cd-inverted; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &t_flash_detect>; - pinctrl-names = "default"; - status = "okay"; -}; - -&onenand { - status = "okay"; -}; - -&hsotg { - vusb_a-supply = <&ldo3_reg>; - vusb_d-supply = <&ldo8_reg>; - dr_mode = "peripheral"; - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; - -&fimd { - pinctrl-0 = <&lcd_clk &lcd_data24 &pwm1_out>; - pinctrl-names = "default"; - status = "okay"; - - display-timings { - native-mode = <&timing0>; - timing0: timing { - clock-frequency = <0>; - hactive = <800>; - vactive = <480>; - hfront-porch = <16>; - hback-porch = <16>; - hsync-len = <2>; - vback-porch = <3>; - vfront-porch = <28>; - vsync-len = <1>; - }; - }; -}; - -&pinctrl0 { - t_flash_detect: t-flash-detect { - samsung,pins = "gph3-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; -}; diff --git a/sys/gnu/dts/arm/s5pv210-aries.dtsi b/sys/gnu/dts/arm/s5pv210-aries.dtsi deleted file mode 100644 index 8ff70b85633..00000000000 --- a/sys/gnu/dts/arm/s5pv210-aries.dtsi +++ /dev/null @@ -1,509 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's S5PV210 based Galaxy Aries board device tree source - */ - -/dts-v1/; -#include -#include -#include "s5pv210.dtsi" - -/ { - compatible = "samsung,aries", "samsung,s5pv210"; - - aliases { - i2c6 = &i2c_pmic; - i2c9 = &i2c_fuel; - }; - - memory@30000000 { - device_type = "memory"; - reg = <0x30000000 0x05000000 - 0x40000000 0x10000000 - 0x50000000 0x08000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - mfc_left: region@43000000 { - compatible = "shared-dma-pool"; - no-map; - reg = <0x43000000 0x2000000>; - }; - - mfc_right: region@51000000 { - compatible = "shared-dma-pool"; - no-map; - reg = <0x51000000 0x2000000>; - }; - }; - - vibrator_pwr: regulator-fixed-0 { - compatible = "regulator-fixed"; - regulator-name = "vibrator-en"; - enable-active-high; - gpio = <&gpj1 1 GPIO_ACTIVE_HIGH>; - }; - - wifi_pwrseq: wifi-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpg1 2 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&wlan_gpio_rst>; - post-power-on-delay-ms = <500>; - power-off-delay-us = <500>; - }; - - i2c_pmic: i2c-gpio-0 { - compatible = "i2c-gpio"; - sda-gpios = <&gpj4 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpj4 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <2>; - #address-cells = <1>; - #size-cells = <0>; - - pmic@66 { - compatible = "maxim,max8998"; - reg = <0x66>; - interrupt-parent = <&gph0>; - interrupts = <7 IRQ_TYPE_EDGE_FALLING>; - - max8998,pmic-buck1-default-dvs-idx = <1>; - max8998,pmic-buck1-dvs-gpios = <&gph0 3 GPIO_ACTIVE_HIGH>, - <&gph0 4 GPIO_ACTIVE_HIGH>; - max8998,pmic-buck1-dvs-voltage = <1275000>, <1200000>, - <1050000>, <950000>; - - max8998,pmic-buck2-default-dvs-idx = <0>; - max8998,pmic-buck2-dvs-gpio = <&gph0 5 GPIO_ACTIVE_HIGH>; - max8998,pmic-buck2-dvs-voltage = <1100000>, <1000000>; - - regulators { - ldo2_reg: LDO2 { - regulator-name = "VALIVE_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - ldo3_reg: LDO3 { - regulator-name = "VUSB_1.1V"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo4_reg: LDO4 { - regulator-name = "VADC_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo5_reg: LDO5 { - regulator-name = "VTF_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo6_reg: LDO6 { - regulator-name = "LDO6"; - regulator-min-microvolt = <1600000>; - regulator-max-microvolt = <3600000>; - }; - - ldo7_reg: LDO7 { - regulator-name = "VLCD_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - /* Till we get panel driver */ - regulator-always-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo8_reg: LDO8 { - regulator-name = "VUSB_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo9_reg: LDO9 { - regulator-name = "VCC_2.8V_PDA"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - ldo10_reg: LDO10 { - regulator-name = "VPLL_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - ldo11_reg: LDO11 { - regulator-name = "CAM_AF_3.0V"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo12_reg: LDO12 { - regulator-name = "CAM_SENSOR_CORE_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo13_reg: LDO13 { - regulator-name = "VGA_VDDIO_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo14_reg: LDO14 { - regulator-name = "VGA_DVDD_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo15_reg: LDO15 { - regulator-name = "CAM_ISP_HOST_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo16_reg: LDO16 { - regulator-name = "VGA_AVDD_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo17_reg: LDO17 { - regulator-name = "VCC_3.0V_LCD"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - /* Till we get panel driver */ - regulator-always-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck1_reg: BUCK1 { - regulator-name = "vddarm"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1500000>; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <1250000>; - }; - }; - - buck2_reg: BUCK2 { - regulator-name = "vddint"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1500000>; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <1100000>; - }; - }; - - buck3_reg: BUCK3 { - regulator-name = "VCC_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - buck4_reg: BUCK4 { - regulator-name = "CAM_ISP_CORE_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ap32khz_reg: EN32KHz-AP { - regulator-name = "32KHz AP"; - regulator-always-on; - }; - - cp32khz_reg: EN32KHz-CP { - regulator-name = "32KHz CP"; - }; - - vichg_reg: ENVICHG { - regulator-name = "VICHG"; - regulator-always-on; - }; - - safe1_sreg: ESAFEOUT1 { - regulator-name = "SAFEOUT1"; - }; - - safe2_sreg: ESAFEOUT2 { - regulator-name = "SAFEOUT2"; - }; - }; - }; - }; - - i2c_fuel: i2c-gpio-1 { - compatible = "i2c-gpio"; - sda-gpios = <&mp05 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - scl-gpios = <&mp05 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <2>; - #address-cells = <1>; - #size-cells = <0>; - - fuelgauge@36 { - compatible = "maxim,max17040"; - interrupt-parent = <&vic0>; - interrupts = <7>; - reg = <0x36>; - }; - }; - - vibrator: pwm-vibrator { - compatible = "pwm-vibrator"; - pwms = <&pwm 1 44642 0>; - pwm-names = "enable"; - vcc-supply = <&vibrator_pwr>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm1_out>; - }; - - poweroff: syscon-poweroff { - compatible = "syscon-poweroff"; - regmap = <&pmu_syscon>; - offset = <0x681c>; /* PS_HOLD_CONTROL */ - value = <0x5200>; - }; -}; - -&fimd { - pinctrl-names = "default"; - pinctrl-0 = <&lcd_clk &lcd_data24>; - status = "okay"; - - samsung,invert-vden; - samsung,invert-vclk; - - display-timings { - timing-0 { - /* 480x800@60Hz */ - clock-frequency = <25628040>; - hactive = <480>; - vactive = <800>; - hfront-porch = <16>; - hback-porch = <16>; - hsync-len = <2>; - vfront-porch = <28>; - vback-porch = <1>; - vsync-len = <2>; - }; - }; -}; - -&hsotg { - vusb_a-supply = <&ldo8_reg>; - vusb_d-supply = <&ldo3_reg>; - dr_mode = "peripheral"; - status = "okay"; -}; - -&i2c2 { - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <400000>; - samsung,i2c-slave-addr = <0x10>; - status = "okay"; - - touchscreen@4a { - compatible = "atmel,maxtouch"; - reg = <0x4a>; - interrupt-parent = <&gpj0>; - interrupts = <5 IRQ_TYPE_EDGE_FALLING>; - pinctrl-names = "default"; - pinctrl-0 = <&ts_irq>; - reset-gpios = <&gpj1 3 GPIO_ACTIVE_HIGH>; - }; -}; - -&mfc { - memory-region = <&mfc_left>, <&mfc_right>; -}; - -&pinctrl0 { - wlan_bt_en: wlan-bt-en { - samsung,pins = "gpb-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-val = <1>; - }; - - wlan_gpio_rst: wlan-gpio-rst { - samsung,pins = "gpg1-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - wifi_host_wake: wifi-host-wake { - samsung,pins = "gph2-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - bt_host_wake: bt-host-wake { - samsung,pins = "gph2-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - tf_detect: tf-detect { - samsung,pins = "gph3-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - wifi_wake: wifi-wake { - samsung,pins = "gph3-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - ts_irq: ts-irq { - samsung,pins = "gpj0-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pwm { - samsung,pwm-outputs = <1>; -}; - -&sdhci1 { - #address-cells = <1>; - #size-cells = <0>; - - bus-width = <4>; - max-frequency = <38400000>; - pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_bus4 &wifi_wake &wifi_host_wake &wlan_bt_en>; - pinctrl-names = "default"; - cap-sd-highspeed; - cap-mmc-highspeed; - - mmc-pwrseq = <&wifi_pwrseq>; - non-removable; - status = "okay"; - - wlan@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - interrupt-parent = <&gph2>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "host-wake"; - }; -}; - -&sdhci2 { - bus-width = <4>; - cd-gpios = <&gph3 4 GPIO_ACTIVE_LOW>; - vmmc-supply = <&ldo5_reg>; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &tf_detect>; - pinctrl-names = "default"; - status = "okay"; -}; - -&uart0 { - status = "okay"; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - max-speed = <115200>; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_data &uart0_fctl &bt_host_wake>; - shutdown-gpios = <&gpb 3 GPIO_ACTIVE_HIGH>; - device-wakeup-gpios = <&gpg3 4 GPIO_ACTIVE_HIGH>; - host-wakeup-gpios = <&gph2 5 GPIO_ACTIVE_HIGH>; - }; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&usbphy { - status = "okay"; - vbus-supply = <&safe1_sreg>; -}; - -&xusbxti { - clock-frequency = <24000000>; -}; diff --git a/sys/gnu/dts/arm/s5pv210-fascinate4g.dts b/sys/gnu/dts/arm/s5pv210-fascinate4g.dts deleted file mode 100644 index 07a8d9bbe5b..00000000000 --- a/sys/gnu/dts/arm/s5pv210-fascinate4g.dts +++ /dev/null @@ -1,38 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -/dts-v1/; -#include -#include -#include "s5pv210-aries.dtsi" - -/ { - model = "Samsung Galaxy S Fascinate 4G (SGH-T959P) based on S5PV210"; - compatible = "samsung,fascinate4g", "samsung,aries", "samsung,s5pv210"; - - chosen { - stdout-path = &uart2; - }; - - gpio-keys { - compatible = "gpio-keys"; - - power { - label = "power"; - gpios = <&gph2 6 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - - vol-down { - label = "volume_down"; - gpios = <&gph3 2 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - vol-up { - label = "volume_up"; - gpios = <&gph3 1 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; -}; diff --git a/sys/gnu/dts/arm/s5pv210-galaxys.dts b/sys/gnu/dts/arm/s5pv210-galaxys.dts deleted file mode 100644 index cf161bbfbac..00000000000 --- a/sys/gnu/dts/arm/s5pv210-galaxys.dts +++ /dev/null @@ -1,70 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -/dts-v1/; -#include -#include -#include "s5pv210-aries.dtsi" - -/ { - model = "Samsung Galaxy S1 (GT-I9000) based on S5PV210"; - compatible = "samsung,galaxys", "samsung,aries", "samsung,s5pv210"; - - chosen { - stdout-path = &uart2; - }; - - nand_pwrseq: nand-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpj2 7 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&massmemory_en>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - power { - label = "power"; - gpios = <&gph2 6 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - - vol-down { - label = "volume_down"; - gpios = <&gph3 1 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - vol-up { - label = "volume_up"; - gpios = <&gph3 2 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - home { - label = "home"; - gpios = <&gph3 5 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - }; -}; - -&pinctrl0 { - massmemory_en: massmemory-en { - samsung,pins = "gpj2-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&sdhci0 { - bus-width = <4>; - non-removable; - mmc-pwrseq = <&nand_pwrseq>; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4>; - pinctrl-names = "default"; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/s5pv210-goni.dts b/sys/gnu/dts/arm/s5pv210-goni.dts deleted file mode 100644 index fbbd9370740..00000000000 --- a/sys/gnu/dts/arm/s5pv210-goni.dts +++ /dev/null @@ -1,447 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's S5PV210 SoC device tree source - * - * Copyright (c) 2013-2014 Samsung Electronics, Co. Ltd. - * - * Mateusz Krawczuk - * Tomasz Figa - * - * Board device tree source for Samsung Goni board. - */ - -/dts-v1/; -#include -#include "s5pv210.dtsi" - -/ { - model = "Samsung Goni based on S5PC110"; - compatible = "samsung,goni", "samsung,s5pv210"; - - aliases { - i2c3 = &i2c_pmic; - }; - - chosen { - bootargs = "console=ttySAC0,115200n8 root=/dev/mmcblk0p5 rw rootwait ignore_loglevel earlyprintk"; - }; - - memory@30000000 { - device_type = "memory"; - reg = <0x30000000 0x05000000 - 0x40000000 0x10000000 - 0x50000000 0x08000000>; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - vtf_reg: fixed-regulator@0 { - compatible = "regulator-fixed"; - regulator-name = "V_TF_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - reg = <0>; - gpio = <&mp05 4 0>; - enable-active-high; - }; - - pda_reg: fixed-regulator@1 { - compatible = "regulator-fixed"; - regulator-name = "VCC_1.8V_PDA"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - reg = <1>; - }; - - bat_reg: fixed-regulator@2 { - compatible = "regulator-fixed"; - regulator-name = "V_BAT"; - regulator-min-microvolt = <3700000>; - regulator-max-microvolt = <3700000>; - reg = <2>; - }; - - tsp_reg: fixed-regulator@3 { - compatible = "regulator-fixed"; - regulator-name = "TSP_VDD"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - reg = <3>; - gpio = <&gpj1 3 0>; - enable-active-high; - }; - }; - - i2c_pmic: i2c-pmic { - compatible = "i2c-gpio"; - gpios = <&gpj4 0 0>, /* sda */ - <&gpj4 3 0>; /* scl */ - i2c-gpio,delay-us = <2>; /* ~100 kHz */ - #address-cells = <1>; - #size-cells = <0>; - - pmic@66 { - compatible = "national,lp3974"; - reg = <0x66>; - - max8998,pmic-buck1-default-dvs-idx = <0>; - max8998,pmic-buck1-dvs-gpios = <&gph0 3 0>, - <&gph0 4 0>; - max8998,pmic-buck1-dvs-voltage = <1200000>, <1200000>, - <1200000>, <1200000>; - - max8998,pmic-buck2-default-dvs-idx = <0>; - max8998,pmic-buck2-dvs-gpio = <&gph0 5 0>; - max8998,pmic-buck2-dvs-voltage = <1200000>, <1200000>; - - regulators { - ldo2_reg: LDO2 { - regulator-name = "VALIVE_1.1V"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - ldo3_reg: LDO3 { - regulator-name = "VUSB+MIPI_1.1V"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - ldo4_reg: LDO4 { - regulator-name = "VADC_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo5_reg: LDO5 { - regulator-name = "VTF_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo6_reg: LDO6 { - regulator-name = "VCC_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo7_reg: LDO7 { - regulator-name = "VLCD_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo8_reg: LDO8 { - regulator-name = "VUSB+VDAC_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo9_reg: LDO9 { - regulator-name = "VCC+VCAM_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo10_reg: LDO10 { - regulator-name = "VPLL_1.1V"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-boot-on; - }; - - ldo11_reg: LDO11 { - regulator-name = "CAM_IO_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo12_reg: LDO12 { - regulator-name = "CAM_ISP_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - ldo13_reg: LDO13 { - regulator-name = "CAM_A_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo14_reg: LDO14 { - regulator-name = "CAM_CIF_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo15_reg: LDO15 { - regulator-name = "CAM_AF_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo16_reg: LDO16 { - regulator-name = "VMIPI_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo17_reg: LDO17 { - regulator-name = "CAM_8M_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - buck1_reg: BUCK1 { - regulator-name = "VARM_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - buck2_reg: BUCK2 { - regulator-name = "VINT_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - buck3_reg: BUCK3 { - regulator-name = "VCC_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - buck4_reg: BUCK4 { - regulator-name = "CAM_CORE_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - }; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - power-key { - gpios = <&gph2 6 1>; - linux,code = ; - label = "power"; - debounce-interval = <1>; - wakeup-source; - }; - }; -}; - -&xusbxti { - clock-frequency = <24000000>; -}; - -&keypad { - linux,input-no-autorepeat; - wakeup-source; - samsung,keypad-num-rows = <3>; - samsung,keypad-num-columns = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&keypad_row0>, <&keypad_row1>, <&keypad_row2>, - <&keypad_col0>, <&keypad_col1>, <&keypad_col2>; - status = "okay"; - - key_1 { - keypad,row = <0>; - keypad,column = <1>; - linux,code = ; - }; - - key_2 { - keypad,row = <0>; - keypad,column = <2>; - linux,code = ; - }; - - key_3 { - keypad,row = <1>; - keypad,column = <1>; - linux,code = ; - }; - - key_4 { - keypad,row = <1>; - keypad,column = <2>; - linux,code = ; - }; - - key_5 { - keypad,row = <2>; - keypad,column = <1>; - linux,code = ; - }; - - key_6 { - keypad,row = <2>; - keypad,column = <2>; - linux,code = ; - }; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&sdhci0 { - bus-width = <4>; - non-removable; - vmmc-supply = <&ldo5_reg>; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus1 &sd0_bus4>; - pinctrl-names = "default"; - status = "okay"; -}; - -&sdhci2 { - bus-width = <4>; - cd-gpios = <&gph3 4 1>; - vmmc-supply = <&vtf_reg>; - cd-inverted; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4>; - pinctrl-names = "default"; - status = "okay"; -}; - -&hsotg { - vusb_a-supply = <&ldo3_reg>; - vusb_d-supply = <&ldo8_reg>; - dr_mode = "peripheral"; - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; - -&i2c2 { - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <400000>; - samsung,i2c-slave-addr = <0x10>; - status = "okay"; - - tsp@4a { - compatible = "atmel,maxtouch"; - reg = <0x4a>; - interrupt-parent = <&gpj0>; - interrupts = <5 2>; - - atmel,x-line = <17>; - atmel,y-line = <11>; - atmel,x-size = <800>; - atmel,y-size = <480>; - atmel,burst-length = <0x21>; - atmel,threshold = <0x28>; - atmel,orientation = <1>; - - vdd-supply = <&tsp_reg>; - }; -}; - -&i2c0 { - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <100000>; - samsung,i2c-slave-addr = <0x10>; - status = "okay"; - - noon010pc30: sensor@30 { - compatible = "siliconfile,noon010pc30"; - reg = <0x30>; - vddio-supply = <&ldo11_reg>; - vdda-supply = <&ldo13_reg>; - vdd_core-supply = <&ldo14_reg>; - - clock-frequency = <16000000>; - clocks = <&camera 0>; - clock-names = "mclk"; - nreset-gpios = <&gpb 2 0>; - nstby-gpios = <&gpb 0 0>; - - port { - noon010pc30_ep: endpoint { - remote-endpoint = <&fimc0_ep>; - bus-width = <8>; - hsync-active = <0>; - vsync-active = <1>; - pclk-sample = <1>; - }; - }; - }; -}; - -&camera { - pinctrl-0 = <&cam_port_a_io &cam_port_a_clk_active>; - pinctrl-1 = <&cam_port_a_io &cam_port_a_clk_idle>; - pinctrl-names = "default", "idle"; - - parallel-ports { - #address-cells = <1>; - #size-cells = <0>; - - /* camera A input */ - port@1 { - reg = <1>; - fimc0_ep: endpoint { - remote-endpoint = <&noon010pc30_ep>; - bus-width = <8>; - hsync-active = <1>; - vsync-active = <1>; - pclk-sample = <0>; - }; - }; - }; -}; - -&fimd { - pinctrl-0 = <&lcd_clk &lcd_data24>; - pinctrl-names = "default"; - status = "okay"; - - display-timings { - native-mode = <&timing0>; - timing0: timing { - /* 480x800@55Hz */ - clock-frequency = <23439570>; - hactive = <480>; - hfront-porch = <16>; - hback-porch = <16>; - hsync-len = <2>; - vactive = <800>; - vback-porch = <2>; - vfront-porch = <28>; - vsync-len = <1>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - }; - }; -}; - -&onenand { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/s5pv210-pinctrl.dtsi b/sys/gnu/dts/arm/s5pv210-pinctrl.dtsi deleted file mode 100644 index 7f0c9d44787..00000000000 --- a/sys/gnu/dts/arm/s5pv210-pinctrl.dtsi +++ /dev/null @@ -1,840 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's S5PV210 SoC device tree source - * - * Copyright (c) 2013-2014 Samsung Electronics, Co. Ltd. - * - * Mateusz Krawczuk - * Tomasz Figa - * - * Samsung's S5PV210 SoC device nodes are listed in this file. S5PV210 - * based board files can include this file and provide values for board specfic - * bindings. - * - * Note: This file does not include device nodes for all the controllers in - * S5PV210 SoC. As device tree coverage for S5PV210 increases, additional - * nodes can be added to this file. - */ - -#include - -&pinctrl0 { - gpa0: gpa0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpa1: gpa1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpb: gpb { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc0: gpc0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc1: gpc1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpd0: gpd0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpd1: gpd1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpe0: gpe0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpe1: gpe1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf0: gpf0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf1: gpf1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf2: gpf2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf3: gpf3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpg0: gpg0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpg1: gpg1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpg2: gpg2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpg3: gpg3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpj0: gpj0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpj1: gpj1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpj2: gpj2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpj3: gpj3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpj4: gpj4 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpgi: gpgi { - gpio-controller; - #gpio-cells = <2>; - }; - - mp01: mp01 { - gpio-controller; - #gpio-cells = <2>; - }; - - mp02: mp02 { - gpio-controller; - #gpio-cells = <2>; - }; - - mp03: mp03 { - gpio-controller; - #gpio-cells = <2>; - }; - - mp04: mp04 { - gpio-controller; - #gpio-cells = <2>; - }; - - mp05: mp05 { - gpio-controller; - #gpio-cells = <2>; - }; - - mp06: mp06 { - gpio-controller; - #gpio-cells = <2>; - }; - - mp07: mp07 { - gpio-controller; - #gpio-cells = <2>; - }; - - gph0: gph0 { - gpio-controller; - interrupt-controller; - interrupt-parent = <&vic0>; - interrupts = <0>, <1>, <2>, <3>, - <4>, <5>, <6>, <7>; - #gpio-cells = <2>; - #interrupt-cells = <2>; - }; - - gph1: gph1 { - gpio-controller; - interrupt-controller; - interrupt-parent = <&vic0>; - interrupts = <8>, <9>, <10>, <11>, - <12>, <13>, <14>, <15>; - #gpio-cells = <2>; - #interrupt-cells = <2>; - }; - - gph2: gph2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gph3: gph3 { - gpio-controller; - #gpio-cells = <2>; - #interrupt-cells = <2>; - }; - - uart0_data: uart0-data { - samsung,pins = "gpa0-0", "gpa0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart0_fctl: uart0-fctl { - samsung,pins = "gpa0-2", "gpa0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart1_data: uart1-data { - samsung,pins = "gpa0-4", "gpa0-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart1_fctl: uart1-fctl { - samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart2_data: uart2-data { - samsung,pins = "gpa1-0", "gpa1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart2_fctl: uart2-fctl { - samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart3_data: uart3-data { - samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart_audio: uart-audio { - samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spi0_bus: spi0-bus { - samsung,pins = "gpb-0", "gpb-2", "gpb-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spi1_bus: spi1-bus { - samsung,pins = "gpb-4", "gpb-6", "gpb-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2s0_bus: i2s0-bus { - samsung,pins = "gpi-0", "gpi-1", "gpi-2", "gpi-3", - "gpi-4", "gpi-5", "gpi-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2s1_bus: i2s1-bus { - samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", - "gpc0-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2s2_bus: i2s2-bus { - samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", - "gpc1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pcm1_bus: pcm1-bus { - samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", - "gpc0-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - ac97_bus: ac97-bus { - samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", - "gpc0-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2s2_bus: i2s2-bus { - samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", - "gpc1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pcm2_bus: pcm2-bus { - samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", - "gpc1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spdif_bus: spdif-bus { - samsung,pins = "gpc1-0", "gpc1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spi2_bus: spi2-bus { - samsung,pins = "gpc1-1", "gpc1-2", "gpc1-3", "gpc1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c0_bus: i2c0-bus { - samsung,pins = "gpd1-0", "gpd1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c1_bus: i2c1-bus { - samsung,pins = "gpd1-2", "gpd1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c2_bus: i2c2-bus { - samsung,pins = "gpd1-4", "gpd1-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm0_out: pwm0-out { - samsung,pins = "gpd0-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm1_out: pwm1-out { - samsung,pins = "gpd0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm2_out: pwm2-out { - samsung,pins = "gpd0-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm3_out: pwm3-out { - samsung,pins = "gpd0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - keypad_row0: keypad-row-0 { - samsung,pins = "gph3-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - keypad_row1: keypad-row-1 { - samsung,pins = "gph3-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - keypad_row2: keypad-row-2 { - samsung,pins = "gph3-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - keypad_row3: keypad-row-3 { - samsung,pins = "gph3-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - keypad_row4: keypad-row-4 { - samsung,pins = "gph3-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - keypad_row5: keypad-row-5 { - samsung,pins = "gph3-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - keypad_row6: keypad-row-6 { - samsung,pins = "gph3-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - keypad_row7: keypad-row-7 { - samsung,pins = "gph3-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - keypad_col0: keypad-col-0 { - samsung,pins = "gph2-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - keypad_col1: keypad-col-1 { - samsung,pins = "gph2-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - keypad_col2: keypad-col-2 { - samsung,pins = "gph2-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - keypad_col3: keypad-col-3 { - samsung,pins = "gph2-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - keypad_col4: keypad-col-4 { - samsung,pins = "gph2-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - keypad_col5: keypad-col-5 { - samsung,pins = "gph2-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - keypad_col6: keypad-col-6 { - samsung,pins = "gph2-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - keypad_col7: keypad-col-7 { - samsung,pins = "gph2-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_clk: sd0-clk { - samsung,pins = "gpg0-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_cmd: sd0-cmd { - samsung,pins = "gpg0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_cd: sd0-cd { - samsung,pins = "gpg0-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus1: sd0-bus-width1 { - samsung,pins = "gpg0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus4: sd0-bus-width4 { - samsung,pins = "gpg0-3", "gpg0-4", "gpg0-5", "gpg0-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus8: sd0-bus-width8 { - samsung,pins = "gpg1-3", "gpg1-4", "gpg1-5", "gpg1-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_clk: sd1-clk { - samsung,pins = "gpg1-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_cmd: sd1-cmd { - samsung,pins = "gpg1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_cd: sd1-cd { - samsung,pins = "gpg1-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_bus1: sd1-bus-width1 { - samsung,pins = "gpg1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_bus4: sd1-bus-width4 { - samsung,pins = "gpg1-3", "gpg1-4", "gpg1-5", "gpg1-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_clk: sd2-clk { - samsung,pins = "gpg2-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_cmd: sd2-cmd { - samsung,pins = "gpg2-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_cd: sd2-cd { - samsung,pins = "gpg2-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_bus1: sd2-bus-width1 { - samsung,pins = "gpg2-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_bus4: sd2-bus-width4 { - samsung,pins = "gpg2-3", "gpg2-4", "gpg2-5", "gpg2-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_bus8: sd2-bus-width8 { - samsung,pins = "gpg3-3", "gpg3-4", "gpg3-5", "gpg3-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd3_clk: sd3-clk { - samsung,pins = "gpg3-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd3_cmd: sd3-cmd { - samsung,pins = "gpg3-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd3_cd: sd3-cd { - samsung,pins = "gpg3-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd3_bus1: sd3-bus-width1 { - samsung,pins = "gpg3-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd3_bus4: sd3-bus-width4 { - samsung,pins = "gpg3-3", "gpg3-4", "gpg3-5", "gpg3-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - eint0: ext-int0 { - samsung,pins = "gph0-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - eint8: ext-int8 { - samsung,pins = "gph1-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - eint15: ext-int15 { - samsung,pins = "gph1-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - eint16: ext-int16 { - samsung,pins = "gph2-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - eint31: ext-int31 { - samsung,pins = "gph3-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_port_a_io: cam-port-a-io { - samsung,pins = "gpe0-0", "gpe0-1", "gpe0-2", "gpe0-3", - "gpe0-4", "gpe0-5", "gpe0-6", "gpe0-7", - "gpe1-0", "gpe1-1", "gpe1-2", "gpe1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_port_a_clk_active: cam-port-a-clk-active { - samsung,pins = "gpe1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_port_a_clk_idle: cam-port-a-clk-idle { - samsung,pins = "gpe1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_port_b_io: cam-port-b-io { - samsung,pins = "gpj0-0", "gpj0-1", "gpj0-2", "gpj0-3", - "gpj0-4", "gpj0-5", "gpj0-6", "gpj0-7", - "gpj1-0", "gpj1-1", "gpj1-2", "gpj1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_port_b_clk_active: cam-port-b-clk-active { - samsung,pins = "gpj1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_port_b_clk_idle: cam-port-b-clk-idle { - samsung,pins = "gpj1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - lcd_ctrl: lcd-ctrl { - samsung,pins = "gpd0-0", "gpd0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - lcd_sync: lcd-sync { - samsung,pins = "gpf0-0", "gpf0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - lcd_clk: lcd-clk { - samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - lcd_data24: lcd-data-width24 { - samsung,pins = "gpf0-4", "gpf0-5", "gpf0-6", "gpf0-7", - "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3", - "gpf1-4", "gpf1-5", "gpf1-6", "gpf1-7", - "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3", - "gpf2-4", "gpf2-5", "gpf2-6", "gpf2-7", - "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; diff --git a/sys/gnu/dts/arm/s5pv210-smdkc110.dts b/sys/gnu/dts/arm/s5pv210-smdkc110.dts deleted file mode 100644 index e5aec6c526f..00000000000 --- a/sys/gnu/dts/arm/s5pv210-smdkc110.dts +++ /dev/null @@ -1,75 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's S5PV210 SoC device tree source - * - * Copyright (c) 2013-2014 Samsung Electronics, Co. Ltd. - * - * Mateusz Krawczuk - * Tomasz Figa - * - * Board device tree source for YIC System SMDC110 board. - * - * NOTE: This file is completely based on original board file for mach-smdkc110 - * available in Linux 3.15 and intends to provide equivalent level of hardware - * support. Due to lack of hardware, _no_ testing has been performed. - */ - -/dts-v1/; -#include -#include "s5pv210.dtsi" - -/ { - model = "YIC System SMDKC110 based on S5PC110"; - compatible = "yic,smdkc110", "samsung,s5pv210"; - - chosen { - bootargs = "console=ttySAC0,115200n8 root=/dev/mmcblk0p1 rw rootwait ignore_loglevel earlyprintk"; - }; - - memory@20000000 { - device_type = "memory"; - reg = <0x20000000 0x20000000>; - }; -}; - -&xusbxti { - clock-frequency = <24000000>; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&rtc { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - audio-codec@1b { - compatible = "wlf,wm8580"; - reg = <0x1b>; - }; - - eeprom@50 { - compatible = "atmel,24c08"; - reg = <0x50>; - }; -}; - -&i2s0 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/s5pv210-smdkv210.dts b/sys/gnu/dts/arm/s5pv210-smdkv210.dts deleted file mode 100644 index 84b38f18519..00000000000 --- a/sys/gnu/dts/arm/s5pv210-smdkv210.dts +++ /dev/null @@ -1,236 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's S5PV210 SoC device tree source - * - * Copyright (c) 2013-2014 Samsung Electronics, Co. Ltd. - * - * Mateusz Krawczuk - * Tomasz Figa - * - * Board device tree source for YIC System SMDV210 board. - * - * NOTE: This file is completely based on original board file for mach-smdkv210 - * available in Linux 3.15 and intends to provide equivalent level of hardware - * support. Due to lack of hardware, _no_ testing has been performed. - */ - -/dts-v1/; -#include -#include "s5pv210.dtsi" - -/ { - model = "YIC System SMDKV210 based on S5PV210"; - compatible = "yic,smdkv210", "samsung,s5pv210"; - - chosen { - bootargs = "console=ttySAC0,115200n8 root=/dev/mmcblk0p1 rw rootwait ignore_loglevel earlyprintk"; - }; - - memory@20000000 { - device_type = "memory"; - reg = <0x20000000 0x40000000>; - }; - - ethernet@18000000 { - compatible = "davicom,dm9000"; - reg = <0xA8000000 0x2 0xA8000002 0x2>; - interrupt-parent = <&gph1>; - interrupts = <1 4>; - local-mac-address = [00 00 de ad be ef]; - davicom,no-eeprom; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 3 5000000 0>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm3_out>; - }; -}; - -&xusbxti { - clock-frequency = <24000000>; -}; - -&keypad { - linux,input-no-autorepeat; - wakeup-source; - samsung,keypad-num-rows = <8>; - samsung,keypad-num-columns = <8>; - pinctrl-names = "default"; - pinctrl-0 = <&keypad_row0>, <&keypad_row1>, <&keypad_row2>, - <&keypad_row3>, <&keypad_row4>, <&keypad_row5>, - <&keypad_row6>, <&keypad_row7>, - <&keypad_col0>, <&keypad_col1>, <&keypad_col2>, - <&keypad_col3>, <&keypad_col4>, <&keypad_col5>, - <&keypad_col6>, <&keypad_col7>; - status = "okay"; - - key_1 { - keypad,row = <0>; - keypad,column = <3>; - linux,code = ; - }; - - key_2 { - keypad,row = <0>; - keypad,column = <4>; - linux,code = ; - }; - - key_3 { - keypad,row = <0>; - keypad,column = <5>; - linux,code = ; - }; - - key_4 { - keypad,row = <0>; - keypad,column = <6>; - linux,code = ; - }; - - key_5 { - keypad,row = <0 - >; - keypad,column = <7>; - linux,code = ; - }; - - key_6 { - keypad,row = <1>; - keypad,column = <3>; - linux,code = ; - }; - key_7 { - keypad,row = <1>; - keypad,column = <4>; - linux,code = ; - }; - - key_8 { - keypad,row = <1>; - keypad,column = <5>; - linux,code = ; - }; - - key_9 { - keypad,row = <1>; - keypad,column = <6>; - linux,code = ; - }; - - key_10 { - keypad,row = <1>; - keypad,column = <7>; - linux,code = ; - }; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&rtc { - status = "okay"; -}; - -&sdhci0 { - bus-width = <4>; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus1 &sd0_bus4>; - pinctrl-names = "default"; - status = "okay"; -}; - -&sdhci1 { - bus-width = <4>; - pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus1 &sd1_bus4>; - pinctrl-names = "default"; - status = "okay"; -}; - -&sdhci2 { - bus-width = <4>; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>; - pinctrl-names = "default"; - status = "okay"; -}; - -&sdhci3 { - bus-width = <4>; - pinctrl-0 = <&sd3_clk &sd3_cmd &sd3_cd &sd3_bus1 &sd3_bus4>; - pinctrl-names = "default"; - status = "okay"; -}; - -&hsotg { - dr_mode = "peripheral"; - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; - -&fimd { - pinctrl-0 = <&lcd_clk &lcd_data24>; - pinctrl-names = "default"; - status = "okay"; - - display-timings { - native-mode = <&timing0>; - - timing0: timing { - /* 800x480@60Hz */ - clock-frequency = <24373920>; - hactive = <800>; - vactive = <480>; - hfront-porch = <8>; - hback-porch = <13>; - hsync-len = <3>; - vback-porch = <7>; - vfront-porch = <5>; - vsync-len = <1>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; -}; - -&pwm { - samsung,pwm-outputs = <3>; -}; - -&i2c0 { - status = "okay"; - - audio-codec@1b { - compatible = "wlf,wm8580"; - reg = <0x1b>; - }; - - eeprom@50 { - compatible = "atmel,24c08"; - reg = <0x50>; - }; -}; - -&i2s0 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/s5pv210-torbreck.dts b/sys/gnu/dts/arm/s5pv210-torbreck.dts deleted file mode 100644 index cd25e72ccd8..00000000000 --- a/sys/gnu/dts/arm/s5pv210-torbreck.dts +++ /dev/null @@ -1,89 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's S5PV210 SoC device tree source - * - * Copyright (c) 2013-2014 Samsung Electronics, Co. Ltd. - * - * Mateusz Krawczuk - * Tomasz Figa - * - * Board device tree source for Torbreck board. - * - * NOTE: This file is completely based on original board file for mach-torbreck - * available in Linux 3.15 and intends to provide equivalent level of hardware - * support. Due to lack of hardware, _no_ testing has been performed. - */ - -/dts-v1/; -#include -#include "s5pv210.dtsi" - -/ { - model = "aESOP Torbreck based on S5PV210"; - compatible = "aesop,torbreck", "samsung,s5pv210"; - - chosen { - bootargs = "console=ttySAC0,115200n8 root=/dev/mmcblk0p1 rw rootwait ignore_loglevel earlyprintk"; - }; - - memory@20000000 { - device_type = "memory"; - reg = <0x20000000 0x20000000>; - }; -}; - -&xusbxti { - clock-frequency = <24000000>; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&rtc { - status = "okay"; -}; - -&sdhci0 { - bus-width = <4>; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus1 &sd0_bus4>; - pinctrl-names = "default"; - status = "okay"; -}; - -&sdhci1 { - bus-width = <4>; - pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus1 &sd1_bus4>; - pinctrl-names = "default"; - status = "okay"; -}; - -&sdhci2 { - bus-width = <4>; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus1 &sd2_bus4>; - pinctrl-names = "default"; - status = "okay"; -}; - -&sdhci3 { - bus-width = <4>; - pinctrl-0 = <&sd3_clk &sd3_cmd &sd3_cd &sd3_bus1 &sd3_bus4>; - pinctrl-names = "default"; - status = "okay"; -}; - -&i2s0 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/s5pv210.dtsi b/sys/gnu/dts/arm/s5pv210.dtsi deleted file mode 100644 index 2ad642f51fd..00000000000 --- a/sys/gnu/dts/arm/s5pv210.dtsi +++ /dev/null @@ -1,661 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's S5PV210 SoC device tree source - * - * Copyright (c) 2013-2014 Samsung Electronics, Co. Ltd. - * - * Mateusz Krawczuk - * Tomasz Figa - * - * Samsung's S5PV210 SoC device nodes are listed in this file. S5PV210 - * based board files can include this file and provide values for board specfic - * bindings. - * - * Note: This file does not include device nodes for all the controllers in - * S5PV210 SoC. As device tree coverage for S5PV210 increases, additional - * nodes can be added to this file. - */ - -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - - aliases { - csis0 = &csis0; - dmc0 = &dmc0; - dmc1 = &dmc1; - fimc0 = &fimc0; - fimc1 = &fimc1; - fimc2 = &fimc2; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2s0 = &i2s0; - i2s1 = &i2s1; - i2s2 = &i2s2; - pinctrl0 = &pinctrl0; - spi0 = &spi0; - spi1 = &spi1; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a8"; - reg = <0>; - }; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - external-clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - xxti: oscillator@0 { - compatible = "fixed-clock"; - reg = <0>; - clock-frequency = <0>; - clock-output-names = "xxti"; - #clock-cells = <0>; - }; - - xusbxti: oscillator@1 { - compatible = "fixed-clock"; - reg = <1>; - clock-frequency = <0>; - clock-output-names = "xusbxti"; - #clock-cells = <0>; - }; - }; - - onenand: onenand@b0600000 { - compatible = "samsung,s5pv210-onenand"; - reg = <0xb0600000 0x2000>, - <0xb0000000 0x20000>, - <0xb0040000 0x20000>; - interrupt-parent = <&vic1>; - interrupts = <31>; - clocks = <&clocks CLK_NANDXL>, <&clocks DOUT_FLASH>; - clock-names = "bus", "onenand"; - #address-cells = <1>; - #size-cells = <1>; - status = "disabled"; - }; - - chipid@e0000000 { - compatible = "samsung,s5pv210-chipid"; - reg = <0xe0000000 0x1000>; - }; - - clocks: clock-controller@e0100000 { - compatible = "samsung,s5pv210-clock", "simple-bus"; - reg = <0xe0100000 0x10000>; - clock-names = "xxti", "xusbxti"; - clocks = <&xxti>, <&xusbxti>; - #clock-cells = <1>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - pmu_syscon: syscon@e0108000 { - compatible = "samsung-s5pv210-pmu", "syscon"; - reg = <0xe0108000 0x8000>; - }; - }; - - pinctrl0: pinctrl@e0200000 { - compatible = "samsung,s5pv210-pinctrl"; - reg = <0xe0200000 0x1000>; - interrupt-parent = <&vic0>; - interrupts = <30>; - - wakeup-interrupt-controller { - compatible = "samsung,s5pv210-wakeup-eint"; - interrupts = <16>; - interrupt-parent = <&vic0>; - }; - }; - - amba { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges; - - pdma0: dma@e0900000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0xe0900000 0x1000>; - interrupt-parent = <&vic0>; - interrupts = <19>; - clocks = <&clocks CLK_PDMA0>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; - }; - - pdma1: dma@e0a00000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0xe0a00000 0x1000>; - interrupt-parent = <&vic0>; - interrupts = <20>; - clocks = <&clocks CLK_PDMA1>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; - }; - }; - - spi0: spi@e1300000 { - compatible = "samsung,s5pv210-spi"; - reg = <0xe1300000 0x1000>; - interrupt-parent = <&vic1>; - interrupts = <15>; - dmas = <&pdma0 7>, <&pdma0 6>; - dma-names = "tx", "rx"; - clocks = <&clocks SCLK_SPI0>, <&clocks CLK_SPI0>; - clock-names = "spi", "spi_busclk0"; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_bus>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi1: spi@e1400000 { - compatible = "samsung,s5pv210-spi"; - reg = <0xe1400000 0x1000>; - interrupt-parent = <&vic1>; - interrupts = <16>; - dmas = <&pdma1 7>, <&pdma1 6>; - dma-names = "tx", "rx"; - clocks = <&clocks SCLK_SPI1>, <&clocks CLK_SPI1>; - clock-names = "spi", "spi_busclk0"; - pinctrl-names = "default"; - pinctrl-0 = <&spi1_bus>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - keypad: keypad@e1600000 { - compatible = "samsung,s5pv210-keypad"; - reg = <0xe1600000 0x1000>; - interrupt-parent = <&vic2>; - interrupts = <25>; - clocks = <&clocks CLK_KEYIF>; - clock-names = "keypad"; - status = "disabled"; - }; - - i2c0: i2c@e1800000 { - compatible = "samsung,s3c2440-i2c"; - reg = <0xe1800000 0x1000>; - interrupt-parent = <&vic1>; - interrupts = <14>; - clocks = <&clocks CLK_I2C0>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_bus>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@e1a00000 { - compatible = "samsung,s3c2440-i2c"; - reg = <0xe1a00000 0x1000>; - interrupt-parent = <&vic1>; - interrupts = <19>; - clocks = <&clocks CLK_I2C2>; - clock-names = "i2c"; - pinctrl-0 = <&i2c2_bus>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - audio-subsystem { - compatible = "samsung,s5pv210-audss", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - clk_audss: clock-controller@eee10000 { - compatible = "samsung,s5pv210-audss-clock"; - reg = <0xeee10000 0x1000>; - clock-names = "hclk", "xxti", - "fout_epll", - "sclk_audio0"; - clocks = <&clocks DOUT_HCLKP>, <&xxti>, - <&clocks FOUT_EPLL>, - <&clocks SCLK_AUDIO0>; - #clock-cells = <1>; - }; - - i2s0: i2s@eee30000 { - compatible = "samsung,s5pv210-i2s"; - reg = <0xeee30000 0x1000>; - interrupt-parent = <&vic2>; - interrupts = <16>; - dma-names = "rx", "tx", "tx-sec"; - dmas = <&pdma1 9>, <&pdma1 10>, <&pdma1 11>; - clock-names = "iis", - "i2s_opclk0", - "i2s_opclk1"; - clocks = <&clk_audss CLK_I2S>, - <&clk_audss CLK_I2S>, - <&clk_audss CLK_DOUT_AUD_BUS>; - samsung,idma-addr = <0xc0010000>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_bus>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - }; - - i2s1: i2s@e2100000 { - compatible = "samsung,s3c6410-i2s"; - reg = <0xe2100000 0x1000>; - interrupt-parent = <&vic2>; - interrupts = <17>; - dma-names = "rx", "tx"; - dmas = <&pdma1 12>, <&pdma1 13>; - clock-names = "iis", "i2s_opclk0"; - clocks = <&clocks CLK_I2S1>, <&clocks SCLK_AUDIO1>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s1_bus>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - i2s2: i2s@e2a00000 { - compatible = "samsung,s3c6410-i2s"; - reg = <0xe2a00000 0x1000>; - interrupt-parent = <&vic2>; - interrupts = <18>; - dma-names = "rx", "tx"; - dmas = <&pdma1 14>, <&pdma1 15>; - clock-names = "iis", "i2s_opclk0"; - clocks = <&clocks CLK_I2S2>, <&clocks SCLK_AUDIO2>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s2_bus>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - pwm: pwm@e2500000 { - compatible = "samsung,s5pc100-pwm"; - reg = <0xe2500000 0x1000>; - interrupt-parent = <&vic0>; - interrupts = <21>, <22>, <23>, <24>, <25>; - clock-names = "timers"; - clocks = <&clocks CLK_PWM>; - #pwm-cells = <3>; - }; - - watchdog: watchdog@e2700000 { - compatible = "samsung,s3c6410-wdt"; - reg = <0xe2700000 0x1000>; - interrupt-parent = <&vic0>; - interrupts = <26>; - clock-names = "watchdog"; - clocks = <&clocks CLK_WDT>; - }; - - rtc: rtc@e2800000 { - compatible = "samsung,s3c6410-rtc"; - reg = <0xe2800000 0x100>; - interrupt-parent = <&vic0>; - interrupts = <28>, <29>; - clocks = <&clocks CLK_RTC>; - clock-names = "rtc"; - status = "disabled"; - }; - - uart0: serial@e2900000 { - compatible = "samsung,s5pv210-uart"; - reg = <0xe2900000 0x400>; - interrupt-parent = <&vic1>; - interrupts = <10>; - clock-names = "uart", "clk_uart_baud0", - "clk_uart_baud1"; - clocks = <&clocks CLK_UART0>, <&clocks CLK_UART0>, - <&clocks SCLK_UART0>; - status = "disabled"; - }; - - uart1: serial@e2900400 { - compatible = "samsung,s5pv210-uart"; - reg = <0xe2900400 0x400>; - interrupt-parent = <&vic1>; - interrupts = <11>; - clock-names = "uart", "clk_uart_baud0", - "clk_uart_baud1"; - clocks = <&clocks CLK_UART1>, <&clocks CLK_UART1>, - <&clocks SCLK_UART1>; - status = "disabled"; - }; - - uart2: serial@e2900800 { - compatible = "samsung,s5pv210-uart"; - reg = <0xe2900800 0x400>; - interrupt-parent = <&vic1>; - interrupts = <12>; - clock-names = "uart", "clk_uart_baud0", - "clk_uart_baud1"; - clocks = <&clocks CLK_UART2>, <&clocks CLK_UART2>, - <&clocks SCLK_UART2>; - status = "disabled"; - }; - - uart3: serial@e2900c00 { - compatible = "samsung,s5pv210-uart"; - reg = <0xe2900c00 0x400>; - interrupt-parent = <&vic1>; - interrupts = <13>; - clock-names = "uart", "clk_uart_baud0", - "clk_uart_baud1"; - clocks = <&clocks CLK_UART3>, <&clocks CLK_UART3>, - <&clocks SCLK_UART3>; - status = "disabled"; - }; - - sdhci0: sdhci@eb000000 { - compatible = "samsung,s3c6410-sdhci"; - reg = <0xeb000000 0x100000>; - interrupt-parent = <&vic1>; - interrupts = <26>; - clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.2"; - clocks = <&clocks CLK_HSMMC0>, <&clocks CLK_HSMMC0>, - <&clocks SCLK_MMC0>; - status = "disabled"; - }; - - sdhci1: sdhci@eb100000 { - compatible = "samsung,s3c6410-sdhci"; - reg = <0xeb100000 0x100000>; - interrupt-parent = <&vic1>; - interrupts = <27>; - clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.2"; - clocks = <&clocks CLK_HSMMC1>, <&clocks CLK_HSMMC1>, - <&clocks SCLK_MMC1>; - status = "disabled"; - }; - - sdhci2: sdhci@eb200000 { - compatible = "samsung,s3c6410-sdhci"; - reg = <0xeb200000 0x100000>; - interrupt-parent = <&vic1>; - interrupts = <28>; - clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.2"; - clocks = <&clocks CLK_HSMMC2>, <&clocks CLK_HSMMC2>, - <&clocks SCLK_MMC2>; - status = "disabled"; - }; - - sdhci3: sdhci@eb300000 { - compatible = "samsung,s3c6410-sdhci"; - reg = <0xeb300000 0x100000>; - interrupt-parent = <&vic3>; - interrupts = <2>; - clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.3"; - clocks = <&clocks CLK_HSMMC3>, <&clocks CLK_HSMMC3>, - <&clocks SCLK_MMC3>; - status = "disabled"; - }; - - hsotg: hsotg@ec000000 { - compatible = "samsung,s3c6400-hsotg"; - reg = <0xec000000 0x20000>; - interrupt-parent = <&vic1>; - interrupts = <24>; - clocks = <&clocks CLK_USB_OTG>; - clock-names = "otg"; - phy-names = "usb2-phy"; - phys = <&usbphy 0>; - status = "disabled"; - }; - - usbphy: usbphy@ec100000 { - compatible = "samsung,s5pv210-usb2-phy"; - reg = <0xec100000 0x100>; - samsung,pmureg-phandle = <&pmu_syscon>; - clocks = <&clocks CLK_USB_OTG>, <&xusbxti>; - clock-names = "phy", "ref"; - #phy-cells = <1>; - status = "disabled"; - }; - - ehci: ehci@ec200000 { - compatible = "samsung,exynos4210-ehci"; - reg = <0xec200000 0x100>; - interrupts = <23>; - interrupt-parent = <&vic1>; - clocks = <&clocks CLK_USB_HOST>; - clock-names = "usbhost"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - port@0 { - reg = <0>; - phys = <&usbphy 1>; - }; - }; - - ohci: ohci@ec300000 { - compatible = "samsung,exynos4210-ohci"; - reg = <0xec300000 0x100>; - interrupts = <23>; - interrupt-parent = <&vic1>; - clocks = <&clocks CLK_USB_HOST>; - clock-names = "usbhost"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - port@0 { - reg = <0>; - phys = <&usbphy 1>; - }; - }; - - mfc: codec@f1700000 { - compatible = "samsung,mfc-v5"; - reg = <0xf1700000 0x10000>; - interrupt-parent = <&vic2>; - interrupts = <14>; - clocks = <&clocks DOUT_MFC>, <&clocks CLK_MFC>; - clock-names = "sclk_mfc", "mfc"; - }; - - vic0: interrupt-controller@f2000000 { - compatible = "arm,pl192-vic"; - interrupt-controller; - reg = <0xf2000000 0x1000>; - #interrupt-cells = <1>; - }; - - vic1: interrupt-controller@f2100000 { - compatible = "arm,pl192-vic"; - interrupt-controller; - reg = <0xf2100000 0x1000>; - #interrupt-cells = <1>; - }; - - vic2: interrupt-controller@f2200000 { - compatible = "arm,pl192-vic"; - interrupt-controller; - reg = <0xf2200000 0x1000>; - #interrupt-cells = <1>; - }; - - vic3: interrupt-controller@f2300000 { - compatible = "arm,pl192-vic"; - interrupt-controller; - reg = <0xf2300000 0x1000>; - #interrupt-cells = <1>; - }; - - fimd: fimd@f8000000 { - compatible = "samsung,s5pv210-fimd"; - interrupt-parent = <&vic2>; - reg = <0xf8000000 0x20000>; - interrupt-names = "fifo", "vsync", "lcd_sys"; - interrupts = <0>, <1>, <2>; - clocks = <&clocks SCLK_FIMD>, <&clocks CLK_FIMD>; - clock-names = "sclk_fimd", "fimd"; - status = "disabled"; - }; - - dmc0: dmc@f0000000 { - compatible = "samsung,s5pv210-dmc"; - reg = <0xf0000000 0x1000>; - }; - - dmc1: dmc@f1400000 { - compatible = "samsung,s5pv210-dmc"; - reg = <0xf1400000 0x1000>; - }; - - g2d: g2d@fa000000 { - compatible = "samsung,s5pv210-g2d"; - reg = <0xfa000000 0x1000>; - interrupt-parent = <&vic2>; - interrupts = <9>; - clocks = <&clocks DOUT_G2D>, <&clocks CLK_G2D>; - clock-names = "sclk_fimg2d", "fimg2d"; - }; - - mdma1: mdma@fa200000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0xfa200000 0x1000>; - interrupt-parent = <&vic0>; - interrupts = <18>; - clocks = <&clocks CLK_MDMA>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <1>; - }; - - rotator: rotator@fa300000 { - compatible = "samsung,s5pv210-rotator"; - reg = <0xfa300000 0x1000>; - interrupt-parent = <&vic2>; - interrupts = <4>; - clocks = <&clocks CLK_ROTATOR>; - clock-names = "rotator"; - }; - - i2c1: i2c@fab00000 { - compatible = "samsung,s3c2440-i2c"; - reg = <0xfab00000 0x1000>; - interrupt-parent = <&vic2>; - interrupts = <13>; - clocks = <&clocks CLK_I2C1>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_bus>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - camera: camera { - compatible = "samsung,fimc", "simple-bus"; - pinctrl-names = "default"; - pinctrl-0 = <>; - clocks = <&clocks SCLK_CAM0>, <&clocks SCLK_CAM1>; - clock-names = "sclk_cam0", "sclk_cam1"; - #address-cells = <1>; - #size-cells = <1>; - #clock-cells = <1>; - clock-output-names = "cam_a_clkout", "cam_b_clkout"; - ranges; - - csis0: csis@fa600000 { - compatible = "samsung,s5pv210-csis"; - reg = <0xfa600000 0x4000>; - interrupt-parent = <&vic2>; - interrupts = <29>; - clocks = <&clocks CLK_CSIS>, - <&clocks SCLK_CSIS>; - clock-names = "clk_csis", - "sclk_csis"; - bus-width = <4>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - fimc0: fimc@fb200000 { - compatible = "samsung,s5pv210-fimc"; - reg = <0xfb200000 0x1000>; - interrupts = <5>; - interrupt-parent = <&vic2>; - clocks = <&clocks CLK_FIMC0>, - <&clocks SCLK_FIMC0>; - clock-names = "fimc", - "sclk_fimc"; - samsung,pix-limits = <4224 8192 1920 4224>; - samsung,mainscaler-ext; - samsung,cam-if; - }; - - fimc1: fimc@fb300000 { - compatible = "samsung,s5pv210-fimc"; - reg = <0xfb300000 0x1000>; - interrupt-parent = <&vic2>; - interrupts = <6>; - clocks = <&clocks CLK_FIMC1>, - <&clocks SCLK_FIMC1>; - clock-names = "fimc", - "sclk_fimc"; - samsung,pix-limits = <4224 8192 1920 4224>; - samsung,mainscaler-ext; - samsung,cam-if; - }; - - fimc2: fimc@fb400000 { - compatible = "samsung,s5pv210-fimc"; - reg = <0xfb400000 0x1000>; - interrupt-parent = <&vic2>; - interrupts = <7>; - clocks = <&clocks CLK_FIMC2>, - <&clocks SCLK_FIMC2>; - clock-names = "fimc", - "sclk_fimc"; - samsung,pix-limits = <4224 8192 1920 4224>; - samsung,mainscaler-ext; - samsung,lcd-wb; - }; - }; - - jpeg_codec: jpeg-codec@fb600000 { - compatible = "samsung,s5pv210-jpeg"; - reg = <0xfb600000 0x1000>; - interrupt-parent = <&vic2>; - interrupts = <8>; - clocks = <&clocks CLK_JPEG>; - clock-names = "jpeg"; - }; - }; -}; - -#include "s5pv210-pinctrl.dtsi" diff --git a/sys/gnu/dts/arm/sam9x60.dtsi b/sys/gnu/dts/arm/sam9x60.dtsi deleted file mode 100644 index 326b39328b5..00000000000 --- a/sys/gnu/dts/arm/sam9x60.dtsi +++ /dev/null @@ -1,691 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * sam9x60.dtsi - Device Tree Include file for Microchip SAM9X60 SoC - * - * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries - * - * Author: Sandeep Sheriker M - */ - -#include -#include -#include -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - model = "Microchip SAM9X60 SoC"; - compatible = "microchip,sam9x60"; - interrupt-parent = <&aic>; - - aliases { - serial0 = &dbgu; - gpio0 = &pioA; - gpio1 = &pioB; - gpio2 = &pioC; - gpio3 = &pioD; - tcb0 = &tcb0; - tcb1 = &tcb1; - }; - - cpus { - #address-cells = <0>; - #size-cells = <0>; - - cpu { - compatible = "arm,arm926ej-s"; - device_type = "cpu"; - }; - }; - - memory { - device_type = "memory"; - reg = <0x20000000 0x10000000>; - }; - - clocks { - slow_xtal: slow_xtal { - compatible = "fixed-clock"; - #clock-cells = <0>; - }; - - main_xtal: main_xtal { - compatible = "fixed-clock"; - #clock-cells = <0>; - }; - }; - - sram: sram@300000 { - compatible = "mmio-sram"; - reg = <0x00300000 0x100000>; - }; - - ahb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - usb1: ohci@600000 { - compatible = "atmel,at91rm9200-ohci", "usb-ohci"; - reg = <0x00600000 0x100000>; - interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_SYSTEM 6>; - clock-names = "ohci_clk", "hclk", "uhpck"; - status = "disabled"; - }; - - usb2: ehci@700000 { - compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; - reg = <0x00700000 0x100000>; - interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 22>; - clock-names = "usb_clk", "ehci_clk"; - assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>; - assigned-clock-rates = <480000000>; - status = "disabled"; - }; - - ebi: ebi@10000000 { - compatible = "microchip,sam9x60-ebi"; - #address-cells = <2>; - #size-cells = <1>; - atmel,smc = <&smc>; - microchip,sfr = <&sfr>; - reg = <0x10000000 0x60000000>; - ranges = <0x0 0x0 0x10000000 0x10000000 - 0x1 0x0 0x20000000 0x10000000 - 0x2 0x0 0x30000000 0x10000000 - 0x3 0x0 0x40000000 0x10000000 - 0x4 0x0 0x50000000 0x10000000 - 0x5 0x0 0x60000000 0x10000000>; - clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; - status = "disabled"; - - nand_controller: nand-controller { - compatible = "microchip,sam9x60-nand-controller"; - ecc-engine = <&pmecc>; - #address-cells = <2>; - #size-cells = <1>; - ranges; - status = "disabled"; - }; - }; - - sdmmc0: sdio-host@80000000 { - compatible = "microchip,sam9x60-sdhci"; - reg = <0x80000000 0x300>; - interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 12>, <&pmc PMC_TYPE_GCK 12>; - clock-names = "hclock", "multclk"; - assigned-clocks = <&pmc PMC_TYPE_GCK 12>; - assigned-clock-rates = <100000000>; - status = "disabled"; - }; - - sdmmc1: sdio-host@90000000 { - compatible = "microchip,sam9x60-sdhci"; - reg = <0x90000000 0x300>; - interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 26>, <&pmc PMC_TYPE_GCK 26>; - clock-names = "hclock", "multclk"; - assigned-clocks = <&pmc PMC_TYPE_GCK 26>; - assigned-clock-rates = <100000000>; - status = "disabled"; - }; - - apb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - flx4: flexcom@f0000000 { - compatible = "atmel,sama5d2-flexcom"; - reg = <0xf0000000 0x200>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xf0000000 0x800>; - status = "disabled"; - }; - - flx5: flexcom@f0004000 { - compatible = "atmel,sama5d2-flexcom"; - reg = <0xf0004000 0x200>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xf0004000 0x800>; - status = "disabled"; - }; - - dma0: dma-controller@f0008000 { - compatible = "microchip,sam9x60-dma", "atmel,sama5d4-dma"; - reg = <0xf0008000 0x1000>; - interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; - #dma-cells = <1>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; - clock-names = "dma_clk"; - }; - - ssc: ssc@f0010000 { - compatible = "atmel,at91sam9g45-ssc"; - reg = <0xf0010000 0x4000>; - interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(38))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(39))>; - dma-names = "tx", "rx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 28>; - clock-names = "pclk"; - status = "disabled"; - }; - - qspi: spi@f0014000 { - compatible = "microchip,sam9x60-qspi"; - reg = <0xf0014000 0x100>, <0x70000000 0x10000000>; - reg-names = "qspi_base", "qspi_mmap"; - interrupts = <35 IRQ_TYPE_LEVEL_HIGH 7>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(26))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(27))>; - dma-names = "tx", "rx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 35>, <&pmc PMC_TYPE_SYSTEM 19>; - clock-names = "pclk", "qspick"; - atmel,pmc = <&pmc>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2s: i2s@f001c000 { - compatible = "microchip,sam9x60-i2smcc"; - reg = <0xf001c000 0x100>; - interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(36))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(37))>; - dma-names = "tx", "rx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 34>, <&pmc PMC_TYPE_GCK 34>; - clock-names = "pclk", "gclk"; - status = "disabled"; - }; - - flx11: flexcom@f0020000 { - compatible = "atmel,sama5d2-flexcom"; - reg = <0xf0020000 0x200>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 32>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xf0020000 0x800>; - status = "disabled"; - }; - - flx12: flexcom@f0024000 { - compatible = "atmel,sama5d2-flexcom"; - reg = <0xf0024000 0x200>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 33>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xf0024000 0x800>; - status = "disabled"; - }; - - pit64b: timer@f0028000 { - compatible = "microchip,sam9x60-pit64b"; - reg = <0xf0028000 0x100>; - interrupts = <37 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 37>, <&pmc PMC_TYPE_GCK 37>; - clock-names = "pclk", "gclk"; - }; - - sha: sha@f002c000 { - compatible = "atmel,at91sam9g46-sha"; - reg = <0xf002c000 0x100>; - interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(34))>; - dma-names = "tx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 41>; - clock-names = "sha_clk"; - status = "okay"; - }; - - trng: trng@f0030000 { - compatible = "microchip,sam9x60-trng"; - reg = <0xf0030000 0x100>; - interrupts = <38 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; - status = "okay"; - }; - - aes: aes@f0034000 { - compatible = "atmel,at91sam9g46-aes"; - reg = <0xf0034000 0x100>; - interrupts = <39 IRQ_TYPE_LEVEL_HIGH 0>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(32))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(33))>; - dma-names = "tx", "rx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; - clock-names = "aes_clk"; - status = "okay"; - }; - - tdes: tdes@f0038000 { - compatible = "atmel,at91sam9g46-tdes"; - reg = <0xf0038000 0x100>; - interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(31))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(30))>; - dma-names = "tx", "rx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 40>; - clock-names = "tdes_clk"; - status = "okay"; - }; - - classd: classd@f003c000 { - compatible = "atmel,sama5d2-classd"; - reg = <0xf003c000 0x100>; - interrupts = <42 IRQ_TYPE_LEVEL_HIGH 7>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(35))>; - dma-names = "tx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 42>, <&pmc PMC_TYPE_GCK 42>; - clock-names = "pclk", "gclk"; - status = "disabled"; - }; - - can0: can@f8000000 { - compatible = "microchip,sam9x60-can", "atmel,at91sam9x5-can"; - reg = <0xf8000000 0x300>; - interrupts = <29 IRQ_TYPE_LEVEL_HIGH 3>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 29>; - clock-names = "can_clk"; - status = "disabled"; - }; - - can1: can@f8004000 { - compatible = "microchip,sam9x60-can", "atmel,at91sam9x5-can"; - reg = <0xf8004000 0x300>; - interrupts = <30 IRQ_TYPE_LEVEL_HIGH 3>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 30>; - clock-names = "can_clk"; - status = "disabled"; - }; - - tcb0: timer@f8008000 { - compatible = "microchip,sam9x60-tcb", "atmel,at91sam9x5-tcb", "simple-mfd", "syscon"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xf8008000 0x100>; - interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&clk32k 0>; - clock-names = "t0_clk", "slow_clk"; - }; - - tcb1: timer@f800c000 { - compatible = "microchip,sam9x60-tcb", "atmel,at91sam9x5-tcb", "simple-mfd", "syscon"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xf800c000 0x100>; - interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 45>, <&clk32k 0>; - clock-names = "t0_clk", "slow_clk"; - }; - - flx6: flexcom@f8010000 { - compatible = "atmel,sama5d2-flexcom"; - reg = <0xf8010000 0x200>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xf8010000 0x800>; - status = "disabled"; - }; - - flx7: flexcom@f8014000 { - compatible = "atmel,sama5d2-flexcom"; - reg = <0xf8014000 0x200>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xf8014000 0x800>; - status = "disabled"; - }; - - flx8: flexcom@f8018000 { - compatible = "atmel,sama5d2-flexcom"; - reg = <0xf8018000 0x200>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xf8018000 0x800>; - status = "disabled"; - }; - - flx0: flexcom@f801c000 { - compatible = "atmel,sama5d2-flexcom"; - reg = <0xf801c000 0x200>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xf801c000 0x800>; - status = "disabled"; - }; - - flx1: flexcom@f8020000 { - compatible = "atmel,sama5d2-flexcom"; - reg = <0xf8020000 0x200>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xf8020000 0x800>; - status = "disabled"; - }; - - flx2: flexcom@f8024000 { - compatible = "atmel,sama5d2-flexcom"; - reg = <0xf8024000 0x200>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xf8024000 0x800>; - status = "disabled"; - }; - - flx3: flexcom@f8028000 { - compatible = "atmel,sama5d2-flexcom"; - reg = <0xf8028000 0x200>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xf8028000 0x800>; - status = "disabled"; - }; - - macb0: ethernet@f802c000 { - compatible = "cdns,sam9x60-macb", "cdns,macb"; - reg = <0xf802c000 0x1000>; - interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 24>, <&pmc PMC_TYPE_PERIPHERAL 24>; - clock-names = "hclk", "pclk"; - status = "disabled"; - }; - - macb1: ethernet@f8030000 { - compatible = "cdns,sam9x60-macb", "cdns,macb"; - reg = <0xf8030000 0x1000>; - interrupts = <27 IRQ_TYPE_LEVEL_HIGH 3>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 27>, <&pmc PMC_TYPE_PERIPHERAL 27>; - clock-names = "hclk", "pclk"; - status = "disabled"; - }; - - pwm0: pwm@f8034000 { - compatible = "microchip,sam9x60-pwm"; - reg = <0xf8034000 0x300>; - interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 18>; - #pwm-cells = <3>; - status="disabled"; - }; - - hlcdc: hlcdc@f8038000 { - compatible = "microchip,sam9x60-hlcdc"; - reg = <0xf8038000 0x4000>; - interrupts = <25 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 25>, <&pmc PMC_TYPE_GCK 25>, <&clk32k 1>; - clock-names = "periph_clk","sys_clk", "slow_clk"; - assigned-clocks = <&pmc PMC_TYPE_GCK 25>; - assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_MCK>; - status = "disabled"; - - hlcdc-display-controller { - compatible = "atmel,hlcdc-display-controller"; - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - }; - - hlcdc_pwm: hlcdc-pwm { - compatible = "atmel,hlcdc-pwm"; - #pwm-cells = <3>; - }; - }; - - flx9: flexcom@f8040000 { - compatible = "atmel,sama5d2-flexcom"; - reg = <0xf8040000 0x200>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 15>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xf8040000 0x800>; - status = "disabled"; - }; - - flx10: flexcom@f8044000 { - compatible = "atmel,sama5d2-flexcom"; - reg = <0xf8044000 0x200>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 16>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xf8044000 0x800>; - status = "disabled"; - }; - - isi: isi@f8048000 { - compatible = "microchip,sam9x60-isi", "atmel,at91sam9g45-isi"; - reg = <0xf8048000 0x100>; - interrupts = <43 IRQ_TYPE_LEVEL_HIGH 5>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 43>; - clock-names = "isi_clk"; - status = "disabled"; - port { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - adc: adc@f804c000 { - compatible = "microchip,sam9x60-adc", "atmel,sama5d2-adc"; - reg = <0xf804c000 0x100>; - interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; - clock-names = "adc_clk"; - dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(40))>; - dma-names = "rx"; - atmel,min-sample-rate-hz = <200000>; - atmel,max-sample-rate-hz = <20000000>; - atmel,startup-time-ms = <4>; - atmel,trigger-edge-type = ; - #io-channel-cells = <1>; - status = "disabled"; - }; - - sfr: sfr@f8050000 { - compatible = "microchip,sam9x60-sfr", "syscon"; - reg = <0xf8050000 0x100>; - }; - - matrix: matrix@ffffde00 { - compatible = "microchip,sam9x60-matrix", "atmel,at91sam9x5-matrix", "syscon"; - reg = <0xffffde00 0x200>; - }; - - pmecc: ecc-engine@ffffe000 { - compatible = "microchip,sam9x60-pmecc", "atmel,at91sam9g45-pmecc"; - reg = <0xffffe000 0x300>, - <0xffffe600 0x100>; - }; - - mpddrc: mpddrc@ffffe800 { - compatible = "microchip,sam9x60-ddramc", "atmel,sama5d3-ddramc"; - reg = <0xffffe800 0x200>; - clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_CORE PMC_MCK>; - clock-names = "ddrck", "mpddr"; - }; - - smc: smc@ffffea00 { - compatible = "microchip,sam9x60-smc", "atmel,at91sam9260-smc", "syscon"; - reg = <0xffffea00 0x100>; - }; - - aic: interrupt-controller@fffff100 { - compatible = "microchip,sam9x60-aic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0xfffff100 0x100>; - atmel,external-irqs = <31>; - }; - - dbgu: serial@fffff200 { - compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; - reg = <0xfffff200 0x200>; - interrupts = <47 IRQ_TYPE_LEVEL_HIGH 7>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(28))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(29))>; - dma-names = "tx", "rx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 47>; - clock-names = "usart"; - status = "disabled"; - }; - - pinctrl: pinctrl@fffff400 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "microchip,sam9x60-pinctrl", "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus"; - ranges = <0xfffff400 0xfffff400 0x800>; - - pioA: gpio@fffff400 { - compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfffff400 0x200>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; - }; - - pioB: gpio@fffff600 { - compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfffff600 0x200>; - interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - #gpio-lines = <26>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 3>; - }; - - pioC: gpio@fffff800 { - compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfffff800 0x200>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 4>; - }; - - pioD: gpio@fffffa00 { - compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfffffa00 0x200>; - interrupts = <44 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - #gpio-lines = <22>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 44>; - }; - }; - - pmc: pmc@fffffc00 { - compatible = "microchip,sam9x60-pmc", "syscon"; - reg = <0xfffffc00 0x200>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - #clock-cells = <2>; - clocks = <&clk32k 1>, <&clk32k 0>, <&main_xtal>; - clock-names = "td_slck", "md_slck", "main_xtal"; - }; - - reset_controller: rstc@fffffe00 { - compatible = "microchip,sam9x60-rstc"; - reg = <0xfffffe00 0x10>; - clocks = <&clk32k 0>; - }; - - shutdown_controller: shdwc@fffffe10 { - compatible = "microchip,sam9x60-shdwc"; - reg = <0xfffffe10 0x10>; - clocks = <&clk32k 0>; - #address-cells = <1>; - #size-cells = <0>; - atmel,wakeup-rtc-timer; - atmel,wakeup-rtt-timer; - status = "disabled"; - }; - - pit: timer@fffffe40 { - compatible = "atmel,at91sam9260-pit"; - reg = <0xfffffe40 0x10>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; - }; - - clk32k: sckc@fffffe50 { - compatible = "microchip,sam9x60-sckc"; - reg = <0xfffffe50 0x4>; - clocks = <&slow_xtal>; - #clock-cells = <1>; - }; - - gpbr: syscon@fffffe60 { - compatible = "microchip,sam9x60-gpbr", "atmel,at91sam9260-gpbr", "syscon"; - reg = <0xfffffe60 0x10>; - }; - - rtc: rtc@fffffea8 { - compatible = "microchip,sam9x60-rtc", "atmel,at91sam9x5-rtc"; - reg = <0xfffffea8 0x100>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&clk32k 0>; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/sama5d2-pinfunc.h b/sys/gnu/dts/arm/sama5d2-pinfunc.h deleted file mode 100644 index 28a2e45752f..00000000000 --- a/sys/gnu/dts/arm/sama5d2-pinfunc.h +++ /dev/null @@ -1,881 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#define PINMUX_PIN(no, func, ioset) \ -(((no) & 0xffff) | (((func) & 0xf) << 16) | (((ioset) & 0xff) << 20)) - -#define PIN_PA0 0 -#define PIN_PA0__GPIO PINMUX_PIN(PIN_PA0, 0, 0) -#define PIN_PA0__SDMMC0_CK PINMUX_PIN(PIN_PA0, 1, 1) -#define PIN_PA0__QSPI0_SCK PINMUX_PIN(PIN_PA0, 2, 1) -#define PIN_PA0__D0 PINMUX_PIN(PIN_PA0, 6, 2) -#define PIN_PA1 1 -#define PIN_PA1__GPIO PINMUX_PIN(PIN_PA1, 0, 0) -#define PIN_PA1__SDMMC0_CMD PINMUX_PIN(PIN_PA1, 1, 1) -#define PIN_PA1__QSPI0_CS PINMUX_PIN(PIN_PA1, 2, 1) -#define PIN_PA1__D1 PINMUX_PIN(PIN_PA1, 6, 2) -#define PIN_PA2 2 -#define PIN_PA2__GPIO PINMUX_PIN(PIN_PA2, 0, 0) -#define PIN_PA2__SDMMC0_DAT0 PINMUX_PIN(PIN_PA2, 1, 1) -#define PIN_PA2__QSPI0_IO0 PINMUX_PIN(PIN_PA2, 2, 1) -#define PIN_PA2__D2 PINMUX_PIN(PIN_PA2, 6, 2) -#define PIN_PA3 3 -#define PIN_PA3__GPIO PINMUX_PIN(PIN_PA3, 0, 0) -#define PIN_PA3__SDMMC0_DAT1 PINMUX_PIN(PIN_PA3, 1, 1) -#define PIN_PA3__QSPI0_IO1 PINMUX_PIN(PIN_PA3, 2, 1) -#define PIN_PA3__D3 PINMUX_PIN(PIN_PA3, 6, 2) -#define PIN_PA4 4 -#define PIN_PA4__GPIO PINMUX_PIN(PIN_PA4, 0, 0) -#define PIN_PA4__SDMMC0_DAT2 PINMUX_PIN(PIN_PA4, 1, 1) -#define PIN_PA4__QSPI0_IO2 PINMUX_PIN(PIN_PA4, 2, 1) -#define PIN_PA4__D4 PINMUX_PIN(PIN_PA4, 6, 2) -#define PIN_PA5 5 -#define PIN_PA5__GPIO PINMUX_PIN(PIN_PA5, 0, 0) -#define PIN_PA5__SDMMC0_DAT3 PINMUX_PIN(PIN_PA5, 1, 1) -#define PIN_PA5__QSPI0_IO3 PINMUX_PIN(PIN_PA5, 2, 1) -#define PIN_PA5__D5 PINMUX_PIN(PIN_PA5, 6, 2) -#define PIN_PA6 6 -#define PIN_PA6__GPIO PINMUX_PIN(PIN_PA6, 0, 0) -#define PIN_PA6__SDMMC0_DAT4 PINMUX_PIN(PIN_PA6, 1, 1) -#define PIN_PA6__QSPI1_SCK PINMUX_PIN(PIN_PA6, 2, 1) -#define PIN_PA6__TIOA5 PINMUX_PIN(PIN_PA6, 4, 1) -#define PIN_PA6__FLEXCOM2_IO0 PINMUX_PIN(PIN_PA6, 5, 1) -#define PIN_PA6__D6 PINMUX_PIN(PIN_PA6, 6, 2) -#define PIN_PA7 7 -#define PIN_PA7__GPIO PINMUX_PIN(PIN_PA7, 0, 0) -#define PIN_PA7__SDMMC0_DAT5 PINMUX_PIN(PIN_PA7, 1, 1) -#define PIN_PA7__QSPI1_IO0 PINMUX_PIN(PIN_PA7, 2, 1) -#define PIN_PA7__TIOB5 PINMUX_PIN(PIN_PA7, 4, 1) -#define PIN_PA7__FLEXCOM2_IO1 PINMUX_PIN(PIN_PA7, 5, 1) -#define PIN_PA7__D7 PINMUX_PIN(PIN_PA7, 6, 2) -#define PIN_PA8 8 -#define PIN_PA8__GPIO PINMUX_PIN(PIN_PA8, 0, 0) -#define PIN_PA8__SDMMC0_DAT6 PINMUX_PIN(PIN_PA8, 1, 1) -#define PIN_PA8__QSPI1_IO1 PINMUX_PIN(PIN_PA8, 2, 1) -#define PIN_PA8__TCLK5 PINMUX_PIN(PIN_PA8, 4, 1) -#define PIN_PA8__FLEXCOM2_IO2 PINMUX_PIN(PIN_PA8, 5, 1) -#define PIN_PA8__NWE_NANDWE PINMUX_PIN(PIN_PA8, 6, 2) -#define PIN_PA9 9 -#define PIN_PA9__GPIO PINMUX_PIN(PIN_PA9, 0, 0) -#define PIN_PA9__SDMMC0_DAT7 PINMUX_PIN(PIN_PA9, 1, 1) -#define PIN_PA9__QSPI1_IO2 PINMUX_PIN(PIN_PA9, 2, 1) -#define PIN_PA9__TIOA4 PINMUX_PIN(PIN_PA9, 4, 1) -#define PIN_PA9__FLEXCOM2_IO3 PINMUX_PIN(PIN_PA9, 5, 1) -#define PIN_PA9__NCS3 PINMUX_PIN(PIN_PA9, 6, 2) -#define PIN_PA10 10 -#define PIN_PA10__GPIO PINMUX_PIN(PIN_PA10, 0, 0) -#define PIN_PA10__SDMMC0_RSTN PINMUX_PIN(PIN_PA10, 1, 1) -#define PIN_PA10__QSPI1_IO3 PINMUX_PIN(PIN_PA10, 2, 1) -#define PIN_PA10__TIOB4 PINMUX_PIN(PIN_PA10, 4, 1) -#define PIN_PA10__FLEXCOM2_IO4 PINMUX_PIN(PIN_PA10, 5, 1) -#define PIN_PA10__A21_NANDALE PINMUX_PIN(PIN_PA10, 6, 2) -#define PIN_PA11 11 -#define PIN_PA11__GPIO PINMUX_PIN(PIN_PA11, 0, 0) -#define PIN_PA11__SDMMC0_VDDSEL PINMUX_PIN(PIN_PA11, 1, 1) -#define PIN_PA11__QSPI1_CS PINMUX_PIN(PIN_PA11, 2, 1) -#define PIN_PA11__TCLK4 PINMUX_PIN(PIN_PA11, 4, 1) -#define PIN_PA11__A22_NANDCLE PINMUX_PIN(PIN_PA11, 6, 2) -#define PIN_PA12 12 -#define PIN_PA12__GPIO PINMUX_PIN(PIN_PA12, 0, 0) -#define PIN_PA12__SDMMC0_WP PINMUX_PIN(PIN_PA12, 1, 1) -#define PIN_PA12__IRQ PINMUX_PIN(PIN_PA12, 2, 1) -#define PIN_PA12__NRD_NANDOE PINMUX_PIN(PIN_PA12, 6, 2) -#define PIN_PA13 13 -#define PIN_PA13__GPIO PINMUX_PIN(PIN_PA13, 0, 0) -#define PIN_PA13__SDMMC0_CD PINMUX_PIN(PIN_PA13, 1, 1) -#define PIN_PA13__FLEXCOM3_IO1 PINMUX_PIN(PIN_PA13, 5, 1) -#define PIN_PA13__D8 PINMUX_PIN(PIN_PA13, 6, 2) -#define PIN_PA14 14 -#define PIN_PA14__GPIO PINMUX_PIN(PIN_PA14, 0, 0) -#define PIN_PA14__SPI0_SPCK PINMUX_PIN(PIN_PA14, 1, 1) -#define PIN_PA14__TK1 PINMUX_PIN(PIN_PA14, 2, 1) -#define PIN_PA14__QSPI0_SCK PINMUX_PIN(PIN_PA14, 3, 2) -#define PIN_PA14__I2SC1_MCK PINMUX_PIN(PIN_PA14, 4, 2) -#define PIN_PA14__FLEXCOM3_IO2 PINMUX_PIN(PIN_PA14, 5, 1) -#define PIN_PA14__D9 PINMUX_PIN(PIN_PA14, 6, 2) -#define PIN_PA15 15 -#define PIN_PA15__GPIO PINMUX_PIN(PIN_PA15, 0, 0) -#define PIN_PA15__SPI0_MOSI PINMUX_PIN(PIN_PA15, 1, 1) -#define PIN_PA15__TF1 PINMUX_PIN(PIN_PA15, 2, 1) -#define PIN_PA15__QSPI0_CS PINMUX_PIN(PIN_PA15, 3, 2) -#define PIN_PA15__I2SC1_CK PINMUX_PIN(PIN_PA15, 4, 2) -#define PIN_PA15__FLEXCOM3_IO0 PINMUX_PIN(PIN_PA15, 5, 1) -#define PIN_PA15__D10 PINMUX_PIN(PIN_PA15, 6, 2) -#define PIN_PA16 16 -#define PIN_PA16__GPIO PINMUX_PIN(PIN_PA16, 0, 0) -#define PIN_PA16__SPI0_MISO PINMUX_PIN(PIN_PA16, 1, 1) -#define PIN_PA16__TD1 PINMUX_PIN(PIN_PA16, 2, 1) -#define PIN_PA16__QSPI0_IO0 PINMUX_PIN(PIN_PA16, 3, 2) -#define PIN_PA16__I2SC1_WS PINMUX_PIN(PIN_PA16, 4, 2) -#define PIN_PA16__FLEXCOM3_IO3 PINMUX_PIN(PIN_PA16, 5, 1) -#define PIN_PA16__D11 PINMUX_PIN(PIN_PA16, 6, 2) -#define PIN_PA17 17 -#define PIN_PA17__GPIO PINMUX_PIN(PIN_PA17, 0, 0) -#define PIN_PA17__SPI0_NPCS0 PINMUX_PIN(PIN_PA17, 1, 1) -#define PIN_PA17__RD1 PINMUX_PIN(PIN_PA17, 2, 1) -#define PIN_PA17__QSPI0_IO1 PINMUX_PIN(PIN_PA17, 3, 2) -#define PIN_PA17__I2SC1_DI0 PINMUX_PIN(PIN_PA17, 4, 2) -#define PIN_PA17__FLEXCOM3_IO4 PINMUX_PIN(PIN_PA17, 5, 1) -#define PIN_PA17__D12 PINMUX_PIN(PIN_PA17, 6, 2) -#define PIN_PA18 18 -#define PIN_PA18__GPIO PINMUX_PIN(PIN_PA18, 0, 0) -#define PIN_PA18__SPI0_NPCS1 PINMUX_PIN(PIN_PA18, 1, 1) -#define PIN_PA18__RK1 PINMUX_PIN(PIN_PA18, 2, 1) -#define PIN_PA18__QSPI0_IO2 PINMUX_PIN(PIN_PA18, 3, 2) -#define PIN_PA18__I2SC1_DO0 PINMUX_PIN(PIN_PA18, 4, 2) -#define PIN_PA18__SDMMC1_DAT0 PINMUX_PIN(PIN_PA18, 5, 1) -#define PIN_PA18__D13 PINMUX_PIN(PIN_PA18, 6, 2) -#define PIN_PA19 19 -#define PIN_PA19__GPIO PINMUX_PIN(PIN_PA19, 0, 0) -#define PIN_PA19__SPI0_NPCS2 PINMUX_PIN(PIN_PA19, 1, 1) -#define PIN_PA19__RF1 PINMUX_PIN(PIN_PA19, 2, 1) -#define PIN_PA19__QSPI0_IO3 PINMUX_PIN(PIN_PA19, 3, 2) -#define PIN_PA19__TIOA0 PINMUX_PIN(PIN_PA19, 4, 1) -#define PIN_PA19__SDMMC1_DAT1 PINMUX_PIN(PIN_PA19, 5, 1) -#define PIN_PA19__D14 PINMUX_PIN(PIN_PA19, 6, 2) -#define PIN_PA20 20 -#define PIN_PA20__GPIO PINMUX_PIN(PIN_PA20, 0, 0) -#define PIN_PA20__SPI0_NPCS3 PINMUX_PIN(PIN_PA20, 1, 1) -#define PIN_PA20__TIOB0 PINMUX_PIN(PIN_PA20, 4, 1) -#define PIN_PA20__SDMMC1_DAT2 PINMUX_PIN(PIN_PA20, 5, 1) -#define PIN_PA20__D15 PINMUX_PIN(PIN_PA20, 6, 2) -#define PIN_PA21 21 -#define PIN_PA21__GPIO PINMUX_PIN(PIN_PA21, 0, 0) -#define PIN_PA21__IRQ PINMUX_PIN(PIN_PA21, 1, 2) -#define PIN_PA21__PCK2 PINMUX_PIN(PIN_PA21, 2, 3) -#define PIN_PA21__TCLK0 PINMUX_PIN(PIN_PA21, 4, 1) -#define PIN_PA21__SDMMC1_DAT3 PINMUX_PIN(PIN_PA21, 5, 1) -#define PIN_PA21__NANDRDY PINMUX_PIN(PIN_PA21, 6, 2) -#define PIN_PA22 22 -#define PIN_PA22__GPIO PINMUX_PIN(PIN_PA22, 0, 0) -#define PIN_PA22__FLEXCOM1_IO2 PINMUX_PIN(PIN_PA22, 1, 1) -#define PIN_PA22__D0 PINMUX_PIN(PIN_PA22, 2, 1) -#define PIN_PA22__TCK PINMUX_PIN(PIN_PA22, 3, 4) -#define PIN_PA22__SPI1_SPCK PINMUX_PIN(PIN_PA22, 4, 2) -#define PIN_PA22__SDMMC1_CK PINMUX_PIN(PIN_PA22, 5, 1) -#define PIN_PA22__QSPI0_SCK PINMUX_PIN(PIN_PA22, 6, 3) -#define PIN_PA23 23 -#define PIN_PA23__GPIO PINMUX_PIN(PIN_PA23, 0, 0) -#define PIN_PA23__FLEXCOM1_IO1 PINMUX_PIN(PIN_PA23, 1, 1) -#define PIN_PA23__D1 PINMUX_PIN(PIN_PA23, 2, 1) -#define PIN_PA23__TDI PINMUX_PIN(PIN_PA23, 3, 4) -#define PIN_PA23__SPI1_MOSI PINMUX_PIN(PIN_PA23, 4, 2) -#define PIN_PA23__QSPI0_CS PINMUX_PIN(PIN_PA23, 6, 3) -#define PIN_PA24 24 -#define PIN_PA24__GPIO PINMUX_PIN(PIN_PA24, 0, 0) -#define PIN_PA24__FLEXCOM1_IO0 PINMUX_PIN(PIN_PA24, 1, 1) -#define PIN_PA24__D2 PINMUX_PIN(PIN_PA24, 2, 1) -#define PIN_PA24__TDO PINMUX_PIN(PIN_PA24, 3, 4) -#define PIN_PA24__SPI1_MISO PINMUX_PIN(PIN_PA24, 4, 2) -#define PIN_PA24__QSPI0_IO0 PINMUX_PIN(PIN_PA24, 6, 3) -#define PIN_PA25 25 -#define PIN_PA25__GPIO PINMUX_PIN(PIN_PA25, 0, 0) -#define PIN_PA25__FLEXCOM1_IO3 PINMUX_PIN(PIN_PA25, 1, 1) -#define PIN_PA25__D3 PINMUX_PIN(PIN_PA25, 2, 1) -#define PIN_PA25__TMS PINMUX_PIN(PIN_PA25, 3, 4) -#define PIN_PA25__SPI1_NPCS0 PINMUX_PIN(PIN_PA25, 4, 2) -#define PIN_PA25__QSPI0_IO1 PINMUX_PIN(PIN_PA25, 6, 3) -#define PIN_PA26 26 -#define PIN_PA26__GPIO PINMUX_PIN(PIN_PA26, 0, 0) -#define PIN_PA26__FLEXCOM1_IO4 PINMUX_PIN(PIN_PA26, 1, 1) -#define PIN_PA26__D4 PINMUX_PIN(PIN_PA26, 2, 1) -#define PIN_PA26__NTRST PINMUX_PIN(PIN_PA26, 3, 4) -#define PIN_PA26__SPI1_NPCS1 PINMUX_PIN(PIN_PA26, 4, 2) -#define PIN_PA26__QSPI0_IO2 PINMUX_PIN(PIN_PA26, 6, 3) -#define PIN_PA27 27 -#define PIN_PA27__GPIO PINMUX_PIN(PIN_PA27, 0, 0) -#define PIN_PA27__TIOA1 PINMUX_PIN(PIN_PA27, 1, 2) -#define PIN_PA27__D5 PINMUX_PIN(PIN_PA27, 2, 1) -#define PIN_PA27__SPI0_NPCS2 PINMUX_PIN(PIN_PA27, 3, 2) -#define PIN_PA27__SPI1_NPCS2 PINMUX_PIN(PIN_PA27, 4, 2) -#define PIN_PA27__SDMMC1_RSTN PINMUX_PIN(PIN_PA27, 5, 1) -#define PIN_PA27__QSPI0_IO3 PINMUX_PIN(PIN_PA27, 6, 3) -#define PIN_PA28 28 -#define PIN_PA28__GPIO PINMUX_PIN(PIN_PA28, 0, 0) -#define PIN_PA28__TIOB1 PINMUX_PIN(PIN_PA28, 1, 2) -#define PIN_PA28__D6 PINMUX_PIN(PIN_PA28, 2, 1) -#define PIN_PA28__SPI0_NPCS3 PINMUX_PIN(PIN_PA28, 3, 2) -#define PIN_PA28__SPI1_NPCS3 PINMUX_PIN(PIN_PA28, 4, 2) -#define PIN_PA28__SDMMC1_CMD PINMUX_PIN(PIN_PA28, 5, 1) -#define PIN_PA28__CLASSD_L0 PINMUX_PIN(PIN_PA28, 6, 1) -#define PIN_PA29 29 -#define PIN_PA29__GPIO PINMUX_PIN(PIN_PA29, 0, 0) -#define PIN_PA29__TCLK1 PINMUX_PIN(PIN_PA29, 1, 2) -#define PIN_PA29__D7 PINMUX_PIN(PIN_PA29, 2, 1) -#define PIN_PA29__SPI0_NPCS1 PINMUX_PIN(PIN_PA29, 3, 2) -#define PIN_PA29__SDMMC1_WP PINMUX_PIN(PIN_PA29, 5, 1) -#define PIN_PA29__CLASSD_L1 PINMUX_PIN(PIN_PA29, 6, 1) -#define PIN_PA30 30 -#define PIN_PA30__GPIO PINMUX_PIN(PIN_PA30, 0, 0) -#define PIN_PA30__NWE_NANDWE PINMUX_PIN(PIN_PA30, 2, 1) -#define PIN_PA30__SPI0_NPCS0 PINMUX_PIN(PIN_PA30, 3, 2) -#define PIN_PA30__PWMH0 PINMUX_PIN(PIN_PA30, 4, 1) -#define PIN_PA30__SDMMC1_CD PINMUX_PIN(PIN_PA30, 5, 1) -#define PIN_PA30__CLASSD_L2 PINMUX_PIN(PIN_PA30, 6, 1) -#define PIN_PA31 31 -#define PIN_PA31__GPIO PINMUX_PIN(PIN_PA31, 0, 0) -#define PIN_PA31__NCS3 PINMUX_PIN(PIN_PA31, 2, 1) -#define PIN_PA31__SPI0_MISO PINMUX_PIN(PIN_PA31, 3, 2) -#define PIN_PA31__PWML0 PINMUX_PIN(PIN_PA31, 4, 1) -#define PIN_PA31__CLASSD_L3 PINMUX_PIN(PIN_PA31, 6, 1) -#define PIN_PB0 32 -#define PIN_PB0__GPIO PINMUX_PIN(PIN_PB0, 0, 0) -#define PIN_PB0__A21_NANDALE PINMUX_PIN(PIN_PB0, 2, 1) -#define PIN_PB0__SPI0_MOSI PINMUX_PIN(PIN_PB0, 3, 2) -#define PIN_PB0__PWMH1 PINMUX_PIN(PIN_PB0, 4, 1) -#define PIN_PB1 33 -#define PIN_PB1__GPIO PINMUX_PIN(PIN_PB1, 0, 0) -#define PIN_PB1__A22_NANDCLE PINMUX_PIN(PIN_PB1, 2, 1) -#define PIN_PB1__SPI0_SPCK PINMUX_PIN(PIN_PB1, 3, 2) -#define PIN_PB1__PWML1 PINMUX_PIN(PIN_PB1, 4, 1) -#define PIN_PB1__CLASSD_R0 PINMUX_PIN(PIN_PB1, 6, 1) -#define PIN_PB2 34 -#define PIN_PB2__GPIO PINMUX_PIN(PIN_PB2, 0, 0) -#define PIN_PB2__NRD_NANDOE PINMUX_PIN(PIN_PB2, 2, 1) -#define PIN_PB2__PWMFI0 PINMUX_PIN(PIN_PB2, 4, 1) -#define PIN_PB2__CLASSD_R1 PINMUX_PIN(PIN_PB2, 6, 1) -#define PIN_PB3 35 -#define PIN_PB3__GPIO PINMUX_PIN(PIN_PB3, 0, 0) -#define PIN_PB3__URXD4 PINMUX_PIN(PIN_PB3, 1, 1) -#define PIN_PB3__D8 PINMUX_PIN(PIN_PB3, 2, 1) -#define PIN_PB3__IRQ PINMUX_PIN(PIN_PB3, 3, 3) -#define PIN_PB3__PWMEXTRG0 PINMUX_PIN(PIN_PB3, 4, 1) -#define PIN_PB3__CLASSD_R2 PINMUX_PIN(PIN_PB3, 6, 1) -#define PIN_PB4 36 -#define PIN_PB4__GPIO PINMUX_PIN(PIN_PB4, 0, 0) -#define PIN_PB4__UTXD4 PINMUX_PIN(PIN_PB4, 1, 1) -#define PIN_PB4__D9 PINMUX_PIN(PIN_PB4, 2, 1) -#define PIN_PB4__FIQ PINMUX_PIN(PIN_PB4, 3, 4) -#define PIN_PB4__CLASSD_R3 PINMUX_PIN(PIN_PB4, 6, 1) -#define PIN_PB5 37 -#define PIN_PB5__GPIO PINMUX_PIN(PIN_PB5, 0, 0) -#define PIN_PB5__TCLK2 PINMUX_PIN(PIN_PB5, 1, 1) -#define PIN_PB5__D10 PINMUX_PIN(PIN_PB5, 2, 1) -#define PIN_PB5__PWMH2 PINMUX_PIN(PIN_PB5, 3, 1) -#define PIN_PB5__QSPI1_SCK PINMUX_PIN(PIN_PB5, 4, 2) -#define PIN_PB5__GTSUCOMP PINMUX_PIN(PIN_PB5, 6, 3) -#define PIN_PB6 38 -#define PIN_PB6__GPIO PINMUX_PIN(PIN_PB6, 0, 0) -#define PIN_PB6__TIOA2 PINMUX_PIN(PIN_PB6, 1, 1) -#define PIN_PB6__D11 PINMUX_PIN(PIN_PB6, 2, 1) -#define PIN_PB6__PWML2 PINMUX_PIN(PIN_PB6, 3, 1) -#define PIN_PB6__QSPI1_CS PINMUX_PIN(PIN_PB6, 4, 2) -#define PIN_PB6__GTXER PINMUX_PIN(PIN_PB6, 6, 3) -#define PIN_PB7 39 -#define PIN_PB7__GPIO PINMUX_PIN(PIN_PB7, 0, 0) -#define PIN_PB7__TIOB2 PINMUX_PIN(PIN_PB7, 1, 1) -#define PIN_PB7__D12 PINMUX_PIN(PIN_PB7, 2, 1) -#define PIN_PB7__PWMH3 PINMUX_PIN(PIN_PB7, 3, 1) -#define PIN_PB7__QSPI1_IO0 PINMUX_PIN(PIN_PB7, 4, 2) -#define PIN_PB7__GRXCK PINMUX_PIN(PIN_PB7, 6, 3) -#define PIN_PB8 40 -#define PIN_PB8__GPIO PINMUX_PIN(PIN_PB8, 0, 0) -#define PIN_PB8__TCLK3 PINMUX_PIN(PIN_PB8, 1, 1) -#define PIN_PB8__D13 PINMUX_PIN(PIN_PB8, 2, 1) -#define PIN_PB8__PWML3 PINMUX_PIN(PIN_PB8, 3, 1) -#define PIN_PB8__QSPI1_IO1 PINMUX_PIN(PIN_PB8, 4, 2) -#define PIN_PB8__GCRS PINMUX_PIN(PIN_PB8, 6, 3) -#define PIN_PB9 41 -#define PIN_PB9__GPIO PINMUX_PIN(PIN_PB9, 0, 0) -#define PIN_PB9__TIOA3 PINMUX_PIN(PIN_PB9, 1, 1) -#define PIN_PB9__D14 PINMUX_PIN(PIN_PB9, 2, 1) -#define PIN_PB9__PWMFI1 PINMUX_PIN(PIN_PB9, 3, 1) -#define PIN_PB9__QSPI1_IO2 PINMUX_PIN(PIN_PB9, 4, 2) -#define PIN_PB9__GCOL PINMUX_PIN(PIN_PB9, 6, 3) -#define PIN_PB10 42 -#define PIN_PB10__GPIO PINMUX_PIN(PIN_PB10, 0, 0) -#define PIN_PB10__TIOB3 PINMUX_PIN(PIN_PB10, 1, 1) -#define PIN_PB10__D15 PINMUX_PIN(PIN_PB10, 2, 1) -#define PIN_PB10__PWMEXTRG1 PINMUX_PIN(PIN_PB10, 3, 1) -#define PIN_PB10__QSPI1_IO3 PINMUX_PIN(PIN_PB10, 4, 2) -#define PIN_PB10__GRX2 PINMUX_PIN(PIN_PB10, 6, 3) -#define PIN_PB11 43 -#define PIN_PB11__GPIO PINMUX_PIN(PIN_PB11, 0, 0) -#define PIN_PB11__LCDDAT0 PINMUX_PIN(PIN_PB11, 1, 1) -#define PIN_PB11__A0_NBS0 PINMUX_PIN(PIN_PB11, 2, 1) -#define PIN_PB11__URXD3 PINMUX_PIN(PIN_PB11, 3, 3) -#define PIN_PB11__PDMIC_DAT PINMUX_PIN(PIN_PB11, 4, 2) -#define PIN_PB11__GRX3 PINMUX_PIN(PIN_PB11, 6, 3) -#define PIN_PB12 44 -#define PIN_PB12__GPIO PINMUX_PIN(PIN_PB12, 0, 0) -#define PIN_PB12__LCDDAT1 PINMUX_PIN(PIN_PB12, 1, 1) -#define PIN_PB12__A1 PINMUX_PIN(PIN_PB12, 2, 1) -#define PIN_PB12__UTXD3 PINMUX_PIN(PIN_PB12, 3, 3) -#define PIN_PB12__PDMIC_CLK PINMUX_PIN(PIN_PB12, 4, 2) -#define PIN_PB12__GTX2 PINMUX_PIN(PIN_PB12, 6, 3) -#define PIN_PB13 45 -#define PIN_PB13__GPIO PINMUX_PIN(PIN_PB13, 0, 0) -#define PIN_PB13__LCDDAT2 PINMUX_PIN(PIN_PB13, 1, 1) -#define PIN_PB13__A2 PINMUX_PIN(PIN_PB13, 2, 1) -#define PIN_PB13__PCK1 PINMUX_PIN(PIN_PB13, 3, 3) -#define PIN_PB13__GTX3 PINMUX_PIN(PIN_PB13, 6, 3) -#define PIN_PB14 46 -#define PIN_PB14__GPIO PINMUX_PIN(PIN_PB14, 0, 0) -#define PIN_PB14__LCDDAT3 PINMUX_PIN(PIN_PB14, 1, 1) -#define PIN_PB14__A3 PINMUX_PIN(PIN_PB14, 2, 1) -#define PIN_PB14__TK1 PINMUX_PIN(PIN_PB14, 3, 2) -#define PIN_PB14__I2SC1_MCK PINMUX_PIN(PIN_PB14, 4, 1) -#define PIN_PB14__QSPI1_SCK PINMUX_PIN(PIN_PB14, 5, 3) -#define PIN_PB14__GTXCK PINMUX_PIN(PIN_PB14, 6, 3) -#define PIN_PB15 47 -#define PIN_PB15__GPIO PINMUX_PIN(PIN_PB15, 0, 0) -#define PIN_PB15__LCDDAT4 PINMUX_PIN(PIN_PB15, 1, 1) -#define PIN_PB15__A4 PINMUX_PIN(PIN_PB15, 2, 1) -#define PIN_PB15__TF1 PINMUX_PIN(PIN_PB15, 3, 2) -#define PIN_PB15__I2SC1_CK PINMUX_PIN(PIN_PB15, 4, 1) -#define PIN_PB15__QSPI1_CS PINMUX_PIN(PIN_PB15, 5, 3) -#define PIN_PB15__GTXEN PINMUX_PIN(PIN_PB15, 6, 3) -#define PIN_PB16 48 -#define PIN_PB16__GPIO PINMUX_PIN(PIN_PB16, 0, 0) -#define PIN_PB16__LCDDAT5 PINMUX_PIN(PIN_PB16, 1, 1) -#define PIN_PB16__A5 PINMUX_PIN(PIN_PB16, 2, 1) -#define PIN_PB16__TD1 PINMUX_PIN(PIN_PB16, 3, 2) -#define PIN_PB16__I2SC1_WS PINMUX_PIN(PIN_PB16, 4, 1) -#define PIN_PB16__QSPI1_IO0 PINMUX_PIN(PIN_PB16, 5, 3) -#define PIN_PB16__GRXDV PINMUX_PIN(PIN_PB16, 6, 3) -#define PIN_PB17 49 -#define PIN_PB17__GPIO PINMUX_PIN(PIN_PB17, 0, 0) -#define PIN_PB17__LCDDAT6 PINMUX_PIN(PIN_PB17, 1, 1) -#define PIN_PB17__A6 PINMUX_PIN(PIN_PB17, 2, 1) -#define PIN_PB17__RD1 PINMUX_PIN(PIN_PB17, 3, 2) -#define PIN_PB17__I2SC1_DI0 PINMUX_PIN(PIN_PB17, 4, 1) -#define PIN_PB17__QSPI1_IO1 PINMUX_PIN(PIN_PB17, 5, 3) -#define PIN_PB17__GRXER PINMUX_PIN(PIN_PB17, 6, 3) -#define PIN_PB18 50 -#define PIN_PB18__GPIO PINMUX_PIN(PIN_PB18, 0, 0) -#define PIN_PB18__LCDDAT7 PINMUX_PIN(PIN_PB18, 1, 1) -#define PIN_PB18__A7 PINMUX_PIN(PIN_PB18, 2, 1) -#define PIN_PB18__RK1 PINMUX_PIN(PIN_PB18, 3, 2) -#define PIN_PB18__I2SC1_DO0 PINMUX_PIN(PIN_PB18, 4, 1) -#define PIN_PB18__QSPI1_IO2 PINMUX_PIN(PIN_PB18, 5, 3) -#define PIN_PB18__GRX0 PINMUX_PIN(PIN_PB18, 6, 3) -#define PIN_PB19 51 -#define PIN_PB19__GPIO PINMUX_PIN(PIN_PB19, 0, 0) -#define PIN_PB19__LCDDAT8 PINMUX_PIN(PIN_PB19, 1, 1) -#define PIN_PB19__A8 PINMUX_PIN(PIN_PB19, 2, 1) -#define PIN_PB19__RF1 PINMUX_PIN(PIN_PB19, 3, 2) -#define PIN_PB19__TIOA3 PINMUX_PIN(PIN_PB19, 4, 2) -#define PIN_PB19__QSPI1_IO3 PINMUX_PIN(PIN_PB19, 5, 3) -#define PIN_PB19__GRX1 PINMUX_PIN(PIN_PB19, 6, 3) -#define PIN_PB20 52 -#define PIN_PB20__GPIO PINMUX_PIN(PIN_PB20, 0, 0) -#define PIN_PB20__LCDDAT9 PINMUX_PIN(PIN_PB20, 1, 1) -#define PIN_PB20__A9 PINMUX_PIN(PIN_PB20, 2, 1) -#define PIN_PB20__TK0 PINMUX_PIN(PIN_PB20, 3, 1) -#define PIN_PB20__TIOB3 PINMUX_PIN(PIN_PB20, 4, 2) -#define PIN_PB20__PCK1 PINMUX_PIN(PIN_PB20, 5, 4) -#define PIN_PB20__GTX0 PINMUX_PIN(PIN_PB20, 6, 3) -#define PIN_PB21 53 -#define PIN_PB21__GPIO PINMUX_PIN(PIN_PB21, 0, 0) -#define PIN_PB21__LCDDAT10 PINMUX_PIN(PIN_PB21, 1, 1) -#define PIN_PB21__A10 PINMUX_PIN(PIN_PB21, 2, 1) -#define PIN_PB21__TF0 PINMUX_PIN(PIN_PB21, 3, 1) -#define PIN_PB21__TCLK3 PINMUX_PIN(PIN_PB21, 4, 2) -#define PIN_PB21__FLEXCOM3_IO2 PINMUX_PIN(PIN_PB21, 5, 3) -#define PIN_PB21__GTX1 PINMUX_PIN(PIN_PB21, 6, 3) -#define PIN_PB22 54 -#define PIN_PB22__GPIO PINMUX_PIN(PIN_PB22, 0, 0) -#define PIN_PB22__LCDDAT11 PINMUX_PIN(PIN_PB22, 1, 1) -#define PIN_PB22__A11 PINMUX_PIN(PIN_PB22, 2, 1) -#define PIN_PB22__TD0 PINMUX_PIN(PIN_PB22, 3, 1) -#define PIN_PB22__TIOA2 PINMUX_PIN(PIN_PB22, 4, 2) -#define PIN_PB22__FLEXCOM3_IO1 PINMUX_PIN(PIN_PB22, 5, 3) -#define PIN_PB22__GMDC PINMUX_PIN(PIN_PB22, 6, 3) -#define PIN_PB23 55 -#define PIN_PB23__GPIO PINMUX_PIN(PIN_PB23, 0, 0) -#define PIN_PB23__LCDDAT12 PINMUX_PIN(PIN_PB23, 1, 1) -#define PIN_PB23__A12 PINMUX_PIN(PIN_PB23, 2, 1) -#define PIN_PB23__RD0 PINMUX_PIN(PIN_PB23, 3, 1) -#define PIN_PB23__TIOB2 PINMUX_PIN(PIN_PB23, 4, 2) -#define PIN_PB23__FLEXCOM3_IO0 PINMUX_PIN(PIN_PB23, 5, 3) -#define PIN_PB23__GMDIO PINMUX_PIN(PIN_PB23, 6, 3) -#define PIN_PB24 56 -#define PIN_PB24__GPIO PINMUX_PIN(PIN_PB24, 0, 0) -#define PIN_PB24__LCDDAT13 PINMUX_PIN(PIN_PB24, 1, 1) -#define PIN_PB24__A13 PINMUX_PIN(PIN_PB24, 2, 1) -#define PIN_PB24__RK0 PINMUX_PIN(PIN_PB24, 3, 1) -#define PIN_PB24__TCLK2 PINMUX_PIN(PIN_PB24, 4, 2) -#define PIN_PB24__FLEXCOM3_IO3 PINMUX_PIN(PIN_PB24, 5, 3) -#define PIN_PB24__ISC_D10 PINMUX_PIN(PIN_PB24, 6, 3) -#define PIN_PB25 57 -#define PIN_PB25__GPIO PINMUX_PIN(PIN_PB25, 0, 0) -#define PIN_PB25__LCDDAT14 PINMUX_PIN(PIN_PB25, 1, 1) -#define PIN_PB25__A14 PINMUX_PIN(PIN_PB25, 2, 1) -#define PIN_PB25__RF0 PINMUX_PIN(PIN_PB25, 3, 1) -#define PIN_PB25__FLEXCOM3_IO4 PINMUX_PIN(PIN_PB25, 5, 3) -#define PIN_PB25__ISC_D11 PINMUX_PIN(PIN_PB25, 6, 3) -#define PIN_PB26 58 -#define PIN_PB26__GPIO PINMUX_PIN(PIN_PB26, 0, 0) -#define PIN_PB26__LCDDAT15 PINMUX_PIN(PIN_PB26, 1, 1) -#define PIN_PB26__A15 PINMUX_PIN(PIN_PB26, 2, 1) -#define PIN_PB26__URXD0 PINMUX_PIN(PIN_PB26, 3, 1) -#define PIN_PB26__PDMIC_DAT PINMUX_PIN(PIN_PB26, 4, 1) -#define PIN_PB26__ISC_D0 PINMUX_PIN(PIN_PB26, 6, 3) -#define PIN_PB27 59 -#define PIN_PB27__GPIO PINMUX_PIN(PIN_PB27, 0, 0) -#define PIN_PB27__LCDDAT16 PINMUX_PIN(PIN_PB27, 1, 1) -#define PIN_PB27__A16 PINMUX_PIN(PIN_PB27, 2, 1) -#define PIN_PB27__UTXD0 PINMUX_PIN(PIN_PB27, 3, 1) -#define PIN_PB27__PDMIC_CLK PINMUX_PIN(PIN_PB27, 4, 1) -#define PIN_PB27__ISC_D1 PINMUX_PIN(PIN_PB27, 6, 3) -#define PIN_PB28 60 -#define PIN_PB28__GPIO PINMUX_PIN(PIN_PB28, 0, 0) -#define PIN_PB28__LCDDAT17 PINMUX_PIN(PIN_PB28, 1, 1) -#define PIN_PB28__A17 PINMUX_PIN(PIN_PB28, 2, 1) -#define PIN_PB28__FLEXCOM0_IO0 PINMUX_PIN(PIN_PB28, 3, 1) -#define PIN_PB28__TIOA5 PINMUX_PIN(PIN_PB28, 4, 2) -#define PIN_PB28__ISC_D2 PINMUX_PIN(PIN_PB28, 6, 3) -#define PIN_PB29 61 -#define PIN_PB29__GPIO PINMUX_PIN(PIN_PB29, 0, 0) -#define PIN_PB29__LCDDAT18 PINMUX_PIN(PIN_PB29, 1, 1) -#define PIN_PB29__A18 PINMUX_PIN(PIN_PB29, 2, 1) -#define PIN_PB29__FLEXCOM0_IO1 PINMUX_PIN(PIN_PB29, 3, 1) -#define PIN_PB29__TIOB5 PINMUX_PIN(PIN_PB29, 4, 2) -#define PIN_PB29__ISC_D3 PINMUX_PIN(PIN_PB29, 7, 3) -#define PIN_PB30 62 -#define PIN_PB30__GPIO PINMUX_PIN(PIN_PB30, 0, 0) -#define PIN_PB30__LCDDAT19 PINMUX_PIN(PIN_PB30, 1, 1) -#define PIN_PB30__A19 PINMUX_PIN(PIN_PB30, 2, 1) -#define PIN_PB30__FLEXCOM0_IO2 PINMUX_PIN(PIN_PB30, 3, 1) -#define PIN_PB30__TCLK5 PINMUX_PIN(PIN_PB30, 4, 2) -#define PIN_PB30__ISC_D4 PINMUX_PIN(PIN_PB30, 6, 3) -#define PIN_PB31 63 -#define PIN_PB31__GPIO PINMUX_PIN(PIN_PB31, 0, 0) -#define PIN_PB31__LCDDAT20 PINMUX_PIN(PIN_PB31, 1, 1) -#define PIN_PB31__A20 PINMUX_PIN(PIN_PB31, 2, 1) -#define PIN_PB31__FLEXCOM0_IO3 PINMUX_PIN(PIN_PB31, 3, 1) -#define PIN_PB31__TWD0 PINMUX_PIN(PIN_PB31, 4, 1) -#define PIN_PB31__ISC_D5 PINMUX_PIN(PIN_PB31, 6, 3) -#define PIN_PC0 64 -#define PIN_PC0__GPIO PINMUX_PIN(PIN_PC0, 0, 0) -#define PIN_PC0__LCDDAT21 PINMUX_PIN(PIN_PC0, 1, 1) -#define PIN_PC0__A23 PINMUX_PIN(PIN_PC0, 2, 1) -#define PIN_PC0__FLEXCOM0_IO4 PINMUX_PIN(PIN_PC0, 3, 1) -#define PIN_PC0__TWCK0 PINMUX_PIN(PIN_PC0, 4, 1) -#define PIN_PC0__ISC_D6 PINMUX_PIN(PIN_PC0, 6, 3) -#define PIN_PC1 65 -#define PIN_PC1__GPIO PINMUX_PIN(PIN_PC1, 0, 0) -#define PIN_PC1__LCDDAT22 PINMUX_PIN(PIN_PC1, 1, 1) -#define PIN_PC1__A24 PINMUX_PIN(PIN_PC1, 2, 1) -#define PIN_PC1__CANTX0 PINMUX_PIN(PIN_PC1, 3, 1) -#define PIN_PC1__SPI1_SPCK PINMUX_PIN(PIN_PC1, 4, 1) -#define PIN_PC1__I2SC0_CK PINMUX_PIN(PIN_PC1, 5, 1) -#define PIN_PC1__ISC_D7 PINMUX_PIN(PIN_PC1, 6, 3) -#define PIN_PC2 66 -#define PIN_PC2__GPIO PINMUX_PIN(PIN_PC2, 0, 0) -#define PIN_PC2__LCDDAT23 PINMUX_PIN(PIN_PC2, 1, 1) -#define PIN_PC2__A25 PINMUX_PIN(PIN_PC2, 2, 1) -#define PIN_PC2__CANRX0 PINMUX_PIN(PIN_PC2, 3, 1) -#define PIN_PC2__SPI1_MOSI PINMUX_PIN(PIN_PC2, 4, 1) -#define PIN_PC2__I2SC0_MCK PINMUX_PIN(PIN_PC2, 5, 1) -#define PIN_PC2__ISC_D8 PINMUX_PIN(PIN_PC2, 6, 3) -#define PIN_PC3 67 -#define PIN_PC3__GPIO PINMUX_PIN(PIN_PC3, 0, 0) -#define PIN_PC3__LCDPWM PINMUX_PIN(PIN_PC3, 1, 1) -#define PIN_PC3__NWAIT PINMUX_PIN(PIN_PC3, 2, 1) -#define PIN_PC3__TIOA1 PINMUX_PIN(PIN_PC3, 3, 1) -#define PIN_PC3__SPI1_MISO PINMUX_PIN(PIN_PC3, 4, 1) -#define PIN_PC3__I2SC0_WS PINMUX_PIN(PIN_PC3, 5, 1) -#define PIN_PC3__ISC_D9 PINMUX_PIN(PIN_PC3, 6, 3) -#define PIN_PC4 68 -#define PIN_PC4__GPIO PINMUX_PIN(PIN_PC4, 0, 0) -#define PIN_PC4__LCDDISP PINMUX_PIN(PIN_PC4, 1, 1) -#define PIN_PC4__NWR1_NBS1 PINMUX_PIN(PIN_PC4, 2, 1) -#define PIN_PC4__TIOB1 PINMUX_PIN(PIN_PC4, 3, 1) -#define PIN_PC4__SPI1_NPCS0 PINMUX_PIN(PIN_PC4, 4, 1) -#define PIN_PC4__I2SC0_DI0 PINMUX_PIN(PIN_PC4, 5, 1) -#define PIN_PC4__ISC_PCK PINMUX_PIN(PIN_PC4, 6, 3) -#define PIN_PC5 69 -#define PIN_PC5__GPIO PINMUX_PIN(PIN_PC5, 0, 0) -#define PIN_PC5__LCDVSYNC PINMUX_PIN(PIN_PC5, 1, 1) -#define PIN_PC5__NCS0 PINMUX_PIN(PIN_PC5, 2, 1) -#define PIN_PC5__TCLK1 PINMUX_PIN(PIN_PC5, 3, 1) -#define PIN_PC5__SPI1_NPCS1 PINMUX_PIN(PIN_PC5, 4, 1) -#define PIN_PC5__I2SC0_DO0 PINMUX_PIN(PIN_PC5, 5, 1) -#define PIN_PC5__ISC_VSYNC PINMUX_PIN(PIN_PC5, 6, 3) -#define PIN_PC6 70 -#define PIN_PC6__GPIO PINMUX_PIN(PIN_PC6, 0, 0) -#define PIN_PC6__LCDHSYNC PINMUX_PIN(PIN_PC6, 1, 1) -#define PIN_PC6__NCS1 PINMUX_PIN(PIN_PC6, 2, 1) -#define PIN_PC6__TWD1 PINMUX_PIN(PIN_PC6, 3, 1) -#define PIN_PC6__SPI1_NPCS2 PINMUX_PIN(PIN_PC6, 4, 1) -#define PIN_PC6__ISC_HSYNC PINMUX_PIN(PIN_PC6, 6, 3) -#define PIN_PC7 71 -#define PIN_PC7__GPIO PINMUX_PIN(PIN_PC7, 0, 0) -#define PIN_PC7__LCDPCK PINMUX_PIN(PIN_PC7, 1, 1) -#define PIN_PC7__NCS2 PINMUX_PIN(PIN_PC7, 2, 1) -#define PIN_PC7__TWCK1 PINMUX_PIN(PIN_PC7, 3, 1) -#define PIN_PC7__SPI1_NPCS3 PINMUX_PIN(PIN_PC7, 4, 1) -#define PIN_PC7__URXD1 PINMUX_PIN(PIN_PC7, 5, 2) -#define PIN_PC7__ISC_MCK PINMUX_PIN(PIN_PC7, 6, 3) -#define PIN_PC8 72 -#define PIN_PC8__GPIO PINMUX_PIN(PIN_PC8, 0, 0) -#define PIN_PC8__LCDDEN PINMUX_PIN(PIN_PC8, 1, 1) -#define PIN_PC8__NANDRDY PINMUX_PIN(PIN_PC8, 2, 1) -#define PIN_PC8__FIQ PINMUX_PIN(PIN_PC8, 3, 1) -#define PIN_PC8__PCK0 PINMUX_PIN(PIN_PC8, 4, 3) -#define PIN_PC8__UTXD1 PINMUX_PIN(PIN_PC8, 5, 2) -#define PIN_PC8__ISC_FIELD PINMUX_PIN(PIN_PC8, 6, 3) -#define PIN_PC9 73 -#define PIN_PC9__GPIO PINMUX_PIN(PIN_PC9, 0, 0) -#define PIN_PC9__FIQ PINMUX_PIN(PIN_PC9, 1, 3) -#define PIN_PC9__GTSUCOMP PINMUX_PIN(PIN_PC9, 2, 1) -#define PIN_PC9__ISC_D0 PINMUX_PIN(PIN_PC9, 3, 1) -#define PIN_PC9__TIOA4 PINMUX_PIN(PIN_PC9, 4, 2) -#define PIN_PC10 74 -#define PIN_PC10__GPIO PINMUX_PIN(PIN_PC10, 0, 0) -#define PIN_PC10__LCDDAT2 PINMUX_PIN(PIN_PC10, 1, 2) -#define PIN_PC10__GTXCK PINMUX_PIN(PIN_PC10, 2, 1) -#define PIN_PC10__ISC_D1 PINMUX_PIN(PIN_PC10, 3, 1) -#define PIN_PC10__TIOB4 PINMUX_PIN(PIN_PC10, 4, 2) -#define PIN_PC10__CANTX0 PINMUX_PIN(PIN_PC10, 5, 2) -#define PIN_PC11 75 -#define PIN_PC11__GPIO PINMUX_PIN(PIN_PC11, 0, 0) -#define PIN_PC11__LCDDAT3 PINMUX_PIN(PIN_PC11, 1, 2) -#define PIN_PC11__GTXEN PINMUX_PIN(PIN_PC11, 2, 1) -#define PIN_PC11__ISC_D2 PINMUX_PIN(PIN_PC11, 3, 1) -#define PIN_PC11__TCLK4 PINMUX_PIN(PIN_PC11, 4, 2) -#define PIN_PC11__CANRX0 PINMUX_PIN(PIN_PC11, 5, 2) -#define PIN_PC11__A0_NBS0 PINMUX_PIN(PIN_PC11, 6, 2) -#define PIN_PC12 76 -#define PIN_PC12__GPIO PINMUX_PIN(PIN_PC12, 0, 0) -#define PIN_PC12__LCDDAT4 PINMUX_PIN(PIN_PC12, 1, 2) -#define PIN_PC12__GRXDV PINMUX_PIN(PIN_PC12, 2, 1) -#define PIN_PC12__ISC_D3 PINMUX_PIN(PIN_PC12, 3, 1) -#define PIN_PC12__URXD3 PINMUX_PIN(PIN_PC12, 4, 1) -#define PIN_PC12__TK0 PINMUX_PIN(PIN_PC12, 5, 2) -#define PIN_PC12__A1 PINMUX_PIN(PIN_PC12, 6, 2) -#define PIN_PC13 77 -#define PIN_PC13__GPIO PINMUX_PIN(PIN_PC13, 0, 0) -#define PIN_PC13__LCDDAT5 PINMUX_PIN(PIN_PC13, 1, 2) -#define PIN_PC13__GRXER PINMUX_PIN(PIN_PC13, 2, 1) -#define PIN_PC13__ISC_D4 PINMUX_PIN(PIN_PC13, 3, 1) -#define PIN_PC13__UTXD3 PINMUX_PIN(PIN_PC13, 4, 1) -#define PIN_PC13__TF0 PINMUX_PIN(PIN_PC13, 5, 2) -#define PIN_PC13__A2 PINMUX_PIN(PIN_PC13, 6, 2) -#define PIN_PC14 78 -#define PIN_PC14__GPIO PINMUX_PIN(PIN_PC14, 0, 0) -#define PIN_PC14__LCDDAT6 PINMUX_PIN(PIN_PC14, 1, 2) -#define PIN_PC14__GRX0 PINMUX_PIN(PIN_PC14, 2, 1) -#define PIN_PC14__ISC_D5 PINMUX_PIN(PIN_PC14, 3, 1) -#define PIN_PC14__TD0 PINMUX_PIN(PIN_PC14, 5, 2) -#define PIN_PC14__A3 PINMUX_PIN(PIN_PC14, 6, 2) -#define PIN_PC15 79 -#define PIN_PC15__GPIO PINMUX_PIN(PIN_PC15, 0, 0) -#define PIN_PC15__LCDDAT7 PINMUX_PIN(PIN_PC15, 1, 2) -#define PIN_PC15__GRX1 PINMUX_PIN(PIN_PC15, 2, 1) -#define PIN_PC15__ISC_D6 PINMUX_PIN(PIN_PC15, 3, 1) -#define PIN_PC15__RD0 PINMUX_PIN(PIN_PC15, 5, 2) -#define PIN_PC15__A4 PINMUX_PIN(PIN_PC15, 6, 2) -#define PIN_PC16 80 -#define PIN_PC16__GPIO PINMUX_PIN(PIN_PC16, 0, 0) -#define PIN_PC16__LCDDAT10 PINMUX_PIN(PIN_PC16, 1, 2) -#define PIN_PC16__GTX0 PINMUX_PIN(PIN_PC16, 2, 1) -#define PIN_PC16__ISC_D7 PINMUX_PIN(PIN_PC16, 3, 1) -#define PIN_PC16__RK0 PINMUX_PIN(PIN_PC16, 5, 2) -#define PIN_PC16__A5 PINMUX_PIN(PIN_PC16, 6, 2) -#define PIN_PC17 81 -#define PIN_PC17__GPIO PINMUX_PIN(PIN_PC17, 0, 0) -#define PIN_PC17__LCDDAT11 PINMUX_PIN(PIN_PC17, 1, 2) -#define PIN_PC17__GTX1 PINMUX_PIN(PIN_PC17, 2, 1) -#define PIN_PC17__ISC_D8 PINMUX_PIN(PIN_PC17, 3, 1) -#define PIN_PC17__RF0 PINMUX_PIN(PIN_PC17, 5, 2) -#define PIN_PC17__A6 PINMUX_PIN(PIN_PC17, 6, 2) -#define PIN_PC18 82 -#define PIN_PC18__GPIO PINMUX_PIN(PIN_PC18, 0, 0) -#define PIN_PC18__LCDDAT12 PINMUX_PIN(PIN_PC18, 1, 2) -#define PIN_PC18__GMDC PINMUX_PIN(PIN_PC18, 2, 1) -#define PIN_PC18__ISC_D9 PINMUX_PIN(PIN_PC18, 3, 1) -#define PIN_PC18__FLEXCOM3_IO2 PINMUX_PIN(PIN_PC18, 5, 2) -#define PIN_PC18__A7 PINMUX_PIN(PIN_PC18, 6, 2) -#define PIN_PC19 83 -#define PIN_PC19__GPIO PINMUX_PIN(PIN_PC19, 0, 0) -#define PIN_PC19__LCDDAT13 PINMUX_PIN(PIN_PC19, 1, 2) -#define PIN_PC19__GMDIO PINMUX_PIN(PIN_PC19, 2, 1) -#define PIN_PC19__ISC_D10 PINMUX_PIN(PIN_PC19, 3, 1) -#define PIN_PC19__FLEXCOM3_IO1 PINMUX_PIN(PIN_PC19, 5, 2) -#define PIN_PC19__A8 PINMUX_PIN(PIN_PC19, 6, 2) -#define PIN_PC20 84 -#define PIN_PC20__GPIO PINMUX_PIN(PIN_PC20, 0, 0) -#define PIN_PC20__LCDDAT14 PINMUX_PIN(PIN_PC20, 1, 2) -#define PIN_PC20__GRXCK PINMUX_PIN(PIN_PC20, 2, 1) -#define PIN_PC20__ISC_D11 PINMUX_PIN(PIN_PC20, 3, 1) -#define PIN_PC20__FLEXCOM3_IO0 PINMUX_PIN(PIN_PC20, 5, 2) -#define PIN_PC20__A9 PINMUX_PIN(PIN_PC20, 6, 2) -#define PIN_PC21 85 -#define PIN_PC21__GPIO PINMUX_PIN(PIN_PC21, 0, 0) -#define PIN_PC21__LCDDAT15 PINMUX_PIN(PIN_PC21, 1, 2) -#define PIN_PC21__GTXER PINMUX_PIN(PIN_PC21, 2, 1) -#define PIN_PC21__ISC_PCK PINMUX_PIN(PIN_PC21, 3, 1) -#define PIN_PC21__FLEXCOM3_IO3 PINMUX_PIN(PIN_PC21, 5, 2) -#define PIN_PC21__A10 PINMUX_PIN(PIN_PC21, 6, 2) -#define PIN_PC22 86 -#define PIN_PC22__GPIO PINMUX_PIN(PIN_PC22, 0, 0) -#define PIN_PC22__LCDDAT18 PINMUX_PIN(PIN_PC22, 1, 2) -#define PIN_PC22__GCRS PINMUX_PIN(PIN_PC22, 2, 1) -#define PIN_PC22__ISC_VSYNC PINMUX_PIN(PIN_PC22, 3, 1) -#define PIN_PC22__FLEXCOM3_IO4 PINMUX_PIN(PIN_PC22, 5, 2) -#define PIN_PC22__A11 PINMUX_PIN(PIN_PC22, 6, 2) -#define PIN_PC23 87 -#define PIN_PC23__GPIO PINMUX_PIN(PIN_PC23, 0, 0) -#define PIN_PC23__LCDDAT19 PINMUX_PIN(PIN_PC23, 1, 2) -#define PIN_PC23__GCOL PINMUX_PIN(PIN_PC23, 2, 1) -#define PIN_PC23__ISC_HSYNC PINMUX_PIN(PIN_PC23, 3, 1) -#define PIN_PC23__A12 PINMUX_PIN(PIN_PC23, 6, 2) -#define PIN_PC24 88 -#define PIN_PC24__GPIO PINMUX_PIN(PIN_PC24, 0, 0) -#define PIN_PC24__LCDDAT20 PINMUX_PIN(PIN_PC24, 1, 2) -#define PIN_PC24__GRX2 PINMUX_PIN(PIN_PC24, 2, 1) -#define PIN_PC24__ISC_MCK PINMUX_PIN(PIN_PC24, 3, 1) -#define PIN_PC24__A13 PINMUX_PIN(PIN_PC24, 6, 2) -#define PIN_PC25 89 -#define PIN_PC25__GPIO PINMUX_PIN(PIN_PC25, 0, 0) -#define PIN_PC25__LCDDAT21 PINMUX_PIN(PIN_PC25, 1, 2) -#define PIN_PC25__GRX3 PINMUX_PIN(PIN_PC25, 2, 1) -#define PIN_PC25__ISC_FIELD PINMUX_PIN(PIN_PC25, 3, 1) -#define PIN_PC25__A14 PINMUX_PIN(PIN_PC25, 6, 2) -#define PIN_PC26 90 -#define PIN_PC26__GPIO PINMUX_PIN(PIN_PC26, 0, 0) -#define PIN_PC26__LCDDAT22 PINMUX_PIN(PIN_PC26, 1, 2) -#define PIN_PC26__GTX2 PINMUX_PIN(PIN_PC26, 2, 1) -#define PIN_PC26__CANTX1 PINMUX_PIN(PIN_PC26, 4, 1) -#define PIN_PC26__A15 PINMUX_PIN(PIN_PC26, 6, 2) -#define PIN_PC27 91 -#define PIN_PC27__GPIO PINMUX_PIN(PIN_PC27, 0, 0) -#define PIN_PC27__LCDDAT23 PINMUX_PIN(PIN_PC27, 1, 2) -#define PIN_PC27__GTX3 PINMUX_PIN(PIN_PC27, 2, 1) -#define PIN_PC27__PCK1 PINMUX_PIN(PIN_PC27, 3, 2) -#define PIN_PC27__CANRX1 PINMUX_PIN(PIN_PC27, 4, 1) -#define PIN_PC27__TWD0 PINMUX_PIN(PIN_PC27, 5, 2) -#define PIN_PC27__A16 PINMUX_PIN(PIN_PC27, 6, 2) -#define PIN_PC28 92 -#define PIN_PC28__GPIO PINMUX_PIN(PIN_PC28, 0, 0) -#define PIN_PC28__LCDPWM PINMUX_PIN(PIN_PC28, 1, 2) -#define PIN_PC28__FLEXCOM4_IO0 PINMUX_PIN(PIN_PC28, 2, 1) -#define PIN_PC28__PCK2 PINMUX_PIN(PIN_PC28, 3, 2) -#define PIN_PC28__TWCK0 PINMUX_PIN(PIN_PC28, 5, 2) -#define PIN_PC28__A17 PINMUX_PIN(PIN_PC28, 6, 2) -#define PIN_PC29 93 -#define PIN_PC29__GPIO PINMUX_PIN(PIN_PC29, 0, 0) -#define PIN_PC29__LCDDISP PINMUX_PIN(PIN_PC29, 1, 2) -#define PIN_PC29__FLEXCOM4_IO1 PINMUX_PIN(PIN_PC29, 2, 1) -#define PIN_PC29__A18 PINMUX_PIN(PIN_PC29, 6, 2) -#define PIN_PC30 94 -#define PIN_PC30__GPIO PINMUX_PIN(PIN_PC30, 0, 0) -#define PIN_PC30__LCDVSYNC PINMUX_PIN(PIN_PC30, 1, 2) -#define PIN_PC30__FLEXCOM4_IO2 PINMUX_PIN(PIN_PC30, 2, 1) -#define PIN_PC30__A19 PINMUX_PIN(PIN_PC30, 6, 2) -#define PIN_PC31 95 -#define PIN_PC31__GPIO PINMUX_PIN(PIN_PC31, 0, 0) -#define PIN_PC31__LCDHSYNC PINMUX_PIN(PIN_PC31, 1, 2) -#define PIN_PC31__FLEXCOM4_IO3 PINMUX_PIN(PIN_PC31, 2, 1) -#define PIN_PC31__URXD3 PINMUX_PIN(PIN_PC31, 3, 2) -#define PIN_PC31__A20 PINMUX_PIN(PIN_PC31, 6, 2) -#define PIN_PD0 96 -#define PIN_PD0__GPIO PINMUX_PIN(PIN_PD0, 0, 0) -#define PIN_PD0__LCDPCK PINMUX_PIN(PIN_PD0, 1, 2) -#define PIN_PD0__FLEXCOM4_IO4 PINMUX_PIN(PIN_PD0, 2, 1) -#define PIN_PD0__UTXD3 PINMUX_PIN(PIN_PD0, 3, 2) -#define PIN_PD0__GTSUCOMP PINMUX_PIN(PIN_PD0, 4, 2) -#define PIN_PD0__A23 PINMUX_PIN(PIN_PD0, 6, 2) -#define PIN_PD1 97 -#define PIN_PD1__GPIO PINMUX_PIN(PIN_PD1, 0, 0) -#define PIN_PD1__LCDDEN PINMUX_PIN(PIN_PD1, 1, 2) -#define PIN_PD1__GRXCK PINMUX_PIN(PIN_PD1, 4, 2) -#define PIN_PD1__A24 PINMUX_PIN(PIN_PD1, 6, 2) -#define PIN_PD2 98 -#define PIN_PD2__GPIO PINMUX_PIN(PIN_PD2, 0, 0) -#define PIN_PD2__URXD1 PINMUX_PIN(PIN_PD2, 1, 1) -#define PIN_PD2__GTXER PINMUX_PIN(PIN_PD2, 4, 2) -#define PIN_PD2__ISC_MCK PINMUX_PIN(PIN_PD2, 5, 2) -#define PIN_PD2__A25 PINMUX_PIN(PIN_PD2, 6, 2) -#define PIN_PD3 99 -#define PIN_PD3__GPIO PINMUX_PIN(PIN_PD3, 0, 0) -#define PIN_PD3__UTXD1 PINMUX_PIN(PIN_PD3, 1, 1) -#define PIN_PD3__FIQ PINMUX_PIN(PIN_PD3, 2, 2) -#define PIN_PD3__GCRS PINMUX_PIN(PIN_PD3, 4, 2) -#define PIN_PD3__ISC_D11 PINMUX_PIN(PIN_PD3, 5, 2) -#define PIN_PD3__NWAIT PINMUX_PIN(PIN_PD3, 6, 2) -#define PIN_PD4 100 -#define PIN_PD4__GPIO PINMUX_PIN(PIN_PD4, 0, 0) -#define PIN_PD4__TWD1 PINMUX_PIN(PIN_PD4, 1, 2) -#define PIN_PD4__URXD2 PINMUX_PIN(PIN_PD4, 2, 1) -#define PIN_PD4__GCOL PINMUX_PIN(PIN_PD4, 4, 2) -#define PIN_PD4__ISC_D10 PINMUX_PIN(PIN_PD4, 5, 2) -#define PIN_PD4__NCS0 PINMUX_PIN(PIN_PD4, 6, 2) -#define PIN_PD5 101 -#define PIN_PD5__GPIO PINMUX_PIN(PIN_PD5, 0, 0) -#define PIN_PD5__TWCK1 PINMUX_PIN(PIN_PD5, 1, 2) -#define PIN_PD5__UTXD2 PINMUX_PIN(PIN_PD5, 2, 1) -#define PIN_PD5__GRX2 PINMUX_PIN(PIN_PD5, 4, 2) -#define PIN_PD5__ISC_D9 PINMUX_PIN(PIN_PD5, 5, 2) -#define PIN_PD5__NCS1 PINMUX_PIN(PIN_PD5, 6, 2) -#define PIN_PD6 102 -#define PIN_PD6__GPIO PINMUX_PIN(PIN_PD6, 0, 0) -#define PIN_PD6__TCK PINMUX_PIN(PIN_PD6, 1, 2) -#define PIN_PD6__PCK1 PINMUX_PIN(PIN_PD6, 2, 1) -#define PIN_PD6__GRX3 PINMUX_PIN(PIN_PD6, 4, 2) -#define PIN_PD6__ISC_D8 PINMUX_PIN(PIN_PD6, 5, 2) -#define PIN_PD6__NCS2 PINMUX_PIN(PIN_PD6, 6, 2) -#define PIN_PD7 103 -#define PIN_PD7__GPIO PINMUX_PIN(PIN_PD7, 0, 0) -#define PIN_PD7__TDI PINMUX_PIN(PIN_PD7, 1, 2) -#define PIN_PD7__UTMI_RXVAL PINMUX_PIN(PIN_PD7, 3, 1) -#define PIN_PD7__GTX2 PINMUX_PIN(PIN_PD7, 4, 2) -#define PIN_PD7__ISC_D0 PINMUX_PIN(PIN_PD7, 5, 2) -#define PIN_PD7__NWR1_NBS1 PINMUX_PIN(PIN_PD7, 6, 2) -#define PIN_PD8 104 -#define PIN_PD8__GPIO PINMUX_PIN(PIN_PD8, 0, 0) -#define PIN_PD8__TDO PINMUX_PIN(PIN_PD8, 1, 2) -#define PIN_PD8__UTMI_RXERR PINMUX_PIN(PIN_PD8, 3, 1) -#define PIN_PD8__GTX3 PINMUX_PIN(PIN_PD8, 4, 2) -#define PIN_PD8__ISC_D1 PINMUX_PIN(PIN_PD8, 5, 2) -#define PIN_PD8__NANDRDY PINMUX_PIN(PIN_PD8, 6, 2) -#define PIN_PD9 105 -#define PIN_PD9__GPIO PINMUX_PIN(PIN_PD9, 0, 0) -#define PIN_PD9__TMS PINMUX_PIN(PIN_PD9, 1, 2) -#define PIN_PD9__UTMI_RXACT PINMUX_PIN(PIN_PD9, 3, 1) -#define PIN_PD9__GTXCK PINMUX_PIN(PIN_PD9, 4, 2) -#define PIN_PD9__ISC_D2 PINMUX_PIN(PIN_PD9, 5, 2) -#define PIN_PD10 106 -#define PIN_PD10__GPIO PINMUX_PIN(PIN_PD10, 0, 0) -#define PIN_PD10__NTRST PINMUX_PIN(PIN_PD10, 1, 2) -#define PIN_PD10__UTMI_HDIS PINMUX_PIN(PIN_PD10, 3, 1) -#define PIN_PD10__GTXEN PINMUX_PIN(PIN_PD10, 4, 2) -#define PIN_PD10__ISC_D3 PINMUX_PIN(PIN_PD10, 5, 2) -#define PIN_PD11 107 -#define PIN_PD11__GPIO PINMUX_PIN(PIN_PD11, 0, 0) -#define PIN_PD11__TIOA1 PINMUX_PIN(PIN_PD11, 1, 3) -#define PIN_PD11__PCK2 PINMUX_PIN(PIN_PD11, 2, 2) -#define PIN_PD11__UTMI_LS0 PINMUX_PIN(PIN_PD11, 3, 1) -#define PIN_PD11__GRXDV PINMUX_PIN(PIN_PD11, 4, 2) -#define PIN_PD11__ISC_D4 PINMUX_PIN(PIN_PD11, 5, 2) -#define PIN_PD11__ISC_MCK PINMUX_PIN(PIN_PD11, 7, 4) -#define PIN_PD12 108 -#define PIN_PD12__GPIO PINMUX_PIN(PIN_PD12, 0, 0) -#define PIN_PD12__TIOB1 PINMUX_PIN(PIN_PD12, 1, 3) -#define PIN_PD12__FLEXCOM4_IO0 PINMUX_PIN(PIN_PD12, 2, 2) -#define PIN_PD12__UTMI_LS1 PINMUX_PIN(PIN_PD12, 3, 1) -#define PIN_PD12__GRXER PINMUX_PIN(PIN_PD12, 4, 2) -#define PIN_PD12__ISC_D5 PINMUX_PIN(PIN_PD12, 5, 2) -#define PIN_PD12__ISC_D4 PINMUX_PIN(PIN_PD12, 6, 4) -#define PIN_PD13 109 -#define PIN_PD13__GPIO PINMUX_PIN(PIN_PD13, 0, 0) -#define PIN_PD13__TCLK1 PINMUX_PIN(PIN_PD13, 1, 3) -#define PIN_PD13__FLEXCOM4_IO1 PINMUX_PIN(PIN_PD13, 2, 2) -#define PIN_PD13__UTMI_CDRPCSEL0 PINMUX_PIN(PIN_PD13, 3, 1) -#define PIN_PD13__GRX0 PINMUX_PIN(PIN_PD13, 4, 2) -#define PIN_PD13__ISC_D6 PINMUX_PIN(PIN_PD13, 5, 2) -#define PIN_PD13__ISC_D5 PINMUX_PIN(PIN_PD13, 6, 4) -#define PIN_PD14 110 -#define PIN_PD14__GPIO PINMUX_PIN(PIN_PD14, 0, 0) -#define PIN_PD14__TCK PINMUX_PIN(PIN_PD14, 1, 1) -#define PIN_PD14__FLEXCOM4_IO2 PINMUX_PIN(PIN_PD14, 2, 2) -#define PIN_PD14__UTMI_CDRPCSEL1 PINMUX_PIN(PIN_PD14, 3, 1) -#define PIN_PD14__GRX1 PINMUX_PIN(PIN_PD14, 4, 2) -#define PIN_PD14__ISC_D7 PINMUX_PIN(PIN_PD14, 5, 2) -#define PIN_PD14__ISC_D6 PINMUX_PIN(PIN_PD14, 6, 4) -#define PIN_PD15 111 -#define PIN_PD15__GPIO PINMUX_PIN(PIN_PD15, 0, 0) -#define PIN_PD15__TDI PINMUX_PIN(PIN_PD15, 1, 1) -#define PIN_PD15__FLEXCOM4_IO3 PINMUX_PIN(PIN_PD15, 2, 2) -#define PIN_PD15__UTMI_CDRCPDIVEN PINMUX_PIN(PIN_PD15, 3, 1) -#define PIN_PD15__GTX0 PINMUX_PIN(PIN_PD15, 4, 2) -#define PIN_PD15__ISC_PCK PINMUX_PIN(PIN_PD15, 5, 2) -#define PIN_PD15__ISC_D7 PINMUX_PIN(PIN_PD15, 6, 4) -#define PIN_PD16 112 -#define PIN_PD16__GPIO PINMUX_PIN(PIN_PD16, 0, 0) -#define PIN_PD16__TDO PINMUX_PIN(PIN_PD16, 1, 1) -#define PIN_PD16__FLEXCOM4_IO4 PINMUX_PIN(PIN_PD16, 2, 2) -#define PIN_PD16__UTMI_CDRBISTEN PINMUX_PIN(PIN_PD16, 3, 1) -#define PIN_PD16__GTX1 PINMUX_PIN(PIN_PD16, 4, 2) -#define PIN_PD16__ISC_VSYNC PINMUX_PIN(PIN_PD16, 5, 2) -#define PIN_PD16__ISC_D8 PINMUX_PIN(PIN_PD16, 6, 4) -#define PIN_PD17 113 -#define PIN_PD17__GPIO PINMUX_PIN(PIN_PD17, 0, 0) -#define PIN_PD17__TMS PINMUX_PIN(PIN_PD17, 1, 1) -#define PIN_PD17__UTMI_CDRCPSELDIV PINMUX_PIN(PIN_PD17, 3, 1) -#define PIN_PD17__GMDC PINMUX_PIN(PIN_PD17, 4, 2) -#define PIN_PD17__ISC_HSYNC PINMUX_PIN(PIN_PD17, 5, 2) -#define PIN_PD17__ISC_D9 PINMUX_PIN(PIN_PD17, 6, 4) -#define PIN_PD18 114 -#define PIN_PD18__GPIO PINMUX_PIN(PIN_PD18, 0, 0) -#define PIN_PD18__NTRST PINMUX_PIN(PIN_PD18, 1, 1) -#define PIN_PD18__GMDIO PINMUX_PIN(PIN_PD18, 4, 2) -#define PIN_PD18__ISC_FIELD PINMUX_PIN(PIN_PD18, 5, 2) -#define PIN_PD18__ISC_D10 PINMUX_PIN(PIN_PD18, 6, 4) -#define PIN_PD19 115 -#define PIN_PD19__GPIO PINMUX_PIN(PIN_PD19, 0, 0) -#define PIN_PD19__PCK0 PINMUX_PIN(PIN_PD19, 1, 1) -#define PIN_PD19__TWD1 PINMUX_PIN(PIN_PD19, 2, 3) -#define PIN_PD19__URXD2 PINMUX_PIN(PIN_PD19, 3, 3) -#define PIN_PD19__I2SC0_CK PINMUX_PIN(PIN_PD19, 5, 2) -#define PIN_PD19__ISC_D11 PINMUX_PIN(PIN_PD19, 6, 4) -#define PIN_PD20 116 -#define PIN_PD20__GPIO PINMUX_PIN(PIN_PD20, 0, 0) -#define PIN_PD20__TIOA2 PINMUX_PIN(PIN_PD20, 1, 3) -#define PIN_PD20__TWCK1 PINMUX_PIN(PIN_PD20, 2, 3) -#define PIN_PD20__UTXD2 PINMUX_PIN(PIN_PD20, 3, 3) -#define PIN_PD20__I2SC0_MCK PINMUX_PIN(PIN_PD20, 5, 2) -#define PIN_PD20__ISC_PCK PINMUX_PIN(PIN_PD20, 6, 4) -#define PIN_PD21 117 -#define PIN_PD21__GPIO PINMUX_PIN(PIN_PD21, 0, 0) -#define PIN_PD21__TIOB2 PINMUX_PIN(PIN_PD21, 1, 3) -#define PIN_PD21__TWD0 PINMUX_PIN(PIN_PD21, 2, 4) -#define PIN_PD21__FLEXCOM4_IO0 PINMUX_PIN(PIN_PD21, 3, 3) -#define PIN_PD21__I2SC0_WS PINMUX_PIN(PIN_PD21, 5, 2) -#define PIN_PD21__ISC_VSYNC PINMUX_PIN(PIN_PD21, 6, 4) -#define PIN_PD22 118 -#define PIN_PD22__GPIO PINMUX_PIN(PIN_PD22, 0, 0) -#define PIN_PD22__TCLK2 PINMUX_PIN(PIN_PD22, 1, 3) -#define PIN_PD22__TWCK0 PINMUX_PIN(PIN_PD22, 2, 4) -#define PIN_PD22__FLEXCOM4_IO1 PINMUX_PIN(PIN_PD22, 3, 3) -#define PIN_PD22__I2SC0_DI0 PINMUX_PIN(PIN_PD22, 5, 2) -#define PIN_PD22__ISC_HSYNC PINMUX_PIN(PIN_PD22, 6, 4) -#define PIN_PD23 119 -#define PIN_PD23__GPIO PINMUX_PIN(PIN_PD23, 0, 0) -#define PIN_PD23__URXD2 PINMUX_PIN(PIN_PD23, 1, 2) -#define PIN_PD23__FLEXCOM4_IO2 PINMUX_PIN(PIN_PD23, 3, 3) -#define PIN_PD23__I2SC0_DO0 PINMUX_PIN(PIN_PD23, 5, 2) -#define PIN_PD23__ISC_FIELD PINMUX_PIN(PIN_PD23, 6, 4) -#define PIN_PD24 120 -#define PIN_PD24__GPIO PINMUX_PIN(PIN_PD24, 0, 0) -#define PIN_PD24__UTXD2 PINMUX_PIN(PIN_PD24, 1, 2) -#define PIN_PD24__FLEXCOM4_IO3 PINMUX_PIN(PIN_PD24, 3, 3) -#define PIN_PD25 121 -#define PIN_PD25__GPIO PINMUX_PIN(PIN_PD25, 0, 0) -#define PIN_PD25__SPI1_SPCK PINMUX_PIN(PIN_PD25, 1, 3) -#define PIN_PD25__FLEXCOM4_IO4 PINMUX_PIN(PIN_PD25, 3, 3) -#define PIN_PD26 122 -#define PIN_PD26__GPIO PINMUX_PIN(PIN_PD26, 0, 0) -#define PIN_PD26__SPI1_MOSI PINMUX_PIN(PIN_PD26, 1, 3) -#define PIN_PD26__FLEXCOM2_IO0 PINMUX_PIN(PIN_PD26, 3, 2) -#define PIN_PD27 123 -#define PIN_PD27__GPIO PINMUX_PIN(PIN_PD27, 0, 0) -#define PIN_PD27__SPI1_MISO PINMUX_PIN(PIN_PD27, 1, 3) -#define PIN_PD27__TCK PINMUX_PIN(PIN_PD27, 2, 3) -#define PIN_PD27__FLEXCOM2_IO1 PINMUX_PIN(PIN_PD27, 3, 2) -#define PIN_PD28 124 -#define PIN_PD28__GPIO PINMUX_PIN(PIN_PD28, 0, 0) -#define PIN_PD28__SPI1_NPCS0 PINMUX_PIN(PIN_PD28, 1, 3) -#define PIN_PD28__TCI PINMUX_PIN(PIN_PD28, 2, 3) -#define PIN_PD28__FLEXCOM2_IO2 PINMUX_PIN(PIN_PD28, 3, 2) -#define PIN_PD29 125 -#define PIN_PD29__GPIO PINMUX_PIN(PIN_PD29, 0, 0) -#define PIN_PD29__SPI1_NPCS1 PINMUX_PIN(PIN_PD29, 1, 3) -#define PIN_PD29__TDO PINMUX_PIN(PIN_PD29, 2, 3) -#define PIN_PD29__FLEXCOM2_IO3 PINMUX_PIN(PIN_PD29, 3, 2) -#define PIN_PD29__TIOA3 PINMUX_PIN(PIN_PD29, 4, 3) -#define PIN_PD29__TWD0 PINMUX_PIN(PIN_PD29, 5, 3) -#define PIN_PD30 126 -#define PIN_PD30__GPIO PINMUX_PIN(PIN_PD30, 0, 0) -#define PIN_PD30__SPI1_NPCS2 PINMUX_PIN(PIN_PD30, 1, 3) -#define PIN_PD30__TMS PINMUX_PIN(PIN_PD30, 2, 3) -#define PIN_PD30__FLEXCOM2_IO4 PINMUX_PIN(PIN_PD30, 3, 2) -#define PIN_PD30__TIOB3 PINMUX_PIN(PIN_PD30, 4, 3) -#define PIN_PD30__TWCK0 PINMUX_PIN(PIN_PD30, 5, 3) -#define PIN_PD31 127 -#define PIN_PD31__GPIO PINMUX_PIN(PIN_PD31, 0, 0) -#define PIN_PD31__ADTRG PINMUX_PIN(PIN_PD31, 1, 1) -#define PIN_PD31__NTRST PINMUX_PIN(PIN_PD31, 2, 3) -#define PIN_PD31__IRQ PINMUX_PIN(PIN_PD31, 3, 4) -#define PIN_PD31__TCLK3 PINMUX_PIN(PIN_PD31, 4, 3) -#define PIN_PD31__PCK0 PINMUX_PIN(PIN_PD31, 5, 2) diff --git a/sys/gnu/dts/arm/sama5d2.dtsi b/sys/gnu/dts/arm/sama5d2.dtsi deleted file mode 100644 index 2012b7407c6..00000000000 --- a/sys/gnu/dts/arm/sama5d2.dtsi +++ /dev/null @@ -1,974 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * sama5d2.dtsi - Device Tree Include file for SAMA5D2 family SoC - * - * Copyright (C) 2015 Atmel, - * 2015 Ludovic Desroches - */ - -#include -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - model = "Atmel SAMA5D2 family SoC"; - compatible = "atmel,sama5d2"; - interrupt-parent = <&aic>; - - aliases { - serial0 = &uart1; - serial1 = &uart3; - tcb0 = &tcb0; - tcb1 = &tcb1; - i2s0 = &i2s0; - i2s1 = &i2s1; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a5"; - reg = <0>; - next-level-cache = <&L2>; - }; - }; - - pmu { - compatible = "arm,cortex-a5-pmu"; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH 0>; - }; - - etb { - compatible = "arm,coresight-etb10", "arm,primecell"; - reg = <0x740000 0x1000>; - - clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; - clock-names = "apb_pclk"; - - in-ports { - port { - etb_in: endpoint { - remote-endpoint = <&etm_out>; - }; - }; - }; - }; - - etm { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0x73C000 0x1000>; - - clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; - clock-names = "apb_pclk"; - - out-ports { - port { - etm_out: endpoint { - remote-endpoint = <&etb_in>; - }; - }; - }; - }; - - memory { - device_type = "memory"; - reg = <0x20000000 0x20000000>; - }; - - clocks { - slow_xtal: slow_xtal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - main_xtal: main_xtal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - }; - - ns_sram: sram@200000 { - compatible = "mmio-sram"; - reg = <0x00200000 0x20000>; - }; - - ahb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - nfc_sram: sram@100000 { - compatible = "mmio-sram"; - no-memory-wc; - reg = <0x00100000 0x2400>; - }; - - usb0: gadget@300000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "atmel,sama5d3-udc"; - reg = <0x00300000 0x100000 - 0xfc02c000 0x400>; - interrupts = <42 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 42>, <&pmc PMC_TYPE_CORE PMC_UTMI>; - clock-names = "pclk", "hclk"; - status = "disabled"; - - ep@0 { - reg = <0>; - atmel,fifo-size = <64>; - atmel,nb-banks = <1>; - }; - - ep@1 { - reg = <1>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <3>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@2 { - reg = <2>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <3>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@3 { - reg = <3>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@4 { - reg = <4>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@5 { - reg = <5>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@6 { - reg = <6>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@7 { - reg = <7>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@8 { - reg = <8>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-isoc; - }; - - ep@9 { - reg = <9>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-isoc; - }; - - ep@10 { - reg = <10>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-isoc; - }; - - ep@11 { - reg = <11>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-isoc; - }; - - ep@12 { - reg = <12>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-isoc; - }; - - ep@13 { - reg = <13>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-isoc; - }; - - ep@14 { - reg = <14>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-isoc; - }; - - ep@15 { - reg = <15>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-isoc; - }; - }; - - usb1: ohci@400000 { - compatible = "atmel,at91rm9200-ohci", "usb-ohci"; - reg = <0x00400000 0x100000>; - interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 41>, <&pmc PMC_TYPE_PERIPHERAL 41>, <&pmc PMC_TYPE_SYSTEM 6>; - clock-names = "ohci_clk", "hclk", "uhpck"; - status = "disabled"; - }; - - usb2: ehci@500000 { - compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; - reg = <0x00500000 0x100000>; - interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 41>; - clock-names = "usb_clk", "ehci_clk"; - status = "disabled"; - }; - - L2: cache-controller@a00000 { - compatible = "arm,pl310-cache"; - reg = <0x00a00000 0x1000>; - interrupts = <63 IRQ_TYPE_LEVEL_HIGH 4>; - cache-unified; - cache-level = <2>; - }; - - ebi: ebi@10000000 { - compatible = "atmel,sama5d3-ebi"; - #address-cells = <2>; - #size-cells = <1>; - atmel,smc = <&hsmc>; - reg = <0x10000000 0x10000000 - 0x60000000 0x30000000>; - ranges = <0x0 0x0 0x10000000 0x10000000 - 0x1 0x0 0x60000000 0x10000000 - 0x2 0x0 0x70000000 0x10000000 - 0x3 0x0 0x80000000 0x10000000>; - clocks = <&pmc PMC_TYPE_CORE PMC_MCK2>; - status = "disabled"; - - nand_controller: nand-controller { - compatible = "atmel,sama5d3-nand-controller"; - atmel,nfc-sram = <&nfc_sram>; - atmel,nfc-io = <&nfc_io>; - ecc-engine = <&pmecc>; - #address-cells = <2>; - #size-cells = <1>; - ranges; - status = "disabled"; - }; - }; - - sdmmc0: sdio-host@a0000000 { - compatible = "atmel,sama5d2-sdhci"; - reg = <0xa0000000 0x300>; - interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 31>, <&pmc PMC_TYPE_GCK 31>, <&pmc PMC_TYPE_CORE PMC_MAIN>; - clock-names = "hclock", "multclk", "baseclk"; - assigned-clocks = <&pmc PMC_TYPE_GCK 31>; - assigned-clock-rates = <480000000>; - status = "disabled"; - }; - - sdmmc1: sdio-host@b0000000 { - compatible = "atmel,sama5d2-sdhci"; - reg = <0xb0000000 0x300>; - interrupts = <32 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 32>, <&pmc PMC_TYPE_GCK 32>, <&pmc PMC_TYPE_CORE PMC_MAIN>; - clock-names = "hclock", "multclk", "baseclk"; - assigned-clocks = <&pmc PMC_TYPE_GCK 32>; - assigned-clock-rates = <480000000>; - status = "disabled"; - }; - - nfc_io: nfc-io@c0000000 { - compatible = "atmel,sama5d3-nfc-io", "syscon"; - reg = <0xc0000000 0x8000000>; - }; - - apb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - hlcdc: hlcdc@f0000000 { - compatible = "atmel,sama5d2-hlcdc"; - reg = <0xf0000000 0x2000>; - interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 45>, <&pmc PMC_TYPE_SYSTEM 3>, <&clk32k>; - clock-names = "periph_clk","sys_clk", "slow_clk"; - status = "disabled"; - - hlcdc-display-controller { - compatible = "atmel,hlcdc-display-controller"; - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - }; - - hlcdc_pwm: hlcdc-pwm { - compatible = "atmel,hlcdc-pwm"; - #pwm-cells = <3>; - }; - }; - - isc: isc@f0008000 { - compatible = "atmel,sama5d2-isc"; - reg = <0xf0008000 0x4000>; - interrupts = <46 IRQ_TYPE_LEVEL_HIGH 5>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 46>, <&pmc PMC_TYPE_SYSTEM 18>, <&pmc PMC_TYPE_GCK 46>; - clock-names = "hclock", "iscck", "gck"; - #clock-cells = <0>; - clock-output-names = "isc-mck"; - status = "disabled"; - }; - - ramc0: ramc@f000c000 { - compatible = "atmel,sama5d3-ddramc"; - reg = <0xf000c000 0x200>; - clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_PERIPHERAL 13>; - clock-names = "ddrck", "mpddr"; - }; - - dma0: dma-controller@f0010000 { - compatible = "atmel,sama5d4-dma"; - reg = <0xf0010000 0x1000>; - interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>; - #dma-cells = <1>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; - clock-names = "dma_clk"; - }; - - /* Place dma1 here despite its address */ - dma1: dma-controller@f0004000 { - compatible = "atmel,sama5d4-dma"; - reg = <0xf0004000 0x1000>; - interrupts = <7 IRQ_TYPE_LEVEL_HIGH 0>; - #dma-cells = <1>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; - clock-names = "dma_clk"; - }; - - pmc: pmc@f0014000 { - compatible = "atmel,sama5d2-pmc", "syscon"; - reg = <0xf0014000 0x160>; - interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>; - #clock-cells = <2>; - clocks = <&clk32k>, <&main_xtal>; - clock-names = "slow_clk", "main_xtal"; - }; - - qspi0: spi@f0020000 { - compatible = "atmel,sama5d2-qspi"; - reg = <0xf0020000 0x100>, <0xd0000000 0x08000000>; - reg-names = "qspi_base", "qspi_mmap"; - interrupts = <52 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 52>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - qspi1: spi@f0024000 { - compatible = "atmel,sama5d2-qspi"; - reg = <0xf0024000 0x100>, <0xd8000000 0x08000000>; - reg-names = "qspi_base", "qspi_mmap"; - interrupts = <53 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 53>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - sha@f0028000 { - compatible = "atmel,at91sam9g46-sha"; - reg = <0xf0028000 0x100>; - interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(30))>; - dma-names = "tx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 12>; - clock-names = "sha_clk"; - status = "okay"; - }; - - aes@f002c000 { - compatible = "atmel,at91sam9g46-aes"; - reg = <0xf002c000 0x100>; - interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(26))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(27))>; - dma-names = "tx", "rx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; - clock-names = "aes_clk"; - status = "okay"; - }; - - spi0: spi@f8000000 { - compatible = "atmel,at91rm9200-spi"; - reg = <0xf8000000 0x100>; - interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(6))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(7))>; - dma-names = "tx", "rx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 33>; - clock-names = "spi_clk"; - atmel,fifo-size = <16>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - ssc0: ssc@f8004000 { - compatible = "atmel,at91sam9g45-ssc"; - reg = <0xf8004000 0x4000>; - interrupts = <43 IRQ_TYPE_LEVEL_HIGH 4>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(21))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(22))>; - dma-names = "tx", "rx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 43>; - clock-names = "pclk"; - status = "disabled"; - }; - - macb0: ethernet@f8008000 { - compatible = "atmel,sama5d2-gem"; - reg = <0xf8008000 0x1000>; - interrupts = <5 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 0 */ - 66 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 1 */ - 67 IRQ_TYPE_LEVEL_HIGH 3>; /* Queue 2 */ - #address-cells = <1>; - #size-cells = <0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 5>, <&pmc PMC_TYPE_PERIPHERAL 5>; - clock-names = "hclk", "pclk"; - status = "disabled"; - }; - - tcb0: timer@f800c000 { - compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xf800c000 0x100>; - interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 35>, <&clk32k>; - clock-names = "t0_clk", "slow_clk"; - }; - - tcb1: timer@f8010000 { - compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xf8010000 0x100>; - interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 36>, <&clk32k>; - clock-names = "t0_clk", "slow_clk"; - }; - - hsmc: hsmc@f8014000 { - compatible = "atmel,sama5d2-smc", "syscon", "simple-mfd"; - reg = <0xf8014000 0x1000>; - interrupts = <17 IRQ_TYPE_LEVEL_HIGH 6>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 17>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - pmecc: ecc-engine@f8014070 { - compatible = "atmel,sama5d2-pmecc"; - reg = <0xf8014070 0x490>, - <0xf8014500 0x100>; - }; - }; - - pdmic: pdmic@f8018000 { - compatible = "atmel,sama5d2-pdmic"; - reg = <0xf8018000 0x124>; - interrupts = <48 IRQ_TYPE_LEVEL_HIGH 7>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(50))>; - dma-names = "rx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 48>, <&pmc PMC_TYPE_GCK 48>; - clock-names = "pclk", "gclk"; - status = "disabled"; - }; - - uart0: serial@f801c000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xf801c000 0x100>; - interrupts = <24 IRQ_TYPE_LEVEL_HIGH 7>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(35))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(36))>; - dma-names = "tx", "rx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 24>; - clock-names = "usart"; - status = "disabled"; - }; - - uart1: serial@f8020000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xf8020000 0x100>; - interrupts = <25 IRQ_TYPE_LEVEL_HIGH 7>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(37))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(38))>; - dma-names = "tx", "rx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 25>; - clock-names = "usart"; - status = "disabled"; - }; - - uart2: serial@f8024000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xf8024000 0x100>; - interrupts = <26 IRQ_TYPE_LEVEL_HIGH 7>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(39))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(40))>; - dma-names = "tx", "rx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 26>; - clock-names = "usart"; - status = "disabled"; - }; - - i2c0: i2c@f8028000 { - compatible = "atmel,sama5d2-i2c"; - reg = <0xf8028000 0x100>; - interrupts = <29 IRQ_TYPE_LEVEL_HIGH 7>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(0))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(1))>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 29>; - atmel,fifo-size = <16>; - status = "disabled"; - }; - - pwm0: pwm@f802c000 { - compatible = "atmel,sama5d2-pwm"; - reg = <0xf802c000 0x4000>; - interrupts = <38 IRQ_TYPE_LEVEL_HIGH 7>; - #pwm-cells = <3>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; - status = "disabled"; - }; - - sfr: sfr@f8030000 { - compatible = "atmel,sama5d2-sfr", "syscon"; - reg = <0xf8030000 0x98>; - }; - - flx0: flexcom@f8034000 { - compatible = "atmel,sama5d2-flexcom"; - reg = <0xf8034000 0x200>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xf8034000 0x800>; - status = "disabled"; - }; - - flx1: flexcom@f8038000 { - compatible = "atmel,sama5d2-flexcom"; - reg = <0xf8038000 0x200>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xf8038000 0x800>; - status = "disabled"; - }; - - securam: sram@f8044000 { - compatible = "atmel,sama5d2-securam", "mmio-sram"; - reg = <0xf8044000 0x1420>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 51>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0xf8044000 0x1420>; - }; - - reset_controller: rstc@f8048000 { - compatible = "atmel,sama5d3-rstc"; - reg = <0xf8048000 0x10>; - clocks = <&clk32k>; - }; - - shutdown_controller: shdwc@f8048010 { - compatible = "atmel,sama5d2-shdwc"; - reg = <0xf8048010 0x10>; - clocks = <&clk32k>; - #address-cells = <1>; - #size-cells = <0>; - atmel,wakeup-rtc-timer; - }; - - pit: timer@f8048030 { - compatible = "atmel,at91sam9260-pit"; - reg = <0xf8048030 0x10>; - interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>; - clocks = <&pmc PMC_TYPE_CORE PMC_MCK2>; - }; - - watchdog: watchdog@f8048040 { - compatible = "atmel,sama5d4-wdt"; - reg = <0xf8048040 0x10>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&clk32k>; - status = "disabled"; - }; - - clk32k: sckc@f8048050 { - compatible = "atmel,sama5d4-sckc"; - reg = <0xf8048050 0x4>; - - clocks = <&slow_xtal>; - #clock-cells = <0>; - }; - - rtc: rtc@f80480b0 { - compatible = "atmel,at91rm9200-rtc"; - reg = <0xf80480b0 0x30>; - interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&clk32k>; - }; - - i2s0: i2s@f8050000 { - compatible = "atmel,sama5d2-i2s"; - reg = <0xf8050000 0x100>; - interrupts = <54 IRQ_TYPE_LEVEL_HIGH 7>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(31))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(32))>; - dma-names = "tx", "rx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 54>, <&pmc PMC_TYPE_GCK 54>; - clock-names = "pclk", "gclk"; - assigned-clocks = <&pmc PMC_TYPE_CORE PMC_I2S0_MUX>; - assigned-clock-parents = <&pmc PMC_TYPE_GCK 54>; - status = "disabled"; - }; - - can0: can@f8054000 { - compatible = "bosch,m_can"; - reg = <0xf8054000 0x4000>, <0x210000 0x4000>; - reg-names = "m_can", "message_ram"; - interrupts = <56 IRQ_TYPE_LEVEL_HIGH 7>, - <64 IRQ_TYPE_LEVEL_HIGH 7>; - interrupt-names = "int0", "int1"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 56>, <&pmc PMC_TYPE_GCK 56>; - clock-names = "hclk", "cclk"; - assigned-clocks = <&pmc PMC_TYPE_GCK 56>; - assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; - assigned-clock-rates = <40000000>; - bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>; - status = "disabled"; - }; - - spi1: spi@fc000000 { - compatible = "atmel,at91rm9200-spi"; - reg = <0xfc000000 0x100>; - interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(8))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(9))>; - dma-names = "tx", "rx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 34>; - clock-names = "spi_clk"; - atmel,fifo-size = <16>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - uart3: serial@fc008000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xfc008000 0x100>; - interrupts = <27 IRQ_TYPE_LEVEL_HIGH 7>; - dmas = <&dma1 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(41))>, - <&dma1 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(42))>; - dma-names = "tx", "rx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 27>; - clock-names = "usart"; - status = "disabled"; - }; - - uart4: serial@fc00c000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xfc00c000 0x100>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(43))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(44))>; - dma-names = "tx", "rx"; - interrupts = <28 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 28>; - clock-names = "usart"; - status = "disabled"; - }; - - flx2: flexcom@fc010000 { - compatible = "atmel,sama5d2-flexcom"; - reg = <0xfc010000 0x200>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xfc010000 0x800>; - status = "disabled"; - }; - - flx3: flexcom@fc014000 { - compatible = "atmel,sama5d2-flexcom"; - reg = <0xfc014000 0x200>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xfc014000 0x800>; - status = "disabled"; - }; - - flx4: flexcom@fc018000 { - compatible = "atmel,sama5d2-flexcom"; - reg = <0xfc018000 0x200>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xfc018000 0x800>; - status = "disabled"; - }; - - trng@fc01c000 { - compatible = "atmel,at91sam9g45-trng"; - reg = <0xfc01c000 0x100>; - interrupts = <47 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 47>; - }; - - aic: interrupt-controller@fc020000 { - #interrupt-cells = <3>; - compatible = "atmel,sama5d2-aic"; - interrupt-controller; - reg = <0xfc020000 0x200>; - atmel,external-irqs = <49>; - }; - - i2c1: i2c@fc028000 { - compatible = "atmel,sama5d2-i2c"; - reg = <0xfc028000 0x100>; - interrupts = <30 IRQ_TYPE_LEVEL_HIGH 7>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(2))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(3))>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 30>; - atmel,fifo-size = <16>; - status = "disabled"; - }; - - adc: adc@fc030000 { - compatible = "atmel,sama5d2-adc"; - reg = <0xfc030000 0x100>; - interrupts = <40 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 40>; - clock-names = "adc_clk"; - dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(25))>; - dma-names = "rx"; - atmel,min-sample-rate-hz = <200000>; - atmel,max-sample-rate-hz = <20000000>; - atmel,startup-time-ms = <4>; - atmel,trigger-edge-type = ; - #io-channel-cells = <1>; - status = "disabled"; - }; - - resistive_touch: resistive-touch { - compatible = "resistive-adc-touch"; - io-channels = <&adc AT91_SAMA5D2_ADC_X_CHANNEL>, - <&adc AT91_SAMA5D2_ADC_Y_CHANNEL>, - <&adc AT91_SAMA5D2_ADC_P_CHANNEL>; - io-channel-names = "x", "y", "pressure"; - touchscreen-min-pressure = <50000>; - status = "disabled"; - }; - - pioA: pinctrl@fc038000 { - compatible = "atmel,sama5d2-pinctrl"; - reg = <0xfc038000 0x600>; - interrupts = <18 IRQ_TYPE_LEVEL_HIGH 7>, - <68 IRQ_TYPE_LEVEL_HIGH 7>, - <69 IRQ_TYPE_LEVEL_HIGH 7>, - <70 IRQ_TYPE_LEVEL_HIGH 7>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 18>; - }; - - pioBU: secumod@fc040000 { - compatible = "atmel,sama5d2-secumod", "syscon"; - reg = <0xfc040000 0x100>; - - gpio-controller; - #gpio-cells = <2>; - }; - - tdes@fc044000 { - compatible = "atmel,at91sam9g46-tdes"; - reg = <0xfc044000 0x100>; - interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(28))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(29))>; - dma-names = "tx", "rx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; - clock-names = "tdes_clk"; - status = "okay"; - }; - - classd: classd@fc048000 { - compatible = "atmel,sama5d2-classd"; - reg = <0xfc048000 0x100>; - interrupts = <59 IRQ_TYPE_LEVEL_HIGH 7>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(47))>; - dma-names = "tx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 59>, <&pmc PMC_TYPE_GCK 59>; - clock-names = "pclk", "gclk"; - status = "disabled"; - }; - - i2s1: i2s@fc04c000 { - compatible = "atmel,sama5d2-i2s"; - reg = <0xfc04c000 0x100>; - interrupts = <55 IRQ_TYPE_LEVEL_HIGH 7>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(33))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(34))>; - dma-names = "tx", "rx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 55>, <&pmc PMC_TYPE_GCK 55>; - clock-names = "pclk", "gclk"; - assigned-clocks = <&pmc PMC_TYPE_CORE PMC_I2S1_MUX>; - assigned-parrents = <&pmc PMC_TYPE_GCK 55>; - status = "disabled"; - }; - - can1: can@fc050000 { - compatible = "bosch,m_can"; - reg = <0xfc050000 0x4000>, <0x210000 0x4000>; - reg-names = "m_can", "message_ram"; - interrupts = <57 IRQ_TYPE_LEVEL_HIGH 7>, - <65 IRQ_TYPE_LEVEL_HIGH 7>; - interrupt-names = "int0", "int1"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 57>, <&pmc PMC_TYPE_GCK 57>; - clock-names = "hclk", "cclk"; - assigned-clocks = <&pmc PMC_TYPE_GCK 57>; - assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; - assigned-clock-rates = <40000000>; - bosch,mram-cfg = <0x1100 0 0 64 0 0 32 32>; - status = "disabled"; - }; - - sfrbu: sfr@fc05c000 { - compatible = "atmel,sama5d2-sfrbu", "syscon"; - reg = <0xfc05c000 0x20>; - }; - - chipid@fc069000 { - compatible = "atmel,sama5d2-chipid"; - reg = <0xfc069000 0x8>; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/sama5d3.dtsi b/sys/gnu/dts/arm/sama5d3.dtsi deleted file mode 100644 index 203d40be70a..00000000000 --- a/sys/gnu/dts/arm/sama5d3.dtsi +++ /dev/null @@ -1,1561 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * sama5d3.dtsi - Device Tree Include file for SAMA5D3 family SoC - * applies to SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35, SAMA5D36 SoC - * - * Copyright (C) 2013 Atmel, - * 2013 Ludovic Desroches - */ - -#include -#include -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - model = "Atmel SAMA5D3 family SoC"; - compatible = "atmel,sama5d3", "atmel,sama5"; - interrupt-parent = <&aic>; - - aliases { - serial0 = &dbgu; - serial1 = &usart0; - serial2 = &usart1; - serial3 = &usart2; - serial4 = &usart3; - serial5 = &uart0; - gpio0 = &pioA; - gpio1 = &pioB; - gpio2 = &pioC; - gpio3 = &pioD; - gpio4 = &pioE; - tcb0 = &tcb0; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - ssc0 = &ssc0; - ssc1 = &ssc1; - pwm0 = &pwm0; - }; - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a5"; - reg = <0x0>; - }; - }; - - pmu { - compatible = "arm,cortex-a5-pmu"; - interrupts = <46 IRQ_TYPE_LEVEL_HIGH 0>; - }; - - memory { - device_type = "memory"; - reg = <0x20000000 0x8000000>; - }; - - clocks { - slow_xtal: slow_xtal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - main_xtal: main_xtal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - adc_op_clk: adc_op_clk{ - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <1000000>; - }; - }; - - sram: sram@300000 { - compatible = "mmio-sram"; - reg = <0x00300000 0x20000>; - }; - - ahb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - apb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - mmc0: mmc@f0000000 { - compatible = "atmel,hsmci"; - reg = <0xf0000000 0x600>; - interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>; - dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(0)>; - dma-names = "rxtx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_dat4_7>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&mci0_clk>; - clock-names = "mci_clk"; - }; - - spi0: spi@f0004000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "atmel,at91rm9200-spi"; - reg = <0xf0004000 0x100>; - interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>; - dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(1)>, - <&dma0 2 AT91_DMA_CFG_PER_ID(2)>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi0>; - clocks = <&spi0_clk>; - clock-names = "spi_clk"; - status = "disabled"; - }; - - ssc0: ssc@f0008000 { - compatible = "atmel,at91sam9g45-ssc"; - reg = <0xf0008000 0x4000>; - interrupts = <38 IRQ_TYPE_LEVEL_HIGH 4>; - dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(13)>, - <&dma0 2 AT91_DMA_CFG_PER_ID(14)>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; - clocks = <&ssc0_clk>; - clock-names = "pclk"; - status = "disabled"; - }; - - tcb0: timer@f0010000 { - compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xf0010000 0x100>; - interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tcb0_clk>, <&clk32k>; - clock-names = "t0_clk", "slow_clk"; - }; - - i2c0: i2c@f0014000 { - compatible = "atmel,at91sam9x5-i2c"; - reg = <0xf0014000 0x4000>; - interrupts = <18 IRQ_TYPE_LEVEL_HIGH 6>; - dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(7)>, - <&dma0 2 AT91_DMA_CFG_PER_ID(8)>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&twi0_clk>; - status = "disabled"; - }; - - i2c1: i2c@f0018000 { - compatible = "atmel,at91sam9x5-i2c"; - reg = <0xf0018000 0x4000>; - interrupts = <19 IRQ_TYPE_LEVEL_HIGH 6>; - dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(9)>, - <&dma0 2 AT91_DMA_CFG_PER_ID(10)>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&twi1_clk>; - status = "disabled"; - }; - - usart0: serial@f001c000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xf001c000 0x100>; - interrupts = <12 IRQ_TYPE_LEVEL_HIGH 5>; - dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(3)>, - <&dma0 2 (AT91_DMA_CFG_PER_ID(4) | AT91_DMA_CFG_FIFOCFG_ASAP)>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart0>; - clocks = <&usart0_clk>; - clock-names = "usart"; - status = "disabled"; - }; - - usart1: serial@f0020000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xf0020000 0x100>; - interrupts = <13 IRQ_TYPE_LEVEL_HIGH 5>; - dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(5)>, - <&dma0 2 (AT91_DMA_CFG_PER_ID(6) | AT91_DMA_CFG_FIFOCFG_ASAP)>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart1>; - clocks = <&usart1_clk>; - clock-names = "usart"; - status = "disabled"; - }; - - uart0: serial@f0024000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xf0024000 0x100>; - interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0>; - clocks = <&uart0_clk>; - clock-names = "usart"; - status = "disabled"; - }; - - pwm0: pwm@f002c000 { - compatible = "atmel,sama5d3-pwm"; - reg = <0xf002c000 0x300>; - interrupts = <28 IRQ_TYPE_LEVEL_HIGH 4>; - #pwm-cells = <3>; - clocks = <&pwm_clk>; - status = "disabled"; - }; - - isi: isi@f0034000 { - compatible = "atmel,at91sam9g45-isi"; - reg = <0xf0034000 0x4000>; - interrupts = <37 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_isi_data_0_7>; - clocks = <&isi_clk>; - clock-names = "isi_clk"; - status = "disabled"; - port { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - sfr: sfr@f0038000 { - compatible = "atmel,sama5d3-sfr", "syscon"; - reg = <0xf0038000 0x60>; - }; - - mmc1: mmc@f8000000 { - compatible = "atmel,hsmci"; - reg = <0xf8000000 0x600>; - interrupts = <22 IRQ_TYPE_LEVEL_HIGH 0>; - dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(0)>; - dma-names = "rxtx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&mci1_clk>; - clock-names = "mci_clk"; - }; - - spi1: spi@f8008000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "atmel,at91rm9200-spi"; - reg = <0xf8008000 0x100>; - interrupts = <25 IRQ_TYPE_LEVEL_HIGH 3>; - dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(15)>, - <&dma1 2 AT91_DMA_CFG_PER_ID(16)>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1>; - clocks = <&spi1_clk>; - clock-names = "spi_clk"; - status = "disabled"; - }; - - ssc1: ssc@f800c000 { - compatible = "atmel,at91sam9g45-ssc"; - reg = <0xf800c000 0x4000>; - interrupts = <39 IRQ_TYPE_LEVEL_HIGH 4>; - dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(3)>, - <&dma1 2 AT91_DMA_CFG_PER_ID(4)>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; - clocks = <&ssc1_clk>; - clock-names = "pclk"; - status = "disabled"; - }; - - adc0: adc@f8018000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "atmel,at91sam9x5-adc"; - reg = <0xf8018000 0x100>; - interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = < - &pinctrl_adc0_adtrg - &pinctrl_adc0_ad0 - &pinctrl_adc0_ad1 - &pinctrl_adc0_ad2 - &pinctrl_adc0_ad3 - &pinctrl_adc0_ad4 - &pinctrl_adc0_ad5 - &pinctrl_adc0_ad6 - &pinctrl_adc0_ad7 - &pinctrl_adc0_ad8 - &pinctrl_adc0_ad9 - &pinctrl_adc0_ad10 - &pinctrl_adc0_ad11 - >; - clocks = <&adc_clk>, - <&adc_op_clk>; - clock-names = "adc_clk", "adc_op_clk"; - atmel,adc-channels-used = <0xfff>; - atmel,adc-startup-time = <40>; - atmel,adc-use-external-triggers; - atmel,adc-vref = <3000>; - atmel,adc-res = <10 12>; - atmel,adc-sample-hold-time = <11>; - atmel,adc-res-names = "lowres", "highres"; - status = "disabled"; - - trigger0 { - trigger-name = "external-rising"; - trigger-value = <0x1>; - trigger-external; - }; - trigger1 { - trigger-name = "external-falling"; - trigger-value = <0x2>; - trigger-external; - }; - trigger2 { - trigger-name = "external-any"; - trigger-value = <0x3>; - trigger-external; - }; - trigger3 { - trigger-name = "continuous"; - trigger-value = <0x6>; - }; - }; - - i2c2: i2c@f801c000 { - compatible = "atmel,at91sam9x5-i2c"; - reg = <0xf801c000 0x4000>; - interrupts = <20 IRQ_TYPE_LEVEL_HIGH 6>; - dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(11)>, - <&dma1 2 AT91_DMA_CFG_PER_ID(12)>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&twi2_clk>; - status = "disabled"; - }; - - usart2: serial@f8020000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xf8020000 0x100>; - interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>; - dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(7)>, - <&dma1 2 (AT91_DMA_CFG_PER_ID(8) | AT91_DMA_CFG_FIFOCFG_ASAP)>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart2>; - clocks = <&usart2_clk>; - clock-names = "usart"; - status = "disabled"; - }; - - usart3: serial@f8024000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xf8024000 0x100>; - interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>; - dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(9)>, - <&dma1 2 (AT91_DMA_CFG_PER_ID(10) | AT91_DMA_CFG_FIFOCFG_ASAP)>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart3>; - clocks = <&usart3_clk>; - clock-names = "usart"; - status = "disabled"; - }; - - sha@f8034000 { - compatible = "atmel,at91sam9g46-sha"; - reg = <0xf8034000 0x100>; - interrupts = <42 IRQ_TYPE_LEVEL_HIGH 0>; - dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(17)>; - dma-names = "tx"; - clocks = <&sha_clk>; - clock-names = "sha_clk"; - }; - - aes@f8038000 { - compatible = "atmel,at91sam9g46-aes"; - reg = <0xf8038000 0x100>; - interrupts = <43 IRQ_TYPE_LEVEL_HIGH 0>; - dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(18)>, - <&dma1 2 AT91_DMA_CFG_PER_ID(19)>; - dma-names = "tx", "rx"; - clocks = <&aes_clk>; - clock-names = "aes_clk"; - }; - - tdes@f803c000 { - compatible = "atmel,at91sam9g46-tdes"; - reg = <0xf803c000 0x100>; - interrupts = <44 IRQ_TYPE_LEVEL_HIGH 0>; - dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(20)>, - <&dma1 2 AT91_DMA_CFG_PER_ID(21)>; - dma-names = "tx", "rx"; - clocks = <&tdes_clk>; - clock-names = "tdes_clk"; - }; - - trng@f8040000 { - compatible = "atmel,at91sam9g45-trng"; - reg = <0xf8040000 0x100>; - interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&trng_clk>; - }; - - hsmc: hsmc@ffffc000 { - compatible = "atmel,sama5d3-smc", "syscon", "simple-mfd"; - reg = <0xffffc000 0x1000>; - interrupts = <5 IRQ_TYPE_LEVEL_HIGH 6>; - clocks = <&hsmc_clk>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - pmecc: ecc-engine@ffffc070 { - compatible = "atmel,at91sam9g45-pmecc"; - reg = <0xffffc070 0x490>, - <0xffffc500 0x100>; - }; - }; - - dma0: dma-controller@ffffe600 { - compatible = "atmel,at91sam9g45-dma"; - reg = <0xffffe600 0x200>; - interrupts = <30 IRQ_TYPE_LEVEL_HIGH 0>; - #dma-cells = <2>; - clocks = <&dma0_clk>; - clock-names = "dma_clk"; - }; - - dma1: dma-controller@ffffe800 { - compatible = "atmel,at91sam9g45-dma"; - reg = <0xffffe800 0x200>; - interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>; - #dma-cells = <2>; - clocks = <&dma1_clk>; - clock-names = "dma_clk"; - }; - - ramc0: ramc@ffffea00 { - compatible = "atmel,sama5d3-ddramc"; - reg = <0xffffea00 0x200>; - clocks = <&ddrck>, <&mpddr_clk>; - clock-names = "ddrck", "mpddr"; - }; - - dbgu: serial@ffffee00 { - compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; - reg = <0xffffee00 0x200>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>; - dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(13)>, - <&dma1 2 (AT91_DMA_CFG_PER_ID(14) | AT91_DMA_CFG_FIFOCFG_ASAP)>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_dbgu>; - clocks = <&dbgu_clk>; - clock-names = "usart"; - status = "disabled"; - }; - - aic: interrupt-controller@fffff000 { - #interrupt-cells = <3>; - compatible = "atmel,sama5d3-aic"; - interrupt-controller; - reg = <0xfffff000 0x200>; - atmel,external-irqs = <47>; - }; - - pinctrl: pinctrl@fffff200 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "atmel,sama5d3-pinctrl", "atmel,at91sam9x5-pinctrl", "simple-bus"; - ranges = <0xfffff200 0xfffff200 0xa00>; - atmel,mux-mask = < - /* A B C */ - 0xffffffff 0xc0fc0000 0xc0ff0000 /* pioA */ - 0xffffffff 0x0ff8ffff 0x00000000 /* pioB */ - 0xffffffff 0xbc00f1ff 0x7c00fc00 /* pioC */ - 0xffffffff 0xc001c0e0 0x0001c1e0 /* pioD */ - 0xffffffff 0xbf9f8000 0x18000000 /* pioE */ - >; - - /* shared pinctrl settings */ - adc0 { - pinctrl_adc0_adtrg: adc0_adtrg { - atmel,pins = - ; /* PD19 periph A ADTRG */ - }; - pinctrl_adc0_ad0: adc0_ad0 { - atmel,pins = - ; /* PD20 periph A AD0 */ - }; - pinctrl_adc0_ad1: adc0_ad1 { - atmel,pins = - ; /* PD21 periph A AD1 */ - }; - pinctrl_adc0_ad2: adc0_ad2 { - atmel,pins = - ; /* PD22 periph A AD2 */ - }; - pinctrl_adc0_ad3: adc0_ad3 { - atmel,pins = - ; /* PD23 periph A AD3 */ - }; - pinctrl_adc0_ad4: adc0_ad4 { - atmel,pins = - ; /* PD24 periph A AD4 */ - }; - pinctrl_adc0_ad5: adc0_ad5 { - atmel,pins = - ; /* PD25 periph A AD5 */ - }; - pinctrl_adc0_ad6: adc0_ad6 { - atmel,pins = - ; /* PD26 periph A AD6 */ - }; - pinctrl_adc0_ad7: adc0_ad7 { - atmel,pins = - ; /* PD27 periph A AD7 */ - }; - pinctrl_adc0_ad8: adc0_ad8 { - atmel,pins = - ; /* PD28 periph A AD8 */ - }; - pinctrl_adc0_ad9: adc0_ad9 { - atmel,pins = - ; /* PD29 periph A AD9 */ - }; - pinctrl_adc0_ad10: adc0_ad10 { - atmel,pins = - ; /* PD30 periph A AD10, conflicts with PCK0 */ - }; - pinctrl_adc0_ad11: adc0_ad11 { - atmel,pins = - ; /* PD31 periph A AD11, conflicts with PCK1 */ - }; - }; - - dbgu { - pinctrl_dbgu: dbgu-0 { - atmel,pins = - ; - }; - }; - - ebi { - pinctrl_ebi_addr: ebi-addr-0 { - atmel,pins = - ; - }; - - pinctrl_ebi_nand_addr: ebi-addr-1 { - atmel,pins = - ; - }; - - pinctrl_ebi_cs0: ebi-cs0-0 { - atmel,pins = - ; - }; - - pinctrl_ebi_cs1: ebi-cs1-0 { - atmel,pins = - ; - }; - - pinctrl_ebi_cs2: ebi-cs2-0 { - atmel,pins = - ; - }; - - pinctrl_ebi_nwait: ebi-nwait-0 { - atmel,pins = - ; - }; - - pinctrl_ebi_nwr1_nbs1: ebi-nwr1-nbs1-0 { - atmel,pins = - ; - }; - }; - - i2c0 { - pinctrl_i2c0: i2c0-0 { - atmel,pins = - ; /* PA31 periph A TWCK0 pin, conflicts with UTXD1, ISI_HSYNC */ - }; - }; - - i2c1 { - pinctrl_i2c1: i2c1-0 { - atmel,pins = - ; /* PC27 periph B TWCK1 pin, conflicts with SPI1_NPCS2, ISI_D10 */ - }; - }; - - i2c2 { - pinctrl_i2c2: i2c2-0 { - atmel,pins = - ; /* TWCK2 pin, conflicts with LCDDAT19, ISI_D3 */ - }; - }; - - isi { - pinctrl_isi_data_0_7: isi-0-data-0-7 { - atmel,pins = - ; /* PA30 periph C ISI_VSYNC, conflicts with TWD0, URXD1 */ - }; - - pinctrl_isi_data_8_9: isi-0-data-8-9 { - atmel,pins = - ; /* PC28 periph C ISI_PD9, conflicts with SPI1_NPCS3, PWMFI0 */ - }; - - pinctrl_isi_data_10_11: isi-0-data-10-11 { - atmel,pins = - ; /* PC26 periph C ISI_PD11, conflicts with SPI1_NPCS1, TWD1 */ - }; - }; - - mmc0 { - pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 { - atmel,pins = - ; /* PD1 periph A MCI0_DA0 with pullup */ - }; - pinctrl_mmc0_dat1_3: mmc0_dat1_3 { - atmel,pins = - ; /* PD4 periph A MCI0_DA3 with pullup */ - }; - pinctrl_mmc0_dat4_7: mmc0_dat4_7 { - atmel,pins = - ; /* PD8 periph A MCI0_DA7 with pullup, conflicts with PWML3 */ - }; - }; - - mmc1 { - pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 { - atmel,pins = - ; /* PB20 periph A MCI1_DA0 with pullup, conflicts with GTX5 */ - }; - pinctrl_mmc1_dat1_3: mmc1_dat1_3 { - atmel,pins = - ; /* PB23 periph A MCI1_DA3 with pullup, conflicts with GRX4 */ - }; - }; - - nand0 { - pinctrl_nand0_ale_cle: nand0_ale_cle-0 { - atmel,pins = - ; /* PE22 periph A with pullup */ - }; - }; - - pwm0 { - pinctrl_pwm0_pwmh0_0: pwm0_pwmh0-0 { - atmel,pins = - ; /* conflicts with ISI_D4 and LCDDAT20 */ - }; - pinctrl_pwm0_pwmh0_1: pwm0_pwmh0-1 { - atmel,pins = - ; /* conflicts with GTX0 */ - }; - pinctrl_pwm0_pwml0_0: pwm0_pwml0-0 { - atmel,pins = - ; /* conflicts with ISI_D5 and LCDDAT21 */ - }; - pinctrl_pwm0_pwml0_1: pwm0_pwml0-1 { - atmel,pins = - ; /* conflicts with GTX1 */ - }; - - pinctrl_pwm0_pwmh1_0: pwm0_pwmh1-0 { - atmel,pins = - ; /* conflicts with ISI_D6 and LCDDAT22 */ - }; - pinctrl_pwm0_pwmh1_1: pwm0_pwmh1-1 { - atmel,pins = - ; /* conflicts with GRX0 */ - }; - pinctrl_pwm0_pwmh1_2: pwm0_pwmh1-2 { - atmel,pins = - ; /* conflicts with G125CKO and RTS1 */ - }; - pinctrl_pwm0_pwml1_0: pwm0_pwml1-0 { - atmel,pins = - ; /* conflicts with ISI_D7 and LCDDAT23 */ - }; - pinctrl_pwm0_pwml1_1: pwm0_pwml1-1 { - atmel,pins = - ; /* conflicts with GRX1 */ - }; - pinctrl_pwm0_pwml1_2: pwm0_pwml1-2 { - atmel,pins = - ; /* conflicts with IRQ */ - }; - - pinctrl_pwm0_pwmh2_0: pwm0_pwmh2-0 { - atmel,pins = - ; /* conflicts with GTXCK */ - }; - pinctrl_pwm0_pwmh2_1: pwm0_pwmh2-1 { - atmel,pins = - ; /* conflicts with MCI0_DA4 and TIOA0 */ - }; - pinctrl_pwm0_pwml2_0: pwm0_pwml2-0 { - atmel,pins = - ; /* conflicts with GTXEN */ - }; - pinctrl_pwm0_pwml2_1: pwm0_pwml2-1 { - atmel,pins = - ; /* conflicts with MCI0_DA5 and TIOB0 */ - }; - - pinctrl_pwm0_pwmh3_0: pwm0_pwmh3-0 { - atmel,pins = - ; /* conflicts with GRXDV */ - }; - pinctrl_pwm0_pwmh3_1: pwm0_pwmh3-1 { - atmel,pins = - ; /* conflicts with MCI0_DA6 and TCLK0 */ - }; - pinctrl_pwm0_pwml3_0: pwm0_pwml3-0 { - atmel,pins = - ; /* conflicts with GRXER */ - }; - pinctrl_pwm0_pwml3_1: pwm0_pwml3-1 { - atmel,pins = - ; /* conflicts with MCI0_DA7 */ - }; - }; - - spi0 { - pinctrl_spi0: spi0-0 { - atmel,pins = - ; /* PD12 periph A SPI0_SPCK pin */ - }; - }; - - spi1 { - pinctrl_spi1: spi1-0 { - atmel,pins = - ; /* PC24 periph A SPI1_SPCK pin */ - }; - }; - - ssc0 { - pinctrl_ssc0_tx: ssc0_tx { - atmel,pins = - ; /* PC18 periph A TD0 */ - }; - - pinctrl_ssc0_rx: ssc0_rx { - atmel,pins = - ; /* PC21 periph A RD0 */ - }; - }; - - ssc1 { - pinctrl_ssc1_tx: ssc1_tx { - atmel,pins = - ; /* PB6 periph B TD1, conflicts with TD1 */ - }; - - pinctrl_ssc1_rx: ssc1_rx { - atmel,pins = - ; /* PB11 periph B RD1, conflicts with GRXCK */ - }; - }; - - uart0 { - pinctrl_uart0: uart0-0 { - atmel,pins = - ; /* conflicts with ISI_PCK */ - }; - }; - - uart1 { - pinctrl_uart1: uart1-0 { - atmel,pins = - ; /* conflicts with TWCK0, ISI_HSYNC */ - }; - }; - - usart0 { - pinctrl_usart0: usart0-0 { - atmel,pins = - ; - }; - - pinctrl_usart0_rts_cts: usart0_rts_cts-0 { - atmel,pins = - ; /* PD16 periph A, conflicts with SPI0_NPCS3, PWMFI3 */ - }; - }; - - usart1 { - pinctrl_usart1: usart1-0 { - atmel,pins = - ; - }; - - pinctrl_usart1_rts_cts: usart1_rts_cts-0 { - atmel,pins = - ; /* PB27 periph A, conflicts with G125CKO */ - }; - }; - - usart2 { - pinctrl_usart2: usart2-0 { - atmel,pins = - ; /* conflicts NCS0 */ - }; - - pinctrl_usart2_rts_cts: usart2_rts_cts-0 { - atmel,pins = - ; /* PE24 periph B, conflicts with A24 */ - }; - }; - - usart3 { - pinctrl_usart3: usart3-0 { - atmel,pins = - ; /* conflicts with A19 */ - }; - - pinctrl_usart3_rts_cts: usart3_rts_cts-0 { - atmel,pins = - ; /* PE17 periph B, conflicts with A17 */ - }; - }; - - - pioA: gpio@fffff200 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfffff200 0x100>; - interrupts = <6 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioA_clk>; - }; - - pioB: gpio@fffff400 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfffff400 0x100>; - interrupts = <7 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioB_clk>; - }; - - pioC: gpio@fffff600 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfffff600 0x100>; - interrupts = <8 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioC_clk>; - }; - - pioD: gpio@fffff800 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfffff800 0x100>; - interrupts = <9 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioD_clk>; - }; - - pioE: gpio@fffffa00 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfffffa00 0x100>; - interrupts = <10 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioE_clk>; - }; - }; - - pmc: pmc@fffffc00 { - compatible = "atmel,sama5d3-pmc", "syscon"; - reg = <0xfffffc00 0x120>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - interrupt-controller; - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - - main_rc_osc: main_rc_osc { - compatible = "atmel,at91sam9x5-clk-main-rc-osc"; - #clock-cells = <0>; - interrupt-parent = <&pmc>; - interrupts = ; - clock-frequency = <12000000>; - clock-accuracy = <50000000>; - }; - - main_osc: main_osc { - compatible = "atmel,at91rm9200-clk-main-osc"; - #clock-cells = <0>; - interrupt-parent = <&pmc>; - interrupts = ; - clocks = <&main_xtal>; - }; - - main: mainck { - compatible = "atmel,at91sam9x5-clk-main"; - #clock-cells = <0>; - interrupt-parent = <&pmc>; - interrupts = ; - clocks = <&main_rc_osc &main_osc>; - }; - - plla: pllack { - compatible = "atmel,sama5d3-clk-pll"; - #clock-cells = <0>; - interrupt-parent = <&pmc>; - interrupts = ; - clocks = <&main>; - reg = <0>; - atmel,clk-input-range = <8000000 50000000>; - #atmel,pll-clk-output-range-cells = <4>; - atmel,pll-clk-output-ranges = <400000000 1000000000 0 0>; - }; - - plladiv: plladivck { - compatible = "atmel,at91sam9x5-clk-plldiv"; - #clock-cells = <0>; - clocks = <&plla>; - }; - - utmi: utmick { - compatible = "atmel,at91sam9x5-clk-utmi"; - #clock-cells = <0>; - interrupt-parent = <&pmc>; - interrupts = ; - clocks = <&main>; - }; - - mck: masterck { - compatible = "atmel,at91sam9x5-clk-master"; - #clock-cells = <0>; - interrupt-parent = <&pmc>; - interrupts = ; - clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>; - atmel,clk-output-range = <0 166000000>; - atmel,clk-divisors = <1 2 4 3>; - }; - - usb: usbck { - compatible = "atmel,at91sam9x5-clk-usb"; - #clock-cells = <0>; - clocks = <&plladiv>, <&utmi>; - }; - - prog: progck { - compatible = "atmel,at91sam9x5-clk-programmable"; - #address-cells = <1>; - #size-cells = <0>; - interrupt-parent = <&pmc>; - clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>; - - prog0: prog0 { - #clock-cells = <0>; - reg = <0>; - interrupts = ; - }; - - prog1: prog1 { - #clock-cells = <0>; - reg = <1>; - interrupts = ; - }; - - prog2: prog2 { - #clock-cells = <0>; - reg = <2>; - interrupts = ; - }; - }; - - smd: smdclk { - compatible = "atmel,at91sam9x5-clk-smd"; - #clock-cells = <0>; - clocks = <&plladiv>, <&utmi>; - }; - - systemck { - compatible = "atmel,at91rm9200-clk-system"; - #address-cells = <1>; - #size-cells = <0>; - - ddrck: ddrck { - #clock-cells = <0>; - reg = <2>; - clocks = <&mck>; - }; - - smdck: smdck { - #clock-cells = <0>; - reg = <4>; - clocks = <&smd>; - }; - - uhpck: uhpck { - #clock-cells = <0>; - reg = <6>; - clocks = <&usb>; - }; - - udpck: udpck { - #clock-cells = <0>; - reg = <7>; - clocks = <&usb>; - }; - - pck0: pck0 { - #clock-cells = <0>; - reg = <8>; - clocks = <&prog0>; - }; - - pck1: pck1 { - #clock-cells = <0>; - reg = <9>; - clocks = <&prog1>; - }; - - pck2: pck2 { - #clock-cells = <0>; - reg = <10>; - clocks = <&prog2>; - }; - }; - - periphck { - compatible = "atmel,at91sam9x5-clk-peripheral"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&mck>; - - dbgu_clk: dbgu_clk { - #clock-cells = <0>; - reg = <2>; - }; - - hsmc_clk: hsmc_clk { - #clock-cells = <0>; - reg = <5>; - }; - - pioA_clk: pioA_clk { - #clock-cells = <0>; - reg = <6>; - }; - - pioB_clk: pioB_clk { - #clock-cells = <0>; - reg = <7>; - }; - - pioC_clk: pioC_clk { - #clock-cells = <0>; - reg = <8>; - }; - - pioD_clk: pioD_clk { - #clock-cells = <0>; - reg = <9>; - }; - - pioE_clk: pioE_clk { - #clock-cells = <0>; - reg = <10>; - }; - - usart0_clk: usart0_clk { - #clock-cells = <0>; - reg = <12>; - atmel,clk-output-range = <0 83000000>; - }; - - usart1_clk: usart1_clk { - #clock-cells = <0>; - reg = <13>; - atmel,clk-output-range = <0 83000000>; - }; - - usart2_clk: usart2_clk { - #clock-cells = <0>; - reg = <14>; - atmel,clk-output-range = <0 83000000>; - }; - - usart3_clk: usart3_clk { - #clock-cells = <0>; - reg = <15>; - atmel,clk-output-range = <0 83000000>; - }; - - uart0_clk: uart0_clk { - #clock-cells = <0>; - reg = <16>; - atmel,clk-output-range = <0 83000000>; - }; - - twi0_clk: twi0_clk { - reg = <18>; - #clock-cells = <0>; - atmel,clk-output-range = <0 41500000>; - }; - - twi1_clk: twi1_clk { - #clock-cells = <0>; - reg = <19>; - atmel,clk-output-range = <0 41500000>; - }; - - twi2_clk: twi2_clk { - #clock-cells = <0>; - reg = <20>; - atmel,clk-output-range = <0 41500000>; - }; - - mci0_clk: mci0_clk { - #clock-cells = <0>; - reg = <21>; - }; - - mci1_clk: mci1_clk { - #clock-cells = <0>; - reg = <22>; - }; - - spi0_clk: spi0_clk { - #clock-cells = <0>; - reg = <24>; - atmel,clk-output-range = <0 166000000>; - }; - - spi1_clk: spi1_clk { - #clock-cells = <0>; - reg = <25>; - atmel,clk-output-range = <0 166000000>; - }; - - tcb0_clk: tcb0_clk { - #clock-cells = <0>; - reg = <26>; - atmel,clk-output-range = <0 166000000>; - }; - - pwm_clk: pwm_clk { - #clock-cells = <0>; - reg = <28>; - }; - - adc_clk: adc_clk { - #clock-cells = <0>; - reg = <29>; - atmel,clk-output-range = <0 83000000>; - }; - - dma0_clk: dma0_clk { - #clock-cells = <0>; - reg = <30>; - }; - - dma1_clk: dma1_clk { - #clock-cells = <0>; - reg = <31>; - }; - - uhphs_clk: uhphs_clk { - #clock-cells = <0>; - reg = <32>; - }; - - udphs_clk: udphs_clk { - #clock-cells = <0>; - reg = <33>; - }; - - isi_clk: isi_clk { - #clock-cells = <0>; - reg = <37>; - }; - - ssc0_clk: ssc0_clk { - #clock-cells = <0>; - reg = <38>; - atmel,clk-output-range = <0 83000000>; - }; - - ssc1_clk: ssc1_clk { - #clock-cells = <0>; - reg = <39>; - atmel,clk-output-range = <0 83000000>; - }; - - sha_clk: sha_clk { - #clock-cells = <0>; - reg = <42>; - }; - - aes_clk: aes_clk { - #clock-cells = <0>; - reg = <43>; - }; - - tdes_clk: tdes_clk { - #clock-cells = <0>; - reg = <44>; - }; - - trng_clk: trng_clk { - #clock-cells = <0>; - reg = <45>; - }; - - fuse_clk: fuse_clk { - #clock-cells = <0>; - reg = <48>; - }; - - mpddr_clk: mpddr_clk { - #clock-cells = <0>; - reg = <49>; - }; - }; - }; - - reset_controller: rstc@fffffe00 { - compatible = "atmel,sama5d3-rstc", "atmel,at91sam9g45-rstc"; - reg = <0xfffffe00 0x10>; - clocks = <&clk32k>; - }; - - shutdown_controller: shutdown-controller@fffffe10 { - compatible = "atmel,at91sam9x5-shdwc"; - reg = <0xfffffe10 0x10>; - clocks = <&clk32k>; - }; - - pit: timer@fffffe30 { - compatible = "atmel,at91sam9260-pit"; - reg = <0xfffffe30 0xf>; - interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>; - clocks = <&mck>; - }; - - watchdog: watchdog@fffffe40 { - compatible = "atmel,at91sam9260-wdt"; - reg = <0xfffffe40 0x10>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&clk32k>; - atmel,watchdog-type = "hardware"; - atmel,reset-type = "all"; - atmel,dbg-halt; - status = "disabled"; - }; - - clk32k: sckc@fffffe50 { - compatible = "atmel,sama5d3-sckc"; - reg = <0xfffffe50 0x4>; - clocks = <&slow_xtal>; - #clock-cells = <0>; - }; - - rtc@fffffeb0 { - compatible = "atmel,at91rm9200-rtc"; - reg = <0xfffffeb0 0x30>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&clk32k>; - }; - }; - - nfc_sram: sram@200000 { - compatible = "mmio-sram"; - no-memory-wc; - reg = <0x200000 0x2400>; - }; - - usb0: gadget@500000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "atmel,sama5d3-udc"; - reg = <0x00500000 0x100000 - 0xf8030000 0x4000>; - interrupts = <33 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&udphs_clk>, <&utmi>; - clock-names = "pclk", "hclk"; - status = "disabled"; - - ep@0 { - reg = <0>; - atmel,fifo-size = <64>; - atmel,nb-banks = <1>; - }; - - ep@1 { - reg = <1>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <3>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@2 { - reg = <2>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <3>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@3 { - reg = <3>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-dma; - }; - - ep@4 { - reg = <4>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-dma; - }; - - ep@5 { - reg = <5>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-dma; - }; - - ep@6 { - reg = <6>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-dma; - }; - - ep@7 { - reg = <7>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-dma; - }; - - ep@8 { - reg = <8>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - }; - - ep@9 { - reg = <9>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - }; - - ep@10 { - reg = <10>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - }; - - ep@11 { - reg = <11>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - }; - - ep@12 { - reg = <12>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - }; - - ep@13 { - reg = <13>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - }; - - ep@14 { - reg = <14>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - }; - - ep@15 { - reg = <15>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - }; - }; - - usb1: ohci@600000 { - compatible = "atmel,at91rm9200-ohci", "usb-ohci"; - reg = <0x00600000 0x100000>; - interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>; - clock-names = "ohci_clk", "hclk", "uhpck"; - status = "disabled"; - }; - - usb2: ehci@700000 { - compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; - reg = <0x00700000 0x100000>; - interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&utmi>, <&uhphs_clk>; - clock-names = "usb_clk", "ehci_clk"; - status = "disabled"; - }; - - ebi: ebi@10000000 { - compatible = "atmel,sama5d3-ebi"; - #address-cells = <2>; - #size-cells = <1>; - atmel,smc = <&hsmc>; - reg = <0x10000000 0x10000000 - 0x40000000 0x30000000>; - ranges = <0x0 0x0 0x10000000 0x10000000 - 0x1 0x0 0x40000000 0x10000000 - 0x2 0x0 0x50000000 0x10000000 - 0x3 0x0 0x60000000 0x10000000>; - clocks = <&mck>; - status = "disabled"; - - nand_controller: nand-controller { - compatible = "atmel,sama5d3-nand-controller"; - atmel,nfc-sram = <&nfc_sram>; - atmel,nfc-io = <&nfc_io>; - ecc-engine = <&pmecc>; - #address-cells = <2>; - #size-cells = <1>; - ranges; - status = "disabled"; - }; - }; - - nfc_io: nfc-io@70000000 { - compatible = "atmel,sama5d3-nfc-io", "syscon"; - reg = <0x70000000 0x8000000>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/sama5d31.dtsi b/sys/gnu/dts/arm/sama5d31.dtsi deleted file mode 100644 index cbe8f275ecc..00000000000 --- a/sys/gnu/dts/arm/sama5d31.dtsi +++ /dev/null @@ -1,15 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * sama5d31.dtsi - Device Tree Include file for SAMA5D31 SoC - * - * Copyright (C) 2013 Boris BREZILLON - */ -#include "sama5d3.dtsi" -#include "sama5d3_lcd.dtsi" -#include "sama5d3_emac.dtsi" -#include "sama5d3_mci2.dtsi" -#include "sama5d3_uart.dtsi" - -/ { - compatible = "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5"; -}; diff --git a/sys/gnu/dts/arm/sama5d31ek.dts b/sys/gnu/dts/arm/sama5d31ek.dts deleted file mode 100644 index 10fc80d6d30..00000000000 --- a/sys/gnu/dts/arm/sama5d31ek.dts +++ /dev/null @@ -1,52 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * sama5d31ek.dts - Device Tree file for SAMA5D31-EK board - * - * Copyright (C) 2013 Atmel, - * 2013 Ludovic Desroches - */ -/dts-v1/; -#include "sama5d31.dtsi" -#include "sama5d3xmb.dtsi" -#include "sama5d3xmb_emac.dtsi" -#include "sama5d3xdm.dtsi" - -/ { - model = "Atmel SAMA5D31-EK"; - compatible = "atmel,sama5d31ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5"; - - ahb { - apb { - spi0: spi@f0004000 { - status = "okay"; - }; - - ssc0: ssc@f0008000 { - status = "okay"; - }; - - i2c0: i2c@f0014000 { - status = "okay"; - }; - - i2c1: i2c@f0018000 { - status = "okay"; - }; - - macb1: ethernet@f802c000 { - status = "okay"; - }; - }; - }; - - leds { - d3 { - label = "d3"; - gpios = <&pioE 24 GPIO_ACTIVE_HIGH>; - }; - }; - - sound { - status = "okay"; - }; -}; diff --git a/sys/gnu/dts/arm/sama5d33.dtsi b/sys/gnu/dts/arm/sama5d33.dtsi deleted file mode 100644 index 146fd59acea..00000000000 --- a/sys/gnu/dts/arm/sama5d33.dtsi +++ /dev/null @@ -1,13 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * sama5d33.dtsi - Device Tree Include file for SAMA5D33 SoC - * - * Copyright (C) 2013 Boris BREZILLON - */ -#include "sama5d3.dtsi" -#include "sama5d3_lcd.dtsi" -#include "sama5d3_gmac.dtsi" - -/ { - compatible = "atmel,sama5d33", "atmel,sama5d3", "atmel,sama5"; -}; diff --git a/sys/gnu/dts/arm/sama5d33ek.dts b/sys/gnu/dts/arm/sama5d33ek.dts deleted file mode 100644 index 7d4ae168293..00000000000 --- a/sys/gnu/dts/arm/sama5d33ek.dts +++ /dev/null @@ -1,45 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * sama5d33ek.dts - Device Tree file for SAMA5D33-EK board - * - * Copyright (C) 2013 Atmel, - * 2013 Ludovic Desroches - */ -/dts-v1/; -#include "sama5d33.dtsi" -#include "sama5d3xmb.dtsi" -#include "sama5d3xmb_gmac.dtsi" -#include "sama5d3xdm.dtsi" - -/ { - model = "Atmel SAMA5D33-EK"; - compatible = "atmel,sama5d33ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d33", "atmel,sama5d3", "atmel,sama5"; - - ahb { - apb { - spi0: spi@f0004000 { - status = "okay"; - }; - - ssc0: ssc@f0008000 { - status = "okay"; - }; - - i2c0: i2c@f0014000 { - status = "okay"; - }; - - i2c1: i2c@f0018000 { - status = "okay"; - }; - - macb0: ethernet@f0028000 { - status = "okay"; - }; - }; - }; - - sound { - status = "okay"; - }; -}; diff --git a/sys/gnu/dts/arm/sama5d34.dtsi b/sys/gnu/dts/arm/sama5d34.dtsi deleted file mode 100644 index 132918c889a..00000000000 --- a/sys/gnu/dts/arm/sama5d34.dtsi +++ /dev/null @@ -1,15 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * sama5d34.dtsi - Device Tree Include file for SAMA5D34 SoC - * - * Copyright (C) 2013 Boris BREZILLON - */ -#include "sama5d3.dtsi" -#include "sama5d3_lcd.dtsi" -#include "sama5d3_gmac.dtsi" -#include "sama5d3_can.dtsi" -#include "sama5d3_mci2.dtsi" - -/ { - compatible = "atmel,sama5d34", "atmel,sama5d3", "atmel,sama5"; -}; diff --git a/sys/gnu/dts/arm/sama5d34ek.dts b/sys/gnu/dts/arm/sama5d34ek.dts deleted file mode 100644 index 2335bf906f6..00000000000 --- a/sys/gnu/dts/arm/sama5d34ek.dts +++ /dev/null @@ -1,62 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * sama5d34ek.dts - Device Tree file for SAMA5D34-EK board - * - * Copyright (C) 2013 Atmel, - * 2013 Ludovic Desroches - */ -/dts-v1/; -#include "sama5d34.dtsi" -#include "sama5d3xmb.dtsi" -#include "sama5d3xmb_gmac.dtsi" -#include "sama5d3xdm.dtsi" - -/ { - model = "Atmel SAMA5D34-EK"; - compatible = "atmel,sama5d34ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d34", "atmel,sama5d3", "atmel,sama5"; - - ahb { - apb { - spi0: spi@f0004000 { - status = "okay"; - }; - - ssc0: ssc@f0008000 { - status = "okay"; - }; - - can0: can@f000c000 { - status = "okay"; - }; - - i2c0: i2c@f0014000 { - status = "okay"; - }; - - i2c1: i2c@f0018000 { - status = "okay"; - - 24c256@50 { - compatible = "atmel,24c256"; - reg = <0x50>; - pagesize = <64>; - }; - }; - - macb0: ethernet@f0028000 { - status = "okay"; - }; - }; - }; - - leds { - d3 { - label = "d3"; - gpios = <&pioE 24 GPIO_ACTIVE_HIGH>; - }; - }; - - sound { - status = "okay"; - }; -}; diff --git a/sys/gnu/dts/arm/sama5d35.dtsi b/sys/gnu/dts/arm/sama5d35.dtsi deleted file mode 100644 index b2ccfa77c4b..00000000000 --- a/sys/gnu/dts/arm/sama5d35.dtsi +++ /dev/null @@ -1,17 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * sama5d35.dtsi - Device Tree Include file for SAMA5D35 SoC - * - * Copyright (C) 2013 Boris BREZILLON - */ -#include "sama5d3.dtsi" -#include "sama5d3_gmac.dtsi" -#include "sama5d3_emac.dtsi" -#include "sama5d3_can.dtsi" -#include "sama5d3_mci2.dtsi" -#include "sama5d3_uart.dtsi" -#include "sama5d3_tcb1.dtsi" - -/ { - compatible = "atmel,sama5d35", "atmel,sama5d3", "atmel,sama5"; -}; diff --git a/sys/gnu/dts/arm/sama5d35ek.dts b/sys/gnu/dts/arm/sama5d35ek.dts deleted file mode 100644 index 8edfcebb1df..00000000000 --- a/sys/gnu/dts/arm/sama5d35ek.dts +++ /dev/null @@ -1,56 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * sama5d35ek.dts - Device Tree file for SAMA5D35-EK board - * - * Copyright (C) 2013 Atmel, - * 2013 Ludovic Desroches - */ -/dts-v1/; -#include "sama5d35.dtsi" -#include "sama5d3xmb.dtsi" -#include "sama5d3xmb_emac.dtsi" -#include "sama5d3xmb_gmac.dtsi" - -/ { - model = "Atmel SAMA5D35-EK"; - compatible = "atmel,sama5d35ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d35", "atmel,sama5d3", "atmel,sama5"; - - ahb { - apb { - spi0: spi@f0004000 { - status = "okay"; - }; - - can0: can@f000c000 { - status = "okay"; - }; - - i2c1: i2c@f0018000 { - status = "okay"; - }; - - macb0: ethernet@f0028000 { - status = "okay"; - }; - - isi: isi@f0034000 { - status = "okay"; - }; - - macb1: ethernet@f802c000 { - status = "okay"; - }; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - - pb_user1 { - label = "pb_user1"; - gpios = <&pioE 27 GPIO_ACTIVE_HIGH>; - linux,code = <0x100>; - wakeup-source; - }; - }; -}; diff --git a/sys/gnu/dts/arm/sama5d36.dtsi b/sys/gnu/dts/arm/sama5d36.dtsi deleted file mode 100644 index 5d88f996713..00000000000 --- a/sys/gnu/dts/arm/sama5d36.dtsi +++ /dev/null @@ -1,19 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * sama5d36.dtsi - Device Tree Include file for SAMA5D36 SoC - * - * Copyright (C) 2013 Atmel, - * 2013 Josh Wu - */ -#include "sama5d3.dtsi" -#include "sama5d3_can.dtsi" -#include "sama5d3_gmac.dtsi" -#include "sama5d3_emac.dtsi" -#include "sama5d3_lcd.dtsi" -#include "sama5d3_mci2.dtsi" -#include "sama5d3_tcb1.dtsi" -#include "sama5d3_uart.dtsi" - -/ { - compatible = "atmel,sama5d36", "atmel,sama5d3", "atmel,sama5"; -}; diff --git a/sys/gnu/dts/arm/sama5d36ek.dts b/sys/gnu/dts/arm/sama5d36ek.dts deleted file mode 100644 index 26950f9284c..00000000000 --- a/sys/gnu/dts/arm/sama5d36ek.dts +++ /dev/null @@ -1,54 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * sama5d36ek.dts - Device Tree file for SAMA5D36-EK board - * - * Copyright (C) 2013 Atmel, - * 2013 Josh Wu - */ -/dts-v1/; -#include "sama5d36.dtsi" -#include "sama5d3xmb.dtsi" -#include "sama5d3xdm.dtsi" -#include "sama5d3xmb_emac.dtsi" -#include "sama5d3xmb_gmac.dtsi" - -/ { - model = "Atmel SAMA5D36-EK"; - compatible = "atmel,sama5d36ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d36", "atmel,sama5d3", "atmel,sama5"; - - ahb { - apb { - spi0: spi@f0004000 { - status = "okay"; - }; - - ssc0: ssc@f0008000 { - status = "okay"; - }; - - can0: can@f000c000 { - status = "okay"; - }; - - i2c0: i2c@f0014000 { - status = "okay"; - }; - - i2c1: i2c@f0018000 { - status = "okay"; - }; - - macb0: ethernet@f0028000 { - status = "okay"; - }; - - macb1: ethernet@f802c000 { - status = "okay"; - }; - }; - }; - - sound { - status = "okay"; - }; -}; diff --git a/sys/gnu/dts/arm/sama5d36ek_cmp.dts b/sys/gnu/dts/arm/sama5d36ek_cmp.dts deleted file mode 100644 index 66695b9a3e7..00000000000 --- a/sys/gnu/dts/arm/sama5d36ek_cmp.dts +++ /dev/null @@ -1,50 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * sama5d36ek_cmp.dts - Device Tree file for SAMA5D36-EK CMP board - * - * Copyright (C) 2016 Atmel, - */ -/dts-v1/; -#include "sama5d36.dtsi" -#include "sama5d3xmb_cmp.dtsi" - -/ { - model = "Atmel SAMA5D36EK-CMP"; - compatible = "atmel,sama5d36ek-cmp", "atmel,sama5d3xmb-cmp", "atmel,sama5d3xcm-cmp", "atmel,sama5d36", "atmel,sama5d3", "atmel,sama5"; - - ahb { - apb { - spi0: spi@f0004000 { - status = "okay"; - }; - - ssc0: ssc@f0008000 { - status = "okay"; - }; - - can0: can@f000c000 { - status = "okay"; - }; - - i2c0: i2c@f0014000 { - status = "okay"; - }; - - i2c1: i2c@f0018000 { - status = "okay"; - }; - - macb0: ethernet@f0028000 { - status = "okay"; - }; - - macb1: ethernet@f802c000 { - status = "okay"; - }; - }; - }; - - sound { - status = "okay"; - }; -}; diff --git a/sys/gnu/dts/arm/sama5d3_can.dtsi b/sys/gnu/dts/arm/sama5d3_can.dtsi deleted file mode 100644 index 2470dd3fff2..00000000000 --- a/sys/gnu/dts/arm/sama5d3_can.dtsi +++ /dev/null @@ -1,73 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * sama5d3_can.dtsi - Device Tree Include file for SAMA5D3 SoC with - * CAN support - * - * Copyright (C) 2013 Boris BREZILLON - */ - -#include -#include - -/ { - ahb { - apb { - pinctrl@fffff200 { - can0 { - pinctrl_can0_rx_tx: can0_rx_tx { - atmel,pins = - ; /* PD15 periph C TX, conflicts with CTS0, SPI0_NPCS2 */ - }; - }; - - can1 { - pinctrl_can1_rx_tx: can1_rx_tx { - atmel,pins = - ; /* PB15 periph B TX, conflicts with GCOL */ - }; - }; - - }; - - pmc: pmc@fffffc00 { - periphck { - can0_clk: can0_clk { - #clock-cells = <0>; - reg = <40>; - atmel,clk-output-range = <0 83000000>; - }; - - can1_clk: can1_clk { - #clock-cells = <0>; - reg = <41>; - atmel,clk-output-range = <0 83000000>; - }; - }; - }; - - can0: can@f000c000 { - compatible = "atmel,at91sam9x5-can"; - reg = <0xf000c000 0x300>; - interrupts = <40 IRQ_TYPE_LEVEL_HIGH 3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can0_rx_tx>; - clocks = <&can0_clk>; - clock-names = "can_clk"; - status = "disabled"; - }; - - can1: can@f8010000 { - compatible = "atmel,at91sam9x5-can"; - reg = <0xf8010000 0x300>; - interrupts = <41 IRQ_TYPE_LEVEL_HIGH 3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can1_rx_tx>; - clocks = <&can1_clk>; - clock-names = "can_clk"; - status = "disabled"; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/sama5d3_emac.dtsi b/sys/gnu/dts/arm/sama5d3_emac.dtsi deleted file mode 100644 index 9aef414bcd2..00000000000 --- a/sys/gnu/dts/arm/sama5d3_emac.dtsi +++ /dev/null @@ -1,54 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * sama5d3_emac.dtsi - Device Tree Include file for SAMA5D3 SoC with - * Ethernet. - * - * Copyright (C) 2013 Boris BREZILLON - */ - -#include -#include - -/ { - ahb { - apb { - pinctrl@fffff200 { - macb1 { - pinctrl_macb1_rmii: macb1_rmii-0 { - atmel,pins = - ; /* PC9 periph A EMDIO */ - }; - }; - }; - - pmc: pmc@fffffc00 { - periphck { - macb1_clk: macb1_clk { - #clock-cells = <0>; - reg = <35>; - }; - }; - }; - - macb1: ethernet@f802c000 { - compatible = "atmel,sama5d3-macb", "cdns,at91sam9260-macb", "cdns,macb"; - reg = <0xf802c000 0x100>; - interrupts = <35 IRQ_TYPE_LEVEL_HIGH 3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_macb1_rmii>; - clocks = <&macb1_clk>, <&macb1_clk>; - clock-names = "hclk", "pclk"; - status = "disabled"; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/sama5d3_gmac.dtsi b/sys/gnu/dts/arm/sama5d3_gmac.dtsi deleted file mode 100644 index 3667765a138..00000000000 --- a/sys/gnu/dts/arm/sama5d3_gmac.dtsi +++ /dev/null @@ -1,87 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * sama5d3_gmac.dtsi - Device Tree Include file for SAMA5D3 SoC with - * Gigabit Ethernet. - * - * Copyright (C) 2013 Boris BREZILLON - */ - -#include -#include - -/ { - ahb { - apb { - pinctrl@fffff200 { - macb0 { - pinctrl_macb0_data_rgmii: macb0_data_rgmii { - atmel,pins = - ; /* PB7 periph A GRX3, conflicts with RK1 */ - }; - pinctrl_macb0_data_gmii: macb0_data_gmii { - atmel,pins = - ; /* PB26 periph B GRX7, conflicts with CTS1 */ - }; - pinctrl_macb0_signal_rgmii: macb0_signal_rgmii { - atmel,pins = - ; /* PB18 periph A G125CK */ - }; - pinctrl_macb0_signal_gmii: macb0_signal_gmii { - atmel,pins = - ; /* PB27 periph B G125CKO */ - }; - - }; - }; - - pmc: pmc@fffffc00 { - periphck { - macb0_clk: macb0_clk { - #clock-cells = <0>; - reg = <34>; - }; - }; - }; - - macb0: ethernet@f0028000 { - compatible = "atmel,sama5d3-gem"; - reg = <0xf0028000 0x100>; - interrupts = <34 IRQ_TYPE_LEVEL_HIGH 3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_macb0_data_rgmii &pinctrl_macb0_signal_rgmii>; - clocks = <&macb0_clk>, <&macb0_clk>; - clock-names = "hclk", "pclk"; - status = "disabled"; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/sama5d3_lcd.dtsi b/sys/gnu/dts/arm/sama5d3_lcd.dtsi deleted file mode 100644 index 2cf046cd4e9..00000000000 --- a/sys/gnu/dts/arm/sama5d3_lcd.dtsi +++ /dev/null @@ -1,214 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * sama5d3_lcd.dtsi - Device Tree Include file for SAMA5D3 SoC with - * LCD support - * - * Copyright (C) 2013 Boris BREZILLON - */ - -#include -#include - -/ { - ahb { - apb { - hlcdc: hlcdc@f0030000 { - compatible = "atmel,sama5d3-hlcdc"; - reg = <0xf0030000 0x2000>; - interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>; - clock-names = "periph_clk","sys_clk", "slow_clk"; - status = "disabled"; - - hlcdc-display-controller { - compatible = "atmel,hlcdc-display-controller"; - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - }; - - hlcdc_pwm: hlcdc-pwm { - compatible = "atmel,hlcdc-pwm"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd_pwm>; - #pwm-cells = <3>; - }; - }; - - pinctrl@fffff200 { - lcd { - pinctrl_lcd_base: lcd-base-0 { - atmel,pins = - ; /* LCDPCK */ - }; - - pinctrl_lcd_pwm: lcd-pwm-0 { - atmel,pins = ; /* LCDPWM */ - }; - - pinctrl_lcd_rgb444: lcd-rgb-0 { - atmel,pins = - ; /* LCDD11 pin */ - }; - - pinctrl_lcd_rgb565: lcd-rgb-1 { - atmel,pins = - ; /* LCDD15 pin */ - }; - - pinctrl_lcd_rgb666: lcd-rgb-2 { - atmel,pins = - ; /* LCDD17 pin */ - }; - - pinctrl_lcd_rgb666_alt: lcd-rgb-2-alt { - atmel,pins = - ; /* LCDD17 pin */ - }; - - pinctrl_lcd_rgb888: lcd-rgb-3 { - atmel,pins = - ; /* LCDD23 pin */ - }; - - pinctrl_lcd_rgb888_alt: lcd-rgb-3-alt { - atmel,pins = - ; /* LCDD23 pin */ - }; - }; - }; - - pmc: pmc@fffffc00 { - periphck { - lcdc_clk: lcdc_clk { - #clock-cells = <0>; - reg = <36>; - }; - }; - - systemck { - lcdck: lcdck { - #clock-cells = <0>; - reg = <3>; - clocks = <&mck>; - }; - }; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/sama5d3_mci2.dtsi b/sys/gnu/dts/arm/sama5d3_mci2.dtsi deleted file mode 100644 index 3c83c1c36ac..00000000000 --- a/sys/gnu/dts/arm/sama5d3_mci2.dtsi +++ /dev/null @@ -1,58 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * sama5d3_mci2.dtsi - Device Tree Include file for SAMA5D3 SoC with - * 3 MMC ports - * - * Copyright (C) 2013 Boris BREZILLON - */ - -#include -#include -#include - -/ { - ahb { - apb { - pinctrl@fffff200 { - mmc2 { - pinctrl_mmc2_clk_cmd_dat0: mmc2_clk_cmd_dat0 { - atmel,pins = - ; /* PC11 periph A MCI2_DA0 with pullup */ - }; - pinctrl_mmc2_dat1_3: mmc2_dat1_3 { - atmel,pins = - ; /* PC14 periph A MCI2_DA3 with pullup, conflicts with TCLK1 */ - }; - }; - }; - - pmc: pmc@fffffc00 { - periphck { - mci2_clk: mci2_clk { - #clock-cells = <0>; - reg = <23>; - }; - }; - }; - - mmc2: mmc@f8004000 { - compatible = "atmel,hsmci"; - reg = <0xf8004000 0x600>; - interrupts = <23 IRQ_TYPE_LEVEL_HIGH 0>; - dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(1)>; - dma-names = "rxtx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mmc2_clk_cmd_dat0 &pinctrl_mmc2_dat1_3>; - clocks = <&mci2_clk>; - clock-names = "mci_clk"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/sama5d3_tcb1.dtsi b/sys/gnu/dts/arm/sama5d3_tcb1.dtsi deleted file mode 100644 index 215802b8db3..00000000000 --- a/sys/gnu/dts/arm/sama5d3_tcb1.dtsi +++ /dev/null @@ -1,41 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * sama5d3_tcb1.dtsi - Device Tree Include file for SAMA5D3 SoC with - * 2 TC blocks. - * - * Copyright (C) 2013 Boris BREZILLON - */ - -#include -#include -#include - -/ { - aliases { - tcb1 = &tcb1; - }; - - ahb { - apb { - pmc: pmc@fffffc00 { - periphck { - tcb1_clk: tcb1_clk { - #clock-cells = <0>; - reg = <27>; - atmel,clk-output-range = <0 166000000>; - }; - }; - }; - - tcb1: timer@f8014000 { - compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xf8014000 0x100>; - interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tcb1_clk>, <&clk32k>; - clock-names = "t0_clk", "slow_clk"; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/sama5d3_uart.dtsi b/sys/gnu/dts/arm/sama5d3_uart.dtsi deleted file mode 100644 index cb62adbd28e..00000000000 --- a/sys/gnu/dts/arm/sama5d3_uart.dtsi +++ /dev/null @@ -1,78 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * sama5d3_uart.dtsi - Device Tree Include file for SAMA5D3 SoC with - * UART support - * - * Copyright (C) 2013 Boris BREZILLON - */ - -#include -#include -#include - -/ { - aliases { - serial5 = &uart0; - serial6 = &uart1; - }; - - ahb { - apb { - pinctrl@fffff200 { - uart0 { - pinctrl_uart0: uart0-0 { - atmel,pins = - ; /* conflicts with ISI_PCK */ - }; - }; - - uart1 { - pinctrl_uart1: uart1-0 { - atmel,pins = - ; /* conflicts with TWCK0, ISI_HSYNC */ - }; - }; - }; - - pmc: pmc@fffffc00 { - periphck { - uart0_clk: uart0_clk { - #clock-cells = <0>; - reg = <16>; - atmel,clk-output-range = <0 83000000>; - }; - - uart1_clk: uart1_clk { - #clock-cells = <0>; - reg = <17>; - atmel,clk-output-range = <0 83000000>; - }; - }; - }; - - uart0: serial@f0024000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xf0024000 0x100>; - interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0>; - clocks = <&uart0_clk>; - clock-names = "usart"; - status = "disabled"; - }; - - uart1: serial@f8028000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xf8028000 0x100>; - interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - clocks = <&uart1_clk>; - clock-names = "usart"; - status = "disabled"; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/sama5d3xcm.dtsi b/sys/gnu/dts/arm/sama5d3xcm.dtsi deleted file mode 100644 index 65566e4b78d..00000000000 --- a/sys/gnu/dts/arm/sama5d3xcm.dtsi +++ /dev/null @@ -1,139 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * sama5d3xcm.dtsi - Device Tree Include file for SAMA5D3x CPU Module - * - * Copyright (C) 2013 Atmel, - * 2013 Ludovic Desroches - */ - -/ { - compatible = "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5"; - - chosen { - bootargs = "rootfstype=ubifs ubi.mtd=5 root=ubi0:rootfs"; - stdout-path = "serial0:115200n8"; - }; - - memory { - reg = <0x20000000 0x20000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <12000000>; - }; - }; - - ahb { - apb { - spi0: spi@f0004000 { - cs-gpios = <&pioD 13 0>, <0>, <0>, <0>; - }; - - tcb0: timer@f0010000 { - timer@0 { - compatible = "atmel,tcb-timer"; - reg = <0>; - }; - - timer@1 { - compatible = "atmel,tcb-timer"; - reg = <1>; - }; - }; - }; - - ebi@10000000 { - pinctrl-0 = <&pinctrl_ebi_addr &pinctrl_ebi_cs0>; - pinctr-name = "default"; - status = "okay"; - - nor: flash@0,0 { - compatible = "cfi-flash"; - linux,mtd-name = "physmap-flash.0"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x0 0x0 0x1000000>; - bank-width = <2>; - atmel,smc-read-mode = "nrd"; - atmel,smc-write-mode = "nwe"; - atmel,smc-bus-width = <16>; - atmel,smc-ncs-rd-setup-ns = <0>; - atmel,smc-ncs-wr-setup-ns = <0>; - atmel,smc-nwe-setup-ns = <8>; - atmel,smc-nrd-setup-ns = <16>; - atmel,smc-ncs-rd-pulse-ns = <84>; - atmel,smc-ncs-wr-pulse-ns = <84>; - atmel,smc-nrd-pulse-ns = <76>; - atmel,smc-nwe-pulse-ns = <76>; - atmel,smc-nrd-cycle-ns = <107>; - atmel,smc-nwe-cycle-ns = <84>; - atmel,smc-tdf-ns = <16>; - }; - - nand_controller: nand-controller { - status = "okay"; - - nand@3 { - reg = <0x3 0x0 0x2>; - atmel,rb = <0>; - nand-ecc-mode = "hw"; - nand-ecc-strength = <4>; - nand-ecc-step-size = <512>; - nand-on-flash-bbt; - label = "atmel_nand"; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - at91bootstrap@0 { - label = "at91bootstrap"; - reg = <0x0 0x40000>; - }; - - bootloader@40000 { - label = "bootloader"; - reg = <0x40000 0x80000>; - }; - - bootloaderenv@c0000 { - label = "bootloader env"; - reg = <0xc0000 0xc0000>; - }; - - dtb@180000 { - label = "device tree"; - reg = <0x180000 0x80000>; - }; - - kernel@200000 { - label = "kernel"; - reg = <0x200000 0x600000>; - }; - - rootfs@800000 { - label = "rootfs"; - reg = <0x800000 0x0f800000>; - }; - }; - }; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - d2 { - label = "d2"; - gpios = <&pioE 25 GPIO_ACTIVE_LOW>; /* PE25, conflicts with A25, RXD2 */ - linux,default-trigger = "heartbeat"; - }; - }; -}; diff --git a/sys/gnu/dts/arm/sama5d3xcm_cmp.dtsi b/sys/gnu/dts/arm/sama5d3xcm_cmp.dtsi deleted file mode 100644 index 9d2563602cb..00000000000 --- a/sys/gnu/dts/arm/sama5d3xcm_cmp.dtsi +++ /dev/null @@ -1,193 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * sama5d3xcm_cmp.dtsi - Device Tree Include file for SAMA5D36 CMP CPU Module - * - * Copyright (C) 2016 Atmel, - */ - -/ { - compatible = "atmel,sama5d3xcm-cmp", "atmel,sama5d3", "atmel,sama5"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - reg = <0x20000000 0x20000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <12000000>; - }; - }; - - ahb { - apb { - spi0: spi@f0004000 { - cs-gpios = <&pioD 13 0>, <0>, <0>, <0>; - }; - - tcb0: timer@f0010000 { - timer@0 { - compatible = "atmel,tcb-timer"; - reg = <0>; - }; - - timer@1 { - compatible = "atmel,tcb-timer"; - reg = <1>; - }; - }; - - macb0: ethernet@f0028000 { - phy-mode = "rgmii"; - #address-cells = <1>; - #size-cells = <0>; - - ethernet-phy@1 { - reg = <0x1>; - interrupt-parent = <&pioB>; - interrupts = <25 IRQ_TYPE_EDGE_FALLING>; - txen-skew-ps = <800>; - txc-skew-ps = <3000>; - rxdv-skew-ps = <400>; - rxc-skew-ps = <3000>; - rxd0-skew-ps = <400>; - rxd1-skew-ps = <400>; - rxd2-skew-ps = <400>; - rxd3-skew-ps = <400>; - }; - - ethernet-phy@7 { - reg = <0x7>; - interrupt-parent = <&pioB>; - interrupts = <25 IRQ_TYPE_EDGE_FALLING>; - txen-skew-ps = <800>; - txc-skew-ps = <3000>; - rxdv-skew-ps = <400>; - rxc-skew-ps = <3000>; - rxd0-skew-ps = <400>; - rxd1-skew-ps = <400>; - rxd2-skew-ps = <400>; - rxd3-skew-ps = <400>; - }; - }; - - i2c1: i2c@f0018000 { - pmic: act8865@5b { - compatible = "active-semi,act8865"; - reg = <0x5b>; - status = "disabled"; - - regulators { - vcc_1v8_reg: DCDC_REG1 { - regulator-name = "VCC_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vcc_1v2_reg: DCDC_REG2 { - regulator-name = "VCC_1V2"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - }; - - vcc_3v3_reg: DCDC_REG3 { - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vddana_reg: LDO_REG1 { - regulator-name = "VDDANA"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vddfuse_reg: LDO_REG2 { - regulator-name = "FUSE_2V5"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - }; - }; - }; - }; - }; - - ebi: ebi@10000000 { - pinctrl-0 = <&pinctrl_ebi_nand_addr>; - pinctrl-names = "default"; - status = "okay"; - - nand_controller: nand-controller { - status = "okay"; - - nand@3 { - reg = <0x3 0x0 0x2>; - atmel,rb = <0>; - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - nand-ecc-strength = <4>; - nand-ecc-step-size = <512>; - nand-on-flash-bbt; - label = "atmel_nand"; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - at91bootstrap@0 { - label = "at91bootstrap"; - reg = <0x0 0x40000>; - }; - - bootloader@40000 { - label = "bootloader"; - reg = <0x40000 0x80000>; - }; - - bootloaderenv@c0000 { - label = "bootloader env"; - reg = <0xc0000 0xc0000>; - }; - - dtb@180000 { - label = "device tree"; - reg = <0x180000 0x80000>; - }; - - kernel@200000 { - label = "kernel"; - reg = <0x200000 0x600000>; - }; - - rootfs@800000 { - label = "rootfs"; - reg = <0x800000 0x0f800000>; - }; - }; - }; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - d2 { - label = "d2"; - gpios = <&pioE 25 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - }; - }; -}; diff --git a/sys/gnu/dts/arm/sama5d3xdm.dtsi b/sys/gnu/dts/arm/sama5d3xdm.dtsi deleted file mode 100644 index 3c1c4d62fbf..00000000000 --- a/sys/gnu/dts/arm/sama5d3xdm.dtsi +++ /dev/null @@ -1,40 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * sama5d3dm.dtsi - Device Tree file for SAMA5 display module - * - * Copyright (C) 2013 Atmel, - * 2013 Ludovic Desroches - */ - -/ { - ahb { - apb { - i2c1: i2c@f0018000 { - qt1070: keyboard@1b { - compatible = "qt1070"; - reg = <0x1b>; - interrupt-parent = <&pioE>; - interrupts = <31 0x0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_qt1070_irq>; - wakeup-source; - }; - }; - - adc0: adc@f8018000 { - atmel,adc-ts-wires = <4>; - atmel,adc-ts-pressure-threshold = <10000>; - status = "okay"; - }; - - pinctrl@fffff200 { - board { - pinctrl_qt1070_irq: qt1070_irq { - atmel,pins = - ; /* PE31 GPIO with pull up deglith */ - }; - }; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/sama5d3xmb.dtsi b/sys/gnu/dts/arm/sama5d3xmb.dtsi deleted file mode 100644 index 35031bbc7e7..00000000000 --- a/sys/gnu/dts/arm/sama5d3xmb.dtsi +++ /dev/null @@ -1,208 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * sama5d3xmb.dts - Device Tree file for SAMA5D3x mother board - * - * Copyright (C) 2013 Atmel, - * 2013 Ludovic Desroches - */ -#include "sama5d3xcm.dtsi" - -/ { - compatible = "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5"; - - ahb { - apb { - mmc0: mmc@f0000000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_cd>; - status = "okay"; - slot@0 { - reg = <0>; - bus-width = <4>; - cd-gpios = <&pioD 17 GPIO_ACTIVE_HIGH>; - }; - }; - - spi0: spi@f0004000 { - dmas = <0>, <0>; /* Do not use DMA for spi0 */ - - m25p80@0 { - compatible = "atmel,at25df321a"; - spi-max-frequency = <50000000>; - reg = <0>; - }; - }; - - ssc0: ssc@f0008000 { - atmel,clk-from-rk-pin; - }; - - /* - * i2c0 conflicts with ISI: - * disable it to allow the use of ISI - * can not enable audio when i2c0 disabled - */ - i2c0: i2c@f0014000 { - wm8904: wm8904@1a { - compatible = "wlf,wm8904"; - reg = <0x1a>; - clocks = <&pck0>; - clock-names = "mclk"; - }; - }; - - i2c1: i2c@f0018000 { - ov2640: camera@30 { - compatible = "ovti,ov2640"; - reg = <0x30>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pck1_as_isi_mck &pinctrl_sensor_power &pinctrl_sensor_reset>; - resetb-gpios = <&pioE 24 GPIO_ACTIVE_LOW>; - pwdn-gpios = <&pioE 29 GPIO_ACTIVE_HIGH>; - /* use pck1 for the master clock of ov2640 */ - clocks = <&pck1>; - clock-names = "xvclk"; - assigned-clocks = <&pck1>; - assigned-clock-rates = <25000000>; - - port { - ov2640_0: endpoint { - remote-endpoint = <&isi_0>; - bus-width = <8>; - }; - }; - }; - }; - - usart1: serial@f0020000 { - dmas = <0>, <0>; /* Do not use DMA for usart1 */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts_cts>; - status = "okay"; - }; - - isi: isi@f0034000 { - port { - isi_0: endpoint { - remote-endpoint = <&ov2640_0>; - bus-width = <8>; - vsync-active = <1>; - hsync-active = <1>; - }; - }; - }; - - mmc1: mmc@f8000000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3 &pinctrl_mmc1_cd>; - status = "okay"; - slot@0 { - reg = <0>; - bus-width = <4>; - cd-gpios = <&pioD 18 GPIO_ACTIVE_HIGH>; - }; - }; - - adc0: adc@f8018000 { - pinctrl-names = "default"; - pinctrl-0 = < - &pinctrl_adc0_adtrg - &pinctrl_adc0_ad0 - &pinctrl_adc0_ad1 - &pinctrl_adc0_ad2 - &pinctrl_adc0_ad3 - &pinctrl_adc0_ad4 - >; - status = "okay"; - }; - - pinctrl@fffff200 { - board { - pinctrl_mmc0_cd: mmc0_cd { - atmel,pins = - ; /* PD17 GPIO with pullup deglitch */ - }; - - pinctrl_mmc1_cd: mmc1_cd { - atmel,pins = - ; /* PD18 GPIO with pullup deglitch */ - }; - - pinctrl_pck0_as_audio_mck: pck0_as_audio_mck { - atmel,pins = - ; /* PD30 periph B */ - }; - - pinctrl_pck1_as_isi_mck: pck1_as_isi_mck-0 { - atmel,pins = - ; /* PD31 periph B ISI_MCK */ - }; - - pinctrl_sensor_reset: sensor_reset-0 { - atmel,pins = - ; /* PE24 gpio */ - }; - - pinctrl_sensor_power: sensor_power-0 { - atmel,pins = - ; /* PE29 gpio */ - }; - - pinctrl_usba_vbus: usba_vbus { - atmel,pins = - ; /* PD29 GPIO with deglitch */ - }; - }; - }; - - dbgu: serial@ffffee00 { - dmas = <0>, <0>; /* Do not use DMA for dbgu */ - status = "okay"; - }; - - watchdog@fffffe40 { - status = "okay"; - }; - }; - - usb0: gadget@500000 { - atmel,vbus-gpio = <&pioD 29 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usba_vbus>; - status = "okay"; - }; - - usb1: ohci@600000 { - num-ports = <3>; - atmel,vbus-gpio = <&pioD 25 GPIO_ACTIVE_HIGH - &pioD 26 GPIO_ACTIVE_LOW - &pioD 27 GPIO_ACTIVE_LOW - >; - status = "okay"; - }; - - usb2: ehci@700000 { - status = "okay"; - }; - }; - - sound { - compatible = "atmel,asoc-wm8904"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pck0_as_audio_mck>; - - atmel,model = "wm8904 @ SAMA5D3EK"; - atmel,audio-routing = - "Headphone Jack", "HPOUTL", - "Headphone Jack", "HPOUTR", - "IN2L", "Line In Jack", - "IN2R", "Line In Jack", - "Mic", "MICBIAS", - "IN1L", "Mic"; - - atmel,ssc-controller = <&ssc0>; - atmel,audio-codec = <&wm8904>; - - status = "disabled"; - }; -}; diff --git a/sys/gnu/dts/arm/sama5d3xmb_cmp.dtsi b/sys/gnu/dts/arm/sama5d3xmb_cmp.dtsi deleted file mode 100644 index 8a6916a69da..00000000000 --- a/sys/gnu/dts/arm/sama5d3xmb_cmp.dtsi +++ /dev/null @@ -1,264 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * sama5d3xmb_cmp.dts - Device Tree file for SAMA5D3x CMP mother board - * - * Copyright (C) 2016 Atmel, - */ -#include "sama5d3xcm_cmp.dtsi" - -/ { - compatible = "atmel,sama5d3xmb-cmp", "atmel,sama5d3xcm-cmp", "atmel,sama5d3", "atmel,sama5"; - - ahb { - apb { - mmc0: mmc@f0000000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_cd>; - status = "okay"; - slot@0 { - reg = <0>; - bus-width = <4>; - cd-gpios = <&pioD 17 GPIO_ACTIVE_HIGH>; - }; - }; - - spi0: spi@f0004000 { - dmas = <0>, <0>; /* Do not use DMA for spi0 */ - - m25p80@0 { - compatible = "atmel,at25df321a"; - spi-max-frequency = <50000000>; - reg = <0>; - }; - }; - - ssc0: ssc@f0008000 { - atmel,clk-from-rk-pin; - }; - - /* - * i2c0 conflicts with ISI: - * disable it to allow the use of ISI - * can not enable audio when i2c0 disabled - */ - i2c0: i2c@f0014000 { - wm8904: wm8904@1a { - compatible = "wlf,wm8904"; - reg = <0x1a>; - clocks = <&pck0>; - clock-names = "mclk"; - }; - }; - - i2c1: i2c@f0018000 { - ov2640: camera@30 { - compatible = "ovti,ov2640"; - reg = <0x30>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pck1_as_isi_mck &pinctrl_sensor_power &pinctrl_sensor_reset>; - resetb-gpios = <&pioE 24 GPIO_ACTIVE_LOW>; - pwdn-gpios = <&pioE 29 GPIO_ACTIVE_HIGH>; - /* use pck1 for the master clock of ov2640 */ - clocks = <&pck1>; - clock-names = "xvclk"; - assigned-clocks = <&pck1>; - assigned-clock-rates = <25000000>; - - port { - ov2640_0: endpoint { - remote-endpoint = <&isi_0>; - bus-width = <8>; - }; - }; - }; - }; - - usart1: serial@f0020000 { - dmas = <0>, <0>; /* Do not use DMA for usart1 */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts_cts>; - status = "okay"; - }; - - isi: isi@f0034000 { - port { - isi_0: endpoint { - remote-endpoint = <&ov2640_0>; - bus-width = <8>; - vsync-active = <1>; - hsync-active = <1>; - }; - }; - }; - - mmc1: mmc@f8000000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3 &pinctrl_mmc1_cd>; - status = "okay"; - slot@0 { - reg = <0>; - bus-width = <4>; - cd-gpios = <&pioD 18 GPIO_ACTIVE_HIGH>; - }; - }; - - adc0: adc@f8018000 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = < - &pinctrl_adc0_adtrg - &pinctrl_adc0_ad0 - &pinctrl_adc0_ad1 - &pinctrl_adc0_ad2 - &pinctrl_adc0_ad3 - &pinctrl_adc0_ad4 - >; - pinctrl-1 = < - &pinctrl_adc0_adtrg_sleep - &pinctrl_adc0_ad0_sleep - &pinctrl_adc0_ad1_sleep - &pinctrl_adc0_ad2_sleep - &pinctrl_adc0_ad3_sleep - &pinctrl_adc0_ad4_sleep - >; - status = "okay"; - }; - - macb1: ethernet@f802c000 { - phy-mode = "rmii"; - - #address-cells = <1>; - #size-cells = <0>; - phy0: ethernet-phy@1 { - /*interrupt-parent = <&pioE>;*/ - /*interrupts = <30 IRQ_TYPE_EDGE_FALLING>;*/ - reg = <1>; - }; - }; - - pinctrl@fffff200 { - adc0 { - pinctrl_adc0_adtrg_sleep: adc0_adtrg_1 { - atmel,pins = - ; - }; - pinctrl_adc0_ad0_sleep: adc0_ad0_1 { - atmel,pins = - ; - }; - pinctrl_adc0_ad1_sleep: adc0_ad1_1 { - atmel,pins = - ; - }; - pinctrl_adc0_ad2_sleep: adc0_ad2_1 { - atmel,pins = - ; - }; - pinctrl_adc0_ad3_sleep: adc0_ad3_1 { - atmel,pins = - ; - }; - pinctrl_adc0_ad4_sleep: adc0_ad4_1 { - atmel,pins = - ; - }; - }; - - board { - pinctrl_gpio_keys: gpio_keys { - atmel,pins = - ; - }; - - pinctrl_mmc0_cd: mmc0_cd { - atmel,pins = - ; - }; - - pinctrl_mmc1_cd: mmc1_cd { - atmel,pins = - ; - }; - - pinctrl_pck0_as_audio_mck: pck0_as_audio_mck { - atmel,pins = - ; - }; - - pinctrl_pck1_as_isi_mck: pck1_as_isi_mck-0 { - atmel,pins = - ; - }; - - pinctrl_sensor_reset: sensor_reset-0 { - atmel,pins = - ; - }; - - pinctrl_sensor_power: sensor_power-0 { - atmel,pins = - ; - }; - - pinctrl_usba_vbus: usba_vbus { - atmel,pins = - ; - }; - }; - }; - - dbgu: serial@ffffee00 { - dmas = <0>, <0>; /* Do not use DMA for dbgu */ - status = "okay"; - }; - - watchdog@fffffe40 { - status = "okay"; - }; - }; - - usb0: gadget@500000 { - atmel,vbus-gpio = <&pioD 29 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usba_vbus>; - status = "okay"; - }; - }; - - sound { - compatible = "atmel,asoc-wm8904"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pck0_as_audio_mck>; - - atmel,model = "wm8904 @ SAMA5D3EK"; - atmel,audio-routing = - "Headphone Jack", "HPOUTL", - "Headphone Jack", "HPOUTR", - "IN2L", "Line In Jack", - "IN2R", "Line In Jack", - "Mic", "MICBIAS", - "IN1L", "Mic"; - - atmel,ssc-controller = <&ssc0>; - atmel,audio-codec = <&wm8904>; - - status = "disabled"; - }; - - /* Conflict with LCD pins */ - gpio_keys { - compatible = "gpio-keys"; - status = "okay"; - - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_keys>; - - pb_user1 { - label = "pb_user1"; - gpios = <&pioE 27 GPIO_ACTIVE_HIGH>; - linux,code = <0x100>; - wakeup-source; - }; - }; -}; diff --git a/sys/gnu/dts/arm/sama5d3xmb_emac.dtsi b/sys/gnu/dts/arm/sama5d3xmb_emac.dtsi deleted file mode 100644 index a5dd41cd952..00000000000 --- a/sys/gnu/dts/arm/sama5d3xmb_emac.dtsi +++ /dev/null @@ -1,25 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * sama5d3xmb_emac.dts - Device Tree Include file for SAMA5D3x mother board - * Ethernet - * - * Copyright (C) 2016 Atmel, - */ - -/ { - ahb { - apb { - macb1: ethernet@f802c000 { - phy-mode = "rmii"; - - #address-cells = <1>; - #size-cells = <0>; - phy0: ethernet-phy@1 { - interrupt-parent = <&pioE>; - interrupts = <30 IRQ_TYPE_EDGE_FALLING>; - reg = <1>; - }; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/sama5d3xmb_gmac.dtsi b/sys/gnu/dts/arm/sama5d3xmb_gmac.dtsi deleted file mode 100644 index d750da38ff3..00000000000 --- a/sys/gnu/dts/arm/sama5d3xmb_gmac.dtsi +++ /dev/null @@ -1,47 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * sama5d3xmb_gmac.dtsi - Device Tree Include file for SAMA5D3x motherboard - * Gigabit Ethernet - * - * Copyright (C) 2016 Atmel, - */ - -/ { - ahb { - apb { - macb0: ethernet@f0028000 { - phy-mode = "rgmii"; - #address-cells = <1>; - #size-cells = <0>; - - ethernet-phy@1 { - reg = <0x1>; - interrupt-parent = <&pioB>; - interrupts = <25 IRQ_TYPE_EDGE_FALLING>; - txen-skew-ps = <800>; - txc-skew-ps = <3000>; - rxdv-skew-ps = <400>; - rxc-skew-ps = <3000>; - rxd0-skew-ps = <400>; - rxd1-skew-ps = <400>; - rxd2-skew-ps = <400>; - rxd3-skew-ps = <400>; - }; - - ethernet-phy@7 { - reg = <0x7>; - interrupt-parent = <&pioB>; - interrupts = <25 IRQ_TYPE_EDGE_FALLING>; - txen-skew-ps = <800>; - txc-skew-ps = <3000>; - rxdv-skew-ps = <400>; - rxc-skew-ps = <3000>; - rxd0-skew-ps = <400>; - rxd1-skew-ps = <400>; - rxd2-skew-ps = <400>; - rxd3-skew-ps = <400>; - }; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/sama5d4.dtsi b/sys/gnu/dts/arm/sama5d4.dtsi deleted file mode 100644 index 6ab27a7b388..00000000000 --- a/sys/gnu/dts/arm/sama5d4.dtsi +++ /dev/null @@ -1,1549 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * sama5d4.dtsi - Device Tree Include file for SAMA5D4 family SoC - * - * Copyright (C) 2014 Atmel, - * 2014 Nicolas Ferre - */ - -#include -#include -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - model = "Atmel SAMA5D4 family SoC"; - compatible = "atmel,sama5d4"; - interrupt-parent = <&aic>; - - aliases { - serial0 = &usart3; - serial1 = &usart4; - serial2 = &usart2; - serial3 = &usart0; - serial4 = &usart1; - serial5 = &uart0; - serial6 = &uart1; - gpio0 = &pioA; - gpio1 = &pioB; - gpio2 = &pioC; - gpio3 = &pioD; - gpio4 = &pioE; - pwm0 = &pwm0; - ssc0 = &ssc0; - ssc1 = &ssc1; - tcb0 = &tcb0; - tcb1 = &tcb1; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - }; - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a5"; - reg = <0>; - next-level-cache = <&L2>; - }; - }; - - memory { - device_type = "memory"; - reg = <0x20000000 0x20000000>; - }; - - clocks { - slow_xtal: slow_xtal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - main_xtal: main_xtal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - adc_op_clk: adc_op_clk{ - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <1000000>; - }; - }; - - ns_sram: sram@210000 { - compatible = "mmio-sram"; - reg = <0x00210000 0x10000>; - }; - - ahb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - nfc_sram: sram@100000 { - compatible = "mmio-sram"; - no-memory-wc; - reg = <0x100000 0x2400>; - }; - - usb0: gadget@400000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "atmel,sama5d3-udc"; - reg = <0x00400000 0x100000 - 0xfc02c000 0x4000>; - interrupts = <47 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 47>, <&pmc PMC_TYPE_CORE PMC_UTMI>; - clock-names = "pclk", "hclk"; - status = "disabled"; - - ep@0 { - reg = <0>; - atmel,fifo-size = <64>; - atmel,nb-banks = <1>; - }; - - ep@1 { - reg = <1>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <3>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@2 { - reg = <2>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <3>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@3 { - reg = <3>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@4 { - reg = <4>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@5 { - reg = <5>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@6 { - reg = <6>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@7 { - reg = <7>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@8 { - reg = <8>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-isoc; - }; - - ep@9 { - reg = <9>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-isoc; - }; - - ep@10 { - reg = <10>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-isoc; - }; - - ep@11 { - reg = <11>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-isoc; - }; - - ep@12 { - reg = <12>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-isoc; - }; - - ep@13 { - reg = <13>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-isoc; - }; - - ep@14 { - reg = <14>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-isoc; - }; - - ep@15 { - reg = <15>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-isoc; - }; - }; - - usb1: ohci@500000 { - compatible = "atmel,at91rm9200-ohci", "usb-ohci"; - reg = <0x00500000 0x100000>; - interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 46>, <&pmc PMC_TYPE_PERIPHERAL 46>, <&pmc PMC_TYPE_SYSTEM 6>; - clock-names = "ohci_clk", "hclk", "uhpck"; - status = "disabled"; - }; - - usb2: ehci@600000 { - compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; - reg = <0x00600000 0x100000>; - interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 46>; - clock-names = "usb_clk", "ehci_clk"; - status = "disabled"; - }; - - L2: cache-controller@a00000 { - compatible = "arm,pl310-cache"; - reg = <0x00a00000 0x1000>; - interrupts = <67 IRQ_TYPE_LEVEL_HIGH 4>; - cache-unified; - cache-level = <2>; - }; - - ebi: ebi@10000000 { - compatible = "atmel,sama5d3-ebi"; - #address-cells = <2>; - #size-cells = <1>; - atmel,smc = <&hsmc>; - reg = <0x10000000 0x10000000 - 0x60000000 0x28000000>; - ranges = <0x0 0x0 0x10000000 0x10000000 - 0x1 0x0 0x60000000 0x10000000 - 0x2 0x0 0x70000000 0x10000000 - 0x3 0x0 0x80000000 0x8000000>; - clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; - status = "disabled"; - - nand_controller: nand-controller { - compatible = "atmel,sama5d3-nand-controller"; - atmel,nfc-sram = <&nfc_sram>; - atmel,nfc-io = <&nfc_io>; - ecc-engine = <&pmecc>; - #address-cells = <2>; - #size-cells = <1>; - ranges; - status = "disabled"; - }; - }; - - nfc_io: nfc-io@90000000 { - compatible = "atmel,sama5d3-nfc-io", "syscon"; - reg = <0x90000000 0x8000000>; - }; - - apb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - hlcdc: hlcdc@f0000000 { - compatible = "atmel,sama5d4-hlcdc"; - reg = <0xf0000000 0x4000>; - interrupts = <51 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 51>, <&pmc PMC_TYPE_SYSTEM 3>, <&clk32k>; - clock-names = "periph_clk","sys_clk", "slow_clk"; - status = "disabled"; - - hlcdc-display-controller { - compatible = "atmel,hlcdc-display-controller"; - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - }; - - hlcdc_pwm: hlcdc-pwm { - compatible = "atmel,hlcdc-pwm"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd_pwm>; - #pwm-cells = <3>; - }; - }; - - dma1: dma-controller@f0004000 { - compatible = "atmel,sama5d4-dma"; - reg = <0xf0004000 0x200>; - interrupts = <50 IRQ_TYPE_LEVEL_HIGH 0>; - #dma-cells = <1>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 50>; - clock-names = "dma_clk"; - }; - - isi: isi@f0008000 { - compatible = "atmel,at91sam9g45-isi"; - reg = <0xf0008000 0x4000>; - interrupts = <52 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_isi_data_0_7>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 52>; - clock-names = "isi_clk"; - status = "disabled"; - port { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - ramc0: ramc@f0010000 { - compatible = "atmel,sama5d3-ddramc"; - reg = <0xf0010000 0x200>; - clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_PERIPHERAL 16>; - clock-names = "ddrck", "mpddr"; - }; - - dma0: dma-controller@f0014000 { - compatible = "atmel,sama5d4-dma"; - reg = <0xf0014000 0x200>; - interrupts = <8 IRQ_TYPE_LEVEL_HIGH 0>; - #dma-cells = <1>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; - clock-names = "dma_clk"; - }; - - pmc: pmc@f0018000 { - compatible = "atmel,sama5d4-pmc", "syscon"; - reg = <0xf0018000 0x120>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - #clock-cells = <2>; - clocks = <&clk32k>, <&main_xtal>; - clock-names = "slow_clk", "main_xtal"; - }; - - mmc0: mmc@f8000000 { - compatible = "atmel,hsmci"; - reg = <0xf8000000 0x600>; - interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>; - dmas = <&dma1 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(0))>; - dma-names = "rxtx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 35>; - clock-names = "mci_clk"; - }; - - uart0: serial@f8004000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xf8004000 0x100>; - interrupts = <27 IRQ_TYPE_LEVEL_HIGH 5>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(22))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(23))>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 27>; - clock-names = "usart"; - status = "disabled"; - }; - - ssc0: ssc@f8008000 { - compatible = "atmel,at91sam9g45-ssc"; - reg = <0xf8008000 0x4000>; - interrupts = <48 IRQ_TYPE_LEVEL_HIGH 0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; - dmas = <&dma1 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(26))>, - <&dma1 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(27))>; - dma-names = "tx", "rx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 48>; - clock-names = "pclk"; - status = "disabled"; - }; - - pwm0: pwm@f800c000 { - compatible = "atmel,sama5d3-pwm"; - reg = <0xf800c000 0x300>; - interrupts = <43 IRQ_TYPE_LEVEL_HIGH 4>; - #pwm-cells = <3>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 43>; - status = "disabled"; - }; - - spi0: spi@f8010000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "atmel,at91rm9200-spi"; - reg = <0xf8010000 0x100>; - interrupts = <37 IRQ_TYPE_LEVEL_HIGH 3>; - dmas = <&dma1 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(10))>, - <&dma1 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(11))>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 37>; - clock-names = "spi_clk"; - status = "disabled"; - }; - - i2c0: i2c@f8014000 { - compatible = "atmel,sama5d4-i2c"; - reg = <0xf8014000 0x4000>; - interrupts = <32 IRQ_TYPE_LEVEL_HIGH 6>; - dmas = <&dma1 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(2))>, - <&dma1 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(3))>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 32>; - status = "disabled"; - }; - - i2c1: i2c@f8018000 { - compatible = "atmel,sama5d4-i2c"; - reg = <0xf8018000 0x4000>; - interrupts = <33 IRQ_TYPE_LEVEL_HIGH 6>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(4))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(5))>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 33>; - status = "disabled"; - }; - - tcb0: timer@f801c000 { - compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xf801c000 0x100>; - interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 40>, <&clk32k>; - clock-names = "t0_clk", "slow_clk"; - }; - - macb0: ethernet@f8020000 { - compatible = "atmel,sama5d4-gem"; - reg = <0xf8020000 0x100>; - interrupts = <54 IRQ_TYPE_LEVEL_HIGH 3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_macb0_rmii>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 54>, <&pmc PMC_TYPE_PERIPHERAL 54>; - clock-names = "hclk", "pclk"; - status = "disabled"; - }; - - i2c2: i2c@f8024000 { - compatible = "atmel,sama5d4-i2c"; - reg = <0xf8024000 0x4000>; - interrupts = <34 IRQ_TYPE_LEVEL_HIGH 6>; - dmas = <&dma1 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(6))>, - <&dma1 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(7))>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 34>; - status = "disabled"; - }; - - sfr: sfr@f8028000 { - compatible = "atmel,sama5d4-sfr", "syscon"; - reg = <0xf8028000 0x60>; - }; - - usart0: serial@f802c000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xf802c000 0x100>; - interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(36))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(37))>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart0 &pinctrl_usart0_rts &pinctrl_usart0_cts>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; - clock-names = "usart"; - status = "disabled"; - }; - - usart1: serial@f8030000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xf8030000 0x100>; - interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(38))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(39))>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts &pinctrl_usart1_cts>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; - clock-names = "usart"; - status = "disabled"; - }; - - mmc1: mmc@fc000000 { - compatible = "atmel,hsmci"; - reg = <0xfc000000 0x600>; - interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>; - dmas = <&dma1 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(1))>; - dma-names = "rxtx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 36>; - clock-names = "mci_clk"; - }; - - uart1: serial@fc004000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xfc004000 0x100>; - interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(24))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(25))>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 28>; - clock-names = "usart"; - status = "disabled"; - }; - - usart2: serial@fc008000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xfc008000 0x100>; - interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>; - dmas = <&dma1 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(16))>, - <&dma1 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(17))>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart2 &pinctrl_usart2_rts &pinctrl_usart2_cts>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 29>; - clock-names = "usart"; - status = "disabled"; - }; - - usart3: serial@fc00c000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xfc00c000 0x100>; - interrupts = <30 IRQ_TYPE_LEVEL_HIGH 5>; - dmas = <&dma1 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(18))>, - <&dma1 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(19))>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart3>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 30>; - clock-names = "usart"; - status = "disabled"; - }; - - usart4: serial@fc010000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xfc010000 0x100>; - interrupts = <31 IRQ_TYPE_LEVEL_HIGH 5>; - dmas = <&dma1 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(20))>, - <&dma1 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(21))>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart4>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 31>; - clock-names = "usart"; - status = "disabled"; - }; - - ssc1: ssc@fc014000 { - compatible = "atmel,at91sam9g45-ssc"; - reg = <0xfc014000 0x4000>; - interrupts = <49 IRQ_TYPE_LEVEL_HIGH 0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; - dmas = <&dma1 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(28))>, - <&dma1 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(29))>; - dma-names = "tx", "rx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 49>; - clock-names = "pclk"; - status = "disabled"; - }; - - spi1: spi@fc018000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "atmel,at91rm9200-spi"; - reg = <0xfc018000 0x100>; - interrupts = <38 IRQ_TYPE_LEVEL_HIGH 3>; - dmas = <&dma1 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(12))>, - <&dma1 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(13))>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; - clock-names = "spi_clk"; - status = "disabled"; - }; - - spi2: spi@fc01c000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "atmel,at91rm9200-spi"; - reg = <0xfc01c000 0x100>; - interrupts = <39 IRQ_TYPE_LEVEL_HIGH 3>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(14))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(15))>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; - clock-names = "spi_clk"; - status = "disabled"; - }; - - tcb1: timer@fc020000 { - compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xfc020000 0x100>; - interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 41>, <&clk32k>; - clock-names = "t0_clk", "slow_clk"; - }; - - tcb2: timer@fc024000 { - compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xfc024000 0x100>; - interrupts = <42 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 42>, <&clk32k>; - clock-names = "t0_clk", "slow_clk"; - }; - - macb1: ethernet@fc028000 { - compatible = "atmel,sama5d4-gem"; - reg = <0xfc028000 0x100>; - interrupts = <55 IRQ_TYPE_LEVEL_HIGH 3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_macb1_rmii>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 55>, <&pmc PMC_TYPE_PERIPHERAL 55>; - clock-names = "hclk", "pclk"; - status = "disabled"; - }; - - trng@fc030000 { - compatible = "atmel,at91sam9g45-trng"; - reg = <0xfc030000 0x100>; - interrupts = <53 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 53>; - }; - - adc0: adc@fc034000 { - compatible = "atmel,at91sam9x5-adc"; - reg = <0xfc034000 0x100>; - interrupts = <44 IRQ_TYPE_LEVEL_HIGH 5>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 44>, - <&adc_op_clk>; - clock-names = "adc_clk", "adc_op_clk"; - atmel,adc-channels-used = <0x01f>; - atmel,adc-startup-time = <40>; - atmel,adc-use-external-triggers; - atmel,adc-vref = <3000>; - atmel,adc-res = <8 10>; - atmel,adc-sample-hold-time = <11>; - atmel,adc-res-names = "lowres", "highres"; - atmel,adc-ts-pressure-threshold = <10000>; - status = "disabled"; - - trigger0 { - trigger-name = "external-rising"; - trigger-value = <0x1>; - trigger-external; - }; - trigger1 { - trigger-name = "external-falling"; - trigger-value = <0x2>; - trigger-external; - }; - trigger2 { - trigger-name = "external-any"; - trigger-value = <0x3>; - trigger-external; - }; - trigger3 { - trigger-name = "continuous"; - trigger-value = <0x6>; - }; - }; - - aes@fc044000 { - compatible = "atmel,at91sam9g46-aes"; - reg = <0xfc044000 0x100>; - interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; - dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(41))>, - <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(40))>; - dma-names = "tx", "rx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 12>; - clock-names = "aes_clk"; - status = "okay"; - }; - - tdes@fc04c000 { - compatible = "atmel,at91sam9g46-tdes"; - reg = <0xfc04c000 0x100>; - interrupts = <14 IRQ_TYPE_LEVEL_HIGH 0>; - dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(42))>, - <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(43))>; - dma-names = "tx", "rx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; - clock-names = "tdes_clk"; - status = "okay"; - }; - - sha@fc050000 { - compatible = "atmel,at91sam9g46-sha"; - reg = <0xfc050000 0x100>; - interrupts = <15 IRQ_TYPE_LEVEL_HIGH 0>; - dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(44))>; - dma-names = "tx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 15>; - clock-names = "sha_clk"; - status = "okay"; - }; - - hsmc: smc@fc05c000 { - compatible = "atmel,sama5d3-smc", "syscon", "simple-mfd"; - reg = <0xfc05c000 0x1000>; - interrupts = <22 IRQ_TYPE_LEVEL_HIGH 6>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - pmecc: ecc-engine@ffffc070 { - compatible = "atmel,sama5d4-pmecc"; - reg = <0xfc05c070 0x490>, - <0xfc05c500 0x100>; - }; - }; - - reset_controller: rstc@fc068600 { - compatible = "atmel,sama5d3-rstc", "atmel,at91sam9g45-rstc"; - reg = <0xfc068600 0x10>; - clocks = <&clk32k>; - }; - - shutdown_controller: shdwc@fc068610 { - compatible = "atmel,at91sam9x5-shdwc"; - reg = <0xfc068610 0x10>; - clocks = <&clk32k>; - }; - - pit: timer@fc068630 { - compatible = "atmel,at91sam9260-pit"; - reg = <0xfc068630 0x10>; - interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>; - clocks = <&pmc PMC_TYPE_CORE PMC_MCK2>; - }; - - watchdog: watchdog@fc068640 { - compatible = "atmel,sama5d4-wdt"; - reg = <0xfc068640 0x10>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&clk32k>; - status = "disabled"; - }; - - clk32k: sckc@fc068650 { - compatible = "atmel,sama5d4-sckc"; - reg = <0xfc068650 0x4>; - #clock-cells = <0>; - clocks = <&slow_xtal>; - }; - - rtc@fc0686b0 { - compatible = "atmel,at91rm9200-rtc"; - reg = <0xfc0686b0 0x30>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&clk32k>; - }; - - dbgu: serial@fc069000 { - compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; - reg = <0xfc069000 0x200>; - interrupts = <45 IRQ_TYPE_LEVEL_HIGH 7>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_dbgu>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 45>; - clock-names = "usart"; - status = "disabled"; - }; - - - pinctrl: pinctrl@fc06a000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "atmel,sama5d3-pinctrl", "atmel,at91sam9x5-pinctrl", "simple-bus"; - ranges = <0xfc068000 0xfc068000 0x100 - 0xfc06a000 0xfc06a000 0x4000>; - /* WARNING: revisit as pin spec has changed */ - atmel,mux-mask = < - /* A B C */ - 0xffffffff 0x3ffcfe7c 0x1c010101 /* pioA */ - 0x7fffffff 0xfffccc3a 0x3f00cc3a /* pioB */ - 0xffffffff 0x3ff83fff 0xff00ffff /* pioC */ - 0x0003ff00 0x8002a800 0x00000000 /* pioD */ - 0xffffffff 0x7fffffff 0x76fff1bf /* pioE */ - >; - - pioA: gpio@fc06a000 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfc06a000 0x100>; - interrupts = <23 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; - }; - - pioB: gpio@fc06b000 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfc06b000 0x100>; - interrupts = <24 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 24>; - }; - - pioC: gpio@fc06c000 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfc06c000 0x100>; - interrupts = <25 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 25>; - }; - - pioD: gpio@fc068000 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfc068000 0x100>; - interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; - }; - - pioE: gpio@fc06d000 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfc06d000 0x100>; - interrupts = <26 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 26>; - }; - - /* pinctrl pin settings */ - adc0 { - pinctrl_adc0_adtrg: adc0_adtrg { - atmel,pins = - ; /* conflicts with USBA_VBUS */ - }; - pinctrl_adc0_ad0: adc0_ad0 { - atmel,pins = - ; - }; - pinctrl_adc0_ad1: adc0_ad1 { - atmel,pins = - ; - }; - pinctrl_adc0_ad2: adc0_ad2 { - atmel,pins = - ; - }; - pinctrl_adc0_ad3: adc0_ad3 { - atmel,pins = - ; - }; - pinctrl_adc0_ad4: adc0_ad4 { - atmel,pins = - ; - }; - }; - - dbgu { - pinctrl_dbgu: dbgu-0 { - atmel,pins = - ; /* conflicts with D15 and TDO */ - }; - }; - - ebi { - pinctrl_ebi_addr: ebi-addr-0 { - atmel,pins = - ; - }; - - pinctrl_ebi_nand_addr: ebi-addr-1 { - atmel,pins = - ; - }; - - pinctrl_ebi_cs0: ebi-cs0-0 { - atmel,pins = - ; - }; - - pinctrl_ebi_cs1: ebi-cs1-0 { - atmel,pins = - ; - }; - - pinctrl_ebi_cs2: ebi-cs2-0 { - atmel,pins = - ; - }; - - pinctrl_ebi_cs3: ebi-cs3-0 { - atmel,pins = - ; - }; - - pinctrl_ebi_data_0_7: ebi-data-lsb-0 { - atmel,pins = - ; - }; - - pinctrl_ebi_data_8_15: ebi-data-msb-0 { - atmel,pins = - ; - }; - - pinctrl_ebi_nandrdy: ebi-nandrdy-0 { - atmel,pins = - ; - }; - - pinctrl_ebi_nrd_nandoe: ebi-nrd-nandoe-0 { - atmel,pins = - ; - }; - - pinctrl_ebi_nwait: ebi-nwait-0 { - atmel,pins = - ; - }; - - pinctrl_ebi_nwe_nandwe: ebi-nwe-nandwe-0 { - atmel,pins = - ; - }; - - pinctrl_ebi_nwr1_nbs1: ebi-nwr1-nbs1-0 { - atmel,pins = - ; - }; - }; - - i2c0 { - pinctrl_i2c0: i2c0-0 { - atmel,pins = - ; - }; - }; - - i2c1 { - pinctrl_i2c1: i2c1-0 { - atmel,pins = - ; /* TWCK1, conflicts with UART0 TX and DIBN */ - }; - }; - - i2c2 { - pinctrl_i2c2: i2c2-0 { - atmel,pins = - ; /* TWCK2, conflicts with RF0 */ - }; - }; - - isi { - pinctrl_isi_data_0_7: isi-0-data-0-7 { - atmel,pins = - ; /* ISI_HSYNC */ - }; - pinctrl_isi_data_8_9: isi-0-data-8-9 { - atmel,pins = - ; /* ISI_D9, conflicts with SPI0_MOSI, PWML2 */ - }; - pinctrl_isi_data_10_11: isi-0-data-10-11 { - atmel,pins = - ; /* ISI_D11, conflicts with SPI0_NPCS0, PWML3 */ - }; - }; - - lcd { - pinctrl_lcd_base: lcd-base-0 { - atmel,pins = - ; /* LCDPCK */ - }; - pinctrl_lcd_pwm: lcd-pwm-0 { - atmel,pins = ; /* LCDPWM */ - }; - pinctrl_lcd_rgb444: lcd-rgb-0 { - atmel,pins = - ; /* LCDD11 pin */ - }; - pinctrl_lcd_rgb565: lcd-rgb-1 { - atmel,pins = - ; /* LCDD15 pin */ - }; - pinctrl_lcd_rgb666: lcd-rgb-2 { - atmel,pins = - ; /* LCDD23 pin */ - }; - pinctrl_lcd_rgb777: lcd-rgb-3 { - atmel,pins = - /* LCDDAT0 conflicts with TMS */ - ; /* LCDD23 pin */ - }; - pinctrl_lcd_rgb888: lcd-rgb-4 { - atmel,pins = - ; /* LCDD23 pin */ - }; - }; - - macb0 { - pinctrl_macb0_rmii: macb0_rmii-0 { - atmel,pins = - ; - }; - }; - - macb1 { - pinctrl_macb1_rmii: macb1_rmii-0 { - atmel,pins = - ; - }; - }; - - mmc0 { - pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 { - atmel,pins = - ; - }; - pinctrl_mmc0_dat1_3: mmc0_dat1_3 { - atmel,pins = - ; - }; - pinctrl_mmc0_dat4_7: mmc0_dat4_7 { - atmel,pins = - ; - }; - }; - - mmc1 { - pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 { - atmel,pins = - ; - }; - pinctrl_mmc1_dat1_3: mmc1_dat1_3 { - atmel,pins = - ; - }; - }; - - nand0 { - pinctrl_nand: nand-0 { - atmel,pins = - ; /* PC12 periph A Data bit 7 */ - }; - }; - - spi0 { - pinctrl_spi0: spi0-0 { - atmel,pins = - ; - }; - }; - - ssc0 { - pinctrl_ssc0_tx: ssc0_tx { - atmel,pins = - ; /* TD0 */ - }; - - pinctrl_ssc0_rx: ssc0_rx { - atmel,pins = - ; /* RD0 */ - }; - }; - - ssc1 { - pinctrl_ssc1_tx: ssc1_tx { - atmel,pins = - ; /* TD1 */ - }; - - pinctrl_ssc1_rx: ssc1_rx { - atmel,pins = - ; /* RD1 */ - }; - }; - - spi1 { - pinctrl_spi1: spi1-0 { - atmel,pins = - ; - }; - }; - - spi2 { - pinctrl_spi2: spi2-0 { - atmel,pins = - ; - }; - }; - - uart0 { - pinctrl_uart0: uart0-0 { - atmel,pins = - ; - }; - }; - - uart1 { - pinctrl_uart1: uart1-0 { - atmel,pins = - ; - }; - }; - - usart0 { - pinctrl_usart0: usart0-0 { - atmel,pins = - ; - }; - pinctrl_usart0_rts: usart0_rts-0 { - atmel,pins = ; - }; - pinctrl_usart0_cts: usart0_cts-0 { - atmel,pins = ; - }; - }; - - usart1 { - pinctrl_usart1: usart1-0 { - atmel,pins = - ; - }; - pinctrl_usart1_rts: usart1_rts-0 { - atmel,pins = ; - }; - pinctrl_usart1_cts: usart1_cts-0 { - atmel,pins = ; - }; - }; - - usart2 { - pinctrl_usart2: usart2-0 { - atmel,pins = - ; - }; - pinctrl_usart2_rts: usart2_rts-0 { - atmel,pins = ; /* conflicts with G0_RX3, PWMH1 */ - }; - pinctrl_usart2_cts: usart2_cts-0 { - atmel,pins = ; /* conflicts with G0_TXER, ISI_VSYNC */ - }; - }; - - usart3 { - pinctrl_usart3: usart3-0 { - atmel,pins = - ; - }; - }; - - usart4 { - pinctrl_usart4: usart4-0 { - atmel,pins = - ; - }; - pinctrl_usart4_rts: usart4_rts-0 { - atmel,pins = ; /* conflicts with NWAIT, A19 */ - }; - pinctrl_usart4_cts: usart4_cts-0 { - atmel,pins = ; /* conflicts with A0/NBS0, MCI0_CDB */ - }; - }; - }; - - aic: interrupt-controller@fc06e000 { - #interrupt-cells = <3>; - compatible = "atmel,sama5d4-aic"; - interrupt-controller; - reg = <0xfc06e000 0x200>; - atmel,external-irqs = <56>; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/samsung_k3pe0e000b.dtsi b/sys/gnu/dts/arm/samsung_k3pe0e000b.dtsi deleted file mode 100644 index 9657a5cbc3a..00000000000 --- a/sys/gnu/dts/arm/samsung_k3pe0e000b.dtsi +++ /dev/null @@ -1,67 +0,0 @@ -/* - * Timings and Geometry for Samsung K3PE0E000B memory part - */ - -/ { - samsung_K3PE0E000B: lpddr2 { - compatible = "Samsung,K3PE0E000B","jedec,lpddr2-s4"; - density = <4096>; - io-width = <32>; - - tRPab-min-tck = <3>; - tRCD-min-tck = <3>; - tWR-min-tck = <3>; - tRASmin-min-tck = <3>; - tRRD-min-tck = <2>; - tWTR-min-tck = <2>; - tXP-min-tck = <2>; - tRTP-min-tck = <2>; - tCKE-min-tck = <3>; - tCKESR-min-tck = <3>; - tFAW-min-tck = <8>; - - timings_samsung_K3PE0E000B_533MHz: lpddr2-timings@0 { - compatible = "jedec,lpddr2-timings"; - min-freq = <10000000>; - max-freq = <533333333>; - tRPab = <21000>; - tRCD = <18000>; - tWR = <15000>; - tRAS-min = <42000>; - tRRD = <10000>; - tWTR = <7500>; - tXP = <7500>; - tRTP = <7500>; - tCKESR = <15000>; - tDQSCK-max = <5500>; - tFAW = <50000>; - tZQCS = <90000>; - tZQCL = <360000>; - tZQinit = <1000000>; - tRAS-max-ns = <70000>; - tDQSCK-max-derated = <6000>; - }; - - timings_samsung_K3PE0E000B_266MHz: lpddr2-timings@1 { - compatible = "jedec,lpddr2-timings"; - min-freq = <10000000>; - max-freq = <266666666>; - tRPab = <21000>; - tRCD = <18000>; - tWR = <15000>; - tRAS-min = <42000>; - tRRD = <10000>; - tWTR = <7500>; - tXP = <7500>; - tRTP = <7500>; - tCKESR = <15000>; - tDQSCK-max = <5500>; - tFAW = <50000>; - tZQCS = <90000>; - tZQCL = <360000>; - tZQinit = <1000000>; - tRAS-max-ns = <70000>; - tDQSCK-max-derated = <6000>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/sh73a0-kzm9g.dts b/sys/gnu/dts/arm/sh73a0-kzm9g.dts deleted file mode 100644 index 1916f31a30f..00000000000 --- a/sys/gnu/dts/arm/sh73a0-kzm9g.dts +++ /dev/null @@ -1,406 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the KZM-A9-GT board - * - * Copyright (C) 2012 Horms Solutions Ltd. - * - * Based on sh73a0-kzm9g.dts - * Copyright (C) 2012 Renesas Solutions Corp. - */ - -/dts-v1/; -#include "sh73a0.dtsi" -#include -#include -#include - -/ { - model = "KZM-A9-GT"; - compatible = "renesas,kzm9g", "renesas,sh73a0"; - - aliases { - serial0 = &scifa4; - }; - - cpus { - cpu@0 { - cpu0-supply = <&vdd_dvfs>; - operating-points = < - /* kHz uV */ - 1196000 1315000 - 598000 1175000 - 398667 1065000 - >; - voltage-tolerance = <1>; /* 1% */ - }; - }; - - chosen { - bootargs = "root=/dev/nfs ip=on ignore_loglevel rw"; - stdout-path = "serial0:115200n8"; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x20000000>; - }; - - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-name = "fixed-1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - vmmc_sdhi0: regulator-vmmc-sdhi0 { - compatible = "regulator-fixed"; - regulator-name = "SDHI0 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&pfc 15 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vmmc_sdhi2: regulator-vmmc-sdhi2 { - compatible = "regulator-fixed"; - regulator-name = "SDHI2 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&pfc 14 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - leds { - compatible = "gpio-leds"; - led1 { - gpios = <&pfc 20 GPIO_ACTIVE_LOW>; - label = "LED1"; - }; - led2 { - gpios = <&pfc 21 GPIO_ACTIVE_LOW>; - label = "LED2"; - }; - led3 { - gpios = <&pfc 22 GPIO_ACTIVE_LOW>; - label = "LED3"; - }; - led4 { - gpios = <&pfc 23 GPIO_ACTIVE_LOW>; - label = "LED4"; - }; - }; - - keyboard { - compatible = "gpio-keys"; - - back-key { - gpios = <&pcf8575 8 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW3"; - }; - - right-key { - gpios = <&pcf8575 9 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW2-R"; - }; - - left-key { - gpios = <&pcf8575 10 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW2-L"; - }; - - enter-key { - gpios = <&pcf8575 11 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW2-P"; - }; - - up-key { - gpios = <&pcf8575 12 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW2-U"; - }; - - down-key { - gpios = <&pcf8575 13 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW2-D"; - }; - - home-key { - gpios = <&pcf8575 14 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW1"; - wakeup-source; - }; - - wakeup-key { - gpios = <&pfc 159 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "NMI"; - wakeup-source; - }; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,format = "left_j"; - simple-audio-card,cpu { - sound-dai = <&sh_fsi2 0>; - }; - simple-audio-card,codec { - sound-dai = <&ak4648>; - bitclock-master; - frame-master; - system-clock-frequency = <11289600>; - }; - }; -}; - -&bsc { - ethernet@10000000 { - compatible = "smsc,lan9220", "smsc,lan9115"; - reg = <0x10000000 0x100>; - phy-mode = "mii"; - interrupt-parent = <&irqpin0>; - interrupts = <3 IRQ_TYPE_EDGE_FALLING>; - reg-io-width = <4>; - smsc,irq-push-pull; - smsc,save-mac-address; - vddvario-supply = <®_1p8v>; - vdd33a-supply = <®_3p3v>; - }; -}; - -&cmt1 { - status = "okay"; -}; - -&extal2_clk { - clock-frequency = <48000000>; -}; - -&i2c0 { - status = "okay"; - - compass@c { - compatible = "asahi-kasei,ak8975"; - reg = <0x0c>; - interrupt-parent = <&irqpin3>; - interrupts = <4 IRQ_TYPE_EDGE_FALLING>; - }; - - ak4648: codec@12 { - compatible = "asahi-kasei,ak4648"; - reg = <0x12>; - #sound-dai-cells = <0>; - }; - - accelerometer@1d { - compatible = "adi,adxl345"; - reg = <0x1d>; - interrupt-parent = <&irqpin3>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH>, - <3 IRQ_TYPE_LEVEL_HIGH>; - }; - - rtc@32 { - compatible = "ricoh,r2025sd"; - reg = <0x32>; - }; - - as3711@40 { - compatible = "ams,as3711"; - reg = <0x40>; - - regulators { - vdd_dvfs: sd1 { - regulator-name = "1.315V CPU"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - sd2 { - regulator-name = "1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - sd4 { - regulator-name = "1.215V"; - regulator-min-microvolt = <1215000>; - regulator-max-microvolt = <1235000>; - regulator-always-on; - regulator-boot-on; - }; - ldo2 { - regulator-name = "2.8V CPU"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - regulator-boot-on; - }; - ldo3 { - regulator-name = "3.0V CPU"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - regulator-boot-on; - }; - ldo4 { - regulator-name = "2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - regulator-boot-on; - }; - ldo5 { - regulator-name = "2.8V #2"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - regulator-boot-on; - }; - ldo7 { - regulator-name = "1.15V CPU"; - regulator-min-microvolt = <1150000>; - regulator-max-microvolt = <1150000>; - regulator-always-on; - regulator-boot-on; - }; - ldo8 { - regulator-name = "1.15V CPU #2"; - regulator-min-microvolt = <1150000>; - regulator-max-microvolt = <1150000>; - regulator-always-on; - regulator-boot-on; - }; - }; - }; -}; - -&i2c1 { - status = "okay"; - - touchscreen@55 { - compatible = "sitronix,st1232"; - reg = <0x55>; - interrupt-parent = <&irqpin1>; - interrupts = <0 IRQ_TYPE_EDGE_FALLING>; - }; -}; - -&i2c3 { - pinctrl-0 = <&i2c3_pins>; - pinctrl-names = "default"; - status = "okay"; - - pcf8575: gpio@20 { - compatible = "nxp,pcf8575"; - reg = <0x20>; - interrupt-parent = <&irqpin2>; - interrupts = <3 IRQ_TYPE_EDGE_FALLING>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; -}; - -&mmcif { - pinctrl-0 = <&mmcif_pins>; - pinctrl-names = "default"; - - bus-width = <8>; - vmmc-supply = <®_1p8v>; - status = "okay"; -}; - -&pfc { - i2c3_pins: i2c3 { - groups = "i2c3_1"; - function = "i2c3"; - }; - - mmcif_pins: mmc { - mux { - groups = "mmc0_data8_0", "mmc0_ctrl_0"; - function = "mmc0"; - }; - cfg { - groups = "mmc0_data8_0"; - pins = "PORT279"; - bias-pull-up; - }; - }; - - scifa4_pins: scifa4 { - groups = "scifa4_data", "scifa4_ctrl"; - function = "scifa4"; - }; - - sdhi0_pins: sd0 { - groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd", "sdhi0_wp"; - function = "sdhi0"; - }; - - sdhi2_pins: sd2 { - groups = "sdhi2_data4", "sdhi2_ctrl"; - function = "sdhi2"; - }; - - fsia_pins: sounda { - groups = "fsia_mclk_in", "fsia_sclk_in", - "fsia_data_in", "fsia_data_out"; - function = "fsia"; - }; -}; - -&scifa4 { - pinctrl-0 = <&scifa4_pins>; - pinctrl-names = "default"; - - uart-has-rtscts; - status = "okay"; -}; - -&sdhi0 { - pinctrl-0 = <&sdhi0_pins>; - pinctrl-names = "default"; - - vmmc-supply = <&vmmc_sdhi0>; - bus-width = <4>; - status = "okay"; -}; - -&sdhi2 { - pinctrl-0 = <&sdhi2_pins>; - pinctrl-names = "default"; - - vmmc-supply = <&vmmc_sdhi2>; - bus-width = <4>; - broken-cd; - status = "okay"; -}; - -&sh_fsi2 { - pinctrl-0 = <&fsia_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sh73a0.dtsi b/sys/gnu/dts/arm/sh73a0.dtsi deleted file mode 100644 index c134154bcce..00000000000 --- a/sys/gnu/dts/arm/sh73a0.dtsi +++ /dev/null @@ -1,948 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the SH-Mobile AG5 (R8A73A00/SH73A0) SoC - * - * Copyright (C) 2012 Renesas Solutions Corp. - */ - -#include -#include -#include - -/ { - compatible = "renesas,sh73a0"; - interrupt-parent = <&gic>; - #address-cells = <1>; - #size-cells = <1>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - clock-frequency = <1196000000>; - clocks = <&cpg_clocks SH73A0_CLK_Z>; - power-domains = <&pd_a2sl>; - next-level-cache = <&L2>; - }; - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <1>; - clock-frequency = <1196000000>; - clocks = <&cpg_clocks SH73A0_CLK_Z>; - power-domains = <&pd_a2sl>; - next-level-cache = <&L2>; - }; - }; - - timer@f0000200 { - compatible = "arm,cortex-a9-global-timer"; - reg = <0xf0000200 0x100>; - interrupts = ; - clocks = <&periph_clk>; - }; - - timer@f0000600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0xf0000600 0x20>; - interrupts = ; - clocks = <&periph_clk>; - }; - - gic: interrupt-controller@f0001000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0xf0001000 0x1000>, - <0xf0000100 0x100>; - }; - - L2: cache-controller@f0100000 { - compatible = "arm,pl310-cache"; - reg = <0xf0100000 0x1000>; - interrupts = ; - power-domains = <&pd_a3sm>; - arm,data-latency = <3 3 3>; - arm,tag-latency = <2 2 2>; - arm,shared-override; - cache-unified; - cache-level = <2>; - }; - - sbsc2: memory-controller@fb400000 { - compatible = "renesas,sbsc-sh73a0"; - reg = <0xfb400000 0x400>; - interrupts = , - ; - interrupt-names = "sec", "temp"; - power-domains = <&pd_a4bc1>; - }; - - sbsc1: memory-controller@fe400000 { - compatible = "renesas,sbsc-sh73a0"; - reg = <0xfe400000 0x400>; - interrupts = , - ; - interrupt-names = "sec", "temp"; - power-domains = <&pd_a4bc0>; - }; - - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts = , - ; - interrupt-affinity = <&cpu0>, <&cpu1>; - }; - - cmt1: timer@e6138000 { - compatible = "renesas,cmt-48-sh73a0", "renesas,cmt-48"; - reg = <0xe6138000 0x200>; - interrupts = ; - clocks = <&mstp3_clks SH73A0_CLK_CMT1>; - clock-names = "fck"; - power-domains = <&pd_c5>; - status = "disabled"; - }; - - irqpin0: interrupt-controller@e6900000 { - compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0xe6900000 4>, - <0xe6900010 4>, - <0xe6900020 1>, - <0xe6900040 1>, - <0xe6900060 1>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&mstp5_clks SH73A0_CLK_INTCA0>; - power-domains = <&pd_a4s>; - control-parent; - }; - - irqpin1: interrupt-controller@e6900004 { - compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0xe6900004 4>, - <0xe6900014 4>, - <0xe6900024 1>, - <0xe6900044 1>, - <0xe6900064 1>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&mstp5_clks SH73A0_CLK_INTCA0>; - power-domains = <&pd_a4s>; - control-parent; - }; - - irqpin2: interrupt-controller@e6900008 { - compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0xe6900008 4>, - <0xe6900018 4>, - <0xe6900028 1>, - <0xe6900048 1>, - <0xe6900068 1>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&mstp5_clks SH73A0_CLK_INTCA0>; - power-domains = <&pd_a4s>; - control-parent; - }; - - irqpin3: interrupt-controller@e690000c { - compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0xe690000c 4>, - <0xe690001c 4>, - <0xe690002c 1>, - <0xe690004c 1>, - <0xe690006c 1>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&mstp5_clks SH73A0_CLK_INTCA0>; - power-domains = <&pd_a4s>; - control-parent; - }; - - i2c0: i2c@e6820000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic"; - reg = <0xe6820000 0x425>; - interrupts = , - , - , - ; - clocks = <&mstp1_clks SH73A0_CLK_IIC0>; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - i2c1: i2c@e6822000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic"; - reg = <0xe6822000 0x425>; - interrupts = , - , - , - ; - clocks = <&mstp3_clks SH73A0_CLK_IIC1>; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - i2c2: i2c@e6824000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic"; - reg = <0xe6824000 0x425>; - interrupts = , - , - , - ; - clocks = <&mstp0_clks SH73A0_CLK_IIC2>; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - i2c3: i2c@e6826000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic"; - reg = <0xe6826000 0x425>; - interrupts = , - , - , - ; - clocks = <&mstp4_clks SH73A0_CLK_IIC3>; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - i2c4: i2c@e6828000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic"; - reg = <0xe6828000 0x425>; - interrupts = , - , - , - ; - clocks = <&mstp4_clks SH73A0_CLK_IIC4>; - power-domains = <&pd_c5>; - status = "disabled"; - }; - - mmcif: mmc@e6bd0000 { - compatible = "renesas,mmcif-sh73a0", "renesas,sh-mmcif"; - reg = <0xe6bd0000 0x100>; - interrupts = , - ; - clocks = <&mstp3_clks SH73A0_CLK_MMCIF0>; - power-domains = <&pd_a3sp>; - reg-io-width = <4>; - status = "disabled"; - }; - - msiof0: spi@e6e20000 { - compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof"; - reg = <0xe6e20000 0x0064>; - interrupts = ; - clocks = <&mstp0_clks SH73A0_CLK_MSIOF0>; - power-domains = <&pd_a3sp>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof1: spi@e6e10000 { - compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof"; - reg = <0xe6e10000 0x0064>; - interrupts = ; - clocks = <&mstp2_clks SH73A0_CLK_MSIOF1>; - power-domains = <&pd_a3sp>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof2: spi@e6e00000 { - compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof"; - reg = <0xe6e00000 0x0064>; - interrupts = ; - clocks = <&mstp2_clks SH73A0_CLK_MSIOF2>; - power-domains = <&pd_a3sp>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof3: spi@e6c90000 { - compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof"; - reg = <0xe6c90000 0x0064>; - interrupts = ; - clocks = <&mstp2_clks SH73A0_CLK_MSIOF3>; - power-domains = <&pd_a3sp>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - sdhi0: sd@ee100000 { - compatible = "renesas,sdhi-sh73a0"; - reg = <0xee100000 0x100>; - interrupts = , - , - ; - clocks = <&mstp3_clks SH73A0_CLK_SDHI0>; - power-domains = <&pd_a3sp>; - cap-sd-highspeed; - status = "disabled"; - }; - - /* SDHI1 and SDHI2 have no CD pins, no need for CD IRQ */ - sdhi1: sd@ee120000 { - compatible = "renesas,sdhi-sh73a0"; - reg = <0xee120000 0x100>; - interrupts = , - ; - clocks = <&mstp3_clks SH73A0_CLK_SDHI1>; - power-domains = <&pd_a3sp>; - disable-wp; - cap-sd-highspeed; - status = "disabled"; - }; - - sdhi2: sd@ee140000 { - compatible = "renesas,sdhi-sh73a0"; - reg = <0xee140000 0x100>; - interrupts = , - ; - clocks = <&mstp3_clks SH73A0_CLK_SDHI2>; - power-domains = <&pd_a3sp>; - disable-wp; - cap-sd-highspeed; - status = "disabled"; - }; - - scifa0: serial@e6c40000 { - compatible = "renesas,scifa-sh73a0", "renesas,scifa"; - reg = <0xe6c40000 0x100>; - interrupts = ; - clocks = <&mstp2_clks SH73A0_CLK_SCIFA0>; - clock-names = "fck"; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - scifa1: serial@e6c50000 { - compatible = "renesas,scifa-sh73a0", "renesas,scifa"; - reg = <0xe6c50000 0x100>; - interrupts = ; - clocks = <&mstp2_clks SH73A0_CLK_SCIFA1>; - clock-names = "fck"; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - scifa2: serial@e6c60000 { - compatible = "renesas,scifa-sh73a0", "renesas,scifa"; - reg = <0xe6c60000 0x100>; - interrupts = ; - clocks = <&mstp2_clks SH73A0_CLK_SCIFA2>; - clock-names = "fck"; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - scifa3: serial@e6c70000 { - compatible = "renesas,scifa-sh73a0", "renesas,scifa"; - reg = <0xe6c70000 0x100>; - interrupts = ; - clocks = <&mstp2_clks SH73A0_CLK_SCIFA3>; - clock-names = "fck"; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - scifa4: serial@e6c80000 { - compatible = "renesas,scifa-sh73a0", "renesas,scifa"; - reg = <0xe6c80000 0x100>; - interrupts = ; - clocks = <&mstp2_clks SH73A0_CLK_SCIFA4>; - clock-names = "fck"; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - scifa5: serial@e6cb0000 { - compatible = "renesas,scifa-sh73a0", "renesas,scifa"; - reg = <0xe6cb0000 0x100>; - interrupts = ; - clocks = <&mstp2_clks SH73A0_CLK_SCIFA5>; - clock-names = "fck"; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - scifa6: serial@e6cc0000 { - compatible = "renesas,scifa-sh73a0", "renesas,scifa"; - reg = <0xe6cc0000 0x100>; - interrupts = ; - clocks = <&mstp3_clks SH73A0_CLK_SCIFA6>; - clock-names = "fck"; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - scifa7: serial@e6cd0000 { - compatible = "renesas,scifa-sh73a0", "renesas,scifa"; - reg = <0xe6cd0000 0x100>; - interrupts = ; - clocks = <&mstp2_clks SH73A0_CLK_SCIFA7>; - clock-names = "fck"; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - scifb: serial@e6c30000 { - compatible = "renesas,scifb-sh73a0", "renesas,scifb"; - reg = <0xe6c30000 0x100>; - interrupts = ; - clocks = <&mstp2_clks SH73A0_CLK_SCIFB>; - clock-names = "fck"; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - pfc: pin-controller@e6050000 { - compatible = "renesas,pfc-sh73a0"; - reg = <0xe6050000 0x8000>, - <0xe605801c 0x1c>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = - <&pfc 0 0 119>, <&pfc 128 128 37>, <&pfc 192 192 91>, - <&pfc 288 288 22>; - interrupts-extended = - <&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>, - <&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>, - <&irqpin1 0 0>, <&irqpin1 1 0>, <&irqpin1 2 0>, <&irqpin1 3 0>, - <&irqpin1 4 0>, <&irqpin1 5 0>, <&irqpin1 6 0>, <&irqpin1 7 0>, - <&irqpin2 0 0>, <&irqpin2 1 0>, <&irqpin2 2 0>, <&irqpin2 3 0>, - <&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>, - <&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>, - <&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>; - power-domains = <&pd_c5>; - }; - - sysc: system-controller@e6180000 { - compatible = "renesas,sysc-sh73a0", "renesas,sysc-rmobile"; - reg = <0xe6180000 0x8000>, <0xe6188000 0x8000>; - - pm-domains { - pd_c5: c5 { - #address-cells = <1>; - #size-cells = <0>; - #power-domain-cells = <0>; - - pd_c4: c4@0 { - reg = <0>; - #power-domain-cells = <0>; - }; - - pd_d4: d4@1 { - reg = <1>; - #power-domain-cells = <0>; - }; - - pd_a4bc0: a4bc0@4 { - reg = <4>; - #power-domain-cells = <0>; - }; - - pd_a4bc1: a4bc1@5 { - reg = <5>; - #power-domain-cells = <0>; - }; - - pd_a4lc0: a4lc0@6 { - reg = <6>; - #power-domain-cells = <0>; - }; - - pd_a4lc1: a4lc1@7 { - reg = <7>; - #power-domain-cells = <0>; - }; - - pd_a4mp: a4mp@8 { - reg = <8>; - #address-cells = <1>; - #size-cells = <0>; - #power-domain-cells = <0>; - - pd_a3mp: a3mp@9 { - reg = <9>; - #power-domain-cells = <0>; - }; - - pd_a3vc: a3vc@10 { - reg = <10>; - #power-domain-cells = <0>; - }; - }; - - pd_a4rm: a4rm@12 { - reg = <12>; - #address-cells = <1>; - #size-cells = <0>; - #power-domain-cells = <0>; - - pd_a3r: a3r@13 { - reg = <13>; - #address-cells = <1>; - #size-cells = <0>; - #power-domain-cells = <0>; - - pd_a2rv: a2rv@14 { - reg = <14>; - #address-cells = <1>; - #size-cells = <0>; - #power-domain-cells = <0>; - }; - }; - }; - - pd_a4s: a4s@16 { - reg = <16>; - #address-cells = <1>; - #size-cells = <0>; - #power-domain-cells = <0>; - - pd_a3sp: a3sp@17 { - reg = <17>; - #power-domain-cells = <0>; - }; - - pd_a3sg: a3sg@18 { - reg = <18>; - #power-domain-cells = <0>; - }; - - pd_a3sm: a3sm@19 { - reg = <19>; - #address-cells = <1>; - #size-cells = <0>; - #power-domain-cells = <0>; - - pd_a2sl: a2sl@20 { - reg = <20>; - #power-domain-cells = <0>; - }; - }; - }; - }; - }; - }; - - sh_fsi2: sound@ec230000 { - #sound-dai-cells = <1>; - compatible = "renesas,fsi2-sh73a0", "renesas,sh_fsi2"; - reg = <0xec230000 0x400>; - interrupts = ; - power-domains = <&pd_a4mp>; - status = "disabled"; - }; - - bsc: bus@fec10000 { - compatible = "renesas,bsc-sh73a0", "renesas,bsc", - "simple-pm-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x20000000>; - reg = <0xfec10000 0x400>; - interrupts = ; - clocks = <&zb_clk>; - power-domains = <&pd_a4s>; - }; - - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - /* External root clocks */ - extalr_clk: extalr { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - extal1_clk: extal1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <26000000>; - }; - extal2_clk: extal2 { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - extcki_clk: extcki { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value can be overridden by the board. */ - clock-frequency = <0>; - }; - fsiack_clk: fsiack { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value can be overridden by the board. */ - clock-frequency = <0>; - }; - fsibck_clk: fsibck { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value can be overridden by the board. */ - clock-frequency = <0>; - }; - - /* Special CPG clocks */ - cpg_clocks: cpg_clocks@e6150000 { - compatible = "renesas,sh73a0-cpg-clocks"; - reg = <0xe6150000 0x10000>; - clocks = <&extal1_clk>, <&extal2_clk>; - #clock-cells = <1>; - clock-output-names = "main", "pll0", "pll1", "pll2", - "pll3", "dsi0phy", "dsi1phy", - "zg", "m3", "b", "m1", "m2", - "z", "zx", "hp"; - }; - - /* Variable factor clocks (DIV6) */ - vclk1_clk: vclk1@e6150008 { - compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; - reg = <0xe6150008 4>; - clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, - <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>, - <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>, - <0>; - #clock-cells = <0>; - }; - vclk2_clk: vclk2@e615000c { - compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; - reg = <0xe615000c 4>; - clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, - <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>, - <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>, - <0>; - #clock-cells = <0>; - }; - vclk3_clk: vclk3@e615001c { - compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; - reg = <0xe615001c 4>; - clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, - <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>, - <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>, - <0>; - #clock-cells = <0>; - }; - zb_clk: zb_clk@e6150010 { - compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; - reg = <0xe6150010 4>; - clocks = <&pll1_div2_clk>, <0>, - <&cpg_clocks SH73A0_CLK_PLL2>, <0>; - #clock-cells = <0>; - clock-output-names = "zb"; - }; - flctl_clk: flctlck@e6150014 { - compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; - reg = <0xe6150014 4>; - clocks = <&pll1_div2_clk>, <0>, - <&cpg_clocks SH73A0_CLK_PLL2>, <0>; - #clock-cells = <0>; - }; - sdhi0_clk: sdhi0ck@e6150074 { - compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; - reg = <0xe6150074 4>; - clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, - <&pll1_div13_clk>, <0>; - #clock-cells = <0>; - }; - sdhi1_clk: sdhi1ck@e6150078 { - compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; - reg = <0xe6150078 4>; - clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, - <&pll1_div13_clk>, <0>; - #clock-cells = <0>; - }; - sdhi2_clk: sdhi2ck@e615007c { - compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; - reg = <0xe615007c 4>; - clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, - <&pll1_div13_clk>, <0>; - #clock-cells = <0>; - }; - fsia_clk: fsia@e6150018 { - compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; - reg = <0xe6150018 4>; - clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, - <&fsiack_clk>, <&fsiack_clk>; - #clock-cells = <0>; - }; - fsib_clk: fsib@e6150090 { - compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; - reg = <0xe6150090 4>; - clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, - <&fsibck_clk>, <&fsibck_clk>; - #clock-cells = <0>; - }; - sub_clk: sub@e6150080 { - compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; - reg = <0xe6150080 4>; - clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, - <&extal2_clk>, <&extal2_clk>; - #clock-cells = <0>; - }; - spua_clk: spua@e6150084 { - compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; - reg = <0xe6150084 4>; - clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, - <&extal2_clk>, <&extal2_clk>; - #clock-cells = <0>; - }; - spuv_clk: spuv@e6150094 { - compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; - reg = <0xe6150094 4>; - clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, - <&extal2_clk>, <&extal2_clk>; - #clock-cells = <0>; - }; - msu_clk: msu@e6150088 { - compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; - reg = <0xe6150088 4>; - clocks = <&pll1_div2_clk>, <0>, - <&cpg_clocks SH73A0_CLK_PLL2>, <0>; - #clock-cells = <0>; - }; - hsi_clk: hsi@e615008c { - compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; - reg = <0xe615008c 4>; - clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, - <&pll1_div7_clk>, <0>; - #clock-cells = <0>; - }; - mfg1_clk: mfg1@e6150098 { - compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; - reg = <0xe6150098 4>; - clocks = <&pll1_div2_clk>, <0>, - <&cpg_clocks SH73A0_CLK_PLL2>, <0>; - #clock-cells = <0>; - }; - mfg2_clk: mfg2@e615009c { - compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; - reg = <0xe615009c 4>; - clocks = <&pll1_div2_clk>, <0>, - <&cpg_clocks SH73A0_CLK_PLL2>, <0>; - #clock-cells = <0>; - }; - dsit_clk: dsit@e6150060 { - compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; - reg = <0xe6150060 4>; - clocks = <&pll1_div2_clk>, <0>, - <&cpg_clocks SH73A0_CLK_PLL2>, <0>; - #clock-cells = <0>; - }; - dsi0p_clk: dsi0pck@e6150064 { - compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; - reg = <0xe6150064 4>; - clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, - <&cpg_clocks SH73A0_CLK_MAIN>, <&extal2_clk>, - <&extcki_clk>, <0>, <0>, <0>; - #clock-cells = <0>; - }; - - /* Fixed factor clocks */ - main_div2_clk: main_div2 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks SH73A0_CLK_MAIN>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - pll1_div2_clk: pll1_div2 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks SH73A0_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - pll1_div7_clk: pll1_div7 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks SH73A0_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <7>; - clock-mult = <1>; - }; - pll1_div13_clk: pll1_div13 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks SH73A0_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <13>; - clock-mult = <1>; - }; - periph_clk: periph { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks SH73A0_CLK_Z>; - #clock-cells = <0>; - clock-div = <4>; - clock-mult = <1>; - }; - - /* Gate clocks */ - mstp0_clks: mstp0_clks@e6150130 { - compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0xe6150130 4>, <0xe6150030 4>; - clocks = <&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>; - #clock-cells = <1>; - clock-indices = < - SH73A0_CLK_IIC2 SH73A0_CLK_MSIOF0 - >; - clock-output-names = - "iic2", "msiof0"; - }; - mstp1_clks: mstp1_clks@e6150134 { - compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0xe6150134 4>, <0xe6150038 4>; - clocks = <&cpg_clocks SH73A0_CLK_B>, - <&cpg_clocks SH73A0_CLK_B>, - <&cpg_clocks SH73A0_CLK_B>, - <&cpg_clocks SH73A0_CLK_B>, - <&sub_clk>, <&cpg_clocks SH73A0_CLK_B>, - <&cpg_clocks SH73A0_CLK_HP>, - <&cpg_clocks SH73A0_CLK_ZG>, - <&cpg_clocks SH73A0_CLK_B>; - #clock-cells = <1>; - clock-indices = < - SH73A0_CLK_CEU1 SH73A0_CLK_CSI2_RX1 - SH73A0_CLK_CEU0 SH73A0_CLK_CSI2_RX0 - SH73A0_CLK_TMU0 SH73A0_CLK_DSITX0 - SH73A0_CLK_IIC0 SH73A0_CLK_SGX - SH73A0_CLK_LCDC0 - >; - clock-output-names = - "ceu1", "csi2_rx1", "ceu0", "csi2_rx0", - "tmu0", "dsitx0", "iic0", "sgx", "lcdc0"; - }; - mstp2_clks: mstp2_clks@e6150138 { - compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0xe6150138 4>, <0xe6150040 4>; - clocks = <&sub_clk>, <&cpg_clocks SH73A0_CLK_HP>, - <&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>, - <&sub_clk>, <&sub_clk>, <&sub_clk>, - <&sub_clk>, <&sub_clk>, <&sub_clk>, - <&sub_clk>, <&sub_clk>, <&sub_clk>; - #clock-cells = <1>; - clock-indices = < - SH73A0_CLK_SCIFA7 SH73A0_CLK_SY_DMAC - SH73A0_CLK_MP_DMAC SH73A0_CLK_MSIOF3 - SH73A0_CLK_MSIOF1 SH73A0_CLK_SCIFA5 - SH73A0_CLK_SCIFB SH73A0_CLK_MSIOF2 - SH73A0_CLK_SCIFA0 SH73A0_CLK_SCIFA1 - SH73A0_CLK_SCIFA2 SH73A0_CLK_SCIFA3 - SH73A0_CLK_SCIFA4 - >; - clock-output-names = - "scifa7", "sy_dmac", "mp_dmac", "msiof3", - "msiof1", "scifa5", "scifb", "msiof2", - "scifa0", "scifa1", "scifa2", "scifa3", - "scifa4"; - }; - mstp3_clks: mstp3_clks@e615013c { - compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0xe615013c 4>, <0xe6150048 4>; - clocks = <&sub_clk>, <&extalr_clk>, - <&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>, - <&cpg_clocks SH73A0_CLK_HP>, - <&cpg_clocks SH73A0_CLK_HP>, <&flctl_clk>, - <&sdhi0_clk>, <&sdhi1_clk>, - <&cpg_clocks SH73A0_CLK_HP>, <&sdhi2_clk>, - <&main_div2_clk>, <&main_div2_clk>, - <&main_div2_clk>, <&main_div2_clk>, - <&main_div2_clk>; - #clock-cells = <1>; - clock-indices = < - SH73A0_CLK_SCIFA6 SH73A0_CLK_CMT1 - SH73A0_CLK_FSI SH73A0_CLK_IRDA - SH73A0_CLK_IIC1 SH73A0_CLK_USB SH73A0_CLK_FLCTL - SH73A0_CLK_SDHI0 SH73A0_CLK_SDHI1 - SH73A0_CLK_MMCIF0 SH73A0_CLK_SDHI2 - SH73A0_CLK_TPU0 SH73A0_CLK_TPU1 - SH73A0_CLK_TPU2 SH73A0_CLK_TPU3 - SH73A0_CLK_TPU4 - >; - clock-output-names = - "scifa6", "cmt1", "fsi", "irda", "iic1", - "usb", "flctl", "sdhi0", "sdhi1", "mmcif0", "sdhi2", - "tpu0", "tpu1", "tpu2", "tpu3", "tpu4"; - }; - mstp4_clks: mstp4_clks@e6150140 { - compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0xe6150140 4>, <0xe615004c 4>; - clocks = <&cpg_clocks SH73A0_CLK_HP>, - <&cpg_clocks SH73A0_CLK_HP>, <&extalr_clk>; - #clock-cells = <1>; - clock-indices = < - SH73A0_CLK_IIC3 SH73A0_CLK_IIC4 - SH73A0_CLK_KEYSC - >; - clock-output-names = - "iic3", "iic4", "keysc"; - }; - mstp5_clks: mstp5_clks@e6150144 { - compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0xe6150144 4>, <0xe615003c 4>; - clocks = <&cpg_clocks SH73A0_CLK_HP>; - #clock-cells = <1>; - clock-indices = < - SH73A0_CLK_INTCA0 - >; - clock-output-names = - "intca0"; - }; - }; -}; diff --git a/sys/gnu/dts/arm/skeleton.dtsi b/sys/gnu/dts/arm/skeleton.dtsi deleted file mode 100644 index b41d241de2c..00000000000 --- a/sys/gnu/dts/arm/skeleton.dtsi +++ /dev/null @@ -1,13 +0,0 @@ -/* - * Skeleton device tree; the bare minimum needed to boot; just include and - * add a compatible value. The bootloader will typically populate the memory - * node. - */ - -/ { - #address-cells = <1>; - #size-cells = <1>; - chosen { }; - aliases { }; - memory { device_type = "memory"; reg = <0 0>; }; -}; diff --git a/sys/gnu/dts/arm/skeleton64.dtsi b/sys/gnu/dts/arm/skeleton64.dtsi deleted file mode 100644 index b5d7f36f33d..00000000000 --- a/sys/gnu/dts/arm/skeleton64.dtsi +++ /dev/null @@ -1,13 +0,0 @@ -/* - * Skeleton device tree in the 64 bits version; the bare minimum - * needed to boot; just include and add a compatible value. The - * bootloader will typically populate the memory node. - */ - -/ { - #address-cells = <2>; - #size-cells = <2>; - chosen { }; - aliases { }; - memory { device_type = "memory"; reg = <0 0 0 0>; }; -}; diff --git a/sys/gnu/dts/arm/socfpga.dtsi b/sys/gnu/dts/arm/socfpga.dtsi deleted file mode 100644 index 4f3993cc022..00000000000 --- a/sys/gnu/dts/arm/socfpga.dtsi +++ /dev/null @@ -1,960 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2012 Altera - */ - -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - timer0 = &timer0; - timer1 = &timer1; - timer2 = &timer2; - timer3 = &timer3; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "altr,socfpga-smp"; - - cpu0: cpu@0 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - reg = <0>; - next-level-cache = <&L2>; - }; - cpu1: cpu@1 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - reg = <1>; - next-level-cache = <&L2>; - }; - }; - - pmu: pmu@ff111000 { - compatible = "arm,cortex-a9-pmu"; - interrupt-parent = <&intc>; - interrupts = <0 176 4>, <0 177 4>; - interrupt-affinity = <&cpu0>, <&cpu1>; - reg = <0xff111000 0x1000>, - <0xff113000 0x1000>; - }; - - intc: intc@fffed000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0xfffed000 0x1000>, - <0xfffec100 0x100>; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - device_type = "soc"; - interrupt-parent = <&intc>; - ranges; - - amba { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - pdma: pdma@ffe01000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0xffe01000 0x1000>; - interrupts = <0 104 4>, - <0 105 4>, - <0 106 4>, - <0 107 4>, - <0 108 4>, - <0 109 4>, - <0 110 4>, - <0 111 4>; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; - clocks = <&l4_main_clk>; - clock-names = "apb_pclk"; - resets = <&rst DMA_RESET>; - reset-names = "dma"; - }; - }; - - base_fpga_region { - compatible = "fpga-region"; - fpga-mgr = <&fpgamgr0>; - - #address-cells = <0x1>; - #size-cells = <0x1>; - }; - - can0: can@ffc00000 { - compatible = "bosch,d_can"; - reg = <0xffc00000 0x1000>; - interrupts = <0 131 4>, <0 132 4>, <0 133 4>, <0 134 4>; - clocks = <&can0_clk>; - resets = <&rst CAN0_RESET>; - status = "disabled"; - }; - - can1: can@ffc01000 { - compatible = "bosch,d_can"; - reg = <0xffc01000 0x1000>; - interrupts = <0 135 4>, <0 136 4>, <0 137 4>, <0 138 4>; - clocks = <&can1_clk>; - resets = <&rst CAN1_RESET>; - status = "disabled"; - }; - - clkmgr@ffd04000 { - compatible = "altr,clk-mgr"; - reg = <0xffd04000 0x1000>; - - clocks { - #address-cells = <1>; - #size-cells = <0>; - - osc1: osc1 { - #clock-cells = <0>; - compatible = "fixed-clock"; - }; - - osc2: osc2 { - #clock-cells = <0>; - compatible = "fixed-clock"; - }; - - f2s_periph_ref_clk: f2s_periph_ref_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - }; - - f2s_sdram_ref_clk: f2s_sdram_ref_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - }; - - main_pll: main_pll@40 { - #address-cells = <1>; - #size-cells = <0>; - #clock-cells = <0>; - compatible = "altr,socfpga-pll-clock"; - clocks = <&osc1>; - reg = <0x40>; - - mpuclk: mpuclk@48 { - #clock-cells = <0>; - compatible = "altr,socfpga-perip-clk"; - clocks = <&main_pll>; - div-reg = <0xe0 0 9>; - reg = <0x48>; - }; - - mainclk: mainclk@4c { - #clock-cells = <0>; - compatible = "altr,socfpga-perip-clk"; - clocks = <&main_pll>; - div-reg = <0xe4 0 9>; - reg = <0x4C>; - }; - - dbg_base_clk: dbg_base_clk@50 { - #clock-cells = <0>; - compatible = "altr,socfpga-perip-clk"; - clocks = <&main_pll>, <&osc1>; - div-reg = <0xe8 0 9>; - reg = <0x50>; - }; - - main_qspi_clk: main_qspi_clk@54 { - #clock-cells = <0>; - compatible = "altr,socfpga-perip-clk"; - clocks = <&main_pll>; - reg = <0x54>; - }; - - main_nand_sdmmc_clk: main_nand_sdmmc_clk@58 { - #clock-cells = <0>; - compatible = "altr,socfpga-perip-clk"; - clocks = <&main_pll>; - reg = <0x58>; - }; - - cfg_h2f_usr0_clk: cfg_h2f_usr0_clk@5c { - #clock-cells = <0>; - compatible = "altr,socfpga-perip-clk"; - clocks = <&main_pll>; - reg = <0x5C>; - }; - }; - - periph_pll: periph_pll@80 { - #address-cells = <1>; - #size-cells = <0>; - #clock-cells = <0>; - compatible = "altr,socfpga-pll-clock"; - clocks = <&osc1>, <&osc2>, <&f2s_periph_ref_clk>; - reg = <0x80>; - - emac0_clk: emac0_clk@88 { - #clock-cells = <0>; - compatible = "altr,socfpga-perip-clk"; - clocks = <&periph_pll>; - reg = <0x88>; - }; - - emac1_clk: emac1_clk@8c { - #clock-cells = <0>; - compatible = "altr,socfpga-perip-clk"; - clocks = <&periph_pll>; - reg = <0x8C>; - }; - - per_qspi_clk: per_qsi_clk@90 { - #clock-cells = <0>; - compatible = "altr,socfpga-perip-clk"; - clocks = <&periph_pll>; - reg = <0x90>; - }; - - per_nand_mmc_clk: per_nand_mmc_clk@94 { - #clock-cells = <0>; - compatible = "altr,socfpga-perip-clk"; - clocks = <&periph_pll>; - reg = <0x94>; - }; - - per_base_clk: per_base_clk@98 { - #clock-cells = <0>; - compatible = "altr,socfpga-perip-clk"; - clocks = <&periph_pll>; - reg = <0x98>; - }; - - h2f_usr1_clk: h2f_usr1_clk@9c { - #clock-cells = <0>; - compatible = "altr,socfpga-perip-clk"; - clocks = <&periph_pll>; - reg = <0x9C>; - }; - }; - - sdram_pll: sdram_pll@c0 { - #address-cells = <1>; - #size-cells = <0>; - #clock-cells = <0>; - compatible = "altr,socfpga-pll-clock"; - clocks = <&osc1>, <&osc2>, <&f2s_sdram_ref_clk>; - reg = <0xC0>; - - ddr_dqs_clk: ddr_dqs_clk@c8 { - #clock-cells = <0>; - compatible = "altr,socfpga-perip-clk"; - clocks = <&sdram_pll>; - reg = <0xC8>; - }; - - ddr_2x_dqs_clk: ddr_2x_dqs_clk@cc { - #clock-cells = <0>; - compatible = "altr,socfpga-perip-clk"; - clocks = <&sdram_pll>; - reg = <0xCC>; - }; - - ddr_dq_clk: ddr_dq_clk@d0 { - #clock-cells = <0>; - compatible = "altr,socfpga-perip-clk"; - clocks = <&sdram_pll>; - reg = <0xD0>; - }; - - h2f_usr2_clk: h2f_usr2_clk@d4 { - #clock-cells = <0>; - compatible = "altr,socfpga-perip-clk"; - clocks = <&sdram_pll>; - reg = <0xD4>; - }; - }; - - mpu_periph_clk: mpu_periph_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-perip-clk"; - clocks = <&mpuclk>; - fixed-divider = <4>; - }; - - mpu_l2_ram_clk: mpu_l2_ram_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-perip-clk"; - clocks = <&mpuclk>; - fixed-divider = <2>; - }; - - l4_main_clk: l4_main_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&mainclk>; - clk-gate = <0x60 0>; - }; - - l3_main_clk: l3_main_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-perip-clk"; - clocks = <&mainclk>; - fixed-divider = <1>; - }; - - l3_mp_clk: l3_mp_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&mainclk>; - div-reg = <0x64 0 2>; - clk-gate = <0x60 1>; - }; - - l3_sp_clk: l3_sp_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&l3_mp_clk>; - div-reg = <0x64 2 2>; - }; - - l4_mp_clk: l4_mp_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&mainclk>, <&per_base_clk>; - div-reg = <0x64 4 3>; - clk-gate = <0x60 2>; - }; - - l4_sp_clk: l4_sp_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&mainclk>, <&per_base_clk>; - div-reg = <0x64 7 3>; - clk-gate = <0x60 3>; - }; - - dbg_at_clk: dbg_at_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&dbg_base_clk>; - div-reg = <0x68 0 2>; - clk-gate = <0x60 4>; - }; - - dbg_clk: dbg_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&dbg_at_clk>; - div-reg = <0x68 2 2>; - clk-gate = <0x60 5>; - }; - - dbg_trace_clk: dbg_trace_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&dbg_base_clk>; - div-reg = <0x6C 0 3>; - clk-gate = <0x60 6>; - }; - - dbg_timer_clk: dbg_timer_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&dbg_base_clk>; - clk-gate = <0x60 7>; - }; - - cfg_clk: cfg_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&cfg_h2f_usr0_clk>; - clk-gate = <0x60 8>; - }; - - h2f_user0_clk: h2f_user0_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&cfg_h2f_usr0_clk>; - clk-gate = <0x60 9>; - }; - - emac_0_clk: emac_0_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&emac0_clk>; - clk-gate = <0xa0 0>; - }; - - emac_1_clk: emac_1_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&emac1_clk>; - clk-gate = <0xa0 1>; - }; - - usb_mp_clk: usb_mp_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&per_base_clk>; - clk-gate = <0xa0 2>; - div-reg = <0xa4 0 3>; - }; - - spi_m_clk: spi_m_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&per_base_clk>; - clk-gate = <0xa0 3>; - div-reg = <0xa4 3 3>; - }; - - can0_clk: can0_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&per_base_clk>; - clk-gate = <0xa0 4>; - div-reg = <0xa4 6 3>; - }; - - can1_clk: can1_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&per_base_clk>; - clk-gate = <0xa0 5>; - div-reg = <0xa4 9 3>; - }; - - gpio_db_clk: gpio_db_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&per_base_clk>; - clk-gate = <0xa0 6>; - div-reg = <0xa8 0 24>; - }; - - h2f_user1_clk: h2f_user1_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&h2f_usr1_clk>; - clk-gate = <0xa0 7>; - }; - - sdmmc_clk: sdmmc_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; - clk-gate = <0xa0 8>; - clk-phase = <0 135>; - }; - - sdmmc_clk_divided: sdmmc_clk_divided { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&sdmmc_clk>; - clk-gate = <0xa0 8>; - fixed-divider = <4>; - }; - - nand_x_clk: nand_x_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; - clk-gate = <0xa0 9>; - }; - - nand_ecc_clk: nand_ecc_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&nand_x_clk>; - clk-gate = <0xa0 9>; - }; - - nand_clk: nand_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&nand_x_clk>; - clk-gate = <0xa0 10>; - fixed-divider = <4>; - }; - - qspi_clk: qspi_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>; - clk-gate = <0xa0 11>; - }; - - ddr_dqs_clk_gate: ddr_dqs_clk_gate { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&ddr_dqs_clk>; - clk-gate = <0xd8 0>; - }; - - ddr_2x_dqs_clk_gate: ddr_2x_dqs_clk_gate { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&ddr_2x_dqs_clk>; - clk-gate = <0xd8 1>; - }; - - ddr_dq_clk_gate: ddr_dq_clk_gate { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&ddr_dq_clk>; - clk-gate = <0xd8 2>; - }; - - h2f_user2_clk: h2f_user2_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&h2f_usr2_clk>; - clk-gate = <0xd8 3>; - }; - - }; - }; - - fpga_bridge0: fpga_bridge@ff400000 { - compatible = "altr,socfpga-lwhps2fpga-bridge"; - reg = <0xff400000 0x100000>; - resets = <&rst LWHPS2FPGA_RESET>; - clocks = <&l4_main_clk>; - }; - - fpga_bridge1: fpga_bridge@ff500000 { - compatible = "altr,socfpga-hps2fpga-bridge"; - reg = <0xff500000 0x10000>; - resets = <&rst HPS2FPGA_RESET>; - clocks = <&l4_main_clk>; - }; - - fpgamgr0: fpgamgr@ff706000 { - compatible = "altr,socfpga-fpga-mgr"; - reg = <0xff706000 0x1000 - 0xffb90000 0x4>; - interrupts = <0 175 4>; - }; - - gmac0: ethernet@ff700000 { - compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac"; - altr,sysmgr-syscon = <&sysmgr 0x60 0>; - reg = <0xff700000 0x2000>; - interrupts = <0 115 4>; - interrupt-names = "macirq"; - mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */ - clocks = <&emac_0_clk>; - clock-names = "stmmaceth"; - resets = <&rst EMAC0_RESET>; - reset-names = "stmmaceth"; - snps,multicast-filter-bins = <256>; - snps,perfect-filter-entries = <128>; - tx-fifo-depth = <4096>; - rx-fifo-depth = <4096>; - status = "disabled"; - }; - - gmac1: ethernet@ff702000 { - compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac"; - altr,sysmgr-syscon = <&sysmgr 0x60 2>; - reg = <0xff702000 0x2000>; - interrupts = <0 120 4>; - interrupt-names = "macirq"; - mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */ - clocks = <&emac_1_clk>; - clock-names = "stmmaceth"; - resets = <&rst EMAC1_RESET>; - reset-names = "stmmaceth"; - snps,multicast-filter-bins = <256>; - snps,perfect-filter-entries = <128>; - tx-fifo-depth = <4096>; - rx-fifo-depth = <4096>; - status = "disabled"; - }; - - gpio0: gpio@ff708000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dw-apb-gpio"; - reg = <0xff708000 0x1000>; - clocks = <&l4_mp_clk>; - resets = <&rst GPIO0_RESET>; - status = "disabled"; - - porta: gpio-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <29>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <0 164 4>; - }; - }; - - gpio1: gpio@ff709000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dw-apb-gpio"; - reg = <0xff709000 0x1000>; - clocks = <&l4_mp_clk>; - resets = <&rst GPIO1_RESET>; - status = "disabled"; - - portb: gpio-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <29>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <0 165 4>; - }; - }; - - gpio2: gpio@ff70a000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dw-apb-gpio"; - reg = <0xff70a000 0x1000>; - clocks = <&l4_mp_clk>; - resets = <&rst GPIO2_RESET>; - status = "disabled"; - - portc: gpio-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <27>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <0 166 4>; - }; - }; - - i2c0: i2c@ffc04000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0xffc04000 0x1000>; - resets = <&rst I2C0_RESET>; - clocks = <&l4_sp_clk>; - interrupts = <0 158 0x4>; - status = "disabled"; - }; - - i2c1: i2c@ffc05000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0xffc05000 0x1000>; - resets = <&rst I2C1_RESET>; - clocks = <&l4_sp_clk>; - interrupts = <0 159 0x4>; - status = "disabled"; - }; - - i2c2: i2c@ffc06000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0xffc06000 0x1000>; - resets = <&rst I2C2_RESET>; - clocks = <&l4_sp_clk>; - interrupts = <0 160 0x4>; - status = "disabled"; - }; - - i2c3: i2c@ffc07000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0xffc07000 0x1000>; - resets = <&rst I2C3_RESET>; - clocks = <&l4_sp_clk>; - interrupts = <0 161 0x4>; - status = "disabled"; - }; - - eccmgr: eccmgr { - compatible = "altr,socfpga-ecc-manager"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - l2-ecc@ffd08140 { - compatible = "altr,socfpga-l2-ecc"; - reg = <0xffd08140 0x4>; - interrupts = <0 36 1>, <0 37 1>; - }; - - ocram-ecc@ffd08144 { - compatible = "altr,socfpga-ocram-ecc"; - reg = <0xffd08144 0x4>; - iram = <&ocram>; - interrupts = <0 178 1>, <0 179 1>; - }; - }; - - L2: l2-cache@fffef000 { - compatible = "arm,pl310-cache"; - reg = <0xfffef000 0x1000>; - interrupts = <0 38 0x04>; - cache-unified; - cache-level = <2>; - arm,tag-latency = <1 1 1>; - arm,data-latency = <2 1 1>; - prefetch-data = <1>; - prefetch-instr = <1>; - arm,shared-override; - arm,double-linefill = <1>; - arm,double-linefill-incr = <0>; - arm,double-linefill-wrap = <1>; - arm,prefetch-drop = <0>; - arm,prefetch-offset = <7>; - }; - - l3regs@0xff800000 { - compatible = "altr,l3regs", "syscon"; - reg = <0xff800000 0x1000>; - }; - - mmc: dwmmc0@ff704000 { - compatible = "altr,socfpga-dw-mshc"; - reg = <0xff704000 0x1000>; - interrupts = <0 139 4>; - fifo-depth = <0x400>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&l4_mp_clk>, <&sdmmc_clk_divided>; - clock-names = "biu", "ciu"; - resets = <&rst SDMMC_RESET>; - status = "disabled"; - }; - - nand0: nand@ff900000 { - #address-cells = <0x1>; - #size-cells = <0x0>; - compatible = "altr,socfpga-denali-nand"; - reg = <0xff900000 0x100000>, - <0xffb80000 0x10000>; - reg-names = "nand_data", "denali_reg"; - interrupts = <0x0 0x90 0x4>; - clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>; - clock-names = "nand", "nand_x", "ecc"; - resets = <&rst NAND_RESET>; - status = "disabled"; - }; - - ocram: sram@ffff0000 { - compatible = "mmio-sram"; - reg = <0xffff0000 0x10000>; - }; - - qspi: spi@ff705000 { - compatible = "cdns,qspi-nor"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xff705000 0x1000>, - <0xffa00000 0x1000>; - interrupts = <0 151 4>; - cdns,fifo-depth = <128>; - cdns,fifo-width = <4>; - cdns,trigger-address = <0x00000000>; - clocks = <&qspi_clk>; - resets = <&rst QSPI_RESET>; - status = "disabled"; - }; - - rst: rstmgr@ffd05000 { - #reset-cells = <1>; - compatible = "altr,rst-mgr"; - reg = <0xffd05000 0x1000>; - altr,modrst-offset = <0x10>; - }; - - scu: snoop-control-unit@fffec000 { - compatible = "arm,cortex-a9-scu"; - reg = <0xfffec000 0x100>; - }; - - sdr: sdr@ffc25000 { - compatible = "altr,sdr-ctl", "syscon"; - reg = <0xffc25000 0x1000>; - resets = <&rst SDR_RESET>; - }; - - sdramedac { - compatible = "altr,sdram-edac"; - altr,sdr-syscon = <&sdr>; - interrupts = <0 39 4>; - }; - - spi0: spi@fff00000 { - compatible = "snps,dw-apb-ssi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xfff00000 0x1000>; - interrupts = <0 154 4>; - num-cs = <4>; - clocks = <&spi_m_clk>; - resets = <&rst SPIM0_RESET>; - status = "disabled"; - }; - - spi1: spi@fff01000 { - compatible = "snps,dw-apb-ssi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xfff01000 0x1000>; - interrupts = <0 155 4>; - num-cs = <4>; - clocks = <&spi_m_clk>; - resets = <&rst SPIM1_RESET>; - status = "disabled"; - }; - - sysmgr: sysmgr@ffd08000 { - compatible = "altr,sys-mgr", "syscon"; - reg = <0xffd08000 0x4000>; - }; - - /* Local timer */ - timer@fffec600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0xfffec600 0x100>; - interrupts = <1 13 0xf01>; - clocks = <&mpu_periph_clk>; - }; - - timer0: timer0@ffc08000 { - compatible = "snps,dw-apb-timer"; - interrupts = <0 167 4>; - reg = <0xffc08000 0x1000>; - clocks = <&l4_sp_clk>; - clock-names = "timer"; - resets = <&rst SPTIMER0_RESET>; - reset-names = "timer"; - }; - - timer1: timer1@ffc09000 { - compatible = "snps,dw-apb-timer"; - interrupts = <0 168 4>; - reg = <0xffc09000 0x1000>; - clocks = <&l4_sp_clk>; - clock-names = "timer"; - resets = <&rst SPTIMER1_RESET>; - reset-names = "timer"; - }; - - timer2: timer2@ffd00000 { - compatible = "snps,dw-apb-timer"; - interrupts = <0 169 4>; - reg = <0xffd00000 0x1000>; - clocks = <&osc1>; - clock-names = "timer"; - resets = <&rst OSC1TIMER0_RESET>; - reset-names = "timer"; - }; - - timer3: timer3@ffd01000 { - compatible = "snps,dw-apb-timer"; - interrupts = <0 170 4>; - reg = <0xffd01000 0x1000>; - clocks = <&osc1>; - clock-names = "timer"; - resets = <&rst OSC1TIMER1_RESET>; - reset-names = "timer"; - }; - - uart0: serial0@ffc02000 { - compatible = "snps,dw-apb-uart"; - reg = <0xffc02000 0x1000>; - interrupts = <0 162 4>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&l4_sp_clk>; - dmas = <&pdma 28>, - <&pdma 29>; - dma-names = "tx", "rx"; - resets = <&rst UART0_RESET>; - }; - - uart1: serial1@ffc03000 { - compatible = "snps,dw-apb-uart"; - reg = <0xffc03000 0x1000>; - interrupts = <0 163 4>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&l4_sp_clk>; - dmas = <&pdma 30>, - <&pdma 31>; - dma-names = "tx", "rx"; - resets = <&rst UART1_RESET>; - }; - - usbphy0: usbphy { - #phy-cells = <0>; - compatible = "usb-nop-xceiv"; - status = "okay"; - }; - - usb0: usb@ffb00000 { - compatible = "snps,dwc2"; - reg = <0xffb00000 0xffff>; - interrupts = <0 125 4>; - clocks = <&usb_mp_clk>; - clock-names = "otg"; - resets = <&rst USB0_RESET>; - reset-names = "dwc2"; - phys = <&usbphy0>; - phy-names = "usb2-phy"; - status = "disabled"; - }; - - usb1: usb@ffb40000 { - compatible = "snps,dwc2"; - reg = <0xffb40000 0xffff>; - interrupts = <0 128 4>; - clocks = <&usb_mp_clk>; - clock-names = "otg"; - resets = <&rst USB1_RESET>; - reset-names = "dwc2"; - phys = <&usbphy0>; - phy-names = "usb2-phy"; - status = "disabled"; - }; - - watchdog0: watchdog@ffd02000 { - compatible = "snps,dw-wdt"; - reg = <0xffd02000 0x1000>; - interrupts = <0 171 4>; - clocks = <&osc1>; - resets = <&rst L4WD0_RESET>; - status = "disabled"; - }; - - watchdog1: watchdog@ffd03000 { - compatible = "snps,dw-wdt"; - reg = <0xffd03000 0x1000>; - interrupts = <0 172 4>; - clocks = <&osc1>; - resets = <&rst L4WD1_RESET>; - status = "disabled"; - }; - }; -}; diff --git a/sys/gnu/dts/arm/socfpga_arria10.dtsi b/sys/gnu/dts/arm/socfpga_arria10.dtsi deleted file mode 100644 index 2a86e72d979..00000000000 --- a/sys/gnu/dts/arm/socfpga_arria10.dtsi +++ /dev/null @@ -1,901 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright Altera Corporation (C) 2014. All rights reserved. - */ - -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "altr,socfpga-a10-smp"; - - cpu@0 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - reg = <0>; - next-level-cache = <&L2>; - }; - cpu@1 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - reg = <1>; - next-level-cache = <&L2>; - }; - }; - - intc: intc@ffffd000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0xffffd000 0x1000>, - <0xffffc100 0x100>; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - device_type = "soc"; - interrupt-parent = <&intc>; - ranges; - - amba { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - pdma: pdma@ffda1000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0xffda1000 0x1000>; - interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>, - <0 84 IRQ_TYPE_LEVEL_HIGH>, - <0 85 IRQ_TYPE_LEVEL_HIGH>, - <0 86 IRQ_TYPE_LEVEL_HIGH>, - <0 87 IRQ_TYPE_LEVEL_HIGH>, - <0 88 IRQ_TYPE_LEVEL_HIGH>, - <0 89 IRQ_TYPE_LEVEL_HIGH>, - <0 90 IRQ_TYPE_LEVEL_HIGH>, - <0 91 IRQ_TYPE_LEVEL_HIGH>; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; - clocks = <&l4_main_clk>; - clock-names = "apb_pclk"; - resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>; - reset-names = "dma", "dma-ocp"; - }; - }; - - base_fpga_region { - #address-cells = <0x1>; - #size-cells = <0x1>; - - compatible = "fpga-region"; - fpga-mgr = <&fpga_mgr>; - }; - - clkmgr@ffd04000 { - compatible = "altr,clk-mgr"; - reg = <0xffd04000 0x1000>; - - clocks { - #address-cells = <1>; - #size-cells = <0>; - - cb_intosc_hs_div2_clk: cb_intosc_hs_div2_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - }; - - cb_intosc_ls_clk: cb_intosc_ls_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - }; - - f2s_free_clk: f2s_free_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - }; - - osc1: osc1 { - #clock-cells = <0>; - compatible = "fixed-clock"; - }; - - main_pll: main_pll@40 { - #address-cells = <1>; - #size-cells = <0>; - #clock-cells = <0>; - compatible = "altr,socfpga-a10-pll-clock"; - clocks = <&osc1>, <&cb_intosc_ls_clk>, - <&f2s_free_clk>; - reg = <0x40>; - - main_mpu_base_clk: main_mpu_base_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&main_pll>; - div-reg = <0x140 0 11>; - }; - - main_noc_base_clk: main_noc_base_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&main_pll>; - div-reg = <0x144 0 11>; - }; - - main_emaca_clk: main_emaca_clk@68 { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&main_pll>; - reg = <0x68>; - }; - - main_emacb_clk: main_emacb_clk@6c { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&main_pll>; - reg = <0x6C>; - }; - - main_emac_ptp_clk: main_emac_ptp_clk@70 { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&main_pll>; - reg = <0x70>; - }; - - main_gpio_db_clk: main_gpio_db_clk@74 { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&main_pll>; - reg = <0x74>; - }; - - main_sdmmc_clk: main_sdmmc_clk@78 { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk" -; - clocks = <&main_pll>; - reg = <0x78>; - }; - - main_s2f_usr0_clk: main_s2f_usr0_clk@7c { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&main_pll>; - reg = <0x7C>; - }; - - main_s2f_usr1_clk: main_s2f_usr1_clk@80 { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&main_pll>; - reg = <0x80>; - }; - - main_hmc_pll_ref_clk: main_hmc_pll_ref_clk@84 { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&main_pll>; - reg = <0x84>; - }; - - main_periph_ref_clk: main_periph_ref_clk@9c { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&main_pll>; - reg = <0x9C>; - }; - }; - - periph_pll: periph_pll@c0 { - #address-cells = <1>; - #size-cells = <0>; - #clock-cells = <0>; - compatible = "altr,socfpga-a10-pll-clock"; - clocks = <&osc1>, <&cb_intosc_ls_clk>, - <&f2s_free_clk>, <&main_periph_ref_clk>; - reg = <0xC0>; - - peri_mpu_base_clk: peri_mpu_base_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&periph_pll>; - div-reg = <0x140 16 11>; - }; - - peri_noc_base_clk: peri_noc_base_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&periph_pll>; - div-reg = <0x144 16 11>; - }; - - peri_emaca_clk: peri_emaca_clk@e8 { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&periph_pll>; - reg = <0xE8>; - }; - - peri_emacb_clk: peri_emacb_clk@ec { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&periph_pll>; - reg = <0xEC>; - }; - - peri_emac_ptp_clk: peri_emac_ptp_clk@f0 { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&periph_pll>; - reg = <0xF0>; - }; - - peri_gpio_db_clk: peri_gpio_db_clk@f4 { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&periph_pll>; - reg = <0xF4>; - }; - - peri_sdmmc_clk: peri_sdmmc_clk@f8 { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&periph_pll>; - reg = <0xF8>; - }; - - peri_s2f_usr0_clk: peri_s2f_usr0_clk@fc { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&periph_pll>; - reg = <0xFC>; - }; - - peri_s2f_usr1_clk: peri_s2f_usr1_clk@100 { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&periph_pll>; - reg = <0x100>; - }; - - peri_hmc_pll_ref_clk: peri_hmc_pll_ref_clk@104 { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&periph_pll>; - reg = <0x104>; - }; - }; - - mpu_free_clk: mpu_free_clk@60 { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&main_mpu_base_clk>, <&peri_mpu_base_clk>, - <&osc1>, <&cb_intosc_hs_div2_clk>, - <&f2s_free_clk>; - reg = <0x60>; - }; - - noc_free_clk: noc_free_clk@64 { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&main_noc_base_clk>, <&peri_noc_base_clk>, - <&osc1>, <&cb_intosc_hs_div2_clk>, - <&f2s_free_clk>; - reg = <0x64>; - }; - - s2f_user1_free_clk: s2f_user1_free_clk@104 { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&main_s2f_usr1_clk>, <&peri_s2f_usr1_clk>, - <&osc1>, <&cb_intosc_hs_div2_clk>, - <&f2s_free_clk>; - reg = <0x104>; - }; - - sdmmc_free_clk: sdmmc_free_clk@f8 { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&main_sdmmc_clk>, <&peri_sdmmc_clk>, - <&osc1>, <&cb_intosc_hs_div2_clk>, - <&f2s_free_clk>; - fixed-divider = <4>; - reg = <0xF8>; - }; - - l4_sys_free_clk: l4_sys_free_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&noc_free_clk>; - fixed-divider = <4>; - }; - - l4_main_clk: l4_main_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-gate-clk"; - clocks = <&noc_free_clk>; - div-reg = <0xA8 0 2>; - clk-gate = <0x48 1>; - }; - - l4_mp_clk: l4_mp_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-gate-clk"; - clocks = <&noc_free_clk>; - div-reg = <0xA8 8 2>; - clk-gate = <0x48 2>; - }; - - l4_sp_clk: l4_sp_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-gate-clk"; - clocks = <&noc_free_clk>; - div-reg = <0xA8 16 2>; - clk-gate = <0x48 3>; - }; - - mpu_periph_clk: mpu_periph_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-gate-clk"; - clocks = <&mpu_free_clk>; - fixed-divider = <4>; - clk-gate = <0x48 0>; - }; - - sdmmc_clk: sdmmc_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-gate-clk"; - clocks = <&sdmmc_free_clk>; - clk-gate = <0xC8 5>; - clk-phase = <0 135>; - }; - - qspi_clk: qspi_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-gate-clk"; - clocks = <&l4_main_clk>; - clk-gate = <0xC8 11>; - }; - - nand_x_clk: nand_x_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-gate-clk"; - clocks = <&l4_mp_clk>; - clk-gate = <0xC8 10>; - }; - - nand_ecc_clk: nand_ecc_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-gate-clk"; - clocks = <&nand_x_clk>; - clk-gate = <0xC8 10>; - }; - - nand_clk: nand_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-gate-clk"; - clocks = <&nand_x_clk>; - fixed-divider = <4>; - clk-gate = <0xC8 10>; - }; - - spi_m_clk: spi_m_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-gate-clk"; - clocks = <&l4_main_clk>; - clk-gate = <0xC8 9>; - }; - - usb_clk: usb_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-gate-clk"; - clocks = <&l4_mp_clk>; - clk-gate = <0xC8 8>; - }; - - s2f_usr1_clk: s2f_usr1_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-gate-clk"; - clocks = <&peri_s2f_usr1_clk>; - clk-gate = <0xC8 6>; - }; - }; - }; - - socfpga_axi_setup: stmmac-axi-config { - snps,wr_osr_lmt = <0xf>; - snps,rd_osr_lmt = <0xf>; - snps,blen = <0 0 0 0 16 0 0>; - }; - - gmac0: ethernet@ff800000 { - compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.72a", "snps,dwmac"; - altr,sysmgr-syscon = <&sysmgr 0x44 0>; - reg = <0xff800000 0x2000>; - interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "macirq"; - /* Filled in by bootloader */ - mac-address = [00 00 00 00 00 00]; - snps,multicast-filter-bins = <256>; - snps,perfect-filter-entries = <128>; - tx-fifo-depth = <4096>; - rx-fifo-depth = <16384>; - clocks = <&l4_mp_clk>; - clock-names = "stmmaceth"; - resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>; - reset-names = "stmmaceth", "stmmaceth-ocp"; - snps,axi-config = <&socfpga_axi_setup>; - status = "disabled"; - }; - - gmac1: ethernet@ff802000 { - compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.72a", "snps,dwmac"; - altr,sysmgr-syscon = <&sysmgr 0x48 8>; - reg = <0xff802000 0x2000>; - interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "macirq"; - /* Filled in by bootloader */ - mac-address = [00 00 00 00 00 00]; - snps,multicast-filter-bins = <256>; - snps,perfect-filter-entries = <128>; - tx-fifo-depth = <4096>; - rx-fifo-depth = <16384>; - clocks = <&l4_mp_clk>; - clock-names = "stmmaceth"; - resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>; - reset-names = "stmmaceth", "stmmaceth-ocp"; - snps,axi-config = <&socfpga_axi_setup>; - status = "disabled"; - }; - - gmac2: ethernet@ff804000 { - compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.72a", "snps,dwmac"; - altr,sysmgr-syscon = <&sysmgr 0x4C 16>; - reg = <0xff804000 0x2000>; - interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "macirq"; - /* Filled in by bootloader */ - mac-address = [00 00 00 00 00 00]; - snps,multicast-filter-bins = <256>; - snps,perfect-filter-entries = <128>; - tx-fifo-depth = <4096>; - rx-fifo-depth = <16384>; - clocks = <&l4_mp_clk>; - clock-names = "stmmaceth"; - resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>; - reset-names = "stmmaceth", "stmmaceth-ocp"; - snps,axi-config = <&socfpga_axi_setup>; - status = "disabled"; - }; - - gpio0: gpio@ffc02900 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dw-apb-gpio"; - reg = <0xffc02900 0x100>; - resets = <&rst GPIO0_RESET>; - status = "disabled"; - - porta: gpio-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <29>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - - gpio1: gpio@ffc02a00 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dw-apb-gpio"; - reg = <0xffc02a00 0x100>; - resets = <&rst GPIO1_RESET>; - status = "disabled"; - - portb: gpio-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <29>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - - gpio2: gpio@ffc02b00 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dw-apb-gpio"; - reg = <0xffc02b00 0x100>; - resets = <&rst GPIO2_RESET>; - status = "disabled"; - - portc: gpio-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <27>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - - fpga_mgr: fpga-mgr@ffd03000 { - compatible = "altr,socfpga-a10-fpga-mgr"; - reg = <0xffd03000 0x100 - 0xffcfe400 0x20>; - clocks = <&l4_mp_clk>; - resets = <&rst FPGAMGR_RESET>; - reset-names = "fpgamgr"; - }; - - i2c0: i2c@ffc02200 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0xffc02200 0x100>; - interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&l4_sp_clk>; - resets = <&rst I2C0_RESET>; - status = "disabled"; - }; - - i2c1: i2c@ffc02300 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0xffc02300 0x100>; - interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&l4_sp_clk>; - resets = <&rst I2C1_RESET>; - status = "disabled"; - }; - - i2c2: i2c@ffc02400 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0xffc02400 0x100>; - interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&l4_sp_clk>; - resets = <&rst I2C2_RESET>; - status = "disabled"; - }; - - i2c3: i2c@ffc02500 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0xffc02500 0x100>; - interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&l4_sp_clk>; - resets = <&rst I2C3_RESET>; - status = "disabled"; - }; - - i2c4: i2c@ffc02600 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0xffc02600 0x100>; - interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&l4_sp_clk>; - resets = <&rst I2C4_RESET>; - status = "disabled"; - }; - - spi0: spi@ffda4000 { - compatible = "snps,dw-apb-ssi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xffda4000 0x100>; - interrupts = <0 101 4>; - num-cs = <4>; - /*32bit_access;*/ - clocks = <&spi_m_clk>; - resets = <&rst SPIM0_RESET>; - status = "disabled"; - }; - - spi1: spi@ffda5000 { - compatible = "snps,dw-apb-ssi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xffda5000 0x100>; - interrupts = <0 102 4>; - num-cs = <4>; - /*32bit_access;*/ - tx-dma-channel = <&pdma 16>; - rx-dma-channel = <&pdma 17>; - clocks = <&spi_m_clk>; - resets = <&rst SPIM1_RESET>; - status = "disabled"; - }; - - sdr: sdr@ffcfb100 { - compatible = "altr,sdr-ctl", "syscon"; - reg = <0xffcfb100 0x80>; - }; - - L2: l2-cache@fffff000 { - compatible = "arm,pl310-cache"; - reg = <0xfffff000 0x1000>; - interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>; - cache-unified; - cache-level = <2>; - prefetch-data = <1>; - prefetch-instr = <1>; - arm,shared-override; - }; - - mmc: dwmmc0@ff808000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "altr,socfpga-dw-mshc"; - reg = <0xff808000 0x1000>; - interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; - fifo-depth = <0x400>; - clocks = <&l4_mp_clk>, <&sdmmc_clk>; - clock-names = "biu", "ciu"; - resets = <&rst SDMMC_RESET>; - status = "disabled"; - }; - - nand: nand@ffb90000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "altr,socfpga-denali-nand"; - reg = <0xffb90000 0x72000>, - <0xffb80000 0x10000>; - reg-names = "nand_data", "denali_reg"; - interrupts = <0 99 4>; - clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>; - clock-names = "nand", "nand_x", "ecc"; - resets = <&rst NAND_RESET>; - status = "disabled"; - }; - - ocram: sram@ffe00000 { - compatible = "mmio-sram"; - reg = <0xffe00000 0x40000>; - }; - - eccmgr: eccmgr { - compatible = "altr,socfpga-a10-ecc-manager"; - altr,sysmgr-syscon = <&sysmgr>; - #address-cells = <1>; - #size-cells = <1>; - interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>, - <0 0 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - #interrupt-cells = <2>; - ranges; - - sdramedac { - compatible = "altr,sdram-edac-a10"; - altr,sdr-syscon = <&sdr>; - interrupts = <17 IRQ_TYPE_LEVEL_HIGH>, - <49 IRQ_TYPE_LEVEL_HIGH>; - }; - - l2-ecc@ffd06010 { - compatible = "altr,socfpga-a10-l2-ecc"; - reg = <0xffd06010 0x4>; - interrupts = <0 IRQ_TYPE_LEVEL_HIGH>, - <32 IRQ_TYPE_LEVEL_HIGH>; - }; - - ocram-ecc@ff8c3000 { - compatible = "altr,socfpga-a10-ocram-ecc"; - reg = <0xff8c3000 0x400>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH>, - <33 IRQ_TYPE_LEVEL_HIGH>; - }; - - emac0-rx-ecc@ff8c0800 { - compatible = "altr,socfpga-eth-mac-ecc"; - reg = <0xff8c0800 0x400>; - altr,ecc-parent = <&gmac0>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH>, - <36 IRQ_TYPE_LEVEL_HIGH>; - }; - - emac0-tx-ecc@ff8c0c00 { - compatible = "altr,socfpga-eth-mac-ecc"; - reg = <0xff8c0c00 0x400>; - altr,ecc-parent = <&gmac0>; - interrupts = <5 IRQ_TYPE_LEVEL_HIGH>, - <37 IRQ_TYPE_LEVEL_HIGH>; - }; - - dma-ecc@ff8c8000 { - compatible = "altr,socfpga-dma-ecc"; - reg = <0xff8c8000 0x400>; - altr,ecc-parent = <&pdma>; - interrupts = <10 IRQ_TYPE_LEVEL_HIGH>, - <42 IRQ_TYPE_LEVEL_HIGH>; - }; - - usb0-ecc@ff8c8800 { - compatible = "altr,socfpga-usb-ecc"; - reg = <0xff8c8800 0x400>; - altr,ecc-parent = <&usb0>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH>, - <34 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - - qspi: spi@ff809000 { - compatible = "cdns,qspi-nor"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xff809000 0x100>, - <0xffa00000 0x100000>; - interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>; - cdns,fifo-depth = <128>; - cdns,fifo-width = <4>; - cdns,trigger-address = <0x00000000>; - clocks = <&qspi_clk>; - resets = <&rst QSPI_RESET>, <&rst QSPI_OCP_RESET>; - reset-names = "qspi", "qspi-ocp"; - status = "disabled"; - }; - - rst: rstmgr@ffd05000 { - #reset-cells = <1>; - compatible = "altr,rst-mgr"; - reg = <0xffd05000 0x100>; - altr,modrst-offset = <0x20>; - }; - - scu: snoop-control-unit@ffffc000 { - compatible = "arm,cortex-a9-scu"; - reg = <0xffffc000 0x100>; - }; - - sysmgr: sysmgr@ffd06000 { - compatible = "altr,sys-mgr", "syscon"; - reg = <0xffd06000 0x300>; - cpu1-start-addr = <0xffd06230>; - }; - - /* Local timer */ - timer@ffffc600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0xffffc600 0x100>; - interrupts = <1 13 0xf01>; - clocks = <&mpu_periph_clk>; - }; - - timer0: timer0@ffc02700 { - compatible = "snps,dw-apb-timer"; - interrupts = <0 115 IRQ_TYPE_LEVEL_HIGH>; - reg = <0xffc02700 0x100>; - clocks = <&l4_sp_clk>; - clock-names = "timer"; - resets = <&rst SPTIMER0_RESET>; - reset-names = "timer"; - }; - - timer1: timer1@ffc02800 { - compatible = "snps,dw-apb-timer"; - interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>; - reg = <0xffc02800 0x100>; - clocks = <&l4_sp_clk>; - clock-names = "timer"; - resets = <&rst SPTIMER1_RESET>; - reset-names = "timer"; - }; - - timer2: timer2@ffd00000 { - compatible = "snps,dw-apb-timer"; - interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH>; - reg = <0xffd00000 0x100>; - clocks = <&l4_sys_free_clk>; - clock-names = "timer"; - resets = <&rst L4SYSTIMER0_RESET>; - reset-names = "timer"; - }; - - timer3: timer3@ffd00100 { - compatible = "snps,dw-apb-timer"; - interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>; - reg = <0xffd01000 0x100>; - clocks = <&l4_sys_free_clk>; - clock-names = "timer"; - resets = <&rst L4SYSTIMER1_RESET>; - reset-names = "timer"; - }; - - uart0: serial0@ffc02000 { - compatible = "snps,dw-apb-uart"; - reg = <0xffc02000 0x100>; - interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&l4_sp_clk>; - resets = <&rst UART0_RESET>; - status = "disabled"; - }; - - uart1: serial1@ffc02100 { - compatible = "snps,dw-apb-uart"; - reg = <0xffc02100 0x100>; - interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&l4_sp_clk>; - resets = <&rst UART1_RESET>; - status = "disabled"; - }; - - usbphy0: usbphy { - #phy-cells = <0>; - compatible = "usb-nop-xceiv"; - status = "okay"; - }; - - usb0: usb@ffb00000 { - compatible = "snps,dwc2"; - reg = <0xffb00000 0xffff>; - interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&usb_clk>; - clock-names = "otg"; - resets = <&rst USB0_RESET>; - reset-names = "dwc2"; - phys = <&usbphy0>; - phy-names = "usb2-phy"; - status = "disabled"; - }; - - usb1: usb@ffb40000 { - compatible = "snps,dwc2"; - reg = <0xffb40000 0xffff>; - interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&usb_clk>; - clock-names = "otg"; - resets = <&rst USB1_RESET>; - reset-names = "dwc2"; - phys = <&usbphy0>; - phy-names = "usb2-phy"; - status = "disabled"; - }; - - watchdog0: watchdog@ffd00200 { - compatible = "snps,dw-wdt"; - reg = <0xffd00200 0x100>; - interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&l4_sys_free_clk>; - resets = <&rst L4WD0_RESET>; - status = "disabled"; - }; - - watchdog1: watchdog@ffd00300 { - compatible = "snps,dw-wdt"; - reg = <0xffd00300 0x100>; - interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&l4_sys_free_clk>; - resets = <&rst L4WD1_RESET>; - status = "disabled"; - }; - }; -}; diff --git a/sys/gnu/dts/arm/socfpga_arria10_socdk.dtsi b/sys/gnu/dts/arm/socfpga_arria10_socdk.dtsi deleted file mode 100644 index 0efbeccc5cd..00000000000 --- a/sys/gnu/dts/arm/socfpga_arria10_socdk.dtsi +++ /dev/null @@ -1,178 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2015 Altera Corporation - */ -#include "socfpga_arria10.dtsi" - -/ { - model = "Altera SOCFPGA Arria 10"; - compatible = "altr,socfpga-arria10", "altr,socfpga"; - - aliases { - ethernet0 = &gmac0; - serial0 = &uart1; - }; - - chosen { - bootargs = "earlyprintk"; - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - name = "memory"; - device_type = "memory"; - reg = <0x0 0x40000000>; /* 1GB */ - }; - - a10leds { - compatible = "gpio-leds"; - - a10sr_led0 { - label = "a10sr-led0"; - gpios = <&a10sr_gpio 0 1>; - }; - - a10sr_led1 { - label = "a10sr-led1"; - gpios = <&a10sr_gpio 1 1>; - }; - - a10sr_led2 { - label = "a10sr-led2"; - gpios = <&a10sr_gpio 2 1>; - }; - - a10sr_led3 { - label = "a10sr-led3"; - gpios = <&a10sr_gpio 3 1>; - }; - }; - - ref_033v: 033-v-ref { - compatible = "regulator-fixed"; - regulator-name = "0.33V"; - regulator-min-microvolt = <330000>; - regulator-max-microvolt = <330000>; - }; - - soc { - clkmgr@ffd04000 { - clocks { - osc1 { - clock-frequency = <25000000>; - }; - }; - }; - }; -}; - -&gmac0 { - phy-mode = "rgmii"; - phy-addr = <0xffffffff>; /* probe for phy addr */ - - /* - * These skews assume the user's FPGA design is adding 600ps of delay - * for TX_CLK on Arria 10. - * - * All skews are offset since hardware skew values for the ksz9031 - * range from a negative skew to a positive skew. - * See the micrel-ksz90x1.txt Documentation file for details. - */ - txd0-skew-ps = <0>; /* -420ps */ - txd1-skew-ps = <0>; /* -420ps */ - txd2-skew-ps = <0>; /* -420ps */ - txd3-skew-ps = <0>; /* -420ps */ - rxd0-skew-ps = <420>; /* 0ps */ - rxd1-skew-ps = <420>; /* 0ps */ - rxd2-skew-ps = <420>; /* 0ps */ - rxd3-skew-ps = <420>; /* 0ps */ - txen-skew-ps = <0>; /* -420ps */ - txc-skew-ps = <1860>; /* 960ps */ - rxdv-skew-ps = <420>; /* 0ps */ - rxc-skew-ps = <1680>; /* 780ps */ - max-frame-size = <3800>; - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&spi1 { - status = "okay"; - - resource-manager@0 { - compatible = "altr,a10sr"; - reg = <0>; - spi-max-frequency = <100000>; - /* low-level active IRQ at GPIO1_5 */ - interrupt-parent = <&portb>; - interrupts = <5 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells = <2>; - - a10sr_gpio: gpio-controller { - compatible = "altr,a10sr-gpio"; - gpio-controller; - #gpio-cells = <2>; - }; - - a10sr_rst: reset-controller { - compatible = "altr,a10sr-reset"; - #reset-cells = <1>; - }; - }; -}; - -&i2c1 { - status = "okay"; - - /* - * adjust the falling times to decrease the i2c frequency to 50Khz - * because the LCD module does not work at the standard 100Khz - */ - clock-frequency = <100000>; - i2c-sda-falling-time-ns = <6000>; - i2c-scl-falling-time-ns = <6000>; - - adc@14 { - compatible = "lltc,ltc2497"; - reg = <0x14>; - vref-supply = <&ref_033v>; - }; - - adc@16 { - compatible = "lltc,ltc2497"; - reg = <0x16>; - vref-supply = <&ref_033v>; - }; - - eeprom@51 { - compatible = "atmel,24c32"; - reg = <0x51>; - pagesize = <32>; - }; - - rtc@68 { - compatible = "dallas,ds1339"; - reg = <0x68>; - }; - - ltc@5c { - compatible = "ltc2977"; - reg = <0x5c>; - }; -}; - -&uart1 { - status = "okay"; -}; - -&usb0 { - status = "okay"; - disable-over-current; -}; - -&watchdog1 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/socfpga_arria10_socdk_nand.dts b/sys/gnu/dts/arm/socfpga_arria10_socdk_nand.dts deleted file mode 100644 index 9bd9e04c736..00000000000 --- a/sys/gnu/dts/arm/socfpga_arria10_socdk_nand.dts +++ /dev/null @@ -1,26 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2015 Altera Corporation. All rights reserved. - */ - -/dts-v1/; -#include "socfpga_arria10_socdk.dtsi" - -&nand { - status = "okay"; - - nand@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "Boot and fpga data"; - reg = <0x0 0x1C00000>; - }; - partition@1c00000 { - label = "Root Filesystem - JFFS2"; - reg = <0x1C00000 0x6400000>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/socfpga_arria10_socdk_qspi.dts b/sys/gnu/dts/arm/socfpga_arria10_socdk_qspi.dts deleted file mode 100644 index 2b645642b93..00000000000 --- a/sys/gnu/dts/arm/socfpga_arria10_socdk_qspi.dts +++ /dev/null @@ -1,38 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2016 Intel. All rights reserved. - */ - -/dts-v1/; -#include "socfpga_arria10_socdk.dtsi" - -&qspi { - status = "okay"; - - flash0: n25q00@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "n25q00aa"; - reg = <0>; - spi-max-frequency = <100000000>; - - m25p,fast-read; - cdns,page-size = <256>; - cdns,block-size = <16>; - cdns,read-delay = <3>; - cdns,tshsl-ns = <50>; - cdns,tsd2d-ns = <50>; - cdns,tchsh-ns = <4>; - cdns,tslch-ns = <4>; - - partition@qspi-boot { - label = "Boot and fpga data"; - reg = <0x0 0x2720000>; - }; - - partition@qspi-rootfs { - label = "Root Filesystem - JFFS2"; - reg = <0x2720000 0x58E0000>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/socfpga_arria10_socdk_sdmmc.dts b/sys/gnu/dts/arm/socfpga_arria10_socdk_sdmmc.dts deleted file mode 100644 index 64dc0799f3d..00000000000 --- a/sys/gnu/dts/arm/socfpga_arria10_socdk_sdmmc.dts +++ /dev/null @@ -1,27 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2014-2015 Altera Corporation - */ - -/dts-v1/; -#include "socfpga_arria10_socdk.dtsi" - -&mmc { - status = "okay"; - cap-sd-highspeed; - cap-mmc-highspeed; - broken-cd; - bus-width = <4>; -}; - -&eccmgr { - sdmmca-ecc@ff8c2c00 { - compatible = "altr,socfpga-sdmmc-ecc"; - reg = <0xff8c2c00 0x400>; - altr,ecc-parent = <&mmc>; - interrupts = <15 IRQ_TYPE_LEVEL_HIGH>, - <47 IRQ_TYPE_LEVEL_HIGH>, - <16 IRQ_TYPE_LEVEL_HIGH>, - <48 IRQ_TYPE_LEVEL_HIGH>; - }; -}; diff --git a/sys/gnu/dts/arm/socfpga_arria5.dtsi b/sys/gnu/dts/arm/socfpga_arria5.dtsi deleted file mode 100644 index 22dbf07afcf..00000000000 --- a/sys/gnu/dts/arm/socfpga_arria5.dtsi +++ /dev/null @@ -1,36 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2013 Altera Corporation - */ - -/dts-v1/; -/* First 4KB has trampoline code for secondary cores. */ -/memreserve/ 0x00000000 0x0001000; -#include "socfpga.dtsi" - -/ { - soc { - clkmgr@ffd04000 { - clocks { - osc1 { - clock-frequency = <25000000>; - }; - }; - }; - - mmc0: dwmmc0@ff704000 { - broken-cd; - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - }; - - sysmgr@ffd08000 { - cpu1-start-addr = <0xffd080c4>; - }; - }; -}; - -&watchdog0 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/socfpga_arria5_socdk.dts b/sys/gnu/dts/arm/socfpga_arria5_socdk.dts deleted file mode 100644 index 90e676e7019..00000000000 --- a/sys/gnu/dts/arm/socfpga_arria5_socdk.dts +++ /dev/null @@ -1,151 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2013 Altera Corporation - */ - -#include "socfpga_arria5.dtsi" - -/ { - model = "Altera SOCFPGA Arria V SoC Development Kit"; - compatible = "altr,socfpga-arria5", "altr,socfpga"; - - chosen { - bootargs = "earlyprintk"; - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - name = "memory"; - device_type = "memory"; - reg = <0x0 0x40000000>; /* 1GB */ - }; - - aliases { - /* this allow the ethaddr uboot environmnet variable contents - * to be added to the gmac1 device tree blob. - */ - ethernet0 = &gmac1; - }; - - leds { - compatible = "gpio-leds"; - hps0 { - label = "hps_led0"; - gpios = <&porta 0 1>; - }; - - hps1 { - label = "hps_led1"; - gpios = <&portb 11 1>; - }; - - hps2 { - label = "hps_led2"; - gpios = <&porta 17 1>; - }; - - hps3 { - label = "hps_led3"; - gpios = <&porta 18 1>; - }; - }; - - regulator_3_3v: 3-3-v-regulator { - compatible = "regulator-fixed"; - regulator-name = "3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&gmac1 { - status = "okay"; - phy-mode = "rgmii"; - - rxd0-skew-ps = <0>; - rxd1-skew-ps = <0>; - rxd2-skew-ps = <0>; - rxd3-skew-ps = <0>; - txen-skew-ps = <0>; - txc-skew-ps = <2600>; - rxdv-skew-ps = <0>; - rxc-skew-ps = <2000>; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&gpio2 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - clock-frequency = <100000>; - - /* - * adjust the falling times to decrease the i2c frequency to 50Khz - * because the LCD module does not work at the standard 100Khz - */ - i2c-sda-falling-time-ns = <5000>; - i2c-scl-falling-time-ns = <5000>; - - eeprom@51 { - compatible = "atmel,24c32"; - reg = <0x51>; - pagesize = <32>; - }; - - rtc@68 { - compatible = "dallas,ds1339"; - reg = <0x68>; - }; -}; - -&mmc0 { - vmmc-supply = <®ulator_3_3v>; - vqmmc-supply = <®ulator_3_3v>; - status = "okay"; -}; - -&qspi { - status = "okay"; - - flash: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "n25q256a"; - reg = <0>; - spi-max-frequency = <100000000>; - - m25p,fast-read; - cdns,page-size = <256>; - cdns,block-size = <16>; - cdns,read-delay = <4>; - cdns,tshsl-ns = <50>; - cdns,tsd2d-ns = <50>; - cdns,tchsh-ns = <4>; - cdns,tslch-ns = <4>; - - partition@qspi-boot { - /* 8MB for raw data. */ - label = "Flash 0 Raw Data"; - reg = <0x0 0x800000>; - }; - - partition@qspi-rootfs { - /* 120MB for jffs2 data. */ - label = "Flash 0 jffs2 Filesystem"; - reg = <0x800000 0x7800000>; - }; - }; -}; - -&usb1 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/socfpga_cyclone5.dtsi b/sys/gnu/dts/arm/socfpga_cyclone5.dtsi deleted file mode 100644 index 319a71e41ea..00000000000 --- a/sys/gnu/dts/arm/socfpga_cyclone5.dtsi +++ /dev/null @@ -1,36 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2012 Altera Corporation - */ - -/dts-v1/; -/* First 4KB has trampoline code for secondary cores. */ -/memreserve/ 0x00000000 0x0001000; -#include "socfpga.dtsi" - -/ { - soc { - clkmgr@ffd04000 { - clocks { - osc1 { - clock-frequency = <25000000>; - }; - }; - }; - - mmc0: dwmmc0@ff704000 { - broken-cd; - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - }; - - sysmgr@ffd08000 { - cpu1-start-addr = <0xffd080c4>; - }; - }; -}; - -&watchdog0 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/socfpga_cyclone5_chameleon96.dts b/sys/gnu/dts/arm/socfpga_cyclone5_chameleon96.dts deleted file mode 100644 index f6561766d83..00000000000 --- a/sys/gnu/dts/arm/socfpga_cyclone5_chameleon96.dts +++ /dev/null @@ -1,130 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Device Tree file for the Chameleon96 - * - * Copyright (c) 2018 Manivannan Sadhasivam - */ - -#include - -#include "socfpga_cyclone5.dtsi" - -/ { - model = "Novetech Chameleon96"; - compatible = "novtech,chameleon96", "altr,socfpga-cyclone5", "altr,socfpga"; - - chosen { - bootargs = "earlyprintk"; - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - name = "memory"; - device_type = "memory"; - reg = <0x0 0x20000000>; /* 512MB */ - }; - - regulator_3_3v: 3-3-v-regulator { - compatible = "regulator-fixed"; - regulator-name = "3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - leds { - compatible = "gpio-leds"; - - user_led1 { - label = "green:user1"; - gpios = <&porta 14 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - }; - - user_led2 { - label = "green:user2"; - gpios = <&porta 22 GPIO_ACTIVE_LOW>; - linux,default-trigger = "mmc0"; - }; - - user_led3 { - label = "green:user3"; - gpios = <&porta 25 GPIO_ACTIVE_LOW>; - linux,default-trigger = "none"; - }; - - user_led4 { - label = "green:user4"; - gpios = <&portb 3 GPIO_ACTIVE_LOW>; - panic-indicator; - linux,default-trigger = "none"; - }; - }; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&i2c0 { - /* On Low speed expansion */ - label = "LS-I2C0"; - status = "okay"; -}; - -&i2c1 { - /* On Low speed expansion */ - label = "LS-I2C1"; - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c3 { - /* On High speed expansion */ - label = "HS-I2C2"; - status = "okay"; -}; - -&mmc0 { - vmmc-supply = <®ulator_3_3v>; - vqmmc-supply = <®ulator_3_3v>; - status = "okay"; -}; - -&spi0 { - /* On High speed expansion */ - label = "HS-SPI1"; - status = "okay"; -}; - -&spi1 { - /* On Low speed expansion */ - label = "LS-SPI0"; - status = "okay"; -}; - -&uart0 { - /* On Low speed expansion */ - label = "LS-UART1"; - status = "okay"; -}; - -&uart1 { - /* On Low speed expansion */ - label = "LS-UART0"; - status = "okay"; -}; - -&usbphy0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/socfpga_cyclone5_de0_nano_soc.dts b/sys/gnu/dts/arm/socfpga_cyclone5_de0_nano_soc.dts deleted file mode 100644 index 67076e1b1c7..00000000000 --- a/sys/gnu/dts/arm/socfpga_cyclone5_de0_nano_soc.dts +++ /dev/null @@ -1,101 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright Altera Corporation (C) 2015. All rights reserved. - */ - -#include "socfpga_cyclone5.dtsi" - -/ { - model = "Terasic DE-0(Atlas)"; - compatible = "terasic,de0-atlas", "altr,socfpga-cyclone5", "altr,socfpga"; - - chosen { - bootargs = "earlyprintk"; - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - name = "memory"; - device_type = "memory"; - reg = <0x0 0x40000000>; /* 1GB */ - }; - - aliases { - ethernet0 = &gmac1; - }; - - regulator_3_3v: 3-3-v-regulator { - compatible = "regulator-fixed"; - regulator-name = "3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - leds { - compatible = "gpio-leds"; - hps0 { - label = "hps_led0"; - gpios = <&portb 24 0>; - linux,default-trigger = "heartbeat"; - }; - }; -}; - -&gmac1 { - status = "okay"; - phy-mode = "rgmii"; - - txd0-skew-ps = <0>; /* -420ps */ - txd1-skew-ps = <0>; /* -420ps */ - txd2-skew-ps = <0>; /* -420ps */ - txd3-skew-ps = <0>; /* -420ps */ - rxd0-skew-ps = <420>; /* 0ps */ - rxd1-skew-ps = <420>; /* 0ps */ - rxd2-skew-ps = <420>; /* 0ps */ - rxd3-skew-ps = <420>; /* 0ps */ - txen-skew-ps = <0>; /* -420ps */ - txc-skew-ps = <1860>; /* 960ps */ - rxdv-skew-ps = <420>; /* 0ps */ - rxc-skew-ps = <1680>; /* 780ps */ - - max-frame-size = <3800>; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&gpio2 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - clock-frequency = <100000>; - - adxl345: adxl345@53 { - compatible = "adi,adxl345"; - reg = <0x53>; - - interrupt-parent = <&portc>; - interrupts = <3 2>; - }; -}; - -&mmc0 { - vmmc-supply = <®ulator_3_3v>; - vqmmc-supply = <®ulator_3_3v>; - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/socfpga_cyclone5_de0_sockit.dts b/sys/gnu/dts/arm/socfpga_cyclone5_de0_sockit.dts deleted file mode 100644 index afea3645ada..00000000000 --- a/sys/gnu/dts/arm/socfpga_cyclone5_de0_sockit.dts +++ /dev/null @@ -1,112 +0,0 @@ -/* - * Copyright Altera Corporation (C) 2015. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see . - */ - -#include "socfpga_cyclone5.dtsi" - -/ { - model = "Terasic DE-0(Atlas)"; - compatible = "altr,socfpga-cyclone5", "altr,socfpga"; - - chosen { - bootargs = "earlyprintk"; - stdout-path = "serial0:115200n8"; - }; - - memory { - name = "memory"; - device_type = "memory"; - reg = <0x0 0x40000000>; /* 1GB */ - }; - - aliases { - ethernet0 = &gmac1; - }; - - regulator_3_3v: 3-3-v-regulator { - compatible = "regulator-fixed"; - regulator-name = "3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - leds { - compatible = "gpio-leds"; - hps0 { - label = "hps_led0"; - gpios = <&portb 24 0>; - linux,default-trigger = "heartbeat"; - }; - }; -}; - -&gmac1 { - status = "okay"; - phy-mode = "rgmii"; - - txd0-skew-ps = <0>; /* -420ps */ - txd1-skew-ps = <0>; /* -420ps */ - txd2-skew-ps = <0>; /* -420ps */ - txd3-skew-ps = <0>; /* -420ps */ - rxd0-skew-ps = <420>; /* 0ps */ - rxd1-skew-ps = <420>; /* 0ps */ - rxd2-skew-ps = <420>; /* 0ps */ - rxd3-skew-ps = <420>; /* 0ps */ - txen-skew-ps = <0>; /* -420ps */ - txc-skew-ps = <1860>; /* 960ps */ - rxdv-skew-ps = <420>; /* 0ps */ - rxc-skew-ps = <1680>; /* 780ps */ - - max-frame-size = <3800>; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&gpio2 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - speed-mode = <0>; - - adxl345: adxl345@0 { - compatible = "adi,adxl345"; - reg = <0x53>; - - interrupt-parent = <&portc>; - interrupts = <3 2>; - }; -}; - -&mmc0 { - vmmc-supply = <®ulator_3_3v>; - vqmmc-supply = <®ulator_3_3v>; - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/socfpga_cyclone5_mcv.dtsi b/sys/gnu/dts/arm/socfpga_cyclone5_mcv.dtsi deleted file mode 100644 index bd92806ffc1..00000000000 --- a/sys/gnu/dts/arm/socfpga_cyclone5_mcv.dtsi +++ /dev/null @@ -1,22 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2015 Marek Vasut - */ - -#include "socfpga_cyclone5.dtsi" - -/ { - model = "Aries/DENX MCV"; - compatible = "altr,socfpga-cyclone5", "altr,socfpga"; - - memory@0 { - name = "memory"; - device_type = "memory"; - reg = <0x0 0x40000000>; /* 1 GiB */ - }; -}; - -&mmc0 { /* On-SoM eMMC */ - bus-width = <8>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/socfpga_cyclone5_mcvevk.dts b/sys/gnu/dts/arm/socfpga_cyclone5_mcvevk.dts deleted file mode 100644 index ceaec29770c..00000000000 --- a/sys/gnu/dts/arm/socfpga_cyclone5_mcvevk.dts +++ /dev/null @@ -1,81 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2015 Marek Vasut - */ - -#include "socfpga_cyclone5_mcv.dtsi" - -/ { - model = "Aries/DENX MCV EVK"; - compatible = "denx,mcvevk", "altr,socfpga-cyclone5", "altr,socfpga"; - - aliases { - ethernet0 = &gmac0; - stmpe-i2c0 = &stmpe1; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&can0 { - status = "okay"; -}; - -&can1 { - status = "okay"; -}; - -&gmac0 { - phy-mode = "rgmii"; - status = "okay"; -}; - -&gpio0 { /* GPIO 0 ... 28 */ - status = "okay"; -}; - -&gpio1 { /* GPIO 29 ... 57 */ - status = "okay"; -}; - -&gpio2 { /* GPIO 58..66 (HLGPI 0..13 at offset 13) */ - status = "okay"; -}; - -&i2c0 { - status = "okay"; - clock-frequency = <100000>; - - stmpe1: stmpe811@41 { - compatible = "st,stmpe811"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x41>; - id = <0>; - blocks = <0x5>; - irq-gpio = <&portb 28 0x4>; /* GPIO 57, trig. level HI */ - - stmpe_touchscreen { - compatible = "st,stmpe-ts"; - ts,sample-time = <4>; - ts,mod-12b = <1>; - ts,ref-sel = <0>; - ts,adc-freq = <1>; - ts,ave-ctrl = <1>; - ts,touch-det-delay = <3>; - ts,settling = <4>; - ts,fraction-z = <7>; - ts,i-drive = <1>; - }; - }; -}; - -&uart0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/socfpga_cyclone5_socdk.dts b/sys/gnu/dts/arm/socfpga_cyclone5_socdk.dts deleted file mode 100644 index 6f138b2b261..00000000000 --- a/sys/gnu/dts/arm/socfpga_cyclone5_socdk.dts +++ /dev/null @@ -1,166 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2012 Altera Corporation - */ - -#include "socfpga_cyclone5.dtsi" - -/ { - model = "Altera SOCFPGA Cyclone V SoC Development Kit"; - compatible = "altr,socfpga-cyclone5-socdk", "altr,socfpga-cyclone5", "altr,socfpga"; - - chosen { - bootargs = "earlyprintk"; - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - name = "memory"; - device_type = "memory"; - reg = <0x0 0x40000000>; /* 1GB */ - }; - - aliases { - /* this allow the ethaddr uboot environmnet variable contents - * to be added to the gmac1 device tree blob. - */ - ethernet0 = &gmac1; - }; - - leds { - compatible = "gpio-leds"; - hps0 { - label = "hps_led0"; - gpios = <&portb 15 1>; - }; - - hps1 { - label = "hps_led1"; - gpios = <&portb 14 1>; - }; - - hps2 { - label = "hps_led2"; - gpios = <&portb 13 1>; - }; - - hps3 { - label = "hps_led3"; - gpios = <&portb 12 1>; - }; - }; - - regulator_3_3v: 3-3-v-regulator { - compatible = "regulator-fixed"; - regulator-name = "3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&can0 { - status = "okay"; -}; - -&gmac1 { - status = "okay"; - phy-mode = "rgmii"; - - rxd0-skew-ps = <0>; - rxd1-skew-ps = <0>; - rxd2-skew-ps = <0>; - rxd3-skew-ps = <0>; - txen-skew-ps = <0>; - txc-skew-ps = <2600>; - rxdv-skew-ps = <0>; - rxc-skew-ps = <2000>; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&gpio2 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - clock-frequency = <100000>; - - /* - * adjust the falling times to decrease the i2c frequency to 50Khz - * because the LCD module does not work at the standard 100Khz - */ - i2c-sda-falling-time-ns = <5000>; - i2c-scl-falling-time-ns = <5000>; - - eeprom@51 { - compatible = "atmel,24c32"; - reg = <0x51>; - pagesize = <32>; - }; - - rtc@68 { - compatible = "dallas,ds1339"; - reg = <0x68>; - }; -}; - -&mmc0 { - cd-gpios = <&portb 18 0>; - vmmc-supply = <®ulator_3_3v>; - vqmmc-supply = <®ulator_3_3v>; - status = "okay"; -}; - -&qspi { - status = "okay"; - - flash0: n25q00@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "n25q00"; - reg = <0>; /* chip select */ - spi-max-frequency = <100000000>; - - m25p,fast-read; - cdns,page-size = <256>; - cdns,block-size = <16>; - cdns,read-delay = <4>; - cdns,tshsl-ns = <50>; - cdns,tsd2d-ns = <50>; - cdns,tchsh-ns = <4>; - cdns,tslch-ns = <4>; - - partition@qspi-boot { - /* 8MB for raw data. */ - label = "Flash 0 Raw Data"; - reg = <0x0 0x800000>; - }; - - partition@qspi-rootfs { - /* 120MB for jffs2 data. */ - label = "Flash 0 jffs2 Filesystem"; - reg = <0x800000 0x7800000>; - }; - }; -}; - -&spi0 { - status = "okay"; - - spidev@0 { - compatible = "rohm,dh2228fv"; - reg = <0>; - spi-max-frequency = <1000000>; - }; -}; - -&usb1 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/socfpga_cyclone5_sockit.dts b/sys/gnu/dts/arm/socfpga_cyclone5_sockit.dts deleted file mode 100644 index c155ff02eb6..00000000000 --- a/sys/gnu/dts/arm/socfpga_cyclone5_sockit.dts +++ /dev/null @@ -1,189 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2013 Steffen Trumtrar - */ - -#include "socfpga_cyclone5.dtsi" - -/ { - model = "Terasic SoCkit"; - compatible = "terasic,socfpga-cyclone5-sockit", "altr,socfpga-cyclone5", "altr,socfpga"; - - chosen { - bootargs = "earlyprintk"; - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - name = "memory"; - device_type = "memory"; - reg = <0x0 0x40000000>; /* 1GB */ - }; - - aliases { - /* this allow the ethaddr uboot environmnet variable contents - * to be added to the gmac1 device tree blob. - */ - ethernet0 = &gmac1; - }; - - leds { - compatible = "gpio-leds"; - - hps_led0 { - label = "hps:blue:led0"; - gpios = <&portb 24 0>; /* HPS_GPIO53 */ - linux,default-trigger = "heartbeat"; - }; - - hps_led1 { - label = "hps:blue:led1"; - gpios = <&portb 25 0>; /* HPS_GPIO54 */ - linux,default-trigger = "heartbeat"; - }; - - hps_led2 { - label = "hps:blue:led2"; - gpios = <&portb 26 0>; /* HPS_GPIO55 */ - linux,default-trigger = "heartbeat"; - }; - - hps_led3 { - label = "hps:blue:led3"; - gpios = <&portb 27 0>; /* HPS_GPIO56 */ - linux,default-trigger = "heartbeat"; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - hps_sw0 { - label = "hps_sw0"; - gpios = <&portc 20 0>; /* HPS_GPI7 */ - linux,input-type = <5>; /* EV_SW */ - linux,code = <0x0>; /* SW_LID */ - }; - - hps_sw1 { - label = "hps_sw1"; - gpios = <&portc 19 0>; /* HPS_GPI6 */ - linux,input-type = <5>; /* EV_SW */ - linux,code = <0x5>; /* SW_DOCK */ - }; - - hps_sw2 { - label = "hps_sw2"; - gpios = <&portc 18 0>; /* HPS_GPI5 */ - linux,input-type = <5>; /* EV_SW */ - linux,code = <0xa>; /* SW_KEYPAD_SLIDE */ - }; - - hps_sw3 { - label = "hps_sw3"; - gpios = <&portc 17 0>; /* HPS_GPI4 */ - linux,input-type = <5>; /* EV_SW */ - linux,code = <0xc>; /* SW_ROTATE_LOCK */ - }; - - hps_hkey0 { - label = "hps_hkey0"; - gpios = <&portc 21 1>; /* HPS_GPI8 */ - linux,code = <187>; /* KEY_F17 */ - }; - - hps_hkey1 { - label = "hps_hkey1"; - gpios = <&portc 22 1>; /* HPS_GPI9 */ - linux,code = <188>; /* KEY_F18 */ - }; - - hps_hkey2 { - label = "hps_hkey2"; - gpios = <&portc 23 1>; /* HPS_GPI10 */ - linux,code = <189>; /* KEY_F19 */ - }; - - hps_hkey3 { - label = "hps_hkey3"; - gpios = <&portc 24 1>; /* HPS_GPI11 */ - linux,code = <190>; /* KEY_F20 */ - }; - }; - - regulator_3_3v: vcc3p3-regulator { - compatible = "regulator-fixed"; - regulator-name = "VCC3P3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&gmac1 { - status = "okay"; - phy-mode = "rgmii"; - - rxd0-skew-ps = <0>; - rxd1-skew-ps = <0>; - rxd2-skew-ps = <0>; - rxd3-skew-ps = <0>; - txen-skew-ps = <0>; - txc-skew-ps = <2600>; - rxdv-skew-ps = <0>; - rxc-skew-ps = <2000>; -}; - -&gpio0 { /* GPIO 0..29 */ - status = "okay"; -}; - -&gpio1 { /* GPIO 30..57 */ - status = "okay"; -}; - -&gpio2 { /* GPIO 58..66 (HLGPI 0..13 at offset 13) */ - status = "okay"; -}; - -&i2c1 { - status = "okay"; - - accel1: accelerometer@53 { - compatible = "adi,adxl345"; - reg = <0x53>; - - interrupt-parent = <&portc>; - interrupts = <3 2>; - }; -}; - -&mmc0 { - vmmc-supply = <®ulator_3_3v>; - vqmmc-supply = <®ulator_3_3v>; - status = "okay"; -}; - -&qspi { - status = "okay"; - - flash: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "n25q00"; - reg = <0>; - spi-max-frequency = <100000000>; - - m25p,fast-read; - cdns,page-size = <256>; - cdns,block-size = <16>; - cdns,read-delay = <4>; - cdns,tshsl-ns = <50>; - cdns,tsd2d-ns = <50>; - cdns,tchsh-ns = <4>; - cdns,tslch-ns = <4>; - }; -}; - -&usb1 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/socfpga_cyclone5_socrates.dts b/sys/gnu/dts/arm/socfpga_cyclone5_socrates.dts deleted file mode 100644 index 8d5d3996f6f..00000000000 --- a/sys/gnu/dts/arm/socfpga_cyclone5_socrates.dts +++ /dev/null @@ -1,94 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2014 Steffen Trumtrar - */ - -#include "socfpga_cyclone5.dtsi" - -/ { - model = "EBV SOCrates"; - compatible = "ebv,socrates", "altr,socfpga-cyclone5", "altr,socfpga"; - - aliases { - ethernet0 = &gmac1; - }; - - chosen { - bootargs = "earlyprintk"; - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - name = "memory"; - device_type = "memory"; - reg = <0x0 0x40000000>; /* 1GB */ - }; - - leds: gpio-leds { - }; -}; - -&gmac1 { - phy-mode = "rgmii"; - status = "okay"; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - rtc: rtc@68 { - compatible = "st,m41t82"; - reg = <0x68>; - }; -}; - -&leds { - compatible = "gpio-leds"; - - led0 { - label = "led:green:heartbeat"; - gpios = <&porta 28 1>; - linux,default-trigger = "heartbeat"; - }; - - led1 { - label = "led:green:D7"; - gpios = <&portb 19 1>; - }; - - led2 { - label = "led:green:D8"; - gpios = <&portb 25 1>; - }; -}; - -&mmc { - status = "okay"; -}; - -&qspi { - status = "okay"; - - flash: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "n25q256a"; - reg = <0>; - spi-max-frequency = <100000000>; - m25p,fast-read; - cdns,read-delay = <4>; - cdns,tshsl-ns = <50>; - cdns,tsd2d-ns = <50>; - cdns,tchsh-ns = <4>; - cdns,tslch-ns = <4>; - status = "okay"; - }; -}; diff --git a/sys/gnu/dts/arm/socfpga_cyclone5_sodia.dts b/sys/gnu/dts/arm/socfpga_cyclone5_sodia.dts deleted file mode 100644 index 99a71757cdf..00000000000 --- a/sys/gnu/dts/arm/socfpga_cyclone5_sodia.dts +++ /dev/null @@ -1,132 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2016 Nobuhiro Iwamatsu - */ - -#include "socfpga_cyclone5.dtsi" -#include -#include - -/ { - model = "Altera SOCFPGA Cyclone V SoC Macnica Sodia board"; - compatible = "macnica,sodia", "altr,socfpga-cyclone5", "altr,socfpga"; - - chosen { - bootargs = "earlyprintk"; - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - name = "memory"; - device_type = "memory"; - reg = <0x0 0x40000000>; - }; - - aliases { - ethernet0 = &gmac1; - }; - - regulator_3_3v: 3-3-v-regulator { - compatible = "regulator-fixed"; - regulator-name = "3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - leds: gpio-leds { - compatible = "gpio-leds"; - - hps_led0 { - label = "hps:green:led0"; - gpios = <&portb 12 GPIO_ACTIVE_LOW>; - }; - - hps_led1 { - label = "hps:green:led1"; - gpios = <&portb 13 GPIO_ACTIVE_LOW>; - }; - - hps_led2 { - label = "hps:green:led2"; - gpios = <&portb 14 GPIO_ACTIVE_LOW>; - }; - - hps_led3 { - label = "hps:green:led3"; - gpios = <&portb 15 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&gmac1 { - status = "okay"; - phy-mode = "rgmii"; - phy = <&phy0>; - - mdio0 { - #address-cells = <1>; - #size-cells = <0>; - phy0: ethernet-phy@0 { - reg = <0>; - rxd0-skew-ps = <0>; - rxd1-skew-ps = <0>; - rxd2-skew-ps = <0>; - rxd3-skew-ps = <0>; - rxdv-skew-ps = <0>; - rxc-skew-ps = <3000>; - txen-skew-ps = <0>; - txc-skew-ps = <3000>; - }; - }; -}; - -&gpio1 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - eeprom@51 { - compatible = "atmel,24c32"; - reg = <0x51>; - pagesize = <32>; - }; - - rtc@68 { - compatible = "dallas,ds1339"; - reg = <0x68>; - }; -}; - -&mmc0 { - cd-gpios = <&portb 18 0>; - vmmc-supply = <®ulator_3_3v>; - vqmmc-supply = <®ulator_3_3v>; - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; - -&qspi { - status = "okay"; - - flash0: n25q512a@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "n25q512a"; - reg = <0>; - spi-max-frequency = <100000000>; - - m25p,fast-read; - cdns,page-size = <256>; - cdns,block-size = <16>; - cdns,read-delay = <4>; - cdns,tshsl-ns = <50>; - cdns,tsd2d-ns = <50>; - cdns,tchsh-ns = <4>; - cdns,tslch-ns = <4>; - }; -}; diff --git a/sys/gnu/dts/arm/socfpga_cyclone5_vining_fpga.dts b/sys/gnu/dts/arm/socfpga_cyclone5_vining_fpga.dts deleted file mode 100644 index a060718758b..00000000000 --- a/sys/gnu/dts/arm/socfpga_cyclone5_vining_fpga.dts +++ /dev/null @@ -1,267 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR X11) -/* - * Copyright (C) 2015 Marek Vasut - */ - -#include "socfpga_cyclone5.dtsi" -#include -#include - -/ { - model = "samtec VIN|ING FPGA"; - compatible = "samtec,vining", "altr,socfpga-cyclone5", "altr,socfpga"; - - chosen { - bootargs = "earlyprintk"; - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - name = "memory"; - device_type = "memory"; - reg = <0x0 0x40000000>; /* 1GB */ - }; - - aliases { - /* - * This allow the ethaddr uboot environment variable contents - * to be added to the gmac1 device tree blob. - */ - ethernet0 = &gmac1; - ethernet1 = &gmac0; - }; - - gpio-keys { - compatible = "gpio-keys"; - - hps_temp0 { - label = "BTN_0"; /* TEMP_OS */ - gpios = <&portc 18 GPIO_ACTIVE_LOW>; /* HPS_GPI5 */ - linux,code = ; - }; - - hps_hkey0 { - label = "GP_SWITCH"; /* GP_SWITCH */ - gpios = <&portc 19 GPIO_ACTIVE_LOW>; /* HPS_GPI6 */ - linux,code = ; - }; - - hps_hkey1 { - label = "RESET_SWITCH"; /* RESET_SWITCH */ - gpios = <&portc 20 GPIO_ACTIVE_LOW>; /* HPS_GPI7 */ - linux,code = ; - }; - - hps_hkey2 { - label = "POWER_DOWN"; /* POWER_DOWN */ - gpios = <&portc 4 GPIO_ACTIVE_LOW>; /* HPS_GPIO62 */ - linux,code = ; - }; - - hps_hkey3 { - label = "SENSE"; /* SENSE */ - gpios = <&porta 9 GPIO_ACTIVE_LOW>; /* HPS_GPIO9 */ - linux,code = ; - }; - }; - - regulator-usb-nrst { - compatible = "regulator-fixed"; - regulator-name = "usb_nrst"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&portb 5 GPIO_ACTIVE_HIGH>; - startup-delay-us = <70000>; - enable-active-high; - regulator-always-on; - }; -}; - -&gmac1 { - status = "okay"; - phy-mode = "rgmii"; - phy-handle = <&phy1>; - - snps,reset-gpio = <&porta 0 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <10000 10000 10000>; - - mdio0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - phy1: ethernet-phy@1 { - reg = <1>; - rxd0-skew-ps = <0>; - rxd1-skew-ps = <0>; - rxd2-skew-ps = <0>; - rxd3-skew-ps = <0>; - txd0-skew-ps = <0>; - txd1-skew-ps = <0>; - txd2-skew-ps = <0>; - txd3-skew-ps = <0>; - txen-skew-ps = <0>; - txc-skew-ps = <1860>; - rxdv-skew-ps = <0>; - rxc-skew-ps = <1860>; - }; - }; -}; - -&gpio0 { /* GPIO 0..29 */ - status = "okay"; -}; - -&gpio1 { /* GPIO 30..57 */ - status = "okay"; -}; - -&gpio2 { /* GPIO 58..66 (HLGPI 0..13 at offset 13) */ - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - gpio: pca9557@1f { - compatible = "nxp,pca9557"; - reg = <0x1f>; - gpio-controller; - #gpio-cells = <2>; - }; - - temp: lm75@48 { - compatible = "lm75"; - reg = <0x48>; - }; - - at24@50 { - compatible = "atmel,24c01"; - pagesize = <8>; - reg = <0x50>; - }; - - i2cswitch@70 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x70>; - - i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - - i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - - i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - - i2c@6 { /* Backplane EEPROM */ - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - eeprom@51 { - compatible = "atmel,24c01"; - pagesize = <8>; - reg = <0x51>; - }; - }; - - i2c@7 { /* Power board EEPROM */ - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - eeprom@51 { - compatible = "atmel,24c01"; - pagesize = <8>; - reg = <0x51>; - }; - }; - }; -}; - -&i2c1 { - status = "okay"; - clock-frequency = <100000>; - - at24@50 { - compatible = "atmel,24c02"; - pagesize = <8>; - reg = <0x50>; - }; -}; - -&qspi { - status = "okay"; - - n25q128@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "n25q128"; - reg = <0>; /* chip select */ - spi-max-frequency = <100000000>; - m25p,fast-read; - - cdns,page-size = <256>; - cdns,block-size = <16>; - cdns,read-delay = <4>; - cdns,tshsl-ns = <50>; - cdns,tsd2d-ns = <50>; - cdns,tchsh-ns = <4>; - cdns,tslch-ns = <4>; - }; - - n25q00@1 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "n25q00"; - reg = <1>; /* chip select */ - spi-max-frequency = <100000000>; - m25p,fast-read; - - cdns,page-size = <256>; - cdns,block-size = <16>; - cdns,read-delay = <4>; - cdns,tshsl-ns = <50>; - cdns,tsd2d-ns = <50>; - cdns,tchsh-ns = <4>; - cdns,tslch-ns = <4>; - }; -}; - -&usb0 { - dr_mode = "host"; - status = "okay"; -}; - -&usb1 { - dr_mode = "peripheral"; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/socfpga_vt.dts b/sys/gnu/dts/arm/socfpga_vt.dts deleted file mode 100644 index a77846f73b3..00000000000 --- a/sys/gnu/dts/arm/socfpga_vt.dts +++ /dev/null @@ -1,77 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2013 Altera Corporation - */ - -/dts-v1/; -#include "socfpga.dtsi" - -/ { - model = "Altera SOCFPGA VT"; - compatible = "altr,socfpga-vt", "altr,socfpga"; - - chosen { - bootargs = "console=ttyS0,57600"; - }; - - memory@0 { - name = "memory"; - device_type = "memory"; - reg = <0x0 0x40000000>; /* 1 GB */ - }; - - soc { - clkmgr@ffd04000 { - clocks { - osc1 { - clock-frequency = <10000000>; - }; - }; - }; - - dwmmc0@ff704000 { - broken-cd; - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - }; - - ethernet@ff700000 { - phy-mode = "gmii"; - status = "okay"; - }; - - timer0@ffc08000 { - clock-frequency = <7000000>; - }; - - timer1@ffc09000 { - clock-frequency = <7000000>; - }; - - timer2@ffd00000 { - clock-frequency = <7000000>; - }; - - timer3@ffd01000 { - clock-frequency = <7000000>; - }; - - serial0@ffc02000 { - clock-frequency = <7372800>; - }; - - serial1@ffc03000 { - clock-frequency = <7372800>; - }; - - sysmgr@ffd08000 { - cpu1-start-addr = <0xffd08010>; - }; - }; -}; - -&gmac0 { - status = "okay"; - phy-mode = "gmii"; -}; diff --git a/sys/gnu/dts/arm/spear1310-evb.dts b/sys/gnu/dts/arm/spear1310-evb.dts deleted file mode 100644 index 8fcb6be6e7c..00000000000 --- a/sys/gnu/dts/arm/spear1310-evb.dts +++ /dev/null @@ -1,421 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * DTS file for SPEAr1310 Evaluation Baord - * - * Copyright 2012 Viresh Kumar - */ - -/dts-v1/; -/include/ "spear1310.dtsi" - -/ { - model = "ST SPEAr1310 Evaluation Board"; - compatible = "st,spear1310-evb", "st,spear1310"; - #address-cells = <1>; - #size-cells = <1>; - - memory { - reg = <0 0x40000000>; - }; - - ahb { - pinmux@e0700000 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - i2c0 { - st,pins = "i2c0_grp"; - st,function = "i2c0"; - }; - i2s0 { - st,pins = "i2s0_grp"; - st,function = "i2s0"; - }; - i2s1 { - st,pins = "i2s1_grp"; - st,function = "i2s1"; - }; - gpio { - st,pins = "arm_gpio_grp"; - st,function = "arm_gpio"; - }; - clcd { - st,pins = "clcd_grp" , "clcd_high_res"; - st,function = "clcd"; - }; - eth { - st,pins = "gmii_grp"; - st,function = "gmii"; - }; - ssp0 { - st,pins = "ssp0_grp"; - st,function = "ssp0"; - }; - kbd { - st,pins = "keyboard_6x6_grp"; - st,function = "keyboard"; - }; - sdhci { - st,pins = "sdhci_grp"; - st,function = "sdhci"; - }; - smi-pmx { - st,pins = "smi_2_chips_grp"; - st,function = "smi"; - }; - uart0 { - st,pins = "uart0_grp"; - st,function = "uart0"; - }; - rs485 { - st,pins = "rs485_0_1_tdm_0_1_grp"; - st,function = "rs485_0_1_tdm_0_1"; - }; - i2c1_2 { - st,pins = "i2c_1_2_grp"; - st,function = "i2c_1_2"; - }; - smii { - st,pins = "smii_0_1_2_grp"; - st,function = "smii_0_1_2"; - }; - nand { - st,pins = "nand_8bit_grp", - "nand_16bit_grp"; - st,function = "nand"; - }; - sata { - st,pins = "sata0_grp"; - st,function = "sata"; - }; - pcie { - st,pins = "pcie1_grp", "pcie2_grp"; - st,function = "pci_express"; - }; - }; - }; - - ahci@b1000000 { - status = "okay"; - }; - - miphy@eb800000 { - status = "okay"; - }; - - cf@b2800000 { - status = "okay"; - }; - - dma@ea800000 { - status = "okay"; - }; - - dma@eb000000 { - status = "okay"; - }; - - fsmc: flash@b0000000 { - status = "okay"; - - partition@0 { - label = "xloader"; - reg = <0x0 0x80000>; - }; - partition@80000 { - label = "u-boot"; - reg = <0x80000 0x140000>; - }; - partition@1C0000 { - label = "environment"; - reg = <0x1C0000 0x40000>; - }; - partition@200000 { - label = "dtb"; - reg = <0x200000 0x40000>; - }; - partition@240000 { - label = "linux"; - reg = <0x240000 0xC00000>; - }; - partition@E40000 { - label = "rootfs"; - reg = <0xE40000 0x0>; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - button@1 { - label = "wakeup"; - linux,code = <0x100>; - gpios = <&gpio0 7 0x4>; - debounce-interval = <20>; - wakeup-source; - }; - }; - - gmac0: eth@e2000000 { - phy-mode = "gmii"; - status = "okay"; - }; - - sdhci@b3000000 { - status = "okay"; - }; - - smi: flash@ea000000 { - status = "okay"; - clock-rate=<50000000>; - - flash@e6000000 { - #address-cells = <1>; - #size-cells = <1>; - reg = <0xe6000000 0x800000>; - st,smi-fast-mode; - - partition@0 { - label = "xloader"; - reg = <0x0 0x10000>; - }; - partition@10000 { - label = "u-boot"; - reg = <0x10000 0x50000>; - }; - partition@60000 { - label = "environment"; - reg = <0x60000 0x10000>; - }; - partition@70000 { - label = "dtb"; - reg = <0x70000 0x10000>; - }; - partition@80000 { - label = "linux"; - reg = <0x80000 0x310000>; - }; - partition@390000 { - label = "rootfs"; - reg = <0x390000 0x0>; - }; - }; - }; - - ehci@e4800000 { - status = "okay"; - }; - - ehci@e5800000 { - status = "okay"; - }; - - ohci@e4000000 { - status = "okay"; - }; - - ohci@e5000000 { - status = "okay"; - }; - - apb { - adc@e0080000 { - status = "okay"; - }; - - gpio0: gpio@e0600000 { - status = "okay"; - }; - - gpio1: gpio@e0680000 { - status = "okay"; - }; - - gpio@d8400000 { - status = "okay"; - }; - - i2c0: i2c@e0280000 { - status = "okay"; - }; - - kbd@e0300000 { - linux,keymap = < 0x00000001 - 0x00010002 - 0x00020003 - 0x00030004 - 0x00040005 - 0x00050006 - 0x00060007 - 0x00070008 - 0x00080009 - 0x0100000a - 0x0101000c - 0x0102000d - 0x0103000e - 0x0104000f - 0x01050010 - 0x01060011 - 0x01070012 - 0x01080013 - 0x02000014 - 0x02010015 - 0x02020016 - 0x02030017 - 0x02040018 - 0x02050019 - 0x0206001a - 0x0207001b - 0x0208001c - 0x0300001d - 0x0301001e - 0x0302001f - 0x03030020 - 0x03040021 - 0x03050022 - 0x03060023 - 0x03070024 - 0x03080025 - 0x04000026 - 0x04010027 - 0x04020028 - 0x04030029 - 0x0404002a - 0x0405002b - 0x0406002c - 0x0407002d - 0x0408002e - 0x0500002f - 0x05010030 - 0x05020031 - 0x05030032 - 0x05040033 - 0x05050034 - 0x05060035 - 0x05070036 - 0x05080037 - 0x06000038 - 0x06010039 - 0x0602003a - 0x0603003b - 0x0604003c - 0x0605003d - 0x0606003e - 0x0607003f - 0x06080040 - 0x07000041 - 0x07010042 - 0x07020043 - 0x07030044 - 0x07040045 - 0x07050046 - 0x07060047 - 0x07070048 - 0x07080049 - 0x0800004a - 0x0801004b - 0x0802004c - 0x0803004d - 0x0804004e - 0x0805004f - 0x08060050 - 0x08070051 - 0x08080052 >; - autorepeat; - st,mode = <0>; - suspended_rate = <2000000>; - status = "okay"; - }; - - rtc@e0580000 { - status = "okay"; - }; - - serial@e0000000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <>; - }; - - spi0: spi@e0100000 { - status = "okay"; - num-cs = <3>; - cs-gpios = <&gpio1 7 0>, <&spics 0 0>, <&spics 1 0>; - - stmpe610@0 { - compatible = "st,stmpe610"; - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - spi-max-frequency = <1000000>; - spi-cpha; - pl022,hierarchy = <0>; - pl022,interface = <0>; - pl022,slave-tx-disable; - pl022,com-mode = <0>; - pl022,rx-level-trig = <0>; - pl022,tx-level-trig = <0>; - pl022,ctrl-len = <0x7>; - pl022,wait-state = <0>; - pl022,duplex = <0>; - interrupts = <6 0x4>; - interrupt-parent = <&gpio1>; - irq-trigger = <0x2>; - - stmpe_touchscreen { - compatible = "st,stmpe-ts"; - ts,sample-time = <4>; - ts,mod-12b = <1>; - ts,ref-sel = <0>; - ts,adc-freq = <1>; - ts,ave-ctrl = <1>; - ts,touch-det-delay = <2>; - ts,settling = <2>; - ts,fraction-z = <7>; - ts,i-drive = <1>; - }; - }; - - m25p80@1 { - compatible = "st,m25p80"; - reg = <1>; - spi-max-frequency = <12000000>; - spi-cpol; - spi-cpha; - pl022,hierarchy = <0>; - pl022,interface = <0>; - pl022,slave-tx-disable; - pl022,com-mode = <0x2>; - pl022,rx-level-trig = <0>; - pl022,tx-level-trig = <0>; - pl022,ctrl-len = <0x11>; - pl022,wait-state = <0>; - pl022,duplex = <0>; - }; - - spidev@2 { - compatible = "spidev"; - reg = <2>; - spi-max-frequency = <25000000>; - spi-cpha; - pl022,hierarchy = <0>; - pl022,interface = <0>; - pl022,slave-tx-disable; - pl022,com-mode = <0x2>; - pl022,rx-level-trig = <0>; - pl022,tx-level-trig = <0>; - pl022,ctrl-len = <0x11>; - pl022,wait-state = <0>; - pl022,duplex = <0>; - }; - }; - - wdt@ec800620 { - status = "okay"; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/spear1310.dtsi b/sys/gnu/dts/arm/spear1310.dtsi deleted file mode 100644 index c4b49baf980..00000000000 --- a/sys/gnu/dts/arm/spear1310.dtsi +++ /dev/null @@ -1,313 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * DTS file for all SPEAr1310 SoCs - * - * Copyright 2012 Viresh Kumar - */ - -/include/ "spear13xx.dtsi" - -/ { - compatible = "st,spear1310"; - - ahb { - spics: spics@e0700000{ - compatible = "st,spear-spics-gpio"; - reg = <0xe0700000 0x1000>; - st-spics,peripcfg-reg = <0x3b0>; - st-spics,sw-enable-bit = <12>; - st-spics,cs-value-bit = <11>; - st-spics,cs-enable-mask = <3>; - st-spics,cs-enable-shift = <8>; - gpio-controller; - #gpio-cells = <2>; - }; - - miphy0: miphy@eb800000 { - compatible = "st,spear1310-miphy"; - reg = <0xeb800000 0x4000>; - misc = <&misc>; - phy-id = <0>; - #phy-cells = <1>; - status = "disabled"; - }; - - miphy1: miphy@eb804000 { - compatible = "st,spear1310-miphy"; - reg = <0xeb804000 0x4000>; - misc = <&misc>; - phy-id = <1>; - #phy-cells = <1>; - status = "disabled"; - }; - - miphy2: miphy@eb808000 { - compatible = "st,spear1310-miphy"; - reg = <0xeb808000 0x4000>; - misc = <&misc>; - phy-id = <2>; - #phy-cells = <1>; - status = "disabled"; - }; - - ahci0: ahci@b1000000 { - compatible = "snps,spear-ahci"; - reg = <0xb1000000 0x10000>; - interrupts = <0 68 0x4>; - phys = <&miphy0 0>; - phy-names = "sata-phy"; - status = "disabled"; - }; - - ahci1: ahci@b1800000 { - compatible = "snps,spear-ahci"; - reg = <0xb1800000 0x10000>; - interrupts = <0 69 0x4>; - phys = <&miphy1 0>; - phy-names = "sata-phy"; - status = "disabled"; - }; - - ahci2: ahci@b4000000 { - compatible = "snps,spear-ahci"; - reg = <0xb4000000 0x10000>; - interrupts = <0 70 0x4>; - phys = <&miphy2 0>; - phy-names = "sata-phy"; - status = "disabled"; - }; - - pcie0: pcie@b1000000 { - compatible = "st,spear1340-pcie", "snps,dw-pcie"; - reg = <0xb1000000 0x4000>, <0x80000000 0x20000>; - reg-names = "dbi", "config"; - interrupts = <0 68 0x4>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0x0 0 &gic 0 68 0x4>; - num-lanes = <1>; - phys = <&miphy0 1>; - phy-names = "pcie-phy"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges = <0x81000000 0 0 0x80020000 0 0x00010000 /* downstream I/O */ - 0x82000000 0 0x80030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */ - bus-range = <0x00 0xff>; - status = "disabled"; - }; - - pcie1: pcie@b1800000 { - compatible = "st,spear1340-pcie", "snps,dw-pcie"; - reg = <0xb1800000 0x4000>, <0x90000000 0x20000>; - reg-names = "dbi", "config"; - interrupts = <0 69 0x4>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0x0 0 &gic 0 69 0x4>; - num-lanes = <1>; - phys = <&miphy1 1>; - phy-names = "pcie-phy"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges = <0x81000000 0 0 0x90020000 0 0x00010000 /* downstream I/O */ - 0x82000000 0 0x90030000 0x90030000 0 0x0ffd0000>; /* non-prefetchable memory */ - bus-range = <0x00 0xff>; - status = "disabled"; - }; - - pcie2: pcie@b4000000 { - compatible = "st,spear1340-pcie", "snps,dw-pcie"; - reg = <0xb4000000 0x4000>, <0xc0000000 0x20000>; - reg-names = "dbi", "config"; - interrupts = <0 70 0x4>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0x0 0 &gic 0 70 0x4>; - num-lanes = <1>; - phys = <&miphy2 1>; - phy-names = "pcie-phy"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges = <0x81000000 0 0 0xc0020000 0 0x00010000 /* downstream I/O */ - 0x82000000 0 0xc0030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */ - bus-range = <0x00 0xff>; - status = "disabled"; - }; - - gmac1: eth@5c400000 { - compatible = "st,spear600-gmac"; - reg = <0x5c400000 0x8000>; - interrupts = <0 95 0x4>; - interrupt-names = "macirq"; - phy-mode = "mii"; - status = "disabled"; - }; - - gmac2: eth@5c500000 { - compatible = "st,spear600-gmac"; - reg = <0x5c500000 0x8000>; - interrupts = <0 96 0x4>; - interrupt-names = "macirq"; - phy-mode = "mii"; - status = "disabled"; - }; - - gmac3: eth@5c600000 { - compatible = "st,spear600-gmac"; - reg = <0x5c600000 0x8000>; - interrupts = <0 97 0x4>; - interrupt-names = "macirq"; - phy-mode = "rmii"; - status = "disabled"; - }; - - gmac4: eth@5c700000 { - compatible = "st,spear600-gmac"; - reg = <0x5c700000 0x8000>; - interrupts = <0 98 0x4>; - interrupt-names = "macirq"; - phy-mode = "rgmii"; - status = "disabled"; - }; - - pinmux: pinmux@e0700000 { - compatible = "st,spear1310-pinmux"; - reg = <0xe0700000 0x1000>; - #gpio-range-cells = <3>; - }; - - apb { - i2c1: i2c@5cd00000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0x5cd00000 0x1000>; - interrupts = <0 87 0x4>; - status = "disabled"; - }; - - i2c2: i2c@5ce00000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0x5ce00000 0x1000>; - interrupts = <0 88 0x4>; - status = "disabled"; - }; - - i2c3: i2c@5cf00000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0x5cf00000 0x1000>; - interrupts = <0 89 0x4>; - status = "disabled"; - }; - - i2c4: i2c@5d000000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0x5d000000 0x1000>; - interrupts = <0 90 0x4>; - status = "disabled"; - }; - - i2c5: i2c@5d100000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0x5d100000 0x1000>; - interrupts = <0 91 0x4>; - status = "disabled"; - }; - - i2c6: i2c@5d200000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0x5d200000 0x1000>; - interrupts = <0 92 0x4>; - status = "disabled"; - }; - - i2c7: i2c@5d300000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0x5d300000 0x1000>; - interrupts = <0 93 0x4>; - status = "disabled"; - }; - - spi1: spi@5d400000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x5d400000 0x1000>; - interrupts = <0 99 0x4>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - serial@5c800000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x5c800000 0x1000>; - interrupts = <0 82 0x4>; - status = "disabled"; - }; - - serial@5c900000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x5c900000 0x1000>; - interrupts = <0 83 0x4>; - status = "disabled"; - }; - - serial@5ca00000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x5ca00000 0x1000>; - interrupts = <0 84 0x4>; - status = "disabled"; - }; - - serial@5cb00000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x5cb00000 0x1000>; - interrupts = <0 85 0x4>; - status = "disabled"; - }; - - serial@5cc00000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x5cc00000 0x1000>; - interrupts = <0 86 0x4>; - status = "disabled"; - }; - - thermal@e07008c4 { - st,thermal-flags = <0x7000>; - }; - - gpiopinctrl: gpio@d8400000 { - compatible = "st,spear-plgpio"; - reg = <0xd8400000 0x1000>; - interrupts = <0 100 0x4>; - #interrupt-cells = <1>; - interrupt-controller; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinmux 0 0 246>; - status = "disabled"; - - st-plgpio,ngpio = <246>; - st-plgpio,enb-reg = <0xd0>; - st-plgpio,wdata-reg = <0x90>; - st-plgpio,dir-reg = <0xb0>; - st-plgpio,ie-reg = <0x30>; - st-plgpio,rdata-reg = <0x70>; - st-plgpio,mis-reg = <0x10>; - st-plgpio,eit-reg = <0x50>; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/spear1340-evb.dts b/sys/gnu/dts/arm/spear1340-evb.dts deleted file mode 100644 index f70ff56d454..00000000000 --- a/sys/gnu/dts/arm/spear1340-evb.dts +++ /dev/null @@ -1,519 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * DTS file for SPEAr1340 Evaluation Baord - * - * Copyright 2012 Viresh Kumar - */ - -/dts-v1/; -/include/ "spear1340.dtsi" - -/ { - model = "ST SPEAr1340 Evaluation Board"; - compatible = "st,spear1340-evb", "st,spear1340"; - #address-cells = <1>; - #size-cells = <1>; - - memory { - reg = <0 0x40000000>; - }; - - ahb { - pinmux@e0700000 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - pads_as_gpio { - st,pins = "pads_as_gpio_grp"; - st,function = "pads_as_gpio"; - }; - fsmc { - st,pins = "fsmc_8bit_grp"; - st,function = "fsmc"; - }; - uart0 { - st,pins = "uart0_grp"; - st,function = "uart0"; - }; - i2c0 { - st,pins = "i2c0_grp"; - st,function = "i2c0"; - }; - i2c1 { - st,pins = "i2c1_grp"; - st,function = "i2c1"; - }; - spdif-in { - st,pins = "spdif_in_grp"; - st,function = "spdif_in"; - }; - spdif-out { - st,pins = "spdif_out_grp"; - st,function = "spdif_out"; - }; - ssp0 { - st,pins = "ssp0_grp", "ssp0_cs1_grp", "ssp0_cs2_grp", "ssp0_cs3_grp"; - st,function = "ssp0"; - }; - smi-pmx { - st,pins = "smi_grp"; - st,function = "smi"; - }; - i2s { - st,pins = "i2s_in_grp", "i2s_out_grp"; - st,function = "i2s"; - }; - gmac { - st,pins = "gmii_grp", "rgmii_grp"; - st,function = "gmac"; - }; - cam0 { - st,pins = "cam0_grp"; - st,function = "cam0"; - }; - cam1 { - st,pins = "cam1_grp"; - st,function = "cam1"; - }; - cam2 { - st,pins = "cam2_grp"; - st,function = "cam2"; - }; - cam3 { - st,pins = "cam3_grp"; - st,function = "cam3"; - }; - cec0 { - st,pins = "cec0_grp"; - st,function = "cec0"; - }; - cec1 { - st,pins = "cec1_grp"; - st,function = "cec1"; - }; - sdhci { - st,pins = "sdhci_grp"; - st,function = "sdhci"; - }; - clcd { - st,pins = "clcd_grp"; - st,function = "clcd"; - }; - sata { - st,pins = "sata_grp"; - st,function = "sata"; - }; - pcie { - st,pins = "pcie_grp"; - st,function = "pcie"; - }; - - }; - }; - - ahci@b1000000 { - status = "okay"; - }; - - miphy@eb800000 { - status = "okay"; - }; - - dma@ea800000 { - status = "okay"; - }; - - dma@eb000000 { - status = "okay"; - }; - - fsmc: flash@b0000000 { - status = "okay"; - - partition@0 { - label = "xloader"; - reg = <0x0 0x200000>; - }; - partition@200000 { - label = "u-boot"; - reg = <0x200000 0x200000>; - }; - partition@400000 { - label = "environment"; - reg = <0x400000 0x100000>; - }; - partition@500000 { - label = "dtb"; - reg = <0x500000 0x100000>; - }; - partition@600000 { - label = "linux"; - reg = <0x600000 0xC00000>; - }; - partition@1200000 { - label = "rootfs"; - reg = <0x1200000 0x0>; - }; - }; - - gmac0: eth@e2000000 { - phy-mode = "rgmii"; - status = "okay"; - }; - - sdhci@b3000000 { - status = "okay"; - }; - - smi: flash@ea000000 { - status = "okay"; - clock-rate=<50000000>; - - flash@e6000000 { - #address-cells = <1>; - #size-cells = <1>; - reg = <0xe6000000 0x800000>; - st,smi-fast-mode; - - partition@0 { - label = "xloader"; - reg = <0x0 0x10000>; - }; - partition@10000 { - label = "u-boot"; - reg = <0x10000 0x50000>; - }; - partition@60000 { - label = "environment"; - reg = <0x60000 0x10000>; - }; - partition@70000 { - label = "dtb"; - reg = <0x70000 0x10000>; - }; - partition@80000 { - label = "linux"; - reg = <0x80000 0x310000>; - }; - partition@390000 { - label = "rootfs"; - reg = <0x390000 0x0>; - }; - }; - }; - - ehci@e4800000 { - status = "okay"; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - button@1 { - label = "wakeup"; - linux,code = <0x100>; - gpios = <&gpio1 1 0x4>; - debounce-interval = <20>; - wakeup-source; - }; - }; - - ehci@e5800000 { - status = "okay"; - }; - - i2s0: i2s-play@b2400000 { - status = "okay"; - }; - - i2s1: i2s-rec@b2000000 { - status = "okay"; - }; - - incodec: dir-hifi { - compatible = "dummy,dir-hifi"; - status = "okay"; - }; - - ohci@e4000000 { - status = "okay"; - }; - - ohci@e5000000 { - status = "okay"; - }; - - outcodec: dit-hifi { - compatible = "dummy,dit-hifi"; - status = "okay"; - }; - - sound { - compatible = "spear,spear-evb"; - audio-controllers = <&spdif0 &spdif1 &i2s0 &i2s1>; - audio-codecs = <&incodec &outcodec &sta529 &sta529>; - codec_dai_name = "dir-hifi", "dit-hifi", "sta529-audio", "sta529-audio"; - stream_name = "spdif-cap", "spdif-play", "i2s-play", "i2s-cap"; - dai_name = "spdifin-pcm", "spdifout-pcm", "i2s0-pcm", "i2s1-pcm"; - nr_controllers = <4>; - status = "okay"; - }; - - spdif0: spdif-in@d0100000 { - status = "okay"; - }; - - spdif1: spdif-out@d0000000 { - status = "okay"; - }; - - apb { - adc@e0080000 { - status = "okay"; - }; - - i2s-play@b2400000 { - status = "okay"; - }; - - i2s-rec@b2000000 { - status = "okay"; - }; - - gpio0: gpio@e0600000 { - status = "okay"; - }; - - gpio1: gpio@e0680000 { - status = "okay"; - }; - - gpio@e2800000 { - status = "okay"; - }; - - i2c0: i2c@e0280000 { - status = "okay"; - - sta529: sta529@1a { - compatible = "st,sta529"; - reg = <0x1a>; - }; - }; - - i2c1: i2c@b4000000 { - status = "okay"; - - eeprom0@56 { - compatible = "st,eeprom"; - reg = <0x56>; - }; - - stmpe801@41 { - compatible = "st,stmpe801"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x41>; - interrupts = <4 0x4>; - interrupt-parent = <&gpio0>; - irq-trigger = <0x2>; - - stmpegpio: stmpe_gpio { - compatible = "st,stmpe-gpio"; - gpio-controller; - #gpio-cells = <2>; - }; - }; - }; - - kbd@e0300000 { - linux,keymap = < 0x00000001 - 0x00010002 - 0x00020003 - 0x00030004 - 0x00040005 - 0x00050006 - 0x00060007 - 0x00070008 - 0x00080009 - 0x0100000a - 0x0101000c - 0x0102000d - 0x0103000e - 0x0104000f - 0x01050010 - 0x01060011 - 0x01070012 - 0x01080013 - 0x02000014 - 0x02010015 - 0x02020016 - 0x02030017 - 0x02040018 - 0x02050019 - 0x0206001a - 0x0207001b - 0x0208001c - 0x0300001d - 0x0301001e - 0x0302001f - 0x03030020 - 0x03040021 - 0x03050022 - 0x03060023 - 0x03070024 - 0x03080025 - 0x04000026 - 0x04010027 - 0x04020028 - 0x04030029 - 0x0404002a - 0x0405002b - 0x0406002c - 0x0407002d - 0x0408002e - 0x0500002f - 0x05010030 - 0x05020031 - 0x05030032 - 0x05040033 - 0x05050034 - 0x05060035 - 0x05070036 - 0x05080037 - 0x06000038 - 0x06010039 - 0x0602003a - 0x0603003b - 0x0604003c - 0x0605003d - 0x0606003e - 0x0607003f - 0x06080040 - 0x07000041 - 0x07010042 - 0x07020043 - 0x07030044 - 0x07040045 - 0x07050046 - 0x07060047 - 0x07070048 - 0x07080049 - 0x0800004a - 0x0801004b - 0x0802004c - 0x0803004d - 0x0804004e - 0x0805004f - 0x08060050 - 0x08070051 - 0x08080052 >; - autorepeat; - st,mode = <0>; - suspended_rate = <2000000>; - status = "okay"; - }; - - rtc@e0580000 { - status = "okay"; - }; - - serial@e0000000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <>; - }; - - serial@b4100000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <>; - }; - - spi0: spi@e0100000 { - status = "okay"; - num-cs = <3>; - cs-gpios = <&gpiopinctrl 80 0>, <&gpiopinctrl 24 0>, - <&gpiopinctrl 85 0>; - - m25p80@0 { - compatible = "m25p80"; - reg = <0>; - spi-max-frequency = <12000000>; - spi-cpol; - spi-cpha; - pl022,hierarchy = <0>; - pl022,interface = <0>; - pl022,slave-tx-disable; - pl022,com-mode = <0x2>; - pl022,rx-level-trig = <0>; - pl022,tx-level-trig = <0>; - pl022,ctrl-len = <0x11>; - pl022,wait-state = <0>; - pl022,duplex = <0>; - }; - - stmpe610@1 { - compatible = "st,stmpe610"; - spi-max-frequency = <1000000>; - spi-cpha; - reg = <1>; - pl022,hierarchy = <0>; - pl022,interface = <0>; - pl022,slave-tx-disable; - pl022,com-mode = <0>; - pl022,rx-level-trig = <0>; - pl022,tx-level-trig = <0>; - pl022,ctrl-len = <0x7>; - pl022,wait-state = <0>; - pl022,duplex = <0>; - interrupts = <100 0>; - interrupt-parent = <&gpiopinctrl>; - irq-trigger = <0x2>; - #address-cells = <1>; - #size-cells = <0>; - - stmpe_touchscreen { - compatible = "st,stmpe-ts"; - ts,sample-time = <4>; - ts,mod-12b = <1>; - ts,ref-sel = <0>; - ts,adc-freq = <1>; - ts,ave-ctrl = <1>; - ts,touch-det-delay = <2>; - ts,settling = <2>; - ts,fraction-z = <7>; - ts,i-drive = <1>; - }; - }; - - spidev@2 { - compatible = "spidev"; - reg = <2>; - spi-max-frequency = <25000000>; - spi-cpha; - pl022,hierarchy = <0>; - pl022,interface = <0>; - pl022,slave-tx-disable; - pl022,com-mode = <0x2>; - pl022,rx-level-trig = <0>; - pl022,tx-level-trig = <0>; - pl022,ctrl-len = <0x11>; - pl022,wait-state = <0>; - pl022,duplex = <0>; - }; - }; - - timer@ec800600 { - status = "okay"; - }; - - wdt@ec800620 { - status = "okay"; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/spear1340.dtsi b/sys/gnu/dts/arm/spear1340.dtsi deleted file mode 100644 index 1a8f5e8b10e..00000000000 --- a/sys/gnu/dts/arm/spear1340.dtsi +++ /dev/null @@ -1,169 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * DTS file for all SPEAr1340 SoCs - * - * Copyright 2012 Viresh Kumar - */ - -/include/ "spear13xx.dtsi" - -/ { - compatible = "st,spear1340"; - - ahb { - - spics: spics@e0700000{ - compatible = "st,spear-spics-gpio"; - reg = <0xe0700000 0x1000>; - st-spics,peripcfg-reg = <0x42c>; - st-spics,sw-enable-bit = <21>; - st-spics,cs-value-bit = <20>; - st-spics,cs-enable-mask = <3>; - st-spics,cs-enable-shift = <18>; - gpio-controller; - #gpio-cells = <2>; - status = "disabled"; - }; - - miphy0: miphy@eb800000 { - compatible = "st,spear1340-miphy"; - reg = <0xeb800000 0x4000>; - misc = <&misc>; - #phy-cells = <1>; - status = "disabled"; - }; - - ahci0: ahci@b1000000 { - compatible = "snps,spear-ahci"; - reg = <0xb1000000 0x10000>; - interrupts = <0 72 0x4>; - phys = <&miphy0 0>; - phy-names = "sata-phy"; - status = "disabled"; - }; - - pcie0: pcie@b1000000 { - compatible = "st,spear1340-pcie", "snps,dw-pcie"; - reg = <0xb1000000 0x4000>, <0x80000000 0x20000>; - reg-names = "dbi", "config"; - interrupts = <0 68 0x4>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0x0 0 &gic 0 68 0x4>; - num-lanes = <1>; - phys = <&miphy0 1>; - phy-names = "pcie-phy"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges = <0x81000000 0 0 0x80020000 0 0x00010000 /* downstream I/O */ - 0x82000000 0 0x80030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */ - bus-range = <0x00 0xff>; - status = "disabled"; - }; - - i2s-play@b2400000 { - compatible = "snps,designware-i2s"; - reg = <0xb2400000 0x10000>; - interrupt-names = "play_irq"; - interrupts = <0 98 0x4 - 0 99 0x4>; - play; - channel = <8>; - status = "disabled"; - }; - - i2s-rec@b2000000 { - compatible = "snps,designware-i2s"; - reg = <0xb2000000 0x10000>; - interrupt-names = "record_irq"; - interrupts = <0 100 0x4 - 0 101 0x4>; - record; - channel = <8>; - status = "disabled"; - }; - - pinmux: pinmux@e0700000 { - compatible = "st,spear1340-pinmux"; - reg = <0xe0700000 0x1000>; - #gpio-range-cells = <3>; - }; - - pwm: pwm@e0180000 { - compatible ="st,spear13xx-pwm"; - reg = <0xe0180000 0x1000>; - #pwm-cells = <2>; - status = "disabled"; - }; - - spdif-in@d0100000 { - compatible = "st,spdif-in"; - reg = < 0xd0100000 0x20000 - 0xd0110000 0x10000 >; - interrupts = <0 84 0x4>; - status = "disabled"; - }; - - spdif-out@d0000000 { - compatible = "st,spdif-out"; - reg = <0xd0000000 0x20000>; - interrupts = <0 85 0x4>; - status = "disabled"; - }; - - spi1: spi@5d400000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x5d400000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 99 0x4>; - status = "disabled"; - }; - - apb { - i2c1: i2c@b4000000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0xb4000000 0x1000>; - interrupts = <0 104 0x4>; - write-16bit; - status = "disabled"; - }; - - serial@b4100000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0xb4100000 0x1000>; - interrupts = <0 105 0x4>; - status = "disabled"; - dmas = <&dwdma0 12 0 1>, - <&dwdma0 13 1 0>; - dma-names = "tx", "rx"; - }; - - thermal@e07008c4 { - st,thermal-flags = <0x2a00>; - }; - - gpiopinctrl: gpio@e2800000 { - compatible = "st,spear-plgpio"; - reg = <0xe2800000 0x1000>; - interrupts = <0 107 0x4>; - #interrupt-cells = <1>; - interrupt-controller; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinmux 0 0 252>; - status = "disabled"; - - st-plgpio,ngpio = <250>; - st-plgpio,wdata-reg = <0x40>; - st-plgpio,dir-reg = <0x00>; - st-plgpio,ie-reg = <0x80>; - st-plgpio,rdata-reg = <0x20>; - st-plgpio,mis-reg = <0xa0>; - st-plgpio,eit-reg = <0x60>; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/spear13xx.dtsi b/sys/gnu/dts/arm/spear13xx.dtsi deleted file mode 100644 index f187da4485f..00000000000 --- a/sys/gnu/dts/arm/spear13xx.dtsi +++ /dev/null @@ -1,339 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * DTS file for all SPEAr13xx SoCs - * - * Copyright 2012 Viresh Kumar - */ - -/ { - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&gic>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - reg = <0>; - next-level-cache = <&L2>; - }; - - cpu@1 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - reg = <1>; - next-level-cache = <&L2>; - }; - }; - - gic: interrupt-controller@ec801000 { - compatible = "arm,cortex-a9-gic"; - interrupt-controller; - #interrupt-cells = <3>; - reg = < 0xec801000 0x1000 >, - < 0xec800100 0x0100 >; - }; - - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts = <0 6 0x04 - 0 7 0x04>; - }; - - L2: l2-cache { - compatible = "arm,pl310-cache"; - reg = <0xed000000 0x1000>; - cache-unified; - cache-level = <2>; - }; - - memory { - name = "memory"; - device_type = "memory"; - reg = <0 0x40000000>; - }; - - chosen { - bootargs = "console=ttyAMA0,115200"; - }; - - cpufreq { - compatible = "st,cpufreq-spear"; - cpufreq_tbl = < 166000 - 200000 - 250000 - 300000 - 400000 - 500000 - 600000 >; - status = "disabled"; - }; - - ahb { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0x50000000 0x50000000 0x10000000 - 0x80000000 0x80000000 0x20000000 - 0xb0000000 0xb0000000 0x22000000 - 0xd8000000 0xd8000000 0x01000000 - 0xe0000000 0xe0000000 0x10000000>; - - sdhci@b3000000 { - compatible = "st,sdhci-spear"; - reg = <0xb3000000 0x100>; - interrupts = <0 28 0x4>; - status = "disabled"; - }; - - cf@b2800000 { - compatible = "arasan,cf-spear1340"; - reg = <0xb2800000 0x1000>; - interrupts = <0 29 0x4>; - status = "disabled"; - dmas = <&dwdma0 0 0 0>; - dma-names = "data"; - }; - - dwdma0: dma@ea800000 { - compatible = "snps,dma-spear1340"; - reg = <0xea800000 0x1000>; - interrupts = <0 19 0x4>; - status = "disabled"; - - dma-channels = <8>; - #dma-cells = <3>; - dma-requests = <32>; - chan_allocation_order = <1>; - chan_priority = <1>; - block_size = <0xfff>; - dma-masters = <2>; - data-width = <8 8>; - multi-block = <1 1 1 1 1 1 1 1>; - }; - - dma@eb000000 { - compatible = "snps,dma-spear1340"; - reg = <0xeb000000 0x1000>; - interrupts = <0 59 0x4>; - status = "disabled"; - - dma-requests = <32>; - dma-channels = <8>; - dma-masters = <2>; - #dma-cells = <3>; - chan_allocation_order = <1>; - chan_priority = <1>; - block_size = <0xfff>; - data-width = <8 8>; - multi-block = <1 1 1 1 1 1 1 1>; - }; - - fsmc: flash@b0000000 { - compatible = "st,spear600-fsmc-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0xb0000000 0x1000 /* FSMC Register*/ - 0xb0800000 0x0010 /* NAND Base DATA */ - 0xb0820000 0x0010 /* NAND Base ADDR */ - 0xb0810000 0x0010>; /* NAND Base CMD */ - reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd"; - interrupts = <0 20 0x4 - 0 21 0x4 - 0 22 0x4 - 0 23 0x4>; - st,mode = <2>; - status = "disabled"; - }; - - gmac0: eth@e2000000 { - compatible = "st,spear600-gmac"; - reg = <0xe2000000 0x8000>; - interrupts = <0 33 0x4 - 0 34 0x4>; - interrupt-names = "macirq", "eth_wake_irq"; - status = "disabled"; - }; - - pcm { - compatible = "st,pcm-audio"; - #address-cells = <0>; - #size-cells = <0>; - status = "disabled"; - }; - - smi: flash@ea000000 { - compatible = "st,spear600-smi"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0xea000000 0x1000>; - interrupts = <0 30 0x4>; - status = "disabled"; - }; - - ehci@e4800000 { - compatible = "st,spear600-ehci", "usb-ehci"; - reg = <0xe4800000 0x1000>; - interrupts = <0 64 0x4>; - usbh0_id = <0>; - status = "disabled"; - }; - - ehci@e5800000 { - compatible = "st,spear600-ehci", "usb-ehci"; - reg = <0xe5800000 0x1000>; - interrupts = <0 66 0x4>; - usbh1_id = <1>; - status = "disabled"; - }; - - ohci@e4000000 { - compatible = "st,spear600-ohci", "usb-ohci"; - reg = <0xe4000000 0x1000>; - interrupts = <0 65 0x4>; - usbh0_id = <0>; - status = "disabled"; - }; - - ohci@e5000000 { - compatible = "st,spear600-ohci", "usb-ohci"; - reg = <0xe5000000 0x1000>; - interrupts = <0 67 0x4>; - usbh1_id = <1>; - status = "disabled"; - }; - - apb { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0x50000000 0x50000000 0x10000000 - 0xb0000000 0xb0000000 0x10000000 - 0xd0000000 0xd0000000 0x02000000 - 0xd8000000 0xd8000000 0x01000000 - 0xe0000000 0xe0000000 0x10000000>; - - misc: syscon@e0700000 { - compatible = "st,spear1340-misc", "syscon"; - reg = <0xe0700000 0x1000>; - }; - - gpio0: gpio@e0600000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0xe0600000 0x1000>; - interrupts = <0 24 0x4>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - status = "disabled"; - }; - - gpio1: gpio@e0680000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0xe0680000 0x1000>; - interrupts = <0 25 0x4>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - status = "disabled"; - }; - - kbd@e0300000 { - compatible = "st,spear300-kbd"; - reg = <0xe0300000 0x1000>; - interrupts = <0 52 0x4>; - status = "disabled"; - }; - - i2c0: i2c@e0280000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0xe0280000 0x1000>; - interrupts = <0 41 0x4>; - status = "disabled"; - }; - - i2s@e0180000 { - compatible = "st,designware-i2s"; - reg = <0xe0180000 0x1000>; - interrupt-names = "play_irq", "record_irq"; - interrupts = <0 10 0x4 - 0 11 0x4 >; - status = "disabled"; - }; - - i2s@e0200000 { - compatible = "st,designware-i2s"; - reg = <0xe0200000 0x1000>; - interrupt-names = "play_irq", "record_irq"; - interrupts = <0 26 0x4 - 0 53 0x4>; - status = "disabled"; - }; - - spi0: spi@e0100000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0xe0100000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 31 0x4>; - status = "disabled"; - dmas = <&dwdma0 4 0 0>, - <&dwdma0 5 0 0>; - dma-names = "tx", "rx"; - }; - - rtc@e0580000 { - compatible = "st,spear600-rtc"; - reg = <0xe0580000 0x1000>; - interrupts = <0 36 0x4>; - status = "disabled"; - }; - - serial@e0000000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0xe0000000 0x1000>; - interrupts = <0 35 0x4>; - status = "disabled"; - }; - - adc@e0080000 { - compatible = "st,spear600-adc"; - reg = <0xe0080000 0x1000>; - interrupts = <0 12 0x4>; - status = "disabled"; - }; - - timer@e0380000 { - compatible = "st,spear-timer"; - reg = <0xe0380000 0x400>; - interrupts = <0 37 0x4>; - }; - - timer@ec800600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0xec800600 0x20>; - interrupts = <1 13 0x4>; - status = "disabled"; - }; - - wdt@ec800620 { - compatible = "arm,cortex-a9-twd-wdt"; - reg = <0xec800620 0x20>; - status = "disabled"; - }; - - thermal@e07008c4 { - compatible = "st,thermal-spear1340"; - reg = <0xe07008c4 0x4>; - thermal_flags = <0x7000>; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/spear300-evb.dts b/sys/gnu/dts/arm/spear300-evb.dts deleted file mode 100644 index 2beb30ca2cb..00000000000 --- a/sys/gnu/dts/arm/spear300-evb.dts +++ /dev/null @@ -1,249 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * DTS file for SPEAr300 Evaluation Baord - * - * Copyright 2012 Viresh Kumar - */ - -/dts-v1/; -/include/ "spear300.dtsi" - -/ { - model = "ST SPEAr300 Evaluation Board"; - compatible = "st,spear300-evb", "st,spear300"; - #address-cells = <1>; - #size-cells = <1>; - - memory { - reg = <0 0x40000000>; - }; - - ahb { - pinmux@99000000 { - st,pinmux-mode = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - i2c0 { - st,pins = "i2c0_grp"; - st,function = "i2c0"; - }; - ssp0 { - st,pins = "ssp0_grp"; - st,function = "ssp0"; - }; - mii0 { - st,pins = "mii0_grp"; - st,function = "mii0"; - }; - uart0 { - st,pins = "uart0_grp"; - st,function = "uart0"; - }; - clcd { - st,pins = "clcd_pfmode_grp"; - st,function = "clcd"; - }; - sdhci { - st,pins = "sdhci_4bit_grp"; - st,function = "sdhci"; - }; - gpio1 { - st,pins = "gpio1_4_to_7_grp", - "gpio1_0_to_3_grp"; - st,function = "gpio1"; - }; - }; - }; - - clcd@60000000 { - status = "okay"; - }; - - dma@fc400000 { - status = "okay"; - }; - - fsmc: flash@94000000 { - status = "okay"; - }; - - gmac: eth@e0800000 { - status = "okay"; - }; - - sdhci@70000000 { - cd-gpios = <&gpio1 0 0>; - status = "okay"; - }; - - smi: flash@fc000000 { - status = "okay"; - clock-rate=<50000000>; - - flash@f8000000 { - #address-cells = <1>; - #size-cells = <1>; - reg = <0xf8000000 0x800000>; - st,smi-fast-mode; - - partition@0 { - label = "xloader"; - reg = <0x0 0x10000>; - }; - partition@10000 { - label = "u-boot"; - reg = <0x10000 0x50000>; - }; - partition@60000 { - label = "environment"; - reg = <0x60000 0x10000>; - }; - partition@70000 { - label = "dtb"; - reg = <0x70000 0x10000>; - }; - partition@80000 { - label = "linux"; - reg = <0x80000 0x310000>; - }; - partition@390000 { - label = "rootfs"; - reg = <0x390000 0x0>; - }; - }; - }; - - spi0: spi@d0100000 { - status = "okay"; - }; - - ehci@e1800000 { - status = "okay"; - }; - - ohci@e1900000 { - status = "okay"; - }; - - ohci@e2100000 { - status = "okay"; - }; - - apb { - gpio0: gpio@fc980000 { - status = "okay"; - }; - - gpio1: gpio@a9000000 { - status = "okay"; - }; - - i2c0: i2c@d0180000 { - status = "okay"; - }; - - kbd@a0000000 { - linux,keymap = < 0x00000001 - 0x00010002 - 0x00020003 - 0x00030004 - 0x00040005 - 0x00050006 - 0x00060007 - 0x00070008 - 0x00080009 - 0x0100000a - 0x0101000c - 0x0102000d - 0x0103000e - 0x0104000f - 0x01050010 - 0x01060011 - 0x01070012 - 0x01080013 - 0x02000014 - 0x02010015 - 0x02020016 - 0x02030017 - 0x02040018 - 0x02050019 - 0x0206001a - 0x0207001b - 0x0208001c - 0x0300001d - 0x0301001e - 0x0302001f - 0x03030020 - 0x03040021 - 0x03050022 - 0x03060023 - 0x03070024 - 0x03080025 - 0x04000026 - 0x04010027 - 0x04020028 - 0x04030029 - 0x0404002a - 0x0405002b - 0x0406002c - 0x0407002d - 0x0408002e - 0x0500002f - 0x05010030 - 0x05020031 - 0x05030032 - 0x05040033 - 0x05050034 - 0x05060035 - 0x05070036 - 0x05080037 - 0x06000038 - 0x06010039 - 0x0602003a - 0x0603003b - 0x0604003c - 0x0605003d - 0x0606003e - 0x0607003f - 0x06080040 - 0x07000041 - 0x07010042 - 0x07020043 - 0x07030044 - 0x07040045 - 0x07050046 - 0x07060047 - 0x07070048 - 0x07080049 - 0x0800004a - 0x0801004b - 0x0802004c - 0x0803004d - 0x0804004e - 0x0805004f - 0x08060050 - 0x08070051 - 0x08080052 >; - autorepeat; - st,mode = <0>; - status = "okay"; - }; - - rtc@fc900000 { - status = "okay"; - }; - - serial@d0000000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <>; - }; - - wdt@fc880000 { - status = "okay"; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/spear300.dtsi b/sys/gnu/dts/arm/spear300.dtsi deleted file mode 100644 index b39bd5a2262..00000000000 --- a/sys/gnu/dts/arm/spear300.dtsi +++ /dev/null @@ -1,83 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * DTS file for SPEAr300 SoC - * - * Copyright 2012 Viresh Kumar - */ - -/include/ "spear3xx.dtsi" - -/ { - ahb { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0x60000000 0x60000000 0x50000000 - 0xd0000000 0xd0000000 0x30000000>; - - pinmux@99000000 { - compatible = "st,spear300-pinmux"; - reg = <0x99000000 0x1000>; - }; - - clcd@60000000 { - compatible = "arm,pl110", "arm,primecell"; - reg = <0x60000000 0x1000>; - interrupts = <30>; - status = "disabled"; - }; - - fsmc: flash@94000000 { - compatible = "st,spear600-fsmc-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x94000000 0x1000 /* FSMC Register */ - 0x80000000 0x0010 /* NAND Base DATA */ - 0x80020000 0x0010 /* NAND Base ADDR */ - 0x80010000 0x0010>; /* NAND Base CMD */ - reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd"; - status = "disabled"; - }; - - sdhci@70000000 { - compatible = "st,sdhci-spear"; - reg = <0x70000000 0x100>; - interrupts = <1>; - status = "disabled"; - }; - - shirq: interrupt-controller@0x50000000 { - compatible = "st,spear300-shirq"; - reg = <0x50000000 0x1000>; - interrupts = <28>; - #interrupt-cells = <1>; - interrupt-controller; - }; - - apb { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0xa0000000 0xa0000000 0x10000000 - 0xd0000000 0xd0000000 0x30000000>; - - gpio1: gpio@a9000000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0xa9000000 0x1000>; - interrupts = <8>; - interrupt-parent = <&shirq>; - status = "disabled"; - }; - - kbd@a0000000 { - compatible = "st,spear300-kbd"; - reg = <0xa0000000 0x1000>; - interrupts = <7>; - interrupt-parent = <&shirq>; - status = "disabled"; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/spear310-evb.dts b/sys/gnu/dts/arm/spear310-evb.dts deleted file mode 100644 index 1c41e4a4033..00000000000 --- a/sys/gnu/dts/arm/spear310-evb.dts +++ /dev/null @@ -1,202 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * DTS file for SPEAr310 Evaluation Baord - * - * Copyright 2012 Viresh Kumar - */ - -/dts-v1/; -/include/ "spear310.dtsi" - -/ { - model = "ST SPEAr310 Evaluation Board"; - compatible = "st,spear310-evb", "st,spear310"; - #address-cells = <1>; - #size-cells = <1>; - - memory { - reg = <0 0x40000000>; - }; - - ahb { - pinmux@b4000000 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - gpio0 { - st,pins = "gpio0_pin0_grp", - "gpio0_pin1_grp", - "gpio0_pin2_grp", - "gpio0_pin3_grp", - "gpio0_pin4_grp", - "gpio0_pin5_grp"; - st,function = "gpio0"; - }; - i2c0 { - st,pins = "i2c0_grp"; - st,function = "i2c0"; - }; - mii0 { - st,pins = "mii0_grp"; - st,function = "mii0"; - }; - ssp0 { - st,pins = "ssp0_grp"; - st,function = "ssp0"; - }; - uart0 { - st,pins = "uart0_grp"; - st,function = "uart0"; - }; - emi { - st,pins = "emi_cs_0_to_5_grp"; - st,function = "emi"; - }; - fsmc { - st,pins = "fsmc_grp"; - st,function = "fsmc"; - }; - uart1 { - st,pins = "uart1_grp"; - st,function = "uart1"; - }; - uart2 { - st,pins = "uart2_grp"; - st,function = "uart2"; - }; - uart3 { - st,pins = "uart3_grp"; - st,function = "uart3"; - }; - uart4 { - st,pins = "uart4_grp"; - st,function = "uart4"; - }; - uart5 { - st,pins = "uart5_grp"; - st,function = "uart5"; - }; - }; - }; - - dma@fc400000 { - status = "okay"; - }; - - fsmc: flash@44000000 { - status = "okay"; - }; - - gmac: eth@e0800000 { - status = "okay"; - }; - - smi: flash@fc000000 { - status = "okay"; - clock-rate=<50000000>; - - flash@f8000000 { - #address-cells = <1>; - #size-cells = <1>; - reg = <0xf8000000 0x800000>; - st,smi-fast-mode; - - partition@0 { - label = "xloader"; - reg = <0x0 0x10000>; - }; - partition@10000 { - label = "u-boot"; - reg = <0x10000 0x50000>; - }; - partition@60000 { - label = "environment"; - reg = <0x60000 0x10000>; - }; - partition@70000 { - label = "dtb"; - reg = <0x70000 0x10000>; - }; - partition@80000 { - label = "linux"; - reg = <0x80000 0x310000>; - }; - partition@390000 { - label = "rootfs"; - reg = <0x390000 0x0>; - }; - }; - }; - - spi0: spi@d0100000 { - status = "okay"; - }; - - ehci@e1800000 { - status = "okay"; - }; - - ohci@e1900000 { - status = "okay"; - }; - - ohci@e2100000 { - status = "okay"; - }; - - apb { - gpio0: gpio@fc980000 { - status = "okay"; - }; - - i2c0: i2c@d0180000 { - status = "okay"; - }; - - rtc@fc900000 { - status = "okay"; - }; - - serial@d0000000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <>; - }; - - serial@b2000000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <>; - }; - - serial@b2080000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <>; - }; - - serial@b2100000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <>; - }; - - serial@b2180000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <>; - }; - - serial@b2200000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <>; - }; - - wdt@fc880000 { - status = "okay"; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/spear310.dtsi b/sys/gnu/dts/arm/spear310.dtsi deleted file mode 100644 index 8ce751a1376..00000000000 --- a/sys/gnu/dts/arm/spear310.dtsi +++ /dev/null @@ -1,112 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * DTS file for SPEAr310 SoC - * - * Copyright 2012 Viresh Kumar - */ - -/include/ "spear3xx.dtsi" - -/ { - ahb { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0x40000000 0x40000000 0x10000000 - 0xb0000000 0xb0000000 0x10000000 - 0xd0000000 0xd0000000 0x30000000>; - - pinmux: pinmux@b4000000 { - compatible = "st,spear310-pinmux"; - reg = <0xb4000000 0x1000>; - #gpio-range-cells = <3>; - }; - - fsmc: flash@44000000 { - compatible = "st,spear600-fsmc-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x44000000 0x1000 /* FSMC Register */ - 0x40000000 0x0010 /* NAND Base DATA */ - 0x40020000 0x0010 /* NAND Base ADDR */ - 0x40010000 0x0010>; /* NAND Base CMD */ - reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd"; - status = "disabled"; - }; - - shirq: interrupt-controller@0xb4000000 { - compatible = "st,spear310-shirq"; - reg = <0xb4000000 0x1000>; - interrupts = <28 29 30 1>; - #interrupt-cells = <1>; - interrupt-controller; - }; - - apb { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0xb0000000 0xb0000000 0x10000000 - 0xd0000000 0xd0000000 0x30000000>; - - serial@b2000000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0xb2000000 0x1000>; - interrupts = <8>; - interrupt-parent = <&shirq>; - status = "disabled"; - }; - - serial@b2080000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0xb2080000 0x1000>; - interrupts = <9>; - interrupt-parent = <&shirq>; - status = "disabled"; - }; - - serial@b2100000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0xb2100000 0x1000>; - interrupts = <10>; - interrupt-parent = <&shirq>; - status = "disabled"; - }; - - serial@b2180000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0xb2180000 0x1000>; - interrupts = <11>; - interrupt-parent = <&shirq>; - status = "disabled"; - }; - - serial@b2200000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0xb2200000 0x1000>; - interrupts = <12>; - interrupt-parent = <&shirq>; - status = "disabled"; - }; - - gpiopinctrl: gpio@b4000000 { - compatible = "st,spear-plgpio"; - reg = <0xb4000000 0x1000>; - #interrupt-cells = <1>; - interrupt-controller; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinmux 0 0 102>; - status = "disabled"; - - st-plgpio,ngpio = <102>; - st-plgpio,enb-reg = <0x10>; - st-plgpio,wdata-reg = <0x20>; - st-plgpio,dir-reg = <0x30>; - st-plgpio,ie-reg = <0x50>; - st-plgpio,rdata-reg = <0x40>; - st-plgpio,mis-reg = <0x60>; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/spear320-evb.dts b/sys/gnu/dts/arm/spear320-evb.dts deleted file mode 100644 index c322407a0ad..00000000000 --- a/sys/gnu/dts/arm/spear320-evb.dts +++ /dev/null @@ -1,201 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * DTS file for SPEAr320 Evaluation Baord - * - * Copyright 2012 Viresh Kumar - */ - -/dts-v1/; -/include/ "spear320.dtsi" - -/ { - model = "ST SPEAr320 Evaluation Board"; - compatible = "st,spear320-evb", "st,spear320"; - #address-cells = <1>; - #size-cells = <1>; - - memory { - reg = <0 0x40000000>; - }; - - ahb { - pinmux@b3000000 { - st,pinmux-mode = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - i2c0 { - st,pins = "i2c0_grp"; - st,function = "i2c0"; - }; - mii0 { - st,pins = "mii0_grp"; - st,function = "mii0"; - }; - ssp0 { - st,pins = "ssp0_grp"; - st,function = "ssp0"; - }; - uart0 { - st,pins = "uart0_grp"; - st,function = "uart0"; - }; - sdhci { - st,pins = "sdhci_cd_51_grp"; - st,function = "sdhci"; - }; - i2s { - st,pins = "i2s_grp"; - st,function = "i2s"; - }; - uart1 { - st,pins = "uart1_grp"; - st,function = "uart1"; - }; - uart2 { - st,pins = "uart2_grp"; - st,function = "uart2"; - }; - can0 { - st,pins = "can0_grp"; - st,function = "can0"; - }; - can1 { - st,pins = "can1_grp"; - st,function = "can1"; - }; - mii2 { - st,pins = "mii2_grp"; - st,function = "mii2"; - }; - pwm0_1 { - st,pins = "pwm0_1_pin_37_38_grp"; - st,function = "pwm0_1"; - }; - }; - }; - - dma@fc400000 { - status = "okay"; - }; - - fsmc: flash@4c000000 { - status = "okay"; - }; - - gmac: eth@e0800000 { - status = "okay"; - }; - - sdhci@70000000 { - power-gpio = <&gpiopinctrl 61 1>; - status = "okay"; - }; - - smi: flash@fc000000 { - status = "okay"; - clock-rate=<50000000>; - - flash@f8000000 { - #address-cells = <1>; - #size-cells = <1>; - reg = <0xf8000000 0x800000>; - st,smi-fast-mode; - - partition@0 { - label = "xloader"; - reg = <0x0 0x10000>; - }; - partition@10000 { - label = "u-boot"; - reg = <0x10000 0x50000>; - }; - partition@60000 { - label = "environment"; - reg = <0x60000 0x10000>; - }; - partition@70000 { - label = "dtb"; - reg = <0x70000 0x10000>; - }; - partition@80000 { - label = "linux"; - reg = <0x80000 0x310000>; - }; - partition@390000 { - label = "rootfs"; - reg = <0x390000 0x0>; - }; - }; - }; - - spi0: spi@d0100000 { - status = "okay"; - }; - - spi1: spi@a5000000 { - status = "okay"; - }; - - spi2: spi@a6000000 { - status = "okay"; - }; - - ehci@e1800000 { - status = "okay"; - }; - - ohci@e1900000 { - status = "okay"; - }; - - ohci@e2100000 { - status = "okay"; - }; - - apb { - gpio0: gpio@fc980000 { - status = "okay"; - }; - - gpio@b3000000 { - status = "okay"; - }; - - i2c0: i2c@d0180000 { - status = "okay"; - }; - - i2c1: i2c@a7000000 { - status = "okay"; - }; - - rtc@fc900000 { - status = "okay"; - }; - - serial@d0000000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <>; - }; - - serial@a3000000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <>; - }; - - serial@a4000000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <>; - }; - - wdt@fc880000 { - status = "okay"; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/spear320-hmi.dts b/sys/gnu/dts/arm/spear320-hmi.dts deleted file mode 100644 index 367ba48aac3..00000000000 --- a/sys/gnu/dts/arm/spear320-hmi.dts +++ /dev/null @@ -1,299 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * DTS file for SPEAr320 Evaluation Baord - * - * Copyright 2012 Shiraz Hashim - */ - -/dts-v1/; -/include/ "spear320.dtsi" - -/ { - model = "ST SPEAr320 HMI Board"; - compatible = "st,spear320-hmi", "st,spear320"; - #address-cells = <1>; - #size-cells = <1>; - - memory { - reg = <0 0x40000000>; - }; - - ahb { - pinmux@b3000000 { - st,pinmux-mode = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - i2c0 { - st,pins = "i2c0_grp"; - st,function = "i2c0"; - }; - ssp0 { - st,pins = "ssp0_grp"; - st,function = "ssp0"; - }; - uart0 { - st,pins = "uart0_grp"; - st,function = "uart0"; - }; - clcd { - st,pins = "clcd_grp"; - st,function = "clcd"; - }; - fsmc { - st,pins = "fsmc_8bit_grp"; - st,function = "fsmc"; - }; - sdhci { - st,pins = "sdhci_cd_12_grp"; - st,function = "sdhci"; - }; - i2s { - st,pins = "i2s_grp"; - st,function = "i2s"; - }; - uart1 { - st,pins = "uart1_grp"; - st,function = "uart1"; - }; - uart2 { - st,pins = "uart2_grp"; - st,function = "uart2"; - }; - can0 { - st,pins = "can0_grp"; - st,function = "can0"; - }; - can1 { - st,pins = "can1_grp"; - st,function = "can1"; - }; - mii0_1 { - st,pins = "rmii0_1_grp"; - st,function = "mii0_1"; - }; - pwm0_1 { - st,pins = "pwm0_1_pin_37_38_grp"; - st,function = "pwm0_1"; - }; - pwm2 { - st,pins = "pwm2_pin_34_grp"; - st,function = "pwm2"; - }; - }; - }; - - clcd@90000000 { - status = "okay"; - }; - - dma@fc400000 { - status = "okay"; - }; - - ehci@e1800000 { - status = "okay"; - }; - - fsmc: flash@4c000000 { - status = "okay"; - - partition@0 { - label = "xloader"; - reg = <0x0 0x80000>; - }; - partition@80000 { - label = "u-boot"; - reg = <0x80000 0x140000>; - }; - partition@1C0000 { - label = "environment"; - reg = <0x1C0000 0x40000>; - }; - partition@200000 { - label = "dtb"; - reg = <0x200000 0x40000>; - }; - partition@240000 { - label = "linux"; - reg = <0x240000 0xC00000>; - }; - partition@E40000 { - label = "rootfs"; - reg = <0xE40000 0x0>; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - button@1 { - label = "user button 1"; - linux,code = <0x100>; - gpios = <&stmpegpio 3 0x4>; - debounce-interval = <20>; - wakeup-source; - }; - - button@2 { - label = "user button 2"; - linux,code = <0x200>; - gpios = <&stmpegpio 2 0x4>; - debounce-interval = <20>; - wakeup-source; - }; - }; - - ohci@e1900000 { - status = "okay"; - }; - - ohci@e2100000 { - status = "okay"; - }; - - pwm: pwm@a8000000 { - status = "okay"; - }; - - sdhci@70000000 { - power-gpio = <&gpiopinctrl 50 1>; - power_always_enb; - status = "okay"; - }; - - smi: flash@fc000000 { - status = "okay"; - clock-rate=<50000000>; - - flash@f8000000 { - #address-cells = <1>; - #size-cells = <1>; - reg = <0xf8000000 0x800000>; - st,smi-fast-mode; - - partition@0 { - label = "xloader"; - reg = <0x0 0x10000>; - }; - partition@10000 { - label = "u-boot"; - reg = <0x10000 0x50000>; - }; - partition@60000 { - label = "environment"; - reg = <0x60000 0x10000>; - }; - partition@70000 { - label = "dtb"; - reg = <0x70000 0x10000>; - }; - partition@80000 { - label = "linux"; - reg = <0x80000 0x310000>; - }; - partition@390000 { - label = "rootfs"; - reg = <0x390000 0x0>; - }; - }; - }; - - spi0: spi@d0100000 { - status = "okay"; - }; - - spi1: spi@a5000000 { - status = "okay"; - }; - - spi2: spi@a6000000 { - status = "okay"; - }; - - usbd@e1100000 { - status = "okay"; - }; - - apb { - gpio0: gpio@fc980000 { - status = "okay"; - }; - - gpio@b3000000 { - status = "okay"; - }; - - i2c0: i2c@d0180000 { - status = "okay"; - - stmpe811@41 { - compatible = "st,stmpe811"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x41>; - irq-over-gpio; - irq-gpios = <&gpiopinctrl 29 0x4>; - id = <0>; - blocks = <0x5>; - irq-trigger = <0x1>; - - stmpegpio: stmpe-gpio { - compatible = "stmpe,gpio"; - reg = <0>; - gpio-controller; - #gpio-cells = <2>; - gpio,norequest-mask = <0xF3>; - }; - - stmpe610-ts { - compatible = "stmpe,ts"; - reg = <0>; - ts,sample-time = <4>; - ts,mod-12b = <1>; - ts,ref-sel = <0>; - ts,adc-freq = <1>; - ts,ave-ctrl = <1>; - ts,touch-det-delay = <3>; - ts,settling = <4>; - ts,fraction-z = <7>; - ts,i-drive = <1>; - }; - }; - }; - - i2c1: i2c@a7000000 { - status = "okay"; - }; - - rtc@fc900000 { - status = "okay"; - }; - - serial@d0000000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <>; - }; - - serial@a3000000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <>; - }; - - serial@a4000000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <>; - }; - - wdt@fc880000 { - status = "okay"; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/spear320.dtsi b/sys/gnu/dts/arm/spear320.dtsi deleted file mode 100644 index 3bc1e93a0a5..00000000000 --- a/sys/gnu/dts/arm/spear320.dtsi +++ /dev/null @@ -1,141 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * DTS file for SPEAr320 SoC - * - * Copyright 2012 Viresh Kumar - */ - -/include/ "spear3xx.dtsi" - -/ { - ahb { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0x40000000 0x40000000 0x80000000 - 0xd0000000 0xd0000000 0x30000000>; - - pinmux: pinmux@b3000000 { - compatible = "st,spear320-pinmux"; - reg = <0xb3000000 0x1000>; - #gpio-range-cells = <3>; - }; - - clcd@90000000 { - compatible = "arm,pl110", "arm,primecell"; - reg = <0x90000000 0x1000>; - interrupts = <8>; - interrupt-parent = <&shirq>; - status = "disabled"; - }; - - fsmc: flash@4c000000 { - compatible = "st,spear600-fsmc-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x4c000000 0x1000 /* FSMC Register */ - 0x50000000 0x0010 /* NAND Base DATA */ - 0x50020000 0x0010 /* NAND Base ADDR */ - 0x50010000 0x0010>; /* NAND Base CMD */ - reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd"; - status = "disabled"; - }; - - sdhci@70000000 { - compatible = "st,sdhci-spear"; - reg = <0x70000000 0x100>; - interrupts = <10>; - interrupt-parent = <&shirq>; - status = "disabled"; - }; - - shirq: interrupt-controller@0xb3000000 { - compatible = "st,spear320-shirq"; - reg = <0xb3000000 0x1000>; - interrupts = <30 28 29 1>; - #interrupt-cells = <1>; - interrupt-controller; - }; - - spi1: spi@a5000000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0xa5000000 0x1000>; - interrupts = <15>; - interrupt-parent = <&shirq>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi2: spi@a6000000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0xa6000000 0x1000>; - interrupts = <16>; - interrupt-parent = <&shirq>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - pwm: pwm@a8000000 { - compatible ="st,spear-pwm"; - reg = <0xa8000000 0x1000>; - #pwm-cells = <2>; - status = "disabled"; - }; - - apb { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0xa0000000 0xa0000000 0x20000000 - 0xd0000000 0xd0000000 0x30000000>; - - i2c1: i2c@a7000000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0xa7000000 0x1000>; - interrupts = <21>; - interrupt-parent = <&shirq>; - status = "disabled"; - }; - - serial@a3000000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0xa3000000 0x1000>; - interrupts = <13>; - interrupt-parent = <&shirq>; - status = "disabled"; - }; - - serial@a4000000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0xa4000000 0x1000>; - interrupts = <14>; - interrupt-parent = <&shirq>; - status = "disabled"; - }; - - gpiopinctrl: gpio@b3000000 { - compatible = "st,spear-plgpio"; - reg = <0xb3000000 0x1000>; - #interrupt-cells = <1>; - interrupt-controller; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinmux 0 0 102>; - status = "disabled"; - - st-plgpio,ngpio = <102>; - st-plgpio,enb-reg = <0x24>; - st-plgpio,wdata-reg = <0x34>; - st-plgpio,dir-reg = <0x44>; - st-plgpio,ie-reg = <0x64>; - st-plgpio,rdata-reg = <0x54>; - st-plgpio,mis-reg = <0x84>; - st-plgpio,eit-reg = <0x94>; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/spear3xx.dtsi b/sys/gnu/dts/arm/spear3xx.dtsi deleted file mode 100644 index f266b7b0348..00000000000 --- a/sys/gnu/dts/arm/spear3xx.dtsi +++ /dev/null @@ -1,151 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * DTS file for all SPEAr3xx SoCs - * - * Copyright 2012 Viresh Kumar - */ - -/ { - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&vic>; - - cpus { - #address-cells = <0>; - #size-cells = <0>; - - cpu { - compatible = "arm,arm926ej-s"; - device_type = "cpu"; - }; - }; - - memory { - device_type = "memory"; - reg = <0 0x40000000>; - }; - - ahb { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0xd0000000 0xd0000000 0x30000000>; - - vic: interrupt-controller@f1100000 { - compatible = "arm,pl190-vic"; - interrupt-controller; - reg = <0xf1100000 0x1000>; - #interrupt-cells = <1>; - }; - - dma@fc400000 { - compatible = "arm,pl080", "arm,primecell"; - reg = <0xfc400000 0x1000>; - interrupt-parent = <&vic>; - interrupts = <8>; - status = "disabled"; - }; - - gmac: eth@e0800000 { - compatible = "st,spear600-gmac"; - reg = <0xe0800000 0x8000>; - interrupts = <23 22>; - interrupt-names = "macirq", "eth_wake_irq"; - phy-mode = "mii"; - status = "disabled"; - }; - - smi: flash@fc000000 { - compatible = "st,spear600-smi"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0xfc000000 0x1000>; - interrupts = <9>; - status = "disabled"; - }; - - spi0: spi@d0100000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0xd0100000 0x1000>; - interrupts = <20>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - ehci@e1800000 { - compatible = "st,spear600-ehci", "usb-ehci"; - reg = <0xe1800000 0x1000>; - interrupts = <26>; - status = "disabled"; - }; - - ohci@e1900000 { - compatible = "st,spear600-ohci", "usb-ohci"; - reg = <0xe1900000 0x1000>; - interrupts = <25>; - status = "disabled"; - }; - - ohci@e2100000 { - compatible = "st,spear600-ohci", "usb-ohci"; - reg = <0xe2100000 0x1000>; - interrupts = <27>; - status = "disabled"; - }; - - apb { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0xd0000000 0xd0000000 0x30000000>; - - gpio0: gpio@fc980000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0xfc980000 0x1000>; - interrupts = <11>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - status = "disabled"; - }; - - i2c0: i2c@d0180000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0xd0180000 0x1000>; - interrupts = <21>; - status = "disabled"; - }; - - rtc@fc900000 { - compatible = "st,spear600-rtc"; - reg = <0xfc900000 0x1000>; - interrupts = <10>; - status = "disabled"; - }; - - serial@d0000000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0xd0000000 0x1000>; - interrupts = <19>; - status = "disabled"; - }; - - wdt@fc880000 { - compatible = "arm,sp805", "arm,primecell"; - reg = <0xfc880000 0x1000>; - interrupts = <12>; - status = "disabled"; - }; - - timer@f0000000 { - compatible = "st,spear-timer"; - reg = <0xf0000000 0x400>; - interrupts = <2>; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/spear600-evb.dts b/sys/gnu/dts/arm/spear600-evb.dts deleted file mode 100644 index a25b86d149a..00000000000 --- a/sys/gnu/dts/arm/spear600-evb.dts +++ /dev/null @@ -1,106 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2012 Stefan Roese - */ - -/dts-v1/; -/include/ "spear600.dtsi" - -/ { - model = "ST SPEAr600 Evaluation Board"; - compatible = "st,spear600-evb", "st,spear600"; - #address-cells = <1>; - #size-cells = <1>; - - memory { - device_type = "memory"; - reg = <0 0x10000000>; - }; -}; - -&clcd { - status = "okay"; -}; - -&dmac { - status = "okay"; -}; - -&ehci_usb0 { - status = "okay"; -}; - -&ehci_usb1 { - status = "okay"; -}; - -&gmac { - phy-mode = "gmii"; - status = "okay"; -}; - -&ohci_usb0 { - status = "okay"; -}; - -&ohci_usb1 { - status = "okay"; -}; - -&smi { - status = "okay"; - clock-rate = <50000000>; - - flash@f8000000 { - reg = <0xf8000000 0x800000>; - st,smi-fast-mode; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "xloader"; - reg = <0x0 0x10000>; - }; - partition@10000 { - label = "u-boot"; - reg = <0x10000 0x50000>; - }; - partition@60000 { - label = "environment"; - reg = <0x60000 0x10000>; - }; - partition@70000 { - label = "dtb"; - reg = <0x70000 0x10000>; - }; - partition@80000 { - label = "linux"; - reg = <0x80000 0x310000>; - }; - partition@390000 { - label = "rootfs"; - reg = <0x390000 0x0>; - }; - }; - }; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&rtc { - status = "okay"; -}; - -&i2c { - clock-frequency = <400000>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/spear600.dtsi b/sys/gnu/dts/arm/spear600.dtsi deleted file mode 100644 index fd41243a0b2..00000000000 --- a/sys/gnu/dts/arm/spear600.dtsi +++ /dev/null @@ -1,212 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2012 Stefan Roese - */ - -/ { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,spear600"; - - cpus { - #address-cells = <0>; - #size-cells = <0>; - - cpu { - compatible = "arm,arm926ej-s"; - device_type = "cpu"; - }; - }; - - memory { - device_type = "memory"; - reg = <0 0x40000000>; - }; - - ahb { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0xd0000000 0xd0000000 0x30000000>; - - vic0: interrupt-controller@f1100000 { - compatible = "arm,pl190-vic"; - interrupt-controller; - reg = <0xf1100000 0x1000>; - #interrupt-cells = <1>; - }; - - vic1: interrupt-controller@f1000000 { - compatible = "arm,pl190-vic"; - interrupt-controller; - reg = <0xf1000000 0x1000>; - #interrupt-cells = <1>; - }; - - clcd: clcd@fc200000 { - compatible = "arm,pl110", "arm,primecell"; - reg = <0xfc200000 0x1000>; - interrupt-parent = <&vic1>; - interrupts = <12>; - status = "disabled"; - }; - - dmac: dma@fc400000 { - compatible = "arm,pl080", "arm,primecell"; - reg = <0xfc400000 0x1000>; - interrupt-parent = <&vic1>; - interrupts = <10>; - status = "disabled"; - }; - - gmac: ethernet@e0800000 { - compatible = "st,spear600-gmac"; - reg = <0xe0800000 0x8000>; - interrupt-parent = <&vic1>; - interrupts = <24 23>; - interrupt-names = "macirq", "eth_wake_irq"; - phy-mode = "gmii"; - status = "disabled"; - }; - - fsmc: flash@d1800000 { - compatible = "st,spear600-fsmc-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0xd1800000 0x1000 /* FSMC Register */ - 0xd2000000 0x0010 /* NAND Base DATA */ - 0xd2020000 0x0010 /* NAND Base ADDR */ - 0xd2010000 0x0010>; /* NAND Base CMD */ - reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd"; - status = "disabled"; - }; - - smi: flash@fc000000 { - compatible = "st,spear600-smi"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0xfc000000 0x1000>; - interrupt-parent = <&vic1>; - interrupts = <12>; - status = "disabled"; - }; - - ehci_usb0: ehci@e1800000 { - compatible = "st,spear600-ehci", "usb-ehci"; - reg = <0xe1800000 0x1000>; - interrupt-parent = <&vic1>; - interrupts = <27>; - status = "disabled"; - }; - - ehci_usb1: ehci@e2000000 { - compatible = "st,spear600-ehci", "usb-ehci"; - reg = <0xe2000000 0x1000>; - interrupt-parent = <&vic1>; - interrupts = <29>; - status = "disabled"; - }; - - ohci_usb0: ohci@e1900000 { - compatible = "st,spear600-ohci", "usb-ohci"; - reg = <0xe1900000 0x1000>; - interrupt-parent = <&vic1>; - interrupts = <26>; - status = "disabled"; - }; - - ohci_usb1: ohci@e2100000 { - compatible = "st,spear600-ohci", "usb-ohci"; - reg = <0xe2100000 0x1000>; - interrupt-parent = <&vic1>; - interrupts = <28>; - status = "disabled"; - }; - - apb { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0xd0000000 0xd0000000 0x30000000>; - - uart0: serial@d0000000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0xd0000000 0x1000>; - interrupt-parent = <&vic0>; - interrupts = <24>; - status = "disabled"; - }; - - uart1: serial@d0080000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0xd0080000 0x1000>; - interrupt-parent = <&vic0>; - interrupts = <25>; - status = "disabled"; - }; - - /* local/cpu GPIO */ - gpio0: gpio@f0100000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0xf0100000 0x1000>; - interrupt-parent = <&vic0>; - interrupts = <18>; - }; - - /* basic GPIO */ - gpio1: gpio@fc980000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0xfc980000 0x1000>; - interrupt-parent = <&vic1>; - interrupts = <19>; - }; - - /* appl GPIO */ - gpio2: gpio@d8100000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0xd8100000 0x1000>; - interrupt-parent = <&vic1>; - interrupts = <4>; - }; - - i2c: i2c@d0200000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0xd0200000 0x1000>; - interrupt-parent = <&vic0>; - interrupts = <28>; - status = "disabled"; - }; - - rtc: rtc@fc900000 { - compatible = "st,spear600-rtc"; - reg = <0xfc900000 0x1000>; - interrupt-parent = <&vic0>; - interrupts = <10>; - status = "disabled"; - }; - - timer@f0000000 { - compatible = "st,spear-timer"; - reg = <0xf0000000 0x400>; - interrupt-parent = <&vic0>; - interrupts = <16>; - }; - - adc: adc@d820b000 { - compatible = "st,spear600-adc"; - reg = <0xd820b000 0x1000>; - interrupt-parent = <&vic1>; - interrupts = <6>; - status = "disabled"; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/st-pincfg.h b/sys/gnu/dts/arm/st-pincfg.h deleted file mode 100644 index d8055120229..00000000000 --- a/sys/gnu/dts/arm/st-pincfg.h +++ /dev/null @@ -1,72 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _ST_PINCFG_H_ -#define _ST_PINCFG_H_ - -/* Alternate functions */ -#define ALT1 1 -#define ALT2 2 -#define ALT3 3 -#define ALT4 4 -#define ALT5 5 -#define ALT6 6 -#define ALT7 7 - -/* Output enable */ -#define OE (1 << 27) -/* Pull Up */ -#define PU (1 << 26) -/* Open Drain */ -#define OD (1 << 25) -#define RT (1 << 23) -#define INVERTCLK (1 << 22) -#define CLKNOTDATA (1 << 21) -#define DOUBLE_EDGE (1 << 20) -#define CLK_A (0 << 18) -#define CLK_B (1 << 18) -#define CLK_C (2 << 18) -#define CLK_D (3 << 18) - -/* User-frendly defines for Pin Direction */ - /* oe = 0, pu = 0, od = 0 */ -#define IN (0) - /* oe = 0, pu = 1, od = 0 */ -#define IN_PU (PU) - /* oe = 1, pu = 0, od = 0 */ -#define OUT (OE) - /* oe = 1, pu = 0, od = 1 */ -#define BIDIR (OE | OD) - /* oe = 1, pu = 1, od = 1 */ -#define BIDIR_PU (OE | PU | OD) - -/* RETIME_TYPE */ -/* - * B Mode - * Bypass retime with optional delay parameter - */ -#define BYPASS (0) -/* - * R0, R1, R0D, R1D modes - * single-edge data non inverted clock, retime data with clk - */ -#define SE_NICLK_IO (RT) -/* - * RIV0, RIV1, RIV0D, RIV1D modes - * single-edge data inverted clock, retime data with clk - */ -#define SE_ICLK_IO (RT | INVERTCLK) -/* - * R0E, R1E, R0ED, R1ED modes - * double-edge data, retime data with clk - */ -#define DE_IO (RT | DOUBLE_EDGE) -/* - * CIV0, CIV1 modes with inverted clock - * Retiming the clk pins will park clock & reduce the noise within the core. - */ -#define ICLK (RT | CLKNOTDATA | INVERTCLK) -/* - * CLK0, CLK1 modes with non-inverted clock - * Retiming the clk pins will park clock & reduce the noise within the core. - */ -#define NICLK (RT | CLKNOTDATA) -#endif /* _ST_PINCFG_H_ */ diff --git a/sys/gnu/dts/arm/ste-ab8500.dtsi b/sys/gnu/dts/arm/ste-ab8500.dtsi deleted file mode 100644 index 14d4d8617d7..00000000000 --- a/sys/gnu/dts/arm/ste-ab8500.dtsi +++ /dev/null @@ -1,328 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2012 Linaro Ltd - */ - -#include - -/ { - /* Essential housekeeping hardware monitors */ - iio-hwmon { - compatible = "iio-hwmon"; - io-channels = <&gpadc 0x02>, /* Battery temperature */ - <&gpadc 0x03>, /* Main charger voltage */ - <&gpadc 0x08>, /* Main battery voltage */ - <&gpadc 0x09>, /* VBUS */ - <&gpadc 0x0a>, /* Main charger current */ - <&gpadc 0x0b>, /* USB charger current */ - <&gpadc 0x0c>, /* Backup battery voltage */ - <&gpadc 0x0d>, /* Die temperature */ - <&gpadc 0x12>; /* Crystal temperature */ - }; - - soc { - prcmu@80157000 { - ab8500 { - compatible = "stericsson,ab8500"; - interrupt-parent = <&intc>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <2>; - - ab8500_clock: clock-controller { - compatible = "stericsson,ab8500-clk"; - #clock-cells = <1>; - }; - - ab8500_gpio: ab8500-gpio { - compatible = "stericsson,ab8500-gpio"; - gpio-controller; - #gpio-cells = <2>; - }; - - ab8500-rtc { - compatible = "stericsson,ab8500-rtc"; - interrupts = <17 IRQ_TYPE_LEVEL_HIGH - 18 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "60S", "ALARM"; - }; - - gpadc: ab8500-gpadc { - compatible = "stericsson,ab8500-gpadc"; - interrupts = <32 IRQ_TYPE_LEVEL_HIGH - 39 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "HW_CONV_END", "SW_CONV_END"; - vddadc-supply = <&ab8500_ldo_tvout_reg>; - #address-cells = <1>; - #size-cells = <0>; - #io-channel-cells = <1>; - - /* GPADC channels */ - bat_ctrl: channel@01 { - reg = <0x01>; - }; - btemp_ball: channel@02 { - reg = <0x02>; - }; - main_charger_v: channel@03 { - reg = <0x03>; - }; - acc_detect1: channel@04 { - reg = <0x04>; - }; - acc_detect2: channel@05 { - reg = <0x05>; - }; - adc_aux1: channel@06 { - reg = <0x06>; - }; - adc_aux2: channel@07 { - reg = <0x07>; - }; - main_batt_v: channel@08 { - reg = <0x08>; - }; - vbus_v: channel@09 { - reg = <0x09>; - }; - main_charger_c: channel@0a { - reg = <0x0a>; - }; - usb_charger_c: channel@0b { - reg = <0x0b>; - }; - bk_bat_v: channel@0c { - reg = <0x0c>; - }; - die_temp: channel@0d { - reg = <0x0d>; - }; - usb_id: channel@0e { - reg = <0x0e>; - }; - xtal_temp: channel@12 { - reg = <0x12>; - }; - vbat_true_meas: channel@13 { - reg = <0x13>; - }; - bat_ctrl_and_ibat: channel@1c { - reg = <0x1c>; - }; - vbat_meas_and_ibat: channel@1d { - reg = <0x1d>; - }; - vbat_true_meas_and_ibat: channel@1e { - reg = <0x1e>; - }; - bat_temp_and_ibat: channel@1f { - reg = <0x1f>; - }; - }; - - ab8500_temp { - compatible = "stericsson,abx500-temp"; - io-channels = <&gpadc 0x06>, - <&gpadc 0x07>; - io-channel-name = "aux1", "aux2"; - }; - - ab8500_battery: ab8500_battery { - stericsson,battery-type = "LIPO"; - thermistor-on-batctrl; - }; - - ab8500_fg { - compatible = "stericsson,ab8500-fg"; - battery = <&ab8500_battery>; - io-channels = <&gpadc 0x08>; - io-channel-name = "main_bat_v"; - }; - - ab8500_btemp { - compatible = "stericsson,ab8500-btemp"; - battery = <&ab8500_battery>; - io-channels = <&gpadc 0x02>, - <&gpadc 0x01>; - io-channel-name = "btemp_ball", - "bat_ctrl"; - }; - - ab8500_charger { - compatible = "stericsson,ab8500-charger"; - battery = <&ab8500_battery>; - vddadc-supply = <&ab8500_ldo_tvout_reg>; - io-channels = <&gpadc 0x03>, - <&gpadc 0x0a>, - <&gpadc 0x09>, - <&gpadc 0x0b>; - io-channel-name = "main_charger_v", - "main_charger_c", - "vbus_v", - "usb_charger_c"; - }; - - ab8500_chargalg { - compatible = "stericsson,ab8500-chargalg"; - battery = <&ab8500_battery>; - }; - - ab8500_usb { - compatible = "stericsson,ab8500-usb"; - interrupts = < 90 IRQ_TYPE_LEVEL_HIGH - 96 IRQ_TYPE_LEVEL_HIGH - 14 IRQ_TYPE_LEVEL_HIGH - 15 IRQ_TYPE_LEVEL_HIGH - 79 IRQ_TYPE_LEVEL_HIGH - 74 IRQ_TYPE_LEVEL_HIGH - 75 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "ID_WAKEUP_R", - "ID_WAKEUP_F", - "VBUS_DET_F", - "VBUS_DET_R", - "USB_LINK_STATUS", - "USB_ADP_PROBE_PLUG", - "USB_ADP_PROBE_UNPLUG"; - vddulpivio18-supply = <&ab8500_ldo_intcore_reg>; - v-ape-supply = <&db8500_vape_reg>; - musb_1v8-supply = <&db8500_vsmps2_reg>; - clocks = <&prcmu_clk PRCMU_SYSCLK>; - clock-names = "sysclk"; - }; - - ab8500-ponkey { - compatible = "stericsson,ab8500-poweron-key"; - interrupts = <6 IRQ_TYPE_LEVEL_HIGH - 7 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "ONKEY_DBF", "ONKEY_DBR"; - }; - - ab8500-sysctrl { - compatible = "stericsson,ab8500-sysctrl"; - }; - - ab8500-pwm { - compatible = "stericsson,ab8500-pwm"; - clocks = <&ab8500_clock AB8500_SYSCLK_INT>; - clock-names = "intclk"; - }; - - ab8500-debugfs { - compatible = "stericsson,ab8500-debug"; - }; - - codec: ab8500-codec { - compatible = "stericsson,ab8500-codec"; - - V-AUD-supply = <&ab8500_ldo_audio_reg>; - V-AMIC1-supply = <&ab8500_ldo_anamic1_reg>; - V-AMIC2-supply = <&ab8500_ldo_anamic2_reg>; - V-DMIC-supply = <&ab8500_ldo_dmic_reg>; - - clocks = <&ab8500_clock AB8500_SYSCLK_AUDIO>; - clock-names = "audioclk"; - - stericsson,earpeice-cmv = <950>; /* Units in mV. */ - }; - - ext_regulators: ab8500-ext-regulators { - compatible = "stericsson,ab8500-ext-regulator"; - - ab8500_ext1_reg: ab8500_ext1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - ab8500_ext2_reg: ab8500_ext2 { - regulator-min-microvolt = <1360000>; - regulator-max-microvolt = <1360000>; - regulator-boot-on; - regulator-always-on; - }; - - ab8500_ext3_reg: ab8500_ext3 { - regulator-min-microvolt = <3400000>; - regulator-max-microvolt = <3400000>; - regulator-boot-on; - }; - }; - - ab8500-regulators { - compatible = "stericsson,ab8500-regulator"; - vin-supply = <&ab8500_ext3_reg>; - - // supplies to the display/camera - ab8500_ldo_aux1_reg: ab8500_ldo_aux1 { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2900000>; - regulator-boot-on; - /* BUG: If turned off MMC will be affected. */ - regulator-always-on; - }; - - // supplies to the on-board eMMC - ab8500_ldo_aux2_reg: ab8500_ldo_aux2 { - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <3300000>; - }; - - // supply for VAUX3; SDcard slots - ab8500_ldo_aux3_reg: ab8500_ldo_aux3 { - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <3300000>; - }; - - // supply for v-intcore12; VINTCORE12 LDO - ab8500_ldo_intcore_reg: ab8500_ldo_intcore { - }; - - // supply for tvout; gpadc; TVOUT LDO - ab8500_ldo_tvout_reg: ab8500_ldo_tvout { - }; - - // supply for ab8500-vaudio; VAUDIO LDO - ab8500_ldo_audio_reg: ab8500_ldo_audio { - }; - - // supply for v-anamic1 VAMIC1 LDO - ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 { - }; - - // supply for v-amic2; VAMIC2 LDO; reuse constants for AMIC1 - ab8500_ldo_anamic2_reg: ab8500_ldo_anamic2 { - }; - - // supply for v-dmic; VDMIC LDO - ab8500_ldo_dmic_reg: ab8500_ldo_dmic { - }; - - // supply for U8500 CSI/DSI; VANA LDO - ab8500_ldo_ana_reg: ab8500_ldo_ana { - }; - }; - }; - }; - - sound { - stericsson,audio-codec = <&codec>; - clocks = <&prcmu_clk PRCMU_SYSCLK>, <&ab8500_clock AB8500_SYSCLK_ULP>, <&ab8500_clock AB8500_SYSCLK_INT>; - clock-names = "sysclk", "ulpclk", "intclk"; - }; - - mcde@a0350000 { - vana-supply = <&ab8500_ldo_ana_reg>; - - dsi@a0351000 { - vana-supply = <&ab8500_ldo_ana_reg>; - }; - dsi@a0352000 { - vana-supply = <&ab8500_ldo_ana_reg>; - }; - dsi@a0353000 { - vana-supply = <&ab8500_ldo_ana_reg>; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/ste-ab8505.dtsi b/sys/gnu/dts/arm/ste-ab8505.dtsi deleted file mode 100644 index c72aa250bf6..00000000000 --- a/sys/gnu/dts/arm/ste-ab8505.dtsi +++ /dev/null @@ -1,275 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2012 Linaro Ltd - */ - -#include - -/ { - /* Essential housekeeping hardware monitors */ - iio-hwmon { - compatible = "iio-hwmon"; - io-channels = <&gpadc 0x02>, /* Battery temperature */ - <&gpadc 0x08>, /* Main battery voltage */ - <&gpadc 0x09>, /* VBUS */ - <&gpadc 0x0b>, /* Charger current */ - <&gpadc 0x0c>; /* Backup battery voltage */ - }; - - soc { - prcmu@80157000 { - ab8505 { - compatible = "stericsson,ab8505"; - interrupt-parent = <&intc>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <2>; - - ab8500_clock: clock-controller { - compatible = "stericsson,ab8500-clk"; - #clock-cells = <1>; - }; - - ab8505_gpio: ab8505-gpio { - compatible = "stericsson,ab8505-gpio"; - gpio-controller; - #gpio-cells = <2>; - }; - - ab8500-rtc { - compatible = "stericsson,ab8500-rtc"; - interrupts = <17 IRQ_TYPE_LEVEL_HIGH - 18 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "60S", "ALARM"; - }; - - gpadc: ab8500-gpadc { - compatible = "stericsson,ab8500-gpadc"; - interrupts = <32 IRQ_TYPE_LEVEL_HIGH - 39 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "HW_CONV_END", "SW_CONV_END"; - vddadc-supply = <&ab8500_ldo_adc_reg>; - #address-cells = <1>; - #size-cells = <0>; - #io-channel-cells = <1>; - - /* GPADC channels */ - bat_ctrl: channel@01 { - reg = <0x01>; - }; - btemp_ball: channel@02 { - reg = <0x02>; - }; - acc_detect1: channel@04 { - reg = <0x04>; - }; - acc_detect2: channel@05 { - reg = <0x05>; - }; - adc_aux1: channel@06 { - reg = <0x06>; - }; - adc_aux2: channel@07 { - reg = <0x07>; - }; - main_batt_v: channel@08 { - reg = <0x08>; - }; - vbus_v: channel@09 { - reg = <0x09>; - }; - charger_c: channel@0b { - reg = <0x0b>; - }; - bk_bat_v: channel@0c { - reg = <0x0c>; - }; - usb_id: channel@0e { - reg = <0x0e>; - }; - }; - - ab8500_battery: ab8500_battery { - status = "disabled"; - thermistor-on-batctrl; - }; - - ab8500_fg { - status = "disabled"; - compatible = "stericsson,ab8500-fg"; - battery = <&ab8500_battery>; - io-channels = <&gpadc 0x08>; - io-channel-name = "main_bat_v"; - }; - - ab8500_btemp { - status = "disabled"; - compatible = "stericsson,ab8500-btemp"; - battery = <&ab8500_battery>; - io-channels = <&gpadc 0x02>, - <&gpadc 0x01>; - io-channel-name = "btemp_ball", - "bat_ctrl"; - }; - - ab8500_charger { - status = "disabled"; - compatible = "stericsson,ab8500-charger"; - battery = <&ab8500_battery>; - vddadc-supply = <&ab8500_ldo_adc_reg>; - io-channels = <&gpadc 0x09>, - <&gpadc 0x0b>; - io-channel-name = "vbus_v", - "usb_charger_c"; - }; - - ab8500_chargalg { - status = "disabled"; - compatible = "stericsson,ab8500-chargalg"; - battery = <&ab8500_battery>; - }; - - ab8500_usb: ab8500_usb { - compatible = "stericsson,ab8500-usb"; - interrupts = < 90 IRQ_TYPE_LEVEL_HIGH - 96 IRQ_TYPE_LEVEL_HIGH - 14 IRQ_TYPE_LEVEL_HIGH - 15 IRQ_TYPE_LEVEL_HIGH - 79 IRQ_TYPE_LEVEL_HIGH - 74 IRQ_TYPE_LEVEL_HIGH - 75 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "ID_WAKEUP_R", - "ID_WAKEUP_F", - "VBUS_DET_F", - "VBUS_DET_R", - "USB_LINK_STATUS", - "USB_ADP_PROBE_PLUG", - "USB_ADP_PROBE_UNPLUG"; - vddulpivio18-supply = <&ab8500_ldo_intcore_reg>; - v-ape-supply = <&db8500_vape_reg>; - musb_1v8-supply = <&db8500_vsmps2_reg>; - clocks = <&prcmu_clk PRCMU_SYSCLK>; - clock-names = "sysclk"; - }; - - ab8500-ponkey { - compatible = "stericsson,ab8500-poweron-key"; - interrupts = <6 IRQ_TYPE_LEVEL_HIGH - 7 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "ONKEY_DBF", "ONKEY_DBR"; - }; - - ab8500-sysctrl { - compatible = "stericsson,ab8500-sysctrl"; - }; - - ab8500-pwm { - compatible = "stericsson,ab8500-pwm"; - clocks = <&ab8500_clock AB8500_SYSCLK_INT>; - clock-names = "intclk"; - }; - - ab8500-debugfs { - compatible = "stericsson,ab8500-debug"; - }; - - codec: ab8500-codec { - compatible = "stericsson,ab8500-codec"; - - V-AUD-supply = <&ab8500_ldo_audio_reg>; - V-AMIC1-supply = <&ab8500_ldo_anamic1_reg>; - V-AMIC2-supply = <&ab8500_ldo_anamic2_reg>; - - clocks = <&ab8500_clock AB8500_SYSCLK_AUDIO>; - clock-names = "audioclk"; - - stericsson,earpeice-cmv = <950>; /* Units in mV. */ - }; - - ab8505-regulators { - compatible = "stericsson,ab8505-regulator"; - - ab8500_ldo_aux1_reg: ab8500_ldo_aux1 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <3300000>; - }; - - ab8500_ldo_aux2_reg: ab8500_ldo_aux2 { - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <3300000>; - }; - - ab8500_ldo_aux3_reg: ab8500_ldo_aux3 { - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <3300000>; - }; - - ab8500_ldo_aux4_reg: ab8500_ldo_aux4 { - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <3300000>; - }; - - ab8500_ldo_aux5_reg: ab8500_ldo_aux5 { - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <2790000>; - }; - - ab8500_ldo_aux6_reg: ab8500_ldo_aux6 { - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <2790000>; - }; - - // supply for v-intcore12; VINTCORE12 LDO - ab8500_ldo_intcore_reg: ab8500_ldo_intcore { - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1350000>; - }; - - // supply for gpadc; ADC LDO - ab8500_ldo_adc_reg: ab8500_ldo_adc { - }; - - // supply for ab8500-vaudio; VAUDIO LDO - ab8500_ldo_audio_reg: ab8500_ldo_audio { - }; - - // supply for v-anamic1 VAMIC1 LDO - ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 { - }; - - // supply for v-amic2; VAMIC2 LDO; reuse constants for AMIC1 - ab8500_ldo_anamic2_reg: ab8500_ldo_anamic2 { - }; - - // supply for v-aux8; VAUX8 LDO - ab8500_ldo_aux8_reg: ab8500_ldo_aux8 { - }; - - // supply for U8500 CSI/DSI; VANA LDO - ab8500_ldo_ana_reg: ab8500_ldo_ana { - }; - }; - }; - }; - - sound { - stericsson,audio-codec = <&codec>; - clocks = <&prcmu_clk PRCMU_SYSCLK>, <&ab8500_clock AB8500_SYSCLK_ULP>, <&ab8500_clock AB8500_SYSCLK_INT>; - clock-names = "sysclk", "ulpclk", "intclk"; - }; - - mcde@a0350000 { - vana-supply = <&ab8500_ldo_ana_reg>; - - dsi@a0351000 { - vana-supply = <&ab8500_ldo_ana_reg>; - }; - dsi@a0352000 { - vana-supply = <&ab8500_ldo_ana_reg>; - }; - dsi@a0353000 { - vana-supply = <&ab8500_ldo_ana_reg>; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/ste-ccu8540-pinctrl.dtsi b/sys/gnu/dts/arm/ste-ccu8540-pinctrl.dtsi deleted file mode 100644 index 52dba2e39c7..00000000000 --- a/sys/gnu/dts/arm/ste-ccu8540-pinctrl.dtsi +++ /dev/null @@ -1,196 +0,0 @@ -/* - * Copyright 2012 ST-Ericsson - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#include "ste-nomadik-pinctrl.dtsi" - -/ { - soc { - pinctrl { - uart0 { - uart0_default_mux: uart0_mux { - default_mux { - function = "u0"; - groups = "u0_a_1"; - }; - }; - - uart0_default_mode: uart0_default { - default_cfg1 { - pins = "GPIO0", "GPIO2"; - ste,config = <&in_pu>; - }; - - default_cfg2 { - pins = "GPIO1", "GPIO3"; - ste,config = <&out_hi>; - }; - }; - - uart0_sleep_mode: uart0_sleep { - sleep_cfg1 { - pins = "GPIO0", "GPIO2"; - ste,config = <&slpm_in_pu>; - }; - - sleep_cfg2 { - pins = "GPIO1", "GPIO3"; - ste,config = <&slpm_out_hi>; - }; - }; - }; - - uart2 { - uart2_default_mode: uart2_default { - default_mux { - function = "u2"; - groups = "u2txrx_a_1"; - }; - - default_cfg1 { - pins = "GPIO120"; - ste,config = <&in_pu>; - }; - - default_cfg2 { - pins = "GPIO121"; - ste,config = <&out_hi>; - }; - }; - - uart2_sleep_mode: uart2_sleep { - sleep_cfg1 { - pins = "GPIO120"; - ste,config = <&slpm_in_pu>; - }; - - sleep_cfg2 { - pins = "GPIO121"; - ste,config = <&slpm_out_hi>; - }; - }; - }; - - i2c0 { - i2c0_default_mux: i2c_mux { - default_mux { - function = "i2c0"; - groups = "i2c0_a_1"; - }; - }; - - i2c0_default_mode: i2c_default { - default_cfg1 { - pins = "GPIO147", "GPIO148"; - ste,config = <&in_pu>; - }; - }; - - i2c0_sleep_mode: i2c_sleep { - sleep_cfg1 { - pins = "GPIO147", "GPIO148"; - ste,config = <&slpm_in_pu>; - }; - }; - }; - - i2c1 { - i2c1_default_mux: i2c_mux { - default_mux { - function = "i2c1"; - groups = "i2c1_b_2"; - }; - }; - - i2c1_default_mode: i2c_default { - default_cfg1 { - pins = "GPIO16", "GPIO17"; - ste,config = <&in_pu>; - }; - }; - - i2c1_sleep_mode: i2c_sleep { - sleep_cfg1 { - pins = "GPIO16", "GPIO17"; - ste,config = <&slpm_in_pu>; - }; - }; - }; - - i2c2 { - i2c2_default_mux: i2c_mux { - default_mux { - function = "i2c2"; - groups = "i2c2_b_2"; - }; - }; - - i2c2_default_mode: i2c_default { - default_cfg1 { - pins = "GPIO10", "GPIO11"; - ste,config = <&in_pu>; - }; - }; - - i2c2_sleep_mode: i2c_sleep { - sleep_cfg1 { - pins = "GPIO11", "GPIO11"; - ste,config = <&slpm_in_pu>; - }; - }; - }; - - i2c4 { - i2c4_default_mux: i2c_mux { - default_mux { - function = "i2c4"; - groups = "i2c4_b_2"; - }; - }; - - i2c4_default_mode: i2c_default { - default_cfg1 { - pins = "GPIO122", "GPIO123"; - ste,config = <&in_pu>; - }; - }; - - i2c4_sleep_mode: i2c_sleep { - sleep_cfg1 { - pins = "GPIO122", "GPIO123"; - ste,config = <&slpm_in_pu>; - }; - }; - }; - - i2c5 { - i2c5_default_mux: i2c_mux { - default_mux { - function = "i2c5"; - groups = "i2c5_c_2"; - }; - }; - - i2c5_default_mode: i2c_default { - default_cfg1 { - pins = "GPIO118", "GPIO119"; - ste,config = <&in_pu>; - }; - }; - - i2c5_sleep_mode: i2c_sleep { - sleep_cfg1 { - pins = "GPIO118", "GPIO119"; - ste,config = <&slpm_in_pu>; - }; - }; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/ste-ccu8540.dts b/sys/gnu/dts/arm/ste-ccu8540.dts deleted file mode 100644 index 6eaaf638e52..00000000000 --- a/sys/gnu/dts/arm/ste-ccu8540.dts +++ /dev/null @@ -1,94 +0,0 @@ -/* - * Copyright 2013 ST-Ericsson AB - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; -#include "ste-dbx5x0.dtsi" -#include "ste-ccu8540-pinctrl.dtsi" - -/ { - model = "ST-Ericsson U8540 platform with Device Tree"; - compatible = "st-ericsson,ccu8540", "st-ericsson,u8540"; - - /* This stablilizes the serial port enumeration */ - aliases { - serial0 = &ux500_serial0; - serial1 = &ux500_serial1; - serial2 = &ux500_serial2; - }; - - memory@0 { - device_type = "memory"; - reg = <0x20000000 0x1f000000>, <0xc0000000 0x3f000000>; - }; - - soc { - pinctrl { - compatible = "stericsson,db8540-pinctrl"; - }; - - prcmu@80157000 { - reg = <0x80157000 0x2000>, <0x801b0000 0x8000>, <0x801b8000 0x3000>; - reg-names = "prcmu", "prcmu-tcpm", "prcmu-tcdm"; - }; - - uart@80120000 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&uart0_default_mux>, <&uart0_default_mode>; - pinctrl-1 = <&uart0_sleep_mode>; - status = "okay"; - }; - - uart@80121000 { - status = "okay"; - }; - - uart@80007000 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&uart2_default_mode>; - pinctrl-1 = <&uart2_sleep_mode>; - status = "okay"; - }; - - i2c0: i2c@80004000 { - pinctrl-names = "default","sleep"; - pinctrl-0 = <&i2c0_default_mux>, <&i2c0_default_mode>; - pinctrl-1 = <&i2c0_sleep_mode>; - }; - - i2c1: i2c@80122000 { - pinctrl-names = "default","sleep"; - pinctrl-0 = <&i2c1_default_mux>, <&i2c1_default_mode>; - pinctrl-1 = <&i2c1_sleep_mode>; - }; - - i2c2: i2c@80128000 { - pinctrl-names = "default","sleep"; - pinctrl-0 = <&i2c2_default_mux>, <&i2c2_default_mode>; - pinctrl-1 = <&i2c2_sleep_mode>; - }; - - i2c3: i2c@80110000 { - status = "disabled"; - }; - - i2c4: i2c@8012a000 { - pinctrl-names = "default","sleep"; - pinctrl-0 = <&i2c4_default_mux>, <&i2c4_default_mode>; - pinctrl-1 = <&i2c4_sleep_mode>; - }; - - i2c5: i2c@80001000 { - pinctrl-names = "default","sleep"; - pinctrl-0 = <&i2c5_default_mux>, <&i2c5_default_mode>; - pinctrl-1 = <&i2c5_sleep_mode>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/ste-ccu9540.dts b/sys/gnu/dts/arm/ste-ccu9540.dts deleted file mode 100644 index c8b815819cf..00000000000 --- a/sys/gnu/dts/arm/ste-ccu9540.dts +++ /dev/null @@ -1,79 +0,0 @@ -/* - * Copyright 2012 ST-Ericsson AB - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; -#include "ste-dbx5x0.dtsi" - -/ { - model = "ST-Ericsson CCU9540 platform with Device Tree"; - compatible = "st-ericsson,ccu9540", "st-ericsson,u9540"; - - /* This stablilizes the serial port enumeration */ - aliases { - serial0 = &ux500_serial0; - serial1 = &ux500_serial1; - serial2 = &ux500_serial2; - }; - - memory { - reg = <0x00000000 0x20000000>; - }; - - soc { - uart@80120000 { - status = "okay"; - }; - - uart@80121000 { - status = "okay"; - }; - - uart@80007000 { - status = "okay"; - }; - - // External Micro SD slot - sdi0_per1@80126000 { - arm,primecell-periphid = <0x10480180>; - max-frequency = <100000000>; - bus-width = <4>; - cap-sd-highspeed; - cap-mmc-highspeed; - vmmc-supply = <&ab8500_ldo_aux3_reg>; - - cd-gpios = <&gpio7 6 0x4>; // 230 - cd-inverted; - - status = "okay"; - }; - - - // WLAN SDIO channel - sdi1_per2@80118000 { - arm,primecell-periphid = <0x10480180>; - max-frequency = <100000000>; - bus-width = <4>; - - status = "okay"; - }; - - // On-board eMMC - sdi4_per2@80114000 { - arm,primecell-periphid = <0x10480180>; - max-frequency = <100000000>; - bus-width = <8>; - cap-mmc-highspeed; - vmmc-supply = <&ab8500_ldo_aux2_reg>; - - status = "okay"; - }; - }; -}; diff --git a/sys/gnu/dts/arm/ste-db8500.dtsi b/sys/gnu/dts/arm/ste-db8500.dtsi deleted file mode 100644 index d309fad3222..00000000000 --- a/sys/gnu/dts/arm/ste-db8500.dtsi +++ /dev/null @@ -1,15 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later - -#include "ste-dbx5x0.dtsi" - -/ { - cpus { - cpu@300 { - /* cpufreq controls */ - operating-points = <998400 0 - 800000 0 - 400000 0 - 200000 0>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/ste-db8520.dtsi b/sys/gnu/dts/arm/ste-db8520.dtsi deleted file mode 100644 index 48bd8728ae2..00000000000 --- a/sys/gnu/dts/arm/ste-db8520.dtsi +++ /dev/null @@ -1,15 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later - -#include "ste-dbx5x0.dtsi" - -/ { - cpus { - cpu@300 { - /* cpufreq controls */ - operating-points = <1152000 0 - 800000 0 - 400000 0 - 200000 0>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/ste-dbx5x0-pinctrl.dtsi b/sys/gnu/dts/arm/ste-dbx5x0-pinctrl.dtsi deleted file mode 100644 index 7bf7a2d34cb..00000000000 --- a/sys/gnu/dts/arm/ste-dbx5x0-pinctrl.dtsi +++ /dev/null @@ -1,632 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Linaro Ltd. - */ - -#include "ste-nomadik-pinctrl.dtsi" - -&pinctrl { - /* Settings for all UART default and sleep states */ - uart0 { - u0_a_1_default: u0_a_1_default { - default_mux { - function = "u0"; - groups = "u0_a_1"; - }; - default_cfg1 { - pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */ - ste,config = <&in_pu>; - }; - default_cfg2 { - pins = "GPIO1_AJ3", "GPIO3_AH3"; /* RTS+TXD */ - ste,config = <&out_hi>; - }; - }; - - u0_a_1_sleep: u0_a_1_sleep { - sleep_cfg1 { - pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */ - ste,config = <&slpm_in_wkup_pdis>; - }; - sleep_cfg2 { - pins = "GPIO1_AJ3"; /* RTS */ - ste,config = <&slpm_out_hi_wkup_pdis>; - }; - sleep_cfg3 { - pins = "GPIO3_AH3"; /* TXD */ - ste,config = <&slpm_out_wkup_pdis>; - }; - }; - }; - - uart1 { - u1rxtx_a_1_default: u1rxtx_a_1_default { - default_mux { - function = "u1"; - groups = "u1rxtx_a_1"; - }; - default_cfg1 { - pins = "GPIO4_AH6"; /* RXD */ - ste,config = <&in_pu>; - }; - default_cfg2 { - pins = "GPIO5_AG6"; /* TXD */ - ste,config = <&out_hi>; - }; - }; - - u1rxtx_a_1_sleep: u1rxtx_a_1_sleep { - sleep_cfg1 { - pins = "GPIO4_AH6"; /* RXD */ - ste,config = <&slpm_in_wkup_pdis>; - }; - sleep_cfg2 { - pins = "GPIO5_AG6"; /* TXD */ - ste,config = <&slpm_out_wkup_pdis>; - }; - }; - - u1ctsrts_a_1_default: u1ctsrts_a_1_default { - default_mux { - function = "u1"; - groups = "u1ctsrts_a_1"; - }; - default_cfg1 { - pins = "GPIO6_AF6"; /* CTS */ - ste,config = <&in_pu>; - }; - default_cfg2 { - pins = "GPIO7_AG5"; /* RTS */ - ste,config = <&out_hi>; - }; - }; - - u1ctsrts_a_1_sleep: u1ctsrts_a_1_sleep { - sleep_cfg1 { - pins = "GPIO6_AF6"; /* CTS */ - ste,config = <&slpm_in_wkup_pdis>; - }; - sleep_cfg2 { - pins = "GPIO7_AG5"; /* RTS */ - ste,config = <&slpm_out_hi_wkup_pdis>; - }; - }; - }; - - uart2 { - u2rxtx_c_1_default: u2rxtx_c_1_default { - default_mux { - function = "u2"; - groups = "u2rxtx_c_1"; - }; - default_cfg1 { - pins = "GPIO29_W2"; /* RXD */ - ste,config = <&in_pu>; - }; - default_cfg2 { - pins = "GPIO30_W3"; /* TXD */ - ste,config = <&out_hi>; - }; - }; - - u2rxtx_c_1_sleep: u2rxtx_c_1_sleep { - sleep_cfg1 { - pins = "GPIO29_W2"; /* RXD */ - ste,config = <&in_wkup_pdis>; - }; - sleep_cfg2 { - pins = "GPIO30_W3"; /* TXD */ - ste,config = <&out_wkup_pdis>; - }; - }; - }; - - /* Settings for all I2C default and sleep states */ - i2c0 { - i2c0_a_1_default: i2c0_a_1_default { - default_mux { - function = "i2c0"; - groups = "i2c0_a_1"; - }; - default_cfg1 { - pins = "GPIO147_C15", "GPIO148_B16"; /* SDA/SCL */ - ste,config = <&in_nopull>; - }; - }; - - i2c0_a_1_sleep: i2c0_a_1_sleep { - sleep_cfg1 { - pins = "GPIO147_C15", "GPIO148_B16"; /* SDA/SCL */ - ste,config = <&slpm_in_wkup_pdis>; - }; - }; - }; - - i2c1 { - i2c1_b_2_default: i2c1_b_2_default { - default_mux { - function = "i2c1"; - groups = "i2c1_b_2"; - }; - default_cfg1 { - pins = "GPIO16_AD3", "GPIO17_AD4"; /* SDA/SCL */ - ste,config = <&in_nopull>; - }; - }; - - i2c1_b_2_sleep: i2c1_b_2_sleep { - sleep_cfg1 { - pins = "GPIO16_AD3", "GPIO17_AD4"; /* SDA/SCL */ - ste,config = <&slpm_in_wkup_pdis>; - }; - }; - }; - - i2c2 { - i2c2_b_2_default: i2c2_b_2_default { - default_mux { - function = "i2c2"; - groups = "i2c2_b_2"; - }; - default_cfg1 { - pins = "GPIO10_AF5", "GPIO11_AG4"; /* SDA/SCL */ - ste,config = <&in_nopull>; - }; - }; - - i2c2_b_2_sleep: i2c2_b_2_sleep { - sleep_cfg1 { - pins = "GPIO10_AF5", "GPIO11_AG4"; /* SDA/SCL */ - ste,config = <&slpm_in_wkup_pdis>; - }; - }; - }; - - i2c3 { - i2c3_c_2_default: i2c3_c_2_default { - default_mux { - function = "i2c3"; - groups = "i2c3_c_2"; - }; - default_cfg1 { - pins = "GPIO229_AG7", "GPIO230_AF7"; /* SDA/SCL */ - ste,config = <&in_nopull>; - }; - }; - - i2c3_c_2_sleep: i2c3_c_2_sleep { - sleep_cfg1 { - pins = "GPIO229_AG7", "GPIO230_AF7"; /* SDA/SCL */ - ste,config = <&slpm_in_wkup_pdis>; - }; - }; - }; - - /* - * Activating I2C4 will conflict with UART1 about the same pins so do not - * enable I2C4 and UART1 at the same time. - */ - i2c4 { - i2c4_b_1_default: i2c4_b_1_default { - default_mux { - function = "i2c4"; - groups = "i2c4_b_1"; - }; - default_cfg1 { - pins = "GPIO4_AH6", "GPIO5_AG6"; /* SDA/SCL */ - ste,config = <&in_nopull>; - }; - }; - - i2c4_b_1_sleep: i2c4_b_1_sleep { - sleep_cfg1 { - pins = "GPIO4_AH6", "GPIO5_AG6"; /* SDA/SCL */ - ste,config = <&slpm_in_wkup_pdis>; - }; - }; - }; - - /* Settings for all MMC/SD/SDIO default and sleep states */ - sdi0 { - /* This is the external SD card slot, 4 bits wide */ - mc0_a_1_default: mc0_a_1_default { - default_mux { - function = "mc0"; - groups = "mc0_a_1"; - }; - default_cfg1 { - pins = - "GPIO18_AC2", /* CMDDIR */ - "GPIO19_AC1", /* DAT0DIR */ - "GPIO20_AB4"; /* DAT2DIR */ - ste,config = <&out_hi>; - }; - default_cfg2 { - pins = "GPIO22_AA3"; /* FBCLK */ - ste,config = <&in_nopull>; - }; - default_cfg3 { - pins = "GPIO23_AA4"; /* CLK */ - ste,config = <&out_lo>; - }; - default_cfg4 { - pins = - "GPIO24_AB2", /* CMD */ - "GPIO25_Y4", /* DAT0 */ - "GPIO26_Y2", /* DAT1 */ - "GPIO27_AA2", /* DAT2 */ - "GPIO28_AA1"; /* DAT3 */ - ste,config = <&in_pu>; - }; - }; - - mc0_a_1_sleep: mc0_a_1_sleep { - sleep_cfg1 { - pins = - "GPIO18_AC2", /* CMDDIR */ - "GPIO19_AC1", /* DAT0DIR */ - "GPIO20_AB4"; /* DAT2DIR */ - ste,config = <&slpm_out_hi_wkup_pdis>; - }; - sleep_cfg2 { - pins = - "GPIO22_AA3", /* FBCLK */ - "GPIO24_AB2", /* CMD */ - "GPIO25_Y4", /* DAT0 */ - "GPIO26_Y2", /* DAT1 */ - "GPIO27_AA2", /* DAT2 */ - "GPIO28_AA1"; /* DAT3 */ - ste,config = <&slpm_in_wkup_pdis>; - }; - sleep_cfg3 { - pins = "GPIO23_AA4"; /* CLK */ - ste,config = <&slpm_out_lo_wkup_pdis>; - }; - }; - - mc0_a_2_default: mc0_a_2_default { - default_mux { - function = "mc0"; - groups = "mc0_a_2"; - }; - default_cfg1 { - pins = "GPIO22_AA3"; /* FBCLK */ - ste,config = <&in_nopull>; - }; - default_cfg2 { - pins = "GPIO23_AA4"; /* CLK */ - ste,config = <&out_lo>; - }; - default_cfg3 { - pins = - "GPIO24_AB2", /* CMD */ - "GPIO25_Y4", /* DAT0 */ - "GPIO26_Y2", /* DAT1 */ - "GPIO27_AA2", /* DAT2 */ - "GPIO28_AA1"; /* DAT3 */ - ste,config = <&in_pu>; - }; - }; - - mc0_a_2_sleep: mc0_a_2_sleep { - sleep_cfg1 { - pins = - "GPIO22_AA3", /* FBCLK */ - "GPIO24_AB2", /* CMD */ - "GPIO25_Y4", /* DAT0 */ - "GPIO26_Y2", /* DAT1 */ - "GPIO27_AA2", /* DAT2 */ - "GPIO28_AA1"; /* DAT3 */ - ste,config = <&slpm_in_wkup_pdis>; - }; - sleep_cfg2 { - pins = "GPIO23_AA4"; /* CLK */ - ste,config = <&slpm_out_lo_wkup_pdis>; - }; - }; - }; - - sdi1 { - /* This is the WLAN SDIO 4 bits wide */ - mc1_a_1_default: mc1_a_1_default { - default_mux { - function = "mc1"; - groups = "mc1_a_1"; - }; - default_cfg1 { - pins = "GPIO208_AH16"; /* CLK */ - ste,config = <&out_lo>; - }; - default_cfg2 { - pins = "GPIO209_AG15"; /* FBCLK */ - ste,config = <&in_nopull>; - }; - default_cfg3 { - pins = - "GPIO210_AJ15", /* CMD */ - "GPIO211_AG14", /* DAT0 */ - "GPIO212_AF13", /* DAT1 */ - "GPIO213_AG13", /* DAT2 */ - "GPIO214_AH15"; /* DAT3 */ - ste,config = <&in_pu>; - }; - }; - - mc1_a_1_sleep: mc1_a_1_sleep { - sleep_cfg1 { - pins = "GPIO208_AH16"; /* CLK */ - ste,config = <&slpm_out_lo_wkup_pdis>; - }; - sleep_cfg2 { - pins = - "GPIO209_AG15", /* FBCLK */ - "GPIO210_AJ15", /* CMD */ - "GPIO211_AG14", /* DAT0 */ - "GPIO212_AF13", /* DAT1 */ - "GPIO213_AG13", /* DAT2 */ - "GPIO214_AH15"; /* DAT3 */ - ste,config = <&slpm_in_wkup_pdis>; - }; - }; - - mc1_a_2_default: mc1_a_2_default { - default_mux { - function = "mc1"; - groups = "mc1_a_2"; - }; - default_cfg1 { - pins = "GPIO208_AH16"; /* CLK */ - ste,config = <&out_lo>; - }; - default_cfg2 { - pins = - "GPIO210_AJ15", /* CMD */ - "GPIO211_AG14", /* DAT0 */ - "GPIO212_AF13", /* DAT1 */ - "GPIO213_AG13", /* DAT2 */ - "GPIO214_AH15"; /* DAT3 */ - ste,config = <&in_pu>; - }; - }; - - mc1_a_2_sleep: mc1_a_2_sleep { - sleep_cfg1 { - pins = "GPIO208_AH16"; /* CLK */ - ste,config = <&slpm_out_lo_wkup_pdis>; - }; - sleep_cfg2 { - pins = - "GPIO210_AJ15", /* CMD */ - "GPIO211_AG14", /* DAT0 */ - "GPIO212_AF13", /* DAT1 */ - "GPIO213_AG13", /* DAT2 */ - "GPIO214_AH15"; /* DAT3 */ - ste,config = <&slpm_in_wkup_pdis>; - }; - }; - }; - - sdi2 { - /* This is the eMMC 8 bits wide, usually PoP eMMC */ - mc2_a_1_default: mc2_a_1_default { - default_mux { - function = "mc2"; - groups = "mc2_a_1"; - }; - default_cfg1 { - pins = "GPIO128_A5"; /* CLK */ - ste,config = <&out_lo>; - }; - default_cfg2 { - pins = "GPIO130_C8"; /* FBCLK */ - ste,config = <&in_nopull>; - }; - default_cfg3 { - pins = - "GPIO129_B4", /* CMD */ - "GPIO131_A12", /* DAT0 */ - "GPIO132_C10", /* DAT1 */ - "GPIO133_B10", /* DAT2 */ - "GPIO134_B9", /* DAT3 */ - "GPIO135_A9", /* DAT4 */ - "GPIO136_C7", /* DAT5 */ - "GPIO137_A7", /* DAT6 */ - "GPIO138_C5"; /* DAT7 */ - ste,config = <&in_pu>; - }; - }; - - mc2_a_1_sleep: mc2_a_1_sleep { - sleep_cfg1 { - pins = "GPIO128_A5"; /* CLK */ - ste,config = <&out_lo_wkup_pdis>; - }; - sleep_cfg2 { - pins = - "GPIO130_C8", /* FBCLK */ - "GPIO129_B4"; /* CMD */ - ste,config = <&in_wkup_pdis_en>; - }; - sleep_cfg3 { - pins = - "GPIO131_A12", /* DAT0 */ - "GPIO132_C10", /* DAT1 */ - "GPIO133_B10", /* DAT2 */ - "GPIO134_B9", /* DAT3 */ - "GPIO135_A9", /* DAT4 */ - "GPIO136_C7", /* DAT5 */ - "GPIO137_A7", /* DAT6 */ - "GPIO138_C5"; /* DAT7 */ - ste,config = <&in_wkup_pdis>; - }; - }; - }; - - sdi4 { - /* This is the eMMC 8 bits wide, usually PCB-mounted eMMC */ - mc4_a_1_default: mc4_a_1_default { - default_mux { - function = "mc4"; - groups = "mc4_a_1"; - }; - default_cfg1 { - pins = "GPIO203_AE23"; /* CLK */ - ste,config = <&out_lo>; - }; - default_cfg2 { - pins = "GPIO202_AF25"; /* FBCLK */ - ste,config = <&in_nopull>; - }; - default_cfg3 { - pins = - "GPIO201_AF24", /* CMD */ - "GPIO200_AH26", /* DAT0 */ - "GPIO199_AH23", /* DAT1 */ - "GPIO198_AG25", /* DAT2 */ - "GPIO197_AH24", /* DAT3 */ - "GPIO207_AJ23", /* DAT4 */ - "GPIO206_AG24", /* DAT5 */ - "GPIO205_AG23", /* DAT6 */ - "GPIO204_AF23"; /* DAT7 */ - ste,config = <&in_pu>; - }; - }; - - mc4_a_1_sleep: mc4_a_1_sleep { - sleep_cfg1 { - pins = "GPIO203_AE23"; /* CLK */ - ste,config = <&out_lo_wkup_pdis>; - }; - sleep_cfg2 { - pins = - "GPIO202_AF25", /* FBCLK */ - "GPIO201_AF24", /* CMD */ - "GPIO200_AH26", /* DAT0 */ - "GPIO199_AH23", /* DAT1 */ - "GPIO198_AG25", /* DAT2 */ - "GPIO197_AH24", /* DAT3 */ - "GPIO207_AJ23", /* DAT4 */ - "GPIO206_AG24", /* DAT5 */ - "GPIO205_AG23", /* DAT6 */ - "GPIO204_AF23"; /* DAT7 */ - ste,config = <&slpm_in_wkup_pdis>; - }; - }; - }; - - /* - * Multi-rate serial ports (MSPs) - MSP3 output is internal and - * cannot be muxed onto any pins. - */ - msp0 { - msp0txrxtfstck_a_1_default: msp0txrxtfstck_a_1_default { - default_msp0_mux { - function = "msp0"; - groups = "msp0txrx_a_1", "msp0tfstck_a_1"; - }; - default_msp0_cfg { - pins = - "GPIO12_AC4", /* TXD */ - "GPIO15_AC3", /* RXD */ - "GPIO13_AF3", /* TFS */ - "GPIO14_AE3"; /* TCK */ - ste,config = <&in_nopull>; - }; - }; - }; - - msp1 { - msp1txrx_a_1_default: msp1txrx_a_1_default { - default_mux { - function = "msp1"; - groups = "msp1txrx_a_1", "msp1_a_1"; - }; - default_cfg1 { - pins = "GPIO33_AF2"; - ste,config = <&out_lo>; - }; - default_cfg2 { - pins = - "GPIO34_AE1", - "GPIO35_AE2", - "GPIO36_AG2"; - ste,config = <&in_nopull>; - }; - }; - }; - - msp2 { - msp2_a_1_default: msp2_a_1_default { - /* MSP2 usually used for HDMI audio */ - default_mux { - function = "msp2"; - groups = "msp2_a_1"; - }; - default_cfg1 { - pins = - "GPIO193_AH27", /* TXD */ - "GPIO194_AF27", /* TCK */ - "GPIO195_AG28"; /* TFS */ - ste,config = <&in_pd>; - }; - default_cfg2 { - pins = "GPIO196_AG26"; /* RXD */ - ste,config = <&out_lo>; - }; - }; - }; - - musb { - usb_a_1_default: usb_a_1_default { - default_mux { - function = "usb"; - groups = "usb_a_1"; - }; - default_cfg1 { - pins = - "GPIO256_AF28", /* NXT */ - "GPIO258_AD29", /* XCLK */ - "GPIO259_AC29", /* DIR */ - "GPIO260_AD28", /* DAT7 */ - "GPIO261_AD26", /* DAT6 */ - "GPIO262_AE26", /* DAT5 */ - "GPIO263_AG29", /* DAT4 */ - "GPIO264_AE27", /* DAT3 */ - "GPIO265_AD27", /* DAT2 */ - "GPIO266_AC28", /* DAT1 */ - "GPIO267_AC27"; /* DAT0 */ - ste,config = <&in_nopull>; - }; - default_cfg2 { - pins = "GPIO257_AE29"; /* STP */ - ste,config = <&out_hi>; - }; - }; - - usb_a_1_sleep: usb_a_1_sleep { - sleep_cfg1 { - pins = - "GPIO256_AF28", /* NXT */ - "GPIO258_AD29", /* XCLK */ - "GPIO259_AC29"; /* DIR */ - ste,config = <&slpm_wkup_pdis_en>; - }; - sleep_cfg2 { - pins = "GPIO257_AE29"; /* STP */ - ste,config = <&slpm_out_hi_wkup_pdis>; - }; - sleep_cfg3 { - pins = - "GPIO260_AD28", /* DAT7 */ - "GPIO261_AD26", /* DAT6 */ - "GPIO262_AE26", /* DAT5 */ - "GPIO263_AG29", /* DAT4 */ - "GPIO264_AE27", /* DAT3 */ - "GPIO265_AD27", /* DAT2 */ - "GPIO266_AC28", /* DAT1 */ - "GPIO267_AC27"; /* DAT0 */ - ste,config = <&slpm_in_wkup_pdis_en>; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/ste-dbx5x0.dtsi b/sys/gnu/dts/arm/ste-dbx5x0.dtsi deleted file mode 100644 index 6671f74c9f0..00000000000 --- a/sys/gnu/dts/arm/ste-dbx5x0.dtsi +++ /dev/null @@ -1,1144 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2012 Linaro Ltd - */ - -#include -#include -#include -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - - /* This stablilizes the device enumeration */ - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - spi0 = &spi0; - spi1 = &spi1; - spi2 = &spi2; - spi3 = &spi3; - serial0 = &serial0; - serial1 = &serial1; - serial2 = &serial2; - }; - - chosen { - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "ste,dbx500-smp"; - - cpu-map { - cluster0 { - core0 { - cpu = <&CPU0>; - }; - core1 { - cpu = <&CPU1>; - }; - }; - }; - CPU0: cpu@300 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0x300>; - clocks = <&prcmu_clk PRCMU_ARMSS>; - clock-names = "cpu"; - clock-latency = <20000>; - #cooling-cells = <2>; - }; - CPU1: cpu@301 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0x301>; - }; - }; - - thermal-zones { - /* - * Thermal zone for the SoC, using the thermal sensor in the - * PRCMU for temperature and the cpufreq driver for passive - * cooling. - */ - cpu_thermal: cpu-thermal { - polling-delay-passive = <250>; - /* - * This sensor fires interrupts to update the thermal - * zone, so no polling is needed. - */ - polling-delay = <0>; - - thermal-sensors = <&thermal>; - - trips { - cpu_alert: cpu-alert { - temperature = <70000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu-crit { - temperature = <85000>; - hysteresis = <0>; - type = "critical"; - }; - }; - - cooling-maps { - trip = <&cpu_alert>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - contribution = <100>; - }; - }; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "stericsson,db8500", "simple-bus"; - interrupt-parent = <&intc>; - ranges; - - ptm@801ae000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0x801ae000 0x1000>; - - clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>; - clock-names = "apb_pclk", "atclk"; - cpu = <&CPU0>; - out-ports { - port { - ptm0_out_port: endpoint { - remote-endpoint = <&funnel_in_port0>; - }; - }; - }; - }; - - ptm@801af000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0x801af000 0x1000>; - - clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>; - clock-names = "apb_pclk", "atclk"; - cpu = <&CPU1>; - out-ports { - port { - ptm1_out_port: endpoint { - remote-endpoint = <&funnel_in_port1>; - }; - }; - }; - }; - - funnel@801a6000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0x801a6000 0x1000>; - - clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>; - clock-names = "apb_pclk", "atclk"; - out-ports { - port { - funnel_out_port: endpoint { - remote-endpoint = - <&replicator_in_port0>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - funnel_in_port0: endpoint { - remote-endpoint = <&ptm0_out_port>; - }; - }; - - port@1 { - reg = <1>; - funnel_in_port1: endpoint { - remote-endpoint = <&ptm1_out_port>; - }; - }; - }; - }; - - replicator { - compatible = "arm,coresight-static-replicator"; - clocks = <&prcmu_clk PRCMU_APEATCLK>; - clock-names = "atclk"; - - out-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - replicator_out_port0: endpoint { - remote-endpoint = <&tpiu_in_port>; - }; - }; - port@1 { - reg = <1>; - replicator_out_port1: endpoint { - remote-endpoint = <&etb_in_port>; - }; - }; - }; - - in-ports { - port { - replicator_in_port0: endpoint { - remote-endpoint = <&funnel_out_port>; - }; - }; - }; - }; - - tpiu@80190000 { - compatible = "arm,coresight-tpiu", "arm,primecell"; - reg = <0x80190000 0x1000>; - - clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>; - clock-names = "apb_pclk", "atclk"; - in-ports { - port { - tpiu_in_port: endpoint { - remote-endpoint = <&replicator_out_port0>; - }; - }; - }; - }; - - etb@801a4000 { - compatible = "arm,coresight-etb10", "arm,primecell"; - reg = <0x801a4000 0x1000>; - - clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>; - clock-names = "apb_pclk", "atclk"; - in-ports { - port { - etb_in_port: endpoint { - remote-endpoint = <&replicator_out_port1>; - }; - }; - }; - }; - - intc: interrupt-controller@a0411000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <1>; - interrupt-controller; - reg = <0xa0411000 0x1000>, - <0xa0410100 0x100>; - }; - - scu@a0410000 { - compatible = "arm,cortex-a9-scu"; - reg = <0xa0410000 0x100>; - }; - - /* - * The backup RAM is used for retention during sleep - * and various things like spin tables - */ - backupram@80150000 { - compatible = "ste,dbx500-backupram"; - reg = <0x80150000 0x2000>; - }; - - L2: l2-cache { - compatible = "arm,pl310-cache"; - reg = <0xa0412000 0x1000>; - interrupts = ; - cache-unified; - cache-level = <2>; - }; - - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts = ; - }; - - pm_domains: pm_domains0 { - compatible = "stericsson,ux500-pm-domains"; - #power-domain-cells = <1>; - }; - - clocks { - compatible = "stericsson,u8500-clks"; - /* - * Registers for the CLKRST block on peripheral - * groups 1, 2, 3, 5, 6, - */ - reg = <0x8012f000 0x1000>, <0x8011f000 0x1000>, - <0x8000f000 0x1000>, <0xa03ff000 0x1000>, - <0xa03cf000 0x1000>; - - prcmu_clk: prcmu-clock { - #clock-cells = <1>; - }; - - prcc_pclk: prcc-periph-clock { - #clock-cells = <2>; - }; - - prcc_kclk: prcc-kernel-clock { - #clock-cells = <2>; - }; - - rtc_clk: rtc32k-clock { - #clock-cells = <0>; - }; - - smp_twd_clk: smp-twd-clock { - #clock-cells = <0>; - }; - }; - - mtu@a03c6000 { - /* Nomadik System Timer */ - compatible = "st,nomadik-mtu"; - reg = <0xa03c6000 0x1000>; - interrupts = ; - - clocks = <&prcmu_clk PRCMU_TIMCLK>, <&prcc_pclk 6 6>; - clock-names = "timclk", "apb_pclk"; - }; - - timer@a0410600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0xa0410600 0x20>; - interrupts = ; - - clocks = <&smp_twd_clk>; - }; - - watchdog@a0410620 { - compatible = "arm,cortex-a9-twd-wdt"; - reg = <0xa0410620 0x20>; - interrupts = ; - clocks = <&smp_twd_clk>; - }; - - rtc@80154000 { - compatible = "arm,pl031", "arm,primecell"; - reg = <0x80154000 0x1000>; - interrupts = ; - - clocks = <&rtc_clk>; - clock-names = "apb_pclk"; - }; - - gpio0: gpio@8012e000 { - compatible = "stericsson,db8500-gpio", - "st,nomadik-gpio"; - reg = <0x8012e000 0x80>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <2>; - st,supports-sleepmode; - gpio-controller; - #gpio-cells = <2>; - gpio-bank = <0>; - gpio-ranges = <&pinctrl 0 0 32>; - clocks = <&prcc_pclk 1 9>; - }; - - gpio1: gpio@8012e080 { - compatible = "stericsson,db8500-gpio", - "st,nomadik-gpio"; - reg = <0x8012e080 0x80>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <2>; - st,supports-sleepmode; - gpio-controller; - #gpio-cells = <2>; - gpio-bank = <1>; - gpio-ranges = <&pinctrl 0 32 5>; - clocks = <&prcc_pclk 1 9>; - }; - - gpio2: gpio@8000e000 { - compatible = "stericsson,db8500-gpio", - "st,nomadik-gpio"; - reg = <0x8000e000 0x80>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <2>; - st,supports-sleepmode; - gpio-controller; - #gpio-cells = <2>; - gpio-bank = <2>; - gpio-ranges = <&pinctrl 0 64 32>; - clocks = <&prcc_pclk 3 8>; - }; - - gpio3: gpio@8000e080 { - compatible = "stericsson,db8500-gpio", - "st,nomadik-gpio"; - reg = <0x8000e080 0x80>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <2>; - st,supports-sleepmode; - gpio-controller; - #gpio-cells = <2>; - gpio-bank = <3>; - gpio-ranges = <&pinctrl 0 96 2>; - clocks = <&prcc_pclk 3 8>; - }; - - gpio4: gpio@8000e100 { - compatible = "stericsson,db8500-gpio", - "st,nomadik-gpio"; - reg = <0x8000e100 0x80>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <2>; - st,supports-sleepmode; - gpio-controller; - #gpio-cells = <2>; - gpio-bank = <4>; - gpio-ranges = <&pinctrl 0 128 32>; - clocks = <&prcc_pclk 3 8>; - }; - - gpio5: gpio@8000e180 { - compatible = "stericsson,db8500-gpio", - "st,nomadik-gpio"; - reg = <0x8000e180 0x80>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <2>; - st,supports-sleepmode; - gpio-controller; - #gpio-cells = <2>; - gpio-bank = <5>; - gpio-ranges = <&pinctrl 0 160 12>; - clocks = <&prcc_pclk 3 8>; - }; - - gpio6: gpio@8011e000 { - compatible = "stericsson,db8500-gpio", - "st,nomadik-gpio"; - reg = <0x8011e000 0x80>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <2>; - st,supports-sleepmode; - gpio-controller; - #gpio-cells = <2>; - gpio-bank = <6>; - gpio-ranges = <&pinctrl 0 192 32>; - clocks = <&prcc_pclk 2 11>; - }; - - gpio7: gpio@8011e080 { - compatible = "stericsson,db8500-gpio", - "st,nomadik-gpio"; - reg = <0x8011e080 0x80>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <2>; - st,supports-sleepmode; - gpio-controller; - #gpio-cells = <2>; - gpio-bank = <7>; - gpio-ranges = <&pinctrl 0 224 7>; - clocks = <&prcc_pclk 2 11>; - }; - - gpio8: gpio@a03fe000 { - compatible = "stericsson,db8500-gpio", - "st,nomadik-gpio"; - reg = <0xa03fe000 0x80>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <2>; - st,supports-sleepmode; - gpio-controller; - #gpio-cells = <2>; - gpio-bank = <8>; - gpio-ranges = <&pinctrl 0 256 12>; - clocks = <&prcc_pclk 5 1>; - }; - - pinctrl: pinctrl { - compatible = "stericsson,db8500-pinctrl"; - nomadik-gpio-chips = <&gpio0>, <&gpio1>, <&gpio2>, <&gpio3>, - <&gpio4>, <&gpio5>, <&gpio6>, <&gpio7>, - <&gpio8>; - prcm = <&prcmu>; - }; - - usb_per5@a03e0000 { - compatible = "stericsson,db8500-musb"; - reg = <0xa03e0000 0x10000>; - interrupts = ; - interrupt-names = "mc"; - - dr_mode = "otg"; - - dmas = <&dma 38 0 0x2>, /* Logical - DevToMem */ - <&dma 38 0 0x0>, /* Logical - MemToDev */ - <&dma 37 0 0x2>, /* Logical - DevToMem */ - <&dma 37 0 0x0>, /* Logical - MemToDev */ - <&dma 36 0 0x2>, /* Logical - DevToMem */ - <&dma 36 0 0x0>, /* Logical - MemToDev */ - <&dma 19 0 0x2>, /* Logical - DevToMem */ - <&dma 19 0 0x0>, /* Logical - MemToDev */ - <&dma 18 0 0x2>, /* Logical - DevToMem */ - <&dma 18 0 0x0>, /* Logical - MemToDev */ - <&dma 17 0 0x2>, /* Logical - DevToMem */ - <&dma 17 0 0x0>, /* Logical - MemToDev */ - <&dma 16 0 0x2>, /* Logical - DevToMem */ - <&dma 16 0 0x0>, /* Logical - MemToDev */ - <&dma 39 0 0x2>, /* Logical - DevToMem */ - <&dma 39 0 0x0>; /* Logical - MemToDev */ - - dma-names = "iep_1_9", "oep_1_9", - "iep_2_10", "oep_2_10", - "iep_3_11", "oep_3_11", - "iep_4_12", "oep_4_12", - "iep_5_13", "oep_5_13", - "iep_6_14", "oep_6_14", - "iep_7_15", "oep_7_15", - "iep_8", "oep_8"; - - clocks = <&prcc_pclk 5 0>; - }; - - dma: dma-controller@801C0000 { - compatible = "stericsson,db8500-dma40", "stericsson,dma40"; - reg = <0x801C0000 0x1000 0x40010000 0x800>; - reg-names = "base", "lcpa"; - interrupts = ; - - #dma-cells = <3>; - memcpy-channels = <56 57 58 59 60>; - - clocks = <&prcmu_clk PRCMU_DMACLK>; - }; - - prcmu: prcmu@80157000 { - compatible = "stericsson,db8500-prcmu", "syscon"; - reg = <0x80157000 0x2000>, <0x801b0000 0x8000>, <0x801b8000 0x1000>; - reg-names = "prcmu", "prcmu-tcpm", "prcmu-tcdm"; - interrupts = ; - #address-cells = <1>; - #size-cells = <1>; - interrupt-controller; - #interrupt-cells = <2>; - ranges; - - prcmu-timer-4@80157450 { - compatible = "stericsson,db8500-prcmu-timer-4"; - reg = <0x80157450 0xC>; - }; - - thermal: thermal@801573c0 { - compatible = "stericsson,db8500-thermal"; - reg = <0x801573c0 0x40>; - interrupt-parent = <&prcmu>; - interrupts = <21 IRQ_TYPE_LEVEL_HIGH>, - <22 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "IRQ_HOTMON_LOW", "IRQ_HOTMON_HIGH"; - #thermal-sensor-cells = <0>; - }; - - db8500-prcmu-regulators { - compatible = "stericsson,db8500-prcmu-regulator"; - - // DB8500_REGULATOR_VAPE - db8500_vape_reg: db8500_vape { - regulator-always-on; - }; - - // DB8500_REGULATOR_VARM - db8500_varm_reg: db8500_varm { - }; - - // DB8500_REGULATOR_VMODEM - db8500_vmodem_reg: db8500_vmodem { - }; - - // DB8500_REGULATOR_VPLL - db8500_vpll_reg: db8500_vpll { - }; - - // DB8500_REGULATOR_VSMPS1 - db8500_vsmps1_reg: db8500_vsmps1 { - }; - - // DB8500_REGULATOR_VSMPS2 - db8500_vsmps2_reg: db8500_vsmps2 { - }; - - // DB8500_REGULATOR_VSMPS3 - db8500_vsmps3_reg: db8500_vsmps3 { - }; - - // DB8500_REGULATOR_VRF1 - db8500_vrf1_reg: db8500_vrf1 { - }; - - // DB8500_REGULATOR_SWITCH_SVAMMDSP - db8500_sva_mmdsp_reg: db8500_sva_mmdsp { - }; - - // DB8500_REGULATOR_SWITCH_SVAMMDSPRET - db8500_sva_mmdsp_ret_reg: db8500_sva_mmdsp_ret { - }; - - // DB8500_REGULATOR_SWITCH_SVAPIPE - db8500_sva_pipe_reg: db8500_sva_pipe { - }; - - // DB8500_REGULATOR_SWITCH_SIAMMDSP - db8500_sia_mmdsp_reg: db8500_sia_mmdsp { - }; - - // DB8500_REGULATOR_SWITCH_SIAMMDSPRET - db8500_sia_mmdsp_ret_reg: db8500_sia_mmdsp_ret { - }; - - // DB8500_REGULATOR_SWITCH_SIAPIPE - db8500_sia_pipe_reg: db8500_sia_pipe { - }; - - // DB8500_REGULATOR_SWITCH_SGA - db8500_sga_reg: db8500_sga { - vin-supply = <&db8500_vape_reg>; - }; - - // DB8500_REGULATOR_SWITCH_B2R2_MCDE - db8500_b2r2_mcde_reg: db8500_b2r2_mcde { - vin-supply = <&db8500_vape_reg>; - }; - - // DB8500_REGULATOR_SWITCH_ESRAM12 - db8500_esram12_reg: db8500_esram12 { - }; - - // DB8500_REGULATOR_SWITCH_ESRAM12RET - db8500_esram12_ret_reg: db8500_esram12_ret { - }; - - // DB8500_REGULATOR_SWITCH_ESRAM34 - db8500_esram34_reg: db8500_esram34 { - }; - - // DB8500_REGULATOR_SWITCH_ESRAM34RET - db8500_esram34_ret_reg: db8500_esram34_ret { - }; - }; - }; - - i2c0: i2c@80004000 { - compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; - reg = <0x80004000 0x1000>; - interrupts = ; - - #address-cells = <1>; - #size-cells = <0>; - v-i2c-supply = <&db8500_vape_reg>; - - clock-frequency = <400000>; - clocks = <&prcc_kclk 3 3>, <&prcc_pclk 3 3>; - clock-names = "i2cclk", "apb_pclk"; - power-domains = <&pm_domains DOMAIN_VAPE>; - - status = "disabled"; - }; - - i2c1: i2c@80122000 { - compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; - reg = <0x80122000 0x1000>; - interrupts = ; - - #address-cells = <1>; - #size-cells = <0>; - v-i2c-supply = <&db8500_vape_reg>; - - clock-frequency = <400000>; - - clocks = <&prcc_kclk 1 2>, <&prcc_pclk 1 2>; - clock-names = "i2cclk", "apb_pclk"; - power-domains = <&pm_domains DOMAIN_VAPE>; - - status = "disabled"; - }; - - i2c2: i2c@80128000 { - compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; - reg = <0x80128000 0x1000>; - interrupts = ; - - #address-cells = <1>; - #size-cells = <0>; - v-i2c-supply = <&db8500_vape_reg>; - - clock-frequency = <400000>; - - clocks = <&prcc_kclk 1 6>, <&prcc_pclk 1 6>; - clock-names = "i2cclk", "apb_pclk"; - power-domains = <&pm_domains DOMAIN_VAPE>; - - status = "disabled"; - }; - - i2c3: i2c@80110000 { - compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; - reg = <0x80110000 0x1000>; - interrupts = ; - - #address-cells = <1>; - #size-cells = <0>; - v-i2c-supply = <&db8500_vape_reg>; - - clock-frequency = <400000>; - - clocks = <&prcc_kclk 2 0>, <&prcc_pclk 2 0>; - clock-names = "i2cclk", "apb_pclk"; - power-domains = <&pm_domains DOMAIN_VAPE>; - - status = "disabled"; - }; - - i2c4: i2c@8012a000 { - compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; - reg = <0x8012a000 0x1000>; - interrupts = ; - - #address-cells = <1>; - #size-cells = <0>; - v-i2c-supply = <&db8500_vape_reg>; - - clock-frequency = <400000>; - - clocks = <&prcc_kclk 1 9>, <&prcc_pclk 1 10>; - clock-names = "i2cclk", "apb_pclk"; - power-domains = <&pm_domains DOMAIN_VAPE>; - - status = "disabled"; - }; - - ssp0: spi@80002000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x80002000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&prcc_kclk 3 1>, <&prcc_pclk 3 1>; - clock-names = "SSPCLK", "apb_pclk"; - dmas = <&dma 8 0 0x2>, /* Logical - DevToMem */ - <&dma 8 0 0x0>; /* Logical - MemToDev */ - dma-names = "rx", "tx"; - power-domains = <&pm_domains DOMAIN_VAPE>; - - status = "disabled"; - }; - - ssp1: spi@80003000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x80003000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&prcc_kclk 3 2>, <&prcc_pclk 3 2>; - clock-names = "SSPCLK", "apb_pclk"; - dmas = <&dma 9 0 0x2>, /* Logical - DevToMem */ - <&dma 9 0 0x0>; /* Logical - MemToDev */ - dma-names = "rx", "tx"; - power-domains = <&pm_domains DOMAIN_VAPE>; - - status = "disabled"; - }; - - spi0: spi@8011a000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x8011a000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - /* Same clock wired to kernel and pclk */ - clocks = <&prcc_pclk 2 8>, <&prcc_pclk 2 8>; - clock-names = "SSPCLK", "apb_pclk"; - dmas = <&dma 0 0 0x2>, /* Logical - DevToMem */ - <&dma 0 0 0x0>; /* Logical - MemToDev */ - dma-names = "rx", "tx"; - power-domains = <&pm_domains DOMAIN_VAPE>; - - status = "disabled"; - }; - - spi1: spi@80112000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x80112000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - /* Same clock wired to kernel and pclk */ - clocks = <&prcc_pclk 2 2>, <&prcc_pclk 2 2>; - clock-names = "SSPCLK", "apb_pclk"; - dmas = <&dma 35 0 0x2>, /* Logical - DevToMem */ - <&dma 35 0 0x0>; /* Logical - MemToDev */ - dma-names = "rx", "tx"; - power-domains = <&pm_domains DOMAIN_VAPE>; - - status = "disabled"; - }; - - spi2: spi@80111000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x80111000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - /* Same clock wired to kernel and pclk */ - clocks = <&prcc_pclk 2 1>, <&prcc_pclk 2 1>; - clock-names = "SSPCLK", "apb_pclk"; - dmas = <&dma 33 0 0x2>, /* Logical - DevToMem */ - <&dma 33 0 0x0>; /* Logical - MemToDev */ - dma-names = "rx", "tx"; - power-domains = <&pm_domains DOMAIN_VAPE>; - - status = "disabled"; - }; - - spi3: spi@80129000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x80129000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - /* Same clock wired to kernel and pclk */ - clocks = <&prcc_pclk 1 7>, <&prcc_pclk 1 7>; - clock-names = "SSPCLK", "apb_pclk"; - dmas = <&dma 40 0 0x2>, /* Logical - DevToMem */ - <&dma 40 0 0x0>; /* Logical - MemToDev */ - dma-names = "rx", "tx"; - power-domains = <&pm_domains DOMAIN_VAPE>; - - status = "disabled"; - }; - - serial0: uart@80120000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x80120000 0x1000>; - interrupts = ; - - dmas = <&dma 13 0 0x2>, /* Logical - DevToMem */ - <&dma 13 0 0x0>; /* Logical - MemToDev */ - dma-names = "rx", "tx"; - - clocks = <&prcc_kclk 1 0>, <&prcc_pclk 1 0>; - clock-names = "uart", "apb_pclk"; - - status = "disabled"; - }; - - serial1: uart@80121000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x80121000 0x1000>; - interrupts = ; - - dmas = <&dma 12 0 0x2>, /* Logical - DevToMem */ - <&dma 12 0 0x0>; /* Logical - MemToDev */ - dma-names = "rx", "tx"; - - clocks = <&prcc_kclk 1 1>, <&prcc_pclk 1 1>; - clock-names = "uart", "apb_pclk"; - - status = "disabled"; - }; - - serial2: uart@80007000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x80007000 0x1000>; - interrupts = ; - - dmas = <&dma 11 0 0x2>, /* Logical - DevToMem */ - <&dma 11 0 0x0>; /* Logical - MemToDev */ - dma-names = "rx", "tx"; - - clocks = <&prcc_kclk 3 6>, <&prcc_pclk 3 6>; - clock-names = "uart", "apb_pclk"; - - status = "disabled"; - }; - - sdi0_per1@80126000 { - compatible = "arm,pl18x", "arm,primecell"; - reg = <0x80126000 0x1000>; - interrupts = ; - - dmas = <&dma 29 0 0x2>, /* Logical - DevToMem */ - <&dma 29 0 0x0>; /* Logical - MemToDev */ - dma-names = "rx", "tx"; - - clocks = <&prcc_kclk 1 5>, <&prcc_pclk 1 5>; - clock-names = "sdi", "apb_pclk"; - power-domains = <&pm_domains DOMAIN_VAPE>; - - status = "disabled"; - }; - - sdi1_per2@80118000 { - compatible = "arm,pl18x", "arm,primecell"; - reg = <0x80118000 0x1000>; - interrupts = ; - - dmas = <&dma 32 0 0x2>, /* Logical - DevToMem */ - <&dma 32 0 0x0>; /* Logical - MemToDev */ - dma-names = "rx", "tx"; - - clocks = <&prcc_kclk 2 4>, <&prcc_pclk 2 6>; - clock-names = "sdi", "apb_pclk"; - power-domains = <&pm_domains DOMAIN_VAPE>; - - status = "disabled"; - }; - - sdi2_per3@80005000 { - compatible = "arm,pl18x", "arm,primecell"; - reg = <0x80005000 0x1000>; - interrupts = ; - - dmas = <&dma 28 0 0x2>, /* Logical - DevToMem */ - <&dma 28 0 0x0>; /* Logical - MemToDev */ - dma-names = "rx", "tx"; - - clocks = <&prcc_kclk 3 4>, <&prcc_pclk 3 4>; - clock-names = "sdi", "apb_pclk"; - power-domains = <&pm_domains DOMAIN_VAPE>; - - status = "disabled"; - }; - - sdi3_per2@80119000 { - compatible = "arm,pl18x", "arm,primecell"; - reg = <0x80119000 0x1000>; - interrupts = ; - - dmas = <&dma 41 0 0x2>, /* Logical - DevToMem */ - <&dma 41 0 0x0>; /* Logical - MemToDev */ - dma-names = "rx", "tx"; - - clocks = <&prcc_kclk 2 5>, <&prcc_pclk 2 7>; - clock-names = "sdi", "apb_pclk"; - power-domains = <&pm_domains DOMAIN_VAPE>; - - status = "disabled"; - }; - - sdi4_per2@80114000 { - compatible = "arm,pl18x", "arm,primecell"; - reg = <0x80114000 0x1000>; - interrupts = ; - - dmas = <&dma 42 0 0x2>, /* Logical - DevToMem */ - <&dma 42 0 0x0>; /* Logical - MemToDev */ - dma-names = "rx", "tx"; - - clocks = <&prcc_kclk 2 2>, <&prcc_pclk 2 4>; - clock-names = "sdi", "apb_pclk"; - power-domains = <&pm_domains DOMAIN_VAPE>; - - status = "disabled"; - }; - - sdi5_per3@80008000 { - compatible = "arm,pl18x", "arm,primecell"; - reg = <0x80008000 0x1000>; - interrupts = ; - - dmas = <&dma 43 0 0x2>, /* Logical - DevToMem */ - <&dma 43 0 0x0>; /* Logical - MemToDev */ - dma-names = "rx", "tx"; - - clocks = <&prcc_kclk 3 7>, <&prcc_pclk 3 7>; - clock-names = "sdi", "apb_pclk"; - power-domains = <&pm_domains DOMAIN_VAPE>; - - status = "disabled"; - }; - - sound { - compatible = "stericsson,snd-soc-mop500"; - stericsson,cpu-dai = <&msp1 &msp3>; - }; - - msp0: msp@80123000 { - compatible = "stericsson,ux500-msp-i2s"; - reg = <0x80123000 0x1000>; - interrupts = ; - v-ape-supply = <&db8500_vape_reg>; - - dmas = <&dma 31 0 0x12>, /* Logical - DevToMem - HighPrio */ - <&dma 31 0 0x10>; /* Logical - MemToDev - HighPrio */ - dma-names = "rx", "tx"; - - clocks = <&prcc_kclk 1 3>, <&prcc_pclk 1 3>; - clock-names = "msp", "apb_pclk"; - - status = "disabled"; - }; - - msp1: msp@80124000 { - compatible = "stericsson,ux500-msp-i2s"; - reg = <0x80124000 0x1000>; - interrupts = ; - v-ape-supply = <&db8500_vape_reg>; - - /* This DMA channel only exist on DB8500 v1 */ - dmas = <&dma 30 0 0x10>; /* Logical - MemToDev - HighPrio */ - dma-names = "tx"; - - clocks = <&prcc_kclk 1 4>, <&prcc_pclk 1 4>; - clock-names = "msp", "apb_pclk"; - - status = "disabled"; - }; - - // HDMI sound - msp2: msp@80117000 { - compatible = "stericsson,ux500-msp-i2s"; - reg = <0x80117000 0x1000>; - interrupts = ; - v-ape-supply = <&db8500_vape_reg>; - - dmas = <&dma 14 0 0x12>, /* Logical - DevToMem - HighPrio */ - <&dma 14 1 0x19>; /* Physical Chan 1 - MemToDev - HighPrio - Fixed */ - dma-names = "rx", "tx"; - - clocks = <&prcc_kclk 2 3>, <&prcc_pclk 2 5>; - clock-names = "msp", "apb_pclk"; - - status = "disabled"; - }; - - msp3: msp@80125000 { - compatible = "stericsson,ux500-msp-i2s"; - reg = <0x80125000 0x1000>; - interrupts = ; - v-ape-supply = <&db8500_vape_reg>; - - /* This DMA channel only exist on DB8500 v2 */ - dmas = <&dma 30 0 0x12>; /* Logical - DevToMem - HighPrio */ - dma-names = "rx"; - - clocks = <&prcc_kclk 1 10>, <&prcc_pclk 1 11>; - clock-names = "msp", "apb_pclk"; - - status = "disabled"; - }; - - external-bus@50000000 { - compatible = "simple-bus"; - reg = <0x50000000 0x4000000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x50000000 0x4000000>; - status = "disabled"; - }; - - gpu@a0300000 { - /* - * This block is referred to as "Smart Graphics Adapter SGA500" - * in documentation but is in practice a pretty straight-forward - * MALI-400 GPU block. - */ - compatible = "stericsson,db8500-mali", "arm,mali-400"; - reg = <0xa0300000 0x10000>; - interrupts = , - , - , - , - ; - interrupt-names = "gp", - "gpmmu", - "pp0", - "ppmmu0", - "combined"; - clocks = <&prcmu_clk PRCMU_ACLK>, <&prcmu_clk PRCMU_SGACLK>; - clock-names = "bus", "core"; - mali-supply = <&db8500_sga_reg>; - power-domains = <&pm_domains DOMAIN_VAPE>; - }; - - mcde@a0350000 { - compatible = "ste,mcde"; - reg = <0xa0350000 0x1000>; - interrupts = ; - epod-supply = <&db8500_b2r2_mcde_reg>; - clocks = <&prcmu_clk PRCMU_MCDECLK>, /* Main MCDE clock */ - <&prcmu_clk PRCMU_LCDCLK>, /* LCD clock */ - <&prcmu_clk PRCMU_PLLDSI>; /* HDMI clock */ - clock-names = "mcde", "lcd", "hdmi"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - status = "disabled"; - - dsi0: dsi@a0351000 { - compatible = "ste,mcde-dsi"; - reg = <0xa0351000 0x1000>; - clocks = <&prcmu_clk PRCMU_DSI0CLK>, <&prcmu_clk PRCMU_DSI0ESCCLK>; - clock-names = "hs", "lp"; - #address-cells = <1>; - #size-cells = <0>; - }; - dsi1: dsi@a0352000 { - compatible = "ste,mcde-dsi"; - reg = <0xa0352000 0x1000>; - clocks = <&prcmu_clk PRCMU_DSI1CLK>, <&prcmu_clk PRCMU_DSI1ESCCLK>; - clock-names = "hs", "lp"; - #address-cells = <1>; - #size-cells = <0>; - }; - dsi2: dsi@a0353000 { - compatible = "ste,mcde-dsi"; - reg = <0xa0353000 0x1000>; - /* This DSI port only has the Low Power / Energy Save clock */ - clocks = <&prcmu_clk PRCMU_DSI2ESCCLK>; - clock-names = "lp"; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - cryp@a03cb000 { - compatible = "stericsson,ux500-cryp"; - reg = <0xa03cb000 0x1000>; - interrupts = ; - - v-ape-supply = <&db8500_vape_reg>; - clocks = <&prcc_pclk 6 1>; - }; - - hash@a03c2000 { - compatible = "stericsson,ux500-hash"; - reg = <0xa03c2000 0x1000>; - - v-ape-supply = <&db8500_vape_reg>; - clocks = <&prcc_pclk 6 2>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/ste-href-ab8500.dtsi b/sys/gnu/dts/arm/ste-href-ab8500.dtsi deleted file mode 100644 index 4946743de7b..00000000000 --- a/sys/gnu/dts/arm/ste-href-ab8500.dtsi +++ /dev/null @@ -1,424 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2014 Linaro Ltd. - */ - -#include "ste-ab8500.dtsi" - -/ { - soc { - prcmu@80157000 { - ab8500 { - ab8500-gpio { - /* Hog a few default settings */ - pinctrl-names = "default"; - pinctrl-0 = <&gpio2_default_mode>, - <&gpio4_default_mode>, - <&gpio10_default_mode>, - <&gpio11_default_mode>, - <&gpio12_default_mode>, - <&gpio13_default_mode>, - <&gpio16_default_mode>, - <&gpio24_default_mode>, - <&gpio25_default_mode>, - <&gpio36_default_mode>, - <&gpio37_default_mode>, - <&gpio38_default_mode>, - <&gpio39_default_mode>, - <&gpio42_default_mode>, - <&gpio26_default_mode>, - <&gpio35_default_mode>, - <&ycbcr_default_mode>, - <&pwm_default_mode>, - <&adi1_default_mode>, - <&usbuicc_default_mode>, - <&dmic_default_mode>, - <&extcpena_default_mode>, - <&modsclsda_default_mode>; - - /* - * Pins 2, 4, 10, 11, 12, 13, 16, 24, 25, 36, 37, 38, 39 and 42 - * are muxed in as GPIO, and configured as INPUT PULL DOWN - */ - gpio2 { - gpio2_default_mode: gpio2_default { - default_mux { - function = "gpio"; - groups = "gpio2_a_1"; - }; - default_cfg { - pins = "GPIO2_T9"; - input-enable; - bias-pull-down; - }; - }; - }; - gpio4 { - gpio4_default_mode: gpio4_default { - default_mux { - function = "gpio"; - groups = "gpio4_a_1"; - }; - default_cfg { - pins = "GPIO4_W2"; - input-enable; - bias-pull-down; - }; - }; - }; - gpio10 { - gpio10_default_mode: gpio10_default { - default_mux { - function = "gpio"; - groups = "gpio10_d_1"; - }; - default_cfg { - pins = "GPIO10_U17"; - input-enable; - bias-pull-down; - }; - }; - }; - gpio11 { - gpio11_default_mode: gpio11_default { - default_mux { - function = "gpio"; - groups = "gpio11_d_1"; - }; - default_cfg { - pins = "GPIO11_AA18"; - input-enable; - bias-pull-down; - }; - }; - }; - gpio12 { - gpio12_default_mode: gpio12_default { - default_mux { - function = "gpio"; - groups = "gpio12_d_1"; - }; - default_cfg { - pins = "GPIO12_U16"; - input-enable; - bias-pull-down; - }; - }; - }; - gpio13 { - gpio13_default_mode: gpio13_default { - default_mux { - function = "gpio"; - groups = "gpio13_d_1"; - }; - default_cfg { - pins = "GPIO13_W17"; - input-enable; - bias-pull-down; - }; - }; - }; - gpio16 { - gpio16_default_mode: gpio16_default { - default_mux { - function = "gpio"; - groups = "gpio16_a_1"; - }; - default_cfg { - pins = "GPIO16_F15"; - input-enable; - bias-pull-down; - }; - }; - }; - gpio24 { - gpio24_default_mode: gpio24_default { - default_mux { - function = "gpio"; - groups = "gpio24_a_1"; - }; - default_cfg { - pins = "GPIO24_T14"; - input-enable; - bias-pull-down; - }; - }; - }; - gpio25 { - gpio25_default_mode: gpio25_default { - default_mux { - function = "gpio"; - groups = "gpio25_a_1"; - }; - default_cfg { - pins = "GPIO25_R16"; - input-enable; - bias-pull-down; - }; - }; - }; - gpio36 { - gpio36_default_mode: gpio36_default { - default_mux { - function = "gpio"; - groups = "gpio36_a_1"; - }; - default_cfg { - pins = "GPIO36_A17"; - input-enable; - bias-pull-down; - }; - }; - }; - gpio37 { - gpio37_default_mode: gpio37_default { - default_mux { - function = "gpio"; - groups = "gpio37_a_1"; - }; - default_cfg { - pins = "GPIO37_E15"; - input-enable; - bias-pull-down; - }; - }; - }; - gpio38 { - gpio38_default_mode: gpio38_default { - default_mux { - function = "gpio"; - groups = "gpio38_a_1"; - }; - default_cfg { - pins = "GPIO38_C17"; - input-enable; - bias-pull-down; - }; - }; - }; - gpio39 { - gpio39_default_mode: gpio39_default { - default_mux { - function = "gpio"; - groups = "gpio39_a_1"; - }; - default_cfg { - pins = "GPIO39_E16"; - input-enable; - bias-pull-down; - }; - }; - }; - gpio42 { - gpio42_default_mode: gpio42_default { - default_mux { - function = "gpio"; - groups = "gpio42_a_1"; - }; - default_cfg { - pins = "GPIO42_U2"; - input-enable; - bias-pull-down; - }; - }; - }; - /* - * Pins 26 and 35 muxed in as GPIO, and configured as OUTPUT LOW - */ - gpio26 { - gpio26_default_mode: gpio26_default { - default_mux { - function = "gpio"; - groups = "gpio26_d_1"; - }; - default_cfg { - pins = "GPIO26_M16"; - output-low; - }; - }; - }; - gpio35 { - gpio35_default_mode: gpio35_default { - default_mux { - function = "gpio"; - groups = "gpio35_d_1"; - }; - default_cfg { - pins = "GPIO35_W15"; - output-low; - }; - }; - }; - /* - * This sets up the YCBCR connector pins, i.e. analog video out. - * Set as input with no bias. - */ - ycbcr { - ycbcr_default_mode: ycbcr_default { - default_mux { - function = "ycbcr"; - groups = "ycbcr0123_d_1"; - }; - default_cfg { - pins = "GPIO6_Y18", - "GPIO7_AA20", - "GPIO8_W18", - "GPIO9_AA19"; - input-enable; - bias-disable; - }; - }; - }; - /* This sets up the PWM pins 14 and 15 */ - pwm { - pwm_default_mode: pwm_default { - default_mux { - function = "pwmout"; - groups = "pwmout1_d_1", "pwmout2_d_1"; - }; - default_cfg { - pins = "GPIO14_F14", - "GPIO15_B17"; - input-enable; - bias-pull-down; - }; - }; - }; - /* This sets up audio interface 1 */ - adi1 { - adi1_default_mode: adi1_default { - default_mux { - function = "adi1"; - groups = "adi1_d_1"; - }; - default_cfg { - pins = "GPIO17_P5", - "GPIO18_R5", - "GPIO19_U5", - "GPIO20_T5"; - input-enable; - bias-pull-down; - }; - }; - }; - /* This sets up the USB UICC pins */ - usbuicc { - usbuicc_default_mode: usbuicc_default { - default_mux { - function = "usbuicc"; - groups = "usbuicc_d_1"; - }; - default_cfg { - pins = "GPIO21_H19", - "GPIO22_G20", - "GPIO23_G19"; - input-enable; - bias-pull-down; - }; - }; - }; - /* This sets up the microphone pins */ - dmic { - dmic_default_mode: dmic_default { - default_mux { - function = "dmic"; - groups = "dmic12_d_1", - "dmic34_d_1", - "dmic56_d_1"; - }; - default_cfg { - pins = "GPIO27_J6", - "GPIO28_K6", - "GPIO29_G6", - "GPIO30_H6", - "GPIO31_F5", - "GPIO32_G5"; - input-enable; - bias-pull-down; - }; - }; - }; - extcpena { - extcpena_default_mode: extcpena_default { - default_mux { - function = "extcpena"; - groups = "extcpena_d_1"; - }; - default_cfg { - pins = "GPIO34_R17"; - input-enable; - bias-pull-down; - }; - }; - }; - /* Modem I2C setup (SCL and SDA pins) */ - modsclsda { - modsclsda_default_mode: modsclsda_default { - default_mux { - function = "modsclsda"; - groups = "modsclsda_d_1"; - }; - default_cfg { - pins = "GPIO40_T19", - "GPIO41_U19"; - input-enable; - bias-pull-down; - }; - }; - }; - /* - * Clock output pins associated with regulators. - */ - sysclkreq2 { - sysclkreq2_default_mode: sysclkreq2_default { - default_mux { - function = "sysclkreq"; - groups = "sysclkreq2_d_1"; - }; - default_cfg { - pins = "GPIO1_T10"; - input-enable; - bias-disable; - }; - }; - sysclkreq2_sleep_mode: sysclkreq2_sleep { - default_mux { - function = "gpio"; - groups = "gpio1_a_1"; - }; - default_cfg { - pins = "GPIO1_T10"; - input-enable; - bias-pull-down; - }; - }; - }; - sysclkreq4 { - sysclkreq4_default_mode: sysclkreq4_default { - default_mux { - function = "sysclkreq"; - groups = "sysclkreq4_d_1"; - }; - default_cfg { - pins = "GPIO3_U9"; - input-enable; - bias-disable; - }; - }; - sysclkreq4_sleep_mode: sysclkreq4_sleep { - default_mux { - function = "gpio"; - groups = "gpio3_a_1"; - }; - default_cfg { - pins = "GPIO3_U9"; - input-enable; - bias-pull-down; - }; - }; - }; - }; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/ste-href-ab8505.dtsi b/sys/gnu/dts/arm/ste-href-ab8505.dtsi deleted file mode 100644 index ccf37a9df05..00000000000 --- a/sys/gnu/dts/arm/ste-href-ab8505.dtsi +++ /dev/null @@ -1,240 +0,0 @@ -/* - * Copyright 2014 Linaro Ltd. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/ { - soc { - prcmu@80157000 { - ab8505 { - ab8505-gpio { - /* Hog a few default settings */ - pinctrl-names = "default"; - pinctrl-0 = <&gpio2_default_mode>, - <&gpio10_default_mode>, - <&gpio11_default_mode>, - <&gpio13_default_mode>, - <&gpio34_default_mode>, - <&gpio50_default_mode>, - <&pwm_default_mode>, - <&adi2_default_mode>, - <&modsclsda_default_mode>, - <&resethw_default_mode>, - <&service_default_mode>; - - /* - * Pins 2, 10, 11, 13, 34 and 50 - * are muxed in as GPIO, and configured as INPUT PULL DOWN - */ - gpio2 { - gpio2_default_mode: gpio2_default { - default_mux { - function = "gpio"; - groups = "gpio2_a_1"; - }; - default_cfg { - pins = "GPIO2_R5"; - input-enable; - bias-pull-down; - }; - }; - }; - gpio10 { - gpio10_default_mode: gpio10_default { - default_mux { - function = "gpio"; - groups = "gpio10_d_1"; - }; - default_cfg { - pins = "GPIO10_B16"; - input-enable; - bias-pull-down; - }; - }; - }; - gpio11 { - gpio11_default_mode: gpio11_default { - default_mux { - function = "gpio"; - groups = "gpio11_d_1"; - }; - default_cfg { - pins = "GPIO11_B17"; - input-enable; - bias-pull-down; - }; - }; - }; - gpio13 { - gpio13_default_mode: gpio13_default { - default_mux { - function = "gpio"; - groups = "gpio13_d_1"; - }; - default_cfg { - pins = "GPIO13_D17"; - input-enable; - bias-disable; - }; - }; - }; - gpio34 { - gpio34_default_mode: gpio34_default { - default_mux { - function = "gpio"; - groups = "gpio34_a_1"; - }; - default_cfg { - pins = "GPIO34_H14"; - input-enable; - bias-pull-down; - }; - }; - }; - gpio50 { - gpio50_default_mode: gpio50_default { - default_mux { - function = "gpio"; - groups = "gpio50_d_1"; - }; - default_cfg { - pins = "GPIO50_L4"; - input-enable; - bias-disable; - }; - }; - }; - /* This sets up the PWM pin 14 */ - pwm { - pwm_default_mode: pwm_default { - default_mux { - function = "pwmout"; - groups = "pwmout1_d_1"; - }; - default_cfg { - pins = "GPIO14_C16"; - input-enable; - bias-pull-down; - }; - }; - }; - /* This sets up audio interface 2 */ - adi2 { - adi2_default_mode: adi2_default { - default_mux { - function = "adi2"; - groups = "adi2_d_1"; - }; - default_cfg { - pins = "GPIO17_P2", - "GPIO18_N3", - "GPIO19_T1", - "GPIO20_P3"; - input-enable; - bias-pull-down; - }; - }; - }; - /* Modem I2C setup (SCL and SDA pins) */ - modsclsda { - modsclsda_default_mode: modsclsda_default { - default_mux { - function = "modsclsda"; - groups = "modsclsda_d_1"; - }; - default_cfg { - pins = "GPIO40_J15", - "GPIO41_J14"; - input-enable; - bias-pull-down; - }; - }; - }; - resethw { - resethw_default_mode: resethw_default { - default_mux { - function = "resethw"; - groups = "resethw_d_1"; - }; - default_cfg { - pins = "GPIO52_D16"; - input-enable; - bias-pull-down; - }; - }; - }; - service { - service_default_mode: service_default { - default_mux { - function = "service"; - groups = "service_d_1"; - }; - default_cfg { - pins = "GPIO53_D15"; - input-enable; - bias-pull-down; - }; - }; - }; - /* - * Clock output pins associated with regulators. - */ - sysclkreq2 { - sysclkreq2_default_mode: sysclkreq2_default { - default_mux { - function = "sysclkreq"; - groups = "sysclkreq2_d_1"; - }; - default_cfg { - pins = "GPIO1_N4"; - input-enable; - bias-disable; - }; - }; - sysclkreq2_sleep_mode: sysclkreq2_sleep { - default_mux { - function = "gpio"; - groups = "gpio1_a_1"; - }; - default_cfg { - pins = "GPIO1_N4"; - input-enable; - bias-pull-down; - }; - }; - }; - sysclkreq4 { - sysclkreq4_default_mode: sysclkreq4_default { - default_mux { - function = "sysclkreq"; - groups = "sysclkreq4_d_1"; - }; - default_cfg { - pins = "GPIO3_P5"; - input-enable; - bias-disable; - }; - }; - sysclkreq4_sleep_mode: sysclkreq4_sleep { - default_mux { - function = "gpio"; - groups = "gpio3_a_1"; - }; - default_cfg { - pins = "GPIO3_P5"; - input-enable; - bias-pull-down; - }; - }; - }; - }; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/ste-href-family-pinctrl.dtsi b/sys/gnu/dts/arm/ste-href-family-pinctrl.dtsi deleted file mode 100644 index 434fa6baf71..00000000000 --- a/sys/gnu/dts/arm/ste-href-family-pinctrl.dtsi +++ /dev/null @@ -1,212 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Linaro Ltd. - */ - -#include "ste-dbx5x0-pinctrl.dtsi" - -/ { - soc { - pinctrl { - /* Settings for all SPI default and sleep states */ - spi2 { - spi2_default_mode: spi_default { - default_mux { - function = "spi2"; - groups = "spi2_oc1_2"; - }; - default_cfg1 { - pins = "GPIO216_AG12"; /* FRM */ - ste,config = <&gpio_out_hi>; - }; - default_cfg2 { - pins = "GPIO218_AH11"; /* RXD */ - ste,config = <&in_pd>; - }; - default_cfg3 { - pins = - "GPIO215_AH13", /* TXD */ - "GPIO217_AH12"; /* CLK */ - ste,config = <&out_lo>; - }; - }; - - spi2_idle_mode: spi_idle { - /* - * The idle mode is basically sleep mode sans wakeups. Also - * note that we have muxes the pins off the function here - * as we do not state any muxing. - */ - idle_cfg1 { - pins = "GPIO218_AH11"; /* RXD */ - ste,config = <&slpm_in_pdis>; - }; - idle_cfg2 { - pins = "GPIO215_AH13"; /* TXD */ - ste,config = <&slpm_out_lo_pdis>; - }; - idle_cfg3 { - pins = "GPIO217_AH12"; /* CLK */ - ste,config = <&slpm_pdis>; - }; - }; - - spi2_sleep_mode: spi_sleep { - sleep_cfg1 { - pins = - "GPIO216_AG12", /* FRM */ - "GPIO218_AH11"; /* RXD */ - ste,config = <&slpm_in_wkup_pdis>; - }; - sleep_cfg2 { - pins = "GPIO215_AH13"; /* TXD */ - ste,config = <&slpm_out_lo_wkup_pdis>; - }; - sleep_cfg3 { - pins = "GPIO217_AH12"; /* CLK */ - ste,config = <&slpm_wkup_pdis>; - }; - }; - }; - - mcde { - lcd_default_mode: lcd_default { - default_mux1 { - /* Mux in VSI0 and all the data lines */ - function = "lcd"; - groups = - "lcdvsi0_a_1", /* VSI0 for LCD */ - "lcd_d0_d7_a_1", /* Data lines */ - "lcdvsi1_a_1"; /* VSI1 for HDMI */ - }; - default_mux2 { - function = "lcda"; - groups = - "lcdaclk_b_1"; /* Clock line for TV-out */ - }; - default_cfg1 { - pins = - "GPIO68_E1", /* VSI0 */ - "GPIO69_E2"; /* VSI1 */ - ste,config = <&in_pu>; - }; - }; - lcd_sleep_mode: lcd_sleep { - sleep_cfg1 { - pins = "GPIO69_E2"; /* VSI1 */ - ste,config = <&slpm_in_wkup_pdis>; - }; - }; - }; - - ske { - /* SKE keys on position 2 in an 8x8 matrix */ - ske_kpa2_default_mode: ske_kpa2_default { - default_mux { - function = "kp"; - groups = "kp_a_2"; - }; - default_cfg1 { - pins = - "GPIO153_B17", /* I7 */ - "GPIO154_C16", /* I6 */ - "GPIO155_C19", /* I5 */ - "GPIO156_C17", /* I4 */ - "GPIO161_D21", /* I3 */ - "GPIO162_D20", /* I2 */ - "GPIO163_C20", /* I1 */ - "GPIO164_B21"; /* I0 */ - ste,config = <&in_pd>; - }; - default_cfg2 { - pins = - "GPIO157_A18", /* O7 */ - "GPIO158_C18", /* O6 */ - "GPIO159_B19", /* O5 */ - "GPIO160_B20", /* O4 */ - "GPIO165_C21", /* O3 */ - "GPIO166_A22", /* O2 */ - "GPIO167_B24", /* O1 */ - "GPIO168_C22"; /* O0 */ - ste,config = <&out_lo>; - }; - }; - ske_kpa2_sleep_mode: ske_kpa2_sleep { - sleep_cfg1 { - pins = - "GPIO153_B17", /* I7 */ - "GPIO154_C16", /* I6 */ - "GPIO155_C19", /* I5 */ - "GPIO156_C17", /* I4 */ - "GPIO161_D21", /* I3 */ - "GPIO162_D20", /* I2 */ - "GPIO163_C20", /* I1 */ - "GPIO164_B21"; /* I0 */ - ste,config = <&slpm_in_pu_wkup_pdis_en>; - }; - sleep_cfg2 { - pins = - "GPIO157_A18", /* O7 */ - "GPIO158_C18", /* O6 */ - "GPIO159_B19", /* O5 */ - "GPIO160_B20", /* O4 */ - "GPIO165_C21", /* O3 */ - "GPIO166_A22", /* O2 */ - "GPIO167_B24", /* O1 */ - "GPIO168_C22"; /* O0 */ - ste,config = <&slpm_out_lo_pdis>; - }; - }; - /* - * SKE keys on position 1 and "other C1" combi giving - * six rows of six keys. - */ - ske_kpaoc1_default_mode: ske_kpaoc1_default { - default_mux { - function = "kp"; - groups = "kp_a_1", "kp_oc1_1"; - }; - default_cfg1 { - pins = - "GPIO91_B6", /* KP_O0 */ - "GPIO90_A3", /* KP_O1 */ - "GPIO87_B3", /* KP_O2 */ - "GPIO86_C6", /* KP_O3 */ - "GPIO96_D8", /* KP_O6 */ - "GPIO94_D7"; /* KP_O7 */ - ste,config = <&out_lo>; - }; - default_cfg2 { - pins = - "GPIO93_B7", /* KP_I0 */ - "GPIO92_D6", /* KP_I1 */ - "GPIO89_E6", /* KP_I2 */ - "GPIO88_C4", /* KP_I3 */ - "GPIO97_D9", /* KP_I6 */ - "GPIO95_E8"; /* KP_I7 */ - ste,config = <&in_pu>; - }; - }; - }; - - wlan { - wlan_default_mode: wlan_default { - /* - * Activate this mode with the WLAN chip. - * These are plain GPIO pins used by WLAN - */ - default_cfg1 { - pins = - "GPIO226_AF8", /* WLAN_PMU_EN */ - "GPIO85_D5"; /* WLAN_ENA */ - ste,config = <&gpio_out_lo>; - }; - default_cfg2 { - pins = "GPIO4_AH6"; /* WLAN_IRQ on UART1 */ - ste,config = <&gpio_in_pu>; - }; - }; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/ste-href-stuib.dtsi b/sys/gnu/dts/arm/ste-href-stuib.dtsi deleted file mode 100644 index e32d0c36feb..00000000000 --- a/sys/gnu/dts/arm/ste-href-stuib.dtsi +++ /dev/null @@ -1,212 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2012 ST-Ericsson AB - */ - -#include - -/ { - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - vdd-supply = <&ab8500_ldo_aux1_reg>; - pinctrl-names = "default"; - pinctrl-0 = <&prox_stuib_mode>, <&hall_stuib_mode>; - - button@139 { - /* Proximity sensor */ - gpios = <&gpio6 25 GPIO_ACTIVE_HIGH>; - linux,code = <11>; /* SW_FRONT_PROXIMITY */ - label = "SFH7741 Proximity Sensor"; - }; - button@145 { - /* Hall sensor */ - gpios = <&gpio4 17 GPIO_ACTIVE_HIGH>; - linux,code = <0>; /* SW_LID */ - label = "HED54XXU11 Hall Effect Sensor"; - }; - }; - - soc { - i2c@80004000 { - stmpe1601: stmpe1601@40 { - compatible = "st,stmpe1601"; - reg = <0x40>; - interrupts = <26 IRQ_TYPE_EDGE_FALLING>; - interrupt-parent = <&gpio6>; - interrupt-controller; - vcc-supply = <&db8500_vsmps2_reg>; - vio-supply = <&db8500_vsmps2_reg>; - pinctrl-names = "default"; - pinctrl-0 = <&stmpe_stuib_mode>; - - wakeup-source; - st,autosleep-timeout = <1024>; - - stmpe_keypad { - compatible = "st,stmpe-keypad"; - - debounce-interval = <64>; - st,scan-count = <8>; - st,no-autorepeat; - - linux,keymap = <0x205006b - 0x4010074 - 0x3050072 - 0x1030004 - 0x502006a - 0x500000a - 0x5008b - 0x706001c - 0x405000b - 0x6070003 - 0x3040067 - 0x303006c - 0x60400e7 - 0x602009e - 0x4020073 - 0x5050002 - 0x4030069 - 0x3020008>; - }; - }; - }; - - /* Sensors mounted on this board variant */ - i2c@80128000 { - lis331dl@1c { - /* Accelerometer */ - compatible = "st,lis331dl-accel"; - st,drdy-int-pin = <1>; - reg = <0x1c>; - vdd-supply = <&ab8500_ldo_aux1_reg>; - vddio-supply = <&db8500_vsmps2_reg>; - pinctrl-names = "default"; - pinctrl-0 = <&accel_stuib_mode>; - interrupt-parent = <&gpio2>; - interrupts = <18 IRQ_TYPE_EDGE_RISING>, - <19 IRQ_TYPE_EDGE_RISING>; - }; - ak8974@f { - /* Magnetometer */ - compatible = "asahi-kasei,ak8974"; - reg = <0x0f>; - vdd-supply = <&ab8500_ldo_aux1_reg>; - vddio-supply = <&db8500_vsmps2_reg>; - pinctrl-names = "default"; - pinctrl-0 = <&magneto_stuib_mode>; - interrupt-parent = <&gpio1>; - interrupts = <0 IRQ_TYPE_EDGE_RISING>; - }; - }; - - i2c@80110000 { - bu21013_tp@5c { - compatible = "rohm,bu21013_tp"; - reg = <0x5c>; - avdd-supply = <&ab8500_ldo_aux1_reg>; - - rohm,touch-max-x = <384>; - rohm,touch-max-y = <704>; - rohm,flip-y; - pinctrl-names = "default"; - pinctrl-0 = <&touch_rohm_mode>; - }; - - bu21013_tp@5d { - compatible = "rohm,bu21013_tp"; - reg = <0x5d>; - avdd-supply = <&ab8500_ldo_aux1_reg>; - - rohm,touch-max-x = <384>; - rohm,touch-max-y = <704>; - rohm,flip-y; - pinctrl-names = "default"; - pinctrl-0 = <&touch_rohm_mode>; - }; - }; - - pinctrl { - /* Pull up this GPIO pin */ - stmpe { - stmpe_stuib_mode: stmpe_stuib { - stuib_cfg { - ste,pins = "GPIO218_AH11"; - ste,config = <&gpio_in_pu>; - }; - }; - }; - prox { - prox_stuib_mode: prox_stuib { - stuib_cfg { - pins = "GPIO217_AH12"; - ste,config = <&gpio_in_pu>; - }; - }; - }; - hall { - hall_stuib_mode: stuib_tvk { - stuib_cfg { - pins = "GPIO145_C13"; - ste,config = <&gpio_in_pu>; - }; - }; - }; - accelerometer { - accel_stuib_mode: accel_stuib { - /* Accelerometer interrupt lines 1 & 2 */ - stuib_cfg { - pins = "GPIO82_C1", "GPIO83_D3"; - ste,config = <&gpio_in_pu>; - }; - }; - }; - magnetometer { - magneto_stuib_mode: magneto_stuib { - /* Magnetometer uses GPIO 31 and 32, pull these up/down respectively */ - stuib_cfg1 { - pins = "GPIO31_V3"; - ste,config = <&gpio_in_pu>; - }; - stuib_cfg2 { - pins = "GPIO32_V2"; - ste,config = <&gpio_in_pd>; - }; - }; - }; - touch { - touch_rohm_mode: touch_rohm { - /* - * ROHM touch screen uses GPIO 143 for - * RST1, GPIO 146 for RST2 and - * GPIO 67 for interrupts. Pull-up - * the IRQ line and drive both - * reset signals low. - */ - stuib_cfg1 { - pins = "GPIO143_D12", "GPIO146_D13"; - ste,config = <&gpio_out_lo>; - }; - stuib_cfg2 { - pins = "GPIO67_G2"; - ste,config = <&gpio_in_pu>; - }; - }; - }; - }; - - mcde@a0350000 { - status = "okay"; - - dsi@a0351000 { - panel { - compatible = "samsung,s6d16d0"; - reg = <0>; - vdd1-supply = <&ab8500_ldo_aux1_reg>; - reset-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; - }; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/ste-href-tvk1281618-r2.dtsi b/sys/gnu/dts/arm/ste-href-tvk1281618-r2.dtsi deleted file mode 100644 index e024520f4d4..00000000000 --- a/sys/gnu/dts/arm/ste-href-tvk1281618-r2.dtsi +++ /dev/null @@ -1,79 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Device Tree for the TVK1281618 R2 UIB - */ - -#include "ste-href-tvk1281618.dtsi" - -/ { - soc { - i2c@80128000 { - lsm303dlh@18 { - /* Accelerometer */ - compatible = "st,lsm303dlh-accel"; - st,drdy-int-pin = <1>; - drive-open-drain; - reg = <0x18>; - vdd-supply = <&ab8500_ldo_aux1_reg>; - vddio-supply = <&db8500_vsmps2_reg>; - pinctrl-names = "default"; - pinctrl-0 = <&accel_tvk_mode>; - /* - * These interrupts cannot be used: the other component - * ST-Micro L3D4200D gyro that is connected to the same lines - * cannot set its DRDY line to open drain, so it cannot be - * shared with other peripherals. The should be defined for - * the falling edge if they could be wired together. - * - * interrupts-extended = - * <&gpio1 0 IRQ_TYPE_EDGE_FALLING>, - * <&gpio2 19 IRQ_TYPE_EDGE_FALLING>; - */ - }; - lsm303dlh@1e { - /* Magnetometer */ - compatible = "st,lsm303dlh-magn"; - reg = <0x1e>; - vdd-supply = <&ab8500_ldo_aux1_reg>; - vddio-supply = <&db8500_vsmps2_reg>; - /* - * These interrupts cannot be used: the other component - * ST-Micro L3D4200D gyro that is connected to the same lines - * cannot set its DRDY line to open drain, so it cannot be - * shared with other peripherals. The should be defined for - * the falling edge if they could be wired together. - * - * interrupts-extended = - * <&gpio1 0 IRQ_TYPE_EDGE_FALLING>, - * <&gpio2 19 IRQ_TYPE_EDGE_FALLING>; - */ - }; - lis331dl@1c { - /* Accelerometer */ - compatible = "st,lis331dl-accel"; - st,drdy-int-pin = <1>; - reg = <0x1c>; - vdd-supply = <&ab8500_ldo_aux1_reg>; - vddio-supply = <&db8500_vsmps2_reg>; - pinctrl-names = "default"; - pinctrl-0 = <&accel_tvk_mode>; - interrupt-parent = <&gpio2>; - /* INT2 would need to be open drain */ - interrupts = <18 IRQ_TYPE_EDGE_RISING>, - <19 IRQ_TYPE_EDGE_RISING>; - }; - }; - mcde@a0350000 { - status = "okay"; - - dsi@a0351000 { - panel { - compatible = "samsung,s6d16d0"; - reg = <0>; - vdd1-supply = <&ab8500_ldo_aux1_reg>; - reset-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; - }; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/ste-href-tvk1281618-r3.dtsi b/sys/gnu/dts/arm/ste-href-tvk1281618-r3.dtsi deleted file mode 100644 index cb3677f0a1c..00000000000 --- a/sys/gnu/dts/arm/ste-href-tvk1281618-r3.dtsi +++ /dev/null @@ -1,58 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Device Tree for the TVK1281618 R2 UIB - */ - -#include "ste-href-tvk1281618.dtsi" - -/ { - soc { - i2c@80128000 { - /* Marked: - * 129 - * M35 - * L3GD20 - */ - l3gd20@6a { - /* Gyroscope */ - compatible = "st,l3gd20"; - status = "disabled"; - st,drdy-int-pin = <1>; - drive-open-drain; - reg = <0x6a>; // 0x6a or 0x6b - vdd-supply = <&ab8500_ldo_aux1_reg>; - vddio-supply = <&db8500_vsmps2_reg>; - }; - /* - * Marked: - * 2122 - * C3H - * DQEEE - * LIS3DH? - */ - lis3dh@18 { - /* Accelerometer */ - compatible = "st,lis3dh-accel"; - st,drdy-int-pin = <1>; - reg = <0x18>; - vdd-supply = <&ab8500_ldo_aux1_reg>; - vddio-supply = <&db8500_vsmps2_reg>; - pinctrl-names = "default"; - pinctrl-0 = <&accel_tvk_mode>; - }; - }; - - mcde@a0350000 { - status = "okay"; - - dsi@a0351000 { - panel { - compatible = "sony,acx424akp"; - reg = <0>; - vddi-supply = <&ab8500_ldo_aux1_reg>; - reset-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; - }; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/ste-href-tvk1281618.dtsi b/sys/gnu/dts/arm/ste-href-tvk1281618.dtsi deleted file mode 100644 index e1dbfae2259..00000000000 --- a/sys/gnu/dts/arm/ste-href-tvk1281618.dtsi +++ /dev/null @@ -1,218 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2012 ST-Ericsson AB - * - * Device Tree for the TVK1281618 family of UIBs - */ - -#include - -/ { - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - vdd-supply = <&ab8500_ldo_aux1_reg>; - pinctrl-names = "default"; - pinctrl-0 = <&prox_tvk_mode>, <&hall_tvk_mode>; - - button@139 { - /* Proximity sensor */ - gpios = <&gpio6 25 GPIO_ACTIVE_HIGH>; - linux,code = <11>; /* SW_FRONT_PROXIMITY */ - label = "SFH7741 Proximity Sensor"; - }; - button@145 { - /* Hall sensor */ - gpios = <&gpio4 17 GPIO_ACTIVE_HIGH>; - linux,code = <0>; /* SW_LID */ - label = "HED54XXU11 Hall Effect Sensor"; - }; - }; - - soc { - i2c@80004000 { - tc35893@44 { - compatible = "toshiba,tc35893"; - reg = <0x44>; - interrupt-parent = <&gpio6>; - interrupts = <26 IRQ_TYPE_EDGE_RISING>; - pinctrl-names = "default"; - pinctrl-0 = <&tc35893_tvk_mode>; - - interrupt-controller; - #interrupt-cells = <1>; - - tc3589x_gpio { - compatible = "toshiba,tc3589x-gpio"; - interrupts = <0>; - - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - }; - tc3589x_keypad { - compatible = "toshiba,tc3589x-keypad"; - interrupts = <6>; - debounce-delay-ms = <4>; - keypad,num-columns = <8>; - keypad,num-rows = <8>; - linux,no-autorepeat; - wakeup-source; - linux,keymap = <0x0301006b - 0x04010066 - 0x06040072 - 0x040200d7 - 0x0303006a - 0x0205000e - 0x0607008b - 0x0500001c - 0x0403000b - 0x03040034 - 0x05020067 - 0x0305006c - 0x040500e7 - 0x0005009e - 0x06020073 - 0x01030039 - 0x07060069 - 0x050500d9>; - }; - }; - }; - /* Sensors mounted on all board variants */ - i2c@80128000 { - ak8974@f { - /* Magnetometer */ - compatible = "asahi-kasei,ak8974"; - reg = <0x0f>; - avdd-supply = <&ab8500_ldo_aux1_reg>; - dvdd-supply = <&db8500_vsmps2_reg>; - pinctrl-names = "default"; - pinctrl-0 = <&gyro_magn_tvk_mode>; - /* - * These interrupts cannot be used: the other component - * ST-Micro L3D4200D gyro that is connected to the same lines - * cannot set its DRDY line to open drain, so it cannot be - * shared with other peripherals. The should be defined for - * the falling edge if they could be wired together. - * - * interrupts-extended = - * <&gpio1 0 IRQ_TYPE_EDGE_FALLING>, - * <&gpio0 31 IRQ_TYPE_EDGE_FALLING>; - */ - }; - l3g4200d@68 { - /* Gyroscope */ - compatible = "st,l3g4200d-gyro"; - st,drdy-int-pin = <2>; - reg = <0x68>; - vdd-supply = <&ab8500_ldo_aux1_reg>; - vddio-supply = <&db8500_vsmps2_reg>; - pinctrl-names = "default"; - pinctrl-0 = <&gyro_magn_tvk_mode>; - interrupts-extended = - <&gpio1 0 IRQ_TYPE_EDGE_RISING>, - <&gpio0 31 IRQ_TYPE_EDGE_RISING>; - }; - lsp001wm@5c { - /* Barometer/pressure sensor */ - compatible = "st,lps001wp-press"; - reg = <0x5c>; - vdd-supply = <&ab8500_ldo_aux1_reg>; - vddio-supply = <&db8500_vsmps2_reg>; - }; - }; - - i2c@80110000 { - synaptics@4b { - /* Synaptics RMI4 TM1217 touchscreen */ - compatible = "syna,rmi4-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x4b>; - vdd-supply = <&ab8500_ldo_aux1_reg>; - vddio-supply = <&db8500_vsmps2_reg>; - pinctrl-names = "default"; - pinctrl-0 = <&synaptics_tvk_mode>; - interrupt-parent = <&gpio2>; - interrupts = <20 IRQ_TYPE_EDGE_FALLING>; - - rmi-f01@1 { - reg = <0x1>; - syna,nosleep = <1>; - }; - rmi-f11@11 { - reg = <0x11>; - touchscreen-inverted-x; - syna,sensor-type = <1>; - }; - }; - }; - - pinctrl { - /* Pull up this GPIO pin */ - tc35893 { - tc35893_tvk_mode: tc35893_tvk { - tvk_cfg { - pins = "GPIO218_AH11"; - ste,config = <&gpio_in_pu>; - }; - }; - }; - prox { - prox_tvk_mode: prox_tvk { - tvk_cfg { - pins = "GPIO217_AH12"; - ste,config = <&gpio_in_pu>; - }; - }; - }; - hall { - hall_tvk_mode: hall_tvk { - tvk_cfg { - pins = "GPIO145_C13"; - ste,config = <&gpio_in_pu>; - }; - }; - }; - accelerometer { - accel_tvk_mode: accel_tvk { - /* Accelerometer interrupt lines 1 & 2 */ - tvk_cfg { - pins = "GPIO82_C1", "GPIO83_D3"; - ste,config = <&gpio_in_pd>; - }; - }; - }; - gyroscope { - /* - * These lines are shared between Gyroscope l3g400dh - * and AK8974 magnetometer. - */ - gyro_magn_tvk_mode: gyro_magn_tvk { - /* GPIO 31 used for INT pull down the line */ - tvk_cfg1 { - pins = "GPIO31_V3"; - ste,config = <&gpio_in_pd>; - }; - /* GPIO 32 used for DRDY, pull this down */ - tvk_cfg2 { - pins = "GPIO32_V2"; - ste,config = <&gpio_in_pd>; - }; - }; - }; - synaptics { - synaptics_tvk_mode: synaptics_tvk { - /* Touchscreen uses GPIO 84 */ - tvk_cfg1 { - pins = "GPIO84_C2"; - ste,config = <&gpio_in_pu>; - }; - }; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/ste-href.dtsi b/sys/gnu/dts/arm/ste-href.dtsi deleted file mode 100644 index 33e3b0b3c53..00000000000 --- a/sys/gnu/dts/arm/ste-href.dtsi +++ /dev/null @@ -1,277 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2012 ST-Ericsson AB - */ - -#include -#include "ste-href-family-pinctrl.dtsi" - -/ { - memory { - device_type = "memory"; - reg = <0x00000000 0x20000000>; - }; - - soc { - uart@80120000 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&u0_a_1_default>; - pinctrl-1 = <&u0_a_1_sleep>; - status = "okay"; - }; - - /* This UART is unused and thus left disabled */ - uart@80121000 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&u1rxtx_a_1_default>; - pinctrl-1 = <&u1rxtx_a_1_sleep>; - }; - - uart@80007000 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&u2rxtx_c_1_default>; - pinctrl-1 = <&u2rxtx_c_1_sleep>; - status = "okay"; - }; - - i2c@80004000 { - pinctrl-names = "default","sleep"; - pinctrl-0 = <&i2c0_a_1_default>; - pinctrl-1 = <&i2c0_a_1_sleep>; - status = "okay"; - }; - - i2c@80122000 { - pinctrl-names = "default","sleep"; - pinctrl-0 = <&i2c1_b_2_default>; - pinctrl-1 = <&i2c1_b_2_sleep>; - status = "okay"; - }; - - i2c@80128000 { - pinctrl-names = "default","sleep"; - pinctrl-0 = <&i2c2_b_2_default>; - pinctrl-1 = <&i2c2_b_2_sleep>; - status = "okay"; - lp5521@33 { - compatible = "national,lp5521"; - reg = <0x33>; - label = "lp5521_pri"; - clock-mode = /bits/ 8 <2>; - chan0 { - led-cur = /bits/ 8 <0x2f>; - max-cur = /bits/ 8 <0x5f>; - linux,default-trigger = "heartbeat"; - }; - chan1 { - led-cur = /bits/ 8 <0x2f>; - max-cur = /bits/ 8 <0x5f>; - }; - chan2 { - led-cur = /bits/ 8 <0x2f>; - max-cur = /bits/ 8 <0x5f>; - }; - }; - lp5521@34 { - compatible = "national,lp5521"; - reg = <0x34>; - label = "lp5521_sec"; - clock-mode = /bits/ 8 <2>; - chan0 { - led-cur = /bits/ 8 <0x2f>; - max-cur = /bits/ 8 <0x5f>; - }; - chan1 { - led-cur = /bits/ 8 <0x2f>; - max-cur = /bits/ 8 <0x5f>; - }; - chan2 { - led-cur = /bits/ 8 <0x2f>; - max-cur = /bits/ 8 <0x5f>; - }; - }; - bh1780@29 { - compatible = "rohm,bh1780gli"; - reg = <0x29>; - }; - }; - - i2c@80110000 { - pinctrl-names = "default","sleep"; - pinctrl-0 = <&i2c3_c_2_default>; - pinctrl-1 = <&i2c3_c_2_sleep>; - status = "okay"; - }; - - /* ST6G3244ME level translator for 1.8/2.9 V */ - vmmci: regulator-gpio { - compatible = "regulator-gpio"; - - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2900000>; - regulator-name = "mmci-reg"; - regulator-type = "voltage"; - - startup-delay-us = <100>; - - states = <1800000 0x1 - 2900000 0x0>; - }; - - // External Micro SD slot - sdi0_per1@80126000 { - arm,primecell-periphid = <0x10480180>; - max-frequency = <100000000>; - bus-width = <4>; - cap-sd-highspeed; - cap-mmc-highspeed; - sd-uhs-sdr12; - sd-uhs-sdr25; - full-pwr-cycle; - st,sig-dir-dat0; - st,sig-dir-dat2; - st,sig-dir-cmd; - st,sig-pin-fbclk; - vmmc-supply = <&ab8500_ldo_aux3_reg>; - vqmmc-supply = <&vmmci>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&mc0_a_1_default &sdi0_default_mode>; - pinctrl-1 = <&mc0_a_1_sleep>; - - status = "okay"; - }; - - // WLAN SDIO channel - sdi1_per2@80118000 { - arm,primecell-periphid = <0x10480180>; - max-frequency = <100000000>; - bus-width = <4>; - non-removable; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&mc1_a_1_default>; - pinctrl-1 = <&mc1_a_1_sleep>; - - status = "okay"; - }; - - // PoP:ed eMMC - sdi2_per3@80005000 { - arm,primecell-periphid = <0x10480180>; - max-frequency = <100000000>; - bus-width = <8>; - cap-mmc-highspeed; - non-removable; - vmmc-supply = <&db8500_vsmps2_reg>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&mc2_a_1_default>; - pinctrl-1 = <&mc2_a_1_sleep>; - - status = "okay"; - }; - - // On-board eMMC - sdi4_per2@80114000 { - arm,primecell-periphid = <0x10480180>; - max-frequency = <100000000>; - bus-width = <8>; - cap-mmc-highspeed; - non-removable; - vmmc-supply = <&ab8500_ldo_aux2_reg>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&mc4_a_1_default>; - pinctrl-1 = <&mc4_a_1_sleep>; - - status = "okay"; - }; - - msp0: msp@80123000 { - pinctrl-names = "default"; - pinctrl-0 = <&msp0txrxtfstck_a_1_default>; - status = "okay"; - }; - - msp1: msp@80124000 { - pinctrl-names = "default"; - pinctrl-0 = <&msp1txrx_a_1_default>; - status = "okay"; - }; - - msp2: msp@80117000 { - pinctrl-names = "default"; - pinctrl-0 = <&msp2_a_1_default>; - }; - - msp3: msp@80125000 { - status = "okay"; - }; - - prcmu@80157000 { - ab8500 { - ab8500-gpio { - }; - - ab8500_usb { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&usb_a_1_default>; - pinctrl-1 = <&usb_a_1_sleep>; - }; - - ab8500-regulators { - ab8500_ldo_aux1_reg: ab8500_ldo_aux1 { - regulator-name = "V-DISPLAY"; - }; - - ab8500_ldo_aux2_reg: ab8500_ldo_aux2 { - regulator-name = "V-eMMC1"; - }; - - ab8500_ldo_aux3_reg: ab8500_ldo_aux3 { - regulator-name = "V-MMC-SD"; - }; - - ab8500_ldo_intcore_reg: ab8500_ldo_intcore { - regulator-name = "V-INTCORE"; - }; - - ab8500_ldo_tvout_reg: ab8500_ldo_tvout { - regulator-name = "V-TVOUT"; - }; - - ab8500_ldo_audio_reg: ab8500_ldo_audio { - regulator-name = "V-AUD"; - }; - - ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 { - regulator-name = "V-AMIC1"; - }; - - ab8500_ldo_anamic2_reg: ab8500_ldo_anamic2 { - regulator-name = "V-AMIC2"; - }; - - ab8500_ldo_dmic_reg: ab8500_ldo_dmic { - regulator-name = "V-DMIC"; - }; - - ab8500_ldo_ana_reg: ab8500_ldo_ana { - regulator-name = "V-CSI/DSI"; - }; - }; - }; - }; - - pinctrl { - sdi0 { - sdi0_default_mode: sdi0_default { - /* Some boards set additional settings here */ - }; - }; - }; - - mcde@a0350000 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&lcd_default_mode>; - pinctrl-1 = <&lcd_sleep_mode>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/ste-href520-tvk.dts b/sys/gnu/dts/arm/ste-href520-tvk.dts deleted file mode 100644 index f8c0c1e6aa0..00000000000 --- a/sys/gnu/dts/arm/ste-href520-tvk.dts +++ /dev/null @@ -1,22 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Device Tree for the HREF520 version with the TVK1281618 UIB - */ - -/dts-v1/; -#include "ste-db8520.dtsi" -#include "ste-hrefv60plus.dtsi" -#include "ste-href-tvk1281618-r3.dtsi" - -/ { - model = "ST-Ericsson HREF520 and TVK1281618 UIB"; - compatible = "st-ericsson,href520", "st-ericsson,u8500"; - - soc { - vmmci: regulator-gpio { - gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>; - enable-gpio = <&gpio2 14 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - }; -}; diff --git a/sys/gnu/dts/arm/ste-hrefprev60-stuib.dts b/sys/gnu/dts/arm/ste-hrefprev60-stuib.dts deleted file mode 100644 index 8ce6b723abf..00000000000 --- a/sys/gnu/dts/arm/ste-hrefprev60-stuib.dts +++ /dev/null @@ -1,33 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2012 ST-Ericsson AB - */ - -/dts-v1/; -#include "ste-db8500.dtsi" -#include "ste-hrefprev60.dtsi" -#include "ste-href-stuib.dtsi" - -/ { - model = "ST-Ericsson HREF (pre-v60) and ST UIB"; - compatible = "st-ericsson,mop500", "st-ericsson,u8500"; - - soc { - /* Reset line for the BU21013 touchscreen */ - i2c@80110000 { - /* Only one of these will be used */ - bu21013_tp@5c { - interrupt-parent = <&gpio2>; - interrupts = <12 IRQ_TYPE_LEVEL_LOW>; - touch-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; - reset-gpios = <&tc3589x_gpio 13 GPIO_LINE_OPEN_DRAIN>; - }; - bu21013_tp@5d { - interrupt-parent = <&gpio2>; - interrupts = <12 IRQ_TYPE_LEVEL_LOW>; - touch-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; - reset-gpios = <&tc3589x_gpio 13 GPIO_LINE_OPEN_DRAIN>; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/ste-hrefprev60-tvk.dts b/sys/gnu/dts/arm/ste-hrefprev60-tvk.dts deleted file mode 100644 index 142f5475521..00000000000 --- a/sys/gnu/dts/arm/ste-hrefprev60-tvk.dts +++ /dev/null @@ -1,14 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2012 ST-Ericsson AB - */ - -/dts-v1/; -#include "ste-db8500.dtsi" -#include "ste-hrefprev60.dtsi" -#include "ste-href-tvk1281618-r2.dtsi" - -/ { - model = "ST-Ericsson HREF (pre-v60) and TVK1281618 UIB"; - compatible = "st-ericsson,mop500", "st-ericsson,u8500"; -}; diff --git a/sys/gnu/dts/arm/ste-hrefprev60.dtsi b/sys/gnu/dts/arm/ste-hrefprev60.dtsi deleted file mode 100644 index 115495de861..00000000000 --- a/sys/gnu/dts/arm/ste-hrefprev60.dtsi +++ /dev/null @@ -1,128 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2012 ST-Ericsson AB - * - * Device Tree for the HREF+ prior to the v60 variant. - */ - -#include "ste-href-ab8500.dtsi" -#include "ste-href.dtsi" - -/ { - gpio_keys { - button@1 { - gpios = <&tc3589x_gpio 7 GPIO_ACTIVE_HIGH>; - }; - }; - - soc { - /* Enable UART1 on this board */ - uart@80121000 { - status = "okay"; - }; - - i2c@80004000 { - tps61052@33 { - compatible = "ti,tps61052"; - reg = <0x33>; - }; - - tc35892@42 { - compatible = "toshiba,tc35892"; - reg = <0x42>; - interrupt-parent = <&gpio6>; - interrupts = <25 IRQ_TYPE_EDGE_RISING>; - pinctrl-names = "default"; - pinctrl-0 = <&tc35892_hrefprev60_mode>; - - interrupt-controller; - #interrupt-cells = <1>; - - tc3589x_gpio: tc3589x_gpio { - compatible = "tc3589x-gpio"; - interrupts = <0>; - - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - }; - }; - }; - - spi@80002000 { - /* - * On the first generation boards, this SSP/SPI port was connected - * to the AB8500. - */ - pinctrl-names = "default"; - pinctrl-0 = <&ssp0_hrefprev60_mode>; - status = "okay"; - }; - - // External Micro SD slot - sdi0_per1@80126000 { - cd-gpios = <&tc3589x_gpio 3 GPIO_ACTIVE_HIGH>; - }; - - vmmci: regulator-gpio { - gpios = <&tc3589x_gpio 18 GPIO_ACTIVE_HIGH>; - enable-gpio = <&tc3589x_gpio 17 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - pinctrl { - /* Set this up using hogs */ - pinctrl-names = "default"; - pinctrl-0 = <&ipgpio_hrefprev60_mode>; - - ssp0 { - ssp0_hrefprev60_mode: ssp0_hrefprev60_default { - hrefprev60_mux { - function = "ssp0"; - groups = "ssp0_a_1"; - }; - hrefprev60_cfg1 { - pins = "GPIO145_C13"; /* RXD */ - ste,config = <&in_pd>; - }; - - }; - }; - sdi0 { - /* This additional pin needed on early MOP500 and HREFs previous to v60 */ - sdi0_default_mode: sdi0_default { - hrefprev60_mux { - function = "mc0"; - groups = "mc0dat31dir_a_1"; - }; - hrefprev60_cfg1 { - pins = "GPIO21_AB3"; /* DAT31DIR */ - ste,config = <&out_hi>; - }; - - }; - }; - tc35892 { - tc35892_hrefprev60_mode: tc35892_hrefprev60 { - hrefprev60_cfg { - pins = "GPIO217_AH12"; - ste,config = <&gpio_in_pu>; - }; - }; - }; - ipgpio { - ipgpio_hrefprev60_mode: ipgpio_hrefprev60 { - hrefprev60_mux { - function = "ipgpio"; - groups = "ipgpio0_c_1", "ipgpio1_c_1"; - }; - hrefprev60_cfg1 { - pins = "GPIO6_AF6", "GPIO7_AG5"; - ste,config = <&in_pu>; - }; - }; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/ste-hrefv60plus-stuib.dts b/sys/gnu/dts/arm/ste-hrefv60plus-stuib.dts deleted file mode 100644 index 1316886e6bc..00000000000 --- a/sys/gnu/dts/arm/ste-hrefv60plus-stuib.dts +++ /dev/null @@ -1,35 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2012 ST-Ericsson AB - * - * Device Tree for the HREF version 60 or later with the ST UIB - */ - -/dts-v1/; -#include "ste-db8500.dtsi" -#include "ste-hrefv60plus.dtsi" -#include "ste-href-stuib.dtsi" - -/ { - model = "ST-Ericsson HREF (v60+) and ST UIB"; - compatible = "st-ericsson,hrefv60+", "st-ericsson,u8500"; - - soc { - /* Reset line for the BU21013 touchscreen */ - i2c@80110000 { - /* Only one of these will be used */ - bu21013_tp@5c { - interrupt-parent = <&gpio2>; - interrupts = <20 IRQ_TYPE_LEVEL_LOW>; - touch-gpios = <&gpio2 20 GPIO_ACTIVE_LOW>; - reset-gpios = <&gpio4 17 GPIO_LINE_OPEN_DRAIN>; - }; - bu21013_tp@5d { - interrupt-parent = <&gpio2>; - interrupts = <20 IRQ_TYPE_LEVEL_LOW>; - touch-gpios = <&gpio2 20 GPIO_ACTIVE_LOW>; - reset-gpios = <&gpio4 17 GPIO_LINE_OPEN_DRAIN>; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/ste-hrefv60plus-tvk.dts b/sys/gnu/dts/arm/ste-hrefv60plus-tvk.dts deleted file mode 100644 index 5d4b8245f02..00000000000 --- a/sys/gnu/dts/arm/ste-hrefv60plus-tvk.dts +++ /dev/null @@ -1,16 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2012 ST-Ericsson AB - * - * Device Tree for the HREF version 60 or later with the TVK1281618 UIB - */ - -/dts-v1/; -#include "ste-db8500.dtsi" -#include "ste-hrefv60plus.dtsi" -#include "ste-href-tvk1281618-r2.dtsi" - -/ { - model = "ST-Ericsson HREF (v60+) and TVK1281618 UIB"; - compatible = "st-ericsson,hrefv60+", "st-ericsson,u8500"; -}; diff --git a/sys/gnu/dts/arm/ste-hrefv60plus.dtsi b/sys/gnu/dts/arm/ste-hrefv60plus.dtsi deleted file mode 100644 index 05b4fbbba57..00000000000 --- a/sys/gnu/dts/arm/ste-hrefv60plus.dtsi +++ /dev/null @@ -1,335 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2012 ST-Ericsson AB - */ - -#include "ste-href-ab8500.dtsi" -#include "ste-href.dtsi" - -/ { - model = "ST-Ericsson HREF (v60+) platform with Device Tree"; - compatible = "st-ericsson,hrefv60+", "st-ericsson,u8500"; - - soc { - /* Name the GPIO muxed rails on the HREF boards */ - gpio@8012e000 { - /* GPIOs 0 - 31 */ - gpio-line-names = - /* GPIO0,1 used for UART0 BT RX/TX */ - "", "", - "UART_WAKE", - "BT_WAKE", - "", - "SDMMC_1V8_3V_SEL", - "FLASH_LED_SYNC (FLASH_CTRL_0)", - "XENON_READY (FLASH_CTRL_1)", - "", "", "", "", "", "", "", "", - "", "", "", "", - "", - "FLASH_LED_EN (FLASH_CTRL_3)", - "", "", - "", "", "", "", "", - /* Used by UART2 (console) */ - "", "", - "MAGNETOMETER_INT"; - }; - - gpio@8012e080 { - /* GPIOs 32 - 63 */ - gpio-line-names = - "MAGNETOMETER_DRDY", - "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; - }; - - gpio@8000e000 { - /* GPIOs 64 - 95 */ - gpio-line-names = "XENON_EN2 (FLASH_CTRL_4)", - "DISP1_RST", - "DISP2_RST", - "TOUCH_INT2", - "LCD_VSI0_A", - "LCD_VSI1_A", - /* GPIO 70-77 used for ETM */ - "", "", "", "", "", "", "", "", - /* GPIO 78-81 used for YCBCR */ - "", "", "", "", - "ACCELEROMETER_INT1_RDY", - "ACCELEROMETER_INT2", - "TOUCH_INT", - "WLAN_ENA", - "", "", "", "", "", - "FORCE_SENSING_INT", - "FORCE_SENSING_RESET", - "", "", - "SDMMC_CD"; - }; - - gpio@8000e080 { - /* GPIOs 96 - 127 */ - gpio-line-names = "", - "FORCE_SENSING_WU", - "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; - }; - - gpio@8000e100 { - /* GPIOs 128 - 159 */ - gpio-line-names = "", "", "", "", "", "", "", "", - "", "", "", - "DIPRO_INT", /* GPIO139 */ - "XSHUTDOWN_SECONDARY_SENSOR", - "XSHUTDOWN_PRIMARY_SENSOR", - "NFC_RST (NFC_CTRL_", - "TOUCH_RST", - "NFC_IRQ (NFC_CTRL_1)", - "HAL_SW", - "TOUCH_RST2", - "", "", - "VAUDIO_HF_EN", /* GPIO149 */ - "", "", "", "", "", "", "", "", "", ""; - }; - - gpio@8000e180 { - /* GPIOs 160 - 191 */ - gpio-line-names = "", "", "", "", "", "", "", "", - "", - "SDMMC_EN", - "XENON_CHARGE (FLASH_CONTROL_5)", - "GBF_ENA_RESET", - "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; - }; - - gpio@8011e000 { - /* GPIOs 192 - 223 */ - gpio-line-names = "HDTV_INTN", - "", "", "", - "HDTV_RSTN", - "", "", "", - "", /* GPIO200 */ - "", "", "", "", "", "", "", - /* GPIO208-216 used for WGBF_MC1 */ - "", "", "", "", "", "", "", "", "", - "SW_FRONT_PROXIMITY", /* GPIO217 */ - "KPD_CTRL_INT", /* Keypad controller */ - "", "", "", "", ""; - }; - - gpio@8011e080 { - /* GPIOs 224 - 255 */ - gpio-line-names = "", "", - "HSIT_ACWAKE0", - "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; - }; - - // External Micro SD slot - sdi0_per1@80126000 { - cd-gpios = <&gpio2 31 GPIO_ACTIVE_HIGH>; // 95 - }; - - vmmci: regulator-gpio { - gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>; - enable-gpio = <&gpio5 9 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - pinctrl { - /* - * Set this up using hogs, as time goes by and as seems fit, these - * can be moved over to being controlled by respective device. - */ - pinctrl-names = "default"; - pinctrl-0 = <&ipgpio_hrefv60_mode>, - <&etm_hrefv60_mode>, - <&nahj_hrefv60_mode>, - <&nfc_hrefv60_mode>, - <&force_hrefv60_mode>, - <&dipro_hrefv60_mode>, - <&vaudio_hf_hrefv60_mode>, - <&gbf_hrefv60_mode>, - <&hdtv_hrefv60_mode>, - <&gpios_hrefv60_mode>; - - sdi0 { - sdi0_default_mode: sdi0_default { - /* SD card detect GPIO pin, extend default state */ - default_hrefv60_cfg1 { - pins = "GPIO95_E8"; - ste,config = <&gpio_in_pu>; - }; - /* VMMCI level-shifter enable */ - default_hrefv60_cfg2 { - pins = "GPIO169_D22"; - ste,config = <&gpio_out_hi>; - }; - /* VMMCI level-shifter voltage select */ - default_hrefv60_cfg3 { - pins = "GPIO5_AG6"; - ste,config = <&gpio_out_hi>; - }; - }; - }; - ipgpio { - /* - * XENON Flashgun on image processor GPIO (controlled from image - * processor firmware), mux in these image processor GPIO lines 0 - * (XENON_FLASH_ID), 1 (XENON_READY) and there is an assistant - * LED on IP GPIO 4 (XENON_EN2) on altfunction C, that need bias - * from GPIO21 so pull up 0, 1 and drive 4 and GPIO21 low as output. - */ - ipgpio_hrefv60_mode: ipgpio_hrefv60 { - hrefv60_mux { - function = "ipgpio"; - groups = "ipgpio0_c_1", "ipgpio1_c_1", "ipgpio4_c_1"; - }; - hrefv60_cfg1 { - pins = "GPIO6_AF6", "GPIO7_AG5"; - ste,config = <&in_pu>; - }; - hrefv60_cfg2 { - pins = "GPIO21_AB3"; - ste,config = <&gpio_out_lo>; - }; - hrefv60_cfg3 { - pins = "GPIO64_F3"; - ste,config = <&out_lo>; - }; - }; - }; - etm { - /* - * Drive D19-D23 for the ETM PTM trace interface low, - * (presumably pins are unconnected therefore grounded here, - * the "other alt C1" setting enables these pins) - */ - etm_hrefv60_mode: etm_hrefv60 { - hrefv60_cfg1 { - pins = - "GPIO70_G5", - "GPIO71_G4", - "GPIO72_H4", - "GPIO73_H3", - "GPIO74_J3"; - ste,config = <&gpio_out_lo>; - }; - }; - }; - nahj { - nahj_hrefv60_mode: nahj_hrefv60 { - /* NAHJ CTRL on GPIO76 to low, CTRL_INV on GPIO216 to high */ - hrefv60_cfg1 { - pins = "GPIO76_J2"; - ste,config = <&gpio_out_lo>; - }; - hrefv60_cfg2 { - pins = "GPIO216_AG12"; - ste,config = <&gpio_out_hi>; - }; - }; - }; - nfc { - nfc_hrefv60_mode: nfc_hrefv60 { - /* NFC ENA and RESET to low, pulldown IRQ line */ - hrefv60_cfg1 { - pins = - "GPIO77_H1", /* NFC_ENA */ - "GPIO142_C11"; /* NFC_RESET */ - ste,config = <&gpio_out_lo>; - }; - hrefv60_cfg2 { - pins = "GPIO144_B13"; /* NFC_IRQ */ - ste,config = <&gpio_in_pd>; - }; - }; - }; - force { - force_hrefv60_mode: force_hrefv60 { - hrefv60_cfg1 { - pins = "GPIO91_B6"; /* FORCE_SENSING_INT */ - ste,config = <&gpio_in_pu>; - }; - hrefv60_cfg2 { - pins = - "GPIO92_D6", /* FORCE_SENSING_RST */ - "GPIO97_D9"; /* FORCE_SENSING_WU */ - ste,config = <&gpio_out_lo>; - }; - }; - }; - dipro { - dipro_hrefv60_mode: dipro_hrefv60 { - hrefv60_cfg1 { - pins = "GPIO139_C9"; /* DIPRO_INT */ - ste,config = <&gpio_in_pu>; - }; - }; - }; - vaudio_hf { - vaudio_hf_hrefv60_mode: vaudio_hf_hrefv60 { - /* Audio Amplifier HF enable GPIO */ - hrefv60_cfg1 { - pins = "GPIO149_B14"; /* VAUDIO_HF_EN, enable MAX8968 */ - ste,config = <&gpio_out_hi>; - }; - }; - }; - gbf { - gbf_hrefv60_mode: gbf_hrefv60 { - /* - * GBF (GPS, Bluetooth, FM-radio) interface, - * pull low to reset state - */ - hrefv60_cfg1 { - pins = "GPIO171_D23"; /* GBF_ENA_RESET */ - ste,config = <&gpio_out_lo>; - }; - }; - }; - hdtv { - hdtv_hrefv60_mode: hdtv_hrefv60 { - /* MSP : HDTV INTERFACE GPIO line */ - hrefv60_cfg1 { - pins = "GPIO192_AJ27"; - ste,config = <&gpio_in_pd>; - }; - }; - }; - mcde { - lcd_hrefv60_mode: lcd_hrefv60 { - /* - * Display Interface 1 uses GPIO 65 for RST (reset). - * Display Interface 2 uses GPIO 66 for RST (reset). - * Drive DISP1 reset high (not reset), driver DISP2 reset low (reset) - */ - hrefv60_cfg1 { - pins ="GPIO65_F1"; - ste,config = <&gpio_out_hi>; - }; - hrefv60_cfg2 { - pins ="GPIO66_G3"; - ste,config = <&gpio_out_lo>; - }; - }; - }; - gpios { - /* Dangling GPIO pins */ - gpios_hrefv60_mode: gpios_hrefv60 { - default_cfg1 { - /* Normally UART1 RXD, now dangling */ - pins = "GPIO4_AH6"; - ste,config = <&in_pu>; - }; - }; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/ste-nomadik-nhk15.dts b/sys/gnu/dts/arm/ste-nomadik-nhk15.dts deleted file mode 100644 index 41ed21a4fdc..00000000000 --- a/sys/gnu/dts/arm/ste-nomadik-nhk15.dts +++ /dev/null @@ -1,266 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree for the ST Microelectronics Nomadik NHK8815 board - */ - -/dts-v1/; -#include -#include -#include "ste-nomadik-stn8815.dtsi" - -/ { - model = "Nomadik STN8815NHK"; - compatible = "st,nomadik-nhk-15"; - - chosen { - bootargs = "root=/dev/ram0 console=ttyAMA1,115200n8 earlyprintk"; - }; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - stmpe-i2c0 = &stmpe0; - stmpe-i2c1 = &stmpe1; - }; - - pinctrl { - uart0 { - uart0_nhk_mode: uart0_mux { - u0_default_mux { - function = "u0"; - groups = "u0txrx_a_1", "u0ctsrts_a_1"; - }; - }; - }; - - stmpe2401_1 { - stmpe2401_1_nhk_mode: stmpe2401_1_nhk { - nhk_cfg1 { - pins = "GPIO76_B20"; // IRQ line - ste,input = <0>; - }; - nhk_cfg2 { - pins = "GPIO77_B8"; // reset line - ste,output = <1>; - }; - }; - }; - stmpe2401_2 { - stmpe2401_2_nhk_mode: stmpe2401_2_nhk { - nhk_cfg1 { - pins = "GPIO78_A8"; // IRQ line - ste,input = <0>; - }; - nhk_cfg2 { - pins = "GPIO79_C9"; // reset line - ste,output = <1>; - }; - }; - }; - lis3lv02dl { - lis3lv02dl_nhk_mode: lis3lv02dl_nhk { - nhk_cfg1 { - pins = "GPIO82_C10"; // IRQ line - ste,input = <0>; - }; - }; - }; - }; - src@101e0000 { - /* These chrystal outputs are not used on this board */ - disable-sxtalo; - disable-mxtalo; - }; - - /* This is where the interrupt is routed on the NHK-15 debug board */ - external-bus@34000000 { - compatible = "simple-bus"; - reg = <0x34000000 0x1000000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x34000000 0x1000000>; - ethernet@300 { - compatible = "smsc,lan91c111"; - reg = <0x300 0x0fd00>; - reg-io-width = <2>; - reset-gpios = <&stmpe_gpio44 10 GPIO_ACTIVE_HIGH>; - interrupt-parent = <&stmpe_gpio44>; - interrupts = <11 IRQ_TYPE_EDGE_RISING>; - }; - }; - - i2c0 { - lis3lv02dl@1d { - /* Accelerometer */ - compatible = "st,lis3lv02dl-accel"; - interrupt-parent = <&gpio2>; - interrupts = <18 IRQ_TYPE_EDGE_RISING>; // GPIO 82 - pinctrl-0 = <&lis3lv02dl_nhk_mode>; - pinctrl-names = "default"; - reg = <0x1d>; - }; - stmpe0: stmpe2401@43 { - compatible = "st,stmpe2401"; - reg = <0x43>; - reset-gpios = <&gpio2 13 GPIO_ACTIVE_LOW>; // GPIO77 - interrupts = <12 IRQ_TYPE_EDGE_FALLING>; // GPIO76 - interrupt-parent = <&gpio2>; - interrupt-controller; - wakeup-source; - pinctrl-names = "default"; - pinctrl-0 = <&stmpe2401_1_nhk_mode>; - stmpe_gpio43: stmpe_gpio { - compatible = "st,stmpe-gpio"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - /* Some pins in alternate functions */ - st,norequest-mask = <0xf0f002>; - }; - stmpe_keypad { - compatible = "st,stmpe-keypad"; - debounce-interval = <64>; - st,scan-count = <8>; - st,no-autorepeat; - keypad,num-rows = <8>; - keypad,num-columns = <8>; - linux,keymap = <0x00020072 // Vol down - 0x00030073 // Vol up - 0x0100009e // Back - 0x010100e3 // TV out - 0x01020098 // Lock - 0x0103013b // Start - 0x020000a3 // Next - 0x020100a4 // Play - 0x020200a5 // Prev - 0x02030160 // OK - 0x03000069 // Left - 0x0301006a // Right - 0x03020067 // Up - 0x0303006c>; // Down - }; - stmpe0_pwm: stmpe_pwm { - compatible = "st,stmpe-pwm"; - #pwm-cells = <2>; - }; - }; - stmpe1: stmpe2401@44 { - compatible = "st,stmpe2401"; - reg = <0x44>; - reset-gpios = <&gpio2 15 GPIO_ACTIVE_LOW>; // GPIO79 - interrupts = <14 IRQ_TYPE_EDGE_FALLING>; // GPIO78 - interrupt-parent = <&gpio2>; - interrupt-controller; - wakeup-source; - pinctrl-names = "default"; - pinctrl-0 = <&stmpe2401_2_nhk_mode>; - stmpe_gpio44: stmpe_gpio { - compatible = "st,stmpe-gpio"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - /* - * This will turn off SATA so that MMC/SD - * can thrive - */ - mmcsd-gpio { - gpio-hog; - gpios = <2 0x0>; - output-low; - line-name = "SATA EN"; - }; - }; - }; - }; - - amba { - clcd@10120000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&clcd_24bit_mux>; - port { - nomadik_clcd: endpoint { - remote-endpoint = <&nomadik_clcd_panel>; - arm,pl11x,tft-r0g0b0-pads = <16 8 0>; - }; - }; - - }; - - /* Activate RX/TX and CTS/RTS on UART 0 */ - uart0: uart@101fd000 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_nhk_mode>; - status = "okay"; - }; - mmcsd: sdi@101f6000 { - cd-gpios = <&stmpe_gpio44 7 GPIO_ACTIVE_LOW>; - wp-gpios = <&stmpe_gpio44 18 GPIO_ACTIVE_HIGH>; - }; - }; - - spi { - compatible = "spi-gpio"; - #address-cells = <1>; - #size-cells = <0>; - - /* - * As we're dealing with 3wire SPI, we only define SCK - * and MOSI (in the spec MOSI is called "SDA"). - */ - gpio-sck = <&gpio0 5 GPIO_ACTIVE_HIGH>; - gpio-mosi = <&gpio0 4 GPIO_ACTIVE_HIGH>; - cs-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; - num-chipselects = <1>; - - /* - * WVGA connector 21 - * WVGA (800x480): 4.3" TPG110 TDO43MTEA2 24-bit RGB - * with TPO touch screen. - */ - panel: display@0 { - /* - * The TPO display driver is connected to a - * 5.7" OSD OSD057VA01CT TFT display. - */ - compatible = "tpo,tpg110"; - reg = <0>; - spi-3wire; - /* 320 ns min period ~= 3 MHz */ - spi-max-frequency = <3000000>; - /* Width and height from the OSD data sheet */ - width-mm = <116>; - height-mm = <87>; - grestb-gpios = <&stmpe_gpio44 5 GPIO_ACTIVE_LOW>; - backlight = <&bl>; - - port { - nomadik_clcd_panel: endpoint { - remote-endpoint = <&nomadik_clcd>; - }; - }; - }; - }; - - bl: backlight { - compatible = "pwm-backlight"; - pwms = <&stmpe0_pwm 0 500000>; - pwm-names = "backlight"; - brightness-levels = < - 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100 - >; - default-brightness-level = <100>; - }; -}; diff --git a/sys/gnu/dts/arm/ste-nomadik-pinctrl.dtsi b/sys/gnu/dts/arm/ste-nomadik-pinctrl.dtsi deleted file mode 100644 index bfdb5d9a014..00000000000 --- a/sys/gnu/dts/arm/ste-nomadik-pinctrl.dtsi +++ /dev/null @@ -1,174 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2012 ST-Ericsson - */ -#include - -/ { - in_nopull: in_nopull { - ste,input = ; - }; - - in_pu: input_pull_up { - ste,input = ; - }; - - in_pd: input_pull_down { - ste,input = ; - }; - - out_hi: output_high { - ste,output = ; - }; - - out_lo: output_low { - ste,output = ; - }; - - gpio_in_nopull: gpio_input_nopull { - ste,gpio = ; - ste,input = ; - }; - - gpio_in_pu: gpio_input_pull_up { - ste,gpio = ; - ste,input = ; - }; - - gpio_in_pd: gpio_input_pull_down { - ste,gpio = ; - ste,input = ; - }; - - gpio_out_lo: gpio_output_low { - ste,gpio = ; - ste,output = ; - }; - - gpio_out_hi: gpio_output_high { - ste,gpio = ; - ste,output = ; - }; - - slpm_pdis: slpm_pdis { - ste,sleep = ; - ste,sleep-wakeup = ; - ste,sleep-pull-disable = ; - }; - - slpm_wkup_pdis: slpm_wkup_pdis { - ste,sleep = ; - ste,sleep-wakeup = ; - ste,sleep-pull-disable = ; - }; - - slpm_wkup_pdis_en: slpm_wkup_pdis_en { - ste,sleep = ; - ste,sleep-wakeup = ; - ste,sleep-pull-disable = ; - }; - - slpm_in_pu: slpm_in_pu { - ste,sleep = ; - ste,sleep-input = ; - ste,sleep-wakeup = ; - }; - - slpm_in_pdis: slpm_in_pdis { - ste,sleep = ; - ste,sleep-input = ; - ste,sleep-wakeup = ; - ste,sleep-pull-disable = ; - }; - - slpm_in_wkup_pdis: slpm_in_wkup_pdis { - ste,sleep = ; - ste,sleep-input = ; - ste,sleep-wakeup = ; - ste,sleep-pull-disable = ; - }; - - slpm_in_wkup_pdis_en: slpm_in_wkup_pdis_en { - ste,sleep = ; - ste,sleep-input = ; - ste,sleep-wakeup = ; - ste,sleep-pull-disable = ; - }; - - slpm_in_pu_wkup_pdis_en: slpm_in_wkup_pdis_en { - ste,sleep = ; - ste,sleep-input = ; - ste,sleep-wakeup = ; - ste,sleep-pull-disable = ; - }; - - slpm_out_lo: slpm_out_lo { - ste,sleep = ; - ste,sleep-output = ; - ste,sleep-wakeup = ; - }; - - slpm_out_hi: slpm_out_hi { - ste,sleep = ; - ste,sleep-output = ; - ste,sleep-wakeup = ; - }; - - slpm_out_hi_wkup_pdis: slpm_out_hi_wkup_pdis { - ste,sleep = ; - ste,sleep-output = ; - ste,sleep-wakeup = ; - ste,sleep-pull-disable = ; - }; - - slpm_out_lo_pdis: slpm_out_lo_pdis { - ste,sleep = ; - ste,sleep-output = ; - ste,sleep-wakeup = ; - ste,sleep-pull-disable = ; - }; - - slpm_out_lo_wkup_pdis: slpm_out_lo_wkup_pdis { - ste,sleep = ; - ste,sleep-output = ; - ste,sleep-wakeup = ; - ste,sleep-pull-disable = ; - }; - - slpm_out_wkup_pdis: slpm_out_wkup_pdis { - ste,sleep = ; - ste,sleep-output = ; - ste,sleep-wakeup = ; - ste,sleep-pull-disable = ; - }; - - in_wkup_pdis: in_wkup_pdis { - ste,sleep-input = ; - ste,sleep-wakeup = ; - ste,sleep-pull-disable = ; - }; - - in_wkup_pdis_en: in_wkup_pdis_en { - ste,sleep-input = ; - ste,sleep-wakeup = ; - ste,sleep-pull-disable = ; - }; - - out_lo_wkup_pdis: out_lo_wkup_pdis { - ste,sleep-output = ; - ste,sleep-wakeup = ; - ste,sleep-pull-disable = ; - }; - - out_hi_wkup_pdis: out_hi_wkup_pdis { - ste,sleep-output = ; - ste,sleep-wakeup = ; - ste,sleep-pull-disable = ; - }; - - out_wkup_pdis: out_wkup_pdis { - ste,sleep-output = ; - ste,sleep-wakeup = ; - ste,sleep-pull-disable = ; - }; -}; diff --git a/sys/gnu/dts/arm/ste-nomadik-s8815.dts b/sys/gnu/dts/arm/ste-nomadik-s8815.dts deleted file mode 100644 index 4445446fa82..00000000000 --- a/sys/gnu/dts/arm/ste-nomadik-s8815.dts +++ /dev/null @@ -1,172 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree for the ST-Ericsson Nomadik S8815 board - * Produced by Calao Systems - */ - -/dts-v1/; -#include -#include "ste-nomadik-stn8815.dtsi" - -/ { - model = "Calao Systems USB-S8815"; - compatible = "calaosystems,usb-s8815"; - - chosen { - bootargs = "root=/dev/ram0 console=ttyAMA1,115200n8 earlyprintk"; - }; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - }; - - gpio3: gpio@101e7000 { - /* This hog will bias the MMC/SD card detect line */ - mmcsd-gpio { - gpio-hog; - gpios = <16 0x0>; - output-low; - line-name = "card detect bias"; - }; - }; - - src@101e0000 { - /* These chrystal drivers are not used on this board */ - disable-sxtalo; - disable-mxtalo; - }; - - pinctrl { - /* Hog CD pins */ - pinctrl-names = "default"; - pinctrl-0 = <&cd_default_mode>; - - uart0 { - /* Only use RX/TX pins */ - uart0_s8815_mode: uart0_mux { - u0_default_mux { - function = "u0"; - groups = "u0txrx_a_1"; - }; - }; - }; - mmcsd-cd { - cd_default_mode: cd_default { - cd_default_cfg1 { - /* CD input GPIO */ - pins = "GPIO111_H21"; - ste,input = <0>; - }; - cd_default_cfg2 { - /* CD GPIO biasing */ - pins = "GPIO112_J21"; - ste,output = <0>; - }; - }; - }; - gpioi2c { - gpioi2c_default_mode: gpioi2c_default { - gpioi2c_default_cfg { - pins = "GPIO73_C21", "GPIO74_C20"; - ste,input = <0>; - }; - }; - }; - user-led { - user_led_default_mode: user_led_default { - user_led_default_cfg { - pins = "GPIO2_C5"; - ste,output = <1>; - }; - }; - }; - user-button { - user_button_default_mode: user_button_default { - user_button_default_cfg { - pins = "GPIO3_A4"; - ste,input = <0>; - }; - }; - }; - }; - - /* Ethernet */ - external-bus@34000000 { - compatible = "simple-bus"; - reg = <0x34000000 0x1000000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x34000000 0x1000000>; - ethernet@300 { - compatible = "smsc,lan91c111"; - reg = <0x300 0x0fd00>; - interrupt-parent = <&gpio3>; - interrupts = <8 IRQ_TYPE_EDGE_RISING>; - }; - }; - - i2c1 { - lis3lv02dl@1d { - /* Accelerometer */ - compatible = "st,lis3lv02dl-accel"; - reg = <0x1d>; - }; - }; - - /* GPIO I2C connected to the USB portions of the STw4811 only */ - gpio-i2c { - compatible = "i2c-gpio"; - gpios = <&gpio2 10 0>, /* sda */ - <&gpio2 9 0>; /* scl */ - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&gpioi2c_default_mode>; - - stw4811@2d { - compatible = "st,stw4811-usb"; - reg = <0x2d>; - }; - }; - - - amba { - /* Activate RXTX on UART 0 */ - uart0: uart@101fd000 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_s8815_mode>; - status = "okay"; - }; - /* Configure card detect for the uSD slot */ - mmcsd: sdi@101f6000 { - cd-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>; - }; - }; - - /* The user LED on the board is set up to be used for heartbeat */ - leds { - compatible = "gpio-leds"; - user-led { - label = "user_led"; - gpios = <&gpio0 2 0x1>; - default-state = "off"; - linux,default-trigger = "heartbeat"; - pinctrl-names = "default"; - pinctrl-0 = <&user_led_default_mode>; - }; - }; - - /* User key mapped in as "escape" */ - gpio-keys { - compatible = "gpio-keys"; - user-button { - label = "user_button"; - gpios = <&gpio0 3 0x1>; - linux,code = <1>; /* KEY_ESC */ - wakeup-source; - pinctrl-names = "default"; - pinctrl-0 = <&user_button_default_mode>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/ste-nomadik-stn8815.dtsi b/sys/gnu/dts/arm/ste-nomadik-stn8815.dtsi deleted file mode 100644 index f78b4eabd68..00000000000 --- a/sys/gnu/dts/arm/ste-nomadik-stn8815.dtsi +++ /dev/null @@ -1,884 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree for the ST-Ericsson Nomadik 8815 STn8815 SoC - */ - -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - - memory { - device_type = "memory"; - reg = <0x00000000 0x04000000>, - <0x08000000 0x04000000>; - }; - - L2: l2-cache { - compatible = "arm,l210-cache"; - reg = <0x10210000 0x1000>; - interrupt-parent = <&vica>; - interrupts = <30>; - cache-unified; - cache-level = <2>; - cache-size = <131072>; - cache-sets = <512>; - cache-line-size = <32>; - /* At full speed latency must be >=2 */ - arm,tag-latency = <8>; - arm,data-latency = <8 8>; - arm,dirty-latency = <8>; - }; - - mtu0: mtu@101e2000 { - /* Nomadik system timer */ - compatible = "st,nomadik-mtu"; - reg = <0x101e2000 0x1000>; - interrupt-parent = <&vica>; - interrupts = <4>; - clocks = <&timclk>, <&pclk>; - clock-names = "timclk", "apb_pclk"; - }; - - mtu1: mtu@101e3000 { - /* Secondary timer */ - reg = <0x101e3000 0x1000>; - interrupt-parent = <&vica>; - interrupts = <5>; - clocks = <&timclk>, <&pclk>; - clock-names = "timclk", "apb_pclk"; - }; - - gpio0: gpio@101e4000 { - compatible = "st,nomadik-gpio"; - reg = <0x101e4000 0x80>; - interrupt-parent = <&vica>; - interrupts = <6>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - gpio-bank = <0>; - gpio-ranges = <&pinctrl 0 0 32>; - clocks = <&pclk>; - }; - - gpio1: gpio@101e5000 { - compatible = "st,nomadik-gpio"; - reg = <0x101e5000 0x80>; - interrupt-parent = <&vica>; - interrupts = <7>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - gpio-bank = <1>; - gpio-ranges = <&pinctrl 0 32 32>; - clocks = <&pclk>; - }; - - gpio2: gpio@101e6000 { - compatible = "st,nomadik-gpio"; - reg = <0x101e6000 0x80>; - interrupt-parent = <&vica>; - interrupts = <8>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - gpio-bank = <2>; - gpio-ranges = <&pinctrl 0 64 32>; - clocks = <&pclk>; - }; - - gpio3: gpio@101e7000 { - compatible = "st,nomadik-gpio"; - reg = <0x101e7000 0x80>; - ngpio = <28>; - interrupt-parent = <&vica>; - interrupts = <9>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - gpio-bank = <3>; - gpio-ranges = <&pinctrl 0 96 28>; - clocks = <&pclk>; - }; - - pinctrl: pinctrl { - compatible = "stericsson,stn8815-pinctrl"; - nomadik-gpio-chips = <&gpio0>, <&gpio1>, <&gpio2>, <&gpio3>; - /* Pin configurations */ - uart1 { - uart1_default_mux: uart1_mux { - u1_default_mux { - function = "u1"; - groups = "u1_a_1"; - }; - }; - }; - mmcsd { - mmcsd_default_mux: mmcsd_mux { - mmcsd_default_mux { - function = "mmcsd"; - groups = "mmcsd_a_1", "mmcsd_b_1"; - }; - }; - mmcsd_default_mode: mmcsd_default { - mmcsd_default_cfg1 { - /* - * MCCLK, MCCMDDIR, MCDAT0DIR, MCDAT31DIR, MCDATDIR2 - * MCCMD, MCDAT3-0, MCMSFBCLK - */ - pins = "GPIO8_B10", "GPIO9_A10", "GPIO10_C11", "GPIO11_B11", - "GPIO12_A11", "GPIO13_C12", "GPIO14_B12", "GPIO15_A12", - "GPIO16_C13", "GPIO23_D15", "GPIO24_C15"; - ste,output = <2>; - }; - }; - }; - i2c0 { - i2c0_default_mux: i2c0_mux { - i2c0_default_mux { - function = "i2c0"; - groups = "i2c0_a_1"; - }; - }; - i2c0_default_mode: i2c0_default { - i2c0_default_cfg { - pins = "GPIO62_D3", "GPIO63_D2"; - ste,input = <0>; - }; - }; - }; - i2c1 { - i2c1_default_mux: i2c1_mux { - i2c1_default_mux { - function = "i2c1"; - groups = "i2c1_a_1"; - }; - }; - i2c1_default_mode: i2c1_default { - i2c1_default_cfg { - pins = "GPIO53_L4", "GPIO54_L3"; - ste,input = <0>; - }; - }; - }; - clcd { - /* - * This should be activated to use the additional - * 8 lines for bits 16 thru 23 from the CLCD block. - */ - clcd_24bit_mux: clcd_mux { - clcd_24bit_mux { - function = "clcd"; - groups = "clcd_16_23_b_1"; - }; - }; - }; - }; - - /* Power Management Unit */ - pmu: pmu@101e9000 { - compatible = "stericsson,nomadik-pmu", "syscon"; - reg = <0x101e0000 0x1000>; - }; - - src: src@101e0000 { - compatible = "stericsson,nomadik-src"; - reg = <0x101e0000 0x1000>; - - /* - * MXTAL "Main Chrystal" is a chrystal oscillator @19.2 MHz - * that is parent of TIMCLK, PLL1 and PLL2 - */ - mxtal: mxtal@19.2M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <19200000>; - }; - - /* - * The 2.4 MHz TIMCLK reference clock is active at - * boot time, this is actually the MXTALCLK @19.2 MHz - * divided by 8. This clock is used by the timers and - * watchdog. See page 105 ff. - */ - timclk: timclk@2.4M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <8>; - clock-mult = <1>; - clocks = <&mxtal>; - }; - - /* PLL1 is locked to MXTALI and variable from 20.4 to 334 MHz */ - pll1: pll1@0 { - #clock-cells = <0>; - compatible = "st,nomadik-pll-clock"; - pll-id = <1>; - clocks = <&mxtal>; - }; - - /* HCLK divides the PLL1 with 1,2,3 or 4 */ - hclk: hclk@0 { - #clock-cells = <0>; - compatible = "st,nomadik-hclk-clock"; - clocks = <&pll1>; - }; - /* The PCLK domain uses HCLK right off */ - pclk: pclk@0 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&hclk>; - }; - - /* PLL2 is usually 864 MHz and divided into a few fixed rates */ - pll2: pll2@0 { - #clock-cells = <0>; - compatible = "st,nomadik-pll-clock"; - pll-id = <2>; - clocks = <&mxtal>; - }; - clk216: clk216@216M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <4>; - clock-mult = <1>; - clocks = <&pll2>; - }; - clk108: clk108@108M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <2>; - clock-mult = <1>; - clocks = <&clk216>; - }; - clk72: clk72@72M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - /* The data sheet does not say how this is derived */ - clock-div = <12>; - clock-mult = <1>; - clocks = <&pll2>; - }; - clk48: clk48@48M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - /* The data sheet does not say how this is derived */ - clock-div = <18>; - clock-mult = <1>; - clocks = <&pll2>; - }; - clk27: clk27@27M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <4>; - clock-mult = <1>; - clocks = <&clk108>; - }; - - /* This apparently exists as well */ - ulpiclk: ulpiclk@60M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <60000000>; - }; - - /* - * IP AMBA bus clocks, driving the bus side of the - * peripheral clocking, clock gates. - */ - - hclkdma0: hclkdma0@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <0>; - clocks = <&hclk>; - }; - hclksmc: hclksmc@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <1>; - clocks = <&hclk>; - }; - hclksdram: hclksdram@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <2>; - clocks = <&hclk>; - }; - hclkdma1: hclkdma1@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <3>; - clocks = <&hclk>; - }; - hclkclcd: hclkclcd@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <4>; - clocks = <&hclk>; - }; - pclkirda: pclkirda@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <5>; - clocks = <&pclk>; - }; - pclkssp: pclkssp@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <6>; - clocks = <&pclk>; - }; - pclkuart0: pclkuart0@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <7>; - clocks = <&pclk>; - }; - pclksdi: pclksdi@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <8>; - clocks = <&pclk>; - }; - pclki2c0: pclki2c0@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <9>; - clocks = <&pclk>; - }; - pclki2c1: pclki2c1@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <10>; - clocks = <&pclk>; - }; - pclkuart1: pclkuart1@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <11>; - clocks = <&pclk>; - }; - pclkmsp0: pclkmsp0@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <12>; - clocks = <&pclk>; - }; - hclkusb: hclkusb@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <13>; - clocks = <&hclk>; - }; - hclkdif: hclkdif@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <14>; - clocks = <&hclk>; - }; - hclksaa: hclksaa@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <15>; - clocks = <&hclk>; - }; - hclksva: hclksva@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <16>; - clocks = <&hclk>; - }; - pclkhsi: pclkhsi@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <17>; - clocks = <&pclk>; - }; - pclkxti: pclkxti@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <18>; - clocks = <&pclk>; - }; - pclkuart2: pclkuart2@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <19>; - clocks = <&pclk>; - }; - pclkmsp1: pclkmsp1@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <20>; - clocks = <&pclk>; - }; - pclkmsp2: pclkmsp2@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <21>; - clocks = <&pclk>; - }; - pclkowm: pclkowm@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <22>; - clocks = <&pclk>; - }; - hclkhpi: hclkhpi@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <23>; - clocks = <&hclk>; - }; - pclkske: pclkske@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <24>; - clocks = <&pclk>; - }; - pclkhsem: pclkhsem@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <25>; - clocks = <&pclk>; - }; - hclk3d: hclk3d@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <26>; - clocks = <&hclk>; - }; - hclkhash: hclkhash@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <27>; - clocks = <&hclk>; - }; - hclkcryp: hclkcryp@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <28>; - clocks = <&hclk>; - }; - pclkmshc: pclkmshc@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <29>; - clocks = <&pclk>; - }; - hclkusbm: hclkusbm@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <30>; - clocks = <&hclk>; - }; - hclkrng: hclkrng@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <31>; - clocks = <&hclk>; - }; - - /* IP kernel clocks */ - clcdclk: clcdclk@0 { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <36>; - clocks = <&clk72 &clk48>; - }; - irdaclk: irdaclk@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <37>; - clocks = <&clk48>; - }; - sspiclk: sspiclk@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <38>; - clocks = <&clk48>; - }; - uart0clk: uart0clk@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <39>; - clocks = <&clk48>; - }; - sdiclk: sdiclk@48M { - /* Also called MCCLK in some documents */ - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <40>; - clocks = <&clk48>; - }; - i2c0clk: i2c0clk@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <41>; - clocks = <&clk48>; - }; - i2c1clk: i2c1clk@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <42>; - clocks = <&clk48>; - }; - uart1clk: uart1clk@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <43>; - clocks = <&clk48>; - }; - mspclk0: mspclk0@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <44>; - clocks = <&clk48>; - }; - usbclk: usbclk@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <45>; - clocks = <&clk48>; /* 48 MHz not ULPI */ - }; - difclk: difclk@72M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <46>; - clocks = <&clk72>; - }; - ipi2cclk: ipi2cclk@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <47>; - clocks = <&clk48>; /* Guess */ - }; - ipbmcclk: ipbmcclk@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <48>; - clocks = <&clk48>; /* Guess */ - }; - hsiclkrx: hsiclkrx@216M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <49>; - clocks = <&clk216>; - }; - hsiclktx: hsiclktx@108M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <50>; - clocks = <&clk108>; - }; - uart2clk: uart2clk@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <51>; - clocks = <&clk48>; - }; - mspclk1: mspclk1@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <52>; - clocks = <&clk48>; - }; - mspclk2: mspclk2@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <53>; - clocks = <&clk48>; - }; - owmclk: owmclk@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <54>; - clocks = <&clk48>; /* Guess */ - }; - skeclk: skeclk@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <56>; - clocks = <&clk48>; /* Guess */ - }; - x3dclk: x3dclk@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <58>; - clocks = <&clk48>; /* Guess */ - }; - pclkmsp3: pclkmsp3@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <59>; - clocks = <&pclk>; - }; - mspclk3: mspclk3@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <60>; - clocks = <&clk48>; - }; - mshcclk: mshcclk@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <61>; - clocks = <&clk48>; /* Guess */ - }; - usbmclk: usbmclk@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <62>; - /* Stated as "48 MHz not ULPI clock" */ - clocks = <&clk48>; - }; - rngcclk: rngcclk@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <63>; - clocks = <&clk48>; /* Guess */ - }; - }; - - /* A NAND flash of 128 MiB */ - fsmc: flash@40000000 { - compatible = "stericsson,fsmc-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x10100000 0x1000>, /* FSMC Register*/ - <0x40000000 0x2000>, /* NAND Base DATA */ - <0x41000000 0x2000>, /* NAND Base ADDR */ - <0x40800000 0x2000>; /* NAND Base CMD */ - reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd"; - clocks = <&hclksmc>; - status = "okay"; - - partition@0 { - label = "X-Loader(NAND)"; - reg = <0x0 0x40000>; - }; - partition@40000 { - label = "MemInit(NAND)"; - reg = <0x40000 0x40000>; - }; - partition@80000 { - label = "BootLoader(NAND)"; - reg = <0x80000 0x200000>; - }; - partition@280000 { - label = "Kernel zImage(NAND)"; - reg = <0x280000 0x300000>; - }; - partition@580000 { - label = "Root Filesystem(NAND)"; - reg = <0x580000 0x1600000>; - }; - partition@1b80000 { - label = "User Filesystem(NAND)"; - reg = <0x1b80000 0x6480000>; - }; - }; - - /* I2C0 connected to the STw4811 power management chip */ - i2c0 { - compatible = "st,nomadik-i2c", "arm,primecell"; - reg = <0x101f8000 0x1000>; - interrupt-parent = <&vica>; - interrupts = <20>; - clock-frequency = <100000>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&i2c0clk>, <&pclki2c0>; - clock-names = "mclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_default_mux>, <&i2c0_default_mode>; - - stw4811@2d { - compatible = "st,stw4811"; - reg = <0x2d>; - vmmc_regulator: vmmc { - compatible = "st,stw481x-vmmc"; - regulator-name = "VMMC"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - }; - }; - - /* I2C1 connected to various sensors */ - i2c1 { - compatible = "st,nomadik-i2c", "arm,primecell"; - reg = <0x101f7000 0x1000>; - interrupt-parent = <&vica>; - interrupts = <21>; - clock-frequency = <100000>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&i2c1clk>, <&pclki2c1>; - clock-names = "mclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_default_mux>, <&i2c1_default_mode>; - - camera@2d { - compatible = "st,camera"; - reg = <0x10>; - }; - stw5095@1a { - compatible = "st,stw5095"; - reg = <0x1a>; - }; - }; - - amba { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - clcd@10120000 { - compatible = "arm,pl110", "arm,primecell"; - reg = <0x10120000 0x1000>; - interrupt-names = "combined"; - interrupts = <14>; - interrupt-parent = <&vica>; - clocks = <&clcdclk>, <&hclkclcd>; - clock-names = "clcdclk", "apb_pclk"; - status = "disabled"; - }; - - vica: intc@10140000 { - compatible = "arm,versatile-vic"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x10140000 0x20>; - }; - - vicb: intc@10140020 { - compatible = "arm,versatile-vic"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x10140020 0x20>; - }; - - uart0: uart@101fd000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x101fd000 0x1000>; - interrupt-parent = <&vica>; - interrupts = <12>; - clocks = <&uart0clk>, <&pclkuart0>; - clock-names = "uartclk", "apb_pclk"; - status = "disabled"; - dmas = <&dmac0 14 1>, - <&dmac0 15 1>; - dma-names = "rx", "tx"; - }; - - uart1: uart@101fb000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x101fb000 0x1000>; - interrupt-parent = <&vica>; - interrupts = <17>; - clocks = <&uart1clk>, <&pclkuart1>; - clock-names = "uartclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart1_default_mux>; - dmas = <&dmac1 22 1>, - <&dmac1 23 1>; - dma-names = "rx", "tx"; - }; - - uart2: uart@101f2000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x101f2000 0x1000>; - interrupt-parent = <&vica>; - interrupts = <28>; - clocks = <&uart2clk>, <&pclkuart2>; - clock-names = "uartclk", "apb_pclk"; - status = "disabled"; - dmas = <&dmac1 30 1>, - <&dmac1 31 1>; - dma-names = "rx", "tx"; - }; - - rng: rng@101b0000 { - compatible = "arm,primecell"; - reg = <0x101b0000 0x1000>; - clocks = <&rngcclk>, <&hclkrng>; - clock-names = "rng", "apb_pclk"; - }; - - rtc: rtc@101e8000 { - compatible = "arm,pl031", "arm,primecell"; - reg = <0x101e8000 0x1000>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - interrupt-parent = <&vica>; - interrupts = <10>; - }; - - mmcsd: sdi@101f6000 { - compatible = "arm,pl18x", "arm,primecell"; - reg = <0x101f6000 0x1000>; - clocks = <&sdiclk>, <&pclksdi>; - clock-names = "mclk", "apb_pclk"; - interrupt-parent = <&vica>; - interrupts = <22>; - max-frequency = <400000>; - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - full-pwr-cycle; - /* - * The STw4811 circuit used with the Nomadik strictly - * requires that all of these signal direction pins be - * routed and used for its 4-bit levelshifter. - */ - st,sig-dir-dat0; - st,sig-dir-dat2; - st,sig-dir-dat31; - st,sig-dir-cmd; - st,sig-pin-fbclk; - pinctrl-names = "default"; - pinctrl-0 = <&mmcsd_default_mux>, <&mmcsd_default_mode>; - vmmc-supply = <&vmmc_regulator>; - }; - - dmac0: dma-controller@10130000 { - compatible = "arm,pl080", "arm,primecell"; - reg = <0x10130000 0x1000>; - interrupt-parent = <&vica>; - interrupts = <15>; - clocks = <&hclkdma0>; - clock-names = "apb_pclk"; - lli-bus-interface-ahb1; - lli-bus-interface-ahb2; - mem-bus-interface-ahb2; - memcpy-burst-size = <256>; - memcpy-bus-width = <32>; - #dma-cells = <2>; - }; - dmac1: dma-controller@10150000 { - compatible = "arm,pl080", "arm,primecell"; - reg = <0x10150000 0x1000>; - interrupt-parent = <&vica>; - interrupts = <13>; - clocks = <&hclkdma1>; - clock-names = "apb_pclk"; - lli-bus-interface-ahb1; - lli-bus-interface-ahb2; - mem-bus-interface-ahb2; - memcpy-burst-size = <256>; - memcpy-bus-width = <32>; - #dma-cells = <2>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/ste-snowball.dts b/sys/gnu/dts/arm/ste-snowball.dts deleted file mode 100644 index be90e73c923..00000000000 --- a/sys/gnu/dts/arm/ste-snowball.dts +++ /dev/null @@ -1,624 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2011 ST-Ericsson AB - */ - -/dts-v1/; -#include "ste-db8500.dtsi" -#include "ste-href-ab8500.dtsi" -#include "ste-href-family-pinctrl.dtsi" - -/ { - model = "Calao Systems Snowball platform with device tree"; - compatible = "calaosystems,snowball-a9500", "st-ericsson,u9500"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x20000000>; - }; - - en_3v3_reg: en_3v3 { - compatible = "regulator-fixed"; - regulator-name = "en-3v3-fixed-supply"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - /* AB8500 GPIOs start from 1 - offset 25 is GPIO26. */ - gpio = <&ab8500_gpio 25 0x4>; - startup-delay-us = <5000>; - enable-active-high; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - button@1 { - debounce-interval = <50>; - wakeup-source; - linux,code = <2>; - label = "userpb"; - gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; - }; - button@2 { - debounce-interval = <50>; - wakeup-source; - linux,code = <3>; - label = "extkb1"; - gpios = <&gpio4 23 GPIO_ACTIVE_HIGH>; - }; - button@3 { - debounce-interval = <50>; - wakeup-source; - linux,code = <4>; - label = "extkb2"; - gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>; - }; - button@4 { - debounce-interval = <50>; - wakeup-source; - linux,code = <5>; - label = "extkb3"; - gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; - }; - button@5 { - debounce-interval = <50>; - wakeup-source; - linux,code = <6>; - label = "extkb4"; - gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&gpioled_snowball_mode>; - used-led { - label = "user_led"; - gpios = <&gpio4 14 GPIO_ACTIVE_HIGH>; - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - }; - - soc { - /* Name the GPIO muxed rails on the Snowball board */ - gpio@8012e000 { - /* GPIOs 0 - 31 */ - gpio-line-names = "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", - "AP_GPIO31"; - }; - - gpio@8012e080 { - /* GPIOs 32 - 63 */ - gpio-line-names = "USR PB", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; - }; - - gpio@8000e000 { - /* GPIOs 64 - 95 */ - gpio-line-names = "", "", "", "", "AP_GPIO68", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; - }; - - gpio@8000e100 { - /* GPIOs 128 - 159 */ - gpio-line-names = "", "", "", "", "", "", "", "", - "", "", "", "", "IRQ_LAN", "RSTn_LAN", - "USR_LED", "", "", "", "", "", "", - "", "", "AP_GPIO151", "AP_GPIO152", - "", "", "", "", "", "", ""; - }; - - gpio@8000e180 { - /* GPIOs 160 - 191 */ - gpio-line-names = "", "AP_GPIO161", "AP_GPIO162", - "ACCELEROMETER_INT1_RDY", - "ACCELEROMETER_INT2", "MAG_DRDY", - "GYRO_DRDY", "RSTn_MLC", "RSTn_SLC", - "GYRO_INT", "UART_WAKE", "GBF_RESET", - "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; - }; - - gpio@8011e000 { - /* GPIOs 192 - 223 */ - gpio-line-names = "HDTV_INTn", "", "", "", "HDTV_RST", - "", "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", "", - "WLAN_RESETN", "WLAN_IRQ", "MMC_EN", - "MMC_CD", "", "", "", "", ""; - }; - - gpio@8011e080 { - /* GPIOs 224 - 255 */ - gpio-line-names = "", "", "", "", "SD_SEL", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; - }; - - msp0: msp@80123000 { - pinctrl-names = "default"; - pinctrl-0 = <&msp0txrxtfstck_a_1_default>; - status = "okay"; - }; - - msp1: msp@80124000 { - pinctrl-names = "default"; - pinctrl-0 = <&msp1txrx_a_1_default>; - status = "okay"; - }; - - msp2: msp@80117000 { - pinctrl-names = "default"; - pinctrl-0 = <&msp2_a_1_default>; - }; - - msp3: msp@80125000 { - status = "okay"; - }; - - external-bus@50000000 { - status = "okay"; - - ethernet@0 { - compatible = "smsc,lan9115"; - reg = <0 0x10000>; - interrupts = <12 IRQ_TYPE_EDGE_RISING>; - interrupt-parent = <&gpio4>; - vdd33a-supply = <&en_3v3_reg>; - vddvario-supply = <&db8500_vape_reg>; - pinctrl-names = "default"; - pinctrl-0 = <ð_snowball_mode>; - - reg-shift = <1>; - reg-io-width = <2>; - smsc,force-internal-phy; - smsc,irq-active-high; - smsc,irq-push-pull; - - clocks = <&prcc_pclk 3 0>; - }; - }; - - /* ST6G3244ME level translator for 1.8/2.9 V */ - vmmci: regulator-gpio { - compatible = "regulator-gpio"; - - /* GPIO228 SD_SEL */ - gpios = <&gpio7 4 GPIO_ACTIVE_HIGH>; - /* GPIO217 MMC_EN */ - enable-gpio = <&gpio6 25 GPIO_ACTIVE_HIGH>; - enable-active-high; - - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2900000>; - regulator-name = "mmci-reg"; - regulator-type = "voltage"; - - startup-delay-us = <100>; - - states = <1800000 0x1 - 2900000 0x0>; - }; - - // External Micro SD slot - sdi0_per1@80126000 { - arm,primecell-periphid = <0x10480180>; - max-frequency = <100000000>; - bus-width = <4>; - cap-sd-highspeed; - cap-mmc-highspeed; - sd-uhs-sdr12; - sd-uhs-sdr25; - /* All direction control is used */ - st,sig-dir-cmd; - st,sig-dir-dat0; - st,sig-dir-dat2; - st,sig-dir-dat31; - st,sig-pin-fbclk; - full-pwr-cycle; - vmmc-supply = <&ab8500_ldo_aux3_reg>; - vqmmc-supply = <&vmmci>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&mc0_a_1_default &sdi0_default_mode>; - pinctrl-1 = <&mc0_a_1_sleep>; - - /* GPIO218 MMC_CD */ - cd-gpios = <&gpio6 26 GPIO_ACTIVE_LOW>; - - status = "okay"; - }; - - // WLAN SDIO channel - sdi1_per2@80118000 { - arm,primecell-periphid = <0x10480180>; - max-frequency = <100000000>; - bus-width = <4>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&mc1_a_1_default>; - pinctrl-1 = <&mc1_a_1_sleep>; - - status = "okay"; - }; - - // Unused PoP eMMC - register and put it to sleep by default */ - sdi2_per3@80005000 { - arm,primecell-periphid = <0x10480180>; - pinctrl-names = "default"; - pinctrl-0 = <&mc2_a_1_sleep>; - - status = "okay"; - }; - - // On-board eMMC - sdi4_per2@80114000 { - arm,primecell-periphid = <0x10480180>; - max-frequency = <100000000>; - bus-width = <8>; - cap-mmc-highspeed; - vmmc-supply = <&ab8500_ldo_aux2_reg>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&mc4_a_1_default>; - pinctrl-1 = <&mc4_a_1_sleep>; - - status = "okay"; - }; - - uart@80120000 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&u0_a_1_default>; - pinctrl-1 = <&u0_a_1_sleep>; - status = "okay"; - }; - - /* This UART is unused and thus left disabled */ - uart@80121000 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&u1rxtx_a_1_default>; - pinctrl-1 = <&u1rxtx_a_1_sleep>; - }; - - uart@80007000 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&u2rxtx_c_1_default>; - pinctrl-1 = <&u2rxtx_c_1_sleep>; - status = "okay"; - }; - - i2c@80004000 { - pinctrl-names = "default","sleep"; - pinctrl-0 = <&i2c0_a_1_default>; - pinctrl-1 = <&i2c0_a_1_sleep>; - status = "okay"; - }; - - i2c@80122000 { - pinctrl-names = "default","sleep"; - pinctrl-0 = <&i2c1_b_2_default>; - pinctrl-1 = <&i2c1_b_2_sleep>; - status = "okay"; - }; - - i2c@80128000 { - pinctrl-names = "default","sleep"; - pinctrl-0 = <&i2c2_b_2_default>; - pinctrl-1 = <&i2c2_b_2_sleep>; - status = "okay"; - lsm303dlh@18 { - /* Accelerometer */ - compatible = "st,lsm303dlh-accel"; - st,drdy-int-pin = <1>; - reg = <0x18>; - vdd-supply = <&ab8500_ldo_aux1_reg>; - vddio-supply = <&db8500_vsmps2_reg>; - pinctrl-names = "default"; - pinctrl-0 = <&accel_snowball_mode>; - interrupt-parent = <&gpio5>; - interrupts = <3 IRQ_TYPE_EDGE_RISING>, /* INT1 */ - <4 IRQ_TYPE_EDGE_RISING>; /* INT2 */ - }; - lsm303dlh@1e { - /* Magnetometer */ - compatible = "st,lsm303dlh-magn"; - reg = <0x1e>; - vdd-supply = <&ab8500_ldo_aux1_reg>; - vddio-supply = <&db8500_vsmps2_reg>; - pinctrl-names = "default"; - pinctrl-0 = <&magneto_snowball_mode>; - interrupt-parent = <&gpio5>; - interrupts = <5 IRQ_TYPE_EDGE_RISING>; /* DRDY line */ - }; - l3g4200d@68 { - /* Gyroscope */ - compatible = "st,l3g4200d-gyro"; - st,drdy-int-pin = <2>; - reg = <0x68>; - vdd-supply = <&ab8500_ldo_aux1_reg>; - vddio-supply = <&db8500_vsmps2_reg>; - pinctrl-names = "default"; - pinctrl-0 = <&gyro_snowball_mode>; - interrupt-parent = <&gpio5>; - interrupts = <6 IRQ_TYPE_EDGE_RISING>, /* DRDY line */ - <9 IRQ_TYPE_EDGE_RISING>; /* INT1 */ - }; - lsp001wm@5c { - /* Barometer/pressure sensor */ - compatible = "st,lps001wp-press"; - reg = <0x5c>; - vdd-supply = <&ab8500_ldo_aux1_reg>; - vddio-supply = <&db8500_vsmps2_reg>; - }; - }; - - i2c@80110000 { - pinctrl-names = "default","sleep"; - pinctrl-0 = <&i2c3_c_2_default>; - pinctrl-1 = <&i2c3_c_2_sleep>; - status = "okay"; - }; - - spi@80002000 { - pinctrl-names = "default"; - pinctrl-0 = <&ssp0_snowball_mode>; - status = "okay"; - }; - - prcmu@80157000 { - ab8500 { - ab8500-gpio { - /* - * AB8500 GPIOs are numbered starting from 1, so the first - * index 0 is what in the datasheet is called "GPIO1", and - * the second is "GPIO2" and so forth. Confusingly, the - * Snowball schematic then names the "GPIO2" line "PM_GPIO1". - * while later naming "GPIO4" as "PM_GPIO4". - */ - gpio-line-names = "", /* AB8500 GPIO1 */ - "PM_GPIO1", /* AB8500 GPIO2 */ - "WLAN_CLK_REQ", /* AB8500 GPIO3 */ - "PM_GPIO4", /* AB8500 GPIO4 */ - "", "", "", "", "", "", "", "", "", "", "", - "EN_3V6", /* AB8500 GPIO16 */ - "", "", "", "" ,"", "", "", "", "", - "EN_3V3", /* AB8500 GPIO26 */ - "", "", "", "", "", "", "", "", "", "", "", "", "", - "PM_GPIO40", /* AB8500 GPIO40 */ - "PM_GPIO41", /* AB8500 GPIO41 */ - "PM_GPIO42"; /* AB8500 GPIO42 */ - }; - - ab8500_usb { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&usb_a_1_default>; - pinctrl-1 = <&usb_a_1_sleep>; - }; - - ext_regulators: ab8500-ext-regulators { - ab8500_ext1_reg: ab8500_ext1 { - regulator-name = "ab8500-ext-supply1"; - }; - - ab8500_ext2_reg_reg: ab8500_ext2 { - regulator-name = "ab8500-ext-supply2"; - }; - - ab8500_ext3_reg_reg: ab8500_ext3 { - regulator-name = "ab8500-ext-supply3"; - }; - }; - - ab8500-regulators { - ab8500_ldo_aux1_reg: ab8500_ldo_aux1 { - regulator-name = "V-DISPLAY"; - }; - - ab8500_ldo_aux2_reg: ab8500_ldo_aux2 { - regulator-name = "V-eMMC1"; - }; - - ab8500_ldo_aux3_reg: ab8500_ldo_aux3 { - regulator-name = "V-MMC-SD"; - }; - - ab8500_ldo_intcore_reg: ab8500_ldo_intcore { - regulator-name = "V-INTCORE"; - }; - - ab8500_ldo_tvout_reg: ab8500_ldo_tvout { - regulator-name = "V-TVOUT"; - }; - - ab8500_ldo_audio_reg: ab8500_ldo_audio { - regulator-name = "V-AUD"; - }; - - ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 { - regulator-name = "V-AMIC1"; - }; - - ab8500_ldo_anamic2_reg: ab8500_ldo_anamic2 { - regulator-name = "V-AMIC2"; - }; - - ab8500_ldo_dmic_reg: ab8500_ldo_dmic { - regulator-name = "V-DMIC"; - }; - - ab8500_ldo_ana_reg: ab8500_ldo_ana { - regulator-name = "V-CSI/DSI"; - }; - }; - }; - }; - - pinctrl { - /* - * Set this up using hogs, as time goes by and as seems fit, these - * can be moved over to being controlled by respective device. - */ - pinctrl-names = "default"; - pinctrl-0 = <&gbf_snowball_mode>, - <&wlan_snowball_mode>; - - ethernet { - /* - * Mux in "SM" which is used for the - * SMSC911x Ethernet adapter - */ - eth_snowball_mode: eth_snowball { - snowball_mux { - function = "sm"; - groups = "sm_b_1"; - }; - /* LAN IRQ pin */ - snowball_cfg1 { - pins = "GPIO140_B11"; - ste,config = <&in_nopull>; - }; - /* LAN reset pin */ - snowball_cfg2 { - pins = "GPIO141_C12"; - ste,config = <&gpio_out_hi>; - }; - - }; - }; - sdi0 { - sdi0_default_mode: sdi0_default { - snowball_mux { - function = "mc0"; - /* Add the DAT31 pin even if it is not really used */ - groups = "mc0dat31dir_a_1"; - }; - snowball_cfg1 { - pins = "GPIO21_AB3"; /* DAT31DIR */ - ste,config = <&out_hi>; - }; - /* SD card detect GPIO pin, extend default state */ - snowball_cfg2 { - pins = "GPIO218_AH11"; - ste,config = <&gpio_in_pu>; - }; - /* VMMCI level-shifter enable */ - snowball_cfg3 { - pins = "GPIO217_AH12"; - ste,config = <&gpio_out_hi>; - }; - /* VMMCI level-shifter voltage select */ - snowball_cfg4 { - pins = "GPIO228_AJ6"; - ste,config = <&gpio_out_hi>; - }; - }; - }; - ssp0 { - ssp0_snowball_mode: ssp0_snowball_default { - snowball_mux { - function = "ssp0"; - groups = "ssp0_a_1"; - }; - snowball_cfg1 { - pins = "GPIO144_B13"; /* FRM */ - ste,config = <&gpio_out_hi>; - }; - snowball_cfg2 { - pins = "GPIO145_C13"; /* RXD */ - ste,config = <&in_pd>; - }; - snowball_cfg3 { - pins = - "GPIO146_D13", /* TXD */ - "GPIO143_D12"; /* CLK */ - ste,config = <&out_lo>; - }; - - }; - }; - gpio_led { - gpioled_snowball_mode: gpioled_default { - snowball_cfg1 { - pins = "GPIO142_C11"; - ste,config = <&gpio_out_hi>; - }; - - }; - }; - accelerometer { - accel_snowball_mode: accel_snowball { - /* Accelerometer lines */ - snowball_cfg1 { - pins = - "GPIO163_C20", /* ACCEL_IRQ1 */ - "GPIO164_B21"; /* ACCEL_IRQ2 */ - ste,config = <&gpio_in_pu>; - }; - }; - }; - gyro { - gyro_snowball_mode: gyro_snowball { - snowball_cfg1 { - pins = - "GPIO166_A22", /* DRDY */ - "GPIO169_D22"; /* INT */ - ste,config = <&gpio_in_pu>; - }; - }; - }; - magnetometer { - magneto_snowball_mode: magneto_snowball { - snowball_cfg1 { - pins = "GPIO165_C21"; /* MAG_DRDY */ - ste,config = <&gpio_in_pu>; - }; - }; - }; - gbf { - gbf_snowball_mode: gbf_snowball { - /* - * GBF (GPS, Bluetooth, FM-radio) interface, - * pull low to reset state - */ - snowball_cfg1 { - pins = "GPIO171_D23"; /* GBF_ENA_RESET */ - ste,config = <&gpio_out_lo>; - }; - }; - }; - wlan { - wlan_snowball_mode: wlan_snowball { - /* - * Activate this mode with the WLAN chip. - * These are plain GPIO pins used by WLAN - */ - snowball_cfg1 { - pins = - "GPIO161_D21", /* WLAN_PMU_EN */ - "GPIO215_AH13"; /* WLAN_ENA */ - ste,config = <&gpio_out_lo>; - }; - snowball_cfg2 { - pins = "GPIO216_AG12"; /* WLAN_IRQ */ - ste,config = <&gpio_in_pu>; - }; - }; - }; - }; - - mcde@a0350000 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&lcd_default_mode>; - pinctrl-1 = <&lcd_sleep_mode>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/ste-u300.dts b/sys/gnu/dts/arm/ste-u300.dts deleted file mode 100644 index f4e7660fead..00000000000 --- a/sys/gnu/dts/arm/ste-u300.dts +++ /dev/null @@ -1,464 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree for the ST-Ericsson U300 Machine and SoC - */ - -/dts-v1/; - -/ { - model = "ST-Ericsson U300"; - compatible = "stericsson,u300"; - #address-cells = <1>; - #size-cells = <1>; - - chosen { - bootargs = "root=/dev/ram0 console=ttyAMA0,115200n8 earlyprintk"; - }; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - }; - - memory { - device_type = "memory"; - reg = <0x48000000 0x03c00000>; - }; - - s365 { - compatible = "stericsson,s365"; - vana15-supply = <&ab3100_ldo_d_reg>; - syscon = <&syscon>; - }; - - syscon: syscon@c0011000 { - compatible = "stericsson,u300-syscon", "syscon"; - reg = <0xc0011000 0x1000>; - clk32: app_32_clk@32k { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - pll13: pll13@13M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <13000000>; - }; - /* Slow bridge clocks under PLL13 */ - slow_clk: slow_clk@13M { - #clock-cells = <0>; - compatible = "stericsson,u300-syscon-clk"; - clock-type = <0>; /* Slow */ - clock-id = <0>; - clocks = <&pll13>; - }; - uart0_clk: uart0_clk@13M { - #clock-cells = <0>; - compatible = "stericsson,u300-syscon-clk"; - clock-type = <0>; /* Slow */ - clock-id = <1>; - clocks = <&slow_clk>; - }; - gpio_clk: gpio_clk@13M { - #clock-cells = <0>; - compatible = "stericsson,u300-syscon-clk"; - clock-type = <0>; /* Slow */ - clock-id = <4>; - clocks = <&slow_clk>; - }; - rtc_clk: rtc_clk@13M { - #clock-cells = <0>; - compatible = "stericsson,u300-syscon-clk"; - clock-type = <0>; /* Slow */ - clock-id = <6>; - clocks = <&slow_clk>; - }; - apptimer_clk: app_tmr_clk@13M { - #clock-cells = <0>; - compatible = "stericsson,u300-syscon-clk"; - clock-type = <0>; /* Slow */ - clock-id = <7>; - clocks = <&slow_clk>; - }; - acc_tmr_clk@13M { - #clock-cells = <0>; - compatible = "stericsson,u300-syscon-clk"; - clock-type = <0>; /* Slow */ - clock-id = <8>; - clocks = <&slow_clk>; - }; - pll208: pll208@208M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <208000000>; - }; - app208: app_208_clk@208M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&pll208>; - }; - cpu_clk@208M { - #clock-cells = <0>; - compatible = "stericsson,u300-syscon-clk"; - clock-type = <2>; /* Rest */ - clock-id = <3>; - clocks = <&app208>; - }; - app104: app_104_clk@104M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <2>; - clock-mult = <1>; - clocks = <&pll208>; - }; - semi_clk@104M { - #clock-cells = <0>; - compatible = "stericsson,u300-syscon-clk"; - clock-type = <2>; /* Rest */ - clock-id = <9>; - clocks = <&app104>; - }; - app52: app_52_clk@52M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <4>; - clock-mult = <1>; - clocks = <&pll208>; - }; - /* AHB subsystem clocks */ - ahb_clk: ahb_subsys_clk@52M { - #clock-cells = <0>; - compatible = "stericsson,u300-syscon-clk"; - clock-type = <2>; /* Rest */ - clock-id = <10>; - clocks = <&app52>; - }; - intcon_clk@52M { - #clock-cells = <0>; - compatible = "stericsson,u300-syscon-clk"; - clock-type = <2>; /* Rest */ - clock-id = <12>; - clocks = <&ahb_clk>; - }; - emif_clk@52M { - #clock-cells = <0>; - compatible = "stericsson,u300-syscon-clk"; - clock-type = <2>; /* Rest */ - clock-id = <5>; - clocks = <&ahb_clk>; - }; - dmac_clk: dmac_clk@52M { - #clock-cells = <0>; - compatible = "stericsson,u300-syscon-clk"; - clock-type = <2>; /* Rest */ - clock-id = <4>; - clocks = <&app52>; - }; - fsmc_clk: fsmc_clk@52M { - #clock-cells = <0>; - compatible = "stericsson,u300-syscon-clk"; - clock-type = <2>; /* Rest */ - clock-id = <6>; - clocks = <&app52>; - }; - xgam_clk: xgam_clk@52M { - #clock-cells = <0>; - compatible = "stericsson,u300-syscon-clk"; - clock-type = <2>; /* Rest */ - clock-id = <8>; - clocks = <&app52>; - }; - app26: app_26_clk@26M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <2>; - clock-mult = <1>; - clocks = <&app52>; - }; - /* Fast bridge clocks */ - fast_clk: fast_clk@26M { - #clock-cells = <0>; - compatible = "stericsson,u300-syscon-clk"; - clock-type = <1>; /* Fast */ - clock-id = <0>; - clocks = <&app26>; - }; - i2c0_clk: i2c0_clk@26M { - #clock-cells = <0>; - compatible = "stericsson,u300-syscon-clk"; - clock-type = <1>; /* Fast */ - clock-id = <1>; - clocks = <&fast_clk>; - }; - i2c1_clk: i2c1_clk@26M { - #clock-cells = <0>; - compatible = "stericsson,u300-syscon-clk"; - clock-type = <1>; /* Fast */ - clock-id = <2>; - clocks = <&fast_clk>; - }; - mmc_pclk: mmc_p_clk@26M { - #clock-cells = <0>; - compatible = "stericsson,u300-syscon-clk"; - clock-type = <1>; /* Fast */ - clock-id = <5>; - clocks = <&fast_clk>; - }; - mmc_mclk: mmc_mclk { - #clock-cells = <0>; - compatible = "stericsson,u300-syscon-mclk"; - clocks = <&mmc_pclk>; - }; - spi_clk: spi_p_clk@26M { - #clock-cells = <0>; - compatible = "stericsson,u300-syscon-clk"; - clock-type = <1>; /* Fast */ - clock-id = <6>; - clocks = <&fast_clk>; - }; - }; - - timer: timer@c0014000 { - compatible = "stericsson,u300-apptimer"; - reg = <0xc0014000 0x1000>; - interrupt-parent = <&vica>; - interrupts = <24 25 26 27>; - clocks = <&apptimer_clk>; - }; - - gpio: gpio@c0016000 { - compatible = "stericsson,gpio-coh901"; - reg = <0xc0016000 0x1000>; - interrupt-parent = <&vicb>; - interrupts = <0 1 2 18 21 22 23>; - clocks = <&gpio_clk>; - interrupt-names = "gpio0", "gpio1", "gpio2", "gpio3", - "gpio4", "gpio5", "gpio6"; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - }; - - pinctrl: pinctrl@c0011000 { - compatible = "stericsson,pinctrl-u300"; - reg = <0xc0011000 0x1000>; - }; - - watchdog: watchdog@c0012000 { - compatible = "stericsson,coh901327"; - reg = <0xc0012000 0x1000>; - interrupt-parent = <&vicb>; - interrupts = <3>; - clocks = <&clk32>; - }; - - rtc: rtc@c0017000 { - compatible = "stericsson,coh901331"; - reg = <0xc0017000 0x1000>; - interrupt-parent = <&vicb>; - interrupts = <10>; - clocks = <&rtc_clk>; - }; - - dmac: dma-controller@c00020000 { - compatible = "stericsson,coh901318"; - reg = <0xc0020000 0x1000>; - interrupt-parent = <&vica>; - interrupts = <2>; - #dma-cells = <1>; - dma-channels = <40>; - clocks = <&dmac_clk>; - }; - - /* A NAND flash of 128 MiB */ - fsmc: flash@40000000 { - compatible = "stericsson,fsmc-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x9f800000 0x1000>, /* FSMC Register*/ - <0x80000000 0x4000>, /* NAND Base DATA */ - <0x80020000 0x4000>, /* NAND Base ADDR */ - <0x80010000 0x4000>; /* NAND Base CMD */ - reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd"; - nand-skip-bbtscan; - clocks = <&fsmc_clk>; - - partition@0 { - label = "boot records"; - reg = <0x0 0x20000>; - }; - partition@20000 { - label = "free"; - reg = <0x20000 0x7e0000>; - }; - partition@800000 { - label = "platform"; - reg = <0x800000 0xf800000>; - }; - }; - - i2c0: i2c@c0004000 { - compatible = "st,ddci2c"; - reg = <0xc0004000 0x1000>; - interrupt-parent = <&vicb>; - interrupts = <8>; - clocks = <&i2c0_clk>; - #address-cells = <1>; - #size-cells = <0>; - ab3100: ab3100@48 { - compatible = "stericsson,ab3100"; - reg = <0x48>; - interrupt-parent = <&vica>; - interrupts = <0>; /* EXT0 IRQ */ - ab3100-regulators { - compatible = "stericsson,ab3100-regulators"; - ab3100_ldo_a_reg: ab3100_ldo_a { - startup-delay-us = <200>; - regulator-always-on; - regulator-boot-on; - }; - ab3100_ldo_c_reg: ab3100_ldo_c { - startup-delay-us = <200>; - }; - ab3100_ldo_d_reg: ab3100_ldo_d { - startup-delay-us = <200>; - }; - ab3100_ldo_e_reg: ab3100_ldo_e { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - startup-delay-us = <200>; - regulator-always-on; - regulator-boot-on; - }; - ab3100_ldo_f_reg: ab3100_ldo_f { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - startup-delay-us = <600>; - regulator-always-on; - regulator-boot-on; - }; - ab3100_ldo_g_reg: ab3100_ldo_g { - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <2850000>; - startup-delay-us = <400>; - }; - ab3100_ldo_h_reg: ab3100_ldo_h { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <2750000>; - startup-delay-us = <200>; - }; - ab3100_ldo_k_reg: ab3100_ldo_k { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2750000>; - startup-delay-us = <200>; - }; - ab3100_ext_reg: ab3100_ext { - }; - ab3100_buck_reg: ab3100_buck { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1800000>; - startup-delay-us = <1000>; - regulator-always-on; - regulator-boot-on; - }; - }; - }; - }; - - i2c1: i2c@c0005000 { - compatible = "st,ddci2c"; - reg = <0xc0005000 0x1000>; - interrupt-parent = <&vicb>; - interrupts = <9>; - clocks = <&i2c1_clk>; - #address-cells = <1>; - #size-cells = <0>; - fwcam0: fwcam@10 { - reg = <0x10>; - }; - fwcam1: fwcam@5d { - reg = <0x5d>; - }; - }; - - amba { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - vica: interrupt-controller@a0001000 { - compatible = "arm,versatile-vic"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0xa0001000 0x20>; - }; - - vicb: interrupt-controller@a0002000 { - compatible = "arm,versatile-vic"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0xa0002000 0x20>; - }; - - uart0: serial@c0013000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0xc0013000 0x1000>; - interrupt-parent = <&vica>; - interrupts = <22>; - clocks = <&uart0_clk>, <&uart0_clk>; - clock-names = "apb_pclk", "uart0_clk"; - dmas = <&dmac 17 &dmac 18>; - dma-names = "tx", "rx"; - }; - - uart1: serial@c0007000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0xc0007000 0x1000>; - interrupt-parent = <&vicb>; - interrupts = <20>; - dmas = <&dmac 38 &dmac 39>; - dma-names = "tx", "rx"; - }; - - mmcsd: mmcsd@c0001000 { - compatible = "arm,pl18x", "arm,primecell"; - reg = <0xc0001000 0x1000>; - interrupt-parent = <&vicb>; - interrupts = <6 7>; - clocks = <&mmc_pclk>, <&mmc_mclk>; - clock-names = "apb_pclk", "mclk"; - max-frequency = <24000000>; - bus-width = <4>; // SD-card slot - cap-mmc-highspeed; - cap-sd-highspeed; - cd-gpios = <&gpio 12 0x4>; - cd-inverted; - vmmc-supply = <&ab3100_ldo_g_reg>; - dmas = <&dmac 14>; - dma-names = "rx"; - }; - - spi: spi@c0006000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0xc0006000 0x1000>; - interrupt-parent = <&vica>; - interrupts = <23>; - clocks = <&spi_clk>, <&spi_clk>; - clock-names = "SSPCLK", "apb_pclk"; - dmas = <&dmac 27 &dmac 28>; - dma-names = "tx", "rx"; - num-cs = <3>; - #address-cells = <1>; - #size-cells = <0>; - spi-dummy@1 { - compatible = "arm,pl022-dummy"; - reg = <1>; - spi-max-frequency = <20000000>; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/ste-ux500-samsung-golden.dts b/sys/gnu/dts/arm/ste-ux500-samsung-golden.dts deleted file mode 100644 index 313f0ab1686..00000000000 --- a/sys/gnu/dts/arm/ste-ux500-samsung-golden.dts +++ /dev/null @@ -1,455 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/dts-v1/; - -#include "ste-db8500.dtsi" -#include "ste-ab8505.dtsi" -#include "ste-dbx5x0-pinctrl.dtsi" -#include -#include -#include - -/* - * Note: This device tree cannot be booted directly with the Samsung bootloader. - * You need an intermediate, device-tree compatible bootloader - * that locks the L2 cache. Otherwise the kernel will crash after decompression. - * - * There is a port of (mainline) U-Boot, see - * https://wiki.postmarketos.org/wiki/ST-Ericsson_NovaThor_U8500#U-Boot - */ -/ { - model = "Samsung Galaxy S III mini (GT-I8190)"; - compatible = "samsung,golden", "st-ericsson,u8500"; - - chosen { - stdout-path = &serial2; - }; - - soc { - /* External Micro SD card slot */ - sdi0_per1@80126000 { - status = "okay"; - - arm,primecell-periphid = <0x10480180>; - max-frequency = <100000000>; - bus-width = <4>; - - non-removable; - /* - * Unfortunately, there is no way to enable the UHS - * modes due to a limitation of the SD level translator: - * It will either translate to 2.9V or disconnect the - * DATA lines, so switching to 1.8V signal voltage fails. - */ - cap-sd-highspeed; - cap-mmc-highspeed; - st,sig-pin-fbclk; - full-pwr-cycle; - - vmmc-supply = <&ab8500_ldo_aux3_reg>; - vqmmc-supply = <&sd_level_translator>; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&mc0_a_2_default>; - pinctrl-1 = <&mc0_a_2_sleep>; - }; - - /* WLAN SDIO */ - sdi1_per2@80118000 { - status = "okay"; - - arm,primecell-periphid = <0x10480180>; - max-frequency = <50000000>; - bus-width = <4>; - - non-removable; - cap-sd-highspeed; - - vmmc-supply = <&wl_reg_on>; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&mc1_a_2_default>; - pinctrl-1 = <&mc1_a_2_sleep>; - - #address-cells = <1>; - #size-cells = <0>; - - wifi@1 { - compatible = "brcm,bcm4329-fmac"; - reg = <1>; - - /* GPIO216 (WLAN_HOST_WAKE) */ - interrupt-parent = <&gpio6>; - interrupts = <24 IRQ_TYPE_EDGE_FALLING>; - interrupt-names = "host-wake"; - - pinctrl-names = "default"; - pinctrl-0 = <&wlan_default>; - }; - }; - - /* eMMC */ - sdi2_per3@80005000 { - status = "okay"; - - arm,primecell-periphid = <0x10480180>; - max-frequency = <100000000>; - bus-width = <8>; - - non-removable; - cap-mmc-highspeed; - mmc-ddr-1_8v; - - vmmc-supply = <&vmem_3v3>; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&mc2_a_1_default>; - pinctrl-1 = <&mc2_a_1_sleep>; - }; - - /* BT UART */ - uart@80120000 { - status = "okay"; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&u0_a_1_default>; - pinctrl-1 = <&u0_a_1_sleep>; - - bluetooth { - compatible = "brcm,bcm4330-bt"; - /* GPIO222 (BT_VREG_ON) */ - shutdown-gpios = <&gpio6 30 GPIO_ACTIVE_HIGH>; - /* GPIO199 (BT_WAKE) */ - device-wakeup-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; - /* GPIO97 (BT_HOST_WAKE) */ - host-wakeup-gpios = <&gpio3 1 GPIO_ACTIVE_HIGH>; - - pinctrl-names = "default"; - pinctrl-0 = <&bluetooth_default>; - }; - }; - - /* GPF UART */ - uart@80121000 { - status = "okay"; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&u1rxtx_a_1_default &u1ctsrts_a_1_default>; - pinctrl-1 = <&u1rxtx_a_1_sleep &u1ctsrts_a_1_sleep>; - }; - - /* Debugging console UART */ - uart@80007000 { - status = "okay"; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&u2rxtx_c_1_default>; - pinctrl-1 = <&u2rxtx_c_1_sleep>; - }; - - i2c@80128000 { - status = "okay"; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c2_b_2_default>; - pinctrl-1 = <&i2c2_b_2_sleep>; - - imu@68 { - compatible = "invensense,mpu6050"; - reg = <0x68>; - - /* GPIO206 (ACC_INT) */ - interrupt-parent = <&gpio6>; - interrupts = <14 IRQ_TYPE_EDGE_RISING>; - - mount-matrix = "0", "1", "0", - "-1", "0", "0", - "0", "0", "1"; - - vdd-supply = <&ab8500_ldo_aux1_reg>; - vddio-supply = <&ab8500_ldo_aux8_reg>; - - pinctrl-names = "default"; - pinctrl-0 = <&imu_default>; - }; - }; - - i2c@80110000 { - status = "okay"; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c3_c_2_default>; - pinctrl-1 = <&i2c3_c_2_sleep>; - - touchscreen@4a { - compatible = "atmel,maxtouch"; - reg = <0x4a>; - - /* GPIO218 (TSP_INT_1V8) */ - interrupt-parent = <&gpio6>; - interrupts = <26 IRQ_TYPE_EDGE_FALLING>; - - pinctrl-names = "default"; - pinctrl-0 = <&tsp_default>; - }; - }; - - prcmu@80157000 { - ab8505 { - ab8500_usb { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&usb_a_1_default>; - pinctrl-1 = <&usb_a_1_sleep>; - }; - - ab8505-regulators { - ab8500_ldo_aux1 { - regulator-name = "sensor_3v"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - ab8500_ldo_aux2 { - regulator-name = "vreg_tsp_a3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; /* FIXME */ - }; - - ab8500_ldo_aux3 { - regulator-name = "vdd_tf_2v91"; - }; - - ab8500_ldo_aux4 { - regulator-name = "key_led_3.3v"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ab8500_ldo_aux5 { - regulator-name = "vreg_tsp_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; /* FIXME */ - }; - - ab8500_ldo_aux6 { - regulator-name = "touch_key_2.2v"; - regulator-min-microvolt = <2200000>; - regulator-max-microvolt = <2200000>; - }; - - ab8500_ldo_aux8 { - regulator-name = "sensor_1v8"; - }; - }; - }; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - pinctrl-names = "default"; - pinctrl-0 = <&gpio_keys_default>; - - label = "GPIO Buttons"; - - volume-up { - label = "Volume Up"; - /* GPIO67 (VOL_UP) */ - gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - volume-down { - label = "Volume Down"; - /* GPIO92 (VOL_DOWN) */ - gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - home { - label = "Home"; - /* GPIO91 (HOME_KEY) */ - gpios = <&gpio2 27 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - vibrator { - compatible = "gpio-vibrator"; - /* GPIO195 (MOT_EN) */ - enable-gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>; - - pinctrl-names = "default"; - pinctrl-0 = <&vibrator_default>; - }; - - /* External LDO for eMMC */ - vmem_3v3: regulator-vmem { - compatible = "regulator-fixed"; - - regulator-name = "vmem_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - - startup-delay-us = <200>; - - /* GPIO223 (MEM_LDO_EN) */ - gpio = <&gpio6 31 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-names = "default"; - pinctrl-0 = <&mem_ldo_default>; - }; - - /* TI TXS0206-29 level translator for 2.9 V */ - sd_level_translator: regulator-sd-level-translator { - compatible = "regulator-fixed"; - - regulator-name = "sd-level-translator"; - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - - startup-delay-us = <200>; - - /* GPIO87 (TXS0206-29_EN) */ - gpios = <&gpio2 23 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-names = "default"; - pinctrl-0 = <&sd_level_translator_default>; - }; - - /* - * WL_REG_ON takes WLAN out of reset and enables the internal regulators. - * The voltage specified here is only used to determine the OCR mask, - * the BCM chip is actually connected directly to VBAT. - */ - wl_reg_on: regulator-wl-reg-on { - compatible = "regulator-fixed"; - - regulator-name = "wl-reg-on"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - - startup-delay-us = <100000>; - - /* GPIO215 (WLAN_EN) */ - gpio = <&gpio6 23 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-names = "default"; - pinctrl-0 = <&wlan_en_default>; - }; -}; - -&pinctrl { - gpio-keys { - gpio_keys_default: gpio_keys_default { - golden_cfg1 { - pins = "GPIO67", /* VOL_UP */ - "GPIO91", /* HOME_KEY */ - "GPIO92"; /* VOL_DOWN */ - ste,config = <&gpio_in_pu>; - }; - }; - }; - - sdi0 { - sd_level_translator_default: sd_level_translator_default { - golden_cfg1 { - pins = "GPIO87_B3"; /* TXS0206-29_EN */ - ste,config = <&gpio_out_lo>; - }; - }; - }; - - sdi2 { - mem_ldo_default: mem_ldo_default { - golden_cfg1 { - pins = "GPIO223_AH9"; /* MEM_LDO_EN */ - ste,config = <&gpio_out_hi>; - }; - }; - }; - - imu { - imu_default: imu_default { - golden_cfg1 { - pins = "GPIO206_AG24"; /* ACC_INT */ - ste,config = <&gpio_in_pd>; - }; - }; - }; - - tsp { - tsp_default: tsp_default { - golden_cfg1 { - pins = "GPIO218_AH11"; /* TSP_INT_1V8 */ - ste,config = <&gpio_in_nopull>; - }; - }; - }; - - wlan { - wlan_default: wlan_default { - golden_cfg1 { - pins = "GPIO216_AG12"; /* WLAN_HOST_WAKE */ - ste,config = <&gpio_in_pd>; - }; - }; - - wlan_en_default: wlan_en_default { - golden_cfg1 { - pins = "GPIO215_AH13"; /* WLAN_EN */ - ste,config = <&gpio_out_lo>; - }; - }; - }; - - bluetooth { - bluetooth_default: bluetooth_default { - golden_cfg1 { - pins = "GPIO199_AH23", /* BT_WAKE */ - "GPIO222_AJ9"; /* BT_VREG_ON */ - ste,config = <&gpio_out_lo>; - }; - golden_cfg2 { - pins = "GPIO97_D9"; /* BT_HOST_WAKE */ - ste,config = <&gpio_in_nopull>; - }; - }; - }; - - vibrator { - vibrator_default: vibrator_default { - golden_cfg1 { - pins = "GPIO195_AG28"; /* MOT_EN */ - ste,config = <&gpio_out_lo>; - }; - }; - }; -}; - -&ab8505_gpio { - /* Hog a few default settings */ - pinctrl-names = "default"; - pinctrl-0 = <&gpio_default>; - - gpio { - gpio_default: gpio_default { - golden_mux { - /* Change unused pins to GPIO mode */ - function = "gpio"; - groups = "gpio3_a_1", /* default: SysClkReq4 */ - "gpio14_a_1"; /* default: PWMOut1 */ - }; - golden_cfg1 { - pins = "GPIO11_B17", "GPIO13_D17", "GPIO50_L4"; - bias-disable; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/stih407-b2120.dts b/sys/gnu/dts/arm/stih407-b2120.dts deleted file mode 100644 index 31c85f945c6..00000000000 --- a/sys/gnu/dts/arm/stih407-b2120.dts +++ /dev/null @@ -1,28 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 STMicroelectronics (R&D) Limited. - * Author: Giuseppe Cavallaro - */ -/dts-v1/; -#include "stih407.dtsi" -#include "stihxxx-b2120.dtsi" -/ { - model = "STiH407 B2120"; - compatible = "st,stih407-b2120", "st,stih407"; - - chosen { - bootargs = "clk_ignore_unused"; - stdout-path = &sbc_serial0; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x80000000>; - }; - - aliases { - serial0 = &sbc_serial0; - ethernet0 = ðernet0; - }; - -}; diff --git a/sys/gnu/dts/arm/stih407-clock.dtsi b/sys/gnu/dts/arm/stih407-clock.dtsi deleted file mode 100644 index 1ab40db7c91..00000000000 --- a/sys/gnu/dts/arm/stih407-clock.dtsi +++ /dev/null @@ -1,323 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 STMicroelectronics R&D Limited - */ -#include -/ { - /* - * Fixed 30MHz oscillator inputs to SoC - */ - clk_sysin: clk-sysin { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <30000000>; - }; - - clk_tmdsout_hdmi: clk-tmdsout-hdmi { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - /* - * A9 PLL. - */ - clockgen-a9@92b0000 { - compatible = "st,clkgen-c32"; - reg = <0x92b0000 0xffff>; - - clockgen_a9_pll: clockgen-a9-pll { - #clock-cells = <1>; - compatible = "st,stih407-clkgen-plla9"; - - clocks = <&clk_sysin>; - - clock-output-names = "clockgen-a9-pll-odf"; - }; - }; - - /* - * ARM CPU related clocks. - */ - clk_m_a9: clk-m-a9@92b0000 { - #clock-cells = <0>; - compatible = "st,stih407-clkgen-a9-mux"; - reg = <0x92b0000 0x10000>; - - clocks = <&clockgen_a9_pll 0>, - <&clockgen_a9_pll 0>, - <&clk_s_c0_flexgen 13>, - <&clk_m_a9_ext2f_div2>; - - - /* - * ARM Peripheral clock for timers - */ - arm_periph_clk: clk-m-a9-periphs { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - - clocks = <&clk_m_a9>; - clock-div = <2>; - clock-mult = <1>; - }; - }; - - clockgen-a@90ff000 { - compatible = "st,clkgen-c32"; - reg = <0x90ff000 0x1000>; - - clk_s_a0_pll: clk-s-a0-pll { - #clock-cells = <1>; - compatible = "st,clkgen-pll0"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-a0-pll-ofd-0"; - clock-critical = <0>; /* clk-s-a0-pll-ofd-0 */ - }; - - clk_s_a0_flexgen: clk-s-a0-flexgen { - compatible = "st,flexgen"; - - #clock-cells = <1>; - - clocks = <&clk_s_a0_pll 0>, - <&clk_sysin>; - - clock-output-names = "clk-ic-lmi0"; - clock-critical = ; - }; - }; - - clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 { - #clock-cells = <1>; - compatible = "st,quadfs-pll"; - reg = <0x9103000 0x1000>; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-c0-fs0-ch0", - "clk-s-c0-fs0-ch1", - "clk-s-c0-fs0-ch2", - "clk-s-c0-fs0-ch3"; - clock-critical = <0>; /* clk-s-c0-fs0-ch0 */ - }; - - clk_s_c0: clockgen-c@9103000 { - compatible = "st,clkgen-c32"; - reg = <0x9103000 0x1000>; - - clk_s_c0_pll0: clk-s-c0-pll0 { - #clock-cells = <1>; - compatible = "st,clkgen-pll0"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-c0-pll0-odf-0"; - clock-critical = <0>; /* clk-s-c0-pll0-odf-0 */ - }; - - clk_s_c0_pll1: clk-s-c0-pll1 { - #clock-cells = <1>; - compatible = "st,clkgen-pll1"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-c0-pll1-odf-0"; - }; - - clk_s_c0_flexgen: clk-s-c0-flexgen { - #clock-cells = <1>; - compatible = "st,flexgen"; - - clocks = <&clk_s_c0_pll0 0>, - <&clk_s_c0_pll1 0>, - <&clk_s_c0_quadfs 0>, - <&clk_s_c0_quadfs 1>, - <&clk_s_c0_quadfs 2>, - <&clk_s_c0_quadfs 3>, - <&clk_sysin>; - - clock-output-names = "clk-icn-gpu", - "clk-fdma", - "clk-nand", - "clk-hva", - "clk-proc-stfe", - "clk-proc-tp", - "clk-rx-icn-dmu", - "clk-rx-icn-hva", - "clk-icn-cpu", - "clk-tx-icn-dmu", - "clk-mmc-0", - "clk-mmc-1", - "clk-jpegdec", - "clk-ext2fa9", - "clk-ic-bdisp-0", - "clk-ic-bdisp-1", - "clk-pp-dmu", - "clk-vid-dmu", - "clk-dss-lpc", - "clk-st231-aud-0", - "clk-st231-gp-1", - "clk-st231-dmu", - "clk-icn-lmi", - "clk-tx-icn-disp-1", - "clk-icn-sbc", - "clk-stfe-frc2", - "clk-eth-phy", - "clk-eth-ref-phyclk", - "clk-flash-promip", - "clk-main-disp", - "clk-aux-disp", - "clk-compo-dvp"; - clock-critical = , - , - , - , - , - ; - - /* - * ARM Peripheral clock for timers - */ - clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - - clocks = <&clk_s_c0_flexgen 13>; - - clock-output-names = "clk-m-a9-ext2f-div2"; - - clock-div = <2>; - clock-mult = <1>; - }; - }; - }; - - clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 { - #clock-cells = <1>; - compatible = "st,quadfs"; - reg = <0x9104000 0x1000>; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-d0-fs0-ch0", - "clk-s-d0-fs0-ch1", - "clk-s-d0-fs0-ch2", - "clk-s-d0-fs0-ch3"; - }; - - clockgen-d0@9104000 { - compatible = "st,clkgen-c32"; - reg = <0x9104000 0x1000>; - - clk_s_d0_flexgen: clk-s-d0-flexgen { - #clock-cells = <1>; - compatible = "st,flexgen-audio", "st,flexgen"; - - clocks = <&clk_s_d0_quadfs 0>, - <&clk_s_d0_quadfs 1>, - <&clk_s_d0_quadfs 2>, - <&clk_s_d0_quadfs 3>, - <&clk_sysin>; - - clock-output-names = "clk-pcm-0", - "clk-pcm-1", - "clk-pcm-2", - "clk-spdiff"; - }; - }; - - clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 { - #clock-cells = <1>; - compatible = "st,quadfs"; - reg = <0x9106000 0x1000>; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-d2-fs0-ch0", - "clk-s-d2-fs0-ch1", - "clk-s-d2-fs0-ch2", - "clk-s-d2-fs0-ch3"; - }; - - clockgen-d2@9106000 { - compatible = "st,clkgen-c32"; - reg = <0x9106000 0x1000>; - - clk_s_d2_flexgen: clk-s-d2-flexgen { - #clock-cells = <1>; - compatible = "st,flexgen-video", "st,flexgen"; - - clocks = <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 1>, - <&clk_s_d2_quadfs 2>, - <&clk_s_d2_quadfs 3>, - <&clk_sysin>, - <&clk_sysin>, - <&clk_tmdsout_hdmi>; - - clock-output-names = "clk-pix-main-disp", - "clk-pix-pip", - "clk-pix-gdp1", - "clk-pix-gdp2", - "clk-pix-gdp3", - "clk-pix-gdp4", - "clk-pix-aux-disp", - "clk-denc", - "clk-pix-hddac", - "clk-hddac", - "clk-sddac", - "clk-pix-dvo", - "clk-dvo", - "clk-pix-hdmi", - "clk-tmds-hdmi", - "clk-ref-hdmiphy"; - }; - }; - - clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 { - #clock-cells = <1>; - compatible = "st,quadfs"; - reg = <0x9107000 0x1000>; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-d3-fs0-ch0", - "clk-s-d3-fs0-ch1", - "clk-s-d3-fs0-ch2", - "clk-s-d3-fs0-ch3"; - }; - - clockgen-d3@9107000 { - compatible = "st,clkgen-c32"; - reg = <0x9107000 0x1000>; - - clk_s_d3_flexgen: clk-s-d3-flexgen { - #clock-cells = <1>; - compatible = "st,flexgen"; - - clocks = <&clk_s_d3_quadfs 0>, - <&clk_s_d3_quadfs 1>, - <&clk_s_d3_quadfs 2>, - <&clk_s_d3_quadfs 3>, - <&clk_sysin>; - - clock-output-names = "clk-stfe-frc1", - "clk-tsout-0", - "clk-tsout-1", - "clk-mchi", - "clk-vsens-compo", - "clk-frc1-remote", - "clk-lpc-0", - "clk-lpc-1"; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/stih407-family.dtsi b/sys/gnu/dts/arm/stih407-family.dtsi deleted file mode 100644 index 7c36c37260a..00000000000 --- a/sys/gnu/dts/arm/stih407-family.dtsi +++ /dev/null @@ -1,1000 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 STMicroelectronics Limited. - * Author: Giuseppe Cavallaro - */ -#include "stih407-pinctrl.dtsi" -#include -#include -#include -#include -/ { - #address-cells = <1>; - #size-cells = <1>; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gp0_reserved: rproc@45000000 { - compatible = "shared-dma-pool"; - reg = <0x45000000 0x00400000>; - no-map; - }; - - delta_reserved: rproc@44000000 { - compatible = "shared-dma-pool"; - reg = <0x44000000 0x01000000>; - no-map; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - - /* u-boot puts hpen in SBC dmem at 0xa4 offset */ - cpu-release-addr = <0x94100A4>; - - /* kHz uV */ - operating-points = <1500000 0 - 1200000 0 - 800000 0 - 500000 0>; - - clocks = <&clk_m_a9>; - clock-names = "cpu"; - clock-latency = <100000>; - cpu0-supply = <&pwm_regulator>; - st,syscfg = <&syscfg_core 0x8e0>; - }; - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <1>; - - /* u-boot puts hpen in SBC dmem at 0xa4 offset */ - cpu-release-addr = <0x94100A4>; - - /* kHz uV */ - operating-points = <1500000 0 - 1200000 0 - 800000 0 - 500000 0>; - }; - }; - - intc: interrupt-controller@8761000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x08761000 0x1000>, <0x08760100 0x100>; - }; - - scu@8760000 { - compatible = "arm,cortex-a9-scu"; - reg = <0x08760000 0x1000>; - }; - - timer@8760200 { - interrupt-parent = <&intc>; - compatible = "arm,cortex-a9-global-timer"; - reg = <0x08760200 0x100>; - interrupts = ; - clocks = <&arm_periph_clk>; - }; - - l2: cache-controller@8762000 { - compatible = "arm,pl310-cache"; - reg = <0x08762000 0x1000>; - arm,data-latency = <3 3 3>; - arm,tag-latency = <2 2 2>; - cache-unified; - cache-level = <2>; - }; - - arm-pmu { - interrupt-parent = <&intc>; - compatible = "arm,cortex-a9-pmu"; - interrupts = ; - }; - - pwm_regulator: pwm-regulator { - compatible = "pwm-regulator"; - pwms = <&pwm1 3 8448>; - regulator-name = "CPU_1V0_AVS"; - regulator-min-microvolt = <784000>; - regulator-max-microvolt = <1299000>; - regulator-always-on; - max-duty-cycle = <255>; - status = "okay"; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&intc>; - ranges; - compatible = "simple-bus"; - - restart: restart-controller@0 { - compatible = "st,stih407-restart"; - reg = <0 0>; - st,syscfg = <&syscfg_sbc_reg>; - status = "okay"; - }; - - powerdown: powerdown-controller@0 { - compatible = "st,stih407-powerdown"; - reg = <0 0>; - #reset-cells = <1>; - }; - - softreset: softreset-controller@0 { - compatible = "st,stih407-softreset"; - reg = <0 0>; - #reset-cells = <1>; - }; - - picophyreset: picophyreset-controller@0 { - compatible = "st,stih407-picophyreset"; - reg = <0 0>; - #reset-cells = <1>; - }; - - syscfg_sbc: sbc-syscfg@9620000 { - compatible = "st,stih407-sbc-syscfg", "syscon"; - reg = <0x9620000 0x1000>; - }; - - syscfg_front: front-syscfg@9280000 { - compatible = "st,stih407-front-syscfg", "syscon"; - reg = <0x9280000 0x1000>; - }; - - syscfg_rear: rear-syscfg@9290000 { - compatible = "st,stih407-rear-syscfg", "syscon"; - reg = <0x9290000 0x1000>; - }; - - syscfg_flash: flash-syscfg@92a0000 { - compatible = "st,stih407-flash-syscfg", "syscon"; - reg = <0x92a0000 0x1000>; - }; - - syscfg_sbc_reg: fvdp-lite-syscfg@9600000 { - compatible = "st,stih407-sbc-reg-syscfg", "syscon"; - reg = <0x9600000 0x1000>; - }; - - syscfg_core: core-syscfg@92b0000 { - compatible = "st,stih407-core-syscfg", "syscon"; - reg = <0x92b0000 0x1000>; - - sti_sasg_codec: sti-sasg-codec { - compatible = "st,stih407-sas-codec"; - #sound-dai-cells = <1>; - status = "disabled"; - st,syscfg = <&syscfg_core>; - }; - }; - - syscfg_lpm: lpm-syscfg@94b5100 { - compatible = "st,stih407-lpm-syscfg", "syscon"; - reg = <0x94b5100 0x1000>; - }; - - irq-syscfg@0 { - compatible = "st,stih407-irq-syscfg"; - reg = <0 0>; - st,syscfg = <&syscfg_core>; - st,irq-device = , - ; - st,fiq-device = , - ; - }; - - /* Display */ - vtg_main: sti-vtg-main@8d02800 { - compatible = "st,vtg"; - reg = <0x8d02800 0x200>; - interrupts = ; - }; - - vtg_aux: sti-vtg-aux@8d00200 { - compatible = "st,vtg"; - reg = <0x8d00200 0x100>; - interrupts = ; - }; - - serial@9830000 { - compatible = "st,asc"; - reg = <0x9830000 0x2c>; - interrupts = ; - clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; - /* Pinctrl moved out to a per-board configuration */ - - status = "disabled"; - }; - - serial@9831000 { - compatible = "st,asc"; - reg = <0x9831000 0x2c>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_serial1>; - clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; - - status = "disabled"; - }; - - serial@9832000 { - compatible = "st,asc"; - reg = <0x9832000 0x2c>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_serial2>; - clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; - - status = "disabled"; - }; - - /* SBC_ASC0 - UART10 */ - sbc_serial0: serial@9530000 { - compatible = "st,asc"; - reg = <0x9530000 0x2c>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sbc_serial0>; - clocks = <&clk_sysin>; - - status = "disabled"; - }; - - serial@9531000 { - compatible = "st,asc"; - reg = <0x9531000 0x2c>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sbc_serial1>; - clocks = <&clk_sysin>; - - status = "disabled"; - }; - - i2c@9840000 { - compatible = "st,comms-ssc4-i2c"; - interrupts = ; - reg = <0x9840000 0x110>; - clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; - clock-names = "ssc"; - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0_default>; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - i2c@9841000 { - compatible = "st,comms-ssc4-i2c"; - reg = <0x9841000 0x110>; - interrupts = ; - clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; - clock-names = "ssc"; - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1_default>; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - i2c@9842000 { - compatible = "st,comms-ssc4-i2c"; - reg = <0x9842000 0x110>; - interrupts = ; - clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; - clock-names = "ssc"; - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2_default>; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - i2c@9843000 { - compatible = "st,comms-ssc4-i2c"; - reg = <0x9843000 0x110>; - interrupts = ; - clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; - clock-names = "ssc"; - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3_default>; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - i2c@9844000 { - compatible = "st,comms-ssc4-i2c"; - reg = <0x9844000 0x110>; - interrupts = ; - clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; - clock-names = "ssc"; - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4_default>; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - i2c@9845000 { - compatible = "st,comms-ssc4-i2c"; - reg = <0x9845000 0x110>; - interrupts = ; - clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; - clock-names = "ssc"; - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c5_default>; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - - /* SSCs on SBC */ - i2c@9540000 { - compatible = "st,comms-ssc4-i2c"; - reg = <0x9540000 0x110>; - interrupts = ; - clocks = <&clk_sysin>; - clock-names = "ssc"; - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c10_default>; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - i2c@9541000 { - compatible = "st,comms-ssc4-i2c"; - reg = <0x9541000 0x110>; - interrupts = ; - clocks = <&clk_sysin>; - clock-names = "ssc"; - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c11_default>; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - usb2_picophy0: phy1@0 { - compatible = "st,stih407-usb2-phy"; - reg = <0 0>; - #phy-cells = <0>; - st,syscfg = <&syscfg_core 0x100 0xf4>; - resets = <&softreset STIH407_PICOPHY_SOFTRESET>, - <&picophyreset STIH407_PICOPHY2_RESET>; - reset-names = "global", "port"; - }; - - miphy28lp_phy: miphy28lp@0 { - compatible = "st,miphy28lp-phy"; - st,syscfg = <&syscfg_core>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - reg = <0 0>; - - phy_port0: port@9b22000 { - reg = <0x9b22000 0xff>, - <0x9b09000 0xff>, - <0x9b04000 0xff>; - reg-names = "sata-up", - "pcie-up", - "pipew"; - - st,syscfg = <0x114 0x818 0xe0 0xec>; - #phy-cells = <1>; - - reset-names = "miphy-sw-rst"; - resets = <&softreset STIH407_MIPHY0_SOFTRESET>; - }; - - phy_port1: port@9b2a000 { - reg = <0x9b2a000 0xff>, - <0x9b19000 0xff>, - <0x9b14000 0xff>; - reg-names = "sata-up", - "pcie-up", - "pipew"; - - st,syscfg = <0x118 0x81c 0xe4 0xf0>; - - #phy-cells = <1>; - - reset-names = "miphy-sw-rst"; - resets = <&softreset STIH407_MIPHY1_SOFTRESET>; - }; - - phy_port2: port@8f95000 { - reg = <0x8f95000 0xff>, - <0x8f90000 0xff>; - reg-names = "pipew", - "usb3-up"; - - st,syscfg = <0x11c 0x820>; - - #phy-cells = <1>; - - reset-names = "miphy-sw-rst"; - resets = <&softreset STIH407_MIPHY2_SOFTRESET>; - }; - }; - - spi@9840000 { - compatible = "st,comms-ssc4-spi"; - reg = <0x9840000 0x110>; - interrupts = ; - clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; - clock-names = "ssc"; - pinctrl-0 = <&pinctrl_spi0_default>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - spi@9841000 { - compatible = "st,comms-ssc4-spi"; - reg = <0x9841000 0x110>; - interrupts = ; - clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; - clock-names = "ssc"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1_default>; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - spi@9842000 { - compatible = "st,comms-ssc4-spi"; - reg = <0x9842000 0x110>; - interrupts = ; - clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; - clock-names = "ssc"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi2_default>; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - spi@9843000 { - compatible = "st,comms-ssc4-spi"; - reg = <0x9843000 0x110>; - interrupts = ; - clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; - clock-names = "ssc"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi3_default>; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - spi@9844000 { - compatible = "st,comms-ssc4-spi"; - reg = <0x9844000 0x110>; - interrupts = ; - clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; - clock-names = "ssc"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi4_default>; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - /* SBC SSC */ - spi@9540000 { - compatible = "st,comms-ssc4-spi"; - reg = <0x9540000 0x110>; - interrupts = ; - clocks = <&clk_sysin>; - clock-names = "ssc"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi10_default>; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - spi@9541000 { - compatible = "st,comms-ssc4-spi"; - reg = <0x9541000 0x110>; - interrupts = ; - clocks = <&clk_sysin>; - clock-names = "ssc"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi11_default>; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - spi@9542000 { - compatible = "st,comms-ssc4-spi"; - reg = <0x9542000 0x110>; - interrupts = ; - clocks = <&clk_sysin>; - clock-names = "ssc"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi12_default>; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - mmc0: sdhci@9060000 { - compatible = "st,sdhci-stih407", "st,sdhci"; - status = "disabled"; - reg = <0x09060000 0x7ff>, <0x9061008 0x20>; - reg-names = "mmc", "top-mmc-delay"; - interrupts = ; - interrupt-names = "mmcirq"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mmc0>; - clock-names = "mmc", "icn"; - clocks = <&clk_s_c0_flexgen CLK_MMC_0>, - <&clk_s_c0_flexgen CLK_RX_ICN_HVA>; - bus-width = <8>; - }; - - mmc1: sdhci@9080000 { - compatible = "st,sdhci-stih407", "st,sdhci"; - status = "disabled"; - reg = <0x09080000 0x7ff>; - reg-names = "mmc"; - interrupts = ; - interrupt-names = "mmcirq"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sd1>; - clock-names = "mmc", "icn"; - clocks = <&clk_s_c0_flexgen CLK_MMC_1>, - <&clk_s_c0_flexgen CLK_RX_ICN_HVA>; - resets = <&softreset STIH407_MMC1_SOFTRESET>; - bus-width = <4>; - }; - - /* Watchdog and Real-Time Clock */ - lpc@8787000 { - compatible = "st,stih407-lpc"; - reg = <0x8787000 0x1000>; - interrupts = ; - clocks = <&clk_s_d3_flexgen CLK_LPC_0>; - timeout-sec = <120>; - st,syscfg = <&syscfg_core>; - st,lpc-mode = ; - }; - - lpc@8788000 { - compatible = "st,stih407-lpc"; - reg = <0x8788000 0x1000>; - interrupts = ; - clocks = <&clk_s_d3_flexgen CLK_LPC_1>; - st,lpc-mode = ; - }; - - sata0: sata@9b20000 { - compatible = "st,ahci"; - reg = <0x9b20000 0x1000>; - - interrupts = ; - interrupt-names = "hostc"; - - phys = <&phy_port0 PHY_TYPE_SATA>; - phy-names = "ahci_phy"; - - resets = <&powerdown STIH407_SATA0_POWERDOWN>, - <&softreset STIH407_SATA0_SOFTRESET>, - <&softreset STIH407_SATA0_PWR_SOFTRESET>; - reset-names = "pwr-dwn", "sw-rst", "pwr-rst"; - - clock-names = "ahci_clk"; - clocks = <&clk_s_c0_flexgen CLK_ICN_REG>; - - ports-implemented = <0x1>; - - status = "disabled"; - }; - - sata1: sata@9b28000 { - compatible = "st,ahci"; - reg = <0x9b28000 0x1000>; - - interrupts = ; - interrupt-names = "hostc"; - - phys = <&phy_port1 PHY_TYPE_SATA>; - phy-names = "ahci_phy"; - - resets = <&powerdown STIH407_SATA1_POWERDOWN>, - <&softreset STIH407_SATA1_SOFTRESET>, - <&softreset STIH407_SATA1_PWR_SOFTRESET>; - reset-names = "pwr-dwn", - "sw-rst", - "pwr-rst"; - - clock-names = "ahci_clk"; - clocks = <&clk_s_c0_flexgen CLK_ICN_REG>; - - ports-implemented = <0x1>; - - status = "disabled"; - }; - - - st_dwc3: dwc3@8f94000 { - compatible = "st,stih407-dwc3"; - reg = <0x08f94000 0x1000>, <0x110 0x4>; - reg-names = "reg-glue", "syscfg-reg"; - st,syscfg = <&syscfg_core>; - resets = <&powerdown STIH407_USB3_POWERDOWN>, - <&softreset STIH407_MIPHY2_SOFTRESET>; - reset-names = "powerdown", "softreset"; - #address-cells = <1>; - #size-cells = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb3>; - ranges; - - status = "disabled"; - - dwc3: dwc3@9900000 { - compatible = "snps,dwc3"; - reg = <0x09900000 0x100000>; - interrupts = ; - dr_mode = "host"; - phy-names = "usb2-phy", "usb3-phy"; - phys = <&usb2_picophy0>, - <&phy_port2 PHY_TYPE_USB3>; - snps,dis_u3_susphy_quirk; - }; - }; - - /* COMMS PWM Module */ - pwm0: pwm@9810000 { - compatible = "st,sti-pwm"; - #pwm-cells = <2>; - reg = <0x9810000 0x68>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm0_chan0_default>; - clock-names = "pwm"; - clocks = <&clk_sysin>; - st,pwm-num-chan = <1>; - - status = "disabled"; - }; - - /* SBC PWM Module */ - pwm1: pwm@9510000 { - compatible = "st,sti-pwm"; - #pwm-cells = <2>; - reg = <0x9510000 0x68>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1_chan0_default - &pinctrl_pwm1_chan1_default - &pinctrl_pwm1_chan2_default - &pinctrl_pwm1_chan3_default>; - clock-names = "pwm"; - clocks = <&clk_sysin>; - st,pwm-num-chan = <4>; - - status = "disabled"; - }; - - rng10: rng@8a89000 { - compatible = "st,rng"; - reg = <0x08a89000 0x1000>; - clocks = <&clk_sysin>; - status = "okay"; - }; - - rng11: rng@8a8a000 { - compatible = "st,rng"; - reg = <0x08a8a000 0x1000>; - clocks = <&clk_sysin>; - status = "okay"; - }; - - ethernet0: dwmac@9630000 { - device_type = "network"; - status = "disabled"; - compatible = "st,stih407-dwmac", "snps,dwmac", "snps,dwmac-3.710"; - reg = <0x9630000 0x8000>, <0x80 0x4>; - reg-names = "stmmaceth", "sti-ethconf"; - - st,syscon = <&syscfg_sbc_reg 0x80>; - st,gmac_en; - resets = <&softreset STIH407_ETH1_SOFTRESET>; - reset-names = "stmmaceth"; - - interrupts = , - ; - interrupt-names = "macirq", "eth_wake_irq"; - - /* DMA Bus Mode */ - snps,pbl = <8>; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rgmii1>; - - clock-names = "stmmaceth", "sti-ethclk"; - clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>, - <&clk_s_c0_flexgen CLK_ETH_PHY>; - }; - - rng10: rng@8a89000 { - compatible = "st,rng"; - reg = <0x08a89000 0x1000>; - clocks = <&clk_sysin>; - status = "okay"; - }; - - rng11: rng@8a8a000 { - compatible = "st,rng"; - reg = <0x08a8a000 0x1000>; - clocks = <&clk_sysin>; - status = "okay"; - }; - - mailbox0: mailbox@8f00000 { - compatible = "st,stih407-mailbox"; - reg = <0x8f00000 0x1000>; - interrupts = ; - #mbox-cells = <2>; - mbox-name = "a9"; - status = "okay"; - }; - - mailbox1: mailbox@8f01000 { - compatible = "st,stih407-mailbox"; - reg = <0x8f01000 0x1000>; - #mbox-cells = <2>; - mbox-name = "st231_gp_1"; - status = "okay"; - }; - - mailbox2: mailbox@8f02000 { - compatible = "st,stih407-mailbox"; - reg = <0x8f02000 0x1000>; - #mbox-cells = <2>; - mbox-name = "st231_gp_0"; - status = "okay"; - }; - - mailbox3: mailbox@8f03000 { - compatible = "st,stih407-mailbox"; - reg = <0x8f03000 0x1000>; - #mbox-cells = <2>; - mbox-name = "st231_audio_video"; - status = "okay"; - }; - - st231_gp0: st231-gp0@0 { - compatible = "st,st231-rproc"; - reg = <0 0>; - memory-region = <&gp0_reserved>; - resets = <&softreset STIH407_ST231_GP0_SOFTRESET>; - reset-names = "sw_reset"; - clocks = <&clk_s_c0_flexgen CLK_ST231_GP_0>; - clock-frequency = <600000000>; - st,syscfg = <&syscfg_core 0x22c>; - #mbox-cells = <1>; - mbox-names = "vq0_rx", "vq0_tx", "vq1_rx", "vq1_tx"; - mboxes = <&mailbox0 0 2>, <&mailbox2 0 1>, <&mailbox0 0 3>, <&mailbox2 0 0>; - }; - - st231_delta: st231-delta@0 { - compatible = "st,st231-rproc"; - reg = <0 0>; - memory-region = <&delta_reserved>; - resets = <&softreset STIH407_ST231_DMU_SOFTRESET>; - reset-names = "sw_reset"; - clocks = <&clk_s_c0_flexgen CLK_ST231_DMU>; - clock-frequency = <600000000>; - st,syscfg = <&syscfg_core 0x224>; - #mbox-cells = <1>; - mbox-names = "vq0_rx", "vq0_tx", "vq1_rx", "vq1_tx"; - mboxes = <&mailbox0 0 0>, <&mailbox3 0 1>, <&mailbox0 0 1>, <&mailbox3 0 0>; - }; - - /* fdma audio */ - fdma0: dma-controller@8e20000 { - compatible = "st,stih407-fdma-mpe31-11", "st,slim-rproc"; - reg = <0x8e20000 0x8000>, - <0x8e30000 0x3000>, - <0x8e37000 0x1000>, - <0x8e38000 0x8000>; - reg-names = "slimcore", "dmem", "peripherals", "imem"; - clocks = <&clk_s_c0_flexgen CLK_FDMA>, - <&clk_s_c0_flexgen CLK_EXT2F_A9>, - <&clk_s_c0_flexgen CLK_EXT2F_A9>, - <&clk_s_c0_flexgen CLK_EXT2F_A9>; - interrupts = ; - dma-channels = <16>; - #dma-cells = <3>; - }; - - /* fdma app */ - fdma1: dma-controller@8e40000 { - compatible = "st,stih407-fdma-mpe31-12", "st,slim-rproc"; - reg = <0x8e40000 0x8000>, - <0x8e50000 0x3000>, - <0x8e57000 0x1000>, - <0x8e58000 0x8000>; - reg-names = "slimcore", "dmem", "peripherals", "imem"; - clocks = <&clk_s_c0_flexgen CLK_FDMA>, - <&clk_s_c0_flexgen CLK_TX_ICN_DMU>, - <&clk_s_c0_flexgen CLK_TX_ICN_DMU>, - <&clk_s_c0_flexgen CLK_EXT2F_A9>; - - interrupts = ; - dma-channels = <16>; - #dma-cells = <3>; - - status = "disabled"; - }; - - /* fdma free running */ - fdma2: dma-controller@8e60000 { - compatible = "st,stih407-fdma-mpe31-13", "st,slim-rproc"; - reg = <0x8e60000 0x8000>, - <0x8e70000 0x3000>, - <0x8e77000 0x1000>, - <0x8e78000 0x8000>; - reg-names = "slimcore", "dmem", "peripherals", "imem"; - interrupts = ; - dma-channels = <16>; - #dma-cells = <3>; - clocks = <&clk_s_c0_flexgen CLK_FDMA>, - <&clk_s_c0_flexgen CLK_EXT2F_A9>, - <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>, - <&clk_s_c0_flexgen CLK_EXT2F_A9>; - - status = "disabled"; - }; - - sti_uni_player0: sti-uni-player@8d80000 { - compatible = "st,stih407-uni-player-hdmi"; - #sound-dai-cells = <0>; - st,syscfg = <&syscfg_core>; - clocks = <&clk_s_d0_flexgen CLK_PCM_0>; - assigned-clocks = <&clk_s_d0_quadfs 0>, <&clk_s_d0_flexgen CLK_PCM_0>; - assigned-clock-parents = <0>, <&clk_s_d0_quadfs 0>; - assigned-clock-rates = <50000000>; - reg = <0x8d80000 0x158>; - interrupts = ; - dmas = <&fdma0 2 0 1>; - dma-names = "tx"; - - status = "disabled"; - }; - - sti_uni_player1: sti-uni-player@8d81000 { - compatible = "st,stih407-uni-player-pcm-out"; - #sound-dai-cells = <0>; - st,syscfg = <&syscfg_core>; - clocks = <&clk_s_d0_flexgen CLK_PCM_1>; - assigned-clocks = <&clk_s_d0_quadfs 1>, <&clk_s_d0_flexgen CLK_PCM_1>; - assigned-clock-parents = <0>, <&clk_s_d0_quadfs 1>; - assigned-clock-rates = <50000000>; - reg = <0x8d81000 0x158>; - interrupts = ; - dmas = <&fdma0 3 0 1>; - dma-names = "tx"; - - status = "disabled"; - }; - - sti_uni_player2: sti-uni-player@8d82000 { - compatible = "st,stih407-uni-player-dac"; - #sound-dai-cells = <0>; - st,syscfg = <&syscfg_core>; - clocks = <&clk_s_d0_flexgen CLK_PCM_2>; - assigned-clocks = <&clk_s_d0_quadfs 2>, <&clk_s_d0_flexgen CLK_PCM_2>; - assigned-clock-parents = <0>, <&clk_s_d0_quadfs 2>; - assigned-clock-rates = <50000000>; - reg = <0x8d82000 0x158>; - interrupts = ; - dmas = <&fdma0 4 0 1>; - dma-names = "tx"; - - status = "disabled"; - }; - - sti_uni_player3: sti-uni-player@8d85000 { - compatible = "st,stih407-uni-player-spdif"; - #sound-dai-cells = <0>; - st,syscfg = <&syscfg_core>; - clocks = <&clk_s_d0_flexgen CLK_SPDIFF>; - assigned-clocks = <&clk_s_d0_quadfs 3>, <&clk_s_d0_flexgen CLK_SPDIFF>; - assigned-clock-parents = <0>, <&clk_s_d0_quadfs 3>; - assigned-clock-rates = <50000000>; - reg = <0x8d85000 0x158>; - interrupts = ; - dmas = <&fdma0 7 0 1>; - dma-names = "tx"; - - status = "disabled"; - }; - - sti_uni_reader0: sti-uni-reader@8d83000 { - compatible = "st,stih407-uni-reader-pcm_in"; - #sound-dai-cells = <0>; - st,syscfg = <&syscfg_core>; - reg = <0x8d83000 0x158>; - interrupts = ; - dmas = <&fdma0 5 0 1>; - dma-names = "rx"; - - status = "disabled"; - }; - - sti_uni_reader1: sti-uni-reader@8d84000 { - compatible = "st,stih407-uni-reader-hdmi"; - #sound-dai-cells = <0>; - st,syscfg = <&syscfg_core>; - reg = <0x8d84000 0x158>; - interrupts = ; - dmas = <&fdma0 6 0 1>; - dma-names = "rx"; - - status = "disabled"; - }; - - delta0@0 { - compatible = "st,st-delta"; - reg = <0 0>; - clock-names = "delta", - "delta-st231", - "delta-flash-promip"; - clocks = <&clk_s_c0_flexgen CLK_VID_DMU>, - <&clk_s_c0_flexgen CLK_ST231_DMU>, - <&clk_s_c0_flexgen CLK_FLASH_PROMIP>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/stih407-pinctrl.dtsi b/sys/gnu/dts/arm/stih407-pinctrl.dtsi deleted file mode 100644 index 2cf335714ca..00000000000 --- a/sys/gnu/dts/arm/stih407-pinctrl.dtsi +++ /dev/null @@ -1,1262 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 STMicroelectronics Limited. - * Author: Giuseppe Cavallaro - */ -#include "st-pincfg.h" -#include -/ { - - aliases { - /* 0-5: PIO_SBC */ - gpio0 = &pio0; - gpio1 = &pio1; - gpio2 = &pio2; - gpio3 = &pio3; - gpio4 = &pio4; - gpio5 = &pio5; - /* 10-19: PIO_FRONT0 */ - gpio6 = &pio10; - gpio7 = &pio11; - gpio8 = &pio12; - gpio9 = &pio13; - gpio10 = &pio14; - gpio11 = &pio15; - gpio12 = &pio16; - gpio13 = &pio17; - gpio14 = &pio18; - gpio15 = &pio19; - /* 20: PIO_FRONT1 */ - gpio16 = &pio20; - /* 30-35: PIO_REAR */ - gpio17 = &pio30; - gpio18 = &pio31; - gpio19 = &pio32; - gpio20 = &pio33; - gpio21 = &pio34; - gpio22 = &pio35; - /* 40-42: PIO_FLASH */ - gpio23 = &pio40; - gpio24 = &pio41; - gpio25 = &pio42; - }; - - soc { - pin-controller-sbc@961f080 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stih407-sbc-pinctrl"; - st,syscfg = <&syscfg_sbc>; - reg = <0x0961f080 0x4>; - reg-names = "irqmux"; - interrupts = ; - interrupt-names = "irqmux"; - ranges = <0 0x09610000 0x6000>; - - pio0: gpio@9610000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x0 0x100>; - st,bank-name = "PIO0"; - }; - pio1: gpio@9611000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1000 0x100>; - st,bank-name = "PIO1"; - }; - pio2: gpio@9612000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x2000 0x100>; - st,bank-name = "PIO2"; - }; - pio3: gpio@9613000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x3000 0x100>; - st,bank-name = "PIO3"; - }; - pio4: gpio@9614000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x4000 0x100>; - st,bank-name = "PIO4"; - }; - - pio5: gpio@9615000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x5000 0x100>; - st,bank-name = "PIO5"; - st,retime-pin-mask = <0x3f>; - }; - - cec0 { - pinctrl_cec0_default: cec0-default { - st,pins { - hdmi_cec = <&pio2 4 ALT1 BIDIR>; - }; - }; - }; - - rc { - pinctrl_ir: ir0 { - st,pins { - ir = <&pio4 0 ALT2 IN>; - }; - }; - - pinctrl_uhf: uhf0 { - st,pins { - ir = <&pio4 1 ALT2 IN>; - }; - }; - - pinctrl_tx: tx0 { - st,pins { - tx = <&pio4 2 ALT2 OUT>; - }; - }; - - pinctrl_tx_od: tx_od0 { - st,pins { - tx_od = <&pio4 3 ALT2 OUT>; - }; - }; - }; - - /* SBC_ASC0 - UART10 */ - sbc_serial0 { - pinctrl_sbc_serial0: sbc_serial0-0 { - st,pins { - tx = <&pio3 4 ALT1 OUT>; - rx = <&pio3 5 ALT1 IN>; - }; - }; - }; - /* SBC_ASC1 - UART11 */ - sbc_serial1 { - pinctrl_sbc_serial1: sbc_serial1-0 { - st,pins { - tx = <&pio2 6 ALT3 OUT>; - rx = <&pio2 7 ALT3 IN>; - }; - }; - }; - - i2c10 { - pinctrl_i2c10_default: i2c10-default { - st,pins { - sda = <&pio4 6 ALT1 BIDIR>; - scl = <&pio4 5 ALT1 BIDIR>; - }; - }; - }; - - i2c11 { - pinctrl_i2c11_default: i2c11-default { - st,pins { - sda = <&pio5 1 ALT1 BIDIR>; - scl = <&pio5 0 ALT1 BIDIR>; - }; - }; - }; - - keyscan { - pinctrl_keyscan: keyscan { - st,pins { - keyin0 = <&pio4 0 ALT6 IN>; - keyin1 = <&pio4 5 ALT4 IN>; - keyin2 = <&pio0 4 ALT2 IN>; - keyin3 = <&pio2 6 ALT2 IN>; - - keyout0 = <&pio4 6 ALT4 OUT>; - keyout1 = <&pio1 7 ALT2 OUT>; - keyout2 = <&pio0 6 ALT2 OUT>; - keyout3 = <&pio2 7 ALT2 OUT>; - }; - }; - }; - - gmac1 { - /* - * Almost all the boards based on STiH407 SoC have an embedded - * switch where the mdio/mdc have been used for managing the SMI - * iface via I2C. For this reason these lines can be allocated - * by using dedicated configuration (in case of there will be a - * standard PHY transceiver on-board). - */ - pinctrl_rgmii1: rgmii1-0 { - st,pins { - - txd0 = <&pio0 0 ALT1 OUT DE_IO 0 CLK_A>; - txd1 = <&pio0 1 ALT1 OUT DE_IO 0 CLK_A>; - txd2 = <&pio0 2 ALT1 OUT DE_IO 0 CLK_A>; - txd3 = <&pio0 3 ALT1 OUT DE_IO 0 CLK_A>; - txen = <&pio0 5 ALT1 OUT DE_IO 0 CLK_A>; - txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>; - rxd0 = <&pio1 4 ALT1 IN DE_IO 0 CLK_A>; - rxd1 = <&pio1 5 ALT1 IN DE_IO 0 CLK_A>; - rxd2 = <&pio1 6 ALT1 IN DE_IO 0 CLK_A>; - rxd3 = <&pio1 7 ALT1 IN DE_IO 0 CLK_A>; - rxdv = <&pio2 0 ALT1 IN DE_IO 0 CLK_A>; - rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>; - clk125 = <&pio3 7 ALT4 IN NICLK 0 CLK_A>; - phyclk = <&pio2 3 ALT4 OUT NICLK 1250 CLK_B>; - }; - }; - - pinctrl_rgmii1_mdio: rgmii1-mdio { - st,pins { - mdio = <&pio1 0 ALT1 OUT BYPASS 0>; - mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>; - mdint = <&pio1 3 ALT1 IN BYPASS 0>; - }; - }; - - pinctrl_rgmii1_mdio_1: rgmii1-mdio-1 { - st,pins { - mdio = <&pio1 0 ALT1 OUT BYPASS 0>; - mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>; - }; - }; - - pinctrl_mii1: mii1 { - st,pins { - txd0 = <&pio0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txd1 = <&pio0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txd2 = <&pio0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txd3 = <&pio0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txer = <&pio0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txen = <&pio0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>; - col = <&pio0 7 ALT1 IN BYPASS 1000>; - - mdio = <&pio1 0 ALT1 OUT BYPASS 1500>; - mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>; - crs = <&pio1 2 ALT1 IN BYPASS 1000>; - mdint = <&pio1 3 ALT1 IN BYPASS 0>; - rxd0 = <&pio1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; - rxd1 = <&pio1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>; - rxd2 = <&pio1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>; - rxd3 = <&pio1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>; - - rxdv = <&pio2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; - rx_er = <&pio2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; - rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>; - phyclk = <&pio2 3 ALT1 OUT NICLK 0 CLK_A>; - }; - }; - - pinctrl_rmii1: rmii1-0 { - st,pins { - txd0 = <&pio0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txd1 = <&pio0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txen = <&pio0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - mdio = <&pio1 0 ALT1 OUT BYPASS 0>; - mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>; - mdint = <&pio1 3 ALT1 IN BYPASS 0>; - rxd0 = <&pio1 4 ALT1 IN SE_NICLK_IO 0 CLK_B>; - rxd1 = <&pio1 5 ALT1 IN SE_NICLK_IO 0 CLK_B>; - rxdv = <&pio2 0 ALT1 IN SE_NICLK_IO 0 CLK_B>; - rx_er = <&pio2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; - }; - }; - - pinctrl_rmii1_phyclk: rmii1_phyclk { - st,pins { - phyclk = <&pio2 3 ALT1 OUT NICLK 0 CLK_A>; - }; - }; - - pinctrl_rmii1_phyclk_ext: rmii1_phyclk_ext { - st,pins { - phyclk = <&pio2 3 ALT2 IN NICLK 0 CLK_A>; - }; - }; - }; - - pwm1 { - pinctrl_pwm1_chan0_default: pwm1-0-default { - st,pins { - pwm-out = <&pio3 0 ALT1 OUT>; - pwm-capturein = <&pio3 2 ALT1 IN>; - }; - }; - pinctrl_pwm1_chan1_default: pwm1-1-default { - st,pins { - pwm-capturein = <&pio4 3 ALT1 IN>; - pwm-out = <&pio4 4 ALT1 OUT>; - }; - }; - pinctrl_pwm1_chan2_default: pwm1-2-default { - st,pins { - pwm-out = <&pio4 6 ALT3 OUT>; - }; - }; - pinctrl_pwm1_chan3_default: pwm1-3-default { - st,pins { - pwm-out = <&pio4 7 ALT3 OUT>; - }; - }; - }; - - spi10 { - pinctrl_spi10_default: spi10-4w-alt1-0 { - st,pins { - mtsr = <&pio4 6 ALT1 OUT>; - mrst = <&pio4 7 ALT1 IN>; - scl = <&pio4 5 ALT1 OUT>; - }; - }; - - pinctrl_spi10_3w_alt1_0: spi10-3w-alt1-0 { - st,pins { - mtsr = <&pio4 6 ALT1 BIDIR_PU>; - scl = <&pio4 5 ALT1 OUT>; - }; - }; - }; - - spi11 { - pinctrl_spi11_default: spi11-4w-alt2-0 { - st,pins { - mtsr = <&pio3 1 ALT2 OUT>; - mrst = <&pio3 0 ALT2 IN>; - scl = <&pio3 2 ALT2 OUT>; - }; - }; - - pinctrl_spi11_3w_alt2_0: spi11-3w-alt2-0 { - st,pins { - mtsr = <&pio3 1 ALT2 BIDIR_PU>; - scl = <&pio3 2 ALT2 OUT>; - }; - }; - }; - - spi12 { - pinctrl_spi12_default: spi12-4w-alt2-0 { - st,pins { - mtsr = <&pio3 6 ALT2 OUT>; - mrst = <&pio3 4 ALT2 IN>; - scl = <&pio3 7 ALT2 OUT>; - }; - }; - - pinctrl_spi12_3w_alt2_0: spi12-3w-alt2-0 { - st,pins { - mtsr = <&pio3 6 ALT2 BIDIR_PU>; - scl = <&pio3 7 ALT2 OUT>; - }; - }; - }; - }; - - pin-controller-front0@920f080 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stih407-front-pinctrl"; - st,syscfg = <&syscfg_front>; - reg = <0x0920f080 0x4>; - reg-names = "irqmux"; - interrupts = ; - interrupt-names = "irqmux"; - ranges = <0 0x09200000 0x10000>; - - pio10: pio@9200000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x0 0x100>; - st,bank-name = "PIO10"; - }; - pio11: pio@9201000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1000 0x100>; - st,bank-name = "PIO11"; - }; - pio12: pio@9202000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x2000 0x100>; - st,bank-name = "PIO12"; - }; - pio13: pio@9203000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x3000 0x100>; - st,bank-name = "PIO13"; - }; - pio14: pio@9204000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x4000 0x100>; - st,bank-name = "PIO14"; - }; - pio15: pio@9205000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x5000 0x100>; - st,bank-name = "PIO15"; - }; - pio16: pio@9206000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x6000 0x100>; - st,bank-name = "PIO16"; - }; - pio17: pio@9207000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x7000 0x100>; - st,bank-name = "PIO17"; - }; - pio18: pio@9208000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x8000 0x100>; - st,bank-name = "PIO18"; - }; - pio19: pio@9209000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x9000 0x100>; - st,bank-name = "PIO19"; - }; - - /* Comms */ - serial0 { - pinctrl_serial0: serial0-0 { - st,pins { - tx = <&pio17 0 ALT1 OUT>; - rx = <&pio17 1 ALT1 IN>; - }; - }; - pinctrl_serial0_hw_flowctrl: serial0-0_hw_flowctrl { - st,pins { - tx = <&pio17 0 ALT1 OUT>; - rx = <&pio17 1 ALT1 IN>; - cts = <&pio17 2 ALT1 IN>; - rts = <&pio17 3 ALT1 OUT>; - }; - }; - }; - - serial1 { - pinctrl_serial1: serial1-0 { - st,pins { - tx = <&pio16 0 ALT1 OUT>; - rx = <&pio16 1 ALT1 IN>; - }; - }; - }; - - serial2 { - pinctrl_serial2: serial2-0 { - st,pins { - tx = <&pio15 0 ALT1 OUT>; - rx = <&pio15 1 ALT1 IN>; - }; - }; - }; - - mmc1 { - pinctrl_sd1: sd1-0 { - st,pins { - sd_clk = <&pio19 3 ALT5 BIDIR NICLK 0 CLK_B>; - sd_cmd = <&pio19 2 ALT5 BIDIR_PU BYPASS 0>; - sd_dat0 = <&pio19 4 ALT5 BIDIR_PU BYPASS 0>; - sd_dat1 = <&pio19 5 ALT5 BIDIR_PU BYPASS 0>; - sd_dat2 = <&pio19 6 ALT5 BIDIR_PU BYPASS 0>; - sd_dat3 = <&pio19 7 ALT5 BIDIR_PU BYPASS 0>; - sd_led = <&pio16 6 ALT6 OUT>; - sd_pwren = <&pio16 7 ALT6 OUT>; - sd_cd = <&pio19 0 ALT6 IN>; - sd_wp = <&pio19 1 ALT6 IN>; - }; - }; - }; - - - i2c0 { - pinctrl_i2c0_default: i2c0-default { - st,pins { - sda = <&pio10 6 ALT2 BIDIR>; - scl = <&pio10 5 ALT2 BIDIR>; - }; - }; - }; - - i2c1 { - pinctrl_i2c1_default: i2c1-default { - st,pins { - sda = <&pio11 1 ALT2 BIDIR>; - scl = <&pio11 0 ALT2 BIDIR>; - }; - }; - }; - - i2c2 { - pinctrl_i2c2_default: i2c2-default { - st,pins { - sda = <&pio15 6 ALT2 BIDIR>; - scl = <&pio15 5 ALT2 BIDIR>; - }; - }; - - pinctrl_i2c2_alt2_1: i2c2-alt2-1 { - st,pins { - sda = <&pio12 6 ALT2 BIDIR>; - scl = <&pio12 5 ALT2 BIDIR>; - }; - }; - }; - - i2c3 { - pinctrl_i2c3_default: i2c3-alt1-0 { - st,pins { - sda = <&pio18 6 ALT1 BIDIR>; - scl = <&pio18 5 ALT1 BIDIR>; - }; - }; - pinctrl_i2c3_alt1_1: i2c3-alt1-1 { - st,pins { - sda = <&pio17 7 ALT1 BIDIR>; - scl = <&pio17 6 ALT1 BIDIR>; - }; - }; - pinctrl_i2c3_alt3_0: i2c3-alt3-0 { - st,pins { - sda = <&pio13 6 ALT3 BIDIR>; - scl = <&pio13 5 ALT3 BIDIR>; - }; - }; - }; - - spi0 { - pinctrl_spi0_default: spi0-4w-alt2-0 { - st,pins { - mtsr = <&pio10 6 ALT2 OUT>; - mrst = <&pio10 7 ALT2 IN>; - scl = <&pio10 5 ALT2 OUT>; - }; - }; - - pinctrl_spi0_3w_alt2_0: spi0-3w-alt2-0 { - st,pins { - mtsr = <&pio10 6 ALT2 BIDIR_PU>; - scl = <&pio10 5 ALT2 OUT>; - }; - }; - - pinctrl_spi0_4w_alt1_0: spi0-4w-alt1-0 { - st,pins { - mtsr = <&pio19 7 ALT1 OUT>; - mrst = <&pio19 5 ALT1 IN>; - scl = <&pio19 6 ALT1 OUT>; - }; - }; - - pinctrl_spi0_3w_alt1_0: spi0-3w-alt1-0 { - st,pins { - mtsr = <&pio19 7 ALT1 BIDIR_PU>; - scl = <&pio19 6 ALT1 OUT>; - }; - }; - }; - - spi1 { - pinctrl_spi1_default: spi1-4w-alt2-0 { - st,pins { - mtsr = <&pio11 1 ALT2 OUT>; - mrst = <&pio11 2 ALT2 IN>; - scl = <&pio11 0 ALT2 OUT>; - }; - }; - - pinctrl_spi1_3w_alt2_0: spi1-3w-alt2-0 { - st,pins { - mtsr = <&pio11 1 ALT2 BIDIR_PU>; - scl = <&pio11 0 ALT2 OUT>; - }; - }; - - pinctrl_spi1_4w_alt1_0: spi1-4w-alt1-0 { - st,pins { - mtsr = <&pio14 3 ALT1 OUT>; - mrst = <&pio14 4 ALT1 IN>; - scl = <&pio14 2 ALT1 OUT>; - }; - }; - - pinctrl_spi1_3w_alt1_0: spi1-3w-alt1-0 { - st,pins { - mtsr = <&pio14 3 ALT1 BIDIR_PU>; - scl = <&pio14 2 ALT1 OUT>; - }; - }; - }; - - spi2 { - pinctrl_spi2_default: spi2-4w-alt2-0 { - st,pins { - mtsr = <&pio12 6 ALT2 OUT>; - mrst = <&pio12 7 ALT2 IN>; - scl = <&pio12 5 ALT2 OUT>; - }; - }; - - pinctrl_spi2_3w_alt2_0: spi2-3w-alt2-0 { - st,pins { - mtsr = <&pio12 6 ALT2 BIDIR_PU>; - scl = <&pio12 5 ALT2 OUT>; - }; - }; - - pinctrl_spi2_4w_alt1_0: spi2-4w-alt1-0 { - st,pins { - mtsr = <&pio14 6 ALT1 OUT>; - mrst = <&pio14 7 ALT1 IN>; - scl = <&pio14 5 ALT1 OUT>; - }; - }; - - pinctrl_spi2_3w_alt1_0: spi2-3w-alt1-0 { - st,pins { - mtsr = <&pio14 6 ALT1 BIDIR_PU>; - scl = <&pio14 5 ALT1 OUT>; - }; - }; - - pinctrl_spi2_4w_alt2_1: spi2-4w-alt2-1 { - st,pins { - mtsr = <&pio15 6 ALT2 OUT>; - mrst = <&pio15 7 ALT2 IN>; - scl = <&pio15 5 ALT2 OUT>; - }; - }; - - pinctrl_spi2_3w_alt2_1: spi2-3w-alt2-1 { - st,pins { - mtsr = <&pio15 6 ALT2 BIDIR_PU>; - scl = <&pio15 5 ALT2 OUT>; - }; - }; - }; - - spi3 { - pinctrl_spi3_default: spi3-4w-alt3-0 { - st,pins { - mtsr = <&pio13 6 ALT3 OUT>; - mrst = <&pio13 7 ALT3 IN>; - scl = <&pio13 5 ALT3 OUT>; - }; - }; - - pinctrl_spi3_3w_alt3_0: spi3-3w-alt3-0 { - st,pins { - mtsr = <&pio13 6 ALT3 BIDIR_PU>; - scl = <&pio13 5 ALT3 OUT>; - }; - }; - - pinctrl_spi3_4w_alt1_0: spi3-4w-alt1-0 { - st,pins { - mtsr = <&pio17 7 ALT1 OUT>; - mrst = <&pio17 5 ALT1 IN>; - scl = <&pio17 6 ALT1 OUT>; - }; - }; - - pinctrl_spi3_3w_alt1_0: spi3-3w-alt1-0 { - st,pins { - mtsr = <&pio17 7 ALT1 BIDIR_PU>; - scl = <&pio17 6 ALT1 OUT>; - }; - }; - - pinctrl_spi3_4w_alt1_1: spi3-4w-alt1-1 { - st,pins { - mtsr = <&pio18 6 ALT1 OUT>; - mrst = <&pio18 7 ALT1 IN>; - scl = <&pio18 5 ALT1 OUT>; - }; - }; - - pinctrl_spi3_3w_alt1_1: spi3-3w-alt1-1 { - st,pins { - mtsr = <&pio18 6 ALT1 BIDIR_PU>; - scl = <&pio18 5 ALT1 OUT>; - }; - }; - }; - - tsin0 { - pinctrl_tsin0_parallel: tsin0_parallel { - st,pins { - DATA7 = <&pio10 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; - DATA6 = <&pio10 5 ALT1 IN SE_NICLK_IO 0 CLK_A>; - DATA5 = <&pio10 6 ALT1 IN SE_NICLK_IO 0 CLK_A>; - DATA4 = <&pio10 7 ALT1 IN SE_NICLK_IO 0 CLK_A>; - DATA3 = <&pio11 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; - DATA2 = <&pio11 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; - DATA1 = <&pio11 2 ALT1 IN SE_NICLK_IO 0 CLK_A>; - DATA0 = <&pio11 3 ALT1 IN SE_NICLK_IO 0 CLK_A>; - CLKIN = <&pio10 3 ALT1 IN CLKNOTDATA 0 CLK_A>; - VALID = <&pio10 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; - ERROR = <&pio10 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; - PKCLK = <&pio10 2 ALT1 IN SE_NICLK_IO 0 CLK_A>; - }; - }; - pinctrl_tsin0_serial: tsin0_serial { - st,pins { - DATA7 = <&pio10 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; - CLKIN = <&pio10 3 ALT1 IN CLKNOTDATA 0 CLK_A>; - VALID = <&pio10 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; - ERROR = <&pio10 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; - PKCLK = <&pio10 2 ALT1 IN SE_NICLK_IO 0 CLK_A>; - }; - }; - }; - - tsin1 { - pinctrl_tsin1_parallel: tsin1_parallel { - st,pins { - DATA7 = <&pio12 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; - DATA6 = <&pio12 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; - DATA5 = <&pio12 2 ALT1 IN SE_NICLK_IO 0 CLK_A>; - DATA4 = <&pio12 3 ALT1 IN SE_NICLK_IO 0 CLK_A>; - DATA3 = <&pio12 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; - DATA2 = <&pio12 5 ALT1 IN SE_NICLK_IO 0 CLK_A>; - DATA1 = <&pio12 6 ALT1 IN SE_NICLK_IO 0 CLK_A>; - DATA0 = <&pio12 7 ALT1 IN SE_NICLK_IO 0 CLK_A>; - CLKIN = <&pio11 7 ALT1 IN CLKNOTDATA 0 CLK_A>; - VALID = <&pio11 5 ALT1 IN SE_NICLK_IO 0 CLK_A>; - ERROR = <&pio11 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; - PKCLK = <&pio11 6 ALT1 IN SE_NICLK_IO 0 CLK_A>; - }; - }; - pinctrl_tsin1_serial: tsin1_serial { - st,pins { - DATA7 = <&pio12 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; - CLKIN = <&pio11 7 ALT1 IN CLKNOTDATA 0 CLK_A>; - VALID = <&pio11 5 ALT1 IN SE_NICLK_IO 0 CLK_A>; - ERROR = <&pio11 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; - PKCLK = <&pio11 6 ALT1 IN SE_NICLK_IO 0 CLK_A>; - }; - }; - }; - - tsin2 { - pinctrl_tsin2_parallel: tsin2_parallel { - st,pins { - DATA7 = <&pio13 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; - DATA6 = <&pio13 5 ALT2 IN SE_NICLK_IO 0 CLK_B>; - DATA5 = <&pio13 6 ALT2 IN SE_NICLK_IO 0 CLK_B>; - DATA4 = <&pio13 7 ALT2 IN SE_NICLK_IO 0 CLK_B>; - DATA3 = <&pio14 0 ALT2 IN SE_NICLK_IO 0 CLK_A>; - DATA2 = <&pio14 1 ALT2 IN SE_NICLK_IO 0 CLK_B>; - DATA1 = <&pio14 2 ALT2 IN SE_NICLK_IO 0 CLK_A>; - DATA0 = <&pio14 3 ALT2 IN SE_NICLK_IO 0 CLK_A>; - CLKIN = <&pio13 3 ALT1 IN CLKNOTDATA 0 CLK_A>; - VALID = <&pio13 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; - ERROR = <&pio13 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; - PKCLK = <&pio13 2 ALT1 IN SE_NICLK_IO 0 CLK_A>; - }; - }; - pinctrl_tsin2_serial: tsin2_serial { - st,pins { - DATA7 = <&pio13 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; - CLKIN = <&pio13 3 ALT1 IN CLKNOTDATA 0 CLK_A>; - VALID = <&pio13 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; - ERROR = <&pio13 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; - PKCLK = <&pio13 2 ALT1 IN SE_NICLK_IO 0 CLK_A>; - }; - }; - }; - - tsin3 { - pinctrl_tsin3_serial: tsin3_serial { - st,pins { - DATA7 = <&pio14 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; - CLKIN = <&pio14 0 ALT1 IN CLKNOTDATA 0 CLK_A>; - VALID = <&pio13 6 ALT1 IN SE_NICLK_IO 0 CLK_A>; - ERROR = <&pio13 5 ALT1 IN SE_NICLK_IO 0 CLK_A>; - PKCLK = <&pio13 7 ALT1 IN SE_NICLK_IO 0 CLK_A>; - }; - }; - }; - - tsin4 { - pinctrl_tsin4_serial_alt3: tsin4_serial_alt3 { - st,pins { - DATA7 = <&pio14 6 ALT3 IN SE_NICLK_IO 0 CLK_A>; - CLKIN = <&pio14 5 ALT3 IN CLKNOTDATA 0 CLK_A>; - VALID = <&pio14 3 ALT3 IN SE_NICLK_IO 0 CLK_B>; - ERROR = <&pio14 2 ALT3 IN SE_NICLK_IO 0 CLK_B>; - PKCLK = <&pio14 4 ALT3 IN SE_NICLK_IO 0 CLK_A>; - }; - }; - }; - - tsin5 { - pinctrl_tsin5_serial_alt1: tsin5_serial_alt1 { - st,pins { - DATA7 = <&pio18 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; - CLKIN = <&pio18 3 ALT1 IN CLKNOTDATA 0 CLK_A>; - VALID = <&pio18 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; - ERROR = <&pio18 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; - PKCLK = <&pio18 2 ALT1 IN SE_NICLK_IO 0 CLK_A>; - }; - }; - pinctrl_tsin5_serial_alt2: tsin5_serial_alt2 { - st,pins { - DATA7 = <&pio19 4 ALT2 IN SE_NICLK_IO 0 CLK_A>; - CLKIN = <&pio19 3 ALT2 IN CLKNOTDATA 0 CLK_A>; - VALID = <&pio19 1 ALT2 IN SE_NICLK_IO 0 CLK_A>; - ERROR = <&pio19 0 ALT2 IN SE_NICLK_IO 0 CLK_A>; - PKCLK = <&pio19 2 ALT2 IN SE_NICLK_IO 0 CLK_A>; - }; - }; - }; - - tsout0 { - pinctrl_tsout0_parallel: tsout0_parallel { - st,pins { - DATA7 = <&pio12 0 ALT3 OUT SE_NICLK_IO 0 CLK_A>; - DATA6 = <&pio12 1 ALT3 OUT SE_NICLK_IO 0 CLK_A>; - DATA5 = <&pio12 2 ALT3 OUT SE_NICLK_IO 0 CLK_A>; - DATA4 = <&pio12 3 ALT3 OUT SE_NICLK_IO 0 CLK_A>; - DATA3 = <&pio12 4 ALT3 OUT SE_NICLK_IO 0 CLK_A>; - DATA2 = <&pio12 5 ALT3 OUT SE_NICLK_IO 0 CLK_A>; - DATA1 = <&pio12 6 ALT3 OUT SE_NICLK_IO 0 CLK_A>; - DATA0 = <&pio12 7 ALT3 OUT SE_NICLK_IO 0 CLK_A>; - CLKIN = <&pio11 7 ALT3 OUT NICLK 0 CLK_A>; - VALID = <&pio11 5 ALT3 OUT SE_NICLK_IO 0 CLK_A>; - ERROR = <&pio11 4 ALT3 OUT SE_NICLK_IO 0 CLK_A>; - PKCLK = <&pio11 6 ALT3 OUT SE_NICLK_IO 0 CLK_A>; - }; - }; - pinctrl_tsout0_serial: tsout0_serial { - st,pins { - DATA7 = <&pio12 0 ALT3 OUT SE_NICLK_IO 0 CLK_A>; - CLKIN = <&pio11 7 ALT3 OUT NICLK 0 CLK_A>; - VALID = <&pio11 5 ALT3 OUT SE_NICLK_IO 0 CLK_A>; - ERROR = <&pio11 4 ALT3 OUT SE_NICLK_IO 0 CLK_A>; - PKCLK = <&pio11 6 ALT3 OUT SE_NICLK_IO 0 CLK_A>; - }; - }; - }; - - tsout1 { - pinctrl_tsout1_serial: tsout1_serial { - st,pins { - DATA7 = <&pio19 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - CLKIN = <&pio19 3 ALT1 OUT NICLK 0 CLK_A>; - VALID = <&pio19 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - ERROR = <&pio19 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - PKCLK = <&pio19 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - }; - }; - }; - - mtsin0 { - pinctrl_mtsin0_parallel: mtsin0_parallel { - st,pins { - DATA7 = <&pio10 4 ALT3 IN SE_NICLK_IO 0 CLK_A>; - DATA6 = <&pio10 5 ALT3 IN SE_NICLK_IO 0 CLK_A>; - DATA5 = <&pio10 6 ALT3 IN SE_NICLK_IO 0 CLK_A>; - DATA4 = <&pio10 7 ALT3 IN SE_NICLK_IO 0 CLK_A>; - DATA3 = <&pio11 0 ALT3 IN SE_NICLK_IO 0 CLK_A>; - DATA2 = <&pio11 1 ALT3 IN SE_NICLK_IO 0 CLK_A>; - DATA1 = <&pio11 2 ALT3 IN SE_NICLK_IO 0 CLK_A>; - DATA0 = <&pio11 3 ALT3 IN SE_NICLK_IO 0 CLK_A>; - CLKIN = <&pio10 3 ALT3 IN CLKNOTDATA 0 CLK_A>; - VALID = <&pio10 1 ALT3 IN SE_NICLK_IO 0 CLK_A>; - ERROR = <&pio10 0 ALT3 IN SE_NICLK_IO 0 CLK_A>; - PKCLK = <&pio10 2 ALT3 IN SE_NICLK_IO 0 CLK_A>; - }; - }; - }; - - systrace { - pinctrl_systrace_default: systrace-default { - st,pins { - trc_data0 = <&pio11 3 ALT5 OUT>; - trc_data1 = <&pio11 4 ALT5 OUT>; - trc_data2 = <&pio11 5 ALT5 OUT>; - trc_data3 = <&pio11 6 ALT5 OUT>; - trc_clk = <&pio11 7 ALT5 OUT>; - }; - }; - }; - }; - - pin-controller-front1@921f080 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stih407-front-pinctrl"; - st,syscfg = <&syscfg_front>; - reg = <0x0921f080 0x4>; - reg-names = "irqmux"; - interrupts = ; - interrupt-names = "irqmux"; - ranges = <0 0x09210000 0x10000>; - - pio20: pio@9210000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x0 0x100>; - st,bank-name = "PIO20"; - }; - - tsin4 { - pinctrl_tsin4_serial_alt1: tsin4_serial_alt1 { - st,pins { - DATA7 = <&pio20 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; - CLKIN = <&pio20 3 ALT1 IN CLKNOTDATA 0 CLK_A>; - VALID = <&pio20 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; - ERROR = <&pio20 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; - PKCLK = <&pio20 2 ALT1 IN SE_NICLK_IO 0 CLK_A>; - }; - }; - }; - }; - - pin-controller-rear@922f080 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stih407-rear-pinctrl"; - st,syscfg = <&syscfg_rear>; - reg = <0x0922f080 0x4>; - reg-names = "irqmux"; - interrupts = ; - interrupt-names = "irqmux"; - ranges = <0 0x09220000 0x6000>; - - pio30: gpio@9220000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x0 0x100>; - st,bank-name = "PIO30"; - }; - pio31: gpio@9221000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1000 0x100>; - st,bank-name = "PIO31"; - }; - pio32: gpio@9222000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x2000 0x100>; - st,bank-name = "PIO32"; - }; - pio33: gpio@9223000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x3000 0x100>; - st,bank-name = "PIO33"; - }; - pio34: gpio@9224000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x4000 0x100>; - st,bank-name = "PIO34"; - }; - pio35: gpio@9225000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x5000 0x100>; - st,bank-name = "PIO35"; - st,retime-pin-mask = <0x7f>; - }; - - i2c4 { - pinctrl_i2c4_default: i2c4-default { - st,pins { - sda = <&pio30 1 ALT1 BIDIR>; - scl = <&pio30 0 ALT1 BIDIR>; - }; - }; - }; - - i2c5 { - pinctrl_i2c5_default: i2c5-default { - st,pins { - sda = <&pio34 4 ALT1 BIDIR>; - scl = <&pio34 3 ALT1 BIDIR>; - }; - }; - }; - - usb3 { - pinctrl_usb3: usb3-2 { - st,pins { - usb-oc-detect = <&pio35 4 ALT1 IN>; - usb-pwr-enable = <&pio35 5 ALT1 OUT>; - usb-vbus-valid = <&pio35 6 ALT1 IN>; - }; - }; - }; - - pwm0 { - pinctrl_pwm0_chan0_default: pwm0-0-default { - st,pins { - pwm-capturein = <&pio31 0 ALT1 IN>; - pwm-out = <&pio31 1 ALT1 OUT>; - }; - }; - }; - - spi4 { - pinctrl_spi4_default: spi4-4w-alt1-0 { - st,pins { - mtsr = <&pio30 1 ALT1 OUT>; - mrst = <&pio30 2 ALT1 IN>; - scl = <&pio30 0 ALT1 OUT>; - }; - }; - - pinctrl_spi4_3w_alt1_0: spi4-3w-alt1-0 { - st,pins { - mtsr = <&pio30 1 ALT1 BIDIR_PU>; - scl = <&pio30 0 ALT1 OUT>; - }; - }; - - pinctrl_spi4_4w_alt3_0: spi4-4w-alt3-0 { - st,pins { - mtsr = <&pio34 1 ALT3 OUT>; - mrst = <&pio34 2 ALT3 IN>; - scl = <&pio34 0 ALT3 OUT>; - }; - }; - - pinctrl_spi4_3w_alt3_0: spi4-3w-alt3-0 { - st,pins { - mtsr = <&pio34 1 ALT3 BIDIR_PU>; - scl = <&pio34 0 ALT3 OUT>; - }; - }; - }; - - i2s_out { - pinctrl_i2s_8ch_out: i2s_8ch_out{ - st,pins { - mclk = <&pio33 5 ALT1 OUT>; - lrclk = <&pio33 7 ALT1 OUT>; - sclk = <&pio33 6 ALT1 OUT>; - data0 = <&pio33 4 ALT1 OUT>; - data1 = <&pio34 0 ALT1 OUT>; - data2 = <&pio34 1 ALT1 OUT>; - data3 = <&pio34 2 ALT1 OUT>; - }; - }; - - pinctrl_i2s_2ch_out: i2s_2ch_out{ - st,pins { - mclk = <&pio33 5 ALT1 OUT>; - lrclk = <&pio33 7 ALT1 OUT>; - sclk = <&pio33 6 ALT1 OUT>; - data0 = <&pio33 4 ALT1 OUT>; - }; - }; - }; - - i2s_in { - pinctrl_i2s_8ch_in: i2s_8ch_in{ - st,pins { - mclk = <&pio32 5 ALT1 IN>; - lrclk = <&pio32 7 ALT1 IN>; - sclk = <&pio32 6 ALT1 IN>; - data0 = <&pio32 4 ALT1 IN>; - data1 = <&pio33 0 ALT1 IN>; - data2 = <&pio33 1 ALT1 IN>; - data3 = <&pio33 2 ALT1 IN>; - data4 = <&pio33 3 ALT1 IN>; - }; - }; - - pinctrl_i2s_2ch_in: i2s_2ch_in{ - st,pins { - mclk = <&pio32 5 ALT1 IN>; - lrclk = <&pio32 7 ALT1 IN>; - sclk = <&pio32 6 ALT1 IN>; - data0 = <&pio32 4 ALT1 IN>; - }; - }; - }; - - spdif_out { - pinctrl_spdif_out: spdif_out{ - st,pins { - spdif_out = <&pio34 7 ALT1 OUT>; - }; - }; - }; - - serial3 { - pinctrl_serial3: serial3-0 { - st,pins { - tx = <&pio31 3 ALT1 OUT>; - rx = <&pio31 4 ALT1 IN>; - }; - }; - }; - }; - - pin-controller-flash@923f080 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stih407-flash-pinctrl"; - st,syscfg = <&syscfg_flash>; - reg = <0x0923f080 0x4>; - reg-names = "irqmux"; - interrupts = ; - interrupt-names = "irqmux"; - ranges = <0 0x09230000 0x3000>; - - pio40: gpio@9230000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0 0x100>; - st,bank-name = "PIO40"; - }; - pio41: gpio@9231000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1000 0x100>; - st,bank-name = "PIO41"; - }; - pio42: gpio@9232000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x2000 0x100>; - st,bank-name = "PIO42"; - }; - - mmc0 { - pinctrl_mmc0: mmc0-0 { - st,pins { - emmc_clk = <&pio40 6 ALT1 BIDIR>; - emmc_cmd = <&pio40 7 ALT1 BIDIR_PU>; - emmc_d0 = <&pio41 0 ALT1 BIDIR_PU>; - emmc_d1 = <&pio41 1 ALT1 BIDIR_PU>; - emmc_d2 = <&pio41 2 ALT1 BIDIR_PU>; - emmc_d3 = <&pio41 3 ALT1 BIDIR_PU>; - emmc_d4 = <&pio41 4 ALT1 BIDIR_PU>; - emmc_d5 = <&pio41 5 ALT1 BIDIR_PU>; - emmc_d6 = <&pio41 6 ALT1 BIDIR_PU>; - emmc_d7 = <&pio41 7 ALT1 BIDIR_PU>; - }; - }; - pinctrl_sd0: sd0-0 { - st,pins { - sd_clk = <&pio40 6 ALT1 BIDIR>; - sd_cmd = <&pio40 7 ALT1 BIDIR_PU>; - sd_dat0 = <&pio41 0 ALT1 BIDIR_PU>; - sd_dat1 = <&pio41 1 ALT1 BIDIR_PU>; - sd_dat2 = <&pio41 2 ALT1 BIDIR_PU>; - sd_dat3 = <&pio41 3 ALT1 BIDIR_PU>; - sd_led = <&pio42 0 ALT2 OUT>; - sd_pwren = <&pio42 2 ALT2 OUT>; - sd_vsel = <&pio42 3 ALT2 OUT>; - sd_cd = <&pio42 4 ALT2 IN>; - sd_wp = <&pio42 5 ALT2 IN>; - }; - }; - }; - - fsm { - pinctrl_fsm: fsm { - st,pins { - spi-fsm-clk = <&pio40 1 ALT1 OUT>; - spi-fsm-cs = <&pio40 0 ALT1 OUT>; - spi-fsm-mosi = <&pio40 2 ALT1 OUT>; - spi-fsm-miso = <&pio40 3 ALT1 IN>; - spi-fsm-hol = <&pio40 5 ALT1 OUT>; - spi-fsm-wp = <&pio40 4 ALT1 OUT>; - }; - }; - }; - - nand { - pinctrl_nand: nand { - st,pins { - nand_cs1 = <&pio40 6 ALT3 OUT>; - nand_cs0 = <&pio40 7 ALT3 OUT>; - nand_d0 = <&pio41 0 ALT3 BIDIR>; - nand_d1 = <&pio41 1 ALT3 BIDIR>; - nand_d2 = <&pio41 2 ALT3 BIDIR>; - nand_d3 = <&pio41 3 ALT3 BIDIR>; - nand_d4 = <&pio41 4 ALT3 BIDIR>; - nand_d5 = <&pio41 5 ALT3 BIDIR>; - nand_d6 = <&pio41 6 ALT3 BIDIR>; - nand_d7 = <&pio41 7 ALT3 BIDIR>; - nand_we = <&pio42 0 ALT3 OUT>; - nand_dqs = <&pio42 1 ALT3 OUT>; - nand_ale = <&pio42 2 ALT3 OUT>; - nand_cle = <&pio42 3 ALT3 OUT>; - nand_rnb = <&pio42 4 ALT3 IN>; - nand_oe = <&pio42 5 ALT3 OUT>; - }; - }; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/stih407.dtsi b/sys/gnu/dts/arm/stih407.dtsi deleted file mode 100644 index 9e212b0af89..00000000000 --- a/sys/gnu/dts/arm/stih407.dtsi +++ /dev/null @@ -1,145 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2015 STMicroelectronics Limited. - * Author: Gabriel Fernandez - */ -#include "stih407-clock.dtsi" -#include "stih407-family.dtsi" -#include -/ { - soc { - sti-display-subsystem@0 { - compatible = "st,sti-display-subsystem"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0 0>; - assigned-clocks = <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 1>, - <&clk_s_c0_pll1 0>, - <&clk_s_c0_flexgen CLK_COMPO_DVP>, - <&clk_s_c0_flexgen CLK_MAIN_DISP>, - <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>, - <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>, - <&clk_s_d2_flexgen CLK_PIX_GDP1>, - <&clk_s_d2_flexgen CLK_PIX_GDP2>, - <&clk_s_d2_flexgen CLK_PIX_GDP3>, - <&clk_s_d2_flexgen CLK_PIX_GDP4>; - - assigned-clock-parents = <0>, - <0>, - <0>, - <&clk_s_c0_pll1 0>, - <&clk_s_c0_pll1 0>, - <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 1>, - <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 0>; - - assigned-clock-rates = <297000000>, - <108000000>, - <0>, - <400000000>, - <400000000>; - - ranges; - - sti-compositor@9d11000 { - compatible = "st,stih407-compositor"; - reg = <0x9d11000 0x1000>; - - clock-names = "compo_main", - "compo_aux", - "pix_main", - "pix_aux", - "pix_gdp1", - "pix_gdp2", - "pix_gdp3", - "pix_gdp4", - "main_parent", - "aux_parent"; - - clocks = <&clk_s_c0_flexgen CLK_COMPO_DVP>, - <&clk_s_c0_flexgen CLK_COMPO_DVP>, - <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>, - <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>, - <&clk_s_d2_flexgen CLK_PIX_GDP1>, - <&clk_s_d2_flexgen CLK_PIX_GDP2>, - <&clk_s_d2_flexgen CLK_PIX_GDP3>, - <&clk_s_d2_flexgen CLK_PIX_GDP4>, - <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 1>; - - reset-names = "compo-main", "compo-aux"; - resets = <&softreset STIH407_COMPO_SOFTRESET>, - <&softreset STIH407_COMPO_SOFTRESET>; - st,vtg = <&vtg_main>, <&vtg_aux>; - }; - - sti-tvout@8d08000 { - compatible = "st,stih407-tvout"; - reg = <0x8d08000 0x1000>; - reg-names = "tvout-reg"; - reset-names = "tvout"; - resets = <&softreset STIH407_HDTVOUT_SOFTRESET>; - #address-cells = <1>; - #size-cells = <1>; - assigned-clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>, - <&clk_s_d2_flexgen CLK_TMDS_HDMI>, - <&clk_s_d2_flexgen CLK_REF_HDMIPHY>, - <&clk_s_d0_flexgen CLK_PCM_0>, - <&clk_s_d2_flexgen CLK_PIX_HDDAC>, - <&clk_s_d2_flexgen CLK_HDDAC>; - - assigned-clock-parents = <&clk_s_d2_quadfs 0>, - <&clk_tmdsout_hdmi>, - <&clk_s_d2_quadfs 0>, - <&clk_s_d0_quadfs 0>, - <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 0>; - }; - - sti_hdmi: sti-hdmi@8d04000 { - compatible = "st,stih407-hdmi"; - reg = <0x8d04000 0x1000>; - reg-names = "hdmi-reg"; - #sound-dai-cells = <0>; - interrupts = ; - interrupt-names = "irq"; - clock-names = "pix", - "tmds", - "phy", - "audio", - "main_parent", - "aux_parent"; - - clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>, - <&clk_s_d2_flexgen CLK_TMDS_HDMI>, - <&clk_s_d2_flexgen CLK_REF_HDMIPHY>, - <&clk_s_d0_flexgen CLK_PCM_0>, - <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 1>; - - hdmi,hpd-gpio = <&pio5 3 GPIO_ACTIVE_LOW>; - reset-names = "hdmi"; - resets = <&softreset STIH407_HDMI_TX_PHY_SOFTRESET>; - ddc = <&hdmiddc>; - }; - - sti-hda@8d02000 { - compatible = "st,stih407-hda"; - reg = <0x8d02000 0x400>, <0x92b0120 0x4>; - reg-names = "hda-reg", "video-dacs-ctrl"; - clock-names = "pix", - "hddac", - "main_parent", - "aux_parent"; - clocks = <&clk_s_d2_flexgen CLK_PIX_HDDAC>, - <&clk_s_d2_flexgen CLK_HDDAC>, - <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 1>; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/stih410-b2120.dts b/sys/gnu/dts/arm/stih410-b2120.dts deleted file mode 100644 index 158b2268748..00000000000 --- a/sys/gnu/dts/arm/stih410-b2120.dts +++ /dev/null @@ -1,67 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 STMicroelectronics (R&D) Limited. - * Author: Peter Griffin - */ -/dts-v1/; -#include "stih410.dtsi" -#include "stihxxx-b2120.dtsi" -/ { - model = "STiH410 B2120"; - compatible = "st,stih410-b2120", "st,stih410"; - - chosen { - bootargs = "clk_ignore_unused"; - stdout-path = &sbc_serial0; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x80000000>; - }; - - aliases { - serial0 = &sbc_serial0; - ethernet0 = ðernet0; - }; - - soc { - - mmc0: sdhci@9060000 { - max-frequency = <200000000>; - sd-uhs-sdr50; - sd-uhs-sdr104; - sd-uhs-ddr50; - }; - - usb2_picophy1: phy2@0 { - status = "okay"; - }; - - usb2_picophy2: phy3@0 { - status = "okay"; - }; - - ohci0: usb@9a03c00 { - status = "okay"; - }; - - ehci0: usb@9a03e00 { - status = "okay"; - }; - - ohci1: usb@9a83c00 { - status = "okay"; - }; - - ehci1: usb@9a83e00 { - status = "okay"; - }; - - sti-display-subsystem@0 { - sti-hda@8d02000 { - status = "okay"; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/stih410-b2260.dts b/sys/gnu/dts/arm/stih410-b2260.dts deleted file mode 100644 index e2bb5978314..00000000000 --- a/sys/gnu/dts/arm/stih410-b2260.dts +++ /dev/null @@ -1,211 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2016 STMicroelectronics (R&D) Limited. - * Author: Patrice Chotard - */ -/dts-v1/; -#include "stih410.dtsi" -#include - -/ { - model = "STiH410 B2260"; - compatible = "st,stih410-b2260", "st,stih410"; - - chosen { - bootargs = "clk_ignore_unused"; - stdout-path = &uart1; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x40000000>; - }; - - aliases { - serial1 = &uart1; - ethernet0 = ðernet0; - }; - - leds { - compatible = "gpio-leds"; - user_green_1 { - label = "User_green_1"; - gpios = <&pio1 3 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - - user_green_2 { - label = "User_green_2"; - gpios = <&pio4 1 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - user_green_3 { - label = "User_green_3"; - gpios = <&pio2 1 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - user_green_4 { - label = "User_green_4"; - gpios = <&pio2 5 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - }; - - sound: sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "STI-B2260"; - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - - simple-audio-card,dai-link@0 { - reg = <0>; - /* DAC */ - format = "i2s"; - mclk-fs = <128>; - cpu { - sound-dai = <&sti_uni_player0>; - }; - - codec { - sound-dai = <&sti_hdmi>; - }; - }; - }; - - soc { - /* Low speed expansion connector */ - uart0: serial@9830000 { - label = "LS-UART0"; - pinctrl-names = "default", "no-hw-flowctrl"; - pinctrl-0 = <&pinctrl_serial0_hw_flowctrl>; - pinctrl-1 = <&pinctrl_serial0>; - rts-gpios = <&pio17 3 GPIO_ACTIVE_LOW>; - uart-has-rtscts; - status = "okay"; - }; - - /* Low speed expansion connector */ - uart1: serial@9831000 { - label = "LS-UART1"; - status = "okay"; - }; - - /* Low speed expansion connector */ - spi0: spi@9844000 { - label = "LS-SPI0"; - cs-gpios = <&pio30 3 0>; - status = "okay"; - }; - - /* Low speed expansion connector */ - i2c0: i2c@9840000 { - label = "LS-I2C0"; - status = "okay"; - }; - - /* Low speed expansion connector */ - i2c1: i2c@9841000 { - label = "LS-I2C1"; - status = "okay"; - }; - - /* high speed expansion connector */ - i2c2: i2c@9842000 { - label = "HS-I2C2"; - pinctrl-0 = <&pinctrl_i2c2_alt2_1>; - status = "okay"; - }; - - /* high speed expansion connector */ - i2c3: i2c@9843000 { - label = "HS-I2C3"; - pinctrl-0 = <&pinctrl_i2c3_alt3_0>; - status = "okay"; - }; - - mmc0: sdhci@9060000 { - pinctrl-0 = <&pinctrl_sd0>; - bus-width = <4>; - status = "okay"; - }; - - /* high speed expansion connector */ - mmc1: sdhci@9080000 { - status = "okay"; - }; - - pwm0: pwm@9810000 { - status = "okay"; - }; - - pwm1: pwm@9510000 { - status = "okay"; - }; - - usb2_picophy1: phy2@0 { - status = "okay"; - }; - - usb2_picophy2: phy3@0 { - status = "okay"; - }; - - ohci0: usb@9a03c00 { - status = "okay"; - }; - - ehci0: usb@9a03e00 { - status = "okay"; - }; - - ohci1: usb@9a83c00 { - status = "okay"; - }; - - ehci1: usb@9a83e00 { - status = "okay"; - }; - - st_dwc3: dwc3@8f94000 { - status = "okay"; - }; - - ethernet0: dwmac@9630000 { - phy-mode = "rgmii"; - pinctrl-0 = <&pinctrl_rgmii1 &pinctrl_rgmii1_mdio_1>; - - snps,reset-gpio = <&pio0 7 0>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 1000000>; - - status = "okay"; - }; - - sti_uni_player0: sti-uni-player@8d80000 { - status = "okay"; - }; - /* SSC11 to HDMI */ - hdmiddc: i2c@9541000 { - /* HDMI V1.3a supports Standard mode only */ - clock-frequency = <100000>; - st,i2c-min-scl-pulse-width-us = <0>; - st,i2c-min-sda-pulse-width-us = <5>; - status = "okay"; - }; - - miphy28lp_phy: miphy28lp@0 { - - phy_port1: port@9b2a000 { - st,osc-force-ext; - }; - }; - - sata1: sata@9b28000 { - status = "okay"; - }; - }; -}; diff --git a/sys/gnu/dts/arm/stih410-clock.dtsi b/sys/gnu/dts/arm/stih410-clock.dtsi deleted file mode 100644 index 81a8c25d7ba..00000000000 --- a/sys/gnu/dts/arm/stih410-clock.dtsi +++ /dev/null @@ -1,333 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 STMicroelectronics R&D Limited - */ -#include -/ { - /* - * Fixed 30MHz oscillator inputs to SoC - */ - clk_sysin: clk-sysin { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <30000000>; - clock-output-names = "CLK_SYSIN"; - }; - - clk_tmdsout_hdmi: clk-tmdsout-hdmi { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - compatible = "st,stih410-clk", "simple-bus"; - - /* - * A9 PLL. - */ - clockgen-a9@92b0000 { - compatible = "st,clkgen-c32"; - reg = <0x92b0000 0xffff>; - - clockgen_a9_pll: clockgen-a9-pll { - #clock-cells = <1>; - compatible = "st,stih407-clkgen-plla9"; - - clocks = <&clk_sysin>; - - clock-output-names = "clockgen-a9-pll-odf"; - }; - }; - - /* - * ARM CPU related clocks. - */ - clk_m_a9: clk-m-a9@92b0000 { - #clock-cells = <0>; - compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux"; - reg = <0x92b0000 0x10000>; - - clocks = <&clockgen_a9_pll 0>, - <&clockgen_a9_pll 0>, - <&clk_s_c0_flexgen 13>, - <&clk_m_a9_ext2f_div2>; - /* - * ARM Peripheral clock for timers - */ - arm_periph_clk: clk-m-a9-periphs { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&clk_m_a9>; - clock-div = <2>; - clock-mult = <1>; - }; - }; - - clockgen-a@90ff000 { - compatible = "st,clkgen-c32"; - reg = <0x90ff000 0x1000>; - - clk_s_a0_pll: clk-s-a0-pll { - #clock-cells = <1>; - compatible = "st,clkgen-pll0"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-a0-pll-ofd-0"; - clock-critical = <0>; /* clk-s-a0-pll-ofd-0 */ - }; - - clk_s_a0_flexgen: clk-s-a0-flexgen { - compatible = "st,flexgen"; - - #clock-cells = <1>; - - clocks = <&clk_s_a0_pll 0>, - <&clk_sysin>; - - clock-output-names = "clk-ic-lmi0", - "clk-ic-lmi1"; - clock-critical = ; - }; - }; - - clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 { - #clock-cells = <1>; - compatible = "st,quadfs-pll"; - reg = <0x9103000 0x1000>; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-c0-fs0-ch0", - "clk-s-c0-fs0-ch1", - "clk-s-c0-fs0-ch2", - "clk-s-c0-fs0-ch3"; - clock-critical = <0>; /* clk-s-c0-fs0-ch0 */ - }; - - clk_s_c0: clockgen-c@9103000 { - compatible = "st,clkgen-c32"; - reg = <0x9103000 0x1000>; - - clk_s_c0_pll0: clk-s-c0-pll0 { - #clock-cells = <1>; - compatible = "st,clkgen-pll0"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-c0-pll0-odf-0"; - clock-critical = <0>; /* clk-s-c0-pll0-odf-0 */ - }; - - clk_s_c0_pll1: clk-s-c0-pll1 { - #clock-cells = <1>; - compatible = "st,clkgen-pll1"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-c0-pll1-odf-0"; - }; - - clk_s_c0_flexgen: clk-s-c0-flexgen { - #clock-cells = <1>; - compatible = "st,flexgen"; - - clocks = <&clk_s_c0_pll0 0>, - <&clk_s_c0_pll1 0>, - <&clk_s_c0_quadfs 0>, - <&clk_s_c0_quadfs 1>, - <&clk_s_c0_quadfs 2>, - <&clk_s_c0_quadfs 3>, - <&clk_sysin>; - - clock-output-names = "clk-icn-gpu", - "clk-fdma", - "clk-nand", - "clk-hva", - "clk-proc-stfe", - "clk-proc-tp", - "clk-rx-icn-dmu", - "clk-rx-icn-hva", - "clk-icn-cpu", - "clk-tx-icn-dmu", - "clk-mmc-0", - "clk-mmc-1", - "clk-jpegdec", - "clk-ext2fa9", - "clk-ic-bdisp-0", - "clk-ic-bdisp-1", - "clk-pp-dmu", - "clk-vid-dmu", - "clk-dss-lpc", - "clk-st231-aud-0", - "clk-st231-gp-1", - "clk-st231-dmu", - "clk-icn-lmi", - "clk-tx-icn-disp-1", - "clk-icn-sbc", - "clk-stfe-frc2", - "clk-eth-phy", - "clk-eth-ref-phyclk", - "clk-flash-promip", - "clk-main-disp", - "clk-aux-disp", - "clk-compo-dvp", - "clk-tx-icn-hades", - "clk-rx-icn-hades", - "clk-icn-reg-16", - "clk-pp-hades", - "clk-clust-hades", - "clk-hwpe-hades", - "clk-fc-hades"; - clock-critical = , - , - , - , - , - ; - - /* - * ARM Peripheral clock for timers - */ - clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - - clocks = <&clk_s_c0_flexgen 13>; - - clock-output-names = "clk-m-a9-ext2f-div2"; - - clock-div = <2>; - clock-mult = <1>; - }; - }; - }; - - clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 { - #clock-cells = <1>; - compatible = "st,quadfs"; - reg = <0x9104000 0x1000>; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-d0-fs0-ch0", - "clk-s-d0-fs0-ch1", - "clk-s-d0-fs0-ch2", - "clk-s-d0-fs0-ch3"; - }; - - clockgen-d0@9104000 { - compatible = "st,clkgen-c32"; - reg = <0x9104000 0x1000>; - - clk_s_d0_flexgen: clk-s-d0-flexgen { - #clock-cells = <1>; - compatible = "st,flexgen-audio", "st,flexgen"; - - clocks = <&clk_s_d0_quadfs 0>, - <&clk_s_d0_quadfs 1>, - <&clk_s_d0_quadfs 2>, - <&clk_s_d0_quadfs 3>, - <&clk_sysin>; - - clock-output-names = "clk-pcm-0", - "clk-pcm-1", - "clk-pcm-2", - "clk-spdiff", - "clk-pcmr10-master", - "clk-usb2-phy"; - }; - }; - - clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 { - #clock-cells = <1>; - compatible = "st,quadfs"; - reg = <0x9106000 0x1000>; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-d2-fs0-ch0", - "clk-s-d2-fs0-ch1", - "clk-s-d2-fs0-ch2", - "clk-s-d2-fs0-ch3"; - }; - - clockgen-d2@9106000 { - compatible = "st,clkgen-c32"; - reg = <0x9106000 0x1000>; - - clk_s_d2_flexgen: clk-s-d2-flexgen { - #clock-cells = <1>; - compatible = "st,flexgen-video", "st,flexgen"; - - clocks = <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 1>, - <&clk_s_d2_quadfs 2>, - <&clk_s_d2_quadfs 3>, - <&clk_sysin>, - <&clk_sysin>, - <&clk_tmdsout_hdmi>; - - clock-output-names = "clk-pix-main-disp", - "clk-pix-pip", - "clk-pix-gdp1", - "clk-pix-gdp2", - "clk-pix-gdp3", - "clk-pix-gdp4", - "clk-pix-aux-disp", - "clk-denc", - "clk-pix-hddac", - "clk-hddac", - "clk-sddac", - "clk-pix-dvo", - "clk-dvo", - "clk-pix-hdmi", - "clk-tmds-hdmi", - "clk-ref-hdmiphy"; - }; - }; - - clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 { - #clock-cells = <1>; - compatible = "st,quadfs"; - reg = <0x9107000 0x1000>; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-d3-fs0-ch0", - "clk-s-d3-fs0-ch1", - "clk-s-d3-fs0-ch2", - "clk-s-d3-fs0-ch3"; - }; - - clockgen-d3@9107000 { - compatible = "st,clkgen-c32"; - reg = <0x9107000 0x1000>; - - clk_s_d3_flexgen: clk-s-d3-flexgen { - #clock-cells = <1>; - compatible = "st,flexgen"; - - clocks = <&clk_s_d3_quadfs 0>, - <&clk_s_d3_quadfs 1>, - <&clk_s_d3_quadfs 2>, - <&clk_s_d3_quadfs 3>, - <&clk_sysin>; - - clock-output-names = "clk-stfe-frc1", - "clk-tsout-0", - "clk-tsout-1", - "clk-mchi", - "clk-vsens-compo", - "clk-frc1-remote", - "clk-lpc-0", - "clk-lpc-1"; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/stih410-pinctrl.dtsi b/sys/gnu/dts/arm/stih410-pinctrl.dtsi deleted file mode 100644 index e6eadd12441..00000000000 --- a/sys/gnu/dts/arm/stih410-pinctrl.dtsi +++ /dev/null @@ -1,31 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 STMicroelectronics Limited. - * Author: Peter Griffin - */ -#include "st-pincfg.h" -/ { - - soc { - pin-controller-rear@922f080 { - - usb0 { - pinctrl_usb0: usb2-0 { - st,pins { - usb-oc-detect = <&pio35 0 ALT1 IN>; - usb-pwr-enable = <&pio35 1 ALT1 OUT>; - }; - }; - }; - - usb1 { - pinctrl_usb1: usb2-1 { - st,pins { - usb-oc-detect = <&pio35 2 ALT1 IN>; - usb-pwr-enable = <&pio35 3 ALT1 OUT>; - }; - }; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/stih410.dtsi b/sys/gnu/dts/arm/stih410.dtsi deleted file mode 100644 index 6d847019c55..00000000000 --- a/sys/gnu/dts/arm/stih410.dtsi +++ /dev/null @@ -1,300 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 STMicroelectronics Limited. - * Author: Peter Griffin - */ -#include "stih410-clock.dtsi" -#include "stih407-family.dtsi" -#include "stih410-pinctrl.dtsi" -#include -/ { - aliases { - bdisp0 = &bdisp0; - }; - - soc { - usb2_picophy1: phy2@0 { - compatible = "st,stih407-usb2-phy"; - reg = <0 0>; - #phy-cells = <0>; - st,syscfg = <&syscfg_core 0xf8 0xf4>; - resets = <&softreset STIH407_PICOPHY_SOFTRESET>, - <&picophyreset STIH407_PICOPHY0_RESET>; - reset-names = "global", "port"; - - status = "disabled"; - }; - - usb2_picophy2: phy3@0 { - compatible = "st,stih407-usb2-phy"; - reg = <0 0>; - #phy-cells = <0>; - st,syscfg = <&syscfg_core 0xfc 0xf4>; - resets = <&softreset STIH407_PICOPHY_SOFTRESET>, - <&picophyreset STIH407_PICOPHY1_RESET>; - reset-names = "global", "port"; - - status = "disabled"; - }; - - ohci0: usb@9a03c00 { - compatible = "st,st-ohci-300x"; - reg = <0x9a03c00 0x100>; - interrupts = ; - clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>, - <&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>; - resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>, - <&softreset STIH407_USB2_PORT0_SOFTRESET>; - reset-names = "power", "softreset"; - phys = <&usb2_picophy1>; - phy-names = "usb"; - - status = "disabled"; - }; - - ehci0: usb@9a03e00 { - compatible = "st,st-ehci-300x"; - reg = <0x9a03e00 0x100>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb0>; - clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>, - <&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>; - resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>, - <&softreset STIH407_USB2_PORT0_SOFTRESET>; - reset-names = "power", "softreset"; - phys = <&usb2_picophy1>; - phy-names = "usb"; - - status = "disabled"; - }; - - ohci1: usb@9a83c00 { - compatible = "st,st-ohci-300x"; - reg = <0x9a83c00 0x100>; - interrupts = ; - clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>, - <&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>; - resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>, - <&softreset STIH407_USB2_PORT1_SOFTRESET>; - reset-names = "power", "softreset"; - phys = <&usb2_picophy2>; - phy-names = "usb"; - - status = "disabled"; - }; - - ehci1: usb@9a83e00 { - compatible = "st,st-ehci-300x"; - reg = <0x9a83e00 0x100>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb1>; - clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>, - <&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>; - resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>, - <&softreset STIH407_USB2_PORT1_SOFTRESET>; - reset-names = "power", "softreset"; - phys = <&usb2_picophy2>; - phy-names = "usb"; - - status = "disabled"; - }; - - sti-display-subsystem@0 { - compatible = "st,sti-display-subsystem"; - #address-cells = <1>; - #size-cells = <1>; - - reg = <0 0>; - assigned-clocks = <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 1>, - <&clk_s_c0_pll1 0>, - <&clk_s_c0_flexgen CLK_COMPO_DVP>, - <&clk_s_c0_flexgen CLK_MAIN_DISP>, - <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>, - <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>, - <&clk_s_d2_flexgen CLK_PIX_GDP1>, - <&clk_s_d2_flexgen CLK_PIX_GDP2>, - <&clk_s_d2_flexgen CLK_PIX_GDP3>, - <&clk_s_d2_flexgen CLK_PIX_GDP4>; - - assigned-clock-parents = <0>, - <0>, - <0>, - <&clk_s_c0_pll1 0>, - <&clk_s_c0_pll1 0>, - <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 1>, - <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 0>; - - assigned-clock-rates = <297000000>, - <297000000>, - <0>, - <400000000>, - <400000000>; - - ranges; - - sti-compositor@9d11000 { - compatible = "st,stih407-compositor"; - reg = <0x9d11000 0x1000>; - - clock-names = "compo_main", - "compo_aux", - "pix_main", - "pix_aux", - "pix_gdp1", - "pix_gdp2", - "pix_gdp3", - "pix_gdp4", - "main_parent", - "aux_parent"; - - clocks = <&clk_s_c0_flexgen CLK_COMPO_DVP>, - <&clk_s_c0_flexgen CLK_COMPO_DVP>, - <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>, - <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>, - <&clk_s_d2_flexgen CLK_PIX_GDP1>, - <&clk_s_d2_flexgen CLK_PIX_GDP2>, - <&clk_s_d2_flexgen CLK_PIX_GDP3>, - <&clk_s_d2_flexgen CLK_PIX_GDP4>, - <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 1>; - - reset-names = "compo-main", "compo-aux"; - resets = <&softreset STIH407_COMPO_SOFTRESET>, - <&softreset STIH407_COMPO_SOFTRESET>; - st,vtg = <&vtg_main>, <&vtg_aux>; - }; - - sti-tvout@8d08000 { - compatible = "st,stih407-tvout"; - reg = <0x8d08000 0x1000>; - reg-names = "tvout-reg"; - reset-names = "tvout"; - resets = <&softreset STIH407_HDTVOUT_SOFTRESET>; - #address-cells = <1>; - #size-cells = <1>; - assigned-clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>, - <&clk_s_d2_flexgen CLK_TMDS_HDMI>, - <&clk_s_d2_flexgen CLK_REF_HDMIPHY>, - <&clk_s_d0_flexgen CLK_PCM_0>, - <&clk_s_d2_flexgen CLK_PIX_HDDAC>, - <&clk_s_d2_flexgen CLK_HDDAC>; - - assigned-clock-parents = <&clk_s_d2_quadfs 0>, - <&clk_tmdsout_hdmi>, - <&clk_s_d2_quadfs 0>, - <&clk_s_d0_quadfs 0>, - <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 0>; - }; - - sti_hdmi: sti-hdmi@8d04000 { - compatible = "st,stih407-hdmi"; - reg = <0x8d04000 0x1000>; - reg-names = "hdmi-reg"; - #sound-dai-cells = <0>; - interrupts = ; - interrupt-names = "irq"; - clock-names = "pix", - "tmds", - "phy", - "audio", - "main_parent", - "aux_parent"; - - clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>, - <&clk_s_d2_flexgen CLK_TMDS_HDMI>, - <&clk_s_d2_flexgen CLK_REF_HDMIPHY>, - <&clk_s_d0_flexgen CLK_PCM_0>, - <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 1>; - - hdmi,hpd-gpio = <&pio5 3 GPIO_ACTIVE_LOW>; - reset-names = "hdmi"; - resets = <&softreset STIH407_HDMI_TX_PHY_SOFTRESET>; - ddc = <&hdmiddc>; - }; - - sti-hda@8d02000 { - compatible = "st,stih407-hda"; - status = "disabled"; - reg = <0x8d02000 0x400>, <0x92b0120 0x4>; - reg-names = "hda-reg", "video-dacs-ctrl"; - clock-names = "pix", - "hddac", - "main_parent", - "aux_parent"; - clocks = <&clk_s_d2_flexgen CLK_PIX_HDDAC>, - <&clk_s_d2_flexgen CLK_HDDAC>, - <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 1>; - }; - - sti-hqvdp@9c00000 { - compatible = "st,stih407-hqvdp"; - reg = <0x9C00000 0x100000>; - clock-names = "hqvdp", "pix_main"; - clocks = <&clk_s_c0_flexgen CLK_MAIN_DISP>, - <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>; - reset-names = "hqvdp"; - resets = <&softreset STIH407_HDQVDP_SOFTRESET>; - st,vtg = <&vtg_main>; - }; - }; - - bdisp0:bdisp@9f10000 { - compatible = "st,stih407-bdisp"; - reg = <0x9f10000 0x1000>; - interrupts = ; - clock-names = "bdisp"; - clocks = <&clk_s_c0_flexgen CLK_IC_BDISP_0>; - }; - - hva@8c85000 { - compatible = "st,st-hva"; - reg = <0x8c85000 0x400>, <0x6000000 0x40000>; - reg-names = "hva_registers", "hva_esram"; - interrupts = , - ; - clock-names = "clk_hva"; - clocks = <&clk_s_c0_flexgen CLK_HVA>; - }; - - thermal@91a0000 { - compatible = "st,stih407-thermal"; - reg = <0x91a0000 0x28>; - clock-names = "thermal"; - clocks = <&clk_sysin>; - interrupts = ; - }; - - delta0@0 { - compatible = "st,st-delta"; - clock-names = "delta", - "delta-st231", - "delta-flash-promip"; - clocks = <&clk_s_c0_flexgen CLK_VID_DMU>, - <&clk_s_c0_flexgen CLK_ST231_DMU>, - <&clk_s_c0_flexgen CLK_FLASH_PROMIP>; - }; - - sti-cec@94a087c { - compatible = "st,stih-cec"; - reg = <0x94a087c 0x64>; - clocks = <&clk_sysin>; - clock-names = "cec-clk"; - interrupts = ; - interrupt-names = "cec-irq"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_cec0_default>; - resets = <&softreset STIH407_LPM_SOFTRESET>; - hdmi-phandle = <&sti_hdmi>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/stih415-b2000.dts b/sys/gnu/dts/arm/stih415-b2000.dts deleted file mode 100644 index bdfbd3765db..00000000000 --- a/sys/gnu/dts/arm/stih415-b2000.dts +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright (C) 2013 STMicroelectronics (R&D) Limited. - * Author: Srinivas Kandagatla - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. - */ -/dts-v1/; -#include "stih415.dtsi" -#include "stih41x-b2000.dtsi" -/ { - model = "STiH415 B2000 Board"; - compatible = "st,stih415-b2000", "st,stih415"; -}; diff --git a/sys/gnu/dts/arm/stih415-b2020.dts b/sys/gnu/dts/arm/stih415-b2020.dts deleted file mode 100644 index 71903a87bd3..00000000000 --- a/sys/gnu/dts/arm/stih415-b2020.dts +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright (C) 2013 STMicroelectronics (R&D) Limited. - * Author: Srinivas Kandagatla - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. - */ -/dts-v1/; -#include "stih415.dtsi" -#include "stih41x-b2020.dtsi" -/ { - model = "STiH415 B2020 Board"; - compatible = "st,stih415-b2020", "st,stih415"; -}; diff --git a/sys/gnu/dts/arm/stih415-clock.dtsi b/sys/gnu/dts/arm/stih415-clock.dtsi deleted file mode 100644 index 3ee34514bc4..00000000000 --- a/sys/gnu/dts/arm/stih415-clock.dtsi +++ /dev/null @@ -1,533 +0,0 @@ -/* - * Copyright (C) 2013 STMicroelectronics (R&D) Limited - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include - -/ { - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - /* - * Fixed 30MHz oscillator input to SoC - */ - clk_sysin: clk-sysin { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <30000000>; - }; - - /* - * ClockGenAs on SASG1 - */ - clockgen-a@fee62000 { - reg = <0xfee62000 0xb48>; - - clk_s_a0_pll: clk-s-a0-pll { - #clock-cells = <1>; - compatible = "st,clkgena-plls-c65"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-a0-pll0-hs", - "clk-s-a0-pll0-ls", - "clk-s-a0-pll1"; - }; - - clk_s_a0_osc_prediv: clk-s-a0-osc-prediv { - #clock-cells = <0>; - compatible = "st,clkgena-prediv-c65", - "st,clkgena-prediv"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-a0-osc-prediv"; - }; - - clk_s_a0_hs: clk-s-a0-hs { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c65-hs", - "st,clkgena-divmux"; - - clocks = <&clk_s_a0_osc_prediv>, - <&clk_s_a0_pll 0>, /* PLL0 HS */ - <&clk_s_a0_pll 2>; /* PLL1 */ - - clock-output-names = "clk-s-fdma-0", - "clk-s-fdma-1", - ""; /* clk-s-jit-sense */ - /* Fourth output unused */ - }; - - clk_s_a0_ls: clk-s-a0-ls { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c65-ls", - "st,clkgena-divmux"; - - clocks = <&clk_s_a0_osc_prediv>, - <&clk_s_a0_pll 1>, /* PLL0 LS */ - <&clk_s_a0_pll 2>; /* PLL1 */ - - clock-output-names = "clk-s-icn-reg-0", - "clk-s-icn-if-0", - "clk-s-icn-reg-lp-0", - "clk-s-emiss", - "clk-s-eth1-phy", - "clk-s-mii-ref-out"; - /* Remaining outputs unused */ - }; - }; - - clockgen-a@fee81000 { - reg = <0xfee81000 0xb48>; - - clk_s_a1_pll: clk-s-a1-pll { - #clock-cells = <1>; - compatible = "st,clkgena-plls-c65"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-a1-pll0-hs", - "clk-s-a1-pll0-ls", - "clk-s-a1-pll1"; - }; - - clk_s_a1_osc_prediv: clk-s-a1-osc-prediv { - #clock-cells = <0>; - compatible = "st,clkgena-prediv-c65", - "st,clkgena-prediv"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-a1-osc-prediv"; - }; - - clk_s_a1_hs: clk-s-a1-hs { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c65-hs", - "st,clkgena-divmux"; - - clocks = <&clk_s_a1_osc_prediv>, - <&clk_s_a1_pll 0>, /* PLL0 HS */ - <&clk_s_a1_pll 2>; /* PLL1 */ - - clock-output-names = "", /* Reserved */ - "", /* Reserved */ - "clk-s-stac-phy", - "clk-s-vtac-tx-phy"; - }; - - clk_s_a1_ls: clk-s-a1-ls { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c65-ls", - "st,clkgena-divmux"; - - clocks = <&clk_s_a1_osc_prediv>, - <&clk_s_a1_pll 1>, /* PLL0 LS */ - <&clk_s_a1_pll 2>; /* PLL1 */ - - clock-output-names = "clk-s-icn-if-2", - "clk-s-card-mmc", - "clk-s-icn-if-1", - "clk-s-gmac0-phy", - "clk-s-nand-ctrl", - "", /* Reserved */ - "clk-s-mii0-ref-out", - ""; /* clk-s-stac-sys */ - /* Remaining outputs unused */ - }; - }; - - /* - * ClockGenAs on MPE41 - */ - clockgen-a@fde12000 { - reg = <0xfde12000 0xb50>; - - clk_m_a0_pll0: clk-m-a0-pll0 { - #clock-cells = <1>; - compatible = "st,plls-c32-a1x-0", "st,clkgen-plls-c32"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-m-a0-pll0-phi0", - "clk-m-a0-pll0-phi1", - "clk-m-a0-pll0-phi2", - "clk-m-a0-pll0-phi3"; - }; - - clk_m_a0_pll1: clk-m-a0-pll1 { - #clock-cells = <1>; - compatible = "st,plls-c32-a1x-1", "st,clkgen-plls-c32"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-m-a0-pll1-phi0", - "clk-m-a0-pll1-phi1", - "clk-m-a0-pll1-phi2", - "clk-m-a0-pll1-phi3"; - }; - - clk_m_a0_osc_prediv: clk-m-a0-osc-prediv { - #clock-cells = <0>; - compatible = "st,clkgena-prediv-c32", - "st,clkgena-prediv"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-m-a0-osc-prediv"; - }; - - clk_m_a0_div0: clk-m-a0-div0 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf0", - "st,clkgena-divmux"; - - clocks = <&clk_m_a0_osc_prediv>, - <&clk_m_a0_pll0 0>, /* PLL0 PHI0 */ - <&clk_m_a0_pll1 0>; /* PLL1 PHI0 */ - - clock-output-names = "clk-m-apb-pm", /* Unused */ - "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - "clk-m-pp-dmu-0", - "clk-m-pp-dmu-1", - "clk-m-icm-disp", - ""; /* Unused */ - }; - - clk_m_a0_div1: clk-m-a0-div1 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf1", - "st,clkgena-divmux"; - - clocks = <&clk_m_a0_osc_prediv>, - <&clk_m_a0_pll0 1>, /* PLL0 PHI1 */ - <&clk_m_a0_pll1 1>; /* PLL1 PHI1 */ - - clock-output-names = "", /* Unused */ - "", /* Unused */ - "clk-m-a9-ext2f", - "clk-m-st40rt", - "clk-m-st231-dmu-0", - "clk-m-st231-dmu-1", - "clk-m-st231-aud", - "clk-m-st231-gp-0"; - }; - - clk_m_a0_div2: clk-m-a0-div2 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf2", - "st,clkgena-divmux"; - - clocks = <&clk_m_a0_osc_prediv>, - <&clk_m_a0_pll0 2>, /* PLL0 PHI2 */ - <&clk_m_a0_pll1 2>; /* PLL1 PHI2 */ - - clock-output-names = "clk-m-st231-gp-1", - "clk-m-icn-cpu", - "clk-m-icn-stac", - "clk-m-icn-dmu-0", - "clk-m-icn-dmu-1", - "", /* Unused */ - "", /* Unused */ - ""; /* Unused */ - }; - - clk_m_a0_div3: clk-m-a0-div3 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf3", - "st,clkgena-divmux"; - - clocks = <&clk_m_a0_osc_prediv>, - <&clk_m_a0_pll0 3>, /* PLL0 PHI3 */ - <&clk_m_a0_pll1 3>; /* PLL1 PHI3 */ - - clock-output-names = "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - "clk-m-icn-eram", - "clk-m-a9-trace"; - }; - }; - - clockgen-a@fd6db000 { - reg = <0xfd6db000 0xb50>; - - clk_m_a1_pll0: clk-m-a1-pll0 { - #clock-cells = <1>; - compatible = "st,plls-c32-a1x-0", "st,clkgen-plls-c32"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-m-a1-pll0-phi0", - "clk-m-a1-pll0-phi1", - "clk-m-a1-pll0-phi2", - "clk-m-a1-pll0-phi3"; - }; - - clk_m_a1_pll1: clk-m-a1-pll1 { - #clock-cells = <1>; - compatible = "st,plls-c32-a1x-1", "st,clkgen-plls-c32"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-m-a1-pll1-phi0", - "clk-m-a1-pll1-phi1", - "clk-m-a1-pll1-phi2", - "clk-m-a1-pll1-phi3"; - }; - - clk_m_a1_osc_prediv: clk-m-a1-osc-prediv { - #clock-cells = <0>; - compatible = "st,clkgena-prediv-c32", - "st,clkgena-prediv"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-m-a1-osc-prediv"; - }; - - clk_m_a1_div0: clk-m-a1-div0 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf0", - "st,clkgena-divmux"; - - clocks = <&clk_m_a1_osc_prediv>, - <&clk_m_a1_pll0 0>, /* PLL0 PHI0 */ - <&clk_m_a1_pll1 0>; /* PLL1 PHI0 */ - - clock-output-names = "clk-m-fdma-12", - "clk-m-fdma-10", - "clk-m-fdma-11", - "clk-m-hva-lmi", - "clk-m-proc-sc", - "clk-m-tp", - "clk-m-icn-gpu", - "clk-m-icn-vdp-0"; - }; - - clk_m_a1_div1: clk-m-a1-div1 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf1", - "st,clkgena-divmux"; - - clocks = <&clk_m_a1_osc_prediv>, - <&clk_m_a1_pll0 1>, /* PLL0 PHI1 */ - <&clk_m_a1_pll1 1>; /* PLL1 PHI1 */ - - clock-output-names = "clk-m-icn-vdp-1", - "clk-m-icn-vdp-2", - "clk-m-icn-vdp-3", - "clk-m-prv-t1-bus", - "clk-m-icn-vdp-4", - "clk-m-icn-reg-10", - "", /* Unused */ - ""; /* clk-m-icn-st231 */ - }; - - clk_m_a1_div2: clk-m-a1-div2 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf2", - "st,clkgena-divmux"; - - clocks = <&clk_m_a1_osc_prediv>, - <&clk_m_a1_pll0 2>, /* PLL0 PHI2 */ - <&clk_m_a1_pll1 2>; /* PLL1 PHI2 */ - - clock-output-names = "clk-m-fvdp-proc-alt", - "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - ""; /* Unused */ - }; - - clk_m_a1_div3: clk-m-a1-div3 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf3", - "st,clkgena-divmux"; - - clocks = <&clk_m_a1_osc_prediv>, - <&clk_m_a1_pll0 3>, /* PLL0 PHI3 */ - <&clk_m_a1_pll1 3>; /* PLL1 PHI3 */ - - clock-output-names = "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - ""; /* Unused */ - }; - }; - - clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&clk_m_a0_div1 2>; - clock-div = <2>; - clock-mult = <1>; - }; - - clockgen-a@fd345000 { - reg = <0xfd345000 0xb50>; - - clk_m_a2_pll0: clk-m-a2-pll0 { - #clock-cells = <1>; - compatible = "st,plls-c32-a1x-0", "st,clkgen-plls-c32"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-m-a2-pll0-phi0", - "clk-m-a2-pll0-phi1", - "clk-m-a2-pll0-phi2", - "clk-m-a2-pll0-phi3"; - }; - - clk_m_a2_pll1: clk-m-a2-pll1 { - #clock-cells = <1>; - compatible = "st,plls-c32-a1x-1", "st,clkgen-plls-c32"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-m-a2-pll1-phi0", - "clk-m-a2-pll1-phi1", - "clk-m-a2-pll1-phi2", - "clk-m-a2-pll1-phi3"; - }; - - clk_m_a2_osc_prediv: clk-m-a2-osc-prediv { - #clock-cells = <0>; - compatible = "st,clkgena-prediv-c32", - "st,clkgena-prediv"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-m-a2-osc-prediv"; - }; - - clk_m_a2_div0: clk-m-a2-div0 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf0", - "st,clkgena-divmux"; - - clocks = <&clk_m_a2_osc_prediv>, - <&clk_m_a2_pll0 0>, /* PLL0 PHI0 */ - <&clk_m_a2_pll1 0>; /* PLL1 PHI0 */ - - clock-output-names = "clk-m-vtac-main-phy", - "clk-m-vtac-aux-phy", - "clk-m-stac-phy", - "clk-m-stac-sys", - "", /* clk-m-mpestac-pg */ - "", /* clk-m-mpestac-wc */ - "", /* clk-m-mpevtacaux-pg*/ - ""; /* clk-m-mpevtacmain-pg*/ - }; - - clk_m_a2_div1: clk-m-a2-div1 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf1", - "st,clkgena-divmux"; - - clocks = <&clk_m_a2_osc_prediv>, - <&clk_m_a2_pll0 1>, /* PLL0 PHI1 */ - <&clk_m_a2_pll1 1>; /* PLL1 PHI1 */ - - clock-output-names = "", /* clk-m-mpevtacrx0-wc */ - "", /* clk-m-mpevtacrx1-wc */ - "clk-m-compo-main", - "clk-m-compo-aux", - "clk-m-bdisp-0", - "clk-m-bdisp-1", - "clk-m-icn-bdisp-0", - "clk-m-icn-bdisp-1"; - }; - - clk_m_a2_div2: clk-m-a2-div2 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf2", - "st,clkgena-divmux"; - - clocks = <&clk_m_a2_osc_prediv>, - <&clk_m_a2_pll0 2>, /* PLL0 PHI2 */ - <&clk_m_a2_pll1 2>; /* PLL1 PHI2 */ - - clock-output-names = "", /* clk-m-icn-hqvdp0 */ - "", /* clk-m-icn-hqvdp1 */ - "clk-m-icn-compo", - "", /* clk-m-icn-vdpaux */ - "clk-m-icn-ts", - "clk-m-icn-reg-lp-10", - "clk-m-dcephy-impctrl", - ""; /* Unused */ - }; - - clk_m_a2_div3: clk-m-a2-div3 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf3", - "st,clkgena-divmux"; - - clocks = <&clk_m_a2_osc_prediv>, - <&clk_m_a2_pll0 3>, /* PLL0 PHI3 */ - <&clk_m_a2_pll1 3>; /* PLL1 PHI3 */ - - clock-output-names = ""; /* Unused */ - /* Remaining outputs unused */ - }; - }; - - /* - * A9 PLL - */ - clockgen-a9@fdde00d8 { - reg = <0xfdde00d8 0x70>; - - clockgen_a9_pll: clockgen-a9-pll { - #clock-cells = <1>; - compatible = "st,stih415-plls-c32-a9", "st,clkgen-plls-c32"; - - clocks = <&clk_sysin>; - clock-output-names = "clockgen-a9-pll-odf"; - }; - }; - - /* - * ARM CPU related clocks - */ - clk_m_a9: clk-m-a9@fdde00d8 { - #clock-cells = <0>; - compatible = "st,stih415-clkgen-a9-mux", "st,clkgen-mux"; - reg = <0xfdde00d8 0x4>; - clocks = <&clockgen_a9_pll 0>, - <&clockgen_a9_pll 0>, - <&clk_m_a0_div1 2>, - <&clk_m_a9_ext2f_div2>; - }; - - /* - * ARM Peripheral clock for timers - */ - arm_periph_clk: clk-m-a9-periphs { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&clk_m_a9>; - clock-div = <2>; - clock-mult = <1>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/stih415-pinctrl.dtsi b/sys/gnu/dts/arm/stih415-pinctrl.dtsi deleted file mode 100644 index 3791ad95dba..00000000000 --- a/sys/gnu/dts/arm/stih415-pinctrl.dtsi +++ /dev/null @@ -1,545 +0,0 @@ -/* - * Copyright (C) 2013 STMicroelectronics (R&D) Limited. - * Author: Srinivas Kandagatla - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. - */ -#include "st-pincfg.h" -#include -/ { - - aliases { - gpio0 = &pio0; - gpio1 = &pio1; - gpio2 = &pio2; - gpio3 = &pio3; - gpio4 = &pio4; - gpio5 = &pio5; - gpio6 = &pio6; - gpio7 = &pio7; - gpio8 = &pio8; - gpio9 = &pio9; - gpio10 = &pio10; - gpio11 = &pio11; - gpio12 = &pio12; - gpio13 = &pio13; - gpio14 = &pio14; - gpio15 = &pio15; - gpio16 = &pio16; - gpio17 = &pio17; - gpio18 = &pio18; - gpio19 = &pio100; - gpio20 = &pio101; - gpio21 = &pio102; - gpio22 = &pio103; - gpio23 = &pio104; - gpio24 = &pio105; - gpio25 = &pio106; - gpio26 = &pio107; - }; - - soc { - pin-controller-sbc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stih415-sbc-pinctrl"; - st,syscfg = <&syscfg_sbc>; - reg = <0xfe61f080 0x4>; - reg-names = "irqmux"; - interrupts = ; - interrupt-names = "irqmux"; - ranges = <0 0xfe610000 0x5000>; - - pio0: gpio@fe610000 { - gpio-controller; - #gpio-cells = <1>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0 0x100>; - st,bank-name = "PIO0"; - }; - pio1: gpio@fe611000 { - gpio-controller; - #gpio-cells = <1>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1000 0x100>; - st,bank-name = "PIO1"; - }; - pio2: gpio@fe612000 { - gpio-controller; - #gpio-cells = <1>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x2000 0x100>; - st,bank-name = "PIO2"; - }; - pio3: gpio@fe613000 { - gpio-controller; - #gpio-cells = <1>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x3000 0x100>; - st,bank-name = "PIO3"; - }; - pio4: gpio@fe614000 { - gpio-controller; - #gpio-cells = <1>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x4000 0x100>; - st,bank-name = "PIO4"; - }; - - sbc_serial1 { - pinctrl_sbc_serial1:sbc_serial1 { - st,pins { - tx = <&pio2 6 ALT3 OUT>; - rx = <&pio2 7 ALT3 IN>; - }; - }; - }; - - keyscan { - pinctrl_keyscan: keyscan { - st,pins { - keyin0 = <&pio0 2 ALT2 IN>; - keyin1 = <&pio0 3 ALT2 IN>; - keyin2 = <&pio0 4 ALT2 IN>; - keyin3 = <&pio2 6 ALT2 IN>; - - keyout0 = <&pio1 6 ALT2 OUT>; - keyout1 = <&pio1 7 ALT2 OUT>; - keyout2 = <&pio0 6 ALT2 OUT>; - keyout3 = <&pio2 7 ALT2 OUT>; - }; - }; - }; - - sbc_i2c0 { - pinctrl_sbc_i2c0_default: sbc_i2c0-default { - st,pins { - sda = <&pio4 6 ALT1 BIDIR>; - scl = <&pio4 5 ALT1 BIDIR>; - }; - }; - }; - - sbc_i2c1 { - pinctrl_sbc_i2c1_default: sbc_i2c1-default { - st,pins { - sda = <&pio3 2 ALT2 BIDIR>; - scl = <&pio3 1 ALT2 BIDIR>; - }; - }; - }; - - rc{ - pinctrl_ir: ir0 { - st,pins { - ir = <&pio4 0 ALT2 IN>; - }; - }; - }; - - gmac1 { - pinctrl_mii1: mii1 { - st,pins { - txd0 = <&pio0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txd1 = <&pio0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txd2 = <&pio0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txd3 = <&pio0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txer = <&pio0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txen = <&pio0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>; - col = <&pio0 7 ALT1 IN BYPASS 1000>; - mdio = <&pio1 0 ALT1 OUT BYPASS 0>; - mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>; - crs = <&pio1 2 ALT1 IN BYPASS 1000>; - mdint = <&pio1 3 ALT1 IN BYPASS 0>; - rxd0 = <&pio1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; - rxd1 = <&pio1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>; - rxd2 = <&pio1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>; - rxd3 = <&pio1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>; - rxdv = <&pio2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; - rx_er = <&pio2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; - rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>; - phyclk = <&pio2 3 ALT1 IN NICLK 1000 CLK_A>; - }; - }; - - pinctrl_rgmii1: rgmii1-0 { - st,pins { - txd0 = <&pio0 0 ALT1 OUT DE_IO 1000 CLK_A>; - txd1 = <&pio0 1 ALT1 OUT DE_IO 1000 CLK_A>; - txd2 = <&pio0 2 ALT1 OUT DE_IO 1000 CLK_A>; - txd3 = <&pio0 3 ALT1 OUT DE_IO 1000 CLK_A>; - txen = <&pio0 5 ALT1 OUT DE_IO 0 CLK_A>; - txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>; - mdio = <&pio1 0 ALT1 OUT BYPASS 0>; - mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>; - rxd0 = <&pio1 4 ALT1 IN DE_IO 0 CLK_A>; - rxd1 = <&pio1 5 ALT1 IN DE_IO 0 CLK_A>; - rxd2 = <&pio1 6 ALT1 IN DE_IO 0 CLK_A>; - rxd3 = <&pio1 7 ALT1 IN DE_IO 0 CLK_A>; - - rxdv = <&pio2 0 ALT1 IN DE_IO 500 CLK_A>; - rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>; - phyclk = <&pio2 3 ALT4 OUT NICLK 0 CLK_B>; - - clk125= <&pio3 7 ALT4 IN NICLK 0 CLK_A>; - }; - }; - }; - }; - - pin-controller-front { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stih415-front-pinctrl"; - st,syscfg = <&syscfg_front>; - reg = <0xfee0f080 0x4>; - reg-names = "irqmux"; - interrupts = ; - interrupt-names = "irqmux"; - ranges = <0 0xfee00000 0x8000>; - - pio5: gpio@fee00000 { - gpio-controller; - #gpio-cells = <1>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0 0x100>; - st,bank-name = "PIO5"; - }; - pio6: gpio@fee01000 { - gpio-controller; - #gpio-cells = <1>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1000 0x100>; - st,bank-name = "PIO6"; - }; - pio7: gpio@fee02000 { - gpio-controller; - #gpio-cells = <1>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x2000 0x100>; - st,bank-name = "PIO7"; - }; - pio8: gpio@fee03000 { - gpio-controller; - #gpio-cells = <1>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x3000 0x100>; - st,bank-name = "PIO8"; - }; - pio9: gpio@fee04000 { - gpio-controller; - #gpio-cells = <1>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x4000 0x100>; - st,bank-name = "PIO9"; - }; - pio10: gpio@fee05000 { - gpio-controller; - #gpio-cells = <1>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x5000 0x100>; - st,bank-name = "PIO10"; - }; - pio11: gpio@fee06000 { - gpio-controller; - #gpio-cells = <1>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x6000 0x100>; - st,bank-name = "PIO11"; - }; - pio12: gpio@fee07000 { - gpio-controller; - #gpio-cells = <1>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x7000 0x100>; - st,bank-name = "PIO12"; - }; - - i2c0 { - pinctrl_i2c0_default: i2c0-default { - st,pins { - sda = <&pio9 3 ALT1 BIDIR>; - scl = <&pio9 2 ALT1 BIDIR>; - }; - }; - }; - - i2c1 { - pinctrl_i2c1_default: i2c1-default { - st,pins { - sda = <&pio12 1 ALT1 BIDIR>; - scl = <&pio12 0 ALT1 BIDIR>; - }; - }; - }; - }; - - pin-controller-rear { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stih415-rear-pinctrl"; - st,syscfg = <&syscfg_rear>; - reg = <0xfe82f080 0x4>; - reg-names = "irqmux"; - interrupts = ; - interrupt-names = "irqmux"; - ranges = <0 0xfe820000 0x8000>; - - pio13: gpio@fe820000 { - gpio-controller; - #gpio-cells = <1>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0 0x100>; - st,bank-name = "PIO13"; - }; - pio14: gpio@fe821000 { - gpio-controller; - #gpio-cells = <1>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1000 0x100>; - st,bank-name = "PIO14"; - }; - pio15: gpio@fe822000 { - gpio-controller; - #gpio-cells = <1>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x2000 0x100>; - st,bank-name = "PIO15"; - }; - pio16: gpio@fe823000 { - gpio-controller; - #gpio-cells = <1>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x3000 0x100>; - st,bank-name = "PIO16"; - }; - pio17: gpio@fe824000 { - gpio-controller; - #gpio-cells = <1>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x4000 0x100>; - st,bank-name = "PIO17"; - }; - pio18: gpio@fe825000 { - gpio-controller; - #gpio-cells = <1>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x5000 0x100>; - st,bank-name = "PIO18"; - }; - - serial2 { - pinctrl_serial2: serial2-0 { - st,pins { - tx = <&pio17 4 ALT2 OUT>; - rx = <&pio17 5 ALT2 IN>; - }; - }; - }; - - gmac0{ - pinctrl_mii0: mii0 { - st,pins { - mdint = <&pio13 6 ALT2 IN BYPASS 0>; - txen = <&pio13 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - - txd0 = <&pio14 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - txd1 = <&pio14 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - txd2 = <&pio14 2 ALT2 OUT SE_NICLK_IO 0 CLK_B>; - txd3 = <&pio14 3 ALT2 OUT SE_NICLK_IO 0 CLK_B>; - - txclk = <&pio15 0 ALT2 IN NICLK 0 CLK_A>; - txer = <&pio15 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - crs = <&pio15 2 ALT2 IN BYPASS 1000>; - col = <&pio15 3 ALT2 IN BYPASS 1000>; - mdio = <&pio15 4 ALT2 OUT BYPASS 3000>; - mdc = <&pio15 5 ALT2 OUT NICLK 0 CLK_B>; - - rxd0 = <&pio16 0 ALT2 IN SE_NICLK_IO 0 CLK_A>; - rxd1 = <&pio16 1 ALT2 IN SE_NICLK_IO 0 CLK_A>; - rxd2 = <&pio16 2 ALT2 IN SE_NICLK_IO 0 CLK_A>; - rxd3 = <&pio16 3 ALT2 IN SE_NICLK_IO 0 CLK_A>; - rxdv = <&pio15 6 ALT2 IN SE_NICLK_IO 0 CLK_A>; - rx_er = <&pio15 7 ALT2 IN SE_NICLK_IO 0 CLK_A>; - rxclk = <&pio17 0 ALT2 IN NICLK 0 CLK_A>; - phyclk = <&pio13 5 ALT2 OUT NICLK 1000 CLK_A>; - - }; - }; - - pinctrl_gmii0: gmii0 { - st,pins { - mdint = <&pio13 6 ALT2 IN BYPASS 0>; - mdio = <&pio15 4 ALT2 OUT BYPASS 3000>; - mdc = <&pio15 5 ALT2 OUT NICLK 0 CLK_B>; - txen = <&pio13 7 ALT2 OUT SE_NICLK_IO 3000 CLK_A>; - - txd0 = <&pio14 0 ALT2 OUT SE_NICLK_IO 3000 CLK_A>; - txd1 = <&pio14 1 ALT2 OUT SE_NICLK_IO 3000 CLK_A>; - txd2 = <&pio14 2 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; - txd3 = <&pio14 3 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; - txd4 = <&pio14 4 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; - txd5 = <&pio14 5 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; - txd6 = <&pio14 6 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; - txd7 = <&pio14 7 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; - - txclk = <&pio15 0 ALT2 IN NICLK 0 CLK_A>; - txer = <&pio15 1 ALT2 OUT SE_NICLK_IO 3000 CLK_A>; - crs = <&pio15 2 ALT2 IN BYPASS 1000>; - col = <&pio15 3 ALT2 IN BYPASS 1000>; - rxdv = <&pio15 6 ALT2 IN SE_NICLK_IO 1500 CLK_A>; - rx_er = <&pio15 7 ALT2 IN SE_NICLK_IO 1500 CLK_A>; - - rxd0 = <&pio16 0 ALT2 IN SE_NICLK_IO 1500 CLK_A>; - rxd1 = <&pio16 1 ALT2 IN SE_NICLK_IO 1500 CLK_A>; - rxd2 = <&pio16 2 ALT2 IN SE_NICLK_IO 1500 CLK_A>; - rxd3 = <&pio16 3 ALT2 IN SE_NICLK_IO 1500 CLK_A>; - rxd4 = <&pio16 4 ALT2 IN SE_NICLK_IO 1500 CLK_A>; - rxd5 = <&pio16 5 ALT2 IN SE_NICLK_IO 1500 CLK_A>; - rxd6 = <&pio16 6 ALT2 IN SE_NICLK_IO 1500 CLK_A>; - rxd7 = <&pio16 7 ALT2 IN SE_NICLK_IO 1500 CLK_A>; - - rxclk = <&pio17 0 ALT2 IN NICLK 0 CLK_A>; - clk125 = <&pio17 6 ALT1 IN NICLK 0 CLK_A>; - phyclk = <&pio13 5 ALT4 OUT NICLK 0 CLK_B>; - - - }; - }; - }; - - mmc0 { - pinctrl_mmc0: mmc0 { - st,pins { - mmcclk = <&pio13 4 ALT4 BIDIR_PU NICLK 0 CLK_B>; - data0 = <&pio14 4 ALT4 BIDIR_PU BYPASS 0>; - data1 = <&pio14 5 ALT4 BIDIR_PU BYPASS 0>; - data2 = <&pio14 6 ALT4 BIDIR_PU BYPASS 0>; - data3 = <&pio14 7 ALT4 BIDIR_PU BYPASS 0>; - cmd = <&pio15 1 ALT4 BIDIR_PU BYPASS 0>; - wp = <&pio15 3 ALT4 IN>; - data4 = <&pio16 4 ALT4 BIDIR_PU BYPASS 0>; - data5 = <&pio16 5 ALT4 BIDIR_PU BYPASS 0>; - data6 = <&pio16 6 ALT4 BIDIR_PU BYPASS 0>; - data7 = <&pio16 7 ALT4 BIDIR_PU BYPASS 0>; - pwr = <&pio17 1 ALT4 OUT>; - cd = <&pio17 2 ALT4 IN>; - led = <&pio17 3 ALT4 OUT>; - }; - }; - }; - }; - - pin-controller-left { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stih415-left-pinctrl"; - st,syscfg = <&syscfg_left>; - reg = <0xfd6bf080 0x4>; - reg-names = "irqmux"; - interrupts = ; - interrupt-names = "irqmux"; - ranges = <0 0xfd6b0000 0x3000>; - - pio100: gpio@fd6b0000 { - gpio-controller; - #gpio-cells = <1>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0 0x100>; - st,bank-name = "PIO100"; - }; - pio101: gpio@fd6b1000 { - gpio-controller; - #gpio-cells = <1>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1000 0x100>; - st,bank-name = "PIO101"; - }; - pio102: gpio@fd6b2000 { - gpio-controller; - #gpio-cells = <1>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x2000 0x100>; - st,bank-name = "PIO102"; - }; - }; - - pin-controller-right { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stih415-right-pinctrl"; - st,syscfg = <&syscfg_right>; - reg = <0xfd33f080 0x4>; - reg-names = "irqmux"; - interrupts = ; - interrupt-names = "irqmux"; - ranges = <0 0xfd330000 0x5000>; - - pio103: gpio@fd330000 { - gpio-controller; - #gpio-cells = <1>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0 0x100>; - st,bank-name = "PIO103"; - }; - pio104: gpio@fd331000 { - gpio-controller; - #gpio-cells = <1>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1000 0x100>; - st,bank-name = "PIO104"; - }; - pio105: gpio@fd332000 { - gpio-controller; - #gpio-cells = <1>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x2000 0x100>; - st,bank-name = "PIO105"; - }; - pio106: gpio@fd333000 { - gpio-controller; - #gpio-cells = <1>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x3000 0x100>; - st,bank-name = "PIO106"; - }; - pio107: gpio@fd334000 { - gpio-controller; - #gpio-cells = <1>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x4000 0x100>; - st,bank-name = "PIO107"; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/stih415.dtsi b/sys/gnu/dts/arm/stih415.dtsi deleted file mode 100644 index 12427e651e5..00000000000 --- a/sys/gnu/dts/arm/stih415.dtsi +++ /dev/null @@ -1,234 +0,0 @@ -/* - * Copyright (C) 2013 STMicroelectronics (R&D) Limited. - * Author: Srinivas Kandagatla - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. - */ -#include "stih41x.dtsi" -#include "stih415-clock.dtsi" -#include "stih415-pinctrl.dtsi" -#include -#include -/ { - - L2: cache-controller { - compatible = "arm,pl310-cache"; - reg = <0xfffe2000 0x1000>; - arm,data-latency = <3 2 2>; - arm,tag-latency = <1 1 1>; - cache-unified; - cache-level = <2>; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&intc>; - ranges; - compatible = "simple-bus"; - - powerdown: powerdown-controller { - #reset-cells = <1>; - compatible = "st,stih415-powerdown"; - }; - - softreset: softreset-controller { - #reset-cells = <1>; - compatible = "st,stih415-softreset"; - }; - - syscfg_sbc: sbc-syscfg@fe600000{ - compatible = "st,stih415-sbc-syscfg", "syscon"; - reg = <0xfe600000 0xb4>; - }; - - syscfg_front: front-syscfg@fee10000{ - compatible = "st,stih415-front-syscfg", "syscon"; - reg = <0xfee10000 0x194>; - }; - - syscfg_rear: rear-syscfg@fe830000{ - compatible = "st,stih415-rear-syscfg", "syscon"; - reg = <0xfe830000 0x190>; - }; - - /* MPE syscfgs */ - syscfg_left: left-syscfg@fd690000{ - compatible = "st,stih415-left-syscfg", "syscon"; - reg = <0xfd690000 0x78>; - }; - - syscfg_right: right-syscfg@fd320000{ - compatible = "st,stih415-right-syscfg", "syscon"; - reg = <0xfd320000 0x180>; - }; - - syscfg_system: system-syscfg@fdde0000 { - compatible = "st,stih415-system-syscfg", "syscon"; - reg = <0xfdde0000 0x15c>; - }; - - syscfg_lpm: lpm-syscfg@fe4b5100{ - compatible = "st,stih415-lpm-syscfg", "syscon"; - reg = <0xfe4b5100 0x08>; - }; - - serial2: serial@fed32000 { - compatible = "st,asc"; - status = "disabled"; - reg = <0xfed32000 0x2c>; - interrupts = <0 197 0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_serial2>; - clocks = <&clk_s_a0_ls CLK_ICN_REG>; - }; - - /* SBC comms block ASCs in SASG1 */ - sbc_serial1: serial@fe531000 { - compatible = "st,asc"; - status = "disabled"; - reg = <0xfe531000 0x2c>; - interrupts = <0 210 0>; - clocks = <&clk_sysin>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sbc_serial1>; - }; - - i2c@fed40000 { - compatible = "st,comms-ssc4-i2c"; - reg = <0xfed40000 0x110>; - interrupts = ; - clocks = <&clk_s_a0_ls CLK_ICN_REG>; - clock-names = "ssc"; - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0_default>; - - status = "disabled"; - }; - - i2c@fed41000 { - compatible = "st,comms-ssc4-i2c"; - reg = <0xfed41000 0x110>; - interrupts = ; - clocks = <&clk_s_a0_ls CLK_ICN_REG>; - clock-names = "ssc"; - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1_default>; - - status = "disabled"; - }; - - i2c@fe540000 { - compatible = "st,comms-ssc4-i2c"; - reg = <0xfe540000 0x110>; - interrupts = ; - clocks = <&clk_sysin>; - clock-names = "ssc"; - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sbc_i2c0_default>; - - status = "disabled"; - }; - - i2c@fe541000 { - compatible = "st,comms-ssc4-i2c"; - reg = <0xfe541000 0x110>; - interrupts = ; - clocks = <&clk_sysin>; - clock-names = "ssc"; - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sbc_i2c1_default>; - - status = "disabled"; - }; - - ethernet0: dwmac@fe810000 { - device_type = "network"; - compatible = "st,stih415-dwmac", "snps,dwmac", "snps,dwmac-3.610"; - status = "disabled"; - - reg = <0xfe810000 0x8000>; - reg-names = "stmmaceth"; - - interrupts = <0 147 0>, <0 148 0>, <0 149 0>; - interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; - resets = <&softreset STIH415_ETH0_SOFTRESET>; - reset-names = "stmmaceth"; - - snps,pbl = <32>; - snps,mixed-burst; - snps,force_sf_dma_mode; - - st,syscon = <&syscfg_rear 0x148>; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mii0>; - clock-names = "stmmaceth", "sti-ethclk"; - clocks = <&clk_s_a1_ls CLK_ICN_IF_2>, <&clk_s_a1_ls CLK_GMAC0_PHY>; - }; - - ethernet1: dwmac@fef08000 { - device_type = "network"; - compatible = "st,stih415-dwmac", "snps,dwmac", "snps,dwmac-3.610"; - status = "disabled"; - reg = <0xfef08000 0x8000>; - reg-names = "stmmaceth"; - interrupts = <0 150 0>, <0 151 0>, <0 152 0>; - interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; - - snps,pbl = <32>; - snps,mixed-burst; - snps,force_sf_dma_mode; - - st,syscon = <&syscfg_sbc 0x74>; - - resets = <&softreset STIH415_ETH1_SOFTRESET>; - reset-names = "stmmaceth"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mii1>; - clock-names = "stmmaceth", "sti-ethclk"; - clocks = <&clk_s_a0_ls CLK_ICN_REG>, <&clk_s_a0_ls CLK_ETH1_PHY>; - }; - - rc: rc@fe518000 { - compatible = "st,comms-irb"; - reg = <0xfe518000 0x234>; - interrupts = <0 203 0>; - clocks = <&clk_sysin>; - rx-mode = "infrared"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ir>; - resets = <&softreset STIH415_IRB_SOFTRESET>; - }; - - keyscan: keyscan@fe4b0000 { - compatible = "st,sti-keyscan"; - status = "disabled"; - reg = <0xfe4b0000 0x2000>; - interrupts = ; - clocks = <&clk_sysin>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_keyscan>; - resets = <&powerdown STIH415_KEYSCAN_POWERDOWN>, - <&softreset STIH415_KEYSCAN_SOFTRESET>; - }; - - mmc0: sdhci@fe81e000 { - compatible = "st,sdhci"; - status = "disabled"; - reg = <0xfe81e000 0x1000>; - interrupts = ; - interrupt-names = "mmcirq"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mmc0>; - clock-names = "mmc"; - clocks = <&clk_s_a1_ls 1>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/stih416-b2000.dts b/sys/gnu/dts/arm/stih416-b2000.dts deleted file mode 100644 index 488e80a5d69..00000000000 --- a/sys/gnu/dts/arm/stih416-b2000.dts +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright (C) 2013 STMicroelectronics (R&D) Limited. - * Author: Srinivas Kandagatla - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. - */ -/dts-v1/; -#include "stih416.dtsi" -#include "stih41x-b2000.dtsi" -/ { - model = "STiH416 B2000"; - compatible = "st,stih416-b2000", "st,stih416"; -}; diff --git a/sys/gnu/dts/arm/stih416-b2020.dts b/sys/gnu/dts/arm/stih416-b2020.dts deleted file mode 100644 index 200a8184476..00000000000 --- a/sys/gnu/dts/arm/stih416-b2020.dts +++ /dev/null @@ -1,37 +0,0 @@ -/* - * Copyright (C) 2013 STMicroelectronics (R&D) Limited. - * Author: Srinivas Kandagatla - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. - */ -/dts-v1/; -#include "stih416.dtsi" -#include "stih41x-b2020.dtsi" -/ { - model = "STiH416 B2020"; - compatible = "st,stih416-b2020", "st,stih416"; - - soc { - mmc1: sdhci@fe81f000 { - status = "okay"; - bus-width = <8>; - non-removable; - }; - - miphy365x_phy: phy@fe382000 { - phy_port0: port@fe382000 { - st,sata-gen = <3>; - }; - - phy_port1: port@fe38a000 { - st,pcie-tx-pol-inv; - }; - }; - - sata0: sata@fe380000{ - status = "okay"; - }; - }; -}; diff --git a/sys/gnu/dts/arm/stih416-b2020e.dts b/sys/gnu/dts/arm/stih416-b2020e.dts deleted file mode 100644 index f1ceee192a0..00000000000 --- a/sys/gnu/dts/arm/stih416-b2020e.dts +++ /dev/null @@ -1,65 +0,0 @@ -/* - * Copyright (C) 2014 STMicroelectronics (R&D) Limited. - * Author: Lee Jones - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. - */ -/dts-v1/; -#include "stih416.dtsi" -#include "stih41x-b2020.dtsi" -/ { - model = "STiH416 B2020 REV-E"; - compatible = "st,stih416-b2020", "st,stih416"; - - soc { - leds { - compatible = "gpio-leds"; - red { - #gpio-cells = <1>; - label = "Front Panel LED"; - gpios = <&pio4 1>; - linux,default-trigger = "heartbeat"; - }; - green { - gpios = <&pio1 3>; - default-state = "off"; - }; - }; - - ethernet1: dwmac@fef08000 { - snps,reset-gpio = <&pio0 7>; - }; - - mmc1: sdhci@fe81f000 { - status = "okay"; - bus-width = <8>; - non-removable; - }; - - miphy365x_phy: phy@fe382000 { - phy_port0: port@fe382000 { - st,sata-gen = <3>; - }; - - phy_port1: port@fe38a000 { - st,pcie-tx-pol-inv; - }; - }; - - sata0: sata@fe380000{ - status = "okay"; - }; - - /* SAS PWM Module */ - pwm0: pwm@fed10000 { - status = "okay"; - }; - - /* SBC PWM Module */ - pwm1: pwm@fe510000 { - status = "okay"; - }; - }; -}; diff --git a/sys/gnu/dts/arm/stih416-clock.dtsi b/sys/gnu/dts/arm/stih416-clock.dtsi deleted file mode 100644 index 5b4fb838cdd..00000000000 --- a/sys/gnu/dts/arm/stih416-clock.dtsi +++ /dev/null @@ -1,756 +0,0 @@ -/* - * Copyright (C) 2013 STMicroelectronics R&D Limited - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include - -/ { - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - /* - * Fixed 30MHz oscillator inputs to SoC - */ - clk_sysin: clk-sysin { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <30000000>; - }; - - /* - * ClockGenAs on SASG2 - */ - clockgen-a@fee62000 { - reg = <0xfee62000 0xb48>; - - clk_s_a0_pll: clk-s-a0-pll { - #clock-cells = <1>; - compatible = "st,clkgena-plls-c65"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-a0-pll0-hs", - "clk-s-a0-pll0-ls", - "clk-s-a0-pll1"; - }; - - clk_s_a0_osc_prediv: clk-s-a0-osc-prediv { - #clock-cells = <0>; - compatible = "st,clkgena-prediv-c65", - "st,clkgena-prediv"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-a0-osc-prediv"; - }; - - clk_s_a0_hs: clk-s-a0-hs { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c65-hs", - "st,clkgena-divmux"; - - clocks = <&clk_s_a0_osc_prediv>, - <&clk_s_a0_pll 0>, /* PLL0 HS */ - <&clk_s_a0_pll 2>; /* PLL1 */ - - clock-output-names = "clk-s-fdma-0", - "clk-s-fdma-1", - ""; /* clk-s-jit-sense */ - /* Fourth output unused */ - }; - - clk_s_a0_ls: clk-s-a0-ls { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c65-ls", - "st,clkgena-divmux"; - - clocks = <&clk_s_a0_osc_prediv>, - <&clk_s_a0_pll 1>, /* PLL0 LS */ - <&clk_s_a0_pll 2>; /* PLL1 */ - - clock-output-names = "clk-s-icn-reg-0", - "clk-s-icn-if-0", - "clk-s-icn-reg-lp-0", - "clk-s-emiss", - "clk-s-eth1-phy", - "clk-s-mii-ref-out"; - /* Remaining outputs unused */ - }; - }; - - clockgen-a@fee81000 { - reg = <0xfee81000 0xb48>; - - clk_s_a1_pll: clk-s-a1-pll { - #clock-cells = <1>; - compatible = "st,clkgena-plls-c65"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-a1-pll0-hs", - "clk-s-a1-pll0-ls", - "clk-s-a1-pll1"; - }; - - clk_s_a1_osc_prediv: clk-s-a1-osc-prediv { - #clock-cells = <0>; - compatible = "st,clkgena-prediv-c65", - "st,clkgena-prediv"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-a1-osc-prediv"; - }; - - clk_s_a1_hs: clk-s-a1-hs { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c65-hs", - "st,clkgena-divmux"; - - clocks = <&clk_s_a1_osc_prediv>, - <&clk_s_a1_pll 0>, /* PLL0 HS */ - <&clk_s_a1_pll 2>; /* PLL1 */ - - clock-output-names = "", /* Reserved */ - "", /* Reserved */ - "clk-s-stac-phy", - "clk-s-vtac-tx-phy"; - }; - - clk_s_a1_ls: clk-s-a1-ls { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c65-ls", - "st,clkgena-divmux"; - - clocks = <&clk_s_a1_osc_prediv>, - <&clk_s_a1_pll 1>, /* PLL0 LS */ - <&clk_s_a1_pll 2>; /* PLL1 */ - - clock-output-names = "clk-s-icn-if-2", - "clk-s-card-mmc-0", - "clk-s-icn-if-1", - "clk-s-gmac0-phy", - "clk-s-nand-ctrl", - "", /* Reserved */ - "clk-s-mii0-ref-out", - "clk-s-stac-sys", - "clk-s-card-mmc-1"; - /* Remaining outputs unused */ - }; - }; - - /* - * ClockGenAs on MPE42 - */ - clockgen-a@fde12000 { - reg = <0xfde12000 0xb50>; - - clk_m_a0_pll0: clk-m-a0-pll0 { - #clock-cells = <1>; - compatible = "st,plls-c32-a1x-0", "st,clkgen-plls-c32"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-m-a0-pll0-phi0", - "clk-m-a0-pll0-phi1", - "clk-m-a0-pll0-phi2", - "clk-m-a0-pll0-phi3"; - }; - - clk_m_a0_pll1: clk-m-a0-pll1 { - #clock-cells = <1>; - compatible = "st,plls-c32-a1x-1", "st,clkgen-plls-c32"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-m-a0-pll1-phi0", - "clk-m-a0-pll1-phi1", - "clk-m-a0-pll1-phi2", - "clk-m-a0-pll1-phi3"; - }; - - clk_m_a0_osc_prediv: clk-m-a0-osc-prediv { - #clock-cells = <0>; - compatible = "st,clkgena-prediv-c32", - "st,clkgena-prediv"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-m-a0-osc-prediv"; - }; - - clk_m_a0_div0: clk-m-a0-div0 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf0", - "st,clkgena-divmux"; - - clocks = <&clk_m_a0_osc_prediv>, - <&clk_m_a0_pll0 0>, /* PLL0 PHI0 */ - <&clk_m_a0_pll1 0>; /* PLL1 PHI0 */ - - clock-output-names = "", /* Unused */ - "", /* Unused */ - "clk-m-fdma-12", - "", /* Unused */ - "clk-m-pp-dmu-0", - "clk-m-pp-dmu-1", - "clk-m-icm-lmi", - "clk-m-vid-dmu-0"; - }; - - clk_m_a0_div1: clk-m-a0-div1 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf1", - "st,clkgena-divmux"; - - clocks = <&clk_m_a0_osc_prediv>, - <&clk_m_a0_pll0 1>, /* PLL0 PHI1 */ - <&clk_m_a0_pll1 1>; /* PLL1 PHI1 */ - - clock-output-names = "clk-m-vid-dmu-1", - "", /* Unused */ - "clk-m-a9-ext2f", - "clk-m-st40rt", - "clk-m-st231-dmu-0", - "clk-m-st231-dmu-1", - "clk-m-st231-aud", - "clk-m-st231-gp-0"; - }; - - clk_m_a0_div2: clk-m-a0-div2 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf2", - "st,clkgena-divmux"; - - clocks = <&clk_m_a0_osc_prediv>, - <&clk_m_a0_pll0 2>, /* PLL0 PHI2 */ - <&clk_m_a0_pll1 2>; /* PLL1 PHI2 */ - - clock-output-names = "clk-m-st231-gp-1", - "clk-m-icn-cpu", - "clk-m-icn-stac", - "clk-m-tx-icn-dmu-0", - "clk-m-tx-icn-dmu-1", - "clk-m-tx-icn-ts", - "clk-m-icn-vdp-0", - "clk-m-icn-vdp-1"; - }; - - clk_m_a0_div3: clk-m-a0-div3 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf3", - "st,clkgena-divmux"; - - clocks = <&clk_m_a0_osc_prediv>, - <&clk_m_a0_pll0 3>, /* PLL0 PHI3 */ - <&clk_m_a0_pll1 3>; /* PLL1 PHI3 */ - - clock-output-names = "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - "clk-m-icn-vp8", - "", /* Unused */ - "clk-m-icn-reg-11", - "clk-m-a9-trace"; - }; - }; - - clockgen-a@fd6db000 { - reg = <0xfd6db000 0xb50>; - - clk_m_a1_pll0: clk-m-a1-pll0 { - #clock-cells = <1>; - compatible = "st,plls-c32-a1x-0", "st,clkgen-plls-c32"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-m-a1-pll0-phi0", - "clk-m-a1-pll0-phi1", - "clk-m-a1-pll0-phi2", - "clk-m-a1-pll0-phi3"; - }; - - clk_m_a1_pll1: clk-m-a1-pll1 { - #clock-cells = <1>; - compatible = "st,plls-c32-a1x-1", "st,clkgen-plls-c32"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-m-a1-pll1-phi0", - "clk-m-a1-pll1-phi1", - "clk-m-a1-pll1-phi2", - "clk-m-a1-pll1-phi3"; - }; - - clk_m_a1_osc_prediv: clk-m-a1-osc-prediv { - #clock-cells = <0>; - compatible = "st,clkgena-prediv-c32", - "st,clkgena-prediv"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-m-a1-osc-prediv"; - }; - - clk_m_a1_div0: clk-m-a1-div0 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf0", - "st,clkgena-divmux"; - - clocks = <&clk_m_a1_osc_prediv>, - <&clk_m_a1_pll0 0>, /* PLL0 PHI0 */ - <&clk_m_a1_pll1 0>; /* PLL1 PHI0 */ - - clock-output-names = "", /* Unused */ - "clk-m-fdma-10", - "clk-m-fdma-11", - "clk-m-hva-alt", - "clk-m-proc-sc", - "clk-m-tp", - "clk-m-rx-icn-dmu-0", - "clk-m-rx-icn-dmu-1"; - }; - - clk_m_a1_div1: clk-m-a1-div1 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf1", - "st,clkgena-divmux"; - - clocks = <&clk_m_a1_osc_prediv>, - <&clk_m_a1_pll0 1>, /* PLL0 PHI1 */ - <&clk_m_a1_pll1 1>; /* PLL1 PHI1 */ - - clock-output-names = "clk-m-rx-icn-ts", - "clk-m-rx-icn-vdp-0", - "", /* Unused */ - "clk-m-prv-t1-bus", - "clk-m-icn-reg-12", - "clk-m-icn-reg-10", - "", /* Unused */ - "clk-m-icn-st231"; - }; - - clk_m_a1_div2: clk-m-a1-div2 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf2", - "st,clkgena-divmux"; - - clocks = <&clk_m_a1_osc_prediv>, - <&clk_m_a1_pll0 2>, /* PLL0 PHI2 */ - <&clk_m_a1_pll1 2>; /* PLL1 PHI2 */ - - clock-output-names = "clk-m-fvdp-proc-alt", - "clk-m-icn-reg-13", - "clk-m-tx-icn-gpu", - "clk-m-rx-icn-gpu", - "", /* Unused */ - "", /* Unused */ - "", /* clk-m-apb-pm-12 */ - ""; /* Unused */ - }; - - clk_m_a1_div3: clk-m-a1-div3 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf3", - "st,clkgena-divmux"; - - clocks = <&clk_m_a1_osc_prediv>, - <&clk_m_a1_pll0 3>, /* PLL0 PHI3 */ - <&clk_m_a1_pll1 3>; /* PLL1 PHI3 */ - - clock-output-names = "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - ""; /* clk-m-gpu-alt */ - }; - }; - - clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&clk_m_a0_div1 2>; - clock-div = <2>; - clock-mult = <1>; - }; - - clockgen-a@fd345000 { - reg = <0xfd345000 0xb50>; - - clk_m_a2_pll0: clk-m-a2-pll0 { - #clock-cells = <1>; - compatible = "st,plls-c32-a1x-0", "st,clkgen-plls-c32"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-m-a2-pll0-phi0", - "clk-m-a2-pll0-phi1", - "clk-m-a2-pll0-phi2", - "clk-m-a2-pll0-phi3"; - }; - - clk_m_a2_pll1: clk-m-a2-pll1 { - #clock-cells = <1>; - compatible = "st,plls-c32-a1x-1", "st,clkgen-plls-c32"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-m-a2-pll1-phi0", - "clk-m-a2-pll1-phi1", - "clk-m-a2-pll1-phi2", - "clk-m-a2-pll1-phi3"; - }; - - clk_m_a2_osc_prediv: clk-m-a2-osc-prediv { - #clock-cells = <0>; - compatible = "st,clkgena-prediv-c32", - "st,clkgena-prediv"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-m-a2-osc-prediv"; - }; - - clk_m_a2_div0: clk-m-a2-div0 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf0", - "st,clkgena-divmux"; - - clocks = <&clk_m_a2_osc_prediv>, - <&clk_m_a2_pll0 0>, /* PLL0 PHI0 */ - <&clk_m_a2_pll1 0>; /* PLL1 PHI0 */ - - clock-output-names = "clk-m-vtac-main-phy", - "clk-m-vtac-aux-phy", - "clk-m-stac-phy", - "clk-m-stac-sys", - "", /* clk-m-mpestac-pg */ - "", /* clk-m-mpestac-wc */ - "", /* clk-m-mpevtacaux-pg*/ - ""; /* clk-m-mpevtacmain-pg*/ - }; - - clk_m_a2_div1: clk-m-a2-div1 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf1", - "st,clkgena-divmux"; - - clocks = <&clk_m_a2_osc_prediv>, - <&clk_m_a2_pll0 1>, /* PLL0 PHI1 */ - <&clk_m_a2_pll1 1>; /* PLL1 PHI1 */ - - clock-output-names = "", /* clk-m-mpevtacrx0-wc */ - "", /* clk-m-mpevtacrx1-wc */ - "clk-m-compo-main", - "clk-m-compo-aux", - "clk-m-bdisp-0", - "clk-m-bdisp-1", - "clk-m-icn-bdisp", - "clk-m-icn-compo"; - }; - - clk_m_a2_div2: clk-m-a2-div2 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf2", - "st,clkgena-divmux"; - - clocks = <&clk_m_a2_osc_prediv>, - <&clk_m_a2_pll0 2>, /* PLL0 PHI2 */ - <&clk_m_a2_pll1 2>; /* PLL1 PHI2 */ - - clock-output-names = "clk-m-icn-vdp-2", - "", /* Unused */ - "clk-m-icn-reg-14", - "clk-m-mdtp", - "clk-m-jpegdec", - "", /* Unused */ - "clk-m-dcephy-impctrl", - ""; /* Unused */ - }; - - clk_m_a2_div3: clk-m-a2-div3 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf3", - "st,clkgena-divmux"; - - clocks = <&clk_m_a2_osc_prediv>, - <&clk_m_a2_pll0 3>, /* PLL0 PHI3 */ - <&clk_m_a2_pll1 3>; /* PLL1 PHI3 */ - - clock-output-names = "", /* Unused */ - ""; /* clk-m-apb-pm-11 */ - /* Remaining outputs unused */ - }; - }; - - /* - * A9 PLL - */ - clockgen-a9@fdde08b0 { - reg = <0xfdde08b0 0x70>; - - clockgen_a9_pll: clockgen-a9-pll { - #clock-cells = <1>; - compatible = "st,stih416-plls-c32-a9", "st,clkgen-plls-c32"; - - clocks = <&clk_sysin>; - clock-output-names = "clockgen-a9-pll-odf"; - }; - }; - - /* - * ARM CPU related clocks - */ - clk_m_a9: clk-m-a9@fdde08ac { - #clock-cells = <0>; - compatible = "st,stih416-clkgen-a9-mux", "st,clkgen-mux"; - reg = <0xfdde08ac 0x4>; - clocks = <&clockgen_a9_pll 0>, - <&clockgen_a9_pll 0>, - <&clk_m_a0_div1 2>, - <&clk_m_a9_ext2f_div2>; - }; - - /* - * ARM Peripheral clock for timers - */ - arm_periph_clk: clk-m-a9-periphs { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&clk_m_a9>; - clock-div = <2>; - clock-mult = <1>; - }; - - /* - * Frequency synthesizers on the SASG2 - */ - clockgen_b0: clockgen-b0@fee108b4 { - #clock-cells = <1>; - compatible = "st,stih416-quadfs216", "st,quadfs"; - reg = <0xfee108b4 0x44>; - - clocks = <&clk_sysin>; - clock-output-names = "clk-s-usb48", - "clk-s-dss", - "clk-s-stfe-frc-2", - "clk-s-thsens-scard"; - }; - - clockgen_b1: clockgen-b1@fe8308c4 { - #clock-cells = <1>; - compatible = "st,stih416-quadfs216", "st,quadfs"; - reg = <0xfe8308c4 0x44>; - - clocks = <&clk_sysin>; - clock-output-names = "clk-s-pcm-0", - "clk-s-pcm-1", - "clk-s-pcm-2", - "clk-s-pcm-3"; - }; - - clockgen_c: clockgen-c@fe8307d0 { - #clock-cells = <1>; - compatible = "st,stih416-quadfs432", "st,quadfs"; - reg = <0xfe8307d0 0x44>; - - clocks = <&clk_sysin>; - clock-output-names = "clk-s-c-fs0-ch0", - "clk-s-c-vcc-sd", - "clk-s-c-fs0-ch2"; - }; - - clk_s_vcc_hd: clk-s-vcc-hd@fe8308b8 { - #clock-cells = <0>; - compatible = "st,stih416-clkgenc-vcc-hd", "st,clkgen-mux"; - reg = <0xfe8308b8 0x4>; /* SYSCFG2558 */ - - clocks = <&clk_sysin>, - <&clockgen_c 0>; - }; - - /* - * Add a dummy clock for the HDMI PHY for the VCC input mux - */ - clk_s_tmds_fromphy: clk-s-tmds-fromphy { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - clockgen_c_vcc: clockgen-c-vcc@fe8308ac { - #clock-cells = <1>; - compatible = "st,stih416-clkgenc", "st,clkgen-vcc"; - reg = <0xfe8308ac 0xc>; /* SYSCFG2555,2556,2557 */ - - clocks = <&clk_s_vcc_hd>, - <&clockgen_c 1>, - <&clk_s_tmds_fromphy>, - <&clockgen_c 2>; - - clock-output-names = "clk-s-pix-hdmi", - "clk-s-pix-dvo", - "clk-s-out-dvo", - "clk-s-pix-hd", - "clk-s-hddac", - "clk-s-denc", - "clk-s-sddac", - "clk-s-pix-main", - "clk-s-pix-aux", - "clk-s-stfe-frc-0", - "clk-s-ref-mcru", - "clk-s-slave-mcru", - "clk-s-tmds-hdmi", - "clk-s-hdmi-reject-pll", - "clk-s-thsens"; - }; - - clockgen_d: clockgen-d@fee107e0 { - #clock-cells = <1>; - compatible = "st,stih416-quadfs216", "st,quadfs"; - reg = <0xfee107e0 0x44>; - - clocks = <&clk_sysin>; - clock-output-names = "clk-s-ccsc", - "clk-s-stfe-frc-1", - "clk-s-tsout-1", - "clk-s-mchi"; - }; - - /* - * Frequency synthesizers on the MPE42 - */ - clockgen_e: clockgen-e@fd3208bc { - #clock-cells = <1>; - compatible = "st,stih416-quadfs660-E", "st,quadfs"; - reg = <0xfd3208bc 0xb0>; - - clocks = <&clk_sysin>; - clock-output-names = "clk-m-pix-mdtp-0", - "clk-m-pix-mdtp-1", - "clk-m-pix-mdtp-2", - "clk-m-mpelpc"; - }; - - clockgen_f: clockgen-f@fd320878 { - #clock-cells = <1>; - compatible = "st,stih416-quadfs660-F", "st,quadfs"; - reg = <0xfd320878 0xf0>; - - clocks = <&clk_sysin>; - clock-output-names = "clk-m-main-vidfs", - "clk-m-hva-fs", - "clk-m-fvdp-vcpu", - "clk-m-fvdp-proc-fs"; - }; - - clk_m_fvdp_proc: clk-m-fvdp-proc@fd320910 { - #clock-cells = <0>; - compatible = "st,stih416-clkgenf-vcc-fvdp", "st,clkgen-mux"; - reg = <0xfd320910 0x4>; /* SYSCFG8580 */ - - clocks = <&clk_m_a1_div2 0>, - <&clockgen_f 3>; - }; - - clk_m_hva: clk-m-hva@fd690868 { - #clock-cells = <0>; - compatible = "st,stih416-clkgenf-vcc-hva", "st,clkgen-mux"; - reg = <0xfd690868 0x4>; /* SYSCFG9538 */ - - clocks = <&clockgen_f 1>, - <&clk_m_a1_div0 3>; - }; - - clk_m_f_vcc_hd: clk-m-f-vcc-hd@fd32086c { - #clock-cells = <0>; - compatible = "st,stih416-clkgenf-vcc-hd", "st,clkgen-mux"; - reg = <0xfd32086c 0x4>; /* SYSCFG8539 */ - - clocks = <&clockgen_c_vcc 7>, - <&clockgen_f 0>; - }; - - clk_m_f_vcc_sd: clk-m-f-vcc-sd@fd32086c { - #clock-cells = <0>; - compatible = "st,stih416-clkgenf-vcc-sd", "st,clkgen-mux"; - reg = <0xfd32086c 0x4>; /* SYSCFG8539 */ - - clocks = <&clockgen_c_vcc 8>, - <&clockgen_f 1>; - }; - - /* - * Add a dummy clock for the HDMIRx external signal clock - */ - clk_m_pix_hdmirx_sas: clk-m-pix-hdmirx-sas { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - clockgen_f_vcc: clockgen-f-vcc@fd32086c { - #clock-cells = <1>; - compatible = "st,stih416-clkgenf", "st,clkgen-vcc"; - reg = <0xfd32086c 0xc>; /* SYSCFG8539,8540,8541 */ - - clocks = <&clk_m_f_vcc_hd>, - <&clk_m_f_vcc_sd>, - <&clockgen_f 0>, - <&clk_m_pix_hdmirx_sas>; - - clock-output-names = "clk-m-pix-main-pipe", - "clk-m-pix-aux-pipe", - "clk-m-pix-main-cru", - "clk-m-pix-aux-cru", - "clk-m-xfer-be-compo", - "clk-m-xfer-pip-compo", - "clk-m-xfer-aux-compo", - "clk-m-vsens", - "clk-m-pix-hdmirx-0", - "clk-m-pix-hdmirx-1"; - }; - - /* - * DDR PLL - */ - clockgen-ddr@0xfdde07d8 { - reg = <0xfdde07d8 0x110>; - - clockgen_ddr_pll: clockgen-ddr-pll { - #clock-cells = <1>; - compatible = "st,stih416-plls-c32-ddr", "st,clkgen-plls-c32"; - - clocks = <&clk_sysin>; - clock-output-names = "clockgen-ddr0", - "clockgen-ddr1"; - }; - }; - - /* - * GPU PLL - */ - clockgen-gpu@fd68ff00 { - reg = <0xfd68ff00 0x910>; - - clockgen_gpu_pll: clockgen-gpu-pll { - #clock-cells = <1>; - compatible = "st,stih416-gpu-pll-c32", "st,clkgengpu-pll-c32"; - - clocks = <&clk_sysin>; - clock-output-names = "clockgen-gpu-pll"; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/stih416-pinctrl.dtsi b/sys/gnu/dts/arm/stih416-pinctrl.dtsi deleted file mode 100644 index 051fc16f370..00000000000 --- a/sys/gnu/dts/arm/stih416-pinctrl.dtsi +++ /dev/null @@ -1,687 +0,0 @@ - -/* - * Copyright (C) 2013 STMicroelectronics Limited. - * Author: Srinivas Kandagatla - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. - */ -#include "st-pincfg.h" -#include -/ { - - aliases { - gpio0 = &pio0; - gpio1 = &pio1; - gpio2 = &pio2; - gpio3 = &pio3; - gpio4 = &pio4; - gpio5 = &pio40; - gpio6 = &pio5; - gpio7 = &pio6; - gpio8 = &pio7; - gpio9 = &pio8; - gpio10 = &pio9; - gpio11 = &pio10; - gpio12 = &pio11; - gpio13 = &pio12; - gpio14 = &pio30; - gpio15 = &pio31; - gpio16 = &pio13; - gpio17 = &pio14; - gpio18 = &pio15; - gpio19 = &pio16; - gpio20 = &pio17; - gpio21 = &pio18; - gpio22 = &pio100; - gpio23 = &pio101; - gpio24 = &pio102; - gpio25 = &pio103; - gpio26 = &pio104; - gpio27 = &pio105; - gpio28 = &pio106; - gpio29 = &pio107; - }; - - soc { - pin-controller-sbc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stih416-sbc-pinctrl"; - st,syscfg = <&syscfg_sbc>; - reg = <0xfe61f080 0x4>; - reg-names = "irqmux"; - interrupts = ; - interrupt-names = "irqmux"; - ranges = <0 0xfe610000 0x6000>; - - pio0: gpio@fe610000 { - gpio-controller; - #gpio-cells = <1>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0 0x100>; - st,bank-name = "PIO0"; - }; - pio1: gpio@fe611000 { - gpio-controller; - #gpio-cells = <1>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1000 0x100>; - st,bank-name = "PIO1"; - }; - pio2: gpio@fe612000 { - gpio-controller; - #gpio-cells = <1>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x2000 0x100>; - st,bank-name = "PIO2"; - }; - pio3: gpio@fe613000 { - gpio-controller; - #gpio-cells = <1>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x3000 0x100>; - st,bank-name = "PIO3"; - }; - pio4: gpio@fe614000 { - gpio-controller; - #gpio-cells = <1>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x4000 0x100>; - st,bank-name = "PIO4"; - }; - pio40: gpio@fe615000 { - gpio-controller; - #gpio-cells = <1>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x5000 0x100>; - st,bank-name = "PIO40"; - st,retime-pin-mask = <0x7f>; - }; - - rc{ - pinctrl_ir: ir0 { - st,pins { - ir = <&pio4 0 ALT2 IN>; - }; - }; - }; - sbc_serial1 { - pinctrl_sbc_serial1: sbc_serial1 { - st,pins { - tx = <&pio2 6 ALT3 OUT>; - rx = <&pio2 7 ALT3 IN>; - }; - }; - }; - - keyscan { - pinctrl_keyscan: keyscan { - st,pins { - keyin0 = <&pio0 2 ALT2 IN>; - keyin1 = <&pio0 3 ALT2 IN>; - keyin2 = <&pio0 4 ALT2 IN>; - keyin3 = <&pio2 6 ALT2 IN>; - - keyout0 = <&pio1 6 ALT2 OUT>; - keyout1 = <&pio1 7 ALT2 OUT>; - keyout2 = <&pio0 6 ALT2 OUT>; - keyout3 = <&pio2 7 ALT2 OUT>; - }; - }; - }; - - sbc_i2c0 { - pinctrl_sbc_i2c0_default: sbc_i2c0-default { - st,pins { - sda = <&pio4 6 ALT1 BIDIR>; - scl = <&pio4 5 ALT1 BIDIR>; - }; - }; - }; - - usb { - pinctrl_usb3: usb3 { - st,pins { - oc-detect = <&pio40 0 ALT1 IN>; - pwr-enable = <&pio40 1 ALT1 OUT>; - }; - }; - }; - - sbc_i2c1 { - pinctrl_sbc_i2c1_default: sbc_i2c1-default { - st,pins { - sda = <&pio3 2 ALT2 BIDIR>; - scl = <&pio3 1 ALT2 BIDIR>; - }; - }; - }; - - gmac1 { - pinctrl_mii1: mii1 { - st,pins { - txd0 = <&pio0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txd1 = <&pio0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txd2 = <&pio0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txd3 = <&pio0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txer = <&pio0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txen = <&pio0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>; - col = <&pio0 7 ALT1 IN BYPASS 1000>; - - mdio = <&pio1 0 ALT1 OUT BYPASS 1500>; - mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>; - crs = <&pio1 2 ALT1 IN BYPASS 1000>; - mdint = <&pio1 3 ALT1 IN BYPASS 0>; - rxd0 = <&pio1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; - rxd1 = <&pio1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>; - rxd2 = <&pio1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>; - rxd3 = <&pio1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>; - - rxdv = <&pio2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; - rx_er = <&pio2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; - rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>; - phyclk = <&pio2 3 ALT1 OUT NICLK 0 CLK_A>; - }; - }; - pinctrl_rgmii1: rgmii1-0 { - st,pins { - txd0 = <&pio0 0 ALT1 OUT DE_IO 500 CLK_A>; - txd1 = <&pio0 1 ALT1 OUT DE_IO 500 CLK_A>; - txd2 = <&pio0 2 ALT1 OUT DE_IO 500 CLK_A>; - txd3 = <&pio0 3 ALT1 OUT DE_IO 500 CLK_A>; - txen = <&pio0 5 ALT1 OUT DE_IO 0 CLK_A>; - txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>; - - mdio = <&pio1 0 ALT1 OUT BYPASS 0>; - mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>; - rxd0 = <&pio1 4 ALT1 IN DE_IO 500 CLK_A>; - rxd1 = <&pio1 5 ALT1 IN DE_IO 500 CLK_A>; - rxd2 = <&pio1 6 ALT1 IN DE_IO 500 CLK_A>; - rxd3 = <&pio1 7 ALT1 IN DE_IO 500 CLK_A>; - - rxdv = <&pio2 0 ALT1 IN DE_IO 500 CLK_A>; - rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>; - phyclk = <&pio2 3 ALT4 OUT NICLK 0 CLK_B>; - - clk125= <&pio3 7 ALT4 IN NICLK 0 CLK_A>; - }; - }; - }; - - pwm1 { - pinctrl_pwm1_chan0_default: pwm1-0-default { - st,pins { - pwm-out = <&pio3 0 ALT1 OUT>; - }; - }; - pinctrl_pwm1_chan1_default: pwm1-1-default { - st,pins { - pwm-out = <&pio4 4 ALT1 OUT>; - }; - }; - pinctrl_pwm1_chan2_default: pwm1-2-default { - st,pins { - pwm-out = <&pio4 6 ALT3 OUT>; - }; - }; - pinctrl_pwm1_chan3_default: pwm1-3-default { - st,pins { - pwm-out = <&pio4 7 ALT3 OUT>; - }; - }; - }; - }; - - pin-controller-front { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stih416-front-pinctrl"; - st,syscfg = <&syscfg_front>; - reg = <0xfee0f080 0x4>; - reg-names = "irqmux"; - interrupts = ; - interrupt-names = "irqmux"; - ranges = <0 0xfee00000 0x10000>; - - pio5: gpio@fee00000 { - gpio-controller; - #gpio-cells = <1>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0 0x100>; - st,bank-name = "PIO5"; - }; - pio6: gpio@fee01000 { - gpio-controller; - #gpio-cells = <1>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1000 0x100>; - st,bank-name = "PIO6"; - }; - pio7: gpio@fee02000 { - gpio-controller; - #gpio-cells = <1>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x2000 0x100>; - st,bank-name = "PIO7"; - }; - pio8: gpio@fee03000 { - gpio-controller; - #gpio-cells = <1>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x3000 0x100>; - st,bank-name = "PIO8"; - }; - pio9: gpio@fee04000 { - gpio-controller; - #gpio-cells = <1>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x4000 0x100>; - st,bank-name = "PIO9"; - }; - pio10: gpio@fee05000 { - gpio-controller; - #gpio-cells = <1>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x5000 0x100>; - st,bank-name = "PIO10"; - }; - pio11: gpio@fee06000 { - gpio-controller; - #gpio-cells = <1>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x6000 0x100>; - st,bank-name = "PIO11"; - }; - pio12: gpio@fee07000 { - gpio-controller; - #gpio-cells = <1>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x7000 0x100>; - st,bank-name = "PIO12"; - }; - pio30: gpio@fee08000 { - gpio-controller; - #gpio-cells = <1>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x8000 0x100>; - st,bank-name = "PIO30"; - }; - pio31: gpio@fee09000 { - gpio-controller; - #gpio-cells = <1>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x9000 0x100>; - st,bank-name = "PIO31"; - }; - - pwm0 { - pinctrl_pwm0_chan0_default: pwm0-0-default { - st,pins { - pwm-out = <&pio9 7 ALT2 OUT>; - }; - }; - }; - - serial2-oe { - pinctrl_serial2_oe: serial2-1 { - st,pins { - output-enable = <&pio11 3 ALT2 OUT>; - }; - }; - }; - - i2c0 { - pinctrl_i2c0_default: i2c0-default { - st,pins { - sda = <&pio9 3 ALT1 BIDIR>; - scl = <&pio9 2 ALT1 BIDIR>; - }; - }; - }; - - usb { - pinctrl_usb0: usb0 { - st,pins { - oc-detect = <&pio9 4 ALT1 IN>; - pwr-enable = <&pio9 5 ALT1 OUT>; - }; - }; - }; - - - i2c1 { - pinctrl_i2c1_default: i2c1-default { - st,pins { - sda = <&pio12 1 ALT1 BIDIR>; - scl = <&pio12 0 ALT1 BIDIR>; - }; - }; - }; - - fsm { - pinctrl_fsm: fsm { - st,pins { - spi-fsm-clk = <&pio12 2 ALT1 OUT>; - spi-fsm-cs = <&pio12 3 ALT1 OUT>; - spi-fsm-mosi = <&pio12 4 ALT1 OUT>; - spi-fsm-miso = <&pio12 5 ALT1 IN>; - spi-fsm-hol = <&pio12 6 ALT1 OUT>; - spi-fsm-wp = <&pio12 7 ALT1 OUT>; - }; - }; - }; - }; - - pin-controller-rear { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stih416-rear-pinctrl"; - st,syscfg = <&syscfg_rear>; - reg = <0xfe82f080 0x4>; - reg-names = "irqmux"; - interrupts = ; - interrupt-names = "irqmux"; - ranges = <0 0xfe820000 0x6000>; - - pio13: gpio@fe820000 { - gpio-controller; - #gpio-cells = <1>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0 0x100>; - st,bank-name = "PIO13"; - }; - pio14: gpio@fe821000 { - gpio-controller; - #gpio-cells = <1>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1000 0x100>; - st,bank-name = "PIO14"; - }; - pio15: gpio@fe822000 { - gpio-controller; - #gpio-cells = <1>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x2000 0x100>; - st,bank-name = "PIO15"; - }; - pio16: gpio@fe823000 { - gpio-controller; - #gpio-cells = <1>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x3000 0x100>; - st,bank-name = "PIO16"; - }; - pio17: gpio@fe824000 { - gpio-controller; - #gpio-cells = <1>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x4000 0x100>; - st,bank-name = "PIO17"; - }; - pio18: gpio@fe825000 { - gpio-controller; - #gpio-cells = <1>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x5000 0x100>; - st,bank-name = "PIO18"; - st,retime-pin-mask = <0xf>; - }; - - serial2 { - pinctrl_serial2: serial2-0 { - st,pins { - tx = <&pio17 4 ALT2 OUT>; - rx = <&pio17 5 ALT2 IN>; - }; - }; - }; - - gmac0 { - pinctrl_mii0: mii0 { - st,pins { - mdint = <&pio13 6 ALT2 IN BYPASS 0>; - txen = <&pio13 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - txd0 = <&pio14 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - txd1 = <&pio14 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - txd2 = <&pio14 2 ALT2 OUT SE_NICLK_IO 0 CLK_B>; - txd3 = <&pio14 3 ALT2 OUT SE_NICLK_IO 0 CLK_B>; - - txclk = <&pio15 0 ALT2 IN NICLK 0 CLK_A>; - txer = <&pio15 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - crs = <&pio15 2 ALT2 IN BYPASS 1000>; - col = <&pio15 3 ALT2 IN BYPASS 1000>; - mdio= <&pio15 4 ALT2 OUT BYPASS 1500>; - mdc = <&pio15 5 ALT2 OUT NICLK 0 CLK_B>; - - rxd0 = <&pio16 0 ALT2 IN SE_NICLK_IO 0 CLK_A>; - rxd1 = <&pio16 1 ALT2 IN SE_NICLK_IO 0 CLK_A>; - rxd2 = <&pio16 2 ALT2 IN SE_NICLK_IO 0 CLK_A>; - rxd3 = <&pio16 3 ALT2 IN SE_NICLK_IO 0 CLK_A>; - rxdv = <&pio15 6 ALT2 IN SE_NICLK_IO 0 CLK_A>; - rx_er = <&pio15 7 ALT2 IN SE_NICLK_IO 0 CLK_A>; - rxclk = <&pio17 0 ALT2 IN NICLK 0 CLK_A>; - phyclk = <&pio13 5 ALT2 OUT NICLK 0 CLK_B>; - }; - }; - - pinctrl_gmii0: gmii0 { - st,pins { - }; - }; - pinctrl_rgmii0: rgmii0 { - st,pins { - phyclk = <&pio13 5 ALT4 OUT NICLK 0 CLK_B>; - txen = <&pio13 7 ALT2 OUT DE_IO 0 CLK_A>; - txd0 = <&pio14 0 ALT2 OUT DE_IO 500 CLK_A>; - txd1 = <&pio14 1 ALT2 OUT DE_IO 500 CLK_A>; - txd2 = <&pio14 2 ALT2 OUT DE_IO 500 CLK_B>; - txd3 = <&pio14 3 ALT2 OUT DE_IO 500 CLK_B>; - txclk = <&pio15 0 ALT2 IN NICLK 0 CLK_A>; - - mdio = <&pio15 4 ALT2 OUT BYPASS 0>; - mdc = <&pio15 5 ALT2 OUT NICLK 0 CLK_B>; - - rxdv = <&pio15 6 ALT2 IN DE_IO 500 CLK_A>; - rxd0 =<&pio16 0 ALT2 IN DE_IO 500 CLK_A>; - rxd1 =<&pio16 1 ALT2 IN DE_IO 500 CLK_A>; - rxd2 =<&pio16 2 ALT2 IN DE_IO 500 CLK_A>; - rxd3 =<&pio16 3 ALT2 IN DE_IO 500 CLK_A>; - rxclk =<&pio17 0 ALT2 IN NICLK 0 CLK_A>; - - clk125=<&pio17 6 ALT1 IN NICLK 0 CLK_A>; - }; - }; - }; - - mmc0 { - pinctrl_mmc0: mmc0 { - st,pins { - mmcclk = <&pio13 4 ALT4 BIDIR_PU NICLK 0 CLK_B>; - data0 = <&pio14 4 ALT4 BIDIR_PU BYPASS 0>; - data1 = <&pio14 5 ALT4 BIDIR_PU BYPASS 0>; - data2 = <&pio14 6 ALT4 BIDIR_PU BYPASS 0>; - data3 = <&pio14 7 ALT4 BIDIR_PU BYPASS 0>; - cmd = <&pio15 1 ALT4 BIDIR_PU BYPASS 0>; - wp = <&pio15 3 ALT4 IN>; - data4 = <&pio16 4 ALT4 BIDIR_PU BYPASS 0>; - data5 = <&pio16 5 ALT4 BIDIR_PU BYPASS 0>; - data6 = <&pio16 6 ALT4 BIDIR_PU BYPASS 0>; - data7 = <&pio16 7 ALT4 BIDIR_PU BYPASS 0>; - pwr = <&pio17 1 ALT4 OUT>; - cd = <&pio17 2 ALT4 IN>; - led = <&pio17 3 ALT4 OUT>; - }; - }; - }; - mmc1 { - pinctrl_mmc1: mmc1 { - st,pins { - mmcclk = <&pio15 0 ALT3 BIDIR_PU NICLK 0 CLK_B>; - data0 = <&pio13 7 ALT3 BIDIR_PU BYPASS 0>; - data1 = <&pio14 1 ALT3 BIDIR_PU BYPASS 0>; - data2 = <&pio14 2 ALT3 BIDIR_PU BYPASS 0>; - data3 = <&pio14 3 ALT3 BIDIR_PU BYPASS 0>; - cmd = <&pio15 4 ALT3 BIDIR_PU BYPASS 0>; - data4 = <&pio15 6 ALT3 BIDIR_PU BYPASS 0>; - data5 = <&pio15 7 ALT3 BIDIR_PU BYPASS 0>; - data6 = <&pio16 0 ALT3 BIDIR_PU BYPASS 0>; - data7 = <&pio16 1 ALT3 BIDIR_PU BYPASS 0>; - pwr = <&pio16 2 ALT3 OUT>; - nreset = <&pio13 6 ALT3 OUT>; - }; - }; - }; - - usb { - pinctrl_usb1: usb1 { - st,pins { - oc-detect = <&pio18 0 ALT1 IN>; - pwr-enable = <&pio18 1 ALT1 OUT>; - }; - }; - pinctrl_usb2: usb2 { - st,pins { - oc-detect = <&pio18 2 ALT1 IN>; - pwr-enable = <&pio18 3 ALT1 OUT>; - }; - }; - }; - - pwm0 { - pinctrl_pwm0_chan1_default: pwm0-1-default { - st,pins { - pwm-out = <&pio13 2 ALT2 OUT>; - }; - }; - pinctrl_pwm0_chan2_default: pwm0-2-default { - st,pins { - pwm-out = <&pio15 2 ALT4 OUT>; - }; - }; - pinctrl_pwm0_chan3_default: pwm0-3-default { - st,pins { - pwm-out = <&pio17 4 ALT1 OUT>; - }; - }; - }; - - }; - - pin-controller-fvdp-fe { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stih416-fvdp-fe-pinctrl"; - st,syscfg = <&syscfg_fvdp_fe>; - reg = <0xfd6bf080 0x4>; - reg-names = "irqmux"; - interrupts = ; - interrupt-names = "irqmux"; - ranges = <0 0xfd6b0000 0x3000>; - - pio100: gpio@fd6b0000 { - gpio-controller; - #gpio-cells = <1>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0 0x100>; - st,bank-name = "PIO100"; - }; - pio101: gpio@fd6b1000 { - gpio-controller; - #gpio-cells = <1>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1000 0x100>; - st,bank-name = "PIO101"; - }; - pio102: gpio@fd6b2000 { - gpio-controller; - #gpio-cells = <1>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x2000 0x100>; - st,bank-name = "PIO102"; - }; - }; - - pin-controller-fvdp-lite { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stih416-fvdp-lite-pinctrl"; - st,syscfg = <&syscfg_fvdp_lite>; - reg = <0xfd33f080 0x4>; - reg-names = "irqmux"; - interrupts = ; - interrupt-names = "irqmux"; - ranges = <0 0xfd330000 0x5000>; - - pio103: gpio@fd330000 { - gpio-controller; - #gpio-cells = <1>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0 0x100>; - st,bank-name = "PIO103"; - }; - pio104: gpio@fd331000 { - gpio-controller; - #gpio-cells = <1>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1000 0x100>; - st,bank-name = "PIO104"; - }; - pio105: gpio@fd332000 { - gpio-controller; - #gpio-cells = <1>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x2000 0x100>; - st,bank-name = "PIO105"; - }; - pio106: gpio@fd333000 { - gpio-controller; - #gpio-cells = <1>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x3000 0x100>; - st,bank-name = "PIO106"; - }; - - pio107: gpio@fd334000 { - gpio-controller; - #gpio-cells = <1>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x4000 0x100>; - st,bank-name = "PIO107"; - st,retime-pin-mask = <0xf>; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/stih416.dtsi b/sys/gnu/dts/arm/stih416.dtsi deleted file mode 100644 index 9e3170ccd18..00000000000 --- a/sys/gnu/dts/arm/stih416.dtsi +++ /dev/null @@ -1,513 +0,0 @@ -/* - * Copyright (C) 2012 STMicroelectronics Limited. - * Author: Srinivas Kandagatla - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. - */ -#include "stih41x.dtsi" -#include "stih416-clock.dtsi" -#include "stih416-pinctrl.dtsi" - -#include -#include -#include -#include -/ { - L2: cache-controller { - compatible = "arm,pl310-cache"; - reg = <0xfffe2000 0x1000>; - arm,data-latency = <3 3 3>; - arm,tag-latency = <2 2 2>; - cache-unified; - cache-level = <2>; - }; - - arm-pmu { - compatible = "arm,cortex-a9-pmu"; - interrupt-parent = <&intc>; - interrupts = ; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&intc>; - ranges; - compatible = "simple-bus"; - - restart { - compatible = "st,stih416-restart"; - st,syscfg = <&syscfg_sbc>; - status = "okay"; - }; - - powerdown: powerdown-controller { - #reset-cells = <1>; - compatible = "st,stih416-powerdown"; - }; - - softreset: softreset-controller { - #reset-cells = <1>; - compatible = "st,stih416-softreset"; - }; - - syscfg_sbc:sbc-syscfg@fe600000{ - compatible = "st,stih416-sbc-syscfg", "syscon"; - reg = <0xfe600000 0x1000>; - }; - - syscfg_front:front-syscfg@fee10000{ - compatible = "st,stih416-front-syscfg", "syscon"; - reg = <0xfee10000 0x1000>; - }; - - syscfg_rear:rear-syscfg@fe830000{ - compatible = "st,stih416-rear-syscfg", "syscon"; - reg = <0xfe830000 0x1000>; - }; - - /* MPE */ - syscfg_fvdp_fe:fvdp-fe-syscfg@fddf0000{ - compatible = "st,stih416-fvdp-fe-syscfg", "syscon"; - reg = <0xfddf0000 0x1000>; - }; - - syscfg_fvdp_lite:fvdp-lite-syscfg@fd6a0000{ - compatible = "st,stih416-fvdp-lite-syscfg", "syscon"; - reg = <0xfd6a0000 0x1000>; - }; - - syscfg_cpu:cpu-syscfg@fdde0000{ - compatible = "st,stih416-cpu-syscfg", "syscon"; - reg = <0xfdde0000 0x1000>; - }; - - syscfg_compo:compo-syscfg@fd320000{ - compatible = "st,stih416-compo-syscfg", "syscon"; - reg = <0xfd320000 0x1000>; - }; - - syscfg_transport:transport-syscfg@fd690000{ - compatible = "st,stih416-transport-syscfg", "syscon"; - reg = <0xfd690000 0x1000>; - }; - - syscfg_lpm:lpm-syscfg@fe4b5100{ - compatible = "st,stih416-lpm-syscfg", "syscon"; - reg = <0xfe4b5100 0x8>; - }; - - irq-syscfg { - compatible = "st,stih416-irq-syscfg"; - st,syscfg = <&syscfg_cpu>; - st,irq-device = , - ; - st,fiq-device = , - ; - }; - - serial2: serial@fed32000{ - compatible = "st,asc"; - status = "disabled"; - reg = <0xfed32000 0x2c>; - interrupts = <0 197 0>; - clocks = <&clk_s_a0_ls CLK_ICN_REG>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_serial2 &pinctrl_serial2_oe>; - }; - - /* SBC_UART1 */ - sbc_serial1: serial@fe531000 { - compatible = "st,asc"; - status = "disabled"; - reg = <0xfe531000 0x2c>; - interrupts = <0 210 0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sbc_serial1>; - clocks = <&clk_sysin>; - }; - - i2c@fed40000 { - compatible = "st,comms-ssc4-i2c"; - reg = <0xfed40000 0x110>; - interrupts = ; - clocks = <&clk_s_a0_ls CLK_ICN_REG>; - clock-names = "ssc"; - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0_default>; - - status = "disabled"; - }; - - i2c@fed41000 { - compatible = "st,comms-ssc4-i2c"; - reg = <0xfed41000 0x110>; - interrupts = ; - clocks = <&clk_s_a0_ls CLK_ICN_REG>; - clock-names = "ssc"; - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1_default>; - - status = "disabled"; - }; - - i2c@fe540000 { - compatible = "st,comms-ssc4-i2c"; - reg = <0xfe540000 0x110>; - interrupts = ; - clocks = <&clk_sysin>; - clock-names = "ssc"; - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sbc_i2c0_default>; - - status = "disabled"; - }; - - i2c@fe541000 { - compatible = "st,comms-ssc4-i2c"; - reg = <0xfe541000 0x110>; - interrupts = ; - clocks = <&clk_sysin>; - clock-names = "ssc"; - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sbc_i2c1_default>; - - status = "disabled"; - }; - - ethernet0: dwmac@fe810000 { - device_type = "network"; - compatible = "st,stih416-dwmac", "snps,dwmac", "snps,dwmac-3.710"; - status = "disabled"; - reg = <0xfe810000 0x8000>; - reg-names = "stmmaceth"; - - interrupts = <0 133 0>, <0 134 0>, <0 135 0>; - interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; - - snps,pbl = <32>; - snps,mixed-burst; - - st,syscon = <&syscfg_rear 0x8bc>; - resets = <&softreset STIH416_ETH0_SOFTRESET>; - reset-names = "stmmaceth"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mii0>; - clock-names = "stmmaceth", "sti-ethclk"; - clocks = <&clk_s_a1_ls CLK_ICN_IF_2>, <&clk_s_a1_ls CLK_GMAC0_PHY>; - }; - - ethernet1: dwmac@fef08000 { - device_type = "network"; - compatible = "st,stih416-dwmac", "snps,dwmac", "snps,dwmac-3.710"; - status = "disabled"; - reg = <0xfef08000 0x8000>; - reg-names = "stmmaceth"; - interrupts = <0 136 0>, <0 137 0>, <0 138 0>; - interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; - - snps,pbl = <32>; - snps,mixed-burst; - - st,syscon = <&syscfg_sbc 0x7f0>; - - resets = <&softreset STIH416_ETH1_SOFTRESET>; - reset-names = "stmmaceth"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mii1>; - clock-names = "stmmaceth", "sti-ethclk"; - clocks = <&clk_s_a0_ls CLK_ICN_REG>, <&clk_s_a0_ls CLK_ETH1_PHY>; - }; - - rc: rc@fe518000 { - compatible = "st,comms-irb"; - reg = <0xfe518000 0x234>; - interrupts = <0 203 0>; - rx-mode = "infrared"; - clocks = <&clk_sysin>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ir>; - resets = <&softreset STIH416_IRB_SOFTRESET>; - }; - - /* FSM */ - spifsm: spifsm@fe902000 { - compatible = "st,spi-fsm"; - reg = <0xfe902000 0x1000>; - pinctrl-0 = <&pinctrl_fsm>; - - st,syscfg = <&syscfg_rear>; - st,boot-device-reg = <0x958>; - st,boot-device-spi = <0x1a>; - - status = "disabled"; - }; - - keyscan: keyscan@fe4b0000 { - compatible = "st,sti-keyscan"; - status = "disabled"; - reg = <0xfe4b0000 0x2000>; - interrupts = ; - clocks = <&clk_sysin>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_keyscan>; - resets = <&powerdown STIH416_KEYSCAN_POWERDOWN>, - <&softreset STIH416_KEYSCAN_SOFTRESET>; - }; - - temp0 { - compatible = "st,stih416-sas-thermal"; - clock-names = "thermal"; - clocks = <&clockgen_c_vcc 14>; - - status = "okay"; - }; - - temp1@fdfe8000 { - compatible = "st,stih416-mpe-thermal"; - reg = <0xfdfe8000 0x10>; - clocks = <&clockgen_e 3>; - clock-names = "thermal"; - interrupts = ; - - status = "okay"; - }; - - mmc0: sdhci@fe81e000 { - compatible = "st,sdhci"; - status = "disabled"; - reg = <0xfe81e000 0x1000>; - interrupts = ; - interrupt-names = "mmcirq"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mmc0>; - clock-names = "mmc"; - clocks = <&clk_s_a1_ls 1>; - }; - - mmc1: sdhci@fe81f000 { - compatible = "st,sdhci"; - status = "disabled"; - reg = <0xfe81f000 0x1000>; - interrupts = ; - interrupt-names = "mmcirq"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mmc1>; - clock-names = "mmc"; - clocks = <&clk_s_a1_ls 8>; - }; - - miphy365x_phy: phy@fe382000 { - compatible = "st,miphy365x-phy"; - st,syscfg = <&syscfg_rear 0x824 0x828>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - phy_port0: port@fe382000 { - #phy-cells = <1>; - reg = <0xfe382000 0x100>, <0xfe394000 0x100>; - reg-names = "sata", "pcie"; - }; - - phy_port1: port@fe38a000 { - #phy-cells = <1>; - reg = <0xfe38a000 0x100>, <0xfe804000 0x100>; - reg-names = "sata", "pcie"; - }; - }; - - sata0: sata@fe380000 { - compatible = "st,sti-ahci"; - reg = <0xfe380000 0x1000>; - interrupts = ; - interrupt-names = "hostc"; - phys = <&phy_port0 PHY_TYPE_SATA>; - phy-names = "sata-phy"; - resets = <&powerdown STIH416_SATA0_POWERDOWN>, - <&softreset STIH416_SATA0_SOFTRESET>; - reset-names = "pwr-dwn", "sw-rst"; - clock-names = "ahci_clk"; - clocks = <&clk_s_a0_ls CLK_ICN_REG>; - - status = "disabled"; - }; - - usb2_phy: phy@0 { - compatible = "st,stih416-usb-phy"; - #phy-cells = <0>; - st,syscfg = <&syscfg_rear>; - clocks = <&clk_sysin>; - clock-names = "osc_phy"; - }; - - ehci0: usb@fe1ffe00 { - compatible = "st,st-ehci-300x"; - reg = <0xfe1ffe00 0x100>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb0>; - clocks = <&clk_s_a1_ls 0>, - <&clockgen_b0 0>; - clock-names = "ic", "clk48"; - phys = <&usb2_phy>; - phy-names = "usb"; - resets = <&powerdown STIH416_USB0_POWERDOWN>, - <&softreset STIH416_USB0_SOFTRESET>; - reset-names = "power", "softreset"; - }; - - ohci0: usb@fe1ffc00 { - compatible = "st,st-ohci-300x"; - reg = <0xfe1ffc00 0x100>; - interrupts = ; - clocks = <&clk_s_a1_ls 0>, - <&clockgen_b0 0>; - clock-names = "ic", "clk48"; - phys = <&usb2_phy>; - phy-names = "usb"; - status = "okay"; - resets = <&powerdown STIH416_USB0_POWERDOWN>, - <&softreset STIH416_USB0_SOFTRESET>; - reset-names = "power", "softreset"; - }; - - ehci1: usb@fe203e00 { - compatible = "st,st-ehci-300x"; - reg = <0xfe203e00 0x100>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb1>; - clocks = <&clk_s_a1_ls 0>, - <&clockgen_b0 0>; - clock-names = "ic", "clk48"; - phys = <&usb2_phy>; - phy-names = "usb"; - resets = <&powerdown STIH416_USB1_POWERDOWN>, - <&softreset STIH416_USB1_SOFTRESET>; - reset-names = "power", "softreset"; - }; - - ohci1: usb@fe203c00 { - compatible = "st,st-ohci-300x"; - reg = <0xfe203c00 0x100>; - interrupts = ; - clocks = <&clk_s_a1_ls 0>, - <&clockgen_b0 0>; - clock-names = "ic", "clk48"; - phys = <&usb2_phy>; - phy-names = "usb"; - resets = <&powerdown STIH416_USB1_POWERDOWN>, - <&softreset STIH416_USB1_SOFTRESET>; - reset-names = "power", "softreset"; - }; - - ehci2: usb@fe303e00 { - compatible = "st,st-ehci-300x"; - reg = <0xfe303e00 0x100>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb2>; - clocks = <&clk_s_a1_ls 0>, - <&clockgen_b0 0>; - clock-names = "ic", "clk48"; - phys = <&usb2_phy>; - phy-names = "usb"; - resets = <&powerdown STIH416_USB2_POWERDOWN>, - <&softreset STIH416_USB2_SOFTRESET>; - reset-names = "power", "softreset"; - }; - - ohci2: usb@fe303c00 { - compatible = "st,st-ohci-300x"; - reg = <0xfe303c00 0x100>; - interrupts = ; - clocks = <&clk_s_a1_ls 0>, - <&clockgen_b0 0>; - clock-names = "ic", "clk48"; - phys = <&usb2_phy>; - phy-names = "usb"; - resets = <&powerdown STIH416_USB2_POWERDOWN>, - <&softreset STIH416_USB2_SOFTRESET>; - reset-names = "power", "softreset"; - }; - - ehci3: usb@fe343e00 { - compatible = "st,st-ehci-300x"; - reg = <0xfe343e00 0x100>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb3>; - clocks = <&clk_s_a1_ls 0>, - <&clockgen_b0 0>; - clock-names = "ic", "clk48"; - phys = <&usb2_phy>; - phy-names = "usb"; - resets = <&powerdown STIH416_USB3_POWERDOWN>, - <&softreset STIH416_USB3_SOFTRESET>; - reset-names = "power", "softreset"; - }; - - ohci3: usb@fe343c00 { - compatible = "st,st-ohci-300x"; - reg = <0xfe343c00 0x100>; - interrupts = ; - clocks = <&clk_s_a1_ls 0>, - <&clockgen_b0 0>; - clock-names = "ic", "clk48"; - phys = <&usb2_phy>; - phy-names = "usb"; - resets = <&powerdown STIH416_USB3_POWERDOWN>, - <&softreset STIH416_USB3_SOFTRESET>; - reset-names = "power", "softreset"; - }; - - /* SAS PWM Module */ - pwm0: pwm@fed10000 { - compatible = "st,sti-pwm"; - status = "disabled"; - #pwm-cells = <2>; - reg = <0xfed10000 0x68>; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm0_chan0_default - &pinctrl_pwm0_chan1_default - &pinctrl_pwm0_chan2_default - &pinctrl_pwm0_chan3_default>; - - clock-names = "pwm"; - clocks = <&clk_sysin>; - st,pwm-num-chan = <4>; - }; - - /* SBC PWM Module */ - pwm1: pwm@fe510000 { - compatible = "st,sti-pwm"; - status = "disabled"; - #pwm-cells = <2>; - reg = <0xfe510000 0x68>; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1_chan0_default - /* - * Shared with SBC_OBS_NOTRST. Don't - * enable unless you really know what - * you're doing. - * - * &pinctrl_pwm1_chan1_default - */ - &pinctrl_pwm1_chan2_default - &pinctrl_pwm1_chan3_default>; - - clock-names = "pwm"; - clocks = <&clk_sysin>; - st,pwm-num-chan = <3>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/stih418-b2199.dts b/sys/gnu/dts/arm/stih418-b2199.dts deleted file mode 100644 index 48c3c64e4c4..00000000000 --- a/sys/gnu/dts/arm/stih418-b2199.dts +++ /dev/null @@ -1,110 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2015 STMicroelectronics (R&D) Limited. - * Author: Maxime Coquelin - */ -/dts-v1/; -#include "stih418.dtsi" -#include -/ { - model = "STiH418 B2199"; - compatible = "st,stih418-b2199", "st,stih418"; - - chosen { - bootargs = "clk_ignore_unused"; - stdout-path = &sbc_serial0; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0xc0000000>; - }; - - aliases { - serial0 = &sbc_serial0; - ethernet0 = ðernet0; - }; - - leds { - compatible = "gpio-leds"; - red { - label = "Front Panel LED"; - gpios = <&pio4 1 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - green { - gpios = <&pio1 3 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - - soc { - sbc_serial0: serial@9530000 { - status = "okay"; - }; - - i2c@9842000 { - status = "okay"; - }; - - i2c@9843000 { - status = "okay"; - }; - - i2c@9844000 { - status = "okay"; - }; - - i2c@9845000 { - status = "okay"; - }; - - i2c@9540000 { - status = "okay"; - }; - - /* SSC11 to HDMI */ - i2c@9541000 { - status = "okay"; - /* HDMI V1.3a supports Standard mode only */ - clock-frequency = <100000>; - st,i2c-min-scl-pulse-width-us = <0>; - st,i2c-min-sda-pulse-width-us = <5>; - }; - - mmc1: sdhci@9080000 { - status = "okay"; - }; - - mmc0: sdhci@9060000 { - status = "okay"; - max-frequency = <200000000>; - sd-uhs-sdr50; - sd-uhs-sdr104; - sd-uhs-ddr50; - non-removable; - }; - - miphy28lp_phy: miphy28lp@0 { - - phy_port0: port@9b22000 { - st,osc-rdy; - }; - - phy_port1: port@9b2a000 { - st,osc-force-ext; - }; - }; - - st_dwc3: dwc3@8f94000 { - status = "okay"; - }; - - ethernet0: dwmac@9630000 { - st,tx-retime-src = "clkgen"; - status = "okay"; - phy-mode = "rgmii"; - fixed-link = <0 1 1000 0 0>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/stih418-clock.dtsi b/sys/gnu/dts/arm/stih418-clock.dtsi deleted file mode 100644 index 8fa09246210..00000000000 --- a/sys/gnu/dts/arm/stih418-clock.dtsi +++ /dev/null @@ -1,334 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2015 STMicroelectronics R&D Limited - */ -#include -/ { - /* - * Fixed 30MHz oscillator inputs to SoC - */ - clk_sysin: clk-sysin { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <30000000>; - clock-output-names = "CLK_SYSIN"; - }; - - clk_tmdsout_hdmi: clk-tmdsout-hdmi { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - compatible = "st,stih418-clk", "simple-bus"; - - /* - * A9 PLL. - */ - clockgen-a9@92b0000 { - compatible = "st,clkgen-c32"; - reg = <0x92b0000 0xffff>; - - clockgen_a9_pll: clockgen-a9-pll { - #clock-cells = <1>; - compatible = "st,stih418-clkgen-plla9"; - - clocks = <&clk_sysin>; - - clock-output-names = "clockgen-a9-pll-odf"; - }; - }; - - /* - * ARM CPU related clocks. - */ - clk_m_a9: clk-m-a9@92b0000 { - #clock-cells = <0>; - compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux"; - reg = <0x92b0000 0x10000>; - - clocks = <&clockgen_a9_pll 0>, - <&clockgen_a9_pll 0>, - <&clk_s_c0_flexgen 13>, - <&clk_m_a9_ext2f_div2>; - - /* - * ARM Peripheral clock for timers - */ - arm_periph_clk: clk-m-a9-periphs { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&clk_m_a9>; - clock-div = <2>; - clock-mult = <1>; - }; - }; - - clockgen-a@90ff000 { - compatible = "st,clkgen-c32"; - reg = <0x90ff000 0x1000>; - - clk_s_a0_pll: clk-s-a0-pll { - #clock-cells = <1>; - compatible = "st,clkgen-pll0"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-a0-pll-ofd-0"; - }; - - clk_s_a0_flexgen: clk-s-a0-flexgen { - compatible = "st,flexgen"; - - #clock-cells = <1>; - - clocks = <&clk_s_a0_pll 0>, - <&clk_sysin>; - - clock-output-names = "clk-ic-lmi0", - "clk-ic-lmi1"; - }; - }; - - clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 { - #clock-cells = <1>; - compatible = "st,quadfs-pll"; - reg = <0x9103000 0x1000>; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-c0-fs0-ch0", - "clk-s-c0-fs0-ch1", - "clk-s-c0-fs0-ch2", - "clk-s-c0-fs0-ch3"; - }; - - clk_s_c0: clockgen-c@9103000 { - compatible = "st,clkgen-c32"; - reg = <0x9103000 0x1000>; - - clk_s_c0_pll0: clk-s-c0-pll0 { - #clock-cells = <1>; - compatible = "st,clkgen-pll0"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-c0-pll0-odf-0"; - }; - - clk_s_c0_pll1: clk-s-c0-pll1 { - #clock-cells = <1>; - compatible = "st,clkgen-pll1"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-c0-pll1-odf-0"; - }; - - clk_s_c0_flexgen: clk-s-c0-flexgen { - #clock-cells = <1>; - compatible = "st,flexgen"; - - clocks = <&clk_s_c0_pll0 0>, - <&clk_s_c0_pll1 0>, - <&clk_s_c0_quadfs 0>, - <&clk_s_c0_quadfs 1>, - <&clk_s_c0_quadfs 2>, - <&clk_s_c0_quadfs 3>, - <&clk_sysin>; - - clock-output-names = "clk-icn-gpu", - "clk-fdma", - "clk-nand", - "clk-hva", - "clk-proc-stfe", - "clk-tp", - "clk-rx-icn-dmu", - "clk-rx-icn-hva", - "clk-icn-cpu", - "clk-tx-icn-dmu", - "clk-mmc-0", - "clk-mmc-1", - "clk-jpegdec", - "clk-icn-reg", - "clk-proc-bdisp-0", - "clk-proc-bdisp-1", - "clk-pp-dmu", - "clk-vid-dmu", - "clk-dss-lpc", - "clk-st231-aud-0", - "clk-st231-gp-1", - "clk-st231-dmu", - "clk-icn-lmi", - "clk-tx-icn-1", - "clk-icn-sbc", - "clk-stfe-frc2", - "clk-eth-phyref", - "clk-eth-ref-phyclk", - "clk-flash-promip", - "clk-main-disp", - "clk-aux-disp", - "clk-compo-dvp", - "clk-tx-icn-hades", - "clk-rx-icn-hades", - "clk-icn-reg-16", - "clk-pp-hevc", - "clk-clust-hevc", - "clk-hwpe-hevc", - "clk-fc-hevc", - "clk-proc-mixer", - "clk-proc-sc", - "clk-avsp-hevc"; - - /* - * ARM Peripheral clock for timers - */ - clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - - clocks = <&clk_s_c0_flexgen 13>; - - clock-output-names = "clk-m-a9-ext2f-div2"; - - clock-div = <2>; - clock-mult = <1>; - }; - }; - }; - - clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 { - #clock-cells = <1>; - compatible = "st,quadfs"; - reg = <0x9104000 0x1000>; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-d0-fs0-ch0", - "clk-s-d0-fs0-ch1", - "clk-s-d0-fs0-ch2", - "clk-s-d0-fs0-ch3"; - }; - - clockgen-d0@9104000 { - compatible = "st,clkgen-c32"; - reg = <0x9104000 0x1000>; - - clk_s_d0_flexgen: clk-s-d0-flexgen { - #clock-cells = <1>; - compatible = "st,flexgen-audio", "st,flexgen"; - - clocks = <&clk_s_d0_quadfs 0>, - <&clk_s_d0_quadfs 1>, - <&clk_s_d0_quadfs 2>, - <&clk_s_d0_quadfs 3>, - <&clk_sysin>; - - clock-output-names = "clk-pcm-0", - "clk-pcm-1", - "clk-pcm-2", - "clk-spdiff", - "clk-pcmr10-master", - "clk-usb2-phy"; - }; - }; - - clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 { - #clock-cells = <1>; - compatible = "st,quadfs"; - reg = <0x9106000 0x1000>; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-d2-fs0-ch0", - "clk-s-d2-fs0-ch1", - "clk-s-d2-fs0-ch2", - "clk-s-d2-fs0-ch3"; - }; - - clockgen-d2@9106000 { - compatible = "st,clkgen-c32"; - reg = <0x9106000 0x1000>; - - clk_s_d2_flexgen: clk-s-d2-flexgen { - #clock-cells = <1>; - compatible = "st,flexgen-video", "st,flexgen"; - - clocks = <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 1>, - <&clk_s_d2_quadfs 2>, - <&clk_s_d2_quadfs 3>, - <&clk_sysin>, - <&clk_sysin>, - <&clk_tmdsout_hdmi>; - - clock-output-names = "clk-pix-main-disp", - "", - "", - "", - "", - "clk-tmds-hdmi-div2", - "clk-pix-aux-disp", - "clk-denc", - "clk-pix-hddac", - "clk-hddac", - "clk-sddac", - "clk-pix-dvo", - "clk-dvo", - "clk-pix-hdmi", - "clk-tmds-hdmi", - "clk-ref-hdmiphy", - "", "", "", "", "", - "", "", "", "", "", - "", "", "", "", "", - "", "", "", "", "", - "", "", "", "", "", - "", "", "", "", "", - "", "clk-vp9"; - }; - }; - - clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 { - #clock-cells = <1>; - compatible = "st,quadfs"; - reg = <0x9107000 0x1000>; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-d3-fs0-ch0", - "clk-s-d3-fs0-ch1", - "clk-s-d3-fs0-ch2", - "clk-s-d3-fs0-ch3"; - }; - - clockgen-d3@9107000 { - compatible = "st,clkgen-c32"; - reg = <0x9107000 0x1000>; - - clk_s_d3_flexgen: clk-s-d3-flexgen { - #clock-cells = <1>; - compatible = "st,flexgen"; - - clocks = <&clk_s_d3_quadfs 0>, - <&clk_s_d3_quadfs 1>, - <&clk_s_d3_quadfs 2>, - <&clk_s_d3_quadfs 3>, - <&clk_sysin>; - - clock-output-names = "clk-stfe-frc1", - "clk-tsout-0", - "clk-tsout-1", - "clk-mchi", - "clk-vsens-compo", - "clk-frc1-remote", - "clk-lpc-0", - "clk-lpc-1"; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/stih418.dtsi b/sys/gnu/dts/arm/stih418.dtsi deleted file mode 100644 index 83411322bd9..00000000000 --- a/sys/gnu/dts/arm/stih418.dtsi +++ /dev/null @@ -1,108 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 STMicroelectronics Limited. - * Author: Peter Griffin - */ -#include "stih418-clock.dtsi" -#include "stih407-family.dtsi" -#include "stih410-pinctrl.dtsi" -/ { - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <2>; - /* u-boot puts hpen in SBC dmem at 0xa4 offset */ - cpu-release-addr = <0x94100A4>; - }; - cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <3>; - /* u-boot puts hpen in SBC dmem at 0xa4 offset */ - cpu-release-addr = <0x94100A4>; - }; - }; - - soc { - usb2_picophy1: phy2@0 { - compatible = "st,stih407-usb2-phy"; - reg = <0 0>; - #phy-cells = <0>; - st,syscfg = <&syscfg_core 0xf8 0xf4>; - resets = <&softreset STIH407_PICOPHY_SOFTRESET>, - <&picophyreset STIH407_PICOPHY0_RESET>; - reset-names = "global", "port"; - }; - - usb2_picophy2: phy3@0 { - compatible = "st,stih407-usb2-phy"; - reg = <0 0>; - #phy-cells = <0>; - st,syscfg = <&syscfg_core 0xfc 0xf4>; - resets = <&softreset STIH407_PICOPHY_SOFTRESET>, - <&picophyreset STIH407_PICOPHY1_RESET>; - reset-names = "global", "port"; - }; - - ohci0: usb@9a03c00 { - compatible = "st,st-ohci-300x"; - reg = <0x9a03c00 0x100>; - interrupts = ; - clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>; - resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>, - <&softreset STIH407_USB2_PORT0_SOFTRESET>; - reset-names = "power", "softreset"; - phys = <&usb2_picophy1>; - phy-names = "usb"; - }; - - ehci0: usb@9a03e00 { - compatible = "st,st-ehci-300x"; - reg = <0x9a03e00 0x100>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb0>; - clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>; - resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>, - <&softreset STIH407_USB2_PORT0_SOFTRESET>; - reset-names = "power", "softreset"; - phys = <&usb2_picophy1>; - phy-names = "usb"; - }; - - ohci1: usb@9a83c00 { - compatible = "st,st-ohci-300x"; - reg = <0x9a83c00 0x100>; - interrupts = ; - clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>; - resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>, - <&softreset STIH407_USB2_PORT1_SOFTRESET>; - reset-names = "power", "softreset"; - phys = <&usb2_picophy2>; - phy-names = "usb"; - }; - - ehci1: usb@9a83e00 { - compatible = "st,st-ehci-300x"; - reg = <0x9a83e00 0x100>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb1>; - clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>; - resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>, - <&softreset STIH407_USB2_PORT1_SOFTRESET>; - reset-names = "power", "softreset"; - phys = <&usb2_picophy2>; - phy-names = "usb"; - }; - - mmc0: sdhci@9060000 { - assigned-clocks = <&clk_s_c0_flexgen CLK_MMC_0>; - assigned-clock-parents = <&clk_s_c0_pll1 0>; - assigned-clock-rates = <200000000>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/stih41x-b2000.dtsi b/sys/gnu/dts/arm/stih41x-b2000.dtsi deleted file mode 100644 index 5f91f455f05..00000000000 --- a/sys/gnu/dts/arm/stih41x-b2000.dtsi +++ /dev/null @@ -1,95 +0,0 @@ -/* - * Copyright (C) 2013 STMicroelectronics (R&D) Limited. - * Author: Srinivas Kandagatla - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. - */ -#include -/ { - - memory{ - device_type = "memory"; - reg = <0x60000000 0x40000000>; - }; - - chosen { - bootargs = "console=ttyAS0,115200 clk_ignore_unused"; - linux,stdout-path = &serial2; - }; - - aliases { - ttyAS0 = &serial2; - ethernet0 = ðernet0; - ethernet1 = ðernet1; - }; - - soc { - serial2: serial@fed32000 { - status = "okay"; - }; - - leds { - compatible = "gpio-leds"; - fp_led { - #gpio-cells = <1>; - label = "Front Panel LED"; - gpios = <&pio105 7>; - linux,default-trigger = "heartbeat"; - }; - }; - - /* HDMI Tx I2C */ - i2c@fed41000 { - /* HDMI V1.3a supports Standard mode only */ - clock-frequency = <100000>; - i2c-min-scl-pulse-width-us = <0>; - i2c-min-sda-pulse-width-us = <5>; - - status = "okay"; - }; - - ethernet0: dwmac@fe810000 { - status = "okay"; - phy-mode = "mii"; - pinctrl-0 = <&pinctrl_mii0>; - - snps,reset-gpio = <&pio106 2>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 10000>; - }; - - ethernet1: dwmac@fef08000 { - status = "disabled"; - phy-mode = "mii"; - st,tx-retime-src = "txclk"; - - snps,reset-gpio = <&pio4 7>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 10000>; - }; - - keyscan: keyscan@fe4b0000 { - keypad,num-rows = <4>; - keypad,num-columns = <4>; - st,debounce-us = <5000>; - linux,keymap = < MATRIX_KEY(0x00, 0x00, KEY_F13) - MATRIX_KEY(0x00, 0x01, KEY_F9) - MATRIX_KEY(0x00, 0x02, KEY_F5) - MATRIX_KEY(0x00, 0x03, KEY_F1) - MATRIX_KEY(0x01, 0x00, KEY_F14) - MATRIX_KEY(0x01, 0x01, KEY_F10) - MATRIX_KEY(0x01, 0x02, KEY_F6) - MATRIX_KEY(0x01, 0x03, KEY_F2) - MATRIX_KEY(0x02, 0x00, KEY_F15) - MATRIX_KEY(0x02, 0x01, KEY_F11) - MATRIX_KEY(0x02, 0x02, KEY_F7) - MATRIX_KEY(0x02, 0x03, KEY_F3) - MATRIX_KEY(0x03, 0x00, KEY_F16) - MATRIX_KEY(0x03, 0x01, KEY_F12) - MATRIX_KEY(0x03, 0x02, KEY_F8) - MATRIX_KEY(0x03, 0x03, KEY_F4) >; - }; - }; -}; diff --git a/sys/gnu/dts/arm/stih41x-b2020.dtsi b/sys/gnu/dts/arm/stih41x-b2020.dtsi deleted file mode 100644 index 487d7d87dbe..00000000000 --- a/sys/gnu/dts/arm/stih41x-b2020.dtsi +++ /dev/null @@ -1,82 +0,0 @@ -/* - * Copyright (C) 2013 STMicroelectronics (R&D) Limited. - * Author: Srinivas Kandagatla - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. - */ -#include "stih41x-b2020x.dtsi" -/ { - memory{ - device_type = "memory"; - reg = <0x40000000 0x80000000>; - }; - - chosen { - bootargs = "console=ttyAS0,115200 clk_ignore_unused"; - linux,stdout-path = &sbc_serial1; - }; - - aliases { - ttyAS0 = &sbc_serial1; - ethernet1 = ðernet1; - }; - soc { - sbc_serial1: serial@fe531000 { - status = "okay"; - }; - - leds { - compatible = "gpio-leds"; - red { - #gpio-cells = <1>; - label = "Front Panel LED"; - gpios = <&pio4 1>; - linux,default-trigger = "heartbeat"; - }; - green { - gpios = <&pio4 7>; - default-state = "off"; - }; - }; - - i2c@fed40000 { - status = "okay"; - }; - - /* HDMI Tx I2C */ - i2c@fed41000 { - /* HDMI V1.3a supports Standard mode only */ - clock-frequency = <100000>; - i2c-min-scl-pulse-width-us = <0>; - i2c-min-sda-pulse-width-us = <5>; - - status = "okay"; - }; - - i2c@fe540000 { - status = "okay"; - }; - - i2c@fe541000 { - status = "okay"; - }; - - ethernet1: dwmac@fef08000 { - status = "okay"; - phy-mode = "rgmii-id"; - max-speed = <1000>; - st,tx-retime-src = "clk_125"; - snps,reset-gpio = <&pio3 0>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 10000>; - - pinctrl-0 = <&pinctrl_rgmii1>; - }; - - mmc0: sdhci@fe81e000 { - bus-width = <8>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/stih41x-b2020x.dtsi b/sys/gnu/dts/arm/stih41x-b2020x.dtsi deleted file mode 100644 index f797a060738..00000000000 --- a/sys/gnu/dts/arm/stih41x-b2020x.dtsi +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Copyright (C) 2013 STMicroelectronics (R&D) Limited. - * Author: Lee Jones - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. - */ -/ { - soc { - mmc0: sdhci@fe81e000 { - status = "okay"; - }; - - spifsm: spifsm@fe902000 { - #address-cells = <1>; - #size-cells = <1>; - - status = "okay"; - - partition@0 { - label = "SerialFlash1"; - reg = <0x00000000 0x00500000>; - }; - - partition@500000 { - label = "SerialFlash2"; - reg = <0x00500000 0x00b00000>; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/stih41x.dtsi b/sys/gnu/dts/arm/stih41x.dtsi deleted file mode 100644 index 5cb0e63376b..00000000000 --- a/sys/gnu/dts/arm/stih41x.dtsi +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Copyright (C) 2014 STMicroelectronics Limited. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. - */ -/ { - #address-cells = <1>; - #size-cells = <1>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - }; - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <1>; - }; - }; - - intc: interrupt-controller@fffe1000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0xfffe1000 0x1000>, - <0xfffe0100 0x100>; - }; - - scu@fffe0000 { - compatible = "arm,cortex-a9-scu"; - reg = <0xfffe0000 0x1000>; - }; - - timer@fffe0200 { - interrupt-parent = <&intc>; - compatible = "arm,cortex-a9-global-timer"; - reg = <0xfffe0200 0x100>; - interrupts = <1 11 0x04>; - clocks = <&arm_periph_clk>; - }; -}; diff --git a/sys/gnu/dts/arm/stihxxx-b2120.dtsi b/sys/gnu/dts/arm/stihxxx-b2120.dtsi deleted file mode 100644 index d051f080e52..00000000000 --- a/sys/gnu/dts/arm/stihxxx-b2120.dtsi +++ /dev/null @@ -1,206 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 STMicroelectronics (R&D) Limited. - * Author: Giuseppe Cavallaro - */ -#include -#include -#include -/ { - leds { - compatible = "gpio-leds"; - red { - label = "Front Panel LED"; - gpios = <&pio4 1 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - green { - gpios = <&pio1 3 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - - sound: sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "STI-B2120"; - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - - simple-audio-card,dai-link@0 { - reg = <0>; - /* HDMI */ - format = "i2s"; - mclk-fs = <128>; - cpu { - sound-dai = <&sti_uni_player0>; - }; - - codec { - sound-dai = <&sti_hdmi>; - }; - }; - - simple-audio-card,dai-link@1 { - reg = <1>; - /* DAC */ - format = "i2s"; - mclk-fs = <256>; - frame-inversion; - cpu { - sound-dai = <&sti_uni_player2>; - }; - - codec { - sound-dai = <&sti_sasg_codec 1>; - }; - }; - - simple-audio-card,dai-link@2 { - reg = <2>; - /* SPDIF */ - format = "left_j"; - mclk-fs = <128>; - cpu { - sound-dai = <&sti_uni_player3>; - }; - - codec { - sound-dai = <&sti_sasg_codec 0>; - }; - }; - }; - - soc { - sbc_serial0: serial@9530000 { - status = "okay"; - }; - - pwm0: pwm@9810000 { - status = "okay"; - }; - - pwm1: pwm@9510000 { - status = "okay"; - }; - - ssc2: i2c@9842000 { - status = "okay"; - clock-frequency = <100000>; - st,i2c-min-scl-pulse-width-us = <0>; - st,i2c-min-sda-pulse-width-us = <5>; - }; - - ssc3: i2c@9843000 { - status = "okay"; - clock-frequency = <100000>; - st,i2c-min-scl-pulse-width-us = <0>; - st,i2c-min-sda-pulse-width-us = <5>; - }; - - i2c@9844000 { - status = "okay"; - }; - - i2c@9845000 { - status = "okay"; - }; - - i2c@9540000 { - status = "okay"; - }; - - mmc0: sdhci@9060000 { - non-removable; - status = "okay"; - }; - - mmc1: sdhci@9080000 { - status = "okay"; - }; - - /* SSC11 to HDMI */ - hdmiddc: i2c@9541000 { - status = "okay"; - /* HDMI V1.3a supports Standard mode only */ - clock-frequency = <100000>; - st,i2c-min-scl-pulse-width-us = <0>; - st,i2c-min-sda-pulse-width-us = <5>; - }; - - miphy28lp_phy: miphy28lp@0 { - - phy_port0: port@9b22000 { - st,osc-rdy; - }; - - phy_port1: port@9b2a000 { - st,osc-force-ext; - }; - }; - - st_dwc3: dwc3@8f94000 { - status = "okay"; - }; - - ethernet0: dwmac@9630000 { - st,tx-retime-src = "clkgen"; - status = "okay"; - phy-mode = "rgmii"; - fixed-link = <0 1 1000 0 0>; - }; - - demux@8a20000 { - compatible = "st,stih407-c8sectpfe"; - status = "okay"; - reg = <0x08a20000 0x10000>, - <0x08a00000 0x4000>; - reg-names = "c8sectpfe", "c8sectpfe-ram"; - interrupts = , - ; - interrupt-names = "c8sectpfe-error-irq", - "c8sectpfe-idle-irq"; - pinctrl-0 = <&pinctrl_tsin0_serial>; - pinctrl-1 = <&pinctrl_tsin0_parallel>; - pinctrl-2 = <&pinctrl_tsin3_serial>; - pinctrl-3 = <&pinctrl_tsin4_serial_alt3>; - pinctrl-4 = <&pinctrl_tsin5_serial_alt1>; - pinctrl-names = "tsin0-serial", - "tsin0-parallel", - "tsin3-serial", - "tsin4-serial", - "tsin5-serial"; - clocks = <&clk_s_c0_flexgen CLK_PROC_STFE>; - clock-names = "c8sectpfe"; - - /* tsin0 is TSA on NIMA */ - tsin0: port { - tsin-num = <0>; - serial-not-parallel; - i2c-bus = <&ssc2>; - reset-gpios = <&pio15 4 GPIO_ACTIVE_HIGH>; - dvb-card = ; - }; - }; - - sti_uni_player0: sti-uni-player@8d80000 { - status = "okay"; - }; - - sti_uni_player2: sti-uni-player@8d82000 { - status = "okay"; - }; - - sti_uni_player3: sti-uni-player@8d85000 { - status = "okay"; - }; - - syscfg_core: core-syscfg@92b0000 { - sti_sasg_codec: sti-sasg-codec { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spdif_out>; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/stm32429i-eval.dts b/sys/gnu/dts/arm/stm32429i-eval.dts deleted file mode 100644 index c27fa355e5a..00000000000 --- a/sys/gnu/dts/arm/stm32429i-eval.dts +++ /dev/null @@ -1,325 +0,0 @@ -/* - * Copyright 2015 - Maxime Coquelin - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "stm32f429.dtsi" -#include "stm32f429-pinctrl.dtsi" -#include -#include - -/ { - model = "STMicroelectronics STM32429i-EVAL board"; - compatible = "st,stm32429i-eval", "st,stm32f429"; - - chosen { - bootargs = "root=/dev/ram"; - stdout-path = "serial0:115200n8"; - }; - - memory@00000000 { - device_type = "memory"; - reg = <0x00000000 0x2000000>; - }; - - aliases { - serial0 = &usart1; - }; - - clocks { - clk_ext_camera: clk-ext-camera { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - }; - }; - - soc { - dma-ranges = <0xc0000000 0x0 0x10000000>; - }; - - vdda: regulator-vdda { - compatible = "regulator-fixed"; - regulator-name = "vdda"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vref: regulator-vref { - compatible = "regulator-fixed"; - regulator-name = "vref"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vdd_panel: vdd-panel { - compatible = "regulator-fixed"; - regulator-name = "vdd_panel"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - leds { - compatible = "gpio-leds"; - green { - gpios = <&gpiog 6 1>; - linux,default-trigger = "heartbeat"; - }; - orange { - gpios = <&gpiog 7 1>; - }; - red { - gpios = <&gpiog 10 1>; - }; - blue { - gpios = <&gpiog 12 1>; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - autorepeat; - button@0 { - label = "Wake up"; - linux,code = ; - gpios = <&gpioa 0 0>; - }; - button@1 { - label = "Tamper"; - linux,code = ; - gpios = <&gpioc 13 0>; - }; - }; - - usbotg_hs_phy: usbphy { - #phy-cells = <0>; - compatible = "usb-nop-xceiv"; - clocks = <&rcc 0 STM32F4_AHB1_CLOCK(OTGHSULPI)>; - clock-names = "main_clk"; - }; - - panel_rgb: panel-rgb { - compatible = "ampire,am-480272h3tmqw-t01h"; - power-supply = <&vdd_panel>; - status = "okay"; - port { - panel_in_rgb: endpoint { - remote-endpoint = <<dc_out_rgb>; - }; - }; - }; - - mmc_vcard: mmc_vcard { - compatible = "regulator-fixed"; - regulator-name = "mmc_vcard"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&adc { - pinctrl-names = "default"; - pinctrl-0 = <&adc3_in8_pin>; - vdda-supply = <&vdda>; - vref-supply = <&vref>; - status = "okay"; - adc3: adc@200 { - st,adc-channels = <8>; - status = "okay"; - }; -}; - -&clk_hse { - clock-frequency = <25000000>; -}; - -&crc { - status = "okay"; -}; - -&dcmi { - status = "okay"; - - port { - dcmi_0: endpoint { - remote-endpoint = <&ov2640_0>; - bus-width = <8>; - hsync-active = <0>; - vsync-active = <0>; - pclk-sample = <1>; - }; - }; -}; - -&i2c1 { - pinctrl-0 = <&i2c1_pins>; - pinctrl-names = "default"; - status = "okay"; - - ov2640: camera@30 { - compatible = "ovti,ov2640"; - reg = <0x30>; - resetb-gpios = <&stmpegpio 2 GPIO_ACTIVE_HIGH>; - pwdn-gpios = <&stmpegpio 0 GPIO_ACTIVE_LOW>; - clocks = <&clk_ext_camera>; - clock-names = "xvclk"; - status = "okay"; - - port { - ov2640_0: endpoint { - remote-endpoint = <&dcmi_0>; - }; - }; - }; - - stmpe1600: stmpe1600@42 { - compatible = "st,stmpe1600"; - reg = <0x42>; - interrupts = <8 3>; - interrupt-parent = <&gpioi>; - interrupt-controller; - wakeup-source; - - stmpegpio: stmpe_gpio { - compatible = "st,stmpe-gpio"; - gpio-controller; - #gpio-cells = <2>; - }; - }; -}; - -&iwdg { - status = "okay"; - timeout-sec = <32>; -}; - -<dc { - status = "okay"; - pinctrl-0 = <<dc_pins>; - pinctrl-names = "default"; - - port { - ltdc_out_rgb: endpoint { - remote-endpoint = <&panel_in_rgb>; - }; - }; -}; - -&mac { - status = "okay"; - pinctrl-0 = <ðernet_mii>; - pinctrl-names = "default"; - phy-mode = "mii"; - phy-handle = <&phy1>; - mdio0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - phy1: ethernet-phy@1 { - reg = <1>; - }; - }; -}; - -&rtc { - status = "okay"; -}; - -&sdio { - status = "okay"; - vmmc-supply = <&mmc_vcard>; - cd-gpios = <&stmpegpio 15 GPIO_ACTIVE_LOW>; - pinctrl-names = "default", "opendrain"; - pinctrl-0 = <&sdio_pins>; - pinctrl-1 = <&sdio_pins_od>; - bus-width = <4>; - max-frequency = <12500000>; -}; - -&timers1 { - status = "okay"; - - pwm { - pinctrl-0 = <&pwm1_pins>; - pinctrl-names = "default"; - status = "okay"; - }; - - timer@0 { - status = "okay"; - }; -}; - -&timers3 { - status = "okay"; - - pwm { - pinctrl-0 = <&pwm3_pins>; - pinctrl-names = "default"; - status = "okay"; - }; - - timer@2 { - status = "okay"; - }; -}; - -&usart1 { - pinctrl-0 = <&usart1_pins_a>; - pinctrl-names = "default"; - status = "okay"; -}; - -&usbotg_hs { - dr_mode = "host"; - phys = <&usbotg_hs_phy>; - phy-names = "usb2-phy"; - pinctrl-0 = <&usbotg_hs_pins_a>; - pinctrl-names = "default"; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/stm32746g-eval.dts b/sys/gnu/dts/arm/stm32746g-eval.dts deleted file mode 100644 index fcc804e3c15..00000000000 --- a/sys/gnu/dts/arm/stm32746g-eval.dts +++ /dev/null @@ -1,212 +0,0 @@ -/* - * Copyright 2015 - Maxime Coquelin - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "stm32f746.dtsi" -#include "stm32f746-pinctrl.dtsi" -#include -#include - -/ { - model = "STMicroelectronics STM32746g-EVAL board"; - compatible = "st,stm32746g-eval", "st,stm32f746"; - - chosen { - bootargs = "root=/dev/ram"; - stdout-path = "serial0:115200n8"; - }; - - memory@c0000000 { - device_type = "memory"; - reg = <0xc0000000 0x2000000>; - }; - - aliases { - serial0 = &usart1; - }; - - leds { - compatible = "gpio-leds"; - green { - gpios = <&gpiof 10 1>; - linux,default-trigger = "heartbeat"; - }; - orange { - gpios = <&stmfx_pinctrl 17 1>; - }; - red { - gpios = <&gpiob 7 1>; - }; - blue { - gpios = <&stmfx_pinctrl 19 1>; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - autorepeat; - button@0 { - label = "Wake up"; - linux,code = ; - gpios = <&gpioc 13 0>; - }; - }; - - joystick { - compatible = "gpio-keys"; - pinctrl-0 = <&joystick_pins>; - pinctrl-names = "default"; - button-0 { - label = "JoySel"; - linux,code = ; - interrupt-parent = <&stmfx_pinctrl>; - interrupts = <0 IRQ_TYPE_EDGE_FALLING>; - }; - button-1 { - label = "JoyDown"; - linux,code = ; - interrupt-parent = <&stmfx_pinctrl>; - interrupts = <1 IRQ_TYPE_EDGE_FALLING>; - }; - button-2 { - label = "JoyLeft"; - linux,code = ; - interrupt-parent = <&stmfx_pinctrl>; - interrupts = <2 IRQ_TYPE_EDGE_FALLING>; - }; - button-3 { - label = "JoyRight"; - linux,code = ; - interrupt-parent = <&stmfx_pinctrl>; - interrupts = <3 IRQ_TYPE_EDGE_FALLING>; - }; - button-4 { - label = "JoyUp"; - linux,code = ; - interrupt-parent = <&stmfx_pinctrl>; - interrupts = <4 IRQ_TYPE_EDGE_FALLING>; - }; - }; - - usbotg_hs_phy: usb-phy { - #phy-cells = <0>; - compatible = "usb-nop-xceiv"; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHSULPI)>; - clock-names = "main_clk"; - }; - - mmc_vcard: mmc_vcard { - compatible = "regulator-fixed"; - regulator-name = "mmc_vcard"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&clk_hse { - clock-frequency = <25000000>; -}; - -&crc { - status = "okay"; -}; - -&i2c1 { - pinctrl-0 = <&i2c1_pins_b>; - pinctrl-names = "default"; - i2c-scl-rising-time-ns = <185>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; - - stmfx: stmfx@42 { - compatible = "st,stmfx-0300"; - reg = <0x42>; - interrupts = <8 IRQ_TYPE_EDGE_RISING>; - interrupt-parent = <&gpioi>; - - stmfx_pinctrl: stmfx-pin-controller { - compatible = "st,stmfx-0300-pinctrl"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&stmfx_pinctrl 0 0 24>; - - joystick_pins: joystick { - pins = "gpio0", "gpio1", "gpio2", "gpio3", "gpio4"; - drive-push-pull; - bias-pull-up; - }; - }; - }; -}; - -&rtc { - status = "okay"; -}; - -&sdio1 { - status = "okay"; - vmmc-supply = <&mmc_vcard>; - broken-cd; - pinctrl-names = "default", "opendrain"; - pinctrl-0 = <&sdio_pins_a>; - pinctrl-1 = <&sdio_pins_od_a>; - bus-width = <4>; -}; - -&usart1 { - pinctrl-0 = <&usart1_pins_a>; - pinctrl-names = "default"; - status = "okay"; -}; - -&usbotg_hs { - dr_mode = "otg"; - phys = <&usbotg_hs_phy>; - phy-names = "usb2-phy"; - pinctrl-0 = <&usbotg_hs_pins_a>; - pinctrl-names = "default"; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/stm32f4-pinctrl.dtsi b/sys/gnu/dts/arm/stm32f4-pinctrl.dtsi deleted file mode 100644 index 392fa143ce0..00000000000 --- a/sys/gnu/dts/arm/stm32f4-pinctrl.dtsi +++ /dev/null @@ -1,374 +0,0 @@ -/* - * Copyright 2017 - Alexandre Torgue - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include -#include - -/ { - soc { - pinctrl: pin-controller { - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x40020000 0x3000>; - interrupt-parent = <&exti>; - st,syscfg = <&syscfg 0x8>; - pins-are-numbered; - - gpioa: gpio@40020000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x0 0x400>; - clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>; - st,bank-name = "GPIOA"; - }; - - gpiob: gpio@40020400 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x400 0x400>; - clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOB)>; - st,bank-name = "GPIOB"; - }; - - gpioc: gpio@40020800 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x800 0x400>; - clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOC)>; - st,bank-name = "GPIOC"; - }; - - gpiod: gpio@40020c00 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0xc00 0x400>; - clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOD)>; - st,bank-name = "GPIOD"; - }; - - gpioe: gpio@40021000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1000 0x400>; - clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOE)>; - st,bank-name = "GPIOE"; - }; - - gpiof: gpio@40021400 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1400 0x400>; - clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOF)>; - st,bank-name = "GPIOF"; - }; - - gpiog: gpio@40021800 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1800 0x400>; - clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOG)>; - st,bank-name = "GPIOG"; - }; - - gpioh: gpio@40021c00 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1c00 0x400>; - clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOH)>; - st,bank-name = "GPIOH"; - }; - - gpioi: gpio@40022000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x2000 0x400>; - clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOI)>; - st,bank-name = "GPIOI"; - }; - - gpioj: gpio@40022400 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x2400 0x400>; - clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOJ)>; - st,bank-name = "GPIOJ"; - }; - - gpiok: gpio@40022800 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x2800 0x400>; - clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOK)>; - st,bank-name = "GPIOK"; - }; - - usart1_pins_a: usart1-0 { - pins1 { - pinmux = ; /* USART1_TX */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = ; /* USART1_RX */ - bias-disable; - }; - }; - - usart3_pins_a: usart3-0 { - pins1 { - pinmux = ; /* USART3_TX */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = ; /* USART3_RX */ - bias-disable; - }; - }; - - usbotg_fs_pins_a: usbotg-fs-0 { - pins { - pinmux = , /* OTG_FS_ID */ - , /* OTG_FS_DM */ - ; /* OTG_FS_DP */ - bias-disable; - drive-push-pull; - slew-rate = <2>; - }; - }; - - usbotg_fs_pins_b: usbotg-fs-1 { - pins { - pinmux = , /* OTG_HS_ID */ - , /* OTG_HS_DM */ - ; /* OTG_HS_DP */ - bias-disable; - drive-push-pull; - slew-rate = <2>; - }; - }; - - usbotg_hs_pins_a: usbotg-hs-0 { - pins { - pinmux = , /* OTG_HS_ULPI_NXT*/ - , /* OTG_HS_ULPI_DIR */ - , /* OTG_HS_ULPI_STP */ - , /* OTG_HS_ULPI_CK */ - , /* OTG_HS_ULPI_D0 */ - , /* OTG_HS_ULPI_D1 */ - , /* OTG_HS_ULPI_D2 */ - , /* OTG_HS_ULPI_D3 */ - , /* OTG_HS_ULPI_D4 */ - , /* OTG_HS_ULPI_D5 */ - , /* OTG_HS_ULPI_D6 */ - ; /* OTG_HS_ULPI_D7 */ - bias-disable; - drive-push-pull; - slew-rate = <2>; - }; - }; - - ethernet_mii: mii-0 { - pins { - pinmux = , /* ETH_MII_TXD0_ETH_RMII_TXD0 */ - , /* ETH_MII_TXD1_ETH_RMII_TXD1 */ - , /* ETH_MII_TXD2 */ - , /* ETH_MII_TXD3 */ - , /* ETH_MII_TX_CLK */ - , /* ETH_MII_TX_EN_ETH_RMII_TX_EN */ - , /* ETH_MDIO */ - , /* ETH_MDC */ - , /* ETH_MII_RX_CLK_ETH_RMII_REF_CLK */ - , /* ETH_MII_RX_DV_ETH_RMII_CRS_DV */ - , /* ETH_MII_RXD0_ETH_RMII_RXD0 */ - , /* ETH_MII_RXD1_ETH_RMII_RXD1 */ - , /* ETH_MII_RXD2 */ - ; /* ETH_MII_RXD3 */ - slew-rate = <2>; - }; - }; - - adc3_in8_pin: adc-200 { - pins { - pinmux = ; - }; - }; - - pwm1_pins: pwm-1 { - pins { - pinmux = , /* TIM1_CH1 */ - , /* TIM1_CH1N */ - ; /* TIM1_BKIN */ - }; - }; - - pwm3_pins: pwm-3 { - pins { - pinmux = , /* TIM3_CH1 */ - ; /* TIM3_CH2 */ - }; - }; - - i2c1_pins: i2c1-0 { - pins { - pinmux = , /* I2C1_SDA */ - ; /* I2C1_SCL */ - bias-disable; - drive-open-drain; - slew-rate = <3>; - }; - }; - - ltdc_pins: ltdc-0 { - pins { - pinmux = , /* LCD_HSYNC */ - , /* LCD_VSYNC */ - , /* LCD_CLK */ - , /* LCD_R0 */ - , /* LCD_R1 */ - , /* LCD_R2 */ - , /* LCD_R3 */ - , /* LCD_R4 */ - , /* LCD_R5 */ - , /* LCD_R6*/ - , /* LCD_R7 */ - , /* LCD_G0 */ - , /* LCD_G1 */ - , /* LCD_G2 */ - , /* LCD_G3 */ - , /* LCD_G4 */ - , /* LCD_B0 */ - , /* LCD_B1 */ - , /* LCD_B2 */ - , /* LCD_B3*/ - , /* LCD_G5 */ - , /* LCD_G6 */ - , /* LCD_G7 */ - , /* LCD_B4 */ - , /* LCD_B5 */ - , /* LCD_B6 */ - , /* LCD_B7 */ - ; /* LCD_DE */ - slew-rate = <2>; - }; - }; - - dcmi_pins: dcmi-0 { - pins { - pinmux = , /* DCMI_HSYNC */ - , /* DCMI_VSYNC */ - , /* DCMI_PIXCLK */ - , /* DCMI_D0 */ - , /* DCMI_D1 */ - , /* DCMI_D2 */ - , /* DCMI_D3 */ - , /*DCMI_D4 */ - , /* DCMI_D5 */ - , /* DCMI_D6 */ - , /* DCMI_D7 */ - , /* DCMI_D8 */ - , /* DCMI_D9 */ - , /* DCMI_D10 */ - ; /* DCMI_D11 */ - bias-disable; - drive-push-pull; - slew-rate = <3>; - }; - }; - - sdio_pins: sdio-pins-0 { - pins { - pinmux = , /* SDIO_D0 */ - , /* SDIO_D1 */ - , /* SDIO_D2 */ - , /* SDIO_D3 */ - , /* SDIO_CK */ - ; /* SDIO_CMD */ - drive-push-pull; - slew-rate = <2>; - }; - }; - - sdio_pins_od: sdio-pins-od-0 { - pins1 { - pinmux = , /* SDIO_D0 */ - , /* SDIO_D1 */ - , /* SDIO_D2 */ - , /* SDIO_D3 */ - ; /* SDIO_CK */ - drive-push-pull; - slew-rate = <2>; - }; - - pins2 { - pinmux = ; /* SDIO_CMD */ - drive-open-drain; - slew-rate = <2>; - }; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/stm32f429-disco.dts b/sys/gnu/dts/arm/stm32f429-disco.dts deleted file mode 100644 index 30c0f671787..00000000000 --- a/sys/gnu/dts/arm/stm32f429-disco.dts +++ /dev/null @@ -1,129 +0,0 @@ -/* - * Copyright 2015 - Maxime Coquelin - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "stm32f429.dtsi" -#include "stm32f429-pinctrl.dtsi" -#include - -/ { - model = "STMicroelectronics STM32F429i-DISCO board"; - compatible = "st,stm32f429i-disco", "st,stm32f429"; - - chosen { - bootargs = "root=/dev/ram"; - stdout-path = "serial0:115200n8"; - }; - - memory@90000000 { - device_type = "memory"; - reg = <0x90000000 0x800000>; - }; - - aliases { - serial0 = &usart1; - }; - - leds { - compatible = "gpio-leds"; - red { - gpios = <&gpiog 14 0>; - }; - green { - gpios = <&gpiog 13 0>; - linux,default-trigger = "heartbeat"; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - autorepeat; - button@0 { - label = "User"; - linux,code = ; - gpios = <&gpioa 0 0>; - }; - }; - - /* This turns on vbus for otg for host mode (dwc2) */ - vcc5v_otg: vcc5v-otg-regulator { - compatible = "regulator-fixed"; - gpio = <&gpioc 4 0>; - regulator-name = "vcc5_host1"; - regulator-always-on; - }; -}; - -&clk_hse { - clock-frequency = <8000000>; -}; - -&crc { - status = "okay"; -}; - -&rtc { - assigned-clocks = <&rcc 1 CLK_RTC>; - assigned-clock-parents = <&rcc 1 CLK_LSI>; - status = "okay"; -}; - -&usart1 { - pinctrl-0 = <&usart1_pins_a>; - pinctrl-names = "default"; - status = "okay"; -}; - -&usbotg_hs { - compatible = "st,stm32f4x9-fsotg"; - dr_mode = "host"; - pinctrl-0 = <&usbotg_fs_pins_b>; - pinctrl-names = "default"; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/stm32f429-pinctrl.dtsi b/sys/gnu/dts/arm/stm32f429-pinctrl.dtsi deleted file mode 100644 index 3e7a17d9112..00000000000 --- a/sys/gnu/dts/arm/stm32f429-pinctrl.dtsi +++ /dev/null @@ -1,95 +0,0 @@ -/* - * Copyright 2017 - Alexandre Torgue - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "stm32f4-pinctrl.dtsi" - -/ { - soc { - pinctrl: pin-controller { - compatible = "st,stm32f429-pinctrl"; - - gpioa: gpio@40020000 { - gpio-ranges = <&pinctrl 0 0 16>; - }; - - gpiob: gpio@40020400 { - gpio-ranges = <&pinctrl 0 16 16>; - }; - - gpioc: gpio@40020800 { - gpio-ranges = <&pinctrl 0 32 16>; - }; - - gpiod: gpio@40020c00 { - gpio-ranges = <&pinctrl 0 48 16>; - }; - - gpioe: gpio@40021000 { - gpio-ranges = <&pinctrl 0 64 16>; - }; - - gpiof: gpio@40021400 { - gpio-ranges = <&pinctrl 0 80 16>; - }; - - gpiog: gpio@40021800 { - gpio-ranges = <&pinctrl 0 96 16>; - }; - - gpioh: gpio@40021c00 { - gpio-ranges = <&pinctrl 0 112 16>; - }; - - gpioi: gpio@40022000 { - gpio-ranges = <&pinctrl 0 128 16>; - }; - - gpioj: gpio@40022400 { - gpio-ranges = <&pinctrl 0 144 16>; - }; - - gpiok: gpio@40022800 { - gpio-ranges = <&pinctrl 0 160 8>; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/stm32f429.dtsi b/sys/gnu/dts/arm/stm32f429.dtsi deleted file mode 100644 index d7770699feb..00000000000 --- a/sys/gnu/dts/arm/stm32f429.dtsi +++ /dev/null @@ -1,800 +0,0 @@ -/* - * Copyright 2015 - Maxime Coquelin - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "armv7-m.dtsi" -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - - clocks { - clk_hse: clk-hse { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - clk_lse: clk-lse { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - clk_lsi: clk-lsi { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32000>; - }; - - clk_i2s_ckin: i2s-ckin { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - }; - - soc { - romem: efuse@1fff7800 { - compatible = "st,stm32f4-otp"; - reg = <0x1fff7800 0x400>; - #address-cells = <1>; - #size-cells = <1>; - ts_cal1: calib@22c { - reg = <0x22c 0x2>; - }; - ts_cal2: calib@22e { - reg = <0x22e 0x2>; - }; - }; - - timer2: timer@40000000 { - compatible = "st,stm32-timer"; - reg = <0x40000000 0x400>; - interrupts = <28>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>; - status = "disabled"; - }; - - timers2: timers@40000000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40000000 0x400>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@1 { - compatible = "st,stm32-timer-trigger"; - reg = <1>; - status = "disabled"; - }; - }; - - timer3: timer@40000400 { - compatible = "st,stm32-timer"; - reg = <0x40000400 0x400>; - interrupts = <29>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>; - status = "disabled"; - }; - - timers3: timers@40000400 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40000400 0x400>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@2 { - compatible = "st,stm32-timer-trigger"; - reg = <2>; - status = "disabled"; - }; - }; - - timer4: timer@40000800 { - compatible = "st,stm32-timer"; - reg = <0x40000800 0x400>; - interrupts = <30>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>; - status = "disabled"; - }; - - timers4: timers@40000800 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40000800 0x400>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@3 { - compatible = "st,stm32-timer-trigger"; - reg = <3>; - status = "disabled"; - }; - }; - - timer5: timer@40000c00 { - compatible = "st,stm32-timer"; - reg = <0x40000c00 0x400>; - interrupts = <50>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>; - }; - - timers5: timers@40000c00 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40000C00 0x400>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@4 { - compatible = "st,stm32-timer-trigger"; - reg = <4>; - status = "disabled"; - }; - }; - - timer6: timer@40001000 { - compatible = "st,stm32-timer"; - reg = <0x40001000 0x400>; - interrupts = <54>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>; - status = "disabled"; - }; - - timers6: timers@40001000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40001000 0x400>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>; - clock-names = "int"; - status = "disabled"; - - timer@5 { - compatible = "st,stm32-timer-trigger"; - reg = <5>; - status = "disabled"; - }; - }; - - timer7: timer@40001400 { - compatible = "st,stm32-timer"; - reg = <0x40001400 0x400>; - interrupts = <55>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>; - status = "disabled"; - }; - - timers7: timers@40001400 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40001400 0x400>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>; - clock-names = "int"; - status = "disabled"; - - timer@6 { - compatible = "st,stm32-timer-trigger"; - reg = <6>; - status = "disabled"; - }; - }; - - timers12: timers@40001800 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40001800 0x400>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM12)>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@11 { - compatible = "st,stm32-timer-trigger"; - reg = <11>; - status = "disabled"; - }; - }; - - timers13: timers@40001c00 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40001C00 0x400>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM13)>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - }; - - timers14: timers@40002000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40002000 0x400>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM14)>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - }; - - rtc: rtc@40002800 { - compatible = "st,stm32-rtc"; - reg = <0x40002800 0x400>; - clocks = <&rcc 1 CLK_RTC>; - assigned-clocks = <&rcc 1 CLK_RTC>; - assigned-clock-parents = <&rcc 1 CLK_LSE>; - interrupt-parent = <&exti>; - interrupts = <17 1>; - interrupt-names = "alarm"; - st,syscfg = <&pwrcfg 0x00 0x100>; - status = "disabled"; - }; - - iwdg: watchdog@40003000 { - compatible = "st,stm32-iwdg"; - reg = <0x40003000 0x400>; - clocks = <&clk_lsi>; - clock-names = "lsi"; - status = "disabled"; - }; - - spi2: spi@40003800 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32f4-spi"; - reg = <0x40003800 0x400>; - interrupts = <36>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(SPI2)>; - status = "disabled"; - }; - - spi3: spi@40003c00 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32f4-spi"; - reg = <0x40003c00 0x400>; - interrupts = <51>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(SPI3)>; - status = "disabled"; - }; - - usart2: serial@40004400 { - compatible = "st,stm32-uart"; - reg = <0x40004400 0x400>; - interrupts = <38>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART2)>; - status = "disabled"; - }; - - usart3: serial@40004800 { - compatible = "st,stm32-uart"; - reg = <0x40004800 0x400>; - interrupts = <39>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART3)>; - status = "disabled"; - dmas = <&dma1 1 4 0x400 0x0>, - <&dma1 3 4 0x400 0x0>; - dma-names = "rx", "tx"; - }; - - usart4: serial@40004c00 { - compatible = "st,stm32-uart"; - reg = <0x40004c00 0x400>; - interrupts = <52>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART4)>; - status = "disabled"; - }; - - usart5: serial@40005000 { - compatible = "st,stm32-uart"; - reg = <0x40005000 0x400>; - interrupts = <53>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART5)>; - status = "disabled"; - }; - - i2c1: i2c@40005400 { - compatible = "st,stm32f4-i2c"; - reg = <0x40005400 0x400>; - interrupts = <31>, - <32>; - resets = <&rcc STM32F4_APB1_RESET(I2C1)>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C1)>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - dac: dac@40007400 { - compatible = "st,stm32f4-dac-core"; - reg = <0x40007400 0x400>; - resets = <&rcc STM32F4_APB1_RESET(DAC)>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(DAC)>; - clock-names = "pclk"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - dac1: dac@1 { - compatible = "st,stm32-dac"; - #io-channels-cells = <1>; - reg = <1>; - status = "disabled"; - }; - - dac2: dac@2 { - compatible = "st,stm32-dac"; - #io-channels-cells = <1>; - reg = <2>; - status = "disabled"; - }; - }; - - usart7: serial@40007800 { - compatible = "st,stm32-uart"; - reg = <0x40007800 0x400>; - interrupts = <82>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART7)>; - status = "disabled"; - }; - - usart8: serial@40007c00 { - compatible = "st,stm32-uart"; - reg = <0x40007c00 0x400>; - interrupts = <83>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART8)>; - status = "disabled"; - }; - - timers1: timers@40010000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40010000 0x400>; - clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM1)>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@0 { - compatible = "st,stm32-timer-trigger"; - reg = <0>; - status = "disabled"; - }; - }; - - timers8: timers@40010400 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40010400 0x400>; - clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM8)>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@7 { - compatible = "st,stm32-timer-trigger"; - reg = <7>; - status = "disabled"; - }; - }; - - usart1: serial@40011000 { - compatible = "st,stm32-uart"; - reg = <0x40011000 0x400>; - interrupts = <37>; - clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART1)>; - status = "disabled"; - dmas = <&dma2 2 4 0x400 0x0>, - <&dma2 7 4 0x400 0x0>; - dma-names = "rx", "tx"; - }; - - usart6: serial@40011400 { - compatible = "st,stm32-uart"; - reg = <0x40011400 0x400>; - interrupts = <71>; - clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART6)>; - status = "disabled"; - }; - - adc: adc@40012000 { - compatible = "st,stm32f4-adc-core"; - reg = <0x40012000 0x400>; - interrupts = <18>; - clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>; - clock-names = "adc"; - interrupt-controller; - #interrupt-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - adc1: adc@0 { - compatible = "st,stm32f4-adc"; - #io-channel-cells = <1>; - reg = <0x0>; - clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>; - interrupt-parent = <&adc>; - interrupts = <0>; - dmas = <&dma2 0 0 0x400 0x0>; - dma-names = "rx"; - status = "disabled"; - }; - - adc2: adc@100 { - compatible = "st,stm32f4-adc"; - #io-channel-cells = <1>; - reg = <0x100>; - clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC2)>; - interrupt-parent = <&adc>; - interrupts = <1>; - dmas = <&dma2 3 1 0x400 0x0>; - dma-names = "rx"; - status = "disabled"; - }; - - adc3: adc@200 { - compatible = "st,stm32f4-adc"; - #io-channel-cells = <1>; - reg = <0x200>; - clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC3)>; - interrupt-parent = <&adc>; - interrupts = <2>; - dmas = <&dma2 1 2 0x400 0x0>; - dma-names = "rx"; - status = "disabled"; - }; - }; - - sdio: sdio@40012c00 { - compatible = "arm,pl180", "arm,primecell"; - arm,primecell-periphid = <0x00880180>; - reg = <0x40012c00 0x400>; - clocks = <&rcc 0 STM32F4_APB2_CLOCK(SDIO)>; - clock-names = "apb_pclk"; - interrupts = <49>; - max-frequency = <48000000>; - status = "disabled"; - }; - - spi1: spi@40013000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32f4-spi"; - reg = <0x40013000 0x400>; - interrupts = <35>; - clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI1)>; - status = "disabled"; - }; - - spi4: spi@40013400 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32f4-spi"; - reg = <0x40013400 0x400>; - interrupts = <84>; - clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI4)>; - status = "disabled"; - }; - - syscfg: system-config@40013800 { - compatible = "syscon"; - reg = <0x40013800 0x400>; - }; - - exti: interrupt-controller@40013c00 { - compatible = "st,stm32-exti"; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x40013C00 0x400>; - interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>; - }; - - timers9: timers@40014000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40014000 0x400>; - clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM9)>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@8 { - compatible = "st,stm32-timer-trigger"; - reg = <8>; - status = "disabled"; - }; - }; - - timers10: timers@40014400 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40014400 0x400>; - clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM10)>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - }; - - timers11: timers@40014800 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40014800 0x400>; - clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM11)>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - }; - - spi5: spi@40015000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32f4-spi"; - reg = <0x40015000 0x400>; - interrupts = <85>; - clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI5)>; - status = "disabled"; - }; - - spi6: spi@40015400 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32f4-spi"; - reg = <0x40015400 0x400>; - interrupts = <86>; - clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI6)>; - status = "disabled"; - }; - - pwrcfg: power-config@40007000 { - compatible = "syscon"; - reg = <0x40007000 0x400>; - }; - - ltdc: display-controller@40016800 { - compatible = "st,stm32-ltdc"; - reg = <0x40016800 0x200>; - interrupts = <88>, <89>; - resets = <&rcc STM32F4_APB2_RESET(LTDC)>; - clocks = <&rcc 1 CLK_LCD>; - clock-names = "lcd"; - status = "disabled"; - }; - - crc: crc@40023000 { - compatible = "st,stm32f4-crc"; - reg = <0x40023000 0x400>; - clocks = <&rcc 0 STM32F4_AHB1_CLOCK(CRC)>; - status = "disabled"; - }; - - rcc: rcc@40023810 { - #reset-cells = <1>; - #clock-cells = <2>; - compatible = "st,stm32f42xx-rcc", "st,stm32-rcc"; - reg = <0x40023800 0x400>; - clocks = <&clk_hse>, <&clk_i2s_ckin>; - st,syscfg = <&pwrcfg>; - assigned-clocks = <&rcc 1 CLK_HSE_RTC>; - assigned-clock-rates = <1000000>; - }; - - dma1: dma-controller@40026000 { - compatible = "st,stm32-dma"; - reg = <0x40026000 0x400>; - interrupts = <11>, - <12>, - <13>, - <14>, - <15>, - <16>, - <17>, - <47>; - clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA1)>; - #dma-cells = <4>; - }; - - dma2: dma-controller@40026400 { - compatible = "st,stm32-dma"; - reg = <0x40026400 0x400>; - interrupts = <56>, - <57>, - <58>, - <59>, - <60>, - <68>, - <69>, - <70>; - clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2)>; - #dma-cells = <4>; - st,mem2mem; - }; - - mac: ethernet@40028000 { - compatible = "st,stm32-dwmac", "snps,dwmac-3.50a"; - reg = <0x40028000 0x8000>; - reg-names = "stmmaceth"; - interrupts = <61>; - interrupt-names = "macirq"; - clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx"; - clocks = <&rcc 0 STM32F4_AHB1_CLOCK(ETHMAC)>, - <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACTX)>, - <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACRX)>; - st,syscon = <&syscfg 0x4>; - snps,pbl = <8>; - snps,mixed-burst; - status = "disabled"; - }; - - usbotg_hs: usb@40040000 { - compatible = "snps,dwc2"; - reg = <0x40040000 0x40000>; - interrupts = <77>; - clocks = <&rcc 0 STM32F4_AHB1_CLOCK(OTGHS)>; - clock-names = "otg"; - status = "disabled"; - }; - - usbotg_fs: usb@50000000 { - compatible = "st,stm32f4x9-fsotg"; - reg = <0x50000000 0x40000>; - interrupts = <67>; - clocks = <&rcc 0 39>; - clock-names = "otg"; - status = "disabled"; - }; - - dcmi: dcmi@50050000 { - compatible = "st,stm32-dcmi"; - reg = <0x50050000 0x400>; - interrupts = <78>; - resets = <&rcc STM32F4_AHB2_RESET(DCMI)>; - clocks = <&rcc 0 STM32F4_AHB2_CLOCK(DCMI)>; - clock-names = "mclk"; - pinctrl-names = "default"; - pinctrl-0 = <&dcmi_pins>; - dmas = <&dma2 1 1 0x414 0x3>; - dma-names = "tx"; - status = "disabled"; - }; - - rng: rng@50060800 { - compatible = "st,stm32-rng"; - reg = <0x50060800 0x400>; - clocks = <&rcc 0 STM32F4_AHB2_CLOCK(RNG)>; - - }; - }; -}; - -&systick { - clocks = <&rcc 1 SYSTICK>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/stm32f469-disco.dts b/sys/gnu/dts/arm/stm32f469-disco.dts deleted file mode 100644 index 9397db0c43d..00000000000 --- a/sys/gnu/dts/arm/stm32f469-disco.dts +++ /dev/null @@ -1,240 +0,0 @@ -/* - * Copyright 2016 - Lee Jones - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "stm32f469.dtsi" -#include "stm32f469-pinctrl.dtsi" -#include -#include - -/ { - model = "STMicroelectronics STM32F469i-DISCO board"; - compatible = "st,stm32f469i-disco", "st,stm32f469"; - - chosen { - bootargs = "root=/dev/ram"; - stdout-path = "serial0:115200n8"; - }; - - memory@00000000 { - device_type = "memory"; - reg = <0x00000000 0x1000000>; - }; - - aliases { - serial0 = &usart3; - }; - - mmc_vcard: mmc_vcard { - compatible = "regulator-fixed"; - regulator-name = "mmc_vcard"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vdd_dsi: vdd-dsi { - compatible = "regulator-fixed"; - regulator-name = "vdd_dsi"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - soc { - dma-ranges = <0xc0000000 0x0 0x10000000>; - }; - - leds { - compatible = "gpio-leds"; - green { - gpios = <&gpiog 6 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - }; - orange { - gpios = <&gpiod 4 GPIO_ACTIVE_LOW>; - }; - red { - gpios = <&gpiod 5 GPIO_ACTIVE_LOW>; - }; - blue { - gpios = <&gpiok 3 GPIO_ACTIVE_LOW>; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - autorepeat; - button@0 { - label = "User"; - linux,code = ; - gpios = <&gpioa 0 GPIO_ACTIVE_HIGH>; - }; - }; - - /* This turns on vbus for otg for host mode (dwc2) */ - vcc5v_otg: vcc5v-otg-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpiob 2 GPIO_ACTIVE_HIGH>; - regulator-name = "vcc5_host1"; - regulator-always-on; - }; -}; - -&rcc { - compatible = "st,stm32f469-rcc", "st,stm32f42xx-rcc", "st,stm32-rcc"; -}; - -&clk_hse { - clock-frequency = <8000000>; -}; - -&dsi { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dsi_in: endpoint { - remote-endpoint = <<dc_out_dsi>; - }; - }; - - port@1 { - reg = <1>; - dsi_out: endpoint { - remote-endpoint = <&dsi_panel_in>; - }; - }; - }; - - panel-dsi@0 { - compatible = "orisetech,otm8009a"; - reg = <0>; /* dsi virtual channel (0..3) */ - reset-gpios = <&gpioh 7 GPIO_ACTIVE_LOW>; - power-supply = <&vdd_dsi>; - status = "okay"; - - port { - dsi_panel_in: endpoint { - remote-endpoint = <&dsi_out>; - }; - }; - }; -}; - -<dc { - status = "okay"; - - port { - ltdc_out_dsi: endpoint@0 { - remote-endpoint = <&dsi_in>; - }; - }; -}; - -&rtc { - status = "okay"; -}; - -&timers1 { - status = "okay"; - - pwm { - pinctrl-0 = <&pwm1_pins>; - pinctrl-names = "default"; - status = "okay"; - }; - - timer@0 { - status = "okay"; - }; -}; - -&timers3 { - status = "okay"; - - pwm { - pinctrl-0 = <&pwm3_pins>; - pinctrl-names = "default"; - status = "okay"; - }; - - timer@2 { - status = "okay"; - }; -}; - -&sdio { - status = "okay"; - vmmc-supply = <&mmc_vcard>; - cd-gpios = <&gpiog 2 GPIO_ACTIVE_LOW>; - broken-cd; - pinctrl-names = "default", "opendrain"; - pinctrl-0 = <&sdio_pins>; - pinctrl-1 = <&sdio_pins_od>; - bus-width = <4>; -}; - -&usart3 { - pinctrl-0 = <&usart3_pins_a>; - pinctrl-names = "default"; - status = "okay"; -}; - -&usbotg_fs { - dr_mode = "host"; - pinctrl-0 = <&usbotg_fs_pins_a>; - pinctrl-names = "default"; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/stm32f469-pinctrl.dtsi b/sys/gnu/dts/arm/stm32f469-pinctrl.dtsi deleted file mode 100644 index fff542662ee..00000000000 --- a/sys/gnu/dts/arm/stm32f469-pinctrl.dtsi +++ /dev/null @@ -1,96 +0,0 @@ -/* - * Copyright 2017 - Alexandre Torgue - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "stm32f4-pinctrl.dtsi" - -/ { - soc { - pinctrl: pin-controller { - compatible = "st,stm32f469-pinctrl"; - - gpioa: gpio@40020000 { - gpio-ranges = <&pinctrl 0 0 16>; - }; - - gpiob: gpio@40020400 { - gpio-ranges = <&pinctrl 0 16 16>; - }; - - gpioc: gpio@40020800 { - gpio-ranges = <&pinctrl 0 32 16>; - }; - - gpiod: gpio@40020c00 { - gpio-ranges = <&pinctrl 0 48 16>; - }; - - gpioe: gpio@40021000 { - gpio-ranges = <&pinctrl 0 64 16>; - }; - - gpiof: gpio@40021400 { - gpio-ranges = <&pinctrl 0 80 16>; - }; - - gpiog: gpio@40021800 { - gpio-ranges = <&pinctrl 0 96 16>; - }; - - gpioh: gpio@40021c00 { - gpio-ranges = <&pinctrl 0 112 16>; - }; - - gpioi: gpio@40022000 { - gpio-ranges = <&pinctrl 0 128 16>; - }; - - gpioj: gpio@40022400 { - gpio-ranges = <&pinctrl 0 144 6>, - <&pinctrl 12 156 4>; - }; - - gpiok: gpio@40022800 { - gpio-ranges = <&pinctrl 3 163 5>; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/stm32f469.dtsi b/sys/gnu/dts/arm/stm32f469.dtsi deleted file mode 100644 index be002e8a78a..00000000000 --- a/sys/gnu/dts/arm/stm32f469.dtsi +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ -/* Copyright (C) STMicroelectronics 2017 - All Rights Reserved */ - -#include "stm32f429.dtsi" - -/ { - soc { - dsi: dsi@40016c00 { - compatible = "st,stm32-dsi"; - reg = <0x40016c00 0x800>; - resets = <&rcc STM32F4_APB2_RESET(DSI)>; - reset-names = "apb"; - clocks = <&rcc 1 CLK_F469_DSI>, <&clk_hse>; - clock-names = "pclk", "ref"; - status = "disabled"; - }; - }; -}; diff --git a/sys/gnu/dts/arm/stm32f7-pinctrl.dtsi b/sys/gnu/dts/arm/stm32f7-pinctrl.dtsi deleted file mode 100644 index fe4cfda72a4..00000000000 --- a/sys/gnu/dts/arm/stm32f7-pinctrl.dtsi +++ /dev/null @@ -1,289 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (C) STMicroelectronics 2017 - All Rights Reserved - * Author: Alexandre Torgue for STMicroelectronics. - */ - -#include -#include - -/ { - soc { - pinctrl: pin-controller { - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x40020000 0x3000>; - interrupt-parent = <&exti>; - st,syscfg = <&syscfg 0x8>; - pins-are-numbered; - - gpioa: gpio@40020000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x0 0x400>; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOA)>; - st,bank-name = "GPIOA"; - }; - - gpiob: gpio@40020400 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x400 0x400>; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOB)>; - st,bank-name = "GPIOB"; - }; - - gpioc: gpio@40020800 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x800 0x400>; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOC)>; - st,bank-name = "GPIOC"; - }; - - gpiod: gpio@40020c00 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0xc00 0x400>; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOD)>; - st,bank-name = "GPIOD"; - }; - - gpioe: gpio@40021000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1000 0x400>; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOE)>; - st,bank-name = "GPIOE"; - }; - - gpiof: gpio@40021400 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1400 0x400>; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOF)>; - st,bank-name = "GPIOF"; - }; - - gpiog: gpio@40021800 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1800 0x400>; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOG)>; - st,bank-name = "GPIOG"; - }; - - gpioh: gpio@40021c00 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1c00 0x400>; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOH)>; - st,bank-name = "GPIOH"; - }; - - gpioi: gpio@40022000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x2000 0x400>; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOI)>; - st,bank-name = "GPIOI"; - }; - - gpioj: gpio@40022400 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x2400 0x400>; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOJ)>; - st,bank-name = "GPIOJ"; - }; - - gpiok: gpio@40022800 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x2800 0x400>; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOK)>; - st,bank-name = "GPIOK"; - }; - - cec_pins_a: cec-0 { - pins { - pinmux = ; /* HDMI CEC */ - slew-rate = <0>; - drive-open-drain; - bias-disable; - }; - }; - - usart1_pins_a: usart1-0 { - pins1 { - pinmux = ; /* USART1_TX */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = ; /* USART1_RX */ - bias-disable; - }; - }; - - usart1_pins_b: usart1-1 { - pins1 { - pinmux = ; /* USART1_TX */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = ; /* USART1_RX */ - bias-disable; - }; - }; - - i2c1_pins_b: i2c1-0 { - pins { - pinmux = , /* I2C1 SDA */ - ; /* I2C1 SCL */ - bias-disable; - drive-open-drain; - slew-rate = <0>; - }; - }; - - usbotg_hs_pins_a: usbotg-hs-0 { - pins { - pinmux = , /* OTG_HS_ULPI_NXT */ - , /* OTG_HS_ULPI_DIR */ - , /* OTG_HS_ULPI_STP */ - , /* OTG_HS_ULPI_CK */ - , /* OTG_HS_ULPI_D0 */ - , /* OTG_HS_ULPI_D1 */ - , /* OTG_HS_ULPI_D2 */ - , /* OTG_HS_ULPI_D3 */ - , /* OTG_HS_ULPI_D4 */ - , /* OTG_HS_ULPI_D5 */ - , /* OTG_HS_ULPI_D6 */ - ; /* OTG_HS_ULPI_D7 */ - bias-disable; - drive-push-pull; - slew-rate = <2>; - }; - }; - - usbotg_hs_pins_b: usbotg-hs-1 { - pins { - pinmux = , /* OTG_HS_ULPI_NXT */ - , /* OTG_HS_ULPI_DIR */ - , /* OTG_HS_ULPI_STP */ - , /* OTG_HS_ULPI_CK */ - , /* OTG_HS_ULPI_D0 */ - , /* OTG_HS_ULPI_D1 */ - , /* OTG_HS_ULPI_D2 */ - , /* OTG_HS_ULPI_D3 */ - , /* OTG_HS_ULPI_D4 */ - , /* OTG_HS_ULPI_D5 */ - , /* OTG_HS_ULPI_D6 */ - ; /* OTG_HS_ULPI_D7 */ - bias-disable; - drive-push-pull; - slew-rate = <2>; - }; - }; - - usbotg_fs_pins_a: usbotg-fs-0 { - pins { - pinmux = , /* OTG_FS_ID */ - , /* OTG_FS_DM */ - ; /* OTG_FS_DP */ - bias-disable; - drive-push-pull; - slew-rate = <2>; - }; - }; - - sdio_pins_a: sdio-pins-a-0 { - pins { - pinmux = , /* SDMMC1 D0 */ - , /* SDMMC1 D1 */ - , /* SDMMC1 D2 */ - , /* SDMMC1 D3 */ - , /* SDMMC1 CLK */ - ; /* SDMMC1 CMD */ - drive-push-pull; - slew-rate = <2>; - }; - }; - - sdio_pins_od_a: sdio-pins-od-a-0 { - pins1 { - pinmux = , /* SDMMC1 D0 */ - , /* SDMMC1 D1 */ - , /* SDMMC1 D2 */ - , /* SDMMC1 D3 */ - ; /* SDMMC1 CLK */ - drive-push-pull; - slew-rate = <2>; - }; - - pins2 { - pinmux = ; /* SDMMC1 CMD */ - drive-open-drain; - slew-rate = <2>; - }; - }; - - sdio_pins_b: sdio-pins-b-0 { - pins { - pinmux = , /* SDMMC2 D0 */ - , /* SDMMC2 D1 */ - , /* SDMMC2 D2 */ - , /* SDMMC2 D3 */ - , /* SDMMC2 CLK */ - ; /* SDMMC2 CMD */ - drive-push-pull; - slew-rate = <2>; - }; - }; - - sdio_pins_od_b: sdio-pins-od-b-0 { - pins1 { - pinmux = , /* SDMMC2 D0 */ - , /* SDMMC2 D1 */ - , /* SDMMC2 D2 */ - , /* SDMMC2 D3 */ - ; /* SDMMC2 CLK */ - drive-push-pull; - slew-rate = <2>; - }; - - pins2 { - pinmux = ; /* SDMMC2 CMD */ - drive-open-drain; - slew-rate = <2>; - }; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/stm32f746-disco.dts b/sys/gnu/dts/arm/stm32f746-disco.dts deleted file mode 100644 index 569d23cc61e..00000000000 --- a/sys/gnu/dts/arm/stm32f746-disco.dts +++ /dev/null @@ -1,132 +0,0 @@ -/* - * Copyright 2017 - Vikas MANOCHA - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "stm32f746.dtsi" -#include "stm32f746-pinctrl.dtsi" -#include -#include - -/ { - model = "STMicroelectronics STM32F746-DISCO board"; - compatible = "st,stm32f746-disco", "st,stm32f746"; - - chosen { - bootargs = "root=/dev/ram"; - stdout-path = "serial0:115200n8"; - }; - - memory@c0000000 { - device_type = "memory"; - reg = <0xC0000000 0x800000>; - }; - - aliases { - serial0 = &usart1; - }; - - usbotg_hs_phy: usb-phy { - #phy-cells = <0>; - compatible = "usb-nop-xceiv"; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHSULPI)>; - clock-names = "main_clk"; - }; - - /* This turns on vbus for otg fs for host mode (dwc2) */ - vcc5v_otg_fs: vcc5v-otg-fs-regulator { - compatible = "regulator-fixed"; - gpio = <&gpiod 5 0>; - regulator-name = "vcc5_host1"; - regulator-always-on; - }; - - mmc_vcard: mmc_vcard { - compatible = "regulator-fixed"; - regulator-name = "mmc_vcard"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&clk_hse { - clock-frequency = <25000000>; -}; - -&i2c1 { - pinctrl-0 = <&i2c1_pins_b>; - pinctrl-names = "default"; - i2c-scl-rising-time-ns = <185>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; -}; - -&sdio1 { - status = "okay"; - vmmc-supply = <&mmc_vcard>; - cd-gpios = <&gpioc 13 GPIO_ACTIVE_LOW>; - pinctrl-names = "default", "opendrain"; - pinctrl-0 = <&sdio_pins_a>; - pinctrl-1 = <&sdio_pins_od_a>; - bus-width = <4>; -}; - -&usart1 { - pinctrl-0 = <&usart1_pins_b>; - pinctrl-names = "default"; - status = "okay"; -}; - -&usbotg_fs { - dr_mode = "host"; - pinctrl-0 = <&usbotg_fs_pins_a>; - pinctrl-names = "default"; - status = "okay"; -}; - -&usbotg_hs { - dr_mode = "host"; - phys = <&usbotg_hs_phy>; - phy-names = "usb2-phy"; - pinctrl-0 = <&usbotg_hs_pins_b>; - pinctrl-names = "default"; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/stm32f746-pinctrl.dtsi b/sys/gnu/dts/arm/stm32f746-pinctrl.dtsi deleted file mode 100644 index fcfd2ac7239..00000000000 --- a/sys/gnu/dts/arm/stm32f746-pinctrl.dtsi +++ /dev/null @@ -1,11 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (C) STMicroelectronics 2017 - All Rights Reserved - * Author: Alexandre Torgue for STMicroelectronics. - */ - -#include "stm32f7-pinctrl.dtsi" - -&pinctrl{ - compatible = "st,stm32f746-pinctrl"; -}; diff --git a/sys/gnu/dts/arm/stm32f746.dtsi b/sys/gnu/dts/arm/stm32f746.dtsi deleted file mode 100644 index 93c06379678..00000000000 --- a/sys/gnu/dts/arm/stm32f746.dtsi +++ /dev/null @@ -1,648 +0,0 @@ -/* - * Copyright 2015 - Maxime Coquelin - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "armv7-m.dtsi" -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - - clocks { - clk_hse: clk-hse { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - clk-lse { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - clk-lsi { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32000>; - }; - - clk_i2s_ckin: clk-i2s-ckin { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <48000000>; - }; - }; - - soc { - timer2: timer@40000000 { - compatible = "st,stm32-timer"; - reg = <0x40000000 0x400>; - interrupts = <28>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>; - status = "disabled"; - }; - - timers2: timers@40000000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40000000 0x400>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@1 { - compatible = "st,stm32-timer-trigger"; - reg = <1>; - status = "disabled"; - }; - }; - - timer3: timer@40000400 { - compatible = "st,stm32-timer"; - reg = <0x40000400 0x400>; - interrupts = <29>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>; - status = "disabled"; - }; - - timers3: timers@40000400 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40000400 0x400>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@2 { - compatible = "st,stm32-timer-trigger"; - reg = <2>; - status = "disabled"; - }; - }; - - timer4: timer@40000800 { - compatible = "st,stm32-timer"; - reg = <0x40000800 0x400>; - interrupts = <30>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>; - status = "disabled"; - }; - - timers4: timers@40000800 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40000800 0x400>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@3 { - compatible = "st,stm32-timer-trigger"; - reg = <3>; - status = "disabled"; - }; - }; - - timer5: timer@40000c00 { - compatible = "st,stm32-timer"; - reg = <0x40000c00 0x400>; - interrupts = <50>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>; - }; - - timers5: timers@40000c00 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40000C00 0x400>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@4 { - compatible = "st,stm32-timer-trigger"; - reg = <4>; - status = "disabled"; - }; - }; - - timer6: timer@40001000 { - compatible = "st,stm32-timer"; - reg = <0x40001000 0x400>; - interrupts = <54>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>; - status = "disabled"; - }; - - timers6: timers@40001000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40001000 0x400>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>; - clock-names = "int"; - status = "disabled"; - - timer@5 { - compatible = "st,stm32-timer-trigger"; - reg = <5>; - status = "disabled"; - }; - }; - - timer7: timer@40001400 { - compatible = "st,stm32-timer"; - reg = <0x40001400 0x400>; - interrupts = <55>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>; - status = "disabled"; - }; - - timers7: timers@40001400 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40001400 0x400>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>; - clock-names = "int"; - status = "disabled"; - - timer@6 { - compatible = "st,stm32-timer-trigger"; - reg = <6>; - status = "disabled"; - }; - }; - - timers12: timers@40001800 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40001800 0x400>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM12)>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@11 { - compatible = "st,stm32-timer-trigger"; - reg = <11>; - status = "disabled"; - }; - }; - - timers13: timers@40001c00 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40001C00 0x400>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM13)>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - }; - - timers14: timers@40002000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40002000 0x400>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM14)>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - }; - - rtc: rtc@40002800 { - compatible = "st,stm32-rtc"; - reg = <0x40002800 0x400>; - clocks = <&rcc 1 CLK_RTC>; - assigned-clocks = <&rcc 1 CLK_RTC>; - assigned-clock-parents = <&rcc 1 CLK_LSE>; - interrupt-parent = <&exti>; - interrupts = <17 1>; - interrupt-names = "alarm"; - st,syscfg = <&pwrcfg 0x00 0x100>; - status = "disabled"; - }; - - usart2: serial@40004400 { - compatible = "st,stm32f7-uart"; - reg = <0x40004400 0x400>; - interrupts = <38>; - clocks = <&rcc 1 CLK_USART2>; - status = "disabled"; - }; - - usart3: serial@40004800 { - compatible = "st,stm32f7-uart"; - reg = <0x40004800 0x400>; - interrupts = <39>; - clocks = <&rcc 1 CLK_USART3>; - status = "disabled"; - }; - - usart4: serial@40004c00 { - compatible = "st,stm32f7-uart"; - reg = <0x40004c00 0x400>; - interrupts = <52>; - clocks = <&rcc 1 CLK_UART4>; - status = "disabled"; - }; - - usart5: serial@40005000 { - compatible = "st,stm32f7-uart"; - reg = <0x40005000 0x400>; - interrupts = <53>; - clocks = <&rcc 1 CLK_UART5>; - status = "disabled"; - }; - - i2c1: i2c@40005400 { - compatible = "st,stm32f7-i2c"; - reg = <0x40005400 0x400>; - interrupts = <31>, - <32>; - resets = <&rcc STM32F7_APB1_RESET(I2C1)>; - clocks = <&rcc 1 CLK_I2C1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@40005800 { - compatible = "st,stm32f7-i2c"; - reg = <0x40005800 0x400>; - interrupts = <33>, - <34>; - resets = <&rcc STM32F7_APB1_RESET(I2C2)>; - clocks = <&rcc 1 CLK_I2C2>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c3: i2c@40005C00 { - compatible = "st,stm32f7-i2c"; - reg = <0x40005C00 0x400>; - interrupts = <72>, - <73>; - resets = <&rcc STM32F7_APB1_RESET(I2C3)>; - clocks = <&rcc 1 CLK_I2C3>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c4: i2c@40006000 { - compatible = "st,stm32f7-i2c"; - reg = <0x40006000 0x400>; - interrupts = <95>, - <96>; - resets = <&rcc STM32F7_APB1_RESET(I2C4)>; - clocks = <&rcc 1 CLK_I2C4>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - cec: cec@40006c00 { - compatible = "st,stm32-cec"; - reg = <0x40006C00 0x400>; - interrupts = <94>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(CEC)>, <&rcc 1 CLK_HDMI_CEC>; - clock-names = "cec", "hdmi-cec"; - status = "disabled"; - }; - - usart7: serial@40007800 { - compatible = "st,stm32f7-uart"; - reg = <0x40007800 0x400>; - interrupts = <82>; - clocks = <&rcc 1 CLK_UART7>; - status = "disabled"; - }; - - usart8: serial@40007c00 { - compatible = "st,stm32f7-uart"; - reg = <0x40007c00 0x400>; - interrupts = <83>; - clocks = <&rcc 1 CLK_UART8>; - status = "disabled"; - }; - - timers1: timers@40010000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40010000 0x400>; - clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM1)>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@0 { - compatible = "st,stm32-timer-trigger"; - reg = <0>; - status = "disabled"; - }; - }; - - timers8: timers@40010400 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40010400 0x400>; - clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM8)>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@7 { - compatible = "st,stm32-timer-trigger"; - reg = <7>; - status = "disabled"; - }; - }; - - usart1: serial@40011000 { - compatible = "st,stm32f7-uart"; - reg = <0x40011000 0x400>; - interrupts = <37>; - clocks = <&rcc 1 CLK_USART1>; - status = "disabled"; - }; - - usart6: serial@40011400 { - compatible = "st,stm32f7-uart"; - reg = <0x40011400 0x400>; - interrupts = <71>; - clocks = <&rcc 1 CLK_USART6>; - status = "disabled"; - }; - - sdio2: sdio2@40011c00 { - compatible = "arm,pl180", "arm,primecell"; - arm,primecell-periphid = <0x00880180>; - reg = <0x40011c00 0x400>; - clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC2)>; - clock-names = "apb_pclk"; - interrupts = <103>; - max-frequency = <48000000>; - status = "disabled"; - }; - - sdio1: sdio1@40012c00 { - compatible = "arm,pl180", "arm,primecell"; - arm,primecell-periphid = <0x00880180>; - reg = <0x40012c00 0x400>; - clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC1)>; - clock-names = "apb_pclk"; - interrupts = <49>; - max-frequency = <48000000>; - status = "disabled"; - }; - - syscfg: system-config@40013800 { - compatible = "syscon"; - reg = <0x40013800 0x400>; - }; - - exti: interrupt-controller@40013c00 { - compatible = "st,stm32-exti"; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x40013C00 0x400>; - interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>; - }; - - timers9: timers@40014000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40014000 0x400>; - clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM9)>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@8 { - compatible = "st,stm32-timer-trigger"; - reg = <8>; - status = "disabled"; - }; - }; - - timers10: timers@40014400 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40014400 0x400>; - clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM10)>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - }; - - timers11: timers@40014800 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40014800 0x400>; - clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM11)>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - }; - - pwrcfg: power-config@40007000 { - compatible = "syscon"; - reg = <0x40007000 0x400>; - }; - - crc: crc@40023000 { - compatible = "st,stm32f7-crc"; - reg = <0x40023000 0x400>; - clocks = <&rcc 0 12>; - status = "disabled"; - }; - - rcc: rcc@40023800 { - #reset-cells = <1>; - #clock-cells = <2>; - compatible = "st,stm32f746-rcc", "st,stm32-rcc"; - reg = <0x40023800 0x400>; - clocks = <&clk_hse>, <&clk_i2s_ckin>; - st,syscfg = <&pwrcfg>; - assigned-clocks = <&rcc 1 CLK_HSE_RTC>; - assigned-clock-rates = <1000000>; - }; - - dma1: dma-controller@40026000 { - compatible = "st,stm32-dma"; - reg = <0x40026000 0x400>; - interrupts = <11>, - <12>, - <13>, - <14>, - <15>, - <16>, - <17>, - <47>; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA1)>; - #dma-cells = <4>; - status = "disabled"; - }; - - dma2: dma-controller@40026400 { - compatible = "st,stm32-dma"; - reg = <0x40026400 0x400>; - interrupts = <56>, - <57>, - <58>, - <59>, - <60>, - <68>, - <69>, - <70>; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA2)>; - #dma-cells = <4>; - st,mem2mem; - status = "disabled"; - }; - - usbotg_hs: usb@40040000 { - compatible = "st,stm32f7-hsotg"; - reg = <0x40040000 0x40000>; - interrupts = <77>; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHS)>; - clock-names = "otg"; - g-rx-fifo-size = <256>; - g-np-tx-fifo-size = <32>; - g-tx-fifo-size = <128 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - usbotg_fs: usb@50000000 { - compatible = "st,stm32f4x9-fsotg"; - reg = <0x50000000 0x40000>; - interrupts = <67>; - clocks = <&rcc 0 STM32F7_AHB2_CLOCK(OTGFS)>; - clock-names = "otg"; - status = "disabled"; - }; - }; -}; - -&systick { - clocks = <&rcc 1 0>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/stm32f769-disco.dts b/sys/gnu/dts/arm/stm32f769-disco.dts deleted file mode 100644 index 1626e00bb2c..00000000000 --- a/sys/gnu/dts/arm/stm32f769-disco.dts +++ /dev/null @@ -1,155 +0,0 @@ -/* - * Copyright 2017 - Vikas MANOCHA - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "stm32f746.dtsi" -#include "stm32f769-pinctrl.dtsi" -#include -#include - -/ { - model = "STMicroelectronics STM32F769-DISCO board"; - compatible = "st,stm32f769-disco", "st,stm32f769"; - - chosen { - bootargs = "root=/dev/ram"; - stdout-path = "serial0:115200n8"; - }; - - memory@c0000000 { - device_type = "memory"; - reg = <0xC0000000 0x1000000>; - }; - - aliases { - serial0 = &usart1; - }; - - leds { - compatible = "gpio-leds"; - green { - gpios = <&gpioj 5 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - red { - gpios = <&gpioj 13 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - autorepeat; - button@0 { - label = "User"; - linux,code = ; - gpios = <&gpioa 0 GPIO_ACTIVE_HIGH>; - }; - }; - - usbotg_hs_phy: usb-phy { - #phy-cells = <0>; - compatible = "usb-nop-xceiv"; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHSULPI)>; - clock-names = "main_clk"; - }; - - mmc_vcard: mmc_vcard { - compatible = "regulator-fixed"; - regulator-name = "mmc_vcard"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&rcc { - compatible = "st,stm32f769-rcc", "st,stm32f746-rcc", "st,stm32-rcc"; -}; - -&cec { - pinctrl-0 = <&cec_pins_a>; - pinctrl-names = "default"; - status = "okay"; -}; - -&clk_hse { - clock-frequency = <25000000>; -}; - -&i2c1 { - pinctrl-0 = <&i2c1_pins_b>; - pinctrl-names = "default"; - i2c-scl-rising-time-ns = <185>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; -}; - -&rtc { - status = "okay"; -}; - -&sdio2 { - status = "okay"; - vmmc-supply = <&mmc_vcard>; - cd-gpios = <&gpioi 15 GPIO_ACTIVE_LOW>; - broken-cd; - pinctrl-names = "default", "opendrain"; - pinctrl-0 = <&sdio_pins_b>; - pinctrl-1 = <&sdio_pins_od_b>; - bus-width = <4>; -}; - -&usart1 { - pinctrl-0 = <&usart1_pins_a>; - pinctrl-names = "default"; - status = "okay"; -}; - -&usbotg_hs { - dr_mode = "otg"; - phys = <&usbotg_hs_phy>; - phy-names = "usb2-phy"; - pinctrl-0 = <&usbotg_hs_pins_a>; - pinctrl-names = "default"; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/stm32f769-pinctrl.dtsi b/sys/gnu/dts/arm/stm32f769-pinctrl.dtsi deleted file mode 100644 index 31005dd9929..00000000000 --- a/sys/gnu/dts/arm/stm32f769-pinctrl.dtsi +++ /dev/null @@ -1,11 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (C) STMicroelectronics 2017 - All Rights Reserved - * Author: Alexandre Torgue for STMicroelectronics. - */ - -#include "stm32f7-pinctrl.dtsi" - -&pinctrl{ - compatible = "st,stm32f769-pinctrl"; -}; diff --git a/sys/gnu/dts/arm/stm32h743-pinctrl.dtsi b/sys/gnu/dts/arm/stm32h743-pinctrl.dtsi deleted file mode 100644 index e44e7baa3f1..00000000000 --- a/sys/gnu/dts/arm/stm32h743-pinctrl.dtsi +++ /dev/null @@ -1,306 +0,0 @@ -/* - * Copyright 2017 - Alexandre Torgue - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include - -/ { - soc { - pin-controller { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stm32h743-pinctrl"; - ranges = <0 0x58020000 0x3000>; - interrupt-parent = <&exti>; - st,syscfg = <&syscfg 0x8>; - pins-are-numbered; - - gpioa: gpio@58020000 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x0 0x400>; - clocks = <&rcc GPIOA_CK>; - st,bank-name = "GPIOA"; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpiob: gpio@58020400 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x400 0x400>; - clocks = <&rcc GPIOB_CK>; - st,bank-name = "GPIOB"; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpioc: gpio@58020800 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x800 0x400>; - clocks = <&rcc GPIOC_CK>; - st,bank-name = "GPIOC"; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpiod: gpio@58020c00 { - gpio-controller; - #gpio-cells = <2>; - reg = <0xc00 0x400>; - clocks = <&rcc GPIOD_CK>; - st,bank-name = "GPIOD"; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpioe: gpio@58021000 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x1000 0x400>; - clocks = <&rcc GPIOE_CK>; - st,bank-name = "GPIOE"; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpiof: gpio@58021400 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x1400 0x400>; - clocks = <&rcc GPIOF_CK>; - st,bank-name = "GPIOF"; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpiog: gpio@58021800 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x1800 0x400>; - clocks = <&rcc GPIOG_CK>; - st,bank-name = "GPIOG"; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpioh: gpio@58021c00 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x1c00 0x400>; - clocks = <&rcc GPIOH_CK>; - st,bank-name = "GPIOH"; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpioi: gpio@58022000 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x2000 0x400>; - clocks = <&rcc GPIOI_CK>; - st,bank-name = "GPIOI"; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpioj: gpio@58022400 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x2400 0x400>; - clocks = <&rcc GPIOJ_CK>; - st,bank-name = "GPIOJ"; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpiok: gpio@58022800 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x2800 0x400>; - clocks = <&rcc GPIOK_CK>; - st,bank-name = "GPIOK"; - interrupt-controller; - #interrupt-cells = <2>; - }; - - i2c1_pins_a: i2c1@0 { - pins { - pinmux = , /* I2C1_SCL */ - ; /* I2C1_SDA */ - bias-disable; - drive-open-drain; - slew-rate = <0>; - }; - }; - - ethernet_rmii: rmii@0 { - pins { - pinmux = , - , - , - , - , - , - , - , - ; - slew-rate = <2>; - }; - }; - - sdmmc1_b4_pins_a: sdmmc1-b4-0 { - pins { - pinmux = , /* SDMMC1_D0 */ - , /* SDMMC1_D1 */ - , /* SDMMC1_D2 */ - , /* SDMMC1_D3 */ - , /* SDMMC1_CK */ - ; /* SDMMC1_CMD */ - slew-rate = <3>; - drive-push-pull; - bias-disable; - }; - }; - - sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 { - pins1 { - pinmux = , /* SDMMC1_D0 */ - , /* SDMMC1_D1 */ - , /* SDMMC1_D2 */ - , /* SDMMC1_D3 */ - ; /* SDMMC1_CK */ - slew-rate = <3>; - drive-push-pull; - bias-disable; - }; - pins2{ - pinmux = ; /* SDMMC1_CMD */ - slew-rate = <3>; - drive-open-drain; - bias-disable; - }; - }; - - sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 { - pins { - pinmux = , /* SDMMC1_D0 */ - , /* SDMMC1_D1 */ - , /* SDMMC1_D2 */ - , /* SDMMC1_D3 */ - , /* SDMMC1_CK */ - ; /* SDMMC1_CMD */ - }; - }; - - sdmmc1_dir_pins_a: sdmmc1-dir-0 { - pins1 { - pinmux = , /* SDMMC1_D0DIR */ - , /* SDMMC1_D123DIR */ - ; /* SDMMC1_CDIR */ - slew-rate = <3>; - drive-push-pull; - bias-pull-up; - }; - pins2{ - pinmux = ; /* SDMMC1_CKIN */ - bias-pull-up; - }; - }; - - sdmmc1_dir_sleep_pins_a: sdmmc1-dir-sleep-0 { - pins { - pinmux = , /* SDMMC1_D0DIR */ - , /* SDMMC1_D123DIR */ - , /* SDMMC1_CDIR */ - ; /* SDMMC1_CKIN */ - }; - }; - - usart1_pins: usart1@0 { - pins1 { - pinmux = ; /* USART1_TX */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = ; /* USART1_RX */ - bias-disable; - }; - }; - - usart2_pins: usart2@0 { - pins1 { - pinmux = ; /* USART2_TX */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = ; /* USART2_RX */ - bias-disable; - }; - }; - - usbotg_hs_pins_a: usbotg-hs@0 { - pins { - pinmux = , /* ULPI_NXT */ - , /* ULPI_DIR> */ - , /* ULPI_STP> */ - , /* ULPI_CK> */ - , /* ULPI_D0> */ - , /* ULPI_D1> */ - , /* ULPI_D2> */ - , /* ULPI_D3> */ - , /* ULPI_D4> */ - , /* ULPI_D5> */ - , /* ULPI_D6> */ - ; /* ULPI_D7> */ - bias-disable; - drive-push-pull; - slew-rate = <2>; - }; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/stm32h743.dtsi b/sys/gnu/dts/arm/stm32h743.dtsi deleted file mode 100644 index 05eb02e6d08..00000000000 --- a/sys/gnu/dts/arm/stm32h743.dtsi +++ /dev/null @@ -1,549 +0,0 @@ -/* - * Copyright 2017 - Alexandre Torgue - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "armv7-m.dtsi" -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - - clocks { - clk_hse: clk-hse { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - clk_lse: clk-lse { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - clk_i2s: i2s_ckin { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - }; - - soc { - timer5: timer@40000c00 { - compatible = "st,stm32-timer"; - reg = <0x40000c00 0x400>; - interrupts = <50>; - clocks = <&rcc TIM5_CK>; - }; - - lptimer1: timer@40002400 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-lptimer"; - reg = <0x40002400 0x400>; - clocks = <&rcc LPTIM1_CK>; - clock-names = "mux"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm-lp"; - #pwm-cells = <3>; - status = "disabled"; - }; - - trigger@0 { - compatible = "st,stm32-lptimer-trigger"; - reg = <0>; - status = "disabled"; - }; - - counter { - compatible = "st,stm32-lptimer-counter"; - status = "disabled"; - }; - }; - - spi2: spi@40003800 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32h7-spi"; - reg = <0x40003800 0x400>; - interrupts = <36>; - clocks = <&rcc SPI2_CK>; - status = "disabled"; - - }; - - spi3: spi@40003c00 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32h7-spi"; - reg = <0x40003c00 0x400>; - interrupts = <51>; - clocks = <&rcc SPI3_CK>; - status = "disabled"; - }; - - usart2: serial@40004400 { - compatible = "st,stm32f7-uart"; - reg = <0x40004400 0x400>; - interrupts = <38>; - status = "disabled"; - clocks = <&rcc USART2_CK>; - }; - - i2c1: i2c@40005400 { - compatible = "st,stm32f7-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x40005400 0x400>; - interrupts = <31>, - <32>; - resets = <&rcc STM32H7_APB1L_RESET(I2C1)>; - clocks = <&rcc I2C1_CK>; - status = "disabled"; - }; - - i2c2: i2c@40005800 { - compatible = "st,stm32f7-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x40005800 0x400>; - interrupts = <33>, - <34>; - resets = <&rcc STM32H7_APB1L_RESET(I2C2)>; - clocks = <&rcc I2C2_CK>; - status = "disabled"; - }; - - i2c3: i2c@40005C00 { - compatible = "st,stm32f7-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x40005C00 0x400>; - interrupts = <72>, - <73>; - resets = <&rcc STM32H7_APB1L_RESET(I2C3)>; - clocks = <&rcc I2C3_CK>; - status = "disabled"; - }; - - dac: dac@40007400 { - compatible = "st,stm32h7-dac-core"; - reg = <0x40007400 0x400>; - clocks = <&rcc DAC12_CK>; - clock-names = "pclk"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - dac1: dac@1 { - compatible = "st,stm32-dac"; - #io-channels-cells = <1>; - reg = <1>; - status = "disabled"; - }; - - dac2: dac@2 { - compatible = "st,stm32-dac"; - #io-channels-cells = <1>; - reg = <2>; - status = "disabled"; - }; - }; - - usart1: serial@40011000 { - compatible = "st,stm32f7-uart"; - reg = <0x40011000 0x400>; - interrupts = <37>; - status = "disabled"; - clocks = <&rcc USART1_CK>; - }; - - spi1: spi@40013000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32h7-spi"; - reg = <0x40013000 0x400>; - interrupts = <35>; - clocks = <&rcc SPI1_CK>; - status = "disabled"; - }; - - spi4: spi@40013400 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32h7-spi"; - reg = <0x40013400 0x400>; - interrupts = <84>; - clocks = <&rcc SPI4_CK>; - status = "disabled"; - }; - - spi5: spi@40015000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32h7-spi"; - reg = <0x40015000 0x400>; - interrupts = <85>; - clocks = <&rcc SPI5_CK>; - status = "disabled"; - }; - - dma1: dma-controller@40020000 { - compatible = "st,stm32-dma"; - reg = <0x40020000 0x400>; - interrupts = <11>, - <12>, - <13>, - <14>, - <15>, - <16>, - <17>, - <47>; - clocks = <&rcc DMA1_CK>; - #dma-cells = <4>; - st,mem2mem; - dma-requests = <8>; - status = "disabled"; - }; - - dma2: dma-controller@40020400 { - compatible = "st,stm32-dma"; - reg = <0x40020400 0x400>; - interrupts = <56>, - <57>, - <58>, - <59>, - <60>, - <68>, - <69>, - <70>; - clocks = <&rcc DMA2_CK>; - #dma-cells = <4>; - st,mem2mem; - dma-requests = <8>; - status = "disabled"; - }; - - dmamux1: dma-router@40020800 { - compatible = "st,stm32h7-dmamux"; - reg = <0x40020800 0x1c>; - #dma-cells = <3>; - dma-channels = <16>; - dma-requests = <128>; - dma-masters = <&dma1 &dma2>; - clocks = <&rcc DMA1_CK>; - }; - - adc_12: adc@40022000 { - compatible = "st,stm32h7-adc-core"; - reg = <0x40022000 0x400>; - interrupts = <18>; - clocks = <&rcc ADC12_CK>; - clock-names = "bus"; - interrupt-controller; - #interrupt-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - adc1: adc@0 { - compatible = "st,stm32h7-adc"; - #io-channel-cells = <1>; - reg = <0x0>; - interrupt-parent = <&adc_12>; - interrupts = <0>; - status = "disabled"; - }; - - adc2: adc@100 { - compatible = "st,stm32h7-adc"; - #io-channel-cells = <1>; - reg = <0x100>; - interrupt-parent = <&adc_12>; - interrupts = <1>; - status = "disabled"; - }; - }; - - usbotg_hs: usb@40040000 { - compatible = "st,stm32f7-hsotg"; - reg = <0x40040000 0x40000>; - interrupts = <77>; - clocks = <&rcc USB1OTG_CK>; - clock-names = "otg"; - g-rx-fifo-size = <256>; - g-np-tx-fifo-size = <32>; - g-tx-fifo-size = <128 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - usbotg_fs: usb@40080000 { - compatible = "st,stm32f4x9-fsotg"; - reg = <0x40080000 0x40000>; - interrupts = <101>; - clocks = <&rcc USB2OTG_CK>; - clock-names = "otg"; - status = "disabled"; - }; - - mdma1: dma-controller@52000000 { - compatible = "st,stm32h7-mdma"; - reg = <0x52000000 0x1000>; - interrupts = <122>; - clocks = <&rcc MDMA_CK>; - #dma-cells = <5>; - dma-channels = <16>; - dma-requests = <32>; - }; - - sdmmc1: sdmmc@52007000 { - compatible = "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x10153180>; - reg = <0x52007000 0x1000>; - interrupts = <49>; - interrupt-names = "cmd_irq"; - clocks = <&rcc SDMMC1_CK>; - clock-names = "apb_pclk"; - resets = <&rcc STM32H7_AHB3_RESET(SDMMC1)>; - cap-sd-highspeed; - cap-mmc-highspeed; - max-frequency = <120000000>; - }; - - exti: interrupt-controller@58000000 { - compatible = "st,stm32h7-exti"; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x58000000 0x400>; - interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <62>, <76>; - }; - - syscfg: system-config@58000400 { - compatible = "syscon"; - reg = <0x58000400 0x400>; - }; - - spi6: spi@58001400 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32h7-spi"; - reg = <0x58001400 0x400>; - interrupts = <86>; - clocks = <&rcc SPI6_CK>; - status = "disabled"; - }; - - i2c4: i2c@58001C00 { - compatible = "st,stm32f7-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x58001C00 0x400>; - interrupts = <95>, - <96>; - resets = <&rcc STM32H7_APB4_RESET(I2C4)>; - clocks = <&rcc I2C4_CK>; - status = "disabled"; - }; - - lptimer2: timer@58002400 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-lptimer"; - reg = <0x58002400 0x400>; - clocks = <&rcc LPTIM2_CK>; - clock-names = "mux"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm-lp"; - #pwm-cells = <3>; - status = "disabled"; - }; - - trigger@1 { - compatible = "st,stm32-lptimer-trigger"; - reg = <1>; - status = "disabled"; - }; - - counter { - compatible = "st,stm32-lptimer-counter"; - status = "disabled"; - }; - }; - - lptimer3: timer@58002800 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-lptimer"; - reg = <0x58002800 0x400>; - clocks = <&rcc LPTIM3_CK>; - clock-names = "mux"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm-lp"; - #pwm-cells = <3>; - status = "disabled"; - }; - - trigger@2 { - compatible = "st,stm32-lptimer-trigger"; - reg = <2>; - status = "disabled"; - }; - }; - - lptimer4: timer@58002c00 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-lptimer"; - reg = <0x58002c00 0x400>; - clocks = <&rcc LPTIM4_CK>; - clock-names = "mux"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm-lp"; - #pwm-cells = <3>; - status = "disabled"; - }; - }; - - lptimer5: timer@58003000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-lptimer"; - reg = <0x58003000 0x400>; - clocks = <&rcc LPTIM5_CK>; - clock-names = "mux"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm-lp"; - #pwm-cells = <3>; - status = "disabled"; - }; - }; - - vrefbuf: regulator@58003c00 { - compatible = "st,stm32-vrefbuf"; - reg = <0x58003C00 0x8>; - clocks = <&rcc VREF_CK>; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <2500000>; - status = "disabled"; - }; - - rtc: rtc@58004000 { - compatible = "st,stm32h7-rtc"; - reg = <0x58004000 0x400>; - clocks = <&rcc RTCAPB_CK>, <&rcc RTC_CK>; - clock-names = "pclk", "rtc_ck"; - assigned-clocks = <&rcc RTC_CK>; - assigned-clock-parents = <&rcc LSE_CK>; - interrupt-parent = <&exti>; - interrupts = <17 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "alarm"; - st,syscfg = <&pwrcfg 0x00 0x100>; - status = "disabled"; - }; - - rcc: reset-clock-controller@58024400 { - compatible = "st,stm32h743-rcc", "st,stm32-rcc"; - reg = <0x58024400 0x400>; - #clock-cells = <1>; - #reset-cells = <1>; - clocks = <&clk_hse>, <&clk_lse>, <&clk_i2s>; - st,syscfg = <&pwrcfg>; - }; - - pwrcfg: power-config@58024800 { - compatible = "syscon"; - reg = <0x58024800 0x400>; - }; - - adc_3: adc@58026000 { - compatible = "st,stm32h7-adc-core"; - reg = <0x58026000 0x400>; - interrupts = <127>; - clocks = <&rcc ADC3_CK>; - clock-names = "bus"; - interrupt-controller; - #interrupt-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - adc3: adc@0 { - compatible = "st,stm32h7-adc"; - #io-channel-cells = <1>; - reg = <0x0>; - interrupt-parent = <&adc_3>; - interrupts = <0>; - status = "disabled"; - }; - }; - - mac: ethernet@40028000 { - compatible = "st,stm32-dwmac", "snps,dwmac-4.10a"; - reg = <0x40028000 0x8000>; - reg-names = "stmmaceth"; - interrupts = <61>; - interrupt-names = "macirq"; - clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx"; - clocks = <&rcc ETH1MAC_CK>, <&rcc ETH1TX_CK>, <&rcc ETH1RX_CK>; - st,syscon = <&syscfg 0x4>; - snps,pbl = <8>; - status = "disabled"; - }; - }; -}; - -&systick { - clock-frequency = <250000000>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/stm32h743i-disco.dts b/sys/gnu/dts/arm/stm32h743i-disco.dts deleted file mode 100644 index e446d311c52..00000000000 --- a/sys/gnu/dts/arm/stm32h743i-disco.dts +++ /dev/null @@ -1,111 +0,0 @@ -/* - * Copyright 2017 - Patrice Chotard - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "stm32h743.dtsi" -#include "stm32h743-pinctrl.dtsi" - -/ { - model = "STMicroelectronics STM32H743i-Discovery board"; - compatible = "st,stm32h743i-disco", "st,stm32h743"; - - chosen { - bootargs = "root=/dev/ram"; - stdout-path = "serial0:115200n8"; - }; - - memory@d0000000 { - device_type = "memory"; - reg = <0xd0000000 0x2000000>; - }; - - aliases { - serial0 = &usart2; - }; - - v3v3: regulator-v3v3 { - compatible = "regulator-fixed"; - regulator-name = "v3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; -}; - -&clk_hse { - clock-frequency = <25000000>; -}; - -&mac { - status = "disabled"; - pinctrl-0 = <ðernet_rmii>; - pinctrl-names = "default"; - phy-mode = "rmii"; - phy-handle = <&phy0>; - - mdio0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - phy0: ethernet-phy@0 { - reg = <0>; - }; - }; -}; - -&sdmmc1 { - pinctrl-names = "default", "opendrain", "sleep"; - pinctrl-0 = <&sdmmc1_b4_pins_a>; - pinctrl-1 = <&sdmmc1_b4_od_pins_a>; - pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; - broken-cd; - st,neg-edge; - bus-width = <4>; - vmmc-supply = <&v3v3>; - status = "okay"; -}; - -&usart2 { - pinctrl-0 = <&usart2_pins>; - pinctrl-names = "default"; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/stm32h743i-eval.dts b/sys/gnu/dts/arm/stm32h743i-eval.dts deleted file mode 100644 index 8f398178f5e..00000000000 --- a/sys/gnu/dts/arm/stm32h743i-eval.dts +++ /dev/null @@ -1,160 +0,0 @@ -/* - * Copyright 2017 - Alexandre Torgue - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "stm32h743.dtsi" -#include "stm32h743-pinctrl.dtsi" - -/ { - model = "STMicroelectronics STM32H743i-EVAL board"; - compatible = "st,stm32h743i-eval", "st,stm32h743"; - - chosen { - bootargs = "root=/dev/ram"; - stdout-path = "serial0:115200n8"; - }; - - memory@d0000000 { - device_type = "memory"; - reg = <0xd0000000 0x2000000>; - }; - - aliases { - serial0 = &usart1; - }; - - vdda: regulator-vdda { - compatible = "regulator-fixed"; - regulator-name = "vdda"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - v2v9_sd: regulator-v2v9_sd { - compatible = "regulator-fixed"; - regulator-name = "v2v9_sd"; - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - regulator-always-on; - }; - - usbotg_hs_phy: usb-phy { - #phy-cells = <0>; - compatible = "usb-nop-xceiv"; - clocks = <&rcc USB1ULPI_CK>; - clock-names = "main_clk"; - }; -}; - -&adc_12 { - vdda-supply = <&vdda>; - vref-supply = <&vdda>; - status = "okay"; - adc1: adc@0 { - /* potentiometer */ - st,adc-channels = <0>; - status = "okay"; - }; -}; - -&clk_hse { - clock-frequency = <25000000>; -}; - -&i2c1 { - pinctrl-0 = <&i2c1_pins_a>; - pinctrl-names = "default"; - i2c-scl-rising-time-ns = <185>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; -}; - -&rtc { - status = "okay"; -}; - -&mac { - status = "disabled"; - pinctrl-0 = <ðernet_rmii>; - pinctrl-names = "default"; - phy-mode = "rmii"; - phy-handle = <&phy0>; - - mdio0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - phy0: ethernet-phy@0 { - reg = <0>; - }; - }; -}; - -&sdmmc1 { - pinctrl-names = "default", "opendrain", "sleep"; - pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>; - pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_a>; - pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_a>; - broken-cd; - st,sig-dir; - st,neg-edge; - st,use-ckin; - bus-width = <4>; - vmmc-supply = <&v2v9_sd>; - status = "okay"; -}; - -&usart1 { - pinctrl-0 = <&usart1_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&usbotg_hs { - pinctrl-0 = <&usbotg_hs_pins_a>; - pinctrl-names = "default"; - phys = <&usbotg_hs_phy>; - phy-names = "usb2-phy"; - dr_mode = "otg"; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/stm32mp15-pinctrl.dtsi b/sys/gnu/dts/arm/stm32mp15-pinctrl.dtsi deleted file mode 100644 index 0237d4ddaa9..00000000000 --- a/sys/gnu/dts/arm/stm32mp15-pinctrl.dtsi +++ /dev/null @@ -1,1092 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (C) STMicroelectronics 2017 - All Rights Reserved - * Author: Ludovic Barre for STMicroelectronics. - */ -#include - -&pinctrl { - adc1_in6_pins_a: adc1-in6 { - pins { - pinmux = ; - }; - }; - - adc12_ain_pins_a: adc12-ain-0 { - pins { - pinmux = , /* ADC1 in13 */ - , /* ADC1 in6 */ - , /* ADC2 in2 */ - ; /* ADC2 in6 */ - }; - }; - - adc12_usb_cc_pins_a: adc12-usb-cc-pins-0 { - pins { - pinmux = , /* ADC12 in18 */ - ; /* ADC12 in19 */ - }; - }; - - cec_pins_a: cec-0 { - pins { - pinmux = ; - bias-disable; - drive-open-drain; - slew-rate = <0>; - }; - }; - - cec_pins_sleep_a: cec-sleep-0 { - pins { - pinmux = ; /* HDMI_CEC */ - }; - }; - - cec_pins_b: cec-1 { - pins { - pinmux = ; - bias-disable; - drive-open-drain; - slew-rate = <0>; - }; - }; - - cec_pins_sleep_b: cec-sleep-1 { - pins { - pinmux = ; /* HDMI_CEC */ - }; - }; - - dac_ch1_pins_a: dac-ch1 { - pins { - pinmux = ; - }; - }; - - dac_ch2_pins_a: dac-ch2 { - pins { - pinmux = ; - }; - }; - - dcmi_pins_a: dcmi-0 { - pins { - pinmux = ,/* DCMI_HSYNC */ - ,/* DCMI_VSYNC */ - ,/* DCMI_PIXCLK */ - ,/* DCMI_D0 */ - ,/* DCMI_D1 */ - ,/* DCMI_D2 */ - ,/* DCMI_D3 */ - ,/* DCMI_D4 */ - ,/* DCMI_D5 */ - ,/* DCMI_D6 */ - ,/* DCMI_D7 */ - ,/* DCMI_D8 */ - ,/* DCMI_D9 */ - ,/* DCMI_D10 */ - ;/* DCMI_D11 */ - bias-disable; - }; - }; - - dcmi_sleep_pins_a: dcmi-sleep-0 { - pins { - pinmux = ,/* DCMI_HSYNC */ - ,/* DCMI_VSYNC */ - ,/* DCMI_PIXCLK */ - ,/* DCMI_D0 */ - ,/* DCMI_D1 */ - ,/* DCMI_D2 */ - ,/* DCMI_D3 */ - ,/* DCMI_D4 */ - ,/* DCMI_D5 */ - ,/* DCMI_D6 */ - ,/* DCMI_D7 */ - ,/* DCMI_D8 */ - ,/* DCMI_D9 */ - ,/* DCMI_D10 */ - ;/* DCMI_D11 */ - }; - }; - - ethernet0_rgmii_pins_a: rgmii-0 { - pins1 { - pinmux = , /* ETH_RGMII_CLK125 */ - , /* ETH_RGMII_GTX_CLK */ - , /* ETH_RGMII_TXD0 */ - , /* ETH_RGMII_TXD1 */ - , /* ETH_RGMII_TXD2 */ - , /* ETH_RGMII_TXD3 */ - , /* ETH_RGMII_TX_CTL */ - ; /* ETH_MDC */ - bias-disable; - drive-push-pull; - slew-rate = <2>; - }; - pins2 { - pinmux = ; /* ETH_MDIO */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins3 { - pinmux = , /* ETH_RGMII_RXD0 */ - , /* ETH_RGMII_RXD1 */ - , /* ETH_RGMII_RXD2 */ - , /* ETH_RGMII_RXD3 */ - , /* ETH_RGMII_RX_CLK */ - ; /* ETH_RGMII_RX_CTL */ - bias-disable; - }; - }; - - ethernet0_rgmii_pins_sleep_a: rgmii-sleep-0 { - pins1 { - pinmux = , /* ETH_RGMII_CLK125 */ - , /* ETH_RGMII_GTX_CLK */ - , /* ETH_RGMII_TXD0 */ - , /* ETH_RGMII_TXD1 */ - , /* ETH_RGMII_TXD2 */ - , /* ETH_RGMII_TXD3 */ - , /* ETH_RGMII_TX_CTL */ - , /* ETH_MDIO */ - , /* ETH_MDC */ - , /* ETH_RGMII_RXD0 */ - , /* ETH_RGMII_RXD1 */ - , /* ETH_RGMII_RXD2 */ - , /* ETH_RGMII_RXD3 */ - , /* ETH_RGMII_RX_CLK */ - ; /* ETH_RGMII_RX_CTL */ - }; - }; - - fmc_pins_a: fmc-0 { - pins1 { - pinmux = , /* FMC_NOE */ - , /* FMC_NWE */ - , /* FMC_A16_FMC_CLE */ - , /* FMC_A17_FMC_ALE */ - , /* FMC_D0 */ - , /* FMC_D1 */ - , /* FMC_D2 */ - , /* FMC_D3 */ - , /* FMC_D4 */ - , /* FMC_D5 */ - , /* FMC_D6 */ - , /* FMC_D7 */ - ; /* FMC_NE2_FMC_NCE */ - bias-disable; - drive-push-pull; - slew-rate = <1>; - }; - pins2 { - pinmux = ; /* FMC_NWAIT */ - bias-pull-up; - }; - }; - - fmc_sleep_pins_a: fmc-sleep-0 { - pins { - pinmux = , /* FMC_NOE */ - , /* FMC_NWE */ - , /* FMC_A16_FMC_CLE */ - , /* FMC_A17_FMC_ALE */ - , /* FMC_D0 */ - , /* FMC_D1 */ - , /* FMC_D2 */ - , /* FMC_D3 */ - , /* FMC_D4 */ - , /* FMC_D5 */ - , /* FMC_D6 */ - , /* FMC_D7 */ - , /* FMC_NWAIT */ - ; /* FMC_NE2_FMC_NCE */ - }; - }; - - i2c1_pins_a: i2c1-0 { - pins { - pinmux = , /* I2C1_SCL */ - ; /* I2C1_SDA */ - bias-disable; - drive-open-drain; - slew-rate = <0>; - }; - }; - - i2c1_pins_sleep_a: i2c1-1 { - pins { - pinmux = , /* I2C1_SCL */ - ; /* I2C1_SDA */ - }; - }; - - i2c1_pins_b: i2c1-2 { - pins { - pinmux = , /* I2C1_SCL */ - ; /* I2C1_SDA */ - bias-disable; - drive-open-drain; - slew-rate = <0>; - }; - }; - - i2c1_pins_sleep_b: i2c1-3 { - pins { - pinmux = , /* I2C1_SCL */ - ; /* I2C1_SDA */ - }; - }; - - i2c2_pins_a: i2c2-0 { - pins { - pinmux = , /* I2C2_SCL */ - ; /* I2C2_SDA */ - bias-disable; - drive-open-drain; - slew-rate = <0>; - }; - }; - - i2c2_pins_sleep_a: i2c2-1 { - pins { - pinmux = , /* I2C2_SCL */ - ; /* I2C2_SDA */ - }; - }; - - i2c2_pins_b1: i2c2-2 { - pins { - pinmux = ; /* I2C2_SDA */ - bias-disable; - drive-open-drain; - slew-rate = <0>; - }; - }; - - i2c2_pins_sleep_b1: i2c2-3 { - pins { - pinmux = ; /* I2C2_SDA */ - }; - }; - - i2c5_pins_a: i2c5-0 { - pins { - pinmux = , /* I2C5_SCL */ - ; /* I2C5_SDA */ - bias-disable; - drive-open-drain; - slew-rate = <0>; - }; - }; - - i2c5_pins_sleep_a: i2c5-1 { - pins { - pinmux = , /* I2C5_SCL */ - ; /* I2C5_SDA */ - - }; - }; - - i2s2_pins_a: i2s2-0 { - pins { - pinmux = , /* I2S2_SDO */ - , /* I2S2_WS */ - ; /* I2S2_CK */ - slew-rate = <1>; - drive-push-pull; - bias-disable; - }; - }; - - i2s2_pins_sleep_a: i2s2-1 { - pins { - pinmux = , /* I2S2_SDO */ - , /* I2S2_WS */ - ; /* I2S2_CK */ - }; - }; - - ltdc_pins_a: ltdc-a-0 { - pins { - pinmux = , /* LCD_CLK */ - , /* LCD_HSYNC */ - , /* LCD_VSYNC */ - , /* LCD_DE */ - , /* LCD_R0 */ - , /* LCD_R1 */ - , /* LCD_R2 */ - , /* LCD_R3 */ - , /* LCD_R4 */ - , /* LCD_R5 */ - , /* LCD_R6 */ - , /* LCD_R7 */ - , /* LCD_G0 */ - , /* LCD_G1 */ - , /* LCD_G2 */ - , /* LCD_G3 */ - , /* LCD_G4 */ - , /* LCD_G5 */ - , /* LCD_G6 */ - , /* LCD_G7 */ - , /* LCD_B0 */ - , /* LCD_B1 */ - , /* LCD_B2 */ - , /* LCD_B3 */ - , /* LCD_B4 */ - , /* LCD_B5 */ - , /* LCD_B6 */ - ; /* LCD_B7 */ - bias-disable; - drive-push-pull; - slew-rate = <1>; - }; - }; - - ltdc_pins_sleep_a: ltdc-a-1 { - pins { - pinmux = , /* LCD_CLK */ - , /* LCD_HSYNC */ - , /* LCD_VSYNC */ - , /* LCD_DE */ - , /* LCD_R0 */ - , /* LCD_R1 */ - , /* LCD_R2 */ - , /* LCD_R3 */ - , /* LCD_R4 */ - , /* LCD_R5 */ - , /* LCD_R6 */ - , /* LCD_R7 */ - , /* LCD_G0 */ - , /* LCD_G1 */ - , /* LCD_G2 */ - , /* LCD_G3 */ - , /* LCD_G4 */ - , /* LCD_G5 */ - , /* LCD_G6 */ - , /* LCD_G7 */ - , /* LCD_B0 */ - , /* LCD_B1 */ - , /* LCD_B2 */ - , /* LCD_B3 */ - , /* LCD_B4 */ - , /* LCD_B5 */ - , /* LCD_B6 */ - ; /* LCD_B7 */ - }; - }; - - ltdc_pins_b: ltdc-b-0 { - pins { - pinmux = , /* LCD_CLK */ - , /* LCD_HSYNC */ - , /* LCD_VSYNC */ - , /* LCD_DE */ - , /* LCD_R0 */ - , /* LCD_R1 */ - , /* LCD_R2 */ - , /* LCD_R3 */ - , /* LCD_R4 */ - , /* LCD_R5 */ - , /* LCD_R6 */ - , /* LCD_R7 */ - , /* LCD_G0 */ - , /* LCD_G1 */ - , /* LCD_G2 */ - , /* LCD_G3 */ - , /* LCD_G4 */ - , /* LCD_G5 */ - , /* LCD_G6 */ - , /* LCD_G7 */ - , /* LCD_B0 */ - , /* LCD_B1 */ - , /* LCD_B2 */ - , /* LCD_B3 */ - , /* LCD_B4 */ - , /* LCD_B5 */ - , /* LCD_B6 */ - ; /* LCD_B7 */ - bias-disable; - drive-push-pull; - slew-rate = <1>; - }; - }; - - ltdc_pins_sleep_b: ltdc-b-1 { - pins { - pinmux = , /* LCD_CLK */ - , /* LCD_HSYNC */ - , /* LCD_VSYNC */ - , /* LCD_DE */ - , /* LCD_R0 */ - , /* LCD_R1 */ - , /* LCD_R2 */ - , /* LCD_R3 */ - , /* LCD_R4 */ - , /* LCD_R5 */ - , /* LCD_R6 */ - , /* LCD_R7 */ - , /* LCD_G0 */ - , /* LCD_G1 */ - , /* LCD_G2 */ - , /* LCD_G3 */ - , /* LCD_G4 */ - , /* LCD_G5 */ - , /* LCD_G6 */ - , /* LCD_G7 */ - , /* LCD_B0 */ - , /* LCD_B1 */ - , /* LCD_B2 */ - , /* LCD_B3 */ - , /* LCD_B4 */ - , /* LCD_B5 */ - , /* LCD_B6 */ - ; /* LCD_B7 */ - }; - }; - - m_can1_pins_a: m-can1-0 { - pins1 { - pinmux = ; /* CAN1_TX */ - slew-rate = <1>; - drive-push-pull; - bias-disable; - }; - pins2 { - pinmux = ; /* CAN1_RX */ - bias-disable; - }; - }; - - m_can1_sleep_pins_a: m_can1-sleep-0 { - pins { - pinmux = , /* CAN1_TX */ - ; /* CAN1_RX */ - }; - }; - - pwm1_pins_a: pwm1-0 { - pins { - pinmux = , /* TIM1_CH1 */ - , /* TIM1_CH2 */ - ; /* TIM1_CH4 */ - bias-pull-down; - drive-push-pull; - slew-rate = <0>; - }; - }; - - pwm1_sleep_pins_a: pwm1-sleep-0 { - pins { - pinmux = , /* TIM1_CH1 */ - , /* TIM1_CH2 */ - ; /* TIM1_CH4 */ - }; - }; - - pwm2_pins_a: pwm2-0 { - pins { - pinmux = ; /* TIM2_CH4 */ - bias-pull-down; - drive-push-pull; - slew-rate = <0>; - }; - }; - - pwm2_sleep_pins_a: pwm2-sleep-0 { - pins { - pinmux = ; /* TIM2_CH4 */ - }; - }; - - pwm3_pins_a: pwm3-0 { - pins { - pinmux = ; /* TIM3_CH2 */ - bias-pull-down; - drive-push-pull; - slew-rate = <0>; - }; - }; - - pwm3_sleep_pins_a: pwm3-sleep-0 { - pins { - pinmux = ; /* TIM3_CH2 */ - }; - }; - - pwm4_pins_a: pwm4-0 { - pins { - pinmux = , /* TIM4_CH3 */ - ; /* TIM4_CH4 */ - bias-pull-down; - drive-push-pull; - slew-rate = <0>; - }; - }; - - pwm4_sleep_pins_a: pwm4-sleep-0 { - pins { - pinmux = , /* TIM4_CH3 */ - ; /* TIM4_CH4 */ - }; - }; - - pwm4_pins_b: pwm4-1 { - pins { - pinmux = ; /* TIM4_CH2 */ - bias-pull-down; - drive-push-pull; - slew-rate = <0>; - }; - }; - - pwm4_sleep_pins_b: pwm4-sleep-1 { - pins { - pinmux = ; /* TIM4_CH2 */ - }; - }; - - pwm5_pins_a: pwm5-0 { - pins { - pinmux = ; /* TIM5_CH2 */ - bias-pull-down; - drive-push-pull; - slew-rate = <0>; - }; - }; - - pwm5_sleep_pins_a: pwm5-sleep-0 { - pins { - pinmux = ; /* TIM5_CH2 */ - }; - }; - - pwm8_pins_a: pwm8-0 { - pins { - pinmux = ; /* TIM8_CH4 */ - bias-pull-down; - drive-push-pull; - slew-rate = <0>; - }; - }; - - pwm8_sleep_pins_a: pwm8-sleep-0 { - pins { - pinmux = ; /* TIM8_CH4 */ - }; - }; - - pwm12_pins_a: pwm12-0 { - pins { - pinmux = ; /* TIM12_CH1 */ - bias-pull-down; - drive-push-pull; - slew-rate = <0>; - }; - }; - - pwm12_sleep_pins_a: pwm12-sleep-0 { - pins { - pinmux = ; /* TIM12_CH1 */ - }; - }; - - qspi_clk_pins_a: qspi-clk-0 { - pins { - pinmux = ; /* QSPI_CLK */ - bias-disable; - drive-push-pull; - slew-rate = <3>; - }; - }; - - qspi_clk_sleep_pins_a: qspi-clk-sleep-0 { - pins { - pinmux = ; /* QSPI_CLK */ - }; - }; - - qspi_bk1_pins_a: qspi-bk1-0 { - pins1 { - pinmux = , /* QSPI_BK1_IO0 */ - , /* QSPI_BK1_IO1 */ - , /* QSPI_BK1_IO2 */ - ; /* QSPI_BK1_IO3 */ - bias-disable; - drive-push-pull; - slew-rate = <1>; - }; - pins2 { - pinmux = ; /* QSPI_BK1_NCS */ - bias-pull-up; - drive-push-pull; - slew-rate = <1>; - }; - }; - - qspi_bk1_sleep_pins_a: qspi-bk1-sleep-0 { - pins { - pinmux = , /* QSPI_BK1_IO0 */ - , /* QSPI_BK1_IO1 */ - , /* QSPI_BK1_IO2 */ - , /* QSPI_BK1_IO3 */ - ; /* QSPI_BK1_NCS */ - }; - }; - - qspi_bk2_pins_a: qspi-bk2-0 { - pins1 { - pinmux = , /* QSPI_BK2_IO0 */ - , /* QSPI_BK2_IO1 */ - , /* QSPI_BK2_IO2 */ - ; /* QSPI_BK2_IO3 */ - bias-disable; - drive-push-pull; - slew-rate = <1>; - }; - pins2 { - pinmux = ; /* QSPI_BK2_NCS */ - bias-pull-up; - drive-push-pull; - slew-rate = <1>; - }; - }; - - qspi_bk2_sleep_pins_a: qspi-bk2-sleep-0 { - pins { - pinmux = , /* QSPI_BK2_IO0 */ - , /* QSPI_BK2_IO1 */ - , /* QSPI_BK2_IO2 */ - , /* QSPI_BK2_IO3 */ - ; /* QSPI_BK2_NCS */ - }; - }; - - sai2a_pins_a: sai2a-0 { - pins { - pinmux = , /* SAI2_SCK_A */ - , /* SAI2_SD_A */ - , /* SAI2_FS_A */ - ; /* SAI2_MCLK_A */ - slew-rate = <0>; - drive-push-pull; - bias-disable; - }; - }; - - sai2a_sleep_pins_a: sai2a-1 { - pins { - pinmux = , /* SAI2_SCK_A */ - , /* SAI2_SD_A */ - , /* SAI2_FS_A */ - ; /* SAI2_MCLK_A */ - }; - }; - - sai2b_pins_a: sai2b-0 { - pins1 { - pinmux = , /* SAI2_SCK_B */ - , /* SAI2_FS_B */ - ; /* SAI2_MCLK_B */ - slew-rate = <0>; - drive-push-pull; - bias-disable; - }; - pins2 { - pinmux = ; /* SAI2_SD_B */ - bias-disable; - }; - }; - - sai2b_sleep_pins_a: sai2b-1 { - pins { - pinmux = , /* SAI2_SD_B */ - , /* SAI2_SCK_B */ - , /* SAI2_FS_B */ - ; /* SAI2_MCLK_B */ - }; - }; - - sai2b_pins_b: sai2b-2 { - pins { - pinmux = ; /* SAI2_SD_B */ - bias-disable; - }; - }; - - sai2b_sleep_pins_b: sai2b-3 { - pins { - pinmux = ; /* SAI2_SD_B */ - }; - }; - - sai4a_pins_a: sai4a-0 { - pins { - pinmux = ; /* SAI4_SD_A */ - slew-rate = <0>; - drive-push-pull; - bias-disable; - }; - }; - - sai4a_sleep_pins_a: sai4a-1 { - pins { - pinmux = ; /* SAI4_SD_A */ - }; - }; - - sdmmc1_b4_pins_a: sdmmc1-b4-0 { - pins1 { - pinmux = , /* SDMMC1_D0 */ - , /* SDMMC1_D1 */ - , /* SDMMC1_D2 */ - , /* SDMMC1_D3 */ - ; /* SDMMC1_CMD */ - slew-rate = <1>; - drive-push-pull; - bias-disable; - }; - pins2 { - pinmux = ; /* SDMMC1_CK */ - slew-rate = <2>; - drive-push-pull; - bias-disable; - }; - }; - - sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 { - pins1 { - pinmux = , /* SDMMC1_D0 */ - , /* SDMMC1_D1 */ - , /* SDMMC1_D2 */ - ; /* SDMMC1_D3 */ - slew-rate = <1>; - drive-push-pull; - bias-disable; - }; - pins2 { - pinmux = ; /* SDMMC1_CK */ - slew-rate = <2>; - drive-push-pull; - bias-disable; - }; - pins3 { - pinmux = ; /* SDMMC1_CMD */ - slew-rate = <1>; - drive-open-drain; - bias-disable; - }; - }; - - sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 { - pins { - pinmux = , /* SDMMC1_D0 */ - , /* SDMMC1_D1 */ - , /* SDMMC1_D2 */ - , /* SDMMC1_D3 */ - , /* SDMMC1_CK */ - ; /* SDMMC1_CMD */ - }; - }; - - sdmmc1_dir_pins_a: sdmmc1-dir-0 { - pins1 { - pinmux = , /* SDMMC1_D0DIR */ - , /* SDMMC1_D123DIR */ - ; /* SDMMC1_CDIR */ - slew-rate = <1>; - drive-push-pull; - bias-pull-up; - }; - pins2{ - pinmux = ; /* SDMMC1_CKIN */ - bias-pull-up; - }; - }; - - sdmmc1_dir_sleep_pins_a: sdmmc1-dir-sleep-0 { - pins { - pinmux = , /* SDMMC1_D0DIR */ - , /* SDMMC1_D123DIR */ - , /* SDMMC1_CDIR */ - ; /* SDMMC1_CKIN */ - }; - }; - - sdmmc2_b4_pins_a: sdmmc2-b4-0 { - pins1 { - pinmux = , /* SDMMC2_D0 */ - , /* SDMMC2_D1 */ - , /* SDMMC2_D2 */ - , /* SDMMC2_D3 */ - ; /* SDMMC2_CMD */ - slew-rate = <1>; - drive-push-pull; - bias-pull-up; - }; - pins2 { - pinmux = ; /* SDMMC2_CK */ - slew-rate = <2>; - drive-push-pull; - bias-pull-up; - }; - }; - - sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 { - pins1 { - pinmux = , /* SDMMC2_D0 */ - , /* SDMMC2_D1 */ - , /* SDMMC2_D2 */ - ; /* SDMMC2_D3 */ - slew-rate = <1>; - drive-push-pull; - bias-pull-up; - }; - pins2 { - pinmux = ; /* SDMMC2_CK */ - slew-rate = <2>; - drive-push-pull; - bias-pull-up; - }; - pins3 { - pinmux = ; /* SDMMC2_CMD */ - slew-rate = <1>; - drive-open-drain; - bias-pull-up; - }; - }; - - sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 { - pins { - pinmux = , /* SDMMC2_D0 */ - , /* SDMMC2_D1 */ - , /* SDMMC2_D2 */ - , /* SDMMC2_D3 */ - , /* SDMMC2_CK */ - ; /* SDMMC2_CMD */ - }; - }; - - sdmmc2_b4_pins_b: sdmmc2-b4-1 { - pins1 { - pinmux = , /* SDMMC2_D0 */ - , /* SDMMC2_D1 */ - , /* SDMMC2_D2 */ - , /* SDMMC2_D3 */ - ; /* SDMMC2_CMD */ - slew-rate = <1>; - drive-push-pull; - bias-disable; - }; - pins2 { - pinmux = ; /* SDMMC2_CK */ - slew-rate = <2>; - drive-push-pull; - bias-disable; - }; - }; - - sdmmc2_b4_od_pins_b: sdmmc2-b4-od-1 { - pins1 { - pinmux = , /* SDMMC2_D0 */ - , /* SDMMC2_D1 */ - , /* SDMMC2_D2 */ - ; /* SDMMC2_D3 */ - slew-rate = <1>; - drive-push-pull; - bias-disable; - }; - pins2 { - pinmux = ; /* SDMMC2_CK */ - slew-rate = <2>; - drive-push-pull; - bias-disable; - }; - pins3 { - pinmux = ; /* SDMMC2_CMD */ - slew-rate = <1>; - drive-open-drain; - bias-disable; - }; - }; - - sdmmc2_d47_pins_a: sdmmc2-d47-0 { - pins { - pinmux = , /* SDMMC2_D4 */ - , /* SDMMC2_D5 */ - , /* SDMMC2_D6 */ - ; /* SDMMC2_D7 */ - slew-rate = <1>; - drive-push-pull; - bias-pull-up; - }; - }; - - sdmmc2_d47_sleep_pins_a: sdmmc2-d47-sleep-0 { - pins { - pinmux = , /* SDMMC2_D4 */ - , /* SDMMC2_D5 */ - , /* SDMMC2_D6 */ - ; /* SDMMC2_D7 */ - }; - }; - - sdmmc3_b4_pins_a: sdmmc3-b4-0 { - pins1 { - pinmux = , /* SDMMC3_D0 */ - , /* SDMMC3_D1 */ - , /* SDMMC3_D2 */ - , /* SDMMC3_D3 */ - ; /* SDMMC3_CMD */ - slew-rate = <1>; - drive-push-pull; - bias-pull-up; - }; - pins2 { - pinmux = ; /* SDMMC3_CK */ - slew-rate = <2>; - drive-push-pull; - bias-pull-up; - }; - }; - - sdmmc3_b4_od_pins_a: sdmmc3-b4-od-0 { - pins1 { - pinmux = , /* SDMMC3_D0 */ - , /* SDMMC3_D1 */ - , /* SDMMC3_D2 */ - ; /* SDMMC3_D3 */ - slew-rate = <1>; - drive-push-pull; - bias-pull-up; - }; - pins2 { - pinmux = ; /* SDMMC3_CK */ - slew-rate = <2>; - drive-push-pull; - bias-pull-up; - }; - pins3 { - pinmux = ; /* SDMMC2_CMD */ - slew-rate = <1>; - drive-open-drain; - bias-pull-up; - }; - }; - - sdmmc3_b4_sleep_pins_a: sdmmc3-b4-sleep-0 { - pins { - pinmux = , /* SDMMC3_D0 */ - , /* SDMMC3_D1 */ - , /* SDMMC3_D2 */ - , /* SDMMC3_D3 */ - , /* SDMMC3_CK */ - ; /* SDMMC3_CMD */ - }; - }; - - spdifrx_pins_a: spdifrx-0 { - pins { - pinmux = ; /* SPDIF_IN1 */ - bias-disable; - }; - }; - - spdifrx_sleep_pins_a: spdifrx-1 { - pins { - pinmux = ; /* SPDIF_IN1 */ - }; - }; - - uart4_pins_a: uart4-0 { - pins1 { - pinmux = ; /* UART4_TX */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = ; /* UART4_RX */ - bias-disable; - }; - }; - - uart4_pins_b: uart4-1 { - pins1 { - pinmux = ; /* UART4_TX */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = ; /* UART4_RX */ - bias-disable; - }; - }; - - uart7_pins_a: uart7-0 { - pins1 { - pinmux = ; /* UART4_TX */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = , /* UART4_RX */ - , /* UART4_CTS */ - ; /* UART4_RTS */ - bias-disable; - }; - }; -}; - -&pinctrl_z { - i2c2_pins_b2: i2c2-0 { - pins { - pinmux = ; /* I2C2_SCL */ - bias-disable; - drive-open-drain; - slew-rate = <0>; - }; - }; - - i2c2_pins_sleep_b2: i2c2-1 { - pins { - pinmux = ; /* I2C2_SCL */ - }; - }; - - i2c4_pins_a: i2c4-0 { - pins { - pinmux = , /* I2C4_SCL */ - ; /* I2C4_SDA */ - bias-disable; - drive-open-drain; - slew-rate = <0>; - }; - }; - - i2c4_pins_sleep_a: i2c4-1 { - pins { - pinmux = , /* I2C4_SCL */ - ; /* I2C4_SDA */ - }; - }; - - spi1_pins_a: spi1-0 { - pins1 { - pinmux = , /* SPI1_SCK */ - ; /* SPI1_MOSI */ - bias-disable; - drive-push-pull; - slew-rate = <1>; - }; - - pins2 { - pinmux = ; /* SPI1_MISO */ - bias-disable; - }; - }; -}; diff --git a/sys/gnu/dts/arm/stm32mp151.dtsi b/sys/gnu/dts/arm/stm32mp151.dtsi deleted file mode 100644 index fb41d0778b0..00000000000 --- a/sys/gnu/dts/arm/stm32mp151.dtsi +++ /dev/null @@ -1,1692 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (C) STMicroelectronics 2017 - All Rights Reserved - * Author: Ludovic Barre for STMicroelectronics. - */ -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <0>; - }; - }; - - psci { - compatible = "arm,psci"; - method = "smc"; - cpu_off = <0x84000002>; - cpu_on = <0x84000003>; - }; - - intc: interrupt-controller@a0021000 { - compatible = "arm,cortex-a7-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0xa0021000 0x1000>, - <0xa0022000 0x2000>; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; - interrupt-parent = <&intc>; - }; - - clocks { - clk_hse: clk-hse { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - }; - - clk_hsi: clk-hsi { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <64000000>; - }; - - clk_lse: clk-lse { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - clk_lsi: clk-lsi { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32000>; - }; - - clk_csi: clk-csi { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <4000000>; - }; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&dts>; - - trips { - cpu_alert1: cpu-alert1 { - temperature = <85000>; - hysteresis = <0>; - type = "passive"; - }; - - cpu-crit { - temperature = <120000>; - hysteresis = <0>; - type = "critical"; - }; - }; - - cooling-maps { - }; - }; - }; - - booster: regulator-booster { - compatible = "st,stm32mp1-booster"; - st,syscfg = <&syscfg>; - status = "disabled"; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&intc>; - ranges; - - timers2: timer@40000000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40000000 0x400>; - clocks = <&rcc TIM2_K>; - clock-names = "int"; - dmas = <&dmamux1 18 0x400 0x1>, - <&dmamux1 19 0x400 0x1>, - <&dmamux1 20 0x400 0x1>, - <&dmamux1 21 0x400 0x1>, - <&dmamux1 22 0x400 0x1>; - dma-names = "ch1", "ch2", "ch3", "ch4", "up"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@1 { - compatible = "st,stm32h7-timer-trigger"; - reg = <1>; - status = "disabled"; - }; - - counter { - compatible = "st,stm32-timer-counter"; - status = "disabled"; - }; - }; - - timers3: timer@40001000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40001000 0x400>; - clocks = <&rcc TIM3_K>; - clock-names = "int"; - dmas = <&dmamux1 23 0x400 0x1>, - <&dmamux1 24 0x400 0x1>, - <&dmamux1 25 0x400 0x1>, - <&dmamux1 26 0x400 0x1>, - <&dmamux1 27 0x400 0x1>, - <&dmamux1 28 0x400 0x1>; - dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@2 { - compatible = "st,stm32h7-timer-trigger"; - reg = <2>; - status = "disabled"; - }; - - counter { - compatible = "st,stm32-timer-counter"; - status = "disabled"; - }; - }; - - timers4: timer@40002000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40002000 0x400>; - clocks = <&rcc TIM4_K>; - clock-names = "int"; - dmas = <&dmamux1 29 0x400 0x1>, - <&dmamux1 30 0x400 0x1>, - <&dmamux1 31 0x400 0x1>, - <&dmamux1 32 0x400 0x1>; - dma-names = "ch1", "ch2", "ch3", "ch4"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@3 { - compatible = "st,stm32h7-timer-trigger"; - reg = <3>; - status = "disabled"; - }; - - counter { - compatible = "st,stm32-timer-counter"; - status = "disabled"; - }; - }; - - timers5: timer@40003000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40003000 0x400>; - clocks = <&rcc TIM5_K>; - clock-names = "int"; - dmas = <&dmamux1 55 0x400 0x1>, - <&dmamux1 56 0x400 0x1>, - <&dmamux1 57 0x400 0x1>, - <&dmamux1 58 0x400 0x1>, - <&dmamux1 59 0x400 0x1>, - <&dmamux1 60 0x400 0x1>; - dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@4 { - compatible = "st,stm32h7-timer-trigger"; - reg = <4>; - status = "disabled"; - }; - - counter { - compatible = "st,stm32-timer-counter"; - status = "disabled"; - }; - }; - - timers6: timer@40004000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40004000 0x400>; - clocks = <&rcc TIM6_K>; - clock-names = "int"; - dmas = <&dmamux1 69 0x400 0x1>; - dma-names = "up"; - status = "disabled"; - - timer@5 { - compatible = "st,stm32h7-timer-trigger"; - reg = <5>; - status = "disabled"; - }; - }; - - timers7: timer@40005000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40005000 0x400>; - clocks = <&rcc TIM7_K>; - clock-names = "int"; - dmas = <&dmamux1 70 0x400 0x1>; - dma-names = "up"; - status = "disabled"; - - timer@6 { - compatible = "st,stm32h7-timer-trigger"; - reg = <6>; - status = "disabled"; - }; - }; - - timers12: timer@40006000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40006000 0x400>; - clocks = <&rcc TIM12_K>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@11 { - compatible = "st,stm32h7-timer-trigger"; - reg = <11>; - status = "disabled"; - }; - }; - - timers13: timer@40007000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40007000 0x400>; - clocks = <&rcc TIM13_K>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@12 { - compatible = "st,stm32h7-timer-trigger"; - reg = <12>; - status = "disabled"; - }; - }; - - timers14: timer@40008000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40008000 0x400>; - clocks = <&rcc TIM14_K>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@13 { - compatible = "st,stm32h7-timer-trigger"; - reg = <13>; - status = "disabled"; - }; - }; - - lptimer1: timer@40009000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-lptimer"; - reg = <0x40009000 0x400>; - clocks = <&rcc LPTIM1_K>; - clock-names = "mux"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm-lp"; - #pwm-cells = <3>; - status = "disabled"; - }; - - trigger@0 { - compatible = "st,stm32-lptimer-trigger"; - reg = <0>; - status = "disabled"; - }; - - counter { - compatible = "st,stm32-lptimer-counter"; - status = "disabled"; - }; - }; - - spi2: spi@4000b000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32h7-spi"; - reg = <0x4000b000 0x400>; - interrupts = ; - clocks = <&rcc SPI2_K>; - resets = <&rcc SPI2_R>; - dmas = <&dmamux1 39 0x400 0x05>, - <&dmamux1 40 0x400 0x05>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2s2: audio-controller@4000b000 { - compatible = "st,stm32h7-i2s"; - #sound-dai-cells = <0>; - reg = <0x4000b000 0x400>; - interrupts = ; - dmas = <&dmamux1 39 0x400 0x01>, - <&dmamux1 40 0x400 0x01>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi3: spi@4000c000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32h7-spi"; - reg = <0x4000c000 0x400>; - interrupts = ; - clocks = <&rcc SPI3_K>; - resets = <&rcc SPI3_R>; - dmas = <&dmamux1 61 0x400 0x05>, - <&dmamux1 62 0x400 0x05>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2s3: audio-controller@4000c000 { - compatible = "st,stm32h7-i2s"; - #sound-dai-cells = <0>; - reg = <0x4000c000 0x400>; - interrupts = ; - dmas = <&dmamux1 61 0x400 0x01>, - <&dmamux1 62 0x400 0x01>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spdifrx: audio-controller@4000d000 { - compatible = "st,stm32h7-spdifrx"; - #sound-dai-cells = <0>; - reg = <0x4000d000 0x400>; - clocks = <&rcc SPDIF_K>; - clock-names = "kclk"; - interrupts = ; - dmas = <&dmamux1 93 0x400 0x01>, - <&dmamux1 94 0x400 0x01>; - dma-names = "rx", "rx-ctrl"; - status = "disabled"; - }; - - usart2: serial@4000e000 { - compatible = "st,stm32h7-uart"; - reg = <0x4000e000 0x400>; - interrupts = ; - clocks = <&rcc USART2_K>; - status = "disabled"; - }; - - usart3: serial@4000f000 { - compatible = "st,stm32h7-uart"; - reg = <0x4000f000 0x400>; - interrupts = ; - clocks = <&rcc USART3_K>; - status = "disabled"; - }; - - uart4: serial@40010000 { - compatible = "st,stm32h7-uart"; - reg = <0x40010000 0x400>; - interrupts = ; - clocks = <&rcc UART4_K>; - status = "disabled"; - }; - - uart5: serial@40011000 { - compatible = "st,stm32h7-uart"; - reg = <0x40011000 0x400>; - interrupts = ; - clocks = <&rcc UART5_K>; - status = "disabled"; - }; - - i2c1: i2c@40012000 { - compatible = "st,stm32f7-i2c"; - reg = <0x40012000 0x400>; - interrupt-names = "event", "error"; - interrupts = , - ; - clocks = <&rcc I2C1_K>; - resets = <&rcc I2C1_R>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@40013000 { - compatible = "st,stm32f7-i2c"; - reg = <0x40013000 0x400>; - interrupt-names = "event", "error"; - interrupts = , - ; - clocks = <&rcc I2C2_K>; - resets = <&rcc I2C2_R>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c3: i2c@40014000 { - compatible = "st,stm32f7-i2c"; - reg = <0x40014000 0x400>; - interrupt-names = "event", "error"; - interrupts = , - ; - clocks = <&rcc I2C3_K>; - resets = <&rcc I2C3_R>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c5: i2c@40015000 { - compatible = "st,stm32f7-i2c"; - reg = <0x40015000 0x400>; - interrupt-names = "event", "error"; - interrupts = , - ; - clocks = <&rcc I2C5_K>; - resets = <&rcc I2C5_R>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - cec: cec@40016000 { - compatible = "st,stm32-cec"; - reg = <0x40016000 0x400>; - interrupts = ; - clocks = <&rcc CEC_K>, <&clk_lse>; - clock-names = "cec", "hdmi-cec"; - status = "disabled"; - }; - - dac: dac@40017000 { - compatible = "st,stm32h7-dac-core"; - reg = <0x40017000 0x400>; - clocks = <&rcc DAC12>; - clock-names = "pclk"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - dac1: dac@1 { - compatible = "st,stm32-dac"; - #io-channels-cells = <1>; - reg = <1>; - status = "disabled"; - }; - - dac2: dac@2 { - compatible = "st,stm32-dac"; - #io-channels-cells = <1>; - reg = <2>; - status = "disabled"; - }; - }; - - uart7: serial@40018000 { - compatible = "st,stm32h7-uart"; - reg = <0x40018000 0x400>; - interrupts = ; - clocks = <&rcc UART7_K>; - status = "disabled"; - }; - - uart8: serial@40019000 { - compatible = "st,stm32h7-uart"; - reg = <0x40019000 0x400>; - interrupts = ; - clocks = <&rcc UART8_K>; - status = "disabled"; - }; - - timers1: timer@44000000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x44000000 0x400>; - clocks = <&rcc TIM1_K>; - clock-names = "int"; - dmas = <&dmamux1 11 0x400 0x1>, - <&dmamux1 12 0x400 0x1>, - <&dmamux1 13 0x400 0x1>, - <&dmamux1 14 0x400 0x1>, - <&dmamux1 15 0x400 0x1>, - <&dmamux1 16 0x400 0x1>, - <&dmamux1 17 0x400 0x1>; - dma-names = "ch1", "ch2", "ch3", "ch4", - "up", "trig", "com"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@0 { - compatible = "st,stm32h7-timer-trigger"; - reg = <0>; - status = "disabled"; - }; - - counter { - compatible = "st,stm32-timer-counter"; - status = "disabled"; - }; - }; - - timers8: timer@44001000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x44001000 0x400>; - clocks = <&rcc TIM8_K>; - clock-names = "int"; - dmas = <&dmamux1 47 0x400 0x1>, - <&dmamux1 48 0x400 0x1>, - <&dmamux1 49 0x400 0x1>, - <&dmamux1 50 0x400 0x1>, - <&dmamux1 51 0x400 0x1>, - <&dmamux1 52 0x400 0x1>, - <&dmamux1 53 0x400 0x1>; - dma-names = "ch1", "ch2", "ch3", "ch4", - "up", "trig", "com"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@7 { - compatible = "st,stm32h7-timer-trigger"; - reg = <7>; - status = "disabled"; - }; - - counter { - compatible = "st,stm32-timer-counter"; - status = "disabled"; - }; - }; - - usart6: serial@44003000 { - compatible = "st,stm32h7-uart"; - reg = <0x44003000 0x400>; - interrupts = ; - clocks = <&rcc USART6_K>; - status = "disabled"; - }; - - spi1: spi@44004000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32h7-spi"; - reg = <0x44004000 0x400>; - interrupts = ; - clocks = <&rcc SPI1_K>; - resets = <&rcc SPI1_R>; - dmas = <&dmamux1 37 0x400 0x05>, - <&dmamux1 38 0x400 0x05>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2s1: audio-controller@44004000 { - compatible = "st,stm32h7-i2s"; - #sound-dai-cells = <0>; - reg = <0x44004000 0x400>; - interrupts = ; - dmas = <&dmamux1 37 0x400 0x01>, - <&dmamux1 38 0x400 0x01>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi4: spi@44005000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32h7-spi"; - reg = <0x44005000 0x400>; - interrupts = ; - clocks = <&rcc SPI4_K>; - resets = <&rcc SPI4_R>; - dmas = <&dmamux1 83 0x400 0x05>, - <&dmamux1 84 0x400 0x05>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - timers15: timer@44006000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x44006000 0x400>; - clocks = <&rcc TIM15_K>; - clock-names = "int"; - dmas = <&dmamux1 105 0x400 0x1>, - <&dmamux1 106 0x400 0x1>, - <&dmamux1 107 0x400 0x1>, - <&dmamux1 108 0x400 0x1>; - dma-names = "ch1", "up", "trig", "com"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@14 { - compatible = "st,stm32h7-timer-trigger"; - reg = <14>; - status = "disabled"; - }; - }; - - timers16: timer@44007000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x44007000 0x400>; - clocks = <&rcc TIM16_K>; - clock-names = "int"; - dmas = <&dmamux1 109 0x400 0x1>, - <&dmamux1 110 0x400 0x1>; - dma-names = "ch1", "up"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - timer@15 { - compatible = "st,stm32h7-timer-trigger"; - reg = <15>; - status = "disabled"; - }; - }; - - timers17: timer@44008000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x44008000 0x400>; - clocks = <&rcc TIM17_K>; - clock-names = "int"; - dmas = <&dmamux1 111 0x400 0x1>, - <&dmamux1 112 0x400 0x1>; - dma-names = "ch1", "up"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@16 { - compatible = "st,stm32h7-timer-trigger"; - reg = <16>; - status = "disabled"; - }; - }; - - spi5: spi@44009000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32h7-spi"; - reg = <0x44009000 0x400>; - interrupts = ; - clocks = <&rcc SPI5_K>; - resets = <&rcc SPI5_R>; - dmas = <&dmamux1 85 0x400 0x05>, - <&dmamux1 86 0x400 0x05>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - sai1: sai@4400a000 { - compatible = "st,stm32h7-sai"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x4400a000 0x400>; - reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>; - interrupts = ; - resets = <&rcc SAI1_R>; - status = "disabled"; - - sai1a: audio-controller@4400a004 { - #sound-dai-cells = <0>; - - compatible = "st,stm32-sai-sub-a"; - reg = <0x4 0x1c>; - clocks = <&rcc SAI1_K>; - clock-names = "sai_ck"; - dmas = <&dmamux1 87 0x400 0x01>; - status = "disabled"; - }; - - sai1b: audio-controller@4400a024 { - #sound-dai-cells = <0>; - compatible = "st,stm32-sai-sub-b"; - reg = <0x24 0x1c>; - clocks = <&rcc SAI1_K>; - clock-names = "sai_ck"; - dmas = <&dmamux1 88 0x400 0x01>; - status = "disabled"; - }; - }; - - sai2: sai@4400b000 { - compatible = "st,stm32h7-sai"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x4400b000 0x400>; - reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>; - interrupts = ; - resets = <&rcc SAI2_R>; - status = "disabled"; - - sai2a: audio-controller@4400b004 { - #sound-dai-cells = <0>; - compatible = "st,stm32-sai-sub-a"; - reg = <0x4 0x1c>; - clocks = <&rcc SAI2_K>; - clock-names = "sai_ck"; - dmas = <&dmamux1 89 0x400 0x01>; - status = "disabled"; - }; - - sai2b: audio-controller@4400b024 { - #sound-dai-cells = <0>; - compatible = "st,stm32-sai-sub-b"; - reg = <0x24 0x1c>; - clocks = <&rcc SAI2_K>; - clock-names = "sai_ck"; - dmas = <&dmamux1 90 0x400 0x01>; - status = "disabled"; - }; - }; - - sai3: sai@4400c000 { - compatible = "st,stm32h7-sai"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x4400c000 0x400>; - reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>; - interrupts = ; - resets = <&rcc SAI3_R>; - status = "disabled"; - - sai3a: audio-controller@4400c004 { - #sound-dai-cells = <0>; - compatible = "st,stm32-sai-sub-a"; - reg = <0x04 0x1c>; - clocks = <&rcc SAI3_K>; - clock-names = "sai_ck"; - dmas = <&dmamux1 113 0x400 0x01>; - status = "disabled"; - }; - - sai3b: audio-controller@4400c024 { - #sound-dai-cells = <0>; - compatible = "st,stm32-sai-sub-b"; - reg = <0x24 0x1c>; - clocks = <&rcc SAI3_K>; - clock-names = "sai_ck"; - dmas = <&dmamux1 114 0x400 0x01>; - status = "disabled"; - }; - }; - - dfsdm: dfsdm@4400d000 { - compatible = "st,stm32mp1-dfsdm"; - reg = <0x4400d000 0x800>; - clocks = <&rcc DFSDM_K>; - clock-names = "dfsdm"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - dfsdm0: filter@0 { - compatible = "st,stm32-dfsdm-adc"; - #io-channel-cells = <1>; - reg = <0>; - interrupts = ; - dmas = <&dmamux1 101 0x400 0x01>; - dma-names = "rx"; - status = "disabled"; - }; - - dfsdm1: filter@1 { - compatible = "st,stm32-dfsdm-adc"; - #io-channel-cells = <1>; - reg = <1>; - interrupts = ; - dmas = <&dmamux1 102 0x400 0x01>; - dma-names = "rx"; - status = "disabled"; - }; - - dfsdm2: filter@2 { - compatible = "st,stm32-dfsdm-adc"; - #io-channel-cells = <1>; - reg = <2>; - interrupts = ; - dmas = <&dmamux1 103 0x400 0x01>; - dma-names = "rx"; - status = "disabled"; - }; - - dfsdm3: filter@3 { - compatible = "st,stm32-dfsdm-adc"; - #io-channel-cells = <1>; - reg = <3>; - interrupts = ; - dmas = <&dmamux1 104 0x400 0x01>; - dma-names = "rx"; - status = "disabled"; - }; - - dfsdm4: filter@4 { - compatible = "st,stm32-dfsdm-adc"; - #io-channel-cells = <1>; - reg = <4>; - interrupts = ; - dmas = <&dmamux1 91 0x400 0x01>; - dma-names = "rx"; - status = "disabled"; - }; - - dfsdm5: filter@5 { - compatible = "st,stm32-dfsdm-adc"; - #io-channel-cells = <1>; - reg = <5>; - interrupts = ; - dmas = <&dmamux1 92 0x400 0x01>; - dma-names = "rx"; - status = "disabled"; - }; - }; - - dma1: dma-controller@48000000 { - compatible = "st,stm32-dma"; - reg = <0x48000000 0x400>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&rcc DMA1>; - #dma-cells = <4>; - st,mem2mem; - dma-requests = <8>; - }; - - dma2: dma-controller@48001000 { - compatible = "st,stm32-dma"; - reg = <0x48001000 0x400>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&rcc DMA2>; - #dma-cells = <4>; - st,mem2mem; - dma-requests = <8>; - }; - - dmamux1: dma-router@48002000 { - compatible = "st,stm32h7-dmamux"; - reg = <0x48002000 0x1c>; - #dma-cells = <3>; - dma-requests = <128>; - dma-masters = <&dma1 &dma2>; - dma-channels = <16>; - clocks = <&rcc DMAMUX>; - }; - - adc: adc@48003000 { - compatible = "st,stm32mp1-adc-core"; - reg = <0x48003000 0x400>; - interrupts = , - ; - clocks = <&rcc ADC12>, <&rcc ADC12_K>; - clock-names = "bus", "adc"; - interrupt-controller; - st,syscfg = <&syscfg>; - #interrupt-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - adc1: adc@0 { - compatible = "st,stm32mp1-adc"; - #io-channel-cells = <1>; - reg = <0x0>; - interrupt-parent = <&adc>; - interrupts = <0>; - dmas = <&dmamux1 9 0x400 0x01>; - dma-names = "rx"; - status = "disabled"; - }; - - adc2: adc@100 { - compatible = "st,stm32mp1-adc"; - #io-channel-cells = <1>; - reg = <0x100>; - interrupt-parent = <&adc>; - interrupts = <1>; - dmas = <&dmamux1 10 0x400 0x01>; - dma-names = "rx"; - status = "disabled"; - }; - }; - - sdmmc3: sdmmc@48004000 { - compatible = "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x10153180>; - reg = <0x48004000 0x400>; - interrupts = ; - interrupt-names = "cmd_irq"; - clocks = <&rcc SDMMC3_K>; - clock-names = "apb_pclk"; - resets = <&rcc SDMMC3_R>; - cap-sd-highspeed; - cap-mmc-highspeed; - max-frequency = <120000000>; - status = "disabled"; - }; - - usbotg_hs: usb-otg@49000000 { - compatible = "snps,dwc2"; - reg = <0x49000000 0x10000>; - clocks = <&rcc USBO_K>; - clock-names = "otg"; - resets = <&rcc USBO_R>; - reset-names = "dwc2"; - interrupts = ; - g-rx-fifo-size = <256>; - g-np-tx-fifo-size = <32>; - g-tx-fifo-size = <128 128 64 64 64 64 32 32>; - dr_mode = "otg"; - status = "disabled"; - }; - - ipcc: mailbox@4c001000 { - compatible = "st,stm32mp1-ipcc"; - #mbox-cells = <1>; - reg = <0x4c001000 0x400>; - st,proc-id = <0>; - interrupts-extended = - <&intc GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, - <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, - <&exti 61 1>; - interrupt-names = "rx", "tx", "wakeup"; - clocks = <&rcc IPCC>; - wakeup-source; - status = "disabled"; - }; - - dcmi: dcmi@4c006000 { - compatible = "st,stm32-dcmi"; - reg = <0x4c006000 0x400>; - interrupts = ; - resets = <&rcc CAMITF_R>; - clocks = <&rcc DCMI>; - clock-names = "mclk"; - dmas = <&dmamux1 75 0x400 0x0d>; - dma-names = "tx"; - status = "disabled"; - }; - - rcc: rcc@50000000 { - compatible = "st,stm32mp1-rcc", "syscon"; - reg = <0x50000000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - pwr_regulators: pwr@50001000 { - compatible = "st,stm32mp1,pwr-reg"; - reg = <0x50001000 0x10>; - - reg11: reg11 { - regulator-name = "reg11"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - }; - - reg18: reg18 { - regulator-name = "reg18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - usb33: usb33 { - regulator-name = "usb33"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - }; - - exti: interrupt-controller@5000d000 { - compatible = "st,stm32mp1-exti", "syscon"; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x5000d000 0x400>; - }; - - syscfg: syscon@50020000 { - compatible = "st,stm32mp157-syscfg", "syscon"; - reg = <0x50020000 0x400>; - clocks = <&rcc SYSCFG>; - }; - - lptimer2: timer@50021000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-lptimer"; - reg = <0x50021000 0x400>; - clocks = <&rcc LPTIM2_K>; - clock-names = "mux"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm-lp"; - #pwm-cells = <3>; - status = "disabled"; - }; - - trigger@1 { - compatible = "st,stm32-lptimer-trigger"; - reg = <1>; - status = "disabled"; - }; - - counter { - compatible = "st,stm32-lptimer-counter"; - status = "disabled"; - }; - }; - - lptimer3: timer@50022000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-lptimer"; - reg = <0x50022000 0x400>; - clocks = <&rcc LPTIM3_K>; - clock-names = "mux"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm-lp"; - #pwm-cells = <3>; - status = "disabled"; - }; - - trigger@2 { - compatible = "st,stm32-lptimer-trigger"; - reg = <2>; - status = "disabled"; - }; - }; - - lptimer4: timer@50023000 { - compatible = "st,stm32-lptimer"; - reg = <0x50023000 0x400>; - clocks = <&rcc LPTIM4_K>; - clock-names = "mux"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm-lp"; - #pwm-cells = <3>; - status = "disabled"; - }; - }; - - lptimer5: timer@50024000 { - compatible = "st,stm32-lptimer"; - reg = <0x50024000 0x400>; - clocks = <&rcc LPTIM5_K>; - clock-names = "mux"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm-lp"; - #pwm-cells = <3>; - status = "disabled"; - }; - }; - - vrefbuf: vrefbuf@50025000 { - compatible = "st,stm32-vrefbuf"; - reg = <0x50025000 0x8>; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <2500000>; - clocks = <&rcc VREF>; - status = "disabled"; - }; - - sai4: sai@50027000 { - compatible = "st,stm32h7-sai"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x50027000 0x400>; - reg = <0x50027000 0x4>, <0x500273f0 0x10>; - interrupts = ; - resets = <&rcc SAI4_R>; - status = "disabled"; - - sai4a: audio-controller@50027004 { - #sound-dai-cells = <0>; - compatible = "st,stm32-sai-sub-a"; - reg = <0x04 0x1c>; - clocks = <&rcc SAI4_K>; - clock-names = "sai_ck"; - dmas = <&dmamux1 99 0x400 0x01>; - status = "disabled"; - }; - - sai4b: audio-controller@50027024 { - #sound-dai-cells = <0>; - compatible = "st,stm32-sai-sub-b"; - reg = <0x24 0x1c>; - clocks = <&rcc SAI4_K>; - clock-names = "sai_ck"; - dmas = <&dmamux1 100 0x400 0x01>; - status = "disabled"; - }; - }; - - dts: thermal@50028000 { - compatible = "st,stm32-thermal"; - reg = <0x50028000 0x100>; - interrupts = ; - clocks = <&rcc TMPSENS>; - clock-names = "pclk"; - #thermal-sensor-cells = <0>; - status = "disabled"; - }; - - hash1: hash@54002000 { - compatible = "st,stm32f756-hash"; - reg = <0x54002000 0x400>; - interrupts = ; - clocks = <&rcc HASH1>; - resets = <&rcc HASH1_R>; - dmas = <&mdma1 31 0x10 0x1000A02 0x0 0x0>; - dma-names = "in"; - dma-maxburst = <2>; - status = "disabled"; - }; - - rng1: rng@54003000 { - compatible = "st,stm32-rng"; - reg = <0x54003000 0x400>; - clocks = <&rcc RNG1_K>; - resets = <&rcc RNG1_R>; - status = "disabled"; - }; - - mdma1: dma-controller@58000000 { - compatible = "st,stm32h7-mdma"; - reg = <0x58000000 0x1000>; - interrupts = ; - clocks = <&rcc MDMA>; - #dma-cells = <5>; - dma-channels = <32>; - dma-requests = <48>; - }; - - fmc: nand-controller@58002000 { - compatible = "st,stm32mp15-fmc2"; - reg = <0x58002000 0x1000>, - <0x80000000 0x1000>, - <0x88010000 0x1000>, - <0x88020000 0x1000>, - <0x81000000 0x1000>, - <0x89010000 0x1000>, - <0x89020000 0x1000>; - interrupts = ; - dmas = <&mdma1 20 0x10 0x12000a02 0x0 0x0>, - <&mdma1 20 0x10 0x12000a08 0x0 0x0>, - <&mdma1 21 0x10 0x12000a0a 0x0 0x0>; - dma-names = "tx", "rx", "ecc"; - clocks = <&rcc FMC_K>; - resets = <&rcc FMC_R>; - status = "disabled"; - }; - - qspi: spi@58003000 { - compatible = "st,stm32f469-qspi"; - reg = <0x58003000 0x1000>, <0x70000000 0x10000000>; - reg-names = "qspi", "qspi_mm"; - interrupts = ; - dmas = <&mdma1 22 0x10 0x100002 0x0 0x0>, - <&mdma1 22 0x10 0x100008 0x0 0x0>; - dma-names = "tx", "rx"; - clocks = <&rcc QSPI_K>; - resets = <&rcc QSPI_R>; - status = "disabled"; - }; - - sdmmc1: sdmmc@58005000 { - compatible = "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x10153180>; - reg = <0x58005000 0x1000>; - interrupts = ; - interrupt-names = "cmd_irq"; - clocks = <&rcc SDMMC1_K>; - clock-names = "apb_pclk"; - resets = <&rcc SDMMC1_R>; - cap-sd-highspeed; - cap-mmc-highspeed; - max-frequency = <120000000>; - status = "disabled"; - }; - - sdmmc2: sdmmc@58007000 { - compatible = "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x10153180>; - reg = <0x58007000 0x1000>; - interrupts = ; - interrupt-names = "cmd_irq"; - clocks = <&rcc SDMMC2_K>; - clock-names = "apb_pclk"; - resets = <&rcc SDMMC2_R>; - cap-sd-highspeed; - cap-mmc-highspeed; - max-frequency = <120000000>; - status = "disabled"; - }; - - crc1: crc@58009000 { - compatible = "st,stm32f7-crc"; - reg = <0x58009000 0x400>; - clocks = <&rcc CRC1>; - status = "disabled"; - }; - - stmmac_axi_config_0: stmmac-axi-config { - snps,wr_osr_lmt = <0x7>; - snps,rd_osr_lmt = <0x7>; - snps,blen = <0 0 0 0 16 8 4>; - }; - - ethernet0: ethernet@5800a000 { - compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a"; - reg = <0x5800a000 0x2000>; - reg-names = "stmmaceth"; - interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "macirq"; - clock-names = "stmmaceth", - "mac-clk-tx", - "mac-clk-rx", - "ethstp"; - clocks = <&rcc ETHMAC>, - <&rcc ETHTX>, - <&rcc ETHRX>, - <&rcc ETHSTP>; - st,syscon = <&syscfg 0x4>; - snps,mixed-burst; - snps,pbl = <2>; - snps,en-tx-lpi-clockgating; - snps,axi-config = <&stmmac_axi_config_0>; - snps,tso; - status = "disabled"; - }; - - usbh_ohci: usbh-ohci@5800c000 { - compatible = "generic-ohci"; - reg = <0x5800c000 0x1000>; - clocks = <&rcc USBH>; - resets = <&rcc USBH_R>; - interrupts = ; - status = "disabled"; - }; - - usbh_ehci: usbh-ehci@5800d000 { - compatible = "generic-ehci"; - reg = <0x5800d000 0x1000>; - clocks = <&rcc USBH>; - resets = <&rcc USBH_R>; - interrupts = ; - companion = <&usbh_ohci>; - status = "disabled"; - }; - - ltdc: display-controller@5a001000 { - compatible = "st,stm32-ltdc"; - reg = <0x5a001000 0x400>; - interrupts = , - ; - clocks = <&rcc LTDC_PX>; - clock-names = "lcd"; - resets = <&rcc LTDC_R>; - status = "disabled"; - }; - - iwdg2: watchdog@5a002000 { - compatible = "st,stm32mp1-iwdg"; - reg = <0x5a002000 0x400>; - clocks = <&rcc IWDG2>, <&rcc CK_LSI>; - clock-names = "pclk", "lsi"; - status = "disabled"; - }; - - usbphyc: usbphyc@5a006000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32mp1-usbphyc"; - reg = <0x5a006000 0x1000>; - clocks = <&rcc USBPHY_K>; - resets = <&rcc USBPHY_R>; - status = "disabled"; - - usbphyc_port0: usb-phy@0 { - #phy-cells = <0>; - reg = <0>; - }; - - usbphyc_port1: usb-phy@1 { - #phy-cells = <1>; - reg = <1>; - }; - }; - - usart1: serial@5c000000 { - compatible = "st,stm32h7-uart"; - reg = <0x5c000000 0x400>; - interrupts = ; - clocks = <&rcc USART1_K>; - status = "disabled"; - }; - - spi6: spi@5c001000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32h7-spi"; - reg = <0x5c001000 0x400>; - interrupts = ; - clocks = <&rcc SPI6_K>; - resets = <&rcc SPI6_R>; - dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>, - <&mdma1 35 0x0 0x40002 0x0 0x0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c4: i2c@5c002000 { - compatible = "st,stm32f7-i2c"; - reg = <0x5c002000 0x400>; - interrupt-names = "event", "error"; - interrupts = , - ; - clocks = <&rcc I2C4_K>; - resets = <&rcc I2C4_R>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - rtc: rtc@5c004000 { - compatible = "st,stm32mp1-rtc"; - reg = <0x5c004000 0x400>; - clocks = <&rcc RTCAPB>, <&rcc RTC>; - clock-names = "pclk", "rtc_ck"; - interrupts = ; - status = "disabled"; - }; - - bsec: efuse@5c005000 { - compatible = "st,stm32mp15-bsec"; - reg = <0x5c005000 0x400>; - #address-cells = <1>; - #size-cells = <1>; - ts_cal1: calib@5c { - reg = <0x5c 0x2>; - }; - ts_cal2: calib@5e { - reg = <0x5e 0x2>; - }; - }; - - i2c6: i2c@5c009000 { - compatible = "st,stm32f7-i2c"; - reg = <0x5c009000 0x400>; - interrupt-names = "event", "error"; - interrupts = , - ; - clocks = <&rcc I2C6_K>; - resets = <&rcc I2C6_R>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - /* - * Break node order to solve dependency probe issue between - * pinctrl and exti. - */ - pinctrl: pin-controller@50002000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stm32mp157-pinctrl"; - ranges = <0 0x50002000 0xa400>; - interrupt-parent = <&exti>; - st,syscfg = <&exti 0x60 0xff>; - pins-are-numbered; - - gpioa: gpio@50002000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x0 0x400>; - clocks = <&rcc GPIOA>; - st,bank-name = "GPIOA"; - status = "disabled"; - }; - - gpiob: gpio@50003000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1000 0x400>; - clocks = <&rcc GPIOB>; - st,bank-name = "GPIOB"; - status = "disabled"; - }; - - gpioc: gpio@50004000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x2000 0x400>; - clocks = <&rcc GPIOC>; - st,bank-name = "GPIOC"; - status = "disabled"; - }; - - gpiod: gpio@50005000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x3000 0x400>; - clocks = <&rcc GPIOD>; - st,bank-name = "GPIOD"; - status = "disabled"; - }; - - gpioe: gpio@50006000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x4000 0x400>; - clocks = <&rcc GPIOE>; - st,bank-name = "GPIOE"; - status = "disabled"; - }; - - gpiof: gpio@50007000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x5000 0x400>; - clocks = <&rcc GPIOF>; - st,bank-name = "GPIOF"; - status = "disabled"; - }; - - gpiog: gpio@50008000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x6000 0x400>; - clocks = <&rcc GPIOG>; - st,bank-name = "GPIOG"; - status = "disabled"; - }; - - gpioh: gpio@50009000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x7000 0x400>; - clocks = <&rcc GPIOH>; - st,bank-name = "GPIOH"; - status = "disabled"; - }; - - gpioi: gpio@5000a000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x8000 0x400>; - clocks = <&rcc GPIOI>; - st,bank-name = "GPIOI"; - status = "disabled"; - }; - - gpioj: gpio@5000b000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x9000 0x400>; - clocks = <&rcc GPIOJ>; - st,bank-name = "GPIOJ"; - status = "disabled"; - }; - - gpiok: gpio@5000c000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0xa000 0x400>; - clocks = <&rcc GPIOK>; - st,bank-name = "GPIOK"; - status = "disabled"; - }; - }; - - pinctrl_z: pin-controller-z@54004000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stm32mp157-z-pinctrl"; - ranges = <0 0x54004000 0x400>; - pins-are-numbered; - interrupt-parent = <&exti>; - st,syscfg = <&exti 0x60 0xff>; - - gpioz: gpio@54004000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0 0x400>; - clocks = <&rcc GPIOZ>; - st,bank-name = "GPIOZ"; - st,bank-ioport = <11>; - status = "disabled"; - }; - }; - }; - - mlahb: ahb { - compatible = "st,mlahb", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - dma-ranges = <0x00000000 0x38000000 0x10000>, - <0x10000000 0x10000000 0x60000>, - <0x30000000 0x30000000 0x60000>; - - m4_rproc: m4@10000000 { - compatible = "st,stm32mp1-m4"; - reg = <0x10000000 0x40000>, - <0x30000000 0x40000>, - <0x38000000 0x10000>; - resets = <&rcc MCU_R>; - st,syscfg-holdboot = <&rcc 0x10C 0x1>; - st,syscfg-tz = <&rcc 0x000 0x1>; - status = "disabled"; - }; - }; -}; diff --git a/sys/gnu/dts/arm/stm32mp153.dtsi b/sys/gnu/dts/arm/stm32mp153.dtsi deleted file mode 100644 index 2d759fc6015..00000000000 --- a/sys/gnu/dts/arm/stm32mp153.dtsi +++ /dev/null @@ -1,45 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (C) STMicroelectronics 2019 - All Rights Reserved - * Author: Alexandre Torgue for STMicroelectronics. - */ - -#include "stm32mp151.dtsi" - -/ { - cpus { - cpu1: cpu@1 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <1>; - }; - }; - - soc { - m_can1: can@4400e000 { - compatible = "bosch,m_can"; - reg = <0x4400e000 0x400>, <0x44011000 0x1400>; - reg-names = "m_can", "message_ram"; - interrupts = , - ; - interrupt-names = "int0", "int1"; - clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; - clock-names = "hclk", "cclk"; - bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>; - status = "disabled"; - }; - - m_can2: can@4400f000 { - compatible = "bosch,m_can"; - reg = <0x4400f000 0x400>, <0x44011000 0x2800>; - reg-names = "m_can", "message_ram"; - interrupts = , - ; - interrupt-names = "int0", "int1"; - clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; - clock-names = "hclk", "cclk"; - bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>; - status = "disabled"; - }; - }; -}; diff --git a/sys/gnu/dts/arm/stm32mp157.dtsi b/sys/gnu/dts/arm/stm32mp157.dtsi deleted file mode 100644 index 3f0a4a91cce..00000000000 --- a/sys/gnu/dts/arm/stm32mp157.dtsi +++ /dev/null @@ -1,31 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (C) STMicroelectronics 2019 - All Rights Reserved - * Author: Alexandre Torgue for STMicroelectronics. - */ - -#include "stm32mp153.dtsi" - -/ { - soc { - gpu: gpu@59000000 { - compatible = "vivante,gc"; - reg = <0x59000000 0x800>; - interrupts = ; - clocks = <&rcc GPU>, <&rcc GPU_K>; - clock-names = "bus" ,"core"; - resets = <&rcc GPU_R>; - status = "disabled"; - }; - - dsi: dsi@5a000000 { - compatible = "st,stm32-dsi"; - reg = <0x5a000000 0x800>; - clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>; - clock-names = "pclk", "ref", "px_clk"; - resets = <&rcc DSI_R>; - reset-names = "apb"; - status = "disabled"; - }; - }; -}; diff --git a/sys/gnu/dts/arm/stm32mp157a-avenger96.dts b/sys/gnu/dts/arm/stm32mp157a-avenger96.dts deleted file mode 100644 index cbfa4075907..00000000000 --- a/sys/gnu/dts/arm/stm32mp157a-avenger96.dts +++ /dev/null @@ -1,326 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) -/* - * Copyright (C) Linaro Ltd 2019 - All Rights Reserved - * Author: Manivannan Sadhasivam - */ - -/dts-v1/; - -#include "stm32mp157.dtsi" -#include "stm32mp15-pinctrl.dtsi" -#include "stm32mp15xxac-pinctrl.dtsi" -#include -#include - -/ { - model = "Arrow Electronics STM32MP157A Avenger96 board"; - compatible = "arrow,stm32mp157a-avenger96", "st,stm32mp157"; - - aliases { - ethernet0 = ðernet0; - mmc0 = &sdmmc1; - serial0 = &uart4; - serial1 = &uart7; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@c0000000 { - device_type = "memory"; - reg = <0xc0000000 0x40000000>; - }; - - led { - compatible = "gpio-leds"; - led1 { - label = "green:user1"; - gpios = <&gpioz 7 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - - led2 { - label = "green:user2"; - gpios = <&gpiof 3 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc0"; - default-state = "off"; - }; - - led3 { - label = "green:user3"; - gpios = <&gpiog 0 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc1"; - default-state = "off"; - }; - - led4 { - label = "green:user3"; - gpios = <&gpiog 1 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "none"; - default-state = "off"; - panic-indicator; - }; - - led5 { - label = "yellow:wifi"; - gpios = <&gpioz 3 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "phy0tx"; - default-state = "off"; - }; - - led6 { - label = "blue:bt"; - gpios = <&gpioz 6 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "bluetooth-power"; - default-state = "off"; - }; - }; -}; - -ðernet0 { - status = "okay"; - pinctrl-0 = <ðernet0_rgmii_pins_a>; - pinctrl-1 = <ðernet0_rgmii_pins_sleep_a>; - pinctrl-names = "default", "sleep"; - phy-mode = "rgmii"; - max-speed = <1000>; - phy-handle = <&phy0>; - - mdio0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - phy0: ethernet-phy@7 { - reg = <7>; - }; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_b>; - i2c-scl-rising-time-ns = <185>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; - /delete-property/dmas; - /delete-property/dma-names; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_b1 &i2c2_pins_b2>; - i2c-scl-rising-time-ns = <185>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; - /delete-property/dmas; - /delete-property/dma-names; -}; - -&i2c4 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_pins_a>; - i2c-scl-rising-time-ns = <185>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; - /delete-property/dmas; - /delete-property/dma-names; - - pmic: stpmic@33 { - compatible = "st,stpmic1"; - reg = <0x33>; - interrupts-extended = <&exti 55 IRQ_TYPE_EDGE_FALLING>; - interrupt-controller; - #interrupt-cells = <2>; - status = "okay"; - - st,main-control-register = <0x04>; - st,vin-control-register = <0xc0>; - st,usb-control-register = <0x30>; - - regulators { - compatible = "st,stpmic1-regulators"; - - ldo1-supply = <&v3v3>; - ldo2-supply = <&v3v3>; - ldo3-supply = <&vdd_ddr>; - ldo5-supply = <&v3v3>; - ldo6-supply = <&v3v3>; - pwr_sw1-supply = <&bst_out>; - pwr_sw2-supply = <&bst_out>; - - vddcore: buck1 { - regulator-name = "vddcore"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-initial-mode = <0>; - regulator-over-current-protection; - }; - - vdd_ddr: buck2 { - regulator-name = "vdd_ddr"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-initial-mode = <0>; - regulator-over-current-protection; - }; - - vdd: buck3 { - regulator-name = "vdd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - st,mask_reset; - regulator-initial-mode = <0>; - regulator-over-current-protection; - }; - - v3v3: buck4 { - regulator-name = "v3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-over-current-protection; - regulator-initial-mode = <0>; - }; - - vdda: ldo1 { - regulator-name = "vdda"; - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - interrupts = ; - interrupt-parent = <&pmic>; - }; - - v2v8: ldo2 { - regulator-name = "v2v8"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - interrupts = ; - interrupt-parent = <&pmic>; - }; - - vtt_ddr: ldo3 { - regulator-name = "vtt_ddr"; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <750000>; - regulator-always-on; - regulator-over-current-protection; - }; - - vdd_usb: ldo4 { - regulator-name = "vdd_usb"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - interrupts = ; - interrupt-parent = <&pmic>; - }; - - vdd_sd: ldo5 { - regulator-name = "vdd_sd"; - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - interrupts = ; - interrupt-parent = <&pmic>; - regulator-boot-on; - }; - - v1v8: ldo6 { - regulator-name = "v1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - interrupts = ; - interrupt-parent = <&pmic>; - regulator-enable-ramp-delay = <300000>; - }; - - vref_ddr: vref_ddr { - regulator-name = "vref_ddr"; - regulator-always-on; - regulator-over-current-protection; - }; - - bst_out: boost { - regulator-name = "bst_out"; - interrupts = ; - interrupt-parent = <&pmic>; - }; - - vbus_otg: pwr_sw1 { - regulator-name = "vbus_otg"; - interrupts = ; - interrupt-parent = <&pmic>; - }; - - vbus_sw: pwr_sw2 { - regulator-name = "vbus_sw"; - interrupts = ; - interrupt-parent = <&pmic>; - regulator-active-discharge = <1>; - }; - }; - - onkey { - compatible = "st,stpmic1-onkey"; - interrupts = , ; - interrupt-names = "onkey-falling", "onkey-rising"; - status = "okay"; - }; - - watchdog { - compatible = "st,stpmic1-wdt"; - status = "disabled"; - }; - }; -}; - -&iwdg2 { - timeout-sec = <32>; - status = "okay"; -}; - -&pwr_regulators { - vdd-supply = <&vdd>; - vdd_3v3_usbfs-supply = <&vdd_usb>; -}; - -&rng1 { - status = "okay"; -}; - -&rtc { - status = "okay"; -}; - -&sdmmc1 { - pinctrl-names = "default", "opendrain", "sleep"; - pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>; - pinctrl-1 = <&sdmmc1_b4_od_pins_a>; - pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; - broken-cd; - st,sig-dir; - st,neg-edge; - st,use-ckin; - bus-width = <4>; - vmmc-supply = <&vdd_sd>; - status = "okay"; -}; - -&uart4 { - /* On Low speed expansion header */ - label = "LS-UART1"; - pinctrl-names = "default"; - pinctrl-0 = <&uart4_pins_b>; - status = "okay"; -}; - -&uart7 { - /* On Low speed expansion header */ - label = "LS-UART0"; - pinctrl-names = "default"; - pinctrl-0 = <&uart7_pins_a>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/stm32mp157a-dk1.dts b/sys/gnu/dts/arm/stm32mp157a-dk1.dts deleted file mode 100644 index d03d4cd2606..00000000000 --- a/sys/gnu/dts/arm/stm32mp157a-dk1.dts +++ /dev/null @@ -1,26 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (C) STMicroelectronics 2019 - All Rights Reserved - * Author: Alexandre Torgue for STMicroelectronics. - */ - -/dts-v1/; - -#include "stm32mp157.dtsi" -#include "stm32mp15-pinctrl.dtsi" -#include "stm32mp15xxac-pinctrl.dtsi" -#include "stm32mp15xx-dkx.dtsi" - -/ { - model = "STMicroelectronics STM32MP157A-DK1 Discovery Board"; - compatible = "st,stm32mp157a-dk1", "st,stm32mp157"; - - aliases { - ethernet0 = ðernet0; - serial0 = &uart4; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; diff --git a/sys/gnu/dts/arm/stm32mp157c-dk2.dts b/sys/gnu/dts/arm/stm32mp157c-dk2.dts deleted file mode 100644 index 7985b80967c..00000000000 --- a/sys/gnu/dts/arm/stm32mp157c-dk2.dts +++ /dev/null @@ -1,94 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (C) STMicroelectronics 2019 - All Rights Reserved - * Author: Alexandre Torgue for STMicroelectronics. - */ - -/dts-v1/; - -#include "stm32mp157.dtsi" -#include "stm32mp15xc.dtsi" -#include "stm32mp15-pinctrl.dtsi" -#include "stm32mp15xxac-pinctrl.dtsi" -#include "stm32mp15xx-dkx.dtsi" - -/ { - model = "STMicroelectronics STM32MP157C-DK2 Discovery Board"; - compatible = "st,stm32mp157c-dk2", "st,stm32mp157"; - - aliases { - ethernet0 = ðernet0; - serial0 = &uart4; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&dsi { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - phy-dsi-supply = <®18>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dsi_in: endpoint { - remote-endpoint = <<dc_ep1_out>; - }; - }; - - port@1 { - reg = <1>; - dsi_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; - - panel@0 { - compatible = "orisetech,otm8009a"; - reg = <0>; - reset-gpios = <&gpioe 4 GPIO_ACTIVE_LOW>; - power-supply = <&v3v3>; - status = "okay"; - - port { - panel_in: endpoint { - remote-endpoint = <&dsi_out>; - }; - }; - }; -}; - -&i2c1 { - touchscreen@38 { - compatible = "focaltech,ft6236"; - reg = <0x38>; - interrupts = <2 2>; - interrupt-parent = <&gpiof>; - interrupt-controller; - touchscreen-size-x = <480>; - touchscreen-size-y = <800>; - status = "okay"; - }; -}; - -<dc { - status = "okay"; - - port { - #address-cells = <1>; - #size-cells = <0>; - - ltdc_ep1_out: endpoint@1 { - reg = <1>; - remote-endpoint = <&dsi_in>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/stm32mp157c-ed1.dts b/sys/gnu/dts/arm/stm32mp157c-ed1.dts deleted file mode 100644 index 1fc43251d69..00000000000 --- a/sys/gnu/dts/arm/stm32mp157c-ed1.dts +++ /dev/null @@ -1,368 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (C) STMicroelectronics 2017 - All Rights Reserved - * Author: Ludovic Barre for STMicroelectronics. - */ -/dts-v1/; - -#include "stm32mp157.dtsi" -#include "stm32mp15xc.dtsi" -#include "stm32mp15-pinctrl.dtsi" -#include "stm32mp15xxaa-pinctrl.dtsi" -#include -#include - -/ { - model = "STMicroelectronics STM32MP157C eval daughter"; - compatible = "st,stm32mp157c-ed1", "st,stm32mp157"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@c0000000 { - device_type = "memory"; - reg = <0xC0000000 0x40000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - mcuram2: mcuram2@10000000 { - compatible = "shared-dma-pool"; - reg = <0x10000000 0x40000>; - no-map; - }; - - vdev0vring0: vdev0vring0@10040000 { - compatible = "shared-dma-pool"; - reg = <0x10040000 0x1000>; - no-map; - }; - - vdev0vring1: vdev0vring1@10041000 { - compatible = "shared-dma-pool"; - reg = <0x10041000 0x1000>; - no-map; - }; - - vdev0buffer: vdev0buffer@10042000 { - compatible = "shared-dma-pool"; - reg = <0x10042000 0x4000>; - no-map; - }; - - mcuram: mcuram@30000000 { - compatible = "shared-dma-pool"; - reg = <0x30000000 0x40000>; - no-map; - }; - - retram: retram@38000000 { - compatible = "shared-dma-pool"; - reg = <0x38000000 0x10000>; - no-map; - }; - - gpu_reserved: gpu@e8000000 { - reg = <0xe8000000 0x8000000>; - no-map; - }; - }; - - aliases { - serial0 = &uart4; - }; - - sd_switch: regulator-sd_switch { - compatible = "regulator-gpio"; - regulator-name = "sd_switch"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2900000>; - regulator-type = "voltage"; - regulator-always-on; - - gpios = <&gpiof 14 GPIO_ACTIVE_HIGH>; - gpios-states = <0>; - states = <1800000 0x1>, - <2900000 0x0>; - }; -}; - -&adc { - /* ANA0, ANA1 are dedicated pins and don't need pinctrl: only in6. */ - pinctrl-0 = <&adc1_in6_pins_a>; - pinctrl-names = "default"; - vdd-supply = <&vdd>; - vdda-supply = <&vdda>; - vref-supply = <&vdda>; - status = "disabled"; - adc1: adc@0 { - st,adc-channels = <0 1 6>; - /* 16.5 ck_cycles sampling time */ - st,min-sample-time-nsecs = <400>; - status = "okay"; - }; -}; - -&dac { - pinctrl-names = "default"; - pinctrl-0 = <&dac_ch1_pins_a &dac_ch2_pins_a>; - vref-supply = <&vdda>; - status = "disabled"; - dac1: dac@1 { - status = "okay"; - }; - dac2: dac@2 { - status = "okay"; - }; -}; - -&dts { - status = "okay"; -}; - -&gpu { - contiguous-area = <&gpu_reserved>; - status = "okay"; -}; - -&i2c4 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_pins_a>; - i2c-scl-rising-time-ns = <185>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; - /* spare dmas for other usage */ - /delete-property/dmas; - /delete-property/dma-names; - - pmic: stpmic@33 { - compatible = "st,stpmic1"; - reg = <0x33>; - interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; - interrupt-controller; - #interrupt-cells = <2>; - status = "okay"; - - regulators { - compatible = "st,stpmic1-regulators"; - ldo1-supply = <&v3v3>; - ldo2-supply = <&v3v3>; - ldo3-supply = <&vdd_ddr>; - ldo5-supply = <&v3v3>; - ldo6-supply = <&v3v3>; - pwr_sw1-supply = <&bst_out>; - pwr_sw2-supply = <&bst_out>; - - vddcore: buck1 { - regulator-name = "vddcore"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-initial-mode = <0>; - regulator-over-current-protection; - }; - - vdd_ddr: buck2 { - regulator-name = "vdd_ddr"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-initial-mode = <0>; - regulator-over-current-protection; - }; - - vdd: buck3 { - regulator-name = "vdd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - st,mask-reset; - regulator-initial-mode = <0>; - regulator-over-current-protection; - }; - - v3v3: buck4 { - regulator-name = "v3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-over-current-protection; - regulator-initial-mode = <0>; - }; - - vdda: ldo1 { - regulator-name = "vdda"; - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - interrupts = ; - }; - - v2v8: ldo2 { - regulator-name = "v2v8"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - interrupts = ; - }; - - vtt_ddr: ldo3 { - regulator-name = "vtt_ddr"; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <750000>; - regulator-always-on; - regulator-over-current-protection; - }; - - vdd_usb: ldo4 { - regulator-name = "vdd_usb"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - interrupts = ; - }; - - vdd_sd: ldo5 { - regulator-name = "vdd_sd"; - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - interrupts = ; - regulator-boot-on; - }; - - v1v8: ldo6 { - regulator-name = "v1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - interrupts = ; - }; - - vref_ddr: vref_ddr { - regulator-name = "vref_ddr"; - regulator-always-on; - regulator-over-current-protection; - }; - - bst_out: boost { - regulator-name = "bst_out"; - interrupts = ; - }; - - vbus_otg: pwr_sw1 { - regulator-name = "vbus_otg"; - interrupts = ; - }; - - vbus_sw: pwr_sw2 { - regulator-name = "vbus_sw"; - interrupts = ; - regulator-active-discharge = <1>; - }; - }; - - onkey { - compatible = "st,stpmic1-onkey"; - interrupts = , ; - interrupt-names = "onkey-falling", "onkey-rising"; - power-off-time-sec = <10>; - status = "okay"; - }; - - watchdog { - compatible = "st,stpmic1-wdt"; - status = "disabled"; - }; - }; -}; - -&ipcc { - status = "okay"; -}; - -&iwdg2 { - timeout-sec = <32>; - status = "okay"; -}; - -&m4_rproc { - memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>, - <&vdev0vring1>, <&vdev0buffer>; - mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>; - mbox-names = "vq0", "vq1", "shutdown"; - interrupt-parent = <&exti>; - interrupts = <68 1>; - status = "okay"; -}; - -&pwr_regulators { - vdd-supply = <&vdd>; - vdd_3v3_usbfs-supply = <&vdd_usb>; -}; - -&rng1 { - status = "okay"; -}; - -&rtc { - status = "okay"; -}; - -&sdmmc1 { - pinctrl-names = "default", "opendrain", "sleep"; - pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>; - pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_a>; - pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_a>; - broken-cd; - st,sig-dir; - st,neg-edge; - st,use-ckin; - bus-width = <4>; - vmmc-supply = <&vdd_sd>; - vqmmc-supply = <&sd_switch>; - status = "okay"; -}; - -&sdmmc2 { - pinctrl-names = "default", "opendrain", "sleep"; - pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>; - pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_a>; - pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_a>; - non-removable; - no-sd; - no-sdio; - st,neg-edge; - bus-width = <8>; - vmmc-supply = <&v3v3>; - vqmmc-supply = <&v3v3>; - mmc-ddr-3_3v; - status = "okay"; -}; - -&timers6 { - status = "okay"; - /* spare dmas for other usage */ - /delete-property/dmas; - /delete-property/dma-names; - timer@5 { - status = "okay"; - }; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&uart4_pins_a>; - status = "okay"; -}; - -&usbphyc_port0 { - phy-supply = <&vdd_usb>; - vdda1v1-supply = <®11>; - vdda1v8-supply = <®18>; -}; - -&usbphyc_port1 { - phy-supply = <&vdd_usb>; - vdda1v1-supply = <®11>; - vdda1v8-supply = <®18>; -}; diff --git a/sys/gnu/dts/arm/stm32mp157c-ev1.dts b/sys/gnu/dts/arm/stm32mp157c-ev1.dts deleted file mode 100644 index 228e35e1688..00000000000 --- a/sys/gnu/dts/arm/stm32mp157c-ev1.dts +++ /dev/null @@ -1,364 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (C) STMicroelectronics 2017 - All Rights Reserved - * Author: Ludovic Barre for STMicroelectronics. - */ -/dts-v1/; - -#include "stm32mp157c-ed1.dts" -#include -#include - -/ { - model = "STMicroelectronics STM32MP157C eval daughter on eval mother"; - compatible = "st,stm32mp157c-ev1", "st,stm32mp157c-ed1", "st,stm32mp157"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - aliases { - serial0 = &uart4; - ethernet0 = ðernet0; - }; - - clocks { - clk_ext_camera: clk-ext-camera { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - }; - }; - - joystick { - compatible = "gpio-keys"; - pinctrl-0 = <&joystick_pins>; - pinctrl-names = "default"; - button-0 { - label = "JoySel"; - linux,code = ; - interrupt-parent = <&stmfx_pinctrl>; - interrupts = <0 IRQ_TYPE_EDGE_RISING>; - }; - button-1 { - label = "JoyDown"; - linux,code = ; - interrupt-parent = <&stmfx_pinctrl>; - interrupts = <1 IRQ_TYPE_EDGE_RISING>; - }; - button-2 { - label = "JoyLeft"; - linux,code = ; - interrupt-parent = <&stmfx_pinctrl>; - interrupts = <2 IRQ_TYPE_EDGE_RISING>; - }; - button-3 { - label = "JoyRight"; - linux,code = ; - interrupt-parent = <&stmfx_pinctrl>; - interrupts = <3 IRQ_TYPE_EDGE_RISING>; - }; - button-4 { - label = "JoyUp"; - linux,code = ; - interrupt-parent = <&stmfx_pinctrl>; - interrupts = <4 IRQ_TYPE_EDGE_RISING>; - }; - }; - - panel_backlight: panel-backlight { - compatible = "gpio-backlight"; - gpios = <&gpiod 13 GPIO_ACTIVE_LOW>; - default-on; - status = "okay"; - }; -}; - -&cec { - pinctrl-names = "default"; - pinctrl-0 = <&cec_pins_a>; - status = "okay"; -}; - -&dcmi { - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&dcmi_pins_a>; - pinctrl-1 = <&dcmi_sleep_pins_a>; - - port { - dcmi_0: endpoint { - remote-endpoint = <&ov5640_0>; - bus-width = <8>; - hsync-active = <0>; - vsync-active = <0>; - pclk-sample = <1>; - }; - }; -}; - -&dsi { - #address-cells = <1>; - #size-cells = <0>; - phy-dsi-supply = <®18>; - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dsi_in: endpoint { - remote-endpoint = <<dc_ep0_out>; - }; - }; - - port@1 { - reg = <1>; - dsi_out: endpoint { - remote-endpoint = <&dsi_panel_in>; - }; - }; - }; - - panel-dsi@0 { - compatible = "raydium,rm68200"; - reg = <0>; - reset-gpios = <&gpiof 15 GPIO_ACTIVE_LOW>; - backlight = <&panel_backlight>; - power-supply = <&v3v3>; - status = "okay"; - - port { - dsi_panel_in: endpoint { - remote-endpoint = <&dsi_out>; - }; - }; - }; -}; - -ðernet0 { - status = "okay"; - pinctrl-0 = <ðernet0_rgmii_pins_a>; - pinctrl-1 = <ðernet0_rgmii_pins_sleep_a>; - pinctrl-names = "default", "sleep"; - phy-mode = "rgmii-id"; - max-speed = <1000>; - phy-handle = <&phy0>; - - mdio0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - phy0: ethernet-phy@0 { - reg = <0>; - }; - }; -}; - -&fmc { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&fmc_pins_a>; - pinctrl-1 = <&fmc_sleep_pins_a>; - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - - nand@0 { - reg = <0>; - nand-on-flash-bbt; - #address-cells = <1>; - #size-cells = <1>; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; - i2c-scl-rising-time-ns = <185>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; - - ov5640: camera@3c { - compatible = "ovti,ov5640"; - reg = <0x3c>; - clocks = <&clk_ext_camera>; - clock-names = "xclk"; - DOVDD-supply = <&v2v8>; - powerdown-gpios = <&stmfx_pinctrl 18 (GPIO_ACTIVE_HIGH | GPIO_PUSH_PULL)>; - reset-gpios = <&stmfx_pinctrl 19 (GPIO_ACTIVE_LOW | GPIO_PUSH_PULL)>; - rotation = <180>; - status = "okay"; - - port { - ov5640_0: endpoint { - remote-endpoint = <&dcmi_0>; - bus-width = <8>; - data-shift = <2>; /* lines 9:2 are used */ - hsync-active = <0>; - vsync-active = <0>; - pclk-sample = <1>; - }; - }; - }; - - stmfx: stmfx@42 { - compatible = "st,stmfx-0300"; - reg = <0x42>; - interrupts = <8 IRQ_TYPE_EDGE_RISING>; - interrupt-parent = <&gpioi>; - vdd-supply = <&v3v3>; - - stmfx_pinctrl: stmfx-pin-controller { - compatible = "st,stmfx-0300-pinctrl"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&stmfx_pinctrl 0 0 24>; - - joystick_pins: joystick { - pins = "gpio0", "gpio1", "gpio2", "gpio3", "gpio4"; - bias-pull-down; - }; - }; - }; -}; - -&i2c5 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c5_pins_a>; - i2c-scl-rising-time-ns = <185>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; -}; - -<dc { - status = "okay"; - - port { - #address-cells = <1>; - #size-cells = <0>; - - ltdc_ep0_out: endpoint@0 { - reg = <0>; - remote-endpoint = <&dsi_in>; - }; - }; -}; - -&m_can1 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&m_can1_pins_a>; - pinctrl-1 = <&m_can1_sleep_pins_a>; - status = "okay"; -}; - -&qspi { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a &qspi_bk2_pins_a>; - pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a &qspi_bk2_sleep_pins_a>; - reg = <0x58003000 0x1000>, <0x70000000 0x4000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - flash0: mx66l51235l@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-rx-bus-width = <4>; - spi-max-frequency = <108000000>; - #address-cells = <1>; - #size-cells = <1>; - }; - - flash1: mx66l51235l@1 { - compatible = "jedec,spi-nor"; - reg = <1>; - spi-rx-bus-width = <4>; - spi-max-frequency = <108000000>; - #address-cells = <1>; - #size-cells = <1>; - }; -}; - -&sdmmc3 { - pinctrl-names = "default", "opendrain", "sleep"; - pinctrl-0 = <&sdmmc3_b4_pins_a>; - pinctrl-1 = <&sdmmc3_b4_od_pins_a>; - pinctrl-2 = <&sdmmc3_b4_sleep_pins_a>; - broken-cd; - st,neg-edge; - bus-width = <4>; - vmmc-supply = <&v3v3>; - status = "disabled"; -}; - -&spi1 { - pinctrl-names = "default"; - pinctrl-0 = <&spi1_pins_a>; - status = "disabled"; -}; - -&timers2 { - /* spare dmas for other usage (un-delete to enable pwm capture) */ - /delete-property/dmas; - /delete-property/dma-names; - status = "disabled"; - pwm { - pinctrl-0 = <&pwm2_pins_a>; - pinctrl-1 = <&pwm2_sleep_pins_a>; - pinctrl-names = "default", "sleep"; - status = "okay"; - }; - timer@1 { - status = "okay"; - }; -}; - -&timers8 { - /delete-property/dmas; - /delete-property/dma-names; - status = "disabled"; - pwm { - pinctrl-0 = <&pwm8_pins_a>; - pinctrl-1 = <&pwm8_sleep_pins_a>; - pinctrl-names = "default", "sleep"; - status = "okay"; - }; - timer@7 { - status = "okay"; - }; -}; - -&timers12 { - /delete-property/dmas; - /delete-property/dma-names; - status = "disabled"; - pwm { - pinctrl-0 = <&pwm12_pins_a>; - pinctrl-1 = <&pwm12_sleep_pins_a>; - pinctrl-names = "default", "sleep"; - status = "okay"; - }; - timer@11 { - status = "okay"; - }; -}; - -&usbh_ehci { - phys = <&usbphyc_port0>; - status = "okay"; -}; - -&usbotg_hs { - dr_mode = "peripheral"; - phys = <&usbphyc_port1 0>; - phy-names = "usb2-phy"; - status = "okay"; -}; - -&usbphyc { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/stm32mp15xc.dtsi b/sys/gnu/dts/arm/stm32mp15xc.dtsi deleted file mode 100644 index b06a55a2fa1..00000000000 --- a/sys/gnu/dts/arm/stm32mp15xc.dtsi +++ /dev/null @@ -1,18 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (C) STMicroelectronics 2019 - All Rights Reserved - * Author: Alexandre Torgue for STMicroelectronics. - */ - -/ { - soc { - cryp1: cryp@54001000 { - compatible = "st,stm32mp1-cryp"; - reg = <0x54001000 0x400>; - interrupts = ; - clocks = <&rcc CRYP1>; - resets = <&rcc CRYP1_R>; - status = "disabled"; - }; - }; -}; diff --git a/sys/gnu/dts/arm/stm32mp15xx-dkx.dtsi b/sys/gnu/dts/arm/stm32mp15xx-dkx.dtsi deleted file mode 100644 index f6672e87aef..00000000000 --- a/sys/gnu/dts/arm/stm32mp15xx-dkx.dtsi +++ /dev/null @@ -1,625 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (C) STMicroelectronics 2019 - All Rights Reserved - * Author: Alexandre Torgue for STMicroelectronics. - */ - -#include -#include - -/ { - memory@c0000000 { - device_type = "memory"; - reg = <0xc0000000 0x20000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - mcuram2: mcuram2@10000000 { - compatible = "shared-dma-pool"; - reg = <0x10000000 0x40000>; - no-map; - }; - - vdev0vring0: vdev0vring0@10040000 { - compatible = "shared-dma-pool"; - reg = <0x10040000 0x1000>; - no-map; - }; - - vdev0vring1: vdev0vring1@10041000 { - compatible = "shared-dma-pool"; - reg = <0x10041000 0x1000>; - no-map; - }; - - vdev0buffer: vdev0buffer@10042000 { - compatible = "shared-dma-pool"; - reg = <0x10042000 0x4000>; - no-map; - }; - - mcuram: mcuram@30000000 { - compatible = "shared-dma-pool"; - reg = <0x30000000 0x40000>; - no-map; - }; - - retram: retram@38000000 { - compatible = "shared-dma-pool"; - reg = <0x38000000 0x10000>; - no-map; - }; - - gpu_reserved: gpu@d4000000 { - reg = <0xd4000000 0x4000000>; - no-map; - }; - }; - - led { - compatible = "gpio-leds"; - blue { - label = "heartbeat"; - gpios = <&gpiod 11 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - }; - - sound { - compatible = "audio-graph-card"; - label = "STM32MP1-DK"; - routing = - "Playback" , "MCLK", - "Capture" , "MCLK", - "MICL" , "Mic Bias"; - dais = <&sai2a_port &sai2b_port &i2s2_port>; - status = "okay"; - }; -}; - -&adc { - pinctrl-names = "default"; - pinctrl-0 = <&adc12_ain_pins_a>, <&adc12_usb_cc_pins_a>; - vdd-supply = <&vdd>; - vdda-supply = <&vdd>; - vref-supply = <&vrefbuf>; - status = "disabled"; - adc1: adc@0 { - /* - * Type-C USB_PWR_CC1 & USB_PWR_CC2 on in18 & in19. - * Use at least 5 * RC time, e.g. 5 * (Rp + Rd) * C: - * 5 * (56 + 47kOhms) * 5pF => 2.5us. - * Use arbitrary margin here (e.g. 5us). - */ - st,min-sample-time-nsecs = <5000>; - /* AIN connector, USB Type-C CC1 & CC2 */ - st,adc-channels = <0 1 6 13 18 19>; - status = "okay"; - }; - adc2: adc@100 { - /* AIN connector, USB Type-C CC1 & CC2 */ - st,adc-channels = <0 1 2 6 18 19>; - st,min-sample-time-nsecs = <5000>; - status = "okay"; - }; -}; - -&cec { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&cec_pins_b>; - pinctrl-1 = <&cec_pins_sleep_b>; - status = "okay"; -}; - -ðernet0 { - status = "okay"; - pinctrl-0 = <ðernet0_rgmii_pins_a>; - pinctrl-1 = <ðernet0_rgmii_pins_sleep_a>; - pinctrl-names = "default", "sleep"; - phy-mode = "rgmii-id"; - max-speed = <1000>; - phy-handle = <&phy0>; - - mdio0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - phy0: ethernet-phy@0 { - reg = <0>; - }; - }; -}; - -&gpu { - contiguous-area = <&gpu_reserved>; - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c1_pins_a>; - pinctrl-1 = <&i2c1_pins_sleep_a>; - i2c-scl-rising-time-ns = <100>; - i2c-scl-falling-time-ns = <7>; - status = "okay"; - /delete-property/dmas; - /delete-property/dma-names; - - hdmi-transmitter@39 { - compatible = "sil,sii9022"; - reg = <0x39>; - iovcc-supply = <&v3v3_hdmi>; - cvcc12-supply = <&v1v2_hdmi>; - reset-gpios = <&gpioa 10 GPIO_ACTIVE_LOW>; - interrupts = <1 IRQ_TYPE_EDGE_FALLING>; - interrupt-parent = <&gpiog>; - #sound-dai-cells = <0>; - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - sii9022_in: endpoint { - remote-endpoint = <<dc_ep0_out>; - }; - }; - - port@3 { - reg = <3>; - sii9022_tx_endpoint: endpoint { - remote-endpoint = <&i2s2_endpoint>; - }; - }; - }; - }; - - cs42l51: cs42l51@4a { - compatible = "cirrus,cs42l51"; - reg = <0x4a>; - #sound-dai-cells = <0>; - VL-supply = <&v3v3>; - VD-supply = <&v1v8_audio>; - VA-supply = <&v1v8_audio>; - VAHP-supply = <&v1v8_audio>; - reset-gpios = <&gpiog 9 GPIO_ACTIVE_LOW>; - clocks = <&sai2a>; - clock-names = "MCLK"; - status = "okay"; - - cs42l51_port: port { - #address-cells = <1>; - #size-cells = <0>; - - cs42l51_tx_endpoint: endpoint@0 { - reg = <0>; - remote-endpoint = <&sai2a_endpoint>; - frame-master; - bitclock-master; - }; - - cs42l51_rx_endpoint: endpoint@1 { - reg = <1>; - remote-endpoint = <&sai2b_endpoint>; - frame-master; - bitclock-master; - }; - }; - }; -}; - -&i2c4 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_pins_a>; - i2c-scl-rising-time-ns = <185>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; - /* spare dmas for other usage */ - /delete-property/dmas; - /delete-property/dma-names; - - pmic: stpmic@33 { - compatible = "st,stpmic1"; - reg = <0x33>; - interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; - interrupt-controller; - #interrupt-cells = <2>; - status = "okay"; - - regulators { - compatible = "st,stpmic1-regulators"; - ldo1-supply = <&v3v3>; - ldo3-supply = <&vdd_ddr>; - ldo6-supply = <&v3v3>; - pwr_sw1-supply = <&bst_out>; - pwr_sw2-supply = <&bst_out>; - - vddcore: buck1 { - regulator-name = "vddcore"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-initial-mode = <0>; - regulator-over-current-protection; - }; - - vdd_ddr: buck2 { - regulator-name = "vdd_ddr"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-initial-mode = <0>; - regulator-over-current-protection; - }; - - vdd: buck3 { - regulator-name = "vdd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - st,mask-reset; - regulator-initial-mode = <0>; - regulator-over-current-protection; - }; - - v3v3: buck4 { - regulator-name = "v3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-over-current-protection; - regulator-initial-mode = <0>; - }; - - v1v8_audio: ldo1 { - regulator-name = "v1v8_audio"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - interrupts = ; - }; - - v3v3_hdmi: ldo2 { - regulator-name = "v3v3_hdmi"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - interrupts = ; - }; - - vtt_ddr: ldo3 { - regulator-name = "vtt_ddr"; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <750000>; - regulator-always-on; - regulator-over-current-protection; - }; - - vdd_usb: ldo4 { - regulator-name = "vdd_usb"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - interrupts = ; - }; - - vdda: ldo5 { - regulator-name = "vdda"; - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - interrupts = ; - regulator-boot-on; - }; - - v1v2_hdmi: ldo6 { - regulator-name = "v1v2_hdmi"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - interrupts = ; - }; - - vref_ddr: vref_ddr { - regulator-name = "vref_ddr"; - regulator-always-on; - regulator-over-current-protection; - }; - - bst_out: boost { - regulator-name = "bst_out"; - interrupts = ; - }; - - vbus_otg: pwr_sw1 { - regulator-name = "vbus_otg"; - interrupts = ; - }; - - vbus_sw: pwr_sw2 { - regulator-name = "vbus_sw"; - interrupts = ; - regulator-active-discharge = <1>; - }; - }; - - onkey { - compatible = "st,stpmic1-onkey"; - interrupts = , ; - interrupt-names = "onkey-falling", "onkey-rising"; - power-off-time-sec = <10>; - status = "okay"; - }; - - watchdog { - compatible = "st,stpmic1-wdt"; - status = "disabled"; - }; - }; -}; - -&i2s2 { - clocks = <&rcc SPI2>, <&rcc SPI2_K>, <&rcc PLL3_Q>, <&rcc PLL3_R>; - clock-names = "pclk", "i2sclk", "x8k", "x11k"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2s2_pins_a>; - pinctrl-1 = <&i2s2_pins_sleep_a>; - status = "okay"; - - i2s2_port: port { - i2s2_endpoint: endpoint { - remote-endpoint = <&sii9022_tx_endpoint>; - format = "i2s"; - mclk-fs = <256>; - }; - }; -}; - -&ipcc { - status = "okay"; -}; - -&iwdg2 { - timeout-sec = <32>; - status = "okay"; -}; - -<dc { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <<dc_pins_a>; - pinctrl-1 = <<dc_pins_sleep_a>; - status = "okay"; - - port { - #address-cells = <1>; - #size-cells = <0>; - - ltdc_ep0_out: endpoint@0 { - reg = <0>; - remote-endpoint = <&sii9022_in>; - }; - }; -}; - -&m4_rproc { - memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>, - <&vdev0vring1>, <&vdev0buffer>; - mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>; - mbox-names = "vq0", "vq1", "shutdown"; - interrupt-parent = <&exti>; - interrupts = <68 1>; - status = "okay"; -}; - -&pwr_regulators { - vdd-supply = <&vdd>; - vdd_3v3_usbfs-supply = <&vdd_usb>; -}; - -&rng1 { - status = "okay"; -}; - -&rtc { - status = "okay"; -}; - -&sai2 { - clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>; - clock-names = "pclk", "x8k", "x11k"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sai2a_pins_a>, <&sai2b_pins_b>; - pinctrl-1 = <&sai2a_sleep_pins_a>, <&sai2b_sleep_pins_b>; - status = "okay"; - - sai2a: audio-controller@4400b004 { - #clock-cells = <0>; - dma-names = "tx"; - clocks = <&rcc SAI2_K>; - clock-names = "sai_ck"; - status = "okay"; - - sai2a_port: port { - sai2a_endpoint: endpoint { - remote-endpoint = <&cs42l51_tx_endpoint>; - format = "i2s"; - mclk-fs = <256>; - dai-tdm-slot-num = <2>; - dai-tdm-slot-width = <32>; - }; - }; - }; - - sai2b: audio-controller@4400b024 { - dma-names = "rx"; - st,sync = <&sai2a 2>; - clocks = <&rcc SAI2_K>, <&sai2a>; - clock-names = "sai_ck", "MCLK"; - status = "okay"; - - sai2b_port: port { - sai2b_endpoint: endpoint { - remote-endpoint = <&cs42l51_rx_endpoint>; - format = "i2s"; - mclk-fs = <256>; - dai-tdm-slot-num = <2>; - dai-tdm-slot-width = <32>; - }; - }; - }; -}; - -&sdmmc1 { - pinctrl-names = "default", "opendrain", "sleep"; - pinctrl-0 = <&sdmmc1_b4_pins_a>; - pinctrl-1 = <&sdmmc1_b4_od_pins_a>; - pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; - broken-cd; - st,neg-edge; - bus-width = <4>; - vmmc-supply = <&v3v3>; - status = "okay"; -}; - -&sdmmc3 { - pinctrl-names = "default", "opendrain", "sleep"; - pinctrl-0 = <&sdmmc3_b4_pins_a>; - pinctrl-1 = <&sdmmc3_b4_od_pins_a>; - pinctrl-2 = <&sdmmc3_b4_sleep_pins_a>; - broken-cd; - st,neg-edge; - bus-width = <4>; - vmmc-supply = <&v3v3>; - status = "disabled"; -}; - -&timers1 { - /* spare dmas for other usage */ - /delete-property/dmas; - /delete-property/dma-names; - status = "disabled"; - pwm { - pinctrl-0 = <&pwm1_pins_a>; - pinctrl-1 = <&pwm1_sleep_pins_a>; - pinctrl-names = "default", "sleep"; - status = "okay"; - }; - timer@0 { - status = "okay"; - }; -}; - -&timers3 { - /delete-property/dmas; - /delete-property/dma-names; - status = "disabled"; - pwm { - pinctrl-0 = <&pwm3_pins_a>; - pinctrl-1 = <&pwm3_sleep_pins_a>; - pinctrl-names = "default", "sleep"; - status = "okay"; - }; - timer@2 { - status = "okay"; - }; -}; - -&timers4 { - /delete-property/dmas; - /delete-property/dma-names; - status = "disabled"; - pwm { - pinctrl-0 = <&pwm4_pins_a &pwm4_pins_b>; - pinctrl-1 = <&pwm4_sleep_pins_a &pwm4_sleep_pins_b>; - pinctrl-names = "default", "sleep"; - status = "okay"; - }; - timer@3 { - status = "okay"; - }; -}; - -&timers5 { - /delete-property/dmas; - /delete-property/dma-names; - status = "disabled"; - pwm { - pinctrl-0 = <&pwm5_pins_a>; - pinctrl-1 = <&pwm5_sleep_pins_a>; - pinctrl-names = "default", "sleep"; - status = "okay"; - }; - timer@4 { - status = "okay"; - }; -}; - -&timers6 { - /delete-property/dmas; - /delete-property/dma-names; - status = "disabled"; - timer@5 { - status = "okay"; - }; -}; - -&timers12 { - /delete-property/dmas; - /delete-property/dma-names; - status = "disabled"; - pwm { - pinctrl-0 = <&pwm12_pins_a>; - pinctrl-1 = <&pwm12_sleep_pins_a>; - pinctrl-names = "default", "sleep"; - status = "okay"; - }; - timer@11 { - status = "okay"; - }; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&uart4_pins_a>; - status = "okay"; -}; - -&usbh_ehci { - phys = <&usbphyc_port0>; - status = "okay"; -}; - -&usbotg_hs { - dr_mode = "peripheral"; - phys = <&usbphyc_port1 0>; - phy-names = "usb2-phy"; - status = "okay"; -}; - -&usbphyc { - status = "okay"; -}; - -&usbphyc_port0 { - phy-supply = <&vdd_usb>; - vdda1v1-supply = <®11>; - vdda1v8-supply = <®18>; -}; - -&usbphyc_port1 { - phy-supply = <&vdd_usb>; - vdda1v1-supply = <®11>; - vdda1v8-supply = <®18>; -}; - -&vrefbuf { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - vdda-supply = <&vdd>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/stm32mp15xxaa-pinctrl.dtsi b/sys/gnu/dts/arm/stm32mp15xxaa-pinctrl.dtsi deleted file mode 100644 index 04f7a43ad66..00000000000 --- a/sys/gnu/dts/arm/stm32mp15xxaa-pinctrl.dtsi +++ /dev/null @@ -1,85 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (C) STMicroelectronics 2019 - All Rights Reserved - * Author: Alexandre Torgue for STMicroelectronics. - */ - -&pinctrl { - st,package = ; - - gpioa: gpio@50002000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 0 16>; - }; - - gpiob: gpio@50003000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 16 16>; - }; - - gpioc: gpio@50004000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 32 16>; - }; - - gpiod: gpio@50005000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 48 16>; - }; - - gpioe: gpio@50006000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 64 16>; - }; - - gpiof: gpio@50007000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 80 16>; - }; - - gpiog: gpio@50008000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 96 16>; - }; - - gpioh: gpio@50009000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 112 16>; - }; - - gpioi: gpio@5000a000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 128 16>; - }; - - gpioj: gpio@5000b000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 144 16>; - }; - - gpiok: gpio@5000c000 { - status = "okay"; - ngpios = <8>; - gpio-ranges = <&pinctrl 0 160 8>; - }; -}; - -&pinctrl_z { - st,package = ; - - gpioz: gpio@54004000 { - status = "okay"; - ngpios = <8>; - gpio-ranges = <&pinctrl_z 0 400 8>; - }; -}; diff --git a/sys/gnu/dts/arm/stm32mp15xxab-pinctrl.dtsi b/sys/gnu/dts/arm/stm32mp15xxab-pinctrl.dtsi deleted file mode 100644 index 328dad140e9..00000000000 --- a/sys/gnu/dts/arm/stm32mp15xxab-pinctrl.dtsi +++ /dev/null @@ -1,57 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (C) STMicroelectronics 2019 - All Rights Reserved - * Author: Alexandre Torgue for STMicroelectronics. - */ - -&pinctrl { - st,package = ; - - gpioa: gpio@50002000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 0 16>; - }; - - gpiob: gpio@50003000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 16 16>; - }; - - gpioc: gpio@50004000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 32 16>; - }; - - gpiod: gpio@50005000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 48 16>; - }; - - gpioe: gpio@50006000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 64 16>; - }; - - gpiof: gpio@50007000 { - status = "okay"; - ngpios = <6>; - gpio-ranges = <&pinctrl 6 86 6>; - }; - - gpiog: gpio@50008000 { - status = "okay"; - ngpios = <10>; - gpio-ranges = <&pinctrl 6 102 10>; - }; - - gpioh: gpio@50009000 { - status = "okay"; - ngpios = <2>; - gpio-ranges = <&pinctrl 0 112 2>; - }; -}; diff --git a/sys/gnu/dts/arm/stm32mp15xxac-pinctrl.dtsi b/sys/gnu/dts/arm/stm32mp15xxac-pinctrl.dtsi deleted file mode 100644 index 7eaa245f44d..00000000000 --- a/sys/gnu/dts/arm/stm32mp15xxac-pinctrl.dtsi +++ /dev/null @@ -1,73 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (C) STMicroelectronics 2019 - All Rights Reserved - * Author: Alexandre Torgue for STMicroelectronics. - */ - -&pinctrl { - st,package = ; - - gpioa: gpio@50002000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 0 16>; - }; - - gpiob: gpio@50003000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 16 16>; - }; - - gpioc: gpio@50004000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 32 16>; - }; - - gpiod: gpio@50005000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 48 16>; - }; - - gpioe: gpio@50006000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 64 16>; - }; - - gpiof: gpio@50007000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 80 16>; - }; - - gpiog: gpio@50008000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 96 16>; - }; - - gpioh: gpio@50009000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 112 16>; - }; - - gpioi: gpio@5000a000 { - status = "okay"; - ngpios = <12>; - gpio-ranges = <&pinctrl 0 128 12>; - }; -}; - -&pinctrl_z { - st,package = ; - - gpioz: gpio@54004000 { - status = "okay"; - ngpios = <8>; - gpio-ranges = <&pinctrl_z 0 400 8>; - }; -}; diff --git a/sys/gnu/dts/arm/stm32mp15xxad-pinctrl.dtsi b/sys/gnu/dts/arm/stm32mp15xxad-pinctrl.dtsi deleted file mode 100644 index b63e207de21..00000000000 --- a/sys/gnu/dts/arm/stm32mp15xxad-pinctrl.dtsi +++ /dev/null @@ -1,57 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (C) STMicroelectronics 2019 - All Rights Reserved - * Author: Alexandre Torgue for STMicroelectronics. - */ - -&pinctrl { - st,package = ; - - gpioa: gpio@50002000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 0 16>; - }; - - gpiob: gpio@50003000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 16 16>; - }; - - gpioc: gpio@50004000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 32 16>; - }; - - gpiod: gpio@50005000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 48 16>; - }; - - gpioe: gpio@50006000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 64 16>; - }; - - gpiof: gpio@50007000 { - status = "okay"; - ngpios = <6>; - gpio-ranges = <&pinctrl 6 86 6>; - }; - - gpiog: gpio@50008000 { - status = "okay"; - ngpios = <10>; - gpio-ranges = <&pinctrl 6 102 10>; - }; - - gpioh: gpio@50009000 { - status = "okay"; - ngpios = <2>; - gpio-ranges = <&pinctrl 0 112 2>; - }; -}; diff --git a/sys/gnu/dts/arm/sun4i-a10-a1000.dts b/sys/gnu/dts/arm/sun4i-a10-a1000.dts deleted file mode 100644 index 8692b11a83c..00000000000 --- a/sys/gnu/dts/arm/sun4i-a10-a1000.dts +++ /dev/null @@ -1,230 +0,0 @@ -/* - * Copyright 2013 Emilio López - * - * Emilio López - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun4i-a10.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include - -/ { - model = "Mele A1000"; - compatible = "mele,a1000", "allwinner,sun4i-a10"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - red { - label = "a1000:red:usr"; - gpios = <&pio 7 10 GPIO_ACTIVE_HIGH>; - }; - - blue { - label = "a1000:blue:pwr"; - gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; - - reg_emac_3v3: emac-3v3 { - compatible = "regulator-fixed"; - regulator-name = "emac-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <20000>; - enable-active-high; - gpio = <&pio 7 15 GPIO_ACTIVE_HIGH>; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "On-board SPDIF"; - - simple-audio-card,cpu { - sound-dai = <&spdif>; - }; - - simple-audio-card,codec { - sound-dai = <&spdif_out>; - }; - }; - - spdif_out: spdif-out { - #sound-dai-cells = <0>; - compatible = "linux,spdif-dit"; - }; -}; - -&ahci { - status = "okay"; -}; - -&codec { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&emac { - phy-handle = <&phy1>; - status = "okay"; -}; - -&emac_sram { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - compatible = "x-powers,axp209"; - reg = <0x34>; - interrupts = <0>; - - interrupt-controller; - #interrupt-cells = <1>; - }; -}; - -&ir0 { - pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pins>; - status = "okay"; -}; - -&mdio { - phy-supply = <®_emac_3v3>; - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -#include "axp209.dtsi" - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1250000>; - regulator-name = "vdd-int-dll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&spdif { - pinctrl-names = "default"; - pinctrl-0 = <&spdif_tx_pin>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usbphy { - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun4i-a10-ba10-tvbox.dts b/sys/gnu/dts/arm/sun4i-a10-ba10-tvbox.dts deleted file mode 100644 index 816d534ac09..00000000000 --- a/sys/gnu/dts/arm/sun4i-a10-ba10-tvbox.dts +++ /dev/null @@ -1,151 +0,0 @@ -/* - * Copyright 2014 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun4i-a10.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include - -/ { - model = "BA10 tvbox"; - compatible = "allwinner,ba10-tvbox", "allwinner,sun4i-a10"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&emac { - phy-handle = <&phy1>; - status = "okay"; -}; - -&emac_sram { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - compatible = "x-powers,axp209"; - reg = <0x34>; - interrupts = <0>; - - interrupt-controller; - #interrupt-cells = <1>; - }; -}; - -&ir0 { - pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pins>; - status = "okay"; -}; - -&mdio { - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -®_usb0_vbus { - regulator-boot-on; - status = "okay"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - gpio = <&pio 7 12 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "host"; - status = "okay"; -}; - -&usbphy { - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun4i-a10-chuwi-v7-cw0825.dts b/sys/gnu/dts/arm/sun4i-a10-chuwi-v7-cw0825.dts deleted file mode 100644 index 74262988881..00000000000 --- a/sys/gnu/dts/arm/sun4i-a10-chuwi-v7-cw0825.dts +++ /dev/null @@ -1,159 +0,0 @@ -/* - * Copyright 2015 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun4i-a10.dtsi" -#include "sunxi-common-regulators.dtsi" -#include -#include -#include - -/ { - model = "Chuwi V7 CW0825"; - compatible = "chuwi,v7-cw0825", "allwinner,sun4i-a10"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&ehci1 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - compatible = "x-powers,axp209"; - reg = <0x34>; - interrupts = <0>; - - interrupt-controller; - #interrupt-cells = <1>; - }; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; - - ft5306de4: touchscreen@38 { - compatible = "edt,edt-ft5406"; - reg = <0x38>; - interrupt-parent = <&pio>; - interrupts = <7 21 IRQ_TYPE_EDGE_FALLING>; - touchscreen-size-x = <1024>; - touchscreen-size-y = <768>; - }; -}; - -&lradc { - vref-supply = <®_vcc3v0>; - status = "okay"; - - button-800 { - label = "Volume Up"; - linux,code = ; - channel = <0>; - voltage = <800000>; - }; - - button-1000 { - label = "Volume Down"; - linux,code = ; - channel = <0>; - voltage = <1000000>; - }; - - button-1200 { - label = "Back"; - linux,code = ; - channel = <0>; - voltage = <1200000>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -®_usb0_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ - usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */ - usb0_vbus-supply = <®_usb0_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun4i-a10-cubieboard.dts b/sys/gnu/dts/arm/sun4i-a10-cubieboard.dts deleted file mode 100644 index 6ca02e824ac..00000000000 --- a/sys/gnu/dts/arm/sun4i-a10-cubieboard.dts +++ /dev/null @@ -1,255 +0,0 @@ -/* - * Copyright 2012 Stefan Roese - * Stefan Roese - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun4i-a10.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include - -/ { - model = "Cubietech Cubieboard"; - compatible = "cubietech,a10-cubieboard", "allwinner,sun4i-a10"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_cubieboard>; - - blue { - label = "cubieboard:blue:usr"; - gpios = <&pio 7 21 GPIO_ACTIVE_HIGH>; /* LED1 */ - }; - - green { - label = "cubieboard:green:usr"; - gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>; /* LED2 */ - linux,default-trigger = "heartbeat"; - }; - }; -}; - -&ahci { - target-supply = <®_ahci_5v>; - status = "okay"; -}; - -&codec { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&de { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&emac { - phy-handle = <&phy1>; - status = "okay"; -}; - -&emac_sram { - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupts = <0>; - }; -}; - -&i2c1 { - status = "okay"; -}; - -&ir0 { - pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pins>; - status = "okay"; -}; - -&mdio { - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pio { - led_pins_cubieboard: led-pins { - pins = "PH20", "PH21"; - function = "gpio_out"; - drive-strength = <20>; - }; -}; - -®_ahci_5v { - status = "okay"; -}; - -#include "axp209.dtsi" - -&ac_power_supply { - status = "okay"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1450000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-int-dll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pi_pins>, - <&spi0_cs0_pi_pin>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun4i-a10-dserve-dsrv9703c.dts b/sys/gnu/dts/arm/sun4i-a10-dserve-dsrv9703c.dts deleted file mode 100644 index 8ee3ff42bd5..00000000000 --- a/sys/gnu/dts/arm/sun4i-a10-dserve-dsrv9703c.dts +++ /dev/null @@ -1,217 +0,0 @@ -/* - * Copyright 2016 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun4i-a10.dtsi" -#include "sunxi-common-regulators.dtsi" -#include -#include -#include -#include - -/ { - model = "Dserve DSRV9703C"; - compatible = "dserve,dsrv9703c", "allwinner,sun4i-a10"; - - aliases { - serial0 = &uart0; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; - brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; - default-brightness-level = <8>; - enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */ - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - haptics { - compatible = "regulator-haptic"; - haptic-supply = <®_motor>; - min-microvolt = <3000000>; - max-microvolt = <3000000>; - }; - - reg_motor: reg-motor { - compatible = "regulator-fixed"; - regulator-name = "vcc-motor"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - enable-active-high; - gpio = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */ - }; -}; - -&codec { - allwinner,pa-gpios = <&pio 7 15 GPIO_ACTIVE_HIGH>; /* PH15 */ - status = "okay"; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&ehci1 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupts = <0>; - }; -}; - -#include "axp209.dtsi" - -&i2c1 { - /* pull-ups and devices require AXP209 LDO3 */ - status = "failed"; -}; - -&i2c2 { - status = "okay"; - - ft5406ee8: touchscreen@38 { - compatible = "edt,edt-ft5406"; - reg = <0x38>; - interrupt-parent = <&pio>; - interrupts = <7 21 IRQ_TYPE_EDGE_FALLING>; - reset-gpios = <&pio 1 13 GPIO_ACTIVE_LOW>; - touchscreen-size-x = <1024>; - touchscreen-size-y = <768>; - }; -}; - -&lradc { - vref-supply = <®_ldo2>; - status = "okay"; - - button-400 { - label = "Volume Down"; - linux,code = ; - channel = <0>; - voltage = <400000>; - }; - - button-800 { - label = "Volume Up"; - linux,code = ; - channel = <0>; - voltage = <800000>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pin>; - status = "okay"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1250000>; - regulator-name = "vdd-int-dll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_usb0_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ - usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */ - usb0_vbus-supply = <®_usb0_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun4i-a10-gemei-g9.dts b/sys/gnu/dts/arm/sun4i-a10-gemei-g9.dts deleted file mode 100644 index ea7a59dcf8f..00000000000 --- a/sys/gnu/dts/arm/sun4i-a10-gemei-g9.dts +++ /dev/null @@ -1,192 +0,0 @@ -/* - * Copyright 2015 Priit Laes - * - * Priit Laes - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun4i-a10.dtsi" -#include "sunxi-common-regulators.dtsi" -#include -#include -#include - -/ { - model = "Gemei G9 Tablet"; - compatible = "gemei,g9", "allwinner,sun4i-a10"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -/* - * TODO: - * 2x cameras via CSI - * AXP battery management - * NAND - * OTG - * Touchscreen - gt801_2plus1 @ i2c adapter 2 @ 0x48 - */ -&codec { - /* PH15 controls power to external amplifier (ft2012q) */ - allwinner,pa-gpios = <&pio 7 15 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupts = <0>; - }; -}; - -#include "axp209.dtsi" - -&i2c1 { - status = "okay"; - - /* Accelerometer */ - bma250@18 { - compatible = "bosch,bma250"; - reg = <0x18>; - interrupt-parent = <&pio>; - interrupts = <7 0 IRQ_TYPE_EDGE_RISING>; /* PH00 / EINT0 */ - }; -}; - -&lradc { - vref-supply = <®_ldo2>; - - status = "okay"; - - button-158 { - label = "Volume Down"; - linux,code = ; - channel = <0>; - voltage = <158730>; - }; - - button-349 { - label = "Volume Up"; - linux,code = ; - channel = <0>; - voltage = <349206>; - }; - - button-1142 { - label = "Esc"; - linux,code = ; - channel = <0>; - voltage = <1142856>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH01 */ - status = "okay"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1250000>; - regulator-name = "vdd-int-dll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usbphy { - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun4i-a10-hackberry.dts b/sys/gnu/dts/arm/sun4i-a10-hackberry.dts deleted file mode 100644 index 47dea092250..00000000000 --- a/sys/gnu/dts/arm/sun4i-a10-hackberry.dts +++ /dev/null @@ -1,140 +0,0 @@ -/* - * Copyright 2012 Maxime Ripard - * - * Maxime Ripard - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun4i-a10.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include - -/ { - model = "Miniand Hackberry"; - compatible = "miniand,hackberry", "allwinner,sun4i-a10"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - reg_emac_3v3: emac-3v3 { - compatible = "regulator-fixed"; - regulator-name = "emac-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <20000>; - enable-active-high; - gpio = <&pio 7 19 GPIO_ACTIVE_HIGH>; - }; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&emac { - phy-handle = <&phy0>; - status = "okay"; -}; - -&emac_sram { - status = "okay"; -}; - -&ir0 { - pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pins>; - status = "okay"; -}; - -&mdio { - phy-supply = <®_emac_3v3>; - status = "okay"; - - phy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - gpio = <&pio 7 12 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&usbphy { - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun4i-a10-hyundai-a7hd.dts b/sys/gnu/dts/arm/sun4i-a10-hyundai-a7hd.dts deleted file mode 100644 index bf2044bac42..00000000000 --- a/sys/gnu/dts/arm/sun4i-a10-hyundai-a7hd.dts +++ /dev/null @@ -1,115 +0,0 @@ -/* - * Copyright 2015 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun4i-a10.dtsi" -#include "sunxi-common-regulators.dtsi" -#include - -/ { - model = "Hyundai A7HD"; - compatible = "hyundai,a7hd", "allwinner,sun4i-a10"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&ehci1 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - compatible = "x-powers,axp209"; - reg = <0x34>; - interrupts = <0>; - - interrupt-controller; - #interrupt-cells = <1>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -®_usb0_vbus { - status = "okay"; -}; - -®_usb2_vbus { - gpio = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */ - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ - usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */ - usb0_vbus-supply = <®_usb0_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun4i-a10-inet1.dts b/sys/gnu/dts/arm/sun4i-a10-inet1.dts deleted file mode 100644 index ca878384e90..00000000000 --- a/sys/gnu/dts/arm/sun4i-a10-inet1.dts +++ /dev/null @@ -1,228 +0,0 @@ -/* - * Copyright 2015 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun4i-a10.dtsi" -#include "sunxi-common-regulators.dtsi" -#include -#include -#include -#include - -/ { - model = "iNet-1"; - compatible = "inet-tek,inet1", "allwinner,sun4i-a10"; - - aliases { - serial0 = &uart0; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; - brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; - default-brightness-level = <8>; - enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */ - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&codec { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupts = <0>; - }; -}; - -#include "axp209.dtsi" - -&i2c1 { - status = "okay"; - - /* Accelerometer */ - bma250@18 { - compatible = "bosch,bma250"; - reg = <0x18>; - interrupt-parent = <&pio>; - interrupts = <7 0 IRQ_TYPE_EDGE_RISING>; /* PH0 / EINT0 */ - }; -}; - -&i2c2 { - status = "okay"; - - ft5x: touchscreen@38 { - compatible = "edt,edt-ft5406"; - reg = <0x38>; - interrupt-parent = <&pio>; - interrupts = <7 21 IRQ_TYPE_EDGE_FALLING>; - wake-gpios = <&pio 1 13 GPIO_ACTIVE_HIGH>; /* PB13 */ - touchscreen-size-x = <600>; - touchscreen-size-y = <1024>; - touchscreen-swapped-x-y; - }; -}; - -&lradc { - vref-supply = <®_ldo2>; - status = "okay"; - - button-200 { - label = "Volume Up"; - linux,code = ; - channel = <0>; - voltage = <200000>; - }; - - button-1000 { - label = "Volume Down"; - linux,code = ; - channel = <0>; - voltage = <1000000>; - }; - - button-1200 { - label = "Home"; - linux,code = ; - channel = <0>; - voltage = <1200000>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pin>; - status = "okay"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1250000>; - regulator-name = "vdd-int-dll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_usb0_vbus { - status = "okay"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ - usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */ - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun4i-a10-inet97fv2.dts b/sys/gnu/dts/arm/sun4i-a10-inet97fv2.dts deleted file mode 100644 index 76016f2ca29..00000000000 --- a/sys/gnu/dts/arm/sun4i-a10-inet97fv2.dts +++ /dev/null @@ -1,203 +0,0 @@ -/* - * Copyright 2014 Open Source Support GmbH - * - * David Lanzendörfer - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun4i-a10.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include -#include - -/ { - model = "INet-97F Rev 02"; - compatible = "primux,inet97fv2", "allwinner,sun4i-a10"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&ehci1 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupts = <0>; - }; -}; - -#include "axp209.dtsi" - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; - - ft5406ee8: touchscreen@38 { - compatible = "edt,edt-ft5406"; - reg = <0x38>; - interrupt-parent = <&pio>; - interrupts = <7 21 IRQ_TYPE_EDGE_FALLING>; - touchscreen-size-x = <800>; - touchscreen-size-y = <480>; - }; -}; - -&lradc { - vref-supply = <®_ldo2>; - status = "okay"; - - button-200 { - label = "Menu"; - linux,code = ; - channel = <0>; - voltage = <200000>; - }; - - button-600 { - label = "Volume Up"; - linux,code = ; - channel = <0>; - voltage = <600000>; - }; - - button-800 { - label = "Volume Down"; - linux,code = ; - channel = <0>; - voltage = <800000>; - }; - - button-1000 { - label = "Home"; - linux,code = ; - channel = <0>; - voltage = <1000000>; - }; - - button-1200 { - label = "Esc"; - linux,code = ; - channel = <0>; - voltage = <1200000>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1250000>; - regulator-name = "vdd-int-dll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_usb0_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ - usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */ - usb0_vbus-supply = <®_usb0_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun4i-a10-inet9f-rev03.dts b/sys/gnu/dts/arm/sun4i-a10-inet9f-rev03.dts deleted file mode 100644 index 0a562b2cc5b..00000000000 --- a/sys/gnu/dts/arm/sun4i-a10-inet9f-rev03.dts +++ /dev/null @@ -1,357 +0,0 @@ -/* - * Copyright 2015 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun4i-a10.dtsi" -#include "sunxi-common-regulators.dtsi" -#include -#include -#include - -/ { - model = "iNet-9F Rev 03"; - compatible = "inet-tek,inet9f-rev03", "allwinner,sun4i-a10"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - gpio-keys { - compatible = "gpio-keys-polled"; - poll-interval = <20>; - - left-joystick-left { - label = "Left Joystick Left"; - linux,code = ; - linux,input-type = ; - linux,input-value = <0xffffffff>; /* -1 */ - gpios = <&pio 0 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA6 */ - }; - - left-joystick-right { - label = "Left Joystick Right"; - linux,code = ; - linux,input-type = ; - linux,input-value = <1>; - gpios = <&pio 0 5 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA5 */ - }; - - left-joystick-up { - label = "Left Joystick Up"; - linux,code = ; - linux,input-type = ; - linux,input-value = <0xffffffff>; /* -1 */ - gpios = <&pio 0 8 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA8 */ - }; - - left-joystick-down { - label = "Left Joystick Down"; - linux,code = ; - linux,input-type = ; - linux,input-value = <1>; - gpios = <&pio 0 9 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA9 */ - }; - - right-joystick-left { - label = "Right Joystick Left"; - linux,code = ; - linux,input-type = ; - linux,input-value = <0xffffffff>; /* -1 */ - gpios = <&pio 0 1 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA1 */ - }; - - right-joystick-right { - label = "Right Joystick Right"; - linux,code = ; - linux,input-type = ; - linux,input-value = <1>; - gpios = <&pio 0 0 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA0 */ - }; - - right-joystick-up { - label = "Right Joystick Up"; - linux,code = ; - linux,input-type = ; - linux,input-value = <0xffffffff>; /* -1 */ - gpios = <&pio 0 3 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA3 */ - }; - - right-joystick-down { - label = "Right Joystick Down"; - linux,code = ; - linux,input-type = ; - linux,input-value = <1>; - gpios = <&pio 0 4 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA4 */ - }; - - dpad-left { - label = "DPad Left"; - linux,code = ; - linux,input-type = ; - linux,input-value = <0xffffffff>; /* -1 */ - gpios = <&pio 7 23 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PH23 */ - }; - - dpad-right { - label = "DPad Right"; - linux,code = ; - linux,input-type = ; - linux,input-value = <1>; - gpios = <&pio 7 24 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PH24 */ - }; - - dpad-up { - label = "DPad Up"; - linux,code = ; - linux,input-type = ; - linux,input-value = <0xffffffff>; /* -1 */ - gpios = <&pio 7 25 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PH25 */ - }; - - dpad-down { - label = "DPad Down"; - linux,code = ; - linux,input-type = ; - linux,input-value = <1>; - gpios = <&pio 7 26 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PH26 */ - }; - - x { - label = "Button X"; - linux,code = ; - gpios = <&pio 0 16 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA16 */ - }; - - y { - label = "Button Y"; - linux,code = ; - gpios = <&pio 0 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA14 */ - }; - - a { - label = "Button A"; - linux,code = ; - gpios = <&pio 0 17 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA17 */ - }; - - b { - label = "Button B"; - linux,code = ; - gpios = <&pio 0 15 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA15 */ - }; - - select { - label = "Select Button"; - linux,code = ; - gpios = <&pio 0 11 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA11 */ - }; - - start { - label = "Start Button"; - linux,code = ; - gpios = <&pio 0 12 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA12 */ - }; - - top-left { - label = "Top Left Button"; - linux,code = ; - gpios = <&pio 7 22 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PH22 */ - }; - - top-right { - label = "Top Right Button"; - linux,code = ; - gpios = <&pio 0 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA13 */ - }; - }; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&ehci1 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupts = <0>; - }; -}; - -#include "axp209.dtsi" - -&i2c1 { - status = "okay"; - - /* Accelerometer */ - bma250@18 { - compatible = "bosch,bma250"; - reg = <0x18>; - interrupt-parent = <&pio>; - interrupts = <7 0 IRQ_TYPE_EDGE_RISING>; /* PH0 / EINT0 */ - }; -}; - -&i2c2 { - status = "okay"; - - ft5406ee8: touchscreen@38 { - compatible = "edt,edt-ft5406"; - reg = <0x38>; - interrupt-parent = <&pio>; - interrupts = <7 21 IRQ_TYPE_EDGE_FALLING>; - touchscreen-size-x = <800>; - touchscreen-size-y = <480>; - }; -}; - -&lradc { - vref-supply = <®_ldo2>; - status = "okay"; - - button-200 { - label = "Menu"; - linux,code = ; - channel = <0>; - voltage = <200000>; - }; - - button-600 { - label = "Volume Up"; - linux,code = ; - channel = <0>; - voltage = <600000>; - }; - - button-800 { - label = "Volume Down"; - linux,code = ; - channel = <0>; - voltage = <800000>; - }; - - button-1000 { - label = "Home"; - linux,code = ; - channel = <0>; - voltage = <1000000>; - }; - - button-1200 { - label = "Esc"; - linux,code = ; - channel = <0>; - voltage = <1200000>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1250000>; - regulator-name = "vdd-int-dll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_usb0_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ - usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */ - usb0_vbus-supply = <®_usb0_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun4i-a10-itead-iteaduino-plus.dts b/sys/gnu/dts/arm/sun4i-a10-itead-iteaduino-plus.dts deleted file mode 100644 index d4e319d16aa..00000000000 --- a/sys/gnu/dts/arm/sun4i-a10-itead-iteaduino-plus.dts +++ /dev/null @@ -1,126 +0,0 @@ -/* - * Copyright 2015 Josef Gajdusek - * Copyright 2015 - Marcus Cooper - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun4i-a10.dtsi" -#include "sunxi-itead-core-common.dtsi" - -/ { - model = "Iteaduino Plus A10"; - compatible = "itead,iteaduino-plus-a10", "allwinner,sun4i-a10"; -}; - -&ahci { - target-supply = <®_ahci_5v>; - status = "okay"; -}; - -&emac { - pinctrl-names = "default"; - pinctrl-0 = <&emac_pins>; - phy-handle = <&phy1>; - status = "okay"; -}; - -&emac_sram { - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - - axp209: pmic@34 { - interrupts = <0>; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - status = "okay"; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - status = "okay"; -}; - -&ir0 { - pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pins>; - status = "okay"; -}; - -&mdio { - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ - status = "okay"; -}; - -®_ahci_5v { - status = "okay"; -}; - -&spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pi_pins>, - <&spi0_cs0_pi_pin>; - status = "okay"; -}; - -&uart0 { - pinctrl-0 = <&uart0_pb_pins>; -}; diff --git a/sys/gnu/dts/arm/sun4i-a10-jesurun-q5.dts b/sys/gnu/dts/arm/sun4i-a10-jesurun-q5.dts deleted file mode 100644 index 8a7b4c53d27..00000000000 --- a/sys/gnu/dts/arm/sun4i-a10-jesurun-q5.dts +++ /dev/null @@ -1,181 +0,0 @@ -/* - * Copyright 2015 Gábor Nyers - * - * Gábor Nyers - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun4i-a10.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include - -/ { - model = "Jesurun Q5"; - compatible = "jesurun,q5", "allwinner,sun4i-a10"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - green { - label = "q5:green:usr"; - gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>; /* PH20 */ - }; - - }; - - reg_emac_3v3: emac-3v3 { - compatible = "regulator-fixed"; - regulator-name = "emac-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <20000>; - enable-active-high; - gpio = <&pio 7 19 GPIO_ACTIVE_HIGH>; /* PH19 */ - }; -}; - -&ahci { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&emac { - phy-handle = <&phy1>; - status = "okay"; -}; - -&emac_sram { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - compatible = "x-powers,axp209"; - reg = <0x34>; - interrupts = <0>; - - interrupt-controller; - #interrupt-cells = <1>; - }; -}; - -&ir0 { - pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pins>; - status = "okay"; -}; - -&mdio { - phy-supply = <®_emac_3v3>; - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -®_usb0_vbus { - regulator-boot-on; - status = "okay"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "host"; - status = "okay"; -}; - -&usbphy { - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun4i-a10-marsboard.dts b/sys/gnu/dts/arm/sun4i-a10-marsboard.dts deleted file mode 100644 index a843e57530e..00000000000 --- a/sys/gnu/dts/arm/sun4i-a10-marsboard.dts +++ /dev/null @@ -1,182 +0,0 @@ -/* - * Copyright 2015 Aleksei Mamlin - * Aleksei Mamlin - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun4i-a10.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include - -/ { - model = "HAOYU Electronics Marsboard A10"; - compatible = "haoyu,a10-marsboard", "allwinner,sun4i-a10"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - red1 { - label = "marsboard:red1:usr"; - gpios = <&pio 1 5 GPIO_ACTIVE_HIGH>; - }; - - red2 { - label = "marsboard:red2:usr"; - gpios = <&pio 1 6 GPIO_ACTIVE_HIGH>; - }; - - red3 { - label = "marsboard:red3:usr"; - gpios = <&pio 1 7 GPIO_ACTIVE_HIGH>; - }; - - red4 { - label = "marsboard:red4:usr"; - gpios = <&pio 1 8 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&ahci { - status = "okay"; -}; - -&codec { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&emac_sram { - status = "okay"; -}; - -&emac { - phy-handle = <&phy1>; - status = "okay"; -}; - -&i2c0 { - status = "okay"; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&mdio { - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pi_pins>, - <&spi0_cs0_pi_pin>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun4i-a10-mini-xplus.dts b/sys/gnu/dts/arm/sun4i-a10-mini-xplus.dts deleted file mode 100644 index f9d74e21031..00000000000 --- a/sys/gnu/dts/arm/sun4i-a10-mini-xplus.dts +++ /dev/null @@ -1,144 +0,0 @@ -/* - * Copyright 2012 Maxime Ripard - * - * Maxime Ripard - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun4i-a10.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include - -/ { - model = "PineRiver Mini X-Plus"; - compatible = "pineriver,mini-xplus", "allwinner,sun4i-a10"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - compatible = "x-powers,axp209"; - reg = <0x34>; - interrupts = <0>; - - interrupt-controller; - #interrupt-cells = <1>; - }; -}; - -&ir0 { - pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pins>; - status = "okay"; -}; - -&ir0_rx_pins { - /* The ir receiver is not always populated */ - bias-pull-up; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -®_usb0_vbus { - regulator-boot-on; - status = "okay"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "host"; - status = "okay"; -}; - -&usbphy { - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun4i-a10-mk802.dts b/sys/gnu/dts/arm/sun4i-a10-mk802.dts deleted file mode 100644 index 059fe9c5d02..00000000000 --- a/sys/gnu/dts/arm/sun4i-a10-mk802.dts +++ /dev/null @@ -1,144 +0,0 @@ -/* - * Copyright 2015 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun4i-a10.dtsi" -#include "sunxi-common-regulators.dtsi" -#include - -/ { - model = "MK802"; - compatible = "allwinner,mk802", "allwinner,sun4i-a10"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; -}; - -&codec { - status = "okay"; -}; - -&de { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -®_usb0_vbus { - status = "okay"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - gpio = <&pio 7 12 GPIO_ACTIVE_HIGH>; /* PH12 */ - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ - usb0_vbus_det-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun4i-a10-mk802ii.dts b/sys/gnu/dts/arm/sun4i-a10-mk802ii.dts deleted file mode 100644 index 17dcdf03111..00000000000 --- a/sys/gnu/dts/arm/sun4i-a10-mk802ii.dts +++ /dev/null @@ -1,111 +0,0 @@ -/* - * Copyright 2015 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun4i-a10.dtsi" -#include "sunxi-common-regulators.dtsi" -#include - -/ { - model = "MK802ii"; - compatible = "allwinner,mk802ii", "allwinner,sun4i-a10"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - compatible = "x-powers,axp209"; - reg = <0x34>; - interrupts = <0>; - - interrupt-controller; - #interrupt-cells = <1>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usbphy { - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun4i-a10-olinuxino-lime.dts b/sys/gnu/dts/arm/sun4i-a10-olinuxino-lime.dts deleted file mode 100644 index 845f76824d5..00000000000 --- a/sys/gnu/dts/arm/sun4i-a10-olinuxino-lime.dts +++ /dev/null @@ -1,226 +0,0 @@ -/* - * Copyright 2014 - Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun4i-a10.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include - -/ { - model = "Olimex A10-OLinuXino-LIME"; - compatible = "olimex,a10-olinuxino-lime", "allwinner,sun4i-a10"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_olinuxinolime>; - - green { - label = "a10-olinuxino-lime:green:usr"; - gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; -}; - -&ahci { - target-supply = <®_ahci_5v>; - status = "okay"; -}; - -&cpu0 { - /* - * The A10-Lime is known to be unstable when running at 1008 MHz - */ - operating-points = < - /* kHz uV */ - 912000 1350000 - 864000 1300000 - 624000 1250000 - >; -}; - -&de { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&emac { - phy-handle = <&phy1>; - status = "okay"; -}; - -&emac_sram { - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - compatible = "x-powers,axp209"; - reg = <0x34>; - interrupts = <0>; - - interrupt-controller; - #interrupt-cells = <1>; - }; -}; - -&i2c1 { - status = "okay"; - - eeprom: eeprom@50 { - compatible = "atmel,24c16"; - reg = <0x50>; - pagesize = <16>; - }; -}; - -&mdio { - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pio { - led_pins_olinuxinolime: led-pin { - pins = "PH2"; - function = "gpio_out"; - drive-strength = <20>; - }; -}; - -®_ahci_5v { - gpio = <&pio 2 3 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -®_usb0_vbus { - status = "okay"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ - usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH5 */ - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun4i-a10-pcduino.dts b/sys/gnu/dts/arm/sun4i-a10-pcduino.dts deleted file mode 100644 index 83287b6c975..00000000000 --- a/sys/gnu/dts/arm/sun4i-a10-pcduino.dts +++ /dev/null @@ -1,200 +0,0 @@ -/* - * Copyright 2014 Zoltan HERPAI - * Zoltan HERPAI - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun4i-a10.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include - -/ { - model = "LinkSprite pcDuino"; - compatible = "linksprite,a10-pcduino", "allwinner,sun4i-a10"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - tx { - label = "pcduino:green:tx"; - gpios = <&pio 7 15 GPIO_ACTIVE_LOW>; - }; - - rx { - label = "pcduino:green:rx"; - gpios = <&pio 7 16 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - back { - label = "Key Back"; - linux,code = ; - gpios = <&pio 7 17 GPIO_ACTIVE_LOW>; - }; - - home { - label = "Key Home"; - linux,code = ; - gpios = <&pio 7 18 GPIO_ACTIVE_LOW>; - }; - - menu { - label = "Key Menu"; - linux,code = ; - gpios = <&pio 7 19 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&emac { - phy-handle = <&phy1>; - status = "okay"; -}; - -&emac_sram { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupts = <0>; - }; -}; - -&mdio { - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -#include "axp209.dtsi" - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-int-dll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ - usb1_vbus-supply = <®_vcc5v0>; /* USB1 VBUS is always on */ - usb2_vbus-supply = <®_vcc5v0>; /* USB2 VBUS is always on */ - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun4i-a10-pcduino2.dts b/sys/gnu/dts/arm/sun4i-a10-pcduino2.dts deleted file mode 100644 index bc4f128965e..00000000000 --- a/sys/gnu/dts/arm/sun4i-a10-pcduino2.dts +++ /dev/null @@ -1,67 +0,0 @@ -/* - * Copyright 2015 Siarhei Siamashka - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/* - * The LinkSprite pcDuino2 board is almost identical to the older - * LinkSprite pcDuino1 board. The only software visible difference - * is that the pcDuino2 board got a USB VBUS voltage regulator, which - * is controlled by the PD2 pin (pulled-up by default). Also one of - * the USB host ports has been replaced with a USB WIFI chip. - */ - -#include "sun4i-a10-pcduino.dts" - -/ { - model = "LinkSprite pcDuino2"; - compatible = "linksprite,a10-pcduino2", "allwinner,sun4i-a10"; -}; - -®_usb2_vbus { - gpio = <&pio 3 2 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&usbphy { - usb1_vbus-supply = <®_vcc3v3>; /* USB WIFI is always on */ - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun4i-a10-pov-protab2-ips9.dts b/sys/gnu/dts/arm/sun4i-a10-pov-protab2-ips9.dts deleted file mode 100644 index 24a3d23e195..00000000000 --- a/sys/gnu/dts/arm/sun4i-a10-pov-protab2-ips9.dts +++ /dev/null @@ -1,205 +0,0 @@ -/* - * Copyright 2015 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun4i-a10.dtsi" -#include "sunxi-common-regulators.dtsi" -#include -#include -#include -#include - -/ { - model = "Point of View Protab2-IPS9"; - compatible = "pov,protab2-ips9", "allwinner,sun4i-a10"; - - aliases { - serial0 = &uart0; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; - brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; - default-brightness-level = <8>; - enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */ - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&codec { - allwinner,pa-gpios = <&pio 7 15 GPIO_ACTIVE_HIGH>; /* PH15 */ - status = "okay"; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&ehci0 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupts = <0>; - }; -}; - -#include "axp209.dtsi" - -&i2c1 { - /* pull-ups and devices require AXP209 LDO3 */ - status = "failed"; -}; - -&i2c2 { - status = "okay"; - - touchscreen@5c { - compatible = "pixcir,pixcir_tangoc"; - reg = <0x5c>; - interrupt-parent = <&pio>; - interrupts = <7 21 IRQ_TYPE_EDGE_FALLING>; /* EINT21 (PH21) */ - attb-gpio = <&pio 7 21 GPIO_ACTIVE_HIGH>; /* PH21 */ - enable-gpios = <&pio 0 5 GPIO_ACTIVE_LOW>; - wake-gpios = <&pio 1 13 GPIO_ACTIVE_LOW>; - touchscreen-size-x = <1024>; - touchscreen-size-y = <768>; - touchscreen-inverted-x; - touchscreen-inverted-y; - }; -}; - -&lradc { - vref-supply = <®_ldo2>; - status = "okay"; - - button-400 { - label = "Volume Up"; - linux,code = ; - channel = <0>; - voltage = <400000>; - }; - - button-800 { - label = "Volume Down"; - linux,code = ; - channel = <0>; - voltage = <800000>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pin>; - status = "okay"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1250000>; - regulator-name = "vdd-int-dll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_usb0_vbus { - status = "okay"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ - usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */ - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_usb1_vbus>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun4i-a10.dtsi b/sys/gnu/dts/arm/sun4i-a10.dtsi deleted file mode 100644 index bf531efc061..00000000000 --- a/sys/gnu/dts/arm/sun4i-a10.dtsi +++ /dev/null @@ -1,1272 +0,0 @@ -/* - * Copyright 2012 Stefan Roese - * Stefan Roese - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&intc>; - - aliases { - ethernet0 = &emac; - }; - - chosen { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - framebuffer-lcd0-hdmi { - compatible = "allwinner,simple-framebuffer", - "simple-framebuffer"; - allwinner,pipeline = "de_be0-lcd0-hdmi"; - clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>, - <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>, - <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_DE_BE0>; - status = "disabled"; - }; - - framebuffer-fe0-lcd0-hdmi { - compatible = "allwinner,simple-framebuffer", - "simple-framebuffer"; - allwinner,pipeline = "de_fe0-de_be0-lcd0-hdmi"; - clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>, - <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_AHB_DE_FE0>, - <&ccu CLK_DE_BE0>, <&ccu CLK_DE_FE0>, - <&ccu CLK_TCON0_CH1>, <&ccu CLK_HDMI>, - <&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>; - status = "disabled"; - }; - - framebuffer-fe0-lcd0 { - compatible = "allwinner,simple-framebuffer", - "simple-framebuffer"; - allwinner,pipeline = "de_fe0-de_be0-lcd0"; - clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_DE_BE0>, - <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_BE0>, - <&ccu CLK_DE_FE0>, <&ccu CLK_TCON0_CH0>, - <&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>; - status = "disabled"; - }; - - framebuffer-fe0-lcd0-tve0 { - compatible = "allwinner,simple-framebuffer", - "simple-framebuffer"; - allwinner,pipeline = "de_fe0-de_be0-lcd0-tve0"; - clocks = <&ccu CLK_AHB_TVE0>, <&ccu CLK_AHB_LCD0>, - <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_AHB_DE_FE0>, - <&ccu CLK_DE_BE0>, <&ccu CLK_DE_FE0>, - <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_TVE0>, - <&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>; - status = "disabled"; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a8"; - reg = <0x0>; - clocks = <&ccu CLK_CPU>; - clock-latency = <244144>; /* 8 32k periods */ - operating-points = < - /* kHz uV */ - 1008000 1400000 - 912000 1350000 - 864000 1300000 - 624000 1250000 - >; - #cooling-cells = <2>; - }; - }; - - thermal-zones { - cpu-thermal { - /* milliseconds */ - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&rtp>; - - cooling-maps { - map0 { - trip = <&cpu_alert0>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - - trips { - cpu_alert0: cpu-alert0 { - /* milliCelsius */ - temperature = <850000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu_crit: cpu-crit { - /* milliCelsius */ - temperature = <100000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - }; - - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - osc24M: clk-24M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "osc24M"; - }; - - osc32k: clk-32k { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - clock-output-names = "osc32k"; - }; - }; - - de: display-engine { - compatible = "allwinner,sun4i-a10-display-engine"; - allwinner,pipelines = <&fe0>, <&fe1>; - status = "disabled"; - }; - - pmu { - compatible = "arm,cortex-a8-pmu"; - interrupts = <3>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - /* Address must be kept in the lower 256 MiBs of DRAM for VE. */ - default-pool { - compatible = "shared-dma-pool"; - size = <0x6000000>; - alloc-ranges = <0x4a000000 0x6000000>; - reusable; - linux,cma-default; - }; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - system-control@1c00000 { - compatible = "allwinner,sun4i-a10-system-control"; - reg = <0x01c00000 0x30>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - sram_a: sram@0 { - compatible = "mmio-sram"; - reg = <0x00000000 0xc000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x00000000 0xc000>; - - emac_sram: sram-section@8000 { - compatible = "allwinner,sun4i-a10-sram-a3-a4"; - reg = <0x8000 0x4000>; - status = "disabled"; - }; - }; - - sram_d: sram@10000 { - compatible = "mmio-sram"; - reg = <0x00010000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x00010000 0x1000>; - - otg_sram: sram-section@0 { - compatible = "allwinner,sun4i-a10-sram-d"; - reg = <0x0000 0x1000>; - status = "disabled"; - }; - }; - - sram_c: sram@1d00000 { - compatible = "mmio-sram"; - reg = <0x01d00000 0xd0000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x01d00000 0xd0000>; - - ve_sram: sram-section@0 { - compatible = "allwinner,sun4i-a10-sram-c1"; - reg = <0x000000 0x80000>; - }; - }; - }; - - dma: dma-controller@1c02000 { - compatible = "allwinner,sun4i-a10-dma"; - reg = <0x01c02000 0x1000>; - interrupts = <27>; - clocks = <&ccu CLK_AHB_DMA>; - #dma-cells = <2>; - }; - - nfc: nand-controller@1c03000 { - compatible = "allwinner,sun4i-a10-nand"; - reg = <0x01c03000 0x1000>; - interrupts = <37>; - clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>; - clock-names = "ahb", "mod"; - dmas = <&dma SUN4I_DMA_DEDICATED 3>; - dma-names = "rxtx"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - spi0: spi@1c05000 { - compatible = "allwinner,sun4i-a10-spi"; - reg = <0x01c05000 0x1000>; - interrupts = <10>; - clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>; - clock-names = "ahb", "mod"; - dmas = <&dma SUN4I_DMA_DEDICATED 27>, - <&dma SUN4I_DMA_DEDICATED 26>; - dma-names = "rx", "tx"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - spi1: spi@1c06000 { - compatible = "allwinner,sun4i-a10-spi"; - reg = <0x01c06000 0x1000>; - interrupts = <11>; - clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>; - clock-names = "ahb", "mod"; - dmas = <&dma SUN4I_DMA_DEDICATED 9>, - <&dma SUN4I_DMA_DEDICATED 8>; - dma-names = "rx", "tx"; - pinctrl-names = "default"; - pinctrl-0 = <&spi1_pins>, <&spi1_cs0_pin>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - emac: ethernet@1c0b000 { - compatible = "allwinner,sun4i-a10-emac"; - reg = <0x01c0b000 0x1000>; - interrupts = <55>; - clocks = <&ccu CLK_AHB_EMAC>; - allwinner,sram = <&emac_sram 1>; - pinctrl-names = "default"; - pinctrl-0 = <&emac_pins>; - status = "disabled"; - }; - - mdio: mdio@1c0b080 { - compatible = "allwinner,sun4i-a10-mdio"; - reg = <0x01c0b080 0x14>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - tcon0: lcd-controller@1c0c000 { - compatible = "allwinner,sun4i-a10-tcon"; - reg = <0x01c0c000 0x1000>; - interrupts = <44>; - resets = <&ccu RST_TCON0>; - reset-names = "lcd"; - clocks = <&ccu CLK_AHB_LCD0>, - <&ccu CLK_TCON0_CH0>, - <&ccu CLK_TCON0_CH1>; - clock-names = "ahb", - "tcon-ch0", - "tcon-ch1"; - clock-output-names = "tcon0-pixel-clock"; - #clock-cells = <0>; - dmas = <&dma SUN4I_DMA_DEDICATED 14>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - tcon0_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - tcon0_in_be0: endpoint@0 { - reg = <0>; - remote-endpoint = <&be0_out_tcon0>; - }; - - tcon0_in_be1: endpoint@1 { - reg = <1>; - remote-endpoint = <&be1_out_tcon0>; - }; - }; - - tcon0_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - tcon0_out_hdmi: endpoint@1 { - reg = <1>; - remote-endpoint = <&hdmi_in_tcon0>; - allwinner,tcon-channel = <1>; - }; - }; - }; - }; - - tcon1: lcd-controller@1c0d000 { - compatible = "allwinner,sun4i-a10-tcon"; - reg = <0x01c0d000 0x1000>; - interrupts = <45>; - resets = <&ccu RST_TCON1>; - reset-names = "lcd"; - clocks = <&ccu CLK_AHB_LCD1>, - <&ccu CLK_TCON1_CH0>, - <&ccu CLK_TCON1_CH1>; - clock-names = "ahb", - "tcon-ch0", - "tcon-ch1"; - clock-output-names = "tcon1-pixel-clock"; - #clock-cells = <0>; - dmas = <&dma SUN4I_DMA_DEDICATED 15>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - tcon1_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - tcon1_in_be0: endpoint@0 { - reg = <0>; - remote-endpoint = <&be0_out_tcon1>; - }; - - tcon1_in_be1: endpoint@1 { - reg = <1>; - remote-endpoint = <&be1_out_tcon1>; - }; - }; - - tcon1_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - tcon1_out_hdmi: endpoint@1 { - reg = <1>; - remote-endpoint = <&hdmi_in_tcon1>; - allwinner,tcon-channel = <1>; - }; - }; - }; - }; - - video-codec@1c0e000 { - compatible = "allwinner,sun4i-a10-video-engine"; - reg = <0x01c0e000 0x1000>; - clocks = <&ccu CLK_AHB_VE>, <&ccu CLK_VE>, - <&ccu CLK_DRAM_VE>; - clock-names = "ahb", "mod", "ram"; - resets = <&ccu RST_VE>; - interrupts = <53>; - allwinner,sram = <&ve_sram 1>; - }; - - mmc0: mmc@1c0f000 { - compatible = "allwinner,sun4i-a10-mmc"; - reg = <0x01c0f000 0x1000>; - clocks = <&ccu CLK_AHB_MMC0>, <&ccu CLK_MMC0>; - clock-names = "ahb", "mmc"; - interrupts = <32>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc1: mmc@1c10000 { - compatible = "allwinner,sun4i-a10-mmc"; - reg = <0x01c10000 0x1000>; - clocks = <&ccu CLK_AHB_MMC1>, <&ccu CLK_MMC1>; - clock-names = "ahb", "mmc"; - interrupts = <33>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc2: mmc@1c11000 { - compatible = "allwinner,sun4i-a10-mmc"; - reg = <0x01c11000 0x1000>; - clocks = <&ccu CLK_AHB_MMC2>, <&ccu CLK_MMC2>; - clock-names = "ahb", "mmc"; - interrupts = <34>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc3: mmc@1c12000 { - compatible = "allwinner,sun4i-a10-mmc"; - reg = <0x01c12000 0x1000>; - clocks = <&ccu CLK_AHB_MMC3>, <&ccu CLK_MMC3>; - clock-names = "ahb", "mmc"; - interrupts = <35>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - usb_otg: usb@1c13000 { - compatible = "allwinner,sun4i-a10-musb"; - reg = <0x01c13000 0x0400>; - clocks = <&ccu CLK_AHB_OTG>; - interrupts = <38>; - interrupt-names = "mc"; - phys = <&usbphy 0>; - phy-names = "usb"; - extcon = <&usbphy 0>; - allwinner,sram = <&otg_sram 1>; - dr_mode = "otg"; - status = "disabled"; - }; - - usbphy: phy@1c13400 { - #phy-cells = <1>; - compatible = "allwinner,sun4i-a10-usb-phy"; - reg = <0x01c13400 0x10>, <0x01c14800 0x4>, <0x01c1c800 0x4>; - reg-names = "phy_ctrl", "pmu1", "pmu2"; - clocks = <&ccu CLK_USB_PHY>; - clock-names = "usb_phy"; - resets = <&ccu RST_USB_PHY0>, - <&ccu RST_USB_PHY1>, - <&ccu RST_USB_PHY2>; - reset-names = "usb0_reset", "usb1_reset", "usb2_reset"; - status = "disabled"; - }; - - ehci0: usb@1c14000 { - compatible = "allwinner,sun4i-a10-ehci", "generic-ehci"; - reg = <0x01c14000 0x100>; - interrupts = <39>; - clocks = <&ccu CLK_AHB_EHCI0>; - phys = <&usbphy 1>; - phy-names = "usb"; - status = "disabled"; - }; - - ohci0: usb@1c14400 { - compatible = "allwinner,sun4i-a10-ohci", "generic-ohci"; - reg = <0x01c14400 0x100>; - interrupts = <64>; - clocks = <&ccu CLK_USB_OHCI0>, <&ccu CLK_AHB_OHCI0>; - phys = <&usbphy 1>; - phy-names = "usb"; - status = "disabled"; - }; - - crypto: crypto-engine@1c15000 { - compatible = "allwinner,sun4i-a10-crypto"; - reg = <0x01c15000 0x1000>; - interrupts = <86>; - clocks = <&ccu CLK_AHB_SS>, <&ccu CLK_SS>; - clock-names = "ahb", "mod"; - }; - - hdmi: hdmi@1c16000 { - compatible = "allwinner,sun4i-a10-hdmi"; - reg = <0x01c16000 0x1000>; - interrupts = <58>; - clocks = <&ccu CLK_AHB_HDMI0>, <&ccu CLK_HDMI>, - <&ccu CLK_PLL_VIDEO0_2X>, - <&ccu CLK_PLL_VIDEO1_2X>; - clock-names = "ahb", "mod", "pll-0", "pll-1"; - dmas = <&dma SUN4I_DMA_NORMAL 16>, - <&dma SUN4I_DMA_NORMAL 16>, - <&dma SUN4I_DMA_DEDICATED 24>; - dma-names = "ddc-tx", "ddc-rx", "audio-tx"; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - hdmi_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - hdmi_in_tcon0: endpoint@0 { - reg = <0>; - remote-endpoint = <&tcon0_out_hdmi>; - }; - - hdmi_in_tcon1: endpoint@1 { - reg = <1>; - remote-endpoint = <&tcon1_out_hdmi>; - }; - }; - - hdmi_out: port@1 { - reg = <1>; - }; - }; - }; - - spi2: spi@1c17000 { - compatible = "allwinner,sun4i-a10-spi"; - reg = <0x01c17000 0x1000>; - interrupts = <12>; - clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>; - clock-names = "ahb", "mod"; - dmas = <&dma SUN4I_DMA_DEDICATED 29>, - <&dma SUN4I_DMA_DEDICATED 28>; - dma-names = "rx", "tx"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - ahci: sata@1c18000 { - compatible = "allwinner,sun4i-a10-ahci"; - reg = <0x01c18000 0x1000>; - interrupts = <56>; - clocks = <&ccu CLK_AHB_SATA>, <&ccu CLK_SATA>; - status = "disabled"; - }; - - ehci1: usb@1c1c000 { - compatible = "allwinner,sun4i-a10-ehci", "generic-ehci"; - reg = <0x01c1c000 0x100>; - interrupts = <40>; - clocks = <&ccu CLK_AHB_EHCI1>; - phys = <&usbphy 2>; - phy-names = "usb"; - status = "disabled"; - }; - - ohci1: usb@1c1c400 { - compatible = "allwinner,sun4i-a10-ohci", "generic-ohci"; - reg = <0x01c1c400 0x100>; - interrupts = <65>; - clocks = <&ccu CLK_USB_OHCI1>, <&ccu CLK_AHB_OHCI1>; - phys = <&usbphy 2>; - phy-names = "usb"; - status = "disabled"; - }; - - csi1: csi@1c1d000 { - compatible = "allwinner,sun4i-a10-csi1"; - reg = <0x01c1d000 0x1000>; - interrupts = <43>; - clocks = <&ccu CLK_AHB_CSI1>, <&ccu CLK_DRAM_CSI1>; - clock-names = "bus", "ram"; - resets = <&ccu RST_CSI1>; - status = "disabled"; - }; - - spi3: spi@1c1f000 { - compatible = "allwinner,sun4i-a10-spi"; - reg = <0x01c1f000 0x1000>; - interrupts = <50>; - clocks = <&ccu CLK_AHB_SPI3>, <&ccu CLK_SPI3>; - clock-names = "ahb", "mod"; - dmas = <&dma SUN4I_DMA_DEDICATED 31>, - <&dma SUN4I_DMA_DEDICATED 30>; - dma-names = "rx", "tx"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - ccu: clock@1c20000 { - compatible = "allwinner,sun4i-a10-ccu"; - reg = <0x01c20000 0x400>; - clocks = <&osc24M>, <&osc32k>; - clock-names = "hosc", "losc"; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - intc: interrupt-controller@1c20400 { - compatible = "allwinner,sun4i-a10-ic"; - reg = <0x01c20400 0x400>; - interrupt-controller; - #interrupt-cells = <1>; - }; - - pio: pinctrl@1c20800 { - compatible = "allwinner,sun4i-a10-pinctrl"; - reg = <0x01c20800 0x400>; - interrupts = <28>; - clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>; - clock-names = "apb", "hosc", "losc"; - gpio-controller; - interrupt-controller; - #interrupt-cells = <3>; - #gpio-cells = <3>; - - can0_ph_pins: can0-ph-pins { - pins = "PH20", "PH21"; - function = "can"; - }; - - /omit-if-no-ref/ - csi1_8bits_pg_pins: csi1-8bits-pg-pins { - pins = "PG0", "PG2", "PG3", "PG4", "PG5", - "PG6", "PG7", "PG8", "PG9", "PG10", - "PG11"; - function = "csi1"; - }; - - /omit-if-no-ref/ - csi1_24bits_ph_pins: csi1-24bits-ph-pins { - pins = "PH0", "PH1", "PH2", "PH3", "PH4", - "PH5", "PH6", "PH7", "PH8", "PH9", - "PH10", "PH11", "PH12", "PH13", "PH14", - "PH15", "PH16", "PH17", "PH18", "PH19", - "PH20", "PH21", "PH22", "PH23", "PH24", - "PH25", "PH26", "PH27"; - function = "csi1"; - }; - - /omit-if-no-ref/ - csi1_clk_pg_pin: csi1-clk-pg-pin { - pins = "PG1"; - function = "csi1"; - }; - - emac_pins: emac0-pins { - pins = "PA0", "PA1", "PA2", - "PA3", "PA4", "PA5", "PA6", - "PA7", "PA8", "PA9", "PA10", - "PA11", "PA12", "PA13", "PA14", - "PA15", "PA16"; - function = "emac"; - }; - - i2c0_pins: i2c0-pins { - pins = "PB0", "PB1"; - function = "i2c0"; - }; - - i2c1_pins: i2c1-pins { - pins = "PB18", "PB19"; - function = "i2c1"; - }; - - i2c2_pins: i2c2-pins { - pins = "PB20", "PB21"; - function = "i2c2"; - }; - - ir0_rx_pins: ir0-rx-pin { - pins = "PB4"; - function = "ir0"; - }; - - ir0_tx_pins: ir0-tx-pin { - pins = "PB3"; - function = "ir0"; - }; - - ir1_rx_pins: ir1-rx-pin { - pins = "PB23"; - function = "ir1"; - }; - - ir1_tx_pins: ir1-tx-pin { - pins = "PB22"; - function = "ir1"; - }; - - mmc0_pins: mmc0-pins { - pins = "PF0", "PF1", "PF2", - "PF3", "PF4", "PF5"; - function = "mmc0"; - drive-strength = <30>; - bias-pull-up; - }; - - ps2_ch0_pins: ps2-ch0-pins { - pins = "PI20", "PI21"; - function = "ps2"; - }; - - ps2_ch1_ph_pins: ps2-ch1-ph-pins { - pins = "PH12", "PH13"; - function = "ps2"; - }; - - pwm0_pin: pwm0-pin { - pins = "PB2"; - function = "pwm"; - }; - - pwm1_pin: pwm1-pin { - pins = "PI3"; - function = "pwm"; - }; - - spdif_tx_pin: spdif-tx-pin { - pins = "PB13"; - function = "spdif"; - bias-pull-up; - }; - - spi0_pi_pins: spi0-pi-pins { - pins = "PI11", "PI12", "PI13"; - function = "spi0"; - }; - - spi0_cs0_pi_pin: spi0-cs0-pi-pin { - pins = "PI10"; - function = "spi0"; - }; - - spi1_pins: spi1-pins { - pins = "PI17", "PI18", "PI19"; - function = "spi1"; - }; - - spi1_cs0_pin: spi1-cs0-pin { - pins = "PI16"; - function = "spi1"; - }; - - spi2_pb_pins: spi2-pb-pins { - pins = "PB15", "PB16", "PB17"; - function = "spi2"; - }; - - spi2_pc_pins: spi2-pc-pins { - pins = "PC20", "PC21", "PC22"; - function = "spi2"; - }; - - spi2_cs0_pb_pin: spi2-cs0-pb-pin { - pins = "PB14"; - function = "spi2"; - }; - - spi2_cs0_pc_pins: spi2-cs0-pc-pin { - pins = "PC19"; - function = "spi2"; - }; - - uart0_pb_pins: uart0-pb-pins { - pins = "PB22", "PB23"; - function = "uart0"; - }; - - uart0_pf_pins: uart0-pf-pins { - pins = "PF2", "PF4"; - function = "uart0"; - }; - - uart1_pins: uart1-pins { - pins = "PA10", "PA11"; - function = "uart1"; - }; - }; - - timer@1c20c00 { - compatible = "allwinner,sun4i-a10-timer"; - reg = <0x01c20c00 0x90>; - interrupts = <22>, - <23>, - <24>, - <25>, - <67>, - <68>; - clocks = <&osc24M>; - }; - - wdt: watchdog@1c20c90 { - compatible = "allwinner,sun4i-a10-wdt"; - reg = <0x01c20c90 0x10>; - interrupts = <24>; - clocks = <&osc24M>; - }; - - rtc: rtc@1c20d00 { - compatible = "allwinner,sun4i-a10-rtc"; - reg = <0x01c20d00 0x20>; - interrupts = <24>; - }; - - pwm: pwm@1c20e00 { - compatible = "allwinner,sun4i-a10-pwm"; - reg = <0x01c20e00 0xc>; - clocks = <&osc24M>; - #pwm-cells = <3>; - status = "disabled"; - }; - - spdif: spdif@1c21000 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun4i-a10-spdif"; - reg = <0x01c21000 0x400>; - interrupts = <13>; - clocks = <&ccu CLK_APB0_SPDIF>, <&ccu CLK_SPDIF>; - clock-names = "apb", "spdif"; - dmas = <&dma SUN4I_DMA_NORMAL 2>, - <&dma SUN4I_DMA_NORMAL 2>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - ir0: ir@1c21800 { - compatible = "allwinner,sun4i-a10-ir"; - clocks = <&ccu CLK_APB0_IR0>, <&ccu CLK_IR0>; - clock-names = "apb", "ir"; - interrupts = <5>; - reg = <0x01c21800 0x40>; - status = "disabled"; - }; - - ir1: ir@1c21c00 { - compatible = "allwinner,sun4i-a10-ir"; - clocks = <&ccu CLK_APB0_IR1>, <&ccu CLK_IR1>; - clock-names = "apb", "ir"; - interrupts = <6>; - reg = <0x01c21c00 0x40>; - status = "disabled"; - }; - - i2s0: i2s@1c22400 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun4i-a10-i2s"; - reg = <0x01c22400 0x400>; - interrupts = <16>; - clocks = <&ccu CLK_APB0_I2S0>, <&ccu CLK_I2S0>; - clock-names = "apb", "mod"; - dmas = <&dma SUN4I_DMA_NORMAL 3>, - <&dma SUN4I_DMA_NORMAL 3>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - lradc: lradc@1c22800 { - compatible = "allwinner,sun4i-a10-lradc-keys"; - reg = <0x01c22800 0x100>; - interrupts = <31>; - status = "disabled"; - }; - - codec: codec@1c22c00 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun4i-a10-codec"; - reg = <0x01c22c00 0x40>; - interrupts = <30>; - clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>; - clock-names = "apb", "codec"; - dmas = <&dma SUN4I_DMA_NORMAL 19>, - <&dma SUN4I_DMA_NORMAL 19>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - sid: eeprom@1c23800 { - compatible = "allwinner,sun4i-a10-sid"; - reg = <0x01c23800 0x10>; - }; - - rtp: rtp@1c25000 { - compatible = "allwinner,sun4i-a10-ts"; - reg = <0x01c25000 0x100>; - interrupts = <29>; - #thermal-sensor-cells = <0>; - }; - - uart0: serial@1c28000 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28000 0x400>; - interrupts = <1>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_APB1_UART0>; - status = "disabled"; - }; - - uart1: serial@1c28400 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28400 0x400>; - interrupts = <2>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_APB1_UART1>; - status = "disabled"; - }; - - uart2: serial@1c28800 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28800 0x400>; - interrupts = <3>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_APB1_UART2>; - status = "disabled"; - }; - - uart3: serial@1c28c00 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28c00 0x400>; - interrupts = <4>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_APB1_UART3>; - status = "disabled"; - }; - - uart4: serial@1c29000 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c29000 0x400>; - interrupts = <17>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_APB1_UART4>; - status = "disabled"; - }; - - uart5: serial@1c29400 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c29400 0x400>; - interrupts = <18>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_APB1_UART5>; - status = "disabled"; - }; - - uart6: serial@1c29800 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c29800 0x400>; - interrupts = <19>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_APB1_UART6>; - status = "disabled"; - }; - - uart7: serial@1c29c00 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c29c00 0x400>; - interrupts = <20>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_APB1_UART7>; - status = "disabled"; - }; - - ps20: ps2@1c2a000 { - compatible = "allwinner,sun4i-a10-ps2"; - reg = <0x01c2a000 0x400>; - interrupts = <62>; - clocks = <&ccu CLK_APB1_PS20>; - status = "disabled"; - }; - - ps21: ps2@1c2a400 { - compatible = "allwinner,sun4i-a10-ps2"; - reg = <0x01c2a400 0x400>; - interrupts = <63>; - clocks = <&ccu CLK_APB1_PS21>; - status = "disabled"; - }; - - i2c0: i2c@1c2ac00 { - compatible = "allwinner,sun4i-a10-i2c"; - reg = <0x01c2ac00 0x400>; - interrupts = <7>; - clocks = <&ccu CLK_APB1_I2C0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c1: i2c@1c2b000 { - compatible = "allwinner,sun4i-a10-i2c"; - reg = <0x01c2b000 0x400>; - interrupts = <8>; - clocks = <&ccu CLK_APB1_I2C1>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c2: i2c@1c2b400 { - compatible = "allwinner,sun4i-a10-i2c"; - reg = <0x01c2b400 0x400>; - interrupts = <9>; - clocks = <&ccu CLK_APB1_I2C2>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - can0: can@1c2bc00 { - compatible = "allwinner,sun4i-a10-can"; - reg = <0x01c2bc00 0x400>; - interrupts = <26>; - clocks = <&ccu CLK_APB1_CAN>; - status = "disabled"; - }; - - mali: gpu@1c40000 { - compatible = "allwinner,sun4i-a10-mali", "arm,mali-400"; - reg = <0x01c40000 0x10000>; - interrupts = <69>, - <70>, - <71>, - <72>, - <73>; - interrupt-names = "gp", - "gpmmu", - "pp0", - "ppmmu0", - "pmu"; - clocks = <&ccu CLK_AHB_GPU>, <&ccu CLK_GPU>; - clock-names = "bus", "core"; - resets = <&ccu RST_GPU>; - - assigned-clocks = <&ccu CLK_GPU>; - assigned-clock-rates = <384000000>; - }; - - fe0: display-frontend@1e00000 { - compatible = "allwinner,sun4i-a10-display-frontend"; - reg = <0x01e00000 0x20000>; - interrupts = <47>; - clocks = <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_FE0>, - <&ccu CLK_DRAM_DE_FE0>; - clock-names = "ahb", "mod", - "ram"; - resets = <&ccu RST_DE_FE0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - fe0_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - fe0_out_be0: endpoint@0 { - reg = <0>; - remote-endpoint = <&be0_in_fe0>; - }; - - fe0_out_be1: endpoint@1 { - reg = <1>; - remote-endpoint = <&be1_in_fe0>; - }; - }; - }; - }; - - fe1: display-frontend@1e20000 { - compatible = "allwinner,sun4i-a10-display-frontend"; - reg = <0x01e20000 0x20000>; - interrupts = <48>; - clocks = <&ccu CLK_AHB_DE_FE1>, <&ccu CLK_DE_FE1>, - <&ccu CLK_DRAM_DE_FE1>; - clock-names = "ahb", "mod", - "ram"; - resets = <&ccu RST_DE_FE1>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - fe1_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - fe1_out_be0: endpoint@0 { - reg = <0>; - remote-endpoint = <&be0_in_fe1>; - }; - - fe1_out_be1: endpoint@1 { - reg = <1>; - remote-endpoint = <&be1_in_fe1>; - }; - }; - }; - }; - - be1: display-backend@1e40000 { - compatible = "allwinner,sun4i-a10-display-backend"; - reg = <0x01e40000 0x10000>; - interrupts = <48>; - clocks = <&ccu CLK_AHB_DE_BE1>, <&ccu CLK_DE_BE1>, - <&ccu CLK_DRAM_DE_BE1>; - clock-names = "ahb", "mod", - "ram"; - resets = <&ccu RST_DE_BE1>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - be1_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - be1_in_fe0: endpoint@0 { - reg = <0>; - remote-endpoint = <&fe0_out_be1>; - }; - - be1_in_fe1: endpoint@1 { - reg = <1>; - remote-endpoint = <&fe1_out_be1>; - }; - }; - - be1_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - be1_out_tcon0: endpoint@0 { - reg = <0>; - remote-endpoint = <&tcon0_in_be1>; - }; - - be1_out_tcon1: endpoint@1 { - reg = <1>; - remote-endpoint = <&tcon1_in_be1>; - }; - }; - }; - }; - - be0: display-backend@1e60000 { - compatible = "allwinner,sun4i-a10-display-backend"; - reg = <0x01e60000 0x10000>; - interrupts = <47>; - clocks = <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>, - <&ccu CLK_DRAM_DE_BE0>; - clock-names = "ahb", "mod", - "ram"; - resets = <&ccu RST_DE_BE0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - be0_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - be0_in_fe0: endpoint@0 { - reg = <0>; - remote-endpoint = <&fe0_out_be0>; - }; - - be0_in_fe1: endpoint@1 { - reg = <1>; - remote-endpoint = <&fe1_out_be0>; - }; - }; - - be0_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - be0_out_tcon0: endpoint@0 { - reg = <0>; - remote-endpoint = <&tcon0_in_be0>; - }; - - be0_out_tcon1: endpoint@1 { - reg = <1>; - remote-endpoint = <&tcon1_in_be0>; - }; - }; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/sun5i-a10s-auxtek-t003.dts b/sys/gnu/dts/arm/sun5i-a10s-auxtek-t003.dts deleted file mode 100644 index 64d50fcfcd3..00000000000 --- a/sys/gnu/dts/arm/sun5i-a10s-auxtek-t003.dts +++ /dev/null @@ -1,137 +0,0 @@ -/* - * Copyright 2015 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun5i-a10s.dtsi" -#include "sunxi-common-regulators.dtsi" -#include - -/ { - model = "Auxtek t003 A10s hdmi tv-stick"; - compatible = "allwinner,auxtek-t003", "allwinner,sun5i-a10s"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_t003>; - - red { - label = "t003-tv-dongle:red:usr"; - gpios = <&pio 1 2 GPIO_ACTIVE_HIGH>; /* PB2 */ - default-state = "on"; - }; - }; -}; - -&ehci0 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp152: pmic@30 { - compatible = "x-powers,axp152"; - reg = <0x30>; - interrupts = <0>; - interrupt-controller; - #interrupt-cells = <1>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 6 1 GPIO_ACTIVE_LOW>; /* PG1 */ - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pio { - led_pins_t003: led-pin { - pins = "PB2"; - function = "gpio_out"; - drive-strength = <20>; - }; -}; - -®_usb0_vbus { - gpio = <&pio 6 13 GPIO_ACTIVE_HIGH>; /* PG13 */ - status = "okay"; -}; - -®_usb1_vbus { - gpio = <&pio 1 10 GPIO_ACTIVE_HIGH>; /* PB10 */ - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "host"; - status = "okay"; -}; - -&usbphy { - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_usb1_vbus>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun5i-a10s-auxtek-t004.dts b/sys/gnu/dts/arm/sun5i-a10s-auxtek-t004.dts deleted file mode 100644 index 8af0eae2ddc..00000000000 --- a/sys/gnu/dts/arm/sun5i-a10s-auxtek-t004.dts +++ /dev/null @@ -1,149 +0,0 @@ -/* - * Copyright 2015 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun5i-a10s.dtsi" -#include "sunxi-common-regulators.dtsi" -#include - -/ { - model = "Auxtek t004 A10s hdmi tv-stick"; - compatible = "allwinner,auxtek-t004", "allwinner,sun5i-a10s"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_t004>; - - red { - label = "t004-tv-dongle:red:usr"; - gpios = <&pio 1 2 GPIO_ACTIVE_HIGH>; /* PB2 */ - default-state = "on"; - }; - }; - - reg_vmmc1: vmmc1 { - compatible = "regulator-fixed"; - regulator-name = "vmmc1"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpio = <&pio 1 18 GPIO_ACTIVE_HIGH>; /* PB18 */ - }; -}; - -&ehci0 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp152: pmic@30 { - compatible = "x-powers,axp152"; - reg = <0x30>; - interrupts = <0>; - interrupt-controller; - #interrupt-cells = <1>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 6 1 GPIO_ACTIVE_LOW>; /* PG1 */ - status = "okay"; -}; - -&mmc1 { - vmmc-supply = <®_vmmc1>; - bus-width = <4>; - non-removable; - cap-sdio-irq; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pio { - led_pins_t004: led-pin { - pins = "PB2"; - function = "gpio_out"; - drive-strength = <20>; - }; -}; - -®_usb1_vbus { - gpio = <&pio 6 13 GPIO_ACTIVE_HIGH>; /* PG13 */ - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 6 12 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PG12 */ - usb1_vbus-supply = <®_usb1_vbus>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun5i-a10s-mk802.dts b/sys/gnu/dts/arm/sun5i-a10s-mk802.dts deleted file mode 100644 index 6e90ccb267a..00000000000 --- a/sys/gnu/dts/arm/sun5i-a10s-mk802.dts +++ /dev/null @@ -1,127 +0,0 @@ -/* - * Copyright 2015 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun5i-a10s.dtsi" -#include "sunxi-common-regulators.dtsi" -#include - -/ { - model = "MK802-A10s"; - compatible = "allwinner,a10s-mk802", "allwinner,sun5i-a10s"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - red { - label = "mk802:red:usr"; - gpios = <&pio 1 2 GPIO_ACTIVE_HIGH>; /* PB2 */ - }; - }; -}; - -&ehci0 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp152: pmic@30 { - compatible = "x-powers,axp152"; - reg = <0x30>; - interrupts = <0>; - interrupt-controller; - #interrupt-cells = <1>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 6 1 GPIO_ACTIVE_LOW>; /* PG1 */ - status = "okay"; -}; - -&mmc1 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - non-removable; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -®_usb1_vbus { - gpio = <&pio 1 10 GPIO_ACTIVE_HIGH>; /* PB10 */ - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "peripheral"; - status = "okay"; -}; - -&usbphy { - usb1_vbus-supply = <®_usb1_vbus>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun5i-a10s-olinuxino-micro.dts b/sys/gnu/dts/arm/sun5i-a10s-olinuxino-micro.dts deleted file mode 100644 index d6bb82c295f..00000000000 --- a/sys/gnu/dts/arm/sun5i-a10s-olinuxino-micro.dts +++ /dev/null @@ -1,272 +0,0 @@ -/* - * Copyright 2013 Maxime Ripard - * - * Maxime Ripard - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun5i-a10s.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include - -/ { - model = "Olimex A10s-Olinuxino Micro"; - compatible = "olimex,a10s-olinuxino-micro", "allwinner,sun5i-a10s"; - - aliases { - serial0 = &uart0; - serial1 = &uart2; - serial2 = &uart3; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_olinuxino>; - - green { - label = "a10s-olinuxino-micro:green:usr"; - gpios = <&pio 4 3 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; -}; - -&be0 { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&emac { - pinctrl-names = "default"; - pinctrl-0 = <&emac_pa_pins>; - phy-handle = <&phy1>; - status = "okay"; -}; - -&emac_sram { - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&i2c0 { - status = "okay"; - - axp152: pmic@30 { - reg = <0x30>; - interrupts = <0>; - }; -}; - -#include "axp152.dtsi" - -&i2c1 { - status = "okay"; - - eeprom@50 { - compatible = "atmel,24c16"; - pagesize = <16>; - reg = <0x50>; - read-only; - }; -}; - -&i2c2 { - status = "okay"; -}; - -&lradc { - vref-supply = <®_vcc3v0>; - status = "okay"; - - button-191 { - label = "Volume Up"; - linux,code = ; - channel = <0>; - voltage = <191274>; - }; - - button-392 { - label = "Volume Down"; - linux,code = ; - channel = <0>; - voltage = <392644>; - }; - - button-601 { - label = "Menu"; - linux,code = ; - channel = <0>; - voltage = <601151>; - }; - - button-795 { - label = "Enter"; - linux,code = ; - channel = <0>; - voltage = <795090>; - }; - - button-987 { - label = "Home"; - linux,code = ; - channel = <0>; - voltage = <987387>; - }; -}; - -&mdio { - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 6 1 GPIO_ACTIVE_LOW>; /* PG1 */ - status = "okay"; -}; - -&mmc1 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 6 13 GPIO_ACTIVE_LOW>; /* PG13 */ - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pio { - led_pins_olinuxino: led-pin { - pins = "PE3"; - function = "gpio_out"; - drive-strength = <20>; - }; -}; - -®_usb0_vbus { - gpio = <&pio 6 11 GPIO_ACTIVE_HIGH>; /* PG11 */ - status = "okay"; -}; - -®_usb1_vbus { - gpio = <&pio 1 10 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&spi2 { - pinctrl-names = "default"; - pinctrl-0 = <&spi2_pb_pins>, - <&spi2_cs0_pb_pin>; - status = "okay"; -}; - -&tcon0 { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pc_pins>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pg_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 6 12 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PG12 */ - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_usb1_vbus>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun5i-a10s-r7-tv-dongle.dts b/sys/gnu/dts/arm/sun5i-a10s-r7-tv-dongle.dts deleted file mode 100644 index b2a49a216eb..00000000000 --- a/sys/gnu/dts/arm/sun5i-a10s-r7-tv-dongle.dts +++ /dev/null @@ -1,118 +0,0 @@ -/* - * Copyright 2014 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun5i-a10s.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include - -/ { - model = "R7 A10s hdmi tv-stick"; - compatible = "allwinner,r7-tv-dongle", "allwinner,sun5i-a10s"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_r7>; - - green { - label = "r7-tv-dongle:green:usr"; - gpios = <&pio 1 2 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; -}; - -&ehci0 { - status = "okay"; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 6 1 GPIO_ACTIVE_LOW>; /* PG1 */ - status = "okay"; -}; - -&mmc1 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - non-removable; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&pio { - led_pins_r7: led-pin { - pins = "PB2"; - function = "gpio_out"; - drive-strength = <20>; - }; -}; - -®_usb1_vbus { - gpio = <&pio 6 13 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usbphy { - usb1_vbus-supply = <®_usb1_vbus>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun5i-a10s-wobo-i5.dts b/sys/gnu/dts/arm/sun5i-a10s-wobo-i5.dts deleted file mode 100644 index 1f74ba1634c..00000000000 --- a/sys/gnu/dts/arm/sun5i-a10s-wobo-i5.dts +++ /dev/null @@ -1,195 +0,0 @@ -/* - * Copyright 2015 Jelle van der Waa - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun5i-a10s.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include - -/ { - model = "A10s-Wobo i5"; - compatible = "wobo,a10s-wobo-i5", "allwinner,sun5i-a10s"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - blue { - label = "a10s-wobo-i5:blue:usr"; - gpios = <&pio 1 2 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; - - reg_emac_3v3: emac-3v3 { - compatible = "regulator-fixed"; - regulator-name = "emac-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <20000>; - enable-active-high; - gpio = <&pio 0 2 GPIO_ACTIVE_HIGH>; - }; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&ehci0 { - status = "okay"; -}; - -&emac { - pinctrl-names = "default"; - pinctrl-0 = <&emac_pd_pins>; - phy-handle = <&phy1>; - status = "okay"; -}; - -&emac_sram { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupts = <0>; - }; -}; - -#include "axp209.dtsi" - -&mdio { - phy-supply = <®_emac_3v3>; - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 1 3 GPIO_ACTIVE_LOW>; /* PB3 */ - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1250000>; - regulator-name = "vdd-int-dll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_ldo3 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi1"; -}; - -®_ldo4 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi2"; -}; - -®_usb1_vbus { - gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "host"; - status = "okay"; -}; - -&usbphy { - usb1_vbus-supply = <®_usb1_vbus>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun5i-a10s.dtsi b/sys/gnu/dts/arm/sun5i-a10s.dtsi deleted file mode 100644 index 09c486b608b..00000000000 --- a/sys/gnu/dts/arm/sun5i-a10s.dtsi +++ /dev/null @@ -1,173 +0,0 @@ -/* - * Copyright 2013 Maxime Ripard - * - * Maxime Ripard - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "sun5i.dtsi" - -#include - -/ { - aliases { - ethernet0 = &emac; - }; - - chosen { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - framebuffer-lcd0-hdmi { - compatible = "allwinner,simple-framebuffer", - "simple-framebuffer"; - allwinner,pipeline = "de_be0-lcd0-hdmi"; - clocks = <&ccu CLK_AHB_LCD>, <&ccu CLK_AHB_HDMI>, - <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DRAM_DE_BE>, - <&ccu CLK_DE_BE>, <&ccu CLK_HDMI>; - status = "disabled"; - }; - }; - - display-engine { - compatible = "allwinner,sun5i-a10s-display-engine"; - allwinner,pipelines = <&fe0>; - }; - - soc { - hdmi: hdmi@1c16000 { - compatible = "allwinner,sun5i-a10s-hdmi"; - reg = <0x01c16000 0x1000>; - interrupts = <58>; - clocks = <&ccu CLK_AHB_HDMI>, <&ccu CLK_HDMI>, - <&ccu CLK_PLL_VIDEO0_2X>, - <&ccu CLK_PLL_VIDEO1_2X>; - clock-names = "ahb", "mod", "pll-0", "pll-1"; - dmas = <&dma SUN4I_DMA_NORMAL 16>, - <&dma SUN4I_DMA_NORMAL 16>, - <&dma SUN4I_DMA_DEDICATED 24>; - dma-names = "ddc-tx", "ddc-rx", "audio-tx"; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - hdmi_in: port@0 { - reg = <0>; - - hdmi_in_tcon0: endpoint { - remote-endpoint = <&tcon0_out_hdmi>; - }; - }; - - hdmi_out: port@1 { - reg = <1>; - }; - }; - }; - - pwm: pwm@1c20e00 { - compatible = "allwinner,sun5i-a10s-pwm"; - reg = <0x01c20e00 0xc>; - clocks = <&ccu CLK_HOSC>; - #pwm-cells = <3>; - status = "disabled"; - }; - }; -}; - -&ccu { - compatible = "allwinner,sun5i-a10s-ccu"; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; -}; - -&pio { - compatible = "allwinner,sun5i-a10s-pinctrl"; - - uart0_pb_pins: uart0-pb-pins { - pins = "PB19", "PB20"; - function = "uart0"; - }; - - uart2_pc_pins: uart2-pc-pins { - pins = "PC18", "PC19"; - function = "uart2"; - }; - - emac_pa_pins: emac-pa-pins { - pins = "PA0", "PA1", "PA2", - "PA3", "PA4", "PA5", "PA6", - "PA7", "PA8", "PA9", "PA10", - "PA11", "PA12", "PA13", "PA14", - "PA15", "PA16"; - function = "emac"; - }; - - mmc1_pins: mmc1-pins { - pins = "PG3", "PG4", "PG5", - "PG6", "PG7", "PG8"; - function = "mmc1"; - drive-strength = <30>; - }; - - spi2_pb_pins: spi2-pb-pins { - pins = "PB12", "PB13", "PB14"; - function = "spi2"; - }; - - spi2_cs0_pb_pin: spi2-cs0-pb-pin { - pins = "PB11"; - function = "spi2"; - }; -}; - -&tcon0_out { - tcon0_out_hdmi: endpoint@2 { - reg = <2>; - remote-endpoint = <&hdmi_in_tcon0>; - allwinner,tcon-channel = <1>; - }; -}; diff --git a/sys/gnu/dts/arm/sun5i-a13-difrnce-dit4350.dts b/sys/gnu/dts/arm/sun5i-a13-difrnce-dit4350.dts deleted file mode 100644 index 894c4c4f9a1..00000000000 --- a/sys/gnu/dts/arm/sun5i-a13-difrnce-dit4350.dts +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Copyright 2016 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun5i-a13.dtsi" -#include "sun5i-reference-design-tablet.dtsi" - -/ { - model = "Difrnce DIT4350"; - compatible = "difrnce,dit4350", "allwinner,sun5i-a13"; -}; diff --git a/sys/gnu/dts/arm/sun5i-a13-empire-electronix-d709.dts b/sys/gnu/dts/arm/sun5i-a13-empire-electronix-d709.dts deleted file mode 100644 index a23bf24792e..00000000000 --- a/sys/gnu/dts/arm/sun5i-a13-empire-electronix-d709.dts +++ /dev/null @@ -1,189 +0,0 @@ -/* - * Copyright 2015 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun5i-a13.dtsi" -#include "sunxi-common-regulators.dtsi" -#include -#include -#include -#include - -/ { - model = "Empire Electronix D709 tablet"; - compatible = "empire-electronix,d709", "allwinner,sun5i-a13"; - - aliases { - serial0 = &uart1; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; - brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; - default-brightness-level = <8>; - /* TODO: backlight uses axp gpio1 as enable pin */ - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&ehci0 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupts = <0>; - }; -}; - -#include "axp209.dtsi" - -&i2c1 { - status = "okay"; - - pcf8563: rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; -}; - -&lradc { - vref-supply = <®_ldo2>; - status = "okay"; - - button-200 { - label = "Volume Up"; - linux,code = ; - channel = <0>; - voltage = <200000>; - }; - - button-400 { - label = "Volume Down"; - linux,code = ; - channel = <0>; - voltage = <400000>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */ - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pin>; - status = "okay"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1250000>; - regulator-name = "vdd-int-pll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_ldo3 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi"; -}; - -®_usb0_vbus { - gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pg_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 6 2 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PG2 */ - usb0_vbus_det-gpios = <&pio 6 1 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PG1 */ - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_ldo3>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun5i-a13-empire-electronix-m712.dts b/sys/gnu/dts/arm/sun5i-a13-empire-electronix-m712.dts deleted file mode 100644 index b1e2afd9de5..00000000000 --- a/sys/gnu/dts/arm/sun5i-a13-empire-electronix-m712.dts +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright 2016 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun5i-a13.dtsi" -#include "sun5i-reference-design-tablet.dtsi" -#include - -/ { - model = "Empire Electronix M712 tablet"; - compatible = "empire-electronix,m712", "allwinner,sun5i-a13"; -}; diff --git a/sys/gnu/dts/arm/sun5i-a13-hsg-h702.dts b/sys/gnu/dts/arm/sun5i-a13-hsg-h702.dts deleted file mode 100644 index 9b9f2a57485..00000000000 --- a/sys/gnu/dts/arm/sun5i-a13-hsg-h702.dts +++ /dev/null @@ -1,182 +0,0 @@ -/* - * Copyright 2014 Chen-Yu Tsai - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun5i-a13.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include - -/ { - model = "HSG H702"; - compatible = "hsg,h702", "allwinner,sun5i-a13"; - - aliases { - serial0 = &uart1; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&ehci0 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupts = <0>; - }; -}; - -&i2c1 { - status = "okay"; - - pcf8563: rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; -}; - -&i2c2 { - status = "okay"; -}; - -&lradc { - vref-supply = <®_ldo2>; - status = "okay"; - - button-200 { - label = "Volume Up"; - linux,code = ; - channel = <0>; - voltage = <200000>; - }; - - button-400 { - label = "Volume Down"; - linux,code = ; - channel = <0>; - voltage = <400000>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */ - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -#include "axp209.dtsi" - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-int-dll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_ldo3 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi"; -}; - -®_usb0_vbus { - gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pg_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 6 2 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PG2 */ - usb0_vbus_det-gpios = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */ - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_ldo3>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun5i-a13-inet-98v-rev2.dts b/sys/gnu/dts/arm/sun5i-a13-inet-98v-rev2.dts deleted file mode 100644 index 439ae3b537d..00000000000 --- a/sys/gnu/dts/arm/sun5i-a13-inet-98v-rev2.dts +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Copyright 2015 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun5i-a13.dtsi" -#include "sun5i-reference-design-tablet.dtsi" - -/ { - model = "INet-98V Rev 02"; - compatible = "primux,inet98v-rev2", "allwinner,sun5i-a13"; -}; diff --git a/sys/gnu/dts/arm/sun5i-a13-licheepi-one.dts b/sys/gnu/dts/arm/sun5i-a13-licheepi-one.dts deleted file mode 100644 index ba8d75b3c71..00000000000 --- a/sys/gnu/dts/arm/sun5i-a13-licheepi-one.dts +++ /dev/null @@ -1,214 +0,0 @@ -/* - * Copyright 2016 Icenowy Zheng - * - * Based on sun5i-a13-olinuxino.dts, which is - * Copyright 2012 Maxime Ripard - * Copyright 2013 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun5i-a13.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include - -/ { - model = "Lichee Pi One"; - compatible = "licheepi,licheepi-one", "allwinner,sun5i-a13"; - - aliases { - serial0 = &uart1; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - red { - label ="licheepi:red:usr"; - gpios = <&pio 2 5 GPIO_ACTIVE_LOW>; - }; - - green { - label ="licheepi:green:usr"; - gpios = <&pio 2 19 GPIO_ACTIVE_LOW>; - default-state = "on"; - }; - - blue { - label ="licheepi:blue:usr"; - gpios = <&pio 2 4 GPIO_ACTIVE_LOW>; - }; - - }; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&ehci0 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - compatible = "x-powers,axp209"; - reg = <0x34>; - interrupts = <0>; - - interrupt-controller; - #interrupt-cells = <1>; - }; -}; - -&i2c1 { - status = "disabled"; -}; - -&i2c2 { - status = "disabled"; -}; - -&lradc { - vref-supply = <®_ldo2>; - status = "okay"; - - button-984 { - label = "Home"; - linux,code = ; - channel = <0>; - voltage = <984126>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - broken-cd; - status = "okay"; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_4bit_pc_pins>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - broken-cd; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -#include "axp209.dtsi" - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-int-dll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_ldo3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "csi-1.8v"; -}; - -®_ldo4 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-name = "csi-2.8v"; -}; - -®_usb0_vbus { - gpio = <&pio 2 12 GPIO_ACTIVE_HIGH>; /* PC12 */ - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pg_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */ - usb0_vbus_det-gpios = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */ - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_vcc5v0>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun5i-a13-olinuxino-micro.dts b/sys/gnu/dts/arm/sun5i-a13-olinuxino-micro.dts deleted file mode 100644 index 5df398d7723..00000000000 --- a/sys/gnu/dts/arm/sun5i-a13-olinuxino-micro.dts +++ /dev/null @@ -1,141 +0,0 @@ -/* - * Copyright 2012 Maxime Ripard - * Copyright 2013 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun5i-a13.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include - -/ { - model = "Olimex A13-Olinuxino Micro"; - compatible = "olimex,a13-olinuxino-micro", "allwinner,sun5i-a13"; - - aliases { - serial0 = &uart1; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_olinuxinom>; - - power { - label = "a13-olinuxino-micro:green:power"; - gpios = <&pio 6 9 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; -}; - -&ehci0 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */ - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pio { - led_pins_olinuxinom: led-pin { - pins = "PG9"; - function = "gpio_out"; - drive-strength = <20>; - }; -}; - -®_usb0_vbus { - gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -®_usb1_vbus { - gpio = <&pio 6 11 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pg_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 6 2 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PG2 */ - usb0_vbus_det-gpios = <&pio 6 1 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PG1 */ - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_usb1_vbus>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun5i-a13-olinuxino.dts b/sys/gnu/dts/arm/sun5i-a13-olinuxino.dts deleted file mode 100644 index 39101228a75..00000000000 --- a/sys/gnu/dts/arm/sun5i-a13-olinuxino.dts +++ /dev/null @@ -1,247 +0,0 @@ -/* - * Copyright 2012 Maxime Ripard - * - * Maxime Ripard - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun5i-a13.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include - -/ { - model = "Olimex A13-Olinuxino"; - compatible = "olimex,a13-olinuxino", "allwinner,sun5i-a13"; - - aliases { - serial0 = &uart1; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_olinuxino>; - - power { - gpios = <&pio 6 9 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; - - bridge { - compatible = "dumb-vga-dac"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - vga_bridge_in: endpoint { - remote-endpoint = <&tcon0_out_vga>; - }; - }; - - port@1 { - reg = <1>; - - vga_bridge_out: endpoint { - remote-endpoint = <&vga_con_in>; - }; - }; - }; - }; - - vga { - compatible = "vga-connector"; - - port { - vga_con_in: endpoint { - remote-endpoint = <&vga_bridge_out>; - }; - }; - }; -}; - -&be0 { - status = "okay"; -}; - -&codec { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - compatible = "x-powers,axp209"; - reg = <0x34>; - interrupts = <0>; - - interrupt-controller; - #interrupt-cells = <1>; - }; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&lradc { - vref-supply = <®_vcc3v0>; - status = "okay"; - - button-191 { - label = "Volume Up"; - linux,code = ; - channel = <0>; - voltage = <191274>; - }; - - button-392 { - label = "Volume Down"; - linux,code = ; - channel = <0>; - voltage = <392644>; - }; - - button-601 { - label = "Menu"; - linux,code = ; - channel = <0>; - voltage = <601151>; - }; - - button-795 { - label = "Enter"; - linux,code = ; - channel = <0>; - voltage = <795090>; - }; - - button-987 { - label = "Home"; - linux,code = ; - channel = <0>; - voltage = <987387>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */ - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pio { - led_pins_olinuxino: led-pin { - pins = "PG9"; - function = "gpio_out"; - drive-strength = <20>; - }; -}; - -®_usb0_vbus { - status = "okay"; - gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ -}; - -®_usb1_vbus { - gpio = <&pio 6 11 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&tcon0 { - pinctrl-names = "default"; - pinctrl-0 = <&lcd_rgb666_pins>; - status = "okay"; -}; - -&tcon0_out { - tcon0_out_vga: endpoint@0 { - reg = <0>; - remote-endpoint = <&vga_bridge_in>; - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pg_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 6 2 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PG2 */ - usb0_vbus_det-gpios = <&pio 6 1 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PG1 */ - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_usb1_vbus>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun5i-a13-q8-tablet.dts b/sys/gnu/dts/arm/sun5i-a13-q8-tablet.dts deleted file mode 100644 index f9fc1c8b60b..00000000000 --- a/sys/gnu/dts/arm/sun5i-a13-q8-tablet.dts +++ /dev/null @@ -1,80 +0,0 @@ -/* - * Copyright 2015 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun5i-a13.dtsi" -#include "sun5i-reference-design-tablet.dtsi" - -/ { - model = "Q8 A13 Tablet"; - compatible = "allwinner,q8-a13", "allwinner,sun5i-a13"; - - panel: panel { - compatible = "bananapi,s070wv20-ct16"; - power-supply = <®_vcc3v3>; - enable-gpios = <&axp_gpio 0 GPIO_ACTIVE_HIGH>; /* AXP GPIO0 */ - backlight = <&backlight>; - - port { - panel_input: endpoint { - remote-endpoint = <&tcon0_out_lcd>; - }; - }; - }; -}; - -&be0 { - status = "okay"; -}; - -&tcon0 { - pinctrl-names = "default"; - pinctrl-0 = <&lcd_rgb666_pins>; - status = "okay"; -}; - -&tcon0_out { - tcon0_out_lcd: endpoint@0 { - reg = <0>; - remote-endpoint = <&panel_input>; - }; -}; diff --git a/sys/gnu/dts/arm/sun5i-a13-utoo-p66.dts b/sys/gnu/dts/arm/sun5i-a13-utoo-p66.dts deleted file mode 100644 index be486d28d04..00000000000 --- a/sys/gnu/dts/arm/sun5i-a13-utoo-p66.dts +++ /dev/null @@ -1,116 +0,0 @@ -/* - * Copyright 2015 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun5i-a13.dtsi" -#include "sun5i-reference-design-tablet.dtsi" -#include - -/ { - model = "Utoo P66"; - compatible = "utoo,p66", "allwinner,sun5i-a13"; - - /* The P66 uses the uart pins as gpios */ - aliases { - /delete-property/serial0; - }; - - chosen { - /delete-property/stdout-path; - }; - - i2c_lcd: i2c { - /* The lcd panel i2c interface is hooked up via gpios */ - compatible = "i2c-gpio"; - sda-gpios = <&pio 6 12 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PG12 */ - scl-gpios = <&pio 6 10 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PG10 */ - i2c-gpio,delay-us = <5>; - }; -}; - -&backlight { - /* Note levels of 10 / 20% result in backlight off */ - brightness-levels = <0 30 40 50 60 70 80 90 100>; - default-brightness-level = <6>; -}; - -&codec { - allwinner,pa-gpios = <&pio 6 3 GPIO_ACTIVE_HIGH>; /* PG3 */ -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_8bit_pins>; - vmmc-supply = <®_vcc3v3>; - bus-width = <8>; - non-removable; - status = "okay"; - - mmccard: mmccard@0 { - reg = <0>; - compatible = "mmc-card"; - broken-hpi; - }; -}; - -®_usb0_vbus { - gpio = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */ -}; - -&touchscreen { - compatible = "chipone,icn8318"; - reg = <0x40>; - /* The P66 uses a different EINT then the reference design */ - interrupts = <6 9 IRQ_TYPE_EDGE_FALLING>; /* EINT9 (PG9) */ - /* The icn8318 binding expects wake-gpios instead of power-gpios */ - wake-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */ - touchscreen-size-x = <800>; - touchscreen-size-y = <480>; - touchscreen-inverted-x; - touchscreen-swapped-x-y; - status = "okay"; -}; - -&uart1 { - /* The P66 uses the uart pins as gpios */ - status = "disabled"; -}; diff --git a/sys/gnu/dts/arm/sun5i-a13.dtsi b/sys/gnu/dts/arm/sun5i-a13.dtsi deleted file mode 100644 index ae04955fd9a..00000000000 --- a/sys/gnu/dts/arm/sun5i-a13.dtsi +++ /dev/null @@ -1,119 +0,0 @@ -/* - * Copyright 2012 Maxime Ripard - * - * Maxime Ripard - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "sun5i.dtsi" - -#include - -/ { - thermal-zones { - cpu_thermal { - /* milliseconds */ - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&rtp>; - - cooling-maps { - map0 { - trip = <&cpu_alert0>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - - trips { - cpu_alert0: cpu_alert0 { - /* milliCelsius */ - temperature = <85000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu_crit: cpu_crit { - /* milliCelsius */ - temperature = <100000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - }; - - display-engine { - compatible = "allwinner,sun5i-a13-display-engine"; - allwinner,pipelines = <&fe0>; - }; - - soc { - pwm: pwm@1c20e00 { - compatible = "allwinner,sun5i-a13-pwm"; - reg = <0x01c20e00 0xc>; - clocks = <&ccu CLK_HOSC>; - #pwm-cells = <3>; - status = "disabled"; - }; - - }; -}; - -&ccu { - compatible = "allwinner,sun5i-a13-ccu"; -}; - -&cpu0 { - clock-latency = <244144>; /* 8 32k periods */ - operating-points = < - /* kHz uV */ - 1008000 1400000 - 912000 1350000 - 864000 1300000 - 624000 1200000 - 576000 1200000 - 432000 1200000 - >; - #cooling-cells = <2>; -}; - -&pio { - compatible = "allwinner,sun5i-a13-pinctrl"; -}; diff --git a/sys/gnu/dts/arm/sun5i-gr8-chip-pro.dts b/sys/gnu/dts/arm/sun5i-gr8-chip-pro.dts deleted file mode 100644 index a32cde3e32e..00000000000 --- a/sys/gnu/dts/arm/sun5i-gr8-chip-pro.dts +++ /dev/null @@ -1,238 +0,0 @@ -/* - * Copyright 2016 Free Electrons - * Copyright 2016 NextThing Co - * - * Maxime Ripard - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun5i-gr8.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include -#include - -/ { - model = "NextThing C.H.I.P. Pro"; - compatible = "nextthing,chip-pro", "nextthing,gr8"; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - status { - label = "chip-pro:white:status"; - gpios = <&axp_gpio 2 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; - - mmc0_pwrseq: mmc0_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&pio 1 10 GPIO_ACTIVE_LOW>; /* PB10 */ - }; -}; - -&codec { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - - /* - * The interrupt is routed through the "External Fast - * Interrupt Request" pin (ball G13 of the module) - * directly to the main interrupt controller, without - * any other controller interfering. - */ - interrupts = <0>; - }; -}; - -#include "axp209.dtsi" - -&i2c1 { - status = "disabled"; -}; - -&i2s0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_mclk_pin>, <&i2s0_data_pins>; - status = "disabled"; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - mmc-pwrseq = <&mmc0_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; -}; - -&nfc { - pinctrl-names = "default"; - pinctrl-0 = <&nand_pins &nand_cs0_pin &nand_rb0_pin>; - status = "okay"; - - nand@0 { - reg = <0>; - allwinner,rb = <0>; - nand-ecc-mode = "hw"; - }; -}; - -&ohci0 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pin>, <&pwm1_pins>; - status = "disabled"; -}; - -®_dcdc2 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; - regulator-always-on; -}; - -®_dcdc3 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1300000>; - regulator-name = "vdd-sys"; - regulator-always-on; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <3300000>; - regulator-name = "avcc"; - regulator-always-on; -}; - -/* - * Both LDO3 and LDO4 are used in parallel to power up the - * WiFi/BT chip. - */ -®_ldo3 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi-1"; - regulator-always-on; -}; - -®_ldo4 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi-2"; - regulator-always-on; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pg_pins>, <&uart1_cts_rts_pins>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pd_pins>, <&uart2_cts_rts_pd_pins>; - status = "disabled"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pg_pins>, <&uart3_cts_rts_pg_pins>; - status = "okay"; -}; - -&usb_otg { - /* - * The CHIP Pro doesn't have a controllable VBUS, nor does it - * have any 5v rail on the board itself. - * - * If one wants to use it as a true OTG port, it should be - * done in the baseboard, and its DT / overlay will add it. - */ - dr_mode = "otg"; - status = "okay"; -}; - -&usb_power_supply { - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */ - usb0_vbus_power-supply = <&usb_power_supply>; - usb1_vbus-supply = <®_vcc5v0>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun5i-gr8-evb.dts b/sys/gnu/dts/arm/sun5i-gr8-evb.dts deleted file mode 100644 index 4c20d731a9c..00000000000 --- a/sys/gnu/dts/arm/sun5i-gr8-evb.dts +++ /dev/null @@ -1,333 +0,0 @@ -/* - * Copyright 2016 Free Electrons - * Copyright 2016 NextThing Co - * - * Mylène Josserand - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun5i-gr8.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include -#include - -/ { - model = "NextThing GR8-EVB"; - compatible = "nextthing,gr8-evb", "nextthing,gr8"; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - serial0 = &uart1; - serial1 = &uart2; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 0 10000 0>; - enable-gpios = <&axp_gpio 1 GPIO_ACTIVE_HIGH>; - - brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; - default-brightness-level = <8>; - }; - - sound-analog { - compatible = "simple-audio-card"; - simple-audio-card,name = "gr8-evb-wm8978"; - simple-audio-card,format = "i2s"; - simple-audio-card,mclk-fs = <512>; - - simple-audio-card,cpu { - sound-dai = <&i2s0>; - }; - - simple-audio-card,codec { - sound-dai = <&wm8978>; - }; - }; - - sound-spdif { - compatible = "simple-audio-card"; - simple-audio-card,name = "On-board SPDIF"; - - simple-audio-card,cpu { - sound-dai = <&spdif>; - }; - - simple-audio-card,codec { - sound-dai = <&spdif_out>; - }; - }; - - spdif_out: spdif-out { - #sound-dai-cells = <0>; - compatible = "linux,spdif-dit"; - }; -}; - -&be0 { - status = "okay"; -}; - -&codec { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - - /* - * The interrupt is routed through the "External Fast - * Interrupt Request" pin (ball G13 of the module) - * directly to the main interrupt controller, without - * any other controller interfering. - */ - interrupts = <0>; - }; -}; - -#include "axp209.dtsi" - -&i2c1 { - status = "okay"; - - wm8978: codec@1a { - #sound-dai-cells = <0>; - compatible = "wlf,wm8978"; - reg = <0x1a>; - }; - - pcf8563: rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; -}; - -&i2c2 { - status = "okay"; -}; - -&i2s0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_mclk_pin>, <&i2s0_data_pins>; - status = "okay"; -}; - -&ir0 { - pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pin>; - status = "okay"; -}; - -&lradc { - vref-supply = <®_ldo2>; - status = "okay"; - - button-190 { - label = "Volume Up"; - linux,code = ; - channel = <0>; - voltage = <190000>; - }; - - button-390 { - label = "Volume Down"; - linux,code = ; - channel = <0>; - voltage = <390000>; - }; - - button-600 { - label = "Menu"; - linux,code = ; - channel = <0>; - voltage = <600000>; - }; - - button-800 { - label = "Search"; - linux,code = ; - channel = <0>; - voltage = <800000>; - }; - - button-980 { - label = "Home"; - linux,code = ; - channel = <0>; - voltage = <980000>; - }; - - button-1180 { - label = "Esc"; - linux,code = ; - channel = <0>; - voltage = <1180000>; - }; - - button-1400 { - label = "Enter"; - linux,code = ; - channel = <0>; - voltage = <1400000>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */ - status = "okay"; -}; - -&nfc { - pinctrl-names = "default"; - pinctrl-0 = <&nand_pins &nand_cs0_pin &nand_rb0_pin>; - - /* MLC Support sucks for now */ - status = "disabled"; -}; - -&ohci0 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pin>; - status = "okay"; -}; - -®_dcdc2 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; - regulator-always-on; -}; - -®_dcdc3 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1300000>; - regulator-name = "vdd-sys"; - regulator-always-on; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <3300000>; - regulator-name = "avcc"; - regulator-always-on; -}; - -®_usb1_vbus { - gpio = <&pio 6 13 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&rtp { - allwinner,ts-attached; -}; - -&spdif { - pinctrl-names = "default"; - pinctrl-0 = <&spdif_tx_pin>; - status = "okay"; -}; - -&tve0 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pg_pins>, <&uart1_cts_rts_pins>; - status = "okay"; -}; - -&usb_otg { - /* - * The GR8-EVB has a somewhat interesting design. There's a - * pin supposed to control VBUS, an ID pin, a VBUS detect pin, - * so everything should work just fine. - * - * Except that the pin supposed to control VBUS is not - * connected to any controllable output, neither to the SoC - * through a GPIO or to the PMIC, and it is pulled down, - * meaning that we will never be able to enable VBUS on this - * board. - */ - dr_mode = "otg"; - status = "okay"; -}; - -&usb_power_supply { - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */ - usb0_vbus_det-gpios = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */ - usb0_vbus_power-supply = <&usb_power_supply>; - usb1_vbus-supply = <®_usb1_vbus>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun5i-gr8.dtsi b/sys/gnu/dts/arm/sun5i-gr8.dtsi deleted file mode 100644 index 98a8fd5e89e..00000000000 --- a/sys/gnu/dts/arm/sun5i-gr8.dtsi +++ /dev/null @@ -1,126 +0,0 @@ -/* - * Copyright 2016 Mylène Josserand - * - * Mylène Josserand - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "sun5i.dtsi" - -#include -#include -#include - -/ { - display-engine { - compatible = "allwinner,sun5i-a13-display-engine"; - allwinner,pipelines = <&fe0>; - }; - - soc { - pwm: pwm@1c20e00 { - compatible = "allwinner,sun5i-a10s-pwm"; - reg = <0x01c20e00 0xc>; - clocks = <&ccu CLK_HOSC>; - #pwm-cells = <3>; - status = "disabled"; - }; - - spdif: spdif@1c21000 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun4i-a10-spdif"; - reg = <0x01c21000 0x400>; - interrupts = <13>; - clocks = <&ccu CLK_APB0_SPDIF>, <&ccu CLK_SPDIF>; - clock-names = "apb", "spdif"; - dmas = <&dma SUN4I_DMA_NORMAL 2>, - <&dma SUN4I_DMA_NORMAL 2>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2s0: i2s@1c22400 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun4i-a10-i2s"; - reg = <0x01c22400 0x400>; - interrupts = <16>; - clocks = <&ccu CLK_APB0_I2S>, <&ccu CLK_I2S>; - clock-names = "apb", "mod"; - dmas = <&dma SUN4I_DMA_NORMAL 3>, - <&dma SUN4I_DMA_NORMAL 3>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - }; -}; - -&ccu { - compatible = "nextthing,gr8-ccu"; -}; - -&pio { - compatible = "nextthing,gr8-pinctrl"; - - i2s0_data_pins: i2s0-data-pins { - pins = "PB6", "PB7", "PB8", "PB9"; - function = "i2s0"; - }; - - i2s0_mclk_pin: i2s0-mclk-pin { - pins = "PB5"; - function = "i2s0"; - }; - - pwm1_pins: pwm1-pin { - pins = "PG13"; - function = "pwm1"; - }; - - spdif_tx_pin: spdif-tx-pin { - pins = "PB10"; - function = "spdif"; - bias-pull-up; - }; - - uart1_cts_rts_pins: uart1-cts-rts-pins { - pins = "PG5", "PG6"; - function = "uart1"; - }; -}; diff --git a/sys/gnu/dts/arm/sun5i-q8-common.dtsi b/sys/gnu/dts/arm/sun5i-q8-common.dtsi deleted file mode 100644 index a78e189f665..00000000000 --- a/sys/gnu/dts/arm/sun5i-q8-common.dtsi +++ /dev/null @@ -1,180 +0,0 @@ -/* - * Copyright 2015 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -#include "sunxi-q8-common.dtsi" - -#include - -/ { - aliases { - serial0 = &uart1; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; - brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; - default-brightness-level = <8>; - /* TODO: backlight uses axp gpio1 as enable pin */ - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&ehci0 { - status = "okay"; -}; - -&i2c0 { - axp209: pmic@34 { - reg = <0x34>; - interrupts = <0>; - }; -}; - -&i2c1 { - pcf8563: rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; -}; - -#include "axp209.dtsi" - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_q8>; - vmmc-supply = <®_vcc3v0>; - bus-width = <4>; - cd-gpios = <&pio 6 0 GPIO_ACTIVE_HIGH>; /* PG0 */ - cd-inverted; - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pio { - mmc0_cd_pin_q8: mmc0_cd_pin@0 { - allwinner,pins = "PG0"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { - allwinner,pins = "PG1"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb0_id_detect_pin: usb0_id_detect_pin@0 { - allwinner,pins = "PG2"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb0_vbus_pin_a: usb0_vbus_pin@0 { - allwinner,pins = "PG12"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-int-pll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_usb0_vbus { - gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins_b>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; - usb0_id_det-gpio = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */ - usb0_vbus_det-gpio = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */ - usb0_vbus-supply = <®_usb0_vbus>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun5i-r8-chip.dts b/sys/gnu/dts/arm/sun5i-r8-chip.dts deleted file mode 100644 index 4bf4943d4eb..00000000000 --- a/sys/gnu/dts/arm/sun5i-r8-chip.dts +++ /dev/null @@ -1,276 +0,0 @@ -/* - * Copyright 2015 Free Electrons - * Copyright 2015 NextThing Co - * - * Maxime Ripard - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun5i-r8.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include - -/ { - model = "NextThing C.H.I.P."; - compatible = "nextthing,chip", "allwinner,sun5i-r8", "allwinner,sun5i-a13"; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - serial0 = &uart1; - serial1 = &uart3; - spi0 = &spi2; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - status { - label = "chip:white:status"; - gpios = <&axp_gpio 2 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; - - mmc0_pwrseq: mmc0_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&pio 2 19 GPIO_ACTIVE_LOW>; /* PC19 */ - }; - - onewire { - compatible = "w1-gpio"; - gpios = <&pio 3 2 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PD2 */ - }; -}; - -&be0 { - status = "okay"; -}; - -&codec { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&ehci0 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - - /* - * The interrupt is routed through the "External Fast - * Interrupt Request" pin (ball G13 of the module) - * directly to the main interrupt controller, without - * any other controller interfering. - */ - interrupts = <0>; - }; -}; - -#include "axp209.dtsi" - -&ac_power_supply { - status = "okay"; -}; - -&battery_power_supply { - status = "okay"; -}; - -&i2c1 { - status = "disabled"; -}; - -&i2c2 { - status = "okay"; - - xio: gpio@38 { - compatible = "nxp,pcf8574a"; - reg = <0x38>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-parent = <&pio>; - interrupts = <6 0 IRQ_TYPE_EDGE_FALLING>; - interrupt-controller; - #interrupt-cells = <2>; - }; -}; - -&mmc0_pins { - bias-pull-up; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - mmc-pwrseq = <&mmc0_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -®_dcdc2 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "cpuvdd"; - regulator-always-on; -}; - -®_dcdc3 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1300000>; - regulator-name = "corevdd"; - regulator-always-on; -}; - -®_ldo1 { - regulator-name = "rtcvdd"; -}; - -®_ldo2 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <3300000>; - regulator-name = "avcc"; - regulator-always-on; -}; - -/* - * Both LDO3 and LDO4 are used in parallel to power up the WiFi/BT - * Chip. - * - * If those are not enabled, the SDIO part will not enumerate, and - * since there's no way currently to pass DT infos to an SDIO device, - * we cannot really do better than this ugly hack for now. - */ -®_ldo3 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi-1"; - regulator-always-on; -}; - -®_ldo4 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi-2"; - regulator-always-on; -}; - -®_ldo5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc-1v8"; -}; - -®_usb0_vbus { - vin-supply = <®_vcc5v0>; - gpio = <&pio 1 10 GPIO_ACTIVE_HIGH>; /* PB10 */ - status = "okay"; -}; - -&spi2 { - pinctrl-names = "default"; - pinctrl-0 = <&spi2_pe_pins>; - status = "disabled"; -}; - -&tcon0 { - status = "okay"; -}; - -&tve0 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pg_pins>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pg_pins>, - <&uart3_cts_rts_pg_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usb_power_supply { - status = "okay"; -}; - -&usbphy { - status = "okay"; - - usb0_id_det-gpios = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */ - usb0_vbus_power-supply = <&usb_power_supply>; - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_vcc5v0>; -}; diff --git a/sys/gnu/dts/arm/sun5i-r8.dtsi b/sys/gnu/dts/arm/sun5i-r8.dtsi deleted file mode 100644 index de35dbcd119..00000000000 --- a/sys/gnu/dts/arm/sun5i-r8.dtsi +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Copyright 2015 Free Electrons - * Copyright 2015 NextThing Co - * - * Maxime Ripard - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "sun5i-a13.dtsi" - diff --git a/sys/gnu/dts/arm/sun5i-reference-design-tablet.dtsi b/sys/gnu/dts/arm/sun5i-reference-design-tablet.dtsi deleted file mode 100644 index 1a9926d7141..00000000000 --- a/sys/gnu/dts/arm/sun5i-reference-design-tablet.dtsi +++ /dev/null @@ -1,193 +0,0 @@ -/* - * Copyright 2015 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -#include "sunxi-reference-design-tablet.dtsi" - -#include -#include - -/ { - aliases { - serial0 = &uart1; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; - brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; - default-brightness-level = <8>; - enable-gpios = <&axp_gpio 1 GPIO_ACTIVE_HIGH>; /* AXP GPIO1 */ - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&codec { - allwinner,pa-gpios = <&pio 6 10 GPIO_ACTIVE_HIGH>; /* PG10 */ - status = "okay"; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&ehci0 { - status = "okay"; -}; - -&i2c0 { - axp209: pmic@34 { - reg = <0x34>; - interrupts = <0>; - }; -}; - -&i2c1 { - /* - * The gsl1680 is rated at 400KHz and it will not work reliable at - * 100KHz, this has been confirmed on multiple different q8 tablets. - * All other devices on this bus are also rated for 400KHz. - */ - clock-frequency = <400000>; - - touchscreen: touchscreen@40 { - reg = <0x40>; - interrupt-parent = <&pio>; - interrupts = <6 11 IRQ_TYPE_EDGE_FALLING>; /* EINT11 (PG11) */ - power-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */ - /* Tablet dts must provide reg and compatible */ - status = "disabled"; - }; - - pcf8563: rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; -}; - -#include "axp209.dtsi" - -&ac_power_supply { - status = "okay"; -}; - -&battery_power_supply { - status = "okay"; -}; - -&lradc { - vref-supply = <®_ldo2>; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; - vmmc-supply = <®_vcc3v0>; - bus-width = <4>; - cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */ - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-int-pll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_ldo3 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi"; -}; - -®_usb0_vbus { - gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pg_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usb_power_supply { - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 6 2 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PG2 */ - usb0_vbus_det-gpios = <&pio 6 1 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PG1 */ - usb0_vbus_power-supply = <&usb_power_supply>; - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_ldo3>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun5i.dtsi b/sys/gnu/dts/arm/sun5i.dtsi deleted file mode 100644 index 0b526e6e5a9..00000000000 --- a/sys/gnu/dts/arm/sun5i.dtsi +++ /dev/null @@ -1,799 +0,0 @@ -/* - * Copyright 2012-2015 Maxime Ripard - * - * Maxime Ripard - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include -#include -#include - -/ { - interrupt-parent = <&intc>; - #address-cells = <1>; - #size-cells = <1>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a8"; - reg = <0x0>; - clocks = <&ccu CLK_CPU>; - }; - }; - - chosen { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - framebuffer-lcd0 { - compatible = "allwinner,simple-framebuffer", - "simple-framebuffer"; - allwinner,pipeline = "de_be0-lcd0"; - clocks = <&ccu CLK_AHB_LCD>, <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>, - <&ccu CLK_TCON_CH0>, <&ccu CLK_DRAM_DE_BE>; - status = "disabled"; - }; - - framebuffer-lcd0-tve0 { - compatible = "allwinner,simple-framebuffer", - "simple-framebuffer"; - allwinner,pipeline = "de_be0-lcd0-tve0"; - clocks = <&ccu CLK_AHB_TVE>, <&ccu CLK_AHB_LCD>, - <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>, - <&ccu CLK_TCON_CH1>, <&ccu CLK_DRAM_DE_BE>; - status = "disabled"; - }; - }; - - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - osc24M: clk-24M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "osc24M"; - }; - - osc32k: clk-32k { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - clock-output-names = "osc32k"; - }; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - /* Address must be kept in the lower 256 MiBs of DRAM for VE. */ - default-pool { - compatible = "shared-dma-pool"; - size = <0x6000000>; - alloc-ranges = <0x4a000000 0x6000000>; - reusable; - linux,cma-default; - }; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - dma-ranges; - ranges; - - system-control@1c00000 { - compatible = "allwinner,sun5i-a13-system-control"; - reg = <0x01c00000 0x30>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - sram_a: sram@0 { - compatible = "mmio-sram"; - reg = <0x00000000 0xc000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x00000000 0xc000>; - - emac_sram: sram-section@8000 { - compatible = "allwinner,sun5i-a13-sram-a3-a4", - "allwinner,sun4i-a10-sram-a3-a4"; - reg = <0x8000 0x4000>; - status = "disabled"; - }; - }; - - sram_d: sram@10000 { - compatible = "mmio-sram"; - reg = <0x00010000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x00010000 0x1000>; - - otg_sram: sram-section@0 { - compatible = "allwinner,sun5i-a13-sram-d", - "allwinner,sun4i-a10-sram-d"; - reg = <0x0000 0x1000>; - status = "disabled"; - }; - }; - - sram_c: sram@1d00000 { - compatible = "mmio-sram"; - reg = <0x01d00000 0xd0000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x01d00000 0xd0000>; - - ve_sram: sram-section@0 { - compatible = "allwinner,sun5i-a13-sram-c1", - "allwinner,sun4i-a10-sram-c1"; - reg = <0x000000 0x80000>; - }; - }; - }; - - mbus: dram-controller@1c01000 { - compatible = "allwinner,sun5i-a13-mbus"; - reg = <0x01c01000 0x1000>; - clocks = <&ccu CLK_MBUS>; - dma-ranges = <0x00000000 0x40000000 0x20000000>; - #interconnect-cells = <1>; - }; - - dma: dma-controller@1c02000 { - compatible = "allwinner,sun4i-a10-dma"; - reg = <0x01c02000 0x1000>; - interrupts = <27>; - clocks = <&ccu CLK_AHB_DMA>; - #dma-cells = <2>; - }; - - nfc: nand-controller@1c03000 { - compatible = "allwinner,sun4i-a10-nand"; - reg = <0x01c03000 0x1000>; - interrupts = <37>; - clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>; - clock-names = "ahb", "mod"; - dmas = <&dma SUN4I_DMA_DEDICATED 3>; - dma-names = "rxtx"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - spi0: spi@1c05000 { - compatible = "allwinner,sun4i-a10-spi"; - reg = <0x01c05000 0x1000>; - interrupts = <10>; - clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>; - clock-names = "ahb", "mod"; - dmas = <&dma SUN4I_DMA_DEDICATED 27>, - <&dma SUN4I_DMA_DEDICATED 26>; - dma-names = "rx", "tx"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - spi1: spi@1c06000 { - compatible = "allwinner,sun4i-a10-spi"; - reg = <0x01c06000 0x1000>; - interrupts = <11>; - clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>; - clock-names = "ahb", "mod"; - dmas = <&dma SUN4I_DMA_DEDICATED 9>, - <&dma SUN4I_DMA_DEDICATED 8>; - dma-names = "rx", "tx"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - tve0: tv-encoder@1c0a000 { - compatible = "allwinner,sun4i-a10-tv-encoder"; - reg = <0x01c0a000 0x1000>; - clocks = <&ccu CLK_AHB_TVE>; - resets = <&ccu RST_TVE>; - status = "disabled"; - - port { - - tve0_in_tcon0: endpoint { - remote-endpoint = <&tcon0_out_tve0>; - }; - }; - }; - - emac: ethernet@1c0b000 { - compatible = "allwinner,sun4i-a10-emac"; - reg = <0x01c0b000 0x1000>; - interrupts = <55>; - clocks = <&ccu CLK_AHB_EMAC>; - allwinner,sram = <&emac_sram 1>; - status = "disabled"; - }; - - mdio: mdio@1c0b080 { - compatible = "allwinner,sun4i-a10-mdio"; - reg = <0x01c0b080 0x14>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - tcon0: lcd-controller@1c0c000 { - compatible = "allwinner,sun5i-a13-tcon"; - reg = <0x01c0c000 0x1000>; - interrupts = <44>; - dmas = <&dma SUN4I_DMA_DEDICATED 14>; - resets = <&ccu RST_LCD>; - reset-names = "lcd"; - clocks = <&ccu CLK_AHB_LCD>, - <&ccu CLK_TCON_CH0>, - <&ccu CLK_TCON_CH1>; - clock-names = "ahb", - "tcon-ch0", - "tcon-ch1"; - clock-output-names = "tcon-pixel-clock"; - #clock-cells = <0>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - tcon0_in: port@0 { - reg = <0>; - - tcon0_in_be0: endpoint { - remote-endpoint = <&be0_out_tcon0>; - }; - }; - - tcon0_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - tcon0_out_tve0: endpoint@1 { - reg = <1>; - remote-endpoint = <&tve0_in_tcon0>; - allwinner,tcon-channel = <1>; - }; - }; - }; - }; - - video-codec@1c0e000 { - compatible = "allwinner,sun5i-a13-video-engine"; - reg = <0x01c0e000 0x1000>; - clocks = <&ccu CLK_AHB_VE>, <&ccu CLK_VE>, - <&ccu CLK_DRAM_VE>; - clock-names = "ahb", "mod", "ram"; - resets = <&ccu RST_VE>; - interrupts = <53>; - allwinner,sram = <&ve_sram 1>; - }; - - mmc0: mmc@1c0f000 { - compatible = "allwinner,sun5i-a13-mmc"; - reg = <0x01c0f000 0x1000>; - clocks = <&ccu CLK_AHB_MMC0>, <&ccu CLK_MMC0>; - clock-names = "ahb", "mmc"; - interrupts = <32>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc1: mmc@1c10000 { - compatible = "allwinner,sun5i-a13-mmc"; - reg = <0x01c10000 0x1000>; - clocks = <&ccu CLK_AHB_MMC1>, <&ccu CLK_MMC1>; - clock-names = "ahb", "mmc"; - interrupts = <33>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc2: mmc@1c11000 { - compatible = "allwinner,sun5i-a13-mmc"; - reg = <0x01c11000 0x1000>; - clocks = <&ccu CLK_AHB_MMC2>, <&ccu CLK_MMC2>; - clock-names = "ahb", "mmc"; - interrupts = <34>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - usb_otg: usb@1c13000 { - compatible = "allwinner,sun4i-a10-musb"; - reg = <0x01c13000 0x0400>; - clocks = <&ccu CLK_AHB_OTG>; - interrupts = <38>; - interrupt-names = "mc"; - phys = <&usbphy 0>; - phy-names = "usb"; - extcon = <&usbphy 0>; - allwinner,sram = <&otg_sram 1>; - dr_mode = "otg"; - status = "disabled"; - }; - - usbphy: phy@1c13400 { - #phy-cells = <1>; - compatible = "allwinner,sun5i-a13-usb-phy"; - reg = <0x01c13400 0x10>, <0x01c14800 0x4>; - reg-names = "phy_ctrl", "pmu1"; - clocks = <&ccu CLK_USB_PHY0>; - clock-names = "usb_phy"; - resets = <&ccu RST_USB_PHY0>, <&ccu RST_USB_PHY1>; - reset-names = "usb0_reset", "usb1_reset"; - status = "disabled"; - }; - - ehci0: usb@1c14000 { - compatible = "allwinner,sun5i-a13-ehci", "generic-ehci"; - reg = <0x01c14000 0x100>; - interrupts = <39>; - clocks = <&ccu CLK_AHB_EHCI>; - phys = <&usbphy 1>; - phy-names = "usb"; - status = "disabled"; - }; - - ohci0: usb@1c14400 { - compatible = "allwinner,sun5i-a13-ohci", "generic-ohci"; - reg = <0x01c14400 0x100>; - interrupts = <40>; - clocks = <&ccu CLK_USB_OHCI>, <&ccu CLK_AHB_OHCI>; - phys = <&usbphy 1>; - phy-names = "usb"; - status = "disabled"; - }; - - crypto: crypto-engine@1c15000 { - compatible = "allwinner,sun5i-a13-crypto", - "allwinner,sun4i-a10-crypto"; - reg = <0x01c15000 0x1000>; - interrupts = <54>; - clocks = <&ccu CLK_AHB_SS>, <&ccu CLK_SS>; - clock-names = "ahb", "mod"; - }; - - spi2: spi@1c17000 { - compatible = "allwinner,sun4i-a10-spi"; - reg = <0x01c17000 0x1000>; - interrupts = <12>; - clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>; - clock-names = "ahb", "mod"; - dmas = <&dma SUN4I_DMA_DEDICATED 29>, - <&dma SUN4I_DMA_DEDICATED 28>; - dma-names = "rx", "tx"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - ccu: clock@1c20000 { - reg = <0x01c20000 0x400>; - clocks = <&osc24M>, <&osc32k>; - clock-names = "hosc", "losc"; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - intc: interrupt-controller@1c20400 { - compatible = "allwinner,sun4i-a10-ic"; - reg = <0x01c20400 0x400>; - interrupt-controller; - #interrupt-cells = <1>; - }; - - pio: pinctrl@1c20800 { - reg = <0x01c20800 0x400>; - interrupts = <28>; - clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>; - clock-names = "apb", "hosc", "losc"; - gpio-controller; - interrupt-controller; - #interrupt-cells = <3>; - #gpio-cells = <3>; - - emac_pd_pins: emac-pd-pins { - pins = "PD6", "PD7", "PD10", - "PD11", "PD12", "PD13", "PD14", - "PD15", "PD18", "PD19", "PD20", - "PD21", "PD22", "PD23", "PD24", - "PD25", "PD26", "PD27"; - function = "emac"; - }; - - i2c0_pins: i2c0-pins { - pins = "PB0", "PB1"; - function = "i2c0"; - }; - - i2c1_pins: i2c1-pins { - pins = "PB15", "PB16"; - function = "i2c1"; - }; - - i2c2_pins: i2c2-pins { - pins = "PB17", "PB18"; - function = "i2c2"; - }; - - ir0_rx_pin: ir0-rx-pin { - pins = "PB4"; - function = "ir0"; - }; - - lcd_rgb565_pins: lcd-rgb565-pins { - pins = "PD3", "PD4", "PD5", "PD6", "PD7", - "PD10", "PD11", "PD12", "PD13", "PD14", "PD15", - "PD19", "PD20", "PD21", "PD22", "PD23", - "PD24", "PD25", "PD26", "PD27"; - function = "lcd0"; - }; - - lcd_rgb666_pins: lcd-rgb666-pins { - pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", - "PD10", "PD11", "PD12", "PD13", "PD14", "PD15", - "PD18", "PD19", "PD20", "PD21", "PD22", "PD23", - "PD24", "PD25", "PD26", "PD27"; - function = "lcd0"; - }; - - mmc0_pins: mmc0-pins { - pins = "PF0", "PF1", "PF2", "PF3", - "PF4", "PF5"; - function = "mmc0"; - drive-strength = <30>; - bias-pull-up; - }; - - mmc2_4bit_pc_pins: mmc2-4bit-pc-pins { - pins = "PC6", "PC7", "PC8", "PC9", - "PC10", "PC11"; - function = "mmc2"; - drive-strength = <30>; - bias-pull-up; - }; - - mmc2_8bit_pins: mmc2-8bit-pins { - pins = "PC6", "PC7", "PC8", "PC9", - "PC10", "PC11", "PC12", "PC13", - "PC14", "PC15"; - function = "mmc2"; - drive-strength = <30>; - bias-pull-up; - }; - - nand_pins: nand-pins { - pins = "PC0", "PC1", "PC2", - "PC5", "PC8", "PC9", "PC10", - "PC11", "PC12", "PC13", "PC14", - "PC15"; - function = "nand0"; - }; - - nand_cs0_pin: nand-cs0-pin { - pins = "PC4"; - function = "nand0"; - }; - - nand_rb0_pin: nand-rb0-pin { - pins = "PC6"; - function = "nand0"; - }; - - pwm0_pin: pwm0-pin { - pins = "PB2"; - function = "pwm"; - }; - - spi2_pe_pins: spi2-pe-pins { - pins = "PE1", "PE2", "PE3"; - function = "spi2"; - }; - - spi2_cs0_pe_pin: spi2-cs0-pe-pin { - pins = "PE0"; - function = "spi2"; - }; - - uart1_pe_pins: uart1-pe-pins { - pins = "PE10", "PE11"; - function = "uart1"; - }; - - uart1_pg_pins: uart1-pg-pins { - pins = "PG3", "PG4"; - function = "uart1"; - }; - - uart2_pd_pins: uart2-pd-pins { - pins = "PD2", "PD3"; - function = "uart2"; - }; - - uart2_cts_rts_pd_pins: uart2-cts-rts-pd-pins { - pins = "PD4", "PD5"; - function = "uart2"; - }; - - uart3_pg_pins: uart3-pg-pins { - pins = "PG9", "PG10"; - function = "uart3"; - }; - - uart3_cts_rts_pg_pins: uart3-cts-rts-pg-pins { - pins = "PG11", "PG12"; - function = "uart3"; - }; - }; - - timer@1c20c00 { - compatible = "allwinner,sun4i-a10-timer"; - reg = <0x01c20c00 0x90>; - interrupts = <22>, - <23>, - <24>, - <25>, - <67>, - <68>; - clocks = <&ccu CLK_HOSC>; - }; - - wdt: watchdog@1c20c90 { - compatible = "allwinner,sun4i-a10-wdt"; - reg = <0x01c20c90 0x10>; - interrupts = <24>; - clocks = <&osc24M>; - }; - - ir0: ir@1c21800 { - compatible = "allwinner,sun4i-a10-ir"; - clocks = <&ccu CLK_APB0_IR>, <&ccu CLK_IR>; - clock-names = "apb", "ir"; - interrupts = <5>; - reg = <0x01c21800 0x40>; - status = "disabled"; - }; - - lradc: lradc@1c22800 { - compatible = "allwinner,sun4i-a10-lradc-keys"; - reg = <0x01c22800 0x100>; - interrupts = <31>; - status = "disabled"; - }; - - codec: codec@1c22c00 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun4i-a10-codec"; - reg = <0x01c22c00 0x40>; - interrupts = <30>; - clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>; - clock-names = "apb", "codec"; - dmas = <&dma SUN4I_DMA_NORMAL 19>, - <&dma SUN4I_DMA_NORMAL 19>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - sid: eeprom@1c23800 { - compatible = "allwinner,sun4i-a10-sid"; - reg = <0x01c23800 0x10>; - }; - - rtp: rtp@1c25000 { - compatible = "allwinner,sun5i-a13-ts"; - reg = <0x01c25000 0x100>; - interrupts = <29>; - #thermal-sensor-cells = <0>; - }; - - uart0: serial@1c28000 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28000 0x400>; - interrupts = <1>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_APB1_UART0>; - status = "disabled"; - }; - - uart1: serial@1c28400 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28400 0x400>; - interrupts = <2>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_APB1_UART1>; - status = "disabled"; - }; - - uart2: serial@1c28800 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28800 0x400>; - interrupts = <3>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_APB1_UART2>; - status = "disabled"; - }; - - uart3: serial@1c28c00 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28c00 0x400>; - interrupts = <4>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_APB1_UART3>; - status = "disabled"; - }; - - i2c0: i2c@1c2ac00 { - compatible = "allwinner,sun4i-a10-i2c"; - reg = <0x01c2ac00 0x400>; - interrupts = <7>; - clocks = <&ccu CLK_APB1_I2C0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c1: i2c@1c2b000 { - compatible = "allwinner,sun4i-a10-i2c"; - reg = <0x01c2b000 0x400>; - interrupts = <8>; - clocks = <&ccu CLK_APB1_I2C1>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c2: i2c@1c2b400 { - compatible = "allwinner,sun4i-a10-i2c"; - reg = <0x01c2b400 0x400>; - interrupts = <9>; - clocks = <&ccu CLK_APB1_I2C2>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - timer@1c60000 { - compatible = "allwinner,sun5i-a13-hstimer"; - reg = <0x01c60000 0x1000>; - interrupts = <82>, <83>; - clocks = <&ccu CLK_AHB_HSTIMER>; - }; - - fe0: display-frontend@1e00000 { - compatible = "allwinner,sun5i-a13-display-frontend"; - reg = <0x01e00000 0x20000>; - interrupts = <47>; - clocks = <&ccu CLK_DE_FE>, <&ccu CLK_DE_FE>, - <&ccu CLK_DRAM_DE_FE>; - clock-names = "ahb", "mod", - "ram"; - resets = <&ccu RST_DE_FE>; - interconnects = <&mbus 19>; - interconnect-names = "dma-mem"; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - fe0_out: port@1 { - reg = <1>; - - fe0_out_be0: endpoint { - remote-endpoint = <&be0_in_fe0>; - }; - }; - }; - }; - - be0: display-backend@1e60000 { - compatible = "allwinner,sun5i-a13-display-backend"; - reg = <0x01e60000 0x10000>; - interrupts = <47>; - clocks = <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>, - <&ccu CLK_DRAM_DE_BE>; - clock-names = "ahb", "mod", - "ram"; - resets = <&ccu RST_DE_BE>; - interconnects = <&mbus 18>; - interconnect-names = "dma-mem"; - status = "disabled"; - - assigned-clocks = <&ccu CLK_DE_BE>; - assigned-clock-rates = <300000000>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - be0_in: port@0 { - reg = <0>; - - be0_in_fe0: endpoint { - remote-endpoint = <&fe0_out_be0>; - }; - }; - - be0_out: port@1 { - reg = <1>; - - be0_out_tcon0: endpoint { - remote-endpoint = <&tcon0_in_be0>; - }; - }; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/sun6i-a31-app4-evb1.dts b/sys/gnu/dts/arm/sun6i-a31-app4-evb1.dts deleted file mode 100644 index 32d22025ac9..00000000000 --- a/sys/gnu/dts/arm/sun6i-a31-app4-evb1.dts +++ /dev/null @@ -1,82 +0,0 @@ -/* - * Copyright 2014 Boris Brezillon - * - * Boris Brezillon - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun6i-a31.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include - -/ { - model = "Allwinner A31 APP4 EVB1 Evaluation Board"; - compatible = "allwinner,app4-evb1", "allwinner,sun6i-a31"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&ehci0 { - status = "okay"; -}; - -®_usb1_vbus { - gpio = <&pio 7 27 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_ph_pins>; - status = "okay"; -}; - -&usbphy { - usb1_vbus-supply = <®_usb1_vbus>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun6i-a31-colombus.dts b/sys/gnu/dts/arm/sun6i-a31-colombus.dts deleted file mode 100644 index 93a15eaaa8c..00000000000 --- a/sys/gnu/dts/arm/sun6i-a31-colombus.dts +++ /dev/null @@ -1,130 +0,0 @@ -/* - * Copyright 2013 Maxime Ripard - * - * Maxime Ripard - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun6i-a31.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include - -/ { - model = "WITS A31 Colombus Evaluation Board"; - compatible = "wits,colombus", "allwinner,sun6i-a31"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - i2c_lcd: i2c { - /* The lcd panel i2c interface is hooked up via gpios */ - compatible = "i2c-gpio"; - sda-gpios = <&pio 0 23 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PA23 */ - scl-gpios = <&pio 0 24 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PA24 */ - i2c-gpio,delay-us = <5>; - }; -}; - -&ehci1 { - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_rgmii_pins>; - phy-handle = <&phy1>; - phy-mode = "rgmii"; - status = "okay"; -}; - -&i2c0 { - status = "fail"; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; - - mma8452: mma8452@1d { - compatible = "fsl,mma8452"; - reg = <0x1d>; - interrupt-parent = <&pio>; - interrupts = <0 9 IRQ_TYPE_LEVEL_LOW>; /* PA9 */ - }; -}; - -&mdio { - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v0>; - bus-width = <4>; - cd-gpios = <&pio 0 8 GPIO_ACTIVE_LOW>; /* PA8 */ - status = "okay"; -}; - -®_usb2_vbus { - gpio = <&pio 7 24 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_ph_pins>; - status = "okay"; -}; - -&usbphy { - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun6i-a31-hummingbird.dts b/sys/gnu/dts/arm/sun6i-a31-hummingbird.dts deleted file mode 100644 index 049e6ab3cf5..00000000000 --- a/sys/gnu/dts/arm/sun6i-a31-hummingbird.dts +++ /dev/null @@ -1,338 +0,0 @@ -/* - * Copyright 2014 Maxime Ripard - * - * Maxime Ripard - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun6i-a31.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include - -/ { - model = "Merrii A31 Hummingbird"; - compatible = "merrii,a31-hummingbird", "allwinner,sun6i-a31"; - - aliases { - rtc0 = &pcf8563; - rtc1 = &rtc; - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - vga-connector { - compatible = "vga-connector"; - - port { - vga_con_in: endpoint { - remote-endpoint = <&vga_dac_out>; - }; - }; - }; - - vga-dac { - compatible = "dumb-vga-dac"; - vdd-supply = <®_vga_3v3>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - vga_dac_in: endpoint { - remote-endpoint = <&tcon0_out_vga>; - }; - }; - - port@1 { - reg = <1>; - - vga_dac_out: endpoint { - remote-endpoint = <&vga_con_in>; - }; - }; - }; - }; - - reg_vga_3v3: vga_3v3_regulator { - compatible = "regulator-fixed"; - regulator-name = "vga-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - enable-active-high; - gpio = <&pio 7 25 GPIO_ACTIVE_HIGH>; /* PH25 */ - }; - - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&pio 6 10 GPIO_ACTIVE_LOW>; /* PG10 */ - }; -}; - -&codec { - allwinner,audio-routing = - "Headphone", "HP", - "Speaker", "LINEOUT", - "LINEIN", "Line In", - "MIC1", "Mic", - "MIC2", "Headset Mic", - "Mic", "MBIAS", - "Headset Mic", "HBIAS"; - allwinner,pa-gpios = <&pio 7 22 GPIO_ACTIVE_HIGH>; /* PH22 */ - status = "okay"; -}; - -&cpu0 { - cpu-supply = <®_dcdc3>; -}; - -&de { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_rgmii_pins>; - phy-handle = <&phy1>; - phy-mode = "rgmii"; - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&i2c0 { - /* pull-ups and devices require AXP221 DLDO3 */ - status = "failed"; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; - - pcf8563: rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; -}; - -&ir { - pinctrl-names = "default"; - pinctrl-0 = <&s_ir_rx_pin>; - status = "okay"; -}; - -&mdio { - phy1: ethernet-phy@1 { - reg = <1>; - reset-gpios = <&pio 0 21 GPIO_ACTIVE_LOW>; - reset-assert-us = <10000>; - reset-deassert-us = <30000>; - }; -}; - -&mmc0 { - vmmc-supply = <®_dcdc1>; - bus-width = <4>; - cd-gpios = <&pio 0 8 GPIO_ACTIVE_LOW>; /* PA8 */ - status = "okay"; -}; - -&mmc1 { - vmmc-supply = <®_aldo1>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&p2wi { - status = "okay"; - - axp22x: pmic@68 { - compatible = "x-powers,axp221"; - reg = <0x68>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - x-powers,drive-vbus-en; - }; -}; - -#include "axp22x.dtsi" - -&ac_power_supply { - status = "okay"; -}; - -®_aldo1 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi"; -}; - -®_aldo3 { - regulator-always-on; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <3300000>; - regulator-name = "avcc"; -}; - -®_dc5ldo { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-cpus"; -}; - -®_dcdc1 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-3v0"; -}; - -®_dcdc2 { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-gpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc4 { - regulator-always-on; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-sys-dll"; -}; - -®_dcdc5 { - regulator-always-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vcc-dram"; -}; - -®_drivevbus { - regulator-name = "usb0-vbus"; - status = "okay"; -}; - -®_usb1_vbus { - gpio = <&pio 7 24 GPIO_ACTIVE_HIGH>; /* PH24 */ - status = "okay"; -}; - -&tcon0 { - pinctrl-names = "default"; - pinctrl-0 = <&lcd0_rgb888_pins>; -}; - -&tcon0_out { - tcon0_out_vga: endpoint@0 { - reg = <0>; - remote-endpoint = <&vga_dac_in>; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_ph_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usb_power_supply { - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 0 15 GPIO_ACTIVE_HIGH>; /* PA15 */ - usb0_vbus_det-gpios = <&pio 0 16 GPIO_ACTIVE_HIGH>; /* PA16 */ - usb0_vbus_power-supply = <&usb_power_supply>; - usb0_vbus-supply = <®_drivevbus>; - usb1_vbus-supply = <®_usb1_vbus>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun6i-a31-i7.dts b/sys/gnu/dts/arm/sun6i-a31-i7.dts deleted file mode 100644 index 6cc8ccf53d8..00000000000 --- a/sys/gnu/dts/arm/sun6i-a31-i7.dts +++ /dev/null @@ -1,178 +0,0 @@ -/* - * Copyright 2015 Marcus Cooper - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun6i-a31.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include - -/ { - model = "Mele I7 Quad top set box"; - compatible = "mele,i7", "allwinner,sun6i-a31"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - blue { - label = "i7:blue:usr"; - gpios = <&pio 7 13 GPIO_ACTIVE_HIGH>; - }; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "On-board SPDIF"; - simple-audio-card,cpu { - sound-dai = <&spdif>; - }; - - simple-audio-card,codec { - sound-dai = <&spdif_out>; - }; - }; - - spdif_out: spdif-out { - #sound-dai-cells = <0>; - compatible = "linux,spdif-dit"; - }; -}; - -&codec { - allwinner,audio-routing = - "Headphone", "HP"; - status = "okay"; -}; - -&de { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_mii_pins>; - phy-handle = <&phy1>; - phy-mode = "mii"; - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&ir { - pinctrl-names = "default"; - pinctrl-0 = <&s_ir_rx_pin>; - status = "okay"; -}; - -&mdio { - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 22 GPIO_ACTIVE_LOW>; /* PH22 */ - status = "okay"; -}; - -®_usb1_vbus { - gpio = <&pio 2 27 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&spdif { - pinctrl-names = "default"; - pinctrl-0 = <&spdif_tx_pin>; - status = "okay"; -}; - -&tcon0 { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_ph_pins>; - status = "okay"; -}; - -&usbphy { - usb1_vbus-supply = <®_usb1_vbus>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun6i-a31-m9.dts b/sys/gnu/dts/arm/sun6i-a31-m9.dts deleted file mode 100644 index a645c8f4257..00000000000 --- a/sys/gnu/dts/arm/sun6i-a31-m9.dts +++ /dev/null @@ -1,212 +0,0 @@ -/* - * Copyright 2014 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun6i-a31.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include - -/ { - model = "Mele M9 top set box"; - compatible = "mele,m9", "allwinner,sun6i-a31"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - blue { - label = "m9:blue:pwr"; - gpios = <&pio 7 13 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; -}; - -&cpu0 { - cpu-supply = <®_dcdc3>; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_mii_pins>; - phy-handle = <&phy1>; - phy-mode = "mii"; - phy-supply = <®_dldo1>; - status = "okay"; -}; - -&ir { - pinctrl-names = "default"; - pinctrl-0 = <&s_ir_rx_pin>; - status = "okay"; -}; - -&mdio { - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&mmc0 { - vmmc-supply = <®_dcdc1>; - bus-width = <4>; - cd-gpios = <&pio 7 22 GPIO_ACTIVE_LOW>; /* PH22 */ - status = "okay"; -}; - -&p2wi { - status = "okay"; - - axp22x: pmic@68 { - compatible = "x-powers,axp221"; - reg = <0x68>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -#include "axp22x.dtsi" - -®_aldo1 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi"; -}; - -®_aldo3 { - regulator-always-on; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <3300000>; - regulator-name = "avcc"; -}; - -®_dc5ldo { - regulator-always-on; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-cpus"; /* This is an educated guess */ -}; - -®_dcdc1 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-3v3"; -}; - -®_dcdc2 { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-gpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc4 { - regulator-always-on; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-sys-dll"; -}; - -®_dcdc5 { - regulator-always-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vcc-dram"; -}; - -®_dldo1 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-ethernet-phy"; -}; - -/* - * Both reg_usb1_vbus and reg_dldo4 need to be on for the hub attached - * to usb1 to work, and we can list only one usb1_vbus-supply, so dldo4 is - * marked as regulator-always-on. - */ -®_dldo4 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-usb-hub"; -}; - -®_usb1_vbus { - gpio = <&pio 2 27 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_ph_pins>; - status = "okay"; -}; - -&usbphy { - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_aldo1>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun6i-a31-mele-a1000g-quad.dts b/sys/gnu/dts/arm/sun6i-a31-mele-a1000g-quad.dts deleted file mode 100644 index 648f2474623..00000000000 --- a/sys/gnu/dts/arm/sun6i-a31-mele-a1000g-quad.dts +++ /dev/null @@ -1,217 +0,0 @@ -/* - * Copyright 2014 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun6i-a31.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include - -/ { - model = "Mele A1000G Quad top set box"; - compatible = "mele,a1000g-quad", "allwinner,sun6i-a31"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - blue { - label = "a1000g:blue:pwr"; - gpios = <&pio 7 13 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; -}; - -&cpu0 { - cpu-supply = <®_dcdc3>; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_mii_pins>; - phy-handle = <&phy1>; - phy-mode = "mii"; - phy-supply = <®_dldo1>; - status = "okay"; -}; - -&ir { - pinctrl-names = "default"; - pinctrl-0 = <&s_ir_rx_pin>; - status = "okay"; -}; - -&mdio { - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&mmc0 { - vmmc-supply = <®_dcdc1>; - bus-width = <4>; - cd-gpios = <&pio 7 22 GPIO_ACTIVE_LOW>; /* PH22 */ - status = "okay"; -}; - -&p2wi { - status = "okay"; - - axp22x: pmic@68 { - compatible = "x-powers,axp221"; - reg = <0x68>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -#include "axp22x.dtsi" - -®_aldo1 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi"; -}; - -®_aldo3 { - regulator-always-on; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <3300000>; - regulator-name = "avcc"; -}; - -®_dc5ldo { - regulator-always-on; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-cpus"; /* This is an educated guess */ -}; - -®_dcdc1 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-3v3"; -}; - -®_dcdc2 { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-gpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc4 { - regulator-always-on; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-sys-dll"; -}; - -®_dcdc5 { - regulator-always-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vcc-dram"; -}; - -®_dldo1 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-ethernet-phy"; -}; - -/* - * Both reg_usb1_vbus and reg_dldo4 need to be on for the hub attached - * to usb1 to work, and we can list only one usb1_vbus-supply, so dldo4 is - * marked as regulator-always-on. - */ -®_dldo4 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-usb-hub"; -}; - -®_usb1_vbus { - gpio = <&pio 2 27 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_ph_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "host"; - status = "okay"; -}; - -&usbphy { - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_aldo1>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun6i-a31.dtsi b/sys/gnu/dts/arm/sun6i-a31.dtsi deleted file mode 100644 index 7762fbd9a13..00000000000 --- a/sys/gnu/dts/arm/sun6i-a31.dtsi +++ /dev/null @@ -1,1433 +0,0 @@ -/* - * Copyright 2013 Maxime Ripard - * - * Maxime Ripard - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include -#include - -#include -#include - -/ { - interrupt-parent = <&gic>; - #address-cells = <1>; - #size-cells = <1>; - - aliases { - ethernet0 = &gmac; - }; - - chosen { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - simplefb_hdmi: framebuffer-lcd0-hdmi { - compatible = "allwinner,simple-framebuffer", - "simple-framebuffer"; - allwinner,pipeline = "de_be0-lcd0-hdmi"; - clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>, - <&ccu CLK_AHB1_HDMI>, <&ccu CLK_DRAM_BE0>, - <&ccu CLK_IEP_DRC0>, <&ccu CLK_BE0>, - <&ccu CLK_LCD0_CH1>, <&ccu CLK_HDMI>; - status = "disabled"; - }; - - simplefb_lcd: framebuffer-lcd0 { - compatible = "allwinner,simple-framebuffer", - "simple-framebuffer"; - allwinner,pipeline = "de_be0-lcd0"; - clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>, - <&ccu CLK_DRAM_BE0>, <&ccu CLK_IEP_DRC0>, - <&ccu CLK_BE0>, <&ccu CLK_LCD0_CH0>; - status = "disabled"; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; - clock-frequency = <24000000>; - arm,cpu-registers-not-fw-configured; - }; - - cpus { - enable-method = "allwinner,sun6i-a31"; - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <0>; - clocks = <&ccu CLK_CPU>; - clock-latency = <244144>; /* 8 32k periods */ - operating-points = < - /* kHz uV */ - 1008000 1200000 - 864000 1200000 - 720000 1100000 - 480000 1000000 - >; - #cooling-cells = <2>; - }; - - cpu1: cpu@1 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <1>; - clocks = <&ccu CLK_CPU>; - clock-latency = <244144>; /* 8 32k periods */ - operating-points = < - /* kHz uV */ - 1008000 1200000 - 864000 1200000 - 720000 1100000 - 480000 1000000 - >; - #cooling-cells = <2>; - }; - - cpu2: cpu@2 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <2>; - clocks = <&ccu CLK_CPU>; - clock-latency = <244144>; /* 8 32k periods */ - operating-points = < - /* kHz uV */ - 1008000 1200000 - 864000 1200000 - 720000 1100000 - 480000 1000000 - >; - #cooling-cells = <2>; - }; - - cpu3: cpu@3 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <3>; - clocks = <&ccu CLK_CPU>; - clock-latency = <244144>; /* 8 32k periods */ - operating-points = < - /* kHz uV */ - 1008000 1200000 - 864000 1200000 - 720000 1100000 - 480000 1000000 - >; - #cooling-cells = <2>; - }; - }; - - thermal-zones { - cpu_thermal { - /* milliseconds */ - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&rtp>; - - cooling-maps { - map0 { - trip = <&cpu_alert0>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - - trips { - cpu_alert0: cpu_alert0 { - /* milliCelsius */ - temperature = <70000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu_crit: cpu_crit { - /* milliCelsius */ - temperature = <100000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - }; - - pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts = , - , - , - ; - }; - - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - osc24M: clk-24M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-accuracy = <50000>; - clock-output-names = "osc24M"; - }; - - osc32k: clk-32k { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - clock-accuracy = <50000>; - clock-output-names = "ext_osc32k"; - }; - - /* - * The following two are dummy clocks, placeholders - * used in the gmac_tx clock. The gmac driver will - * choose one parent depending on the PHY interface - * mode, using clk_set_rate auto-reparenting. - * - * The actual TX clock rate is not controlled by the - * gmac_tx clock. - */ - mii_phy_tx_clk: clk-mii-phy-tx { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <25000000>; - clock-output-names = "mii_phy_tx"; - }; - - gmac_int_tx_clk: clk-gmac-int-tx { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "gmac_int_tx"; - }; - - gmac_tx_clk: clk@1c200d0 { - #clock-cells = <0>; - compatible = "allwinner,sun7i-a20-gmac-clk"; - reg = <0x01c200d0 0x4>; - clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>; - clock-output-names = "gmac_tx"; - }; - }; - - de: display-engine { - compatible = "allwinner,sun6i-a31-display-engine"; - allwinner,pipelines = <&fe0>, <&fe1>; - status = "disabled"; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - dma: dma-controller@1c02000 { - compatible = "allwinner,sun6i-a31-dma"; - reg = <0x01c02000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_AHB1_DMA>; - resets = <&ccu RST_AHB1_DMA>; - #dma-cells = <1>; - }; - - tcon0: lcd-controller@1c0c000 { - compatible = "allwinner,sun6i-a31-tcon"; - reg = <0x01c0c000 0x1000>; - interrupts = ; - dmas = <&dma 11>; - resets = <&ccu RST_AHB1_LCD0>, - <&ccu RST_AHB1_LVDS>; - reset-names = "lcd", - "lvds"; - clocks = <&ccu CLK_AHB1_LCD0>, - <&ccu CLK_LCD0_CH0>, - <&ccu CLK_LCD0_CH1>, - <&ccu 15>; - clock-names = "ahb", - "tcon-ch0", - "tcon-ch1", - "lvds-alt"; - clock-output-names = "tcon0-pixel-clock"; - #clock-cells = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - tcon0_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - tcon0_in_drc0: endpoint@0 { - reg = <0>; - remote-endpoint = <&drc0_out_tcon0>; - }; - - tcon0_in_drc1: endpoint@1 { - reg = <1>; - remote-endpoint = <&drc1_out_tcon0>; - }; - }; - - tcon0_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - tcon0_out_hdmi: endpoint@1 { - reg = <1>; - remote-endpoint = <&hdmi_in_tcon0>; - allwinner,tcon-channel = <1>; - }; - }; - }; - }; - - tcon1: lcd-controller@1c0d000 { - compatible = "allwinner,sun6i-a31-tcon"; - reg = <0x01c0d000 0x1000>; - interrupts = ; - dmas = <&dma 12>; - resets = <&ccu RST_AHB1_LCD1>, - <&ccu RST_AHB1_LVDS>; - reset-names = "lcd", "lvds"; - clocks = <&ccu CLK_AHB1_LCD1>, - <&ccu CLK_LCD1_CH0>, - <&ccu CLK_LCD1_CH1>, - <&ccu 15>; - clock-names = "ahb", - "tcon-ch0", - "tcon-ch1", - "lvds-alt"; - clock-output-names = "tcon1-pixel-clock"; - #clock-cells = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - tcon1_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - tcon1_in_drc0: endpoint@0 { - reg = <0>; - remote-endpoint = <&drc0_out_tcon1>; - }; - - tcon1_in_drc1: endpoint@1 { - reg = <1>; - remote-endpoint = <&drc1_out_tcon1>; - }; - }; - - tcon1_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - tcon1_out_hdmi: endpoint@1 { - reg = <1>; - remote-endpoint = <&hdmi_in_tcon1>; - allwinner,tcon-channel = <1>; - }; - }; - }; - }; - - mmc0: mmc@1c0f000 { - compatible = "allwinner,sun7i-a20-mmc"; - reg = <0x01c0f000 0x1000>; - clocks = <&ccu CLK_AHB1_MMC0>, - <&ccu CLK_MMC0>, - <&ccu CLK_MMC0_OUTPUT>, - <&ccu CLK_MMC0_SAMPLE>; - clock-names = "ahb", - "mmc", - "output", - "sample"; - resets = <&ccu RST_AHB1_MMC0>; - reset-names = "ahb"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc1: mmc@1c10000 { - compatible = "allwinner,sun7i-a20-mmc"; - reg = <0x01c10000 0x1000>; - clocks = <&ccu CLK_AHB1_MMC1>, - <&ccu CLK_MMC1>, - <&ccu CLK_MMC1_OUTPUT>, - <&ccu CLK_MMC1_SAMPLE>; - clock-names = "ahb", - "mmc", - "output", - "sample"; - resets = <&ccu RST_AHB1_MMC1>; - reset-names = "ahb"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc2: mmc@1c11000 { - compatible = "allwinner,sun7i-a20-mmc"; - reg = <0x01c11000 0x1000>; - clocks = <&ccu CLK_AHB1_MMC2>, - <&ccu CLK_MMC2>, - <&ccu CLK_MMC2_OUTPUT>, - <&ccu CLK_MMC2_SAMPLE>; - clock-names = "ahb", - "mmc", - "output", - "sample"; - resets = <&ccu RST_AHB1_MMC2>; - reset-names = "ahb"; - interrupts = ; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc3: mmc@1c12000 { - compatible = "allwinner,sun7i-a20-mmc"; - reg = <0x01c12000 0x1000>; - clocks = <&ccu CLK_AHB1_MMC3>, - <&ccu CLK_MMC3>, - <&ccu CLK_MMC3_OUTPUT>, - <&ccu CLK_MMC3_SAMPLE>; - clock-names = "ahb", - "mmc", - "output", - "sample"; - resets = <&ccu RST_AHB1_MMC3>; - reset-names = "ahb"; - interrupts = ; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - hdmi: hdmi@1c16000 { - compatible = "allwinner,sun6i-a31-hdmi"; - reg = <0x01c16000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_AHB1_HDMI>, <&ccu CLK_HDMI>, - <&ccu CLK_HDMI_DDC>, - <&ccu CLK_PLL_VIDEO0_2X>, - <&ccu CLK_PLL_VIDEO1_2X>; - clock-names = "ahb", "mod", "ddc", "pll-0", "pll-1"; - resets = <&ccu RST_AHB1_HDMI>; - dma-names = "ddc-tx", "ddc-rx", "audio-tx"; - dmas = <&dma 13>, <&dma 13>, <&dma 14>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - hdmi_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - hdmi_in_tcon0: endpoint@0 { - reg = <0>; - remote-endpoint = <&tcon0_out_hdmi>; - }; - - hdmi_in_tcon1: endpoint@1 { - reg = <1>; - remote-endpoint = <&tcon1_out_hdmi>; - }; - }; - - hdmi_out: port@1 { - reg = <1>; - }; - }; - }; - - usb_otg: usb@1c19000 { - compatible = "allwinner,sun6i-a31-musb"; - reg = <0x01c19000 0x0400>; - clocks = <&ccu CLK_AHB1_OTG>; - resets = <&ccu RST_AHB1_OTG>; - interrupts = ; - interrupt-names = "mc"; - phys = <&usbphy 0>; - phy-names = "usb"; - extcon = <&usbphy 0>; - dr_mode = "otg"; - status = "disabled"; - }; - - usbphy: phy@1c19400 { - compatible = "allwinner,sun6i-a31-usb-phy"; - reg = <0x01c19400 0x10>, - <0x01c1a800 0x4>, - <0x01c1b800 0x4>; - reg-names = "phy_ctrl", - "pmu1", - "pmu2"; - clocks = <&ccu CLK_USB_PHY0>, - <&ccu CLK_USB_PHY1>, - <&ccu CLK_USB_PHY2>; - clock-names = "usb0_phy", - "usb1_phy", - "usb2_phy"; - resets = <&ccu RST_USB_PHY0>, - <&ccu RST_USB_PHY1>, - <&ccu RST_USB_PHY2>; - reset-names = "usb0_reset", - "usb1_reset", - "usb2_reset"; - status = "disabled"; - #phy-cells = <1>; - }; - - ehci0: usb@1c1a000 { - compatible = "allwinner,sun6i-a31-ehci", "generic-ehci"; - reg = <0x01c1a000 0x100>; - interrupts = ; - clocks = <&ccu CLK_AHB1_EHCI0>; - resets = <&ccu RST_AHB1_EHCI0>; - phys = <&usbphy 1>; - phy-names = "usb"; - status = "disabled"; - }; - - ohci0: usb@1c1a400 { - compatible = "allwinner,sun6i-a31-ohci", "generic-ohci"; - reg = <0x01c1a400 0x100>; - interrupts = ; - clocks = <&ccu CLK_AHB1_OHCI0>, <&ccu CLK_USB_OHCI0>; - resets = <&ccu RST_AHB1_OHCI0>; - phys = <&usbphy 1>; - phy-names = "usb"; - status = "disabled"; - }; - - ehci1: usb@1c1b000 { - compatible = "allwinner,sun6i-a31-ehci", "generic-ehci"; - reg = <0x01c1b000 0x100>; - interrupts = ; - clocks = <&ccu CLK_AHB1_EHCI1>; - resets = <&ccu RST_AHB1_EHCI1>; - phys = <&usbphy 2>; - phy-names = "usb"; - status = "disabled"; - }; - - ohci1: usb@1c1b400 { - compatible = "allwinner,sun6i-a31-ohci", "generic-ohci"; - reg = <0x01c1b400 0x100>; - interrupts = ; - clocks = <&ccu CLK_AHB1_OHCI1>, <&ccu CLK_USB_OHCI1>; - resets = <&ccu RST_AHB1_OHCI1>; - phys = <&usbphy 2>; - phy-names = "usb"; - status = "disabled"; - }; - - ohci2: usb@1c1c400 { - compatible = "allwinner,sun6i-a31-ohci", "generic-ohci"; - reg = <0x01c1c400 0x100>; - interrupts = ; - clocks = <&ccu CLK_AHB1_OHCI2>, <&ccu CLK_USB_OHCI2>; - resets = <&ccu RST_AHB1_OHCI2>; - status = "disabled"; - }; - - ccu: clock@1c20000 { - compatible = "allwinner,sun6i-a31-ccu"; - reg = <0x01c20000 0x400>; - clocks = <&osc24M>, <&rtc 0>; - clock-names = "hosc", "losc"; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - pio: pinctrl@1c20800 { - compatible = "allwinner,sun6i-a31-pinctrl"; - reg = <0x01c20800 0x400>; - interrupts = , - , - , - ; - clocks = <&ccu CLK_APB1_PIO>, <&osc24M>, <&rtc 0>; - clock-names = "apb", "hosc", "losc"; - gpio-controller; - interrupt-controller; - #interrupt-cells = <3>; - #gpio-cells = <3>; - - gmac_gmii_pins: gmac-gmii-pins { - pins = "PA0", "PA1", "PA2", "PA3", - "PA4", "PA5", "PA6", "PA7", - "PA8", "PA9", "PA10", "PA11", - "PA12", "PA13", "PA14", "PA15", - "PA16", "PA17", "PA18", "PA19", - "PA20", "PA21", "PA22", "PA23", - "PA24", "PA25", "PA26", "PA27"; - function = "gmac"; - /* - * data lines in GMII mode run at 125MHz and - * might need a higher signal drive strength - */ - drive-strength = <30>; - }; - - gmac_mii_pins: gmac-mii-pins { - pins = "PA0", "PA1", "PA2", "PA3", - "PA8", "PA9", "PA11", - "PA12", "PA13", "PA14", "PA19", - "PA20", "PA21", "PA22", "PA23", - "PA24", "PA26", "PA27"; - function = "gmac"; - }; - - gmac_rgmii_pins: gmac-rgmii-pins { - pins = "PA0", "PA1", "PA2", "PA3", - "PA9", "PA10", "PA11", - "PA12", "PA13", "PA14", "PA19", - "PA20", "PA25", "PA26", "PA27"; - function = "gmac"; - /* - * data lines in RGMII mode use DDR mode - * and need a higher signal drive strength - */ - drive-strength = <40>; - }; - - i2c0_pins: i2c0-pins { - pins = "PH14", "PH15"; - function = "i2c0"; - }; - - i2c1_pins: i2c1-pins { - pins = "PH16", "PH17"; - function = "i2c1"; - }; - - i2c2_pins: i2c2-pins { - pins = "PH18", "PH19"; - function = "i2c2"; - }; - - lcd0_rgb888_pins: lcd0-rgb888-pins { - pins = "PD0", "PD1", "PD2", "PD3", - "PD4", "PD5", "PD6", "PD7", - "PD8", "PD9", "PD10", "PD11", - "PD12", "PD13", "PD14", "PD15", - "PD16", "PD17", "PD18", "PD19", - "PD20", "PD21", "PD22", "PD23", - "PD24", "PD25", "PD26", "PD27"; - function = "lcd0"; - }; - - mmc0_pins: mmc0-pins { - pins = "PF0", "PF1", "PF2", - "PF3", "PF4", "PF5"; - function = "mmc0"; - drive-strength = <30>; - bias-pull-up; - }; - - mmc1_pins: mmc1-pins { - pins = "PG0", "PG1", "PG2", "PG3", - "PG4", "PG5"; - function = "mmc1"; - drive-strength = <30>; - bias-pull-up; - }; - - mmc2_4bit_pins: mmc2-4bit-pins { - pins = "PC6", "PC7", "PC8", "PC9", - "PC10", "PC11"; - function = "mmc2"; - drive-strength = <30>; - bias-pull-up; - }; - - mmc2_8bit_emmc_pins: mmc2-8bit-emmc-pins { - pins = "PC6", "PC7", "PC8", "PC9", - "PC10", "PC11", "PC12", - "PC13", "PC14", "PC15", - "PC24"; - function = "mmc2"; - drive-strength = <30>; - bias-pull-up; - }; - - mmc3_8bit_emmc_pins: mmc3-8bit-emmc-pins { - pins = "PC6", "PC7", "PC8", "PC9", - "PC10", "PC11", "PC12", - "PC13", "PC14", "PC15", - "PC24"; - function = "mmc3"; - drive-strength = <40>; - bias-pull-up; - }; - - spdif_tx_pin: spdif-tx-pin { - pins = "PH28"; - function = "spdif"; - }; - - uart0_ph_pins: uart0-ph-pins { - pins = "PH20", "PH21"; - function = "uart0"; - }; - }; - - timer@1c20c00 { - compatible = "allwinner,sun4i-a10-timer"; - reg = <0x01c20c00 0xa0>; - interrupts = , - , - , - , - , - ; - clocks = <&osc24M>; - }; - - wdt1: watchdog@1c20ca0 { - compatible = "allwinner,sun6i-a31-wdt"; - reg = <0x01c20ca0 0x20>; - interrupts = ; - clocks = <&osc24M>; - }; - - spdif: spdif@1c21000 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun6i-a31-spdif"; - reg = <0x01c21000 0x400>; - interrupts = ; - clocks = <&ccu CLK_APB1_SPDIF>, <&ccu CLK_SPDIF>; - resets = <&ccu RST_APB1_SPDIF>; - clock-names = "apb", "spdif"; - dmas = <&dma 2>, <&dma 2>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2s0: i2s@1c22000 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun6i-a31-i2s"; - reg = <0x01c22000 0x400>; - interrupts = ; - clocks = <&ccu CLK_APB1_DAUDIO0>, <&ccu CLK_DAUDIO0>; - resets = <&ccu RST_APB1_DAUDIO0>; - clock-names = "apb", "mod"; - dmas = <&dma 3>, <&dma 3>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2s1: i2s@1c22400 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun6i-a31-i2s"; - reg = <0x01c22400 0x400>; - interrupts = ; - clocks = <&ccu CLK_APB1_DAUDIO1>, <&ccu CLK_DAUDIO1>; - resets = <&ccu RST_APB1_DAUDIO1>; - clock-names = "apb", "mod"; - dmas = <&dma 4>, <&dma 4>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - lradc: lradc@1c22800 { - compatible = "allwinner,sun4i-a10-lradc-keys"; - reg = <0x01c22800 0x100>; - interrupts = ; - status = "disabled"; - }; - - rtp: rtp@1c25000 { - compatible = "allwinner,sun6i-a31-ts"; - reg = <0x01c25000 0x100>; - interrupts = ; - #thermal-sensor-cells = <0>; - }; - - uart0: serial@1c28000 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_APB2_UART0>; - resets = <&ccu RST_APB2_UART0>; - dmas = <&dma 6>, <&dma 6>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart1: serial@1c28400 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28400 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_APB2_UART1>; - resets = <&ccu RST_APB2_UART1>; - dmas = <&dma 7>, <&dma 7>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart2: serial@1c28800 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28800 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_APB2_UART2>; - resets = <&ccu RST_APB2_UART2>; - dmas = <&dma 8>, <&dma 8>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart3: serial@1c28c00 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28c00 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_APB2_UART3>; - resets = <&ccu RST_APB2_UART3>; - dmas = <&dma 9>, <&dma 9>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart4: serial@1c29000 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c29000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_APB2_UART4>; - resets = <&ccu RST_APB2_UART4>; - dmas = <&dma 10>, <&dma 10>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart5: serial@1c29400 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c29400 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_APB2_UART5>; - resets = <&ccu RST_APB2_UART5>; - dmas = <&dma 22>, <&dma 22>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c0: i2c@1c2ac00 { - compatible = "allwinner,sun6i-a31-i2c"; - reg = <0x01c2ac00 0x400>; - interrupts = ; - clocks = <&ccu CLK_APB2_I2C0>; - resets = <&ccu RST_APB2_I2C0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c1: i2c@1c2b000 { - compatible = "allwinner,sun6i-a31-i2c"; - reg = <0x01c2b000 0x400>; - interrupts = ; - clocks = <&ccu CLK_APB2_I2C1>; - resets = <&ccu RST_APB2_I2C1>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c2: i2c@1c2b400 { - compatible = "allwinner,sun6i-a31-i2c"; - reg = <0x01c2b400 0x400>; - interrupts = ; - clocks = <&ccu CLK_APB2_I2C2>; - resets = <&ccu RST_APB2_I2C2>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c3: i2c@1c2b800 { - compatible = "allwinner,sun6i-a31-i2c"; - reg = <0x01c2b800 0x400>; - interrupts = ; - clocks = <&ccu CLK_APB2_I2C3>; - resets = <&ccu RST_APB2_I2C3>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - gmac: ethernet@1c30000 { - compatible = "allwinner,sun7i-a20-gmac"; - reg = <0x01c30000 0x1054>; - interrupts = ; - interrupt-names = "macirq"; - clocks = <&ccu CLK_AHB1_EMAC>, <&gmac_tx_clk>; - clock-names = "stmmaceth", "allwinner_gmac_tx"; - resets = <&ccu RST_AHB1_EMAC>; - reset-names = "stmmaceth"; - snps,pbl = <2>; - snps,fixed-burst; - snps,force_sf_dma_mode; - status = "disabled"; - - mdio: mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - crypto: crypto-engine@1c15000 { - compatible = "allwinner,sun6i-a31-crypto", - "allwinner,sun4i-a10-crypto"; - reg = <0x01c15000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_AHB1_SS>, <&ccu CLK_SS>; - clock-names = "ahb", "mod"; - resets = <&ccu RST_AHB1_SS>; - reset-names = "ahb"; - }; - - codec: codec@1c22c00 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun6i-a31-codec"; - reg = <0x01c22c00 0x400>; - interrupts = ; - clocks = <&ccu CLK_APB1_CODEC>, <&ccu CLK_CODEC>; - clock-names = "apb", "codec"; - resets = <&ccu RST_APB1_CODEC>; - dmas = <&dma 15>, <&dma 15>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - timer@1c60000 { - compatible = "allwinner,sun6i-a31-hstimer", - "allwinner,sun7i-a20-hstimer"; - reg = <0x01c60000 0x1000>; - interrupts = , - , - , - ; - clocks = <&ccu CLK_AHB1_HSTIMER>; - resets = <&ccu RST_AHB1_HSTIMER>; - }; - - spi0: spi@1c68000 { - compatible = "allwinner,sun6i-a31-spi"; - reg = <0x01c68000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_AHB1_SPI0>, <&ccu CLK_SPI0>; - clock-names = "ahb", "mod"; - dmas = <&dma 23>, <&dma 23>; - dma-names = "rx", "tx"; - resets = <&ccu RST_AHB1_SPI0>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - spi1: spi@1c69000 { - compatible = "allwinner,sun6i-a31-spi"; - reg = <0x01c69000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_AHB1_SPI1>, <&ccu CLK_SPI1>; - clock-names = "ahb", "mod"; - dmas = <&dma 24>, <&dma 24>; - dma-names = "rx", "tx"; - resets = <&ccu RST_AHB1_SPI1>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - spi2: spi@1c6a000 { - compatible = "allwinner,sun6i-a31-spi"; - reg = <0x01c6a000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_AHB1_SPI2>, <&ccu CLK_SPI2>; - clock-names = "ahb", "mod"; - dmas = <&dma 25>, <&dma 25>; - dma-names = "rx", "tx"; - resets = <&ccu RST_AHB1_SPI2>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - spi3: spi@1c6b000 { - compatible = "allwinner,sun6i-a31-spi"; - reg = <0x01c6b000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_AHB1_SPI3>, <&ccu CLK_SPI3>; - clock-names = "ahb", "mod"; - dmas = <&dma 26>, <&dma 26>; - dma-names = "rx", "tx"; - resets = <&ccu RST_AHB1_SPI3>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - gic: interrupt-controller@1c81000 { - compatible = "arm,gic-400"; - reg = <0x01c81000 0x1000>, - <0x01c82000 0x2000>, - <0x01c84000 0x2000>, - <0x01c86000 0x2000>; - interrupt-controller; - #interrupt-cells = <3>; - interrupts = ; - }; - - fe0: display-frontend@1e00000 { - compatible = "allwinner,sun6i-a31-display-frontend"; - reg = <0x01e00000 0x20000>; - interrupts = ; - clocks = <&ccu CLK_AHB1_FE0>, <&ccu CLK_FE0>, - <&ccu CLK_DRAM_FE0>; - clock-names = "ahb", "mod", - "ram"; - resets = <&ccu RST_AHB1_FE0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - fe0_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - fe0_out_be0: endpoint@0 { - reg = <0>; - remote-endpoint = <&be0_in_fe0>; - }; - - fe0_out_be1: endpoint@1 { - reg = <1>; - remote-endpoint = <&be1_in_fe0>; - }; - }; - }; - }; - - fe1: display-frontend@1e20000 { - compatible = "allwinner,sun6i-a31-display-frontend"; - reg = <0x01e20000 0x20000>; - interrupts = ; - clocks = <&ccu CLK_AHB1_FE1>, <&ccu CLK_FE1>, - <&ccu CLK_DRAM_FE1>; - clock-names = "ahb", "mod", - "ram"; - resets = <&ccu RST_AHB1_FE1>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - fe1_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - fe1_out_be0: endpoint@0 { - reg = <0>; - remote-endpoint = <&be0_in_fe1>; - }; - - fe1_out_be1: endpoint@1 { - reg = <1>; - remote-endpoint = <&be1_in_fe1>; - }; - }; - }; - }; - - be1: display-backend@1e40000 { - compatible = "allwinner,sun6i-a31-display-backend"; - reg = <0x01e40000 0x10000>; - interrupts = ; - clocks = <&ccu CLK_AHB1_BE1>, <&ccu CLK_BE1>, - <&ccu CLK_DRAM_BE1>; - clock-names = "ahb", "mod", - "ram"; - resets = <&ccu RST_AHB1_BE1>; - - assigned-clocks = <&ccu CLK_BE1>; - assigned-clock-rates = <300000000>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - be1_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - be1_in_fe0: endpoint@0 { - reg = <0>; - remote-endpoint = <&fe0_out_be1>; - }; - - be1_in_fe1: endpoint@1 { - reg = <1>; - remote-endpoint = <&fe1_out_be1>; - }; - }; - - be1_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - be1_out_drc1: endpoint@1 { - reg = <1>; - remote-endpoint = <&drc1_in_be1>; - }; - }; - }; - }; - - drc1: drc@1e50000 { - compatible = "allwinner,sun6i-a31-drc"; - reg = <0x01e50000 0x10000>; - interrupts = ; - clocks = <&ccu CLK_AHB1_DRC1>, <&ccu CLK_IEP_DRC1>, - <&ccu CLK_DRAM_DRC1>; - clock-names = "ahb", "mod", - "ram"; - resets = <&ccu RST_AHB1_DRC1>; - - assigned-clocks = <&ccu CLK_IEP_DRC1>; - assigned-clock-rates = <300000000>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - drc1_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - drc1_in_be1: endpoint@1 { - reg = <1>; - remote-endpoint = <&be1_out_drc1>; - }; - }; - - drc1_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - drc1_out_tcon0: endpoint@0 { - reg = <0>; - remote-endpoint = <&tcon0_in_drc1>; - }; - - drc1_out_tcon1: endpoint@1 { - reg = <1>; - remote-endpoint = <&tcon1_in_drc1>; - }; - }; - }; - }; - - be0: display-backend@1e60000 { - compatible = "allwinner,sun6i-a31-display-backend"; - reg = <0x01e60000 0x10000>; - interrupts = ; - clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_BE0>, - <&ccu CLK_DRAM_BE0>; - clock-names = "ahb", "mod", - "ram"; - resets = <&ccu RST_AHB1_BE0>; - - assigned-clocks = <&ccu CLK_BE0>; - assigned-clock-rates = <300000000>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - be0_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - be0_in_fe0: endpoint@0 { - reg = <0>; - remote-endpoint = <&fe0_out_be0>; - }; - - be0_in_fe1: endpoint@1 { - reg = <1>; - remote-endpoint = <&fe1_out_be0>; - }; - }; - - be0_out: port@1 { - reg = <1>; - - be0_out_drc0: endpoint { - remote-endpoint = <&drc0_in_be0>; - }; - }; - }; - }; - - drc0: drc@1e70000 { - compatible = "allwinner,sun6i-a31-drc"; - reg = <0x01e70000 0x10000>; - interrupts = ; - clocks = <&ccu CLK_AHB1_DRC0>, <&ccu CLK_IEP_DRC0>, - <&ccu CLK_DRAM_DRC0>; - clock-names = "ahb", "mod", - "ram"; - resets = <&ccu RST_AHB1_DRC0>; - - assigned-clocks = <&ccu CLK_IEP_DRC0>; - assigned-clock-rates = <300000000>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - drc0_in: port@0 { - reg = <0>; - - drc0_in_be0: endpoint { - remote-endpoint = <&be0_out_drc0>; - }; - }; - - drc0_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - drc0_out_tcon0: endpoint@0 { - reg = <0>; - remote-endpoint = <&tcon0_in_drc0>; - }; - - drc0_out_tcon1: endpoint@1 { - reg = <1>; - remote-endpoint = <&tcon1_in_drc0>; - }; - }; - }; - }; - - rtc: rtc@1f00000 { - #clock-cells = <1>; - compatible = "allwinner,sun6i-a31-rtc"; - reg = <0x01f00000 0x54>; - interrupts = , - ; - clocks = <&osc32k>; - clock-output-names = "osc32k"; - }; - - nmi_intc: interrupt-controller@1f00c00 { - compatible = "allwinner,sun6i-a31-r-intc"; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x01f00c00 0x400>; - interrupts = ; - }; - - prcm@1f01400 { - compatible = "allwinner,sun6i-a31-prcm"; - reg = <0x01f01400 0x200>; - - ar100: ar100_clk { - compatible = "allwinner,sun6i-a31-ar100-clk"; - #clock-cells = <0>; - clocks = <&rtc 0>, <&osc24M>, - <&ccu CLK_PLL_PERIPH>, - <&ccu CLK_PLL_PERIPH>; - clock-output-names = "ar100"; - }; - - ahb0: ahb0_clk { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clock-div = <1>; - clock-mult = <1>; - clocks = <&ar100>; - clock-output-names = "ahb0"; - }; - - apb0: apb0_clk { - compatible = "allwinner,sun6i-a31-apb0-clk"; - #clock-cells = <0>; - clocks = <&ahb0>; - clock-output-names = "apb0"; - }; - - apb0_gates: apb0_gates_clk { - compatible = "allwinner,sun6i-a31-apb0-gates-clk"; - #clock-cells = <1>; - clocks = <&apb0>; - clock-output-names = "apb0_pio", "apb0_ir", - "apb0_timer", "apb0_p2wi", - "apb0_uart", "apb0_1wire", - "apb0_i2c"; - }; - - ir_clk: ir_clk { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - clocks = <&rtc 0>, <&osc24M>; - clock-output-names = "ir"; - }; - - apb0_rst: apb0_rst { - compatible = "allwinner,sun6i-a31-clock-reset"; - #reset-cells = <1>; - }; - }; - - cpucfg@1f01c00 { - compatible = "allwinner,sun6i-a31-cpuconfig"; - reg = <0x01f01c00 0x300>; - }; - - ir: ir@1f02000 { - compatible = "allwinner,sun6i-a31-ir"; - clocks = <&apb0_gates 1>, <&ir_clk>; - clock-names = "apb", "ir"; - resets = <&apb0_rst 1>; - interrupts = ; - reg = <0x01f02000 0x40>; - status = "disabled"; - }; - - r_pio: pinctrl@1f02c00 { - compatible = "allwinner,sun6i-a31-r-pinctrl"; - reg = <0x01f02c00 0x400>; - interrupts = , - ; - clocks = <&apb0_gates 0>, <&osc24M>, <&rtc 0>; - clock-names = "apb", "hosc", "losc"; - resets = <&apb0_rst 0>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <3>; - #gpio-cells = <3>; - - s_ir_rx_pin: s-ir-rx-pin { - pins = "PL4"; - function = "s_ir"; - }; - - s_p2wi_pins: s-p2wi-pins { - pins = "PL0", "PL1"; - function = "s_p2wi"; - }; - }; - - p2wi: i2c@1f03400 { - compatible = "allwinner,sun6i-a31-p2wi"; - reg = <0x01f03400 0x400>; - interrupts = ; - clocks = <&apb0_gates 3>; - clock-frequency = <100000>; - resets = <&apb0_rst 3>; - pinctrl-names = "default"; - pinctrl-0 = <&s_p2wi_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/sun6i-a31s-colorfly-e708-q1.dts b/sys/gnu/dts/arm/sun6i-a31s-colorfly-e708-q1.dts deleted file mode 100644 index a2ef7846e2c..00000000000 --- a/sys/gnu/dts/arm/sun6i-a31s-colorfly-e708-q1.dts +++ /dev/null @@ -1,72 +0,0 @@ -/* - * Copyright 2016 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun6i-a31s.dtsi" -#include "sun6i-reference-design-tablet.dtsi" - -/ { - model = "Colorfly E708 Q1 tablet"; - compatible = "colorfly,e708-q1", "allwinner,sun6i-a31s"; -}; - -&lradc { - vref-supply = <®_aldo3>; - status = "okay"; - - button-1000 { - label = "Home"; - linux,code = ; - channel = <0>; - voltage = <1000000>; - }; -}; - -®_dldo2 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc-pg"; -}; - -&simplefb_lcd { - vcc-pg-supply = <®_dldo2>; -}; diff --git a/sys/gnu/dts/arm/sun6i-a31s-cs908.dts b/sys/gnu/dts/arm/sun6i-a31s-cs908.dts deleted file mode 100644 index 1d15e15011c..00000000000 --- a/sys/gnu/dts/arm/sun6i-a31s-cs908.dts +++ /dev/null @@ -1,104 +0,0 @@ -/* - * Copyright 2014 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun6i-a31s.dtsi" - -/ { - model = "CSQ CS908 top set box"; - compatible = "csq,cs908", "allwinner,sun6i-a31s"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_mii_pins>; - phy-handle = <&phy1>; - phy-mode = "mii"; - status = "okay"; -}; - -&ir { - pinctrl-names = "default"; - pinctrl-0 = <&s_ir_rx_pin>; - status = "okay"; -}; - -&mdio { - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&ohci1 { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_ph_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "host"; - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun6i-a31s-inet-q972.dts b/sys/gnu/dts/arm/sun6i-a31s-inet-q972.dts deleted file mode 100644 index c5e2c55cdc6..00000000000 --- a/sys/gnu/dts/arm/sun6i-a31s-inet-q972.dts +++ /dev/null @@ -1,98 +0,0 @@ -/* - * Copyright 2016 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun6i-a31s.dtsi" -#include "sun6i-reference-design-tablet.dtsi" - -/ { - model = "iNet Q972 tablet"; - compatible = "inet-tek,inet-q972", "allwinner,sun6i-a31s"; -}; - -&ehci1 { - status = "okay"; -}; - -&i2c1 { - status = "okay"; - - ft5406ee8: touchscreen@38 { - compatible = "edt,edt-ft5406"; - reg = <0x38>; - interrupt-parent = <&pio>; - interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>; /* PA3 */ - touchscreen-size-x = <768>; - touchscreen-size-y = <1024>; - touchscreen-swapped-x-y; - }; -}; - -&lradc { - vref-supply = <®_aldo3>; - status = "okay"; - - button-200 { - label = "Volume Down"; - linux,code = ; - channel = <0>; - voltage = <200000>; - }; - - button-900 { - label = "Volume Up"; - linux,code = ; - channel = <0>; - voltage = <900000>; - }; - - button-1200 { - label = "Back"; - linux,code = ; - channel = <0>; - voltage = <1200000>; - }; -}; - -&ohci1 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun6i-a31s-primo81.dts b/sys/gnu/dts/arm/sun6i-a31s-primo81.dts deleted file mode 100644 index bc3170a0b8b..00000000000 --- a/sys/gnu/dts/arm/sun6i-a31s-primo81.dts +++ /dev/null @@ -1,268 +0,0 @@ -/* - * Copyright 2014 Siarhei Siamashka - * Copyright 2015 Karsten Merker - * Copyright 2015 Chen-Yu Tsai - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun6i-a31s.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include - -/ { - model = "MSI Primo81 tablet"; - compatible = "msi,primo81", "allwinner,sun6i-a31s"; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "c"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; -}; - -&cpu0 { - cpu-supply = <®_dcdc3>; -}; - -&de { - status = "okay"; -}; - -&ehci0 { - /* rtl8188etv wifi is connected here */ - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&i2c0 { - /* pull-ups and device VDDIO use AXP221 DLDO3 */ - status = "failed"; -}; - -&i2c1 { - status = "okay"; - - ctp@5d { - compatible = "goodix,gt911"; - reg = <0x5d>; - interrupt-parent = <&pio>; - interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>; /* PA3 */ - touchscreen-swapped-x-y; - }; -}; - -&i2c2 { - status = "okay"; - - accelerometer@1c { - pinctrl-names = "default"; - pinctrl-0 = <&mma8452_int_primo81>; - compatible = "fsl,mma8452"; - reg = <0x1c>; - interrupt-parent = <&pio>; - interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; /* PA9 */ - #io-channel-cells = <1>; - }; -}; - -&lradc { - vref-supply = <®_aldo3>; - status = "okay"; - - button-158 { - label = "Volume Up"; - linux,code = ; - channel = <0>; - voltage = <158730>; - }; - - button-349 { - label = "Volume Down"; - linux,code = ; - channel = <0>; - voltage = <349206>; - }; -}; - -&mmc0 { - vmmc-supply = <®_dcdc1>; - bus-width = <4>; - cd-gpios = <&pio 0 8 GPIO_ACTIVE_LOW>; /* PA8 */ - status = "okay"; -}; - -&pio { - mma8452_int_primo81: mma8452-int-pin { - pins = "PA9"; - function = "gpio_in"; - bias-pull-up; - }; -}; - -&p2wi { - status = "okay"; - - axp22x: pmic@68 { - compatible = "x-powers,axp221"; - reg = <0x68>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - x-powers,drive-vbus-en; - }; -}; - -#include "axp22x.dtsi" - -&battery_power_supply { - status = "okay"; -}; - -®_aldo3 { - regulator-always-on; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <3300000>; - regulator-name = "avcc"; -}; - -®_dc1sw { - regulator-name = "vcc-lcd"; -}; - -®_dc5ldo { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-cpus"; /* This is an educated guess */ -}; - -®_dcdc1 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-3v0"; -}; - -®_dcdc2 { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-gpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc4 { - regulator-always-on; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-sys-dll"; -}; - -®_dcdc5 { - regulator-always-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vcc-dram"; -}; - -®_dldo1 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi"; -}; - -®_dldo3 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-name = "vddio-csi"; -}; - -®_drivevbus { - regulator-name = "usb0-vbus"; - status = "okay"; -}; - -®_eldo3 { - regulator-min-microvolt = <1080000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-mipi-bridge"; -}; - -&simplefb_lcd { - vcc-lcd-supply = <®_dc1sw>; - vdd-mipi-bridge-supply = <®_eldo3>; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usb_power_supply { - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 0 15 GPIO_ACTIVE_HIGH>; /* PA15 */ - usb0_vbus_power-supply = <&usb_power_supply>; - usb0_vbus-supply = <®_drivevbus>; - usb1_vbus-supply = <®_dldo1>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun6i-a31s-sina31s-core.dtsi b/sys/gnu/dts/arm/sun6i-a31s-sina31s-core.dtsi deleted file mode 100644 index 3099491de8c..00000000000 --- a/sys/gnu/dts/arm/sun6i-a31s-sina31s-core.dtsi +++ /dev/null @@ -1,141 +0,0 @@ -/* - * Copyright 2015 Chen-Yu Tsai - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun6i-a31s.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include - -/ { - model = "Sinlinx SinA31s Core Board"; - compatible = "sinlinx,sina31s", "allwinner,sun6i-a31s"; - - aliases { - serial0 = &uart0; - }; -}; - -&cpu0 { - cpu-supply = <®_dcdc3>; -}; - -/* eMMC on core board */ -&mmc3 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc3_8bit_emmc_pins>; - vmmc-supply = <®_dcdc1>; - vqmmc-supply = <®_dcdc1>; - bus-width = <8>; - non-removable; - cap-mmc-hw-reset; - status = "okay"; -}; - -/* AXP221s PMIC on core board */ -&p2wi { - status = "okay"; - - axp22x: pmic@68 { - compatible = "x-powers,axp221"; - reg = <0x68>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -#include "axp22x.dtsi" - -®_aldo3 { - regulator-always-on; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <3300000>; - regulator-name = "avcc"; -}; - -®_dc5ldo { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-cpus"; -}; - -®_dcdc1 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-3v0"; -}; - -®_dcdc2 { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-gpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc4 { - regulator-always-on; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-sys-dll"; -}; - -®_dcdc5 { - regulator-always-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vcc-dram"; -}; - -/* UART0 pads available on core board */ -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_ph_pins>; - status = "okay"; -}; - diff --git a/sys/gnu/dts/arm/sun6i-a31s-sina31s.dts b/sys/gnu/dts/arm/sun6i-a31s-sina31s.dts deleted file mode 100644 index 0af48e143b6..00000000000 --- a/sys/gnu/dts/arm/sun6i-a31s-sina31s.dts +++ /dev/null @@ -1,195 +0,0 @@ -/* - * Copyright 2015 Chen-Yu Tsai - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/* The SinA31s development board has the SinA31s core board soldered on */ -#include "sun6i-a31s-sina31s-core.dtsi" - -#include - -/ { - model = "Sinlinx SinA31s Development Board"; - compatible = "sinlinx,sina31s-sdk", "allwinner,sun6i-a31s"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - status { - label = "sina31s:status:usr"; - gpios = <&pio 7 13 GPIO_ACTIVE_HIGH>; /* PH13 */ - }; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "On-board SPDIF"; - simple-audio-card,cpu { - sound-dai = <&spdif>; - }; - - simple-audio-card,codec { - sound-dai = <&spdif_out>; - }; - }; - - spdif_out: spdif-out { - #sound-dai-cells = <0>; - compatible = "linux,spdif-dit"; - }; -}; - -&codec { - allwinner,audio-routing = - "Line Out", "LINEOUT", - "MIC1", "Mic", - "Mic", "MBIAS"; - status = "okay"; -}; - -&de { - status = "okay"; -}; - -&ehci0 { - /* USB 2.0 4 port hub IC */ - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_mii_pins>; - phy-handle = <&phy1>; - phy-mode = "mii"; - phy-supply = <®_dldo1>; - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&ir { - pinctrl-names = "default"; - pinctrl-0 = <&s_ir_rx_pin>; - status = "okay"; -}; - -&lradc { - vref-supply = <®_aldo3>; - status = "okay"; - - button-158 { - label = "Volume Up"; - linux,code = ; - channel = <0>; - voltage = <158730>; - }; - - button-349 { - label = "Volume Down"; - linux,code = ; - channel = <0>; - voltage = <349206>; - }; -}; - -&mdio { - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&mmc0 { - vmmc-supply = <®_dcdc1>; - bus-width = <4>; - cd-gpios = <&pio 0 4 GPIO_ACTIVE_LOW>; /* PA4 */ - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -®_dldo1 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-gmac-phy"; -}; - -&spdif { - pinctrl-names = "default"; - pinctrl-0 = <&spdif_tx_pin>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "peripheral"; - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun6i-a31s-sinovoip-bpi-m2.dts b/sys/gnu/dts/arm/sun6i-a31s-sinovoip-bpi-m2.dts deleted file mode 100644 index 708caee5242..00000000000 --- a/sys/gnu/dts/arm/sun6i-a31s-sinovoip-bpi-m2.dts +++ /dev/null @@ -1,263 +0,0 @@ -/* - * Copyright 2015 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun6i-a31s.dtsi" -#include - -/ { - model = "Sinovoip BPI-M2"; - compatible = "sinovoip,bpi-m2", "allwinner,sun6i-a31s"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - blue { - label = "bpi-m2:blue:usr"; - gpios = <&pio 6 11 GPIO_ACTIVE_HIGH>; /* PG11 */ - }; - - green { - label = "bpi-m2:green:usr"; - gpios = <&pio 6 10 GPIO_ACTIVE_HIGH>; /* PG10 */ - }; - - red { - label = "bpi-m2:red:usr"; - gpios = <&pio 6 5 GPIO_ACTIVE_HIGH>; /* PG5 */ - }; - }; - - mmc2_pwrseq: mmc2_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&r_pio 0 8 GPIO_ACTIVE_LOW>; /* PL8 WIFI_EN */ - }; -}; - -&cpu0 { - cpu-supply = <®_dcdc3>; -}; - -&ehci0 { - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_rgmii_pins>; - phy-handle = <&phy1>; - phy-mode = "rgmii"; - phy-supply = <®_dldo1>; - status = "okay"; -}; - -&ir { - pinctrl-names = "default"; - pinctrl-0 = <&s_ir_rx_pin>; - status = "okay"; -}; - -&mdio { - phy1: ethernet-phy@1 { - reg = <1>; - reset-gpios = <&pio 0 21 GPIO_ACTIVE_LOW>; /* PA21 */ - reset-assert-us = <10000>; - reset-deassert-us = <30000>; - }; -}; - -&mmc0 { - vmmc-supply = <®_dcdc1>; - bus-width = <4>; - cd-gpios = <&pio 0 4 GPIO_ACTIVE_LOW>; /* PA4 */ - status = "okay"; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_4bit_pins>; - vmmc-supply = <®_aldo1>; - mmc-pwrseq = <&mmc2_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - interrupt-parent = <&r_pio>; - interrupts = <0 5 IRQ_TYPE_LEVEL_LOW>; /* PL5 */ - interrupt-names = "host-wake"; - }; -}; - -&ohci0 { - status = "okay"; -}; - -&p2wi { - status = "okay"; - - axp22x: pmic@68 { - compatible = "x-powers,axp221"; - reg = <0x68>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - eldoin-supply = <®_dcdc1>; - x-powers,drive-vbus-en; - }; -}; - -#include "axp22x.dtsi" - -®_aldo1 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi"; -}; - -®_aldo2 { - regulator-always-on; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-name = "vcc-gmac"; -}; - -®_aldo3 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_dc5ldo { - regulator-always-on; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-cpus"; -}; - -®_dcdc1 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vdd-3v0"; -}; - -®_dcdc2 { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-gpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc4 { - regulator-always-on; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-sys-dll"; -}; - -®_dcdc5 { - regulator-always-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vcc-dram"; -}; - -®_dldo1 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-mac"; -}; - -®_dldo2 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-name = "avdd-csi"; -}; - -®_dldo3 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-pb"; -}; - -®_eldo1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vdd-csi"; - status = "okay"; -}; - -®_ldo_io1 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc-pm-cpus"; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_ph_pins>; - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun6i-a31s-yones-toptech-bs1078-v2.dts b/sys/gnu/dts/arm/sun6i-a31s-yones-toptech-bs1078-v2.dts deleted file mode 100644 index 2504e7189c5..00000000000 --- a/sys/gnu/dts/arm/sun6i-a31s-yones-toptech-bs1078-v2.dts +++ /dev/null @@ -1,182 +0,0 @@ -/* - * Copyright 2015 Lawrence Yu - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun6i-a31s.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include - -/ { - model = "Yones TopTech BS1078 v2 Tablet"; - compatible = "yones-toptech,bs1078-v2", "allwinner,sun6i-a31s"; - - aliases { - serial0 = &uart0; - i2c1 = &i2c1; - i2c2 = &i2c2; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v0>; - bus-width = <4>; - cd-gpios = <&pio 0 8 GPIO_ACTIVE_LOW>; /* PA8 */ - status = "okay"; -}; - -&p2wi { - status = "okay"; - - axp22x: pmic@68 { - compatible = "x-powers,axp221"; - reg = <0x68>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -#include "axp22x.dtsi" - -®_aldo3 { - regulator-always-on; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <3300000>; - regulator-name = "avcc"; -}; - -®_dc1sw { - regulator-name = "vcc-lcd-usb2"; -}; - -®_dc5ldo { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-cpus"; -}; - -®_dcdc1 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-3v0"; -}; - -®_dcdc2 { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-gpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc4 { - regulator-always-on; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-sys-dll"; -}; - -®_dcdc5 { - regulator-always-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vcc-dram"; -}; - -®_dldo1 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi"; -}; - -/* Voltage source for I2C pullup resistors for I2C Bus 0 */ -®_dldo3 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-name = "vddio-csi"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_ph_pins>; - status = "okay"; -}; - -&usbphy { - usb1_vbus-supply = <®_dldo1>; - usb2_vbus-supply = <®_dc1sw>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun6i-a31s.dtsi b/sys/gnu/dts/arm/sun6i-a31s.dtsi deleted file mode 100644 index 97e2c51d0ae..00000000000 --- a/sys/gnu/dts/arm/sun6i-a31s.dtsi +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright 2014 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/* - * The A31s is the same die as the A31 in a different package, this is - * reflected by it having different pinctrl compatible everything else is - * identical. - */ - -#include "sun6i-a31.dtsi" - -&de { - compatible = "allwinner,sun6i-a31s-display-engine"; -}; - -&pio { - compatible = "allwinner,sun6i-a31s-pinctrl"; -}; - -&tcon0 { - compatible = "allwinner,sun6i-a31s-tcon"; -}; diff --git a/sys/gnu/dts/arm/sun6i-reference-design-tablet.dtsi b/sys/gnu/dts/arm/sun6i-reference-design-tablet.dtsi deleted file mode 100644 index 7de2abd541c..00000000000 --- a/sys/gnu/dts/arm/sun6i-reference-design-tablet.dtsi +++ /dev/null @@ -1,173 +0,0 @@ -/* - * Copyright 2016 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "sunxi-common-regulators.dtsi" - -#include -#include - -/ { - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&cpu0 { - cpu-supply = <®_dcdc3>; -}; - -&ehci0 { - /* Wifi is connected here */ - status = "okay"; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; - vmmc-supply = <®_dcdc1>; - bus-width = <4>; - cd-gpios = <&pio 0 8 GPIO_ACTIVE_LOW>; /* PA8 */ - status = "okay"; -}; - -&p2wi { - status = "okay"; - - axp22x: pmic@68 { - compatible = "x-powers,axp221"; - reg = <0x68>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - drivevbus-supply = <®_vcc5v0>; - x-powers,drive-vbus-en; - }; -}; - -#include "axp22x.dtsi" - -®_aldo3 { - regulator-always-on; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <3300000>; - regulator-name = "avcc"; -}; - -®_dc1sw { - regulator-name = "vcc-lcd"; -}; - -®_dc5ldo { - regulator-always-on; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-cpus"; /* This is an educated guess */ -}; - -®_dcdc1 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-3v0"; -}; - -®_dcdc2 { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-gpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc4 { - regulator-always-on; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-sys-dll"; -}; - -®_dcdc5 { - regulator-always-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vcc-dram"; -}; - -®_dldo1 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi"; -}; - -®_drivevbus { - regulator-name = "usb0-vbus"; - status = "okay"; -}; - -&simplefb_lcd { - vcc-lcd-supply = <®_dc1sw>; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usb_power_supply { - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 0 15 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PA15 */ - usb0_vbus_power-supply = <&usb_power_supply>; - usb0_vbus-supply = <®_drivevbus>; - usb1_vbus-supply = <®_dldo1>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun7i-a20-bananapi-m1-plus.dts b/sys/gnu/dts/arm/sun7i-a20-bananapi-m1-plus.dts deleted file mode 100644 index 32d5d45a35c..00000000000 --- a/sys/gnu/dts/arm/sun7i-a20-bananapi-m1-plus.dts +++ /dev/null @@ -1,264 +0,0 @@ -/* - * Copyright 2016 Luo Yi - * - * Thanks to the original work by Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun7i-a20.dtsi" -#include "sunxi-common-regulators.dtsi" -#include -#include - -/ { - model = "Banana Pi BPI-M1-Plus"; - compatible = "sinovoip,bpi-m1-plus", "allwinner,sun7i-a20"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - green { - label = "bananapi-m1-plus:green:usr"; - gpios = <&pio 7 24 GPIO_ACTIVE_HIGH>; - }; - - pwr { - label = "bananapi-m1-plus:pwr:usr"; - gpios = <&pio 7 25 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; - - mmc3_pwrseq: mmc3_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&pio 7 22 GPIO_ACTIVE_LOW>; /* PH22 WL-PMU-EN */ - }; - - reg_gmac_3v3: gmac-3v3 { - compatible = "regulator-fixed"; - regulator-name = "gmac-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <100000>; - enable-active-high; - gpio = <&pio 7 23 GPIO_ACTIVE_HIGH>; - }; -}; - -&ahci { - status = "okay"; -}; - -&codec { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&de { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_rgmii_pins>; - phy-handle = <&phy1>; - phy-mode = "rgmii"; - phy-supply = <®_gmac_3v3>; - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -#include "axp209.dtsi" - -&ac_power_supply { - status = "okay"; -}; - -&ir0 { - pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pin>; - status = "okay"; -}; - -&gmac_mdio { - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 10 GPIO_ACTIVE_LOW>; /* PH10 */ - status = "okay"; -}; - -&mmc3 { - #address-cells = <1>; - #size-cells = <0>; - vmmc-supply = <®_vcc3v3>; - mmc-pwrseq = <&mmc3_pwrseq>; - bus-width = <4>; - non-removable; - wakeup-source; - status = "okay"; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - interrupt-parent = <&pio>; - interrupts = <7 15 IRQ_TYPE_LEVEL_LOW>; - interrupt-names = "host-wake"; - }; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-int-dll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_usb0_vbus { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usb_power_supply { - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ - usb0_vbus_power-supply = <&usb_power_supply>; - usb0_vbus-supply = <®_usb0_vbus>; - /* VBUS on usb host ports are tied to DC5V and therefore always on */ - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun7i-a20-bananapi.dts b/sys/gnu/dts/arm/sun7i-a20-bananapi.dts deleted file mode 100644 index bb3987e101c..00000000000 --- a/sys/gnu/dts/arm/sun7i-a20-bananapi.dts +++ /dev/null @@ -1,334 +0,0 @@ -/* - * Copyright 2014 Hans de Goede - * - * Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun7i-a20.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include - -/ { - model = "LeMaker Banana Pi"; - compatible = "lemaker,bananapi", "allwinner,sun7i-a20"; - - aliases { - serial0 = &uart0; - serial1 = &uart3; - serial2 = &uart7; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - green { - label = "bananapi:green:usr"; - gpios = <&pio 7 24 GPIO_ACTIVE_HIGH>; - }; - }; - - reg_gmac_3v3: gmac-3v3 { - compatible = "regulator-fixed"; - regulator-name = "gmac-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <100000>; - enable-active-high; - gpio = <&pio 7 23 GPIO_ACTIVE_HIGH>; - }; -}; - -&ahci { - status = "okay"; -}; - -&codec { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; - operating-points = < - /* kHz uV */ - 960000 1400000 - 912000 1400000 - 864000 1350000 - 720000 1250000 - 528000 1150000 - 312000 1100000 - 144000 1050000 - >; -}; - -&de { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_rgmii_pins>; - phy-handle = <&phy1>; - phy-mode = "rgmii"; - phy-supply = <®_gmac_3v3>; - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&i2c2 { - status = "okay"; -}; - -&ir0 { - pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pin>; - status = "okay"; -}; - -&gmac_mdio { - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 10 GPIO_ACTIVE_LOW>; /* PH10 */ - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pio { - vcc-pa-supply = <®_vcc3v3>; - vcc-pc-supply = <®_vcc3v3>; - vcc-pe-supply = <®_vcc3v3>; - vcc-pf-supply = <®_vcc3v3>; - vcc-pg-supply = <®_vcc3v3>; - gpio-line-names = - /* PA */ - "ERXD3", "ERXD2", "ERXD1", "ERXD0", "ETXD3", - "ETXD2", "ETXD1", "ETXD0", - "ERXCK", "ERXERR", "ERXDV", "EMDC", "EMDIO", - "ETXEN", "ETXCK", "ECRS", - "ECOL", "ETXERR", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - /* PB */ - "PMU-SCK", "PMU-SDA", "", "", "", "", "", "", - "", "USB0-DRV", "", "", "", "", "", "", - "", "", "", "", "SCL", "SDA", "", "", - "", "", "", "", "", "", "", "", - /* PC */ - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - /* PD */ - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - /* PE */ - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - /* PF */ - "SD0-D1", "SD0-D0", "SD0-CLK", "SD0-CMD", "SD0-D3", - "SD0-D2", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - /* PG */ - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - /* PH */ - "TXD0", "RXD0", "IO-1", "PH3", "USB0-IDDET", "PH5", "", "", - "", "", "SD0-DET", "", "", "", "", "", - "", "", "", "", "IO-4", "IO-5", "", "EMAC-PWR-EN", - "LED1", "", "", "", "", "", "", "", - /* PI */ - "", "", "", "IO-GCLK", "", "", "", "", - "", "", "SPI-CE0", "SPI-CLK", "SPI-MOSI", - "SPI-MISO", "SPI-CE1", "", - "IO-6", "IO-3", "IO-2", "IO-0", "", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -#include "axp209.dtsi" - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-int-dll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_usb0_vbus { - status = "okay"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pi_pins>, - <&spi0_cs0_pi_pin>, - <&spi0_cs1_pi_pin>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_ph_pins>; - status = "okay"; -}; - -&uart7 { - pinctrl-names = "default"; - pinctrl-0 = <&uart7_pi_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usb_power_supply { - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ - usb0_vbus_power-supply = <&usb_power_supply>; - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun7i-a20-bananapro.dts b/sys/gnu/dts/arm/sun7i-a20-bananapro.dts deleted file mode 100644 index 01ccff75699..00000000000 --- a/sys/gnu/dts/arm/sun7i-a20-bananapro.dts +++ /dev/null @@ -1,219 +0,0 @@ -/* - * Copyright 2015 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun7i-a20.dtsi" -#include "sunxi-common-regulators.dtsi" -#include -#include - -/ { - model = "LeMaker Banana Pro"; - compatible = "lemaker,bananapro", "allwinner,sun7i-a20"; - - aliases { - serial0 = &uart0; - serial1 = &uart4; - serial2 = &uart7; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - blue { - label = "bananapro:blue:usr"; - gpios = <&pio 6 2 GPIO_ACTIVE_HIGH>; - }; - - green { - label = "bananapro:green:usr"; - gpios = <&pio 7 24 GPIO_ACTIVE_HIGH>; - }; - }; - - wifi_pwrseq: wifi-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&pio 7 22 GPIO_ACTIVE_LOW>; - }; - - reg_gmac_3v3: gmac-3v3 { - compatible = "regulator-fixed"; - regulator-name = "gmac-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <100000>; - enable-active-high; - gpio = <&pio 7 23 GPIO_ACTIVE_HIGH>; - }; -}; - -&ahci { - status = "okay"; -}; - -&codec { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_rgmii_pins>; - phy-handle = <&phy1>; - phy-mode = "rgmii"; - phy-supply = <®_gmac_3v3>; - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - compatible = "x-powers,axp209"; - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - - interrupt-controller; - #interrupt-cells = <1>; - }; -}; - -&i2c2 { - status = "okay"; -}; - -&ir0 { - pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pin>; - status = "okay"; -}; - -&gmac_mdio { - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 10 GPIO_ACTIVE_LOW>; /* PH10 */ - status = "okay"; -}; - -&mmc3 { - vmmc-supply = <®_vcc3v3>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - interrupt-parent = <&pio>; - interrupts = <7 15 IRQ_TYPE_LEVEL_LOW>; - interrupt-names = "host-wake"; - }; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -®_usb1_vbus { - gpio = <&pio 7 0 GPIO_ACTIVE_HIGH>; /* PH0 */ - status = "okay"; -}; - -®_usb2_vbus { - gpio = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - status = "okay"; -}; - -&spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pi_pins>, - <&spi0_cs0_pi_pin>, - <&spi0_cs1_pi_pin>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&uart4_ph_pins>; - status = "okay"; -}; - -&uart7 { - pinctrl-names = "default"; - pinctrl-0 = <&uart7_pi_pins>; - status = "okay"; -}; - -&usbphy { - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun7i-a20-cubieboard2.dts b/sys/gnu/dts/arm/sun7i-a20-cubieboard2.dts deleted file mode 100644 index b8203e4ef21..00000000000 --- a/sys/gnu/dts/arm/sun7i-a20-cubieboard2.dts +++ /dev/null @@ -1,237 +0,0 @@ -/* - * Copyright 2013 Maxime Ripard - * - * Maxime Ripard - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun7i-a20.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include - -/ { - model = "Cubietech Cubieboard2"; - compatible = "cubietech,cubieboard2", "allwinner,sun7i-a20"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - blue { - label = "cubieboard2:blue:usr"; - gpios = <&pio 7 21 GPIO_ACTIVE_HIGH>; - }; - - green { - label = "cubieboard2:green:usr"; - gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&ahci { - target-supply = <®_ahci_5v>; - status = "okay"; -}; - -&codec { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&de { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_mii_pins>; - phy-handle = <&phy1>; - phy-mode = "mii"; - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&i2c1 { - status = "okay"; -}; - -&ir0 { - pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pin>; - status = "okay"; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ - status = "okay"; -}; - -&gmac_mdio { - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -®_ahci_5v { - status = "okay"; -}; - -#include "axp209.dtsi" - -&ac_power_supply { - status = "okay"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1450000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-int-dll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun7i-a20-cubietruck.dts b/sys/gnu/dts/arm/sun7i-a20-cubietruck.dts deleted file mode 100644 index 8c8dee6ea46..00000000000 --- a/sys/gnu/dts/arm/sun7i-a20-cubietruck.dts +++ /dev/null @@ -1,345 +0,0 @@ -/* - * Copyright 2013 Oliver Schinagl - * - * Oliver Schinagl - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun7i-a20.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include - -/ { - model = "Cubietech Cubietruck"; - compatible = "cubietech,cubietruck", "allwinner,sun7i-a20"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - blue { - label = "cubietruck:blue:usr"; - gpios = <&pio 7 21 GPIO_ACTIVE_HIGH>; - }; - - orange { - label = "cubietruck:orange:usr"; - gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>; - }; - - white { - label = "cubietruck:white:usr"; - gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>; - }; - - green { - label = "cubietruck:green:usr"; - gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; - }; - }; - - mmc3_pwrseq: mmc3_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&pio 7 9 GPIO_ACTIVE_LOW>; /* PH9 WIFI_EN */ - clocks = <&ccu CLK_OUT_A>; - clock-names = "ext_clock"; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "On-board SPDIF"; - - simple-audio-card,cpu { - sound-dai = <&spdif>; - }; - - simple-audio-card,codec { - sound-dai = <&spdif_out>; - }; - }; - - spdif_out: spdif-out { - #sound-dai-cells = <0>; - compatible = "linux,spdif-dit"; - }; -}; - -&ahci { - target-supply = <®_ahci_5v>; - status = "okay"; -}; - -&codec { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&de { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_rgmii_pins>; - phy-handle = <&phy1>; - phy-mode = "rgmii"; - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&ir0 { - pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pin>; - status = "okay"; -}; - -&gmac_mdio { - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ - status = "okay"; -}; - -&mmc3 { - vmmc-supply = <®_vcc3v3>; - mmc-pwrseq = <&mmc3_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - interrupt-parent = <&pio>; - interrupts = <7 10 IRQ_TYPE_LEVEL_LOW>; /* PH10 / EINT10 */ - interrupt-names = "host-wake"; - }; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pio { - /* Pin outputs low power clock for WiFi and BT */ - pinctrl-0 = <&clk_out_a_pin>; - pinctrl-names = "default"; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pin>, <&pwm1_pin>; - status = "okay"; -}; - -®_ahci_5v { - gpio = <&pio 7 12 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -#include "axp209.dtsi" - -&ac_power_supply { - status = "okay"; -}; - -&battery_power_supply { - status = "okay"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1450000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-int-dll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_usb0_vbus { - gpio = <&pio 7 17 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&spdif { - pinctrl-names = "default"; - pinctrl-0 = <&spdif_tx_pin>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pi_pins>, <&uart2_cts_rts_pi_pins>; - uart-has-rtscts; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm20702a1"; - clocks = <&ccu CLK_OUT_A>; - clock-names = "lpo"; - device-wakeup-gpios = <&pio 7 24 GPIO_ACTIVE_LOW>; /* PH24 */ - host-wakeup-gpios = <&pio 7 25 GPIO_ACTIVE_LOW>; /* PH25 */ - shutdown-gpios = <&pio 7 18 GPIO_ACTIVE_HIGH>; /* PH18 */ - max-speed = <1500000>; - }; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usb_power_supply { - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 7 19 GPIO_ACTIVE_HIGH>; /* PH19 */ - usb0_vbus_det-gpios = <&pio 7 22 GPIO_ACTIVE_HIGH>; /* PH22 */ - usb0_vbus_power-supply = <&usb_power_supply>; - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun7i-a20-hummingbird.dts b/sys/gnu/dts/arm/sun7i-a20-hummingbird.dts deleted file mode 100644 index 3def2a33059..00000000000 --- a/sys/gnu/dts/arm/sun7i-a20-hummingbird.dts +++ /dev/null @@ -1,233 +0,0 @@ -/* - * Copyright 2013 Wills Wang - * - * Wills Wang - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun7i-a20.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include - -/ { - model = "Merrii A20 Hummingbird"; - compatible = "merrii,a20-hummingbird", "allwinner,sun7i-a20"; - - aliases { - serial0 = &uart0; - serial1 = &uart2; - serial2 = &uart3; - serial3 = &uart4; - serial4 = &uart5; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - reg_mmc3_vdd: mmc3_vdd { - compatible = "regulator-fixed"; - regulator-name = "mmc3_vdd"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - enable-active-high; - gpio = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */ - }; - - reg_gmac_vdd: gmac_vdd { - compatible = "regulator-fixed"; - regulator-name = "gmac_vdd"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - enable-active-high; - gpio = <&pio 7 16 GPIO_ACTIVE_HIGH>; /* PH16 */ - }; -}; - -&ahci { - target-supply = <®_ahci_5v>; - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_rgmii_pins>; - phy-handle = <&phy1>; - phy-mode = "rgmii"; - phy-supply = <®_gmac_vdd>; - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - compatible = "x-powers,axp209"; - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells = <1>; - }; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c3 { - status = "okay"; -}; - -&ir0 { - pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pin>; - status = "okay"; -}; - -&gmac_mdio { - phy1: ethernet-phy@1 { - reg = <1>; - reset-gpios = <&pio 0 17 GPIO_ACTIVE_LOW>; /* PA17 */ - reset-assert-us = <10000>; - /* wait 1s after reset, otherwise fail to read phy id */ - reset-deassert-us = <1000000>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v0>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ - status = "okay"; -}; - -&mmc3 { - vmmc-supply = <®_mmc3_vdd>; - bus-width = <4>; - non-removable; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pin>; - status = "okay"; -}; - -®_ahci_5v { - gpio = <&pio 7 15 GPIO_ACTIVE_HIGH>; /* PH15 */ - status = "okay"; -}; - -®_usb1_vbus { - gpio = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */ - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&spi2 { - pinctrl-names = "default"; - pinctrl-0 = <&spi2_pb_pins>, - <&spi2_cs0_pb_pin>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pi_pins>, <&uart2_cts_rts_pi_pins>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pg_pins>, <&uart3_cts_rts_pg_pins>; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&uart4_pg_pins>; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&uart5_pi_pins>; - status = "okay"; -}; - -&usbphy { - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun7i-a20-i12-tvbox.dts b/sys/gnu/dts/arm/sun7i-a20-i12-tvbox.dts deleted file mode 100644 index 358ed5f1b1c..00000000000 --- a/sys/gnu/dts/arm/sun7i-a20-i12-tvbox.dts +++ /dev/null @@ -1,198 +0,0 @@ -/* - * Copyright 2014 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun7i-a20.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include - -/ { - model = "I12 / Q5 / QT840A A20 tvbox"; - compatible = "allwinner,i12-tvbox", "allwinner,sun7i-a20"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - red { - label = "i12_tvbox:red:usr"; - gpios = <&pio 7 9 GPIO_ACTIVE_LOW>; - }; - - blue { - label = "i12_tvbox:blue:usr"; - gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>; - }; - }; - - reg_vmmc3: vmmc3 { - compatible = "regulator-fixed"; - regulator-name = "vmmc3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpio = <&pio 7 2 GPIO_ACTIVE_HIGH>; - }; - - reg_vmmc3_io: vmmc3-io { - compatible = "regulator-fixed"; - regulator-name = "vmmc3-io"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - /* This controls VCC-PI, must be always on! */ - regulator-always-on; - enable-active-high; - gpio = <&pio 7 12 GPIO_ACTIVE_HIGH>; - }; - - reg_gmac_3v3: gmac-3v3 { - compatible = "regulator-fixed"; - regulator-name = "gmac-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <50000>; - enable-active-high; - gpio = <&pio 7 21 GPIO_ACTIVE_HIGH>; - }; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_mii_pins>; - phy-handle = <&phy1>; - phy-mode = "mii"; - phy-supply = <®_gmac_3v3>; - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - compatible = "x-powers,axp209"; - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - - interrupt-controller; - #interrupt-cells = <1>; - }; -}; - -&ir0 { - pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pin>; - status = "okay"; -}; - -&gmac_mdio { - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ - status = "okay"; -}; - -&mmc3 { - vmmc-supply = <®_vmmc3>; - bus-width = <4>; - non-removable; - status = "okay"; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - interrupt-parent = <&pio>; - interrupts = <7 10 IRQ_TYPE_LEVEL_LOW>; /* PH10 / EINT10 */ - interrupt-names = "host-wake"; - }; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usbphy { - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun7i-a20-icnova-swac.dts b/sys/gnu/dts/arm/sun7i-a20-icnova-swac.dts deleted file mode 100644 index 413505f45a8..00000000000 --- a/sys/gnu/dts/arm/sun7i-a20-icnova-swac.dts +++ /dev/null @@ -1,164 +0,0 @@ -/* - * Copyright 2015 Stefan Roese - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun7i-a20.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include - -/ { - model = "ICnova-A20 SWAC"; - compatible = "incircuit,icnova-a20-swac", "incircuit,icnova-a20", - "allwinner,sun7i-a20"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_mii_pins>; - phy-handle = <&phy1>; - phy-mode = "mii"; - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&i2c1 { - status = "okay"; -}; - -&gmac_mdio { - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 8 5 GPIO_ACTIVE_LOW>; /* PI5 */ - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -#include "axp209.dtsi" - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-int-dll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usbphy { - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun7i-a20-itead-ibox.dts b/sys/gnu/dts/arm/sun7i-a20-itead-ibox.dts deleted file mode 100644 index 946c2727832..00000000000 --- a/sys/gnu/dts/arm/sun7i-a20-itead-ibox.dts +++ /dev/null @@ -1,147 +0,0 @@ -/* - * Copyright 2015 - Marcus Cooper - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun7i-a20.dtsi" -#include "sunxi-itead-core-common.dtsi" - -/ { - model = "Itead Ibox A20"; - compatible = "itead,itead-ibox-a20", "allwinner,sun7i-a20"; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_itead_core>; - - green { - label = "itead_core:green:usr"; - gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - blue { - label = "itead_core:blue:usr"; - gpios = <&pio 7 21 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "On-board SPDIF"; - - simple-audio-card,cpu { - sound-dai = <&spdif>; - }; - - simple-audio-card,codec { - sound-dai = <&spdif_out>; - }; - }; - - spdif_out: spdif-out { - #sound-dai-cells = <0>; - compatible = "linux,spdif-dit"; - }; -}; - -&ahci { - target-supply = <®_ahci_5v>; - status = "okay"; -}; - -&codec { - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_mii_pins>; - phy-handle = <&phy1>; - phy-mode = "mii"; - status = "okay"; -}; - -&gmac_mdio { - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&i2c0 { - axp209: pmic@34 { - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&ir0 { - pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pin>; - status = "okay"; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ - status = "okay"; -}; - -&pio { - led_pins_itead_core: led-pins { - pins = "PH20","PH21"; - function = "gpio_out"; - drive-strength = <20>; - }; -}; - -®_ahci_5v { - status = "okay"; -}; - -&spdif { - pinctrl-names = "default"; - pinctrl-0 = <&spdif_tx_pin>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun7i-a20-lamobo-r1.dts b/sys/gnu/dts/arm/sun7i-a20-lamobo-r1.dts deleted file mode 100644 index 17fa8901fc0..00000000000 --- a/sys/gnu/dts/arm/sun7i-a20-lamobo-r1.dts +++ /dev/null @@ -1,320 +0,0 @@ -/* - * Copyright 2015 Jelle de Jong - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun7i-a20.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include - -/ { - model = "Lamobo R1"; - compatible = "lamobo,lamobo-r1", "allwinner,sun7i-a20"; - - aliases { - serial0 = &uart0; - serial1 = &uart3; - serial2 = &uart7; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - green { - label = "lamobo_r1:green:usr"; - gpios = <&pio 7 24 GPIO_ACTIVE_HIGH>; - }; - }; - - reg_gmac_3v3: gmac-3v3 { - compatible = "regulator-fixed"; - regulator-name = "gmac-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <100000>; - enable-active-high; - gpio = <&pio 7 23 GPIO_ACTIVE_HIGH>; /* PH23 */ - }; -}; - -&ahci { - target-supply = <®_ahci_5v>; - status = "okay"; -}; - -&codec { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&de { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_rgmii_pins>; - phy-mode = "rgmii"; - phy-supply = <®_gmac_3v3>; - status = "okay"; - - fixed-link { - speed = <1000>; - full-duplex; - }; - - mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - switch: ethernet-switch@1e { - compatible = "brcm,bcm53125"; - reg = <30>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port0: port@0 { - reg = <0>; - label = "lan2"; - }; - - port1: port@1 { - reg = <1>; - label = "lan3"; - }; - - port2: port@2 { - reg = <2>; - label = "lan4"; - }; - - port3: port@3 { - reg = <3>; - label = "wan"; - }; - - port4: port@4 { - reg = <4>; - label = "lan1"; - }; - - port8: port@8 { - reg = <8>; - label = "cpu"; - ethernet = <&gmac>; - phy-mode = "rgmii-txid"; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; - }; - }; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&i2c2 { - status = "okay"; -}; - -&ir0 { - pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pin>; - status = "okay"; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 10 GPIO_ACTIVE_LOW>; /* PH10 */ - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -#include "axp209.dtsi" - -&ac_power_supply { - status = "okay"; -}; - -&battery_power_supply { - status = "okay"; -}; - -®_ahci_5v { - gpio = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */ - status = "okay"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-int-dll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_usb0_vbus { - status = "okay"; -}; - -®_usb2_vbus { - gpio = <&pio 7 12 GPIO_ACTIVE_HIGH>; /* PH12 */ - status = "okay"; -}; - -&spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pi_pins>, - <&spi0_cs0_pi_pin>, - <&spi0_cs1_pi_pin>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_ph_pins>; - status = "okay"; -}; - -&uart7 { - pinctrl-names = "default"; - pinctrl-0 = <&uart7_pi_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usb_power_supply { - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ - usb0_vbus_power-supply = <&usb_power_supply>; - usb0_vbus-supply = <®_usb0_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun7i-a20-m3.dts b/sys/gnu/dts/arm/sun7i-a20-m3.dts deleted file mode 100644 index 6bff9e731fc..00000000000 --- a/sys/gnu/dts/arm/sun7i-a20-m3.dts +++ /dev/null @@ -1,156 +0,0 @@ -/* - * Copyright 2014 Hans de Goede - * - * Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun7i-a20.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include - -/ { - model = "Mele M3"; - compatible = "mele,m3", "allwinner,sun7i-a20"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - blue { - label = "m3:blue:usr"; - gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_mii_pins>; - phy-handle = <&phy1>; - phy-mode = "mii"; - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - compatible = "x-powers,axp209"; - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - - interrupt-controller; - #interrupt-cells = <1>; - }; -}; - -&ir0 { - pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pin>; - status = "okay"; -}; - -&gmac_mdio { - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ - status = "okay"; -}; - -&mmc2 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - non-removable; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usbphy { - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun7i-a20-mk808c.dts b/sys/gnu/dts/arm/sun7i-a20-mk808c.dts deleted file mode 100644 index 1491c603f66..00000000000 --- a/sys/gnu/dts/arm/sun7i-a20-mk808c.dts +++ /dev/null @@ -1,184 +0,0 @@ -/* - * Copyright 2015 Marcus Cooper - * - * Marcus Cooper - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun7i-a20.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include - -/ { - model = "mk808c"; - compatible = "allwinner,mk808c", "allwinner,sun7i-a20"; - - aliases { - serial0 = &uart0; - serial1 = &uart2; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; -}; - -&codec { - status = "okay"; -}; - -&de { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - compatible = "x-powers,axp209"; - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells = <1>; - }; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v0>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -®_usb0_vbus { - status = "okay"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pi_pins>, <&uart2_cts_rts_pi_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ - usb0_vbus_det-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun7i-a20-olimex-som-evb-emmc.dts b/sys/gnu/dts/arm/sun7i-a20-olimex-som-evb-emmc.dts deleted file mode 100644 index 20bf09b2226..00000000000 --- a/sys/gnu/dts/arm/sun7i-a20-olimex-som-evb-emmc.dts +++ /dev/null @@ -1,35 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree Source for A20-Olimex-SOM-EVB-eMMC Board - * - * Copyright (C) 2018 Olimex Ltd. - * Author: Stefan Mavrodiev - */ - -/dts-v1/; -#include "sun7i-a20-olimex-som-evb.dts" - -/ { - - model = "Olimex A20-Olimex-SOM-EVB-eMMC"; - compatible = "olimex,a20-olimex-som-evb-emmc", "allwinner,sun7i-a20"; - - mmc2_pwrseq: mmc2_pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&pio 2 18 GPIO_ACTIVE_LOW>; - }; -}; - -&mmc2 { - vmmc-supply = <®_vcc3v3>; - mmc-pwrseq = <&mmc2_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; - - emmc: emmc@0 { - reg = <0>; - compatible = "mmc-card"; - broken-hpi; - }; -}; diff --git a/sys/gnu/dts/arm/sun7i-a20-olimex-som-evb.dts b/sys/gnu/dts/arm/sun7i-a20-olimex-som-evb.dts deleted file mode 100644 index 6f9c54b8e49..00000000000 --- a/sys/gnu/dts/arm/sun7i-a20-olimex-som-evb.dts +++ /dev/null @@ -1,329 +0,0 @@ -/* - * Copyright 2015 - Marcus Cooper - * Copyright 2015 - Karsten Merker - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun7i-a20.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include -#include - -/ { - model = "Olimex A20-Olimex-SOM-EVB"; - compatible = "olimex,a20-olimex-som-evb", "allwinner,sun7i-a20"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - green { - label = "a20-olimex-som-evb:green:usr"; - gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; -}; - -&ahci { - target-supply = <®_ahci_5v>; - status = "okay"; -}; - -&de { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&codec { - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_rgmii_pins>; - phy-handle = <&phy1>; - phy-mode = "rgmii"; - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&lradc { - vref-supply = <®_vcc3v0>; - status = "okay"; - - button-190 { - label = "Volume Up"; - linux,code = ; - channel = <0>; - voltage = <190000>; - }; - - button-390 { - label = "Volume Down"; - linux,code = ; - channel = <0>; - voltage = <390000>; - }; - - button-600 { - label = "Menu"; - linux,code = ; - channel = <0>; - voltage = <600000>; - }; - - button-800 { - label = "Search"; - linux,code = ; - channel = <0>; - voltage = <800000>; - }; - - button-980 { - label = "Home"; - linux,code = ; - channel = <0>; - voltage = <980000>; - }; - - button-1180 { - label = "Esc"; - linux,code = ; - channel = <0>; - voltage = <1180000>; - }; - - button-1400 { - label = "Enter"; - linux,code = ; - channel = <0>; - voltage = <1400000>; - }; -}; - -&gmac_mdio { - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ - status = "okay"; -}; - -&mmc3 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 0 GPIO_ACTIVE_LOW>; /* PH0 */ - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pio { - led_pins_olimex_som_evb: led-pins { - pins = "PH2"; - function = "gpio_out"; - drive-strength = <20>; - }; -}; - -®_ahci_5v { - gpio = <&pio 2 3 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -#include "axp209.dtsi" - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-int-dll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_usb0_vbus { - status = "okay"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&spi1 { - pinctrl-names = "default"; - pinctrl-0 = <&spi1_pi_pins>, - <&spi1_cs0_pi_pin>; - status = "okay"; -}; - -&spi2 { - pinctrl-names = "default"; - pinctrl-0 = <&spi2_pc_pins>, - <&spi2_cs0_pc_pin>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&uart6 { - pinctrl-names = "default"; - pinctrl-0 = <&uart6_pi_pins>; - status = "okay"; -}; - -&uart7 { - pinctrl-names = "default"; - pinctrl-0 = <&uart7_pi_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH04 */ - usb0_vbus_det-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH05 */ - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun7i-a20-olimex-som204-evb-emmc.dts b/sys/gnu/dts/arm/sun7i-a20-olimex-som204-evb-emmc.dts deleted file mode 100644 index a59755a2e7a..00000000000 --- a/sys/gnu/dts/arm/sun7i-a20-olimex-som204-evb-emmc.dts +++ /dev/null @@ -1,34 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree Source for A20-SOM204-EVB-eMMC Board - * - * Copyright (C) 2018 Olimex Ltd. - * Author: Stefan Mavrodiev - */ - -/dts-v1/; -#include "sun7i-a20-olimex-som204-evb.dts" - -/ { - model = "Olimex A20-SOM204-EVB-eMMC"; - compatible = "olimex,a20-olimex-som204-evb-emmc", "allwinner,sun7i-a20"; - - mmc2_pwrseq: mmc2_pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&pio 2 16 GPIO_ACTIVE_LOW>; - }; -}; - -&mmc2 { - vmmc-supply = <®_vcc3v3>; - mmc-pwrseq = <&mmc2_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; - - emmc: emmc@0 { - reg = <0>; - compatible = "mmc-card"; - broken-hpi; - }; -}; diff --git a/sys/gnu/dts/arm/sun7i-a20-olimex-som204-evb.dts b/sys/gnu/dts/arm/sun7i-a20-olimex-som204-evb.dts deleted file mode 100644 index 230d62a6b8f..00000000000 --- a/sys/gnu/dts/arm/sun7i-a20-olimex-som204-evb.dts +++ /dev/null @@ -1,326 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree Source for A20-SOM204-EVB Board - * - * Copyright (C) 2018 Olimex Ltd. - * Author: Stefan Mavrodiev - */ - -/dts-v1/; -#include "sun7i-a20.dtsi" -#include "sunxi-common-regulators.dtsi" - - -#include -#include -#include - -/ { - model = "Olimex A20-SOM204-EVB"; - compatible = "olimex,a20-olimex-som204-evb", "allwinner,sun7i-a20"; - - aliases { - serial0 = &uart0; - serial1 = &uart4; - serial2 = &uart7; - spi0 = &spi1; - spi1 = &spi2; - ethernet1 = &rtl8723bs; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - stat { - label = "a20-som204-evb:green:stat"; - gpios = <&pio 8 0 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - led1 { - label = "a20-som204-evb:green:led1"; - gpios = <&pio 8 10 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - led2 { - label = "a20-som204-evb:yellow:led2"; - gpios = <&pio 8 11 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; - - rtl_pwrseq: rtl_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&pio 6 9 GPIO_ACTIVE_LOW>; - }; -}; - -&ahci { - target-supply = <®_ahci_5v>; - status = "okay"; -}; - -&can0 { - pinctrl-names = "default"; - pinctrl-0 = <&can_ph_pins>; - status = "okay"; -}; - -&codec { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&de { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_rgmii_pins>; - phy-handle = <&phy3>; - phy-mode = "rgmii"; - phy-supply = <®_vcc3v3>; - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -/* Exposed to UEXT1 */ -&i2c1 { - status = "okay"; - - eeprom: eeprom@50 { - compatible = "atmel,24c16"; - reg = <0x50>; - pagesize = <16>; - }; -}; - -/* Exposed to UEXT2 */ -&i2c2 { - status = "okay"; -}; - -&ir0 { - pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pin>; - status = "okay"; -}; - -&gmac_mdio { - phy3: ethernet-phy@3 { - reg = <3>; - reset-gpios = <&pio 0 17 GPIO_ACTIVE_LOW>; /* PA17 */ - reset-assert-us = <10000>; - /* wait 1s after reset, otherwise fail to read phy id */ - reset-deassert-us = <1000000>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&mmc3 { - vmmc-supply = <®_vcc3v3>; - mmc-pwrseq = <&rtl_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; - - rtl8723bs: sdio_wifi@1 { - reg = <1>; - }; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pio { - uart3_rts_pin: uart3-rts-pin { - pins = "PG8"; - function = "uart3"; - }; -}; - -#include "axp209.dtsi" - -&ac_power_supply { - status = "okay"; -}; - -&battery_power_supply { - status = "okay"; -}; - -®_ahci_5v { - gpio = <&pio 2 3 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-int-dll"; -}; - -®_ldo1 { - regulator-always-on; - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_ldo4 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-pg"; -}; - -®_usb0_vbus { - gpio = <&pio 2 17 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -/* Exposed to UEXT1 */ -&spi1 { - pinctrl-names = "default"; - pinctrl-0 = <&spi1_pi_pins>, - <&spi1_cs0_pi_pin>; - status = "okay"; -}; - -/* Exposed to UEXT2 */ -&spi2 { - pinctrl-names = "default"; - pinctrl-0 = <&spi2_pc_pins>, - <&spi2_cs0_pc_pin>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -/* Used for RTL8723BS bluetooth */ -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pg_pins>, <&uart3_rts_pin>; - status = "okay"; -}; - -/* Exposed to UEXT1 */ -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&uart4_pg_pins>; - status = "okay"; -}; - -/* Exposed to UEXT2 */ -&uart7 { - pinctrl-names = "default"; - pinctrl-0 = <&uart7_pi_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usb_power_supply { - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ - usb0_vbus_det-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ - usb0_vbus_power-supply = <&usb_power_supply>; - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun7i-a20-olinuxino-lime.dts b/sys/gnu/dts/arm/sun7i-a20-olinuxino-lime.dts deleted file mode 100644 index 2adbac86011..00000000000 --- a/sys/gnu/dts/arm/sun7i-a20-olinuxino-lime.dts +++ /dev/null @@ -1,216 +0,0 @@ -/* - * This is based on sun4i-a10-olinuxino-lime.dts - * - * Copyright 2014 - Hans de Goede - * Copyright (c) 2014 FUKAUMI Naoki - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun7i-a20.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include - -/ { - model = "Olimex A20-OLinuXino-LIME"; - compatible = "olimex,a20-olinuxino-lime", "allwinner,sun7i-a20"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_olinuxinolime>; - - green { - label = "a20-olinuxino-lime:green:usr"; - gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; -}; - -&ahci { - target-supply = <®_ahci_5v>; - status = "okay"; -}; - -&de { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_mii_pins>; - phy-handle = <&phy1>; - phy-mode = "mii"; - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - compatible = "x-powers,axp209"; - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - - interrupt-controller; - #interrupt-cells = <1>; - }; -}; - -&i2c1 { - status = "okay"; - - eeprom: eeprom@50 { - compatible = "atmel,24c16"; - reg = <0x50>; - pagesize = <16>; - }; -}; - -&gmac_mdio { - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pio { - led_pins_olinuxinolime: led-pins { - pins = "PH2"; - function = "gpio_out"; - drive-strength = <20>; - }; -}; - -®_ahci_5v { - gpio = <&pio 2 3 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -®_usb0_vbus { - status = "okay"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ - usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */ - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun7i-a20-olinuxino-lime2-emmc.dts b/sys/gnu/dts/arm/sun7i-a20-olinuxino-lime2-emmc.dts deleted file mode 100644 index decb014a382..00000000000 --- a/sys/gnu/dts/arm/sun7i-a20-olinuxino-lime2-emmc.dts +++ /dev/null @@ -1,69 +0,0 @@ - /* - * Copyright 2015 - Ultimaker B.V. - * Author Olliver Schinagl - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "sun7i-a20-olinuxino-lime2.dts" - -/ { - model = "Olimex A20-OLinuXino-LIME2-eMMC"; - compatible = "olimex,a20-olinuxino-lime2-emmc", "allwinner,sun7i-a20"; - - mmc2_pwrseq: pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&pio 2 16 GPIO_ACTIVE_LOW>; - }; -}; - -&mmc2 { - vmmc-supply = <®_vcc3v3>; - vqmmc-supply = <®_vcc3v3>; - bus-width = <4>; - non-removable; - mmc-pwrseq = <&mmc2_pwrseq>; - status = "okay"; - - emmc: emmc@0 { - reg = <0>; - compatible = "mmc-card"; - broken-hpi; - }; -}; diff --git a/sys/gnu/dts/arm/sun7i-a20-olinuxino-lime2.dts b/sys/gnu/dts/arm/sun7i-a20-olinuxino-lime2.dts deleted file mode 100644 index 9ba62774e89..00000000000 --- a/sys/gnu/dts/arm/sun7i-a20-olinuxino-lime2.dts +++ /dev/null @@ -1,280 +0,0 @@ -/* - * Copyright 2014 - Iain Paton - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun7i-a20.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include - -/ { - model = "Olimex A20-OLinuXino-LIME2"; - compatible = "olimex,a20-olinuxino-lime2", "allwinner,sun7i-a20"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_olinuxinolime>; - - green { - label = "a20-olinuxino-lime2:green:usr"; - gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; - - reg_axp_ipsout: axp_ipsout { - compatible = "regulator-fixed"; - regulator-name = "axp-ipsout"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; -}; - -&ahci { - target-supply = <®_ahci_5v>; - status = "okay"; -}; - -&de { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_rgmii_pins>; - phy-handle = <&phy1>; - phy-mode = "rgmii"; - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&i2c1 { - status = "okay"; - - eeprom: eeprom@50 { - compatible = "atmel,24c16"; - reg = <0x50>; - pagesize = <16>; - }; -}; - -&lradc { - vref-supply = <®_vcc3v0>; -}; - -&gmac_mdio { - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pio { - vcc-pa-supply = <®_vcc3v3>; - vcc-pc-supply = <®_vcc3v3>; - vcc-pe-supply = <®_ldo3>; - vcc-pf-supply = <®_vcc3v3>; - vcc-pg-supply = <®_ldo4>; - - led_pins_olinuxinolime: led-pins { - pins = "PH2"; - function = "gpio_out"; - drive-strength = <20>; - }; -}; - -®_ahci_5v { - gpio = <&pio 2 3 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -#include "axp209.dtsi" - -&ac_power_supply { - status = "okay"; -}; - -&battery_power_supply { - status = "okay"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-int-dll"; -}; - -®_ldo1 { - regulator-always-on; - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_ldo3 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-name = "vddio-csi0"; - regulator-soft-start; - regulator-ramp-delay = <1600>; -}; - -®_ldo4 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-name = "vddio-csi1"; -}; - -®_usb0_vbus { - gpio = <&pio 2 17 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ - usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */ - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun7i-a20-olinuxino-micro-emmc.dts b/sys/gnu/dts/arm/sun7i-a20-olinuxino-micro-emmc.dts deleted file mode 100644 index 2337b44a88a..00000000000 --- a/sys/gnu/dts/arm/sun7i-a20-olinuxino-micro-emmc.dts +++ /dev/null @@ -1,68 +0,0 @@ - /* - * Copyright 2017 Olimex Ltd. - * Stefan Mavrodiev - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "sun7i-a20-olinuxino-micro.dts" - -/ { - model = "Olimex A20-OLinuXino-MICRO-eMMC"; - compatible = "olimex,a20-olinuxino-micro-emmc", "allwinner,sun7i-a20"; - - mmc2_pwrseq: pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&pio 2 16 GPIO_ACTIVE_LOW>; - }; -}; - -&mmc2 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - non-removable; - mmc-pwrseq = <&mmc2_pwrseq>; - status = "okay"; - - emmc: emmc@0 { - reg = <0>; - compatible = "mmc-card"; - broken-hpi; - }; -}; diff --git a/sys/gnu/dts/arm/sun7i-a20-olinuxino-micro.dts b/sys/gnu/dts/arm/sun7i-a20-olinuxino-micro.dts deleted file mode 100644 index 359bd0d5b3b..00000000000 --- a/sys/gnu/dts/arm/sun7i-a20-olinuxino-micro.dts +++ /dev/null @@ -1,354 +0,0 @@ -/* - * Copyright 2013 Maxime Ripard - * - * Maxime Ripard - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun7i-a20.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include -#include - -/ { - model = "Olimex A20-Olinuxino Micro"; - compatible = "olimex,a20-olinuxino-micro", "allwinner,sun7i-a20"; - - aliases { - serial0 = &uart0; - serial1 = &uart6; - serial2 = &uart7; - spi0 = &spi1; - spi1 = &spi2; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_olinuxino>; - - green { - label = "a20-olinuxino-micro:green:usr"; - gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; -}; - -&ahci { - target-supply = <®_ahci_5v>; - status = "okay"; -}; - -&codec { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&de { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_mii_pins>, <&gmac_txerr>; - phy-handle = <&phy1>; - phy-mode = "mii"; - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&i2c1 { - status = "okay"; - - eeprom: eeprom@50 { - compatible = "atmel,24c16"; - reg = <0x50>; - pagesize = <16>; - }; -}; - -&i2c2 { - status = "okay"; -}; - -&lradc { - vref-supply = <®_vcc3v0>; - status = "okay"; - - button-191 { - label = "Volume Up"; - linux,code = ; - channel = <0>; - voltage = <191274>; - }; - - button-392 { - label = "Volume Down"; - linux,code = ; - channel = <0>; - voltage = <392644>; - }; - - button-601 { - label = "Menu"; - linux,code = ; - channel = <0>; - voltage = <601151>; - }; - - button-795 { - label = "Search"; - linux,code = ; - channel = <0>; - voltage = <795090>; - }; - - button-987 { - label = "Home"; - linux,code = ; - channel = <0>; - voltage = <987387>; - }; - - button-1184 { - label = "Esc"; - linux,code = ; - channel = <0>; - voltage = <1184678>; - }; - - button-1398 { - label = "Enter"; - linux,code = ; - channel = <0>; - voltage = <1398804>; - }; -}; - -&gmac_mdio { - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ - status = "okay"; -}; - -&mmc3 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 11 GPIO_ACTIVE_LOW>; /* PH11 */ - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pio { - gmac_txerr: gmac-txerr-pin { - pins = "PA17"; - function = "gmac"; - }; - - led_pins_olinuxino: led-pins { - pins = "PH2"; - function = "gpio_out"; - drive-strength = <20>; - }; -}; - -#include "axp209.dtsi" - -&ac_power_supply { - status = "okay"; -}; - -&battery_power_supply { - status = "okay"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-int-dll"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_ahci_5v { - status = "okay"; -}; - -®_usb0_vbus { - status = "okay"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&spi1 { - pinctrl-names = "default"; - pinctrl-0 = <&spi1_pi_pins>, - <&spi1_cs0_pi_pin>; - status = "okay"; -}; - -&spi2 { - pinctrl-names = "default"; - pinctrl-0 = <&spi2_pc_pins>, - <&spi2_cs0_pc_pin>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&uart6 { - pinctrl-names = "default"; - pinctrl-0 = <&uart6_pi_pins>; - status = "okay"; -}; - -&uart7 { - pinctrl-names = "default"; - pinctrl-0 = <&uart7_pi_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usb_power_supply { - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ - usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */ - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun7i-a20-orangepi-mini.dts b/sys/gnu/dts/arm/sun7i-a20-orangepi-mini.dts deleted file mode 100644 index 2e328d2cefc..00000000000 --- a/sys/gnu/dts/arm/sun7i-a20-orangepi-mini.dts +++ /dev/null @@ -1,242 +0,0 @@ -/* - * Copyright 2015 Hans de Goede - * - * Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun7i-a20.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include - -/ { - model = "Orange Pi Mini"; - compatible = "xunlong,orangepi-mini", "allwinner,sun7i-a20"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - green { - label = "orangepi:green:usr"; - gpios = <&pio 7 24 GPIO_ACTIVE_HIGH>; /* PH24 */ - }; - - blue { - label = "orangepi:blue:usr"; - gpios = <&pio 7 25 GPIO_ACTIVE_HIGH>; /* PH25 */ - }; - }; - - reg_gmac_3v3: gmac-3v3 { - compatible = "regulator-fixed"; - regulator-name = "gmac-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <100000>; - enable-active-high; - gpio = <&pio 7 23 GPIO_ACTIVE_HIGH>; /* PH23 */ - }; -}; - -&ahci { - status = "okay"; -}; - -&codec { - status = "okay"; -}; - -&de { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_rgmii_pins>; - phy-handle = <&phy1>; - phy-mode = "rgmii"; - phy-supply = <®_gmac_3v3>; - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -#include "axp209.dtsi" - -&ir0 { - pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pin>; - status = "okay"; -}; - -&gmac_mdio { - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 10 GPIO_ACTIVE_LOW>; /* PH10 */ - status = "okay"; -}; - -&mmc3 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 11 GPIO_ACTIVE_LOW>; /* PH11 */ - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-int-pll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_usb0_vbus { - status = "okay"; -}; - -®_usb1_vbus { - gpio = <&pio 7 26 GPIO_ACTIVE_HIGH>; /* PH26 */ - status = "okay"; -}; - -®_usb2_vbus { - gpio = <&pio 7 22 GPIO_ACTIVE_HIGH>; /* PH22 */ - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usb_power_supply { - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ - usb0_vbus_power-supply = <&usb_power_supply>; - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun7i-a20-orangepi.dts b/sys/gnu/dts/arm/sun7i-a20-orangepi.dts deleted file mode 100644 index d75b2e2bab2..00000000000 --- a/sys/gnu/dts/arm/sun7i-a20-orangepi.dts +++ /dev/null @@ -1,201 +0,0 @@ -/* - * Copyright 2015 Hans de Goede - * - * Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun7i-a20.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include - -/ { - model = "Orange Pi"; - compatible = "xunlong,orangepi", "allwinner,sun7i-a20"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - green { - label = "orangepi:green:usr"; - gpios = <&pio 7 24 GPIO_ACTIVE_HIGH>; /* PH24 */ - }; - }; - - reg_gmac_3v3: gmac-3v3 { - compatible = "regulator-fixed"; - regulator-name = "gmac-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <100000>; - enable-active-high; - gpio = <&pio 7 23 GPIO_ACTIVE_HIGH>; /* PH23 */ - }; -}; - -&ahci { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_rgmii_pins>; - phy-handle = <&phy1>; - phy-mode = "rgmii"; - phy-supply = <®_gmac_3v3>; - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -#include "axp209.dtsi" - -&ir0 { - pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pin>; - status = "okay"; -}; - -&gmac_mdio { - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 10 GPIO_ACTIVE_LOW>; /* PH10 */ - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-int-pll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_usb0_vbus { - status = "okay"; -}; - -®_usb1_vbus { - gpio = <&pio 7 26 GPIO_ACTIVE_HIGH>; /* PH26 */ - status = "okay"; -}; - -®_usb2_vbus { - gpio = <&pio 7 22 GPIO_ACTIVE_HIGH>; /* PH22 */ - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usb_power_supply { - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ - usb0_vbus_power-supply = <&usb_power_supply>; - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun7i-a20-pcduino3-nano.dts b/sys/gnu/dts/arm/sun7i-a20-pcduino3-nano.dts deleted file mode 100644 index fce2f7fcd08..00000000000 --- a/sys/gnu/dts/arm/sun7i-a20-pcduino3-nano.dts +++ /dev/null @@ -1,227 +0,0 @@ -/* - * Copyright 2015 Adam Sampson - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun7i-a20.dtsi" -#include "sunxi-common-regulators.dtsi" -#include -#include - -/ { - model = "LinkSprite pcDuino3 Nano"; - compatible = "linksprite,pcduino3-nano", "allwinner,sun7i-a20"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - /* Marked "LED3" on the PCB. */ - usr1 { - label = "pcduino3-nano:green:usr1"; - gpios = <&pio 7 16 GPIO_ACTIVE_LOW>; /* PH16 */ - }; - - /* Marked "LED4" on the PCB. */ - usr2 { - label = "pcduino3-nano:green:usr2"; - gpios = <&pio 7 15 GPIO_ACTIVE_LOW>; /* PH15 */ - }; - }; -}; - -&ahci { - target-supply = <®_ahci_5v>; - status = "okay"; -}; - -&codec { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&de { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_rgmii_pins>; - phy-handle = <&phy1>; - phy-mode = "rgmii"; - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&ir0 { - pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pin>; - status = "okay"; -}; - -&gmac_mdio { - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -®_ahci_5v { - gpio = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */ - status = "okay"; -}; - -#include "axp209.dtsi" - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-int-pll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -/* A single regulator (U24) powers both USB host ports. */ -®_usb1_vbus { - gpio = <&pio 3 2 GPIO_ACTIVE_HIGH>; /* PD2 */ - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb1_vbus>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun7i-a20-pcduino3.dts b/sys/gnu/dts/arm/sun7i-a20-pcduino3.dts deleted file mode 100644 index cc8271d777b..00000000000 --- a/sys/gnu/dts/arm/sun7i-a20-pcduino3.dts +++ /dev/null @@ -1,227 +0,0 @@ -/* - * Copyright 2014 Zoltan HERPAI - * Zoltan HERPAI - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun7i-a20.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include -#include - -/ { - model = "LinkSprite pcDuino3"; - compatible = "linksprite,pcduino3", "allwinner,sun7i-a20"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - tx { - label = "pcduino3:green:tx"; - gpios = <&pio 7 15 GPIO_ACTIVE_LOW>; - }; - - rx { - label = "pcduino3:green:rx"; - gpios = <&pio 7 16 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - back { - label = "Key Back"; - linux,code = ; - gpios = <&pio 7 17 GPIO_ACTIVE_LOW>; - }; - - home { - label = "Key Home"; - linux,code = ; - gpios = <&pio 7 18 GPIO_ACTIVE_LOW>; - }; - - menu { - label = "Key Menu"; - linux,code = ; - gpios = <&pio 7 19 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&ahci { - target-supply = <®_ahci_5v>; - status = "okay"; -}; - -&codec { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_mii_pins>; - phy-handle = <&phy1>; - phy-mode = "mii"; - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -#include "axp209.dtsi" - -&ir0 { - pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pin>; - status = "okay"; -}; - -&gmac_mdio { - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -®_ahci_5v { - gpio = <&pio 7 2 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-int-pll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun7i-a20-wexler-tab7200.dts b/sys/gnu/dts/arm/sun7i-a20-wexler-tab7200.dts deleted file mode 100644 index 6a66b0432df..00000000000 --- a/sys/gnu/dts/arm/sun7i-a20-wexler-tab7200.dts +++ /dev/null @@ -1,224 +0,0 @@ -/* - * Copyright 2015 Aleksei Mamlin - * Aleksei Mamlin - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun7i-a20.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include -#include -#include - -/ { - model = "Wexler TAB7200"; - compatible = "wexler,tab7200", "allwinner,sun7i-a20"; - - aliases { - serial0 = &uart0; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; - brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; - default-brightness-level = <8>; - enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */ - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&codec { - allwinner,pa-gpios = <&pio 7 15 GPIO_ACTIVE_HIGH>; /* PH15 */ - status = "okay"; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -#include "axp209.dtsi" - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; - - gt911: touchscreen@5d { - compatible = "goodix,gt911"; - reg = <0x5d>; - interrupt-parent = <&pio>; - interrupts = <7 21 IRQ_TYPE_EDGE_FALLING>; /* EINT21 (PH21) */ - irq-gpios = <&pio 7 21 GPIO_ACTIVE_HIGH>; /* INT (PH21) */ - reset-gpios = <&pio 1 13 GPIO_ACTIVE_HIGH>; /* RST (PB13) */ - touchscreen-swapped-x-y; - }; -}; - -&lradc { - vref-supply = <®_vcc3v0>; - status = "okay"; - - button-571 { - label = "Volume Up"; - linux,code = ; - channel = <0>; - voltage = <571428>; - }; - - button-761 { - label = "Volume Down"; - linux,code = ; - channel = <0>; - voltage = <761904>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pin>; - status = "okay"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1450000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-int-dll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_usb0_vbus { - status = "okay"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usb_power_supply { - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ - usb0_vbus_power-supply = <&usb_power_supply>; - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun7i-a20-wits-pro-a20-dkt.dts b/sys/gnu/dts/arm/sun7i-a20-wits-pro-a20-dkt.dts deleted file mode 100644 index 3bfae98f3cc..00000000000 --- a/sys/gnu/dts/arm/sun7i-a20-wits-pro-a20-dkt.dts +++ /dev/null @@ -1,209 +0,0 @@ -/* - * Copyright 2015 Jelle de Jong - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun7i-a20.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include -#include - -/ { - model = "Wits Pro A20 DKT"; - compatible = "wits,pro-a20-dkt", "allwinner,sun7i-a20"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - mmc3_pwrseq: mmc3_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&pio 7 9 GPIO_ACTIVE_LOW>; /* PH9 WIFI_EN */ - }; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_rgmii_pins>; - phy-handle = <&phy1>; - phy-mode = "rgmii"; - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -#include "axp209.dtsi" - -&gmac_mdio { - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ - status = "okay"; -}; - -&mmc3 { - vmmc-supply = <®_vcc3v3>; - mmc-pwrseq = <&mmc3_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - interrupt-parent = <&pio>; - interrupts = <7 10 IRQ_TYPE_LEVEL_LOW>; /* PH10 / EINT10 */ - interrupt-names = "host-wake"; - }; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1450000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-int-dll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_usb0_vbus { - status = "okay"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usb_power_supply { - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ - usb0_vbus_power-supply = <&usb_power_supply>; - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun7i-a20.dtsi b/sys/gnu/dts/arm/sun7i-a20.dtsi deleted file mode 100644 index 92b5be97085..00000000000 --- a/sys/gnu/dts/arm/sun7i-a20.dtsi +++ /dev/null @@ -1,1695 +0,0 @@ -/* - * Copyright 2013 Maxime Ripard - * - * Maxime Ripard - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include -#include -#include -#include -#include - -/ { - interrupt-parent = <&gic>; - #address-cells = <1>; - #size-cells = <1>; - - aliases { - ethernet0 = &gmac; - }; - - chosen { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - framebuffer-lcd0-hdmi { - compatible = "allwinner,simple-framebuffer", - "simple-framebuffer"; - allwinner,pipeline = "de_be0-lcd0-hdmi"; - clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>, - <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>, - <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_DE_BE0>, - <&ccu CLK_HDMI>; - status = "disabled"; - }; - - framebuffer-lcd0 { - compatible = "allwinner,simple-framebuffer", - "simple-framebuffer"; - allwinner,pipeline = "de_be0-lcd0"; - clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_DE_BE0>, - <&ccu CLK_DE_BE0>, <&ccu CLK_TCON0_CH0>, - <&ccu CLK_DRAM_DE_BE0>; - status = "disabled"; - }; - - framebuffer-lcd0-tve0 { - compatible = "allwinner,simple-framebuffer", - "simple-framebuffer"; - allwinner,pipeline = "de_be0-lcd0-tve0"; - clocks = <&ccu CLK_AHB_TVE0>, <&ccu CLK_AHB_LCD0>, - <&ccu CLK_AHB_DE_BE0>, - <&ccu CLK_DE_BE0>, <&ccu CLK_TCON0_CH1>, - <&ccu CLK_DRAM_TVE0>, <&ccu CLK_DRAM_DE_BE0>; - status = "disabled"; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <0>; - clocks = <&ccu CLK_CPU>; - clock-latency = <244144>; /* 8 32k periods */ - operating-points = < - /* kHz uV */ - 960000 1400000 - 912000 1400000 - 864000 1300000 - 720000 1200000 - 528000 1100000 - 312000 1000000 - 144000 1000000 - >; - #cooling-cells = <2>; - }; - - cpu1: cpu@1 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <1>; - clocks = <&ccu CLK_CPU>; - clock-latency = <244144>; /* 8 32k periods */ - operating-points = < - /* kHz uV */ - 960000 1400000 - 912000 1400000 - 864000 1300000 - 720000 1200000 - 528000 1100000 - 312000 1000000 - 144000 1000000 - >; - #cooling-cells = <2>; - }; - }; - - thermal-zones { - cpu_thermal { - /* milliseconds */ - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&rtp>; - - cooling-maps { - map0 { - trip = <&cpu_alert0>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - - trips { - cpu_alert0: cpu_alert0 { - /* milliCelsius */ - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu_crit: cpu_crit { - /* milliCelsius */ - temperature = <100000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - /* Address must be kept in the lower 256 MiBs of DRAM for VE. */ - default-pool { - compatible = "shared-dma-pool"; - size = <0x6000000>; - alloc-ranges = <0x4a000000 0x6000000>; - reusable; - linux,cma-default; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; - }; - - pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts = , - ; - }; - - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - osc24M: clk-24M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "osc24M"; - }; - - osc32k: clk-32k { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - clock-output-names = "osc32k"; - }; - - /* - * The following two are dummy clocks, placeholders - * used in the gmac_tx clock. The gmac driver will - * choose one parent depending on the PHY interface - * mode, using clk_set_rate auto-reparenting. - * - * The actual TX clock rate is not controlled by the - * gmac_tx clock. - */ - mii_phy_tx_clk: clk-mii-phy-tx { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <25000000>; - clock-output-names = "mii_phy_tx"; - }; - - gmac_int_tx_clk: clk-gmac-int-tx { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "gmac_int_tx"; - }; - - gmac_tx_clk: clk@1c20164 { - #clock-cells = <0>; - compatible = "allwinner,sun7i-a20-gmac-clk"; - reg = <0x01c20164 0x4>; - clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>; - clock-output-names = "gmac_tx"; - }; - }; - - - de: display-engine { - compatible = "allwinner,sun7i-a20-display-engine"; - allwinner,pipelines = <&fe0>, <&fe1>; - status = "disabled"; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - system-control@1c00000 { - compatible = "allwinner,sun7i-a20-system-control", - "allwinner,sun4i-a10-system-control"; - reg = <0x01c00000 0x30>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - sram_a: sram@0 { - compatible = "mmio-sram"; - reg = <0x00000000 0xc000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x00000000 0xc000>; - - emac_sram: sram-section@8000 { - compatible = "allwinner,sun7i-a20-sram-a3-a4", - "allwinner,sun4i-a10-sram-a3-a4"; - reg = <0x8000 0x4000>; - status = "disabled"; - }; - }; - - sram_d: sram@10000 { - compatible = "mmio-sram"; - reg = <0x00010000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x00010000 0x1000>; - - otg_sram: sram-section@0 { - compatible = "allwinner,sun7i-a20-sram-d", - "allwinner,sun4i-a10-sram-d"; - reg = <0x0000 0x1000>; - status = "disabled"; - }; - }; - - sram_c: sram@1d00000 { - compatible = "mmio-sram"; - reg = <0x01d00000 0xd0000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x01d00000 0xd0000>; - - ve_sram: sram-section@0 { - compatible = "allwinner,sun7i-a20-sram-c1", - "allwinner,sun4i-a10-sram-c1"; - reg = <0x000000 0x80000>; - }; - }; - }; - - nmi_intc: interrupt-controller@1c00030 { - compatible = "allwinner,sun7i-a20-sc-nmi"; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x01c00030 0x0c>; - interrupts = ; - }; - - dma: dma-controller@1c02000 { - compatible = "allwinner,sun4i-a10-dma"; - reg = <0x01c02000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_AHB_DMA>; - #dma-cells = <2>; - }; - - nfc: nand-controller@1c03000 { - compatible = "allwinner,sun4i-a10-nand"; - reg = <0x01c03000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>; - clock-names = "ahb", "mod"; - dmas = <&dma SUN4I_DMA_DEDICATED 3>; - dma-names = "rxtx"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - spi0: spi@1c05000 { - compatible = "allwinner,sun4i-a10-spi"; - reg = <0x01c05000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>; - clock-names = "ahb", "mod"; - dmas = <&dma SUN4I_DMA_DEDICATED 27>, - <&dma SUN4I_DMA_DEDICATED 26>; - dma-names = "rx", "tx"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - num-cs = <4>; - }; - - spi1: spi@1c06000 { - compatible = "allwinner,sun4i-a10-spi"; - reg = <0x01c06000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>; - clock-names = "ahb", "mod"; - dmas = <&dma SUN4I_DMA_DEDICATED 9>, - <&dma SUN4I_DMA_DEDICATED 8>; - dma-names = "rx", "tx"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - num-cs = <1>; - }; - - csi0: csi@1c09000 { - compatible = "allwinner,sun7i-a20-csi0"; - reg = <0x01c09000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_AHB_CSI0>, <&ccu CLK_CSI_SCLK>, <&ccu CLK_DRAM_CSI0>; - clock-names = "bus", "isp", "ram"; - resets = <&ccu RST_CSI0>; - status = "disabled"; - }; - - emac: ethernet@1c0b000 { - compatible = "allwinner,sun4i-a10-emac"; - reg = <0x01c0b000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_AHB_EMAC>; - allwinner,sram = <&emac_sram 1>; - status = "disabled"; - }; - - mdio: mdio@1c0b080 { - compatible = "allwinner,sun4i-a10-mdio"; - reg = <0x01c0b080 0x14>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - tcon0: lcd-controller@1c0c000 { - compatible = "allwinner,sun7i-a20-tcon"; - reg = <0x01c0c000 0x1000>; - interrupts = ; - resets = <&ccu RST_TCON0>; - reset-names = "lcd"; - clocks = <&ccu CLK_AHB_LCD0>, - <&ccu CLK_TCON0_CH0>, - <&ccu CLK_TCON0_CH1>; - clock-names = "ahb", - "tcon-ch0", - "tcon-ch1"; - clock-output-names = "tcon0-pixel-clock"; - #clock-cells = <0>; - dmas = <&dma SUN4I_DMA_DEDICATED 14>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - tcon0_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - tcon0_in_be0: endpoint@0 { - reg = <0>; - remote-endpoint = <&be0_out_tcon0>; - }; - - tcon0_in_be1: endpoint@1 { - reg = <1>; - remote-endpoint = <&be1_out_tcon0>; - }; - }; - - tcon0_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - tcon0_out_hdmi: endpoint@1 { - reg = <1>; - remote-endpoint = <&hdmi_in_tcon0>; - allwinner,tcon-channel = <1>; - }; - }; - }; - }; - - tcon1: lcd-controller@1c0d000 { - compatible = "allwinner,sun7i-a20-tcon"; - reg = <0x01c0d000 0x1000>; - interrupts = ; - resets = <&ccu RST_TCON1>; - reset-names = "lcd"; - clocks = <&ccu CLK_AHB_LCD1>, - <&ccu CLK_TCON1_CH0>, - <&ccu CLK_TCON1_CH1>; - clock-names = "ahb", - "tcon-ch0", - "tcon-ch1"; - clock-output-names = "tcon1-pixel-clock"; - #clock-cells = <0>; - dmas = <&dma SUN4I_DMA_DEDICATED 15>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - tcon1_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - tcon1_in_be0: endpoint@0 { - reg = <0>; - remote-endpoint = <&be0_out_tcon1>; - }; - - tcon1_in_be1: endpoint@1 { - reg = <1>; - remote-endpoint = <&be1_out_tcon1>; - }; - }; - - tcon1_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - tcon1_out_hdmi: endpoint@1 { - reg = <1>; - remote-endpoint = <&hdmi_in_tcon1>; - allwinner,tcon-channel = <1>; - }; - }; - }; - }; - - video-codec@1c0e000 { - compatible = "allwinner,sun7i-a20-video-engine"; - reg = <0x01c0e000 0x1000>; - clocks = <&ccu CLK_AHB_VE>, <&ccu CLK_VE>, - <&ccu CLK_DRAM_VE>; - clock-names = "ahb", "mod", "ram"; - resets = <&ccu RST_VE>; - interrupts = ; - allwinner,sram = <&ve_sram 1>; - }; - - mmc0: mmc@1c0f000 { - compatible = "allwinner,sun7i-a20-mmc"; - reg = <0x01c0f000 0x1000>; - clocks = <&ccu CLK_AHB_MMC0>, - <&ccu CLK_MMC0>, - <&ccu CLK_MMC0_OUTPUT>, - <&ccu CLK_MMC0_SAMPLE>; - clock-names = "ahb", - "mmc", - "output", - "sample"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc1: mmc@1c10000 { - compatible = "allwinner,sun7i-a20-mmc"; - reg = <0x01c10000 0x1000>; - clocks = <&ccu CLK_AHB_MMC1>, - <&ccu CLK_MMC1>, - <&ccu CLK_MMC1_OUTPUT>, - <&ccu CLK_MMC1_SAMPLE>; - clock-names = "ahb", - "mmc", - "output", - "sample"; - interrupts = ; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc2: mmc@1c11000 { - compatible = "allwinner,sun7i-a20-mmc"; - reg = <0x01c11000 0x1000>; - clocks = <&ccu CLK_AHB_MMC2>, - <&ccu CLK_MMC2>, - <&ccu CLK_MMC2_OUTPUT>, - <&ccu CLK_MMC2_SAMPLE>; - clock-names = "ahb", - "mmc", - "output", - "sample"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc3: mmc@1c12000 { - compatible = "allwinner,sun7i-a20-mmc"; - reg = <0x01c12000 0x1000>; - clocks = <&ccu CLK_AHB_MMC3>, - <&ccu CLK_MMC3>, - <&ccu CLK_MMC3_OUTPUT>, - <&ccu CLK_MMC3_SAMPLE>; - clock-names = "ahb", - "mmc", - "output", - "sample"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&mmc3_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - usb_otg: usb@1c13000 { - compatible = "allwinner,sun4i-a10-musb"; - reg = <0x01c13000 0x0400>; - clocks = <&ccu CLK_AHB_OTG>; - interrupts = ; - interrupt-names = "mc"; - phys = <&usbphy 0>; - phy-names = "usb"; - extcon = <&usbphy 0>; - allwinner,sram = <&otg_sram 1>; - dr_mode = "otg"; - status = "disabled"; - }; - - usbphy: phy@1c13400 { - #phy-cells = <1>; - compatible = "allwinner,sun7i-a20-usb-phy"; - reg = <0x01c13400 0x10>, <0x01c14800 0x4>, <0x01c1c800 0x4>; - reg-names = "phy_ctrl", "pmu1", "pmu2"; - clocks = <&ccu CLK_USB_PHY>; - clock-names = "usb_phy"; - resets = <&ccu RST_USB_PHY0>, - <&ccu RST_USB_PHY1>, - <&ccu RST_USB_PHY2>; - reset-names = "usb0_reset", "usb1_reset", "usb2_reset"; - status = "disabled"; - }; - - ehci0: usb@1c14000 { - compatible = "allwinner,sun7i-a20-ehci", "generic-ehci"; - reg = <0x01c14000 0x100>; - interrupts = ; - clocks = <&ccu CLK_AHB_EHCI0>; - phys = <&usbphy 1>; - phy-names = "usb"; - status = "disabled"; - }; - - ohci0: usb@1c14400 { - compatible = "allwinner,sun7i-a20-ohci", "generic-ohci"; - reg = <0x01c14400 0x100>; - interrupts = ; - clocks = <&ccu CLK_USB_OHCI0>, <&ccu CLK_AHB_OHCI0>; - phys = <&usbphy 1>; - phy-names = "usb"; - status = "disabled"; - }; - - crypto: crypto-engine@1c15000 { - compatible = "allwinner,sun7i-a20-crypto", - "allwinner,sun4i-a10-crypto"; - reg = <0x01c15000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_AHB_SS>, <&ccu CLK_SS>; - clock-names = "ahb", "mod"; - }; - - hdmi: hdmi@1c16000 { - compatible = "allwinner,sun7i-a20-hdmi", - "allwinner,sun5i-a10s-hdmi"; - reg = <0x01c16000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_AHB_HDMI0>, <&ccu CLK_HDMI>, - <&ccu CLK_PLL_VIDEO0_2X>, - <&ccu CLK_PLL_VIDEO1_2X>; - clock-names = "ahb", "mod", "pll-0", "pll-1"; - dmas = <&dma SUN4I_DMA_NORMAL 16>, - <&dma SUN4I_DMA_NORMAL 16>, - <&dma SUN4I_DMA_DEDICATED 24>; - dma-names = "ddc-tx", "ddc-rx", "audio-tx"; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - hdmi_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - hdmi_in_tcon0: endpoint@0 { - reg = <0>; - remote-endpoint = <&tcon0_out_hdmi>; - }; - - hdmi_in_tcon1: endpoint@1 { - reg = <1>; - remote-endpoint = <&tcon1_out_hdmi>; - }; - }; - - hdmi_out: port@1 { - reg = <1>; - }; - }; - }; - - spi2: spi@1c17000 { - compatible = "allwinner,sun4i-a10-spi"; - reg = <0x01c17000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>; - clock-names = "ahb", "mod"; - dmas = <&dma SUN4I_DMA_DEDICATED 29>, - <&dma SUN4I_DMA_DEDICATED 28>; - dma-names = "rx", "tx"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - num-cs = <1>; - }; - - ahci: sata@1c18000 { - compatible = "allwinner,sun4i-a10-ahci"; - reg = <0x01c18000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_AHB_SATA>, <&ccu CLK_SATA>; - status = "disabled"; - }; - - ehci1: usb@1c1c000 { - compatible = "allwinner,sun7i-a20-ehci", "generic-ehci"; - reg = <0x01c1c000 0x100>; - interrupts = ; - clocks = <&ccu CLK_AHB_EHCI1>; - phys = <&usbphy 2>; - phy-names = "usb"; - status = "disabled"; - }; - - ohci1: usb@1c1c400 { - compatible = "allwinner,sun7i-a20-ohci", "generic-ohci"; - reg = <0x01c1c400 0x100>; - interrupts = ; - clocks = <&ccu CLK_USB_OHCI1>, <&ccu CLK_AHB_OHCI1>; - phys = <&usbphy 2>; - phy-names = "usb"; - status = "disabled"; - }; - - csi1: csi@1c1d000 { - compatible = "allwinner,sun7i-a20-csi1", - "allwinner,sun4i-a10-csi1"; - reg = <0x01c1d000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_AHB_CSI1>, <&ccu CLK_DRAM_CSI1>; - clock-names = "bus", "ram"; - resets = <&ccu RST_CSI1>; - status = "disabled"; - }; - - spi3: spi@1c1f000 { - compatible = "allwinner,sun4i-a10-spi"; - reg = <0x01c1f000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_AHB_SPI3>, <&ccu CLK_SPI3>; - clock-names = "ahb", "mod"; - dmas = <&dma SUN4I_DMA_DEDICATED 31>, - <&dma SUN4I_DMA_DEDICATED 30>; - dma-names = "rx", "tx"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - num-cs = <1>; - }; - - ccu: clock@1c20000 { - compatible = "allwinner,sun7i-a20-ccu"; - reg = <0x01c20000 0x400>; - clocks = <&osc24M>, <&osc32k>; - clock-names = "hosc", "losc"; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - pio: pinctrl@1c20800 { - compatible = "allwinner,sun7i-a20-pinctrl"; - reg = <0x01c20800 0x400>; - interrupts = ; - clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>; - clock-names = "apb", "hosc", "losc"; - gpio-controller; - interrupt-controller; - #interrupt-cells = <3>; - #gpio-cells = <3>; - - /omit-if-no-ref/ - can_pa_pins: can-pa-pins { - pins = "PA16", "PA17"; - function = "can"; - }; - - /omit-if-no-ref/ - can_ph_pins: can-ph-pins { - pins = "PH20", "PH21"; - function = "can"; - }; - - /omit-if-no-ref/ - clk_out_a_pin: clk-out-a-pin { - pins = "PI12"; - function = "clk_out_a"; - }; - - /omit-if-no-ref/ - clk_out_b_pin: clk-out-b-pin { - pins = "PI13"; - function = "clk_out_b"; - }; - - /omit-if-no-ref/ - csi0_8bits_pins: csi-8bits-pins { - pins = "PE0", "PE2", "PE3", "PE4", "PE5", - "PE6", "PE7", "PE8", "PE9", "PE10", - "PE11"; - function = "csi0"; - }; - - /omit-if-no-ref/ - csi0_clk_pin: csi-clk-pin { - pins = "PE1"; - function = "csi0"; - }; - - /omit-if-no-ref/ - csi1_8bits_pg_pins: csi1-8bits-pg-pins { - pins = "PG0", "PG2", "PG3", "PG4", "PG5", - "PG6", "PG7", "PG8", "PG9", "PG10", - "PG11"; - function = "csi1"; - }; - - /omit-if-no-ref/ - csi1_24bits_ph_pins: csi1-24bits-ph-pins { - pins = "PH0", "PH1", "PH2", "PH3", "PH4", - "PH5", "PH6", "PH7", "PH8", "PH9", - "PH10", "PH11", "PH12", "PH13", "PH14", - "PH15", "PH16", "PH17", "PH18", "PH19", - "PH20", "PH21", "PH22", "PH23", "PH24", - "PH25", "PH26", "PH27"; - function = "csi1"; - }; - - /omit-if-no-ref/ - csi1_clk_pg_pin: csi1-clk-pg-pin { - pins = "PG1"; - function = "csi1"; - }; - - /omit-if-no-ref/ - emac_pa_pins: emac-pa-pins { - pins = "PA0", "PA1", "PA2", - "PA3", "PA4", "PA5", "PA6", - "PA7", "PA8", "PA9", "PA10", - "PA11", "PA12", "PA13", "PA14", - "PA15", "PA16"; - function = "emac"; - }; - - /omit-if-no-ref/ - emac_ph_pins: emac-ph-pins { - pins = "PH8", "PH9", "PH10", "PH11", - "PH14", "PH15", "PH16", "PH17", - "PH18", "PH19", "PH20", "PH21", - "PH22", "PH23", "PH24", "PH25", - "PH26"; - function = "emac"; - }; - - /omit-if-no-ref/ - gmac_mii_pins: gmac-mii-pins { - pins = "PA0", "PA1", "PA2", - "PA3", "PA4", "PA5", "PA6", - "PA7", "PA8", "PA9", "PA10", - "PA11", "PA12", "PA13", "PA14", - "PA15", "PA16"; - function = "gmac"; - }; - - /omit-if-no-ref/ - gmac_rgmii_pins: gmac-rgmii-pins { - pins = "PA0", "PA1", "PA2", - "PA3", "PA4", "PA5", "PA6", - "PA7", "PA8", "PA10", - "PA11", "PA12", "PA13", - "PA15", "PA16"; - function = "gmac"; - /* - * data lines in RGMII mode use DDR mode - * and need a higher signal drive strength - */ - drive-strength = <40>; - }; - - /omit-if-no-ref/ - i2c0_pins: i2c0-pins { - pins = "PB0", "PB1"; - function = "i2c0"; - }; - - /omit-if-no-ref/ - i2c1_pins: i2c1-pins { - pins = "PB18", "PB19"; - function = "i2c1"; - }; - - /omit-if-no-ref/ - i2c2_pins: i2c2-pins { - pins = "PB20", "PB21"; - function = "i2c2"; - }; - - /omit-if-no-ref/ - i2c3_pins: i2c3-pins { - pins = "PI0", "PI1"; - function = "i2c3"; - }; - - /omit-if-no-ref/ - ir0_rx_pin: ir0-rx-pin { - pins = "PB4"; - function = "ir0"; - }; - - /omit-if-no-ref/ - ir0_tx_pin: ir0-tx-pin { - pins = "PB3"; - function = "ir0"; - }; - - /omit-if-no-ref/ - ir1_rx_pin: ir1-rx-pin { - pins = "PB23"; - function = "ir1"; - }; - - /omit-if-no-ref/ - ir1_tx_pin: ir1-tx-pin { - pins = "PB22"; - function = "ir1"; - }; - - /omit-if-no-ref/ - mmc0_pins: mmc0-pins { - pins = "PF0", "PF1", "PF2", - "PF3", "PF4", "PF5"; - function = "mmc0"; - drive-strength = <30>; - bias-pull-up; - }; - - /omit-if-no-ref/ - mmc2_pins: mmc2-pins { - pins = "PC6", "PC7", "PC8", - "PC9", "PC10", "PC11"; - function = "mmc2"; - drive-strength = <30>; - bias-pull-up; - }; - - /omit-if-no-ref/ - mmc3_pins: mmc3-pins { - pins = "PI4", "PI5", "PI6", - "PI7", "PI8", "PI9"; - function = "mmc3"; - drive-strength = <30>; - bias-pull-up; - }; - - /omit-if-no-ref/ - ps2_0_pins: ps2-0-pins { - pins = "PI20", "PI21"; - function = "ps2"; - }; - - /omit-if-no-ref/ - ps2_1_ph_pins: ps2-1-ph-pins { - pins = "PH12", "PH13"; - function = "ps2"; - }; - - /omit-if-no-ref/ - pwm0_pin: pwm0-pin { - pins = "PB2"; - function = "pwm"; - }; - - /omit-if-no-ref/ - pwm1_pin: pwm1-pin { - pins = "PI3"; - function = "pwm"; - }; - - /omit-if-no-ref/ - spdif_tx_pin: spdif-tx-pin { - pins = "PB13"; - function = "spdif"; - bias-pull-up; - }; - - /omit-if-no-ref/ - spi0_pi_pins: spi0-pi-pins { - pins = "PI11", "PI12", "PI13"; - function = "spi0"; - }; - - /omit-if-no-ref/ - spi0_cs0_pi_pin: spi0-cs0-pi-pin { - pins = "PI10"; - function = "spi0"; - }; - - /omit-if-no-ref/ - spi0_cs1_pi_pin: spi0-cs1-pi-pin { - pins = "PI14"; - function = "spi0"; - }; - - /omit-if-no-ref/ - spi1_pi_pins: spi1-pi-pins { - pins = "PI17", "PI18", "PI19"; - function = "spi1"; - }; - - /omit-if-no-ref/ - spi1_cs0_pi_pin: spi1-cs0-pi-pin { - pins = "PI16"; - function = "spi1"; - }; - - /omit-if-no-ref/ - spi2_pb_pins: spi2-pb-pins { - pins = "PB15", "PB16", "PB17"; - function = "spi2"; - }; - - /omit-if-no-ref/ - spi2_cs0_pb_pin: spi2-cs0-pb-pin { - pins = "PB14"; - function = "spi2"; - }; - - /omit-if-no-ref/ - spi2_pc_pins: spi2-pc-pins { - pins = "PC20", "PC21", "PC22"; - function = "spi2"; - }; - - /omit-if-no-ref/ - spi2_cs0_pc_pin: spi2-cs0-pc-pin { - pins = "PC19"; - function = "spi2"; - }; - - /omit-if-no-ref/ - uart0_pb_pins: uart0-pb-pins { - pins = "PB22", "PB23"; - function = "uart0"; - }; - - /omit-if-no-ref/ - uart0_pf_pins: uart0-pf-pins { - pins = "PF2", "PF4"; - function = "uart0"; - }; - - /omit-if-no-ref/ - uart1_pa_pins: uart1-pa-pins { - pins = "PA10", "PA11"; - function = "uart1"; - }; - - /omit-if-no-ref/ - uart1_cts_rts_pa_pins: uart1-cts-rts-pa-pins { - pins = "PA12", "PA13"; - function = "uart1"; - }; - - /omit-if-no-ref/ - uart2_pa_pins: uart2-pa-pins { - pins = "PA2", "PA3"; - function = "uart2"; - }; - - /omit-if-no-ref/ - uart2_cts_rts_pa_pins: uart2-cts-rts-pa-pins { - pins = "PA0", "PA1"; - function = "uart2"; - }; - - /omit-if-no-ref/ - uart2_pi_pins: uart2-pi-pins { - pins = "PI18", "PI19"; - function = "uart2"; - }; - - /omit-if-no-ref/ - uart2_cts_rts_pi_pins: uart2-cts-rts-pi-pins { - pins = "PI16", "PI17"; - function = "uart2"; - }; - - /omit-if-no-ref/ - uart3_pg_pins: uart3-pg-pins { - pins = "PG6", "PG7"; - function = "uart3"; - }; - - /omit-if-no-ref/ - uart3_cts_rts_pg_pins: uart3-cts-rts-pg-pins { - pins = "PG8", "PG9"; - function = "uart3"; - }; - - /omit-if-no-ref/ - uart3_ph_pins: uart3-ph-pins { - pins = "PH0", "PH1"; - function = "uart3"; - }; - - /omit-if-no-ref/ - uart3_cts_rts_ph_pins: uart3-cts-rts-ph-pins { - pins = "PH2", "PH3"; - function = "uart3"; - }; - - /omit-if-no-ref/ - uart4_pg_pins: uart4-pg-pins { - pins = "PG10", "PG11"; - function = "uart4"; - }; - - /omit-if-no-ref/ - uart4_ph_pins: uart4-ph-pins { - pins = "PH4", "PH5"; - function = "uart4"; - }; - - /omit-if-no-ref/ - uart5_ph_pins: uart5-ph-pins { - pins = "PH6", "PH7"; - function = "uart5"; - }; - - /omit-if-no-ref/ - uart5_pi_pins: uart5-pi-pins { - pins = "PI10", "PI11"; - function = "uart5"; - }; - - /omit-if-no-ref/ - uart6_pa_pins: uart6-pa-pins { - pins = "PA12", "PA13"; - function = "uart6"; - }; - - /omit-if-no-ref/ - uart6_pi_pins: uart6-pi-pins { - pins = "PI12", "PI13"; - function = "uart6"; - }; - - /omit-if-no-ref/ - uart7_pa_pins: uart7-pa-pins { - pins = "PA14", "PA15"; - function = "uart7"; - }; - - /omit-if-no-ref/ - uart7_pi_pins: uart7-pi-pins { - pins = "PI20", "PI21"; - function = "uart7"; - }; - }; - - timer@1c20c00 { - compatible = "allwinner,sun4i-a10-timer"; - reg = <0x01c20c00 0x90>; - interrupts = , - , - , - , - , - ; - clocks = <&osc24M>; - }; - - wdt: watchdog@1c20c90 { - compatible = "allwinner,sun4i-a10-wdt"; - reg = <0x01c20c90 0x10>; - interrupts = ; - clocks = <&osc24M>; - }; - - rtc: rtc@1c20d00 { - compatible = "allwinner,sun7i-a20-rtc"; - reg = <0x01c20d00 0x20>; - interrupts = ; - }; - - pwm: pwm@1c20e00 { - compatible = "allwinner,sun7i-a20-pwm"; - reg = <0x01c20e00 0xc>; - clocks = <&osc24M>; - #pwm-cells = <3>; - status = "disabled"; - }; - - spdif: spdif@1c21000 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun4i-a10-spdif"; - reg = <0x01c21000 0x400>; - interrupts = ; - clocks = <&ccu CLK_APB0_SPDIF>, <&ccu CLK_SPDIF>; - clock-names = "apb", "spdif"; - dmas = <&dma SUN4I_DMA_NORMAL 2>, - <&dma SUN4I_DMA_NORMAL 2>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - ir0: ir@1c21800 { - compatible = "allwinner,sun4i-a10-ir"; - clocks = <&ccu CLK_APB0_IR0>, <&ccu CLK_IR0>; - clock-names = "apb", "ir"; - interrupts = ; - reg = <0x01c21800 0x40>; - status = "disabled"; - }; - - ir1: ir@1c21c00 { - compatible = "allwinner,sun4i-a10-ir"; - clocks = <&ccu CLK_APB0_IR1>, <&ccu CLK_IR1>; - clock-names = "apb", "ir"; - interrupts = ; - reg = <0x01c21c00 0x40>; - status = "disabled"; - }; - - i2s1: i2s@1c22000 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun4i-a10-i2s"; - reg = <0x01c22000 0x400>; - interrupts = ; - clocks = <&ccu CLK_APB0_I2S1>, <&ccu CLK_I2S1>; - clock-names = "apb", "mod"; - dmas = <&dma SUN4I_DMA_NORMAL 4>, - <&dma SUN4I_DMA_NORMAL 4>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2s0: i2s@1c22400 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun4i-a10-i2s"; - reg = <0x01c22400 0x400>; - interrupts = ; - clocks = <&ccu CLK_APB0_I2S0>, <&ccu CLK_I2S0>; - clock-names = "apb", "mod"; - dmas = <&dma SUN4I_DMA_NORMAL 3>, - <&dma SUN4I_DMA_NORMAL 3>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - lradc: lradc@1c22800 { - compatible = "allwinner,sun4i-a10-lradc-keys"; - reg = <0x01c22800 0x100>; - interrupts = ; - status = "disabled"; - }; - - codec: codec@1c22c00 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun7i-a20-codec"; - reg = <0x01c22c00 0x40>; - interrupts = ; - clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>; - clock-names = "apb", "codec"; - dmas = <&dma SUN4I_DMA_NORMAL 19>, - <&dma SUN4I_DMA_NORMAL 19>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - sid: eeprom@1c23800 { - compatible = "allwinner,sun7i-a20-sid"; - reg = <0x01c23800 0x200>; - }; - - i2s2: i2s@1c24400 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun4i-a10-i2s"; - reg = <0x01c24400 0x400>; - interrupts = ; - clocks = <&ccu CLK_APB0_I2S2>, <&ccu CLK_I2S2>; - clock-names = "apb", "mod"; - dmas = <&dma SUN4I_DMA_NORMAL 6>, - <&dma SUN4I_DMA_NORMAL 6>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - rtp: rtp@1c25000 { - compatible = "allwinner,sun5i-a13-ts"; - reg = <0x01c25000 0x100>; - interrupts = ; - #thermal-sensor-cells = <0>; - }; - - uart0: serial@1c28000 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_APB1_UART0>; - status = "disabled"; - }; - - uart1: serial@1c28400 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28400 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_APB1_UART1>; - status = "disabled"; - }; - - uart2: serial@1c28800 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28800 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_APB1_UART2>; - status = "disabled"; - }; - - uart3: serial@1c28c00 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28c00 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_APB1_UART3>; - status = "disabled"; - }; - - uart4: serial@1c29000 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c29000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_APB1_UART4>; - status = "disabled"; - }; - - uart5: serial@1c29400 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c29400 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_APB1_UART5>; - status = "disabled"; - }; - - uart6: serial@1c29800 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c29800 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_APB1_UART6>; - status = "disabled"; - }; - - uart7: serial@1c29c00 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c29c00 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_APB1_UART7>; - status = "disabled"; - }; - - ps20: ps2@1c2a000 { - compatible = "allwinner,sun4i-a10-ps2"; - reg = <0x01c2a000 0x400>; - interrupts = ; - clocks = <&ccu CLK_APB1_PS20>; - status = "disabled"; - }; - - ps21: ps2@1c2a400 { - compatible = "allwinner,sun4i-a10-ps2"; - reg = <0x01c2a400 0x400>; - interrupts = ; - clocks = <&ccu CLK_APB1_PS21>; - status = "disabled"; - }; - - i2c0: i2c@1c2ac00 { - compatible = "allwinner,sun7i-a20-i2c", - "allwinner,sun4i-a10-i2c"; - reg = <0x01c2ac00 0x400>; - interrupts = ; - clocks = <&ccu CLK_APB1_I2C0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c1: i2c@1c2b000 { - compatible = "allwinner,sun7i-a20-i2c", - "allwinner,sun4i-a10-i2c"; - reg = <0x01c2b000 0x400>; - interrupts = ; - clocks = <&ccu CLK_APB1_I2C1>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c2: i2c@1c2b400 { - compatible = "allwinner,sun7i-a20-i2c", - "allwinner,sun4i-a10-i2c"; - reg = <0x01c2b400 0x400>; - interrupts = ; - clocks = <&ccu CLK_APB1_I2C2>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c3: i2c@1c2b800 { - compatible = "allwinner,sun7i-a20-i2c", - "allwinner,sun4i-a10-i2c"; - reg = <0x01c2b800 0x400>; - interrupts = ; - clocks = <&ccu CLK_APB1_I2C3>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - can0: can@1c2bc00 { - compatible = "allwinner,sun7i-a20-can", - "allwinner,sun4i-a10-can"; - reg = <0x01c2bc00 0x400>; - interrupts = ; - clocks = <&ccu CLK_APB1_CAN>; - status = "disabled"; - }; - - i2c4: i2c@1c2c000 { - compatible = "allwinner,sun7i-a20-i2c", - "allwinner,sun4i-a10-i2c"; - reg = <0x01c2c000 0x400>; - interrupts = ; - clocks = <&ccu CLK_APB1_I2C4>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mali: gpu@1c40000 { - compatible = "allwinner,sun7i-a20-mali", "arm,mali-400"; - reg = <0x01c40000 0x10000>; - interrupts = , - , - , - , - , - , - ; - interrupt-names = "gp", - "gpmmu", - "pp0", - "ppmmu0", - "pp1", - "ppmmu1", - "pmu"; - clocks = <&ccu CLK_AHB_GPU>, <&ccu CLK_GPU>; - clock-names = "bus", "core"; - resets = <&ccu RST_GPU>; - - assigned-clocks = <&ccu CLK_GPU>; - assigned-clock-rates = <384000000>; - }; - - gmac: ethernet@1c50000 { - compatible = "allwinner,sun7i-a20-gmac"; - reg = <0x01c50000 0x10000>; - interrupts = ; - interrupt-names = "macirq"; - clocks = <&ccu CLK_AHB_GMAC>, <&gmac_tx_clk>; - clock-names = "stmmaceth", "allwinner_gmac_tx"; - snps,pbl = <2>; - snps,fixed-burst; - snps,force_sf_dma_mode; - status = "disabled"; - - gmac_mdio: mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - hstimer@1c60000 { - compatible = "allwinner,sun7i-a20-hstimer"; - reg = <0x01c60000 0x1000>; - interrupts = , - , - , - ; - clocks = <&ccu CLK_AHB_HSTIMER>; - }; - - gic: interrupt-controller@1c81000 { - compatible = "arm,gic-400"; - reg = <0x01c81000 0x1000>, - <0x01c82000 0x2000>, - <0x01c84000 0x2000>, - <0x01c86000 0x2000>; - interrupt-controller; - #interrupt-cells = <3>; - interrupts = ; - }; - - fe0: display-frontend@1e00000 { - compatible = "allwinner,sun7i-a20-display-frontend"; - reg = <0x01e00000 0x20000>; - interrupts = ; - clocks = <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_FE0>, - <&ccu CLK_DRAM_DE_FE0>; - clock-names = "ahb", "mod", - "ram"; - resets = <&ccu RST_DE_FE0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - fe0_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - fe0_out_be0: endpoint@0 { - reg = <0>; - remote-endpoint = <&be0_in_fe0>; - }; - - fe0_out_be1: endpoint@1 { - reg = <1>; - remote-endpoint = <&be1_in_fe0>; - }; - }; - }; - }; - - fe1: display-frontend@1e20000 { - compatible = "allwinner,sun7i-a20-display-frontend"; - reg = <0x01e20000 0x20000>; - interrupts = ; - clocks = <&ccu CLK_AHB_DE_FE1>, <&ccu CLK_DE_FE1>, - <&ccu CLK_DRAM_DE_FE1>; - clock-names = "ahb", "mod", - "ram"; - resets = <&ccu RST_DE_FE1>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - fe1_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - fe1_out_be0: endpoint@0 { - reg = <0>; - remote-endpoint = <&be0_in_fe1>; - }; - - fe1_out_be1: endpoint@1 { - reg = <1>; - remote-endpoint = <&be1_in_fe1>; - }; - }; - }; - }; - - be1: display-backend@1e40000 { - compatible = "allwinner,sun7i-a20-display-backend"; - reg = <0x01e40000 0x10000>; - interrupts = ; - clocks = <&ccu CLK_AHB_DE_BE1>, <&ccu CLK_DE_BE1>, - <&ccu CLK_DRAM_DE_BE1>; - clock-names = "ahb", "mod", - "ram"; - resets = <&ccu RST_DE_BE1>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - be1_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - be1_in_fe0: endpoint@0 { - reg = <0>; - remote-endpoint = <&fe0_out_be1>; - }; - - be1_in_fe1: endpoint@1 { - reg = <1>; - remote-endpoint = <&fe1_out_be1>; - }; - }; - - be1_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - be1_out_tcon0: endpoint@0 { - reg = <0>; - remote-endpoint = <&tcon0_in_be1>; - }; - - be1_out_tcon1: endpoint@1 { - reg = <1>; - remote-endpoint = <&tcon1_in_be1>; - }; - }; - }; - }; - - be0: display-backend@1e60000 { - compatible = "allwinner,sun7i-a20-display-backend"; - reg = <0x01e60000 0x10000>; - interrupts = ; - clocks = <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>, - <&ccu CLK_DRAM_DE_BE0>; - clock-names = "ahb", "mod", - "ram"; - resets = <&ccu RST_DE_BE0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - be0_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - be0_in_fe0: endpoint@0 { - reg = <0>; - remote-endpoint = <&fe0_out_be0>; - }; - - be0_in_fe1: endpoint@1 { - reg = <1>; - remote-endpoint = <&fe1_out_be0>; - }; - }; - - be0_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - be0_out_tcon0: endpoint@0 { - reg = <0>; - remote-endpoint = <&tcon0_in_be0>; - }; - - be0_out_tcon1: endpoint@1 { - reg = <1>; - remote-endpoint = <&tcon1_in_be0>; - }; - }; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/sun8i-a23-a33.dtsi b/sys/gnu/dts/arm/sun8i-a23-a33.dtsi deleted file mode 100644 index 48487f6d4ab..00000000000 --- a/sys/gnu/dts/arm/sun8i-a23-a33.dtsi +++ /dev/null @@ -1,853 +0,0 @@ -/* - * Copyright 2014 Chen-Yu Tsai - * - * Chen-Yu Tsai - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include - -#include -#include - -/ { - interrupt-parent = <&gic>; - #address-cells = <1>; - #size-cells = <1>; - - chosen { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - simplefb_lcd: framebuffer-lcd0 { - compatible = "allwinner,simple-framebuffer", - "simple-framebuffer"; - allwinner,pipeline = "de_be0-lcd0"; - clocks = <&ccu CLK_BUS_LCD>, <&ccu CLK_BUS_DE_BE>, - <&ccu CLK_LCD_CH0>, <&ccu CLK_DE_BE>, - <&ccu CLK_DRAM_DE_BE>, <&ccu CLK_DRC>; - status = "disabled"; - }; - }; - - de: display-engine { - /* compatible gets set in SoC specific dtsi file */ - allwinner,pipelines = <&fe0>; - status = "disabled"; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; - clock-frequency = <24000000>; - arm,cpu-registers-not-fw-configured; - }; - - cpus { - enable-method = "allwinner,sun8i-a23"; - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <0>; - }; - - cpu@1 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <1>; - }; - }; - - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - osc24M: osc24M_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-accuracy = <50000>; - clock-output-names = "osc24M"; - }; - - ext_osc32k: ext_osc32k_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - clock-accuracy = <50000>; - clock-output-names = "ext-osc32k"; - }; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - system-control@1c00000 { - compatible = "allwinner,sun8i-a23-system-control"; - reg = <0x01c00000 0x30>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - sram_c: sram@1d00000 { - compatible = "mmio-sram"; - reg = <0x01d00000 0x80000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x01d00000 0x80000>; - - ve_sram: sram-section@0 { - compatible = "allwinner,sun8i-a23-sram-c1", - "allwinner,sun4i-a10-sram-c1"; - reg = <0x000000 0x80000>; - }; - }; - }; - - dma: dma-controller@1c02000 { - compatible = "allwinner,sun8i-a23-dma"; - reg = <0x01c02000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_BUS_DMA>; - resets = <&ccu RST_BUS_DMA>; - #dma-cells = <1>; - }; - - nfc: nand-controller@1c03000 { - compatible = "allwinner,sun8i-a23-nand-controller"; - reg = <0x01c03000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_BUS_NAND>, <&ccu CLK_NAND>; - clock-names = "ahb", "mod"; - resets = <&ccu RST_BUS_NAND>; - reset-names = "ahb"; - dmas = <&dma 5>; - dma-names = "rxtx"; - pinctrl-names = "default"; - pinctrl-0 = <&nand_pins &nand_cs0_pin &nand_rb0_pin>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - tcon0: lcd-controller@1c0c000 { - /* compatible gets set in SoC specific dtsi file */ - reg = <0x01c0c000 0x1000>; - interrupts = ; - dmas = <&dma 12>; - clocks = <&ccu CLK_BUS_LCD>, - <&ccu CLK_LCD_CH0>, - <&ccu 13>; - clock-names = "ahb", - "tcon-ch0", - "lvds-alt"; - clock-output-names = "tcon-pixel-clock"; - #clock-cells = <0>; - resets = <&ccu RST_BUS_LCD>, - <&ccu RST_BUS_LVDS>; - reset-names = "lcd", - "lvds"; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - tcon0_in: port@0 { - reg = <0>; - - tcon0_in_drc0: endpoint { - remote-endpoint = <&drc0_out_tcon0>; - }; - }; - - tcon0_out: port@1 { - reg = <1>; - }; - }; - }; - - mmc0: mmc@1c0f000 { - compatible = "allwinner,sun7i-a20-mmc"; - reg = <0x01c0f000 0x1000>; - clocks = <&ccu CLK_BUS_MMC0>, - <&ccu CLK_MMC0>, - <&ccu CLK_MMC0_OUTPUT>, - <&ccu CLK_MMC0_SAMPLE>; - clock-names = "ahb", - "mmc", - "output", - "sample"; - resets = <&ccu RST_BUS_MMC0>; - reset-names = "ahb"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc1: mmc@1c10000 { - compatible = "allwinner,sun7i-a20-mmc"; - reg = <0x01c10000 0x1000>; - clocks = <&ccu CLK_BUS_MMC1>, - <&ccu CLK_MMC1>, - <&ccu CLK_MMC1_OUTPUT>, - <&ccu CLK_MMC1_SAMPLE>; - clock-names = "ahb", - "mmc", - "output", - "sample"; - resets = <&ccu RST_BUS_MMC1>; - reset-names = "ahb"; - interrupts = ; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc2: mmc@1c11000 { - compatible = "allwinner,sun7i-a20-mmc"; - reg = <0x01c11000 0x1000>; - clocks = <&ccu CLK_BUS_MMC2>, - <&ccu CLK_MMC2>, - <&ccu CLK_MMC2_OUTPUT>, - <&ccu CLK_MMC2_SAMPLE>; - clock-names = "ahb", - "mmc", - "output", - "sample"; - resets = <&ccu RST_BUS_MMC2>; - reset-names = "ahb"; - interrupts = ; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - usb_otg: usb@1c19000 { - /* compatible gets set in SoC specific dtsi file */ - reg = <0x01c19000 0x0400>; - clocks = <&ccu CLK_BUS_OTG>; - resets = <&ccu RST_BUS_OTG>; - interrupts = ; - interrupt-names = "mc"; - phys = <&usbphy 0>; - phy-names = "usb"; - extcon = <&usbphy 0>; - dr_mode = "otg"; - status = "disabled"; - }; - - usbphy: phy@1c19400 { - /* - * compatible and address regions get set in - * SoC specific dtsi file - */ - clocks = <&ccu CLK_USB_PHY0>, - <&ccu CLK_USB_PHY1>; - clock-names = "usb0_phy", - "usb1_phy"; - resets = <&ccu RST_USB_PHY0>, - <&ccu RST_USB_PHY1>; - reset-names = "usb0_reset", - "usb1_reset"; - status = "disabled"; - #phy-cells = <1>; - }; - - ehci0: usb@1c1a000 { - compatible = "allwinner,sun8i-a23-ehci", "generic-ehci"; - reg = <0x01c1a000 0x100>; - interrupts = ; - clocks = <&ccu CLK_BUS_EHCI>; - resets = <&ccu RST_BUS_EHCI>; - phys = <&usbphy 1>; - phy-names = "usb"; - status = "disabled"; - }; - - ohci0: usb@1c1a400 { - compatible = "allwinner,sun8i-a23-ohci", "generic-ohci"; - reg = <0x01c1a400 0x100>; - interrupts = ; - clocks = <&ccu CLK_BUS_OHCI>, <&ccu CLK_USB_OHCI>; - resets = <&ccu RST_BUS_OHCI>; - phys = <&usbphy 1>; - phy-names = "usb"; - status = "disabled"; - }; - - ccu: clock@1c20000 { - reg = <0x01c20000 0x400>; - clocks = <&osc24M>, <&rtc 0>; - clock-names = "hosc", "losc"; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - pio: pinctrl@1c20800 { - /* compatible gets set in SoC specific dtsi file */ - reg = <0x01c20800 0x400>; - /* interrupts get set in SoC specific dtsi file */ - clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>; - clock-names = "apb", "hosc", "losc"; - gpio-controller; - interrupt-controller; - #interrupt-cells = <3>; - #gpio-cells = <3>; - - i2c0_pins: i2c0-pins { - pins = "PH2", "PH3"; - function = "i2c0"; - }; - - i2c1_pins: i2c1-pins { - pins = "PH4", "PH5"; - function = "i2c1"; - }; - - i2c2_pins: i2c2-pins { - pins = "PE12", "PE13"; - function = "i2c2"; - }; - - lcd_rgb666_pins: lcd-rgb666-pins { - pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", - "PD10", "PD11", "PD12", "PD13", "PD14", "PD15", - "PD18", "PD19", "PD20", "PD21", "PD22", "PD23", - "PD24", "PD25", "PD26", "PD27"; - function = "lcd0"; - }; - - mmc0_pins: mmc0-pins { - pins = "PF0", "PF1", "PF2", - "PF3", "PF4", "PF5"; - function = "mmc0"; - drive-strength = <30>; - bias-pull-up; - }; - - mmc1_pg_pins: mmc1-pg-pins { - pins = "PG0", "PG1", "PG2", - "PG3", "PG4", "PG5"; - function = "mmc1"; - drive-strength = <30>; - bias-pull-up; - }; - - mmc2_8bit_pins: mmc2-8bit-pins { - pins = "PC5", "PC6", "PC8", - "PC9", "PC10", "PC11", - "PC12", "PC13", "PC14", - "PC15", "PC16"; - function = "mmc2"; - drive-strength = <30>; - bias-pull-up; - }; - - nand_pins: nand-pins { - pins = "PC0", "PC1", "PC2", "PC5", - "PC8", "PC9", "PC10", "PC11", - "PC12", "PC13", "PC14", "PC15"; - function = "nand0"; - }; - - nand_cs0_pin: nand-cs0-pin { - pins = "PC4"; - function = "nand0"; - bias-pull-up; - }; - - nand_cs1_pin: nand-cs1-pin { - pins = "PC3"; - function = "nand0"; - bias-pull-up; - }; - - nand_rb0_pin: nand-rb0-pin { - pins = "PC6"; - function = "nand0"; - bias-pull-up; - }; - - nand_rb1_pin: nand-rb1-pin { - pins = "PC7"; - function = "nand0"; - bias-pull-up; - }; - - pwm0_pin: pwm0-pin { - pins = "PH0"; - function = "pwm0"; - }; - - uart0_pf_pins: uart0-pf-pins { - pins = "PF2", "PF4"; - function = "uart0"; - }; - - uart1_pg_pins: uart1-pg-pins { - pins = "PG6", "PG7"; - function = "uart1"; - }; - - uart1_cts_rts_pg_pins: uart1-cts-rts-pg-pins { - pins = "PG8", "PG9"; - function = "uart1"; - }; - }; - - timer@1c20c00 { - compatible = "allwinner,sun8i-a23-timer"; - reg = <0x01c20c00 0xa0>; - interrupts = , - ; - clocks = <&osc24M>; - }; - - wdt0: watchdog@1c20ca0 { - compatible = "allwinner,sun6i-a31-wdt"; - reg = <0x01c20ca0 0x20>; - interrupts = ; - clocks = <&osc24M>; - }; - - pwm: pwm@1c21400 { - compatible = "allwinner,sun7i-a20-pwm"; - reg = <0x01c21400 0xc>; - clocks = <&osc24M>; - #pwm-cells = <3>; - status = "disabled"; - }; - - lradc: lradc@1c22800 { - compatible = "allwinner,sun4i-a10-lradc-keys"; - reg = <0x01c22800 0x100>; - interrupts = ; - status = "disabled"; - }; - - uart0: serial@1c28000 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART0>; - resets = <&ccu RST_BUS_UART0>; - dmas = <&dma 6>, <&dma 6>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart1: serial@1c28400 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28400 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART1>; - resets = <&ccu RST_BUS_UART1>; - dmas = <&dma 7>, <&dma 7>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart2: serial@1c28800 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28800 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART2>; - resets = <&ccu RST_BUS_UART2>; - dmas = <&dma 8>, <&dma 8>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart3: serial@1c28c00 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28c00 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART3>; - resets = <&ccu RST_BUS_UART3>; - dmas = <&dma 9>, <&dma 9>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart4: serial@1c29000 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c29000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART4>; - resets = <&ccu RST_BUS_UART4>; - dmas = <&dma 10>, <&dma 10>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c0: i2c@1c2ac00 { - compatible = "allwinner,sun6i-a31-i2c"; - reg = <0x01c2ac00 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_I2C0>; - resets = <&ccu RST_BUS_I2C0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c1: i2c@1c2b000 { - compatible = "allwinner,sun6i-a31-i2c"; - reg = <0x01c2b000 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_I2C1>; - resets = <&ccu RST_BUS_I2C1>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c2: i2c@1c2b400 { - compatible = "allwinner,sun6i-a31-i2c"; - reg = <0x01c2b400 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_I2C2>; - resets = <&ccu RST_BUS_I2C2>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mali: gpu@1c40000 { - compatible = "allwinner,sun8i-a23-mali", - "allwinner,sun7i-a20-mali", "arm,mali-400"; - reg = <0x01c40000 0x10000>; - interrupts = , - , - , - , - , - , - ; - interrupt-names = "gp", - "gpmmu", - "pp0", - "ppmmu0", - "pp1", - "ppmmu1", - "pmu"; - clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>; - clock-names = "bus", "core"; - resets = <&ccu RST_BUS_GPU>; - #cooling-cells = <2>; - - assigned-clocks = <&ccu CLK_GPU>; - assigned-clock-rates = <384000000>; - }; - - gic: interrupt-controller@1c81000 { - compatible = "arm,gic-400"; - reg = <0x01c81000 0x1000>, - <0x01c82000 0x2000>, - <0x01c84000 0x2000>, - <0x01c86000 0x2000>; - interrupt-controller; - #interrupt-cells = <3>; - interrupts = ; - }; - - fe0: display-frontend@1e00000 { - /* compatible gets set in SoC specific dtsi file */ - reg = <0x01e00000 0x20000>; - interrupts = ; - clocks = <&ccu CLK_BUS_DE_FE>, <&ccu CLK_DE_FE>, - <&ccu CLK_DRAM_DE_FE>; - clock-names = "ahb", "mod", - "ram"; - resets = <&ccu RST_BUS_DE_FE>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - fe0_out: port@1 { - reg = <1>; - - fe0_out_be0: endpoint { - remote-endpoint = <&be0_in_fe0>; - }; - }; - }; - }; - - be0: display-backend@1e60000 { - /* compatible gets set in SoC specific dtsi file */ - reg = <0x01e60000 0x10000>; - interrupts = ; - clocks = <&ccu CLK_BUS_DE_BE>, <&ccu CLK_DE_BE>, - <&ccu CLK_DRAM_DE_BE>; - clock-names = "ahb", "mod", - "ram"; - resets = <&ccu RST_BUS_DE_BE>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - be0_in: port@0 { - reg = <0>; - - be0_in_fe0: endpoint { - remote-endpoint = <&fe0_out_be0>; - }; - }; - - be0_out: port@1 { - reg = <1>; - - be0_out_drc0: endpoint { - remote-endpoint = <&drc0_in_be0>; - }; - }; - }; - }; - - drc0: drc@1e70000 { - /* compatible gets set in SoC specific dtsi file */ - reg = <0x01e70000 0x10000>; - interrupts = ; - clocks = <&ccu CLK_BUS_DRC>, <&ccu CLK_DRC>, - <&ccu CLK_DRAM_DRC>; - clock-names = "ahb", "mod", "ram"; - resets = <&ccu RST_BUS_DRC>; - - assigned-clocks = <&ccu CLK_DRC>; - assigned-clock-rates = <300000000>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - drc0_in: port@0 { - reg = <0>; - - drc0_in_be0: endpoint { - remote-endpoint = <&be0_out_drc0>; - }; - }; - - drc0_out: port@1 { - reg = <1>; - - drc0_out_tcon0: endpoint { - remote-endpoint = <&tcon0_in_drc0>; - }; - }; - }; - }; - - rtc: rtc@1f00000 { - compatible = "allwinner,sun8i-a23-rtc"; - reg = <0x01f00000 0x400>; - interrupts = , - ; - clock-output-names = "osc32k", "osc32k-out"; - clocks = <&ext_osc32k>; - #clock-cells = <1>; - }; - - nmi_intc: interrupt-controller@1f00c00 { - compatible = "allwinner,sun6i-a31-r-intc"; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x01f00c00 0x400>; - interrupts = ; - }; - - prcm@1f01400 { - compatible = "allwinner,sun8i-a23-prcm"; - reg = <0x01f01400 0x200>; - - ar100: ar100_clk { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clock-div = <1>; - clock-mult = <1>; - clocks = <&osc24M>; - clock-output-names = "ar100"; - }; - - ahb0: ahb0_clk { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clock-div = <1>; - clock-mult = <1>; - clocks = <&ar100>; - clock-output-names = "ahb0"; - }; - - apb0: apb0_clk { - compatible = "allwinner,sun8i-a23-apb0-clk"; - #clock-cells = <0>; - clocks = <&ahb0>; - clock-output-names = "apb0"; - }; - - apb0_gates: apb0_gates_clk { - compatible = "allwinner,sun8i-a23-apb0-gates-clk"; - #clock-cells = <1>; - clocks = <&apb0>; - clock-output-names = "apb0_pio", "apb0_timer", - "apb0_rsb", "apb0_uart", - "apb0_i2c"; - }; - - apb0_rst: apb0_rst { - compatible = "allwinner,sun6i-a31-clock-reset"; - #reset-cells = <1>; - }; - - codec_analog: codec-analog { - compatible = "allwinner,sun8i-a23-codec-analog"; - }; - }; - - cpucfg@1f01c00 { - compatible = "allwinner,sun8i-a23-cpuconfig"; - reg = <0x01f01c00 0x300>; - }; - - r_uart: serial@1f02800 { - compatible = "snps,dw-apb-uart"; - reg = <0x01f02800 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&apb0_gates 4>; - resets = <&apb0_rst 4>; - status = "disabled"; - }; - - r_i2c: i2c@1f02400 { - compatible = "allwinner,sun8i-a23-i2c", - "allwinner,sun6i-a31-i2c"; - reg = <0x01f02400 0x400>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&r_i2c_pins>; - clocks = <&apb0_gates 6>; - resets = <&apb0_rst 6>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - r_pio: pinctrl@1f02c00 { - compatible = "allwinner,sun8i-a23-r-pinctrl"; - reg = <0x01f02c00 0x400>; - interrupts = ; - clocks = <&apb0_gates 0>, <&osc24M>, <&rtc 0>; - clock-names = "apb", "hosc", "losc"; - resets = <&apb0_rst 0>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <3>; - #gpio-cells = <3>; - - r_i2c_pins: r-i2c-pins { - pins = "PL0", "PL1"; - function = "s_i2c"; - bias-pull-up; - }; - - r_rsb_pins: r-rsb-pins { - pins = "PL0", "PL1"; - function = "s_rsb"; - drive-strength = <20>; - bias-pull-up; - }; - - r_uart_pins_a: r-uart-pins { - pins = "PL2", "PL3"; - function = "s_uart"; - }; - }; - - r_rsb: rsb@1f03400 { - compatible = "allwinner,sun8i-a23-rsb"; - reg = <0x01f03400 0x400>; - interrupts = ; - clocks = <&apb0_gates 3>; - clock-frequency = <3000000>; - resets = <&apb0_rst 3>; - pinctrl-names = "default"; - pinctrl-0 = <&r_rsb_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/sun8i-a23-evb.dts b/sys/gnu/dts/arm/sun8i-a23-evb.dts deleted file mode 100644 index 53fb1be0401..00000000000 --- a/sys/gnu/dts/arm/sun8i-a23-evb.dts +++ /dev/null @@ -1,117 +0,0 @@ -/* - * Copyright 2015 Maxime Ripard - * - * Maxime Ripard - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun8i-a23.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include - -/ { - model = "Allwinner A23 Evaluation Board"; - compatible = "allwinner,sun8i-a23-evb", "allwinner,sun8i-a23"; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - serial0 = &r_uart; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&i2c0 { - status = "okay"; -}; - -&i2c1 { - status = "okay"; -}; - -&lradc { - vref-supply = <®_vcc3v0>; - status = "okay"; - - button-190 { - label = "Volume Up"; - linux,code = ; - channel = <0>; - voltage = <190000>; - }; - - button-390 { - label = "Volume Down"; - linux,code = ; - channel = <0>; - voltage = <390000>; - }; - - button-600 { - label = "Home"; - linux,code = ; - channel = <0>; - voltage = <600000>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v0>; - bus-width = <4>; - cd-gpios = <&pio 1 4 GPIO_ACTIVE_LOW>; /* PB4 */ - status = "okay"; -}; - -/* - * The RX line has a non-populated resistance. In order to use it, you - * need to solder R207 on the back of the board in order to close the - * line and get a working UART. - */ -&r_uart { - pinctrl-names = "default"; - pinctrl-0 = <&r_uart_pins_a>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun8i-a23-gt90h-v4.dts b/sys/gnu/dts/arm/sun8i-a23-gt90h-v4.dts deleted file mode 100644 index bcbc9b0758f..00000000000 --- a/sys/gnu/dts/arm/sun8i-a23-gt90h-v4.dts +++ /dev/null @@ -1,76 +0,0 @@ -/* - * Copyright 2015 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun8i-a23.dtsi" -#include "sun8i-reference-design-tablet.dtsi" - -/ { - model = "Allwinner GT90H Dual Core Tablet (v4)"; - compatible = "allwinner,gt90h-v4", "allwinner,sun8i-a23"; -}; - -&ehci0 { - status = "okay"; -}; - -&touchscreen { - reg = <0x40>; - compatible = "silead,gsl3675"; - firmware-name = "gsl3675-gt90h.fw"; - touchscreen-size-x = <1792>; - touchscreen-size-y = <1024>; - status = "okay"; -}; - -&lradc { - button-600 { - label = "Back"; - linux,code = ; - channel = <0>; - voltage = <600000>; - }; -}; - -&usbphy { - usb1_vbus-supply = <®_dldo1>; -}; diff --git a/sys/gnu/dts/arm/sun8i-a23-inet86dz.dts b/sys/gnu/dts/arm/sun8i-a23-inet86dz.dts deleted file mode 100644 index d4405752a41..00000000000 --- a/sys/gnu/dts/arm/sun8i-a23-inet86dz.dts +++ /dev/null @@ -1,67 +0,0 @@ -/* - * Copyright 2016 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun8i-a23.dtsi" -#include "sun8i-reference-design-tablet.dtsi" - -/ { - model = "INet-86DZ Rev 01"; - compatible = "primux,inet86dz", "allwinner,sun8i-a23"; -}; - -&ehci0 { - status = "okay"; -}; - -&touchscreen { - reg = <0x40>; - compatible = "silead,gsl1680"; - firmware-name = "gsl1680-inet86dz.fw"; - touchscreen-size-x = <960>; - touchscreen-size-y = <640>; - status = "okay"; -}; - -&usbphy { - usb1_vbus-supply = <®_dldo1>; -}; diff --git a/sys/gnu/dts/arm/sun8i-a23-ippo-q8h-v1.2.dts b/sys/gnu/dts/arm/sun8i-a23-ippo-q8h-v1.2.dts deleted file mode 100644 index 51097c77a15..00000000000 --- a/sys/gnu/dts/arm/sun8i-a23-ippo-q8h-v1.2.dts +++ /dev/null @@ -1,73 +0,0 @@ -/* - * Copyright 2015 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun8i-a23.dtsi" -#include "sun8i-q8-common.dtsi" - -/ { - model = "Q8 A23 Tablet"; - compatible = "allwinner,q8-a23", "allwinner,sun8i-a23"; -}; - -&codec { - allwinner,pa-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */ - allwinner,audio-routing = - "Headphone", "HP", - "Headphone", "HPCOM", - "Speaker", "HP", - "MIC1", "Mic", - "MIC2", "Headset Mic", - "Mic", "MBIAS", - "Headset Mic", "HBIAS"; - status = "okay"; -}; - -&panel { - compatible = "bananapi,s070wv20-ct16"; -}; - -&tcon0_out { - tcon0_out_lcd: endpoint { - remote-endpoint = <&panel_input>; - }; -}; diff --git a/sys/gnu/dts/arm/sun8i-a23-ippo-q8h-v5.dts b/sys/gnu/dts/arm/sun8i-a23-ippo-q8h-v5.dts deleted file mode 100644 index 51097c77a15..00000000000 --- a/sys/gnu/dts/arm/sun8i-a23-ippo-q8h-v5.dts +++ /dev/null @@ -1,73 +0,0 @@ -/* - * Copyright 2015 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun8i-a23.dtsi" -#include "sun8i-q8-common.dtsi" - -/ { - model = "Q8 A23 Tablet"; - compatible = "allwinner,q8-a23", "allwinner,sun8i-a23"; -}; - -&codec { - allwinner,pa-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */ - allwinner,audio-routing = - "Headphone", "HP", - "Headphone", "HPCOM", - "Speaker", "HP", - "MIC1", "Mic", - "MIC2", "Headset Mic", - "Mic", "MBIAS", - "Headset Mic", "HBIAS"; - status = "okay"; -}; - -&panel { - compatible = "bananapi,s070wv20-ct16"; -}; - -&tcon0_out { - tcon0_out_lcd: endpoint { - remote-endpoint = <&panel_input>; - }; -}; diff --git a/sys/gnu/dts/arm/sun8i-a23-polaroid-mid2407pxe03.dts b/sys/gnu/dts/arm/sun8i-a23-polaroid-mid2407pxe03.dts deleted file mode 100644 index d5f6aebd721..00000000000 --- a/sys/gnu/dts/arm/sun8i-a23-polaroid-mid2407pxe03.dts +++ /dev/null @@ -1,96 +0,0 @@ -/* - * Copyright 2016 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun8i-a23.dtsi" -#include "sun8i-reference-design-tablet.dtsi" - -/ { - model = "Polaroid MID2407PXE03 tablet"; - compatible = "polaroid,mid2407pxe03", "allwinner,sun8i-a23"; - - aliases { - ethernet0 = &esp8089; - }; - - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&r_pio 0 6 GPIO_ACTIVE_LOW>; /* PL6 */ - /* The esp8089 needs 200 ms after driving wifi-en high */ - post-power-on-delay-ms = <200>; - }; -}; - -&i2c1 { - mma7660: accelerometer@4c { - reg = <0x4c>; - compatible = "fsl,mma7660"; - }; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pg_pins>; - vmmc-supply = <®_dldo1>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; - - esp8089: sdio_wifi@1 { - compatible = "esp,esp8089"; - reg = <1>; - esp,crystal-26M-en = <2>; - }; -}; - -&touchscreen { - reg = <0x40>; - compatible = "silead,gsl1680"; - firmware-name = "gsl1680-polaroid-mid2407pxe03.fw"; - touchscreen-size-x = <960>; - touchscreen-size-y = <640>; - touchscreen-inverted-x; - touchscreen-inverted-y; - vddio-supply = <®_ldo_io1>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun8i-a23-polaroid-mid2809pxe04.dts b/sys/gnu/dts/arm/sun8i-a23-polaroid-mid2809pxe04.dts deleted file mode 100644 index 9f9232a2fef..00000000000 --- a/sys/gnu/dts/arm/sun8i-a23-polaroid-mid2809pxe04.dts +++ /dev/null @@ -1,86 +0,0 @@ -/* - * Copyright 2016 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun8i-a23.dtsi" -#include "sun8i-reference-design-tablet.dtsi" - -/ { - model = "Polaroid MID2809PXE04 tablet"; - compatible = "polaroid,mid2809pxe04", "allwinner,sun8i-a23"; - - aliases { - ethernet0 = &esp8089; - }; - - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&r_pio 0 6 GPIO_ACTIVE_LOW>; /* PL6 */ - /* The esp8089 needs 200 ms after driving wifi-en high */ - post-power-on-delay-ms = <200>; - }; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pg_pins>; - vmmc-supply = <®_dldo1>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; - - esp8089: sdio_wifi@1 { - compatible = "esp,esp8089"; - reg = <1>; - esp,crystal-26M-en = <2>; - }; -}; - -&touchscreen { - reg = <0x40>; - compatible = "silead,gsl3670"; - firmware-name = "gsl3670-polaroid-mid2809pxe04.fw"; - touchscreen-size-x = <1660>; - touchscreen-size-y = <890>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun8i-a23-q8-tablet.dts b/sys/gnu/dts/arm/sun8i-a23-q8-tablet.dts deleted file mode 100644 index 51097c77a15..00000000000 --- a/sys/gnu/dts/arm/sun8i-a23-q8-tablet.dts +++ /dev/null @@ -1,73 +0,0 @@ -/* - * Copyright 2015 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun8i-a23.dtsi" -#include "sun8i-q8-common.dtsi" - -/ { - model = "Q8 A23 Tablet"; - compatible = "allwinner,q8-a23", "allwinner,sun8i-a23"; -}; - -&codec { - allwinner,pa-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */ - allwinner,audio-routing = - "Headphone", "HP", - "Headphone", "HPCOM", - "Speaker", "HP", - "MIC1", "Mic", - "MIC2", "Headset Mic", - "Mic", "MBIAS", - "Headset Mic", "HBIAS"; - status = "okay"; -}; - -&panel { - compatible = "bananapi,s070wv20-ct16"; -}; - -&tcon0_out { - tcon0_out_lcd: endpoint { - remote-endpoint = <&panel_input>; - }; -}; diff --git a/sys/gnu/dts/arm/sun8i-a23.dtsi b/sys/gnu/dts/arm/sun8i-a23.dtsi deleted file mode 100644 index a5e884a8b2a..00000000000 --- a/sys/gnu/dts/arm/sun8i-a23.dtsi +++ /dev/null @@ -1,104 +0,0 @@ -/* - * Copyright 2014 Chen-Yu Tsai - * - * Chen-Yu Tsai - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "sun8i-a23-a33.dtsi" - -/ { - soc { - codec: codec@1c22c00 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun8i-a23-codec"; - reg = <0x01c22c00 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; - clock-names = "apb", "codec"; - resets = <&ccu RST_BUS_CODEC>; - dmas = <&dma 15>, <&dma 15>; - dma-names = "rx", "tx"; - allwinner,codec-analog-controls = <&codec_analog>; - status = "disabled"; - }; - }; -}; - -&be0 { - compatible = "allwinner,sun8i-a23-display-backend"; -}; - -&ccu { - compatible = "allwinner,sun8i-a23-ccu"; -}; - -&de { - compatible = "allwinner,sun8i-a23-display-engine"; -}; - -&drc0 { - compatible = "allwinner,sun8i-a23-drc"; -}; - -&fe0 { - compatible = "allwinner,sun8i-a23-display-frontend"; -}; - -&pio { - compatible = "allwinner,sun8i-a23-pinctrl"; - interrupts = , - , - ; -}; - -&tcon0 { - compatible = "allwinner,sun8i-a23-tcon"; -}; - -&usb_otg { - compatible = "allwinner,sun6i-a31-musb"; -}; - -&usbphy { - compatible = "allwinner,sun8i-a23-usb-phy"; - reg = <0x01c19400 0x10>, <0x01c1a800 0x4>; - reg-names = "phy_ctrl", "pmu1"; -}; diff --git a/sys/gnu/dts/arm/sun8i-a33-et-q8-v1.6.dts b/sys/gnu/dts/arm/sun8i-a33-et-q8-v1.6.dts deleted file mode 100644 index 9c5750c2561..00000000000 --- a/sys/gnu/dts/arm/sun8i-a33-et-q8-v1.6.dts +++ /dev/null @@ -1,57 +0,0 @@ -/* - * Copyright 2015 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun8i-a33.dtsi" -#include "sun8i-q8-common.dtsi" - -/ { - model = "Q8 A33 Tablet"; - compatible = "allwinner,q8-a33", "allwinner,sun8i-a33"; -}; - -&tcon0_out { - tcon0_out_lcd: endpoint@0 { - reg = <0>; - remote-endpoint = <&panel_input>; - }; -}; diff --git a/sys/gnu/dts/arm/sun8i-a33-ga10h-v1.1.dts b/sys/gnu/dts/arm/sun8i-a33-ga10h-v1.1.dts deleted file mode 100644 index 2dfdd0a3151..00000000000 --- a/sys/gnu/dts/arm/sun8i-a33-ga10h-v1.1.dts +++ /dev/null @@ -1,95 +0,0 @@ -/* - * Copyright 2015 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun8i-a33.dtsi" -#include "sun8i-reference-design-tablet.dtsi" - -/ { - model = "Allwinner GA10H Quad Core Tablet (v1.1)"; - compatible = "allwinner,ga10h-v1.1", "allwinner,sun8i-a33"; - - aliases { - /* Make u-boot set mac-address for rtl8703as (no eeprom) */ - ethernet0 = &rtl8703as; - }; -}; - -&ehci0 { - status = "okay"; -}; - -&touchscreen { - reg = <0x40>; - compatible = "silead,gsl3675"; - firmware-name = "gsl3675-ga10h.fw"; - touchscreen-size-x = <1630>; - touchscreen-size-y = <990>; - touchscreen-inverted-y; - status = "okay"; -}; - -&lradc { - button-600 { - label = "Back"; - linux,code = ; - channel = <0>; - voltage = <600000>; - }; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pg_pins>; - vmmc-supply = <®_dldo1>; - bus-width = <4>; - non-removable; - status = "okay"; - - rtl8703as: sdio_wifi@1 { - reg = <1>; - }; -}; - -&ohci0 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun8i-a33-inet-d978-rev2.dts b/sys/gnu/dts/arm/sun8i-a33-inet-d978-rev2.dts deleted file mode 100644 index 317763069c0..00000000000 --- a/sys/gnu/dts/arm/sun8i-a33-inet-d978-rev2.dts +++ /dev/null @@ -1,103 +0,0 @@ -/* - * Copyright 2015 Hans de Goede - * Copyright 2016 Icenowy Zheng - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun8i-a33.dtsi" -#include "sun8i-reference-design-tablet.dtsi" - -/ { - model = "INet-D978 Rev 02"; - compatible = "primux,inet-d978-rev2", "allwinner,sun8i-a33"; - - aliases { - serial0 = &uart1; - }; - - chosen { - /* Delete debug UART as serial0 is the UART for bluetooth */ - /delete-property/stdout-path; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pin_d978>; - - home { - label = "d978:blue:home"; - gpios = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* PL5 */ - }; - }; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pg_pins>; - vmmc-supply = <®_dldo1>; - bus-width = <4>; - non-removable; - status = "okay"; - - rtl8723bs: sdio_wifi@1 { - reg = <1>; - }; -}; - -&r_pio { - led_pin_d978: led-pin { - pins = "PL5"; - function = "gpio_out"; - drive-strength = <20>; - }; -}; - -&r_uart { - status = "disabled"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pg_pins>, - <&uart1_cts_rts_pg_pins>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun8i-a33-ippo-q8h-v1.2.dts b/sys/gnu/dts/arm/sun8i-a33-ippo-q8h-v1.2.dts deleted file mode 100644 index 9c5750c2561..00000000000 --- a/sys/gnu/dts/arm/sun8i-a33-ippo-q8h-v1.2.dts +++ /dev/null @@ -1,57 +0,0 @@ -/* - * Copyright 2015 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun8i-a33.dtsi" -#include "sun8i-q8-common.dtsi" - -/ { - model = "Q8 A33 Tablet"; - compatible = "allwinner,q8-a33", "allwinner,sun8i-a33"; -}; - -&tcon0_out { - tcon0_out_lcd: endpoint@0 { - reg = <0>; - remote-endpoint = <&panel_input>; - }; -}; diff --git a/sys/gnu/dts/arm/sun8i-a33-olinuxino.dts b/sys/gnu/dts/arm/sun8i-a33-olinuxino.dts deleted file mode 100644 index 3d78169cdee..00000000000 --- a/sys/gnu/dts/arm/sun8i-a33-olinuxino.dts +++ /dev/null @@ -1,226 +0,0 @@ -/* - * Copyright 2016 - Stefan Mavrodiev - * Olimex LTD. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun8i-a33.dtsi" - -#include -#include - -/ { - model = "Olimex A33-OLinuXino"; - compatible = "olimex,a33-olinuxino","allwinner,sun8i-a33"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - green { - label = "a33-olinuxino:green:usr"; - gpios = <&pio 1 7 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&codec { - status = "okay"; -}; - -&dai { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&mmc0 { - vmmc-supply = <®_dcdc1>; - bus-width = <4>; - cd-gpios = <&pio 1 4 GPIO_ACTIVE_LOW>; /* PB4 */ - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&r_rsb { - status = "okay"; - - axp22x: pmic@3a3 { - compatible = "x-powers,axp223"; - reg = <0x3a3>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - eldoin-supply = <®_dcdc1>; - x-powers,drive-vbus-en; - }; -}; - -#include "axp223.dtsi" - -&ac_power_supply { - status = "okay"; -}; - -&battery_power_supply { - status = "okay"; -}; - -®_aldo1 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-io"; -}; - -®_aldo2 { - regulator-always-on; - regulator-min-microvolt = <2350000>; - regulator-max-microvolt = <2650000>; - regulator-name = "vdd-dll"; -}; - -®_aldo3 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-avcc"; -}; - -®_dc1sw { - regulator-name = "vcc-lcd"; -}; - -®_dc5ldo { - regulator-always-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpus"; -}; - -®_dcdc1 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-3v3"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-sys"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc5 { - regulator-always-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vcc-dram"; -}; - -®_drivevbus { - regulator-name = "usb0-vbus"; - status = "okay"; -}; - -®_rtc_ldo { - regulator-name = "vcc-rtc"; -}; - -&simplefb_lcd { - vcc-lcd-supply = <®_dc1sw>; -}; - -&sound { - /* Board level jack widgets */ - simple-audio-card,widgets = "Microphone", "Microphone Jack", - "Headphone", "Headphone Jack"; - /* Board level routing. First 2 routes copied from SoC level */ - simple-audio-card,routing = - "Left DAC", "AIF1 Slot 0 Left", - "Right DAC", "AIF1 Slot 0 Right", - "HP", "HPCOM", - "Headphone Jack", "HP", - "MIC1", "Microphone Jack", - "Microphone Jack", "MBIAS"; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usb_power_supply { - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */ - usb0_vbus_power-supply = <&usb_power_supply>; - usb0_vbus-supply = <®_drivevbus>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun8i-a33-q8-tablet.dts b/sys/gnu/dts/arm/sun8i-a33-q8-tablet.dts deleted file mode 100644 index 9c5750c2561..00000000000 --- a/sys/gnu/dts/arm/sun8i-a33-q8-tablet.dts +++ /dev/null @@ -1,57 +0,0 @@ -/* - * Copyright 2015 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun8i-a33.dtsi" -#include "sun8i-q8-common.dtsi" - -/ { - model = "Q8 A33 Tablet"; - compatible = "allwinner,q8-a33", "allwinner,sun8i-a33"; -}; - -&tcon0_out { - tcon0_out_lcd: endpoint@0 { - reg = <0>; - remote-endpoint = <&panel_input>; - }; -}; diff --git a/sys/gnu/dts/arm/sun8i-a33-sinlinx-sina33.dts b/sys/gnu/dts/arm/sun8i-a33-sinlinx-sina33.dts deleted file mode 100644 index 785798e3a10..00000000000 --- a/sys/gnu/dts/arm/sun8i-a33-sinlinx-sina33.dts +++ /dev/null @@ -1,274 +0,0 @@ -/* - * Copyright 2015 Chen-Yu Tsai - * - * Chen-Yu Tsai - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun8i-a33.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include - -/ { - model = "Sinlinx SinA33"; - compatible = "sinlinx,sina33", "allwinner,sun8i-a33"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - panel { - compatible = "netron-dy,e231732"; - - port { - panel_input: endpoint { - remote-endpoint = <&tcon0_out_panel>; - }; - }; - }; -}; - -&codec { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <®_dcdc3>; -}; - -&cpu0_opp_table { - opp-1104000000 { - opp-hz = /bits/ 64 <1104000000>; - opp-microvolt = <1320000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - }; - - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <1320000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - }; -}; - -&de { - status = "okay"; -}; - -&dai { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&lradc { - vref-supply = <®_dcdc1>; - status = "okay"; - - button-200 { - label = "Volume Up"; - linux,code = ; - channel = <0>; - voltage = <191011>; - }; - - button-400 { - label = "Volume Down"; - linux,code = ; - channel = <0>; - voltage = <391304>; - }; - - button-600 { - label = "Home"; - linux,code = ; - channel = <0>; - voltage = <600000>; - }; -}; - -&mmc0 { - vmmc-supply = <®_dcdc1>; - bus-width = <4>; - cd-gpios = <&pio 1 4 GPIO_ACTIVE_LOW>; /* PB4 */ - status = "okay"; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_8bit_pins>; - vmmc-supply = <®_dcdc1>; - bus-width = <8>; - non-removable; - cap-mmc-hw-reset; - status = "okay"; -}; - -&mmc2_8bit_pins { - /* Increase drive strength for DDR modes */ - drive-strength = <40>; -}; - -&ohci0 { - status = "okay"; -}; - -&r_rsb { - status = "okay"; - - axp22x: pmic@3a3 { - compatible = "x-powers,axp223"; - reg = <0x3a3>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - eldoin-supply = <®_dcdc1>; - }; -}; - -#include "axp223.dtsi" - -&ac_power_supply { - status = "okay"; -}; - -&battery_power_supply { - status = "okay"; -}; - -®_aldo1 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-io"; -}; - -®_aldo2 { - regulator-always-on; - regulator-min-microvolt = <2350000>; - regulator-max-microvolt = <2650000>; - regulator-name = "vdd-dll"; -}; - -®_aldo3 { - regulator-always-on; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-pll-avcc"; -}; - -®_dc5ldo { - regulator-always-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpus"; -}; - -®_dcdc1 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-3v0"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-sys"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc5 { - regulator-always-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vcc-dram"; -}; - -®_rtc_ldo { - regulator-name = "vcc-rtc"; -}; - -&sound { - status = "okay"; -}; - -&tcon0 { - pinctrl-names = "default"; - pinctrl-0 = <&lcd_rgb666_pins>; - status = "okay"; -}; - -&tcon0_out { - tcon0_out_panel: endpoint@0 { - reg = <0>; - remote-endpoint = <&panel_input>; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "peripheral"; - status = "okay"; -}; - -&usbphy { - status = "okay"; - usb1_vbus-supply = <®_vcc5v0>; /* USB1 VBUS is always on */ -}; diff --git a/sys/gnu/dts/arm/sun8i-a33.dtsi b/sys/gnu/dts/arm/sun8i-a33.dtsi deleted file mode 100644 index a2c37adacf7..00000000000 --- a/sys/gnu/dts/arm/sun8i-a33.dtsi +++ /dev/null @@ -1,433 +0,0 @@ -/* - * Copyright 2014 Chen-Yu Tsai - * - * Chen-Yu Tsai - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "sun8i-a23-a33.dtsi" -#include - -/ { - cpu0_opp_table: opp_table0 { - compatible = "operating-points-v2"; - opp-shared; - - opp-120000000 { - opp-hz = /bits/ 64 <120000000>; - opp-microvolt = <1040000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - }; - - opp-240000000 { - opp-hz = /bits/ 64 <240000000>; - opp-microvolt = <1040000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - }; - - opp-312000000 { - opp-hz = /bits/ 64 <312000000>; - opp-microvolt = <1040000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - }; - - opp-408000000 { - opp-hz = /bits/ 64 <408000000>; - opp-microvolt = <1040000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - }; - - opp-480000000 { - opp-hz = /bits/ 64 <480000000>; - opp-microvolt = <1040000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - }; - - opp-504000000 { - opp-hz = /bits/ 64 <504000000>; - opp-microvolt = <1040000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - }; - - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <1040000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - }; - - opp-648000000 { - opp-hz = /bits/ 64 <648000000>; - opp-microvolt = <1040000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - }; - - opp-720000000 { - opp-hz = /bits/ 64 <720000000>; - opp-microvolt = <1100000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - }; - - opp-816000000 { - opp-hz = /bits/ 64 <816000000>; - opp-microvolt = <1100000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - }; - - opp-912000000 { - opp-hz = /bits/ 64 <912000000>; - opp-microvolt = <1200000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - }; - - opp-1008000000 { - opp-hz = /bits/ 64 <1008000000>; - opp-microvolt = <1200000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - }; - }; - - cpus { - cpu@0 { - clocks = <&ccu CLK_CPUX>; - clock-names = "cpu"; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; - }; - - cpu1: cpu@1 { - clocks = <&ccu CLK_CPUX>; - clock-names = "cpu"; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; - }; - - cpu2: cpu@2 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <2>; - clocks = <&ccu CLK_CPUX>; - clock-names = "cpu"; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; - }; - - cpu3: cpu@3 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <3>; - clocks = <&ccu CLK_CPUX>; - clock-names = "cpu"; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; - }; - }; - - iio-hwmon { - compatible = "iio-hwmon"; - io-channels = <&ths>; - }; - - mali_opp_table: gpu-opp-table { - compatible = "operating-points-v2"; - - opp-144000000 { - opp-hz = /bits/ 64 <144000000>; - }; - - opp-240000000 { - opp-hz = /bits/ 64 <240000000>; - }; - - opp-384000000 { - opp-hz = /bits/ 64 <384000000>; - }; - }; - - sound: sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "sun8i-a33-audio"; - simple-audio-card,format = "i2s"; - simple-audio-card,frame-master = <&link_codec>; - simple-audio-card,bitclock-master = <&link_codec>; - simple-audio-card,mclk-fs = <128>; - simple-audio-card,aux-devs = <&codec_analog>; - simple-audio-card,routing = - "Left DAC", "AIF1 Slot 0 Left", - "Right DAC", "AIF1 Slot 0 Right"; - status = "disabled"; - - simple-audio-card,cpu { - sound-dai = <&dai>; - }; - - link_codec: simple-audio-card,codec { - sound-dai = <&codec>; - }; - }; - - soc { - video-codec@1c0e000 { - compatible = "allwinner,sun8i-a33-video-engine"; - reg = <0x01c0e000 0x1000>; - clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, - <&ccu CLK_DRAM_VE>; - clock-names = "ahb", "mod", "ram"; - resets = <&ccu RST_BUS_VE>; - interrupts = ; - allwinner,sram = <&ve_sram 1>; - }; - - crypto: crypto-engine@1c15000 { - compatible = "allwinner,sun8i-a33-crypto"; - reg = <0x01c15000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_BUS_SS>, <&ccu CLK_SS>; - clock-names = "ahb", "mod"; - resets = <&ccu RST_BUS_SS>; - reset-names = "ahb"; - }; - - dai: dai@1c22c00 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun6i-a31-i2s"; - reg = <0x01c22c00 0x200>; - interrupts = ; - clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; - clock-names = "apb", "mod"; - resets = <&ccu RST_BUS_CODEC>; - dmas = <&dma 15>, <&dma 15>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - codec: codec@1c22e00 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun8i-a33-codec"; - reg = <0x01c22e00 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; - clock-names = "bus", "mod"; - status = "disabled"; - }; - - ths: ths@1c25000 { - compatible = "allwinner,sun8i-a33-ths"; - reg = <0x01c25000 0x100>; - #thermal-sensor-cells = <0>; - #io-channel-cells = <0>; - }; - - dsi: dsi@1ca0000 { - compatible = "allwinner,sun6i-a31-mipi-dsi"; - reg = <0x01ca0000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_BUS_MIPI_DSI>, - <&ccu CLK_DSI_SCLK>; - clock-names = "bus", "mod"; - resets = <&ccu RST_BUS_MIPI_DSI>; - phys = <&dphy>; - phy-names = "dphy"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - - port { - dsi_in_tcon0: endpoint { - remote-endpoint = <&tcon0_out_dsi>; - }; - }; - }; - - dphy: d-phy@1ca1000 { - compatible = "allwinner,sun6i-a31-mipi-dphy"; - reg = <0x01ca1000 0x1000>; - clocks = <&ccu CLK_BUS_MIPI_DSI>, - <&ccu CLK_DSI_DPHY>; - clock-names = "bus", "mod"; - resets = <&ccu RST_BUS_MIPI_DSI>; - status = "disabled"; - #phy-cells = <0>; - }; - }; - - thermal-zones { - cpu_thermal { - /* milliseconds */ - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&ths>; - - cooling-maps { - map0 { - trip = <&cpu_alert0>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu_alert1>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - - map2 { - trip = <&gpu_alert0>; - cooling-device = <&mali 1 THERMAL_NO_LIMIT>; - }; - - map3 { - trip = <&gpu_alert1>; - cooling-device = <&mali 2 THERMAL_NO_LIMIT>; - }; - }; - - trips { - cpu_alert0: cpu_alert0 { - /* milliCelsius */ - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - - gpu_alert0: gpu_alert0 { - /* milliCelsius */ - temperature = <85000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu_alert1: cpu_alert1 { - /* milliCelsius */ - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - - gpu_alert1: gpu_alert1 { - /* milliCelsius */ - temperature = <95000>; - hysteresis = <2000>; - type = "hot"; - }; - - cpu_crit: cpu_crit { - /* milliCelsius */ - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - }; -}; - -&be0 { - compatible = "allwinner,sun8i-a33-display-backend"; - /* A33 has an extra "SAT" module packed inside the display backend */ - reg = <0x01e60000 0x10000>, <0x01e80000 0x1000>; - reg-names = "be", "sat"; - clocks = <&ccu CLK_BUS_DE_BE>, <&ccu CLK_DE_BE>, - <&ccu CLK_DRAM_DE_BE>, <&ccu CLK_BUS_SAT>; - clock-names = "ahb", "mod", - "ram", "sat"; - resets = <&ccu RST_BUS_DE_BE>, <&ccu RST_BUS_SAT>; - reset-names = "be", "sat"; - assigned-clocks = <&ccu CLK_DE_BE>; - assigned-clock-rates = <300000000>; -}; - -&ccu { - compatible = "allwinner,sun8i-a33-ccu"; -}; - -&de { - compatible = "allwinner,sun8i-a33-display-engine"; -}; - -&drc0 { - compatible = "allwinner,sun8i-a33-drc"; -}; - -&fe0 { - compatible = "allwinner,sun8i-a33-display-frontend"; -}; - -&mali { - operating-points-v2 = <&mali_opp_table>; -}; - -&pio { - compatible = "allwinner,sun8i-a33-pinctrl"; - interrupts = , - ; - - uart0_pb_pins: uart0-pb-pins { - pins = "PB0", "PB1"; - function = "uart0"; - }; - -}; - -&tcon0 { - compatible = "allwinner,sun8i-a33-tcon"; -}; - -&tcon0_out { - #address-cells = <1>; - #size-cells = <0>; - - tcon0_out_dsi: endpoint@1 { - reg = <1>; - remote-endpoint = <&dsi_in_tcon0>; - }; -}; - -&usb_otg { - compatible = "allwinner,sun8i-a33-musb"; -}; - -&usbphy { - compatible = "allwinner,sun8i-a33-usb-phy"; - reg = <0x01c19400 0x14>, <0x01c1a800 0x4>; - reg-names = "phy_ctrl", "pmu1"; -}; diff --git a/sys/gnu/dts/arm/sun8i-a83t-allwinner-h8homlet-v2.dts b/sys/gnu/dts/arm/sun8i-a83t-allwinner-h8homlet-v2.dts deleted file mode 100644 index 9c006fc1882..00000000000 --- a/sys/gnu/dts/arm/sun8i-a83t-allwinner-h8homlet-v2.dts +++ /dev/null @@ -1,281 +0,0 @@ -/* - * Copyright 2015 Vishnu Patekar - * Vishnu Patekar - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun8i-a83t.dtsi" - -#include - -/ { - model = "Allwinner A83T H8Homlet Proto Dev Board v2.0"; - compatible = "allwinner,h8homlet-v2", "allwinner,sun8i-a83t"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - reg_usb0_vbus: reg-usb0-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb0-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - enable-active-high; - gpio = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* PL5 */ - }; - - reg_usb1_vbus: reg-usb1-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb1-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - enable-active-high; - gpio = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ - }; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&cpu100 { - cpu-supply = <®_dcdc3>; -}; - -&ehci0 { - status = "okay"; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; - vmmc-supply = <®_dcdc1>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ - bus-width = <4>; - status = "okay"; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_8bit_emmc_pins>; - vmmc-supply = <®_dcdc1>; - vqmmc-supply = <®_dcdc1>; - bus-width = <8>; - non-removable; - cap-mmc-hw-reset; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&r_rsb { - status = "okay"; - - axp81x: pmic@3a3 { - compatible = "x-powers,axp818", "x-powers,axp813"; - reg = <0x3a3>; - interrupt-parent = <&r_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - eldoin-supply = <®_dcdc1>; - swin-supply = <®_dcdc1>; - }; - - ac100: codec@e89 { - compatible = "x-powers,ac100"; - reg = <0xe89>; - - ac100_codec: codec { - compatible = "x-powers,ac100-codec"; - interrupt-parent = <&r_pio>; - interrupts = <0 11 IRQ_TYPE_LEVEL_LOW>; /* PL11 */ - #clock-cells = <0>; - clock-output-names = "4M_adda"; - }; - - ac100_rtc: rtc { - compatible = "x-powers,ac100-rtc"; - interrupt-parent = <&r_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - clocks = <&ac100_codec>; - #clock-cells = <1>; - clock-output-names = "cko1_rtc", - "cko2_rtc", - "cko3_rtc"; - }; - }; -}; - -#include "axp81x.dtsi" - -&ac_power_supply { - status = "okay"; -}; - -®_aldo1 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc-1v8"; -}; - -®_aldo2 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "dram-pll"; -}; - -®_aldo3 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_dcdc1 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-3v3"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-cpua"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-cpub"; -}; - -®_dcdc4 { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-gpu"; -}; - -®_dcdc5 { - regulator-always-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vcc-dram"; -}; - -®_dcdc6 { - regulator-always-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - regulator-name = "vdd-sys"; -}; - -®_dldo2 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-mipi"; -}; - -®_dldo4 { - /* - * The PHY requires 20ms after all voltages are applied until core - * logic is ready and 30ms after the reset pin is de-asserted. - * Set a 100ms delay to account for PMIC ramp time and board traces. - */ - regulator-enable-ramp-delay = <100000>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-ephy"; -}; - -®_fldo1 { - regulator-min-microvolt = <1080000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd12-hsic"; -}; - -®_fldo2 { - /* - * Despite the embedded CPUs core not being used in any way, - * this must remain on or the system will hang. - */ - regulator-always-on; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-cpus"; -}; - -®_rtc_ldo { - regulator-name = "vcc-rtc"; -}; - -®_sw { - regulator-name = "vcc-wifi"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usbphy { - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_usb1_vbus>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "host"; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun8i-a83t-bananapi-m3.dts b/sys/gnu/dts/arm/sun8i-a83t-bananapi-m3.dts deleted file mode 100644 index 9d34eabba12..00000000000 --- a/sys/gnu/dts/arm/sun8i-a83t-bananapi-m3.dts +++ /dev/null @@ -1,407 +0,0 @@ -/* - * Copyright 2017 Chen-Yu Tsai - * - * Chen-Yu Tsai - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun8i-a83t.dtsi" - -#include - -/ { - model = "Banana Pi BPI-M3"; - compatible = "sinovoip,bpi-m3", "allwinner,sun8i-a83t"; - - aliases { - ethernet0 = &emac; - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - blue { - label = "bananapi-m3:blue:usr"; - gpios = <&axp_gpio 1 GPIO_ACTIVE_HIGH>; - }; - - green { - label = "bananapi-m3:green:usr"; - gpios = <&axp_gpio 0 GPIO_ACTIVE_HIGH>; - }; - }; - - reg_usb1_vbus: reg-usb1-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb1-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - enable-active-high; - gpio = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */ - }; - - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&ac100_rtc 1>; - clock-names = "ext_clock"; - /* The WiFi low power clock must be 32768 Hz */ - assigned-clocks = <&ac100_rtc 1>; - assigned-clock-rates = <32768>; - /* enables internal regulator and de-asserts reset */ - reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 WL-PMU-EN */ - }; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&cpu100 { - cpu-supply = <®_dcdc3>; -}; - -&de { - status = "okay"; -}; - -&ehci0 { - /* Terminus Tech FE 1.1s 4-port USB 2.0 hub here */ - status = "okay"; - - /* TODO GL830 USB-to-SATA bridge downstream w/ GPIO power controls */ -}; - -&emac { - pinctrl-names = "default"; - pinctrl-0 = <&emac_rgmii_pins>; - phy-supply = <®_sw>; - phy-handle = <&rgmii_phy>; - phy-mode = "rgmii"; - allwinner,rx-delay-ps = <700>; - allwinner,tx-delay-ps = <700>; - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&mdio { - rgmii_phy: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; - vmmc-supply = <®_dcdc1>; - bus-width = <4>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ - status = "okay"; -}; - -&mmc1 { - vmmc-supply = <®_dldo1>; - vqmmc-supply = <®_dldo1>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - interrupt-parent = <&r_pio>; - interrupts = <0 3 IRQ_TYPE_LEVEL_LOW>; - interrupt-names = "host-wake"; - }; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_8bit_emmc_pins>; - vmmc-supply = <®_dcdc1>; - vqmmc-supply = <®_dcdc1>; - bus-width = <8>; - non-removable; - cap-mmc-hw-reset; - status = "okay"; -}; - -&r_cir { - clock-frequency = <3000000>; - status = "okay"; -}; - -&r_rsb { - status = "okay"; - - axp81x: pmic@3a3 { - compatible = "x-powers,axp813"; - reg = <0x3a3>; - interrupt-parent = <&r_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - eldoin-supply = <®_dcdc1>; - fldoin-supply = <®_dcdc5>; - swin-supply = <®_dcdc1>; - x-powers,drive-vbus-en; - }; - - ac100: codec@e89 { - compatible = "x-powers,ac100"; - reg = <0xe89>; - - ac100_codec: codec { - compatible = "x-powers,ac100-codec"; - interrupt-parent = <&r_pio>; - interrupts = <0 11 IRQ_TYPE_LEVEL_LOW>; /* PL11 */ - #clock-cells = <0>; - clock-output-names = "4M_adda"; - }; - - ac100_rtc: rtc { - compatible = "x-powers,ac100-rtc"; - interrupt-parent = <&r_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - clocks = <&ac100_codec>; - #clock-cells = <1>; - clock-output-names = "cko1_rtc", - "cko2_rtc", - "cko3_rtc"; - }; - }; -}; - -#include "axp81x.dtsi" - -&ac_power_supply { - status = "okay"; -}; - -&battery_power_supply { - status = "okay"; -}; - -®_aldo1 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc-1v8"; -}; - -®_aldo2 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "dram-pll"; -}; - -®_aldo3 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_dcdc1 { - /* schematics says 3.1V but FEX file says 3.3V */ - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-3v3"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-cpua"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-cpub"; -}; - -®_dcdc4 { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-gpu"; -}; - -®_dcdc5 { - regulator-always-on; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-name = "vcc-dram"; -}; - -®_dcdc6 { - regulator-always-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - regulator-name = "vdd-sys"; -}; - -®_dldo1 { - /* - * This powers both the WiFi/BT module's main power, I/O supply, - * and external pull-ups on all the data lines. It should be set - * to the same voltage as the I/O supply (DCDC1 in this case) to - * avoid any leakage or mismatch. - */ - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi"; -}; - -®_dldo3 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-pd"; -}; - -®_drivevbus { - regulator-name = "usb0-vbus"; - status = "okay"; -}; - -®_fldo1 { - regulator-min-microvolt = <1080000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd12-hsic"; -}; - -®_fldo2 { - /* - * Despite the embedded CPUs core not being used in any way, - * this must remain on or the system will hang. - */ - regulator-always-on; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-cpus"; -}; - -®_rtc_ldo { - regulator-name = "vcc-rtc"; -}; - -®_sw { - /* - * The PHY requires 20ms after all voltages - * are applied until core logic is ready and - * 30ms after the reset pin is de-asserted. - * Set a 100ms delay to account for PMIC - * ramp time and board traces. - */ - regulator-enable-ramp-delay = <100000>; - regulator-name = "vcc-ephy"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; - uart-has-rtscts; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - clocks = <&ac100_rtc 1>; - clock-names = "lpo"; - vbat-supply = <®_dldo1>; - vddio-supply = <®_dldo1>; - device-wakeup-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */ - host-wakeup-gpios = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* PL5 */ - shutdown-gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */ - }; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usb_power_supply { - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>; /* PH11 */ - usb0_vbus_power-supply = <&usb_power_supply>; - usb0_vbus-supply = <®_drivevbus>; - usb1_vbus-supply = <®_usb1_vbus>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun8i-a83t-cubietruck-plus.dts b/sys/gnu/dts/arm/sun8i-a83t-cubietruck-plus.dts deleted file mode 100644 index d9be511f054..00000000000 --- a/sys/gnu/dts/arm/sun8i-a83t-cubietruck-plus.dts +++ /dev/null @@ -1,464 +0,0 @@ -/* - * Copyright 2015 Chen-Yu Tsai - * - * Chen-Yu Tsai - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun8i-a83t.dtsi" - -#include - -/ { - model = "Cubietech Cubietruck Plus"; - compatible = "cubietech,cubietruck-plus", "allwinner,sun8i-a83t"; - - aliases { - ethernet0 = &emac; - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - blue { - label = "cubietruck-plus:blue:usr"; - gpios = <&pio 3 25 GPIO_ACTIVE_HIGH>; /* PD25 */ - }; - - orange { - label = "cubietruck-plus:orange:usr"; - gpios = <&pio 3 26 GPIO_ACTIVE_HIGH>; /* PD26 */ - }; - - white { - label = "cubietruck-plus:white:usr"; - gpios = <&pio 3 27 GPIO_ACTIVE_HIGH>; /* PD27 */ - }; - - green { - label = "cubietruck-plus:green:usr"; - gpios = <&pio 4 4 GPIO_ACTIVE_HIGH>; /* PE4 */ - }; - }; - - usb-hub { - /* I2C is not connected */ - compatible = "smsc,usb3503"; - initial-mode = <1>; /* initialize in HUB mode */ - disabled-ports = <1>; - intn-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ - reset-gpios = <&pio 4 16 GPIO_ACTIVE_LOW>; /* PE16 */ - connect-gpios = <&pio 4 17 GPIO_ACTIVE_HIGH>; /* PE17 */ - refclk-frequency = <19200000>; - }; - - reg_usb1_vbus: reg-usb1-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb1-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - enable-active-high; - gpio = <&pio 3 29 GPIO_ACTIVE_HIGH>; /* PD29 */ - }; - - reg_usb2_vbus: reg-usb2-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb2-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - enable-active-high; - gpio = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "On-board SPDIF"; - - simple-audio-card,cpu { - sound-dai = <&spdif>; - }; - - simple-audio-card,codec { - sound-dai = <&spdif_out>; - }; - }; - - spdif_out: spdif-out { - #sound-dai-cells = <0>; - compatible = "linux,spdif-dit"; - }; - - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&ac100_rtc 1>; - clock-names = "ext_clock"; - /* The WiFi low power clock must be 32768 Hz */ - assigned-clocks = <&ac100_rtc 1>; - assigned-clock-rates = <32768>; - /* enables internal regulator and de-asserts reset */ - reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 WL-PMU-EN */ - }; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&cpu100 { - cpu-supply = <®_dcdc3>; -}; - -&de { - status = "okay"; -}; - -&ehci0 { - /* GL830 USB-to-SATA bridge here */ - status = "okay"; -}; - -&ehci1 { - /* USB3503 HSIC USB 2.0 hub here */ - status = "okay"; -}; - -&emac { - pinctrl-names = "default"; - pinctrl-0 = <&emac_rgmii_pins>; - phy-supply = <®_dldo4>; - phy-handle = <&rgmii_phy>; - phy-mode = "rgmii"; - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&mdio { - rgmii_phy: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; - vmmc-supply = <®_dcdc1>; - bus-width = <4>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ - status = "okay"; -}; - -&mmc1 { - vmmc-supply = <®_dcdc1>; - vqmmc-supply = <®_sw>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_8bit_emmc_pins>; - vmmc-supply = <®_dcdc1>; - bus-width = <8>; - non-removable; - cap-mmc-hw-reset; - status = "okay"; -}; - -&r_rsb { - status = "okay"; - - axp81x: pmic@3a3 { - compatible = "x-powers,axp818", "x-powers,axp813"; - reg = <0x3a3>; - interrupt-parent = <&r_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - eldoin-supply = <®_dcdc1>; - swin-supply = <®_dcdc1>; - x-powers,drive-vbus-en; - }; - - ac100: codec@e89 { - compatible = "x-powers,ac100"; - reg = <0xe89>; - - ac100_codec: codec { - compatible = "x-powers,ac100-codec"; - interrupt-parent = <&r_pio>; - interrupts = <0 11 IRQ_TYPE_LEVEL_LOW>; /* PL11 */ - #clock-cells = <0>; - clock-output-names = "4M_adda"; - }; - - ac100_rtc: rtc { - compatible = "x-powers,ac100-rtc"; - interrupt-parent = <&r_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - clocks = <&ac100_codec>; - #clock-cells = <1>; - clock-output-names = "cko1_rtc", - "cko2_rtc", - "cko3_rtc"; - }; - }; -}; - -#include "axp81x.dtsi" - -&ac_power_supply { - status = "okay"; -}; - -&battery_power_supply { - status = "okay"; -}; - -®_aldo1 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc-1v8"; -}; - -®_aldo2 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "dram-pll"; -}; - -®_aldo3 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_dcdc1 { - /* - * The schematics say this should be 3.3V, but the FEX file says - * it should be 3V. The latter makes sense, as the WiFi module's - * I/O is indirectly powered from DCDC1, through SW. It is rated - * at 2.98V maximum. - */ - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-3v"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-cpua"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-cpub"; -}; - -®_dcdc4 { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-gpu"; -}; - -®_dcdc5 { - regulator-always-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vcc-dram"; -}; - -®_dcdc6 { - regulator-always-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - regulator-name = "vdd-sys"; -}; - -®_dldo2 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "dp-pwr"; -}; - -®_dldo3 { - regulator-always-on; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-name = "ephy-io"; -}; - -®_dldo4 { - /* - * The PHY requires 20ms after all voltages are applied until core - * logic is ready and 30ms after the reset pin is de-asserted. - * Set a 100ms delay to account for PMIC ramp time and board traces. - */ - regulator-enable-ramp-delay = <100000>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "ephy"; -}; - -®_drivevbus { - regulator-name = "usb0-vbus"; - status = "okay"; -}; - -®_eldo1 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-name = "dp-bridge-1"; -}; - -®_eldo2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-name = "dp-bridge-2"; -}; - -®_fldo1 { - /* TODO should be handled by USB PHY */ - regulator-always-on; - regulator-min-microvolt = <1080000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd12-hsic"; -}; - -®_fldo2 { - /* - * Despite the embedded CPUs core not being used in any way, - * this must remain on or the system will hang. - */ - regulator-always-on; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-cpus"; -}; - -®_rtc_ldo { - regulator-name = "vcc-rtc"; -}; - -®_sw { - regulator-name = "vcc-wifi-io"; -}; - -&spdif { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; - uart-has-rtscts; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm4330-bt"; - clocks = <&ac100_rtc 1>; - clock-names = "lpo"; - vbat-supply = <®_dcdc1>; - vddio-supply = <®_sw>; - device-wakeup-gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */ - host-wakeup-gpios = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */ - shutdown-gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */ - }; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usb_power_supply { - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>; /* PH11 */ - usb0_vbus_power-supply = <&usb_power_supply>; - usb0_vbus-supply = <®_drivevbus>; - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun8i-a83t-tbs-a711.dts b/sys/gnu/dts/arm/sun8i-a83t-tbs-a711.dts deleted file mode 100644 index e8b3669e0e5..00000000000 --- a/sys/gnu/dts/arm/sun8i-a83t-tbs-a711.dts +++ /dev/null @@ -1,507 +0,0 @@ -/* - * Copyright (C) 2017 Touchless Biometric Systems AG - * Tomas Novotny - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun8i-a83t.dtsi" - -#include -#include -#include - -/ { - model = "TBS A711 Tablet"; - compatible = "tbs-biometrics,a711", "allwinner,sun8i-a83t"; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; - enable-gpios = <&pio 3 29 GPIO_ACTIVE_HIGH>; - - brightness-levels = <0 1 2 4 8 16 32 64 128 255>; - default-brightness-level = <9>; - }; - - panel { - compatible = "tbs,a711-panel", "panel-lvds"; - backlight = <&backlight>; - power-supply = <®_sw>; - - width-mm = <153>; - height-mm = <90>; - data-mapping = "vesa-24"; - - panel-timing { - /* 1024x600 @60Hz */ - clock-frequency = <52000000>; - hactive = <1024>; - vactive = <600>; - hsync-len = <20>; - hfront-porch = <180>; - hback-porch = <160>; - vfront-porch = <12>; - vback-porch = <23>; - vsync-len = <5>; - }; - - port { - panel_input: endpoint { - remote-endpoint = <&tcon0_out_lcd>; - }; - }; - }; - - reg_gps: reg-gps { - compatible = "regulator-fixed"; - regulator-name = "gps"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - reg_vbat: reg-vbat { - compatible = "regulator-fixed"; - regulator-name = "vbat"; - regulator-min-microvolt = <3700000>; - regulator-max-microvolt = <3700000>; - }; - - reg_vmain: reg-vmain { - compatible = "regulator-fixed"; - regulator-name = "vmain"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&r_pio 0 9 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <®_vbat>; - }; - - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 WL-PMU-EN */ - - /* - * This is actually Bluetooth's clock, but we have to - * hook it up somewheere - */ - clocks = <&ac100_rtc 1>; - clock-names = "ext_clock"; - }; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&cpu100 { - cpu-supply = <®_dcdc3>; -}; - -&de { - status = "okay"; -}; - -/* - * An USB-2 hub is connected here, which also means we don't need to - * enable the OHCI controller. - */ -&ehci0 { - status = "okay"; -}; - -/* - * There's a modem connected here that needs to be initialised before - * being able to be enumerated. - */ -&ehci1 { - status = "okay"; -}; - -&i2c0 { - clock-frequency = <400000>; - status = "okay"; - - touchscreen@38 { - compatible = "edt,edt-ft5x06"; - reg = <0x38>; - interrupt-parent = <&r_pio>; - interrupts = <0 7 IRQ_TYPE_EDGE_FALLING>; /* PL7 */ - reset-gpios = <&pio 3 5 GPIO_ACTIVE_LOW>; /* PD5 */ - vcc-supply = <®_ldo_io0>; - touchscreen-size-x = <1024>; - touchscreen-size-y = <600>; - }; -}; - -&i2c1 { - clock-frequency = <400000>; - status = "okay"; - - accelerometer@18 { - compatible = "bosch,bma250"; - reg = <0x18>; - interrupt-parent = <&pio>; - interrupts = <7 10 IRQ_TYPE_EDGE_RISING>; /* PH10 / EINT10 */ - }; -}; - -&mmc0 { - vmmc-supply = <®_dcdc1>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; - bus-width = <4>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&mmc1 { - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - vmmc-supply = <®_dldo1>; - vqmmc-supply = <®_dldo1>; - non-removable; - wakeup-source; - keep-power-in-suspend; - status = "okay"; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - interrupt-parent = <&r_pio>; - interrupts = <0 3 IRQ_TYPE_LEVEL_LOW>; /* PL3 WL_WAKE_UP */ - interrupt-names = "host-wake"; - }; -}; - -&mmc2 { - pinctrl-0 = <&mmc2_8bit_emmc_pins>; - pinctrl-names = "default"; - vmmc-supply = <®_dcdc1>; - vqmmc-supply = <®_dcdc1>; - bus-width = <8>; - non-removable; - cap-mmc-hw-reset; - status = "okay"; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm_pin>; - status = "okay"; -}; - -&r_lradc { - vref-supply = <®_aldo2>; - status = "okay"; - - button-210 { - label = "Volume Up"; - linux,code = ; - channel = <0>; - voltage = <210000>; - }; - - button-410 { - label = "Volume Down"; - linux,code = ; - channel = <0>; - voltage = <410000>; - }; -}; - -&r_rsb { - status = "okay"; - - axp81x: pmic@3a3 { - compatible = "x-powers,axp813"; - reg = <0x3a3>; - interrupt-parent = <&r_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - swin-supply = <®_dcdc1>; - x-powers,drive-vbus-en; - }; - - ac100: codec@e89 { - compatible = "x-powers,ac100"; - reg = <0xe89>; - - ac100_codec: codec { - compatible = "x-powers,ac100-codec"; - interrupt-parent = <&r_pio>; - interrupts = <0 12 IRQ_TYPE_LEVEL_LOW>; /* PL12 */ - #clock-cells = <0>; - clock-output-names = "4M_adda"; - }; - - ac100_rtc: rtc { - compatible = "x-powers,ac100-rtc"; - interrupt-parent = <&r_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - clocks = <&ac100_codec>; - #clock-cells = <1>; - clock-output-names = "cko1_rtc", - "cko2_rtc", - "cko3_rtc"; - }; - }; - -}; - -#include "axp81x.dtsi" - -&battery_power_supply { - status = "okay"; -}; - -®_aldo1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc-1.8"; -}; - -®_aldo2 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-name = "vdd-drampll"; -}; - -®_aldo3 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - regulator-name = "avcc"; -}; - -®_dcdc1 { - regulator-min-microvolt = <3100000>; - regulator-max-microvolt = <3100000>; - regulator-always-on; - regulator-name = "vcc-io"; -}; - -®_dcdc2 { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - regulator-name = "vdd-cpu-A"; -}; - -®_dcdc3 { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - regulator-name = "vdd-cpu-B"; -}; - -®_dcdc4 { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-gpu"; -}; - -®_dcdc5 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-name = "vcc-dram"; -}; - -®_dcdc6 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - regulator-always-on; - regulator-name = "vdd-sys"; -}; - -®_dldo1 { - regulator-min-microvolt = <3100000>; - regulator-max-microvolt = <3100000>; - regulator-name = "vcc-wifi-io"; -}; - -®_dldo2 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <4200000>; - regulator-name = "vcc-mipi"; -}; - -®_dldo3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vdd-csi"; -}; - -®_dldo4 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-name = "avdd-csi"; -}; - -®_drivevbus { - regulator-name = "usb0-vbus"; - status = "okay"; -}; - -®_eldo1 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1800000>; - regulator-name = "dvdd-csi-r"; -}; - -®_eldo2 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc-dsi"; -}; - -®_eldo3 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1800000>; - regulator-name = "dvdd-csi-f"; -}; - -®_fldo1 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-name = "vcc-hsic"; -}; - -®_fldo2 { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - regulator-name = "vdd-cpus"; -}; - -®_ldo_io0 { - regulator-min-microvolt = <3100000>; - regulator-max-microvolt = <3100000>; - regulator-name = "vcc-ctp"; - status = "okay"; -}; - -®_ldo_io1 { - regulator-min-microvolt = <3100000>; - regulator-max-microvolt = <3100000>; - regulator-name = "vcc-vb"; - status = "okay"; -}; - -®_sw { - regulator-min-microvolt = <3100000>; - regulator-max-microvolt = <3100000>; - regulator-name = "vcc-lcd"; -}; - -&tcon0 { - pinctrl-names = "default"; - pinctrl-0 = <&lcd_lvds_pins>; -}; - -&tcon0_out { - tcon0_out_lcd: endpoint { - remote-endpoint = <&panel_input>; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -/* There's the BT part of the AP6210 connected to that UART */ -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; - uart-has-rtscts; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm20702a1"; - clocks = <&ac100_rtc 1>; - clock-names = "lpo"; - vbat-supply = <®_vbat>; - vddio-supply = <®_dldo1>; - device-wakeup-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ - host-wakeup-gpios = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* PL5 */ - shutdown-gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */ - max-speed = <1500000>; - }; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pb_pins>; - status = "okay"; - - gnss { - compatible = "u-blox,neo-6m"; - - v-bckp-supply = <®_rtc_ldo>; - vcc-supply = <®_gps>; - current-speed = <9600>; - }; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 7 11 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH11 */ - usb0_vbus_power-supply = <&usb_power_supply>; - usb0_vbus-supply = <®_drivevbus>; - usb1_vbus-supply = <®_vmain>; - usb2_vbus-supply = <®_vmain>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun8i-a83t.dtsi b/sys/gnu/dts/arm/sun8i-a83t.dtsi deleted file mode 100644 index e7b9bef1be6..00000000000 --- a/sys/gnu/dts/arm/sun8i-a83t.dtsi +++ /dev/null @@ -1,1205 +0,0 @@ -/* - * Copyright 2015 Vishnu Patekar - * - * Vishnu Patekar - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include - -#include -#include -#include -#include -#include -#include -#include - -/ { - interrupt-parent = <&gic>; - #address-cells = <1>; - #size-cells = <1>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - clocks = <&ccu CLK_C0CPUX>; - operating-points-v2 = <&cpu0_opp_table>; - cci-control-port = <&cci_control0>; - enable-method = "allwinner,sun8i-a83t-smp"; - reg = <0>; - #cooling-cells = <2>; - }; - - cpu@1 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - clocks = <&ccu CLK_C0CPUX>; - operating-points-v2 = <&cpu0_opp_table>; - cci-control-port = <&cci_control0>; - enable-method = "allwinner,sun8i-a83t-smp"; - reg = <1>; - #cooling-cells = <2>; - }; - - cpu@2 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - clocks = <&ccu CLK_C0CPUX>; - operating-points-v2 = <&cpu0_opp_table>; - cci-control-port = <&cci_control0>; - enable-method = "allwinner,sun8i-a83t-smp"; - reg = <2>; - #cooling-cells = <2>; - }; - - cpu@3 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - clocks = <&ccu CLK_C0CPUX>; - operating-points-v2 = <&cpu0_opp_table>; - cci-control-port = <&cci_control0>; - enable-method = "allwinner,sun8i-a83t-smp"; - reg = <3>; - #cooling-cells = <2>; - }; - - cpu100: cpu@100 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - clocks = <&ccu CLK_C1CPUX>; - operating-points-v2 = <&cpu1_opp_table>; - cci-control-port = <&cci_control1>; - enable-method = "allwinner,sun8i-a83t-smp"; - reg = <0x100>; - #cooling-cells = <2>; - }; - - cpu@101 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - clocks = <&ccu CLK_C1CPUX>; - operating-points-v2 = <&cpu1_opp_table>; - cci-control-port = <&cci_control1>; - enable-method = "allwinner,sun8i-a83t-smp"; - reg = <0x101>; - #cooling-cells = <2>; - }; - - cpu@102 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - clocks = <&ccu CLK_C1CPUX>; - operating-points-v2 = <&cpu1_opp_table>; - cci-control-port = <&cci_control1>; - enable-method = "allwinner,sun8i-a83t-smp"; - reg = <0x102>; - #cooling-cells = <2>; - }; - - cpu@103 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - clocks = <&ccu CLK_C1CPUX>; - operating-points-v2 = <&cpu1_opp_table>; - cci-control-port = <&cci_control1>; - enable-method = "allwinner,sun8i-a83t-smp"; - reg = <0x103>; - #cooling-cells = <2>; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; - }; - - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - /* TODO: PRCM block has a mux for this. */ - osc24M: osc24M_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-accuracy = <50000>; - clock-output-names = "osc24M"; - }; - - /* - * This is called "internal OSC" in some places. - * It is an internal RC-based oscillator. - * TODO: Its controls are in the PRCM block. - */ - osc16M: osc16M_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <16000000>; - clock-output-names = "osc16M"; - }; - - osc16Md512: osc16Md512_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <512>; - clock-mult = <1>; - clocks = <&osc16M>; - clock-output-names = "osc16M-d512"; - }; - }; - - de: display-engine { - compatible = "allwinner,sun8i-a83t-display-engine"; - allwinner,pipelines = <&mixer0>, <&mixer1>; - status = "disabled"; - }; - - cpu0_opp_table: opp_table0 { - compatible = "operating-points-v2"; - opp-shared; - - opp-480000000 { - opp-hz = /bits/ 64 <480000000>; - opp-microvolt = <840000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - }; - - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <840000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - }; - - opp-720000000 { - opp-hz = /bits/ 64 <720000000>; - opp-microvolt = <840000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - }; - - opp-864000000 { - opp-hz = /bits/ 64 <864000000>; - opp-microvolt = <840000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - }; - - opp-912000000 { - opp-hz = /bits/ 64 <912000000>; - opp-microvolt = <840000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - }; - - opp-1008000000 { - opp-hz = /bits/ 64 <1008000000>; - opp-microvolt = <840000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - }; - - opp-1128000000 { - opp-hz = /bits/ 64 <1128000000>; - opp-microvolt = <840000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - }; - - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <840000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - }; - }; - - cpu1_opp_table: opp_table1 { - compatible = "operating-points-v2"; - opp-shared; - - opp-480000000 { - opp-hz = /bits/ 64 <480000000>; - opp-microvolt = <840000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - }; - - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <840000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - }; - - opp-720000000 { - opp-hz = /bits/ 64 <720000000>; - opp-microvolt = <840000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - }; - - opp-864000000 { - opp-hz = /bits/ 64 <864000000>; - opp-microvolt = <840000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - }; - - opp-912000000 { - opp-hz = /bits/ 64 <912000000>; - opp-microvolt = <840000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - }; - - opp-1008000000 { - opp-hz = /bits/ 64 <1008000000>; - opp-microvolt = <840000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - }; - - opp-1128000000 { - opp-hz = /bits/ 64 <1128000000>; - opp-microvolt = <840000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - }; - - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <840000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - }; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - display_clocks: clock@1000000 { - compatible = "allwinner,sun8i-a83t-de2-clk"; - reg = <0x01000000 0x100000>; - clocks = <&ccu CLK_BUS_DE>, - <&ccu CLK_PLL_DE>; - clock-names = "bus", - "mod"; - resets = <&ccu RST_BUS_DE>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - mixer0: mixer@1100000 { - compatible = "allwinner,sun8i-a83t-de2-mixer-0"; - reg = <0x01100000 0x100000>; - clocks = <&display_clocks CLK_BUS_MIXER0>, - <&display_clocks CLK_MIXER0>; - clock-names = "bus", - "mod"; - resets = <&display_clocks RST_MIXER0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - mixer0_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - mixer0_out_tcon0: endpoint@0 { - reg = <0>; - remote-endpoint = <&tcon0_in_mixer0>; - }; - - mixer0_out_tcon1: endpoint@1 { - reg = <1>; - remote-endpoint = <&tcon1_in_mixer0>; - }; - }; - }; - }; - - mixer1: mixer@1200000 { - compatible = "allwinner,sun8i-a83t-de2-mixer-1"; - reg = <0x01200000 0x100000>; - clocks = <&display_clocks CLK_BUS_MIXER1>, - <&display_clocks CLK_MIXER1>; - clock-names = "bus", - "mod"; - resets = <&display_clocks RST_WB>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - mixer1_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - mixer1_out_tcon0: endpoint@0 { - reg = <0>; - remote-endpoint = <&tcon0_in_mixer1>; - }; - - mixer1_out_tcon1: endpoint@1 { - reg = <1>; - remote-endpoint = <&tcon1_in_mixer1>; - }; - }; - }; - }; - - cpucfg@1700000 { - compatible = "allwinner,sun8i-a83t-cpucfg"; - reg = <0x01700000 0x400>; - }; - - cci@1790000 { - compatible = "arm,cci-400"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x01790000 0x10000>; - ranges = <0x0 0x01790000 0x10000>; - - cci_control0: slave-if@4000 { - compatible = "arm,cci-400-ctrl-if"; - interface-type = "ace"; - reg = <0x4000 0x1000>; - }; - - cci_control1: slave-if@5000 { - compatible = "arm,cci-400-ctrl-if"; - interface-type = "ace"; - reg = <0x5000 0x1000>; - }; - - pmu@9000 { - compatible = "arm,cci-400-pmu,r1"; - reg = <0x9000 0x5000>; - interrupts = , - , - , - , - , - , - , - ; - }; - }; - - syscon: syscon@1c00000 { - compatible = "allwinner,sun8i-a83t-system-controller", - "syscon"; - reg = <0x01c00000 0x1000>; - }; - - dma: dma-controller@1c02000 { - compatible = "allwinner,sun8i-a83t-dma"; - reg = <0x01c02000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_BUS_DMA>; - resets = <&ccu RST_BUS_DMA>; - #dma-cells = <1>; - }; - - tcon0: lcd-controller@1c0c000 { - compatible = "allwinner,sun8i-a83t-tcon-lcd"; - reg = <0x01c0c000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>; - clock-names = "ahb", "tcon-ch0"; - clock-output-names = "tcon-pixel-clock"; - #clock-cells = <0>; - resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>; - reset-names = "lcd", "lvds"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - tcon0_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - tcon0_in_mixer0: endpoint@0 { - reg = <0>; - remote-endpoint = <&mixer0_out_tcon0>; - }; - - tcon0_in_mixer1: endpoint@1 { - reg = <1>; - remote-endpoint = <&mixer1_out_tcon0>; - }; - }; - - tcon0_out: port@1 { - reg = <1>; - }; - }; - }; - - tcon1: lcd-controller@1c0d000 { - compatible = "allwinner,sun8i-a83t-tcon-tv"; - reg = <0x01c0d000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>; - clock-names = "ahb", "tcon-ch1"; - resets = <&ccu RST_BUS_TCON1>; - reset-names = "lcd"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - tcon1_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - tcon1_in_mixer0: endpoint@0 { - reg = <0>; - remote-endpoint = <&mixer0_out_tcon1>; - }; - - tcon1_in_mixer1: endpoint@1 { - reg = <1>; - remote-endpoint = <&mixer1_out_tcon1>; - }; - }; - - tcon1_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - tcon1_out_hdmi: endpoint@1 { - reg = <1>; - remote-endpoint = <&hdmi_in_tcon1>; - }; - }; - }; - }; - - mmc0: mmc@1c0f000 { - compatible = "allwinner,sun8i-a83t-mmc", - "allwinner,sun7i-a20-mmc"; - reg = <0x01c0f000 0x1000>; - clocks = <&ccu CLK_BUS_MMC0>, - <&ccu CLK_MMC0>, - <&ccu CLK_MMC0_OUTPUT>, - <&ccu CLK_MMC0_SAMPLE>; - clock-names = "ahb", - "mmc", - "output", - "sample"; - resets = <&ccu RST_BUS_MMC0>; - reset-names = "ahb"; - interrupts = ; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc1: mmc@1c10000 { - compatible = "allwinner,sun8i-a83t-mmc", - "allwinner,sun7i-a20-mmc"; - reg = <0x01c10000 0x1000>; - clocks = <&ccu CLK_BUS_MMC1>, - <&ccu CLK_MMC1>, - <&ccu CLK_MMC1_OUTPUT>, - <&ccu CLK_MMC1_SAMPLE>; - clock-names = "ahb", - "mmc", - "output", - "sample"; - resets = <&ccu RST_BUS_MMC1>; - reset-names = "ahb"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc2: mmc@1c11000 { - compatible = "allwinner,sun8i-a83t-emmc"; - reg = <0x01c11000 0x1000>; - clocks = <&ccu CLK_BUS_MMC2>, - <&ccu CLK_MMC2>, - <&ccu CLK_MMC2_OUTPUT>, - <&ccu CLK_MMC2_SAMPLE>; - clock-names = "ahb", - "mmc", - "output", - "sample"; - resets = <&ccu RST_BUS_MMC2>; - reset-names = "ahb"; - interrupts = ; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - sid: eeprom@1c14000 { - compatible = "allwinner,sun8i-a83t-sid"; - reg = <0x1c14000 0x400>; - #address-cells = <1>; - #size-cells = <1>; - - ths_calibration: thermal-sensor-calibration@34 { - reg = <0x34 8>; - }; - }; - - crypto: crypto@1c15000 { - compatible = "allwinner,sun8i-a83t-crypto"; - reg = <0x01c15000 0x1000>; - interrupts = ; - resets = <&ccu RST_BUS_SS>; - clocks = <&ccu CLK_BUS_SS>, <&ccu CLK_SS>; - clock-names = "bus", "mod"; - }; - - usb_otg: usb@1c19000 { - compatible = "allwinner,sun8i-a83t-musb", - "allwinner,sun8i-a33-musb"; - reg = <0x01c19000 0x0400>; - clocks = <&ccu CLK_BUS_OTG>; - resets = <&ccu RST_BUS_OTG>; - interrupts = ; - interrupt-names = "mc"; - phys = <&usbphy 0>; - phy-names = "usb"; - extcon = <&usbphy 0>; - dr_mode = "otg"; - status = "disabled"; - }; - - usbphy: phy@1c19400 { - compatible = "allwinner,sun8i-a83t-usb-phy"; - reg = <0x01c19400 0x10>, - <0x01c1a800 0x14>, - <0x01c1b800 0x14>; - reg-names = "phy_ctrl", - "pmu1", - "pmu2"; - clocks = <&ccu CLK_USB_PHY0>, - <&ccu CLK_USB_PHY1>, - <&ccu CLK_USB_HSIC>, - <&ccu CLK_USB_HSIC_12M>; - clock-names = "usb0_phy", - "usb1_phy", - "usb2_phy", - "usb2_hsic_12M"; - resets = <&ccu RST_USB_PHY0>, - <&ccu RST_USB_PHY1>, - <&ccu RST_USB_HSIC>; - reset-names = "usb0_reset", - "usb1_reset", - "usb2_reset"; - status = "disabled"; - #phy-cells = <1>; - }; - - ehci0: usb@1c1a000 { - compatible = "allwinner,sun8i-a83t-ehci", - "generic-ehci"; - reg = <0x01c1a000 0x100>; - interrupts = ; - clocks = <&ccu CLK_BUS_EHCI0>; - resets = <&ccu RST_BUS_EHCI0>; - phys = <&usbphy 1>; - phy-names = "usb"; - status = "disabled"; - }; - - ohci0: usb@1c1a400 { - compatible = "allwinner,sun8i-a83t-ohci", - "generic-ohci"; - reg = <0x01c1a400 0x100>; - interrupts = ; - clocks = <&ccu CLK_BUS_OHCI0>, <&ccu CLK_USB_OHCI0>; - resets = <&ccu RST_BUS_OHCI0>; - phys = <&usbphy 1>; - phy-names = "usb"; - status = "disabled"; - }; - - ehci1: usb@1c1b000 { - compatible = "allwinner,sun8i-a83t-ehci", - "generic-ehci"; - reg = <0x01c1b000 0x100>; - interrupts = ; - clocks = <&ccu CLK_BUS_EHCI1>; - resets = <&ccu RST_BUS_EHCI1>; - phys = <&usbphy 2>; - phy-names = "usb"; - status = "disabled"; - }; - - ccu: clock@1c20000 { - compatible = "allwinner,sun8i-a83t-ccu"; - reg = <0x01c20000 0x400>; - clocks = <&osc24M>, <&osc16Md512>; - clock-names = "hosc", "losc"; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - pio: pinctrl@1c20800 { - compatible = "allwinner,sun8i-a83t-pinctrl"; - interrupts = , - , - ; - reg = <0x01c20800 0x400>; - clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc16Md512>; - clock-names = "apb", "hosc", "losc"; - gpio-controller; - interrupt-controller; - #interrupt-cells = <3>; - #gpio-cells = <3>; - - /omit-if-no-ref/ - csi_8bit_parallel_pins: csi-8bit-parallel-pins { - pins = "PE0", "PE2", "PE3", "PE6", "PE7", - "PE8", "PE9", "PE10", "PE11", - "PE12", "PE13"; - function = "csi"; - }; - - /omit-if-no-ref/ - csi_mclk_pin: csi-mclk-pin { - pins = "PE1"; - function = "csi"; - }; - - emac_rgmii_pins: emac-rgmii-pins { - pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", - "PD11", "PD12", "PD13", "PD14", "PD18", - "PD19", "PD21", "PD22", "PD23"; - function = "gmac"; - /* - * data lines in RGMII mode use DDR mode - * and need a higher signal drive strength - */ - drive-strength = <40>; - }; - - hdmi_pins: hdmi-pins { - pins = "PH6", "PH7", "PH8"; - function = "hdmi"; - }; - - i2c0_pins: i2c0-pins { - pins = "PH0", "PH1"; - function = "i2c0"; - }; - - i2c1_pins: i2c1-pins { - pins = "PH2", "PH3"; - function = "i2c1"; - }; - - /omit-if-no-ref/ - i2c2_pe_pins: i2c2-pe-pins { - pins = "PE14", "PE15"; - function = "i2c2"; - }; - - i2c2_ph_pins: i2c2-ph-pins { - pins = "PH4", "PH5"; - function = "i2c2"; - }; - - i2s1_pins: i2s1-pins { - /* I2S1 does not have external MCLK pin */ - pins = "PG10", "PG11", "PG12", "PG13"; - function = "i2s1"; - }; - - lcd_lvds_pins: lcd-lvds-pins { - pins = "PD18", "PD19", "PD20", "PD21", "PD22", - "PD23", "PD24", "PD25", "PD26", "PD27"; - function = "lvds0"; - }; - - mmc0_pins: mmc0-pins { - pins = "PF0", "PF1", "PF2", - "PF3", "PF4", "PF5"; - function = "mmc0"; - drive-strength = <30>; - bias-pull-up; - }; - - mmc1_pins: mmc1-pins { - pins = "PG0", "PG1", "PG2", - "PG3", "PG4", "PG5"; - function = "mmc1"; - drive-strength = <30>; - bias-pull-up; - }; - - mmc2_8bit_emmc_pins: mmc2-8bit-emmc-pins { - pins = "PC5", "PC6", "PC8", "PC9", - "PC10", "PC11", "PC12", "PC13", - "PC14", "PC15", "PC16"; - function = "mmc2"; - drive-strength = <30>; - bias-pull-up; - }; - - pwm_pin: pwm-pin { - pins = "PD28"; - function = "pwm"; - }; - - spdif_tx_pin: spdif-tx-pin { - pins = "PE18"; - function = "spdif"; - }; - - uart0_pb_pins: uart0-pb-pins { - pins = "PB9", "PB10"; - function = "uart0"; - }; - - uart0_pf_pins: uart0-pf-pins { - pins = "PF2", "PF4"; - function = "uart0"; - }; - - uart1_pins: uart1-pins { - pins = "PG6", "PG7"; - function = "uart1"; - }; - - uart1_rts_cts_pins: uart1-rts-cts-pins { - pins = "PG8", "PG9"; - function = "uart1"; - }; - - /omit-if-no-ref/ - uart2_pb_pins: uart2-pb-pins { - pins = "PB0", "PB1"; - function = "uart2"; - }; - }; - - timer@1c20c00 { - compatible = "allwinner,sun8i-a23-timer"; - reg = <0x01c20c00 0xa0>; - interrupts = , - ; - clocks = <&osc24M>; - }; - - watchdog@1c20ca0 { - compatible = "allwinner,sun6i-a31-wdt"; - reg = <0x01c20ca0 0x20>; - interrupts = ; - clocks = <&osc24M>; - }; - - spdif: spdif@1c21000 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun8i-a83t-spdif", - "allwinner,sun8i-h3-spdif"; - reg = <0x01c21000 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; - resets = <&ccu RST_BUS_SPDIF>; - clock-names = "apb", "spdif"; - dmas = <&dma 2>; - dma-names = "tx"; - pinctrl-names = "default"; - pinctrl-0 = <&spdif_tx_pin>; - status = "disabled"; - }; - - i2s0: i2s@1c22000 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun8i-a83t-i2s"; - reg = <0x01c22000 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>; - clock-names = "apb", "mod"; - dmas = <&dma 3>, <&dma 3>; - resets = <&ccu RST_BUS_I2S0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2s1: i2s@1c22400 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun8i-a83t-i2s"; - reg = <0x01c22400 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>; - clock-names = "apb", "mod"; - dmas = <&dma 4>, <&dma 4>; - resets = <&ccu RST_BUS_I2S1>; - dma-names = "rx", "tx"; - pinctrl-names = "default"; - pinctrl-0 = <&i2s1_pins>; - status = "disabled"; - }; - - i2s2: i2s@1c22800 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun8i-a83t-i2s"; - reg = <0x01c22800 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>; - clock-names = "apb", "mod"; - dmas = <&dma 27>; - resets = <&ccu RST_BUS_I2S2>; - dma-names = "tx"; - status = "disabled"; - }; - - pwm: pwm@1c21400 { - compatible = "allwinner,sun8i-a83t-pwm", - "allwinner,sun8i-h3-pwm"; - reg = <0x01c21400 0x400>; - clocks = <&osc24M>; - #pwm-cells = <3>; - status = "disabled"; - }; - - uart0: serial@1c28000 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART0>; - resets = <&ccu RST_BUS_UART0>; - status = "disabled"; - }; - - uart1: serial@1c28400 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28400 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART1>; - resets = <&ccu RST_BUS_UART1>; - status = "disabled"; - }; - - uart2: serial@1c28800 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28800 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART2>; - resets = <&ccu RST_BUS_UART2>; - status = "disabled"; - }; - - uart3: serial@1c28c00 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28c00 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART3>; - resets = <&ccu RST_BUS_UART3>; - status = "disabled"; - }; - - uart4: serial@1c29000 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c29000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART4>; - resets = <&ccu RST_BUS_UART4>; - status = "disabled"; - }; - - i2c0: i2c@1c2ac00 { - compatible = "allwinner,sun8i-a83t-i2c", - "allwinner,sun6i-a31-i2c"; - reg = <0x01c2ac00 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_I2C0>; - resets = <&ccu RST_BUS_I2C0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c1: i2c@1c2b000 { - compatible = "allwinner,sun8i-a83t-i2c", - "allwinner,sun6i-a31-i2c"; - reg = <0x01c2b000 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_I2C1>; - resets = <&ccu RST_BUS_I2C1>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c2: i2c@1c2b400 { - compatible = "allwinner,sun8i-a83t-i2c", - "allwinner,sun6i-a31-i2c"; - reg = <0x01c2b400 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_I2C2>; - resets = <&ccu RST_BUS_I2C2>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - emac: ethernet@1c30000 { - compatible = "allwinner,sun8i-a83t-emac"; - syscon = <&syscon>; - reg = <0x01c30000 0x104>; - interrupts = ; - interrupt-names = "macirq"; - clocks = <&ccu CLK_BUS_EMAC>; - clock-names = "stmmaceth"; - resets = <&ccu RST_BUS_EMAC>; - reset-names = "stmmaceth"; - status = "disabled"; - - mdio: mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - gic: interrupt-controller@1c81000 { - compatible = "arm,gic-400"; - reg = <0x01c81000 0x1000>, - <0x01c82000 0x2000>, - <0x01c84000 0x2000>, - <0x01c86000 0x2000>; - interrupt-controller; - #interrupt-cells = <3>; - interrupts = ; - }; - - csi: camera@1cb0000 { - compatible = "allwinner,sun8i-a83t-csi"; - reg = <0x01cb0000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_BUS_CSI>, - <&ccu CLK_CSI_SCLK>, - <&ccu CLK_DRAM_CSI>; - clock-names = "bus", "mod", "ram"; - resets = <&ccu RST_BUS_CSI>; - status = "disabled"; - - csi_in: port { - }; - }; - - hdmi: hdmi@1ee0000 { - compatible = "allwinner,sun8i-a83t-dw-hdmi"; - reg = <0x01ee0000 0x10000>; - reg-io-width = <1>; - interrupts = ; - clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>, - <&ccu CLK_HDMI>; - clock-names = "iahb", "isfr", "tmds"; - resets = <&ccu RST_BUS_HDMI1>; - reset-names = "ctrl"; - phys = <&hdmi_phy>; - phy-names = "phy"; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_pins>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - hdmi_in: port@0 { - reg = <0>; - - hdmi_in_tcon1: endpoint { - remote-endpoint = <&tcon1_out_hdmi>; - }; - }; - - hdmi_out: port@1 { - reg = <1>; - }; - }; - }; - - hdmi_phy: hdmi-phy@1ef0000 { - compatible = "allwinner,sun8i-a83t-hdmi-phy"; - reg = <0x01ef0000 0x10000>; - clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>; - clock-names = "bus", "mod"; - resets = <&ccu RST_BUS_HDMI0>; - reset-names = "phy"; - #phy-cells = <0>; - }; - - r_intc: interrupt-controller@1f00c00 { - compatible = "allwinner,sun8i-a83t-r-intc", - "allwinner,sun6i-a31-r-intc"; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x01f00c00 0x400>; - interrupts = ; - }; - - r_ccu: clock@1f01400 { - compatible = "allwinner,sun8i-a83t-r-ccu"; - reg = <0x01f01400 0x400>; - clocks = <&osc24M>, <&osc16Md512>, <&osc16M>, - <&ccu CLK_PLL_PERIPH>; - clock-names = "hosc", "losc", "iosc", "pll-periph"; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - r_cpucfg@1f01c00 { - compatible = "allwinner,sun8i-a83t-r-cpucfg"; - reg = <0x1f01c00 0x400>; - }; - - r_cir: ir@1f02000 { - compatible = "allwinner,sun8i-a83t-ir", - "allwinner,sun6i-a31-ir"; - clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>; - clock-names = "apb", "ir"; - resets = <&r_ccu RST_APB0_IR>; - interrupts = ; - reg = <0x01f02000 0x400>; - pinctrl-names = "default"; - pinctrl-0 = <&r_cir_pin>; - status = "disabled"; - }; - - r_lradc: lradc@1f03c00 { - compatible = "allwinner,sun8i-a83t-r-lradc"; - reg = <0x01f03c00 0x100>; - interrupts = ; - status = "disabled"; - }; - - r_pio: pinctrl@1f02c00 { - compatible = "allwinner,sun8i-a83t-r-pinctrl"; - reg = <0x01f02c00 0x400>; - interrupts = ; - clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, - <&osc16Md512>; - clock-names = "apb", "hosc", "losc"; - gpio-controller; - #gpio-cells = <3>; - interrupt-controller; - #interrupt-cells = <3>; - - r_cir_pin: r-cir-pin { - pins = "PL12"; - function = "s_cir_rx"; - }; - - r_rsb_pins: r-rsb-pins { - pins = "PL0", "PL1"; - function = "s_rsb"; - drive-strength = <20>; - bias-pull-up; - }; - }; - - r_rsb: rsb@1f03400 { - compatible = "allwinner,sun8i-a83t-rsb", - "allwinner,sun8i-a23-rsb"; - reg = <0x01f03400 0x400>; - interrupts = ; - clocks = <&r_ccu CLK_APB0_RSB>; - clock-frequency = <3000000>; - resets = <&r_ccu RST_APB0_RSB>; - pinctrl-names = "default"; - pinctrl-0 = <&r_rsb_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - ths: thermal-sensor@1f04000 { - compatible = "allwinner,sun8i-a83t-ths"; - reg = <0x01f04000 0x100>; - interrupts = ; - nvmem-cells = <&ths_calibration>; - nvmem-cell-names = "calibration"; - #thermal-sensor-cells = <1>; - }; - }; - - thermal-zones { - cpu0_thermal: cpu0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&ths 0>; - }; - - cpu1_thermal: cpu1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&ths 1>; - }; - - gpu_thermal: gpu-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&ths 2>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/sun8i-h2-plus-bananapi-m2-zero.dts b/sys/gnu/dts/arm/sun8i-h2-plus-bananapi-m2-zero.dts deleted file mode 100644 index d277d043031..00000000000 --- a/sys/gnu/dts/arm/sun8i-h2-plus-bananapi-m2-zero.dts +++ /dev/null @@ -1,153 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2017 Icenowy Zheng - * - * Based on sun8i-h3-bananapi-m2-plus.dts, which is: - * Copyright (C) 2016 Chen-Yu Tsai - */ - -/dts-v1/; -#include "sun8i-h3.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include - -/ { - model = "Banana Pi BPI-M2-Zero"; - compatible = "sinovoip,bpi-m2-zero", "allwinner,sun8i-h2-plus"; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - pwr_led { - label = "bananapi-m2-zero:red:pwr"; - gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */ - default-state = "on"; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - - sw4 { - label = "power"; - linux,code = ; - gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; - }; - }; - - reg_vdd_cpux: vdd-cpux-regulator { - compatible = "regulator-gpio"; - regulator-name = "vdd-cpux"; - regulator-type = "voltage"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1300000>; - regulator-ramp-delay = <50>; /* 4ms */ - - gpios = <&r_pio 0 1 GPIO_ACTIVE_HIGH>; /* PL1 */ - enable-active-high; - gpios-states = <0x1>; - states = <1100000 0>, <1300000 1>; - }; - - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ - clocks = <&rtc 1>; - clock-names = "ext_clock"; - }; -}; - -&cpu0 { - cpu-supply = <®_vdd_cpux>; -}; - -&ehci0 { - status = "okay"; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - /* - * On the production batch of this board the card detect GPIO is - * high active (card inserted), although on the early samples it's - * low active. - */ - cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ - status = "okay"; -}; - -&mmc1 { - vmmc-supply = <®_vcc3v3>; - vqmmc-supply = <®_vcc3v3>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - interrupt-parent = <&pio>; - interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 / EINT10 */ - interrupt-names = "host-wake"; - }; -}; - -&ohci0 { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pa_pins>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; - uart-has-rtscts; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - clocks = <&rtc 1>; - clock-names = "lpo"; - vbat-supply = <®_vcc3v3>; - vddio-supply = <®_vcc3v3>; - device-wakeup-gpios = <&pio 6 13 GPIO_ACTIVE_HIGH>; /* PG13 */ - host-wakeup-gpios = <&pio 6 11 GPIO_ACTIVE_HIGH>; /* PG11 */ - shutdown-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ - }; - -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ - /* - * There're two micro-USB connectors, one is power-only and another is - * OTG. The Vbus of these two connectors are connected together, so - * the external USB device will be powered just by the power input - * from the power-only USB port. - */ - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun8i-h2-plus-libretech-all-h3-cc.dts b/sys/gnu/dts/arm/sun8i-h2-plus-libretech-all-h3-cc.dts deleted file mode 100644 index 4db0d4bb65e..00000000000 --- a/sys/gnu/dts/arm/sun8i-h2-plus-libretech-all-h3-cc.dts +++ /dev/null @@ -1,13 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2018 Chen-Yu Tsai - */ - -/dts-v1/; -#include "sun8i-h3.dtsi" -#include "sunxi-libretech-all-h3-cc.dtsi" - -/ { - model = "Libre Computer Board ALL-H3-CC H2+"; - compatible = "libretech,all-h3-cc-h2-plus", "allwinner,sun8i-h2-plus"; -}; diff --git a/sys/gnu/dts/arm/sun8i-h2-plus-orangepi-r1.dts b/sys/gnu/dts/arm/sun8i-h2-plus-orangepi-r1.dts deleted file mode 100644 index 3356f4210d4..00000000000 --- a/sys/gnu/dts/arm/sun8i-h2-plus-orangepi-r1.dts +++ /dev/null @@ -1,99 +0,0 @@ -/* - * Copyright (C) 2017 Icenowy Zheng - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/* Orange Pi R1 is based on Orange Pi Zero design */ -#include "sun8i-h2-plus-orangepi-zero.dts" - -/ { - model = "Xunlong Orange Pi R1"; - compatible = "xunlong,orangepi-r1", "allwinner,sun8i-h2-plus"; - - /delete-node/ reg_vcc_wifi; - - /* - * Ths pin of this regulator is the same with the Wi-Fi extra - * regulator on the original Zero. However it's used for USB - * Ethernet rather than the Wi-Fi now. - */ - reg_vcc_usb_eth: reg-vcc-usb-ethernet { - compatible = "regulator-fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-usb-ethernet"; - enable-active-high; - gpio = <&pio 0 20 GPIO_ACTIVE_HIGH>; - }; - - aliases { - ethernet1 = &rtl8189etv; - }; -}; - -&spi0 { - status = "okay"; - - flash@0 { - compatible = "mxicy,mx25l12805d", "jedec,spi-nor"; - }; -}; - -&ohci1 { - /* - * RTL8152B USB-Ethernet adapter is connected to USB1, - * and it's a USB 2.0 device. So the OHCI1 controller - * can be left disabled. - */ - status = "disabled"; -}; - -&mmc1 { - vmmc-supply = <®_vcc3v3>; - vqmmc-supply = <®_vcc3v3>; - - rtl8189etv: sdio_wifi@1 { - reg = <1>; - }; -}; - -&usbphy { - usb1_vbus-supply = <®_vcc_usb_eth>; -}; diff --git a/sys/gnu/dts/arm/sun8i-h2-plus-orangepi-zero.dts b/sys/gnu/dts/arm/sun8i-h2-plus-orangepi-zero.dts deleted file mode 100644 index f19ed981da9..00000000000 --- a/sys/gnu/dts/arm/sun8i-h2-plus-orangepi-zero.dts +++ /dev/null @@ -1,209 +0,0 @@ -/* - * Copyright (C) 2016 Icenowy Zheng - * - * Based on sun8i-h3-orangepi-one.dts, which is: - * Copyright (C) 2016 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun8i-h3.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include - -/ { - model = "Xunlong Orange Pi Zero"; - compatible = "xunlong,orangepi-zero", "allwinner,sun8i-h2-plus"; - - aliases { - serial0 = &uart0; - /* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */ - ethernet0 = &emac; - ethernet1 = &xr819; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - pwr_led { - label = "orangepi:green:pwr"; - gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - status_led { - label = "orangepi:red:status"; - gpios = <&pio 0 17 GPIO_ACTIVE_HIGH>; - }; - }; - - reg_vcc_wifi: reg_vcc_wifi { - compatible = "regulator-fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi"; - enable-active-high; - gpio = <&pio 0 20 GPIO_ACTIVE_HIGH>; - }; - - reg_vdd_cpux: vdd-cpux-regulator { - compatible = "regulator-gpio"; - regulator-name = "vdd-cpux"; - regulator-type = "voltage"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1300000>; - regulator-ramp-delay = <50>; /* 4ms */ - - gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ - enable-active-high; - gpios-states = <1>; - states = <1100000 0>, <1300000 1>; - }; - - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; - post-power-on-delay-ms = <200>; - }; -}; - -&cpu0 { - cpu-supply = <®_vdd_cpux>; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&emac { - phy-handle = <&int_mii_phy>; - phy-mode = "mii"; - allwinner,leds-active-low; - status = "okay"; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ - status = "okay"; -}; - -&mmc1 { - vmmc-supply = <®_vcc_wifi>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; - - /* - * Explicitly define the sdio device, so that we can add an ethernet - * alias for it (which e.g. makes u-boot set a mac-address). - */ - xr819: sdio_wifi@1 { - reg = <1>; - }; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&spi0 { - /* Disable SPI NOR by default: it optional on Orange Pi Zero boards */ - status = "disabled"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "mxicy,mx25l1606e", "winbond,w25q128"; - reg = <0>; - spi-max-frequency = <40000000>; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pa_pins>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; - status = "disabled"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; - status = "disabled"; -}; - -&usb_otg { - dr_mode = "peripheral"; - status = "okay"; -}; - -&usbphy { - /* - * USB Type-A port VBUS is always on. However, MicroUSB VBUS can only - * power up the board; when it's used as OTG port, this VBUS is - * always off even if the board is powered via GPIO pins. - */ - status = "okay"; - usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ -}; diff --git a/sys/gnu/dts/arm/sun8i-h3-bananapi-m2-plus-v1.2.dts b/sys/gnu/dts/arm/sun8i-h3-bananapi-m2-plus-v1.2.dts deleted file mode 100644 index fc4a8c3d084..00000000000 --- a/sys/gnu/dts/arm/sun8i-h3-bananapi-m2-plus-v1.2.dts +++ /dev/null @@ -1,13 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2018 Chen-Yu Tsai - */ - -/dts-v1/; -#include "sun8i-h3.dtsi" -#include "sunxi-bananapi-m2-plus-v1.2.dtsi" - -/ { - model = "Banana Pi BPI-M2-Plus v1.2 H3"; - compatible = "bananapi,bpi-m2-plus-v1.2", "allwinner,sun8i-h3"; -}; diff --git a/sys/gnu/dts/arm/sun8i-h3-bananapi-m2-plus.dts b/sys/gnu/dts/arm/sun8i-h3-bananapi-m2-plus.dts deleted file mode 100644 index 195a75da13f..00000000000 --- a/sys/gnu/dts/arm/sun8i-h3-bananapi-m2-plus.dts +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Copyright (C) 2016 Chen-Yu Tsai - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun8i-h3.dtsi" -#include "sunxi-bananapi-m2-plus.dtsi" - -/ { - model = "Banana Pi BPI-M2-Plus H3"; - compatible = "sinovoip,bpi-m2-plus", "allwinner,sun8i-h3"; -}; diff --git a/sys/gnu/dts/arm/sun8i-h3-beelink-x2.dts b/sys/gnu/dts/arm/sun8i-h3-beelink-x2.dts deleted file mode 100644 index 45a24441ff1..00000000000 --- a/sys/gnu/dts/arm/sun8i-h3-beelink-x2.dts +++ /dev/null @@ -1,221 +0,0 @@ -/* - * Copyright (C) 2017 Marcus Cooper - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun8i-h3.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include - -/ { - model = "Beelink X2"; - compatible = "roofull,beelink-x2", "allwinner,sun8i-h3"; - - aliases { - serial0 = &uart0; - ethernet0 = &emac; - ethernet1 = &sdiowifi; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - blue { - label = "beelink-x2:blue:pwr"; - gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */ - default-state = "on"; - }; - - red { - label = "beelink-x2:red:standby"; - gpios = <&pio 0 15 GPIO_ACTIVE_HIGH>; /* PA15 */ - }; - }; - - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ - clocks = <&rtc 1>; - clock-names = "ext_clock"; - }; - - sound_spdif { - compatible = "simple-audio-card"; - simple-audio-card,name = "On-board SPDIF"; - - simple-audio-card,cpu { - sound-dai = <&spdif>; - }; - - simple-audio-card,codec { - sound-dai = <&spdif_out>; - }; - }; - - spdif_out: spdif-out { - #sound-dai-cells = <0>; - compatible = "linux,spdif-dit"; - }; -}; - -&de { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&emac { - phy-handle = <&int_mii_phy>; - phy-mode = "mii"; - allwinner,leds-active-low; - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&ir { - linux,rc-map-name = "rc-tanix-tx3mini"; - pinctrl-names = "default"; - pinctrl-0 = <&r_ir_rx_pin>; - status = "okay"; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ - status = "okay"; -}; - -&mmc1 { - vmmc-supply = <®_vcc3v3>; - vqmmc-supply = <®_vcc3v3>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; - - /* - * Explicitly define the sdio device, so that we can add an ethernet - * alias for it (which e.g. makes u-boot set a mac-address). - */ - sdiowifi: sdio_wifi@1 { - reg = <1>; - }; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_8bit_pins>; - vmmc-supply = <®_vcc3v3>; - bus-width = <8>; - non-removable; - cap-mmc-hw-reset; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -®_usb0_vbus { - gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */ - status = "okay"; -}; - -&spdif { - pinctrl-names = "default"; - pinctrl-0 = <&spdif_tx_pin>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pa_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - /* USB VBUS is always on except for the OTG port */ - status = "okay"; - usb0_id_det-gpios = <&pio 0 7 GPIO_ACTIVE_HIGH>; /* PA07 */ - usb0_vbus-supply = <®_usb0_vbus>; -}; diff --git a/sys/gnu/dts/arm/sun8i-h3-emlid-neutis-n5h3-devboard.dts b/sys/gnu/dts/arm/sun8i-h3-emlid-neutis-n5h3-devboard.dts deleted file mode 100644 index 02fbe00cde9..00000000000 --- a/sys/gnu/dts/arm/sun8i-h3-emlid-neutis-n5h3-devboard.dts +++ /dev/null @@ -1,72 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * DTS for Emlid Neutis N5 Dev board. - * - * Copyright (C) 2019 Georgii Staroselskii - */ - -/dts-v1/; - -#include "sun8i-h3-emlid-neutis-n5h3.dtsi" - -/ { - model = "Emlid Neutis N5H3 Developer board"; - compatible = "emlid,neutis-n5h3-devboard", - "emlid,neutis-n5h3", - "allwinner,sun8i-h3"; - - vdd_cpux: gpio-regulator { - compatible = "regulator-gpio"; - regulator-name = "vdd-cpux"; - regulator-type = "voltage"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1300000>; - regulator-ramp-delay = <50>; /* 4ms */ - gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ - gpios-states = <0x1>; - states = <1100000 0x0>, <1300000 0x1>; - }; - - connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - -}; - -&cpu0 { - cpu-supply = <&vdd_cpux>; -}; - -&codec { - status = "okay"; -}; - -&emac { - phy-handle = <&int_mii_phy>; - phy-mode = "mii"; - allwinner,leds-active-low; - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&i2c1 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun8i-h3-emlid-neutis-n5h3.dtsi b/sys/gnu/dts/arm/sun8i-h3-emlid-neutis-n5h3.dtsi deleted file mode 100644 index eedd5da5dc2..00000000000 --- a/sys/gnu/dts/arm/sun8i-h3-emlid-neutis-n5h3.dtsi +++ /dev/null @@ -1,11 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * DTSI for Emlid Neutis N5 SoM. - * - * Copyright (C) 2019 Georgii Staroselskii - */ - -/dts-v1/; - -#include "sun8i-h3.dtsi" -#include diff --git a/sys/gnu/dts/arm/sun8i-h3-libretech-all-h3-cc.dts b/sys/gnu/dts/arm/sun8i-h3-libretech-all-h3-cc.dts deleted file mode 100644 index a8b2f0f1c11..00000000000 --- a/sys/gnu/dts/arm/sun8i-h3-libretech-all-h3-cc.dts +++ /dev/null @@ -1,14 +0,0 @@ -/* - * Copyright (C) 2017 Chen-Yu Tsai - * - * SPDX-License-Identifier: (GPL-2.0+ OR MIT) - */ - -/dts-v1/; -#include "sun8i-h3.dtsi" -#include "sunxi-libretech-all-h3-cc.dtsi" - -/ { - model = "Libre Computer Board ALL-H3-CC H3"; - compatible = "libretech,all-h3-cc-h3", "allwinner,sun8i-h3"; -}; diff --git a/sys/gnu/dts/arm/sun8i-h3-mapleboard-mp130.dts b/sys/gnu/dts/arm/sun8i-h3-mapleboard-mp130.dts deleted file mode 100644 index ff0a7a952e0..00000000000 --- a/sys/gnu/dts/arm/sun8i-h3-mapleboard-mp130.dts +++ /dev/null @@ -1,152 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2017 Centrum Embedded Systems, Jia-Bin Huang - * Copyright (C) 2018 Jonathan McDowell - */ - -/dts-v1/; -#include "sun8i-h3.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include - -/ { - model = "MapleBoard MP130"; - compatible = "mapleboard,mp130", "allwinner,sun8i-h3"; - - aliases { - ethernet0 = &emac; - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - pwr_led { - label = "mp130:orange:pwr"; - gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - status_led { - label = "mp130:orange:status"; - gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>; - }; - }; - - r_gpio_keys { - compatible = "gpio-keys"; - - power { - label = "power"; - linux,code = ; - gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; /* PL3 */ - }; - - user { - label = "user"; - linux,code = ; - gpios = <&r_pio 0 4 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&codec { - allwinner,audio-routing = - "Line Out", "LINEOUT", - "LINEIN", "Line In"; - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&ehci2 { - status = "okay"; -}; - -&ehci3 { - status = "okay"; -}; - -&emac { - phy-handle = <&int_mii_phy>; - phy-mode = "mii"; - allwinner,leds-active-low; - status = "okay"; -}; - -&ir { - pinctrl-names = "default"; - pinctrl-0 = <&r_ir_rx_pin>; - status = "okay"; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ - status = "okay"; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_8bit_pins>; - vmmc-supply = <®_vcc3v3>; - bus-width = <8>; - non-removable; - cap-mmc-hw-reset; - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&ohci2 { - status = "okay"; -}; - -&ohci3 { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pa_pins>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; - status = "disabled"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; - status = "disabled"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; - status = "disabled"; -}; - -&usb_otg { - dr_mode = "peripheral"; - status = "okay"; -}; - -&usbphy { - /* USB VBUS is always on */ - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun8i-h3-nanopi-duo2.dts b/sys/gnu/dts/arm/sun8i-h3-nanopi-duo2.dts deleted file mode 100644 index 6b149271ef1..00000000000 --- a/sys/gnu/dts/arm/sun8i-h3-nanopi-duo2.dts +++ /dev/null @@ -1,173 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2019 Karl Palsson - */ - -/dts-v1/; -#include "sun8i-h3.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include - -/ { - model = "FriendlyARM NanoPi Duo2"; - compatible = "friendlyarm,nanopi-duo2", "allwinner,sun8i-h3"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - pwr { - label = "nanopi:red:pwr"; - gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */ - default-state = "on"; - }; - - status { - label = "nanopi:green:status"; - gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>; /* PA10 */ - }; - }; - - r_gpio_keys { - compatible = "gpio-keys"; - - k1 { - label = "k1"; - linux,code = ; - gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; /* PL3 */ - }; - }; - - reg_vdd_cpux: vdd-cpux-regulator { - compatible = "regulator-gpio"; - regulator-name = "vdd-cpux"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - regulator-ramp-delay = <50>; /* 4ms */ - - enable-active-high; - enable-gpio = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */ - gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ - gpios-states = <0x1>; - states = <1100000 0>, <1300000 1>; - }; - - reg_vcc_dram: vcc-dram { - compatible = "regulator-fixed"; - regulator-name = "vcc-dram"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&r_pio 0 9 GPIO_ACTIVE_HIGH>; /* PL9 */ - vin-supply = <®_vcc5v0>; - }; - - reg_vdd_sys: vdd-sys { - compatible = "regulator-fixed"; - regulator-name = "vdd-sys"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */ - vin-supply = <®_vcc5v0>; - }; - - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ - clocks = <&rtc 1>; - clock-names = "ext_clock"; - }; - -}; - -&cpu0 { - cpu-supply = <®_vdd_cpux>; -}; - -&ehci0 { - status = "okay"; -}; - -&mmc0 { - bus-width = <4>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ - status = "okay"; - vmmc-supply = <®_vcc3v3>; -}; - -&mmc1 { - vmmc-supply = <®_vcc3v3>; - vqmmc-supply = <®_vcc3v3>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; - - sdio_wifi: sdio_wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - interrupt-parent = <&pio>; - interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 / EINT10 */ - interrupt-names = "host-wake"; - }; -}; - -&ohci0 { - status = "okay"; -}; - -®_usb0_vbus { - gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */ - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pa_pins>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>, <&uart2_rts_cts_pins>; - uart-has-rtscts; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - clocks = <&rtc 1>; - clock-names = "lpo"; - vbat-supply = <®_vcc3v3>; - vddio-supply = <®_vcc3v3>; - device-wakeup-gpios = <&pio 0 8 GPIO_ACTIVE_HIGH>; /* PA8 */ - host-wakeup-gpios = <&pio 0 7 GPIO_ACTIVE_HIGH>; /* PA7 */ - shutdown-gpios = <&pio 6 13 GPIO_ACTIVE_HIGH>; /* PG13 */ - }; -}; - -&usb_otg { - status = "okay"; - dr_mode = "otg"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ - usb0_vbus-supply = <®_usb0_vbus>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun8i-h3-nanopi-m1-plus.dts b/sys/gnu/dts/arm/sun8i-h3-nanopi-m1-plus.dts deleted file mode 100644 index 4ba533b0340..00000000000 --- a/sys/gnu/dts/arm/sun8i-h3-nanopi-m1-plus.dts +++ /dev/null @@ -1,166 +0,0 @@ -/* - * Copyright (C) 2017 Jagan Teki - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "sun8i-h3-nanopi.dtsi" - -/ { - model = "FriendlyArm NanoPi M1 Plus"; - compatible = "friendlyarm,nanopi-m1-plus", "allwinner,sun8i-h3"; - - aliases { - serial1 = &uart3; - ethernet0 = &emac; - ethernet1 = &sdio_wifi; - }; - - reg_gmac_3v3: gmac-3v3 { - compatible = "regulator-fixed"; - regulator-name = "gmac-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <100000>; - enable-active-high; - gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; - }; - - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ - }; - - connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; -}; - -&de { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&ehci2 { - status = "okay"; -}; - -&emac { - pinctrl-names = "default"; - pinctrl-0 = <&emac_rgmii_pins>; - phy-supply = <®_gmac_3v3>; - phy-handle = <&ext_rgmii_phy>; - phy-mode = "rgmii"; - - status = "okay"; -}; - -&external_mdio { - ext_rgmii_phy: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <7>; - }; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&ir { - pinctrl-names = "default"; - pinctrl-0 = <&r_ir_rx_pin>; - status = "okay"; -}; - -&mmc1 { - vmmc-supply = <®_vcc3v3>; - vqmmc-supply = <®_vcc3v3>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; - - sdio_wifi: sdio_wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - interrupt-parent = <&pio>; - interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 / EINT10 */ - interrupt-names = "host-wake"; - }; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_8bit_pins>; - vmmc-supply = <®_vcc3v3>; - vqmmc-supply = <®_vcc3v3>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&ohci2 { - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>, <&uart3_rts_cts_pins>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun8i-h3-nanopi-m1.dts b/sys/gnu/dts/arm/sun8i-h3-nanopi-m1.dts deleted file mode 100644 index 69243dcb30a..00000000000 --- a/sys/gnu/dts/arm/sun8i-h3-nanopi-m1.dts +++ /dev/null @@ -1,106 +0,0 @@ -/* - * Copyright (C) 2016 Milo Kim - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "sun8i-h3-nanopi.dtsi" - -/ { - model = "FriendlyArm NanoPi M1"; - compatible = "friendlyarm,nanopi-m1", "allwinner,sun8i-h3"; - - aliases { - ethernet0 = &emac; - }; - - connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; -}; - -&de { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&ehci2 { - status = "okay"; -}; - -&emac { - phy-handle = <&int_mii_phy>; - phy-mode = "mii"; - allwinner,leds-active-low; - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&ir { - pinctrl-names = "default"; - pinctrl-0 = <&r_ir_rx_pin>; - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&ohci2 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun8i-h3-nanopi-neo-air.dts b/sys/gnu/dts/arm/sun8i-h3-nanopi-neo-air.dts deleted file mode 100644 index 07867a0d569..00000000000 --- a/sys/gnu/dts/arm/sun8i-h3-nanopi-neo-air.dts +++ /dev/null @@ -1,115 +0,0 @@ -/* - * Copyright (C) 2017 Jelle van der Waa - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun8i-h3.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include - -/ { - model = "FriendlyARM NanoPi NEO Air"; - compatible = "friendlyarm,nanopi-neo-air", "allwinner,sun8i-h3"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - pwr { - label = "nanopi:green:pwr"; - gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */ - default-state = "on"; - }; - - status { - label = "nanopi:blue:status"; - gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>; /* PA10 */ - }; - }; - - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ - status = "okay"; -}; - -&mmc1 { - vmmc-supply = <®_vcc3v3>; - vqmmc-supply = <®_vcc3v3>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; - - brcmf: bcrmf@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - interrupt-parent = <&pio>; - interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 / EINT10 */ - interrupt-names = "host-wake"; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pa_pins>; - status = "okay"; -}; - -&usbphy { - /* USB VBUS is always on */ - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun8i-h3-nanopi-neo.dts b/sys/gnu/dts/arm/sun8i-h3-nanopi-neo.dts deleted file mode 100644 index 9f33f6fae59..00000000000 --- a/sys/gnu/dts/arm/sun8i-h3-nanopi-neo.dts +++ /dev/null @@ -1,72 +0,0 @@ -/* - * Copyright (C) 2016 James Pettigrew - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "sun8i-h3-nanopi.dtsi" - -/ { - model = "FriendlyARM NanoPi NEO"; - compatible = "friendlyarm,nanopi-neo", "allwinner,sun8i-h3"; -}; - -&ehci0 { - status = "okay"; -}; - -&emac { - phy-handle = <&int_mii_phy>; - phy-mode = "mii"; - allwinner,leds-active-low; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&usb_otg { - status = "okay"; - dr_mode = "peripheral"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ -}; diff --git a/sys/gnu/dts/arm/sun8i-h3-nanopi.dtsi b/sys/gnu/dts/arm/sun8i-h3-nanopi.dtsi deleted file mode 100644 index 4df29a65316..00000000000 --- a/sys/gnu/dts/arm/sun8i-h3-nanopi.dtsi +++ /dev/null @@ -1,111 +0,0 @@ -/* - * Copyright (C) 2016 James Pettigrew - * Copyright (C) 2016 Milo Kim - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun8i-h3.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include - -/ { - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - status { - label = "nanopi:blue:status"; - gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - - pwr { - label = "nanopi:green:pwr"; - gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; - - r_gpio_keys { - compatible = "gpio-keys"; - input-name = "k1"; - - k1 { - label = "k1"; - linux,code = ; - gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&ehci3 { - status = "okay"; -}; - -&mmc0 { - bus-width = <4>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; - status = "okay"; - vmmc-supply = <®_vcc3v3>; -}; - -&ohci3 { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pa_pins>; - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun8i-h3-orangepi-2.dts b/sys/gnu/dts/arm/sun8i-h3-orangepi-2.dts deleted file mode 100644 index 597c425d08e..00000000000 --- a/sys/gnu/dts/arm/sun8i-h3-orangepi-2.dts +++ /dev/null @@ -1,208 +0,0 @@ -/* - * Copyright (C) 2016 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun8i-h3.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include - -/ { - model = "Xunlong Orange Pi 2"; - compatible = "xunlong,orangepi-2", "allwinner,sun8i-h3"; - - aliases { - serial0 = &uart0; - /* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */ - ethernet0 = &emac; - ethernet1 = &rtl8189; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - status_led { - label = "orangepi:red:status"; - gpios = <&pio 0 15 GPIO_ACTIVE_HIGH>; - }; - - pwr_led { - label = "orangepi:green:pwr"; - gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; - - r_gpio_keys { - compatible = "gpio-keys"; - - sw2 { - label = "sw2"; - linux,code = ; - gpios = <&r_pio 0 4 GPIO_ACTIVE_LOW>; - }; - - sw4 { - label = "sw4"; - linux,code = ; - gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; - }; - }; - - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 WIFI_EN */ - }; -}; - -&codec { - allwinner,pa-gpios = <&pio 0 16 GPIO_ACTIVE_HIGH>; /* PA16 */ - allwinner,audio-routing = - "Speaker", "LINEOUT", - "MIC1", "Mic", - "Mic", "MBIAS"; - status = "okay"; -}; - -&de { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&emac { - phy-handle = <&int_mii_phy>; - phy-mode = "mii"; - allwinner,leds-active-low; - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&ir { - pinctrl-names = "default"; - pinctrl-0 = <&r_ir_rx_pin>; - status = "okay"; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ - status = "okay"; -}; - -&mmc1 { - vmmc-supply = <®_vcc3v3>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; - - /* - * Explicitly define the sdio device, so that we can add an ethernet - * alias for it (which e.g. makes u-boot set a mac-address). - */ - rtl8189: sdio_wifi@1 { - reg = <1>; - }; -}; - -®_usb1_vbus { - gpio = <&pio 6 13 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pa_pins>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; - status = "disabled"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; - status = "disabled"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; - status = "disabled"; -}; - -&usbphy { - usb1_vbus-supply = <®_usb1_vbus>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun8i-h3-orangepi-lite.dts b/sys/gnu/dts/arm/sun8i-h3-orangepi-lite.dts deleted file mode 100644 index 6f9c97add54..00000000000 --- a/sys/gnu/dts/arm/sun8i-h3-orangepi-lite.dts +++ /dev/null @@ -1,168 +0,0 @@ -/* - * Copyright (C) 2016 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun8i-h3.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include - -/ { - model = "Xunlong Orange Pi Lite"; - compatible = "xunlong,orangepi-lite", "allwinner,sun8i-h3"; - - aliases { - /* The H3 emac is not used so the wifi is ethernet0 */ - ethernet0 = &rtl8189ftv; - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - pwr_led { - label = "orangepi:green:pwr"; - gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - status_led { - label = "orangepi:red:status"; - gpios = <&pio 0 15 GPIO_ACTIVE_HIGH>; - }; - }; - - r_gpio_keys { - compatible = "gpio-keys"; - - sw4 { - label = "sw4"; - linux,code = ; - gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&de { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&ehci2 { - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&ir { - pinctrl-names = "default"; - pinctrl-0 = <&r_ir_rx_pin>; - status = "okay"; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ - status = "okay"; -}; - -&mmc1 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - non-removable; - status = "okay"; - - /* - * Explicitly define the sdio device, so that we can add an ethernet - * alias for it (which e.g. makes u-boot set a mac-address). - */ - rtl8189ftv: sdio_wifi@1 { - reg = <1>; - }; -}; - -&ohci1 { - status = "okay"; -}; - -&ohci2 { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pa_pins>; - status = "okay"; -}; - -&usbphy { - /* USB VBUS is always on */ - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun8i-h3-orangepi-one.dts b/sys/gnu/dts/arm/sun8i-h3-orangepi-one.dts deleted file mode 100644 index 4759ba3f298..00000000000 --- a/sys/gnu/dts/arm/sun8i-h3-orangepi-one.dts +++ /dev/null @@ -1,203 +0,0 @@ -/* - * Copyright (C) 2016 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun8i-h3.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include - -/ { - model = "Xunlong Orange Pi One"; - compatible = "xunlong,orangepi-one", "allwinner,sun8i-h3"; - - aliases { - ethernet0 = &emac; - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - pwr_led { - label = "orangepi:green:pwr"; - gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - status_led { - label = "orangepi:red:status"; - gpios = <&pio 0 15 GPIO_ACTIVE_HIGH>; - }; - }; - - r_gpio_keys { - compatible = "gpio-keys"; - - sw4 { - label = "sw4"; - linux,code = ; - gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; - }; - }; - - reg_vdd_cpux: vdd-cpux-regulator { - compatible = "regulator-gpio"; - regulator-name = "vdd-cpux"; - regulator-type = "voltage"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1300000>; - regulator-ramp-delay = <50>; /* 4ms */ - - gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ - enable-active-high; - gpios-states = <0x1>; - states = <1100000 0>, <1300000 1>; - }; -}; - -&cpu0 { - cpu-supply = <®_vdd_cpux>; -}; - -&de { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&emac { - phy-handle = <&int_mii_phy>; - phy-mode = "mii"; - allwinner,leds-active-low; - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -®_usb0_vbus { - gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */ - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pa_pins>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; - status = "disabled"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; - status = "disabled"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; - status = "disabled"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - /* USB Type-A port's VBUS is always on */ - usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ - usb0_vbus-supply = <®_usb0_vbus>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun8i-h3-orangepi-pc-plus.dts b/sys/gnu/dts/arm/sun8i-h3-orangepi-pc-plus.dts deleted file mode 100644 index 71fb7320893..00000000000 --- a/sys/gnu/dts/arm/sun8i-h3-orangepi-pc-plus.dts +++ /dev/null @@ -1,91 +0,0 @@ -/* - * Copyright (C) 2016 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/* The Orange Pi PC Plus is an extended version of the regular PC */ -#include "sun8i-h3-orangepi-pc.dts" - -/ { - model = "Xunlong Orange Pi PC Plus"; - compatible = "xunlong,orangepi-pc-plus", "allwinner,sun8i-h3"; - - aliases { - /* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */ - ethernet1 = &rtl8189ftv; - }; -}; - -&emac { - /* LEDs changed to active high on the plus */ - /delete-property/ allwinner,leds-active-low; -}; - -&mmc1 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - non-removable; - status = "okay"; - - /* - * Explicitly define the sdio device, so that we can add an ethernet - * alias for it (which e.g. makes u-boot set a mac-address). - */ - rtl8189ftv: sdio_wifi@1 { - reg = <1>; - }; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_8bit_pins>; - vmmc-supply = <®_vcc3v3>; - bus-width = <8>; - non-removable; - cap-mmc-hw-reset; - status = "okay"; -}; - -&mmc2_8bit_pins { - /* Increase drive strength for DDR modes */ - drive-strength = <40>; - /* eMMC is missing pull-ups */ - bias-pull-up; -}; diff --git a/sys/gnu/dts/arm/sun8i-h3-orangepi-pc.dts b/sys/gnu/dts/arm/sun8i-h3-orangepi-pc.dts deleted file mode 100644 index 5aff8ecc66c..00000000000 --- a/sys/gnu/dts/arm/sun8i-h3-orangepi-pc.dts +++ /dev/null @@ -1,241 +0,0 @@ -/* - * Copyright (C) 2015 Chen-Yu Tsai - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun8i-h3.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include - -/ { - model = "Xunlong Orange Pi PC"; - compatible = "xunlong,orangepi-pc", "allwinner,sun8i-h3"; - - aliases { - ethernet0 = &emac; - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - pwr_led { - label = "orangepi:green:pwr"; - gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - status_led { - label = "orangepi:red:status"; - gpios = <&pio 0 15 GPIO_ACTIVE_HIGH>; - }; - }; - - r_gpio_keys { - compatible = "gpio-keys"; - - sw4 { - label = "sw4"; - linux,code = ; - gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&codec { - allwinner,audio-routing = - "Line Out", "LINEOUT", - "MIC1", "Mic", - "Mic", "MBIAS"; - status = "okay"; -}; - -&de { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <®_vdd_cpux>; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&ehci2 { - status = "okay"; -}; - -&ehci3 { - status = "okay"; -}; - -&emac { - phy-handle = <&int_mii_phy>; - phy-mode = "mii"; - allwinner,leds-active-low; - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&ir { - pinctrl-names = "default"; - pinctrl-0 = <&r_ir_rx_pin>; - status = "okay"; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&ohci2 { - status = "okay"; -}; - -&ohci3 { - status = "okay"; -}; - -&r_i2c { - status = "okay"; - - reg_vdd_cpux: regulator@65 { - compatible = "silergy,sy8106a"; - reg = <0x65>; - regulator-name = "vdd-cpux"; - silergy,fixed-microvolt = <1200000>; - /* - * The datasheet uses 1.1V as the minimum value of VDD-CPUX, - * however both the Armbian DVFS table and the official one - * have operating points with voltage under 1.1V, and both - * DVFS table are known to work properly at the lowest - * operating point. - * - * Use 1.0V as the minimum voltage instead. - */ - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - regulator-always-on; - }; -}; - -®_usb0_vbus { - gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */ - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pa_pins>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; - status = "disabled"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; - status = "disabled"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; - status = "disabled"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ - usb0_vbus-supply = <®_usb0_vbus>; - /* VBUS on USB host ports are always on */ - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun8i-h3-orangepi-plus.dts b/sys/gnu/dts/arm/sun8i-h3-orangepi-plus.dts deleted file mode 100644 index 97f497854e0..00000000000 --- a/sys/gnu/dts/arm/sun8i-h3-orangepi-plus.dts +++ /dev/null @@ -1,135 +0,0 @@ -/* - * Copyright (C) 2015 Jens Kuske - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/* The Orange Pi Plus is an extended version of the Orange Pi 2 */ -#include "sun8i-h3-orangepi-2.dts" - -/ { - model = "Xunlong Orange Pi Plus / Plus 2"; - compatible = "xunlong,orangepi-plus", "allwinner,sun8i-h3"; - - aliases { - ethernet0 = &emac; - }; - - reg_gmac_3v3: gmac-3v3 { - compatible = "regulator-fixed"; - regulator-name = "gmac-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <100000>; - enable-active-high; - gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; - }; - - reg_usb3_vbus: usb3-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb3-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - enable-active-high; - gpio = <&pio 6 11 GPIO_ACTIVE_HIGH>; - }; -}; - -&cpu0 { - cpu-supply = <®_vdd_cpux>; -}; - -&ehci3 { - status = "okay"; -}; - -&emac { - pinctrl-names = "default"; - pinctrl-0 = <&emac_rgmii_pins>; - phy-supply = <®_gmac_3v3>; - phy-handle = <&ext_rgmii_phy>; - phy-mode = "rgmii"; - - status = "okay"; -}; - -&external_mdio { - ext_rgmii_phy: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - }; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_8bit_pins>; - vmmc-supply = <®_vcc3v3>; - bus-width = <8>; - non-removable; - cap-mmc-hw-reset; - status = "okay"; -}; - -&mmc2_8bit_pins { - /* Increase drive strength for DDR modes */ - drive-strength = <40>; - /* eMMC is missing pull-ups */ - bias-pull-up; -}; - -&r_i2c { - status = "okay"; - - reg_vdd_cpux: regulator@65 { - compatible = "silergy,sy8106a"; - reg = <0x65>; - regulator-name = "vdd-cpux"; - silergy,fixed-microvolt = <1200000>; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-ramp-delay = <200>; - regulator-boot-on; - regulator-always-on; - }; -}; - -&usbphy { - usb3_vbus-supply = <®_usb3_vbus>; -}; diff --git a/sys/gnu/dts/arm/sun8i-h3-orangepi-plus2e.dts b/sys/gnu/dts/arm/sun8i-h3-orangepi-plus2e.dts deleted file mode 100644 index 6dbf7b2e0c1..00000000000 --- a/sys/gnu/dts/arm/sun8i-h3-orangepi-plus2e.dts +++ /dev/null @@ -1,79 +0,0 @@ -/* - * Copyright (C) 2016 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/* - * The Orange Pi Plus 2E is an extended version of the Orange Pi PC Plus, - * with 2G RAM and an external gbit ethernet phy. - */ - -#include "sun8i-h3-orangepi-pc-plus.dts" - -/ { - model = "Xunlong Orange Pi Plus 2E"; - compatible = "xunlong,orangepi-plus2e", "allwinner,sun8i-h3"; - - reg_gmac_3v3: gmac-3v3 { - compatible = "regulator-fixed"; - regulator-name = "gmac-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <100000>; - enable-active-high; - gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */ - }; -}; - -&emac { - pinctrl-names = "default"; - pinctrl-0 = <&emac_rgmii_pins>; - phy-supply = <®_gmac_3v3>; - phy-handle = <&ext_rgmii_phy>; - phy-mode = "rgmii"; - status = "okay"; -}; - -&external_mdio { - ext_rgmii_phy: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; -}; diff --git a/sys/gnu/dts/arm/sun8i-h3-orangepi-zero-plus2.dts b/sys/gnu/dts/arm/sun8i-h3-orangepi-zero-plus2.dts deleted file mode 100644 index b8f46e2802f..00000000000 --- a/sys/gnu/dts/arm/sun8i-h3-orangepi-zero-plus2.dts +++ /dev/null @@ -1,139 +0,0 @@ -/* - * Copyright (C) 2017 Jagan Teki - * Copyright (C) 2018 Diego Rondini - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include "sun8i-h3.dtsi" - -#include - -/ { - model = "OrangePi Zero Plus2 H3"; - compatible = "xunlong,orangepi-zero-plus2-h3", "allwinner,sun8i-h3"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - reg_vcc3v3: vcc3v3 { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&pio 0 9 GPIO_ACTIVE_LOW>; /* PA9 */ - post-power-on-delay-ms = <200>; - }; -}; - -&de { - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&mmc1 { - vmmc-supply = <®_vcc3v3>; - vqmmc-supply = <®_vcc3v3>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - interrupt-parent = <&r_pio>; - interrupts = <0 7 IRQ_TYPE_LEVEL_LOW>; /* PL7 */ - interrupt-names = "host-wake"; - }; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_8bit_pins>; - vmmc-supply = <®_vcc3v3>; - bus-width = <8>; - non-removable; - cap-mmc-hw-reset; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pa_pins>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun8i-h3-rervision-dvk.dts b/sys/gnu/dts/arm/sun8i-h3-rervision-dvk.dts deleted file mode 100644 index 4738f3a9efe..00000000000 --- a/sys/gnu/dts/arm/sun8i-h3-rervision-dvk.dts +++ /dev/null @@ -1,114 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2019 Bootlin - * Author: Paul Kocialkowski - */ - -/dts-v1/; -#include "sun8i-h3.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include - -/ { - model = "RerVision H3-DVK"; - compatible = "rervision,h3-dvk", "allwinner,sun8i-h3"; - - aliases { - ethernet0 = &emac; - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; -}; - -&de { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&ehci2 { - status = "okay"; -}; - -&ehci3 { - status = "okay"; -}; - -&emac { - phy-handle = <&int_mii_phy>; - phy-mode = "mii"; - allwinner,leds-active-low; - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&mmc0 { - bus-width = <4>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ - status = "okay"; - vmmc-supply = <®_vcc3v3>; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_8bit_pins>; - vmmc-supply = <®_vcc3v3>; - bus-width = <8>; - non-removable; - cap-mmc-hw-reset; - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&ohci2 { - status = "okay"; -}; - -&ohci3 { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pa_pins>; - status = "okay"; -}; - -&usb_otg { - status = "okay"; - dr_mode = "peripheral"; -}; - -&usbphy { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun8i-h3.dtsi b/sys/gnu/dts/arm/sun8i-h3.dtsi deleted file mode 100644 index 20217e2ca4d..00000000000 --- a/sys/gnu/dts/arm/sun8i-h3.dtsi +++ /dev/null @@ -1,288 +0,0 @@ -/* - * Copyright (C) 2015 Jens Kuske - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "sunxi-h3-h5.dtsi" - -/ { - cpu0_opp_table: opp_table0 { - compatible = "operating-points-v2"; - opp-shared; - - opp-648000000 { - opp-hz = /bits/ 64 <648000000>; - opp-microvolt = <1040000 1040000 1300000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - }; - - opp-816000000 { - opp-hz = /bits/ 64 <816000000>; - opp-microvolt = <1100000 1100000 1300000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - }; - - opp-1008000000 { - opp-hz = /bits/ 64 <1008000000>; - opp-microvolt = <1200000 1200000 1300000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <0>; - clocks = <&ccu CLK_CPUX>; - clock-names = "cpu"; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; - }; - - cpu1: cpu@1 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <1>; - clocks = <&ccu CLK_CPUX>; - clock-names = "cpu"; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; - }; - - cpu2: cpu@2 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <2>; - clocks = <&ccu CLK_CPUX>; - clock-names = "cpu"; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; - }; - - cpu3: cpu@3 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <3>; - clocks = <&ccu CLK_CPUX>; - clock-names = "cpu"; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; - }; - }; - - pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts = , - , - , - ; - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; - }; - - soc { - deinterlace: deinterlace@1400000 { - compatible = "allwinner,sun8i-h3-deinterlace"; - reg = <0x01400000 0x20000>; - clocks = <&ccu CLK_BUS_DEINTERLACE>, - <&ccu CLK_DEINTERLACE>, - <&ccu CLK_DRAM_DEINTERLACE>; - clock-names = "bus", "mod", "ram"; - resets = <&ccu RST_BUS_DEINTERLACE>; - interrupts = ; - interconnects = <&mbus 9>; - interconnect-names = "dma-mem"; - }; - - syscon: system-control@1c00000 { - compatible = "allwinner,sun8i-h3-system-control"; - reg = <0x01c00000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - sram_c: sram@1d00000 { - compatible = "mmio-sram"; - reg = <0x01d00000 0x80000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x01d00000 0x80000>; - - ve_sram: sram-section@0 { - compatible = "allwinner,sun8i-h3-sram-c1", - "allwinner,sun4i-a10-sram-c1"; - reg = <0x000000 0x80000>; - }; - }; - }; - - video-codec@1c0e000 { - compatible = "allwinner,sun8i-h3-video-engine"; - reg = <0x01c0e000 0x1000>; - clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, - <&ccu CLK_DRAM_VE>; - clock-names = "ahb", "mod", "ram"; - resets = <&ccu RST_BUS_VE>; - interrupts = ; - allwinner,sram = <&ve_sram 1>; - }; - - crypto: crypto@1c15000 { - compatible = "allwinner,sun8i-h3-crypto"; - reg = <0x01c15000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>; - clock-names = "bus", "mod"; - resets = <&ccu RST_BUS_CE>; - }; - - mali: gpu@1c40000 { - compatible = "allwinner,sun8i-h3-mali", "arm,mali-400"; - reg = <0x01c40000 0x10000>; - interrupts = , - , - , - , - , - , - ; - interrupt-names = "gp", - "gpmmu", - "pp0", - "ppmmu0", - "pp1", - "ppmmu1", - "pmu"; - clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>; - clock-names = "bus", "core"; - resets = <&ccu RST_BUS_GPU>; - - assigned-clocks = <&ccu CLK_GPU>; - assigned-clock-rates = <384000000>; - }; - - ths: thermal-sensor@1c25000 { - compatible = "allwinner,sun8i-h3-ths"; - reg = <0x01c25000 0x400>; - interrupts = ; - resets = <&ccu RST_BUS_THS>; - clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>; - clock-names = "bus", "mod"; - nvmem-cells = <&ths_calibration>; - nvmem-cell-names = "calibration"; - #thermal-sensor-cells = <0>; - }; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&ths 0>; - }; - }; -}; - -&ccu { - compatible = "allwinner,sun8i-h3-ccu"; -}; - -&display_clocks { - compatible = "allwinner,sun8i-h3-de2-clk"; -}; - -&mmc0 { - compatible = "allwinner,sun7i-a20-mmc"; - clocks = <&ccu CLK_BUS_MMC0>, - <&ccu CLK_MMC0>, - <&ccu CLK_MMC0_OUTPUT>, - <&ccu CLK_MMC0_SAMPLE>; - clock-names = "ahb", - "mmc", - "output", - "sample"; -}; - -&mmc1 { - compatible = "allwinner,sun7i-a20-mmc"; - clocks = <&ccu CLK_BUS_MMC1>, - <&ccu CLK_MMC1>, - <&ccu CLK_MMC1_OUTPUT>, - <&ccu CLK_MMC1_SAMPLE>; - clock-names = "ahb", - "mmc", - "output", - "sample"; -}; - -&mmc2 { - compatible = "allwinner,sun7i-a20-mmc"; - clocks = <&ccu CLK_BUS_MMC2>, - <&ccu CLK_MMC2>, - <&ccu CLK_MMC2_OUTPUT>, - <&ccu CLK_MMC2_SAMPLE>; - clock-names = "ahb", - "mmc", - "output", - "sample"; -}; - -&pio { - compatible = "allwinner,sun8i-h3-pinctrl"; -}; - -&rtc { - compatible = "allwinner,sun8i-h3-rtc"; -}; - -&sid { - compatible = "allwinner,sun8i-h3-sid"; -}; diff --git a/sys/gnu/dts/arm/sun8i-q8-common.dtsi b/sys/gnu/dts/arm/sun8i-q8-common.dtsi deleted file mode 100644 index 3d9a1524e17..00000000000 --- a/sys/gnu/dts/arm/sun8i-q8-common.dtsi +++ /dev/null @@ -1,118 +0,0 @@ -/* - * Copyright 2015 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -#include "sunxi-reference-design-tablet.dtsi" -#include "sun8i-reference-design-tablet.dtsi" - -/ { - aliases { - serial0 = &r_uart; - /* Make u-boot set mac-address for wifi without an eeprom */ - ethernet0 = &sdio_wifi; - }; - - panel: panel { - /* Tablet dts should provide panel compatible */ - backlight = <&backlight>; - enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */ - power-supply = <®_dc1sw>; - - port { - panel_input: endpoint { - remote-endpoint = <&tcon0_out_lcd>; - }; - }; - }; - - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-simple"; - /* - * Q8 boards use various PL# pins as wifi-en. On other boards - * these may be connected to a wifi module output pin. To avoid - * short-circuits we configure these as inputs with pull-ups via - * pinctrl, instead of listing them as active-low reset-gpios. - */ - pinctrl-names = "default"; - pinctrl-0 = <&wifi_pwrseq_pin_q8>; - /* The esp8089 needs 200 ms after driving wifi-en high */ - post-power-on-delay-ms = <200>; - }; -}; - -&de { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pg_pins>; - vmmc-supply = <®_dldo1>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; - - sdio_wifi: sdio_wifi@1 { - reg = <1>; - }; -}; - -&r_pio { - wifi_pwrseq_pin_q8: wifi-pwrseq-pins { - pins = "PL6", "PL7", "PL11"; - function = "gpio_in"; - bias-pull-up; - }; -}; - -&tcon0 { - pinctrl-names = "default"; - pinctrl-0 = <&lcd_rgb666_pins>; - status = "okay"; -}; - -&usbphy { - usb1_vbus-supply = <®_dldo1>; -}; diff --git a/sys/gnu/dts/arm/sun8i-r16-bananapi-m2m.dts b/sys/gnu/dts/arm/sun8i-r16-bananapi-m2m.dts deleted file mode 100644 index e1c75f7fa3c..00000000000 --- a/sys/gnu/dts/arm/sun8i-r16-bananapi-m2m.dts +++ /dev/null @@ -1,311 +0,0 @@ -/* - * Copyright (c) 2017 Free Electrons - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun8i-a33.dtsi" - -#include - -/ { - model = "BananaPi M2 Magic"; - compatible = "sinovoip,bananapi-m2m", "allwinner,sun8i-a33"; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - serial0 = &uart0; - serial1 = &uart1; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - blue { - label = "bpi-m2m:blue:usr"; - gpios = <&pio 2 7 GPIO_ACTIVE_LOW>; - }; - - green { - label = "bpi-m2m:green:usr"; - gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; - }; - - red { - label = "bpi-m2m:red:power"; - gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; - default-state = "on"; - }; - }; - - reg_vcc5v0: vcc5v0 { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&r_pio 0 6 GPIO_ACTIVE_LOW>; /* PL06 */ - clocks = <&rtc 1>; - clock-names = "ext_clock"; - }; -}; - -&codec { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <®_dcdc3>; -}; - -&cpu0_opp_table { - opp-1104000000 { - opp-hz = /bits/ 64 <1104000000>; - opp-microvolt = <1320000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - }; - - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <1320000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - }; -}; - -&dai { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&mmc0 { - vmmc-supply = <®_dcdc1>; - bus-width = <4>; - cd-gpios = <&pio 1 4 GPIO_ACTIVE_LOW>; /* PB4 */ - status = "okay"; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pg_pins>; - vmmc-supply = <®_aldo1>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_8bit_pins>; - vmmc-supply = <®_dcdc1>; - bus-width = <8>; - non-removable; - cap-mmc-hw-reset; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&r_rsb { - status = "okay"; - - axp22x: pmic@3a3 { - compatible = "x-powers,axp223"; - reg = <0x3a3>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - eldoin-supply = <®_dcdc1>; - x-powers,drive-vbus-en; - }; -}; - -#include "axp223.dtsi" - -&ac_power_supply { - status = "okay"; -}; - -®_aldo1 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-io"; -}; - -®_aldo2 { - regulator-always-on; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-name = "vdd-dll"; -}; - -®_aldo3 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_dc1sw { - regulator-name = "vcc-lcd"; -}; - -®_dc5ldo { - regulator-always-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpus"; -}; - -®_dcdc1 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-3v0"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-sys"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc5 { - regulator-always-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vcc-dram"; -}; - -/* - * Our WiFi chip needs both DLDO1 and DLDO2 to be powered at the same - * time, with the two being in sync. Since this is not really - * supported right now, just use the two as always on, and we will fix - * it later. - */ -®_dldo1 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi0"; -}; - -®_dldo2 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi1"; -}; - -®_drivevbus { - regulator-name = "usb0-vbus"; - status = "okay"; -}; - -®_rtc_ldo { - regulator-name = "vcc-rtc"; -}; - -&sound { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pg_pins>, <&uart1_cts_rts_pg_pins>; - uart-has-rtscts; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - clocks = <&rtc 1>; - clock-names = "lpo"; - vbat-supply = <®_dldo1>; - vddio-supply = <®_aldo3>; - device-wakeup-gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */ - host-wakeup-gpios = <&r_pio 0 9 GPIO_ACTIVE_HIGH>; /* PL9 */ - shutdown-gpios = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */ - }; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usb_power_supply { - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 7 8 GPIO_ACTIVE_HIGH>; /* PH8 */ - usb0_vbus_power-supply = <&usb_power_supply>; - usb0_vbus-supply = <®_drivevbus>; - usb1_vbus-supply = <®_vcc5v0>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun8i-r16-nintendo-nes-classic.dts b/sys/gnu/dts/arm/sun8i-r16-nintendo-nes-classic.dts deleted file mode 100644 index 246dec5846a..00000000000 --- a/sys/gnu/dts/arm/sun8i-r16-nintendo-nes-classic.dts +++ /dev/null @@ -1,54 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR X11 -/* Copyright (c) 2016 FUKAUMI Naoki */ - -/dts-v1/; -#include "sun8i-a33.dtsi" -#include "sunxi-common-regulators.dtsi" - -/ { - model = "Nintendo NES Classic Edition"; - compatible = "nintendo,nes-classic", "allwinner,sun8i-r16", - "allwinner,sun8i-a33"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&uart0 { - /* - * UART0 is available on two ports: PB and PF, both are accessible. - * PF can also be used for the SD card so PB is preferred. - */ - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pf_pins>; - status = "okay"; -}; - -&nfc { - status = "okay"; - - /* 2Gb Macronix MX30LF2G18AC (3V) */ - nand@0 { - reg = <0>; - allwinner,rb = <0>; - nand-ecc-mode = "hw"; - nand-ecc-strength = <16>; - nand-ecc-step-size = <1024>; - }; -}; - -&usb_otg { - status = "okay"; - dr_mode = "otg"; -}; - -&usbphy { - /* VBUS is always on because it is wired to the power supply */ - usb1_vbus-supply = <®_vcc5v0>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun8i-r16-nintendo-super-nes-classic.dts b/sys/gnu/dts/arm/sun8i-r16-nintendo-super-nes-classic.dts deleted file mode 100644 index 80761d7904e..00000000000 --- a/sys/gnu/dts/arm/sun8i-r16-nintendo-super-nes-classic.dts +++ /dev/null @@ -1,11 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR X11 -/* Copyright (c) 2018 Miquèl RAYNAL */ - -/dts-v1/; -#include "sun8i-r16-nintendo-nes-classic.dts" - -/ { - model = "Nintendo SuperNES Classic Edition"; - compatible = "nintendo,super-nes-classic", "nintendo,nes-classic", - "allwinner,sun8i-r16", "allwinner,sun8i-a33"; -}; diff --git a/sys/gnu/dts/arm/sun8i-r16-parrot.dts b/sys/gnu/dts/arm/sun8i-r16-parrot.dts deleted file mode 100644 index 4f48eec6b2e..00000000000 --- a/sys/gnu/dts/arm/sun8i-r16-parrot.dts +++ /dev/null @@ -1,313 +0,0 @@ -/* - * Copyright 2016 Quentin Schulz - * - * Quentin Schulz - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun8i-a33.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include - -/ { - model = "Allwinner R16 EVB (Parrot)"; - compatible = "allwinner,parrot", "allwinner,sun8i-a33"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - led1 { - label = "parrot:led1:usr"; - gpio = <&pio 4 17 GPIO_ACTIVE_HIGH>; /* PE17 */ - }; - - led2 { - label = "parrot:led2:usr"; - gpio = <&pio 4 16 GPIO_ACTIVE_HIGH>; /* PE16 */ - }; - }; - - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&r_pio 0 6 GPIO_ACTIVE_LOW>; /* PL06 */ - }; - -}; - -&codec { - status = "okay"; -}; - -&dai { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&i2c1 { - status = "okay"; - - /* - * FIXME: An as-yet-unknown accelerometer is connected to this - * i2c bus. - */ -}; - -&lradc { - vref-supply = <®_aldo3>; - status = "okay"; - - button-190 { - label = "V+"; - linux,code = ; - channel = <0>; - voltage = <190000>; - }; - - button-390 { - label = "V-"; - linux,code = ; - channel = <0>; - voltage = <390000>; - }; - -}; - -&mmc0 { - vmmc-supply = <®_dcdc1>; - cd-gpios = <&pio 3 14 GPIO_ACTIVE_LOW>; /* PD14 */ - bus-width = <4>; - status = "okay"; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pg_pins>; - vmmc-supply = <®_aldo1>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_8bit_pins>; - vmmc-supply = <®_dcdc1>; - bus-width = <8>; - non-removable; - cap-mmc-hw-reset; - status = "okay"; -}; - -&mmc2_8bit_pins { - drive-strength = <40>; -}; - -&ohci0 { - status = "okay"; -}; - -&r_rsb { - status = "okay"; - - axp22x: pmic@3a3 { - compatible = "x-powers,axp223"; - reg = <0x3a3>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - drivevbus-supply = <®_vcc5v0>; - x-powers,drive-vbus-en; - }; -}; - -#include "axp223.dtsi" - -®_aldo1 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-io"; -}; - -®_aldo2 { - regulator-always-on; - regulator-min-microvolt = <2350000>; - regulator-max-microvolt = <2650000>; - regulator-name = "vdd-dll"; -}; - -®_aldo3 { - regulator-always-on; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-pll-avcc"; -}; - -®_dc5ldo { - regulator-always-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpus"; -}; - -®_dcdc1 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-3v0"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-sys"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc5 { - regulator-always-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vcc-dram"; -}; - -®_dldo1 { - /* - * TODO: WiFi chip needs dldo1 AND dldo2 to be on to be powered. - * Remove next line once it is possible to sync two regulators. - */ - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi0"; -}; - -®_dldo2 { - /* - * TODO: WiFi chip needs dldo1 AND dldo2 to be on to be powered. - * Remove next line once it is possible to sync two regulators. - */ - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi1"; -}; - -®_dldo3 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-3v0-csi"; -}; - -®_drivevbus { - regulator-name = "usb0-vbus"; - status = "okay"; -}; - -®_eldo1 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-name = "vcc-1v2-hsic"; -}; - -®_eldo2 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-dsp"; -}; - -®_eldo3 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "eldo3"; -}; - -®_usb1_vbus { - gpio = <&pio 3 12 GPIO_ACTIVE_HIGH>; /* PD12 */ - status = "okay"; -}; - -&sound { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usb_power_supply { - status = "okay"; -}; - -&usbphy { - status = "okay"; - usb0_vbus-supply = <®_drivevbus>; - usb0_id_det-gpios = <&pio 3 10 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PD10 */ - usb0_vbus_power-supply = <&usb_power_supply>; - usb1_vbus-supply = <®_usb1_vbus>; -}; diff --git a/sys/gnu/dts/arm/sun8i-r40-bananapi-m2-ultra.dts b/sys/gnu/dts/arm/sun8i-r40-bananapi-m2-ultra.dts deleted file mode 100644 index 42d62d1ba1d..00000000000 --- a/sys/gnu/dts/arm/sun8i-r40-bananapi-m2-ultra.dts +++ /dev/null @@ -1,331 +0,0 @@ -/* - * Copyright (C) 2017 Chen-Yu Tsai - * Copyright (C) 2017 Icenowy Zheng - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun8i-r40.dtsi" - -#include - -/ { - model = "Banana Pi BPI-M2-Ultra"; - compatible = "sinovoip,bpi-m2-ultra", "allwinner,sun8i-r40"; - - aliases { - ethernet0 = &gmac; - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - pwr-led { - label = "bananapi:red:pwr"; - gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - user-led-green { - label = "bananapi:green:user"; - gpios = <&pio 7 21 GPIO_ACTIVE_HIGH>; - }; - - user-led-blue { - label = "bananapi:blue:user"; - gpios = <&pio 7 22 GPIO_ACTIVE_HIGH>; - }; - }; - - reg_vcc5v0: vcc5v0 { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&pio 7 23 GPIO_ACTIVE_HIGH>; /* PH23 */ - enable-active-high; - }; - - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&pio 6 10 GPIO_ACTIVE_LOW>; /* PG10 WIFI_EN */ - clocks = <&ccu CLK_OUTA>; - clock-names = "ext_clock"; - }; -}; - -&ahci { - ahci-supply = <®_dldo4>; - phy-supply = <®_eldo3>; - status = "okay"; -}; - -&de { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&ehci2 { - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_rgmii_pins>; - phy-handle = <&phy1>; - phy-mode = "rgmii"; - phy-supply = <®_dc1sw>; - status = "okay"; -}; - -&gmac_mdio { - phy1: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&i2c0 { - status = "okay"; - - axp22x: pmic@34 { - compatible = "x-powers,axp221"; - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -#include "axp22x.dtsi" - -&mmc0 { - vmmc-supply = <®_dcdc1>; - bus-width = <4>; - cd-gpios = <&pio 7 13 GPIO_ACTIVE_LOW>; /* PH13 */ - status = "okay"; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pg_pins>; - vmmc-supply = <®_dldo2>; - vqmmc-supply = <®_dldo1>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; -}; - -&mmc2 { - vmmc-supply = <®_dcdc1>; - vqmmc-supply = <®_dcdc1>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&ohci2 { - status = "okay"; -}; - -&pio { - pinctrl-names = "default"; - pinctrl-0 = <&clk_out_a_pin>; - vcc-pa-supply = <®_aldo2>; - vcc-pc-supply = <®_dcdc1>; - vcc-pd-supply = <®_dcdc1>; - vcc-pe-supply = <®_eldo1>; - vcc-pf-supply = <®_dcdc1>; - vcc-pg-supply = <®_dldo1>; -}; - -®_aldo2 { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-name = "vcc-pa"; -}; - -®_aldo3 { - regulator-always-on; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <3300000>; - regulator-name = "avcc"; -}; - -®_dc1sw { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-gmac-phy"; -}; - -®_dcdc1 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-3v0"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1300000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1300000>; - regulator-name = "vdd-sys"; -}; - -®_dcdc5 { - regulator-always-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vcc-dram"; -}; - -®_dldo1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi-io"; -}; - -/* - * Our WiFi chip needs both DLDO2 and DLDO3 to be powered at the same - * time, with the two being in sync, to be able to meet maximum power - * consumption during transmits. Since this is not really supported - * right now, just use the two as always on, and we will fix it later. - */ - -®_dldo2 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi"; -}; - -®_dldo3 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi-2"; -}; - -®_dldo4 { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-name = "vdd2v5-sata"; -}; - -®_eldo3 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-name = "vdd1v2-sata"; -}; - -&tcon_tv0 { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pg_pins>, <&uart3_rts_cts_pg_pins>; - uart-has-rtscts; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - clocks = <&ccu CLK_OUTA>; - clock-names = "lpo"; - vbat-supply = <®_dldo2>; - vddio-supply = <®_dldo1>; - device-wakeup-gpios = <&pio 6 11 GPIO_ACTIVE_HIGH>; /* PG11 */ - /* TODO host wake line connected to PMIC GPIO pins */ - shutdown-gpios = <&pio 7 12 GPIO_ACTIVE_HIGH>; /* PH12 */ - max-speed = <1500000>; - }; -}; - -&usbphy { - usb1_vbus-supply = <®_vcc5v0>; - usb2_vbus-supply = <®_vcc5v0>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun8i-r40.dtsi b/sys/gnu/dts/arm/sun8i-r40.dtsi deleted file mode 100644 index a9d5d6ddbd7..00000000000 --- a/sys/gnu/dts/arm/sun8i-r40.dtsi +++ /dev/null @@ -1,1021 +0,0 @@ -/* - * Copyright 2017 Chen-Yu Tsai - * Copyright 2017 Icenowy Zheng - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include -#include -#include -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&gic>; - - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - osc24M: osc24M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-accuracy = <50000>; - clock-output-names = "osc24M"; - }; - - osc32k: osc32k { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - clock-accuracy = <20000>; - clock-output-names = "ext-osc32k"; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <0>; - }; - - cpu1: cpu@1 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <1>; - }; - - cpu2: cpu@2 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <2>; - }; - - cpu3: cpu@3 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <3>; - }; - }; - - de: display-engine { - compatible = "allwinner,sun8i-r40-display-engine"; - allwinner,pipelines = <&mixer0>, <&mixer1>; - status = "disabled"; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - display_clocks: clock@1000000 { - compatible = "allwinner,sun8i-r40-de2-clk", - "allwinner,sun8i-h3-de2-clk"; - reg = <0x01000000 0x100000>; - clocks = <&ccu CLK_BUS_DE>, - <&ccu CLK_DE>; - clock-names = "bus", - "mod"; - resets = <&ccu RST_BUS_DE>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - mixer0: mixer@1100000 { - compatible = "allwinner,sun8i-r40-de2-mixer-0"; - reg = <0x01100000 0x100000>; - clocks = <&display_clocks CLK_BUS_MIXER0>, - <&display_clocks CLK_MIXER0>; - clock-names = "bus", - "mod"; - resets = <&display_clocks RST_MIXER0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - mixer0_out: port@1 { - reg = <1>; - mixer0_out_tcon_top: endpoint { - remote-endpoint = <&tcon_top_mixer0_in_mixer0>; - }; - }; - }; - }; - - mixer1: mixer@1200000 { - compatible = "allwinner,sun8i-r40-de2-mixer-1"; - reg = <0x01200000 0x100000>; - clocks = <&display_clocks CLK_BUS_MIXER1>, - <&display_clocks CLK_MIXER1>; - clock-names = "bus", - "mod"; - resets = <&display_clocks RST_WB>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - mixer1_out: port@1 { - reg = <1>; - mixer1_out_tcon_top: endpoint { - remote-endpoint = <&tcon_top_mixer1_in_mixer1>; - }; - }; - }; - }; - - nmi_intc: interrupt-controller@1c00030 { - compatible = "allwinner,sun7i-a20-sc-nmi"; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x01c00030 0x0c>; - interrupts = ; - }; - - spi0: spi@1c05000 { - compatible = "allwinner,sun8i-r40-spi", - "allwinner,sun8i-h3-spi"; - reg = <0x01c05000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; - clock-names = "ahb", "mod"; - resets = <&ccu RST_BUS_SPI0>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - spi1: spi@1c06000 { - compatible = "allwinner,sun8i-r40-spi", - "allwinner,sun8i-h3-spi"; - reg = <0x01c06000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; - clock-names = "ahb", "mod"; - resets = <&ccu RST_BUS_SPI1>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - csi0: csi@1c09000 { - compatible = "allwinner,sun8i-r40-csi0", - "allwinner,sun7i-a20-csi0"; - reg = <0x01c09000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_BUS_CSI0>, <&ccu CLK_CSI_SCLK>, - <&ccu CLK_DRAM_CSI0>; - clock-names = "bus", "isp", "ram"; - resets = <&ccu RST_BUS_CSI0>; - interconnects = <&mbus 5>; - interconnect-names = "dma-mem"; - status = "disabled"; - }; - - mmc0: mmc@1c0f000 { - compatible = "allwinner,sun8i-r40-mmc", - "allwinner,sun50i-a64-mmc"; - reg = <0x01c0f000 0x1000>; - clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; - clock-names = "ahb", "mmc"; - resets = <&ccu RST_BUS_MMC0>; - reset-names = "ahb"; - pinctrl-0 = <&mmc0_pins>; - pinctrl-names = "default"; - interrupts = ; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc1: mmc@1c10000 { - compatible = "allwinner,sun8i-r40-mmc", - "allwinner,sun50i-a64-mmc"; - reg = <0x01c10000 0x1000>; - clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; - clock-names = "ahb", "mmc"; - resets = <&ccu RST_BUS_MMC1>; - reset-names = "ahb"; - interrupts = ; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc2: mmc@1c11000 { - compatible = "allwinner,sun8i-r40-emmc", - "allwinner,sun50i-a64-emmc"; - reg = <0x01c11000 0x1000>; - clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; - clock-names = "ahb", "mmc"; - resets = <&ccu RST_BUS_MMC2>; - reset-names = "ahb"; - pinctrl-0 = <&mmc2_pins>; - pinctrl-names = "default"; - interrupts = ; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc3: mmc@1c12000 { - compatible = "allwinner,sun8i-r40-mmc", - "allwinner,sun50i-a64-mmc"; - reg = <0x01c12000 0x1000>; - clocks = <&ccu CLK_BUS_MMC3>, <&ccu CLK_MMC3>; - clock-names = "ahb", "mmc"; - resets = <&ccu RST_BUS_MMC3>; - reset-names = "ahb"; - interrupts = ; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - usbphy: phy@1c13400 { - compatible = "allwinner,sun8i-r40-usb-phy"; - reg = <0x01c13400 0x14>, - <0x01c14800 0x4>, - <0x01c19800 0x4>, - <0x01c1c800 0x4>; - reg-names = "phy_ctrl", - "pmu0", - "pmu1", - "pmu2"; - clocks = <&ccu CLK_USB_PHY0>, - <&ccu CLK_USB_PHY1>, - <&ccu CLK_USB_PHY2>; - clock-names = "usb0_phy", - "usb1_phy", - "usb2_phy"; - resets = <&ccu RST_USB_PHY0>, - <&ccu RST_USB_PHY1>, - <&ccu RST_USB_PHY2>; - reset-names = "usb0_reset", - "usb1_reset", - "usb2_reset"; - status = "disabled"; - #phy-cells = <1>; - }; - - crypto: crypto@1c15000 { - compatible = "allwinner,sun8i-r40-crypto"; - reg = <0x01c15000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>; - clock-names = "bus", "mod"; - resets = <&ccu RST_BUS_CE>; - }; - - spi2: spi@1c17000 { - compatible = "allwinner,sun8i-r40-spi", - "allwinner,sun8i-h3-spi"; - reg = <0x01c17000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_BUS_SPI2>, <&ccu CLK_SPI2>; - clock-names = "ahb", "mod"; - resets = <&ccu RST_BUS_SPI2>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - ahci: sata@1c18000 { - compatible = "allwinner,sun8i-r40-ahci"; - reg = <0x01c18000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_BUS_SATA>, <&ccu CLK_SATA>; - resets = <&ccu RST_BUS_SATA>; - reset-names = "ahci"; - status = "disabled"; - }; - - ehci1: usb@1c19000 { - compatible = "allwinner,sun8i-r40-ehci", "generic-ehci"; - reg = <0x01c19000 0x100>; - interrupts = ; - clocks = <&ccu CLK_BUS_EHCI1>; - resets = <&ccu RST_BUS_EHCI1>; - phys = <&usbphy 1>; - phy-names = "usb"; - status = "disabled"; - }; - - ohci1: usb@1c19400 { - compatible = "allwinner,sun8i-r40-ohci", "generic-ohci"; - reg = <0x01c19400 0x100>; - interrupts = ; - clocks = <&ccu CLK_BUS_OHCI1>, - <&ccu CLK_USB_OHCI1>; - resets = <&ccu RST_BUS_OHCI1>; - phys = <&usbphy 1>; - phy-names = "usb"; - status = "disabled"; - }; - - ehci2: usb@1c1c000 { - compatible = "allwinner,sun8i-r40-ehci", "generic-ehci"; - reg = <0x01c1c000 0x100>; - interrupts = ; - clocks = <&ccu CLK_BUS_EHCI2>; - resets = <&ccu RST_BUS_EHCI2>; - phys = <&usbphy 2>; - phy-names = "usb"; - status = "disabled"; - }; - - ohci2: usb@1c1c400 { - compatible = "allwinner,sun8i-r40-ohci", "generic-ohci"; - reg = <0x01c1c400 0x100>; - interrupts = ; - clocks = <&ccu CLK_BUS_OHCI2>, - <&ccu CLK_USB_OHCI2>; - resets = <&ccu RST_BUS_OHCI2>; - phys = <&usbphy 2>; - phy-names = "usb"; - status = "disabled"; - }; - - spi3: spi@1c1f000 { - compatible = "allwinner,sun8i-r40-spi", - "allwinner,sun8i-h3-spi"; - reg = <0x01c1f000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_BUS_SPI3>, <&ccu CLK_SPI3>; - clock-names = "ahb", "mod"; - resets = <&ccu RST_BUS_SPI3>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - ccu: clock@1c20000 { - compatible = "allwinner,sun8i-r40-ccu"; - reg = <0x01c20000 0x400>; - clocks = <&osc24M>, <&rtc 0>; - clock-names = "hosc", "losc"; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - rtc: rtc@1c20400 { - compatible = "allwinner,sun8i-r40-rtc"; - reg = <0x01c20400 0x400>; - interrupts = ; - clock-output-names = "osc32k", "osc32k-out"; - clocks = <&osc32k>; - #clock-cells = <1>; - }; - - pio: pinctrl@1c20800 { - compatible = "allwinner,sun8i-r40-pinctrl"; - reg = <0x01c20800 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>; - clock-names = "apb", "hosc", "losc"; - gpio-controller; - interrupt-controller; - #interrupt-cells = <3>; - #gpio-cells = <3>; - - clk_out_a_pin: clk-out-a-pin { - pins = "PI12"; - function = "clk_out_a"; - }; - - /omit-if-no-ref/ - csi0_8bits_pins: csi0-8bits-pins { - pins = "PE0", "PE2", "PE3", "PE4", "PE5", - "PE6", "PE7", "PE8", "PE9", "PE10", - "PE11"; - function = "csi0"; - }; - - /omit-if-no-ref/ - csi0_mclk_pin: csi0-mclk-pin { - pins = "PE1"; - function = "csi0"; - }; - - gmac_rgmii_pins: gmac-rgmii-pins { - pins = "PA0", "PA1", "PA2", "PA3", - "PA4", "PA5", "PA6", "PA7", - "PA8", "PA10", "PA11", "PA12", - "PA13", "PA15", "PA16"; - function = "gmac"; - /* - * data lines in RGMII mode use DDR mode - * and need a higher signal drive strength - */ - drive-strength = <40>; - }; - - i2c0_pins: i2c0-pins { - pins = "PB0", "PB1"; - function = "i2c0"; - }; - - i2c1_pins: i2c1-pins { - pins = "PB18", "PB19"; - function = "i2c1"; - }; - - i2c2_pins: i2c2-pins { - pins = "PB20", "PB21"; - function = "i2c2"; - }; - - i2c3_pins: i2c3-pins { - pins = "PI0", "PI1"; - function = "i2c3"; - }; - - i2c4_pins: i2c4-pins { - pins = "PI2", "PI3"; - function = "i2c4"; - }; - - mmc0_pins: mmc0-pins { - pins = "PF0", "PF1", "PF2", - "PF3", "PF4", "PF5"; - function = "mmc0"; - drive-strength = <30>; - bias-pull-up; - }; - - mmc1_pg_pins: mmc1-pg-pins { - pins = "PG0", "PG1", "PG2", - "PG3", "PG4", "PG5"; - function = "mmc1"; - drive-strength = <30>; - bias-pull-up; - }; - - mmc2_pins: mmc2-pins { - pins = "PC5", "PC6", "PC7", "PC8", "PC9", - "PC10", "PC11", "PC12", "PC13", "PC14", - "PC15", "PC24"; - function = "mmc2"; - drive-strength = <30>; - bias-pull-up; - }; - - /omit-if-no-ref/ - spi0_pc_pins: spi0-pc-pins { - pins = "PC0", "PC1", "PC2"; - function = "spi0"; - }; - - /omit-if-no-ref/ - spi0_cs0_pc_pin: spi0-cs0-pc-pin { - pins = "PC23"; - function = "spi0"; - }; - - /omit-if-no-ref/ - spi1_pi_pins: spi1-pi-pins { - pins = "PI17", "PI18", "PI19"; - function = "spi1"; - }; - - /omit-if-no-ref/ - spi1_cs0_pi_pin: spi1-cs0-pi-pin { - pins = "PI16"; - function = "spi1"; - }; - - /omit-if-no-ref/ - spi1_cs1_pi_pin: spi1-cs1-pi-pin { - pins = "PI15"; - function = "spi1"; - }; - - uart0_pb_pins: uart0-pb-pins { - pins = "PB22", "PB23"; - function = "uart0"; - }; - - uart3_pg_pins: uart3-pg-pins { - pins = "PG6", "PG7"; - function = "uart3"; - }; - - uart3_rts_cts_pg_pins: uart3-rts-cts-pg-pins { - pins = "PG8", "PG9"; - function = "uart3"; - }; - }; - - wdt: watchdog@1c20c90 { - compatible = "allwinner,sun4i-a10-wdt"; - reg = <0x01c20c90 0x10>; - interrupts = ; - clocks = <&osc24M>; - }; - - uart0: serial@1c28000 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART0>; - resets = <&ccu RST_BUS_UART0>; - status = "disabled"; - }; - - uart1: serial@1c28400 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28400 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART1>; - resets = <&ccu RST_BUS_UART1>; - status = "disabled"; - }; - - uart2: serial@1c28800 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28800 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART2>; - resets = <&ccu RST_BUS_UART2>; - status = "disabled"; - }; - - uart3: serial@1c28c00 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28c00 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART3>; - resets = <&ccu RST_BUS_UART3>; - status = "disabled"; - }; - - uart4: serial@1c29000 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c29000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART4>; - resets = <&ccu RST_BUS_UART4>; - status = "disabled"; - }; - - uart5: serial@1c29400 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c29400 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART5>; - resets = <&ccu RST_BUS_UART5>; - status = "disabled"; - }; - - uart6: serial@1c29800 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c29800 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART6>; - resets = <&ccu RST_BUS_UART6>; - status = "disabled"; - }; - - uart7: serial@1c29c00 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c29c00 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART7>; - resets = <&ccu RST_BUS_UART7>; - status = "disabled"; - }; - - i2c0: i2c@1c2ac00 { - compatible = "allwinner,sun6i-a31-i2c"; - reg = <0x01c2ac00 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_I2C0>; - resets = <&ccu RST_BUS_I2C0>; - pinctrl-0 = <&i2c0_pins>; - pinctrl-names = "default"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c1: i2c@1c2b000 { - compatible = "allwinner,sun6i-a31-i2c"; - reg = <0x01c2b000 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_I2C1>; - resets = <&ccu RST_BUS_I2C1>; - pinctrl-0 = <&i2c1_pins>; - pinctrl-names = "default"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c2: i2c@1c2b400 { - compatible = "allwinner,sun6i-a31-i2c"; - reg = <0x01c2b400 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_I2C2>; - resets = <&ccu RST_BUS_I2C2>; - pinctrl-0 = <&i2c2_pins>; - pinctrl-names = "default"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c3: i2c@1c2b800 { - compatible = "allwinner,sun6i-a31-i2c"; - reg = <0x01c2b800 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_I2C3>; - resets = <&ccu RST_BUS_I2C3>; - pinctrl-0 = <&i2c3_pins>; - pinctrl-names = "default"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c4: i2c@1c2c000 { - compatible = "allwinner,sun6i-a31-i2c"; - reg = <0x01c2c000 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_I2C4>; - resets = <&ccu RST_BUS_I2C4>; - pinctrl-0 = <&i2c4_pins>; - pinctrl-names = "default"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - gmac: ethernet@1c50000 { - compatible = "allwinner,sun8i-r40-gmac"; - syscon = <&ccu>; - reg = <0x01c50000 0x10000>; - interrupts = ; - interrupt-names = "macirq"; - resets = <&ccu RST_BUS_GMAC>; - reset-names = "stmmaceth"; - clocks = <&ccu CLK_BUS_GMAC>; - clock-names = "stmmaceth"; - status = "disabled"; - - gmac_mdio: mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - mbus: dram-controller@1c62000 { - compatible = "allwinner,sun8i-r40-mbus"; - reg = <0x01c62000 0x1000>; - clocks = <&ccu 155>; - dma-ranges = <0x00000000 0x40000000 0x80000000>; - #interconnect-cells = <1>; - }; - - tcon_top: tcon-top@1c70000 { - compatible = "allwinner,sun8i-r40-tcon-top"; - reg = <0x01c70000 0x1000>; - clocks = <&ccu CLK_BUS_TCON_TOP>, - <&ccu CLK_TCON_TV0>, - <&ccu CLK_TVE0>, - <&ccu CLK_TCON_TV1>, - <&ccu CLK_TVE1>, - <&ccu CLK_DSI_DPHY>; - clock-names = "bus", - "tcon-tv0", - "tve0", - "tcon-tv1", - "tve1", - "dsi"; - clock-output-names = "tcon-top-tv0", - "tcon-top-tv1", - "tcon-top-dsi"; - resets = <&ccu RST_BUS_TCON_TOP>; - #clock-cells = <1>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - tcon_top_mixer0_in: port@0 { - reg = <0>; - - tcon_top_mixer0_in_mixer0: endpoint { - remote-endpoint = <&mixer0_out_tcon_top>; - }; - }; - - tcon_top_mixer0_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - tcon_top_mixer0_out_tcon_lcd0: endpoint@0 { - reg = <0>; - }; - - tcon_top_mixer0_out_tcon_lcd1: endpoint@1 { - reg = <1>; - }; - - tcon_top_mixer0_out_tcon_tv0: endpoint@2 { - reg = <2>; - remote-endpoint = <&tcon_tv0_in_tcon_top_mixer0>; - }; - - tcon_top_mixer0_out_tcon_tv1: endpoint@3 { - reg = <3>; - remote-endpoint = <&tcon_tv1_in_tcon_top_mixer0>; - }; - }; - - tcon_top_mixer1_in: port@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - - tcon_top_mixer1_in_mixer1: endpoint@1 { - reg = <1>; - remote-endpoint = <&mixer1_out_tcon_top>; - }; - }; - - tcon_top_mixer1_out: port@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - - tcon_top_mixer1_out_tcon_lcd0: endpoint@0 { - reg = <0>; - }; - - tcon_top_mixer1_out_tcon_lcd1: endpoint@1 { - reg = <1>; - }; - - tcon_top_mixer1_out_tcon_tv0: endpoint@2 { - reg = <2>; - remote-endpoint = <&tcon_tv0_in_tcon_top_mixer1>; - }; - - tcon_top_mixer1_out_tcon_tv1: endpoint@3 { - reg = <3>; - remote-endpoint = <&tcon_tv1_in_tcon_top_mixer1>; - }; - }; - - tcon_top_hdmi_in: port@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - - tcon_top_hdmi_in_tcon_tv0: endpoint@0 { - reg = <0>; - remote-endpoint = <&tcon_tv0_out_tcon_top>; - }; - - tcon_top_hdmi_in_tcon_tv1: endpoint@1 { - reg = <1>; - remote-endpoint = <&tcon_tv1_out_tcon_top>; - }; - }; - - tcon_top_hdmi_out: port@5 { - reg = <5>; - - tcon_top_hdmi_out_hdmi: endpoint { - remote-endpoint = <&hdmi_in_tcon_top>; - }; - }; - }; - }; - - tcon_tv0: lcd-controller@1c73000 { - compatible = "allwinner,sun8i-r40-tcon-tv"; - reg = <0x01c73000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_BUS_TCON_TV0>, <&tcon_top CLK_TCON_TOP_TV0>; - clock-names = "ahb", "tcon-ch1"; - resets = <&ccu RST_BUS_TCON_TV0>; - reset-names = "lcd"; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - tcon_tv0_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - tcon_tv0_in_tcon_top_mixer0: endpoint@0 { - reg = <0>; - remote-endpoint = <&tcon_top_mixer0_out_tcon_tv0>; - }; - - tcon_tv0_in_tcon_top_mixer1: endpoint@1 { - reg = <1>; - remote-endpoint = <&tcon_top_mixer1_out_tcon_tv0>; - }; - }; - - tcon_tv0_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - tcon_tv0_out_tcon_top: endpoint@1 { - reg = <1>; - remote-endpoint = <&tcon_top_hdmi_in_tcon_tv0>; - }; - }; - }; - }; - - tcon_tv1: lcd-controller@1c74000 { - compatible = "allwinner,sun8i-r40-tcon-tv"; - reg = <0x01c74000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_BUS_TCON_TV1>, <&tcon_top CLK_TCON_TOP_TV1>; - clock-names = "ahb", "tcon-ch1"; - resets = <&ccu RST_BUS_TCON_TV1>; - reset-names = "lcd"; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - tcon_tv1_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - tcon_tv1_in_tcon_top_mixer0: endpoint@0 { - reg = <0>; - remote-endpoint = <&tcon_top_mixer0_out_tcon_tv1>; - }; - - tcon_tv1_in_tcon_top_mixer1: endpoint@1 { - reg = <1>; - remote-endpoint = <&tcon_top_mixer1_out_tcon_tv1>; - }; - }; - - tcon_tv1_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - tcon_tv1_out_tcon_top: endpoint@1 { - reg = <1>; - remote-endpoint = <&tcon_top_hdmi_in_tcon_tv1>; - }; - }; - }; - }; - - gic: interrupt-controller@1c81000 { - compatible = "arm,gic-400"; - reg = <0x01c81000 0x1000>, - <0x01c82000 0x2000>, - <0x01c84000 0x2000>, - <0x01c86000 0x2000>; - interrupt-controller; - #interrupt-cells = <3>; - interrupts = ; - }; - - hdmi: hdmi@1ee0000 { - compatible = "allwinner,sun8i-r40-dw-hdmi", - "allwinner,sun8i-a83t-dw-hdmi"; - reg = <0x01ee0000 0x10000>; - reg-io-width = <1>; - interrupts = ; - clocks = <&ccu CLK_BUS_HDMI0>, <&ccu CLK_HDMI_SLOW>, - <&ccu CLK_HDMI>; - clock-names = "iahb", "isfr", "tmds"; - resets = <&ccu RST_BUS_HDMI1>; - reset-names = "ctrl"; - phys = <&hdmi_phy>; - phy-names = "phy"; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - hdmi_in: port@0 { - reg = <0>; - - hdmi_in_tcon_top: endpoint { - remote-endpoint = <&tcon_top_hdmi_out_hdmi>; - }; - }; - - hdmi_out: port@1 { - reg = <1>; - }; - }; - }; - - hdmi_phy: hdmi-phy@1ef0000 { - compatible = "allwinner,sun8i-r40-hdmi-phy"; - reg = <0x01ef0000 0x10000>; - clocks = <&ccu CLK_BUS_HDMI1>, <&ccu CLK_HDMI_SLOW>, - <&ccu CLK_PLL_VIDEO0>, <&ccu CLK_PLL_VIDEO1>; - clock-names = "bus", "mod", "pll-0", "pll-1"; - resets = <&ccu RST_BUS_HDMI0>; - reset-names = "phy"; - #phy-cells = <0>; - }; - }; - - pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts = , - , - , - ; - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; - }; -}; diff --git a/sys/gnu/dts/arm/sun8i-reference-design-tablet.dtsi b/sys/gnu/dts/arm/sun8i-reference-design-tablet.dtsi deleted file mode 100644 index b3d8b8f056c..00000000000 --- a/sys/gnu/dts/arm/sun8i-reference-design-tablet.dtsi +++ /dev/null @@ -1,223 +0,0 @@ -/* - * Copyright 2015 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -#include "sunxi-reference-design-tablet.dtsi" - -#include - -/ { - aliases { - serial0 = &r_uart; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; - brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; - default-brightness-level = <8>; - enable-gpios = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */ - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&i2c0 { - /* - * The gsl1680 is rated at 400KHz and it will not work reliable at - * 100KHz, this has been confirmed on multiple different q8 tablets. - * The gsl1680 is the only device on this bus. - */ - clock-frequency = <400000>; - - touchscreen: touchscreen@40 { - reg = <0x40>; - interrupt-parent = <&pio>; - interrupts = <1 5 IRQ_TYPE_EDGE_FALLING>; /* PB5 */ - power-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - /* Tablet dts must provide reg and compatible */ - status = "disabled"; - }; -}; - -&mmc0 { - vmmc-supply = <®_dcdc1>; - bus-width = <4>; - cd-gpios = <&pio 1 4 GPIO_ACTIVE_LOW>; /* PB4 */ - status = "okay"; -}; - -&r_rsb { - status = "okay"; - - axp22x: pmic@3a3 { - compatible = "x-powers,axp223"; - reg = <0x3a3>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - eldoin-supply = <®_dcdc1>; - drivevbus-supply = <®_vcc5v0>; - x-powers,drive-vbus-en; - }; -}; - -#include "axp223.dtsi" - -&ac_power_supply { - status = "okay"; -}; - -&battery_power_supply { - status = "okay"; -}; - -®_aldo1 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-io"; -}; - -®_aldo2 { - regulator-always-on; - regulator-min-microvolt = <2350000>; - regulator-max-microvolt = <2650000>; - regulator-name = "vdd-dll"; -}; - -®_aldo3 { - regulator-always-on; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-pll-avcc"; -}; - -®_dc1sw { - regulator-name = "vcc-lcd"; -}; - -®_dc5ldo { - regulator-always-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpus"; -}; - -®_dcdc1 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-3v0"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-sys"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc5 { - regulator-always-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vcc-dram"; -}; - -®_dldo1 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi"; -}; - -®_drivevbus { - regulator-name = "usb0-vbus"; - status = "okay"; -}; - -®_ldo_io1 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-touchscreen"; - status = "okay"; -}; - -®_rtc_ldo { - regulator-name = "vcc-rtc"; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&r_uart { - pinctrl-names = "default"; - pinctrl-0 = <&r_uart_pins_a>; - status = "okay"; -}; - -&simplefb_lcd { - vcc-lcd-supply = <®_dc1sw>; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usb_power_supply { - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 7 8 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH8 */ - usb0_vbus_power-supply = <&usb_power_supply>; - usb0_vbus-supply = <®_drivevbus>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun8i-s3-lichee-zero-plus.dts b/sys/gnu/dts/arm/sun8i-s3-lichee-zero-plus.dts deleted file mode 100644 index d18192d51d1..00000000000 --- a/sys/gnu/dts/arm/sun8i-s3-lichee-zero-plus.dts +++ /dev/null @@ -1,53 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2019 Icenowy Zheng - */ - -/dts-v1/; -#include "sun8i-v3.dtsi" - -#include - -/ { - model = "Sipeed Lichee Zero Plus"; - compatible = "sipeed,lichee-zero-plus", "sochip,s3", - "allwinner,sun8i-v3"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - reg_vcc3v3: vcc3v3 { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&mmc0 { - broken-cd; - bus-width = <4>; - vmmc-supply = <®_vcc3v3>; - status = "okay"; -}; - -&uart0 { - pinctrl-0 = <&uart0_pb_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&usb_otg { - dr_mode = "peripheral"; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun8i-t3-cqa3t-bv3.dts b/sys/gnu/dts/arm/sun8i-t3-cqa3t-bv3.dts deleted file mode 100644 index 6931aaab238..00000000000 --- a/sys/gnu/dts/arm/sun8i-t3-cqa3t-bv3.dts +++ /dev/null @@ -1,226 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (C) 2017 Chen-Yu Tsai - * Copyright (C) 2017 Icenowy Zheng - * Copyright (C) 2018 Hao Zhang - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun8i-r40.dtsi" - -#include - -/ { - model = "t3-cqa3t-bv3"; - compatible = "qihua,t3-cqa3t-bv3", "allwinner,sun8i-t3", - "allwinner,sun8i-r40"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - reg_vcc5v0: vcc5v0 { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&pio 7 23 GPIO_ACTIVE_HIGH>; /* PH23 */ - enable-active-high; - }; -}; - -&ahci { - ahci-supply = <®_dldo4>; - phy-supply = <®_eldo3>; - status = "okay"; -}; - -&de { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&ehci2 { - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&i2c0 { - status = "okay"; - - axp22x: pmic@34 { - compatible = "x-powers,axp221"; - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -#include "axp22x.dtsi" - -&mmc0 { - vmmc-supply = <®_dcdc1>; - bus-width = <4>; - cd-gpios = <&pio 7 15 GPIO_ACTIVE_LOW>; /* PH15 */ - status = "okay"; -}; - -&mmc2 { - vmmc-supply = <®_dcdc1>; - vqmmc-supply = <®_dcdc1>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&ohci2 { - status = "okay"; -}; - -®_aldo2 { - regulator-always-on; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-name = "vcc-pa"; -}; - -®_aldo3 { - regulator-always-on; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <3300000>; - regulator-name = "avcc"; -}; - -®_dcdc1 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-3v0"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1300000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1300000>; - regulator-name = "vdd-sys"; -}; - -®_dcdc5 { - regulator-always-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vcc-dram"; -}; - -®_dldo1 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-pg"; -}; - -®_dldo3 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-dldo3"; -}; - -®_eldo3 { - regulator-always-on; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-name = "vcc-pe"; -}; - -&tcon_tv0 { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usbphy { - usb1_vbus-supply = <®_vcc5v0>; - usb2_vbus-supply = <®_vcc5v0>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun8i-v3.dtsi b/sys/gnu/dts/arm/sun8i-v3.dtsi deleted file mode 100644 index 6ae8645ade5..00000000000 --- a/sys/gnu/dts/arm/sun8i-v3.dtsi +++ /dev/null @@ -1,14 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2019 Icenowy Zheng - */ - -#include "sun8i-v3s.dtsi" - -&ccu { - compatible = "allwinner,sun8i-v3-ccu"; -}; - -&pio { - compatible = "allwinner,sun8i-v3-pinctrl"; -}; diff --git a/sys/gnu/dts/arm/sun8i-v3s-licheepi-zero-dock.dts b/sys/gnu/dts/arm/sun8i-v3s-licheepi-zero-dock.dts deleted file mode 100644 index db5cd0b8574..00000000000 --- a/sys/gnu/dts/arm/sun8i-v3s-licheepi-zero-dock.dts +++ /dev/null @@ -1,96 +0,0 @@ -/* - * Copyright (C) 2016 Icenowy Zheng - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "sun8i-v3s-licheepi-zero.dts" - -#include - -/ { - model = "Lichee Pi Zero with Dock"; - compatible = "licheepi,licheepi-zero-dock", "licheepi,licheepi-zero", - "allwinner,sun8i-v3s"; - - leds { - /* The LEDs use PG0~2 pins, which conflict with MMC1 */ - status = "disabled"; - }; -}; - -&mmc1 { - broken-cd; - bus-width = <4>; - vmmc-supply = <®_vcc3v3>; - status = "okay"; -}; - -&lradc { - vref-supply = <®_vcc3v0>; - status = "okay"; - - button-200 { - label = "Volume Up"; - linux,code = ; - channel = <0>; - voltage = <200000>; - }; - - button-400 { - label = "Volume Down"; - linux,code = ; - channel = <0>; - voltage = <400000>; - }; - - button-600 { - label = "Select"; - linux,code = ; - channel = <0>; - voltage = <600000>; - }; - - button-800 { - label = "Start"; - linux,code = ; - channel = <0>; - voltage = <800000>; - }; -}; diff --git a/sys/gnu/dts/arm/sun8i-v3s-licheepi-zero.dts b/sys/gnu/dts/arm/sun8i-v3s-licheepi-zero.dts deleted file mode 100644 index 2e4587d26ce..00000000000 --- a/sys/gnu/dts/arm/sun8i-v3s-licheepi-zero.dts +++ /dev/null @@ -1,101 +0,0 @@ -/* - * Copyright (C) 2016 Icenowy Zheng - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun8i-v3s.dtsi" -#include "sunxi-common-regulators.dtsi" - -/ { - model = "Lichee Pi Zero"; - compatible = "licheepi,licheepi-zero", "allwinner,sun8i-v3s"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - blue_led { - label = "licheepi:blue:usr"; - gpios = <&pio 6 1 GPIO_ACTIVE_LOW>; /* PG1 */ - }; - - green_led { - label = "licheepi:green:usr"; - gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */ - default-state = "on"; - }; - - red_led { - label = "licheepi:red:usr"; - gpios = <&pio 6 2 GPIO_ACTIVE_LOW>; /* PG2 */ - }; - }; -}; - -&mmc0 { - broken-cd; - bus-width = <4>; - vmmc-supply = <®_vcc3v3>; - status = "okay"; -}; - -&uart0 { - pinctrl-0 = <&uart0_pb_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun8i-v3s.dtsi b/sys/gnu/dts/arm/sun8i-v3s.dtsi deleted file mode 100644 index 81ea50838cd..00000000000 --- a/sys/gnu/dts/arm/sun8i-v3s.dtsi +++ /dev/null @@ -1,432 +0,0 @@ -/* - * Copyright (C) 2016 Icenowy Zheng - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&gic>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <0>; - clocks = <&ccu CLK_CPU>; - }; - }; - - de: display-engine { - compatible = "allwinner,sun8i-v3s-display-engine"; - allwinner,pipelines = <&mixer0>; - status = "disabled"; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; - }; - - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - osc24M: osc24M_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-accuracy = <50000>; - clock-output-names = "osc24M"; - }; - - osc32k: osc32k_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - clock-accuracy = <50000>; - clock-output-names = "ext-osc32k"; - }; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - display_clocks: clock@1000000 { - compatible = "allwinner,sun8i-v3s-de2-clk"; - reg = <0x01000000 0x100000>; - clocks = <&ccu CLK_BUS_DE>, - <&ccu CLK_DE>; - clock-names = "bus", - "mod"; - resets = <&ccu RST_BUS_DE>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - mixer0: mixer@1100000 { - compatible = "allwinner,sun8i-v3s-de2-mixer"; - reg = <0x01100000 0x100000>; - clocks = <&display_clocks 0>, - <&display_clocks 6>; - clock-names = "bus", - "mod"; - resets = <&display_clocks 0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - mixer0_out: port@1 { - reg = <1>; - - mixer0_out_tcon0: endpoint { - remote-endpoint = <&tcon0_in_mixer0>; - }; - }; - }; - }; - - tcon0: lcd-controller@1c0c000 { - compatible = "allwinner,sun8i-v3s-tcon"; - reg = <0x01c0c000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_BUS_TCON0>, - <&ccu CLK_TCON0>; - clock-names = "ahb", - "tcon-ch0"; - clock-output-names = "tcon-pixel-clock"; - #clock-cells = <0>; - resets = <&ccu RST_BUS_TCON0>; - reset-names = "lcd"; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - tcon0_in: port@0 { - reg = <0>; - - tcon0_in_mixer0: endpoint { - remote-endpoint = <&mixer0_out_tcon0>; - }; - }; - - tcon0_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - }; - }; - - - mmc0: mmc@1c0f000 { - compatible = "allwinner,sun7i-a20-mmc"; - reg = <0x01c0f000 0x1000>; - clocks = <&ccu CLK_BUS_MMC0>, - <&ccu CLK_MMC0>, - <&ccu CLK_MMC0_OUTPUT>, - <&ccu CLK_MMC0_SAMPLE>; - clock-names = "ahb", - "mmc", - "output", - "sample"; - resets = <&ccu RST_BUS_MMC0>; - reset-names = "ahb"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc1: mmc@1c10000 { - compatible = "allwinner,sun7i-a20-mmc"; - reg = <0x01c10000 0x1000>; - clocks = <&ccu CLK_BUS_MMC1>, - <&ccu CLK_MMC1>, - <&ccu CLK_MMC1_OUTPUT>, - <&ccu CLK_MMC1_SAMPLE>; - clock-names = "ahb", - "mmc", - "output", - "sample"; - resets = <&ccu RST_BUS_MMC1>; - reset-names = "ahb"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc2: mmc@1c11000 { - compatible = "allwinner,sun7i-a20-mmc"; - reg = <0x01c11000 0x1000>; - clocks = <&ccu CLK_BUS_MMC2>, - <&ccu CLK_MMC2>, - <&ccu CLK_MMC2_OUTPUT>, - <&ccu CLK_MMC2_SAMPLE>; - clock-names = "ahb", - "mmc", - "output", - "sample"; - resets = <&ccu RST_BUS_MMC2>; - reset-names = "ahb"; - interrupts = ; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - usb_otg: usb@1c19000 { - compatible = "allwinner,sun8i-h3-musb"; - reg = <0x01c19000 0x0400>; - clocks = <&ccu CLK_BUS_OTG>; - resets = <&ccu RST_BUS_OTG>; - interrupts = ; - interrupt-names = "mc"; - phys = <&usbphy 0>; - phy-names = "usb"; - extcon = <&usbphy 0>; - status = "disabled"; - }; - - usbphy: phy@1c19400 { - compatible = "allwinner,sun8i-v3s-usb-phy"; - reg = <0x01c19400 0x2c>, - <0x01c1a800 0x4>; - reg-names = "phy_ctrl", - "pmu0"; - clocks = <&ccu CLK_USB_PHY0>; - clock-names = "usb0_phy"; - resets = <&ccu RST_USB_PHY0>; - reset-names = "usb0_reset"; - status = "disabled"; - #phy-cells = <1>; - }; - - ccu: clock@1c20000 { - compatible = "allwinner,sun8i-v3s-ccu"; - reg = <0x01c20000 0x400>; - clocks = <&osc24M>, <&rtc 0>; - clock-names = "hosc", "losc"; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - rtc: rtc@1c20400 { - #clock-cells = <1>; - compatible = "allwinner,sun8i-v3-rtc"; - reg = <0x01c20400 0x54>; - interrupts = , - ; - clocks = <&osc32k>; - clock-output-names = "osc32k", "osc32k-out"; - }; - - pio: pinctrl@1c20800 { - compatible = "allwinner,sun8i-v3s-pinctrl"; - reg = <0x01c20800 0x400>; - interrupts = , - ; - clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>; - clock-names = "apb", "hosc", "losc"; - gpio-controller; - #gpio-cells = <3>; - interrupt-controller; - #interrupt-cells = <3>; - - i2c0_pins: i2c0-pins { - pins = "PB6", "PB7"; - function = "i2c0"; - }; - - uart0_pb_pins: uart0-pb-pins { - pins = "PB8", "PB9"; - function = "uart0"; - }; - - mmc0_pins: mmc0-pins { - pins = "PF0", "PF1", "PF2", "PF3", - "PF4", "PF5"; - function = "mmc0"; - drive-strength = <30>; - bias-pull-up; - }; - - mmc1_pins: mmc1-pins { - pins = "PG0", "PG1", "PG2", "PG3", - "PG4", "PG5"; - function = "mmc1"; - drive-strength = <30>; - bias-pull-up; - }; - - spi0_pins: spi0-pins { - pins = "PC0", "PC1", "PC2", "PC3"; - function = "spi0"; - }; - }; - - timer@1c20c00 { - compatible = "allwinner,sun8i-v3s-timer"; - reg = <0x01c20c00 0xa0>; - interrupts = , - , - ; - clocks = <&osc24M>; - }; - - wdt0: watchdog@1c20ca0 { - compatible = "allwinner,sun6i-a31-wdt"; - reg = <0x01c20ca0 0x20>; - interrupts = ; - clocks = <&osc24M>; - }; - - lradc: lradc@1c22800 { - compatible = "allwinner,sun4i-a10-lradc-keys"; - reg = <0x01c22800 0x400>; - interrupts = ; - status = "disabled"; - }; - - uart0: serial@1c28000 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART0>; - resets = <&ccu RST_BUS_UART0>; - status = "disabled"; - }; - - uart1: serial@1c28400 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28400 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART1>; - resets = <&ccu RST_BUS_UART1>; - status = "disabled"; - }; - - uart2: serial@1c28800 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28800 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART2>; - resets = <&ccu RST_BUS_UART2>; - status = "disabled"; - }; - - i2c0: i2c@1c2ac00 { - compatible = "allwinner,sun6i-a31-i2c"; - reg = <0x01c2ac00 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_I2C0>; - resets = <&ccu RST_BUS_I2C0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c1: i2c@1c2b000 { - compatible = "allwinner,sun6i-a31-i2c"; - reg = <0x01c2b000 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_I2C1>; - resets = <&ccu RST_BUS_I2C1>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - spi0: spi@1c68000 { - compatible = "allwinner,sun8i-h3-spi"; - reg = <0x01c68000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; - clock-names = "ahb", "mod"; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins>; - resets = <&ccu RST_BUS_SPI0>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - gic: interrupt-controller@1c81000 { - compatible = "arm,gic-400"; - reg = <0x01c81000 0x1000>, - <0x01c82000 0x1000>, - <0x01c84000 0x2000>, - <0x01c86000 0x2000>; - interrupt-controller; - #interrupt-cells = <3>; - interrupts = ; - }; - }; -}; diff --git a/sys/gnu/dts/arm/sun8i-v40-bananapi-m2-berry.dts b/sys/gnu/dts/arm/sun8i-v40-bananapi-m2-berry.dts deleted file mode 100644 index 15c22b06fc4..00000000000 --- a/sys/gnu/dts/arm/sun8i-v40-bananapi-m2-berry.dts +++ /dev/null @@ -1,305 +0,0 @@ -/* - * Copyright (C) 2017 Icenowy Zheng - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun8i-r40.dtsi" - -#include - -/ { - model = "Banana Pi M2 Berry"; - compatible = "sinovoip,bpi-m2-berry", "allwinner,sun8i-r40"; - - aliases { - ethernet0 = &gmac; - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - pwr-led { - label = "bananapi:red:pwr"; - gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - user-led { - label = "bananapi:green:user"; - gpios = <&pio 7 21 GPIO_ACTIVE_HIGH>; - }; - }; - - reg_vcc5v0: vcc5v0 { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&pio 7 23 GPIO_ACTIVE_HIGH>; /* PH23 */ - enable-active-high; - }; - - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&pio 6 10 GPIO_ACTIVE_LOW>; /* PG10 WIFI_EN */ - clocks = <&ccu CLK_OUTA>; - clock-names = "ext_clock"; - }; -}; - -&ahci { - ahci-supply = <®_dldo4>; - phy-supply = <®_eldo3>; - status = "okay"; -}; - -&de { - status = "okay"; -}; - -&ehci1 { - /* Terminus Tech FE 1.1s 4-port USB 2.0 hub here */ - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_rgmii_pins>; - phy-handle = <&phy1>; - phy-mode = "rgmii"; - phy-supply = <®_dc1sw>; - status = "okay"; -}; - -&gmac_mdio { - phy1: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&i2c0 { - status = "okay"; - - axp22x: pmic@34 { - compatible = "x-powers,axp221"; - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -#include "axp22x.dtsi" - -&mmc0 { - vmmc-supply = <®_dcdc1>; - bus-width = <4>; - cd-gpios = <&pio 7 13 GPIO_ACTIVE_LOW>; /* PH13 */ - status = "okay"; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pg_pins>; - vmmc-supply = <®_dldo2>; - vqmmc-supply = <®_dldo1>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; -}; - -&pio { - pinctrl-names = "default"; - pinctrl-0 = <&clk_out_a_pin>; - vcc-pa-supply = <®_aldo2>; - vcc-pc-supply = <®_dcdc1>; - vcc-pd-supply = <®_dcdc1>; - vcc-pe-supply = <®_eldo1>; - vcc-pf-supply = <®_dcdc1>; - vcc-pg-supply = <®_dldo1>; -}; - -®_aldo2 { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-name = "vcc-pa"; -}; - -®_aldo3 { - regulator-always-on; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <3300000>; - regulator-name = "avcc"; -}; - -®_dc1sw { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-gmac-phy"; -}; - -®_dcdc1 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-3v0"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1300000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1300000>; - regulator-name = "vdd-sys"; -}; - -®_dcdc5 { - regulator-always-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vcc-dram"; -}; - -®_dldo1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi-io"; -}; - -/* - * Our WiFi chip needs both DLDO2 and DLDO3 to be powered at the same - * time, with the two being in sync, to be able to meet maximum power - * consumption during transmits. Since this is not really supported - * right now, just use the two as always on, and we will fix it later. - */ - -®_dldo2 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi"; -}; - -®_dldo3 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi-2"; -}; - -®_dldo4 { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-name = "vdd2v5-sata"; -}; - -®_eldo3 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-name = "vdd1v2-sata"; -}; - -&tcon_tv0 { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pg_pins>, <&uart3_rts_cts_pg_pins>; - uart-has-rtscts; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - clocks = <&ccu CLK_OUTA>; - clock-names = "lpo"; - vbat-supply = <®_dldo2>; - vddio-supply = <®_dldo1>; - device-wakeup-gpios = <&pio 6 11 GPIO_ACTIVE_HIGH>; /* PG11 */ - /* TODO host wake line connected to PMIC GPIO pins */ - shutdown-gpios = <&pio 7 12 GPIO_ACTIVE_HIGH>; /* PH12 */ - max-speed = <1500000>; - }; -}; - -&usbphy { - usb1_vbus-supply = <®_vcc5v0>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun9i-a80-cubieboard4.dts b/sys/gnu/dts/arm/sun9i-a80-cubieboard4.dts deleted file mode 100644 index d3b337b043a..00000000000 --- a/sys/gnu/dts/arm/sun9i-a80-cubieboard4.dts +++ /dev/null @@ -1,508 +0,0 @@ -/* - * Copyright 2015 Tyler Baker - * - * Tyler Baker - * Chen-Yu Tsai - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun9i-a80.dtsi" - -#include - -/ { - model = "Cubietech Cubieboard4"; - compatible = "cubietech,a80-cubieboard4", "allwinner,sun9i-a80"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - green { - label = "cubieboard4:green:usr"; - gpios = <&pio 7 17 GPIO_ACTIVE_HIGH>; /* PH17 */ - }; - - red { - label = "cubieboard4:red:usr"; - gpios = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */ - }; - }; - - vga-connector { - compatible = "vga-connector"; - label = "vga"; - ddc-i2c-bus = <&i2c3>; - - port { - vga_con_in: endpoint { - remote-endpoint = <&vga_dac_out>; - }; - }; - }; - - vga-dac { - compatible = "corpro,gm7123", "adi,adv7123", "dumb-vga-dac"; - vdd-supply = <®_dcdc1>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - vga_dac_in: endpoint { - remote-endpoint = <&tcon0_out_vga>; - }; - }; - - port@1 { - reg = <1>; - - vga_dac_out: endpoint { - remote-endpoint = <&vga_con_in>; - }; - }; - }; - }; - - wifi_pwrseq: wifi-pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&ac100_rtc 1>; - clock-names = "ext_clock"; - /* enables internal regulator and de-asserts reset */ - reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 WL-PMU-EN */ - }; -}; - -&de { - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_rgmii_pins>; - phy-handle = <&phy1>; - phy-mode = "rgmii"; - phy-supply = <®_cldo1>; - status = "okay"; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_pins>; - status = "okay"; -}; - -&mdio { - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; - vmmc-supply = <®_dcdc1>; - bus-width = <4>; - cd-gpios = <&pio 7 18 GPIO_ACTIVE_LOW>; /* PH18 */ - status = "okay"; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - vmmc-supply = <®_dldo1>; - vqmmc-supply = <®_cldo3>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; -}; - -&mmc1_pins { - bias-pull-up; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_8bit_pins>; - vmmc-supply = <®_dcdc1>; - bus-width = <8>; - non-removable; - cap-mmc-hw-reset; - status = "okay"; -}; - -&mmc2_8bit_pins { - /* Increase drive strength for DDR modes */ - drive-strength = <40>; -}; - -&osc32k { - /* osc32k input is from AC100 */ - clocks = <&ac100_rtc 0>; -}; - -&pio { - vcc-pa-supply = <®_ldo_io1>; - vcc-pb-supply = <®_aldo2>; - vcc-pc-supply = <®_dcdc1>; - vcc-pd-supply = <®_dc1sw>; - vcc-pe-supply = <®_eldo2>; - vcc-pf-supply = <®_dcdc1>; - vcc-pg-supply = <®_ldo_io0>; - vcc-ph-supply = <®_dcdc1>; -}; - -&r_ir { - status = "okay"; -}; - -&r_pio { - vcc-pl-supply = <®_dldo2>; - vcc-pm-supply = <®_eldo3>; -}; - -&r_rsb { - status = "okay"; - - axp809: pmic@3a3 { - reg = <0x3a3>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - - regulators { - reg_aldo1: aldo1 { - /* - * TODO: This should be handled by the - * USB PHY driver. - */ - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc33-usbh"; - }; - - reg_aldo2: aldo2 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc-pb-io-cam"; - }; - - aldo3 { - /* unused */ - }; - - reg_dc1sw: dc1sw { - regulator-name = "vcc-pd"; - }; - - reg_dc5ldo: dc5ldo { - regulator-always-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-cpus-09-usbh"; - }; - - reg_dcdc1: dcdc1 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-3v"; - }; - - reg_dcdc2: dcdc2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-gpu"; - }; - - reg_dcdc3: dcdc3 { - regulator-always-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-cpua"; - }; - - reg_dcdc4: dcdc4 { - regulator-always-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-sys-usb0-hdmi"; - }; - - reg_dcdc5: dcdc5 { - regulator-always-on; - regulator-min-microvolt = <1425000>; - regulator-max-microvolt = <1575000>; - regulator-name = "vcc-dram"; - }; - - reg_dldo1: dldo1 { - /* - * The WiFi chip supports a wide range - * (3.0 ~ 4.8V) of voltages, and so does - * this regulator (3.0 ~ 4.2V), but - * Allwinner SDK always sets it to 3.3V. - */ - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi"; - }; - - reg_dldo2: dldo2 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-pl"; - }; - - reg_eldo1: eldo1 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-name = "vcc-dvdd-cam"; - }; - - reg_eldo2: eldo2 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc-pe"; - }; - - reg_eldo3: eldo3 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-pm-codec-io1"; - }; - - reg_ldo_io0: ldo_io0 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-pg"; - }; - - reg_ldo_io1: ldo_io1 { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-name = "vcc-pa-gmac-2v5"; - }; - - reg_rtc_ldo: rtc_ldo { - regulator-name = "vcc-rtc-vdd1v8-io"; - }; - - sw { - /* unused */ - }; - }; - }; - - axp806: pmic@745 { - compatible = "x-powers,axp806"; - reg = <0x745>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells = <1>; - bldoin-supply = <®_dcdce>; - - regulators { - reg_s_aldo1: aldo1 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; - }; - - aldo2 { - /* - * unused, but use a different name to - * avoid name clash with axp809's aldo's - */ - regulator-name = "s_aldo2"; - }; - - aldo3 { - /* - * unused, but use a different name to - * avoid name clash with axp809's aldo's - */ - regulator-name = "s_aldo3"; - }; - - reg_bldo1: bldo1 { - regulator-always-on; - regulator-min-microvolt = <1700000>; - regulator-max-microvolt = <1900000>; - regulator-name = "vcc18-efuse-adc-display-csi"; - }; - - reg_bldo2: bldo2 { - regulator-always-on; - regulator-min-microvolt = <1700000>; - regulator-max-microvolt = <1900000>; - regulator-name = - "vdd18-drampll-vcc18-pll-cpvdd"; - }; - - bldo3 { - /* unused */ - }; - - reg_bldo4: bldo4 { - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1300000>; - regulator-name = "vcc12-hsic"; - }; - - reg_cldo1: cldo1 { - /* - * This was 3V in the original design, but - * 3.3V is the recommended supply voltage - * for the Ethernet PHY. - */ - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - /* - * The PHY requires 20ms after all voltages - * are applied until core logic is ready and - * 30ms after the reset pin is de-asserted. - * Set a 100ms delay to account for PMIC - * ramp time and board traces. - */ - regulator-enable-ramp-delay = <100000>; - regulator-name = "vcc-gmac-phy"; - }; - - reg_cldo2: cldo2 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-name = "afvcc-cam"; - }; - - reg_cldo3: cldo3 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-io-wifi-codec-io2"; - }; - - reg_dcdca: dcdca { - regulator-always-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-cpub"; - }; - - reg_dcdcd: dcdcd { - regulator-always-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-vpu"; - }; - - reg_dcdce: dcdce { - regulator-always-on; - regulator-min-microvolt = <2100000>; - regulator-max-microvolt = <2100000>; - regulator-name = "vcc-bldo-codec-ldoin"; - }; - - sw { - /* - * unused, but use a different name to - * avoid name clash with axp809's sw - */ - regulator-name = "s_sw"; - }; - }; - }; - - ac100: codec@e89 { - compatible = "x-powers,ac100"; - reg = <0xe89>; - - ac100_codec: codec { - compatible = "x-powers,ac100-codec"; - interrupt-parent = <&r_pio>; - interrupts = <0 9 IRQ_TYPE_LEVEL_LOW>; /* PL9 */ - #clock-cells = <0>; - clock-output-names = "4M_adda"; - }; - - ac100_rtc: rtc { - compatible = "x-powers,ac100-rtc"; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - clocks = <&ac100_codec>; - #clock-cells = <1>; - clock-output-names = "cko1_rtc", - "cko2_rtc", - "cko3_rtc"; - }; - }; -}; - -#include "axp809.dtsi" - -&tcon0 { - pinctrl-names = "default"; - pinctrl-0 = <&lcd0_rgb888_pins>; -}; - -&tcon0_out { - tcon0_out_vga: endpoint { - remote-endpoint = <&vga_dac_in>; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_ph_pins>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun9i-a80-optimus.dts b/sys/gnu/dts/arm/sun9i-a80-optimus.dts deleted file mode 100644 index bbc6335e563..00000000000 --- a/sys/gnu/dts/arm/sun9i-a80-optimus.dts +++ /dev/null @@ -1,510 +0,0 @@ -/* - * Copyright 2014 Chen-Yu Tsai - * - * Chen-Yu Tsai - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun9i-a80.dtsi" - -#include - -/ { - model = "Merrii A80 Optimus Board"; - compatible = "merrii,a80-optimus", "allwinner,sun9i-a80"; - - aliases { - serial0 = &uart0; - serial1 = &uart4; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - /* The LED names match those found on the board */ - led2 { - label = "optimus:led2:usr"; - gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; - }; - - led3 { - label = "optimus:led3:usr"; - gpios = <&r_pio 1 15 GPIO_ACTIVE_HIGH>; /* PM15 */ - }; - - led4 { - label = "optimus:led4:usr"; - gpios = <&pio 7 0 GPIO_ACTIVE_HIGH>; - }; - }; - - reg_usb1_vbus: usb1-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb1-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ - }; - - reg_usb3_vbus: usb3-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb3-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ - }; - - wifi_pwrseq: wifi-pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&ac100_rtc 1>; - clock-names = "ext_clock"; - /* enables internal regulator and de-asserts reset */ - reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 WL-PMU-EN */ - }; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - /* Enable if HSIC peripheral is connected */ - status = "disabled"; -}; - -&ehci2 { - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_rgmii_pins>; - phy-handle = <&phy1>; - phy-mode = "rgmii"; - phy-supply = <®_cldo1>; - status = "okay"; -}; - -&mdio { - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; - vmmc-supply = <®_dcdc1>; - bus-width = <4>; - cd-gpios = <&pio 7 18 GPIO_ACTIVE_LOW>; /* PH8 */ - status = "okay"; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - vmmc-supply = <®_dldo1>; - vqmmc-supply = <®_cldo3>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; -}; - -&mmc1_pins { - bias-pull-up; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_8bit_pins>; - vmmc-supply = <®_dcdc1>; - bus-width = <8>; - non-removable; - cap-mmc-hw-reset; - status = "okay"; -}; - -&mmc2_8bit_pins { - /* Increase drive strength for DDR modes */ - drive-strength = <40>; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci2 { - status = "okay"; -}; - -&osc32k { - /* osc32k input is from AC100 */ - clocks = <&ac100_rtc 0>; -}; - -&pio { - vcc-pa-supply = <®_ldo_io1>; - vcc-pb-supply = <®_aldo2>; - vcc-pc-supply = <®_dcdc1>; - vcc-pd-supply = <®_dcdc1>; - vcc-pe-supply = <®_eldo2>; - vcc-pf-supply = <®_dcdc1>; - vcc-pg-supply = <®_ldo_io0>; - vcc-ph-supply = <®_dcdc1>; -}; - -&r_ir { - status = "okay"; -}; - -&r_pio { - vcc-pl-supply = <®_dldo2>; - vcc-pm-supply = <®_eldo3>; -}; - -&r_rsb { - status = "okay"; - - axp809: pmic@3a3 { - reg = <0x3a3>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - - regulators { - reg_aldo1: aldo1 { - /* - * TODO: This should be handled by the - * USB PHY driver. - */ - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc33-usbh"; - }; - - reg_aldo2: aldo2 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc-pb-io-cam"; - }; - - aldo3 { - /* unused */ - }; - - reg_dc5ldo: dc5ldo { - regulator-always-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-cpus-09-usbh"; - }; - - dc1sw { - /* unused */ - }; - - reg_dcdc1: dcdc1 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-3v"; - }; - - reg_dcdc2: dcdc2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-gpu"; - }; - - reg_dcdc3: dcdc3 { - regulator-always-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-cpua"; - }; - - reg_dcdc4: dcdc4 { - regulator-always-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-sys-usb0-hdmi"; - }; - - reg_dcdc5: dcdc5 { - regulator-always-on; - regulator-min-microvolt = <1425000>; - regulator-max-microvolt = <1575000>; - regulator-name = "vcc-dram"; - }; - - reg_dldo1: dldo1 { - /* - * The WiFi chip supports a wide range - * (3.0 ~ 4.8V) of voltages, and so does - * this regulator (3.0 ~ 4.2V), but - * Allwinner SDK always sets it to 3.3V. - */ - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi"; - }; - - reg_dldo2: dldo2 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-pl"; - }; - - reg_eldo1: eldo1 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-name = "vcc-dvdd-cam"; - }; - - reg_eldo2: eldo2 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc-pe"; - }; - - reg_eldo3: eldo3 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-pm-codec-io1"; - }; - - reg_ldo_io0: ldo_io0 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-pg"; - }; - - reg_ldo_io1: ldo_io1 { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-name = "vcc-pa-gmac-2v5"; - }; - - reg_rtc_ldo: rtc_ldo { - regulator-name = "vcc-rtc-vdd1v8-io"; - }; - - sw { - /* unused */ - }; - }; - }; - - axp806: pmic@745 { - compatible = "x-powers,axp806"; - reg = <0x745>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells = <1>; - bldoin-supply = <®_dcdce>; - - regulators { - reg_s_aldo1: aldo1 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; - }; - - aldo2 { - /* - * unused, but use a different name to - * avoid name clash with axp809's aldo's - */ - regulator-name = "s_aldo2"; - }; - - aldo3 { - /* - * unused, but use a different name to - * avoid name clash with axp809's aldo's - */ - regulator-name = "s_aldo3"; - }; - - reg_bldo1: bldo1 { - regulator-always-on; - regulator-min-microvolt = <1700000>; - regulator-max-microvolt = <1900000>; - regulator-name = "vcc18-efuse-adc-display-csi"; - }; - - reg_bldo2: bldo2 { - regulator-always-on; - regulator-min-microvolt = <1700000>; - regulator-max-microvolt = <1900000>; - regulator-name = - "vdd18-drampll-vcc18-pll-cpvdd"; - }; - - bldo3 { - /* unused */ - }; - - reg_bldo4: bldo4 { - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1300000>; - regulator-name = "vcc12-hsic"; - }; - - reg_cldo1: cldo1 { - /* - * This was 3V in the original design, but - * 3.3V is the recommended supply voltage - * for the Ethernet PHY. - */ - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - /* - * The PHY requires 20ms after all voltages - * are applied until core logic is ready and - * 30ms after the reset pin is de-asserted. - * Set a 100ms delay to account for PMIC - * ramp time and board traces. - */ - regulator-enable-ramp-delay = <100000>; - regulator-name = "vcc-gmac-phy"; - }; - - reg_cldo2: cldo2 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-name = "afvcc-cam"; - }; - - reg_cldo3: cldo3 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-io-wifi-codec-io2"; - }; - - reg_dcdca: dcdca { - regulator-always-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-cpub"; - }; - - reg_dcdcd: dcdcd { - regulator-always-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-vpu"; - }; - - reg_dcdce: dcdce { - regulator-always-on; - regulator-min-microvolt = <2100000>; - regulator-max-microvolt = <2100000>; - regulator-name = "vcc-bldo-codec-ldoin"; - }; - - sw { - /* - * unused, but use a different name to - * avoid name clash with axp809's sw - */ - regulator-name = "s_sw"; - }; - }; - }; - - ac100: codec@e89 { - compatible = "x-powers,ac100"; - reg = <0xe89>; - - ac100_codec: codec { - compatible = "x-powers,ac100-codec"; - interrupt-parent = <&r_pio>; - interrupts = <0 9 IRQ_TYPE_LEVEL_LOW>; /* PL9 */ - #clock-cells = <0>; - clock-output-names = "4M_adda"; - }; - - ac100_rtc: rtc { - compatible = "x-powers,ac100-rtc"; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - clocks = <&ac100_codec>; - #clock-cells = <1>; - clock-output-names = "cko1_rtc", - "cko2_rtc", - "cko3_rtc"; - }; - }; -}; - -#include "axp809.dtsi" - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_ph_pins>; - status = "okay"; -}; - -&usbphy1 { - phy-supply = <®_usb1_vbus>; - status = "okay"; -}; - -&usbphy2 { - phy-supply = <®_bldo4>; - /* Enable if HSIC peripheral is connected */ - status = "disabled"; -}; - -&usbphy3 { - phy-supply = <®_usb3_vbus>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sun9i-a80.dtsi b/sys/gnu/dts/arm/sun9i-a80.dtsi deleted file mode 100644 index ce4fa6706d0..00000000000 --- a/sys/gnu/dts/arm/sun9i-a80.dtsi +++ /dev/null @@ -1,1254 +0,0 @@ -/* - * Copyright 2014 Chen-Yu Tsai - * - * Chen-Yu Tsai - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include - -#include -#include -#include -#include -#include -#include - -/ { - #address-cells = <2>; - #size-cells = <2>; - interrupt-parent = <&gic>; - - aliases { - ethernet0 = &gmac; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - cci-control-port = <&cci_control0>; - clock-frequency = <12000000>; - enable-method = "allwinner,sun9i-a80-smp"; - reg = <0x0>; - }; - - cpu1: cpu@1 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - cci-control-port = <&cci_control0>; - clock-frequency = <12000000>; - enable-method = "allwinner,sun9i-a80-smp"; - reg = <0x1>; - }; - - cpu2: cpu@2 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - cci-control-port = <&cci_control0>; - clock-frequency = <12000000>; - enable-method = "allwinner,sun9i-a80-smp"; - reg = <0x2>; - }; - - cpu3: cpu@3 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - cci-control-port = <&cci_control0>; - clock-frequency = <12000000>; - enable-method = "allwinner,sun9i-a80-smp"; - reg = <0x3>; - }; - - cpu4: cpu@100 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - cci-control-port = <&cci_control1>; - clock-frequency = <18000000>; - enable-method = "allwinner,sun9i-a80-smp"; - reg = <0x100>; - }; - - cpu5: cpu@101 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - cci-control-port = <&cci_control1>; - clock-frequency = <18000000>; - enable-method = "allwinner,sun9i-a80-smp"; - reg = <0x101>; - }; - - cpu6: cpu@102 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - cci-control-port = <&cci_control1>; - clock-frequency = <18000000>; - enable-method = "allwinner,sun9i-a80-smp"; - reg = <0x102>; - }; - - cpu7: cpu@103 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - cci-control-port = <&cci_control1>; - clock-frequency = <18000000>; - enable-method = "allwinner,sun9i-a80-smp"; - reg = <0x103>; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; - clock-frequency = <24000000>; - arm,cpu-registers-not-fw-configured; - }; - - clocks { - #address-cells = <1>; - #size-cells = <1>; - /* - * map 64 bit address range down to 32 bits, - * as the peripherals are all under 512MB. - */ - ranges = <0 0 0 0x20000000>; - - /* - * This clock is actually configurable from the PRCM address - * space. The external 24M oscillator can be turned off, and - * the clock switched to an internal 16M RC oscillator. Under - * normal operation there's no reason to do this, and the - * default is to use the external good one, so just model this - * as a fixed clock. Also it is not entirely clear if the - * osc24M mux in the PRCM affects the entire clock tree, which - * would also throw all the PLL clock rates off, or just the - * downstream clocks in the PRCM. - */ - osc24M: clk-24M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "osc24M"; - }; - - /* - * The 32k clock is from an external source, normally the - * AC100 codec/RTC chip. This serves as a placeholder for - * board dts files to specify the source. - */ - osc32k: clk-32k { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clock-output-names = "osc32k"; - }; - - /* - * The following two are dummy clocks, placeholders - * used in the gmac_tx clock. The gmac driver will - * choose one parent depending on the PHY interface - * mode, using clk_set_rate auto-reparenting. - * - * The actual TX clock rate is not controlled by the - * gmac_tx clock. - */ - mii_phy_tx_clk: mii_phy_tx_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <25000000>; - clock-output-names = "mii_phy_tx"; - }; - - gmac_int_tx_clk: gmac_int_tx_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "gmac_int_tx"; - }; - - gmac_tx_clk: clk@800030 { - #clock-cells = <0>; - compatible = "allwinner,sun7i-a20-gmac-clk"; - reg = <0x00800030 0x4>; - clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>; - clock-output-names = "gmac_tx"; - }; - - cpus_clk: clk@8001410 { - compatible = "allwinner,sun9i-a80-cpus-clk"; - reg = <0x08001410 0x4>; - #clock-cells = <0>; - clocks = <&osc32k>, <&osc24M>, - <&ccu CLK_PLL_PERIPH0>, - <&ccu CLK_PLL_AUDIO>; - clock-output-names = "cpus"; - }; - - ahbs: clk-ahbs { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clock-div = <1>; - clock-mult = <1>; - clocks = <&cpus_clk>; - clock-output-names = "ahbs"; - }; - - apbs: clk@800141c { - compatible = "allwinner,sun8i-a23-apb0-clk"; - reg = <0x0800141c 0x4>; - #clock-cells = <0>; - clocks = <&ahbs>; - clock-output-names = "apbs"; - }; - - apbs_gates: clk@8001428 { - compatible = "allwinner,sun9i-a80-apbs-gates-clk"; - reg = <0x08001428 0x4>; - #clock-cells = <1>; - clocks = <&apbs>; - clock-indices = <0>, <1>, - <2>, <3>, - <4>, <5>, - <6>, <7>, - <12>, <13>, - <16>, <17>, - <18>, <20>; - clock-output-names = "apbs_pio", "apbs_ir", - "apbs_timer", "apbs_rsb", - "apbs_uart", "apbs_1wire", - "apbs_i2c0", "apbs_i2c1", - "apbs_ps2_0", "apbs_ps2_1", - "apbs_dma", "apbs_i2s0", - "apbs_i2s1", "apbs_twd"; - }; - - r_1wire_clk: clk@8001450 { - reg = <0x08001450 0x4>; - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - clocks = <&osc32k>, <&osc24M>; - clock-output-names = "r_1wire"; - }; - - r_ir_clk: clk@8001454 { - reg = <0x08001454 0x4>; - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - clocks = <&osc32k>, <&osc24M>; - clock-output-names = "r_ir"; - }; - }; - - de: display-engine { - compatible = "allwinner,sun9i-a80-display-engine"; - allwinner,pipelines = <&fe0>, <&fe1>; - status = "disabled"; - }; - - soc@20000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - /* - * map 64 bit address range down to 32 bits, - * as the peripherals are all under 512MB. - */ - ranges = <0 0 0 0x20000000>; - - sram_b: sram@20000 { - /* 256 KiB secure SRAM at 0x20000 */ - compatible = "mmio-sram"; - reg = <0x00020000 0x40000>; - - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x00020000 0x40000>; - - smp-sram@1000 { - /* - * This is checked by BROM to determine if - * cpu0 should jump to SMP entry vector - */ - compatible = "allwinner,sun9i-a80-smp-sram"; - reg = <0x1000 0x8>; - }; - }; - - gmac: ethernet@830000 { - compatible = "allwinner,sun7i-a20-gmac"; - reg = <0x00830000 0x1054>; - interrupts = ; - interrupt-names = "macirq"; - clocks = <&ccu CLK_BUS_GMAC>, <&gmac_tx_clk>; - clock-names = "stmmaceth", "allwinner_gmac_tx"; - resets = <&ccu RST_BUS_GMAC>; - reset-names = "stmmaceth"; - snps,pbl = <2>; - snps,fixed-burst; - snps,force_sf_dma_mode; - status = "disabled"; - - mdio: mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - ehci0: usb@a00000 { - compatible = "allwinner,sun9i-a80-ehci", "generic-ehci"; - reg = <0x00a00000 0x100>; - interrupts = ; - clocks = <&usb_clocks CLK_BUS_HCI0>; - resets = <&usb_clocks RST_USB0_HCI>; - phys = <&usbphy1>; - phy-names = "usb"; - status = "disabled"; - }; - - ohci0: usb@a00400 { - compatible = "allwinner,sun9i-a80-ohci", "generic-ohci"; - reg = <0x00a00400 0x100>; - interrupts = ; - clocks = <&usb_clocks CLK_BUS_HCI0>, - <&usb_clocks CLK_USB_OHCI0>; - resets = <&usb_clocks RST_USB0_HCI>; - phys = <&usbphy1>; - phy-names = "usb"; - status = "disabled"; - }; - - usbphy1: phy@a00800 { - compatible = "allwinner,sun9i-a80-usb-phy"; - reg = <0x00a00800 0x4>; - clocks = <&usb_clocks CLK_USB0_PHY>; - clock-names = "phy"; - resets = <&usb_clocks RST_USB0_PHY>; - reset-names = "phy"; - status = "disabled"; - #phy-cells = <0>; - }; - - ehci1: usb@a01000 { - compatible = "allwinner,sun9i-a80-ehci", "generic-ehci"; - reg = <0x00a01000 0x100>; - interrupts = ; - clocks = <&usb_clocks CLK_BUS_HCI1>; - resets = <&usb_clocks RST_USB1_HCI>; - phys = <&usbphy2>; - phy-names = "usb"; - status = "disabled"; - }; - - usbphy2: phy@a01800 { - compatible = "allwinner,sun9i-a80-usb-phy"; - reg = <0x00a01800 0x4>; - clocks = <&usb_clocks CLK_USB1_PHY>, - <&usb_clocks CLK_USB_HSIC>, - <&usb_clocks CLK_USB1_HSIC>; - clock-names = "phy", - "hsic_12M", - "hsic_480M"; - resets = <&usb_clocks RST_USB1_PHY>, - <&usb_clocks RST_USB1_HSIC>; - reset-names = "phy", - "hsic"; - status = "disabled"; - #phy-cells = <0>; - /* usb1 is always used with HSIC */ - phy_type = "hsic"; - }; - - ehci2: usb@a02000 { - compatible = "allwinner,sun9i-a80-ehci", "generic-ehci"; - reg = <0x00a02000 0x100>; - interrupts = ; - clocks = <&usb_clocks CLK_BUS_HCI2>; - resets = <&usb_clocks RST_USB2_HCI>; - phys = <&usbphy3>; - phy-names = "usb"; - status = "disabled"; - }; - - ohci2: usb@a02400 { - compatible = "allwinner,sun9i-a80-ohci", "generic-ohci"; - reg = <0x00a02400 0x100>; - interrupts = ; - clocks = <&usb_clocks CLK_BUS_HCI2>, - <&usb_clocks CLK_USB_OHCI2>; - resets = <&usb_clocks RST_USB2_HCI>; - phys = <&usbphy3>; - phy-names = "usb"; - status = "disabled"; - }; - - usbphy3: phy@a02800 { - compatible = "allwinner,sun9i-a80-usb-phy"; - reg = <0x00a02800 0x4>; - clocks = <&usb_clocks CLK_USB2_PHY>, - <&usb_clocks CLK_USB_HSIC>, - <&usb_clocks CLK_USB2_HSIC>; - clock-names = "phy", - "hsic_12M", - "hsic_480M"; - resets = <&usb_clocks RST_USB2_PHY>, - <&usb_clocks RST_USB2_HSIC>; - reset-names = "phy", - "hsic"; - status = "disabled"; - #phy-cells = <0>; - }; - - usb_clocks: clock@a08000 { - compatible = "allwinner,sun9i-a80-usb-clks"; - reg = <0x00a08000 0x8>; - clocks = <&ccu CLK_BUS_USB>, <&osc24M>; - clock-names = "bus", "hosc"; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - cpucfg@1700000 { - compatible = "allwinner,sun9i-a80-cpucfg"; - reg = <0x01700000 0x100>; - }; - - crypto: crypto@1c02000 { - compatible = "allwinner,sun9i-a80-crypto"; - reg = <0x01c02000 0x1000>; - interrupts = ; - resets = <&ccu RST_BUS_SS>; - clocks = <&ccu CLK_BUS_SS>, <&ccu CLK_SS>; - clock-names = "bus", "mod"; - }; - - mmc0: mmc@1c0f000 { - compatible = "allwinner,sun9i-a80-mmc"; - reg = <0x01c0f000 0x1000>; - clocks = <&mmc_config_clk 0>, <&ccu CLK_MMC0>, - <&ccu CLK_MMC0_OUTPUT>, - <&ccu CLK_MMC0_SAMPLE>; - clock-names = "ahb", "mmc", "output", "sample"; - resets = <&mmc_config_clk 0>; - reset-names = "ahb"; - interrupts = ; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc1: mmc@1c10000 { - compatible = "allwinner,sun9i-a80-mmc"; - reg = <0x01c10000 0x1000>; - clocks = <&mmc_config_clk 1>, <&ccu CLK_MMC1>, - <&ccu CLK_MMC1_OUTPUT>, - <&ccu CLK_MMC1_SAMPLE>; - clock-names = "ahb", "mmc", "output", "sample"; - resets = <&mmc_config_clk 1>; - reset-names = "ahb"; - interrupts = ; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc2: mmc@1c11000 { - compatible = "allwinner,sun9i-a80-mmc"; - reg = <0x01c11000 0x1000>; - clocks = <&mmc_config_clk 2>, <&ccu CLK_MMC2>, - <&ccu CLK_MMC2_OUTPUT>, - <&ccu CLK_MMC2_SAMPLE>; - clock-names = "ahb", "mmc", "output", "sample"; - resets = <&mmc_config_clk 2>; - reset-names = "ahb"; - interrupts = ; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc3: mmc@1c12000 { - compatible = "allwinner,sun9i-a80-mmc"; - reg = <0x01c12000 0x1000>; - clocks = <&mmc_config_clk 3>, <&ccu CLK_MMC3>, - <&ccu CLK_MMC3_OUTPUT>, - <&ccu CLK_MMC3_SAMPLE>; - clock-names = "ahb", "mmc", "output", "sample"; - resets = <&mmc_config_clk 3>; - reset-names = "ahb"; - interrupts = ; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc_config_clk: clk@1c13000 { - compatible = "allwinner,sun9i-a80-mmc-config-clk"; - reg = <0x01c13000 0x10>; - clocks = <&ccu CLK_BUS_MMC>; - resets = <&ccu RST_BUS_MMC>; - #clock-cells = <1>; - #reset-cells = <1>; - clock-output-names = "mmc0_config", "mmc1_config", - "mmc2_config", "mmc3_config"; - }; - - gic: interrupt-controller@1c41000 { - compatible = "arm,gic-400"; - reg = <0x01c41000 0x1000>, - <0x01c42000 0x2000>, - <0x01c44000 0x2000>, - <0x01c46000 0x2000>; - interrupt-controller; - #interrupt-cells = <3>; - interrupts = ; - }; - - cci: cci@1c90000 { - compatible = "arm,cci-400"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x01c90000 0x1000>; - ranges = <0x0 0x01c90000 0x10000>; - - cci_control0: slave-if@4000 { - compatible = "arm,cci-400-ctrl-if"; - interface-type = "ace"; - reg = <0x4000 0x1000>; - }; - - cci_control1: slave-if@5000 { - compatible = "arm,cci-400-ctrl-if"; - interface-type = "ace"; - reg = <0x5000 0x1000>; - }; - - pmu@9000 { - compatible = "arm,cci-400-pmu,r1"; - reg = <0x9000 0x5000>; - interrupts = , - , - , - , - ; - }; - }; - - de_clocks: clock@3000000 { - compatible = "allwinner,sun9i-a80-de-clks"; - reg = <0x03000000 0x30>; - clocks = <&ccu CLK_DE>, - <&ccu CLK_SDRAM>, - <&ccu CLK_BUS_DE>; - clock-names = "mod", - "dram", - "bus"; - resets = <&ccu RST_BUS_DE>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - fe0: display-frontend@3100000 { - compatible = "allwinner,sun9i-a80-display-frontend"; - reg = <0x03100000 0x40000>; - interrupts = ; - clocks = <&de_clocks CLK_BUS_FE0>, <&de_clocks CLK_FE0>, - <&de_clocks CLK_DRAM_FE0>; - clock-names = "ahb", "mod", - "ram"; - resets = <&de_clocks RST_FE0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - fe0_out: port@1 { - reg = <1>; - - fe0_out_deu0: endpoint { - remote-endpoint = <&deu0_in_fe0>; - }; - }; - }; - }; - - fe1: display-frontend@3140000 { - compatible = "allwinner,sun9i-a80-display-frontend"; - reg = <0x03140000 0x40000>; - interrupts = ; - clocks = <&de_clocks CLK_BUS_FE1>, <&de_clocks CLK_FE1>, - <&de_clocks CLK_DRAM_FE1>; - clock-names = "ahb", "mod", - "ram"; - resets = <&de_clocks RST_FE0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - fe1_out: port@1 { - reg = <1>; - - fe1_out_deu1: endpoint { - remote-endpoint = <&deu1_in_fe1>; - }; - }; - }; - }; - - be0: display-backend@3200000 { - compatible = "allwinner,sun9i-a80-display-backend"; - reg = <0x03200000 0x40000>; - interrupts = ; - clocks = <&de_clocks CLK_BUS_BE0>, <&de_clocks CLK_BE0>, - <&de_clocks CLK_DRAM_BE0>; - clock-names = "ahb", "mod", - "ram"; - resets = <&de_clocks RST_BE0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - be0_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - be0_in_deu0: endpoint@0 { - reg = <0>; - remote-endpoint = <&deu0_out_be0>; - }; - - be0_in_deu1: endpoint@1 { - reg = <1>; - remote-endpoint = <&deu1_out_be0>; - }; - }; - - be0_out: port@1 { - reg = <1>; - - be0_out_drc0: endpoint { - remote-endpoint = <&drc0_in_be0>; - }; - }; - }; - }; - - be1: display-backend@3240000 { - compatible = "allwinner,sun9i-a80-display-backend"; - reg = <0x03240000 0x40000>; - interrupts = ; - clocks = <&de_clocks CLK_BUS_BE1>, <&de_clocks CLK_BE1>, - <&de_clocks CLK_DRAM_BE1>; - clock-names = "ahb", "mod", - "ram"; - resets = <&de_clocks RST_BE1>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - be1_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - be1_in_deu0: endpoint@0 { - reg = <0>; - remote-endpoint = <&deu0_out_be1>; - }; - - be1_in_deu1: endpoint@1 { - reg = <1>; - remote-endpoint = <&deu1_out_be1>; - }; - }; - - be1_out: port@1 { - reg = <1>; - - be1_out_drc1: endpoint { - remote-endpoint = <&drc1_in_be1>; - }; - }; - }; - }; - - deu0: deu@3300000 { - compatible = "allwinner,sun9i-a80-deu"; - reg = <0x03300000 0x40000>; - interrupts = ; - clocks = <&de_clocks CLK_BUS_DEU0>, - <&de_clocks CLK_IEP_DEU0>, - <&de_clocks CLK_DRAM_DEU0>; - clock-names = "ahb", - "mod", - "ram"; - resets = <&de_clocks RST_DEU0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - deu0_in: port@0 { - reg = <0>; - - deu0_in_fe0: endpoint { - remote-endpoint = <&fe0_out_deu0>; - }; - }; - - deu0_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - deu0_out_be0: endpoint@0 { - reg = <0>; - remote-endpoint = <&be0_in_deu0>; - }; - - deu0_out_be1: endpoint@1 { - reg = <1>; - remote-endpoint = <&be1_in_deu0>; - }; - }; - }; - }; - - deu1: deu@3340000 { - compatible = "allwinner,sun9i-a80-deu"; - reg = <0x03340000 0x40000>; - interrupts = ; - clocks = <&de_clocks CLK_BUS_DEU1>, - <&de_clocks CLK_IEP_DEU1>, - <&de_clocks CLK_DRAM_DEU1>; - clock-names = "ahb", - "mod", - "ram"; - resets = <&de_clocks RST_DEU1>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - deu1_in: port@0 { - reg = <0>; - - deu1_in_fe1: endpoint { - remote-endpoint = <&fe1_out_deu1>; - }; - }; - - deu1_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - deu1_out_be0: endpoint@0 { - reg = <0>; - remote-endpoint = <&be0_in_deu1>; - }; - - deu1_out_be1: endpoint@1 { - reg = <1>; - remote-endpoint = <&be1_in_deu1>; - }; - }; - }; - }; - - drc0: drc@3400000 { - compatible = "allwinner,sun9i-a80-drc"; - reg = <0x03400000 0x40000>; - interrupts = ; - clocks = <&de_clocks CLK_BUS_DRC0>, - <&de_clocks CLK_IEP_DRC0>, - <&de_clocks CLK_DRAM_DRC0>; - clock-names = "ahb", - "mod", - "ram"; - resets = <&de_clocks RST_DRC0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - drc0_in: port@0 { - reg = <0>; - - drc0_in_be0: endpoint { - remote-endpoint = <&be0_out_drc0>; - }; - }; - - drc0_out: port@1 { - reg = <1>; - - drc0_out_tcon0: endpoint { - remote-endpoint = <&tcon0_in_drc0>; - }; - }; - }; - }; - - drc1: drc@3440000 { - compatible = "allwinner,sun9i-a80-drc"; - reg = <0x03440000 0x40000>; - interrupts = ; - clocks = <&de_clocks CLK_BUS_DRC1>, - <&de_clocks CLK_IEP_DRC1>, - <&de_clocks CLK_DRAM_DRC1>; - clock-names = "ahb", - "mod", - "ram"; - resets = <&de_clocks RST_DRC1>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - drc1_in: port@0 { - reg = <0>; - - drc1_in_be1: endpoint { - remote-endpoint = <&be1_out_drc1>; - }; - }; - - drc1_out: port@1 { - reg = <1>; - - drc1_out_tcon1: endpoint { - remote-endpoint = <&tcon1_in_drc1>; - }; - }; - }; - }; - - tcon0: lcd-controller@3c00000 { - compatible = "allwinner,sun9i-a80-tcon-lcd"; - reg = <0x03c00000 0x10000>; - interrupts = ; - clocks = <&ccu CLK_BUS_LCD0>, <&ccu CLK_LCD0>; - clock-names = "ahb", "tcon-ch0"; - resets = <&ccu RST_BUS_LCD0>, - <&ccu RST_BUS_EDP>, - <&ccu RST_BUS_LVDS>; - reset-names = "lcd", - "edp", - "lvds"; - clock-output-names = "tcon0-pixel-clock"; - #clock-cells = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - tcon0_in: port@0 { - reg = <0>; - - tcon0_in_drc0: endpoint { - remote-endpoint = <&drc0_out_tcon0>; - }; - }; - - tcon0_out: port@1 { - reg = <1>; - }; - }; - }; - - tcon1: lcd-controller@3c10000 { - compatible = "allwinner,sun9i-a80-tcon-tv"; - reg = <0x03c10000 0x10000>; - interrupts = ; - clocks = <&ccu CLK_BUS_LCD1>, <&ccu CLK_LCD1>; - clock-names = "ahb", "tcon-ch1"; - resets = <&ccu RST_BUS_LCD1>, <&ccu RST_BUS_EDP>; - reset-names = "lcd", "edp"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - tcon1_in: port@0 { - reg = <0>; - - tcon1_in_drc1: endpoint { - remote-endpoint = <&drc1_out_tcon1>; - }; - }; - - tcon1_out: port@1 { - reg = <1>; - }; - }; - }; - - ccu: clock@6000000 { - compatible = "allwinner,sun9i-a80-ccu"; - reg = <0x06000000 0x800>; - clocks = <&osc24M>, <&osc32k>; - clock-names = "hosc", "losc"; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - timer@6000c00 { - compatible = "allwinner,sun4i-a10-timer"; - reg = <0x06000c00 0xa0>; - interrupts = , - , - , - , - , - ; - - clocks = <&osc24M>; - }; - - wdt: watchdog@6000ca0 { - compatible = "allwinner,sun6i-a31-wdt"; - reg = <0x06000ca0 0x20>; - interrupts = ; - clocks = <&osc24M>; - }; - - pio: pinctrl@6000800 { - compatible = "allwinner,sun9i-a80-pinctrl"; - reg = <0x06000800 0x400>; - interrupts = , - , - , - , - ; - clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>; - clock-names = "apb", "hosc", "losc"; - gpio-controller; - interrupt-controller; - #interrupt-cells = <3>; - #gpio-cells = <3>; - - gmac_rgmii_pins: gmac-rgmii-pins { - pins = "PA0", "PA1", "PA2", "PA3", "PA4", "PA5", - "PA7", "PA8", "PA9", "PA10", "PA12", - "PA13", "PA15", "PA16", "PA17"; - function = "gmac"; - /* - * data lines in RGMII mode use DDR mode - * and need a higher signal drive strength - */ - drive-strength = <40>; - }; - - i2c3_pins: i2c3-pins { - pins = "PG10", "PG11"; - function = "i2c3"; - }; - - lcd0_rgb888_pins: lcd0-rgb888-pins { - pins = "PD0", "PD1", "PD2", "PD3", - "PD4", "PD5", "PD6", "PD7", - "PD8", "PD9", "PD10", "PD11", - "PD12", "PD13", "PD14", "PD15", - "PD16", "PD17", "PD18", "PD19", - "PD20", "PD21", "PD22", "PD23", - "PD24", "PD25", "PD26", "PD27"; - function = "lcd0"; - }; - - mmc0_pins: mmc0-pins { - pins = "PF0", "PF1" ,"PF2", "PF3", - "PF4", "PF5"; - function = "mmc0"; - drive-strength = <30>; - bias-pull-up; - }; - - mmc1_pins: mmc1-pins { - pins = "PG0", "PG1" ,"PG2", "PG3", - "PG4", "PG5"; - function = "mmc1"; - drive-strength = <30>; - bias-pull-up; - }; - - mmc2_8bit_pins: mmc2-8bit-pins { - pins = "PC6", "PC7", "PC8", "PC9", - "PC10", "PC11", "PC12", - "PC13", "PC14", "PC15", - "PC16"; - function = "mmc2"; - drive-strength = <30>; - bias-pull-up; - }; - - uart0_ph_pins: uart0-ph-pins { - pins = "PH12", "PH13"; - function = "uart0"; - }; - - uart4_pins: uart4-pins { - pins = "PG12", "PG13", "PG14", "PG15"; - function = "uart4"; - }; - }; - - uart0: serial@7000000 { - compatible = "snps,dw-apb-uart"; - reg = <0x07000000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART0>; - resets = <&ccu RST_BUS_UART0>; - status = "disabled"; - }; - - uart1: serial@7000400 { - compatible = "snps,dw-apb-uart"; - reg = <0x07000400 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART1>; - resets = <&ccu RST_BUS_UART1>; - status = "disabled"; - }; - - uart2: serial@7000800 { - compatible = "snps,dw-apb-uart"; - reg = <0x07000800 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART2>; - resets = <&ccu RST_BUS_UART2>; - status = "disabled"; - }; - - uart3: serial@7000c00 { - compatible = "snps,dw-apb-uart"; - reg = <0x07000c00 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART3>; - resets = <&ccu RST_BUS_UART3>; - status = "disabled"; - }; - - uart4: serial@7001000 { - compatible = "snps,dw-apb-uart"; - reg = <0x07001000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART4>; - resets = <&ccu RST_BUS_UART4>; - status = "disabled"; - }; - - uart5: serial@7001400 { - compatible = "snps,dw-apb-uart"; - reg = <0x07001400 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART5>; - resets = <&ccu RST_BUS_UART5>; - status = "disabled"; - }; - - i2c0: i2c@7002800 { - compatible = "allwinner,sun6i-a31-i2c"; - reg = <0x07002800 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_I2C0>; - resets = <&ccu RST_BUS_I2C0>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c1: i2c@7002c00 { - compatible = "allwinner,sun6i-a31-i2c"; - reg = <0x07002c00 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_I2C1>; - resets = <&ccu RST_BUS_I2C1>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c2: i2c@7003000 { - compatible = "allwinner,sun6i-a31-i2c"; - reg = <0x07003000 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_I2C2>; - resets = <&ccu RST_BUS_I2C2>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c3: i2c@7003400 { - compatible = "allwinner,sun6i-a31-i2c"; - reg = <0x07003400 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_I2C3>; - resets = <&ccu RST_BUS_I2C3>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c4: i2c@7003800 { - compatible = "allwinner,sun6i-a31-i2c"; - reg = <0x07003800 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_I2C4>; - resets = <&ccu RST_BUS_I2C4>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - r_wdt: watchdog@8001000 { - compatible = "allwinner,sun6i-a31-wdt"; - reg = <0x08001000 0x20>; - interrupts = ; - clocks = <&osc24M>; - }; - - prcm@8001400 { - compatible = "allwinner,sun9i-a80-prcm"; - reg = <0x08001400 0x200>; - }; - - apbs_rst: reset@80014b0 { - reg = <0x080014b0 0x4>; - compatible = "allwinner,sun6i-a31-clock-reset"; - #reset-cells = <1>; - }; - - nmi_intc: interrupt-controller@80015a0 { - compatible = "allwinner,sun9i-a80-nmi"; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x080015a0 0xc>; - interrupts = ; - }; - - r_ir: ir@8002000 { - compatible = "allwinner,sun6i-a31-ir"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&r_ir_pins>; - clocks = <&apbs_gates 1>, <&r_ir_clk>; - clock-names = "apb", "ir"; - resets = <&apbs_rst 1>; - reg = <0x08002000 0x40>; - status = "disabled"; - }; - - r_uart: serial@8002800 { - compatible = "snps,dw-apb-uart"; - reg = <0x08002800 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&apbs_gates 4>; - resets = <&apbs_rst 4>; - status = "disabled"; - }; - - r_pio: pinctrl@8002c00 { - compatible = "allwinner,sun9i-a80-r-pinctrl"; - reg = <0x08002c00 0x400>; - interrupts = , - ; - clocks = <&apbs_gates 0>, <&osc24M>, <&osc32k>; - clock-names = "apb", "hosc", "losc"; - resets = <&apbs_rst 0>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <3>; - #gpio-cells = <3>; - - r_ir_pins: r-ir-pins { - pins = "PL6"; - function = "s_cir_rx"; - }; - - r_rsb_pins: r-rsb-pins { - pins = "PN0", "PN1"; - function = "s_rsb"; - drive-strength = <20>; - bias-pull-up; - }; - }; - - r_rsb: rsb@8003400 { - compatible = "allwinner,sun8i-a23-rsb"; - reg = <0x08003400 0x400>; - interrupts = ; - clocks = <&apbs_gates 3>; - clock-frequency = <3000000>; - resets = <&apbs_rst 3>; - pinctrl-names = "default"; - pinctrl-0 = <&r_rsb_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/suniv-f1c100s-licheepi-nano.dts b/sys/gnu/dts/arm/suniv-f1c100s-licheepi-nano.dts deleted file mode 100644 index a1154e6c7cb..00000000000 --- a/sys/gnu/dts/arm/suniv-f1c100s-licheepi-nano.dts +++ /dev/null @@ -1,26 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR X11) -/* - * Copyright 2018 Icenowy Zheng - */ - -/dts-v1/; -#include "suniv-f1c100s.dtsi" - -/ { - model = "Lichee Pi Nano"; - compatible = "licheepi,licheepi-nano", "allwinner,suniv-f1c100s"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pe_pins>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/suniv-f1c100s.dtsi b/sys/gnu/dts/arm/suniv-f1c100s.dtsi deleted file mode 100644 index 6100d3b75f6..00000000000 --- a/sys/gnu/dts/arm/suniv-f1c100s.dtsi +++ /dev/null @@ -1,144 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR X11) -/* - * Copyright 2018 Icenowy Zheng - * Copyright 2018 Mesih Kilinc - */ - -/ { - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&intc>; - - clocks { - osc24M: clk-24M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "osc24M"; - }; - - osc32k: clk-32k { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - clock-output-names = "osc32k"; - }; - }; - - cpus { - cpu { - compatible = "arm,arm926ej-s"; - device_type = "cpu"; - }; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - sram-controller@1c00000 { - compatible = "allwinner,suniv-f1c100s-system-control", - "allwinner,sun4i-a10-system-control"; - reg = <0x01c00000 0x30>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - sram_d: sram@10000 { - compatible = "mmio-sram"; - reg = <0x00010000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x00010000 0x1000>; - - otg_sram: sram-section@0 { - compatible = "allwinner,suniv-f1c100s-sram-d", - "allwinner,sun4i-a10-sram-d"; - reg = <0x0000 0x1000>; - status = "disabled"; - }; - }; - }; - - ccu: clock@1c20000 { - compatible = "allwinner,suniv-f1c100s-ccu"; - reg = <0x01c20000 0x400>; - clocks = <&osc24M>, <&osc32k>; - clock-names = "hosc", "losc"; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - intc: interrupt-controller@1c20400 { - compatible = "allwinner,suniv-f1c100s-ic"; - reg = <0x01c20400 0x400>; - interrupt-controller; - #interrupt-cells = <1>; - }; - - pio: pinctrl@1c20800 { - compatible = "allwinner,suniv-f1c100s-pinctrl"; - reg = <0x01c20800 0x400>; - interrupts = <38>, <39>, <40>; - clocks = <&ccu 37>, <&osc24M>, <&osc32k>; - clock-names = "apb", "hosc", "losc"; - gpio-controller; - interrupt-controller; - #interrupt-cells = <3>; - #gpio-cells = <3>; - - uart0_pe_pins: uart0-pe-pins { - pins = "PE0", "PE1"; - function = "uart0"; - }; - }; - - timer@1c20c00 { - compatible = "allwinner,suniv-f1c100s-timer"; - reg = <0x01c20c00 0x90>; - interrupts = <13>; - clocks = <&osc24M>; - }; - - wdt: watchdog@1c20ca0 { - compatible = "allwinner,suniv-f1c100s-wdt", - "allwinner,sun4i-a10-wdt"; - reg = <0x01c20ca0 0x20>; - }; - - uart0: serial@1c25000 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c25000 0x400>; - interrupts = <1>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu 38>; - resets = <&ccu 24>; - status = "disabled"; - }; - - uart1: serial@1c25400 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c25400 0x400>; - interrupts = <2>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu 39>; - resets = <&ccu 25>; - status = "disabled"; - }; - - uart2: serial@1c25800 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c25800 0x400>; - interrupts = <3>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu 40>; - resets = <&ccu 26>; - status = "disabled"; - }; - }; -}; diff --git a/sys/gnu/dts/arm/sunxi-bananapi-m2-plus-v1.2.dtsi b/sys/gnu/dts/arm/sunxi-bananapi-m2-plus-v1.2.dtsi deleted file mode 100644 index 22466afd38a..00000000000 --- a/sys/gnu/dts/arm/sunxi-bananapi-m2-plus-v1.2.dtsi +++ /dev/null @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2018 Chen-Yu Tsai - */ - -#include "sunxi-bananapi-m2-plus.dtsi" - -/ { - /* - * Bananapi M2+ v1.2 uses a GPIO line to change the effective - * resistance on the CPU regulator's feedback pin. - */ - reg_vdd_cpux: vdd-cpux { - compatible = "regulator-gpio"; - regulator-name = "vdd-cpux"; - regulator-type = "voltage"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1300000>; - regulator-ramp-delay = <50>; /* 4ms */ - gpios = <&r_pio 0 1 GPIO_ACTIVE_HIGH>; /* PL1 */ - gpios-states = <0x1>; - states = <1100000 0>, <1300000 1>; - }; -}; - -&cpu0 { - cpu-supply = <®_vdd_cpux>; -}; diff --git a/sys/gnu/dts/arm/sunxi-bananapi-m2-plus.dtsi b/sys/gnu/dts/arm/sunxi-bananapi-m2-plus.dtsi deleted file mode 100644 index 39263e74fbb..00000000000 --- a/sys/gnu/dts/arm/sunxi-bananapi-m2-plus.dtsi +++ /dev/null @@ -1,242 +0,0 @@ -/* - * Copyright (C) 2016 Chen-Yu Tsai - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "sunxi-common-regulators.dtsi" - -#include -#include - -/ { - aliases { - ethernet0 = &emac; - serial0 = &uart0; - serial1 = &uart1; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - pwr_led { - label = "bananapi-m2-plus:red:pwr"; - gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */ - default-state = "on"; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - - sw4 { - label = "power"; - linux,code = ; - gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; - }; - }; - - reg_gmac_3v3: gmac-3v3 { - compatible = "regulator-fixed"; - regulator-name = "gmac-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <100000>; - enable-active-high; - gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; - }; - - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ - clocks = <&rtc 1>; - clock-names = "ext_clock"; - }; -}; - -&de { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&ehci2 { - status = "okay"; -}; - -&emac { - pinctrl-names = "default"; - pinctrl-0 = <&emac_rgmii_pins>; - phy-supply = <®_gmac_3v3>; - phy-handle = <&ext_rgmii_phy>; - phy-mode = "rgmii"; - - status = "okay"; -}; - -&external_mdio { - ext_rgmii_phy: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&ir { - pinctrl-names = "default"; - pinctrl-0 = <&r_ir_rx_pin>; - status = "okay"; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ - status = "okay"; -}; - -&mmc1 { - vmmc-supply = <®_vcc3v3>; - vqmmc-supply = <®_vcc3v3>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - interrupt-parent = <&pio>; - interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 / EINT10 */ - interrupt-names = "host-wake"; - }; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_8bit_pins>; - vmmc-supply = <®_vcc3v3>; - vqmmc-supply = <®_vcc3v3>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&ohci2 { - status = "okay"; -}; - -®_usb0_vbus { - gpio = <&pio 3 11 GPIO_ACTIVE_HIGH>; /* PD11 */ - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pa_pins>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; - uart-has-rtscts; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - clocks = <&rtc 1>; - clock-names = "lpo"; - vbat-supply = <®_vcc3v3>; - vddio-supply = <®_vcc3v3>; - device-wakeup-gpios = <&pio 6 13 GPIO_ACTIVE_HIGH>; /* PG13 */ - host-wakeup-gpios = <&pio 6 11 GPIO_ACTIVE_HIGH>; /* PG11 */ - shutdown-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ - }; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ - usb0_vbus-supply = <®_usb0_vbus>; - /* USB host VBUS is on as long as VCC-IO is on */ - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sunxi-common-regulators.dtsi b/sys/gnu/dts/arm/sunxi-common-regulators.dtsi deleted file mode 100644 index d8e5826fb3d..00000000000 --- a/sys/gnu/dts/arm/sunxi-common-regulators.dtsi +++ /dev/null @@ -1,111 +0,0 @@ -/* - * sunxi boards common regulator (ahci target power supply, usb-vbus) code - * - * Copyright 2014 - Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include - -/ { - reg_ahci_5v: ahci-5v { - compatible = "regulator-fixed"; - regulator-name = "ahci-5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - enable-active-high; - gpio = <&pio 1 8 GPIO_ACTIVE_HIGH>; - status = "disabled"; - }; - - reg_usb0_vbus: usb0-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb0-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&pio 1 9 GPIO_ACTIVE_HIGH>; - status = "disabled"; - }; - - reg_usb1_vbus: usb1-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb1-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - enable-active-high; - gpio = <&pio 7 6 GPIO_ACTIVE_HIGH>; - status = "disabled"; - }; - - reg_usb2_vbus: usb2-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb2-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - enable-active-high; - gpio = <&pio 7 3 GPIO_ACTIVE_HIGH>; - status = "disabled"; - }; - - reg_vcc3v0: vcc3v0 { - compatible = "regulator-fixed"; - regulator-name = "vcc3v0"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - reg_vcc3v3: vcc3v3 { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_vcc5v0: vcc5v0 { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; -}; diff --git a/sys/gnu/dts/arm/sunxi-h3-h5-emlid-neutis.dtsi b/sys/gnu/dts/arm/sunxi-h3-h5-emlid-neutis.dtsi deleted file mode 100644 index fc67e30fe21..00000000000 --- a/sys/gnu/dts/arm/sunxi-h3-h5-emlid-neutis.dtsi +++ /dev/null @@ -1,170 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * DTSI for Emlid Neutis SoMs. - * - * Copyright (C) 2019 Georgii Staroselskii - */ - -#include "sunxi-common-regulators.dtsi" - -#include - -/ { - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&pio 2 7 GPIO_ACTIVE_LOW>; /* PC7 */ - post-power-on-delay-ms = <200>; - clocks = <&rtc 1>; - clock-names = "ext_clock"; - }; -}; - -&cpu0 { - cpu-supply = <&vdd_cpux>; -}; - -®_usb0_vbus { - gpio = <&r_pio 0 9 GPIO_ACTIVE_HIGH>; /* PL9 */ - status = "okay"; -}; - - -&de { - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&ohci2 { - status = "okay"; -}; - -&ohci3 { - status = "okay"; -}; - - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&ehci2 { - status = "okay"; -}; - -&ehci3 { - status = "okay"; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ - status = "okay"; -}; - - -&mmc1 { - vmmc-supply = <®_vcc3v3>; - vqmmc-supply = <®_vcc3v3>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - interrupt-parent = <&r_pio>; - interrupts = <0 5 IRQ_TYPE_LEVEL_LOW>; /* PL5 */ - interrupt-names = "host-wake"; - }; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_8bit_pins>; - vmmc-supply = <®_vcc3v3>; - bus-width = <8>; - non-removable; - cap-mmc-hw-reset; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pa_pins>; - status = "okay"; -}; - - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; - uart-has-rtscts; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - clocks = <&rtc 1>; - clock-names = "lpo"; - vbat-supply = <®_vcc3v3>; - vddio-supply = <®_vcc3v3>; - shutdown-gpios = <&pio 2 4 GPIO_ACTIVE_HIGH>; /* PC4 */ - device-wakeup-gpios = <&r_pio 0 7 GPIO_ACTIVE_HIGH>; /* PL7 */ - }; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */ - usb0_vbus-supply = <®_usb0_vbus>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&codec { - allwinner,audio-routing = - "Line Out", "LINEOUT", - "LINEIN", "Line In", - "MIC1", "Mic", - "MIC2", "Mic", - "Mic", "MBIAS"; -}; - -&i2c0 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sunxi-h3-h5.dtsi b/sys/gnu/dts/arm/sunxi-h3-h5.dtsi deleted file mode 100644 index 5e9c3060aa0..00000000000 --- a/sys/gnu/dts/arm/sunxi-h3-h5.dtsi +++ /dev/null @@ -1,897 +0,0 @@ -/* - * Copyright (C) 2015 Jens Kuske - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include -#include -#include -#include -#include -#include -#include - -/ { - interrupt-parent = <&gic>; - #address-cells = <1>; - #size-cells = <1>; - - chosen { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - framebuffer-hdmi { - compatible = "allwinner,simple-framebuffer", - "simple-framebuffer"; - allwinner,pipeline = "mixer0-lcd0-hdmi"; - clocks = <&display_clocks CLK_MIXER0>, - <&ccu CLK_TCON0>, <&ccu CLK_HDMI>; - status = "disabled"; - }; - - framebuffer-tve { - compatible = "allwinner,simple-framebuffer", - "simple-framebuffer"; - allwinner,pipeline = "mixer1-lcd1-tve"; - clocks = <&display_clocks CLK_MIXER1>, - <&ccu CLK_TVE>; - status = "disabled"; - }; - }; - - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - osc24M: osc24M_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-accuracy = <50000>; - clock-output-names = "osc24M"; - }; - - osc32k: osc32k_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - clock-accuracy = <50000>; - clock-output-names = "ext_osc32k"; - }; - }; - - de: display-engine { - compatible = "allwinner,sun8i-h3-display-engine"; - allwinner,pipelines = <&mixer0>; - status = "disabled"; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - dma-ranges; - ranges; - - display_clocks: clock@1000000 { - /* compatible is in per SoC .dtsi file */ - reg = <0x01000000 0x100000>; - clocks = <&ccu CLK_BUS_DE>, - <&ccu CLK_DE>; - clock-names = "bus", - "mod"; - resets = <&ccu RST_BUS_DE>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - mixer0: mixer@1100000 { - compatible = "allwinner,sun8i-h3-de2-mixer-0"; - reg = <0x01100000 0x100000>; - clocks = <&display_clocks CLK_BUS_MIXER0>, - <&display_clocks CLK_MIXER0>; - clock-names = "bus", - "mod"; - resets = <&display_clocks RST_MIXER0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - mixer0_out: port@1 { - reg = <1>; - - mixer0_out_tcon0: endpoint { - remote-endpoint = <&tcon0_in_mixer0>; - }; - }; - }; - }; - - dma: dma-controller@1c02000 { - compatible = "allwinner,sun8i-h3-dma"; - reg = <0x01c02000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_BUS_DMA>; - resets = <&ccu RST_BUS_DMA>; - #dma-cells = <1>; - }; - - tcon0: lcd-controller@1c0c000 { - compatible = "allwinner,sun8i-h3-tcon-tv", - "allwinner,sun8i-a83t-tcon-tv"; - reg = <0x01c0c000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>; - clock-names = "ahb", "tcon-ch1"; - resets = <&ccu RST_BUS_TCON0>; - reset-names = "lcd"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - tcon0_in: port@0 { - reg = <0>; - - tcon0_in_mixer0: endpoint { - remote-endpoint = <&mixer0_out_tcon0>; - }; - }; - - tcon0_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - tcon0_out_hdmi: endpoint@1 { - reg = <1>; - remote-endpoint = <&hdmi_in_tcon0>; - }; - }; - }; - }; - - mmc0: mmc@1c0f000 { - /* compatible and clocks are in per SoC .dtsi file */ - reg = <0x01c0f000 0x1000>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; - resets = <&ccu RST_BUS_MMC0>; - reset-names = "ahb"; - interrupts = ; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc1: mmc@1c10000 { - /* compatible and clocks are in per SoC .dtsi file */ - reg = <0x01c10000 0x1000>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - resets = <&ccu RST_BUS_MMC1>; - reset-names = "ahb"; - interrupts = ; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc2: mmc@1c11000 { - /* compatible and clocks are in per SoC .dtsi file */ - reg = <0x01c11000 0x1000>; - resets = <&ccu RST_BUS_MMC2>; - reset-names = "ahb"; - interrupts = ; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - sid: eeprom@1c14000 { - /* compatible is in per SoC .dtsi file */ - reg = <0x1c14000 0x400>; - #address-cells = <1>; - #size-cells = <1>; - - ths_calibration: thermal-sensor-calibration@34 { - reg = <0x34 4>; - }; - }; - - usb_otg: usb@1c19000 { - compatible = "allwinner,sun8i-h3-musb"; - reg = <0x01c19000 0x400>; - clocks = <&ccu CLK_BUS_OTG>; - resets = <&ccu RST_BUS_OTG>; - interrupts = ; - interrupt-names = "mc"; - phys = <&usbphy 0>; - phy-names = "usb"; - extcon = <&usbphy 0>; - dr_mode = "otg"; - status = "disabled"; - }; - - usbphy: phy@1c19400 { - compatible = "allwinner,sun8i-h3-usb-phy"; - reg = <0x01c19400 0x2c>, - <0x01c1a800 0x4>, - <0x01c1b800 0x4>, - <0x01c1c800 0x4>, - <0x01c1d800 0x4>; - reg-names = "phy_ctrl", - "pmu0", - "pmu1", - "pmu2", - "pmu3"; - clocks = <&ccu CLK_USB_PHY0>, - <&ccu CLK_USB_PHY1>, - <&ccu CLK_USB_PHY2>, - <&ccu CLK_USB_PHY3>; - clock-names = "usb0_phy", - "usb1_phy", - "usb2_phy", - "usb3_phy"; - resets = <&ccu RST_USB_PHY0>, - <&ccu RST_USB_PHY1>, - <&ccu RST_USB_PHY2>, - <&ccu RST_USB_PHY3>; - reset-names = "usb0_reset", - "usb1_reset", - "usb2_reset", - "usb3_reset"; - status = "disabled"; - #phy-cells = <1>; - }; - - ehci0: usb@1c1a000 { - compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; - reg = <0x01c1a000 0x100>; - interrupts = ; - clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>; - resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>; - status = "disabled"; - }; - - ohci0: usb@1c1a400 { - compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; - reg = <0x01c1a400 0x100>; - interrupts = ; - clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>, - <&ccu CLK_USB_OHCI0>; - resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>; - status = "disabled"; - }; - - ehci1: usb@1c1b000 { - compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; - reg = <0x01c1b000 0x100>; - interrupts = ; - clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>; - resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>; - phys = <&usbphy 1>; - phy-names = "usb"; - status = "disabled"; - }; - - ohci1: usb@1c1b400 { - compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; - reg = <0x01c1b400 0x100>; - interrupts = ; - clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>, - <&ccu CLK_USB_OHCI1>; - resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>; - phys = <&usbphy 1>; - phy-names = "usb"; - status = "disabled"; - }; - - ehci2: usb@1c1c000 { - compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; - reg = <0x01c1c000 0x100>; - interrupts = ; - clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>; - resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>; - phys = <&usbphy 2>; - phy-names = "usb"; - status = "disabled"; - }; - - ohci2: usb@1c1c400 { - compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; - reg = <0x01c1c400 0x100>; - interrupts = ; - clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>, - <&ccu CLK_USB_OHCI2>; - resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>; - phys = <&usbphy 2>; - phy-names = "usb"; - status = "disabled"; - }; - - ehci3: usb@1c1d000 { - compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; - reg = <0x01c1d000 0x100>; - interrupts = ; - clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>; - resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>; - phys = <&usbphy 3>; - phy-names = "usb"; - status = "disabled"; - }; - - ohci3: usb@1c1d400 { - compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; - reg = <0x01c1d400 0x100>; - interrupts = ; - clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>, - <&ccu CLK_USB_OHCI3>; - resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>; - phys = <&usbphy 3>; - phy-names = "usb"; - status = "disabled"; - }; - - ccu: clock@1c20000 { - /* compatible is in per SoC .dtsi file */ - reg = <0x01c20000 0x400>; - clocks = <&osc24M>, <&rtc 0>; - clock-names = "hosc", "losc"; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - pio: pinctrl@1c20800 { - /* compatible is in per SoC .dtsi file */ - reg = <0x01c20800 0x400>; - interrupts = , - ; - clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>; - clock-names = "apb", "hosc", "losc"; - gpio-controller; - #gpio-cells = <3>; - interrupt-controller; - #interrupt-cells = <3>; - - csi_pins: csi-pins { - pins = "PE0", "PE2", "PE3", "PE4", "PE5", - "PE6", "PE7", "PE8", "PE9", "PE10", - "PE11"; - function = "csi"; - }; - - emac_rgmii_pins: emac-rgmii-pins { - pins = "PD0", "PD1", "PD2", "PD3", "PD4", - "PD5", "PD7", "PD8", "PD9", "PD10", - "PD12", "PD13", "PD15", "PD16", "PD17"; - function = "emac"; - drive-strength = <40>; - }; - - i2c0_pins: i2c0-pins { - pins = "PA11", "PA12"; - function = "i2c0"; - }; - - i2c1_pins: i2c1-pins { - pins = "PA18", "PA19"; - function = "i2c1"; - }; - - i2c2_pins: i2c2-pins { - pins = "PE12", "PE13"; - function = "i2c2"; - }; - - mmc0_pins: mmc0-pins { - pins = "PF0", "PF1", "PF2", "PF3", - "PF4", "PF5"; - function = "mmc0"; - drive-strength = <30>; - bias-pull-up; - }; - - mmc1_pins: mmc1-pins { - pins = "PG0", "PG1", "PG2", "PG3", - "PG4", "PG5"; - function = "mmc1"; - drive-strength = <30>; - bias-pull-up; - }; - - mmc2_8bit_pins: mmc2-8bit-pins { - pins = "PC5", "PC6", "PC8", - "PC9", "PC10", "PC11", - "PC12", "PC13", "PC14", - "PC15", "PC16"; - function = "mmc2"; - drive-strength = <30>; - bias-pull-up; - }; - - spdif_tx_pin: spdif-tx-pin { - pins = "PA17"; - function = "spdif"; - }; - - spi0_pins: spi0-pins { - pins = "PC0", "PC1", "PC2", "PC3"; - function = "spi0"; - }; - - spi1_pins: spi1-pins { - pins = "PA15", "PA16", "PA14", "PA13"; - function = "spi1"; - }; - - uart0_pa_pins: uart0-pa-pins { - pins = "PA4", "PA5"; - function = "uart0"; - }; - - uart1_pins: uart1-pins { - pins = "PG6", "PG7"; - function = "uart1"; - }; - - uart1_rts_cts_pins: uart1-rts-cts-pins { - pins = "PG8", "PG9"; - function = "uart1"; - }; - - uart2_pins: uart2-pins { - pins = "PA0", "PA1"; - function = "uart2"; - }; - - uart2_rts_cts_pins: uart2-rts-cts-pins { - pins = "PA2", "PA3"; - function = "uart2"; - }; - - uart3_pins: uart3-pins { - pins = "PA13", "PA14"; - function = "uart3"; - }; - - uart3_rts_cts_pins: uart3-rts-cts-pins { - pins = "PA15", "PA16"; - function = "uart3"; - }; - }; - - timer@1c20c00 { - compatible = "allwinner,sun8i-a23-timer"; - reg = <0x01c20c00 0xa0>; - interrupts = , - ; - clocks = <&osc24M>; - }; - - emac: ethernet@1c30000 { - compatible = "allwinner,sun8i-h3-emac"; - syscon = <&syscon>; - reg = <0x01c30000 0x10000>; - interrupts = ; - interrupt-names = "macirq"; - resets = <&ccu RST_BUS_EMAC>; - reset-names = "stmmaceth"; - clocks = <&ccu CLK_BUS_EMAC>; - clock-names = "stmmaceth"; - status = "disabled"; - - mdio: mdio { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - }; - - mdio-mux { - compatible = "allwinner,sun8i-h3-mdio-mux"; - #address-cells = <1>; - #size-cells = <0>; - - mdio-parent-bus = <&mdio>; - /* Only one MDIO is usable at the time */ - internal_mdio: mdio@1 { - compatible = "allwinner,sun8i-h3-mdio-internal"; - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - int_mii_phy: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - clocks = <&ccu CLK_BUS_EPHY>; - resets = <&ccu RST_BUS_EPHY>; - }; - }; - - external_mdio: mdio@2 { - reg = <2>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - }; - - mbus: dram-controller@1c62000 { - compatible = "allwinner,sun8i-h3-mbus"; - reg = <0x01c62000 0x1000>; - clocks = <&ccu CLK_MBUS>; - dma-ranges = <0x00000000 0x40000000 0xc0000000>; - #interconnect-cells = <1>; - }; - - spi0: spi@1c68000 { - compatible = "allwinner,sun8i-h3-spi"; - reg = <0x01c68000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; - clock-names = "ahb", "mod"; - dmas = <&dma 23>, <&dma 23>; - dma-names = "rx", "tx"; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins>; - resets = <&ccu RST_BUS_SPI0>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - spi1: spi@1c69000 { - compatible = "allwinner,sun8i-h3-spi"; - reg = <0x01c69000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; - clock-names = "ahb", "mod"; - dmas = <&dma 24>, <&dma 24>; - dma-names = "rx", "tx"; - pinctrl-names = "default"; - pinctrl-0 = <&spi1_pins>; - resets = <&ccu RST_BUS_SPI1>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - wdt0: watchdog@1c20ca0 { - compatible = "allwinner,sun6i-a31-wdt"; - reg = <0x01c20ca0 0x20>; - interrupts = ; - clocks = <&osc24M>; - }; - - spdif: spdif@1c21000 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun8i-h3-spdif"; - reg = <0x01c21000 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; - resets = <&ccu RST_BUS_SPDIF>; - clock-names = "apb", "spdif"; - dmas = <&dma 2>; - dma-names = "tx"; - status = "disabled"; - }; - - pwm: pwm@1c21400 { - compatible = "allwinner,sun8i-h3-pwm"; - reg = <0x01c21400 0x8>; - clocks = <&osc24M>; - #pwm-cells = <3>; - status = "disabled"; - }; - - i2s0: i2s@1c22000 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun8i-h3-i2s"; - reg = <0x01c22000 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>; - clock-names = "apb", "mod"; - dmas = <&dma 3>, <&dma 3>; - resets = <&ccu RST_BUS_I2S0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2s1: i2s@1c22400 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun8i-h3-i2s"; - reg = <0x01c22400 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>; - clock-names = "apb", "mod"; - dmas = <&dma 4>, <&dma 4>; - resets = <&ccu RST_BUS_I2S1>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - codec: codec@1c22c00 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun8i-h3-codec"; - reg = <0x01c22c00 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; - clock-names = "apb", "codec"; - resets = <&ccu RST_BUS_CODEC>; - dmas = <&dma 15>, <&dma 15>; - dma-names = "rx", "tx"; - allwinner,codec-analog-controls = <&codec_analog>; - status = "disabled"; - }; - - uart0: serial@1c28000 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART0>; - resets = <&ccu RST_BUS_UART0>; - dmas = <&dma 6>, <&dma 6>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart1: serial@1c28400 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28400 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART1>; - resets = <&ccu RST_BUS_UART1>; - dmas = <&dma 7>, <&dma 7>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart2: serial@1c28800 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28800 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART2>; - resets = <&ccu RST_BUS_UART2>; - dmas = <&dma 8>, <&dma 8>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart3: serial@1c28c00 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28c00 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART3>; - resets = <&ccu RST_BUS_UART3>; - dmas = <&dma 9>, <&dma 9>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c0: i2c@1c2ac00 { - compatible = "allwinner,sun6i-a31-i2c"; - reg = <0x01c2ac00 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_I2C0>; - resets = <&ccu RST_BUS_I2C0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c1: i2c@1c2b000 { - compatible = "allwinner,sun6i-a31-i2c"; - reg = <0x01c2b000 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_I2C1>; - resets = <&ccu RST_BUS_I2C1>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c2: i2c@1c2b400 { - compatible = "allwinner,sun6i-a31-i2c"; - reg = <0x01c2b400 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_I2C2>; - resets = <&ccu RST_BUS_I2C2>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - gic: interrupt-controller@1c81000 { - compatible = "arm,gic-400"; - reg = <0x01c81000 0x1000>, - <0x01c82000 0x2000>, - <0x01c84000 0x2000>, - <0x01c86000 0x2000>; - interrupt-controller; - #interrupt-cells = <3>; - interrupts = ; - }; - - csi: camera@1cb0000 { - compatible = "allwinner,sun8i-h3-csi"; - reg = <0x01cb0000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_BUS_CSI>, - <&ccu CLK_CSI_SCLK>, - <&ccu CLK_DRAM_CSI>; - clock-names = "bus", "mod", "ram"; - resets = <&ccu RST_BUS_CSI>; - pinctrl-names = "default"; - pinctrl-0 = <&csi_pins>; - status = "disabled"; - }; - - hdmi: hdmi@1ee0000 { - compatible = "allwinner,sun8i-h3-dw-hdmi", - "allwinner,sun8i-a83t-dw-hdmi"; - reg = <0x01ee0000 0x10000>; - reg-io-width = <1>; - interrupts = ; - clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, - <&ccu CLK_HDMI>; - clock-names = "iahb", "isfr", "tmds"; - resets = <&ccu RST_BUS_HDMI1>; - reset-names = "ctrl"; - phys = <&hdmi_phy>; - phy-names = "phy"; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - hdmi_in: port@0 { - reg = <0>; - - hdmi_in_tcon0: endpoint { - remote-endpoint = <&tcon0_out_hdmi>; - }; - }; - - hdmi_out: port@1 { - reg = <1>; - }; - }; - }; - - hdmi_phy: hdmi-phy@1ef0000 { - compatible = "allwinner,sun8i-h3-hdmi-phy"; - reg = <0x01ef0000 0x10000>; - clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, - <&ccu CLK_PLL_VIDEO>; - clock-names = "bus", "mod", "pll-0"; - resets = <&ccu RST_BUS_HDMI0>; - reset-names = "phy"; - #phy-cells = <0>; - }; - - rtc: rtc@1f00000 { - /* compatible is in per SoC .dtsi file */ - reg = <0x01f00000 0x400>; - interrupts = , - ; - clock-output-names = "osc32k", "osc32k-out", "iosc"; - clocks = <&osc32k>; - #clock-cells = <1>; - }; - - r_ccu: clock@1f01400 { - compatible = "allwinner,sun8i-h3-r-ccu"; - reg = <0x01f01400 0x100>; - clocks = <&osc24M>, <&rtc 0>, <&rtc 2>, - <&ccu CLK_PLL_PERIPH0>; - clock-names = "hosc", "losc", "iosc", "pll-periph"; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - codec_analog: codec-analog@1f015c0 { - compatible = "allwinner,sun8i-h3-codec-analog"; - reg = <0x01f015c0 0x4>; - }; - - ir: ir@1f02000 { - compatible = "allwinner,sun6i-a31-ir"; - clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>; - clock-names = "apb", "ir"; - resets = <&r_ccu RST_APB0_IR>; - interrupts = ; - reg = <0x01f02000 0x400>; - status = "disabled"; - }; - - r_i2c: i2c@1f02400 { - compatible = "allwinner,sun6i-a31-i2c"; - reg = <0x01f02400 0x400>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&r_i2c_pins>; - clocks = <&r_ccu CLK_APB0_I2C>; - resets = <&r_ccu RST_APB0_I2C>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - r_pio: pinctrl@1f02c00 { - compatible = "allwinner,sun8i-h3-r-pinctrl"; - reg = <0x01f02c00 0x400>; - interrupts = ; - clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&rtc 0>; - clock-names = "apb", "hosc", "losc"; - gpio-controller; - #gpio-cells = <3>; - interrupt-controller; - #interrupt-cells = <3>; - - r_ir_rx_pin: r-ir-rx-pin { - pins = "PL11"; - function = "s_cir_rx"; - }; - - r_i2c_pins: r-i2c-pins { - pins = "PL0", "PL1"; - function = "s_i2c"; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/sunxi-itead-core-common.dtsi b/sys/gnu/dts/arm/sunxi-itead-core-common.dtsi deleted file mode 100644 index 0d002f83a25..00000000000 --- a/sys/gnu/dts/arm/sunxi-itead-core-common.dtsi +++ /dev/null @@ -1,132 +0,0 @@ -/* - * Copyright 2015 - Marcus Cooper - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "sunxi-common-regulators.dtsi" - -/ { - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - }; -}; - -&i2c1 { - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -#include "axp209.dtsi" - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-int-dll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usbphy { - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sunxi-libretech-all-h3-cc.dtsi b/sys/gnu/dts/arm/sunxi-libretech-all-h3-cc.dtsi deleted file mode 100644 index 19b3b23cfaa..00000000000 --- a/sys/gnu/dts/arm/sunxi-libretech-all-h3-cc.dtsi +++ /dev/null @@ -1,224 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2017 Chen-Yu Tsai - */ - -#include -#include - -/ { - aliases { - ethernet0 = &emac; - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - pwr_led { - label = "librecomputer:green:pwr"; - gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */ - default-state = "on"; - }; - - status_led { - label = "librecomputer:blue:status"; - gpios = <&pio 0 7 GPIO_ACTIVE_HIGH>; /* PA7 */ - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - - power { - label = "power"; - linux,code = ; - gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ - }; - }; - - reg_vcc1v2: vcc1v2 { - compatible = "regulator-fixed"; - regulator-name = "vcc1v2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <®_vcc5v0>; - gpio = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */ - enable-active-high; - }; - - reg_vcc3v3: vcc3v3 { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <®_vcc5v0>; - }; - - /* This represents the board's 5V input */ - reg_vcc5v0: vcc5v0 { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_vcc_dram: vcc-dram { - compatible = "regulator-fixed"; - regulator-name = "vcc-dram"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <®_vcc5v0>; - gpio = <&r_pio 0 9 GPIO_ACTIVE_HIGH>; /* PL9 */ - enable-active-high; - }; - - reg_vcc_io: vcc-io { - compatible = "regulator-fixed"; - regulator-name = "vcc-io"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <®_vcc3v3>; - gpio = <&r_pio 0 5 GPIO_ACTIVE_LOW>; /* PL5 */ - }; - - reg_vdd_cpux: vdd-cpux { - compatible = "regulator-fixed"; - regulator-name = "vdd-cpux"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <®_vcc5v0>; - gpio = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */ - enable-active-high; - }; -}; - -&codec { - allwinner,audio-routing = - "Line Out", "LINEOUT", - "MIC1", "Mic", - "Mic", "MBIAS"; - status = "okay"; -}; - -&cpu0 { - cpu-supply = <®_vdd_cpux>; -}; - -&de { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&ehci2 { - status = "okay"; -}; - -&ehci3 { - status = "okay"; -}; - -&emac { - phy-handle = <&int_mii_phy>; - phy-mode = "mii"; - allwinner,leds-active-low; - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&ir { - pinctrl-names = "default"; - pinctrl-0 = <&r_ir_rx_pin>; - status = "okay"; -}; - -&mmc0 { - vmmc-supply = <®_vcc_io>; - bus-width = <4>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ - status = "okay"; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_8bit_pins>; - vmmc-supply = <®_vcc_io>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&ohci2 { - status = "okay"; -}; - -&ohci3 { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pa_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "host"; - status = "okay"; -}; - -&usbphy { - /* VBUS on USB ports are always on */ - usb0_vbus-supply = <®_vcc5v0>; - usb1_vbus-supply = <®_vcc5v0>; - usb2_vbus-supply = <®_vcc5v0>; - usb3_vbus-supply = <®_vcc5v0>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sunxi-libretech-all-h3-it.dtsi b/sys/gnu/dts/arm/sunxi-libretech-all-h3-it.dtsi deleted file mode 100644 index 204fba3614f..00000000000 --- a/sys/gnu/dts/arm/sunxi-libretech-all-h3-it.dtsi +++ /dev/null @@ -1,180 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (C) 2019 Chen-Yu Tsai - -#include -#include - -/ { - aliases { - serial0 = &uart0; - spi0 = &spi0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - connector { - compatible = "hdmi-connector"; - type = "d"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - status_led { - label = "librecomputer:blue:status"; - gpios = <&pio 0 7 GPIO_ACTIVE_HIGH>; /* PA7 */ - }; - }; - - reg_vcc3v3: vcc3v3 { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <®_vcc5v0>; - }; - - /* This represents the board's 5V input */ - reg_vcc5v0: vcc5v0 { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - reg_vcc_dram: vcc-dram { - compatible = "regulator-fixed"; - regulator-name = "vcc-dram"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <®_vcc5v0>; - gpio = <&r_pio 0 9 GPIO_ACTIVE_HIGH>; /* PL9 */ - enable-active-high; - }; - - reg_vcc_io: vcc-io { - compatible = "regulator-fixed"; - regulator-name = "vcc-io"; - /* This is simply a MOSFET switch */ - regulator-always-on; - regulator-boot-on; - vin-supply = <®_vcc3v3>; - gpio = <&r_pio 0 5 GPIO_ACTIVE_LOW>; /* PL5 */ - }; - - reg_vcc_usbwifi: vcc-usbwifi { - compatible = "regulator-fixed"; - regulator-name = "vcc-usbwifi"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <®_vcc5v0>; - gpio = <&pio 6 4 GPIO_ACTIVE_HIGH>; /* PG4 */ - enable-active-high; - }; - - reg_vdd_cpux: vdd-cpux { - compatible = "regulator-fixed"; - regulator-name = "vdd-cpux"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <®_vcc5v0>; - gpio = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */ - enable-active-high; - }; -}; - -&cpu0 { - cpu-supply = <®_vdd_cpux>; -}; - -&cpu1 { - cpu-supply = <®_vdd_cpux>; -}; - -&cpu2 { - cpu-supply = <®_vdd_cpux>; -}; - -&cpu3 { - cpu-supply = <®_vdd_cpux>; -}; - -&de { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc_io>; - bus-width = <4>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ - status = "okay"; -}; - -&pio { - vcc-pa-supply = <®_vcc_io>; - vcc-pc-supply = <®_vcc_io>; - vcc-pd-supply = <®_vcc_io>; - vcc-pe-supply = <®_vcc_io>; - vcc-pf-supply = <®_vcc_io>; - vcc-pg-supply = <®_vcc_io>; -}; - -&r_pio { - vcc-pl-supply = <®_vcc3v3>; -}; - -&spi0 { - status = "okay"; - - spiflash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <50000000>; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pa_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "peripheral"; - status = "okay"; -}; - -&usbphy { - usb1_vbus-supply = <®_vcc_usbwifi>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sunxi-q8-common.dtsi b/sys/gnu/dts/arm/sunxi-q8-common.dtsi deleted file mode 100644 index b8241462fce..00000000000 --- a/sys/gnu/dts/arm/sunxi-q8-common.dtsi +++ /dev/null @@ -1,83 +0,0 @@ -/* - * Copyright 2015 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include -#include -#include -#include "sunxi-common-regulators.dtsi" - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; - status = "okay"; -}; - -&lradc { - vref-supply = <®_vcc3v0>; - status = "okay"; - - button@200 { - label = "Volume Up"; - linux,code = ; - channel = <0>; - voltage = <200000>; - }; - - button@400 { - label = "Volume Down"; - linux,code = ; - channel = <0>; - voltage = <400000>; - }; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pins>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/sunxi-reference-design-tablet.dtsi b/sys/gnu/dts/arm/sunxi-reference-design-tablet.dtsi deleted file mode 100644 index 117198c52e1..00000000000 --- a/sys/gnu/dts/arm/sunxi-reference-design-tablet.dtsi +++ /dev/null @@ -1,82 +0,0 @@ -/* - * Copyright 2015 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include -#include -#include "sunxi-common-regulators.dtsi" - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - status = "okay"; -}; - -&lradc { - vref-supply = <®_vcc3v0>; - status = "okay"; - - button-200 { - label = "Volume Up"; - linux,code = ; - channel = <0>; - voltage = <200000>; - }; - - button-400 { - label = "Volume Down"; - linux,code = ; - channel = <0>; - voltage = <400000>; - }; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pin>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/tango4-common.dtsi b/sys/gnu/dts/arm/tango4-common.dtsi deleted file mode 100644 index ff72a8efb73..00000000000 --- a/sys/gnu/dts/arm/tango4-common.dtsi +++ /dev/null @@ -1,184 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Based on Mans Rullgard's Tango3 DT - * https://github.com/mansr/linux-tangox - */ - -#include - -#define CPU_CLK 0 -#define SYS_CLK 1 -#define USB_CLK 2 -#define SDIO_CLK 3 - -/ { - interrupt-parent = <&gic>; - #address-cells = <1>; - #size-cells = <1>; - - periph_clk: periph_clk { - compatible = "fixed-factor-clock"; - clocks = <&clkgen CPU_CLK>; - clock-mult = <1>; - clock-div = <2>; - #clock-cells = <0>; - }; - - mpcore { - compatible = "simple-bus"; - ranges = <0x00000000 0x20000000 0x2000>; - #address-cells = <1>; - #size-cells = <1>; - - scu@0 { - compatible = "arm,cortex-a9-scu"; - reg = <0x0 0x100>; - }; - - twd@600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0x600 0x10>; - interrupts = ; - clocks = <&periph_clk>; - always-on; - }; - - gic: interrupt-controller@1000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x1000 0x1000>, <0x100 0x100>; - }; - }; - - l2cc: l2-cache-controller@20100000 { - compatible = "arm,pl310-cache"; - reg = <0x20100000 0x1000>; - cache-level = <2>; - cache-unified; - }; - - soc { - compatible = "simple-bus"; - interrupt-parent = <&irq0>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - xtal: xtal { - compatible = "fixed-clock"; - clock-frequency = <27000000>; - #clock-cells = <0>; - }; - - clkgen: clkgen@10000 { - compatible = "sigma,tango4-clkgen"; - reg = <0x10000 0x100>; - clocks = <&xtal>; - #clock-cells = <1>; - }; - - tick-counter@10048 { - compatible = "sigma,tick-counter"; - reg = <0x10048 0x4>; - clocks = <&xtal>; - }; - - uart: serial@10700 { - compatible = "ralink,rt2880-uart"; - reg = <0x10700 0x30>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <7372800>; - reg-shift = <2>; - }; - - watchdog@1fd00 { - compatible = "sigma,smp8759-wdt"; - reg = <0x1fd00 8>; - clocks = <&xtal>; - }; - - mmc0: mmc@21000 { - compatible = "arasan,sdhci-8.9a"; - reg = <0x21000 0x200>; - clock-names = "clk_xin", "clk_ahb"; - clocks = <&clkgen SDIO_CLK>, <&clkgen SYS_CLK>; - interrupts = <60 IRQ_TYPE_LEVEL_HIGH>; - }; - - mmc1: mmc@21200 { - compatible = "arasan,sdhci-8.9a"; - reg = <0x21200 0x200>; - clock-names = "clk_xin", "clk_ahb"; - clocks = <&clkgen SDIO_CLK>, <&clkgen SYS_CLK>; - interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; - }; - - usb0: usb@21400 { - compatible = "chipidea,usb2"; - reg = <0x21400 0x200>; - interrupts = <40 IRQ_TYPE_LEVEL_HIGH>; - phys = <&usb0_phy>; - phy-names = "usb-phy"; - }; - - usb0_phy: phy@21700 { - compatible = "sigma,smp8642-usb-phy"; - reg = <0x21700 0x100>; - #phy-cells = <0>; - clocks = <&clkgen USB_CLK>; - }; - - usb1: usb@25400 { - compatible = "chipidea,usb2"; - reg = <0x25400 0x200>; - interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; - phys = <&usb1_phy>; - phy-names = "usb-phy"; - }; - - usb1_phy: phy@25700 { - compatible = "sigma,smp8642-usb-phy"; - reg = <0x25700 0x100>; - #phy-cells = <0>; - clocks = <&clkgen USB_CLK>; - }; - - eth0: ethernet@26000 { - compatible = "sigma,smp8734-ethernet"; - reg = <0x26000 0x800>; - interrupts = <38 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clkgen SYS_CLK>; - }; - - intc: interrupt-controller@6e000 { - compatible = "sigma,smp8642-intc"; - reg = <0x6e000 0x400>; - ranges = <0 0x6e000 0x400>; - interrupt-parent = <&gic>; - #address-cells = <1>; - #size-cells = <1>; - - irq0: irq0@0 { - reg = <0x000 0x100>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = ; - }; - - irq1: irq1@100 { - reg = <0x100 0x100>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = ; - }; - - irq2: irq2@300 { - reg = <0x300 0x100>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = ; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/tango4-smp8758.dtsi b/sys/gnu/dts/arm/tango4-smp8758.dtsi deleted file mode 100644 index 1c6a5bf1a86..00000000000 --- a/sys/gnu/dts/arm/tango4-smp8758.dtsi +++ /dev/null @@ -1,57 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "tango4-common.dtsi" - -/ { - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "sigma,tango4-smp"; - - cpu0: cpu@0 { - compatible = "arm,cortex-a9"; - next-level-cache = <&l2cc>; - device_type = "cpu"; - reg = <0>; - clocks = <&clkgen CPU_CLK>; - clock-latency = <1>; - }; - - cpu1: cpu@1 { - compatible = "arm,cortex-a9"; - next-level-cache = <&l2cc>; - device_type = "cpu"; - reg = <1>; - }; - }; - - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupt-affinity = <&cpu0>, <&cpu1>; - interrupts = - , - ; - }; - - soc { - cpu_temp: thermal@920100 { - #thermal-sensor-cells = <0>; - compatible = "sigma,smp8758-thermal"; - reg = <0x920100 12>; - }; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay = <997>; /* milliseconds */ - polling-delay-passive = <499>; /* milliseconds */ - thermal-sensors = <&cpu_temp>; - trips { - cpu_critical { - temperature = <120000>; - hysteresis = <2500>; - type = "critical"; - }; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/tango4-vantage-1172.dts b/sys/gnu/dts/arm/tango4-vantage-1172.dts deleted file mode 100644 index d237d7f02c5..00000000000 --- a/sys/gnu/dts/arm/tango4-vantage-1172.dts +++ /dev/null @@ -1,42 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "tango4-smp8758.dtsi" - -/ { - model = "Sigma Designs SMP8758 Vantage-1172 Rev E1"; - compatible = "sigma,vantage-1172", "sigma,smp8758", "sigma,tango4"; - - aliases { - serial = &uart; - eth0 = ð0; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x80000000>; /* 2 GB */ - }; - - chosen { - stdout-path = "serial:115200n8"; - }; -}; - -ð0 { - phy-connection-type = "rgmii-id"; - phy-handle = <ð0_phy>; - #address-cells = <1>; - #size-cells = <0>; - - /* Atheros AR8035 */ - eth0_phy: ethernet-phy@4 { - compatible = "ethernet-phy-id004d.d072", - "ethernet-phy-ieee802.3-c22"; - interrupts = <37 IRQ_TYPE_EDGE_RISING>; - reg = <4>; - }; -}; - -&mmc1 { - non-removable; /* eMMC */ -}; diff --git a/sys/gnu/dts/arm/tegra114-dalmore.dts b/sys/gnu/dts/arm/tegra114-dalmore.dts deleted file mode 100644 index 97a5c3504bb..00000000000 --- a/sys/gnu/dts/arm/tegra114-dalmore.dts +++ /dev/null @@ -1,1302 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * This dts file supports Dalmore A04. - * Other board revisions are not supported - */ - -/dts-v1/; - -#include -#include "tegra114.dtsi" - -/ { - model = "NVIDIA Tegra114 Dalmore evaluation board"; - compatible = "nvidia,dalmore", "nvidia,tegra114"; - - aliases { - rtc0 = "/i2c@7000d000/tps65913@58"; - rtc1 = "/rtc@7000e000"; - serial0 = &uartd; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@80000000 { - reg = <0x80000000 0x40000000>; - }; - - host1x@50000000 { - hdmi@54280000 { - status = "okay"; - - hdmi-supply = <&vdd_5v0_hdmi>; - vdd-supply = <&vdd_hdmi_reg>; - pll-supply = <&palmas_smps3_reg>; - - nvidia,ddc-i2c-bus = <&hdmi_ddc>; - nvidia,hpd-gpio = - <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; - }; - - dsi@54300000 { - status = "okay"; - - avdd-dsi-csi-supply = <&avdd_1v2_reg>; - - panel@0 { - compatible = "panasonic,vvx10f004b00", - "simple-panel"; - reg = <0>; - - power-supply = <&avdd_lcd_reg>; - backlight = <&backlight>; - }; - }; - }; - - pinmux@70000868 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - clk1_out_pw4 { - nvidia,pins = "clk1_out_pw4"; - nvidia,function = "extperiph1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap1_din_pn1 { - nvidia,pins = "dap1_din_pn1"; - nvidia,function = "i2s0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap1_dout_pn2 { - nvidia,pins = "dap1_dout_pn2", - "dap1_fs_pn0", - "dap1_sclk_pn3"; - nvidia,function = "i2s0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap2_din_pa4 { - nvidia,pins = "dap2_din_pa4"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap2_dout_pa5 { - nvidia,pins = "dap2_dout_pa5", - "dap2_fs_pa2", - "dap2_sclk_pa3"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap4_din_pp5 { - nvidia,pins = "dap4_din_pp5", - "dap4_dout_pp6", - "dap4_fs_pp4", - "dap4_sclk_pp7"; - nvidia,function = "i2s3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dvfs_pwm_px0 { - nvidia,pins = "dvfs_pwm_px0", - "dvfs_clk_px2"; - nvidia,function = "cldvfs"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_clk_py0 { - nvidia,pins = "ulpi_clk_py0", - "ulpi_data0_po1", - "ulpi_data1_po2", - "ulpi_data2_po3", - "ulpi_data3_po4", - "ulpi_data4_po5", - "ulpi_data5_po6", - "ulpi_data6_po7", - "ulpi_data7_po0"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_dir_py1 { - nvidia,pins = "ulpi_dir_py1", - "ulpi_nxt_py2"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_stp_py3 { - nvidia,pins = "ulpi_stp_py3"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - cam_i2c_scl_pbb1 { - nvidia,pins = "cam_i2c_scl_pbb1", - "cam_i2c_sda_pbb2"; - nvidia,function = "i2c3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,lock = ; - nvidia,open-drain = ; - }; - cam_mclk_pcc0 { - nvidia,pins = "cam_mclk_pcc0", - "pbb0"; - nvidia,function = "vi_alt3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,lock = ; - }; - gen2_i2c_scl_pt5 { - nvidia,pins = "gen2_i2c_scl_pt5", - "gen2_i2c_sda_pt6"; - nvidia,function = "i2c2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,lock = ; - nvidia,open-drain = ; - }; - gmi_a16_pj7 { - nvidia,pins = "gmi_a16_pj7"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_a17_pb0 { - nvidia,pins = "gmi_a17_pb0", - "gmi_a18_pb1"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_a19_pk7 { - nvidia,pins = "gmi_a19_pk7"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad5_pg5 { - nvidia,pins = "gmi_ad5_pg5", - "gmi_cs6_n_pi3", - "gmi_wr_n_pi0"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad6_pg6 { - nvidia,pins = "gmi_ad6_pg6", - "gmi_ad7_pg7"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad12_ph4 { - nvidia,pins = "gmi_ad12_ph4"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad9_ph1 { - nvidia,pins = "gmi_ad9_ph1"; - nvidia,function = "pwm1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_cs1_n_pj2 { - nvidia,pins = "gmi_cs1_n_pj2", - "gmi_oe_n_pi1"; - nvidia,function = "soc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk2_out_pw5 { - nvidia,pins = "clk2_out_pw5"; - nvidia,function = "extperiph2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_clk_pz0 { - nvidia,pins = "sdmmc1_clk_pz0"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_cmd_pz1 { - nvidia,pins = "sdmmc1_cmd_pz1", - "sdmmc1_dat0_py7", - "sdmmc1_dat1_py6", - "sdmmc1_dat2_py5", - "sdmmc1_dat3_py4"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_wp_n_pv3 { - nvidia,pins = "sdmmc1_wp_n_pv3"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_clk_pa6 { - nvidia,pins = "sdmmc3_clk_pa6"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_cmd_pa7 { - nvidia,pins = "sdmmc3_cmd_pa7", - "sdmmc3_dat0_pb7", - "sdmmc3_dat1_pb6", - "sdmmc3_dat2_pb5", - "sdmmc3_dat3_pb4", - "kb_col4_pq4", - "sdmmc3_clk_lb_out_pee4", - "sdmmc3_clk_lb_in_pee5"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_clk_pcc4 { - nvidia,pins = "sdmmc4_clk_pcc4"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_cmd_pt7 { - nvidia,pins = "sdmmc4_cmd_pt7", - "sdmmc4_dat0_paa0", - "sdmmc4_dat1_paa1", - "sdmmc4_dat2_paa2", - "sdmmc4_dat3_paa3", - "sdmmc4_dat4_paa4", - "sdmmc4_dat5_paa5", - "sdmmc4_dat6_paa6", - "sdmmc4_dat7_paa7"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk_32k_out_pa0 { - nvidia,pins = "clk_32k_out_pa0"; - nvidia,function = "blink"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col0_pq0 { - nvidia,pins = "kb_col0_pq0", - "kb_col1_pq1", - "kb_col2_pq2", - "kb_row0_pr0", - "kb_row1_pr1", - "kb_row2_pr2"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3_din_pp1 { - nvidia,pins = "dap3_din_pp1", - "dap3_sclk_pp3"; - nvidia,function = "displayb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pv0 { - nvidia,pins = "pv0"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row7_pr7 { - nvidia,pins = "kb_row7_pr7"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row10_ps2 { - nvidia,pins = "kb_row10_ps2"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row9_ps1 { - nvidia,pins = "kb_row9_ps1"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pwr_i2c_scl_pz6 { - nvidia,pins = "pwr_i2c_scl_pz6", - "pwr_i2c_sda_pz7"; - nvidia,function = "i2cpwr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,lock = ; - nvidia,open-drain = ; - }; - sys_clk_req_pz5 { - nvidia,pins = "sys_clk_req_pz5"; - nvidia,function = "sysclk"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - core_pwr_req { - nvidia,pins = "core_pwr_req"; - nvidia,function = "pwron"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - cpu_pwr_req { - nvidia,pins = "cpu_pwr_req"; - nvidia,function = "cpu"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pwr_int_n { - nvidia,pins = "pwr_int_n"; - nvidia,function = "pmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - reset_out_n { - nvidia,pins = "reset_out_n"; - nvidia,function = "reset_out_n"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk3_out_pee0 { - nvidia,pins = "clk3_out_pee0"; - nvidia,function = "extperiph3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gen1_i2c_scl_pc4 { - nvidia,pins = "gen1_i2c_scl_pc4", - "gen1_i2c_sda_pc5"; - nvidia,function = "i2c1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,lock = ; - nvidia,open-drain = ; - }; - uart2_cts_n_pj5 { - nvidia,pins = "uart2_cts_n_pj5"; - nvidia,function = "uartb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2_rts_n_pj6 { - nvidia,pins = "uart2_rts_n_pj6"; - nvidia,function = "uartb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2_rxd_pc3 { - nvidia,pins = "uart2_rxd_pc3"; - nvidia,function = "irda"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2_txd_pc2 { - nvidia,pins = "uart2_txd_pc2"; - nvidia,function = "irda"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart3_cts_n_pa1 { - nvidia,pins = "uart3_cts_n_pa1", - "uart3_rxd_pw7"; - nvidia,function = "uartc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart3_rts_n_pc0 { - nvidia,pins = "uart3_rts_n_pc0", - "uart3_txd_pw6"; - nvidia,function = "uartc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - owr { - nvidia,pins = "owr"; - nvidia,function = "owr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - hdmi_cec_pee3 { - nvidia,pins = "hdmi_cec_pee3"; - nvidia,function = "cec"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,lock = ; - nvidia,open-drain = ; - }; - ddc_scl_pv4 { - nvidia,pins = "ddc_scl_pv4", - "ddc_sda_pv5"; - nvidia,function = "i2c4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,lock = ; - nvidia,rcv-sel = ; - }; - spdif_in_pk6 { - nvidia,pins = "spdif_in_pk6"; - nvidia,function = "usb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,lock = ; - }; - usb_vbus_en0_pn4 { - nvidia,pins = "usb_vbus_en0_pn4"; - nvidia,function = "usb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,lock = ; - nvidia,open-drain = ; - }; - gpio_x6_aud_px6 { - nvidia,pins = "gpio_x6_aud_px6"; - nvidia,function = "spi6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_x4_aud_px4 { - nvidia,pins = "gpio_x4_aud_px4", - "gpio_x7_aud_px7"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_x5_aud_px5 { - nvidia,pins = "gpio_x5_aud_px5"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_w2_aud_pw2 { - nvidia,pins = "gpio_w2_aud_pw2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_w3_aud_pw3 { - nvidia,pins = "gpio_w3_aud_pw3"; - nvidia,function = "spi6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_x1_aud_px1 { - nvidia,pins = "gpio_x1_aud_px1"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_x3_aud_px3 { - nvidia,pins = "gpio_x3_aud_px3"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3_fs_pp0 { - nvidia,pins = "dap3_fs_pp0"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3_dout_pp2 { - nvidia,pins = "dap3_dout_pp2"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pv1 { - nvidia,pins = "pv1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pbb3 { - nvidia,pins = "pbb3", - "pbb5", - "pbb6", - "pbb7"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pcc1 { - nvidia,pins = "pcc1", - "pcc2"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad0_pg0 { - nvidia,pins = "gmi_ad0_pg0", - "gmi_ad1_pg1"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad10_ph2 { - nvidia,pins = "gmi_ad10_ph2", - "gmi_ad11_ph3", - "gmi_ad13_ph5", - "gmi_ad8_ph0", - "gmi_clk_pk1"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad2_pg2 { - nvidia,pins = "gmi_ad2_pg2", - "gmi_ad3_pg3"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_adv_n_pk0 { - nvidia,pins = "gmi_adv_n_pk0", - "gmi_cs0_n_pj0", - "gmi_cs2_n_pk3", - "gmi_cs4_n_pk2", - "gmi_cs7_n_pi6", - "gmi_dqs_p_pj3", - "gmi_iordy_pi5", - "gmi_wp_n_pc7"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_cs3_n_pk4 { - nvidia,pins = "gmi_cs3_n_pk4"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk2_req_pcc5 { - nvidia,pins = "clk2_req_pcc5"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col3_pq3 { - nvidia,pins = "kb_col3_pq3", - "kb_col6_pq6", - "kb_col7_pq7"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col5_pq5 { - nvidia,pins = "kb_col5_pq5"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row3_pr3 { - nvidia,pins = "kb_row3_pr3", - "kb_row4_pr4", - "kb_row6_pr6", - "kb_row8_ps0"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk3_req_pee1 { - nvidia,pins = "clk3_req_pee1"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu4 { - nvidia,pins = "pu4"; - nvidia,function = "displayb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu5 { - nvidia,pins = "pu5", - "pu6"; - nvidia,function = "displayb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - hdmi_int_pn7 { - nvidia,pins = "hdmi_int_pn7"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk1_req_pee2 { - nvidia,pins = "clk1_req_pee2", - "usb_vbus_en1_pn5"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - drive_sdio1 { - nvidia,pins = "drive_sdio1"; - nvidia,high-speed-mode = ; - nvidia,schmitt = ; - nvidia,pull-down-strength = <36>; - nvidia,pull-up-strength = <20>; - nvidia,slew-rate-rising = ; - nvidia,slew-rate-falling = ; - }; - drive_sdio3 { - nvidia,pins = "drive_sdio3"; - nvidia,high-speed-mode = ; - nvidia,schmitt = ; - nvidia,pull-down-strength = <22>; - nvidia,pull-up-strength = <36>; - nvidia,slew-rate-rising = ; - nvidia,slew-rate-falling = ; - }; - drive_gma { - nvidia,pins = "drive_gma"; - nvidia,high-speed-mode = ; - nvidia,schmitt = ; - nvidia,pull-down-strength = <2>; - nvidia,pull-up-strength = <1>; - nvidia,slew-rate-rising = ; - nvidia,slew-rate-falling = ; - }; - }; - }; - - serial@70006300 { - status = "okay"; - }; - - pwm@7000a000 { - status = "okay"; - }; - - i2c@7000c000 { - status = "okay"; - clock-frequency = <100000>; - - battery: smart-battery@b { - compatible = "ti,bq20z45", "sbs,sbs-battery"; - reg = <0xb>; - battery-name = "battery"; - sbs,i2c-retry-count = <2>; - sbs,poll-retry-count = <100>; - power-supplies = <&charger>; - }; - - rt5640: rt5640@1c { - compatible = "realtek,rt5640"; - reg = <0x1c>; - interrupt-parent = <&gpio>; - interrupts = ; - realtek,ldo1-en-gpios = - <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>; - }; - - temperature-sensor@4c { - compatible = "onnn,nct1008"; - reg = <0x4c>; - vcc-supply = <&palmas_ldo6_reg>; - interrupt-parent = <&gpio>; - interrupts = ; - }; - }; - - hdmi_ddc: i2c@7000c700 { - status = "okay"; - }; - - i2c@7000d000 { - status = "okay"; - clock-frequency = <400000>; - - tps51632@43 { - compatible = "ti,tps51632"; - reg = <0x43>; - regulator-name = "vdd-cpu"; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1520000>; - regulator-boot-on; - regulator-always-on; - }; - - tps65090@48 { - compatible = "ti,tps65090"; - reg = <0x48>; - interrupt-parent = <&gpio>; - interrupts = ; - - vsys1-supply = <&vdd_ac_bat_reg>; - vsys2-supply = <&vdd_ac_bat_reg>; - vsys3-supply = <&vdd_ac_bat_reg>; - infet1-supply = <&vdd_ac_bat_reg>; - infet2-supply = <&vdd_ac_bat_reg>; - infet3-supply = <&tps65090_dcdc2_reg>; - infet4-supply = <&tps65090_dcdc2_reg>; - infet5-supply = <&tps65090_dcdc2_reg>; - infet6-supply = <&tps65090_dcdc2_reg>; - infet7-supply = <&tps65090_dcdc2_reg>; - vsys-l1-supply = <&vdd_ac_bat_reg>; - vsys-l2-supply = <&vdd_ac_bat_reg>; - - charger: charger { - compatible = "ti,tps65090-charger"; - ti,enable-low-current-chrg; - }; - - regulators { - tps65090_dcdc1_reg: dcdc1 { - regulator-name = "vdd-sys-5v0"; - regulator-always-on; - regulator-boot-on; - }; - - tps65090_dcdc2_reg: dcdc2 { - regulator-name = "vdd-sys-3v3"; - regulator-always-on; - regulator-boot-on; - }; - - tps65090_dcdc3_reg: dcdc3 { - regulator-name = "vdd-ao"; - regulator-always-on; - regulator-boot-on; - }; - - vdd_bl_reg: fet1 { - regulator-name = "vdd-lcd-bl"; - }; - - fet3 { - regulator-name = "vdd-modem-3v3"; - }; - - avdd_lcd_reg: fet4 { - regulator-name = "avdd-lcd"; - }; - - fet5 { - regulator-name = "vdd-lvds"; - }; - - fet6 { - regulator-name = "vdd-sd-slot"; - regulator-always-on; - regulator-boot-on; - }; - - fet7 { - regulator-name = "vdd-com-3v3"; - }; - - ldo1 { - regulator-name = "vdd-sby-5v0"; - regulator-always-on; - regulator-boot-on; - }; - - ldo2 { - regulator-name = "vdd-sby-3v3"; - regulator-always-on; - regulator-boot-on; - }; - }; - }; - - palmas: tps65913@58 { - compatible = "ti,palmas"; - reg = <0x58>; - interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; - - #interrupt-cells = <2>; - interrupt-controller; - - ti,system-power-controller; - - palmas_gpio: gpio { - compatible = "ti,palmas-gpio"; - gpio-controller; - #gpio-cells = <2>; - }; - - pmic { - compatible = "ti,tps65913-pmic", "ti,palmas-pmic"; - smps1-in-supply = <&tps65090_dcdc3_reg>; - smps3-in-supply = <&tps65090_dcdc3_reg>; - smps4-in-supply = <&tps65090_dcdc2_reg>; - smps7-in-supply = <&tps65090_dcdc2_reg>; - smps8-in-supply = <&tps65090_dcdc2_reg>; - smps9-in-supply = <&tps65090_dcdc2_reg>; - ldo1-in-supply = <&tps65090_dcdc2_reg>; - ldo2-in-supply = <&tps65090_dcdc2_reg>; - ldo3-in-supply = <&palmas_smps3_reg>; - ldo4-in-supply = <&tps65090_dcdc2_reg>; - ldo5-in-supply = <&vdd_ac_bat_reg>; - ldo6-in-supply = <&tps65090_dcdc2_reg>; - ldo7-in-supply = <&tps65090_dcdc2_reg>; - ldo8-in-supply = <&tps65090_dcdc3_reg>; - ldo9-in-supply = <&palmas_smps9_reg>; - ldoln-in-supply = <&tps65090_dcdc1_reg>; - ldousb-in-supply = <&tps65090_dcdc1_reg>; - - regulators { - smps12 { - regulator-name = "vddio-ddr"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - - palmas_smps3_reg: smps3 { - regulator-name = "vddio-1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - smps45 { - regulator-name = "vdd-core"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-boot-on; - }; - - smps457 { - regulator-name = "vdd-core"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-boot-on; - }; - - smps8 { - regulator-name = "avdd-pll"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - regulator-always-on; - regulator-boot-on; - }; - - palmas_smps9_reg: smps9 { - regulator-name = "sdhci-vdd-sd-slot"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - ldo1 { - regulator-name = "avdd-cam1"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo2 { - regulator-name = "avdd-cam2"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - avdd_1v2_reg: ldo3 { - regulator-name = "avdd-dsi-csi"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - ldo4 { - regulator-name = "vpp-fuse"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - palmas_ldo6_reg: ldo6 { - regulator-name = "vdd-sensor-2v85"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - ldo7 { - regulator-name = "vdd-af-cam1"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo8 { - regulator-name = "vdd-rtc"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - regulator-always-on; - regulator-boot-on; - ti,enable-ldo8-tracking; - }; - - ldo9 { - regulator-name = "vddio-sdmmc-2"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - ldoln { - regulator-name = "hvdd-usb"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldousb { - regulator-name = "avdd-usb"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - regen1 { - regulator-name = "rail-3v3"; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - regen2 { - regulator-name = "rail-5v0"; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - }; - }; - - rtc { - compatible = "ti,palmas-rtc"; - interrupt-parent = <&palmas>; - interrupts = <8 0>; - }; - - pinmux { - compatible = "ti,tps65913-pinctrl"; - pinctrl-names = "default"; - pinctrl-0 = <&palmas_default>; - - palmas_default: pinmux { - pin_gpio6 { - pins = "gpio6"; - function = "gpio"; - }; - }; - }; - }; - }; - - spi@7000da00 { - status = "okay"; - spi-max-frequency = <25000000>; - spi-flash@0 { - compatible = "winbond,w25q32dw", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <20000000>; - }; - }; - - pmc@7000e400 { - nvidia,invert-interrupt; - nvidia,suspend-mode = <1>; - nvidia,cpu-pwr-good-time = <500>; - nvidia,cpu-pwr-off-time = <300>; - nvidia,core-pwr-good-time = <641 3845>; - nvidia,core-pwr-off-time = <61036>; - nvidia,core-power-req-active-high; - nvidia,sys-clock-req-active-high; - }; - - ahub@70080000 { - i2s@70080400 { - status = "okay"; - }; - }; - - sdhci@78000400 { - cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_HIGH>; - bus-width = <4>; - status = "okay"; - }; - - sdhci@78000600 { - bus-width = <8>; - status = "okay"; - non-removable; - }; - - usb@7d000000 { - compatible = "nvidia,tegra114-udc"; - status = "okay"; - dr_mode = "peripheral"; - }; - - usb-phy@7d000000 { - status = "okay"; - }; - - usb@7d008000 { - status = "okay"; - }; - - usb-phy@7d008000 { - status = "okay"; - vbus-supply = <&usb3_vbus_reg>; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - - enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; - power-supply = <&vdd_bl_reg>; - pwms = <&pwm 1 1000000>; - - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - }; - - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - home { - label = "Home"; - gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - power { - label = "Power"; - gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - - volume_down { - label = "Volume Down"; - gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - volume_up { - label = "Volume Up"; - gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - vdd_ac_bat_reg: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "vdd_ac_bat"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - dvdd_ts_reg: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "dvdd_ts"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(H, 5) GPIO_ACTIVE_HIGH>; - }; - - usb1_vbus_reg: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "usb1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; - gpio-open-drain; - vin-supply = <&tps65090_dcdc1_reg>; - }; - - usb3_vbus_reg: regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "usb2_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; - gpio-open-drain; - vin-supply = <&tps65090_dcdc1_reg>; - }; - - vdd_hdmi_reg: regulator@5 { - compatible = "regulator-fixed"; - reg = <5>; - regulator-name = "vdd_hdmi_5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&tps65090_dcdc1_reg>; - }; - - vdd_cam_1v8_reg: regulator@6 { - compatible = "regulator-fixed"; - reg = <6>; - regulator-name = "vdd_cam_1v8_reg"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - enable-active-high; - gpio = <&palmas_gpio 6 0>; - }; - - vdd_5v0_hdmi: regulator@7 { - compatible = "regulator-fixed"; - reg = <7>; - regulator-name = "VDD_5V0_HDMI_CON"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&tps65090_dcdc1_reg>; - }; - }; - - sound { - compatible = "nvidia,tegra-audio-rt5640-dalmore", - "nvidia,tegra-audio-rt5640"; - nvidia,model = "NVIDIA Tegra Dalmore"; - - nvidia,audio-routing = - "Headphones", "HPOR", - "Headphones", "HPOL", - "Speakers", "SPORP", - "Speakers", "SPORN", - "Speakers", "SPOLP", - "Speakers", "SPOLN", - "Mic Jack", "MICBIAS1", - "IN2P", "Mic Jack"; - - nvidia,i2s-controller = <&tegra_i2s1>; - nvidia,audio-codec = <&rt5640>; - - nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>; - - clocks = <&tegra_car TEGRA114_CLK_PLL_A>, - <&tegra_car TEGRA114_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA114_CLK_EXTERN1>; - clock-names = "pll_a", "pll_a_out0", "mclk"; - }; -}; diff --git a/sys/gnu/dts/arm/tegra114-roth.dts b/sys/gnu/dts/arm/tegra114-roth.dts deleted file mode 100644 index 3d3835591cd..00000000000 --- a/sys/gnu/dts/arm/tegra114-roth.dts +++ /dev/null @@ -1,1127 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include -#include "tegra114.dtsi" - -/ { - model = "NVIDIA SHIELD"; - compatible = "nvidia,roth", "nvidia,tegra114"; - - chosen { - /* SHIELD's bootloader's arguments need to be overridden */ - bootargs = "console=ttyS0,115200n8 console=tty1 gpt fbcon=rotate:1"; - /* SHIELD's bootloader will place initrd at this address */ - linux,initrd-start = <0x82000000>; - linux,initrd-end = <0x82800000>; - }; - - aliases { - serial0 = &uartd; - }; - - firmware { - trusted-foundations { - compatible = "tlm,trusted-foundations"; - tlm,version-major = <2>; - tlm,version-minor = <8>; - }; - }; - - memory@80000000 { - /* memory >= 0x79600000 is reserved for firmware usage */ - reg = <0x80000000 0x79600000>; - }; - - host1x@50000000 { - dsi@54300000 { - status = "okay"; - - vdd-supply = <&vdd_1v2_ap>; - - panel@0 { - compatible = "lg,lh500wx1-sd03"; - reg = <0>; - - power-supply = <&vdd_lcd>; - backlight = <&backlight>; - }; - }; - }; - - pinmux@70000868 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - clk1_out_pw4 { - nvidia,pins = "clk1_out_pw4"; - nvidia,function = "extperiph1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap1_din_pn1 { - nvidia,pins = "dap1_din_pn1"; - nvidia,function = "i2s0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap1_dout_pn2 { - nvidia,pins = "dap1_dout_pn2", - "dap1_fs_pn0", - "dap1_sclk_pn3"; - nvidia,function = "i2s0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap2_din_pa4 { - nvidia,pins = "dap2_din_pa4"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap2_dout_pa5 { - nvidia,pins = "dap2_dout_pa5", - "dap2_fs_pa2", - "dap2_sclk_pa3"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap4_din_pp5 { - nvidia,pins = "dap4_din_pp5", - "dap4_dout_pp6", - "dap4_fs_pp4", - "dap4_sclk_pp7"; - nvidia,function = "i2s3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dvfs_pwm_px0 { - nvidia,pins = "dvfs_pwm_px0", - "dvfs_clk_px2"; - nvidia,function = "cldvfs"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_clk_py0 { - nvidia,pins = "ulpi_clk_py0", - "ulpi_data0_po1", - "ulpi_data1_po2", - "ulpi_data2_po3", - "ulpi_data3_po4", - "ulpi_data4_po5", - "ulpi_data5_po6", - "ulpi_data6_po7", - "ulpi_data7_po0"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_dir_py1 { - nvidia,pins = "ulpi_dir_py1", - "ulpi_nxt_py2"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_stp_py3 { - nvidia,pins = "ulpi_stp_py3"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - cam_i2c_scl_pbb1 { - nvidia,pins = "cam_i2c_scl_pbb1", - "cam_i2c_sda_pbb2"; - nvidia,function = "i2c3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,lock = ; - nvidia,open-drain = ; - }; - cam_mclk_pcc0 { - nvidia,pins = "cam_mclk_pcc0", - "pbb0"; - nvidia,function = "vi_alt3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,lock = ; - }; - pbb4 { - nvidia,pins = "pbb4"; - nvidia,function = "vgp4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,lock = ; - }; - gen2_i2c_scl_pt5 { - nvidia,pins = "gen2_i2c_scl_pt5", - "gen2_i2c_sda_pt6"; - nvidia,function = "i2c2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,lock = ; - nvidia,open-drain = ; - }; - gmi_a16_pj7 { - nvidia,pins = "gmi_a16_pj7", - "gmi_a19_pk7"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_a17_pb0 { - nvidia,pins = "gmi_a17_pb0", - "gmi_a18_pb1"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad5_pg5 { - nvidia,pins = "gmi_ad5_pg5", - "gmi_wr_n_pi0"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad6_pg6 { - nvidia,pins = "gmi_ad6_pg6", - "gmi_ad7_pg7"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad12_ph4 { - nvidia,pins = "gmi_ad12_ph4"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_cs6_n_pi13 { - nvidia,pins = "gmi_cs6_n_pi3"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad9_ph1 { - nvidia,pins = "gmi_ad9_ph1"; - nvidia,function = "pwm1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_cs1_n_pj2 { - nvidia,pins = "gmi_cs1_n_pj2", - "gmi_oe_n_pi1"; - nvidia,function = "soc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_rst_n_pi4 { - nvidia,pins = "gmi_rst_n_pi4"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_iordy_pi5 { - nvidia,pins = "gmi_iordy_pi5"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk2_out_pw5 { - nvidia,pins = "clk2_out_pw5"; - nvidia,function = "extperiph2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_clk_pz0 { - nvidia,pins = "sdmmc1_clk_pz0"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_cmd_pz1 { - nvidia,pins = "sdmmc1_cmd_pz1", - "sdmmc1_dat0_py7", - "sdmmc1_dat1_py6", - "sdmmc1_dat2_py5", - "sdmmc1_dat3_py4"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_clk_pa6 { - nvidia,pins = "sdmmc3_clk_pa6"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_cmd_pa7 { - nvidia,pins = "sdmmc3_cmd_pa7", - "sdmmc3_dat0_pb7", - "sdmmc3_dat1_pb6", - "sdmmc3_dat2_pb5", - "sdmmc3_dat3_pb4", - "sdmmc3_cd_n_pv2", - "sdmmc3_clk_lb_out_pee4", - "sdmmc3_clk_lb_in_pee5"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col4_pq4 { - nvidia,pins = "kb_col4_pq4"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_clk_pcc4 { - nvidia,pins = "sdmmc4_clk_pcc4"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_cmd_pt7 { - nvidia,pins = "sdmmc4_cmd_pt7", - "sdmmc4_dat0_paa0", - "sdmmc4_dat1_paa1", - "sdmmc4_dat2_paa2", - "sdmmc4_dat3_paa3", - "sdmmc4_dat4_paa4", - "sdmmc4_dat5_paa5", - "sdmmc4_dat6_paa6", - "sdmmc4_dat7_paa7"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk_32k_out_pa0 { - nvidia,pins = "clk_32k_out_pa0"; - nvidia,function = "blink"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col0_pq0 { - nvidia,pins = "kb_col0_pq0", - "kb_col1_pq1", - "kb_col2_pq2", - "kb_row0_pr0", - "kb_row1_pr1", - "kb_row2_pr2", - "kb_row8_ps0"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row7_pr7 { - nvidia,pins = "kb_row7_pr7"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row10_ps2 { - nvidia,pins = "kb_row10_ps2"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row9_ps1 { - nvidia,pins = "kb_row9_ps1"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pwr_i2c_scl_pz6 { - nvidia,pins = "pwr_i2c_scl_pz6", - "pwr_i2c_sda_pz7"; - nvidia,function = "i2cpwr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,lock = ; - nvidia,open-drain = ; - }; - sys_clk_req_pz5 { - nvidia,pins = "sys_clk_req_pz5"; - nvidia,function = "sysclk"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - core_pwr_req { - nvidia,pins = "core_pwr_req"; - nvidia,function = "pwron"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - cpu_pwr_req { - nvidia,pins = "cpu_pwr_req"; - nvidia,function = "cpu"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pwr_int_n { - nvidia,pins = "pwr_int_n"; - nvidia,function = "pmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - reset_out_n { - nvidia,pins = "reset_out_n"; - nvidia,function = "reset_out_n"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk3_out_pee0 { - nvidia,pins = "clk3_out_pee0"; - nvidia,function = "extperiph3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gen1_i2c_scl_pc4 { - nvidia,pins = "gen1_i2c_scl_pc4", - "gen1_i2c_sda_pc5"; - nvidia,function = "i2c1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,lock = ; - nvidia,open-drain = ; - }; - uart2_cts_n_pj5 { - nvidia,pins = "uart2_cts_n_pj5"; - nvidia,function = "uartb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2_rts_n_pj6 { - nvidia,pins = "uart2_rts_n_pj6"; - nvidia,function = "uartb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2_rxd_pc3 { - nvidia,pins = "uart2_rxd_pc3"; - nvidia,function = "irda"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2_txd_pc2 { - nvidia,pins = "uart2_txd_pc2"; - nvidia,function = "irda"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart3_cts_n_pa1 { - nvidia,pins = "uart3_cts_n_pa1", - "uart3_rxd_pw7"; - nvidia,function = "uartc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart3_rts_n_pc0 { - nvidia,pins = "uart3_rts_n_pc0", - "uart3_txd_pw6"; - nvidia,function = "uartc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - owr { - nvidia,pins = "owr"; - nvidia,function = "owr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - hdmi_cec_pee3 { - nvidia,pins = "hdmi_cec_pee3"; - nvidia,function = "cec"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,lock = ; - nvidia,open-drain = ; - }; - ddc_scl_pv4 { - nvidia,pins = "ddc_scl_pv4", - "ddc_sda_pv5"; - nvidia,function = "i2c4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,lock = ; - nvidia,rcv-sel = ; - }; - spdif_in_pk6 { - nvidia,pins = "spdif_in_pk6"; - nvidia,function = "usb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,lock = ; - }; - usb_vbus_en0_pn4 { - nvidia,pins = "usb_vbus_en0_pn4"; - nvidia,function = "usb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,lock = ; - nvidia,open-drain = ; - }; - gpio_x6_aud_px6 { - nvidia,pins = "gpio_x6_aud_px6"; - nvidia,function = "spi6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_x1_aud_px1 { - nvidia,pins = "gpio_x1_aud_px1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_x7_aud_px7 { - nvidia,pins = "gpio_x7_aud_px7"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_adv_n_pk0 { - nvidia,pins = "gmi_adv_n_pk0"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_cs0_n_pj0 { - nvidia,pins = "gmi_cs0_n_pj0"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu3 { - nvidia,pins = "pu3"; - nvidia,function = "pwm0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_x4_aud_px4 { - nvidia,pins = "gpio_x4_aud_px4", - "gpio_x5_aud_px5"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_x3_aud_px3 { - nvidia,pins = "gpio_x3_aud_px3"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_w2_aud_pw2 { - nvidia,pins = "gpio_w2_aud_pw2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_w3_aud_pw3 { - nvidia,pins = "gpio_w3_aud_pw3"; - nvidia,function = "spi6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3_fs_pp0 { - nvidia,pins = "dap3_fs_pp0", - "dap3_din_pp1", - "dap3_dout_pp2", - "dap3_sclk_pp3"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pv0 { - nvidia,pins = "pv0"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pv1 { - nvidia,pins = "pv1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pbb3 { - nvidia,pins = "pbb3", - "pbb5", - "pbb6", - "pbb7"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pcc1 { - nvidia,pins = "pcc1", - "pcc2"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad0_pg0 { - nvidia,pins = "gmi_ad0_pg0", - "gmi_ad1_pg1"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad10_ph2 { - nvidia,pins = "gmi_ad10_ph2", - "gmi_ad12_ph4", - "gmi_ad15_ph7", - "gmi_cs3_n_pk4"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad11_ph3 { - nvidia,pins = "gmi_ad11_ph3", - "gmi_ad13_ph5", - "gmi_ad8_ph0", - "gmi_clk_pk1", - "gmi_cs2_n_pk3"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad14_ph6 { - nvidia,pins = "gmi_ad14_ph6", - "gmi_cs0_n_pj0", - "gmi_cs4_n_pk2", - "gmi_cs7_n_pi6", - "gmi_dqs_p_pj3", - "gmi_wp_n_pc7"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad2_pg2 { - nvidia,pins = "gmi_ad2_pg2", - "gmi_ad3_pg3"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_wp_n_pv3 { - nvidia,pins = "sdmmc1_wp_n_pv3"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk2_req_pcc5 { - nvidia,pins = "clk2_req_pcc5"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col3_pq3 { - nvidia,pins = "kb_col3_pq3"; - nvidia,function = "pwm2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col5_pq5 { - nvidia,pins = "kb_col5_pq5"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col6_pq6 { - nvidia,pins = "kb_col6_pq6", - "kb_col7_pq7"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row3_pr3 { - nvidia,pins = "kb_row3_pr3", - "kb_row4_pr4", - "kb_row6_pr6"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk3_req_pee1 { - nvidia,pins = "clk3_req_pee1"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu2 { - nvidia,pins = "pu2"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - hdmi_int_pn7 { - nvidia,pins = "hdmi_int_pn7"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - drive_sdio1 { - nvidia,pins = "drive_sdio1"; - nvidia,high-speed-mode = ; - nvidia,schmitt = ; - nvidia,pull-down-strength = <36>; - nvidia,pull-up-strength = <20>; - nvidia,slew-rate-rising = ; - nvidia,slew-rate-falling = ; - }; - drive_sdio3 { - nvidia,pins = "drive_sdio3"; - nvidia,high-speed-mode = ; - nvidia,schmitt = ; - nvidia,pull-down-strength = <36>; - nvidia,pull-up-strength = <20>; - nvidia,slew-rate-rising = ; - nvidia,slew-rate-falling = ; - }; - drive_gma { - nvidia,pins = "drive_gma"; - nvidia,high-speed-mode = ; - nvidia,schmitt = ; - nvidia,pull-down-strength = <2>; - nvidia,pull-up-strength = <2>; - nvidia,slew-rate-rising = ; - nvidia,slew-rate-falling = ; - }; - }; - }; - - /* Usable on reworked devices only */ - serial@70006300 { - status = "okay"; - }; - - pwm@7000a000 { - status = "okay"; - }; - - i2c@7000d000 { - status = "okay"; - clock-frequency = <400000>; - - regulator@43 { - compatible = "ti,tps51632"; - reg = <0x43>; - regulator-name = "vdd-cpu"; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1520000>; - regulator-always-on; - regulator-boot-on; - }; - - palmas: pmic@58 { - compatible = "ti,palmas"; - reg = <0x58>; - interrupts = ; - - #interrupt-cells = <2>; - interrupt-controller; - - ti,system-power-controller; - - palmas_gpio: gpio { - compatible = "ti,palmas-gpio"; - gpio-controller; - #gpio-cells = <2>; - }; - - pmic { - compatible = "ti,tps65913-pmic", "ti,palmas-pmic"; - - regulators { - smps12 { - regulator-name = "vdd-ddr"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_1v8: smps3 { - regulator-name = "vdd-1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - }; - - smps457 { - regulator-name = "vdd-soc"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-boot-on; - }; - - smps8 { - regulator-name = "avdd-pll-1v05"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - regulator-always-on; - regulator-boot-on; - }; - - smps9 { - regulator-name = "vdd-2v85-emmc"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - smps10_out1 { - regulator-name = "vdd-fan"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - smps10_out2 { - regulator-name = "vdd-5v0-sys"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo2 { - regulator-name = "vdd-2v8-display"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_1v2_ap: ldo3 { - regulator-name = "avdd-1v2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo4 { - regulator-name = "vpp-fuse"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo5 { - regulator-name = "avdd-hdmi-pll"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - ldo6 { - regulator-name = "vdd-sensor-2v8"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - ldo8 { - regulator-name = "vdd-rtc"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - regulator-boot-on; - ti,enable-ldo8-tracking; - }; - - vddio_sdmmc3: ldo9 { - regulator-name = "vddio-sdmmc3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - ldousb { - regulator-name = "avdd-usb-hdmi"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_3v3_sys: regen1 { - regulator-name = "rail-3v3"; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - regen2 { - regulator-name = "rail-5v0"; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - }; - }; - - rtc { - compatible = "ti,palmas-rtc"; - interrupt-parent = <&palmas>; - interrupts = <8 0>; - }; - - }; - }; - - pmc@7000e400 { - nvidia,invert-interrupt; - }; - - /* SD card */ - sdhci@78000400 { - status = "okay"; - bus-width = <4>; - vqmmc-supply = <&vddio_sdmmc3>; - cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; - power-gpios = <&gpio TEGRA_GPIO(H, 0) GPIO_ACTIVE_HIGH>; - }; - - /* eMMC */ - sdhci@78000600 { - status = "okay"; - bus-width = <8>; - non-removable; - }; - - /* External USB port (must be powered) */ - usb@7d000000 { - status = "okay"; - }; - - usb-phy@7d000000 { - status = "okay"; - nvidia,xcvr-setup = <7>; - nvidia,xcvr-lsfslew = <2>; - nvidia,xcvr-lsrslew = <2>; - interrupts = ; - /* Should be changed to "otg" once we have vbus_supply */ - /* As of now, USB devices need to be powered externally */ - dr_mode = "host"; - }; - - /* SHIELD controller */ - usb@7d008000 { - status = "okay"; - }; - - usb-phy@7d008000 { - status = "okay"; - nvidia,xcvr-setup = <7>; - nvidia,xcvr-lsfslew = <2>; - nvidia,xcvr-lsrslew = <2>; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 1 40000>; - - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - - power-supply = <&lcd_bl_en>; - enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; - }; - - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - back { - label = "Back"; - gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - home { - label = "Home"; - gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - power { - label = "Power"; - gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - lcd_bl_en: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "lcd_bl_en"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - }; - - vdd_lcd: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "vdd_lcd_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vdd_1v8>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>; - regulator-boot-on; - }; - - regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "vdd_1v8_ts"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio TEGRA_GPIO(K, 3) GPIO_ACTIVE_LOW>; - regulator-boot-on; - }; - - regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "vdd_3v3_ts"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(H, 5) GPIO_ACTIVE_HIGH>; - regulator-boot-on; - }; - - regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "vdd_1v8_com"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vdd_1v8>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(X, 1) GPIO_ACTIVE_HIGH>; - regulator-boot-on; - }; - - regulator@5 { - compatible = "regulator-fixed"; - reg = <5>; - regulator-name = "vdd_3v3_com"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vdd_3v3_sys>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_HIGH>; - regulator-always-on; - regulator-boot-on; - }; - }; -}; diff --git a/sys/gnu/dts/arm/tegra114-tn7.dts b/sys/gnu/dts/arm/tegra114-tn7.dts deleted file mode 100644 index bfdd1bf6181..00000000000 --- a/sys/gnu/dts/arm/tegra114-tn7.dts +++ /dev/null @@ -1,352 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include -#include "tegra114.dtsi" - -/ { - model = "Tegra Note 7"; - compatible = "nvidia,tn7", "nvidia,tegra114"; - - chosen { - /* TN7's bootloader's arguments need to be overridden */ - bootargs = "console=ttyS0,115200n8 console=tty1 gpt fbcon=rotate:2"; - /* TN7's bootloader will place initrd at this address */ - linux,initrd-start = <0x82000000>; - linux,initrd-end = <0x82800000>; - }; - - aliases { - serial0 = &uartd; - }; - - firmware { - trusted-foundations { - compatible = "tlm,trusted-foundations"; - tlm,version-major = <2>; - tlm,version-minor = <8>; - }; - }; - - memory@80000000 { - /* memory >= 0x37e00000 is reserved for firmware usage */ - reg = <0x80000000 0x37e00000>; - }; - - host1x@50000000 { - dsi@54300000 { - status = "okay"; - - vdd-supply = <&vdd_1v2_ap>; - - panel@0 { - compatible = "lg,ld070wx3-sl01"; - reg = <0>; - - power-supply = <&vdd_lcd>; - backlight = <&backlight>; - }; - }; - }; - - serial@70006300 { - status = "okay"; - }; - - pwm@7000a000 { - status = "okay"; - }; - - i2c@7000d000 { - status = "okay"; - clock-frequency = <400000>; - - palmas: pmic@58 { - compatible = "ti,palmas"; - reg = <0x58>; - interrupts = ; - - #interrupt-cells = <2>; - interrupt-controller; - - ti,system-power-controller; - - palmas_gpio: gpio { - compatible = "ti,palmas-gpio"; - gpio-controller; - #gpio-cells = <2>; - }; - - pmic { - compatible = "ti,tps65913-pmic", "ti,palmas-pmic"; - - ldoln-in-supply = <&vdd_smps10_out2>; - - regulators { - smps123 { - regulator-name = "vd-cpu"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-boot-on; - }; - - smps45 { - regulator-name = "vd-soc"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - regulator-boot-on; - }; - - smps6 { - regulator-name = "va-lcd-hv"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - regulator-boot-on; - }; - - smps7 { - regulator-name = "vd-ddr"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_1v8: smps8 { - regulator-name = "vs-pmu-1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_2v9_sys: smps9 { - regulator-name = "vs-sys-2v9"; - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_smps10_out1: smps10_out1 { - regulator-name = "vd-smps10-out1"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_smps10_out2: smps10_out2 { - regulator-name = "vd-smps10-out2"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo1 { - regulator-name = "va-pllx"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_1v2_ap: ldo2 { - regulator-name = "va-ap-1v2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo3 { - regulator-name = "vd-fuse"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo4 { - regulator-name = "vd-ts-hv"; - regulator-min-microvolt = <3200000>; - regulator-max-microvolt = <3200000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo5 { - regulator-name = "va-cam2-hv"; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; - - ldo6 { - regulator-name = "va-sns-hv"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - ldo7 { - regulator-name = "va-cam1-hv"; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; - - ldo8 { - regulator-name = "va-ap-rtc"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - ti,enable-ldo8-tracking; - regulator-always-on; - regulator-boot-on; - }; - - ldo9 { - regulator-name = "vi-sdcard"; - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - }; - - ldousb { - regulator-name = "avdd-usb"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - ldoln { - regulator-name = "va-hdmi"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - }; - }; - - rtc { - compatible = "ti,palmas-rtc"; - interrupt-parent = <&palmas>; - interrupts = <8 0>; - }; - - }; - }; - - pmc@7000e400 { - nvidia,invert-interrupt; - }; - - /* eMMC */ - sdhci@78000600 { - status = "okay"; - bus-width = <8>; - non-removable; - }; - - usb@7d000000 { - status = "okay"; - }; - - usb-phy@7d000000 { - status = "okay"; - nvidia,xcvr-setup = <7>; - nvidia,xcvr-lsfslew = <2>; - nvidia,xcvr-lsrslew = <2>; - interrupts = ; - /* Should be changed to "otg" once we have vbus_supply */ - /* As of now, USB devices need to be powered externally */ - dr_mode = "host"; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 1 40000>; - - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - - power-supply = <&lcd_bl_en>; - }; - - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - power { - label = "Power"; - gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - - volume_down { - label = "Volume Down"; - gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - volume_up { - label = "Volume Up"; - gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - /* FIXME: output of BQ24192 */ - vs_sys: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "VS_SYS"; - regulator-min-microvolt = <4200000>; - regulator-max-microvolt = <4200000>; - regulator-always-on; - regulator-boot-on; - }; - - lcd_bl_en: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "VDD_LCD_BL"; - regulator-min-microvolt = <16500000>; - regulator-max-microvolt = <16500000>; - gpio = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vs_sys>; - regulator-boot-on; - }; - - vdd_lcd: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "VD_LCD_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&palmas_gpio 4 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_1v8>; - regulator-boot-on; - }; - }; -}; diff --git a/sys/gnu/dts/arm/tegra114.dtsi b/sys/gnu/dts/arm/tegra114.dtsi deleted file mode 100644 index 0d7a6327e40..00000000000 --- a/sys/gnu/dts/arm/tegra114.dtsi +++ /dev/null @@ -1,798 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include -#include -#include -#include -#include - -/ { - compatible = "nvidia,tegra114"; - interrupt-parent = <&lic>; - #address-cells = <1>; - #size-cells = <1>; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x0>; - }; - - host1x@50000000 { - compatible = "nvidia,tegra114-host1x", "simple-bus"; - reg = <0x50000000 0x00028000>; - interrupts = , /* syncpt */ - ; /* general */ - clocks = <&tegra_car TEGRA114_CLK_HOST1X>; - resets = <&tegra_car 28>; - reset-names = "host1x"; - iommus = <&mc TEGRA_SWGROUP_HC>; - - #address-cells = <1>; - #size-cells = <1>; - - ranges = <0x54000000 0x54000000 0x01000000>; - - gr2d@54140000 { - compatible = "nvidia,tegra114-gr2d", "nvidia,tegra20-gr2d"; - reg = <0x54140000 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA114_CLK_GR2D>; - resets = <&tegra_car 21>; - reset-names = "2d"; - - iommus = <&mc TEGRA_SWGROUP_G2>; - }; - - gr3d@54180000 { - compatible = "nvidia,tegra114-gr3d", "nvidia,tegra20-gr3d"; - reg = <0x54180000 0x00040000>; - clocks = <&tegra_car TEGRA114_CLK_GR3D>; - resets = <&tegra_car 24>; - reset-names = "3d"; - - iommus = <&mc TEGRA_SWGROUP_NV>; - }; - - dc@54200000 { - compatible = "nvidia,tegra114-dc", "nvidia,tegra20-dc"; - reg = <0x54200000 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA114_CLK_DISP1>, - <&tegra_car TEGRA114_CLK_PLL_P>; - clock-names = "dc", "parent"; - resets = <&tegra_car 27>; - reset-names = "dc"; - - iommus = <&mc TEGRA_SWGROUP_DC>; - - nvidia,head = <0>; - - rgb { - status = "disabled"; - }; - }; - - dc@54240000 { - compatible = "nvidia,tegra114-dc", "nvidia,tegra20-dc"; - reg = <0x54240000 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA114_CLK_DISP2>, - <&tegra_car TEGRA114_CLK_PLL_P>; - clock-names = "dc", "parent"; - resets = <&tegra_car 26>; - reset-names = "dc"; - - iommus = <&mc TEGRA_SWGROUP_DCB>; - - nvidia,head = <1>; - - rgb { - status = "disabled"; - }; - }; - - hdmi@54280000 { - compatible = "nvidia,tegra114-hdmi"; - reg = <0x54280000 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA114_CLK_HDMI>, - <&tegra_car TEGRA114_CLK_PLL_D2_OUT0>; - clock-names = "hdmi", "parent"; - resets = <&tegra_car 51>; - reset-names = "hdmi"; - status = "disabled"; - }; - - dsi@54300000 { - compatible = "nvidia,tegra114-dsi"; - reg = <0x54300000 0x00040000>; - clocks = <&tegra_car TEGRA114_CLK_DSIA>, - <&tegra_car TEGRA114_CLK_DSIALP>, - <&tegra_car TEGRA114_CLK_PLL_D_OUT0>; - clock-names = "dsi", "lp", "parent"; - resets = <&tegra_car 48>; - reset-names = "dsi"; - nvidia,mipi-calibrate = <&mipi 0x060>; /* DSIA & DSIB pads */ - status = "disabled"; - - #address-cells = <1>; - #size-cells = <0>; - }; - - dsi@54400000 { - compatible = "nvidia,tegra114-dsi"; - reg = <0x54400000 0x00040000>; - clocks = <&tegra_car TEGRA114_CLK_DSIB>, - <&tegra_car TEGRA114_CLK_DSIBLP>, - <&tegra_car TEGRA114_CLK_PLL_D2_OUT0>; - clock-names = "dsi", "lp", "parent"; - resets = <&tegra_car 82>; - reset-names = "dsi"; - nvidia,mipi-calibrate = <&mipi 0x180>; /* DSIC & DSID pads */ - status = "disabled"; - - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - gic: interrupt-controller@50041000 { - compatible = "arm,cortex-a15-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x50041000 0x1000>, - <0x50042000 0x1000>, - <0x50044000 0x2000>, - <0x50046000 0x2000>; - interrupts = ; - interrupt-parent = <&gic>; - }; - - lic: interrupt-controller@60004000 { - compatible = "nvidia,tegra114-ictlr", "nvidia,tegra30-ictlr"; - reg = <0x60004000 0x100>, - <0x60004100 0x50>, - <0x60004200 0x50>, - <0x60004300 0x50>, - <0x60004400 0x50>; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - }; - - timer@60005000 { - compatible = "nvidia,tegra114-timer", "nvidia,tegra30-timer", "nvidia,tegra20-timer"; - reg = <0x60005000 0x400>; - interrupts = , - , - , - , - , - ; - clocks = <&tegra_car TEGRA114_CLK_TIMER>; - }; - - tegra_car: clock@60006000 { - compatible = "nvidia,tegra114-car"; - reg = <0x60006000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - flow-controller@60007000 { - compatible = "nvidia,tegra114-flowctrl"; - reg = <0x60007000 0x1000>; - }; - - apbdma: dma@6000a000 { - compatible = "nvidia,tegra114-apbdma"; - reg = <0x6000a000 0x1400>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - clocks = <&tegra_car TEGRA114_CLK_APBDMA>; - resets = <&tegra_car 34>; - reset-names = "dma"; - #dma-cells = <1>; - }; - - ahb: ahb@6000c000 { - compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb"; - reg = <0x6000c000 0x150>; - }; - - gpio: gpio@6000d000 { - compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio"; - reg = <0x6000d000 0x1000>; - interrupts = , - , - , - , - , - , - , - ; - #gpio-cells = <2>; - gpio-controller; - #interrupt-cells = <2>; - interrupt-controller; - /* - gpio-ranges = <&pinmux 0 0 246>; - */ - }; - - apbmisc@70000800 { - compatible = "nvidia,tegra114-apbmisc", "nvidia,tegra20-apbmisc"; - reg = <0x70000800 0x64 /* Chip revision */ - 0x70000008 0x04>; /* Strapping options */ - }; - - pinmux: pinmux@70000868 { - compatible = "nvidia,tegra114-pinmux"; - reg = <0x70000868 0x148 /* Pad control registers */ - 0x70003000 0x40c>; /* Mux registers */ - }; - - /* - * There are two serial driver i.e. 8250 based simple serial - * driver and APB DMA based serial driver for higher baudrate - * and performace. To enable the 8250 based driver, the compatible - * is "nvidia,tegra114-uart", "nvidia,tegra20-uart" and to enable - * the APB DMA based serial driver, the compatible is - * "nvidia,tegra114-hsuart", "nvidia,tegra30-hsuart". - */ - uarta: serial@70006000 { - compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; - reg = <0x70006000 0x40>; - reg-shift = <2>; - interrupts = ; - clocks = <&tegra_car TEGRA114_CLK_UARTA>; - resets = <&tegra_car 6>; - reset-names = "serial"; - dmas = <&apbdma 8>, <&apbdma 8>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uartb: serial@70006040 { - compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; - reg = <0x70006040 0x40>; - reg-shift = <2>; - interrupts = ; - clocks = <&tegra_car TEGRA114_CLK_UARTB>; - resets = <&tegra_car 7>; - reset-names = "serial"; - dmas = <&apbdma 9>, <&apbdma 9>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uartc: serial@70006200 { - compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; - reg = <0x70006200 0x100>; - reg-shift = <2>; - interrupts = ; - clocks = <&tegra_car TEGRA114_CLK_UARTC>; - resets = <&tegra_car 55>; - reset-names = "serial"; - dmas = <&apbdma 10>, <&apbdma 10>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uartd: serial@70006300 { - compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; - reg = <0x70006300 0x100>; - reg-shift = <2>; - interrupts = ; - clocks = <&tegra_car TEGRA114_CLK_UARTD>; - resets = <&tegra_car 65>; - reset-names = "serial"; - dmas = <&apbdma 19>, <&apbdma 19>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - pwm: pwm@7000a000 { - compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm"; - reg = <0x7000a000 0x100>; - #pwm-cells = <2>; - clocks = <&tegra_car TEGRA114_CLK_PWM>; - resets = <&tegra_car 17>; - reset-names = "pwm"; - status = "disabled"; - }; - - i2c@7000c000 { - compatible = "nvidia,tegra114-i2c"; - reg = <0x7000c000 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA114_CLK_I2C1>; - clock-names = "div-clk"; - resets = <&tegra_car 12>; - reset-names = "i2c"; - dmas = <&apbdma 21>, <&apbdma 21>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c@7000c400 { - compatible = "nvidia,tegra114-i2c"; - reg = <0x7000c400 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA114_CLK_I2C2>; - clock-names = "div-clk"; - resets = <&tegra_car 54>; - reset-names = "i2c"; - dmas = <&apbdma 22>, <&apbdma 22>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c@7000c500 { - compatible = "nvidia,tegra114-i2c"; - reg = <0x7000c500 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA114_CLK_I2C3>; - clock-names = "div-clk"; - resets = <&tegra_car 67>; - reset-names = "i2c"; - dmas = <&apbdma 23>, <&apbdma 23>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c@7000c700 { - compatible = "nvidia,tegra114-i2c"; - reg = <0x7000c700 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA114_CLK_I2C4>; - clock-names = "div-clk"; - resets = <&tegra_car 103>; - reset-names = "i2c"; - dmas = <&apbdma 26>, <&apbdma 26>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c@7000d000 { - compatible = "nvidia,tegra114-i2c"; - reg = <0x7000d000 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA114_CLK_I2C5>; - clock-names = "div-clk"; - resets = <&tegra_car 47>; - reset-names = "i2c"; - dmas = <&apbdma 24>, <&apbdma 24>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi@7000d400 { - compatible = "nvidia,tegra114-spi"; - reg = <0x7000d400 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA114_CLK_SBC1>; - clock-names = "spi"; - resets = <&tegra_car 41>; - reset-names = "spi"; - dmas = <&apbdma 15>, <&apbdma 15>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi@7000d600 { - compatible = "nvidia,tegra114-spi"; - reg = <0x7000d600 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA114_CLK_SBC2>; - clock-names = "spi"; - resets = <&tegra_car 44>; - reset-names = "spi"; - dmas = <&apbdma 16>, <&apbdma 16>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi@7000d800 { - compatible = "nvidia,tegra114-spi"; - reg = <0x7000d800 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA114_CLK_SBC3>; - clock-names = "spi"; - resets = <&tegra_car 46>; - reset-names = "spi"; - dmas = <&apbdma 17>, <&apbdma 17>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi@7000da00 { - compatible = "nvidia,tegra114-spi"; - reg = <0x7000da00 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA114_CLK_SBC4>; - clock-names = "spi"; - resets = <&tegra_car 68>; - reset-names = "spi"; - dmas = <&apbdma 18>, <&apbdma 18>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi@7000dc00 { - compatible = "nvidia,tegra114-spi"; - reg = <0x7000dc00 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA114_CLK_SBC5>; - clock-names = "spi"; - resets = <&tegra_car 104>; - reset-names = "spi"; - dmas = <&apbdma 27>, <&apbdma 27>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi@7000de00 { - compatible = "nvidia,tegra114-spi"; - reg = <0x7000de00 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA114_CLK_SBC6>; - clock-names = "spi"; - resets = <&tegra_car 105>; - reset-names = "spi"; - dmas = <&apbdma 28>, <&apbdma 28>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - rtc@7000e000 { - compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc"; - reg = <0x7000e000 0x100>; - interrupts = ; - clocks = <&tegra_car TEGRA114_CLK_RTC>; - }; - - kbc@7000e200 { - compatible = "nvidia,tegra114-kbc"; - reg = <0x7000e200 0x100>; - interrupts = ; - clocks = <&tegra_car TEGRA114_CLK_KBC>; - resets = <&tegra_car 36>; - reset-names = "kbc"; - status = "disabled"; - }; - - pmc@7000e400 { - compatible = "nvidia,tegra114-pmc"; - reg = <0x7000e400 0x400>; - clocks = <&tegra_car TEGRA114_CLK_PCLK>, <&clk32k_in>; - clock-names = "pclk", "clk32k_in"; - }; - - fuse@7000f800 { - compatible = "nvidia,tegra114-efuse"; - reg = <0x7000f800 0x400>; - clocks = <&tegra_car TEGRA114_CLK_FUSE>; - clock-names = "fuse"; - resets = <&tegra_car 39>; - reset-names = "fuse"; - }; - - mc: memory-controller@70019000 { - compatible = "nvidia,tegra114-mc"; - reg = <0x70019000 0x1000>; - clocks = <&tegra_car TEGRA114_CLK_MC>; - clock-names = "mc"; - - interrupts = ; - - #iommu-cells = <1>; - }; - - ahub@70080000 { - compatible = "nvidia,tegra114-ahub"; - reg = <0x70080000 0x200>, - <0x70080200 0x100>, - <0x70081000 0x200>; - interrupts = ; - clocks = <&tegra_car TEGRA114_CLK_D_AUDIO>, - <&tegra_car TEGRA114_CLK_APBIF>; - clock-names = "d_audio", "apbif"; - resets = <&tegra_car 106>, /* d_audio */ - <&tegra_car 107>, /* apbif */ - <&tegra_car 30>, /* i2s0 */ - <&tegra_car 11>, /* i2s1 */ - <&tegra_car 18>, /* i2s2 */ - <&tegra_car 101>, /* i2s3 */ - <&tegra_car 102>, /* i2s4 */ - <&tegra_car 108>, /* dam0 */ - <&tegra_car 109>, /* dam1 */ - <&tegra_car 110>, /* dam2 */ - <&tegra_car 10>, /* spdif */ - <&tegra_car 153>, /* amx */ - <&tegra_car 154>; /* adx */ - reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", - "i2s3", "i2s4", "dam0", "dam1", "dam2", - "spdif", "amx", "adx"; - dmas = <&apbdma 1>, <&apbdma 1>, - <&apbdma 2>, <&apbdma 2>, - <&apbdma 3>, <&apbdma 3>, - <&apbdma 4>, <&apbdma 4>, - <&apbdma 6>, <&apbdma 6>, - <&apbdma 7>, <&apbdma 7>, - <&apbdma 12>, <&apbdma 12>, - <&apbdma 13>, <&apbdma 13>, - <&apbdma 14>, <&apbdma 14>, - <&apbdma 29>, <&apbdma 29>; - dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2", - "rx3", "tx3", "rx4", "tx4", "rx5", "tx5", - "rx6", "tx6", "rx7", "tx7", "rx8", "tx8", - "rx9", "tx9"; - ranges; - #address-cells = <1>; - #size-cells = <1>; - - tegra_i2s0: i2s@70080300 { - compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; - reg = <0x70080300 0x100>; - nvidia,ahub-cif-ids = <4 4>; - clocks = <&tegra_car TEGRA114_CLK_I2S0>; - resets = <&tegra_car 30>; - reset-names = "i2s"; - status = "disabled"; - }; - - tegra_i2s1: i2s@70080400 { - compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; - reg = <0x70080400 0x100>; - nvidia,ahub-cif-ids = <5 5>; - clocks = <&tegra_car TEGRA114_CLK_I2S1>; - resets = <&tegra_car 11>; - reset-names = "i2s"; - status = "disabled"; - }; - - tegra_i2s2: i2s@70080500 { - compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; - reg = <0x70080500 0x100>; - nvidia,ahub-cif-ids = <6 6>; - clocks = <&tegra_car TEGRA114_CLK_I2S2>; - resets = <&tegra_car 18>; - reset-names = "i2s"; - status = "disabled"; - }; - - tegra_i2s3: i2s@70080600 { - compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; - reg = <0x70080600 0x100>; - nvidia,ahub-cif-ids = <7 7>; - clocks = <&tegra_car TEGRA114_CLK_I2S3>; - resets = <&tegra_car 101>; - reset-names = "i2s"; - status = "disabled"; - }; - - tegra_i2s4: i2s@70080700 { - compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; - reg = <0x70080700 0x100>; - nvidia,ahub-cif-ids = <8 8>; - clocks = <&tegra_car TEGRA114_CLK_I2S4>; - resets = <&tegra_car 102>; - reset-names = "i2s"; - status = "disabled"; - }; - }; - - mipi: mipi@700e3000 { - compatible = "nvidia,tegra114-mipi"; - reg = <0x700e3000 0x100>; - clocks = <&tegra_car TEGRA114_CLK_MIPI_CAL>; - #nvidia,mipi-calibrate-cells = <1>; - }; - - sdhci@78000000 { - compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; - reg = <0x78000000 0x200>; - interrupts = ; - clocks = <&tegra_car TEGRA114_CLK_SDMMC1>; - resets = <&tegra_car 14>; - reset-names = "sdhci"; - status = "disabled"; - }; - - sdhci@78000200 { - compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; - reg = <0x78000200 0x200>; - interrupts = ; - clocks = <&tegra_car TEGRA114_CLK_SDMMC2>; - resets = <&tegra_car 9>; - reset-names = "sdhci"; - status = "disabled"; - }; - - sdhci@78000400 { - compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; - reg = <0x78000400 0x200>; - interrupts = ; - clocks = <&tegra_car TEGRA114_CLK_SDMMC3>; - resets = <&tegra_car 69>; - reset-names = "sdhci"; - status = "disabled"; - }; - - sdhci@78000600 { - compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; - reg = <0x78000600 0x200>; - interrupts = ; - clocks = <&tegra_car TEGRA114_CLK_SDMMC4>; - resets = <&tegra_car 15>; - reset-names = "sdhci"; - status = "disabled"; - }; - - usb@7d000000 { - compatible = "nvidia,tegra114-ehci", "nvidia,tegra30-ehci", "usb-ehci"; - reg = <0x7d000000 0x4000>; - interrupts = ; - phy_type = "utmi"; - clocks = <&tegra_car TEGRA114_CLK_USBD>; - resets = <&tegra_car 22>; - reset-names = "usb"; - nvidia,phy = <&phy1>; - status = "disabled"; - }; - - phy1: usb-phy@7d000000 { - compatible = "nvidia,tegra114-usb-phy", "nvidia,tegra30-usb-phy"; - reg = <0x7d000000 0x4000 0x7d000000 0x4000>; - phy_type = "utmi"; - clocks = <&tegra_car TEGRA114_CLK_USBD>, - <&tegra_car TEGRA114_CLK_PLL_U>, - <&tegra_car TEGRA114_CLK_USBD>; - clock-names = "reg", "pll_u", "utmi-pads"; - resets = <&tegra_car 22>, <&tegra_car 22>; - reset-names = "usb", "utmi-pads"; - nvidia,hssync-start-delay = <0>; - nvidia,idle-wait-delay = <17>; - nvidia,elastic-limit = <16>; - nvidia,term-range-adj = <6>; - nvidia,xcvr-setup = <9>; - nvidia,xcvr-lsfslew = <0>; - nvidia,xcvr-lsrslew = <3>; - nvidia,hssquelch-level = <2>; - nvidia,hsdiscon-level = <5>; - nvidia,xcvr-hsslew = <12>; - nvidia,has-utmi-pad-registers; - status = "disabled"; - }; - - usb@7d008000 { - compatible = "nvidia,tegra114-ehci", "nvidia,tegra30-ehci", "usb-ehci"; - reg = <0x7d008000 0x4000>; - interrupts = ; - phy_type = "utmi"; - clocks = <&tegra_car TEGRA114_CLK_USB3>; - resets = <&tegra_car 59>; - reset-names = "usb"; - nvidia,phy = <&phy3>; - status = "disabled"; - }; - - phy3: usb-phy@7d008000 { - compatible = "nvidia,tegra114-usb-phy", "nvidia,tegra30-usb-phy"; - reg = <0x7d008000 0x4000 0x7d000000 0x4000>; - phy_type = "utmi"; - clocks = <&tegra_car TEGRA114_CLK_USB3>, - <&tegra_car TEGRA114_CLK_PLL_U>, - <&tegra_car TEGRA114_CLK_USBD>; - clock-names = "reg", "pll_u", "utmi-pads"; - resets = <&tegra_car 59>, <&tegra_car 22>; - reset-names = "usb", "utmi-pads"; - nvidia,hssync-start-delay = <0>; - nvidia,idle-wait-delay = <17>; - nvidia,elastic-limit = <16>; - nvidia,term-range-adj = <6>; - nvidia,xcvr-setup = <9>; - nvidia,xcvr-lsfslew = <0>; - nvidia,xcvr-lsrslew = <3>; - nvidia,hssquelch-level = <2>; - nvidia,hsdiscon-level = <5>; - nvidia,xcvr-hsslew = <12>; - status = "disabled"; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <1>; - }; - - cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <2>; - }; - - cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <3>; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = - , - , - , - ; - interrupt-parent = <&gic>; - }; -}; diff --git a/sys/gnu/dts/arm/tegra124-apalis-emc.dtsi b/sys/gnu/dts/arm/tegra124-apalis-emc.dtsi deleted file mode 100644 index 32401457ae7..00000000000 --- a/sys/gnu/dts/arm/tegra124-apalis-emc.dtsi +++ /dev/null @@ -1,1467 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR X11 -/* - * Copyright 2016-2019 Toradex AG - * - */ - -/ { - clock@60006000 { - emc-timings-1 { - nvidia,ram-code = <1>; - - timing-12750000 { - clock-frequency = <12750000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - timing-20400000 { - clock-frequency = <20400000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - timing-40800000 { - clock-frequency = <40800000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - timing-68000000 { - clock-frequency = <68000000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - timing-102000000 { - clock-frequency = <102000000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - timing-204000000 { - clock-frequency = <204000000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - timing-300000000 { - clock-frequency = <300000000>; - nvidia,parent-clock-frequency = <600000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_C>; - clock-names = "emc-parent"; - }; - timing-396000000 { - clock-frequency = <396000000>; - nvidia,parent-clock-frequency = <792000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_M>; - clock-names = "emc-parent"; - }; - timing-528000000 { - clock-frequency = <528000000>; - nvidia,parent-clock-frequency = <528000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; - clock-names = "emc-parent"; - }; - timing-600000000 { - clock-frequency = <600000000>; - nvidia,parent-clock-frequency = <600000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_C_UD>; - clock-names = "emc-parent"; - }; - timing-792000000 { - clock-frequency = <792000000>; - nvidia,parent-clock-frequency = <792000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; - clock-names = "emc-parent"; - }; - timing-924000000 { - clock-frequency = <924000000>; - nvidia,parent-clock-frequency = <924000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; - clock-names = "emc-parent"; - }; - }; - }; - - external-memory-controller@7001b000 { - emc-timings-1 { - nvidia,ram-code = <1>; - - timing-12750000 { - clock-frequency = <12750000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000e000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000000 0x00000003 - 0x00000000 0x00000000 - 0x00000000 0x00000004 - 0x0000000a 0x00000005 - 0x0000000b 0x00000000 - 0x00000000 0x00000003 - 0x00000003 0x00000000 - 0x00000006 0x00000006 - 0x00000006 0x00000002 - 0x00000000 0x00000005 - 0x00000005 0x00010000 - 0x00000003 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000004 - 0x0000000c 0x0000000d - 0x0000000f 0x00000060 - 0x00000000 0x00000018 - 0x00000002 0x00000002 - 0x00000001 0x00000000 - 0x00000007 0x0000000f - 0x00000005 0x00000005 - 0x00000004 0x00000005 - 0x00000004 0x00000000 - 0x00000000 0x00000005 - 0x00000005 0x00000064 - 0x00000000 0x00000000 - 0x00000000 0x106aa298 - 0x002c00a0 0x00008000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x000fc000 0x000fc000 - 0x000fc000 0x000fc000 - 0x0000fc00 0x0000fc00 - 0x0000fc00 0x0000fc00 - 0x10000280 0x00000000 - 0x00111111 0x00000000 - 0x00000000 0x77ffc081 - 0x00000e0e 0x81f1f108 - 0x07070004 0x0000003f - 0x016eeeee 0x51451400 - 0x00514514 0x00514514 - 0x51451400 0x0000003f - 0x00000007 0x00000000 - 0x00000042 0x000e000e - 0x00000000 0x00000003 - 0x0000f2f3 0x800001c5 - 0x0000000a - >; - }; - - timing-20400000 { - clock-frequency = <20400000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000e000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000000 0x00000005 - 0x00000000 0x00000000 - 0x00000000 0x00000004 - 0x0000000a 0x00000005 - 0x0000000b 0x00000000 - 0x00000000 0x00000003 - 0x00000003 0x00000000 - 0x00000006 0x00000006 - 0x00000006 0x00000002 - 0x00000000 0x00000005 - 0x00000005 0x00010000 - 0x00000003 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000004 - 0x0000000c 0x0000000d - 0x0000000f 0x0000009a - 0x00000000 0x00000026 - 0x00000002 0x00000002 - 0x00000001 0x00000000 - 0x00000007 0x0000000f - 0x00000006 0x00000006 - 0x00000004 0x00000005 - 0x00000004 0x00000000 - 0x00000000 0x00000005 - 0x00000005 0x000000a0 - 0x00000000 0x00000000 - 0x00000000 0x106aa298 - 0x002c00a0 0x00008000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x000fc000 0x000fc000 - 0x000fc000 0x000fc000 - 0x0000fc00 0x0000fc00 - 0x0000fc00 0x0000fc00 - 0x10000280 0x00000000 - 0x00111111 0x00000000 - 0x00000000 0x77ffc081 - 0x00000e0e 0x81f1f108 - 0x07070004 0x0000003f - 0x016eeeee 0x51451400 - 0x00514514 0x00514514 - 0x51451400 0x0000003f - 0x0000000b 0x00000000 - 0x00000042 0x000e000e - 0x00000000 0x00000003 - 0x0000f2f3 0x8000023a - 0x0000000a - >; - }; - - timing-40800000 { - clock-frequency = <40800000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000e000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000001 0x0000000a - 0x00000000 0x00000001 - 0x00000000 0x00000004 - 0x0000000a 0x00000005 - 0x0000000b 0x00000000 - 0x00000000 0x00000003 - 0x00000003 0x00000000 - 0x00000006 0x00000006 - 0x00000006 0x00000002 - 0x00000000 0x00000005 - 0x00000005 0x00010000 - 0x00000003 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000004 - 0x0000000c 0x0000000d - 0x0000000f 0x00000134 - 0x00000000 0x0000004d - 0x00000002 0x00000002 - 0x00000001 0x00000000 - 0x00000008 0x0000000f - 0x0000000c 0x0000000c - 0x00000004 0x00000005 - 0x00000004 0x00000000 - 0x00000000 0x00000005 - 0x00000005 0x0000013f - 0x00000000 0x00000000 - 0x00000000 0x106aa298 - 0x002c00a0 0x00008000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x000fc000 0x000fc000 - 0x000fc000 0x000fc000 - 0x0000fc00 0x0000fc00 - 0x0000fc00 0x0000fc00 - 0x10000280 0x00000000 - 0x00111111 0x00000000 - 0x00000000 0x77ffc081 - 0x00000e0e 0x81f1f108 - 0x07070004 0x0000003f - 0x016eeeee 0x51451400 - 0x00514514 0x00514514 - 0x51451400 0x0000003f - 0x00000015 0x00000000 - 0x00000042 0x000e000e - 0x00000000 0x00000003 - 0x0000f2f3 0x80000370 - 0x0000000a - >; - }; - - timing-68000000 { - clock-frequency = <68000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000e000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000003 0x00000011 - 0x00000000 0x00000002 - 0x00000000 0x00000004 - 0x0000000a 0x00000005 - 0x0000000b 0x00000000 - 0x00000000 0x00000003 - 0x00000003 0x00000000 - 0x00000006 0x00000006 - 0x00000006 0x00000002 - 0x00000000 0x00000005 - 0x00000005 0x00010000 - 0x00000003 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000004 - 0x0000000c 0x0000000d - 0x0000000f 0x00000202 - 0x00000000 0x00000080 - 0x00000002 0x00000002 - 0x00000001 0x00000000 - 0x0000000f 0x0000000f - 0x00000013 0x00000013 - 0x00000004 0x00000005 - 0x00000004 0x00000001 - 0x00000000 0x00000005 - 0x00000005 0x00000213 - 0x00000000 0x00000000 - 0x00000000 0x106aa298 - 0x002c00a0 0x00008000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x000fc000 0x000fc000 - 0x000fc000 0x000fc000 - 0x0000fc00 0x0000fc00 - 0x0000fc00 0x0000fc00 - 0x10000280 0x00000000 - 0x00111111 0x00000000 - 0x00000000 0x77ffc081 - 0x00000e0e 0x81f1f108 - 0x07070004 0x0000003f - 0x016eeeee 0x51451400 - 0x00514514 0x00514514 - 0x51451400 0x0000003f - 0x00000022 0x00000000 - 0x00000042 0x000e000e - 0x00000000 0x00000003 - 0x0000f2f3 0x8000050e - 0x0000000a - >; - }; - - timing-102000000 { - clock-frequency = <102000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000e000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000004 0x0000001a - 0x00000000 0x00000003 - 0x00000001 0x00000004 - 0x0000000a 0x00000005 - 0x0000000b 0x00000001 - 0x00000001 0x00000003 - 0x00000003 0x00000000 - 0x00000006 0x00000006 - 0x00000006 0x00000002 - 0x00000000 0x00000005 - 0x00000005 0x00010000 - 0x00000003 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000004 - 0x0000000c 0x0000000d - 0x0000000f 0x00000304 - 0x00000000 0x000000c1 - 0x00000002 0x00000002 - 0x00000001 0x00000000 - 0x00000018 0x0000000f - 0x0000001c 0x0000001c - 0x00000004 0x00000005 - 0x00000004 0x00000002 - 0x00000000 0x00000005 - 0x00000005 0x0000031c - 0x00000000 0x00000000 - 0x00000000 0x106aa298 - 0x002c00a0 0x00008000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x000fc000 0x000fc000 - 0x000fc000 0x000fc000 - 0x0000fc00 0x0000fc00 - 0x0000fc00 0x0000fc00 - 0x10000280 0x00000000 - 0x00111111 0x00000000 - 0x00000000 0x77ffc081 - 0x00000e0e 0x81f1f108 - 0x07070004 0x0000003f - 0x016eeeee 0x51451400 - 0x00514514 0x00514514 - 0x51451400 0x0000003f - 0x00000033 0x00000000 - 0x00000042 0x000e000e - 0x00000000 0x00000003 - 0x0000f2f3 0x80000713 - 0x0000000a - >; - }; - - timing-204000000 { - clock-frequency = <204000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008cd>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000e000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x00000009 0x00000035 - 0x00000000 0x00000006 - 0x00000002 0x00000005 - 0x0000000a 0x00000005 - 0x0000000b 0x00000002 - 0x00000002 0x00000003 - 0x00000003 0x00000000 - 0x00000005 0x00000005 - 0x00000006 0x00000002 - 0x00000000 0x00000004 - 0x00000006 0x00010000 - 0x00000003 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000003 - 0x0000000d 0x0000000f - 0x00000011 0x00000607 - 0x00000000 0x00000181 - 0x00000002 0x00000002 - 0x00000001 0x00000000 - 0x00000032 0x0000000f - 0x00000038 0x00000038 - 0x00000004 0x00000005 - 0x00000004 0x00000006 - 0x00000000 0x00000005 - 0x00000005 0x00000638 - 0x00000000 0x00000000 - 0x00000000 0x106aa298 - 0x002c00a0 0x00008000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00008000 0x00000000 - 0x00000000 0x00008000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00090000 0x00090000 - 0x00090000 0x00090000 - 0x00009000 0x00009000 - 0x00009000 0x00009000 - 0x10000280 0x00000000 - 0x00111111 0x00000000 - 0x00000000 0x77ffc081 - 0x00000707 0x81f1f108 - 0x07070004 0x0000003f - 0x016eeeee 0x51451400 - 0x00514514 0x00514514 - 0x51451400 0x0000003f - 0x00000066 0x00000000 - 0x00000100 0x000e000e - 0x00000000 0x00000003 - 0x0000d2b3 0x80000d22 - 0x0000000a - >; - }; - - timing-300000000 { - clock-frequency = <300000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73340000>; - nvidia,emc-cfg-2 = <0x000008d5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200000>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000321>; - nvidia,emc-mrs-wait-cnt = <0x0173000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x01231339>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x0000000d 0x0000004d - 0x00000000 0x00000009 - 0x00000003 0x00000004 - 0x00000008 0x00000002 - 0x00000009 0x00000003 - 0x00000003 0x00000002 - 0x00000002 0x00000000 - 0x00000003 0x00000003 - 0x00000005 0x00000002 - 0x00000000 0x00000002 - 0x00000007 0x00020000 - 0x00000003 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000001 - 0x0000000e 0x00000010 - 0x00000012 0x000008e4 - 0x00000000 0x00000239 - 0x00000001 0x00000008 - 0x00000001 0x00000000 - 0x0000004b 0x0000000e - 0x00000052 0x00000200 - 0x00000004 0x00000005 - 0x00000004 0x00000008 - 0x00000000 0x00000005 - 0x00000005 0x00000924 - 0x00000000 0x00000000 - 0x00000000 0x104ab098 - 0x002c00a0 0x00008000 - 0x00030000 0x00030000 - 0x00030000 0x00030000 - 0x00030000 0x00030000 - 0x00030000 0x00030000 - 0x00030000 0x00030000 - 0x00030000 0x00030000 - 0x00030000 0x00030000 - 0x00030000 0x00030000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00098000 0x00098000 - 0x00000000 0x00098000 - 0x00098000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00050000 0x00050000 - 0x00050000 0x00050000 - 0x00005000 0x00005000 - 0x00005000 0x00005000 - 0x10000280 0x00000000 - 0x00111111 0x00000000 - 0x00000000 0x77ffc081 - 0x00000505 0x81f1f108 - 0x07070004 0x00000000 - 0x016eeeee 0x51451420 - 0x00514514 0x00514514 - 0x51451400 0x0000003f - 0x00000096 0x00000000 - 0x00000100 0x0173000e - 0x00000000 0x00000003 - 0x000052a3 0x800012d7 - 0x00000009 - >; - }; - - timing-396000000 { - clock-frequency = <396000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73340000>; - nvidia,emc-cfg-2 = <0x00000895>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200000>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000521>; - nvidia,emc-mrs-wait-cnt = <0x015b000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040008>; - nvidia,emc-xm2dqspadctrl2 = <0x01231339>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x00000011 0x00000066 - 0x00000000 0x0000000c - 0x00000004 0x00000004 - 0x00000008 0x00000002 - 0x0000000a 0x00000004 - 0x00000004 0x00000002 - 0x00000002 0x00000000 - 0x00000003 0x00000003 - 0x00000005 0x00000002 - 0x00000000 0x00000001 - 0x00000008 0x00020000 - 0x00000003 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x0000000f 0x00000010 - 0x00000012 0x00000bd1 - 0x00000000 0x000002f4 - 0x00000001 0x00000008 - 0x00000001 0x00000000 - 0x00000063 0x0000000f - 0x0000006c 0x00000200 - 0x00000004 0x00000005 - 0x00000004 0x0000000b - 0x00000000 0x00000005 - 0x00000005 0x00000c11 - 0x00000000 0x00000000 - 0x00000000 0x104ab098 - 0x002c00a0 0x00008000 - 0x00030000 0x00030000 - 0x00030000 0x00030000 - 0x00030000 0x00030000 - 0x00030000 0x00030000 - 0x00030000 0x00030000 - 0x00030000 0x00030000 - 0x00030000 0x00030000 - 0x00030000 0x00030000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00070000 0x00070000 - 0x00000000 0x00070000 - 0x00070000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00038000 0x00038000 - 0x00038000 0x00038000 - 0x00003800 0x00003800 - 0x00003800 0x00003800 - 0x10000280 0x00000000 - 0x00111111 0x00000000 - 0x00000000 0x77ffc081 - 0x00000505 0x81f1f108 - 0x07070004 0x00000000 - 0x016eeeee 0x51451420 - 0x00514514 0x00514514 - 0x51451400 0x0000003f - 0x000000c6 0x00000000 - 0x00000100 0x015b000e - 0x00000000 0x00000003 - 0x000052a3 0x8000188b - 0x00000009 - >; - }; - - timing-528000000 { - clock-frequency = <528000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73300000>; - nvidia,emc-cfg-2 = <0x0000089d>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000941>; - nvidia,emc-mrs-wait-cnt = <0x0139000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040008>; - nvidia,emc-xm2dqspadctrl2 = <0x0123133d>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x00000018 0x00000088 - 0x00000000 0x00000010 - 0x00000006 0x00000006 - 0x00000009 0x00000002 - 0x0000000d 0x00000006 - 0x00000006 0x00000002 - 0x00000002 0x00000000 - 0x00000003 0x00000003 - 0x00000006 0x00000002 - 0x00000000 0x00000001 - 0x00000009 0x00030000 - 0x00000003 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000010 0x00000012 - 0x00000014 0x00000fd6 - 0x00000000 0x000003f5 - 0x00000002 0x0000000b - 0x00000001 0x00000000 - 0x00000085 0x00000012 - 0x00000090 0x00000200 - 0x00000004 0x00000005 - 0x00000004 0x00000010 - 0x00000000 0x00000006 - 0x00000006 0x00001017 - 0x00000000 0x00000000 - 0x00000000 0x104ab098 - 0xe01200b1 0x00008000 - 0x0000000a 0x0000000a - 0x0000000a 0x0000000a - 0x0000000a 0x0000000a - 0x0000000a 0x0000000a - 0x0000000a 0x0000000a - 0x0000000a 0x0000000a - 0x0000000a 0x0000000a - 0x0000000a 0x0000000a - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00054000 0x00054000 - 0x00000000 0x00054000 - 0x00054000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x0000000c 0x0000000c - 0x0000000c 0x0000000c - 0x0000000c 0x0000000c - 0x0000000c 0x0000000c - 0x100002a0 0x00000000 - 0x00111111 0x00000000 - 0x00000000 0x77ffc085 - 0x00000505 0x81f1f108 - 0x07070004 0x00000000 - 0x016eeeee 0x51451420 - 0x00514514 0x00514514 - 0x51451400 0x0606003f - 0x00000000 0x00000000 - 0x00000100 0x0139000e - 0x00000000 0x00000003 - 0x000042a0 0x80002062 - 0x0000000a - >; - }; - - timing-600000000 { - clock-frequency = <600000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73300000>; - nvidia,emc-cfg-2 = <0x0000089d>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200010>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000b61>; - nvidia,emc-mrs-wait-cnt = <0x0127000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040008>; - nvidia,emc-xm2dqspadctrl2 = <0x0121113d>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x0000001b 0x0000009b - 0x00000000 0x00000013 - 0x00000007 0x00000007 - 0x0000000b 0x00000003 - 0x00000010 0x00000007 - 0x00000007 0x00000002 - 0x00000002 0x00000000 - 0x00000005 0x00000005 - 0x0000000a 0x00000002 - 0x00000000 0x00000003 - 0x0000000b 0x00070000 - 0x00000003 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000002 - 0x00000012 0x00000016 - 0x00000018 0x00001208 - 0x00000000 0x00000482 - 0x00000002 0x0000000d - 0x00000001 0x00000000 - 0x00000097 0x00000015 - 0x000000a3 0x00000200 - 0x00000004 0x00000005 - 0x00000004 0x00000013 - 0x00000000 0x00000006 - 0x00000006 0x00001248 - 0x00000000 0x00000000 - 0x00000000 0x104ab098 - 0xe00e00b1 0x00008000 - 0x0000000a 0x0000000a - 0x0000000a 0x0000000a - 0x0000000a 0x0000000a - 0x0000000a 0x0000000a - 0x0000000a 0x0000000a - 0x0000000a 0x0000000a - 0x0000000a 0x0000000a - 0x0000000a 0x0000000a - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00048000 0x00048000 - 0x00000000 0x00048000 - 0x00048000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x0000000d 0x0000000d - 0x0000000d 0x0000000d - 0x0000000d 0x0000000d - 0x0000000d 0x0000000d - 0x100002a0 0x00000000 - 0x00111111 0x00000000 - 0x00000000 0x77ffc085 - 0x00000505 0x81f1f108 - 0x07070004 0x00000000 - 0x016eeeee 0x51451420 - 0x00514514 0x00514514 - 0x51451400 0x0606003f - 0x00000000 0x00000000 - 0x00000100 0x0127000e - 0x00000000 0x00000003 - 0x000040a0 0x800024aa - 0x0000000e - >; - }; - - timing-792000000 { - clock-frequency = <792000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73300000>; - nvidia,emc-cfg-2 = <0x0000089d>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200018>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000d71>; - nvidia,emc-mrs-wait-cnt = <0x00f7000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040000>; - nvidia,emc-xm2dqspadctrl2 = <0x0120113d>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x00000024 0x000000cd - 0x00000000 0x00000019 - 0x0000000a 0x00000008 - 0x0000000d 0x00000004 - 0x00000013 0x0000000a - 0x0000000a 0x00000004 - 0x00000002 0x00000000 - 0x00000006 0x00000006 - 0x0000000b 0x00000002 - 0x00000000 0x00000002 - 0x0000000d 0x00080000 - 0x00000004 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000001 - 0x00000014 0x00000018 - 0x0000001a 0x000017e2 - 0x00000000 0x000005f8 - 0x00000003 0x00000011 - 0x00000001 0x00000000 - 0x000000c7 0x00000018 - 0x000000d7 0x00000200 - 0x00000005 0x00000006 - 0x00000005 0x00000019 - 0x00000000 0x00000008 - 0x00000008 0x00001822 - 0x00000000 0x00000000 - 0x00000000 0x104ab098 - 0xe00700b1 0x00008000 - 0x007fc008 0x007fc008 - 0x007fc008 0x007fc008 - 0x007fc008 0x007fc008 - 0x007fc008 0x007fc008 - 0x007fc008 0x007fc008 - 0x007fc008 0x007fc008 - 0x007fc008 0x007fc008 - 0x007fc008 0x007fc008 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00034000 0x00034000 - 0x00000000 0x00034000 - 0x00034000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000005 0x00000005 - 0x00000005 0x00000005 - 0x00000005 0x00000005 - 0x00000005 0x00000005 - 0x00000005 0x00000005 - 0x00000005 0x00000005 - 0x00000005 0x00000005 - 0x00000005 0x00000005 - 0x0000000a 0x0000000a - 0x0000000a 0x0000000a - 0x0000000a 0x0000000a - 0x0000000a 0x0000000a - 0x100002a0 0x00000000 - 0x00111111 0x00000000 - 0x00000000 0x77ffc085 - 0x00000000 0x81f1f108 - 0x07070004 0x00000000 - 0x016eeeee 0x61861820 - 0x00514514 0x00514514 - 0x61861800 0x0606003f - 0x00000000 0x00000000 - 0x00000100 0x00f7000e - 0x00000000 0x00000004 - 0x00004080 0x80003012 - 0x0000000f - >; - }; - - timing-924000000 { - clock-frequency = <924000000>; - - nvidia,emc-auto-cal-config = <0xa1430303>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73300000>; - nvidia,emc-cfg-2 = <0x0000089d>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200020>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000f15>; - nvidia,emc-mrs-wait-cnt = <0x00cd000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040000>; - nvidia,emc-xm2dqspadctrl2 = <0x0120113d>; - nvidia,emc-zcal-cnt-long = <0x0000004c>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x0000002b 0x000000f0 - 0x00000000 0x0000001e - 0x0000000b 0x00000009 - 0x0000000f 0x00000005 - 0x00000016 0x0000000b - 0x0000000b 0x00000004 - 0x00000002 0x00000000 - 0x00000007 0x00000007 - 0x0000000d 0x00000002 - 0x00000000 0x00000002 - 0x0000000f 0x000a0000 - 0x00000004 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000001 - 0x00000016 0x0000001a - 0x0000001c 0x00001be7 - 0x00000000 0x000006f9 - 0x00000004 0x00000015 - 0x00000001 0x00000000 - 0x000000e7 0x0000001b - 0x000000fb 0x00000200 - 0x00000006 0x00000007 - 0x00000006 0x0000001e - 0x00000000 0x0000000a - 0x0000000a 0x00001c28 - 0x00000000 0x00000000 - 0x00000000 0x104ab898 - 0xe00400b1 0x00008000 - 0x007f800a 0x007f800a - 0x007f800a 0x007f800a - 0x007f800a 0x007f800a - 0x007f800a 0x007f800a - 0x007f800a 0x007f800a - 0x007f800a 0x007f800a - 0x007f800a 0x007f800a - 0x007f800a 0x007f800a - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x0002c000 0x0002c000 - 0x00000000 0x0002c000 - 0x0002c000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000004 0x00000004 - 0x00000004 0x00000004 - 0x00000004 0x00000004 - 0x00000004 0x00000004 - 0x00000004 0x00000004 - 0x00000004 0x00000004 - 0x00000004 0x00000004 - 0x00000004 0x00000004 - 0x00000008 0x00000008 - 0x00000008 0x00000008 - 0x00000008 0x00000008 - 0x00000008 0x00000008 - 0x100002a0 0x00000000 - 0x00111111 0x00000000 - 0x00000000 0x77ffc085 - 0x00000000 0x81f1f108 - 0x07070004 0x00000000 - 0x016eeeee 0x5d75d720 - 0x00514514 0x00514514 - 0x5d75d700 0x0606003f - 0x00000000 0x00000000 - 0x00000128 0x00cd000e - 0x00000000 0x00000004 - 0x00004080 0x800037ea - 0x00000011 - >; - }; - - }; - }; - - memory-controller@70019000 { - emc-timings-1 { - nvidia,ram-code = <1>; - - timing-12750000 { - clock-frequency = <12750000>; - - nvidia,emem-configuration = < - 0x40040001 0x8000000a - 0x00000001 0x00000001 - 0x00000002 0x00000000 - 0x00000002 0x00000001 - 0x00000003 0x00000008 - 0x00000003 0x00000002 - 0x00000003 0x00000006 - 0x06030203 0x000a0502 - 0x77e30303 0x70000f03 - 0x001f0000 - >; - }; - - timing-20400000 { - clock-frequency = <20400000>; - - nvidia,emem-configuration = < - 0x40020001 0x80000012 - 0x00000001 0x00000001 - 0x00000002 0x00000000 - 0x00000002 0x00000001 - 0x00000003 0x00000008 - 0x00000003 0x00000002 - 0x00000003 0x00000006 - 0x06030203 0x000a0502 - 0x76230303 0x70000f03 - 0x001f0000 - >; - }; - - timing-40800000 { - clock-frequency = <40800000>; - - nvidia,emem-configuration = < - 0xa0000001 0x80000017 - 0x00000001 0x00000001 - 0x00000002 0x00000000 - 0x00000002 0x00000001 - 0x00000003 0x00000008 - 0x00000003 0x00000002 - 0x00000003 0x00000006 - 0x06030203 0x000a0502 - 0x74a30303 0x70000f03 - 0x001f0000 - >; - }; - - timing-68000000 { - clock-frequency = <68000000>; - - nvidia,emem-configuration = < - 0x00000001 0x8000001e - 0x00000001 0x00000001 - 0x00000002 0x00000000 - 0x00000002 0x00000001 - 0x00000003 0x00000008 - 0x00000003 0x00000002 - 0x00000003 0x00000006 - 0x06030203 0x000a0502 - 0x74230403 0x70000f03 - 0x001f0000 - >; - }; - - timing-102000000 { - clock-frequency = <102000000>; - - nvidia,emem-configuration = < - 0x08000001 0x80000026 - 0x00000001 0x00000001 - 0x00000003 0x00000000 - 0x00000002 0x00000001 - 0x00000003 0x00000008 - 0x00000003 0x00000002 - 0x00000003 0x00000006 - 0x06030203 0x000a0503 - 0x73c30504 0x70000f03 - 0x001f0000 - >; - }; - - timing-204000000 { - clock-frequency = <204000000>; - - nvidia,emem-configuration = < - 0x01000003 0x80000040 - 0x00000001 0x00000001 - 0x00000004 0x00000002 - 0x00000003 0x00000001 - 0x00000003 0x00000008 - 0x00000003 0x00000002 - 0x00000004 0x00000006 - 0x06040203 0x000a0504 - 0x73840a05 0x70000f03 - 0x001f0000 - >; - }; - - timing-300000000 { - clock-frequency = <300000000>; - - nvidia,emem-configuration = < - 0x08000004 0x80000040 - 0x00000001 0x00000002 - 0x00000007 0x00000004 - 0x00000004 0x00000001 - 0x00000002 0x00000007 - 0x00000002 0x00000002 - 0x00000004 0x00000006 - 0x06040202 0x000b0607 - 0x77450e08 0x70000f03 - 0x001f0000 - >; - }; - - timing-396000000 { - clock-frequency = <396000000>; - - nvidia,emem-configuration = < - 0x0f000005 0x80000040 - 0x00000001 0x00000002 - 0x00000009 0x00000005 - 0x00000006 0x00000001 - 0x00000002 0x00000008 - 0x00000002 0x00000002 - 0x00000004 0x00000006 - 0x06040202 0x000d0709 - 0x7586120a 0x70000f03 - 0x001f0000 - >; - }; - - timing-528000000 { - clock-frequency = <528000000>; - - nvidia,emem-configuration = < - 0x0f000007 0x80000040 - 0x00000002 0x00000003 - 0x0000000c 0x00000007 - 0x00000008 0x00000001 - 0x00000002 0x00000009 - 0x00000002 0x00000002 - 0x00000005 0x00000006 - 0x06050202 0x0010090c - 0x7428180d 0x70000f03 - 0x001f0000 - >; - }; - - timing-600000000 { - clock-frequency = <600000000>; - - nvidia,emem-configuration = < - 0x00000009 0x80000040 - 0x00000003 0x00000004 - 0x0000000e 0x00000009 - 0x0000000a 0x00000001 - 0x00000003 0x0000000b - 0x00000002 0x00000002 - 0x00000005 0x00000007 - 0x07050202 0x00130b0e - 0x73a91b0f 0x70000f03 - 0x001f0000 - >; - }; - - timing-792000000 { - clock-frequency = <792000000>; - - nvidia,emem-configuration = < - 0x0e00000b 0x80000040 - 0x00000004 0x00000005 - 0x00000013 0x0000000c - 0x0000000d 0x00000002 - 0x00000003 0x0000000c - 0x00000002 0x00000002 - 0x00000006 0x00000008 - 0x08060202 0x00170e13 - 0x736c2414 0x70000f02 - 0x001f0000 - >; - }; - - timing-924000000 { - clock-frequency = <924000000>; - - nvidia,emem-configuration = < - 0x0e00000d 0x80000040 - 0x00000005 0x00000006 - 0x00000016 0x0000000e - 0x0000000f 0x00000002 - 0x00000004 0x0000000e - 0x00000002 0x00000002 - 0x00000006 0x00000009 - 0x09060202 0x001a1016 - 0x734e2a17 0x70000f02 - 0x001f0000 - >; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/tegra124-apalis-eval.dts b/sys/gnu/dts/arm/tegra124-apalis-eval.dts deleted file mode 100644 index ceb3f6388c7..00000000000 --- a/sys/gnu/dts/arm/tegra124-apalis-eval.dts +++ /dev/null @@ -1,255 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR X11 -/* - * Copyright 2016-2019 Toradex AG - */ - -/dts-v1/; - -#include -#include "tegra124-apalis.dtsi" - -/ { - model = "Toradex Apalis TK1 on Apalis Evaluation Board"; - compatible = "toradex,apalis-tk1-eval", "toradex,apalis-tk1", - "nvidia,tegra124"; - - aliases { - rtc0 = "/i2c@7000c000/rtc@68"; - rtc1 = "/i2c@7000d000/pmic@40"; - rtc2 = "/rtc@7000e000"; - serial0 = &uarta; - serial1 = &uartb; - serial2 = &uartc; - serial3 = &uartd; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - pcie@1003000 { - pci@1,0 { - status = "okay"; - }; - }; - - host1x@50000000 { - hdmi@54280000 { - status = "okay"; - hdmi-supply = <®_5v0>; - }; - }; - - /* Apalis UART1 */ - serial@70006000 { - status = "okay"; - }; - - /* Apalis UART2 */ - serial@70006040 { - status = "okay"; - }; - - /* Apalis UART3 */ - serial@70006200 { - status = "okay"; - }; - - /* Apalis UART4 */ - serial@70006300 { - status = "okay"; - }; - - pwm@7000a000 { - status = "okay"; - }; - - /* - * GEN1_I2C: I2C1_SDA/SCL on MXM3 pin 209/211 (e.g. RTC on carrier - * board) - */ - i2c@7000c000 { - status = "okay"; - clock-frequency = <400000>; - - pcie-switch@58 { - compatible = "plx,pex8605"; - reg = <0x58>; - }; - - /* M41T0M6 real time clock on carrier board */ - rtc@68 { - compatible = "st,m41t0"; - reg = <0x68>; - }; - }; - - /* - * GEN2_I2C: I2C2_SDA/SCL (DDC) on MXM3 pin 205/207 (e.g. display EDID) - */ - i2c@7000c400 { - status = "okay"; - }; - - /* - * CAM_I2C: I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor - * on carrier board) - */ - i2c@7000c500 { - status = "okay"; - clock-frequency = <400000>; - }; - - /* I2C4 (DDC): unused */ - - /* SPI1: Apalis SPI1 */ - spi@7000d400 { - status = "okay"; - spi-max-frequency = <50000000>; - }; - - /* SPI4: Apalis SPI2 */ - spi@7000da00 { - status = "okay"; - spi-max-frequency = <50000000>; - }; - - /* Apalis Serial ATA */ - sata@70020000 { - status = "okay"; - target-5v-supply = <®_5v0>; - target-12v-supply = <®_12v0>; - }; - - hda@70030000 { - status = "okay"; - }; - - usb@70090000 { - status = "okay"; - }; - - /* Apalis MMC1 */ - sdhci@700b0000 { - status = "okay"; - bus-width = <4>; - /* MMC1_CD# */ - cd-gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>; - vqmmc-supply = <&vddio_sdmmc1>; - }; - - /* Apalis SD1 */ - sdhci@700b0400 { - status = "okay"; - bus-width = <4>; - /* SD1_CD# */ - cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; - vqmmc-supply = <&vddio_sdmmc3>; - }; - - /* EHCI instance 0: USB1_DP/N -> USBO1_DP/N */ - usb@7d000000 { - status = "okay"; - dr_mode = "otg"; - }; - - usb-phy@7d000000 { - status = "okay"; - vbus-supply = <®_usbo1_vbus>; - }; - - /* EHCI instance 1: USB2_DP/N -> USBH2_DP/N */ - usb@7d004000 { - status = "okay"; - }; - - usb-phy@7d004000 { - status = "okay"; - vbus-supply = <®_usbh_vbus>; - }; - - /* EHCI instance 2: USB3_DP/N -> USBH4_DP/N */ - usb@7d008000 { - status = "okay"; - }; - - usb-phy@7d008000 { - status = "okay"; - vbus-supply = <®_usbh_vbus>; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - brightness-levels = <255 231 223 207 191 159 127 0>; - default-brightness-level = <6>; - /* BKL1_ON */ - enable-gpios = <&gpio TEGRA_GPIO(BB, 5) GPIO_ACTIVE_HIGH>; - power-supply = <®_3v3>; - pwms = <&pwm 3 5000000>; /* BKL1_PWM */ - }; - - gpio-keys { - compatible = "gpio-keys"; - - wakeup { - label = "WAKE1_MICO"; - gpios = <&gpio TEGRA_GPIO(DD, 3) GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <10>; - wakeup-source; - }; - }; - - reg_3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "3.3V_SW"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_5v0: regulator-5v0 { - compatible = "regulator-fixed"; - regulator-name = "5V_SW"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_12v0: regulator-12v0 { - compatible = "regulator-fixed"; - regulator-name = "12V_SW"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - /* USBO1_EN */ - reg_usbo1_vbus: regulator-usbo1-vbus { - compatible = "regulator-fixed"; - regulator-name = "VCC_USBO1"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <®_5v0>; - }; - - /* USBH_EN */ - reg_usbh_vbus: regulator-usbh-vbus { - compatible = "regulator-fixed"; - regulator-name = "VCC_USBH(2A|2C|2D|3|4)"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <®_5v0>; - }; -}; - -&gpio { - /* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */ - pex-perst-n { - gpio-hog; - gpios = ; - output-high; - line-name = "PEX_PERST_N"; - }; -}; diff --git a/sys/gnu/dts/arm/tegra124-apalis-v1.2-eval.dts b/sys/gnu/dts/arm/tegra124-apalis-v1.2-eval.dts deleted file mode 100644 index 826b776fbe6..00000000000 --- a/sys/gnu/dts/arm/tegra124-apalis-v1.2-eval.dts +++ /dev/null @@ -1,257 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT -/* - * Copyright 2016-2018 Toradex AG - */ - -/dts-v1/; - -#include -#include "tegra124-apalis-v1.2.dtsi" - -/ { - model = "Toradex Apalis TK1 on Apalis Evaluation Board"; - compatible = "toradex,apalis-tk1-v1.2-eval", "toradex,apalis-tk1-eval", - "toradex,apalis-tk1-v1.2", "toradex,apalis-tk1", - "nvidia,tegra124"; - - aliases { - rtc0 = "/i2c@7000c000/rtc@68"; - rtc1 = "/i2c@7000d000/pmic@40"; - rtc2 = "/rtc@7000e000"; - serial0 = &uarta; - serial1 = &uartb; - serial2 = &uartc; - serial3 = &uartd; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - pcie@1003000 { - pci@1,0 { - status = "okay"; - }; - }; - - host1x@50000000 { - hdmi@54280000 { - status = "okay"; - hdmi-supply = <®_5v0>; - }; - }; - - /* Apalis UART1 */ - serial@70006000 { - status = "okay"; - }; - - /* Apalis UART2 */ - serial@70006040 { - status = "okay"; - }; - - /* Apalis UART3 */ - serial@70006200 { - status = "okay"; - }; - - /* Apalis UART4 */ - serial@70006300 { - status = "okay"; - }; - - pwm@7000a000 { - status = "okay"; - }; - - /* - * GEN1_I2C: I2C1_SDA/SCL on MXM3 pin 209/211 (e.g. RTC on carrier - * board) - */ - i2c@7000c000 { - status = "okay"; - clock-frequency = <400000>; - - pcie-switch@58 { - compatible = "plx,pex8605"; - reg = <0x58>; - }; - - /* M41T0M6 real time clock on carrier board */ - rtc@68 { - compatible = "st,m41t0"; - reg = <0x68>; - }; - }; - - /* GEN2_I2C: unused */ - - /* - * CAM_I2C: I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor - * on carrier board) - */ - i2c@7000c500 { - status = "okay"; - clock-frequency = <400000>; - }; - - /* - * I2C4 (DDC): I2C4_SDA/SCL (DDC) on MXM3 pin 205/207 - * (e.g. display EDID) - */ - i2c@7000c700 { - status = "okay"; - }; - - /* SPI1: Apalis SPI1 */ - spi@7000d400 { - status = "okay"; - spi-max-frequency = <50000000>; - }; - - /* SPI4: Apalis SPI2 */ - spi@7000da00 { - status = "okay"; - spi-max-frequency = <50000000>; - }; - - /* Apalis Serial ATA */ - sata@70020000 { - status = "okay"; - target-5v-supply = <®_5v0>; - target-12v-supply = <®_12v0>; - }; - - hda@70030000 { - status = "okay"; - }; - - usb@70090000 { - status = "okay"; - }; - - /* Apalis MMC1 */ - sdhci@700b0000 { - status = "okay"; - bus-width = <4>; - /* MMC1_CD# */ - cd-gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>; - vqmmc-supply = <&vddio_sdmmc1>; - }; - - /* Apalis SD1 */ - sdhci@700b0400 { - status = "okay"; - bus-width = <4>; - /* SD1_CD# */ - cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; - vqmmc-supply = <&vddio_sdmmc3>; - }; - - /* EHCI instance 0: USB1_DP/N -> USBO1_DP/N */ - usb@7d000000 { - status = "okay"; - dr_mode = "otg"; - }; - - usb-phy@7d000000 { - status = "okay"; - vbus-supply = <®_usbo1_vbus>; - }; - - /* EHCI instance 1: USB2_DP/N -> USBH2_DP/N */ - usb@7d004000 { - status = "okay"; - }; - - usb-phy@7d004000 { - status = "okay"; - vbus-supply = <®_usbh_vbus>; - }; - - /* EHCI instance 2: USB3_DP/N -> USBH4_DP/N */ - usb@7d008000 { - status = "okay"; - }; - - usb-phy@7d008000 { - status = "okay"; - vbus-supply = <®_usbh_vbus>; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - brightness-levels = <255 231 223 207 191 159 127 0>; - default-brightness-level = <6>; - /* BKL1_ON */ - enable-gpios = <&gpio TEGRA_GPIO(BB, 5) GPIO_ACTIVE_HIGH>; - power-supply = <®_3v3>; - pwms = <&pwm 3 5000000>; /* BKL1_PWM */ - }; - - gpio-keys { - compatible = "gpio-keys"; - - wakeup { - label = "WAKE1_MICO"; - gpios = <&gpio TEGRA_GPIO(DD, 3) GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <10>; - wakeup-source; - }; - }; - - reg_3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "3.3V_SW"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_5v0: regulator-5v0 { - compatible = "regulator-fixed"; - regulator-name = "5V_SW"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_12v0: regulator-12v0 { - compatible = "regulator-fixed"; - regulator-name = "12V_SW"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - /* USBO1_EN */ - reg_usbo1_vbus: regulator-usbo1-vbus { - compatible = "regulator-fixed"; - regulator-name = "VCC_USBO1"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(T, 5) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <®_5v0>; - }; - - /* USBH_EN */ - reg_usbh_vbus: regulator-usbh-vbus { - compatible = "regulator-fixed"; - regulator-name = "VCC_USBH(2A|2C|2D|3|4)"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(T, 6) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <®_5v0>; - }; -}; - -&gpio { - /* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */ - pex-perst-n { - gpio-hog; - gpios = ; - output-high; - line-name = "PEX_PERST_N"; - }; -}; diff --git a/sys/gnu/dts/arm/tegra124-apalis-v1.2.dtsi b/sys/gnu/dts/arm/tegra124-apalis-v1.2.dtsi deleted file mode 100644 index 0462ed2dd8b..00000000000 --- a/sys/gnu/dts/arm/tegra124-apalis-v1.2.dtsi +++ /dev/null @@ -1,2065 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT -/* - * Copyright 2016-2018 Toradex AG - */ - -#include "tegra124.dtsi" -#include "tegra124-apalis-emc.dtsi" - -/* - * Toradex Apalis TK1 Module Device Tree - * Compatible for Revisions 2GB: V1.2A - */ -/ { - memory@80000000 { - reg = <0x0 0x80000000 0x0 0x80000000>; - }; - - pcie@1003000 { - status = "okay"; - - avddio-pex-supply = <®_1v05_vdd>; - avdd-pex-pll-supply = <®_1v05_vdd>; - avdd-pll-erefe-supply = <®_1v05_avdd>; - dvddio-pex-supply = <®_1v05_vdd>; - hvdd-pex-pll-e-supply = <®_module_3v3>; - hvdd-pex-supply = <®_module_3v3>; - vddio-pex-ctl-supply = <®_module_3v3>; - - /* Apalis PCIe (additional lane Apalis type specific) */ - pci@1,0 { - /* PCIE1_RX/TX and TS_DIFF1/2 */ - phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>, - <&{/padctl@7009f000/pads/pcie/lanes/pcie-3}>; - phy-names = "pcie-0", "pcie-1"; - }; - - /* I210 Gigabit Ethernet Controller (On-module) */ - pci@2,0 { - phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>; - phy-names = "pcie-0"; - status = "okay"; - - pcie@0 { - reg = <0 0 0 0 0>; - local-mac-address = [00 00 00 00 00 00]; - }; - }; - }; - - host1x@50000000 { - hdmi@54280000 { - nvidia,ddc-i2c-bus = <&hdmi_ddc>; - nvidia,hpd-gpio = - <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; - pll-supply = <®_1v05_avdd_hdmi_pll>; - vdd-supply = <®_3v3_avdd_hdmi>; - }; - }; - - gpu@0,57000000 { - /* - * Node left disabled on purpose - the bootloader will enable - * it after having set the VPR up - */ - vdd-supply = <®_vdd_gpu>; - }; - - pinmux@70000868 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - /* Analogue Audio (On-module) */ - dap3-fs-pp0 { - nvidia,pins = "dap3_fs_pp0"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3-din-pp1 { - nvidia,pins = "dap3_din_pp1"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3-dout-pp2 { - nvidia,pins = "dap3_dout_pp2"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3-sclk-pp3 { - nvidia,pins = "dap3_sclk_pp3"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap-mclk1-pw4 { - nvidia,pins = "dap_mclk1_pw4"; - nvidia,function = "extperiph1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis BKL1_ON */ - pbb5 { - nvidia,pins = "pbb5"; - nvidia,function = "vgp5"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis BKL1_PWM */ - pu6 { - nvidia,pins = "pu6"; - nvidia,function = "pwm3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis CAM1_MCLK */ - cam-mclk-pcc0 { - nvidia,pins = "cam_mclk_pcc0"; - nvidia,function = "vi_alt3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis Digital Audio */ - dap2-fs-pa2 { - nvidia,pins = "dap2_fs_pa2"; - nvidia,function = "hda"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap2-sclk-pa3 { - nvidia,pins = "dap2_sclk_pa3"; - nvidia,function = "hda"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap2-din-pa4 { - nvidia,pins = "dap2_din_pa4"; - nvidia,function = "hda"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap2-dout-pa5 { - nvidia,pins = "dap2_dout_pa5"; - nvidia,function = "hda"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pbb3 { /* DAP1_RESET */ - nvidia,pins = "pbb3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk3-out-pee0 { - nvidia,pins = "clk3_out_pee0"; - nvidia,function = "extperiph3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis GPIO */ - usb-vbus-en0-pn4 { - nvidia,pins = "usb_vbus_en0_pn4"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - usb-vbus-en1-pn5 { - nvidia,pins = "usb_vbus_en1_pn5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pex-l0-rst-n-pdd1 { - nvidia,pins = "pex_l0_rst_n_pdd1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex-l0-clkreq-n-pdd2 { - nvidia,pins = "pex_l0_clkreq_n_pdd2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex-l1-rst-n-pdd5 { - nvidia,pins = "pex_l1_rst_n_pdd5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex-l1-clkreq-n-pdd6 { - nvidia,pins = "pex_l1_clkreq_n_pdd6"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dp-hpd-pff0 { - nvidia,pins = "dp_hpd_pff0"; - nvidia,function = "dp"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pff2 { - nvidia,pins = "pff2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - owr { /* PEX_L1_CLKREQ_N multiplexed GPIO6 */ - nvidia,pins = "owr"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,rcv-sel = ; - }; - - /* Apalis HDMI1_CEC */ - hdmi-cec-pee3 { - nvidia,pins = "hdmi_cec_pee3"; - nvidia,function = "cec"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - - /* Apalis HDMI1_HPD */ - hdmi-int-pn7 { - nvidia,pins = "hdmi_int_pn7"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,rcv-sel = ; - }; - - /* Apalis I2C1 */ - gen1-i2c-scl-pc4 { - nvidia,pins = "gen1_i2c_scl_pc4"; - nvidia,function = "i2c1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gen1-i2c-sda-pc5 { - nvidia,pins = "gen1_i2c_sda_pc5"; - nvidia,function = "i2c1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - - /* Apalis I2C3 (CAM) */ - cam-i2c-scl-pbb1 { - nvidia,pins = "cam_i2c_scl_pbb1"; - nvidia,function = "i2c3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam-i2c-sda-pbb2 { - nvidia,pins = "cam_i2c_sda_pbb2"; - nvidia,function = "i2c3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - - /* Apalis I2C4 (DDC) */ - ddc-scl-pv4 { - nvidia,pins = "ddc_scl_pv4"; - nvidia,function = "i2c4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,rcv-sel = ; - }; - ddc-sda-pv5 { - nvidia,pins = "ddc_sda_pv5"; - nvidia,function = "i2c4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,rcv-sel = ; - }; - - /* Apalis MMC1 */ - sdmmc1-cd-n-pv3 { /* CD# GPIO */ - nvidia,pins = "sdmmc1_wp_n_pv3"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk2-out-pw5 { /* D5 GPIO */ - nvidia,pins = "clk2_out_pw5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1-dat3-py4 { - nvidia,pins = "sdmmc1_dat3_py4"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1-dat2-py5 { - nvidia,pins = "sdmmc1_dat2_py5"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1-dat1-py6 { - nvidia,pins = "sdmmc1_dat1_py6"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1-dat0-py7 { - nvidia,pins = "sdmmc1_dat0_py7"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1-clk-pz0 { - nvidia,pins = "sdmmc1_clk_pz0"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1-cmd-pz1 { - nvidia,pins = "sdmmc1_cmd_pz1"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk2-req-pcc5 { /* D4 GPIO */ - nvidia,pins = "clk2_req_pcc5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3-clk-lb-in-pee5 { /* D6 GPIO */ - nvidia,pins = "sdmmc3_clk_lb_in_pee5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - usb-vbus-en2-pff1 { /* D7 GPIO */ - nvidia,pins = "usb_vbus_en2_pff1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis PWM */ - ph0 { - nvidia,pins = "ph0"; - nvidia,function = "pwm0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph1 { - nvidia,pins = "ph1"; - nvidia,function = "pwm1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph2 { - nvidia,pins = "ph2"; - nvidia,function = "pwm2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - /* PWM3 active on pu6 being Apalis BKL1_PWM as well */ - ph3 { - nvidia,pins = "ph3"; - nvidia,function = "pwm3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis SATA1_ACT# */ - dap1-dout-pn2 { - nvidia,pins = "dap1_dout_pn2"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis SD1 */ - sdmmc3-clk-pa6 { - nvidia,pins = "sdmmc3_clk_pa6"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3-cmd-pa7 { - nvidia,pins = "sdmmc3_cmd_pa7"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3-dat3-pb4 { - nvidia,pins = "sdmmc3_dat3_pb4"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3-dat2-pb5 { - nvidia,pins = "sdmmc3_dat2_pb5"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3-dat1-pb6 { - nvidia,pins = "sdmmc3_dat1_pb6"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3-dat0-pb7 { - nvidia,pins = "sdmmc3_dat0_pb7"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3-cd-n-pv2 { /* CD# GPIO */ - nvidia,pins = "sdmmc3_cd_n_pv2"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis SPDIF */ - spdif-out-pk5 { - nvidia,pins = "spdif_out_pk5"; - nvidia,function = "spdif"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - spdif-in-pk6 { - nvidia,pins = "spdif_in_pk6"; - nvidia,function = "spdif"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis SPI1 */ - ulpi-clk-py0 { - nvidia,pins = "ulpi_clk_py0"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi-dir-py1 { - nvidia,pins = "ulpi_dir_py1"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi-nxt-py2 { - nvidia,pins = "ulpi_nxt_py2"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi-stp-py3 { - nvidia,pins = "ulpi_stp_py3"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis SPI2 */ - pg5 { - nvidia,pins = "pg5"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg6 { - nvidia,pins = "pg6"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg7 { - nvidia,pins = "pg7"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi3 { - nvidia,pins = "pi3"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis UART1 */ - pb1 { /* DCD GPIO */ - nvidia,pins = "pb1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pk7 { /* RI GPIO */ - nvidia,pins = "pk7"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart1-txd-pu0 { - nvidia,pins = "pu0"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart1-rxd-pu1 { - nvidia,pins = "pu1"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart1-cts-n-pu2 { - nvidia,pins = "pu2"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart1-rts-n-pu3 { - nvidia,pins = "pu3"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart3-cts-n-pa1 { /* DSR GPIO */ - nvidia,pins = "uart3_cts_n_pa1"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart3-rts-n-pc0 { /* DTR GPIO */ - nvidia,pins = "uart3_rts_n_pc0"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis UART2 */ - uart2-txd-pc2 { - nvidia,pins = "uart2_txd_pc2"; - nvidia,function = "irda"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2-rxd-pc3 { - nvidia,pins = "uart2_rxd_pc3"; - nvidia,function = "irda"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2-cts-n-pj5 { - nvidia,pins = "uart2_cts_n_pj5"; - nvidia,function = "uartb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2-rts-n-pj6 { - nvidia,pins = "uart2_rts_n_pj6"; - nvidia,function = "uartb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis UART3 */ - uart3-txd-pw6 { - nvidia,pins = "uart3_txd_pw6"; - nvidia,function = "uartc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart3-rxd-pw7 { - nvidia,pins = "uart3_rxd_pw7"; - nvidia,function = "uartc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis UART4 */ - uart4-rxd-pb0 { - nvidia,pins = "pb0"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart4-txd-pj7 { - nvidia,pins = "pj7"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis USBH_EN */ - gen2-i2c-sda-pt6 { - nvidia,pins = "gen2_i2c_sda_pt6"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - - /* Apalis USBH_OC# */ - pbb0 { - nvidia,pins = "pbb0"; - nvidia,function = "vgp6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis USBO1_EN */ - gen2-i2c-scl-pt5 { - nvidia,pins = "gen2_i2c_scl_pt5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - - /* Apalis USBO1_OC# */ - pbb4 { - nvidia,pins = "pbb4"; - nvidia,function = "vgp4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis WAKE1_MICO */ - pex-wake-n-pdd3 { - nvidia,pins = "pex_wake_n_pdd3"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* CORE_PWR_REQ */ - core-pwr-req { - nvidia,pins = "core_pwr_req"; - nvidia,function = "pwron"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* CPU_PWR_REQ */ - cpu-pwr-req { - nvidia,pins = "cpu_pwr_req"; - nvidia,function = "cpu"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* DVFS */ - dvfs-pwm-px0 { - nvidia,pins = "dvfs_pwm_px0"; - nvidia,function = "cldvfs"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dvfs-clk-px2 { - nvidia,pins = "dvfs_clk_px2"; - nvidia,function = "cldvfs"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* eMMC */ - sdmmc4-dat0-paa0 { - nvidia,pins = "sdmmc4_dat0_paa0"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4-dat1-paa1 { - nvidia,pins = "sdmmc4_dat1_paa1"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4-dat2-paa2 { - nvidia,pins = "sdmmc4_dat2_paa2"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4-dat3-paa3 { - nvidia,pins = "sdmmc4_dat3_paa3"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4-dat4-paa4 { - nvidia,pins = "sdmmc4_dat4_paa4"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4-dat5-paa5 { - nvidia,pins = "sdmmc4_dat5_paa5"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4-dat6-paa6 { - nvidia,pins = "sdmmc4_dat6_paa6"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4-dat7-paa7 { - nvidia,pins = "sdmmc4_dat7_paa7"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4-clk-pcc4 { - nvidia,pins = "sdmmc4_clk_pcc4"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4-cmd-pt7 { - nvidia,pins = "sdmmc4_cmd_pt7"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* JTAG_RTCK */ - jtag-rtck { - nvidia,pins = "jtag_rtck"; - nvidia,function = "rtck"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* LAN_DEV_OFF# */ - ulpi-data5-po6 { - nvidia,pins = "ulpi_data5_po6"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* LAN_RESET# */ - kb-row10-ps2 { - nvidia,pins = "kb_row10_ps2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* LAN_WAKE# */ - ulpi-data4-po5 { - nvidia,pins = "ulpi_data4_po5"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* MCU_INT1# */ - pk2 { - nvidia,pins = "pk2"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* MCU_INT2# */ - pj2 { - nvidia,pins = "pj2"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* MCU_INT3# */ - pi5 { - nvidia,pins = "pi5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* MCU_INT4# */ - pj0 { - nvidia,pins = "pj0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* MCU_RESET */ - pbb6 { - nvidia,pins = "pbb6"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* MCU SPI */ - gpio-x4-aud-px4 { - nvidia,pins = "gpio_x4_aud_px4"; - nvidia,function = "spi2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio-x5-aud-px5 { - nvidia,pins = "gpio_x5_aud_px5"; - nvidia,function = "spi2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio-x6-aud-px6 { /* MCU_CS */ - nvidia,pins = "gpio_x6_aud_px6"; - nvidia,function = "spi2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio-x7-aud-px7 { - nvidia,pins = "gpio_x7_aud_px7"; - nvidia,function = "spi2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio-w2-aud-pw2 { /* MCU_CSEZP */ - nvidia,pins = "gpio_w2_aud_pw2"; - nvidia,function = "spi2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* PMIC_CLK_32K */ - clk-32k-in { - nvidia,pins = "clk_32k_in"; - nvidia,function = "clk"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* PMIC_CPU_OC_INT */ - clk-32k-out-pa0 { - nvidia,pins = "clk_32k_out_pa0"; - nvidia,function = "soc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* PWR_I2C */ - pwr-i2c-scl-pz6 { - nvidia,pins = "pwr_i2c_scl_pz6"; - nvidia,function = "i2cpwr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pwr-i2c-sda-pz7 { - nvidia,pins = "pwr_i2c_sda_pz7"; - nvidia,function = "i2cpwr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - - /* PWR_INT_N */ - pwr-int-n { - nvidia,pins = "pwr_int_n"; - nvidia,function = "pmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* RESET_MOCI_CTRL */ - pu4 { - nvidia,pins = "pu4"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* RESET_OUT_N */ - reset-out-n { - nvidia,pins = "reset_out_n"; - nvidia,function = "reset_out_n"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* SHIFT_CTRL_DIR_IN */ - kb-row0-pr0 { - nvidia,pins = "kb_row0_pr0"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-row1-pr1 { - nvidia,pins = "kb_row1_pr1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Configure level-shifter as output for HDA */ - kb-row11-ps3 { - nvidia,pins = "kb_row11_ps3"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* SHIFT_CTRL_DIR_OUT */ - kb-col5-pq5 { - nvidia,pins = "kb_col5_pq5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-col6-pq6 { - nvidia,pins = "kb_col6_pq6"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-col7-pq7 { - nvidia,pins = "kb_col7_pq7"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* SHIFT_CTRL_OE */ - kb-col0-pq0 { - nvidia,pins = "kb_col0_pq0"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-col1-pq1 { - nvidia,pins = "kb_col1_pq1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-col2-pq2 { - nvidia,pins = "kb_col2_pq2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-col4-pq4 { - nvidia,pins = "kb_col4_pq4"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-row2-pr2 { - nvidia,pins = "kb_row2_pr2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* GPIO_PI6 aka TMP451 ALERT#/THERM2# */ - pi6 { - nvidia,pins = "pi6"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* TOUCH_INT */ - gpio-w3-aud-pw3 { - nvidia,pins = "gpio_w3_aud_pw3"; - nvidia,function = "spi6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - pc7 { /* NC */ - nvidia,pins = "pc7"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg0 { /* NC */ - nvidia,pins = "pg0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg1 { /* NC */ - nvidia,pins = "pg1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg2 { /* NC */ - nvidia,pins = "pg2"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg3 { /* NC */ - nvidia,pins = "pg3"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg4 { /* NC */ - nvidia,pins = "pg4"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph4 { /* NC */ - nvidia,pins = "ph4"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph5 { /* NC */ - nvidia,pins = "ph5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph6 { /* NC */ - nvidia,pins = "ph6"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph7 { /* NC */ - nvidia,pins = "ph7"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi0 { /* NC */ - nvidia,pins = "pi0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi1 { /* NC */ - nvidia,pins = "pi1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi2 { /* NC */ - nvidia,pins = "pi2"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi4 { /* NC */ - nvidia,pins = "pi4"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi7 { /* NC */ - nvidia,pins = "pi7"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pk0 { /* NC */ - nvidia,pins = "pk0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pk1 { /* NC */ - nvidia,pins = "pk1"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pk3 { /* NC */ - nvidia,pins = "pk3"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pk4 { /* NC */ - nvidia,pins = "pk4"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap1-fs-pn0 { /* NC */ - nvidia,pins = "dap1_fs_pn0"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap1-din-pn1 { /* NC */ - nvidia,pins = "dap1_din_pn1"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap1-sclk-pn3 { /* NC */ - nvidia,pins = "dap1_sclk_pn3"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi-data7-po0 { /* NC */ - nvidia,pins = "ulpi_data7_po0"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi-data0-po1 { /* NC */ - nvidia,pins = "ulpi_data0_po1"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi-data1-po2 { /* NC */ - nvidia,pins = "ulpi_data1_po2"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi-data2-po3 { /* NC */ - nvidia,pins = "ulpi_data2_po3"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi-data3-po4 { /* NC */ - nvidia,pins = "ulpi_data3_po4"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi-data6-po7 { /* NC */ - nvidia,pins = "ulpi_data6_po7"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap4-fs-pp4 { /* NC */ - nvidia,pins = "dap4_fs_pp4"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap4-din-pp5 { /* NC */ - nvidia,pins = "dap4_din_pp5"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap4-dout-pp6 { /* NC */ - nvidia,pins = "dap4_dout_pp6"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap4-sclk-pp7 { /* NC */ - nvidia,pins = "dap4_sclk_pp7"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-col3-pq3 { /* NC */ - nvidia,pins = "kb_col3_pq3"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-row3-pr3 { /* NC */ - nvidia,pins = "kb_row3_pr3"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-row4-pr4 { /* NC */ - nvidia,pins = "kb_row4_pr4"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-row5-pr5 { /* NC */ - nvidia,pins = "kb_row5_pr5"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-row6-pr6 { /* NC */ - nvidia,pins = "kb_row6_pr6"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-row7-pr7 { /* NC */ - nvidia,pins = "kb_row7_pr7"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-row8-ps0 { /* NC */ - nvidia,pins = "kb_row8_ps0"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-row9-ps1 { /* NC */ - nvidia,pins = "kb_row9_ps1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-row12-ps4 { /* NC */ - nvidia,pins = "kb_row12_ps4"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-row13-ps5 { /* NC */ - nvidia,pins = "kb_row13_ps5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-row14-ps6 { /* NC */ - nvidia,pins = "kb_row14_ps6"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-row15-ps7 { /* NC */ - nvidia,pins = "kb_row15_ps7"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-row16-pt0 { /* NC */ - nvidia,pins = "kb_row16_pt0"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-row17-pt1 { /* NC */ - nvidia,pins = "kb_row17_pt1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu5 { /* NC */ - nvidia,pins = "pu5"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - /* - * PCB Version Indication: V1.2 and later have GPIO_PV0 - * wired to GND, was NC before - */ - pv0 { - nvidia,pins = "pv0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pv1 { /* NC */ - nvidia,pins = "pv1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio-x1-aud-px1 { /* NC */ - nvidia,pins = "gpio_x1_aud_px1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio-x3-aud-px3 { /* NC */ - nvidia,pins = "gpio_x3_aud_px3"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pbb7 { /* NC */ - nvidia,pins = "pbb7"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pcc1 { /* NC */ - nvidia,pins = "pcc1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pcc2 { /* NC */ - nvidia,pins = "pcc2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk3-req-pee1 { /* NC */ - nvidia,pins = "clk3_req_pee1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap-mclk1-req-pee2 { /* NC */ - nvidia,pins = "dap_mclk1_req_pee2"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - /* - * Leave SDMMC3_CLK_LB_OUT muxed as SDMMC3 with output - * driver enabled aka not tristated and input driver - * enabled as well as it features some magic properties - * even though the external loopback is disabled and the - * internal loopback used as per - * SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1 - * bits being set to 0xfffd according to the TRM! - */ - sdmmc3-clk-lb-out-pee4 { /* NC */ - nvidia,pins = "sdmmc3_clk_lb_out_pee4"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - }; - }; - - serial@70006040 { - compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; - }; - - serial@70006200 { - compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; - }; - - serial@70006300 { - compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; - }; - - hdmi_ddc: i2c@7000c700 { - clock-frequency = <10000>; - }; - - /* PWR_I2C: power I2C to audio codec, PMIC and temperature sensor */ - i2c@7000d000 { - status = "okay"; - clock-frequency = <400000>; - - /* SGTL5000 audio codec */ - sgtl5000: codec@a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - VDDA-supply = <®_module_3v3_audio>; - VDDD-supply = <®_1v8_vddio>; - VDDIO-supply = <®_1v8_vddio>; - clocks = <&tegra_car TEGRA124_CLK_EXTERN1>; - }; - - pmic: pmic@40 { - compatible = "ams,as3722"; - reg = <0x40>; - interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; - ams,system-power-controller; - #interrupt-cells = <2>; - interrupt-controller; - gpio-controller; - #gpio-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&as3722_default>; - - as3722_default: pinmux { - gpio2-7 { - pins = "gpio2", /* PWR_EN_+V3.3 */ - "gpio7"; /* +V1.6_LPO */ - function = "gpio"; - bias-pull-up; - }; - - gpio0-1-3-4-5-6 { - pins = "gpio0", "gpio1", "gpio3", - "gpio4", "gpio5", "gpio6"; - bias-high-impedance; - }; - }; - - regulators { - vsup-sd2-supply = <®_module_3v3>; - vsup-sd3-supply = <®_module_3v3>; - vsup-sd4-supply = <®_module_3v3>; - vsup-sd5-supply = <®_module_3v3>; - vin-ldo0-supply = <®_1v35_vddio_ddr>; - vin-ldo1-6-supply = <®_module_3v3>; - vin-ldo2-5-7-supply = <®_1v8_vddio>; - vin-ldo3-4-supply = <®_module_3v3>; - vin-ldo9-10-supply = <®_module_3v3>; - vin-ldo11-supply = <®_module_3v3>; - - reg_vdd_cpu: sd0 { - regulator-name = "+VDD_CPU_AP"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1400000>; - regulator-min-microamp = <3500000>; - regulator-max-microamp = <3500000>; - regulator-always-on; - regulator-boot-on; - ams,ext-control = <2>; - }; - - sd1 { - regulator-name = "+VDD_CORE"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1350000>; - regulator-min-microamp = <2500000>; - regulator-max-microamp = <4000000>; - regulator-always-on; - regulator-boot-on; - ams,ext-control = <1>; - }; - - reg_1v35_vddio_ddr: sd2 { - regulator-name = - "+V1.35_VDDIO_DDR(sd2)"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - - sd3 { - regulator-name = - "+V1.35_VDDIO_DDR(sd3)"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - - reg_1v05_vdd: sd4 { - regulator-name = "+V1.05"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - }; - - reg_1v8_vddio: sd5 { - regulator-name = "+V1.8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_vdd_gpu: sd6 { - regulator-name = "+VDD_GPU_AP"; - regulator-min-microvolt = <650000>; - regulator-max-microvolt = <1200000>; - regulator-min-microamp = <3500000>; - regulator-max-microamp = <3500000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_1v05_avdd: ldo0 { - regulator-name = "+V1.05_AVDD"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - regulator-boot-on; - regulator-always-on; - ams,ext-control = <1>; - }; - - vddio_sdmmc1: ldo1 { - regulator-name = "VDDIO_SDMMC1"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - ldo2 { - regulator-name = "+V1.2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo3 { - regulator-name = "+V1.05_RTC"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-boot-on; - regulator-always-on; - ams,enable-tracking; - }; - - /* 1.8V for LVDS, 3.3V for eDP */ - ldo4 { - regulator-name = "AVDD_LVDS0_PLL"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - /* LDO5 not used */ - - vddio_sdmmc3: ldo6 { - regulator-name = "VDDIO_SDMMC3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - /* LDO7 not used */ - - ldo9 { - regulator-name = "+V3.3_ETH(ldo9)"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo10 { - regulator-name = "+V3.3_ETH(ldo10)"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo11 { - regulator-name = "+V1.8_VPP_FUSE"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - }; - }; - - /* - * TMP451 temperature sensor - * Note: THERM_N directly connected to AS3722 PMIC THERM - */ - temp-sensor@4c { - compatible = "ti,tmp451"; - reg = <0x4c>; - interrupt-parent = <&gpio>; - interrupts = ; - #thermal-sensor-cells = <1>; - vcc-supply = <®_module_3v3>; - }; - }; - - /* SPI2: MCU SPI */ - spi@7000d600 { - status = "okay"; - spi-max-frequency = <25000000>; - }; - - pmc@7000e400 { - nvidia,invert-interrupt; - nvidia,suspend-mode = <1>; - nvidia,cpu-pwr-good-time = <500>; - nvidia,cpu-pwr-off-time = <300>; - nvidia,core-pwr-good-time = <641 3845>; - nvidia,core-pwr-off-time = <61036>; - nvidia,core-power-req-active-high; - nvidia,sys-clock-req-active-high; - - /* Set power_off bit in ResetControl register of AS3722 PMIC */ - i2c-thermtrip { - nvidia,i2c-controller-id = <4>; - nvidia,bus-addr = <0x40>; - nvidia,reg-addr = <0x36>; - nvidia,reg-data = <0x2>; - }; - }; - - sata@70020000 { - phys = <&{/padctl@7009f000/pads/sata/lanes/sata-0}>; - phy-names = "sata-0"; - avdd-supply = <®_1v05_vdd>; - hvdd-supply = <®_module_3v3>; - vddio-supply = <®_1v05_vdd>; - }; - - usb@70090000 { - /* USBO1, USBO1 (SS), USBH2, USBH4 and USBH4 (SS) */ - phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>, - <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>, - <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>, - <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>, - <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>; - phy-names = "usb2-0", "usb3-1", "usb2-1", "usb2-2", "usb3-0"; - - avddio-pex-supply = <®_1v05_vdd>; - avdd-pll-erefe-supply = <®_1v05_avdd>; - avdd-pll-utmip-supply = <®_1v8_vddio>; - avdd-usb-ss-pll-supply = <®_1v05_vdd>; - avdd-usb-supply = <®_module_3v3>; - dvddio-pex-supply = <®_1v05_vdd>; - hvdd-usb-ss-pll-e-supply = <®_module_3v3>; - hvdd-usb-ss-supply = <®_module_3v3>; - }; - - padctl@7009f000 { - avdd-pll-utmip-supply = <®_1v8_vddio>; - avdd-pll-erefe-supply = <®_1v05_avdd>; - avdd-pex-pll-supply = <®_1v05_vdd>; - hvdd-pex-pll-e-supply = <®_module_3v3>; - - pads { - usb2 { - status = "okay"; - - lanes { - usb2-0 { - status = "okay"; - nvidia,function = "xusb"; - }; - - usb2-1 { - status = "okay"; - nvidia,function = "xusb"; - }; - - usb2-2 { - status = "okay"; - nvidia,function = "xusb"; - }; - }; - }; - - pcie { - status = "okay"; - - lanes { - pcie-0 { - status = "okay"; - nvidia,function = "usb3-ss"; - }; - - pcie-1 { - status = "okay"; - nvidia,function = "usb3-ss"; - }; - - pcie-2 { - status = "okay"; - nvidia,function = "pcie"; - }; - - pcie-3 { - status = "okay"; - nvidia,function = "pcie"; - }; - - pcie-4 { - status = "okay"; - nvidia,function = "pcie"; - }; - }; - }; - - sata { - status = "okay"; - - lanes { - sata-0 { - status = "okay"; - nvidia,function = "sata"; - }; - }; - }; - }; - - ports { - /* USBO1 */ - usb2-0 { - status = "okay"; - mode = "otg"; - vbus-supply = <®_usbo1_vbus>; - }; - - /* USBH2 */ - usb2-1 { - status = "okay"; - mode = "host"; - vbus-supply = <®_usbh_vbus>; - }; - - /* USBH4 */ - usb2-2 { - status = "okay"; - mode = "host"; - vbus-supply = <®_usbh_vbus>; - }; - - usb3-0 { - status = "okay"; - nvidia,usb2-companion = <2>; - vbus-supply = <®_usbh_vbus>; - }; - - usb3-1 { - status = "okay"; - nvidia,usb2-companion = <0>; - vbus-supply = <®_usbo1_vbus>; - }; - }; - }; - - /* eMMC */ - sdhci@700b0600 { - status = "okay"; - bus-width = <8>; - non-removable; - vmmc-supply = <®_module_3v3>; /* VCC */ - vqmmc-supply = <®_1v8_vddio>; /* VCCQ */ - mmc-ddr-1_8v; - }; - - /* CPU DFLL clock */ - clock@70110000 { - status = "okay"; - nvidia,i2c-fs-rate = <400000>; - vdd-cpu-supply = <®_vdd_cpu>; - }; - - ahub@70300000 { - i2s@70301200 { - status = "okay"; - }; - }; - - clk32k_in: osc3 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - - cpus { - cpu@0 { - vdd-cpu-supply = <®_vdd_cpu>; - }; - }; - - reg_1v05_avdd_hdmi_pll: regulator-1v05-avdd-hdmi-pll { - compatible = "regulator-fixed"; - regulator-name = "+V1.05_AVDD_HDMI_PLL"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>; - vin-supply = <®_1v05_vdd>; - }; - - reg_3v3_mxm: regulator-3v3-mxm { - compatible = "regulator-fixed"; - regulator-name = "+V3.3_MXM"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - reg_3v3_avdd_hdmi: regulator-3v3-avdd-hdmi { - compatible = "regulator-fixed"; - regulator-name = "+V3.3_AVDD_HDMI"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <®_1v05_vdd>; - }; - - reg_module_3v3: regulator-module-3v3 { - compatible = "regulator-fixed"; - regulator-name = "+V3.3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - /* PWR_EN_+V3.3 */ - gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <®_3v3_mxm>; - }; - - reg_module_3v3_audio: regulator-module-3v3-audio { - compatible = "regulator-fixed"; - regulator-name = "+V3.3_AUDIO_AVDD_S"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - sound { - compatible = "toradex,tegra-audio-sgtl5000-apalis_tk1", - "nvidia,tegra-audio-sgtl5000"; - nvidia,model = "Toradex Apalis TK1"; - nvidia,audio-routing = - "Headphone Jack", "HP_OUT", - "LINE_IN", "Line In Jack", - "MIC_IN", "Mic Jack"; - nvidia,i2s-controller = <&tegra_i2s2>; - nvidia,audio-codec = <&sgtl5000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_A>, - <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA124_CLK_EXTERN1>; - clock-names = "pll_a", "pll_a_out0", "mclk"; - }; - - thermal-zones { - cpu { - trips { - cpu-shutdown-trip { - temperature = <101000>; - hysteresis = <0>; - type = "critical"; - }; - }; - }; - - mem { - trips { - mem-shutdown-trip { - temperature = <101000>; - hysteresis = <0>; - type = "critical"; - }; - }; - }; - - gpu { - trips { - gpu-shutdown-trip { - temperature = <101000>; - hysteresis = <0>; - type = "critical"; - }; - }; - }; - }; -}; - -&gpio { - /* I210 Gigabit Ethernet Controller Reset */ - lan-reset-n { - gpio-hog; - gpios = ; - output-high; - line-name = "LAN_RESET_N"; - }; - - /* Control MXM3 pin 26 Reset Module Output Carrier Input */ - reset-moci-ctrl { - gpio-hog; - gpios = ; - output-high; - line-name = "RESET_MOCI_CTRL"; - }; -}; diff --git a/sys/gnu/dts/arm/tegra124-apalis.dtsi b/sys/gnu/dts/arm/tegra124-apalis.dtsi deleted file mode 100644 index d1e8593ef0d..00000000000 --- a/sys/gnu/dts/arm/tegra124-apalis.dtsi +++ /dev/null @@ -1,2057 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR X11 -/* - * Copyright 2016-2019 Toradex AG - */ - -#include "tegra124.dtsi" -#include "tegra124-apalis-emc.dtsi" - -/* - * Toradex Apalis TK1 Module Device Tree - * Compatible for Revisions 2GB: V1.0A, V1.0B, V1.1A - */ -/ { - memory@80000000 { - reg = <0x0 0x80000000 0x0 0x80000000>; - }; - - pcie@1003000 { - status = "okay"; - avddio-pex-supply = <®_1v05_vdd>; - avdd-pex-pll-supply = <®_1v05_vdd>; - avdd-pll-erefe-supply = <®_1v05_avdd>; - dvddio-pex-supply = <®_1v05_vdd>; - hvdd-pex-pll-e-supply = <®_module_3v3>; - hvdd-pex-supply = <®_module_3v3>; - vddio-pex-ctl-supply = <®_module_3v3>; - - /* Apalis PCIe (additional lane Apalis type specific) */ - pci@1,0 { - /* PCIE1_RX/TX and TS_DIFF1/2 */ - phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>, - <&{/padctl@7009f000/pads/pcie/lanes/pcie-3}>; - phy-names = "pcie-0", "pcie-1"; - }; - - /* I210 Gigabit Ethernet Controller (On-module) */ - pci@2,0 { - phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>; - phy-names = "pcie-0"; - status = "okay"; - - pcie@0 { - reg = <0 0 0 0 0>; - local-mac-address = [00 00 00 00 00 00]; - }; - }; - }; - - host1x@50000000 { - hdmi@54280000 { - nvidia,ddc-i2c-bus = <&hdmi_ddc>; - nvidia,hpd-gpio = - <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; - pll-supply = <®_1v05_avdd_hdmi_pll>; - vdd-supply = <®_3v3_avdd_hdmi>; - }; - }; - - gpu@0,57000000 { - /* - * Node left disabled on purpose - the bootloader will enable - * it after having set the VPR up - */ - vdd-supply = <®_vdd_gpu>; - }; - - pinmux@70000868 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - /* Analogue Audio (On-module) */ - dap3-fs-pp0 { - nvidia,pins = "dap3_fs_pp0"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3-din-pp1 { - nvidia,pins = "dap3_din_pp1"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3-dout-pp2 { - nvidia,pins = "dap3_dout_pp2"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3-sclk-pp3 { - nvidia,pins = "dap3_sclk_pp3"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap-mclk1-pw4 { - nvidia,pins = "dap_mclk1_pw4"; - nvidia,function = "extperiph1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis BKL1_ON */ - pbb5 { - nvidia,pins = "pbb5"; - nvidia,function = "vgp5"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis BKL1_PWM */ - pu6 { - nvidia,pins = "pu6"; - nvidia,function = "pwm3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis CAM1_MCLK */ - cam-mclk-pcc0 { - nvidia,pins = "cam_mclk_pcc0"; - nvidia,function = "vi_alt3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis Digital Audio */ - dap2-fs-pa2 { - nvidia,pins = "dap2_fs_pa2"; - nvidia,function = "hda"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap2-sclk-pa3 { - nvidia,pins = "dap2_sclk_pa3"; - nvidia,function = "hda"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap2-din-pa4 { - nvidia,pins = "dap2_din_pa4"; - nvidia,function = "hda"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap2-dout-pa5 { - nvidia,pins = "dap2_dout_pa5"; - nvidia,function = "hda"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pbb3 { /* DAP1_RESET */ - nvidia,pins = "pbb3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk3-out-pee0 { - nvidia,pins = "clk3_out_pee0"; - nvidia,function = "extperiph3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis GPIO */ - ddc-scl-pv4 { - nvidia,pins = "ddc_scl_pv4"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ddc-sda-pv5 { - nvidia,pins = "ddc_sda_pv5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex-l0-rst-n-pdd1 { - nvidia,pins = "pex_l0_rst_n_pdd1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex-l0-clkreq-n-pdd2 { - nvidia,pins = "pex_l0_clkreq_n_pdd2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex-l1-rst-n-pdd5 { - nvidia,pins = "pex_l1_rst_n_pdd5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex-l1-clkreq-n-pdd6 { - nvidia,pins = "pex_l1_clkreq_n_pdd6"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dp-hpd-pff0 { - nvidia,pins = "dp_hpd_pff0"; - nvidia,function = "dp"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pff2 { - nvidia,pins = "pff2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - owr { /* PEX_L1_CLKREQ_N multiplexed GPIO6 */ - nvidia,pins = "owr"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,rcv-sel = ; - }; - - /* Apalis HDMI1_CEC */ - hdmi-cec-pee3 { - nvidia,pins = "hdmi_cec_pee3"; - nvidia,function = "cec"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - - /* Apalis HDMI1_HPD */ - hdmi-int-pn7 { - nvidia,pins = "hdmi_int_pn7"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,rcv-sel = ; - }; - - /* Apalis I2C1 */ - gen1-i2c-scl-pc4 { - nvidia,pins = "gen1_i2c_scl_pc4"; - nvidia,function = "i2c1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gen1-i2c-sda-pc5 { - nvidia,pins = "gen1_i2c_sda_pc5"; - nvidia,function = "i2c1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - - /* Apalis I2C2 (DDC) */ - gen2-i2c-scl-pt5 { - nvidia,pins = "gen2_i2c_scl_pt5"; - nvidia,function = "i2c2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gen2-i2c-sda-pt6 { - nvidia,pins = "gen2_i2c_sda_pt6"; - nvidia,function = "i2c2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - - /* Apalis I2C3 (CAM) */ - cam-i2c-scl-pbb1 { - nvidia,pins = "cam_i2c_scl_pbb1"; - nvidia,function = "i2c3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam-i2c-sda-pbb2 { - nvidia,pins = "cam_i2c_sda_pbb2"; - nvidia,function = "i2c3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - - /* Apalis MMC1 */ - sdmmc1-cd-n-pv3 { /* CD# GPIO */ - nvidia,pins = "sdmmc1_wp_n_pv3"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk2-out-pw5 { /* D5 GPIO */ - nvidia,pins = "clk2_out_pw5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1-dat3-py4 { - nvidia,pins = "sdmmc1_dat3_py4"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1-dat2-py5 { - nvidia,pins = "sdmmc1_dat2_py5"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1-dat1-py6 { - nvidia,pins = "sdmmc1_dat1_py6"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1-dat0-py7 { - nvidia,pins = "sdmmc1_dat0_py7"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1-clk-pz0 { - nvidia,pins = "sdmmc1_clk_pz0"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1-cmd-pz1 { - nvidia,pins = "sdmmc1_cmd_pz1"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk2-req-pcc5 { /* D4 GPIO */ - nvidia,pins = "clk2_req_pcc5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3-clk-lb-in-pee5 { /* D6 GPIO */ - nvidia,pins = "sdmmc3_clk_lb_in_pee5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - usb-vbus-en2-pff1 { /* D7 GPIO */ - nvidia,pins = "usb_vbus_en2_pff1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis PWM */ - ph0 { - nvidia,pins = "ph0"; - nvidia,function = "pwm0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph1 { - nvidia,pins = "ph1"; - nvidia,function = "pwm1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph2 { - nvidia,pins = "ph2"; - nvidia,function = "pwm2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - /* PWM3 active on pu6 being Apalis BKL1_PWM as well */ - ph3 { - nvidia,pins = "ph3"; - nvidia,function = "pwm3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis SATA1_ACT# */ - dap1-dout-pn2 { - nvidia,pins = "dap1_dout_pn2"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis SD1 */ - sdmmc3-clk-pa6 { - nvidia,pins = "sdmmc3_clk_pa6"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3-cmd-pa7 { - nvidia,pins = "sdmmc3_cmd_pa7"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3-dat3-pb4 { - nvidia,pins = "sdmmc3_dat3_pb4"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3-dat2-pb5 { - nvidia,pins = "sdmmc3_dat2_pb5"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3-dat1-pb6 { - nvidia,pins = "sdmmc3_dat1_pb6"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3-dat0-pb7 { - nvidia,pins = "sdmmc3_dat0_pb7"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3-cd-n-pv2 { /* CD# GPIO */ - nvidia,pins = "sdmmc3_cd_n_pv2"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis SPDIF */ - spdif-out-pk5 { - nvidia,pins = "spdif_out_pk5"; - nvidia,function = "spdif"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - spdif-in-pk6 { - nvidia,pins = "spdif_in_pk6"; - nvidia,function = "spdif"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis SPI1 */ - ulpi-clk-py0 { - nvidia,pins = "ulpi_clk_py0"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi-dir-py1 { - nvidia,pins = "ulpi_dir_py1"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi-nxt-py2 { - nvidia,pins = "ulpi_nxt_py2"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi-stp-py3 { - nvidia,pins = "ulpi_stp_py3"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis SPI2 */ - pg5 { - nvidia,pins = "pg5"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg6 { - nvidia,pins = "pg6"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg7 { - nvidia,pins = "pg7"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi3 { - nvidia,pins = "pi3"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis UART1 */ - pb1 { /* DCD GPIO */ - nvidia,pins = "pb1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pk7 { /* RI GPIO */ - nvidia,pins = "pk7"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart1-txd-pu0 { - nvidia,pins = "pu0"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart1-rxd-pu1 { - nvidia,pins = "pu1"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart1-cts-n-pu2 { - nvidia,pins = "pu2"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart1-rts-n-pu3 { - nvidia,pins = "pu3"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart3-cts-n-pa1 { /* DSR GPIO */ - nvidia,pins = "uart3_cts_n_pa1"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart3-rts-n-pc0 { /* DTR GPIO */ - nvidia,pins = "uart3_rts_n_pc0"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis UART2 */ - uart2-txd-pc2 { - nvidia,pins = "uart2_txd_pc2"; - nvidia,function = "irda"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2-rxd-pc3 { - nvidia,pins = "uart2_rxd_pc3"; - nvidia,function = "irda"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2-cts-n-pj5 { - nvidia,pins = "uart2_cts_n_pj5"; - nvidia,function = "uartb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2-rts-n-pj6 { - nvidia,pins = "uart2_rts_n_pj6"; - nvidia,function = "uartb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis UART3 */ - uart3-txd-pw6 { - nvidia,pins = "uart3_txd_pw6"; - nvidia,function = "uartc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart3-rxd-pw7 { - nvidia,pins = "uart3_rxd_pw7"; - nvidia,function = "uartc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis UART4 */ - uart4-rxd-pb0 { - nvidia,pins = "pb0"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart4-txd-pj7 { - nvidia,pins = "pj7"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis USBH_EN */ - usb-vbus-en1-pn5 { - nvidia,pins = "usb_vbus_en1_pn5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - - /* Apalis USBH_OC# */ - pbb0 { - nvidia,pins = "pbb0"; - nvidia,function = "vgp6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis USBO1_EN */ - usb-vbus-en0-pn4 { - nvidia,pins = "usb_vbus_en0_pn4"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - - /* Apalis USBO1_OC# */ - pbb4 { - nvidia,pins = "pbb4"; - nvidia,function = "vgp4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis WAKE1_MICO */ - pex-wake-n-pdd3 { - nvidia,pins = "pex_wake_n_pdd3"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* CORE_PWR_REQ */ - core-pwr-req { - nvidia,pins = "core_pwr_req"; - nvidia,function = "pwron"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* CPU_PWR_REQ */ - cpu-pwr-req { - nvidia,pins = "cpu_pwr_req"; - nvidia,function = "cpu"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* DVFS */ - dvfs-pwm-px0 { - nvidia,pins = "dvfs_pwm_px0"; - nvidia,function = "cldvfs"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dvfs-clk-px2 { - nvidia,pins = "dvfs_clk_px2"; - nvidia,function = "cldvfs"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* eMMC */ - sdmmc4-dat0-paa0 { - nvidia,pins = "sdmmc4_dat0_paa0"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4-dat1-paa1 { - nvidia,pins = "sdmmc4_dat1_paa1"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4-dat2-paa2 { - nvidia,pins = "sdmmc4_dat2_paa2"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4-dat3-paa3 { - nvidia,pins = "sdmmc4_dat3_paa3"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4-dat4-paa4 { - nvidia,pins = "sdmmc4_dat4_paa4"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4-dat5-paa5 { - nvidia,pins = "sdmmc4_dat5_paa5"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4-dat6-paa6 { - nvidia,pins = "sdmmc4_dat6_paa6"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4-dat7-paa7 { - nvidia,pins = "sdmmc4_dat7_paa7"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4-clk-pcc4 { - nvidia,pins = "sdmmc4_clk_pcc4"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4-cmd-pt7 { - nvidia,pins = "sdmmc4_cmd_pt7"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* JTAG_RTCK */ - jtag-rtck { - nvidia,pins = "jtag_rtck"; - nvidia,function = "rtck"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* LAN_DEV_OFF# */ - ulpi-data5-po6 { - nvidia,pins = "ulpi_data5_po6"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* LAN_RESET# */ - kb-row10-ps2 { - nvidia,pins = "kb_row10_ps2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* LAN_WAKE# */ - ulpi-data4-po5 { - nvidia,pins = "ulpi_data4_po5"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* MCU_INT1# */ - pk2 { - nvidia,pins = "pk2"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* MCU_INT2# */ - pj2 { - nvidia,pins = "pj2"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* MCU_INT3# */ - pi5 { - nvidia,pins = "pi5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* MCU_INT4# */ - pj0 { - nvidia,pins = "pj0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* MCU_RESET */ - pbb6 { - nvidia,pins = "pbb6"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* MCU SPI */ - gpio-x4-aud-px4 { - nvidia,pins = "gpio_x4_aud_px4"; - nvidia,function = "spi2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio-x5-aud-px5 { - nvidia,pins = "gpio_x5_aud_px5"; - nvidia,function = "spi2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio-x6-aud-px6 { /* MCU_CS */ - nvidia,pins = "gpio_x6_aud_px6"; - nvidia,function = "spi2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio-x7-aud-px7 { - nvidia,pins = "gpio_x7_aud_px7"; - nvidia,function = "spi2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio-w2-aud-pw2 { /* MCU_CSEZP */ - nvidia,pins = "gpio_w2_aud_pw2"; - nvidia,function = "spi2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* PMIC_CLK_32K */ - clk-32k-in { - nvidia,pins = "clk_32k_in"; - nvidia,function = "clk"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* PMIC_CPU_OC_INT */ - clk-32k-out-pa0 { - nvidia,pins = "clk_32k_out_pa0"; - nvidia,function = "soc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* PWR_I2C */ - pwr-i2c-scl-pz6 { - nvidia,pins = "pwr_i2c_scl_pz6"; - nvidia,function = "i2cpwr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pwr-i2c-sda-pz7 { - nvidia,pins = "pwr_i2c_sda_pz7"; - nvidia,function = "i2cpwr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - - /* PWR_INT_N */ - pwr-int-n { - nvidia,pins = "pwr_int_n"; - nvidia,function = "pmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* RESET_MOCI_CTRL */ - pu4 { - nvidia,pins = "pu4"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* RESET_OUT_N */ - reset-out-n { - nvidia,pins = "reset_out_n"; - nvidia,function = "reset_out_n"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* SHIFT_CTRL_DIR_IN */ - kb-row0-pr0 { - nvidia,pins = "kb_row0_pr0"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-row1-pr1 { - nvidia,pins = "kb_row1_pr1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Configure level-shifter as output for HDA */ - kb-row11-ps3 { - nvidia,pins = "kb_row11_ps3"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* SHIFT_CTRL_DIR_OUT */ - kb-col5-pq5 { - nvidia,pins = "kb_col5_pq5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-col6-pq6 { - nvidia,pins = "kb_col6_pq6"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-col7-pq7 { - nvidia,pins = "kb_col7_pq7"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* SHIFT_CTRL_OE */ - kb-col0-pq0 { - nvidia,pins = "kb_col0_pq0"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-col1-pq1 { - nvidia,pins = "kb_col1_pq1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-col2-pq2 { - nvidia,pins = "kb_col2_pq2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-col4-pq4 { - nvidia,pins = "kb_col4_pq4"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-row2-pr2 { - nvidia,pins = "kb_row2_pr2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* GPIO_PI6 aka TMP451 ALERT#/THERM2# */ - pi6 { - nvidia,pins = "pi6"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* TOUCH_INT */ - gpio-w3-aud-pw3 { - nvidia,pins = "gpio_w3_aud_pw3"; - nvidia,function = "spi6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - pc7 { /* NC */ - nvidia,pins = "pc7"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg0 { /* NC */ - nvidia,pins = "pg0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg1 { /* NC */ - nvidia,pins = "pg1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg2 { /* NC */ - nvidia,pins = "pg2"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg3 { /* NC */ - nvidia,pins = "pg3"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg4 { /* NC */ - nvidia,pins = "pg4"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph4 { /* NC */ - nvidia,pins = "ph4"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph5 { /* NC */ - nvidia,pins = "ph5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph6 { /* NC */ - nvidia,pins = "ph6"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph7 { /* NC */ - nvidia,pins = "ph7"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi0 { /* NC */ - nvidia,pins = "pi0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi1 { /* NC */ - nvidia,pins = "pi1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi2 { /* NC */ - nvidia,pins = "pi2"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi4 { /* NC */ - nvidia,pins = "pi4"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi7 { /* NC */ - nvidia,pins = "pi7"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pk0 { /* NC */ - nvidia,pins = "pk0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pk1 { /* NC */ - nvidia,pins = "pk1"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pk3 { /* NC */ - nvidia,pins = "pk3"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pk4 { /* NC */ - nvidia,pins = "pk4"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap1-fs-pn0 { /* NC */ - nvidia,pins = "dap1_fs_pn0"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap1-din-pn1 { /* NC */ - nvidia,pins = "dap1_din_pn1"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap1-sclk-pn3 { /* NC */ - nvidia,pins = "dap1_sclk_pn3"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi-data7-po0 { /* NC */ - nvidia,pins = "ulpi_data7_po0"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi-data0-po1 { /* NC */ - nvidia,pins = "ulpi_data0_po1"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi-data1-po2 { /* NC */ - nvidia,pins = "ulpi_data1_po2"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi-data2-po3 { /* NC */ - nvidia,pins = "ulpi_data2_po3"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi-data3-po4 { /* NC */ - nvidia,pins = "ulpi_data3_po4"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi-data6-po7 { /* NC */ - nvidia,pins = "ulpi_data6_po7"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap4-fs-pp4 { /* NC */ - nvidia,pins = "dap4_fs_pp4"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap4-din-pp5 { /* NC */ - nvidia,pins = "dap4_din_pp5"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap4-dout-pp6 { /* NC */ - nvidia,pins = "dap4_dout_pp6"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap4-sclk-pp7 { /* NC */ - nvidia,pins = "dap4_sclk_pp7"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-col3-pq3 { /* NC */ - nvidia,pins = "kb_col3_pq3"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-row3-pr3 { /* NC */ - nvidia,pins = "kb_row3_pr3"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-row4-pr4 { /* NC */ - nvidia,pins = "kb_row4_pr4"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-row5-pr5 { /* NC */ - nvidia,pins = "kb_row5_pr5"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-row6-pr6 { /* NC */ - nvidia,pins = "kb_row6_pr6"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-row7-pr7 { /* NC */ - nvidia,pins = "kb_row7_pr7"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-row8-ps0 { /* NC */ - nvidia,pins = "kb_row8_ps0"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-row9-ps1 { /* NC */ - nvidia,pins = "kb_row9_ps1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-row12-ps4 { /* NC */ - nvidia,pins = "kb_row12_ps4"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-row13-ps5 { /* NC */ - nvidia,pins = "kb_row13_ps5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-row14-ps6 { /* NC */ - nvidia,pins = "kb_row14_ps6"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-row15-ps7 { /* NC */ - nvidia,pins = "kb_row15_ps7"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-row16-pt0 { /* NC */ - nvidia,pins = "kb_row16_pt0"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-row17-pt1 { /* NC */ - nvidia,pins = "kb_row17_pt1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu5 { /* NC */ - nvidia,pins = "pu5"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pv0 { /* NC */ - nvidia,pins = "pv0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pv1 { /* NC */ - nvidia,pins = "pv1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio-x1-aud-px1 { /* NC */ - nvidia,pins = "gpio_x1_aud_px1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio-x3-aud-px3 { /* NC */ - nvidia,pins = "gpio_x3_aud_px3"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pbb7 { /* NC */ - nvidia,pins = "pbb7"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pcc1 { /* NC */ - nvidia,pins = "pcc1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pcc2 { /* NC */ - nvidia,pins = "pcc2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk3-req-pee1 { /* NC */ - nvidia,pins = "clk3_req_pee1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap-mclk1-req-pee2 { /* NC */ - nvidia,pins = "dap_mclk1_req_pee2"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - /* - * Leave SDMMC3_CLK_LB_OUT muxed as SDMMC3 with output - * driver enabled aka not tristated and input driver - * enabled as well as it features some magic properties - * even though the external loopback is disabled and the - * internal loopback used as per - * SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1 - * bits being set to 0xfffd according to the TRM! - */ - sdmmc3-clk-lb-out-pee4 { /* NC */ - nvidia,pins = "sdmmc3_clk_lb_out_pee4"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - }; - }; - - serial@70006040 { - compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; - }; - - serial@70006200 { - compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; - }; - - serial@70006300 { - compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; - }; - - hdmi_ddc: i2c@7000c400 { - clock-frequency = <10000>; - }; - - /* PWR_I2C: power I2C to audio codec, PMIC and temperature sensor */ - i2c@7000d000 { - status = "okay"; - clock-frequency = <400000>; - - /* SGTL5000 audio codec */ - sgtl5000: codec@a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - VDDA-supply = <®_module_3v3_audio>; - VDDD-supply = <®_1v8_vddio>; - VDDIO-supply = <®_1v8_vddio>; - clocks = <&tegra_car TEGRA124_CLK_EXTERN1>; - }; - - pmic: pmic@40 { - compatible = "ams,as3722"; - reg = <0x40>; - interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; - ams,system-power-controller; - #interrupt-cells = <2>; - interrupt-controller; - gpio-controller; - #gpio-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&as3722_default>; - - as3722_default: pinmux { - gpio2-7 { - pins = "gpio2", /* PWR_EN_+V3.3 */ - "gpio7"; /* +V1.6_LPO */ - function = "gpio"; - bias-pull-up; - }; - - gpio0-1-3-4-5-6 { - pins = "gpio0", "gpio1", "gpio3", - "gpio4", "gpio5", "gpio6"; - bias-high-impedance; - }; - }; - - regulators { - vsup-sd2-supply = <®_module_3v3>; - vsup-sd3-supply = <®_module_3v3>; - vsup-sd4-supply = <®_module_3v3>; - vsup-sd5-supply = <®_module_3v3>; - vin-ldo0-supply = <®_1v35_vddio_ddr>; - vin-ldo1-6-supply = <®_module_3v3>; - vin-ldo2-5-7-supply = <®_1v8_vddio>; - vin-ldo3-4-supply = <®_module_3v3>; - vin-ldo9-10-supply = <®_module_3v3>; - vin-ldo11-supply = <®_module_3v3>; - - reg_vdd_cpu: sd0 { - regulator-name = "+VDD_CPU_AP"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1400000>; - regulator-min-microamp = <3500000>; - regulator-max-microamp = <3500000>; - regulator-always-on; - regulator-boot-on; - ams,ext-control = <2>; - }; - - sd1 { - regulator-name = "+VDD_CORE"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1350000>; - regulator-min-microamp = <2500000>; - regulator-max-microamp = <4000000>; - regulator-always-on; - regulator-boot-on; - ams,ext-control = <1>; - }; - - reg_1v35_vddio_ddr: sd2 { - regulator-name = - "+V1.35_VDDIO_DDR(sd2)"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - - sd3 { - regulator-name = - "+V1.35_VDDIO_DDR(sd3)"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - - reg_1v05_vdd: sd4 { - regulator-name = "+V1.05"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - }; - - reg_1v8_vddio: sd5 { - regulator-name = "+V1.8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_vdd_gpu: sd6 { - regulator-name = "+VDD_GPU_AP"; - regulator-min-microvolt = <650000>; - regulator-max-microvolt = <1200000>; - regulator-min-microamp = <3500000>; - regulator-max-microamp = <3500000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_1v05_avdd: ldo0 { - regulator-name = "+V1.05_AVDD"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - regulator-boot-on; - regulator-always-on; - ams,ext-control = <1>; - }; - - vddio_sdmmc1: ldo1 { - regulator-name = "VDDIO_SDMMC1"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - ldo2 { - regulator-name = "+V1.2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo3 { - regulator-name = "+V1.05_RTC"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-boot-on; - regulator-always-on; - ams,enable-tracking; - }; - - /* 1.8V for LVDS, 3.3V for eDP */ - ldo4 { - regulator-name = "AVDD_LVDS0_PLL"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - /* LDO5 not used */ - - vddio_sdmmc3: ldo6 { - regulator-name = "VDDIO_SDMMC3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - /* LDO7 not used */ - - ldo9 { - regulator-name = "+V3.3_ETH(ldo9)"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo10 { - regulator-name = "+V3.3_ETH(ldo10)"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo11 { - regulator-name = "+V1.8_VPP_FUSE"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - }; - }; - - /* - * TMP451 temperature sensor - * Note: THERM_N directly connected to AS3722 PMIC THERM - */ - temp-sensor@4c { - compatible = "ti,tmp451"; - reg = <0x4c>; - interrupt-parent = <&gpio>; - interrupts = ; - #thermal-sensor-cells = <1>; - vcc-supply = <®_module_3v3>; - }; - }; - - /* SPI2: MCU SPI */ - spi@7000d600 { - status = "okay"; - spi-max-frequency = <25000000>; - }; - - pmc@7000e400 { - nvidia,invert-interrupt; - nvidia,suspend-mode = <1>; - nvidia,cpu-pwr-good-time = <500>; - nvidia,cpu-pwr-off-time = <300>; - nvidia,core-pwr-good-time = <641 3845>; - nvidia,core-pwr-off-time = <61036>; - nvidia,core-power-req-active-high; - nvidia,sys-clock-req-active-high; - - /* Set power_off bit in ResetControl register of AS3722 PMIC */ - i2c-thermtrip { - nvidia,i2c-controller-id = <4>; - nvidia,bus-addr = <0x40>; - nvidia,reg-addr = <0x36>; - nvidia,reg-data = <0x2>; - }; - }; - - sata@70020000 { - phys = <&{/padctl@7009f000/pads/sata/lanes/sata-0}>; - phy-names = "sata-0"; - avdd-supply = <®_1v05_vdd>; - hvdd-supply = <®_module_3v3>; - vddio-supply = <®_1v05_vdd>; - }; - - usb@70090000 { - /* USBO1, USBO1 (SS), USBH2, USBH4 and USBH4 (SS) */ - phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>, - <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>, - <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>, - <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>, - <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>; - phy-names = "usb2-0", "usb3-1", "usb2-1", "usb2-2", "usb3-0"; - avddio-pex-supply = <®_1v05_vdd>; - avdd-pll-erefe-supply = <®_1v05_avdd>; - avdd-pll-utmip-supply = <®_1v8_vddio>; - avdd-usb-ss-pll-supply = <®_1v05_vdd>; - avdd-usb-supply = <®_module_3v3>; - dvddio-pex-supply = <®_1v05_vdd>; - hvdd-usb-ss-pll-e-supply = <®_module_3v3>; - hvdd-usb-ss-supply = <®_module_3v3>; - }; - - padctl@7009f000 { - avdd-pll-utmip-supply = <®_1v8_vddio>; - avdd-pll-erefe-supply = <®_1v05_avdd>; - avdd-pex-pll-supply = <®_1v05_vdd>; - hvdd-pex-pll-e-supply = <®_module_3v3>; - - pads { - usb2 { - status = "okay"; - - lanes { - usb2-0 { - status = "okay"; - nvidia,function = "xusb"; - }; - - usb2-1 { - status = "okay"; - nvidia,function = "xusb"; - }; - - usb2-2 { - status = "okay"; - nvidia,function = "xusb"; - }; - }; - }; - - pcie { - status = "okay"; - - lanes { - pcie-0 { - status = "okay"; - nvidia,function = "usb3-ss"; - }; - - pcie-1 { - status = "okay"; - nvidia,function = "usb3-ss"; - }; - - pcie-2 { - status = "okay"; - nvidia,function = "pcie"; - }; - - pcie-3 { - status = "okay"; - nvidia,function = "pcie"; - }; - - pcie-4 { - status = "okay"; - nvidia,function = "pcie"; - }; - }; - }; - - sata { - status = "okay"; - - lanes { - sata-0 { - status = "okay"; - nvidia,function = "sata"; - }; - }; - }; - }; - - ports { - /* USBO1 */ - usb2-0 { - status = "okay"; - mode = "otg"; - vbus-supply = <®_usbo1_vbus>; - }; - - /* USBH2 */ - usb2-1 { - status = "okay"; - mode = "host"; - vbus-supply = <®_usbh_vbus>; - }; - - /* USBH4 */ - usb2-2 { - status = "okay"; - mode = "host"; - vbus-supply = <®_usbh_vbus>; - }; - - usb3-0 { - status = "okay"; - nvidia,usb2-companion = <2>; - vbus-supply = <®_usbh_vbus>; - }; - - usb3-1 { - status = "okay"; - nvidia,usb2-companion = <0>; - vbus-supply = <®_usbo1_vbus>; - }; - }; - }; - - /* eMMC */ - sdhci@700b0600 { - status = "okay"; - bus-width = <8>; - non-removable; - vmmc-supply = <®_module_3v3>; /* VCC */ - vqmmc-supply = <®_1v8_vddio>; /* VCCQ */ - mmc-ddr-1_8v; - }; - - /* CPU DFLL clock */ - clock@70110000 { - status = "okay"; - nvidia,i2c-fs-rate = <400000>; - vdd-cpu-supply = <®_vdd_cpu>; - }; - - ahub@70300000 { - i2s@70301200 { - status = "okay"; - }; - }; - - clk32k_in: osc3 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - - cpus { - cpu@0 { - vdd-cpu-supply = <®_vdd_cpu>; - }; - }; - - reg_1v05_avdd_hdmi_pll: regulator-1v05-avdd-hdmi-pll { - compatible = "regulator-fixed"; - regulator-name = "+V1.05_AVDD_HDMI_PLL"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>; - vin-supply = <®_1v05_vdd>; - }; - - reg_3v3_mxm: regulator-3v3-mxm { - compatible = "regulator-fixed"; - regulator-name = "+V3.3_MXM"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - reg_3v3_avdd_hdmi: regulator-3v3-avdd-hdmi { - compatible = "regulator-fixed"; - regulator-name = "+V3.3_AVDD_HDMI"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <®_1v05_vdd>; - }; - - reg_module_3v3: regulator-module-3v3 { - compatible = "regulator-fixed"; - regulator-name = "+V3.3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - /* PWR_EN_+V3.3 */ - gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <®_3v3_mxm>; - }; - - reg_module_3v3_audio: regulator-module-3v3-audio { - compatible = "regulator-fixed"; - regulator-name = "+V3.3_AUDIO_AVDD_S"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - sound { - compatible = "toradex,tegra-audio-sgtl5000-apalis_tk1", - "nvidia,tegra-audio-sgtl5000"; - nvidia,model = "Toradex Apalis TK1"; - nvidia,audio-routing = - "Headphone Jack", "HP_OUT", - "LINE_IN", "Line In Jack", - "MIC_IN", "Mic Jack"; - nvidia,i2s-controller = <&tegra_i2s2>; - nvidia,audio-codec = <&sgtl5000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_A>, - <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA124_CLK_EXTERN1>; - clock-names = "pll_a", "pll_a_out0", "mclk"; - }; - - thermal-zones { - cpu { - trips { - cpu-shutdown-trip { - temperature = <101000>; - hysteresis = <0>; - type = "critical"; - }; - }; - }; - - mem { - trips { - mem-shutdown-trip { - temperature = <101000>; - hysteresis = <0>; - type = "critical"; - }; - }; - }; - - gpu { - trips { - gpu-shutdown-trip { - temperature = <101000>; - hysteresis = <0>; - type = "critical"; - }; - }; - }; - }; -}; - -&gpio { - /* I210 Gigabit Ethernet Controller Reset */ - lan-reset-n { - gpio-hog; - gpios = ; - output-high; - line-name = "LAN_RESET_N"; - }; - - /* Control MXM3 pin 26 Reset Module Output Carrier Input */ - reset-moci-ctrl { - gpio-hog; - gpios = ; - output-high; - line-name = "RESET_MOCI_CTRL"; - }; -}; diff --git a/sys/gnu/dts/arm/tegra124-jetson-tk1-emc.dtsi b/sys/gnu/dts/arm/tegra124-jetson-tk1-emc.dtsi deleted file mode 100644 index 861d3f22116..00000000000 --- a/sys/gnu/dts/arm/tegra124-jetson-tk1-emc.dtsi +++ /dev/null @@ -1,2422 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/ { - clock@60006000 { - emc-timings-3 { - nvidia,ram-code = <3>; - - timing-12750000 { - clock-frequency = <12750000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - timing-20400000 { - clock-frequency = <20400000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - timing-40800000 { - clock-frequency = <40800000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - timing-68000000 { - clock-frequency = <68000000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - timing-102000000 { - clock-frequency = <102000000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - timing-204000000 { - clock-frequency = <204000000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - timing-300000000 { - clock-frequency = <300000000>; - nvidia,parent-clock-frequency = <600000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_C>; - clock-names = "emc-parent"; - }; - timing-396000000 { - clock-frequency = <396000000>; - nvidia,parent-clock-frequency = <792000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_M>; - clock-names = "emc-parent"; - }; - timing-528000000 { - clock-frequency = <528000000>; - nvidia,parent-clock-frequency = <528000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; - clock-names = "emc-parent"; - }; - timing-600000000 { - clock-frequency = <600000000>; - nvidia,parent-clock-frequency = <600000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_C_UD>; - clock-names = "emc-parent"; - }; - timing-792000000 { - clock-frequency = <792000000>; - nvidia,parent-clock-frequency = <792000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; - clock-names = "emc-parent"; - }; - timing-924000000 { - clock-frequency = <924000000>; - nvidia,parent-clock-frequency = <924000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; - clock-names = "emc-parent"; - }; - }; - }; - - external-memory-controller@7001b000 { - emc-timings-3 { - nvidia,ram-code = <3>; - - timing-12750000 { - clock-frequency = <12750000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000e000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000000 - 0x00000003 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000004 - 0x0000000a - 0x00000005 - 0x0000000b - 0x00000000 - 0x00000000 - 0x00000003 - 0x00000003 - 0x00000000 - 0x00000006 - 0x00000006 - 0x00000006 - 0x00000002 - 0x00000000 - 0x00000005 - 0x00000005 - 0x00010000 - 0x00000003 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000004 - 0x0000000c - 0x0000000d - 0x0000000f - 0x00000060 - 0x00000000 - 0x00000018 - 0x00000002 - 0x00000002 - 0x00000001 - 0x00000000 - 0x00000007 - 0x0000000f - 0x00000005 - 0x00000005 - 0x00000004 - 0x00000005 - 0x00000004 - 0x00000000 - 0x00000000 - 0x00000005 - 0x00000005 - 0x00000064 - 0x00000000 - 0x00000000 - 0x00000000 - 0x106aa298 - 0x002c00a0 - 0x00008000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x000fc000 - 0x000fc000 - 0x000fc000 - 0x000fc000 - 0x0000fc00 - 0x0000fc00 - 0x0000fc00 - 0x0000fc00 - 0x10000280 - 0x00000000 - 0x00111111 - 0x00000000 - 0x00000000 - 0x77ffc081 - 0x00000e0e - 0x81f1f108 - 0x07070004 - 0x0000003f - 0x016eeeee - 0x51451400 - 0x00514514 - 0x00514514 - 0x51451400 - 0x0000003f - 0x00000007 - 0x00000000 - 0x00000042 - 0x000e000e - 0x00000000 - 0x00000003 - 0x0000f2f3 - 0x800001c5 - 0x0000000a - >; - }; - - timing-20400000 { - clock-frequency = <20400000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000e000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000000 - 0x00000005 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000004 - 0x0000000a - 0x00000005 - 0x0000000b - 0x00000000 - 0x00000000 - 0x00000003 - 0x00000003 - 0x00000000 - 0x00000006 - 0x00000006 - 0x00000006 - 0x00000002 - 0x00000000 - 0x00000005 - 0x00000005 - 0x00010000 - 0x00000003 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000004 - 0x0000000c - 0x0000000d - 0x0000000f - 0x0000009a - 0x00000000 - 0x00000026 - 0x00000002 - 0x00000002 - 0x00000001 - 0x00000000 - 0x00000007 - 0x0000000f - 0x00000006 - 0x00000006 - 0x00000004 - 0x00000005 - 0x00000004 - 0x00000000 - 0x00000000 - 0x00000005 - 0x00000005 - 0x000000a0 - 0x00000000 - 0x00000000 - 0x00000000 - 0x106aa298 - 0x002c00a0 - 0x00008000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x000fc000 - 0x000fc000 - 0x000fc000 - 0x000fc000 - 0x0000fc00 - 0x0000fc00 - 0x0000fc00 - 0x0000fc00 - 0x10000280 - 0x00000000 - 0x00111111 - 0x00000000 - 0x00000000 - 0x77ffc081 - 0x00000e0e - 0x81f1f108 - 0x07070004 - 0x0000003f - 0x016eeeee - 0x51451400 - 0x00514514 - 0x00514514 - 0x51451400 - 0x0000003f - 0x0000000b - 0x00000000 - 0x00000042 - 0x000e000e - 0x00000000 - 0x00000003 - 0x0000f2f3 - 0x8000023a - 0x0000000a - >; - }; - - timing-40800000 { - clock-frequency = <40800000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000e000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000001 - 0x0000000a - 0x00000000 - 0x00000001 - 0x00000000 - 0x00000004 - 0x0000000a - 0x00000005 - 0x0000000b - 0x00000000 - 0x00000000 - 0x00000003 - 0x00000003 - 0x00000000 - 0x00000006 - 0x00000006 - 0x00000006 - 0x00000002 - 0x00000000 - 0x00000005 - 0x00000005 - 0x00010000 - 0x00000003 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000004 - 0x0000000c - 0x0000000d - 0x0000000f - 0x00000134 - 0x00000000 - 0x0000004d - 0x00000002 - 0x00000002 - 0x00000001 - 0x00000000 - 0x00000008 - 0x0000000f - 0x0000000c - 0x0000000c - 0x00000004 - 0x00000005 - 0x00000004 - 0x00000000 - 0x00000000 - 0x00000005 - 0x00000005 - 0x0000013f - 0x00000000 - 0x00000000 - 0x00000000 - 0x106aa298 - 0x002c00a0 - 0x00008000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x000fc000 - 0x000fc000 - 0x000fc000 - 0x000fc000 - 0x0000fc00 - 0x0000fc00 - 0x0000fc00 - 0x0000fc00 - 0x10000280 - 0x00000000 - 0x00111111 - 0x00000000 - 0x00000000 - 0x77ffc081 - 0x00000e0e - 0x81f1f108 - 0x07070004 - 0x0000003f - 0x016eeeee - 0x51451400 - 0x00514514 - 0x00514514 - 0x51451400 - 0x0000003f - 0x00000015 - 0x00000000 - 0x00000042 - 0x000e000e - 0x00000000 - 0x00000003 - 0x0000f2f3 - 0x80000370 - 0x0000000a - >; - }; - - timing-68000000 { - clock-frequency = <68000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000e000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000003 - 0x00000011 - 0x00000000 - 0x00000002 - 0x00000000 - 0x00000004 - 0x0000000a - 0x00000005 - 0x0000000b - 0x00000000 - 0x00000000 - 0x00000003 - 0x00000003 - 0x00000000 - 0x00000006 - 0x00000006 - 0x00000006 - 0x00000002 - 0x00000000 - 0x00000005 - 0x00000005 - 0x00010000 - 0x00000003 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000004 - 0x0000000c - 0x0000000d - 0x0000000f - 0x00000202 - 0x00000000 - 0x00000080 - 0x00000002 - 0x00000002 - 0x00000001 - 0x00000000 - 0x0000000f - 0x0000000f - 0x00000013 - 0x00000013 - 0x00000004 - 0x00000005 - 0x00000004 - 0x00000001 - 0x00000000 - 0x00000005 - 0x00000005 - 0x00000213 - 0x00000000 - 0x00000000 - 0x00000000 - 0x106aa298 - 0x002c00a0 - 0x00008000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x000fc000 - 0x000fc000 - 0x000fc000 - 0x000fc000 - 0x0000fc00 - 0x0000fc00 - 0x0000fc00 - 0x0000fc00 - 0x10000280 - 0x00000000 - 0x00111111 - 0x00000000 - 0x00000000 - 0x77ffc081 - 0x00000e0e - 0x81f1f108 - 0x07070004 - 0x0000003f - 0x016eeeee - 0x51451400 - 0x00514514 - 0x00514514 - 0x51451400 - 0x0000003f - 0x00000022 - 0x00000000 - 0x00000042 - 0x000e000e - 0x00000000 - 0x00000003 - 0x0000f2f3 - 0x8000050e - 0x0000000a - >; - }; - - timing-102000000 { - clock-frequency = <102000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000e000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000004 - 0x0000001a - 0x00000000 - 0x00000003 - 0x00000001 - 0x00000004 - 0x0000000a - 0x00000005 - 0x0000000b - 0x00000001 - 0x00000001 - 0x00000003 - 0x00000003 - 0x00000000 - 0x00000006 - 0x00000006 - 0x00000006 - 0x00000002 - 0x00000000 - 0x00000005 - 0x00000005 - 0x00010000 - 0x00000003 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000004 - 0x0000000c - 0x0000000d - 0x0000000f - 0x00000304 - 0x00000000 - 0x000000c1 - 0x00000002 - 0x00000002 - 0x00000001 - 0x00000000 - 0x00000018 - 0x0000000f - 0x0000001c - 0x0000001c - 0x00000004 - 0x00000005 - 0x00000004 - 0x00000002 - 0x00000000 - 0x00000005 - 0x00000005 - 0x0000031c - 0x00000000 - 0x00000000 - 0x00000000 - 0x106aa298 - 0x002c00a0 - 0x00008000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x000fc000 - 0x000fc000 - 0x000fc000 - 0x000fc000 - 0x0000fc00 - 0x0000fc00 - 0x0000fc00 - 0x0000fc00 - 0x10000280 - 0x00000000 - 0x00111111 - 0x00000000 - 0x00000000 - 0x77ffc081 - 0x00000e0e - 0x81f1f108 - 0x07070004 - 0x0000003f - 0x016eeeee - 0x51451400 - 0x00514514 - 0x00514514 - 0x51451400 - 0x0000003f - 0x00000033 - 0x00000000 - 0x00000042 - 0x000e000e - 0x00000000 - 0x00000003 - 0x0000f2f3 - 0x80000713 - 0x0000000a - >; - }; - - timing-204000000 { - clock-frequency = <204000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008cd>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000e000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x00000009 - 0x00000035 - 0x00000000 - 0x00000006 - 0x00000002 - 0x00000005 - 0x0000000a - 0x00000005 - 0x0000000b - 0x00000002 - 0x00000002 - 0x00000003 - 0x00000003 - 0x00000000 - 0x00000005 - 0x00000005 - 0x00000006 - 0x00000002 - 0x00000000 - 0x00000004 - 0x00000006 - 0x00010000 - 0x00000003 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000003 - 0x0000000d - 0x0000000f - 0x00000011 - 0x00000607 - 0x00000000 - 0x00000181 - 0x00000002 - 0x00000002 - 0x00000001 - 0x00000000 - 0x00000032 - 0x0000000f - 0x00000038 - 0x00000038 - 0x00000004 - 0x00000005 - 0x00000004 - 0x00000006 - 0x00000000 - 0x00000005 - 0x00000005 - 0x00000638 - 0x00000000 - 0x00000000 - 0x00000000 - 0x106aa298 - 0x002c00a0 - 0x00008000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00008000 - 0x00000000 - 0x00000000 - 0x00008000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00090000 - 0x00090000 - 0x00090000 - 0x00090000 - 0x00009000 - 0x00009000 - 0x00009000 - 0x00009000 - 0x10000280 - 0x00000000 - 0x00111111 - 0x00000000 - 0x00000000 - 0x77ffc081 - 0x00000707 - 0x81f1f108 - 0x07070004 - 0x0000003f - 0x016eeeee - 0x51451400 - 0x00514514 - 0x00514514 - 0x51451400 - 0x0000003f - 0x00000066 - 0x00000000 - 0x00000100 - 0x000e000e - 0x00000000 - 0x00000003 - 0x0000d2b3 - 0x80000d22 - 0x0000000a - >; - }; - - timing-300000000 { - clock-frequency = <300000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73340000>; - nvidia,emc-cfg-2 = <0x000008d5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200000>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000321>; - nvidia,emc-mrs-wait-cnt = <0x0173000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x01231339>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x0000000d - 0x0000004d - 0x00000000 - 0x00000009 - 0x00000003 - 0x00000004 - 0x00000008 - 0x00000002 - 0x00000009 - 0x00000003 - 0x00000003 - 0x00000002 - 0x00000002 - 0x00000000 - 0x00000003 - 0x00000003 - 0x00000005 - 0x00000002 - 0x00000000 - 0x00000002 - 0x00000007 - 0x00020000 - 0x00000003 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000001 - 0x0000000e - 0x00000010 - 0x00000012 - 0x000008e4 - 0x00000000 - 0x00000239 - 0x00000001 - 0x00000008 - 0x00000001 - 0x00000000 - 0x0000004b - 0x0000000e - 0x00000052 - 0x00000200 - 0x00000004 - 0x00000005 - 0x00000004 - 0x00000008 - 0x00000000 - 0x00000005 - 0x00000005 - 0x00000924 - 0x00000000 - 0x00000000 - 0x00000000 - 0x104ab098 - 0x002c00a0 - 0x00008000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00098000 - 0x00098000 - 0x00000000 - 0x00098000 - 0x00098000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00050000 - 0x00050000 - 0x00050000 - 0x00050000 - 0x00005000 - 0x00005000 - 0x00005000 - 0x00005000 - 0x10000280 - 0x00000000 - 0x00111111 - 0x00000000 - 0x00000000 - 0x77ffc081 - 0x00000505 - 0x81f1f108 - 0x07070004 - 0x00000000 - 0x016eeeee - 0x51451420 - 0x00514514 - 0x00514514 - 0x51451400 - 0x0000003f - 0x00000096 - 0x00000000 - 0x00000100 - 0x0173000e - 0x00000000 - 0x00000003 - 0x000052a3 - 0x800012d7 - 0x00000009 - >; - }; - - timing-396000000 { - clock-frequency = <396000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73340000>; - nvidia,emc-cfg-2 = <0x00000895>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200000>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000521>; - nvidia,emc-mrs-wait-cnt = <0x015b000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040008>; - nvidia,emc-xm2dqspadctrl2 = <0x01231339>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x00000011 - 0x00000066 - 0x00000000 - 0x0000000c - 0x00000004 - 0x00000004 - 0x00000008 - 0x00000002 - 0x0000000a - 0x00000004 - 0x00000004 - 0x00000002 - 0x00000002 - 0x00000000 - 0x00000003 - 0x00000003 - 0x00000005 - 0x00000002 - 0x00000000 - 0x00000001 - 0x00000008 - 0x00020000 - 0x00000003 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x0000000f - 0x00000010 - 0x00000012 - 0x00000bd1 - 0x00000000 - 0x000002f4 - 0x00000001 - 0x00000008 - 0x00000001 - 0x00000000 - 0x00000063 - 0x0000000f - 0x0000006c - 0x00000200 - 0x00000004 - 0x00000005 - 0x00000004 - 0x0000000b - 0x00000000 - 0x00000005 - 0x00000005 - 0x00000c11 - 0x00000000 - 0x00000000 - 0x00000000 - 0x104ab098 - 0x002c00a0 - 0x00008000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00070000 - 0x00070000 - 0x00000000 - 0x00070000 - 0x00070000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00038000 - 0x00038000 - 0x00038000 - 0x00038000 - 0x00003800 - 0x00003800 - 0x00003800 - 0x00003800 - 0x10000280 - 0x00000000 - 0x00111111 - 0x00000000 - 0x00000000 - 0x77ffc081 - 0x00000505 - 0x81f1f108 - 0x07070004 - 0x00000000 - 0x016eeeee - 0x51451420 - 0x00514514 - 0x00514514 - 0x51451400 - 0x0000003f - 0x000000c6 - 0x00000000 - 0x00000100 - 0x015b000e - 0x00000000 - 0x00000003 - 0x000052a3 - 0x8000188b - 0x00000009 - >; - }; - - timing-528000000 { - clock-frequency = <528000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73300000>; - nvidia,emc-cfg-2 = <0x0000089d>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000941>; - nvidia,emc-mrs-wait-cnt = <0x0139000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040008>; - nvidia,emc-xm2dqspadctrl2 = <0x0123133d>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x00000018 - 0x00000088 - 0x00000000 - 0x00000010 - 0x00000006 - 0x00000006 - 0x00000009 - 0x00000002 - 0x0000000d - 0x00000006 - 0x00000006 - 0x00000002 - 0x00000002 - 0x00000000 - 0x00000003 - 0x00000003 - 0x00000006 - 0x00000002 - 0x00000000 - 0x00000001 - 0x00000009 - 0x00030000 - 0x00000003 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000010 - 0x00000012 - 0x00000014 - 0x00000fd6 - 0x00000000 - 0x000003f5 - 0x00000002 - 0x0000000b - 0x00000001 - 0x00000000 - 0x00000085 - 0x00000012 - 0x00000090 - 0x00000200 - 0x00000004 - 0x00000005 - 0x00000004 - 0x00000010 - 0x00000000 - 0x00000006 - 0x00000006 - 0x00001017 - 0x00000000 - 0x00000000 - 0x00000000 - 0x104ab098 - 0xe01200b1 - 0x00008000 - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00054000 - 0x00054000 - 0x00000000 - 0x00054000 - 0x00054000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x0000000c - 0x0000000c - 0x0000000c - 0x0000000c - 0x0000000c - 0x0000000c - 0x0000000c - 0x0000000c - 0x100002a0 - 0x00000000 - 0x00111111 - 0x00000000 - 0x00000000 - 0x77ffc085 - 0x00000505 - 0x81f1f108 - 0x07070004 - 0x00000000 - 0x016eeeee - 0x51451420 - 0x00514514 - 0x00514514 - 0x51451400 - 0x0606003f - 0x00000000 - 0x00000000 - 0x00000100 - 0x0139000e - 0x00000000 - 0x00000003 - 0x000042a0 - 0x80002062 - 0x0000000a - >; - }; - - timing-600000000 { - clock-frequency = <600000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73300000>; - nvidia,emc-cfg-2 = <0x0000089d>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200010>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000b61>; - nvidia,emc-mrs-wait-cnt = <0x0127000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040008>; - nvidia,emc-xm2dqspadctrl2 = <0x0121113d>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x0000001b - 0x0000009b - 0x00000000 - 0x00000013 - 0x00000007 - 0x00000007 - 0x0000000b - 0x00000003 - 0x00000010 - 0x00000007 - 0x00000007 - 0x00000002 - 0x00000002 - 0x00000000 - 0x00000005 - 0x00000005 - 0x0000000a - 0x00000002 - 0x00000000 - 0x00000003 - 0x0000000b - 0x00070000 - 0x00000003 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000002 - 0x00000012 - 0x00000016 - 0x00000018 - 0x00001208 - 0x00000000 - 0x00000482 - 0x00000002 - 0x0000000d - 0x00000001 - 0x00000000 - 0x00000097 - 0x00000015 - 0x000000a3 - 0x00000200 - 0x00000004 - 0x00000005 - 0x00000004 - 0x00000013 - 0x00000000 - 0x00000006 - 0x00000006 - 0x00001248 - 0x00000000 - 0x00000000 - 0x00000000 - 0x104ab098 - 0xe00e00b1 - 0x00008000 - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00048000 - 0x00048000 - 0x00000000 - 0x00048000 - 0x00048000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x0000000d - 0x0000000d - 0x0000000d - 0x0000000d - 0x0000000d - 0x0000000d - 0x0000000d - 0x0000000d - 0x100002a0 - 0x00000000 - 0x00111111 - 0x00000000 - 0x00000000 - 0x77ffc085 - 0x00000505 - 0x81f1f108 - 0x07070004 - 0x00000000 - 0x016eeeee - 0x51451420 - 0x00514514 - 0x00514514 - 0x51451400 - 0x0606003f - 0x00000000 - 0x00000000 - 0x00000100 - 0x0127000e - 0x00000000 - 0x00000003 - 0x000040a0 - 0x800024aa - 0x0000000e - >; - }; - - timing-792000000 { - clock-frequency = <792000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73300000>; - nvidia,emc-cfg-2 = <0x0000089d>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200018>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000d71>; - nvidia,emc-mrs-wait-cnt = <0x00f7000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040000>; - nvidia,emc-xm2dqspadctrl2 = <0x0120113d>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x00000024 - 0x000000cd - 0x00000000 - 0x00000019 - 0x0000000a - 0x00000008 - 0x0000000d - 0x00000004 - 0x00000013 - 0x0000000a - 0x0000000a - 0x00000004 - 0x00000002 - 0x00000000 - 0x00000006 - 0x00000006 - 0x0000000b - 0x00000002 - 0x00000000 - 0x00000002 - 0x0000000d - 0x00080000 - 0x00000004 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000001 - 0x00000014 - 0x00000018 - 0x0000001a - 0x000017e2 - 0x00000000 - 0x000005f8 - 0x00000003 - 0x00000011 - 0x00000001 - 0x00000000 - 0x000000c7 - 0x00000018 - 0x000000d7 - 0x00000200 - 0x00000005 - 0x00000006 - 0x00000005 - 0x00000019 - 0x00000000 - 0x00000008 - 0x00000008 - 0x00001822 - 0x00000000 - 0x00000000 - 0x00000000 - 0x104ab098 - 0xe00700b1 - 0x00008000 - 0x007fc008 - 0x007fc008 - 0x007fc008 - 0x007fc008 - 0x007fc008 - 0x007fc008 - 0x007fc008 - 0x007fc008 - 0x007fc008 - 0x007fc008 - 0x007fc008 - 0x007fc008 - 0x007fc008 - 0x007fc008 - 0x007fc008 - 0x007fc008 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00034000 - 0x00034000 - 0x00000000 - 0x00034000 - 0x00034000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000005 - 0x00000005 - 0x00000005 - 0x00000005 - 0x00000005 - 0x00000005 - 0x00000005 - 0x00000005 - 0x00000005 - 0x00000005 - 0x00000005 - 0x00000005 - 0x00000005 - 0x00000005 - 0x00000005 - 0x00000005 - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x100002a0 - 0x00000000 - 0x00111111 - 0x00000000 - 0x00000000 - 0x77ffc085 - 0x00000000 - 0x81f1f108 - 0x07070004 - 0x00000000 - 0x016eeeee - 0x61861820 - 0x00514514 - 0x00514514 - 0x61861800 - 0x0606003f - 0x00000000 - 0x00000000 - 0x00000100 - 0x00f7000e - 0x00000000 - 0x00000004 - 0x00004080 - 0x80003012 - 0x0000000f - >; - }; - - timing-924000000 { - clock-frequency = <924000000>; - - nvidia,emc-auto-cal-config = <0xa1430303>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73300000>; - nvidia,emc-cfg-2 = <0x0000089d>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200020>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000f15>; - nvidia,emc-mrs-wait-cnt = <0x00cd000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040000>; - nvidia,emc-xm2dqspadctrl2 = <0x0120113d>; - nvidia,emc-zcal-cnt-long = <0x0000004c>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x0000002b - 0x000000f0 - 0x00000000 - 0x0000001e - 0x0000000b - 0x00000009 - 0x0000000f - 0x00000005 - 0x00000016 - 0x0000000b - 0x0000000b - 0x00000004 - 0x00000002 - 0x00000000 - 0x00000007 - 0x00000007 - 0x0000000d - 0x00000002 - 0x00000000 - 0x00000002 - 0x0000000f - 0x000a0000 - 0x00000004 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000001 - 0x00000016 - 0x0000001a - 0x0000001c - 0x00001be7 - 0x00000000 - 0x000006f9 - 0x00000004 - 0x00000015 - 0x00000001 - 0x00000000 - 0x000000e7 - 0x0000001b - 0x000000fb - 0x00000200 - 0x00000006 - 0x00000007 - 0x00000006 - 0x0000001e - 0x00000000 - 0x0000000a - 0x0000000a - 0x00001c28 - 0x00000000 - 0x00000000 - 0x00000000 - 0x104ab898 - 0xe00400b1 - 0x00008000 - 0x007f800a - 0x007f800a - 0x007f800a - 0x007f800a - 0x007f800a - 0x007f800a - 0x007f800a - 0x007f800a - 0x007f800a - 0x007f800a - 0x007f800a - 0x007f800a - 0x007f800a - 0x007f800a - 0x007f800a - 0x007f800a - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x0002c000 - 0x0002c000 - 0x00000000 - 0x0002c000 - 0x0002c000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000004 - 0x00000004 - 0x00000004 - 0x00000004 - 0x00000004 - 0x00000004 - 0x00000004 - 0x00000004 - 0x00000004 - 0x00000004 - 0x00000004 - 0x00000004 - 0x00000004 - 0x00000004 - 0x00000004 - 0x00000004 - 0x00000008 - 0x00000008 - 0x00000008 - 0x00000008 - 0x00000008 - 0x00000008 - 0x00000008 - 0x00000008 - 0x100002a0 - 0x00000000 - 0x00111111 - 0x00000000 - 0x00000000 - 0x77ffc085 - 0x00000000 - 0x81f1f108 - 0x07070004 - 0x00000000 - 0x016eeeee - 0x5d75d720 - 0x00514514 - 0x00514514 - 0x5d75d700 - 0x0606003f - 0x00000000 - 0x00000000 - 0x00000128 - 0x00cd000e - 0x00000000 - 0x00000004 - 0x00004080 - 0x800037ea - 0x00000011 - >; - }; - - }; - }; - - memory-controller@70019000 { - emc-timings-3 { - nvidia,ram-code = <3>; - - timing-12750000 { - clock-frequency = <12750000>; - - nvidia,emem-configuration = < - 0x40040001 - 0x8000000a - 0x00000001 - 0x00000001 - 0x00000002 - 0x00000000 - 0x00000002 - 0x00000001 - 0x00000003 - 0x00000008 - 0x00000003 - 0x00000002 - 0x00000003 - 0x00000006 - 0x06030203 - 0x000a0502 - 0x77e30303 - 0x70000f03 - 0x001f0000 - >; - }; - - timing-20400000 { - clock-frequency = <20400000>; - - nvidia,emem-configuration = < - 0x40020001 - 0x80000012 - 0x00000001 - 0x00000001 - 0x00000002 - 0x00000000 - 0x00000002 - 0x00000001 - 0x00000003 - 0x00000008 - 0x00000003 - 0x00000002 - 0x00000003 - 0x00000006 - 0x06030203 - 0x000a0502 - 0x76230303 - 0x70000f03 - 0x001f0000 - >; - }; - - timing-40800000 { - clock-frequency = <40800000>; - - nvidia,emem-configuration = < - 0xa0000001 - 0x80000017 - 0x00000001 - 0x00000001 - 0x00000002 - 0x00000000 - 0x00000002 - 0x00000001 - 0x00000003 - 0x00000008 - 0x00000003 - 0x00000002 - 0x00000003 - 0x00000006 - 0x06030203 - 0x000a0502 - 0x74a30303 - 0x70000f03 - 0x001f0000 - >; - }; - - timing-68000000 { - clock-frequency = <68000000>; - - nvidia,emem-configuration = < - 0x00000001 - 0x8000001e - 0x00000001 - 0x00000001 - 0x00000002 - 0x00000000 - 0x00000002 - 0x00000001 - 0x00000003 - 0x00000008 - 0x00000003 - 0x00000002 - 0x00000003 - 0x00000006 - 0x06030203 - 0x000a0502 - 0x74230403 - 0x70000f03 - 0x001f0000 - >; - }; - - timing-102000000 { - clock-frequency = <102000000>; - - nvidia,emem-configuration = < - 0x08000001 - 0x80000026 - 0x00000001 - 0x00000001 - 0x00000003 - 0x00000000 - 0x00000002 - 0x00000001 - 0x00000003 - 0x00000008 - 0x00000003 - 0x00000002 - 0x00000003 - 0x00000006 - 0x06030203 - 0x000a0503 - 0x73c30504 - 0x70000f03 - 0x001f0000 - >; - }; - - timing-204000000 { - clock-frequency = <204000000>; - - nvidia,emem-configuration = < - 0x01000003 - 0x80000040 - 0x00000001 - 0x00000001 - 0x00000004 - 0x00000002 - 0x00000003 - 0x00000001 - 0x00000003 - 0x00000008 - 0x00000003 - 0x00000002 - 0x00000004 - 0x00000006 - 0x06040203 - 0x000a0504 - 0x73840a05 - 0x70000f03 - 0x001f0000 - >; - }; - - timing-300000000 { - clock-frequency = <300000000>; - - nvidia,emem-configuration = < - 0x08000004 - 0x80000040 - 0x00000001 - 0x00000002 - 0x00000007 - 0x00000004 - 0x00000004 - 0x00000001 - 0x00000002 - 0x00000007 - 0x00000002 - 0x00000002 - 0x00000004 - 0x00000006 - 0x06040202 - 0x000b0607 - 0x77450e08 - 0x70000f03 - 0x001f0000 - >; - }; - - timing-396000000 { - clock-frequency = <396000000>; - - nvidia,emem-configuration = < - 0x0f000005 - 0x80000040 - 0x00000001 - 0x00000002 - 0x00000009 - 0x00000005 - 0x00000006 - 0x00000001 - 0x00000002 - 0x00000008 - 0x00000002 - 0x00000002 - 0x00000004 - 0x00000006 - 0x06040202 - 0x000d0709 - 0x7586120a - 0x70000f03 - 0x001f0000 - >; - }; - - timing-528000000 { - clock-frequency = <528000000>; - - nvidia,emem-configuration = < - 0x0f000007 - 0x80000040 - 0x00000002 - 0x00000003 - 0x0000000c - 0x00000007 - 0x00000008 - 0x00000001 - 0x00000002 - 0x00000009 - 0x00000002 - 0x00000002 - 0x00000005 - 0x00000006 - 0x06050202 - 0x0010090c - 0x7428180d - 0x70000f03 - 0x001f0000 - >; - }; - - timing-600000000 { - clock-frequency = <600000000>; - - nvidia,emem-configuration = < - 0x00000009 - 0x80000040 - 0x00000003 - 0x00000004 - 0x0000000e - 0x00000009 - 0x0000000a - 0x00000001 - 0x00000003 - 0x0000000b - 0x00000002 - 0x00000002 - 0x00000005 - 0x00000007 - 0x07050202 - 0x00130b0e - 0x73a91b0f - 0x70000f03 - 0x001f0000 - >; - }; - - timing-792000000 { - clock-frequency = <792000000>; - - nvidia,emem-configuration = < - 0x0e00000b - 0x80000040 - 0x00000004 - 0x00000005 - 0x00000013 - 0x0000000c - 0x0000000d - 0x00000002 - 0x00000003 - 0x0000000c - 0x00000002 - 0x00000002 - 0x00000006 - 0x00000008 - 0x08060202 - 0x00170e13 - 0x736c2414 - 0x70000f02 - 0x001f0000 - >; - }; - - timing-924000000 { - clock-frequency = <924000000>; - - nvidia,emem-configuration = < - 0x0e00000d - 0x80000040 - 0x00000005 - 0x00000006 - 0x00000016 - 0x0000000e - 0x0000000f - 0x00000002 - 0x00000004 - 0x0000000e - 0x00000002 - 0x00000002 - 0x00000006 - 0x00000009 - 0x09060202 - 0x001a1016 - 0x734e2a17 - 0x70000f02 - 0x001f0000 - >; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/tegra124-jetson-tk1.dts b/sys/gnu/dts/arm/tegra124-jetson-tk1.dts deleted file mode 100644 index d5fd642f8b7..00000000000 --- a/sys/gnu/dts/arm/tegra124-jetson-tk1.dts +++ /dev/null @@ -1,2096 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include -#include "tegra124.dtsi" - -#include "tegra124-jetson-tk1-emc.dtsi" - -/ { - model = "NVIDIA Tegra124 Jetson TK1"; - compatible = "nvidia,jetson-tk1", "nvidia,tegra124"; - - aliases { - rtc0 = "/i2c@7000d000/pmic@40"; - rtc1 = "/rtc@7000e000"; - - /* This order keeps the mapping DB9 connector <-> ttyS0 */ - serial0 = &uartd; - serial1 = &uarta; - serial2 = &uartb; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@80000000 { - reg = <0x0 0x80000000 0x0 0x80000000>; - }; - - pcie@1003000 { - status = "okay"; - - avddio-pex-supply = <&vdd_1v05_run>; - dvddio-pex-supply = <&vdd_1v05_run>; - avdd-pex-pll-supply = <&vdd_1v05_run>; - hvdd-pex-supply = <&vdd_3v3_lp0>; - hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>; - vddio-pex-ctl-supply = <&vdd_3v3_lp0>; - avdd-pll-erefe-supply = <&avdd_1v05_run>; - - /* Mini PCIe */ - pci@1,0 { - phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>; - phy-names = "pcie-0"; - status = "okay"; - }; - - /* Gigabit Ethernet */ - pci@2,0 { - phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>; - phy-names = "pcie-0"; - status = "okay"; - }; - }; - - host1x@50000000 { - hdmi@54280000 { - status = "okay"; - - hdmi-supply = <&vdd_5v0_hdmi>; - pll-supply = <&vdd_hdmi_pll>; - vdd-supply = <&vdd_3v3_hdmi>; - - nvidia,ddc-i2c-bus = <&hdmi_ddc>; - nvidia,hpd-gpio = - <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; - }; - }; - - cec@70015000 { - status = "okay"; - }; - - gpu@0,57000000 { - /* - * Node left disabled on purpose - the bootloader will enable - * it after having set the VPR up - */ - vdd-supply = <&vdd_gpu>; - }; - - pinmux: pinmux@70000868 { - pinctrl-names = "boot"; - pinctrl-0 = <&state_boot>; - - state_boot: pinmux { - clk_32k_out_pa0 { - nvidia,pins = "clk_32k_out_pa0"; - nvidia,function = "soc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart3_cts_n_pa1 { - nvidia,pins = "uart3_cts_n_pa1"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap2_fs_pa2 { - nvidia,pins = "dap2_fs_pa2"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap2_sclk_pa3 { - nvidia,pins = "dap2_sclk_pa3"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap2_din_pa4 { - nvidia,pins = "dap2_din_pa4"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap2_dout_pa5 { - nvidia,pins = "dap2_dout_pa5"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_clk_pa6 { - nvidia,pins = "sdmmc3_clk_pa6"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_cmd_pa7 { - nvidia,pins = "sdmmc3_cmd_pa7"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pb0 { - nvidia,pins = "pb0"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pb1 { - nvidia,pins = "pb1"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_dat3_pb4 { - nvidia,pins = "sdmmc3_dat3_pb4"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_dat2_pb5 { - nvidia,pins = "sdmmc3_dat2_pb5"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_dat1_pb6 { - nvidia,pins = "sdmmc3_dat1_pb6"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_dat0_pb7 { - nvidia,pins = "sdmmc3_dat0_pb7"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart3_rts_n_pc0 { - nvidia,pins = "uart3_rts_n_pc0"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2_txd_pc2 { - nvidia,pins = "uart2_txd_pc2"; - nvidia,function = "irda"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2_rxd_pc3 { - nvidia,pins = "uart2_rxd_pc3"; - nvidia,function = "irda"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gen1_i2c_scl_pc4 { - nvidia,pins = "gen1_i2c_scl_pc4"; - nvidia,function = "i2c1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gen1_i2c_sda_pc5 { - nvidia,pins = "gen1_i2c_sda_pc5"; - nvidia,function = "i2c1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pc7 { - nvidia,pins = "pc7"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg0 { - nvidia,pins = "pg0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg1 { - nvidia,pins = "pg1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg2 { - nvidia,pins = "pg2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg3 { - nvidia,pins = "pg3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg4 { - nvidia,pins = "pg4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg5 { - nvidia,pins = "pg5"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg6 { - nvidia,pins = "pg6"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg7 { - nvidia,pins = "pg7"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph0 { - nvidia,pins = "ph0"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph1 { - nvidia,pins = "ph1"; - nvidia,function = "pwm1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph2 { - nvidia,pins = "ph2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph3 { - nvidia,pins = "ph3"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph4 { - nvidia,pins = "ph4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph5 { - nvidia,pins = "ph5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph6 { - nvidia,pins = "ph6"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph7 { - nvidia,pins = "ph7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi0 { - nvidia,pins = "pi0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi1 { - nvidia,pins = "pi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi2 { - nvidia,pins = "pi2"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi3 { - nvidia,pins = "pi3"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi4 { - nvidia,pins = "pi4"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi5 { - nvidia,pins = "pi5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi6 { - nvidia,pins = "pi6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi7 { - nvidia,pins = "pi7"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pj0 { - nvidia,pins = "pj0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pj2 { - nvidia,pins = "pj2"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2_cts_n_pj5 { - nvidia,pins = "uart2_cts_n_pj5"; - nvidia,function = "uartb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2_rts_n_pj6 { - nvidia,pins = "uart2_rts_n_pj6"; - nvidia,function = "uartb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pj7 { - nvidia,pins = "pj7"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pk0 { - nvidia,pins = "pk0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pk1 { - nvidia,pins = "pk1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pk2 { - nvidia,pins = "pk2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pk3 { - nvidia,pins = "pk3"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pk4 { - nvidia,pins = "pk4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - spdif_out_pk5 { - nvidia,pins = "spdif_out_pk5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - spdif_in_pk6 { - nvidia,pins = "spdif_in_pk6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pk7 { - nvidia,pins = "pk7"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap1_fs_pn0 { - nvidia,pins = "dap1_fs_pn0"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap1_din_pn1 { - nvidia,pins = "dap1_din_pn1"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap1_dout_pn2 { - nvidia,pins = "dap1_dout_pn2"; - nvidia,function = "sata"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap1_sclk_pn3 { - nvidia,pins = "dap1_sclk_pn3"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - usb_vbus_en0_pn4 { - nvidia,pins = "usb_vbus_en0_pn4"; - nvidia,function = "usb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - usb_vbus_en1_pn5 { - nvidia,pins = "usb_vbus_en1_pn5"; - nvidia,function = "usb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - hdmi_int_pn7 { - nvidia,pins = "hdmi_int_pn7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,rcv-sel = ; - }; - ulpi_data7_po0 { - nvidia,pins = "ulpi_data7_po0"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data0_po1 { - nvidia,pins = "ulpi_data0_po1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data1_po2 { - nvidia,pins = "ulpi_data1_po2"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data2_po3 { - nvidia,pins = "ulpi_data2_po3"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data3_po4 { - nvidia,pins = "ulpi_data3_po4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data4_po5 { - nvidia,pins = "ulpi_data4_po5"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data5_po6 { - nvidia,pins = "ulpi_data5_po6"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data6_po7 { - nvidia,pins = "ulpi_data6_po7"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3_fs_pp0 { - nvidia,pins = "dap3_fs_pp0"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3_din_pp1 { - nvidia,pins = "dap3_din_pp1"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3_dout_pp2 { - nvidia,pins = "dap3_dout_pp2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3_sclk_pp3 { - nvidia,pins = "dap3_sclk_pp3"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap4_fs_pp4 { - nvidia,pins = "dap4_fs_pp4"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap4_din_pp5 { - nvidia,pins = "dap4_din_pp5"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap4_dout_pp6 { - nvidia,pins = "dap4_dout_pp6"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap4_sclk_pp7 { - nvidia,pins = "dap4_sclk_pp7"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col0_pq0 { - nvidia,pins = "kb_col0_pq0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col1_pq1 { - nvidia,pins = "kb_col1_pq1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col2_pq2 { - nvidia,pins = "kb_col2_pq2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col3_pq3 { - nvidia,pins = "kb_col3_pq3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col4_pq4 { - nvidia,pins = "kb_col4_pq4"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col5_pq5 { - nvidia,pins = "kb_col5_pq5"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col6_pq6 { - nvidia,pins = "kb_col6_pq6"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col7_pq7 { - nvidia,pins = "kb_col7_pq7"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row0_pr0 { - nvidia,pins = "kb_row0_pr0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row1_pr1 { - nvidia,pins = "kb_row1_pr1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row2_pr2 { - nvidia,pins = "kb_row2_pr2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row3_pr3 { - nvidia,pins = "kb_row3_pr3"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row4_pr4 { - nvidia,pins = "kb_row4_pr4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row5_pr5 { - nvidia,pins = "kb_row5_pr5"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row6_pr6 { - nvidia,pins = "kb_row6_pr6"; - nvidia,function = "displaya_alt"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row7_pr7 { - nvidia,pins = "kb_row7_pr7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row8_ps0 { - nvidia,pins = "kb_row8_ps0"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row9_ps1 { - nvidia,pins = "kb_row9_ps1"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row10_ps2 { - nvidia,pins = "kb_row10_ps2"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row11_ps3 { - nvidia,pins = "kb_row11_ps3"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row12_ps4 { - nvidia,pins = "kb_row12_ps4"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row13_ps5 { - nvidia,pins = "kb_row13_ps5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row14_ps6 { - nvidia,pins = "kb_row14_ps6"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row15_ps7 { - nvidia,pins = "kb_row15_ps7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row16_pt0 { - nvidia,pins = "kb_row16_pt0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row17_pt1 { - nvidia,pins = "kb_row17_pt1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gen2_i2c_scl_pt5 { - nvidia,pins = "gen2_i2c_scl_pt5"; - nvidia,function = "i2c2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gen2_i2c_sda_pt6 { - nvidia,pins = "gen2_i2c_sda_pt6"; - nvidia,function = "i2c2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc4_cmd_pt7 { - nvidia,pins = "sdmmc4_cmd_pt7"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu0 { - nvidia,pins = "pu0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu1 { - nvidia,pins = "pu1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu2 { - nvidia,pins = "pu2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu3 { - nvidia,pins = "pu3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu4 { - nvidia,pins = "pu4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu5 { - nvidia,pins = "pu5"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu6 { - nvidia,pins = "pu6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pv0 { - nvidia,pins = "pv0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pv1 { - nvidia,pins = "pv1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_cd_n_pv2 { - nvidia,pins = "sdmmc3_cd_n_pv2"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_wp_n_pv3 { - nvidia,pins = "sdmmc1_wp_n_pv3"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ddc_scl_pv4 { - nvidia,pins = "ddc_scl_pv4"; - nvidia,function = "i2c4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,rcv-sel = ; - }; - ddc_sda_pv5 { - nvidia,pins = "ddc_sda_pv5"; - nvidia,function = "i2c4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,rcv-sel = ; - }; - gpio_w2_aud_pw2 { - nvidia,pins = "gpio_w2_aud_pw2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_w3_aud_pw3 { - nvidia,pins = "gpio_w3_aud_pw3"; - nvidia,function = "spi6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap_mclk1_pw4 { - nvidia,pins = "dap_mclk1_pw4"; - nvidia,function = "extperiph1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk2_out_pw5 { - nvidia,pins = "clk2_out_pw5"; - nvidia,function = "extperiph2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart3_txd_pw6 { - nvidia,pins = "uart3_txd_pw6"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart3_rxd_pw7 { - nvidia,pins = "uart3_rxd_pw7"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dvfs_pwm_px0 { - nvidia,pins = "dvfs_pwm_px0"; - nvidia,function = "cldvfs"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_x1_aud_px1 { - nvidia,pins = "gpio_x1_aud_px1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dvfs_clk_px2 { - nvidia,pins = "dvfs_clk_px2"; - nvidia,function = "cldvfs"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_x3_aud_px3 { - nvidia,pins = "gpio_x3_aud_px3"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_x4_aud_px4 { - nvidia,pins = "gpio_x4_aud_px4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_x5_aud_px5 { - nvidia,pins = "gpio_x5_aud_px5"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_x6_aud_px6 { - nvidia,pins = "gpio_x6_aud_px6"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_x7_aud_px7 { - nvidia,pins = "gpio_x7_aud_px7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_clk_py0 { - nvidia,pins = "ulpi_clk_py0"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_dir_py1 { - nvidia,pins = "ulpi_dir_py1"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_nxt_py2 { - nvidia,pins = "ulpi_nxt_py2"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_stp_py3 { - nvidia,pins = "ulpi_stp_py3"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_dat3_py4 { - nvidia,pins = "sdmmc1_dat3_py4"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_dat2_py5 { - nvidia,pins = "sdmmc1_dat2_py5"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_dat1_py6 { - nvidia,pins = "sdmmc1_dat1_py6"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_dat0_py7 { - nvidia,pins = "sdmmc1_dat0_py7"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_clk_pz0 { - nvidia,pins = "sdmmc1_clk_pz0"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_cmd_pz1 { - nvidia,pins = "sdmmc1_cmd_pz1"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pwr_i2c_scl_pz6 { - nvidia,pins = "pwr_i2c_scl_pz6"; - nvidia,function = "i2cpwr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pwr_i2c_sda_pz7 { - nvidia,pins = "pwr_i2c_sda_pz7"; - nvidia,function = "i2cpwr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc4_dat0_paa0 { - nvidia,pins = "sdmmc4_dat0_paa0"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_dat1_paa1 { - nvidia,pins = "sdmmc4_dat1_paa1"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_dat2_paa2 { - nvidia,pins = "sdmmc4_dat2_paa2"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_dat3_paa3 { - nvidia,pins = "sdmmc4_dat3_paa3"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_dat4_paa4 { - nvidia,pins = "sdmmc4_dat4_paa4"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_dat5_paa5 { - nvidia,pins = "sdmmc4_dat5_paa5"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_dat6_paa6 { - nvidia,pins = "sdmmc4_dat6_paa6"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_dat7_paa7 { - nvidia,pins = "sdmmc4_dat7_paa7"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pbb0 { - nvidia,pins = "pbb0"; - nvidia,function = "vimclk2_alt"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - cam_i2c_scl_pbb1 { - nvidia,pins = "cam_i2c_scl_pbb1"; - nvidia,function = "i2c3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam_i2c_sda_pbb2 { - nvidia,pins = "cam_i2c_sda_pbb2"; - nvidia,function = "i2c3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pbb3 { - nvidia,pins = "pbb3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pbb4 { - nvidia,pins = "pbb4"; - nvidia,function = "vgp4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pbb5 { - nvidia,pins = "pbb5"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pbb6 { - nvidia,pins = "pbb6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pbb7 { - nvidia,pins = "pbb7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - cam_mclk_pcc0 { - nvidia,pins = "cam_mclk_pcc0"; - nvidia,function = "vi_alt3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pcc1 { - nvidia,pins = "pcc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pcc2 { - nvidia,pins = "pcc2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_clk_pcc4 { - nvidia,pins = "sdmmc4_clk_pcc4"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk2_req_pcc5 { - nvidia,pins = "clk2_req_pcc5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex_l0_rst_n_pdd1 { - nvidia,pins = "pex_l0_rst_n_pdd1"; - nvidia,function = "pe0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex_l0_clkreq_n_pdd2 { - nvidia,pins = "pex_l0_clkreq_n_pdd2"; - nvidia,function = "pe0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex_wake_n_pdd3 { - nvidia,pins = "pex_wake_n_pdd3"; - nvidia,function = "pe"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex_l1_rst_n_pdd5 { - nvidia,pins = "pex_l1_rst_n_pdd5"; - nvidia,function = "pe1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex_l1_clkreq_n_pdd6 { - nvidia,pins = "pex_l1_clkreq_n_pdd6"; - nvidia,function = "pe1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk3_out_pee0 { - nvidia,pins = "clk3_out_pee0"; - nvidia,function = "extperiph3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk3_req_pee1 { - nvidia,pins = "clk3_req_pee1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap_mclk1_req_pee2 { - nvidia,pins = "dap_mclk1_req_pee2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - hdmi_cec_pee3 { - nvidia,pins = "hdmi_cec_pee3"; - nvidia,function = "cec"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc3_clk_lb_out_pee4 { - nvidia,pins = "sdmmc3_clk_lb_out_pee4"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_clk_lb_in_pee5 { - nvidia,pins = "sdmmc3_clk_lb_in_pee5"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dp_hpd_pff0 { - nvidia,pins = "dp_hpd_pff0"; - nvidia,function = "dp"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - usb_vbus_en2_pff1 { - nvidia,pins = "usb_vbus_en2_pff1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pff2 { - nvidia,pins = "pff2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - core_pwr_req { - nvidia,pins = "core_pwr_req"; - nvidia,function = "pwron"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - cpu_pwr_req { - nvidia,pins = "cpu_pwr_req"; - nvidia,function = "cpu"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pwr_int_n { - nvidia,pins = "pwr_int_n"; - nvidia,function = "pmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - reset_out_n { - nvidia,pins = "reset_out_n"; - nvidia,function = "reset_out_n"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk_32k_in { - nvidia,pins = "clk_32k_in"; - nvidia,function = "clk"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - jtag_rtck { - nvidia,pins = "jtag_rtck"; - nvidia,function = "rtck"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dsi_b { - nvidia,pins = "mipi_pad_ctrl_dsi_b"; - nvidia,function = "dsi_b"; - }; - }; - }; - - /* - * First high speed UART, exposed on the expansion connector J3A2 - * Pin 41: BR_UART1_TXD - * Pin 44: BR_UART1_RXD - */ - serial@70006000 { - compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; - status = "okay"; - }; - - /* - * Second high speed UART, exposed on the expansion connector J3A2 - * Pin 65: UART2_RXD - * Pin 68: UART2_TXD - * Pin 71: UART2_CTS_L - * Pin 74: UART2_RTS_L - */ - serial@70006040 { - compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; - status = "okay"; - }; - - /* DB9 serial port */ - serial@70006300 { - status = "okay"; - }; - - /* Expansion GEN1_I2C_*, mini-PCIe I2C, on-board components */ - i2c@7000c000 { - status = "okay"; - clock-frequency = <100000>; - - rt5639: audio-codec@1c { - compatible = "realtek,rt5639"; - reg = <0x1c>; - interrupt-parent = <&gpio>; - interrupts = ; - realtek,ldo1-en-gpios = - <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_HIGH>; - }; - - temperature-sensor@4c { - compatible = "ti,tmp451"; - reg = <0x4c>; - interrupt-parent = <&gpio>; - interrupts = ; - }; - - eeprom@56 { - compatible = "atmel,24c02"; - reg = <0x56>; - pagesize = <8>; - }; - }; - - /* Expansion GEN2_I2C_* */ - i2c@7000c400 { - status = "okay"; - clock-frequency = <100000>; - }; - - /* Expansion CAM_I2C_* */ - i2c@7000c500 { - status = "okay"; - clock-frequency = <100000>; - }; - - /* HDMI DDC */ - hdmi_ddc: i2c@7000c700 { - status = "okay"; - clock-frequency = <100000>; - }; - - /* Expansion PWR_I2C_*, on-board components */ - i2c@7000d000 { - status = "okay"; - clock-frequency = <400000>; - - pmic: pmic@40 { - compatible = "ams,as3722"; - reg = <0x40>; - interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; - - ams,system-power-controller; - - #interrupt-cells = <2>; - interrupt-controller; - - gpio-controller; - #gpio-cells = <2>; - - pinctrl-names = "default"; - pinctrl-0 = <&as3722_default>; - - as3722_default: pinmux { - gpio0 { - pins = "gpio0"; - function = "gpio"; - bias-pull-down; - }; - - gpio1_2_4_7 { - pins = "gpio1", "gpio2", "gpio4", "gpio7"; - function = "gpio"; - bias-pull-up; - }; - - gpio3_5_6 { - pins = "gpio3", "gpio5", "gpio6"; - bias-high-impedance; - }; - }; - - regulators { - vsup-sd2-supply = <&vdd_5v0_sys>; - vsup-sd3-supply = <&vdd_5v0_sys>; - vsup-sd4-supply = <&vdd_5v0_sys>; - vsup-sd5-supply = <&vdd_5v0_sys>; - vin-ldo0-supply = <&vdd_1v35_lp0>; - vin-ldo1-6-supply = <&vdd_3v3_run>; - vin-ldo2-5-7-supply = <&vddio_1v8>; - vin-ldo3-4-supply = <&vdd_3v3_sys>; - vin-ldo9-10-supply = <&vdd_5v0_sys>; - vin-ldo11-supply = <&vdd_3v3_run>; - - vdd_cpu: sd0 { - regulator-name = "+VDD_CPU_AP"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1400000>; - regulator-min-microamp = <3500000>; - regulator-max-microamp = <3500000>; - regulator-always-on; - regulator-boot-on; - ams,ext-control = <2>; - }; - - sd1 { - regulator-name = "+VDD_CORE"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1350000>; - regulator-min-microamp = <2500000>; - regulator-max-microamp = <2500000>; - regulator-always-on; - regulator-boot-on; - ams,ext-control = <1>; - }; - - vdd_1v35_lp0: sd2 { - regulator-name = "+1.35V_LP0(sd2)"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - - sd3 { - regulator-name = "+1.35V_LP0(sd3)"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_1v05_run: sd4 { - regulator-name = "+1.05V_RUN"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - }; - - vddio_1v8: sd5 { - regulator-name = "+1.8V_VDDIO"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - vdd_gpu: sd6 { - regulator-name = "+VDD_GPU_AP"; - regulator-min-microvolt = <650000>; - regulator-max-microvolt = <1200000>; - regulator-min-microamp = <3500000>; - regulator-max-microamp = <3500000>; - regulator-boot-on; - regulator-always-on; - }; - - avdd_1v05_run: ldo0 { - regulator-name = "+1.05V_RUN_AVDD"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - regulator-boot-on; - regulator-always-on; - ams,ext-control = <1>; - }; - - ldo1 { - regulator-name = "+1.8V_RUN_CAM"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo2 { - regulator-name = "+1.2V_GEN_AVDD"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo3 { - regulator-name = "+1.05V_LP0_VDD_RTC"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-boot-on; - regulator-always-on; - ams,enable-tracking; - }; - - ldo4 { - regulator-name = "+2.8V_RUN_CAM"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo5 { - regulator-name = "+1.2V_RUN_CAM_FRONT"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - vddio_sdmmc3: ldo6 { - regulator-name = "+VDDIO_SDMMC3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - ldo7 { - regulator-name = "+1.05V_RUN_CAM_REAR"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - }; - - ldo9 { - regulator-name = "+3.3V_RUN_TOUCH"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo10 { - regulator-name = "+2.8V_RUN_CAM_AF"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo11 { - regulator-name = "+1.8V_RUN_VPP_FUSE"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - }; - }; - }; - - /* Expansion TS_SPI_* */ - spi@7000d400 { - status = "okay"; - }; - - /* Internal SPI */ - spi@7000da00 { - status = "okay"; - spi-max-frequency = <25000000>; - spi-flash@0 { - compatible = "winbond,w25q32dw", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <20000000>; - }; - }; - - pmc@7000e400 { - nvidia,invert-interrupt; - nvidia,suspend-mode = <1>; - nvidia,cpu-pwr-good-time = <500>; - nvidia,cpu-pwr-off-time = <300>; - nvidia,core-pwr-good-time = <641 3845>; - nvidia,core-pwr-off-time = <61036>; - nvidia,core-power-req-active-high; - nvidia,sys-clock-req-active-high; - - i2c-thermtrip { - nvidia,i2c-controller-id = <4>; - nvidia,bus-addr = <0x40>; - nvidia,reg-addr = <0x36>; - nvidia,reg-data = <0x2>; - }; - }; - - /* Serial ATA */ - sata@70020000 { - status = "okay"; - - phys = <&{/padctl@7009f000/pads/sata/lanes/sata-0}>; - phy-names = "sata-0"; - - hvdd-supply = <&vdd_3v3_lp0>; - vddio-supply = <&vdd_1v05_run>; - avdd-supply = <&vdd_1v05_run>; - - target-5v-supply = <&vdd_5v0_sata>; - target-12v-supply = <&vdd_12v0_sata>; - }; - - hda@70030000 { - status = "okay"; - }; - - usb@70090000 { - phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>, /* Micro A/B */ - <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>, /* Mini PCIe */ - <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>, /* USB3 */ - <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>; /* USB3 */ - phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-0"; - - avddio-pex-supply = <&vdd_1v05_run>; - dvddio-pex-supply = <&vdd_1v05_run>; - avdd-usb-supply = <&vdd_3v3_lp0>; - avdd-pll-utmip-supply = <&vddio_1v8>; - avdd-pll-erefe-supply = <&avdd_1v05_run>; - avdd-usb-ss-pll-supply = <&vdd_1v05_run>; - hvdd-usb-ss-supply = <&vdd_3v3_lp0>; - hvdd-usb-ss-pll-e-supply = <&vdd_3v3_lp0>; - - status = "okay"; - }; - - padctl@7009f000 { - status = "okay"; - - avdd-pll-utmip-supply = <&vddio_1v8>; - avdd-pll-erefe-supply = <&avdd_1v05_run>; - avdd-pex-pll-supply = <&vdd_1v05_run>; - hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>; - - pads { - usb2 { - status = "okay"; - - lanes { - usb2-0 { - nvidia,function = "snps"; - status = "okay"; - }; - - usb2-1 { - nvidia,function = "xusb"; - status = "okay"; - }; - - usb2-2 { - nvidia,function = "xusb"; - status = "okay"; - }; - }; - }; - - pcie { - status = "okay"; - - lanes { - pcie-0 { - nvidia,function = "usb3-ss"; - status = "okay"; - }; - - pcie-2 { - nvidia,function = "pcie"; - status = "okay"; - }; - - pcie-4 { - nvidia,function = "pcie"; - status = "okay"; - }; - }; - }; - - sata { - status = "okay"; - - lanes { - sata-0 { - nvidia,function = "sata"; - status = "okay"; - }; - }; - }; - }; - - ports { - /* Micro A/B */ - usb2-0 { - status = "okay"; - mode = "otg"; - }; - - /* Mini PCIe */ - usb2-1 { - status = "okay"; - mode = "host"; - }; - - /* USB3 */ - usb2-2 { - status = "okay"; - mode = "host"; - - vbus-supply = <&vdd_usb3_vbus>; - }; - - usb3-0 { - nvidia,usb2-companion = <2>; - status = "okay"; - }; - }; - }; - - /* SD card */ - sdhci@700b0400 { - status = "okay"; - cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; - power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; - wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_HIGH>; - bus-width = <4>; - vqmmc-supply = <&vddio_sdmmc3>; - }; - - /* eMMC */ - sdhci@700b0600 { - status = "okay"; - bus-width = <8>; - non-removable; - }; - - /* CPU DFLL clock */ - clock@70110000 { - status = "okay"; - vdd-cpu-supply = <&vdd_cpu>; - nvidia,i2c-fs-rate = <400000>; - }; - - ahub@70300000 { - i2s@70301100 { - status = "okay"; - }; - }; - - usb@7d000000 { - compatible = "nvidia,tegra124-udc"; - status = "okay"; - dr_mode = "peripheral"; - }; - - usb-phy@7d000000 { - status = "okay"; - }; - - /* mini-PCIe USB */ - usb@7d004000 { - status = "okay"; - }; - - usb-phy@7d004000 { - status = "okay"; - }; - - /* USB A connector */ - usb@7d008000 { - status = "okay"; - }; - - usb-phy@7d008000 { - status = "okay"; - vbus-supply = <&vdd_usb3_vbus>; - }; - - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - cpus { - cpu@0 { - vdd-cpu-supply = <&vdd_cpu>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - power { - label = "Power"; - gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <10>; - wakeup-source; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - vdd_mux: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "+VDD_MUX"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_5v0_sys: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "+5V_SYS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vdd_mux>; - }; - - vdd_3v3_sys: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "+3.3V_SYS"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vdd_mux>; - }; - - vdd_3v3_run: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "+3.3V_RUN"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_3v3_sys>; - }; - - vdd_3v3_hdmi: regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "+3.3V_AVDD_HDMI_AP_GATED"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vdd_3v3_run>; - }; - - vdd_usb1_vbus: regulator@7 { - compatible = "regulator-fixed"; - reg = <7>; - regulator-name = "+USB0_VBUS_SW"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; - enable-active-high; - gpio-open-drain; - vin-supply = <&vdd_5v0_sys>; - }; - - vdd_usb3_vbus: regulator@8 { - compatible = "regulator-fixed"; - reg = <8>; - regulator-name = "+5V_USB_HS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>; - enable-active-high; - gpio-open-drain; - vin-supply = <&vdd_5v0_sys>; - }; - - vdd_3v3_lp0: regulator@10 { - compatible = "regulator-fixed"; - reg = <10>; - regulator-name = "+3.3V_LP0"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_3v3_sys>; - }; - - vdd_hdmi_pll: regulator@11 { - compatible = "regulator-fixed"; - reg = <11>; - regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>; - vin-supply = <&vdd_1v05_run>; - }; - - vdd_5v0_hdmi: regulator@12 { - compatible = "regulator-fixed"; - reg = <12>; - regulator-name = "+5V_HDMI_CON"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_5v0_sys>; - }; - - /* Molex power connector */ - vdd_5v0_sata: regulator@13 { - compatible = "regulator-fixed"; - reg = <13>; - regulator-name = "+5V_SATA"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(EE, 2) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_5v0_sys>; - }; - - vdd_12v0_sata: regulator@14 { - compatible = "regulator-fixed"; - reg = <14>; - regulator-name = "+12V_SATA"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - gpio = <&gpio TEGRA_GPIO(EE, 2) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_mux>; - }; - }; - - sound { - compatible = "nvidia,tegra-audio-rt5640-jetson-tk1", - "nvidia,tegra-audio-rt5640"; - nvidia,model = "NVIDIA Tegra Jetson TK1"; - - nvidia,audio-routing = - "Headphones", "HPOR", - "Headphones", "HPOL", - "Mic Jack", "MICBIAS1", - "IN2P", "Mic Jack"; - - nvidia,i2s-controller = <&tegra_i2s1>; - nvidia,audio-codec = <&rt5639>; - - nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_LOW>; - - clocks = <&tegra_car TEGRA124_CLK_PLL_A>, - <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA124_CLK_EXTERN1>; - clock-names = "pll_a", "pll_a_out0", "mclk"; - }; - - thermal-zones { - cpu { - trips { - cpu-shutdown-trip { - temperature = <101000>; - hysteresis = <0>; - type = "critical"; - }; - }; - }; - - mem { - trips { - mem-shutdown-trip { - temperature = <101000>; - hysteresis = <0>; - type = "critical"; - }; - }; - }; - - gpu { - trips { - gpu-shutdown-trip { - temperature = <101000>; - hysteresis = <0>; - type = "critical"; - }; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/tegra124-nyan-big-emc.dtsi b/sys/gnu/dts/arm/tegra124-nyan-big-emc.dtsi deleted file mode 100644 index c91647d13a5..00000000000 --- a/sys/gnu/dts/arm/tegra124-nyan-big-emc.dtsi +++ /dev/null @@ -1,6651 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/ { - apbmisc@70000800 { - nvidia,long-ram-code; - }; - - clock@60006000 { - emc-timings-1 { - nvidia,ram-code = <1>; - - timing-12750000 { - clock-frequency = <12750000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - timing-20400000 { - clock-frequency = <20400000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - timing-40800000 { - clock-frequency = <40800000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - timing-68000000 { - clock-frequency = <68000000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - timing-102000000 { - clock-frequency = <102000000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - timing-204000000 { - clock-frequency = <204000000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - timing-300000000 { - clock-frequency = <300000000>; - nvidia,parent-clock-frequency = <600000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_C>; - clock-names = "emc-parent"; - }; - timing-396000000 { - clock-frequency = <396000000>; - nvidia,parent-clock-frequency = <792000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_M>; - clock-names = "emc-parent"; - }; - timing-528000000 { - clock-frequency = <528000000>; - nvidia,parent-clock-frequency = <528000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; - clock-names = "emc-parent"; - }; - timing-600000000 { - clock-frequency = <600000000>; - nvidia,parent-clock-frequency = <600000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_C_UD>; - clock-names = "emc-parent"; - }; - timing-792000000 { - clock-frequency = <792000000>; - nvidia,parent-clock-frequency = <792000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; - clock-names = "emc-parent"; - }; - }; - - emc-timings-4 { - nvidia,ram-code = <4>; - - timing-12750000 { - clock-frequency = <12750000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - timing-20400000 { - clock-frequency = <20400000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - timing-40800000 { - clock-frequency = <40800000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - timing-68000000 { - clock-frequency = <68000000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - timing-102000000 { - clock-frequency = <102000000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - timing-204000000 { - clock-frequency = <204000000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - timing-300000000 { - clock-frequency = <300000000>; - nvidia,parent-clock-frequency = <600000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_C>; - clock-names = "emc-parent"; - }; - timing-396000000 { - clock-frequency = <396000000>; - nvidia,parent-clock-frequency = <792000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_M>; - clock-names = "emc-parent"; - }; - timing-528000000 { - clock-frequency = <528000000>; - nvidia,parent-clock-frequency = <528000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; - clock-names = "emc-parent"; - }; - timing-600000000 { - clock-frequency = <600000000>; - nvidia,parent-clock-frequency = <600000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_C_UD>; - clock-names = "emc-parent"; - }; - timing-792000000 { - clock-frequency = <792000000>; - nvidia,parent-clock-frequency = <792000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; - clock-names = "emc-parent"; - }; - }; - - emc-timings-6 { - nvidia,ram-code = <6>; - - timing-12750000 { - clock-frequency = <12750000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - timing-20400000 { - clock-frequency = <20400000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - timing-40800000 { - clock-frequency = <40800000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - timing-68000000 { - clock-frequency = <68000000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - timing-102000000 { - clock-frequency = <102000000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - timing-204000000 { - clock-frequency = <204000000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - timing-300000000 { - clock-frequency = <300000000>; - nvidia,parent-clock-frequency = <600000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_C>; - clock-names = "emc-parent"; - }; - timing-396000000 { - clock-frequency = <396000000>; - nvidia,parent-clock-frequency = <792000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_M>; - clock-names = "emc-parent"; - }; - timing-528000000 { - clock-frequency = <528000000>; - nvidia,parent-clock-frequency = <528000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; - clock-names = "emc-parent"; - }; - timing-600000000 { - clock-frequency = <600000000>; - nvidia,parent-clock-frequency = <600000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_C_UD>; - clock-names = "emc-parent"; - }; - timing-792000000 { - clock-frequency = <792000000>; - nvidia,parent-clock-frequency = <792000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; - clock-names = "emc-parent"; - }; - }; - }; - - external-memory-controller@7001b000 { - emc-timings-1 { - nvidia,ram-code = <1>; - - timing-12750000 { - clock-frequency = <12750000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000c000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000000 /* EMC_RC */ - 0x00000003 /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000000 /* EMC_RAS */ - 0x00000000 /* EMC_RP */ - 0x00000004 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000003 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000000 /* EMC_RD_RCD */ - 0x00000000 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000003 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000006 /* EMC_WDV */ - 0x00000006 /* EMC_WDV_MASK */ - 0x00000006 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000005 /* EMC_EINPUT */ - 0x00000005 /* EMC_EINPUT_DURATION */ - 0x00010000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000004 /* EMC_QRST */ - 0x0000000c /* EMC_QSAFE */ - 0x0000000d /* EMC_RDV */ - 0x0000000f /* EMC_RDV_MASK */ - 0x00000060 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000018 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000007 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x00000005 /* EMC_TXSR */ - 0x00000005 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000000 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000005 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x00000064 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x106aa298 /* EMC_FBIO_CFG5 */ - 0x002c00a0 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00064000 /* EMC_DLL_XFORM_DQS0 */ - 0x00064000 /* EMC_DLL_XFORM_DQS1 */ - 0x00064000 /* EMC_DLL_XFORM_DQS2 */ - 0x00064000 /* EMC_DLL_XFORM_DQS3 */ - 0x00064000 /* EMC_DLL_XFORM_DQS4 */ - 0x00064000 /* EMC_DLL_XFORM_DQS5 */ - 0x00064000 /* EMC_DLL_XFORM_DQS6 */ - 0x00064000 /* EMC_DLL_XFORM_DQS7 */ - 0x00064000 /* EMC_DLL_XFORM_DQS8 */ - 0x00064000 /* EMC_DLL_XFORM_DQS9 */ - 0x00064000 /* EMC_DLL_XFORM_DQS10 */ - 0x00064000 /* EMC_DLL_XFORM_DQS11 */ - 0x00064000 /* EMC_DLL_XFORM_DQS12 */ - 0x00064000 /* EMC_DLL_XFORM_DQS13 */ - 0x00064000 /* EMC_DLL_XFORM_DQS14 */ - 0x00064000 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ - 0x10000280 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc081 /* EMC_XM2CLKPADCTRL */ - 0x00000303 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451400 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0000003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000007 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000042 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x0000f2f3 /* EMC_CFG_PIPE */ - 0x800001c5 /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000a /* EMC_QPOP */ - >; - }; - - timing-20400000 { - clock-frequency = <20400000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000c000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000000 /* EMC_RC */ - 0x00000005 /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000000 /* EMC_RAS */ - 0x00000000 /* EMC_RP */ - 0x00000004 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000003 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000000 /* EMC_RD_RCD */ - 0x00000000 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000003 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000006 /* EMC_WDV */ - 0x00000006 /* EMC_WDV_MASK */ - 0x00000006 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000005 /* EMC_EINPUT */ - 0x00000005 /* EMC_EINPUT_DURATION */ - 0x00010000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000004 /* EMC_QRST */ - 0x0000000c /* EMC_QSAFE */ - 0x0000000d /* EMC_RDV */ - 0x0000000f /* EMC_RDV_MASK */ - 0x0000009a /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000026 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000007 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x00000006 /* EMC_TXSR */ - 0x00000006 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000000 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000005 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x000000a0 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x106aa298 /* EMC_FBIO_CFG5 */ - 0x002c00a0 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00064000 /* EMC_DLL_XFORM_DQS0 */ - 0x00064000 /* EMC_DLL_XFORM_DQS1 */ - 0x00064000 /* EMC_DLL_XFORM_DQS2 */ - 0x00064000 /* EMC_DLL_XFORM_DQS3 */ - 0x00064000 /* EMC_DLL_XFORM_DQS4 */ - 0x00064000 /* EMC_DLL_XFORM_DQS5 */ - 0x00064000 /* EMC_DLL_XFORM_DQS6 */ - 0x00064000 /* EMC_DLL_XFORM_DQS7 */ - 0x00064000 /* EMC_DLL_XFORM_DQS8 */ - 0x00064000 /* EMC_DLL_XFORM_DQS9 */ - 0x00064000 /* EMC_DLL_XFORM_DQS10 */ - 0x00064000 /* EMC_DLL_XFORM_DQS11 */ - 0x00064000 /* EMC_DLL_XFORM_DQS12 */ - 0x00064000 /* EMC_DLL_XFORM_DQS13 */ - 0x00064000 /* EMC_DLL_XFORM_DQS14 */ - 0x00064000 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ - 0x10000280 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc081 /* EMC_XM2CLKPADCTRL */ - 0x00000303 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451400 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0000003f /* EMC_DSR_VTTGEN_DRV */ - 0x0000000b /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000042 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x0000f2f3 /* EMC_CFG_PIPE */ - 0x8000023a /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000a /* EMC_QPOP */ - >; - }; - - timing-40800000 { - clock-frequency = <40800000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000c000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000001 /* EMC_RC */ - 0x0000000a /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000001 /* EMC_RAS */ - 0x00000000 /* EMC_RP */ - 0x00000004 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000003 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000000 /* EMC_RD_RCD */ - 0x00000000 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000003 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000006 /* EMC_WDV */ - 0x00000006 /* EMC_WDV_MASK */ - 0x00000006 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000005 /* EMC_EINPUT */ - 0x00000005 /* EMC_EINPUT_DURATION */ - 0x00010000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000004 /* EMC_QRST */ - 0x0000000c /* EMC_QSAFE */ - 0x0000000d /* EMC_RDV */ - 0x0000000f /* EMC_RDV_MASK */ - 0x00000134 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x0000004d /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000008 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x0000000c /* EMC_TXSR */ - 0x0000000c /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000000 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000005 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x0000013f /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x106aa298 /* EMC_FBIO_CFG5 */ - 0x002c00a0 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00064000 /* EMC_DLL_XFORM_DQS0 */ - 0x00064000 /* EMC_DLL_XFORM_DQS1 */ - 0x00064000 /* EMC_DLL_XFORM_DQS2 */ - 0x00064000 /* EMC_DLL_XFORM_DQS3 */ - 0x00064000 /* EMC_DLL_XFORM_DQS4 */ - 0x00064000 /* EMC_DLL_XFORM_DQS5 */ - 0x00064000 /* EMC_DLL_XFORM_DQS6 */ - 0x00064000 /* EMC_DLL_XFORM_DQS7 */ - 0x00064000 /* EMC_DLL_XFORM_DQS8 */ - 0x00064000 /* EMC_DLL_XFORM_DQS9 */ - 0x00064000 /* EMC_DLL_XFORM_DQS10 */ - 0x00064000 /* EMC_DLL_XFORM_DQS11 */ - 0x00064000 /* EMC_DLL_XFORM_DQS12 */ - 0x00064000 /* EMC_DLL_XFORM_DQS13 */ - 0x00064000 /* EMC_DLL_XFORM_DQS14 */ - 0x00064000 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ - 0x10000280 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc081 /* EMC_XM2CLKPADCTRL */ - 0x00000303 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451400 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0000003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000015 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000042 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x0000f2f3 /* EMC_CFG_PIPE */ - 0x80000370 /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000a /* EMC_QPOP */ - >; - }; - - timing-68000000 { - clock-frequency = <68000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000c000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000003 /* EMC_RC */ - 0x00000011 /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000002 /* EMC_RAS */ - 0x00000000 /* EMC_RP */ - 0x00000004 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000003 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000000 /* EMC_RD_RCD */ - 0x00000000 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000003 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000006 /* EMC_WDV */ - 0x00000006 /* EMC_WDV_MASK */ - 0x00000006 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000005 /* EMC_EINPUT */ - 0x00000005 /* EMC_EINPUT_DURATION */ - 0x00010000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000004 /* EMC_QRST */ - 0x0000000c /* EMC_QSAFE */ - 0x0000000d /* EMC_RDV */ - 0x0000000f /* EMC_RDV_MASK */ - 0x00000202 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000080 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x0000000f /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x00000013 /* EMC_TXSR */ - 0x00000013 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000001 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000005 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x00000213 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x106aa298 /* EMC_FBIO_CFG5 */ - 0x002c00a0 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00064000 /* EMC_DLL_XFORM_DQS0 */ - 0x00064000 /* EMC_DLL_XFORM_DQS1 */ - 0x00064000 /* EMC_DLL_XFORM_DQS2 */ - 0x00064000 /* EMC_DLL_XFORM_DQS3 */ - 0x00064000 /* EMC_DLL_XFORM_DQS4 */ - 0x00064000 /* EMC_DLL_XFORM_DQS5 */ - 0x00064000 /* EMC_DLL_XFORM_DQS6 */ - 0x00064000 /* EMC_DLL_XFORM_DQS7 */ - 0x00064000 /* EMC_DLL_XFORM_DQS8 */ - 0x00064000 /* EMC_DLL_XFORM_DQS9 */ - 0x00064000 /* EMC_DLL_XFORM_DQS10 */ - 0x00064000 /* EMC_DLL_XFORM_DQS11 */ - 0x00064000 /* EMC_DLL_XFORM_DQS12 */ - 0x00064000 /* EMC_DLL_XFORM_DQS13 */ - 0x00064000 /* EMC_DLL_XFORM_DQS14 */ - 0x00064000 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ - 0x10000280 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc081 /* EMC_XM2CLKPADCTRL */ - 0x00000303 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451400 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0000003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000022 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000042 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x0000f2f3 /* EMC_CFG_PIPE */ - 0x8000050e /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000a /* EMC_QPOP */ - >; - }; - - timing-102000000 { - clock-frequency = <102000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000c000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000004 /* EMC_RC */ - 0x0000001a /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000003 /* EMC_RAS */ - 0x00000001 /* EMC_RP */ - 0x00000004 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000003 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000001 /* EMC_RD_RCD */ - 0x00000001 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000003 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000006 /* EMC_WDV */ - 0x00000006 /* EMC_WDV_MASK */ - 0x00000006 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000005 /* EMC_EINPUT */ - 0x00000005 /* EMC_EINPUT_DURATION */ - 0x00010000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000004 /* EMC_QRST */ - 0x0000000c /* EMC_QSAFE */ - 0x0000000d /* EMC_RDV */ - 0x0000000f /* EMC_RDV_MASK */ - 0x00000304 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x000000c1 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000018 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x0000001c /* EMC_TXSR */ - 0x0000001c /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000003 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000005 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x0000031c /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x106aa298 /* EMC_FBIO_CFG5 */ - 0x002c00a0 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00064000 /* EMC_DLL_XFORM_DQS0 */ - 0x00064000 /* EMC_DLL_XFORM_DQS1 */ - 0x00064000 /* EMC_DLL_XFORM_DQS2 */ - 0x00064000 /* EMC_DLL_XFORM_DQS3 */ - 0x00064000 /* EMC_DLL_XFORM_DQS4 */ - 0x00064000 /* EMC_DLL_XFORM_DQS5 */ - 0x00064000 /* EMC_DLL_XFORM_DQS6 */ - 0x00064000 /* EMC_DLL_XFORM_DQS7 */ - 0x00064000 /* EMC_DLL_XFORM_DQS8 */ - 0x00064000 /* EMC_DLL_XFORM_DQS9 */ - 0x00064000 /* EMC_DLL_XFORM_DQS10 */ - 0x00064000 /* EMC_DLL_XFORM_DQS11 */ - 0x00064000 /* EMC_DLL_XFORM_DQS12 */ - 0x00064000 /* EMC_DLL_XFORM_DQS13 */ - 0x00064000 /* EMC_DLL_XFORM_DQS14 */ - 0x00064000 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ - 0x10000280 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc081 /* EMC_XM2CLKPADCTRL */ - 0x00000303 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451400 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0000003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000033 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000042 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x0000f2f3 /* EMC_CFG_PIPE */ - 0x80000713 /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000a /* EMC_QPOP */ - >; - }; - - timing-204000000 { - clock-frequency = <204000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x0000088d>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000c000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040008>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x00000009 /* EMC_RC */ - 0x00000035 /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000007 /* EMC_RAS */ - 0x00000002 /* EMC_RP */ - 0x00000005 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000003 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000002 /* EMC_RD_RCD */ - 0x00000002 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000003 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000005 /* EMC_WDV */ - 0x00000005 /* EMC_WDV_MASK */ - 0x00000006 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000004 /* EMC_EINPUT */ - 0x00000006 /* EMC_EINPUT_DURATION */ - 0x00010000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000003 /* EMC_QRST */ - 0x0000000d /* EMC_QSAFE */ - 0x0000000f /* EMC_RDV */ - 0x00000011 /* EMC_RDV_MASK */ - 0x00000607 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000181 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000032 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x00000038 /* EMC_TXSR */ - 0x00000038 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000007 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000005 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x00000638 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x106aa298 /* EMC_FBIO_CFG5 */ - 0x002c00a0 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00064000 /* EMC_DLL_XFORM_DQS0 */ - 0x00064000 /* EMC_DLL_XFORM_DQS1 */ - 0x00064000 /* EMC_DLL_XFORM_DQS2 */ - 0x00064000 /* EMC_DLL_XFORM_DQS3 */ - 0x00064000 /* EMC_DLL_XFORM_DQS4 */ - 0x00064000 /* EMC_DLL_XFORM_DQS5 */ - 0x00064000 /* EMC_DLL_XFORM_DQS6 */ - 0x00064000 /* EMC_DLL_XFORM_DQS7 */ - 0x00064000 /* EMC_DLL_XFORM_DQS8 */ - 0x00064000 /* EMC_DLL_XFORM_DQS9 */ - 0x00064000 /* EMC_DLL_XFORM_DQS10 */ - 0x00064000 /* EMC_DLL_XFORM_DQS11 */ - 0x00064000 /* EMC_DLL_XFORM_DQS12 */ - 0x00064000 /* EMC_DLL_XFORM_DQS13 */ - 0x00064000 /* EMC_DLL_XFORM_DQS14 */ - 0x00064000 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ - 0x00090000 /* EMC_DLL_XFORM_DQ0 */ - 0x00090000 /* EMC_DLL_XFORM_DQ1 */ - 0x00094000 /* EMC_DLL_XFORM_DQ2 */ - 0x00094000 /* EMC_DLL_XFORM_DQ3 */ - 0x00009400 /* EMC_DLL_XFORM_DQ4 */ - 0x00009000 /* EMC_DLL_XFORM_DQ5 */ - 0x00009000 /* EMC_DLL_XFORM_DQ6 */ - 0x00009000 /* EMC_DLL_XFORM_DQ7 */ - 0x10000280 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc081 /* EMC_XM2CLKPADCTRL */ - 0x00000303 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451400 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0000003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000066 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x0000d2b3 /* EMC_CFG_PIPE */ - 0x80000d22 /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000a /* EMC_QPOP */ - >; - }; - - timing-300000000 { - clock-frequency = <300000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73340000>; - nvidia,emc-cfg-2 = <0x000008d5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200000>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000321>; - nvidia,emc-mrs-wait-cnt = <0x0174000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x01231339>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x0000000d /* EMC_RC */ - 0x0000004c /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000009 /* EMC_RAS */ - 0x00000003 /* EMC_RP */ - 0x00000004 /* EMC_R2W */ - 0x00000008 /* EMC_W2R */ - 0x00000002 /* EMC_R2P */ - 0x00000009 /* EMC_W2P */ - 0x00000003 /* EMC_RD_RCD */ - 0x00000003 /* EMC_WR_RCD */ - 0x00000002 /* EMC_RRD */ - 0x00000002 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000003 /* EMC_WDV */ - 0x00000003 /* EMC_WDV_MASK */ - 0x00000005 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000002 /* EMC_EINPUT */ - 0x00000007 /* EMC_EINPUT_DURATION */ - 0x00020000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000001 /* EMC_QRST */ - 0x0000000e /* EMC_QSAFE */ - 0x00000010 /* EMC_RDV */ - 0x00000012 /* EMC_RDV_MASK */ - 0x000008e4 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000239 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000001 /* EMC_PDEX2WR */ - 0x00000008 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x0000004a /* EMC_AR2PDEN */ - 0x0000000e /* EMC_RW2PDEN */ - 0x00000051 /* EMC_TXSR */ - 0x00000200 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000009 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000005 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x00000924 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x104ab098 /* EMC_FBIO_CFG5 */ - 0x002c00a0 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00030000 /* EMC_DLL_XFORM_DQS0 */ - 0x00030000 /* EMC_DLL_XFORM_DQS1 */ - 0x00030000 /* EMC_DLL_XFORM_DQS2 */ - 0x00030000 /* EMC_DLL_XFORM_DQS3 */ - 0x00030000 /* EMC_DLL_XFORM_DQS4 */ - 0x00030000 /* EMC_DLL_XFORM_DQS5 */ - 0x00030000 /* EMC_DLL_XFORM_DQS6 */ - 0x00030000 /* EMC_DLL_XFORM_DQS7 */ - 0x00030000 /* EMC_DLL_XFORM_DQS8 */ - 0x00030000 /* EMC_DLL_XFORM_DQS9 */ - 0x00030000 /* EMC_DLL_XFORM_DQS10 */ - 0x00030000 /* EMC_DLL_XFORM_DQS11 */ - 0x00030000 /* EMC_DLL_XFORM_DQS12 */ - 0x00030000 /* EMC_DLL_XFORM_DQS13 */ - 0x00030000 /* EMC_DLL_XFORM_DQS14 */ - 0x00030000 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00098000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00098000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00098000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00098000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ - 0x00060000 /* EMC_DLL_XFORM_DQ0 */ - 0x00060000 /* EMC_DLL_XFORM_DQ1 */ - 0x00060000 /* EMC_DLL_XFORM_DQ2 */ - 0x00060000 /* EMC_DLL_XFORM_DQ3 */ - 0x00006000 /* EMC_DLL_XFORM_DQ4 */ - 0x00006000 /* EMC_DLL_XFORM_DQ5 */ - 0x00006000 /* EMC_DLL_XFORM_DQ6 */ - 0x00006000 /* EMC_DLL_XFORM_DQ7 */ - 0x10000280 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc081 /* EMC_XM2CLKPADCTRL */ - 0x00000101 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451420 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0000003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000096 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x0174000c /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x000052a3 /* EMC_CFG_PIPE */ - 0x800012d7 /* EMC_DYN_SELF_REF_CONTROL */ - 0x00000009 /* EMC_QPOP */ - >; - }; - - timing-396000000 { - clock-frequency = <396000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73340000>; - nvidia,emc-cfg-2 = <0x00000895>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200000>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000521>; - nvidia,emc-mrs-wait-cnt = <0x015b000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040008>; - nvidia,emc-xm2dqspadctrl2 = <0x01231339>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x00000012 /* EMC_RC */ - 0x00000065 /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x0000000c /* EMC_RAS */ - 0x00000004 /* EMC_RP */ - 0x00000005 /* EMC_R2W */ - 0x00000008 /* EMC_W2R */ - 0x00000002 /* EMC_R2P */ - 0x0000000a /* EMC_W2P */ - 0x00000004 /* EMC_RD_RCD */ - 0x00000004 /* EMC_WR_RCD */ - 0x00000002 /* EMC_RRD */ - 0x00000002 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000003 /* EMC_WDV */ - 0x00000003 /* EMC_WDV_MASK */ - 0x00000005 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000001 /* EMC_EINPUT */ - 0x00000008 /* EMC_EINPUT_DURATION */ - 0x00020000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000000 /* EMC_QRST */ - 0x0000000f /* EMC_QSAFE */ - 0x00000010 /* EMC_RDV */ - 0x00000012 /* EMC_RDV_MASK */ - 0x00000bd1 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x000002f4 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000001 /* EMC_PDEX2WR */ - 0x00000008 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000063 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x0000006b /* EMC_TXSR */ - 0x00000200 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x0000000d /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000005 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x00000c11 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x104ab098 /* EMC_FBIO_CFG5 */ - 0x002c00a0 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00030000 /* EMC_DLL_XFORM_DQS0 */ - 0x00030000 /* EMC_DLL_XFORM_DQS1 */ - 0x00030000 /* EMC_DLL_XFORM_DQS2 */ - 0x00030000 /* EMC_DLL_XFORM_DQS3 */ - 0x00030000 /* EMC_DLL_XFORM_DQS4 */ - 0x00030000 /* EMC_DLL_XFORM_DQS5 */ - 0x00030000 /* EMC_DLL_XFORM_DQS6 */ - 0x00030000 /* EMC_DLL_XFORM_DQS7 */ - 0x00030000 /* EMC_DLL_XFORM_DQS8 */ - 0x00030000 /* EMC_DLL_XFORM_DQS9 */ - 0x00030000 /* EMC_DLL_XFORM_DQS10 */ - 0x00030000 /* EMC_DLL_XFORM_DQS11 */ - 0x00030000 /* EMC_DLL_XFORM_DQS12 */ - 0x00030000 /* EMC_DLL_XFORM_DQS13 */ - 0x00030000 /* EMC_DLL_XFORM_DQS14 */ - 0x00030000 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00070000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00070000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00070000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00070000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ - 0x00048000 /* EMC_DLL_XFORM_DQ0 */ - 0x00048000 /* EMC_DLL_XFORM_DQ1 */ - 0x00048000 /* EMC_DLL_XFORM_DQ2 */ - 0x00048000 /* EMC_DLL_XFORM_DQ3 */ - 0x00004800 /* EMC_DLL_XFORM_DQ4 */ - 0x00004800 /* EMC_DLL_XFORM_DQ5 */ - 0x00004800 /* EMC_DLL_XFORM_DQ6 */ - 0x00004800 /* EMC_DLL_XFORM_DQ7 */ - 0x10000280 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc081 /* EMC_XM2CLKPADCTRL */ - 0x00000101 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451420 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0000003f /* EMC_DSR_VTTGEN_DRV */ - 0x000000c6 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x015b000c /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x000052a3 /* EMC_CFG_PIPE */ - 0x8000188b /* EMC_DYN_SELF_REF_CONTROL */ - 0x00000009 /* EMC_QPOP */ - >; - }; - - timing-528000000 { - clock-frequency = <528000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73300000>; - nvidia,emc-cfg-2 = <0x0000089d>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000941>; - nvidia,emc-mrs-wait-cnt = <0x013a000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040008>; - nvidia,emc-xm2dqspadctrl2 = <0x0123133d>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x00000018 /* EMC_RC */ - 0x00000088 /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000011 /* EMC_RAS */ - 0x00000006 /* EMC_RP */ - 0x00000006 /* EMC_R2W */ - 0x00000009 /* EMC_W2R */ - 0x00000002 /* EMC_R2P */ - 0x0000000d /* EMC_W2P */ - 0x00000006 /* EMC_RD_RCD */ - 0x00000006 /* EMC_WR_RCD */ - 0x00000002 /* EMC_RRD */ - 0x00000002 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000003 /* EMC_WDV */ - 0x00000003 /* EMC_WDV_MASK */ - 0x00000007 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000002 /* EMC_EINPUT */ - 0x00000009 /* EMC_EINPUT_DURATION */ - 0x00040000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000001 /* EMC_QRST */ - 0x00000010 /* EMC_QSAFE */ - 0x00000013 /* EMC_RDV */ - 0x00000015 /* EMC_RDV_MASK */ - 0x00000fd6 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x000003f5 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x0000000b /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000084 /* EMC_AR2PDEN */ - 0x00000012 /* EMC_RW2PDEN */ - 0x0000008f /* EMC_TXSR */ - 0x00000200 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000013 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000006 /* EMC_TCLKSTABLE */ - 0x00000006 /* EMC_TCLKSTOP */ - 0x00001017 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x104ab098 /* EMC_FBIO_CFG5 */ - 0xe01200b1 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x0000000a /* EMC_DLL_XFORM_DQS0 */ - 0x0000000a /* EMC_DLL_XFORM_DQS1 */ - 0x0000000a /* EMC_DLL_XFORM_DQS2 */ - 0x0000000a /* EMC_DLL_XFORM_DQS3 */ - 0x0000000a /* EMC_DLL_XFORM_DQS4 */ - 0x0000000a /* EMC_DLL_XFORM_DQS5 */ - 0x0000000a /* EMC_DLL_XFORM_DQS6 */ - 0x0000000a /* EMC_DLL_XFORM_DQS7 */ - 0x0000000a /* EMC_DLL_XFORM_DQS8 */ - 0x0000000a /* EMC_DLL_XFORM_DQS9 */ - 0x0000000a /* EMC_DLL_XFORM_DQS10 */ - 0x0000000a /* EMC_DLL_XFORM_DQS11 */ - 0x0000000a /* EMC_DLL_XFORM_DQS12 */ - 0x0000000a /* EMC_DLL_XFORM_DQS13 */ - 0x0000000a /* EMC_DLL_XFORM_DQS14 */ - 0x0000000a /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00050000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00050000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00050000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00050000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000002 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000002 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000003 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000004 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000001 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000004 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000003 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000002 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000002 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000003 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000004 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000001 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000004 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000003 /* EMC_DLI_TRIM_TXDQS15 */ - 0x0000000e /* EMC_DLL_XFORM_DQ0 */ - 0x0000000e /* EMC_DLL_XFORM_DQ1 */ - 0x0000000e /* EMC_DLL_XFORM_DQ2 */ - 0x0000000e /* EMC_DLL_XFORM_DQ3 */ - 0x0000000e /* EMC_DLL_XFORM_DQ4 */ - 0x0000000e /* EMC_DLL_XFORM_DQ5 */ - 0x0000000e /* EMC_DLL_XFORM_DQ6 */ - 0x0000000e /* EMC_DLL_XFORM_DQ7 */ - 0x100002a0 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc085 /* EMC_XM2CLKPADCTRL */ - 0x00000101 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451420 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0606003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000000 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x013a000c /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x000042a0 /* EMC_CFG_PIPE */ - 0x80002062 /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000b /* EMC_QPOP */ - >; - }; - - timing-600000000 { - clock-frequency = <600000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73300000>; - nvidia,emc-cfg-2 = <0x0000089d>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200010>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000b61>; - nvidia,emc-mrs-wait-cnt = <0x0128000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040008>; - nvidia,emc-xm2dqspadctrl2 = <0x0121113d>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x0000001c /* EMC_RC */ - 0x0000009a /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000013 /* EMC_RAS */ - 0x00000007 /* EMC_RP */ - 0x00000007 /* EMC_R2W */ - 0x0000000b /* EMC_W2R */ - 0x00000003 /* EMC_R2P */ - 0x00000010 /* EMC_W2P */ - 0x00000007 /* EMC_RD_RCD */ - 0x00000007 /* EMC_WR_RCD */ - 0x00000002 /* EMC_RRD */ - 0x00000002 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000005 /* EMC_WDV */ - 0x00000005 /* EMC_WDV_MASK */ - 0x0000000a /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000003 /* EMC_EINPUT */ - 0x0000000b /* EMC_EINPUT_DURATION */ - 0x00070000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000002 /* EMC_QRST */ - 0x00000012 /* EMC_QSAFE */ - 0x00000016 /* EMC_RDV */ - 0x00000018 /* EMC_RDV_MASK */ - 0x00001208 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000482 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x0000000d /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000096 /* EMC_AR2PDEN */ - 0x00000015 /* EMC_RW2PDEN */ - 0x000000a2 /* EMC_TXSR */ - 0x00000200 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000015 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000006 /* EMC_TCLKSTABLE */ - 0x00000006 /* EMC_TCLKSTOP */ - 0x00001249 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x104ab098 /* EMC_FBIO_CFG5 */ - 0xe00e00b1 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x0000000a /* EMC_DLL_XFORM_DQS0 */ - 0x0000000a /* EMC_DLL_XFORM_DQS1 */ - 0x0000000a /* EMC_DLL_XFORM_DQS2 */ - 0x0000000a /* EMC_DLL_XFORM_DQS3 */ - 0x0000000a /* EMC_DLL_XFORM_DQS4 */ - 0x0000000a /* EMC_DLL_XFORM_DQS5 */ - 0x0000000a /* EMC_DLL_XFORM_DQS6 */ - 0x0000000a /* EMC_DLL_XFORM_DQS7 */ - 0x0000000a /* EMC_DLL_XFORM_DQS8 */ - 0x0000000a /* EMC_DLL_XFORM_DQS9 */ - 0x0000000a /* EMC_DLL_XFORM_DQS10 */ - 0x0000000a /* EMC_DLL_XFORM_DQS11 */ - 0x0000000a /* EMC_DLL_XFORM_DQS12 */ - 0x0000000a /* EMC_DLL_XFORM_DQS13 */ - 0x0000000a /* EMC_DLL_XFORM_DQS14 */ - 0x0000000a /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00048000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00048000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00048000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00048000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000004 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000004 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000002 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000005 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000006 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000003 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000006 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000005 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000004 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000004 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000002 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000005 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000006 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000003 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000006 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000005 /* EMC_DLI_TRIM_TXDQS15 */ - 0x0000000e /* EMC_DLL_XFORM_DQ0 */ - 0x0000000e /* EMC_DLL_XFORM_DQ1 */ - 0x0000000e /* EMC_DLL_XFORM_DQ2 */ - 0x0000000e /* EMC_DLL_XFORM_DQ3 */ - 0x0000000e /* EMC_DLL_XFORM_DQ4 */ - 0x0000000e /* EMC_DLL_XFORM_DQ5 */ - 0x0000000e /* EMC_DLL_XFORM_DQ6 */ - 0x0000000e /* EMC_DLL_XFORM_DQ7 */ - 0x100002a0 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc085 /* EMC_XM2CLKPADCTRL */ - 0x00000101 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451420 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0606003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000000 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x0128000c /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x000040a0 /* EMC_CFG_PIPE */ - 0x800024aa /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000e /* EMC_QPOP */ - >; - }; - - timing-792000000 { - clock-frequency = <792000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73300000>; - nvidia,emc-cfg-2 = <0x0080089d>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200418>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000d71>; - nvidia,emc-mrs-wait-cnt = <0x00f8000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040000>; - nvidia,emc-xm2dqspadctrl2 = <0x0120113d>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x00000025 /* EMC_RC */ - 0x000000cc /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x0000001a /* EMC_RAS */ - 0x00000009 /* EMC_RP */ - 0x00000008 /* EMC_R2W */ - 0x0000000d /* EMC_W2R */ - 0x00000004 /* EMC_R2P */ - 0x00000013 /* EMC_W2P */ - 0x00000009 /* EMC_RD_RCD */ - 0x00000009 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000002 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000006 /* EMC_WDV */ - 0x00000006 /* EMC_WDV_MASK */ - 0x0000000b /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000002 /* EMC_EINPUT */ - 0x0000000d /* EMC_EINPUT_DURATION */ - 0x00080000 /* EMC_PUTERM_EXTRA */ - 0x00000004 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000001 /* EMC_QRST */ - 0x00000014 /* EMC_QSAFE */ - 0x00000018 /* EMC_RDV */ - 0x0000001a /* EMC_RDV_MASK */ - 0x000017e2 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x000005f8 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000003 /* EMC_PDEX2WR */ - 0x00000011 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x000000c6 /* EMC_AR2PDEN */ - 0x00000018 /* EMC_RW2PDEN */ - 0x000000d6 /* EMC_TXSR */ - 0x00000200 /* EMC_TXSRDLL */ - 0x00000005 /* EMC_TCKE */ - 0x00000006 /* EMC_TCKESR */ - 0x00000005 /* EMC_TPD */ - 0x0000001d /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000008 /* EMC_TCLKSTABLE */ - 0x00000008 /* EMC_TCLKSTOP */ - 0x00001822 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x80000005 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x104ab198 /* EMC_FBIO_CFG5 */ - 0xe00700b1 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00000005 /* EMC_DLL_XFORM_DQS0 */ - 0x00000005 /* EMC_DLL_XFORM_DQS1 */ - 0x00000005 /* EMC_DLL_XFORM_DQS2 */ - 0x00000005 /* EMC_DLL_XFORM_DQS3 */ - 0x00000005 /* EMC_DLL_XFORM_DQS4 */ - 0x00000005 /* EMC_DLL_XFORM_DQS5 */ - 0x00000005 /* EMC_DLL_XFORM_DQS6 */ - 0x00000005 /* EMC_DLL_XFORM_DQS7 */ - 0x00000005 /* EMC_DLL_XFORM_DQS8 */ - 0x00000005 /* EMC_DLL_XFORM_DQS9 */ - 0x00000005 /* EMC_DLL_XFORM_DQS10 */ - 0x00000005 /* EMC_DLL_XFORM_DQS11 */ - 0x00000005 /* EMC_DLL_XFORM_DQS12 */ - 0x00000005 /* EMC_DLL_XFORM_DQS13 */ - 0x00000005 /* EMC_DLL_XFORM_DQS14 */ - 0x00000005 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00034000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00034000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00034000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00034000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000008 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000008 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000005 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000009 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000009 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000007 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000009 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000008 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000008 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000008 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000005 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000009 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000009 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000007 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000009 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000008 /* EMC_DLI_TRIM_TXDQS15 */ - 0x0000000a /* EMC_DLL_XFORM_DQ0 */ - 0x0000000a /* EMC_DLL_XFORM_DQ1 */ - 0x0000000a /* EMC_DLL_XFORM_DQ2 */ - 0x0000000a /* EMC_DLL_XFORM_DQ3 */ - 0x0000000a /* EMC_DLL_XFORM_DQ4 */ - 0x0000000a /* EMC_DLL_XFORM_DQ5 */ - 0x0000000a /* EMC_DLL_XFORM_DQ6 */ - 0x0000000a /* EMC_DLL_XFORM_DQ7 */ - 0x100002a0 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc085 /* EMC_XM2CLKPADCTRL */ - 0x00000101 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x61861820 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x61861800 /* EMC_XM2DQSPADCTRL6 */ - 0x0606003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000000 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x00f8000c /* EMC_MRS_WAIT_CNT2 */ - 0x00000007 /* EMC_CTT */ - 0x00000004 /* EMC_CTT_DURATION */ - 0x00004080 /* EMC_CFG_PIPE */ - 0x80003012 /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000f /* EMC_QPOP */ - >; - }; - }; - - emc-timings-4 { - nvidia,ram-code = <4>; - - timing-12750000 { - clock-frequency = <12750000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x00100003>; - nvidia,emc-mode-2 = <0x00200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x00001221>; - nvidia,emc-mrs-wait-cnt = <0x000e000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000000 /* EMC_RC */ - 0x00000004 /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000000 /* EMC_RAS */ - 0x00000000 /* EMC_RP */ - 0x00000004 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000005 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000000 /* EMC_RD_RCD */ - 0x00000000 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000003 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000006 /* EMC_WDV */ - 0x00000006 /* EMC_WDV_MASK */ - 0x00000006 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000005 /* EMC_EINPUT */ - 0x00000005 /* EMC_EINPUT_DURATION */ - 0x00010000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000004 /* EMC_QRST */ - 0x0000000c /* EMC_QSAFE */ - 0x0000000d /* EMC_RDV */ - 0x0000000f /* EMC_RDV_MASK */ - 0x00000060 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000018 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000007 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x00000005 /* EMC_TXSR */ - 0x00000005 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000000 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000005 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x00000064 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x106aa298 /* EMC_FBIO_CFG5 */ - 0x002c00a0 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00064000 /* EMC_DLL_XFORM_DQS0 */ - 0x00064000 /* EMC_DLL_XFORM_DQS1 */ - 0x00064000 /* EMC_DLL_XFORM_DQS2 */ - 0x00064000 /* EMC_DLL_XFORM_DQS3 */ - 0x00064000 /* EMC_DLL_XFORM_DQS4 */ - 0x00064000 /* EMC_DLL_XFORM_DQS5 */ - 0x00064000 /* EMC_DLL_XFORM_DQS6 */ - 0x00064000 /* EMC_DLL_XFORM_DQS7 */ - 0x00064000 /* EMC_DLL_XFORM_DQS8 */ - 0x00064000 /* EMC_DLL_XFORM_DQS9 */ - 0x00064000 /* EMC_DLL_XFORM_DQS10 */ - 0x00064000 /* EMC_DLL_XFORM_DQS11 */ - 0x00064000 /* EMC_DLL_XFORM_DQS12 */ - 0x00064000 /* EMC_DLL_XFORM_DQS13 */ - 0x00064000 /* EMC_DLL_XFORM_DQS14 */ - 0x00064000 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ - 0x00080000 /* EMC_DLL_XFORM_DQ0 */ - 0x00080000 /* EMC_DLL_XFORM_DQ1 */ - 0x00080000 /* EMC_DLL_XFORM_DQ2 */ - 0x00080000 /* EMC_DLL_XFORM_DQ3 */ - 0x00008000 /* EMC_DLL_XFORM_DQ4 */ - 0x00008000 /* EMC_DLL_XFORM_DQ5 */ - 0x00008000 /* EMC_DLL_XFORM_DQ6 */ - 0x00008000 /* EMC_DLL_XFORM_DQ7 */ - 0x10000280 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc081 /* EMC_XM2CLKPADCTRL */ - 0x00000303 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451400 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0000003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000007 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000042 /* EMC_ZCAL_WAIT_CNT */ - 0x000e000e /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x0000f2f3 /* EMC_CFG_PIPE */ - 0x800001c5 /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000a /* EMC_QPOP */ - >; - }; - - timing-20400000 { - clock-frequency = <20400000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x00100003>; - nvidia,emc-mode-2 = <0x00200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x00001221>; - nvidia,emc-mrs-wait-cnt = <0x000e000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000000 /* EMC_RC */ - 0x00000007 /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000000 /* EMC_RAS */ - 0x00000000 /* EMC_RP */ - 0x00000004 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000005 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000000 /* EMC_RD_RCD */ - 0x00000000 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000003 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000006 /* EMC_WDV */ - 0x00000006 /* EMC_WDV_MASK */ - 0x00000006 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000005 /* EMC_EINPUT */ - 0x00000005 /* EMC_EINPUT_DURATION */ - 0x00010000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000004 /* EMC_QRST */ - 0x0000000c /* EMC_QSAFE */ - 0x0000000d /* EMC_RDV */ - 0x0000000f /* EMC_RDV_MASK */ - 0x0000009a /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000026 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000007 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x00000008 /* EMC_TXSR */ - 0x00000008 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000000 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000005 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x000000a0 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x106aa298 /* EMC_FBIO_CFG5 */ - 0x002c00a0 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00064000 /* EMC_DLL_XFORM_DQS0 */ - 0x00064000 /* EMC_DLL_XFORM_DQS1 */ - 0x00064000 /* EMC_DLL_XFORM_DQS2 */ - 0x00064000 /* EMC_DLL_XFORM_DQS3 */ - 0x00064000 /* EMC_DLL_XFORM_DQS4 */ - 0x00064000 /* EMC_DLL_XFORM_DQS5 */ - 0x00064000 /* EMC_DLL_XFORM_DQS6 */ - 0x00064000 /* EMC_DLL_XFORM_DQS7 */ - 0x00064000 /* EMC_DLL_XFORM_DQS8 */ - 0x00064000 /* EMC_DLL_XFORM_DQS9 */ - 0x00064000 /* EMC_DLL_XFORM_DQS10 */ - 0x00064000 /* EMC_DLL_XFORM_DQS11 */ - 0x00064000 /* EMC_DLL_XFORM_DQS12 */ - 0x00064000 /* EMC_DLL_XFORM_DQS13 */ - 0x00064000 /* EMC_DLL_XFORM_DQS14 */ - 0x00064000 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ - 0x00080000 /* EMC_DLL_XFORM_DQ0 */ - 0x00080000 /* EMC_DLL_XFORM_DQ1 */ - 0x00080000 /* EMC_DLL_XFORM_DQ2 */ - 0x00080000 /* EMC_DLL_XFORM_DQ3 */ - 0x00008000 /* EMC_DLL_XFORM_DQ4 */ - 0x00008000 /* EMC_DLL_XFORM_DQ5 */ - 0x00008000 /* EMC_DLL_XFORM_DQ6 */ - 0x00008000 /* EMC_DLL_XFORM_DQ7 */ - 0x10000280 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc081 /* EMC_XM2CLKPADCTRL */ - 0x00000303 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451400 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0000003f /* EMC_DSR_VTTGEN_DRV */ - 0x0000000b /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000042 /* EMC_ZCAL_WAIT_CNT */ - 0x000e000e /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x0000f2f3 /* EMC_CFG_PIPE */ - 0x8000023a /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000a /* EMC_QPOP */ - >; - }; - - timing-40800000 { - clock-frequency = <40800000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x00100003>; - nvidia,emc-mode-2 = <0x00200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x00001221>; - nvidia,emc-mrs-wait-cnt = <0x000e000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000001 /* EMC_RC */ - 0x0000000e /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000001 /* EMC_RAS */ - 0x00000000 /* EMC_RP */ - 0x00000004 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000005 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000000 /* EMC_RD_RCD */ - 0x00000000 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000003 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000006 /* EMC_WDV */ - 0x00000006 /* EMC_WDV_MASK */ - 0x00000006 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000005 /* EMC_EINPUT */ - 0x00000005 /* EMC_EINPUT_DURATION */ - 0x00010000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000004 /* EMC_QRST */ - 0x0000000c /* EMC_QSAFE */ - 0x0000000d /* EMC_RDV */ - 0x0000000f /* EMC_RDV_MASK */ - 0x00000134 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x0000004d /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x0000000c /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x0000000f /* EMC_TXSR */ - 0x0000000f /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000000 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000005 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x0000013f /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x106aa298 /* EMC_FBIO_CFG5 */ - 0x002c00a0 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00064000 /* EMC_DLL_XFORM_DQS0 */ - 0x00064000 /* EMC_DLL_XFORM_DQS1 */ - 0x00064000 /* EMC_DLL_XFORM_DQS2 */ - 0x00064000 /* EMC_DLL_XFORM_DQS3 */ - 0x00064000 /* EMC_DLL_XFORM_DQS4 */ - 0x00064000 /* EMC_DLL_XFORM_DQS5 */ - 0x00064000 /* EMC_DLL_XFORM_DQS6 */ - 0x00064000 /* EMC_DLL_XFORM_DQS7 */ - 0x00064000 /* EMC_DLL_XFORM_DQS8 */ - 0x00064000 /* EMC_DLL_XFORM_DQS9 */ - 0x00064000 /* EMC_DLL_XFORM_DQS10 */ - 0x00064000 /* EMC_DLL_XFORM_DQS11 */ - 0x00064000 /* EMC_DLL_XFORM_DQS12 */ - 0x00064000 /* EMC_DLL_XFORM_DQS13 */ - 0x00064000 /* EMC_DLL_XFORM_DQS14 */ - 0x00064000 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ - 0x00080000 /* EMC_DLL_XFORM_DQ0 */ - 0x00080000 /* EMC_DLL_XFORM_DQ1 */ - 0x00080000 /* EMC_DLL_XFORM_DQ2 */ - 0x00080000 /* EMC_DLL_XFORM_DQ3 */ - 0x00008000 /* EMC_DLL_XFORM_DQ4 */ - 0x00008000 /* EMC_DLL_XFORM_DQ5 */ - 0x00008000 /* EMC_DLL_XFORM_DQ6 */ - 0x00008000 /* EMC_DLL_XFORM_DQ7 */ - 0x10000280 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc081 /* EMC_XM2CLKPADCTRL */ - 0x00000303 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451400 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0000003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000015 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000042 /* EMC_ZCAL_WAIT_CNT */ - 0x000e000e /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x0000f2f3 /* EMC_CFG_PIPE */ - 0x80000370 /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000a /* EMC_QPOP */ - >; - }; - - timing-68000000 { - clock-frequency = <68000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x00100003>; - nvidia,emc-mode-2 = <0x00200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x00001221>; - nvidia,emc-mrs-wait-cnt = <0x000e000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000003 /* EMC_RC */ - 0x00000017 /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000002 /* EMC_RAS */ - 0x00000000 /* EMC_RP */ - 0x00000004 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000005 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000000 /* EMC_RD_RCD */ - 0x00000000 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000003 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000006 /* EMC_WDV */ - 0x00000006 /* EMC_WDV_MASK */ - 0x00000006 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000005 /* EMC_EINPUT */ - 0x00000005 /* EMC_EINPUT_DURATION */ - 0x00010000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000004 /* EMC_QRST */ - 0x0000000c /* EMC_QSAFE */ - 0x0000000d /* EMC_RDV */ - 0x0000000f /* EMC_RDV_MASK */ - 0x00000202 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000080 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000015 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x00000019 /* EMC_TXSR */ - 0x00000019 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000001 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000005 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x00000213 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x106aa298 /* EMC_FBIO_CFG5 */ - 0x002c00a0 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00064000 /* EMC_DLL_XFORM_DQS0 */ - 0x00064000 /* EMC_DLL_XFORM_DQS1 */ - 0x00064000 /* EMC_DLL_XFORM_DQS2 */ - 0x00064000 /* EMC_DLL_XFORM_DQS3 */ - 0x00064000 /* EMC_DLL_XFORM_DQS4 */ - 0x00064000 /* EMC_DLL_XFORM_DQS5 */ - 0x00064000 /* EMC_DLL_XFORM_DQS6 */ - 0x00064000 /* EMC_DLL_XFORM_DQS7 */ - 0x00064000 /* EMC_DLL_XFORM_DQS8 */ - 0x00064000 /* EMC_DLL_XFORM_DQS9 */ - 0x00064000 /* EMC_DLL_XFORM_DQS10 */ - 0x00064000 /* EMC_DLL_XFORM_DQS11 */ - 0x00064000 /* EMC_DLL_XFORM_DQS12 */ - 0x00064000 /* EMC_DLL_XFORM_DQS13 */ - 0x00064000 /* EMC_DLL_XFORM_DQS14 */ - 0x00064000 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ - 0x00080000 /* EMC_DLL_XFORM_DQ0 */ - 0x00080000 /* EMC_DLL_XFORM_DQ1 */ - 0x00080000 /* EMC_DLL_XFORM_DQ2 */ - 0x00080000 /* EMC_DLL_XFORM_DQ3 */ - 0x00008000 /* EMC_DLL_XFORM_DQ4 */ - 0x00008000 /* EMC_DLL_XFORM_DQ5 */ - 0x00008000 /* EMC_DLL_XFORM_DQ6 */ - 0x00008000 /* EMC_DLL_XFORM_DQ7 */ - 0x10000280 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc081 /* EMC_XM2CLKPADCTRL */ - 0x00000303 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451400 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0000003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000022 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000042 /* EMC_ZCAL_WAIT_CNT */ - 0x000e000e /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x0000f2f3 /* EMC_CFG_PIPE */ - 0x8000050e /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000a /* EMC_QPOP */ - >; - }; - - timing-102000000 { - clock-frequency = <102000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x00100003>; - nvidia,emc-mode-2 = <0x00200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x00001221>; - nvidia,emc-mrs-wait-cnt = <0x000e000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000004 /* EMC_RC */ - 0x00000023 /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000003 /* EMC_RAS */ - 0x00000001 /* EMC_RP */ - 0x00000004 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000005 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000001 /* EMC_RD_RCD */ - 0x00000001 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000003 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000006 /* EMC_WDV */ - 0x00000006 /* EMC_WDV_MASK */ - 0x00000006 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000005 /* EMC_EINPUT */ - 0x00000005 /* EMC_EINPUT_DURATION */ - 0x00010000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000004 /* EMC_QRST */ - 0x0000000c /* EMC_QSAFE */ - 0x0000000d /* EMC_RDV */ - 0x0000000f /* EMC_RDV_MASK */ - 0x00000304 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x000000c1 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000021 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x00000025 /* EMC_TXSR */ - 0x00000025 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000003 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000005 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x0000031c /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x106aa298 /* EMC_FBIO_CFG5 */ - 0x002c00a0 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00064000 /* EMC_DLL_XFORM_DQS0 */ - 0x00064000 /* EMC_DLL_XFORM_DQS1 */ - 0x00064000 /* EMC_DLL_XFORM_DQS2 */ - 0x00064000 /* EMC_DLL_XFORM_DQS3 */ - 0x00064000 /* EMC_DLL_XFORM_DQS4 */ - 0x00064000 /* EMC_DLL_XFORM_DQS5 */ - 0x00064000 /* EMC_DLL_XFORM_DQS6 */ - 0x00064000 /* EMC_DLL_XFORM_DQS7 */ - 0x00064000 /* EMC_DLL_XFORM_DQS8 */ - 0x00064000 /* EMC_DLL_XFORM_DQS9 */ - 0x00064000 /* EMC_DLL_XFORM_DQS10 */ - 0x00064000 /* EMC_DLL_XFORM_DQS11 */ - 0x00064000 /* EMC_DLL_XFORM_DQS12 */ - 0x00064000 /* EMC_DLL_XFORM_DQS13 */ - 0x00064000 /* EMC_DLL_XFORM_DQS14 */ - 0x00064000 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ - 0x00080000 /* EMC_DLL_XFORM_DQ0 */ - 0x00080000 /* EMC_DLL_XFORM_DQ1 */ - 0x00080000 /* EMC_DLL_XFORM_DQ2 */ - 0x00080000 /* EMC_DLL_XFORM_DQ3 */ - 0x00008000 /* EMC_DLL_XFORM_DQ4 */ - 0x00008000 /* EMC_DLL_XFORM_DQ5 */ - 0x00008000 /* EMC_DLL_XFORM_DQ6 */ - 0x00008000 /* EMC_DLL_XFORM_DQ7 */ - 0x10000280 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc081 /* EMC_XM2CLKPADCTRL */ - 0x00000303 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451400 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0000003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000033 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000042 /* EMC_ZCAL_WAIT_CNT */ - 0x000e000e /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x0000f2f3 /* EMC_CFG_PIPE */ - 0x80000713 /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000a /* EMC_QPOP */ - >; - }; - - timing-204000000 { - clock-frequency = <204000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x0000088d>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x00100003>; - nvidia,emc-mode-2 = <0x00200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x00001221>; - nvidia,emc-mrs-wait-cnt = <0x000e000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040008>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x00000009 /* EMC_RC */ - 0x00000047 /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000006 /* EMC_RAS */ - 0x00000002 /* EMC_RP */ - 0x00000005 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000005 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000002 /* EMC_RD_RCD */ - 0x00000002 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000003 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000005 /* EMC_WDV */ - 0x00000005 /* EMC_WDV_MASK */ - 0x00000006 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000004 /* EMC_EINPUT */ - 0x00000006 /* EMC_EINPUT_DURATION */ - 0x00010000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000003 /* EMC_QRST */ - 0x0000000d /* EMC_QSAFE */ - 0x0000000f /* EMC_RDV */ - 0x00000011 /* EMC_RDV_MASK */ - 0x00000607 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000181 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000044 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x0000004a /* EMC_TXSR */ - 0x0000004a /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000007 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000005 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x00000638 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x106aa298 /* EMC_FBIO_CFG5 */ - 0x002c00a0 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00064000 /* EMC_DLL_XFORM_DQS0 */ - 0x00064000 /* EMC_DLL_XFORM_DQS1 */ - 0x00064000 /* EMC_DLL_XFORM_DQS2 */ - 0x00064000 /* EMC_DLL_XFORM_DQS3 */ - 0x00064000 /* EMC_DLL_XFORM_DQS4 */ - 0x00064000 /* EMC_DLL_XFORM_DQS5 */ - 0x00064000 /* EMC_DLL_XFORM_DQS6 */ - 0x00064000 /* EMC_DLL_XFORM_DQS7 */ - 0x00064000 /* EMC_DLL_XFORM_DQS8 */ - 0x00064000 /* EMC_DLL_XFORM_DQS9 */ - 0x00064000 /* EMC_DLL_XFORM_DQS10 */ - 0x00064000 /* EMC_DLL_XFORM_DQS11 */ - 0x00064000 /* EMC_DLL_XFORM_DQS12 */ - 0x00064000 /* EMC_DLL_XFORM_DQS13 */ - 0x00064000 /* EMC_DLL_XFORM_DQS14 */ - 0x00064000 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ - 0x00090000 /* EMC_DLL_XFORM_DQ0 */ - 0x00090000 /* EMC_DLL_XFORM_DQ1 */ - 0x00094000 /* EMC_DLL_XFORM_DQ2 */ - 0x00094000 /* EMC_DLL_XFORM_DQ3 */ - 0x00009400 /* EMC_DLL_XFORM_DQ4 */ - 0x00009000 /* EMC_DLL_XFORM_DQ5 */ - 0x00009000 /* EMC_DLL_XFORM_DQ6 */ - 0x00009000 /* EMC_DLL_XFORM_DQ7 */ - 0x10000280 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc081 /* EMC_XM2CLKPADCTRL */ - 0x00000303 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451400 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0000003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000066 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x000e000e /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x0000d2b3 /* EMC_CFG_PIPE */ - 0x80000d22 /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000a /* EMC_QPOP */ - >; - }; - - timing-300000000 { - clock-frequency = <300000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73340000>; - nvidia,emc-cfg-2 = <0x000008d5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x00100002>; - nvidia,emc-mode-2 = <0x00200000>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x00000321>; - nvidia,emc-mrs-wait-cnt = <0x0117000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x01231339>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x0000000d /* EMC_RC */ - 0x00000067 /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000009 /* EMC_RAS */ - 0x00000003 /* EMC_RP */ - 0x00000004 /* EMC_R2W */ - 0x00000008 /* EMC_W2R */ - 0x00000002 /* EMC_R2P */ - 0x00000009 /* EMC_W2P */ - 0x00000003 /* EMC_RD_RCD */ - 0x00000003 /* EMC_WR_RCD */ - 0x00000002 /* EMC_RRD */ - 0x00000002 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000003 /* EMC_WDV */ - 0x00000003 /* EMC_WDV_MASK */ - 0x00000005 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000002 /* EMC_EINPUT */ - 0x00000007 /* EMC_EINPUT_DURATION */ - 0x00020000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000001 /* EMC_QRST */ - 0x0000000e /* EMC_QSAFE */ - 0x00000010 /* EMC_RDV */ - 0x00000012 /* EMC_RDV_MASK */ - 0x000008e4 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000239 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000001 /* EMC_PDEX2WR */ - 0x00000008 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000065 /* EMC_AR2PDEN */ - 0x0000000e /* EMC_RW2PDEN */ - 0x0000006c /* EMC_TXSR */ - 0x00000200 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000009 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000005 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x00000924 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x104ab098 /* EMC_FBIO_CFG5 */ - 0x002c00a0 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00030000 /* EMC_DLL_XFORM_DQS0 */ - 0x00030000 /* EMC_DLL_XFORM_DQS1 */ - 0x00030000 /* EMC_DLL_XFORM_DQS2 */ - 0x00030000 /* EMC_DLL_XFORM_DQS3 */ - 0x00030000 /* EMC_DLL_XFORM_DQS4 */ - 0x00030000 /* EMC_DLL_XFORM_DQS5 */ - 0x00030000 /* EMC_DLL_XFORM_DQS6 */ - 0x00030000 /* EMC_DLL_XFORM_DQS7 */ - 0x00030000 /* EMC_DLL_XFORM_DQS8 */ - 0x00030000 /* EMC_DLL_XFORM_DQS9 */ - 0x00030000 /* EMC_DLL_XFORM_DQS10 */ - 0x00030000 /* EMC_DLL_XFORM_DQS11 */ - 0x00030000 /* EMC_DLL_XFORM_DQS12 */ - 0x00030000 /* EMC_DLL_XFORM_DQS13 */ - 0x00030000 /* EMC_DLL_XFORM_DQS14 */ - 0x00030000 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00098000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00098000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00098000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00098000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ - 0x00060000 /* EMC_DLL_XFORM_DQ0 */ - 0x00060000 /* EMC_DLL_XFORM_DQ1 */ - 0x00060000 /* EMC_DLL_XFORM_DQ2 */ - 0x00060000 /* EMC_DLL_XFORM_DQ3 */ - 0x00006000 /* EMC_DLL_XFORM_DQ4 */ - 0x00006000 /* EMC_DLL_XFORM_DQ5 */ - 0x00006000 /* EMC_DLL_XFORM_DQ6 */ - 0x00006000 /* EMC_DLL_XFORM_DQ7 */ - 0x10000280 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc081 /* EMC_XM2CLKPADCTRL */ - 0x00000101 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451420 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0000003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000096 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x0117000e /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x000052a3 /* EMC_CFG_PIPE */ - 0x800012d7 /* EMC_DYN_SELF_REF_CONTROL */ - 0x00000009 /* EMC_QPOP */ - >; - }; - - timing-396000000 { - clock-frequency = <396000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73340000>; - nvidia,emc-cfg-2 = <0x00000895>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x00100002>; - nvidia,emc-mode-2 = <0x00200000>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x00000521>; - nvidia,emc-mrs-wait-cnt = <0x00f5000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040008>; - nvidia,emc-xm2dqspadctrl2 = <0x01231339>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x00000011 /* EMC_RC */ - 0x00000089 /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x0000000c /* EMC_RAS */ - 0x00000004 /* EMC_RP */ - 0x00000005 /* EMC_R2W */ - 0x00000008 /* EMC_W2R */ - 0x00000002 /* EMC_R2P */ - 0x0000000a /* EMC_W2P */ - 0x00000004 /* EMC_RD_RCD */ - 0x00000004 /* EMC_WR_RCD */ - 0x00000002 /* EMC_RRD */ - 0x00000002 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000003 /* EMC_WDV */ - 0x00000003 /* EMC_WDV_MASK */ - 0x00000005 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000001 /* EMC_EINPUT */ - 0x00000008 /* EMC_EINPUT_DURATION */ - 0x00020000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000000 /* EMC_QRST */ - 0x0000000f /* EMC_QSAFE */ - 0x00000010 /* EMC_RDV */ - 0x00000012 /* EMC_RDV_MASK */ - 0x00000bd1 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x000002f4 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000001 /* EMC_PDEX2WR */ - 0x00000008 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000087 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x0000008f /* EMC_TXSR */ - 0x00000200 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x0000000d /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000005 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x00000c11 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x104ab098 /* EMC_FBIO_CFG5 */ - 0x002c00a0 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00030000 /* EMC_DLL_XFORM_DQS0 */ - 0x00030000 /* EMC_DLL_XFORM_DQS1 */ - 0x00030000 /* EMC_DLL_XFORM_DQS2 */ - 0x00030000 /* EMC_DLL_XFORM_DQS3 */ - 0x00030000 /* EMC_DLL_XFORM_DQS4 */ - 0x00030000 /* EMC_DLL_XFORM_DQS5 */ - 0x00030000 /* EMC_DLL_XFORM_DQS6 */ - 0x00030000 /* EMC_DLL_XFORM_DQS7 */ - 0x00030000 /* EMC_DLL_XFORM_DQS8 */ - 0x00030000 /* EMC_DLL_XFORM_DQS9 */ - 0x00030000 /* EMC_DLL_XFORM_DQS10 */ - 0x00030000 /* EMC_DLL_XFORM_DQS11 */ - 0x00030000 /* EMC_DLL_XFORM_DQS12 */ - 0x00030000 /* EMC_DLL_XFORM_DQS13 */ - 0x00030000 /* EMC_DLL_XFORM_DQS14 */ - 0x00030000 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00070000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00070000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00070000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00070000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ - 0x00048000 /* EMC_DLL_XFORM_DQ0 */ - 0x00048000 /* EMC_DLL_XFORM_DQ1 */ - 0x00048000 /* EMC_DLL_XFORM_DQ2 */ - 0x00048000 /* EMC_DLL_XFORM_DQ3 */ - 0x00004800 /* EMC_DLL_XFORM_DQ4 */ - 0x00004800 /* EMC_DLL_XFORM_DQ5 */ - 0x00004800 /* EMC_DLL_XFORM_DQ6 */ - 0x00004800 /* EMC_DLL_XFORM_DQ7 */ - 0x10000280 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc081 /* EMC_XM2CLKPADCTRL */ - 0x00000101 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451420 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0000003f /* EMC_DSR_VTTGEN_DRV */ - 0x000000c6 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x00f5000e /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x000052a3 /* EMC_CFG_PIPE */ - 0x8000188b /* EMC_DYN_SELF_REF_CONTROL */ - 0x00000009 /* EMC_QPOP */ - >; - }; - - timing-528000000 { - clock-frequency = <528000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73300000>; - nvidia,emc-cfg-2 = <0x0000089d>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x00100002>; - nvidia,emc-mode-2 = <0x00200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x00000941>; - nvidia,emc-mrs-wait-cnt = <0x00c8000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040008>; - nvidia,emc-xm2dqspadctrl2 = <0x0123133d>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x00000018 /* EMC_RC */ - 0x000000b7 /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000010 /* EMC_RAS */ - 0x00000006 /* EMC_RP */ - 0x00000006 /* EMC_R2W */ - 0x00000009 /* EMC_W2R */ - 0x00000002 /* EMC_R2P */ - 0x0000000d /* EMC_W2P */ - 0x00000006 /* EMC_RD_RCD */ - 0x00000006 /* EMC_WR_RCD */ - 0x00000002 /* EMC_RRD */ - 0x00000002 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000003 /* EMC_WDV */ - 0x00000003 /* EMC_WDV_MASK */ - 0x00000007 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000002 /* EMC_EINPUT */ - 0x00000009 /* EMC_EINPUT_DURATION */ - 0x00040000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000001 /* EMC_QRST */ - 0x00000010 /* EMC_QSAFE */ - 0x00000013 /* EMC_RDV */ - 0x00000015 /* EMC_RDV_MASK */ - 0x00000fd6 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x000003f5 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x0000000b /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x000000b4 /* EMC_AR2PDEN */ - 0x00000012 /* EMC_RW2PDEN */ - 0x000000bf /* EMC_TXSR */ - 0x00000200 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000013 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000006 /* EMC_TCLKSTABLE */ - 0x00000006 /* EMC_TCLKSTOP */ - 0x00001017 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x104ab098 /* EMC_FBIO_CFG5 */ - 0xe01200b1 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x0000000a /* EMC_DLL_XFORM_DQS0 */ - 0x0000000a /* EMC_DLL_XFORM_DQS1 */ - 0x0000000a /* EMC_DLL_XFORM_DQS2 */ - 0x0000000a /* EMC_DLL_XFORM_DQS3 */ - 0x0000000a /* EMC_DLL_XFORM_DQS4 */ - 0x0000000a /* EMC_DLL_XFORM_DQS5 */ - 0x0000000a /* EMC_DLL_XFORM_DQS6 */ - 0x0000000a /* EMC_DLL_XFORM_DQS7 */ - 0x0000000a /* EMC_DLL_XFORM_DQS8 */ - 0x0000000a /* EMC_DLL_XFORM_DQS9 */ - 0x0000000a /* EMC_DLL_XFORM_DQS10 */ - 0x0000000a /* EMC_DLL_XFORM_DQS11 */ - 0x0000000a /* EMC_DLL_XFORM_DQS12 */ - 0x0000000a /* EMC_DLL_XFORM_DQS13 */ - 0x0000000a /* EMC_DLL_XFORM_DQS14 */ - 0x0000000a /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00050000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00050000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00050000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00050000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000002 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000002 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000003 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000004 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000001 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000004 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000003 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000002 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000002 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000003 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000004 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000001 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000004 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000003 /* EMC_DLI_TRIM_TXDQS15 */ - 0x0000000e /* EMC_DLL_XFORM_DQ0 */ - 0x0000000e /* EMC_DLL_XFORM_DQ1 */ - 0x0000000e /* EMC_DLL_XFORM_DQ2 */ - 0x0000000e /* EMC_DLL_XFORM_DQ3 */ - 0x0000000e /* EMC_DLL_XFORM_DQ4 */ - 0x0000000e /* EMC_DLL_XFORM_DQ5 */ - 0x0000000e /* EMC_DLL_XFORM_DQ6 */ - 0x0000000e /* EMC_DLL_XFORM_DQ7 */ - 0x100002a0 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc085 /* EMC_XM2CLKPADCTRL */ - 0x00000101 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451420 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0606003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000000 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x00c8000e /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x000042a0 /* EMC_CFG_PIPE */ - 0x80002062 /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000b /* EMC_QPOP */ - >; - }; - - timing-600000000 { - clock-frequency = <600000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73300000>; - nvidia,emc-cfg-2 = <0x0000089d>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x00100002>; - nvidia,emc-mode-2 = <0x00200010>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x00000b61>; - nvidia,emc-mrs-wait-cnt = <0x00b0000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040008>; - nvidia,emc-xm2dqspadctrl2 = <0x0121113d>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x0000001b /* EMC_RC */ - 0x000000d0 /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000013 /* EMC_RAS */ - 0x00000007 /* EMC_RP */ - 0x00000007 /* EMC_R2W */ - 0x0000000b /* EMC_W2R */ - 0x00000003 /* EMC_R2P */ - 0x00000010 /* EMC_W2P */ - 0x00000007 /* EMC_RD_RCD */ - 0x00000007 /* EMC_WR_RCD */ - 0x00000002 /* EMC_RRD */ - 0x00000002 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000005 /* EMC_WDV */ - 0x00000005 /* EMC_WDV_MASK */ - 0x0000000a /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000003 /* EMC_EINPUT */ - 0x0000000b /* EMC_EINPUT_DURATION */ - 0x00070000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000002 /* EMC_QRST */ - 0x00000012 /* EMC_QSAFE */ - 0x00000016 /* EMC_RDV */ - 0x00000018 /* EMC_RDV_MASK */ - 0x00001208 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000482 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x0000000d /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x000000cc /* EMC_AR2PDEN */ - 0x00000015 /* EMC_RW2PDEN */ - 0x000000d8 /* EMC_TXSR */ - 0x00000200 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000015 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000006 /* EMC_TCLKSTABLE */ - 0x00000006 /* EMC_TCLKSTOP */ - 0x00001249 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x104ab098 /* EMC_FBIO_CFG5 */ - 0xe00e00b1 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x0000000a /* EMC_DLL_XFORM_DQS0 */ - 0x0000000a /* EMC_DLL_XFORM_DQS1 */ - 0x0000000a /* EMC_DLL_XFORM_DQS2 */ - 0x0000000a /* EMC_DLL_XFORM_DQS3 */ - 0x0000000a /* EMC_DLL_XFORM_DQS4 */ - 0x0000000a /* EMC_DLL_XFORM_DQS5 */ - 0x0000000a /* EMC_DLL_XFORM_DQS6 */ - 0x0000000a /* EMC_DLL_XFORM_DQS7 */ - 0x0000000a /* EMC_DLL_XFORM_DQS8 */ - 0x0000000a /* EMC_DLL_XFORM_DQS9 */ - 0x0000000a /* EMC_DLL_XFORM_DQS10 */ - 0x0000000a /* EMC_DLL_XFORM_DQS11 */ - 0x0000000a /* EMC_DLL_XFORM_DQS12 */ - 0x0000000a /* EMC_DLL_XFORM_DQS13 */ - 0x0000000a /* EMC_DLL_XFORM_DQS14 */ - 0x0000000a /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00048000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00048000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00048000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00048000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000004 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000004 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000002 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000005 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000006 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000003 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000006 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000005 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000004 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000004 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000002 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000005 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000006 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000003 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000006 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000005 /* EMC_DLI_TRIM_TXDQS15 */ - 0x0000000e /* EMC_DLL_XFORM_DQ0 */ - 0x0000000e /* EMC_DLL_XFORM_DQ1 */ - 0x0000000e /* EMC_DLL_XFORM_DQ2 */ - 0x0000000e /* EMC_DLL_XFORM_DQ3 */ - 0x0000000e /* EMC_DLL_XFORM_DQ4 */ - 0x0000000e /* EMC_DLL_XFORM_DQ5 */ - 0x0000000e /* EMC_DLL_XFORM_DQ6 */ - 0x0000000e /* EMC_DLL_XFORM_DQ7 */ - 0x100002a0 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc085 /* EMC_XM2CLKPADCTRL */ - 0x00000101 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451420 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0606003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000000 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x00b0000e /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x000040a0 /* EMC_CFG_PIPE */ - 0x800024aa /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000e /* EMC_QPOP */ - >; - }; - - timing-792000000 { - clock-frequency = <792000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73300000>; - nvidia,emc-cfg-2 = <0x0080089d>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x00100002>; - nvidia,emc-mode-2 = <0x00200418>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x00000d71>; - nvidia,emc-mrs-wait-cnt = <0x006f000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040000>; - nvidia,emc-xm2dqspadctrl2 = <0x0120113d>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x00000024 /* EMC_RC */ - 0x00000114 /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000019 /* EMC_RAS */ - 0x0000000a /* EMC_RP */ - 0x00000008 /* EMC_R2W */ - 0x0000000d /* EMC_W2R */ - 0x00000004 /* EMC_R2P */ - 0x00000013 /* EMC_W2P */ - 0x0000000a /* EMC_RD_RCD */ - 0x0000000a /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000002 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000006 /* EMC_WDV */ - 0x00000006 /* EMC_WDV_MASK */ - 0x0000000b /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000002 /* EMC_EINPUT */ - 0x0000000d /* EMC_EINPUT_DURATION */ - 0x00080000 /* EMC_PUTERM_EXTRA */ - 0x00000004 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000001 /* EMC_QRST */ - 0x00000014 /* EMC_QSAFE */ - 0x00000018 /* EMC_RDV */ - 0x0000001a /* EMC_RDV_MASK */ - 0x000017e2 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x000005f8 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000003 /* EMC_PDEX2WR */ - 0x00000011 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x0000010d /* EMC_AR2PDEN */ - 0x00000018 /* EMC_RW2PDEN */ - 0x0000011e /* EMC_TXSR */ - 0x00000200 /* EMC_TXSRDLL */ - 0x00000005 /* EMC_TCKE */ - 0x00000006 /* EMC_TCKESR */ - 0x00000005 /* EMC_TPD */ - 0x0000001d /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000008 /* EMC_TCLKSTABLE */ - 0x00000008 /* EMC_TCLKSTOP */ - 0x00001822 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x80000005 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x104ab198 /* EMC_FBIO_CFG5 */ - 0xe00700b1 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x007fc007 /* EMC_DLL_XFORM_DQS0 */ - 0x007fc008 /* EMC_DLL_XFORM_DQS1 */ - 0x007f400c /* EMC_DLL_XFORM_DQS2 */ - 0x007fc007 /* EMC_DLL_XFORM_DQS3 */ - 0x007f4006 /* EMC_DLL_XFORM_DQS4 */ - 0x007f8004 /* EMC_DLL_XFORM_DQS5 */ - 0x007f8005 /* EMC_DLL_XFORM_DQS6 */ - 0x007f8004 /* EMC_DLL_XFORM_DQS7 */ - 0x007fc007 /* EMC_DLL_XFORM_DQS8 */ - 0x007fc008 /* EMC_DLL_XFORM_DQS9 */ - 0x007f400c /* EMC_DLL_XFORM_DQS10 */ - 0x007fc007 /* EMC_DLL_XFORM_DQS11 */ - 0x007f4006 /* EMC_DLL_XFORM_DQS12 */ - 0x007f8004 /* EMC_DLL_XFORM_DQS13 */ - 0x007f8005 /* EMC_DLL_XFORM_DQS14 */ - 0x007f8004 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00034000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00034000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00034000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00034000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000006 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000008 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000005 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000009 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000006 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000007 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000006 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000006 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000008 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000008 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000005 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000009 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000006 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000007 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000006 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000008 /* EMC_DLI_TRIM_TXDQS15 */ - 0x0000000e /* EMC_DLL_XFORM_DQ0 */ - 0x0000000e /* EMC_DLL_XFORM_DQ1 */ - 0x0000000e /* EMC_DLL_XFORM_DQ2 */ - 0x0000000e /* EMC_DLL_XFORM_DQ3 */ - 0x0000000e /* EMC_DLL_XFORM_DQ4 */ - 0x0000000e /* EMC_DLL_XFORM_DQ5 */ - 0x0000000e /* EMC_DLL_XFORM_DQ6 */ - 0x0000000e /* EMC_DLL_XFORM_DQ7 */ - 0x100002a0 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc085 /* EMC_XM2CLKPADCTRL */ - 0x00000101 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x61861820 /* EMC_XM2DQSPADCTRL3 */ - 0x00492492 /* EMC_XM2DQSPADCTRL4 */ - 0x00492492 /* EMC_XM2DQSPADCTRL5 */ - 0x61861800 /* EMC_XM2DQSPADCTRL6 */ - 0x0606003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000000 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x006f000e /* EMC_MRS_WAIT_CNT2 */ - 0x00000007 /* EMC_CTT */ - 0x00000004 /* EMC_CTT_DURATION */ - 0x00004080 /* EMC_CFG_PIPE */ - 0x80003012 /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000f /* EMC_QPOP */ - >; - }; - }; - - emc-timings-6 { - nvidia,ram-code = <6>; - - timing-12750000 { - clock-frequency = <12750000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000c000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000000 /* EMC_RC */ - 0x00000003 /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000000 /* EMC_RAS */ - 0x00000000 /* EMC_RP */ - 0x00000004 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000003 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000000 /* EMC_RD_RCD */ - 0x00000000 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000003 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000006 /* EMC_WDV */ - 0x00000006 /* EMC_WDV_MASK */ - 0x00000006 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000005 /* EMC_EINPUT */ - 0x00000005 /* EMC_EINPUT_DURATION */ - 0x00010000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000004 /* EMC_QRST */ - 0x0000000c /* EMC_QSAFE */ - 0x0000000d /* EMC_RDV */ - 0x0000000f /* EMC_RDV_MASK */ - 0x00000060 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000018 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000007 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x00000005 /* EMC_TXSR */ - 0x00000005 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000000 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000005 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x00000064 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x106aa298 /* EMC_FBIO_CFG5 */ - 0x002c00a0 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00064000 /* EMC_DLL_XFORM_DQS0 */ - 0x00064000 /* EMC_DLL_XFORM_DQS1 */ - 0x00064000 /* EMC_DLL_XFORM_DQS2 */ - 0x00064000 /* EMC_DLL_XFORM_DQS3 */ - 0x00064000 /* EMC_DLL_XFORM_DQS4 */ - 0x00064000 /* EMC_DLL_XFORM_DQS5 */ - 0x00064000 /* EMC_DLL_XFORM_DQS6 */ - 0x00064000 /* EMC_DLL_XFORM_DQS7 */ - 0x00064000 /* EMC_DLL_XFORM_DQS8 */ - 0x00064000 /* EMC_DLL_XFORM_DQS9 */ - 0x00064000 /* EMC_DLL_XFORM_DQS10 */ - 0x00064000 /* EMC_DLL_XFORM_DQS11 */ - 0x00064000 /* EMC_DLL_XFORM_DQS12 */ - 0x00064000 /* EMC_DLL_XFORM_DQS13 */ - 0x00064000 /* EMC_DLL_XFORM_DQS14 */ - 0x00064000 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ - 0x10000280 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc081 /* EMC_XM2CLKPADCTRL */ - 0x00000303 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451400 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0000003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000007 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000042 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x0000f2f3 /* EMC_CFG_PIPE */ - 0x800001c5 /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000a /* EMC_QPOP */ - >; - }; - - timing-20400000 { - clock-frequency = <20400000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000c000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000000 /* EMC_RC */ - 0x00000005 /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000000 /* EMC_RAS */ - 0x00000000 /* EMC_RP */ - 0x00000004 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000003 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000000 /* EMC_RD_RCD */ - 0x00000000 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000003 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000006 /* EMC_WDV */ - 0x00000006 /* EMC_WDV_MASK */ - 0x00000006 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000005 /* EMC_EINPUT */ - 0x00000005 /* EMC_EINPUT_DURATION */ - 0x00010000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000004 /* EMC_QRST */ - 0x0000000c /* EMC_QSAFE */ - 0x0000000d /* EMC_RDV */ - 0x0000000f /* EMC_RDV_MASK */ - 0x0000009a /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000026 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000007 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x00000006 /* EMC_TXSR */ - 0x00000006 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000000 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000005 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x000000a0 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x106aa298 /* EMC_FBIO_CFG5 */ - 0x002c00a0 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00064000 /* EMC_DLL_XFORM_DQS0 */ - 0x00064000 /* EMC_DLL_XFORM_DQS1 */ - 0x00064000 /* EMC_DLL_XFORM_DQS2 */ - 0x00064000 /* EMC_DLL_XFORM_DQS3 */ - 0x00064000 /* EMC_DLL_XFORM_DQS4 */ - 0x00064000 /* EMC_DLL_XFORM_DQS5 */ - 0x00064000 /* EMC_DLL_XFORM_DQS6 */ - 0x00064000 /* EMC_DLL_XFORM_DQS7 */ - 0x00064000 /* EMC_DLL_XFORM_DQS8 */ - 0x00064000 /* EMC_DLL_XFORM_DQS9 */ - 0x00064000 /* EMC_DLL_XFORM_DQS10 */ - 0x00064000 /* EMC_DLL_XFORM_DQS11 */ - 0x00064000 /* EMC_DLL_XFORM_DQS12 */ - 0x00064000 /* EMC_DLL_XFORM_DQS13 */ - 0x00064000 /* EMC_DLL_XFORM_DQS14 */ - 0x00064000 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ - 0x10000280 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc081 /* EMC_XM2CLKPADCTRL */ - 0x00000303 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451400 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0000003f /* EMC_DSR_VTTGEN_DRV */ - 0x0000000b /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000042 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x0000f2f3 /* EMC_CFG_PIPE */ - 0x8000023a /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000a /* EMC_QPOP */ - >; - }; - - timing-40800000 { - clock-frequency = <40800000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000c000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000001 /* EMC_RC */ - 0x0000000a /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000001 /* EMC_RAS */ - 0x00000000 /* EMC_RP */ - 0x00000004 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000003 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000000 /* EMC_RD_RCD */ - 0x00000000 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000003 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000006 /* EMC_WDV */ - 0x00000006 /* EMC_WDV_MASK */ - 0x00000006 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000005 /* EMC_EINPUT */ - 0x00000005 /* EMC_EINPUT_DURATION */ - 0x00010000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000004 /* EMC_QRST */ - 0x0000000c /* EMC_QSAFE */ - 0x0000000d /* EMC_RDV */ - 0x0000000f /* EMC_RDV_MASK */ - 0x00000134 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x0000004d /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000008 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x0000000c /* EMC_TXSR */ - 0x0000000c /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000000 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000005 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x0000013f /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x106aa298 /* EMC_FBIO_CFG5 */ - 0x002c00a0 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00064000 /* EMC_DLL_XFORM_DQS0 */ - 0x00064000 /* EMC_DLL_XFORM_DQS1 */ - 0x00064000 /* EMC_DLL_XFORM_DQS2 */ - 0x00064000 /* EMC_DLL_XFORM_DQS3 */ - 0x00064000 /* EMC_DLL_XFORM_DQS4 */ - 0x00064000 /* EMC_DLL_XFORM_DQS5 */ - 0x00064000 /* EMC_DLL_XFORM_DQS6 */ - 0x00064000 /* EMC_DLL_XFORM_DQS7 */ - 0x00064000 /* EMC_DLL_XFORM_DQS8 */ - 0x00064000 /* EMC_DLL_XFORM_DQS9 */ - 0x00064000 /* EMC_DLL_XFORM_DQS10 */ - 0x00064000 /* EMC_DLL_XFORM_DQS11 */ - 0x00064000 /* EMC_DLL_XFORM_DQS12 */ - 0x00064000 /* EMC_DLL_XFORM_DQS13 */ - 0x00064000 /* EMC_DLL_XFORM_DQS14 */ - 0x00064000 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ - 0x10000280 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc081 /* EMC_XM2CLKPADCTRL */ - 0x00000303 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451400 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0000003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000015 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000042 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x0000f2f3 /* EMC_CFG_PIPE */ - 0x80000370 /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000a /* EMC_QPOP */ - >; - }; - - timing-68000000 { - clock-frequency = <68000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000c000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000003 /* EMC_RC */ - 0x00000011 /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000002 /* EMC_RAS */ - 0x00000000 /* EMC_RP */ - 0x00000004 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000003 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000000 /* EMC_RD_RCD */ - 0x00000000 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000003 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000006 /* EMC_WDV */ - 0x00000006 /* EMC_WDV_MASK */ - 0x00000006 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000005 /* EMC_EINPUT */ - 0x00000005 /* EMC_EINPUT_DURATION */ - 0x00010000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000004 /* EMC_QRST */ - 0x0000000c /* EMC_QSAFE */ - 0x0000000d /* EMC_RDV */ - 0x0000000f /* EMC_RDV_MASK */ - 0x00000202 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000080 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x0000000f /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x00000013 /* EMC_TXSR */ - 0x00000013 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000001 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000005 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x00000213 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x106aa298 /* EMC_FBIO_CFG5 */ - 0x002c00a0 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00064000 /* EMC_DLL_XFORM_DQS0 */ - 0x00064000 /* EMC_DLL_XFORM_DQS1 */ - 0x00064000 /* EMC_DLL_XFORM_DQS2 */ - 0x00064000 /* EMC_DLL_XFORM_DQS3 */ - 0x00064000 /* EMC_DLL_XFORM_DQS4 */ - 0x00064000 /* EMC_DLL_XFORM_DQS5 */ - 0x00064000 /* EMC_DLL_XFORM_DQS6 */ - 0x00064000 /* EMC_DLL_XFORM_DQS7 */ - 0x00064000 /* EMC_DLL_XFORM_DQS8 */ - 0x00064000 /* EMC_DLL_XFORM_DQS9 */ - 0x00064000 /* EMC_DLL_XFORM_DQS10 */ - 0x00064000 /* EMC_DLL_XFORM_DQS11 */ - 0x00064000 /* EMC_DLL_XFORM_DQS12 */ - 0x00064000 /* EMC_DLL_XFORM_DQS13 */ - 0x00064000 /* EMC_DLL_XFORM_DQS14 */ - 0x00064000 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ - 0x10000280 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc081 /* EMC_XM2CLKPADCTRL */ - 0x00000303 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451400 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0000003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000022 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000042 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x0000f2f3 /* EMC_CFG_PIPE */ - 0x8000050e /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000a /* EMC_QPOP */ - >; - }; - - timing-102000000 { - clock-frequency = <102000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000c000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000004 /* EMC_RC */ - 0x0000001a /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000003 /* EMC_RAS */ - 0x00000001 /* EMC_RP */ - 0x00000004 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000003 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000001 /* EMC_RD_RCD */ - 0x00000001 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000003 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000006 /* EMC_WDV */ - 0x00000006 /* EMC_WDV_MASK */ - 0x00000006 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000005 /* EMC_EINPUT */ - 0x00000005 /* EMC_EINPUT_DURATION */ - 0x00010000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000004 /* EMC_QRST */ - 0x0000000c /* EMC_QSAFE */ - 0x0000000d /* EMC_RDV */ - 0x0000000f /* EMC_RDV_MASK */ - 0x00000304 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x000000c1 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000018 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x0000001c /* EMC_TXSR */ - 0x0000001c /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000003 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000005 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x0000031c /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x106aa298 /* EMC_FBIO_CFG5 */ - 0x002c00a0 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00064000 /* EMC_DLL_XFORM_DQS0 */ - 0x00064000 /* EMC_DLL_XFORM_DQS1 */ - 0x00064000 /* EMC_DLL_XFORM_DQS2 */ - 0x00064000 /* EMC_DLL_XFORM_DQS3 */ - 0x00064000 /* EMC_DLL_XFORM_DQS4 */ - 0x00064000 /* EMC_DLL_XFORM_DQS5 */ - 0x00064000 /* EMC_DLL_XFORM_DQS6 */ - 0x00064000 /* EMC_DLL_XFORM_DQS7 */ - 0x00064000 /* EMC_DLL_XFORM_DQS8 */ - 0x00064000 /* EMC_DLL_XFORM_DQS9 */ - 0x00064000 /* EMC_DLL_XFORM_DQS10 */ - 0x00064000 /* EMC_DLL_XFORM_DQS11 */ - 0x00064000 /* EMC_DLL_XFORM_DQS12 */ - 0x00064000 /* EMC_DLL_XFORM_DQS13 */ - 0x00064000 /* EMC_DLL_XFORM_DQS14 */ - 0x00064000 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ - 0x10000280 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc081 /* EMC_XM2CLKPADCTRL */ - 0x00000303 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451400 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0000003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000033 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000042 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x0000f2f3 /* EMC_CFG_PIPE */ - 0x80000713 /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000a /* EMC_QPOP */ - >; - }; - - timing-204000000 { - clock-frequency = <204000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x0000088d>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000c000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040008>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x00000009 /* EMC_RC */ - 0x00000035 /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000007 /* EMC_RAS */ - 0x00000002 /* EMC_RP */ - 0x00000005 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000003 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000002 /* EMC_RD_RCD */ - 0x00000002 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000003 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000005 /* EMC_WDV */ - 0x00000005 /* EMC_WDV_MASK */ - 0x00000006 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000004 /* EMC_EINPUT */ - 0x00000006 /* EMC_EINPUT_DURATION */ - 0x00010000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000003 /* EMC_QRST */ - 0x0000000d /* EMC_QSAFE */ - 0x0000000f /* EMC_RDV */ - 0x00000011 /* EMC_RDV_MASK */ - 0x00000607 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000181 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000032 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x00000038 /* EMC_TXSR */ - 0x00000038 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000007 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000005 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x00000638 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x106aa298 /* EMC_FBIO_CFG5 */ - 0x002c00a0 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00064000 /* EMC_DLL_XFORM_DQS0 */ - 0x00064000 /* EMC_DLL_XFORM_DQS1 */ - 0x00064000 /* EMC_DLL_XFORM_DQS2 */ - 0x00064000 /* EMC_DLL_XFORM_DQS3 */ - 0x00064000 /* EMC_DLL_XFORM_DQS4 */ - 0x00064000 /* EMC_DLL_XFORM_DQS5 */ - 0x00064000 /* EMC_DLL_XFORM_DQS6 */ - 0x00064000 /* EMC_DLL_XFORM_DQS7 */ - 0x00064000 /* EMC_DLL_XFORM_DQS8 */ - 0x00064000 /* EMC_DLL_XFORM_DQS9 */ - 0x00064000 /* EMC_DLL_XFORM_DQS10 */ - 0x00064000 /* EMC_DLL_XFORM_DQS11 */ - 0x00064000 /* EMC_DLL_XFORM_DQS12 */ - 0x00064000 /* EMC_DLL_XFORM_DQS13 */ - 0x00064000 /* EMC_DLL_XFORM_DQS14 */ - 0x00064000 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ - 0x00090000 /* EMC_DLL_XFORM_DQ0 */ - 0x00090000 /* EMC_DLL_XFORM_DQ1 */ - 0x00094000 /* EMC_DLL_XFORM_DQ2 */ - 0x00094000 /* EMC_DLL_XFORM_DQ3 */ - 0x00009400 /* EMC_DLL_XFORM_DQ4 */ - 0x00009000 /* EMC_DLL_XFORM_DQ5 */ - 0x00009000 /* EMC_DLL_XFORM_DQ6 */ - 0x00009000 /* EMC_DLL_XFORM_DQ7 */ - 0x10000280 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc081 /* EMC_XM2CLKPADCTRL */ - 0x00000303 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451400 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0000003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000066 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x0000d2b3 /* EMC_CFG_PIPE */ - 0x80000d22 /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000a /* EMC_QPOP */ - >; - }; - - timing-300000000 { - clock-frequency = <300000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73340000>; - nvidia,emc-cfg-2 = <0x000008d5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200000>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000321>; - nvidia,emc-mrs-wait-cnt = <0x0174000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x01231339>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x0000000d /* EMC_RC */ - 0x0000004c /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000009 /* EMC_RAS */ - 0x00000003 /* EMC_RP */ - 0x00000004 /* EMC_R2W */ - 0x00000008 /* EMC_W2R */ - 0x00000002 /* EMC_R2P */ - 0x00000009 /* EMC_W2P */ - 0x00000003 /* EMC_RD_RCD */ - 0x00000003 /* EMC_WR_RCD */ - 0x00000002 /* EMC_RRD */ - 0x00000002 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000003 /* EMC_WDV */ - 0x00000003 /* EMC_WDV_MASK */ - 0x00000005 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000002 /* EMC_EINPUT */ - 0x00000007 /* EMC_EINPUT_DURATION */ - 0x00020000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000001 /* EMC_QRST */ - 0x0000000e /* EMC_QSAFE */ - 0x00000010 /* EMC_RDV */ - 0x00000012 /* EMC_RDV_MASK */ - 0x000008e4 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000239 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000001 /* EMC_PDEX2WR */ - 0x00000008 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x0000004a /* EMC_AR2PDEN */ - 0x0000000e /* EMC_RW2PDEN */ - 0x00000051 /* EMC_TXSR */ - 0x00000200 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000009 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000005 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x00000924 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x104ab098 /* EMC_FBIO_CFG5 */ - 0x002c00a0 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00030000 /* EMC_DLL_XFORM_DQS0 */ - 0x00030000 /* EMC_DLL_XFORM_DQS1 */ - 0x00030000 /* EMC_DLL_XFORM_DQS2 */ - 0x00030000 /* EMC_DLL_XFORM_DQS3 */ - 0x00030000 /* EMC_DLL_XFORM_DQS4 */ - 0x00030000 /* EMC_DLL_XFORM_DQS5 */ - 0x00030000 /* EMC_DLL_XFORM_DQS6 */ - 0x00030000 /* EMC_DLL_XFORM_DQS7 */ - 0x00030000 /* EMC_DLL_XFORM_DQS8 */ - 0x00030000 /* EMC_DLL_XFORM_DQS9 */ - 0x00030000 /* EMC_DLL_XFORM_DQS10 */ - 0x00030000 /* EMC_DLL_XFORM_DQS11 */ - 0x00030000 /* EMC_DLL_XFORM_DQS12 */ - 0x00030000 /* EMC_DLL_XFORM_DQS13 */ - 0x00030000 /* EMC_DLL_XFORM_DQS14 */ - 0x00030000 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00098000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00098000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00098000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00098000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ - 0x00060000 /* EMC_DLL_XFORM_DQ0 */ - 0x00060000 /* EMC_DLL_XFORM_DQ1 */ - 0x00060000 /* EMC_DLL_XFORM_DQ2 */ - 0x00060000 /* EMC_DLL_XFORM_DQ3 */ - 0x00006000 /* EMC_DLL_XFORM_DQ4 */ - 0x00006000 /* EMC_DLL_XFORM_DQ5 */ - 0x00006000 /* EMC_DLL_XFORM_DQ6 */ - 0x00006000 /* EMC_DLL_XFORM_DQ7 */ - 0x10000280 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc081 /* EMC_XM2CLKPADCTRL */ - 0x00000101 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451420 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0000003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000096 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x0174000c /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x000052a3 /* EMC_CFG_PIPE */ - 0x800012d7 /* EMC_DYN_SELF_REF_CONTROL */ - 0x00000009 /* EMC_QPOP */ - >; - }; - - timing-396000000 { - clock-frequency = <396000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73340000>; - nvidia,emc-cfg-2 = <0x00000895>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200000>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000521>; - nvidia,emc-mrs-wait-cnt = <0x015b000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040008>; - nvidia,emc-xm2dqspadctrl2 = <0x01231339>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x00000012 /* EMC_RC */ - 0x00000065 /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x0000000c /* EMC_RAS */ - 0x00000004 /* EMC_RP */ - 0x00000005 /* EMC_R2W */ - 0x00000008 /* EMC_W2R */ - 0x00000002 /* EMC_R2P */ - 0x0000000a /* EMC_W2P */ - 0x00000004 /* EMC_RD_RCD */ - 0x00000004 /* EMC_WR_RCD */ - 0x00000002 /* EMC_RRD */ - 0x00000002 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000003 /* EMC_WDV */ - 0x00000003 /* EMC_WDV_MASK */ - 0x00000005 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000001 /* EMC_EINPUT */ - 0x00000008 /* EMC_EINPUT_DURATION */ - 0x00020000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000000 /* EMC_QRST */ - 0x0000000f /* EMC_QSAFE */ - 0x00000010 /* EMC_RDV */ - 0x00000012 /* EMC_RDV_MASK */ - 0x00000bd1 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x000002f4 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000001 /* EMC_PDEX2WR */ - 0x00000008 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000063 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x0000006b /* EMC_TXSR */ - 0x00000200 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x0000000d /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000005 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x00000c11 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x104ab098 /* EMC_FBIO_CFG5 */ - 0x002c00a0 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00030000 /* EMC_DLL_XFORM_DQS0 */ - 0x00030000 /* EMC_DLL_XFORM_DQS1 */ - 0x00030000 /* EMC_DLL_XFORM_DQS2 */ - 0x00030000 /* EMC_DLL_XFORM_DQS3 */ - 0x00030000 /* EMC_DLL_XFORM_DQS4 */ - 0x00030000 /* EMC_DLL_XFORM_DQS5 */ - 0x00030000 /* EMC_DLL_XFORM_DQS6 */ - 0x00030000 /* EMC_DLL_XFORM_DQS7 */ - 0x00030000 /* EMC_DLL_XFORM_DQS8 */ - 0x00030000 /* EMC_DLL_XFORM_DQS9 */ - 0x00030000 /* EMC_DLL_XFORM_DQS10 */ - 0x00030000 /* EMC_DLL_XFORM_DQS11 */ - 0x00030000 /* EMC_DLL_XFORM_DQS12 */ - 0x00030000 /* EMC_DLL_XFORM_DQS13 */ - 0x00030000 /* EMC_DLL_XFORM_DQS14 */ - 0x00030000 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00070000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00070000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00070000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00070000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ - 0x00048000 /* EMC_DLL_XFORM_DQ0 */ - 0x00048000 /* EMC_DLL_XFORM_DQ1 */ - 0x00048000 /* EMC_DLL_XFORM_DQ2 */ - 0x00048000 /* EMC_DLL_XFORM_DQ3 */ - 0x00004800 /* EMC_DLL_XFORM_DQ4 */ - 0x00004800 /* EMC_DLL_XFORM_DQ5 */ - 0x00004800 /* EMC_DLL_XFORM_DQ6 */ - 0x00004800 /* EMC_DLL_XFORM_DQ7 */ - 0x10000280 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc081 /* EMC_XM2CLKPADCTRL */ - 0x00000101 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451420 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0000003f /* EMC_DSR_VTTGEN_DRV */ - 0x000000c6 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x015b000c /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x000052a3 /* EMC_CFG_PIPE */ - 0x8000188b /* EMC_DYN_SELF_REF_CONTROL */ - 0x00000009 /* EMC_QPOP */ - >; - }; - - timing-528000000 { - clock-frequency = <528000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73300000>; - nvidia,emc-cfg-2 = <0x0000089d>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000941>; - nvidia,emc-mrs-wait-cnt = <0x013a000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040008>; - nvidia,emc-xm2dqspadctrl2 = <0x0123133d>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x00000018 /* EMC_RC */ - 0x00000088 /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000011 /* EMC_RAS */ - 0x00000006 /* EMC_RP */ - 0x00000006 /* EMC_R2W */ - 0x00000009 /* EMC_W2R */ - 0x00000002 /* EMC_R2P */ - 0x0000000d /* EMC_W2P */ - 0x00000006 /* EMC_RD_RCD */ - 0x00000006 /* EMC_WR_RCD */ - 0x00000002 /* EMC_RRD */ - 0x00000002 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000003 /* EMC_WDV */ - 0x00000003 /* EMC_WDV_MASK */ - 0x00000007 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000002 /* EMC_EINPUT */ - 0x00000009 /* EMC_EINPUT_DURATION */ - 0x00040000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000001 /* EMC_QRST */ - 0x00000010 /* EMC_QSAFE */ - 0x00000013 /* EMC_RDV */ - 0x00000015 /* EMC_RDV_MASK */ - 0x00000fd6 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x000003f5 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x0000000b /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000084 /* EMC_AR2PDEN */ - 0x00000012 /* EMC_RW2PDEN */ - 0x0000008f /* EMC_TXSR */ - 0x00000200 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000013 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000006 /* EMC_TCLKSTABLE */ - 0x00000006 /* EMC_TCLKSTOP */ - 0x00001017 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x104ab098 /* EMC_FBIO_CFG5 */ - 0xe01200b1 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x0000000a /* EMC_DLL_XFORM_DQS0 */ - 0x0000000a /* EMC_DLL_XFORM_DQS1 */ - 0x0000000a /* EMC_DLL_XFORM_DQS2 */ - 0x0000000a /* EMC_DLL_XFORM_DQS3 */ - 0x0000000a /* EMC_DLL_XFORM_DQS4 */ - 0x0000000a /* EMC_DLL_XFORM_DQS5 */ - 0x0000000a /* EMC_DLL_XFORM_DQS6 */ - 0x0000000a /* EMC_DLL_XFORM_DQS7 */ - 0x0000000a /* EMC_DLL_XFORM_DQS8 */ - 0x0000000a /* EMC_DLL_XFORM_DQS9 */ - 0x0000000a /* EMC_DLL_XFORM_DQS10 */ - 0x0000000a /* EMC_DLL_XFORM_DQS11 */ - 0x0000000a /* EMC_DLL_XFORM_DQS12 */ - 0x0000000a /* EMC_DLL_XFORM_DQS13 */ - 0x0000000a /* EMC_DLL_XFORM_DQS14 */ - 0x0000000a /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00050000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00050000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00050000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00050000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000002 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000002 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000003 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000004 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000001 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000004 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000003 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000002 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000002 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000003 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000004 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000001 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000004 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000003 /* EMC_DLI_TRIM_TXDQS15 */ - 0x0000000e /* EMC_DLL_XFORM_DQ0 */ - 0x0000000e /* EMC_DLL_XFORM_DQ1 */ - 0x0000000e /* EMC_DLL_XFORM_DQ2 */ - 0x0000000e /* EMC_DLL_XFORM_DQ3 */ - 0x0000000e /* EMC_DLL_XFORM_DQ4 */ - 0x0000000e /* EMC_DLL_XFORM_DQ5 */ - 0x0000000e /* EMC_DLL_XFORM_DQ6 */ - 0x0000000e /* EMC_DLL_XFORM_DQ7 */ - 0x100002a0 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc085 /* EMC_XM2CLKPADCTRL */ - 0x00000101 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451420 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0606003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000000 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x013a000c /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x000042a0 /* EMC_CFG_PIPE */ - 0x80002062 /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000b /* EMC_QPOP */ - >; - }; - - timing-600000000 { - clock-frequency = <600000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73300000>; - nvidia,emc-cfg-2 = <0x0000089d>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200010>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000b61>; - nvidia,emc-mrs-wait-cnt = <0x0128000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040008>; - nvidia,emc-xm2dqspadctrl2 = <0x0121113d>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x0000001c /* EMC_RC */ - 0x0000009a /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000013 /* EMC_RAS */ - 0x00000007 /* EMC_RP */ - 0x00000007 /* EMC_R2W */ - 0x0000000b /* EMC_W2R */ - 0x00000003 /* EMC_R2P */ - 0x00000010 /* EMC_W2P */ - 0x00000007 /* EMC_RD_RCD */ - 0x00000007 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000002 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000005 /* EMC_WDV */ - 0x00000005 /* EMC_WDV_MASK */ - 0x0000000a /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000003 /* EMC_EINPUT */ - 0x0000000b /* EMC_EINPUT_DURATION */ - 0x00070000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000002 /* EMC_QRST */ - 0x00000012 /* EMC_QSAFE */ - 0x00000016 /* EMC_RDV */ - 0x00000018 /* EMC_RDV_MASK */ - 0x00001208 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000482 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x0000000d /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000096 /* EMC_AR2PDEN */ - 0x00000015 /* EMC_RW2PDEN */ - 0x000000a2 /* EMC_TXSR */ - 0x00000200 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000015 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000006 /* EMC_TCLKSTABLE */ - 0x00000006 /* EMC_TCLKSTOP */ - 0x00001249 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x104ab098 /* EMC_FBIO_CFG5 */ - 0xe00e00b1 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x0000000a /* EMC_DLL_XFORM_DQS0 */ - 0x0000000a /* EMC_DLL_XFORM_DQS1 */ - 0x0000000a /* EMC_DLL_XFORM_DQS2 */ - 0x0000000a /* EMC_DLL_XFORM_DQS3 */ - 0x0000000a /* EMC_DLL_XFORM_DQS4 */ - 0x0000000a /* EMC_DLL_XFORM_DQS5 */ - 0x0000000a /* EMC_DLL_XFORM_DQS6 */ - 0x0000000a /* EMC_DLL_XFORM_DQS7 */ - 0x0000000a /* EMC_DLL_XFORM_DQS8 */ - 0x0000000a /* EMC_DLL_XFORM_DQS9 */ - 0x0000000a /* EMC_DLL_XFORM_DQS10 */ - 0x0000000a /* EMC_DLL_XFORM_DQS11 */ - 0x0000000a /* EMC_DLL_XFORM_DQS12 */ - 0x0000000a /* EMC_DLL_XFORM_DQS13 */ - 0x0000000a /* EMC_DLL_XFORM_DQS14 */ - 0x0000000a /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00048000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00048000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00048000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00048000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000004 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000004 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000002 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000005 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000006 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000003 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000006 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000005 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000004 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000004 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000002 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000005 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000006 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000003 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000006 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000005 /* EMC_DLI_TRIM_TXDQS15 */ - 0x0000000e /* EMC_DLL_XFORM_DQ0 */ - 0x0000000e /* EMC_DLL_XFORM_DQ1 */ - 0x0000000e /* EMC_DLL_XFORM_DQ2 */ - 0x0000000e /* EMC_DLL_XFORM_DQ3 */ - 0x0000000e /* EMC_DLL_XFORM_DQ4 */ - 0x0000000e /* EMC_DLL_XFORM_DQ5 */ - 0x0000000e /* EMC_DLL_XFORM_DQ6 */ - 0x0000000e /* EMC_DLL_XFORM_DQ7 */ - 0x100002a0 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc085 /* EMC_XM2CLKPADCTRL */ - 0x00000101 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451420 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0606003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000000 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x0128000c /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x000040a0 /* EMC_CFG_PIPE */ - 0x800024aa /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000e /* EMC_QPOP */ - >; - }; - - timing-792000000 { - clock-frequency = <792000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73300000>; - nvidia,emc-cfg-2 = <0x0080089d>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200418>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000d71>; - nvidia,emc-mrs-wait-cnt = <0x00f8000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040000>; - nvidia,emc-xm2dqspadctrl2 = <0x0120113d>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x00000025 /* EMC_RC */ - 0x000000cc /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x0000001a /* EMC_RAS */ - 0x00000009 /* EMC_RP */ - 0x00000008 /* EMC_R2W */ - 0x0000000d /* EMC_W2R */ - 0x00000004 /* EMC_R2P */ - 0x00000013 /* EMC_W2P */ - 0x00000009 /* EMC_RD_RCD */ - 0x00000009 /* EMC_WR_RCD */ - 0x00000004 /* EMC_RRD */ - 0x00000002 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000006 /* EMC_WDV */ - 0x00000006 /* EMC_WDV_MASK */ - 0x0000000b /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000002 /* EMC_EINPUT */ - 0x0000000d /* EMC_EINPUT_DURATION */ - 0x00080000 /* EMC_PUTERM_EXTRA */ - 0x00000004 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000001 /* EMC_QRST */ - 0x00000014 /* EMC_QSAFE */ - 0x00000018 /* EMC_RDV */ - 0x0000001a /* EMC_RDV_MASK */ - 0x000017e2 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x000005f8 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000003 /* EMC_PDEX2WR */ - 0x00000011 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x000000c6 /* EMC_AR2PDEN */ - 0x00000018 /* EMC_RW2PDEN */ - 0x000000d6 /* EMC_TXSR */ - 0x00000200 /* EMC_TXSRDLL */ - 0x00000005 /* EMC_TCKE */ - 0x00000006 /* EMC_TCKESR */ - 0x00000005 /* EMC_TPD */ - 0x0000001d /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000008 /* EMC_TCLKSTABLE */ - 0x00000008 /* EMC_TCLKSTOP */ - 0x00001822 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x80000005 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x104ab198 /* EMC_FBIO_CFG5 */ - 0xe00700b1 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00000009 /* EMC_DLL_XFORM_DQS0 */ - 0x00000009 /* EMC_DLL_XFORM_DQS1 */ - 0x00000009 /* EMC_DLL_XFORM_DQS2 */ - 0x00000007 /* EMC_DLL_XFORM_DQS3 */ - 0x00000006 /* EMC_DLL_XFORM_DQS4 */ - 0x00000006 /* EMC_DLL_XFORM_DQS5 */ - 0x007fc009 /* EMC_DLL_XFORM_DQS6 */ - 0x00000006 /* EMC_DLL_XFORM_DQS7 */ - 0x00000009 /* EMC_DLL_XFORM_DQS8 */ - 0x00000009 /* EMC_DLL_XFORM_DQS9 */ - 0x00000009 /* EMC_DLL_XFORM_DQS10 */ - 0x00000007 /* EMC_DLL_XFORM_DQS11 */ - 0x00000006 /* EMC_DLL_XFORM_DQS12 */ - 0x00000007 /* EMC_DLL_XFORM_DQS13 */ - 0x00000009 /* EMC_DLL_XFORM_DQS14 */ - 0x00000007 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00034002 /* EMC_DLL_XFORM_ADDR0 */ - 0x00034002 /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00034002 /* EMC_DLL_XFORM_ADDR3 */ - 0x00034002 /* EMC_DLL_XFORM_ADDR4 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000008 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000008 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000005 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000009 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000009 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000007 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000009 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000008 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000008 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000008 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000005 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000009 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000009 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000007 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000009 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000008 /* EMC_DLI_TRIM_TXDQS15 */ - 0x0000000e /* EMC_DLL_XFORM_DQ0 */ - 0x0000000e /* EMC_DLL_XFORM_DQ1 */ - 0x0000000e /* EMC_DLL_XFORM_DQ2 */ - 0x0000000e /* EMC_DLL_XFORM_DQ3 */ - 0x0000000e /* EMC_DLL_XFORM_DQ4 */ - 0x0000000e /* EMC_DLL_XFORM_DQ5 */ - 0x0000000e /* EMC_DLL_XFORM_DQ6 */ - 0x0000000e /* EMC_DLL_XFORM_DQ7 */ - 0x100002a0 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc085 /* EMC_XM2CLKPADCTRL */ - 0x00000101 /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x61861820 /* EMC_XM2DQSPADCTRL3 */ - 0x004d34d3 /* EMC_XM2DQSPADCTRL4 */ - 0x004d34d3 /* EMC_XM2DQSPADCTRL5 */ - 0x61861800 /* EMC_XM2DQSPADCTRL6 */ - 0x0606003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000000 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000100 /* EMC_ZCAL_WAIT_CNT */ - 0x00f8000c /* EMC_MRS_WAIT_CNT2 */ - 0x00000007 /* EMC_CTT */ - 0x00000004 /* EMC_CTT_DURATION */ - 0x00004080 /* EMC_CFG_PIPE */ - 0x80003012 /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000f /* EMC_QPOP */ - >; - }; - }; - }; - - memory-controller@70019000 { - emc-timings-1 { - nvidia,ram-code = <1>; - - timing-12750000 { - clock-frequency = <12750000>; - - nvidia,emem-configuration = < - 0x40040001 /* MC_EMEM_ARB_CFG */ - 0x8000000a /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ - 0x77e30303 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-20400000 { - clock-frequency = <20400000>; - - nvidia,emem-configuration = < - 0x40020001 /* MC_EMEM_ARB_CFG */ - 0x80000012 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ - 0x76230303 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-40800000 { - clock-frequency = <40800000>; - - nvidia,emem-configuration = < - 0xa0000001 /* MC_EMEM_ARB_CFG */ - 0x80000017 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ - 0x74a30303 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-68000000 { - clock-frequency = <68000000>; - - nvidia,emem-configuration = < - 0x00000001 /* MC_EMEM_ARB_CFG */ - 0x8000001e /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ - 0x74230403 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-102000000 { - clock-frequency = <102000000>; - - nvidia,emem-configuration = < - 0x08000001 /* MC_EMEM_ARB_CFG */ - 0x80000026 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0403 /* MC_EMEM_ARB_DA_COVERS */ - 0x73c30504 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-204000000 { - clock-frequency = <204000000>; - - nvidia,emem-configuration = < - 0x01000003 /* MC_EMEM_ARB_CFG */ - 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000005 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000004 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06040203 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0405 /* MC_EMEM_ARB_DA_COVERS */ - 0x73840a06 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-300000000 { - clock-frequency = <300000000>; - - nvidia,emem-configuration = < - 0x08000004 /* MC_EMEM_ARB_CFG */ - 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000007 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000004 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000005 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000007 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06040202 /* MC_EMEM_ARB_DA_TURNS */ - 0x000b0607 /* MC_EMEM_ARB_DA_COVERS */ - 0x77450e08 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-396000000 { - clock-frequency = <396000000>; - - nvidia,emem-configuration = < - 0x0f000005 /* MC_EMEM_ARB_CFG */ - 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000009 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000005 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000007 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06040202 /* MC_EMEM_ARB_DA_TURNS */ - 0x000d0709 /* MC_EMEM_ARB_DA_COVERS */ - 0x7586120a /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-528000000 { - clock-frequency = <528000000>; - - nvidia,emem-configuration = < - 0x0f000007 /* MC_EMEM_ARB_CFG */ - 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RP */ - 0x0000000d /* MC_EMEM_ARB_TIMING_RC */ - 0x00000008 /* MC_EMEM_ARB_TIMING_RAS */ - 0x0000000a /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000009 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000005 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06050202 /* MC_EMEM_ARB_DA_TURNS */ - 0x0010090d /* MC_EMEM_ARB_DA_COVERS */ - 0x7428180e /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-600000000 { - clock-frequency = <600000000>; - - nvidia,emem-configuration = < - 0x00000009 /* MC_EMEM_ARB_CFG */ - 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000004 /* MC_EMEM_ARB_TIMING_RP */ - 0x0000000e /* MC_EMEM_ARB_TIMING_RC */ - 0x00000009 /* MC_EMEM_ARB_TIMING_RAS */ - 0x0000000b /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x0000000b /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000005 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000007 /* MC_EMEM_ARB_TIMING_W2R */ - 0x07050202 /* MC_EMEM_ARB_DA_TURNS */ - 0x00130b0e /* MC_EMEM_ARB_DA_COVERS */ - 0x73a91b0f /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-792000000 { - clock-frequency = <792000000>; - - nvidia,emem-configuration = < - 0x0e00000b /* MC_EMEM_ARB_CFG */ - 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000004 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000005 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000013 /* MC_EMEM_ARB_TIMING_RC */ - 0x0000000c /* MC_EMEM_ARB_TIMING_RAS */ - 0x0000000f /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x0000000c /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */ - 0x08060202 /* MC_EMEM_ARB_DA_TURNS */ - 0x00160d13 /* MC_EMEM_ARB_DA_COVERS */ - 0x734c2414 /* MC_EMEM_ARB_MISC0 */ - 0x70000f02 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - }; - - emc-timings-4 { - nvidia,ram-code = <4>; - - timing-12750000 { - clock-frequency = <12750000>; - - nvidia,emem-configuration = < - 0x40040001 /* MC_EMEM_ARB_CFG */ - 0x8000000a /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ - 0x77e30303 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-20400000 { - clock-frequency = <20400000>; - - nvidia,emem-configuration = < - 0x40020001 /* MC_EMEM_ARB_CFG */ - 0x80000012 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ - 0x77430303 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-40800000 { - clock-frequency = <40800000>; - - nvidia,emem-configuration = < - 0xa0000001 /* MC_EMEM_ARB_CFG */ - 0x80000017 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ - 0x75e30303 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-68000000 { - clock-frequency = <68000000>; - - nvidia,emem-configuration = < - 0x00000001 /* MC_EMEM_ARB_CFG */ - 0x8000001e /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ - 0x75430403 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-102000000 { - clock-frequency = <102000000>; - - nvidia,emem-configuration = < - 0x08000001 /* MC_EMEM_ARB_CFG */ - 0x80000026 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0503 /* MC_EMEM_ARB_DA_COVERS */ - 0x74e30504 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-204000000 { - clock-frequency = <204000000>; - - nvidia,emem-configuration = < - 0x01000003 /* MC_EMEM_ARB_CFG */ - 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000004 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000004 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06040203 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0504 /* MC_EMEM_ARB_DA_COVERS */ - 0x74a40a05 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-300000000 { - clock-frequency = <300000000>; - - nvidia,emem-configuration = < - 0x08000004 /* MC_EMEM_ARB_CFG */ - 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000007 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000004 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000005 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000007 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06040202 /* MC_EMEM_ARB_DA_TURNS */ - 0x000b0607 /* MC_EMEM_ARB_DA_COVERS */ - 0x77450e08 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-396000000 { - clock-frequency = <396000000>; - - nvidia,emem-configuration = < - 0x0f000005 /* MC_EMEM_ARB_CFG */ - 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000009 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000005 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000007 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06040202 /* MC_EMEM_ARB_DA_TURNS */ - 0x000d0709 /* MC_EMEM_ARB_DA_COVERS */ - 0x7586120a /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-528000000 { - clock-frequency = <528000000>; - - nvidia,emem-configuration = < - 0x0f000007 /* MC_EMEM_ARB_CFG */ - 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RP */ - 0x0000000c /* MC_EMEM_ARB_TIMING_RC */ - 0x00000007 /* MC_EMEM_ARB_TIMING_RAS */ - 0x0000000a /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000009 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000005 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06050202 /* MC_EMEM_ARB_DA_TURNS */ - 0x0010090c /* MC_EMEM_ARB_DA_COVERS */ - 0x7488180d /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-600000000 { - clock-frequency = <600000000>; - - nvidia,emem-configuration = < - 0x00000009 /* MC_EMEM_ARB_CFG */ - 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000004 /* MC_EMEM_ARB_TIMING_RP */ - 0x0000000e /* MC_EMEM_ARB_TIMING_RC */ - 0x00000009 /* MC_EMEM_ARB_TIMING_RAS */ - 0x0000000b /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x0000000b /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000005 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000007 /* MC_EMEM_ARB_TIMING_W2R */ - 0x07050202 /* MC_EMEM_ARB_DA_TURNS */ - 0x00130b0e /* MC_EMEM_ARB_DA_COVERS */ - 0x74691b0f /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-792000000 { - clock-frequency = <792000000>; - - nvidia,emem-configuration = < - 0x0e00000b /* MC_EMEM_ARB_CFG */ - 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000004 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000005 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000013 /* MC_EMEM_ARB_TIMING_RC */ - 0x0000000c /* MC_EMEM_ARB_TIMING_RAS */ - 0x0000000f /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x0000000c /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */ - 0x08060202 /* MC_EMEM_ARB_DA_TURNS */ - 0x00170e13 /* MC_EMEM_ARB_DA_COVERS */ - 0x746c2414 /* MC_EMEM_ARB_MISC0 */ - 0x70000f02 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - }; - - emc-timings-6 { - nvidia,ram-code = <6>; - - timing-12750000 { - clock-frequency = <12750000>; - - nvidia,emem-configuration = < - 0x40040001 /* MC_EMEM_ARB_CFG */ - 0x8000000a /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ - 0x77e30303 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-20400000 { - clock-frequency = <20400000>; - - nvidia,emem-configuration = < - 0x40020001 /* MC_EMEM_ARB_CFG */ - 0x80000012 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ - 0x76230303 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-40800000 { - clock-frequency = <40800000>; - - nvidia,emem-configuration = < - 0xa0000001 /* MC_EMEM_ARB_CFG */ - 0x80000017 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ - 0x74a30303 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-68000000 { - clock-frequency = <68000000>; - - nvidia,emem-configuration = < - 0x00000001 /* MC_EMEM_ARB_CFG */ - 0x8000001e /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ - 0x74230403 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-102000000 { - clock-frequency = <102000000>; - - nvidia,emem-configuration = < - 0x08000001 /* MC_EMEM_ARB_CFG */ - 0x80000026 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0403 /* MC_EMEM_ARB_DA_COVERS */ - 0x73c30504 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-204000000 { - clock-frequency = <204000000>; - - nvidia,emem-configuration = < - 0x01000003 /* MC_EMEM_ARB_CFG */ - 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000005 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000004 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06040203 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0405 /* MC_EMEM_ARB_DA_COVERS */ - 0x73840a06 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-300000000 { - clock-frequency = <300000000>; - - nvidia,emem-configuration = < - 0x08000004 /* MC_EMEM_ARB_CFG */ - 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000007 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000004 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000005 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000007 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06040202 /* MC_EMEM_ARB_DA_TURNS */ - 0x000b0607 /* MC_EMEM_ARB_DA_COVERS */ - 0x77450e08 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-396000000 { - clock-frequency = <396000000>; - - nvidia,emem-configuration = < - 0x0f000005 /* MC_EMEM_ARB_CFG */ - 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000009 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000005 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000007 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06040202 /* MC_EMEM_ARB_DA_TURNS */ - 0x000d0709 /* MC_EMEM_ARB_DA_COVERS */ - 0x7586120a /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-528000000 { - clock-frequency = <528000000>; - - nvidia,emem-configuration = < - 0x0f000007 /* MC_EMEM_ARB_CFG */ - 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RP */ - 0x0000000d /* MC_EMEM_ARB_TIMING_RC */ - 0x00000008 /* MC_EMEM_ARB_TIMING_RAS */ - 0x0000000a /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000009 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000005 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06050202 /* MC_EMEM_ARB_DA_TURNS */ - 0x0010090d /* MC_EMEM_ARB_DA_COVERS */ - 0x7428180e /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-600000000 { - clock-frequency = <600000000>; - - nvidia,emem-configuration = < - 0x00000009 /* MC_EMEM_ARB_CFG */ - 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000004 /* MC_EMEM_ARB_TIMING_RP */ - 0x0000000e /* MC_EMEM_ARB_TIMING_RC */ - 0x00000009 /* MC_EMEM_ARB_TIMING_RAS */ - 0x0000000b /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x0000000b /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000005 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000007 /* MC_EMEM_ARB_TIMING_W2R */ - 0x07050202 /* MC_EMEM_ARB_DA_TURNS */ - 0x00130b0e /* MC_EMEM_ARB_DA_COVERS */ - 0x73a91b0f /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - - timing-792000000 { - clock-frequency = <792000000>; - - nvidia,emem-configuration = < - 0x0e00000b /* MC_EMEM_ARB_CFG */ - 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000004 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000005 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000013 /* MC_EMEM_ARB_TIMING_RC */ - 0x0000000c /* MC_EMEM_ARB_TIMING_RAS */ - 0x0000000f /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x0000000c /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */ - 0x08060202 /* MC_EMEM_ARB_DA_TURNS */ - 0x00160d13 /* MC_EMEM_ARB_DA_COVERS */ - 0x734c2414 /* MC_EMEM_ARB_MISC0 */ - 0x70000f02 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/tegra124-nyan-big.dts b/sys/gnu/dts/arm/tegra124-nyan-big.dts deleted file mode 100644 index d97791b9895..00000000000 --- a/sys/gnu/dts/arm/tegra124-nyan-big.dts +++ /dev/null @@ -1,1343 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "tegra124-nyan.dtsi" - -#include "tegra124-nyan-big-emc.dtsi" - -/ { - model = "Acer Chromebook 13 CB5-311"; - compatible = "google,nyan-big-rev7", "google,nyan-big-rev6", - "google,nyan-big-rev5", "google,nyan-big-rev4", - "google,nyan-big-rev3", "google,nyan-big-rev2", - "google,nyan-big-rev1", "google,nyan-big-rev0", - "google,nyan-big", "google,nyan", "nvidia,tegra124"; - - panel: panel { - compatible = "auo,b133xtn01"; - - backlight = <&backlight>; - ddc-i2c-bus = <&dpaux>; - }; - - sdhci@700b0400 { /* SD Card on this bus */ - wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>; - }; - - sound { - compatible = "nvidia,tegra-audio-max98090-nyan-big", - "nvidia,tegra-audio-max98090-nyan", - "nvidia,tegra-audio-max98090"; - nvidia,model = "GoogleNyanBig"; - }; - - pinmux@70000868 { - pinctrl-names = "default"; - pinctrl-0 = <&pinmux_default>; - - pinmux_default: common { - clk_32k_out_pa0 { - nvidia,pins = "clk_32k_out_pa0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart3_cts_n_pa1 { - nvidia,pins = "uart3_cts_n_pa1"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap2_fs_pa2 { - nvidia,pins = "dap2_fs_pa2"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap2_sclk_pa3 { - nvidia,pins = "dap2_sclk_pa3"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap2_din_pa4 { - nvidia,pins = "dap2_din_pa4"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap2_dout_pa5 { - nvidia,pins = "dap2_dout_pa5"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_clk_pa6 { - nvidia,pins = "sdmmc3_clk_pa6"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_cmd_pa7 { - nvidia,pins = "sdmmc3_cmd_pa7"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pb0 { - nvidia,pins = "pb0"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pb1 { - nvidia,pins = "pb1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_dat3_pb4 { - nvidia,pins = "sdmmc3_dat3_pb4"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_dat2_pb5 { - nvidia,pins = "sdmmc3_dat2_pb5"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_dat1_pb6 { - nvidia,pins = "sdmmc3_dat1_pb6"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_dat0_pb7 { - nvidia,pins = "sdmmc3_dat0_pb7"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart3_rts_n_pc0 { - nvidia,pins = "uart3_rts_n_pc0"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2_txd_pc2 { - nvidia,pins = "uart2_txd_pc2"; - nvidia,function = "irda"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2_rxd_pc3 { - nvidia,pins = "uart2_rxd_pc3"; - nvidia,function = "irda"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gen1_i2c_scl_pc4 { - nvidia,pins = "gen1_i2c_scl_pc4"; - nvidia,function = "i2c1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gen1_i2c_sda_pc5 { - nvidia,pins = "gen1_i2c_sda_pc5"; - nvidia,function = "i2c1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pc7 { - nvidia,pins = "pc7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg0 { - nvidia,pins = "pg0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg1 { - nvidia,pins = "pg1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg2 { - nvidia,pins = "pg2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg3 { - nvidia,pins = "pg3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg4 { - nvidia,pins = "pg4"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg5 { - nvidia,pins = "pg5"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg6 { - nvidia,pins = "pg6"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg7 { - nvidia,pins = "pg7"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph0 { - nvidia,pins = "ph0"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph1 { - nvidia,pins = "ph1"; - nvidia,function = "pwm1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph2 { - nvidia,pins = "ph2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph3 { - nvidia,pins = "ph3"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph4 { - nvidia,pins = "ph4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph5 { - nvidia,pins = "ph5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph6 { - nvidia,pins = "ph6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph7 { - nvidia,pins = "ph7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi0 { - nvidia,pins = "pi0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi1 { - nvidia,pins = "pi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi2 { - nvidia,pins = "pi2"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi3 { - nvidia,pins = "pi3"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi4 { - nvidia,pins = "pi4"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi5 { - nvidia,pins = "pi5"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi6 { - nvidia,pins = "pi6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi7 { - nvidia,pins = "pi7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pj0 { - nvidia,pins = "pj0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pj2 { - nvidia,pins = "pj2"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2_cts_n_pj5 { - nvidia,pins = "uart2_cts_n_pj5"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2_rts_n_pj6 { - nvidia,pins = "uart2_rts_n_pj6"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pj7 { - nvidia,pins = "pj7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pk0 { - nvidia,pins = "pk0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pk1 { - nvidia,pins = "pk1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pk2 { - nvidia,pins = "pk2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pk3 { - nvidia,pins = "pk3"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pk4 { - nvidia,pins = "pk4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - spdif_out_pk5 { - nvidia,pins = "spdif_out_pk5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - spdif_in_pk6 { - nvidia,pins = "spdif_in_pk6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pk7 { - nvidia,pins = "pk7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap1_fs_pn0 { - nvidia,pins = "dap1_fs_pn0"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap1_din_pn1 { - nvidia,pins = "dap1_din_pn1"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap1_dout_pn2 { - nvidia,pins = "dap1_dout_pn2"; - nvidia,function = "i2s0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap1_sclk_pn3 { - nvidia,pins = "dap1_sclk_pn3"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - usb_vbus_en0_pn4 { - nvidia,pins = "usb_vbus_en0_pn4"; - nvidia,function = "usb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - usb_vbus_en1_pn5 { - nvidia,pins = "usb_vbus_en1_pn5"; - nvidia,function = "usb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - hdmi_int_pn7 { - nvidia,pins = "hdmi_int_pn7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,rcv-sel = ; - }; - ulpi_data7_po0 { - nvidia,pins = "ulpi_data7_po0"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data0_po1 { - nvidia,pins = "ulpi_data0_po1"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data1_po2 { - nvidia,pins = "ulpi_data1_po2"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data2_po3 { - nvidia,pins = "ulpi_data2_po3"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data3_po4 { - nvidia,pins = "ulpi_data3_po4"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data4_po5 { - nvidia,pins = "ulpi_data4_po5"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data5_po6 { - nvidia,pins = "ulpi_data5_po6"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data6_po7 { - nvidia,pins = "ulpi_data6_po7"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3_fs_pp0 { - nvidia,pins = "dap3_fs_pp0"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3_din_pp1 { - nvidia,pins = "dap3_din_pp1"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3_dout_pp2 { - nvidia,pins = "dap3_dout_pp2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3_sclk_pp3 { - nvidia,pins = "dap3_sclk_pp3"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap4_fs_pp4 { - nvidia,pins = "dap4_fs_pp4"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap4_din_pp5 { - nvidia,pins = "dap4_din_pp5"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap4_dout_pp6 { - nvidia,pins = "dap4_dout_pp6"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap4_sclk_pp7 { - nvidia,pins = "dap4_sclk_pp7"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col0_pq0 { - nvidia,pins = "kb_col0_pq0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col1_pq1 { - nvidia,pins = "kb_col1_pq1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col2_pq2 { - nvidia,pins = "kb_col2_pq2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col3_pq3 { - nvidia,pins = "kb_col3_pq3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col4_pq4 { - nvidia,pins = "kb_col4_pq4"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col5_pq5 { - nvidia,pins = "kb_col5_pq5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col6_pq6 { - nvidia,pins = "kb_col6_pq6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col7_pq7 { - nvidia,pins = "kb_col7_pq7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row0_pr0 { - nvidia,pins = "kb_row0_pr0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row1_pr1 { - nvidia,pins = "kb_row1_pr1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row2_pr2 { - nvidia,pins = "kb_row2_pr2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row3_pr3 { - nvidia,pins = "kb_row3_pr3"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row4_pr4 { - nvidia,pins = "kb_row4_pr4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row5_pr5 { - nvidia,pins = "kb_row5_pr5"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row6_pr6 { - nvidia,pins = "kb_row6_pr6"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row7_pr7 { - nvidia,pins = "kb_row7_pr7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row8_ps0 { - nvidia,pins = "kb_row8_ps0"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row9_ps1 { - nvidia,pins = "kb_row9_ps1"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row10_ps2 { - nvidia,pins = "kb_row10_ps2"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row11_ps3 { - nvidia,pins = "kb_row11_ps3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row12_ps4 { - nvidia,pins = "kb_row12_ps4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row13_ps5 { - nvidia,pins = "kb_row13_ps5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row14_ps6 { - nvidia,pins = "kb_row14_ps6"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row15_ps7 { - nvidia,pins = "kb_row15_ps7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row16_pt0 { - nvidia,pins = "kb_row16_pt0"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row17_pt1 { - nvidia,pins = "kb_row17_pt1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gen2_i2c_scl_pt5 { - nvidia,pins = "gen2_i2c_scl_pt5"; - nvidia,function = "i2c2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gen2_i2c_sda_pt6 { - nvidia,pins = "gen2_i2c_sda_pt6"; - nvidia,function = "i2c2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc4_cmd_pt7 { - nvidia,pins = "sdmmc4_cmd_pt7"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu0 { - nvidia,pins = "pu0"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu1 { - nvidia,pins = "pu1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu2 { - nvidia,pins = "pu2"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu3 { - nvidia,pins = "pu3"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu4 { - nvidia,pins = "pu4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu5 { - nvidia,pins = "pu5"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu6 { - nvidia,pins = "pu6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pv0 { - nvidia,pins = "pv0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pv1 { - nvidia,pins = "pv1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_cd_n_pv2 { - nvidia,pins = "sdmmc3_cd_n_pv2"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_wp_n_pv3 { - nvidia,pins = "sdmmc1_wp_n_pv3"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ddc_scl_pv4 { - nvidia,pins = "ddc_scl_pv4"; - nvidia,function = "i2c4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,rcv-sel = ; - }; - ddc_sda_pv5 { - nvidia,pins = "ddc_sda_pv5"; - nvidia,function = "i2c4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,rcv-sel = ; - }; - gpio_w2_aud_pw2 { - nvidia,pins = "gpio_w2_aud_pw2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_w3_aud_pw3 { - nvidia,pins = "gpio_w3_aud_pw3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap_mclk1_pw4 { - nvidia,pins = "dap_mclk1_pw4"; - nvidia,function = "extperiph1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk2_out_pw5 { - nvidia,pins = "clk2_out_pw5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart3_txd_pw6 { - nvidia,pins = "uart3_txd_pw6"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart3_rxd_pw7 { - nvidia,pins = "uart3_rxd_pw7"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dvfs_pwm_px0 { - nvidia,pins = "dvfs_pwm_px0"; - nvidia,function = "cldvfs"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_x1_aud_px1 { - nvidia,pins = "gpio_x1_aud_px1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dvfs_clk_px2 { - nvidia,pins = "dvfs_clk_px2"; - nvidia,function = "cldvfs"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_x3_aud_px3 { - nvidia,pins = "gpio_x3_aud_px3"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_x4_aud_px4 { - nvidia,pins = "gpio_x4_aud_px4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_x5_aud_px5 { - nvidia,pins = "gpio_x5_aud_px5"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_x6_aud_px6 { - nvidia,pins = "gpio_x6_aud_px6"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_x7_aud_px7 { - nvidia,pins = "gpio_x7_aud_px7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_clk_py0 { - nvidia,pins = "ulpi_clk_py0"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_dir_py1 { - nvidia,pins = "ulpi_dir_py1"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_nxt_py2 { - nvidia,pins = "ulpi_nxt_py2"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_stp_py3 { - nvidia,pins = "ulpi_stp_py3"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_dat3_py4 { - nvidia,pins = "sdmmc1_dat3_py4"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_dat2_py5 { - nvidia,pins = "sdmmc1_dat2_py5"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_dat1_py6 { - nvidia,pins = "sdmmc1_dat1_py6"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_dat0_py7 { - nvidia,pins = "sdmmc1_dat0_py7"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_clk_pz0 { - nvidia,pins = "sdmmc1_clk_pz0"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_cmd_pz1 { - nvidia,pins = "sdmmc1_cmd_pz1"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pwr_i2c_scl_pz6 { - nvidia,pins = "pwr_i2c_scl_pz6"; - nvidia,function = "i2cpwr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pwr_i2c_sda_pz7 { - nvidia,pins = "pwr_i2c_sda_pz7"; - nvidia,function = "i2cpwr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc4_dat0_paa0 { - nvidia,pins = "sdmmc4_dat0_paa0"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_dat1_paa1 { - nvidia,pins = "sdmmc4_dat1_paa1"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_dat2_paa2 { - nvidia,pins = "sdmmc4_dat2_paa2"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_dat3_paa3 { - nvidia,pins = "sdmmc4_dat3_paa3"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_dat4_paa4 { - nvidia,pins = "sdmmc4_dat4_paa4"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_dat5_paa5 { - nvidia,pins = "sdmmc4_dat5_paa5"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_dat6_paa6 { - nvidia,pins = "sdmmc4_dat6_paa6"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_dat7_paa7 { - nvidia,pins = "sdmmc4_dat7_paa7"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pbb0 { - nvidia,pins = "pbb0"; - nvidia,function = "vgp6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - cam_i2c_scl_pbb1 { - nvidia,pins = "cam_i2c_scl_pbb1"; - nvidia,function = "i2c3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam_i2c_sda_pbb2 { - nvidia,pins = "cam_i2c_sda_pbb2"; - nvidia,function = "i2c3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pbb3 { - nvidia,pins = "pbb3"; - nvidia,function = "vgp3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pbb4 { - nvidia,pins = "pbb4"; - nvidia,function = "vgp4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pbb5 { - nvidia,pins = "pbb5"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pbb6 { - nvidia,pins = "pbb6"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pbb7 { - nvidia,pins = "pbb7"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - cam_mclk_pcc0 { - nvidia,pins = "cam_mclk_pcc0"; - nvidia,function = "vi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pcc1 { - nvidia,pins = "pcc1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pcc2 { - nvidia,pins = "pcc2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_clk_pcc4 { - nvidia,pins = "sdmmc4_clk_pcc4"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk2_req_pcc5 { - nvidia,pins = "clk2_req_pcc5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex_l0_rst_n_pdd1 { - nvidia,pins = "pex_l0_rst_n_pdd1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex_l0_clkreq_n_pdd2 { - nvidia,pins = "pex_l0_clkreq_n_pdd2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex_wake_n_pdd3 { - nvidia,pins = "pex_wake_n_pdd3"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex_l1_rst_n_pdd5 { - nvidia,pins = "pex_l1_rst_n_pdd5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex_l1_clkreq_n_pdd6 { - nvidia,pins = "pex_l1_clkreq_n_pdd6"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk3_out_pee0 { - nvidia,pins = "clk3_out_pee0"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk3_req_pee1 { - nvidia,pins = "clk3_req_pee1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap_mclk1_req_pee2 { - nvidia,pins = "dap_mclk1_req_pee2"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - hdmi_cec_pee3 { - nvidia,pins = "hdmi_cec_pee3"; - nvidia,function = "cec"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc3_clk_lb_out_pee4 { - nvidia,pins = "sdmmc3_clk_lb_out_pee4"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_clk_lb_in_pee5 { - nvidia,pins = "sdmmc3_clk_lb_in_pee5"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dp_hpd_pff0 { - nvidia,pins = "dp_hpd_pff0"; - nvidia,function = "dp"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - usb_vbus_en2_pff1 { - nvidia,pins = "usb_vbus_en2_pff1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pff2 { - nvidia,pins = "pff2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - core_pwr_req { - nvidia,pins = "core_pwr_req"; - nvidia,function = "pwron"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - cpu_pwr_req { - nvidia,pins = "cpu_pwr_req"; - nvidia,function = "cpu"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pwr_int_n { - nvidia,pins = "pwr_int_n"; - nvidia,function = "pmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - reset_out_n { - nvidia,pins = "reset_out_n"; - nvidia,function = "reset_out_n"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - owr { - nvidia,pins = "owr"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,rcv-sel = ; - }; - clk_32k_in { - nvidia,pins = "clk_32k_in"; - nvidia,function = "clk"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - jtag_rtck { - nvidia,pins = "jtag_rtck"; - nvidia,function = "rtck"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/tegra124-nyan-blaze-emc.dtsi b/sys/gnu/dts/arm/tegra124-nyan-blaze-emc.dtsi deleted file mode 100644 index d2beea0bd15..00000000000 --- a/sys/gnu/dts/arm/tegra124-nyan-blaze-emc.dtsi +++ /dev/null @@ -1,2050 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/ { - clock@60006000 { - emc-timings-1 { - nvidia,ram-code = <1>; - - timing-12750000 { - clock-frequency = <12750000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - timing-20400000 { - clock-frequency = <20400000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - timing-40800000 { - clock-frequency = <40800000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - timing-68000000 { - clock-frequency = <68000000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - timing-102000000 { - clock-frequency = <102000000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - timing-204000000 { - clock-frequency = <204000000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - timing-300000000 { - clock-frequency = <300000000>; - nvidia,parent-clock-frequency = <600000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_C>; - clock-names = "emc-parent"; - }; - timing-396000000 { - clock-frequency = <396000000>; - nvidia,parent-clock-frequency = <792000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_M>; - clock-names = "emc-parent"; - }; - /* TODO: Add 528MHz frequency */ - timing-600000000 { - clock-frequency = <600000000>; - nvidia,parent-clock-frequency = <600000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_C_UD>; - clock-names = "emc-parent"; - }; - timing-792000000 { - clock-frequency = <792000000>; - nvidia,parent-clock-frequency = <792000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; - clock-names = "emc-parent"; - }; - }; - }; - - external-memory-controller@7001b000 { - emc-timings-1 { - nvidia,ram-code = <1>; - - timing-12750000 { - clock-frequency = <12750000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000c000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000000 - 0x00000003 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000004 - 0x0000000a - 0x00000003 - 0x0000000b - 0x00000000 - 0x00000000 - 0x00000003 - 0x00000003 - 0x00000000 - 0x00000006 - 0x00000006 - 0x00000006 - 0x00000002 - 0x00000000 - 0x00000005 - 0x00000005 - 0x00010000 - 0x00000003 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000004 - 0x0000000c - 0x0000000d - 0x0000000f - 0x00000060 - 0x00000000 - 0x00000018 - 0x00000002 - 0x00000002 - 0x00000001 - 0x00000000 - 0x00000007 - 0x0000000f - 0x00000005 - 0x00000005 - 0x00000004 - 0x00000005 - 0x00000004 - 0x00000000 - 0x00000000 - 0x00000005 - 0x00000005 - 0x00000064 - 0x00000000 - 0x00000000 - 0x00000000 - 0x106aa298 - 0x002c00a0 - 0x00008000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x0000c000 - 0x00000000 - 0x00000000 - 0x0000c000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x000fc000 - 0x000fc000 - 0x000fc000 - 0x000fc000 - 0x0000fc00 - 0x0000fc00 - 0x0000fc00 - 0x0000fc00 - 0x10000280 - 0x00000000 - 0x00111111 - 0x00000000 - 0x00000000 - 0x77ffc081 - 0x00000505 - 0x81f1f108 - 0x07070004 - 0x0000003f - 0x016eeeee - 0x51451400 - 0x00514514 - 0x00514514 - 0x51451400 - 0x0000003f - 0x00000007 - 0x00000000 - 0x00000042 - 0x000c000c - 0x00000000 - 0x00000003 - 0x0000f2f3 - 0x800001c5 - 0x0000000a - >; - }; - - timing-20400000 { - clock-frequency = <20400000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000c000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000000 - 0x00000005 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000004 - 0x0000000a - 0x00000003 - 0x0000000b - 0x00000000 - 0x00000000 - 0x00000003 - 0x00000003 - 0x00000000 - 0x00000006 - 0x00000006 - 0x00000006 - 0x00000002 - 0x00000000 - 0x00000005 - 0x00000005 - 0x00010000 - 0x00000003 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000004 - 0x0000000c - 0x0000000d - 0x0000000f - 0x0000009a - 0x00000000 - 0x00000026 - 0x00000002 - 0x00000002 - 0x00000001 - 0x00000000 - 0x00000007 - 0x0000000f - 0x00000006 - 0x00000006 - 0x00000004 - 0x00000005 - 0x00000004 - 0x00000000 - 0x00000000 - 0x00000005 - 0x00000005 - 0x000000a0 - 0x00000000 - 0x00000000 - 0x00000000 - 0x106aa298 - 0x002c00a0 - 0x00008000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x0000c000 - 0x00000000 - 0x00000000 - 0x0000c000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x000fc000 - 0x000fc000 - 0x000fc000 - 0x000fc000 - 0x0000fc00 - 0x0000fc00 - 0x0000fc00 - 0x0000fc00 - 0x10000280 - 0x00000000 - 0x00111111 - 0x00000000 - 0x00000000 - 0x77ffc081 - 0x00000505 - 0x81f1f108 - 0x07070004 - 0x0000003f - 0x016eeeee - 0x51451400 - 0x00514514 - 0x00514514 - 0x51451400 - 0x0000003f - 0x0000000b - 0x00000000 - 0x00000042 - 0x000c000c - 0x00000000 - 0x00000003 - 0x0000f2f3 - 0x8000023a - 0x0000000a - >; - }; - - timing-40800000 { - clock-frequency = <40800000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000c000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000001 - 0x0000000a - 0x00000000 - 0x00000001 - 0x00000000 - 0x00000004 - 0x0000000a - 0x00000003 - 0x0000000b - 0x00000000 - 0x00000000 - 0x00000003 - 0x00000003 - 0x00000000 - 0x00000006 - 0x00000006 - 0x00000006 - 0x00000002 - 0x00000000 - 0x00000005 - 0x00000005 - 0x00010000 - 0x00000003 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000004 - 0x0000000c - 0x0000000d - 0x0000000f - 0x00000134 - 0x00000000 - 0x0000004d - 0x00000002 - 0x00000002 - 0x00000001 - 0x00000000 - 0x00000008 - 0x0000000f - 0x0000000c - 0x0000000c - 0x00000004 - 0x00000005 - 0x00000004 - 0x00000000 - 0x00000000 - 0x00000005 - 0x00000005 - 0x0000013f - 0x00000000 - 0x00000000 - 0x00000000 - 0x106aa298 - 0x002c00a0 - 0x00008000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x0000c000 - 0x00000000 - 0x00000000 - 0x0000c000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x000fc000 - 0x000fc000 - 0x000fc000 - 0x000fc000 - 0x0000fc00 - 0x0000fc00 - 0x0000fc00 - 0x0000fc00 - 0x10000280 - 0x00000000 - 0x00111111 - 0x00000000 - 0x00000000 - 0x77ffc081 - 0x00000505 - 0x81f1f108 - 0x07070004 - 0x0000003f - 0x016eeeee - 0x51451400 - 0x00514514 - 0x00514514 - 0x51451400 - 0x0000003f - 0x00000015 - 0x00000000 - 0x00000042 - 0x000c000c - 0x00000000 - 0x00000003 - 0x0000f2f3 - 0x80000370 - 0x0000000a - >; - }; - - timing-68000000 { - clock-frequency = <68000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000c000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000003 - 0x00000011 - 0x00000000 - 0x00000002 - 0x00000000 - 0x00000004 - 0x0000000a - 0x00000003 - 0x0000000b - 0x00000000 - 0x00000000 - 0x00000003 - 0x00000003 - 0x00000000 - 0x00000006 - 0x00000006 - 0x00000006 - 0x00000002 - 0x00000000 - 0x00000005 - 0x00000005 - 0x00010000 - 0x00000003 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000004 - 0x0000000c - 0x0000000d - 0x0000000f - 0x00000202 - 0x00000000 - 0x00000080 - 0x00000002 - 0x00000002 - 0x00000001 - 0x00000000 - 0x0000000f - 0x0000000f - 0x00000013 - 0x00000013 - 0x00000004 - 0x00000005 - 0x00000004 - 0x00000001 - 0x00000000 - 0x00000005 - 0x00000005 - 0x00000213 - 0x00000000 - 0x00000000 - 0x00000000 - 0x106aa298 - 0x002c00a0 - 0x00008000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x0000c000 - 0x00000000 - 0x00000000 - 0x0000c000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x000fc000 - 0x000fc000 - 0x000fc000 - 0x000fc000 - 0x0000fc00 - 0x0000fc00 - 0x0000fc00 - 0x0000fc00 - 0x10000280 - 0x00000000 - 0x00111111 - 0x00000000 - 0x00000000 - 0x77ffc081 - 0x00000505 - 0x81f1f108 - 0x07070004 - 0x0000003f - 0x016eeeee - 0x51451400 - 0x00514514 - 0x00514514 - 0x51451400 - 0x0000003f - 0x00000022 - 0x00000000 - 0x00000042 - 0x000c000c - 0x00000000 - 0x00000003 - 0x0000f2f3 - 0x8000050e - 0x0000000a - >; - }; - - timing-102000000 { - clock-frequency = <102000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000c000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000004 - 0x0000001a - 0x00000000 - 0x00000003 - 0x00000001 - 0x00000004 - 0x0000000a - 0x00000003 - 0x0000000b - 0x00000001 - 0x00000001 - 0x00000003 - 0x00000003 - 0x00000000 - 0x00000006 - 0x00000006 - 0x00000006 - 0x00000002 - 0x00000000 - 0x00000005 - 0x00000005 - 0x00010000 - 0x00000003 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000004 - 0x0000000c - 0x0000000d - 0x0000000f - 0x00000304 - 0x00000000 - 0x000000c1 - 0x00000002 - 0x00000002 - 0x00000001 - 0x00000000 - 0x00000018 - 0x0000000f - 0x0000001c - 0x0000001c - 0x00000004 - 0x00000005 - 0x00000004 - 0x00000003 - 0x00000000 - 0x00000005 - 0x00000005 - 0x0000031c - 0x00000000 - 0x00000000 - 0x00000000 - 0x106aa298 - 0x002c00a0 - 0x00008000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x0000c000 - 0x00000000 - 0x00000000 - 0x0000c000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x000fc000 - 0x000fc000 - 0x000fc000 - 0x000fc000 - 0x0000fc00 - 0x0000fc00 - 0x0000fc00 - 0x0000fc00 - 0x10000280 - 0x00000000 - 0x00111111 - 0x00000000 - 0x00000000 - 0x77ffc081 - 0x00000505 - 0x81f1f108 - 0x07070004 - 0x0000003f - 0x016eeeee - 0x51451400 - 0x00514514 - 0x00514514 - 0x51451400 - 0x0000003f - 0x00000033 - 0x00000000 - 0x00000042 - 0x000c000c - 0x00000000 - 0x00000003 - 0x0000f2f3 - 0x80000713 - 0x0000000a - >; - }; - - timing-204000000 { - clock-frequency = <204000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x0000088d>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000c000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040008>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x00000009 - 0x00000035 - 0x00000000 - 0x00000007 - 0x00000002 - 0x00000005 - 0x0000000a - 0x00000003 - 0x0000000b - 0x00000002 - 0x00000002 - 0x00000003 - 0x00000003 - 0x00000000 - 0x00000005 - 0x00000005 - 0x00000006 - 0x00000002 - 0x00000000 - 0x00000004 - 0x00000006 - 0x00010000 - 0x00000003 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000003 - 0x0000000d - 0x0000000f - 0x00000011 - 0x00000607 - 0x00000000 - 0x00000181 - 0x00000002 - 0x00000002 - 0x00000001 - 0x00000000 - 0x00000032 - 0x0000000f - 0x00000038 - 0x00000038 - 0x00000004 - 0x00000005 - 0x00000004 - 0x00000007 - 0x00000000 - 0x00000005 - 0x00000005 - 0x00000638 - 0x00000000 - 0x00000000 - 0x00000000 - 0x106aa298 - 0x002c00a0 - 0x00008000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x0000c000 - 0x00000000 - 0x00000000 - 0x0000c000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00090000 - 0x00090000 - 0x00090000 - 0x00090000 - 0x00009000 - 0x00009000 - 0x00009000 - 0x00009000 - 0x10000280 - 0x00000000 - 0x00111111 - 0x00000000 - 0x00000000 - 0x77ffc081 - 0x00000505 - 0x81f1f108 - 0x07070004 - 0x0000003f - 0x016eeeee - 0x51451400 - 0x00514514 - 0x00514514 - 0x51451400 - 0x0000003f - 0x00000066 - 0x00000000 - 0x00000100 - 0x000c000c - 0x00000000 - 0x00000003 - 0x0000d2b3 - 0x80000d22 - 0x0000000a - >; - }; - - timing-300000000 { - clock-frequency = <300000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73340000>; - nvidia,emc-cfg-2 = <0x000008d5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200000>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000321>; - nvidia,emc-mrs-wait-cnt = <0x0174000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x01231339>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x0000000d - 0x0000004c - 0x00000000 - 0x00000009 - 0x00000003 - 0x00000004 - 0x00000008 - 0x00000002 - 0x00000009 - 0x00000003 - 0x00000003 - 0x00000002 - 0x00000002 - 0x00000000 - 0x00000003 - 0x00000003 - 0x00000005 - 0x00000002 - 0x00000000 - 0x00000002 - 0x00000007 - 0x00020000 - 0x00000003 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000001 - 0x0000000e - 0x00000010 - 0x00000012 - 0x000008e4 - 0x00000000 - 0x00000239 - 0x00000001 - 0x00000008 - 0x00000001 - 0x00000000 - 0x0000004a - 0x0000000e - 0x00000051 - 0x00000200 - 0x00000004 - 0x00000005 - 0x00000004 - 0x00000009 - 0x00000000 - 0x00000005 - 0x00000005 - 0x00000924 - 0x00000000 - 0x00000000 - 0x00000000 - 0x104ab098 - 0x002c00a0 - 0x00008000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00090000 - 0x00090000 - 0x00000000 - 0x00090000 - 0x00090000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00060000 - 0x00060000 - 0x00060000 - 0x00060000 - 0x00006000 - 0x00006000 - 0x00006000 - 0x00006000 - 0x10000280 - 0x00000000 - 0x00111111 - 0x00000000 - 0x00000000 - 0x77ffc081 - 0x00000202 - 0x81f1f108 - 0x07070004 - 0x00000000 - 0x016eeeee - 0x51451420 - 0x00514514 - 0x00514514 - 0x51451400 - 0x0000003f - 0x00000096 - 0x00000000 - 0x00000100 - 0x0174000c - 0x00000000 - 0x00000003 - 0x000052a3 - 0x800012d7 - 0x00000009 - >; - }; - - timing-396000000 { - clock-frequency = <396000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73340000>; - nvidia,emc-cfg-2 = <0x00000895>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200000>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000521>; - nvidia,emc-mrs-wait-cnt = <0x015b000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040008>; - nvidia,emc-xm2dqspadctrl2 = <0x01231339>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x00000012 - 0x00000065 - 0x00000000 - 0x0000000c - 0x00000004 - 0x00000005 - 0x00000008 - 0x00000002 - 0x0000000a - 0x00000004 - 0x00000004 - 0x00000002 - 0x00000002 - 0x00000000 - 0x00000003 - 0x00000003 - 0x00000005 - 0x00000002 - 0x00000000 - 0x00000001 - 0x00000008 - 0x00020000 - 0x00000003 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x0000000f - 0x00000010 - 0x00000012 - 0x00000bd1 - 0x00000000 - 0x000002f4 - 0x00000001 - 0x00000008 - 0x00000001 - 0x00000000 - 0x00000063 - 0x0000000f - 0x0000006b - 0x00000200 - 0x00000004 - 0x00000005 - 0x00000004 - 0x0000000d - 0x00000000 - 0x00000005 - 0x00000005 - 0x00000c11 - 0x00000000 - 0x00000000 - 0x00000000 - 0x104ab098 - 0x002c00a0 - 0x00008000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00068000 - 0x00068000 - 0x00000000 - 0x00068000 - 0x00068000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00058000 - 0x00058000 - 0x00058000 - 0x00058000 - 0x00005800 - 0x00005800 - 0x00005800 - 0x00005800 - 0x10000280 - 0x00000000 - 0x00111111 - 0x00000000 - 0x00000000 - 0x77ffc081 - 0x00000202 - 0x81f1f108 - 0x07070004 - 0x00000000 - 0x016eeeee - 0x51451420 - 0x00514514 - 0x00514514 - 0x51451400 - 0x0000003f - 0x000000c6 - 0x00000000 - 0x00000100 - 0x015b000c - 0x00000000 - 0x00000003 - 0x000052a3 - 0x8000188b - 0x00000009 - >; - }; - - timing-600000000 { - clock-frequency = <600000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73300000>; - nvidia,emc-cfg-2 = <0x0000089d>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200010>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000b61>; - nvidia,emc-mrs-wait-cnt = <0x0128000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040008>; - nvidia,emc-xm2dqspadctrl2 = <0x0121113d>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x0000001c - 0x0000009a - 0x00000000 - 0x00000013 - 0x00000007 - 0x00000007 - 0x0000000b - 0x00000003 - 0x00000010 - 0x00000007 - 0x00000007 - 0x00000002 - 0x00000002 - 0x00000000 - 0x00000005 - 0x00000005 - 0x0000000a - 0x00000002 - 0x00000000 - 0x00000003 - 0x0000000b - 0x00070000 - 0x00000003 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000002 - 0x00000012 - 0x00000016 - 0x00000018 - 0x00001208 - 0x00000000 - 0x00000482 - 0x00000002 - 0x0000000d - 0x00000001 - 0x00000000 - 0x00000096 - 0x00000015 - 0x000000a2 - 0x00000200 - 0x00000004 - 0x00000005 - 0x00000004 - 0x00000015 - 0x00000000 - 0x00000006 - 0x00000006 - 0x00001248 - 0x00000000 - 0x00000000 - 0x00000000 - 0x104ab098 - 0xe00e00b1 - 0x00008000 - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00040000 - 0x00040000 - 0x00000000 - 0x00040000 - 0x00040000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000004 - 0x00000004 - 0x00000001 - 0x00000005 - 0x00000007 - 0x00000004 - 0x00000006 - 0x00000007 - 0x00000004 - 0x00000004 - 0x00000001 - 0x00000005 - 0x00000007 - 0x00000004 - 0x00000006 - 0x00000007 - 0x0000000e - 0x0000000e - 0x0000000e - 0x0000000e - 0x0000000e - 0x0000000e - 0x0000000e - 0x0000000e - 0x100002a0 - 0x00000000 - 0x00111111 - 0x00000000 - 0x00000000 - 0x77ffc085 - 0x00000202 - 0x81f1f108 - 0x07070004 - 0x00000000 - 0x016eeeee - 0x51451420 - 0x00514514 - 0x00514514 - 0x51451400 - 0x0606003f - 0x00000000 - 0x00000000 - 0x00000100 - 0x0128000c - 0x00000000 - 0x00000003 - 0x000040a0 - 0x800024a9 - 0x0000000e - >; - }; - - timing-792000000 { - clock-frequency = <792000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73300000>; - nvidia,emc-cfg-2 = <0x0000089d>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200018>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000d71>; - nvidia,emc-mrs-wait-cnt = <0x00f8000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040000>; - nvidia,emc-xm2dqspadctrl2 = <0x0120113d>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x00000025 - 0x000000cc - 0x00000000 - 0x0000001a - 0x00000009 - 0x00000008 - 0x0000000d - 0x00000004 - 0x00000013 - 0x00000009 - 0x00000009 - 0x00000003 - 0x00000002 - 0x00000000 - 0x00000006 - 0x00000006 - 0x0000000b - 0x00000002 - 0x00000000 - 0x00000002 - 0x0000000d - 0x00080000 - 0x00000004 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000001 - 0x00000014 - 0x00000018 - 0x0000001a - 0x000017e2 - 0x00000000 - 0x000005f8 - 0x00000003 - 0x00000011 - 0x00000001 - 0x00000000 - 0x000000c6 - 0x00000018 - 0x000000d6 - 0x00000200 - 0x00000005 - 0x00000006 - 0x00000005 - 0x0000001d - 0x00000000 - 0x00000008 - 0x00000008 - 0x00001822 - 0x00000000 - 0x00000000 - 0x00000000 - 0x104ab098 - 0xe00700b1 - 0x00008000 - 0x00000008 - 0x00000008 - 0x00000008 - 0x00000008 - 0x00000008 - 0x00000008 - 0x00000008 - 0x00000008 - 0x00000008 - 0x00000008 - 0x00000008 - 0x00000008 - 0x00000008 - 0x00000008 - 0x00000008 - 0x00000008 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x0002c000 - 0x0002c000 - 0x00000000 - 0x0002c000 - 0x0002c000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000008 - 0x00000008 - 0x00000005 - 0x00000008 - 0x0000000a - 0x00000008 - 0x0000000a - 0x0000000a - 0x00000008 - 0x00000008 - 0x00000005 - 0x00000008 - 0x0000000a - 0x00000008 - 0x0000000a - 0x0000000a - 0x0000000e - 0x0000000e - 0x0000000e - 0x0000000e - 0x0000000e - 0x0000000e - 0x0000000e - 0x0000000e - 0x100002a0 - 0x00000000 - 0x00111111 - 0x00000000 - 0x00000000 - 0x77ffc085 - 0x00000202 - 0x81f1f108 - 0x07070004 - 0x00000000 - 0x016eeeee - 0x61861820 - 0x00492492 - 0x00492492 - 0x61861800 - 0x0606003f - 0x00000000 - 0x00000000 - 0x00000100 - 0x00f8000c - 0x00000000 - 0x00000004 - 0x00004080 - 0x80003012 - 0x0000000f - >; - }; - - }; - }; - - memory-controller@70019000 { - emc-timings-1 { - nvidia,ram-code = <1>; - - - timing-12750000 { - clock-frequency = <12750000>; - - nvidia,emem-configuration = < - 0x40040001 - 0x8000000a - 0x00000001 - 0x00000001 - 0x00000002 - 0x00000000 - 0x00000002 - 0x00000001 - 0x00000002 - 0x00000008 - 0x00000003 - 0x00000002 - 0x00000003 - 0x00000006 - 0x06030203 - 0x000a0402 - 0x77e30303 - 0x70000f03 - 0x001f0000 - >; - }; - - timing-20400000 { - clock-frequency = <20400000>; - - nvidia,emem-configuration = < - 0x40020001 - 0x80000012 - 0x00000001 - 0x00000001 - 0x00000002 - 0x00000000 - 0x00000002 - 0x00000001 - 0x00000002 - 0x00000008 - 0x00000003 - 0x00000002 - 0x00000003 - 0x00000006 - 0x06030203 - 0x000a0402 - 0x76230303 - 0x70000f03 - 0x001f0000 - >; - }; - - timing-40800000 { - clock-frequency = <40800000>; - - nvidia,emem-configuration = < - 0xa0000001 - 0x80000017 - 0x00000001 - 0x00000001 - 0x00000002 - 0x00000000 - 0x00000002 - 0x00000001 - 0x00000002 - 0x00000008 - 0x00000003 - 0x00000002 - 0x00000003 - 0x00000006 - 0x06030203 - 0x000a0402 - 0x74a30303 - 0x70000f03 - 0x001f0000 - >; - }; - - timing-68000000 { - clock-frequency = <68000000>; - - nvidia,emem-configuration = < - 0x00000001 - 0x8000001e - 0x00000001 - 0x00000001 - 0x00000002 - 0x00000000 - 0x00000002 - 0x00000001 - 0x00000002 - 0x00000008 - 0x00000003 - 0x00000002 - 0x00000003 - 0x00000006 - 0x06030203 - 0x000a0402 - 0x74230403 - 0x70000f03 - 0x001f0000 - >; - }; - - timing-102000000 { - clock-frequency = <102000000>; - - nvidia,emem-configuration = < - 0x08000001 - 0x80000026 - 0x00000001 - 0x00000001 - 0x00000003 - 0x00000000 - 0x00000002 - 0x00000001 - 0x00000002 - 0x00000008 - 0x00000003 - 0x00000002 - 0x00000003 - 0x00000006 - 0x06030203 - 0x000a0403 - 0x73c30504 - 0x70000f03 - 0x001f0000 - >; - }; - - timing-204000000 { - clock-frequency = <204000000>; - - nvidia,emem-configuration = < - 0x01000003 - 0x80000040 - 0x00000001 - 0x00000001 - 0x00000005 - 0x00000002 - 0x00000004 - 0x00000001 - 0x00000002 - 0x00000008 - 0x00000003 - 0x00000002 - 0x00000004 - 0x00000006 - 0x06040203 - 0x000a0405 - 0x73840a06 - 0x70000f03 - 0x001f0000 - >; - }; - - timing-300000000 { - clock-frequency = <300000000>; - - nvidia,emem-configuration = < - 0x08000004 - 0x80000040 - 0x00000001 - 0x00000002 - 0x00000007 - 0x00000004 - 0x00000005 - 0x00000001 - 0x00000002 - 0x00000007 - 0x00000002 - 0x00000002 - 0x00000004 - 0x00000006 - 0x06040202 - 0x000b0607 - 0x77450e08 - 0x70000f03 - 0x001f0000 - >; - }; - - timing-396000000 { - clock-frequency = <396000000>; - - nvidia,emem-configuration = < - 0x0f000005 - 0x80000040 - 0x00000001 - 0x00000002 - 0x00000009 - 0x00000005 - 0x00000007 - 0x00000001 - 0x00000002 - 0x00000008 - 0x00000002 - 0x00000002 - 0x00000004 - 0x00000006 - 0x06040202 - 0x000d0709 - 0x7586120a - 0x70000f03 - 0x001f0000 - >; - }; - - timing-528000000 { - clock-frequency = <528000000>; - - nvidia,emem-configuration = < - 0x0f000007 - 0x80000040 - 0x00000002 - 0x00000003 - 0x0000000d - 0x00000008 - 0x0000000a - 0x00000001 - 0x00000002 - 0x00000009 - 0x00000002 - 0x00000002 - 0x00000005 - 0x00000006 - 0x06050202 - 0x0010090d - 0x7428180e - 0x70000f03 - 0x001f0000 - >; - }; - - timing-600000000 { - clock-frequency = <600000000>; - - nvidia,emem-configuration = < - 0x00000009 - 0x80000040 - 0x00000003 - 0x00000004 - 0x0000000e - 0x00000009 - 0x0000000b - 0x00000001 - 0x00000003 - 0x0000000b - 0x00000002 - 0x00000002 - 0x00000005 - 0x00000007 - 0x07050202 - 0x00130b0e - 0x73a91b0f - 0x70000f03 - 0x001f0000 - >; - }; - - timing-792000000 { - clock-frequency = <792000000>; - - nvidia,emem-configuration = < - 0x0e00000b - 0x80000040 - 0x00000004 - 0x00000005 - 0x00000013 - 0x0000000c - 0x0000000f - 0x00000002 - 0x00000003 - 0x0000000c - 0x00000002 - 0x00000002 - 0x00000006 - 0x00000008 - 0x08060202 - 0x00160d13 - 0x734c2414 - 0x70000f02 - 0x001f0000 - >; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/tegra124-nyan-blaze.dts b/sys/gnu/dts/arm/tegra124-nyan-blaze.dts deleted file mode 100644 index 2a029ee86dd..00000000000 --- a/sys/gnu/dts/arm/tegra124-nyan-blaze.dts +++ /dev/null @@ -1,1341 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "tegra124-nyan.dtsi" - -#include "tegra124-nyan-blaze-emc.dtsi" - -/ { - model = "HP Chromebook 14"; - compatible = "google,nyan-blaze-rev10", "google,nyan-blaze-rev9", - "google,nyan-blaze-rev8", "google,nyan-blaze-rev7", - "google,nyan-blaze-rev6", "google,nyan-blaze-rev5", - "google,nyan-blaze-rev4", "google,nyan-blaze-rev3", - "google,nyan-blaze-rev2", "google,nyan-blaze-rev1", - "google,nyan-blaze-rev0", "google,nyan-blaze", - "google,nyan", "nvidia,tegra124"; - - panel: panel { - compatible = "samsung,ltn140at29-301"; - - backlight = <&backlight>; - ddc-i2c-bus = <&dpaux>; - }; - - sound { - compatible = "nvidia,tegra-audio-max98090-nyan-blaze", - "nvidia,tegra-audio-max98090-nyan", - "nvidia,tegra-audio-max98090"; - nvidia,model = "GoogleNyanBlaze"; - }; - - pinmux@70000868 { - pinctrl-names = "default"; - pinctrl-0 = <&pinmux_default>; - - pinmux_default: common { - clk_32k_out_pa0 { - nvidia,pins = "clk_32k_out_pa0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart3_cts_n_pa1 { - nvidia,pins = "uart3_cts_n_pa1"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap2_fs_pa2 { - nvidia,pins = "dap2_fs_pa2"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap2_sclk_pa3 { - nvidia,pins = "dap2_sclk_pa3"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap2_din_pa4 { - nvidia,pins = "dap2_din_pa4"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap2_dout_pa5 { - nvidia,pins = "dap2_dout_pa5"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_clk_pa6 { - nvidia,pins = "sdmmc3_clk_pa6"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_cmd_pa7 { - nvidia,pins = "sdmmc3_cmd_pa7"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pb0 { - nvidia,pins = "pb0"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pb1 { - nvidia,pins = "pb1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_dat3_pb4 { - nvidia,pins = "sdmmc3_dat3_pb4"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_dat2_pb5 { - nvidia,pins = "sdmmc3_dat2_pb5"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_dat1_pb6 { - nvidia,pins = "sdmmc3_dat1_pb6"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_dat0_pb7 { - nvidia,pins = "sdmmc3_dat0_pb7"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart3_rts_n_pc0 { - nvidia,pins = "uart3_rts_n_pc0"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2_txd_pc2 { - nvidia,pins = "uart2_txd_pc2"; - nvidia,function = "irda"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2_rxd_pc3 { - nvidia,pins = "uart2_rxd_pc3"; - nvidia,function = "irda"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gen1_i2c_scl_pc4 { - nvidia,pins = "gen1_i2c_scl_pc4"; - nvidia,function = "i2c1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gen1_i2c_sda_pc5 { - nvidia,pins = "gen1_i2c_sda_pc5"; - nvidia,function = "i2c1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pc7 { - nvidia,pins = "pc7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg0 { - nvidia,pins = "pg0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg1 { - nvidia,pins = "pg1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg2 { - nvidia,pins = "pg2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg3 { - nvidia,pins = "pg3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg4 { - nvidia,pins = "pg4"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg5 { - nvidia,pins = "pg5"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg6 { - nvidia,pins = "pg6"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg7 { - nvidia,pins = "pg7"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph0 { - nvidia,pins = "ph0"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph1 { - nvidia,pins = "ph1"; - nvidia,function = "pwm1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph2 { - nvidia,pins = "ph2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph3 { - nvidia,pins = "ph3"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph4 { - nvidia,pins = "ph4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph5 { - nvidia,pins = "ph5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph6 { - nvidia,pins = "ph6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph7 { - nvidia,pins = "ph7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi0 { - nvidia,pins = "pi0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi1 { - nvidia,pins = "pi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi2 { - nvidia,pins = "pi2"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi3 { - nvidia,pins = "pi3"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi4 { - nvidia,pins = "pi4"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi5 { - nvidia,pins = "pi5"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi6 { - nvidia,pins = "pi6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi7 { - nvidia,pins = "pi7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pj0 { - nvidia,pins = "pj0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pj2 { - nvidia,pins = "pj2"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2_cts_n_pj5 { - nvidia,pins = "uart2_cts_n_pj5"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2_rts_n_pj6 { - nvidia,pins = "uart2_rts_n_pj6"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pj7 { - nvidia,pins = "pj7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pk0 { - nvidia,pins = "pk0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pk1 { - nvidia,pins = "pk1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pk2 { - nvidia,pins = "pk2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pk3 { - nvidia,pins = "pk3"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pk4 { - nvidia,pins = "pk4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - spdif_out_pk5 { - nvidia,pins = "spdif_out_pk5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - spdif_in_pk6 { - nvidia,pins = "spdif_in_pk6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pk7 { - nvidia,pins = "pk7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap1_fs_pn0 { - nvidia,pins = "dap1_fs_pn0"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap1_din_pn1 { - nvidia,pins = "dap1_din_pn1"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap1_dout_pn2 { - nvidia,pins = "dap1_dout_pn2"; - nvidia,function = "i2s0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap1_sclk_pn3 { - nvidia,pins = "dap1_sclk_pn3"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - usb_vbus_en0_pn4 { - nvidia,pins = "usb_vbus_en0_pn4"; - nvidia,function = "usb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - usb_vbus_en1_pn5 { - nvidia,pins = "usb_vbus_en1_pn5"; - nvidia,function = "usb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - hdmi_int_pn7 { - nvidia,pins = "hdmi_int_pn7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,rcv-sel = ; - }; - ulpi_data7_po0 { - nvidia,pins = "ulpi_data7_po0"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data0_po1 { - nvidia,pins = "ulpi_data0_po1"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data1_po2 { - nvidia,pins = "ulpi_data1_po2"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data2_po3 { - nvidia,pins = "ulpi_data2_po3"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data3_po4 { - nvidia,pins = "ulpi_data3_po4"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data4_po5 { - nvidia,pins = "ulpi_data4_po5"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data5_po6 { - nvidia,pins = "ulpi_data5_po6"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data6_po7 { - nvidia,pins = "ulpi_data6_po7"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3_fs_pp0 { - nvidia,pins = "dap3_fs_pp0"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3_din_pp1 { - nvidia,pins = "dap3_din_pp1"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3_dout_pp2 { - nvidia,pins = "dap3_dout_pp2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3_sclk_pp3 { - nvidia,pins = "dap3_sclk_pp3"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap4_fs_pp4 { - nvidia,pins = "dap4_fs_pp4"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap4_din_pp5 { - nvidia,pins = "dap4_din_pp5"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap4_dout_pp6 { - nvidia,pins = "dap4_dout_pp6"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap4_sclk_pp7 { - nvidia,pins = "dap4_sclk_pp7"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col0_pq0 { - nvidia,pins = "kb_col0_pq0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col1_pq1 { - nvidia,pins = "kb_col1_pq1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col2_pq2 { - nvidia,pins = "kb_col2_pq2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col3_pq3 { - nvidia,pins = "kb_col3_pq3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col4_pq4 { - nvidia,pins = "kb_col4_pq4"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col5_pq5 { - nvidia,pins = "kb_col5_pq5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col6_pq6 { - nvidia,pins = "kb_col6_pq6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col7_pq7 { - nvidia,pins = "kb_col7_pq7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row0_pr0 { - nvidia,pins = "kb_row0_pr0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row1_pr1 { - nvidia,pins = "kb_row1_pr1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row2_pr2 { - nvidia,pins = "kb_row2_pr2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row3_pr3 { - nvidia,pins = "kb_row3_pr3"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row4_pr4 { - nvidia,pins = "kb_row4_pr4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row5_pr5 { - nvidia,pins = "kb_row5_pr5"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row6_pr6 { - nvidia,pins = "kb_row6_pr6"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row7_pr7 { - nvidia,pins = "kb_row7_pr7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row8_ps0 { - nvidia,pins = "kb_row8_ps0"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row9_ps1 { - nvidia,pins = "kb_row9_ps1"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row10_ps2 { - nvidia,pins = "kb_row10_ps2"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row11_ps3 { - nvidia,pins = "kb_row11_ps3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row12_ps4 { - nvidia,pins = "kb_row12_ps4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row13_ps5 { - nvidia,pins = "kb_row13_ps5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row14_ps6 { - nvidia,pins = "kb_row14_ps6"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row15_ps7 { - nvidia,pins = "kb_row15_ps7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row16_pt0 { - nvidia,pins = "kb_row16_pt0"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row17_pt1 { - nvidia,pins = "kb_row17_pt1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gen2_i2c_scl_pt5 { - nvidia,pins = "gen2_i2c_scl_pt5"; - nvidia,function = "i2c2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gen2_i2c_sda_pt6 { - nvidia,pins = "gen2_i2c_sda_pt6"; - nvidia,function = "i2c2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc4_cmd_pt7 { - nvidia,pins = "sdmmc4_cmd_pt7"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu0 { - nvidia,pins = "pu0"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu1 { - nvidia,pins = "pu1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu2 { - nvidia,pins = "pu2"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu3 { - nvidia,pins = "pu3"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu4 { - nvidia,pins = "pu4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu5 { - nvidia,pins = "pu5"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu6 { - nvidia,pins = "pu6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pv0 { - nvidia,pins = "pv0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pv1 { - nvidia,pins = "pv1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_cd_n_pv2 { - nvidia,pins = "sdmmc3_cd_n_pv2"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_wp_n_pv3 { - nvidia,pins = "sdmmc1_wp_n_pv3"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ddc_scl_pv4 { - nvidia,pins = "ddc_scl_pv4"; - nvidia,function = "i2c4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,rcv-sel = ; - }; - ddc_sda_pv5 { - nvidia,pins = "ddc_sda_pv5"; - nvidia,function = "i2c4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,rcv-sel = ; - }; - gpio_w2_aud_pw2 { - nvidia,pins = "gpio_w2_aud_pw2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_w3_aud_pw3 { - nvidia,pins = "gpio_w3_aud_pw3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap_mclk1_pw4 { - nvidia,pins = "dap_mclk1_pw4"; - nvidia,function = "extperiph1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk2_out_pw5 { - nvidia,pins = "clk2_out_pw5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart3_txd_pw6 { - nvidia,pins = "uart3_txd_pw6"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart3_rxd_pw7 { - nvidia,pins = "uart3_rxd_pw7"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dvfs_pwm_px0 { - nvidia,pins = "dvfs_pwm_px0"; - nvidia,function = "cldvfs"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_x1_aud_px1 { - nvidia,pins = "gpio_x1_aud_px1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dvfs_clk_px2 { - nvidia,pins = "dvfs_clk_px2"; - nvidia,function = "cldvfs"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_x3_aud_px3 { - nvidia,pins = "gpio_x3_aud_px3"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_x4_aud_px4 { - nvidia,pins = "gpio_x4_aud_px4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_x5_aud_px5 { - nvidia,pins = "gpio_x5_aud_px5"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_x6_aud_px6 { - nvidia,pins = "gpio_x6_aud_px6"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_x7_aud_px7 { - nvidia,pins = "gpio_x7_aud_px7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_clk_py0 { - nvidia,pins = "ulpi_clk_py0"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_dir_py1 { - nvidia,pins = "ulpi_dir_py1"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_nxt_py2 { - nvidia,pins = "ulpi_nxt_py2"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_stp_py3 { - nvidia,pins = "ulpi_stp_py3"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_dat3_py4 { - nvidia,pins = "sdmmc1_dat3_py4"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_dat2_py5 { - nvidia,pins = "sdmmc1_dat2_py5"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_dat1_py6 { - nvidia,pins = "sdmmc1_dat1_py6"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_dat0_py7 { - nvidia,pins = "sdmmc1_dat0_py7"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_clk_pz0 { - nvidia,pins = "sdmmc1_clk_pz0"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_cmd_pz1 { - nvidia,pins = "sdmmc1_cmd_pz1"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pwr_i2c_scl_pz6 { - nvidia,pins = "pwr_i2c_scl_pz6"; - nvidia,function = "i2cpwr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pwr_i2c_sda_pz7 { - nvidia,pins = "pwr_i2c_sda_pz7"; - nvidia,function = "i2cpwr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc4_dat0_paa0 { - nvidia,pins = "sdmmc4_dat0_paa0"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_dat1_paa1 { - nvidia,pins = "sdmmc4_dat1_paa1"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_dat2_paa2 { - nvidia,pins = "sdmmc4_dat2_paa2"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_dat3_paa3 { - nvidia,pins = "sdmmc4_dat3_paa3"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_dat4_paa4 { - nvidia,pins = "sdmmc4_dat4_paa4"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_dat5_paa5 { - nvidia,pins = "sdmmc4_dat5_paa5"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_dat6_paa6 { - nvidia,pins = "sdmmc4_dat6_paa6"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_dat7_paa7 { - nvidia,pins = "sdmmc4_dat7_paa7"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pbb0 { - nvidia,pins = "pbb0"; - nvidia,function = "vgp6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - cam_i2c_scl_pbb1 { - nvidia,pins = "cam_i2c_scl_pbb1"; - nvidia,function = "i2c3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam_i2c_sda_pbb2 { - nvidia,pins = "cam_i2c_sda_pbb2"; - nvidia,function = "i2c3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pbb3 { - nvidia,pins = "pbb3"; - nvidia,function = "vgp3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pbb4 { - nvidia,pins = "pbb4"; - nvidia,function = "vgp4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pbb5 { - nvidia,pins = "pbb5"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pbb6 { - nvidia,pins = "pbb6"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pbb7 { - nvidia,pins = "pbb7"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - cam_mclk_pcc0 { - nvidia,pins = "cam_mclk_pcc0"; - nvidia,function = "vi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pcc1 { - nvidia,pins = "pcc1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pcc2 { - nvidia,pins = "pcc2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_clk_pcc4 { - nvidia,pins = "sdmmc4_clk_pcc4"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk2_req_pcc5 { - nvidia,pins = "clk2_req_pcc5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex_l0_rst_n_pdd1 { - nvidia,pins = "pex_l0_rst_n_pdd1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex_l0_clkreq_n_pdd2 { - nvidia,pins = "pex_l0_clkreq_n_pdd2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex_wake_n_pdd3 { - nvidia,pins = "pex_wake_n_pdd3"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex_l1_rst_n_pdd5 { - nvidia,pins = "pex_l1_rst_n_pdd5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex_l1_clkreq_n_pdd6 { - nvidia,pins = "pex_l1_clkreq_n_pdd6"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk3_out_pee0 { - nvidia,pins = "clk3_out_pee0"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk3_req_pee1 { - nvidia,pins = "clk3_req_pee1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap_mclk1_req_pee2 { - nvidia,pins = "dap_mclk1_req_pee2"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - hdmi_cec_pee3 { - nvidia,pins = "hdmi_cec_pee3"; - nvidia,function = "cec"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc3_clk_lb_out_pee4 { - nvidia,pins = "sdmmc3_clk_lb_out_pee4"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_clk_lb_in_pee5 { - nvidia,pins = "sdmmc3_clk_lb_in_pee5"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dp_hpd_pff0 { - nvidia,pins = "dp_hpd_pff0"; - nvidia,function = "dp"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - usb_vbus_en2_pff1 { - nvidia,pins = "usb_vbus_en2_pff1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pff2 { - nvidia,pins = "pff2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - core_pwr_req { - nvidia,pins = "core_pwr_req"; - nvidia,function = "pwron"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - cpu_pwr_req { - nvidia,pins = "cpu_pwr_req"; - nvidia,function = "cpu"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pwr_int_n { - nvidia,pins = "pwr_int_n"; - nvidia,function = "pmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - reset_out_n { - nvidia,pins = "reset_out_n"; - nvidia,function = "reset_out_n"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - owr { - nvidia,pins = "owr"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,rcv-sel = ; - }; - clk_32k_in { - nvidia,pins = "clk_32k_in"; - nvidia,function = "clk"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - jtag_rtck { - nvidia,pins = "jtag_rtck"; - nvidia,function = "rtck"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/tegra124-nyan.dtsi b/sys/gnu/dts/arm/tegra124-nyan.dtsi deleted file mode 100644 index 3b10f475037..00000000000 --- a/sys/gnu/dts/arm/tegra124-nyan.dtsi +++ /dev/null @@ -1,806 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include -#include "tegra124.dtsi" - -/ { - aliases { - rtc0 = "/i2c@7000d000/pmic@40"; - rtc1 = "/rtc@7000e000"; - serial0 = &uarta; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - /* - * Note that recent version of the device tree compiler (starting with - * version 1.4.2) warn about this node containing a reg property, but - * missing a unit-address. However, the bootloader on these Chromebook - * devices relies on the full name of this node to be exactly /memory. - * Adding the unit-address causes the bootloader to create a /memory - * node and write the memory bank configuration to that node, which in - * turn leads the kernel to believe that the device has 2 GiB of - * memory instead of the amount detected by the bootloader. - * - * The name of this node is effectively ABI and must not be changed. - */ - memory { - device_type = "memory"; - reg = <0x0 0x80000000 0x0 0x80000000>; - }; - - /delete-node/ memory@80000000; - - host1x@50000000 { - hdmi@54280000 { - status = "okay"; - - vdd-supply = <&vdd_3v3_hdmi>; - pll-supply = <&vdd_hdmi_pll>; - hdmi-supply = <&vdd_5v0_hdmi>; - - nvidia,ddc-i2c-bus = <&hdmi_ddc>; - nvidia,hpd-gpio = - <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; - }; - - sor@54540000 { - status = "okay"; - - nvidia,dpaux = <&dpaux>; - nvidia,panel = <&panel>; - }; - - dpaux@545c0000 { - vdd-supply = <&vdd_3v3_panel>; - status = "okay"; - }; - }; - - gpu@0,57000000 { - status = "okay"; - - vdd-supply = <&vdd_gpu>; - }; - - serial@70006000 { - /* Debug connector on the bottom of the board near SD card. */ - status = "okay"; - }; - - pwm@7000a000 { - status = "okay"; - }; - - i2c@7000c000 { - status = "okay"; - clock-frequency = <100000>; - - acodec: audio-codec@10 { - compatible = "maxim,max98090"; - reg = <0x10>; - interrupt-parent = <&gpio>; - interrupts = ; - }; - - temperature-sensor@4c { - compatible = "ti,tmp451"; - reg = <0x4c>; - interrupt-parent = <&gpio>; - interrupts = ; - - #thermal-sensor-cells = <1>; - }; - }; - - i2c@7000c400 { - status = "okay"; - clock-frequency = <100000>; - - trackpad@15 { - compatible = "elan,ekth3000"; - reg = <0x15>; - interrupt-parent = <&gpio>; - interrupts = ; - wakeup-source; - }; - }; - - i2c@7000c500 { - status = "okay"; - clock-frequency = <400000>; - - tpm@20 { - compatible = "infineon,slb9645tt"; - reg = <0x20>; - }; - }; - - hdmi_ddc: i2c@7000c700 { - status = "okay"; - clock-frequency = <100000>; - }; - - i2c@7000d000 { - status = "okay"; - clock-frequency = <400000>; - - pmic: pmic@40 { - compatible = "ams,as3722"; - reg = <0x40>; - interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; - - ams,system-power-controller; - - #interrupt-cells = <2>; - interrupt-controller; - - gpio-controller; - #gpio-cells = <2>; - - pinctrl-names = "default"; - pinctrl-0 = <&as3722_default>; - - as3722_default: pinmux { - gpio0 { - pins = "gpio0"; - function = "gpio"; - bias-pull-down; - }; - - gpio1 { - pins = "gpio1"; - function = "gpio"; - bias-pull-up; - }; - - gpio2_4_7 { - pins = "gpio2", "gpio4", "gpio7"; - function = "gpio"; - bias-pull-up; - }; - - gpio3_6 { - pins = "gpio3", "gpio6"; - bias-high-impedance; - }; - - gpio5 { - pins = "gpio5"; - function = "clk32k-out"; - bias-pull-down; - }; - }; - - regulators { - vsup-sd2-supply = <&vdd_5v0_sys>; - vsup-sd3-supply = <&vdd_5v0_sys>; - vsup-sd4-supply = <&vdd_5v0_sys>; - vsup-sd5-supply = <&vdd_5v0_sys>; - vin-ldo0-supply = <&vdd_1v35_lp0>; - vin-ldo1-6-supply = <&vdd_3v3_run>; - vin-ldo2-5-7-supply = <&vddio_1v8>; - vin-ldo3-4-supply = <&vdd_3v3_sys>; - vin-ldo9-10-supply = <&vdd_5v0_sys>; - vin-ldo11-supply = <&vdd_3v3_run>; - - vdd_cpu: sd0 { - regulator-name = "+VDD_CPU_AP"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1350000>; - regulator-min-microamp = <3500000>; - regulator-max-microamp = <3500000>; - regulator-always-on; - regulator-boot-on; - ams,ext-control = <2>; - }; - - sd1 { - regulator-name = "+VDD_CORE"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1350000>; - regulator-min-microamp = <2500000>; - regulator-max-microamp = <4000000>; - regulator-always-on; - regulator-boot-on; - ams,ext-control = <1>; - }; - - vdd_1v35_lp0: sd2 { - regulator-name = "+1.35V_LP0(sd2)"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - - sd3 { - regulator-name = "+1.35V_LP0(sd3)"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_1v05_run: sd4 { - regulator-name = "+1.05V_RUN"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - }; - - vddio_1v8: sd5 { - regulator-name = "+1.8V_VDDIO"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vdd_gpu: sd6 { - regulator-name = "+VDD_GPU_AP"; - regulator-min-microvolt = <650000>; - regulator-max-microvolt = <1200000>; - regulator-min-microamp = <3500000>; - regulator-max-microamp = <3500000>; - regulator-boot-on; - regulator-always-on; - }; - - avdd_1v05_run: ldo0 { - regulator-name = "+1.05V_RUN_AVDD"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - regulator-boot-on; - regulator-always-on; - ams,ext-control = <1>; - }; - - ldo1 { - regulator-name = "+1.8V_RUN_CAM"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo2 { - regulator-name = "+1.2V_GEN_AVDD"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo3 { - regulator-name = "+1.00V_LP0_VDD_RTC"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-boot-on; - regulator-always-on; - ams,enable-tracking; - }; - - vdd_run_cam: ldo4 { - regulator-name = "+3.3V_RUN_CAM"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo5 { - regulator-name = "+1.2V_RUN_CAM_FRONT"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - vddio_sdmmc3: ldo6 { - regulator-name = "+VDDIO_SDMMC3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - ldo7 { - regulator-name = "+1.05V_RUN_CAM_REAR"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - }; - - ldo9 { - regulator-name = "+2.8V_RUN_TOUCH"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo10 { - regulator-name = "+2.8V_RUN_CAM_AF"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo11 { - regulator-name = "+1.8V_RUN_VPP_FUSE"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - }; - }; - }; - - spi@7000d400 { - status = "okay"; - - cros_ec: cros-ec@0 { - compatible = "google,cros-ec-spi"; - spi-max-frequency = <3000000>; - interrupt-parent = <&gpio>; - interrupts = ; - reg = <0>; - - google,cros-ec-spi-msg-delay = <2000>; - - i2c-tunnel { - compatible = "google,cros-ec-i2c-tunnel"; - #address-cells = <1>; - #size-cells = <0>; - - google,remote-bus = <0>; - - charger: bq24735@9 { - compatible = "ti,bq24735"; - reg = <0x9>; - interrupt-parent = <&gpio>; - interrupts = ; - ti,ac-detect-gpios = <&gpio - TEGRA_GPIO(J, 0) - GPIO_ACTIVE_HIGH>; - ti,external-control; - }; - - battery: sbs-battery@b { - compatible = "sbs,sbs-battery"; - reg = <0xb>; - sbs,i2c-retry-count = <2>; - sbs,poll-retry-count = <10>; - power-supplies = <&charger>; - }; - }; - }; - }; - - spi@7000da00 { - status = "okay"; - spi-max-frequency = <25000000>; - - flash@0 { - compatible = "winbond,w25q32dw", "jedec,spi-nor"; - spi-max-frequency = <25000000>; - reg = <0>; - }; - }; - - pmc@7000e400 { - nvidia,invert-interrupt; - nvidia,suspend-mode = <0>; - nvidia,cpu-pwr-good-time = <500>; - nvidia,cpu-pwr-off-time = <300>; - nvidia,core-pwr-good-time = <641 3845>; - nvidia,core-pwr-off-time = <61036>; - nvidia,core-power-req-active-high; - nvidia,sys-clock-req-active-high; - }; - - hda@70030000 { - status = "okay"; - }; - - usb@70090000 { - phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>, /* 1st USB A */ - <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>, /* Internal USB */ - <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>, /* 2nd USB A */ - <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>, /* 1st USB A */ - <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>; /* 2nd USB A */ - phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-0", "usb3-1"; - - avddio-pex-supply = <&vdd_1v05_run>; - dvddio-pex-supply = <&vdd_1v05_run>; - avdd-usb-supply = <&vdd_3v3_lp0>; - avdd-pll-utmip-supply = <&vddio_1v8>; - avdd-pll-erefe-supply = <&avdd_1v05_run>; - avdd-usb-ss-pll-supply = <&vdd_1v05_run>; - hvdd-usb-ss-supply = <&vdd_3v3_lp0>; - hvdd-usb-ss-pll-e-supply = <&vdd_3v3_lp0>; - - status = "okay"; - }; - - padctl@7009f000 { - status = "okay"; - - avdd-pll-utmip-supply = <&vddio_1v8>; - avdd-pll-erefe-supply = <&avdd_1v05_run>; - avdd-pex-pll-supply = <&vdd_1v05_run>; - hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>; - - pads { - usb2 { - status = "okay"; - - lanes { - usb2-0 { - nvidia,function = "xusb"; - status = "okay"; - }; - - usb2-1 { - nvidia,function = "xusb"; - status = "okay"; - }; - - usb2-2 { - nvidia,function = "xusb"; - status = "okay"; - }; - }; - }; - - pcie { - status = "okay"; - - lanes { - pcie-0 { - nvidia,function = "usb3-ss"; - status = "okay"; - }; - - pcie-1 { - nvidia,function = "usb3-ss"; - status = "okay"; - }; - }; - }; - }; - - ports { - usb2-0 { - vbus-supply = <&vdd_usb1_vbus>; - status = "okay"; - mode = "otg"; - }; - - usb2-1 { - vbus-supply = <&vdd_run_cam>; - status = "okay"; - mode = "host"; - }; - - usb2-2 { - vbus-supply = <&vdd_usb3_vbus>; - status = "okay"; - mode = "host"; - }; - - usb3-0 { - nvidia,usb2-companion = <0>; - status = "okay"; - }; - - usb3-1 { - nvidia,usb2-companion = <1>; - status = "okay"; - }; - }; - }; - - sdhci0_pwrseq: sdhci0_pwrseq { - compatible = "mmc-pwrseq-simple"; - - reset-gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>; - }; - - sdhci@700b0000 { /* WiFi/BT on this bus */ - status = "okay"; - bus-width = <4>; - no-1-8-v; - non-removable; - mmc-pwrseq = <&sdhci0_pwrseq>; - vmmc-supply = <&vdd_3v3_lp0>; - vqmmc-supply = <&vddio_1v8>; - keep-power-in-suspend; - }; - - sdhci@700b0400 { /* SD Card on this bus */ - status = "okay"; - cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; - power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; - bus-width = <4>; - no-1-8-v; - vqmmc-supply = <&vddio_sdmmc3>; - }; - - sdhci@700b0600 { /* eMMC on this bus */ - status = "okay"; - bus-width = <8>; - no-1-8-v; - non-removable; - }; - - /* CPU DFLL clock */ - clock@70110000 { - status = "disabled"; - vdd-cpu-supply = <&vdd_cpu>; - nvidia,i2c-fs-rate = <400000>; - }; - - ahub@70300000 { - i2s@70301100 { - status = "okay"; - }; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - - enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; - power-supply = <&vdd_led>; - pwms = <&pwm 1 1000000>; - - default-brightness-level = <224>; - brightness-levels = - < 0 1 2 3 4 5 6 7 - 8 9 10 11 12 13 14 15 - 16 17 18 19 20 21 22 23 - 24 25 26 27 28 29 30 31 - 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 - 48 49 50 51 52 53 54 55 - 56 57 58 59 60 61 62 63 - 64 65 66 67 68 69 70 71 - 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 - 88 89 90 91 92 93 94 95 - 96 97 98 99 100 101 102 103 - 104 105 106 107 108 109 110 111 - 112 113 114 115 116 117 118 119 - 120 121 122 123 124 125 126 127 - 128 129 130 131 132 133 134 135 - 136 137 138 139 140 141 142 143 - 144 145 146 147 148 149 150 151 - 152 153 154 155 156 157 158 159 - 160 161 162 163 164 165 166 167 - 168 169 170 171 172 173 174 175 - 176 177 178 179 180 181 182 183 - 184 185 186 187 188 189 190 191 - 192 193 194 195 196 197 198 199 - 200 201 202 203 204 205 206 207 - 208 209 210 211 212 213 214 215 - 216 217 218 219 220 221 222 223 - 224 225 226 227 228 229 230 231 - 232 233 234 235 236 237 238 239 - 240 241 242 243 244 245 246 247 - 248 249 250 251 252 253 254 255 - 256>; - }; - - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - cpus { - cpu@0 { - vdd-cpu-supply = <&vdd_cpu>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - lid { - label = "Lid"; - gpios = <&gpio TEGRA_GPIO(R, 4) GPIO_ACTIVE_LOW>; - linux,input-type = <5>; - linux,code = ; - debounce-interval = <1>; - wakeup-source; - }; - - power { - label = "Power"; - gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <30>; - wakeup-source; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - vdd_mux: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "+VDD_MUX"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_5v0_sys: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "+5V_SYS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vdd_mux>; - }; - - vdd_3v3_sys: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "+3.3V_SYS"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vdd_mux>; - }; - - vdd_3v3_run: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "+3.3V_RUN"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_3v3_sys>; - }; - - vdd_3v3_hdmi: regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "+3.3V_AVDD_HDMI_AP_GATED"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vdd_3v3_run>; - }; - - vdd_led: regulator@5 { - compatible = "regulator-fixed"; - reg = <5>; - regulator-name = "+VDD_LED"; - gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_mux>; - }; - - vdd_5v0_ts: regulator@6 { - compatible = "regulator-fixed"; - reg = <6>; - regulator-name = "+5V_VDD_TS_SW"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_5v0_sys>; - }; - - vdd_usb1_vbus: regulator@7 { - compatible = "regulator-fixed"; - reg = <7>; - regulator-name = "+5V_USB_HS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; - enable-active-high; - gpio-open-drain; - vin-supply = <&vdd_5v0_sys>; - }; - - vdd_usb3_vbus: regulator@8 { - compatible = "regulator-fixed"; - reg = <8>; - regulator-name = "+5V_USB_SS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>; - enable-active-high; - gpio-open-drain; - vin-supply = <&vdd_5v0_sys>; - }; - - vdd_3v3_panel: regulator@9 { - compatible = "regulator-fixed"; - reg = <9>; - regulator-name = "+3.3V_PANEL"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&pmic 4 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_3v3_run>; - }; - - vdd_3v3_lp0: regulator@10 { - compatible = "regulator-fixed"; - reg = <10>; - regulator-name = "+3.3V_LP0"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - /* - * TODO: find a way to wire this up with the USB EHCI - * controllers so that it can be enabled on demand. - */ - regulator-always-on; - gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_3v3_sys>; - }; - - vdd_hdmi_pll: regulator@11 { - compatible = "regulator-fixed"; - reg = <11>; - regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>; - vin-supply = <&vdd_1v05_run>; - }; - - vdd_5v0_hdmi: regulator@12 { - compatible = "regulator-fixed"; - reg = <12>; - regulator-name = "+5V_HDMI_CON"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_5v0_sys>; - }; - }; - - sound { - nvidia,audio-routing = - "Headphones", "HPR", - "Headphones", "HPL", - "Speakers", "SPKR", - "Speakers", "SPKL", - "Mic Jack", "MICBIAS", - "DMICL", "Int Mic", - "DMICR", "Int Mic", - "IN34", "Mic Jack"; - - nvidia,i2s-controller = <&tegra_i2s1>; - nvidia,audio-codec = <&acodec>; - - clocks = <&tegra_car TEGRA124_CLK_PLL_A>, - <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA124_CLK_EXTERN1>; - clock-names = "pll_a", "pll_a_out0", "mclk"; - - nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(I, 7) GPIO_ACTIVE_HIGH>; - nvidia,mic-det-gpios = - <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>; - }; - - gpio-restart { - compatible = "gpio-restart"; - gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; - priority = <200>; - }; -}; - -#include "cros-ec-keyboard.dtsi" diff --git a/sys/gnu/dts/arm/tegra124-venice2.dts b/sys/gnu/dts/arm/tegra124-venice2.dts deleted file mode 100644 index 7309393bfce..00000000000 --- a/sys/gnu/dts/arm/tegra124-venice2.dts +++ /dev/null @@ -1,1274 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include -#include "tegra124.dtsi" - -/ { - model = "NVIDIA Tegra124 Venice2"; - compatible = "nvidia,venice2", "nvidia,tegra124"; - - aliases { - rtc0 = "/i2c@7000d000/pmic@40"; - rtc1 = "/rtc@7000e000"; - serial0 = &uarta; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@80000000 { - reg = <0x0 0x80000000 0x0 0x80000000>; - }; - - host1x@50000000 { - hdmi@54280000 { - status = "okay"; - - vdd-supply = <&vdd_3v3_hdmi>; - pll-supply = <&vdd_hdmi_pll>; - hdmi-supply = <&vdd_5v0_hdmi>; - - nvidia,ddc-i2c-bus = <&hdmi_ddc>; - nvidia,hpd-gpio = - <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; - }; - - sor@54540000 { - status = "okay"; - - avdd-io-hdmi-dp-supply = <&vdd_1v05_run>; - vdd-hdmi-dp-pll-supply = <&vdd_3v3_run>; - - nvidia,dpaux = <&dpaux>; - nvidia,panel = <&panel>; - }; - - dpaux@545c0000 { - vdd-supply = <&vdd_3v3_panel>; - status = "okay"; - }; - }; - - gpu@0,57000000 { - /* - * Node left disabled on purpose - the bootloader will enable - * it after having set the VPR up - */ - vdd-supply = <&vdd_gpu>; - }; - - pinmux: pinmux@70000868 { - pinctrl-names = "boot"; - pinctrl-0 = <&pinmux_boot>; - - pinmux_boot: common { - dap_mclk1_pw4 { - nvidia,pins = "dap_mclk1_pw4"; - nvidia,function = "extperiph1"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - dap1_din_pn1 { - nvidia,pins = "dap1_din_pn1"; - nvidia,function = "i2s0"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - dap1_dout_pn2 { - nvidia,pins = "dap1_dout_pn2", - "dap1_fs_pn0", - "dap1_sclk_pn3"; - nvidia,function = "i2s0"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - dap2_din_pa4 { - nvidia,pins = "dap2_din_pa4"; - nvidia,function = "i2s1"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - dap2_dout_pa5 { - nvidia,pins = "dap2_dout_pa5", - "dap2_fs_pa2", - "dap2_sclk_pa3"; - nvidia,function = "i2s1"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - dvfs_pwm_px0 { - nvidia,pins = "dvfs_pwm_px0", - "dvfs_clk_px2"; - nvidia,function = "cldvfs"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - ulpi_clk_py0 { - nvidia,pins = "ulpi_clk_py0", - "ulpi_nxt_py2", - "ulpi_stp_py3"; - nvidia,function = "spi1"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - ulpi_dir_py1 { - nvidia,pins = "ulpi_dir_py1"; - nvidia,function = "spi1"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - cam_i2c_scl_pbb1 { - nvidia,pins = "cam_i2c_scl_pbb1", - "cam_i2c_sda_pbb2"; - nvidia,function = "i2c3"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,lock = ; - nvidia,open-drain = ; - }; - gen2_i2c_scl_pt5 { - nvidia,pins = "gen2_i2c_scl_pt5", - "gen2_i2c_sda_pt6"; - nvidia,function = "i2c2"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,lock = ; - nvidia,open-drain = ; - }; - pg4 { - nvidia,pins = "pg4", - "pg5", - "pg6", - "pi3"; - nvidia,function = "spi4"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - pg7 { - nvidia,pins = "pg7"; - nvidia,function = "spi4"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - ph1 { - nvidia,pins = "ph1"; - nvidia,function = "pwm1"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - pk0 { - nvidia,pins = "pk0", - "kb_row15_ps7", - "clk_32k_out_pa0"; - nvidia,function = "soc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_clk_pz0 { - nvidia,pins = "sdmmc1_clk_pz0"; - nvidia,function = "sdmmc1"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - sdmmc1_cmd_pz1 { - nvidia,pins = "sdmmc1_cmd_pz1", - "sdmmc1_dat0_py7", - "sdmmc1_dat1_py6", - "sdmmc1_dat2_py5", - "sdmmc1_dat3_py4"; - nvidia,function = "sdmmc1"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - sdmmc3_clk_pa6 { - nvidia,pins = "sdmmc3_clk_pa6"; - nvidia,function = "sdmmc3"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - sdmmc3_cmd_pa7 { - nvidia,pins = "sdmmc3_cmd_pa7", - "sdmmc3_dat0_pb7", - "sdmmc3_dat1_pb6", - "sdmmc3_dat2_pb5", - "sdmmc3_dat3_pb4", - "sdmmc3_clk_lb_out_pee4", - "sdmmc3_clk_lb_in_pee5"; - nvidia,function = "sdmmc3"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - sdmmc4_clk_pcc4 { - nvidia,pins = "sdmmc4_clk_pcc4"; - nvidia,function = "sdmmc4"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - sdmmc4_cmd_pt7 { - nvidia,pins = "sdmmc4_cmd_pt7", - "sdmmc4_dat0_paa0", - "sdmmc4_dat1_paa1", - "sdmmc4_dat2_paa2", - "sdmmc4_dat3_paa3", - "sdmmc4_dat4_paa4", - "sdmmc4_dat5_paa5", - "sdmmc4_dat6_paa6", - "sdmmc4_dat7_paa7"; - nvidia,function = "sdmmc4"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - pwr_i2c_scl_pz6 { - nvidia,pins = "pwr_i2c_scl_pz6", - "pwr_i2c_sda_pz7"; - nvidia,function = "i2cpwr"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,lock = ; - nvidia,open-drain = ; - }; - jtag_rtck { - nvidia,pins = "jtag_rtck"; - nvidia,function = "rtck"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - clk_32k_in { - nvidia,pins = "clk_32k_in"; - nvidia,function = "clk"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - core_pwr_req { - nvidia,pins = "core_pwr_req"; - nvidia,function = "pwron"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - cpu_pwr_req { - nvidia,pins = "cpu_pwr_req"; - nvidia,function = "cpu"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - pwr_int_n { - nvidia,pins = "pwr_int_n"; - nvidia,function = "pmi"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - reset_out_n { - nvidia,pins = "reset_out_n"; - nvidia,function = "reset_out_n"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - clk3_out_pee0 { - nvidia,pins = "clk3_out_pee0"; - nvidia,function = "extperiph3"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - dap4_din_pp5 { - nvidia,pins = "dap4_din_pp5"; - nvidia,function = "i2s3"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - dap4_dout_pp6 { - nvidia,pins = "dap4_dout_pp6", - "dap4_fs_pp4", - "dap4_sclk_pp7"; - nvidia,function = "i2s3"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - gen1_i2c_sda_pc5 { - nvidia,pins = "gen1_i2c_sda_pc5", - "gen1_i2c_scl_pc4"; - nvidia,function = "i2c1"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,lock = ; - nvidia,open-drain = ; - }; - uart2_cts_n_pj5 { - nvidia,pins = "uart2_cts_n_pj5"; - nvidia,function = "uartb"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - uart2_rts_n_pj6 { - nvidia,pins = "uart2_rts_n_pj6"; - nvidia,function = "uartb"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - uart2_rxd_pc3 { - nvidia,pins = "uart2_rxd_pc3"; - nvidia,function = "irda"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - uart2_txd_pc2 { - nvidia,pins = "uart2_txd_pc2"; - nvidia,function = "irda"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - uart3_cts_n_pa1 { - nvidia,pins = "uart3_cts_n_pa1", - "uart3_rxd_pw7"; - nvidia,function = "uartc"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - uart3_rts_n_pc0 { - nvidia,pins = "uart3_rts_n_pc0", - "uart3_txd_pw6"; - nvidia,function = "uartc"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - hdmi_cec_pee3 { - nvidia,pins = "hdmi_cec_pee3"; - nvidia,function = "cec"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,lock = ; - nvidia,open-drain = ; - }; - hdmi_int_pn7 { - nvidia,pins = "hdmi_int_pn7"; - nvidia,function = "rsvd1"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - ddc_scl_pv4 { - nvidia,pins = "ddc_scl_pv4", - "ddc_sda_pv5"; - nvidia,function = "i2c4"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,lock = ; - nvidia,rcv-sel = ; - }; - pj7 { - nvidia,pins = "pj7", - "pk7"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pb0 { - nvidia,pins = "pb0", - "pb1"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph0 { - nvidia,pins = "ph0"; - nvidia,function = "pwm0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row10_ps2 { - nvidia,pins = "kb_row10_ps2"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row9_ps1 { - nvidia,pins = "kb_row9_ps1"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row6_pr6 { - nvidia,pins = "kb_row6_pr6"; - nvidia,function = "displaya_alt"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - usb_vbus_en0_pn4 { - nvidia,pins = "usb_vbus_en0_pn4", - "usb_vbus_en1_pn5"; - nvidia,function = "usb"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,lock = ; - nvidia,open-drain = ; - }; - drive_sdio1 { - nvidia,pins = "drive_sdio1"; - nvidia,high-speed-mode = ; - nvidia,schmitt = ; - nvidia,pull-down-strength = <32>; - nvidia,pull-up-strength = <42>; - nvidia,slew-rate-rising = ; - nvidia,slew-rate-falling = ; - }; - drive_sdio3 { - nvidia,pins = "drive_sdio3"; - nvidia,high-speed-mode = ; - nvidia,schmitt = ; - nvidia,pull-down-strength = <20>; - nvidia,pull-up-strength = <36>; - nvidia,slew-rate-rising = ; - nvidia,slew-rate-falling = ; - }; - drive_gma { - nvidia,pins = "drive_gma"; - nvidia,high-speed-mode = ; - nvidia,schmitt = ; - nvidia,low-power-mode = ; - nvidia,pull-down-strength = <1>; - nvidia,pull-up-strength = <2>; - nvidia,slew-rate-rising = ; - nvidia,slew-rate-falling = ; - nvidia,drive-type = <1>; - }; - als_irq_l { - nvidia,pins = "gpio_x3_aud_px3"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - codec_irq_l { - nvidia,pins = "ph4"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_bl_en { - nvidia,pins = "ph2"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - touch_irq_l { - nvidia,pins = "gpio_w3_aud_pw3"; - nvidia,function = "spi6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - tpm_davint_l { - nvidia,pins = "ph6"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ts_irq_l { - nvidia,pins = "pk2"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ts_reset_l { - nvidia,pins = "pk4"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ts_shdn_l { - nvidia,pins = "pk1"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph7 { - nvidia,pins = "ph7"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col0_ap { - nvidia,pins = "kb_col0_pq0"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lid_open { - nvidia,pins = "kb_row4_pr4"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - en_vdd_sd { - nvidia,pins = "kb_row0_pr0"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ac_ok { - nvidia,pins = "pj0"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sensor_irq_l { - nvidia,pins = "pi6"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - wifi_en { - nvidia,pins = "gpio_x7_aud_px7"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - wifi_rst_l { - nvidia,pins = "clk2_req_pcc5"; - nvidia,function = "dap"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - hp_det_l { - nvidia,pins = "ulpi_data1_po2"; - nvidia,function = "spi3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - }; - }; - - serial@70006000 { - status = "okay"; - }; - - pwm@7000a000 { - status = "okay"; - }; - - i2c@7000c000 { - status = "okay"; - clock-frequency = <100000>; - - acodec: audio-codec@10 { - compatible = "maxim,max98090"; - reg = <0x10>; - interrupt-parent = <&gpio>; - interrupts = ; - }; - }; - - i2c@7000c400 { - status = "okay"; - clock-frequency = <100000>; - - trackpad@4b { - compatible = "atmel,maxtouch"; - reg = <0x4b>; - interrupt-parent = <&gpio>; - interrupts = ; - linux,gpio-keymap = <0 0 0 BTN_LEFT>; - }; - }; - - i2c@7000c500 { - status = "okay"; - clock-frequency = <100000>; - }; - - hdmi_ddc: i2c@7000c700 { - status = "okay"; - clock-frequency = <100000>; - }; - - i2c@7000d000 { - status = "okay"; - clock-frequency = <400000>; - - pmic: pmic@40 { - compatible = "ams,as3722"; - reg = <0x40>; - interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; - - ams,system-power-controller; - - #interrupt-cells = <2>; - interrupt-controller; - - gpio-controller; - #gpio-cells = <2>; - - pinctrl-names = "default"; - pinctrl-0 = <&as3722_default>; - - as3722_default: pinmux { - gpio0 { - pins = "gpio0"; - function = "gpio"; - bias-pull-down; - }; - - gpio1_2_4_7 { - pins = "gpio1", "gpio2", "gpio4", "gpio7"; - function = "gpio"; - bias-pull-up; - }; - - gpio3_6 { - pins = "gpio3", "gpio6"; - bias-high-impedance; - }; - - gpio5 { - pins = "gpio5"; - function = "clk32k-out"; - }; - }; - - regulators { - vsup-sd2-supply = <&vdd_5v0_sys>; - vsup-sd3-supply = <&vdd_5v0_sys>; - vsup-sd4-supply = <&vdd_5v0_sys>; - vsup-sd5-supply = <&vdd_5v0_sys>; - vin-ldo0-supply = <&vdd_1v35_lp0>; - vin-ldo1-6-supply = <&vdd_3v3_run>; - vin-ldo2-5-7-supply = <&vddio_1v8>; - vin-ldo3-4-supply = <&vdd_3v3_sys>; - vin-ldo9-10-supply = <&vdd_5v0_sys>; - vin-ldo11-supply = <&vdd_3v3_run>; - - sd0 { - regulator-name = "+VDD_CPU_AP"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1400000>; - regulator-min-microamp = <3500000>; - regulator-max-microamp = <3500000>; - regulator-always-on; - regulator-boot-on; - ams,ext-control = <2>; - }; - - sd1 { - regulator-name = "+VDD_CORE"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1350000>; - regulator-min-microamp = <2500000>; - regulator-max-microamp = <2500000>; - regulator-always-on; - regulator-boot-on; - ams,ext-control = <1>; - }; - - vdd_1v35_lp0: sd2 { - regulator-name = "+1.35V_LP0(sd2)"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - - sd3 { - regulator-name = "+1.35V_LP0(sd3)"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_1v05_run: sd4 { - regulator-name = "+1.05V_RUN"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - }; - - vddio_1v8: sd5 { - regulator-name = "+1.8V_VDDIO"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - vdd_gpu: sd6 { - regulator-name = "+VDD_GPU_AP"; - regulator-min-microvolt = <650000>; - regulator-max-microvolt = <1200000>; - regulator-min-microamp = <3500000>; - regulator-max-microamp = <3500000>; - regulator-boot-on; - regulator-always-on; - }; - - avdd_1v05_run: ldo0 { - regulator-name = "+1.05V_RUN_AVDD"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - regulator-boot-on; - regulator-always-on; - ams,ext-control = <1>; - }; - - ldo1 { - regulator-name = "+1.8V_RUN_CAM"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo2 { - regulator-name = "+1.2V_GEN_AVDD"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo3 { - regulator-name = "+1.00V_LP0_VDD_RTC"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-boot-on; - regulator-always-on; - ams,enable-tracking; - }; - - vdd_run_cam: ldo4 { - regulator-name = "+3.3V_RUN_CAM"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo5 { - regulator-name = "+1.2V_RUN_CAM_FRONT"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - vddio_sdmmc3: ldo6 { - regulator-name = "+VDDIO_SDMMC3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - ldo7 { - regulator-name = "+1.05V_RUN_CAM_REAR"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - }; - - ldo9 { - regulator-name = "+2.8V_RUN_TOUCH"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo10 { - regulator-name = "+2.8V_RUN_CAM_AF"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo11 { - regulator-name = "+1.8V_RUN_VPP_FUSE"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - }; - }; - }; - - spi@7000d400 { - status = "okay"; - - cros_ec: cros-ec@0 { - compatible = "google,cros-ec-spi"; - spi-max-frequency = <4000000>; - interrupt-parent = <&gpio>; - interrupts = ; - reg = <0>; - - google,cros-ec-spi-msg-delay = <2000>; - - i2c-tunnel { - compatible = "google,cros-ec-i2c-tunnel"; - #address-cells = <1>; - #size-cells = <0>; - - google,remote-bus = <0>; - - charger: bq24735@9 { - compatible = "ti,bq24735"; - reg = <0x9>; - interrupt-parent = <&gpio>; - interrupts = ; - ti,ac-detect-gpios = <&gpio - TEGRA_GPIO(J, 0) - GPIO_ACTIVE_HIGH>; - }; - - battery: sbs-battery@b { - compatible = "sbs,sbs-battery"; - reg = <0xb>; - sbs,i2c-retry-count = <2>; - sbs,poll-retry-count = <1>; - }; - }; - }; - }; - - spi@7000da00 { - status = "okay"; - spi-max-frequency = <25000000>; - spi-flash@0 { - compatible = "winbond,w25q32dw", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <20000000>; - }; - }; - - pmc@7000e400 { - nvidia,invert-interrupt; - nvidia,suspend-mode = <1>; - nvidia,cpu-pwr-good-time = <500>; - nvidia,cpu-pwr-off-time = <300>; - nvidia,core-pwr-good-time = <641 3845>; - nvidia,core-pwr-off-time = <61036>; - nvidia,core-power-req-active-high; - nvidia,sys-clock-req-active-high; - }; - - hda@70030000 { - status = "okay"; - }; - - usb@70090000 { - phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>, /* 1st USB A */ - <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>, /* Internal USB */ - <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>, /* 2nd USB A */ - <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>, /* 1st USB A */ - <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>; /* 2nd USB A */ - phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-0", "usb3-1"; - - avddio-pex-supply = <&vdd_1v05_run>; - dvddio-pex-supply = <&vdd_1v05_run>; - avdd-usb-supply = <&vdd_3v3_lp0>; - avdd-pll-utmip-supply = <&vddio_1v8>; - avdd-pll-erefe-supply = <&avdd_1v05_run>; - avdd-usb-ss-pll-supply = <&vdd_1v05_run>; - hvdd-usb-ss-supply = <&vdd_3v3_lp0>; - hvdd-usb-ss-pll-e-supply = <&vdd_3v3_lp0>; - - status = "okay"; - }; - - padctl@7009f000 { - avdd-pll-utmip-supply = <&vddio_1v8>; - avdd-pll-erefe-supply = <&avdd_1v05_run>; - avdd-pex-pll-supply = <&vdd_1v05_run>; - hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>; - - pads { - usb2 { - status = "okay"; - - lanes { - usb2-0 { - nvidia,function = "xusb"; - status = "okay"; - }; - - usb2-1 { - nvidia,function = "xusb"; - status = "okay"; - }; - - usb2-2 { - nvidia,function = "xusb"; - status = "okay"; - }; - }; - }; - - pcie { - status = "okay"; - - lanes { - pcie-0 { - nvidia,function = "usb3-ss"; - status = "okay"; - }; - - pcie-1 { - nvidia,function = "usb3-ss"; - status = "okay"; - }; - }; - }; - }; - - ports { - usb2-0 { - status = "okay"; - mode = "otg"; - - vbus-supply = <&vdd_usb1_vbus>; - }; - - usb2-1 { - status = "okay"; - mode = "host"; - - vbus-supply = <&vdd_run_cam>; - }; - - usb2-2 { - status = "okay"; - mode = "host"; - - vbus-supply = <&vdd_usb3_vbus>; - }; - - usb3-0 { - nvidia,usb2-companion = <0>; - status = "okay"; - }; - - usb3-1 { - nvidia,usb2-companion = <2>; - status = "okay"; - }; - }; - }; - - sdhci@700b0400 { - cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; - power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; - wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>; - status = "okay"; - bus-width = <4>; - vqmmc-supply = <&vddio_sdmmc3>; - }; - - sdhci@700b0600 { - status = "okay"; - bus-width = <8>; - non-removable; - }; - - ahub@70300000 { - i2s@70301100 { - status = "okay"; - }; - }; - - usb@7d000000 { - status = "okay"; - }; - - usb-phy@7d000000 { - status = "okay"; - vbus-supply = <&vdd_usb1_vbus>; - }; - - usb@7d004000 { - status = "okay"; - }; - - usb-phy@7d004000 { - status = "okay"; - vbus-supply = <&vdd_run_cam>; - }; - - usb@7d008000 { - status = "okay"; - }; - - usb-phy@7d008000 { - status = "okay"; - vbus-supply = <&vdd_usb3_vbus>; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - - enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; - power-supply = <&vdd_led>; - pwms = <&pwm 1 1000000>; - - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - }; - - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - power { - label = "Power"; - gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <10>; - wakeup-source; - }; - }; - - panel: panel { - compatible = "lg,lp129qe", "simple-panel"; - - backlight = <&backlight>; - ddc-i2c-bus = <&dpaux>; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - vdd_mux: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "+VDD_MUX"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_5v0_sys: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "+5V_SYS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vdd_mux>; - }; - - vdd_3v3_sys: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "+3.3V_SYS"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vdd_mux>; - }; - - vdd_3v3_run: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "+3.3V_RUN"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_3v3_sys>; - }; - - vdd_3v3_hdmi: regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "+3.3V_AVDD_HDMI_AP_GATED"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vdd_3v3_run>; - }; - - vdd_led: regulator@5 { - compatible = "regulator-fixed"; - reg = <5>; - regulator-name = "+VDD_LED"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_mux>; - }; - - vdd_5v0_ts: regulator@6 { - compatible = "regulator-fixed"; - reg = <6>; - regulator-name = "+5V_VDD_TS_SW"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_5v0_sys>; - }; - - vdd_usb1_vbus: regulator@7 { - compatible = "regulator-fixed"; - reg = <7>; - regulator-name = "+5V_USB_HS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; - enable-active-high; - gpio-open-drain; - vin-supply = <&vdd_5v0_sys>; - }; - - vdd_usb3_vbus: regulator@8 { - compatible = "regulator-fixed"; - reg = <8>; - regulator-name = "+5V_USB_SS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>; - enable-active-high; - gpio-open-drain; - vin-supply = <&vdd_5v0_sys>; - }; - - vdd_3v3_panel: regulator@9 { - compatible = "regulator-fixed"; - reg = <9>; - regulator-name = "+3.3V_PANEL"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&pmic 4 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_3v3_run>; - }; - - vdd_3v3_lp0: regulator@10 { - compatible = "regulator-fixed"; - reg = <10>; - regulator-name = "+3.3V_LP0"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - /* - * TODO: find a way to wire this up with the USB EHCI - * controllers so that it can be enabled on demand. - */ - regulator-always-on; - gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_3v3_sys>; - }; - - vdd_hdmi_pll: regulator@11 { - compatible = "regulator-fixed"; - reg = <11>; - regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>; - vin-supply = <&vdd_1v05_run>; - }; - - vdd_5v0_hdmi: regulator@12 { - compatible = "regulator-fixed"; - reg = <12>; - regulator-name = "+5V_HDMI_CON"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_5v0_sys>; - }; - }; - - sound { - compatible = "nvidia,tegra-audio-max98090-venice2", - "nvidia,tegra-audio-max98090"; - nvidia,model = "NVIDIA Tegra Venice2"; - - nvidia,audio-routing = - "Headphones", "HPR", - "Headphones", "HPL", - "Speakers", "SPKR", - "Speakers", "SPKL", - "Mic Jack", "MICBIAS", - "IN34", "Mic Jack"; - - nvidia,i2s-controller = <&tegra_i2s1>; - nvidia,audio-codec = <&acodec>; - - clocks = <&tegra_car TEGRA124_CLK_PLL_A>, - <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA124_CLK_EXTERN1>; - clock-names = "pll_a", "pll_a_out0", "mclk"; - }; -}; - -#include "cros-ec-keyboard.dtsi" diff --git a/sys/gnu/dts/arm/tegra124.dtsi b/sys/gnu/dts/arm/tegra124.dtsi deleted file mode 100644 index 7f330b1f150..00000000000 --- a/sys/gnu/dts/arm/tegra124.dtsi +++ /dev/null @@ -1,1309 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include -#include -#include -#include -#include -#include -#include - -/ { - compatible = "nvidia,tegra124"; - interrupt-parent = <&lic>; - #address-cells = <2>; - #size-cells = <2>; - - memory@80000000 { - device_type = "memory"; - reg = <0x0 0x80000000 0x0 0x0>; - }; - - pcie@1003000 { - compatible = "nvidia,tegra124-pcie"; - device_type = "pci"; - reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */ - 0x0 0x01003800 0x0 0x00000800 /* AFI registers */ - 0x0 0x02000000 0x0 0x10000000>; /* configuration space */ - reg-names = "pads", "afi", "cs"; - interrupts = , /* controller interrupt */ - ; /* MSI interrupt */ - interrupt-names = "intr", "msi"; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; - - bus-range = <0x00 0xff>; - #address-cells = <3>; - #size-cells = <2>; - - ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */ - 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */ - 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */ - 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */ - 0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ - - clocks = <&tegra_car TEGRA124_CLK_PCIE>, - <&tegra_car TEGRA124_CLK_AFI>, - <&tegra_car TEGRA124_CLK_PLL_E>, - <&tegra_car TEGRA124_CLK_CML0>; - clock-names = "pex", "afi", "pll_e", "cml"; - resets = <&tegra_car 70>, - <&tegra_car 72>, - <&tegra_car 74>; - reset-names = "pex", "afi", "pcie_x"; - status = "disabled"; - - pci@1,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>; - reg = <0x000800 0 0 0 0>; - bus-range = <0x00 0xff>; - status = "disabled"; - - #address-cells = <3>; - #size-cells = <2>; - ranges; - - nvidia,num-lanes = <2>; - }; - - pci@2,0 { - device_type = "pci"; - assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>; - reg = <0x001000 0 0 0 0>; - bus-range = <0x00 0xff>; - status = "disabled"; - - #address-cells = <3>; - #size-cells = <2>; - ranges; - - nvidia,num-lanes = <1>; - }; - }; - - host1x@50000000 { - compatible = "nvidia,tegra124-host1x", "simple-bus"; - reg = <0x0 0x50000000 0x0 0x00034000>; - interrupts = , /* syncpt */ - ; /* general */ - clocks = <&tegra_car TEGRA124_CLK_HOST1X>; - resets = <&tegra_car 28>; - reset-names = "host1x"; - iommus = <&mc TEGRA_SWGROUP_HC>; - - #address-cells = <2>; - #size-cells = <2>; - - ranges = <0 0x54000000 0 0x54000000 0 0x01000000>; - - dc@54200000 { - compatible = "nvidia,tegra124-dc"; - reg = <0x0 0x54200000 0x0 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_DISP1>, - <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "dc", "parent"; - resets = <&tegra_car 27>; - reset-names = "dc"; - - iommus = <&mc TEGRA_SWGROUP_DC>; - - nvidia,head = <0>; - }; - - dc@54240000 { - compatible = "nvidia,tegra124-dc"; - reg = <0x0 0x54240000 0x0 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_DISP2>, - <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "dc", "parent"; - resets = <&tegra_car 26>; - reset-names = "dc"; - - iommus = <&mc TEGRA_SWGROUP_DCB>; - - nvidia,head = <1>; - }; - - hdmi: hdmi@54280000 { - compatible = "nvidia,tegra124-hdmi"; - reg = <0x0 0x54280000 0x0 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_HDMI>, - <&tegra_car TEGRA124_CLK_PLL_D2_OUT0>; - clock-names = "hdmi", "parent"; - resets = <&tegra_car 51>; - reset-names = "hdmi"; - status = "disabled"; - }; - - vic@54340000 { - compatible = "nvidia,tegra124-vic"; - reg = <0x0 0x54340000 0x0 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_VIC03>; - clock-names = "vic"; - resets = <&tegra_car 178>; - reset-names = "vic"; - - iommus = <&mc TEGRA_SWGROUP_VIC>; - }; - - sor@54540000 { - compatible = "nvidia,tegra124-sor"; - reg = <0x0 0x54540000 0x0 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_SOR0>, - <&tegra_car TEGRA124_CLK_SOR0_OUT>, - <&tegra_car TEGRA124_CLK_PLL_D_OUT0>, - <&tegra_car TEGRA124_CLK_PLL_DP>, - <&tegra_car TEGRA124_CLK_CLK_M>; - clock-names = "sor", "out", "parent", "dp", "safe"; - resets = <&tegra_car 182>; - reset-names = "sor"; - status = "disabled"; - }; - - dpaux: dpaux@545c0000 { - compatible = "nvidia,tegra124-dpaux"; - reg = <0x0 0x545c0000 0x0 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_DPAUX>, - <&tegra_car TEGRA124_CLK_PLL_DP>; - clock-names = "dpaux", "parent"; - resets = <&tegra_car 181>; - reset-names = "dpaux"; - status = "disabled"; - }; - }; - - gic: interrupt-controller@50041000 { - compatible = "arm,cortex-a15-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x0 0x50041000 0x0 0x1000>, - <0x0 0x50042000 0x0 0x1000>, - <0x0 0x50044000 0x0 0x2000>, - <0x0 0x50046000 0x0 0x2000>; - interrupts = ; - interrupt-parent = <&gic>; - }; - - /* - * Please keep the following 0, notation in place as a former mainline - * U-Boot version was looking for that particular notation in order to - * perform required fix-ups on that GPU node. - */ - gpu@0,57000000 { - compatible = "nvidia,gk20a"; - reg = <0x0 0x57000000 0x0 0x01000000>, - <0x0 0x58000000 0x0 0x01000000>; - interrupts = , - ; - interrupt-names = "stall", "nonstall"; - clocks = <&tegra_car TEGRA124_CLK_GPU>, - <&tegra_car TEGRA124_CLK_PLL_P_OUT5>; - clock-names = "gpu", "pwr"; - resets = <&tegra_car 184>; - reset-names = "gpu"; - - iommus = <&mc TEGRA_SWGROUP_GPU>; - - status = "disabled"; - }; - - lic: interrupt-controller@60004000 { - compatible = "nvidia,tegra124-ictlr", "nvidia,tegra30-ictlr"; - reg = <0x0 0x60004000 0x0 0x100>, - <0x0 0x60004100 0x0 0x100>, - <0x0 0x60004200 0x0 0x100>, - <0x0 0x60004300 0x0 0x100>, - <0x0 0x60004400 0x0 0x100>; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - }; - - timer@60005000 { - compatible = "nvidia,tegra124-timer", "nvidia,tegra30-timer", "nvidia,tegra20-timer"; - reg = <0x0 0x60005000 0x0 0x400>; - interrupts = , - , - , - , - , - ; - clocks = <&tegra_car TEGRA124_CLK_TIMER>; - }; - - tegra_car: clock@60006000 { - compatible = "nvidia,tegra124-car"; - reg = <0x0 0x60006000 0x0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - nvidia,external-memory-controller = <&emc>; - }; - - flow-controller@60007000 { - compatible = "nvidia,tegra124-flowctrl"; - reg = <0x0 0x60007000 0x0 0x1000>; - }; - - actmon@6000c800 { - compatible = "nvidia,tegra124-actmon"; - reg = <0x0 0x6000c800 0x0 0x400>; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_ACTMON>, - <&tegra_car TEGRA124_CLK_EMC>; - clock-names = "actmon", "emc"; - resets = <&tegra_car 119>; - reset-names = "actmon"; - }; - - gpio: gpio@6000d000 { - compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio"; - reg = <0x0 0x6000d000 0x0 0x1000>; - interrupts = , - , - , - , - , - , - , - ; - #gpio-cells = <2>; - gpio-controller; - #interrupt-cells = <2>; - interrupt-controller; - /* - gpio-ranges = <&pinmux 0 0 251>; - */ - }; - - apbdma: dma@60020000 { - compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma"; - reg = <0x0 0x60020000 0x0 0x1400>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - clocks = <&tegra_car TEGRA124_CLK_APBDMA>; - resets = <&tegra_car 34>; - reset-names = "dma"; - #dma-cells = <1>; - }; - - apbmisc@70000800 { - compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc"; - reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */ - <0x0 0x7000e864 0x0 0x04>; /* Strapping options */ - }; - - pinmux: pinmux@70000868 { - compatible = "nvidia,tegra124-pinmux"; - reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */ - <0x0 0x70003000 0x0 0x434>, /* Mux registers */ - <0x0 0x70000820 0x0 0x008>; /* MIPI pad control */ - }; - - /* - * There are two serial driver i.e. 8250 based simple serial - * driver and APB DMA based serial driver for higher baudrate - * and performace. To enable the 8250 based driver, the compatible - * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable - * the APB DMA based serial driver, the compatible is - * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". - */ - uarta: serial@70006000 { - compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; - reg = <0x0 0x70006000 0x0 0x40>; - reg-shift = <2>; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_UARTA>; - resets = <&tegra_car 6>; - reset-names = "serial"; - dmas = <&apbdma 8>, <&apbdma 8>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uartb: serial@70006040 { - compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; - reg = <0x0 0x70006040 0x0 0x40>; - reg-shift = <2>; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_UARTB>; - resets = <&tegra_car 7>; - reset-names = "serial"; - dmas = <&apbdma 9>, <&apbdma 9>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uartc: serial@70006200 { - compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; - reg = <0x0 0x70006200 0x0 0x40>; - reg-shift = <2>; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_UARTC>; - resets = <&tegra_car 55>; - reset-names = "serial"; - dmas = <&apbdma 10>, <&apbdma 10>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uartd: serial@70006300 { - compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; - reg = <0x0 0x70006300 0x0 0x40>; - reg-shift = <2>; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_UARTD>; - resets = <&tegra_car 65>; - reset-names = "serial"; - dmas = <&apbdma 19>, <&apbdma 19>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - pwm: pwm@7000a000 { - compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm"; - reg = <0x0 0x7000a000 0x0 0x100>; - #pwm-cells = <2>; - clocks = <&tegra_car TEGRA124_CLK_PWM>; - resets = <&tegra_car 17>; - reset-names = "pwm"; - status = "disabled"; - }; - - i2c@7000c000 { - compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; - reg = <0x0 0x7000c000 0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA124_CLK_I2C1>; - clock-names = "div-clk"; - resets = <&tegra_car 12>; - reset-names = "i2c"; - dmas = <&apbdma 21>, <&apbdma 21>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c@7000c400 { - compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; - reg = <0x0 0x7000c400 0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA124_CLK_I2C2>; - clock-names = "div-clk"; - resets = <&tegra_car 54>; - reset-names = "i2c"; - dmas = <&apbdma 22>, <&apbdma 22>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c@7000c500 { - compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; - reg = <0x0 0x7000c500 0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA124_CLK_I2C3>; - clock-names = "div-clk"; - resets = <&tegra_car 67>; - reset-names = "i2c"; - dmas = <&apbdma 23>, <&apbdma 23>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c@7000c700 { - compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; - reg = <0x0 0x7000c700 0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA124_CLK_I2C4>; - clock-names = "div-clk"; - resets = <&tegra_car 103>; - reset-names = "i2c"; - dmas = <&apbdma 26>, <&apbdma 26>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c@7000d000 { - compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; - reg = <0x0 0x7000d000 0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA124_CLK_I2C5>; - clock-names = "div-clk"; - resets = <&tegra_car 47>; - reset-names = "i2c"; - dmas = <&apbdma 24>, <&apbdma 24>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c@7000d100 { - compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; - reg = <0x0 0x7000d100 0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA124_CLK_I2C6>; - clock-names = "div-clk"; - resets = <&tegra_car 166>; - reset-names = "i2c"; - dmas = <&apbdma 30>, <&apbdma 30>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi@7000d400 { - compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; - reg = <0x0 0x7000d400 0x0 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA124_CLK_SBC1>; - clock-names = "spi"; - resets = <&tegra_car 41>; - reset-names = "spi"; - dmas = <&apbdma 15>, <&apbdma 15>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi@7000d600 { - compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; - reg = <0x0 0x7000d600 0x0 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA124_CLK_SBC2>; - clock-names = "spi"; - resets = <&tegra_car 44>; - reset-names = "spi"; - dmas = <&apbdma 16>, <&apbdma 16>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi@7000d800 { - compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; - reg = <0x0 0x7000d800 0x0 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA124_CLK_SBC3>; - clock-names = "spi"; - resets = <&tegra_car 46>; - reset-names = "spi"; - dmas = <&apbdma 17>, <&apbdma 17>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi@7000da00 { - compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; - reg = <0x0 0x7000da00 0x0 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA124_CLK_SBC4>; - clock-names = "spi"; - resets = <&tegra_car 68>; - reset-names = "spi"; - dmas = <&apbdma 18>, <&apbdma 18>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi@7000dc00 { - compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; - reg = <0x0 0x7000dc00 0x0 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA124_CLK_SBC5>; - clock-names = "spi"; - resets = <&tegra_car 104>; - reset-names = "spi"; - dmas = <&apbdma 27>, <&apbdma 27>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi@7000de00 { - compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; - reg = <0x0 0x7000de00 0x0 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA124_CLK_SBC6>; - clock-names = "spi"; - resets = <&tegra_car 105>; - reset-names = "spi"; - dmas = <&apbdma 28>, <&apbdma 28>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - rtc@7000e000 { - compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc"; - reg = <0x0 0x7000e000 0x0 0x100>; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_RTC>; - }; - - pmc@7000e400 { - compatible = "nvidia,tegra124-pmc"; - reg = <0x0 0x7000e400 0x0 0x400>; - clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>; - clock-names = "pclk", "clk32k_in"; - }; - - fuse@7000f800 { - compatible = "nvidia,tegra124-efuse"; - reg = <0x0 0x7000f800 0x0 0x400>; - clocks = <&tegra_car TEGRA124_CLK_FUSE>; - clock-names = "fuse"; - resets = <&tegra_car 39>; - reset-names = "fuse"; - }; - - mc: memory-controller@70019000 { - compatible = "nvidia,tegra124-mc"; - reg = <0x0 0x70019000 0x0 0x1000>; - clocks = <&tegra_car TEGRA124_CLK_MC>; - clock-names = "mc"; - - interrupts = ; - - #iommu-cells = <1>; - }; - - emc: external-memory-controller@7001b000 { - compatible = "nvidia,tegra124-emc"; - reg = <0x0 0x7001b000 0x0 0x1000>; - clocks = <&tegra_car TEGRA124_CLK_EMC>; - clock-names = "emc"; - - nvidia,memory-controller = <&mc>; - }; - - sata@70020000 { - compatible = "nvidia,tegra124-ahci"; - reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */ - <0x0 0x70020000 0x0 0x7000>; /* SATA */ - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_SATA>, - <&tegra_car TEGRA124_CLK_SATA_OOB>, - <&tegra_car TEGRA124_CLK_CML1>, - <&tegra_car TEGRA124_CLK_PLL_E>; - clock-names = "sata", "sata-oob", "cml1", "pll_e"; - resets = <&tegra_car 124>, - <&tegra_car 123>, - <&tegra_car 129>; - reset-names = "sata", "sata-oob", "sata-cold"; - status = "disabled"; - }; - - hda@70030000 { - compatible = "nvidia,tegra124-hda", "nvidia,tegra30-hda"; - reg = <0x0 0x70030000 0x0 0x10000>; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_HDA>, - <&tegra_car TEGRA124_CLK_HDA2HDMI>, - <&tegra_car TEGRA124_CLK_HDA2CODEC_2X>; - clock-names = "hda", "hda2hdmi", "hda2codec_2x"; - resets = <&tegra_car 125>, /* hda */ - <&tegra_car 128>, /* hda2hdmi */ - <&tegra_car 111>; /* hda2codec_2x */ - reset-names = "hda", "hda2hdmi", "hda2codec_2x"; - status = "disabled"; - }; - - usb@70090000 { - compatible = "nvidia,tegra124-xusb"; - reg = <0x0 0x70090000 0x0 0x8000>, - <0x0 0x70098000 0x0 0x1000>, - <0x0 0x70099000 0x0 0x1000>; - reg-names = "hcd", "fpci", "ipfs"; - - interrupts = , - ; - - clocks = <&tegra_car TEGRA124_CLK_XUSB_HOST>, - <&tegra_car TEGRA124_CLK_XUSB_HOST_SRC>, - <&tegra_car TEGRA124_CLK_XUSB_FALCON_SRC>, - <&tegra_car TEGRA124_CLK_XUSB_SS>, - <&tegra_car TEGRA124_CLK_XUSB_SS_DIV2>, - <&tegra_car TEGRA124_CLK_XUSB_SS_SRC>, - <&tegra_car TEGRA124_CLK_XUSB_HS_SRC>, - <&tegra_car TEGRA124_CLK_XUSB_FS_SRC>, - <&tegra_car TEGRA124_CLK_PLL_U_480M>, - <&tegra_car TEGRA124_CLK_CLK_M>, - <&tegra_car TEGRA124_CLK_PLL_E>; - clock-names = "xusb_host", "xusb_host_src", - "xusb_falcon_src", "xusb_ss", - "xusb_ss_div2", "xusb_ss_src", - "xusb_hs_src", "xusb_fs_src", - "pll_u_480m", "clk_m", "pll_e"; - resets = <&tegra_car 89>, <&tegra_car 156>, - <&tegra_car 143>; - reset-names = "xusb_host", "xusb_ss", "xusb_src"; - - nvidia,xusb-padctl = <&padctl>; - - status = "disabled"; - }; - - padctl: padctl@7009f000 { - compatible = "nvidia,tegra124-xusb-padctl"; - reg = <0x0 0x7009f000 0x0 0x1000>; - resets = <&tegra_car 142>; - reset-names = "padctl"; - - pads { - usb2 { - status = "disabled"; - - lanes { - usb2-0 { - status = "disabled"; - #phy-cells = <0>; - }; - - usb2-1 { - status = "disabled"; - #phy-cells = <0>; - }; - - usb2-2 { - status = "disabled"; - #phy-cells = <0>; - }; - }; - }; - - ulpi { - status = "disabled"; - - lanes { - ulpi-0 { - status = "disabled"; - #phy-cells = <0>; - }; - }; - }; - - hsic { - status = "disabled"; - - lanes { - hsic-0 { - status = "disabled"; - #phy-cells = <0>; - }; - - hsic-1 { - status = "disabled"; - #phy-cells = <0>; - }; - }; - }; - - pcie { - status = "disabled"; - - lanes { - pcie-0 { - status = "disabled"; - #phy-cells = <0>; - }; - - pcie-1 { - status = "disabled"; - #phy-cells = <0>; - }; - - pcie-2 { - status = "disabled"; - #phy-cells = <0>; - }; - - pcie-3 { - status = "disabled"; - #phy-cells = <0>; - }; - - pcie-4 { - status = "disabled"; - #phy-cells = <0>; - }; - }; - }; - - sata { - status = "disabled"; - - lanes { - sata-0 { - status = "disabled"; - #phy-cells = <0>; - }; - }; - }; - }; - - ports { - usb2-0 { - status = "disabled"; - }; - - usb2-1 { - status = "disabled"; - }; - - usb2-2 { - status = "disabled"; - }; - - ulpi-0 { - status = "disabled"; - }; - - hsic-0 { - status = "disabled"; - }; - - hsic-1 { - status = "disabled"; - }; - - usb3-0 { - status = "disabled"; - }; - - usb3-1 { - status = "disabled"; - }; - }; - }; - - sdhci@700b0000 { - compatible = "nvidia,tegra124-sdhci"; - reg = <0x0 0x700b0000 0x0 0x200>; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_SDMMC1>; - resets = <&tegra_car 14>; - reset-names = "sdhci"; - status = "disabled"; - }; - - sdhci@700b0200 { - compatible = "nvidia,tegra124-sdhci"; - reg = <0x0 0x700b0200 0x0 0x200>; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_SDMMC2>; - resets = <&tegra_car 9>; - reset-names = "sdhci"; - status = "disabled"; - }; - - sdhci@700b0400 { - compatible = "nvidia,tegra124-sdhci"; - reg = <0x0 0x700b0400 0x0 0x200>; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_SDMMC3>; - resets = <&tegra_car 69>; - reset-names = "sdhci"; - status = "disabled"; - }; - - sdhci@700b0600 { - compatible = "nvidia,tegra124-sdhci"; - reg = <0x0 0x700b0600 0x0 0x200>; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_SDMMC4>; - resets = <&tegra_car 15>; - reset-names = "sdhci"; - status = "disabled"; - }; - - cec@70015000 { - compatible = "nvidia,tegra124-cec"; - reg = <0x0 0x70015000 0x0 0x00001000>; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_CEC>; - clock-names = "cec"; - status = "disabled"; - hdmi-phandle = <&hdmi>; - }; - - soctherm: thermal-sensor@700e2000 { - compatible = "nvidia,tegra124-soctherm"; - reg = <0x0 0x700e2000 0x0 0x600 /* SOC_THERM reg_base */ - 0x0 0x60006000 0x0 0x400>; /* CAR reg_base */ - reg-names = "soctherm-reg", "car-reg"; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_TSENSOR>, - <&tegra_car TEGRA124_CLK_SOC_THERM>; - clock-names = "tsensor", "soctherm"; - resets = <&tegra_car 78>; - reset-names = "soctherm"; - #thermal-sensor-cells = <1>; - - throttle-cfgs { - throttle_heavy: heavy { - nvidia,priority = <100>; - nvidia,cpu-throt-percent = <85>; - - #cooling-cells = <2>; - }; - }; - }; - - dfll: clock@70110000 { - compatible = "nvidia,tegra124-dfll"; - reg = <0 0x70110000 0 0x100>, /* DFLL control */ - <0 0x70110000 0 0x100>, /* I2C output control */ - <0 0x70110100 0 0x100>, /* Integrated I2C controller */ - <0 0x70110200 0 0x100>; /* Look-up table RAM */ - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_DFLL_SOC>, - <&tegra_car TEGRA124_CLK_DFLL_REF>, - <&tegra_car TEGRA124_CLK_I2C5>; - clock-names = "soc", "ref", "i2c"; - resets = <&tegra_car TEGRA124_RST_DFLL_DVCO>; - reset-names = "dvco"; - #clock-cells = <0>; - clock-output-names = "dfllCPU_out"; - nvidia,sample-rate = <12500>; - nvidia,droop-ctrl = <0x00000f00>; - nvidia,force-mode = <1>; - nvidia,cf = <10>; - nvidia,ci = <0>; - nvidia,cg = <2>; - status = "disabled"; - }; - - ahub@70300000 { - compatible = "nvidia,tegra124-ahub"; - reg = <0x0 0x70300000 0x0 0x200>, - <0x0 0x70300800 0x0 0x800>, - <0x0 0x70300200 0x0 0x600>; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>, - <&tegra_car TEGRA124_CLK_APBIF>; - clock-names = "d_audio", "apbif"; - resets = <&tegra_car 106>, /* d_audio */ - <&tegra_car 107>, /* apbif */ - <&tegra_car 30>, /* i2s0 */ - <&tegra_car 11>, /* i2s1 */ - <&tegra_car 18>, /* i2s2 */ - <&tegra_car 101>, /* i2s3 */ - <&tegra_car 102>, /* i2s4 */ - <&tegra_car 108>, /* dam0 */ - <&tegra_car 109>, /* dam1 */ - <&tegra_car 110>, /* dam2 */ - <&tegra_car 10>, /* spdif */ - <&tegra_car 153>, /* amx */ - <&tegra_car 185>, /* amx1 */ - <&tegra_car 154>, /* adx */ - <&tegra_car 180>, /* adx1 */ - <&tegra_car 186>, /* afc0 */ - <&tegra_car 187>, /* afc1 */ - <&tegra_car 188>, /* afc2 */ - <&tegra_car 189>, /* afc3 */ - <&tegra_car 190>, /* afc4 */ - <&tegra_car 191>; /* afc5 */ - reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", - "i2s3", "i2s4", "dam0", "dam1", "dam2", - "spdif", "amx", "amx1", "adx", "adx1", - "afc0", "afc1", "afc2", "afc3", "afc4", "afc5"; - dmas = <&apbdma 1>, <&apbdma 1>, - <&apbdma 2>, <&apbdma 2>, - <&apbdma 3>, <&apbdma 3>, - <&apbdma 4>, <&apbdma 4>, - <&apbdma 6>, <&apbdma 6>, - <&apbdma 7>, <&apbdma 7>, - <&apbdma 12>, <&apbdma 12>, - <&apbdma 13>, <&apbdma 13>, - <&apbdma 14>, <&apbdma 14>, - <&apbdma 29>, <&apbdma 29>; - dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2", - "rx3", "tx3", "rx4", "tx4", "rx5", "tx5", - "rx6", "tx6", "rx7", "tx7", "rx8", "tx8", - "rx9", "tx9"; - ranges; - #address-cells = <2>; - #size-cells = <2>; - - tegra_i2s0: i2s@70301000 { - compatible = "nvidia,tegra124-i2s"; - reg = <0x0 0x70301000 0x0 0x100>; - nvidia,ahub-cif-ids = <4 4>; - clocks = <&tegra_car TEGRA124_CLK_I2S0>; - resets = <&tegra_car 30>; - reset-names = "i2s"; - status = "disabled"; - }; - - tegra_i2s1: i2s@70301100 { - compatible = "nvidia,tegra124-i2s"; - reg = <0x0 0x70301100 0x0 0x100>; - nvidia,ahub-cif-ids = <5 5>; - clocks = <&tegra_car TEGRA124_CLK_I2S1>; - resets = <&tegra_car 11>; - reset-names = "i2s"; - status = "disabled"; - }; - - tegra_i2s2: i2s@70301200 { - compatible = "nvidia,tegra124-i2s"; - reg = <0x0 0x70301200 0x0 0x100>; - nvidia,ahub-cif-ids = <6 6>; - clocks = <&tegra_car TEGRA124_CLK_I2S2>; - resets = <&tegra_car 18>; - reset-names = "i2s"; - status = "disabled"; - }; - - tegra_i2s3: i2s@70301300 { - compatible = "nvidia,tegra124-i2s"; - reg = <0x0 0x70301300 0x0 0x100>; - nvidia,ahub-cif-ids = <7 7>; - clocks = <&tegra_car TEGRA124_CLK_I2S3>; - resets = <&tegra_car 101>; - reset-names = "i2s"; - status = "disabled"; - }; - - tegra_i2s4: i2s@70301400 { - compatible = "nvidia,tegra124-i2s"; - reg = <0x0 0x70301400 0x0 0x100>; - nvidia,ahub-cif-ids = <8 8>; - clocks = <&tegra_car TEGRA124_CLK_I2S4>; - resets = <&tegra_car 102>; - reset-names = "i2s"; - status = "disabled"; - }; - }; - - usb@7d000000 { - compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; - reg = <0x0 0x7d000000 0x0 0x4000>; - interrupts = ; - phy_type = "utmi"; - clocks = <&tegra_car TEGRA124_CLK_USBD>; - resets = <&tegra_car 22>; - reset-names = "usb"; - nvidia,phy = <&phy1>; - status = "disabled"; - }; - - phy1: usb-phy@7d000000 { - compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; - reg = <0x0 0x7d000000 0x0 0x4000>, - <0x0 0x7d000000 0x0 0x4000>; - phy_type = "utmi"; - clocks = <&tegra_car TEGRA124_CLK_USBD>, - <&tegra_car TEGRA124_CLK_PLL_U>, - <&tegra_car TEGRA124_CLK_USBD>; - clock-names = "reg", "pll_u", "utmi-pads"; - resets = <&tegra_car 22>, <&tegra_car 22>; - reset-names = "usb", "utmi-pads"; - nvidia,hssync-start-delay = <0>; - nvidia,idle-wait-delay = <17>; - nvidia,elastic-limit = <16>; - nvidia,term-range-adj = <6>; - nvidia,xcvr-setup = <9>; - nvidia,xcvr-lsfslew = <0>; - nvidia,xcvr-lsrslew = <3>; - nvidia,hssquelch-level = <2>; - nvidia,hsdiscon-level = <5>; - nvidia,xcvr-hsslew = <12>; - nvidia,has-utmi-pad-registers; - status = "disabled"; - }; - - usb@7d004000 { - compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; - reg = <0x0 0x7d004000 0x0 0x4000>; - interrupts = ; - phy_type = "utmi"; - clocks = <&tegra_car TEGRA124_CLK_USB2>; - resets = <&tegra_car 58>; - reset-names = "usb"; - nvidia,phy = <&phy2>; - status = "disabled"; - }; - - phy2: usb-phy@7d004000 { - compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; - reg = <0x0 0x7d004000 0x0 0x4000>, - <0x0 0x7d000000 0x0 0x4000>; - phy_type = "utmi"; - clocks = <&tegra_car TEGRA124_CLK_USB2>, - <&tegra_car TEGRA124_CLK_PLL_U>, - <&tegra_car TEGRA124_CLK_USBD>; - clock-names = "reg", "pll_u", "utmi-pads"; - resets = <&tegra_car 58>, <&tegra_car 22>; - reset-names = "usb", "utmi-pads"; - nvidia,hssync-start-delay = <0>; - nvidia,idle-wait-delay = <17>; - nvidia,elastic-limit = <16>; - nvidia,term-range-adj = <6>; - nvidia,xcvr-setup = <9>; - nvidia,xcvr-lsfslew = <0>; - nvidia,xcvr-lsrslew = <3>; - nvidia,hssquelch-level = <2>; - nvidia,hsdiscon-level = <5>; - nvidia,xcvr-hsslew = <12>; - status = "disabled"; - }; - - usb@7d008000 { - compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; - reg = <0x0 0x7d008000 0x0 0x4000>; - interrupts = ; - phy_type = "utmi"; - clocks = <&tegra_car TEGRA124_CLK_USB3>; - resets = <&tegra_car 59>; - reset-names = "usb"; - nvidia,phy = <&phy3>; - status = "disabled"; - }; - - phy3: usb-phy@7d008000 { - compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; - reg = <0x0 0x7d008000 0x0 0x4000>, - <0x0 0x7d000000 0x0 0x4000>; - phy_type = "utmi"; - clocks = <&tegra_car TEGRA124_CLK_USB3>, - <&tegra_car TEGRA124_CLK_PLL_U>, - <&tegra_car TEGRA124_CLK_USBD>; - clock-names = "reg", "pll_u", "utmi-pads"; - resets = <&tegra_car 59>, <&tegra_car 22>; - reset-names = "usb", "utmi-pads"; - nvidia,hssync-start-delay = <0>; - nvidia,idle-wait-delay = <17>; - nvidia,elastic-limit = <16>; - nvidia,term-range-adj = <6>; - nvidia,xcvr-setup = <9>; - nvidia,xcvr-lsfslew = <0>; - nvidia,xcvr-lsrslew = <3>; - nvidia,hssquelch-level = <2>; - nvidia,hsdiscon-level = <5>; - nvidia,xcvr-hsslew = <12>; - status = "disabled"; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0>; - - clocks = <&tegra_car TEGRA124_CLK_CCLK_G>, - <&tegra_car TEGRA124_CLK_CCLK_LP>, - <&tegra_car TEGRA124_CLK_PLL_X>, - <&tegra_car TEGRA124_CLK_PLL_P>, - <&dfll>; - clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll"; - /* FIXME: what's the actual transition time? */ - clock-latency = <300000>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <1>; - }; - - cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <2>; - }; - - cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <3>; - }; - }; - - pmu { - compatible = "arm,cortex-a15-pmu"; - interrupts = , - , - , - ; - interrupt-affinity = <&{/cpus/cpu@0}>, - <&{/cpus/cpu@1}>, - <&{/cpus/cpu@2}>, - <&{/cpus/cpu@3}>; - }; - - thermal-zones { - cpu { - polling-delay-passive = <1000>; - polling-delay = <1000>; - - thermal-sensors = - <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>; - - trips { - cpu-shutdown-trip { - temperature = <103000>; - hysteresis = <0>; - type = "critical"; - }; - cpu_throttle_trip: throttle-trip { - temperature = <100000>; - hysteresis = <1000>; - type = "hot"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu_throttle_trip>; - cooling-device = <&throttle_heavy 1 1>; - }; - }; - }; - - mem { - polling-delay-passive = <1000>; - polling-delay = <1000>; - - thermal-sensors = - <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>; - - trips { - mem-shutdown-trip { - temperature = <103000>; - hysteresis = <0>; - type = "critical"; - }; - }; - - cooling-maps { - /* - * There are currently no cooling maps, - * because there are no cooling devices. - */ - }; - }; - - gpu { - polling-delay-passive = <1000>; - polling-delay = <1000>; - - thermal-sensors = - <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>; - - trips { - gpu-shutdown-trip { - temperature = <101000>; - hysteresis = <0>; - type = "critical"; - }; - gpu_throttle_trip: throttle-trip { - temperature = <99000>; - hysteresis = <1000>; - type = "hot"; - }; - }; - - cooling-maps { - map0 { - trip = <&gpu_throttle_trip>; - cooling-device = <&throttle_heavy 1 1>; - }; - }; - }; - - pllx { - polling-delay-passive = <1000>; - polling-delay = <1000>; - - thermal-sensors = - <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>; - - trips { - pllx-shutdown-trip { - temperature = <103000>; - hysteresis = <0>; - type = "critical"; - }; - }; - - cooling-maps { - /* - * There are currently no cooling maps, - * because there are no cooling devices. - */ - }; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; - interrupt-parent = <&gic>; - }; -}; diff --git a/sys/gnu/dts/arm/tegra20-colibri-512.dtsi b/sys/gnu/dts/arm/tegra20-colibri-512.dtsi deleted file mode 100644 index 8e0066ad962..00000000000 --- a/sys/gnu/dts/arm/tegra20-colibri-512.dtsi +++ /dev/null @@ -1,533 +0,0 @@ -#include "tegra20.dtsi" - -/ { - model = "Toradex Colibri T20 512MB"; - compatible = "toradex,colibri_t20-512", "nvidia,tegra20"; - - aliases { - rtc0 = "/i2c@7000d000/tps6586x@34"; - rtc1 = "/rtc@7000e000"; - }; - - memory { - reg = <0x00000000 0x20000000>; - }; - - host1x@50000000 { - hdmi@54280000 { - vdd-supply = <&hdmi_vdd_reg>; - pll-supply = <&hdmi_pll_reg>; - - nvidia,ddc-i2c-bus = <&i2c_ddc>; - nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) - GPIO_ACTIVE_HIGH>; - }; - }; - - pinmux@70000014 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - audio_refclk { - nvidia,pins = "cdev1"; - nvidia,function = "plla_out"; - nvidia,pull = ; - nvidia,tristate = ; - }; - crt { - nvidia,pins = "crtp"; - nvidia,function = "crt"; - nvidia,pull = ; - nvidia,tristate = ; - }; - dap3 { - nvidia,pins = "dap3"; - nvidia,function = "dap3"; - nvidia,pull = ; - nvidia,tristate = ; - }; - displaya { - nvidia,pins = "ld0", "ld1", "ld2", "ld3", - "ld4", "ld5", "ld6", "ld7", "ld8", - "ld9", "ld10", "ld11", "ld12", "ld13", - "ld14", "ld15", "ld16", "ld17", - "lhs", "lpw0", "lpw2", "lsc0", - "lsc1", "lsck", "lsda", "lspi", "lvs"; - nvidia,function = "displaya"; - nvidia,tristate = ; - }; - gpio_dte { - nvidia,pins = "dte"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - }; - gpio_gmi { - nvidia,pins = "ata", "atc", "atd", "ate", - "dap1", "dap2", "dap4", "gpu", "irrx", - "irtx", "spia", "spib", "spic"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - }; - gpio_pta { - nvidia,pins = "pta"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - }; - gpio_uac { - nvidia,pins = "uac"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - }; - hdint { - nvidia,pins = "hdint"; - nvidia,function = "hdmi"; - nvidia,tristate = ; - }; - i2c1 { - nvidia,pins = "rm"; - nvidia,function = "i2c1"; - nvidia,pull = ; - nvidia,tristate = ; - }; - i2c3 { - nvidia,pins = "dtf"; - nvidia,function = "i2c3"; - nvidia,pull = ; - nvidia,tristate = ; - }; - i2cddc { - nvidia,pins = "ddc"; - nvidia,function = "i2c2"; - nvidia,pull = ; - nvidia,tristate = ; - }; - i2cp { - nvidia,pins = "i2cp"; - nvidia,function = "i2cp"; - nvidia,pull = ; - nvidia,tristate = ; - }; - irda { - nvidia,pins = "uad"; - nvidia,function = "irda"; - nvidia,pull = ; - nvidia,tristate = ; - }; - nand { - nvidia,pins = "kbca", "kbcc", "kbcd", - "kbce", "kbcf"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - }; - owc { - nvidia,pins = "owc"; - nvidia,function = "owr"; - nvidia,pull = ; - nvidia,tristate = ; - }; - pmc { - nvidia,pins = "pmc"; - nvidia,function = "pwr_on"; - nvidia,tristate = ; - }; - pwm { - nvidia,pins = "sdb", "sdc", "sdd"; - nvidia,function = "pwm"; - nvidia,tristate = ; - }; - sdio4 { - nvidia,pins = "atb", "gma", "gme"; - nvidia,function = "sdio4"; - nvidia,pull = ; - nvidia,tristate = ; - }; - spi1 { - nvidia,pins = "spid", "spie", "spif"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - }; - spi4 { - nvidia,pins = "slxa", "slxc", "slxd", "slxk"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - }; - uarta { - nvidia,pins = "sdio1"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - }; - uartd { - nvidia,pins = "gmc"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - }; - ulpi { - nvidia,pins = "uaa", "uab", "uda"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - }; - ulpi_refclk { - nvidia,pins = "cdev2"; - nvidia,function = "pllp_out4"; - nvidia,pull = ; - nvidia,tristate = ; - }; - usb_gpio { - nvidia,pins = "spig", "spih"; - nvidia,function = "spi2_alt"; - nvidia,pull = ; - nvidia,tristate = ; - }; - vi { - nvidia,pins = "dta", "dtb", "dtc", "dtd"; - nvidia,function = "vi"; - nvidia,pull = ; - nvidia,tristate = ; - }; - vi_sc { - nvidia,pins = "csus"; - nvidia,function = "vi_sensor_clk"; - nvidia,pull = ; - nvidia,tristate = ; - }; - }; - }; - - ac97: ac97@70002000 { - status = "okay"; - nvidia,codec-reset-gpio = <&gpio TEGRA_GPIO(V, 0) - GPIO_ACTIVE_HIGH>; - nvidia,codec-sync-gpio = <&gpio TEGRA_GPIO(P, 0) - GPIO_ACTIVE_HIGH>; - }; - - i2c@7000c000 { - clock-frequency = <400000>; - }; - - i2c_ddc: i2c@7000c400 { - clock-frequency = <100000>; - }; - - i2c@7000c500 { - clock-frequency = <400000>; - }; - - i2c@7000d000 { - status = "okay"; - clock-frequency = <400000>; - - pmic: tps6586x@34 { - compatible = "ti,tps6586x"; - reg = <0x34>; - interrupts = ; - - ti,system-power-controller; - - #gpio-cells = <2>; - gpio-controller; - - sys-supply = <&vdd_3v3_reg>; - vin-sm0-supply = <&sys_reg>; - vin-sm1-supply = <&sys_reg>; - vin-sm2-supply = <&sys_reg>; - vinldo01-supply = <&sm2_reg>; - vinldo23-supply = <&vdd_3v3_reg>; - vinldo4-supply = <&vdd_3v3_reg>; - vinldo678-supply = <&vdd_3v3_reg>; - vinldo9-supply = <&vdd_3v3_reg>; - - regulators { - #address-cells = <1>; - #size-cells = <0>; - - sys_reg: regulator@0 { - reg = <0>; - regulator-compatible = "sys"; - regulator-name = "vdd_sys"; - regulator-always-on; - }; - - regulator@1 { - reg = <1>; - regulator-compatible = "sm0"; - regulator-name = "vdd_sm0,vdd_core"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - regulator@2 { - reg = <2>; - regulator-compatible = "sm1"; - regulator-name = "vdd_sm1,vdd_cpu"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - sm2_reg: regulator@3 { - reg = <3>; - regulator-compatible = "sm2"; - regulator-name = "vdd_sm2,vin_ldo*"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - /* LDO0 is not connected to anything */ - - regulator@5 { - reg = <5>; - regulator-compatible = "ldo1"; - regulator-name = "vdd_ldo1,avdd_pll*"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - regulator@6 { - reg = <6>; - regulator-compatible = "ldo2"; - regulator-name = "vdd_ldo2,vdd_rtc"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - /* LDO3 is not connected to anything */ - - regulator@8 { - reg = <8>; - regulator-compatible = "ldo4"; - regulator-name = "vdd_ldo4,avdd_osc,vddio_sys"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo5_reg: regulator@9 { - reg = <9>; - regulator-compatible = "ldo5"; - regulator-name = "vdd_ldo5,vdd_fuse"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - regulator@10 { - reg = <10>; - regulator-compatible = "ldo6"; - regulator-name = "vdd_ldo6,avdd_vdac,vddio_vi,vddio_cam"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - hdmi_vdd_reg: regulator@11 { - reg = <11>; - regulator-compatible = "ldo7"; - regulator-name = "vdd_ldo7,avdd_hdmi"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - hdmi_pll_reg: regulator@12 { - reg = <12>; - regulator-compatible = "ldo8"; - regulator-name = "vdd_ldo8,avdd_hdmi_pll"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - regulator@13 { - reg = <13>; - regulator-compatible = "ldo9"; - regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - regulator-always-on; - }; - - regulator@14 { - reg = <14>; - regulator-compatible = "ldo_rtc"; - regulator-name = "vdd_rtc_out,vdd_cell"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; - - temperature-sensor@4c { - compatible = "national,lm95245"; - reg = <0x4c>; - }; - }; - - pmc@7000e400 { - nvidia,suspend-mode = <1>; - nvidia,cpu-pwr-good-time = <5000>; - nvidia,cpu-pwr-off-time = <5000>; - nvidia,core-pwr-good-time = <3845 3845>; - nvidia,core-pwr-off-time = <3875>; - nvidia,sys-clock-req-active-high; - }; - - memory-controller@7000f400 { - emc-table@83250 { - reg = <83250>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <83250>; - nvidia,emc-registers = <0x00000005 0x00000011 - 0x00000004 0x00000002 0x00000004 0x00000004 - 0x00000001 0x0000000a 0x00000002 0x00000002 - 0x00000001 0x00000001 0x00000003 0x00000004 - 0x00000003 0x00000009 0x0000000c 0x0000025f - 0x00000000 0x00000003 0x00000003 0x00000002 - 0x00000002 0x00000001 0x00000008 0x000000c8 - 0x00000003 0x00000005 0x00000003 0x0000000c - 0x00000002 0x00000000 0x00000000 0x00000002 - 0x00000000 0x00000000 0x00000083 0x00520006 - 0x00000010 0x00000008 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000>; - }; - emc-table@133200 { - reg = <133200>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <133200>; - nvidia,emc-registers = <0x00000008 0x00000019 - 0x00000006 0x00000002 0x00000004 0x00000004 - 0x00000001 0x0000000a 0x00000002 0x00000002 - 0x00000002 0x00000001 0x00000003 0x00000004 - 0x00000003 0x00000009 0x0000000c 0x0000039f - 0x00000000 0x00000003 0x00000003 0x00000002 - 0x00000002 0x00000001 0x00000008 0x000000c8 - 0x00000003 0x00000007 0x00000003 0x0000000c - 0x00000002 0x00000000 0x00000000 0x00000002 - 0x00000000 0x00000000 0x00000083 0x00510006 - 0x00000010 0x00000008 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000>; - }; - emc-table@166500 { - reg = <166500>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <166500>; - nvidia,emc-registers = <0x0000000a 0x00000021 - 0x00000008 0x00000003 0x00000004 0x00000004 - 0x00000002 0x0000000a 0x00000003 0x00000003 - 0x00000002 0x00000001 0x00000003 0x00000004 - 0x00000003 0x00000009 0x0000000c 0x000004df - 0x00000000 0x00000003 0x00000003 0x00000003 - 0x00000003 0x00000001 0x00000009 0x000000c8 - 0x00000003 0x00000009 0x00000004 0x0000000c - 0x00000002 0x00000000 0x00000000 0x00000002 - 0x00000000 0x00000000 0x00000083 0x004f0006 - 0x00000010 0x00000008 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000>; - }; - emc-table@333000 { - reg = <333000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <333000>; - nvidia,emc-registers = <0x00000014 0x00000041 - 0x0000000f 0x00000005 0x00000004 0x00000005 - 0x00000003 0x0000000a 0x00000005 0x00000005 - 0x00000004 0x00000001 0x00000003 0x00000004 - 0x00000003 0x00000009 0x0000000c 0x000009ff - 0x00000000 0x00000003 0x00000003 0x00000005 - 0x00000005 0x00000001 0x0000000e 0x000000c8 - 0x00000003 0x00000011 0x00000006 0x0000000c - 0x00000002 0x00000000 0x00000000 0x00000002 - 0x00000000 0x00000000 0x00000083 0x00380006 - 0x00000010 0x00000008 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000>; - }; - }; - - usb@c5004000 { - status = "okay"; - nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) - GPIO_ACTIVE_LOW>; - }; - - usb-phy@c5004000 { - status = "okay"; - nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) - GPIO_ACTIVE_LOW>; - }; - - sdhci@c8000600 { - cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>; - }; - - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock@0 { - compatible = "fixed-clock"; - reg=<0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - vdd_3v3_reg: regulator@100 { - compatible = "regulator-fixed"; - reg = <100>; - regulator-name = "vdd_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - regulator@101 { - compatible = "regulator-fixed"; - reg = <101>; - regulator-name = "internal_usb"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-boot-on; - regulator-always-on; - gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>; - }; - }; - - sound { - compatible = "nvidia,tegra-audio-wm9712-colibri_t20", - "nvidia,tegra-audio-wm9712"; - nvidia,model = "Colibri T20 AC97 Audio"; - - nvidia,audio-routing = - "Headphone", "HPOUTL", - "Headphone", "HPOUTR", - "LineIn", "LINEINL", - "LineIn", "LINEINR", - "Mic", "MIC1"; - - nvidia,ac97-controller = <&ac97>; - - clocks = <&tegra_car TEGRA20_CLK_PLL_A>, - <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA20_CLK_CDEV1>; - clock-names = "pll_a", "pll_a_out0", "mclk"; - }; -}; diff --git a/sys/gnu/dts/arm/tegra20-colibri-eval-v3.dts b/sys/gnu/dts/arm/tegra20-colibri-eval-v3.dts deleted file mode 100644 index 3c0f2681fcd..00000000000 --- a/sys/gnu/dts/arm/tegra20-colibri-eval-v3.dts +++ /dev/null @@ -1,262 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT -/dts-v1/; - -#include -#include "tegra20-colibri.dtsi" - -/ { - model = "Toradex Colibri T20 on Colibri Evaluation Board"; - compatible = "toradex,colibri_t20-eval-v3", "toradex,colibri_t20", - "nvidia,tegra20"; - - aliases { - rtc0 = "/i2c@7000c000/rtc@68"; - rtc1 = "/i2c@7000d000/pmic@34"; - rtc2 = "/rtc@7000e000"; - serial0 = &uarta; - serial1 = &uartd; - serial2 = &uartb; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - host1x@50000000 { - dc@54200000 { - rgb { - status = "okay"; - nvidia,panel = <&panel>; - }; - }; - - hdmi@54280000 { - status = "okay"; - hdmi-supply = <®_5v0>; - }; - }; - - pinmux@70000014 { - state_default: pinmux { - bl-on { - nvidia,tristate = ; - }; - - ddc { - nvidia,tristate = ; - }; - - hotplug-detect { - nvidia,tristate = ; - }; - - i2c { - nvidia,tristate = ; - }; - - lcd { - nvidia,tristate = ; - }; - - lm1 { - nvidia,tristate = ; - }; - - mmc { - nvidia,tristate = ; - }; - - mmccd { - nvidia,tristate = ; - }; - - pwm-a-b { - nvidia,tristate = ; - }; - - pwm-c-d { - nvidia,tristate = ; - }; - - ssp { - nvidia,tristate = ; - }; - - uart-a { - nvidia,tristate = ; - }; - - uart-b { - nvidia,tristate = ; - }; - - uart-c { - nvidia,tristate = ; - }; - - usbh-pen { - nvidia,tristate = ; - }; - }; - }; - - /* Colibri UART-A */ - serial@70006000 { - status = "okay"; - }; - - /* Colibri UART-C */ - serial@70006040 { - status = "okay"; - }; - - /* Colibri UART-B */ - serial@70006300 { - status = "okay"; - }; - - pwm@7000a000 { - status = "okay"; - }; - - /* - * GEN1_I2C: I2C_SDA/SCL on SODIMM pin 194/196 (e.g. RTC on carrier - * board) - */ - i2c@7000c000 { - status = "okay"; - clock-frequency = <400000>; - - /* M41T0M6 real time clock on carrier board */ - rtc@68 { - compatible = "st,m41t0"; - reg = <0x68>; - }; - }; - - /* GEN2_I2C: unused */ - - /* CAM_I2C (I2C3): unused */ - - /* DDC_CLOCK/DATA on X3 pin 15/16 (e.g. display EDID) */ - i2c@7000c400 { - status = "okay"; - }; - - /* EHCI instance 0: USB1_DP/N -> USBC_P/N */ - usb@c5000000 { - status = "okay"; - dr_mode = "otg"; - }; - - usb-phy@c5000000 { - status = "okay"; - vbus-supply = <®_usbc_vbus>; - }; - - /* EHCI instance 2: USB3_DP/N -> USBH_P/N */ - usb@c5008000 { - status = "okay"; - }; - - usb-phy@c5008000 { - status = "okay"; - vbus-supply = <®_usbh_vbus>; - }; - - /* SPI4: Colibri SSP */ - spi@7000da00 { - status = "okay"; - spi-max-frequency = <25000000>; - - can@0 { - compatible = "microchip,mcp2515"; - reg = <0>; - clocks = <&clk16m>; - interrupt-parent = <&gpio>; - /* CAN_INT */ - interrupts = ; - spi-max-frequency = <10000000>; - vdd-supply = <®_3v3>; - xceiver-supply = <®_5v0>; - }; - }; - - /* SD/MMC */ - sdhci@c8000600 { - status = "okay"; - bus-width = <4>; - cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>; /* MMCD */ - no-1-8-v; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - brightness-levels = <255 128 64 32 16 8 4 0>; - default-brightness-level = <6>; - /* BL_ON */ - enable-gpios = <&gpio TEGRA_GPIO(T, 4) GPIO_ACTIVE_HIGH>; - power-supply = <®_3v3>; - pwms = <&pwm 0 5000000>; /* PWM */ - }; - - clk16m: osc3 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <16000000>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - wakeup { - label = "SODIMM pin 45 wakeup"; - gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>; - linux,code = ; - debounce-interval = <10>; - wakeup-source; - }; - }; - - panel: panel { - /* - * edt,et057090dhu: EDT 5.7" LCD TFT - * edt,et070080dh6: EDT 7.0" LCD TFT - */ - compatible = "edt,et057090dhu", "simple-panel"; - backlight = <&backlight>; - power-supply = <®_3v3>; - }; - - reg_3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "3.3V_SW"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_5v0: regulator-5v0 { - compatible = "regulator-fixed"; - regulator-name = "5V_SW"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_usbc_vbus: regulator-usbc-vbus { - compatible = "regulator-fixed"; - regulator-name = "VCC_USB5"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <®_5v0>; - }; - - /* USBH_PEN resp. USB_P_EN */ - reg_usbh_vbus: regulator-usbh-vbus { - compatible = "regulator-fixed"; - regulator-name = "VCC_USB[1-4]"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; - vin-supply = <®_5v0>; - }; -}; diff --git a/sys/gnu/dts/arm/tegra20-colibri-iris.dts b/sys/gnu/dts/arm/tegra20-colibri-iris.dts deleted file mode 100644 index d8004d68efa..00000000000 --- a/sys/gnu/dts/arm/tegra20-colibri-iris.dts +++ /dev/null @@ -1,244 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include -#include "tegra20-colibri.dtsi" - -/ { - model = "Toradex Colibri T20 on Iris"; - compatible = "toradex,colibri_t20-iris", "toradex,colibri_t20", - "nvidia,tegra20"; - - aliases { - rtc0 = "/i2c@7000c000/rtc@68"; - rtc1 = "/i2c@7000d000/pmic@34"; - rtc2 = "/rtc@7000e000"; - serial0 = &uarta; - serial1 = &uartd; - serial2 = &uartb; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - host1x@50000000 { - dc@54200000 { - rgb { - status = "okay"; - nvidia,panel = <&panel>; - }; - }; - - hdmi@54280000 { - status = "okay"; - hdmi-supply = <®_5v0>; - }; - }; - - pinmux@70000014 { - state_default: pinmux { - bl-on { - nvidia,tristate = ; - }; - - ddc { - nvidia,tristate = ; - }; - - hotplug-detect { - nvidia,tristate = ; - }; - - i2c { - nvidia,tristate = ; - }; - - lcd { - nvidia,tristate = ; - }; - - lm1 { - nvidia,tristate = ; - }; - - mmc { - nvidia,tristate = ; - }; - - mmccd { - nvidia,tristate = ; - }; - - pwm-a-b { - nvidia,tristate = ; - }; - - pwm-c-d { - nvidia,tristate = ; - }; - - ssp { - nvidia,tristate = ; - }; - - uart-a { - nvidia,tristate = ; - }; - - uart-b { - nvidia,tristate = ; - }; - - uart-c { - nvidia,tristate = ; - }; - - usbh-pen { - nvidia,tristate = ; - }; - }; - }; - - /* Colibri UART-A */ - serial@70006000 { - status = "okay"; - }; - - /* Colibri UART-C */ - serial@70006040 { - status = "okay"; - }; - - /* Colibri UART-B */ - serial@70006300 { - status = "okay"; - }; - - pwm@7000a000 { - status = "okay"; - }; - - /* - * GEN1_I2C: I2C_SDA/SCL on SODIMM pin 194/196 (e.g. RTC on carrier - * board) - */ - i2c@7000c000 { - status = "okay"; - clock-frequency = <400000>; - - /* M41T0M6 real time clock on carrier board */ - rtc@68 { - compatible = "st,m41t0"; - reg = <0x68>; - }; - }; - - /* GEN2_I2C: unused */ - - /* CAM_I2C (I2C3): unused */ - - /* DDC_CLOCK/DATA on X3 pin 15/16 (e.g. display EDID) */ - i2c@7000c400 { - status = "okay"; - }; - - /* EHCI instance 0: USB1_DP/N -> USBC_P/N */ - usb@c5000000 { - status = "okay"; - dr_mode = "otg"; - }; - - usb-phy@c5000000 { - status = "okay"; - vbus-supply = <®_usbc_vbus>; - }; - - /* EHCI instance 2: USB3_DP/N -> USBH_P/N */ - usb@c5008000 { - status = "okay"; - }; - - usb-phy@c5008000 { - status = "okay"; - vbus-supply = <®_usbh_vbus>; - }; - - /* SPI4: Colibri SSP */ - spi@7000da00 { - status = "okay"; - spi-max-frequency = <25000000>; - }; - - /* SD/MMC */ - sdhci@c8000600 { - status = "okay"; - bus-width = <4>; - cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>; /* MMCD */ - no-1-8-v; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - brightness-levels = <255 128 64 32 16 8 4 0>; - default-brightness-level = <6>; - /* BL_ON */ - enable-gpios = <&gpio TEGRA_GPIO(T, 4) GPIO_ACTIVE_HIGH>; - power-supply = <®_3v3>; - pwms = <&pwm 0 5000000>; /* PWM */ - }; - - gpio-keys { - compatible = "gpio-keys"; - - wakeup { - label = "SODIMM pin 45 wakeup"; - gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>; - linux,code = ; - debounce-interval = <10>; - wakeup-source; - }; - }; - - panel: panel { - /* - * edt,et057090dhu: EDT 5.7" LCD TFT - * edt,et070080dh6: EDT 7.0" LCD TFT - */ - compatible = "edt,et057090dhu", "simple-panel"; - backlight = <&backlight>; - power-supply = <®_3v3>; - }; - - reg_3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_5v0: regulator-5v0 { - compatible = "regulator-fixed"; - regulator-name = "5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_usbc_vbus: regulator-usbc-vbus { - compatible = "regulator-fixed"; - regulator-name = "VCC_USB2"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <®_5v0>; - }; - - /* USBH_PEN resp. USB_P_EN */ - reg_usbh_vbus: regulator-usbh-vbus { - compatible = "regulator-fixed"; - regulator-name = "VCC_USB1"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; - vin-supply = <®_5v0>; - }; -}; diff --git a/sys/gnu/dts/arm/tegra20-colibri.dtsi b/sys/gnu/dts/arm/tegra20-colibri.dtsi deleted file mode 100644 index 6162d193e12..00000000000 --- a/sys/gnu/dts/arm/tegra20-colibri.dtsi +++ /dev/null @@ -1,768 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "tegra20.dtsi" - -/* - * Toradex Colibri T20 Module Device Tree - * Compatible for Revisions Colibri T20 256MB V1.1B, V1.2A; - * Colibri T20 256MB IT V1.2A; Colibri T20 512MB V1.1C, V1.2A; - * Colibri T20 512MB IT V1.2A - */ -/ { - memory@0 { - /* - * Set memory to 256 MB to be safe as this could be used on - * 256 or 512 MB module. It is expected from bootloader - * to fix this up for 512 MB version. - */ - reg = <0x00000000 0x10000000>; - }; - - host1x@50000000 { - hdmi@54280000 { - nvidia,ddc-i2c-bus = <&hdmi_ddc>; - nvidia,hpd-gpio = - <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; - pll-supply = <®_1v8_avdd_hdmi_pll>; - vdd-supply = <®_3v3_avdd_hdmi>; - }; - }; - - pinmux@70000014 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - /* Analogue Audio AC97 to WM9712 (On-module) */ - audio-refclk { - nvidia,pins = "cdev1"; - nvidia,function = "plla_out"; - nvidia,pull = ; - nvidia,tristate = ; - }; - dap3 { - nvidia,pins = "dap3"; - nvidia,function = "dap3"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* - * AC97_RESET, ULPI_RESET, AC97_INT aka WM9712 GENIRQ - * (All on-module), SODIMM Pin 45 Wakeup - */ - gpio-uac { - nvidia,pins = "uac"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* - * Buffer Enables for nPWE and RDnWR (On-module, - * see GPIO hogging further down below) - */ - gpio-pta { - nvidia,pins = "pta"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* - * CLK_32K_OUT, CORE_PWR_REQ, CPU_PWR_REQ, PWR_INT_N, - * SYS_CLK_REQ (All on-module) - */ - pmc { - nvidia,pins = "pmc"; - nvidia,function = "pwr_on"; - nvidia,tristate = ; - }; - - /* - * Colibri Address/Data Bus (GMI) - * Note: spid and spie optionally used for SPI1 - */ - gmi { - nvidia,pins = "atc", "atd", "ate", "dap1", - "dap2", "dap4", "gmd", "gpu", - "irrx", "irtx", "spia", "spib", - "spic", "spid", "spie", "uca", - "ucb"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - }; - /* Further pins may be used as GPIOs */ - gmi-gpio1 { - nvidia,pins = "lpw0", "lsc1", "lsck", "lsda"; - nvidia,function = "hdmi"; - nvidia,tristate = ; - }; - gmi-gpio2 { - nvidia,pins = "lcsn", "ldc", "lm0", "lsdi"; - nvidia,function = "rsvd4"; - nvidia,tristate = ; - }; - - /* Colibri BL_ON */ - bl-on { - nvidia,pins = "dta"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Colibri Backlight PWM, PWM */ - pwm-a-b { - nvidia,pins = "sdc"; - nvidia,function = "pwm"; - nvidia,tristate = ; - }; - - /* Colibri DDC */ - ddc { - nvidia,pins = "ddc"; - nvidia,function = "i2c2"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* - * Colibri EXT_IO* - * Note: dtf optionally used for I2C3 - */ - ext-io { - nvidia,pins = "dtf", "spdi"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* - * Colibri Ethernet (On-module) - * ULPI EHCI instance 1 USB2_DP/N -> AX88772B - */ - ulpi { - nvidia,pins = "uaa", "uab", "uda"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - }; - ulpi-refclk { - nvidia,pins = "cdev2"; - nvidia,function = "pllp_out4"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Colibri HOTPLUG_DETECT (HDMI) */ - hotplug-detect { - nvidia,pins = "hdint"; - nvidia,function = "hdmi"; - nvidia,tristate = ; - }; - - /* Colibri I2C */ - i2c { - nvidia,pins = "rm"; - nvidia,function = "i2c1"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* - * Colibri L_BIAS, LCD_M1 is muxed with LCD_DE - * today's display need DE, disable LCD_M1 - */ - lm1 { - nvidia,pins = "lm1"; - nvidia,function = "rsvd3"; - nvidia,tristate = ; - }; - - /* Colibri LCD (L_* resp. LDD<*>) */ - lcd { - nvidia,pins = "ld0", "ld1", "ld2", "ld3", - "ld4", "ld5", "ld6", "ld7", - "ld8", "ld9", "ld10", "ld11", - "ld12", "ld13", "ld14", "ld15", - "ld16", "ld17", "lhs", "lsc0", - "lspi", "lvs"; - nvidia,function = "displaya"; - nvidia,tristate = ; - }; - /* Colibri LCD (Optional 24 BPP Support) */ - lcd-24 { - nvidia,pins = "ldi", "lhp0", "lhp1", "lhp2", - "lpp", "lvp1"; - nvidia,function = "displaya"; - nvidia,tristate = ; - }; - - /* Colibri MMC */ - mmc { - nvidia,pins = "atb", "gma"; - nvidia,function = "sdio4"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Colibri MMCCD */ - mmccd { - nvidia,pins = "gmb"; - nvidia,function = "gmi_int"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Colibri MMC (Optional 8-bit) */ - mmc-8bit { - nvidia,pins = "gme"; - nvidia,function = "sdio4"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* - * Colibri Parallel Camera (Optional) - * pins multiplexed with others and therefore disabled - * Note: dta used for BL_ON by default - */ - cif-mclk { - nvidia,pins = "csus"; - nvidia,function = "vi_sensor_clk"; - nvidia,pull = ; - nvidia,tristate = ; - }; - cif { - nvidia,pins = "dtb", "dtc", "dtd"; - nvidia,function = "vi"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Colibri PWM, PWM */ - pwm-c-d { - nvidia,pins = "sdb", "sdd"; - nvidia,function = "pwm"; - nvidia,tristate = ; - }; - - /* Colibri SSP */ - ssp { - nvidia,pins = "slxa", "slxc", "slxd", "slxk"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Colibri UART-A */ - uart-a { - nvidia,pins = "sdio1"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - }; - uart-a-dsr { - nvidia,pins = "lpw1"; - nvidia,function = "rsvd3"; - nvidia,tristate = ; - }; - uart-a-dcd { - nvidia,pins = "lpw2"; - nvidia,function = "hdmi"; - nvidia,tristate = ; - }; - - /* Colibri UART-B */ - uart-b { - nvidia,pins = "gmc"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Colibri UART-C */ - uart-c { - nvidia,pins = "uad"; - nvidia,function = "irda"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Colibri USB_CDET */ - usb-cdet { - nvidia,pins = "spdo"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Colibri USBH_OC */ - usbh-oc { - nvidia,pins = "spih"; - nvidia,function = "spi2_alt"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Colibri USBH_PEN */ - usbh-pen { - nvidia,pins = "spig"; - nvidia,function = "spi2_alt"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Colibri VGA not supported */ - vga { - nvidia,pins = "crtp"; - nvidia,function = "crt"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* I2C3 (Optional) */ - i2c3 { - nvidia,pins = "dtf"; - nvidia,function = "i2c3"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* JTAG_RTCK */ - jtag-rtck { - nvidia,pins = "gpu7"; - nvidia,function = "rtck"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* - * LAN_RESET, LAN_EXT_WAKEUP and LAN_PME - * (All On-module) - */ - gpio-gpv { - nvidia,pins = "gpv"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* - * LAN_V_BUS, VDD_FAULT, BATT_FAULT, WM9712 PENDOWN - * (All On-module); Colibri CAN_INT - */ - gpio-dte { - nvidia,pins = "dte"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* NAND (On-module) */ - nand { - nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", - "kbce", "kbcf"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Onewire (Optional) */ - owr { - nvidia,pins = "owc"; - nvidia,function = "owr"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Power I2C (On-module) */ - i2cp { - nvidia,pins = "i2cp"; - nvidia,function = "i2cp"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* RESET_OUT */ - reset-out { - nvidia,pins = "ata"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* - * SPI1 (Optional) - * Note: spid and spie used for Colibri Address/Data - * Bus (GMI) - */ - spi1 { - nvidia,pins = "spid", "spie", "spif"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* - * THERMD_ALERT# (On-module), unlatched I2C address pin - * of LM95245 temperature sensor therefore requires - * disabling for now - */ - lvp0 { - nvidia,pins = "lvp0"; - nvidia,function = "rsvd3"; - nvidia,tristate = ; - }; - }; - }; - - tegra_ac97: ac97@70002000 { - status = "okay"; - nvidia,codec-reset-gpio = - <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_HIGH>; - nvidia,codec-sync-gpio = - <&gpio TEGRA_GPIO(P, 0) GPIO_ACTIVE_HIGH>; - }; - - serial@70006040 { - compatible = "nvidia,tegra20-hsuart"; - }; - - serial@70006300 { - compatible = "nvidia,tegra20-hsuart"; - }; - - nand-controller@70008000 { - status = "okay"; - - nand@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; - nand-bus-width = <8>; - nand-on-flash-bbt; - nand-ecc-algo = "bch"; - nand-is-boot-medium; - nand-ecc-maximize; - wp-gpios = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_LOW>; - }; - }; - - /* - * GEN1_I2C: I2C_SDA/SCL on SODIMM pin 194/196 (e.g. RTC on carrier - * board) - */ - i2c@7000c000 { - clock-frequency = <400000>; - }; - - /* DDC_SCL/SDA on X3 pin 15/16 (e.g. display EDID) */ - hdmi_ddc: i2c@7000c400 { - clock-frequency = <10000>; - }; - - /* GEN2_I2C: unused */ - - /* CAM/GEN3_I2C: used as EXT_IO1/2 GPIOs on SODIMM pin 133/127 */ - - /* PWR_I2C: power I2C to PMIC and temperature sensor (On-module) */ - i2c@7000d000 { - status = "okay"; - clock-frequency = <100000>; - - pmic@34 { - compatible = "ti,tps6586x"; - reg = <0x34>; - interrupts = ; - ti,system-power-controller; - #gpio-cells = <2>; - gpio-controller; - sys-supply = <®_module_3v3>; - vin-sm0-supply = <®_3v3_vsys>; - vin-sm1-supply = <®_3v3_vsys>; - vin-sm2-supply = <®_3v3_vsys>; - vinldo01-supply = <®_1v8_vdd_ddr2>; - vinldo23-supply = <®_module_3v3>; - vinldo4-supply = <®_module_3v3>; - vinldo678-supply = <®_module_3v3>; - vinldo9-supply = <®_module_3v3>; - - regulators { - reg_3v3_vsys: sys { - regulator-name = "VSYS_3.3V"; - regulator-always-on; - }; - - sm0 { - regulator-name = "VDD_CORE_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - sm1 { - regulator-name = "VDD_CPU_1.0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - reg_1v8_vdd_ddr2: sm2 { - regulator-name = "VDD_DDR2_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - /* LDO0 is not connected to anything */ - - /* - * +3.3V_ENABLE_N switching via FET: - * AVDD_AUDIO_S and +3.3V - * see also +3.3V fixed supply - */ - ldo1 { - regulator-name = "AVDD_PLL_1.1V"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - ldo2 { - regulator-name = "VDD_RTC_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - /* LDO3 is not connected to anything */ - - ldo4 { - regulator-name = "VDDIO_SYS_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - /* Switched via FET from regular +3.3V */ - ldo5 { - regulator-name = "+3.3V_USB"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo6 { - regulator-name = "AVDD_VDAC_2.85V"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - reg_3v3_avdd_hdmi: ldo7 { - regulator-name = "AVDD_HDMI_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_1v8_avdd_hdmi_pll: ldo8 { - regulator-name = "AVDD_HDMI_PLL_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo9 { - regulator-name = "VDDIO_RX_DDR_2.85V"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - regulator-always-on; - }; - - ldo_rtc { - regulator-name = "VCC_BATT"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; - - /* LM95245 temperature sensor */ - temp-sensor@4c { - compatible = "national,lm95245"; - reg = <0x4c>; - }; - }; - - pmc@7000e400 { - nvidia,suspend-mode = <1>; - nvidia,cpu-pwr-good-time = <5000>; - nvidia,cpu-pwr-off-time = <5000>; - nvidia,core-pwr-good-time = <3845 3845>; - nvidia,core-pwr-off-time = <3875>; - nvidia,sys-clock-req-active-high; - - /* Set SLEEP MODE bit in SUPPLYENE register of TPS658643 PMIC */ - i2c-thermtrip { - nvidia,i2c-controller-id = <3>; - nvidia,bus-addr = <0x34>; - nvidia,reg-addr = <0x14>; - nvidia,reg-data = <0x8>; - }; - }; - - memory-controller@7000f400 { - emc-table@83250 { - reg = <83250>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <83250>; - nvidia,emc-registers = <0x00000005 0x00000011 - 0x00000004 0x00000002 0x00000004 0x00000004 - 0x00000001 0x0000000a 0x00000002 0x00000002 - 0x00000001 0x00000001 0x00000003 0x00000004 - 0x00000003 0x00000009 0x0000000c 0x0000025f - 0x00000000 0x00000003 0x00000003 0x00000002 - 0x00000002 0x00000001 0x00000008 0x000000c8 - 0x00000003 0x00000005 0x00000003 0x0000000c - 0x00000002 0x00000000 0x00000000 0x00000002 - 0x00000000 0x00000000 0x00000083 0x00520006 - 0x00000010 0x00000008 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000>; - }; - emc-table@133200 { - reg = <133200>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <133200>; - nvidia,emc-registers = <0x00000008 0x00000019 - 0x00000006 0x00000002 0x00000004 0x00000004 - 0x00000001 0x0000000a 0x00000002 0x00000002 - 0x00000002 0x00000001 0x00000003 0x00000004 - 0x00000003 0x00000009 0x0000000c 0x0000039f - 0x00000000 0x00000003 0x00000003 0x00000002 - 0x00000002 0x00000001 0x00000008 0x000000c8 - 0x00000003 0x00000007 0x00000003 0x0000000c - 0x00000002 0x00000000 0x00000000 0x00000002 - 0x00000000 0x00000000 0x00000083 0x00510006 - 0x00000010 0x00000008 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000>; - }; - emc-table@166500 { - reg = <166500>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <166500>; - nvidia,emc-registers = <0x0000000a 0x00000021 - 0x00000008 0x00000003 0x00000004 0x00000004 - 0x00000002 0x0000000a 0x00000003 0x00000003 - 0x00000002 0x00000001 0x00000003 0x00000004 - 0x00000003 0x00000009 0x0000000c 0x000004df - 0x00000000 0x00000003 0x00000003 0x00000003 - 0x00000003 0x00000001 0x00000009 0x000000c8 - 0x00000003 0x00000009 0x00000004 0x0000000c - 0x00000002 0x00000000 0x00000000 0x00000002 - 0x00000000 0x00000000 0x00000083 0x004f0006 - 0x00000010 0x00000008 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000>; - }; - emc-table@333000 { - reg = <333000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <333000>; - nvidia,emc-registers = <0x00000014 0x00000041 - 0x0000000f 0x00000005 0x00000004 0x00000005 - 0x00000003 0x0000000a 0x00000005 0x00000005 - 0x00000004 0x00000001 0x00000003 0x00000004 - 0x00000003 0x00000009 0x0000000c 0x000009ff - 0x00000000 0x00000003 0x00000003 0x00000005 - 0x00000005 0x00000001 0x0000000e 0x000000c8 - 0x00000003 0x00000011 0x00000006 0x0000000c - 0x00000002 0x00000000 0x00000000 0x00000002 - 0x00000000 0x00000000 0x00000083 0x00380006 - 0x00000010 0x00000008 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000>; - }; - }; - - /* EHCI instance 1: ULPI PHY -> AX88772B (On-module) */ - usb@c5004000 { - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - - asix@1 { - reg = <1>; - local-mac-address = [00 00 00 00 00 00]; - }; - }; - - usb-phy@c5004000 { - status = "okay"; - nvidia,phy-reset-gpio = - <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_LOW>; - vbus-supply = <®_lan_v_bus>; - }; - - clk32k_in: xtal3 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - - reg_lan_v_bus: regulator-lan-v-bus { - compatible = "regulator-fixed"; - regulator-name = "LAN_V_BUS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>; - }; - - reg_module_3v3: regulator-module-3v3 { - compatible = "regulator-fixed"; - regulator-name = "+V3.3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - sound { - compatible = "nvidia,tegra-audio-wm9712-colibri_t20", - "nvidia,tegra-audio-wm9712"; - nvidia,model = "Toradex Colibri T20"; - nvidia,audio-routing = - "Headphone", "HPOUTL", - "Headphone", "HPOUTR", - "LineIn", "LINEINL", - "LineIn", "LINEINR", - "Mic", "MIC1"; - nvidia,ac97-controller = <&tegra_ac97>; - clocks = <&tegra_car TEGRA20_CLK_PLL_A>, - <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA20_CLK_CDEV1>; - clock-names = "pll_a", "pll_a_out0", "mclk"; - }; -}; - -&gpio { - lan-reset-n { - gpio-hog; - gpios = ; - output-high; - line-name = "LAN_RESET#"; - }; - - /* Tri-stating GMI_WR_N on SODIMM pin 99 nPWE */ - npwe { - gpio-hog; - gpios = ; - output-high; - line-name = "Tri-state nPWE"; - }; - - /* Not tri-stating GMI_WR_N on SODIMM pin 93 RDnWR */ - rdnwr { - gpio-hog; - gpios = ; - output-low; - line-name = "Not tri-state RDnWR"; - }; -}; diff --git a/sys/gnu/dts/arm/tegra20-cpu-opp-microvolt.dtsi b/sys/gnu/dts/arm/tegra20-cpu-opp-microvolt.dtsi deleted file mode 100644 index e85ffdbef87..00000000000 --- a/sys/gnu/dts/arm/tegra20-cpu-opp-microvolt.dtsi +++ /dev/null @@ -1,201 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -/ { - cpu0_opp_table: cpu_opp_table0 { - opp@216000000_750 { - opp-microvolt = <750000 750000 1125000>; - }; - - opp@216000000_800 { - opp-microvolt = <800000 800000 1125000>; - }; - - opp@312000000_750 { - opp-microvolt = <750000 750000 1125000>; - }; - - opp@312000000_800 { - opp-microvolt = <800000 800000 1125000>; - }; - - opp@456000000_750 { - opp-microvolt = <750000 750000 1125000>; - }; - - opp@456000000_800 { - opp-microvolt = <800000 800000 1125000>; - }; - - opp@456000000_800_2_2 { - opp-microvolt = <800000 800000 1125000>; - }; - - opp@456000000_800_3_2 { - opp-microvolt = <800000 800000 1125000>; - }; - - opp@456000000_825 { - opp-microvolt = <825000 825000 1125000>; - }; - - opp@608000000_750 { - opp-microvolt = <750000 750000 1125000>; - }; - - opp@608000000_800 { - opp-microvolt = <800000 800000 1125000>; - }; - - opp@608000000_800_3_2 { - opp-microvolt = <800000 800000 1125000>; - }; - - opp@608000000_825 { - opp-microvolt = <825000 825000 1125000>; - }; - - opp@608000000_850 { - opp-microvolt = <850000 850000 1125000>; - }; - - opp@608000000_900 { - opp-microvolt = <900000 900000 1125000>; - }; - - opp@760000000_775 { - opp-microvolt = <775000 775000 1125000>; - }; - - opp@760000000_800 { - opp-microvolt = <800000 800000 1125000>; - }; - - opp@760000000_850 { - opp-microvolt = <850000 850000 1125000>; - }; - - opp@760000000_875 { - opp-microvolt = <875000 875000 1125000>; - }; - - opp@760000000_875_1_1 { - opp-microvolt = <875000 875000 1125000>; - }; - - opp@760000000_875_0_2 { - opp-microvolt = <875000 875000 1125000>; - }; - - opp@760000000_875_1_2 { - opp-microvolt = <875000 875000 1125000>; - }; - - opp@760000000_900 { - opp-microvolt = <900000 900000 1125000>; - }; - - opp@760000000_975 { - opp-microvolt = <975000 975000 1125000>; - }; - - opp@816000000_800 { - opp-microvolt = <800000 800000 1125000>; - }; - - opp@816000000_850 { - opp-microvolt = <850000 850000 1125000>; - }; - - opp@816000000_875 { - opp-microvolt = <875000 875000 1125000>; - }; - - opp@816000000_950 { - opp-microvolt = <950000 950000 1125000>; - }; - - opp@816000000_1000 { - opp-microvolt = <1000000 1000000 1125000>; - }; - - opp@912000000_850 { - opp-microvolt = <850000 850000 1125000>; - }; - - opp@912000000_900 { - opp-microvolt = <900000 900000 1125000>; - }; - - opp@912000000_925 { - opp-microvolt = <925000 925000 1125000>; - }; - - opp@912000000_950 { - opp-microvolt = <950000 950000 1125000>; - }; - - opp@912000000_950_0_2 { - opp-microvolt = <950000 950000 1125000>; - }; - - opp@912000000_950_2_2 { - opp-microvolt = <950000 950000 1125000>; - }; - - opp@912000000_1000 { - opp-microvolt = <1000000 1000000 1125000>; - }; - - opp@912000000_1050 { - opp-microvolt = <1050000 1050000 1125000>; - }; - - opp@1000000000_875 { - opp-microvolt = <875000 875000 1125000>; - }; - - opp@1000000000_900 { - opp-microvolt = <900000 900000 1125000>; - }; - - opp@1000000000_950 { - opp-microvolt = <950000 950000 1125000>; - }; - - opp@1000000000_975 { - opp-microvolt = <975000 975000 1125000>; - }; - - opp@1000000000_1000 { - opp-microvolt = <1000000 1000000 1125000>; - }; - - opp@1000000000_1000_0_2 { - opp-microvolt = <1000000 1000000 1125000>; - }; - - opp@1000000000_1025 { - opp-microvolt = <1025000 1025000 1125000>; - }; - - opp@1000000000_1100 { - opp-microvolt = <1100000 1100000 1125000>; - }; - - opp@1200000000_1000 { - opp-microvolt = <1000000 1000000 1125000>; - }; - - opp@1200000000_1050 { - opp-microvolt = <1050000 1050000 1125000>; - }; - - opp@1200000000_1100 { - opp-microvolt = <1100000 1100000 1125000>; - }; - - opp@1200000000_1125 { - opp-microvolt = <1125000 1125000 1125000>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/tegra20-cpu-opp.dtsi b/sys/gnu/dts/arm/tegra20-cpu-opp.dtsi deleted file mode 100644 index c878f423179..00000000000 --- a/sys/gnu/dts/arm/tegra20-cpu-opp.dtsi +++ /dev/null @@ -1,302 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -/ { - cpu0_opp_table: cpu_opp_table0 { - compatible = "operating-points-v2"; - opp-shared; - - opp@216000000_750 { - clock-latency-ns = <400000>; - opp-supported-hw = <0x0F 0x0003>; - opp-hz = /bits/ 64 <216000000>; - }; - - opp@216000000_800 { - clock-latency-ns = <400000>; - opp-supported-hw = <0x0F 0x0004>; - opp-hz = /bits/ 64 <216000000>; - }; - - opp@312000000_750 { - clock-latency-ns = <400000>; - opp-supported-hw = <0x0F 0x0003>; - opp-hz = /bits/ 64 <312000000>; - }; - - opp@312000000_800 { - clock-latency-ns = <400000>; - opp-supported-hw = <0x0F 0x0004>; - opp-hz = /bits/ 64 <312000000>; - }; - - opp@456000000_750 { - clock-latency-ns = <400000>; - opp-supported-hw = <0x0C 0x0003>; - opp-hz = /bits/ 64 <456000000>; - }; - - opp@456000000_800 { - clock-latency-ns = <400000>; - opp-supported-hw = <0x03 0x0006>; - opp-hz = /bits/ 64 <456000000>; - }; - - opp@456000000_800_2_2 { - clock-latency-ns = <400000>; - opp-supported-hw = <0x04 0x0004>; - opp-hz = /bits/ 64 <456000000>; - }; - - opp@456000000_800_3_2 { - clock-latency-ns = <400000>; - opp-supported-hw = <0x08 0x0004>; - opp-hz = /bits/ 64 <456000000>; - }; - - opp@456000000_825 { - clock-latency-ns = <400000>; - opp-supported-hw = <0x03 0x0001>; - opp-hz = /bits/ 64 <456000000>; - }; - - opp@608000000_750 { - clock-latency-ns = <400000>; - opp-supported-hw = <0x08 0x0003>; - opp-hz = /bits/ 64 <608000000>; - }; - - opp@608000000_800 { - clock-latency-ns = <400000>; - opp-supported-hw = <0x04 0x0006>; - opp-hz = /bits/ 64 <608000000>; - }; - - opp@608000000_800_3_2 { - clock-latency-ns = <400000>; - opp-supported-hw = <0x08 0x0004>; - opp-hz = /bits/ 64 <608000000>; - }; - - opp@608000000_825 { - clock-latency-ns = <400000>; - opp-supported-hw = <0x04 0x0001>; - opp-hz = /bits/ 64 <608000000>; - }; - - opp@608000000_850 { - clock-latency-ns = <400000>; - opp-supported-hw = <0x03 0x0006>; - opp-hz = /bits/ 64 <608000000>; - }; - - opp@608000000_900 { - clock-latency-ns = <400000>; - opp-supported-hw = <0x03 0x0001>; - opp-hz = /bits/ 64 <608000000>; - }; - - opp@760000000_775 { - clock-latency-ns = <400000>; - opp-supported-hw = <0x08 0x0003>; - opp-hz = /bits/ 64 <760000000>; - }; - - opp@760000000_800 { - clock-latency-ns = <400000>; - opp-supported-hw = <0x08 0x0004>; - opp-hz = /bits/ 64 <760000000>; - }; - - opp@760000000_850 { - clock-latency-ns = <400000>; - opp-supported-hw = <0x04 0x0006>; - opp-hz = /bits/ 64 <760000000>; - }; - - opp@760000000_875 { - clock-latency-ns = <400000>; - opp-supported-hw = <0x04 0x0001>; - opp-hz = /bits/ 64 <760000000>; - }; - - opp@760000000_875_1_1 { - clock-latency-ns = <400000>; - opp-supported-hw = <0x02 0x0002>; - opp-hz = /bits/ 64 <760000000>; - }; - - opp@760000000_875_0_2 { - clock-latency-ns = <400000>; - opp-supported-hw = <0x01 0x0004>; - opp-hz = /bits/ 64 <760000000>; - }; - - opp@760000000_875_1_2 { - clock-latency-ns = <400000>; - opp-supported-hw = <0x02 0x0004>; - opp-hz = /bits/ 64 <760000000>; - }; - - opp@760000000_900 { - clock-latency-ns = <400000>; - opp-supported-hw = <0x01 0x0002>; - opp-hz = /bits/ 64 <760000000>; - }; - - opp@760000000_975 { - clock-latency-ns = <400000>; - opp-supported-hw = <0x03 0x0001>; - opp-hz = /bits/ 64 <760000000>; - }; - - opp@816000000_800 { - clock-latency-ns = <400000>; - opp-supported-hw = <0x08 0x0007>; - opp-hz = /bits/ 64 <816000000>; - }; - - opp@816000000_850 { - clock-latency-ns = <400000>; - opp-supported-hw = <0x04 0x0002>; - opp-hz = /bits/ 64 <816000000>; - }; - - opp@816000000_875 { - clock-latency-ns = <400000>; - opp-supported-hw = <0x04 0x0005>; - opp-hz = /bits/ 64 <816000000>; - }; - - opp@816000000_950 { - clock-latency-ns = <400000>; - opp-supported-hw = <0x03 0x0006>; - opp-hz = /bits/ 64 <816000000>; - }; - - opp@816000000_1000 { - clock-latency-ns = <400000>; - opp-supported-hw = <0x03 0x0001>; - opp-hz = /bits/ 64 <816000000>; - }; - - opp@912000000_850 { - clock-latency-ns = <400000>; - opp-supported-hw = <0x08 0x0007>; - opp-hz = /bits/ 64 <912000000>; - }; - - opp@912000000_900 { - clock-latency-ns = <400000>; - opp-supported-hw = <0x04 0x0002>; - opp-hz = /bits/ 64 <912000000>; - }; - - opp@912000000_925 { - clock-latency-ns = <400000>; - opp-supported-hw = <0x04 0x0001>; - opp-hz = /bits/ 64 <912000000>; - }; - - opp@912000000_950 { - clock-latency-ns = <400000>; - opp-supported-hw = <0x02 0x0006>; - opp-hz = /bits/ 64 <912000000>; - }; - - opp@912000000_950_0_2 { - clock-latency-ns = <400000>; - opp-supported-hw = <0x01 0x0004>; - opp-hz = /bits/ 64 <912000000>; - }; - - opp@912000000_950_2_2 { - clock-latency-ns = <400000>; - opp-supported-hw = <0x04 0x0004>; - opp-hz = /bits/ 64 <912000000>; - }; - - opp@912000000_1000 { - clock-latency-ns = <400000>; - opp-supported-hw = <0x01 0x0002>; - opp-hz = /bits/ 64 <912000000>; - }; - - opp@912000000_1050 { - clock-latency-ns = <400000>; - opp-supported-hw = <0x03 0x0001>; - opp-hz = /bits/ 64 <912000000>; - }; - - opp@1000000000_875 { - clock-latency-ns = <400000>; - opp-supported-hw = <0x08 0x0007>; - opp-hz = /bits/ 64 <1000000000>; - }; - - opp@1000000000_900 { - clock-latency-ns = <400000>; - opp-supported-hw = <0x04 0x0002>; - opp-hz = /bits/ 64 <1000000000>; - }; - - opp@1000000000_950 { - clock-latency-ns = <400000>; - opp-supported-hw = <0x04 0x0004>; - opp-hz = /bits/ 64 <1000000000>; - }; - - opp@1000000000_975 { - clock-latency-ns = <400000>; - opp-supported-hw = <0x04 0x0001>; - opp-hz = /bits/ 64 <1000000000>; - }; - - opp@1000000000_1000 { - clock-latency-ns = <400000>; - opp-supported-hw = <0x02 0x0006>; - opp-hz = /bits/ 64 <1000000000>; - }; - - opp@1000000000_1000_0_2 { - clock-latency-ns = <400000>; - opp-supported-hw = <0x01 0x0004>; - opp-hz = /bits/ 64 <1000000000>; - }; - - opp@1000000000_1025 { - clock-latency-ns = <400000>; - opp-supported-hw = <0x01 0x0002>; - opp-hz = /bits/ 64 <1000000000>; - }; - - opp@1000000000_1100 { - clock-latency-ns = <400000>; - opp-supported-hw = <0x03 0x0001>; - opp-hz = /bits/ 64 <1000000000>; - }; - - opp@1200000000_1000 { - clock-latency-ns = <400000>; - opp-supported-hw = <0x08 0x0004>; - opp-hz = /bits/ 64 <1200000000>; - }; - - opp@1200000000_1050 { - clock-latency-ns = <400000>; - opp-supported-hw = <0x04 0x0004>; - opp-hz = /bits/ 64 <1200000000>; - }; - - opp@1200000000_1100 { - clock-latency-ns = <400000>; - opp-supported-hw = <0x02 0x0004>; - opp-hz = /bits/ 64 <1200000000>; - }; - - opp@1200000000_1125 { - clock-latency-ns = <400000>; - opp-supported-hw = <0x01 0x0004>; - opp-hz = /bits/ 64 <1200000000>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/tegra20-harmony.dts b/sys/gnu/dts/arm/tegra20-harmony.dts deleted file mode 100644 index 1d96d92b72a..00000000000 --- a/sys/gnu/dts/arm/tegra20-harmony.dts +++ /dev/null @@ -1,782 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include -#include "tegra20.dtsi" - -/ { - model = "NVIDIA Tegra20 Harmony evaluation board"; - compatible = "nvidia,harmony", "nvidia,tegra20"; - - aliases { - rtc0 = "/i2c@7000d000/tps6586x@34"; - rtc1 = "/rtc@7000e000"; - serial0 = &uartd; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - reg = <0x00000000 0x40000000>; - }; - - host1x@50000000 { - dc@54200000 { - rgb { - status = "okay"; - - nvidia,panel = <&panel>; - }; - }; - - hdmi@54280000 { - status = "okay"; - - hdmi-supply = <&vdd_5v0_hdmi>; - vdd-supply = <&hdmi_vdd_reg>; - pll-supply = <&hdmi_pll_reg>; - - nvidia,ddc-i2c-bus = <&hdmi_ddc>; - nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) - GPIO_ACTIVE_HIGH>; - }; - }; - - pinmux@70000014 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - ata { - nvidia,pins = "ata"; - nvidia,function = "ide"; - }; - atb { - nvidia,pins = "atb", "gma", "gme"; - nvidia,function = "sdio4"; - }; - atc { - nvidia,pins = "atc"; - nvidia,function = "nand"; - }; - atd { - nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu", - "spia", "spib", "spic"; - nvidia,function = "gmi"; - }; - cdev1 { - nvidia,pins = "cdev1"; - nvidia,function = "plla_out"; - }; - cdev2 { - nvidia,pins = "cdev2"; - nvidia,function = "pllp_out4"; - }; - crtp { - nvidia,pins = "crtp"; - nvidia,function = "crt"; - }; - csus { - nvidia,pins = "csus"; - nvidia,function = "vi_sensor_clk"; - }; - dap1 { - nvidia,pins = "dap1"; - nvidia,function = "dap1"; - }; - dap2 { - nvidia,pins = "dap2"; - nvidia,function = "dap2"; - }; - dap3 { - nvidia,pins = "dap3"; - nvidia,function = "dap3"; - }; - dap4 { - nvidia,pins = "dap4"; - nvidia,function = "dap4"; - }; - ddc { - nvidia,pins = "ddc"; - nvidia,function = "i2c2"; - }; - dta { - nvidia,pins = "dta", "dtd"; - nvidia,function = "sdio2"; - }; - dtb { - nvidia,pins = "dtb", "dtc", "dte"; - nvidia,function = "rsvd1"; - }; - dtf { - nvidia,pins = "dtf"; - nvidia,function = "i2c3"; - }; - gmc { - nvidia,pins = "gmc"; - nvidia,function = "uartd"; - }; - gpu7 { - nvidia,pins = "gpu7"; - nvidia,function = "rtck"; - }; - gpv { - nvidia,pins = "gpv", "slxa", "slxk"; - nvidia,function = "pcie"; - }; - hdint { - nvidia,pins = "hdint", "pta"; - nvidia,function = "hdmi"; - }; - i2cp { - nvidia,pins = "i2cp"; - nvidia,function = "i2cp"; - }; - irrx { - nvidia,pins = "irrx", "irtx"; - nvidia,function = "uarta"; - }; - kbca { - nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", - "kbce", "kbcf"; - nvidia,function = "kbc"; - }; - lcsn { - nvidia,pins = "lcsn", "ld0", "ld1", "ld2", - "ld3", "ld4", "ld5", "ld6", "ld7", - "ld8", "ld9", "ld10", "ld11", "ld12", - "ld13", "ld14", "ld15", "ld16", "ld17", - "ldc", "ldi", "lhp0", "lhp1", "lhp2", - "lhs", "lm0", "lm1", "lpp", "lpw0", - "lpw1", "lpw2", "lsc0", "lsc1", "lsck", - "lsda", "lsdi", "lspi", "lvp0", "lvp1", - "lvs"; - nvidia,function = "displaya"; - }; - owc { - nvidia,pins = "owc", "spdi", "spdo", "uac"; - nvidia,function = "rsvd2"; - }; - pmc { - nvidia,pins = "pmc"; - nvidia,function = "pwr_on"; - }; - rm { - nvidia,pins = "rm"; - nvidia,function = "i2c1"; - }; - sdb { - nvidia,pins = "sdb", "sdc", "sdd"; - nvidia,function = "pwm"; - }; - sdio1 { - nvidia,pins = "sdio1"; - nvidia,function = "sdio1"; - }; - slxc { - nvidia,pins = "slxc", "slxd"; - nvidia,function = "spdif"; - }; - spid { - nvidia,pins = "spid", "spie", "spif"; - nvidia,function = "spi1"; - }; - spig { - nvidia,pins = "spig", "spih"; - nvidia,function = "spi2_alt"; - }; - uaa { - nvidia,pins = "uaa", "uab", "uda"; - nvidia,function = "ulpi"; - }; - uad { - nvidia,pins = "uad"; - nvidia,function = "irda"; - }; - uca { - nvidia,pins = "uca", "ucb"; - nvidia,function = "uartc"; - }; - conf_ata { - nvidia,pins = "ata", "atb", "atc", "atd", "ate", - "cdev1", "cdev2", "dap1", "dtb", "gma", - "gmb", "gmc", "gmd", "gme", "gpu7", - "gpv", "i2cp", "pta", "rm", "slxa", - "slxk", "spia", "spib", "uac"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_ck32 { - nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", - "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; - nvidia,pull = ; - }; - conf_csus { - nvidia,pins = "csus", "spid", "spif"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_crtp { - nvidia,pins = "crtp", "dap2", "dap3", "dap4", - "dtc", "dte", "dtf", "gpu", "sdio1", - "slxc", "slxd", "spdi", "spdo", "spig", - "uda"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_ddc { - nvidia,pins = "ddc", "dta", "dtd", "kbca", - "kbcb", "kbcc", "kbcd", "kbce", "kbcf", - "sdc"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_hdint { - nvidia,pins = "hdint", "lcsn", "ldc", "lm1", - "lpw1", "lsc1", "lsck", "lsda", "lsdi", - "lvp0", "owc", "sdb"; - nvidia,tristate = ; - }; - conf_irrx { - nvidia,pins = "irrx", "irtx", "sdd", "spic", - "spie", "spih", "uaa", "uab", "uad", - "uca", "ucb"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_lc { - nvidia,pins = "lc", "ls"; - nvidia,pull = ; - }; - conf_ld0 { - nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", - "ld5", "ld6", "ld7", "ld8", "ld9", - "ld10", "ld11", "ld12", "ld13", "ld14", - "ld15", "ld16", "ld17", "ldi", "lhp0", - "lhp1", "lhp2", "lhs", "lm0", "lpp", - "lpw0", "lpw2", "lsc0", "lspi", "lvp1", - "lvs", "pmc"; - nvidia,tristate = ; - }; - conf_ld17_0 { - nvidia,pins = "ld17_0", "ld19_18", "ld21_20", - "ld23_22"; - nvidia,pull = ; - }; - }; - }; - - i2s@70002800 { - status = "okay"; - }; - - serial@70006300 { - status = "okay"; - }; - - pwm: pwm@7000a000 { - status = "okay"; - }; - - i2c@7000c000 { - status = "okay"; - clock-frequency = <400000>; - - wm8903: wm8903@1a { - compatible = "wlf,wm8903"; - reg = <0x1a>; - interrupt-parent = <&gpio>; - interrupts = ; - - gpio-controller; - #gpio-cells = <2>; - - micdet-cfg = <0>; - micdet-delay = <100>; - gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>; - }; - }; - - hdmi_ddc: i2c@7000c400 { - status = "okay"; - clock-frequency = <100000>; - }; - - i2c@7000c500 { - status = "okay"; - clock-frequency = <400000>; - }; - - i2c@7000d000 { - status = "okay"; - clock-frequency = <400000>; - - pmic: tps6586x@34 { - compatible = "ti,tps6586x"; - reg = <0x34>; - interrupts = ; - - ti,system-power-controller; - - #gpio-cells = <2>; - gpio-controller; - - sys-supply = <&vdd_5v0_reg>; - vin-sm0-supply = <&sys_reg>; - vin-sm1-supply = <&sys_reg>; - vin-sm2-supply = <&sys_reg>; - vinldo01-supply = <&sm2_reg>; - vinldo23-supply = <&sm2_reg>; - vinldo4-supply = <&sm2_reg>; - vinldo678-supply = <&sm2_reg>; - vinldo9-supply = <&sm2_reg>; - - regulators { - sys_reg: sys { - regulator-name = "vdd_sys"; - regulator-always-on; - }; - - sm0 { - regulator-name = "vdd_sm0,vdd_core"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - sm1 { - regulator-name = "vdd_sm1,vdd_cpu"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - sm2_reg: sm2 { - regulator-name = "vdd_sm2,vin_ldo*"; - regulator-min-microvolt = <3700000>; - regulator-max-microvolt = <3700000>; - regulator-always-on; - }; - - pci_clk_reg: ldo0 { - regulator-name = "vdd_ldo0,vddio_pex_clk"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo1 { - regulator-name = "vdd_ldo1,avdd_pll*"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - ldo2 { - regulator-name = "vdd_ldo2,vdd_rtc"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - ldo3 { - regulator-name = "vdd_ldo3,avdd_usb*"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo4 { - regulator-name = "vdd_ldo4,avdd_osc,vddio_sys"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo5 { - regulator-name = "vdd_ldo5,vcore_mmc"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - regulator-always-on; - }; - - ldo6 { - regulator-name = "vdd_ldo6,avdd_vdac"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - hdmi_vdd_reg: ldo7 { - regulator-name = "vdd_ldo7,avdd_hdmi"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - hdmi_pll_reg: ldo8 { - regulator-name = "vdd_ldo8,avdd_hdmi_pll"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo9 { - regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - regulator-always-on; - }; - - ldo_rtc { - regulator-name = "vdd_rtc_out,vdd_cell"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; - - temperature-sensor@4c { - compatible = "adi,adt7461"; - reg = <0x4c>; - }; - }; - - kbc@7000e200 { - status = "okay"; - nvidia,debounce-delay-ms = <2>; - nvidia,repeat-delay-ms = <160>; - nvidia,kbc-row-pins = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>; - nvidia,kbc-col-pins = <16 17 18 19 20 21 22 23>; - linux,keymap = ; - }; - - pmc@7000e400 { - nvidia,invert-interrupt; - nvidia,suspend-mode = <1>; - nvidia,cpu-pwr-good-time = <5000>; - nvidia,cpu-pwr-off-time = <5000>; - nvidia,core-pwr-good-time = <3845 3845>; - nvidia,core-pwr-off-time = <3875>; - nvidia,sys-clock-req-active-high; - }; - - pcie@80003000 { - status = "okay"; - - avdd-pex-supply = <&pci_vdd_reg>; - vdd-pex-supply = <&pci_vdd_reg>; - avdd-pex-pll-supply = <&pci_vdd_reg>; - avdd-plle-supply = <&pci_vdd_reg>; - vddio-pex-clk-supply = <&pci_clk_reg>; - - pci@1,0 { - status = "okay"; - }; - - pci@2,0 { - status = "okay"; - }; - }; - - usb@c5000000 { - status = "okay"; - }; - - usb-phy@c5000000 { - status = "okay"; - }; - - usb@c5004000 { - status = "okay"; - nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) - GPIO_ACTIVE_LOW>; - }; - - usb-phy@c5004000 { - status = "okay"; - nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) - GPIO_ACTIVE_LOW>; - }; - - usb@c5008000 { - status = "okay"; - }; - - usb-phy@c5008000 { - status = "okay"; - }; - - sdhci@c8000200 { - status = "okay"; - cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; - power-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>; - bus-width = <4>; - }; - - sdhci@c8000600 { - status = "okay"; - cd-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>; - power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>; - bus-width = <8>; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - - enable-gpios = <&gpio TEGRA_GPIO(B, 5) GPIO_ACTIVE_HIGH>; - power-supply = <&vdd_bl_reg>; - pwms = <&pwm 0 5000000>; - - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - }; - - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - power { - label = "Power"; - gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - }; - - panel: panel { - compatible = "auo,b101aw03", "simple-panel"; - - power-supply = <&vdd_pnl_reg>; - enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>; - - backlight = <&backlight>; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - vdd_5v0_reg: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "vdd_5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "vdd_1v5"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; - }; - - regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "vdd_1v2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - pci_vdd_reg: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "vdd_1v05"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vdd_pnl_reg: regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "vdd_pnl"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vdd_bl_reg: regulator@5 { - compatible = "regulator-fixed"; - reg = <5>; - regulator-name = "vdd_bl"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vdd_5v0_hdmi: regulator@6 { - compatible = "regulator-fixed"; - reg = <6>; - regulator-name = "VDDIO_HDMI"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(T, 2) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_5v0_reg>; - }; - }; - - sound { - compatible = "nvidia,tegra-audio-wm8903-harmony", - "nvidia,tegra-audio-wm8903"; - nvidia,model = "NVIDIA Tegra Harmony"; - - nvidia,audio-routing = - "Headphone Jack", "HPOUTR", - "Headphone Jack", "HPOUTL", - "Int Spk", "ROP", - "Int Spk", "RON", - "Int Spk", "LOP", - "Int Spk", "LON", - "Mic Jack", "MICBIAS", - "IN1L", "Mic Jack"; - - nvidia,i2s-controller = <&tegra_i2s1>; - nvidia,audio-codec = <&wm8903>; - - nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; - nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) - GPIO_ACTIVE_HIGH>; - nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(X, 0) - GPIO_ACTIVE_HIGH>; - nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 1) - GPIO_ACTIVE_HIGH>; - - clocks = <&tegra_car TEGRA20_CLK_PLL_A>, - <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA20_CLK_CDEV1>; - clock-names = "pll_a", "pll_a_out0", "mclk"; - }; -}; diff --git a/sys/gnu/dts/arm/tegra20-iris-512.dts b/sys/gnu/dts/arm/tegra20-iris-512.dts deleted file mode 100644 index 1dd7d7bfdfc..00000000000 --- a/sys/gnu/dts/arm/tegra20-iris-512.dts +++ /dev/null @@ -1,101 +0,0 @@ -/dts-v1/; - -#include "tegra20-colibri-512.dtsi" - -/ { - model = "Toradex Colibri T20 512MB on Iris"; - compatible = "toradex,iris", "toradex,colibri_t20-512", "nvidia,tegra20"; - - aliases { - serial0 = &uarta; - serial1 = &uartd; - }; - - host1x@50000000 { - hdmi@54280000 { - status = "okay"; - }; - }; - - pinmux@70000014 { - state_default: pinmux { - hdint { - nvidia,tristate = ; - }; - - i2cddc { - nvidia,tristate = ; - }; - - sdio4 { - nvidia,tristate = ; - }; - - uarta { - nvidia,tristate = ; - }; - - uartd { - nvidia,tristate = ; - }; - }; - }; - - serial@70006000 { - status = "okay"; - }; - - serial@70006300 { - status = "okay"; - }; - - i2c_ddc: i2c@7000c400 { - status = "okay"; - }; - - usb@c5000000 { - status = "okay"; - }; - - usb-phy@c5000000 { - status = "okay"; - }; - - usb@c5008000 { - status = "okay"; - }; - - usb-phy@c5008000 { - status = "okay"; - }; - - sdhci@c8000600 { - status = "okay"; - bus-width = <4>; - vmmc-supply = <&vcc_sd_reg>; - vqmmc-supply = <&vcc_sd_reg>; - }; - - regulators { - regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "usb_host_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - regulator-always-on; - gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>; - }; - - vcc_sd_reg: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "vcc_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - }; -}; diff --git a/sys/gnu/dts/arm/tegra20-medcom-wide.dts b/sys/gnu/dts/arm/tegra20-medcom-wide.dts deleted file mode 100644 index cda5448c2ac..00000000000 --- a/sys/gnu/dts/arm/tegra20-medcom-wide.dts +++ /dev/null @@ -1,135 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "tegra20-tamonten.dtsi" - -/ { - model = "Avionic Design Medcom-Wide board"; - compatible = "ad,medcom-wide", "ad,tamonten", "nvidia,tegra20"; - - aliases { - serial0 = &uartd; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - pwm@7000a000 { - status = "okay"; - }; - - host1x@50000000 { - dc@54200000 { - rgb { - status = "okay"; - nvidia,panel = <&panel>; - }; - }; - }; - - i2c@7000c000 { - wm8903: wm8903@1a { - compatible = "wlf,wm8903"; - reg = <0x1a>; - interrupt-parent = <&gpio>; - interrupts = ; - - gpio-controller; - #gpio-cells = <2>; - - micdet-cfg = <0>; - micdet-delay = <100>; - gpio-cfg = <0xffffffff - 0xffffffff - 0 - 0xffffffff - 0xffffffff>; - }; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 0 5000000>; - - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - }; - - panel: panel { - compatible = "innolux,n156bge-l21", "simple-panel"; - - power-supply = <&vdd_1v8_reg>, <&vdd_3v3_reg>; - enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>; - - backlight = <&backlight>; - }; - - sound { - compatible = "ad,tegra-audio-wm8903-medcom-wide", - "nvidia,tegra-audio-wm8903"; - nvidia,model = "Avionic Design Medcom-Wide"; - - nvidia,audio-routing = - "Headphone Jack", "HPOUTR", - "Headphone Jack", "HPOUTL", - "Int Spk", "ROP", - "Int Spk", "RON", - "Int Spk", "LOP", - "Int Spk", "LON", - "Mic Jack", "MICBIAS", - "IN1L", "Mic Jack"; - - nvidia,i2s-controller = <&tegra_i2s1>; - nvidia,audio-codec = <&wm8903>; - - nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; - nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>; - - clocks = <&tegra_car TEGRA20_CLK_PLL_A>, - <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA20_CLK_CDEV1>; - clock-names = "pll_a", "pll_a_out0", "mclk"; - }; - - regulators { - vcc_24v_reg: regulator@100 { - compatible = "regulator-fixed"; - reg = <100>; - regulator-name = "vcc_24v"; - regulator-min-microvolt = <24000000>; - regulator-max-microvolt = <24000000>; - regulator-always-on; - }; - - vdd_5v0_reg: regulator@101 { - compatible = "regulator-fixed"; - reg = <101>; - regulator-name = "vdd_5v0"; - vin-supply = <&vcc_24v_reg>; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - vdd_3v3_reg: regulator@102 { - compatible = "regulator-fixed"; - reg = <102>; - regulator-name = "vdd_3v3"; - vin-supply = <&vcc_24v_reg>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_1v8_reg: regulator@103 { - compatible = "regulator-fixed"; - reg = <103>; - regulator-name = "vdd_1v8"; - vin-supply = <&vdd_3v3_reg>; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - }; -}; diff --git a/sys/gnu/dts/arm/tegra20-paz00.dts b/sys/gnu/dts/arm/tegra20-paz00.dts deleted file mode 100644 index be0ab9b84b9..00000000000 --- a/sys/gnu/dts/arm/tegra20-paz00.dts +++ /dev/null @@ -1,679 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include -#include "tegra20.dtsi" -#include "tegra20-cpu-opp.dtsi" -#include "tegra20-cpu-opp-microvolt.dtsi" - -/ { - model = "Toshiba AC100 / Dynabook AZ"; - compatible = "compal,paz00", "nvidia,tegra20"; - - aliases { - rtc0 = "/i2c@7000d000/tps6586x@34"; - rtc1 = "/rtc@7000e000"; - serial0 = &uarta; - serial1 = &uartc; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - reg = <0x00000000 0x20000000>; - }; - - host1x@50000000 { - dc@54200000 { - rgb { - status = "okay"; - - nvidia,panel = <&panel>; - }; - }; - - hdmi@54280000 { - status = "okay"; - - vdd-supply = <&hdmi_vdd_reg>; - pll-supply = <&hdmi_pll_reg>; - - nvidia,ddc-i2c-bus = <&hdmi_ddc>; - nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) - GPIO_ACTIVE_HIGH>; - }; - }; - - pinmux@70000014 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - ata { - nvidia,pins = "ata", "atc", "atd", "ate", - "dap2", "gmb", "gmc", "gmd", "spia", - "spib", "spic", "spid", "spie"; - nvidia,function = "gmi"; - }; - atb { - nvidia,pins = "atb", "gma", "gme"; - nvidia,function = "sdio4"; - }; - cdev1 { - nvidia,pins = "cdev1"; - nvidia,function = "plla_out"; - }; - cdev2 { - nvidia,pins = "cdev2"; - nvidia,function = "pllp_out4"; - }; - crtp { - nvidia,pins = "crtp"; - nvidia,function = "crt"; - }; - csus { - nvidia,pins = "csus"; - nvidia,function = "pllc_out1"; - }; - dap1 { - nvidia,pins = "dap1"; - nvidia,function = "dap1"; - }; - dap3 { - nvidia,pins = "dap3"; - nvidia,function = "dap3"; - }; - dap4 { - nvidia,pins = "dap4"; - nvidia,function = "dap4"; - }; - ddc { - nvidia,pins = "ddc"; - nvidia,function = "i2c2"; - }; - dta { - nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte"; - nvidia,function = "rsvd1"; - }; - dtf { - nvidia,pins = "dtf"; - nvidia,function = "i2c3"; - }; - gpu { - nvidia,pins = "gpu", "sdb", "sdd"; - nvidia,function = "pwm"; - }; - gpu7 { - nvidia,pins = "gpu7"; - nvidia,function = "rtck"; - }; - gpv { - nvidia,pins = "gpv", "slxa", "slxk"; - nvidia,function = "pcie"; - }; - hdint { - nvidia,pins = "hdint", "pta"; - nvidia,function = "hdmi"; - }; - i2cp { - nvidia,pins = "i2cp"; - nvidia,function = "i2cp"; - }; - irrx { - nvidia,pins = "irrx", "irtx"; - nvidia,function = "uarta"; - }; - kbca { - nvidia,pins = "kbca", "kbcc", "kbce", "kbcf"; - nvidia,function = "kbc"; - }; - kbcb { - nvidia,pins = "kbcb", "kbcd"; - nvidia,function = "sdio2"; - }; - lcsn { - nvidia,pins = "lcsn", "ld0", "ld1", "ld2", - "ld3", "ld4", "ld5", "ld6", "ld7", - "ld8", "ld9", "ld10", "ld11", "ld12", - "ld13", "ld14", "ld15", "ld16", "ld17", - "ldc", "ldi", "lhp0", "lhp1", "lhp2", - "lhs", "lm0", "lm1", "lpp", "lpw0", - "lpw1", "lpw2", "lsc0", "lsc1", "lsck", - "lsda", "lsdi", "lspi", "lvp0", "lvp1", - "lvs"; - nvidia,function = "displaya"; - }; - owc { - nvidia,pins = "owc"; - nvidia,function = "owr"; - }; - pmc { - nvidia,pins = "pmc"; - nvidia,function = "pwr_on"; - }; - rm { - nvidia,pins = "rm"; - nvidia,function = "i2c1"; - }; - sdc { - nvidia,pins = "sdc"; - nvidia,function = "twc"; - }; - sdio1 { - nvidia,pins = "sdio1"; - nvidia,function = "sdio1"; - }; - slxc { - nvidia,pins = "slxc", "slxd"; - nvidia,function = "spi4"; - }; - spdi { - nvidia,pins = "spdi", "spdo"; - nvidia,function = "rsvd2"; - }; - spif { - nvidia,pins = "spif", "uac"; - nvidia,function = "rsvd4"; - }; - spig { - nvidia,pins = "spig", "spih"; - nvidia,function = "spi2_alt"; - }; - uaa { - nvidia,pins = "uaa", "uab", "uda"; - nvidia,function = "ulpi"; - }; - uad { - nvidia,pins = "uad"; - nvidia,function = "spdif"; - }; - uca { - nvidia,pins = "uca", "ucb"; - nvidia,function = "uartc"; - }; - conf_ata { - nvidia,pins = "ata", "atb", "atc", "atd", "ate", - "cdev1", "cdev2", "dap1", "dap2", "dtf", - "gma", "gmb", "gmc", "gmd", "gme", - "gpu", "gpu7", "gpv", "i2cp", "pta", - "rm", "sdio1", "slxk", "spdo", "uac", - "uda"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_ck32 { - nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", - "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; - nvidia,pull = ; - }; - conf_crtp { - nvidia,pins = "crtp", "dap3", "dap4", "dtb", - "dtc", "dte", "slxa", "slxc", "slxd", - "spdi"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_csus { - nvidia,pins = "csus", "spia", "spib", "spid", - "spif"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_ddc { - nvidia,pins = "ddc", "irrx", "irtx", "kbca", - "kbcb", "kbcc", "kbcd", "kbce", "kbcf", - "spic", "spig", "uaa", "uab"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_dta { - nvidia,pins = "dta", "dtd", "owc", "sdc", "sdd", - "spie", "spih", "uad", "uca", "ucb"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_hdint { - nvidia,pins = "hdint", "ld0", "ld1", "ld2", - "ld3", "ld4", "ld5", "ld6", "ld7", - "ld8", "ld9", "ld10", "ld11", "ld12", - "ld13", "ld14", "ld15", "ld16", "ld17", - "ldc", "ldi", "lhs", "lsc0", "lspi", - "lvs", "pmc"; - nvidia,tristate = ; - }; - conf_lc { - nvidia,pins = "lc", "ls"; - nvidia,pull = ; - }; - conf_lcsn { - nvidia,pins = "lcsn", "lhp0", "lhp1", "lhp2", - "lm0", "lm1", "lpp", "lpw0", "lpw1", - "lpw2", "lsc1", "lsck", "lsda", "lsdi", - "lvp0", "lvp1", "sdb"; - nvidia,tristate = ; - }; - conf_ld17_0 { - nvidia,pins = "ld17_0", "ld19_18", "ld21_20", - "ld23_22"; - nvidia,pull = ; - }; - }; - }; - - i2s@70002800 { - status = "okay"; - }; - - serial@70006000 { - status = "okay"; - }; - - serial@70006200 { - status = "okay"; - }; - - pwm: pwm@7000a000 { - status = "okay"; - }; - - lvds_ddc: i2c@7000c000 { - status = "okay"; - clock-frequency = <400000>; - - alc5632: alc5632@1e { - compatible = "realtek,alc5632"; - reg = <0x1e>; - gpio-controller; - #gpio-cells = <2>; - }; - }; - - hdmi_ddc: i2c@7000c400 { - status = "okay"; - clock-frequency = <100000>; - }; - - nvec@7000c500 { - compatible = "nvidia,nvec"; - reg = <0x7000c500 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-frequency = <80000>; - request-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; - slave-addr = <138>; - clocks = <&tegra_car TEGRA20_CLK_I2C3>, - <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; - clock-names = "div-clk", "fast-clk"; - resets = <&tegra_car 67>; - reset-names = "i2c"; - }; - - memory-controller@7000f400 { - nvidia,use-ram-code; - - emc-tables@hynix { - nvidia,ram-code = <0x0>; - #address-cells = <1>; - #size-cells = <0>; - - emc-table@166500 { - reg = <166500>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <166500>; - nvidia,emc-registers = <0x0000000a 0x00000016 - 0x00000008 0x00000003 0x00000004 0x00000004 - 0x00000002 0x0000000c 0x00000003 0x00000003 - 0x00000002 0x00000001 0x00000004 0x00000005 - 0x00000004 0x00000009 0x0000000d 0x000004df - 0x00000000 0x00000003 0x00000003 0x00000003 - 0x00000003 0x00000001 0x0000000a 0x000000c8 - 0x00000003 0x00000006 0x00000004 0x00000008 - 0x00000002 0x00000000 0x00000000 0x00000002 - 0x00000000 0x00000000 0x00000083 0xe03b0323 - 0x007fe010 0x00001414 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000>; - }; - - emc-table@333000 { - reg = <333000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <333000>; - nvidia,emc-registers = <0x00000018 0x00000033 - 0x00000012 0x00000004 0x00000004 0x00000005 - 0x00000003 0x0000000c 0x00000006 0x00000006 - 0x00000003 0x00000001 0x00000004 0x00000005 - 0x00000004 0x00000009 0x0000000d 0x00000bff - 0x00000000 0x00000003 0x00000003 0x00000006 - 0x00000006 0x00000001 0x00000011 0x000000c8 - 0x00000003 0x0000000e 0x00000007 0x00000008 - 0x00000002 0x00000000 0x00000000 0x00000002 - 0x00000000 0x00000000 0x00000083 0xf0440303 - 0x007fe010 0x00001414 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000>; - }; - }; - }; - - i2c@7000d000 { - status = "okay"; - clock-frequency = <400000>; - - pmic: tps6586x@34 { - compatible = "ti,tps6586x"; - reg = <0x34>; - interrupts = ; - - #gpio-cells = <2>; - gpio-controller; - - sys-supply = <&p5valw_reg>; - vin-sm0-supply = <&sys_reg>; - vin-sm1-supply = <&sys_reg>; - vin-sm2-supply = <&sys_reg>; - vinldo01-supply = <&sm2_reg>; - vinldo23-supply = <&sm2_reg>; - vinldo4-supply = <&sm2_reg>; - vinldo678-supply = <&sm2_reg>; - vinldo9-supply = <&sm2_reg>; - - regulators { - sys_reg: sys { - regulator-name = "vdd_sys"; - regulator-always-on; - }; - - core_vdd_reg: sm0 { - regulator-name = "+1.2vs_sm0,vdd_core"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1225000>; - regulator-coupled-with = <&rtc_vdd_reg &cpu_vdd_reg>; - regulator-coupled-max-spread = <170000 450000>; - regulator-always-on; - - nvidia,tegra-core-regulator; - }; - - cpu_vdd_reg: sm1 { - regulator-name = "+1.0vs_sm1,vdd_cpu"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1100000>; - regulator-coupled-with = <&core_vdd_reg &rtc_vdd_reg>; - regulator-coupled-max-spread = <450000 450000>; - regulator-always-on; - - nvidia,tegra-cpu-regulator; - }; - - sm2_reg: sm2 { - regulator-name = "+3.7vs_sm2,vin_ldo*"; - regulator-min-microvolt = <3700000>; - regulator-max-microvolt = <3700000>; - regulator-always-on; - }; - - /* LDO0 is not connected to anything */ - - ldo1 { - regulator-name = "+1.1vs_ldo1,avdd_pll*"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - rtc_vdd_reg: ldo2 { - regulator-name = "+1.2vs_ldo2,vdd_rtc"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1225000>; - regulator-coupled-with = <&core_vdd_reg &cpu_vdd_reg>; - regulator-coupled-max-spread = <170000 450000>; - regulator-always-on; - - nvidia,tegra-rtc-regulator; - }; - - ldo3 { - regulator-name = "+3.3vs_ldo3,avdd_usb*"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo4 { - regulator-name = "+1.8vs_ldo4,avdd_osc,vddio_sys"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo5 { - regulator-name = "+2.85vs_ldo5,vcore_mmc"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - regulator-always-on; - }; - - ldo6 { - /* - * Research indicates this should be - * 1.8v; other boards that use this - * rail for the same purpose need it - * set to 1.8v. The schematic signal - * name is incorrect; perhaps copied - * from an incorrect NVIDIA reference. - */ - regulator-name = "+2.85vs_ldo6,avdd_vdac"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - hdmi_vdd_reg: ldo7 { - regulator-name = "+3.3vs_ldo7,avdd_hdmi"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - hdmi_pll_reg: ldo8 { - regulator-name = "+1.8vs_ldo8,avdd_hdmi_pll"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo9 { - regulator-name = "+2.85vs_ldo9,vdd_ddr_rx"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - regulator-always-on; - }; - - ldo_rtc { - regulator-name = "+3.3vs_rtc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; - - adt7461@4c { - compatible = "adi,adt7461"; - reg = <0x4c>; - }; - }; - - pmc@7000e400 { - nvidia,invert-interrupt; - nvidia,suspend-mode = <1>; - nvidia,cpu-pwr-good-time = <2000>; - nvidia,cpu-pwr-off-time = <0>; - nvidia,core-pwr-good-time = <3845 3845>; - nvidia,core-pwr-off-time = <0>; - nvidia,sys-clock-req-active-high; - }; - - usb@c5000000 { - compatible = "nvidia,tegra20-udc"; - status = "okay"; - dr_mode = "peripheral"; - }; - - usb-phy@c5000000 { - status = "okay"; - }; - - usb@c5004000 { - status = "okay"; - nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0) - GPIO_ACTIVE_LOW>; - }; - - usb-phy@c5004000 { - status = "okay"; - nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0) - GPIO_ACTIVE_LOW>; - }; - - usb@c5008000 { - status = "okay"; - }; - - usb-phy@c5008000 { - status = "okay"; - }; - - sdhci@c8000000 { - status = "okay"; - cd-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; - power-gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>; - bus-width = <4>; - }; - - sdhci@c8000600 { - status = "okay"; - bus-width = <8>; - non-removable; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - - enable-gpios = <&gpio TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>; - pwms = <&pwm 0 5000000>; - - brightness-levels = <0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 255>; - default-brightness-level = <10>; - - backlight-boot-off; - }; - - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - wakeup { - label = "Wakeup"; - gpios = <&gpio TEGRA_GPIO(J, 7) GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - wifi { - label = "wifi-led"; - gpios = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>; - linux,default-trigger = "rfkill0"; - }; - }; - - panel: panel { - compatible = "samsung,ltn101nt05", "simple-panel"; - - ddc-i2c-bus = <&lvds_ddc>; - power-supply = <&vdd_pnl_reg>; - enable-gpios = <&gpio TEGRA_GPIO(M, 6) GPIO_ACTIVE_HIGH>; - - backlight = <&backlight>; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - p5valw_reg: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "+5valw"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - vdd_pnl_reg: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "+3VS,vdd_pnl"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - gpio = <&gpio TEGRA_GPIO(A, 4) GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - }; - - sound { - compatible = "nvidia,tegra-audio-alc5632-paz00", - "nvidia,tegra-audio-alc5632"; - - nvidia,model = "Compal PAZ00"; - - nvidia,audio-routing = - "Int Spk", "SPKOUT", - "Int Spk", "SPKOUTN", - "Headset Mic", "MICBIAS1", - "MIC1", "Headset Mic", - "Headset Stereophone", "HPR", - "Headset Stereophone", "HPL", - "DMICDAT", "Digital Mic"; - - nvidia,audio-codec = <&alc5632>; - nvidia,i2s-controller = <&tegra_i2s1>; - nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) - GPIO_ACTIVE_HIGH>; - - clocks = <&tegra_car TEGRA20_CLK_PLL_A>, - <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA20_CLK_CDEV1>; - clock-names = "pll_a", "pll_a_out0", "mclk"; - }; - - cpus { - cpu0: cpu@0 { - cpu-supply = <&cpu_vdd_reg>; - operating-points-v2 = <&cpu0_opp_table>; - }; - - cpu@1 { - cpu-supply = <&cpu_vdd_reg>; - operating-points-v2 = <&cpu0_opp_table>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/tegra20-plutux.dts b/sys/gnu/dts/arm/tegra20-plutux.dts deleted file mode 100644 index 429e4605fbd..00000000000 --- a/sys/gnu/dts/arm/tegra20-plutux.dts +++ /dev/null @@ -1,103 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "tegra20-tamonten.dtsi" - -/ { - model = "Avionic Design Plutux board"; - compatible = "ad,plutux", "ad,tamonten", "nvidia,tegra20"; - - host1x@50000000 { - hdmi@54280000 { - status = "okay"; - }; - }; - - i2c@7000c000 { - wm8903: wm8903@1a { - compatible = "wlf,wm8903"; - reg = <0x1a>; - interrupt-parent = <&gpio>; - interrupts = ; - - gpio-controller; - #gpio-cells = <2>; - - micdet-cfg = <0>; - micdet-delay = <100>; - gpio-cfg = <0xffffffff - 0xffffffff - 0 - 0xffffffff - 0xffffffff>; - }; - }; - - sound { - compatible = "ad,tegra-audio-plutux", - "nvidia,tegra-audio-wm8903"; - nvidia,model = "Avionic Design Plutux"; - - nvidia,audio-routing = - "Headphone Jack", "HPOUTR", - "Headphone Jack", "HPOUTL", - "Int Spk", "ROP", - "Int Spk", "RON", - "Int Spk", "LOP", - "Int Spk", "LON", - "Mic Jack", "MICBIAS", - "IN1L", "Mic Jack"; - - nvidia,i2s-controller = <&tegra_i2s1>; - nvidia,audio-codec = <&wm8903>; - - nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; - nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>; - - clocks = <&tegra_car TEGRA20_CLK_PLL_A>, - <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA20_CLK_CDEV1>; - clock-names = "pll_a", "pll_a_out0", "mclk"; - }; - - regulators { - vcc_24v_reg: regulator@100 { - compatible = "regulator-fixed"; - reg = <100>; - regulator-name = "vcc_24v"; - regulator-min-microvolt = <24000000>; - regulator-max-microvolt = <24000000>; - regulator-always-on; - }; - - vdd_5v0_reg: regulator@101 { - compatible = "regulator-fixed"; - reg = <101>; - regulator-name = "vdd_5v0"; - vin-supply = <&vcc_24v_reg>; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - vdd_3v3_reg: regulator@102 { - compatible = "regulator-fixed"; - reg = <102>; - regulator-name = "vdd_3v3"; - vin-supply = <&vcc_24v_reg>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_1v8_reg: regulator@103 { - compatible = "regulator-fixed"; - reg = <103>; - regulator-name = "vdd_1v8"; - vin-supply = <&vdd_3v3_reg>; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - }; -}; diff --git a/sys/gnu/dts/arm/tegra20-seaboard.dts b/sys/gnu/dts/arm/tegra20-seaboard.dts deleted file mode 100644 index f91441683aa..00000000000 --- a/sys/gnu/dts/arm/tegra20-seaboard.dts +++ /dev/null @@ -1,941 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include -#include "tegra20.dtsi" - -/ { - model = "NVIDIA Seaboard"; - compatible = "nvidia,seaboard", "nvidia,tegra20"; - - aliases { - rtc0 = "/i2c@7000d000/tps6586x@34"; - rtc1 = "/rtc@7000e000"; - serial0 = &uartd; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - reg = <0x00000000 0x40000000>; - }; - - host1x@50000000 { - dc@54200000 { - rgb { - status = "okay"; - - nvidia,panel = <&panel>; - }; - }; - - hdmi@54280000 { - status = "okay"; - - vdd-supply = <&hdmi_vdd_reg>; - pll-supply = <&hdmi_pll_reg>; - hdmi-supply = <&vdd_hdmi>; - - nvidia,ddc-i2c-bus = <&hdmi_ddc>; - nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) - GPIO_ACTIVE_HIGH>; - }; - }; - - pinmux@70000014 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - ata { - nvidia,pins = "ata"; - nvidia,function = "ide"; - }; - atb { - nvidia,pins = "atb", "gma", "gme"; - nvidia,function = "sdio4"; - }; - atc { - nvidia,pins = "atc"; - nvidia,function = "nand"; - }; - atd { - nvidia,pins = "atd", "ate", "gmb", "spia", - "spib", "spic"; - nvidia,function = "gmi"; - }; - cdev1 { - nvidia,pins = "cdev1"; - nvidia,function = "plla_out"; - }; - cdev2 { - nvidia,pins = "cdev2"; - nvidia,function = "pllp_out4"; - }; - crtp { - nvidia,pins = "crtp", "lm1"; - nvidia,function = "crt"; - }; - csus { - nvidia,pins = "csus"; - nvidia,function = "vi_sensor_clk"; - }; - dap1 { - nvidia,pins = "dap1"; - nvidia,function = "dap1"; - }; - dap2 { - nvidia,pins = "dap2"; - nvidia,function = "dap2"; - }; - dap3 { - nvidia,pins = "dap3"; - nvidia,function = "dap3"; - }; - dap4 { - nvidia,pins = "dap4"; - nvidia,function = "dap4"; - }; - dta { - nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte"; - nvidia,function = "vi"; - }; - dtf { - nvidia,pins = "dtf"; - nvidia,function = "i2c3"; - }; - gmc { - nvidia,pins = "gmc"; - nvidia,function = "uartd"; - }; - gmd { - nvidia,pins = "gmd"; - nvidia,function = "sflash"; - }; - gpu { - nvidia,pins = "gpu"; - nvidia,function = "pwm"; - }; - gpu7 { - nvidia,pins = "gpu7"; - nvidia,function = "rtck"; - }; - gpv { - nvidia,pins = "gpv", "slxa", "slxk"; - nvidia,function = "pcie"; - }; - hdint { - nvidia,pins = "hdint", "lpw0", "lpw2", "lsc1", - "lsck", "lsda"; - nvidia,function = "hdmi"; - }; - i2cp { - nvidia,pins = "i2cp"; - nvidia,function = "i2cp"; - }; - irrx { - nvidia,pins = "irrx", "irtx"; - nvidia,function = "uartb"; - }; - kbca { - nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", - "kbce", "kbcf"; - nvidia,function = "kbc"; - }; - lcsn { - nvidia,pins = "lcsn", "ldc", "lm0", "lpw1", - "lsdi", "lvp0"; - nvidia,function = "rsvd4"; - }; - ld0 { - nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", - "ld5", "ld6", "ld7", "ld8", "ld9", - "ld10", "ld11", "ld12", "ld13", "ld14", - "ld15", "ld16", "ld17", "ldi", "lhp0", - "lhp1", "lhp2", "lhs", "lpp", "lsc0", - "lspi", "lvp1", "lvs"; - nvidia,function = "displaya"; - }; - owc { - nvidia,pins = "owc", "spdi", "spdo", "uac"; - nvidia,function = "rsvd2"; - }; - pmc { - nvidia,pins = "pmc"; - nvidia,function = "pwr_on"; - }; - rm { - nvidia,pins = "rm"; - nvidia,function = "i2c1"; - }; - sdb { - nvidia,pins = "sdb", "sdc", "sdd"; - nvidia,function = "sdio3"; - }; - sdio1 { - nvidia,pins = "sdio1"; - nvidia,function = "sdio1"; - }; - slxc { - nvidia,pins = "slxc", "slxd"; - nvidia,function = "spdif"; - }; - spid { - nvidia,pins = "spid", "spie", "spif"; - nvidia,function = "spi1"; - }; - spig { - nvidia,pins = "spig", "spih"; - nvidia,function = "spi2_alt"; - }; - uaa { - nvidia,pins = "uaa", "uab", "uda"; - nvidia,function = "ulpi"; - }; - uad { - nvidia,pins = "uad"; - nvidia,function = "irda"; - }; - uca { - nvidia,pins = "uca", "ucb"; - nvidia,function = "uartc"; - }; - conf_ata { - nvidia,pins = "ata", "atb", "atc", "atd", - "cdev1", "cdev2", "dap1", "dap2", - "dap4", "ddc", "dtf", "gma", "gmc", "gmd", - "gme", "gpu", "gpu7", "i2cp", "irrx", - "irtx", "pta", "rm", "sdc", "sdd", - "slxd", "slxk", "spdi", "spdo", "uac", - "uad", "uca", "ucb", "uda"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_ate { - nvidia,pins = "ate", "csus", "dap3", - "gpv", "owc", "slxc", "spib", "spid", - "spie"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_ck32 { - nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", - "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; - nvidia,pull = ; - }; - conf_crtp { - nvidia,pins = "crtp", "gmb", "slxa", "spia", - "spig", "spih"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_dta { - nvidia,pins = "dta", "dtb", "dtc", "dtd"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_dte { - nvidia,pins = "dte", "spif"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_hdint { - nvidia,pins = "hdint", "lcsn", "ldc", "lm1", - "lpw1", "lsc1", "lsck", "lsda", "lsdi", - "lvp0"; - nvidia,tristate = ; - }; - conf_kbca { - nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", - "kbce", "kbcf", "sdio1", "spic", "uaa", - "uab"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_lc { - nvidia,pins = "lc", "ls"; - nvidia,pull = ; - }; - conf_ld0 { - nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", - "ld5", "ld6", "ld7", "ld8", "ld9", - "ld10", "ld11", "ld12", "ld13", "ld14", - "ld15", "ld16", "ld17", "ldi", "lhp0", - "lhp1", "lhp2", "lhs", "lm0", "lpp", - "lpw0", "lpw2", "lsc0", "lspi", "lvp1", - "lvs", "pmc", "sdb"; - nvidia,tristate = ; - }; - conf_ld17_0 { - nvidia,pins = "ld17_0", "ld19_18", "ld21_20", - "ld23_22"; - nvidia,pull = ; - }; - drive_sdio1 { - nvidia,pins = "drive_sdio1"; - nvidia,high-speed-mode = ; - nvidia,schmitt = ; - nvidia,low-power-mode = ; - nvidia,pull-down-strength = <31>; - nvidia,pull-up-strength = <31>; - nvidia,slew-rate-rising = ; - nvidia,slew-rate-falling = ; - }; - }; - - state_i2cmux_ddc: pinmux_i2cmux_ddc { - ddc { - nvidia,pins = "ddc"; - nvidia,function = "i2c2"; - }; - pta { - nvidia,pins = "pta"; - nvidia,function = "rsvd4"; - }; - }; - - state_i2cmux_pta: pinmux_i2cmux_pta { - ddc { - nvidia,pins = "ddc"; - nvidia,function = "rsvd4"; - }; - pta { - nvidia,pins = "pta"; - nvidia,function = "i2c2"; - }; - }; - - state_i2cmux_idle: pinmux_i2cmux_idle { - ddc { - nvidia,pins = "ddc"; - nvidia,function = "rsvd4"; - }; - pta { - nvidia,pins = "pta"; - nvidia,function = "rsvd4"; - }; - }; - }; - - i2s@70002800 { - status = "okay"; - }; - - serial@70006300 { - status = "okay"; - }; - - pwm: pwm@7000a000 { - status = "okay"; - }; - - i2c@7000c000 { - status = "okay"; - clock-frequency = <400000>; - - wm8903: wm8903@1a { - compatible = "wlf,wm8903"; - reg = <0x1a>; - interrupt-parent = <&gpio>; - interrupts = ; - - gpio-controller; - #gpio-cells = <2>; - - micdet-cfg = <0>; - micdet-delay = <100>; - gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>; - }; - - /* ALS and proximity sensor */ - isl29018@44 { - compatible = "isil,isl29018"; - reg = <0x44>; - interrupt-parent = <&gpio>; - interrupts = ; - }; - - gyrometer@68 { - compatible = "invn,mpu3050"; - reg = <0x68>; - interrupt-parent = <&gpio>; - interrupts = ; - }; - }; - - i2c@7000c400 { - status = "okay"; - clock-frequency = <100000>; - }; - - i2cmux { - compatible = "i2c-mux-pinctrl"; - #address-cells = <1>; - #size-cells = <0>; - - i2c-parent = <&{/i2c@7000c400}>; - - pinctrl-names = "ddc", "pta", "idle"; - pinctrl-0 = <&state_i2cmux_ddc>; - pinctrl-1 = <&state_i2cmux_pta>; - pinctrl-2 = <&state_i2cmux_idle>; - - hdmi_ddc: i2c@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - }; - - lvds_ddc: i2c@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - smart-battery@b { - compatible = "ti,bq20z75", "smart-battery-1.1"; - reg = <0xb>; - ti,i2c-retry-count = <2>; - ti,poll-retry-count = <10>; - }; - }; - }; - - i2c@7000c500 { - status = "okay"; - clock-frequency = <400000>; - }; - - i2c@7000d000 { - status = "okay"; - clock-frequency = <400000>; - - magnetometer@c { - compatible = "asahi-kasei,ak8975"; - reg = <0xc>; - interrupt-parent = <&gpio>; - interrupts = ; - }; - - pmic: tps6586x@34 { - compatible = "ti,tps6586x"; - reg = <0x34>; - interrupts = ; - - ti,system-power-controller; - - #gpio-cells = <2>; - gpio-controller; - - sys-supply = <&vdd_5v0_reg>; - vin-sm0-supply = <&sys_reg>; - vin-sm1-supply = <&sys_reg>; - vin-sm2-supply = <&sys_reg>; - vinldo01-supply = <&sm2_reg>; - vinldo23-supply = <&sm2_reg>; - vinldo4-supply = <&sm2_reg>; - vinldo678-supply = <&sm2_reg>; - vinldo9-supply = <&sm2_reg>; - - regulators { - sys_reg: sys { - regulator-name = "vdd_sys"; - regulator-always-on; - }; - - sm0 { - regulator-name = "vdd_sm0,vdd_core"; - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - }; - - sm1 { - regulator-name = "vdd_sm1,vdd_cpu"; - regulator-min-microvolt = <1125000>; - regulator-max-microvolt = <1125000>; - regulator-always-on; - }; - - sm2_reg: sm2 { - regulator-name = "vdd_sm2,vin_ldo*"; - regulator-min-microvolt = <3700000>; - regulator-max-microvolt = <3700000>; - regulator-always-on; - }; - - /* LDO0 is not connected to anything */ - - ldo1 { - regulator-name = "vdd_ldo1,avdd_pll*"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - ldo2 { - regulator-name = "vdd_ldo2,vdd_rtc"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - ldo3 { - regulator-name = "vdd_ldo3,avdd_usb*"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo4 { - regulator-name = "vdd_ldo4,avdd_osc,vddio_sys"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo5 { - regulator-name = "vdd_ldo5,vcore_mmc"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - regulator-always-on; - }; - - ldo6 { - regulator-name = "vdd_ldo6,avdd_vdac,vddio_vi,vddio_cam"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - hdmi_vdd_reg: ldo7 { - regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - hdmi_pll_reg: ldo8 { - regulator-name = "vdd_ldo8,avdd_hdmi_pll"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo9 { - regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - regulator-always-on; - }; - - ldo_rtc { - regulator-name = "vdd_rtc_out,vdd_cell"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; - - temperature-sensor@4c { - compatible = "onnn,nct1008"; - reg = <0x4c>; - }; - }; - - kbc@7000e200 { - status = "okay"; - nvidia,debounce-delay-ms = <32>; - nvidia,repeat-delay-ms = <160>; - nvidia,ghost-filter; - nvidia,kbc-row-pins = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>; - nvidia,kbc-col-pins = <16 17 18 19 20 21 22 23>; - linux,keymap = ; - }; - - pmc@7000e400 { - nvidia,invert-interrupt; - nvidia,suspend-mode = <1>; - nvidia,cpu-pwr-good-time = <5000>; - nvidia,cpu-pwr-off-time = <5000>; - nvidia,core-pwr-good-time = <3845 3845>; - nvidia,core-pwr-off-time = <3875>; - nvidia,sys-clock-req-active-high; - }; - - memory-controller@7000f400 { - emc-table@190000 { - reg = <190000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <190000>; - nvidia,emc-registers = <0x0000000c 0x00000026 - 0x00000009 0x00000003 0x00000004 0x00000004 - 0x00000002 0x0000000c 0x00000003 0x00000003 - 0x00000002 0x00000001 0x00000004 0x00000005 - 0x00000004 0x00000009 0x0000000d 0x0000059f - 0x00000000 0x00000003 0x00000003 0x00000003 - 0x00000003 0x00000001 0x0000000b 0x000000c8 - 0x00000003 0x00000007 0x00000004 0x0000000f - 0x00000002 0x00000000 0x00000000 0x00000002 - 0x00000000 0x00000000 0x00000083 0xa06204ae - 0x007dc010 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000>; - }; - - emc-table@380000 { - reg = <380000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <380000>; - nvidia,emc-registers = <0x00000017 0x0000004b - 0x00000012 0x00000006 0x00000004 0x00000005 - 0x00000003 0x0000000c 0x00000006 0x00000006 - 0x00000003 0x00000001 0x00000004 0x00000005 - 0x00000004 0x00000009 0x0000000d 0x00000b5f - 0x00000000 0x00000003 0x00000003 0x00000006 - 0x00000006 0x00000001 0x00000011 0x000000c8 - 0x00000003 0x0000000e 0x00000007 0x0000000f - 0x00000002 0x00000000 0x00000000 0x00000002 - 0x00000000 0x00000000 0x00000083 0xe044048b - 0x007d8010 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000>; - }; - }; - - usb@c5000000 { - status = "okay"; - dr_mode = "otg"; - }; - - usb-phy@c5000000 { - status = "okay"; - vbus-supply = <&vbus_reg>; - dr_mode = "otg"; - }; - - usb@c5004000 { - status = "okay"; - nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) - GPIO_ACTIVE_LOW>; - }; - - usb-phy@c5004000 { - status = "okay"; - nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) - GPIO_ACTIVE_LOW>; - }; - - usb@c5008000 { - status = "okay"; - }; - - usb-phy@c5008000 { - status = "okay"; - }; - - sdhci@c8000000 { - status = "okay"; - power-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; - bus-width = <4>; - keep-power-in-suspend; - }; - - sdhci@c8000400 { - status = "okay"; - cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; - power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>; - bus-width = <4>; - }; - - sdhci@c8000600 { - status = "okay"; - bus-width = <8>; - non-removable; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - - enable-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>; - power-supply = <&vdd_bl_reg>; - pwms = <&pwm 2 5000000>; - - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - }; - - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - power { - label = "Power"; - gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - - lid { - label = "Lid"; - gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_HIGH>; - linux,input-type = <5>; /* EV_SW */ - linux,code = <0>; /* SW_LID */ - debounce-interval = <1>; - wakeup-source; - }; - }; - - panel: panel { - compatible = "chunghwa,claa101wa01a", "simple-panel"; - - power-supply = <&vdd_pnl_reg>; - enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>; - - backlight = <&backlight>; - ddc-i2c-bus = <&lvds_ddc>; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - vdd_5v0_reg: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "vdd_5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "vdd_1v5"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; - }; - - regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "vdd_1v2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vbus_reg: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "vdd_vbus_wup1"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(D, 0) 0>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_pnl_reg: regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "vdd_pnl"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vdd_bl_reg: regulator@5 { - compatible = "regulator-fixed"; - reg = <5>; - regulator-name = "vdd_bl"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vdd_hdmi: regulator@6 { - compatible = "regulator-fixed"; - reg = <6>; - regulator-name = "VDDIO_HDMI"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_5v0_reg>; - }; - }; - - sound { - compatible = "nvidia,tegra-audio-wm8903-seaboard", - "nvidia,tegra-audio-wm8903"; - nvidia,model = "NVIDIA Tegra Seaboard"; - - nvidia,audio-routing = - "Headphone Jack", "HPOUTR", - "Headphone Jack", "HPOUTL", - "Int Spk", "ROP", - "Int Spk", "RON", - "Int Spk", "LOP", - "Int Spk", "LON", - "Mic Jack", "MICBIAS", - "IN1R", "Mic Jack"; - - nvidia,i2s-controller = <&tegra_i2s1>; - nvidia,audio-codec = <&wm8903>; - - nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; - nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(X, 1) GPIO_ACTIVE_HIGH>; - - clocks = <&tegra_car TEGRA20_CLK_PLL_A>, - <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA20_CLK_CDEV1>; - clock-names = "pll_a", "pll_a_out0", "mclk"; - }; -}; diff --git a/sys/gnu/dts/arm/tegra20-tamonten.dtsi b/sys/gnu/dts/arm/tegra20-tamonten.dtsi deleted file mode 100644 index 20137fc578b..00000000000 --- a/sys/gnu/dts/arm/tegra20-tamonten.dtsi +++ /dev/null @@ -1,534 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "tegra20.dtsi" - -/ { - model = "Avionic Design Tamonten SOM"; - compatible = "ad,tamonten", "nvidia,tegra20"; - - aliases { - rtc0 = "/i2c@7000d000/tps6586x@34"; - rtc1 = "/rtc@7000e000"; - serial0 = &uartd; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - reg = <0x00000000 0x20000000>; - }; - - host1x@50000000 { - hdmi@54280000 { - vdd-supply = <&hdmi_vdd_reg>; - pll-supply = <&hdmi_pll_reg>; - - nvidia,ddc-i2c-bus = <&hdmi_ddc>; - nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) - GPIO_ACTIVE_HIGH>; - }; - }; - - pinmux@70000014 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - ata { - nvidia,pins = "ata"; - nvidia,function = "ide"; - }; - atb { - nvidia,pins = "atb", "gma", "gme"; - nvidia,function = "sdio4"; - }; - atc { - nvidia,pins = "atc"; - nvidia,function = "nand"; - }; - atd { - nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu", - "spia", "spib", "spic"; - nvidia,function = "gmi"; - }; - cdev1 { - nvidia,pins = "cdev1"; - nvidia,function = "plla_out"; - }; - cdev2 { - nvidia,pins = "cdev2"; - nvidia,function = "pllp_out4"; - }; - crtp { - nvidia,pins = "crtp"; - nvidia,function = "crt"; - }; - csus { - nvidia,pins = "csus"; - nvidia,function = "vi_sensor_clk"; - }; - dap1 { - nvidia,pins = "dap1"; - nvidia,function = "dap1"; - }; - dap2 { - nvidia,pins = "dap2"; - nvidia,function = "dap2"; - }; - dap3 { - nvidia,pins = "dap3"; - nvidia,function = "dap3"; - }; - dap4 { - nvidia,pins = "dap4"; - nvidia,function = "dap4"; - }; - dta { - nvidia,pins = "dta", "dtd"; - nvidia,function = "sdio2"; - }; - dtb { - nvidia,pins = "dtb", "dtc", "dte"; - nvidia,function = "rsvd1"; - }; - dtf { - nvidia,pins = "dtf"; - nvidia,function = "i2c3"; - }; - gmc { - nvidia,pins = "gmc"; - nvidia,function = "uartd"; - }; - gpu7 { - nvidia,pins = "gpu7"; - nvidia,function = "rtck"; - }; - gpv { - nvidia,pins = "gpv", "slxa", "slxk"; - nvidia,function = "pcie"; - }; - hdint { - nvidia,pins = "hdint"; - nvidia,function = "hdmi"; - }; - i2cp { - nvidia,pins = "i2cp"; - nvidia,function = "i2cp"; - }; - irrx { - nvidia,pins = "irrx", "irtx"; - nvidia,function = "uarta"; - }; - kbca { - nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", - "kbce", "kbcf"; - nvidia,function = "kbc"; - }; - lcsn { - nvidia,pins = "lcsn", "ld0", "ld1", "ld2", - "ld3", "ld4", "ld5", "ld6", "ld7", - "ld8", "ld9", "ld10", "ld11", "ld12", - "ld13", "ld14", "ld15", "ld16", "ld17", - "ldc", "ldi", "lhp0", "lhp1", "lhp2", - "lhs", "lm0", "lm1", "lpp", "lpw0", - "lpw1", "lpw2", "lsc0", "lsc1", "lsck", - "lsda", "lsdi", "lspi", "lvp0", "lvp1", - "lvs"; - nvidia,function = "displaya"; - }; - owc { - nvidia,pins = "owc", "spdi", "spdo", "uac"; - nvidia,function = "rsvd2"; - }; - pmc { - nvidia,pins = "pmc"; - nvidia,function = "pwr_on"; - }; - rm { - nvidia,pins = "rm"; - nvidia,function = "i2c1"; - }; - sdb { - nvidia,pins = "sdb", "sdc", "sdd"; - nvidia,function = "pwm"; - }; - sdio1 { - nvidia,pins = "sdio1"; - nvidia,function = "sdio1"; - }; - slxc { - nvidia,pins = "slxc", "slxd"; - nvidia,function = "spdif"; - }; - spid { - nvidia,pins = "spid", "spie", "spif"; - nvidia,function = "spi1"; - }; - spig { - nvidia,pins = "spig", "spih"; - nvidia,function = "spi2_alt"; - }; - uaa { - nvidia,pins = "uaa", "uab", "uda"; - nvidia,function = "ulpi"; - }; - uad { - nvidia,pins = "uad"; - nvidia,function = "irda"; - }; - uca { - nvidia,pins = "uca", "ucb"; - nvidia,function = "uartc"; - }; - conf_ata { - nvidia,pins = "ata", "atb", "atc", "atd", "ate", - "cdev1", "cdev2", "dap1", "dtb", "gma", - "gmb", "gmc", "gmd", "gme", "gpu7", - "gpv", "i2cp", "pta", "rm", "slxa", - "slxk", "spia", "spib", "uac"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_ck32 { - nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", - "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; - nvidia,pull = ; - }; - conf_csus { - nvidia,pins = "csus", "spid", "spif"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_crtp { - nvidia,pins = "crtp", "dap2", "dap3", "dap4", - "dtc", "dte", "dtf", "gpu", "sdio1", - "slxc", "slxd", "spdi", "spdo", "spig", - "uda"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_ddc { - nvidia,pins = "ddc", "dta", "dtd", "kbca", - "kbcb", "kbcc", "kbcd", "kbce", "kbcf", - "sdc"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_hdint { - nvidia,pins = "hdint", "lcsn", "ldc", "lm1", - "lpw1", "lsc1", "lsck", "lsda", "lsdi", - "lvp0", "owc", "sdb"; - nvidia,tristate = ; - }; - conf_irrx { - nvidia,pins = "irrx", "irtx", "sdd", "spic", - "spie", "spih", "uaa", "uab", "uad", - "uca", "ucb"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_lc { - nvidia,pins = "lc", "ls"; - nvidia,pull = ; - }; - conf_ld0 { - nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", - "ld5", "ld6", "ld7", "ld8", "ld9", - "ld10", "ld11", "ld12", "ld13", "ld14", - "ld15", "ld16", "ld17", "ldi", "lhp0", - "lhp1", "lhp2", "lhs", "lm0", "lpp", - "lpw0", "lpw2", "lsc0", "lspi", "lvp1", - "lvs", "pmc"; - nvidia,tristate = ; - }; - conf_ld17_0 { - nvidia,pins = "ld17_0", "ld19_18", "ld21_20", - "ld23_22"; - nvidia,pull = ; - }; - }; - - state_i2cmux_ddc: pinmux_i2cmux_ddc { - ddc { - nvidia,pins = "ddc"; - nvidia,function = "i2c2"; - }; - pta { - nvidia,pins = "pta"; - nvidia,function = "rsvd4"; - }; - }; - - state_i2cmux_pta: pinmux_i2cmux_pta { - ddc { - nvidia,pins = "ddc"; - nvidia,function = "rsvd4"; - }; - pta { - nvidia,pins = "pta"; - nvidia,function = "i2c2"; - }; - }; - - state_i2cmux_idle: pinmux_i2cmux_idle { - ddc { - nvidia,pins = "ddc"; - nvidia,function = "rsvd4"; - }; - pta { - nvidia,pins = "pta"; - nvidia,function = "rsvd4"; - }; - }; - }; - - i2s@70002800 { - status = "okay"; - }; - - serial@70006300 { - status = "okay"; - }; - - i2c@7000c000 { - clock-frequency = <400000>; - status = "okay"; - }; - - i2c@7000c400 { - clock-frequency = <100000>; - status = "okay"; - }; - - i2cmux { - compatible = "i2c-mux-pinctrl"; - #address-cells = <1>; - #size-cells = <0>; - - i2c-parent = <&{/i2c@7000c400}>; - - pinctrl-names = "ddc", "pta", "idle"; - pinctrl-0 = <&state_i2cmux_ddc>; - pinctrl-1 = <&state_i2cmux_pta>; - pinctrl-2 = <&state_i2cmux_idle>; - - hdmi_ddc: i2c@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - i2c@7000d000 { - clock-frequency = <400000>; - status = "okay"; - - pmic: tps6586x@34 { - compatible = "ti,tps6586x"; - reg = <0x34>; - interrupts = ; - - ti,system-power-controller; - - #gpio-cells = <2>; - gpio-controller; - - /* vdd_5v0_reg must be provided by the base board */ - sys-supply = <&vdd_5v0_reg>; - vin-sm0-supply = <&sys_reg>; - vin-sm1-supply = <&sys_reg>; - vin-sm2-supply = <&sys_reg>; - vinldo01-supply = <&sm2_reg>; - vinldo23-supply = <&sm2_reg>; - vinldo4-supply = <&sm2_reg>; - vinldo678-supply = <&sm2_reg>; - vinldo9-supply = <&sm2_reg>; - - regulators { - sys_reg: sys { - regulator-name = "vdd_sys"; - regulator-always-on; - }; - - sm0 { - regulator-name = "vdd_sys_sm0,vdd_core"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - sm1 { - regulator-name = "vdd_sys_sm1,vdd_cpu"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - sm2_reg: sm2 { - regulator-name = "vdd_sys_sm2,vin_ldo*"; - regulator-min-microvolt = <3700000>; - regulator-max-microvolt = <3700000>; - regulator-always-on; - }; - - pci_clk_reg: ldo0 { - regulator-name = "vdd_ldo0,vddio_pex_clk"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo1 { - regulator-name = "vdd_ldo1,avdd_pll*"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - ldo2 { - regulator-name = "vdd_ldo2,vdd_rtc"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - ldo3 { - regulator-name = "vdd_ldo3,avdd_usb*"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo4 { - regulator-name = "vdd_ldo4,avdd_osc,vddio_sys"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo5 { - regulator-name = "vdd_ldo5,vcore_mmc"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - ldo6 { - regulator-name = "vdd_ldo6,avdd_vdac"; - /* - * According to the Tegra 2 Automotive - * DataSheet, a typical value for this - * would be 2.8V, but the PMIC only - * supports 2.85V. - */ - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - hdmi_vdd_reg: ldo7 { - regulator-name = "vdd_ldo7,avdd_hdmi"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - hdmi_pll_reg: ldo8 { - regulator-name = "vdd_ldo8,avdd_hdmi_pll"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo9 { - regulator-name = "vdd_ldo9,vdd_ddr_rx,avdd_cam"; - /* - * According to the Tegra 2 Automotive - * DataSheet, a typical value for this - * would be 2.8V, but the PMIC only - * supports 2.85V. - */ - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - regulator-always-on; - }; - - ldo_rtc { - regulator-name = "vdd_rtc_out"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; - - temperature-sensor@4c { - compatible = "onnn,nct1008"; - reg = <0x4c>; - }; - }; - - pmc@7000e400 { - nvidia,invert-interrupt; - nvidia,suspend-mode = <1>; - nvidia,cpu-pwr-good-time = <5000>; - nvidia,cpu-pwr-off-time = <5000>; - nvidia,core-pwr-good-time = <3845 3845>; - nvidia,core-pwr-off-time = <3875>; - nvidia,sys-clock-req-active-high; - }; - - pcie@80003000 { - avdd-pex-supply = <&pci_vdd_reg>; - vdd-pex-supply = <&pci_vdd_reg>; - avdd-pex-pll-supply = <&pci_vdd_reg>; - avdd-plle-supply = <&pci_vdd_reg>; - vddio-pex-clk-supply = <&pci_clk_reg>; - }; - - usb@c5008000 { - status = "okay"; - }; - - usb-phy@c5008000 { - status = "okay"; - }; - - sdhci@c8000600 { - cd-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>; - bus-width = <4>; - status = "okay"; - }; - - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - regulators { - compatible = "simple-bus"; - - #address-cells = <1>; - #size-cells = <0>; - - pci_vdd_reg: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "vdd_1v05"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - gpio = <&pmic 2 0>; - enable-active-high; - }; - }; -}; diff --git a/sys/gnu/dts/arm/tegra20-tec.dts b/sys/gnu/dts/arm/tegra20-tec.dts deleted file mode 100644 index 4dec2773723..00000000000 --- a/sys/gnu/dts/arm/tegra20-tec.dts +++ /dev/null @@ -1,112 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "tegra20-tamonten.dtsi" - -/ { - model = "Avionic Design Tamonten Evaluation Carrier"; - compatible = "ad,tec", "ad,tamonten", "nvidia,tegra20"; - - host1x@50000000 { - hdmi@54280000 { - status = "okay"; - }; - }; - - i2c@7000c000 { - wm8903: wm8903@1a { - compatible = "wlf,wm8903"; - reg = <0x1a>; - interrupt-parent = <&gpio>; - interrupts = ; - - gpio-controller; - #gpio-cells = <2>; - - micdet-cfg = <0>; - micdet-delay = <100>; - gpio-cfg = <0xffffffff - 0xffffffff - 0 - 0xffffffff - 0xffffffff>; - }; - }; - - pcie@80003000 { - status = "okay"; - - pci@1,0 { - status = "okay"; - }; - }; - - sound { - compatible = "ad,tegra-audio-wm8903-tec", - "nvidia,tegra-audio-wm8903"; - nvidia,model = "Avionic Design TEC"; - - nvidia,audio-routing = - "Headphone Jack", "HPOUTR", - "Headphone Jack", "HPOUTL", - "Int Spk", "ROP", - "Int Spk", "RON", - "Int Spk", "LOP", - "Int Spk", "LON", - "Mic Jack", "MICBIAS", - "IN1L", "Mic Jack"; - - nvidia,i2s-controller = <&tegra_i2s1>; - nvidia,audio-codec = <&wm8903>; - - nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; - nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) - GPIO_ACTIVE_HIGH>; - - clocks = <&tegra_car TEGRA20_CLK_PLL_A>, - <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA20_CLK_CDEV1>; - clock-names = "pll_a", "pll_a_out0", "mclk"; - }; - - regulators { - vcc_24v_reg: regulator@100 { - compatible = "regulator-fixed"; - reg = <100>; - regulator-name = "vcc_24v"; - regulator-min-microvolt = <24000000>; - regulator-max-microvolt = <24000000>; - regulator-always-on; - }; - - vdd_5v0_reg: regulator@101 { - compatible = "regulator-fixed"; - reg = <101>; - regulator-name = "vdd_5v0"; - vin-supply = <&vcc_24v_reg>; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - vdd_3v3_reg: regulator@102 { - compatible = "regulator-fixed"; - reg = <102>; - regulator-name = "vdd_3v3"; - vin-supply = <&vcc_24v_reg>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_1v8_reg: regulator@103 { - compatible = "regulator-fixed"; - reg = <103>; - regulator-name = "vdd_1v8"; - vin-supply = <&vdd_3v3_reg>; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - }; -}; diff --git a/sys/gnu/dts/arm/tegra20-trimslice.dts b/sys/gnu/dts/arm/tegra20-trimslice.dts deleted file mode 100644 index 8debd3d3c20..00000000000 --- a/sys/gnu/dts/arm/tegra20-trimslice.dts +++ /dev/null @@ -1,485 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include -#include "tegra20.dtsi" -#include "tegra20-cpu-opp.dtsi" - -/ { - model = "Compulab TrimSlice board"; - compatible = "compulab,trimslice", "nvidia,tegra20"; - - aliases { - rtc0 = "/i2c@7000c500/rtc@56"; - rtc1 = "/rtc@7000e000"; - serial0 = &uarta; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - reg = <0x00000000 0x40000000>; - }; - - host1x@50000000 { - hdmi@54280000 { - status = "okay"; - - vdd-supply = <&hdmi_vdd_reg>; - pll-supply = <&hdmi_pll_reg>; - - nvidia,ddc-i2c-bus = <&hdmi_ddc>; - nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) - GPIO_ACTIVE_HIGH>; - }; - }; - - pinmux@70000014 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - ata { - nvidia,pins = "ata"; - nvidia,function = "ide"; - }; - atb { - nvidia,pins = "atb", "gma"; - nvidia,function = "sdio4"; - }; - atc { - nvidia,pins = "atc", "gmb"; - nvidia,function = "nand"; - }; - atd { - nvidia,pins = "atd", "ate", "gme", "pta"; - nvidia,function = "gmi"; - }; - cdev1 { - nvidia,pins = "cdev1"; - nvidia,function = "plla_out"; - }; - cdev2 { - nvidia,pins = "cdev2"; - nvidia,function = "pllp_out4"; - }; - crtp { - nvidia,pins = "crtp"; - nvidia,function = "crt"; - }; - csus { - nvidia,pins = "csus"; - nvidia,function = "vi_sensor_clk"; - }; - dap1 { - nvidia,pins = "dap1"; - nvidia,function = "dap1"; - }; - dap2 { - nvidia,pins = "dap2"; - nvidia,function = "dap2"; - }; - dap3 { - nvidia,pins = "dap3"; - nvidia,function = "dap3"; - }; - dap4 { - nvidia,pins = "dap4"; - nvidia,function = "dap4"; - }; - ddc { - nvidia,pins = "ddc"; - nvidia,function = "i2c2"; - }; - dta { - nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte"; - nvidia,function = "vi"; - }; - dtf { - nvidia,pins = "dtf"; - nvidia,function = "i2c3"; - }; - gmc { - nvidia,pins = "gmc", "gmd"; - nvidia,function = "sflash"; - }; - gpu { - nvidia,pins = "gpu"; - nvidia,function = "uarta"; - }; - gpu7 { - nvidia,pins = "gpu7"; - nvidia,function = "rtck"; - }; - gpv { - nvidia,pins = "gpv", "slxa", "slxk"; - nvidia,function = "pcie"; - }; - hdint { - nvidia,pins = "hdint"; - nvidia,function = "hdmi"; - }; - i2cp { - nvidia,pins = "i2cp"; - nvidia,function = "i2cp"; - }; - irrx { - nvidia,pins = "irrx", "irtx"; - nvidia,function = "uartb"; - }; - kbca { - nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", - "kbce", "kbcf"; - nvidia,function = "kbc"; - }; - lcsn { - nvidia,pins = "lcsn", "ld0", "ld1", "ld2", - "ld3", "ld4", "ld5", "ld6", "ld7", - "ld8", "ld9", "ld10", "ld11", "ld12", - "ld13", "ld14", "ld15", "ld16", "ld17", - "ldc", "ldi", "lhp0", "lhp1", "lhp2", - "lhs", "lm0", "lm1", "lpp", "lpw0", - "lpw1", "lpw2", "lsc0", "lsc1", "lsck", - "lsda", "lsdi", "lspi", "lvp0", "lvp1", - "lvs"; - nvidia,function = "displaya"; - }; - owc { - nvidia,pins = "owc", "uac"; - nvidia,function = "rsvd2"; - }; - pmc { - nvidia,pins = "pmc"; - nvidia,function = "pwr_on"; - }; - rm { - nvidia,pins = "rm"; - nvidia,function = "i2c1"; - }; - sdb { - nvidia,pins = "sdb", "sdc", "sdd"; - nvidia,function = "pwm"; - }; - sdio1 { - nvidia,pins = "sdio1"; - nvidia,function = "sdio1"; - }; - slxc { - nvidia,pins = "slxc", "slxd"; - nvidia,function = "sdio3"; - }; - spdi { - nvidia,pins = "spdi", "spdo"; - nvidia,function = "spdif"; - }; - spia { - nvidia,pins = "spia", "spib", "spic"; - nvidia,function = "spi2"; - }; - spid { - nvidia,pins = "spid", "spie", "spif"; - nvidia,function = "spi1"; - }; - spig { - nvidia,pins = "spig", "spih"; - nvidia,function = "spi2_alt"; - }; - uaa { - nvidia,pins = "uaa", "uab", "uda"; - nvidia,function = "ulpi"; - }; - uad { - nvidia,pins = "uad"; - nvidia,function = "irda"; - }; - uca { - nvidia,pins = "uca", "ucb"; - nvidia,function = "uartc"; - }; - conf_ata { - nvidia,pins = "ata", "atc", "atd", "ate", - "crtp", "dap2", "dap3", "dap4", "dta", - "dtb", "dtc", "dtd", "dte", "gmb", - "gme", "i2cp", "pta", "slxc", "slxd", - "spdi", "spdo", "uda"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_atb { - nvidia,pins = "atb", "cdev1", "cdev2", "dap1", - "gma", "gmc", "gmd", "gpu", "gpu7", - "gpv", "sdio1", "slxa", "slxk", "uac"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_ck32 { - nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", - "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; - nvidia,pull = ; - }; - conf_csus { - nvidia,pins = "csus", "spia", "spib", - "spid", "spif"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_ddc { - nvidia,pins = "ddc", "dtf", "rm", "sdc", "sdd"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_hdint { - nvidia,pins = "hdint", "lcsn", "ldc", "lm1", - "lpw1", "lsc1", "lsck", "lsda", "lsdi", - "lvp0", "pmc"; - nvidia,tristate = ; - }; - conf_irrx { - nvidia,pins = "irrx", "irtx", "kbca", "kbcb", - "kbcc", "kbcd", "kbce", "kbcf", "owc", - "spic", "spie", "spig", "spih", "uaa", - "uab", "uad", "uca", "ucb"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_lc { - nvidia,pins = "lc", "ls"; - nvidia,pull = ; - }; - conf_ld0 { - nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", - "ld5", "ld6", "ld7", "ld8", "ld9", - "ld10", "ld11", "ld12", "ld13", "ld14", - "ld15", "ld16", "ld17", "ldi", "lhp0", - "lhp1", "lhp2", "lhs", "lm0", "lpp", - "lpw0", "lpw2", "lsc0", "lspi", "lvp1", - "lvs", "sdb"; - nvidia,tristate = ; - }; - conf_ld17_0 { - nvidia,pins = "ld17_0", "ld19_18", "ld21_20", - "ld23_22"; - nvidia,pull = ; - }; - conf_spif { - nvidia,pins = "spif"; - nvidia,pull = ; - nvidia,tristate = ; - }; - }; - }; - - i2s@70002800 { - status = "okay"; - }; - - serial@70006000 { - status = "okay"; - }; - - dvi_ddc: i2c@7000c000 { - status = "okay"; - clock-frequency = <100000>; - }; - - spi@7000c380 { - status = "okay"; - spi-max-frequency = <48000000>; - spi-flash@0 { - compatible = "winbond,w25q80bl", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <48000000>; - }; - }; - - hdmi_ddc: i2c@7000c400 { - status = "okay"; - clock-frequency = <100000>; - }; - - i2c@7000c500 { - status = "okay"; - clock-frequency = <400000>; - - codec: codec@1a { - compatible = "ti,tlv320aic23"; - reg = <0x1a>; - }; - - rtc@56 { - compatible = "emmicro,em3027"; - reg = <0x56>; - }; - }; - - pmc@7000e400 { - nvidia,suspend-mode = <1>; - nvidia,cpu-pwr-good-time = <5000>; - nvidia,cpu-pwr-off-time = <5000>; - nvidia,core-pwr-good-time = <3845 3845>; - nvidia,core-pwr-off-time = <3875>; - nvidia,sys-clock-req-active-high; - }; - - pcie@80003000 { - status = "okay"; - - avdd-pex-supply = <&pci_vdd_reg>; - vdd-pex-supply = <&pci_vdd_reg>; - avdd-pex-pll-supply = <&pci_vdd_reg>; - avdd-plle-supply = <&pci_vdd_reg>; - vddio-pex-clk-supply = <&pci_clk_reg>; - - pci@1,0 { - status = "okay"; - }; - }; - - usb@c5000000 { - status = "okay"; - }; - - usb-phy@c5000000 { - status = "okay"; - vbus-supply = <&vbus_reg>; - }; - - usb@c5004000 { - status = "okay"; - nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0) - GPIO_ACTIVE_LOW>; - }; - - usb-phy@c5004000 { - status = "okay"; - nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0) - GPIO_ACTIVE_LOW>; - }; - - usb@c5008000 { - status = "okay"; - }; - - usb-phy@c5008000 { - status = "okay"; - }; - - sdhci@c8000000 { - status = "okay"; - broken-cd; - bus-width = <4>; - }; - - sdhci@c8000600 { - status = "okay"; - cd-gpios = <&gpio TEGRA_GPIO(P, 1) GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>; - bus-width = <4>; - }; - - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - power { - label = "Power"; - gpios = <&gpio TEGRA_GPIO(X, 6) GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - }; - - poweroff { - compatible = "gpio-poweroff"; - gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - hdmi_vdd_reg: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "avdd_hdmi"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - hdmi_pll_reg: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "avdd_hdmi_pll"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vbus_reg: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "usb1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(V, 2) 0>; - regulator-always-on; - regulator-boot-on; - }; - - pci_clk_reg: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "pci_clk"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - pci_vdd_reg: regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "pci_vdd"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - regulator-always-on; - }; - }; - - sound { - compatible = "nvidia,tegra-audio-trimslice"; - nvidia,i2s-controller = <&tegra_i2s1>; - nvidia,audio-codec = <&codec>; - - clocks = <&tegra_car TEGRA20_CLK_PLL_A>, - <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA20_CLK_CDEV1>; - clock-names = "pll_a", "pll_a_out0", "mclk"; - }; - - cpus { - cpu0: cpu@0 { - operating-points-v2 = <&cpu0_opp_table>; - }; - - cpu@1 { - operating-points-v2 = <&cpu0_opp_table>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/tegra20-ventana.dts b/sys/gnu/dts/arm/tegra20-ventana.dts deleted file mode 100644 index f44551e2d9d..00000000000 --- a/sys/gnu/dts/arm/tegra20-ventana.dts +++ /dev/null @@ -1,707 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include -#include "tegra20.dtsi" - -/ { - model = "NVIDIA Tegra20 Ventana evaluation board"; - compatible = "nvidia,ventana", "nvidia,tegra20"; - - aliases { - rtc0 = "/i2c@7000d000/tps6586x@34"; - rtc1 = "/rtc@7000e000"; - serial0 = &uartd; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - reg = <0x00000000 0x40000000>; - }; - - host1x@50000000 { - dc@54200000 { - rgb { - status = "okay"; - - nvidia,panel = <&panel>; - }; - }; - - hdmi@54280000 { - status = "okay"; - - vdd-supply = <&hdmi_vdd_reg>; - pll-supply = <&hdmi_pll_reg>; - - nvidia,ddc-i2c-bus = <&hdmi_ddc>; - nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) - GPIO_ACTIVE_HIGH>; - }; - }; - - pinmux@70000014 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - ata { - nvidia,pins = "ata"; - nvidia,function = "ide"; - }; - atb { - nvidia,pins = "atb", "gma", "gme"; - nvidia,function = "sdio4"; - }; - atc { - nvidia,pins = "atc"; - nvidia,function = "nand"; - }; - atd { - nvidia,pins = "atd", "ate", "gmb", "spia", - "spib", "spic"; - nvidia,function = "gmi"; - }; - cdev1 { - nvidia,pins = "cdev1"; - nvidia,function = "plla_out"; - }; - cdev2 { - nvidia,pins = "cdev2"; - nvidia,function = "pllp_out4"; - }; - crtp { - nvidia,pins = "crtp", "lm1"; - nvidia,function = "crt"; - }; - csus { - nvidia,pins = "csus"; - nvidia,function = "vi_sensor_clk"; - }; - dap1 { - nvidia,pins = "dap1"; - nvidia,function = "dap1"; - }; - dap2 { - nvidia,pins = "dap2"; - nvidia,function = "dap2"; - }; - dap3 { - nvidia,pins = "dap3"; - nvidia,function = "dap3"; - }; - dap4 { - nvidia,pins = "dap4"; - nvidia,function = "dap4"; - }; - dta { - nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte"; - nvidia,function = "vi"; - }; - dtf { - nvidia,pins = "dtf"; - nvidia,function = "i2c3"; - }; - gmc { - nvidia,pins = "gmc"; - nvidia,function = "uartd"; - }; - gmd { - nvidia,pins = "gmd"; - nvidia,function = "sflash"; - }; - gpu { - nvidia,pins = "gpu"; - nvidia,function = "pwm"; - }; - gpu7 { - nvidia,pins = "gpu7"; - nvidia,function = "rtck"; - }; - gpv { - nvidia,pins = "gpv", "slxa", "slxk"; - nvidia,function = "pcie"; - }; - hdint { - nvidia,pins = "hdint"; - nvidia,function = "hdmi"; - }; - i2cp { - nvidia,pins = "i2cp"; - nvidia,function = "i2cp"; - }; - irrx { - nvidia,pins = "irrx", "irtx"; - nvidia,function = "uartb"; - }; - kbca { - nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", - "kbce", "kbcf"; - nvidia,function = "kbc"; - }; - lcsn { - nvidia,pins = "lcsn", "ldc", "lm0", "lpw1", - "lsdi", "lvp0"; - nvidia,function = "rsvd4"; - }; - ld0 { - nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", - "ld5", "ld6", "ld7", "ld8", "ld9", - "ld10", "ld11", "ld12", "ld13", "ld14", - "ld15", "ld16", "ld17", "ldi", "lhp0", - "lhp1", "lhp2", "lhs", "lpp", "lpw0", - "lpw2", "lsc0", "lsc1", "lsck", "lsda", - "lspi", "lvp1", "lvs"; - nvidia,function = "displaya"; - }; - owc { - nvidia,pins = "owc", "spdi", "spdo", "uac"; - nvidia,function = "rsvd2"; - }; - pmc { - nvidia,pins = "pmc"; - nvidia,function = "pwr_on"; - }; - rm { - nvidia,pins = "rm"; - nvidia,function = "i2c1"; - }; - sdb { - nvidia,pins = "sdb", "sdc", "sdd", "slxc"; - nvidia,function = "sdio3"; - }; - sdio1 { - nvidia,pins = "sdio1"; - nvidia,function = "sdio1"; - }; - slxd { - nvidia,pins = "slxd"; - nvidia,function = "spdif"; - }; - spid { - nvidia,pins = "spid", "spie", "spif"; - nvidia,function = "spi1"; - }; - spig { - nvidia,pins = "spig", "spih"; - nvidia,function = "spi2_alt"; - }; - uaa { - nvidia,pins = "uaa", "uab", "uda"; - nvidia,function = "ulpi"; - }; - uad { - nvidia,pins = "uad"; - nvidia,function = "irda"; - }; - uca { - nvidia,pins = "uca", "ucb"; - nvidia,function = "uartc"; - }; - conf_ata { - nvidia,pins = "ata", "atb", "atc", "atd", - "cdev1", "cdev2", "dap1", "dap2", - "dap4", "ddc", "dtf", "gma", "gmc", - "gme", "gpu", "gpu7", "i2cp", "irrx", - "irtx", "pta", "rm", "sdc", "sdd", - "slxc", "slxd", "slxk", "spdi", "spdo", - "uac", "uad", "uca", "ucb", "uda"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_ate { - nvidia,pins = "ate", "csus", "dap3", "gmd", - "gpv", "owc", "spia", "spib", "spic", - "spid", "spie", "spig"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_ck32 { - nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", - "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; - nvidia,pull = ; - }; - conf_crtp { - nvidia,pins = "crtp", "gmb", "slxa", "spih"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_dta { - nvidia,pins = "dta", "dtb", "dtc", "dtd"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_dte { - nvidia,pins = "dte", "spif"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_hdint { - nvidia,pins = "hdint", "lcsn", "ldc", "lm1", - "lpw1", "lsck", "lsda", "lsdi", "lvp0"; - nvidia,tristate = ; - }; - conf_kbca { - nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", - "kbce", "kbcf", "sdio1", "uaa", "uab"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_lc { - nvidia,pins = "lc", "ls"; - nvidia,pull = ; - }; - conf_ld0 { - nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", - "ld5", "ld6", "ld7", "ld8", "ld9", - "ld10", "ld11", "ld12", "ld13", "ld14", - "ld15", "ld16", "ld17", "ldi", "lhp0", - "lhp1", "lhp2", "lhs", "lm0", "lpp", - "lpw0", "lpw2", "lsc0", "lsc1", "lspi", - "lvp1", "lvs", "pmc", "sdb"; - nvidia,tristate = ; - }; - conf_ld17_0 { - nvidia,pins = "ld17_0", "ld19_18", "ld21_20", - "ld23_22"; - nvidia,pull = ; - }; - drive_sdio1 { - nvidia,pins = "drive_sdio1"; - nvidia,high-speed-mode = ; - nvidia,schmitt = ; - nvidia,low-power-mode = ; - nvidia,pull-down-strength = <31>; - nvidia,pull-up-strength = <31>; - nvidia,slew-rate-rising = ; - nvidia,slew-rate-falling = ; - }; - }; - - state_i2cmux_ddc: pinmux_i2cmux_ddc { - ddc { - nvidia,pins = "ddc"; - nvidia,function = "i2c2"; - }; - pta { - nvidia,pins = "pta"; - nvidia,function = "rsvd4"; - }; - }; - - state_i2cmux_pta: pinmux_i2cmux_pta { - ddc { - nvidia,pins = "ddc"; - nvidia,function = "rsvd4"; - }; - pta { - nvidia,pins = "pta"; - nvidia,function = "i2c2"; - }; - }; - - state_i2cmux_idle: pinmux_i2cmux_idle { - ddc { - nvidia,pins = "ddc"; - nvidia,function = "rsvd4"; - }; - pta { - nvidia,pins = "pta"; - nvidia,function = "rsvd4"; - }; - }; - }; - - i2s@70002800 { - status = "okay"; - }; - - serial@70006300 { - status = "okay"; - }; - - pwm: pwm@7000a000 { - status = "okay"; - }; - - i2c@7000c000 { - status = "okay"; - clock-frequency = <400000>; - - wm8903: wm8903@1a { - compatible = "wlf,wm8903"; - reg = <0x1a>; - interrupt-parent = <&gpio>; - interrupts = ; - - gpio-controller; - #gpio-cells = <2>; - - micdet-cfg = <0>; - micdet-delay = <100>; - gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>; - }; - - /* ALS and proximity sensor */ - isl29018@44 { - compatible = "isil,isl29018"; - reg = <0x44>; - interrupt-parent = <&gpio>; - interrupts = ; - }; - }; - - i2c@7000c400 { - status = "okay"; - clock-frequency = <100000>; - }; - - i2cmux { - compatible = "i2c-mux-pinctrl"; - #address-cells = <1>; - #size-cells = <0>; - - i2c-parent = <&{/i2c@7000c400}>; - - pinctrl-names = "ddc", "pta", "idle"; - pinctrl-0 = <&state_i2cmux_ddc>; - pinctrl-1 = <&state_i2cmux_pta>; - pinctrl-2 = <&state_i2cmux_idle>; - - hdmi_ddc: i2c@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - }; - - lvds_ddc: i2c@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - i2c@7000c500 { - status = "okay"; - clock-frequency = <400000>; - }; - - i2c@7000d000 { - status = "okay"; - clock-frequency = <400000>; - - pmic: tps6586x@34 { - compatible = "ti,tps6586x"; - reg = <0x34>; - interrupts = ; - - ti,system-power-controller; - - #gpio-cells = <2>; - gpio-controller; - - sys-supply = <&vdd_5v0_reg>; - vin-sm0-supply = <&sys_reg>; - vin-sm1-supply = <&sys_reg>; - vin-sm2-supply = <&sys_reg>; - vinldo01-supply = <&sm2_reg>; - vinldo23-supply = <&sm2_reg>; - vinldo4-supply = <&sm2_reg>; - vinldo678-supply = <&sm2_reg>; - vinldo9-supply = <&sm2_reg>; - - regulators { - sys_reg: sys { - regulator-name = "vdd_sys"; - regulator-always-on; - }; - - sm0 { - regulator-name = "vdd_sm0,vdd_core"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - sm1 { - regulator-name = "vdd_sm1,vdd_cpu"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - sm2_reg: sm2 { - regulator-name = "vdd_sm2,vin_ldo*"; - regulator-min-microvolt = <3700000>; - regulator-max-microvolt = <3700000>; - regulator-always-on; - }; - - /* LDO0 is not connected to anything */ - - ldo1 { - regulator-name = "vdd_ldo1,avdd_pll*"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - ldo2 { - regulator-name = "vdd_ldo2,vdd_rtc"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - ldo3 { - regulator-name = "vdd_ldo3,avdd_usb*"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo4 { - regulator-name = "vdd_ldo4,avdd_osc,vddio_sys"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo5 { - regulator-name = "vdd_ldo5,vcore_mmc"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - regulator-always-on; - }; - - ldo6 { - regulator-name = "vdd_ldo6,avdd_vdac"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - hdmi_vdd_reg: ldo7 { - regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - hdmi_pll_reg: ldo8 { - regulator-name = "vdd_ldo8,avdd_hdmi_pll"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo9 { - regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - regulator-always-on; - }; - - ldo_rtc { - regulator-name = "vdd_rtc_out,vdd_cell"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; - - temperature-sensor@4c { - compatible = "onnn,nct1008"; - reg = <0x4c>; - }; - }; - - pmc@7000e400 { - nvidia,invert-interrupt; - nvidia,suspend-mode = <1>; - nvidia,cpu-pwr-good-time = <2000>; - nvidia,cpu-pwr-off-time = <100>; - nvidia,core-pwr-good-time = <3845 3845>; - nvidia,core-pwr-off-time = <458>; - nvidia,sys-clock-req-active-high; - }; - - usb@c5000000 { - status = "okay"; - }; - - usb-phy@c5000000 { - status = "okay"; - }; - - usb@c5004000 { - status = "okay"; - nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) - GPIO_ACTIVE_LOW>; - }; - - usb-phy@c5004000 { - status = "okay"; - nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) - GPIO_ACTIVE_LOW>; - }; - - usb@c5008000 { - status = "okay"; - }; - - usb-phy@c5008000 { - status = "okay"; - }; - - sdhci@c8000000 { - status = "okay"; - power-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; - bus-width = <4>; - keep-power-in-suspend; - }; - - sdhci@c8000400 { - status = "okay"; - cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; - power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>; - bus-width = <4>; - }; - - sdhci@c8000600 { - status = "okay"; - bus-width = <8>; - non-removable; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - - enable-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>; - power-supply = <&vdd_bl_reg>; - pwms = <&pwm 2 5000000>; - - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - }; - - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - power { - label = "Power"; - gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - }; - - panel: panel { - compatible = "chunghwa,claa101wa01a", "simple-panel"; - - power-supply = <&vdd_pnl_reg>; - enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>; - - backlight = <&backlight>; - ddc-i2c-bus = <&lvds_ddc>; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - vdd_5v0_reg: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "vdd_5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "vdd_1v5"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; - }; - - regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "vdd_1v2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vdd_pnl_reg: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "vdd_pnl"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vdd_bl_reg: regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "vdd_bl"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - }; - - sound { - compatible = "nvidia,tegra-audio-wm8903-ventana", - "nvidia,tegra-audio-wm8903"; - nvidia,model = "NVIDIA Tegra Ventana"; - - nvidia,audio-routing = - "Headphone Jack", "HPOUTR", - "Headphone Jack", "HPOUTL", - "Int Spk", "ROP", - "Int Spk", "RON", - "Int Spk", "LOP", - "Int Spk", "LON", - "Mic Jack", "MICBIAS", - "IN1L", "Mic Jack"; - - nvidia,i2s-controller = <&tegra_i2s1>; - nvidia,audio-codec = <&wm8903>; - - nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; - nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>; - nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(X, 0) - GPIO_ACTIVE_HIGH>; - nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 1) - GPIO_ACTIVE_HIGH>; - - clocks = <&tegra_car TEGRA20_CLK_PLL_A>, - <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA20_CLK_CDEV1>; - clock-names = "pll_a", "pll_a_out0", "mclk"; - }; -}; diff --git a/sys/gnu/dts/arm/tegra20-whistler.dts b/sys/gnu/dts/arm/tegra20-whistler.dts deleted file mode 100644 index 1e06f854c8b..00000000000 --- a/sys/gnu/dts/arm/tegra20-whistler.dts +++ /dev/null @@ -1,636 +0,0 @@ -/dts-v1/; - -#include -#include "tegra20.dtsi" - -/ { - model = "NVIDIA Tegra20 Whistler evaluation board"; - compatible = "nvidia,whistler", "nvidia,tegra20"; - - aliases { - rtc0 = "/i2c@7000d000/max8907@3c"; - rtc1 = "/rtc@7000e000"; - serial0 = &uarta; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - reg = <0x00000000 0x20000000>; - }; - - host1x@50000000 { - hdmi@54280000 { - status = "okay"; - - vdd-supply = <&hdmi_vdd_reg>; - pll-supply = <&hdmi_pll_reg>; - - nvidia,ddc-i2c-bus = <&hdmi_ddc>; - nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) - GPIO_ACTIVE_HIGH>; - }; - }; - - pinmux@70000014 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - ata { - nvidia,pins = "ata", "atb", "ate", "gma", "gmb", - "gmc", "gmd", "gpu"; - nvidia,function = "gmi"; - }; - atc { - nvidia,pins = "atc", "atd"; - nvidia,function = "sdio4"; - }; - cdev1 { - nvidia,pins = "cdev1"; - nvidia,function = "plla_out"; - }; - cdev2 { - nvidia,pins = "cdev2"; - nvidia,function = "osc"; - }; - crtp { - nvidia,pins = "crtp"; - nvidia,function = "crt"; - }; - csus { - nvidia,pins = "csus"; - nvidia,function = "vi_sensor_clk"; - }; - dap1 { - nvidia,pins = "dap1"; - nvidia,function = "dap1"; - }; - dap2 { - nvidia,pins = "dap2"; - nvidia,function = "dap2"; - }; - dap3 { - nvidia,pins = "dap3"; - nvidia,function = "dap3"; - }; - dap4 { - nvidia,pins = "dap4"; - nvidia,function = "dap4"; - }; - ddc { - nvidia,pins = "ddc"; - nvidia,function = "i2c2"; - }; - dta { - nvidia,pins = "dta", "dtb", "dtc", "dtd"; - nvidia,function = "vi"; - }; - dte { - nvidia,pins = "dte"; - nvidia,function = "rsvd1"; - }; - dtf { - nvidia,pins = "dtf"; - nvidia,function = "i2c3"; - }; - gme { - nvidia,pins = "gme"; - nvidia,function = "dap5"; - }; - gpu7 { - nvidia,pins = "gpu7"; - nvidia,function = "rtck"; - }; - gpv { - nvidia,pins = "gpv"; - nvidia,function = "pcie"; - }; - hdint { - nvidia,pins = "hdint", "pta"; - nvidia,function = "hdmi"; - }; - i2cp { - nvidia,pins = "i2cp"; - nvidia,function = "i2cp"; - }; - irrx { - nvidia,pins = "irrx", "irtx"; - nvidia,function = "uartb"; - }; - kbca { - nvidia,pins = "kbca", "kbcc", "kbce", "kbcf"; - nvidia,function = "kbc"; - }; - kbcb { - nvidia,pins = "kbcb", "kbcd"; - nvidia,function = "sdio2"; - }; - lcsn { - nvidia,pins = "lcsn", "lsck", "lsda", "lsdi", - "spia", "spib", "spic"; - nvidia,function = "spi3"; - }; - ld0 { - nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", - "ld5", "ld6", "ld7", "ld8", "ld9", - "ld10", "ld11", "ld12", "ld13", "ld14", - "ld15", "ld16", "ld17", "ldc", "ldi", - "lhp0", "lhp1", "lhp2", "lhs", "lm0", - "lm1", "lpp", "lpw0", "lpw1", "lpw2", - "lsc0", "lsc1", "lspi", "lvp0", "lvp1", - "lvs"; - nvidia,function = "displaya"; - }; - owc { - nvidia,pins = "owc", "uac"; - nvidia,function = "owr"; - }; - pmc { - nvidia,pins = "pmc"; - nvidia,function = "pwr_on"; - }; - rm { - nvidia,pins = "rm"; - nvidia,function = "i2c1"; - }; - sdb { - nvidia,pins = "sdb", "sdc", "sdd", "slxa", - "slxc", "slxd", "slxk"; - nvidia,function = "sdio3"; - }; - sdio1 { - nvidia,pins = "sdio1"; - nvidia,function = "sdio1"; - }; - spdi { - nvidia,pins = "spdi", "spdo"; - nvidia,function = "rsvd2"; - }; - spid { - nvidia,pins = "spid", "spie", "spig", "spih"; - nvidia,function = "spi2_alt"; - }; - spif { - nvidia,pins = "spif"; - nvidia,function = "spi2"; - }; - uaa { - nvidia,pins = "uaa", "uab"; - nvidia,function = "uarta"; - }; - uad { - nvidia,pins = "uad"; - nvidia,function = "irda"; - }; - uca { - nvidia,pins = "uca", "ucb"; - nvidia,function = "uartc"; - }; - uda { - nvidia,pins = "uda"; - nvidia,function = "spi1"; - }; - conf_ata { - nvidia,pins = "ata", "atb", "atc", "ddc", "gma", - "gmb", "gmc", "gmd", "irrx", "irtx", - "kbca", "kbcb", "kbcc", "kbcd", "kbce", - "kbcf", "sdc", "sdd", "spie", "spig", - "spih", "uaa", "uab", "uad", "uca", - "ucb"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_atd { - nvidia,pins = "atd", "ate", "cdev1", "csus", - "dap1", "dap2", "dap3", "dap4", "dte", - "dtf", "gpu", "gpu7", "gpv", "i2cp", - "rm", "sdio1", "slxa", "slxc", "slxd", - "slxk", "spdi", "spdo", "uac", "uda"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_cdev2 { - nvidia,pins = "cdev2", "spia", "spib"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_ck32 { - nvidia,pins = "ck32", "ddrc", "lc", "pmca", - "pmcb", "pmcc", "pmcd", "xm2c", - "xm2d"; - nvidia,pull = ; - }; - conf_crtp { - nvidia,pins = "crtp"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_dta { - nvidia,pins = "dta", "dtb", "dtc", "dtd", - "spid", "spif"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_gme { - nvidia,pins = "gme", "owc", "pta", "spic"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_ld17_0 { - nvidia,pins = "ld17_0", "ld19_18", "ld21_20", - "ld23_22"; - nvidia,pull = ; - }; - conf_ls { - nvidia,pins = "ls", "pmce"; - nvidia,pull = ; - }; - drive_dap1 { - nvidia,pins = "drive_dap1"; - nvidia,high-speed-mode = ; - nvidia,schmitt = ; - nvidia,low-power-mode = ; - nvidia,pull-down-strength = <0>; - nvidia,pull-up-strength = <0>; - nvidia,slew-rate-rising = ; - nvidia,slew-rate-falling = ; - }; - }; - }; - - i2s@70002800 { - status = "okay"; - }; - - serial@70006000 { - status = "okay"; - }; - - hdmi_ddc: i2c@7000c400 { - status = "okay"; - clock-frequency = <100000>; - }; - - i2c@7000d000 { - status = "okay"; - clock-frequency = <100000>; - - codec: codec@1a { - compatible = "wlf,wm8753"; - reg = <0x1a>; - }; - - tca6416: gpio@20 { - compatible = "ti,tca6416"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - }; - - max8907@3c { - compatible = "maxim,max8907"; - reg = <0x3c>; - interrupts = ; - - maxim,system-power-controller; - - mbatt-supply = <&usb0_vbus_reg>; - in-v1-supply = <&mbatt_reg>; - in-v2-supply = <&mbatt_reg>; - in-v3-supply = <&mbatt_reg>; - in1-supply = <&mbatt_reg>; - in2-supply = <&nvvdd_sv3_reg>; - in3-supply = <&mbatt_reg>; - in4-supply = <&mbatt_reg>; - in5-supply = <&mbatt_reg>; - in6-supply = <&mbatt_reg>; - in7-supply = <&mbatt_reg>; - in8-supply = <&mbatt_reg>; - in9-supply = <&mbatt_reg>; - in10-supply = <&mbatt_reg>; - in11-supply = <&mbatt_reg>; - in12-supply = <&mbatt_reg>; - in13-supply = <&mbatt_reg>; - in14-supply = <&mbatt_reg>; - in15-supply = <&mbatt_reg>; - in16-supply = <&mbatt_reg>; - in17-supply = <&nvvdd_sv3_reg>; - in18-supply = <&nvvdd_sv3_reg>; - in19-supply = <&mbatt_reg>; - in20-supply = <&mbatt_reg>; - - regulators { - mbatt_reg: mbatt { - regulator-name = "vbat_pmu"; - regulator-always-on; - }; - - sd1 { - regulator-name = "nvvdd_sv1,vdd_cpu_pmu"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - sd2 { - regulator-name = "nvvdd_sv2,vdd_core"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - nvvdd_sv3_reg: sd3 { - regulator-name = "nvvdd_sv3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo1 { - regulator-name = "nvvdd_ldo1,vddio_rx_ddr,vcore_acc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo2 { - regulator-name = "nvvdd_ldo2,avdd_pll*"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - ldo3 { - regulator-name = "nvvdd_ldo3,vcom_1v8b"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo4 { - regulator-name = "nvvdd_ldo4,avdd_usb*"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo5 { - regulator-name = "nvvdd_ldo5,vcore_mmc,avdd_lcd1,vddio_1wire"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - hdmi_pll_reg: ldo6 { - regulator-name = "nvvdd_ldo6,avdd_hdmi_pll"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo7 { - regulator-name = "nvvdd_ldo7,avddio_audio"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - ldo8 { - regulator-name = "nvvdd_ldo8,vcom_3v0,vcore_cmps"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - ldo9 { - regulator-name = "nvvdd_ldo9,avdd_cam*"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo10 { - regulator-name = "nvvdd_ldo10,avdd_usb_ic_3v0"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - }; - - hdmi_vdd_reg: ldo11 { - regulator-name = "nvvdd_ldo11,vddio_pex_clk,vcom_33,avdd_hdmi"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo12 { - regulator-name = "nvvdd_ldo12,vddio_sdio"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - ldo13 { - regulator-name = "nvvdd_ldo13,vcore_phtn,vdd_af"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo14 { - regulator-name = "nvvdd_ldo14,avdd_vdac"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo15 { - regulator-name = "nvvdd_ldo15,vcore_temp,vddio_hdcp"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo16 { - regulator-name = "nvvdd_ldo16,vdd_dbrtr"; - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - }; - - ldo17 { - regulator-name = "nvvdd_ldo17,vddio_mipi"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - ldo18 { - regulator-name = "nvvdd_ldo18,vddio_vi,vcore_cam*"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo19 { - regulator-name = "nvvdd_ldo19,avdd_lcd2,vddio_lx"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo20 { - regulator-name = "nvvdd_ldo20,vddio_ddr_1v2,vddio_hsic,vcom_1v2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - out5v { - regulator-name = "usb0_vbus_reg"; - }; - - out33v { - regulator-name = "pmu_out3v3"; - }; - - bbat { - regulator-name = "pmu_bbat"; - regulator-min-microvolt = <2400000>; - regulator-max-microvolt = <2400000>; - regulator-always-on; - }; - - sdby { - regulator-name = "vdd_aon"; - regulator-always-on; - }; - - vrtc { - regulator-name = "vrtc,pmu_vccadc"; - regulator-always-on; - }; - }; - }; - }; - - kbc@7000e200 { - status = "okay"; - nvidia,debounce-delay-ms = <20>; - nvidia,repeat-delay-ms = <160>; - nvidia,kbc-row-pins = <0 1 2>; - nvidia,kbc-col-pins = <16 17>; - wakeup-source; - linux,keymap = ; - }; - - pmc@7000e400 { - nvidia,invert-interrupt; - nvidia,suspend-mode = <1>; - nvidia,cpu-pwr-good-time = <2000>; - nvidia,cpu-pwr-off-time = <1000>; - nvidia,core-pwr-good-time = <0 3845>; - nvidia,core-pwr-off-time = <93727>; - nvidia,core-power-req-active-high; - nvidia,sys-clock-req-active-high; - nvidia,combined-power-req; - }; - - usb@c5000000 { - status = "okay"; - }; - - usb-phy@c5000000 { - status = "okay"; - vbus-supply = <&vbus1_reg>; - }; - - usb@c5008000 { - status = "okay"; - }; - - usb-phy@c5008000 { - status = "okay"; - vbus-supply = <&vbus3_reg>; - }; - - sdhci@c8000400 { - status = "okay"; - cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_HIGH>; - bus-width = <8>; - }; - - sdhci@c8000600 { - status = "okay"; - bus-width = <8>; - non-removable; - }; - - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - usb0_vbus_reg: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "usb0_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - vbus1_reg: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "vbus1"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&tca6416 0 0>; /* GPIO_PMU0 */ - regulator-always-on; - regulator-boot-on; - }; - - vbus3_reg: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "vbus3"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&tca6416 1 0>; /* GPIO_PMU1 */ - regulator-always-on; - regulator-boot-on; - }; - }; - - sound { - compatible = "nvidia,tegra-audio-wm8753-whistler", - "nvidia,tegra-audio-wm8753"; - nvidia,model = "NVIDIA Tegra Whistler"; - - nvidia,audio-routing = - "Headphone Jack", "LOUT1", - "Headphone Jack", "ROUT1", - "MIC2", "Mic Jack", - "MIC2N", "Mic Jack"; - - nvidia,i2s-controller = <&tegra_i2s1>; - nvidia,audio-codec = <&codec>; - - clocks = <&tegra_car TEGRA20_CLK_PLL_A>, - <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA20_CLK_CDEV1>; - clock-names = "pll_a", "pll_a_out0", "mclk"; - }; -}; diff --git a/sys/gnu/dts/arm/tegra20.dtsi b/sys/gnu/dts/arm/tegra20.dtsi deleted file mode 100644 index 9c58e7fcf5c..00000000000 --- a/sys/gnu/dts/arm/tegra20.dtsi +++ /dev/null @@ -1,872 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include -#include -#include -#include -#include - -/ { - compatible = "nvidia,tegra20"; - interrupt-parent = <&lic>; - #address-cells = <1>; - #size-cells = <1>; - - memory@0 { - device_type = "memory"; - reg = <0 0>; - }; - - iram@40000000 { - compatible = "mmio-sram"; - reg = <0x40000000 0x40000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x40000000 0x40000>; - - vde_pool: vde@400 { - reg = <0x400 0x3fc00>; - pool; - }; - }; - - host1x@50000000 { - compatible = "nvidia,tegra20-host1x", "simple-bus"; - reg = <0x50000000 0x00024000>; - interrupts = , /* syncpt */ - ; /* general */ - clocks = <&tegra_car TEGRA20_CLK_HOST1X>; - resets = <&tegra_car 28>; - reset-names = "host1x"; - - #address-cells = <1>; - #size-cells = <1>; - - ranges = <0x54000000 0x54000000 0x04000000>; - - mpe@54040000 { - compatible = "nvidia,tegra20-mpe"; - reg = <0x54040000 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA20_CLK_MPE>; - resets = <&tegra_car 60>; - reset-names = "mpe"; - }; - - vi@54080000 { - compatible = "nvidia,tegra20-vi"; - reg = <0x54080000 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA20_CLK_VI>; - resets = <&tegra_car 20>; - reset-names = "vi"; - }; - - epp@540c0000 { - compatible = "nvidia,tegra20-epp"; - reg = <0x540c0000 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA20_CLK_EPP>; - resets = <&tegra_car 19>; - reset-names = "epp"; - }; - - isp@54100000 { - compatible = "nvidia,tegra20-isp"; - reg = <0x54100000 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA20_CLK_ISP>; - resets = <&tegra_car 23>; - reset-names = "isp"; - }; - - gr2d@54140000 { - compatible = "nvidia,tegra20-gr2d"; - reg = <0x54140000 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA20_CLK_GR2D>; - resets = <&tegra_car 21>; - reset-names = "2d"; - }; - - gr3d@54180000 { - compatible = "nvidia,tegra20-gr3d"; - reg = <0x54180000 0x00040000>; - clocks = <&tegra_car TEGRA20_CLK_GR3D>; - resets = <&tegra_car 24>; - reset-names = "3d"; - }; - - dc@54200000 { - compatible = "nvidia,tegra20-dc"; - reg = <0x54200000 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA20_CLK_DISP1>, - <&tegra_car TEGRA20_CLK_PLL_P>; - clock-names = "dc", "parent"; - resets = <&tegra_car 27>; - reset-names = "dc"; - - nvidia,head = <0>; - - rgb { - status = "disabled"; - }; - }; - - dc@54240000 { - compatible = "nvidia,tegra20-dc"; - reg = <0x54240000 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA20_CLK_DISP2>, - <&tegra_car TEGRA20_CLK_PLL_P>; - clock-names = "dc", "parent"; - resets = <&tegra_car 26>; - reset-names = "dc"; - - nvidia,head = <1>; - - rgb { - status = "disabled"; - }; - }; - - hdmi@54280000 { - compatible = "nvidia,tegra20-hdmi"; - reg = <0x54280000 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA20_CLK_HDMI>, - <&tegra_car TEGRA20_CLK_PLL_D_OUT0>; - clock-names = "hdmi", "parent"; - resets = <&tegra_car 51>; - reset-names = "hdmi"; - status = "disabled"; - }; - - tvo@542c0000 { - compatible = "nvidia,tegra20-tvo"; - reg = <0x542c0000 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA20_CLK_TVO>; - status = "disabled"; - }; - - dsi@54300000 { - compatible = "nvidia,tegra20-dsi"; - reg = <0x54300000 0x00040000>; - clocks = <&tegra_car TEGRA20_CLK_DSI>; - resets = <&tegra_car 48>; - reset-names = "dsi"; - status = "disabled"; - }; - }; - - timer@50040600 { - compatible = "arm,cortex-a9-twd-timer"; - interrupt-parent = <&intc>; - reg = <0x50040600 0x20>; - interrupts = ; - clocks = <&tegra_car TEGRA20_CLK_TWD>; - }; - - intc: interrupt-controller@50041000 { - compatible = "arm,cortex-a9-gic"; - reg = <0x50041000 0x1000 - 0x50040100 0x0100>; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&intc>; - }; - - cache-controller@50043000 { - compatible = "arm,pl310-cache"; - reg = <0x50043000 0x1000>; - arm,data-latency = <5 5 2>; - arm,tag-latency = <4 4 2>; - cache-unified; - cache-level = <2>; - }; - - lic: interrupt-controller@60004000 { - compatible = "nvidia,tegra20-ictlr"; - reg = <0x60004000 0x100>, - <0x60004100 0x50>, - <0x60004200 0x50>, - <0x60004300 0x50>; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&intc>; - }; - - timer@60005000 { - compatible = "nvidia,tegra20-timer"; - reg = <0x60005000 0x60>; - interrupts = , - , - , - ; - clocks = <&tegra_car TEGRA20_CLK_TIMER>; - }; - - tegra_car: clock@60006000 { - compatible = "nvidia,tegra20-car"; - reg = <0x60006000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - flow-controller@60007000 { - compatible = "nvidia,tegra20-flowctrl"; - reg = <0x60007000 0x1000>; - }; - - apbdma: dma@6000a000 { - compatible = "nvidia,tegra20-apbdma"; - reg = <0x6000a000 0x1200>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - clocks = <&tegra_car TEGRA20_CLK_APBDMA>; - resets = <&tegra_car 34>; - reset-names = "dma"; - #dma-cells = <1>; - }; - - ahb@6000c000 { - compatible = "nvidia,tegra20-ahb"; - reg = <0x6000c000 0x110>; /* AHB Arbitration + Gizmo Controller */ - }; - - gpio: gpio@6000d000 { - compatible = "nvidia,tegra20-gpio"; - reg = <0x6000d000 0x1000>; - interrupts = , - , - , - , - , - , - ; - #gpio-cells = <2>; - gpio-controller; - #interrupt-cells = <2>; - interrupt-controller; - /* - gpio-ranges = <&pinmux 0 0 224>; - */ - }; - - vde@6001a000 { - compatible = "nvidia,tegra20-vde"; - reg = <0x6001a000 0x1000 /* Syntax Engine */ - 0x6001b000 0x1000 /* Video Bitstream Engine */ - 0x6001c000 0x100 /* Macroblock Engine */ - 0x6001c200 0x100 /* Post-processing Engine */ - 0x6001c400 0x100 /* Motion Compensation Engine */ - 0x6001c600 0x100 /* Transform Engine */ - 0x6001c800 0x100 /* Pixel prediction block */ - 0x6001ca00 0x100 /* Video DMA */ - 0x6001d800 0x300>; /* Video frame controls */ - reg-names = "sxe", "bsev", "mbe", "ppe", "mce", - "tfe", "ppb", "vdma", "frameid"; - iram = <&vde_pool>; /* IRAM region */ - interrupts = , /* Sync token interrupt */ - , /* BSE-V interrupt */ - ; /* SXE interrupt */ - interrupt-names = "sync-token", "bsev", "sxe"; - clocks = <&tegra_car TEGRA20_CLK_VDE>; - reset-names = "vde", "mc"; - resets = <&tegra_car 61>, <&mc TEGRA20_MC_RESET_VDE>; - }; - - apbmisc@70000800 { - compatible = "nvidia,tegra20-apbmisc"; - reg = <0x70000800 0x64 /* Chip revision */ - 0x70000008 0x04>; /* Strapping options */ - }; - - pinmux: pinmux@70000014 { - compatible = "nvidia,tegra20-pinmux"; - reg = <0x70000014 0x10 /* Tri-state registers */ - 0x70000080 0x20 /* Mux registers */ - 0x700000a0 0x14 /* Pull-up/down registers */ - 0x70000868 0xa8>; /* Pad control registers */ - }; - - das@70000c00 { - compatible = "nvidia,tegra20-das"; - reg = <0x70000c00 0x80>; - }; - - tegra_ac97: ac97@70002000 { - compatible = "nvidia,tegra20-ac97"; - reg = <0x70002000 0x200>; - interrupts = ; - clocks = <&tegra_car TEGRA20_CLK_AC97>; - resets = <&tegra_car 3>; - reset-names = "ac97"; - dmas = <&apbdma 12>, <&apbdma 12>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - tegra_i2s1: i2s@70002800 { - compatible = "nvidia,tegra20-i2s"; - reg = <0x70002800 0x200>; - interrupts = ; - clocks = <&tegra_car TEGRA20_CLK_I2S1>; - resets = <&tegra_car 11>; - reset-names = "i2s"; - dmas = <&apbdma 2>, <&apbdma 2>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - tegra_i2s2: i2s@70002a00 { - compatible = "nvidia,tegra20-i2s"; - reg = <0x70002a00 0x200>; - interrupts = ; - clocks = <&tegra_car TEGRA20_CLK_I2S2>; - resets = <&tegra_car 18>; - reset-names = "i2s"; - dmas = <&apbdma 1>, <&apbdma 1>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - /* - * There are two serial driver i.e. 8250 based simple serial - * driver and APB DMA based serial driver for higher baudrate - * and performace. To enable the 8250 based driver, the compatible - * is "nvidia,tegra20-uart" and to enable the APB DMA based serial - * driver, the compatible is "nvidia,tegra20-hsuart". - */ - uarta: serial@70006000 { - compatible = "nvidia,tegra20-uart"; - reg = <0x70006000 0x40>; - reg-shift = <2>; - interrupts = ; - clocks = <&tegra_car TEGRA20_CLK_UARTA>; - resets = <&tegra_car 6>; - reset-names = "serial"; - dmas = <&apbdma 8>, <&apbdma 8>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uartb: serial@70006040 { - compatible = "nvidia,tegra20-uart"; - reg = <0x70006040 0x40>; - reg-shift = <2>; - interrupts = ; - clocks = <&tegra_car TEGRA20_CLK_UARTB>; - resets = <&tegra_car 7>; - reset-names = "serial"; - dmas = <&apbdma 9>, <&apbdma 9>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uartc: serial@70006200 { - compatible = "nvidia,tegra20-uart"; - reg = <0x70006200 0x100>; - reg-shift = <2>; - interrupts = ; - clocks = <&tegra_car TEGRA20_CLK_UARTC>; - resets = <&tegra_car 55>; - reset-names = "serial"; - dmas = <&apbdma 10>, <&apbdma 10>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uartd: serial@70006300 { - compatible = "nvidia,tegra20-uart"; - reg = <0x70006300 0x100>; - reg-shift = <2>; - interrupts = ; - clocks = <&tegra_car TEGRA20_CLK_UARTD>; - resets = <&tegra_car 65>; - reset-names = "serial"; - dmas = <&apbdma 19>, <&apbdma 19>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uarte: serial@70006400 { - compatible = "nvidia,tegra20-uart"; - reg = <0x70006400 0x100>; - reg-shift = <2>; - interrupts = ; - clocks = <&tegra_car TEGRA20_CLK_UARTE>; - resets = <&tegra_car 66>; - reset-names = "serial"; - dmas = <&apbdma 20>, <&apbdma 20>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - nand-controller@70008000 { - compatible = "nvidia,tegra20-nand"; - reg = <0x70008000 0x100>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clocks = <&tegra_car TEGRA20_CLK_NDFLASH>; - clock-names = "nand"; - resets = <&tegra_car 13>; - reset-names = "nand"; - assigned-clocks = <&tegra_car TEGRA20_CLK_NDFLASH>; - assigned-clock-rates = <150000000>; - status = "disabled"; - }; - - gmi@70009000 { - compatible = "nvidia,tegra20-gmi"; - reg = <0x70009000 0x1000>; - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0xd0000000 0xfffffff>; - clocks = <&tegra_car TEGRA20_CLK_NOR>; - clock-names = "gmi"; - resets = <&tegra_car 42>; - reset-names = "gmi"; - status = "disabled"; - }; - - pwm: pwm@7000a000 { - compatible = "nvidia,tegra20-pwm"; - reg = <0x7000a000 0x100>; - #pwm-cells = <2>; - clocks = <&tegra_car TEGRA20_CLK_PWM>; - resets = <&tegra_car 17>; - reset-names = "pwm"; - status = "disabled"; - }; - - rtc@7000e000 { - compatible = "nvidia,tegra20-rtc"; - reg = <0x7000e000 0x100>; - interrupts = ; - clocks = <&tegra_car TEGRA20_CLK_RTC>; - }; - - i2c@7000c000 { - compatible = "nvidia,tegra20-i2c"; - reg = <0x7000c000 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA20_CLK_I2C1>, - <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; - clock-names = "div-clk", "fast-clk"; - resets = <&tegra_car 12>; - reset-names = "i2c"; - dmas = <&apbdma 21>, <&apbdma 21>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi@7000c380 { - compatible = "nvidia,tegra20-sflash"; - reg = <0x7000c380 0x80>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA20_CLK_SPI>; - resets = <&tegra_car 43>; - reset-names = "spi"; - dmas = <&apbdma 11>, <&apbdma 11>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c@7000c400 { - compatible = "nvidia,tegra20-i2c"; - reg = <0x7000c400 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA20_CLK_I2C2>, - <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; - clock-names = "div-clk", "fast-clk"; - resets = <&tegra_car 54>; - reset-names = "i2c"; - dmas = <&apbdma 22>, <&apbdma 22>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c@7000c500 { - compatible = "nvidia,tegra20-i2c"; - reg = <0x7000c500 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA20_CLK_I2C3>, - <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; - clock-names = "div-clk", "fast-clk"; - resets = <&tegra_car 67>; - reset-names = "i2c"; - dmas = <&apbdma 23>, <&apbdma 23>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c@7000d000 { - compatible = "nvidia,tegra20-i2c-dvc"; - reg = <0x7000d000 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA20_CLK_DVC>, - <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; - clock-names = "div-clk", "fast-clk"; - resets = <&tegra_car 47>; - reset-names = "i2c"; - dmas = <&apbdma 24>, <&apbdma 24>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi@7000d400 { - compatible = "nvidia,tegra20-slink"; - reg = <0x7000d400 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA20_CLK_SBC1>; - resets = <&tegra_car 41>; - reset-names = "spi"; - dmas = <&apbdma 15>, <&apbdma 15>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi@7000d600 { - compatible = "nvidia,tegra20-slink"; - reg = <0x7000d600 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA20_CLK_SBC2>; - resets = <&tegra_car 44>; - reset-names = "spi"; - dmas = <&apbdma 16>, <&apbdma 16>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi@7000d800 { - compatible = "nvidia,tegra20-slink"; - reg = <0x7000d800 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA20_CLK_SBC3>; - resets = <&tegra_car 46>; - reset-names = "spi"; - dmas = <&apbdma 17>, <&apbdma 17>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi@7000da00 { - compatible = "nvidia,tegra20-slink"; - reg = <0x7000da00 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA20_CLK_SBC4>; - resets = <&tegra_car 68>; - reset-names = "spi"; - dmas = <&apbdma 18>, <&apbdma 18>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - kbc@7000e200 { - compatible = "nvidia,tegra20-kbc"; - reg = <0x7000e200 0x100>; - interrupts = ; - clocks = <&tegra_car TEGRA20_CLK_KBC>; - resets = <&tegra_car 36>; - reset-names = "kbc"; - status = "disabled"; - }; - - pmc@7000e400 { - compatible = "nvidia,tegra20-pmc"; - reg = <0x7000e400 0x400>; - clocks = <&tegra_car TEGRA20_CLK_PCLK>, <&clk32k_in>; - clock-names = "pclk", "clk32k_in"; - }; - - mc: memory-controller@7000f000 { - compatible = "nvidia,tegra20-mc-gart"; - reg = <0x7000f000 0x400 /* controller registers */ - 0x58000000 0x02000000>; /* GART aperture */ - clocks = <&tegra_car TEGRA20_CLK_MC>; - clock-names = "mc"; - interrupts = ; - #reset-cells = <1>; - #iommu-cells = <0>; - }; - - memory-controller@7000f400 { - compatible = "nvidia,tegra20-emc"; - reg = <0x7000f400 0x200>; - interrupts = ; - clocks = <&tegra_car TEGRA20_CLK_EMC>; - #address-cells = <1>; - #size-cells = <0>; - }; - - fuse@7000f800 { - compatible = "nvidia,tegra20-efuse"; - reg = <0x7000f800 0x400>; - clocks = <&tegra_car TEGRA20_CLK_FUSE>; - clock-names = "fuse"; - resets = <&tegra_car 39>; - reset-names = "fuse"; - }; - - pcie@80003000 { - compatible = "nvidia,tegra20-pcie"; - device_type = "pci"; - reg = <0x80003000 0x00000800 /* PADS registers */ - 0x80003800 0x00000200 /* AFI registers */ - 0x90000000 0x10000000>; /* configuration space */ - reg-names = "pads", "afi", "cs"; - interrupts = ; /* MSI interrupt */ - interrupt-names = "intr", "msi"; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; - - bus-range = <0x00 0xff>; - #address-cells = <3>; - #size-cells = <2>; - - ranges = <0x82000000 0 0x80000000 0x80000000 0 0x00001000 /* port 0 registers */ - 0x82000000 0 0x80001000 0x80001000 0 0x00001000 /* port 1 registers */ - 0x81000000 0 0 0x82000000 0 0x00010000 /* downstream I/O */ - 0x82000000 0 0xa0000000 0xa0000000 0 0x08000000 /* non-prefetchable memory */ - 0xc2000000 0 0xa8000000 0xa8000000 0 0x18000000>; /* prefetchable memory */ - - clocks = <&tegra_car TEGRA20_CLK_PEX>, - <&tegra_car TEGRA20_CLK_AFI>, - <&tegra_car TEGRA20_CLK_PLL_E>; - clock-names = "pex", "afi", "pll_e"; - resets = <&tegra_car 70>, - <&tegra_car 72>, - <&tegra_car 74>; - reset-names = "pex", "afi", "pcie_x"; - status = "disabled"; - - pci@1,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>; - reg = <0x000800 0 0 0 0>; - bus-range = <0x00 0xff>; - status = "disabled"; - - #address-cells = <3>; - #size-cells = <2>; - ranges; - - nvidia,num-lanes = <2>; - }; - - pci@2,0 { - device_type = "pci"; - assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>; - reg = <0x001000 0 0 0 0>; - bus-range = <0x00 0xff>; - status = "disabled"; - - #address-cells = <3>; - #size-cells = <2>; - ranges; - - nvidia,num-lanes = <2>; - }; - }; - - usb@c5000000 { - compatible = "nvidia,tegra20-ehci", "usb-ehci"; - reg = <0xc5000000 0x4000>; - interrupts = ; - phy_type = "utmi"; - nvidia,has-legacy-mode; - clocks = <&tegra_car TEGRA20_CLK_USBD>; - resets = <&tegra_car 22>; - reset-names = "usb"; - nvidia,needs-double-reset; - nvidia,phy = <&phy1>; - status = "disabled"; - }; - - phy1: usb-phy@c5000000 { - compatible = "nvidia,tegra20-usb-phy"; - reg = <0xc5000000 0x4000 0xc5000000 0x4000>; - phy_type = "utmi"; - clocks = <&tegra_car TEGRA20_CLK_USBD>, - <&tegra_car TEGRA20_CLK_PLL_U>, - <&tegra_car TEGRA20_CLK_CLK_M>, - <&tegra_car TEGRA20_CLK_USBD>; - clock-names = "reg", "pll_u", "timer", "utmi-pads"; - resets = <&tegra_car 22>, <&tegra_car 22>; - reset-names = "usb", "utmi-pads"; - nvidia,has-legacy-mode; - nvidia,hssync-start-delay = <9>; - nvidia,idle-wait-delay = <17>; - nvidia,elastic-limit = <16>; - nvidia,term-range-adj = <6>; - nvidia,xcvr-setup = <9>; - nvidia,xcvr-lsfslew = <1>; - nvidia,xcvr-lsrslew = <1>; - nvidia,has-utmi-pad-registers; - status = "disabled"; - }; - - usb@c5004000 { - compatible = "nvidia,tegra20-ehci", "usb-ehci"; - reg = <0xc5004000 0x4000>; - interrupts = ; - phy_type = "ulpi"; - clocks = <&tegra_car TEGRA20_CLK_USB2>; - resets = <&tegra_car 58>; - reset-names = "usb"; - nvidia,phy = <&phy2>; - status = "disabled"; - }; - - phy2: usb-phy@c5004000 { - compatible = "nvidia,tegra20-usb-phy"; - reg = <0xc5004000 0x4000>; - phy_type = "ulpi"; - clocks = <&tegra_car TEGRA20_CLK_USB2>, - <&tegra_car TEGRA20_CLK_PLL_U>, - <&tegra_car TEGRA20_CLK_CDEV2>; - clock-names = "reg", "pll_u", "ulpi-link"; - resets = <&tegra_car 58>, <&tegra_car 22>; - reset-names = "usb", "utmi-pads"; - status = "disabled"; - }; - - usb@c5008000 { - compatible = "nvidia,tegra20-ehci", "usb-ehci"; - reg = <0xc5008000 0x4000>; - interrupts = ; - phy_type = "utmi"; - clocks = <&tegra_car TEGRA20_CLK_USB3>; - resets = <&tegra_car 59>; - reset-names = "usb"; - nvidia,phy = <&phy3>; - status = "disabled"; - }; - - phy3: usb-phy@c5008000 { - compatible = "nvidia,tegra20-usb-phy"; - reg = <0xc5008000 0x4000 0xc5000000 0x4000>; - phy_type = "utmi"; - clocks = <&tegra_car TEGRA20_CLK_USB3>, - <&tegra_car TEGRA20_CLK_PLL_U>, - <&tegra_car TEGRA20_CLK_CLK_M>, - <&tegra_car TEGRA20_CLK_USBD>; - clock-names = "reg", "pll_u", "timer", "utmi-pads"; - resets = <&tegra_car 59>, <&tegra_car 22>; - reset-names = "usb", "utmi-pads"; - nvidia,hssync-start-delay = <9>; - nvidia,idle-wait-delay = <17>; - nvidia,elastic-limit = <16>; - nvidia,term-range-adj = <6>; - nvidia,xcvr-setup = <9>; - nvidia,xcvr-lsfslew = <2>; - nvidia,xcvr-lsrslew = <2>; - status = "disabled"; - }; - - sdhci@c8000000 { - compatible = "nvidia,tegra20-sdhci"; - reg = <0xc8000000 0x200>; - interrupts = ; - clocks = <&tegra_car TEGRA20_CLK_SDMMC1>; - resets = <&tegra_car 14>; - reset-names = "sdhci"; - status = "disabled"; - }; - - sdhci@c8000200 { - compatible = "nvidia,tegra20-sdhci"; - reg = <0xc8000200 0x200>; - interrupts = ; - clocks = <&tegra_car TEGRA20_CLK_SDMMC2>; - resets = <&tegra_car 9>; - reset-names = "sdhci"; - status = "disabled"; - }; - - sdhci@c8000400 { - compatible = "nvidia,tegra20-sdhci"; - reg = <0xc8000400 0x200>; - interrupts = ; - clocks = <&tegra_car TEGRA20_CLK_SDMMC3>; - resets = <&tegra_car 69>; - reset-names = "sdhci"; - status = "disabled"; - }; - - sdhci@c8000600 { - compatible = "nvidia,tegra20-sdhci"; - reg = <0xc8000600 0x200>; - interrupts = ; - clocks = <&tegra_car TEGRA20_CLK_SDMMC4>; - resets = <&tegra_car 15>; - reset-names = "sdhci"; - status = "disabled"; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - clocks = <&tegra_car TEGRA20_CLK_CCLK>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <1>; - clocks = <&tegra_car TEGRA20_CLK_CCLK>; - }; - }; - - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts = , - ; - interrupt-affinity = <&{/cpus/cpu@0}>, - <&{/cpus/cpu@1}>; - }; -}; diff --git a/sys/gnu/dts/arm/tegra30-apalis-eval.dts b/sys/gnu/dts/arm/tegra30-apalis-eval.dts deleted file mode 100644 index 749fc6d1ff7..00000000000 --- a/sys/gnu/dts/arm/tegra30-apalis-eval.dts +++ /dev/null @@ -1,248 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include -#include "tegra30-apalis.dtsi" - -/ { - model = "Toradex Apalis T30 on Apalis Evaluation Board"; - compatible = "toradex,apalis_t30-eval", "toradex,apalis_t30", - "nvidia,tegra30"; - - aliases { - rtc0 = "/i2c@7000c000/rtc@68"; - rtc1 = "/i2c@7000d000/pmic@2d"; - rtc2 = "/rtc@7000e000"; - serial0 = &uarta; - serial1 = &uartb; - serial2 = &uartc; - serial3 = &uartd; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - pcie@3000 { - pci@1,0 { - status = "okay"; - }; - - pci@2,0 { - status = "okay"; - }; - }; - - host1x@50000000 { - dc@54200000 { - rgb { - status = "okay"; - nvidia,panel = <&panel>; - }; - }; - - hdmi@54280000 { - status = "okay"; - hdmi-supply = <®_5v0>; - }; - }; - - /* Apalis UART1 */ - serial@70006000 { - status = "okay"; - }; - - /* Apalis UART2 */ - serial@70006040 { - status = "okay"; - }; - - /* Apalis UART3 */ - serial@70006200 { - status = "okay"; - }; - - /* Apalis UART4 */ - serial@70006300 { - status = "okay"; - }; - - pwm@7000a000 { - status = "okay"; - }; - - /* - * GEN1_I2C: I2C1_SDA/SCL on MXM3 pin 209/211 (e.g. RTC on carrier - * board) - */ - i2c@7000c000 { - status = "okay"; - clock-frequency = <400000>; - - pcie-switch@58 { - compatible = "plx,pex8605"; - reg = <0x58>; - }; - - /* M41T0M6 real time clock on carrier board */ - rtc@68 { - compatible = "st,m41t0"; - reg = <0x68>; - }; - }; - - /* GEN2_I2C: unused */ - - /* - * CAM_I2C: I2C3_SDA/SCL on MXM3 pin 201/203 (e.g. camera sensor on - * carrier board) - */ - i2c@7000c500 { - status = "okay"; - clock-frequency = <400000>; - }; - - /* DDC: I2C2_SDA/SCL on MXM3 pin 205/207 (e.g. display EDID) */ - i2c@7000c700 { - status = "okay"; - }; - - /* SPI1: Apalis SPI1 */ - spi@7000d400 { - status = "okay"; - spi-max-frequency = <25000000>; - }; - - /* SPI5: Apalis SPI2 */ - spi@7000dc00 { - status = "okay"; - spi-max-frequency = <25000000>; - }; - - /* Apalis SD1 */ - sdhci@78000000 { - status = "okay"; - bus-width = <4>; - /* SD1_CD# */ - cd-gpios = <&gpio TEGRA_GPIO(CC, 5) GPIO_ACTIVE_LOW>; - no-1-8-v; - }; - - /* Apalis MMC1 */ - sdhci@78000400 { - status = "okay"; - bus-width = <8>; - /* MMC1_CD# */ - cd-gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>; - no-1-8-v; - }; - - /* EHCI instance 0: USB1_DP/N -> USBO1_DP/N */ - usb@7d000000 { - status = "okay"; - dr_mode = "otg"; - }; - - usb-phy@7d000000 { - status = "okay"; - vbus-supply = <®_usbo1_vbus>; - }; - - /* EHCI instance 1: USB2_DP/N -> USBH2_DP/N */ - usb@7d004000 { - status = "okay"; - }; - - usb-phy@7d004000 { - status = "okay"; - vbus-supply = <®_usbh_vbus>; - }; - - /* EHCI instance 2: USB3_DP/N -> USBH3_DP/N */ - usb@7d008000 { - status = "okay"; - }; - - usb-phy@7d008000 { - status = "okay"; - vbus-supply = <®_usbh_vbus>; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - brightness-levels = <255 231 223 207 191 159 127 0>; - default-brightness-level = <6>; - /* BKL1_ON */ - enable-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; - power-supply = <®_3v3>; - pwms = <&pwm 0 5000000>; /* BKL1_PWM */ - }; - - gpio-keys { - compatible = "gpio-keys"; - - wakeup { - label = "WAKE1_MICO"; - gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <10>; - wakeup-source; - }; - }; - - panel: panel { - /* - * edt,et057090dhu: EDT 5.7" LCD TFT - * edt,et070080dh6: EDT 7.0" LCD TFT - */ - compatible = "edt,et057090dhu", "simple-panel"; - backlight = <&backlight>; - power-supply = <®_3v3>; - }; - - reg_3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "3.3V_SW"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_5v0: regulator-5v0 { - compatible = "regulator-fixed"; - regulator-name = "5V_SW"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - /* USBO1_EN */ - reg_usbo1_vbus: regulator-usbo1-vbus { - compatible = "regulator-fixed"; - regulator-name = "VCC_USBO1"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(T, 5) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <®_5v0>; - }; - - /* USBH_EN */ - reg_usbh_vbus: regulator-usbh-vbus { - compatible = "regulator-fixed"; - regulator-name = "VCC_USBH(2A|2C|2D|3|4)"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <®_5v0>; - }; -}; - -&gpio { - /* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */ - pex-perst-n { - gpio-hog; - gpios = ; - output-high; - line-name = "PEX_PERST_N"; - }; -}; diff --git a/sys/gnu/dts/arm/tegra30-apalis-v1.1-eval.dts b/sys/gnu/dts/arm/tegra30-apalis-v1.1-eval.dts deleted file mode 100644 index 0be50e88168..00000000000 --- a/sys/gnu/dts/arm/tegra30-apalis-v1.1-eval.dts +++ /dev/null @@ -1,266 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT -/dts-v1/; - -#include -#include "tegra30-apalis-v1.1.dtsi" - -/ { - model = "Toradex Apalis T30 on Apalis Evaluation Board"; - compatible = "toradex,apalis_t30-v1.1-eval", "toradex,apalis_t30-eval", - "toradex,apalis_t30-v1.1", "toradex,apalis_t30", - "nvidia,tegra30"; - - aliases { - rtc0 = "/i2c@7000c000/rtc@68"; - rtc1 = "/i2c@7000d000/pmic@2d"; - rtc2 = "/rtc@7000e000"; - serial0 = &uarta; - serial1 = &uartb; - serial2 = &uartc; - serial3 = &uartd; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - pcie@3000 { - pci@1,0 { - status = "okay"; - }; - - pci@2,0 { - status = "okay"; - }; - }; - - host1x@50000000 { - dc@54200000 { - rgb { - status = "okay"; - nvidia,panel = <&panel>; - }; - }; - - hdmi@54280000 { - status = "okay"; - hdmi-supply = <®_5v0>; - }; - }; - - /* Apalis UART1 */ - serial@70006000 { - status = "okay"; - }; - - /* Apalis UART2 */ - serial@70006040 { - status = "okay"; - }; - - /* Apalis UART3 */ - serial@70006200 { - status = "okay"; - }; - - /* Apalis UART4 */ - serial@70006300 { - status = "okay"; - }; - - pwm@7000a000 { - status = "okay"; - }; - - /* - * GEN1_I2C: I2C1_SDA/SCL on MXM3 pin 209/211 (e.g. RTC on carrier - * board) - */ - i2c@7000c000 { - status = "okay"; - clock-frequency = <400000>; - - pcie-switch@58 { - compatible = "plx,pex8605"; - reg = <0x58>; - }; - - /* M41T0M6 real time clock on carrier board */ - rtc@68 { - compatible = "st,m41t0"; - reg = <0x68>; - }; - }; - - /* GEN2_I2C: unused */ - - /* - * CAM_I2C: I2C3_SDA/SCL on MXM3 pin 201/203 (e.g. camera sensor on - * carrier board) - */ - i2c@7000c500 { - status = "okay"; - clock-frequency = <400000>; - }; - - /* DDC: I2C2_SDA/SCL on MXM3 pin 205/207 (e.g. display EDID) */ - i2c@7000c700 { - status = "okay"; - }; - - /* SPI1: Apalis SPI1 */ - spi@7000d400 { - status = "okay"; - spi-max-frequency = <25000000>; - }; - - /* SPI5: Apalis SPI2 */ - spi@7000dc00 { - status = "okay"; - spi-max-frequency = <25000000>; - }; - - /* Apalis SD1 */ - sdhci@78000000 { - status = "okay"; - bus-width = <4>; - /* SD1_CD# */ - cd-gpios = <&gpio TEGRA_GPIO(CC, 5) GPIO_ACTIVE_LOW>; - no-1-8-v; - }; - - /* Apalis MMC1 */ - sdhci@78000400 { - status = "okay"; - bus-width = <8>; - /* MMC1_CD# */ - cd-gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>; - vqmmc-supply = <®_vddio_sdmmc3>; - }; - - /* EHCI instance 0: USB1_DP/N -> USBO1_DP/N */ - usb@7d000000 { - status = "okay"; - dr_mode = "otg"; - }; - - usb-phy@7d000000 { - status = "okay"; - vbus-supply = <®_usbo1_vbus>; - }; - - /* EHCI instance 1: USB2_DP/N -> USBH2_DP/N */ - usb@7d004000 { - status = "okay"; - }; - - usb-phy@7d004000 { - status = "okay"; - vbus-supply = <®_usbh_vbus>; - }; - - /* EHCI instance 2: USB3_DP/N -> USBH3_DP/N */ - usb@7d008000 { - status = "okay"; - }; - - usb-phy@7d008000 { - status = "okay"; - vbus-supply = <®_usbh_vbus>; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - brightness-levels = <255 231 223 207 191 159 127 0>; - default-brightness-level = <6>; - /* BKL1_ON */ - enable-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; - power-supply = <®_3v3>; - pwms = <&pwm 0 5000000>; /* BKL1_PWM */ - }; - - gpio-keys { - compatible = "gpio-keys"; - - wakeup { - label = "WAKE1_MICO"; - gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <10>; - wakeup-source; - }; - }; - - panel: panel { - /* - * edt,et057090dhu: EDT 5.7" LCD TFT - * edt,et070080dh6: EDT 7.0" LCD TFT - */ - compatible = "edt,et057090dhu", "simple-panel"; - backlight = <&backlight>; - power-supply = <®_3v3>; - }; - - reg_3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "3.3V_SW"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_5v0: regulator-5v0 { - compatible = "regulator-fixed"; - regulator-name = "5V_SW"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - /* USBO1_EN */ - reg_usbo1_vbus: regulator-usbo1-vbus { - compatible = "regulator-fixed"; - regulator-name = "VCC_USBO1"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(T, 5) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <®_5v0>; - }; - - /* USBH_EN */ - reg_usbh_vbus: regulator-usbh-vbus { - compatible = "regulator-fixed"; - regulator-name = "VCC_USBH(2A|2C|2D|3|4)"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <®_5v0>; - }; - - /* - * 1.8 volt resp. 3.3 volt VDDIO_SDMMC3 depending on - * EN_+3.3_SDMMC3 GPIO - */ - reg_vddio_sdmmc3: regulator-vddio-sdmmc3 { - compatible = "regulator-gpio"; - regulator-name = "VDDIO_SDMMC3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-type = "voltage"; - gpios = <&gpio TEGRA_GPIO(J, 5) GPIO_ACTIVE_HIGH>; - states = <1800000 0x0 - 3300000 0x1>; - startup-delay-us = <100000>; - vin-supply = <&vddio_sdmmc_1v8_reg>; - }; -}; - -&gpio { - /* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */ - pex-perst-n { - gpio-hog; - gpios = ; - output-high; - line-name = "PEX_PERST_N"; - }; -}; diff --git a/sys/gnu/dts/arm/tegra30-apalis-v1.1.dtsi b/sys/gnu/dts/arm/tegra30-apalis-v1.1.dtsi deleted file mode 100644 index 8b7a827d604..00000000000 --- a/sys/gnu/dts/arm/tegra30-apalis-v1.1.dtsi +++ /dev/null @@ -1,1195 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT -#include "tegra30.dtsi" - -/* - * Toradex Apalis T30 Module Device Tree - * Compatible for Revisions 1GB: V1.1A, V1.1B; 1GB IT: V1.1A, V1.1B; - * 2GB: V1.1A, V1.1B - */ -/ { - memory@80000000 { - reg = <0x80000000 0x40000000>; - }; - - pcie@3000 { - status = "okay"; - avdd-pexa-supply = <&vdd2_reg>; - avdd-pexb-supply = <&vdd2_reg>; - avdd-pex-pll-supply = <&vdd2_reg>; - avdd-plle-supply = <&ldo6_reg>; - hvdd-pex-supply = <®_module_3v3>; - vddio-pex-ctl-supply = <®_module_3v3>; - vdd-pexa-supply = <&vdd2_reg>; - vdd-pexb-supply = <&vdd2_reg>; - - /* Apalis type specific */ - pci@1,0 { - nvidia,num-lanes = <4>; - }; - - /* Apalis PCIe */ - pci@2,0 { - nvidia,num-lanes = <1>; - }; - - /* I210/I211 Gigabit Ethernet Controller (on-module) */ - pci@3,0 { - status = "okay"; - nvidia,num-lanes = <1>; - - pcie@0 { - reg = <0 0 0 0 0>; - local-mac-address = [00 00 00 00 00 00]; - }; - }; - }; - - host1x@50000000 { - hdmi@54280000 { - nvidia,ddc-i2c-bus = <&hdmi_ddc>; - nvidia,hpd-gpio = - <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; - pll-supply = <®_1v8_avdd_hdmi_pll>; - vdd-supply = <®_3v3_avdd_hdmi>; - }; - }; - - pinmux@70000868 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - /* Analogue Audio (On-module) */ - clk1-out-pw4 { - nvidia,pins = "clk1_out_pw4"; - nvidia,function = "extperiph1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3-fs-pp0 { - nvidia,pins = "dap3_fs_pp0", - "dap3_sclk_pp3", - "dap3_din_pp1", - "dap3_dout_pp2"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Apalis BKL1_ON */ - pv2 { - nvidia,pins = "pv2"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis BKL1_PWM */ - uart3-rts-n-pc0 { - nvidia,pins = "uart3_rts_n_pc0"; - nvidia,function = "pwm0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - /* BKL1_PWM_EN#, disable TPS65911 PMIC PWM backlight */ - uart3-cts-n-pa1 { - nvidia,pins = "uart3_cts_n_pa1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis CAN1 on SPI6 */ - spi2-cs0-n-px3 { - nvidia,pins = "spi2_cs0_n_px3", - "spi2_miso_px1", - "spi2_mosi_px0", - "spi2_sck_px2"; - nvidia,function = "spi6"; - nvidia,pull = ; - nvidia,tristate = ; - }; - /* CAN_INT1 */ - spi2-cs1-n-pw2 { - nvidia,pins = "spi2_cs1_n_pw2"; - nvidia,function = "spi3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis CAN2 on SPI4 */ - gmi-a16-pj7 { - nvidia,pins = "gmi_a16_pj7", - "gmi_a17_pb0", - "gmi_a18_pb1", - "gmi_a19_pk7"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - /* CAN_INT2 */ - spi2-cs2-n-pw3 { - nvidia,pins = "spi2_cs2_n_pw3"; - nvidia,function = "spi3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis Digital Audio */ - clk1-req-pee2 { - nvidia,pins = "clk1_req_pee2"; - nvidia,function = "hda"; - nvidia,pull = ; - nvidia,tristate = ; - }; - clk2-out-pw5 { - nvidia,pins = "clk2_out_pw5"; - nvidia,function = "extperiph2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap1-fs-pn0 { - nvidia,pins = "dap1_fs_pn0", - "dap1_din_pn1", - "dap1_dout_pn2", - "dap1_sclk_pn3"; - nvidia,function = "hda"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Apalis GPIO */ - kb-col0-pq0 { - nvidia,pins = "kb_col0_pq0", - "kb_col1_pq1", - "kb_row10_ps2", - "kb_row11_ps3", - "kb_row12_ps4", - "kb_row13_ps5", - "kb_row14_ps6", - "kb_row15_ps7"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - /* Multiplexed and therefore disabled */ - owr { - nvidia,pins = "owr"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis HDMI1 */ - hdmi-cec-pee3 { - nvidia,pins = "hdmi_cec_pee3"; - nvidia,function = "cec"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - hdmi-int-pn7 { - nvidia,pins = "hdmi_int_pn7"; - nvidia,function = "hdmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis I2C1 */ - gen1-i2c-scl-pc4 { - nvidia,pins = "gen1_i2c_scl_pc4", - "gen1_i2c_sda_pc5"; - nvidia,function = "i2c1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - - /* Apalis I2C2 (DDC) */ - ddc-scl-pv4 { - nvidia,pins = "ddc_scl_pv4", - "ddc_sda_pv5"; - nvidia,function = "i2c4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis I2C3 (CAM) */ - cam-i2c-scl-pbb1 { - nvidia,pins = "cam_i2c_scl_pbb1", - "cam_i2c_sda_pbb2"; - nvidia,function = "i2c3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - - /* Apalis LCD1 */ - lcd-d0-pe0 { - nvidia,pins = "lcd_d0_pe0", - "lcd_d1_pe1", - "lcd_d2_pe2", - "lcd_d3_pe3", - "lcd_d4_pe4", - "lcd_d5_pe5", - "lcd_d6_pe6", - "lcd_d7_pe7", - "lcd_d8_pf0", - "lcd_d9_pf1", - "lcd_d10_pf2", - "lcd_d11_pf3", - "lcd_d12_pf4", - "lcd_d13_pf5", - "lcd_d14_pf6", - "lcd_d15_pf7", - "lcd_d16_pm0", - "lcd_d17_pm1", - "lcd_d18_pm2", - "lcd_d19_pm3", - "lcd_d20_pm4", - "lcd_d21_pm5", - "lcd_d22_pm6", - "lcd_d23_pm7", - "lcd_de_pj1", - "lcd_hsync_pj3", - "lcd_pclk_pb3", - "lcd_vsync_pj4"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis MMC1 */ - sdmmc3-clk-pa6 { - nvidia,pins = "sdmmc3_clk_pa6"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - }; - sdmmc3-dat0-pb7 { - nvidia,pins = "sdmmc3_cmd_pa7", - "sdmmc3_dat0_pb7", - "sdmmc3_dat1_pb6", - "sdmmc3_dat2_pb5", - "sdmmc3_dat3_pb4", - "sdmmc3_dat4_pd1", - "sdmmc3_dat5_pd0", - "sdmmc3_dat6_pd3", - "sdmmc3_dat7_pd4"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - }; - /* Apalis MMC1_CD# */ - pv3 { - nvidia,pins = "pv3"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis Parallel Camera */ - cam-mclk-pcc0 { - nvidia,pins = "cam_mclk_pcc0"; - nvidia,function = "vi_alt3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi-vsync-pd6 { - nvidia,pins = "vi_d0_pt4", - "vi_d1_pd5", - "vi_d2_pl0", - "vi_d3_pl1", - "vi_d4_pl2", - "vi_d5_pl3", - "vi_d6_pl4", - "vi_d7_pl5", - "vi_d8_pl6", - "vi_d9_pl7", - "vi_d10_pt2", - "vi_d11_pt3", - "vi_hsync_pd7", - "vi_pclk_pt0", - "vi_vsync_pd6"; - nvidia,function = "vi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - /* Multiplexed and therefore disabled */ - kb-col2-pq2 { - nvidia,pins = "kb_col2_pq2", - "kb_col3_pq3", - "kb_col4_pq4", - "kb_row4_pr4"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-row0-pr0 { - nvidia,pins = "kb_row0_pr0", - "kb_row1_pr1", - "kb_row2_pr2", - "kb_row3_pr3"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-row5-pr5 { - nvidia,pins = "kb_row5_pr5", - "kb_row6_pr6", - "kb_row7_pr7"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - /* - * VI level-shifter direction - * (pull-down => default direction input) - */ - vi-mclk-pt1 { - nvidia,pins = "vi_mclk_pt1"; - nvidia,function = "vi_alt3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis PWM1 */ - pu6 { - nvidia,pins = "pu6"; - nvidia,function = "pwm3"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Apalis PWM2 */ - pu5 { - nvidia,pins = "pu5"; - nvidia,function = "pwm2"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Apalis PWM3 */ - pu4 { - nvidia,pins = "pu4"; - nvidia,function = "pwm1"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Apalis PWM4 */ - pu3 { - nvidia,pins = "pu3"; - nvidia,function = "pwm0"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Apalis RESET_MOCI# */ - gmi-rst-n-pi4 { - nvidia,pins = "gmi_rst_n_pi4"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Apalis SATA1_ACT# */ - pex-l0-prsnt-n-pdd0 { - nvidia,pins = "pex_l0_prsnt_n_pdd0"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis SD1 */ - sdmmc1-clk-pz0 { - nvidia,pins = "sdmmc1_clk_pz0"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - }; - sdmmc1-cmd-pz1 { - nvidia,pins = "sdmmc1_cmd_pz1", - "sdmmc1_dat0_py7", - "sdmmc1_dat1_py6", - "sdmmc1_dat2_py5", - "sdmmc1_dat3_py4"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - }; - /* Apalis SD1_CD# */ - clk2-req-pcc5 { - nvidia,pins = "clk2_req_pcc5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis SPDIF1 */ - spdif-out-pk5 { - nvidia,pins = "spdif_out_pk5", - "spdif_in_pk6"; - nvidia,function = "spdif"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis SPI1 */ - spi1-sck-px5 { - nvidia,pins = "spi1_sck_px5", - "spi1_mosi_px4", - "spi1_miso_px7", - "spi1_cs0_n_px6"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Apalis SPI2 */ - lcd-sck-pz4 { - nvidia,pins = "lcd_sck_pz4", - "lcd_sdout_pn5", - "lcd_sdin_pz2", - "lcd_cs0_n_pn4"; - nvidia,function = "spi5"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* - * Apalis TS (Low-speed type specific) - * pins may be used as GPIOs - */ - kb-col5-pq5 { - nvidia,pins = "kb_col5_pq5"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-col6-pq6 { - nvidia,pins = "kb_col6_pq6", - "kb_col7_pq7", - "kb_row8_ps0", - "kb_row9_ps1"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis UART1 */ - ulpi-data0 { - nvidia,pins = "ulpi_data0_po1", - "ulpi_data1_po2", - "ulpi_data2_po3", - "ulpi_data3_po4", - "ulpi_data4_po5", - "ulpi_data5_po6", - "ulpi_data6_po7", - "ulpi_data7_po0"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Apalis UART2 */ - ulpi-clk-py0 { - nvidia,pins = "ulpi_clk_py0", - "ulpi_dir_py1", - "ulpi_nxt_py2", - "ulpi_stp_py3"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Apalis UART3 */ - uart2-rxd-pc3 { - nvidia,pins = "uart2_rxd_pc3", - "uart2_txd_pc2"; - nvidia,function = "uartb"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Apalis UART4 */ - uart3-rxd-pw7 { - nvidia,pins = "uart3_rxd_pw7", - "uart3_txd_pw6"; - nvidia,function = "uartc"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Apalis USBH_EN */ - pex-l0-rst-n-pdd1 { - nvidia,pins = "pex_l0_rst_n_pdd1"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis USBH_OC# */ - pex-l0-clkreq-n-pdd2 { - nvidia,pins = "pex_l0_clkreq_n_pdd2"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis USBO1_EN */ - gen2-i2c-scl-pt5 { - nvidia,pins = "gen2_i2c_scl_pt5"; - nvidia,function = "rsvd4"; - nvidia,open-drain = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Apalis USBO1_OC# */ - gen2-i2c-sda-pt6 { - nvidia,pins = "gen2_i2c_sda_pt6"; - nvidia,function = "rsvd4"; - nvidia,open-drain = ; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis VGA1 not supported and therefore disabled */ - crt-hsync-pv6 { - nvidia,pins = "crt_hsync_pv6", - "crt_vsync_pv7"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis WAKE1_MICO */ - pv1 { - nvidia,pins = "pv1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* eMMC (On-module) */ - sdmmc4-clk-pcc4 { - nvidia,pins = "sdmmc4_clk_pcc4", - "sdmmc4_cmd_pt7", - "sdmmc4_rst_n_pcc3"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4-dat0-paa0 { - nvidia,pins = "sdmmc4_dat0_paa0", - "sdmmc4_dat1_paa1", - "sdmmc4_dat2_paa2", - "sdmmc4_dat3_paa3", - "sdmmc4_dat4_paa4", - "sdmmc4_dat5_paa5", - "sdmmc4_dat6_paa6", - "sdmmc4_dat7_paa7"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* EN_+3.3_SDMMC3 */ - uart2-cts-n-pj5 { - nvidia,pins = "uart2_cts_n_pj5"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* LAN i210/i211 DEV_OFF_N, PE_RST_N (On-module) */ - pex-l2-prsnt-n-pdd7 { - nvidia,pins = "pex_l2_prsnt_n_pdd7", - "pex_l2_rst_n_pcc6"; - nvidia,function = "pcie"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - /* LAN i210/i211 PE_WAKE_N, SDP3 (On-module) */ - pex-wake-n-pdd3 { - nvidia,pins = "pex_wake_n_pdd3", - "pex_l2_clkreq_n_pcc7"; - nvidia,function = "pcie"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - /* LAN i210/i211 SMB_ALERT_N (On-module) */ - sys-clk-req-pz5 { - nvidia,pins = "sys_clk_req_pz5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* LVDS Transceiver Configuration */ - pbb0 { - nvidia,pins = "pbb0", - "pbb7", - "pcc1", - "pcc2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pbb3 { - nvidia,pins = "pbb3", - "pbb4", - "pbb5", - "pbb6"; - nvidia,function = "displayb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Not connected and therefore disabled */ - clk-32k-out-pa0 { - nvidia,pins = "clk3_out_pee0", - "clk3_req_pee1", - "clk_32k_out_pa0", - "dap4_din_pp5", - "dap4_dout_pp6", - "dap4_fs_pp4", - "dap4_sclk_pp7"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap2-fs-pa2 { - nvidia,pins = "dap2_fs_pa2", - "dap2_sclk_pa3", - "dap2_din_pa4", - "dap2_dout_pa5", - "lcd_dc0_pn6", - "lcd_m1_pw1", - "lcd_pwr1_pc1", - "pex_l1_clkreq_n_pdd6", - "pex_l1_prsnt_n_pdd4", - "pex_l1_rst_n_pdd5"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi-ad0-pg0 { - nvidia,pins = "gmi_ad0_pg0", - "gmi_ad2_pg2", - "gmi_ad3_pg3", - "gmi_ad4_pg4", - "gmi_ad5_pg5", - "gmi_ad6_pg6", - "gmi_ad7_pg7", - "gmi_ad8_ph0", - "gmi_ad9_ph1", - "gmi_ad10_ph2", - "gmi_ad11_ph3", - "gmi_ad12_ph4", - "gmi_ad13_ph5", - "gmi_ad14_ph6", - "gmi_ad15_ph7", - "gmi_adv_n_pk0", - "gmi_clk_pk1", - "gmi_cs4_n_pk2", - "gmi_cs2_n_pk3", - "gmi_dqs_pi2", - "gmi_iordy_pi5", - "gmi_oe_n_pi1", - "gmi_wait_pi7", - "gmi_wr_n_pi0", - "lcd_cs1_n_pw0", - "pu0", - "pu1", - "pu2"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi-cs0-n-pj0 { - nvidia,pins = "gmi_cs0_n_pj0", - "gmi_cs1_n_pj2", - "gmi_cs3_n_pk4"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi-cs6-n-pi3 { - nvidia,pins = "gmi_cs6_n_pi3"; - nvidia,function = "sata"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi-cs7-n-pi6 { - nvidia,pins = "gmi_cs7_n_pi6"; - nvidia,function = "gmi_alt"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd-pwr0-pb2 { - nvidia,pins = "lcd_pwr0_pb2", - "lcd_pwr2_pc6", - "lcd_wr_n_pz3"; - nvidia,function = "hdcp"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2-rts-n-pj6 { - nvidia,pins = "uart2_rts_n_pj6"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Power I2C (On-module) */ - pwr-i2c-scl-pz6 { - nvidia,pins = "pwr_i2c_scl_pz6", - "pwr_i2c_sda_pz7"; - nvidia,function = "i2cpwr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - - /* - * THERMD_ALERT#, unlatched I2C address pin of LM95245 - * temperature sensor therefore requires disabling for - * now - */ - lcd-dc1-pd2 { - nvidia,pins = "lcd_dc1_pd2"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* TOUCH_PEN_INT# (On-module) */ - pv0 { - nvidia,pins = "pv0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - }; - }; - - serial@70006040 { - compatible = "nvidia,tegra30-hsuart"; - }; - - serial@70006200 { - compatible = "nvidia,tegra30-hsuart"; - }; - - serial@70006300 { - compatible = "nvidia,tegra30-hsuart"; - }; - - hdmi_ddc: i2c@7000c700 { - clock-frequency = <10000>; - }; - - /* - * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and - * touch screen controller - */ - i2c@7000d000 { - status = "okay"; - clock-frequency = <100000>; - - /* SGTL5000 audio codec */ - sgtl5000: codec@a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - VDDA-supply = <®_module_3v3_audio>; - VDDD-supply = <®_1v8_vio>; - VDDIO-supply = <®_module_3v3>; - clocks = <&tegra_car TEGRA30_CLK_EXTERN1>; - }; - - pmic: pmic@2d { - compatible = "ti,tps65911"; - reg = <0x2d>; - - interrupts = ; - #interrupt-cells = <2>; - interrupt-controller; - - ti,system-power-controller; - - #gpio-cells = <2>; - gpio-controller; - - vcc1-supply = <®_module_3v3>; - vcc2-supply = <®_module_3v3>; - vcc3-supply = <®_1v8_vio>; - vcc4-supply = <®_module_3v3>; - vcc5-supply = <®_module_3v3>; - vcc6-supply = <®_1v8_vio>; - vcc7-supply = <®_5v0_charge_pump>; - vccio-supply = <®_module_3v3>; - - regulators { - vdd1_reg: vdd1 { - regulator-name = "+V1.35_VDDIO_DDR"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - }; - - vdd2_reg: vdd2 { - regulator-name = "+V1.05"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - }; - - vddctrl_reg: vddctrl { - regulator-name = "+V1.0_VDD_CPU"; - regulator-min-microvolt = <1150000>; - regulator-max-microvolt = <1150000>; - regulator-always-on; - }; - - reg_1v8_vio: vio { - regulator-name = "+V1.8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - /* - * 1.8 volt +VDDIO_SDMMC3 in case EN_+3.3_SDMMC3 - * is off - */ - vddio_sdmmc_1v8_reg: ldo1 { - regulator-name = "+VDDIO_SDMMC3_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - /* - * EN_+V3.3 switching via FET: - * +V3.3_AUDIO_AVDD_S, +V3.3 - * see also +V3.3 fixed supply - */ - ldo2_reg: ldo2 { - regulator-name = "EN_+V3.3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo3_reg: ldo3 { - regulator-name = "+V1.2_CSI"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - ldo4_reg: ldo4 { - regulator-name = "+V1.2_VDD_RTC"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - /* - * +V2.8_AVDD_VDAC: - * only required for (unsupported) analog RGB - */ - ldo5_reg: ldo5 { - regulator-name = "+V2.8_AVDD_VDAC"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - /* - * +V1.05_AVDD_PLLE: avdd_plle should be 1.05V - * but LDO6 can't set voltage in 50mV - * granularity - */ - ldo6_reg: ldo6 { - regulator-name = "+V1.05_AVDD_PLLE"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - }; - - ldo7_reg: ldo7 { - regulator-name = "+V1.2_AVDD_PLL"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - ldo8_reg: ldo8 { - regulator-name = "+V1.0_VDD_DDR_HS"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - }; - }; - - /* STMPE811 touch screen controller */ - touchscreen@41 { - compatible = "st,stmpe811"; - reg = <0x41>; - irq-gpio = <&gpio TEGRA_GPIO(V, 0) IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - id = <0>; - blocks = <0x5>; - irq-trigger = <0x1>; - /* 3.25 MHz ADC clock speed */ - st,adc-freq = <1>; - /* 12-bit ADC */ - st,mod-12b = <1>; - /* internal ADC reference */ - st,ref-sel = <0>; - /* ADC converstion time: 80 clocks */ - st,sample-time = <4>; - - stmpe_touchscreen { - compatible = "st,stmpe-ts"; - /* 8 sample average control */ - st,ave-ctrl = <3>; - /* 7 length fractional part in z */ - st,fraction-z = <7>; - /* - * 50 mA typical 80 mA max touchscreen drivers - * current limit value - */ - st,i-drive = <1>; - /* 1 ms panel driver settling time */ - st,settling = <3>; - /* 5 ms touch detect interrupt delay */ - st,touch-det-delay = <5>; - }; - - stmpe_adc { - compatible = "st,stmpe-adc"; - /* forbid to use ADC channels 3-0 (touch) */ - st,norequest-mask = <0x0F>; - }; - }; - - /* - * LM95245 temperature sensor - * Note: OVERT1# directly connected to TPS65911 PMIC PWRDN - */ - temp-sensor@4c { - compatible = "national,lm95245"; - reg = <0x4c>; - }; - - /* SW: +V1.2_VDD_CORE */ - regulator@60 { - compatible = "ti,tps62362"; - reg = <0x60>; - - regulator-name = "tps62362-vout"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1400000>; - regulator-boot-on; - regulator-always-on; - ti,vsel0-state-low; - /* VSEL1: EN_CORE_DVFS_N low for DVFS */ - ti,vsel1-state-low; - }; - }; - - /* SPI4: CAN2 */ - spi@7000da00 { - status = "okay"; - spi-max-frequency = <10000000>; - - can@1 { - compatible = "microchip,mcp2515"; - reg = <1>; - clocks = <&clk16m>; - interrupt-parent = <&gpio>; - interrupts = ; - spi-max-frequency = <10000000>; - }; - }; - - /* SPI6: CAN1 */ - spi@7000de00 { - status = "okay"; - spi-max-frequency = <10000000>; - - can@0 { - compatible = "microchip,mcp2515"; - reg = <0>; - clocks = <&clk16m>; - interrupt-parent = <&gpio>; - interrupts = ; - spi-max-frequency = <10000000>; - }; - }; - - pmc@7000e400 { - nvidia,invert-interrupt; - nvidia,suspend-mode = <1>; - nvidia,cpu-pwr-good-time = <5000>; - nvidia,cpu-pwr-off-time = <5000>; - nvidia,core-pwr-good-time = <3845 3845>; - nvidia,core-pwr-off-time = <0>; - nvidia,core-power-req-active-high; - nvidia,sys-clock-req-active-high; - - /* Set DEV_OFF bit in DCDC control register of TPS65911 PMIC */ - i2c-thermtrip { - nvidia,i2c-controller-id = <4>; - nvidia,bus-addr = <0x2d>; - nvidia,reg-addr = <0x3f>; - nvidia,reg-data = <0x1>; - }; - }; - - hda@70030000 { - status = "okay"; - }; - - ahub@70080000 { - i2s@70080500 { - status = "okay"; - }; - }; - - /* eMMC */ - sdhci@78000600 { - status = "okay"; - bus-width = <8>; - non-removable; - vmmc-supply = <®_module_3v3>; /* VCC */ - vqmmc-supply = <®_1v8_vio>; /* VCCQ */ - mmc-ddr-1_8v; - }; - - clk32k_in: xtal1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - - clk16m: osc4 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <16000000>; - }; - - reg_1v8_avdd_hdmi_pll: regulator-1v8-avdd-hdmi-pll { - compatible = "regulator-fixed"; - regulator-name = "+V1.8_AVDD_HDMI_PLL"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - enable-active-high; - gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; - vin-supply = <®_1v8_vio>; - }; - - reg_3v3_avdd_hdmi: regulator-3v3-avdd-hdmi { - compatible = "regulator-fixed"; - regulator-name = "+V3.3_AVDD_HDMI"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; - vin-supply = <®_module_3v3>; - }; - - reg_5v0_charge_pump: regulator-5v0-charge-pump { - compatible = "regulator-fixed"; - regulator-name = "+V5.0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - reg_module_3v3: regulator-module-3v3 { - compatible = "regulator-fixed"; - regulator-name = "+V3.3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_module_3v3_audio: regulator-module-3v3-audio { - compatible = "regulator-fixed"; - regulator-name = "+V3.3_AUDIO_AVDD_S"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - sound { - compatible = "toradex,tegra-audio-sgtl5000-apalis_t30", - "nvidia,tegra-audio-sgtl5000"; - nvidia,model = "Toradex Apalis T30"; - nvidia,audio-routing = - "Headphone Jack", "HP_OUT", - "LINE_IN", "Line In Jack", - "MIC_IN", "Mic Jack"; - nvidia,i2s-controller = <&tegra_i2s2>; - nvidia,audio-codec = <&sgtl5000>; - clocks = <&tegra_car TEGRA30_CLK_PLL_A>, - <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA30_CLK_EXTERN1>; - clock-names = "pll_a", "pll_a_out0", "mclk"; - }; -}; diff --git a/sys/gnu/dts/arm/tegra30-apalis.dtsi b/sys/gnu/dts/arm/tegra30-apalis.dtsi deleted file mode 100644 index c18f6f61d76..00000000000 --- a/sys/gnu/dts/arm/tegra30-apalis.dtsi +++ /dev/null @@ -1,1177 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "tegra30.dtsi" - -/* - * Toradex Apalis T30 Module Device Tree - * Compatible for Revisions 1GB: V1.0A; 2GB: V1.0B, V1.0C, V1.0E - */ -/ { - memory@80000000 { - reg = <0x80000000 0x40000000>; - }; - - pcie@3000 { - status = "okay"; - avdd-pexa-supply = <&vdd2_reg>; - avdd-pexb-supply = <&vdd2_reg>; - avdd-pex-pll-supply = <&vdd2_reg>; - avdd-plle-supply = <&ldo6_reg>; - hvdd-pex-supply = <®_module_3v3>; - vddio-pex-ctl-supply = <®_module_3v3>; - vdd-pexa-supply = <&vdd2_reg>; - vdd-pexb-supply = <&vdd2_reg>; - - /* Apalis type specific */ - pci@1,0 { - nvidia,num-lanes = <4>; - }; - - /* Apalis PCIe */ - pci@2,0 { - nvidia,num-lanes = <1>; - }; - - /* I210/I211 Gigabit Ethernet Controller (on-module) */ - pci@3,0 { - status = "okay"; - nvidia,num-lanes = <1>; - - pcie@0 { - reg = <0 0 0 0 0>; - local-mac-address = [00 00 00 00 00 00]; - }; - }; - }; - - host1x@50000000 { - hdmi@54280000 { - nvidia,ddc-i2c-bus = <&hdmi_ddc>; - nvidia,hpd-gpio = - <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; - pll-supply = <®_1v8_avdd_hdmi_pll>; - vdd-supply = <®_3v3_avdd_hdmi>; - }; - }; - - pinmux@70000868 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - /* Analogue Audio (On-module) */ - clk1-out-pw4 { - nvidia,pins = "clk1_out_pw4"; - nvidia,function = "extperiph1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3-fs-pp0 { - nvidia,pins = "dap3_fs_pp0", - "dap3_sclk_pp3", - "dap3_din_pp1", - "dap3_dout_pp2"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Apalis BKL1_ON */ - pv2 { - nvidia,pins = "pv2"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis BKL1_PWM */ - uart3-rts-n-pc0 { - nvidia,pins = "uart3_rts_n_pc0"; - nvidia,function = "pwm0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - /* BKL1_PWM_EN#, disable TPS65911 PMIC PWM backlight */ - uart3-cts-n-pa1 { - nvidia,pins = "uart3_cts_n_pa1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis CAN1 on SPI6 */ - spi2-cs0-n-px3 { - nvidia,pins = "spi2_cs0_n_px3", - "spi2_miso_px1", - "spi2_mosi_px0", - "spi2_sck_px2"; - nvidia,function = "spi6"; - nvidia,pull = ; - nvidia,tristate = ; - }; - /* CAN_INT1 */ - spi2-cs1-n-pw2 { - nvidia,pins = "spi2_cs1_n_pw2"; - nvidia,function = "spi3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis CAN2 on SPI4 */ - gmi-a16-pj7 { - nvidia,pins = "gmi_a16_pj7", - "gmi_a17_pb0", - "gmi_a18_pb1", - "gmi_a19_pk7"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - /* CAN_INT2 */ - spi2-cs2-n-pw3 { - nvidia,pins = "spi2_cs2_n_pw3"; - nvidia,function = "spi3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis Digital Audio */ - clk1-req-pee2 { - nvidia,pins = "clk1_req_pee2"; - nvidia,function = "hda"; - nvidia,pull = ; - nvidia,tristate = ; - }; - clk2-out-pw5 { - nvidia,pins = "clk2_out_pw5"; - nvidia,function = "extperiph2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap1-fs-pn0 { - nvidia,pins = "dap1_fs_pn0", - "dap1_din_pn1", - "dap1_dout_pn2", - "dap1_sclk_pn3"; - nvidia,function = "hda"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Apalis GPIO */ - kb-col0-pq0 { - nvidia,pins = "kb_col0_pq0", - "kb_col1_pq1", - "kb_row10_ps2", - "kb_row11_ps3", - "kb_row12_ps4", - "kb_row13_ps5", - "kb_row14_ps6", - "kb_row15_ps7"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - /* Multiplexed and therefore disabled */ - owr { - nvidia,pins = "owr"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis HDMI1 */ - hdmi-cec-pee3 { - nvidia,pins = "hdmi_cec_pee3"; - nvidia,function = "cec"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - hdmi-int-pn7 { - nvidia,pins = "hdmi_int_pn7"; - nvidia,function = "hdmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis I2C1 */ - gen1-i2c-scl-pc4 { - nvidia,pins = "gen1_i2c_scl_pc4", - "gen1_i2c_sda_pc5"; - nvidia,function = "i2c1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - - /* Apalis I2C2 (DDC) */ - ddc-scl-pv4 { - nvidia,pins = "ddc_scl_pv4", - "ddc_sda_pv5"; - nvidia,function = "i2c4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis I2C3 (CAM) */ - cam-i2c-scl-pbb1 { - nvidia,pins = "cam_i2c_scl_pbb1", - "cam_i2c_sda_pbb2"; - nvidia,function = "i2c3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - - /* Apalis LCD1 */ - lcd-d0-pe0 { - nvidia,pins = "lcd_d0_pe0", - "lcd_d1_pe1", - "lcd_d2_pe2", - "lcd_d3_pe3", - "lcd_d4_pe4", - "lcd_d5_pe5", - "lcd_d6_pe6", - "lcd_d7_pe7", - "lcd_d8_pf0", - "lcd_d9_pf1", - "lcd_d10_pf2", - "lcd_d11_pf3", - "lcd_d12_pf4", - "lcd_d13_pf5", - "lcd_d14_pf6", - "lcd_d15_pf7", - "lcd_d16_pm0", - "lcd_d17_pm1", - "lcd_d18_pm2", - "lcd_d19_pm3", - "lcd_d20_pm4", - "lcd_d21_pm5", - "lcd_d22_pm6", - "lcd_d23_pm7", - "lcd_de_pj1", - "lcd_hsync_pj3", - "lcd_pclk_pb3", - "lcd_vsync_pj4"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis MMC1 */ - sdmmc3-clk-pa6 { - nvidia,pins = "sdmmc3_clk_pa6"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - }; - sdmmc3-dat0-pb7 { - nvidia,pins = "sdmmc3_cmd_pa7", - "sdmmc3_dat0_pb7", - "sdmmc3_dat1_pb6", - "sdmmc3_dat2_pb5", - "sdmmc3_dat3_pb4", - "sdmmc3_dat4_pd1", - "sdmmc3_dat5_pd0", - "sdmmc3_dat6_pd3", - "sdmmc3_dat7_pd4"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - }; - /* Apalis MMC1_CD# */ - pv3 { - nvidia,pins = "pv3"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis Parallel Camera */ - cam-mclk-pcc0 { - nvidia,pins = "cam_mclk_pcc0"; - nvidia,function = "vi_alt3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi-vsync-pd6 { - nvidia,pins = "vi_d0_pt4", - "vi_d1_pd5", - "vi_d2_pl0", - "vi_d3_pl1", - "vi_d4_pl2", - "vi_d5_pl3", - "vi_d6_pl4", - "vi_d7_pl5", - "vi_d8_pl6", - "vi_d9_pl7", - "vi_d10_pt2", - "vi_d11_pt3", - "vi_hsync_pd7", - "vi_pclk_pt0", - "vi_vsync_pd6"; - nvidia,function = "vi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - /* Multiplexed and therefore disabled */ - kb-col2-pq2 { - nvidia,pins = "kb_col2_pq2", - "kb_col3_pq3", - "kb_col4_pq4", - "kb_row4_pr4"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-row0-pr0 { - nvidia,pins = "kb_row0_pr0", - "kb_row1_pr1", - "kb_row2_pr2", - "kb_row3_pr3"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-row5-pr5 { - nvidia,pins = "kb_row5_pr5", - "kb_row6_pr6", - "kb_row7_pr7"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - /* - * VI level-shifter direction - * (pull-down => default direction input) - */ - vi-mclk-pt1 { - nvidia,pins = "vi_mclk_pt1"; - nvidia,function = "vi_alt3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis PWM1 */ - pu6 { - nvidia,pins = "pu6"; - nvidia,function = "pwm3"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Apalis PWM2 */ - pu5 { - nvidia,pins = "pu5"; - nvidia,function = "pwm2"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Apalis PWM3 */ - pu4 { - nvidia,pins = "pu4"; - nvidia,function = "pwm1"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Apalis PWM4 */ - pu3 { - nvidia,pins = "pu3"; - nvidia,function = "pwm0"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Apalis RESET_MOCI# */ - gmi-rst-n-pi4 { - nvidia,pins = "gmi_rst_n_pi4"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Apalis SATA1_ACT# */ - pex-l0-prsnt-n-pdd0 { - nvidia,pins = "pex_l0_prsnt_n_pdd0"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis SD1 */ - sdmmc1-clk-pz0 { - nvidia,pins = "sdmmc1_clk_pz0"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - }; - sdmmc1-cmd-pz1 { - nvidia,pins = "sdmmc1_cmd_pz1", - "sdmmc1_dat0_py7", - "sdmmc1_dat1_py6", - "sdmmc1_dat2_py5", - "sdmmc1_dat3_py4"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - }; - /* Apalis SD1_CD# */ - clk2-req-pcc5 { - nvidia,pins = "clk2_req_pcc5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis SPDIF1 */ - spdif-out-pk5 { - nvidia,pins = "spdif_out_pk5", - "spdif_in_pk6"; - nvidia,function = "spdif"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis SPI1 */ - spi1-sck-px5 { - nvidia,pins = "spi1_sck_px5", - "spi1_mosi_px4", - "spi1_miso_px7", - "spi1_cs0_n_px6"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Apalis SPI2 */ - lcd-sck-pz4 { - nvidia,pins = "lcd_sck_pz4", - "lcd_sdout_pn5", - "lcd_sdin_pz2", - "lcd_cs0_n_pn4"; - nvidia,function = "spi5"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* - * Apalis TS (Low-speed type specific) - * pins may be used as GPIOs - */ - kb-col5-pq5 { - nvidia,pins = "kb_col5_pq5"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-col6-pq6 { - nvidia,pins = "kb_col6_pq6", - "kb_col7_pq7", - "kb_row8_ps0", - "kb_row9_ps1"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis UART1 */ - ulpi-data0 { - nvidia,pins = "ulpi_data0_po1", - "ulpi_data1_po2", - "ulpi_data2_po3", - "ulpi_data3_po4", - "ulpi_data4_po5", - "ulpi_data5_po6", - "ulpi_data6_po7", - "ulpi_data7_po0"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Apalis UART2 */ - ulpi-clk-py0 { - nvidia,pins = "ulpi_clk_py0", - "ulpi_dir_py1", - "ulpi_nxt_py2", - "ulpi_stp_py3"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Apalis UART3 */ - uart2-rxd-pc3 { - nvidia,pins = "uart2_rxd_pc3", - "uart2_txd_pc2"; - nvidia,function = "uartb"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Apalis UART4 */ - uart3-rxd-pw7 { - nvidia,pins = "uart3_rxd_pw7", - "uart3_txd_pw6"; - nvidia,function = "uartc"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Apalis USBH_EN */ - pex-l0-rst-n-pdd1 { - nvidia,pins = "pex_l0_rst_n_pdd1"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis USBH_OC# */ - pex-l0-clkreq-n-pdd2 { - nvidia,pins = "pex_l0_clkreq_n_pdd2"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis USBO1_EN */ - gen2-i2c-scl-pt5 { - nvidia,pins = "gen2_i2c_scl_pt5"; - nvidia,function = "rsvd4"; - nvidia,open-drain = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Apalis USBO1_OC# */ - gen2-i2c-sda-pt6 { - nvidia,pins = "gen2_i2c_sda_pt6"; - nvidia,function = "rsvd4"; - nvidia,open-drain = ; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis VGA1 not supported and therefore disabled */ - crt-hsync-pv6 { - nvidia,pins = "crt_hsync_pv6", - "crt_vsync_pv7"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis WAKE1_MICO */ - pv1 { - nvidia,pins = "pv1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* eMMC (On-module) */ - sdmmc4-clk-pcc4 { - nvidia,pins = "sdmmc4_clk_pcc4", - "sdmmc4_cmd_pt7", - "sdmmc4_rst_n_pcc3"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4-dat0-paa0 { - nvidia,pins = "sdmmc4_dat0_paa0", - "sdmmc4_dat1_paa1", - "sdmmc4_dat2_paa2", - "sdmmc4_dat3_paa3", - "sdmmc4_dat4_paa4", - "sdmmc4_dat5_paa5", - "sdmmc4_dat6_paa6", - "sdmmc4_dat7_paa7"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* LAN i210/i211 DEV_OFF_N, PE_RST_N (On-module) */ - pex-l2-prsnt-n-pdd7 { - nvidia,pins = "pex_l2_prsnt_n_pdd7", - "pex_l2_rst_n_pcc6"; - nvidia,function = "pcie"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - /* LAN i210/i211 PE_WAKE_N, SDP3 (On-module) */ - pex-wake-n-pdd3 { - nvidia,pins = "pex_wake_n_pdd3", - "pex_l2_clkreq_n_pcc7"; - nvidia,function = "pcie"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - /* LAN i210/i211 SMB_ALERT_N (On-module) */ - sys-clk-req-pz5 { - nvidia,pins = "sys_clk_req_pz5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* LVDS Transceiver Configuration */ - pbb0 { - nvidia,pins = "pbb0", - "pbb7", - "pcc1", - "pcc2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pbb3 { - nvidia,pins = "pbb3", - "pbb4", - "pbb5", - "pbb6"; - nvidia,function = "displayb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Not connected and therefore disabled */ - clk-32k-out-pa0 { - nvidia,pins = "clk3_out_pee0", - "clk3_req_pee1", - "clk_32k_out_pa0", - "dap4_din_pp5", - "dap4_dout_pp6", - "dap4_fs_pp4", - "dap4_sclk_pp7"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap2-fs-pa2 { - nvidia,pins = "dap2_fs_pa2", - "dap2_sclk_pa3", - "dap2_din_pa4", - "dap2_dout_pa5", - "lcd_dc0_pn6", - "lcd_m1_pw1", - "lcd_pwr1_pc1", - "pex_l1_clkreq_n_pdd6", - "pex_l1_prsnt_n_pdd4", - "pex_l1_rst_n_pdd5"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi-ad0-pg0 { - nvidia,pins = "gmi_ad0_pg0", - "gmi_ad2_pg2", - "gmi_ad3_pg3", - "gmi_ad4_pg4", - "gmi_ad5_pg5", - "gmi_ad6_pg6", - "gmi_ad7_pg7", - "gmi_ad8_ph0", - "gmi_ad9_ph1", - "gmi_ad10_ph2", - "gmi_ad11_ph3", - "gmi_ad12_ph4", - "gmi_ad13_ph5", - "gmi_ad14_ph6", - "gmi_ad15_ph7", - "gmi_adv_n_pk0", - "gmi_clk_pk1", - "gmi_cs4_n_pk2", - "gmi_cs2_n_pk3", - "gmi_dqs_pi2", - "gmi_iordy_pi5", - "gmi_oe_n_pi1", - "gmi_wait_pi7", - "gmi_wr_n_pi0", - "lcd_cs1_n_pw0", - "pu0", - "pu1", - "pu2"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi-cs0-n-pj0 { - nvidia,pins = "gmi_cs0_n_pj0", - "gmi_cs1_n_pj2", - "gmi_cs3_n_pk4"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi-cs6-n-pi3 { - nvidia,pins = "gmi_cs6_n_pi3"; - nvidia,function = "sata"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi-cs7-n-pi6 { - nvidia,pins = "gmi_cs7_n_pi6"; - nvidia,function = "gmi_alt"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd-pwr0-pb2 { - nvidia,pins = "lcd_pwr0_pb2", - "lcd_pwr2_pc6", - "lcd_wr_n_pz3"; - nvidia,function = "hdcp"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2-cts-n-pj5 { - nvidia,pins = "uart2_cts_n_pj5", - "uart2_rts_n_pj6"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Power I2C (On-module) */ - pwr-i2c-scl-pz6 { - nvidia,pins = "pwr_i2c_scl_pz6", - "pwr_i2c_sda_pz7"; - nvidia,function = "i2cpwr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - - /* - * THERMD_ALERT#, unlatched I2C address pin of LM95245 - * temperature sensor therefore requires disabling for - * now - */ - lcd-dc1-pd2 { - nvidia,pins = "lcd_dc1_pd2"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* TOUCH_PEN_INT# (On-module) */ - pv0 { - nvidia,pins = "pv0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - }; - }; - - serial@70006040 { - compatible = "nvidia,tegra30-hsuart"; - }; - - serial@70006200 { - compatible = "nvidia,tegra30-hsuart"; - }; - - serial@70006300 { - compatible = "nvidia,tegra30-hsuart"; - }; - - hdmi_ddc: i2c@7000c700 { - clock-frequency = <10000>; - }; - - /* - * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and - * touch screen controller - */ - i2c@7000d000 { - status = "okay"; - clock-frequency = <100000>; - - /* SGTL5000 audio codec */ - sgtl5000: codec@a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - VDDA-supply = <®_module_3v3_audio>; - VDDD-supply = <®_1v8_vio>; - VDDIO-supply = <®_module_3v3>; - clocks = <&tegra_car TEGRA30_CLK_EXTERN1>; - }; - - pmic: pmic@2d { - compatible = "ti,tps65911"; - reg = <0x2d>; - - interrupts = ; - #interrupt-cells = <2>; - interrupt-controller; - - ti,system-power-controller; - - #gpio-cells = <2>; - gpio-controller; - - vcc1-supply = <®_module_3v3>; - vcc2-supply = <®_module_3v3>; - vcc3-supply = <®_1v8_vio>; - vcc4-supply = <®_module_3v3>; - vcc5-supply = <®_module_3v3>; - vcc6-supply = <®_1v8_vio>; - vcc7-supply = <®_5v0_charge_pump>; - vccio-supply = <®_module_3v3>; - - regulators { - vdd1_reg: vdd1 { - regulator-name = "+V1.35_VDDIO_DDR"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - }; - - vdd2_reg: vdd2 { - regulator-name = "+V1.05"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - }; - - vddctrl_reg: vddctrl { - regulator-name = "+V1.0_VDD_CPU"; - regulator-min-microvolt = <1150000>; - regulator-max-microvolt = <1150000>; - regulator-always-on; - }; - - reg_1v8_vio: vio { - regulator-name = "+V1.8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - /* LDO1: unused */ - - /* - * EN_+V3.3 switching via FET: - * +V3.3_AUDIO_AVDD_S, +V3.3 - * see also +V3.3 fixed supply - */ - ldo2_reg: ldo2 { - regulator-name = "EN_+V3.3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo3_reg: ldo3 { - regulator-name = "+V1.2_CSI"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - ldo4_reg: ldo4 { - regulator-name = "+V1.2_VDD_RTC"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - /* - * +V2.8_AVDD_VDAC: - * only required for (unsupported) analog RGB - */ - ldo5_reg: ldo5 { - regulator-name = "+V2.8_AVDD_VDAC"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - /* - * +V1.05_AVDD_PLLE: avdd_plle should be 1.05V - * but LDO6 can't set voltage in 50mV - * granularity - */ - ldo6_reg: ldo6 { - regulator-name = "+V1.05_AVDD_PLLE"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - }; - - ldo7_reg: ldo7 { - regulator-name = "+V1.2_AVDD_PLL"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - ldo8_reg: ldo8 { - regulator-name = "+V1.0_VDD_DDR_HS"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - }; - }; - - /* STMPE811 touch screen controller */ - touchscreen@41 { - compatible = "st,stmpe811"; - reg = <0x41>; - irq-gpio = <&gpio TEGRA_GPIO(V, 0) IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - id = <0>; - blocks = <0x5>; - irq-trigger = <0x1>; - /* 3.25 MHz ADC clock speed */ - st,adc-freq = <1>; - /* 12-bit ADC */ - st,mod-12b = <1>; - /* internal ADC reference */ - st,ref-sel = <0>; - /* ADC converstion time: 80 clocks */ - st,sample-time = <4>; - - stmpe_touchscreen { - compatible = "st,stmpe-ts"; - /* 8 sample average control */ - st,ave-ctrl = <3>; - /* 7 length fractional part in z */ - st,fraction-z = <7>; - /* - * 50 mA typical 80 mA max touchscreen drivers - * current limit value - */ - st,i-drive = <1>; - /* 1 ms panel driver settling time */ - st,settling = <3>; - /* 5 ms touch detect interrupt delay */ - st,touch-det-delay = <5>; - }; - - stmpe_adc { - compatible = "st,stmpe-adc"; - /* forbid to use ADC channels 3-0 (touch) */ - st,norequest-mask = <0x0F>; - }; - }; - - /* - * LM95245 temperature sensor - * Note: OVERT1# directly connected to TPS65911 PMIC PWRDN - */ - temp-sensor@4c { - compatible = "national,lm95245"; - reg = <0x4c>; - }; - - /* SW: +V1.2_VDD_CORE */ - regulator@60 { - compatible = "ti,tps62362"; - reg = <0x60>; - - regulator-name = "tps62362-vout"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1400000>; - regulator-boot-on; - regulator-always-on; - ti,vsel0-state-low; - /* VSEL1: EN_CORE_DVFS_N low for DVFS */ - ti,vsel1-state-low; - }; - }; - - /* SPI4: CAN2 */ - spi@7000da00 { - status = "okay"; - spi-max-frequency = <10000000>; - - can@1 { - compatible = "microchip,mcp2515"; - reg = <1>; - clocks = <&clk16m>; - interrupt-parent = <&gpio>; - interrupts = ; - spi-max-frequency = <10000000>; - }; - }; - - /* SPI6: CAN1 */ - spi@7000de00 { - status = "okay"; - spi-max-frequency = <10000000>; - - can@0 { - compatible = "microchip,mcp2515"; - reg = <0>; - clocks = <&clk16m>; - interrupt-parent = <&gpio>; - interrupts = ; - spi-max-frequency = <10000000>; - }; - }; - - pmc@7000e400 { - nvidia,invert-interrupt; - nvidia,suspend-mode = <1>; - nvidia,cpu-pwr-good-time = <5000>; - nvidia,cpu-pwr-off-time = <5000>; - nvidia,core-pwr-good-time = <3845 3845>; - nvidia,core-pwr-off-time = <0>; - nvidia,core-power-req-active-high; - nvidia,sys-clock-req-active-high; - - /* Set DEV_OFF bit in DCDC control register of TPS65911 PMIC */ - i2c-thermtrip { - nvidia,i2c-controller-id = <4>; - nvidia,bus-addr = <0x2d>; - nvidia,reg-addr = <0x3f>; - nvidia,reg-data = <0x1>; - }; - }; - - hda@70030000 { - status = "okay"; - }; - - ahub@70080000 { - i2s@70080500 { - status = "okay"; - }; - }; - - /* eMMC */ - sdhci@78000600 { - status = "okay"; - bus-width = <8>; - non-removable; - vmmc-supply = <®_module_3v3>; /* VCC */ - vqmmc-supply = <®_1v8_vio>; /* VCCQ */ - mmc-ddr-1_8v; - }; - - clk32k_in: xtal1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - - clk16m: osc4 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <16000000>; - }; - - reg_1v8_avdd_hdmi_pll: regulator-1v8-avdd-hdmi-pll { - compatible = "regulator-fixed"; - regulator-name = "+V1.8_AVDD_HDMI_PLL"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - enable-active-high; - gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; - vin-supply = <®_1v8_vio>; - }; - - reg_3v3_avdd_hdmi: regulator-3v3-avdd-hdmi { - compatible = "regulator-fixed"; - regulator-name = "+V3.3_AVDD_HDMI"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; - vin-supply = <®_module_3v3>; - }; - - reg_5v0_charge_pump: regulator-5v0-charge-pump { - compatible = "regulator-fixed"; - regulator-name = "+V5.0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - reg_module_3v3: regulator-module-3v3 { - compatible = "regulator-fixed"; - regulator-name = "+V3.3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_module_3v3_audio: regulator-module-3v3-audio { - compatible = "regulator-fixed"; - regulator-name = "+V3.3_AUDIO_AVDD_S"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - sound { - compatible = "toradex,tegra-audio-sgtl5000-apalis_t30", - "nvidia,tegra-audio-sgtl5000"; - nvidia,model = "Toradex Apalis T30"; - nvidia,audio-routing = - "Headphone Jack", "HP_OUT", - "LINE_IN", "Line In Jack", - "MIC_IN", "Mic Jack"; - nvidia,i2s-controller = <&tegra_i2s2>; - nvidia,audio-codec = <&sgtl5000>; - clocks = <&tegra_car TEGRA30_CLK_PLL_A>, - <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA30_CLK_EXTERN1>; - clock-names = "pll_a", "pll_a_out0", "mclk"; - }; -}; diff --git a/sys/gnu/dts/arm/tegra30-beaver.dts b/sys/gnu/dts/arm/tegra30-beaver.dts deleted file mode 100644 index a3b0f3555cd..00000000000 --- a/sys/gnu/dts/arm/tegra30-beaver.dts +++ /dev/null @@ -1,2117 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "tegra30.dtsi" - -/ { - model = "NVIDIA Tegra30 Beaver evaluation board"; - compatible = "nvidia,beaver", "nvidia,tegra30"; - - aliases { - rtc0 = "/i2c@7000d000/tps65911@2d"; - rtc1 = "/rtc@7000e000"; - serial0 = &uarta; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@80000000 { - reg = <0x80000000 0x7ff00000>; - }; - - pcie@3000 { - status = "okay"; - - avdd-pexa-supply = <&ldo1_reg>; - vdd-pexa-supply = <&ldo1_reg>; - avdd-pexb-supply = <&ldo1_reg>; - vdd-pexb-supply = <&ldo1_reg>; - avdd-pex-pll-supply = <&ldo1_reg>; - avdd-plle-supply = <&ldo1_reg>; - vddio-pex-ctl-supply = <&sys_3v3_reg>; - hvdd-pex-supply = <&sys_3v3_pexs_reg>; - - pci@1,0 { - status = "okay"; - nvidia,num-lanes = <2>; - }; - - pci@2,0 { - nvidia,num-lanes = <2>; - }; - - pci@3,0 { - status = "okay"; - nvidia,num-lanes = <2>; - }; - }; - - host1x@50000000 { - hdmi@54280000 { - status = "okay"; - - hdmi-supply = <&vdd_5v0_hdmi>; - vdd-supply = <&sys_3v3_reg>; - pll-supply = <&vio_reg>; - - nvidia,hpd-gpio = - <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; - nvidia,ddc-i2c-bus = <&hdmiddc>; - }; - }; - - pinmux@70000868 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - clk_32k_out_pa0 { - nvidia,pins = "clk_32k_out_pa0"; - nvidia,function = "blink"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart3_cts_n_pa1 { - nvidia,pins = "uart3_cts_n_pa1"; - nvidia,function = "uartc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap2_fs_pa2 { - nvidia,pins = "dap2_fs_pa2"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap2_sclk_pa3 { - nvidia,pins = "dap2_sclk_pa3"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap2_din_pa4 { - nvidia,pins = "dap2_din_pa4"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap2_dout_pa5 { - nvidia,pins = "dap2_dout_pa5"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_clk_pa6 { - nvidia,pins = "sdmmc3_clk_pa6"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_cmd_pa7 { - nvidia,pins = "sdmmc3_cmd_pa7"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_a17_pb0 { - nvidia,pins = "gmi_a17_pb0"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_a18_pb1 { - nvidia,pins = "gmi_a18_pb1"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_pwr0_pb2 { - nvidia,pins = "lcd_pwr0_pb2"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_pclk_pb3 { - nvidia,pins = "lcd_pclk_pb3"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_dat3_pb4 { - nvidia,pins = "sdmmc3_dat3_pb4"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_dat2_pb5 { - nvidia,pins = "sdmmc3_dat2_pb5"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_dat1_pb6 { - nvidia,pins = "sdmmc3_dat1_pb6"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_dat0_pb7 { - nvidia,pins = "sdmmc3_dat0_pb7"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart3_rts_n_pc0 { - nvidia,pins = "uart3_rts_n_pc0"; - nvidia,function = "uartc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_pwr1_pc1 { - nvidia,pins = "lcd_pwr1_pc1"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2_txd_pc2 { - nvidia,pins = "uart2_txd_pc2"; - nvidia,function = "uartb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2_rxd_pc3 { - nvidia,pins = "uart2_rxd_pc3"; - nvidia,function = "uartb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gen1_i2c_scl_pc4 { - nvidia,pins = "gen1_i2c_scl_pc4"; - nvidia,function = "i2c1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gen1_i2c_sda_pc5 { - nvidia,pins = "gen1_i2c_sda_pc5"; - nvidia,function = "i2c1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - lcd_pwr2_pc6 { - nvidia,pins = "lcd_pwr2_pc6"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_wp_n_pc7 { - nvidia,pins = "gmi_wp_n_pc7"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_dat5_pd0 { - nvidia,pins = "sdmmc3_dat5_pd0"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_dat4_pd1 { - nvidia,pins = "sdmmc3_dat4_pd1"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_dc1_pd2 { - nvidia,pins = "lcd_dc1_pd2"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_dat6_pd3 { - nvidia,pins = "sdmmc3_dat6_pd3"; - nvidia,function = "spdif"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_dat7_pd4 { - nvidia,pins = "sdmmc3_dat7_pd4"; - nvidia,function = "spdif"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi_d1_pd5 { - nvidia,pins = "vi_d1_pd5"; - nvidia,function = "sdmmc2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi_vsync_pd6 { - nvidia,pins = "vi_vsync_pd6"; - nvidia,function = "ddr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi_hsync_pd7 { - nvidia,pins = "vi_hsync_pd7"; - nvidia,function = "ddr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d0_pe0 { - nvidia,pins = "lcd_d0_pe0"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d1_pe1 { - nvidia,pins = "lcd_d1_pe1"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d2_pe2 { - nvidia,pins = "lcd_d2_pe2"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d3_pe3 { - nvidia,pins = "lcd_d3_pe3"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d4_pe4 { - nvidia,pins = "lcd_d4_pe4"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d5_pe5 { - nvidia,pins = "lcd_d5_pe5"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d6_pe6 { - nvidia,pins = "lcd_d6_pe6"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d7_pe7 { - nvidia,pins = "lcd_d7_pe7"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d8_pf0 { - nvidia,pins = "lcd_d8_pf0"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d9_pf1 { - nvidia,pins = "lcd_d9_pf1"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d10_pf2 { - nvidia,pins = "lcd_d10_pf2"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d11_pf3 { - nvidia,pins = "lcd_d11_pf3"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d12_pf4 { - nvidia,pins = "lcd_d12_pf4"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d13_pf5 { - nvidia,pins = "lcd_d13_pf5"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d14_pf6 { - nvidia,pins = "lcd_d14_pf6"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d15_pf7 { - nvidia,pins = "lcd_d15_pf7"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad0_pg0 { - nvidia,pins = "gmi_ad0_pg0"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad1_pg1 { - nvidia,pins = "gmi_ad1_pg1"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad2_pg2 { - nvidia,pins = "gmi_ad2_pg2"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad3_pg3 { - nvidia,pins = "gmi_ad3_pg3"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad4_pg4 { - nvidia,pins = "gmi_ad4_pg4"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad5_pg5 { - nvidia,pins = "gmi_ad5_pg5"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad6_pg6 { - nvidia,pins = "gmi_ad6_pg6"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad7_pg7 { - nvidia,pins = "gmi_ad7_pg7"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad8_ph0 { - nvidia,pins = "gmi_ad8_ph0"; - nvidia,function = "pwm0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad9_ph1 { - nvidia,pins = "gmi_ad9_ph1"; - nvidia,function = "pwm1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad10_ph2 { - nvidia,pins = "gmi_ad10_ph2"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad11_ph3 { - nvidia,pins = "gmi_ad11_ph3"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad12_ph4 { - nvidia,pins = "gmi_ad12_ph4"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad13_ph5 { - nvidia,pins = "gmi_ad13_ph5"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad14_ph6 { - nvidia,pins = "gmi_ad14_ph6"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_wr_n_pi0 { - nvidia,pins = "gmi_wr_n_pi0"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_oe_n_pi1 { - nvidia,pins = "gmi_oe_n_pi1"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_dqs_pi2 { - nvidia,pins = "gmi_dqs_pi2"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_iordy_pi5 { - nvidia,pins = "gmi_iordy_pi5"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_cs7_n_pi6 { - nvidia,pins = "gmi_cs7_n_pi6"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_wait_pi7 { - nvidia,pins = "gmi_wait_pi7"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_de_pj1 { - nvidia,pins = "lcd_de_pj1"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_hsync_pj3 { - nvidia,pins = "lcd_hsync_pj3"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_vsync_pj4 { - nvidia,pins = "lcd_vsync_pj4"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2_cts_n_pj5 { - nvidia,pins = "uart2_cts_n_pj5"; - nvidia,function = "uartb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2_rts_n_pj6 { - nvidia,pins = "uart2_rts_n_pj6"; - nvidia,function = "uartb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_a16_pj7 { - nvidia,pins = "gmi_a16_pj7"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_adv_n_pk0 { - nvidia,pins = "gmi_adv_n_pk0"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_clk_pk1 { - nvidia,pins = "gmi_clk_pk1"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_cs2_n_pk3 { - nvidia,pins = "gmi_cs2_n_pk3"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_cs3_n_pk4 { - nvidia,pins = "gmi_cs3_n_pk4"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - spdif_out_pk5 { - nvidia,pins = "spdif_out_pk5"; - nvidia,function = "spdif"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - spdif_in_pk6 { - nvidia,pins = "spdif_in_pk6"; - nvidia,function = "spdif"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_a19_pk7 { - nvidia,pins = "gmi_a19_pk7"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi_d2_pl0 { - nvidia,pins = "vi_d2_pl0"; - nvidia,function = "sdmmc2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi_d3_pl1 { - nvidia,pins = "vi_d3_pl1"; - nvidia,function = "sdmmc2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi_d4_pl2 { - nvidia,pins = "vi_d4_pl2"; - nvidia,function = "vi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi_d5_pl3 { - nvidia,pins = "vi_d5_pl3"; - nvidia,function = "sdmmc2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi_d6_pl4 { - nvidia,pins = "vi_d6_pl4"; - nvidia,function = "vi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi_d7_pl5 { - nvidia,pins = "vi_d7_pl5"; - nvidia,function = "sdmmc2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi_d8_pl6 { - nvidia,pins = "vi_d8_pl6"; - nvidia,function = "sdmmc2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi_d9_pl7 { - nvidia,pins = "vi_d9_pl7"; - nvidia,function = "sdmmc2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d16_pm0 { - nvidia,pins = "lcd_d16_pm0"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d17_pm1 { - nvidia,pins = "lcd_d17_pm1"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d18_pm2 { - nvidia,pins = "lcd_d18_pm2"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d19_pm3 { - nvidia,pins = "lcd_d19_pm3"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d20_pm4 { - nvidia,pins = "lcd_d20_pm4"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d21_pm5 { - nvidia,pins = "lcd_d21_pm5"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d22_pm6 { - nvidia,pins = "lcd_d22_pm6"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d23_pm7 { - nvidia,pins = "lcd_d23_pm7"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap1_fs_pn0 { - nvidia,pins = "dap1_fs_pn0"; - nvidia,function = "i2s0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap1_din_pn1 { - nvidia,pins = "dap1_din_pn1"; - nvidia,function = "i2s0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap1_dout_pn2 { - nvidia,pins = "dap1_dout_pn2"; - nvidia,function = "i2s0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap1_sclk_pn3 { - nvidia,pins = "dap1_sclk_pn3"; - nvidia,function = "i2s0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_cs0_n_pn4 { - nvidia,pins = "lcd_cs0_n_pn4"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_sdout_pn5 { - nvidia,pins = "lcd_sdout_pn5"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_dc0_pn6 { - nvidia,pins = "lcd_dc0_pn6"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - hdmi_int_pn7 { - nvidia,pins = "hdmi_int_pn7"; - nvidia,function = "hdmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data7_po0 { - nvidia,pins = "ulpi_data7_po0"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data0_po1 { - nvidia,pins = "ulpi_data0_po1"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data1_po2 { - nvidia,pins = "ulpi_data1_po2"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data2_po3 { - nvidia,pins = "ulpi_data2_po3"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data3_po4 { - nvidia,pins = "ulpi_data3_po4"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data4_po5 { - nvidia,pins = "ulpi_data4_po5"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data5_po6 { - nvidia,pins = "ulpi_data5_po6"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data6_po7 { - nvidia,pins = "ulpi_data6_po7"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3_fs_pp0 { - nvidia,pins = "dap3_fs_pp0"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3_din_pp1 { - nvidia,pins = "dap3_din_pp1"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3_dout_pp2 { - nvidia,pins = "dap3_dout_pp2"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3_sclk_pp3 { - nvidia,pins = "dap3_sclk_pp3"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap4_fs_pp4 { - nvidia,pins = "dap4_fs_pp4"; - nvidia,function = "i2s3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap4_din_pp5 { - nvidia,pins = "dap4_din_pp5"; - nvidia,function = "i2s3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap4_dout_pp6 { - nvidia,pins = "dap4_dout_pp6"; - nvidia,function = "i2s3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap4_sclk_pp7 { - nvidia,pins = "dap4_sclk_pp7"; - nvidia,function = "i2s3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col0_pq0 { - nvidia,pins = "kb_col0_pq0"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col1_pq1 { - nvidia,pins = "kb_col1_pq1"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col2_pq2 { - nvidia,pins = "kb_col2_pq2"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col3_pq3 { - nvidia,pins = "kb_col3_pq3"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col4_pq4 { - nvidia,pins = "kb_col4_pq4"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col5_pq5 { - nvidia,pins = "kb_col5_pq5"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col6_pq6 { - nvidia,pins = "kb_col6_pq6"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col7_pq7 { - nvidia,pins = "kb_col7_pq7"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row0_pr0 { - nvidia,pins = "kb_row0_pr0"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row1_pr1 { - nvidia,pins = "kb_row1_pr1"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row2_pr2 { - nvidia,pins = "kb_row2_pr2"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row3_pr3 { - nvidia,pins = "kb_row3_pr3"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row4_pr4 { - nvidia,pins = "kb_row4_pr4"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row5_pr5 { - nvidia,pins = "kb_row5_pr5"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row6_pr6 { - nvidia,pins = "kb_row6_pr6"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row7_pr7 { - nvidia,pins = "kb_row7_pr7"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row8_ps0 { - nvidia,pins = "kb_row8_ps0"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row9_ps1 { - nvidia,pins = "kb_row9_ps1"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row10_ps2 { - nvidia,pins = "kb_row10_ps2"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row11_ps3 { - nvidia,pins = "kb_row11_ps3"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row12_ps4 { - nvidia,pins = "kb_row12_ps4"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row13_ps5 { - nvidia,pins = "kb_row13_ps5"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row14_ps6 { - nvidia,pins = "kb_row14_ps6"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row15_ps7 { - nvidia,pins = "kb_row15_ps7"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi_pclk_pt0 { - nvidia,pins = "vi_pclk_pt0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi_mclk_pt1 { - nvidia,pins = "vi_mclk_pt1"; - nvidia,function = "vi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi_d10_pt2 { - nvidia,pins = "vi_d10_pt2"; - nvidia,function = "ddr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi_d11_pt3 { - nvidia,pins = "vi_d11_pt3"; - nvidia,function = "ddr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi_d0_pt4 { - nvidia,pins = "vi_d0_pt4"; - nvidia,function = "ddr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gen2_i2c_scl_pt5 { - nvidia,pins = "gen2_i2c_scl_pt5"; - nvidia,function = "i2c2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gen2_i2c_sda_pt6 { - nvidia,pins = "gen2_i2c_sda_pt6"; - nvidia,function = "i2c2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc4_cmd_pt7 { - nvidia,pins = "sdmmc4_cmd_pt7"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu0 { - nvidia,pins = "pu0"; - nvidia,function = "owr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu1 { - nvidia,pins = "pu1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu2 { - nvidia,pins = "pu2"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu3 { - nvidia,pins = "pu3"; - nvidia,function = "pwm0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu4 { - nvidia,pins = "pu4"; - nvidia,function = "pwm1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu5 { - nvidia,pins = "pu5"; - nvidia,function = "pwm2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu6 { - nvidia,pins = "pu6"; - nvidia,function = "pwm3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - jtag_rtck_pu7 { - nvidia,pins = "jtag_rtck_pu7"; - nvidia,function = "rtck"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pv0 { - nvidia,pins = "pv0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pv2 { - nvidia,pins = "pv2"; - nvidia,function = "owr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pv3 { - nvidia,pins = "pv3"; - nvidia,function = "clk_12m_out"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ddc_scl_pv4 { - nvidia,pins = "ddc_scl_pv4"; - nvidia,function = "i2c4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ddc_sda_pv5 { - nvidia,pins = "ddc_sda_pv5"; - nvidia,function = "i2c4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - crt_hsync_pv6 { - nvidia,pins = "crt_hsync_pv6"; - nvidia,function = "crt"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - crt_vsync_pv7 { - nvidia,pins = "crt_vsync_pv7"; - nvidia,function = "crt"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_cs1_n_pw0 { - nvidia,pins = "lcd_cs1_n_pw0"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_m1_pw1 { - nvidia,pins = "lcd_m1_pw1"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - spi2_cs1_n_pw2 { - nvidia,pins = "spi2_cs1_n_pw2"; - nvidia,function = "spi2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk1_out_pw4 { - nvidia,pins = "clk1_out_pw4"; - nvidia,function = "extperiph1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk2_out_pw5 { - nvidia,pins = "clk2_out_pw5"; - nvidia,function = "extperiph2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart3_txd_pw6 { - nvidia,pins = "uart3_txd_pw6"; - nvidia,function = "uartc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart3_rxd_pw7 { - nvidia,pins = "uart3_rxd_pw7"; - nvidia,function = "uartc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - spi2_sck_px2 { - nvidia,pins = "spi2_sck_px2"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - spi1_mosi_px4 { - nvidia,pins = "spi1_mosi_px4"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - spi1_sck_px5 { - nvidia,pins = "spi1_sck_px5"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - spi1_cs0_n_px6 { - nvidia,pins = "spi1_cs0_n_px6"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - spi1_miso_px7 { - nvidia,pins = "spi1_miso_px7"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_clk_py0 { - nvidia,pins = "ulpi_clk_py0"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_dir_py1 { - nvidia,pins = "ulpi_dir_py1"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_nxt_py2 { - nvidia,pins = "ulpi_nxt_py2"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_stp_py3 { - nvidia,pins = "ulpi_stp_py3"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_dat3_py4 { - nvidia,pins = "sdmmc1_dat3_py4"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_dat2_py5 { - nvidia,pins = "sdmmc1_dat2_py5"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_dat1_py6 { - nvidia,pins = "sdmmc1_dat1_py6"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_dat0_py7 { - nvidia,pins = "sdmmc1_dat0_py7"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_clk_pz0 { - nvidia,pins = "sdmmc1_clk_pz0"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_cmd_pz1 { - nvidia,pins = "sdmmc1_cmd_pz1"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_sdin_pz2 { - nvidia,pins = "lcd_sdin_pz2"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_wr_n_pz3 { - nvidia,pins = "lcd_wr_n_pz3"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_sck_pz4 { - nvidia,pins = "lcd_sck_pz4"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sys_clk_req_pz5 { - nvidia,pins = "sys_clk_req_pz5"; - nvidia,function = "sysclk"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pwr_i2c_scl_pz6 { - nvidia,pins = "pwr_i2c_scl_pz6"; - nvidia,function = "i2cpwr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pwr_i2c_sda_pz7 { - nvidia,pins = "pwr_i2c_sda_pz7"; - nvidia,function = "i2cpwr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc4_dat0_paa0 { - nvidia,pins = "sdmmc4_dat0_paa0"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_dat1_paa1 { - nvidia,pins = "sdmmc4_dat1_paa1"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_dat2_paa2 { - nvidia,pins = "sdmmc4_dat2_paa2"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_dat3_paa3 { - nvidia,pins = "sdmmc4_dat3_paa3"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_dat4_paa4 { - nvidia,pins = "sdmmc4_dat4_paa4"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_dat5_paa5 { - nvidia,pins = "sdmmc4_dat5_paa5"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_dat6_paa6 { - nvidia,pins = "sdmmc4_dat6_paa6"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_dat7_paa7 { - nvidia,pins = "sdmmc4_dat7_paa7"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pbb0 { - nvidia,pins = "pbb0"; - nvidia,function = "i2s4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - cam_i2c_scl_pbb1 { - nvidia,pins = "cam_i2c_scl_pbb1"; - nvidia,function = "i2c3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam_i2c_sda_pbb2 { - nvidia,pins = "cam_i2c_sda_pbb2"; - nvidia,function = "i2c3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pbb3 { - nvidia,pins = "pbb3"; - nvidia,function = "vgp3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pbb4 { - nvidia,pins = "pbb4"; - nvidia,function = "vgp4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pbb5 { - nvidia,pins = "pbb5"; - nvidia,function = "vgp5"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pbb6 { - nvidia,pins = "pbb6"; - nvidia,function = "vgp6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pbb7 { - nvidia,pins = "pbb7"; - nvidia,function = "i2s4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - cam_mclk_pcc0 { - nvidia,pins = "cam_mclk_pcc0"; - nvidia,function = "vi_alt3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pcc1 { - nvidia,pins = "pcc1"; - nvidia,function = "i2s4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pcc2 { - nvidia,pins = "pcc2"; - nvidia,function = "i2s4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_rst_n_pcc3 { - nvidia,pins = "sdmmc4_rst_n_pcc3"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_clk_pcc4 { - nvidia,pins = "sdmmc4_clk_pcc4"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk2_req_pcc5 { - nvidia,pins = "clk2_req_pcc5"; - nvidia,function = "dap"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex_l2_rst_n_pcc6 { - nvidia,pins = "pex_l2_rst_n_pcc6"; - nvidia,function = "pcie"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex_l2_clkreq_n_pcc7 { - nvidia,pins = "pex_l2_clkreq_n_pcc7"; - nvidia,function = "pcie"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex_l0_prsnt_n_pdd0 { - nvidia,pins = "pex_l0_prsnt_n_pdd0"; - nvidia,function = "pcie"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex_l0_rst_n_pdd1 { - nvidia,pins = "pex_l0_rst_n_pdd1"; - nvidia,function = "pcie"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex_l0_clkreq_n_pdd2 { - nvidia,pins = "pex_l0_clkreq_n_pdd2"; - nvidia,function = "pcie"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex_wake_n_pdd3 { - nvidia,pins = "pex_wake_n_pdd3"; - nvidia,function = "pcie"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex_l1_prsnt_n_pdd4 { - nvidia,pins = "pex_l1_prsnt_n_pdd4"; - nvidia,function = "pcie"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex_l1_rst_n_pdd5 { - nvidia,pins = "pex_l1_rst_n_pdd5"; - nvidia,function = "pcie"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex_l1_clkreq_n_pdd6 { - nvidia,pins = "pex_l1_clkreq_n_pdd6"; - nvidia,function = "pcie"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex_l2_prsnt_n_pdd7 { - nvidia,pins = "pex_l2_prsnt_n_pdd7"; - nvidia,function = "pcie"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk3_out_pee0 { - nvidia,pins = "clk3_out_pee0"; - nvidia,function = "extperiph3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk3_req_pee1 { - nvidia,pins = "clk3_req_pee1"; - nvidia,function = "dev3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk1_req_pee2 { - nvidia,pins = "clk1_req_pee2"; - nvidia,function = "dap"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - hdmi_cec_pee3 { - nvidia,pins = "hdmi_cec_pee3"; - nvidia,function = "cec"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - owr { - nvidia,pins = "owr"; - nvidia,function = "owr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdio3 { - nvidia,pins = "drive_sdio3"; - nvidia,high-speed-mode = ; - nvidia,schmitt = ; - nvidia,pull-down-strength = <46>; - nvidia,pull-up-strength = <42>; - nvidia,slew-rate-rising = <1>; - nvidia,slew-rate-falling = <1>; - }; - gpv { - nvidia,pins = "drive_gpv"; - nvidia,pull-up-strength = <16>; - }; - }; - }; - - serial@70006000 { - status = "okay"; - }; - - i2c@7000c000 { - status = "okay"; - clock-frequency = <100000>; - }; - - i2c@7000c400 { - status = "okay"; - clock-frequency = <100000>; - }; - - i2c@7000c500 { - status = "okay"; - clock-frequency = <100000>; - }; - - hdmiddc: i2c@7000c700 { - status = "okay"; - clock-frequency = <100000>; - }; - - i2c@7000d000 { - status = "okay"; - clock-frequency = <100000>; - - rt5640: rt5640@1c { - compatible = "realtek,rt5640"; - reg = <0x1c>; - interrupt-parent = <&gpio>; - interrupts = ; - realtek,ldo1-en-gpios = - <&gpio TEGRA_GPIO(X, 2) GPIO_ACTIVE_HIGH>; - }; - - pmic: tps65911@2d { - compatible = "ti,tps65911"; - reg = <0x2d>; - - interrupts = ; - #interrupt-cells = <2>; - interrupt-controller; - - ti,system-power-controller; - - #gpio-cells = <2>; - gpio-controller; - - vcc1-supply = <&vdd_5v_in_reg>; - vcc2-supply = <&vdd_5v_in_reg>; - vcc3-supply = <&vio_reg>; - vcc4-supply = <&vdd_5v_in_reg>; - vcc5-supply = <&vdd_5v_in_reg>; - vcc6-supply = <&vdd2_reg>; - vcc7-supply = <&vdd_5v_in_reg>; - vccio-supply = <&vdd_5v_in_reg>; - - regulators { - vdd1_reg: vdd1 { - regulator-name = "vddio_ddr_1v2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - vdd2_reg: vdd2 { - regulator-name = "vdd_1v5_gen"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - }; - - vddctrl_reg: vddctrl { - regulator-name = "vdd_cpu,vdd_sys"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - vio_reg: vio { - regulator-name = "vdd_1v8_gen"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo1_reg: ldo1 { - regulator-name = "vdd_pexa,vdd_pexb"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - }; - - ldo2_reg: ldo2 { - regulator-name = "vdd_sata,avdd_plle"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - }; - - /* LDO3 is not connected to anything */ - - ldo4_reg: ldo4 { - regulator-name = "vdd_rtc"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - ldo5_reg: ldo5 { - regulator-name = "vddio_sdmmc,avdd_vdac"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo6_reg: ldo6 { - regulator-name = "avdd_dsi_csi,pwrdet_mipi"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - ldo7_reg: ldo7 { - regulator-name = "vdd_pllm,x,u,a_p_c_s"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - ldo8_reg: ldo8 { - regulator-name = "vdd_ddr_hs"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - }; - }; - - tps62361@60 { - compatible = "ti,tps62361"; - reg = <0x60>; - - regulator-name = "tps62361-vout"; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - regulator-always-on; - ti,vsel0-state-high; - ti,vsel1-state-high; - }; - }; - - spi@7000da00 { - status = "okay"; - spi-max-frequency = <25000000>; - spi-flash@1 { - compatible = "winbond,w25q32", "jedec,spi-nor"; - reg = <1>; - spi-max-frequency = <20000000>; - }; - }; - - pmc@7000e400 { - status = "okay"; - nvidia,invert-interrupt; - nvidia,suspend-mode = <1>; - nvidia,cpu-pwr-good-time = <2000>; - nvidia,cpu-pwr-off-time = <200>; - nvidia,core-pwr-good-time = <3845 3845>; - nvidia,core-pwr-off-time = <0>; - nvidia,core-power-req-active-high; - nvidia,sys-clock-req-active-high; - }; - - ahub@70080000 { - i2s@70080400 { - status = "okay"; - }; - }; - - sdhci@78000000 { - status = "okay"; - vqmmc-supply = <&ldo5_reg>; - cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>; - power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>; - bus-width = <4>; - }; - - sdhci@78000600 { - status = "okay"; - bus-width = <8>; - non-removable; - }; - - usb@7d000000 { - compatible = "nvidia,tegra30-udc"; - status = "okay"; - dr_mode = "peripheral"; - }; - - usb-phy@7d000000 { - status = "okay"; - }; - - usb@7d004000 { - status = "okay"; - }; - - phy2: usb-phy@7d004000 { - vbus-supply = <&sys_3v3_reg>; - status = "okay"; - }; - - usb@7d008000 { - status = "okay"; - }; - - usb-phy@7d008000 { - vbus-supply = <&usb3_vbus_reg>; - status = "okay"; - }; - - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - gpled1 { - label = "LED1"; /* CR5A1 (blue) */ - gpios = <&gpio TEGRA_GPIO(L, 1) GPIO_ACTIVE_HIGH>; - }; - gpled2 { - label = "LED2"; /* CR4A2 (green) */ - gpios = <&gpio TEGRA_GPIO(L, 0) GPIO_ACTIVE_HIGH>; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - vdd_5v_in_reg: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "vdd_5v_in"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - chargepump_5v_reg: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "chargepump_5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - regulator-always-on; - enable-active-high; - gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; - }; - - ddr_reg: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "vdd_ddr"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&pmic 7 GPIO_ACTIVE_HIGH>; - vin-supply = <&vdd_5v_in_reg>; - }; - - vdd_5v_sata_reg: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "vdd_5v_sata"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(D, 6) GPIO_ACTIVE_HIGH>; - vin-supply = <&vdd_5v_in_reg>; - }; - - usb1_vbus_reg: regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "usb1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(DD, 6) GPIO_ACTIVE_HIGH>; - gpio-open-drain; - vin-supply = <&vdd_5v_in_reg>; - }; - - usb3_vbus_reg: regulator@5 { - compatible = "regulator-fixed"; - reg = <5>; - regulator-name = "usb3_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(DD, 4) GPIO_ACTIVE_HIGH>; - gpio-open-drain; - vin-supply = <&vdd_5v_in_reg>; - }; - - sys_3v3_reg: regulator@6 { - compatible = "regulator-fixed"; - reg = <6>; - regulator-name = "sys_3v3,vdd_3v3_alw"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; - vin-supply = <&vdd_5v_in_reg>; - }; - - sys_3v3_pexs_reg: regulator@7 { - compatible = "regulator-fixed"; - reg = <7>; - regulator-name = "sys_3v3_pexs"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(L, 7) GPIO_ACTIVE_HIGH>; - vin-supply = <&sys_3v3_reg>; - }; - - vdd_5v0_hdmi: regulator@8 { - compatible = "regulator-fixed"; - reg = <8>; - regulator-name = "+VDD_5V_HDMI"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&sys_3v3_reg>; - }; - }; - - sound { - compatible = "nvidia,tegra-audio-rt5640-beaver", - "nvidia,tegra-audio-rt5640"; - nvidia,model = "NVIDIA Tegra Beaver"; - - nvidia,audio-routing = - "Headphones", "HPOR", - "Headphones", "HPOL", - "Mic Jack", "MICBIAS1", - "IN2P", "Mic Jack"; - - nvidia,i2s-controller = <&tegra_i2s1>; - nvidia,audio-codec = <&rt5640>; - - nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>; - - clocks = <&tegra_car TEGRA30_CLK_PLL_A>, - <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA30_CLK_EXTERN1>; - clock-names = "pll_a", "pll_a_out0", "mclk"; - }; -}; diff --git a/sys/gnu/dts/arm/tegra30-cardhu-a02.dts b/sys/gnu/dts/arm/tegra30-cardhu-a02.dts deleted file mode 100644 index a02ec508228..00000000000 --- a/sys/gnu/dts/arm/tegra30-cardhu-a02.dts +++ /dev/null @@ -1,95 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "tegra30-cardhu.dtsi" - -/* This dts file support the cardhu A02 version of board */ - -/ { - model = "NVIDIA Tegra30 Cardhu A02 evaluation board"; - compatible = "nvidia,cardhu-a02", "nvidia,cardhu", "nvidia,tegra30"; - - sdhci@78000400 { - status = "okay"; - power-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>; - bus-width = <4>; - keep-power-in-suspend; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - ddr_reg: regulator@100 { - compatible = "regulator-fixed"; - reg = <100>; - regulator-name = "vdd_ddr"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; - }; - - sys_3v3_reg: regulator@101 { - compatible = "regulator-fixed"; - reg = <101>; - regulator-name = "sys_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&pmic 7 GPIO_ACTIVE_HIGH>; - }; - - usb1_vbus_reg: regulator@102 { - compatible = "regulator-fixed"; - reg = <102>; - regulator-name = "usb1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(I, 4) GPIO_ACTIVE_HIGH>; - gpio-open-drain; - vin-supply = <&vdd_5v0_reg>; - }; - - usb3_vbus_reg: regulator@103 { - compatible = "regulator-fixed"; - reg = <103>; - regulator-name = "usb3_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_HIGH>; - gpio-open-drain; - vin-supply = <&vdd_5v0_reg>; - }; - - vdd_5v0_reg: regulator@104 { - compatible = "regulator-fixed"; - reg = <104>; - regulator-name = "5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; - }; - - vdd_bl_reg: regulator@105 { - compatible = "regulator-fixed"; - reg = <105>; - regulator-name = "vdd_bl"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(K, 3) GPIO_ACTIVE_HIGH>; - }; - }; -}; - diff --git a/sys/gnu/dts/arm/tegra30-cardhu-a04.dts b/sys/gnu/dts/arm/tegra30-cardhu-a04.dts deleted file mode 100644 index 9234988624e..00000000000 --- a/sys/gnu/dts/arm/tegra30-cardhu-a04.dts +++ /dev/null @@ -1,154 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "tegra30-cardhu.dtsi" -#include "tegra30-cpu-opp.dtsi" -#include "tegra30-cpu-opp-microvolt.dtsi" - -/* This dts file support the cardhu A04 and later versions of board */ - -/ { - model = "NVIDIA Tegra30 Cardhu A04 (A05, A06, A07) evaluation board"; - compatible = "nvidia,cardhu-a04", "nvidia,cardhu", "nvidia,tegra30"; - - sdhci@78000400 { - status = "okay"; - power-gpios = <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_HIGH>; - bus-width = <4>; - keep-power-in-suspend; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - ddr_reg: regulator@100 { - compatible = "regulator-fixed"; - regulator-name = "ddr"; - reg = <100>; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&pmic 7 GPIO_ACTIVE_HIGH>; - }; - - sys_3v3_reg: regulator@101 { - compatible = "regulator-fixed"; - reg = <101>; - regulator-name = "sys_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; - }; - - usb1_vbus_reg: regulator@102 { - compatible = "regulator-fixed"; - reg = <102>; - regulator-name = "usb1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(DD, 6) GPIO_ACTIVE_HIGH>; - gpio-open-drain; - vin-supply = <&vdd_5v0_reg>; - }; - - usb3_vbus_reg: regulator@103 { - compatible = "regulator-fixed"; - reg = <103>; - regulator-name = "usb3_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(DD, 4) GPIO_ACTIVE_HIGH>; - gpio-open-drain; - vin-supply = <&vdd_5v0_reg>; - }; - - vdd_5v0_reg: regulator@104 { - compatible = "regulator-fixed"; - reg = <104>; - regulator-name = "5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&pmic 8 GPIO_ACTIVE_HIGH>; - }; - - vdd_bl_reg: regulator@105 { - compatible = "regulator-fixed"; - reg = <105>; - regulator-name = "vdd_bl"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(DD, 2) GPIO_ACTIVE_HIGH>; - }; - - vdd_bl2_reg: regulator@106 { - compatible = "regulator-fixed"; - reg = <106>; - regulator-name = "vdd_bl2"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(DD, 0) GPIO_ACTIVE_HIGH>; - }; - }; - - i2c@7000d000 { - pmic: tps65911@2d { - regulators { - vddctrl_reg: vddctrl { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1125000>; - regulator-coupled-with = <&vddcore_reg>; - regulator-coupled-max-spread = <300000>; - regulator-max-step-microvolt = <100000>; - - nvidia,tegra-cpu-regulator; - }; - }; - }; - - vddcore_reg: tps62361@60 { - regulator-coupled-with = <&vddctrl_reg>; - regulator-coupled-max-spread = <300000>; - regulator-max-step-microvolt = <100000>; - - nvidia,tegra-core-regulator; - }; - }; - - cpus { - cpu0: cpu@0 { - cpu-supply = <&vddctrl_reg>; - operating-points-v2 = <&cpu0_opp_table>; - }; - - cpu@1 { - cpu-supply = <&vddctrl_reg>; - operating-points-v2 = <&cpu0_opp_table>; - }; - - cpu@2 { - cpu-supply = <&vddctrl_reg>; - operating-points-v2 = <&cpu0_opp_table>; - }; - - cpu@3 { - cpu-supply = <&vddctrl_reg>; - operating-points-v2 = <&cpu0_opp_table>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/tegra30-cardhu.dtsi b/sys/gnu/dts/arm/tegra30-cardhu.dtsi deleted file mode 100644 index 7ce61edd52f..00000000000 --- a/sys/gnu/dts/arm/tegra30-cardhu.dtsi +++ /dev/null @@ -1,652 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include -#include "tegra30.dtsi" - -/** - * This file contains common DT entry for all fab version of Cardhu. - * There is multiple fab version of Cardhu starting from A01 to A07. - * Cardhu fab version A01 and A03 are not supported. Cardhu fab version - * A02 will have different sets of GPIOs for fixed regulator compare to - * Cardhu fab version A04. The Cardhu fab version A05, A06, A07 are - * compatible with fab version A04. Based on Cardhu fab version, the - * related dts file need to be chosen like for Cardhu fab version A02, - * use tegra30-cardhu-a02.dts, Cardhu fab version A04 and later, use - * tegra30-cardhu-a04.dts. - * The identification of board is done in two ways, by looking the sticker - * on PCB and by reading board id eeprom. - * The sticker will have number like 600-81291-1000-002 C.3. In this 4th - * number is the fab version like here it is 002 and hence fab version A02. - * The (downstream internal) U-Boot of Cardhu display the board-id as - * follows: - * BoardID: 0C5B, SKU: 0A01, Fab: 02, Rev: 45.00 - * In this Fab version is 02 i.e. A02. - * The BoardID I2C eeprom is interfaced through i2c5 (pwr_i2c address 0x56). - * The location 0x8 of this eeprom contains the Fab version. It is 1 byte - * wide. - */ - -/ { - model = "NVIDIA Tegra30 Cardhu evaluation board"; - compatible = "nvidia,cardhu", "nvidia,tegra30"; - - aliases { - rtc0 = "/i2c@7000d000/tps65911@2d"; - rtc1 = "/rtc@7000e000"; - serial0 = &uarta; - serial1 = &uartc; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@80000000 { - reg = <0x80000000 0x40000000>; - }; - - pcie@3000 { - status = "okay"; - - /* AVDD_PEXA and VDD_PEXA inputs are grounded on Cardhu. */ - avdd-pexb-supply = <&ldo1_reg>; - vdd-pexb-supply = <&ldo1_reg>; - avdd-pex-pll-supply = <&ldo1_reg>; - hvdd-pex-supply = <&pex_hvdd_3v3_reg>; - vddio-pex-ctl-supply = <&sys_3v3_reg>; - avdd-plle-supply = <&ldo2_reg>; - - pci@1,0 { - nvidia,num-lanes = <4>; - }; - - pci@2,0 { - nvidia,num-lanes = <1>; - }; - - pci@3,0 { - status = "okay"; - nvidia,num-lanes = <1>; - }; - }; - - host1x@50000000 { - dc@54200000 { - rgb { - status = "okay"; - - nvidia,panel = <&panel>; - }; - }; - }; - - pinmux@70000868 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - sdmmc1_clk_pz0 { - nvidia,pins = "sdmmc1_clk_pz0"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - }; - sdmmc1_cmd_pz1 { - nvidia,pins = "sdmmc1_cmd_pz1", - "sdmmc1_dat0_py7", - "sdmmc1_dat1_py6", - "sdmmc1_dat2_py5", - "sdmmc1_dat3_py4"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - }; - sdmmc3_clk_pa6 { - nvidia,pins = "sdmmc3_clk_pa6"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - }; - sdmmc3_cmd_pa7 { - nvidia,pins = "sdmmc3_cmd_pa7", - "sdmmc3_dat0_pb7", - "sdmmc3_dat1_pb6", - "sdmmc3_dat2_pb5", - "sdmmc3_dat3_pb4"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - }; - sdmmc4_clk_pcc4 { - nvidia,pins = "sdmmc4_clk_pcc4", - "sdmmc4_rst_n_pcc3"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - }; - sdmmc4_dat0_paa0 { - nvidia,pins = "sdmmc4_dat0_paa0", - "sdmmc4_dat1_paa1", - "sdmmc4_dat2_paa2", - "sdmmc4_dat3_paa3", - "sdmmc4_dat4_paa4", - "sdmmc4_dat5_paa5", - "sdmmc4_dat6_paa6", - "sdmmc4_dat7_paa7"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - }; - dap2_fs_pa2 { - nvidia,pins = "dap2_fs_pa2", - "dap2_sclk_pa3", - "dap2_din_pa4", - "dap2_dout_pa5"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - }; - sdio3 { - nvidia,pins = "drive_sdio3"; - nvidia,high-speed-mode = ; - nvidia,schmitt = ; - nvidia,pull-down-strength = <46>; - nvidia,pull-up-strength = <42>; - nvidia,slew-rate-rising = ; - nvidia,slew-rate-falling = ; - }; - uart3_txd_pw6 { - nvidia,pins = "uart3_txd_pw6", - "uart3_cts_n_pa1", - "uart3_rts_n_pc0", - "uart3_rxd_pw7"; - nvidia,function = "uartc"; - nvidia,pull = ; - nvidia,tristate = ; - }; - }; - }; - - serial@70006000 { - status = "okay"; - }; - - serial@70006200 { - compatible = "nvidia,tegra30-hsuart"; - status = "okay"; - }; - - pwm@7000a000 { - status = "okay"; - }; - - panelddc: i2c@7000c000 { - status = "okay"; - clock-frequency = <100000>; - }; - - i2c@7000c400 { - status = "okay"; - clock-frequency = <100000>; - }; - - i2c@7000c500 { - status = "okay"; - clock-frequency = <100000>; - - /* ALS and Proximity sensor */ - isl29028@44 { - compatible = "isil,isl29028"; - reg = <0x44>; - interrupt-parent = <&gpio>; - interrupts = ; - }; - - i2cmux@70 { - compatible = "nxp,pca9546"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x70>; - reset-gpio = <&gpio TEGRA_GPIO(BB, 0) GPIO_ACTIVE_LOW>; - }; - }; - - i2c@7000c700 { - status = "okay"; - clock-frequency = <100000>; - }; - - i2c@7000d000 { - status = "okay"; - clock-frequency = <100000>; - - wm8903: wm8903@1a { - compatible = "wlf,wm8903"; - reg = <0x1a>; - interrupt-parent = <&gpio>; - interrupts = ; - - gpio-controller; - #gpio-cells = <2>; - - micdet-cfg = <0>; - micdet-delay = <100>; - gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>; - }; - - pmic: tps65911@2d { - compatible = "ti,tps65911"; - reg = <0x2d>; - - interrupts = ; - #interrupt-cells = <2>; - interrupt-controller; - - ti,system-power-controller; - - #gpio-cells = <2>; - gpio-controller; - - vcc1-supply = <&vdd_ac_bat_reg>; - vcc2-supply = <&vdd_ac_bat_reg>; - vcc3-supply = <&vio_reg>; - vcc4-supply = <&vdd_5v0_reg>; - vcc5-supply = <&vdd_ac_bat_reg>; - vcc6-supply = <&vdd2_reg>; - vcc7-supply = <&vdd_ac_bat_reg>; - vccio-supply = <&vdd_ac_bat_reg>; - - regulators { - vdd1_reg: vdd1 { - regulator-name = "vddio_ddr_1v2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - vdd2_reg: vdd2 { - regulator-name = "vdd_1v5_gen"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - }; - - vddctrl_reg: vddctrl { - regulator-name = "vdd_cpu,vdd_sys"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - vio_reg: vio { - regulator-name = "vdd_1v8_gen"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo1_reg: ldo1 { - regulator-name = "vdd_pexa,vdd_pexb"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - }; - - ldo2_reg: ldo2 { - regulator-name = "vdd_sata,avdd_plle"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - }; - - /* LDO3 is not connected to anything */ - - ldo4_reg: ldo4 { - regulator-name = "vdd_rtc"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - ldo5_reg: ldo5 { - regulator-name = "vddio_sdmmc,avdd_vdac"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo6_reg: ldo6 { - regulator-name = "avdd_dsi_csi,pwrdet_mipi"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - ldo7_reg: ldo7 { - regulator-name = "vdd_pllm,x,u,a_p_c_s"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - ldo8_reg: ldo8 { - regulator-name = "vdd_ddr_hs"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - }; - }; - - temperature-sensor@4c { - compatible = "onnn,nct1008"; - reg = <0x4c>; - vcc-supply = <&sys_3v3_reg>; - interrupt-parent = <&gpio>; - interrupts = ; - }; - - tps62361@60 { - compatible = "ti,tps62361"; - reg = <0x60>; - - regulator-name = "tps62361-vout"; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - regulator-always-on; - ti,vsel0-state-high; - ti,vsel1-state-high; - }; - }; - - spi@7000da00 { - status = "okay"; - spi-max-frequency = <25000000>; - spi-flash@1 { - compatible = "winbond,w25q32", "jedec,spi-nor"; - reg = <1>; - spi-max-frequency = <20000000>; - }; - }; - - pmc@7000e400 { - status = "okay"; - nvidia,invert-interrupt; - nvidia,suspend-mode = <1>; - nvidia,cpu-pwr-good-time = <2000>; - nvidia,cpu-pwr-off-time = <200>; - nvidia,core-pwr-good-time = <3845 3845>; - nvidia,core-pwr-off-time = <0>; - nvidia,core-power-req-active-high; - nvidia,sys-clock-req-active-high; - }; - - ahub@70080000 { - i2s@70080400 { - status = "okay"; - }; - }; - - sdhci@78000000 { - status = "okay"; - cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>; - power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>; - bus-width = <4>; - }; - - sdhci@78000600 { - status = "okay"; - bus-width = <8>; - non-removable; - }; - - usb@7d008000 { - status = "okay"; - }; - - usb-phy@7d008000 { - vbus-supply = <&usb3_vbus_reg>; - status = "okay"; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - - enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; - power-supply = <&vdd_bl_reg>; - pwms = <&pwm 0 5000000>; - - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - }; - - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - panel: panel { - compatible = "chunghwa,claa101wb01", "simple-panel"; - ddc-i2c-bus = <&panelddc>; - - power-supply = <&vdd_pnl1_reg>; - enable-gpios = <&gpio TEGRA_GPIO(L, 2) GPIO_ACTIVE_HIGH>; - - backlight = <&backlight>; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - vdd_ac_bat_reg: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "vdd_ac_bat"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - cam_1v8_reg: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "cam_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(BB, 4) GPIO_ACTIVE_HIGH>; - vin-supply = <&vio_reg>; - }; - - cp_5v_reg: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "cp_5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - regulator-always-on; - enable-active-high; - gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; - }; - - emmc_3v3_reg: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "emmc_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(D, 1) GPIO_ACTIVE_HIGH>; - vin-supply = <&sys_3v3_reg>; - }; - - modem_3v3_reg: regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "modem_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(D, 6) GPIO_ACTIVE_HIGH>; - }; - - pex_hvdd_3v3_reg: regulator@5 { - compatible = "regulator-fixed"; - reg = <5>; - regulator-name = "pex_hvdd_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(L, 7) GPIO_ACTIVE_HIGH>; - vin-supply = <&sys_3v3_reg>; - }; - - vdd_cam1_ldo_reg: regulator@6 { - compatible = "regulator-fixed"; - reg = <6>; - regulator-name = "vdd_cam1_ldo"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(R, 6) GPIO_ACTIVE_HIGH>; - vin-supply = <&sys_3v3_reg>; - }; - - vdd_cam2_ldo_reg: regulator@7 { - compatible = "regulator-fixed"; - reg = <7>; - regulator-name = "vdd_cam2_ldo"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>; - vin-supply = <&sys_3v3_reg>; - }; - - vdd_cam3_ldo_reg: regulator@8 { - compatible = "regulator-fixed"; - reg = <8>; - regulator-name = "vdd_cam3_ldo"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_HIGH>; - vin-supply = <&sys_3v3_reg>; - }; - - vdd_com_reg: regulator@9 { - compatible = "regulator-fixed"; - reg = <9>; - regulator-name = "vdd_com"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>; - vin-supply = <&sys_3v3_reg>; - }; - - vdd_fuse_3v3_reg: regulator@10 { - compatible = "regulator-fixed"; - reg = <10>; - regulator-name = "vdd_fuse_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(L, 6) GPIO_ACTIVE_HIGH>; - vin-supply = <&sys_3v3_reg>; - }; - - vdd_pnl1_reg: regulator@11 { - compatible = "regulator-fixed"; - reg = <11>; - regulator-name = "vdd_pnl1"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(L, 4) GPIO_ACTIVE_HIGH>; - vin-supply = <&sys_3v3_reg>; - }; - - vdd_vid_reg: regulator@12 { - compatible = "regulator-fixed"; - reg = <12>; - regulator-name = "vddio_vid"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(T, 0) GPIO_ACTIVE_HIGH>; - gpio-open-drain; - vin-supply = <&vdd_5v0_reg>; - }; - }; - - sound { - compatible = "nvidia,tegra-audio-wm8903-cardhu", - "nvidia,tegra-audio-wm8903"; - nvidia,model = "NVIDIA Tegra Cardhu"; - - nvidia,audio-routing = - "Headphone Jack", "HPOUTR", - "Headphone Jack", "HPOUTL", - "Int Spk", "ROP", - "Int Spk", "RON", - "Int Spk", "LOP", - "Int Spk", "LON", - "Mic Jack", "MICBIAS", - "IN1L", "Mic Jack"; - - nvidia,i2s-controller = <&tegra_i2s1>; - nvidia,audio-codec = <&wm8903>; - - nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; - nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) - GPIO_ACTIVE_HIGH>; - - clocks = <&tegra_car TEGRA30_CLK_PLL_A>, - <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA30_CLK_EXTERN1>; - clock-names = "pll_a", "pll_a_out0", "mclk"; - }; - - gpio-keys { - compatible = "gpio-keys"; - - power { - label = "Power"; - interrupt-parent = <&pmic>; - interrupts = <2 0>; - linux,code = ; - debounce-interval = <100>; - wakeup-source; - }; - - volume-down { - label = "Volume Down"; - gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <10>; - }; - - volume-up { - label = "Volume Up"; - gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <10>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/tegra30-colibri-eval-v3.dts b/sys/gnu/dts/arm/tegra30-colibri-eval-v3.dts deleted file mode 100644 index 5965150ecdd..00000000000 --- a/sys/gnu/dts/arm/tegra30-colibri-eval-v3.dts +++ /dev/null @@ -1,198 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include -#include "tegra30-colibri.dtsi" - -/ { - model = "Toradex Colibri T30 on Colibri Evaluation Board"; - compatible = "toradex,colibri_t30-eval-v3", "toradex,colibri_t30", - "nvidia,tegra30"; - - aliases { - rtc0 = "/i2c@7000c000/rtc@68"; - rtc1 = "/i2c@7000d000/pmic@2d"; - rtc2 = "/rtc@7000e000"; - serial0 = &uarta; - serial1 = &uartb; - serial2 = &uartd; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - host1x@50000000 { - dc@54200000 { - rgb { - status = "okay"; - nvidia,panel = <&panel>; - }; - }; - - hdmi@54280000 { - status = "okay"; - hdmi-supply = <®_5v0>; - }; - }; - - /* Colibri UART-A */ - serial@70006000 { - status = "okay"; - }; - - /* Colibri UART-C */ - serial@70006040 { - status = "okay"; - }; - - /* Colibri UART-B */ - serial@70006300 { - status = "okay"; - }; - - pwm@7000a000 { - status = "okay"; - }; - - /* - * GEN1_I2C: I2C_SDA/SCL on SODIMM pin 194/196 (e.g. RTC on carrier - * board) - */ - i2c@7000c000 { - status = "okay"; - clock-frequency = <400000>; - - /* M41T0M6 real time clock on carrier board */ - rtc@68 { - compatible = "st,m41t0"; - reg = <0x68>; - }; - }; - - /* GEN2_I2C: unused */ - - /* CAM_I2C (I2C3): unused */ - - /* DDC_CLOCK/DATA on X3 pin 15/16 (e.g. display EDID) */ - i2c@7000c700 { - status = "okay"; - }; - - /* SPI1: Colibri SSP */ - spi@7000d400 { - status = "okay"; - spi-max-frequency = <25000000>; - - can@0 { - compatible = "microchip,mcp2515"; - reg = <0>; - clocks = <&clk16m>; - interrupt-parent = <&gpio>; - /* CAN_INT */ - interrupts = ; - spi-max-frequency = <10000000>; - vdd-supply = <®_3v3>; - xceiver-supply = <®_5v0>; - }; - }; - - /* SD/MMC */ - sdhci@78000200 { - status = "okay"; - bus-width = <4>; - cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>; /* MMCD */ - no-1-8-v; - }; - - /* EHCI instance 0: USB1_DP/N -> USBC_P/N */ - usb@7d000000 { - status = "okay"; - dr_mode = "otg"; - }; - - usb-phy@7d000000 { - status = "okay"; - vbus-supply = <®_usbc_vbus>; - }; - - /* EHCI instance 2: USB3_DP/N -> USBH_P/N */ - usb@7d008000 { - status = "okay"; - }; - - usb-phy@7d008000 { - status = "okay"; - vbus-supply = <®_usbh_vbus>; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - brightness-levels = <255 128 64 32 16 8 4 0>; - default-brightness-level = <6>; - /* BL_ON */ - enable-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; - power-supply = <®_3v3>; - pwms = <&pwm 0 5000000>; /* PWM */ - }; - - clk16m: osc3 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <16000000>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - wakeup { - label = "SODIMM pin 45 wakeup"; - gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>; - linux,code = ; - debounce-interval = <10>; - wakeup-source; - }; - }; - - panel: panel { - /* - * edt,et057090dhu: EDT 5.7" LCD TFT - * edt,et070080dh6: EDT 7.0" LCD TFT - */ - compatible = "edt,et057090dhu", "simple-panel"; - backlight = <&backlight>; - power-supply = <®_3v3>; - }; - - reg_3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "3.3V_SW"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_5v0: regulator-5v0 { - compatible = "regulator-fixed"; - regulator-name = "5V_SW"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_usbc_vbus: regulator-usbc-vbus { - compatible = "regulator-fixed"; - regulator-name = "VCC_USB5"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <®_5v0>; - }; - - /* USBH_PEN resp. USB_P_EN */ - reg_usbh_vbus: regulator-usbh-vbus { - compatible = "regulator-fixed"; - regulator-name = "VCC_USB[1-4]"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; - vin-supply = <®_5v0>; - }; -}; diff --git a/sys/gnu/dts/arm/tegra30-colibri.dtsi b/sys/gnu/dts/arm/tegra30-colibri.dtsi deleted file mode 100644 index 1f9198bb24f..00000000000 --- a/sys/gnu/dts/arm/tegra30-colibri.dtsi +++ /dev/null @@ -1,1045 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "tegra30.dtsi" - -/* - * Toradex Colibri T30 Module Device Tree - * Compatible for Revisions V1.1B, V1.1C, V1.1D, V1.1E, V1.1F; IT: V1.1A, V1.1B - */ -/ { - memory@80000000 { - reg = <0x80000000 0x40000000>; - }; - - host1x@50000000 { - hdmi@54280000 { - nvidia,ddc-i2c-bus = <&hdmi_ddc>; - nvidia,hpd-gpio = - <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; - pll-supply = <®_1v8_avdd_hdmi_pll>; - vdd-supply = <®_3v3_avdd_hdmi>; - }; - }; - - pinmux@70000868 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - /* Analogue Audio (On-module) */ - clk1-out-pw4 { - nvidia,pins = "clk1_out_pw4"; - nvidia,function = "extperiph1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3-fs-pp0 { - nvidia,pins = "dap3_fs_pp0", - "dap3_sclk_pp3", - "dap3_din_pp1", - "dap3_dout_pp2"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Colibri Address/Data Bus (GMI) */ - gmi-ad0-pg0 { - nvidia,pins = "gmi_ad0_pg0", - "gmi_ad2_pg2", - "gmi_ad3_pg3", - "gmi_ad4_pg4", - "gmi_ad5_pg5", - "gmi_ad6_pg6", - "gmi_ad7_pg7", - "gmi_ad8_ph0", - "gmi_ad9_ph1", - "gmi_ad10_ph2", - "gmi_ad11_ph3", - "gmi_ad12_ph4", - "gmi_ad13_ph5", - "gmi_ad14_ph6", - "gmi_ad15_ph7", - "gmi_adv_n_pk0", - "gmi_clk_pk1", - "gmi_cs4_n_pk2", - "gmi_cs2_n_pk3", - "gmi_iordy_pi5", - "gmi_oe_n_pi1", - "gmi_wait_pi7", - "gmi_wr_n_pi0", - "dap1_fs_pn0", - "dap1_din_pn1", - "dap1_dout_pn2", - "dap1_sclk_pn3", - "dap2_fs_pa2", - "dap2_sclk_pa3", - "dap2_din_pa4", - "dap2_dout_pa5", - "spi1_sck_px5", - "spi1_mosi_px4", - "spi1_cs0_n_px6", - "spi2_cs0_n_px3", - "spi2_miso_px1", - "spi2_mosi_px0", - "spi2_sck_px2", - "uart2_cts_n_pj5", - "uart2_rts_n_pj6"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - /* Further pins may be used as GPIOs */ - dap4-din-pp5 { - nvidia,pins = "dap4_din_pp5", - "dap4_dout_pp6", - "dap4_fs_pp4", - "dap4_sclk_pp7", - "pbb7", - "sdmmc1_clk_pz0", - "sdmmc1_cmd_pz1", - "sdmmc1_dat0_py7", - "sdmmc1_dat1_py6", - "sdmmc1_dat3_py4", - "uart3_cts_n_pa1", - "uart3_txd_pw6", - "uart3_rxd_pw7"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd-d18-pm2 { - nvidia,pins = "lcd_d18_pm2", - "lcd_d19_pm3", - "lcd_d20_pm4", - "lcd_d21_pm5", - "lcd_d22_pm6", - "lcd_d23_pm7", - "lcd_dc0_pn6", - "pex_l2_clkreq_n_pcc7"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd-cs0-n-pn4 { - nvidia,pins = "lcd_cs0_n_pn4", - "lcd_sdin_pz2", - "pu0", - "pu1", - "pu2", - "pu3", - "pu4", - "pu5", - "pu6", - "spi1_miso_px7", - "uart3_rts_n_pc0"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd-pwr0-pb2 { - nvidia,pins = "lcd_pwr0_pb2", - "lcd_sck_pz4", - "lcd_sdout_pn5", - "lcd_wr_n_pz3"; - nvidia,function = "hdcp"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pbb4 { - nvidia,pins = "pbb4", - "pbb5", - "pbb6"; - nvidia,function = "displayb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - /* Multiplexed RDnWR and therefore disabled */ - lcd-cs1-n-pw0 { - nvidia,pins = "lcd_cs1_n_pw0"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - /* Multiplexed GMI_CLK and therefore disabled */ - owr { - nvidia,pins = "owr"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - /* Tri-stating GMI_WR_N on nPWE SODIMM pin 99 */ - sdmmc3-dat4-pd1 { - nvidia,pins = "sdmmc3_dat4_pd1"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - /* Not tri-stating GMI_WR_N on RDnWR SODIMM pin 93 */ - sdmmc3-dat5-pd0 { - nvidia,pins = "sdmmc3_dat5_pd0"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Colibri BL_ON */ - pv2 { - nvidia,pins = "pv2"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Colibri Backlight PWM */ - sdmmc3-dat3-pb4 { - nvidia,pins = "sdmmc3_dat3_pb4"; - nvidia,function = "pwm0"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Colibri CAN_INT */ - kb-row8-ps0 { - nvidia,pins = "kb_row8_ps0"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Colibri DDC */ - ddc-scl-pv4 { - nvidia,pins = "ddc_scl_pv4", - "ddc_sda_pv5"; - nvidia,function = "i2c4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Colibri EXT_IO* */ - gen2-i2c-scl-pt5 { - nvidia,pins = "gen2_i2c_scl_pt5", - "gen2_i2c_sda_pt6"; - nvidia,function = "rsvd4"; - nvidia,open-drain = ; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - spdif-in-pk6 { - nvidia,pins = "spdif_in_pk6"; - nvidia,function = "hda"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Colibri GPIO */ - clk2-out-pw5 { - nvidia,pins = "clk2_out_pw5", - "pcc2", - "pv3", - "sdmmc1_dat2_py5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd-pwr1-pc1 { - nvidia,pins = "lcd_pwr1_pc1", - "pex_l1_clkreq_n_pdd6", - "pex_l1_rst_n_pdd5"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pv1 { - nvidia,pins = "pv1", - "sdmmc3_dat0_pb7", - "sdmmc3_dat1_pb6"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Colibri HOTPLUG_DETECT (HDMI) */ - hdmi-int-pn7 { - nvidia,pins = "hdmi_int_pn7"; - nvidia,function = "hdmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Colibri I2C */ - gen1-i2c-scl-pc4 { - nvidia,pins = "gen1_i2c_scl_pc4", - "gen1_i2c_sda_pc5"; - nvidia,function = "i2c1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - - /* Colibri LCD (L_* resp. LDD<*>) */ - lcd-d0-pe0 { - nvidia,pins = "lcd_d0_pe0", - "lcd_d1_pe1", - "lcd_d2_pe2", - "lcd_d3_pe3", - "lcd_d4_pe4", - "lcd_d5_pe5", - "lcd_d6_pe6", - "lcd_d7_pe7", - "lcd_d8_pf0", - "lcd_d9_pf1", - "lcd_d10_pf2", - "lcd_d11_pf3", - "lcd_d12_pf4", - "lcd_d13_pf5", - "lcd_d14_pf6", - "lcd_d15_pf7", - "lcd_d16_pm0", - "lcd_d17_pm1", - "lcd_de_pj1", - "lcd_hsync_pj3", - "lcd_pclk_pb3", - "lcd_vsync_pj4"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - /* - * Colibri L_BIAS, LCD_M1 is muxed with LCD_DE - * today's display need DE, disable LCD_M1 - */ - lcd-m1-pw1 { - nvidia,pins = "lcd_m1_pw1"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Colibri MMC */ - kb-row10-ps2 { - nvidia,pins = "kb_row10_ps2"; - nvidia,function = "sdmmc2"; - nvidia,pull = ; - nvidia,tristate = ; - }; - kb-row11-ps3 { - nvidia,pins = "kb_row11_ps3", - "kb_row12_ps4", - "kb_row13_ps5", - "kb_row14_ps6", - "kb_row15_ps7"; - nvidia,function = "sdmmc2"; - nvidia,pull = ; - nvidia,tristate = ; - }; - /* Colibri MMC_CD */ - gmi-wp-n-pc7 { - nvidia,pins = "gmi_wp_n_pc7"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - /* Multiplexed and therefore disabled */ - cam-mclk-pcc0 { - nvidia,pins = "cam_mclk_pcc0"; - nvidia,function = "vi_alt3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - cam-i2c-scl-pbb1 { - nvidia,pins = "cam_i2c_scl_pbb1", - "cam_i2c_sda_pbb2"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pbb0 { - nvidia,pins = "pbb0", - "pcc1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pbb3 { - nvidia,pins = "pbb3"; - nvidia,function = "displayb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Colibri nRESET_OUT */ - gmi-rst-n-pi4 { - nvidia,pins = "gmi_rst_n_pi4"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* - * Colibri Parallel Camera (Optional) - * pins multiplexed with others and therefore disabled - */ - vi-vsync-pd6 { - nvidia,pins = "vi_d0_pt4", - "vi_d1_pd5", - "vi_d2_pl0", - "vi_d3_pl1", - "vi_d4_pl2", - "vi_d5_pl3", - "vi_d6_pl4", - "vi_d7_pl5", - "vi_d8_pl6", - "vi_d9_pl7", - "vi_d10_pt2", - "vi_d11_pt3", - "vi_hsync_pd7", - "vi_mclk_pt1", - "vi_pclk_pt0", - "vi_vsync_pd6"; - nvidia,function = "vi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Colibri PWM */ - sdmmc3-dat2-pb5 { - nvidia,pins = "sdmmc3_dat2_pb5"; - nvidia,function = "pwm1"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Colibri PWM */ - sdmmc3-clk-pa6 { - nvidia,pins = "sdmmc3_clk_pa6"; - nvidia,function = "pwm2"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Colibri PWM */ - sdmmc3-cmd-pa7 { - nvidia,pins = "sdmmc3_cmd_pa7"; - nvidia,function = "pwm3"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Colibri SSP */ - ulpi-clk-py0 { - nvidia,pins = "ulpi_clk_py0", - "ulpi_dir_py1", - "ulpi_nxt_py2", - "ulpi_stp_py3"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - }; - /* Multiplexed SSPFRM, SSPTXD and therefore disabled */ - sdmmc3-dat6-pd3 { - nvidia,pins = "sdmmc3_dat6_pd3", - "sdmmc3_dat7_pd4"; - nvidia,function = "spdif"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Colibri UART-A */ - ulpi-data0 { - nvidia,pins = "ulpi_data0_po1", - "ulpi_data1_po2", - "ulpi_data2_po3", - "ulpi_data3_po4", - "ulpi_data4_po5", - "ulpi_data5_po6", - "ulpi_data6_po7", - "ulpi_data7_po0"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Colibri UART-B */ - gmi-a16-pj7 { - nvidia,pins = "gmi_a16_pj7", - "gmi_a17_pb0", - "gmi_a18_pb1", - "gmi_a19_pk7"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Colibri UART-C */ - uart2-rxd { - nvidia,pins = "uart2_rxd_pc3", - "uart2_txd_pc2"; - nvidia,function = "uartb"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Colibri USBC_DET */ - spdif-out-pk5 { - nvidia,pins = "spdif_out_pk5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Colibri USBH_PEN */ - spi2-cs1-n-pw2 { - nvidia,pins = "spi2_cs1_n_pw2"; - nvidia,function = "spi2_alt"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Colibri USBH_OC */ - spi2-cs2-n-pw3, { - nvidia,pins = "spi2_cs2_n_pw3"; - nvidia,function = "spi2_alt"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Colibri VGA not supported and therefore disabled */ - crt-hsync-pv6 { - nvidia,pins = "crt_hsync_pv6", - "crt_vsync_pv7"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* eMMC (On-module) */ - sdmmc4-clk-pcc4 { - nvidia,pins = "sdmmc4_clk_pcc4", - "sdmmc4_cmd_pt7", - "sdmmc4_rst_n_pcc3"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4-dat0-paa0 { - nvidia,pins = "sdmmc4_dat0_paa0", - "sdmmc4_dat1_paa1", - "sdmmc4_dat2_paa2", - "sdmmc4_dat3_paa3", - "sdmmc4_dat4_paa4", - "sdmmc4_dat5_paa5", - "sdmmc4_dat6_paa6", - "sdmmc4_dat7_paa7"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* LAN_EXT_WAKEUP#, LAN_PME (On-module) */ - pex-l0-rst-n-pdd1 { - nvidia,pins = "pex_l0_rst_n_pdd1", - "pex_wake_n_pdd3"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - /* LAN_V_BUS, LAN_RESET# (On-module) */ - pex-l0-clkreq-n-pdd2 { - nvidia,pins = "pex_l0_clkreq_n_pdd2", - "pex_l0_prsnt_n_pdd0"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* nBATT_FAULT(SENSE), nVDD_FAULT(SENSE) */ - pex-l2-rst-n-pcc6 { - nvidia,pins = "pex_l2_rst_n_pcc6", - "pex_l2_prsnt_n_pdd7"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Not connected and therefore disabled */ - clk1-req-pee2 { - nvidia,pins = "clk1_req_pee2", - "pex_l1_prsnt_n_pdd4"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk2-req-pcc5 { - nvidia,pins = "clk2_req_pcc5", - "clk3_out_pee0", - "clk3_req_pee1", - "clk_32k_out_pa0", - "hdmi_cec_pee3", - "sys_clk_req_pz5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi-dqs-pi2 { - nvidia,pins = "gmi_dqs_pi2", - "kb_col2_pq2", - "kb_col3_pq3", - "kb_col4_pq4", - "kb_col5_pq5", - "kb_row4_pr4"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-col0-pq0 { - nvidia,pins = "kb_col0_pq0", - "kb_col1_pq1", - "kb_col6_pq6", - "kb_col7_pq7", - "kb_row5_pr5", - "kb_row6_pr6", - "kb_row7_pr7", - "kb_row9_ps1"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb-row0-pr0 { - nvidia,pins = "kb_row0_pr0", - "kb_row1_pr1", - "kb_row2_pr2", - "kb_row3_pr3"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd-pwr2-pc6 { - nvidia,pins = "lcd_pwr2_pc6"; - nvidia,function = "hdcp"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Power I2C (On-module) */ - pwr-i2c-scl-pz6 { - nvidia,pins = "pwr_i2c_scl_pz6", - "pwr_i2c_sda_pz7"; - nvidia,function = "i2cpwr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - - /* - * THERMD_ALERT#, unlatched I2C address pin of LM95245 - * temperature sensor therefore requires disabling for - * now - */ - lcd-dc1-pd2 { - nvidia,pins = "lcd_dc1_pd2"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* TOUCH_PEN_INT# (On-module) */ - pv0 { - nvidia,pins = "pv0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - }; - }; - - serial@70006040 { - compatible = "nvidia,tegra30-hsuart"; - }; - - serial@70006300 { - compatible = "nvidia,tegra30-hsuart"; - }; - - hdmi_ddc: i2c@7000c700 { - clock-frequency = <10000>; - }; - - /* - * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and - * touch screen controller (On-module) - */ - i2c@7000d000 { - status = "okay"; - clock-frequency = <100000>; - - /* SGTL5000 audio codec */ - sgtl5000: codec@a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - VDDA-supply = <®_module_3v3_audio>; - VDDD-supply = <®_1v8_vio>; - VDDIO-supply = <®_module_3v3>; - clocks = <&tegra_car TEGRA30_CLK_EXTERN1>; - }; - - pmic: pmic@2d { - compatible = "ti,tps65911"; - reg = <0x2d>; - - interrupts = ; - #interrupt-cells = <2>; - interrupt-controller; - - ti,system-power-controller; - - #gpio-cells = <2>; - gpio-controller; - - vcc1-supply = <®_module_3v3>; - vcc2-supply = <®_module_3v3>; - vcc3-supply = <®_1v8_vio>; - vcc4-supply = <®_module_3v3>; - vcc5-supply = <®_module_3v3>; - vcc6-supply = <®_1v8_vio>; - vcc7-supply = <®_5v0_charge_pump>; - vccio-supply = <®_module_3v3>; - - regulators { - vdd1_reg: vdd1 { - regulator-name = "+V1.35_VDDIO_DDR"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - }; - - /* SW2: unused */ - - vddctrl_reg: vddctrl { - regulator-name = "+V1.0_VDD_CPU"; - regulator-min-microvolt = <1150000>; - regulator-max-microvolt = <1150000>; - regulator-always-on; - }; - - reg_1v8_vio: vio { - regulator-name = "+V1.8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - /* LDO1: unused */ - - /* - * EN_+V3.3 switching via FET: - * +V3.3_AUDIO_AVDD_S, +V3.3 and +V1.8_VDD_LAN - * see also +V3.3 fixed supply - */ - ldo2_reg: ldo2 { - regulator-name = "EN_+V3.3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - /* LDO3: unused */ - - ldo4_reg: ldo4 { - regulator-name = "+V1.2_VDD_RTC"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - /* - * +V2.8_AVDD_VDAC: - * only required for (unsupported) analog RGB - */ - ldo5_reg: ldo5 { - regulator-name = "+V2.8_AVDD_VDAC"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - /* - * +V1.05_AVDD_PLLE: avdd_plle should be 1.05V - * but LDO6 can't set voltage in 50mV - * granularity - */ - ldo6_reg: ldo6 { - regulator-name = "+V1.05_AVDD_PLLE"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - }; - - ldo7_reg: ldo7 { - regulator-name = "+V1.2_AVDD_PLL"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - ldo8_reg: ldo8 { - regulator-name = "+V1.0_VDD_DDR_HS"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - }; - }; - - /* STMPE811 touch screen controller */ - touchscreen@41 { - compatible = "st,stmpe811"; - reg = <0x41>; - irq-gpio = <&gpio TEGRA_GPIO(V, 0) IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - id = <0>; - blocks = <0x5>; - irq-trigger = <0x1>; - /* 3.25 MHz ADC clock speed */ - st,adc-freq = <1>; - /* 12-bit ADC */ - st,mod-12b = <1>; - /* internal ADC reference */ - st,ref-sel = <0>; - /* ADC converstion time: 80 clocks */ - st,sample-time = <4>; - /* forbid to use ADC channels 3-0 (touch) */ - - stmpe_touchscreen { - compatible = "st,stmpe-ts"; - /* 8 sample average control */ - st,ave-ctrl = <3>; - /* 7 length fractional part in z */ - st,fraction-z = <7>; - /* - * 50 mA typical 80 mA max touchscreen drivers - * current limit value - */ - st,i-drive = <1>; - /* 1 ms panel driver settling time */ - st,settling = <3>; - /* 5 ms touch detect interrupt delay */ - st,touch-det-delay = <5>; - }; - - stmpe_adc { - compatible = "st,stmpe-adc"; - st,norequest-mask = <0x0F>; - }; - }; - - /* - * LM95245 temperature sensor - * Note: OVERT1# directly connected to TPS65911 PMIC PWRDN - */ - temp-sensor@4c { - compatible = "national,lm95245"; - reg = <0x4c>; - }; - - /* SW: +V1.2_VDD_CORE */ - regulator@60 { - compatible = "ti,tps62362"; - reg = <0x60>; - - regulator-name = "tps62362-vout"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1400000>; - regulator-boot-on; - regulator-always-on; - ti,vsel0-state-low; - /* VSEL1: EN_CORE_DVFS_N low for DVFS */ - ti,vsel1-state-low; - }; - }; - - pmc@7000e400 { - nvidia,invert-interrupt; - nvidia,suspend-mode = <1>; - nvidia,cpu-pwr-good-time = <5000>; - nvidia,cpu-pwr-off-time = <5000>; - nvidia,core-pwr-good-time = <3845 3845>; - nvidia,core-pwr-off-time = <0>; - nvidia,core-power-req-active-high; - nvidia,sys-clock-req-active-high; - - /* Set DEV_OFF bit in DCDC control register of TPS65911 PMIC */ - i2c-thermtrip { - nvidia,i2c-controller-id = <4>; - nvidia,bus-addr = <0x2d>; - nvidia,reg-addr = <0x3f>; - nvidia,reg-data = <0x1>; - }; - }; - - hda@70030000 { - status = "okay"; - }; - - ahub@70080000 { - i2s@70080500 { - status = "okay"; - }; - }; - - /* eMMC */ - sdhci@78000600 { - status = "okay"; - bus-width = <8>; - non-removable; - vmmc-supply = <®_module_3v3>; /* VCC */ - vqmmc-supply = <®_1v8_vio>; /* VCCQ */ - mmc-ddr-1_8v; - }; - - /* EHCI instance 1: USB2_DP/N -> AX88772B (On-module) */ - usb@7d004000 { - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - - asix@1 { - reg = <1>; - local-mac-address = [00 00 00 00 00 00]; - }; - }; - - usb-phy@7d004000 { - status = "okay"; - vbus-supply = <®_lan_v_bus>; - }; - - clk32k_in: xtal1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - - reg_1v8_avdd_hdmi_pll: regulator-1v8-avdd-hdmi-pll { - compatible = "regulator-fixed"; - regulator-name = "+V1.8_AVDD_HDMI_PLL"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - enable-active-high; - gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; - vin-supply = <®_1v8_vio>; - }; - - reg_3v3_avdd_hdmi: regulator-3v3-avdd-hdmi { - compatible = "regulator-fixed"; - regulator-name = "+V3.3_AVDD_HDMI"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; - vin-supply = <®_module_3v3>; - }; - - reg_5v0_charge_pump: regulator-5v0-charge-pump { - compatible = "regulator-fixed"; - regulator-name = "+V5.0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - reg_lan_v_bus: regulator-lan-v-bus { - compatible = "regulator-fixed"; - regulator-name = "LAN_V_BUS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(DD, 2) GPIO_ACTIVE_HIGH>; - }; - - reg_module_3v3: regulator-module-3v3 { - compatible = "regulator-fixed"; - regulator-name = "+V3.3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_module_3v3_audio: regulator-module-3v3-audio { - compatible = "regulator-fixed"; - regulator-name = "+V3.3_AUDIO_AVDD_S"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - sound { - compatible = "toradex,tegra-audio-sgtl5000-colibri_t30", - "nvidia,tegra-audio-sgtl5000"; - nvidia,model = "Toradex Colibri T30"; - nvidia,audio-routing = - "Headphone Jack", "HP_OUT", - "LINE_IN", "Line In Jack", - "MIC_IN", "Mic Jack"; - nvidia,i2s-controller = <&tegra_i2s2>; - nvidia,audio-codec = <&sgtl5000>; - clocks = <&tegra_car TEGRA30_CLK_PLL_A>, - <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA30_CLK_EXTERN1>; - clock-names = "pll_a", "pll_a_out0", "mclk"; - }; -}; - -&gpio { - lan-reset-n { - gpio-hog; - gpios = ; - output-high; - line-name = "LAN_RESET#"; - }; -}; diff --git a/sys/gnu/dts/arm/tegra30-cpu-opp-microvolt.dtsi b/sys/gnu/dts/arm/tegra30-cpu-opp-microvolt.dtsi deleted file mode 100644 index 5c40ef49894..00000000000 --- a/sys/gnu/dts/arm/tegra30-cpu-opp-microvolt.dtsi +++ /dev/null @@ -1,801 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -/ { - cpu0_opp_table: cpu_opp_table0 { - opp@51000000_800 { - opp-microvolt = <800000 800000 1250000>; - }; - - opp@51000000_850 { - opp-microvolt = <850000 850000 1250000>; - }; - - opp@51000000_912 { - opp-microvolt = <912000 912000 1250000>; - }; - - opp@102000000_800 { - opp-microvolt = <800000 800000 1250000>; - }; - - opp@102000000_850 { - opp-microvolt = <850000 850000 1250000>; - }; - - opp@102000000_912 { - opp-microvolt = <912000 912000 1250000>; - }; - - opp@204000000_800 { - opp-microvolt = <800000 800000 1250000>; - }; - - opp@204000000_850 { - opp-microvolt = <850000 850000 1250000>; - }; - - opp@204000000_912 { - opp-microvolt = <912000 912000 1250000>; - }; - - opp@312000000_850 { - opp-microvolt = <850000 850000 1250000>; - }; - - opp@312000000_912 { - opp-microvolt = <912000 912000 1250000>; - }; - - opp@340000000_800 { - opp-microvolt = <800000 800000 1250000>; - }; - - opp@340000000_850 { - opp-microvolt = <850000 850000 1250000>; - }; - - opp@370000000_800 { - opp-microvolt = <800000 800000 1250000>; - }; - - opp@456000000_850 { - opp-microvolt = <850000 850000 1250000>; - }; - - opp@456000000_912 { - opp-microvolt = <912000 912000 1250000>; - }; - - opp@475000000_800 { - opp-microvolt = <800000 800000 1250000>; - }; - - opp@475000000_850 { - opp-microvolt = <850000 850000 1250000>; - }; - - opp@475000000_850_0_1 { - opp-microvolt = <850000 850000 1250000>; - }; - - opp@475000000_850_0_4 { - opp-microvolt = <850000 850000 1250000>; - }; - - opp@475000000_850_0_7 { - opp-microvolt = <850000 850000 1250000>; - }; - - opp@475000000_850_0_8 { - opp-microvolt = <850000 850000 1250000>; - }; - - opp@608000000_850 { - opp-microvolt = <850000 850000 1250000>; - }; - - opp@608000000_912 { - opp-microvolt = <912000 912000 1250000>; - }; - - opp@620000000_850 { - opp-microvolt = <850000 850000 1250000>; - }; - - opp@640000000_850 { - opp-microvolt = <850000 850000 1250000>; - }; - - opp@640000000_850_1_1 { - opp-microvolt = <850000 850000 1250000>; - }; - - opp@640000000_850_2_1 { - opp-microvolt = <850000 850000 1250000>; - }; - - opp@640000000_850_3_1 { - opp-microvolt = <850000 850000 1250000>; - }; - - opp@640000000_850_1_4 { - opp-microvolt = <850000 850000 1250000>; - }; - - opp@640000000_850_2_4 { - opp-microvolt = <850000 850000 1250000>; - }; - - opp@640000000_850_3_4 { - opp-microvolt = <850000 850000 1250000>; - }; - - opp@640000000_850_1_7 { - opp-microvolt = <850000 850000 1250000>; - }; - - opp@640000000_850_2_7 { - opp-microvolt = <850000 850000 1250000>; - }; - - opp@640000000_850_3_7 { - opp-microvolt = <850000 850000 1250000>; - }; - - opp@640000000_850_4_7 { - opp-microvolt = <850000 850000 1250000>; - }; - - opp@640000000_850_1_8 { - opp-microvolt = <850000 850000 1250000>; - }; - - opp@640000000_850_2_8 { - opp-microvolt = <850000 850000 1250000>; - }; - - opp@640000000_850_3_8 { - opp-microvolt = <850000 850000 1250000>; - }; - - opp@640000000_850_4_8 { - opp-microvolt = <850000 850000 1250000>; - }; - - opp@640000000_900 { - opp-microvolt = <900000 900000 1250000>; - }; - - opp@760000000_850 { - opp-microvolt = <850000 850000 1250000>; - }; - - opp@760000000_850_3_1 { - opp-microvolt = <850000 850000 1250000>; - }; - - opp@760000000_850_3_2 { - opp-microvolt = <850000 850000 1250000>; - }; - - opp@760000000_850_3_3 { - opp-microvolt = <850000 850000 1250000>; - }; - - opp@760000000_850_3_4 { - opp-microvolt = <850000 850000 1250000>; - }; - - opp@760000000_850_3_7 { - opp-microvolt = <850000 850000 1250000>; - }; - - opp@760000000_850_4_7 { - opp-microvolt = <850000 850000 1250000>; - }; - - opp@760000000_850_3_8 { - opp-microvolt = <850000 850000 1250000>; - }; - - opp@760000000_850_4_8 { - opp-microvolt = <850000 850000 1250000>; - }; - - opp@760000000_850_0_10 { - opp-microvolt = <850000 850000 1250000>; - }; - - opp@760000000_900 { - opp-microvolt = <900000 900000 1250000>; - }; - - opp@760000000_900_1_1 { - opp-microvolt = <900000 900000 1250000>; - }; - - opp@760000000_900_2_1 { - opp-microvolt = <900000 900000 1250000>; - }; - - opp@760000000_900_1_2 { - opp-microvolt = <900000 900000 1250000>; - }; - - opp@760000000_900_2_2 { - opp-microvolt = <900000 900000 1250000>; - }; - - opp@760000000_900_1_3 { - opp-microvolt = <900000 900000 1250000>; - }; - - opp@760000000_900_2_3 { - opp-microvolt = <900000 900000 1250000>; - }; - - opp@760000000_900_1_4 { - opp-microvolt = <900000 900000 1250000>; - }; - - opp@760000000_900_2_4 { - opp-microvolt = <900000 900000 1250000>; - }; - - opp@760000000_900_1_7 { - opp-microvolt = <900000 900000 1250000>; - }; - - opp@760000000_900_2_7 { - opp-microvolt = <900000 900000 1250000>; - }; - - opp@760000000_900_1_8 { - opp-microvolt = <900000 900000 1250000>; - }; - - opp@760000000_900_2_8 { - opp-microvolt = <900000 900000 1250000>; - }; - - opp@760000000_912 { - opp-microvolt = <912000 912000 1250000>; - }; - - opp@760000000_975 { - opp-microvolt = <975000 975000 1250000>; - }; - - opp@816000000_850 { - opp-microvolt = <850000 850000 1250000>; - }; - - opp@816000000_912 { - opp-microvolt = <912000 912000 1250000>; - }; - - opp@860000000_850 { - opp-microvolt = <850000 850000 1250000>; - }; - - opp@860000000_900 { - opp-microvolt = <900000 900000 1250000>; - }; - - opp@860000000_900_2_1 { - opp-microvolt = <900000 900000 1250000>; - }; - - opp@860000000_900_3_1 { - opp-microvolt = <900000 900000 1250000>; - }; - - opp@860000000_900_2_2 { - opp-microvolt = <900000 900000 1250000>; - }; - - opp@860000000_900_3_2 { - opp-microvolt = <900000 900000 1250000>; - }; - - opp@860000000_900_2_3 { - opp-microvolt = <900000 900000 1250000>; - }; - - opp@860000000_900_3_3 { - opp-microvolt = <900000 900000 1250000>; - }; - - opp@860000000_900_2_4 { - opp-microvolt = <900000 900000 1250000>; - }; - - opp@860000000_900_3_4 { - opp-microvolt = <900000 900000 1250000>; - }; - - opp@860000000_900_2_7 { - opp-microvolt = <900000 900000 1250000>; - }; - - opp@860000000_900_3_7 { - opp-microvolt = <900000 900000 1250000>; - }; - - opp@860000000_900_4_7 { - opp-microvolt = <900000 900000 1250000>; - }; - - opp@860000000_900_2_8 { - opp-microvolt = <900000 900000 1250000>; - }; - - opp@860000000_900_3_8 { - opp-microvolt = <900000 900000 1250000>; - }; - - opp@860000000_900_4_8 { - opp-microvolt = <900000 900000 1250000>; - }; - - opp@860000000_975 { - opp-microvolt = <975000 975000 1250000>; - }; - - opp@860000000_975_1_1 { - opp-microvolt = <975000 975000 1250000>; - }; - - opp@860000000_975_1_2 { - opp-microvolt = <975000 975000 1250000>; - }; - - opp@860000000_975_1_3 { - opp-microvolt = <975000 975000 1250000>; - }; - - opp@860000000_975_1_4 { - opp-microvolt = <975000 975000 1250000>; - }; - - opp@860000000_975_1_7 { - opp-microvolt = <975000 975000 1250000>; - }; - - opp@860000000_975_1_8 { - opp-microvolt = <975000 975000 1250000>; - }; - - opp@860000000_1000 { - opp-microvolt = <1000000 1000000 1250000>; - }; - - opp@910000000_900 { - opp-microvolt = <900000 900000 1250000>; - }; - - opp@1000000000_900 { - opp-microvolt = <900000 900000 1250000>; - }; - - opp@1000000000_975 { - opp-microvolt = <975000 975000 1250000>; - }; - - opp@1000000000_975_2_1 { - opp-microvolt = <975000 975000 1250000>; - }; - - opp@1000000000_975_3_1 { - opp-microvolt = <975000 975000 1250000>; - }; - - opp@1000000000_975_2_2 { - opp-microvolt = <975000 975000 1250000>; - }; - - opp@1000000000_975_3_2 { - opp-microvolt = <975000 975000 1250000>; - }; - - opp@1000000000_975_2_3 { - opp-microvolt = <975000 975000 1250000>; - }; - - opp@1000000000_975_3_3 { - opp-microvolt = <975000 975000 1250000>; - }; - - opp@1000000000_975_2_4 { - opp-microvolt = <975000 975000 1250000>; - }; - - opp@1000000000_975_3_4 { - opp-microvolt = <975000 975000 1250000>; - }; - - opp@1000000000_975_2_7 { - opp-microvolt = <975000 975000 1250000>; - }; - - opp@1000000000_975_3_7 { - opp-microvolt = <975000 975000 1250000>; - }; - - opp@1000000000_975_4_7 { - opp-microvolt = <975000 975000 1250000>; - }; - - opp@1000000000_975_2_8 { - opp-microvolt = <975000 975000 1250000>; - }; - - opp@1000000000_975_3_8 { - opp-microvolt = <975000 975000 1250000>; - }; - - opp@1000000000_975_4_8 { - opp-microvolt = <975000 975000 1250000>; - }; - - opp@1000000000_1000 { - opp-microvolt = <1000000 1000000 1250000>; - }; - - opp@1000000000_1025 { - opp-microvolt = <1025000 1025000 1250000>; - }; - - opp@1100000000_900 { - opp-microvolt = <900000 900000 1250000>; - }; - - opp@1100000000_975 { - opp-microvolt = <975000 975000 1250000>; - }; - - opp@1100000000_975_3_1 { - opp-microvolt = <975000 975000 1250000>; - }; - - opp@1100000000_975_3_2 { - opp-microvolt = <975000 975000 1250000>; - }; - - opp@1100000000_975_3_3 { - opp-microvolt = <975000 975000 1250000>; - }; - - opp@1100000000_975_3_4 { - opp-microvolt = <975000 975000 1250000>; - }; - - opp@1100000000_975_3_7 { - opp-microvolt = <975000 975000 1250000>; - }; - - opp@1100000000_975_4_7 { - opp-microvolt = <975000 975000 1250000>; - }; - - opp@1100000000_975_3_8 { - opp-microvolt = <975000 975000 1250000>; - }; - - opp@1100000000_975_4_8 { - opp-microvolt = <975000 975000 1250000>; - }; - - opp@1100000000_1000 { - opp-microvolt = <1000000 1000000 1250000>; - }; - - opp@1100000000_1000_2_1 { - opp-microvolt = <1000000 1000000 1250000>; - }; - - opp@1100000000_1000_2_2 { - opp-microvolt = <1000000 1000000 1250000>; - }; - - opp@1100000000_1000_2_3 { - opp-microvolt = <1000000 1000000 1250000>; - }; - - opp@1100000000_1000_2_4 { - opp-microvolt = <1000000 1000000 1250000>; - }; - - opp@1100000000_1000_2_7 { - opp-microvolt = <1000000 1000000 1250000>; - }; - - opp@1100000000_1000_2_8 { - opp-microvolt = <1000000 1000000 1250000>; - }; - - opp@1100000000_1025 { - opp-microvolt = <1025000 1025000 1250000>; - }; - - opp@1100000000_1075 { - opp-microvolt = <1075000 1075000 1250000>; - }; - - opp@1150000000_975 { - opp-microvolt = <975000 975000 1250000>; - }; - - opp@1200000000_975 { - opp-microvolt = <975000 975000 1250000>; - }; - - opp@1200000000_1000 { - opp-microvolt = <1000000 1000000 1250000>; - }; - - opp@1200000000_1000_3_1 { - opp-microvolt = <1000000 1000000 1250000>; - }; - - opp@1200000000_1000_3_2 { - opp-microvolt = <1000000 1000000 1250000>; - }; - - opp@1200000000_1000_3_3 { - opp-microvolt = <1000000 1000000 1250000>; - }; - - opp@1200000000_1000_3_4 { - opp-microvolt = <1000000 1000000 1250000>; - }; - - opp@1200000000_1000_3_7 { - opp-microvolt = <1000000 1000000 1250000>; - }; - - opp@1200000000_1000_4_7 { - opp-microvolt = <1000000 1000000 1250000>; - }; - - opp@1200000000_1000_3_8 { - opp-microvolt = <1000000 1000000 1250000>; - }; - - opp@1200000000_1000_4_8 { - opp-microvolt = <1000000 1000000 1250000>; - }; - - opp@1200000000_1025 { - opp-microvolt = <1025000 1025000 1250000>; - }; - - opp@1200000000_1025_2_1 { - opp-microvolt = <1025000 1025000 1250000>; - }; - - opp@1200000000_1025_2_2 { - opp-microvolt = <1025000 1025000 1250000>; - }; - - opp@1200000000_1025_2_3 { - opp-microvolt = <1025000 1025000 1250000>; - }; - - opp@1200000000_1025_2_4 { - opp-microvolt = <1025000 1025000 1250000>; - }; - - opp@1200000000_1025_2_7 { - opp-microvolt = <1025000 1025000 1250000>; - }; - - opp@1200000000_1025_2_8 { - opp-microvolt = <1025000 1025000 1250000>; - }; - - opp@1200000000_1050 { - opp-microvolt = <1050000 1050000 1250000>; - }; - - opp@1200000000_1075 { - opp-microvolt = <1075000 1075000 1250000>; - }; - - opp@1200000000_1100 { - opp-microvolt = <1100000 1100000 1250000>; - }; - - opp@1300000000_1000 { - opp-microvolt = <1000000 1000000 1250000>; - }; - - opp@1300000000_1000_4_7 { - opp-microvolt = <1000000 1000000 1250000>; - }; - - opp@1300000000_1000_4_8 { - opp-microvolt = <1000000 1000000 1250000>; - }; - - opp@1300000000_1025 { - opp-microvolt = <1025000 1025000 1250000>; - }; - - opp@1300000000_1025_3_1 { - opp-microvolt = <1025000 1025000 1250000>; - }; - - opp@1300000000_1025_3_7 { - opp-microvolt = <1025000 1025000 1250000>; - }; - - opp@1300000000_1025_3_8 { - opp-microvolt = <1025000 1025000 1250000>; - }; - - opp@1300000000_1050 { - opp-microvolt = <1050000 1050000 1250000>; - }; - - opp@1300000000_1050_2_1 { - opp-microvolt = <1050000 1050000 1250000>; - }; - - opp@1300000000_1050_3_2 { - opp-microvolt = <1050000 1050000 1250000>; - }; - - opp@1300000000_1050_3_3 { - opp-microvolt = <1050000 1050000 1250000>; - }; - - opp@1300000000_1050_3_4 { - opp-microvolt = <1050000 1050000 1250000>; - }; - - opp@1300000000_1050_3_5 { - opp-microvolt = <1050000 1050000 1250000>; - }; - - opp@1300000000_1050_3_6 { - opp-microvolt = <1050000 1050000 1250000>; - }; - - opp@1300000000_1050_2_7 { - opp-microvolt = <1050000 1050000 1250000>; - }; - - opp@1300000000_1050_2_8 { - opp-microvolt = <1050000 1050000 1250000>; - }; - - opp@1300000000_1050_3_12 { - opp-microvolt = <1050000 1050000 1250000>; - }; - - opp@1300000000_1050_3_13 { - opp-microvolt = <1050000 1050000 1250000>; - }; - - opp@1300000000_1075 { - opp-microvolt = <1075000 1075000 1250000>; - }; - - opp@1300000000_1075_2_2 { - opp-microvolt = <1075000 1075000 1250000>; - }; - - opp@1300000000_1075_2_3 { - opp-microvolt = <1075000 1075000 1250000>; - }; - - opp@1300000000_1075_2_4 { - opp-microvolt = <1075000 1075000 1250000>; - }; - - opp@1300000000_1100 { - opp-microvolt = <1100000 1100000 1250000>; - }; - - opp@1300000000_1125 { - opp-microvolt = <1125000 1125000 1250000>; - }; - - opp@1300000000_1150 { - opp-microvolt = <1150000 1150000 1250000>; - }; - - opp@1300000000_1175 { - opp-microvolt = <1175000 1175000 1250000>; - }; - - opp@1400000000_1100 { - opp-microvolt = <1100000 1100000 1250000>; - }; - - opp@1400000000_1125 { - opp-microvolt = <1125000 1125000 1250000>; - }; - - opp@1400000000_1150 { - opp-microvolt = <1150000 1150000 1250000>; - }; - - opp@1400000000_1150_2_4 { - opp-microvolt = <1150000 1150000 1250000>; - }; - - opp@1400000000_1175 { - opp-microvolt = <1175000 1175000 1250000>; - }; - - opp@1400000000_1237 { - opp-microvolt = <1237000 1237000 1250000>; - }; - - opp@1500000000_1125 { - opp-microvolt = <1125000 1125000 1250000>; - }; - - opp@1500000000_1125_4_5 { - opp-microvolt = <1125000 1125000 1250000>; - }; - - opp@1500000000_1125_4_6 { - opp-microvolt = <1125000 1125000 1250000>; - }; - - opp@1500000000_1125_4_12 { - opp-microvolt = <1125000 1125000 1250000>; - }; - - opp@1500000000_1125_4_13 { - opp-microvolt = <1125000 1125000 1250000>; - }; - - opp@1500000000_1150 { - opp-microvolt = <1150000 1150000 1250000>; - }; - - opp@1500000000_1150_3_5 { - opp-microvolt = <1150000 1150000 1250000>; - }; - - opp@1500000000_1150_3_6 { - opp-microvolt = <1150000 1150000 1250000>; - }; - - opp@1500000000_1150_3_12 { - opp-microvolt = <1150000 1150000 1250000>; - }; - - opp@1500000000_1150_3_13 { - opp-microvolt = <1150000 1150000 1250000>; - }; - - opp@1500000000_1200 { - opp-microvolt = <1200000 1200000 1250000>; - }; - - opp@1500000000_1237 { - opp-microvolt = <1237000 1237000 1250000>; - }; - - opp@1600000000_1212 { - opp-microvolt = <1212000 1212000 1250000>; - }; - - opp@1600000000_1237 { - opp-microvolt = <1237000 1237000 1250000>; - }; - - opp@1700000000_1212 { - opp-microvolt = <1212000 1212000 1250000>; - }; - - opp@1700000000_1237 { - opp-microvolt = <1237000 1237000 1250000>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/tegra30-cpu-opp.dtsi b/sys/gnu/dts/arm/tegra30-cpu-opp.dtsi deleted file mode 100644 index d64fc262585..00000000000 --- a/sys/gnu/dts/arm/tegra30-cpu-opp.dtsi +++ /dev/null @@ -1,1202 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -/ { - cpu0_opp_table: cpu_opp_table0 { - compatible = "operating-points-v2"; - opp-shared; - - opp@51000000_800 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x1F 0x31FE>; - opp-hz = /bits/ 64 <51000000>; - }; - - opp@51000000_850 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x1F 0x0C01>; - opp-hz = /bits/ 64 <51000000>; - }; - - opp@51000000_912 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x1F 0x0200>; - opp-hz = /bits/ 64 <51000000>; - }; - - opp@102000000_800 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x1F 0x31FE>; - opp-hz = /bits/ 64 <102000000>; - }; - - opp@102000000_850 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x1F 0x0C01>; - opp-hz = /bits/ 64 <102000000>; - }; - - opp@102000000_912 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x1F 0x0200>; - opp-hz = /bits/ 64 <102000000>; - }; - - opp@204000000_800 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x1F 0x31FE>; - opp-hz = /bits/ 64 <204000000>; - }; - - opp@204000000_850 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x1F 0x0C01>; - opp-hz = /bits/ 64 <204000000>; - }; - - opp@204000000_912 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x1F 0x0200>; - opp-hz = /bits/ 64 <204000000>; - }; - - opp@312000000_850 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x1F 0x0C00>; - opp-hz = /bits/ 64 <312000000>; - }; - - opp@312000000_912 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x1F 0x0200>; - opp-hz = /bits/ 64 <312000000>; - }; - - opp@340000000_800 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x1F 0x0192>; - opp-hz = /bits/ 64 <340000000>; - }; - - opp@340000000_850 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x0F 0x0001>; - opp-hz = /bits/ 64 <340000000>; - }; - - opp@370000000_800 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x1E 0x306C>; - opp-hz = /bits/ 64 <370000000>; - }; - - opp@456000000_850 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x1F 0x0C00>; - opp-hz = /bits/ 64 <456000000>; - }; - - opp@456000000_912 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x1F 0x0200>; - opp-hz = /bits/ 64 <456000000>; - }; - - opp@475000000_800 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x1E 0x31FE>; - opp-hz = /bits/ 64 <475000000>; - }; - - opp@475000000_850 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x0F 0x0001>; - opp-hz = /bits/ 64 <475000000>; - }; - - opp@475000000_850_0_1 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x01 0x0002>; - opp-hz = /bits/ 64 <475000000>; - }; - - opp@475000000_850_0_4 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x01 0x0010>; - opp-hz = /bits/ 64 <475000000>; - }; - - opp@475000000_850_0_7 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x01 0x0080>; - opp-hz = /bits/ 64 <475000000>; - }; - - opp@475000000_850_0_8 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x01 0x0100>; - opp-hz = /bits/ 64 <475000000>; - }; - - opp@608000000_850 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x1F 0x0400>; - opp-hz = /bits/ 64 <608000000>; - }; - - opp@608000000_912 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x1F 0x0200>; - opp-hz = /bits/ 64 <608000000>; - }; - - opp@620000000_850 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x1E 0x306C>; - opp-hz = /bits/ 64 <620000000>; - }; - - opp@640000000_850 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x0F 0x0001>; - opp-hz = /bits/ 64 <640000000>; - }; - - opp@640000000_850_1_1 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x02 0x0002>; - opp-hz = /bits/ 64 <640000000>; - }; - - opp@640000000_850_2_1 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x04 0x0002>; - opp-hz = /bits/ 64 <640000000>; - }; - - opp@640000000_850_3_1 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x08 0x0002>; - opp-hz = /bits/ 64 <640000000>; - }; - - opp@640000000_850_1_4 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x02 0x0010>; - opp-hz = /bits/ 64 <640000000>; - }; - - opp@640000000_850_2_4 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x04 0x0010>; - opp-hz = /bits/ 64 <640000000>; - }; - - opp@640000000_850_3_4 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x08 0x0010>; - opp-hz = /bits/ 64 <640000000>; - }; - - opp@640000000_850_1_7 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x02 0x0080>; - opp-hz = /bits/ 64 <640000000>; - }; - - opp@640000000_850_2_7 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x04 0x0080>; - opp-hz = /bits/ 64 <640000000>; - }; - - opp@640000000_850_3_7 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x08 0x0080>; - opp-hz = /bits/ 64 <640000000>; - }; - - opp@640000000_850_4_7 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x10 0x0080>; - opp-hz = /bits/ 64 <640000000>; - }; - - opp@640000000_850_1_8 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x02 0x0100>; - opp-hz = /bits/ 64 <640000000>; - }; - - opp@640000000_850_2_8 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x04 0x0100>; - opp-hz = /bits/ 64 <640000000>; - }; - - opp@640000000_850_3_8 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x08 0x0100>; - opp-hz = /bits/ 64 <640000000>; - }; - - opp@640000000_850_4_8 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x10 0x0100>; - opp-hz = /bits/ 64 <640000000>; - }; - - opp@640000000_900 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x01 0x0192>; - opp-hz = /bits/ 64 <640000000>; - }; - - opp@760000000_850 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x1E 0x3461>; - opp-hz = /bits/ 64 <760000000>; - }; - - opp@760000000_850_3_1 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x08 0x0002>; - opp-hz = /bits/ 64 <760000000>; - }; - - opp@760000000_850_3_2 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x08 0x0004>; - opp-hz = /bits/ 64 <760000000>; - }; - - opp@760000000_850_3_3 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x08 0x0008>; - opp-hz = /bits/ 64 <760000000>; - }; - - opp@760000000_850_3_4 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x08 0x0010>; - opp-hz = /bits/ 64 <760000000>; - }; - - opp@760000000_850_3_7 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x08 0x0080>; - opp-hz = /bits/ 64 <760000000>; - }; - - opp@760000000_850_4_7 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x10 0x0080>; - opp-hz = /bits/ 64 <760000000>; - }; - - opp@760000000_850_3_8 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x08 0x0100>; - opp-hz = /bits/ 64 <760000000>; - }; - - opp@760000000_850_4_8 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x10 0x0100>; - opp-hz = /bits/ 64 <760000000>; - }; - - opp@760000000_850_0_10 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x01 0x0400>; - opp-hz = /bits/ 64 <760000000>; - }; - - opp@760000000_900 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x01 0x0001>; - opp-hz = /bits/ 64 <760000000>; - }; - - opp@760000000_900_1_1 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x02 0x0002>; - opp-hz = /bits/ 64 <760000000>; - }; - - opp@760000000_900_2_1 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x04 0x0002>; - opp-hz = /bits/ 64 <760000000>; - }; - - opp@760000000_900_1_2 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x02 0x0004>; - opp-hz = /bits/ 64 <760000000>; - }; - - opp@760000000_900_2_2 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x04 0x0004>; - opp-hz = /bits/ 64 <760000000>; - }; - - opp@760000000_900_1_3 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x02 0x0008>; - opp-hz = /bits/ 64 <760000000>; - }; - - opp@760000000_900_2_3 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x04 0x0008>; - opp-hz = /bits/ 64 <760000000>; - }; - - opp@760000000_900_1_4 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x02 0x0010>; - opp-hz = /bits/ 64 <760000000>; - }; - - opp@760000000_900_2_4 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x04 0x0010>; - opp-hz = /bits/ 64 <760000000>; - }; - - opp@760000000_900_1_7 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x02 0x0080>; - opp-hz = /bits/ 64 <760000000>; - }; - - opp@760000000_900_2_7 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x04 0x0080>; - opp-hz = /bits/ 64 <760000000>; - }; - - opp@760000000_900_1_8 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x02 0x0100>; - opp-hz = /bits/ 64 <760000000>; - }; - - opp@760000000_900_2_8 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x04 0x0100>; - opp-hz = /bits/ 64 <760000000>; - }; - - opp@760000000_912 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x1F 0x0200>; - opp-hz = /bits/ 64 <760000000>; - }; - - opp@760000000_975 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x01 0x0192>; - opp-hz = /bits/ 64 <760000000>; - }; - - opp@816000000_850 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x1F 0x0400>; - opp-hz = /bits/ 64 <816000000>; - }; - - opp@816000000_912 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x1F 0x0200>; - opp-hz = /bits/ 64 <816000000>; - }; - - opp@860000000_850 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x0C 0x0001>; - opp-hz = /bits/ 64 <860000000>; - }; - - opp@860000000_900 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x02 0x0001>; - opp-hz = /bits/ 64 <860000000>; - }; - - opp@860000000_900_2_1 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x04 0x0002>; - opp-hz = /bits/ 64 <860000000>; - }; - - opp@860000000_900_3_1 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x08 0x0002>; - opp-hz = /bits/ 64 <860000000>; - }; - - opp@860000000_900_2_2 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x04 0x0004>; - opp-hz = /bits/ 64 <860000000>; - }; - - opp@860000000_900_3_2 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x08 0x0004>; - opp-hz = /bits/ 64 <860000000>; - }; - - opp@860000000_900_2_3 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x04 0x0008>; - opp-hz = /bits/ 64 <860000000>; - }; - - opp@860000000_900_3_3 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x08 0x0008>; - opp-hz = /bits/ 64 <860000000>; - }; - - opp@860000000_900_2_4 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x04 0x0010>; - opp-hz = /bits/ 64 <860000000>; - }; - - opp@860000000_900_3_4 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x08 0x0010>; - opp-hz = /bits/ 64 <860000000>; - }; - - opp@860000000_900_2_7 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x04 0x0080>; - opp-hz = /bits/ 64 <860000000>; - }; - - opp@860000000_900_3_7 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x08 0x0080>; - opp-hz = /bits/ 64 <860000000>; - }; - - opp@860000000_900_4_7 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x10 0x0080>; - opp-hz = /bits/ 64 <860000000>; - }; - - opp@860000000_900_2_8 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x04 0x0100>; - opp-hz = /bits/ 64 <860000000>; - }; - - opp@860000000_900_3_8 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x08 0x0100>; - opp-hz = /bits/ 64 <860000000>; - }; - - opp@860000000_900_4_8 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x10 0x0100>; - opp-hz = /bits/ 64 <860000000>; - }; - - opp@860000000_975 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x01 0x0001>; - opp-hz = /bits/ 64 <860000000>; - }; - - opp@860000000_975_1_1 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x02 0x0002>; - opp-hz = /bits/ 64 <860000000>; - }; - - opp@860000000_975_1_2 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x02 0x0004>; - opp-hz = /bits/ 64 <860000000>; - }; - - opp@860000000_975_1_3 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x02 0x0008>; - opp-hz = /bits/ 64 <860000000>; - }; - - opp@860000000_975_1_4 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x02 0x0010>; - opp-hz = /bits/ 64 <860000000>; - }; - - opp@860000000_975_1_7 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x02 0x0080>; - opp-hz = /bits/ 64 <860000000>; - }; - - opp@860000000_975_1_8 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x02 0x0100>; - opp-hz = /bits/ 64 <860000000>; - }; - - opp@860000000_1000 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x01 0x0192>; - opp-hz = /bits/ 64 <860000000>; - }; - - opp@910000000_900 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x18 0x3060>; - opp-hz = /bits/ 64 <910000000>; - }; - - opp@1000000000_900 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x0C 0x0001>; - opp-hz = /bits/ 64 <1000000000>; - }; - - opp@1000000000_975 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x03 0x0001>; - opp-hz = /bits/ 64 <1000000000>; - }; - - opp@1000000000_975_2_1 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x04 0x0002>; - opp-hz = /bits/ 64 <1000000000>; - }; - - opp@1000000000_975_3_1 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x08 0x0002>; - opp-hz = /bits/ 64 <1000000000>; - }; - - opp@1000000000_975_2_2 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x04 0x0004>; - opp-hz = /bits/ 64 <1000000000>; - }; - - opp@1000000000_975_3_2 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x08 0x0004>; - opp-hz = /bits/ 64 <1000000000>; - }; - - opp@1000000000_975_2_3 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x04 0x0008>; - opp-hz = /bits/ 64 <1000000000>; - }; - - opp@1000000000_975_3_3 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x08 0x0008>; - opp-hz = /bits/ 64 <1000000000>; - }; - - opp@1000000000_975_2_4 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x04 0x0010>; - opp-hz = /bits/ 64 <1000000000>; - }; - - opp@1000000000_975_3_4 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x08 0x0010>; - opp-hz = /bits/ 64 <1000000000>; - }; - - opp@1000000000_975_2_7 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x04 0x0080>; - opp-hz = /bits/ 64 <1000000000>; - }; - - opp@1000000000_975_3_7 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x08 0x0080>; - opp-hz = /bits/ 64 <1000000000>; - }; - - opp@1000000000_975_4_7 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x10 0x0080>; - opp-hz = /bits/ 64 <1000000000>; - }; - - opp@1000000000_975_2_8 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x04 0x0100>; - opp-hz = /bits/ 64 <1000000000>; - }; - - opp@1000000000_975_3_8 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x08 0x0100>; - opp-hz = /bits/ 64 <1000000000>; - }; - - opp@1000000000_975_4_8 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x10 0x0100>; - opp-hz = /bits/ 64 <1000000000>; - }; - - opp@1000000000_1000 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x02 0x019E>; - opp-hz = /bits/ 64 <1000000000>; - }; - - opp@1000000000_1025 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x01 0x0192>; - opp-hz = /bits/ 64 <1000000000>; - }; - - opp@1100000000_900 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x08 0x0001>; - opp-hz = /bits/ 64 <1100000000>; - }; - - opp@1100000000_975 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x06 0x0001>; - opp-hz = /bits/ 64 <1100000000>; - }; - - opp@1100000000_975_3_1 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x08 0x0002>; - opp-hz = /bits/ 64 <1100000000>; - }; - - opp@1100000000_975_3_2 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x08 0x0004>; - opp-hz = /bits/ 64 <1100000000>; - }; - - opp@1100000000_975_3_3 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x08 0x0008>; - opp-hz = /bits/ 64 <1100000000>; - }; - - opp@1100000000_975_3_4 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x08 0x0010>; - opp-hz = /bits/ 64 <1100000000>; - }; - - opp@1100000000_975_3_7 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x08 0x0080>; - opp-hz = /bits/ 64 <1100000000>; - }; - - opp@1100000000_975_4_7 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x10 0x0080>; - opp-hz = /bits/ 64 <1100000000>; - }; - - opp@1100000000_975_3_8 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x08 0x0100>; - opp-hz = /bits/ 64 <1100000000>; - }; - - opp@1100000000_975_4_8 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x10 0x0100>; - opp-hz = /bits/ 64 <1100000000>; - }; - - opp@1100000000_1000 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x01 0x0001>; - opp-hz = /bits/ 64 <1100000000>; - }; - - opp@1100000000_1000_2_1 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x04 0x0002>; - opp-hz = /bits/ 64 <1100000000>; - }; - - opp@1100000000_1000_2_2 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x04 0x0004>; - opp-hz = /bits/ 64 <1100000000>; - }; - - opp@1100000000_1000_2_3 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x04 0x0008>; - opp-hz = /bits/ 64 <1100000000>; - }; - - opp@1100000000_1000_2_4 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x04 0x0010>; - opp-hz = /bits/ 64 <1100000000>; - }; - - opp@1100000000_1000_2_7 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x04 0x0080>; - opp-hz = /bits/ 64 <1100000000>; - }; - - opp@1100000000_1000_2_8 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x04 0x0100>; - opp-hz = /bits/ 64 <1100000000>; - }; - - opp@1100000000_1025 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x02 0x019E>; - opp-hz = /bits/ 64 <1100000000>; - }; - - opp@1100000000_1075 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x01 0x0192>; - opp-hz = /bits/ 64 <1100000000>; - }; - - opp@1150000000_975 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x18 0x3060>; - opp-hz = /bits/ 64 <1150000000>; - }; - - opp@1200000000_975 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x08 0x0001>; - opp-hz = /bits/ 64 <1200000000>; - }; - - opp@1200000000_1000 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x04 0x0001>; - opp-hz = /bits/ 64 <1200000000>; - }; - - opp@1200000000_1000_3_1 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x08 0x0002>; - opp-hz = /bits/ 64 <1200000000>; - }; - - opp@1200000000_1000_3_2 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x08 0x0004>; - opp-hz = /bits/ 64 <1200000000>; - }; - - opp@1200000000_1000_3_3 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x08 0x0008>; - opp-hz = /bits/ 64 <1200000000>; - }; - - opp@1200000000_1000_3_4 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x08 0x0010>; - opp-hz = /bits/ 64 <1200000000>; - }; - - opp@1200000000_1000_3_7 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x08 0x0080>; - opp-hz = /bits/ 64 <1200000000>; - }; - - opp@1200000000_1000_4_7 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x10 0x0080>; - opp-hz = /bits/ 64 <1200000000>; - }; - - opp@1200000000_1000_3_8 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x08 0x0100>; - opp-hz = /bits/ 64 <1200000000>; - }; - - opp@1200000000_1000_4_8 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x10 0x0100>; - opp-hz = /bits/ 64 <1200000000>; - }; - - opp@1200000000_1025 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x02 0x0001>; - opp-hz = /bits/ 64 <1200000000>; - }; - - opp@1200000000_1025_2_1 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x04 0x0002>; - opp-hz = /bits/ 64 <1200000000>; - }; - - opp@1200000000_1025_2_2 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x04 0x0004>; - opp-hz = /bits/ 64 <1200000000>; - }; - - opp@1200000000_1025_2_3 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x04 0x0008>; - opp-hz = /bits/ 64 <1200000000>; - }; - - opp@1200000000_1025_2_4 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x04 0x0010>; - opp-hz = /bits/ 64 <1200000000>; - }; - - opp@1200000000_1025_2_7 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x04 0x0080>; - opp-hz = /bits/ 64 <1200000000>; - }; - - opp@1200000000_1025_2_8 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x04 0x0100>; - opp-hz = /bits/ 64 <1200000000>; - }; - - opp@1200000000_1050 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x02 0x019E>; - opp-hz = /bits/ 64 <1200000000>; - }; - - opp@1200000000_1075 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x01 0x0001>; - opp-hz = /bits/ 64 <1200000000>; - }; - - opp@1200000000_1100 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x01 0x0192>; - opp-hz = /bits/ 64 <1200000000>; - }; - - opp@1300000000_1000 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x08 0x0001>; - opp-hz = /bits/ 64 <1300000000>; - }; - - opp@1300000000_1000_4_7 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x10 0x0080>; - opp-hz = /bits/ 64 <1300000000>; - }; - - opp@1300000000_1000_4_8 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x10 0x0100>; - opp-hz = /bits/ 64 <1300000000>; - }; - - opp@1300000000_1025 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x04 0x0001>; - opp-hz = /bits/ 64 <1300000000>; - }; - - opp@1300000000_1025_3_1 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x08 0x0002>; - opp-hz = /bits/ 64 <1300000000>; - }; - - opp@1300000000_1025_3_7 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x08 0x0080>; - opp-hz = /bits/ 64 <1300000000>; - }; - - opp@1300000000_1025_3_8 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x08 0x0100>; - opp-hz = /bits/ 64 <1300000000>; - }; - - opp@1300000000_1050 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x12 0x3061>; - opp-hz = /bits/ 64 <1300000000>; - }; - - opp@1300000000_1050_2_1 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x04 0x0002>; - opp-hz = /bits/ 64 <1300000000>; - }; - - opp@1300000000_1050_3_2 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x08 0x0004>; - opp-hz = /bits/ 64 <1300000000>; - }; - - opp@1300000000_1050_3_3 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x08 0x0008>; - opp-hz = /bits/ 64 <1300000000>; - }; - - opp@1300000000_1050_3_4 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x08 0x0010>; - opp-hz = /bits/ 64 <1300000000>; - }; - - opp@1300000000_1050_3_5 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x08 0x0020>; - opp-hz = /bits/ 64 <1300000000>; - }; - - opp@1300000000_1050_3_6 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x08 0x0040>; - opp-hz = /bits/ 64 <1300000000>; - }; - - opp@1300000000_1050_2_7 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x04 0x0080>; - opp-hz = /bits/ 64 <1300000000>; - }; - - opp@1300000000_1050_2_8 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x04 0x0100>; - opp-hz = /bits/ 64 <1300000000>; - }; - - opp@1300000000_1050_3_12 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x08 0x1000>; - opp-hz = /bits/ 64 <1300000000>; - }; - - opp@1300000000_1050_3_13 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x08 0x2000>; - opp-hz = /bits/ 64 <1300000000>; - }; - - opp@1300000000_1075 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x02 0x0182>; - opp-hz = /bits/ 64 <1300000000>; - }; - - opp@1300000000_1075_2_2 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x04 0x0004>; - opp-hz = /bits/ 64 <1300000000>; - }; - - opp@1300000000_1075_2_3 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x04 0x0008>; - opp-hz = /bits/ 64 <1300000000>; - }; - - opp@1300000000_1075_2_4 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x04 0x0010>; - opp-hz = /bits/ 64 <1300000000>; - }; - - opp@1300000000_1100 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x02 0x001C>; - opp-hz = /bits/ 64 <1300000000>; - }; - - opp@1300000000_1125 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x01 0x0001>; - opp-hz = /bits/ 64 <1300000000>; - }; - - opp@1300000000_1150 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x01 0x0182>; - opp-hz = /bits/ 64 <1300000000>; - }; - - opp@1300000000_1175 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x01 0x0010>; - opp-hz = /bits/ 64 <1300000000>; - }; - - opp@1400000000_1100 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x18 0x307C>; - opp-hz = /bits/ 64 <1400000000>; - }; - - opp@1400000000_1125 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x04 0x000C>; - opp-hz = /bits/ 64 <1400000000>; - }; - - opp@1400000000_1150 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x02 0x000C>; - opp-hz = /bits/ 64 <1400000000>; - }; - - opp@1400000000_1150_2_4 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x04 0x0010>; - opp-hz = /bits/ 64 <1400000000>; - }; - - opp@1400000000_1175 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x02 0x0010>; - opp-hz = /bits/ 64 <1400000000>; - }; - - opp@1400000000_1237 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x01 0x0010>; - opp-hz = /bits/ 64 <1400000000>; - }; - - opp@1500000000_1125 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x08 0x0010>; - opp-hz = /bits/ 64 <1500000000>; - }; - - opp@1500000000_1125_4_5 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x10 0x0020>; - opp-hz = /bits/ 64 <1500000000>; - }; - - opp@1500000000_1125_4_6 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x10 0x0040>; - opp-hz = /bits/ 64 <1500000000>; - }; - - opp@1500000000_1125_4_12 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x10 0x1000>; - opp-hz = /bits/ 64 <1500000000>; - }; - - opp@1500000000_1125_4_13 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x10 0x2000>; - opp-hz = /bits/ 64 <1500000000>; - }; - - opp@1500000000_1150 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x04 0x0010>; - opp-hz = /bits/ 64 <1500000000>; - }; - - opp@1500000000_1150_3_5 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x08 0x0020>; - opp-hz = /bits/ 64 <1500000000>; - }; - - opp@1500000000_1150_3_6 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x08 0x0040>; - opp-hz = /bits/ 64 <1500000000>; - }; - - opp@1500000000_1150_3_12 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x08 0x1000>; - opp-hz = /bits/ 64 <1500000000>; - }; - - opp@1500000000_1150_3_13 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x08 0x2000>; - opp-hz = /bits/ 64 <1500000000>; - }; - - opp@1500000000_1200 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x02 0x0010>; - opp-hz = /bits/ 64 <1500000000>; - }; - - opp@1500000000_1237 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x01 0x0010>; - opp-hz = /bits/ 64 <1500000000>; - }; - - opp@1600000000_1212 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x10 0x3060>; - opp-hz = /bits/ 64 <1600000000>; - }; - - opp@1600000000_1237 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x08 0x3060>; - opp-hz = /bits/ 64 <1600000000>; - }; - - opp@1700000000_1212 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x10 0x3060>; - opp-hz = /bits/ 64 <1700000000>; - }; - - opp@1700000000_1237 { - clock-latency-ns = <100000>; - opp-supported-hw = <0x08 0x3060>; - opp-hz = /bits/ 64 <1700000000>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/tegra30.dtsi b/sys/gnu/dts/arm/tegra30.dtsi deleted file mode 100644 index 55ae050042c..00000000000 --- a/sys/gnu/dts/arm/tegra30.dtsi +++ /dev/null @@ -1,1046 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include -#include -#include -#include -#include - -/ { - compatible = "nvidia,tegra30"; - interrupt-parent = <&lic>; - #address-cells = <1>; - #size-cells = <1>; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x0>; - }; - - pcie@3000 { - compatible = "nvidia,tegra30-pcie"; - device_type = "pci"; - reg = <0x00003000 0x00000800 /* PADS registers */ - 0x00003800 0x00000200 /* AFI registers */ - 0x10000000 0x10000000>; /* configuration space */ - reg-names = "pads", "afi", "cs"; - interrupts = ; /* MSI interrupt */ - interrupt-names = "intr", "msi"; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; - - bus-range = <0x00 0xff>; - #address-cells = <3>; - #size-cells = <2>; - - ranges = <0x82000000 0 0x00000000 0x00000000 0 0x00001000 /* port 0 configuration space */ - 0x82000000 0 0x00001000 0x00001000 0 0x00001000 /* port 1 configuration space */ - 0x82000000 0 0x00004000 0x00004000 0 0x00001000 /* port 2 configuration space */ - 0x81000000 0 0 0x02000000 0 0x00010000 /* downstream I/O */ - 0x82000000 0 0x20000000 0x20000000 0 0x08000000 /* non-prefetchable memory */ - 0xc2000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */ - - clocks = <&tegra_car TEGRA30_CLK_PCIE>, - <&tegra_car TEGRA30_CLK_AFI>, - <&tegra_car TEGRA30_CLK_PLL_E>, - <&tegra_car TEGRA30_CLK_CML0>; - clock-names = "pex", "afi", "pll_e", "cml"; - resets = <&tegra_car 70>, - <&tegra_car 72>, - <&tegra_car 74>; - reset-names = "pex", "afi", "pcie_x"; - status = "disabled"; - - pci@1,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>; - reg = <0x000800 0 0 0 0>; - bus-range = <0x00 0xff>; - status = "disabled"; - - #address-cells = <3>; - #size-cells = <2>; - ranges; - - nvidia,num-lanes = <2>; - }; - - pci@2,0 { - device_type = "pci"; - assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>; - reg = <0x001000 0 0 0 0>; - bus-range = <0x00 0xff>; - status = "disabled"; - - #address-cells = <3>; - #size-cells = <2>; - ranges; - - nvidia,num-lanes = <2>; - }; - - pci@3,0 { - device_type = "pci"; - assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>; - reg = <0x001800 0 0 0 0>; - bus-range = <0x00 0xff>; - status = "disabled"; - - #address-cells = <3>; - #size-cells = <2>; - ranges; - - nvidia,num-lanes = <2>; - }; - }; - - iram@40000000 { - compatible = "mmio-sram"; - reg = <0x40000000 0x40000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x40000000 0x40000>; - - vde_pool: vde@400 { - reg = <0x400 0x3fc00>; - pool; - }; - }; - - host1x@50000000 { - compatible = "nvidia,tegra30-host1x", "simple-bus"; - reg = <0x50000000 0x00024000>; - interrupts = , /* syncpt */ - ; /* general */ - clocks = <&tegra_car TEGRA30_CLK_HOST1X>; - resets = <&tegra_car 28>; - reset-names = "host1x"; - iommus = <&mc TEGRA_SWGROUP_HC>; - - #address-cells = <1>; - #size-cells = <1>; - - ranges = <0x54000000 0x54000000 0x04000000>; - - mpe@54040000 { - compatible = "nvidia,tegra30-mpe"; - reg = <0x54040000 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA30_CLK_MPE>; - resets = <&tegra_car 60>; - reset-names = "mpe"; - - iommus = <&mc TEGRA_SWGROUP_MPE>; - }; - - vi@54080000 { - compatible = "nvidia,tegra30-vi"; - reg = <0x54080000 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA30_CLK_VI>; - resets = <&tegra_car 20>; - reset-names = "vi"; - - iommus = <&mc TEGRA_SWGROUP_VI>; - }; - - epp@540c0000 { - compatible = "nvidia,tegra30-epp"; - reg = <0x540c0000 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA30_CLK_EPP>; - resets = <&tegra_car 19>; - reset-names = "epp"; - - iommus = <&mc TEGRA_SWGROUP_EPP>; - }; - - isp@54100000 { - compatible = "nvidia,tegra30-isp"; - reg = <0x54100000 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA30_CLK_ISP>; - resets = <&tegra_car 23>; - reset-names = "isp"; - - iommus = <&mc TEGRA_SWGROUP_ISP>; - }; - - gr2d@54140000 { - compatible = "nvidia,tegra30-gr2d"; - reg = <0x54140000 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA30_CLK_GR2D>; - resets = <&tegra_car 21>; - reset-names = "2d"; - - iommus = <&mc TEGRA_SWGROUP_G2>; - }; - - gr3d@54180000 { - compatible = "nvidia,tegra30-gr3d"; - reg = <0x54180000 0x00040000>; - clocks = <&tegra_car TEGRA30_CLK_GR3D - &tegra_car TEGRA30_CLK_GR3D2>; - clock-names = "3d", "3d2"; - resets = <&tegra_car 24>, - <&tegra_car 98>; - reset-names = "3d", "3d2"; - - iommus = <&mc TEGRA_SWGROUP_NV>, - <&mc TEGRA_SWGROUP_NV2>; - }; - - dc@54200000 { - compatible = "nvidia,tegra30-dc", "nvidia,tegra20-dc"; - reg = <0x54200000 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA30_CLK_DISP1>, - <&tegra_car TEGRA30_CLK_PLL_P>; - clock-names = "dc", "parent"; - resets = <&tegra_car 27>; - reset-names = "dc"; - - iommus = <&mc TEGRA_SWGROUP_DC>; - - nvidia,head = <0>; - - rgb { - status = "disabled"; - }; - }; - - dc@54240000 { - compatible = "nvidia,tegra30-dc"; - reg = <0x54240000 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA30_CLK_DISP2>, - <&tegra_car TEGRA30_CLK_PLL_P>; - clock-names = "dc", "parent"; - resets = <&tegra_car 26>; - reset-names = "dc"; - - iommus = <&mc TEGRA_SWGROUP_DCB>; - - nvidia,head = <1>; - - rgb { - status = "disabled"; - }; - }; - - hdmi@54280000 { - compatible = "nvidia,tegra30-hdmi"; - reg = <0x54280000 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA30_CLK_HDMI>, - <&tegra_car TEGRA30_CLK_PLL_D2_OUT0>; - clock-names = "hdmi", "parent"; - resets = <&tegra_car 51>; - reset-names = "hdmi"; - status = "disabled"; - }; - - tvo@542c0000 { - compatible = "nvidia,tegra30-tvo"; - reg = <0x542c0000 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA30_CLK_TVO>; - status = "disabled"; - }; - - dsi@54300000 { - compatible = "nvidia,tegra30-dsi"; - reg = <0x54300000 0x00040000>; - clocks = <&tegra_car TEGRA30_CLK_DSIA>; - resets = <&tegra_car 48>; - reset-names = "dsi"; - status = "disabled"; - }; - }; - - timer@50040600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0x50040600 0x20>; - interrupt-parent = <&intc>; - interrupts = ; - clocks = <&tegra_car TEGRA30_CLK_TWD>; - }; - - intc: interrupt-controller@50041000 { - compatible = "arm,cortex-a9-gic"; - reg = <0x50041000 0x1000 - 0x50040100 0x0100>; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&intc>; - }; - - cache-controller@50043000 { - compatible = "arm,pl310-cache"; - reg = <0x50043000 0x1000>; - arm,data-latency = <6 6 2>; - arm,tag-latency = <5 5 2>; - cache-unified; - cache-level = <2>; - }; - - lic: interrupt-controller@60004000 { - compatible = "nvidia,tegra30-ictlr"; - reg = <0x60004000 0x100>, - <0x60004100 0x50>, - <0x60004200 0x50>, - <0x60004300 0x50>, - <0x60004400 0x50>; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&intc>; - }; - - timer@60005000 { - compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer"; - reg = <0x60005000 0x400>; - interrupts = , - , - , - , - , - ; - clocks = <&tegra_car TEGRA30_CLK_TIMER>; - }; - - tegra_car: clock@60006000 { - compatible = "nvidia,tegra30-car"; - reg = <0x60006000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - flow-controller@60007000 { - compatible = "nvidia,tegra30-flowctrl"; - reg = <0x60007000 0x1000>; - }; - - apbdma: dma@6000a000 { - compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma"; - reg = <0x6000a000 0x1400>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - clocks = <&tegra_car TEGRA30_CLK_APBDMA>; - resets = <&tegra_car 34>; - reset-names = "dma"; - #dma-cells = <1>; - }; - - ahb: ahb@6000c000 { - compatible = "nvidia,tegra30-ahb"; - reg = <0x6000c000 0x150>; /* AHB Arbitration + Gizmo Controller */ - }; - - actmon@6000c800 { - compatible = "nvidia,tegra30-actmon"; - reg = <0x6000c800 0x400>; - interrupts = ; - clocks = <&tegra_car TEGRA30_CLK_ACTMON>, - <&tegra_car TEGRA30_CLK_EMC>; - clock-names = "actmon", "emc"; - resets = <&tegra_car TEGRA30_CLK_ACTMON>; - reset-names = "actmon"; - }; - - gpio: gpio@6000d000 { - compatible = "nvidia,tegra30-gpio"; - reg = <0x6000d000 0x1000>; - interrupts = , - , - , - , - , - , - , - ; - #gpio-cells = <2>; - gpio-controller; - #interrupt-cells = <2>; - interrupt-controller; - /* - gpio-ranges = <&pinmux 0 0 248>; - */ - }; - - vde@6001a000 { - compatible = "nvidia,tegra30-vde", "nvidia,tegra20-vde"; - reg = <0x6001a000 0x1000 /* Syntax Engine */ - 0x6001b000 0x1000 /* Video Bitstream Engine */ - 0x6001c000 0x100 /* Macroblock Engine */ - 0x6001c200 0x100 /* Post-processing Engine */ - 0x6001c400 0x100 /* Motion Compensation Engine */ - 0x6001c600 0x100 /* Transform Engine */ - 0x6001c800 0x100 /* Pixel prediction block */ - 0x6001ca00 0x100 /* Video DMA */ - 0x6001d800 0x400>; /* Video frame controls */ - reg-names = "sxe", "bsev", "mbe", "ppe", "mce", - "tfe", "ppb", "vdma", "frameid"; - iram = <&vde_pool>; /* IRAM region */ - interrupts = , /* Sync token interrupt */ - , /* BSE-V interrupt */ - ; /* SXE interrupt */ - interrupt-names = "sync-token", "bsev", "sxe"; - clocks = <&tegra_car TEGRA30_CLK_VDE>; - reset-names = "vde", "mc"; - resets = <&tegra_car 61>, <&mc TEGRA30_MC_RESET_VDE>; - iommus = <&mc TEGRA_SWGROUP_VDE>; - }; - - apbmisc@70000800 { - compatible = "nvidia,tegra30-apbmisc", "nvidia,tegra20-apbmisc"; - reg = <0x70000800 0x64 /* Chip revision */ - 0x70000008 0x04>; /* Strapping options */ - }; - - pinmux: pinmux@70000868 { - compatible = "nvidia,tegra30-pinmux"; - reg = <0x70000868 0xd4 /* Pad control registers */ - 0x70003000 0x3e4>; /* Mux registers */ - }; - - /* - * There are two serial driver i.e. 8250 based simple serial - * driver and APB DMA based serial driver for higher baudrate - * and performace. To enable the 8250 based driver, the compatible - * is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable - * the APB DMA based serial driver, the compatible is - * "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart". - */ - uarta: serial@70006000 { - compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; - reg = <0x70006000 0x40>; - reg-shift = <2>; - interrupts = ; - clocks = <&tegra_car TEGRA30_CLK_UARTA>; - resets = <&tegra_car 6>; - reset-names = "serial"; - dmas = <&apbdma 8>, <&apbdma 8>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uartb: serial@70006040 { - compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; - reg = <0x70006040 0x40>; - reg-shift = <2>; - interrupts = ; - clocks = <&tegra_car TEGRA30_CLK_UARTB>; - resets = <&tegra_car 7>; - reset-names = "serial"; - dmas = <&apbdma 9>, <&apbdma 9>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uartc: serial@70006200 { - compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; - reg = <0x70006200 0x100>; - reg-shift = <2>; - interrupts = ; - clocks = <&tegra_car TEGRA30_CLK_UARTC>; - resets = <&tegra_car 55>; - reset-names = "serial"; - dmas = <&apbdma 10>, <&apbdma 10>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uartd: serial@70006300 { - compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; - reg = <0x70006300 0x100>; - reg-shift = <2>; - interrupts = ; - clocks = <&tegra_car TEGRA30_CLK_UARTD>; - resets = <&tegra_car 65>; - reset-names = "serial"; - dmas = <&apbdma 19>, <&apbdma 19>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uarte: serial@70006400 { - compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; - reg = <0x70006400 0x100>; - reg-shift = <2>; - interrupts = ; - clocks = <&tegra_car TEGRA30_CLK_UARTE>; - resets = <&tegra_car 66>; - reset-names = "serial"; - dmas = <&apbdma 20>, <&apbdma 20>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - gmi@70009000 { - compatible = "nvidia,tegra30-gmi"; - reg = <0x70009000 0x1000>; - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0x48000000 0x7ffffff>; - clocks = <&tegra_car TEGRA30_CLK_NOR>; - clock-names = "gmi"; - resets = <&tegra_car 42>; - reset-names = "gmi"; - status = "disabled"; - }; - - pwm: pwm@7000a000 { - compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm"; - reg = <0x7000a000 0x100>; - #pwm-cells = <2>; - clocks = <&tegra_car TEGRA30_CLK_PWM>; - resets = <&tegra_car 17>; - reset-names = "pwm"; - status = "disabled"; - }; - - rtc@7000e000 { - compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc"; - reg = <0x7000e000 0x100>; - interrupts = ; - clocks = <&tegra_car TEGRA30_CLK_RTC>; - }; - - i2c@7000c000 { - compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; - reg = <0x7000c000 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA30_CLK_I2C1>, - <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; - clock-names = "div-clk", "fast-clk"; - resets = <&tegra_car 12>; - reset-names = "i2c"; - dmas = <&apbdma 21>, <&apbdma 21>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c@7000c400 { - compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; - reg = <0x7000c400 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA30_CLK_I2C2>, - <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; - clock-names = "div-clk", "fast-clk"; - resets = <&tegra_car 54>; - reset-names = "i2c"; - dmas = <&apbdma 22>, <&apbdma 22>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c@7000c500 { - compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; - reg = <0x7000c500 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA30_CLK_I2C3>, - <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; - clock-names = "div-clk", "fast-clk"; - resets = <&tegra_car 67>; - reset-names = "i2c"; - dmas = <&apbdma 23>, <&apbdma 23>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c@7000c700 { - compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; - reg = <0x7000c700 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA30_CLK_I2C4>, - <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; - resets = <&tegra_car 103>; - reset-names = "i2c"; - clock-names = "div-clk", "fast-clk"; - dmas = <&apbdma 26>, <&apbdma 26>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c@7000d000 { - compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; - reg = <0x7000d000 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA30_CLK_I2C5>, - <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; - clock-names = "div-clk", "fast-clk"; - resets = <&tegra_car 47>; - reset-names = "i2c"; - dmas = <&apbdma 24>, <&apbdma 24>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi@7000d400 { - compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; - reg = <0x7000d400 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA30_CLK_SBC1>; - resets = <&tegra_car 41>; - reset-names = "spi"; - dmas = <&apbdma 15>, <&apbdma 15>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi@7000d600 { - compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; - reg = <0x7000d600 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA30_CLK_SBC2>; - resets = <&tegra_car 44>; - reset-names = "spi"; - dmas = <&apbdma 16>, <&apbdma 16>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi@7000d800 { - compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; - reg = <0x7000d800 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA30_CLK_SBC3>; - resets = <&tegra_car 46>; - reset-names = "spi"; - dmas = <&apbdma 17>, <&apbdma 17>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi@7000da00 { - compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; - reg = <0x7000da00 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA30_CLK_SBC4>; - resets = <&tegra_car 68>; - reset-names = "spi"; - dmas = <&apbdma 18>, <&apbdma 18>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi@7000dc00 { - compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; - reg = <0x7000dc00 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA30_CLK_SBC5>; - resets = <&tegra_car 104>; - reset-names = "spi"; - dmas = <&apbdma 27>, <&apbdma 27>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi@7000de00 { - compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; - reg = <0x7000de00 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA30_CLK_SBC6>; - resets = <&tegra_car 106>; - reset-names = "spi"; - dmas = <&apbdma 28>, <&apbdma 28>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - kbc@7000e200 { - compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc"; - reg = <0x7000e200 0x100>; - interrupts = ; - clocks = <&tegra_car TEGRA30_CLK_KBC>; - resets = <&tegra_car 36>; - reset-names = "kbc"; - status = "disabled"; - }; - - pmc@7000e400 { - compatible = "nvidia,tegra30-pmc"; - reg = <0x7000e400 0x400>; - clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>; - clock-names = "pclk", "clk32k_in"; - }; - - mc: memory-controller@7000f000 { - compatible = "nvidia,tegra30-mc"; - reg = <0x7000f000 0x400>; - clocks = <&tegra_car TEGRA30_CLK_MC>; - clock-names = "mc"; - - interrupts = ; - - #iommu-cells = <1>; - #reset-cells = <1>; - }; - - memory-controller@7000f400 { - compatible = "nvidia,tegra30-emc"; - reg = <0x7000f400 0x400>; - interrupts = ; - clocks = <&tegra_car TEGRA30_CLK_EMC>; - - nvidia,memory-controller = <&mc>; - }; - - fuse@7000f800 { - compatible = "nvidia,tegra30-efuse"; - reg = <0x7000f800 0x400>; - clocks = <&tegra_car TEGRA30_CLK_FUSE>; - clock-names = "fuse"; - resets = <&tegra_car 39>; - reset-names = "fuse"; - }; - - hda@70030000 { - compatible = "nvidia,tegra30-hda"; - reg = <0x70030000 0x10000>; - interrupts = ; - clocks = <&tegra_car TEGRA30_CLK_HDA>, - <&tegra_car TEGRA30_CLK_HDA2HDMI>, - <&tegra_car TEGRA30_CLK_HDA2CODEC_2X>; - clock-names = "hda", "hda2hdmi", "hda2codec_2x"; - resets = <&tegra_car 125>, /* hda */ - <&tegra_car 128>, /* hda2hdmi */ - <&tegra_car 111>; /* hda2codec_2x */ - reset-names = "hda", "hda2hdmi", "hda2codec_2x"; - status = "disabled"; - }; - - ahub@70080000 { - compatible = "nvidia,tegra30-ahub"; - reg = <0x70080000 0x200 - 0x70080200 0x100>; - interrupts = ; - clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>, - <&tegra_car TEGRA30_CLK_APBIF>; - clock-names = "d_audio", "apbif"; - resets = <&tegra_car 106>, /* d_audio */ - <&tegra_car 107>, /* apbif */ - <&tegra_car 30>, /* i2s0 */ - <&tegra_car 11>, /* i2s1 */ - <&tegra_car 18>, /* i2s2 */ - <&tegra_car 101>, /* i2s3 */ - <&tegra_car 102>, /* i2s4 */ - <&tegra_car 108>, /* dam0 */ - <&tegra_car 109>, /* dam1 */ - <&tegra_car 110>, /* dam2 */ - <&tegra_car 10>; /* spdif */ - reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", - "i2s3", "i2s4", "dam0", "dam1", "dam2", - "spdif"; - dmas = <&apbdma 1>, <&apbdma 1>, - <&apbdma 2>, <&apbdma 2>, - <&apbdma 3>, <&apbdma 3>, - <&apbdma 4>, <&apbdma 4>; - dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2", - "rx3", "tx3"; - ranges; - #address-cells = <1>; - #size-cells = <1>; - - tegra_i2s0: i2s@70080300 { - compatible = "nvidia,tegra30-i2s"; - reg = <0x70080300 0x100>; - nvidia,ahub-cif-ids = <4 4>; - clocks = <&tegra_car TEGRA30_CLK_I2S0>; - resets = <&tegra_car 30>; - reset-names = "i2s"; - status = "disabled"; - }; - - tegra_i2s1: i2s@70080400 { - compatible = "nvidia,tegra30-i2s"; - reg = <0x70080400 0x100>; - nvidia,ahub-cif-ids = <5 5>; - clocks = <&tegra_car TEGRA30_CLK_I2S1>; - resets = <&tegra_car 11>; - reset-names = "i2s"; - status = "disabled"; - }; - - tegra_i2s2: i2s@70080500 { - compatible = "nvidia,tegra30-i2s"; - reg = <0x70080500 0x100>; - nvidia,ahub-cif-ids = <6 6>; - clocks = <&tegra_car TEGRA30_CLK_I2S2>; - resets = <&tegra_car 18>; - reset-names = "i2s"; - status = "disabled"; - }; - - tegra_i2s3: i2s@70080600 { - compatible = "nvidia,tegra30-i2s"; - reg = <0x70080600 0x100>; - nvidia,ahub-cif-ids = <7 7>; - clocks = <&tegra_car TEGRA30_CLK_I2S3>; - resets = <&tegra_car 101>; - reset-names = "i2s"; - status = "disabled"; - }; - - tegra_i2s4: i2s@70080700 { - compatible = "nvidia,tegra30-i2s"; - reg = <0x70080700 0x100>; - nvidia,ahub-cif-ids = <8 8>; - clocks = <&tegra_car TEGRA30_CLK_I2S4>; - resets = <&tegra_car 102>; - reset-names = "i2s"; - status = "disabled"; - }; - }; - - sdhci@78000000 { - compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; - reg = <0x78000000 0x200>; - interrupts = ; - clocks = <&tegra_car TEGRA30_CLK_SDMMC1>; - resets = <&tegra_car 14>; - reset-names = "sdhci"; - status = "disabled"; - }; - - sdhci@78000200 { - compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; - reg = <0x78000200 0x200>; - interrupts = ; - clocks = <&tegra_car TEGRA30_CLK_SDMMC2>; - resets = <&tegra_car 9>; - reset-names = "sdhci"; - status = "disabled"; - }; - - sdhci@78000400 { - compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; - reg = <0x78000400 0x200>; - interrupts = ; - clocks = <&tegra_car TEGRA30_CLK_SDMMC3>; - resets = <&tegra_car 69>; - reset-names = "sdhci"; - status = "disabled"; - }; - - sdhci@78000600 { - compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; - reg = <0x78000600 0x200>; - interrupts = ; - clocks = <&tegra_car TEGRA30_CLK_SDMMC4>; - resets = <&tegra_car 15>; - reset-names = "sdhci"; - status = "disabled"; - }; - - usb@7d000000 { - compatible = "nvidia,tegra30-ehci", "usb-ehci"; - reg = <0x7d000000 0x4000>; - interrupts = ; - phy_type = "utmi"; - clocks = <&tegra_car TEGRA30_CLK_USBD>; - resets = <&tegra_car 22>; - reset-names = "usb"; - nvidia,needs-double-reset; - nvidia,phy = <&phy1>; - status = "disabled"; - }; - - phy1: usb-phy@7d000000 { - compatible = "nvidia,tegra30-usb-phy"; - reg = <0x7d000000 0x4000 0x7d000000 0x4000>; - phy_type = "utmi"; - clocks = <&tegra_car TEGRA30_CLK_USBD>, - <&tegra_car TEGRA30_CLK_PLL_U>, - <&tegra_car TEGRA30_CLK_USBD>; - clock-names = "reg", "pll_u", "utmi-pads"; - resets = <&tegra_car 22>, <&tegra_car 22>; - reset-names = "usb", "utmi-pads"; - nvidia,hssync-start-delay = <9>; - nvidia,idle-wait-delay = <17>; - nvidia,elastic-limit = <16>; - nvidia,term-range-adj = <6>; - nvidia,xcvr-setup = <51>; - nvidia,xcvr-setup-use-fuses; - nvidia,xcvr-lsfslew = <1>; - nvidia,xcvr-lsrslew = <1>; - nvidia,xcvr-hsslew = <32>; - nvidia,hssquelch-level = <2>; - nvidia,hsdiscon-level = <5>; - nvidia,has-utmi-pad-registers; - status = "disabled"; - }; - - usb@7d004000 { - compatible = "nvidia,tegra30-ehci", "usb-ehci"; - reg = <0x7d004000 0x4000>; - interrupts = ; - phy_type = "utmi"; - clocks = <&tegra_car TEGRA30_CLK_USB2>; - resets = <&tegra_car 58>; - reset-names = "usb"; - nvidia,phy = <&phy2>; - status = "disabled"; - }; - - phy2: usb-phy@7d004000 { - compatible = "nvidia,tegra30-usb-phy"; - reg = <0x7d004000 0x4000 0x7d000000 0x4000>; - phy_type = "utmi"; - clocks = <&tegra_car TEGRA30_CLK_USB2>, - <&tegra_car TEGRA30_CLK_PLL_U>, - <&tegra_car TEGRA30_CLK_USBD>; - clock-names = "reg", "pll_u", "utmi-pads"; - resets = <&tegra_car 58>, <&tegra_car 22>; - reset-names = "usb", "utmi-pads"; - nvidia,hssync-start-delay = <9>; - nvidia,idle-wait-delay = <17>; - nvidia,elastic-limit = <16>; - nvidia,term-range-adj = <6>; - nvidia,xcvr-setup = <51>; - nvidia,xcvr-setup-use-fuses; - nvidia,xcvr-lsfslew = <2>; - nvidia,xcvr-lsrslew = <2>; - nvidia,xcvr-hsslew = <32>; - nvidia,hssquelch-level = <2>; - nvidia,hsdiscon-level = <5>; - status = "disabled"; - }; - - usb@7d008000 { - compatible = "nvidia,tegra30-ehci", "usb-ehci"; - reg = <0x7d008000 0x4000>; - interrupts = ; - phy_type = "utmi"; - clocks = <&tegra_car TEGRA30_CLK_USB3>; - resets = <&tegra_car 59>; - reset-names = "usb"; - nvidia,phy = <&phy3>; - status = "disabled"; - }; - - phy3: usb-phy@7d008000 { - compatible = "nvidia,tegra30-usb-phy"; - reg = <0x7d008000 0x4000 0x7d000000 0x4000>; - phy_type = "utmi"; - clocks = <&tegra_car TEGRA30_CLK_USB3>, - <&tegra_car TEGRA30_CLK_PLL_U>, - <&tegra_car TEGRA30_CLK_USBD>; - clock-names = "reg", "pll_u", "utmi-pads"; - resets = <&tegra_car 59>, <&tegra_car 22>; - reset-names = "usb", "utmi-pads"; - nvidia,hssync-start-delay = <0>; - nvidia,idle-wait-delay = <17>; - nvidia,elastic-limit = <16>; - nvidia,term-range-adj = <6>; - nvidia,xcvr-setup = <51>; - nvidia,xcvr-setup-use-fuses; - nvidia,xcvr-lsfslew = <2>; - nvidia,xcvr-lsrslew = <2>; - nvidia,xcvr-hsslew = <32>; - nvidia,hssquelch-level = <2>; - nvidia,hsdiscon-level = <5>; - status = "disabled"; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - clocks = <&tegra_car TEGRA30_CLK_CCLK_G>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <1>; - clocks = <&tegra_car TEGRA30_CLK_CCLK_G>; - }; - - cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <2>; - clocks = <&tegra_car TEGRA30_CLK_CCLK_G>; - }; - - cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <3>; - clocks = <&tegra_car TEGRA30_CLK_CCLK_G>; - }; - }; - - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts = , - , - , - ; - interrupt-affinity = <&{/cpus/cpu@0}>, - <&{/cpus/cpu@1}>, - <&{/cpus/cpu@2}>, - <&{/cpus/cpu@3}>; - }; -}; diff --git a/sys/gnu/dts/arm/tny_a9260.dts b/sys/gnu/dts/arm/tny_a9260.dts deleted file mode 100644 index ef6d586ce88..00000000000 --- a/sys/gnu/dts/arm/tny_a9260.dts +++ /dev/null @@ -1,14 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * tny_a9260.dts - Device Tree file for Caloa TNY A9260 board - * - * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD - */ -/dts-v1/; -#include "at91sam9260.dtsi" -#include "tny_a9260_common.dtsi" - -/ { - model = "Calao TNY A9260"; - compatible = "calao,tny-a9260", "atmel,at91sam9260", "atmel,at91sam9"; -}; diff --git a/sys/gnu/dts/arm/tny_a9260_common.dtsi b/sys/gnu/dts/arm/tny_a9260_common.dtsi deleted file mode 100644 index dd6957b2077..00000000000 --- a/sys/gnu/dts/arm/tny_a9260_common.dtsi +++ /dev/null @@ -1,112 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * tny_a9260_common.dtsi - Device Tree file for Caloa TNY A926x board - * - * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD - */ - -/ { - chosen { - bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock6 rw rootfstype=ubifs"; - }; - - memory { - reg = <0x20000000 0x4000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <12000000>; - }; - }; - - ahb { - apb { - tcb0: timer@fffa0000 { - timer@0 { - compatible = "atmel,tcb-timer"; - reg = <0>, <1>; - }; - - timer@2 { - compatible = "atmel,tcb-timer"; - reg = <2>; - }; - }; - - dbgu: serial@fffff200 { - status = "okay"; - }; - }; - - ebi: ebi@10000000 { - status = "okay"; - - nand_controller: nand-controller { - status = "okay"; - pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>; - pinctrl-names = "default"; - - nand@3 { - reg = <0x3 0x0 0x800000>; - rb-gpios = <&pioC 13 GPIO_ACTIVE_HIGH>; - cs-gpios = <&pioC 14 GPIO_ACTIVE_HIGH>; - nand-bus-width = <8>; - nand-ecc-mode = "soft"; - nand-on-flash-bbt; - label = "atmel_nand"; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - at91bootstrap@0 { - label = "at91bootstrap"; - reg = <0x0 0x20000>; - }; - - barebox@20000 { - label = "barebox"; - reg = <0x20000 0x40000>; - }; - - bareboxenv@60000 { - label = "bareboxenv"; - reg = <0x60000 0x20000>; - }; - - bareboxenv2@80000 { - label = "bareboxenv2"; - reg = <0x80000 0x20000>; - }; - - oftree@80000 { - label = "oftree"; - reg = <0xa0000 0x20000>; - }; - - kernel@a0000 { - label = "kernel"; - reg = <0xc0000 0x400000>; - }; - - rootfs@4a0000 { - label = "rootfs"; - reg = <0x4c0000 0x7800000>; - }; - - data@7ca0000 { - label = "data"; - reg = <0x7cc0000 0x8340000>; - }; - }; - }; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/tny_a9263.dts b/sys/gnu/dts/arm/tny_a9263.dts deleted file mode 100644 index 2820635952e..00000000000 --- a/sys/gnu/dts/arm/tny_a9263.dts +++ /dev/null @@ -1,126 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * usb_a9263.dts - Device Tree file for Caloa USB A9293 board - * - * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD - */ -/dts-v1/; -#include "at91sam9263.dtsi" - -/ { - model = "Calao TNY A9263"; - compatible = "atmel,tny-a9263", "atmel,at91sam9263", "atmel,at91sam9"; - - chosen { - bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock5 rw rootfstype=ubifs"; - }; - - memory { - reg = <0x20000000 0x4000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <12000000>; - }; - }; - - ahb { - apb { - dbgu: serial@ffffee00 { - status = "okay"; - }; - - tcb0: timer@fff7c000 { - timer@0 { - compatible = "atmel,tcb-timer"; - reg = <0>, <1>; - }; - - timer@2 { - compatible = "atmel,tcb-timer"; - reg = <2>; - }; - }; - - usb1: gadget@fff78000 { - atmel,vbus-gpio = <&pioB 11 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - }; - - ebi0: ebi@10000000 { - status = "okay"; - - nand_controller: nand-controller { - status = "okay"; - pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>; - pinctrl-names = "default"; - - nand@3 { - reg = <0x3 0x0 0x800000>; - rb-gpios = <&pioA 22 GPIO_ACTIVE_HIGH>; - cs-gpios = <&pioA 15 GPIO_ACTIVE_HIGH>; - nand-bus-width = <8>; - nand-ecc-mode = "soft"; - nand-on-flash-bbt; - label = "atmel_nand"; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - at91bootstrap@0 { - label = "at91bootstrap"; - reg = <0x0 0x20000>; - }; - - barebox@20000 { - label = "barebox"; - reg = <0x20000 0x40000>; - }; - - bareboxenv@60000 { - label = "bareboxenv"; - reg = <0x60000 0x20000>; - }; - - bareboxenv2@80000 { - label = "bareboxenv2"; - reg = <0x80000 0x20000>; - }; - - oftree@80000 { - label = "oftree"; - reg = <0xa0000 0x20000>; - }; - - kernel@a0000 { - label = "kernel"; - reg = <0xc0000 0x400000>; - }; - - rootfs@4a0000 { - label = "rootfs"; - reg = <0x4c0000 0x7800000>; - }; - - data@7ca0000 { - label = "data"; - reg = <0x7cc0000 0x8340000>; - }; - }; - }; - }; - }; - }; - - i2c-gpio-0 { - status = "okay"; - }; -}; diff --git a/sys/gnu/dts/arm/tny_a9g20.dts b/sys/gnu/dts/arm/tny_a9g20.dts deleted file mode 100644 index 118d766a126..00000000000 --- a/sys/gnu/dts/arm/tny_a9g20.dts +++ /dev/null @@ -1,14 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * tny_a9g20.dts - Device Tree file for Caloa TNY A9G20 board - * - * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD - */ -/dts-v1/; -#include "at91sam9g20.dtsi" -#include "tny_a9260_common.dtsi" - -/ { - model = "Calao TNY A9G20"; - compatible = "calao,tny-a9g20", "atmel,at91sam9g20", "atmel,at91sam9"; -}; diff --git a/sys/gnu/dts/arm/tps6507x.dtsi b/sys/gnu/dts/arm/tps6507x.dtsi deleted file mode 100644 index db4809d308f..00000000000 --- a/sys/gnu/dts/arm/tps6507x.dtsi +++ /dev/null @@ -1,44 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ - */ - -/* - * Integrated Power Management Chip - * http://www.ti.com/lit/ds/symlink/tps65070.pdf - */ - -&tps { - compatible = "ti,tps6507x"; - - regulators { - #address-cells = <1>; - #size-cells = <0>; - - vdcdc1_reg: regulator@0 { - reg = <0>; - regulator-compatible = "VDCDC1"; - }; - - vdcdc2_reg: regulator@1 { - reg = <1>; - regulator-compatible = "VDCDC2"; - }; - - vdcdc3_reg: regulator@2 { - reg = <2>; - regulator-compatible = "VDCDC3"; - }; - - ldo1_reg: regulator@3 { - reg = <3>; - regulator-compatible = "LDO1"; - }; - - ldo2_reg: regulator@4 { - reg = <4>; - regulator-compatible = "LDO2"; - }; - - }; -}; diff --git a/sys/gnu/dts/arm/tps65217.dtsi b/sys/gnu/dts/arm/tps65217.dtsi deleted file mode 100644 index 0d463de5650..00000000000 --- a/sys/gnu/dts/arm/tps65217.dtsi +++ /dev/null @@ -1,68 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ - */ - -/* - * Integrated Power Management Chip - * http://www.ti.com/lit/ds/symlink/tps65217.pdf - */ - -&tps { - compatible = "ti,tps65217"; - interrupt-controller; - #interrupt-cells = <1>; - - charger { - compatible = "ti,tps65217-charger"; - interrupts = <0>, <1>; - interrupt-names = "USB", "AC"; - status = "disabled"; - }; - - pwrbutton { - compatible = "ti,tps65217-pwrbutton"; - interrupts = <2>; - status = "disabled"; - }; - - regulators { - #address-cells = <1>; - #size-cells = <0>; - - dcdc1_reg: regulator@0 { - reg = <0>; - regulator-compatible = "dcdc1"; - }; - - dcdc2_reg: regulator@1 { - reg = <1>; - regulator-compatible = "dcdc2"; - }; - - dcdc3_reg: regulator@2 { - reg = <2>; - regulator-compatible = "dcdc3"; - }; - - ldo1_reg: regulator@3 { - reg = <3>; - regulator-compatible = "ldo1"; - }; - - ldo2_reg: regulator@4 { - reg = <4>; - regulator-compatible = "ldo2"; - }; - - ldo3_reg: regulator@5 { - reg = <5>; - regulator-compatible = "ldo3"; - }; - - ldo4_reg: regulator@6 { - reg = <6>; - regulator-compatible = "ldo4"; - }; - }; -}; diff --git a/sys/gnu/dts/arm/tps65910.dtsi b/sys/gnu/dts/arm/tps65910.dtsi deleted file mode 100644 index a941d1e6232..00000000000 --- a/sys/gnu/dts/arm/tps65910.dtsi +++ /dev/null @@ -1,88 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ - */ - -/* - * Integrated Power Management Chip - * http://www.ti.com/lit/ds/symlink/tps65910.pdf - */ - -&tps { - compatible = "ti,tps65910"; - - regulators { - #address-cells = <1>; - #size-cells = <0>; - - vrtc_reg: regulator@0 { - reg = <0>; - regulator-compatible = "vrtc"; - }; - - vio_reg: regulator@1 { - reg = <1>; - regulator-compatible = "vio"; - }; - - vdd1_reg: regulator@2 { - reg = <2>; - regulator-compatible = "vdd1"; - }; - - vdd2_reg: regulator@3 { - reg = <3>; - regulator-compatible = "vdd2"; - }; - - vdd3_reg: regulator@4 { - reg = <4>; - regulator-compatible = "vdd3"; - }; - - vdig1_reg: regulator@5 { - reg = <5>; - regulator-compatible = "vdig1"; - }; - - vdig2_reg: regulator@6 { - reg = <6>; - regulator-compatible = "vdig2"; - }; - - vpll_reg: regulator@7 { - reg = <7>; - regulator-compatible = "vpll"; - }; - - vdac_reg: regulator@8 { - reg = <8>; - regulator-compatible = "vdac"; - }; - - vaux1_reg: regulator@9 { - reg = <9>; - regulator-compatible = "vaux1"; - }; - - vaux2_reg: regulator@10 { - reg = <10>; - regulator-compatible = "vaux2"; - }; - - vaux33_reg: regulator@11 { - reg = <11>; - regulator-compatible = "vaux33"; - }; - - vmmc_reg: regulator@12 { - reg = <12>; - regulator-compatible = "vmmc"; - }; - - vbb_reg: regulator@13 { - reg = <13>; - regulator-compatible = "vbb"; - }; - }; -}; diff --git a/sys/gnu/dts/arm/twl4030.dtsi b/sys/gnu/dts/arm/twl4030.dtsi deleted file mode 100644 index 93e07c18781..00000000000 --- a/sys/gnu/dts/arm/twl4030.dtsi +++ /dev/null @@ -1,160 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ - */ - -/* - * Integrated Power Management Chip - */ -&twl { - compatible = "ti,twl4030"; - interrupt-controller; - #interrupt-cells = <1>; - - rtc { - compatible = "ti,twl4030-rtc"; - interrupts = <11>; - }; - - charger: bci { - compatible = "ti,twl4030-bci"; - interrupts = <9>, <2>; - bci3v1-supply = <&vusb3v1>; - io-channels = <&twl_madc 11>; - io-channel-names = "vac"; - }; - - watchdog { - compatible = "ti,twl4030-wdt"; - }; - - vaux1: regulator-vaux1 { - compatible = "ti,twl4030-vaux1"; - }; - - vaux2: regulator-vaux2 { - compatible = "ti,twl4030-vaux2"; - }; - - vaux3: regulator-vaux3 { - compatible = "ti,twl4030-vaux3"; - }; - - vaux4: regulator-vaux4 { - compatible = "ti,twl4030-vaux4"; - }; - - vcc: regulator-vdd1 { - compatible = "ti,twl4030-vdd1"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1450000>; - }; - - vdac: regulator-vdac { - compatible = "ti,twl4030-vdac"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vio: regulator-vio { - compatible = "ti,twl4030-vio"; - }; - - vintana1: regulator-vintana1 { - compatible = "ti,twl4030-vintana1"; - }; - - vintana2: regulator-vintana2 { - compatible = "ti,twl4030-vintana2"; - }; - - vintdig: regulator-vintdig { - compatible = "ti,twl4030-vintdig"; - }; - - vmmc1: regulator-vmmc1 { - compatible = "ti,twl4030-vmmc1"; - regulator-min-microvolt = <1850000>; - regulator-max-microvolt = <3150000>; - }; - - vmmc2: regulator-vmmc2 { - compatible = "ti,twl4030-vmmc2"; - regulator-min-microvolt = <1850000>; - regulator-max-microvolt = <3150000>; - }; - - vusb1v5: regulator-vusb1v5 { - compatible = "ti,twl4030-vusb1v5"; - }; - - vusb1v8: regulator-vusb1v8 { - compatible = "ti,twl4030-vusb1v8"; - }; - - vusb3v1: regulator-vusb3v1 { - compatible = "ti,twl4030-vusb3v1"; - }; - - vpll1: regulator-vpll1 { - compatible = "ti,twl4030-vpll1"; - }; - - vpll2: regulator-vpll2 { - compatible = "ti,twl4030-vpll2"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vsim: regulator-vsim { - compatible = "ti,twl4030-vsim"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3000000>; - }; - - twl_gpio: gpio { - compatible = "ti,twl4030-gpio"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <1>; - }; - - usb2_phy: twl4030-usb { - compatible = "ti,twl4030-usb"; - interrupts = <10>, <4>; - usb1v5-supply = <&vusb1v5>; - usb1v8-supply = <&vusb1v8>; - usb3v1-supply = <&vusb3v1>; - usb_mode = <1>; - #phy-cells = <0>; - }; - - twl_pwm: pwm { - compatible = "ti,twl4030-pwm"; - #pwm-cells = <2>; - }; - - twl_pwmled: pwmled { - compatible = "ti,twl4030-pwmled"; - #pwm-cells = <2>; - }; - - twl_pwrbutton: pwrbutton { - compatible = "ti,twl4030-pwrbutton"; - interrupts = <8>; - }; - - twl_keypad: keypad { - compatible = "ti,twl4030-keypad"; - interrupts = <1>; - keypad,num-rows = <8>; - keypad,num-columns = <8>; - }; - - twl_madc: madc { - compatible = "ti,twl4030-madc"; - interrupts = <3>; - #io-channel-cells = <1>; - }; -}; diff --git a/sys/gnu/dts/arm/twl4030_omap3.dtsi b/sys/gnu/dts/arm/twl4030_omap3.dtsi deleted file mode 100644 index 683419d5c0e..00000000000 --- a/sys/gnu/dts/arm/twl4030_omap3.dtsi +++ /dev/null @@ -1,39 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2013 Linaro, Ltd. - */ - -&twl { - pinctrl-names = "default"; - pinctrl-0 = <&twl4030_pins &twl4030_vpins>; -}; - -&omap3_pmx_core { - /* - * On most OMAP3 platforms, the twl4030 IRQ line is connected - * to the SYS_NIRQ line on OMAP. Therefore, configure the - * defaults for the SYS_NIRQ pin here. - */ - twl4030_pins: pinmux_twl4030_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21e0, PIN_INPUT_PULLUP | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* sys_nirq.sys_nirq */ - >; - }; -}; - -/* - * If your board is not using the I2C4 pins with twl4030, then don't include - * this file. For proper idle mode signaling with sys_clkreq and sys_off_mode - * pins we need to configure I2C4, or else use the legacy sys_nvmode1 and - * sys_nvmode2 signaling. - */ -&omap3_pmx_wkup { - twl4030_vpins: pinmux_twl4030_vpins { - pinctrl-single,pins = < - OMAP3_WKUP_IOPAD(0x2a00, PIN_INPUT | MUX_MODE0) /* i2c4_scl.i2c4_scl */ - OMAP3_WKUP_IOPAD(0x2a02, PIN_INPUT | MUX_MODE0) /* i2c4_sda.i2c4_sda */ - OMAP3_WKUP_IOPAD(0x2a06, PIN_OUTPUT | MUX_MODE0) /* sys_clkreq.sys_clkreq */ - OMAP3_WKUP_IOPAD(0x2a18, PIN_OUTPUT | MUX_MODE0) /* sys_off_mode.sys_off_mode */ - >; - }; -}; diff --git a/sys/gnu/dts/arm/twl6030.dtsi b/sys/gnu/dts/arm/twl6030.dtsi deleted file mode 100644 index 9d588cfaa5c..00000000000 --- a/sys/gnu/dts/arm/twl6030.dtsi +++ /dev/null @@ -1,105 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ - */ - -/* - * Integrated Power Management Chip - * http://www.ti.com/lit/ds/symlink/twl6030.pdf - */ -&twl { - compatible = "ti,twl6030"; - interrupt-controller; - #interrupt-cells = <1>; - - rtc { - compatible = "ti,twl4030-rtc"; - interrupts = <11>; - }; - - vaux1: regulator-vaux1 { - compatible = "ti,twl6030-vaux1"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - }; - - vaux2: regulator-vaux2 { - compatible = "ti,twl6030-vaux2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <2800000>; - }; - - vaux3: regulator-vaux3 { - compatible = "ti,twl6030-vaux3"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - }; - - vmmc: regulator-vmmc { - compatible = "ti,twl6030-vmmc"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3000000>; - }; - - vpp: regulator-vpp { - compatible = "ti,twl6030-vpp"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2500000>; - }; - - vusim: regulator-vusim { - compatible = "ti,twl6030-vusim"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <2900000>; - }; - - vdac: regulator-vdac { - compatible = "ti,twl6030-vdac"; - }; - - vana: regulator-vana { - compatible = "ti,twl6030-vana"; - }; - - vcxio: regulator-vcxio { - compatible = "ti,twl6030-vcxio"; - regulator-always-on; - }; - - vusb: regulator-vusb { - compatible = "ti,twl6030-vusb"; - }; - - v1v8: regulator-v1v8 { - compatible = "ti,twl6030-v1v8"; - regulator-always-on; - }; - - v2v1: regulator-v2v1 { - compatible = "ti,twl6030-v2v1"; - regulator-always-on; - }; - - twl_usb_comparator: usb-comparator { - compatible = "ti,twl6030-usb"; - interrupts = <4>, <10>; - }; - - twl_pwm: pwm { - /* provides two PWMs (id 0, 1 for PWM1 and PWM2) */ - compatible = "ti,twl6030-pwm"; - #pwm-cells = <2>; - }; - - twl_pwmled: pwmled { - /* provides one PWM (id 0 for Charging indicator LED) */ - compatible = "ti,twl6030-pwmled"; - #pwm-cells = <2>; - }; - - gpadc { - compatible = "ti,twl6030-gpadc"; - interrupts = <3>; - #io-channel-cells = <1>; - }; -}; diff --git a/sys/gnu/dts/arm/twl6030_omap4.dtsi b/sys/gnu/dts/arm/twl6030_omap4.dtsi deleted file mode 100644 index fc498d0bde8..00000000000 --- a/sys/gnu/dts/arm/twl6030_omap4.dtsi +++ /dev/null @@ -1,35 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ - */ - -&twl { - /* - * On most OMAP4 platforms, the twl6030 IRQ line is connected - * to the SYS_NIRQ1 line on OMAP and the twl6030 MSECURE line is - * connected to the fref_clk0_out.sys_drm_msecure line. - * Therefore, configure the defaults for the SYS_NIRQ1 and - * fref_clk0_out.sys_drm_msecure pins here. - */ - pinctrl-names = "default"; - pinctrl-0 = < - &twl6030_pins - &twl6030_wkup_pins - >; -}; - -&omap4_pmx_wkup { - twl6030_wkup_pins: pinmux_twl6030_wkup_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x054, PIN_OUTPUT | MUX_MODE2) /* fref_clk0_out.sys_drm_msecure */ - >; - }; -}; - -&omap4_pmx_core { - twl6030_pins: pinmux_twl6030_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x19e, WAKEUP_EN | PIN_INPUT_PULLUP | MUX_MODE0) /* sys_nirq1.sys_nirq1 */ - >; - }; -}; diff --git a/sys/gnu/dts/arm/uniphier-common32.dtsi b/sys/gnu/dts/arm/uniphier-common32.dtsi deleted file mode 100644 index 61a09559820..00000000000 --- a/sys/gnu/dts/arm/uniphier-common32.dtsi +++ /dev/null @@ -1,144 +0,0 @@ -/* - * Device Tree Source commonly used by UniPhier ARM SoCs - * - * Copyright (C) 2015 Masahiro Yamada - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/include/ "skeleton.dtsi" - -/ { - clocks { - refclk: ref { - #clock-cells = <0>; - compatible = "fixed-clock"; - }; - }; - - soc: soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - interrupt-parent = <&intc>; - - serial0: serial@54006800 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006800 0x40>; - interrupts = <0 33 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0>; - clocks = <&uart_clk>; - }; - - serial1: serial@54006900 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006900 0x40>; - interrupts = <0 35 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - clocks = <&uart_clk>; - }; - - serial2: serial@54006a00 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006a00 0x40>; - interrupts = <0 37 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - clocks = <&uart_clk>; - }; - - serial3: serial@54006b00 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006b00 0x40>; - interrupts = <0 177 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - clocks = <&uart_clk>; - }; - - system_bus: system-bus@58c00000 { - compatible = "socionext,uniphier-system-bus"; - status = "disabled"; - reg = <0x58c00000 0x400>; - #address-cells = <2>; - #size-cells = <1>; - }; - - smpctrl@59800000 { - compatible = "socionext,uniphier-smpctrl"; - reg = <0x59801000 0x400>; - }; - - timer@60000200 { - compatible = "arm,cortex-a9-global-timer"; - reg = <0x60000200 0x20>; - interrupts = <1 11 0x104>; - clocks = <&arm_timer_clk>; - }; - - timer@60000600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0x60000600 0x20>; - interrupts = <1 13 0x104>; - clocks = <&arm_timer_clk>; - }; - - intc: interrupt-controller@60001000 { - compatible = "arm,cortex-a9-gic"; - reg = <0x60001000 0x1000>, - <0x60000100 0x100>; - #interrupt-cells = <3>; - interrupt-controller; - }; - - pinctrl: pinctrl@5f801000 { - /* specify compatible in each SoC DTSI */ - reg = <0x5f801000 0xe00>; - }; - }; -}; - -/include/ "uniphier-pinctrl.dtsi" diff --git a/sys/gnu/dts/arm/uniphier-ld4-ref.dts b/sys/gnu/dts/arm/uniphier-ld4-ref.dts deleted file mode 100644 index f2d060f403c..00000000000 --- a/sys/gnu/dts/arm/uniphier-ld4-ref.dts +++ /dev/null @@ -1,84 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -// -// Device Tree Source for UniPhier LD4 Reference Board -// -// Copyright (C) 2015-2016 Socionext Inc. -// Author: Masahiro Yamada - -/dts-v1/; -#include "uniphier-ld4.dtsi" -#include "uniphier-ref-daughter.dtsi" -#include "uniphier-support-card.dtsi" - -/ { - model = "UniPhier LD4 Reference Board"; - compatible = "socionext,uniphier-ld4-ref", "socionext,uniphier-ld4"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - aliases { - serial0 = &serial0; - serial1 = &serial1; - serial2 = &serial2; - serial3 = &serial3; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000>; - }; -}; - -ðsc { - interrupts = <1 8>; -}; - -&serial0 { - status = "okay"; -}; - -&serial2 { - status = "okay"; -}; - -&serial3 { - status = "okay"; -}; - -&gpio { - xirq1 { - gpio-hog; - gpios = ; - input; - }; -}; - -&i2c0 { - status = "okay"; -}; - -&sd { - status = "okay"; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; - -&nand { - status = "okay"; - - nand@0 { - reg = <0>; - }; -}; diff --git a/sys/gnu/dts/arm/uniphier-ld4.dtsi b/sys/gnu/dts/arm/uniphier-ld4.dtsi deleted file mode 100644 index 64ec46c72a4..00000000000 --- a/sys/gnu/dts/arm/uniphier-ld4.dtsi +++ /dev/null @@ -1,419 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -// -// Device Tree Source for UniPhier LD4 SoC -// -// Copyright (C) 2015-2016 Socionext Inc. -// Author: Masahiro Yamada - -#include - -/ { - compatible = "socionext,uniphier-ld4"; - #address-cells = <1>; - #size-cells = <1>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - enable-method = "psci"; - next-level-cache = <&l2>; - }; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - clocks { - refclk: ref { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24576000>; - }; - - arm_timer_clk: arm-timer { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <50000000>; - }; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - interrupt-parent = <&intc>; - - l2: l2-cache@500c0000 { - compatible = "socionext,uniphier-system-cache"; - reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, - <0x506c0000 0x400>; - interrupts = <0 174 4>, <0 175 4>; - cache-unified; - cache-size = <(512 * 1024)>; - cache-sets = <256>; - cache-line-size = <128>; - cache-level = <2>; - }; - - spi: spi@54006000 { - compatible = "socionext,uniphier-scssi"; - status = "disabled"; - reg = <0x54006000 0x100>; - interrupts = <0 39 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi0>; - clocks = <&peri_clk 11>; - resets = <&peri_rst 11>; - }; - - serial0: serial@54006800 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006800 0x40>; - interrupts = <0 33 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0>; - clocks = <&peri_clk 0>; - resets = <&peri_rst 0>; - }; - - serial1: serial@54006900 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006900 0x40>; - interrupts = <0 35 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - clocks = <&peri_clk 1>; - resets = <&peri_rst 1>; - }; - - serial2: serial@54006a00 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006a00 0x40>; - interrupts = <0 37 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - clocks = <&peri_clk 2>; - resets = <&peri_rst 2>; - }; - - serial3: serial@54006b00 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006b00 0x40>; - interrupts = <0 29 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - clocks = <&peri_clk 3>; - resets = <&peri_rst 3>; - }; - - gpio: gpio@55000000 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000000 0x200>; - interrupt-parent = <&aidet>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl 0 0 0>; - gpio-ranges-group-names = "gpio_range"; - ngpios = <136>; - socionext,interrupt-ranges = <0 48 13>, <14 62 2>; - }; - - i2c0: i2c@58400000 { - compatible = "socionext,uniphier-i2c"; - status = "disabled"; - reg = <0x58400000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 41 1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - clocks = <&peri_clk 4>; - resets = <&peri_rst 4>; - clock-frequency = <100000>; - }; - - i2c1: i2c@58480000 { - compatible = "socionext,uniphier-i2c"; - status = "disabled"; - reg = <0x58480000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 42 1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - clocks = <&peri_clk 5>; - resets = <&peri_rst 5>; - clock-frequency = <100000>; - }; - - /* chip-internal connection for DMD */ - i2c2: i2c@58500000 { - compatible = "socionext,uniphier-i2c"; - reg = <0x58500000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 43 1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - clocks = <&peri_clk 6>; - resets = <&peri_rst 6>; - clock-frequency = <400000>; - }; - - i2c3: i2c@58580000 { - compatible = "socionext,uniphier-i2c"; - status = "disabled"; - reg = <0x58580000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 44 1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - clocks = <&peri_clk 7>; - resets = <&peri_rst 7>; - clock-frequency = <100000>; - }; - - system_bus: system-bus@58c00000 { - compatible = "socionext,uniphier-system-bus"; - status = "disabled"; - reg = <0x58c00000 0x400>; - #address-cells = <2>; - #size-cells = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_system_bus>; - }; - - smpctrl@59801000 { - compatible = "socionext,uniphier-smpctrl"; - reg = <0x59801000 0x400>; - }; - - mioctrl@59810000 { - compatible = "socionext,uniphier-ld4-mioctrl", - "simple-mfd", "syscon"; - reg = <0x59810000 0x800>; - - mio_clk: clock { - compatible = "socionext,uniphier-ld4-mio-clock"; - #clock-cells = <1>; - }; - - mio_rst: reset { - compatible = "socionext,uniphier-ld4-mio-reset"; - #reset-cells = <1>; - }; - }; - - perictrl@59820000 { - compatible = "socionext,uniphier-ld4-perictrl", - "simple-mfd", "syscon"; - reg = <0x59820000 0x200>; - - peri_clk: clock { - compatible = "socionext,uniphier-ld4-peri-clock"; - #clock-cells = <1>; - }; - - peri_rst: reset { - compatible = "socionext,uniphier-ld4-peri-reset"; - #reset-cells = <1>; - }; - }; - - dmac: dma-controller@5a000000 { - compatible = "socionext,uniphier-mio-dmac"; - reg = <0x5a000000 0x1000>; - interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>, - <0 71 4>, <0 72 4>, <0 73 4>; - clocks = <&mio_clk 7>; - resets = <&mio_rst 7>; - #dma-cells = <1>; - }; - - sd: sdhc@5a400000 { - compatible = "socionext,uniphier-sd-v2.91"; - status = "disabled"; - reg = <0x5a400000 0x200>; - interrupts = <0 76 4>; - pinctrl-names = "default", "uhs"; - pinctrl-0 = <&pinctrl_sd>; - pinctrl-1 = <&pinctrl_sd_uhs>; - clocks = <&mio_clk 0>; - reset-names = "host", "bridge"; - resets = <&mio_rst 0>, <&mio_rst 3>; - dma-names = "rx-tx"; - dmas = <&dmac 4>; - bus-width = <4>; - cap-sd-highspeed; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - }; - - emmc: sdhc@5a500000 { - compatible = "socionext,uniphier-sd-v2.91"; - status = "disabled"; - reg = <0x5a500000 0x200>; - interrupts = <0 78 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_emmc>; - clocks = <&mio_clk 1>; - reset-names = "host", "bridge", "hw"; - resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>; - dma-names = "rx-tx"; - dmas = <&dmac 6>; - bus-width = <8>; - cap-mmc-highspeed; - cap-mmc-hw-reset; - non-removable; - }; - - usb0: usb@5a800100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a800100 0x100>; - interrupts = <0 80 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb0>; - clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>, - <&mio_clk 12>; - resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>, - <&mio_rst 12>; - has-transaction-translator; - }; - - usb1: usb@5a810100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a810100 0x100>; - interrupts = <0 81 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb1>; - clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>, - <&mio_clk 13>; - resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>, - <&mio_rst 13>; - has-transaction-translator; - }; - - usb2: usb@5a820100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a820100 0x100>; - interrupts = <0 82 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb2>; - clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 10>, - <&mio_clk 14>; - resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>, - <&mio_rst 14>; - has-transaction-translator; - }; - - soc-glue@5f800000 { - compatible = "socionext,uniphier-ld4-soc-glue", - "simple-mfd", "syscon"; - reg = <0x5f800000 0x2000>; - - pinctrl: pinctrl { - compatible = "socionext,uniphier-ld4-pinctrl"; - }; - }; - - soc-glue@5f900000 { - compatible = "socionext,uniphier-ld4-soc-glue-debug", - "simple-mfd"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x5f900000 0x2000>; - - efuse@100 { - compatible = "socionext,uniphier-efuse"; - reg = <0x100 0x28>; - }; - - efuse@130 { - compatible = "socionext,uniphier-efuse"; - reg = <0x130 0x8>; - }; - }; - - timer@60000200 { - compatible = "arm,cortex-a9-global-timer"; - reg = <0x60000200 0x20>; - interrupts = <1 11 0x104>; - clocks = <&arm_timer_clk>; - }; - - timer@60000600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0x60000600 0x20>; - interrupts = <1 13 0x104>; - clocks = <&arm_timer_clk>; - }; - - intc: interrupt-controller@60001000 { - compatible = "arm,cortex-a9-gic"; - reg = <0x60001000 0x1000>, - <0x60000100 0x100>; - #interrupt-cells = <3>; - interrupt-controller; - }; - - aidet: aidet@61830000 { - compatible = "socionext,uniphier-ld4-aidet"; - reg = <0x61830000 0x200>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - sysctrl@61840000 { - compatible = "socionext,uniphier-ld4-sysctrl", - "simple-mfd", "syscon"; - reg = <0x61840000 0x10000>; - - sys_clk: clock { - compatible = "socionext,uniphier-ld4-clock"; - #clock-cells = <1>; - }; - - sys_rst: reset { - compatible = "socionext,uniphier-ld4-reset"; - #reset-cells = <1>; - }; - }; - - nand: nand@68000000 { - compatible = "socionext,uniphier-denali-nand-v5a"; - status = "disabled"; - reg-names = "nand_data", "denali_reg"; - reg = <0x68000000 0x20>, <0x68100000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 65 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nand>; - clock-names = "nand", "nand_x", "ecc"; - clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>; - reset-names = "nand", "reg"; - resets = <&sys_rst 2>, <&sys_rst 2>; - }; - }; -}; - -#include "uniphier-pinctrl.dtsi" diff --git a/sys/gnu/dts/arm/uniphier-ld6b-ref.dts b/sys/gnu/dts/arm/uniphier-ld6b-ref.dts deleted file mode 100644 index 60994b6e8b9..00000000000 --- a/sys/gnu/dts/arm/uniphier-ld6b-ref.dts +++ /dev/null @@ -1,97 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -// -// Device Tree Source for UniPhier LD6b Reference Board -// -// Copyright (C) 2015-2016 Socionext Inc. -// Author: Masahiro Yamada - -/dts-v1/; -#include "uniphier-ld6b.dtsi" -#include "uniphier-ref-daughter.dtsi" -#include "uniphier-support-card.dtsi" - -/ { - model = "UniPhier LD6b Reference Board"; - compatible = "socionext,uniphier-ld6b-ref", "socionext,uniphier-ld6b"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - aliases { - serial0 = &serial0; - serial1 = &serial1; - serial2 = &serial2; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - i2c6 = &i2c6; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x80000000>; - }; -}; - -ðsc { - interrupts = <4 8>; -}; - -&serial0 { - status = "okay"; -}; - -&serial1 { - status = "okay"; -}; - -&serial2 { - status = "okay"; -}; - -&gpio { - xirq4 { - gpio-hog; - gpios = ; - input; - }; -}; - -&i2c0 { - status = "okay"; -}; - -&sd { - status = "okay"; -}; - -ð { - status = "okay"; - phy-handle = <ðphy>; -}; - -&mdio { - ethphy: ethphy@0 { - reg = <0>; - }; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; - -&nand { - status = "okay"; - - nand@0 { - reg = <0>; - }; -}; diff --git a/sys/gnu/dts/arm/uniphier-ld6b.dtsi b/sys/gnu/dts/arm/uniphier-ld6b.dtsi deleted file mode 100644 index 4d07a94c6b3..00000000000 --- a/sys/gnu/dts/arm/uniphier-ld6b.dtsi +++ /dev/null @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -// -// Device Tree Source for UniPhier LD6b SoC -// -// Copyright (C) 2015-2016 Socionext Inc. -// Author: Masahiro Yamada - -/* - * LD6b consists of two silicon dies: D-chip and A-chip. - * The D-chip (digital chip) is the same as the PXs2 die. - * Reuse the PXs2 device tree with some properties overridden. - */ -#include "uniphier-pxs2.dtsi" - -/ { - compatible = "socionext,uniphier-ld6b"; -}; - -/* UART3 unavailable: the pads are not wired to the package balls */ -&serial3 { - status = "disabled"; -}; - -/* - * LD6b and PXs2 have completely different packages, - * which makes the pinctrl driver unshareable. - */ -&pinctrl { - compatible = "socionext,uniphier-ld6b-pinctrl"; -}; diff --git a/sys/gnu/dts/arm/uniphier-ph1-ld4-ref.dts b/sys/gnu/dts/arm/uniphier-ph1-ld4-ref.dts deleted file mode 100644 index ec94b7a661f..00000000000 --- a/sys/gnu/dts/arm/uniphier-ph1-ld4-ref.dts +++ /dev/null @@ -1,101 +0,0 @@ -/* - * Device Tree Source for UniPhier PH1-LD4 Reference Board - * - * Copyright (C) 2015 Masahiro Yamada - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -/include/ "uniphier-ph1-ld4.dtsi" -/include/ "uniphier-ref-daughter.dtsi" -/include/ "uniphier-support-card.dtsi" - -/ { - model = "UniPhier PH1-LD4 Reference Board"; - compatible = "socionext,ph1-ld4-ref", "socionext,ph1-ld4"; - - memory { - device_type = "memory"; - reg = <0x80000000 0x20000000>; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - aliases { - serial0 = &serial0; - serial1 = &serial1; - serial2 = &serial2; - serial3 = &serial3; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - }; -}; - -ðsc { - interrupts = <0 49 4>; -}; - -&serial0 { - status = "okay"; -}; - -&serial2 { - status = "okay"; -}; - -&serial3 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/uniphier-ph1-ld4.dtsi b/sys/gnu/dts/arm/uniphier-ph1-ld4.dtsi deleted file mode 100644 index dadd86070c9..00000000000 --- a/sys/gnu/dts/arm/uniphier-ph1-ld4.dtsi +++ /dev/null @@ -1,186 +0,0 @@ -/* - * Device Tree Source for UniPhier PH1-LD4 SoC - * - * Copyright (C) 2015 Masahiro Yamada - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/include/ "uniphier-common32.dtsi" - -/ { - compatible = "socionext,ph1-ld4"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - next-level-cache = <&l2>; - }; - }; - - clocks { - arm_timer_clk: arm_timer_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <50000000>; - }; - - uart_clk: uart_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <36864000>; - }; - - iobus_clk: iobus_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <100000000>; - }; - }; -}; - -&soc { - l2: l2-cache@500c0000 { - compatible = "socionext,uniphier-system-cache"; - reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>; - interrupts = <0 174 4>, <0 175 4>; - cache-unified; - cache-size = <(512 * 1024)>; - cache-sets = <256>; - cache-line-size = <128>; - cache-level = <2>; - }; - - i2c0: i2c@58400000 { - compatible = "socionext,uniphier-i2c"; - status = "disabled"; - reg = <0x58400000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 41 1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - clocks = <&iobus_clk>; - clock-frequency = <100000>; - }; - - i2c1: i2c@58480000 { - compatible = "socionext,uniphier-i2c"; - status = "disabled"; - reg = <0x58480000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 42 1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - clocks = <&iobus_clk>; - clock-frequency = <100000>; - }; - - /* chip-internal connection for DMD */ - i2c2: i2c@58500000 { - compatible = "socionext,uniphier-i2c"; - reg = <0x58500000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 43 1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - clocks = <&iobus_clk>; - clock-frequency = <400000>; - }; - - i2c3: i2c@58580000 { - compatible = "socionext,uniphier-i2c"; - status = "disabled"; - reg = <0x58580000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 44 1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - clocks = <&iobus_clk>; - clock-frequency = <100000>; - }; - - usb0: usb@5a800100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a800100 0x100>; - interrupts = <0 80 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb0>; - }; - - usb1: usb@5a810100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a810100 0x100>; - interrupts = <0 81 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb1>; - }; - - usb2: usb@5a820100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a820100 0x100>; - interrupts = <0 82 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb2>; - }; - -}; - -&refclk { - clock-frequency = <24576000>; -}; - -&serial3 { - interrupts = <0 29 4>; -}; - -&pinctrl { - compatible = "socionext,ph1-ld4-pinctrl", "syscon"; -}; diff --git a/sys/gnu/dts/arm/uniphier-ph1-ld6b-ref.dts b/sys/gnu/dts/arm/uniphier-ph1-ld6b-ref.dts deleted file mode 100644 index b8134c6e094..00000000000 --- a/sys/gnu/dts/arm/uniphier-ph1-ld6b-ref.dts +++ /dev/null @@ -1,95 +0,0 @@ -/* - * Device Tree Source for UniPhier PH1-LD6b Reference Board - * - * Copyright (C) 2015 Masahiro Yamada - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -/include/ "uniphier-ph1-ld6b.dtsi" -/include/ "uniphier-ref-daughter.dtsi" -/include/ "uniphier-support-card.dtsi" - -/ { - model = "UniPhier PH1-LD6b Reference Board"; - compatible = "socionext,ph1-ld6b-ref", "socionext,ph1-ld6b"; - - memory { - device_type = "memory"; - reg = <0x80000000 0x80000000>; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - aliases { - serial0 = &serial0; - serial1 = &serial1; - serial2 = &serial2; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - i2c6 = &i2c6; - }; -}; - -ðsc { - interrupts = <0 52 4>; -}; - -&serial0 { - status = "okay"; -}; - -&serial1 { - status = "okay"; -}; - -&serial2 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/uniphier-ph1-ld6b.dtsi b/sys/gnu/dts/arm/uniphier-ph1-ld6b.dtsi deleted file mode 100644 index 53211523402..00000000000 --- a/sys/gnu/dts/arm/uniphier-ph1-ld6b.dtsi +++ /dev/null @@ -1,67 +0,0 @@ -/* - * Device Tree Source for UniPhier PH1-LD6b SoC - * - * Copyright (C) 2015 Masahiro Yamada - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/* - * PH1-LD6b consists of two silicon dies: D-chip and A-chip. - * The D-chip (digital chip) is the same as the ProXstream2 die. - * Reuse the ProXstream2 device tree with some properties overridden. - */ -/include/ "uniphier-proxstream2.dtsi" - -/ { - compatible = "socionext,ph1-ld6b"; -}; - -/* UART3 unavailable: the pads are not wired to the package balls */ -&serial3 { - status = "disabled"; -}; - -/* - * PH1-LD6b and ProXstream2 have completely different packages, - * which makes the pinctrl driver unshareable. - */ -&pinctrl { - compatible = "socionext,ph1-ld6b-pinctrl", "syscon"; -}; diff --git a/sys/gnu/dts/arm/uniphier-ph1-pro4-ace.dts b/sys/gnu/dts/arm/uniphier-ph1-pro4-ace.dts deleted file mode 100644 index d34358632be..00000000000 --- a/sys/gnu/dts/arm/uniphier-ph1-pro4-ace.dts +++ /dev/null @@ -1,113 +0,0 @@ -/* - * Device Tree Source for UniPhier PH1-Pro4 Ace Board - * - * Copyright (C) 2016 Masahiro Yamada - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -/include/ "uniphier-ph1-pro4.dtsi" - -/ { - model = "UniPhier PH1-Pro4 Ace Board"; - compatible = "socionext,ph1-pro4-ace", "socionext,ph1-pro4"; - - memory { - device_type = "memory"; - reg = <0x80000000 0x40000000>; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - aliases { - serial0 = &serial0; - serial1 = &serial1; - serial2 = &serial2; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c5 = &i2c5; - i2c6 = &i2c6; - }; -}; - -&serial0 { - status = "okay"; -}; - -&serial1 { - status = "okay"; -}; - -&serial2 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - eeprom@54 { - compatible = "st,24c64"; - reg = <0x54>; - }; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c3 { - status = "okay"; -}; - -&usb2 { - status = "okay"; -}; - -&usb3 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/uniphier-ph1-pro4-ref.dts b/sys/gnu/dts/arm/uniphier-ph1-pro4-ref.dts deleted file mode 100644 index 95f631a3de3..00000000000 --- a/sys/gnu/dts/arm/uniphier-ph1-pro4-ref.dts +++ /dev/null @@ -1,103 +0,0 @@ -/* - * Device Tree Source for UniPhier PH1-Pro4 Reference Board - * - * Copyright (C) 2015 Masahiro Yamada - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -/include/ "uniphier-ph1-pro4.dtsi" -/include/ "uniphier-ref-daughter.dtsi" -/include/ "uniphier-support-card.dtsi" - -/ { - model = "UniPhier PH1-Pro4 Reference Board"; - compatible = "socionext,ph1-pro4-ref", "socionext,ph1-pro4"; - - memory { - device_type = "memory"; - reg = <0x80000000 0x40000000>; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - aliases { - serial0 = &serial0; - serial1 = &serial1; - serial2 = &serial2; - serial3 = &serial3; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c5 = &i2c5; - i2c6 = &i2c6; - }; -}; - -ðsc { - interrupts = <0 50 4>; -}; - -&serial0 { - status = "okay"; -}; - -&serial1 { - status = "okay"; -}; - -&serial2 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; -}; - -&usb2 { - status = "okay"; -}; - -&usb3 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/uniphier-ph1-pro4-sanji.dts b/sys/gnu/dts/arm/uniphier-ph1-pro4-sanji.dts deleted file mode 100644 index 7c3a1fcc9f3..00000000000 --- a/sys/gnu/dts/arm/uniphier-ph1-pro4-sanji.dts +++ /dev/null @@ -1,108 +0,0 @@ -/* - * Device Tree Source for UniPhier PH1-Pro4 Sanji Board - * - * Copyright (C) 2016 Masahiro Yamada - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -/include/ "uniphier-ph1-pro4.dtsi" - -/ { - model = "UniPhier PH1-Pro4 Sanji Board"; - compatible = "socionext,ph1-pro4-sanji", "socionext,ph1-pro4"; - - memory { - device_type = "memory"; - reg = <0x80000000 0x80000000>; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - aliases { - serial0 = &serial0; - serial1 = &serial1; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c5 = &i2c5; - i2c6 = &i2c6; - }; -}; - -&serial0 { - status = "okay"; -}; - -&serial1 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - eeprom@54 { - compatible = "st,24c64"; - reg = <0x54>; - }; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c3 { - status = "okay"; -}; - -&usb2 { - status = "okay"; -}; - -&usb3 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/uniphier-ph1-pro4.dtsi b/sys/gnu/dts/arm/uniphier-ph1-pro4.dtsi deleted file mode 100644 index 20f3f2ae7fa..00000000000 --- a/sys/gnu/dts/arm/uniphier-ph1-pro4.dtsi +++ /dev/null @@ -1,204 +0,0 @@ -/* - * Device Tree Source for UniPhier PH1-Pro4 SoC - * - * Copyright (C) 2015 Masahiro Yamada - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/include/ "uniphier-common32.dtsi" - -/ { - compatible = "socionext,ph1-pro4"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "socionext,uniphier-smp"; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - next-level-cache = <&l2>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <1>; - next-level-cache = <&l2>; - }; - }; - - clocks { - arm_timer_clk: arm_timer_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <50000000>; - }; - - uart_clk: uart_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <73728000>; - }; - - i2c_clk: i2c_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <50000000>; - }; - }; -}; - -&soc { - l2: l2-cache@500c0000 { - compatible = "socionext,uniphier-system-cache"; - reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>; - interrupts = <0 174 4>, <0 175 4>; - cache-unified; - cache-size = <(768 * 1024)>; - cache-sets = <256>; - cache-line-size = <128>; - cache-level = <2>; - }; - - i2c0: i2c@58780000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58780000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 41 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - clocks = <&i2c_clk>; - clock-frequency = <100000>; - }; - - i2c1: i2c@58781000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58781000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 42 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - clocks = <&i2c_clk>; - clock-frequency = <100000>; - }; - - i2c2: i2c@58782000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58782000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 43 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - clocks = <&i2c_clk>; - clock-frequency = <100000>; - }; - - i2c3: i2c@58783000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58783000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 44 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - clocks = <&i2c_clk>; - clock-frequency = <100000>; - }; - - /* i2c4 does not exist */ - - /* chip-internal connection for DMD */ - i2c5: i2c@58785000 { - compatible = "socionext,uniphier-fi2c"; - reg = <0x58785000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 25 4>; - clocks = <&i2c_clk>; - clock-frequency = <400000>; - }; - - /* chip-internal connection for HDMI */ - i2c6: i2c@58786000 { - compatible = "socionext,uniphier-fi2c"; - reg = <0x58786000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 26 4>; - clocks = <&i2c_clk>; - clock-frequency = <400000>; - }; - - usb2: usb@5a800100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a800100 0x100>; - interrupts = <0 80 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb2>; - }; - - usb3: usb@5a810100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a810100 0x100>; - interrupts = <0 81 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb3>; - }; -}; - -&refclk { - clock-frequency = <25000000>; -}; - -&pinctrl { - compatible = "socionext,ph1-pro4-pinctrl", "syscon"; -}; diff --git a/sys/gnu/dts/arm/uniphier-ph1-pro5.dtsi b/sys/gnu/dts/arm/uniphier-ph1-pro5.dtsi deleted file mode 100644 index 24f6f664b26..00000000000 --- a/sys/gnu/dts/arm/uniphier-ph1-pro5.dtsi +++ /dev/null @@ -1,198 +0,0 @@ -/* - * Device Tree Source for UniPhier PH1-Pro5 SoC - * - * Copyright (C) 2015 Masahiro Yamada - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/include/ "uniphier-common32.dtsi" - -/ { - compatible = "socionext,ph1-pro5"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "socionext,uniphier-smp"; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - next-level-cache = <&l2>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <1>; - next-level-cache = <&l2>; - }; - }; - - clocks { - arm_timer_clk: arm_timer_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <50000000>; - }; - - uart_clk: uart_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <73728000>; - }; - - i2c_clk: i2c_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <50000000>; - }; - }; -}; - -&soc { - l2: l2-cache@500c0000 { - compatible = "socionext,uniphier-system-cache"; - reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, <0x506c0000 0x400>; - interrupts = <0 190 4>, <0 191 4>; - cache-unified; - cache-size = <(2 * 1024 * 1024)>; - cache-sets = <512>; - cache-line-size = <128>; - cache-level = <2>; - next-level-cache = <&l3>; - }; - - l3: l3-cache@500c8000 { - compatible = "socionext,uniphier-system-cache"; - reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, <0x506c8000 0x400>; - interrupts = <0 174 4>, <0 175 4>; - cache-unified; - cache-size = <(2 * 1024 * 1024)>; - cache-sets = <512>; - cache-line-size = <256>; - cache-level = <3>; - }; - - i2c0: i2c@58780000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58780000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 41 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - clocks = <&i2c_clk>; - clock-frequency = <100000>; - }; - - i2c1: i2c@58781000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58781000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 42 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - clocks = <&i2c_clk>; - clock-frequency = <100000>; - }; - - i2c2: i2c@58782000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58782000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 43 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - clocks = <&i2c_clk>; - clock-frequency = <100000>; - }; - - i2c3: i2c@58783000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58783000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 44 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - clocks = <&i2c_clk>; - clock-frequency = <100000>; - }; - - /* i2c4 does not exist */ - - /* chip-internal connection for DMD */ - i2c5: i2c@58785000 { - compatible = "socionext,uniphier-fi2c"; - reg = <0x58785000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 25 4>; - clocks = <&i2c_clk>; - clock-frequency = <400000>; - }; - - /* chip-internal connection for HDMI */ - i2c6: i2c@58786000 { - compatible = "socionext,uniphier-fi2c"; - reg = <0x58786000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 26 4>; - clocks = <&i2c_clk>; - clock-frequency = <400000>; - }; -}; - -&refclk { - clock-frequency = <20000000>; -}; - -&pinctrl { - compatible = "socionext,ph1-pro5-pinctrl", "syscon"; -}; diff --git a/sys/gnu/dts/arm/uniphier-ph1-sld3-ref.dts b/sys/gnu/dts/arm/uniphier-ph1-sld3-ref.dts deleted file mode 100644 index acb420492b3..00000000000 --- a/sys/gnu/dts/arm/uniphier-ph1-sld3-ref.dts +++ /dev/null @@ -1,110 +0,0 @@ -/* - * Device Tree Source for UniPhier PH1-sLD3 Reference Board - * - * Copyright (C) 2015 Masahiro Yamada - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -/include/ "uniphier-ph1-sld3.dtsi" -/include/ "uniphier-ref-daughter.dtsi" -/include/ "uniphier-support-card.dtsi" - -/ { - model = "UniPhier PH1-sLD3 Reference Board"; - compatible = "socionext,ph1-sld3-ref", "socionext,ph1-sld3"; - - memory { - device_type = "memory"; - reg = <0x80000000 0x20000000 - 0xc0000000 0x20000000>; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - aliases { - serial0 = &serial0; - serial1 = &serial1; - serial2 = &serial2; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - }; -}; - -ðsc { - interrupts = <0 49 4>; -}; - -&serial0 { - status = "okay"; -}; - -&serial1 { - status = "okay"; -}; - -&serial2 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; - -&usb2 { - status = "okay"; -}; - -&usb3 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/uniphier-ph1-sld3.dtsi b/sys/gnu/dts/arm/uniphier-ph1-sld3.dtsi deleted file mode 100644 index 03292f44330..00000000000 --- a/sys/gnu/dts/arm/uniphier-ph1-sld3.dtsi +++ /dev/null @@ -1,260 +0,0 @@ -/* - * Device Tree Source for UniPhier PH1-sLD3 SoC - * - * Copyright (C) 2015 Masahiro Yamada - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/include/ "skeleton.dtsi" - -/ { - compatible = "socionext,ph1-sld3"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "socionext,uniphier-smp"; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - next-level-cache = <&l2>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <1>; - next-level-cache = <&l2>; - }; - }; - - clocks { - refclk: ref { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24576000>; - }; - - arm_timer_clk: arm_timer_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <50000000>; - }; - - uart_clk: uart_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <36864000>; - }; - - iobus_clk: iobus_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <100000000>; - }; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - interrupt-parent = <&intc>; - - timer@20000200 { - compatible = "arm,cortex-a9-global-timer"; - reg = <0x20000200 0x20>; - interrupts = <1 11 0x304>; - clocks = <&arm_timer_clk>; - }; - - timer@20000600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0x20000600 0x20>; - interrupts = <1 13 0x304>; - clocks = <&arm_timer_clk>; - }; - - intc: interrupt-controller@20001000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x20001000 0x1000>, - <0x20000100 0x100>; - }; - - l2: l2-cache@500c0000 { - compatible = "socionext,uniphier-system-cache"; - reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, - <0x506c0000 0x400>; - interrupts = <0 174 4>, <0 175 4>; - cache-unified; - cache-size = <(512 * 1024)>; - cache-sets = <256>; - cache-line-size = <128>; - cache-level = <2>; - }; - - serial0: serial@54006800 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006800 0x40>; - interrupts = <0 33 4>; - clocks = <&uart_clk>; - fifo-size = <64>; - }; - - serial1: serial@54006900 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006900 0x40>; - interrupts = <0 35 4>; - clocks = <&uart_clk>; - fifo-size = <64>; - }; - - serial2: serial@54006a00 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006a00 0x40>; - interrupts = <0 37 4>; - clocks = <&uart_clk>; - fifo-size = <64>; - }; - - i2c0: i2c@58400000 { - compatible = "socionext,uniphier-i2c"; - status = "disabled"; - reg = <0x58400000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 41 1>; - clocks = <&iobus_clk>; - clock-frequency = <100000>; - }; - - i2c1: i2c@58480000 { - compatible = "socionext,uniphier-i2c"; - status = "disabled"; - reg = <0x58480000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 42 1>; - clocks = <&iobus_clk>; - clock-frequency = <100000>; - }; - - i2c2: i2c@58500000 { - compatible = "socionext,uniphier-i2c"; - status = "disabled"; - reg = <0x58500000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 43 1>; - clocks = <&iobus_clk>; - clock-frequency = <100000>; - }; - - i2c3: i2c@58580000 { - compatible = "socionext,uniphier-i2c"; - status = "disabled"; - reg = <0x58580000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 44 1>; - clocks = <&iobus_clk>; - clock-frequency = <100000>; - }; - - /* chip-internal connection for DMD */ - i2c4: i2c@58600000 { - compatible = "socionext,uniphier-i2c"; - reg = <0x58600000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 45 1>; - clocks = <&iobus_clk>; - clock-frequency = <400000>; - }; - - system_bus: system-bus@58c00000 { - compatible = "socionext,uniphier-system-bus"; - status = "disabled"; - reg = <0x58c00000 0x400>; - #address-cells = <2>; - #size-cells = <1>; - }; - - smpctrl@59800000 { - compatible = "socionext,uniphier-smpctrl"; - reg = <0x59801000 0x400>; - }; - - usb0: usb@5a800100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a800100 0x100>; - interrupts = <0 80 4>; - }; - - usb1: usb@5a810100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a810100 0x100>; - interrupts = <0 81 4>; - }; - - usb2: usb@5a820100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a820100 0x100>; - interrupts = <0 82 4>; - }; - - usb3: usb@5a830100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a830100 0x100>; - interrupts = <0 83 4>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/uniphier-ph1-sld8-ref.dts b/sys/gnu/dts/arm/uniphier-ph1-sld8-ref.dts deleted file mode 100644 index d594f40e7f7..00000000000 --- a/sys/gnu/dts/arm/uniphier-ph1-sld8-ref.dts +++ /dev/null @@ -1,105 +0,0 @@ -/* - * Device Tree Source for UniPhier PH1-sLD8 Reference Board - * - * Copyright (C) 2015 Masahiro Yamada - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -/include/ "uniphier-ph1-sld8.dtsi" -/include/ "uniphier-ref-daughter.dtsi" -/include/ "uniphier-support-card.dtsi" - -/ { - model = "UniPhier PH1-sLD8 Reference Board"; - compatible = "socionext,ph1-sld8-ref", "socionext,ph1-sld8"; - - memory { - device_type = "memory"; - reg = <0x80000000 0x20000000>; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - aliases { - serial0 = &serial0; - serial1 = &serial1; - serial2 = &serial2; - serial3 = &serial3; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - }; -}; - -ðsc { - interrupts = <0 48 4>; -}; - -&serial0 { - status = "okay"; -}; - -&serial2 { - status = "okay"; -}; - -&serial3 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; - -&usb2 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/uniphier-ph1-sld8.dtsi b/sys/gnu/dts/arm/uniphier-ph1-sld8.dtsi deleted file mode 100644 index 6bfd29a0557..00000000000 --- a/sys/gnu/dts/arm/uniphier-ph1-sld8.dtsi +++ /dev/null @@ -1,185 +0,0 @@ -/* - * Device Tree Source for UniPhier PH1-sLD8 SoC - * - * Copyright (C) 2015 Masahiro Yamada - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/include/ "uniphier-common32.dtsi" - -/ { - compatible = "socionext,ph1-sld8"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - next-level-cache = <&l2>; - }; - }; - - clocks { - arm_timer_clk: arm_timer_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <50000000>; - }; - - uart_clk: uart_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <80000000>; - }; - - iobus_clk: iobus_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <100000000>; - }; - }; -}; - -&soc { - l2: l2-cache@500c0000 { - compatible = "socionext,uniphier-system-cache"; - reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>; - interrupts = <0 174 4>, <0 175 4>; - cache-unified; - cache-size = <(256 * 1024)>; - cache-sets = <256>; - cache-line-size = <128>; - cache-level = <2>; - }; - - i2c0: i2c@58400000 { - compatible = "socionext,uniphier-i2c"; - status = "disabled"; - reg = <0x58400000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 41 1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - clocks = <&iobus_clk>; - clock-frequency = <100000>; - }; - - i2c1: i2c@58480000 { - compatible = "socionext,uniphier-i2c"; - status = "disabled"; - reg = <0x58480000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 42 1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - clocks = <&iobus_clk>; - clock-frequency = <100000>; - }; - - /* chip-internal connection for DMD */ - i2c2: i2c@58500000 { - compatible = "socionext,uniphier-i2c"; - reg = <0x58500000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 43 1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - clocks = <&iobus_clk>; - clock-frequency = <400000>; - }; - - i2c3: i2c@58580000 { - compatible = "socionext,uniphier-i2c"; - status = "disabled"; - reg = <0x58580000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 44 1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - clocks = <&iobus_clk>; - clock-frequency = <100000>; - }; - - usb0: usb@5a800100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a800100 0x100>; - interrupts = <0 80 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb0>; - }; - - usb1: usb@5a810100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a810100 0x100>; - interrupts = <0 81 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb1>; - }; - - usb2: usb@5a820100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a820100 0x100>; - interrupts = <0 82 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb2>; - }; -}; - -&refclk { - clock-frequency = <25000000>; -}; - -&serial3 { - interrupts = <0 29 4>; -}; - -&pinctrl { - compatible = "socionext,ph1-sld8-pinctrl", "syscon"; -}; diff --git a/sys/gnu/dts/arm/uniphier-pinctrl.dtsi b/sys/gnu/dts/arm/uniphier-pinctrl.dtsi deleted file mode 100644 index bfdfb764b25..00000000000 --- a/sys/gnu/dts/arm/uniphier-pinctrl.dtsi +++ /dev/null @@ -1,208 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -// -// Device Tree Source for UniPhier SoCs default pinctrl settings -// -// Copyright (C) 2015-2017 Socionext Inc. -// Author: Masahiro Yamada - -&pinctrl { - pinctrl_aout: aout { - groups = "aout"; - function = "aout"; - }; - - pinctrl_ain1: ain1 { - groups = "ain1"; - function = "ain1"; - }; - - pinctrl_ain2: ain2 { - groups = "ain2"; - function = "ain2"; - }; - - pinctrl_ainiec1: ainiec1 { - groups = "ainiec1"; - function = "ainiec1"; - }; - - pinctrl_aout1: aout1 { - groups = "aout1"; - function = "aout1"; - }; - - pinctrl_aout2: aout2 { - groups = "aout2"; - function = "aout2"; - }; - - pinctrl_aout3: aout3 { - groups = "aout3"; - function = "aout3"; - }; - - pinctrl_aoutiec1: aoutiec1 { - groups = "aoutiec1"; - function = "aoutiec1"; - }; - - pinctrl_aoutiec2: aoutiec2 { - groups = "aoutiec2"; - function = "aoutiec2"; - }; - - pinctrl_emmc: emmc { - groups = "emmc", "emmc_dat8"; - function = "emmc"; - }; - - pinctrl_ether_mii: ether-mii { - groups = "ether_mii"; - function = "ether_mii"; - }; - - pinctrl_ether_rgmii: ether-rgmii { - groups = "ether_rgmii"; - function = "ether_rgmii"; - }; - - pinctrl_ether_rmii: ether-rmii { - groups = "ether_rmii"; - function = "ether_rmii"; - }; - - pinctrl_ether1_rgmii: ether1-rgmii { - groups = "ether1_rgmii"; - function = "ether1_rgmii"; - }; - - pinctrl_ether1_rmii: ether1-rmii { - groups = "ether1_rmii"; - function = "ether1_rmii"; - }; - - pinctrl_i2c0: i2c0 { - groups = "i2c0"; - function = "i2c0"; - }; - - pinctrl_i2c1: i2c1 { - groups = "i2c1"; - function = "i2c1"; - }; - - pinctrl_i2c2: i2c2 { - groups = "i2c2"; - function = "i2c2"; - }; - - pinctrl_i2c3: i2c3 { - groups = "i2c3"; - function = "i2c3"; - }; - - pinctrl_i2c4: i2c4 { - groups = "i2c4"; - function = "i2c4"; - }; - - pinctrl_i2c5: i2c5 { - groups = "i2c5"; - function = "i2c5"; - }; - - pinctrl_i2c6: i2c6 { - groups = "i2c6"; - function = "i2c6"; - }; - - pinctrl_nand: nand { - groups = "nand"; - function = "nand"; - }; - - pinctrl_nand2cs: nand2cs { - groups = "nand", "nand_cs1"; - function = "nand"; - }; - - pinctrl_sd: sd { - groups = "sd"; - function = "sd"; - }; - - pinctrl_sd_uhs: sd-uhs { - groups = "sd"; - function = "sd"; - }; - - pinctrl_sd1: sd1 { - groups = "sd1"; - function = "sd1"; - }; - - pinctrl_spi0: spi0 { - groups = "spi0"; - function = "spi0"; - }; - - pinctrl_spi1: spi1 { - groups = "spi1"; - function = "spi1"; - }; - - pinctrl_spi2: spi2 { - groups = "spi2"; - function = "spi2"; - }; - - pinctrl_spi3: spi3 { - groups = "spi3"; - function = "spi3"; - }; - - pinctrl_system_bus: system-bus { - groups = "system_bus", "system_bus_cs1"; - function = "system_bus"; - }; - - pinctrl_uart0: uart0 { - groups = "uart0"; - function = "uart0"; - }; - - pinctrl_uart1: uart1 { - groups = "uart1"; - function = "uart1"; - }; - - pinctrl_uart2: uart2 { - groups = "uart2"; - function = "uart2"; - }; - - pinctrl_uart3: uart3 { - groups = "uart3"; - function = "uart3"; - }; - - pinctrl_usb0: usb0 { - groups = "usb0"; - function = "usb0"; - }; - - pinctrl_usb1: usb1 { - groups = "usb1"; - function = "usb1"; - }; - - pinctrl_usb2: usb2 { - groups = "usb2"; - function = "usb2"; - }; - - pinctrl_usb3: usb3 { - groups = "usb3"; - function = "usb3"; - }; -}; diff --git a/sys/gnu/dts/arm/uniphier-pro4-ace.dts b/sys/gnu/dts/arm/uniphier-pro4-ace.dts deleted file mode 100644 index 92cc48dd86d..00000000000 --- a/sys/gnu/dts/arm/uniphier-pro4-ace.dts +++ /dev/null @@ -1,100 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -// -// Device Tree Source for UniPhier Pro4 Ace Board -// -// Copyright (C) 2016 Socionext Inc. -// Author: Masahiro Yamada - -/dts-v1/; -#include "uniphier-pro4.dtsi" - -/ { - model = "UniPhier Pro4 Ace Board"; - compatible = "socionext,uniphier-pro4-ace", "socionext,uniphier-pro4"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - aliases { - serial0 = &serial0; - serial1 = &serial1; - serial2 = &serial2; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c5 = &i2c5; - i2c6 = &i2c6; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x40000000>; - }; -}; - -&serial0 { - status = "okay"; -}; - -&serial1 { - status = "okay"; -}; - -&serial2 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - eeprom@54 { - compatible = "st,24c64", "atmel,24c64"; - reg = <0x54>; - pagesize = <32>; - }; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c3 { - status = "okay"; -}; - -&sd { - status = "okay"; -}; - -&usb2 { - status = "okay"; -}; - -&usb3 { - status = "okay"; -}; - -ð { - status = "okay"; - phy-handle = <ðphy>; -}; - -&mdio { - ethphy: ethphy@1 { - reg = <1>; - }; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/uniphier-pro4-ref.dts b/sys/gnu/dts/arm/uniphier-pro4-ref.dts deleted file mode 100644 index 854f2eba3e7..00000000000 --- a/sys/gnu/dts/arm/uniphier-pro4-ref.dts +++ /dev/null @@ -1,105 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -// -// Device Tree Source for UniPhier Pro4 Reference Board -// -// Copyright (C) 2015-2016 Socionext Inc. -// Author: Masahiro Yamada - -/dts-v1/; -#include "uniphier-pro4.dtsi" -#include "uniphier-ref-daughter.dtsi" -#include "uniphier-support-card.dtsi" - -/ { - model = "UniPhier Pro4 Reference Board"; - compatible = "socionext,uniphier-pro4-ref", "socionext,uniphier-pro4"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - aliases { - serial0 = &serial0; - serial1 = &serial1; - serial2 = &serial2; - serial3 = &serial3; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c5 = &i2c5; - i2c6 = &i2c6; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x40000000>; - }; -}; - -ðsc { - interrupts = <2 8>; -}; - -&serial0 { - status = "okay"; -}; - -&serial1 { - status = "okay"; -}; - -&serial2 { - status = "okay"; -}; - -&gpio { - xirq2 { - gpio-hog; - gpios = ; - input; - }; -}; - -&i2c0 { - status = "okay"; -}; - -&sd { - status = "okay"; -}; - -&usb2 { - status = "okay"; -}; - -&usb3 { - status = "okay"; -}; - -ð { - status = "okay"; - phy-handle = <ðphy>; -}; - -&mdio { - ethphy: ethphy@0 { - reg = <0>; - }; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; - -&nand { - status = "okay"; - - nand@0 { - reg = <0>; - }; -}; diff --git a/sys/gnu/dts/arm/uniphier-pro4-sanji.dts b/sys/gnu/dts/arm/uniphier-pro4-sanji.dts deleted file mode 100644 index dda1a2f214a..00000000000 --- a/sys/gnu/dts/arm/uniphier-pro4-sanji.dts +++ /dev/null @@ -1,95 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -// -// Device Tree Source for UniPhier Pro4 Sanji Board -// -// Copyright (C) 2016 Socionext Inc. -// Author: Masahiro Yamada - -/dts-v1/; -#include "uniphier-pro4.dtsi" - -/ { - model = "UniPhier Pro4 Sanji Board"; - compatible = "socionext,uniphier-pro4-sanji", "socionext,uniphier-pro4"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - aliases { - serial0 = &serial0; - serial1 = &serial1; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c5 = &i2c5; - i2c6 = &i2c6; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x80000000>; - }; -}; - -&serial0 { - status = "okay"; -}; - -&serial1 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - eeprom@54 { - compatible = "st,24c64", "atmel,24c64"; - reg = <0x54>; - pagesize = <32>; - }; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c3 { - status = "okay"; -}; - -&usb2 { - status = "okay"; -}; - -&usb3 { - status = "okay"; -}; - -&emmc { - status = "okay"; -}; - -ð { - status = "okay"; - phy-handle = <ðphy>; -}; - -&mdio { - ethphy: ethphy@1 { - reg = <1>; - }; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/uniphier-pro4.dtsi b/sys/gnu/dts/arm/uniphier-pro4.dtsi deleted file mode 100644 index 2ec04d7972e..00000000000 --- a/sys/gnu/dts/arm/uniphier-pro4.dtsi +++ /dev/null @@ -1,609 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -// -// Device Tree Source for UniPhier Pro4 SoC -// -// Copyright (C) 2015-2016 Socionext Inc. -// Author: Masahiro Yamada - -#include - -/ { - compatible = "socionext,uniphier-pro4"; - #address-cells = <1>; - #size-cells = <1>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - enable-method = "psci"; - next-level-cache = <&l2>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <1>; - enable-method = "psci"; - next-level-cache = <&l2>; - }; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - clocks { - refclk: ref { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - - arm_timer_clk: arm-timer { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <50000000>; - }; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - interrupt-parent = <&intc>; - - l2: l2-cache@500c0000 { - compatible = "socionext,uniphier-system-cache"; - reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, - <0x506c0000 0x400>; - interrupts = <0 174 4>, <0 175 4>; - cache-unified; - cache-size = <(768 * 1024)>; - cache-sets = <256>; - cache-line-size = <128>; - cache-level = <2>; - }; - - spi0: spi@54006000 { - compatible = "socionext,uniphier-scssi"; - status = "disabled"; - reg = <0x54006000 0x100>; - interrupts = <0 39 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi0>; - clocks = <&peri_clk 11>; - resets = <&peri_rst 11>; - }; - - serial0: serial@54006800 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006800 0x40>; - interrupts = <0 33 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0>; - clocks = <&peri_clk 0>; - resets = <&peri_rst 0>; - }; - - serial1: serial@54006900 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006900 0x40>; - interrupts = <0 35 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - clocks = <&peri_clk 1>; - resets = <&peri_rst 1>; - }; - - serial2: serial@54006a00 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006a00 0x40>; - interrupts = <0 37 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - clocks = <&peri_clk 2>; - resets = <&peri_rst 2>; - }; - - serial3: serial@54006b00 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006b00 0x40>; - interrupts = <0 177 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - clocks = <&peri_clk 3>; - resets = <&peri_rst 3>; - }; - - gpio: gpio@55000000 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000000 0x200>; - interrupt-parent = <&aidet>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl 0 0 0>; - gpio-ranges-group-names = "gpio_range"; - ngpios = <248>; - socionext,interrupt-ranges = <0 48 16>, <16 154 5>; - }; - - i2c0: i2c@58780000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58780000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 41 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - clocks = <&peri_clk 4>; - resets = <&peri_rst 4>; - clock-frequency = <100000>; - }; - - i2c1: i2c@58781000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58781000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 42 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - clocks = <&peri_clk 5>; - resets = <&peri_rst 5>; - clock-frequency = <100000>; - }; - - i2c2: i2c@58782000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58782000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 43 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - clocks = <&peri_clk 6>; - resets = <&peri_rst 6>; - clock-frequency = <100000>; - }; - - i2c3: i2c@58783000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58783000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 44 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - clocks = <&peri_clk 7>; - resets = <&peri_rst 7>; - clock-frequency = <100000>; - }; - - /* i2c4 does not exist */ - - /* chip-internal connection for DMD */ - i2c5: i2c@58785000 { - compatible = "socionext,uniphier-fi2c"; - reg = <0x58785000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 25 4>; - clocks = <&peri_clk 9>; - resets = <&peri_rst 9>; - clock-frequency = <400000>; - }; - - /* chip-internal connection for HDMI */ - i2c6: i2c@58786000 { - compatible = "socionext,uniphier-fi2c"; - reg = <0x58786000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 26 4>; - clocks = <&peri_clk 10>; - resets = <&peri_rst 10>; - clock-frequency = <400000>; - }; - - system_bus: system-bus@58c00000 { - compatible = "socionext,uniphier-system-bus"; - status = "disabled"; - reg = <0x58c00000 0x400>; - #address-cells = <2>; - #size-cells = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_system_bus>; - }; - - smpctrl@59801000 { - compatible = "socionext,uniphier-smpctrl"; - reg = <0x59801000 0x400>; - }; - - mioctrl@59810000 { - compatible = "socionext,uniphier-pro4-mioctrl", - "simple-mfd", "syscon"; - reg = <0x59810000 0x800>; - - mio_clk: clock { - compatible = "socionext,uniphier-pro4-mio-clock"; - #clock-cells = <1>; - }; - - mio_rst: reset { - compatible = "socionext,uniphier-pro4-mio-reset"; - #reset-cells = <1>; - }; - }; - - perictrl@59820000 { - compatible = "socionext,uniphier-pro4-perictrl", - "simple-mfd", "syscon"; - reg = <0x59820000 0x200>; - - peri_clk: clock { - compatible = "socionext,uniphier-pro4-peri-clock"; - #clock-cells = <1>; - }; - - peri_rst: reset { - compatible = "socionext,uniphier-pro4-peri-reset"; - #reset-cells = <1>; - }; - }; - - dmac: dma-controller@5a000000 { - compatible = "socionext,uniphier-mio-dmac"; - reg = <0x5a000000 0x1000>; - interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>, - <0 71 4>, <0 72 4>, <0 73 4>, <0 74 4>; - clocks = <&mio_clk 7>; - resets = <&mio_rst 7>; - #dma-cells = <1>; - }; - - sd: sdhc@5a400000 { - compatible = "socionext,uniphier-sd-v2.91"; - status = "disabled"; - reg = <0x5a400000 0x200>; - interrupts = <0 76 4>; - pinctrl-names = "default", "uhs"; - pinctrl-0 = <&pinctrl_sd>; - pinctrl-1 = <&pinctrl_sd_uhs>; - clocks = <&mio_clk 0>; - reset-names = "host", "bridge"; - resets = <&mio_rst 0>, <&mio_rst 3>; - dma-names = "rx-tx"; - dmas = <&dmac 4>; - bus-width = <4>; - cap-sd-highspeed; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - }; - - emmc: sdhc@5a500000 { - compatible = "socionext,uniphier-sd-v2.91"; - status = "disabled"; - reg = <0x5a500000 0x200>; - interrupts = <0 78 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_emmc>; - clocks = <&mio_clk 1>; - reset-names = "host", "bridge", "hw"; - resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>; - dma-names = "rx-tx"; - dmas = <&dmac 5>; - bus-width = <8>; - cap-mmc-highspeed; - cap-mmc-hw-reset; - non-removable; - }; - - sd1: sdhc@5a600000 { - compatible = "socionext,uniphier-sd-v2.91"; - status = "disabled"; - reg = <0x5a600000 0x200>; - interrupts = <0 85 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sd1>; - clocks = <&mio_clk 2>; - reset-names = "host", "bridge"; - resets = <&mio_rst 2>, <&mio_rst 5>; - dma-names = "rx-tx"; - dmas = <&dmac 6>; - bus-width = <4>; - cap-sd-highspeed; - }; - - usb2: usb@5a800100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a800100 0x100>; - interrupts = <0 80 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb2>; - clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>, - <&mio_clk 12>; - resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>, - <&mio_rst 12>; - phy-names = "usb"; - phys = <&usb_phy0>; - has-transaction-translator; - }; - - usb3: usb@5a810100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a810100 0x100>; - interrupts = <0 81 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb3>; - clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>, - <&mio_clk 13>; - resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>, - <&mio_rst 13>; - phy-names = "usb"; - phys = <&usb_phy1>; - has-transaction-translator; - }; - - soc_glue: soc-glue@5f800000 { - compatible = "socionext,uniphier-pro4-soc-glue", - "simple-mfd", "syscon"; - reg = <0x5f800000 0x2000>; - - pinctrl: pinctrl { - compatible = "socionext,uniphier-pro4-pinctrl"; - }; - - usb-phy { - compatible = "socionext,uniphier-pro4-usb2-phy"; - #address-cells = <1>; - #size-cells = <0>; - - usb_phy0: phy@0 { - reg = <0>; - #phy-cells = <0>; - }; - - usb_phy1: phy@1 { - reg = <1>; - #phy-cells = <0>; - }; - - usb_phy2: phy@2 { - reg = <2>; - #phy-cells = <0>; - vbus-supply = <&usb0_vbus>; - }; - - usb_phy3: phy@3 { - reg = <3>; - #phy-cells = <0>; - vbus-supply = <&usb1_vbus>; - }; - }; - }; - - soc-glue@5f900000 { - compatible = "socionext,uniphier-pro4-soc-glue-debug", - "simple-mfd"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x5f900000 0x2000>; - - efuse@100 { - compatible = "socionext,uniphier-efuse"; - reg = <0x100 0x28>; - }; - - efuse@130 { - compatible = "socionext,uniphier-efuse"; - reg = <0x130 0x8>; - }; - - efuse@200 { - compatible = "socionext,uniphier-efuse"; - reg = <0x200 0x14>; - }; - }; - - aidet: aidet@5fc20000 { - compatible = "socionext,uniphier-pro4-aidet"; - reg = <0x5fc20000 0x200>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - timer@60000200 { - compatible = "arm,cortex-a9-global-timer"; - reg = <0x60000200 0x20>; - interrupts = <1 11 0x304>; - clocks = <&arm_timer_clk>; - }; - - timer@60000600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0x60000600 0x20>; - interrupts = <1 13 0x304>; - clocks = <&arm_timer_clk>; - }; - - intc: interrupt-controller@60001000 { - compatible = "arm,cortex-a9-gic"; - reg = <0x60001000 0x1000>, - <0x60000100 0x100>; - #interrupt-cells = <3>; - interrupt-controller; - }; - - sysctrl@61840000 { - compatible = "socionext,uniphier-pro4-sysctrl", - "simple-mfd", "syscon"; - reg = <0x61840000 0x10000>; - - sys_clk: clock { - compatible = "socionext,uniphier-pro4-clock"; - #clock-cells = <1>; - }; - - sys_rst: reset { - compatible = "socionext,uniphier-pro4-reset"; - #reset-cells = <1>; - }; - }; - - eth: ethernet@65000000 { - compatible = "socionext,uniphier-pro4-ave4"; - status = "disabled"; - reg = <0x65000000 0x8500>; - interrupts = <0 66 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ether_rgmii>; - clock-names = "gio", "ether", "ether-gb", "ether-phy"; - clocks = <&sys_clk 12>, <&sys_clk 6>, <&sys_clk 7>, - <&sys_clk 10>; - reset-names = "gio", "ether"; - resets = <&sys_rst 12>, <&sys_rst 6>; - phy-mode = "rgmii"; - local-mac-address = [00 00 00 00 00 00]; - socionext,syscon-phy-mode = <&soc_glue 0>; - - mdio: mdio { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - usb0: usb@65a00000 { - compatible = "socionext,uniphier-dwc3", "snps,dwc3"; - status = "disabled"; - reg = <0x65a00000 0xcd00>; - interrupt-names = "host", "peripheral"; - interrupts = <0 134 4>, <0 135 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb0>; - clock-names = "ref", "bus_early", "suspend"; - clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>; - resets = <&usb0_rst 4>; - phys = <&usb_phy2>, <&usb0_ssphy>; - dr_mode = "host"; - }; - - usb-glue@65b00000 { - compatible = "socionext,uniphier-pro4-dwc3-glue", - "simple-mfd"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x65b00000 0x100>; - - usb0_vbus: regulator@0 { - compatible = "socionext,uniphier-pro4-usb3-regulator"; - reg = <0 0x10>; - clock-names = "gio", "link"; - clocks = <&sys_clk 12>, <&sys_clk 14>; - reset-names = "gio", "link"; - resets = <&sys_rst 12>, <&sys_rst 14>; - }; - - usb0_ssphy: ss-phy@10 { - compatible = "socionext,uniphier-pro4-usb3-ssphy"; - reg = <0x10 0x10>; - #phy-cells = <0>; - clock-names = "gio", "link"; - clocks = <&sys_clk 12>, <&sys_clk 14>; - reset-names = "gio", "link"; - resets = <&sys_rst 12>, <&sys_rst 14>; - vbus-supply = <&usb0_vbus>; - }; - - usb0_rst: reset@40 { - compatible = "socionext,uniphier-pro4-usb3-reset"; - reg = <0x40 0x4>; - #reset-cells = <1>; - clock-names = "gio", "link"; - clocks = <&sys_clk 12>, <&sys_clk 14>; - reset-names = "gio", "link"; - resets = <&sys_rst 12>, <&sys_rst 14>; - }; - }; - - usb1: usb@65c00000 { - compatible = "socionext,uniphier-dwc3", "snps,dwc3"; - status = "disabled"; - reg = <0x65c00000 0xcd00>; - interrupt-names = "host", "peripheral"; - interrupts = <0 137 4>, <0 138 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb1>; - clock-names = "ref", "bus_early", "suspend"; - clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>; - resets = <&usb1_rst 4>; - phys = <&usb_phy3>; - dr_mode = "host"; - }; - - usb-glue@65d00000 { - compatible = "socionext,uniphier-pro4-dwc3-glue", - "simple-mfd"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x65d00000 0x100>; - - usb1_vbus: regulator@0 { - compatible = "socionext,uniphier-pro4-usb3-regulator"; - reg = <0 0x10>; - clock-names = "gio", "link"; - clocks = <&sys_clk 12>, <&sys_clk 15>; - reset-names = "gio", "link"; - resets = <&sys_rst 12>, <&sys_rst 15>; - }; - - usb1_rst: reset@40 { - compatible = "socionext,uniphier-pro4-usb3-reset"; - reg = <0x40 0x4>; - #reset-cells = <1>; - clock-names = "gio", "link"; - clocks = <&sys_clk 12>, <&sys_clk 15>; - reset-names = "gio", "link"; - resets = <&sys_rst 12>, <&sys_rst 15>; - }; - }; - - nand: nand@68000000 { - compatible = "socionext,uniphier-denali-nand-v5a"; - status = "disabled"; - reg-names = "nand_data", "denali_reg"; - reg = <0x68000000 0x20>, <0x68100000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 65 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nand>; - clock-names = "nand", "nand_x", "ecc"; - clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>; - reset-names = "nand", "reg"; - resets = <&sys_rst 2>, <&sys_rst 2>; - }; - }; -}; - -#include "uniphier-pinctrl.dtsi" diff --git a/sys/gnu/dts/arm/uniphier-pro5.dtsi b/sys/gnu/dts/arm/uniphier-pro5.dtsi deleted file mode 100644 index ea3961f920a..00000000000 --- a/sys/gnu/dts/arm/uniphier-pro5.dtsi +++ /dev/null @@ -1,508 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -// -// Device Tree Source for UniPhier Pro5 SoC -// -// Copyright (C) 2015-2016 Socionext Inc. -// Author: Masahiro Yamada - -/ { - compatible = "socionext,uniphier-pro5"; - #address-cells = <1>; - #size-cells = <1>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - clocks = <&sys_clk 32>; - enable-method = "psci"; - next-level-cache = <&l2>; - operating-points-v2 = <&cpu_opp>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <1>; - clocks = <&sys_clk 32>; - enable-method = "psci"; - next-level-cache = <&l2>; - operating-points-v2 = <&cpu_opp>; - }; - }; - - cpu_opp: opp-table { - compatible = "operating-points-v2"; - opp-shared; - - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - clock-latency-ns = <300>; - }; - opp-116667000 { - opp-hz = /bits/ 64 <116667000>; - clock-latency-ns = <300>; - }; - opp-150000000 { - opp-hz = /bits/ 64 <150000000>; - clock-latency-ns = <300>; - }; - opp-175000000 { - opp-hz = /bits/ 64 <175000000>; - clock-latency-ns = <300>; - }; - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - clock-latency-ns = <300>; - }; - opp-233334000 { - opp-hz = /bits/ 64 <233334000>; - clock-latency-ns = <300>; - }; - opp-300000000 { - opp-hz = /bits/ 64 <300000000>; - clock-latency-ns = <300>; - }; - opp-350000000 { - opp-hz = /bits/ 64 <350000000>; - clock-latency-ns = <300>; - }; - opp-400000000 { - opp-hz = /bits/ 64 <400000000>; - clock-latency-ns = <300>; - }; - opp-466667000 { - opp-hz = /bits/ 64 <466667000>; - clock-latency-ns = <300>; - }; - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - clock-latency-ns = <300>; - }; - opp-700000000 { - opp-hz = /bits/ 64 <700000000>; - clock-latency-ns = <300>; - }; - opp-800000000 { - opp-hz = /bits/ 64 <800000000>; - clock-latency-ns = <300>; - }; - opp-933334000 { - opp-hz = /bits/ 64 <933334000>; - clock-latency-ns = <300>; - }; - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - clock-latency-ns = <300>; - }; - opp-1400000000 { - opp-hz = /bits/ 64 <1400000000>; - clock-latency-ns = <300>; - }; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - clocks { - refclk: ref { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <20000000>; - }; - - arm_timer_clk: arm-timer { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <50000000>; - }; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - interrupt-parent = <&intc>; - - l2: l2-cache@500c0000 { - compatible = "socionext,uniphier-system-cache"; - reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, - <0x506c0000 0x400>; - interrupts = <0 190 4>, <0 191 4>; - cache-unified; - cache-size = <(2 * 1024 * 1024)>; - cache-sets = <512>; - cache-line-size = <128>; - cache-level = <2>; - next-level-cache = <&l3>; - }; - - l3: l3-cache@500c8000 { - compatible = "socionext,uniphier-system-cache"; - reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, - <0x506c8000 0x400>; - interrupts = <0 174 4>, <0 175 4>; - cache-unified; - cache-size = <(2 * 1024 * 1024)>; - cache-sets = <512>; - cache-line-size = <256>; - cache-level = <3>; - }; - - spi0: spi@54006000 { - compatible = "socionext,uniphier-scssi"; - status = "disabled"; - reg = <0x54006000 0x100>; - interrupts = <0 39 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi0>; - clocks = <&peri_clk 11>; - resets = <&peri_rst 11>; - }; - - spi1: spi@54006100 { - compatible = "socionext,uniphier-scssi"; - status = "disabled"; - reg = <0x54006100 0x100>; - interrupts = <0 216 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1>; - clocks = <&peri_clk 11>; - resets = <&peri_rst 11>; - }; - - serial0: serial@54006800 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006800 0x40>; - interrupts = <0 33 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0>; - clocks = <&peri_clk 0>; - resets = <&peri_rst 0>; - }; - - serial1: serial@54006900 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006900 0x40>; - interrupts = <0 35 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - clocks = <&peri_clk 1>; - resets = <&peri_rst 1>; - }; - - serial2: serial@54006a00 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006a00 0x40>; - interrupts = <0 37 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - clocks = <&peri_clk 2>; - resets = <&peri_rst 2>; - }; - - serial3: serial@54006b00 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006b00 0x40>; - interrupts = <0 177 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - clocks = <&peri_clk 3>; - resets = <&peri_rst 3>; - }; - - gpio: gpio@55000000 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000000 0x200>; - interrupt-parent = <&aidet>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl 0 0 0>; - gpio-ranges-group-names = "gpio_range"; - ngpios = <248>; - socionext,interrupt-ranges = <0 48 16>, <16 154 5>; - }; - - i2c0: i2c@58780000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58780000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 41 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - clocks = <&peri_clk 4>; - resets = <&peri_rst 4>; - clock-frequency = <100000>; - }; - - i2c1: i2c@58781000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58781000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 42 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - clocks = <&peri_clk 5>; - resets = <&peri_rst 5>; - clock-frequency = <100000>; - }; - - i2c2: i2c@58782000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58782000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 43 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - clocks = <&peri_clk 6>; - resets = <&peri_rst 6>; - clock-frequency = <100000>; - }; - - i2c3: i2c@58783000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58783000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 44 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - clocks = <&peri_clk 7>; - resets = <&peri_rst 7>; - clock-frequency = <100000>; - }; - - /* i2c4 does not exist */ - - /* chip-internal connection for DMD */ - i2c5: i2c@58785000 { - compatible = "socionext,uniphier-fi2c"; - reg = <0x58785000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 25 4>; - clocks = <&peri_clk 9>; - resets = <&peri_rst 9>; - clock-frequency = <400000>; - }; - - /* chip-internal connection for HDMI */ - i2c6: i2c@58786000 { - compatible = "socionext,uniphier-fi2c"; - reg = <0x58786000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 26 4>; - clocks = <&peri_clk 10>; - resets = <&peri_rst 10>; - clock-frequency = <400000>; - }; - - system_bus: system-bus@58c00000 { - compatible = "socionext,uniphier-system-bus"; - status = "disabled"; - reg = <0x58c00000 0x400>; - #address-cells = <2>; - #size-cells = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_system_bus>; - }; - - smpctrl@59801000 { - compatible = "socionext,uniphier-smpctrl"; - reg = <0x59801000 0x400>; - }; - - sdctrl@59810000 { - compatible = "socionext,uniphier-pro5-sdctrl", - "simple-mfd", "syscon"; - reg = <0x59810000 0x400>; - - sd_clk: clock { - compatible = "socionext,uniphier-pro5-sd-clock"; - #clock-cells = <1>; - }; - - sd_rst: reset { - compatible = "socionext,uniphier-pro5-sd-reset"; - #reset-cells = <1>; - }; - }; - - perictrl@59820000 { - compatible = "socionext,uniphier-pro5-perictrl", - "simple-mfd", "syscon"; - reg = <0x59820000 0x200>; - - peri_clk: clock { - compatible = "socionext,uniphier-pro5-peri-clock"; - #clock-cells = <1>; - }; - - peri_rst: reset { - compatible = "socionext,uniphier-pro5-peri-reset"; - #reset-cells = <1>; - }; - }; - - soc-glue@5f800000 { - compatible = "socionext,uniphier-pro5-soc-glue", - "simple-mfd", "syscon"; - reg = <0x5f800000 0x2000>; - - pinctrl: pinctrl { - compatible = "socionext,uniphier-pro5-pinctrl"; - }; - }; - - soc-glue@5f900000 { - compatible = "socionext,uniphier-pro5-soc-glue-debug", - "simple-mfd"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x5f900000 0x2000>; - - efuse@100 { - compatible = "socionext,uniphier-efuse"; - reg = <0x100 0x28>; - }; - - efuse@130 { - compatible = "socionext,uniphier-efuse"; - reg = <0x130 0x8>; - }; - - efuse@200 { - compatible = "socionext,uniphier-efuse"; - reg = <0x200 0x28>; - }; - - efuse@300 { - compatible = "socionext,uniphier-efuse"; - reg = <0x300 0x14>; - }; - - efuse@400 { - compatible = "socionext,uniphier-efuse"; - reg = <0x400 0x8>; - }; - }; - - aidet: aidet@5fc20000 { - compatible = "socionext,uniphier-pro5-aidet"; - reg = <0x5fc20000 0x200>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - timer@60000200 { - compatible = "arm,cortex-a9-global-timer"; - reg = <0x60000200 0x20>; - interrupts = <1 11 0x304>; - clocks = <&arm_timer_clk>; - }; - - timer@60000600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0x60000600 0x20>; - interrupts = <1 13 0x304>; - clocks = <&arm_timer_clk>; - }; - - intc: interrupt-controller@60001000 { - compatible = "arm,cortex-a9-gic"; - reg = <0x60001000 0x1000>, - <0x60000100 0x100>; - #interrupt-cells = <3>; - interrupt-controller; - }; - - sysctrl@61840000 { - compatible = "socionext,uniphier-pro5-sysctrl", - "simple-mfd", "syscon"; - reg = <0x61840000 0x10000>; - - sys_clk: clock { - compatible = "socionext,uniphier-pro5-clock"; - #clock-cells = <1>; - }; - - sys_rst: reset { - compatible = "socionext,uniphier-pro5-reset"; - #reset-cells = <1>; - }; - }; - - nand: nand@68000000 { - compatible = "socionext,uniphier-denali-nand-v5b"; - status = "disabled"; - reg-names = "nand_data", "denali_reg"; - reg = <0x68000000 0x20>, <0x68100000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 65 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nand>; - clock-names = "nand", "nand_x", "ecc"; - clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>; - reset-names = "nand", "reg"; - resets = <&sys_rst 2>, <&sys_rst 2>; - }; - - emmc: sdhc@68400000 { - compatible = "socionext,uniphier-sd-v3.1"; - status = "disabled"; - reg = <0x68400000 0x800>; - interrupts = <0 78 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_emmc>; - clocks = <&sd_clk 1>; - reset-names = "host", "hw"; - resets = <&sd_rst 1>, <&sd_rst 6>; - bus-width = <8>; - cap-mmc-highspeed; - cap-mmc-hw-reset; - non-removable; - }; - - sd: sdhc@68800000 { - compatible = "socionext,uniphier-sd-v3.1"; - status = "disabled"; - reg = <0x68800000 0x800>; - interrupts = <0 76 4>; - pinctrl-names = "default", "uhs"; - pinctrl-0 = <&pinctrl_sd>; - pinctrl-1 = <&pinctrl_sd_uhs>; - clocks = <&sd_clk 0>; - reset-names = "host"; - resets = <&sd_rst 0>; - bus-width = <4>; - cap-sd-highspeed; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - }; - }; -}; - -#include "uniphier-pinctrl.dtsi" diff --git a/sys/gnu/dts/arm/uniphier-proxstream2-gentil.dts b/sys/gnu/dts/arm/uniphier-proxstream2-gentil.dts deleted file mode 100644 index bf2619e4d48..00000000000 --- a/sys/gnu/dts/arm/uniphier-proxstream2-gentil.dts +++ /dev/null @@ -1,88 +0,0 @@ -/* - * Device Tree Source for UniPhier ProXstream2 Gentil Board - * - * Copyright (C) 2015 Masahiro Yamada - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -/include/ "uniphier-proxstream2.dtsi" - -/ { - model = "UniPhier ProXstream2 Gentil Board"; - compatible = "socionext,proxstream2-gentil", "socionext,proxstream2"; - - memory { - device_type = "memory"; - reg = <0x80000000 0x80000000>; - }; - - chosen { - stdout-path = "serial2:115200n8"; - }; - - aliases { - serial0 = &serial0; - serial1 = &serial1; - serial2 = &serial2; - i2c0 = &i2c0; - i2c2 = &i2c2; - i2c4 = &i2c4; - i2c5 = &i2c5; - i2c6 = &i2c6; - }; -}; - -&serial2 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - eeprom@54 { - compatible = "st,24c64"; - reg = <0x54>; - }; -}; - -&i2c2 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/uniphier-proxstream2-vodka.dts b/sys/gnu/dts/arm/uniphier-proxstream2-vodka.dts deleted file mode 100644 index 498acac3d95..00000000000 --- a/sys/gnu/dts/arm/uniphier-proxstream2-vodka.dts +++ /dev/null @@ -1,78 +0,0 @@ -/* - * Device Tree Source for UniPhier ProXstream2 Vodka Board - * - * Copyright (C) 2015 Masahiro Yamada - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -/include/ "uniphier-proxstream2.dtsi" - -/ { - model = "UniPhier ProXstream2 Vodka Board"; - compatible = "socionext,proxstream2-vodka", "socionext,proxstream2"; - - memory { - device_type = "memory"; - reg = <0x80000000 0x80000000>; - }; - - chosen { - stdout-path = "serial2:115200n8"; - }; - - aliases { - serial0 = &serial0; - serial1 = &serial1; - serial2 = &serial2; - i2c0 = &i2c0; - i2c4 = &i2c4; - i2c5 = &i2c5; - i2c6 = &i2c6; - }; -}; - -&serial2 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/uniphier-proxstream2.dtsi b/sys/gnu/dts/arm/uniphier-proxstream2.dtsi deleted file mode 100644 index 4ac484c6ce4..00000000000 --- a/sys/gnu/dts/arm/uniphier-proxstream2.dtsi +++ /dev/null @@ -1,209 +0,0 @@ -/* - * Device Tree Source for UniPhier ProXstream2 SoC - * - * Copyright (C) 2015 Masahiro Yamada - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/include/ "uniphier-common32.dtsi" - -/ { - compatible = "socionext,proxstream2"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "socionext,uniphier-smp"; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - next-level-cache = <&l2>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <1>; - next-level-cache = <&l2>; - }; - - cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <2>; - next-level-cache = <&l2>; - }; - - cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <3>; - next-level-cache = <&l2>; - }; - }; - - clocks { - arm_timer_clk: arm_timer_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <50000000>; - }; - - uart_clk: uart_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <88900000>; - }; - - i2c_clk: i2c_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <50000000>; - }; - }; -}; - -&soc { - l2: l2-cache@500c0000 { - compatible = "socionext,uniphier-system-cache"; - reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>; - interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>; - cache-unified; - cache-size = <(1280 * 1024)>; - cache-sets = <512>; - cache-line-size = <128>; - cache-level = <2>; - }; - - i2c0: i2c@58780000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58780000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 41 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - clocks = <&i2c_clk>; - clock-frequency = <100000>; - }; - - i2c1: i2c@58781000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58781000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 42 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - clocks = <&i2c_clk>; - clock-frequency = <100000>; - }; - - i2c2: i2c@58782000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58782000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - interrupts = <0 43 4>; - clocks = <&i2c_clk>; - clock-frequency = <100000>; - }; - - i2c3: i2c@58783000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58783000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 44 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - clocks = <&i2c_clk>; - clock-frequency = <100000>; - }; - - /* chip-internal connection for DMD */ - i2c4: i2c@58784000 { - compatible = "socionext,uniphier-fi2c"; - reg = <0x58784000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 45 4>; - clocks = <&i2c_clk>; - clock-frequency = <400000>; - }; - - /* chip-internal connection for STM */ - i2c5: i2c@58785000 { - compatible = "socionext,uniphier-fi2c"; - reg = <0x58785000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 25 4>; - clocks = <&i2c_clk>; - clock-frequency = <400000>; - }; - - /* chip-internal connection for HDMI */ - i2c6: i2c@58786000 { - compatible = "socionext,uniphier-fi2c"; - reg = <0x58786000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 26 4>; - clocks = <&i2c_clk>; - clock-frequency = <400000>; - }; -}; - -&refclk { - clock-frequency = <25000000>; -}; - -&pinctrl { - compatible = "socionext,proxstream2-pinctrl", "syscon"; -}; diff --git a/sys/gnu/dts/arm/uniphier-pxs2-gentil.dts b/sys/gnu/dts/arm/uniphier-pxs2-gentil.dts deleted file mode 100644 index e27fd4f2a56..00000000000 --- a/sys/gnu/dts/arm/uniphier-pxs2-gentil.dts +++ /dev/null @@ -1,100 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -// -// Device Tree Source for UniPhier PXs2 Gentil Board -// -// Copyright (C) 2015-2016 Socionext Inc. -// Author: Masahiro Yamada - -/dts-v1/; -#include "uniphier-pxs2.dtsi" - -/ { - model = "UniPhier PXs2 Gentil Board"; - compatible = "socionext,uniphier-pxs2-gentil", - "socionext,uniphier-pxs2"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - aliases { - serial0 = &serial2; - serial1 = &serial0; - serial2 = &serial1; - i2c0 = &i2c0; - i2c2 = &i2c2; - i2c4 = &i2c4; - i2c5 = &i2c5; - i2c6 = &i2c6; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x80000000>; - }; - - sound { - compatible = "audio-graph-card"; - label = "UniPhier PXs2"; - dais = <&i2s_port2>; - }; -}; - -&serial2 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - eeprom@54 { - compatible = "st,24c64", "atmel,24c64"; - reg = <0x54>; - pagesize = <32>; - }; -}; - -&i2s_aux { - dai-format = "i2s"; - remote-endpoint = <&wm_speaker>; -}; - -&i2c2 { - status = "okay"; - - wm8960@1a { - compatible = "wlf,wm8960"; - reg = <0x1a>; - #sound-dai-cells = <0>; - - port@0 { - wm_speaker: endpoint { - dai-format = "i2s"; - remote-endpoint = <&i2s_aux>; - }; - }; - }; -}; - -&emmc { - status = "okay"; -}; - -ð { - status = "okay"; - phy-handle = <ðphy>; -}; - -&mdio { - ethphy: ethphy@1 { - reg = <1>; - }; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/uniphier-pxs2-vodka.dts b/sys/gnu/dts/arm/uniphier-pxs2-vodka.dts deleted file mode 100644 index 23fe42b7408..00000000000 --- a/sys/gnu/dts/arm/uniphier-pxs2-vodka.dts +++ /dev/null @@ -1,97 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -// -// Device Tree Source for UniPhier PXs2 Vodka Board -// -// Copyright (C) 2015-2016 Socionext Inc. -// Author: Masahiro Yamada - -/dts-v1/; -#include "uniphier-pxs2.dtsi" - -/ { - model = "UniPhier PXs2 Vodka Board"; - compatible = "socionext,uniphier-pxs2-vodka", "socionext,uniphier-pxs2"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - aliases { - serial0 = &serial2; - serial1 = &serial0; - serial2 = &serial1; - i2c0 = &i2c0; - i2c4 = &i2c4; - i2c5 = &i2c5; - i2c6 = &i2c6; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x80000000>; - }; - - sound { - compatible = "audio-graph-card"; - label = "UniPhier PXs2"; - dais = <&spdif_port0 - &comp_spdif_port0>; - }; - - spdif-out { - compatible = "linux,spdif-dit"; - #sound-dai-cells = <0>; - - port@0 { - spdif_tx: endpoint { - remote-endpoint = <&spdif_hiecout1>; - }; - }; - }; - - comp-spdif-out { - compatible = "linux,spdif-dit"; - #sound-dai-cells = <0>; - - port@0 { - comp_spdif_tx: endpoint { - remote-endpoint = <&comp_spdif_hiecout1>; - }; - }; - }; -}; - -&serial2 { - status = "okay"; -}; - -&spdif_hiecout1 { - remote-endpoint = <&spdif_tx>; -}; - -&comp_spdif_hiecout1 { - remote-endpoint = <&comp_spdif_tx>; -}; - -&i2c0 { - status = "okay"; -}; - -&emmc { - status = "okay"; -}; - -ð { - status = "okay"; - phy-handle = <ðphy>; -}; - -&mdio { - ethphy: ethphy@1 { - reg = <1>; - }; -}; - -&usb0 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/uniphier-pxs2.dtsi b/sys/gnu/dts/arm/uniphier-pxs2.dtsi deleted file mode 100644 index 13b0d4a7741..00000000000 --- a/sys/gnu/dts/arm/uniphier-pxs2.dtsi +++ /dev/null @@ -1,782 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -// -// Device Tree Source for UniPhier PXs2 SoC -// -// Copyright (C) 2015-2016 Socionext Inc. -// Author: Masahiro Yamada - -#include -#include - -/ { - compatible = "socionext,uniphier-pxs2"; - #address-cells = <1>; - #size-cells = <1>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - clocks = <&sys_clk 32>; - enable-method = "psci"; - next-level-cache = <&l2>; - operating-points-v2 = <&cpu_opp>; - #cooling-cells = <2>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <1>; - clocks = <&sys_clk 32>; - enable-method = "psci"; - next-level-cache = <&l2>; - operating-points-v2 = <&cpu_opp>; - #cooling-cells = <2>; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <2>; - clocks = <&sys_clk 32>; - enable-method = "psci"; - next-level-cache = <&l2>; - operating-points-v2 = <&cpu_opp>; - #cooling-cells = <2>; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <3>; - clocks = <&sys_clk 32>; - enable-method = "psci"; - next-level-cache = <&l2>; - operating-points-v2 = <&cpu_opp>; - #cooling-cells = <2>; - }; - }; - - cpu_opp: opp-table { - compatible = "operating-points-v2"; - opp-shared; - - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - clock-latency-ns = <300>; - }; - opp-150000000 { - opp-hz = /bits/ 64 <150000000>; - clock-latency-ns = <300>; - }; - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - clock-latency-ns = <300>; - }; - opp-300000000 { - opp-hz = /bits/ 64 <300000000>; - clock-latency-ns = <300>; - }; - opp-400000000 { - opp-hz = /bits/ 64 <400000000>; - clock-latency-ns = <300>; - }; - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - clock-latency-ns = <300>; - }; - opp-800000000 { - opp-hz = /bits/ 64 <800000000>; - clock-latency-ns = <300>; - }; - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - clock-latency-ns = <300>; - }; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - clocks { - refclk: ref { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - - arm_timer_clk: arm-timer { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <50000000>; - }; - }; - - thermal-zones { - cpu-thermal { - polling-delay-passive = <250>; /* 250ms */ - polling-delay = <1000>; /* 1000ms */ - thermal-sensors = <&pvtctl>; - - trips { - cpu_crit: cpu-crit { - temperature = <95000>; /* 95C */ - hysteresis = <2000>; - type = "critical"; - }; - cpu_alert: cpu-alert { - temperature = <85000>; /* 85C */ - hysteresis = <2000>; - type = "passive"; - }; - }; - - cooling-maps { - map { - trip = <&cpu_alert>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - interrupt-parent = <&intc>; - - l2: l2-cache@500c0000 { - compatible = "socionext,uniphier-system-cache"; - reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, - <0x506c0000 0x400>; - interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>; - cache-unified; - cache-size = <(1280 * 1024)>; - cache-sets = <512>; - cache-line-size = <128>; - cache-level = <2>; - }; - - spi0: spi@54006000 { - compatible = "socionext,uniphier-scssi"; - status = "disabled"; - reg = <0x54006000 0x100>; - interrupts = <0 39 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi0>; - clocks = <&peri_clk 11>; - resets = <&peri_rst 11>; - }; - - spi1: spi@54006100 { - compatible = "socionext,uniphier-scssi"; - status = "disabled"; - reg = <0x54006100 0x100>; - interrupts = <0 216 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1>; - clocks = <&peri_clk 11>; - resets = <&peri_rst 11>; - }; - - serial0: serial@54006800 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006800 0x40>; - interrupts = <0 33 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0>; - clocks = <&peri_clk 0>; - resets = <&peri_rst 0>; - }; - - serial1: serial@54006900 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006900 0x40>; - interrupts = <0 35 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - clocks = <&peri_clk 1>; - resets = <&peri_rst 1>; - }; - - serial2: serial@54006a00 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006a00 0x40>; - interrupts = <0 37 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - clocks = <&peri_clk 2>; - resets = <&peri_rst 2>; - }; - - serial3: serial@54006b00 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006b00 0x40>; - interrupts = <0 177 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - clocks = <&peri_clk 3>; - resets = <&peri_rst 3>; - }; - - gpio: gpio@55000000 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000000 0x200>; - interrupt-parent = <&aidet>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl 0 0 0>, - <&pinctrl 96 0 0>; - gpio-ranges-group-names = "gpio_range0", - "gpio_range1"; - ngpios = <232>; - socionext,interrupt-ranges = <0 48 16>, <16 154 5>, - <21 217 3>; - }; - - audio@56000000 { - compatible = "socionext,uniphier-pxs2-aio"; - reg = <0x56000000 0x80000>; - interrupts = <0 144 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ain1>, - <&pinctrl_ain2>, - <&pinctrl_ainiec1>, - <&pinctrl_aout2>, - <&pinctrl_aout3>, - <&pinctrl_aoutiec1>, - <&pinctrl_aoutiec2>; - clock-names = "aio"; - clocks = <&sys_clk 40>; - reset-names = "aio"; - resets = <&sys_rst 40>; - #sound-dai-cells = <1>; - socionext,syscon = <&soc_glue>; - - i2s_port0: port@0 { - i2s_hdmi: endpoint { - }; - }; - - i2s_port1: port@1 { - i2s_line: endpoint { - }; - }; - - i2s_port2: port@2 { - i2s_aux: endpoint { - }; - }; - - spdif_port0: port@3 { - spdif_hiecout1: endpoint { - }; - }; - - spdif_port1: port@4 { - spdif_iecout1: endpoint { - }; - }; - - comp_spdif_port0: port@5 { - comp_spdif_hiecout1: endpoint { - }; - }; - - comp_spdif_port1: port@6 { - comp_spdif_iecout1: endpoint { - }; - }; - }; - - i2c0: i2c@58780000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58780000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 41 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - clocks = <&peri_clk 4>; - resets = <&peri_rst 4>; - clock-frequency = <100000>; - }; - - i2c1: i2c@58781000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58781000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 42 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - clocks = <&peri_clk 5>; - resets = <&peri_rst 5>; - clock-frequency = <100000>; - }; - - i2c2: i2c@58782000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58782000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 43 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - clocks = <&peri_clk 6>; - resets = <&peri_rst 6>; - clock-frequency = <100000>; - }; - - i2c3: i2c@58783000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58783000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 44 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - clocks = <&peri_clk 7>; - resets = <&peri_rst 7>; - clock-frequency = <100000>; - }; - - /* chip-internal connection for DMD */ - i2c4: i2c@58784000 { - compatible = "socionext,uniphier-fi2c"; - reg = <0x58784000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 45 4>; - clocks = <&peri_clk 8>; - resets = <&peri_rst 8>; - clock-frequency = <400000>; - }; - - /* chip-internal connection for STM */ - i2c5: i2c@58785000 { - compatible = "socionext,uniphier-fi2c"; - reg = <0x58785000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 25 4>; - clocks = <&peri_clk 9>; - resets = <&peri_rst 9>; - clock-frequency = <400000>; - }; - - /* chip-internal connection for HDMI */ - i2c6: i2c@58786000 { - compatible = "socionext,uniphier-fi2c"; - reg = <0x58786000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 26 4>; - clocks = <&peri_clk 10>; - resets = <&peri_rst 10>; - clock-frequency = <400000>; - }; - - system_bus: system-bus@58c00000 { - compatible = "socionext,uniphier-system-bus"; - status = "disabled"; - reg = <0x58c00000 0x400>; - #address-cells = <2>; - #size-cells = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_system_bus>; - }; - - smpctrl@59801000 { - compatible = "socionext,uniphier-smpctrl"; - reg = <0x59801000 0x400>; - }; - - sdctrl@59810000 { - compatible = "socionext,uniphier-pxs2-sdctrl", - "simple-mfd", "syscon"; - reg = <0x59810000 0x400>; - - sd_clk: clock { - compatible = "socionext,uniphier-pxs2-sd-clock"; - #clock-cells = <1>; - }; - - sd_rst: reset { - compatible = "socionext,uniphier-pxs2-sd-reset"; - #reset-cells = <1>; - }; - }; - - perictrl@59820000 { - compatible = "socionext,uniphier-pxs2-perictrl", - "simple-mfd", "syscon"; - reg = <0x59820000 0x200>; - - peri_clk: clock { - compatible = "socionext,uniphier-pxs2-peri-clock"; - #clock-cells = <1>; - }; - - peri_rst: reset { - compatible = "socionext,uniphier-pxs2-peri-reset"; - #reset-cells = <1>; - }; - }; - - emmc: sdhc@5a000000 { - compatible = "socionext,uniphier-sd-v3.1.1"; - status = "disabled"; - reg = <0x5a000000 0x800>; - interrupts = <0 78 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_emmc>; - clocks = <&sd_clk 1>; - reset-names = "host", "hw"; - resets = <&sd_rst 1>, <&sd_rst 6>; - bus-width = <8>; - cap-mmc-highspeed; - cap-mmc-hw-reset; - non-removable; - }; - - sd: sdhc@5a400000 { - compatible = "socionext,uniphier-sd-v3.1.1"; - status = "disabled"; - reg = <0x5a400000 0x800>; - interrupts = <0 76 4>; - pinctrl-names = "default", "uhs"; - pinctrl-0 = <&pinctrl_sd>; - pinctrl-1 = <&pinctrl_sd_uhs>; - clocks = <&sd_clk 0>; - reset-names = "host"; - resets = <&sd_rst 0>; - bus-width = <4>; - cap-sd-highspeed; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - }; - - soc_glue: soc-glue@5f800000 { - compatible = "socionext,uniphier-pxs2-soc-glue", - "simple-mfd", "syscon"; - reg = <0x5f800000 0x2000>; - - pinctrl: pinctrl { - compatible = "socionext,uniphier-pxs2-pinctrl"; - }; - }; - - soc-glue@5f900000 { - compatible = "socionext,uniphier-pxs2-soc-glue-debug", - "simple-mfd"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x5f900000 0x2000>; - - efuse@100 { - compatible = "socionext,uniphier-efuse"; - reg = <0x100 0x28>; - }; - - efuse@200 { - compatible = "socionext,uniphier-efuse"; - reg = <0x200 0x58>; - }; - }; - - aidet: aidet@5fc20000 { - compatible = "socionext,uniphier-pxs2-aidet"; - reg = <0x5fc20000 0x200>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - timer@60000200 { - compatible = "arm,cortex-a9-global-timer"; - reg = <0x60000200 0x20>; - interrupts = <1 11 0xf04>; - clocks = <&arm_timer_clk>; - }; - - timer@60000600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0x60000600 0x20>; - interrupts = <1 13 0xf04>; - clocks = <&arm_timer_clk>; - }; - - intc: interrupt-controller@60001000 { - compatible = "arm,cortex-a9-gic"; - reg = <0x60001000 0x1000>, - <0x60000100 0x100>; - #interrupt-cells = <3>; - interrupt-controller; - }; - - sysctrl@61840000 { - compatible = "socionext,uniphier-pxs2-sysctrl", - "simple-mfd", "syscon"; - reg = <0x61840000 0x10000>; - - sys_clk: clock { - compatible = "socionext,uniphier-pxs2-clock"; - #clock-cells = <1>; - }; - - sys_rst: reset { - compatible = "socionext,uniphier-pxs2-reset"; - #reset-cells = <1>; - }; - - pvtctl: pvtctl { - compatible = "socionext,uniphier-pxs2-thermal"; - interrupts = <0 3 4>; - #thermal-sensor-cells = <0>; - socionext,tmod-calibration = <0x0f86 0x6844>; - }; - }; - - eth: ethernet@65000000 { - compatible = "socionext,uniphier-pxs2-ave4"; - status = "disabled"; - reg = <0x65000000 0x8500>; - interrupts = <0 66 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ether_rgmii>; - clock-names = "ether"; - clocks = <&sys_clk 6>; - reset-names = "ether"; - resets = <&sys_rst 6>; - phy-mode = "rgmii"; - local-mac-address = [00 00 00 00 00 00]; - socionext,syscon-phy-mode = <&soc_glue 0>; - - mdio: mdio { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - usb0: usb@65a00000 { - compatible = "socionext,uniphier-dwc3", "snps,dwc3"; - status = "disabled"; - reg = <0x65a00000 0xcd00>; - interrupt-names = "host", "peripheral"; - interrupts = <0 134 4>, <0 135 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>; - clock-names = "ref", "bus_early", "suspend"; - clocks = <&sys_clk 14>, <&sys_clk 14>, <&sys_clk 14>; - resets = <&usb0_rst 15>; - phys = <&usb0_hsphy0>, <&usb0_hsphy1>, - <&usb0_ssphy0>, <&usb0_ssphy1>; - dr_mode = "host"; - }; - - usb-glue@65b00000 { - compatible = "socionext,uniphier-pxs2-dwc3-glue", - "simple-mfd"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x65b00000 0x400>; - - usb0_rst: reset@0 { - compatible = "socionext,uniphier-pxs2-usb3-reset"; - reg = <0x0 0x4>; - #reset-cells = <1>; - clock-names = "link"; - clocks = <&sys_clk 14>; - reset-names = "link"; - resets = <&sys_rst 14>; - }; - - usb0_vbus0: regulator@100 { - compatible = "socionext,uniphier-pxs2-usb3-regulator"; - reg = <0x100 0x10>; - clock-names = "link"; - clocks = <&sys_clk 14>; - reset-names = "link"; - resets = <&sys_rst 14>; - }; - - usb0_vbus1: regulator@110 { - compatible = "socionext,uniphier-pxs2-usb3-regulator"; - reg = <0x110 0x10>; - clock-names = "link"; - clocks = <&sys_clk 14>; - reset-names = "link"; - resets = <&sys_rst 14>; - }; - - usb0_hsphy0: hs-phy@200 { - compatible = "socionext,uniphier-pxs2-usb3-hsphy"; - reg = <0x200 0x10>; - #phy-cells = <0>; - clock-names = "link", "phy"; - clocks = <&sys_clk 14>, <&sys_clk 16>; - reset-names = "link", "phy"; - resets = <&sys_rst 14>, <&sys_rst 16>; - vbus-supply = <&usb0_vbus0>; - }; - - usb0_hsphy1: hs-phy@210 { - compatible = "socionext,uniphier-pxs2-usb3-hsphy"; - reg = <0x210 0x10>; - #phy-cells = <0>; - clock-names = "link", "phy"; - clocks = <&sys_clk 14>, <&sys_clk 16>; - reset-names = "link", "phy"; - resets = <&sys_rst 14>, <&sys_rst 16>; - vbus-supply = <&usb0_vbus1>; - }; - - usb0_ssphy0: ss-phy@300 { - compatible = "socionext,uniphier-pxs2-usb3-ssphy"; - reg = <0x300 0x10>; - #phy-cells = <0>; - clock-names = "link", "phy"; - clocks = <&sys_clk 14>, <&sys_clk 17>; - reset-names = "link", "phy"; - resets = <&sys_rst 14>, <&sys_rst 17>; - vbus-supply = <&usb0_vbus0>; - }; - - usb0_ssphy1: ss-phy@310 { - compatible = "socionext,uniphier-pxs2-usb3-ssphy"; - reg = <0x310 0x10>; - #phy-cells = <0>; - clock-names = "link", "phy"; - clocks = <&sys_clk 14>, <&sys_clk 18>; - reset-names = "link", "phy"; - resets = <&sys_rst 14>, <&sys_rst 18>; - vbus-supply = <&usb0_vbus1>; - }; - }; - - usb1: usb@65c00000 { - compatible = "socionext,uniphier-dwc3", "snps,dwc3"; - status = "disabled"; - reg = <0x65c00000 0xcd00>; - interrupt-names = "host", "peripheral"; - interrupts = <0 137 4>, <0 138 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>; - clock-names = "ref", "bus_early", "suspend"; - clocks = <&sys_clk 15>, <&sys_clk 15>, <&sys_clk 15>; - resets = <&usb1_rst 15>; - phys = <&usb1_hsphy0>, <&usb1_hsphy1>, <&usb1_ssphy0>; - dr_mode = "host"; - }; - - usb-glue@65d00000 { - compatible = "socionext,uniphier-pxs2-dwc3-glue", - "simple-mfd"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x65d00000 0x400>; - - usb1_rst: reset@0 { - compatible = "socionext,uniphier-pxs2-usb3-reset"; - reg = <0x0 0x4>; - #reset-cells = <1>; - clock-names = "link"; - clocks = <&sys_clk 15>; - reset-names = "link"; - resets = <&sys_rst 15>; - }; - - usb1_vbus0: regulator@100 { - compatible = "socionext,uniphier-pxs2-usb3-regulator"; - reg = <0x100 0x10>; - clock-names = "link"; - clocks = <&sys_clk 15>; - reset-names = "link"; - resets = <&sys_rst 15>; - }; - - usb1_vbus1: regulator@110 { - compatible = "socionext,uniphier-pxs2-usb3-regulator"; - reg = <0x110 0x10>; - clock-names = "link"; - clocks = <&sys_clk 15>; - reset-names = "link"; - resets = <&sys_rst 15>; - }; - - usb1_hsphy0: hs-phy@200 { - compatible = "socionext,uniphier-pxs2-usb3-hsphy"; - reg = <0x200 0x10>; - #phy-cells = <0>; - clock-names = "link", "phy"; - clocks = <&sys_clk 15>, <&sys_clk 20>; - reset-names = "link", "phy"; - resets = <&sys_rst 15>, <&sys_rst 20>; - vbus-supply = <&usb1_vbus0>; - }; - - usb1_hsphy1: hs-phy@210 { - compatible = "socionext,uniphier-pxs2-usb3-hsphy"; - reg = <0x210 0x10>; - #phy-cells = <0>; - clock-names = "link", "phy"; - clocks = <&sys_clk 15>, <&sys_clk 20>; - reset-names = "link", "phy"; - resets = <&sys_rst 15>, <&sys_rst 20>; - vbus-supply = <&usb1_vbus1>; - }; - - usb1_ssphy0: ss-phy@300 { - compatible = "socionext,uniphier-pxs2-usb3-ssphy"; - reg = <0x300 0x10>; - #phy-cells = <0>; - clock-names = "link", "phy"; - clocks = <&sys_clk 15>, <&sys_clk 21>; - reset-names = "link", "phy"; - resets = <&sys_rst 15>, <&sys_rst 21>; - vbus-supply = <&usb1_vbus0>; - }; - }; - - nand: nand@68000000 { - compatible = "socionext,uniphier-denali-nand-v5b"; - status = "disabled"; - reg-names = "nand_data", "denali_reg"; - reg = <0x68000000 0x20>, <0x68100000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 65 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nand>; - clock-names = "nand", "nand_x", "ecc"; - clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>; - reset-names = "nand", "reg"; - resets = <&sys_rst 2>, <&sys_rst 2>; - }; - }; -}; - -#include "uniphier-pinctrl.dtsi" diff --git a/sys/gnu/dts/arm/uniphier-ref-daughter.dtsi b/sys/gnu/dts/arm/uniphier-ref-daughter.dtsi deleted file mode 100644 index 04e60c29531..00000000000 --- a/sys/gnu/dts/arm/uniphier-ref-daughter.dtsi +++ /dev/null @@ -1,14 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -// -// Device Tree Source for UniPhier Reference Daughter Board -// -// Copyright (C) 2015-2017 Socionext Inc. -// Author: Masahiro Yamada - -&i2c0 { - eeprom@50 { - compatible = "microchip,24lc128"; - reg = <0x50>; - pagesize = <64>; - }; -}; diff --git a/sys/gnu/dts/arm/uniphier-sld8-ref.dts b/sys/gnu/dts/arm/uniphier-sld8-ref.dts deleted file mode 100644 index cf9ea0b1506..00000000000 --- a/sys/gnu/dts/arm/uniphier-sld8-ref.dts +++ /dev/null @@ -1,88 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -// -// Device Tree Source for UniPhier sLD8 Reference Board -// -// Copyright (C) 2015-2016 Socionext Inc. -// Author: Masahiro Yamada - -/dts-v1/; -#include "uniphier-sld8.dtsi" -#include "uniphier-ref-daughter.dtsi" -#include "uniphier-support-card.dtsi" - -/ { - model = "UniPhier sLD8 Reference Board"; - compatible = "socionext,uniphier-sld8-ref", "socionext,uniphier-sld8"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - aliases { - serial0 = &serial0; - serial1 = &serial1; - serial2 = &serial2; - serial3 = &serial3; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000>; - }; -}; - -ðsc { - interrupts = <0 8>; -}; - -&serial0 { - status = "okay"; -}; - -&serial2 { - status = "okay"; -}; - -&serial3 { - status = "okay"; -}; - -&gpio { - xirq0 { - gpio-hog; - gpios = ; - input; - }; -}; - -&i2c0 { - status = "okay"; -}; - -&sd { - status = "okay"; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; - -&usb2 { - status = "okay"; -}; - -&nand { - status = "okay"; - - nand@0 { - reg = <0>; - }; -}; diff --git a/sys/gnu/dts/arm/uniphier-sld8.dtsi b/sys/gnu/dts/arm/uniphier-sld8.dtsi deleted file mode 100644 index 4fc6676f548..00000000000 --- a/sys/gnu/dts/arm/uniphier-sld8.dtsi +++ /dev/null @@ -1,423 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -// -// Device Tree Source for UniPhier sLD8 SoC -// -// Copyright (C) 2015-2016 Socionext Inc. -// Author: Masahiro Yamada - -#include - -/ { - compatible = "socionext,uniphier-sld8"; - #address-cells = <1>; - #size-cells = <1>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - enable-method = "psci"; - next-level-cache = <&l2>; - }; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - clocks { - refclk: ref { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - - arm_timer_clk: arm-timer { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <50000000>; - }; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - interrupt-parent = <&intc>; - - l2: l2-cache@500c0000 { - compatible = "socionext,uniphier-system-cache"; - reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, - <0x506c0000 0x400>; - interrupts = <0 174 4>, <0 175 4>; - cache-unified; - cache-size = <(256 * 1024)>; - cache-sets = <256>; - cache-line-size = <128>; - cache-level = <2>; - }; - - spi: spi@54006000 { - compatible = "socionext,uniphier-scssi"; - status = "disabled"; - reg = <0x54006000 0x100>; - interrupts = <0 39 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi0>; - clocks = <&peri_clk 11>; - resets = <&peri_rst 11>; - }; - - serial0: serial@54006800 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006800 0x40>; - interrupts = <0 33 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0>; - clocks = <&peri_clk 0>; - resets = <&peri_rst 0>; - }; - - serial1: serial@54006900 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006900 0x40>; - interrupts = <0 35 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - clocks = <&peri_clk 1>; - resets = <&peri_rst 1>; - }; - - serial2: serial@54006a00 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006a00 0x40>; - interrupts = <0 37 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - clocks = <&peri_clk 2>; - resets = <&peri_rst 2>; - }; - - serial3: serial@54006b00 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006b00 0x40>; - interrupts = <0 29 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - clocks = <&peri_clk 3>; - resets = <&peri_rst 3>; - }; - - gpio: gpio@55000000 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000000 0x200>; - interrupt-parent = <&aidet>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl 0 0 0>, - <&pinctrl 104 0 0>, - <&pinctrl 112 0 0>; - gpio-ranges-group-names = "gpio_range0", - "gpio_range1", - "gpio_range2"; - ngpios = <136>; - socionext,interrupt-ranges = <0 48 13>, <14 62 2>; - }; - - i2c0: i2c@58400000 { - compatible = "socionext,uniphier-i2c"; - status = "disabled"; - reg = <0x58400000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 41 1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - clocks = <&peri_clk 4>; - resets = <&peri_rst 4>; - clock-frequency = <100000>; - }; - - i2c1: i2c@58480000 { - compatible = "socionext,uniphier-i2c"; - status = "disabled"; - reg = <0x58480000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 42 1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - clocks = <&peri_clk 5>; - resets = <&peri_rst 5>; - clock-frequency = <100000>; - }; - - /* chip-internal connection for DMD */ - i2c2: i2c@58500000 { - compatible = "socionext,uniphier-i2c"; - reg = <0x58500000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 43 1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - clocks = <&peri_clk 6>; - resets = <&peri_rst 6>; - clock-frequency = <400000>; - }; - - i2c3: i2c@58580000 { - compatible = "socionext,uniphier-i2c"; - status = "disabled"; - reg = <0x58580000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 44 1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - clocks = <&peri_clk 7>; - resets = <&peri_rst 7>; - clock-frequency = <100000>; - }; - - system_bus: system-bus@58c00000 { - compatible = "socionext,uniphier-system-bus"; - status = "disabled"; - reg = <0x58c00000 0x400>; - #address-cells = <2>; - #size-cells = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_system_bus>; - }; - - smpctrl@59801000 { - compatible = "socionext,uniphier-smpctrl"; - reg = <0x59801000 0x400>; - }; - - mioctrl@59810000 { - compatible = "socionext,uniphier-sld8-mioctrl", - "simple-mfd", "syscon"; - reg = <0x59810000 0x800>; - - mio_clk: clock { - compatible = "socionext,uniphier-sld8-mio-clock"; - #clock-cells = <1>; - }; - - mio_rst: reset { - compatible = "socionext,uniphier-sld8-mio-reset"; - #reset-cells = <1>; - }; - }; - - perictrl@59820000 { - compatible = "socionext,uniphier-sld8-perictrl", - "simple-mfd", "syscon"; - reg = <0x59820000 0x200>; - - peri_clk: clock { - compatible = "socionext,uniphier-sld8-peri-clock"; - #clock-cells = <1>; - }; - - peri_rst: reset { - compatible = "socionext,uniphier-sld8-peri-reset"; - #reset-cells = <1>; - }; - }; - - dmac: dma-controller@5a000000 { - compatible = "socionext,uniphier-mio-dmac"; - reg = <0x5a000000 0x1000>; - interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>, - <0 71 4>, <0 72 4>, <0 73 4>; - clocks = <&mio_clk 7>; - resets = <&mio_rst 7>; - #dma-cells = <1>; - }; - - sd: sdhc@5a400000 { - compatible = "socionext,uniphier-sd-v2.91"; - status = "disabled"; - reg = <0x5a400000 0x200>; - interrupts = <0 76 4>; - pinctrl-names = "default", "uhs"; - pinctrl-0 = <&pinctrl_sd>; - pinctrl-1 = <&pinctrl_sd_uhs>; - clocks = <&mio_clk 0>; - reset-names = "host", "bridge"; - resets = <&mio_rst 0>, <&mio_rst 3>; - dma-names = "rx-tx"; - dmas = <&dmac 4>; - bus-width = <4>; - cap-sd-highspeed; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - }; - - emmc: sdhc@5a500000 { - compatible = "socionext,uniphier-sd-v2.91"; - status = "disabled"; - reg = <0x5a500000 0x200>; - interrupts = <0 78 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_emmc>; - clocks = <&mio_clk 1>; - reset-names = "host", "bridge", "hw"; - resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>; - dma-names = "rx-tx"; - dmas = <&dmac 6>; - bus-width = <8>; - cap-mmc-highspeed; - cap-mmc-hw-reset; - non-removable; - }; - - usb0: usb@5a800100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a800100 0x100>; - interrupts = <0 80 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb0>; - clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>, - <&mio_clk 12>; - resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>, - <&mio_rst 12>; - has-transaction-translator; - }; - - usb1: usb@5a810100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a810100 0x100>; - interrupts = <0 81 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb1>; - clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>, - <&mio_clk 13>; - resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>, - <&mio_rst 13>; - has-transaction-translator; - }; - - usb2: usb@5a820100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a820100 0x100>; - interrupts = <0 82 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb2>; - clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 10>, - <&mio_clk 14>; - resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>, - <&mio_rst 14>; - has-transaction-translator; - }; - - soc-glue@5f800000 { - compatible = "socionext,uniphier-sld8-soc-glue", - "simple-mfd", "syscon"; - reg = <0x5f800000 0x2000>; - - pinctrl: pinctrl { - compatible = "socionext,uniphier-sld8-pinctrl"; - }; - }; - - soc-glue@5f900000 { - compatible = "socionext,uniphier-sld8-soc-glue-debug", - "simple-mfd"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x5f900000 0x2000>; - - efuse@100 { - compatible = "socionext,uniphier-efuse"; - reg = <0x100 0x28>; - }; - - efuse@200 { - compatible = "socionext,uniphier-efuse"; - reg = <0x200 0x14>; - }; - }; - - timer@60000200 { - compatible = "arm,cortex-a9-global-timer"; - reg = <0x60000200 0x20>; - interrupts = <1 11 0x104>; - clocks = <&arm_timer_clk>; - }; - - timer@60000600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0x60000600 0x20>; - interrupts = <1 13 0x104>; - clocks = <&arm_timer_clk>; - }; - - intc: interrupt-controller@60001000 { - compatible = "arm,cortex-a9-gic"; - reg = <0x60001000 0x1000>, - <0x60000100 0x100>; - #interrupt-cells = <3>; - interrupt-controller; - }; - - aidet: aidet@61830000 { - compatible = "socionext,uniphier-sld8-aidet"; - reg = <0x61830000 0x200>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - sysctrl@61840000 { - compatible = "socionext,uniphier-sld8-sysctrl", - "simple-mfd", "syscon"; - reg = <0x61840000 0x10000>; - - sys_clk: clock { - compatible = "socionext,uniphier-sld8-clock"; - #clock-cells = <1>; - }; - - sys_rst: reset { - compatible = "socionext,uniphier-sld8-reset"; - #reset-cells = <1>; - }; - }; - - nand: nand@68000000 { - compatible = "socionext,uniphier-denali-nand-v5a"; - status = "disabled"; - reg-names = "nand_data", "denali_reg"; - reg = <0x68000000 0x20>, <0x68100000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 65 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nand>; - clock-names = "nand", "nand_x", "ecc"; - clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>; - reset-names = "nand", "reg"; - resets = <&sys_rst 2>, <&sys_rst 2>; - }; - }; -}; - -#include "uniphier-pinctrl.dtsi" diff --git a/sys/gnu/dts/arm/uniphier-support-card.dtsi b/sys/gnu/dts/arm/uniphier-support-card.dtsi deleted file mode 100644 index bf441c2eff7..00000000000 --- a/sys/gnu/dts/arm/uniphier-support-card.dtsi +++ /dev/null @@ -1,33 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -// -// Device Tree Source for UniPhier Support Card (Expansion Board) -// -// Copyright (C) 2015-2017 Socionext Inc. -// Author: Masahiro Yamada - -&system_bus { - status = "okay"; - ranges = <1 0x00000000 0x42000000 0x02000000>; - - support_card: support-card@1,1f00000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 1 0x01f00000 0x00100000>; - interrupt-parent = <&gpio>; - - ethsc: ethernet@0 { - compatible = "smsc,lan9118", "smsc,lan9115"; - reg = <0x00000000 0x1000>; - phy-mode = "mii"; - reg-io-width = <4>; - }; - - serialsc: uart@b0000 { - compatible = "ns16550a"; - reg = <0x000b0000 0x20>; - clock-frequency = <12288000>; - reg-shift = <1>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/usb_a9260.dts b/sys/gnu/dts/arm/usb_a9260.dts deleted file mode 100644 index ec8cd86b260..00000000000 --- a/sys/gnu/dts/arm/usb_a9260.dts +++ /dev/null @@ -1,31 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * usb_a9260.dts - Device Tree file for Caloa USB A9260 board - * - * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD - */ -/dts-v1/; -#include "at91sam9260.dtsi" -#include "usb_a9260_common.dtsi" - -/ { - model = "Calao USB A9260"; - compatible = "calao,usb-a9260", "atmel,at91sam9260", "atmel,at91sam9"; - - chosen { - bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock5 rw rootfstype=ubifs"; - }; - - memory { - reg = <0x20000000 0x4000000>; - }; - - ahb { - apb { - shdwc@fffffd10 { - atmel,wakeup-counter = <10>; - atmel,wakeup-rtt-timer; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/usb_a9260_common.dtsi b/sys/gnu/dts/arm/usb_a9260_common.dtsi deleted file mode 100644 index 8744b5f6f79..00000000000 --- a/sys/gnu/dts/arm/usb_a9260_common.dtsi +++ /dev/null @@ -1,146 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * usb_a926x.dts - Device Tree file for Caloa USB A926x board - * - * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD - */ - -/ { - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <12000000>; - }; - }; - - ahb { - apb { - dbgu: serial@fffff200 { - status = "okay"; - }; - - tcb0: timer@fffa0000 { - timer@0 { - compatible = "atmel,tcb-timer"; - reg = <0>, <1>; - }; - - timer@2 { - compatible = "atmel,tcb-timer"; - reg = <2>; - }; - }; - - macb0: ethernet@fffc4000 { - phy-mode = "rmii"; - status = "okay"; - }; - - usb1: gadget@fffa4000 { - atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - }; - - ebi: ebi@10000000 { - status = "okay"; - - nand_controller: nand-controller { - status = "okay"; - pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>; - pinctrl-names = "default"; - - nand@3 { - reg = <0x3 0x0 0x800000>; - rb-gpios = <&pioC 13 GPIO_ACTIVE_HIGH>; - cs-gpios = <&pioC 14 GPIO_ACTIVE_HIGH>; - nand-bus-width = <8>; - nand-ecc-mode = "soft"; - nand-on-flash-bbt; - label = "atmel_nand"; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - at91bootstrap@0 { - label = "at91bootstrap"; - reg = <0x0 0x20000>; - }; - - barebox@20000 { - label = "barebox"; - reg = <0x20000 0x40000>; - }; - - bareboxenv@60000 { - label = "bareboxenv"; - reg = <0x60000 0x20000>; - }; - - bareboxenv2@80000 { - label = "bareboxenv2"; - reg = <0x80000 0x20000>; - }; - - oftree@80000 { - label = "oftree"; - reg = <0xa0000 0x20000>; - }; - - kernel@a0000 { - label = "kernel"; - reg = <0xc0000 0x400000>; - }; - - rootfs@4a0000 { - label = "rootfs"; - reg = <0x4c0000 0x7800000>; - }; - - data@7ca0000 { - label = "data"; - reg = <0x7cc0000 0x8340000>; - }; - }; - }; - }; - }; - - usb0: ohci@500000 { - num-ports = <2>; - status = "okay"; - }; - }; - - leds { - compatible = "gpio-leds"; - - user_led { - label = "user_led"; - gpios = <&pioB 21 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - user_pb { - label = "user_pb"; - gpios = <&pioB 10 GPIO_ACTIVE_LOW>; - linux,code = <28>; - wakeup-source; - }; - }; - - i2c-gpio-0 { - status = "okay"; - }; -}; diff --git a/sys/gnu/dts/arm/usb_a9263.dts b/sys/gnu/dts/arm/usb_a9263.dts deleted file mode 100644 index e7a705fddda..00000000000 --- a/sys/gnu/dts/arm/usb_a9263.dts +++ /dev/null @@ -1,174 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * usb_a9263.dts - Device Tree file for Caloa USB A9293 board - * - * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD - */ -/dts-v1/; -#include "at91sam9263.dtsi" - -/ { - model = "Calao USB A9263"; - compatible = "atmel,usb-a9263", "atmel,at91sam9263", "atmel,at91sam9"; - - chosen { - bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock5 rw rootfstype=ubifs"; - }; - - memory { - reg = <0x20000000 0x4000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <12000000>; - }; - }; - - ahb { - apb { - dbgu: serial@ffffee00 { - status = "okay"; - }; - - tcb0: timer@fff7c000 { - timer@0 { - compatible = "atmel,tcb-timer"; - reg = <0>, <1>; - }; - - timer@2 { - compatible = "atmel,tcb-timer"; - reg = <2>; - }; - }; - - macb0: ethernet@fffbc000 { - phy-mode = "rmii"; - status = "okay"; - }; - - usb1: gadget@fff78000 { - atmel,vbus-gpio = <&pioB 11 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - spi0: spi@fffa4000 { - cs-gpios = <&pioB 15 GPIO_ACTIVE_HIGH>; - status = "okay"; - mtd_dataflash@0 { - compatible = "atmel,at45", "atmel,dataflash"; - reg = <0>; - spi-max-frequency = <15000000>; - }; - }; - - shdwc@fffffd10 { - atmel,wakeup-counter = <10>; - atmel,wakeup-rtt-timer; - }; - }; - - ebi0: ebi@10000000 { - status = "okay"; - - nand_controller: nand-controller { - status = "okay"; - pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>; - pinctrl-names = "default"; - - nand@3 { - reg = <0x3 0x0 0x800000>; - rb-gpios = <&pioA 22 GPIO_ACTIVE_HIGH>; - cs-gpios = <&pioA 15 GPIO_ACTIVE_HIGH>; - nand-bus-width = <8>; - nand-ecc-mode = "soft"; - nand-on-flash-bbt; - label = "atmel_nand"; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - at91bootstrap@0 { - label = "at91bootstrap"; - reg = <0x0 0x20000>; - }; - - barebox@20000 { - label = "barebox"; - reg = <0x20000 0x40000>; - }; - - bareboxenv@60000 { - label = "bareboxenv"; - reg = <0x60000 0x20000>; - }; - - bareboxenv2@80000 { - label = "bareboxenv2"; - reg = <0x80000 0x20000>; - }; - - oftree@80000 { - label = "oftree"; - reg = <0xa0000 0x20000>; - }; - - kernel@a0000 { - label = "kernel"; - reg = <0xc0000 0x400000>; - }; - - rootfs@4a0000 { - label = "rootfs"; - reg = <0x4c0000 0x7800000>; - }; - - data@7ca0000 { - label = "data"; - reg = <0x7cc0000 0x8340000>; - }; - }; - }; - }; - }; - - usb0: ohci@a00000 { - num-ports = <2>; - status = "okay"; - }; - }; - - leds { - compatible = "gpio-leds"; - - user_led { - label = "user_led"; - gpios = <&pioB 21 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - user_pb { - label = "user_pb"; - gpios = <&pioB 10 GPIO_ACTIVE_LOW>; - linux,code = <28>; - wakeup-source; - }; - }; - - i2c-gpio-0 { - status = "okay"; - }; -}; diff --git a/sys/gnu/dts/arm/usb_a9g20-dab-mmx.dtsi b/sys/gnu/dts/arm/usb_a9g20-dab-mmx.dtsi deleted file mode 100644 index 08d58081201..00000000000 --- a/sys/gnu/dts/arm/usb_a9g20-dab-mmx.dtsi +++ /dev/null @@ -1,95 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * calao-dab-mmx.dtsi - Device Tree Include file for Calao DAB-MMX Daughter Board - * - * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD - */ - -/ { - ahb { - apb { - usart1: serial@fffb4000 { - status = "okay"; - }; - - usart3: serial@fffd0000 { - status = "okay"; - }; - }; - }; - - i2c-gpio@0 { - status = "okay"; - }; - - leds { - compatible = "gpio-leds"; - - user_led1 { - label = "user_led1"; - gpios = <&pioB 20 GPIO_ACTIVE_LOW>; - }; - -/* -* led already used by mother board but active as high -* user_led2 { -* label = "user_led2"; -* gpios = <&pioB 21 GPIO_ACTIVE_LOW>; -* }; -*/ - user_led3 { - label = "user_led3"; - gpios = <&pioB 22 GPIO_ACTIVE_LOW>; - }; - - user_led4 { - label = "user_led4"; - gpios = <&pioB 23 GPIO_ACTIVE_LOW>; - }; - - red { - label = "red"; - gpios = <&pioB 24 GPIO_ACTIVE_LOW>; - }; - - orange { - label = "orange"; - gpios = <&pioB 30 GPIO_ACTIVE_LOW>; - }; - - green { - label = "green"; - gpios = <&pioB 31 GPIO_ACTIVE_LOW>; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - user_pb1 { - label = "user_pb1"; - gpios = <&pioB 25 GPIO_ACTIVE_LOW>; - linux,code = <0x100>; - }; - - user_pb2 { - label = "user_pb2"; - gpios = <&pioB 13 GPIO_ACTIVE_LOW>; - linux,code = <0x101>; - }; - - user_pb3 { - label = "user_pb3"; - gpios = <&pioA 26 GPIO_ACTIVE_LOW>; - linux,code = <0x102>; - }; - - user_pb4 { - label = "user_pb4"; - gpios = <&pioC 9 GPIO_ACTIVE_LOW>; - linux,code = <0x103>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/usb_a9g20.dts b/sys/gnu/dts/arm/usb_a9g20.dts deleted file mode 100644 index 2f667b083e8..00000000000 --- a/sys/gnu/dts/arm/usb_a9g20.dts +++ /dev/null @@ -1,13 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * usb_a9g20.dts - Device Tree file for Caloa USB A9G20 board - * - * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD - */ -/dts-v1/; -#include "usb_a9g20_common.dtsi" - -/ { - model = "Calao USB A9G20"; - compatible = "calao,usb-a9g20", "atmel,at91sam9g20", "atmel,at91sam9"; -}; diff --git a/sys/gnu/dts/arm/usb_a9g20_common.dtsi b/sys/gnu/dts/arm/usb_a9g20_common.dtsi deleted file mode 100644 index adbe7502473..00000000000 --- a/sys/gnu/dts/arm/usb_a9g20_common.dtsi +++ /dev/null @@ -1,27 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * usb_a9g20.dts - Device Tree file for Caloa USB A9G20 board - * - * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD - */ - -#include "at91sam9g20.dtsi" -#include "usb_a9260_common.dtsi" - -/ { - chosen { - bootargs = "mem=64M root=/dev/mtdblock5 rw rootfstype=ubifs"; - stdout-path = "serial0:115200n8"; - }; - - memory { - reg = <0x20000000 0x4000000>; - }; - - i2c-gpio-0 { - rtc@56 { - compatible = "microcrystal,rv3029"; - reg = <0x56>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/usb_a9g20_lpw.dts b/sys/gnu/dts/arm/usb_a9g20_lpw.dts deleted file mode 100644 index f65712015d4..00000000000 --- a/sys/gnu/dts/arm/usb_a9g20_lpw.dts +++ /dev/null @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * usb_a9g20_lpw.dts - Device Tree file for Caloa USB A9G20 Low Power board - * - * Copyright (C) 2013 Jean-Christophe PLAGNIOL-VILLARD - */ -/dts-v1/; -#include "usb_a9g20_common.dtsi" - -/ { - model = "Calao USB A9G20 Low Power"; - compatible = "calao,usb-a9g20-lpw", "calao,usb-a9g20", "atmel,at91sam9g20", "atmel,at91sam9"; - - ahb { - apb { - spi1: spi@fffcc000 { - cs-gpios = <&pioB 3 GPIO_ACTIVE_HIGH>; - status = "okay"; - mmc-slot@0 { - compatible = "mmc-spi-slot"; - reg = <0>; - voltage-ranges = <3200 3400>; - spi-max-frequency = <25000000>; - interrupt-parent = <&pioC>; - interrupts = <4 IRQ_TYPE_EDGE_BOTH>; - }; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/versatile-ab-ib2.dts b/sys/gnu/dts/arm/versatile-ab-ib2.dts deleted file mode 100644 index 5890cb974f7..00000000000 --- a/sys/gnu/dts/arm/versatile-ab-ib2.dts +++ /dev/null @@ -1,26 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * The Versatile AB with the IB2 expansion board mounted. - * This works as a superset of the Versatile AB. - */ - -#include "versatile-ab.dts" - -/ { - model = "ARM Versatile AB + IB2 board"; - - /* Special IB2 control register */ - ib2_syscon@27000000 { - compatible = "arm,versatile-ib2-syscon", "syscon", "simple-mfd"; - reg = <0x27000000 0x4>; - - led@00.4 { - compatible = "register-bit-led"; - offset = <0x00>; - mask = <0x10>; - label = "versatile-ib2:0"; - linux,default-trigger = "heartbeat"; - default-state = "on"; - }; - }; -}; diff --git a/sys/gnu/dts/arm/versatile-ab.dts b/sys/gnu/dts/arm/versatile-ab.dts deleted file mode 100644 index 37bd41ff8df..00000000000 --- a/sys/gnu/dts/arm/versatile-ab.dts +++ /dev/null @@ -1,440 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -/ { - model = "ARM Versatile AB"; - compatible = "arm,versatile-ab"; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&vic>; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - i2c0 = &i2c0; - }; - - chosen { - stdout-path = &uart0; - }; - - memory { - device_type = "memory"; - reg = <0x0 0x08000000>; - }; - - xtal24mhz: xtal24mhz@24M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - }; - - bridge { - compatible = "ti,ths8134b", "ti,ths8134"; - #address-cells = <1>; - #size-cells = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - vga_bridge_in: endpoint { - remote-endpoint = <&clcd_pads_vga_dac>; - }; - }; - - port@1 { - reg = <1>; - - vga_bridge_out: endpoint { - remote-endpoint = <&vga_con_in>; - }; - }; - }; - }; - - vga { - compatible = "vga-connector"; - - port { - vga_con_in: endpoint { - remote-endpoint = <&vga_bridge_out>; - }; - }; - }; - - core-module@10000000 { - compatible = "arm,core-module-versatile", "syscon", "simple-mfd"; - reg = <0x10000000 0x200>; - - led@08.0 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x01>; - label = "versatile:0"; - linux,default-trigger = "heartbeat"; - default-state = "on"; - }; - led@08.1 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x02>; - label = "versatile:1"; - linux,default-trigger = "mmc0"; - default-state = "off"; - }; - led@08.2 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x04>; - label = "versatile:2"; - linux,default-trigger = "cpu0"; - default-state = "off"; - }; - led@08.3 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x08>; - label = "versatile:3"; - default-state = "off"; - }; - led@08.4 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x10>; - label = "versatile:4"; - default-state = "off"; - }; - led@08.5 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x20>; - label = "versatile:5"; - default-state = "off"; - }; - led@08.6 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x40>; - label = "versatile:6"; - default-state = "off"; - }; - led@08.7 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x80>; - label = "versatile:7"; - default-state = "off"; - }; - - /* OSC1 on AB, OSC4 on PB */ - osc1: cm_aux_osc@24M { - #clock-cells = <0>; - compatible = "arm,versatile-cm-auxosc"; - clocks = <&xtal24mhz>; - }; - - /* The timer clock is the 24 MHz oscillator divided to 1MHz */ - timclk: timclk@1M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <24>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - pclk: pclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - }; - - flash@34000000 { - /* 64 MiB NOR flash in non-interleaved chips */ - compatible = "arm,versatile-flash", "cfi-flash"; - reg = <0x34000000 0x04000000>; - bank-width = <4>; - partitions { - compatible = "arm,arm-firmware-suite"; - }; - }; - - i2c0: i2c@10002000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "arm,versatile-i2c"; - reg = <0x10002000 0x1000>; - - rtc@68 { - compatible = "dallas,ds1338"; - reg = <0x68>; - }; - }; - - net@10010000 { - compatible = "smsc,lan91c111"; - reg = <0x10010000 0x10000>; - interrupts = <25>; - }; - - lcd@10008000 { - compatible = "arm,versatile-lcd"; - reg = <0x10008000 0x1000>; - }; - - amba { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - vic: intc@10140000 { - compatible = "arm,versatile-vic"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x10140000 0x1000>; - clear-mask = <0xffffffff>; - valid-mask = <0xffffffff>; - }; - - sic: intc@10003000 { - compatible = "arm,versatile-sic"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x10003000 0x1000>; - interrupt-parent = <&vic>; - interrupts = <31>; /* Cascaded to vic */ - clear-mask = <0xffffffff>; - /* - * Valid interrupt lines mask according to - * table 4-36 page 4-50 of ARM DUI 0225D - */ - valid-mask = <0x0760031b>; - }; - - dma@10130000 { - compatible = "arm,pl081", "arm,primecell"; - reg = <0x10130000 0x1000>; - interrupts = <17>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - uart0: uart@101f1000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x101f1000 0x1000>; - interrupts = <12>; - clocks = <&xtal24mhz>, <&pclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - uart1: uart@101f2000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x101f2000 0x1000>; - interrupts = <13>; - clocks = <&xtal24mhz>, <&pclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - uart2: uart@101f3000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x101f3000 0x1000>; - interrupts = <14>; - clocks = <&xtal24mhz>, <&pclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - smc@10100000 { - compatible = "arm,primecell"; - reg = <0x10100000 0x1000>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - mpmc@10110000 { - compatible = "arm,primecell"; - reg = <0x10110000 0x1000>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - display@10120000 { - compatible = "arm,pl110", "arm,primecell"; - reg = <0x10120000 0x1000>; - interrupts = <16>; - clocks = <&osc1>, <&pclk>; - clock-names = "clcdclk", "apb_pclk"; - /* 800x600 16bpp @ 36MHz works fine */ - max-memory-bandwidth = <54000000>; - - /* - * This port is routed through a PLD (Programmable - * Logic Device) that routes the output from the CLCD - * (after transformations) to the VGA DAC and also an - * external panel connector. The PLD is essential for - * supporting RGB565/BGR565. - * - * The signals from the port thus reaches two endpoints. - * The PLD is managed through a few special bits in the - * FPGA "sysreg". - * - * This arrangement can be clearly seen in - * ARM DUI 0225D, page 3-41, figure 3-19. - */ - port@0 { - #address-cells = <1>; - #size-cells = <0>; - - clcd_pads_panel: endpoint@0 { - reg = <0>; - remote-endpoint = <&panel_in>; - arm,pl11x,tft-r0g0b0-pads = <0 8 16>; - }; - clcd_pads_vga_dac: endpoint@1 { - reg = <1>; - remote-endpoint = <&vga_bridge_in>; - arm,pl11x,tft-r0g0b0-pads = <0 8 16>; - }; - }; - }; - - sctl@101e0000 { - compatible = "arm,primecell"; - reg = <0x101e0000 0x1000>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - watchdog@101e1000 { - compatible = "arm,primecell"; - reg = <0x101e1000 0x1000>; - interrupts = <0>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - timer@101e2000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x101e2000 0x1000>; - interrupts = <4>; - clocks = <&timclk>, <&timclk>, <&pclk>; - clock-names = "timer0", "timer1", "apb_pclk"; - }; - - timer@101e3000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x101e3000 0x1000>; - interrupts = <5>; - clocks = <&timclk>, <&timclk>, <&pclk>; - clock-names = "timer0", "timer1", "apb_pclk"; - }; - - gpio0: gpio@101e4000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x101e4000 0x1000>; - gpio-controller; - interrupts = <6>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - gpio1: gpio@101e5000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x101e5000 0x1000>; - interrupts = <7>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - rtc@101e8000 { - compatible = "arm,pl030", "arm,primecell"; - reg = <0x101e8000 0x1000>; - interrupts = <10>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - sci@101f0000 { - compatible = "arm,primecell"; - reg = <0x101f0000 0x1000>; - interrupts = <15>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - spi@101f4000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x101f4000 0x1000>; - interrupts = <11>; - clocks = <&xtal24mhz>, <&pclk>; - clock-names = "SSPCLK", "apb_pclk"; - }; - - fpga { - compatible = "arm,versatile-fpga", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x10000000 0x10000>; - - sysreg@0 { - compatible = "arm,versatile-sysreg", "syscon", "simple-mfd"; - reg = <0x00000 0x1000>; - - panel: display@0 { - compatible = "arm,versatile-tft-panel"; - - port { - panel_in: endpoint { - remote-endpoint = <&clcd_pads_panel>; - }; - }; - }; - }; - - aaci@4000 { - compatible = "arm,primecell"; - reg = <0x4000 0x1000>; - interrupts = <24>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - mmc@5000 { - compatible = "arm,pl180", "arm,primecell"; - reg = <0x5000 0x1000>; - interrupts-extended = <&vic 22 &sic 1>; - clocks = <&xtal24mhz>, <&pclk>; - clock-names = "mclk", "apb_pclk"; - }; - kmi@6000 { - compatible = "arm,pl050", "arm,primecell"; - reg = <0x6000 0x1000>; - interrupt-parent = <&sic>; - interrupts = <3>; - clocks = <&xtal24mhz>, <&pclk>; - clock-names = "KMIREFCLK", "apb_pclk"; - }; - kmi@7000 { - compatible = "arm,pl050", "arm,primecell"; - reg = <0x7000 0x1000>; - interrupt-parent = <&sic>; - interrupts = <4>; - clocks = <&xtal24mhz>, <&pclk>; - clock-names = "KMIREFCLK", "apb_pclk"; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/versatile-pb.dts b/sys/gnu/dts/arm/versatile-pb.dts deleted file mode 100644 index 06a0fdf2402..00000000000 --- a/sys/gnu/dts/arm/versatile-pb.dts +++ /dev/null @@ -1,114 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "versatile-ab.dts" - -/ { - model = "ARM Versatile PB"; - compatible = "arm,versatile-pb"; - - amba { - /* The Versatile PB is using more SIC IRQ lines than the AB */ - sic: intc@10003000 { - clear-mask = <0xffffffff>; - /* - * Valid interrupt lines mask according to - * figure 3-30 page 3-74 of ARM DUI 0224B - */ - valid-mask = <0x7fe003ff>; - }; - - gpio2: gpio@101e6000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x101e6000 0x1000>; - interrupts = <8>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - gpio3: gpio@101e7000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x101e7000 0x1000>; - interrupts = <9>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - pci@10001000 { - compatible = "arm,versatile-pci"; - device_type = "pci"; - reg = <0x10001000 0x1000 - 0x41000000 0x10000 - 0x42000000 0x100000>; - bus-range = <0 0xff>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - - ranges = <0x01000000 0 0x00000000 0x43000000 0 0x00010000 /* downstream I/O */ - 0x02000000 0 0x50000000 0x50000000 0 0x10000000 /* non-prefetchable memory */ - 0x42000000 0 0x60000000 0x60000000 0 0x10000000>; /* prefetchable memory */ - - interrupt-map-mask = <0x1800 0 0 7>; - interrupt-map = <0x1800 0 0 1 &sic 28 - 0x1800 0 0 2 &sic 29 - 0x1800 0 0 3 &sic 30 - 0x1800 0 0 4 &sic 27 - - 0x1000 0 0 1 &sic 27 - 0x1000 0 0 2 &sic 28 - 0x1000 0 0 3 &sic 29 - 0x1000 0 0 4 &sic 30 - - 0x0800 0 0 1 &sic 30 - 0x0800 0 0 2 &sic 27 - 0x0800 0 0 3 &sic 28 - 0x0800 0 0 4 &sic 29 - - 0x0000 0 0 1 &sic 29 - 0x0000 0 0 2 &sic 30 - 0x0000 0 0 3 &sic 27 - 0x0000 0 0 4 &sic 28>; - }; - - fpga { - mmc@5000 { - /* - * Overrides the interrupt assignment from - * the Versatile AB board file. - */ - interrupts-extended = <&sic 22 &sic 23>; - }; - uart@9000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x9000 0x1000>; - interrupt-parent = <&sic>; - interrupts = <6>; - clocks = <&xtal24mhz>, <&pclk>; - clock-names = "uartclk", "apb_pclk"; - }; - sci@a000 { - compatible = "arm,primecell"; - reg = <0xa000 0x1000>; - interrupt-parent = <&sic>; - interrupts = <5>; - clocks = <&xtal24mhz>; - clock-names = "apb_pclk"; - }; - mmc@b000 { - compatible = "arm,pl180", "arm,primecell"; - reg = <0xb000 0x1000>; - interrupt-parent = <&sic>; - interrupts = <1>, <2>; - clocks = <&xtal24mhz>, <&pclk>; - clock-names = "mclk", "apb_pclk"; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/vexpress-v2m-rs1.dtsi b/sys/gnu/dts/arm/vexpress-v2m-rs1.dtsi deleted file mode 100644 index dfae90adbb7..00000000000 --- a/sys/gnu/dts/arm/vexpress-v2m-rs1.dtsi +++ /dev/null @@ -1,441 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * ARM Ltd. Versatile Express - * - * Motherboard Express uATX - * V2M-P1 - * - * HBI-0190D - * - * RS1 memory map ("ARM Cortex-A Series memory map" in the board's - * Technical Reference Manual) - * - * WARNING! The hardware described in this file is independent from the - * original variant (vexpress-v2m.dtsi), but there is a strong - * correspondence between the two configurations. - * - * TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT - * CHANGES TO vexpress-v2m.dtsi! - */ - -/ { - smb@8000000 { - motherboard { - model = "V2M-P1"; - arm,hbi = <0x190>; - arm,vexpress,site = <0>; - arm,v2m-memory-map = "rs1"; - compatible = "arm,vexpress,v2m-p1", "simple-bus"; - #address-cells = <2>; /* SMB chipselect number and offset */ - #size-cells = <1>; - #interrupt-cells = <1>; - ranges; - - nor_flash: flash@0,00000000 { - compatible = "arm,vexpress-flash", "cfi-flash"; - reg = <0 0x00000000 0x04000000>, - <4 0x00000000 0x04000000>; - bank-width = <4>; - partitions { - compatible = "arm,arm-firmware-suite"; - }; - }; - - psram@1,00000000 { - compatible = "arm,vexpress-psram", "mtd-ram"; - reg = <1 0x00000000 0x02000000>; - bank-width = <4>; - }; - - ethernet@2,02000000 { - compatible = "smsc,lan9118", "smsc,lan9115"; - reg = <2 0x02000000 0x10000>; - interrupts = <15>; - phy-mode = "mii"; - reg-io-width = <4>; - smsc,irq-active-high; - smsc,irq-push-pull; - vdd33a-supply = <&v2m_fixed_3v3>; - vddvario-supply = <&v2m_fixed_3v3>; - }; - - usb@2,03000000 { - compatible = "nxp,usb-isp1761"; - reg = <2 0x03000000 0x20000>; - interrupts = <16>; - port1-otg; - }; - - iofpga@3,00000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 3 0 0x200000>; - - v2m_sysreg: sysreg@10000 { - compatible = "arm,vexpress-sysreg"; - reg = <0x010000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x10000 0x1000>; - - v2m_led_gpios: gpio@8 { - compatible = "arm,vexpress-sysreg,sys_led"; - reg = <0x008 4>; - gpio-controller; - #gpio-cells = <2>; - }; - - v2m_mmc_gpios: gpio@48 { - compatible = "arm,vexpress-sysreg,sys_mci"; - reg = <0x048 4>; - gpio-controller; - #gpio-cells = <2>; - }; - - v2m_flash_gpios: gpio@4c { - compatible = "arm,vexpress-sysreg,sys_flash"; - reg = <0x04c 4>; - gpio-controller; - #gpio-cells = <2>; - }; - }; - - v2m_sysctl: sysctl@20000 { - compatible = "arm,sp810", "arm,primecell"; - reg = <0x020000 0x1000>; - clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>; - clock-names = "refclk", "timclk", "apb_pclk"; - #clock-cells = <1>; - clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3"; - assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>; - assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>; - }; - - /* PCI-E I2C bus */ - v2m_i2c_pcie: i2c@30000 { - compatible = "arm,versatile-i2c"; - reg = <0x030000 0x1000>; - - #address-cells = <1>; - #size-cells = <0>; - - pcie-switch@60 { - compatible = "idt,89hpes32h8"; - reg = <0x60>; - }; - }; - - aaci@40000 { - compatible = "arm,pl041", "arm,primecell"; - reg = <0x040000 0x1000>; - interrupts = <11>; - clocks = <&smbclk>; - clock-names = "apb_pclk"; - }; - - mmci@50000 { - compatible = "arm,pl180", "arm,primecell"; - reg = <0x050000 0x1000>; - interrupts = <9>, <10>; - cd-gpios = <&v2m_mmc_gpios 0 0>; - wp-gpios = <&v2m_mmc_gpios 1 0>; - max-frequency = <12000000>; - vmmc-supply = <&v2m_fixed_3v3>; - clocks = <&v2m_clk24mhz>, <&smbclk>; - clock-names = "mclk", "apb_pclk"; - }; - - kmi@60000 { - compatible = "arm,pl050", "arm,primecell"; - reg = <0x060000 0x1000>; - interrupts = <12>; - clocks = <&v2m_clk24mhz>, <&smbclk>; - clock-names = "KMIREFCLK", "apb_pclk"; - }; - - kmi@70000 { - compatible = "arm,pl050", "arm,primecell"; - reg = <0x070000 0x1000>; - interrupts = <13>; - clocks = <&v2m_clk24mhz>, <&smbclk>; - clock-names = "KMIREFCLK", "apb_pclk"; - }; - - v2m_serial0: uart@90000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x090000 0x1000>; - interrupts = <5>; - clocks = <&v2m_oscclk2>, <&smbclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - v2m_serial1: uart@a0000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0a0000 0x1000>; - interrupts = <6>; - clocks = <&v2m_oscclk2>, <&smbclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - v2m_serial2: uart@b0000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0b0000 0x1000>; - interrupts = <7>; - clocks = <&v2m_oscclk2>, <&smbclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - v2m_serial3: uart@c0000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0c0000 0x1000>; - interrupts = <8>; - clocks = <&v2m_oscclk2>, <&smbclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - wdt@f0000 { - compatible = "arm,sp805", "arm,primecell"; - reg = <0x0f0000 0x1000>; - interrupts = <0>; - clocks = <&v2m_refclk32khz>, <&smbclk>; - clock-names = "wdogclk", "apb_pclk"; - }; - - v2m_timer01: timer@110000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x110000 0x1000>; - interrupts = <2>; - clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&smbclk>; - clock-names = "timclken1", "timclken2", "apb_pclk"; - }; - - v2m_timer23: timer@120000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x120000 0x1000>; - interrupts = <3>; - clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&smbclk>; - clock-names = "timclken1", "timclken2", "apb_pclk"; - }; - - /* DVI I2C bus */ - v2m_i2c_dvi: i2c@160000 { - compatible = "arm,versatile-i2c"; - reg = <0x160000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - - dvi-transmitter@39 { - compatible = "sil,sii9022-tpi", "sil,sii9022"; - reg = <0x39>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dvi_bridge_in: endpoint { - remote-endpoint = <&clcd_pads>; - }; - }; - }; - }; - - dvi-transmitter@60 { - compatible = "sil,sii9022-cpi", "sil,sii9022"; - reg = <0x60>; - }; - }; - - rtc@170000 { - compatible = "arm,pl031", "arm,primecell"; - reg = <0x170000 0x1000>; - interrupts = <4>; - clocks = <&smbclk>; - clock-names = "apb_pclk"; - }; - - compact-flash@1a0000 { - compatible = "arm,vexpress-cf", "ata-generic"; - reg = <0x1a0000 0x100 - 0x1a0100 0xf00>; - reg-shift = <2>; - }; - - clcd@1f0000 { - compatible = "arm,pl111", "arm,primecell"; - reg = <0x1f0000 0x1000>; - interrupt-names = "combined"; - interrupts = <14>; - clocks = <&v2m_oscclk1>, <&smbclk>; - clock-names = "clcdclk", "apb_pclk"; - /* 800x600 16bpp @36MHz works fine */ - max-memory-bandwidth = <54000000>; - memory-region = <&vram>; - - port { - clcd_pads: endpoint { - remote-endpoint = <&dvi_bridge_in>; - arm,pl11x,tft-r0g0b0-pads = <0 8 16>; - }; - }; - }; - }; - - v2m_fixed_3v3: fixed-regulator-0 { - compatible = "regulator-fixed"; - regulator-name = "3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - v2m_clk24mhz: clk24mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "v2m:clk24mhz"; - }; - - v2m_refclk1mhz: refclk1mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <1000000>; - clock-output-names = "v2m:refclk1mhz"; - }; - - v2m_refclk32khz: refclk32khz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "v2m:refclk32khz"; - }; - - leds { - compatible = "gpio-leds"; - - user1 { - label = "v2m:green:user1"; - gpios = <&v2m_led_gpios 0 0>; - linux,default-trigger = "heartbeat"; - }; - - user2 { - label = "v2m:green:user2"; - gpios = <&v2m_led_gpios 1 0>; - linux,default-trigger = "mmc0"; - }; - - user3 { - label = "v2m:green:user3"; - gpios = <&v2m_led_gpios 2 0>; - linux,default-trigger = "cpu0"; - }; - - user4 { - label = "v2m:green:user4"; - gpios = <&v2m_led_gpios 3 0>; - linux,default-trigger = "cpu1"; - }; - - user5 { - label = "v2m:green:user5"; - gpios = <&v2m_led_gpios 4 0>; - linux,default-trigger = "cpu2"; - }; - - user6 { - label = "v2m:green:user6"; - gpios = <&v2m_led_gpios 5 0>; - linux,default-trigger = "cpu3"; - }; - - user7 { - label = "v2m:green:user7"; - gpios = <&v2m_led_gpios 6 0>; - linux,default-trigger = "cpu4"; - }; - - user8 { - label = "v2m:green:user8"; - gpios = <&v2m_led_gpios 7 0>; - linux,default-trigger = "cpu5"; - }; - }; - - mcc { - compatible = "arm,vexpress,config-bus"; - arm,vexpress,config-bridge = <&v2m_sysreg>; - - oscclk0 { - /* MCC static memory clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 0>; - freq-range = <25000000 60000000>; - #clock-cells = <0>; - clock-output-names = "v2m:oscclk0"; - }; - - v2m_oscclk1: oscclk1 { - /* CLCD clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 1>; - freq-range = <23750000 65000000>; - #clock-cells = <0>; - clock-output-names = "v2m:oscclk1"; - }; - - v2m_oscclk2: oscclk2 { - /* IO FPGA peripheral clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 2>; - freq-range = <24000000 24000000>; - #clock-cells = <0>; - clock-output-names = "v2m:oscclk2"; - }; - - volt-vio { - /* Logic level voltage */ - compatible = "arm,vexpress-volt"; - arm,vexpress-sysreg,func = <2 0>; - regulator-name = "VIO"; - regulator-always-on; - label = "VIO"; - }; - - temp-mcc { - /* MCC internal operating temperature */ - compatible = "arm,vexpress-temp"; - arm,vexpress-sysreg,func = <4 0>; - label = "MCC"; - }; - - reset { - compatible = "arm,vexpress-reset"; - arm,vexpress-sysreg,func = <5 0>; - }; - - muxfpga { - compatible = "arm,vexpress-muxfpga"; - arm,vexpress-sysreg,func = <7 0>; - }; - - shutdown { - compatible = "arm,vexpress-shutdown"; - arm,vexpress-sysreg,func = <8 0>; - }; - - reboot { - compatible = "arm,vexpress-reboot"; - arm,vexpress-sysreg,func = <9 0>; - }; - - dvimode { - compatible = "arm,vexpress-dvimode"; - arm,vexpress-sysreg,func = <11 0>; - }; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/vexpress-v2m.dtsi b/sys/gnu/dts/arm/vexpress-v2m.dtsi deleted file mode 100644 index 2e29d779049..00000000000 --- a/sys/gnu/dts/arm/vexpress-v2m.dtsi +++ /dev/null @@ -1,454 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * ARM Ltd. Versatile Express - * - * Motherboard Express uATX - * V2M-P1 - * - * HBI-0190D - * - * Original memory map ("Legacy memory map" in the board's - * Technical Reference Manual) - * - * WARNING! The hardware described in this file is independent from the - * RS1 variant (vexpress-v2m-rs1.dtsi), but there is a strong - * correspondence between the two configurations. - * - * TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT - * CHANGES TO vexpress-v2m-rs1.dtsi! - */ - -/ { - smb@4000000 { - motherboard { - model = "V2M-P1"; - arm,hbi = <0x190>; - arm,vexpress,site = <0>; - compatible = "arm,vexpress,v2m-p1", "simple-bus"; - #address-cells = <2>; /* SMB chipselect number and offset */ - #size-cells = <1>; - #interrupt-cells = <1>; - ranges; - - flash@0,00000000 { - compatible = "arm,vexpress-flash", "cfi-flash"; - reg = <0 0x00000000 0x04000000>, - <1 0x00000000 0x04000000>; - bank-width = <4>; - partitions { - compatible = "arm,arm-firmware-suite"; - }; - }; - - psram@2,00000000 { - compatible = "arm,vexpress-psram", "mtd-ram"; - reg = <2 0x00000000 0x02000000>; - bank-width = <4>; - }; - - ethernet@3,02000000 { - compatible = "smsc,lan9118", "smsc,lan9115"; - reg = <3 0x02000000 0x10000>; - interrupts = <15>; - phy-mode = "mii"; - reg-io-width = <4>; - smsc,irq-active-high; - smsc,irq-push-pull; - vdd33a-supply = <&v2m_fixed_3v3>; - vddvario-supply = <&v2m_fixed_3v3>; - }; - - usb@3,03000000 { - compatible = "nxp,usb-isp1761"; - reg = <3 0x03000000 0x20000>; - interrupts = <16>; - port1-otg; - }; - - iofpga@7,00000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 7 0 0x20000>; - - v2m_sysreg: sysreg@0 { - compatible = "arm,vexpress-sysreg"; - reg = <0x00000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x1000>; - - v2m_led_gpios: gpio@8 { - compatible = "arm,vexpress-sysreg,sys_led"; - reg = <0x008 4>; - gpio-controller; - #gpio-cells = <2>; - }; - - v2m_mmc_gpios: gpio@48 { - compatible = "arm,vexpress-sysreg,sys_mci"; - reg = <0x048 4>; - gpio-controller; - #gpio-cells = <2>; - }; - - v2m_flash_gpios: gpio@4c { - compatible = "arm,vexpress-sysreg,sys_flash"; - reg = <0x04c 4>; - gpio-controller; - #gpio-cells = <2>; - }; - }; - - v2m_sysctl: sysctl@1000 { - compatible = "arm,sp810", "arm,primecell"; - reg = <0x01000 0x1000>; - clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>; - clock-names = "refclk", "timclk", "apb_pclk"; - #clock-cells = <1>; - clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3"; - assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>; - assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>; - }; - - /* PCI-E I2C bus */ - v2m_i2c_pcie: i2c@2000 { - compatible = "arm,versatile-i2c"; - reg = <0x02000 0x1000>; - - #address-cells = <1>; - #size-cells = <0>; - - pcie-switch@60 { - compatible = "idt,89hpes32h8"; - reg = <0x60>; - }; - }; - - aaci@4000 { - compatible = "arm,pl041", "arm,primecell"; - reg = <0x04000 0x1000>; - interrupts = <11>; - clocks = <&smbclk>; - clock-names = "apb_pclk"; - }; - - mmci@5000 { - compatible = "arm,pl180", "arm,primecell"; - reg = <0x05000 0x1000>; - interrupts = <9>, <10>; - cd-gpios = <&v2m_mmc_gpios 0 0>; - wp-gpios = <&v2m_mmc_gpios 1 0>; - max-frequency = <12000000>; - vmmc-supply = <&v2m_fixed_3v3>; - clocks = <&v2m_clk24mhz>, <&smbclk>; - clock-names = "mclk", "apb_pclk"; - }; - - kmi@6000 { - compatible = "arm,pl050", "arm,primecell"; - reg = <0x06000 0x1000>; - interrupts = <12>; - clocks = <&v2m_clk24mhz>, <&smbclk>; - clock-names = "KMIREFCLK", "apb_pclk"; - }; - - kmi@7000 { - compatible = "arm,pl050", "arm,primecell"; - reg = <0x07000 0x1000>; - interrupts = <13>; - clocks = <&v2m_clk24mhz>, <&smbclk>; - clock-names = "KMIREFCLK", "apb_pclk"; - }; - - v2m_serial0: uart@9000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x09000 0x1000>; - interrupts = <5>; - clocks = <&v2m_oscclk2>, <&smbclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - v2m_serial1: uart@a000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0a000 0x1000>; - interrupts = <6>; - clocks = <&v2m_oscclk2>, <&smbclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - v2m_serial2: uart@b000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0b000 0x1000>; - interrupts = <7>; - clocks = <&v2m_oscclk2>, <&smbclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - v2m_serial3: uart@c000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0c000 0x1000>; - interrupts = <8>; - clocks = <&v2m_oscclk2>, <&smbclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - wdt@f000 { - compatible = "arm,sp805", "arm,primecell"; - reg = <0x0f000 0x1000>; - interrupts = <0>; - clocks = <&v2m_refclk32khz>, <&smbclk>; - clock-names = "wdogclk", "apb_pclk"; - }; - - v2m_timer01: timer@11000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x11000 0x1000>; - interrupts = <2>; - clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&smbclk>; - clock-names = "timclken1", "timclken2", "apb_pclk"; - }; - - v2m_timer23: timer@12000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x12000 0x1000>; - interrupts = <3>; - clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&smbclk>; - clock-names = "timclken1", "timclken2", "apb_pclk"; - }; - - /* DVI I2C bus */ - v2m_i2c_dvi: i2c@16000 { - compatible = "arm,versatile-i2c"; - reg = <0x16000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - - dvi-transmitter@39 { - compatible = "sil,sii9022-tpi", "sil,sii9022"; - reg = <0x39>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - /* - * Both the core tile and the motherboard routes their output - * pads to this transmitter. The motherboard system controller - * can select one of them as input using a mux register in - * "arm,vexpress-muxfpga". The Vexpress with the CA9 core tile is - * the only platform with this specific set-up. - */ - port@0 { - reg = <0>; - dvi_bridge_in_ct: endpoint { - remote-endpoint = <&clcd_pads_ct>; - }; - }; - port@1 { - reg = <1>; - dvi_bridge_in_mb: endpoint { - remote-endpoint = <&clcd_pads_mb>; - }; - }; - }; - }; - - dvi-transmitter@60 { - compatible = "sil,sii9022-cpi", "sil,sii9022"; - reg = <0x60>; - }; - }; - - rtc@17000 { - compatible = "arm,pl031", "arm,primecell"; - reg = <0x17000 0x1000>; - interrupts = <4>; - clocks = <&smbclk>; - clock-names = "apb_pclk"; - }; - - compact-flash@1a000 { - compatible = "arm,vexpress-cf", "ata-generic"; - reg = <0x1a000 0x100 - 0x1a100 0xf00>; - reg-shift = <2>; - }; - - - clcd@1f000 { - compatible = "arm,pl111", "arm,primecell"; - reg = <0x1f000 0x1000>; - interrupt-names = "combined"; - interrupts = <14>; - clocks = <&v2m_oscclk1>, <&smbclk>; - clock-names = "clcdclk", "apb_pclk"; - /* 800x600 16bpp @36MHz works fine */ - max-memory-bandwidth = <54000000>; - memory-region = <&vram>; - - port { - clcd_pads_mb: endpoint { - remote-endpoint = <&dvi_bridge_in_mb>; - arm,pl11x,tft-r0g0b0-pads = <0 8 16>; - }; - }; - }; - }; - - v2m_fixed_3v3: fixed-regulator-0 { - compatible = "regulator-fixed"; - regulator-name = "3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - v2m_clk24mhz: clk24mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "v2m:clk24mhz"; - }; - - v2m_refclk1mhz: refclk1mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <1000000>; - clock-output-names = "v2m:refclk1mhz"; - }; - - v2m_refclk32khz: refclk32khz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "v2m:refclk32khz"; - }; - - leds { - compatible = "gpio-leds"; - - user1 { - label = "v2m:green:user1"; - gpios = <&v2m_led_gpios 0 0>; - linux,default-trigger = "heartbeat"; - }; - - user2 { - label = "v2m:green:user2"; - gpios = <&v2m_led_gpios 1 0>; - linux,default-trigger = "mmc0"; - }; - - user3 { - label = "v2m:green:user3"; - gpios = <&v2m_led_gpios 2 0>; - linux,default-trigger = "cpu0"; - }; - - user4 { - label = "v2m:green:user4"; - gpios = <&v2m_led_gpios 3 0>; - linux,default-trigger = "cpu1"; - }; - - user5 { - label = "v2m:green:user5"; - gpios = <&v2m_led_gpios 4 0>; - linux,default-trigger = "cpu2"; - }; - - user6 { - label = "v2m:green:user6"; - gpios = <&v2m_led_gpios 5 0>; - linux,default-trigger = "cpu3"; - }; - - user7 { - label = "v2m:green:user7"; - gpios = <&v2m_led_gpios 6 0>; - linux,default-trigger = "cpu4"; - }; - - user8 { - label = "v2m:green:user8"; - gpios = <&v2m_led_gpios 7 0>; - linux,default-trigger = "cpu5"; - }; - }; - - mcc { - compatible = "arm,vexpress,config-bus"; - arm,vexpress,config-bridge = <&v2m_sysreg>; - - oscclk0 { - /* MCC static memory clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 0>; - freq-range = <25000000 60000000>; - #clock-cells = <0>; - clock-output-names = "v2m:oscclk0"; - }; - - v2m_oscclk1: oscclk1 { - /* CLCD clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 1>; - freq-range = <23750000 65000000>; - #clock-cells = <0>; - clock-output-names = "v2m:oscclk1"; - }; - - v2m_oscclk2: oscclk2 { - /* IO FPGA peripheral clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 2>; - freq-range = <24000000 24000000>; - #clock-cells = <0>; - clock-output-names = "v2m:oscclk2"; - }; - - volt-vio { - /* Logic level voltage */ - compatible = "arm,vexpress-volt"; - arm,vexpress-sysreg,func = <2 0>; - regulator-name = "VIO"; - regulator-always-on; - label = "VIO"; - }; - - temp-mcc { - /* MCC internal operating temperature */ - compatible = "arm,vexpress-temp"; - arm,vexpress-sysreg,func = <4 0>; - label = "MCC"; - }; - - reset { - compatible = "arm,vexpress-reset"; - arm,vexpress-sysreg,func = <5 0>; - }; - - muxfpga { - compatible = "arm,vexpress-muxfpga"; - arm,vexpress-sysreg,func = <7 0>; - }; - - shutdown { - compatible = "arm,vexpress-shutdown"; - arm,vexpress-sysreg,func = <8 0>; - }; - - reboot { - compatible = "arm,vexpress-reboot"; - arm,vexpress-sysreg,func = <9 0>; - }; - - dvimode { - compatible = "arm,vexpress-dvimode"; - arm,vexpress-sysreg,func = <11 0>; - }; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/vexpress-v2p-ca15-tc1.dts b/sys/gnu/dts/arm/vexpress-v2p-ca15-tc1.dts deleted file mode 100644 index 0dc4277d5f8..00000000000 --- a/sys/gnu/dts/arm/vexpress-v2p-ca15-tc1.dts +++ /dev/null @@ -1,310 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * ARM Ltd. Versatile Express - * - * CoreTile Express A15x2 (version with Test Chip 1) - * Cortex-A15 MPCore (V2P-CA15) - * - * HBI-0237A - */ - -/dts-v1/; -#include "vexpress-v2m-rs1.dtsi" - -/ { - model = "V2P-CA15"; - arm,hbi = <0x237>; - arm,vexpress,site = <0xf>; - compatible = "arm,vexpress,v2p-ca15,tc1", "arm,vexpress,v2p-ca15", "arm,vexpress"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - chosen { }; - - aliases { - serial0 = &v2m_serial0; - serial1 = &v2m_serial1; - serial2 = &v2m_serial2; - serial3 = &v2m_serial3; - i2c0 = &v2m_i2c_dvi; - i2c1 = &v2m_i2c_pcie; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <1>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0 0x80000000 0 0x40000000>; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - /* Chipselect 2 is physically at 0x18000000 */ - vram: vram@18000000 { - /* 8 MB of designated video RAM */ - compatible = "shared-dma-pool"; - reg = <0 0x18000000 0 0x00800000>; - no-map; - }; - }; - - hdlcd@2b000000 { - compatible = "arm,hdlcd"; - reg = <0 0x2b000000 0 0x1000>; - interrupts = <0 85 4>; - clocks = <&hdlcd_clk>; - clock-names = "pxlclk"; - }; - - memory-controller@2b0a0000 { - compatible = "arm,pl341", "arm,primecell"; - reg = <0 0x2b0a0000 0 0x1000>; - clocks = <&sys_pll>; - clock-names = "apb_pclk"; - }; - - wdt@2b060000 { - compatible = "arm,sp805", "arm,primecell"; - status = "disabled"; - reg = <0 0x2b060000 0 0x1000>; - interrupts = <0 98 4>; - clocks = <&sys_pll>; - clock-names = "apb_pclk"; - }; - - gic: interrupt-controller@2c001000 { - compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0 0x2c001000 0 0x1000>, - <0 0x2c002000 0 0x2000>, - <0 0x2c004000 0 0x2000>, - <0 0x2c006000 0 0x2000>; - interrupts = <1 9 0xf04>; - }; - - memory-controller@7ffd0000 { - compatible = "arm,pl354", "arm,primecell"; - reg = <0 0x7ffd0000 0 0x1000>; - interrupts = <0 86 4>, - <0 87 4>; - clocks = <&sys_pll>; - clock-names = "apb_pclk"; - }; - - dma@7ffb0000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0 0x7ffb0000 0 0x1000>; - interrupts = <0 92 4>, - <0 88 4>, - <0 89 4>, - <0 90 4>, - <0 91 4>; - clocks = <&sys_pll>; - clock-names = "apb_pclk"; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = <1 13 0xf08>, - <1 14 0xf08>, - <1 11 0xf08>, - <1 10 0xf08>; - }; - - pmu { - compatible = "arm,cortex-a15-pmu"; - interrupts = <0 68 4>, - <0 69 4>; - }; - - dcc { - compatible = "arm,vexpress,config-bus"; - arm,vexpress,config-bridge = <&v2m_sysreg>; - - oscclk0 { - /* CPU PLL reference clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 0>; - freq-range = <50000000 60000000>; - #clock-cells = <0>; - clock-output-names = "oscclk0"; - }; - - oscclk4 { - /* Multiplexed AXI master clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 4>; - freq-range = <20000000 40000000>; - #clock-cells = <0>; - clock-output-names = "oscclk4"; - }; - - hdlcd_clk: oscclk5 { - /* HDLCD PLL reference clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 5>; - freq-range = <23750000 165000000>; - #clock-cells = <0>; - clock-output-names = "oscclk5"; - }; - - smbclk: oscclk6 { - /* SMB clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 6>; - freq-range = <20000000 50000000>; - #clock-cells = <0>; - clock-output-names = "oscclk6"; - }; - - sys_pll: oscclk7 { - /* SYS PLL reference clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 7>; - freq-range = <20000000 60000000>; - #clock-cells = <0>; - clock-output-names = "oscclk7"; - }; - - oscclk8 { - /* DDR2 PLL reference clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 8>; - freq-range = <40000000 40000000>; - #clock-cells = <0>; - clock-output-names = "oscclk8"; - }; - - volt-cores { - /* CPU core voltage */ - compatible = "arm,vexpress-volt"; - arm,vexpress-sysreg,func = <2 0>; - regulator-name = "Cores"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1050000>; - regulator-always-on; - label = "Cores"; - }; - - amp-cores { - /* Total current for the two cores */ - compatible = "arm,vexpress-amp"; - arm,vexpress-sysreg,func = <3 0>; - label = "Cores"; - }; - - temp-dcc { - /* DCC internal temperature */ - compatible = "arm,vexpress-temp"; - arm,vexpress-sysreg,func = <4 0>; - label = "DCC"; - }; - - power-cores { - /* Total power */ - compatible = "arm,vexpress-power"; - arm,vexpress-sysreg,func = <12 0>; - label = "Cores"; - }; - - energy { - /* Total energy */ - compatible = "arm,vexpress-energy"; - arm,vexpress-sysreg,func = <13 0>; - label = "Cores"; - }; - }; - - smb@8000000 { - compatible = "simple-bus"; - - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0 0x08000000 0x04000000>, - <1 0 0 0x14000000 0x04000000>, - <2 0 0 0x18000000 0x04000000>, - <3 0 0 0x1c000000 0x04000000>, - <4 0 0 0x0c000000 0x04000000>, - <5 0 0 0x10000000 0x04000000>; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 63>; - interrupt-map = <0 0 0 &gic 0 0 4>, - <0 0 1 &gic 0 1 4>, - <0 0 2 &gic 0 2 4>, - <0 0 3 &gic 0 3 4>, - <0 0 4 &gic 0 4 4>, - <0 0 5 &gic 0 5 4>, - <0 0 6 &gic 0 6 4>, - <0 0 7 &gic 0 7 4>, - <0 0 8 &gic 0 8 4>, - <0 0 9 &gic 0 9 4>, - <0 0 10 &gic 0 10 4>, - <0 0 11 &gic 0 11 4>, - <0 0 12 &gic 0 12 4>, - <0 0 13 &gic 0 13 4>, - <0 0 14 &gic 0 14 4>, - <0 0 15 &gic 0 15 4>, - <0 0 16 &gic 0 16 4>, - <0 0 17 &gic 0 17 4>, - <0 0 18 &gic 0 18 4>, - <0 0 19 &gic 0 19 4>, - <0 0 20 &gic 0 20 4>, - <0 0 21 &gic 0 21 4>, - <0 0 22 &gic 0 22 4>, - <0 0 23 &gic 0 23 4>, - <0 0 24 &gic 0 24 4>, - <0 0 25 &gic 0 25 4>, - <0 0 26 &gic 0 26 4>, - <0 0 27 &gic 0 27 4>, - <0 0 28 &gic 0 28 4>, - <0 0 29 &gic 0 29 4>, - <0 0 30 &gic 0 30 4>, - <0 0 31 &gic 0 31 4>, - <0 0 32 &gic 0 32 4>, - <0 0 33 &gic 0 33 4>, - <0 0 34 &gic 0 34 4>, - <0 0 35 &gic 0 35 4>, - <0 0 36 &gic 0 36 4>, - <0 0 37 &gic 0 37 4>, - <0 0 38 &gic 0 38 4>, - <0 0 39 &gic 0 39 4>, - <0 0 40 &gic 0 40 4>, - <0 0 41 &gic 0 41 4>, - <0 0 42 &gic 0 42 4>; - }; - - site2: hsb@40000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x40000000 0x3fef0000>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 3>; - interrupt-map = <0 0 &gic 0 36 4>, - <0 1 &gic 0 37 4>, - <0 2 &gic 0 38 4>, - <0 3 &gic 0 39 4>; - }; -}; diff --git a/sys/gnu/dts/arm/vexpress-v2p-ca15_a7.dts b/sys/gnu/dts/arm/vexpress-v2p-ca15_a7.dts deleted file mode 100644 index 1de0a658adf..00000000000 --- a/sys/gnu/dts/arm/vexpress-v2p-ca15_a7.dts +++ /dev/null @@ -1,691 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * ARM Ltd. Versatile Express - * - * CoreTile Express A15x2 A7x3 - * Cortex-A15_A7 MPCore (V2P-CA15_A7) - * - * HBI-0249A - */ - -/dts-v1/; -#include "vexpress-v2m-rs1.dtsi" - -/ { - model = "V2P-CA15_CA7"; - arm,hbi = <0x249>; - arm,vexpress,site = <0xf>; - compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - chosen { }; - - aliases { - serial0 = &v2m_serial0; - serial1 = &v2m_serial1; - serial2 = &v2m_serial2; - serial3 = &v2m_serial3; - i2c0 = &v2m_i2c_dvi; - i2c1 = &v2m_i2c_pcie; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0>; - cci-control-port = <&cci_control1>; - cpu-idle-states = <&CLUSTER_SLEEP_BIG>; - capacity-dmips-mhz = <1024>; - dynamic-power-coefficient = <990>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <1>; - cci-control-port = <&cci_control1>; - cpu-idle-states = <&CLUSTER_SLEEP_BIG>; - capacity-dmips-mhz = <1024>; - dynamic-power-coefficient = <990>; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x100>; - cci-control-port = <&cci_control2>; - cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>; - capacity-dmips-mhz = <516>; - dynamic-power-coefficient = <133>; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x101>; - cci-control-port = <&cci_control2>; - cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>; - capacity-dmips-mhz = <516>; - dynamic-power-coefficient = <133>; - }; - - cpu4: cpu@4 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x102>; - cci-control-port = <&cci_control2>; - cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>; - capacity-dmips-mhz = <516>; - dynamic-power-coefficient = <133>; - }; - - idle-states { - CLUSTER_SLEEP_BIG: cluster-sleep-big { - compatible = "arm,idle-state"; - local-timer-stop; - entry-latency-us = <1000>; - exit-latency-us = <700>; - min-residency-us = <2000>; - }; - - CLUSTER_SLEEP_LITTLE: cluster-sleep-little { - compatible = "arm,idle-state"; - local-timer-stop; - entry-latency-us = <1000>; - exit-latency-us = <500>; - min-residency-us = <2500>; - }; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0 0x80000000 0 0x40000000>; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - /* Chipselect 2 is physically at 0x18000000 */ - vram: vram@18000000 { - /* 8 MB of designated video RAM */ - compatible = "shared-dma-pool"; - reg = <0 0x18000000 0 0x00800000>; - no-map; - }; - }; - - wdt@2a490000 { - compatible = "arm,sp805", "arm,primecell"; - reg = <0 0x2a490000 0 0x1000>; - interrupts = <0 98 4>; - clocks = <&oscclk6a>, <&oscclk6a>; - clock-names = "wdogclk", "apb_pclk"; - }; - - hdlcd@2b000000 { - compatible = "arm,hdlcd"; - reg = <0 0x2b000000 0 0x1000>; - interrupts = <0 85 4>; - clocks = <&hdlcd_clk>; - clock-names = "pxlclk"; - }; - - memory-controller@2b0a0000 { - compatible = "arm,pl341", "arm,primecell"; - reg = <0 0x2b0a0000 0 0x1000>; - clocks = <&oscclk6a>; - clock-names = "apb_pclk"; - }; - - gic: interrupt-controller@2c001000 { - compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0 0x2c001000 0 0x1000>, - <0 0x2c002000 0 0x2000>, - <0 0x2c004000 0 0x2000>, - <0 0x2c006000 0 0x2000>; - interrupts = <1 9 0xf04>; - }; - - cci@2c090000 { - compatible = "arm,cci-400"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0 0x2c090000 0 0x1000>; - ranges = <0x0 0x0 0x2c090000 0x10000>; - - cci_control1: slave-if@4000 { - compatible = "arm,cci-400-ctrl-if"; - interface-type = "ace"; - reg = <0x4000 0x1000>; - }; - - cci_control2: slave-if@5000 { - compatible = "arm,cci-400-ctrl-if"; - interface-type = "ace"; - reg = <0x5000 0x1000>; - }; - - pmu@9000 { - compatible = "arm,cci-400-pmu,r0"; - reg = <0x9000 0x5000>; - interrupts = <0 105 4>, - <0 101 4>, - <0 102 4>, - <0 103 4>, - <0 104 4>; - }; - }; - - memory-controller@7ffd0000 { - compatible = "arm,pl354", "arm,primecell"; - reg = <0 0x7ffd0000 0 0x1000>; - interrupts = <0 86 4>, - <0 87 4>; - clocks = <&oscclk6a>; - clock-names = "apb_pclk"; - }; - - dma@7ff00000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0 0x7ff00000 0 0x1000>; - interrupts = <0 92 4>, - <0 88 4>, - <0 89 4>, - <0 90 4>, - <0 91 4>; - clocks = <&oscclk6a>; - clock-names = "apb_pclk"; - }; - - scc@7fff0000 { - compatible = "arm,vexpress-scc,v2p-ca15_a7", "arm,vexpress-scc"; - reg = <0 0x7fff0000 0 0x1000>; - interrupts = <0 95 4>; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = <1 13 0xf08>, - <1 14 0xf08>, - <1 11 0xf08>, - <1 10 0xf08>; - }; - - pmu-a15 { - compatible = "arm,cortex-a15-pmu"; - interrupts = <0 68 4>, - <0 69 4>; - interrupt-affinity = <&cpu0>, - <&cpu1>; - }; - - pmu-a7 { - compatible = "arm,cortex-a7-pmu"; - interrupts = <0 128 4>, - <0 129 4>, - <0 130 4>; - interrupt-affinity = <&cpu2>, - <&cpu3>, - <&cpu4>; - }; - - oscclk6a: oscclk6a { - /* Reference 24MHz clock */ - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "oscclk6a"; - }; - - dcc { - compatible = "arm,vexpress,config-bus"; - arm,vexpress,config-bridge = <&v2m_sysreg>; - - oscclk0 { - /* A15 PLL 0 reference clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 0>; - freq-range = <17000000 50000000>; - #clock-cells = <0>; - clock-output-names = "oscclk0"; - }; - - oscclk1 { - /* A15 PLL 1 reference clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 1>; - freq-range = <17000000 50000000>; - #clock-cells = <0>; - clock-output-names = "oscclk1"; - }; - - oscclk2 { - /* A7 PLL 0 reference clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 2>; - freq-range = <17000000 50000000>; - #clock-cells = <0>; - clock-output-names = "oscclk2"; - }; - - oscclk3 { - /* A7 PLL 1 reference clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 3>; - freq-range = <17000000 50000000>; - #clock-cells = <0>; - clock-output-names = "oscclk3"; - }; - - oscclk4 { - /* External AXI master clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 4>; - freq-range = <20000000 40000000>; - #clock-cells = <0>; - clock-output-names = "oscclk4"; - }; - - hdlcd_clk: oscclk5 { - /* HDLCD PLL reference clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 5>; - freq-range = <23750000 165000000>; - #clock-cells = <0>; - clock-output-names = "oscclk5"; - }; - - smbclk: oscclk6 { - /* Static memory controller clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 6>; - freq-range = <20000000 40000000>; - #clock-cells = <0>; - clock-output-names = "oscclk6"; - }; - - oscclk7 { - /* SYS PLL reference clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 7>; - freq-range = <17000000 50000000>; - #clock-cells = <0>; - clock-output-names = "oscclk7"; - }; - - oscclk8 { - /* DDR2 PLL reference clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 8>; - freq-range = <20000000 50000000>; - #clock-cells = <0>; - clock-output-names = "oscclk8"; - }; - - volt-a15 { - /* A15 CPU core voltage */ - compatible = "arm,vexpress-volt"; - arm,vexpress-sysreg,func = <2 0>; - regulator-name = "A15 Vcore"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1050000>; - regulator-always-on; - label = "A15 Vcore"; - }; - - volt-a7 { - /* A7 CPU core voltage */ - compatible = "arm,vexpress-volt"; - arm,vexpress-sysreg,func = <2 1>; - regulator-name = "A7 Vcore"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1050000>; - regulator-always-on; - label = "A7 Vcore"; - }; - - amp-a15 { - /* Total current for the two A15 cores */ - compatible = "arm,vexpress-amp"; - arm,vexpress-sysreg,func = <3 0>; - label = "A15 Icore"; - }; - - amp-a7 { - /* Total current for the three A7 cores */ - compatible = "arm,vexpress-amp"; - arm,vexpress-sysreg,func = <3 1>; - label = "A7 Icore"; - }; - - temp-dcc { - /* DCC internal temperature */ - compatible = "arm,vexpress-temp"; - arm,vexpress-sysreg,func = <4 0>; - label = "DCC"; - }; - - power-a15 { - /* Total power for the two A15 cores */ - compatible = "arm,vexpress-power"; - arm,vexpress-sysreg,func = <12 0>; - label = "A15 Pcore"; - }; - - power-a7 { - /* Total power for the three A7 cores */ - compatible = "arm,vexpress-power"; - arm,vexpress-sysreg,func = <12 1>; - label = "A7 Pcore"; - }; - - energy-a15 { - /* Total energy for the two A15 cores */ - compatible = "arm,vexpress-energy"; - arm,vexpress-sysreg,func = <13 0>, <13 1>; - label = "A15 Jcore"; - }; - - energy-a7 { - /* Total energy for the three A7 cores */ - compatible = "arm,vexpress-energy"; - arm,vexpress-sysreg,func = <13 2>, <13 3>; - label = "A7 Jcore"; - }; - }; - - etb@20010000 { - compatible = "arm,coresight-etb10", "arm,primecell"; - reg = <0 0x20010000 0 0x1000>; - - clocks = <&oscclk6a>; - clock-names = "apb_pclk"; - in-ports { - port { - etb_in_port: endpoint { - remote-endpoint = <&replicator_out_port0>; - }; - }; - }; - }; - - tpiu@20030000 { - compatible = "arm,coresight-tpiu", "arm,primecell"; - reg = <0 0x20030000 0 0x1000>; - - clocks = <&oscclk6a>; - clock-names = "apb_pclk"; - in-ports { - port { - tpiu_in_port: endpoint { - remote-endpoint = <&replicator_out_port1>; - }; - }; - }; - }; - - replicator { - /* non-configurable replicators don't show up on the - * AMBA bus. As such no need to add "arm,primecell". - */ - compatible = "arm,coresight-static-replicator"; - - out-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - replicator_out_port0: endpoint { - remote-endpoint = <&etb_in_port>; - }; - }; - - port@1 { - reg = <1>; - replicator_out_port1: endpoint { - remote-endpoint = <&tpiu_in_port>; - }; - }; - }; - - in-ports { - port { - replicator_in_port0: endpoint { - remote-endpoint = <&funnel_out_port0>; - }; - }; - }; - }; - - funnel@20040000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0x20040000 0 0x1000>; - - clocks = <&oscclk6a>; - clock-names = "apb_pclk"; - out-ports { - port { - funnel_out_port0: endpoint { - remote-endpoint = - <&replicator_in_port0>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - funnel_in_port0: endpoint { - remote-endpoint = <&ptm0_out_port>; - }; - }; - - port@1 { - reg = <1>; - funnel_in_port1: endpoint { - remote-endpoint = <&ptm1_out_port>; - }; - }; - - port@2 { - reg = <2>; - funnel_in_port2: endpoint { - remote-endpoint = <&etm0_out_port>; - }; - }; - - /* Input port #3 is for ITM, not supported here */ - - port@4 { - reg = <4>; - funnel_in_port4: endpoint { - remote-endpoint = <&etm1_out_port>; - }; - }; - - port@5 { - reg = <5>; - funnel_in_port5: endpoint { - remote-endpoint = <&etm2_out_port>; - }; - }; - }; - }; - - ptm@2201c000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0 0x2201c000 0 0x1000>; - - cpu = <&cpu0>; - clocks = <&oscclk6a>; - clock-names = "apb_pclk"; - out-ports { - port { - ptm0_out_port: endpoint { - remote-endpoint = <&funnel_in_port0>; - }; - }; - }; - }; - - ptm@2201d000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0 0x2201d000 0 0x1000>; - - cpu = <&cpu1>; - clocks = <&oscclk6a>; - clock-names = "apb_pclk"; - out-ports { - port { - ptm1_out_port: endpoint { - remote-endpoint = <&funnel_in_port1>; - }; - }; - }; - }; - - etm@2203c000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0 0x2203c000 0 0x1000>; - - cpu = <&cpu2>; - clocks = <&oscclk6a>; - clock-names = "apb_pclk"; - out-ports { - port { - etm0_out_port: endpoint { - remote-endpoint = <&funnel_in_port2>; - }; - }; - }; - }; - - etm@2203d000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0 0x2203d000 0 0x1000>; - - cpu = <&cpu3>; - clocks = <&oscclk6a>; - clock-names = "apb_pclk"; - out-ports { - port { - etm1_out_port: endpoint { - remote-endpoint = <&funnel_in_port4>; - }; - }; - }; - }; - - etm@2203e000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0 0x2203e000 0 0x1000>; - - cpu = <&cpu4>; - clocks = <&oscclk6a>; - clock-names = "apb_pclk"; - out-ports { - port { - etm2_out_port: endpoint { - remote-endpoint = <&funnel_in_port5>; - }; - }; - }; - }; - - smb: smb@8000000 { - compatible = "simple-bus"; - - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0 0x08000000 0x04000000>, - <1 0 0 0x14000000 0x04000000>, - <2 0 0 0x18000000 0x04000000>, - <3 0 0 0x1c000000 0x04000000>, - <4 0 0 0x0c000000 0x04000000>, - <5 0 0 0x10000000 0x04000000>; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 63>; - interrupt-map = <0 0 0 &gic 0 0 4>, - <0 0 1 &gic 0 1 4>, - <0 0 2 &gic 0 2 4>, - <0 0 3 &gic 0 3 4>, - <0 0 4 &gic 0 4 4>, - <0 0 5 &gic 0 5 4>, - <0 0 6 &gic 0 6 4>, - <0 0 7 &gic 0 7 4>, - <0 0 8 &gic 0 8 4>, - <0 0 9 &gic 0 9 4>, - <0 0 10 &gic 0 10 4>, - <0 0 11 &gic 0 11 4>, - <0 0 12 &gic 0 12 4>, - <0 0 13 &gic 0 13 4>, - <0 0 14 &gic 0 14 4>, - <0 0 15 &gic 0 15 4>, - <0 0 16 &gic 0 16 4>, - <0 0 17 &gic 0 17 4>, - <0 0 18 &gic 0 18 4>, - <0 0 19 &gic 0 19 4>, - <0 0 20 &gic 0 20 4>, - <0 0 21 &gic 0 21 4>, - <0 0 22 &gic 0 22 4>, - <0 0 23 &gic 0 23 4>, - <0 0 24 &gic 0 24 4>, - <0 0 25 &gic 0 25 4>, - <0 0 26 &gic 0 26 4>, - <0 0 27 &gic 0 27 4>, - <0 0 28 &gic 0 28 4>, - <0 0 29 &gic 0 29 4>, - <0 0 30 &gic 0 30 4>, - <0 0 31 &gic 0 31 4>, - <0 0 32 &gic 0 32 4>, - <0 0 33 &gic 0 33 4>, - <0 0 34 &gic 0 34 4>, - <0 0 35 &gic 0 35 4>, - <0 0 36 &gic 0 36 4>, - <0 0 37 &gic 0 37 4>, - <0 0 38 &gic 0 38 4>, - <0 0 39 &gic 0 39 4>, - <0 0 40 &gic 0 40 4>, - <0 0 41 &gic 0 41 4>, - <0 0 42 &gic 0 42 4>; - }; - - site2: hsb@40000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x40000000 0x3fef0000>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 3>; - interrupt-map = <0 0 &gic 0 36 4>, - <0 1 &gic 0 37 4>, - <0 2 &gic 0 38 4>, - <0 3 &gic 0 39 4>; - }; -}; - -&nor_flash { - /* - * Unfortunately, accessing the flash disturbs the CPU idle states - * (suspend) and CPU hotplug of this platform. For this reason, flash - * hardware access is disabled by default on this platform alone. - */ - status = "disabled"; -}; diff --git a/sys/gnu/dts/arm/vexpress-v2p-ca5s.dts b/sys/gnu/dts/arm/vexpress-v2p-ca5s.dts deleted file mode 100644 index d5b47d526f9..00000000000 --- a/sys/gnu/dts/arm/vexpress-v2p-ca5s.dts +++ /dev/null @@ -1,280 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * ARM Ltd. Versatile Express - * - * CoreTile Express A5x2 - * Cortex-A5 MPCore (V2P-CA5s) - * - * HBI-0225B - */ - -/dts-v1/; -#include "vexpress-v2m-rs1.dtsi" - -/ { - model = "V2P-CA5s"; - arm,hbi = <0x225>; - arm,vexpress,site = <0xf>; - compatible = "arm,vexpress,v2p-ca5s", "arm,vexpress"; - interrupt-parent = <&gic>; - #address-cells = <1>; - #size-cells = <1>; - - chosen { }; - - aliases { - serial0 = &v2m_serial0; - serial1 = &v2m_serial1; - serial2 = &v2m_serial2; - serial3 = &v2m_serial3; - i2c0 = &v2m_i2c_dvi; - i2c1 = &v2m_i2c_pcie; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a5"; - reg = <0>; - next-level-cache = <&L2>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a5"; - reg = <1>; - next-level-cache = <&L2>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x40000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - /* Chipselect 2 is physically at 0x18000000 */ - vram: vram@18000000 { - /* 8 MB of designated video RAM */ - compatible = "shared-dma-pool"; - reg = <0x18000000 0x00800000>; - no-map; - }; - }; - - hdlcd@2a110000 { - compatible = "arm,hdlcd"; - reg = <0x2a110000 0x1000>; - interrupts = <0 85 4>; - clocks = <&hdlcd_clk>; - clock-names = "pxlclk"; - }; - - memory-controller@2a150000 { - compatible = "arm,pl341", "arm,primecell"; - reg = <0x2a150000 0x1000>; - clocks = <&axi_clk>; - clock-names = "apb_pclk"; - }; - - memory-controller@2a190000 { - compatible = "arm,pl354", "arm,primecell"; - reg = <0x2a190000 0x1000>; - interrupts = <0 86 4>, - <0 87 4>; - clocks = <&axi_clk>; - clock-names = "apb_pclk"; - }; - - scu@2c000000 { - compatible = "arm,cortex-a5-scu"; - reg = <0x2c000000 0x58>; - }; - - timer@2c000600 { - compatible = "arm,cortex-a5-twd-timer"; - reg = <0x2c000600 0x20>; - interrupts = <1 13 0x304>; - }; - - timer@2c000200 { - compatible = "arm,cortex-a5-global-timer", - "arm,cortex-a9-global-timer"; - reg = <0x2c000200 0x20>; - interrupts = <1 11 0x304>; - clocks = <&cpu_clk>; - }; - - watchdog@2c000620 { - compatible = "arm,cortex-a5-twd-wdt"; - reg = <0x2c000620 0x20>; - interrupts = <1 14 0x304>; - }; - - gic: interrupt-controller@2c001000 { - compatible = "arm,cortex-a5-gic", "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x2c001000 0x1000>, - <0x2c000100 0x100>; - }; - - L2: cache-controller@2c0f0000 { - compatible = "arm,pl310-cache"; - reg = <0x2c0f0000 0x1000>; - interrupts = <0 84 4>; - cache-level = <2>; - }; - - pmu { - compatible = "arm,cortex-a5-pmu"; - interrupts = <0 68 4>, - <0 69 4>; - }; - - dcc { - compatible = "arm,vexpress,config-bus"; - arm,vexpress,config-bridge = <&v2m_sysreg>; - - cpu_clk: oscclk0 { - /* CPU and internal AXI reference clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 0>; - freq-range = <50000000 100000000>; - #clock-cells = <0>; - clock-output-names = "oscclk0"; - }; - - axi_clk: oscclk1 { - /* Multiplexed AXI master clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 1>; - freq-range = <5000000 50000000>; - #clock-cells = <0>; - clock-output-names = "oscclk1"; - }; - - oscclk2 { - /* DDR2 */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 2>; - freq-range = <80000000 120000000>; - #clock-cells = <0>; - clock-output-names = "oscclk2"; - }; - - hdlcd_clk: oscclk3 { - /* HDLCD */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 3>; - freq-range = <23750000 165000000>; - #clock-cells = <0>; - clock-output-names = "oscclk3"; - }; - - oscclk4 { - /* Test chip gate configuration */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 4>; - freq-range = <80000000 80000000>; - #clock-cells = <0>; - clock-output-names = "oscclk4"; - }; - - smbclk: oscclk5 { - /* SMB clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 5>; - freq-range = <25000000 60000000>; - #clock-cells = <0>; - clock-output-names = "oscclk5"; - }; - - temp-dcc { - /* DCC internal operating temperature */ - compatible = "arm,vexpress-temp"; - arm,vexpress-sysreg,func = <4 0>; - label = "DCC"; - }; - }; - - smb: smb@8000000 { - compatible = "simple-bus"; - - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0x08000000 0x04000000>, - <1 0 0x14000000 0x04000000>, - <2 0 0x18000000 0x04000000>, - <3 0 0x1c000000 0x04000000>, - <4 0 0x0c000000 0x04000000>, - <5 0 0x10000000 0x04000000>; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 63>; - interrupt-map = <0 0 0 &gic 0 0 4>, - <0 0 1 &gic 0 1 4>, - <0 0 2 &gic 0 2 4>, - <0 0 3 &gic 0 3 4>, - <0 0 4 &gic 0 4 4>, - <0 0 5 &gic 0 5 4>, - <0 0 6 &gic 0 6 4>, - <0 0 7 &gic 0 7 4>, - <0 0 8 &gic 0 8 4>, - <0 0 9 &gic 0 9 4>, - <0 0 10 &gic 0 10 4>, - <0 0 11 &gic 0 11 4>, - <0 0 12 &gic 0 12 4>, - <0 0 13 &gic 0 13 4>, - <0 0 14 &gic 0 14 4>, - <0 0 15 &gic 0 15 4>, - <0 0 16 &gic 0 16 4>, - <0 0 17 &gic 0 17 4>, - <0 0 18 &gic 0 18 4>, - <0 0 19 &gic 0 19 4>, - <0 0 20 &gic 0 20 4>, - <0 0 21 &gic 0 21 4>, - <0 0 22 &gic 0 22 4>, - <0 0 23 &gic 0 23 4>, - <0 0 24 &gic 0 24 4>, - <0 0 25 &gic 0 25 4>, - <0 0 26 &gic 0 26 4>, - <0 0 27 &gic 0 27 4>, - <0 0 28 &gic 0 28 4>, - <0 0 29 &gic 0 29 4>, - <0 0 30 &gic 0 30 4>, - <0 0 31 &gic 0 31 4>, - <0 0 32 &gic 0 32 4>, - <0 0 33 &gic 0 33 4>, - <0 0 34 &gic 0 34 4>, - <0 0 35 &gic 0 35 4>, - <0 0 36 &gic 0 36 4>, - <0 0 37 &gic 0 37 4>, - <0 0 38 &gic 0 38 4>, - <0 0 39 &gic 0 39 4>, - <0 0 40 &gic 0 40 4>, - <0 0 41 &gic 0 41 4>, - <0 0 42 &gic 0 42 4>; - }; - - site2: hsb@40000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x40000000 0x40000000>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 3>; - interrupt-map = <0 0 &gic 0 36 4>, - <0 1 &gic 0 37 4>, - <0 2 &gic 0 38 4>, - <0 3 &gic 0 39 4>; - }; -}; diff --git a/sys/gnu/dts/arm/vexpress-v2p-ca9.dts b/sys/gnu/dts/arm/vexpress-v2p-ca9.dts deleted file mode 100644 index d796efaadbe..00000000000 --- a/sys/gnu/dts/arm/vexpress-v2p-ca9.dts +++ /dev/null @@ -1,368 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * ARM Ltd. Versatile Express - * - * CoreTile Express A9x4 - * Cortex-A9 MPCore (V2P-CA9) - * - * HBI-0191B - */ - -/dts-v1/; -#include "vexpress-v2m.dtsi" - -/ { - model = "V2P-CA9"; - arm,hbi = <0x191>; - arm,vexpress,site = <0xf>; - compatible = "arm,vexpress,v2p-ca9", "arm,vexpress"; - interrupt-parent = <&gic>; - #address-cells = <1>; - #size-cells = <1>; - - chosen { }; - - aliases { - serial0 = &v2m_serial0; - serial1 = &v2m_serial1; - serial2 = &v2m_serial2; - serial3 = &v2m_serial3; - i2c0 = &v2m_i2c_dvi; - i2c1 = &v2m_i2c_pcie; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - A9_0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - next-level-cache = <&L2>; - }; - - A9_1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <1>; - next-level-cache = <&L2>; - }; - - A9_2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <2>; - next-level-cache = <&L2>; - }; - - A9_3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <3>; - next-level-cache = <&L2>; - }; - }; - - memory@60000000 { - device_type = "memory"; - reg = <0x60000000 0x40000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - /* Chipselect 3 is physically at 0x4c000000 */ - vram: vram@4c000000 { - /* 8 MB of designated video RAM */ - compatible = "shared-dma-pool"; - reg = <0x4c000000 0x00800000>; - no-map; - }; - }; - - clcd@10020000 { - compatible = "arm,pl111", "arm,primecell"; - reg = <0x10020000 0x1000>; - interrupt-names = "combined"; - interrupts = <0 44 4>; - clocks = <&oscclk1>, <&oscclk2>; - clock-names = "clcdclk", "apb_pclk"; - /* 1024x768 16bpp @65MHz */ - max-memory-bandwidth = <95000000>; - - port { - clcd_pads_ct: endpoint { - remote-endpoint = <&dvi_bridge_in_ct>; - arm,pl11x,tft-r0g0b0-pads = <0 8 16>; - }; - }; - }; - - memory-controller@100e0000 { - compatible = "arm,pl341", "arm,primecell"; - reg = <0x100e0000 0x1000>; - clocks = <&oscclk2>; - clock-names = "apb_pclk"; - }; - - memory-controller@100e1000 { - compatible = "arm,pl354", "arm,primecell"; - reg = <0x100e1000 0x1000>; - interrupts = <0 45 4>, - <0 46 4>; - clocks = <&oscclk2>; - clock-names = "apb_pclk"; - }; - - timer@100e4000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x100e4000 0x1000>; - interrupts = <0 48 4>, - <0 49 4>; - clocks = <&oscclk2>, <&oscclk2>; - clock-names = "timclk", "apb_pclk"; - status = "disabled"; - }; - - watchdog@100e5000 { - compatible = "arm,sp805", "arm,primecell"; - reg = <0x100e5000 0x1000>; - interrupts = <0 51 4>; - clocks = <&oscclk2>, <&oscclk2>; - clock-names = "wdogclk", "apb_pclk"; - }; - - scu@1e000000 { - compatible = "arm,cortex-a9-scu"; - reg = <0x1e000000 0x58>; - }; - - timer@1e000600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0x1e000600 0x20>; - interrupts = <1 13 0xf04>; - }; - - watchdog@1e000620 { - compatible = "arm,cortex-a9-twd-wdt"; - reg = <0x1e000620 0x20>; - interrupts = <1 14 0xf04>; - }; - - gic: interrupt-controller@1e001000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x1e001000 0x1000>, - <0x1e000100 0x100>; - }; - - L2: cache-controller@1e00a000 { - compatible = "arm,pl310-cache"; - reg = <0x1e00a000 0x1000>; - interrupts = <0 43 4>; - cache-unified; - cache-level = <2>; - arm,data-latency = <1 1 1>; - arm,tag-latency = <1 1 1>; - }; - - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts = <0 60 4>, - <0 61 4>, - <0 62 4>, - <0 63 4>; - interrupt-affinity = <&A9_0>, <&A9_1>, <&A9_2>, <&A9_3>; - - }; - - dcc { - compatible = "arm,vexpress,config-bus"; - arm,vexpress,config-bridge = <&v2m_sysreg>; - - oscclk0: extsaxiclk { - /* ACLK clock to the AXI master port on the test chip */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 0>; - freq-range = <30000000 50000000>; - #clock-cells = <0>; - clock-output-names = "extsaxiclk"; - }; - - oscclk1: clcdclk { - /* Reference clock for the CLCD */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 1>; - freq-range = <10000000 80000000>; - #clock-cells = <0>; - clock-output-names = "clcdclk"; - }; - - smbclk: oscclk2: tcrefclk { - /* Reference clock for the test chip internal PLLs */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 2>; - freq-range = <33000000 100000000>; - #clock-cells = <0>; - clock-output-names = "tcrefclk"; - }; - - volt-vd10 { - /* Test Chip internal logic voltage */ - compatible = "arm,vexpress-volt"; - arm,vexpress-sysreg,func = <2 0>; - regulator-name = "VD10"; - regulator-always-on; - label = "VD10"; - }; - - volt-vd10-s2 { - /* PL310, L2 cache, RAM cell supply (not PL310 logic) */ - compatible = "arm,vexpress-volt"; - arm,vexpress-sysreg,func = <2 1>; - regulator-name = "VD10_S2"; - regulator-always-on; - label = "VD10_S2"; - }; - - volt-vd10-s3 { - /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */ - compatible = "arm,vexpress-volt"; - arm,vexpress-sysreg,func = <2 2>; - regulator-name = "VD10_S3"; - regulator-always-on; - label = "VD10_S3"; - }; - - volt-vcc1v8 { - /* DDR2 SDRAM and Test Chip DDR2 I/O supply */ - compatible = "arm,vexpress-volt"; - arm,vexpress-sysreg,func = <2 3>; - regulator-name = "VCC1V8"; - regulator-always-on; - label = "VCC1V8"; - }; - - volt-ddr2vtt { - /* DDR2 SDRAM VTT termination voltage */ - compatible = "arm,vexpress-volt"; - arm,vexpress-sysreg,func = <2 4>; - regulator-name = "DDR2VTT"; - regulator-always-on; - label = "DDR2VTT"; - }; - - volt-vcc3v3 { - /* Local board supply for miscellaneous logic external to the Test Chip */ - arm,vexpress-sysreg,func = <2 5>; - compatible = "arm,vexpress-volt"; - regulator-name = "VCC3V3"; - regulator-always-on; - label = "VCC3V3"; - }; - - amp-vd10-s2 { - /* PL310, L2 cache, RAM cell supply (not PL310 logic) */ - compatible = "arm,vexpress-amp"; - arm,vexpress-sysreg,func = <3 0>; - label = "VD10_S2"; - }; - - amp-vd10-s3 { - /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */ - compatible = "arm,vexpress-amp"; - arm,vexpress-sysreg,func = <3 1>; - label = "VD10_S3"; - }; - - power-vd10-s2 { - /* PL310, L2 cache, RAM cell supply (not PL310 logic) */ - compatible = "arm,vexpress-power"; - arm,vexpress-sysreg,func = <12 0>; - label = "PVD10_S2"; - }; - - power-vd10-s3 { - /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */ - compatible = "arm,vexpress-power"; - arm,vexpress-sysreg,func = <12 1>; - label = "PVD10_S3"; - }; - }; - - smb: smb@4000000 { - compatible = "simple-bus"; - - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0x40000000 0x04000000>, - <1 0 0x44000000 0x04000000>, - <2 0 0x48000000 0x04000000>, - <3 0 0x4c000000 0x04000000>, - <7 0 0x10000000 0x00020000>; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 63>; - interrupt-map = <0 0 0 &gic 0 0 4>, - <0 0 1 &gic 0 1 4>, - <0 0 2 &gic 0 2 4>, - <0 0 3 &gic 0 3 4>, - <0 0 4 &gic 0 4 4>, - <0 0 5 &gic 0 5 4>, - <0 0 6 &gic 0 6 4>, - <0 0 7 &gic 0 7 4>, - <0 0 8 &gic 0 8 4>, - <0 0 9 &gic 0 9 4>, - <0 0 10 &gic 0 10 4>, - <0 0 11 &gic 0 11 4>, - <0 0 12 &gic 0 12 4>, - <0 0 13 &gic 0 13 4>, - <0 0 14 &gic 0 14 4>, - <0 0 15 &gic 0 15 4>, - <0 0 16 &gic 0 16 4>, - <0 0 17 &gic 0 17 4>, - <0 0 18 &gic 0 18 4>, - <0 0 19 &gic 0 19 4>, - <0 0 20 &gic 0 20 4>, - <0 0 21 &gic 0 21 4>, - <0 0 22 &gic 0 22 4>, - <0 0 23 &gic 0 23 4>, - <0 0 24 &gic 0 24 4>, - <0 0 25 &gic 0 25 4>, - <0 0 26 &gic 0 26 4>, - <0 0 27 &gic 0 27 4>, - <0 0 28 &gic 0 28 4>, - <0 0 29 &gic 0 29 4>, - <0 0 30 &gic 0 30 4>, - <0 0 31 &gic 0 31 4>, - <0 0 32 &gic 0 32 4>, - <0 0 33 &gic 0 33 4>, - <0 0 34 &gic 0 34 4>, - <0 0 35 &gic 0 35 4>, - <0 0 36 &gic 0 36 4>, - <0 0 37 &gic 0 37 4>, - <0 0 38 &gic 0 38 4>, - <0 0 39 &gic 0 39 4>, - <0 0 40 &gic 0 40 4>, - <0 0 41 &gic 0 41 4>, - <0 0 42 &gic 0 42 4>; - }; - - site2: hsb@e0000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0xe0000000 0x20000000>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 3>; - interrupt-map = <0 0 &gic 0 36 4>, - <0 1 &gic 0 37 4>, - <0 2 &gic 0 38 4>, - <0 3 &gic 0 39 4>; - }; -}; diff --git a/sys/gnu/dts/arm/vf-colibri-eval-v3.dtsi b/sys/gnu/dts/arm/vf-colibri-eval-v3.dtsi deleted file mode 100644 index e2da122a63f..00000000000 --- a/sys/gnu/dts/arm/vf-colibri-eval-v3.dtsi +++ /dev/null @@ -1,188 +0,0 @@ -/* - * Copyright 2014 Toradex AG - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/ { - chosen { - stdout-path = "serial0:115200n8"; - }; - - clk16m: clk16m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <16000000>; - }; - - panel: panel { - compatible = "edt,et057090dhu"; - backlight = <&bl>; - - port { - panel_in: endpoint { - remote-endpoint = <&dcu_out>; - }; - }; - }; - - reg_3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_5v0: regulator-5v0 { - compatible = "regulator-fixed"; - regulator-name = "5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_usbh_vbus: regulator-usbh-vbus { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh1_reg>; - regulator-name = "VCC_USB[1-4]"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio2 19 GPIO_ACTIVE_LOW>; /* USBH_PEN resp. USBH_P_EN */ - vin-supply = <®_5v0>; - }; -}; - -&bl { - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - power-supply = <®_3v3>; - status = "okay"; -}; - -&dcu0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_dcu0_1>; - status = "okay"; - - port { - dcu_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; -}; - -&dspi1 { - status = "okay"; - - mcp2515can: can@0 { - compatible = "microchip,mcp2515"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can_int>; - reg = <0>; - clocks = <&clk16m>; - spi-max-frequency = <10000000>; - interrupt-parent = <&gpio1>; - interrupts = <11 IRQ_TYPE_EDGE_RISING>; - }; -}; - -&esdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc1>; - bus-width = <4>; - status = "okay"; -}; - -&fec1 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - /* M41T0M6 real time clock on carrier board */ - rtc: m41t0m6@68 { - compatible = "st,m41t0"; - reg = <0x68>; - }; -}; - -&pwm0 { - status = "okay"; -}; - -&pwm1 { - status = "okay"; -}; - -®_module_3v3 { - vin-supply = <®_3v3>; -}; - -&tcon0 { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usbh_vbus>; -}; - -&iomuxc { - vf610-colibri { - pinctrl_can_int: can_int { - fsl,pins = < - VF610_PAD_PTB21__GPIO_43 0x22ed - >; - }; - }; -}; diff --git a/sys/gnu/dts/arm/vf-colibri.dtsi b/sys/gnu/dts/arm/vf-colibri.dtsi deleted file mode 100644 index fba37b8756f..00000000000 --- a/sys/gnu/dts/arm/vf-colibri.dtsi +++ /dev/null @@ -1,385 +0,0 @@ -/* - * Copyright 2014 Toradex AG - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/ { - aliases { - ethernet0 = &fec1; - ethernet1 = &fec0; - }; - - bl: backlight { - compatible = "pwm-backlight"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_bl_on>; - pwms = <&pwm0 0 5000000 0>; - enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; - status = "disabled"; - }; - - reg_module_3v3: regulator-module-3v3 { - compatible = "regulator-fixed"; - regulator-name = "+V3.3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_module_3v3_avdd: regulator-module-3v3-avdd { - compatible = "regulator-fixed"; - regulator-name = "+V3.3_AVDD_AUDIO"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&adc0 { - status = "okay"; - vref-supply = <®_module_3v3_avdd>; -}; - -&adc1 { - status = "okay"; - vref-supply = <®_module_3v3_avdd>; -}; - -&can0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan0>; - status = "disabled"; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - status = "disabled"; -}; - -&clks { - assigned-clocks = <&clks VF610_CLK_ENET_SEL>, - <&clks VF610_CLK_ENET_TS_SEL>; - assigned-clock-parents = <&clks VF610_CLK_ENET_50M>, - <&clks VF610_CLK_ENET_50M>; -}; - -&dspi1 { - bus-num = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_dspi1>; -}; - -&edma0 { - status = "okay"; -}; - -&edma1 { - status = "okay"; -}; - -&esdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc1>; - bus-width = <4>; - cd-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; - disable-wp; -}; - -&fec1 { - phy-mode = "rmii"; - phy-supply = <®_module_3v3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; -}; - -&i2c0 { - clock-frequency = <400000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c0>; - pinctrl-1 = <&pinctrl_i2c0_gpio>; - scl-gpios = <&gpio1 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio1 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; -}; - -&nfc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nfc>; - status = "okay"; - - nand@0 { - compatible = "fsl,vf610-nfc-nandcs"; - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - nand-ecc-strength = <32>; - nand-ecc-step-size = <2048>; - nand-on-flash-bbt; - }; -}; - -&pwm0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm0>; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0>; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; -}; - -&usbdev0 { - disable-over-current; - status = "okay"; -}; - -&usbh1 { - disable-over-current; - status = "okay"; -}; - -&usbmisc0 { - status = "okay"; -}; - -&usbmisc1 { - status = "okay"; -}; - -&usbphy0 { - status = "okay"; -}; - -&usbphy1 { - status = "okay"; -}; - -&iomuxc { - vf610-colibri { - pinctrl_flexcan0: can0grp { - fsl,pins = < - VF610_PAD_PTB14__CAN0_RX 0x31F1 - VF610_PAD_PTB15__CAN0_TX 0x31F2 - >; - }; - - pinctrl_flexcan1: can1grp { - fsl,pins = < - VF610_PAD_PTB16__CAN1_RX 0x31F1 - VF610_PAD_PTB17__CAN1_TX 0x31F2 - >; - }; - - pinctrl_gpio_ext: gpio_ext { - fsl,pins = < - VF610_PAD_PTD10__GPIO_89 0x22ed /* EXT_IO_0 */ - VF610_PAD_PTD9__GPIO_88 0x22ed /* EXT_IO_1 */ - VF610_PAD_PTD26__GPIO_68 0x22ed /* EXT_IO_2 */ - >; - }; - - pinctrl_dcu0_1: dcu0grp_1 { - fsl,pins = < - VF610_PAD_PTE0__DCU0_HSYNC 0x1902 - VF610_PAD_PTE1__DCU0_VSYNC 0x1902 - VF610_PAD_PTE2__DCU0_PCLK 0x1902 - VF610_PAD_PTE4__DCU0_DE 0x1902 - VF610_PAD_PTE5__DCU0_R0 0x1902 - VF610_PAD_PTE6__DCU0_R1 0x1902 - VF610_PAD_PTE7__DCU0_R2 0x1902 - VF610_PAD_PTE8__DCU0_R3 0x1902 - VF610_PAD_PTE9__DCU0_R4 0x1902 - VF610_PAD_PTE10__DCU0_R5 0x1902 - VF610_PAD_PTE11__DCU0_R6 0x1902 - VF610_PAD_PTE12__DCU0_R7 0x1902 - VF610_PAD_PTE13__DCU0_G0 0x1902 - VF610_PAD_PTE14__DCU0_G1 0x1902 - VF610_PAD_PTE15__DCU0_G2 0x1902 - VF610_PAD_PTE16__DCU0_G3 0x1902 - VF610_PAD_PTE17__DCU0_G4 0x1902 - VF610_PAD_PTE18__DCU0_G5 0x1902 - VF610_PAD_PTE19__DCU0_G6 0x1902 - VF610_PAD_PTE20__DCU0_G7 0x1902 - VF610_PAD_PTE21__DCU0_B0 0x1902 - VF610_PAD_PTE22__DCU0_B1 0x1902 - VF610_PAD_PTE23__DCU0_B2 0x1902 - VF610_PAD_PTE24__DCU0_B3 0x1902 - VF610_PAD_PTE25__DCU0_B4 0x1902 - VF610_PAD_PTE26__DCU0_B5 0x1902 - VF610_PAD_PTE27__DCU0_B6 0x1902 - VF610_PAD_PTE28__DCU0_B7 0x1902 - >; - }; - - pinctrl_dspi1: dspi1grp { - fsl,pins = < - VF610_PAD_PTD5__DSPI1_CS0 0x33e2 - VF610_PAD_PTD6__DSPI1_SIN 0x33e1 - VF610_PAD_PTD7__DSPI1_SOUT 0x33e2 - VF610_PAD_PTD8__DSPI1_SCK 0x33e2 - >; - }; - - pinctrl_esdhc1: esdhc1grp { - fsl,pins = < - VF610_PAD_PTA24__ESDHC1_CLK 0x31ef - VF610_PAD_PTA25__ESDHC1_CMD 0x31ef - VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef - VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef - VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef - VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef - VF610_PAD_PTB20__GPIO_42 0x219d - >; - }; - - pinctrl_fec1: fec1grp { - fsl,pins = < - VF610_PAD_PTA6__RMII_CLKOUT 0x30d2 - VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2 - VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3 - VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1 - VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1 - VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1 - VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1 - VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2 - VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2 - VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2 - >; - }; - - pinctrl_gpio_bl_on: gpio_bl_on { - fsl,pins = < - VF610_PAD_PTC0__GPIO_45 0x22ef - >; - }; - - pinctrl_i2c0: i2c0grp { - fsl,pins = < - VF610_PAD_PTB14__I2C0_SCL 0x37ff - VF610_PAD_PTB15__I2C0_SDA 0x37ff - >; - }; - - pinctrl_i2c0_gpio: i2c0gpiogrp { - fsl,pins = < - VF610_PAD_PTB14__GPIO_36 0x37ff - VF610_PAD_PTB15__GPIO_37 0x37ff - >; - }; - - pinctrl_nfc: nfcgrp { - fsl,pins = < - VF610_PAD_PTD23__NF_IO7 0x28df - VF610_PAD_PTD22__NF_IO6 0x28df - VF610_PAD_PTD21__NF_IO5 0x28df - VF610_PAD_PTD20__NF_IO4 0x28df - VF610_PAD_PTD19__NF_IO3 0x28df - VF610_PAD_PTD18__NF_IO2 0x28df - VF610_PAD_PTD17__NF_IO1 0x28df - VF610_PAD_PTD16__NF_IO0 0x28df - VF610_PAD_PTB24__NF_WE_B 0x28c2 - VF610_PAD_PTB25__NF_CE0_B 0x28c2 - VF610_PAD_PTB27__NF_RE_B 0x28c2 - VF610_PAD_PTC26__NF_RB_B 0x283d - VF610_PAD_PTC27__NF_ALE 0x28c2 - VF610_PAD_PTC28__NF_CLE 0x28c2 - >; - }; - - pinctrl_pwm0: pwm0grp { - fsl,pins = < - VF610_PAD_PTB0__FTM0_CH0 0x1182 - VF610_PAD_PTB1__FTM0_CH1 0x1182 - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - VF610_PAD_PTB8__FTM1_CH0 0x1182 - VF610_PAD_PTB9__FTM1_CH1 0x1182 - >; - }; - - pinctrl_uart0: uart0grp { - fsl,pins = < - VF610_PAD_PTB10__UART0_TX 0x21a2 - VF610_PAD_PTB11__UART0_RX 0x21a1 - VF610_PAD_PTB12__UART0_RTS 0x21a2 - VF610_PAD_PTB13__UART0_CTS 0x21a1 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - VF610_PAD_PTB4__UART1_TX 0x21a2 - VF610_PAD_PTB5__UART1_RX 0x21a1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - VF610_PAD_PTD0__UART2_TX 0x21a2 - VF610_PAD_PTD1__UART2_RX 0x21a1 - VF610_PAD_PTD2__UART2_RTS 0x21a2 - VF610_PAD_PTD3__UART2_CTS 0x21a1 - >; - }; - - pinctrl_usbh1_reg: gpio_usb_vbus { - fsl,pins = < - VF610_PAD_PTD4__GPIO_83 0x22ed - >; - }; - }; -}; diff --git a/sys/gnu/dts/arm/vf500-colibri-eval-v3.dts b/sys/gnu/dts/arm/vf500-colibri-eval-v3.dts deleted file mode 100644 index 076998968fb..00000000000 --- a/sys/gnu/dts/arm/vf500-colibri-eval-v3.dts +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright 2014 Toradex AG - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "vf500-colibri.dtsi" -#include "vf-colibri-eval-v3.dtsi" - -/ { - model = "Toradex Colibri VF50 on Colibri Evaluation Board"; - compatible = "toradex,vf500-colibri_vf50-on-eval", "toradex,vf500-colibri_vf50", "fsl,vf500"; -}; - -&touchscreen { - vf50-ts-min-pressure = <200>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/vf500-colibri.dtsi b/sys/gnu/dts/arm/vf500-colibri.dtsi deleted file mode 100644 index 92255f8893c..00000000000 --- a/sys/gnu/dts/arm/vf500-colibri.dtsi +++ /dev/null @@ -1,105 +0,0 @@ -/* - * Copyright 2014 Toradex AG - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "vf500.dtsi" -#include "vf-colibri.dtsi" - -/ { - model = "Toradex Colibri VF50 COM"; - compatible = "toradex,vf500-colibri_vf50", "fsl,vf500"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x8000000>; - }; - - touchscreen: vf50-touchscreen { - compatible = "toradex,vf50-touchscreen"; - io-channels = <&adc1 0>,<&adc0 0>, - <&adc0 1>,<&adc1 2>; - xp-gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; - xm-gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>; - yp-gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; - ym-gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>; - interrupt-parent = <&gpio0>; - interrupts = <8 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "idle","default","gpios"; - pinctrl-0 = <&pinctrl_touchctrl_idle>; - pinctrl-1 = <&pinctrl_touchctrl_default>; - pinctrl-2 = <&pinctrl_touchctrl_gpios>; - vf50-ts-min-pressure = <200>; - status = "disabled"; - }; -}; - -&nfc { - assigned-clocks = <&clks VF610_CLK_NFC>; - assigned-clock-rates = <33000000>; -}; - -&iomuxc { - vf610-colibri { - pinctrl_touchctrl_idle: touchctrl_idle { - fsl,pins = < - VF610_PAD_PTA18__GPIO_8 0x006d - VF610_PAD_PTA19__GPIO_9 0x006c - >; - }; - - pinctrl_touchctrl_default: touchctrl_default { - fsl,pins = < - VF610_PAD_PTA18__ADC0_SE0 0x0040 - VF610_PAD_PTA19__ADC0_SE1 0x0040 - VF610_PAD_PTA16__ADC1_SE0 0x0040 - VF610_PAD_PTB2__ADC1_SE2 0x0040 - >; - }; - - pinctrl_touchctrl_gpios: touchctrl_gpios { - fsl,pins = < - VF610_PAD_PTA23__GPIO_13 0x22e9 - VF610_PAD_PTB23__GPIO_93 0x22e9 - VF610_PAD_PTA22__GPIO_12 0x22e9 - VF610_PAD_PTA11__GPIO_4 0x22e9 - >; - }; - }; -}; diff --git a/sys/gnu/dts/arm/vf500.dtsi b/sys/gnu/dts/arm/vf500.dtsi deleted file mode 100644 index b0ec475017a..00000000000 --- a/sys/gnu/dts/arm/vf500.dtsi +++ /dev/null @@ -1,64 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -// -// Copyright 2013 Freescale Semiconductor, Inc. - -#include "vfxxx.dtsi" -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - chosen { }; - aliases { }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - a5_cpu: cpu@0 { - compatible = "arm,cortex-a5"; - device_type = "cpu"; - reg = <0x0>; - }; - }; - - soc { - aips-bus@40000000 { - - intc: interrupt-controller@40003000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - interrupt-controller; - interrupt-parent = <&intc>; - reg = <0x40003000 0x1000>, - <0x40002100 0x100>; - }; - - global_timer: timer@40002200 { - compatible = "arm,cortex-a9-global-timer"; - reg = <0x40002200 0x20>; - interrupts = ; - interrupt-parent = <&intc>; - clocks = <&clks VF610_CLK_PLATFORM_BUS>; - }; - }; - - aips-bus@40080000 { - pmu@40089000 { - compatible = "arm,cortex-a5-pmu"; - interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&a5_cpu>; - reg = <0x40089000 0x1000>; - }; - }; - - }; -}; - -&mscm_ir { - interrupt-parent = <&intc>; -}; - -&wdoga5 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/vf610-bk4.dts b/sys/gnu/dts/arm/vf610-bk4.dts deleted file mode 100644 index 830c85476b3..00000000000 --- a/sys/gnu/dts/arm/vf610-bk4.dts +++ /dev/null @@ -1,537 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2018 - * Lukasz Majewski, DENX Software Engineering, lukma@denx.de - */ - -/dts-v1/; -#include "vf610.dtsi" - -/ { - model = "Liebherr BK4 controller"; - compatible = "lwn,bk4", "fsl,vf610"; - - chosen { - stdout-path = &uart1; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x8000000>; - }; - - audio_ext: oscillator-audio { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24576000>; - }; - - enet_ext: oscillator-ethernet { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <50000000>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - /* LED D5 */ - led0: heartbeat { - label = "heartbeat"; - gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_vcc_3v3_mcu: regulator-vcc3v3mcu { - compatible = "regulator-fixed"; - regulator-name = "vcc_3v3_mcu"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - spi-gpio { - compatible = "spi-gpio"; - pinctrl-0 = <&pinctrl_gpio_spi>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - /* PTD12 ->RPIO[91] */ - sck-gpios = <&gpio2 27 GPIO_ACTIVE_LOW>; - /* PTD10 ->RPIO[89] */ - miso-gpios = <&gpio2 25 GPIO_ACTIVE_HIGH>; - num-chipselects = <0>; - - gpio@0 { - compatible = "pisosr-gpio"; - reg = <0>; - gpio-controller; - #gpio-cells = <2>; - /* PTB18 -> RGPIO[40] */ - load-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; - spi-max-frequency = <100000>; - }; - }; -}; - -&adc0 { - vref-supply = <®_vcc_3v3_mcu>; - status = "okay"; -}; - -&adc1 { - vref-supply = <®_vcc_3v3_mcu>; - status = "okay"; -}; - -&can0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can0>; - status = "okay"; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can1>; - status = "okay"; -}; - -&clks { - clocks = <&sxosc>, <&fxosc>, <&enet_ext>, <&audio_ext>; - clock-names = "sxosc", "fxosc", "enet_ext", "audio_ext"; -}; - -&dspi0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_dspi0>; - bus-num = <0>; - status = "okay"; - - spidev0@0 { - compatible = "lwn,bk4"; - spi-max-frequency = <30000000>; - reg = <0>; - fsl,spi-cs-sck-delay = <200>; - fsl,spi-sck-cs-delay = <400>; - }; -}; - -&dspi3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_dspi3>; - bus-num = <3>; - status = "okay"; - spi-slave; - #address-cells = <0>; - - slave { - compatible = "lwn,bk4"; - spi-max-frequency = <30000000>; - }; -}; - -&edma0 { - status = "okay"; -}; - -&edma1 { - status = "okay"; -}; - -&esdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc1>; - bus-width = <4>; - cd-gpios = <&gpio3 2 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&fec0 { - phy-mode = "rmii"; - phy-handle = <ðphy0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec0>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@1 { - reg = <1>; - clocks = <&clks VF610_CLK_ENET_50M>; - clock-names = "rmii-ref"; - }; - }; -}; - -&fec1 { - phy-mode = "rmii"; - phy-handle = <ðphy1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy1: ethernet-phy@1 { - reg = <1>; - clocks = <&clks VF610_CLK_ENET_50M>; - clock-names = "rmii-ref"; - }; - }; -}; - -&i2c2 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - at24c256: eeprom@50 { - compatible = "atmel,24c256"; - reg = <0x50>; - }; - - m41t62: rtc@68 { - compatible = "st,m41t62"; - reg = <0x68>; - }; -}; - -&nfc { - assigned-clocks = <&clks VF610_CLK_NFC>; - assigned-clock-rates = <33000000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nfc>; - status = "okay"; - - nand@0 { - compatible = "fsl,vf610-nfc-nandcs"; - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; - nand-bus-width = <16>; - nand-ecc-mode = "hw"; - nand-ecc-strength = <24>; - nand-ecc-step-size = <2048>; - nand-on-flash-bbt; - }; -}; - -&qspi0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_qspi0>; - status = "okay"; - - n25q128a13_4: flash@0 { - compatible = "n25q128a13", "jedec,spi-nor"; - #address-cells = <1>; - #size-cells = <1>; - spi-max-frequency = <66000000>; - spi-rx-bus-width = <4>; - reg = <0>; - }; - - n25q128a13_2: flash@2 { - compatible = "n25q128a13", "jedec,spi-nor"; - #address-cells = <1>; - #size-cells = <1>; - spi-max-frequency = <66000000>; - spi-rx-bus-width = <2>; - reg = <2>; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0>; - /delete-property/dma-names; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - /delete-property/dma-names; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - /delete-property/dma-names; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - /delete-property/dma-names; - status = "okay"; -}; - -&usbdev0 { - disable-over-current; - status = "okay"; -}; - -&usbh1 { - disable-over-current; - status = "okay"; -}; - -&usbmisc0 { - status = "okay"; -}; - -&usbmisc1 { - status = "okay"; -}; - -&usbphy0 { - status = "okay"; -}; - -&usbphy1 { - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_hog: hoggrp { - fsl,pins = < - /* One_Wire_PSU_EN */ - VF610_PAD_PTC29__GPIO_102 0x1183 - /* SPI ENABLE */ - VF610_PAD_PTB26__GPIO_96 0x1183 - /* EB control */ - VF610_PAD_PTE14__GPIO_119 0x1183 - VF610_PAD_PTE4__GPIO_109 0x1181 - /* Feedback_Lines */ - VF610_PAD_PTC31__GPIO_104 0x1181 - VF610_PAD_PTA7__GPIO_134 0x1181 - VF610_PAD_PTD9__GPIO_88 0x1181 - VF610_PAD_PTE1__GPIO_106 0x1183 - VF610_PAD_PTB2__GPIO_24 0x1181 - VF610_PAD_PTB3__GPIO_25 0x1181 - VF610_PAD_PTB1__GPIO_23 0x1181 - /* SDHC Enable */ - VF610_PAD_PTE19__GPIO_124 0x1183 - /* SDHC Overcurrent */ - VF610_PAD_PTB23__GPIO_93 0x1181 - /* GPI */ - VF610_PAD_PTE2__GPIO_107 0x1181 - VF610_PAD_PTE3__GPIO_108 0x1181 - VF610_PAD_PTE5__GPIO_110 0x1181 - VF610_PAD_PTE6__GPIO_111 0x1181 - /* GPO */ - VF610_PAD_PTE0__GPIO_105 0x1183 - VF610_PAD_PTE7__GPIO_112 0x1183 - /* RS485 Control */ - VF610_PAD_PTB8__GPIO_30 0x1183 - VF610_PAD_PTB9__GPIO_31 0x1183 - VF610_PAD_PTE8__GPIO_113 0x1183 - /* MPBUS MPB_EN */ - VF610_PAD_PTE28__GPIO_133 0x1183 - /* MISC */ - VF610_PAD_PTE10__GPIO_115 0x1183 - VF610_PAD_PTE11__GPIO_116 0x1183 - VF610_PAD_PTE17__GPIO_122 0x1183 - VF610_PAD_PTC30__GPIO_103 0x1183 - VF610_PAD_PTB0__GPIO_22 0x1181 - /* RESETINFO */ - VF610_PAD_PTE26__GPIO_131 0x1183 - VF610_PAD_PTD6__GPIO_85 0x1181 - VF610_PAD_PTE27__GPIO_132 0x1181 - VF610_PAD_PTE13__GPIO_118 0x1181 - VF610_PAD_PTE21__GPIO_126 0x1181 - VF610_PAD_PTE22__GPIO_127 0x1181 - /* EE_5V_EN */ - VF610_PAD_PTE18__GPIO_123 0x1183 - /* EE_5V_OC_N */ - VF610_PAD_PTE25__GPIO_130 0x1181 - >; - }; - - pinctrl_can0: can0grp { - fsl,pins = < - VF610_PAD_PTB14__CAN0_RX 0x1181 - VF610_PAD_PTB15__CAN0_TX 0x1182 - >; - }; - - pinctrl_can1: can1grp { - fsl,pins = < - VF610_PAD_PTB16__CAN1_RX 0x1181 - VF610_PAD_PTB17__CAN1_TX 0x1182 - >; - }; - - pinctrl_dspi0: dspi0grp { - fsl,pins = < - VF610_PAD_PTB18__DSPI0_CS1 0x1182 - VF610_PAD_PTB19__DSPI0_CS0 0x1182 - VF610_PAD_PTB20__DSPI0_SIN 0x1181 - VF610_PAD_PTB21__DSPI0_SOUT 0x1182 - VF610_PAD_PTB22__DSPI0_SCK 0x1182 - >; - }; - - pinctrl_dspi3: dspi3grp { - fsl,pins = < - VF610_PAD_PTD10__DSPI3_CS0 0x1181 - VF610_PAD_PTD11__DSPI3_SIN 0x1181 - VF610_PAD_PTD12__DSPI3_SOUT 0x1182 - VF610_PAD_PTD13__DSPI3_SCK 0x1181 - >; - }; - - pinctrl_esdhc1: esdhc1grp { - fsl,pins = < - VF610_PAD_PTA24__ESDHC1_CLK 0x31ef - VF610_PAD_PTA25__ESDHC1_CMD 0x31ef - VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef - VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef - VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef - VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef - VF610_PAD_PTB28__GPIO_98 0x219d - >; - }; - - pinctrl_fec0: fec0grp { - fsl,pins = < - VF610_PAD_PTA6__RMII_CLKIN 0x30dd - VF610_PAD_PTC0__ENET_RMII0_MDC 0x30de - VF610_PAD_PTC1__ENET_RMII0_MDIO 0x30df - VF610_PAD_PTC2__ENET_RMII0_CRS 0x30dd - VF610_PAD_PTC3__ENET_RMII0_RXD1 0x30dd - VF610_PAD_PTC4__ENET_RMII0_RXD0 0x30dd - VF610_PAD_PTC5__ENET_RMII0_RXER 0x30dd - VF610_PAD_PTC6__ENET_RMII0_TXD1 0x30de - VF610_PAD_PTC7__ENET_RMII0_TXD0 0x30de - VF610_PAD_PTC8__ENET_RMII0_TXEN 0x30de - >; - }; - - pinctrl_fec1: fec1grp { - fsl,pins = < - VF610_PAD_PTC9__ENET_RMII1_MDC 0x30de - VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30df - VF610_PAD_PTC11__ENET_RMII1_CRS 0x30dd - VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30dd - VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30dd - VF610_PAD_PTC14__ENET_RMII1_RXER 0x30dd - VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30de - VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30de - VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30de - >; - }; - - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - /* Heart bit LED */ - VF610_PAD_PTE12__GPIO_117 0x1183 - /* LEDS */ - VF610_PAD_PTE15__GPIO_120 0x1183 - VF610_PAD_PTA12__GPIO_5 0x1183 - VF610_PAD_PTA16__GPIO_6 0x1183 - VF610_PAD_PTE9__GPIO_114 0x1183 - VF610_PAD_PTE20__GPIO_125 0x1183 - VF610_PAD_PTE23__GPIO_128 0x1183 - VF610_PAD_PTE16__GPIO_121 0x1183 - >; - }; - - pinctrl_gpio_spi: pinctrl-gpio-spi { - fsl,pins = < - VF610_PAD_PTB18__GPIO_40 0x1183 - VF610_PAD_PTD10__GPIO_89 0x1183 - VF610_PAD_PTD12__GPIO_91 0x1183 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - VF610_PAD_PTA22__I2C2_SCL 0x34df - VF610_PAD_PTA23__I2C2_SDA 0x34df - >; - }; - - pinctrl_nfc: nfcgrp { - fsl,pins = < - VF610_PAD_PTD23__NF_IO7 0x28df - VF610_PAD_PTD22__NF_IO6 0x28df - VF610_PAD_PTD21__NF_IO5 0x28df - VF610_PAD_PTD20__NF_IO4 0x28df - VF610_PAD_PTD19__NF_IO3 0x28df - VF610_PAD_PTD18__NF_IO2 0x28df - VF610_PAD_PTD17__NF_IO1 0x28df - VF610_PAD_PTD16__NF_IO0 0x28df - VF610_PAD_PTB24__NF_WE_B 0x28c2 - VF610_PAD_PTB25__NF_CE0_B 0x28c2 - VF610_PAD_PTB27__NF_RE_B 0x28c2 - VF610_PAD_PTC26__NF_RB_B 0x283d - VF610_PAD_PTC27__NF_ALE 0x28c2 - VF610_PAD_PTC28__NF_CLE 0x28c2 - >; - }; - - pinctrl_qspi0: qspi0grp { - fsl,pins = < - VF610_PAD_PTD0__QSPI0_A_QSCK 0x397f - VF610_PAD_PTD1__QSPI0_A_CS0 0x397f - VF610_PAD_PTD2__QSPI0_A_DATA3 0x397f - VF610_PAD_PTD3__QSPI0_A_DATA2 0x397f - VF610_PAD_PTD4__QSPI0_A_DATA1 0x397f - VF610_PAD_PTD5__QSPI0_A_DATA0 0x397f - VF610_PAD_PTD7__QSPI0_B_QSCK 0x397f - VF610_PAD_PTD8__QSPI0_B_CS0 0x397f - VF610_PAD_PTD11__QSPI0_B_DATA1 0x397f - VF610_PAD_PTD12__QSPI0_B_DATA0 0x397f - >; - }; - - pinctrl_uart0: uart0grp { - fsl,pins = < - VF610_PAD_PTB10__UART0_TX 0x21a2 - VF610_PAD_PTB11__UART0_RX 0x21a1 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - VF610_PAD_PTB4__UART1_TX 0x21a2 - VF610_PAD_PTB5__UART1_RX 0x21a1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - VF610_PAD_PTB6__UART2_TX 0x21a2 - VF610_PAD_PTB7__UART2_RX 0x21a1 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - VF610_PAD_PTA20__UART3_TX 0x21a2 - VF610_PAD_PTA21__UART3_RX 0x21a1 - >; - }; -}; diff --git a/sys/gnu/dts/arm/vf610-colibri-eval-v3.dts b/sys/gnu/dts/arm/vf610-colibri-eval-v3.dts deleted file mode 100644 index ef9b4d6209f..00000000000 --- a/sys/gnu/dts/arm/vf610-colibri-eval-v3.dts +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright 2014 Toradex AG - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "vf610-colibri.dtsi" -#include "vf-colibri-eval-v3.dtsi" - -/ { - model = "Toradex Colibri VF61 on Colibri Evaluation Board"; - compatible = "toradex,vf610-colibri_vf61-on-eval", "toradex,vf610-colibri_vf61", "fsl,vf610"; -}; diff --git a/sys/gnu/dts/arm/vf610-colibri.dtsi b/sys/gnu/dts/arm/vf610-colibri.dtsi deleted file mode 100644 index 05c9a39509b..00000000000 --- a/sys/gnu/dts/arm/vf610-colibri.dtsi +++ /dev/null @@ -1,58 +0,0 @@ -/* - * Copyright 2014 Toradex AG - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "vf610.dtsi" -#include "vf-colibri.dtsi" - -/ { - model = "Toradex Colibri VF61 COM"; - compatible = "toradex,vf610-colibri_vf61", "fsl,vf610"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x10000000>; - }; -}; - -&nfc { - assigned-clocks = <&clks VF610_CLK_NFC>; - assigned-clock-rates = <50000000>; -}; diff --git a/sys/gnu/dts/arm/vf610-cosmic.dts b/sys/gnu/dts/arm/vf610-cosmic.dts deleted file mode 100644 index 703f375d7e2..00000000000 --- a/sys/gnu/dts/arm/vf610-cosmic.dts +++ /dev/null @@ -1,90 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Freescale Semiconductor, Inc. - * Copyright 2013 Linaro Limited - */ - -/dts-v1/; -#include "vf610.dtsi" - -/ { - model = "PHYTEC Cosmic/Cosmic+ Board"; - compatible = "phytec,vf610-cosmic", "fsl,vf610"; - - chosen { - bootargs = "console=ttyLP1,115200"; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x10000000>; - }; - - enet_ext: enet_ext { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <50000000>; - }; -}; - -&clks { - clocks = <&sxosc>, <&fxosc>, <&enet_ext>; - clock-names = "sxosc", "fxosc", "enet_ext"; -}; - -&esdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc1>; - bus-width = <4>; - status = "okay"; -}; - -&fec1 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - status = "okay"; -}; - -&iomuxc { - vf610-cosmic { - pinctrl_esdhc1: esdhc1grp { - fsl,pins = < - VF610_PAD_PTA24__ESDHC1_CLK 0x31ef - VF610_PAD_PTA25__ESDHC1_CMD 0x31ef - VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef - VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef - VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef - VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef - VF610_PAD_PTB28__GPIO_98 0x219d - >; - }; - - pinctrl_fec1: fec1grp { - fsl,pins = < - VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2 - VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3 - VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1 - VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1 - VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1 - VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1 - VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2 - VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2 - VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - VF610_PAD_PTB4__UART1_TX 0x21a2 - VF610_PAD_PTB5__UART1_RX 0x21a1 - >; - }; - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/vf610-pinfunc.h b/sys/gnu/dts/arm/vf610-pinfunc.h deleted file mode 100644 index f1e5a7cf58a..00000000000 --- a/sys/gnu/dts/arm/vf610-pinfunc.h +++ /dev/null @@ -1,806 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - */ - -#ifndef __DTS_VF610_PINFUNC_H -#define __DTS_VF610_PINFUNC_H - -/* - * The pin function ID for VF610 is a tuple of: - * - */ - -#define ALT0 0x0 -#define ALT1 0x1 -#define ALT2 0x2 -#define ALT3 0x3 -#define ALT4 0x4 -#define ALT5 0x5 -#define ALT6 0x6 -#define ALT7 0x7 - - -#define VF610_PAD_PTA6__GPIO_0 0x000 0x000 ALT0 0x0 -#define VF610_PAD_PTA6__RMII_CLKOUT 0x000 0x000 ALT1 0x0 -#define VF610_PAD_PTA6__RMII_CLKIN 0x000 0x2F0 ALT2 0x0 -#define VF610_PAD_PTA6__DCU1_TCON11 0x000 0x000 ALT4 0x0 -#define VF610_PAD_PTA6__DCU1_R2 0x000 0x000 ALT7 0x0 -#define VF610_PAD_PTA8__GPIO_1 0x004 0x000 ALT0 0x0 -#define VF610_PAD_PTA8__TCLK 0x004 0x000 ALT1 0x0 -#define VF610_PAD_PTA8__DCU0_R0 0x004 0x000 ALT4 0x0 -#define VF610_PAD_PTA8__MLB_CLK 0x004 0x354 ALT7 0x0 -#define VF610_PAD_PTA9__GPIO_2 0x008 0x000 ALT0 0x0 -#define VF610_PAD_PTA9__TDI 0x008 0x000 ALT1 0x0 -#define VF610_PAD_PTA9__RMII_CLKOUT 0x008 0x000 ALT2 0x0 -#define VF610_PAD_PTA9__RMII_CLKIN 0x008 0x2F0 ALT3 0x1 -#define VF610_PAD_PTA9__DCU0_R1 0x008 0x000 ALT4 0x0 -#define VF610_PAD_PTA9__WDOG_B 0x008 0x000 ALT6 0x0 -#define VF610_PAD_PTA10__GPIO_3 0x00C 0x000 ALT0 0x0 -#define VF610_PAD_PTA10__TDO 0x00C 0x000 ALT1 0x0 -#define VF610_PAD_PTA10__EXT_AUDIO_MCLK 0x00C 0x2EC ALT2 0x0 -#define VF610_PAD_PTA10__DCU0_G0 0x00C 0x000 ALT4 0x0 -#define VF610_PAD_PTA10__ENET_TS_CLKIN 0x00C 0x2F4 ALT6 0x0 -#define VF610_PAD_PTA10__MLB_SIGNAL 0x00C 0x35C ALT7 0x0 -#define VF610_PAD_PTA11__GPIO_4 0x010 0x000 ALT0 0x0 -#define VF610_PAD_PTA11__TMS 0x010 0x000 ALT1 0x0 -#define VF610_PAD_PTA11__DCU0_G1 0x010 0x000 ALT4 0x0 -#define VF610_PAD_PTA11__MLB_DATA 0x010 0x358 ALT7 0x0 -#define VF610_PAD_PTA12__GPIO_5 0x014 0x000 ALT0 0x0 -#define VF610_PAD_PTA12__TRACECK 0x014 0x000 ALT1 0x0 -#define VF610_PAD_PTA12__EXT_AUDIO_MCLK 0x014 0x2EC ALT2 0x1 -#define VF610_PAD_PTA12__VIU_DATA13 0x014 0x000 ALT6 0x0 -#define VF610_PAD_PTA12__I2C0_SCL 0x014 0x33C ALT7 0x0 -#define VF610_PAD_PTA16__GPIO_6 0x018 0x000 ALT0 0x0 -#define VF610_PAD_PTA16__TRACED0 0x018 0x000 ALT1 0x0 -#define VF610_PAD_PTA16__USB0_VBUS_EN 0x018 0x000 ALT2 0x0 -#define VF610_PAD_PTA16__ADC1_SE0 0x018 0x000 ALT3 0x0 -#define VF610_PAD_PTA16__LCD29 0x018 0x000 ALT4 0x0 -#define VF610_PAD_PTA16__SAI2_TX_BCLK 0x018 0x370 ALT5 0x0 -#define VF610_PAD_PTA16__VIU_DATA14 0x018 0x000 ALT6 0x0 -#define VF610_PAD_PTA16__I2C0_SDA 0x018 0x340 ALT7 0x0 -#define VF610_PAD_PTA17__GPIO_7 0x01C 0x000 ALT0 0x0 -#define VF610_PAD_PTA17__TRACED1 0x01C 0x000 ALT1 0x0 -#define VF610_PAD_PTA17__USB0_VBUS_OC 0x01C 0x000 ALT2 0x0 -#define VF610_PAD_PTA17__ADC1_SE1 0x01C 0x000 ALT3 0x0 -#define VF610_PAD_PTA17__LCD30 0x01C 0x000 ALT4 0x0 -#define VF610_PAD_PTA17__USB0_SOF_PULSE 0x01C 0x000 ALT5 0x0 -#define VF610_PAD_PTA17__VIU_DATA15 0x01C 0x000 ALT6 0x0 -#define VF610_PAD_PTA17__I2C1_SCL 0x01C 0x344 ALT7 0x0 -#define VF610_PAD_PTA18__GPIO_8 0x020 0x000 ALT0 0x0 -#define VF610_PAD_PTA18__TRACED2 0x020 0x000 ALT1 0x0 -#define VF610_PAD_PTA18__ADC0_SE0 0x020 0x000 ALT2 0x0 -#define VF610_PAD_PTA18__FTM1_QD_PHA 0x020 0x334 ALT3 0x0 -#define VF610_PAD_PTA18__LCD31 0x020 0x000 ALT4 0x0 -#define VF610_PAD_PTA18__SAI2_TX_DATA 0x020 0x000 ALT5 0x0 -#define VF610_PAD_PTA18__VIU_DATA16 0x020 0x000 ALT6 0x0 -#define VF610_PAD_PTA18__I2C1_SDA 0x020 0x348 ALT7 0x0 -#define VF610_PAD_PTA19__GPIO_9 0x024 0x000 ALT0 0x0 -#define VF610_PAD_PTA19__TRACED3 0x024 0x000 ALT1 0x0 -#define VF610_PAD_PTA19__ADC0_SE1 0x024 0x000 ALT2 0x0 -#define VF610_PAD_PTA19__FTM1_QD_PHB 0x024 0x338 ALT3 0x0 -#define VF610_PAD_PTA19__LCD32 0x024 0x000 ALT4 0x0 -#define VF610_PAD_PTA19__SAI2_TX_SYNC 0x024 0x000 ALT5 0x0 -#define VF610_PAD_PTA19__VIU_DATA17 0x024 0x000 ALT6 0x0 -#define VF610_PAD_PTA19__QSPI1_A_QSCK 0x024 0x374 ALT7 0x0 -#define VF610_PAD_PTA20__GPIO_10 0x028 0x000 ALT0 0x0 -#define VF610_PAD_PTA20__TRACED4 0x028 0x000 ALT1 0x0 -#define VF610_PAD_PTA20__LCD33 0x028 0x000 ALT4 0x0 -#define VF610_PAD_PTA20__UART3_TX 0x028 0x394 ALT6 0x0 -#define VF610_PAD_PTA20__DCU1_HSYNC 0x028 0x000 ALT7 0x0 -#define VF610_PAD_PTA21__GPIO_11 0x02C 0x000 ALT0 0x0 -#define VF610_PAD_PTA21__TRACED5 0x02C 0x000 ALT1 0x0 -#define VF610_PAD_PTA21__SAI2_RX_BCLK 0x02C 0x364 ALT5 0x0 -#define VF610_PAD_PTA21__UART3_RX 0x02C 0x390 ALT6 0x0 -#define VF610_PAD_PTA21__DCU1_VSYNC 0x02C 0x000 ALT7 0x0 -#define VF610_PAD_PTA22__GPIO_12 0x030 0x000 ALT0 0x0 -#define VF610_PAD_PTA22__TRACED6 0x030 0x000 ALT1 0x0 -#define VF610_PAD_PTA22__SAI2_RX_DATA 0x030 0x368 ALT5 0x0 -#define VF610_PAD_PTA22__I2C2_SCL 0x030 0x34C ALT6 0x0 -#define VF610_PAD_PTA22__DCU1_TAG 0x030 0x000 ALT7 0x0 -#define VF610_PAD_PTA23__GPIO_13 0x034 0x000 ALT0 0x0 -#define VF610_PAD_PTA23__TRACED7 0x034 0x000 ALT1 0x0 -#define VF610_PAD_PTA23__SAI2_RX_SYNC 0x034 0x36C ALT5 0x0 -#define VF610_PAD_PTA23__I2C2_SDA 0x034 0x350 ALT6 0x0 -#define VF610_PAD_PTA23__DCU1_DE 0x034 0x000 ALT7 0x0 -#define VF610_PAD_PTA24__GPIO_14 0x038 0x000 ALT0 0x0 -#define VF610_PAD_PTA24__TRACED8 0x038 0x000 ALT1 0x0 -#define VF610_PAD_PTA24__USB1_VBUS_EN 0x038 0x000 ALT2 0x0 -#define VF610_PAD_PTA24__ESDHC1_CLK 0x038 0x000 ALT5 0x0 -#define VF610_PAD_PTA24__DCU1_TCON4 0x038 0x000 ALT6 0x0 -#define VF610_PAD_PTA24__DDR_TEST_PAD_CTRL 0x038 0x000 ALT7 0x0 -#define VF610_PAD_PTA25__GPIO_15 0x03C 0x000 ALT0 0x0 -#define VF610_PAD_PTA25__TRACED9 0x03C 0x000 ALT1 0x0 -#define VF610_PAD_PTA25__USB1_VBUS_OC 0x03C 0x000 ALT2 0x0 -#define VF610_PAD_PTA25__ESDHC1_CMD 0x03C 0x000 ALT5 0x0 -#define VF610_PAD_PTA25__DCU1_TCON5 0x03C 0x000 ALT6 0x0 -#define VF610_PAD_PTA26__GPIO_16 0x040 0x000 ALT0 0x0 -#define VF610_PAD_PTA26__TRACED10 0x040 0x000 ALT1 0x0 -#define VF610_PAD_PTA26__SAI3_TX_BCLK 0x040 0x000 ALT2 0x0 -#define VF610_PAD_PTA26__ESDHC1_DAT0 0x040 0x000 ALT5 0x0 -#define VF610_PAD_PTA26__DCU1_TCON6 0x040 0x000 ALT6 0x0 -#define VF610_PAD_PTA27__GPIO_17 0x044 0x000 ALT0 0x0 -#define VF610_PAD_PTA27__TRACED11 0x044 0x000 ALT1 0x0 -#define VF610_PAD_PTA27__SAI3_RX_BCLK 0x044 0x000 ALT2 0x0 -#define VF610_PAD_PTA27__ESDHC1_DAT1 0x044 0x000 ALT5 0x0 -#define VF610_PAD_PTA27__DCU1_TCON7 0x044 0x000 ALT6 0x0 -#define VF610_PAD_PTA28__GPIO_18 0x048 0x000 ALT0 0x0 -#define VF610_PAD_PTA28__TRACED12 0x048 0x000 ALT1 0x0 -#define VF610_PAD_PTA28__SAI3_RX_DATA 0x048 0x000 ALT2 0x0 -#define VF610_PAD_PTA28__ENET1_1588_TMR0 0x048 0x000 ALT3 0x0 -#define VF610_PAD_PTA28__UART4_TX 0x048 0x000 ALT4 0x0 -#define VF610_PAD_PTA28__ESDHC1_DATA2 0x048 0x000 ALT5 0x0 -#define VF610_PAD_PTA28__DCU1_TCON8 0x048 0x000 ALT6 0x0 -#define VF610_PAD_PTA29__GPIO_19 0x04C 0x000 ALT0 0x0 -#define VF610_PAD_PTA29__TRACED13 0x04C 0x000 ALT1 0x0 -#define VF610_PAD_PTA29__SAI3_TX_DATA 0x04C 0x000 ALT2 0x0 -#define VF610_PAD_PTA29__ENET1_1588_TMR1 0x04C 0x000 ALT3 0x0 -#define VF610_PAD_PTA29__UART4_RX 0x04C 0x000 ALT4 0x0 -#define VF610_PAD_PTA29__ESDHC1_DAT3 0x04C 0x000 ALT5 0x0 -#define VF610_PAD_PTA29__DCU1_TCON9 0x04C 0x000 ALT6 0x0 -#define VF610_PAD_PTA30__GPIO_20 0x050 0x000 ALT0 0x0 -#define VF610_PAD_PTA30__TRACED14 0x050 0x000 ALT1 0x0 -#define VF610_PAD_PTA30__SAI3_RX_SYNC 0x050 0x000 ALT2 0x0 -#define VF610_PAD_PTA30__ENET1_1588_TMR2 0x050 0x000 ALT3 0x0 -#define VF610_PAD_PTA30__UART4_RTS 0x050 0x000 ALT4 0x0 -#define VF610_PAD_PTA30__I2C3_SCL 0x050 0x000 ALT5 0x0 -#define VF610_PAD_PTA30__UART3_TX 0x050 0x394 ALT7 0x1 -#define VF610_PAD_PTA31__GPIO_21 0x054 0x000 ALT0 0x0 -#define VF610_PAD_PTA31__TRACED15 0x054 0x000 ALT1 0x0 -#define VF610_PAD_PTA31__SAI3_TX_SYNC 0x054 0x000 ALT2 0x0 -#define VF610_PAD_PTA31__ENET1_1588_TMR3 0x054 0x000 ALT3 0x0 -#define VF610_PAD_PTA31__UART4_CTS 0x054 0x000 ALT4 0x0 -#define VF610_PAD_PTA31__I2C3_SDA 0x054 0x000 ALT5 0x0 -#define VF610_PAD_PTA31__UART3_RX 0x054 0x390 ALT7 0x1 -#define VF610_PAD_PTB0__GPIO_22 0x058 0x000 ALT0 0x0 -#define VF610_PAD_PTB0__FTM0_CH0 0x058 0x000 ALT1 0x0 -#define VF610_PAD_PTB0__ADC0_SE2 0x058 0x000 ALT2 0x0 -#define VF610_PAD_PTB0__TRACE_CTL 0x058 0x000 ALT3 0x0 -#define VF610_PAD_PTB0__LCD34 0x058 0x000 ALT4 0x0 -#define VF610_PAD_PTB0__SAI2_RX_BCLK 0x058 0x364 ALT5 0x1 -#define VF610_PAD_PTB0__VIU_DATA18 0x058 0x000 ALT6 0x0 -#define VF610_PAD_PTB0__QSPI1_A_QPCS0 0x058 0x000 ALT7 0x0 -#define VF610_PAD_PTB1__GPIO_23 0x05C 0x000 ALT0 0x0 -#define VF610_PAD_PTB1__FTM0_CH1 0x05C 0x000 ALT1 0x0 -#define VF610_PAD_PTB1__ADC0_SE3 0x05C 0x000 ALT2 0x0 -#define VF610_PAD_PTB1__SRC_RCON30 0x05C 0x000 ALT3 0x0 -#define VF610_PAD_PTB1__LCD35 0x05C 0x000 ALT4 0x0 -#define VF610_PAD_PTB1__SAI2_RX_DATA 0x05C 0x368 ALT5 0x1 -#define VF610_PAD_PTB1__VIU_DATA19 0x05C 0x000 ALT6 0x0 -#define VF610_PAD_PTB1__QSPI1_A_DATA3 0x05C 0x000 ALT7 0x0 -#define VF610_PAD_PTB2__GPIO_24 0x060 0x000 ALT0 0x0 -#define VF610_PAD_PTB2__FTM0_CH2 0x060 0x000 ALT1 0x0 -#define VF610_PAD_PTB2__ADC1_SE2 0x060 0x000 ALT2 0x0 -#define VF610_PAD_PTB2__SRC_RCON31 0x060 0x000 ALT3 0x0 -#define VF610_PAD_PTB2__LCD36 0x060 0x000 ALT4 0x0 -#define VF610_PAD_PTB2__SAI2_RX_SYNC 0x060 0x36C ALT5 0x1 -#define VF610_PAD_PTB2__VIDEO_IN0_DATA20 0x060 0x000 ALT6 0x0 -#define VF610_PAD_PTB2__QSPI1_A_DATA2 0x060 0x000 ALT7 0x0 -#define VF610_PAD_PTB3__GPIO_25 0x064 0x000 ALT0 0x0 -#define VF610_PAD_PTB3__FTM0_CH3 0x064 0x000 ALT1 0x0 -#define VF610_PAD_PTB3__ADC1_SE3 0x064 0x000 ALT2 0x0 -#define VF610_PAD_PTB3__PDB_EXTRIG 0x064 0x000 ALT3 0x0 -#define VF610_PAD_PTB3__LCD37 0x064 0x000 ALT4 0x0 -#define VF610_PAD_PTB3__VIU_DATA21 0x064 0x000 ALT6 0x0 -#define VF610_PAD_PTB3__QSPI1_A_DATA1 0x064 0x000 ALT7 0x0 -#define VF610_PAD_PTB4__GPIO_26 0x068 0x000 ALT0 0x0 -#define VF610_PAD_PTB4__FTM0_CH4 0x068 0x000 ALT1 0x0 -#define VF610_PAD_PTB4__UART1_TX 0x068 0x380 ALT2 0x0 -#define VF610_PAD_PTB4__ADC0_SE4 0x068 0x000 ALT3 0x0 -#define VF610_PAD_PTB4__LCD38 0x068 0x000 ALT4 0x0 -#define VF610_PAD_PTB4__VIU_FID 0x068 0x3A8 ALT5 0x0 -#define VF610_PAD_PTB4__VIU_DATA22 0x068 0x000 ALT6 0x0 -#define VF610_PAD_PTB4__QSPI1_A_DATA0 0x068 0x000 ALT7 0x0 -#define VF610_PAD_PTB5__GPIO_27 0x06C 0x000 ALT0 0x0 -#define VF610_PAD_PTB5__FTM0_CH5 0x06C 0x000 ALT1 0x0 -#define VF610_PAD_PTB5__UART1_RX 0x06C 0x37C ALT2 0x0 -#define VF610_PAD_PTB5__ADC1_SE4 0x06C 0x000 ALT3 0x0 -#define VF610_PAD_PTB5__LCD39 0x06C 0x000 ALT4 0x0 -#define VF610_PAD_PTB5__VIU_DE 0x06C 0x3A4 ALT5 0x0 -#define VF610_PAD_PTB5__QSPI1_A_DQS 0x06C 0x000 ALT7 0x0 -#define VF610_PAD_PTB6__GPIO_28 0x070 0x000 ALT0 0x0 -#define VF610_PAD_PTB6__FTM0_CH6 0x070 0x000 ALT1 0x0 -#define VF610_PAD_PTB6__UART1_RTS 0x070 0x000 ALT2 0x0 -#define VF610_PAD_PTB6__QSPI0_QPCS1_A 0x070 0x000 ALT3 0x0 -#define VF610_PAD_PTB6__LCD_LCD40 0x070 0x000 ALT4 0x0 -#define VF610_PAD_PTB6__FB_CLKOUT 0x070 0x000 ALT5 0x0 -#define VF610_PAD_PTB6__VIU_HSYNC 0x070 0x000 ALT6 0x0 -#define VF610_PAD_PTB6__UART2_TX 0x070 0x38C ALT7 0x0 -#define VF610_PAD_PTB7__GPIO_29 0x074 0x000 ALT0 0x0 -#define VF610_PAD_PTB7__FTM0_CH7 0x074 0x000 ALT1 0x0 -#define VF610_PAD_PTB7__UART1_CTS 0x074 0x378 ALT2 0x0 -#define VF610_PAD_PTB7__QSPI0_B_QPCS1 0x074 0x000 ALT3 0x0 -#define VF610_PAD_PTB7__LCD41 0x074 0x000 ALT4 0x0 -#define VF610_PAD_PTB7__VIU_VSYNC 0x074 0x000 ALT6 0x0 -#define VF610_PAD_PTB7__UART2_RX 0x074 0x388 ALT7 0x0 -#define VF610_PAD_PTB8__GPIO_30 0x078 0x000 ALT0 0x0 -#define VF610_PAD_PTB8__FTM1_CH0 0x078 0x32C ALT1 0x0 -#define VF610_PAD_PTB8__FTM1_QD_PHA 0x078 0x334 ALT3 0x1 -#define VF610_PAD_PTB8__VIU_DE 0x078 0x3A4 ALT5 0x1 -#define VF610_PAD_PTB8__DCU1_R6 0x078 0x000 ALT7 0x0 -#define VF610_PAD_PTB9__GPIO_31 0x07C 0x000 ALT0 0x0 -#define VF610_PAD_PTB9__FTM1_CH1 0x07C 0x330 ALT1 0x0 -#define VF610_PAD_PTB9__FTM1_QD_PHB 0x07C 0x338 ALT3 0x1 -#define VF610_PAD_PTB9__DCU1_R7 0x07C 0x000 ALT7 0x0 -#define VF610_PAD_PTB10__GPIO_32 0x080 0x000 ALT0 0x0 -#define VF610_PAD_PTB10__UART0_TX 0x080 0x000 ALT1 0x0 -#define VF610_PAD_PTB10__DCU0_TCON4 0x080 0x000 ALT4 0x0 -#define VF610_PAD_PTB10__VIU_DE 0x080 0x3A4 ALT5 0x2 -#define VF610_PAD_PTB10__CKO1 0x080 0x000 ALT6 0x0 -#define VF610_PAD_PTB10__ENET_TS_CLKIN 0x080 0x2F4 ALT7 0x1 -#define VF610_PAD_PTB11__GPIO_33 0x084 0x000 ALT0 0x0 -#define VF610_PAD_PTB11__UART0_RX 0x084 0x000 ALT1 0x0 -#define VF610_PAD_PTB11__DCU0_TCON5 0x084 0x000 ALT4 0x0 -#define VF610_PAD_PTB11__SNVS_ALARM_OUT_B 0x084 0x000 ALT5 0x0 -#define VF610_PAD_PTB11__CKO2 0x084 0x000 ALT6 0x0 -#define VF610_PAD_PTB11_ENET0_1588_TMR0 0x084 0x304 ALT7 0x0 -#define VF610_PAD_PTB12__GPIO_34 0x088 0x000 ALT0 0x0 -#define VF610_PAD_PTB12__UART0_RTS 0x088 0x000 ALT1 0x0 -#define VF610_PAD_PTB12__DSPI0_CS5 0x088 0x000 ALT3 0x0 -#define VF610_PAD_PTB12__DCU0_TCON6 0x088 0x000 ALT4 0x0 -#define VF610_PAD_PTB12__FB_AD1 0x088 0x000 ALT5 0x0 -#define VF610_PAD_PTB12__NMI 0x088 0x000 ALT6 0x0 -#define VF610_PAD_PTB12__ENET0_1588_TMR1 0x088 0x308 ALT7 0x0 -#define VF610_PAD_PTB13__GPIO_35 0x08C 0x000 ALT0 0x0 -#define VF610_PAD_PTB13__UART0_CTS 0x08C 0x000 ALT1 0x0 -#define VF610_PAD_PTB13__DSPI0_CS4 0x08C 0x000 ALT3 0x0 -#define VF610_PAD_PTB13__DCU0_TCON7 0x08C 0x000 ALT4 0x0 -#define VF610_PAD_PTB13__FB_AD0 0x08C 0x000 ALT5 0x0 -#define VF610_PAD_PTB13__TRACE_CTL 0x08C 0x000 ALT6 0x0 -#define VF610_PAD_PTB14__GPIO_36 0x090 0x000 ALT0 0x0 -#define VF610_PAD_PTB14__CAN0_RX 0x090 0x000 ALT1 0x0 -#define VF610_PAD_PTB14__I2C0_SCL 0x090 0x33C ALT2 0x1 -#define VF610_PAD_PTB14__DCU0_TCON8 0x090 0x000 ALT4 0x0 -#define VF610_PAD_PTB14__DCU1_PCLK 0x090 0x000 ALT7 0x0 -#define VF610_PAD_PTB15__GPIO_37 0x094 0x000 ALT0 0x0 -#define VF610_PAD_PTB15__CAN0_TX 0x094 0x000 ALT1 0x0 -#define VF610_PAD_PTB15__I2C0_SDA 0x094 0x340 ALT2 0x1 -#define VF610_PAD_PTB15__DCU0_TCON9 0x094 0x000 ALT4 0x0 -#define VF610_PAD_PTB15__VIU_PIX_CLK 0x094 0x3AC ALT7 0x0 -#define VF610_PAD_PTB16__GPIO_38 0x098 0x000 ALT0 0x0 -#define VF610_PAD_PTB16__CAN1_RX 0x098 0x000 ALT1 0x0 -#define VF610_PAD_PTB16__I2C1_SCL 0x098 0x344 ALT2 0x1 -#define VF610_PAD_PTB16__DCU0_TCON10 0x098 0x000 ALT4 0x0 -#define VF610_PAD_PTB17__GPIO_39 0x09C 0x000 ALT0 0x0 -#define VF610_PAD_PTB17__CAN1_TX 0x09C 0x000 ALT1 0x0 -#define VF610_PAD_PTB17__I2C1_SDA 0x09C 0x348 ALT2 0x1 -#define VF610_PAD_PTB17__DCU0_TCON11 0x09C 0x000 ALT4 0x0 -#define VF610_PAD_PTB18__GPIO_40 0x0A0 0x000 ALT0 0x0 -#define VF610_PAD_PTB18__DSPI0_CS1 0x0A0 0x000 ALT1 0x0 -#define VF610_PAD_PTB18__EXT_AUDIO_MCLK 0x0A0 0x2EC ALT2 0x2 -#define VF610_PAD_PTB18__VIU_DATA9 0x0A0 0x000 ALT6 0x0 -#define VF610_PAD_PTB19__GPIO_41 0x0A4 0x000 ALT0 0x0 -#define VF610_PAD_PTB19__DSPI0_CS0 0x0A4 0x000 ALT1 0x0 -#define VF610_PAD_PTB19__VIU_DATA10 0x0A4 0x000 ALT6 0x0 -#define VF610_PAD_PTB20__GPIO_42 0x0A8 0x000 ALT0 0x0 -#define VF610_PAD_PTB20__DSPI0_SIN 0x0A8 0x000 ALT1 0x0 -#define VF610_PAD_PTB20__LCD42 0x0A8 0x000 ALT4 0x0 -#define VF610_PAD_PTB20__VIU_DATA11 0x0A8 0x000 ALT6 0x0 -#define VF610_PAD_PTB21__GPIO_43 0x0AC 0x000 ALT0 0x0 -#define VF610_PAD_PTB21__DSPI0_SOUT 0x0AC 0x000 ALT1 0x0 -#define VF610_PAD_PTB21__LCD43 0x0AC 0x000 ALT4 0x0 -#define VF610_PAD_PTB21__VIU_DATA12 0x0AC 0x000 ALT6 0x0 -#define VF610_PAD_PTB21__DCU1_PCLK 0x0AC 0x000 ALT7 0x0 -#define VF610_PAD_PTB22__GPIO_44 0x0B0 0x000 ALT0 0x0 -#define VF610_PAD_PTB22__DSPI0_SCK 0x0B0 0x000 ALT1 0x0 -#define VF610_PAD_PTB22__VLCD 0x0B0 0x000 ALT4 0x0 -#define VF610_PAD_PTB22__VIU_FID 0x0B0 0x3A8 ALT5 0x1 -#define VF610_PAD_PTC0__GPIO_45 0x0B4 0x000 ALT0 0x0 -#define VF610_PAD_PTC0__ENET_RMII0_MDC 0x0B4 0x000 ALT1 0x0 -#define VF610_PAD_PTC0__FTM1_CH0 0x0B4 0x32C ALT2 0x1 -#define VF610_PAD_PTC0__DSPI0_CS3 0x0B4 0x000 ALT3 0x0 -#define VF610_PAD_PTC0__ESAI_SCKT 0x0B4 0x310 ALT4 0x0 -#define VF610_PAD_PTC0__ESDHC0_CLK 0x0B4 0x000 ALT5 0x0 -#define VF610_PAD_PTC0__VIU_DATA0 0x0B4 0x000 ALT6 0x0 -#define VF610_PAD_PTC0__SRC_RCON18 0x0B4 0x398 ALT7 0x0 -#define VF610_PAD_PTC1__GPIO_46 0x0B8 0x000 ALT0 0x0 -#define VF610_PAD_PTC1__ENET_RMII0_MDIO 0x0B8 0x000 ALT1 0x0 -#define VF610_PAD_PTC1__FTM1_CH1 0x0B8 0x330 ALT2 0x1 -#define VF610_PAD_PTC1__DSPI0_CS2 0x0B8 0x000 ALT3 0x0 -#define VF610_PAD_PTC1__ESAI_FST 0x0B8 0x30C ALT4 0x0 -#define VF610_PAD_PTC1__ESDHC0_CMD 0x0B8 0x000 ALT5 0x0 -#define VF610_PAD_PTC1__VIU_DATA1 0x0B8 0x000 ALT6 0x0 -#define VF610_PAD_PTC1__SRC_RCON19 0x0B8 0x39C ALT7 0x0 -#define VF610_PAD_PTC2__GPIO_47 0x0BC 0x000 ALT0 0x0 -#define VF610_PAD_PTC2__ENET_RMII0_CRS 0x0BC 0x000 ALT1 0x0 -#define VF610_PAD_PTC2__UART1_TX 0x0BC 0x380 ALT2 0x1 -#define VF610_PAD_PTC2__ESAI_SDO0 0x0BC 0x314 ALT4 0x0 -#define VF610_PAD_PTC2__ESDHC0_DAT0 0x0BC 0x000 ALT5 0x0 -#define VF610_PAD_PTC2__VIU_DATA2 0x0BC 0x000 ALT6 0x0 -#define VF610_PAD_PTC2__SRC_RCON20 0x0BC 0x3A0 ALT7 0x0 -#define VF610_PAD_PTC3__GPIO_48 0x0C0 0x000 ALT0 0x0 -#define VF610_PAD_PTC3__ENET_RMII0_RXD1 0x0C0 0x000 ALT1 0x0 -#define VF610_PAD_PTC3__UART1_RX 0x0C0 0x37C ALT2 0x1 -#define VF610_PAD_PTC3__ESAI_SDO1 0x0C0 0x318 ALT4 0x0 -#define VF610_PAD_PTC3__ESDHC0_DAT1 0x0C0 0x000 ALT5 0x0 -#define VF610_PAD_PTC3__VIU_DATA3 0x0C0 0x000 ALT6 0x0 -#define VF610_PAD_PTC3__DCU0_R0 0x0C0 0x000 ALT7 0x0 -#define VF610_PAD_PTC4__GPIO_49 0x0C4 0x000 ALT0 0x0 -#define VF610_PAD_PTC4__ENET_RMII0_RXD0 0x0C4 0x000 ALT1 0x0 -#define VF610_PAD_PTC4__UART1_RTS 0x0C4 0x000 ALT2 0x0 -#define VF610_PAD_PTC4__DSPI1_CS1 0x0C4 0x000 ALT3 0x0 -#define VF610_PAD_PTC4__ESAI_SDO2 0x0C4 0x31C ALT4 0x0 -#define VF610_PAD_PTC4__ESDHC0_DAT2 0x0C4 0x000 ALT5 0x0 -#define VF610_PAD_PTC4__VIU_DATA4 0x0C4 0x000 ALT6 0x0 -#define VF610_PAD_PTC4__DCU0_R1 0x0C4 0x000 ALT7 0x0 -#define VF610_PAD_PTC5__GPIO_50 0x0C8 0x000 ALT0 0x0 -#define VF610_PAD_PTC5__ENET_RMII0_RXER 0x0C8 0x000 ALT1 0x0 -#define VF610_PAD_PTC5__UART1_CTS 0x0C8 0x378 ALT2 0x1 -#define VF610_PAD_PTC5__DSPI1_CS0 0x0C8 0x300 ALT3 0x0 -#define VF610_PAD_PTC5__ESAI_SDO3 0x0C8 0x320 ALT4 0x0 -#define VF610_PAD_PTC5__ESDHC0_DAT3 0x0C8 0x000 ALT5 0x0 -#define VF610_PAD_PTC5__VIU_DATA5 0x0C8 0x000 ALT6 0x0 -#define VF610_PAD_PTC5__DCU0_G0 0x0C8 0x000 ALT7 0x0 -#define VF610_PAD_PTC6__GPIO_51 0x0CC 0x000 ALT0 0x0 -#define VF610_PAD_PTC6__ENET_RMII0_TXD1 0x0CC 0x000 ALT1 0x0 -#define VF610_PAD_PTC6__DSPI1_SIN 0x0CC 0x2FC ALT3 0x0 -#define VF610_PAD_PTC6__ESAI_SDI0 0x0CC 0x328 ALT4 0x0 -#define VF610_PAD_PTC6__ESDHC0_WP 0x0CC 0x000 ALT5 0x0 -#define VF610_PAD_PTC6__VIU_DATA6 0x0CC 0x000 ALT6 0x0 -#define VF610_PAD_PTC6__DCU0_G1 0x0CC 0x000 ALT7 0x0 -#define VF610_PAD_PTC7__GPIO_52 0x0D0 0x000 ALT0 0x0 -#define VF610_PAD_PTC7__ENET_RMII0_TXD0 0x0D0 0x000 ALT1 0x0 -#define VF610_PAD_PTC7__DSPI1_SOUT 0x0D0 0x000 ALT3 0x0 -#define VF610_PAD_PTC7__ESAI_SDI1 0x0D0 0x324 ALT4 0x0 -#define VF610_PAD_PTC7__VIU_DATA7 0x0D0 0x000 ALT6 0x0 -#define VF610_PAD_PTC7__DCU0_B0 0x0D0 0x000 ALT7 0x0 -#define VF610_PAD_PTC8__GPIO_53 0x0D4 0x000 ALT0 0x0 -#define VF610_PAD_PTC8__ENET_RMII0_TXEN 0x0D4 0x000 ALT1 0x0 -#define VF610_PAD_PTC8__DSPI1_SCK 0x0D4 0x2F8 ALT3 0x0 -#define VF610_PAD_PTC8__VIU_DATA8 0x0D4 0x000 ALT6 0x0 -#define VF610_PAD_PTC8__DCU0_B1 0x0D4 0x000 ALT7 0x0 -#define VF610_PAD_PTC9__GPIO_54 0x0D8 0x000 ALT0 0x0 -#define VF610_PAD_PTC9__ENET_RMII1_MDC 0x0D8 0x000 ALT1 0x0 -#define VF610_PAD_PTC9__ESAI_SCKT 0x0D8 0x310 ALT3 0x1 -#define VF610_PAD_PTC9__MLB_CLK 0x0D8 0x354 ALT6 0x1 -#define VF610_PAD_PTC9__DEBUG_OUT0 0x0D8 0x000 ALT7 0x0 -#define VF610_PAD_PTC10__GPIO_55 0x0DC 0x000 ALT0 0x0 -#define VF610_PAD_PTC10__ENET_RMII1_MDIO 0x0DC 0x000 ALT1 0x0 -#define VF610_PAD_PTC10__ESAI_FST 0x0DC 0x30C ALT3 0x1 -#define VF610_PAD_PTC10__MLB_SIGNAL 0x0DC 0x35C ALT6 0x1 -#define VF610_PAD_PTC10__DEBUG_OUT1 0x0DC 0x000 ALT7 0x0 -#define VF610_PAD_PTC11__GPIO_56 0x0E0 0x000 ALT0 0x0 -#define VF610_PAD_PTC11__ENET_RMII1_CRS 0x0E0 0x000 ALT1 0x0 -#define VF610_PAD_PTC11__ESAI_SDO0 0x0E0 0x314 ALT3 0x1 -#define VF610_PAD_PTC11__MLB_DATA 0x0E0 0x358 ALT6 0x1 -#define VF610_PAD_PTC11__DEBUG_OUT 0x0E0 0x000 ALT7 0x0 -#define VF610_PAD_PTC12__GPIO_57 0x0E4 0x000 ALT0 0x0 -#define VF610_PAD_PTC12__ENET_RMII1_RXD1 0x0E4 0x000 ALT1 0x0 -#define VF610_PAD_PTC12__ESAI_SDO1 0x0E4 0x318 ALT3 0x1 -#define VF610_PAD_PTC12__SAI2_TX_BCLK 0x0E4 0x370 ALT5 0x1 -#define VF610_PAD_PTC12__DEBUG_OUT3 0x0E4 0x000 ALT7 0x0 -#define VF610_PAD_PTC13__GPIO_58 0x0E8 0x000 ALT0 0x0 -#define VF610_PAD_PTC13__ENET_RMII1_RXD0 0x0E8 0x000 ALT1 0x0 -#define VF610_PAD_PTC13__ESAI_SDO2 0x0E8 0x31C ALT3 0x1 -#define VF610_PAD_PTC13__SAI2_RX_BCLK 0x0E8 0x364 ALT5 0x2 -#define VF610_PAD_PTC13__DEBUG_OUT4 0x0E8 0x000 ALT7 0x0 -#define VF610_PAD_PTC14__GPIO_59 0x0EC 0x000 ALT0 0x0 -#define VF610_PAD_PTC14__ENET_RMII1_RXER 0x0EC 0x000 ALT1 0x0 -#define VF610_PAD_PTC14__ESAI_SDO3 0x0EC 0x320 ALT3 0x1 -#define VF610_PAD_PTC14__UART5_TX 0x0EC 0x000 ALT4 0x0 -#define VF610_PAD_PTC14__SAI2_RX_DATA 0x0EC 0x368 ALT5 0x2 -#define VF610_PAD_PTC14__ADC0_SE6 0x0EC 0x000 ALT6 0x0 -#define VF610_PAD_PTC14__DEBUG_OUT5 0x0EC 0x000 ALT7 0x0 -#define VF610_PAD_PTC15__GPIO_60 0x0F0 0x000 ALT0 0x0 -#define VF610_PAD_PTC15__ENET_RMII1_TXD1 0x0F0 0x000 ALT1 0x0 -#define VF610_PAD_PTC15__ESAI_SDI0 0x0F0 0x328 ALT3 0x1 -#define VF610_PAD_PTC15__UART5_RX 0x0F0 0x000 ALT4 0x0 -#define VF610_PAD_PTC15__SAI2_TX_DATA 0x0F0 0x000 ALT5 0x0 -#define VF610_PAD_PTC15__ADC0_SE7 0x0F0 0x000 ALT6 0x0 -#define VF610_PAD_PTC15__DEBUG_OUT6 0x0F0 0x000 ALT7 0x0 -#define VF610_PAD_PTC16__GPIO_61 0x0F4 0x000 ALT0 0x0 -#define VF610_PAD_PTC16__ENET_RMII1_TXD0 0x0F4 0x000 ALT1 0x0 -#define VF610_PAD_PTC16__ESAI_SDI1 0x0F4 0x324 ALT3 0x1 -#define VF610_PAD_PTC16__UART5_RTS 0x0F4 0x000 ALT4 0x0 -#define VF610_PAD_PTC16__SAI2_RX_SYNC 0x0F4 0x36C ALT5 0x2 -#define VF610_PAD_PTC16__ADC1_SE6 0x0F4 0x000 ALT6 0x0 -#define VF610_PAD_PTC16__DEBUG_OUT7 0x0F4 0x000 ALT7 0x0 -#define VF610_PAD_PTC17__GPIO_62 0x0F8 0x000 ALT0 0x0 -#define VF610_PAD_PTC17__ENET_RMII1_TXEN 0x0F8 0x000 ALT1 0x0 -#define VF610_PAD_PTC17__ADC1_SE7 0x0F8 0x000 ALT3 0x0 -#define VF610_PAD_PTC17__UART5_CTS 0x0F8 0x000 ALT4 0x0 -#define VF610_PAD_PTC17__SAI2_TX_SYNC 0x0F8 0x374 ALT5 0x1 -#define VF610_PAD_PTC17__USB1_SOF_PULSE 0x0F8 0x000 ALT6 0x0 -#define VF610_PAD_PTC17__DEBUG_OUT8 0x0F8 0x000 ALT7 0x0 -#define VF610_PAD_PTD31__GPIO_63 0x0FC 0x000 ALT0 0x0 -#define VF610_PAD_PTD31__FB_AD31 0x0FC 0x000 ALT1 0x0 -#define VF610_PAD_PTD31__NF_IO15 0x0FC 0x000 ALT2 0x0 -#define VF610_PAD_PTD31__FTM3_CH0 0x0FC 0x000 ALT4 0x0 -#define VF610_PAD_PTD31__DSPI2_CS1 0x0FC 0x000 ALT5 0x0 -#define VF610_PAD_PTD31__DEBUG_OUT9 0x0FC 0x000 ALT7 0x0 -#define VF610_PAD_PTD30__GPIO_64 0x100 0x000 ALT0 0x0 -#define VF610_PAD_PTD30__FB_AD30 0x100 0x000 ALT1 0x0 -#define VF610_PAD_PTD30__NF_IO14 0x100 0x000 ALT2 0x0 -#define VF610_PAD_PTD30__FTM3_CH1 0x100 0x000 ALT4 0x0 -#define VF610_PAD_PTD30__DSPI2_CS0 0x100 0x000 ALT5 0x0 -#define VF610_PAD_PTD30__DEBUG_OUT10 0x100 0x000 ALT7 0x0 -#define VF610_PAD_PTD29__GPIO_65 0x104 0x000 ALT0 0x0 -#define VF610_PAD_PTD29__FB_AD29 0x104 0x000 ALT1 0x0 -#define VF610_PAD_PTD29__NF_IO13 0x104 0x000 ALT2 0x0 -#define VF610_PAD_PTD29__FTM3_CH2 0x104 0x000 ALT4 0x0 -#define VF610_PAD_PTD29__DSPI2_SIN 0x104 0x000 ALT5 0x0 -#define VF610_PAD_PTD29__DEBUG_OUT11 0x104 0x000 ALT7 0x0 -#define VF610_PAD_PTD28__GPIO_66 0x108 0x000 ALT0 0x0 -#define VF610_PAD_PTD28__FB_AD28 0x108 0x000 ALT1 0x0 -#define VF610_PAD_PTD28__NF_IO12 0x108 0x000 ALT2 0x0 -#define VF610_PAD_PTD28__I2C2_SCL 0x108 0x34C ALT3 0x1 -#define VF610_PAD_PTD28__FTM3_CH3 0x108 0x000 ALT4 0x0 -#define VF610_PAD_PTD28__DSPI2_SOUT 0x108 0x000 ALT5 0x0 -#define VF610_PAD_PTD28__DEBUG_OUT12 0x108 0x000 ALT7 0x0 -#define VF610_PAD_PTD27__GPIO_67 0x10C 0x000 ALT0 0x0 -#define VF610_PAD_PTD27__FB_AD27 0x10C 0x000 ALT1 0x0 -#define VF610_PAD_PTD27__NF_IO11 0x10C 0x000 ALT2 0x0 -#define VF610_PAD_PTD27__I2C2_SDA 0x10C 0x350 ALT3 0x1 -#define VF610_PAD_PTD27__FTM3_CH4 0x10C 0x000 ALT4 0x0 -#define VF610_PAD_PTD27__DSPI2_SCK 0x10C 0x000 ALT5 0x0 -#define VF610_PAD_PTD27__DEBUG_OUT13 0x10C 0x000 ALT7 0x0 -#define VF610_PAD_PTD26__GPIO_68 0x110 0x000 ALT0 0x0 -#define VF610_PAD_PTD26__FB_AD26 0x110 0x000 ALT1 0x0 -#define VF610_PAD_PTD26__NF_IO10 0x110 0x000 ALT2 0x0 -#define VF610_PAD_PTD26__FTM3_CH5 0x110 0x000 ALT4 0x0 -#define VF610_PAD_PTD26__ESDHC1_WP 0x110 0x000 ALT5 0x0 -#define VF610_PAD_PTD26__DEBUG_OUT14 0x110 0x000 ALT7 0x0 -#define VF610_PAD_PTD25__GPIO_69 0x114 0x000 ALT0 0x0 -#define VF610_PAD_PTD25__FB_AD25 0x114 0x000 ALT1 0x0 -#define VF610_PAD_PTD25__NF_IO9 0x114 0x000 ALT2 0x0 -#define VF610_PAD_PTD25__FTM3_CH6 0x114 0x000 ALT4 0x0 -#define VF610_PAD_PTD25__DEBUG_OUT15 0x114 0x000 ALT7 0x0 -#define VF610_PAD_PTD24__GPIO_70 0x118 0x000 ALT0 0x0 -#define VF610_PAD_PTD24__FB_AD24 0x118 0x000 ALT1 0x0 -#define VF610_PAD_PTD24__NF_IO8 0x118 0x000 ALT2 0x0 -#define VF610_PAD_PTD24__FTM3_CH7 0x118 0x000 ALT4 0x0 -#define VF610_PAD_PTD24__DEBUG_OUT16 0x118 0x000 ALT7 0x0 -#define VF610_PAD_PTD23__GPIO_71 0x11C 0x000 ALT0 0x0 -#define VF610_PAD_PTD23__FB_AD23 0x11C 0x000 ALT1 0x0 -#define VF610_PAD_PTD23__NF_IO7 0x11C 0x000 ALT2 0x0 -#define VF610_PAD_PTD23__FTM2_CH0 0x11C 0x000 ALT3 0x0 -#define VF610_PAD_PTD23__ENET0_1588_TMR0 0x11C 0x304 ALT4 0x1 -#define VF610_PAD_PTD23__ESDHC0_DAT4 0x11C 0x000 ALT5 0x0 -#define VF610_PAD_PTD23__UART2_TX 0x11C 0x38C ALT6 0x1 -#define VF610_PAD_PTD23__DCU1_R3 0x11C 0x000 ALT7 0x0 -#define VF610_PAD_PTD22__GPIO_72 0x120 0x000 ALT0 0x0 -#define VF610_PAD_PTD22__FB_AD22 0x120 0x000 ALT1 0x0 -#define VF610_PAD_PTD22__NF_IO6 0x120 0x000 ALT2 0x0 -#define VF610_PAD_PTD22__FTM2_CH1 0x120 0x000 ALT3 0x0 -#define VF610_PAD_PTD22__ENET0_1588_TMR1 0x120 0x308 ALT4 0x1 -#define VF610_PAD_PTD22__ESDHC0_DAT5 0x120 0x000 ALT5 0x0 -#define VF610_PAD_PTD22__UART2_RX 0x120 0x388 ALT6 0x1 -#define VF610_PAD_PTD22__DCU1_R4 0x120 0x000 ALT7 0x0 -#define VF610_PAD_PTD21__GPIO_73 0x124 0x000 ALT0 0x0 -#define VF610_PAD_PTD21__FB_AD21 0x124 0x000 ALT1 0x0 -#define VF610_PAD_PTD21__NF_IO5 0x124 0x000 ALT2 0x0 -#define VF610_PAD_PTD21__ENET0_1588_TMR2 0x124 0x000 ALT4 0x0 -#define VF610_PAD_PTD21__ESDHC0_DAT6 0x124 0x000 ALT5 0x0 -#define VF610_PAD_PTD21__UART2_RTS 0x124 0x000 ALT6 0x0 -#define VF610_PAD_PTD21__DCU1_R5 0x124 0x000 ALT7 0x0 -#define VF610_PAD_PTD20__GPIO_74 0x128 0x000 ALT0 0x0 -#define VF610_PAD_PTD20__FB_AD20 0x128 0x000 ALT1 0x0 -#define VF610_PAD_PTD20__NF_IO4 0x128 0x000 ALT2 0x0 -#define VF610_PAD_PTD20__ENET0_1588_TMR3 0x128 0x000 ALT4 0x0 -#define VF610_PAD_PTD20__ESDHC0_DAT7 0x128 0x000 ALT5 0x0 -#define VF610_PAD_PTD20__UART2_CTS 0x128 0x384 ALT6 0x0 -#define VF610_PAD_PTD20__DCU1_R0 0x128 0x000 ALT7 0x0 -#define VF610_PAD_PTD19__GPIO_75 0x12C 0x000 ALT0 0x0 -#define VF610_PAD_PTD19__FB_AD19 0x12C 0x000 ALT1 0x0 -#define VF610_PAD_PTD19__NF_IO3 0x12C 0x000 ALT2 0x0 -#define VF610_PAD_PTD19__ESAI_SCKR 0x12C 0x000 ALT3 0x0 -#define VF610_PAD_PTD19__I2C0_SCL 0x12C 0x33C ALT4 0x2 -#define VF610_PAD_PTD19__FTM2_QD_PHA 0x12C 0x000 ALT5 0x0 -#define VF610_PAD_PTD19__DCU1_R1 0x12C 0x000 ALT7 0x0 -#define VF610_PAD_PTD18__GPIO_76 0x130 0x000 ALT0 0x0 -#define VF610_PAD_PTD18__FB_AD18 0x130 0x000 ALT1 0x0 -#define VF610_PAD_PTD18__NF_IO2 0x130 0x000 ALT2 0x0 -#define VF610_PAD_PTD18__ESAI_FSR 0x130 0x000 ALT3 0x0 -#define VF610_PAD_PTD18__I2C0_SDA 0x130 0x340 ALT4 0x2 -#define VF610_PAD_PTD18__FTM2_QD_PHB 0x130 0x000 ALT5 0x0 -#define VF610_PAD_PTD18__DCU1_G0 0x130 0x000 ALT7 0x0 -#define VF610_PAD_PTD17__GPIO_77 0x134 0x000 ALT0 0x0 -#define VF610_PAD_PTD17__FB_AD17 0x134 0x000 ALT1 0x0 -#define VF610_PAD_PTD17__NF_IO1 0x134 0x000 ALT2 0x0 -#define VF610_PAD_PTD17__ESAI_HCKR 0x134 0x000 ALT3 0x0 -#define VF610_PAD_PTD17__I2C1_SCL 0x134 0x344 ALT4 0x2 -#define VF610_PAD_PTD17__DCU1_G1 0x134 0x000 ALT7 0x0 -#define VF610_PAD_PTD16__GPIO_78 0x138 0x000 ALT0 0x0 -#define VF610_PAD_PTD16__FB_AD16 0x138 0x000 ALT1 0x0 -#define VF610_PAD_PTD16__NF_IO0 0x138 0x000 ALT2 0x0 -#define VF610_PAD_PTD16__ESAI_HCKT 0x138 0x000 ALT3 0x0 -#define VF610_PAD_PTD16__I2C1_SDA 0x138 0x348 ALT4 0x2 -#define VF610_PAD_PTD16__DCU1_G2 0x138 0x000 ALT7 0x0 -#define VF610_PAD_PTD0__GPIO_79 0x13C 0x000 ALT0 0x0 -#define VF610_PAD_PTD0__QSPI0_A_QSCK 0x13C 0x000 ALT1 0x0 -#define VF610_PAD_PTD0__UART2_TX 0x13C 0x38C ALT2 0x2 -#define VF610_PAD_PTD0__FB_AD15 0x13C 0x000 ALT4 0x0 -#define VF610_PAD_PTD0__SPDIF_EXTCLK 0x13C 0x000 ALT5 0x0 -#define VF610_PAD_PTD0__DEBUG_OUT17 0x13C 0x000 ALT7 0x0 -#define VF610_PAD_PTD1__GPIO_80 0x140 0x000 ALT0 0x0 -#define VF610_PAD_PTD1__QSPI0_A_CS0 0x140 0x000 ALT1 0x0 -#define VF610_PAD_PTD1__UART2_RX 0x140 0x388 ALT2 0x2 -#define VF610_PAD_PTD1__FB_AD14 0x140 0x000 ALT4 0x0 -#define VF610_PAD_PTD1__SPDIF_IN1 0x140 0x000 ALT5 0x0 -#define VF610_PAD_PTD1__DEBUG_OUT18 0x140 0x000 ALT7 0x0 -#define VF610_PAD_PTD2__GPIO_81 0x144 0x000 ALT0 0x0 -#define VF610_PAD_PTD2__QSPI0_A_DATA3 0x144 0x000 ALT1 0x0 -#define VF610_PAD_PTD2__UART2_RTS 0x144 0x000 ALT2 0x0 -#define VF610_PAD_PTD2__DSPI1_CS3 0x144 0x000 ALT3 0x0 -#define VF610_PAD_PTD2__FB_AD13 0x144 0x000 ALT4 0x0 -#define VF610_PAD_PTD2__SPDIF_OUT1 0x144 0x000 ALT5 0x0 -#define VF610_PAD_PTD2__DEBUG_OUT19 0x144 0x000 ALT7 0x0 -#define VF610_PAD_PTD3__GPIO_82 0x148 0x000 ALT0 0x0 -#define VF610_PAD_PTD3__QSPI0_A_DATA2 0x148 0x000 ALT1 0x0 -#define VF610_PAD_PTD3__UART2_CTS 0x148 0x384 ALT2 0x1 -#define VF610_PAD_PTD3__DSPI1_CS2 0x148 0x000 ALT3 0x0 -#define VF610_PAD_PTD3__FB_AD12 0x148 0x000 ALT4 0x0 -#define VF610_PAD_PTD3__SPDIF_PLOCK 0x148 0x000 ALT5 0x0 -#define VF610_PAD_PTD3__DEBUG_OUT20 0x148 0x000 ALT7 0x0 -#define VF610_PAD_PTD4__GPIO_83 0x14C 0x000 ALT0 0x0 -#define VF610_PAD_PTD4__QSPI0_A_DATA1 0x14C 0x000 ALT1 0x0 -#define VF610_PAD_PTD4__DSPI1_CS1 0x14C 0x000 ALT3 0x0 -#define VF610_PAD_PTD4__FB_AD11 0x14C 0x000 ALT4 0x0 -#define VF610_PAD_PTD4__SPDIF_SRCLK 0x14C 0x000 ALT5 0x0 -#define VF610_PAD_PTD4__DEBUG_OUT21 0x14C 0x000 ALT7 0x0 -#define VF610_PAD_PTD5__GPIO_84 0x150 0x000 ALT0 0x0 -#define VF610_PAD_PTD5__QSPI0_A_DATA0 0x150 0x000 ALT1 0x0 -#define VF610_PAD_PTD5__DSPI1_CS0 0x150 0x300 ALT3 0x1 -#define VF610_PAD_PTD5__FB_AD10 0x150 0x000 ALT4 0x0 -#define VF610_PAD_PTD5__DEBUG_OUT22 0x150 0x000 ALT7 0x0 -#define VF610_PAD_PTD6__GPIO_85 0x154 0x000 ALT0 0x0 -#define VF610_PAD_PTD6__QSPI1_A_DQS 0x154 0x000 ALT1 0x0 -#define VF610_PAD_PTD6__DSPI1_SIN 0x154 0x2FC ALT3 0x1 -#define VF610_PAD_PTD6__FB_AD9 0x154 0x000 ALT4 0x0 -#define VF610_PAD_PTD6__DEBUG_OUT23 0x154 0x000 ALT7 0x0 -#define VF610_PAD_PTD7__GPIO_86 0x158 0x000 ALT0 0x0 -#define VF610_PAD_PTD7__QSPI0_B_QSCK 0x158 0x000 ALT1 0x0 -#define VF610_PAD_PTD7__DSPI1_SOUT 0x158 0x000 ALT3 0x0 -#define VF610_PAD_PTD7__FB_AD8 0x158 0x000 ALT4 0x0 -#define VF610_PAD_PTD7__DEBUG_OUT24 0x158 0x000 ALT7 0x0 -#define VF610_PAD_PTD8__GPIO_87 0x15C 0x000 ALT0 0x0 -#define VF610_PAD_PTD8__QSPI0_B_CS0 0x15C 0x000 ALT1 0x0 -#define VF610_PAD_PTD8__FB_CLKOUT 0x15C 0x000 ALT2 0x0 -#define VF610_PAD_PTD8__DSPI1_SCK 0x15C 0x2F8 ALT3 0x1 -#define VF610_PAD_PTD8__FB_AD7 0x15C 0x000 ALT4 0x0 -#define VF610_PAD_PTD8__DEBUG_OUT25 0x15C 0x000 ALT7 0x0 -#define VF610_PAD_PTD9__GPIO_88 0x160 0x000 ALT0 0x0 -#define VF610_PAD_PTD9__QSPI0_B_DATA3 0x160 0x000 ALT1 0x0 -#define VF610_PAD_PTD9__DSPI3_CS1 0x160 0x000 ALT2 0x0 -#define VF610_PAD_PTD9__FB_AD6 0x160 0x000 ALT4 0x0 -#define VF610_PAD_PTD9__SAI1_TX_SYNC 0x160 0x360 ALT6 0x0 -#define VF610_PAD_PTD9__DCU1_B0 0x160 0x000 ALT7 0x0 -#define VF610_PAD_PTD10__GPIO_89 0x164 0x000 ALT0 0x0 -#define VF610_PAD_PTD10__QSPI0_B_DATA2 0x164 0x000 ALT1 0x0 -#define VF610_PAD_PTD10__DSPI3_CS0 0x164 0x000 ALT2 0x0 -#define VF610_PAD_PTD10__FB_AD5 0x164 0x000 ALT4 0x0 -#define VF610_PAD_PTD10__DCU1_B1 0x164 0x000 ALT7 0x0 -#define VF610_PAD_PTD11__GPIO_90 0x168 0x000 ALT0 0x0 -#define VF610_PAD_PTD11__QSPI0_B_DATA1 0x168 0x000 ALT1 0x0 -#define VF610_PAD_PTD11__DSPI3_SIN 0x168 0x000 ALT2 0x0 -#define VF610_PAD_PTD11__FB_AD4 0x168 0x000 ALT4 0x0 -#define VF610_PAD_PTD11__DEBUG_OUT26 0x168 0x000 ALT7 0x0 -#define VF610_PAD_PTD12__GPIO_91 0x16C 0x000 ALT0 0x0 -#define VF610_PAD_PTD12__QSPI0_B_DATA0 0x16C 0x000 ALT1 0x0 -#define VF610_PAD_PTD12__DSPI3_SOUT 0x16C 0x000 ALT2 0x0 -#define VF610_PAD_PTD12__FB_AD3 0x16C 0x000 ALT4 0x0 -#define VF610_PAD_PTD12__DEBUG_OUT27 0x16C 0x000 ALT7 0x0 -#define VF610_PAD_PTD13__GPIO_92 0x170 0x000 ALT0 0x0 -#define VF610_PAD_PTD13__QSPI0_B_DQS 0x170 0x000 ALT1 0x0 -#define VF610_PAD_PTD13__DSPI3_SCK 0x170 0x000 ALT2 0x0 -#define VF610_PAD_PTD13__FB_AD2 0x170 0x000 ALT4 0x0 -#define VF610_PAD_PTD13__DEBUG_OUT28 0x170 0x000 ALT7 0x0 -#define VF610_PAD_PTB23__GPIO_93 0x174 0x000 ALT0 0x0 -#define VF610_PAD_PTB23__SAI0_TX_BCLK 0x174 0x000 ALT1 0x0 -#define VF610_PAD_PTB23__UART1_TX 0x174 0x380 ALT2 0x2 -#define VF610_PAD_PTB23__SRC_RCON18 0x174 0x398 ALT3 0x1 -#define VF610_PAD_PTB23__FB_MUXED_ALE 0x174 0x000 ALT4 0x0 -#define VF610_PAD_PTB23__FB_TS_B 0x174 0x000 ALT5 0x0 -#define VF610_PAD_PTB23__UART3_RTS 0x174 0x000 ALT6 0x0 -#define VF610_PAD_PTB23__DCU1_G3 0x174 0x000 ALT7 0x0 -#define VF610_PAD_PTB24__GPIO_94 0x178 0x000 ALT0 0x0 -#define VF610_PAD_PTB24__SAI0_RX_BCLK 0x178 0x000 ALT1 0x0 -#define VF610_PAD_PTB24__UART1_RX 0x178 0x37C ALT2 0x2 -#define VF610_PAD_PTB24__SRC_RCON19 0x178 0x39C ALT3 0x1 -#define VF610_PAD_PTB24__FB_MUXED_TSIZ0 0x178 0x000 ALT4 0x0 -#define VF610_PAD_PTB24__NF_WE_B 0x178 0x000 ALT5 0x0 -#define VF610_PAD_PTB24__UART3_CTS 0x178 0x000 ALT6 0x0 -#define VF610_PAD_PTB24__DCU1_G4 0x178 0x000 ALT7 0x0 -#define VF610_PAD_PTB25__GPIO_95 0x17C 0x000 ALT0 0x0 -#define VF610_PAD_PTB25__SAI0_RX_DATA 0x17C 0x000 ALT1 0x0 -#define VF610_PAD_PTB25__UART1_RTS 0x17C 0x000 ALT2 0x0 -#define VF610_PAD_PTB25__SRC_RCON20 0x17C 0x3A0 ALT3 0x1 -#define VF610_PAD_PTB25__FB_CS1_B 0x17C 0x000 ALT4 0x0 -#define VF610_PAD_PTB25__NF_CE0_B 0x17C 0x000 ALT5 0x0 -#define VF610_PAD_PTB25__DCU1_G5 0x17C 0x000 ALT7 0x0 -#define VF610_PAD_PTB26__GPIO_96 0x180 0x000 ALT0 0x0 -#define VF610_PAD_PTB26__SAI0_TX_DATA 0x180 0x000 ALT1 0x0 -#define VF610_PAD_PTB26__UART1_CTS 0x180 0x378 ALT2 0x2 -#define VF610_PAD_PTB26__SRC_RCON21 0x180 0x000 ALT3 0x0 -#define VF610_PAD_PTB26__FB_CS0_B 0x180 0x000 ALT4 0x0 -#define VF610_PAD_PTB26__NF_CE1_B 0x180 0x000 ALT5 0x0 -#define VF610_PAD_PTB26__DCU1_G6 0x180 0x000 ALT7 0x0 -#define VF610_PAD_PTB27__GPIO_97 0x184 0x000 ALT0 0x0 -#define VF610_PAD_PTB27__SAI0_RX_SYNC 0x184 0x000 ALT1 0x0 -#define VF610_PAD_PTB27__SRC_RCON22 0x184 0x000 ALT3 0x0 -#define VF610_PAD_PTB27__FB_OE_B 0x184 0x000 ALT4 0x0 -#define VF610_PAD_PTB27__FB_MUXED_TBST_B 0x184 0x000 ALT5 0x0 -#define VF610_PAD_PTB27__NF_RE_B 0x184 0x000 ALT6 0x0 -#define VF610_PAD_PTB27__DCU1_G7 0x184 0x000 ALT7 0x0 -#define VF610_PAD_PTB28__GPIO_98 0x188 0x000 ALT0 0x0 -#define VF610_PAD_PTB28__SAI0_TX_SYNC 0x188 0x000 ALT1 0x0 -#define VF610_PAD_PTB28__SRC_RCON23 0x188 0x000 ALT3 0x0 -#define VF610_PAD_PTB28__FB_RW_B 0x188 0x000 ALT4 0x0 -#define VF610_PAD_PTB28__DCU1_B6 0x188 0x000 ALT7 0x0 -#define VF610_PAD_PTC26__GPIO_99 0x18C 0x000 ALT0 0x0 -#define VF610_PAD_PTC26__SAI1_TX_BCLK 0x18C 0x000 ALT1 0x0 -#define VF610_PAD_PTC26__DSPI0_CS5 0x18C 0x000 ALT2 0x0 -#define VF610_PAD_PTC26__SRC_RCON24 0x18C 0x000 ALT3 0x0 -#define VF610_PAD_PTC26__FB_TA_B 0x18C 0x000 ALT4 0x0 -#define VF610_PAD_PTC26__NF_RB_B 0x18C 0x000 ALT5 0x0 -#define VF610_PAD_PTC26__DCU1_B7 0x18C 0x000 ALT7 0x0 -#define VF610_PAD_PTC27__GPIO_100 0x190 0x000 ALT0 0x0 -#define VF610_PAD_PTC27__SAI1_RX_BCLK 0x190 0x000 ALT1 0x0 -#define VF610_PAD_PTC27__DSPI0_CS4 0x190 0x000 ALT2 0x0 -#define VF610_PAD_PTC27__SRC_RCON25 0x190 0x000 ALT3 0x0 -#define VF610_PAD_PTC27__FB_BE3_B 0x190 0x000 ALT4 0x0 -#define VF610_PAD_PTC27__FB_CS3_B 0x190 0x000 ALT5 0x0 -#define VF610_PAD_PTC27__NF_ALE 0x190 0x000 ALT6 0x0 -#define VF610_PAD_PTC27__DCU1_B2 0x190 0x000 ALT7 0x0 -#define VF610_PAD_PTC28__GPIO_101 0x194 0x000 ALT0 0x0 -#define VF610_PAD_PTC28__SAI1_RX_DATA 0x194 0x000 ALT1 0x0 -#define VF610_PAD_PTC28__DSPI0_CS3 0x194 0x000 ALT2 0x0 -#define VF610_PAD_PTC28__SRC_RCON26 0x194 0x000 ALT3 0x0 -#define VF610_PAD_PTC28__FB_BE2_B 0x194 0x000 ALT4 0x0 -#define VF610_PAD_PTC28__FB_CS2_B 0x194 0x000 ALT5 0x0 -#define VF610_PAD_PTC28__NF_CLE 0x194 0x000 ALT6 0x0 -#define VF610_PAD_PTC28__DCU1_B3 0x194 0x000 ALT7 0x0 -#define VF610_PAD_PTC29__GPIO_102 0x198 0x000 ALT0 0x0 -#define VF610_PAD_PTC29__SAI1_TX_DATA 0x198 0x000 ALT1 0x0 -#define VF610_PAD_PTC29__DSPI0_CS2 0x198 0x000 ALT2 0x0 -#define VF610_PAD_PTC29__SRC_RCON27 0x198 0x000 ALT3 0x0 -#define VF610_PAD_PTC29__FB_BE1_B 0x198 0x000 ALT4 0x0 -#define VF610_PAD_PTC29__FB_MUXED_TSIZE1 0x198 0x000 ALT5 0x0 -#define VF610_PAD_PTC29__DCU1_B4 0x198 0x000 ALT7 0x0 -#define VF610_PAD_PTC30__GPIO_103 0x19C 0x000 ALT0 0x0 -#define VF610_PAD_PTC30__SAI1_RX_SYNC 0x19C 0x000 ALT1 0x0 -#define VF610_PAD_PTC30__DSPI1_CS2 0x19C 0x000 ALT2 0x0 -#define VF610_PAD_PTC30__SRC_RCON28 0x19C 0x000 ALT3 0x0 -#define VF610_PAD_PTC30__FB_MUXED_BE0_B 0x19C 0x000 ALT4 0x0 -#define VF610_PAD_PTC30__FB_TSIZ0 0x19C 0x000 ALT5 0x0 -#define VF610_PAD_PTC30__ADC0_SE5 0x19C 0x000 ALT6 0x0 -#define VF610_PAD_PTC30__DCU1_B5 0x19C 0x000 ALT7 0x0 -#define VF610_PAD_PTC31__GPIO_104 0x1A0 0x000 ALT0 0x0 -#define VF610_PAD_PTC31__SAI1_TX_SYNC 0x1A0 0x360 ALT1 0x1 -#define VF610_PAD_PTC31__SRC_RCON29 0x1A0 0x000 ALT3 0x0 -#define VF610_PAD_PTC31__ADC1_SE5 0x1A0 0x000 ALT6 0x0 -#define VF610_PAD_PTC31__DCU1_B6 0x1A0 0x000 ALT7 0x0 -#define VF610_PAD_PTE0__GPIO_105 0x1A4 0x000 ALT0 0x0 -#define VF610_PAD_PTE0__DCU0_HSYNC 0x1A4 0x000 ALT1 0x0 -#define VF610_PAD_PTE0__SRC_BMODE1 0x1A4 0x000 ALT2 0x0 -#define VF610_PAD_PTE0__LCD0 0x1A4 0x000 ALT4 0x0 -#define VF610_PAD_PTE0__DEBUG_OUT29 0x1A4 0x000 ALT7 0x0 -#define VF610_PAD_PTE1__GPIO_106 0x1A8 0x000 ALT0 0x0 -#define VF610_PAD_PTE1__DCU0_VSYNC 0x1A8 0x000 ALT1 0x0 -#define VF610_PAD_PTE1__SRC_BMODE0 0x1A8 0x000 ALT2 0x0 -#define VF610_PAD_PTE1__LCD1 0x1A8 0x000 ALT4 0x0 -#define VF610_PAD_PTE1__DEBUG_OUT30 0x1A8 0x000 ALT7 0x0 -#define VF610_PAD_PTE2__GPIO_107 0x1AC 0x000 ALT0 0x0 -#define VF610_PAD_PTE2__DCU0_PCLK 0x1AC 0x000 ALT1 0x0 -#define VF610_PAD_PTE2__LCD2 0x1AC 0x000 ALT4 0x0 -#define VF610_PAD_PTE2__DEBUG_OUT31 0x1AC 0x000 ALT7 0x0 -#define VF610_PAD_PTE3__GPIO_108 0x1B0 0x000 ALT0 0x0 -#define VF610_PAD_PTE3__DCU0_TAG 0x1B0 0x000 ALT1 0x0 -#define VF610_PAD_PTE3__LCD3 0x1B0 0x000 ALT4 0x0 -#define VF610_PAD_PTE3__DEBUG_OUT32 0x1B0 0x000 ALT7 0x0 -#define VF610_PAD_PTE4__GPIO_109 0x1B4 0x000 ALT0 0x0 -#define VF610_PAD_PTE4__DCU0_DE 0x1B4 0x000 ALT1 0x0 -#define VF610_PAD_PTE4__LCD4 0x1B4 0x000 ALT4 0x0 -#define VF610_PAD_PTE4__DEBUG_OUT33 0x1B4 0x000 ALT7 0x0 -#define VF610_PAD_PTE5__GPIO_110 0x1B8 0x000 ALT0 0x0 -#define VF610_PAD_PTE5__DCU0_R0 0x1B8 0x000 ALT1 0x0 -#define VF610_PAD_PTE5__LCD5 0x1B8 0x000 ALT4 0x0 -#define VF610_PAD_PTE5__DEBUG_OUT34 0x1B8 0x000 ALT7 0x0 -#define VF610_PAD_PTE6__GPIO_111 0x1BC 0x000 ALT0 0x0 -#define VF610_PAD_PTE6__DCU0_R1 0x1BC 0x000 ALT1 0x0 -#define VF610_PAD_PTE6__LCD6 0x1BC 0x000 ALT4 0x0 -#define VF610_PAD_PTE6__DEBUG_OUT35 0x1BC 0x000 ALT7 0x0 -#define VF610_PAD_PTE7__GPIO_112 0x1C0 0x000 ALT0 0x0 -#define VF610_PAD_PTE7__DCU0_R2 0x1C0 0x000 ALT1 0x0 -#define VF610_PAD_PTE7__SRC_RCON0 0x1C0 0x000 ALT3 0x0 -#define VF610_PAD_PTE7__LCD7 0x1C0 0x000 ALT4 0x0 -#define VF610_PAD_PTE7__DEBUG_OUT36 0x1C0 0x000 ALT7 0x0 -#define VF610_PAD_PTE8__GPIO_113 0x1C4 0x000 ALT0 0x0 -#define VF610_PAD_PTE8__DCU0_R3 0x1C4 0x000 ALT1 0x0 -#define VF610_PAD_PTE8__SRC_RCON1 0x1C4 0x000 ALT3 0x0 -#define VF610_PAD_PTE8__LCD8 0x1C4 0x000 ALT4 0x0 -#define VF610_PAD_PTE8__DEBUG_OUT37 0x1C4 0x000 ALT7 0x0 -#define VF610_PAD_PTE9__GPIO_114 0x1C8 0x000 ALT0 0x0 -#define VF610_PAD_PTE9__DCU0_R4 0x1C8 0x000 ALT1 0x0 -#define VF610_PAD_PTE9__SRC_RCON2 0x1C8 0x000 ALT3 0x0 -#define VF610_PAD_PTE9__LCD9 0x1C8 0x000 ALT4 0x0 -#define VF610_PAD_PTE9__DEBUG_OUT38 0x1C8 0x000 ALT7 0x0 -#define VF610_PAD_PTE10__GPIO_115 0x1CC 0x000 ALT0 0x0 -#define VF610_PAD_PTE10__DCU0_R5 0x1CC 0x000 ALT1 0x0 -#define VF610_PAD_PTE10__SRC_RCON3 0x1CC 0x000 ALT3 0x0 -#define VF610_PAD_PTE10__LCD10 0x1CC 0x000 ALT4 0x0 -#define VF610_PAD_PTE10__DEBUG_OUT39 0x1CC 0x000 ALT7 0x0 -#define VF610_PAD_PTE11__GPIO_116 0x1D0 0x000 ALT0 0x0 -#define VF610_PAD_PTE11__DCU0_R6 0x1D0 0x000 ALT1 0x0 -#define VF610_PAD_PTE11__SRC_RCON4 0x1D0 0x000 ALT3 0x0 -#define VF610_PAD_PTE11__LCD11 0x1D0 0x000 ALT4 0x0 -#define VF610_PAD_PTE11__DEBUG_OUT40 0x1D0 0x000 ALT7 0x0 -#define VF610_PAD_PTE12__GPIO_117 0x1D4 0x000 ALT0 0x0 -#define VF610_PAD_PTE12__DCU0_R7 0x1D4 0x000 ALT1 0x0 -#define VF610_PAD_PTE12__DSPI1_CS3 0x1D4 0x000 ALT2 0x0 -#define VF610_PAD_PTE12__SRC_RCON5 0x1D4 0x000 ALT3 0x0 -#define VF610_PAD_PTE12__LCD12 0x1D4 0x000 ALT4 0x0 -#define VF610_PAD_PTE12__LPT_ALT0 0x1D4 0x000 ALT7 0x0 -#define VF610_PAD_PTE13__GPIO_118 0x1D8 0x000 ALT0 0x0 -#define VF610_PAD_PTE13__DCU0_G0 0x1D8 0x000 ALT1 0x0 -#define VF610_PAD_PTE13__LCD13 0x1D8 0x000 ALT4 0x0 -#define VF610_PAD_PTE13__DEBUG_OUT41 0x1D8 0x000 ALT7 0x0 -#define VF610_PAD_PTE14__GPIO_119 0x1DC 0x000 ALT0 0x0 -#define VF610_PAD_PTE14__DCU0_G1 0x1DC 0x000 ALT1 0x0 -#define VF610_PAD_PTE14__LCD14 0x1DC 0x000 ALT4 0x0 -#define VF610_PAD_PTE14__DEBUG_OUT42 0x1DC 0x000 ALT7 0x0 -#define VF610_PAD_PTE15__GPIO_120 0x1E0 0x000 ALT0 0x0 -#define VF610_PAD_PTE15__DCU0_G2 0x1E0 0x000 ALT1 0x0 -#define VF610_PAD_PTE15__SRC_RCON6 0x1E0 0x000 ALT3 0x0 -#define VF610_PAD_PTE15__LCD15 0x1E0 0x000 ALT4 0x0 -#define VF610_PAD_PTE15__DEBUG_OUT43 0x1E0 0x000 ALT7 0x0 -#define VF610_PAD_PTE16__GPIO_121 0x1E4 0x000 ALT0 0x0 -#define VF610_PAD_PTE16__DCU0_G3 0x1E4 0x000 ALT1 0x0 -#define VF610_PAD_PTE16__SRC_RCON7 0x1E4 0x000 ALT3 0x0 -#define VF610_PAD_PTE16__LCD16 0x1E4 0x000 ALT4 0x0 -#define VF610_PAD_PTE17__GPIO_122 0x1E8 0x000 ALT0 0x0 -#define VF610_PAD_PTE17__DCU0_G4 0x1E8 0x000 ALT1 0x0 -#define VF610_PAD_PTE17__SRC_RCON8 0x1E8 0x000 ALT3 0x0 -#define VF610_PAD_PTE17__LCD17 0x1E8 0x000 ALT4 0x0 -#define VF610_PAD_PTE18__GPIO_123 0x1EC 0x000 ALT0 0x0 -#define VF610_PAD_PTE18__DCU0_G5 0x1EC 0x000 ALT1 0x0 -#define VF610_PAD_PTE18__SRC_RCON9 0x1EC 0x000 ALT3 0x0 -#define VF610_PAD_PTE18__LCD18 0x1EC 0x000 ALT4 0x0 -#define VF610_PAD_PTE19__GPIO_124 0x1F0 0x000 ALT0 0x0 -#define VF610_PAD_PTE19__DCU0_G6 0x1F0 0x000 ALT1 0x0 -#define VF610_PAD_PTE19__SRC_RCON10 0x1F0 0x000 ALT3 0x0 -#define VF610_PAD_PTE19__LCD19 0x1F0 0x000 ALT4 0x0 -#define VF610_PAD_PTE19__I2C0_SCL 0x1F0 0x33C ALT5 0x3 -#define VF610_PAD_PTE20__GPIO_125 0x1F4 0x000 ALT0 0x0 -#define VF610_PAD_PTE20__DCU0_G7 0x1F4 0x000 ALT1 0x0 -#define VF610_PAD_PTE20__SRC_RCON11 0x1F4 0x000 ALT3 0x0 -#define VF610_PAD_PTE20__LCD20 0x1F4 0x000 ALT4 0x0 -#define VF610_PAD_PTE20__I2C0_SDA 0x1F4 0x340 ALT5 0x3 -#define VF610_PAD_PTE20__EWM_IN 0x1F4 0x000 ALT7 0x0 -#define VF610_PAD_PTE21__GPIO_126 0x1F8 0x000 ALT0 0x0 -#define VF610_PAD_PTE21__DCU0_B0 0x1F8 0x000 ALT1 0x0 -#define VF610_PAD_PTE21__LCD21 0x1F8 0x000 ALT4 0x0 -#define VF610_PAD_PTE22__GPIO_127 0x1FC 0x000 ALT0 0x0 -#define VF610_PAD_PTE22__DCU0_B1 0x1FC 0x000 ALT1 0x0 -#define VF610_PAD_PTE22__LCD22 0x1FC 0x000 ALT4 0x0 -#define VF610_PAD_PTE23__GPIO_128 0x200 0x000 ALT0 0x0 -#define VF610_PAD_PTE23__DCU0_B2 0x200 0x000 ALT1 0x0 -#define VF610_PAD_PTE23__SRC_RCON12 0x200 0x000 ALT3 0x0 -#define VF610_PAD_PTE23__LCD23 0x200 0x000 ALT4 0x0 -#define VF610_PAD_PTE24__GPIO_129 0x204 0x000 ALT0 0x0 -#define VF610_PAD_PTE24__DCU0_B3 0x204 0x000 ALT1 0x0 -#define VF610_PAD_PTE24__SRC_RCON13 0x204 0x000 ALT3 0x0 -#define VF610_PAD_PTE24__LCD24 0x204 0x000 ALT4 0x0 -#define VF610_PAD_PTE25__GPIO_130 0x208 0x000 ALT0 0x0 -#define VF610_PAD_PTE25__DCU0_B4 0x208 0x000 ALT1 0x0 -#define VF610_PAD_PTE25__SRC_RCON14 0x208 0x000 ALT3 0x0 -#define VF610_PAD_PTE25__LCD25 0x208 0x000 ALT4 0x0 -#define VF610_PAD_PTE26__GPIO_131 0x20C 0x000 ALT0 0x0 -#define VF610_PAD_PTE26__DCU0_B5 0x20C 0x000 ALT1 0x0 -#define VF610_PAD_PTE26__SRC_RCON15 0x20C 0x000 ALT3 0x0 -#define VF610_PAD_PTE26__LCD26 0x20C 0x000 ALT4 0x0 -#define VF610_PAD_PTE27__GPIO_132 0x210 0x000 ALT0 0x0 -#define VF610_PAD_PTE27__DCU0_B6 0x210 0x000 ALT1 0x0 -#define VF610_PAD_PTE27__SRC_RCON16 0x210 0x000 ALT3 0x0 -#define VF610_PAD_PTE27__LCD27 0x210 0x000 ALT4 0x0 -#define VF610_PAD_PTE27__I2C1_SCL 0x210 0x344 ALT5 0x3 -#define VF610_PAD_PTE28__GPIO_133 0x214 0x000 ALT0 0x0 -#define VF610_PAD_PTE28__DCU0_B7 0x214 0x000 ALT1 0x0 -#define VF610_PAD_PTE28__SRC_RCON17 0x214 0x000 ALT3 0x0 -#define VF610_PAD_PTE28__LCD28 0x214 0x000 ALT4 0x0 -#define VF610_PAD_PTE28__I2C1_SDA 0x214 0x348 ALT5 0x3 -#define VF610_PAD_PTE28__EWM_OUT 0x214 0x000 ALT7 0x0 -#define VF610_PAD_PTA7__GPIO_134 0x218 0x000 ALT0 0x0 -#define VF610_PAD_PTA7__VIU_PIX_CLK 0x218 0x3AC ALT1 0x1 - -#endif diff --git a/sys/gnu/dts/arm/vf610-twr.dts b/sys/gnu/dts/arm/vf610-twr.dts deleted file mode 100644 index dbb5ffcdcec..00000000000 --- a/sys/gnu/dts/arm/vf610-twr.dts +++ /dev/null @@ -1,373 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -// -// Copyright 2013 Freescale Semiconductor, Inc. - -/dts-v1/; -#include "vf610.dtsi" - -/ { - model = "VF610 Tower Board"; - compatible = "fsl,vf610-twr", "fsl,vf610"; - - chosen { - bootargs = "console=ttyLP1,115200"; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x8000000>; - }; - - audio_ext: mclk_osc { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24576000>; - }; - - enet_ext: eth_osc { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <50000000>; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_3p3v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_vcc_3v3_mcu: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "vcc_3v3_mcu"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,widgets = - "Microphone", "Microphone Jack", - "Headphone", "Headphone Jack", - "Speaker", "Speaker Ext", - "Line", "Line In Jack"; - simple-audio-card,routing = - "MIC_IN", "Microphone Jack", - "Microphone Jack", "Mic Bias", - "LINE_IN", "Line In Jack", - "Headphone Jack", "HP_OUT", - "Speaker Ext", "LINE_OUT"; - - simple-audio-card,cpu { - sound-dai = <&sai2>; - frame-master; - bitclock-master; - }; - - simple-audio-card,codec { - sound-dai = <&codec>; - frame-master; - bitclock-master; - }; - }; -}; - -&adc0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_adc0_ad5>; - vref-supply = <®_vcc_3v3_mcu>; - status = "okay"; -}; - -&clks { - clocks = <&sxosc>, <&fxosc>, <&enet_ext>, <&audio_ext>; - clock-names = "sxosc", "fxosc", "enet_ext", "audio_ext"; - assigned-clocks = <&clks VF610_CLK_ENET_SEL>, - <&clks VF610_CLK_ENET_TS_SEL>; - assigned-clock-parents = <&clks VF610_CLK_ENET_EXT>, - <&clks VF610_CLK_ENET_EXT>; -}; - -&dspi0 { - bus-num = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_dspi0>; - status = "okay"; - - sflash: at26df081a@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "atmel,at26df081a"; - spi-max-frequency = <16000000>; - spi-cpol; - spi-cpha; - reg = <0>; - }; -}; - -&edma0 { - status = "okay"; -}; - -&esdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc1>; - bus-width = <4>; - cd-gpios = <&gpio4 6 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&fec0 { - phy-mode = "rmii"; - phy-handle = <ðphy0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec0>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; - - ethphy1: ethernet-phy@1 { - reg = <1>; - }; - }; -}; - -&fec1 { - phy-mode = "rmii"; - phy-handle = <ðphy1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - status = "okay"; -}; - -&i2c0 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - status = "okay"; - - codec: sgtl5000@a { - #sound-dai-cells = <0>; - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - VDDA-supply = <®_3p3v>; - VDDIO-supply = <®_3p3v>; - clocks = <&clks VF610_CLK_SAI2>; - }; -}; - -&iomuxc { - vf610-twr { - pinctrl_adc0_ad5: adc0ad5grp { - fsl,pins = < - VF610_PAD_PTC30__ADC0_SE5 0xa1 - >; - }; - - pinctrl_dspi0: dspi0grp { - fsl,pins = < - VF610_PAD_PTB19__DSPI0_CS0 0x1182 - VF610_PAD_PTB20__DSPI0_SIN 0x1181 - VF610_PAD_PTB21__DSPI0_SOUT 0x1182 - VF610_PAD_PTB22__DSPI0_SCK 0x1182 - >; - }; - - pinctrl_esdhc1: esdhc1grp { - fsl,pins = < - VF610_PAD_PTA24__ESDHC1_CLK 0x31ef - VF610_PAD_PTA25__ESDHC1_CMD 0x31ef - VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef - VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef - VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef - VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef - VF610_PAD_PTA7__GPIO_134 0x219d - >; - }; - - pinctrl_fec0: fec0grp { - fsl,pins = < - VF610_PAD_PTA6__RMII_CLKIN 0x30d1 - VF610_PAD_PTC0__ENET_RMII0_MDC 0x30d3 - VF610_PAD_PTC1__ENET_RMII0_MDIO 0x30d1 - VF610_PAD_PTC2__ENET_RMII0_CRS 0x30d1 - VF610_PAD_PTC3__ENET_RMII0_RXD1 0x30d1 - VF610_PAD_PTC4__ENET_RMII0_RXD0 0x30d1 - VF610_PAD_PTC5__ENET_RMII0_RXER 0x30d1 - VF610_PAD_PTC6__ENET_RMII0_TXD1 0x30d2 - VF610_PAD_PTC7__ENET_RMII0_TXD0 0x30d2 - VF610_PAD_PTC8__ENET_RMII0_TXEN 0x30d2 - >; - }; - - pinctrl_fec1: fec1grp { - fsl,pins = < - VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2 - VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3 - VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1 - VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1 - VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1 - VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1 - VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2 - VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2 - VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2 - >; - }; - - pinctrl_i2c0: i2c0grp { - fsl,pins = < - VF610_PAD_PTB14__I2C0_SCL 0x30d3 - VF610_PAD_PTB15__I2C0_SDA 0x30d3 - >; - }; - - pinctrl_nfc: nfcgrp { - fsl,pins = < - VF610_PAD_PTD31__NF_IO15 0x28df - VF610_PAD_PTD30__NF_IO14 0x28df - VF610_PAD_PTD29__NF_IO13 0x28df - VF610_PAD_PTD28__NF_IO12 0x28df - VF610_PAD_PTD27__NF_IO11 0x28df - VF610_PAD_PTD26__NF_IO10 0x28df - VF610_PAD_PTD25__NF_IO9 0x28df - VF610_PAD_PTD24__NF_IO8 0x28df - VF610_PAD_PTD23__NF_IO7 0x28df - VF610_PAD_PTD22__NF_IO6 0x28df - VF610_PAD_PTD21__NF_IO5 0x28df - VF610_PAD_PTD20__NF_IO4 0x28df - VF610_PAD_PTD19__NF_IO3 0x28df - VF610_PAD_PTD18__NF_IO2 0x28df - VF610_PAD_PTD17__NF_IO1 0x28df - VF610_PAD_PTD16__NF_IO0 0x28df - VF610_PAD_PTB24__NF_WE_B 0x28c2 - VF610_PAD_PTB25__NF_CE0_B 0x28c2 - VF610_PAD_PTB27__NF_RE_B 0x28c2 - VF610_PAD_PTC26__NF_RB_B 0x283d - VF610_PAD_PTC27__NF_ALE 0x28c2 - VF610_PAD_PTC28__NF_CLE 0x28c2 - >; - }; - - pinctrl_pwm0: pwm0grp { - fsl,pins = < - VF610_PAD_PTB0__FTM0_CH0 0x1582 - VF610_PAD_PTB1__FTM0_CH1 0x1582 - VF610_PAD_PTB2__FTM0_CH2 0x1582 - VF610_PAD_PTB3__FTM0_CH3 0x1582 - >; - }; - - pinctrl_sai2: sai2grp { - fsl,pins = < - VF610_PAD_PTA16__SAI2_TX_BCLK 0x02ed - VF610_PAD_PTA18__SAI2_TX_DATA 0x02ee - VF610_PAD_PTA19__SAI2_TX_SYNC 0x02ed - VF610_PAD_PTA21__SAI2_RX_BCLK 0x02ed - VF610_PAD_PTA22__SAI2_RX_DATA 0x02ed - VF610_PAD_PTA23__SAI2_RX_SYNC 0x02ed - VF610_PAD_PTB18__EXT_AUDIO_MCLK 0x02ed - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - VF610_PAD_PTB4__UART1_TX 0x21a2 - VF610_PAD_PTB5__UART1_RX 0x21a1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - VF610_PAD_PTB6__UART2_TX 0x21a2 - VF610_PAD_PTB7__UART2_RX 0x21a1 - >; - }; - }; -}; - -&nfc { - assigned-clocks = <&clks VF610_CLK_NFC>; - assigned-clock-rates = <33000000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nfc>; - status = "okay"; - - nand@0 { - compatible = "fsl,vf610-nfc-nandcs"; - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; - nand-bus-width = <16>; - nand-ecc-mode = "hw"; - nand-ecc-strength = <24>; - nand-ecc-step-size = <2048>; - nand-on-flash-bbt; - }; -}; - -&pwm0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm0>; - status = "okay"; -}; - -&sai2 { - #sound-dai-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai2>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&usbdev0 { - disable-over-current; - status = "okay"; -}; - -&usbh1 { - disable-over-current; - status = "okay"; -}; - -&usbmisc0 { - status = "okay"; -}; - -&usbmisc1 { - status = "okay"; -}; - -&usbphy0 { - status = "okay"; -}; - -&usbphy1 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/vf610-zii-cfu1.dts b/sys/gnu/dts/arm/vf610-zii-cfu1.dts deleted file mode 100644 index 28732249cfc..00000000000 --- a/sys/gnu/dts/arm/vf610-zii-cfu1.dts +++ /dev/null @@ -1,359 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) - -/* - * Copyright (C) 2018 Zodiac Inflight Innovations - */ - -/dts-v1/; -#include "vf610.dtsi" - -/ { - model = "ZII VF610 CFU1 Board"; - compatible = "zii,vf610cfu1", "zii,vf610dev", "fsl,vf610"; - - chosen { - stdout-path = &uart0; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000>; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pinctrl_leds_debug>; - pinctrl-names = "default"; - - led-debug { - label = "zii:green:debug1"; - gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - - led-fail { - label = "zii:red:fail"; - gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led-status { - label = "zii:green:status"; - gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-debug-a { - label = "zii:green:debug_a"; - gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-debug-b { - label = "zii:green:debug_b"; - gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - - reg_vcc_3v3_mcu: regulator-vcc-3v3-mcu { - compatible = "regulator-fixed"; - regulator-name = "vcc_3v3_mcu"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - sff: sfp { - compatible = "sff,sff"; - pinctrl-0 = <&pinctrl_optical>; - pinctrl-names = "default"; - i2c-bus = <&i2c0>; - los-gpio = <&gpio4 4 GPIO_ACTIVE_HIGH>; - tx-disable-gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; - }; -}; - -&adc0 { - vref-supply = <®_vcc_3v3_mcu>; - status = "okay"; -}; - -&adc1 { - vref-supply = <®_vcc_3v3_mcu>; - status = "okay"; -}; - -&dspi1 { - bus-num = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_dspi1>; - /* - * Some CFU1s come with SPI-NOR chip DNPed, so we leave this - * node disabled by default and rely on bootloader to enable - * it when appropriate. - */ - status = "disabled"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "m25p128", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <50000000>; - - partition@0 { - label = "m25p128-0"; - reg = <0x0 0x01000000>; - }; - }; -}; - -&edma0 { - status = "okay"; -}; - -&edma1 { - status = "okay"; -}; - -&esdhc0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc0>; - bus-width = <8>; - non-removable; - no-1-8-v; - keep-power-in-suspend; - no-sdio; - no-sd; - status = "okay"; -}; - -&esdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc1>; - bus-width = <4>; - no-sdio; - status = "okay"; -}; - -&fec1 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - status = "okay"; - - fixed-link { - speed = <100>; - full-duplex; - }; - - mdio1: mdio { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - switch0: switch0@0 { - compatible = "marvell,mv88e6085"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_switch>; - reg = <0>; - eeprom-length = <512>; - interrupt-parent = <&gpio3>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells = <2>; - reset-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "eth_cu_1000_1"; - }; - - port@1 { - reg = <1>; - label = "eth_cu_1000_2"; - }; - - port@2 { - reg = <2>; - label = "eth_cu_1000_3"; - }; - - port@5 { - reg = <5>; - label = "eth_fc_1000_1"; - phy-mode = "1000base-x"; - managed = "in-band-status"; - sfp = <&sff>; - }; - - port@6 { - reg = <6>; - label = "cpu"; - ethernet = <&fec1>; - - fixed-link { - speed = <100>; - full-duplex; - }; - }; - }; - }; - }; -}; - -&i2c0 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - status = "okay"; - - io-expander@22 { - compatible = "nxp,pca9554"; - reg = <0x22>; - gpio-controller; - }; - - lm75@48 { - compatible = "national,lm75"; - reg = <0x48>; - }; - - eeprom@52 { - compatible = "atmel,24c04"; - reg = <0x52>; - label = "nvm"; - }; - - eeprom@54 { - compatible = "atmel,24c04"; - reg = <0x54>; - label = "nameplate"; - }; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - watchdog@38 { - compatible = "zii,rave-wdt"; - reg = <0x38>; - }; -}; - -&snvsrtc { - status = "disabled"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0>; - status = "okay"; -}; - -&iomuxc { - pinctrl_dspi1: dspi1grp { - fsl,pins = < - VF610_PAD_PTD5__DSPI1_CS0 0x1182 - VF610_PAD_PTC6__DSPI1_SIN 0x1181 - VF610_PAD_PTC7__DSPI1_SOUT 0x1182 - VF610_PAD_PTC8__DSPI1_SCK 0x1182 - >; - }; - - pinctrl_esdhc0: esdhc0grp { - fsl,pins = < - VF610_PAD_PTC0__ESDHC0_CLK 0x31ef - VF610_PAD_PTC1__ESDHC0_CMD 0x31ef - VF610_PAD_PTC2__ESDHC0_DAT0 0x31ef - VF610_PAD_PTC3__ESDHC0_DAT1 0x31ef - VF610_PAD_PTC4__ESDHC0_DAT2 0x31ef - VF610_PAD_PTC5__ESDHC0_DAT3 0x31ef - VF610_PAD_PTD23__ESDHC0_DAT4 0x31ef - VF610_PAD_PTD22__ESDHC0_DAT5 0x31ef - VF610_PAD_PTD21__ESDHC0_DAT6 0x31ef - VF610_PAD_PTD20__ESDHC0_DAT7 0x31ef - >; - }; - - pinctrl_esdhc1: esdhc1grp { - fsl,pins = < - VF610_PAD_PTA24__ESDHC1_CLK 0x31ef - VF610_PAD_PTA25__ESDHC1_CMD 0x31ef - VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef - VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef - VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef - VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef - >; - }; - - pinctrl_fec1: fec1grp { - fsl,pins = < - VF610_PAD_PTA6__RMII_CLKIN 0x30d1 - VF610_PAD_PTC9__ENET_RMII1_MDC 0x30fe - VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3 - VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1 - VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1 - VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1 - VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1 - VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2 - VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2 - VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2 - >; - }; - - pinctrl_i2c0: i2c0grp { - fsl,pins = < - VF610_PAD_PTB14__I2C0_SCL 0x37ff - VF610_PAD_PTB15__I2C0_SDA 0x37ff - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - VF610_PAD_PTB16__I2C1_SCL 0x37ff - VF610_PAD_PTB17__I2C1_SDA 0x37ff - >; - }; - - pinctrl_leds_debug: pinctrl-leds-debug { - fsl,pins = < - VF610_PAD_PTD3__GPIO_82 0x31c2 - VF610_PAD_PTE3__GPIO_108 0x31c2 - VF610_PAD_PTE4__GPIO_109 0x31c2 - VF610_PAD_PTE5__GPIO_110 0x31c2 - VF610_PAD_PTE6__GPIO_111 0x31c2 - >; - }; - - pinctrl_optical: optical-grp { - fsl,pins = < - /* SFF SD input */ - VF610_PAD_PTE27__GPIO_132 0x3061 - - /* SFF Transmit disable output */ - VF610_PAD_PTE13__GPIO_118 0x3043 - >; - }; - - pinctrl_switch: switch-grp { - fsl,pins = < - VF610_PAD_PTB28__GPIO_98 0x3061 - VF610_PAD_PTE2__GPIO_107 0x1042 - >; - }; - - pinctrl_uart0: uart0grp { - fsl,pins = < - VF610_PAD_PTB10__UART0_TX 0x21a2 - VF610_PAD_PTB11__UART0_RX 0x21a1 - >; - }; -}; diff --git a/sys/gnu/dts/arm/vf610-zii-dev-rev-b.dts b/sys/gnu/dts/arm/vf610-zii-dev-rev-b.dts deleted file mode 100644 index e500911ce0a..00000000000 --- a/sys/gnu/dts/arm/vf610-zii-dev-rev-b.dts +++ /dev/null @@ -1,441 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2015, 2016 Zodiac Inflight Innovations - */ - -/dts-v1/; -#include "vf610-zii-dev.dtsi" - -/ { - model = "ZII VF610 Development Board, Rev B"; - compatible = "zii,vf610dev-b", "zii,vf610dev", "fsl,vf610"; - - mdio-mux { - compatible = "mdio-mux-gpio"; - pinctrl-0 = <&pinctrl_mdio_mux>; - pinctrl-names = "default"; - gpios = <&gpio0 8 GPIO_ACTIVE_HIGH - &gpio0 9 GPIO_ACTIVE_HIGH - &gpio0 24 GPIO_ACTIVE_HIGH - &gpio0 25 GPIO_ACTIVE_HIGH>; - mdio-parent-bus = <&mdio1>; - #address-cells = <1>; - #size-cells = <0>; - - mdio_mux_1: mdio@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - switch0: switch@0 { - compatible = "marvell,mv88e6085"; - pinctrl-0 = <&pinctrl_gpio_switch0>; - pinctrl-names = "default"; - reg = <0>; - dsa,member = <0 0>; - interrupt-parent = <&gpio0>; - interrupts = <27 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells = <2>; - eeprom-length = <512>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "lan0"; - phy-handle = <&switch0phy0>; - }; - - port@1 { - reg = <1>; - label = "lan1"; - phy-handle = <&switch0phy1>; - }; - - port@2 { - reg = <2>; - label = "lan2"; - phy-handle = <&switch0phy2>; - }; - - switch0port5: port@5 { - reg = <5>; - label = "dsa"; - phy-mode = "rgmii-txid"; - link = <&switch1port6 - &switch2port9>; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - - port@6 { - reg = <6>; - label = "cpu"; - ethernet = <&fec1>; - - fixed-link { - speed = <100>; - full-duplex; - }; - }; - }; - mdio { - #address-cells = <1>; - #size-cells = <0>; - switch0phy0: switch0phy0@0 { - reg = <0>; - interrupt-parent = <&switch0>; - interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; - }; - switch0phy1: switch1phy0@1 { - reg = <1>; - interrupt-parent = <&switch0>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; - }; - switch0phy2: switch1phy0@2 { - reg = <2>; - interrupt-parent = <&switch0>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - }; - }; - - mdio_mux_2: mdio@2 { - reg = <2>; - #address-cells = <1>; - #size-cells = <0>; - - switch1: switch@0 { - compatible = "marvell,mv88e6085"; - pinctrl-0 = <&pinctrl_gpio_switch1>; - pinctrl-names = "default"; - reg = <0>; - dsa,member = <0 1>; - interrupt-parent = <&gpio0>; - interrupts = <26 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells = <2>; - eeprom-length = <512>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "lan3"; - phy-handle = <&switch1phy0>; - }; - - port@1 { - reg = <1>; - label = "lan4"; - phy-handle = <&switch1phy1>; - }; - - port@2 { - reg = <2>; - label = "lan5"; - phy-handle = <&switch1phy2>; - }; - - switch1port5: port@5 { - reg = <5>; - label = "dsa"; - link = <&switch2port9>; - phy-mode = "rgmii-txid"; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - - switch1port6: port@6 { - reg = <6>; - label = "dsa"; - phy-mode = "rgmii-txid"; - link = <&switch0port5>; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; - mdio { - #address-cells = <1>; - #size-cells = <0>; - - switch1phy0: switch1phy0@0 { - reg = <0>; - interrupt-parent = <&switch1>; - interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; - }; - - switch1phy1: switch1phy0@1 { - reg = <1>; - interrupt-parent = <&switch1>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; - }; - - switch1phy2: switch1phy0@2 { - reg = <2>; - interrupt-parent = <&switch1>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - }; - }; - - mdio_mux_4: mdio@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - - switch2: switch@0 { - compatible = "marvell,mv88e6085"; - reg = <0>; - dsa,member = <0 2>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "lan6"; - phy-handle = <&switch2phy0>; - }; - - port@1 { - reg = <1>; - label = "lan7"; - phy-handle = <&switch2phy1>; - }; - - port@2 { - reg = <2>; - label = "lan8"; - phy-handle = <&switch2phy2>; - }; - - port@3 { - reg = <3>; - label = "optical3"; - - fixed-link { - speed = <1000>; - full-duplex; - link-gpios = <&gpio6 2 - GPIO_ACTIVE_HIGH>; - }; - }; - - port@4 { - reg = <4>; - label = "optical4"; - - fixed-link { - speed = <1000>; - full-duplex; - link-gpios = <&gpio6 3 - GPIO_ACTIVE_HIGH>; - }; - }; - - switch2port9: port@9 { - reg = <9>; - label = "dsa"; - phy-mode = "rgmii-txid"; - link = <&switch1port5 - &switch0port5>; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; - mdio { - #address-cells = <1>; - #size-cells = <0>; - - switch2phy0: phy@0 { - reg = <0>; - }; - switch2phy1: phy@1 { - reg = <1>; - }; - switch2phy2: phy@2 { - reg = <2>; - }; - }; - }; - }; - - mdio_mux_8: mdio@8 { - reg = <8>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - spi0 { - compatible = "spi-gpio"; - pinctrl-0 = <&pinctrl_gpio_spi0>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - gpio-sck = <&gpio1 12 GPIO_ACTIVE_HIGH>; - gpio-mosi = <&gpio1 11 GPIO_ACTIVE_HIGH>; - gpio-miso = <&gpio1 10 GPIO_ACTIVE_HIGH>; - cs-gpios = <&gpio1 9 GPIO_ACTIVE_LOW - &gpio1 8 GPIO_ACTIVE_HIGH>; - num-chipselects = <2>; - - flash@0 { - compatible = "m25p128", "jedec,spi-nor"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0>; - spi-max-frequency = <1000000>; - }; - - at93c46d@1 { - compatible = "atmel,at93c46d"; - pinctrl-0 = <&pinctrl_gpio_e6185_eeprom_sel>; - pinctrl-names = "default"; - #address-cells = <0>; - #size-cells = <0>; - reg = <1>; - spi-max-frequency = <500000>; - spi-cs-high; - data-size = <16>; - select-gpios = <&gpio4 4 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&i2c0 { - gpio5: io-expander@20 { - compatible = "nxp,pca9554"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - - }; - - gpio6: io-expander@22 { - compatible = "nxp,pca9554"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pca9554_22>; - reg = <0x22>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - interrupt-parent = <&gpio3>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&i2c2 { - tca9548@70 { - compatible = "nxp,pca9548"; - pinctrl-0 = <&pinctrl_i2c_mux_reset>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x70>; - reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; - - i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - sfp1: eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - }; - }; - - i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - sfp2: eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - }; - }; - - i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - - sfp3: eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - }; - }; - - i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - - sfp4: eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - }; - }; - - i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - }; -}; - - -&iomuxc { - pinctrl_gpio_e6185_eeprom_sel: pinctrl-gpio-e6185-eeprom-spi0 { - fsl,pins = < - VF610_PAD_PTE27__GPIO_132 0x33e2 - >; - }; - - pinctrl_gpio_spi0: pinctrl-gpio-spi0 { - fsl,pins = < - VF610_PAD_PTB22__GPIO_44 0x33e2 - VF610_PAD_PTB21__GPIO_43 0x33e2 - VF610_PAD_PTB20__GPIO_42 0x33e1 - VF610_PAD_PTB19__GPIO_41 0x33e2 - VF610_PAD_PTB18__GPIO_40 0x33e2 - >; - }; - - pinctrl_mdio_mux: pinctrl-mdio-mux { - fsl,pins = < - VF610_PAD_PTA18__GPIO_8 0x31c2 - VF610_PAD_PTA19__GPIO_9 0x31c2 - VF610_PAD_PTB2__GPIO_24 0x31c2 - VF610_PAD_PTB3__GPIO_25 0x31c2 - >; - }; - - pinctrl_pca9554_22: pinctrl-pca95540-22 { - fsl,pins = < - VF610_PAD_PTB28__GPIO_98 0x219d - >; - }; -}; diff --git a/sys/gnu/dts/arm/vf610-zii-dev-rev-c.dts b/sys/gnu/dts/arm/vf610-zii-dev-rev-c.dts deleted file mode 100644 index 778e02c000d..00000000000 --- a/sys/gnu/dts/arm/vf610-zii-dev-rev-c.dts +++ /dev/null @@ -1,456 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2015, 2016 Zodiac Inflight Innovations - */ - -/dts-v1/; -#include "vf610-zii-dev.dtsi" - -/ { - model = "ZII VF610 Development Board, Rev C"; - compatible = "zii,vf610dev-c", "zii,vf610dev", "fsl,vf610"; - - mdio-mux { - compatible = "mdio-mux-gpio"; - pinctrl-0 = <&pinctrl_mdio_mux>; - pinctrl-names = "default"; - gpios = <&gpio0 8 GPIO_ACTIVE_HIGH - &gpio0 9 GPIO_ACTIVE_HIGH - &gpio0 25 GPIO_ACTIVE_HIGH>; - mdio-parent-bus = <&mdio1>; - #address-cells = <1>; - #size-cells = <0>; - - mdio_mux_1: mdio@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - switch0: switch@0 { - compatible = "marvell,mv88e6190"; - pinctrl-0 = <&pinctrl_gpio_switch0>; - pinctrl-names = "default"; - reg = <0>; - dsa,member = <0 0>; - eeprom-length = <65536>; - interrupt-parent = <&gpio0>; - interrupts = <27 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells = <2>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "cpu"; - ethernet = <&fec1>; - - fixed-link { - speed = <100>; - full-duplex; - }; - }; - - port@1 { - reg = <1>; - label = "lan1"; - phy-handle = <&switch0phy1>; - }; - - port@2 { - reg = <2>; - label = "lan2"; - phy-handle = <&switch0phy2>; - }; - - port@3 { - reg = <3>; - label = "lan3"; - phy-handle = <&switch0phy3>; - }; - - port@4 { - reg = <4>; - label = "lan4"; - phy-handle = <&switch0phy4>; - }; - - switch0port10: port@10 { - reg = <10>; - label = "dsa"; - phy-mode = "xaui"; - link = <&switch1port10>; - }; - }; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - switch0phy1: switch0phy@1 { - reg = <1>; - interrupt-parent = <&switch0>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; - }; - - switch0phy2: switch0phy@2 { - reg = <2>; - interrupt-parent = <&switch0>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; - }; - - switch0phy3: switch0phy@3 { - reg = <3>; - interrupt-parent = <&switch0>; - interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; - }; - - switch0phy4: switch0phy@4 { - reg = <4>; - interrupt-parent = <&switch0>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - }; - }; - - mdio_mux_2: mdio@2 { - reg = <2>; - #address-cells = <1>; - #size-cells = <0>; - - switch1: switch@0 { - compatible = "marvell,mv88e6190"; - pinctrl-0 = <&pinctrl_gpio_switch1>; - pinctrl-names = "default"; - reg = <0>; - dsa,member = <0 1>; - eeprom-length = <65536>; - interrupt-parent = <&gpio0>; - interrupts = <26 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells = <2>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - label = "lan5"; - phy-handle = <&switch1phy1>; - }; - - port@2 { - reg = <2>; - label = "lan6"; - phy-handle = <&switch1phy2>; - }; - - port@3 { - reg = <3>; - label = "lan7"; - phy-handle = <&switch1phy3>; - }; - - port@4 { - reg = <4>; - label = "lan8"; - phy-handle = <&switch1phy4>; - }; - - port@9 { - reg = <9>; - label = "sff2"; - phy-mode = "sgmii"; - managed = "in-band-status"; - sfp = <&sff2>; - }; - - switch1port10: port@10 { - reg = <10>; - label = "dsa"; - phy-mode = "xaui"; - link = <&switch0port10>; - }; - }; - mdio { - #address-cells = <1>; - #size-cells = <0>; - - switch1phy1: switch1phy@1 { - reg = <1>; - interrupt-parent = <&switch1>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; - }; - - switch1phy2: switch1phy@2 { - reg = <2>; - interrupt-parent = <&switch1>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; - }; - - switch1phy3: switch1phy@3 { - reg = <3>; - interrupt-parent = <&switch1>; - interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; - }; - - switch1phy4: switch1phy@4 { - reg = <4>; - interrupt-parent = <&switch1>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - }; - }; - - mdio_mux_4: mdio@4 { - reg = <4>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - sff2: sff2 { - /* lower */ - compatible = "sff,sff"; - i2c-bus = <&sff2_i2c>; - los-gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>; - tx-disable-gpios = <&gpio6 14 GPIO_ACTIVE_HIGH>; - }; - - sff3: sff3 { - /* upper */ - compatible = "sff,sff"; - i2c-bus = <&sff3_i2c>; - los-gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>; - tx-disable-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>; - }; -}; - -&dspi0 { - bus-num = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_dspi0>; - status = "okay"; - spi-num-chipselects = <2>; - - flash@0 { - compatible = "m25p128", "jedec,spi-nor"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0>; - spi-max-frequency = <1000000>; - }; - - atzb-rf-233@1 { - compatible = "atmel,at86rf233"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctr_atzb_rf_233>; - - spi-max-frequency = <7500000>; - reg = <1>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; - interrupt-parent = <&gpio3>; - xtal-trim = /bits/ 8 <0x06>; - - sleep-gpio = <&gpio0 24 GPIO_ACTIVE_HIGH>; - reset-gpio = <&gpio6 10 GPIO_ACTIVE_HIGH>; - - fsl,spi-cs-sck-delay = <180>; - fsl,spi-sck-cs-delay = <250>; - }; -}; - -&i2c0 { - /* - * U712 - * - * Exposed signals: - * P1 - WE2_CMD - * P2 - WE2_CLK - */ - gpio5: io-expander@18 { - compatible = "nxp,pca9557"; - reg = <0x18>; - gpio-controller; - #gpio-cells = <2>; - }; - - /* - * U121 - * - * Exposed signals: - * I/O0 - ENET_SWR_EN - * I/O1 - ESW1_RESETn - * I/O2 - ARINC_RESET - * I/O3 - DD1_IO_RESET - * I/O4 - ESW2_RESETn - * I/O5 - ESW3_RESETn - * I/O6 - ESW4_RESETn - * I/O8 - TP909 - * I/O9 - FEM_SEL - * I/O10 - WIFI_RESETn - * I/O11 - PHY_RSTn - * I/O12 - OPT1_SD - * I/O13 - OPT2_SD - * I/O14 - OPT1_TX_DIS - * I/O15 - OPT2_TX_DIS - */ - gpio6: sx1503@20 { - compatible = "semtech,sx1503q"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sx1503_20>; - #gpio-cells = <2>; - #interrupt-cells = <2>; - reg = <0x20>; - interrupt-parent = <&gpio0>; - interrupts = <23 IRQ_TYPE_EDGE_FALLING>; - gpio-controller; - interrupt-controller; - }; - - /* - * U715 - * - * Exposed signals: - * IO0 - WE1_CLK - * IO1 - WE1_CMD - */ - gpio7: io-expander@22 { - compatible = "nxp,pca9554"; - reg = <0x22>; - gpio-controller; - #gpio-cells = <2>; - - }; -}; - -&i2c1 { - eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - read-only; - }; -}; - -&i2c2 { - tca9548@70 { - compatible = "nxp,pca9548"; - pinctrl-0 = <&pinctrl_i2c_mux_reset>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x70>; - reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; - - i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - sff2_i2c: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - sff3_i2c: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - }; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -&gpio0 { - eth0_intrp { - gpio-hog; - gpios = <23 GPIO_ACTIVE_HIGH>; - input; - line-name = "sx1503-irq"; - }; -}; - -&gpio3 { - eth0_intrp { - gpio-hog; - gpios = <2 GPIO_ACTIVE_HIGH>; - input; - line-name = "eth0-intrp"; - }; -}; - -&fec0 { - mdio { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec0_phy_int>; - - interrupt-parent = <&gpio3>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - reg = <0>; - }; - }; -}; - -&iomuxc { - pinctr_atzb_rf_233: pinctrl-atzb-rf-233 { - fsl,pins = < - VF610_PAD_PTB2__GPIO_24 0x31c2 - VF610_PAD_PTE27__GPIO_132 0x33e2 - >; - }; - - - pinctrl_sx1503_20: pinctrl-sx1503-20 { - fsl,pins = < - VF610_PAD_PTB1__GPIO_23 0x219d - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - VF610_PAD_PTA20__UART3_TX 0x21a2 - VF610_PAD_PTA21__UART3_RX 0x21a1 - >; - }; - - pinctrl_mdio_mux: pinctrl-mdio-mux { - fsl,pins = < - VF610_PAD_PTA18__GPIO_8 0x31c2 - VF610_PAD_PTA19__GPIO_9 0x31c2 - VF610_PAD_PTB3__GPIO_25 0x31c2 - >; - }; - - pinctrl_fec0_phy_int: pinctrl-fec0-phy-int { - fsl,pins = < - VF610_PAD_PTB28__GPIO_98 0x219d - >; - }; -}; diff --git a/sys/gnu/dts/arm/vf610-zii-dev.dtsi b/sys/gnu/dts/arm/vf610-zii-dev.dtsi deleted file mode 100644 index a1b4ccee2a1..00000000000 --- a/sys/gnu/dts/arm/vf610-zii-dev.dtsi +++ /dev/null @@ -1,440 +0,0 @@ -/* - * Copyright (C) 2015, 2016 Zodiac Inflight Innovations - * - * Based on an original 'vf610-twr.dts' which is Copyright 2015, - * Freescale Semiconductor, Inc. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "vf610.dtsi" - -/ { - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000>; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pinctrl_leds_debug>; - pinctrl-names = "default"; - - debug { - label = "zii:green:debug1"; - gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - reg_vcc_3v3_mcu: regulator-vcc-3v3-mcu { - compatible = "regulator-fixed"; - regulator-name = "vcc_3v3_mcu"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - usb0_vbus: regulator-usb0-vbus { - compatible = "regulator-fixed"; - pinctrl-0 = <&pinctrl_usb_vbus>; - regulator-name = "usb_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 6 0>; - }; -}; - -&adc0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_adc0_ad5>; - vref-supply = <®_vcc_3v3_mcu>; - status = "okay"; -}; - -&edma0 { - status = "okay"; -}; - -&edma1 { - status = "okay"; -}; - -&esdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc1>; - bus-width = <4>; - status = "okay"; -}; - -&fec0 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec0>; - status = "okay"; -}; - -&fec1 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - status = "okay"; - - fixed-link { - speed = <100>; - full-duplex; - }; - - mdio1: mdio { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - }; -}; - -&i2c0 { - clock-frequency = <100000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c0>; - pinctrl-1 = <&pinctrl_i2c0_gpio>; - scl-gpios = <&gpio1 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; - status = "okay"; - - lm75@48 { - compatible = "national,lm75"; - reg = <0x48>; - }; - - eeprom@50 { - compatible = "atmel,24c04"; - reg = <0x50>; - }; - - eeprom@52 { - compatible = "atmel,24c04"; - reg = <0x52>; - }; - - ds1682@6b { - compatible = "dallas,ds1682"; - reg = <0x6b>; - }; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&qspi0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_qspi0>; - status = "okay"; - - /* - * Attached MT25QL02 can go up to 90Mhz in DTR and 166 in STR - * modes, so, spi-max-frequency is limited to 90MHz - */ - flash@0 { - compatible = "jedec,spi-nor"; - #address-cells = <1>; - #size-cells = <1>; - spi-max-frequency = <90000000>; - spi-rx-bus-width = <4>; - reg = <0>; - m25p,fast-read; - }; - - flash@2 { - compatible = "jedec,spi-nor"; - #address-cells = <1>; - #size-cells = <1>; - spi-max-frequency = <90000000>; - spi-rx-bus-width = <4>; - reg = <2>; - m25p,fast-read; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&usbdev0 { - disable-over-current; - vbus-supply = <&usb0_vbus>; - dr_mode = "host"; - status = "okay"; -}; - -&usbh1 { - disable-over-current; - status = "okay"; -}; - -&usbmisc0 { - status = "okay"; -}; - -&usbmisc1 { - status = "okay"; -}; - -&usbphy0 { - status = "okay"; -}; - -&usbphy1 { - status = "okay"; -}; - -&tempsensor { - io-channels = <&adc0 16>; -}; - -&iomuxc { - pinctrl_adc0_ad5: adc0ad5grp { - fsl,pins = < - VF610_PAD_PTC30__ADC0_SE5 0x00a1 - >; - }; - - pinctrl_dspi0: dspi0grp { - fsl,pins = < - VF610_PAD_PTB18__DSPI0_CS1 0x1182 - VF610_PAD_PTB19__DSPI0_CS0 0x1182 - VF610_PAD_PTB20__DSPI0_SIN 0x1181 - VF610_PAD_PTB21__DSPI0_SOUT 0x1182 - VF610_PAD_PTB22__DSPI0_SCK 0x1182 - >; - }; - - pinctrl_dspi2: dspi2grp { - fsl,pins = < - VF610_PAD_PTD31__DSPI2_CS1 0x1182 - VF610_PAD_PTD30__DSPI2_CS0 0x1182 - VF610_PAD_PTD29__DSPI2_SIN 0x1181 - VF610_PAD_PTD28__DSPI2_SOUT 0x1182 - VF610_PAD_PTD27__DSPI2_SCK 0x1182 - >; - }; - - pinctrl_esdhc1: esdhc1grp { - fsl,pins = < - VF610_PAD_PTA24__ESDHC1_CLK 0x31ef - VF610_PAD_PTA25__ESDHC1_CMD 0x31ef - VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef - VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef - VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef - VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef - VF610_PAD_PTA7__GPIO_134 0x219d - >; - }; - - pinctrl_fec0: fec0grp { - fsl,pins = < - VF610_PAD_PTC0__ENET_RMII0_MDC 0x30d2 - VF610_PAD_PTC1__ENET_RMII0_MDIO 0x30d3 - VF610_PAD_PTC2__ENET_RMII0_CRS 0x30d1 - VF610_PAD_PTC3__ENET_RMII0_RXD1 0x30d1 - VF610_PAD_PTC4__ENET_RMII0_RXD0 0x30d1 - VF610_PAD_PTC5__ENET_RMII0_RXER 0x30d1 - VF610_PAD_PTC6__ENET_RMII0_TXD1 0x30d2 - VF610_PAD_PTC7__ENET_RMII0_TXD0 0x30d2 - VF610_PAD_PTC8__ENET_RMII0_TXEN 0x30d2 - >; - }; - - pinctrl_fec1: fec1grp { - fsl,pins = < - VF610_PAD_PTA6__RMII_CLKIN 0x30d1 - VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2 - VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3 - VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1 - VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1 - VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1 - VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1 - VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2 - VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2 - VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2 - >; - }; - - pinctrl_gpio_spi0: pinctrl-gpio-spi0 { - fsl,pins = < - VF610_PAD_PTB22__GPIO_44 0x33e2 - VF610_PAD_PTB21__GPIO_43 0x33e2 - VF610_PAD_PTB20__GPIO_42 0x33e1 - VF610_PAD_PTB19__GPIO_41 0x33e2 - VF610_PAD_PTB18__GPIO_40 0x33e2 - >; - }; - - pinctrl_gpio_switch0: pinctrl-gpio-switch0 { - fsl,pins = < - VF610_PAD_PTB5__GPIO_27 0x219d - >; - }; - - pinctrl_gpio_switch1: pinctrl-gpio-switch1 { - fsl,pins = < - VF610_PAD_PTB4__GPIO_26 0x219d - >; - }; - - pinctrl_i2c_mux_reset: pinctrl-i2c-mux-reset { - fsl,pins = < - VF610_PAD_PTE14__GPIO_119 0x31c2 - >; - }; - - pinctrl_i2c0: i2c0grp { - fsl,pins = < - VF610_PAD_PTB14__I2C0_SCL 0x37ff - VF610_PAD_PTB15__I2C0_SDA 0x37ff - >; - }; - - pinctrl_i2c0_gpio: i2c0grp-gpio { - fsl,pins = < - VF610_PAD_PTB14__GPIO_36 0x31c2 - VF610_PAD_PTB15__GPIO_37 0x31c2 - >; - }; - - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - VF610_PAD_PTB16__I2C1_SCL 0x37ff - VF610_PAD_PTB17__I2C1_SDA 0x37ff - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - VF610_PAD_PTA22__I2C2_SCL 0x37ff - VF610_PAD_PTA23__I2C2_SDA 0x37ff - >; - }; - - pinctrl_leds_debug: pinctrl-leds-debug { - fsl,pins = < - VF610_PAD_PTD20__GPIO_74 0x31c2 - >; - }; - - pinctrl_qspi0: qspi0grp { - fsl,pins = < - VF610_PAD_PTD0__QSPI0_A_QSCK 0x38c2 - VF610_PAD_PTD1__QSPI0_A_CS0 0x38c2 - VF610_PAD_PTD2__QSPI0_A_DATA3 0x38c3 - VF610_PAD_PTD3__QSPI0_A_DATA2 0x38c3 - VF610_PAD_PTD4__QSPI0_A_DATA1 0x38c3 - VF610_PAD_PTD5__QSPI0_A_DATA0 0x38c3 - VF610_PAD_PTD7__QSPI0_B_QSCK 0x38c2 - VF610_PAD_PTD8__QSPI0_B_CS0 0x38c2 - VF610_PAD_PTD9__QSPI0_B_DATA3 0x38c3 - VF610_PAD_PTD10__QSPI0_B_DATA2 0x38c3 - VF610_PAD_PTD11__QSPI0_B_DATA1 0x38c3 - VF610_PAD_PTD12__QSPI0_B_DATA0 0x38c3 - >; - }; - - pinctrl_uart0: uart0grp { - fsl,pins = < - VF610_PAD_PTB10__UART0_TX 0x21a2 - VF610_PAD_PTB11__UART0_RX 0x21a1 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - VF610_PAD_PTB23__UART1_TX 0x21a2 - VF610_PAD_PTB24__UART1_RX 0x21a1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - VF610_PAD_PTD23__UART2_TX 0x21a2 - VF610_PAD_PTD22__UART2_RX 0x21a1 - >; - }; - - pinctrl_usb_vbus: pinctrl-usb-vbus { - fsl,pins = < - VF610_PAD_PTA16__GPIO_6 0x31c2 - >; - }; - - pinctrl_usb0_host: usb0-host-grp { - fsl,pins = < - VF610_PAD_PTD6__GPIO_85 0x0062 - >; - }; -}; diff --git a/sys/gnu/dts/arm/vf610-zii-scu4-aib.dts b/sys/gnu/dts/arm/vf610-zii-scu4-aib.dts deleted file mode 100644 index b642520199b..00000000000 --- a/sys/gnu/dts/arm/vf610-zii-scu4-aib.dts +++ /dev/null @@ -1,846 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// -// Copyright (C) 2016-2018 Zodiac Inflight Innovations - -/dts-v1/; -#include "vf610.dtsi" - -/ { - model = "ZII VF610 SCU4 AIB"; - compatible = "zii,vf610scu4-aib", "zii,vf610dev", "fsl,vf610"; - - chosen { - stdout-path = &uart0; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000>; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pinctrl_leds_debug>; - pinctrl-names = "default"; - - debug { - label = "zii:green:debug1"; - gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - mdio-mux { - compatible = "mdio-mux-gpio"; - pinctrl-0 = <&pinctrl_mdio_mux>; - pinctrl-names = "default"; - gpios = <&gpio4 4 GPIO_ACTIVE_HIGH - &gpio4 5 GPIO_ACTIVE_HIGH - &gpio3 30 GPIO_ACTIVE_HIGH - &gpio3 31 GPIO_ACTIVE_HIGH>; - mdio-parent-bus = <&mdio1>; - #address-cells = <1>; - #size-cells = <0>; - - mdio_mux_1: mdio@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - switch0: switch0@0 { - compatible = "marvell,mv88e6190"; - reg = <0>; - dsa,member = <0 0>; - eeprom-length = <65536>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "cpu"; - ethernet = <&fec1>; - - fixed-link { - speed = <100>; - full-duplex; - }; - }; - - port@1 { - reg = <1>; - label = "aib2main_1"; - }; - - port@2 { - reg = <2>; - label = "aib2main_2"; - }; - - port@3 { - reg = <3>; - label = "eth_cu_1000_5"; - }; - - port@4 { - reg = <4>; - label = "eth_cu_1000_6"; - }; - - port@5 { - reg = <5>; - label = "eth_cu_1000_4"; - }; - - port@6 { - reg = <6>; - label = "eth_cu_1000_7"; - }; - - port@7 { - reg = <7>; - label = "modem_pic"; - - fixed-link { - speed = <100>; - full-duplex; - }; - }; - - switch0port10: port@10 { - reg = <10>; - label = "dsa"; - phy-mode = "xgmii"; - link = <&switch1port10 - &switch3port10 - &switch2port10>; - }; - }; - }; - }; - - mdio_mux_2: mdio@2 { - reg = <2>; - #address-cells = <1>; - #size-cells = <0>; - - switch1: switch1@0 { - compatible = "marvell,mv88e6190"; - reg = <0>; - dsa,member = <0 1>; - eeprom-length = <65536>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - label = "eth_cu_1000_3"; - }; - - port@2 { - reg = <2>; - label = "eth_cu_100_2"; - }; - - port@3 { - reg = <3>; - label = "eth_cu_100_3"; - }; - - switch1port9: port@9 { - reg = <9>; - label = "dsa"; - phy-mode = "xgmii"; - link = <&switch3port10 - &switch2port10>; - }; - - switch1port10: port@10 { - reg = <10>; - label = "dsa"; - phy-mode = "xgmii"; - link = <&switch0port10>; - }; - }; - }; - }; - - mdio_mux_4: mdio@4 { - reg = <4>; - #address-cells = <1>; - #size-cells = <0>; - - switch2: switch2@0 { - compatible = "marvell,mv88e6190"; - reg = <0>; - dsa,member = <0 2>; - eeprom-length = <65536>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@2 { - reg = <2>; - label = "eth_fc_1000_2"; - phy-mode = "sgmii"; - managed = "in-band-status"; - sfp = <&sff1>; - }; - - port@3 { - reg = <3>; - label = "eth_fc_1000_3"; - phy-mode = "sgmii"; - managed = "in-band-status"; - sfp = <&sff2>; - }; - - port@4 { - reg = <4>; - label = "eth_fc_1000_4"; - phy-mode = "sgmii"; - managed = "in-band-status"; - sfp = <&sff3>; - }; - - port@5 { - reg = <5>; - label = "eth_fc_1000_5"; - phy-mode = "sgmii"; - managed = "in-band-status"; - sfp = <&sff4>; - }; - - port@6 { - reg = <6>; - label = "eth_fc_1000_6"; - phy-mode = "sgmii"; - managed = "in-band-status"; - sfp = <&sff5>; - }; - - port@7 { - reg = <7>; - label = "eth_fc_1000_7"; - phy-mode = "sgmii"; - managed = "in-band-status"; - sfp = <&sff6>; - }; - - port@9 { - reg = <9>; - label = "eth_fc_1000_1"; - phy-mode = "sgmii"; - managed = "in-band-status"; - sfp = <&sff0>; - }; - - switch2port10: port@10 { - reg = <10>; - label = "dsa"; - phy-mode = "2500base-x"; - link = <&switch3port9 - &switch1port9 - &switch0port10>; - }; - }; - }; - }; - - mdio_mux_8: mdio@8 { - reg = <8>; - #address-cells = <1>; - #size-cells = <0>; - - switch3: switch3@0 { - compatible = "marvell,mv88e6190"; - reg = <0>; - dsa,member = <0 3>; - eeprom-length = <65536>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@2 { - reg = <2>; - label = "eth_fc_1000_8"; - phy-mode = "sgmii"; - managed = "in-band-status"; - sfp = <&sff7>; - }; - - port@3 { - reg = <3>; - label = "eth_fc_1000_9"; - phy-mode = "sgmii"; - managed = "in-band-status"; - sfp = <&sff8>; - }; - - port@4 { - reg = <4>; - label = "eth_fc_1000_10"; - phy-mode = "sgmii"; - managed = "in-band-status"; - sfp = <&sff9>; - }; - - switch3port9: port@9 { - reg = <9>; - label = "dsa"; - phy-mode = "2500base-x"; - link = <&switch2port10>; - }; - - switch3port10: port@10 { - reg = <10>; - label = "dsa"; - phy-mode = "xgmii"; - link = <&switch1port9 - &switch0port10>; - }; - }; - }; - }; - }; - - sff0: sff0 { - compatible = "sff,sff"; - i2c-bus = <&sff0_i2c>; - los-gpios = <&gpio9 0 GPIO_ACTIVE_HIGH>; - tx-disable-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; - }; - - sff1: sff1 { - compatible = "sff,sff"; - i2c-bus = <&sff1_i2c>; - los-gpios = <&gpio9 1 GPIO_ACTIVE_HIGH>; - tx-disable-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; - }; - - sff2: sff2 { - compatible = "sff,sff"; - i2c-bus = <&sff2_i2c>; - los-gpios = <&gpio9 2 GPIO_ACTIVE_HIGH>; - tx-disable-gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>; - }; - - sff3: sff3 { - compatible = "sff,sff"; - i2c-bus = <&sff3_i2c>; - los-gpios = <&gpio9 3 GPIO_ACTIVE_HIGH>; - tx-disable-gpios = <&gpio7 3 GPIO_ACTIVE_HIGH>; - }; - - sff4: sff4 { - compatible = "sff,sff"; - i2c-bus = <&sff4_i2c>; - los-gpios = <&gpio9 4 GPIO_ACTIVE_HIGH>; - tx-disable-gpios = <&gpio7 4 GPIO_ACTIVE_HIGH>; - }; - - sff5: sff5 { - compatible = "sff,sff"; - i2c-bus = <&sff5_i2c>; - los-gpios = <&gpio9 5 GPIO_ACTIVE_HIGH>; - tx-disable-gpios = <&gpio7 5 GPIO_ACTIVE_HIGH>; - }; - - sff6: sff6 { - compatible = "sff,sff"; - i2c-bus = <&sff6_i2c>; - los-gpios = <&gpio9 6 GPIO_ACTIVE_HIGH>; - tx-disable-gpios = <&gpio7 6 GPIO_ACTIVE_HIGH>; - }; - - sff7: sff7 { - compatible = "sff,sff"; - i2c-bus = <&sff7_i2c>; - los-gpios = <&gpio9 7 GPIO_ACTIVE_HIGH>; - tx-disable-gpios = <&gpio7 7 GPIO_ACTIVE_HIGH>; - }; - - sff8: sff8 { - compatible = "sff,sff"; - i2c-bus = <&sff8_i2c>; - los-gpios = <&gpio9 8 GPIO_ACTIVE_HIGH>; - tx-disable-gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>; - }; - - sff9: sff9 { - compatible = "sff,sff"; - i2c-bus = <&sff9_i2c>; - los-gpios = <&gpio9 9 GPIO_ACTIVE_HIGH>; - tx-disable-gpios = <&gpio7 9 GPIO_ACTIVE_HIGH>; - }; - - reg_vcc_3v3_mcu: regulator-vcc-3v3-mcu { - compatible = "regulator-fixed"; - regulator-name = "vcc_3v3_mcu"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&dspi0 { - pinctrl-0 = <&pinctrl_dspi0>; - pinctrl-names = "default"; - bus-num = <0>; - status = "okay"; - - adc@5 { - compatible = "holt,hi8435"; - reg = <5>; - gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>; - spi-max-frequency = <1000000>; - }; -}; - -&dspi1 { - bus-num = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_dspi1>; - status = "okay"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <50000000>; - - partition@0 { - label = "m25p128-0"; - reg = <0x0 0x01000000>; - }; - }; - - flash@1 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <1>; - spi-max-frequency = <50000000>; - - partition@0 { - label = "m25p128-1"; - reg = <0x0 0x01000000>; - }; - }; -}; - -&adc0 { - vref-supply = <®_vcc_3v3_mcu>; - status = "okay"; -}; - -&adc1 { - vref-supply = <®_vcc_3v3_mcu>; - status = "okay"; -}; - -&edma0 { - status = "okay"; -}; - -&edma1 { - status = "okay"; -}; - -&esdhc0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc0>; - bus-width = <8>; - non-removable; - no-1-8-v; - no-sd; - no-sdio; - keep-power-in-suspend; - status = "okay"; -}; - -&esdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc1>; - bus-width = <4>; - no-sdio; - status = "okay"; -}; - -&fec1 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - status = "okay"; - - fixed-link { - speed = <100>; - full-duplex; - }; - - mdio1: mdio { - #address-cells = <1>; - #size-cells = <0>; - }; -}; - -&i2c0 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - status = "okay"; - - gpio5: io-expander@20 { - compatible = "nxp,pca9554"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - }; - - gpio6: io-expander@22 { - compatible = "nxp,pca9554"; - reg = <0x22>; - gpio-controller; - #gpio-cells = <2>; - }; - - temp-sensor@48 { - compatible = "national,lm75"; - reg = <0x48>; - }; - - eeprom@50 { - compatible = "atmel,24c04"; - reg = <0x50>; - }; - - eeprom@52 { - compatible = "atmel,24c04"; - reg = <0x52>; - }; - - elapsed-time-recorder@6b { - compatible = "dallas,ds1682"; - reg = <0x6b>; - }; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - watchdog@38 { - compatible = "zii,rave-wdt"; - reg = <0x38>; - }; - - adc@4a { - compatible = "adi,adt7411"; - reg = <0x4a>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - gpio9: io-expander@20 { - compatible = "semtech,sx1503q"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sx1503_20>; - #gpio-cells = <2>; - reg = <0x20>; - gpio-controller; - interrupt-parent = <&gpio1>; - interrupts = <31 IRQ_TYPE_EDGE_FALLING>; - }; - - temp-sensor@4e { - compatible = "national,lm75"; - reg = <0x4e>; - }; - - temp-sensor@4f { - compatible = "national,lm75"; - reg = <0x4f>; - }; - - gpio7: io-expander@23 { - compatible = "nxp,pca9555"; - gpio-controller; - #gpio-cells = <2>; - reg = <0x23>; - }; - - adc@4a { - compatible = "adi,adt7411"; - reg = <0x4a>; - }; - - eeprom@54 { - compatible = "atmel,24c08"; - reg = <0x54>; - }; - - i2c-mux@70 { - compatible = "nxp,pca9548"; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x70>; - i2c-mux-idle-disconnect; - - sff0_i2c: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - sff1_i2c: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - sff2_i2c: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - - sff3_i2c: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - - sff4_i2c: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - }; - - i2c-mux@71 { - compatible = "nxp,pca9548"; - pinctrl-names = "default"; - reg = <0x71>; - #address-cells = <1>; - #size-cells = <0>; - i2c-mux-idle-disconnect; - - sff5_i2c: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - sff6_i2c: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - sff7_i2c: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - - sff8_i2c: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - - sff9_i2c: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - }; -}; - -&snvsrtc { - status = "disabled"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0>; - status = "okay"; -}; - -&uart1 { - linux,rs485-enabled-at-boot-time; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - linux,rs485-enabled-at-boot-time; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&iomuxc { - pinctrl_dspi0: dspi0grp { - fsl,pins = < - VF610_PAD_PTB19__DSPI0_CS0 0x1182 - VF610_PAD_PTB18__DSPI0_CS1 0x1182 - VF610_PAD_PTB13__DSPI0_CS4 0x1182 - VF610_PAD_PTB12__DSPI0_CS5 0x1182 - VF610_PAD_PTB20__DSPI0_SIN 0x1181 - VF610_PAD_PTB21__DSPI0_SOUT 0x1182 - VF610_PAD_PTB22__DSPI0_SCK 0x1182 - >; - }; - - pinctrl_dspi1: dspi1grp { - fsl,pins = < - VF610_PAD_PTD5__DSPI1_CS0 0x1182 - VF610_PAD_PTD4__DSPI1_CS1 0x1182 - VF610_PAD_PTC6__DSPI1_SIN 0x1181 - VF610_PAD_PTC7__DSPI1_SOUT 0x1182 - VF610_PAD_PTC8__DSPI1_SCK 0x1182 - >; - }; - - pinctrl_dspi2: dspi2gpio { - fsl,pins = < - VF610_PAD_PTD30__GPIO_64 0x33e2 - VF610_PAD_PTD29__GPIO_65 0x33e1 - VF610_PAD_PTD28__GPIO_66 0x33e2 - VF610_PAD_PTD27__GPIO_67 0x33e2 - VF610_PAD_PTD26__GPIO_68 0x31c2 - >; - }; - - pinctrl_esdhc0: esdhc0grp { - fsl,pins = < - VF610_PAD_PTC0__ESDHC0_CLK 0x31ef - VF610_PAD_PTC1__ESDHC0_CMD 0x31ef - VF610_PAD_PTC2__ESDHC0_DAT0 0x31ef - VF610_PAD_PTC3__ESDHC0_DAT1 0x31ef - VF610_PAD_PTC4__ESDHC0_DAT2 0x31ef - VF610_PAD_PTC5__ESDHC0_DAT3 0x31ef - VF610_PAD_PTD23__ESDHC0_DAT4 0x31ef - VF610_PAD_PTD22__ESDHC0_DAT5 0x31ef - VF610_PAD_PTD21__ESDHC0_DAT6 0x31ef - VF610_PAD_PTD20__ESDHC0_DAT7 0x31ef - >; - }; - - pinctrl_esdhc1: esdhc1grp { - fsl,pins = < - VF610_PAD_PTA24__ESDHC1_CLK 0x31ef - VF610_PAD_PTA25__ESDHC1_CMD 0x31ef - VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef - VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef - VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef - VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef - >; - }; - - pinctrl_fec1: fec1grp { - fsl,pins = < - VF610_PAD_PTA6__RMII_CLKIN 0x30d1 - VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2 - VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3 - VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1 - VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1 - VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1 - VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1 - VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2 - VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2 - VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2 - >; - }; - - pinctrl_i2c0: i2c0grp { - fsl,pins = < - VF610_PAD_PTB14__I2C0_SCL 0x37ff - VF610_PAD_PTB15__I2C0_SDA 0x37ff - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - VF610_PAD_PTB16__I2C1_SCL 0x37ff - VF610_PAD_PTB17__I2C1_SDA 0x37ff - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - VF610_PAD_PTA22__I2C2_SCL 0x37ff - VF610_PAD_PTA23__I2C2_SDA 0x37ff - >; - }; - - pinctrl_leds_debug: pinctrl-leds-debug { - fsl,pins = < - VF610_PAD_PTB26__GPIO_96 0x31c2 - >; - }; - - pinctrl_mdio_mux: pinctrl-mdio-mux { - fsl,pins = < - VF610_PAD_PTE27__GPIO_132 0x31c2 - VF610_PAD_PTE28__GPIO_133 0x31c2 - VF610_PAD_PTE21__GPIO_126 0x31c2 - VF610_PAD_PTE22__GPIO_127 0x31c2 - >; - }; - - pinctrl_qspi0: qspi0grp { - fsl,pins = < - VF610_PAD_PTD7__QSPI0_B_QSCK 0x31c3 - VF610_PAD_PTD8__QSPI0_B_CS0 0x31ff - VF610_PAD_PTD9__QSPI0_B_DATA3 0x31c3 - VF610_PAD_PTD10__QSPI0_B_DATA2 0x31c3 - VF610_PAD_PTD11__QSPI0_B_DATA1 0x31c3 - VF610_PAD_PTD12__QSPI0_B_DATA0 0x31c3 - >; - }; - - pinctrl_sx1503_20: pinctrl-sx1503-20 { - fsl,pins = < - VF610_PAD_PTD31__GPIO_63 0x219d - >; - }; - - pinctrl_uart0: uart0grp { - fsl,pins = < - VF610_PAD_PTB10__UART0_TX 0x21a2 - VF610_PAD_PTB11__UART0_RX 0x21a1 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - VF610_PAD_PTB23__UART1_TX 0x21a2 - VF610_PAD_PTB24__UART1_RX 0x21a1 - VF610_PAD_PTB25__UART1_RTS 0x21a2 /* Used as DE signal for the RS-485 transceiver */ - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - VF610_PAD_PTD0__UART2_TX 0x21a2 - VF610_PAD_PTD1__UART2_RX 0x21a1 - VF610_PAD_PTD2__UART2_RTS 0x21a2 /* Used as DE signal for the RS-485 transceiver */ - >; - }; -}; diff --git a/sys/gnu/dts/arm/vf610-zii-spb4.dts b/sys/gnu/dts/arm/vf610-zii-spb4.dts deleted file mode 100644 index 77e1484211e..00000000000 --- a/sys/gnu/dts/arm/vf610-zii-spb4.dts +++ /dev/null @@ -1,352 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) - -/* - * Device tree file for ZII's SPB4 board - * - * SPB - Seat Power Box - * - * Copyright (C) 2019 Zodiac Inflight Innovations - */ - -/dts-v1/; -#include "vf610.dtsi" - -/ { - model = "ZII VF610 SPB4 Board"; - compatible = "zii,vf610spb4", "zii,vf610dev", "fsl,vf610"; - - chosen { - stdout-path = &uart0; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000>; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pinctrl_leds_debug>; - pinctrl-names = "default"; - - led-debug { - label = "zii:green:debug1"; - gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - reg_vcc_3v3_mcu: regulator-vcc-3v3-mcu { - compatible = "regulator-fixed"; - regulator-name = "vcc_3v3_mcu"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&adc0 { - vref-supply = <®_vcc_3v3_mcu>; - status = "okay"; -}; - -&adc1 { - vref-supply = <®_vcc_3v3_mcu>; - status = "okay"; -}; - -&dspi1 { - bus-num = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_dspi1>; - status = "okay"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "m25p128", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <50000000>; - }; -}; - -&edma0 { - status = "okay"; -}; - -&edma1 { - status = "okay"; -}; - -&esdhc0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc0>; - bus-width = <8>; - non-removable; - no-1-8-v; - keep-power-in-suspend; - no-sdio; - no-sd; - status = "okay"; -}; - -&esdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc1>; - bus-width = <4>; - no-sdio; - status = "okay"; -}; - -&fec1 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - status = "okay"; - - fixed-link { - speed = <100>; - full-duplex; - }; - - mdio1: mdio { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - switch0: switch0@0 { - compatible = "marvell,mv88e6190"; - pinctrl-0 = <&pinctrl_gpio_switch0>; - pinctrl-names = "default"; - reg = <0>; - eeprom-length = <65536>; - reset-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>; - interrupt-parent = <&gpio3>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells = <2>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "cpu"; - ethernet = <&fec1>; - - fixed-link { - speed = <100>; - full-duplex; - }; - }; - - port@1 { - reg = <1>; - label = "eth_cu_1000_1"; - }; - - port@2 { - reg = <2>; - label = "eth_cu_1000_2"; - }; - - port@3 { - reg = <3>; - label = "eth_cu_1000_3"; - }; - - port@4 { - reg = <4>; - label = "eth_cu_1000_4"; - }; - - port@5 { - reg = <5>; - label = "eth_cu_1000_5"; - }; - - port@6 { - reg = <6>; - label = "eth_cu_1000_6"; - }; - }; - }; - }; -}; - -&i2c0 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - status = "okay"; - - io-expander@22 { - compatible = "nxp,pca9554"; - reg = <0x22>; - gpio-controller; - #gpio-cells = <2>; - }; - - eeprom@50 { - compatible = "atmel,24c04"; - reg = <0x50>; - label = "nameplate"; - }; - - eeprom@52 { - compatible = "atmel,24c04"; - reg = <0x52>; - }; -}; - -&snvsrtc { - status = "disabled"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; - - rave-sp { - compatible = "zii,rave-sp-rdu2"; - current-speed = <1000000>; - #address-cells = <1>; - #size-cells = <1>; - - watchdog { - compatible = "zii,rave-sp-watchdog"; - }; - - eeprom@a3 { - compatible = "zii,rave-sp-eeprom"; - reg = <0xa3 0x4000>; - #address-cells = <1>; - #size-cells = <1>; - zii,eeprom-name = "main-eeprom"; - }; - }; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -&wdoga5 { - status = "disabled"; -}; - -&iomuxc { - pinctrl_dspi1: dspi1grp { - fsl,pins = < - VF610_PAD_PTD5__DSPI1_CS0 0x1182 - VF610_PAD_PTD4__DSPI1_CS1 0x1182 - VF610_PAD_PTC6__DSPI1_SIN 0x1181 - VF610_PAD_PTC7__DSPI1_SOUT 0x1182 - VF610_PAD_PTC8__DSPI1_SCK 0x1182 - >; - }; - - pinctrl_esdhc0: esdhc0grp { - fsl,pins = < - VF610_PAD_PTC0__ESDHC0_CLK 0x31ef - VF610_PAD_PTC1__ESDHC0_CMD 0x31ef - VF610_PAD_PTC2__ESDHC0_DAT0 0x31ef - VF610_PAD_PTC3__ESDHC0_DAT1 0x31ef - VF610_PAD_PTC4__ESDHC0_DAT2 0x31ef - VF610_PAD_PTC5__ESDHC0_DAT3 0x31ef - VF610_PAD_PTD23__ESDHC0_DAT4 0x31ef - VF610_PAD_PTD22__ESDHC0_DAT5 0x31ef - VF610_PAD_PTD21__ESDHC0_DAT6 0x31ef - VF610_PAD_PTD20__ESDHC0_DAT7 0x31ef - >; - }; - - pinctrl_esdhc1: esdhc1grp { - fsl,pins = < - VF610_PAD_PTA24__ESDHC1_CLK 0x31ef - VF610_PAD_PTA25__ESDHC1_CMD 0x31ef - VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef - VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef - VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef - VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef - >; - }; - - pinctrl_fec1: fec1grp { - fsl,pins = < - VF610_PAD_PTA6__RMII_CLKIN 0x30d1 - VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2 - VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3 - VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1 - VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1 - VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1 - VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1 - VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2 - VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2 - VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2 - >; - }; - - pinctrl_gpio_switch0: pinctrl-gpio-switch0 { - fsl,pins = < - VF610_PAD_PTE2__GPIO_107 0x31c2 - VF610_PAD_PTB28__GPIO_98 0x219d - >; - }; - - pinctrl_i2c0: i2c0grp { - fsl,pins = < - VF610_PAD_PTB14__I2C0_SCL 0x37ff - VF610_PAD_PTB15__I2C0_SDA 0x37ff - >; - }; - - pinctrl_leds_debug: pinctrl-leds-debug { - fsl,pins = < - VF610_PAD_PTD3__GPIO_82 0x31c2 - >; - }; - - pinctrl_uart0: uart0grp { - fsl,pins = < - VF610_PAD_PTB10__UART0_TX 0x21a2 - VF610_PAD_PTB11__UART0_RX 0x21a1 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - VF610_PAD_PTB23__UART1_TX 0x21a2 - VF610_PAD_PTB24__UART1_RX 0x21a1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - VF610_PAD_PTD0__UART2_TX 0x21a2 - VF610_PAD_PTD1__UART2_RX 0x21a1 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - VF610_PAD_PTA30__UART3_TX 0x21a2 - VF610_PAD_PTA31__UART3_RX 0x21a1 - >; - }; -}; diff --git a/sys/gnu/dts/arm/vf610-zii-ssmb-dtu.dts b/sys/gnu/dts/arm/vf610-zii-ssmb-dtu.dts deleted file mode 100644 index 847c5858fea..00000000000 --- a/sys/gnu/dts/arm/vf610-zii-ssmb-dtu.dts +++ /dev/null @@ -1,314 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) - -/* - * Device tree file for ZII's SSMB DTU board - * - * SSMB - SPU3 Switch Management Board - * DTU - Digital Tapping Unit - * - * Copyright (C) 2015-2019 Zodiac Inflight Innovations - * - * Based on an original 'vf610-twr.dts' which is Copyright 2015, - * Freescale Semiconductor, Inc. - */ - -/dts-v1/; -#include "vf610.dtsi" - -/ { - model = "ZII VF610 SSMB DTU Board"; - compatible = "zii,vf610dtu", "zii,vf610dev", "fsl,vf610"; - - chosen { - stdout-path = &uart0; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000>; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pinctrl_leds_debug>; - pinctrl-names = "default"; - - led-debug { - label = "zii:green:debug1"; - gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - reg_vcc_3v3_mcu: regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_3v3_mcu"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&adc0 { - vref-supply = <®_vcc_3v3_mcu>; - status = "okay"; -}; - -&adc1 { - vref-supply = <®_vcc_3v3_mcu>; - status = "okay"; -}; - -&edma0 { - status = "okay"; -}; - -&edma1 { - status = "okay"; -}; - -&esdhc0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc0>; - bus-width = <8>; - non-removable; - no-1-8-v; - keep-power-in-suspend; - status = "okay"; -}; - -&esdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc1>; - bus-width = <4>; - status = "okay"; -}; - -&fec1 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - status = "okay"; - - fixed-link { - speed = <100>; - full-duplex; - }; - - mdio1: mdio { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - switch0: switch0@0 { - compatible = "marvell,mv88e6190"; - pinctrl-0 = <&pinctrl_gpio_switch0>; - pinctrl-names = "default"; - reg = <0>; - eeprom-length = <65536>; - reset-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>; - interrupt-parent = <&gpio3>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells = <2>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "cpu"; - ethernet = <&fec1>; - - fixed-link { - speed = <100>; - full-duplex; - }; - }; - - port@1 { - reg = <1>; - label = "eth_cu_100_3"; - }; - - port@5 { - reg = <5>; - label = "eth_cu_1000_4"; - }; - - port@6 { - reg = <6>; - label = "eth_cu_1000_5"; - }; - - port@8 { - reg = <8>; - label = "eth_cu_1000_1"; - }; - - port@9 { - reg = <9>; - label = "eth_cu_1000_2"; - phy-handle = <&phy9>; - phy-mode = "sgmii"; - managed = "in-band-status"; - }; - }; - - mdio1 { - compatible = "marvell,mv88e6xxx-mdio-external"; - #address-cells = <1>; - #size-cells = <0>; - - phy9: phy9@0 { - compatible = "ethernet-phy-ieee802.3-c45"; - pinctrl-0 = <&pinctrl_gpio_phy9>; - pinctrl-names = "default"; - interrupt-parent = <&gpio2>; - interrupts = <30 IRQ_TYPE_LEVEL_LOW>; - reg = <0>; - }; - }; - }; - }; -}; - -&i2c0 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - status = "okay"; - - gpio6: gpio-expander@22 { - compatible = "nxp,pca9554"; - reg = <0x22>; - gpio-controller; - #gpio-cells = <2>; - }; - - /* On SSMB */ - temperature-sensor@48 { - compatible = "national,lm75"; - reg = <0x48>; - }; - - /* On DSB */ - temperature-sensor@4d { - compatible = "national,lm75"; - reg = <0x4d>; - }; - - eeprom@50 { - compatible = "atmel,24c04"; - reg = <0x50>; - label = "nameplate"; - }; - - eeprom@52 { - compatible = "atmel,24c04"; - reg = <0x52>; - }; -}; - -&snvsrtc { - status = "disabled"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0>; - status = "okay"; -}; - -&iomuxc { - pinctrl_dspi1: dspi1grp { - fsl,pins = < - VF610_PAD_PTD5__DSPI1_CS0 0x1182 - VF610_PAD_PTD4__DSPI1_CS1 0x1182 - VF610_PAD_PTC6__DSPI1_SIN 0x1181 - VF610_PAD_PTC7__DSPI1_SOUT 0x1182 - VF610_PAD_PTC8__DSPI1_SCK 0x1182 - >; - }; - - pinctrl_esdhc0: esdhc0grp { - fsl,pins = < - VF610_PAD_PTC0__ESDHC0_CLK 0x31ef - VF610_PAD_PTC1__ESDHC0_CMD 0x31ef - VF610_PAD_PTC2__ESDHC0_DAT0 0x31ef - VF610_PAD_PTC3__ESDHC0_DAT1 0x31ef - VF610_PAD_PTC4__ESDHC0_DAT2 0x31ef - VF610_PAD_PTC5__ESDHC0_DAT3 0x31ef - VF610_PAD_PTD23__ESDHC0_DAT4 0x31ef - VF610_PAD_PTD22__ESDHC0_DAT5 0x31ef - VF610_PAD_PTD21__ESDHC0_DAT6 0x31ef - VF610_PAD_PTD20__ESDHC0_DAT7 0x31ef - >; - }; - - pinctrl_esdhc1: esdhc1grp { - fsl,pins = < - VF610_PAD_PTA24__ESDHC1_CLK 0x31ef - VF610_PAD_PTA25__ESDHC1_CMD 0x31ef - VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef - VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef - VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef - VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef - >; - }; - - pinctrl_fec1: fec1grp { - fsl,pins = < - VF610_PAD_PTA6__RMII_CLKIN 0x30d1 - VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2 - VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3 - VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1 - VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1 - VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1 - VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1 - VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2 - VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2 - VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2 - >; - }; - - pinctrl_gpio_phy9: pinctrl-gpio-phy9 { - fsl,pins = < - VF610_PAD_PTB24__GPIO_94 0x219d - >; - }; - - pinctrl_gpio_switch0: pinctrl-gpio-switch0 { - fsl,pins = < - VF610_PAD_PTE2__GPIO_107 0x31c2 - VF610_PAD_PTB28__GPIO_98 0x219d - >; - }; - - pinctrl_i2c0: i2c0grp { - fsl,pins = < - VF610_PAD_PTB14__I2C0_SCL 0x37ff - VF610_PAD_PTB15__I2C0_SDA 0x37ff - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - VF610_PAD_PTB16__I2C1_SCL 0x37ff - VF610_PAD_PTB17__I2C1_SDA 0x37ff - >; - }; - - pinctrl_leds_debug: pinctrl-leds-debug { - fsl,pins = < - VF610_PAD_PTD3__GPIO_82 0x31c2 - >; - }; - - pinctrl_uart0: uart0grp { - fsl,pins = < - VF610_PAD_PTB10__UART0_TX 0x21a2 - VF610_PAD_PTB11__UART0_RX 0x21a1 - >; - }; -}; diff --git a/sys/gnu/dts/arm/vf610-zii-ssmb-spu3.dts b/sys/gnu/dts/arm/vf610-zii-ssmb-spu3.dts deleted file mode 100644 index 453fce80f85..00000000000 --- a/sys/gnu/dts/arm/vf610-zii-ssmb-spu3.dts +++ /dev/null @@ -1,352 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) - -/* - * Device tree file for ZII's SSMB SPU3 board - * - * SSMB - SPU3 Switch Management Board - * SPU - Seat Power Unit - * - * Copyright (C) 2015, 2016 Zodiac Inflight Innovations - * - * Based on an original 'vf610-twr.dts' which is Copyright 2015, - * Freescale Semiconductor, Inc. - */ - -/dts-v1/; -#include "vf610.dtsi" - -/ { - model = "ZII VF610 SSMB SPU3 Board"; - compatible = "zii,vf610spu3", "zii,vf610dev", "fsl,vf610"; - - chosen { - stdout-path = &uart0; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000>; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pinctrl_leds_debug>; - pinctrl-names = "default"; - - led-debug { - label = "zii:green:debug1"; - gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - reg_vcc_3v3_mcu: regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_3v3_mcu"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&adc0 { - vref-supply = <®_vcc_3v3_mcu>; - status = "okay"; -}; - -&adc1 { - vref-supply = <®_vcc_3v3_mcu>; - status = "okay"; -}; - -&dspi1 { - bus-num = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_dspi1>; - /* - * Some SPU3s come with SPI-NOR chip DNPed, so we leave this - * node disabled by default and rely on bootloader to enable - * it when appropriate. - */ - status = "disabled"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "m25p128", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <50000000>; - - partition@0 { - label = "m25p128-0"; - reg = <0x0 0x01000000>; - }; - }; -}; - -&edma0 { - status = "okay"; -}; - -&edma1 { - status = "okay"; -}; - -&esdhc0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc0>; - bus-width = <8>; - non-removable; - no-1-8-v; - keep-power-in-suspend; - no-sdio; - no-sd; - status = "okay"; -}; - -&esdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc1>; - bus-width = <4>; - no-sdio; - status = "okay"; -}; - -&fec1 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - status = "okay"; - - fixed-link { - speed = <100>; - full-duplex; - }; - - mdio1: mdio { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - switch0: switch0@0 { - compatible = "marvell,mv88e6190"; - pinctrl-0 = <&pinctrl_gpio_switch0>; - pinctrl-names = "default"; - reg = <0>; - eeprom-length = <65536>; - reset-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>; - interrupt-parent = <&gpio3>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells = <2>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "cpu"; - ethernet = <&fec1>; - - fixed-link { - speed = <100>; - full-duplex; - }; - }; - - port@1 { - reg = <1>; - label = "eth_cu_1000_1"; - }; - - port@2 { - reg = <2>; - label = "eth_cu_1000_2"; - }; - - port@3 { - reg = <3>; - label = "eth_cu_1000_3"; - }; - - port@4 { - reg = <4>; - label = "eth_cu_1000_4"; - }; - - port@5 { - reg = <5>; - label = "eth_cu_1000_5"; - }; - - port@6 { - reg = <6>; - label = "eth_cu_1000_6"; - }; - }; - }; - }; -}; - -&i2c0 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - status = "okay"; - - gpio6: io-expander@22 { - compatible = "nxp,pca9554"; - reg = <0x22>; - gpio-controller; - #gpio-cells = <2>; - }; - - lm75@48 { - compatible = "national,lm75"; - reg = <0x48>; - }; - - eeprom@50 { - compatible = "atmel,24c04"; - reg = <0x50>; - label = "nameplate"; - }; - - eeprom@52 { - compatible = "atmel,24c04"; - reg = <0x52>; - }; -}; - -&snvsrtc { - status = "disabled"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; - - rave-sp { - compatible = "zii,rave-sp-rdu2"; - current-speed = <1000000>; - #address-cells = <1>; - #size-cells = <1>; - - watchdog { - compatible = "zii,rave-sp-watchdog"; - }; - - eeprom@a3 { - compatible = "zii,rave-sp-eeprom"; - reg = <0xa3 0x4000>; - #address-cells = <1>; - #size-cells = <1>; - zii,eeprom-name = "main-eeprom"; - }; - }; -}; - -&wdoga5 { - status = "disabled"; -}; - -&iomuxc { - pinctrl_dspi1: dspi1grp { - fsl,pins = < - VF610_PAD_PTD5__DSPI1_CS0 0x1182 - VF610_PAD_PTD4__DSPI1_CS1 0x1182 - VF610_PAD_PTC6__DSPI1_SIN 0x1181 - VF610_PAD_PTC7__DSPI1_SOUT 0x1182 - VF610_PAD_PTC8__DSPI1_SCK 0x1182 - >; - }; - - pinctrl_esdhc0: esdhc0grp { - fsl,pins = < - VF610_PAD_PTC0__ESDHC0_CLK 0x31ef - VF610_PAD_PTC1__ESDHC0_CMD 0x31ef - VF610_PAD_PTC2__ESDHC0_DAT0 0x31ef - VF610_PAD_PTC3__ESDHC0_DAT1 0x31ef - VF610_PAD_PTC4__ESDHC0_DAT2 0x31ef - VF610_PAD_PTC5__ESDHC0_DAT3 0x31ef - VF610_PAD_PTD23__ESDHC0_DAT4 0x31ef - VF610_PAD_PTD22__ESDHC0_DAT5 0x31ef - VF610_PAD_PTD21__ESDHC0_DAT6 0x31ef - VF610_PAD_PTD20__ESDHC0_DAT7 0x31ef - >; - }; - - pinctrl_esdhc1: esdhc1grp { - fsl,pins = < - VF610_PAD_PTA24__ESDHC1_CLK 0x31ef - VF610_PAD_PTA25__ESDHC1_CMD 0x31ef - VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef - VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef - VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef - VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef - >; - }; - - pinctrl_fec1: fec1grp { - fsl,pins = < - VF610_PAD_PTA6__RMII_CLKIN 0x30d1 - VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2 - VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3 - VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1 - VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1 - VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1 - VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1 - VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2 - VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2 - VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2 - >; - }; - - pinctrl_gpio_switch0: pinctrl-gpio-switch0 { - fsl,pins = < - VF610_PAD_PTE2__GPIO_107 0x31c2 - VF610_PAD_PTB28__GPIO_98 0x219d - >; - }; - - pinctrl_i2c0: i2c0grp { - fsl,pins = < - VF610_PAD_PTB14__I2C0_SCL 0x37ff - VF610_PAD_PTB15__I2C0_SDA 0x37ff - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - VF610_PAD_PTB16__I2C1_SCL 0x37ff - VF610_PAD_PTB17__I2C1_SDA 0x37ff - >; - }; - - pinctrl_leds_debug: pinctrl-leds-debug { - fsl,pins = < - VF610_PAD_PTD3__GPIO_82 0x31c2 - >; - }; - - pinctrl_uart0: uart0grp { - fsl,pins = < - VF610_PAD_PTB10__UART0_TX 0x21a2 - VF610_PAD_PTB11__UART0_RX 0x21a1 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - VF610_PAD_PTB23__UART1_TX 0x21a2 - VF610_PAD_PTB24__UART1_RX 0x21a1 - >; - }; -}; diff --git a/sys/gnu/dts/arm/vf610.dtsi b/sys/gnu/dts/arm/vf610.dtsi deleted file mode 100644 index 7fd39817f8a..00000000000 --- a/sys/gnu/dts/arm/vf610.dtsi +++ /dev/null @@ -1,21 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -// -// Copyright 2013 Freescale Semiconductor, Inc. - - -#include "vf500.dtsi" - -&a5_cpu { - next-level-cache = <&L2>; -}; - -&aips0 { - L2: l2-cache@40006000 { - compatible = "arm,pl310-cache"; - reg = <0x40006000 0x1000>; - cache-unified; - cache-level = <2>; - arm,data-latency = <3 3 3>; - arm,tag-latency = <2 2 2>; - }; -}; diff --git a/sys/gnu/dts/arm/vf610m4-colibri.dts b/sys/gnu/dts/arm/vf610m4-colibri.dts deleted file mode 100644 index d4bc0e3f2f1..00000000000 --- a/sys/gnu/dts/arm/vf610m4-colibri.dts +++ /dev/null @@ -1,100 +0,0 @@ -/* - * Device tree for Colibri VF61 Cortex-M4 support - * - * Copyright (C) 2015 Stefan Agner - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "vf610m4.dtsi" - -/ { - model = "VF610 Cortex-M4"; - compatible = "fsl,vf610m4"; - - chosen { - bootargs = "clk_ignore_unused init=/linuxrc rw"; - stdout-path = "serial2:115200"; - }; - - memory@8c000000 { - device_type = "memory"; - reg = <0x8c000000 0x3000000>; - }; -}; - -&gpio0 { - status = "disabled"; -}; - -&gpio1 { - status = "disabled"; -}; - -&gpio2 { - status = "disabled"; -}; - -&gpio3 { - status = "disabled"; -}; - -&gpio4 { - status = "disabled"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&iomuxc { - vf610-colibri { - pinctrl_uart2: uart2grp { - fsl,pins = < - VF610_PAD_PTD0__UART2_TX 0x21a2 - VF610_PAD_PTD1__UART2_RX 0x21a1 - VF610_PAD_PTD2__UART2_RTS 0x21a2 - VF610_PAD_PTD3__UART2_CTS 0x21a1 - >; - }; - }; -}; diff --git a/sys/gnu/dts/arm/vf610m4-cosmic.dts b/sys/gnu/dts/arm/vf610m4-cosmic.dts deleted file mode 100644 index f7474c11aab..00000000000 --- a/sys/gnu/dts/arm/vf610m4-cosmic.dts +++ /dev/null @@ -1,90 +0,0 @@ -/* - * Device tree for Cosmic+ VF6xx Cortex-M4 support - * - * Copyright (C) 2015 - * - * Based on vf610m4 Colibri - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "vf610m4.dtsi" - -/ { - model = "VF610 Cortex-M4"; - compatible = "fsl,vf610m4"; -}; - -&gpio0 { - status = "disabled"; -}; - -&gpio1 { - status = "disabled"; -}; - -&gpio2 { - status = "disabled"; -}; - -&gpio3 { - status = "disabled"; -}; - -&gpio4 { - status = "disabled"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -&iomuxc { - vf610-cosmic { - pinctrl_uart3: uart3grp { - fsl,pins = < - VF610_PAD_PTA20__UART3_TX 0x21a2 - VF610_PAD_PTA21__UART3_RX 0x21a1 - >; - }; - }; -}; diff --git a/sys/gnu/dts/arm/vf610m4.dtsi b/sys/gnu/dts/arm/vf610m4.dtsi deleted file mode 100644 index 76bbfd5e32b..00000000000 --- a/sys/gnu/dts/arm/vf610m4.dtsi +++ /dev/null @@ -1,57 +0,0 @@ -/* - * Device tree for VF6xx Cortex-M4 support - * - * Copyright (C) 2015 Stefan Agner - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "armv7-m.dtsi" -#include "vfxxx.dtsi" - -/ { - #address-cells = <1>; - #size-cells = <1>; - chosen { }; - aliases { }; -}; - -&mscm_ir { - interrupt-parent = <&nvic>; -}; diff --git a/sys/gnu/dts/arm/vfxxx.dtsi b/sys/gnu/dts/arm/vfxxx.dtsi deleted file mode 100644 index 028e0ec30e0..00000000000 --- a/sys/gnu/dts/arm/vfxxx.dtsi +++ /dev/null @@ -1,734 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -// -// Copyright 2013 Freescale Semiconductor, Inc. - -#include "vf610-pinfunc.h" -#include -#include -#include - -/ { - aliases { - can0 = &can0; - can1 = &can1; - ethernet0 = &fec0; - ethernet1 = &fec1; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - serial4 = &uart4; - serial5 = &uart5; - gpio0 = &gpio0; - gpio1 = &gpio1; - gpio2 = &gpio2; - gpio3 = &gpio3; - gpio4 = &gpio4; - usbphy0 = &usbphy0; - usbphy1 = &usbphy1; - }; - - fxosc: fxosc { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - }; - - sxosc: sxosc { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - - reboot: syscon-reboot { - compatible = "syscon-reboot"; - regmap = <&src>; - offset = <0x0>; - mask = <0x1000>; - }; - - tempsensor: iio-hwmon { - compatible = "iio-hwmon"; - io-channels = <&adc0 16>, <&adc1 16>; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&mscm_ir>; - ranges; - - aips0: aips-bus@40000000 { - compatible = "fsl,aips-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x40000000 0x00070000>; - ranges; - - mscm_cpucfg: cpucfg@40001000 { - compatible = "fsl,vf610-mscm-cpucfg", "syscon"; - reg = <0x40001000 0x800>; - }; - - mscm_ir: interrupt-controller@40001800 { - compatible = "fsl,vf610-mscm-ir"; - reg = <0x40001800 0x400>; - fsl,cpucfg = <&mscm_cpucfg>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - edma0: dma-controller@40018000 { - #dma-cells = <2>; - compatible = "fsl,vf610-edma"; - reg = <0x40018000 0x2000>, - <0x40024000 0x1000>, - <0x40025000 0x1000>; - dma-channels = <32>; - interrupts = <8 IRQ_TYPE_LEVEL_HIGH>, - <9 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "edma-tx", "edma-err"; - clock-names = "dmamux0", "dmamux1"; - clocks = <&clks VF610_CLK_DMAMUX0>, - <&clks VF610_CLK_DMAMUX1>; - status = "disabled"; - }; - - can0: flexcan@40020000 { - compatible = "fsl,vf610-flexcan"; - reg = <0x40020000 0x4000>; - interrupts = <58 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_FLEXCAN0>, - <&clks VF610_CLK_FLEXCAN0>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart0: serial@40027000 { - compatible = "fsl,vf610-lpuart"; - reg = <0x40027000 0x1000>; - interrupts = <61 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_UART0>; - clock-names = "ipg"; - dmas = <&edma0 0 2>, - <&edma0 0 3>; - dma-names = "rx","tx"; - status = "disabled"; - }; - - uart1: serial@40028000 { - compatible = "fsl,vf610-lpuart"; - reg = <0x40028000 0x1000>; - interrupts = <62 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_UART1>; - clock-names = "ipg"; - dmas = <&edma0 0 4>, - <&edma0 0 5>; - dma-names = "rx","tx"; - status = "disabled"; - }; - - uart2: serial@40029000 { - compatible = "fsl,vf610-lpuart"; - reg = <0x40029000 0x1000>; - interrupts = <63 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_UART2>; - clock-names = "ipg"; - dmas = <&edma0 0 6>, - <&edma0 0 7>; - dma-names = "rx","tx"; - status = "disabled"; - }; - - uart3: serial@4002a000 { - compatible = "fsl,vf610-lpuart"; - reg = <0x4002a000 0x1000>; - interrupts = <64 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_UART3>; - clock-names = "ipg"; - dmas = <&edma0 0 8>, - <&edma0 0 9>; - dma-names = "rx","tx"; - status = "disabled"; - }; - - dspi0: spi@4002c000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,vf610-dspi"; - reg = <0x4002c000 0x1000>; - interrupts = <67 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_DSPI0>; - clock-names = "dspi"; - spi-num-chipselects = <6>; - dmas = <&edma1 1 12>, - <&edma1 1 13>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - dspi1: spi@4002d000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,vf610-dspi"; - reg = <0x4002d000 0x1000>; - interrupts = <68 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_DSPI1>; - clock-names = "dspi"; - spi-num-chipselects = <4>; - dmas = <&edma1 1 14>, - <&edma1 1 15>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - sai0: sai@4002f000 { - compatible = "fsl,vf610-sai"; - reg = <0x4002f000 0x1000>; - interrupts = <84 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_SAI0>, - <&clks VF610_CLK_SAI0_DIV>, - <&clks 0>, <&clks 0>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dma-names = "tx", "rx"; - dmas = <&edma0 0 17>, - <&edma0 0 16>; - status = "disabled"; - }; - - sai1: sai@40030000 { - compatible = "fsl,vf610-sai"; - reg = <0x40030000 0x1000>; - interrupts = <85 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_SAI1>, - <&clks VF610_CLK_SAI1_DIV>, - <&clks 0>, <&clks 0>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dma-names = "tx", "rx"; - dmas = <&edma0 0 19>, - <&edma0 0 18>; - status = "disabled"; - }; - - sai2: sai@40031000 { - compatible = "fsl,vf610-sai"; - reg = <0x40031000 0x1000>; - interrupts = <86 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_SAI2>, - <&clks VF610_CLK_SAI2_DIV>, - <&clks 0>, <&clks 0>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dma-names = "tx", "rx"; - dmas = <&edma0 0 21>, - <&edma0 0 20>; - status = "disabled"; - }; - - sai3: sai@40032000 { - compatible = "fsl,vf610-sai"; - reg = <0x40032000 0x1000>; - interrupts = <87 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_SAI3>, - <&clks VF610_CLK_SAI3_DIV>, - <&clks 0>, <&clks 0>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dma-names = "tx", "rx"; - dmas = <&edma0 1 9>, - <&edma0 1 8>; - status = "disabled"; - }; - - pit: pit@40037000 { - compatible = "fsl,vf610-pit"; - reg = <0x40037000 0x1000>; - interrupts = <39 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_PIT>; - clock-names = "pit"; - }; - - pwm0: pwm@40038000 { - compatible = "fsl,vf610-ftm-pwm"; - #pwm-cells = <3>; - reg = <0x40038000 0x1000>; - clock-names = "ftm_sys", "ftm_ext", - "ftm_fix", "ftm_cnt_clk_en"; - clocks = <&clks VF610_CLK_FTM0>, - <&clks VF610_CLK_FTM0_EXT_SEL>, - <&clks VF610_CLK_FTM0_FIX_SEL>, - <&clks VF610_CLK_FTM0_EXT_FIX_EN>; - status = "disabled"; - }; - - pwm1: pwm@40039000 { - compatible = "fsl,vf610-ftm-pwm"; - #pwm-cells = <3>; - reg = <0x40039000 0x1000>; - clock-names = "ftm_sys", "ftm_ext", - "ftm_fix", "ftm_cnt_clk_en"; - clocks = <&clks VF610_CLK_FTM1>, - <&clks VF610_CLK_FTM1_EXT_SEL>, - <&clks VF610_CLK_FTM1_FIX_SEL>, - <&clks VF610_CLK_FTM1_EXT_FIX_EN>; - status = "disabled"; - }; - - adc0: adc@4003b000 { - compatible = "fsl,vf610-adc"; - reg = <0x4003b000 0x1000>; - interrupts = <53 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_ADC0>; - clock-names = "adc"; - #io-channel-cells = <1>; - status = "disabled"; - fsl,adck-max-frequency = <30000000>, <40000000>, - <20000000>; - }; - - tcon0: timing-controller@4003d000 { - compatible = "fsl,vf610-tcon"; - reg = <0x4003d000 0x1000>; - clocks = <&clks VF610_CLK_TCON0>; - clock-names = "ipg"; - status = "disabled"; - }; - - wdoga5: wdog@4003e000 { - compatible = "fsl,vf610-wdt", "fsl,imx21-wdt"; - reg = <0x4003e000 0x1000>; - interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_WDT>; - clock-names = "wdog"; - status = "disabled"; - }; - - qspi0: spi@40044000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,vf610-qspi"; - reg = <0x40044000 0x1000>, <0x20000000 0x10000000>; - reg-names = "QuadSPI", "QuadSPI-memory"; - interrupts = <24 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_QSPI0_EN>, - <&clks VF610_CLK_QSPI0>; - clock-names = "qspi_en", "qspi"; - status = "disabled"; - }; - - iomuxc: iomuxc@40048000 { - compatible = "fsl,vf610-iomuxc"; - reg = <0x40048000 0x1000>; - }; - - gpio0: gpio@40049000 { - compatible = "fsl,vf610-gpio"; - reg = <0x40049000 0x1000 0x400ff000 0x40>; - gpio-controller; - #gpio-cells = <2>; - interrupts = <107 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 0 32>; - }; - - gpio1: gpio@4004a000 { - compatible = "fsl,vf610-gpio"; - reg = <0x4004a000 0x1000 0x400ff040 0x40>; - gpio-controller; - #gpio-cells = <2>; - interrupts = <108 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 32 32>; - }; - - gpio2: gpio@4004b000 { - compatible = "fsl,vf610-gpio"; - reg = <0x4004b000 0x1000 0x400ff080 0x40>; - gpio-controller; - #gpio-cells = <2>; - interrupts = <109 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 64 32>; - }; - - gpio3: gpio@4004c000 { - compatible = "fsl,vf610-gpio"; - reg = <0x4004c000 0x1000 0x400ff0c0 0x40>; - gpio-controller; - #gpio-cells = <2>; - interrupts = <110 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 96 32>; - }; - - gpio4: gpio@4004d000 { - compatible = "fsl,vf610-gpio"; - reg = <0x4004d000 0x1000 0x400ff100 0x40>; - gpio-controller; - #gpio-cells = <2>; - interrupts = <111 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 128 7>; - }; - - anatop: anatop@40050000 { - compatible = "fsl,vf610-anatop", "syscon"; - reg = <0x40050000 0x400>; - }; - - usbphy0: usbphy@40050800 { - compatible = "fsl,vf610-usbphy"; - reg = <0x40050800 0x400>; - interrupts = <50 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_USBPHY0>; - fsl,anatop = <&anatop>; - status = "disabled"; - }; - - usbphy1: usbphy@40050c00 { - compatible = "fsl,vf610-usbphy"; - reg = <0x40050c00 0x400>; - interrupts = <51 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_USBPHY1>; - fsl,anatop = <&anatop>; - status = "disabled"; - }; - - dcu0: dcu@40058000 { - compatible = "fsl,vf610-dcu"; - reg = <0x40058000 0x1200>; - interrupts = <30 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_DCU0>, - <&clks VF610_CLK_DCU0_DIV>; - clock-names = "dcu", "pix"; - fsl,tcon = <&tcon0>; - status = "disabled"; - }; - - i2c0: i2c@40066000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,vf610-i2c"; - reg = <0x40066000 0x1000>; - interrupts = <71 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_I2C0>; - clock-names = "ipg"; - dmas = <&edma0 0 50>, - <&edma0 0 51>; - dma-names = "rx","tx"; - status = "disabled"; - }; - - i2c1: i2c@40067000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,vf610-i2c"; - reg = <0x40067000 0x1000>; - interrupts = <72 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_I2C1>; - clock-names = "ipg"; - dmas = <&edma0 0 52>, - <&edma0 0 53>; - dma-names = "rx","tx"; - status = "disabled"; - }; - - clks: ccm@4006b000 { - compatible = "fsl,vf610-ccm"; - reg = <0x4006b000 0x1000>; - clocks = <&sxosc>, <&fxosc>; - clock-names = "sxosc", "fxosc"; - #clock-cells = <1>; - }; - - usbdev0: usb@40034000 { - compatible = "fsl,vf610-usb", "fsl,imx27-usb"; - reg = <0x40034000 0x800>; - interrupts = <75 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_USBC0>; - fsl,usbphy = <&usbphy0>; - fsl,usbmisc = <&usbmisc0 0>; - dr_mode = "peripheral"; - status = "disabled"; - }; - - usbmisc0: usb@40034800 { - #index-cells = <1>; - compatible = "fsl,vf610-usbmisc"; - reg = <0x40034800 0x200>; - clocks = <&clks VF610_CLK_USBC0>; - status = "disabled"; - }; - - src: src@4006e000 { - compatible = "fsl,vf610-src", "syscon"; - reg = <0x4006e000 0x1000>; - interrupts = <96 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - - aips1: aips-bus@40080000 { - compatible = "fsl,aips-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x40080000 0x0007f000>; - ranges; - - edma1: dma-controller@40098000 { - #dma-cells = <2>; - compatible = "fsl,vf610-edma"; - reg = <0x40098000 0x2000>, - <0x400a1000 0x1000>, - <0x400a2000 0x1000>; - dma-channels = <32>; - interrupts = <10 IRQ_TYPE_LEVEL_HIGH>, - <11 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "edma-tx", "edma-err"; - clock-names = "dmamux0", "dmamux1"; - clocks = <&clks VF610_CLK_DMAMUX2>, - <&clks VF610_CLK_DMAMUX3>; - status = "disabled"; - }; - - ocotp: ocotp@400a5000 { - compatible = "fsl,vf610-ocotp"; - reg = <0x400a5000 0x1000>; - clocks = <&clks VF610_CLK_OCOTP>; - }; - - snvs0: snvs@400a7000 { - compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; - reg = <0x400a7000 0x2000>; - - snvsrtc: snvs-rtc-lp { - compatible = "fsl,sec-v4.0-mon-rtc-lp"; - regmap = <&snvs0>; - offset = <0x34>; - interrupts = <100 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_SNVS>; - clock-names = "snvs-rtc"; - }; - }; - - uart4: serial@400a9000 { - compatible = "fsl,vf610-lpuart"; - reg = <0x400a9000 0x1000>; - interrupts = <65 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_UART4>; - clock-names = "ipg"; - status = "disabled"; - }; - - uart5: serial@400aa000 { - compatible = "fsl,vf610-lpuart"; - reg = <0x400aa000 0x1000>; - interrupts = <66 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_UART5>; - clock-names = "ipg"; - status = "disabled"; - }; - - dspi2: spi@400ac000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,vf610-dspi"; - reg = <0x400ac000 0x1000>; - interrupts = <69 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_DSPI2>; - clock-names = "dspi"; - spi-num-chipselects = <2>; - dmas = <&edma1 0 10>, - <&edma1 0 11>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - dspi3: spi@400ad000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,vf610-dspi"; - reg = <0x400ad000 0x1000>; - interrupts = <70 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_DSPI3>; - clock-names = "dspi"; - spi-num-chipselects = <2>; - dmas = <&edma1 0 12>, - <&edma1 0 13>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - adc1: adc@400bb000 { - compatible = "fsl,vf610-adc"; - reg = <0x400bb000 0x1000>; - interrupts = <54 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_ADC1>; - clock-names = "adc"; - #io-channel-cells = <1>; - status = "disabled"; - fsl,adck-max-frequency = <30000000>, <40000000>, - <20000000>; - }; - - esdhc0: esdhc@400b1000 { - compatible = "fsl,imx53-esdhc"; - reg = <0x400b1000 0x1000>; - interrupts = <27 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_IPG_BUS>, - <&clks VF610_CLK_PLATFORM_BUS>, - <&clks VF610_CLK_ESDHC0>; - clock-names = "ipg", "ahb", "per"; - status = "disabled"; - }; - - esdhc1: esdhc@400b2000 { - compatible = "fsl,imx53-esdhc"; - reg = <0x400b2000 0x1000>; - interrupts = <28 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_IPG_BUS>, - <&clks VF610_CLK_PLATFORM_BUS>, - <&clks VF610_CLK_ESDHC1>; - clock-names = "ipg", "ahb", "per"; - status = "disabled"; - }; - - usbh1: usb@400b4000 { - compatible = "fsl,vf610-usb", "fsl,imx27-usb"; - reg = <0x400b4000 0x800>; - interrupts = <76 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_USBC1>; - fsl,usbphy = <&usbphy1>; - fsl,usbmisc = <&usbmisc1 0>; - dr_mode = "host"; - status = "disabled"; - }; - - usbmisc1: usb@400b4800 { - #index-cells = <1>; - compatible = "fsl,vf610-usbmisc"; - reg = <0x400b4800 0x200>; - clocks = <&clks VF610_CLK_USBC1>; - status = "disabled"; - }; - - ftm: ftm@400b8000 { - compatible = "fsl,ftm-timer"; - reg = <0x400b8000 0x1000 0x400b9000 0x1000>; - interrupts = <44 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "ftm-evt", "ftm-src", - "ftm-evt-counter-en", "ftm-src-counter-en"; - clocks = <&clks VF610_CLK_FTM2>, - <&clks VF610_CLK_FTM3>, - <&clks VF610_CLK_FTM2_EXT_FIX_EN>, - <&clks VF610_CLK_FTM3_EXT_FIX_EN>; - status = "disabled"; - }; - - qspi1: spi@400c4000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,vf610-qspi"; - reg = <0x400c4000 0x1000>, <0x50000000 0x10000000>; - reg-names = "QuadSPI", "QuadSPI-memory"; - interrupts = <25 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_QSPI1_EN>, - <&clks VF610_CLK_QSPI1>; - clock-names = "qspi_en", "qspi"; - status = "disabled"; - }; - - dac0: dac@400cc000 { - compatible = "fsl,vf610-dac"; - reg = <0x400cc000 1000>; - interrupts = <55 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "dac"; - clocks = <&clks VF610_CLK_DAC0>; - status = "disabled"; - }; - - dac1: dac@400cd000 { - compatible = "fsl,vf610-dac"; - reg = <0x400cd000 1000>; - interrupts = <56 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "dac"; - clocks = <&clks VF610_CLK_DAC1>; - status = "disabled"; - }; - - fec0: ethernet@400d0000 { - compatible = "fsl,mvf600-fec"; - reg = <0x400d0000 0x1000>; - interrupts = <78 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_ENET0>, - <&clks VF610_CLK_ENET0>, - <&clks VF610_CLK_ENET>; - clock-names = "ipg", "ahb", "ptp"; - status = "disabled"; - }; - - fec1: ethernet@400d1000 { - compatible = "fsl,mvf600-fec"; - reg = <0x400d1000 0x1000>; - interrupts = <79 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_ENET1>, - <&clks VF610_CLK_ENET1>, - <&clks VF610_CLK_ENET>; - clock-names = "ipg", "ahb", "ptp"; - status = "disabled"; - }; - - can1: flexcan@400d4000 { - compatible = "fsl,vf610-flexcan"; - reg = <0x400d4000 0x4000>; - interrupts = <59 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_FLEXCAN1>, - <&clks VF610_CLK_FLEXCAN1>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - nfc: nand@400e0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,vf610-nfc"; - reg = <0x400e0000 0x4000>; - interrupts = <83 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_NFC>; - clock-names = "nfc"; - status = "disabled"; - }; - - i2c2: i2c@400e6000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,vf610-i2c"; - reg = <0x400e6000 0x1000>; - interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_I2C2>; - clock-names = "ipg"; - dmas = <&edma0 1 36>, - <&edma0 1 37>; - dma-names = "rx","tx"; - status = "disabled"; - }; - - i2c3: i2c@400e7000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,vf610-i2c"; - reg = <0x400e7000 0x1000>; - interrupts = <74 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_I2C3>; - clock-names = "ipg"; - dmas = <&edma0 1 38>, - <&edma0 1 39>; - dma-names = "rx","tx"; - status = "disabled"; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/vt8500-bv07.dts b/sys/gnu/dts/arm/vt8500-bv07.dts deleted file mode 100644 index e9f55bd30bd..00000000000 --- a/sys/gnu/dts/arm/vt8500-bv07.dts +++ /dev/null @@ -1,35 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * vt8500-bv07.dts - Device tree file for Benign BV07 Netbook - * - * Copyright (C) 2012 Tony Prisk - */ - -/dts-v1/; -/include/ "vt8500.dtsi" - -/ { - model = "Benign BV07 Netbook"; -}; - -&fb { - bits-per-pixel = <16>; - display-timings { - native-mode = <&timing0>; - timing0: 800x480 { - clock-frequency = <0>; /* unused but required */ - hactive = <800>; - vactive = <480>; - hfront-porch = <40>; - hback-porch = <88>; - hsync-len = <0>; - vback-porch = <32>; - vfront-porch = <11>; - vsync-len = <1>; - }; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/vt8500.dtsi b/sys/gnu/dts/arm/vt8500.dtsi deleted file mode 100644 index b7e09eff5bb..00000000000 --- a/sys/gnu/dts/arm/vt8500.dtsi +++ /dev/null @@ -1,179 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * vt8500.dtsi - Device tree file for VIA VT8500 SoC - * - * Copyright (C) 2012 Tony Prisk - */ - -/ { - #address-cells = <1>; - #size-cells = <1>; - compatible = "via,vt8500"; - - cpus { - #address-cells = <0>; - #size-cells = <0>; - - cpu { - device_type = "cpu"; - compatible = "arm,arm926ej-s"; - }; - }; - - memory { - device_type = "memory"; - reg = <0x0 0x0>; - }; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges; - interrupt-parent = <&intc>; - - intc: interrupt-controller@d8140000 { - compatible = "via,vt8500-intc"; - interrupt-controller; - reg = <0xd8140000 0x10000>; - #interrupt-cells = <1>; - }; - - pinctrl: pinctrl@d8110000 { - compatible = "via,vt8500-pinctrl"; - reg = <0xd8110000 0x10000>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - }; - - pmc@d8130000 { - compatible = "via,vt8500-pmc"; - reg = <0xd8130000 0x1000>; - - clocks { - #address-cells = <1>; - #size-cells = <0>; - - ref24: ref24M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - }; - - clkuart0: uart0 { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&ref24>; - enable-reg = <0x250>; - enable-bit = <1>; - }; - - clkuart1: uart1 { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&ref24>; - enable-reg = <0x250>; - enable-bit = <2>; - }; - - clkuart2: uart2 { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&ref24>; - enable-reg = <0x250>; - enable-bit = <3>; - }; - - clkuart3: uart3 { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&ref24>; - enable-reg = <0x250>; - enable-bit = <4>; - }; - }; - }; - - timer@d8130100 { - compatible = "via,vt8500-timer"; - reg = <0xd8130100 0x28>; - interrupts = <36>; - }; - - ehci@d8007900 { - compatible = "via,vt8500-ehci"; - reg = <0xd8007900 0x200>; - interrupts = <43>; - }; - - uhci@d8007b00 { - compatible = "platform-uhci"; - reg = <0xd8007b00 0x200>; - interrupts = <43>; - }; - - fb: fb@d8050800 { - compatible = "via,vt8500-fb"; - reg = <0xd800e400 0x400>; - interrupts = <12>; - }; - - ge_rops@d8050400 { - compatible = "wm,prizm-ge-rops"; - reg = <0xd8050400 0x100>; - }; - - uart0: serial@d8200000 { - compatible = "via,vt8500-uart"; - reg = <0xd8200000 0x1040>; - interrupts = <32>; - clocks = <&clkuart0>; - status = "disabled"; - }; - - uart1: serial@d82b0000 { - compatible = "via,vt8500-uart"; - reg = <0xd82b0000 0x1040>; - interrupts = <33>; - clocks = <&clkuart1>; - status = "disabled"; - }; - - uart2: serial@d8210000 { - compatible = "via,vt8500-uart"; - reg = <0xd8210000 0x1040>; - interrupts = <47>; - clocks = <&clkuart2>; - status = "disabled"; - }; - - uart3: serial@d82c0000 { - compatible = "via,vt8500-uart"; - reg = <0xd82c0000 0x1040>; - interrupts = <50>; - clocks = <&clkuart3>; - status = "disabled"; - }; - - rtc@d8100000 { - compatible = "via,vt8500-rtc"; - reg = <0xd8100000 0x10000>; - interrupts = <48>; - }; - - ethernet@d8004000 { - compatible = "via,vt8500-rhine"; - reg = <0xd8004000 0x100>; - interrupts = <10>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/wm8505-ref.dts b/sys/gnu/dts/arm/wm8505-ref.dts deleted file mode 100644 index 2d77c087676..00000000000 --- a/sys/gnu/dts/arm/wm8505-ref.dts +++ /dev/null @@ -1,35 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * wm8505-ref.dts - Device tree file for Wondermedia WM8505 reference netbook - * - * Copyright (C) 2012 Tony Prisk - */ - -/dts-v1/; -/include/ "wm8505.dtsi" - -/ { - model = "Wondermedia WM8505 Netbook"; -}; - -&fb { - bits-per-pixel = <32>; - display-timings { - native-mode = <&timing0>; - timing0: 800x480 { - clock-frequency = <0>; /* unused but required */ - hactive = <800>; - vactive = <480>; - hfront-porch = <40>; - hback-porch = <88>; - hsync-len = <0>; - vback-porch = <32>; - vfront-porch = <11>; - vsync-len = <1>; - }; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/wm8505.dtsi b/sys/gnu/dts/arm/wm8505.dtsi deleted file mode 100644 index 168cd12b07b..00000000000 --- a/sys/gnu/dts/arm/wm8505.dtsi +++ /dev/null @@ -1,294 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * wm8505.dtsi - Device tree file for Wondermedia WM8505 SoC - * - * Copyright (C) 2012 Tony Prisk - */ - -/ { - #address-cells = <1>; - #size-cells = <1>; - compatible = "wm,wm8505"; - - cpus { - #address-cells = <0>; - #size-cells = <0>; - - cpu { - device_type = "cpu"; - compatible = "arm,arm926ej-s"; - }; - }; - - memory { - device_type = "memory"; - reg = <0x0 0x0>; - }; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - serial4 = &uart4; - serial5 = &uart5; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges; - interrupt-parent = <&intc0>; - - intc0: interrupt-controller@d8140000 { - compatible = "via,vt8500-intc"; - interrupt-controller; - reg = <0xd8140000 0x10000>; - #interrupt-cells = <1>; - }; - - /* Secondary IC cascaded to intc0 */ - intc1: interrupt-controller@d8150000 { - compatible = "via,vt8500-intc"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0xD8150000 0x10000>; - interrupts = <56 57 58 59 60 61 62 63>; - }; - - pinctrl: pinctrl@d8110000 { - compatible = "wm,wm8505-pinctrl"; - reg = <0xd8110000 0x10000>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - }; - - pmc@d8130000 { - compatible = "via,vt8500-pmc"; - reg = <0xd8130000 0x1000>; - clocks { - #address-cells = <1>; - #size-cells = <0>; - - ref24: ref24M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - }; - - ref25: ref25M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <25000000>; - }; - - plla: plla { - #clock-cells = <0>; - compatible = "via,vt8500-pll-clock"; - clocks = <&ref25>; - reg = <0x200>; - }; - - pllb: pllb { - #clock-cells = <0>; - compatible = "via,vt8500-pll-clock"; - clocks = <&ref25>; - reg = <0x204>; - }; - - pllc: pllc { - #clock-cells = <0>; - compatible = "via,vt8500-pll-clock"; - clocks = <&ref25>; - reg = <0x208>; - }; - - plld: plld { - #clock-cells = <0>; - compatible = "via,vt8500-pll-clock"; - clocks = <&ref25>; - reg = <0x20c>; - }; - - clkarm: arm { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&plla>; - divisor-reg = <0x300>; - }; - - clkahb: ahb { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&pllb>; - divisor-reg = <0x304>; - }; - - clkapb: apb { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&pllb>; - divisor-reg = <0x350>; - }; - - clkddr: ddr { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&plld>; - divisor-reg = <0x310>; - }; - - clkuart0: uart0 { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&ref24>; - enable-reg = <0x250>; - enable-bit = <1>; - }; - - clkuart1: uart1 { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&ref24>; - enable-reg = <0x250>; - enable-bit = <2>; - }; - - clkuart2: uart2 { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&ref24>; - enable-reg = <0x250>; - enable-bit = <3>; - }; - - clkuart3: uart3 { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&ref24>; - enable-reg = <0x250>; - enable-bit = <4>; - }; - - clkuart4: uart4 { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&ref24>; - enable-reg = <0x250>; - enable-bit = <22>; - }; - - clkuart5: uart5 { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&ref24>; - enable-reg = <0x250>; - enable-bit = <23>; - }; - - clksdhc: sdhc { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&pllb>; - divisor-reg = <0x328>; - divisor-mask = <0x3f>; - enable-reg = <0x254>; - enable-bit = <18>; - }; - }; - }; - - timer@d8130100 { - compatible = "via,vt8500-timer"; - reg = <0xd8130100 0x28>; - interrupts = <36>; - }; - - ehci@d8007100 { - compatible = "via,vt8500-ehci"; - reg = <0xd8007100 0x200>; - interrupts = <1>; - }; - - uhci@d8007300 { - compatible = "platform-uhci"; - reg = <0xd8007300 0x200>; - interrupts = <0>; - }; - - fb: fb@d8050800 { - compatible = "wm,wm8505-fb"; - reg = <0xd8050800 0x200>; - }; - - ge_rops@d8050400 { - compatible = "wm,prizm-ge-rops"; - reg = <0xd8050400 0x100>; - }; - - uart0: serial@d8200000 { - compatible = "via,vt8500-uart"; - reg = <0xd8200000 0x1040>; - interrupts = <32>; - clocks = <&clkuart0>; - status = "disabled"; - }; - - uart1: serial@d82b0000 { - compatible = "via,vt8500-uart"; - reg = <0xd82b0000 0x1040>; - interrupts = <33>; - clocks = <&clkuart1>; - status = "disabled"; - }; - - uart2: serial@d8210000 { - compatible = "via,vt8500-uart"; - reg = <0xd8210000 0x1040>; - interrupts = <47>; - clocks = <&clkuart2>; - status = "disabled"; - }; - - uart3: serial@d82c0000 { - compatible = "via,vt8500-uart"; - reg = <0xd82c0000 0x1040>; - interrupts = <50>; - clocks = <&clkuart3>; - status = "disabled"; - }; - - uart4: serial@d8370000 { - compatible = "via,vt8500-uart"; - reg = <0xd8370000 0x1040>; - interrupts = <31>; - clocks = <&clkuart4>; - status = "disabled"; - }; - - uart5: serial@d8380000 { - compatible = "via,vt8500-uart"; - reg = <0xd8380000 0x1040>; - interrupts = <30>; - clocks = <&clkuart5>; - status = "disabled"; - }; - - rtc@d8100000 { - compatible = "via,vt8500-rtc"; - reg = <0xd8100000 0x10000>; - interrupts = <48>; - }; - - sdhc@d800a000 { - compatible = "wm,wm8505-sdhc"; - reg = <0xd800a000 0x400>; - interrupts = <20>, <21>; - clocks = <&clksdhc>; - bus-width = <4>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/wm8650-mid.dts b/sys/gnu/dts/arm/wm8650-mid.dts deleted file mode 100644 index f6a42149a0a..00000000000 --- a/sys/gnu/dts/arm/wm8650-mid.dts +++ /dev/null @@ -1,36 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * wm8650-mid.dts - Device tree file for Wondermedia WM8650-MID Tablet - * - * Copyright (C) 2012 Tony Prisk - */ - -/dts-v1/; -/include/ "wm8650.dtsi" - -/ { - model = "Wondermedia WM8650-MID Tablet"; -}; - -&fb { - bits-per-pixel = <16>; - - display-timings { - native-mode = <&timing0>; - timing0: 800x480 { - clock-frequency = <0>; /* unused but required */ - hactive = <800>; - vactive = <480>; - hfront-porch = <40>; - hback-porch = <88>; - hsync-len = <0>; - vback-porch = <32>; - vfront-porch = <11>; - vsync-len = <1>; - }; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/wm8650.dtsi b/sys/gnu/dts/arm/wm8650.dtsi deleted file mode 100644 index bc057b6f7d1..00000000000 --- a/sys/gnu/dts/arm/wm8650.dtsi +++ /dev/null @@ -1,241 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * wm8650.dtsi - Device tree file for Wondermedia WM8650 SoC - * - * Copyright (C) 2012 Tony Prisk - */ - -/ { - #address-cells = <1>; - #size-cells = <1>; - compatible = "wm,wm8650"; - - cpus { - #address-cells = <0>; - #size-cells = <0>; - - cpu { - device_type = "cpu"; - compatible = "arm,arm926ej-s"; - }; - }; - - memory { - device_type = "memory"; - reg = <0x0 0x0>; - }; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges; - interrupt-parent = <&intc0>; - - intc0: interrupt-controller@d8140000 { - compatible = "via,vt8500-intc"; - interrupt-controller; - reg = <0xd8140000 0x10000>; - #interrupt-cells = <1>; - }; - - /* Secondary IC cascaded to intc0 */ - intc1: interrupt-controller@d8150000 { - compatible = "via,vt8500-intc"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0xD8150000 0x10000>; - interrupts = <56 57 58 59 60 61 62 63>; - }; - - pinctrl: pinctrl@d8110000 { - compatible = "wm,wm8650-pinctrl"; - reg = <0xd8110000 0x10000>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - }; - - pmc@d8130000 { - compatible = "via,vt8500-pmc"; - reg = <0xd8130000 0x1000>; - - clocks { - #address-cells = <1>; - #size-cells = <0>; - - ref25: ref25M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <25000000>; - }; - - ref24: ref24M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - }; - - plla: plla { - #clock-cells = <0>; - compatible = "wm,wm8650-pll-clock"; - clocks = <&ref25>; - reg = <0x200>; - }; - - pllb: pllb { - #clock-cells = <0>; - compatible = "wm,wm8650-pll-clock"; - clocks = <&ref25>; - reg = <0x204>; - }; - - pllc: pllc { - #clock-cells = <0>; - compatible = "wm,wm8650-pll-clock"; - clocks = <&ref25>; - reg = <0x208>; - }; - - plld: plld { - #clock-cells = <0>; - compatible = "wm,wm8650-pll-clock"; - clocks = <&ref25>; - reg = <0x20c>; - }; - - plle: plle { - #clock-cells = <0>; - compatible = "wm,wm8650-pll-clock"; - clocks = <&ref25>; - reg = <0x210>; - }; - - clkarm: arm { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&plla>; - divisor-reg = <0x300>; - }; - - clkahb: ahb { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&pllb>; - divisor-reg = <0x304>; - }; - - clkapb: apb { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&pllb>; - divisor-reg = <0x320>; - }; - - clkddr: ddr { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&plld>; - divisor-reg = <0x310>; - }; - - clkuart0: uart0 { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&ref24>; - enable-reg = <0x250>; - enable-bit = <1>; - }; - - clkuart1: uart1 { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&ref24>; - enable-reg = <0x250>; - enable-bit = <2>; - }; - - clksdhc: sdhc { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&pllb>; - divisor-reg = <0x328>; - divisor-mask = <0x3f>; - enable-reg = <0x254>; - enable-bit = <18>; - }; - }; - }; - - timer@d8130100 { - compatible = "via,vt8500-timer"; - reg = <0xd8130100 0x28>; - interrupts = <36>; - }; - - ehci@d8007900 { - compatible = "via,vt8500-ehci"; - reg = <0xd8007900 0x200>; - interrupts = <43>; - }; - - uhci@d8007b00 { - compatible = "platform-uhci"; - reg = <0xd8007b00 0x200>; - interrupts = <43>; - }; - - sdhc@d800a000 { - compatible = "wm,wm8505-sdhc"; - reg = <0xd800a000 0x400>; - interrupts = <20>, <21>; - clocks = <&clksdhc>; - bus-width = <4>; - sdon-inverted; - }; - - fb: fb@d8050800 { - compatible = "wm,wm8505-fb"; - reg = <0xd8050800 0x200>; - }; - - ge_rops@d8050400 { - compatible = "wm,prizm-ge-rops"; - reg = <0xd8050400 0x100>; - }; - - uart0: serial@d8200000 { - compatible = "via,vt8500-uart"; - reg = <0xd8200000 0x1040>; - interrupts = <32>; - clocks = <&clkuart0>; - status = "disabled"; - }; - - uart1: serial@d82b0000 { - compatible = "via,vt8500-uart"; - reg = <0xd82b0000 0x1040>; - interrupts = <33>; - clocks = <&clkuart1>; - status = "disabled"; - }; - - rtc@d8100000 { - compatible = "via,vt8500-rtc"; - reg = <0xd8100000 0x10000>; - interrupts = <48>; - }; - - ethernet@d8004000 { - compatible = "via,vt8500-rhine"; - reg = <0xd8004000 0x100>; - interrupts = <10>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/wm8750-apc8750.dts b/sys/gnu/dts/arm/wm8750-apc8750.dts deleted file mode 100644 index 136e812bc1e..00000000000 --- a/sys/gnu/dts/arm/wm8750-apc8750.dts +++ /dev/null @@ -1,29 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * wm8750-apc8750.dts - * - Device tree file for VIA APC8750 - * - * Copyright (C) 2012 Tony Prisk - */ - -/dts-v1/; -/include/ "wm8750.dtsi" - -/ { - model = "VIA APC8750"; -}; - -&pinctrl { - pinctrl-names = "default"; - pinctrl-0 = <&i2c>; - - i2c: i2c { - wm,pins = <168 169 170 171>; - wm,function = <2>; /* alt */ - wm,pull = <2>; /* pull-up */ - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/wm8750.dtsi b/sys/gnu/dts/arm/wm8750.dtsi deleted file mode 100644 index 33aeb37491f..00000000000 --- a/sys/gnu/dts/arm/wm8750.dtsi +++ /dev/null @@ -1,351 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * wm8750.dtsi - Device tree file for Wondermedia WM8750 SoC - * - * Copyright (C) 2012 Tony Prisk - */ - -/ { - #address-cells = <1>; - #size-cells = <1>; - compatible = "wm,wm8750"; - - cpus { - #address-cells = <0>; - #size-cells = <0>; - - cpu { - device_type = "cpu"; - compatible = "arm,arm1176jzf"; - }; - }; - - memory { - device_type = "memory"; - reg = <0x0 0x0>; - }; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - serial4 = &uart4; - serial5 = &uart5; - i2c0 = &i2c_0; - i2c1 = &i2c_1; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges; - interrupt-parent = <&intc0>; - - intc0: interrupt-controller@d8140000 { - compatible = "via,vt8500-intc"; - interrupt-controller; - reg = <0xd8140000 0x10000>; - #interrupt-cells = <1>; - }; - - /* Secondary IC cascaded to intc0 */ - intc1: interrupt-controller@d8150000 { - compatible = "via,vt8500-intc"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0xD8150000 0x10000>; - interrupts = <56 57 58 59 60 61 62 63>; - }; - - pinctrl: pinctrl@d8110000 { - compatible = "wm,wm8750-pinctrl"; - reg = <0xd8110000 0x10000>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - }; - - pmc@d8130000 { - compatible = "via,vt8500-pmc"; - reg = <0xd8130000 0x1000>; - - clocks { - #address-cells = <1>; - #size-cells = <0>; - - ref24: ref24M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - }; - - ref25: ref25M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <25000000>; - }; - - plla: plla { - #clock-cells = <0>; - compatible = "wm,wm8750-pll-clock"; - clocks = <&ref25>; - reg = <0x200>; - }; - - pllb: pllb { - #clock-cells = <0>; - compatible = "wm,wm8750-pll-clock"; - clocks = <&ref25>; - reg = <0x204>; - }; - - pllc: pllc { - #clock-cells = <0>; - compatible = "wm,wm8750-pll-clock"; - clocks = <&ref25>; - reg = <0x208>; - }; - - plld: plld { - #clock-cells = <0>; - compatible = "wm,wm8750-pll-clock"; - clocks = <&ref25>; - reg = <0x20C>; - }; - - plle: plle { - #clock-cells = <0>; - compatible = "wm,wm8750-pll-clock"; - clocks = <&ref25>; - reg = <0x210>; - }; - - clkarm: arm { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&plla>; - divisor-reg = <0x300>; - }; - - clkahb: ahb { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&pllb>; - divisor-reg = <0x304>; - }; - - clkapb: apb { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&pllb>; - divisor-reg = <0x320>; - }; - - clkddr: ddr { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&plld>; - divisor-reg = <0x310>; - }; - - clkuart0: uart0 { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&ref24>; - enable-reg = <0x254>; - enable-bit = <24>; - }; - - clkuart1: uart1 { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&ref24>; - enable-reg = <0x254>; - enable-bit = <25>; - }; - - clkuart2: uart2 { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&ref24>; - enable-reg = <0x254>; - enable-bit = <26>; - }; - - clkuart3: uart3 { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&ref24>; - enable-reg = <0x254>; - enable-bit = <27>; - }; - - clkuart4: uart4 { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&ref24>; - enable-reg = <0x254>; - enable-bit = <28>; - }; - - clkuart5: uart5 { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&ref24>; - enable-reg = <0x254>; - enable-bit = <29>; - }; - - clkpwm: pwm { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&pllb>; - divisor-reg = <0x350>; - enable-reg = <0x250>; - enable-bit = <17>; - }; - - clksdhc: sdhc { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&pllb>; - divisor-reg = <0x330>; - divisor-mask = <0x3f>; - enable-reg = <0x250>; - enable-bit = <0>; - }; - - clki2c0: i2c0clk { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&pllb>; - divisor-reg = <0x3A0>; - enable-reg = <0x250>; - enable-bit = <8>; - }; - - clki2c1: i2c1clk { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&pllb>; - divisor-reg = <0x3A4>; - enable-reg = <0x250>; - enable-bit = <9>; - }; - }; - }; - - pwm: pwm@d8220000 { - #pwm-cells = <3>; - compatible = "via,vt8500-pwm"; - reg = <0xd8220000 0x100>; - clocks = <&clkpwm>; - }; - - timer@d8130100 { - compatible = "via,vt8500-timer"; - reg = <0xd8130100 0x28>; - interrupts = <36>; - }; - - ehci@d8007900 { - compatible = "via,vt8500-ehci"; - reg = <0xd8007900 0x200>; - interrupts = <26>; - }; - - uhci@d8007b00 { - compatible = "platform-uhci"; - reg = <0xd8007b00 0x200>; - interrupts = <26>; - }; - - uhci@d8008d00 { - compatible = "platform-uhci"; - reg = <0xd8008d00 0x200>; - interrupts = <26>; - }; - - uart0: serial@d8200000 { - compatible = "via,vt8500-uart"; - reg = <0xd8200000 0x1040>; - interrupts = <32>; - clocks = <&clkuart0>; - status = "disabled"; - }; - - uart1: serial@d82b0000 { - compatible = "via,vt8500-uart"; - reg = <0xd82b0000 0x1040>; - interrupts = <33>; - clocks = <&clkuart1>; - status = "disabled"; - }; - - uart2: serial@d8210000 { - compatible = "via,vt8500-uart"; - reg = <0xd8210000 0x1040>; - interrupts = <47>; - clocks = <&clkuart2>; - status = "disabled"; - }; - - uart3: serial@d82c0000 { - compatible = "via,vt8500-uart"; - reg = <0xd82c0000 0x1040>; - interrupts = <50>; - clocks = <&clkuart3>; - status = "disabled"; - }; - - uart4: serial@d8370000 { - compatible = "via,vt8500-uart"; - reg = <0xd8370000 0x1040>; - interrupts = <30>; - clocks = <&clkuart4>; - status = "disabled"; - }; - - uart5: serial@d8380000 { - compatible = "via,vt8500-uart"; - reg = <0xd8380000 0x1040>; - interrupts = <43>; - clocks = <&clkuart5>; - status = "disabled"; - }; - - rtc@d8100000 { - compatible = "via,vt8500-rtc"; - reg = <0xd8100000 0x10000>; - interrupts = <48>; - }; - - sdhc@d800a000 { - compatible = "wm,wm8505-sdhc"; - reg = <0xd800a000 0x1000>; - interrupts = <20 21>; - clocks = <&clksdhc>; - bus-width = <4>; - sdon-inverted; - }; - - i2c_0: i2c@d8280000 { - compatible = "wm,wm8505-i2c"; - reg = <0xd8280000 0x1000>; - interrupts = <19>; - clocks = <&clki2c0>; - clock-frequency = <400000>; - }; - - i2c_1: i2c@d8320000 { - compatible = "wm,wm8505-i2c"; - reg = <0xd8320000 0x1000>; - interrupts = <18>; - clocks = <&clki2c1>; - clock-frequency = <400000>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/wm8850-w70v2.dts b/sys/gnu/dts/arm/wm8850-w70v2.dts deleted file mode 100644 index c7a6fe0ce48..00000000000 --- a/sys/gnu/dts/arm/wm8850-w70v2.dts +++ /dev/null @@ -1,47 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * wm8850-w70v2.dts - * - Device tree file for Wondermedia WM8850 Tablet - * - 'W70-V2' mainboard - * - HongLianYing 'HLY070ML268-21A' 7" LCD panel - * - * Copyright (C) 2012 Tony Prisk - */ - -/dts-v1/; -/include/ "wm8850.dtsi" -#include - -/ { - model = "Wondermedia WM8850-W70v2 Tablet"; - - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; - - brightness-levels = <0 40 60 80 100 130 190 255>; - default-brightness-level = <5>; - }; -}; - -&fb { - bits-per-pixel = <16>; - display-timings { - native-mode = <&timing0>; - timing0: 800x480 { - clock-frequency = <0>; /* unused but required */ - hactive = <800>; - vactive = <480>; - hfront-porch = <40>; - hback-porch = <88>; - hsync-len = <0>; - vback-porch = <32>; - vfront-porch = <11>; - vsync-len = <1>; - }; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/wm8850.dtsi b/sys/gnu/dts/arm/wm8850.dtsi deleted file mode 100644 index 65c9271050e..00000000000 --- a/sys/gnu/dts/arm/wm8850.dtsi +++ /dev/null @@ -1,312 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * wm8850.dtsi - Device tree file for Wondermedia WM8850 SoC - * - * Copyright (C) 2012 Tony Prisk - */ - -/ { - #address-cells = <1>; - #size-cells = <1>; - compatible = "wm,wm8850"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0x0>; - }; - }; - - memory { - device_type = "memory"; - reg = <0x0 0x0>; - }; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges; - interrupt-parent = <&intc0>; - - intc0: interrupt-controller@d8140000 { - compatible = "via,vt8500-intc"; - interrupt-controller; - reg = <0xd8140000 0x10000>; - #interrupt-cells = <1>; - }; - - /* Secondary IC cascaded to intc0 */ - intc1: interrupt-controller@d8150000 { - compatible = "via,vt8500-intc"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0xD8150000 0x10000>; - interrupts = <56 57 58 59 60 61 62 63>; - }; - - pinctrl: pinctrl@d8110000 { - compatible = "wm,wm8850-pinctrl"; - reg = <0xd8110000 0x10000>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - }; - - pmc@d8130000 { - compatible = "via,vt8500-pmc"; - reg = <0xd8130000 0x1000>; - - clocks { - #address-cells = <1>; - #size-cells = <0>; - - ref25: ref25M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <25000000>; - }; - - ref24: ref24M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - }; - - plla: plla { - #clock-cells = <0>; - compatible = "wm,wm8850-pll-clock"; - clocks = <&ref24>; - reg = <0x200>; - }; - - pllb: pllb { - #clock-cells = <0>; - compatible = "wm,wm8850-pll-clock"; - clocks = <&ref24>; - reg = <0x204>; - }; - - pllc: pllc { - #clock-cells = <0>; - compatible = "wm,wm8850-pll-clock"; - clocks = <&ref24>; - reg = <0x208>; - }; - - plld: plld { - #clock-cells = <0>; - compatible = "wm,wm8850-pll-clock"; - clocks = <&ref24>; - reg = <0x20c>; - }; - - plle: plle { - #clock-cells = <0>; - compatible = "wm,wm8850-pll-clock"; - clocks = <&ref24>; - reg = <0x210>; - }; - - pllf: pllf { - #clock-cells = <0>; - compatible = "wm,wm8850-pll-clock"; - clocks = <&ref24>; - reg = <0x214>; - }; - - pllg: pllg { - #clock-cells = <0>; - compatible = "wm,wm8850-pll-clock"; - clocks = <&ref24>; - reg = <0x218>; - }; - - clkarm: arm { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&plla>; - divisor-reg = <0x300>; - }; - - clkahb: ahb { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&pllb>; - divisor-reg = <0x304>; - }; - - clkapb: apb { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&pllb>; - divisor-reg = <0x320>; - }; - - clkddr: ddr { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&plld>; - divisor-reg = <0x310>; - }; - - clkuart0: uart0 { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&ref24>; - enable-reg = <0x254>; - enable-bit = <24>; - }; - - clkuart1: uart1 { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&ref24>; - enable-reg = <0x254>; - enable-bit = <25>; - }; - - clkuart2: uart2 { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&ref24>; - enable-reg = <0x254>; - enable-bit = <26>; - }; - - clkuart3: uart3 { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&ref24>; - enable-reg = <0x254>; - enable-bit = <27>; - }; - - clkpwm: pwm { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&pllb>; - divisor-reg = <0x350>; - enable-reg = <0x250>; - enable-bit = <17>; - }; - - clksdhc: sdhc { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&pllb>; - divisor-reg = <0x330>; - divisor-mask = <0x3f>; - enable-reg = <0x250>; - enable-bit = <0>; - }; - }; - }; - - fb: fb@d8051700 { - compatible = "wm,wm8505-fb"; - reg = <0xd8051700 0x200>; - }; - - ge_rops@d8050400 { - compatible = "wm,prizm-ge-rops"; - reg = <0xd8050400 0x100>; - }; - - pwm: pwm@d8220000 { - #pwm-cells = <3>; - compatible = "via,vt8500-pwm"; - reg = <0xd8220000 0x100>; - clocks = <&clkpwm>; - }; - - timer@d8130100 { - compatible = "via,vt8500-timer"; - reg = <0xd8130100 0x28>; - interrupts = <36>; - }; - - ehci@d8007900 { - compatible = "via,vt8500-ehci"; - reg = <0xd8007900 0x200>; - interrupts = <26>; - }; - - uhci@d8007b00 { - compatible = "platform-uhci"; - reg = <0xd8007b00 0x200>; - interrupts = <26>; - }; - - uhci@d8008d00 { - compatible = "platform-uhci"; - reg = <0xd8008d00 0x200>; - interrupts = <26>; - }; - - uart0: serial@d8200000 { - compatible = "via,vt8500-uart"; - reg = <0xd8200000 0x1040>; - interrupts = <32>; - clocks = <&clkuart0>; - status = "disabled"; - }; - - uart1: serial@d82b0000 { - compatible = "via,vt8500-uart"; - reg = <0xd82b0000 0x1040>; - interrupts = <33>; - clocks = <&clkuart1>; - status = "disabled"; - }; - - uart2: serial@d8210000 { - compatible = "via,vt8500-uart"; - reg = <0xd8210000 0x1040>; - interrupts = <47>; - clocks = <&clkuart2>; - status = "disabled"; - }; - - uart3: serial@d82c0000 { - compatible = "via,vt8500-uart"; - reg = <0xd82c0000 0x1040>; - interrupts = <50>; - clocks = <&clkuart3>; - status = "disabled"; - }; - - rtc@d8100000 { - compatible = "via,vt8500-rtc"; - reg = <0xd8100000 0x10000>; - interrupts = <48>; - }; - - sdhc@d800a000 { - compatible = "wm,wm8505-sdhc"; - reg = <0xd800a000 0x1000>; - interrupts = <20 21>; - clocks = <&clksdhc>; - bus-width = <4>; - sdon-inverted; - }; - - ethernet@d8004000 { - compatible = "via,vt8500-rhine"; - reg = <0xd8004000 0x100>; - interrupts = <10>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/xenvm-4.2.dts b/sys/gnu/dts/arm/xenvm-4.2.dts deleted file mode 100644 index 384cd92f1f8..00000000000 --- a/sys/gnu/dts/arm/xenvm-4.2.dts +++ /dev/null @@ -1,82 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Xen Virtual Machine for unprivileged guests - * - * Based on ARM Ltd. Versatile Express CoreTile Express (single CPU) - * Cortex-A15 MPCore (V2P-CA15) - * - */ - -/dts-v1/; - -/ { - model = "XENVM-4.2"; - compatible = "xen,xenvm-4.2", "xen,xenvm"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - chosen { - /* this field is going to be adjusted by the hypervisor */ - bootargs = "console=hvc0 root=/dev/xvda"; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <1>; - }; - }; - - psci { - compatible = "arm,psci"; - method = "hvc"; - cpu_off = <1>; - cpu_on = <2>; - }; - - memory@80000000 { - device_type = "memory"; - /* this field is going to be adjusted by the hypervisor */ - reg = <0 0x80000000 0 0x08000000>; - }; - - gic: interrupt-controller@2c001000 { - compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0 0x2c001000 0 0x1000>, - <0 0x2c002000 0 0x100>; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = <1 13 0xf08>, - <1 14 0xf08>, - <1 11 0xf08>, - <1 10 0xf08>; - }; - - hypervisor { - compatible = "xen,xen-4.2", "xen,xen"; - /* this field is going to be adjusted by the hypervisor */ - reg = <0 0xb0000000 0 0x20000>; - /* this field is going to be adjusted by the hypervisor */ - interrupts = <1 15 0xf08>; - }; - - motherboard { - arm,v2m-memory-map = "rs1"; - }; -}; diff --git a/sys/gnu/dts/arm/zx296702-ad1.dts b/sys/gnu/dts/arm/zx296702-ad1.dts deleted file mode 100644 index bd940084002..00000000000 --- a/sys/gnu/dts/arm/zx296702-ad1.dts +++ /dev/null @@ -1,48 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -/dts-v1/; - -#include "zx296702.dtsi" - -/ { - model = "ZTE ZX296702 AD1 Board"; - compatible = "zte,zx296702-ad1", "zte,zx296702"; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - }; - - memory { - device_type = "memory"; - reg = <0x50000000 0x20000000>; - }; -}; - -&mmc0 { - supports-highspeed; - non-removable; - disable-wp; - status = "okay"; - - slot@0 { - reg = <0>; - bus-width = <4>; - }; -}; - -&mmc1 { - supports-highspeed; - non-removable; - disable-wp; - status = "okay"; - - slot@0 { - reg = <0>; - bus-width = <8>; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/zx296702.dtsi b/sys/gnu/dts/arm/zx296702.dtsi deleted file mode 100644 index afd98de029b..00000000000 --- a/sys/gnu/dts/arm/zx296702.dtsi +++ /dev/null @@ -1,142 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "zte,zx296702-smp"; - - cpu@0 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - next-level-cache = <&l2cc>; - reg = <0>; - }; - - cpu@1 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - next-level-cache = <&l2cc>; - reg = <1>; - }; - }; - - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&intc>; - ranges; - - matrix: bus-matrix@400000 { - compatible = "zte,zx-bus-matrix"; - reg = <0x00400000 0x1000>; - }; - - intc: interrupt-controller@801000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <1>; - #size-cells = <1>; - interrupt-controller; - reg = <0x00801000 0x1000>, - <0x00800100 0x100>; - }; - - global_timer: timer@8000200 { - compatible = "arm,cortex-a9-global-timer"; - reg = <0x00800200 0x20>; - interrupts = ; - interrupt-parent = <&intc>; - clocks = <&topclk ZX296702_A9_PERIPHCLK>; - }; - - l2cc: l2-cache-controller@c00000 { - compatible = "arm,pl310-cache"; - reg = <0x00c00000 0x1000>; - cache-unified; - cache-level = <2>; - arm,data-latency = <1 1 1>; - arm,tag-latency = <1 1 1>; - arm,double-linefill = <1>; - arm,double-linefill-incr = <0>; - }; - - pcu: pcu@a0008000 { - compatible = "zte,zx296702-pcu"; - reg = <0xa0008000 0x1000>; - }; - - topclk: topclk@9800000 { - compatible = "zte,zx296702-topcrm-clk"; - reg = <0x09800000 0x1000>; - #clock-cells = <1>; - }; - - lsp1clk: lsp1clk@9400000 { - compatible = "zte,zx296702-lsp1crpm-clk"; - reg = <0x09400000 0x1000>; - #clock-cells = <1>; - }; - - lsp0clk: lsp0clk@b000000 { - compatible = "zte,zx296702-lsp0crpm-clk"; - reg = <0x0b000000 0x1000>; - #clock-cells = <1>; - }; - - uart0: serial@9405000 { - compatible = "zte,zx296702-uart"; - reg = <0x09405000 0x1000>; - interrupts = ; - clocks = <&lsp1clk ZX296702_UART0_WCLK>; - status = "disabled"; - }; - - uart1: serial@9406000 { - compatible = "zte,zx296702-uart"; - reg = <0x09406000 0x1000>; - interrupts = ; - clocks = <&lsp1clk ZX296702_UART1_WCLK>; - status = "disabled"; - }; - - mmc0: mmc@9408000 { - compatible = "snps,dw-mshc"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x09408000 0x1000>; - interrupts = ; - fifo-depth = <32>; - clocks = <&lsp1clk ZX296702_SDMMC0_PCLK>, - <&lsp1clk ZX296702_SDMMC0_WCLK>; - clock-names = "biu", "ciu"; - status = "disabled"; - }; - - mmc1: mmc@b003000 { - compatible = "snps,dw-mshc"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0b003000 0x1000>; - interrupts = ; - fifo-depth = <32>; - clocks = <&lsp0clk ZX296702_SDMMC1_PCLK>, - <&lsp0clk ZX296702_SDMMC1_WCLK>; - clock-names = "biu", "ciu"; - status = "disabled"; - }; - - sysctrl: sysctrl@a0007000 { - compatible = "zte,sysctrl", "syscon"; - reg = <0xa0007000 0x1000>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/zynq-7000.dtsi b/sys/gnu/dts/arm/zynq-7000.dtsi deleted file mode 100644 index db3899b0799..00000000000 --- a/sys/gnu/dts/arm/zynq-7000.dtsi +++ /dev/null @@ -1,504 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2011 - 2014 Xilinx - */ - -/ { - #address-cells = <1>; - #size-cells = <1>; - compatible = "xlnx,zynq-7000"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - reg = <0>; - clocks = <&clkc 3>; - clock-latency = <1000>; - cpu0-supply = <®ulator_vccpint>; - operating-points = < - /* kHz uV */ - 666667 1000000 - 333334 1000000 - >; - }; - - cpu1: cpu@1 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - reg = <1>; - clocks = <&clkc 3>; - }; - }; - - fpga_full: fpga-full { - compatible = "fpga-region"; - fpga-mgr = <&devcfg>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - }; - - pmu@f8891000 { - compatible = "arm,cortex-a9-pmu"; - interrupts = <0 5 4>, <0 6 4>; - interrupt-parent = <&intc>; - reg = <0xf8891000 0x1000>, - <0xf8893000 0x1000>; - }; - - regulator_vccpint: fixedregulator { - compatible = "regulator-fixed"; - regulator-name = "VCCPINT"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-boot-on; - regulator-always-on; - }; - - replicator { - compatible = "arm,coresight-static-replicator"; - clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; - clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; - - out-ports { - #address-cells = <1>; - #size-cells = <0>; - - /* replicator output ports */ - port@0 { - reg = <0>; - replicator_out_port0: endpoint { - remote-endpoint = <&tpiu_in_port>; - }; - }; - port@1 { - reg = <1>; - replicator_out_port1: endpoint { - remote-endpoint = <&etb_in_port>; - }; - }; - }; - in-ports { - /* replicator input port */ - port { - replicator_in_port0: endpoint { - remote-endpoint = <&funnel_out_port>; - }; - }; - }; - }; - - amba: amba { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&intc>; - ranges; - - adc: adc@f8007100 { - compatible = "xlnx,zynq-xadc-1.00.a"; - reg = <0xf8007100 0x20>; - interrupts = <0 7 4>; - interrupt-parent = <&intc>; - clocks = <&clkc 12>; - }; - - can0: can@e0008000 { - compatible = "xlnx,zynq-can-1.0"; - status = "disabled"; - clocks = <&clkc 19>, <&clkc 36>; - clock-names = "can_clk", "pclk"; - reg = <0xe0008000 0x1000>; - interrupts = <0 28 4>; - interrupt-parent = <&intc>; - tx-fifo-depth = <0x40>; - rx-fifo-depth = <0x40>; - }; - - can1: can@e0009000 { - compatible = "xlnx,zynq-can-1.0"; - status = "disabled"; - clocks = <&clkc 20>, <&clkc 37>; - clock-names = "can_clk", "pclk"; - reg = <0xe0009000 0x1000>; - interrupts = <0 51 4>; - interrupt-parent = <&intc>; - tx-fifo-depth = <0x40>; - rx-fifo-depth = <0x40>; - }; - - gpio0: gpio@e000a000 { - compatible = "xlnx,zynq-gpio-1.0"; - #gpio-cells = <2>; - clocks = <&clkc 42>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&intc>; - interrupts = <0 20 4>; - reg = <0xe000a000 0x1000>; - }; - - i2c0: i2c@e0004000 { - compatible = "cdns,i2c-r1p10"; - status = "disabled"; - clocks = <&clkc 38>; - interrupt-parent = <&intc>; - interrupts = <0 25 4>; - reg = <0xe0004000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c1: i2c@e0005000 { - compatible = "cdns,i2c-r1p10"; - status = "disabled"; - clocks = <&clkc 39>; - interrupt-parent = <&intc>; - interrupts = <0 48 4>; - reg = <0xe0005000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - }; - - intc: interrupt-controller@f8f01000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0xF8F01000 0x1000>, - <0xF8F00100 0x100>; - }; - - L2: cache-controller@f8f02000 { - compatible = "arm,pl310-cache"; - reg = <0xF8F02000 0x1000>; - interrupts = <0 2 4>; - arm,data-latency = <3 2 2>; - arm,tag-latency = <2 2 2>; - cache-unified; - cache-level = <2>; - }; - - mc: memory-controller@f8006000 { - compatible = "xlnx,zynq-ddrc-a05"; - reg = <0xf8006000 0x1000>; - }; - - uart0: serial@e0000000 { - compatible = "xlnx,xuartps", "cdns,uart-r1p8"; - status = "disabled"; - clocks = <&clkc 23>, <&clkc 40>; - clock-names = "uart_clk", "pclk"; - reg = <0xE0000000 0x1000>; - interrupts = <0 27 4>; - }; - - uart1: serial@e0001000 { - compatible = "xlnx,xuartps", "cdns,uart-r1p8"; - status = "disabled"; - clocks = <&clkc 24>, <&clkc 41>; - clock-names = "uart_clk", "pclk"; - reg = <0xE0001000 0x1000>; - interrupts = <0 50 4>; - }; - - spi0: spi@e0006000 { - compatible = "xlnx,zynq-spi-r1p6"; - reg = <0xe0006000 0x1000>; - status = "disabled"; - interrupt-parent = <&intc>; - interrupts = <0 26 4>; - clocks = <&clkc 25>, <&clkc 34>; - clock-names = "ref_clk", "pclk"; - #address-cells = <1>; - #size-cells = <0>; - }; - - spi1: spi@e0007000 { - compatible = "xlnx,zynq-spi-r1p6"; - reg = <0xe0007000 0x1000>; - status = "disabled"; - interrupt-parent = <&intc>; - interrupts = <0 49 4>; - clocks = <&clkc 26>, <&clkc 35>; - clock-names = "ref_clk", "pclk"; - #address-cells = <1>; - #size-cells = <0>; - }; - - gem0: ethernet@e000b000 { - compatible = "cdns,zynq-gem", "cdns,gem"; - reg = <0xe000b000 0x1000>; - status = "disabled"; - interrupts = <0 22 4>; - clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>; - clock-names = "pclk", "hclk", "tx_clk"; - #address-cells = <1>; - #size-cells = <0>; - }; - - gem1: ethernet@e000c000 { - compatible = "cdns,zynq-gem", "cdns,gem"; - reg = <0xe000c000 0x1000>; - status = "disabled"; - interrupts = <0 45 4>; - clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>; - clock-names = "pclk", "hclk", "tx_clk"; - #address-cells = <1>; - #size-cells = <0>; - }; - - sdhci0: mmc@e0100000 { - compatible = "arasan,sdhci-8.9a"; - status = "disabled"; - clock-names = "clk_xin", "clk_ahb"; - clocks = <&clkc 21>, <&clkc 32>; - interrupt-parent = <&intc>; - interrupts = <0 24 4>; - reg = <0xe0100000 0x1000>; - }; - - sdhci1: mmc@e0101000 { - compatible = "arasan,sdhci-8.9a"; - status = "disabled"; - clock-names = "clk_xin", "clk_ahb"; - clocks = <&clkc 22>, <&clkc 33>; - interrupt-parent = <&intc>; - interrupts = <0 47 4>; - reg = <0xe0101000 0x1000>; - }; - - slcr: slcr@f8000000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd"; - reg = <0xF8000000 0x1000>; - ranges; - clkc: clkc@100 { - #clock-cells = <1>; - compatible = "xlnx,ps7-clkc"; - fclk-enable = <0>; - clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", - "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", - "dci", "lqspi", "smc", "pcap", "gem0", "gem1", - "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", - "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", - "dma", "usb0_aper", "usb1_aper", "gem0_aper", - "gem1_aper", "sdio0_aper", "sdio1_aper", - "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", - "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", - "gpio_aper", "lqspi_aper", "smc_aper", "swdt", - "dbg_trc", "dbg_apb"; - reg = <0x100 0x100>; - }; - - rstc: rstc@200 { - compatible = "xlnx,zynq-reset"; - reg = <0x200 0x48>; - #reset-cells = <1>; - syscon = <&slcr>; - }; - - pinctrl0: pinctrl@700 { - compatible = "xlnx,pinctrl-zynq"; - reg = <0x700 0x200>; - syscon = <&slcr>; - }; - }; - - dmac_s: dmac@f8003000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0xf8003000 0x1000>; - interrupt-parent = <&intc>; - interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", - "dma4", "dma5", "dma6", "dma7"; - interrupts = <0 13 4>, - <0 14 4>, <0 15 4>, - <0 16 4>, <0 17 4>, - <0 40 4>, <0 41 4>, - <0 42 4>, <0 43 4>; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <4>; - clocks = <&clkc 27>; - clock-names = "apb_pclk"; - }; - - devcfg: devcfg@f8007000 { - compatible = "xlnx,zynq-devcfg-1.0"; - reg = <0xf8007000 0x100>; - interrupt-parent = <&intc>; - interrupts = <0 8 4>; - clocks = <&clkc 12>; - clock-names = "ref_clk"; - syscon = <&slcr>; - }; - - global_timer: timer@f8f00200 { - compatible = "arm,cortex-a9-global-timer"; - reg = <0xf8f00200 0x20>; - interrupts = <1 11 0x301>; - interrupt-parent = <&intc>; - clocks = <&clkc 4>; - }; - - ttc0: timer@f8001000 { - interrupt-parent = <&intc>; - interrupts = <0 10 4>, <0 11 4>, <0 12 4>; - compatible = "cdns,ttc"; - clocks = <&clkc 6>; - reg = <0xF8001000 0x1000>; - }; - - ttc1: timer@f8002000 { - interrupt-parent = <&intc>; - interrupts = <0 37 4>, <0 38 4>, <0 39 4>; - compatible = "cdns,ttc"; - clocks = <&clkc 6>; - reg = <0xF8002000 0x1000>; - }; - - scutimer: timer@f8f00600 { - interrupt-parent = <&intc>; - interrupts = <1 13 0x301>; - compatible = "arm,cortex-a9-twd-timer"; - reg = <0xf8f00600 0x20>; - clocks = <&clkc 4>; - }; - - usb0: usb@e0002000 { - compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; - status = "disabled"; - clocks = <&clkc 28>; - interrupt-parent = <&intc>; - interrupts = <0 21 4>; - reg = <0xe0002000 0x1000>; - phy_type = "ulpi"; - }; - - usb1: usb@e0003000 { - compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; - status = "disabled"; - clocks = <&clkc 29>; - interrupt-parent = <&intc>; - interrupts = <0 44 4>; - reg = <0xe0003000 0x1000>; - phy_type = "ulpi"; - }; - - watchdog0: watchdog@f8005000 { - clocks = <&clkc 45>; - compatible = "cdns,wdt-r1p2"; - interrupt-parent = <&intc>; - interrupts = <0 9 1>; - reg = <0xf8005000 0x1000>; - timeout-sec = <10>; - }; - - etb@f8801000 { - compatible = "arm,coresight-etb10", "arm,primecell"; - reg = <0xf8801000 0x1000>; - clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; - clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; - in-ports { - port { - etb_in_port: endpoint { - remote-endpoint = <&replicator_out_port1>; - }; - }; - }; - }; - - tpiu@f8803000 { - compatible = "arm,coresight-tpiu", "arm,primecell"; - reg = <0xf8803000 0x1000>; - clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; - clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; - in-ports { - port { - tpiu_in_port: endpoint { - remote-endpoint = <&replicator_out_port0>; - }; - }; - }; - }; - - funnel@f8804000 { - compatible = "arm,coresight-static-funnel", "arm,primecell"; - reg = <0xf8804000 0x1000>; - clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; - clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; - - /* funnel output ports */ - out-ports { - port { - funnel_out_port: endpoint { - remote-endpoint = - <&replicator_in_port0>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - /* funnel input ports */ - port@0 { - reg = <0>; - funnel0_in_port0: endpoint { - remote-endpoint = <&ptm0_out_port>; - }; - }; - - port@1 { - reg = <1>; - funnel0_in_port1: endpoint { - remote-endpoint = <&ptm1_out_port>; - }; - }; - - port@2 { - reg = <2>; - funnel0_in_port2: endpoint { - }; - }; - /* The other input ports are not connect to anything */ - }; - }; - - ptm@f889c000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0xf889c000 0x1000>; - clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; - clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; - cpu = <&cpu0>; - out-ports { - port { - ptm0_out_port: endpoint { - remote-endpoint = <&funnel0_in_port0>; - }; - }; - }; - }; - - ptm@f889d000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0xf889d000 0x1000>; - clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; - clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; - cpu = <&cpu1>; - out-ports { - port { - ptm1_out_port: endpoint { - remote-endpoint = <&funnel0_in_port1>; - }; - }; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/zynq-cc108.dts b/sys/gnu/dts/arm/zynq-cc108.dts deleted file mode 100644 index 8b9ab9bba23..00000000000 --- a/sys/gnu/dts/arm/zynq-cc108.dts +++ /dev/null @@ -1,75 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Xilinx CC108 board DTS - * - * (C) Copyright 2007-2018 Xilinx, Inc. - * (C) Copyright 2007-2013 Michal Simek - * (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd - * - * Michal SIMEK - */ -/dts-v1/; -/include/ "zynq-7000.dtsi" - -/ { - model = "Xilinx CC108 board"; - compatible = "xlnx,zynq-cc108", "xlnx,zynq-7000"; - - aliases { - ethernet0 = &gem0; - serial0 = &uart0; - }; - - chosen { - bootargs = ""; - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x20000000>; - }; - - usb_phy0: phy0 { - compatible = "usb-nop-xceiv"; - #phy-cells = <0>; - }; - - usb_phy1: phy1 { - compatible = "usb-nop-xceiv"; - #phy-cells = <0>; - }; -}; - -&gem0 { - status = "okay"; - phy-mode = "rgmii-id"; - phy-handle = <ðernet_phy>; - - ethernet_phy: ethernet-phy@1 { - reg = <1>; - device_type = "ethernet-phy"; - }; -}; - -&sdhci1 { - status = "okay"; - broken-cd ; - wp-inverted ; -}; - -&uart0 { - status = "okay"; -}; - -&usb0 { - status = "okay"; - dr_mode = "host"; - usb-phy = <&usb_phy0>; -}; - -&usb1 { - status = "okay"; - dr_mode = "host"; - usb-phy = <&usb_phy1>; -}; diff --git a/sys/gnu/dts/arm/zynq-microzed.dts b/sys/gnu/dts/arm/zynq-microzed.dts deleted file mode 100644 index 6ed84fb1590..00000000000 --- a/sys/gnu/dts/arm/zynq-microzed.dts +++ /dev/null @@ -1,88 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2011 - 2014 Xilinx - * Copyright (C) 2016 Jagan Teki - */ -/dts-v1/; -/include/ "zynq-7000.dtsi" - -/ { - model = "Avnet MicroZed board"; - compatible = "avnet,zynq-microzed", "xlnx,zynq-microzed", "xlnx,zynq-7000"; - - aliases { - ethernet0 = &gem0; - serial0 = &uart1; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x40000000>; - }; - - chosen { - bootargs = "earlycon"; - stdout-path = "serial0:115200n8"; - }; - - usb_phy0: phy0 { - compatible = "usb-nop-xceiv"; - #phy-cells = <0>; - }; -}; - -&clkc { - ps-clk-frequency = <33333333>; -}; - -&gem0 { - status = "okay"; - phy-mode = "rgmii-id"; - phy-handle = <ðernet_phy>; - - ethernet_phy: ethernet-phy@0 { - reg = <0>; - }; -}; - -&sdhci0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&usb0 { - status = "okay"; - dr_mode = "host"; - usb-phy = <&usb_phy0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb0_default>; -}; - -&pinctrl0 { - pinctrl_usb0_default: usb0-default { - mux { - groups = "usb0_0_grp"; - function = "usb0"; - }; - - conf { - groups = "usb0_0_grp"; - slew-rate = <0>; - io-standard = <1>; - }; - - conf-rx { - pins = "MIO29", "MIO31", "MIO36"; - bias-high-impedance; - }; - - conf-tx { - pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34", - "MIO35", "MIO37", "MIO38", "MIO39"; - bias-disable; - }; - }; -}; diff --git a/sys/gnu/dts/arm/zynq-parallella.dts b/sys/gnu/dts/arm/zynq-parallella.dts deleted file mode 100644 index 54592aeb92b..00000000000 --- a/sys/gnu/dts/arm/zynq-parallella.dts +++ /dev/null @@ -1,88 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2014 SUSE LINUX Products GmbH - * - * Derived from zynq-zed.dts: - * - * Copyright (C) 2011 Xilinx - * Copyright (C) 2012 National Instruments Corp. - * Copyright (C) 2013 Xilinx - */ -/dts-v1/; -/include/ "zynq-7000.dtsi" - -/ { - model = "Adapteva Parallella board"; - compatible = "adapteva,parallella", "xlnx,zynq-7000"; - - aliases { - ethernet0 = &gem0; - serial0 = &uart1; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x40000000>; - }; - - chosen { - bootargs = "root=/dev/mmcblk0p2 rootfstype=ext4 rw rootwait"; - stdout-path = "serial0:115200n8"; - }; -}; - -&clkc { - fclk-enable = <0xf>; - ps-clk-frequency = <33333333>; -}; - -&gem0 { - status = "okay"; - phy-mode = "rgmii-id"; - phy-handle = <ðernet_phy>; - - ethernet_phy: ethernet-phy@0 { - /* Marvell 88E1318 */ - compatible = "ethernet-phy-id0141.0e90", - "ethernet-phy-ieee802.3-c22"; - reg = <0>; - device_type = "ethernet-phy"; - marvell,reg-init = <0x3 0x10 0xff00 0x1e>, - <0x3 0x11 0xfff0 0xa>; - }; -}; - -&i2c0 { - status = "okay"; - - isl9305: isl9305@68 { - compatible = "isil,isl9305"; - reg = <0x68>; - - regulators { - dcd1 { - regulator-name = "VDD_DSP"; - regulator-always-on; - }; - dcd2 { - regulator-name = "1P35V"; - regulator-always-on; - }; - ldo1 { - regulator-name = "VDD_ADJ"; - }; - ldo2 { - regulator-name = "VDD_GPIO"; - regulator-always-on; - }; - }; - }; -}; - -&sdhci1 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/zynq-zc702.dts b/sys/gnu/dts/arm/zynq-zc702.dts deleted file mode 100644 index 27cd6cb52f1..00000000000 --- a/sys/gnu/dts/arm/zynq-zc702.dts +++ /dev/null @@ -1,401 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2011 - 2014 Xilinx - * Copyright (C) 2012 National Instruments Corp. - */ -/dts-v1/; -#include "zynq-7000.dtsi" - -/ { - model = "Xilinx ZC702 board"; - compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000"; - - aliases { - ethernet0 = &gem0; - i2c0 = &i2c0; - serial0 = &uart1; - mmc0 = &sdhci0; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x40000000>; - }; - - chosen { - bootargs = ""; - stdout-path = "serial0:115200n8"; - }; - - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - sw14 { - label = "sw14"; - gpios = <&gpio0 12 0>; - linux,code = <108>; /* down */ - wakeup-source; - autorepeat; - }; - sw13 { - label = "sw13"; - gpios = <&gpio0 14 0>; - linux,code = <103>; /* up */ - wakeup-source; - autorepeat; - }; - }; - - leds { - compatible = "gpio-leds"; - - ds23 { - label = "ds23"; - gpios = <&gpio0 10 0>; - linux,default-trigger = "heartbeat"; - }; - }; - - usb_phy0: phy0 { - compatible = "usb-nop-xceiv"; - #phy-cells = <0>; - }; -}; - -&amba { - ocm: sram@fffc0000 { - compatible = "mmio-sram"; - reg = <0xfffc0000 0x10000>; - }; -}; - -&can0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can0_default>; -}; - -&clkc { - ps-clk-frequency = <33333333>; -}; - -&gem0 { - status = "okay"; - phy-mode = "rgmii-id"; - phy-handle = <ðernet_phy>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gem0_default>; - - ethernet_phy: ethernet-phy@7 { - reg = <7>; - device_type = "ethernet-phy"; - }; -}; - -&gpio0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio0_default>; -}; - -&i2c0 { - status = "okay"; - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0_default>; - - i2c-mux@74 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x74>; - - i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - si570: clock-generator@5d { - #clock-cells = <0>; - compatible = "silabs,si570"; - temperature-stability = <50>; - reg = <0x5d>; - factory-fout = <156250000>; - clock-frequency = <148500000>; - }; - }; - - i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - adv7511: hdmi-tx@39 { - compatible = "adi,adv7511"; - reg = <0x39>; - adi,input-depth = <8>; - adi,input-colorspace = "yuv422"; - adi,input-clock = "1x"; - adi,input-style = <3>; - adi,input-justification = "right"; - }; - }; - - i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - eeprom@54 { - compatible = "atmel,24c08"; - reg = <0x54>; - }; - }; - - i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - gpio@21 { - compatible = "ti,tca6416"; - reg = <0x21>; - gpio-controller; - #gpio-cells = <2>; - }; - }; - - i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; - }; - - i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - hwmon@34 { - compatible = "ti,ucd9248"; - reg = <0x34>; - }; - hwmon@35 { - compatible = "ti,ucd9248"; - reg = <0x35>; - }; - hwmon@36 { - compatible = "ti,ucd9248"; - reg = <0x36>; - }; - }; - }; -}; - -&pinctrl0 { - pinctrl_can0_default: can0-default { - mux { - function = "can0"; - groups = "can0_9_grp"; - }; - - conf { - groups = "can0_9_grp"; - slew-rate = <0>; - io-standard = <1>; - }; - - conf-rx { - pins = "MIO46"; - bias-high-impedance; - }; - - conf-tx { - pins = "MIO47"; - bias-disable; - }; - }; - - pinctrl_gem0_default: gem0-default { - mux { - function = "ethernet0"; - groups = "ethernet0_0_grp"; - }; - - conf { - groups = "ethernet0_0_grp"; - slew-rate = <0>; - io-standard = <4>; - }; - - conf-rx { - pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27"; - bias-high-impedance; - low-power-disable; - }; - - conf-tx { - pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21"; - bias-disable; - low-power-enable; - }; - - mux-mdio { - function = "mdio0"; - groups = "mdio0_0_grp"; - }; - - conf-mdio { - groups = "mdio0_0_grp"; - slew-rate = <0>; - io-standard = <1>; - bias-disable; - }; - }; - - pinctrl_gpio0_default: gpio0-default { - mux { - function = "gpio0"; - groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp", - "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp", - "gpio0_13_grp", "gpio0_14_grp"; - }; - - conf { - groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp", - "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp", - "gpio0_13_grp", "gpio0_14_grp"; - slew-rate = <0>; - io-standard = <1>; - }; - - conf-pull-up { - pins = "MIO9", "MIO10", "MIO11", "MIO12", "MIO13", "MIO14"; - bias-pull-up; - }; - - conf-pull-none { - pins = "MIO7", "MIO8"; - bias-disable; - }; - }; - - pinctrl_i2c0_default: i2c0-default { - mux { - groups = "i2c0_10_grp"; - function = "i2c0"; - }; - - conf { - groups = "i2c0_10_grp"; - bias-pull-up; - slew-rate = <0>; - io-standard = <1>; - }; - }; - - pinctrl_sdhci0_default: sdhci0-default { - mux { - groups = "sdio0_2_grp"; - function = "sdio0"; - }; - - conf { - groups = "sdio0_2_grp"; - slew-rate = <0>; - io-standard = <1>; - bias-disable; - }; - - mux-cd { - groups = "gpio0_0_grp"; - function = "sdio0_cd"; - }; - - conf-cd { - groups = "gpio0_0_grp"; - bias-high-impedance; - bias-pull-up; - slew-rate = <0>; - io-standard = <1>; - }; - - mux-wp { - groups = "gpio0_15_grp"; - function = "sdio0_wp"; - }; - - conf-wp { - groups = "gpio0_15_grp"; - bias-high-impedance; - bias-pull-up; - slew-rate = <0>; - io-standard = <1>; - }; - }; - - pinctrl_uart1_default: uart1-default { - mux { - groups = "uart1_10_grp"; - function = "uart1"; - }; - - conf { - groups = "uart1_10_grp"; - slew-rate = <0>; - io-standard = <1>; - }; - - conf-rx { - pins = "MIO49"; - bias-high-impedance; - }; - - conf-tx { - pins = "MIO48"; - bias-disable; - }; - }; - - pinctrl_usb0_default: usb0-default { - mux { - groups = "usb0_0_grp"; - function = "usb0"; - }; - - conf { - groups = "usb0_0_grp"; - slew-rate = <0>; - io-standard = <1>; - }; - - conf-rx { - pins = "MIO29", "MIO31", "MIO36"; - bias-high-impedance; - }; - - conf-tx { - pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34", - "MIO35", "MIO37", "MIO38", "MIO39"; - bias-disable; - }; - }; -}; - -&sdhci0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sdhci0_default>; -}; - -&uart1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1_default>; -}; - -&usb0 { - status = "okay"; - dr_mode = "host"; - usb-phy = <&usb_phy0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb0_default>; -}; diff --git a/sys/gnu/dts/arm/zynq-zc706.dts b/sys/gnu/dts/arm/zynq-zc706.dts deleted file mode 100644 index 77943c16d33..00000000000 --- a/sys/gnu/dts/arm/zynq-zc706.dts +++ /dev/null @@ -1,324 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2011 - 2014 Xilinx - * Copyright (C) 2012 National Instruments Corp. - */ -/dts-v1/; -#include "zynq-7000.dtsi" - -/ { - model = "Xilinx ZC706 board"; - compatible = "xlnx,zynq-zc706", "xlnx,zynq-7000"; - - aliases { - ethernet0 = &gem0; - i2c0 = &i2c0; - serial0 = &uart1; - mmc0 = &sdhci0; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x40000000>; - }; - - chosen { - bootargs = ""; - stdout-path = "serial0:115200n8"; - }; - - usb_phy0: phy0 { - compatible = "usb-nop-xceiv"; - #phy-cells = <0>; - }; -}; - -&clkc { - ps-clk-frequency = <33333333>; -}; - -&gem0 { - status = "okay"; - phy-mode = "rgmii-id"; - phy-handle = <ðernet_phy>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gem0_default>; - - ethernet_phy: ethernet-phy@7 { - reg = <7>; - device_type = "ethernet-phy"; - }; -}; - -&gpio0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio0_default>; -}; - -&i2c0 { - status = "okay"; - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0_default>; - - i2c-mux@74 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x74>; - - i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - si570: clock-generator@5d { - #clock-cells = <0>; - compatible = "silabs,si570"; - temperature-stability = <50>; - reg = <0x5d>; - factory-fout = <156250000>; - clock-frequency = <148500000>; - }; - }; - - i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - adv7511: hdmi-tx@39 { - compatible = "adi,adv7511"; - reg = <0x39>; - adi,input-depth = <8>; - adi,input-colorspace = "yuv422"; - adi,input-clock = "1x"; - adi,input-style = <3>; - adi,input-justification = "evenly"; - }; - }; - - i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - eeprom@54 { - compatible = "atmel,24c08"; - reg = <0x54>; - }; - }; - - i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - gpio@21 { - compatible = "ti,tca6416"; - reg = <0x21>; - gpio-controller; - #gpio-cells = <2>; - }; - }; - - i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; - }; - - i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - ucd90120@65 { - compatible = "ti,ucd90120"; - reg = <0x65>; - }; - }; - }; -}; - -&pinctrl0 { - pinctrl_gem0_default: gem0-default { - mux { - function = "ethernet0"; - groups = "ethernet0_0_grp"; - }; - - conf { - groups = "ethernet0_0_grp"; - slew-rate = <0>; - io-standard = <4>; - }; - - conf-rx { - pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27"; - bias-high-impedance; - low-power-disable; - }; - - conf-tx { - pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21"; - low-power-enable; - bias-disable; - }; - - mux-mdio { - function = "mdio0"; - groups = "mdio0_0_grp"; - }; - - conf-mdio { - groups = "mdio0_0_grp"; - slew-rate = <0>; - io-standard = <1>; - bias-disable; - }; - }; - - pinctrl_gpio0_default: gpio0-default { - mux { - function = "gpio0"; - groups = "gpio0_7_grp", "gpio0_46_grp", "gpio0_47_grp"; - }; - - conf { - groups = "gpio0_7_grp", "gpio0_46_grp", "gpio0_47_grp"; - slew-rate = <0>; - io-standard = <1>; - }; - - conf-pull-up { - pins = "MIO46", "MIO47"; - bias-pull-up; - }; - - conf-pull-none { - pins = "MIO7"; - bias-disable; - }; - }; - - pinctrl_i2c0_default: i2c0-default { - mux { - groups = "i2c0_10_grp"; - function = "i2c0"; - }; - - conf { - groups = "i2c0_10_grp"; - bias-pull-up; - slew-rate = <0>; - io-standard = <1>; - }; - }; - - pinctrl_sdhci0_default: sdhci0-default { - mux { - groups = "sdio0_2_grp"; - function = "sdio0"; - }; - - conf { - groups = "sdio0_2_grp"; - slew-rate = <0>; - io-standard = <1>; - bias-disable; - }; - - mux-cd { - groups = "gpio0_14_grp"; - function = "sdio0_cd"; - }; - - conf-cd { - groups = "gpio0_14_grp"; - bias-high-impedance; - bias-pull-up; - slew-rate = <0>; - io-standard = <1>; - }; - - mux-wp { - groups = "gpio0_15_grp"; - function = "sdio0_wp"; - }; - - conf-wp { - groups = "gpio0_15_grp"; - bias-high-impedance; - bias-pull-up; - slew-rate = <0>; - io-standard = <1>; - }; - }; - - pinctrl_uart1_default: uart1-default { - mux { - groups = "uart1_10_grp"; - function = "uart1"; - }; - - conf { - groups = "uart1_10_grp"; - slew-rate = <0>; - io-standard = <1>; - }; - - conf-rx { - pins = "MIO49"; - bias-high-impedance; - }; - - conf-tx { - pins = "MIO48"; - bias-disable; - }; - }; - - pinctrl_usb0_default: usb0-default { - mux { - groups = "usb0_0_grp"; - function = "usb0"; - }; - - conf { - groups = "usb0_0_grp"; - slew-rate = <0>; - io-standard = <1>; - }; - - conf-rx { - pins = "MIO29", "MIO31", "MIO36"; - bias-high-impedance; - }; - - conf-tx { - pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34", - "MIO35", "MIO37", "MIO38", "MIO39"; - bias-disable; - }; - }; -}; - -&sdhci0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sdhci0_default>; -}; - -&uart1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1_default>; -}; - -&usb0 { - status = "okay"; - dr_mode = "host"; - usb-phy = <&usb_phy0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb0_default>; -}; diff --git a/sys/gnu/dts/arm/zynq-zc770-xm010.dts b/sys/gnu/dts/arm/zynq-zc770-xm010.dts deleted file mode 100644 index 0dd352289a4..00000000000 --- a/sys/gnu/dts/arm/zynq-zc770-xm010.dts +++ /dev/null @@ -1,95 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Xilinx ZC770 XM010 board DTS - * - * Copyright (C) 2013-2018 Xilinx, Inc. - */ -/dts-v1/; -#include "zynq-7000.dtsi" - -/ { - model = "Xilinx ZC770 XM010 board"; - compatible = "xlnx,zynq-zc770-xm010", "xlnx,zynq-7000"; - - aliases { - ethernet0 = &gem0; - i2c0 = &i2c0; - serial0 = &uart1; - spi1 = &spi1; - }; - - chosen { - bootargs = ""; - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x40000000>; - }; - - usb_phy0: phy0 { - compatible = "usb-nop-xceiv"; - #phy-cells = <0>; - }; -}; - -&can0 { - status = "okay"; -}; - -&gem0 { - status = "okay"; - phy-mode = "rgmii-id"; - phy-handle = <ðernet_phy>; - - ethernet_phy: ethernet-phy@7 { - reg = <7>; - device_type = "ethernet-phy"; - }; -}; - -&i2c0 { - status = "okay"; - clock-frequency = <400000>; - - eeprom: eeprom@52 { - compatible = "atmel,24c02"; - reg = <0x52>; - }; - -}; - -&sdhci0 { - status = "okay"; -}; - -&spi1 { - status = "okay"; - num-cs = <4>; - is-decoded-cs = <0>; - flash@1 { - compatible = "sst25wf080", "jedec,spi-nor"; - reg = <1>; - spi-max-frequency = <1000000>; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - partition@0 { - label = "data"; - reg = <0x0 0x100000>; - }; - }; - }; -}; - -&uart1 { - status = "okay"; -}; - -&usb0 { - status = "okay"; - dr_mode = "host"; - usb-phy = <&usb_phy0>; -}; diff --git a/sys/gnu/dts/arm/zynq-zc770-xm011.dts b/sys/gnu/dts/arm/zynq-zc770-xm011.dts deleted file mode 100644 index b7f65862c02..00000000000 --- a/sys/gnu/dts/arm/zynq-zc770-xm011.dts +++ /dev/null @@ -1,64 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Xilinx ZC770 XM013 board DTS - * - * Copyright (C) 2013-2018 Xilinx, Inc. - */ -/dts-v1/; -#include "zynq-7000.dtsi" - -/ { - model = "Xilinx ZC770 XM011 board"; - compatible = "xlnx,zynq-zc770-xm011", "xlnx,zynq-7000"; - - aliases { - i2c0 = &i2c1; - serial0 = &uart1; - spi0 = &spi0; - }; - - chosen { - bootargs = ""; - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x40000000>; - }; - - usb_phy1: phy1 { - compatible = "usb-nop-xceiv"; - #phy-cells = <0>; - }; -}; - -&can0 { - status = "okay"; -}; - -&i2c1 { - status = "okay"; - clock-frequency = <400000>; - - eeprom: eeprom@52 { - compatible = "atmel,24c02"; - reg = <0x52>; - }; -}; - -&spi0 { - status = "okay"; - num-cs = <4>; - is-decoded-cs = <0>; -}; - -&uart1 { - status = "okay"; -}; - -&usb1 { - status = "okay"; - dr_mode = "host"; - usb-phy = <&usb_phy1>; -}; diff --git a/sys/gnu/dts/arm/zynq-zc770-xm012.dts b/sys/gnu/dts/arm/zynq-zc770-xm012.dts deleted file mode 100644 index d2359b789eb..00000000000 --- a/sys/gnu/dts/arm/zynq-zc770-xm012.dts +++ /dev/null @@ -1,64 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Xilinx ZC770 XM012 board DTS - * - * Copyright (C) 2013-2018 Xilinx, Inc. - */ -/dts-v1/; -#include "zynq-7000.dtsi" - -/ { - model = "Xilinx ZC770 XM012 board"; - compatible = "xlnx,zynq-zc770-xm012", "xlnx,zynq-7000"; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - serial0 = &uart1; - spi0 = &spi1; - }; - - chosen { - bootargs = ""; - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x40000000>; - }; -}; - -&can1 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - clock-frequency = <400000>; - - eeprom0: eeprom@52 { - compatible = "atmel,24c02"; - reg = <0x52>; - }; -}; - -&i2c1 { - status = "okay"; - clock-frequency = <400000>; - - eeprom1: eeprom@52 { - compatible = "atmel,24c02"; - reg = <0x52>; - }; -}; - -&spi1 { - status = "okay"; - num-cs = <4>; - is-decoded-cs = <0>; -}; - -&uart1 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/zynq-zc770-xm013.dts b/sys/gnu/dts/arm/zynq-zc770-xm013.dts deleted file mode 100644 index 4ae2c85df3a..00000000000 --- a/sys/gnu/dts/arm/zynq-zc770-xm013.dts +++ /dev/null @@ -1,78 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Xilinx ZC770 XM013 board DTS - * - * Copyright (C) 2013 Xilinx, Inc. - */ -/dts-v1/; -#include "zynq-7000.dtsi" - -/ { - model = "Xilinx ZC770 XM013 board"; - compatible = "xlnx,zynq-zc770-xm013", "xlnx,zynq-7000"; - - aliases { - ethernet0 = &gem1; - i2c0 = &i2c1; - serial0 = &uart0; - spi1 = &spi0; - }; - - chosen { - bootargs = ""; - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x40000000>; - }; -}; - -&can1 { - status = "okay"; -}; - -&gem1 { - status = "okay"; - phy-mode = "rgmii-id"; - phy-handle = <ðernet_phy>; - - ethernet_phy: ethernet-phy@7 { - reg = <7>; - device_type = "ethernet-phy"; - }; -}; - -&i2c1 { - status = "okay"; - clock-frequency = <400000>; - - si570: clock-generator@55 { - #clock-cells = <0>; - compatible = "silabs,si570"; - temperature-stability = <50>; - reg = <0x55>; - factory-fout = <156250000>; - clock-frequency = <148500000>; - }; -}; - -&spi0 { - status = "okay"; - num-cs = <4>; - is-decoded-cs = <0>; - eeprom: eeprom@2 { - at25,byte-len = <8192>; - at25,addr-mode = <2>; - at25,page-size = <32>; - - compatible = "atmel,at25"; - reg = <2>; - spi-max-frequency = <1000000>; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/zynq-zed.dts b/sys/gnu/dts/arm/zynq-zed.dts deleted file mode 100644 index 6a5a93aa655..00000000000 --- a/sys/gnu/dts/arm/zynq-zed.dts +++ /dev/null @@ -1,62 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2011 - 2014 Xilinx - * Copyright (C) 2012 National Instruments Corp. - */ -/dts-v1/; -#include "zynq-7000.dtsi" - -/ { - model = "Avnet ZedBoard board"; - compatible = "avnet,zynq-zed", "xlnx,zynq-zed", "xlnx,zynq-7000"; - - aliases { - ethernet0 = &gem0; - serial0 = &uart1; - mmc0 = &sdhci0; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x20000000>; - }; - - chosen { - bootargs = ""; - stdout-path = "serial0:115200n8"; - }; - - usb_phy0: phy0 { - compatible = "usb-nop-xceiv"; - #phy-cells = <0>; - }; -}; - -&clkc { - ps-clk-frequency = <33333333>; -}; - -&gem0 { - status = "okay"; - phy-mode = "rgmii-id"; - phy-handle = <ðernet_phy>; - - ethernet_phy: ethernet-phy@0 { - reg = <0>; - device_type = "ethernet-phy"; - }; -}; - -&sdhci0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&usb0 { - status = "okay"; - dr_mode = "host"; - usb-phy = <&usb_phy0>; -}; diff --git a/sys/gnu/dts/arm/zynq-zturn.dts b/sys/gnu/dts/arm/zynq-zturn.dts deleted file mode 100644 index 5ec616ebca0..00000000000 --- a/sys/gnu/dts/arm/zynq-zturn.dts +++ /dev/null @@ -1,114 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2015 Andrea Merello - * Copyright (C) 2017 Alexander Graf - * - * Based on zynq-zed.dts which is: - * Copyright (C) 2011 - 2014 Xilinx - * Copyright (C) 2012 National Instruments Corp. - * - */ - -/dts-v1/; -/include/ "zynq-7000.dtsi" - -/ { - model = "Zynq Z-Turn MYIR Board"; - compatible = "myir,zynq-zturn", "xlnx,zynq-7000"; - - aliases { - ethernet0 = &gem0; - serial0 = &uart1; - serial1 = &uart0; - mmc0 = &sdhci0; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x40000000>; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - gpio-leds { - compatible = "gpio-leds"; - usr-led1 { - label = "usr-led1"; - gpios = <&gpio0 0x0 0x1>; - default-state = "off"; - }; - - usr-led2 { - label = "usr-led2"; - gpios = <&gpio0 0x9 0x1>; - default-state = "off"; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - K1 { - label = "K1"; - gpios = <&gpio0 0x32 0x1>; - linux,code = <0x66>; - wakeup-source; - autorepeat; - }; - }; -}; - -&clkc { - ps-clk-frequency = <33333333>; -}; - -&gem0 { - status = "okay"; - phy-mode = "rgmii-id"; - phy-handle = <ðernet_phy>; - - ethernet_phy: ethernet-phy@0 { - reg = <0x0>; - }; -}; - -&sdhci0 { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&usb0 { - status = "okay"; - dr_mode = "host"; -}; - -&can0 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - clock-frequency = <400000>; - - stlm75@49 { - status = "okay"; - compatible = "lm75"; - reg = <0x49>; - }; - - accelerometer@53 { - compatible = "adi,adxl345", "adxl345", "adi,adxl34x", "adxl34x"; - reg = <0x53>; - interrupt-parent = <&intc>; - interrupts = <0x0 0x1e 0x4>; - }; -}; diff --git a/sys/gnu/dts/arm/zynq-zybo-z7.dts b/sys/gnu/dts/arm/zynq-zybo-z7.dts deleted file mode 100644 index 357b78a5c11..00000000000 --- a/sys/gnu/dts/arm/zynq-zybo-z7.dts +++ /dev/null @@ -1,68 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/dts-v1/; -#include "zynq-7000.dtsi" -#include - -/ { - model = "Digilent Zybo Z7 board"; - compatible = "digilent,zynq-zybo-z7", "xlnx,zynq-7000"; - - aliases { - ethernet0 = &gem0; - serial0 = &uart1; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x40000000>; - }; - - chosen { - bootargs = ""; - stdout-path = "serial0:115200n8"; - }; - - gpio-leds { - compatible = "gpio-leds"; - - ld4 { - label = "zynq-zybo-z7:green:ld4"; - gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>; - }; - }; - - usb_phy0: phy0 { - #phy-cells = <0>; - compatible = "usb-nop-xceiv"; - reset-gpios = <&gpio0 46 GPIO_ACTIVE_LOW>; - }; -}; - -&clkc { - ps-clk-frequency = <33333333>; -}; - -&gem0 { - status = "okay"; - phy-mode = "rgmii-id"; - phy-handle = <ðernet_phy>; - - ethernet_phy: ethernet-phy@0 { - reg = <0>; - device_type = "ethernet-phy"; - }; -}; - -&sdhci0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&usb0 { - status = "okay"; - dr_mode = "host"; - usb-phy = <&usb_phy0>; -}; diff --git a/sys/gnu/dts/arm/zynq-zybo.dts b/sys/gnu/dts/arm/zynq-zybo.dts deleted file mode 100644 index 755f6f109d5..00000000000 --- a/sys/gnu/dts/arm/zynq-zybo.dts +++ /dev/null @@ -1,63 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2011 - 2014 Xilinx - * Copyright (C) 2012 National Instruments Corp. - */ -/dts-v1/; -#include "zynq-7000.dtsi" - -/ { - model = "Digilent Zybo board"; - compatible = "digilent,zynq-zybo", "xlnx,zynq-7000"; - - aliases { - ethernet0 = &gem0; - serial0 = &uart1; - mmc0 = &sdhci0; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x20000000>; - }; - - chosen { - bootargs = ""; - stdout-path = "serial0:115200n8"; - }; - - usb_phy0: phy0 { - #phy-cells = <0>; - compatible = "usb-nop-xceiv"; - reset-gpios = <&gpio0 46 1>; - }; -}; - -&clkc { - ps-clk-frequency = <50000000>; -}; - -&gem0 { - status = "okay"; - phy-mode = "rgmii-id"; - phy-handle = <ðernet_phy>; - - ethernet_phy: ethernet-phy@0 { - reg = <0>; - device_type = "ethernet-phy"; - }; -}; - -&sdhci0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&usb0 { - status = "okay"; - dr_mode = "host"; - usb-phy = <&usb_phy0>; -}; diff --git a/sys/gnu/dts/arm64/actions/s700-cubieboard7.dts b/sys/gnu/dts/arm64/actions/s700-cubieboard7.dts deleted file mode 100644 index 63e375cd9eb..00000000000 --- a/sys/gnu/dts/arm64/actions/s700-cubieboard7.dts +++ /dev/null @@ -1,92 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 Andreas Färber - */ - -/dts-v1/; - -#include "s700.dtsi" - -/ { - compatible = "cubietech,cubieboard7", "actions,s700"; - model = "CubieBoard7"; - - aliases { - serial3 = &uart3; - }; - - chosen { - stdout-path = "serial3:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; - - memory@1,e0000000 { - device_type = "memory"; - reg = <0x1 0xe0000000 0x0 0x0>; - }; -}; - -&i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_default>; -}; - -&i2c1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_default>; -}; - -&i2c2 { - status = "disabled"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_default>; -}; - -&pinctrl { - i2c0_default: i2c0_default { - pinmux { - groups = "i2c0_mfp"; - function = "i2c0"; - }; - pinconf { - pins = "i2c0_sclk", "i2c0_sdata"; - bias-pull-up; - }; - }; - - i2c1_default: i2c1_default { - pinmux { - groups = "i2c1_dummy"; - function = "i2c1"; - }; - pinconf { - pins = "i2c1_sclk", "i2c1_sdata"; - bias-pull-up; - }; - }; - - i2c2_default: i2c2_default { - pinmux { - groups = "i2c2_dummy"; - function = "i2c2"; - }; - pinconf { - pins = "i2c2_sclk", "i2c2_sdata"; - bias-pull-up; - }; - }; -}; - -&timer { - clocks = <&hosc>; -}; - -&uart3 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/actions/s700.dtsi b/sys/gnu/dts/arm64/actions/s700.dtsi deleted file mode 100644 index 2006ad5424f..00000000000 --- a/sys/gnu/dts/arm64/actions/s700.dtsi +++ /dev/null @@ -1,248 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 Andreas Färber - */ - -#include -#include -#include - -/ { - compatible = "actions,s700"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x0>; - enable-method = "psci"; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x1>; - enable-method = "psci"; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x2>; - enable-method = "psci"; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x3>; - enable-method = "psci"; - }; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - secmon@1f000000 { - reg = <0x0 0x1f000000 0x0 0x1000000>; - no-map; - }; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - arm-pmu { - compatible = "arm,cortex-a53-pmu"; - interrupts = , - , - , - ; - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - hosc: hosc { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - #clock-cells = <0>; - }; - - losc: losc { - compatible = "fixed-clock"; - clock-frequency = <32768>; - #clock-cells = <0>; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - gic: interrupt-controller@e00f1000 { - compatible = "arm,gic-400"; - reg = <0x0 0xe00f1000 0x0 0x1000>, - <0x0 0xe00f2000 0x0 0x2000>, - <0x0 0xe00f4000 0x0 0x2000>, - <0x0 0xe00f6000 0x0 0x2000>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <3>; - }; - - uart0: serial@e0120000 { - compatible = "actions,s900-uart", "actions,owl-uart"; - reg = <0x0 0xe0120000 0x0 0x2000>; - clocks = <&cmu CLK_UART0>; - interrupts = ; - status = "disabled"; - }; - - uart1: serial@e0122000 { - compatible = "actions,s900-uart", "actions,owl-uart"; - reg = <0x0 0xe0122000 0x0 0x2000>; - clocks = <&cmu CLK_UART1>; - interrupts = ; - status = "disabled"; - }; - - uart2: serial@e0124000 { - compatible = "actions,s900-uart", "actions,owl-uart"; - reg = <0x0 0xe0124000 0x0 0x2000>; - clocks = <&cmu CLK_UART2>; - interrupts = ; - status = "disabled"; - }; - - uart3: serial@e0126000 { - compatible = "actions,s900-uart", "actions,owl-uart"; - reg = <0x0 0xe0126000 0x0 0x2000>; - clocks = <&cmu CLK_UART3>; - interrupts = ; - status = "disabled"; - }; - - uart4: serial@e0128000 { - compatible = "actions,s900-uart", "actions,owl-uart"; - reg = <0x0 0xe0128000 0x0 0x2000>; - clocks = <&cmu CLK_UART4>; - interrupts = ; - status = "disabled"; - }; - - uart5: serial@e012a000 { - compatible = "actions,s900-uart", "actions,owl-uart"; - reg = <0x0 0xe012a000 0x0 0x2000>; - clocks = <&cmu CLK_UART5>; - interrupts = ; - status = "disabled"; - }; - - uart6: serial@e012c000 { - compatible = "actions,s900-uart", "actions,owl-uart"; - reg = <0x0 0xe012c000 0x0 0x2000>; - clocks = <&cmu CLK_UART6>; - interrupts = ; - status = "disabled"; - }; - - cmu: clock-controller@e0168000 { - compatible = "actions,s700-cmu"; - reg = <0x0 0xe0168000 0x0 0x1000>; - clocks = <&hosc>, <&losc>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - i2c0: i2c@e0170000 { - compatible = "actions,s700-i2c"; - reg = <0 0xe0170000 0 0x1000>; - clocks = <&cmu CLK_I2C0>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c1: i2c@e0174000 { - compatible = "actions,s700-i2c"; - reg = <0 0xe0174000 0 0x1000>; - clocks = <&cmu CLK_I2C1>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@e0178000 { - compatible = "actions,s700-i2c"; - reg = <0 0xe0178000 0 0x1000>; - clocks = <&cmu CLK_I2C2>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c3: i2c@e017c000 { - compatible = "actions,s700-i2c"; - reg = <0 0xe017c000 0 0x1000>; - clocks = <&cmu CLK_I2C3>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - sps: power-controller@e01b0100 { - compatible = "actions,s700-sps"; - reg = <0x0 0xe01b0100 0x0 0x100>; - #power-domain-cells = <1>; - }; - - timer: timer@e024c000 { - compatible = "actions,s700-timer"; - reg = <0x0 0xe024c000 0x0 0x4000>; - interrupts = ; - interrupt-names = "timer1"; - }; - - pinctrl: pinctrl@e01b0000 { - compatible = "actions,s700-pinctrl"; - reg = <0x0 0xe01b0000 0x0 0x1000>; - clocks = <&cmu CLK_GPIO>; - gpio-controller; - gpio-ranges = <&pinctrl 0 0 136>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = , - , - , - , - ; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/actions/s900-bubblegum-96.dts b/sys/gnu/dts/arm64/actions/s900-bubblegum-96.dts deleted file mode 100644 index 59291e0ea1e..00000000000 --- a/sys/gnu/dts/arm64/actions/s900-bubblegum-96.dts +++ /dev/null @@ -1,314 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 Andreas Färber - */ - -/dts-v1/; - -#include "s900.dtsi" - -/ { - compatible = "ucrobotics,bubblegum-96", "actions,s900"; - model = "Bubblegum-96"; - - aliases { - mmc0 = &mmc0; - mmc1 = &mmc1; - mmc2 = &mmc2; - serial5 = &uart5; - }; - - chosen { - stdout-path = "serial5:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; - - /* Fixed regulator used in the absence of PMIC */ - vcc_3v1: vcc-3v1 { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.1V"; - regulator-min-microvolt = <3100000>; - regulator-max-microvolt = <3100000>; - regulator-always-on; - }; - - /* Fixed regulator used in the absence of PMIC */ - sd_vcc: sd-vcc { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.1V"; - regulator-min-microvolt = <3100000>; - regulator-max-microvolt = <3100000>; - regulator-always-on; - }; -}; - -&i2c0 { - status = "disabled"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_default>; -}; - -&i2c1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_default>; -}; - -&i2c2 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_default>; -}; - -/* - * GPIO name legend: proper name = the GPIO line is used as GPIO - * NC = not connected (pin out but not routed from the chip to - * anything the board) - * "[PER]" = pin is muxed for [peripheral] (not GPIO) - * LSEC = Low Speed External Connector - * HSEC = High Speed External Connector - * - * Line names are taken from the schematic "Schematics Bubblegum96" - * version v1.0 - * - * For the lines routed to the external connectors the - * lines are named after the 96Boards CE Specification 1.0, - * Appendix "Expansion Connector Signal Description". - * - * When the 96Boards naming of a line and the schematic name of - * the same line are in conflict, the 96Boards specification - * takes precedence, which means that the external UART on the - * LSEC is named UART0 while the schematic and SoC names this - * UART2. Only exception is the I2C lines for which the schematic - * naming has been preferred. This is only for the informational - * lines i.e. "[FOO]", the GPIO named lines "GPIO-A" thru "GPIO-L" - * are the only ones actually used for GPIO. - */ - -&pinctrl { - gpio-line-names = - "GPIO-A", /* GPIO_0, LSEC pin 23 */ - "GPIO-B", /* GPIO_1, LSEC pin 24 */ - "GPIO-C", /* GPIO_2, LSEC pin 25 */ - "GPIO-D", /* GPIO_3, LSEC pin 26 */ - "GPIO-E", /* GPIO_4, LSEC pin 27 */ - "GPIO-F", /* GPIO_5, LSEC pin 28 */ - "GPIO-G", /* GPIO_6, LSEC pin 29 */ - "GPIO-H", /* GPIO_7, LSEC pin 30 */ - "GPIO-I", /* GPIO_8, LSEC pin 31 */ - "GPIO-J", /* GPIO_9, LSEC pin 32 */ - "NC", /* GPIO_10 */ - "NC", /* GPIO_11 */ - "SIRQ2_1V8", /* GPIO_12 */ - "PCM0_OUT", /* GPIO_13 */ - "WIFI_LED", /* GPIO_14 */ - "PCM0_SYNC", /* GPIO_15 */ - "PCM0_CLK", /* GPIO_16 */ - "PCM0_IN", /* GPIO_17 */ - "BT_LED", /* GPIO_18 */ - "LED0", /* GPIO_19 */ - "LED1", /* GPIO_20 */ - "JTAG_TCK", /* GPIO_21 */ - "JTAG_TMS", /* GPIO_22 */ - "JTAG_TDI", /* GPIO_23 */ - "JTAG_TDO", /* GPIO_24 */ - "[UART1_RxD]", /* GPIO_25, LSEC pin 13 */ - "NC", /* GPIO_26 */ - "[UART1_TxD]", /* GPIO_27, LSEC pin 11 */ - "SD0_D0", /* GPIO_28 */ - "SD0_D1", /* GPIO_29 */ - "SD0_D2", /* GPIO_30 */ - "SD0_D3", /* GPIO_31 */ - "SD1_D0", /* GPIO_32 */ - "SD1_D1", /* GPIO_33 */ - "SD1_D2", /* GPIO_34 */ - "SD1_D3", /* GPIO_35 */ - "SD0_CMD", /* GPIO_36 */ - "SD0_CLK", /* GPIO_37 */ - "SD1_CMD", /* GPIO_38 */ - "SD1_CLK", /* GPIO_39 */ - "SPI0_SCLK", /* GPIO_40, LSEC pin 8 */ - "SPI0_CS", /* GPIO_41, LSEC pin 12 */ - "SPI0_DIN", /* GPIO_42, LSEC pin 10 */ - "SPI0_DOUT", /* GPIO_43, LSEC pin 14 */ - "I2C5_SDATA", /* GPIO_44, HSEC pin 36 */ - "I2C5_SCLK", /* GPIO_45, HSEC pin 38 */ - "UART0_RX", /* GPIO_46, LSEC pin 7 */ - "UART0_TX", /* GPIO_47, LSEC pin 5 */ - "UART0_RTSB", /* GPIO_48, LSEC pin 9 */ - "UART0_CTSB", /* GPIO_49, LSEC pin 3 */ - "I2C4_SCLK", /* GPIO_50, HSEC pin 32 */ - "I2C4_SDATA", /* GPIO_51, HSEC pin 34 */ - "I2C0_SCLK", /* GPIO_52 */ - "I2C0_SDATA", /* GPIO_53 */ - "I2C1_SCLK", /* GPIO_54, LSEC pin 15 */ - "I2C1_SDATA", /* GPIO_55, LSEC pin 17 */ - "I2C2_SCLK", /* GPIO_56, LSEC pin 19 */ - "I2C2_SDATA", /* GPIO_57, LSEC pin 21 */ - "CSI0_DN0", /* GPIO_58, HSEC pin 10 */ - "CSI0_DP0", /* GPIO_59, HSEC pin 8 */ - "CSI0_DN1", /* GPIO_60, HSEC pin 16 */ - "CSI0_DP1", /* GPIO_61, HSEC pin 14 */ - "CSI0_CN", /* GPIO_62, HSEC pin 4 */ - "CSI0_CP", /* GPIO_63, HSEC pin 2 */ - "CSI0_DN2", /* GPIO_64, HSEC pin 22 */ - "CSI0_DP2", /* GPIO_65, HSEC pin 20 */ - "CSI0_DN3", /* GPIO_66, HSEC pin 28 */ - "CSI0_DP3", /* GPIO_67, HSEC pin 26 */ - "[CLK0]", /* GPIO_68, HSEC pin 15 */ - "CSI1_DN0", /* GPIO_69, HSEC pin 44 */ - "CSI1_DP0", /* GPIO_70, HSEC pin 42 */ - "CSI1_DN1", /* GPIO_71, HSEC pin 50 */ - "CSI1_DP1", /* GPIO_72, HSEC pin 48 */ - "CSI1_CN", /* GPIO_73, HSEC pin 56 */ - "CSI1_CP", /* GPIO_74, HSEC pin 54 */ - "[CLK1]", /* GPIO_75, HSEC pin 17 */ - "[GPIOD0]", /* GPIO_76 */ - "[GPIOD1]", /* GPIO_77 */ - "BT_RST_N", /* GPIO_78 */ - "EXT_DC_EN", /* GPIO_79 */ - "[PCM_DI]", /* GPIO_80, LSEC pin 22 */ - "[PCM_DO]", /* GPIO_81, LSEC pin 20 */ - "[PCM_CLK]", /* GPIO_82, LSEC pin 18 */ - "[PCM_FS]", /* GPIO_83, LSEC pin 16 */ - "WAKE_BT", /* GPIO_84 */ - "WL_REG_ON", /* GPIO_85 */ - "NC", /* GPIO_86 */ - "NC", /* GPIO_87 */ - "NC", /* GPIO_88 */ - "NC", /* GPIO_89 */ - "NC", /* GPIO_90 */ - "WIFI_WAKE", /* GPIO_91 */ - "BT_WAKE", /* GPIO_92 */ - "NC", /* GPIO_93 */ - "OTG_EN2", /* GPIO_94 */ - "OTG_EN", /* GPIO_95 */ - "DSI_DP3", /* GPIO_96, HSEC pin 45 */ - "DSI_DN3", /* GPIO_97, HSEC pin 47 */ - "DSI_DP1", /* GPIO_98, HSEC pin 33 */ - "DSI_DN1", /* GPIO_99, HSEC pin 35 */ - "DSI_CP", /* GPIO_100, HSEC pin 21 */ - "DSI_CN", /* GPIO_101, HSEC pin 23 */ - "DSI_DP0", /* GPIO_102, HSEC pin 27 */ - "DSI_DN0", /* GPIO_103, HSEC pin 29 */ - "DSI_DP2", /* GPIO_104, HSEC pin 39 */ - "DSI_DN2", /* GPIO_105, HSEC pin 41 */ - "N0_D0", /* GPIO_106 */ - "N0_D1", /* GPIO_107 */ - "N0_D2", /* GPIO_108 */ - "N0_D3", /* GPIO_109 */ - "N0_D4", /* GPIO_110 */ - "N0_D5", /* GPIO_111 */ - "N0_D6", /* GPIO_112 */ - "N0_D7", /* GPIO_113 */ - "N0_DQS", /* GPIO_114 */ - "N0_DQSN", /* GPIO_115 */ - "NC", /* GPIO_116 */ - "NC", /* GPIO_117 */ - "NC", /* GPIO_118 */ - "N0_CEB1", /* GPIO_119 */ - "CARD_DT", /* GPIO_120 */ - "N0_CEB3", /* GPIO_121 */ - "SD_DAT0", /* GPIO_122, HSEC pin 1 */ - "SD_DAT1", /* GPIO_123, HSEC pin 3 */ - "SD_DAT2", /* GPIO_124, HSEC pin 5 */ - "SD_DAT3", /* GPIO_125, HSEC pin 7 */ - "NC", /* GPIO_126 */ - "NC", /* GPIO_127 */ - "[PWR_BTN_N]", /* GPIO_128, LSEC pin 4 */ - "[RST_BTN_N]", /* GPIO_129, LSEC pin 6 */ - "NC", /* GPIO_130 */ - "SD_CMD", /* GPIO_131 */ - "GPIO-L", /* GPIO_132, LSEC pin 34 */ - "GPIO-K", /* GPIO_133, LSEC pin 33 */ - "NC", /* GPIO_134 */ - "SD_SCLK", /* GPIO_135 */ - "NC", /* GPIO_136 */ - "JTAG_TRST", /* GPIO_137 */ - "I2C3_SCLK", /* GPIO_138 */ - "LED2", /* GPIO_139 */ - "LED3", /* GPIO_140 */ - "I2C3_SDATA", /* GPIO_141 */ - "UART3_RX", /* GPIO_142 */ - "UART3_TX", /* GPIO_143 */ - "UART3_RTSB", /* GPIO_144 */ - "UART3_CTSB"; /* GPIO_145 */ - - i2c0_default: i2c0-default { - pinmux { - groups = "i2c0_mfp"; - function = "i2c0"; - }; - pinconf { - pins = "i2c0_sclk", "i2c0_sdata"; - bias-pull-up; - }; - }; - - i2c1_default: i2c1-default { - pinconf { - pins = "i2c1_sclk", "i2c1_sdata"; - bias-pull-up; - }; - }; - - i2c2_default: i2c2-default { - pinconf { - pins = "i2c2_sclk", "i2c2_sdata"; - bias-pull-up; - }; - }; - - mmc0_default: mmc0_default { - pinmux { - groups = "sd0_d0_mfp", "sd0_d1_mfp", "sd0_d2_d3_mfp", - "sd0_cmd_mfp", "sd0_clk_mfp"; - function = "sd0"; - }; - }; - - mmc2_default: mmc2_default { - pinmux { - groups = "nand0_d0_ceb3_mfp"; - function = "sd2"; - }; - }; -}; - -/* uSD */ -&mmc0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_default>; - no-sdio; - no-mmc; - no-1-8-v; - cd-gpios = <&pinctrl 120 GPIO_ACTIVE_LOW>; - bus-width = <4>; - vmmc-supply = <&sd_vcc>; - vqmmc-supply = <&sd_vcc>; -}; - -/* eMMC */ -&mmc2 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_default>; - no-sdio; - no-sd; - non-removable; - bus-width = <8>; - vmmc-supply = <&vcc_3v1>; -}; - -&timer { - clocks = <&hosc>; -}; - -&uart5 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/actions/s900.dtsi b/sys/gnu/dts/arm64/actions/s900.dtsi deleted file mode 100644 index eb35cf78ab7..00000000000 --- a/sys/gnu/dts/arm64/actions/s900.dtsi +++ /dev/null @@ -1,333 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 Andreas Färber - */ - -#include -#include -#include -#include - -/ { - compatible = "actions,s900"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x0>; - enable-method = "psci"; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x1>; - enable-method = "psci"; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x2>; - enable-method = "psci"; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x3>; - enable-method = "psci"; - }; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - secmon@1f000000 { - reg = <0x0 0x1f000000 0x0 0x1000000>; - no-map; - }; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - arm-pmu { - compatible = "arm,cortex-a53-pmu"; - interrupts = , - , - , - ; - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - hosc: hosc { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - #clock-cells = <0>; - }; - - losc: losc { - compatible = "fixed-clock"; - clock-frequency = <32768>; - #clock-cells = <0>; - }; - - diff24M: diff24M { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - #clock-cells = <0>; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - gic: interrupt-controller@e00f1000 { - compatible = "arm,gic-400"; - reg = <0x0 0xe00f1000 0x0 0x1000>, - <0x0 0xe00f2000 0x0 0x2000>, - <0x0 0xe00f4000 0x0 0x2000>, - <0x0 0xe00f6000 0x0 0x2000>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <3>; - }; - - uart0: serial@e0120000 { - compatible = "actions,s900-uart", "actions,owl-uart"; - reg = <0x0 0xe0120000 0x0 0x2000>; - clocks = <&cmu CLK_UART0>; - interrupts = ; - status = "disabled"; - }; - - uart1: serial@e0122000 { - compatible = "actions,s900-uart", "actions,owl-uart"; - reg = <0x0 0xe0122000 0x0 0x2000>; - clocks = <&cmu CLK_UART1>; - interrupts = ; - status = "disabled"; - }; - - uart2: serial@e0124000 { - compatible = "actions,s900-uart", "actions,owl-uart"; - reg = <0x0 0xe0124000 0x0 0x2000>; - clocks = <&cmu CLK_UART2>; - interrupts = ; - status = "disabled"; - }; - - uart3: serial@e0126000 { - compatible = "actions,s900-uart", "actions,owl-uart"; - reg = <0x0 0xe0126000 0x0 0x2000>; - clocks = <&cmu CLK_UART3>; - interrupts = ; - status = "disabled"; - }; - - uart4: serial@e0128000 { - compatible = "actions,s900-uart", "actions,owl-uart"; - reg = <0x0 0xe0128000 0x0 0x2000>; - clocks = <&cmu CLK_UART4>; - interrupts = ; - status = "disabled"; - }; - - uart5: serial@e012a000 { - compatible = "actions,s900-uart", "actions,owl-uart"; - reg = <0x0 0xe012a000 0x0 0x2000>; - clocks = <&cmu CLK_UART5>; - interrupts = ; - status = "disabled"; - }; - - uart6: serial@e012c000 { - compatible = "actions,s900-uart", "actions,owl-uart"; - reg = <0x0 0xe012c000 0x0 0x2000>; - clocks = <&cmu CLK_UART6>; - interrupts = ; - status = "disabled"; - }; - - sps: power-controller@e012e000 { - compatible = "actions,s900-sps"; - reg = <0x0 0xe012e000 0x0 0x2000>; - #power-domain-cells = <1>; - }; - - cmu: clock-controller@e0160000 { - compatible = "actions,s900-cmu"; - reg = <0x0 0xe0160000 0x0 0x1000>; - clocks = <&hosc>, <&losc>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - i2c0: i2c@e0170000 { - compatible = "actions,s900-i2c"; - reg = <0 0xe0170000 0 0x1000>; - clocks = <&cmu CLK_I2C0>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c1: i2c@e0172000 { - compatible = "actions,s900-i2c"; - reg = <0 0xe0172000 0 0x1000>; - clocks = <&cmu CLK_I2C1>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@e0174000 { - compatible = "actions,s900-i2c"; - reg = <0 0xe0174000 0 0x1000>; - clocks = <&cmu CLK_I2C2>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c3: i2c@e0176000 { - compatible = "actions,s900-i2c"; - reg = <0 0xe0176000 0 0x1000>; - clocks = <&cmu CLK_I2C3>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c4: i2c@e0178000 { - compatible = "actions,s900-i2c"; - reg = <0 0xe0178000 0 0x1000>; - clocks = <&cmu CLK_I2C4>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c5: i2c@e017a000 { - compatible = "actions,s900-i2c"; - reg = <0 0xe017a000 0 0x1000>; - clocks = <&cmu CLK_I2C5>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - pinctrl: pinctrl@e01b0000 { - compatible = "actions,s900-pinctrl"; - reg = <0x0 0xe01b0000 0x0 0x1000>; - clocks = <&cmu CLK_GPIO>; - gpio-controller; - gpio-ranges = <&pinctrl 0 0 146>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = , - , - , - , - , - ; - }; - - timer: timer@e0228000 { - compatible = "actions,s900-timer"; - reg = <0x0 0xe0228000 0x0 0x8000>; - interrupts = ; - interrupt-names = "timer1"; - }; - - dma: dma-controller@e0260000 { - compatible = "actions,s900-dma"; - reg = <0x0 0xe0260000 0x0 0x1000>; - interrupts = , - , - , - ; - #dma-cells = <1>; - dma-channels = <12>; - dma-requests = <46>; - clocks = <&cmu CLK_DMAC>; - }; - - mmc0: mmc@e0330000 { - compatible = "actions,owl-mmc"; - reg = <0x0 0xe0330000 0x0 0x4000>; - interrupts = ; - clocks = <&cmu CLK_SD0>; - resets = <&cmu RESET_SD0>; - dmas = <&dma 2>; - dma-names = "mmc"; - status = "disabled"; - }; - - mmc1: mmc@e0334000 { - compatible = "actions,owl-mmc"; - reg = <0x0 0xe0334000 0x0 0x4000>; - interrupts = ; - clocks = <&cmu CLK_SD1>; - resets = <&cmu RESET_SD1>; - dmas = <&dma 3>; - dma-names = "mmc"; - status = "disabled"; - }; - - mmc2: mmc@e0338000 { - compatible = "actions,owl-mmc"; - reg = <0x0 0xe0338000 0x0 0x4000>; - interrupts = ; - clocks = <&cmu CLK_SD2>; - resets = <&cmu RESET_SD2>; - dmas = <&dma 4>; - dma-names = "mmc"; - status = "disabled"; - }; - - mmc3: mmc@e033c000 { - compatible = "actions,owl-mmc"; - reg = <0x0 0xe033c000 0x0 0x4000>; - interrupts = ; - clocks = <&cmu CLK_SD3>; - resets = <&cmu RESET_SD3>; - dmas = <&dma 46>; - dma-names = "mmc"; - status = "disabled"; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/al/alpine-v2-evp.dts b/sys/gnu/dts/arm64/al/alpine-v2-evp.dts deleted file mode 100644 index a079d7b3063..00000000000 --- a/sys/gnu/dts/arm64/al/alpine-v2-evp.dts +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Antoine Tenart - * - * This software is available to you under a choice of one of two - * licenses. You may choose to be licensed under the terms of the GNU - * General Public License (GPL) Version 2, available from the file - * COPYING in the main directory of this source tree, or the - * BSD license below: - * - * Redistribution and use in source and binary forms, with or - * without modification, are permitted provided that the following - * conditions are met: - * - * - Redistributions of source code must retain the above - * copyright notice, this list of conditions and the following - * disclaimer. - * - * - Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials - * provided with the distribution. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - */ - -#include "alpine-v2.dtsi" - -/ { - model = "Annapurna Labs Alpine v2 EVP"; - compatible = "al,alpine-v2-evp", "al,alpine-v2"; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&uart0 { status = "okay"; }; diff --git a/sys/gnu/dts/arm64/al/alpine-v2.dtsi b/sys/gnu/dts/arm64/al/alpine-v2.dtsi deleted file mode 100644 index d5e7e2bb4e6..00000000000 --- a/sys/gnu/dts/arm64/al/alpine-v2.dtsi +++ /dev/null @@ -1,236 +0,0 @@ -/* - * Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Antoine Tenart - * - * This software is available to you under a choice of one of two - * licenses. You may choose to be licensed under the terms of the GNU - * General Public License (GPL) Version 2, available from the file - * COPYING in the main directory of this source tree, or the - * BSD license below: - * - * Redistribution and use in source and binary forms, with or - * without modification, are permitted provided that the following - * conditions are met: - * - * - Redistributions of source code must retain the above - * copyright notice, this list of conditions and the following - * disclaimer. - * - * - Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials - * provided with the distribution. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - */ - -/dts-v1/; - -#include - -/ { - model = "Annapurna Labs Alpine v2"; - compatible = "al,alpine-v2"; - #address-cells = <2>; - #size-cells = <2>; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu@0 { - compatible = "arm,cortex-a57"; - device_type = "cpu"; - reg = <0x0 0x0>; - enable-method = "psci"; - }; - - cpu@1 { - compatible = "arm,cortex-a57"; - device_type = "cpu"; - reg = <0x0 0x1>; - enable-method = "psci"; - }; - - cpu@2 { - compatible = "arm,cortex-a57"; - device_type = "cpu"; - reg = <0x0 0x2>; - enable-method = "psci"; - }; - - cpu@3 { - compatible = "arm,cortex-a57"; - device_type = "cpu"; - reg = <0x0 0x3>; - enable-method = "psci"; - }; - }; - - psci { - compatible = "arm,psci-0.2", "arm,psci"; - method = "smc"; - cpu_suspend = <0x84000001>; - cpu_off = <0x84000002>; - cpu_on = <0x84000003>; - }; - - sbclk: sbclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <1000000>; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - - interrupt-parent = <&gic>; - ranges; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = , - , - , - ; - }; - - gic: gic@f0100000 { - compatible = "arm,gic-v3"; - reg = <0x0 0xf0200000 0x0 0x10000>, /* GIC Dist */ - <0x0 0xf0280000 0x0 0x200000>, /* GICR */ - <0x0 0xf0100000 0x0 0x2000>, /* GICC */ - <0x0 0xf0110000 0x0 0x2000>, /* GICV */ - <0x0 0xf0120000 0x0 0x2000>; /* GICH */ - interrupts = ; - interrupt-controller; - #interrupt-cells = <3>; - }; - - pci@fbc00000 { - compatible = "pci-host-ecam-generic"; - device_type = "pci"; - #size-cells = <2>; - #address-cells = <3>; - #interrupt-cells = <1>; - reg = <0x0 0xfbc00000 0x0 0x100000>; - interrupt-map-mask = <0xf800 0 0 7>; - /* add legacy interrupts for SATA only */ - interrupt-map = <0x4000 0 0 1 &gic 0 53 4>, - <0x4800 0 0 1 &gic 0 54 4>; - /* 32 bit non prefetchable memory space */ - ranges = <0x2000000 0x0 0xfe000000 0x0 0xfe000000 0x0 0x1000000>; - bus-range = <0x00 0x00>; - msi-parent = <&msix>; - }; - - msix: msix@fbe00000 { - compatible = "al,alpine-msix"; - reg = <0x0 0xfbe00000 0x0 0x100000>; - interrupt-controller; - msi-controller; - al,msi-base-spi = <160>; - al,msi-num-spis = <160>; - }; - - io-fabric { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0xfc000000 0x2000000>; - - uart0: serial@1883000 { - compatible = "ns16550a"; - device_type = "serial"; - reg = <0x1883000 0x1000>; - interrupts = ; - clock-frequency = <500000000>; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uart1: serial@1884000 { - compatible = "ns16550a"; - device_type = "serial"; - reg = <0x1884000 0x1000>; - interrupts = ; - clock-frequency = <500000000>; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uart2: serial@1885000 { - compatible = "ns16550a"; - device_type = "serial"; - reg = <0x1885000 0x1000>; - interrupts = ; - clock-frequency = <500000000>; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uart3: serial@1886000 { - compatible = "ns16550a"; - device_type = "serial"; - reg = <0x1886000 0x1000>; - interrupts = ; - clock-frequency = <500000000>; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - timer0: timer@1890000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x1890000 0x1000>; - interrupts = ; - clocks = <&sbclk>; - }; - - timer1: timer@1891000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x1891000 0x1000>; - interrupts = ; - clocks = <&sbclk>; - status = "disabled"; - }; - - timer2: timer@1892000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x1892000 0x1000>; - interrupts = ; - clocks = <&sbclk>; - status = "disabled"; - }; - - timer3: timer@1893000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x1893000 0x1000>; - interrupts = ; - clocks = <&sbclk>; - status = "disabled"; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/allwinner/axp803.dtsi b/sys/gnu/dts/arm64/allwinner/axp803.dtsi deleted file mode 100644 index 10e9186a76b..00000000000 --- a/sys/gnu/dts/arm64/allwinner/axp803.dtsi +++ /dev/null @@ -1,155 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright 2017 Icenowy Zheng - -/* - * AXP803 Integrated Power Management Chip - * http://files.pine64.org/doc/datasheet/pine64/AXP803_Datasheet_V1.0.pdf - */ - -&axp803 { - interrupt-controller; - #interrupt-cells = <1>; - - ac_power_supply: ac-power-supply { - compatible = "x-powers,axp803-ac-power-supply", - "x-powers,axp813-ac-power-supply"; - status = "disabled"; - }; - - axp_adc: adc { - compatible = "x-powers,axp803-adc", "x-powers,axp813-adc"; - #io-channel-cells = <1>; - }; - - axp_gpio: gpio { - compatible = "x-powers,axp803-gpio", "x-powers,axp813-gpio"; - gpio-controller; - #gpio-cells = <2>; - - gpio0_ldo: gpio0-ldo { - pins = "GPIO0"; - function = "ldo"; - }; - - gpio1_ldo: gpio1-ldo { - pins = "GPIO1"; - function = "ldo"; - }; - }; - - battery_power_supply: battery-power-supply { - compatible = "x-powers,axp803-battery-power-supply", - "x-powers,axp813-battery-power-supply"; - status = "disabled"; - }; - - regulators { - /* Default work frequency for buck regulators */ - x-powers,dcdc-freq = <3000>; - - reg_aldo1: aldo1 { - regulator-name = "aldo1"; - }; - - reg_aldo2: aldo2 { - regulator-name = "aldo2"; - }; - - reg_aldo3: aldo3 { - regulator-name = "aldo3"; - }; - - reg_dc1sw: dc1sw { - regulator-name = "dc1sw"; - }; - - reg_dcdc1: dcdc1 { - regulator-name = "dcdc1"; - }; - - reg_dcdc2: dcdc2 { - regulator-name = "dcdc2"; - }; - - reg_dcdc3: dcdc3 { - regulator-name = "dcdc3"; - }; - - reg_dcdc4: dcdc4 { - regulator-name = "dcdc4"; - }; - - reg_dcdc5: dcdc5 { - regulator-name = "dcdc5"; - }; - - reg_dcdc6: dcdc6 { - regulator-name = "dcdc6"; - }; - - reg_dldo1: dldo1 { - regulator-name = "dldo1"; - }; - - reg_dldo2: dldo2 { - regulator-name = "dldo2"; - }; - - reg_dldo3: dldo3 { - regulator-name = "dldo3"; - }; - - reg_dldo4: dldo4 { - regulator-name = "dldo4"; - }; - - reg_eldo1: eldo1 { - regulator-name = "eldo1"; - }; - - reg_eldo2: eldo2 { - regulator-name = "eldo2"; - }; - - reg_eldo3: eldo3 { - regulator-name = "eldo3"; - }; - - reg_fldo1: fldo1 { - regulator-name = "fldo1"; - }; - - reg_fldo2: fldo2 { - regulator-name = "fldo2"; - }; - - reg_ldo_io0: ldo-io0 { - regulator-name = "ldo-io0"; - status = "disabled"; - }; - - reg_ldo_io1: ldo-io1 { - regulator-name = "ldo-io1"; - status = "disabled"; - }; - - reg_rtc_ldo: rtc-ldo { - /* RTC_LDO is a fixed, always-on regulator */ - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "rtc-ldo"; - }; - - reg_drivevbus: drivevbus { - regulator-name = "drivevbus"; - status = "disabled"; - }; - }; - - usb_power_supply: usb-power-supply { - compatible = "x-powers,axp803-usb-power-supply", - "x-powers,axp813-usb-power-supply"; - status = "disabled"; - }; -}; diff --git a/sys/gnu/dts/arm64/allwinner/sun50i-a64-amarula-relic.dts b/sys/gnu/dts/arm64/allwinner/sun50i-a64-amarula-relic.dts deleted file mode 100644 index c7bd73f35ed..00000000000 --- a/sys/gnu/dts/arm64/allwinner/sun50i-a64-amarula-relic.dts +++ /dev/null @@ -1,320 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (C) 2018 Amarula Solutions B.V. -// Author: Jagan Teki - -/dts-v1/; - -#include "sun50i-a64.dtsi" -#include "sun50i-a64-cpu-opp.dtsi" - -#include - -/ { - model = "Amarula A64-Relic"; - compatible = "amarula,a64-relic", "allwinner,sun50i-a64"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - i2c { - compatible = "i2c-gpio"; - sda-gpios = <&pio 4 13 GPIO_ACTIVE_HIGH>; - scl-gpios = <&pio 4 12 GPIO_ACTIVE_HIGH>; - i2c-gpio,delay-us = <5>; - #address-cells = <1>; - #size-cells = <0>; - - ov5640: camera@3c { - compatible = "ovti,ov5640"; - reg = <0x3c>; - pinctrl-names = "default"; - pinctrl-0 = <&csi_mclk_pin>; - clocks = <&ccu CLK_CSI_MCLK>; - clock-names = "xclk"; - - AVDD-supply = <®_aldo1>; - DOVDD-supply = <®_dldo3>; - DVDD-supply = <®_eldo3>; - reset-gpios = <&pio 4 14 GPIO_ACTIVE_LOW>; /* CSI-RST-R: PE14 */ - powerdown-gpios = <&pio 4 15 GPIO_ACTIVE_HIGH>; /* CSI-STBY-R: PE15 */ - - port { - ov5640_ep: endpoint { - remote-endpoint = <&csi_ep>; - bus-width = <8>; - hsync-active = <1>; /* Active high */ - vsync-active = <0>; /* Active low */ - data-active = <1>; /* Active high */ - pclk-sample = <1>; /* Rising */ - }; - }; - }; - }; - - wifi_pwrseq: wifi-pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&rtc 1>; - clock-names = "ext_clock"; - reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* WL-PMU-EN: PL2 */ - }; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&cpu1 { - cpu-supply = <®_dcdc2>; -}; - -&cpu2 { - cpu-supply = <®_dcdc2>; -}; - -&cpu3 { - cpu-supply = <®_dcdc2>; -}; - -&csi { - status = "okay"; - - port { - csi_ep: endpoint { - remote-endpoint = <&ov5640_ep>; - bus-width = <8>; - hsync-active = <1>; /* Active high */ - vsync-active = <0>; /* Active low */ - data-active = <1>; /* Active high */ - pclk-sample = <1>; /* Rising */ - }; - }; -}; - -&ehci0 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - sensor@48 { - compatible = "st,stlm75"; - reg = <0x48>; - }; -}; - -&i2c0_pins { - bias-pull-up; -}; - -&i2c1 { - status = "okay"; - - touchscreen@5d { - compatible = "goodix,gt5663"; - reg = <0x5d>; - AVDD28-supply = <®_ldo_io0>; /* VCC-CTP: GPIO0-LDO */ - interrupt-parent = <&pio>; - interrupts = <7 4 IRQ_TYPE_EDGE_FALLING>; - irq-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* CTP-INT: PH4 */ - reset-gpios = <&pio 7 8 GPIO_ACTIVE_HIGH>; /* CTP-RST: PH8 */ - touchscreen-inverted-x; - touchscreen-inverted-y; - }; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - vmmc-supply = <®_dcdc1>; - /* - * Schematic shows both dldo4 and eldo1 connected for vcc-io-wifi, but - * dldo4 connection shows DNP(Do Not Populate) and eldo1 connected with - * 0Ohm register to vcc-io-wifi so eldo1 is used. - */ - vqmmc-supply = <®_eldo1>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - interrupt-parent = <&r_pio>; - interrupts = <0 3 IRQ_TYPE_LEVEL_LOW>; /* WL-WAKE-AP: PL3 */ - interrupt-names = "host-wake"; - }; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; - vmmc-supply = <®_dcdc1>; - bus-width = <8>; - non-removable; - cap-mmc-hw-reset; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&r_rsb { - status = "okay"; - - axp803: pmic@3a3 { - compatible = "x-powers,axp803"; - reg = <0x3a3>; - interrupt-parent = <&r_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - x-powers,drive-vbus-en; /* set N_VBUSEN as output pin */ - }; -}; - -#include "axp803.dtsi" - -®_aldo1 { - regulator-always-on; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-name = "avdd-csi"; -}; - -®_aldo2 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-pl"; -}; - -®_aldo3 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-pll-avcc"; -}; - -®_dcdc1 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-3v3"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1040000>; - regulator-max-microvolt = <1300000>; - regulator-name = "vdd-cpux"; -}; - -/* DCDC3 is polyphased with DCDC2 */ - -®_dcdc5 { - regulator-always-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vcc-dram"; -}; - -®_dcdc6 { - regulator-always-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-sys"; -}; - -®_dldo1 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-hdmi-dsi-sensor"; -}; - -®_dldo2 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-mipi"; -}; - -®_dldo3 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-name = "dovdd-csi"; -}; - -®_dldo4 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi-io"; -}; - -®_drivevbus { - regulator-name = "usb0-vbus"; - status = "okay"; -}; - -®_eldo1 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "cpvdd"; -}; - -®_eldo3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "dvdd-csi"; -}; - -®_fldo1 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-name = "vcc-1v2-hsic"; -}; - -/* - * The A64 chip cannot work without this regulator off, although - * it seems to be only driving the AR100 core. - * Maybe we don't still know well about CPUs domain. - */ -®_fldo2 { - regulator-always-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-cpus"; -}; - -®_ldo_io0 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-name = "vcc-ctp"; - status = "okay"; -}; - -®_rtc_ldo { - regulator-name = "vcc-rtc"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */ - usb0_vbus-supply = <®_drivevbus>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/allwinner/sun50i-a64-bananapi-m64.dts b/sys/gnu/dts/arm64/allwinner/sun50i-a64-bananapi-m64.dts deleted file mode 100644 index 883f217efb8..00000000000 --- a/sys/gnu/dts/arm64/allwinner/sun50i-a64-bananapi-m64.dts +++ /dev/null @@ -1,382 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (c) 2016 ARM Ltd. - -/dts-v1/; - -#include "sun50i-a64.dtsi" -#include "sun50i-a64-cpu-opp.dtsi" - -#include - -/ { - model = "BananaPi-M64"; - compatible = "sinovoip,bananapi-m64", "allwinner,sun50i-a64"; - - aliases { - ethernet0 = &emac; - serial0 = &uart0; - serial1 = &uart1; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - pwr-led { - label = "bananapi-m64:red:pwr"; - gpios = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */ - default-state = "on"; - }; - - green { - label = "bananapi-m64:green:user"; - gpios = <&pio 4 14 GPIO_ACTIVE_HIGH>; /* PE14 */ - }; - - blue { - label = "bananapi-m64:blue:user"; - gpios = <&pio 4 15 GPIO_ACTIVE_HIGH>; /* PE15 */ - }; - }; - - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ - clocks = <&rtc 1>; - clock-names = "ext_clock"; - }; -}; - -&codec { - status = "okay"; -}; - -&codec_analog { - cpvdd-supply = <®_eldo1>; - status = "okay"; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&cpu1 { - cpu-supply = <®_dcdc2>; -}; - -&cpu2 { - cpu-supply = <®_dcdc2>; -}; - -&cpu3 { - cpu-supply = <®_dcdc2>; -}; - -&dai { - status = "okay"; -}; - -&de { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&emac { - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - phy-mode = "rgmii"; - phy-handle = <&ext_rgmii_phy>; - phy-supply = <®_dc1sw>; - status = "okay"; -}; - -&hdmi { - hvcc-supply = <®_dldo1>; - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c1_pins { - bias-pull-up; -}; - -&mdio { - ext_rgmii_phy: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; - vmmc-supply = <®_dcdc1>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; - disable-wp; - bus-width = <4>; - status = "okay"; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - vmmc-supply = <®_dldo2>; - vqmmc-supply = <®_dldo4>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - interrupt-parent = <&r_pio>; - interrupts = <0 3 IRQ_TYPE_LEVEL_LOW>; /* PL3 */ - interrupt-names = "host-wake"; - }; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>, <&mmc2_ds_pin>; - vmmc-supply = <®_dcdc1>; - bus-width = <8>; - non-removable; - cap-mmc-hw-reset; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&r_rsb { - status = "okay"; - - axp803: pmic@3a3 { - compatible = "x-powers,axp803"; - reg = <0x3a3>; - interrupt-parent = <&r_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - x-powers,drive-vbus-en; /* set N_VBUSEN as output pin */ - }; -}; - -#include "axp803.dtsi" - -&ac_power_supply { - status = "okay"; -}; - -&battery_power_supply { - status = "okay"; -}; - -®_aldo1 { - /* - * This regulator also drives the PE pingroup GPIOs, - * which also controls two LEDs. - */ - regulator-always-on; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-name = "afvcc-csi"; -}; - -®_aldo2 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-pl"; -}; - -®_aldo3 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-pll-avcc"; -}; - -®_dc1sw { - /* - * This regulator also indirectly drives the PD pingroup GPIOs, - * which also controls the power LED. - */ - regulator-always-on; - regulator-name = "vcc-phy"; -}; - -®_dcdc1 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-3v3"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1040000>; - regulator-max-microvolt = <1300000>; - regulator-name = "vdd-cpux"; -}; - -/* DCDC3 is polyphased with DCDC2 */ - -®_dcdc5 { - regulator-always-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vcc-dram"; -}; - -®_dcdc6 { - regulator-always-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-sys"; -}; - -®_dldo1 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-hdmi-dsi"; -}; - -®_dldo2 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi"; -}; - -®_dldo4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi-io"; -}; - -®_drivevbus { - regulator-name = "usb0-vbus"; - status = "okay"; -}; - -®_eldo1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "cpvdd"; -}; - -®_fldo1 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-name = "vcc-1v2-hsic"; -}; - -/* - * The A64 chip cannot work without this regulator off, although - * it seems to be only driving the AR100 core. - * Maybe we don't still know well about CPUs domain. - */ -®_fldo2 { - regulator-always-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-cpus"; -}; - -®_rtc_ldo { - regulator-name = "vcc-rtc"; -}; - -&simplefb_hdmi { - vcc-hdmi-supply = <®_dldo1>; -}; - -&sound { - status = "okay"; - simple-audio-card,widgets = "Headphone", "Headphone Jack", - "Microphone", "Microphone Jack", - "Microphone", "Onboard Microphone"; - simple-audio-card,routing = - "Left DAC", "AIF1 Slot 0 Left", - "Right DAC", "AIF1 Slot 0 Right", - "AIF1 Slot 0 Left ADC", "Left ADC", - "AIF1 Slot 0 Right ADC", "Right ADC", - "Headphone Jack", "HP", - "MIC2", "Microphone Jack", - "Onboard Microphone", "MBIAS", - "MIC1", "Onboard Microphone"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; - uart-has-rtscts; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - clocks = <&rtc 1>; - clock-names = "lpo"; - vbat-supply = <®_dldo2>; - vddio-supply = <®_dldo4>; - device-wakeup-gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ - host-wakeup-gpios = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* PL5 */ - shutdown-gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */ - }; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usb_power_supply { - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */ - usb0_vbus_power-supply = <&usb_power_supply>; - usb0_vbus-supply = <®_drivevbus>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/allwinner/sun50i-a64-cpu-opp.dtsi b/sys/gnu/dts/arm64/allwinner/sun50i-a64-cpu-opp.dtsi deleted file mode 100644 index 578c37490d9..00000000000 --- a/sys/gnu/dts/arm64/allwinner/sun50i-a64-cpu-opp.dtsi +++ /dev/null @@ -1,75 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2020 Vasily khoruzhick - */ - -/ { - cpu0_opp_table: opp_table0 { - compatible = "operating-points-v2"; - opp-shared; - - opp-648000000 { - opp-hz = /bits/ 64 <648000000>; - opp-microvolt = <1040000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - }; - - opp-816000000 { - opp-hz = /bits/ 64 <816000000>; - opp-microvolt = <1100000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - }; - - opp-912000000 { - opp-hz = /bits/ 64 <912000000>; - opp-microvolt = <1120000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - }; - - opp-960000000 { - opp-hz = /bits/ 64 <960000000>; - opp-microvolt = <1160000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - }; - - opp-1008000000 { - opp-hz = /bits/ 64 <1008000000>; - opp-microvolt = <1200000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - }; - - opp-1056000000 { - opp-hz = /bits/ 64 <1056000000>; - opp-microvolt = <1240000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - }; - - opp-1104000000 { - opp-hz = /bits/ 64 <1104000000>; - opp-microvolt = <1260000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - }; - - opp-1152000000 { - opp-hz = /bits/ 64 <1152000000>; - opp-microvolt = <1300000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - }; - }; -}; - -&cpu0 { - operating-points-v2 = <&cpu0_opp_table>; -}; - -&cpu1 { - operating-points-v2 = <&cpu0_opp_table>; -}; - -&cpu2 { - operating-points-v2 = <&cpu0_opp_table>; -}; - -&cpu3 { - operating-points-v2 = <&cpu0_opp_table>; -}; diff --git a/sys/gnu/dts/arm64/allwinner/sun50i-a64-nanopi-a64.dts b/sys/gnu/dts/arm64/allwinner/sun50i-a64-nanopi-a64.dts deleted file mode 100644 index e58db8a6cab..00000000000 --- a/sys/gnu/dts/arm64/allwinner/sun50i-a64-nanopi-a64.dts +++ /dev/null @@ -1,263 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (C) 2017 Jagan Teki - -/dts-v1/; - -#include "sun50i-a64.dtsi" -#include "sun50i-a64-cpu-opp.dtsi" - -#include - -/ { - model = "FriendlyARM NanoPi A64"; - compatible = "friendlyarm,nanopi-a64", "allwinner,sun50i-a64"; - - aliases { - ethernet0 = &emac; - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - blue { - label = "nanopi-a64:blue:status"; - gpios = <&pio 3 24 GPIO_ACTIVE_LOW>; /* PD24 */ - }; - }; - - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&rtc 1>; - clock-names = "ext_clock"; - reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ - }; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&cpu1 { - cpu-supply = <®_dcdc2>; -}; - -&cpu2 { - cpu-supply = <®_dcdc2>; -}; - -&cpu3 { - cpu-supply = <®_dcdc2>; -}; - -&de { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&emac { - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - phy-mode = "rgmii"; - phy-handle = <&ext_rgmii_phy>; - phy-supply = <®_dcdc1>; - status = "okay"; -}; - -&hdmi { - hvcc-supply = <®_dldo1>; - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -/* i2c1 connected with gpio headers like pine64, bananapi */ -&i2c1_pins { - bias-pull-up; -}; - -&mdio { - ext_rgmii_phy: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <7>; - }; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; - vmmc-supply = <®_dcdc1>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; - disable-wp; - bus-width = <4>; - status = "okay"; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - vmmc-supply = <®_dcdc1>; - vqmmc-supply = <®_dldo4>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; - - rtl8189etv: wifi@1 { - reg = <1>; - interrupt-parent = <&r_pio>; - interrupts = <0 3 IRQ_TYPE_LEVEL_LOW>; /* PL3 */ - interrupt-names = "host-wake"; - }; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&r_rsb { - status = "okay"; - - axp803: pmic@3a3 { - compatible = "x-powers,axp803"; - reg = <0x3a3>; - interrupt-parent = <&r_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -#include "axp803.dtsi" - -&ac_power_supply { - status = "okay"; -}; - -®_aldo2 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-pl"; -}; - -®_aldo3 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-pll-avcc"; -}; - -®_dcdc1 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-3v3"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1040000>; - regulator-max-microvolt = <1300000>; - regulator-name = "vdd-cpux"; -}; - -/* DCDC3 is polyphased with DCDC2 */ - -®_dcdc5 { - regulator-always-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vcc-dram"; -}; - -®_dcdc6 { - regulator-always-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-sys"; -}; - -®_dldo1 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-hdmi-dsi"; -}; - -®_dldo4 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-pg-wifi-io"; -}; - -®_eldo1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "cpvdd"; -}; - -®_fldo1 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-name = "vcc-1v2-hsic"; -}; - -/* - * The A64 chip cannot work without this regulator off, although - * it seems to be only driving the AR100 core. - * Maybe we don't still know well about CPUs domain. - */ -®_fldo2 { - regulator-always-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-cpus"; -}; - -®_rtc_ldo { - regulator-name = "vcc-rtc"; -}; - -&simplefb_hdmi { - vcc-hdmi-supply = <®_dldo1>; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/allwinner/sun50i-a64-oceanic-5205-5inmfd.dts b/sys/gnu/dts/arm64/allwinner/sun50i-a64-oceanic-5205-5inmfd.dts deleted file mode 100644 index 577f9e1d08a..00000000000 --- a/sys/gnu/dts/arm64/allwinner/sun50i-a64-oceanic-5205-5inmfd.dts +++ /dev/null @@ -1,89 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (C) 2019 Oceanic Systems (UK) Ltd. -// Copyright (C) 2019 Amarula Solutions B.V. -// Author: Jagan Teki - -/dts-v1/; - -#include "sun50i-a64-sopine.dtsi" - -/ { - model = "Oceanic 5205 5inMFD"; - compatible = "oceanic,5205-5inmfd", "allwinner,sun50i-a64"; - - aliases { - ethernet0 = &emac; - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&ehci0 { - status = "okay"; -}; - -&emac { - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - phy-mode = "rgmii"; - phy-handle = <&ext_rgmii_phy>; - phy-supply = <®_dc1sw>; - allwinner,tx-delay-ps = <600>; - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - touchscreen@5d { - compatible = "goodix,gt911"; - reg = <0x5d>; - AVDD28-supply = <®_ldo_io0>; /* VDD_CTP: GPIO0-LDO */ - interrupt-parent = <&pio>; - interrupts = <7 4 IRQ_TYPE_EDGE_FALLING>; - irq-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* CTP-INT: PH4 */ - reset-gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>; /* CTP-RST: PH11 */ - touchscreen-inverted-x; - touchscreen-inverted-y; - }; -}; - -&mdio { - ext_rgmii_phy: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; -}; - -&ohci0 { - status = "okay"; -}; - -®_dc1sw { - regulator-name = "vcc-phy"; -}; - -®_ldo_io0 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-name = "vdd-ctp"; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "host"; - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/allwinner/sun50i-a64-olinuxino-emmc.dts b/sys/gnu/dts/arm64/allwinner/sun50i-a64-olinuxino-emmc.dts deleted file mode 100644 index efb20846de4..00000000000 --- a/sys/gnu/dts/arm64/allwinner/sun50i-a64-olinuxino-emmc.dts +++ /dev/null @@ -1,25 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (C) 2018 Martin Ayotte -// Copyright (C) 2019 Sunil Mohan Adapa - -#include "sun50i-a64-olinuxino.dts" - -/ { - model = "Olimex A64-Olinuxino-eMMC"; - compatible = "olimex,a64-olinuxino-emmc", "allwinner,sun50i-a64"; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; - vmmc-supply = <®_dcdc1>; - vqmmc-supply = <®_eldo1>; - bus-width = <8>; - non-removable; - cap-mmc-hw-reset; - status = "okay"; -}; - -&pio { - vcc-pc-supply = <®_eldo1>; -}; diff --git a/sys/gnu/dts/arm64/allwinner/sun50i-a64-olinuxino.dts b/sys/gnu/dts/arm64/allwinner/sun50i-a64-olinuxino.dts deleted file mode 100644 index 6dfafa1c879..00000000000 --- a/sys/gnu/dts/arm64/allwinner/sun50i-a64-olinuxino.dts +++ /dev/null @@ -1,321 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (C) 2017 Jagan Teki - -/dts-v1/; - -#include "sun50i-a64.dtsi" -#include "sun50i-a64-cpu-opp.dtsi" - -#include - -/ { - model = "Olimex A64-Olinuxino"; - compatible = "olimex,a64-olinuxino", "allwinner,sun50i-a64"; - - aliases { - ethernet0 = &emac; - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - reg_usb1_vbus: usb1-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb1-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - enable-active-high; - gpio = <&pio 6 9 GPIO_ACTIVE_HIGH>; /* PG9 */ - status = "okay"; - }; - - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ - }; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&cpu1 { - cpu-supply = <®_dcdc2>; -}; - -&cpu2 { - cpu-supply = <®_dcdc2>; -}; - -&cpu3 { - cpu-supply = <®_dcdc2>; -}; - -&de { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&emac { - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - phy-mode = "rgmii"; - phy-handle = <&ext_rgmii_phy>; - phy-supply = <®_dcdc1>; - allwinner,tx-delay-ps = <600>; - status = "okay"; -}; - -&hdmi { - hvcc-supply = <®_dldo1>; - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&mdio { - ext_rgmii_phy: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; - vmmc-supply = <®_dcdc1>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; - disable-wp; - bus-width = <4>; - status = "okay"; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - vmmc-supply = <®_dcdc1>; - vqmmc-supply = <®_dldo4>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; - - rtl8723bs: wifi@1 { - reg = <1>; - interrupt-parent = <&r_pio>; - interrupts = <0 3 IRQ_TYPE_LEVEL_LOW>; /* PL3 */ - interrupt-names = "host-wake"; - }; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&pio { - vcc-pc-supply = <®_dcdc1>; - vcc-pd-supply = <®_dcdc1>; - vcc-pe-supply = <®_aldo1>; - vcc-pg-supply = <®_dldo4>; -}; - -&r_pio { - /* - * FIXME: We can't add that supply for now since it would - * create a circular dependency between pinctrl, the regulator - * and the RSB Bus. - * - * vcc-pl-supply = <®_aldo2>; - */ -}; - -&r_rsb { - status = "okay"; - - axp803: pmic@3a3 { - compatible = "x-powers,axp803"; - reg = <0x3a3>; - interrupt-parent = <&r_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - x-powers,drive-vbus-en; /* set N_VBUSEN as output pin */ - }; -}; - -#include "axp803.dtsi" - -&ac_power_supply { - status = "okay"; -}; - -&battery_power_supply { - status = "okay"; -}; - -®_aldo1 { - regulator-always-on; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-name = "vcc-pe"; -}; - -®_aldo2 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-pl"; -}; - -®_aldo3 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-pll-avcc"; -}; - -®_dcdc1 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-3v3"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1040000>; - regulator-max-microvolt = <1300000>; - regulator-name = "vdd-cpux"; -}; - -/* DCDC3 is polyphased with DCDC2 */ - -/* - * The board uses DDR3L DRAM chips. 1.36V is the closest to the nominal - * 1.35V that the PMIC can drive. - */ -®_dcdc5 { - regulator-always-on; - regulator-min-microvolt = <1360000>; - regulator-max-microvolt = <1360000>; - regulator-name = "vcc-ddr3"; -}; - -®_dcdc6 { - regulator-always-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-sys"; -}; - -®_dldo1 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-hdmi"; -}; - -®_dldo2 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-mipi"; -}; - -®_dldo3 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-name = "vcc-avdd-csi"; -}; - -®_dldo4 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi-io"; -}; - -®_drivevbus { - regulator-name = "usb0-vbus"; - status = "okay"; -}; - -®_eldo1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "cpvdd"; -}; - -®_eldo2 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc-dvdd-csi"; -}; - -®_fldo1 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-name = "vcc-1v2-hsic"; -}; - -/* - * The A64 chip cannot work without this regulator off, although - * it seems to be only driving the AR100 core. - * Maybe we don't still know well about CPUs domain. - */ -®_fldo2 { - regulator-always-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-cpus"; -}; - -®_rtc_ldo { - regulator-name = "vcc-rtc"; -}; - -&simplefb_hdmi { - vcc-hdmi-supply = <®_dldo1>; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - status = "okay"; - usb0_id_det-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */ - usb0_vbus-supply = <®_drivevbus>; - usb1_vbus-supply = <®_usb1_vbus>; -}; diff --git a/sys/gnu/dts/arm64/allwinner/sun50i-a64-orangepi-win.dts b/sys/gnu/dts/arm64/allwinner/sun50i-a64-orangepi-win.dts deleted file mode 100644 index fde9c7a99b1..00000000000 --- a/sys/gnu/dts/arm64/allwinner/sun50i-a64-orangepi-win.dts +++ /dev/null @@ -1,413 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (C) 2017 Jagan Teki -// Copyright (C) 2017-2018 Samuel Holland - -/dts-v1/; - -#include "sun50i-a64.dtsi" -#include "sun50i-a64-cpu-opp.dtsi" - -#include - -/ { - model = "OrangePi Win/Win Plus"; - compatible = "xunlong,orangepi-win", "allwinner,sun50i-a64"; - - aliases { - ethernet0 = &emac; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - serial4 = &uart4; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - status { - label = "orangepi:green:status"; - gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>; /* PH11 */ - }; - }; - - reg_gmac_3v3: gmac-3v3 { - compatible = "regulator-fixed"; - regulator-name = "gmac-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - enable-active-high; - gpio = <&pio 3 14 GPIO_ACTIVE_HIGH>; /* PD14 */ - status = "okay"; - }; - - reg_usb1_vbus: usb1-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb1-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - enable-active-high; - gpio = <&pio 3 7 GPIO_ACTIVE_HIGH>; /* PD7 */ - status = "okay"; - }; - - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&r_pio 0 8 GPIO_ACTIVE_LOW>; /* PL8 */ - clocks = <&rtc 1>; - clock-names = "ext_clock"; - }; -}; - -&codec { - status = "okay"; -}; - -&codec_analog { - cpvdd-supply = <®_eldo1>; - status = "okay"; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&cpu1 { - cpu-supply = <®_dcdc2>; -}; - -&cpu2 { - cpu-supply = <®_dcdc2>; -}; - -&cpu3 { - cpu-supply = <®_dcdc2>; -}; - -&dai { - status = "okay"; -}; - -&de { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&emac { - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - phy-mode = "rgmii"; - phy-handle = <&ext_rgmii_phy>; - phy-supply = <®_gmac_3v3>; - status = "okay"; -}; - -&hdmi { - hvcc-supply = <®_dldo1>; - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&mdio { - ext_rgmii_phy: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; - vmmc-supply = <®_dcdc1>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ - disable-wp; - bus-width = <4>; - status = "okay"; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - vmmc-supply = <®_dldo2>; - vqmmc-supply = <®_dldo4>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - interrupt-parent = <&r_pio>; - interrupts = <0 7 IRQ_TYPE_LEVEL_LOW>; /* PL7 */ - interrupt-names = "host-wake"; - }; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&r_ir { - status = "okay"; -}; - -&r_rsb { - status = "okay"; - - axp803: pmic@3a3 { - compatible = "x-powers,axp803"; - reg = <0x3a3>; - interrupt-parent = <&r_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - x-powers,drive-vbus-en; /* set N_VBUSEN as output pin */ - }; -}; - -#include "axp803.dtsi" - -&ac_power_supply { - status = "okay"; -}; - -&battery_power_supply { - status = "okay"; -}; - -®_aldo1 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-name = "afvcc-csi"; -}; - -®_aldo2 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-pl"; -}; - -®_aldo3 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-pll-avcc"; -}; - -®_dcdc1 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-3v3"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1040000>; - regulator-max-microvolt = <1300000>; - regulator-name = "vdd-cpux"; -}; - -/* DCDC3 is polyphased with DCDC2 */ - -®_dcdc5 { - regulator-always-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vcc-dram"; -}; - -®_dcdc6 { - regulator-always-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-sys"; -}; - -®_dldo1 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-hdmi-dsi"; -}; - -®_dldo2 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi"; -}; - -®_dldo3 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "avdd-csi"; -}; - -®_dldo4 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi-io"; -}; - -®_drivevbus { - regulator-name = "usb0-vbus"; - status = "okay"; -}; - -®_eldo1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "cpvdd"; -}; - -®_eldo3 { - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1800000>; - regulator-name = "dvdd-csi"; -}; - -®_fldo1 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-name = "vcc-1v2-hsic"; -}; - -/* - * The A64 chip cannot work without this regulator off, although - * it seems to be only driving the AR100 core. - * Maybe we don't still know well about CPUs domain. - */ -®_fldo2 { - regulator-always-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-cpus"; -}; - -®_rtc_ldo { - regulator-name = "vcc-rtc"; -}; - -&simplefb_hdmi { - vcc-hdmi-supply = <®_dldo1>; -}; - -&sound { - status = "okay"; - simple-audio-card,widgets = "Headphone", "Headphone Jack", - "Microphone", "Microphone Jack", - "Microphone", "Onboard Microphone"; - simple-audio-card,routing = - "Left DAC", "AIF1 Slot 0 Left", - "Right DAC", "AIF1 Slot 0 Right", - "AIF1 Slot 0 Left ADC", "Left ADC", - "AIF1 Slot 0 Right ADC", "Right ADC", - "Headphone Jack", "HP", - "MIC2", "Microphone Jack", - "Onboard Microphone", "MBIAS", - "MIC1", "Onboard Microphone"; -}; - -&spi0 { - status = "okay"; - - spi-flash@0 { - compatible = "mxicy,mx25l1606e", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <80000000>; - m25p,fast-read; - status = "okay"; - }; -}; - -/* On debug connector */ -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -/* Bluetooth */ -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; - uart-has-rtscts; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - max-speed = <1500000>; - clocks = <&rtc 1>; - clock-names = "lpo"; - vbat-supply = <®_dldo2>; - vddio-supply = <®_dldo4>; - device-wakeup-gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ - host-wakeup-gpios = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* PL5 */ - shutdown-gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */ - }; -}; - -/* On Pi-2 connector, RTS/CTS optional */ -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; - status = "disabled"; -}; - -/* On Pi-2 connector, RTS/CTS optional */ -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; - status = "disabled"; -}; - -/* On Pi-2 connector (labeled for SPI1), RTS/CTS optional */ -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&uart4_pins>; - status = "disabled"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */ - usb0_vbus-supply = <®_drivevbus>; - usb1_vbus-supply = <®_usb1_vbus>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/allwinner/sun50i-a64-pine64-lts.dts b/sys/gnu/dts/arm64/allwinner/sun50i-a64-pine64-lts.dts deleted file mode 100644 index 302e24be0a3..00000000000 --- a/sys/gnu/dts/arm64/allwinner/sun50i-a64-pine64-lts.dts +++ /dev/null @@ -1,10 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (c) 2018 ARM Ltd. - -#include "sun50i-a64-sopine-baseboard.dts" - -/ { - model = "Pine64 LTS"; - compatible = "pine64,pine64-lts", "allwinner,sun50i-r18", - "allwinner,sun50i-a64"; -}; diff --git a/sys/gnu/dts/arm64/allwinner/sun50i-a64-pine64-plus.dts b/sys/gnu/dts/arm64/allwinner/sun50i-a64-pine64-plus.dts deleted file mode 100644 index b26181cf909..00000000000 --- a/sys/gnu/dts/arm64/allwinner/sun50i-a64-pine64-plus.dts +++ /dev/null @@ -1,35 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (c) 2016 ARM Ltd. - -#include "sun50i-a64-pine64.dts" - -/ { - model = "Pine64+"; - compatible = "pine64,pine64-plus", "allwinner,sun50i-a64"; - - /* TODO: Camera, touchscreen, etc. */ -}; - -&emac { - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - phy-mode = "rgmii"; - phy-handle = <&ext_rgmii_phy>; - status = "okay"; -}; - -&mdio { - ext_rgmii_phy: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; -}; - -®_dc1sw { - /* - * Ethernet PHY needs 30ms to properly power up and some more - * to initialize. 100ms should be plenty of time to finish - * whole process. - */ - regulator-enable-ramp-delay = <100000>; -}; diff --git a/sys/gnu/dts/arm64/allwinner/sun50i-a64-pine64.dts b/sys/gnu/dts/arm64/allwinner/sun50i-a64-pine64.dts deleted file mode 100644 index 2165f238af1..00000000000 --- a/sys/gnu/dts/arm64/allwinner/sun50i-a64-pine64.dts +++ /dev/null @@ -1,320 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (c) 2016 ARM Ltd. - -/dts-v1/; - -#include "sun50i-a64.dtsi" -#include "sun50i-a64-cpu-opp.dtsi" - -#include - -/ { - model = "Pine64"; - compatible = "pine64,pine64", "allwinner,sun50i-a64"; - - aliases { - ethernet0 = &emac; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - serial4 = &uart4; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; -}; - -&codec { - status = "okay"; -}; - -&codec_analog { - cpvdd-supply = <®_eldo1>; - status = "okay"; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&cpu1 { - cpu-supply = <®_dcdc2>; -}; - -&cpu2 { - cpu-supply = <®_dcdc2>; -}; - -&cpu3 { - cpu-supply = <®_dcdc2>; -}; - -&dai { - status = "okay"; -}; - -&de { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&emac { - pinctrl-names = "default"; - pinctrl-0 = <&rmii_pins>; - phy-mode = "rmii"; - phy-handle = <&ext_rmii_phy1>; - phy-supply = <®_dc1sw>; - status = "okay"; - -}; - -&hdmi { - hvcc-supply = <®_dldo1>; - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c1_pins { - bias-pull-up; -}; - -&mdio { - ext_rmii_phy1: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; - vmmc-supply = <®_dcdc1>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; - disable-wp; - bus-width = <4>; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&r_rsb { - status = "okay"; - - axp803: pmic@3a3 { - compatible = "x-powers,axp803"; - reg = <0x3a3>; - interrupt-parent = <&r_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -#include "axp803.dtsi" - -&ac_power_supply { - status = "okay"; -}; - -&battery_power_supply { - status = "okay"; -}; - -®_aldo2 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-pl"; -}; - -®_aldo3 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-pll-avcc"; -}; - -®_dc1sw { - regulator-name = "vcc-phy"; -}; - -®_dcdc1 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-3v3"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1040000>; - regulator-max-microvolt = <1300000>; - regulator-name = "vdd-cpux"; -}; - -/* DCDC3 is polyphased with DCDC2 */ - -/* - * The DRAM chips used by Pine64 boards are DDR3L-compatible, so they can - * work at 1.35V with less power consumption. - * As AXP803 DCDC5 cannot reach 1.35V accurately, use 1.36V instead. - */ -®_dcdc5 { - regulator-always-on; - regulator-min-microvolt = <1360000>; - regulator-max-microvolt = <1360000>; - regulator-name = "vcc-dram"; -}; - -®_dcdc6 { - regulator-always-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-sys"; -}; - -®_dldo1 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-hdmi"; -}; - -®_dldo2 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-mipi"; -}; - -®_dldo4 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi"; -}; - -®_eldo1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "cpvdd"; -}; - -®_fldo1 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-name = "vcc-1v2-hsic"; -}; - -/* - * The A64 chip cannot work without this regulator off, although - * it seems to be only driving the AR100 core. - * Maybe we don't still know well about CPUs domain. - */ -®_fldo2 { - regulator-always-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-cpus"; -}; - -®_rtc_ldo { - regulator-name = "vcc-rtc"; -}; - -&simplefb_hdmi { - vcc-hdmi-supply = <®_dldo1>; -}; - -&sound { - simple-audio-card,aux-devs = <&codec_analog>; - simple-audio-card,widgets = "Microphone", "Microphone Jack", - "Headphone", "Headphone Jack"; - simple-audio-card,routing = - "Left DAC", "AIF1 Slot 0 Left", - "Right DAC", "AIF1 Slot 0 Right", - "Headphone Jack", "HP", - "AIF1 Slot 0 Left ADC", "Left ADC", - "AIF1 Slot 0 Right ADC", "Right ADC", - "MIC2", "Microphone Jack"; - status = "okay"; -}; - -/* On Euler connector */ -&spdif { - status = "disabled"; -}; - -/* On Exp and Euler connectors */ -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -/* On Wifi/BT connector, with RTS/CTS */ -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; - status = "disabled"; -}; - -/* On Pi-2 connector */ -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; - status = "disabled"; -}; - -/* On Euler connector */ -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; - status = "disabled"; -}; - -/* On Euler connector, RTS/CTS optional */ -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&uart4_pins>; - status = "disabled"; -}; - -&usb_otg { - dr_mode = "host"; - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/allwinner/sun50i-a64-pinebook.dts b/sys/gnu/dts/arm64/allwinner/sun50i-a64-pinebook.dts deleted file mode 100644 index 3d894b20890..00000000000 --- a/sys/gnu/dts/arm64/allwinner/sun50i-a64-pinebook.dts +++ /dev/null @@ -1,367 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (C) 2017 Icenowy Zheng -// Copyright (C) 2018 Vasily Khoruzhick - -/dts-v1/; - -#include "sun50i-a64.dtsi" -#include "sun50i-a64-cpu-opp.dtsi" - -#include -#include -#include -#include - -/ { - model = "Pinebook"; - compatible = "pine64,pinebook", "allwinner,sun50i-a64"; - - aliases { - serial0 = &uart0; - ethernet0 = &rtl8723cs; - }; - - vdd_bl: regulator@0 { - compatible = "regulator-fixed"; - regulator-name = "bl-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */ - enable-active-high; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 0 50000 0>; - brightness-levels = <0 5 10 15 20 30 40 55 70 85 100>; - default-brightness-level = <2>; - enable-gpios = <&pio 3 23 GPIO_ACTIVE_HIGH>; /* PD23 */ - power-supply = <&vdd_bl>; - }; - - chosen { - stdout-path = "serial0:115200n8"; - - framebuffer-lcd { - panel-supply = <®_dc1sw>; - dvdd25-supply = <®_dldo2>; - dvdd12-supply = <®_fldo1>; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - - lid_switch { - label = "Lid Switch"; - gpios = <&r_pio 0 12 GPIO_ACTIVE_LOW>; /* PL12 */ - linux,input-type = ; - linux,code = ; - linux,can-disable; - wakeup-source; - wakeup-event-action = ; - }; - }; - - reg_vcc3v3: vcc3v3 { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ - }; - - speaker_amp: audio-amplifier { - compatible = "simple-audio-amplifier"; - /* - * TODO This is actually a fixed regulator controlled by - * the GPIO line on the PMIC. This should be corrected - * once GPIO support is added for this PMIC. - */ - VCC-supply = <®_ldo_io0>; - enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */ - sound-name-prefix = "Speaker Amp"; - }; - -}; - -&codec { - status = "okay"; -}; - -&codec_analog { - cpvdd-supply = <®_eldo1>; - status = "okay"; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&cpu1 { - cpu-supply = <®_dcdc2>; -}; - -&cpu2 { - cpu-supply = <®_dcdc2>; -}; - -&cpu3 { - cpu-supply = <®_dcdc2>; -}; - -&dai { - status = "okay"; -}; - -&ehci0 { - phys = <&usbphy 0>; - phy-names = "usb"; - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; - vmmc-supply = <®_dcdc1>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; - disable-wp; - bus-width = <4>; - status = "okay"; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - vmmc-supply = <®_dldo4>; - vqmmc-supply = <®_eldo1>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; - - rtl8723cs: wifi@1 { - reg = <1>; - }; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>, <&mmc2_ds_pin>; - vmmc-supply = <®_dcdc1>; - vqmmc-supply = <®_eldo1>; - bus-width = <8>; - non-removable; - cap-mmc-hw-reset; - mmc-hs200-1_8v; - status = "okay"; -}; - -&ohci0 { - phys = <&usbphy 0>; - phy-names = "usb"; - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&pwm { - status = "okay"; -}; - -&r_rsb { - status = "okay"; - - axp803: pmic@3a3 { - compatible = "x-powers,axp803"; - reg = <0x3a3>; - interrupt-parent = <&r_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -/* The ANX6345 eDP-bridge is on r_i2c */ -&r_i2c { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&r_i2c_pl89_pins>; - status = "okay"; -}; - -#include "axp803.dtsi" - -&ac_power_supply { - status = "okay"; -}; - -&battery_power_supply { - status = "okay"; -}; - -®_aldo1 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-name = "vcc-csi"; -}; - -®_aldo2 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-pl"; -}; - -®_aldo3 { - regulator-always-on; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-pll-avcc"; -}; - -®_dc1sw { - regulator-name = "vcc-lcd"; -}; - -®_dcdc1 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-3v3"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1300000>; - regulator-name = "vdd-cpux"; -}; - -/* DCDC3 is polyphased with DCDC2 */ - -®_dcdc5 { - regulator-always-on; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-name = "vcc-dram"; -}; - -®_dcdc6 { - regulator-always-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-sys"; -}; - -®_dldo1 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-hdmi"; -}; - -®_dldo2 { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-name = "vcc-edp"; -}; - -®_dldo3 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "avdd-csi"; -}; - -®_dldo4 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi"; -}; - -®_eldo1 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "cpvdd"; -}; - -®_eldo3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vdd-1v8-csi"; -}; - -®_fldo1 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-name = "vcc-1v2-hsic"; -}; - -®_fldo2 { - regulator-always-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-cpus"; -}; - -®_ldo_io0 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-usb"; - status = "okay"; -}; - -®_rtc_ldo { - regulator-name = "vcc-rtc"; -}; - -&simplefb_hdmi { - vcc-hdmi-supply = <®_dldo1>; -}; - -&sound { - status = "okay"; - simple-audio-card,aux-devs = <&codec_analog>, <&speaker_amp>; - simple-audio-card,widgets = "Microphone", "Internal Microphone Left", - "Microphone", "Internal Microphone Right", - "Headphone", "Headphone Jack", - "Speaker", "Internal Speaker"; - simple-audio-card,routing = - "Left DAC", "AIF1 Slot 0 Left", - "Right DAC", "AIF1 Slot 0 Right", - "Speaker Amp INL", "LINEOUT", - "Speaker Amp INR", "LINEOUT", - "Internal Speaker", "Speaker Amp OUTL", - "Internal Speaker", "Speaker Amp OUTR", - "Headphone Jack", "HP", - "AIF1 Slot 0 Left ADC", "Left ADC", - "AIF1 Slot 0 Right ADC", "Right ADC", - "Internal Microphone Left", "MBIAS", - "MIC1", "Internal Microphone Left", - "Internal Microphone Right", "HBIAS", - "MIC2", "Internal Microphone Right"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "host"; -}; - -&usbphy { - usb0_vbus-supply = <®_ldo_io0>; - usb1_vbus-supply = <®_ldo_io0>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/allwinner/sun50i-a64-sopine-baseboard.dts b/sys/gnu/dts/arm64/allwinner/sun50i-a64-sopine-baseboard.dts deleted file mode 100644 index 2f6ea9f3f6a..00000000000 --- a/sys/gnu/dts/arm64/allwinner/sun50i-a64-sopine-baseboard.dts +++ /dev/null @@ -1,205 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (c) 2017 Icenowy Zheng -// Based on sun50i-a64-pine64.dts, which is: -// Copyright (c) 2016 ARM Ltd. - -/dts-v1/; - -#include "sun50i-a64-sopine.dtsi" - -/ { - model = "SoPine with baseboard"; - compatible = "pine64,sopine-baseboard", "pine64,sopine", - "allwinner,sun50i-a64"; - - aliases { - ethernet0 = &emac; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - serial4 = &uart4; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - reg_vcc1v8: vcc1v8 { - compatible = "regulator-fixed"; - regulator-name = "vcc1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; -}; - -&ac_power_supply { - status = "okay"; -}; - -&battery_power_supply { - status = "okay"; -}; - -&codec { - status = "okay"; -}; - -&codec_analog { - status = "okay"; -}; - -&dai { - status = "okay"; -}; - -&de { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&emac { - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - phy-mode = "rgmii"; - phy-handle = <&ext_rgmii_phy>; - phy-supply = <®_dc1sw>; - status = "okay"; -}; - -&hdmi { - hvcc-supply = <®_dldo1>; - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&mdio { - ext_rgmii_phy: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; - vmmc-supply = <®_dcdc1>; - vqmmc-supply = <®_vcc1v8>; - bus-width = <8>; - non-removable; - cap-mmc-hw-reset; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -®_dc1sw { - /* - * Ethernet PHY needs 30ms to properly power up and some more - * to initialize. 100ms should be plenty of time to finish - * whole process. - */ - regulator-enable-ramp-delay = <100000>; - regulator-name = "vcc-phy"; -}; - -®_dldo1 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-hdmi"; -}; - -®_dldo2 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-mipi"; -}; - -®_dldo4 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi"; -}; - -&simplefb_hdmi { - vcc-hdmi-supply = <®_dldo1>; -}; - -&sound { - simple-audio-card,aux-devs = <&codec_analog>; - simple-audio-card,widgets = "Microphone", "Microphone Jack", - "Headphone", "Headphone Jack"; - simple-audio-card,routing = - "Left DAC", "AIF1 Slot 0 Left", - "Right DAC", "AIF1 Slot 0 Right", - "Headphone Jack", "HP", - "AIF1 Slot 0 Left ADC", "Left ADC", - "AIF1 Slot 0 Right ADC", "Right ADC", - "MIC2", "Microphone Jack"; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -/* On Pi-2 connector */ -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; - status = "disabled"; -}; - -/* On Euler connector */ -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; - status = "disabled"; -}; - -/* On Euler connector, RTS/CTS optional */ -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&uart4_pins>; - status = "disabled"; -}; - -&usb_otg { - dr_mode = "host"; - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/allwinner/sun50i-a64-sopine.dtsi b/sys/gnu/dts/arm64/allwinner/sun50i-a64-sopine.dtsi deleted file mode 100644 index c48692b06e1..00000000000 --- a/sys/gnu/dts/arm64/allwinner/sun50i-a64-sopine.dtsi +++ /dev/null @@ -1,138 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (c) 2017 Icenowy Zheng -// Based on sun50i-a64-pine64.dts, which is: -// Copyright (c) 2016 ARM Ltd. - -#include "sun50i-a64.dtsi" -#include "sun50i-a64-cpu-opp.dtsi" - -#include - -&codec_analog { - cpvdd-supply = <®_eldo1>; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&cpu1 { - cpu-supply = <®_dcdc2>; -}; - -&cpu2 { - cpu-supply = <®_dcdc2>; -}; - -&cpu3 { - cpu-supply = <®_dcdc2>; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; - vmmc-supply = <®_dcdc1>; - non-removable; - disable-wp; - bus-width = <4>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ - status = "okay"; -}; - -&r_rsb { - status = "okay"; - - axp803: pmic@3a3 { - compatible = "x-powers,axp803"; - reg = <0x3a3>; - interrupt-parent = <&r_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&spi0 { - status = "okay"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <40000000>; - }; -}; - -#include "axp803.dtsi" - -®_aldo2 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-pl"; -}; - -®_aldo3 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-pll-avcc"; -}; - -®_dcdc1 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-3v3"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1040000>; - regulator-max-microvolt = <1300000>; - regulator-name = "vdd-cpux"; -}; - -/* DCDC3 is polyphased with DCDC2 */ - -®_dcdc5 { - regulator-always-on; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-name = "vcc-dram"; -}; - -®_dcdc6 { - regulator-always-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-sys"; -}; - -®_eldo1 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vdd-1v8-lpddr"; -}; - -®_fldo1 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-name = "vcc-1v2-hsic"; -}; - -/* - * The A64 chip cannot work without this regulator off, although - * it seems to be only driving the AR100 core. - * Maybe we don't still know well about CPUs domain. - */ -®_fldo2 { - regulator-always-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-cpus"; -}; - -®_rtc_ldo { - regulator-name = "vcc-rtc"; -}; diff --git a/sys/gnu/dts/arm64/allwinner/sun50i-a64-teres-i.dts b/sys/gnu/dts/arm64/allwinner/sun50i-a64-teres-i.dts deleted file mode 100644 index f5df5f705b7..00000000000 --- a/sys/gnu/dts/arm64/allwinner/sun50i-a64-teres-i.dts +++ /dev/null @@ -1,382 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -// Copyright (C) Harald Geyer -// based on sun50i-a64-olinuxino.dts by Jagan Teki - -/dts-v1/; - -#include "sun50i-a64.dtsi" -#include "sun50i-a64-cpu-opp.dtsi" - -#include -#include -#include - -/ { - model = "Olimex A64 Teres-I"; - compatible = "olimex,a64-teres-i", "allwinner,sun50i-a64"; - - aliases { - serial0 = &uart0; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 0 50000 0>; - power-supply = <®_dcdc1>; - brightness-levels = <0 5 7 10 14 20 28 40 56 80 112>; - default-brightness-level = <5>; - enable-gpios = <&pio 3 23 GPIO_ACTIVE_HIGH>; /* PD23 */ - }; - - chosen { - stdout-path = "serial0:115200n8"; - - framebuffer-lcd { - eDP25-supply = <®_dldo2>; - eDP12-supply = <®_dldo3>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - lid-switch { - label = "Lid Switch"; - gpios = <&r_pio 0 8 GPIO_ACTIVE_LOW>; /* PL8 */ - linux,input-type = ; - linux,code = ; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - - capslock { - label = "teres-i:green:capslock"; - gpios = <&pio 2 7 GPIO_ACTIVE_HIGH>; /* PC7 */ - }; - - numlock { - label = "teres-i:green:numlock"; - gpios = <&pio 2 4 GPIO_ACTIVE_HIGH>; /* PC4 */ - }; - }; - - reg_usb1_vbus: usb1-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb1-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&r_pio 0 7 GPIO_ACTIVE_HIGH>; /* PL7 */ - status = "okay"; - }; - - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ - }; - - speaker_amp: audio-amplifier { - compatible = "simple-audio-amplifier"; - enable-gpios = <&r_pio 0 12 GPIO_ACTIVE_HIGH>; /* PL12 */ - sound-name-prefix = "Speaker Amp"; - }; -}; - -&codec { - status = "okay"; -}; - -&codec_analog { - cpvdd-supply = <®_eldo1>; - status = "okay"; -}; - -&dai { - status = "okay"; -}; - -&de { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&cpu1 { - cpu-supply = <®_dcdc2>; -}; - -&cpu2 { - cpu-supply = <®_dcdc2>; -}; - -&cpu3 { - cpu-supply = <®_dcdc2>; -}; - -&ehci1 { - status = "okay"; -}; - - -&i2c0 { - clock-frequency = <100000>; - status = "okay"; - - anx6345: anx6345@38 { - compatible = "analogix,anx6345"; - reg = <0x38>; - reset-gpios = <&pio 3 24 GPIO_ACTIVE_LOW>; /* PD24 */ - dvdd25-supply = <®_dldo2>; - dvdd12-supply = <®_dldo3>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - anx6345_in: endpoint { - remote-endpoint = <&tcon0_out_anx6345>; - }; - }; - }; - }; -}; - -&mixer0 { - status = "okay"; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; - vmmc-supply = <®_dcdc1>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; - disable-wp; - bus-width = <4>; - status = "okay"; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - vmmc-supply = <®_aldo2>; - vqmmc-supply = <®_dldo4>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; - - rtl8723bs: wifi@1 { - reg = <1>; - interrupt-parent = <&r_pio>; - interrupts = <0 3 IRQ_TYPE_LEVEL_LOW>; /* PL3 */ - interrupt-names = "host-wake"; - }; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; - vmmc-supply = <®_dcdc1>; - vqmmc-supply = <®_dcdc1>; - bus-width = <8>; - non-removable; - cap-mmc-hw-reset; - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&pwm { - status = "okay"; -}; - -&r_rsb { - status = "okay"; - - axp803: pmic@3a3 { - compatible = "x-powers,axp803"; - reg = <0x3a3>; - interrupt-parent = <&r_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - wakeup-source; - }; -}; - -#include "axp803.dtsi" - -&ac_power_supply { - status = "okay"; -}; - -&battery_power_supply { - status = "okay"; -}; - -®_aldo1 { - regulator-always-on; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-name = "vcc-pe"; -}; - -®_aldo2 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-pl"; -}; - -®_aldo3 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-pll-avcc"; -}; - -®_dcdc1 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-3v3"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1040000>; - regulator-max-microvolt = <1300000>; - regulator-name = "vdd-cpux"; -}; - -/* DCDC3 is polyphased with DCDC2 */ - -®_dcdc5 { - regulator-always-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vcc-ddr3"; -}; - -®_dcdc6 { - regulator-always-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-sys"; -}; - -®_dldo1 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-hdmi"; -}; - -®_dldo2 { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-name = "vcc-pd"; -}; - -®_dldo3 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-name = "vdd-edp"; -}; - -®_dldo4 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi-io"; -}; - -®_eldo1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "cpvdd"; -}; - -®_eldo2 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc-dvdd-csi"; -}; - -®_fldo1 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-name = "vcc-1v2-hsic"; -}; - -/* - * The A64 chip cannot work with this regulator off, although - * it seems to be only driving the AR100 core. - * Maybe we don't still know well about CPUs domain. - */ -®_fldo2 { - regulator-always-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-cpus"; -}; - -®_rtc_ldo { - regulator-name = "vcc-rtc"; -}; - -&simplefb_hdmi { - vcc-hdmi-supply = <®_dldo1>; -}; - -&sound { - simple-audio-card,aux-devs = <&codec_analog>, <&speaker_amp>; - simple-audio-card,widgets = "Headphone", "Headphone Jack", - "Microphone", "Headset Microphone", - "Microphone", "Internal Microphone", - "Speaker", "Internal Speaker"; - simple-audio-card,routing = - "Left DAC", "AIF1 Slot 0 Left", - "Right DAC", "AIF1 Slot 0 Right", - "AIF1 Slot 0 Left ADC", "Left ADC", - "AIF1 Slot 0 Right ADC", "Right ADC", - "Headphone Jack", "HP", - "Speaker Amp INL", "LINEOUT", - "Speaker Amp INR", "LINEOUT", - "Internal Speaker", "Speaker Amp OUTL", - "Internal Speaker", "Speaker Amp OUTR", - "Internal Microphone", "MBIAS", - "MIC1", "Internal Microphone", - "Headset Microphone", "HBIAS", - "MIC2", "Headset Microphone"; - status = "okay"; -}; - -&tcon0 { - pinctrl-names = "default"; - pinctrl-0 = <&lcd_rgb666_pins>; - - status = "okay"; -}; - -&tcon0_out { - tcon0_out_anx6345: endpoint@0 { - reg = <0>; - remote-endpoint = <&anx6345_in>; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usbphy { - usb1_vbus-supply = <®_usb1_vbus>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/allwinner/sun50i-a64.dtsi b/sys/gnu/dts/arm64/allwinner/sun50i-a64.dtsi deleted file mode 100644 index 862b47dc9dc..00000000000 --- a/sys/gnu/dts/arm64/allwinner/sun50i-a64.dtsi +++ /dev/null @@ -1,1279 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (C) 2016 ARM Ltd. -// based on the Allwinner H3 dtsi: -// Copyright (C) 2015 Jens Kuske - -#include -#include -#include -#include -#include -#include -#include -#include - -/ { - interrupt-parent = <&gic>; - #address-cells = <1>; - #size-cells = <1>; - - chosen { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - simplefb_lcd: framebuffer-lcd { - compatible = "allwinner,simple-framebuffer", - "simple-framebuffer"; - allwinner,pipeline = "mixer0-lcd0"; - clocks = <&ccu CLK_TCON0>, - <&display_clocks CLK_MIXER0>; - status = "disabled"; - }; - - simplefb_hdmi: framebuffer-hdmi { - compatible = "allwinner,simple-framebuffer", - "simple-framebuffer"; - allwinner,pipeline = "mixer1-lcd1-hdmi"; - clocks = <&display_clocks CLK_MIXER1>, - <&ccu CLK_TCON1>, <&ccu CLK_HDMI>; - status = "disabled"; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <0>; - enable-method = "psci"; - next-level-cache = <&L2>; - clocks = <&ccu 21>; - clock-names = "cpu"; - #cooling-cells = <2>; - }; - - cpu1: cpu@1 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <1>; - enable-method = "psci"; - next-level-cache = <&L2>; - clocks = <&ccu 21>; - clock-names = "cpu"; - #cooling-cells = <2>; - }; - - cpu2: cpu@2 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <2>; - enable-method = "psci"; - next-level-cache = <&L2>; - clocks = <&ccu 21>; - clock-names = "cpu"; - #cooling-cells = <2>; - }; - - cpu3: cpu@3 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <3>; - enable-method = "psci"; - next-level-cache = <&L2>; - clocks = <&ccu 21>; - clock-names = "cpu"; - #cooling-cells = <2>; - }; - - L2: l2-cache { - compatible = "cache"; - cache-level = <2>; - }; - }; - - de: display-engine { - compatible = "allwinner,sun50i-a64-display-engine"; - allwinner,pipelines = <&mixer0>, - <&mixer1>; - status = "disabled"; - }; - - osc24M: osc24M_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "osc24M"; - }; - - osc32k: osc32k_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - clock-output-names = "ext-osc32k"; - }; - - pmu { - compatible = "arm,cortex-a53-pmu"; - interrupts = , - , - , - ; - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - sound: sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "sun50i-a64-audio"; - simple-audio-card,format = "i2s"; - simple-audio-card,frame-master = <&cpudai>; - simple-audio-card,bitclock-master = <&cpudai>; - simple-audio-card,mclk-fs = <128>; - simple-audio-card,aux-devs = <&codec_analog>; - simple-audio-card,routing = - "Left DAC", "AIF1 Slot 0 Left", - "Right DAC", "AIF1 Slot 0 Right", - "AIF1 Slot 0 Left ADC", "Left ADC", - "AIF1 Slot 0 Right ADC", "Right ADC"; - status = "disabled"; - - cpudai: simple-audio-card,cpu { - sound-dai = <&dai>; - }; - - link_codec: simple-audio-card,codec { - sound-dai = <&codec>; - }; - }; - - sound_spdif { - compatible = "simple-audio-card"; - simple-audio-card,name = "On-board SPDIF"; - - simple-audio-card,cpu { - sound-dai = <&spdif>; - }; - - simple-audio-card,codec { - sound-dai = <&spdif_out>; - }; - }; - - spdif_out: spdif-out { - #sound-dai-cells = <0>; - compatible = "linux,spdif-dit"; - }; - - timer { - compatible = "arm,armv8-timer"; - allwinner,erratum-unknown1; - interrupts = , - , - , - ; - }; - - thermal-zones { - cpu_thermal: cpu0-thermal { - /* milliseconds */ - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&ths 0>; - - cooling-maps { - map0 { - trip = <&cpu_alert0>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu_alert1>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - - trips { - cpu_alert0: cpu_alert0 { - /* milliCelsius */ - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu_alert1: cpu_alert1 { - /* milliCelsius */ - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - - cpu_crit: cpu_crit { - /* milliCelsius */ - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - gpu0_thermal: gpu0-thermal { - /* milliseconds */ - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&ths 1>; - }; - - gpu1_thermal: gpu1-thermal { - /* milliseconds */ - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&ths 2>; - }; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - bus@1000000 { - compatible = "allwinner,sun50i-a64-de2"; - reg = <0x1000000 0x400000>; - allwinner,sram = <&de2_sram 1>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1000000 0x400000>; - - display_clocks: clock@0 { - compatible = "allwinner,sun50i-a64-de2-clk"; - reg = <0x0 0x100000>; - clocks = <&ccu CLK_BUS_DE>, - <&ccu CLK_DE>; - clock-names = "bus", - "mod"; - resets = <&ccu RST_BUS_DE>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - mixer0: mixer@100000 { - compatible = "allwinner,sun50i-a64-de2-mixer-0"; - reg = <0x100000 0x100000>; - clocks = <&display_clocks CLK_BUS_MIXER0>, - <&display_clocks CLK_MIXER0>; - clock-names = "bus", - "mod"; - resets = <&display_clocks RST_MIXER0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - mixer0_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - mixer0_out_tcon0: endpoint@0 { - reg = <0>; - remote-endpoint = <&tcon0_in_mixer0>; - }; - - mixer0_out_tcon1: endpoint@1 { - reg = <1>; - remote-endpoint = <&tcon1_in_mixer0>; - }; - }; - }; - }; - - mixer1: mixer@200000 { - compatible = "allwinner,sun50i-a64-de2-mixer-1"; - reg = <0x200000 0x100000>; - clocks = <&display_clocks CLK_BUS_MIXER1>, - <&display_clocks CLK_MIXER1>; - clock-names = "bus", - "mod"; - resets = <&display_clocks RST_MIXER1>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - mixer1_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - mixer1_out_tcon0: endpoint@0 { - reg = <0>; - remote-endpoint = <&tcon0_in_mixer1>; - }; - - mixer1_out_tcon1: endpoint@1 { - reg = <1>; - remote-endpoint = <&tcon1_in_mixer1>; - }; - }; - }; - }; - }; - - syscon: syscon@1c00000 { - compatible = "allwinner,sun50i-a64-system-control"; - reg = <0x01c00000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - sram_c: sram@18000 { - compatible = "mmio-sram"; - reg = <0x00018000 0x28000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x00018000 0x28000>; - - de2_sram: sram-section@0 { - compatible = "allwinner,sun50i-a64-sram-c"; - reg = <0x0000 0x28000>; - }; - }; - - sram_c1: sram@1d00000 { - compatible = "mmio-sram"; - reg = <0x01d00000 0x40000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x01d00000 0x40000>; - - ve_sram: sram-section@0 { - compatible = "allwinner,sun50i-a64-sram-c1", - "allwinner,sun4i-a10-sram-c1"; - reg = <0x000000 0x40000>; - }; - }; - }; - - dma: dma-controller@1c02000 { - compatible = "allwinner,sun50i-a64-dma"; - reg = <0x01c02000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_BUS_DMA>; - dma-channels = <8>; - dma-requests = <27>; - resets = <&ccu RST_BUS_DMA>; - #dma-cells = <1>; - }; - - tcon0: lcd-controller@1c0c000 { - compatible = "allwinner,sun50i-a64-tcon-lcd", - "allwinner,sun8i-a83t-tcon-lcd"; - reg = <0x01c0c000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>; - clock-names = "ahb", "tcon-ch0"; - clock-output-names = "tcon-pixel-clock"; - #clock-cells = <0>; - resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>; - reset-names = "lcd", "lvds"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - tcon0_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - tcon0_in_mixer0: endpoint@0 { - reg = <0>; - remote-endpoint = <&mixer0_out_tcon0>; - }; - - tcon0_in_mixer1: endpoint@1 { - reg = <1>; - remote-endpoint = <&mixer1_out_tcon0>; - }; - }; - - tcon0_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - tcon0_out_dsi: endpoint@1 { - reg = <1>; - remote-endpoint = <&dsi_in_tcon0>; - allwinner,tcon-channel = <1>; - }; - }; - }; - }; - - tcon1: lcd-controller@1c0d000 { - compatible = "allwinner,sun50i-a64-tcon-tv", - "allwinner,sun8i-a83t-tcon-tv"; - reg = <0x01c0d000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>; - clock-names = "ahb", "tcon-ch1"; - resets = <&ccu RST_BUS_TCON1>; - reset-names = "lcd"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - tcon1_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - tcon1_in_mixer0: endpoint@0 { - reg = <0>; - remote-endpoint = <&mixer0_out_tcon1>; - }; - - tcon1_in_mixer1: endpoint@1 { - reg = <1>; - remote-endpoint = <&mixer1_out_tcon1>; - }; - }; - - tcon1_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - tcon1_out_hdmi: endpoint@1 { - reg = <1>; - remote-endpoint = <&hdmi_in_tcon1>; - }; - }; - }; - }; - - video-codec@1c0e000 { - compatible = "allwinner,sun50i-a64-video-engine"; - reg = <0x01c0e000 0x1000>; - clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, - <&ccu CLK_DRAM_VE>; - clock-names = "ahb", "mod", "ram"; - resets = <&ccu RST_BUS_VE>; - interrupts = ; - allwinner,sram = <&ve_sram 1>; - }; - - mmc0: mmc@1c0f000 { - compatible = "allwinner,sun50i-a64-mmc"; - reg = <0x01c0f000 0x1000>; - clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; - clock-names = "ahb", "mmc"; - resets = <&ccu RST_BUS_MMC0>; - reset-names = "ahb"; - interrupts = ; - max-frequency = <150000000>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc1: mmc@1c10000 { - compatible = "allwinner,sun50i-a64-mmc"; - reg = <0x01c10000 0x1000>; - clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; - clock-names = "ahb", "mmc"; - resets = <&ccu RST_BUS_MMC1>; - reset-names = "ahb"; - interrupts = ; - max-frequency = <150000000>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc2: mmc@1c11000 { - compatible = "allwinner,sun50i-a64-emmc"; - reg = <0x01c11000 0x1000>; - clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; - clock-names = "ahb", "mmc"; - resets = <&ccu RST_BUS_MMC2>; - reset-names = "ahb"; - interrupts = ; - max-frequency = <200000000>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - sid: eeprom@1c14000 { - compatible = "allwinner,sun50i-a64-sid"; - reg = <0x1c14000 0x400>; - #address-cells = <1>; - #size-cells = <1>; - - ths_calibration: thermal-sensor-calibration@34 { - reg = <0x34 0x8>; - }; - }; - - crypto: crypto@1c15000 { - compatible = "allwinner,sun50i-a64-crypto"; - reg = <0x01c15000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>; - clock-names = "bus", "mod"; - resets = <&ccu RST_BUS_CE>; - }; - - usb_otg: usb@1c19000 { - compatible = "allwinner,sun8i-a33-musb"; - reg = <0x01c19000 0x0400>; - clocks = <&ccu CLK_BUS_OTG>; - resets = <&ccu RST_BUS_OTG>; - interrupts = ; - interrupt-names = "mc"; - phys = <&usbphy 0>; - phy-names = "usb"; - extcon = <&usbphy 0>; - dr_mode = "otg"; - status = "disabled"; - }; - - usbphy: phy@1c19400 { - compatible = "allwinner,sun50i-a64-usb-phy"; - reg = <0x01c19400 0x14>, - <0x01c1a800 0x4>, - <0x01c1b800 0x4>; - reg-names = "phy_ctrl", - "pmu0", - "pmu1"; - clocks = <&ccu CLK_USB_PHY0>, - <&ccu CLK_USB_PHY1>; - clock-names = "usb0_phy", - "usb1_phy"; - resets = <&ccu RST_USB_PHY0>, - <&ccu RST_USB_PHY1>; - reset-names = "usb0_reset", - "usb1_reset"; - status = "disabled"; - #phy-cells = <1>; - }; - - ehci0: usb@1c1a000 { - compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; - reg = <0x01c1a000 0x100>; - interrupts = ; - clocks = <&ccu CLK_BUS_OHCI0>, - <&ccu CLK_BUS_EHCI0>, - <&ccu CLK_USB_OHCI0>; - resets = <&ccu RST_BUS_OHCI0>, - <&ccu RST_BUS_EHCI0>; - status = "disabled"; - }; - - ohci0: usb@1c1a400 { - compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; - reg = <0x01c1a400 0x100>; - interrupts = ; - clocks = <&ccu CLK_BUS_OHCI0>, - <&ccu CLK_USB_OHCI0>; - resets = <&ccu RST_BUS_OHCI0>; - status = "disabled"; - }; - - ehci1: usb@1c1b000 { - compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; - reg = <0x01c1b000 0x100>; - interrupts = ; - clocks = <&ccu CLK_BUS_OHCI1>, - <&ccu CLK_BUS_EHCI1>, - <&ccu CLK_USB_OHCI1>; - resets = <&ccu RST_BUS_OHCI1>, - <&ccu RST_BUS_EHCI1>; - phys = <&usbphy 1>; - phy-names = "usb"; - status = "disabled"; - }; - - ohci1: usb@1c1b400 { - compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; - reg = <0x01c1b400 0x100>; - interrupts = ; - clocks = <&ccu CLK_BUS_OHCI1>, - <&ccu CLK_USB_OHCI1>; - resets = <&ccu RST_BUS_OHCI1>; - phys = <&usbphy 1>; - phy-names = "usb"; - status = "disabled"; - }; - - ccu: clock@1c20000 { - compatible = "allwinner,sun50i-a64-ccu"; - reg = <0x01c20000 0x400>; - clocks = <&osc24M>, <&rtc 0>; - clock-names = "hosc", "losc"; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - pio: pinctrl@1c20800 { - compatible = "allwinner,sun50i-a64-pinctrl"; - reg = <0x01c20800 0x400>; - interrupts = , - , - ; - clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>; - clock-names = "apb", "hosc", "losc"; - gpio-controller; - #gpio-cells = <3>; - interrupt-controller; - #interrupt-cells = <3>; - - csi_pins: csi-pins { - pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6", - "PE7", "PE8", "PE9", "PE10", "PE11"; - function = "csi"; - }; - - /omit-if-no-ref/ - csi_mclk_pin: csi-mclk-pin { - pins = "PE1"; - function = "csi"; - }; - - i2c0_pins: i2c0-pins { - pins = "PH0", "PH1"; - function = "i2c0"; - }; - - i2c1_pins: i2c1-pins { - pins = "PH2", "PH3"; - function = "i2c1"; - }; - - /omit-if-no-ref/ - lcd_rgb666_pins: lcd-rgb666-pins { - pins = "PD0", "PD1", "PD2", "PD3", "PD4", - "PD5", "PD6", "PD7", "PD8", "PD9", - "PD10", "PD11", "PD12", "PD13", - "PD14", "PD15", "PD16", "PD17", - "PD18", "PD19", "PD20", "PD21"; - function = "lcd0"; - }; - - mmc0_pins: mmc0-pins { - pins = "PF0", "PF1", "PF2", "PF3", - "PF4", "PF5"; - function = "mmc0"; - drive-strength = <30>; - bias-pull-up; - }; - - mmc1_pins: mmc1-pins { - pins = "PG0", "PG1", "PG2", "PG3", - "PG4", "PG5"; - function = "mmc1"; - drive-strength = <30>; - bias-pull-up; - }; - - mmc2_pins: mmc2-pins { - pins = "PC5", "PC6", "PC8", "PC9", - "PC10","PC11", "PC12", "PC13", - "PC14", "PC15", "PC16"; - function = "mmc2"; - drive-strength = <30>; - bias-pull-up; - }; - - mmc2_ds_pin: mmc2-ds-pin { - pins = "PC1"; - function = "mmc2"; - drive-strength = <30>; - bias-pull-up; - }; - - pwm_pin: pwm-pin { - pins = "PD22"; - function = "pwm"; - }; - - rmii_pins: rmii-pins { - pins = "PD10", "PD11", "PD13", "PD14", "PD17", - "PD18", "PD19", "PD20", "PD22", "PD23"; - function = "emac"; - drive-strength = <40>; - }; - - rgmii_pins: rgmii-pins { - pins = "PD8", "PD9", "PD10", "PD11", "PD12", - "PD13", "PD15", "PD16", "PD17", "PD18", - "PD19", "PD20", "PD21", "PD22", "PD23"; - function = "emac"; - drive-strength = <40>; - }; - - spdif_tx_pin: spdif-tx-pin { - pins = "PH8"; - function = "spdif"; - }; - - spi0_pins: spi0-pins { - pins = "PC0", "PC1", "PC2", "PC3"; - function = "spi0"; - }; - - spi1_pins: spi1-pins { - pins = "PD0", "PD1", "PD2", "PD3"; - function = "spi1"; - }; - - uart0_pb_pins: uart0-pb-pins { - pins = "PB8", "PB9"; - function = "uart0"; - }; - - uart1_pins: uart1-pins { - pins = "PG6", "PG7"; - function = "uart1"; - }; - - uart1_rts_cts_pins: uart1-rts-cts-pins { - pins = "PG8", "PG9"; - function = "uart1"; - }; - - uart2_pins: uart2-pins { - pins = "PB0", "PB1"; - function = "uart2"; - }; - - uart3_pins: uart3-pins { - pins = "PD0", "PD1"; - function = "uart3"; - }; - - uart4_pins: uart4-pins { - pins = "PD2", "PD3"; - function = "uart4"; - }; - - uart4_rts_cts_pins: uart4-rts-cts-pins { - pins = "PD4", "PD5"; - function = "uart4"; - }; - }; - - spdif: spdif@1c21000 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun50i-a64-spdif", - "allwinner,sun8i-h3-spdif"; - reg = <0x01c21000 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; - resets = <&ccu RST_BUS_SPDIF>; - clock-names = "apb", "spdif"; - dmas = <&dma 2>; - dma-names = "tx"; - pinctrl-names = "default"; - pinctrl-0 = <&spdif_tx_pin>; - status = "disabled"; - }; - - lradc: lradc@1c21800 { - compatible = "allwinner,sun50i-a64-lradc", - "allwinner,sun8i-a83t-r-lradc"; - reg = <0x01c21800 0x400>; - interrupts = ; - status = "disabled"; - }; - - i2s0: i2s@1c22000 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun50i-a64-i2s", - "allwinner,sun8i-h3-i2s"; - reg = <0x01c22000 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>; - clock-names = "apb", "mod"; - resets = <&ccu RST_BUS_I2S0>; - dma-names = "rx", "tx"; - dmas = <&dma 3>, <&dma 3>; - status = "disabled"; - }; - - i2s1: i2s@1c22400 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun50i-a64-i2s", - "allwinner,sun8i-h3-i2s"; - reg = <0x01c22400 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>; - clock-names = "apb", "mod"; - resets = <&ccu RST_BUS_I2S1>; - dma-names = "rx", "tx"; - dmas = <&dma 4>, <&dma 4>; - status = "disabled"; - }; - - dai: dai@1c22c00 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun50i-a64-codec-i2s"; - reg = <0x01c22c00 0x200>; - interrupts = ; - clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; - clock-names = "apb", "mod"; - resets = <&ccu RST_BUS_CODEC>; - dmas = <&dma 15>, <&dma 15>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - codec: codec@1c22e00 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun8i-a33-codec"; - reg = <0x01c22e00 0x600>; - interrupts = ; - clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; - clock-names = "bus", "mod"; - status = "disabled"; - }; - - ths: thermal-sensor@1c25000 { - compatible = "allwinner,sun50i-a64-ths"; - reg = <0x01c25000 0x100>; - clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>; - clock-names = "bus", "mod"; - interrupts = ; - resets = <&ccu RST_BUS_THS>; - nvmem-cells = <&ths_calibration>; - nvmem-cell-names = "calibration"; - #thermal-sensor-cells = <1>; - }; - - uart0: serial@1c28000 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART0>; - resets = <&ccu RST_BUS_UART0>; - status = "disabled"; - }; - - uart1: serial@1c28400 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28400 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART1>; - resets = <&ccu RST_BUS_UART1>; - status = "disabled"; - }; - - uart2: serial@1c28800 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28800 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART2>; - resets = <&ccu RST_BUS_UART2>; - status = "disabled"; - }; - - uart3: serial@1c28c00 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28c00 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART3>; - resets = <&ccu RST_BUS_UART3>; - status = "disabled"; - }; - - uart4: serial@1c29000 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c29000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART4>; - resets = <&ccu RST_BUS_UART4>; - status = "disabled"; - }; - - i2c0: i2c@1c2ac00 { - compatible = "allwinner,sun6i-a31-i2c"; - reg = <0x01c2ac00 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_I2C0>; - resets = <&ccu RST_BUS_I2C0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c1: i2c@1c2b000 { - compatible = "allwinner,sun6i-a31-i2c"; - reg = <0x01c2b000 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_I2C1>; - resets = <&ccu RST_BUS_I2C1>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c2: i2c@1c2b400 { - compatible = "allwinner,sun6i-a31-i2c"; - reg = <0x01c2b400 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_I2C2>; - resets = <&ccu RST_BUS_I2C2>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - - spi0: spi@1c68000 { - compatible = "allwinner,sun8i-h3-spi"; - reg = <0x01c68000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; - clock-names = "ahb", "mod"; - dmas = <&dma 23>, <&dma 23>; - dma-names = "rx", "tx"; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins>; - resets = <&ccu RST_BUS_SPI0>; - status = "disabled"; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - }; - - spi1: spi@1c69000 { - compatible = "allwinner,sun8i-h3-spi"; - reg = <0x01c69000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; - clock-names = "ahb", "mod"; - dmas = <&dma 24>, <&dma 24>; - dma-names = "rx", "tx"; - pinctrl-names = "default"; - pinctrl-0 = <&spi1_pins>; - resets = <&ccu RST_BUS_SPI1>; - status = "disabled"; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - }; - - emac: ethernet@1c30000 { - compatible = "allwinner,sun50i-a64-emac"; - syscon = <&syscon>; - reg = <0x01c30000 0x10000>; - interrupts = ; - interrupt-names = "macirq"; - resets = <&ccu RST_BUS_EMAC>; - reset-names = "stmmaceth"; - clocks = <&ccu CLK_BUS_EMAC>; - clock-names = "stmmaceth"; - status = "disabled"; - - mdio: mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - mali: gpu@1c40000 { - compatible = "allwinner,sun50i-a64-mali", "arm,mali-400"; - reg = <0x01c40000 0x10000>; - interrupts = , - , - , - , - , - , - ; - interrupt-names = "gp", - "gpmmu", - "pp0", - "ppmmu0", - "pp1", - "ppmmu1", - "pmu"; - clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>; - clock-names = "bus", "core"; - resets = <&ccu RST_BUS_GPU>; - }; - - gic: interrupt-controller@1c81000 { - compatible = "arm,gic-400"; - reg = <0x01c81000 0x1000>, - <0x01c82000 0x2000>, - <0x01c84000 0x2000>, - <0x01c86000 0x2000>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <3>; - }; - - pwm: pwm@1c21400 { - compatible = "allwinner,sun50i-a64-pwm", - "allwinner,sun5i-a13-pwm"; - reg = <0x01c21400 0x400>; - clocks = <&osc24M>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm_pin>; - #pwm-cells = <3>; - status = "disabled"; - }; - - csi: csi@1cb0000 { - compatible = "allwinner,sun50i-a64-csi"; - reg = <0x01cb0000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_BUS_CSI>, - <&ccu CLK_CSI_SCLK>, - <&ccu CLK_DRAM_CSI>; - clock-names = "bus", "mod", "ram"; - resets = <&ccu RST_BUS_CSI>; - pinctrl-names = "default"; - pinctrl-0 = <&csi_pins>; - status = "disabled"; - }; - - dsi: dsi@1ca0000 { - compatible = "allwinner,sun50i-a64-mipi-dsi"; - reg = <0x01ca0000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_BUS_MIPI_DSI>; - resets = <&ccu RST_BUS_MIPI_DSI>; - phys = <&dphy>; - phy-names = "dphy"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - - port { - dsi_in_tcon0: endpoint { - remote-endpoint = <&tcon0_out_dsi>; - }; - }; - }; - - dphy: d-phy@1ca1000 { - compatible = "allwinner,sun50i-a64-mipi-dphy", - "allwinner,sun6i-a31-mipi-dphy"; - reg = <0x01ca1000 0x1000>; - clocks = <&ccu CLK_BUS_MIPI_DSI>, - <&ccu CLK_DSI_DPHY>; - clock-names = "bus", "mod"; - resets = <&ccu RST_BUS_MIPI_DSI>; - status = "disabled"; - #phy-cells = <0>; - }; - - hdmi: hdmi@1ee0000 { - compatible = "allwinner,sun50i-a64-dw-hdmi", - "allwinner,sun8i-a83t-dw-hdmi"; - reg = <0x01ee0000 0x10000>; - reg-io-width = <1>; - interrupts = ; - clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, - <&ccu CLK_HDMI>; - clock-names = "iahb", "isfr", "tmds"; - resets = <&ccu RST_BUS_HDMI1>; - reset-names = "ctrl"; - phys = <&hdmi_phy>; - phy-names = "phy"; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - hdmi_in: port@0 { - reg = <0>; - - hdmi_in_tcon1: endpoint { - remote-endpoint = <&tcon1_out_hdmi>; - }; - }; - - hdmi_out: port@1 { - reg = <1>; - }; - }; - }; - - hdmi_phy: hdmi-phy@1ef0000 { - compatible = "allwinner,sun50i-a64-hdmi-phy"; - reg = <0x01ef0000 0x10000>; - clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, - <&ccu CLK_PLL_VIDEO0>; - clock-names = "bus", "mod", "pll-0"; - resets = <&ccu RST_BUS_HDMI0>; - reset-names = "phy"; - #phy-cells = <0>; - }; - - rtc: rtc@1f00000 { - compatible = "allwinner,sun50i-a64-rtc", - "allwinner,sun8i-h3-rtc"; - reg = <0x01f00000 0x400>; - interrupts = , - ; - clock-output-names = "osc32k", "osc32k-out", "iosc"; - clocks = <&osc32k>; - #clock-cells = <1>; - }; - - r_intc: interrupt-controller@1f00c00 { - compatible = "allwinner,sun50i-a64-r-intc", - "allwinner,sun6i-a31-r-intc"; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x01f00c00 0x400>; - interrupts = ; - }; - - r_ccu: clock@1f01400 { - compatible = "allwinner,sun50i-a64-r-ccu"; - reg = <0x01f01400 0x100>; - clocks = <&osc24M>, <&rtc 0>, <&rtc 2>, - <&ccu CLK_PLL_PERIPH0>; - clock-names = "hosc", "losc", "iosc", "pll-periph"; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - codec_analog: codec-analog@1f015c0 { - compatible = "allwinner,sun50i-a64-codec-analog"; - reg = <0x01f015c0 0x4>; - status = "disabled"; - }; - - r_i2c: i2c@1f02400 { - compatible = "allwinner,sun50i-a64-i2c", - "allwinner,sun6i-a31-i2c"; - reg = <0x01f02400 0x400>; - interrupts = ; - clocks = <&r_ccu CLK_APB0_I2C>; - resets = <&r_ccu RST_APB0_I2C>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - r_ir: ir@1f02000 { - compatible = "allwinner,sun50i-a64-ir", - "allwinner,sun6i-a31-ir"; - reg = <0x01f02000 0x400>; - clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>; - clock-names = "apb", "ir"; - resets = <&r_ccu RST_APB0_IR>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&r_ir_rx_pin>; - status = "disabled"; - }; - - r_pwm: pwm@1f03800 { - compatible = "allwinner,sun50i-a64-pwm", - "allwinner,sun5i-a13-pwm"; - reg = <0x01f03800 0x400>; - clocks = <&osc24M>; - pinctrl-names = "default"; - pinctrl-0 = <&r_pwm_pin>; - #pwm-cells = <3>; - status = "disabled"; - }; - - r_pio: pinctrl@1f02c00 { - compatible = "allwinner,sun50i-a64-r-pinctrl"; - reg = <0x01f02c00 0x400>; - interrupts = ; - clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>; - clock-names = "apb", "hosc", "losc"; - gpio-controller; - #gpio-cells = <3>; - interrupt-controller; - #interrupt-cells = <3>; - - r_i2c_pl89_pins: r-i2c-pl89-pins { - pins = "PL8", "PL9"; - function = "s_i2c"; - }; - - r_ir_rx_pin: r-ir-rx-pin { - pins = "PL11"; - function = "s_cir_rx"; - }; - - r_pwm_pin: r-pwm-pin { - pins = "PL10"; - function = "s_pwm"; - }; - - r_rsb_pins: r-rsb-pins { - pins = "PL0", "PL1"; - function = "s_rsb"; - }; - }; - - r_rsb: rsb@1f03400 { - compatible = "allwinner,sun8i-a23-rsb"; - reg = <0x01f03400 0x400>; - interrupts = ; - clocks = <&r_ccu 6>; - clock-frequency = <3000000>; - resets = <&r_ccu 2>; - pinctrl-names = "default"; - pinctrl-0 = <&r_rsb_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - wdt0: watchdog@1c20ca0 { - compatible = "allwinner,sun50i-a64-wdt", - "allwinner,sun6i-a31-wdt"; - reg = <0x01c20ca0 0x20>; - interrupts = ; - clocks = <&osc24M>; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/allwinner/sun50i-h5-bananapi-m2-plus-v1.2.dts b/sys/gnu/dts/arm64/allwinner/sun50i-h5-bananapi-m2-plus-v1.2.dts deleted file mode 100644 index 2e2b14c0ae7..00000000000 --- a/sys/gnu/dts/arm64/allwinner/sun50i-h5-bananapi-m2-plus-v1.2.dts +++ /dev/null @@ -1,11 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (C) 2018 Chen-Yu Tsai - -/dts-v1/; -#include "sun50i-h5.dtsi" -#include - -/ { - model = "Banana Pi BPI-M2-Plus v1.2 H5"; - compatible = "bananapi,bpi-m2-plus-v1.2", "allwinner,sun50i-h5"; -}; diff --git a/sys/gnu/dts/arm64/allwinner/sun50i-h5-bananapi-m2-plus.dts b/sys/gnu/dts/arm64/allwinner/sun50i-h5-bananapi-m2-plus.dts deleted file mode 100644 index 77661006dfb..00000000000 --- a/sys/gnu/dts/arm64/allwinner/sun50i-h5-bananapi-m2-plus.dts +++ /dev/null @@ -1,11 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (C) 2018 Chen-Yu Tsai - -/dts-v1/; -#include "sun50i-h5.dtsi" -#include - -/ { - model = "Banana Pi BPI-M2-Plus H5"; - compatible = "sinovoip,bpi-m2-plus", "allwinner,sun50i-h5"; -}; diff --git a/sys/gnu/dts/arm64/allwinner/sun50i-h5-emlid-neutis-n5-devboard.dts b/sys/gnu/dts/arm64/allwinner/sun50i-h5-emlid-neutis-n5-devboard.dts deleted file mode 100644 index 076a0b98310..00000000000 --- a/sys/gnu/dts/arm64/allwinner/sun50i-h5-emlid-neutis-n5-devboard.dts +++ /dev/null @@ -1,71 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -// Copyright (C) 2018 Aleksandr Aleksandrov - -/* - * DTS for Emlid Neutis N5 Dev board. - */ - -/dts-v1/; - -#include "sun50i-h5-emlid-neutis-n5.dtsi" - -/ { - model = "Emlid Neutis N5 Developer board"; - compatible = "emlid,neutis-n5-devboard", - "emlid,neutis-n5", - "allwinner,sun50i-h5"; - - connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - vdd_cpux: gpio-regulator { - compatible = "regulator-gpio"; - regulator-name = "vdd-cpux"; - regulator-type = "voltage"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1300000>; - regulator-ramp-delay = <50>; /* 4ms */ - gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ - gpios-states = <0x1>; - states = <1100000 0>, <1300000 1>; - }; -}; - -&cpu0 { - cpu-supply = <&vdd_cpux>; -}; - -&codec { - status = "okay"; -}; - -&emac { - phy-handle = <&int_mii_phy>; - phy-mode = "mii"; - allwinner,leds-active-low; - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&i2c1 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/allwinner/sun50i-h5-emlid-neutis-n5.dtsi b/sys/gnu/dts/arm64/allwinner/sun50i-h5-emlid-neutis-n5.dtsi deleted file mode 100644 index fc570011495..00000000000 --- a/sys/gnu/dts/arm64/allwinner/sun50i-h5-emlid-neutis-n5.dtsi +++ /dev/null @@ -1,11 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -// Copyright (C) 2018 Aleksandr Aleksandrov - -/* - * DTSI for Emlid Neutis N5 SoM. - */ - -/dts-v1/; - -#include "sun50i-h5.dtsi" -#include diff --git a/sys/gnu/dts/arm64/allwinner/sun50i-h5-libretech-all-h3-cc.dts b/sys/gnu/dts/arm64/allwinner/sun50i-h5-libretech-all-h3-cc.dts deleted file mode 100644 index 64d35daf202..00000000000 --- a/sys/gnu/dts/arm64/allwinner/sun50i-h5-libretech-all-h3-cc.dts +++ /dev/null @@ -1,16 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (C) 2018 BayLibre, SAS -// Author: Neil Armstrong - -/dts-v1/; -#include "sun50i-h5.dtsi" -#include - -/ { - model = "Libre Computer Board ALL-H3-CC H5"; - compatible = "libretech,all-h3-cc-h5", "allwinner,sun50i-h5"; -}; - -&mmc2 { - mmc-ddr-3_3v; -}; diff --git a/sys/gnu/dts/arm64/allwinner/sun50i-h5-libretech-all-h3-it.dts b/sys/gnu/dts/arm64/allwinner/sun50i-h5-libretech-all-h3-it.dts deleted file mode 100644 index e59d68b525f..00000000000 --- a/sys/gnu/dts/arm64/allwinner/sun50i-h5-libretech-all-h3-it.dts +++ /dev/null @@ -1,11 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (C) 2019 Chen-Yu Tsai - -/dts-v1/; -#include "sun50i-h5.dtsi" -#include - -/ { - model = "Libre Computer Board ALL-H3-IT H5"; - compatible = "libretech,all-h3-it-h5", "allwinner,sun50i-h5"; -}; diff --git a/sys/gnu/dts/arm64/allwinner/sun50i-h5-libretech-all-h5-cc.dts b/sys/gnu/dts/arm64/allwinner/sun50i-h5-libretech-all-h5-cc.dts deleted file mode 100644 index df1b9263ad0..00000000000 --- a/sys/gnu/dts/arm64/allwinner/sun50i-h5-libretech-all-h5-cc.dts +++ /dev/null @@ -1,61 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (C) 2020 Chen-Yu Tsai - -#include "sun50i-h5-libretech-all-h3-cc.dts" - -/ { - model = "Libre Computer Board ALL-H5-CC H5"; - compatible = "libretech,all-h5-cc-h5", "allwinner,sun50i-h5"; - - aliases { - spi0 = &spi0; - }; - - reg_gmac_3v3: gmac-3v3 { - compatible = "regulator-fixed"; - regulator-name = "gmac-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <5000>; - enable-active-high; - gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; - vin-supply = <®_vcc5v0>; - }; -}; - -&codec { - /* No line out; only onboard microphone */ - allwinner,audio-routing = - "MIC1", "Mic", - "Mic", "MBIAS"; -}; - -/* This board has external PHY */ -&emac { - pinctrl-names = "default"; - pinctrl-0 = <&emac_rgmii_pins>; - phy-supply = <®_gmac_3v3>; - phy-handle = <&ext_rgmii_phy>; - phy-mode = "rgmii"; - /delete-property/ allwinner,leds-active-low; - status = "okay"; -}; - -&external_mdio { - ext_rgmii_phy: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; -}; - -&spi0 { - status = "okay"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <50000000>; - }; -}; diff --git a/sys/gnu/dts/arm64/allwinner/sun50i-h5-nanopi-neo-plus2.dts b/sys/gnu/dts/arm64/allwinner/sun50i-h5-nanopi-neo-plus2.dts deleted file mode 100644 index 4f9ba53ffaa..00000000000 --- a/sys/gnu/dts/arm64/allwinner/sun50i-h5-nanopi-neo-plus2.dts +++ /dev/null @@ -1,163 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (C) 2017 Antony Antony -// Copyright (C) 2016 ARM Ltd. - -/dts-v1/; -#include "sun50i-h5.dtsi" - -#include -#include -#include - -/ { - model = "FriendlyARM NanoPi NEO Plus2"; - compatible = "friendlyarm,nanopi-neo-plus2", "allwinner,sun50i-h5"; - - aliases { - ethernet0 = &emac; - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - pwr { - label = "nanopi:green:pwr"; - gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - status { - label = "nanopi:red:status"; - gpios = <&pio 0 20 GPIO_ACTIVE_HIGH>; - }; - }; - - reg_gmac_3v3: gmac-3v3 { - compatible = "regulator-fixed"; - regulator-name = "gmac-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <100000>; - enable-active-high; - gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; - }; - - reg_vcc3v3: vcc3v3 { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vdd_cpux: gpio-regulator { - compatible = "regulator-gpio"; - regulator-name = "vdd-cpux"; - regulator-type = "voltage"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1300000>; - regulator-ramp-delay = <50>; /* 4ms */ - gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; - gpios-states = <0x1>; - states = <1100000 0>, <1300000 1>; - }; - - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ - post-power-on-delay-ms = <200>; - }; -}; - -&codec { - allwinner,audio-routing = - "Line Out", "LINEOUT", - "MIC1", "Mic", - "Mic", "MBIAS"; - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci3 { - status = "okay"; -}; - -&emac { - pinctrl-names = "default"; - pinctrl-0 = <&emac_rgmii_pins>; - phy-supply = <®_gmac_3v3>; - phy-handle = <&ext_rgmii_phy>; - phy-mode = "rgmii"; - status = "okay"; -}; - -&external_mdio { - ext_rgmii_phy: ethernet-phy@7 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <7>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ - status = "okay"; -}; - -&mmc1 { - vmmc-supply = <®_vcc3v3>; - vqmmc-supply = <®_vcc3v3>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - }; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_8bit_pins>; - vmmc-supply = <®_vcc3v3>; - bus-width = <8>; - non-removable; - cap-mmc-hw-reset; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci3 { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pa_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "host"; - status = "okay"; -}; - -&usbphy { - /* USB Type-A ports' VBUS is always on */ - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/allwinner/sun50i-h5-nanopi-neo2.dts b/sys/gnu/dts/arm64/allwinner/sun50i-h5-nanopi-neo2.dts deleted file mode 100644 index b059e20813b..00000000000 --- a/sys/gnu/dts/arm64/allwinner/sun50i-h5-nanopi-neo2.dts +++ /dev/null @@ -1,120 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (C) 2017 Icenowy Zheng - -/dts-v1/; -#include "sun50i-h5.dtsi" - -#include - -/ { - model = "FriendlyARM NanoPi NEO 2"; - compatible = "friendlyarm,nanopi-neo2", "allwinner,sun50i-h5"; - - aliases { - ethernet0 = &emac; - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - pwr { - label = "nanopi:green:pwr"; - gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - status { - label = "nanopi:blue:status"; - gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>; - }; - }; - - reg_gmac_3v3: gmac-3v3 { - compatible = "regulator-fixed"; - regulator-name = "gmac-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <100000>; - enable-active-high; - gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; - }; - - reg_vcc3v3: vcc3v3 { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_usb0_vbus: usb0-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb0-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */ - status = "okay"; - }; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci3 { - status = "okay"; -}; - -&emac { - pinctrl-names = "default"; - pinctrl-0 = <&emac_rgmii_pins>; - phy-supply = <®_gmac_3v3>; - phy-handle = <&ext_rgmii_phy>; - phy-mode = "rgmii"; - status = "okay"; -}; - -&external_mdio { - ext_rgmii_phy: ethernet-phy@7 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <7>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci3 { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pa_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - /* USB Type-A port's VBUS is always on */ - usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ - usb0_vbus-supply = <®_usb0_vbus>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/allwinner/sun50i-h5-orangepi-pc2.dts b/sys/gnu/dts/arm64/allwinner/sun50i-h5-orangepi-pc2.dts deleted file mode 100644 index 70b5f099842..00000000000 --- a/sys/gnu/dts/arm64/allwinner/sun50i-h5-orangepi-pc2.dts +++ /dev/null @@ -1,211 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (C) 2016 ARM Ltd. - -/dts-v1/; -#include "sun50i-h5.dtsi" - -#include -#include -#include - -/ { - model = "Xunlong Orange Pi PC 2"; - compatible = "xunlong,orangepi-pc2", "allwinner,sun50i-h5"; - - reg_vcc3v3: vcc3v3 { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - aliases { - ethernet0 = &emac; - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - pwr { - label = "orangepi:green:pwr"; - gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - status { - label = "orangepi:red:status"; - gpios = <&pio 0 20 GPIO_ACTIVE_HIGH>; - }; - }; - - r-gpio-keys { - compatible = "gpio-keys"; - - sw4 { - label = "sw4"; - linux,code = ; - gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; - }; - }; - - reg_gmac_3v3: gmac-3v3 { - compatible = "regulator-fixed"; - regulator-name = "gmac-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <100000>; - enable-active-high; - gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; - }; - - reg_usb0_vbus: usb0-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb0-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */ - status = "okay"; - }; -}; - -&codec { - allwinner,audio-routing = - "Line Out", "LINEOUT", - "MIC1", "Mic", - "Mic", "MBIAS"; - status = "okay"; -}; - -&de { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&ehci2 { - status = "okay"; -}; - -&ehci3 { - status = "okay"; -}; - -&emac { - pinctrl-names = "default"; - pinctrl-0 = <&emac_rgmii_pins>; - phy-supply = <®_gmac_3v3>; - phy-handle = <&ext_rgmii_phy>; - phy-mode = "rgmii"; - status = "okay"; -}; - -&external_mdio { - ext_rgmii_phy: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&ir { - pinctrl-names = "default"; - pinctrl-0 = <&r_ir_rx_pin>; - status = "okay"; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&ohci2 { - status = "okay"; -}; - -&ohci3 { - status = "okay"; -}; - -&spi0 { - status = "okay"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <40000000>; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pa_pins>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; - status = "disabled"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; - status = "disabled"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - /* USB Type-A ports' VBUS is always on */ - usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ - usb0_vbus-supply = <®_usb0_vbus>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/allwinner/sun50i-h5-orangepi-prime.dts b/sys/gnu/dts/arm64/allwinner/sun50i-h5-orangepi-prime.dts deleted file mode 100644 index cb44bfa5981..00000000000 --- a/sys/gnu/dts/arm64/allwinner/sun50i-h5-orangepi-prime.dts +++ /dev/null @@ -1,213 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (C) 2017 Icenowy Zheng -// Based on sun50i-h5-orangepi-pc2.dts, which is: -// Copyright (C) 2016 ARM Ltd. - -/dts-v1/; -#include "sun50i-h5.dtsi" - -#include -#include - -/ { - model = "Xunlong Orange Pi Prime"; - compatible = "xunlong,orangepi-prime", "allwinner,sun50i-h5"; - - aliases { - ethernet0 = &emac; - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - pwr { - label = "orangepi:green:pwr"; - gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - status { - label = "orangepi:red:status"; - gpios = <&pio 0 20 GPIO_ACTIVE_HIGH>; - }; - }; - - r-gpio-keys { - compatible = "gpio-keys"; - - sw4 { - label = "sw4"; - linux,code = ; - gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; - }; - }; - - reg_gmac_3v3: gmac-3v3 { - compatible = "regulator-fixed"; - regulator-name = "gmac-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <100000>; - enable-active-high; - gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; - }; - - reg_vcc3v3: vcc3v3 { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_usb0_vbus: usb0-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb0-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */ - status = "okay"; - }; - - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&pio 2 14 GPIO_ACTIVE_LOW>; /* PC14 */ - }; -}; - -&codec { - allwinner,audio-routing = - "Line Out", "LINEOUT", - "MIC1", "Mic", - "Mic", "MBIAS"; - status = "okay"; -}; - -&de { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&ehci2 { - status = "okay"; -}; - -&ehci3 { - status = "okay"; -}; - -&emac { - pinctrl-names = "default"; - pinctrl-0 = <&emac_rgmii_pins>; - phy-supply = <®_gmac_3v3>; - phy-handle = <&ext_rgmii_phy>; - phy-mode = "rgmii"; - status = "okay"; -}; - -&external_mdio { - ext_rgmii_phy: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&ir { - pinctrl-names = "default"; - pinctrl-0 = <&r_ir_rx_pin>; - status = "okay"; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ - status = "okay"; -}; - -&mmc1 { - vmmc-supply = <®_vcc3v3>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&ohci2 { - status = "okay"; -}; - -&ohci3 { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pa_pins>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; - status = "disabled"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; - status = "disabled"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - /* USB Type-A ports' VBUS is always on */ - usb0_id_det-gpios = <&pio 0 21 GPIO_ACTIVE_HIGH>; /* PA21 */ - usb0_vbus-supply = <®_usb0_vbus>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/allwinner/sun50i-h5-orangepi-zero-plus.dts b/sys/gnu/dts/arm64/allwinner/sun50i-h5-orangepi-zero-plus.dts deleted file mode 100644 index ef5ca644422..00000000000 --- a/sys/gnu/dts/arm64/allwinner/sun50i-h5-orangepi-zero-plus.dts +++ /dev/null @@ -1,140 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (C) 2016 ARM Ltd. -// Copyright (C) 2018 Hauke Mehrtens - -/dts-v1/; -#include "sun50i-h5.dtsi" - -#include -#include -#include - -/ { - model = "Xunlong Orange Pi Zero Plus"; - compatible = "xunlong,orangepi-zero-plus", "allwinner,sun50i-h5"; - - reg_vcc3v3: vcc3v3 { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - aliases { - ethernet0 = &emac; - ethernet1 = &rtl8189ftv; - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - pwr { - label = "orangepi:green:pwr"; - gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PA10 */ - default-state = "on"; - }; - - status { - label = "orangepi:red:status"; - gpios = <&pio 0 17 GPIO_ACTIVE_HIGH>; /* PA17 */ - }; - }; - - reg_gmac_3v3: gmac-3v3 { - compatible = "regulator-fixed"; - regulator-name = "gmac-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <100000>; - enable-active-high; - gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */ - }; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&emac { - pinctrl-names = "default"; - pinctrl-0 = <&emac_rgmii_pins>; - phy-supply = <®_gmac_3v3>; - phy-handle = <&ext_rgmii_phy>; - phy-mode = "rgmii"; - status = "okay"; -}; - -&external_mdio { - ext_rgmii_phy: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ - status = "okay"; -}; - -&mmc1 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - non-removable; - status = "okay"; - - /* - * Explicitly define the sdio device, so that we can add an ethernet - * alias for it (which e.g. makes u-boot set a mac-address). - */ - rtl8189ftv: sdio_wifi@1 { - reg = <1>; - }; -}; - -&spi0 { - status = "okay"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "mxicy,mx25l1606e", "winbond,w25q128"; - reg = <0>; - spi-max-frequency = <40000000>; - }; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pa_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "peripheral"; - status = "okay"; -}; - -&usbphy { - /* USB Type-A ports' VBUS is always on */ - usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/allwinner/sun50i-h5-orangepi-zero-plus2.dts b/sys/gnu/dts/arm64/allwinner/sun50i-h5-orangepi-zero-plus2.dts deleted file mode 100644 index c95a6854130..00000000000 --- a/sys/gnu/dts/arm64/allwinner/sun50i-h5-orangepi-zero-plus2.dts +++ /dev/null @@ -1,105 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (C) 2017 Jagan Teki - -/dts-v1/; - -#include "sun50i-h5.dtsi" - -#include - -/ { - model = "OrangePi Zero Plus2"; - compatible = "xunlong,orangepi-zero-plus2", "allwinner,sun50i-h5"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - reg_vcc3v3: vcc3v3 { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&pio 0 9 GPIO_ACTIVE_LOW>; /* PA9 */ - post-power-on-delay-ms = <200>; - }; -}; - -&de { - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&mmc1 { - vmmc-supply = <®_vcc3v3>; - vqmmc-supply = <®_vcc3v3>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - interrupt-parent = <&r_pio>; - interrupts = <0 7 IRQ_TYPE_LEVEL_LOW>; /* PL7 */ - interrupt-names = "host-wake"; - }; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_8bit_pins>; - vmmc-supply = <®_vcc3v3>; - bus-width = <8>; - non-removable; - cap-mmc-hw-reset; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pa_pins>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/allwinner/sun50i-h5.dtsi b/sys/gnu/dts/arm64/allwinner/sun50i-h5.dtsi deleted file mode 100644 index 9893aa64dd0..00000000000 --- a/sys/gnu/dts/arm64/allwinner/sun50i-h5.dtsi +++ /dev/null @@ -1,221 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (C) 2016 ARM Ltd. - -#include - -/ { - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <0>; - enable-method = "psci"; - }; - - cpu1: cpu@1 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <1>; - enable-method = "psci"; - }; - - cpu2: cpu@2 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <2>; - enable-method = "psci"; - }; - - cpu3: cpu@3 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <3>; - enable-method = "psci"; - }; - }; - - pmu { - compatible = "arm,cortex-a53-pmu", - "arm,armv8-pmuv3"; - interrupts = , - , - , - ; - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - soc { - syscon: system-control@1c00000 { - compatible = "allwinner,sun50i-h5-system-control"; - reg = <0x01c00000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - sram_c1: sram@18000 { - compatible = "mmio-sram"; - reg = <0x00018000 0x1c000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x00018000 0x1c000>; - - ve_sram: sram-section@0 { - compatible = "allwinner,sun50i-h5-sram-c1", - "allwinner,sun4i-a10-sram-c1"; - reg = <0x000000 0x1c000>; - }; - }; - }; - - video-codec@1c0e000 { - compatible = "allwinner,sun50i-h5-video-engine"; - reg = <0x01c0e000 0x1000>; - clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, - <&ccu CLK_DRAM_VE>; - clock-names = "ahb", "mod", "ram"; - resets = <&ccu RST_BUS_VE>; - interrupts = ; - allwinner,sram = <&ve_sram 1>; - }; - - crypto: crypto@1c15000 { - compatible = "allwinner,sun50i-h5-crypto"; - reg = <0x01c15000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>; - clock-names = "bus", "mod"; - resets = <&ccu RST_BUS_CE>; - }; - - mali: gpu@1e80000 { - compatible = "allwinner,sun50i-h5-mali", "arm,mali-450"; - reg = <0x01e80000 0x30000>; - /* - * While the datasheet lists an interrupt for the - * PMU, the actual silicon does not have the PMU - * block. Reads all return zero, and writes are - * ignored. - */ - interrupts = , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "gp", - "gpmmu", - "pp", - "pp0", - "ppmmu0", - "pp1", - "ppmmu1", - "pp2", - "ppmmu2", - "pp3", - "ppmmu3", - "pmu"; - clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>; - clock-names = "bus", "core"; - resets = <&ccu RST_BUS_GPU>; - - assigned-clocks = <&ccu CLK_GPU>; - assigned-clock-rates = <384000000>; - }; - - ths: thermal-sensor@1c25000 { - compatible = "allwinner,sun50i-h5-ths"; - reg = <0x01c25000 0x400>; - interrupts = ; - resets = <&ccu RST_BUS_THS>; - clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>; - clock-names = "bus", "mod"; - nvmem-cells = <&ths_calibration>; - nvmem-cell-names = "calibration"; - #thermal-sensor-cells = <1>; - }; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&ths 0>; - }; - - gpu_thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&ths 1>; - }; - }; -}; - -&ccu { - compatible = "allwinner,sun50i-h5-ccu"; -}; - -&display_clocks { - compatible = "allwinner,sun50i-h5-de2-clk"; -}; - -&mmc0 { - compatible = "allwinner,sun50i-h5-mmc", - "allwinner,sun50i-a64-mmc"; - clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; - clock-names = "ahb", "mmc"; -}; - -&mmc1 { - compatible = "allwinner,sun50i-h5-mmc", - "allwinner,sun50i-a64-mmc"; - clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; - clock-names = "ahb", "mmc"; -}; - -&mmc2 { - compatible = "allwinner,sun50i-h5-emmc", - "allwinner,sun50i-a64-emmc"; - clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; - clock-names = "ahb", "mmc"; -}; - -&pio { - interrupts = , - , - ; - compatible = "allwinner,sun50i-h5-pinctrl"; -}; - -&rtc { - compatible = "allwinner,sun50i-h5-rtc"; -}; - -&sid { - compatible = "allwinner,sun50i-h5-sid"; -}; diff --git a/sys/gnu/dts/arm64/allwinner/sun50i-h6-beelink-gs1.dts b/sys/gnu/dts/arm64/allwinner/sun50i-h6-beelink-gs1.dts deleted file mode 100644 index df6d872c34e..00000000000 --- a/sys/gnu/dts/arm64/allwinner/sun50i-h6-beelink-gs1.dts +++ /dev/null @@ -1,300 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (C) 2019 Clément Péron - -/dts-v1/; - -#include "sun50i-h6.dtsi" - -#include - -/ { - model = "Beelink GS1"; - compatible = "azw,beelink-gs1", "allwinner,sun50i-h6"; - - aliases { - ethernet0 = &emac; - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - connector { - compatible = "hdmi-connector"; - type = "a"; - ddc-en-gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */ - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - power { - label = "beelink:white:power"; - gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */ - default-state = "on"; - }; - }; - - reg_vcc5v: vcc5v { - /* board wide 5V supply directly from the DC jack */ - compatible = "regulator-fixed"; - regulator-name = "vcc-5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - sound-spdif { - compatible = "simple-audio-card"; - simple-audio-card,name = "sun50i-h6-spdif"; - - simple-audio-card,cpu { - sound-dai = <&spdif>; - }; - - simple-audio-card,codec { - sound-dai = <&spdif_out>; - }; - }; - - spdif_out: spdif-out { - #sound-dai-cells = <0>; - compatible = "linux,spdif-dit"; - }; -}; - -&de { - status = "okay"; -}; - -&dwc3 { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&emac { - pinctrl-names = "default"; - pinctrl-0 = <&ext_rgmii_pins>; - phy-mode = "rgmii"; - phy-handle = <&ext_rgmii_phy>; - phy-supply = <®_aldo2>; - status = "okay"; -}; - -&gpu { - mali-supply = <®_dcdcc>; - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&mdio { - ext_rgmii_phy: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; -}; - -&mmc0 { - vmmc-supply = <®_cldo1>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; - bus-width = <4>; - status = "okay"; -}; - -&mmc2 { - vmmc-supply = <®_cldo1>; - vqmmc-supply = <®_bldo2>; - non-removable; - cap-mmc-hw-reset; - bus-width = <8>; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&pio { - vcc-pd-supply = <®_cldo1>; - vcc-pg-supply = <®_aldo1>; -}; - -&r_i2c { - status = "okay"; - - axp805: pmic@36 { - compatible = "x-powers,axp805", "x-powers,axp806"; - reg = <0x36>; - interrupt-parent = <&r_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells = <1>; - x-powers,self-working-mode; - vina-supply = <®_vcc5v>; - vinb-supply = <®_vcc5v>; - vinc-supply = <®_vcc5v>; - vind-supply = <®_vcc5v>; - vine-supply = <®_vcc5v>; - aldoin-supply = <®_vcc5v>; - bldoin-supply = <®_vcc5v>; - cldoin-supply = <®_vcc5v>; - - regulators { - reg_aldo1: aldo1 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-pl"; - }; - - reg_aldo2: aldo2 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-ac200"; - regulator-enable-ramp-delay = <100000>; - }; - - reg_aldo3: aldo3 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc25-dram"; - }; - - reg_bldo1: bldo1 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc-bias-pll"; - }; - - reg_bldo2: bldo2 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc-efuse-pcie-hdmi-io"; - }; - - reg_bldo3: bldo3 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc-dcxoio"; - }; - - bldo4 { - /* unused */ - }; - - reg_cldo1: cldo1 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-3v3"; - }; - - reg_cldo2: cldo2 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi-1"; - }; - - reg_cldo3: cldo3 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi-2"; - }; - - reg_dcdca: dcdca { - regulator-always-on; - regulator-min-microvolt = <810000>; - regulator-max-microvolt = <1080000>; - regulator-name = "vdd-cpu"; - }; - - reg_dcdcc: dcdcc { - regulator-enable-ramp-delay = <32000>; - regulator-min-microvolt = <810000>; - regulator-max-microvolt = <1080000>; - regulator-name = "vdd-gpu"; - }; - - reg_dcdcd: dcdcd { - regulator-always-on; - regulator-min-microvolt = <960000>; - regulator-max-microvolt = <960000>; - regulator-name = "vdd-sys"; - }; - - reg_dcdce: dcdce { - regulator-always-on; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-name = "vcc-dram"; - }; - - sw { - /* unused */ - }; - }; - }; -}; - -&r_ir { - linux,rc-map-name = "rc-beelink-gs1"; - status = "okay"; -}; - -&r_pio { - /* - * PL0 and PL1 are used for PMIC I2C - * don't enable the pl-supply else - * it will fail at boot - * - * vcc-pl-supply = <®_aldo1>; - */ - vcc-pm-supply = <®_aldo1>; -}; - -&spdif { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_ph_pins>; - status = "okay"; -}; - -&usb2otg { - dr_mode = "host"; - status = "okay"; -}; - -&usb2phy { - usb0_vbus-supply = <®_vcc5v>; - status = "okay"; -}; - -&usb3phy { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/allwinner/sun50i-h6-orangepi-3.dts b/sys/gnu/dts/arm64/allwinner/sun50i-h6-orangepi-3.dts deleted file mode 100644 index c311eee52a3..00000000000 --- a/sys/gnu/dts/arm64/allwinner/sun50i-h6-orangepi-3.dts +++ /dev/null @@ -1,322 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (C) 2019 Ondřej Jirman - -/dts-v1/; - -#include "sun50i-h6.dtsi" - -#include - -/ { - model = "OrangePi 3"; - compatible = "xunlong,orangepi-3", "allwinner,sun50i-h6"; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - connector { - compatible = "hdmi-connector"; - ddc-en-gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */ - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - power { - label = "orangepi:red:power"; - gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */ - default-state = "on"; - }; - - status { - label = "orangepi:green:status"; - gpios = <&r_pio 0 7 GPIO_ACTIVE_HIGH>; /* PL7 */ - }; - }; - - reg_vcc5v: vcc5v { - /* board wide 5V supply directly from the DC jack */ - compatible = "regulator-fixed"; - regulator-name = "vcc-5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - reg_vcc33_wifi: vcc33-wifi { - /* Always on 3.3V regulator for WiFi and BT */ - compatible = "regulator-fixed"; - regulator-name = "vcc33-wifi"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - vin-supply = <®_vcc5v>; - }; - - reg_vcc_wifi_io: vcc-wifi-io { - /* Always on 1.8V/300mA regulator for WiFi and BT IO */ - compatible = "regulator-fixed"; - regulator-name = "vcc-wifi-io"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - vin-supply = <®_vcc33_wifi>; - }; - - wifi_pwrseq: wifi-pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&rtc 1>; - clock-names = "ext_clock"; - reset-gpios = <&r_pio 1 3 GPIO_ACTIVE_LOW>; /* PM3 */ - post-power-on-delay-ms = <200>; - }; -}; - -&cpu0 { - cpu-supply = <®_dcdca>; -}; - -&de { - status = "okay"; -}; - -&dwc3 { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci3 { - status = "okay"; -}; - -&gpu { - mali-supply = <®_dcdcc>; - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&mmc0 { - vmmc-supply = <®_cldo1>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ - bus-width = <4>; - status = "okay"; -}; - -&mmc1 { - vmmc-supply = <®_vcc33_wifi>; - vqmmc-supply = <®_vcc_wifi_io>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; - - brcm: sdio-wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - interrupt-parent = <&r_pio>; - interrupts = <1 0 IRQ_TYPE_LEVEL_LOW>; /* PM0 */ - interrupt-names = "host-wake"; - }; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci3 { - status = "okay"; -}; - -&pio { - vcc-pc-supply = <®_bldo2>; - vcc-pd-supply = <®_cldo1>; - vcc-pg-supply = <®_vcc_wifi_io>; -}; - -&r_i2c { - status = "okay"; - - axp805: pmic@36 { - compatible = "x-powers,axp805", "x-powers,axp806"; - reg = <0x36>; - interrupt-parent = <&r_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells = <1>; - x-powers,self-working-mode; - vina-supply = <®_vcc5v>; - vinb-supply = <®_vcc5v>; - vinc-supply = <®_vcc5v>; - vind-supply = <®_vcc5v>; - vine-supply = <®_vcc5v>; - aldoin-supply = <®_vcc5v>; - bldoin-supply = <®_vcc5v>; - cldoin-supply = <®_vcc5v>; - - regulators { - reg_aldo1: aldo1 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-pl-led-ir"; - }; - - reg_aldo2: aldo2 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc33-audio-tv-ephy-mac"; - }; - - /* ALDO3 is shorted to CLDO1 */ - reg_aldo3: aldo3 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc33-io-pd-emmc-sd-usb-uart-1"; - }; - - reg_bldo1: bldo1 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc18-dram-bias-pll"; - }; - - reg_bldo2: bldo2 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc-efuse-pcie-hdmi-pc"; - }; - - bldo3 { - /* unused */ - }; - - bldo4 { - /* unused */ - }; - - reg_cldo1: cldo1 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc33-io-pd-emmc-sd-usb-uart-2"; - }; - - cldo2 { - /* unused */ - }; - - cldo3 { - /* unused */ - }; - - reg_dcdca: dcdca { - regulator-always-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1160000>; - regulator-name = "vdd-cpu"; - }; - - reg_dcdcc: dcdcc { - regulator-enable-ramp-delay = <32000>; - regulator-min-microvolt = <810000>; - regulator-max-microvolt = <1080000>; - regulator-name = "vdd-gpu"; - }; - - reg_dcdcd: dcdcd { - regulator-always-on; - regulator-min-microvolt = <960000>; - regulator-max-microvolt = <960000>; - regulator-name = "vdd-sys"; - }; - - reg_dcdce: dcdce { - regulator-always-on; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-name = "vcc-dram"; - }; - - sw { - /* unused */ - }; - }; - }; -}; - -&r_ir { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_ph_pins>; - status = "okay"; -}; - -/* There's the BT part of the AP6256 connected to that UART */ -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; - uart-has-rtscts; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm4345c5"; - clocks = <&rtc 1>; - clock-names = "lpo"; - device-wakeup-gpios = <&r_pio 1 2 GPIO_ACTIVE_HIGH>; /* PM2 */ - host-wakeup-gpios = <&r_pio 1 1 GPIO_ACTIVE_HIGH>; /* PM1 */ - shutdown-gpios = <&r_pio 1 4 GPIO_ACTIVE_HIGH>; /* PM4 */ - max-speed = <1500000>; - }; -}; - -&usb2otg { - /* - * This board doesn't have a controllable VBUS even though it - * does have an ID pin. Using it as anything but a USB host is - * unsafe. - */ - dr_mode = "host"; - status = "okay"; -}; - -&usb2phy { - usb0_id_det-gpios = <&pio 2 15 GPIO_ACTIVE_HIGH>; /* PC15 */ - usb0_vbus-supply = <®_vcc5v>; - usb3_vbus-supply = <®_vcc5v>; - status = "okay"; -}; - -&usb3phy { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/allwinner/sun50i-h6-orangepi-lite2.dts b/sys/gnu/dts/arm64/allwinner/sun50i-h6-orangepi-lite2.dts deleted file mode 100644 index e7ca75c0d0f..00000000000 --- a/sys/gnu/dts/arm64/allwinner/sun50i-h6-orangepi-lite2.dts +++ /dev/null @@ -1,9 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (C) 2018 Jagan Teki - -#include "sun50i-h6-orangepi.dtsi" - -/ { - model = "OrangePi Lite2"; - compatible = "xunlong,orangepi-lite2", "allwinner,sun50i-h6"; -}; diff --git a/sys/gnu/dts/arm64/allwinner/sun50i-h6-orangepi-one-plus.dts b/sys/gnu/dts/arm64/allwinner/sun50i-h6-orangepi-one-plus.dts deleted file mode 100644 index 83aab736888..00000000000 --- a/sys/gnu/dts/arm64/allwinner/sun50i-h6-orangepi-one-plus.dts +++ /dev/null @@ -1,10 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (C) 2018 Amarula Solutions -// Author: Jagan Teki - -#include "sun50i-h6-orangepi.dtsi" - -/ { - model = "OrangePi One Plus"; - compatible = "xunlong,orangepi-one-plus", "allwinner,sun50i-h6"; -}; diff --git a/sys/gnu/dts/arm64/allwinner/sun50i-h6-orangepi.dtsi b/sys/gnu/dts/arm64/allwinner/sun50i-h6-orangepi.dtsi deleted file mode 100644 index 37f4c57597d..00000000000 --- a/sys/gnu/dts/arm64/allwinner/sun50i-h6-orangepi.dtsi +++ /dev/null @@ -1,216 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (C) 2018 Amarula Solutions -// Author: Jagan Teki - -/dts-v1/; - -#include "sun50i-h6.dtsi" - -#include - -/ { - model = "OrangePi One Plus"; - compatible = "xunlong,orangepi-one-plus", "allwinner,sun50i-h6"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - power { - label = "orangepi:red:power"; - gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */ - default-state = "on"; - }; - - status { - label = "orangepi:green:status"; - gpios = <&r_pio 0 7 GPIO_ACTIVE_HIGH>; /* PL7 */ - }; - }; - - reg_vcc5v: vcc5v { - /* board wide 5V supply directly from the DC jack */ - compatible = "regulator-fixed"; - regulator-name = "vcc-5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci3 { - status = "okay"; -}; - -&gpu { - mali-supply = <®_dcdcc>; - status = "okay"; -}; - -&mmc0 { - vmmc-supply = <®_cldo1>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; - bus-width = <4>; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci3 { - status = "okay"; -}; - -&r_i2c { - status = "okay"; - - axp805: pmic@36 { - compatible = "x-powers,axp805", "x-powers,axp806"; - reg = <0x36>; - interrupt-parent = <&r_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells = <1>; - x-powers,self-working-mode; - vina-supply = <®_vcc5v>; - vinb-supply = <®_vcc5v>; - vinc-supply = <®_vcc5v>; - vind-supply = <®_vcc5v>; - vine-supply = <®_vcc5v>; - aldoin-supply = <®_vcc5v>; - bldoin-supply = <®_vcc5v>; - cldoin-supply = <®_vcc5v>; - - regulators { - reg_aldo1: aldo1 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-pl"; - }; - - reg_aldo2: aldo2 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-ac200"; - }; - - reg_aldo3: aldo3 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc25-dram"; - }; - - reg_bldo1: bldo1 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc-bias-pll"; - }; - - reg_bldo2: bldo2 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc-efuse-pcie-hdmi-io"; - }; - - reg_bldo3: bldo3 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc-dcxoio"; - }; - - bldo4 { - /* unused */ - }; - - reg_cldo1: cldo1 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-3v3"; - }; - - reg_cldo2: cldo2 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi-1"; - }; - - reg_cldo3: cldo3 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi-2"; - }; - - reg_dcdca: dcdca { - regulator-always-on; - regulator-min-microvolt = <810000>; - regulator-max-microvolt = <1080000>; - regulator-name = "vdd-cpu"; - }; - - reg_dcdcc: dcdcc { - regulator-enable-ramp-delay = <32000>; - regulator-min-microvolt = <810000>; - regulator-max-microvolt = <1080000>; - regulator-name = "vdd-gpu"; - }; - - reg_dcdcd: dcdcd { - regulator-always-on; - regulator-min-microvolt = <960000>; - regulator-max-microvolt = <960000>; - regulator-name = "vdd-sys"; - }; - - reg_dcdce: dcdce { - regulator-always-on; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-name = "vcc-dram"; - }; - - sw { - /* unused */ - }; - }; - }; -}; - -&r_ir { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_ph_pins>; - status = "okay"; -}; - -&usb2otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usb2phy { - usb0_id_det-gpios = <&pio 2 6 GPIO_ACTIVE_HIGH>; /* PC6 */ - usb0_vbus-supply = <®_vcc5v>; - usb3_vbus-supply = <®_vcc5v>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/allwinner/sun50i-h6-pine-h64-model-b.dts b/sys/gnu/dts/arm64/allwinner/sun50i-h6-pine-h64-model-b.dts deleted file mode 100644 index f4c8966a649..00000000000 --- a/sys/gnu/dts/arm64/allwinner/sun50i-h6-pine-h64-model-b.dts +++ /dev/null @@ -1,21 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ or MIT) -/* - * Copyright (C) 2019 Corentin LABBE - */ - -#include "sun50i-h6-pine-h64.dts" - -/ { - model = "Pine H64 model B"; - compatible = "pine64,pine-h64-model-b", "allwinner,sun50i-h6"; - - /delete-node/ reg_gmac_3v3; -}; - -&hdmi_connector { - /delete-property/ ddc-en-gpios; -}; - -&emac { - phy-supply = <®_aldo2>; -}; diff --git a/sys/gnu/dts/arm64/allwinner/sun50i-h6-pine-h64.dts b/sys/gnu/dts/arm64/allwinner/sun50i-h6-pine-h64.dts deleted file mode 100644 index d1c2aa5b3a2..00000000000 --- a/sys/gnu/dts/arm64/allwinner/sun50i-h6-pine-h64.dts +++ /dev/null @@ -1,296 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (c) 2017 Icenowy Zheng - -/dts-v1/; - -#include "sun50i-h6.dtsi" - -#include - -/ { - model = "Pine H64 model A"; - compatible = "pine64,pine-h64", "allwinner,sun50i-h6"; - - aliases { - ethernet0 = &emac; - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - hdmi_connector: connector { - compatible = "hdmi-connector"; - type = "a"; - ddc-en-gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */ - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - heartbeat { - label = "pine-h64:green:heartbeat"; - gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */ - }; - - link { - label = "pine-h64:white:link"; - gpios = <&r_pio 0 3 GPIO_ACTIVE_HIGH>; /* PL3 */ - }; - - status { - label = "pine-h64:blue:status"; - gpios = <&r_pio 0 7 GPIO_ACTIVE_HIGH>; /* PL7 */ - }; - }; - - reg_gmac_3v3: gmac-3v3 { - compatible = "regulator-fixed"; - regulator-name = "vcc-gmac-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <100000>; - gpio = <&pio 2 16 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usb_vbus: vbus { - compatible = "regulator-fixed"; - regulator-name = "usb-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - startup-delay-us = <100000>; - gpio = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&emac { - pinctrl-names = "default"; - pinctrl-0 = <&ext_rgmii_pins>; - phy-mode = "rgmii"; - phy-handle = <&ext_rgmii_phy>; - phy-supply = <®_gmac_3v3>; - allwinner,rx-delay-ps = <200>; - allwinner,tx-delay-ps = <200>; - status = "okay"; -}; - -&mdio { - ext_rgmii_phy: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; -}; - -&de { - status = "okay"; -}; - -&gpu { - mali-supply = <®_dcdcc>; - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci3 { - status = "okay"; -}; - -&mmc0 { - vmmc-supply = <®_cldo1>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; - bus-width = <4>; - status = "okay"; -}; - -&mmc2 { - vmmc-supply = <®_cldo1>; - vqmmc-supply = <®_bldo2>; - non-removable; - cap-mmc-hw-reset; - bus-width = <8>; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci3 { - status = "okay"; -}; - -&pio { - vcc-pc-supply = <®_bldo2>; - vcc-pd-supply = <®_cldo1>; - vcc-pg-supply = <®_aldo1>; -}; - -&r_i2c { - status = "okay"; - - axp805: pmic@36 { - compatible = "x-powers,axp805", "x-powers,axp806"; - reg = <0x36>; - interrupt-parent = <&r_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells = <1>; - x-powers,self-working-mode; - - regulators { - reg_aldo1: aldo1 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-pl"; - }; - - reg_aldo2: aldo2 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-ac200"; - regulator-enable-ramp-delay = <100000>; - }; - - reg_aldo3: aldo3 { - /* This regulator is connected with CLDO1 */ - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-3v3-1"; - }; - - reg_bldo1: bldo1 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc-bias-pll"; - }; - - reg_bldo2: bldo2 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc-efuse-pcie-hdmi-io"; - }; - - reg_bldo3: bldo3 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc-dcxoio"; - }; - - bldo4 { - /* unused */ - }; - - reg_cldo1: cldo1 { - /* This regulator is connected with ALDO3 */ - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-3v3-2"; - }; - - reg_cldo2: cldo2 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi-1"; - }; - - reg_cldo3: cldo3 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi-2"; - }; - - reg_dcdca: dcdca { - regulator-always-on; - regulator-min-microvolt = <810000>; - regulator-max-microvolt = <1080000>; - regulator-name = "vdd-cpu"; - }; - - reg_dcdcc: dcdcc { - regulator-enable-ramp-delay = <32000>; - regulator-min-microvolt = <810000>; - regulator-max-microvolt = <1080000>; - regulator-name = "vdd-gpu"; - }; - - reg_dcdcd: dcdcd { - regulator-always-on; - regulator-min-microvolt = <960000>; - regulator-max-microvolt = <960000>; - regulator-name = "vdd-sys"; - }; - - reg_dcdce: dcdce { - regulator-always-on; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-name = "vcc-dram"; - }; - - sw { - /* unused */ - }; - }; - }; - - pcf8563: rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - interrupt-parent = <&r_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - #clock-cells = <0>; - }; -}; - -&r_ir { - status = "okay"; -}; - -&r_pio { - vcc-pm-supply = <®_aldo1>; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_ph_pins>; - status = "okay"; -}; - -&usb2otg { - dr_mode = "host"; - status = "okay"; -}; - -&usb2phy { - usb0_vbus-supply = <®_usb_vbus>; - usb3_vbus-supply = <®_usb_vbus>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/allwinner/sun50i-h6-tanix-tx6.dts b/sys/gnu/dts/arm64/allwinner/sun50i-h6-tanix-tx6.dts deleted file mode 100644 index 83e6cb0e59c..00000000000 --- a/sys/gnu/dts/arm64/allwinner/sun50i-h6-tanix-tx6.dts +++ /dev/null @@ -1,111 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (c) 2019 Jernej Skrabec - -/dts-v1/; - -#include "sun50i-h6.dtsi" - -#include - -/ { - model = "Tanix TX6"; - compatible = "oranth,tanix-tx6", "allwinner,sun50i-h6"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - connector { - compatible = "hdmi-connector"; - ddc-en-gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */ - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - reg_vcc3v3: vcc3v3 { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&de { - status = "okay"; -}; - -&dwc3 { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci3 { - status = "okay"; -}; - -&gpu { - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; - vmmc-supply = <®_vcc3v3>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; - bus-width = <4>; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci3 { - status = "okay"; -}; - -&r_ir { - linux,rc-map-name = "rc-tanix-tx5max"; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_ph_pins>; - status = "okay"; -}; - -&usb2otg { - dr_mode = "host"; - status = "okay"; -}; - -&usb2phy { - status = "okay"; -}; - -&usb3phy { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/allwinner/sun50i-h6.dtsi b/sys/gnu/dts/arm64/allwinner/sun50i-h6.dtsi deleted file mode 100644 index 3329283e38a..00000000000 --- a/sys/gnu/dts/arm64/allwinner/sun50i-h6.dtsi +++ /dev/null @@ -1,911 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (C) 2017 Icenowy Zheng - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/ { - interrupt-parent = <&gic>; - #address-cells = <1>; - #size-cells = <1>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <0>; - enable-method = "psci"; - }; - - cpu1: cpu@1 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <1>; - enable-method = "psci"; - }; - - cpu2: cpu@2 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <2>; - enable-method = "psci"; - }; - - cpu3: cpu@3 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <3>; - enable-method = "psci"; - }; - }; - - de: display-engine { - compatible = "allwinner,sun50i-h6-display-engine"; - allwinner,pipelines = <&mixer0>; - status = "disabled"; - }; - - osc24M: osc24M_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "osc24M"; - }; - - ext_osc32k: ext_osc32k_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - clock-output-names = "ext_osc32k"; - }; - - pmu { - compatible = "arm,cortex-a53-pmu", - "arm,armv8-pmuv3"; - interrupts = , - , - , - ; - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - bus@1000000 { - compatible = "allwinner,sun50i-h6-de3", - "allwinner,sun50i-a64-de2"; - reg = <0x1000000 0x400000>; - allwinner,sram = <&de2_sram 1>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1000000 0x400000>; - - display_clocks: clock@0 { - compatible = "allwinner,sun50i-h6-de3-clk"; - reg = <0x0 0x10000>; - clocks = <&ccu CLK_DE>, - <&ccu CLK_BUS_DE>; - clock-names = "mod", - "bus"; - resets = <&ccu RST_BUS_DE>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - mixer0: mixer@100000 { - compatible = "allwinner,sun50i-h6-de3-mixer-0"; - reg = <0x100000 0x100000>; - clocks = <&display_clocks CLK_BUS_MIXER0>, - <&display_clocks CLK_MIXER0>; - clock-names = "bus", - "mod"; - resets = <&display_clocks RST_MIXER0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - mixer0_out: port@1 { - reg = <1>; - - mixer0_out_tcon_top_mixer0: endpoint { - remote-endpoint = <&tcon_top_mixer0_in_mixer0>; - }; - }; - }; - }; - }; - - video-codec@1c0e000 { - compatible = "allwinner,sun50i-h6-video-engine"; - reg = <0x01c0e000 0x2000>; - clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, - <&ccu CLK_MBUS_VE>; - clock-names = "ahb", "mod", "ram"; - resets = <&ccu RST_BUS_VE>; - interrupts = ; - allwinner,sram = <&ve_sram 1>; - }; - - gpu: gpu@1800000 { - compatible = "allwinner,sun50i-h6-mali", - "arm,mali-t720"; - reg = <0x01800000 0x4000>; - interrupts = , - , - ; - interrupt-names = "job", "mmu", "gpu"; - clocks = <&ccu CLK_GPU>, <&ccu CLK_BUS_GPU>; - clock-names = "core", "bus"; - resets = <&ccu RST_BUS_GPU>; - status = "disabled"; - }; - - crypto: crypto@1904000 { - compatible = "allwinner,sun50i-h6-crypto"; - reg = <0x01904000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>, <&ccu CLK_MBUS_CE>; - clock-names = "bus", "mod", "ram"; - resets = <&ccu RST_BUS_CE>; - }; - - syscon: syscon@3000000 { - compatible = "allwinner,sun50i-h6-system-control", - "allwinner,sun50i-a64-system-control"; - reg = <0x03000000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - sram_c: sram@28000 { - compatible = "mmio-sram"; - reg = <0x00028000 0x1e000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x00028000 0x1e000>; - - de2_sram: sram-section@0 { - compatible = "allwinner,sun50i-h6-sram-c", - "allwinner,sun50i-a64-sram-c"; - reg = <0x0000 0x1e000>; - }; - }; - - sram_c1: sram@1a00000 { - compatible = "mmio-sram"; - reg = <0x01a00000 0x200000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x01a00000 0x200000>; - - ve_sram: sram-section@0 { - compatible = "allwinner,sun50i-h6-sram-c1", - "allwinner,sun4i-a10-sram-c1"; - reg = <0x000000 0x200000>; - }; - }; - }; - - ccu: clock@3001000 { - compatible = "allwinner,sun50i-h6-ccu"; - reg = <0x03001000 0x1000>; - clocks = <&osc24M>, <&rtc 0>, <&rtc 2>; - clock-names = "hosc", "losc", "iosc"; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - dma: dma-controller@3002000 { - compatible = "allwinner,sun50i-h6-dma"; - reg = <0x03002000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>; - clock-names = "bus", "mbus"; - dma-channels = <16>; - dma-requests = <46>; - resets = <&ccu RST_BUS_DMA>; - #dma-cells = <1>; - }; - - sid: efuse@3006000 { - compatible = "allwinner,sun50i-h6-sid"; - reg = <0x03006000 0x400>; - #address-cells = <1>; - #size-cells = <1>; - - ths_calibration: thermal-sensor-calibration@14 { - reg = <0x14 0x8>; - }; - }; - - watchdog: watchdog@30090a0 { - compatible = "allwinner,sun50i-h6-wdt", - "allwinner,sun6i-a31-wdt"; - reg = <0x030090a0 0x20>; - interrupts = ; - clocks = <&osc24M>; - /* Broken on some H6 boards */ - status = "disabled"; - }; - - pwm: pwm@300a000 { - compatible = "allwinner,sun50i-h6-pwm"; - reg = <0x0300a000 0x400>; - clocks = <&osc24M>, <&ccu CLK_BUS_PWM>; - clock-names = "mod", "bus"; - resets = <&ccu RST_BUS_PWM>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pio: pinctrl@300b000 { - compatible = "allwinner,sun50i-h6-pinctrl"; - reg = <0x0300b000 0x400>; - interrupts = , - , - , - ; - clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc 0>; - clock-names = "apb", "hosc", "losc"; - gpio-controller; - #gpio-cells = <3>; - interrupt-controller; - #interrupt-cells = <3>; - - ext_rgmii_pins: rgmii-pins { - pins = "PD0", "PD1", "PD2", "PD3", "PD4", - "PD5", "PD7", "PD8", "PD9", "PD10", - "PD11", "PD12", "PD13", "PD19", "PD20"; - function = "emac"; - drive-strength = <40>; - }; - - hdmi_pins: hdmi-pins { - pins = "PH8", "PH9", "PH10"; - function = "hdmi"; - }; - - i2c0_pins: i2c0-pins { - pins = "PD25", "PD26"; - function = "i2c0"; - }; - - i2c1_pins: i2c1-pins { - pins = "PH5", "PH6"; - function = "i2c1"; - }; - - i2c2_pins: i2c2-pins { - pins = "PD23", "PD24"; - function = "i2c2"; - }; - - mmc0_pins: mmc0-pins { - pins = "PF0", "PF1", "PF2", "PF3", - "PF4", "PF5"; - function = "mmc0"; - drive-strength = <30>; - bias-pull-up; - }; - - /omit-if-no-ref/ - mmc1_pins: mmc1-pins { - pins = "PG0", "PG1", "PG2", "PG3", - "PG4", "PG5"; - function = "mmc1"; - drive-strength = <30>; - bias-pull-up; - }; - - mmc2_pins: mmc2-pins { - pins = "PC1", "PC4", "PC5", "PC6", - "PC7", "PC8", "PC9", "PC10", - "PC11", "PC12", "PC13", "PC14"; - function = "mmc2"; - drive-strength = <30>; - bias-pull-up; - }; - - spdif_tx_pin: spdif-tx-pin { - pins = "PH7"; - function = "spdif"; - }; - - uart0_ph_pins: uart0-ph-pins { - pins = "PH0", "PH1"; - function = "uart0"; - }; - - uart1_pins: uart1-pins { - pins = "PG6", "PG7"; - function = "uart1"; - }; - - uart1_rts_cts_pins: uart1-rts-cts-pins { - pins = "PG8", "PG9"; - function = "uart1"; - }; - }; - - gic: interrupt-controller@3021000 { - compatible = "arm,gic-400"; - reg = <0x03021000 0x1000>, - <0x03022000 0x2000>, - <0x03024000 0x2000>, - <0x03026000 0x2000>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <3>; - }; - - mmc0: mmc@4020000 { - compatible = "allwinner,sun50i-h6-mmc", - "allwinner,sun50i-a64-mmc"; - reg = <0x04020000 0x1000>; - clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; - clock-names = "ahb", "mmc"; - resets = <&ccu RST_BUS_MMC0>; - reset-names = "ahb"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc1: mmc@4021000 { - compatible = "allwinner,sun50i-h6-mmc", - "allwinner,sun50i-a64-mmc"; - reg = <0x04021000 0x1000>; - clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; - clock-names = "ahb", "mmc"; - resets = <&ccu RST_BUS_MMC1>; - reset-names = "ahb"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc2: mmc@4022000 { - compatible = "allwinner,sun50i-h6-emmc", - "allwinner,sun50i-a64-emmc"; - reg = <0x04022000 0x1000>; - clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; - clock-names = "ahb", "mmc"; - resets = <&ccu RST_BUS_MMC2>; - reset-names = "ahb"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - uart0: serial@5000000 { - compatible = "snps,dw-apb-uart"; - reg = <0x05000000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART0>; - resets = <&ccu RST_BUS_UART0>; - status = "disabled"; - }; - - uart1: serial@5000400 { - compatible = "snps,dw-apb-uart"; - reg = <0x05000400 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART1>; - resets = <&ccu RST_BUS_UART1>; - status = "disabled"; - }; - - uart2: serial@5000800 { - compatible = "snps,dw-apb-uart"; - reg = <0x05000800 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART2>; - resets = <&ccu RST_BUS_UART2>; - status = "disabled"; - }; - - uart3: serial@5000c00 { - compatible = "snps,dw-apb-uart"; - reg = <0x05000c00 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART3>; - resets = <&ccu RST_BUS_UART3>; - status = "disabled"; - }; - - i2c0: i2c@5002000 { - compatible = "allwinner,sun50i-h6-i2c", - "allwinner,sun6i-a31-i2c"; - reg = <0x05002000 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_I2C0>; - resets = <&ccu RST_BUS_I2C0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c1: i2c@5002400 { - compatible = "allwinner,sun50i-h6-i2c", - "allwinner,sun6i-a31-i2c"; - reg = <0x05002400 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_I2C1>; - resets = <&ccu RST_BUS_I2C1>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c2: i2c@5002800 { - compatible = "allwinner,sun50i-h6-i2c", - "allwinner,sun6i-a31-i2c"; - reg = <0x05002800 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_I2C2>; - resets = <&ccu RST_BUS_I2C2>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - emac: ethernet@5020000 { - compatible = "allwinner,sun50i-h6-emac", - "allwinner,sun50i-a64-emac"; - syscon = <&syscon>; - reg = <0x05020000 0x10000>; - interrupts = ; - interrupt-names = "macirq"; - resets = <&ccu RST_BUS_EMAC>; - reset-names = "stmmaceth"; - clocks = <&ccu CLK_BUS_EMAC>; - clock-names = "stmmaceth"; - status = "disabled"; - - mdio: mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - spdif: spdif@5093000 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun50i-h6-spdif"; - reg = <0x05093000 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; - clock-names = "apb", "spdif"; - resets = <&ccu RST_BUS_SPDIF>; - dmas = <&dma 2>; - dma-names = "tx"; - pinctrl-names = "default"; - pinctrl-0 = <&spdif_tx_pin>; - status = "disabled"; - }; - - usb2otg: usb@5100000 { - compatible = "allwinner,sun50i-h6-musb", - "allwinner,sun8i-a33-musb"; - reg = <0x05100000 0x0400>; - clocks = <&ccu CLK_BUS_OTG>; - resets = <&ccu RST_BUS_OTG>; - interrupts = ; - interrupt-names = "mc"; - phys = <&usb2phy 0>; - phy-names = "usb"; - extcon = <&usb2phy 0>; - status = "disabled"; - }; - - usb2phy: phy@5100400 { - compatible = "allwinner,sun50i-h6-usb-phy"; - reg = <0x05100400 0x24>, - <0x05101800 0x4>, - <0x05311800 0x4>; - reg-names = "phy_ctrl", - "pmu0", - "pmu3"; - clocks = <&ccu CLK_USB_PHY0>, - <&ccu CLK_USB_PHY3>; - clock-names = "usb0_phy", - "usb3_phy"; - resets = <&ccu RST_USB_PHY0>, - <&ccu RST_USB_PHY3>; - reset-names = "usb0_reset", - "usb3_reset"; - status = "disabled"; - #phy-cells = <1>; - }; - - ehci0: usb@5101000 { - compatible = "allwinner,sun50i-h6-ehci", "generic-ehci"; - reg = <0x05101000 0x100>; - interrupts = ; - clocks = <&ccu CLK_BUS_OHCI0>, - <&ccu CLK_BUS_EHCI0>, - <&ccu CLK_USB_OHCI0>; - resets = <&ccu RST_BUS_OHCI0>, - <&ccu RST_BUS_EHCI0>; - status = "disabled"; - }; - - ohci0: usb@5101400 { - compatible = "allwinner,sun50i-h6-ohci", "generic-ohci"; - reg = <0x05101400 0x100>; - interrupts = ; - clocks = <&ccu CLK_BUS_OHCI0>, - <&ccu CLK_USB_OHCI0>; - resets = <&ccu RST_BUS_OHCI0>; - status = "disabled"; - }; - - dwc3: dwc3@5200000 { - compatible = "snps,dwc3"; - reg = <0x05200000 0x10000>; - interrupts = ; - clocks = <&ccu CLK_BUS_XHCI>, - <&ccu CLK_BUS_XHCI>, - <&rtc 0>; - clock-names = "ref", "bus_early", "suspend"; - resets = <&ccu RST_BUS_XHCI>; - /* - * The datasheet of the chip doesn't declare the - * peripheral function, and there's no boards known - * to have a USB Type-B port routed to the port. - * In addition, no one has tested the peripheral - * function yet. - * So set the dr_mode to "host" in the DTSI file. - */ - dr_mode = "host"; - phys = <&usb3phy>; - phy-names = "usb3-phy"; - status = "disabled"; - }; - - usb3phy: phy@5210000 { - compatible = "allwinner,sun50i-h6-usb3-phy"; - reg = <0x5210000 0x10000>; - clocks = <&ccu CLK_USB_PHY1>; - resets = <&ccu RST_USB_PHY1>; - #phy-cells = <0>; - status = "disabled"; - }; - - ehci3: usb@5311000 { - compatible = "allwinner,sun50i-h6-ehci", "generic-ehci"; - reg = <0x05311000 0x100>; - interrupts = ; - clocks = <&ccu CLK_BUS_OHCI3>, - <&ccu CLK_BUS_EHCI3>, - <&ccu CLK_USB_OHCI3>; - resets = <&ccu RST_BUS_OHCI3>, - <&ccu RST_BUS_EHCI3>; - phys = <&usb2phy 3>; - phy-names = "usb"; - status = "disabled"; - }; - - ohci3: usb@5311400 { - compatible = "allwinner,sun50i-h6-ohci", "generic-ohci"; - reg = <0x05311400 0x100>; - interrupts = ; - clocks = <&ccu CLK_BUS_OHCI3>, - <&ccu CLK_USB_OHCI3>; - resets = <&ccu RST_BUS_OHCI3>; - phys = <&usb2phy 3>; - phy-names = "usb"; - status = "disabled"; - }; - - hdmi: hdmi@6000000 { - compatible = "allwinner,sun50i-h6-dw-hdmi"; - reg = <0x06000000 0x10000>; - reg-io-width = <1>; - interrupts = ; - clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>, - <&ccu CLK_HDMI>, <&ccu CLK_HDMI_CEC>, - <&ccu CLK_HDCP>, <&ccu CLK_BUS_HDCP>; - clock-names = "iahb", "isfr", "tmds", "cec", "hdcp", - "hdcp-bus"; - resets = <&ccu RST_BUS_HDMI_SUB>, <&ccu RST_BUS_HDCP>; - reset-names = "ctrl", "hdcp"; - phys = <&hdmi_phy>; - phy-names = "phy"; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_pins>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - hdmi_in: port@0 { - reg = <0>; - - hdmi_in_tcon_top: endpoint { - remote-endpoint = <&tcon_top_hdmi_out_hdmi>; - }; - }; - - hdmi_out: port@1 { - reg = <1>; - }; - }; - }; - - hdmi_phy: hdmi-phy@6010000 { - compatible = "allwinner,sun50i-h6-hdmi-phy"; - reg = <0x06010000 0x10000>; - clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>; - clock-names = "bus", "mod"; - resets = <&ccu RST_BUS_HDMI>; - reset-names = "phy"; - #phy-cells = <0>; - }; - - tcon_top: tcon-top@6510000 { - compatible = "allwinner,sun50i-h6-tcon-top"; - reg = <0x06510000 0x1000>; - clocks = <&ccu CLK_BUS_TCON_TOP>, - <&ccu CLK_TCON_TV0>; - clock-names = "bus", - "tcon-tv0"; - clock-output-names = "tcon-top-tv0"; - resets = <&ccu RST_BUS_TCON_TOP>; - #clock-cells = <1>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - tcon_top_mixer0_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - tcon_top_mixer0_in_mixer0: endpoint@0 { - reg = <0>; - remote-endpoint = <&mixer0_out_tcon_top_mixer0>; - }; - }; - - tcon_top_mixer0_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - tcon_top_mixer0_out_tcon_tv: endpoint@2 { - reg = <2>; - remote-endpoint = <&tcon_tv_in_tcon_top_mixer0>; - }; - }; - - tcon_top_hdmi_in: port@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - - tcon_top_hdmi_in_tcon_tv: endpoint@0 { - reg = <0>; - remote-endpoint = <&tcon_tv_out_tcon_top>; - }; - }; - - tcon_top_hdmi_out: port@5 { - reg = <5>; - - tcon_top_hdmi_out_hdmi: endpoint { - remote-endpoint = <&hdmi_in_tcon_top>; - }; - }; - }; - }; - - tcon_tv: lcd-controller@6515000 { - compatible = "allwinner,sun50i-h6-tcon-tv", - "allwinner,sun8i-r40-tcon-tv"; - reg = <0x06515000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_BUS_TCON_TV0>, - <&tcon_top CLK_TCON_TOP_TV0>; - clock-names = "ahb", - "tcon-ch1"; - resets = <&ccu RST_BUS_TCON_TV0>; - reset-names = "lcd"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - tcon_tv_in: port@0 { - reg = <0>; - - tcon_tv_in_tcon_top_mixer0: endpoint { - remote-endpoint = <&tcon_top_mixer0_out_tcon_tv>; - }; - }; - - tcon_tv_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - tcon_tv_out_tcon_top: endpoint@1 { - reg = <1>; - remote-endpoint = <&tcon_top_hdmi_in_tcon_tv>; - }; - }; - }; - }; - - rtc: rtc@7000000 { - compatible = "allwinner,sun50i-h6-rtc"; - reg = <0x07000000 0x400>; - interrupts = , - ; - clock-output-names = "osc32k", "osc32k-out", "iosc"; - clocks = <&ext_osc32k>; - #clock-cells = <1>; - }; - - r_ccu: clock@7010000 { - compatible = "allwinner,sun50i-h6-r-ccu"; - reg = <0x07010000 0x400>; - clocks = <&osc24M>, <&rtc 0>, <&rtc 2>, - <&ccu CLK_PLL_PERIPH0>; - clock-names = "hosc", "losc", "iosc", "pll-periph"; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - r_watchdog: watchdog@7020400 { - compatible = "allwinner,sun50i-h6-wdt", - "allwinner,sun6i-a31-wdt"; - reg = <0x07020400 0x20>; - interrupts = ; - clocks = <&osc24M>; - }; - - r_intc: interrupt-controller@7021000 { - compatible = "allwinner,sun50i-h6-r-intc", - "allwinner,sun6i-a31-r-intc"; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x07021000 0x400>; - interrupts = ; - }; - - r_pio: pinctrl@7022000 { - compatible = "allwinner,sun50i-h6-r-pinctrl"; - reg = <0x07022000 0x400>; - interrupts = , - ; - clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, <&rtc 0>; - clock-names = "apb", "hosc", "losc"; - gpio-controller; - #gpio-cells = <3>; - interrupt-controller; - #interrupt-cells = <3>; - - r_i2c_pins: r-i2c-pins { - pins = "PL0", "PL1"; - function = "s_i2c"; - }; - - r_ir_rx_pin: r-ir-rx-pin { - pins = "PL9"; - function = "s_cir_rx"; - }; - }; - - r_ir: ir@7040000 { - compatible = "allwinner,sun50i-h6-ir", - "allwinner,sun6i-a31-ir"; - reg = <0x07040000 0x400>; - interrupts = ; - clocks = <&r_ccu CLK_R_APB1_IR>, - <&r_ccu CLK_IR>; - clock-names = "apb", "ir"; - resets = <&r_ccu RST_R_APB1_IR>; - pinctrl-names = "default"; - pinctrl-0 = <&r_ir_rx_pin>; - status = "disabled"; - }; - - r_i2c: i2c@7081400 { - compatible = "allwinner,sun50i-h6-i2c", - "allwinner,sun6i-a31-i2c"; - reg = <0x07081400 0x400>; - interrupts = ; - clocks = <&r_ccu CLK_R_APB2_I2C>; - resets = <&r_ccu RST_R_APB2_I2C>; - pinctrl-names = "default"; - pinctrl-0 = <&r_i2c_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - ths: thermal-sensor@5070400 { - compatible = "allwinner,sun50i-h6-ths"; - reg = <0x05070400 0x100>; - interrupts = ; - clocks = <&ccu CLK_BUS_THS>; - clock-names = "bus"; - resets = <&ccu RST_BUS_THS>; - nvmem-cells = <&ths_calibration>; - nvmem-cell-names = "calibration"; - #thermal-sensor-cells = <1>; - }; - }; - - thermal-zones { - cpu-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&ths 0>; - }; - - gpu-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&ths 1>; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/altera/socfpga_stratix10.dtsi b/sys/gnu/dts/arm64/altera/socfpga_stratix10.dtsi deleted file mode 100644 index d1fc9c2055f..00000000000 --- a/sys/gnu/dts/arm64/altera/socfpga_stratix10.dtsi +++ /dev/null @@ -1,621 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright Altera Corporation (C) 2015. All rights reserved. - */ - -/dts-v1/; -#include -#include -#include - -/ { - compatible = "altr,socfpga-stratix10"; - #address-cells = <2>; - #size-cells = <2>; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - service_reserved: svcbuffer@0 { - compatible = "shared-dma-pool"; - reg = <0x0 0x0 0x0 0x1000000>; - alignment = <0x1000>; - no-map; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - enable-method = "psci"; - reg = <0x0>; - }; - - cpu1: cpu@1 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - enable-method = "psci"; - reg = <0x1>; - }; - - cpu2: cpu@2 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - enable-method = "psci"; - reg = <0x2>; - }; - - cpu3: cpu@3 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - enable-method = "psci"; - reg = <0x3>; - }; - }; - - pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = <0 170 4>, - <0 171 4>, - <0 172 4>, - <0 173 4>; - interrupt-affinity = <&cpu0>, - <&cpu1>, - <&cpu2>, - <&cpu3>; - interrupt-parent = <&intc>; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - intc: intc@fffc1000 { - compatible = "arm,gic-400", "arm,cortex-a15-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x0 0xfffc1000 0x0 0x1000>, - <0x0 0xfffc2000 0x0 0x2000>, - <0x0 0xfffc4000 0x0 0x2000>, - <0x0 0xfffc6000 0x0 0x2000>; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - device_type = "soc"; - interrupt-parent = <&intc>; - ranges = <0 0 0 0xffffffff>; - - base_fpga_region { - #address-cells = <0x1>; - #size-cells = <0x1>; - - compatible = "fpga-region"; - fpga-mgr = <&fpga_mgr>; - }; - - clkmgr: clock-controller@ffd10000 { - compatible = "intel,stratix10-clkmgr"; - reg = <0xffd10000 0x1000>; - #clock-cells = <1>; - }; - - clocks { - cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - }; - - cb_intosc_ls_clk: cb-intosc-ls-clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - }; - - f2s_free_clk: f2s-free-clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - }; - - osc1: osc1 { - #clock-cells = <0>; - compatible = "fixed-clock"; - }; - - qspi_clk: qspi-clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <200000000>; - }; - }; - - gmac0: ethernet@ff800000 { - compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac"; - reg = <0xff800000 0x2000>; - interrupts = <0 90 4>; - interrupt-names = "macirq"; - mac-address = [00 00 00 00 00 00]; - resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>; - reset-names = "stmmaceth", "stmmaceth-ocp"; - clocks = <&clkmgr STRATIX10_EMAC0_CLK>; - clock-names = "stmmaceth"; - tx-fifo-depth = <16384>; - rx-fifo-depth = <16384>; - snps,multicast-filter-bins = <256>; - iommus = <&smmu 1>; - altr,sysmgr-syscon = <&sysmgr 0x44 0>; - status = "disabled"; - }; - - gmac1: ethernet@ff802000 { - compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac"; - reg = <0xff802000 0x2000>; - interrupts = <0 91 4>; - interrupt-names = "macirq"; - mac-address = [00 00 00 00 00 00]; - resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>; - reset-names = "stmmaceth", "stmmaceth-ocp"; - clocks = <&clkmgr STRATIX10_EMAC1_CLK>; - clock-names = "stmmaceth"; - tx-fifo-depth = <16384>; - rx-fifo-depth = <16384>; - snps,multicast-filter-bins = <256>; - iommus = <&smmu 2>; - altr,sysmgr-syscon = <&sysmgr 0x48 8>; - status = "disabled"; - }; - - gmac2: ethernet@ff804000 { - compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac"; - reg = <0xff804000 0x2000>; - interrupts = <0 92 4>; - interrupt-names = "macirq"; - mac-address = [00 00 00 00 00 00]; - resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>; - reset-names = "stmmaceth", "stmmaceth-ocp"; - clocks = <&clkmgr STRATIX10_EMAC2_CLK>; - clock-names = "stmmaceth"; - tx-fifo-depth = <16384>; - rx-fifo-depth = <16384>; - snps,multicast-filter-bins = <256>; - iommus = <&smmu 3>; - altr,sysmgr-syscon = <&sysmgr 0x4c 16>; - status = "disabled"; - }; - - gpio0: gpio@ffc03200 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dw-apb-gpio"; - reg = <0xffc03200 0x100>; - resets = <&rst GPIO0_RESET>; - status = "disabled"; - - porta: gpio-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <24>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <0 110 4>; - }; - }; - - gpio1: gpio@ffc03300 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dw-apb-gpio"; - reg = <0xffc03300 0x100>; - resets = <&rst GPIO1_RESET>; - status = "disabled"; - - portb: gpio-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <24>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <0 111 4>; - }; - }; - - i2c0: i2c@ffc02800 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0xffc02800 0x100>; - interrupts = <0 103 4>; - resets = <&rst I2C0_RESET>; - clocks = <&clkmgr STRATIX10_L4_SP_CLK>; - status = "disabled"; - }; - - i2c1: i2c@ffc02900 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0xffc02900 0x100>; - interrupts = <0 104 4>; - resets = <&rst I2C1_RESET>; - clocks = <&clkmgr STRATIX10_L4_SP_CLK>; - status = "disabled"; - }; - - i2c2: i2c@ffc02a00 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0xffc02a00 0x100>; - interrupts = <0 105 4>; - resets = <&rst I2C2_RESET>; - clocks = <&clkmgr STRATIX10_L4_SP_CLK>; - status = "disabled"; - }; - - i2c3: i2c@ffc02b00 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0xffc02b00 0x100>; - interrupts = <0 106 4>; - resets = <&rst I2C3_RESET>; - clocks = <&clkmgr STRATIX10_L4_SP_CLK>; - status = "disabled"; - }; - - i2c4: i2c@ffc02c00 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0xffc02c00 0x100>; - interrupts = <0 107 4>; - resets = <&rst I2C4_RESET>; - clocks = <&clkmgr STRATIX10_L4_SP_CLK>; - status = "disabled"; - }; - - mmc: dwmmc0@ff808000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "altr,socfpga-dw-mshc"; - reg = <0xff808000 0x1000>; - interrupts = <0 96 4>; - fifo-depth = <0x400>; - resets = <&rst SDMMC_RESET>; - reset-names = "reset"; - clocks = <&clkmgr STRATIX10_L4_MP_CLK>, - <&clkmgr STRATIX10_SDMMC_CLK>; - clock-names = "biu", "ciu"; - iommus = <&smmu 5>; - status = "disabled"; - }; - - nand: nand@ffb90000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "altr,socfpga-denali-nand"; - reg = <0xffb90000 0x10000>, - <0xffb80000 0x1000>; - reg-names = "nand_data", "denali_reg"; - interrupts = <0 97 4>; - clocks = <&clkmgr STRATIX10_NAND_CLK>, - <&clkmgr STRATIX10_NAND_X_CLK>, - <&clkmgr STRATIX10_NAND_ECC_CLK>; - clock-names = "nand", "nand_x", "ecc"; - resets = <&rst NAND_RESET>, <&rst NAND_OCP_RESET>; - status = "disabled"; - }; - - ocram: sram@ffe00000 { - compatible = "mmio-sram"; - reg = <0xffe00000 0x100000>; - }; - - pdma: pdma@ffda0000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0xffda0000 0x1000>; - interrupts = <0 81 4>, - <0 82 4>, - <0 83 4>, - <0 84 4>, - <0 85 4>, - <0 86 4>, - <0 87 4>, - <0 88 4>, - <0 89 4>; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; - clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>; - clock-names = "apb_pclk"; - resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>; - reset-names = "dma", "dma-ocp"; - }; - - rst: rstmgr@ffd11000 { - #reset-cells = <1>; - compatible = "altr,stratix10-rst-mgr"; - reg = <0xffd11000 0x1000>; - }; - - smmu: iommu@fa000000 { - compatible = "arm,mmu-500", "arm,smmu-v2"; - reg = <0xfa000000 0x40000>; - #global-interrupts = <2>; - #iommu-cells = <1>; - clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>; - clock-names = "iommu"; - interrupt-parent = <&intc>; - interrupts = <0 128 4>, /* Global Secure Fault */ - <0 129 4>, /* Global Non-secure Fault */ - /* Non-secure Context Interrupts (32) */ - <0 138 4>, <0 139 4>, <0 140 4>, <0 141 4>, - <0 142 4>, <0 143 4>, <0 144 4>, <0 145 4>, - <0 146 4>, <0 147 4>, <0 148 4>, <0 149 4>, - <0 150 4>, <0 151 4>, <0 152 4>, <0 153 4>, - <0 154 4>, <0 155 4>, <0 156 4>, <0 157 4>, - <0 158 4>, <0 159 4>, <0 160 4>, <0 161 4>, - <0 162 4>, <0 163 4>, <0 164 4>, <0 165 4>, - <0 166 4>, <0 167 4>, <0 168 4>, <0 169 4>; - stream-match-mask = <0x7ff0>; - status = "disabled"; - }; - - spi0: spi@ffda4000 { - compatible = "snps,dw-apb-ssi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xffda4000 0x1000>; - interrupts = <0 99 4>; - resets = <&rst SPIM0_RESET>; - reg-io-width = <4>; - num-cs = <4>; - clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>; - status = "disabled"; - }; - - spi1: spi@ffda5000 { - compatible = "snps,dw-apb-ssi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xffda5000 0x1000>; - interrupts = <0 100 4>; - resets = <&rst SPIM1_RESET>; - reg-io-width = <4>; - num-cs = <4>; - clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>; - status = "disabled"; - }; - - sysmgr: sysmgr@ffd12000 { - compatible = "altr,sys-mgr-s10","altr,sys-mgr"; - reg = <0xffd12000 0x228>; - }; - - /* Local timer */ - timer { - compatible = "arm,armv8-timer"; - interrupts = <1 13 0xf08>, - <1 14 0xf08>, - <1 11 0xf08>, - <1 10 0xf08>; - }; - - timer0: timer0@ffc03000 { - compatible = "snps,dw-apb-timer"; - interrupts = <0 113 4>; - reg = <0xffc03000 0x100>; - clocks = <&clkmgr STRATIX10_L4_SP_CLK>; - clock-names = "timer"; - }; - - timer1: timer1@ffc03100 { - compatible = "snps,dw-apb-timer"; - interrupts = <0 114 4>; - reg = <0xffc03100 0x100>; - clocks = <&clkmgr STRATIX10_L4_SP_CLK>; - clock-names = "timer"; - }; - - timer2: timer2@ffd00000 { - compatible = "snps,dw-apb-timer"; - interrupts = <0 115 4>; - reg = <0xffd00000 0x100>; - clocks = <&clkmgr STRATIX10_L4_SP_CLK>; - clock-names = "timer"; - }; - - timer3: timer3@ffd00100 { - compatible = "snps,dw-apb-timer"; - interrupts = <0 116 4>; - reg = <0xffd00100 0x100>; - clocks = <&clkmgr STRATIX10_L4_SP_CLK>; - clock-names = "timer"; - }; - - uart0: serial0@ffc02000 { - compatible = "snps,dw-apb-uart"; - reg = <0xffc02000 0x100>; - interrupts = <0 108 4>; - reg-shift = <2>; - reg-io-width = <4>; - resets = <&rst UART0_RESET>; - clocks = <&clkmgr STRATIX10_L4_SP_CLK>; - status = "disabled"; - }; - - uart1: serial1@ffc02100 { - compatible = "snps,dw-apb-uart"; - reg = <0xffc02100 0x100>; - interrupts = <0 109 4>; - reg-shift = <2>; - reg-io-width = <4>; - resets = <&rst UART1_RESET>; - clocks = <&clkmgr STRATIX10_L4_SP_CLK>; - status = "disabled"; - }; - - usbphy0: usbphy@0 { - #phy-cells = <0>; - compatible = "usb-nop-xceiv"; - status = "okay"; - }; - - usb0: usb@ffb00000 { - compatible = "snps,dwc2"; - reg = <0xffb00000 0x40000>; - interrupts = <0 93 4>; - phys = <&usbphy0>; - phy-names = "usb2-phy"; - resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>; - reset-names = "dwc2", "dwc2-ecc"; - clocks = <&clkmgr STRATIX10_USB_CLK>; - iommus = <&smmu 6>; - status = "disabled"; - }; - - usb1: usb@ffb40000 { - compatible = "snps,dwc2"; - reg = <0xffb40000 0x40000>; - interrupts = <0 94 4>; - phys = <&usbphy0>; - phy-names = "usb2-phy"; - resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>; - reset-names = "dwc2", "dwc2-ecc"; - clocks = <&clkmgr STRATIX10_USB_CLK>; - iommus = <&smmu 7>; - status = "disabled"; - }; - - watchdog0: watchdog@ffd00200 { - compatible = "snps,dw-wdt"; - reg = <0xffd00200 0x100>; - interrupts = <0 117 4>; - resets = <&rst WATCHDOG0_RESET>; - clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>; - status = "disabled"; - }; - - watchdog1: watchdog@ffd00300 { - compatible = "snps,dw-wdt"; - reg = <0xffd00300 0x100>; - interrupts = <0 118 4>; - resets = <&rst WATCHDOG1_RESET>; - clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>; - status = "disabled"; - }; - - watchdog2: watchdog@ffd00400 { - compatible = "snps,dw-wdt"; - reg = <0xffd00400 0x100>; - interrupts = <0 125 4>; - resets = <&rst WATCHDOG2_RESET>; - clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>; - status = "disabled"; - }; - - watchdog3: watchdog@ffd00500 { - compatible = "snps,dw-wdt"; - reg = <0xffd00500 0x100>; - interrupts = <0 126 4>; - resets = <&rst WATCHDOG3_RESET>; - clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>; - status = "disabled"; - }; - - sdr: sdr@f8011100 { - compatible = "altr,sdr-ctl", "syscon"; - reg = <0xf8011100 0xc0>; - }; - - eccmgr { - compatible = "altr,socfpga-s10-ecc-manager", - "altr,socfpga-a10-ecc-manager"; - altr,sysmgr-syscon = <&sysmgr>; - #address-cells = <1>; - #size-cells = <1>; - interrupts = <0 15 4>; - interrupt-controller; - #interrupt-cells = <2>; - ranges; - - sdramedac { - compatible = "altr,sdram-edac-s10"; - altr,sdr-syscon = <&sdr>; - interrupts = <16 4>; - }; - - ocram-ecc@ff8cc000 { - compatible = "altr,socfpga-s10-ocram-ecc", - "altr,socfpga-a10-ocram-ecc"; - reg = <0xff8cc000 0x100>; - altr,ecc-parent = <&ocram>; - interrupts = <1 4>; - }; - - usb0-ecc@ff8c4000 { - compatible = "altr,socfpga-s10-usb-ecc", - "altr,socfpga-usb-ecc"; - reg = <0xff8c4000 0x100>; - altr,ecc-parent = <&usb0>; - interrupts = <2 4>; - }; - - emac0-rx-ecc@ff8c0000 { - compatible = "altr,socfpga-s10-eth-mac-ecc", - "altr,socfpga-eth-mac-ecc"; - reg = <0xff8c0000 0x100>; - altr,ecc-parent = <&gmac0>; - interrupts = <4 4>; - }; - - emac0-tx-ecc@ff8c0400 { - compatible = "altr,socfpga-s10-eth-mac-ecc", - "altr,socfpga-eth-mac-ecc"; - reg = <0xff8c0400 0x100>; - altr,ecc-parent = <&gmac0>; - interrupts = <5 4>; - }; - - }; - - qspi: spi@ff8d2000 { - compatible = "cdns,qspi-nor"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xff8d2000 0x100>, - <0xff900000 0x100000>; - interrupts = <0 3 4>; - cdns,fifo-depth = <128>; - cdns,fifo-width = <4>; - cdns,trigger-address = <0x00000000>; - clocks = <&qspi_clk>; - - status = "disabled"; - }; - - firmware { - svc { - compatible = "intel,stratix10-svc"; - method = "smc"; - memory-region = <&service_reserved>; - - fpga_mgr: fpga-mgr { - compatible = "intel,stratix10-soc-fpga-mgr"; - }; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/altera/socfpga_stratix10_socdk.dts b/sys/gnu/dts/arm64/altera/socfpga_stratix10_socdk.dts deleted file mode 100644 index fb11ef05d55..00000000000 --- a/sys/gnu/dts/arm64/altera/socfpga_stratix10_socdk.dts +++ /dev/null @@ -1,190 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright Altera Corporation (C) 2015. All rights reserved. - */ - -#include "socfpga_stratix10.dtsi" - -/ { - model = "SoCFPGA Stratix 10 SoCDK"; - - aliases { - serial0 = &uart0; - ethernet0 = &gmac0; - ethernet1 = &gmac1; - ethernet2 = &gmac2; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - hps0 { - label = "hps_led0"; - gpios = <&portb 20 GPIO_ACTIVE_HIGH>; - }; - - hps1 { - label = "hps_led1"; - gpios = <&portb 19 GPIO_ACTIVE_HIGH>; - }; - - hps2 { - label = "hps_led2"; - gpios = <&portb 21 GPIO_ACTIVE_HIGH>; - }; - }; - - memory { - device_type = "memory"; - /* We expect the bootloader to fill in the reg */ - reg = <0 0 0 0>; - }; - - ref_033v: 033-v-ref { - compatible = "regulator-fixed"; - regulator-name = "0.33V"; - regulator-min-microvolt = <330000>; - regulator-max-microvolt = <330000>; - }; - - soc { - clocks { - osc1 { - clock-frequency = <25000000>; - }; - }; - - eccmgr { - sdmmca-ecc@ff8c8c00 { - compatible = "altr,socfpga-s10-sdmmc-ecc", - "altr,socfpga-sdmmc-ecc"; - reg = <0xff8c8c00 0x100>; - altr,ecc-parent = <&mmc>; - interrupts = <14 4>, - <15 4>; - }; - }; - }; -}; - -&gpio1 { - status = "okay"; -}; - -&gmac0 { - status = "okay"; - phy-mode = "rgmii"; - phy-handle = <&phy0>; - - max-frame-size = <9000>; - - mdio0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - phy0: ethernet-phy@0 { - reg = <4>; - - txd0-skew-ps = <0>; /* -420ps */ - txd1-skew-ps = <0>; /* -420ps */ - txd2-skew-ps = <0>; /* -420ps */ - txd3-skew-ps = <0>; /* -420ps */ - rxd0-skew-ps = <420>; /* 0ps */ - rxd1-skew-ps = <420>; /* 0ps */ - rxd2-skew-ps = <420>; /* 0ps */ - rxd3-skew-ps = <420>; /* 0ps */ - txen-skew-ps = <0>; /* -420ps */ - txc-skew-ps = <900>; /* 0ps */ - rxdv-skew-ps = <420>; /* 0ps */ - rxc-skew-ps = <1680>; /* 780ps */ - }; - }; -}; - -&mmc { - status = "okay"; - cap-sd-highspeed; - cap-mmc-highspeed; - broken-cd; - bus-width = <4>; -}; - -&uart0 { - status = "okay"; -}; - -&usb0 { - status = "okay"; - disable-over-current; -}; - -&watchdog0 { - status = "okay"; -}; - -&i2c1 { - status = "okay"; - clock-frequency = <100000>; - i2c-sda-falling-time-ns = <890>; /* hcnt */ - i2c-sdl-falling-time-ns = <890>; /* lcnt */ - - adc@14 { - compatible = "lltc,ltc2497"; - reg = <0x14>; - vref-supply = <&ref_033v>; - }; - - temp@4c { - compatible = "maxim,max1619"; - reg = <0x4c>; - }; - - eeprom@51 { - compatible = "atmel,24c32"; - reg = <0x51>; - pagesize = <32>; - }; - - rtc@68 { - compatible = "dallas,ds1339"; - reg = <0x68>; - }; -}; - -&qspi { - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "n25q00a"; - reg = <0>; - spi-max-frequency = <100000000>; - - m25p,fast-read; - cdns,page-size = <256>; - cdns,block-size = <16>; - cdns,read-delay = <1>; - cdns,tshsl-ns = <50>; - cdns,tsd2d-ns = <50>; - cdns,tchsh-ns = <4>; - cdns,tslch-ns = <4>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - qspi_boot: partition@0 { - label = "Boot and fpga data"; - reg = <0x0 0x034B0000>; - }; - - qspi_rootfs: partition@4000000 { - label = "Root Filesystem - JFFS2"; - reg = <0x034B0000 0x0EB50000>; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/altera/socfpga_stratix10_socdk_nand.dts b/sys/gnu/dts/arm64/altera/socfpga_stratix10_socdk_nand.dts deleted file mode 100644 index 9946515b8af..00000000000 --- a/sys/gnu/dts/arm64/altera/socfpga_stratix10_socdk_nand.dts +++ /dev/null @@ -1,223 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright Altera Corporation (C) 2015. All rights reserved. - */ - -#include "socfpga_stratix10.dtsi" - -/ { - model = "SoCFPGA Stratix 10 SoCDK"; - - aliases { - serial0 = &uart0; - ethernet0 = &gmac0; - ethernet1 = &gmac1; - ethernet2 = &gmac2; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - hps0 { - label = "hps_led0"; - gpios = <&portb 20 GPIO_ACTIVE_HIGH>; - }; - - hps1 { - label = "hps_led1"; - gpios = <&portb 19 GPIO_ACTIVE_HIGH>; - }; - - hps2 { - label = "hps_led2"; - gpios = <&portb 21 GPIO_ACTIVE_HIGH>; - }; - }; - - memory { - device_type = "memory"; - /* We expect the bootloader to fill in the reg */ - reg = <0 0 0 0>; - }; - - ref_033v: 033-v-ref { - compatible = "regulator-fixed"; - regulator-name = "0.33V"; - regulator-min-microvolt = <330000>; - regulator-max-microvolt = <330000>; - }; - - soc { - clocks { - osc1 { - clock-frequency = <25000000>; - }; - }; - - eccmgr { - sdmmca-ecc@ff8c8c00 { - compatible = "altr,socfpga-s10-sdmmc-ecc", - "altr,socfpga-sdmmc-ecc"; - reg = <0xff8c8c00 0x100>; - altr,ecc-parent = <&mmc>; - interrupts = <14 4>, - <15 4>; - }; - }; - }; -}; - -&gpio1 { - status = "okay"; -}; - -&gmac2 { - status = "okay"; - phy-mode = "rgmii"; - phy-handle = <&phy0>; - - max-frame-size = <9000>; - - mdio0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - phy0: ethernet-phy@0 { - reg = <4>; - - txd0-skew-ps = <0>; /* -420ps */ - txd1-skew-ps = <0>; /* -420ps */ - txd2-skew-ps = <0>; /* -420ps */ - txd3-skew-ps = <0>; /* -420ps */ - rxd0-skew-ps = <420>; /* 0ps */ - rxd1-skew-ps = <420>; /* 0ps */ - rxd2-skew-ps = <420>; /* 0ps */ - rxd3-skew-ps = <420>; /* 0ps */ - txen-skew-ps = <0>; /* -420ps */ - txc-skew-ps = <900>; /* 0ps */ - rxdv-skew-ps = <420>; /* 0ps */ - rxc-skew-ps = <1680>; /* 780ps */ - }; - }; -}; - -&nand { - status = "okay"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - reg = <0>; - nand-bus-width = <16>; - - partition@0 { - label = "u-boot"; - reg = <0 0x200000>; - }; - - partition@200000 { - label = "env"; - reg = <0x200000 0x40000>; - }; - - partition@240000 { - label = "dtb"; - reg = <0x240000 0x40000>; - }; - - partition@280000 { - label = "kernel"; - reg = <0x280000 0x2000000>; - }; - - partition@2280000 { - label = "misc"; - reg = <0x2280000 0x2000000>; - }; - - partition@4280000 { - label = "rootfs"; - reg = <0x4280000 0x3bd80000>; - }; - }; -}; - -&uart0 { - status = "okay"; -}; - -&usb0 { - status = "okay"; - disable-over-current; -}; - -&watchdog0 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; - clock-frequency = <100000>; - i2c-sda-falling-time-ns = <890>; /* hcnt */ - i2c-sdl-falling-time-ns = <890>; /* lcnt */ - - adc@14 { - compatible = "lltc,ltc2497"; - reg = <0x14>; - vref-supply = <&ref_033v>; - }; - - temp@4c { - compatible = "maxim,max1619"; - reg = <0x4c>; - }; - - eeprom@51 { - compatible = "atmel,24c32"; - reg = <0x51>; - pagesize = <32>; - }; - - rtc@68 { - compatible = "dallas,ds1339"; - reg = <0x68>; - }; -}; - -&qspi { - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "n25q00a"; - reg = <0>; - spi-max-frequency = <100000000>; - - m25p,fast-read; - cdns,page-size = <256>; - cdns,block-size = <16>; - cdns,read-delay = <1>; - cdns,tshsl-ns = <50>; - cdns,tsd2d-ns = <50>; - cdns,tchsh-ns = <4>; - cdns,tslch-ns = <4>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - qspi_boot: partition@0 { - label = "Boot and fpga data"; - reg = <0x0 0x034B0000>; - }; - - qspi_rootfs: partition@4000000 { - label = "Root Filesystem - JFFS2"; - reg = <0x034B0000 0x0EB50000>; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/amd/amd-overdrive-rev-b0.dts b/sys/gnu/dts/arm64/amd/amd-overdrive-rev-b0.dts deleted file mode 100644 index 8e341be9a39..00000000000 --- a/sys/gnu/dts/arm64/amd/amd-overdrive-rev-b0.dts +++ /dev/null @@ -1,88 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * DTS file for AMD Seattle Overdrive Development Board - * Note: For Seattle Rev.B0 - * - * Copyright (C) 2015 Advanced Micro Devices, Inc. - */ - -/dts-v1/; - -/include/ "amd-seattle-soc.dtsi" - -/ { - model = "AMD Seattle (Rev.B0) Development Board (Overdrive)"; - compatible = "amd,seattle-overdrive", "amd,seattle"; - - chosen { - stdout-path = &serial0; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; -}; - -&ccp0 { - status = "ok"; - amd,zlib-support = <1>; -}; - -/** - * NOTE: In Rev.B, gpio0 is reserved. - */ -&gpio1 { - status = "ok"; -}; - -&gpio2 { - status = "ok"; -}; - -&gpio3 { - status = "ok"; -}; - -&gpio4 { - status = "ok"; -}; - -&i2c0 { - status = "ok"; -}; - -&i2c1 { - status = "ok"; -}; - -&pcie0 { - status = "ok"; -}; - -&spi0 { - status = "ok"; -}; - -&spi1 { - status = "ok"; - sdcard0: sdcard@0 { - compatible = "mmc-spi-slot"; - reg = <0>; - spi-max-frequency = <20000000>; - voltage-ranges = <3200 3400>; - pl022,hierarchy = <0>; - pl022,interface = <0>; - pl022,com-mode = <0x0>; - pl022,rx-level-trig = <0>; - pl022,tx-level-trig = <0>; - }; -}; - -&ipmi_kcs { - status = "ok"; -}; - -&smb0 { - /include/ "amd-seattle-xgbe-b.dtsi" -}; diff --git a/sys/gnu/dts/arm64/amd/amd-overdrive-rev-b1.dts b/sys/gnu/dts/arm64/amd/amd-overdrive-rev-b1.dts deleted file mode 100644 index 92cef05c6b7..00000000000 --- a/sys/gnu/dts/arm64/amd/amd-overdrive-rev-b1.dts +++ /dev/null @@ -1,92 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * DTS file for AMD Seattle Overdrive Development Board - * Note: For Seattle Rev.B1 - * - * Copyright (C) 2015 Advanced Micro Devices, Inc. - */ - -/dts-v1/; - -/include/ "amd-seattle-soc.dtsi" - -/ { - model = "AMD Seattle (Rev.B1) Development Board (Overdrive)"; - compatible = "amd,seattle-overdrive", "amd,seattle"; - - chosen { - stdout-path = &serial0; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; -}; - -&ccp0 { - status = "ok"; - amd,zlib-support = <1>; -}; - -/** - * NOTE: In Rev.B, gpio0 is reserved. - */ -&gpio1 { - status = "ok"; -}; - -&gpio2 { - status = "ok"; -}; - -&gpio3 { - status = "ok"; -}; - -&gpio4 { - status = "ok"; -}; - -&i2c0 { - status = "ok"; -}; - -&i2c1 { - status = "ok"; -}; - -&pcie0 { - status = "ok"; -}; - -&sata1 { - status = "ok"; -}; - -&spi0 { - status = "ok"; -}; - -&spi1 { - status = "ok"; - sdcard0: sdcard@0 { - compatible = "mmc-spi-slot"; - reg = <0>; - spi-max-frequency = <20000000>; - voltage-ranges = <3200 3400>; - pl022,hierarchy = <0>; - pl022,interface = <0>; - pl022,com-mode = <0x0>; - pl022,rx-level-trig = <0>; - pl022,tx-level-trig = <0>; - }; -}; - -&ipmi_kcs { - status = "ok"; -}; - -&smb0 { - /include/ "amd-seattle-xgbe-b.dtsi" -}; diff --git a/sys/gnu/dts/arm64/amd/amd-overdrive.dts b/sys/gnu/dts/arm64/amd/amd-overdrive.dts deleted file mode 100644 index 41b3a6c0993..00000000000 --- a/sys/gnu/dts/arm64/amd/amd-overdrive.dts +++ /dev/null @@ -1,66 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * DTS file for AMD Seattle Overdrive Development Board - * - * Copyright (C) 2014 Advanced Micro Devices, Inc. - */ - -/dts-v1/; - -/include/ "amd-seattle-soc.dtsi" - -/ { - model = "AMD Seattle Development Board (Overdrive)"; - compatible = "amd,seattle-overdrive", "amd,seattle"; - - chosen { - stdout-path = &serial0; - }; -}; - -&ccp0 { - status = "ok"; -}; - -&gpio0 { - status = "ok"; -}; - -&gpio1 { - status = "ok"; -}; - -&i2c0 { - status = "ok"; -}; - -&pcie0 { - status = "ok"; -}; - -&spi0 { - status = "ok"; -}; - -&spi1 { - status = "ok"; - sdcard0: sdcard@0 { - compatible = "mmc-spi-slot"; - reg = <0>; - spi-max-frequency = <20000000>; - voltage-ranges = <3200 3400>; - gpios = <&gpio0 7 0>; - interrupt-parent = <&gpio0>; - interrupts = <7 3>; - pl022,hierarchy = <0>; - pl022,interface = <0>; - pl022,com-mode = <0x0>; - pl022,rx-level-trig = <0>; - pl022,tx-level-trig = <0>; - }; -}; - -&v2m0 { - arm,msi-base-spi = <64>; - arm,msi-num-spis = <256>; -}; diff --git a/sys/gnu/dts/arm64/amd/amd-seattle-clks.dtsi b/sys/gnu/dts/arm64/amd/amd-seattle-clks.dtsi deleted file mode 100644 index 2dd2c28171e..00000000000 --- a/sys/gnu/dts/arm64/amd/amd-seattle-clks.dtsi +++ /dev/null @@ -1,55 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * DTS file for AMD Seattle Clocks - * - * Copyright (C) 2014 Advanced Micro Devices, Inc. - */ - - adl3clk_100mhz: clk100mhz_0 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - clock-output-names = "adl3clk_100mhz"; - }; - - ccpclk_375mhz: clk375mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <375000000>; - clock-output-names = "ccpclk_375mhz"; - }; - - sataclk_333mhz: clk333mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <333000000>; - clock-output-names = "sataclk_333mhz"; - }; - - pcieclk_500mhz: clk500mhz_0 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <500000000>; - clock-output-names = "pcieclk_500mhz"; - }; - - dmaclk_500mhz: clk500mhz_1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <500000000>; - clock-output-names = "dmaclk_500mhz"; - }; - - miscclk_250mhz: clk250mhz_4 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <250000000>; - clock-output-names = "miscclk_250mhz"; - }; - - uartspiclk_100mhz: clk100mhz_1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - clock-output-names = "uartspiclk_100mhz"; - }; diff --git a/sys/gnu/dts/arm64/amd/amd-seattle-soc.dtsi b/sys/gnu/dts/arm64/amd/amd-seattle-soc.dtsi deleted file mode 100644 index b664e7af74e..00000000000 --- a/sys/gnu/dts/arm64/amd/amd-seattle-soc.dtsi +++ /dev/null @@ -1,251 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * DTS file for AMD Seattle SoC - * - * Copyright (C) 2014 Advanced Micro Devices, Inc. - */ - -/ { - compatible = "amd,seattle"; - interrupt-parent = <&gic0>; - #address-cells = <2>; - #size-cells = <2>; - - gic0: interrupt-controller@e1101000 { - compatible = "arm,gic-400", "arm,cortex-a15-gic"; - interrupt-controller; - #interrupt-cells = <3>; - #address-cells = <2>; - #size-cells = <2>; - reg = <0x0 0xe1110000 0 0x1000>, - <0x0 0xe112f000 0 0x2000>, - <0x0 0xe1140000 0 0x2000>, - <0x0 0xe1160000 0 0x2000>; - interrupts = <1 9 0xf04>; - ranges = <0 0 0 0xe1100000 0 0x100000>; - v2m0: v2m@e0080000 { - compatible = "arm,gic-v2m-frame"; - msi-controller; - reg = <0x0 0x00080000 0 0x1000>; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = <1 13 0xff04>, - <1 14 0xff04>, - <1 11 0xff04>, - <1 10 0xff04>; - }; - - pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = <0 7 4>, - <0 8 4>, - <0 9 4>, - <0 10 4>, - <0 11 4>, - <0 12 4>, - <0 13 4>, - <0 14 4>; - }; - - smb0: smb { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - /* - * dma-ranges is 40-bit address space containing: - * - GICv2m MSI register is at 0xe0080000 - * - DRAM range [0x8000000000 to 0xffffffffff] - */ - dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; - - /include/ "amd-seattle-clks.dtsi" - - sata0: sata@e0300000 { - compatible = "snps,dwc-ahci"; - reg = <0 0xe0300000 0 0xf0000>; - interrupts = <0 355 4>; - clocks = <&sataclk_333mhz>; - dma-coherent; - }; - - /* This is for Rev B only */ - sata1: sata@e0d00000 { - status = "disabled"; - compatible = "snps,dwc-ahci"; - reg = <0 0xe0d00000 0 0xf0000>; - interrupts = <0 354 4>; - clocks = <&sataclk_333mhz>; - dma-coherent; - }; - - i2c0: i2c@e1000000 { - status = "disabled"; - compatible = "snps,designware-i2c"; - reg = <0 0xe1000000 0 0x1000>; - interrupts = <0 357 4>; - clocks = <&miscclk_250mhz>; - }; - - i2c1: i2c@e0050000 { - status = "disabled"; - compatible = "snps,designware-i2c"; - reg = <0 0xe0050000 0 0x1000>; - interrupts = <0 340 4>; - clocks = <&miscclk_250mhz>; - }; - - serial0: serial@e1010000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0 0xe1010000 0 0x1000>; - interrupts = <0 328 4>; - clocks = <&uartspiclk_100mhz>, <&uartspiclk_100mhz>; - clock-names = "uartclk", "apb_pclk"; - }; - - spi0: spi@e1020000 { - status = "disabled"; - compatible = "arm,pl022", "arm,primecell"; - reg = <0 0xe1020000 0 0x1000>; - spi-controller; - interrupts = <0 330 4>; - clocks = <&uartspiclk_100mhz>; - clock-names = "apb_pclk"; - }; - - spi1: spi@e1030000 { - status = "disabled"; - compatible = "arm,pl022", "arm,primecell"; - reg = <0 0xe1030000 0 0x1000>; - spi-controller; - interrupts = <0 329 4>; - clocks = <&uartspiclk_100mhz>; - clock-names = "apb_pclk"; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - }; - - gpio0: gpio@e1040000 { /* Not available to OS for B0 */ - status = "disabled"; - compatible = "arm,pl061", "arm,primecell"; - #gpio-cells = <2>; - reg = <0 0xe1040000 0 0x1000>; - gpio-controller; - interrupts = <0 359 4>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&miscclk_250mhz>; - clock-names = "apb_pclk"; - }; - - gpio1: gpio@e1050000 { /* [0:7] */ - status = "disabled"; - compatible = "arm,pl061", "arm,primecell"; - #gpio-cells = <2>; - reg = <0 0xe1050000 0 0x1000>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <0 358 4>; - clocks = <&miscclk_250mhz>; - clock-names = "apb_pclk"; - }; - - gpio2: gpio@e0020000 { /* [8:15] */ - status = "disabled"; - compatible = "arm,pl061", "arm,primecell"; - #gpio-cells = <2>; - reg = <0 0xe0020000 0 0x1000>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <0 366 4>; - clocks = <&miscclk_250mhz>; - clock-names = "apb_pclk"; - }; - - gpio3: gpio@e0030000 { /* [16:23] */ - status = "disabled"; - compatible = "arm,pl061", "arm,primecell"; - #gpio-cells = <2>; - reg = <0 0xe0030000 0 0x1000>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <0 365 4>; - clocks = <&miscclk_250mhz>; - clock-names = "apb_pclk"; - }; - - gpio4: gpio@e0080000 { /* [24] */ - status = "disabled"; - compatible = "arm,pl061", "arm,primecell"; - #gpio-cells = <2>; - reg = <0 0xe0080000 0 0x1000>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <0 361 4>; - clocks = <&miscclk_250mhz>; - clock-names = "apb_pclk"; - }; - - ccp0: ccp@e0100000 { - status = "disabled"; - compatible = "amd,ccp-seattle-v1a"; - reg = <0 0xe0100000 0 0x10000>; - interrupts = <0 3 4>; - dma-coherent; - }; - - pcie0: pcie@f0000000 { - compatible = "pci-host-ecam-generic"; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - device_type = "pci"; - bus-range = <0 0x7f>; - msi-parent = <&v2m0>; - reg = <0 0xf0000000 0 0x10000000>; - - interrupt-map-mask = <0xf800 0x0 0x0 0x7>; - interrupt-map = - <0x1000 0x0 0x0 0x1 &gic0 0x0 0x0 0x0 0x120 0x1>, - <0x1000 0x0 0x0 0x2 &gic0 0x0 0x0 0x0 0x121 0x1>, - <0x1000 0x0 0x0 0x3 &gic0 0x0 0x0 0x0 0x122 0x1>, - <0x1000 0x0 0x0 0x4 &gic0 0x0 0x0 0x0 0x123 0x1>; - - dma-coherent; - dma-ranges = <0x43000000 0x0 0x0 0x0 0x0 0x100 0x0>; - ranges = - /* I/O Memory (size=64K) */ - <0x01000000 0x00 0x00000000 0x00 0xefff0000 0x00 0x00010000>, - /* 32-bit MMIO (size=2G) */ - <0x02000000 0x00 0x40000000 0x00 0x40000000 0x00 0x80000000>, - /* 64-bit MMIO (size= 124G) */ - <0x03000000 0x01 0x00000000 0x01 0x00000000 0x7f 0x00000000>; - }; - - /* Perf CCN504 PMU */ - ccn: ccn@e8000000 { - compatible = "arm,ccn-504"; - reg = <0x0 0xe8000000 0 0x1000000>; - interrupts = <0 380 4>; - }; - - ipmi_kcs: kcs@e0010000 { - status = "disabled"; - compatible = "ipmi-kcs"; - device_type = "ipmi"; - reg = <0x0 0xe0010000 0 0x8>; - interrupts = <0 389 4>; - reg-size = <1>; - reg-spacing = <4>; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/amd/amd-seattle-xgbe-b.dtsi b/sys/gnu/dts/arm64/amd/amd-seattle-xgbe-b.dtsi deleted file mode 100644 index d97498361ce..00000000000 --- a/sys/gnu/dts/arm64/amd/amd-seattle-xgbe-b.dtsi +++ /dev/null @@ -1,118 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * DTS file for AMD Seattle XGBE (RevB) - * - * Copyright (C) 2015 Advanced Micro Devices, Inc. - */ - - xgmacclk0_dma_250mhz: clk250mhz_0 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <250000000>; - clock-output-names = "xgmacclk0_dma_250mhz"; - }; - - xgmacclk0_ptp_250mhz: clk250mhz_1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <250000000>; - clock-output-names = "xgmacclk0_ptp_250mhz"; - }; - - xgmacclk1_dma_250mhz: clk250mhz_2 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <250000000>; - clock-output-names = "xgmacclk1_dma_250mhz"; - }; - - xgmacclk1_ptp_250mhz: clk250mhz_3 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <250000000>; - clock-output-names = "xgmacclk1_ptp_250mhz"; - }; - - xgmac0: xgmac@e0700000 { - compatible = "amd,xgbe-seattle-v1a"; - reg = <0 0xe0700000 0 0x80000>, - <0 0xe0780000 0 0x80000>, - <0 0xe1240800 0 0x00400>, /* SERDES RX/TX0 */ - <0 0xe1250000 0 0x00060>, /* SERDES IR 1/2 */ - <0 0xe12500f8 0 0x00004>; /* SERDES IR 2/2 */ - interrupts = <0 325 4>, - <0 346 1>, <0 347 1>, <0 348 1>, <0 349 1>, - <0 323 4>; - amd,per-channel-interrupt; - amd,speed-set = <0>; - amd,serdes-blwc = <1>, <1>, <0>; - amd,serdes-cdr-rate = <2>, <2>, <7>; - amd,serdes-pq-skew = <10>, <10>, <18>; - amd,serdes-tx-amp = <0>, <0>, <0>; - amd,serdes-dfe-tap-config = <3>, <3>, <3>; - amd,serdes-dfe-tap-enable = <0>, <0>, <7>; - mac-address = [ 02 A1 A2 A3 A4 A5 ]; - clocks = <&xgmacclk0_dma_250mhz>, <&xgmacclk0_ptp_250mhz>; - clock-names = "dma_clk", "ptp_clk"; - phy-mode = "xgmii"; - #stream-id-cells = <16>; - dma-coherent; - }; - - xgmac1: xgmac@e0900000 { - compatible = "amd,xgbe-seattle-v1a"; - reg = <0 0xe0900000 0 0x80000>, - <0 0xe0980000 0 0x80000>, - <0 0xe1240c00 0 0x00400>, /* SERDES RX/TX1 */ - <0 0xe1250080 0 0x00060>, /* SERDES IR 1/2 */ - <0 0xe12500fc 0 0x00004>; /* SERDES IR 2/2 */ - interrupts = <0 324 4>, - <0 341 1>, <0 342 1>, <0 343 1>, <0 344 1>, - <0 322 4>; - amd,per-channel-interrupt; - amd,speed-set = <0>; - amd,serdes-blwc = <1>, <1>, <0>; - amd,serdes-cdr-rate = <2>, <2>, <7>; - amd,serdes-pq-skew = <10>, <10>, <18>; - amd,serdes-tx-amp = <0>, <0>, <0>; - amd,serdes-dfe-tap-config = <3>, <3>, <3>; - amd,serdes-dfe-tap-enable = <0>, <0>, <7>; - mac-address = [ 02 B1 B2 B3 B4 B5 ]; - clocks = <&xgmacclk1_dma_250mhz>, <&xgmacclk1_ptp_250mhz>; - clock-names = "dma_clk", "ptp_clk"; - phy-mode = "xgmii"; - #stream-id-cells = <16>; - dma-coherent; - }; - - xgmac0_smmu: smmu@e0600000 { - compatible = "arm,mmu-401"; - reg = <0 0xe0600000 0 0x10000>; - #global-interrupts = <1>; - interrupts = /* Uses combined intr for both - * global and context - */ - <0 336 4>, - <0 336 4>; - - mmu-masters = <&xgmac0 - 0 1 2 3 4 5 6 7 - 16 17 18 19 20 21 22 23 - >; - }; - - xgmac1_smmu: smmu@e0800000 { - compatible = "arm,mmu-401"; - reg = <0 0xe0800000 0 0x10000>; - #global-interrupts = <1>; - interrupts = /* Uses combined intr for both - * global and context - */ - <0 335 4>, - <0 335 4>; - - mmu-masters = <&xgmac1 - 0 1 2 3 4 5 6 7 - 16 17 18 19 20 21 22 23 - >; - }; diff --git a/sys/gnu/dts/arm64/amd/husky.dts b/sys/gnu/dts/arm64/amd/husky.dts deleted file mode 100644 index 7acde34772c..00000000000 --- a/sys/gnu/dts/arm64/amd/husky.dts +++ /dev/null @@ -1,84 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * DTS file for AMD/Linaro 96Boards Enterprise Edition Server (Husky) Board - * Note: Based-on AMD Seattle Rev.B0 - * - * Copyright (C) 2015 Advanced Micro Devices, Inc. - */ - -/dts-v1/; - -/include/ "amd-seattle-soc.dtsi" - -/ { - model = "Linaro 96Boards Enterprise Edition Server (Husky) Board"; - compatible = "amd,seattle-overdrive", "amd,seattle"; - - chosen { - stdout-path = &serial0; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; -}; - -&ccp0 { - status = "ok"; - amd,zlib-support = <1>; -}; - -/** - * NOTE: In Rev.B, gpio0 is reserved. - */ -&gpio1 { - status = "ok"; -}; - -&gpio2 { - status = "ok"; -}; - -&gpio3 { - status = "ok"; -}; - -&gpio4 { - status = "ok"; -}; - -&i2c0 { - status = "ok"; -}; - -&i2c1 { - status = "ok"; -}; - -&pcie0 { - status = "ok"; -}; - -&spi0 { - status = "ok"; -}; - -&spi1 { - status = "ok"; - sdcard0: sdcard@0 { - compatible = "mmc-spi-slot"; - reg = <0>; - spi-max-frequency = <20000000>; - voltage-ranges = <3200 3400>; - pl022,hierarchy = <0>; - pl022,interface = <0>; - pl022,com-mode = <0x0>; - pl022,rx-level-trig = <0>; - pl022,tx-level-trig = <0>; - }; -}; - -&smb0 { - /include/ "amd-seattle-xgbe-b.dtsi" -}; diff --git a/sys/gnu/dts/arm64/amlogic/meson-a1-ad401.dts b/sys/gnu/dts/arm64/amlogic/meson-a1-ad401.dts deleted file mode 100644 index 69c25c68c35..00000000000 --- a/sys/gnu/dts/arm64/amlogic/meson-a1-ad401.dts +++ /dev/null @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 Amlogic, Inc. All rights reserved. - */ - -/dts-v1/; - -#include "meson-a1.dtsi" - -/ { - compatible = "amlogic,ad401", "amlogic,a1"; - model = "Amlogic Meson A1 AD401 Development Board"; - - aliases { - serial0 = &uart_AO_B; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x8000000>; - }; -}; - -&uart_AO_B { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/amlogic/meson-a1.dtsi b/sys/gnu/dts/arm64/amlogic/meson-a1.dtsi deleted file mode 100644 index 4dec518c4dd..00000000000 --- a/sys/gnu/dts/arm64/amlogic/meson-a1.dtsi +++ /dev/null @@ -1,155 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 Amlogic, Inc. All rights reserved. - */ - -#include -#include -#include - -/ { - compatible = "amlogic,a1"; - - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a35"; - reg = <0x0 0x0>; - enable-method = "psci"; - next-level-cache = <&l2>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a35"; - reg = <0x0 0x1>; - enable-method = "psci"; - next-level-cache = <&l2>; - }; - - l2: l2-cache0 { - compatible = "cache"; - }; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - linux,cma { - compatible = "shared-dma-pool"; - reusable; - size = <0x0 0x800000>; - alignment = <0x0 0x400000>; - linux,cma-default; - }; - }; - - sm: secure-monitor { - compatible = "amlogic,meson-gxbb-sm"; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - apb: bus@fe000000 { - compatible = "simple-bus"; - reg = <0x0 0xfe000000 0x0 0x1000000>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x1000000>; - - - reset: reset-controller@0 { - compatible = "amlogic,meson-a1-reset"; - reg = <0x0 0x0 0x0 0x8c>; - #reset-cells = <1>; - }; - - periphs_pinctrl: pinctrl@0400 { - compatible = "amlogic,meson-a1-periphs-pinctrl"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - gpio: bank@0400 { - reg = <0x0 0x0400 0x0 0x003c>, - <0x0 0x0480 0x0 0x0118>; - reg-names = "mux", "gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&periphs_pinctrl 0 0 62>; - }; - - }; - - uart_AO: serial@1c00 { - compatible = "amlogic,meson-gx-uart", - "amlogic,meson-ao-uart"; - reg = <0x0 0x1c00 0x0 0x18>; - interrupts = ; - clocks = <&xtal>, <&xtal>, <&xtal>; - clock-names = "xtal", "pclk", "baud"; - status = "disabled"; - }; - - uart_AO_B: serial@2000 { - compatible = "amlogic,meson-gx-uart", - "amlogic,meson-ao-uart"; - reg = <0x0 0x2000 0x0 0x18>; - interrupts = ; - clocks = <&xtal>, <&xtal>, <&xtal>; - clock-names = "xtal", "pclk", "baud"; - status = "disabled"; - }; - }; - - gic: interrupt-controller@ff901000 { - compatible = "arm,gic-400"; - reg = <0x0 0xff901000 0x0 0x1000>, - <0x0 0xff902000 0x0 0x2000>, - <0x0 0xff904000 0x0 0x2000>, - <0x0 0xff906000 0x0 0x2000>; - interrupt-controller; - interrupts = ; - #interrupt-cells = <3>; - #address-cells = <0>; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - xtal: xtal-clk { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "xtal"; - #clock-cells = <0>; - }; -}; diff --git a/sys/gnu/dts/arm64/amlogic/meson-axg-s400.dts b/sys/gnu/dts/arm64/amlogic/meson-axg-s400.dts deleted file mode 100644 index 4cd2d595182..00000000000 --- a/sys/gnu/dts/arm64/amlogic/meson-axg-s400.dts +++ /dev/null @@ -1,586 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 Amlogic, Inc. All rights reserved. - */ - -/dts-v1/; - -#include "meson-axg.dtsi" -#include - -/ { - compatible = "amlogic,s400", "amlogic,a113d", "amlogic,meson-axg"; - model = "Amlogic Meson AXG S400 Development Board"; - - adc_keys { - compatible = "adc-keys"; - io-channels = <&saradc 0>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1800000>; - - button-next { - label = "Next"; - linux,code = ; - press-threshold-microvolt = <1116000>; /* 62% */ - }; - - button-prev { - label = "Previous"; - linux,code = ; - press-threshold-microvolt = <900000>; /* 50% */ - }; - - button-wifi { - label = "Wifi"; - linux,code = ; - press-threshold-microvolt = <684000>; /* 38% */ - }; - - button-up { - label = "Volume Up"; - linux,code = ; - press-threshold-microvolt = <468000>; /* 26% */ - }; - - button-down { - label = "Volume Down"; - linux,code = ; - press-threshold-microvolt = <252000>; /* 14% */ - }; - - button-voice { - label = "Voice"; - linux,code = ; - press-threshold-microvolt = <0>; /* 0% */ - }; - }; - - aliases { - serial0 = &uart_AO; - serial1 = &uart_A; - }; - - linein: audio-codec-0 { - #sound-dai-cells = <0>; - compatible = "everest,es7241"; - VDDA-supply = <&vcc_3v3>; - VDDP-supply = <&vcc_3v3>; - VDDD-supply = <&vcc_3v3>; - status = "okay"; - sound-name-prefix = "Linein"; - }; - - lineout: audio-codec-1 { - #sound-dai-cells = <0>; - compatible = "everest,es7154"; - VDD-supply = <&vcc_3v3>; - PVDD-supply = <&vcc_5v>; - status = "okay"; - sound-name-prefix = "Lineout"; - }; - - spdif_dit: audio-codec-2 { - #sound-dai-cells = <0>; - compatible = "linux,spdif-dit"; - status = "okay"; - sound-name-prefix = "DIT"; - }; - - dmics: audio-codec-3 { - #sound-dai-cells = <0>; - compatible = "dmic-codec"; - num-channels = <7>; - wakeup-delay-ms = <50>; - status = "okay"; - sound-name-prefix = "MIC"; - }; - - spdif_dir: audio-codec-4 { - #sound-dai-cells = <0>; - compatible = "linux,spdif-dir"; - status = "okay"; - sound-name-prefix = "DIR"; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x40000000>; - }; - - main_12v: regulator-main_12v { - compatible = "regulator-fixed"; - regulator-name = "12V"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-always-on; - }; - - vcc_3v3: regulator-vcc_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vddao_3v3>; - regulator-always-on; - }; - - vcc_5v: regulator-vcc_5v { - compatible = "regulator-fixed"; - regulator-name = "VCC5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&main_12v>; - - gpio = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vddao_3v3: regulator-vddao_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&main_12v>; - regulator-always-on; - }; - - vddio_ao18: regulator-vddio_ao18 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vddao_3v3>; - regulator-always-on; - }; - - vddio_boot: regulator-vddio_boot { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_BOOT"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vddao_3v3>; - regulator-always-on; - }; - - usb_pwr: regulator-usb_pwr { - compatible = "regulator-fixed"; - regulator-name = "USB_PWR"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc_5v>; - - gpio = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio GPIOX_7 GPIO_ACTIVE_LOW>; - clocks = <&wifi32k>; - clock-names = "ext_clock"; - }; - - speaker-leds { - compatible = "gpio-leds"; - - aled1 { - label = "speaker:aled1"; - gpios = <&gpio_speaker 7 0>; - }; - - aled2 { - label = "speaker:aled2"; - gpios = <&gpio_speaker 6 0>; - }; - - aled3 { - label = "speaker:aled3"; - gpios = <&gpio_speaker 5 0>; - }; - - aled4 { - label = "speaker:aled4"; - gpios = <&gpio_speaker 4 0>; - }; - - aled5 { - label = "speaker:aled5"; - gpios = <&gpio_speaker 3 0>; - }; - - aled6 { - label = "speaker:aled6"; - gpios = <&gpio_speaker 2 0>; - }; - }; - - sound { - compatible = "amlogic,axg-sound-card"; - model = "AXG-S400"; - audio-aux-devs = <&tdmin_a>, <&tdmin_b>, <&tdmin_c>, - <&tdmin_lb>, <&tdmout_c>; - audio-widgets = "Line", "Lineout", - "Line", "Linein", - "Speaker", "Speaker1 Left", - "Speaker", "Speaker1 Right"; - audio-routing = "TDMOUT_C IN 0", "FRDDR_A OUT 2", - "SPDIFOUT IN 0", "FRDDR_A OUT 3", - "TDMOUT_C IN 1", "FRDDR_B OUT 2", - "SPDIFOUT IN 1", "FRDDR_B OUT 3", - "TDMOUT_C IN 2", "FRDDR_C OUT 2", - "SPDIFOUT IN 2", "FRDDR_C OUT 3", - "TDM_C Playback", "TDMOUT_C OUT", - "TDMIN_A IN 2", "TDM_C Capture", - "TDMIN_A IN 5", "TDM_C Loopback", - "TDMIN_B IN 2", "TDM_C Capture", - "TDMIN_B IN 5", "TDM_C Loopback", - "TDMIN_C IN 2", "TDM_C Capture", - "TDMIN_C IN 5", "TDM_C Loopback", - "TDMIN_LB IN 2", "TDM_C Loopback", - "TDMIN_LB IN 5", "TDM_C Capture", - "TODDR_A IN 0", "TDMIN_A OUT", - "TODDR_B IN 0", "TDMIN_A OUT", - "TODDR_C IN 0", "TDMIN_A OUT", - "TODDR_A IN 1", "TDMIN_B OUT", - "TODDR_B IN 1", "TDMIN_B OUT", - "TODDR_C IN 1", "TDMIN_B OUT", - "TODDR_A IN 2", "TDMIN_C OUT", - "TODDR_B IN 2", "TDMIN_C OUT", - "TODDR_C IN 2", "TDMIN_C OUT", - "TODDR_A IN 3", "SPDIFIN Capture", - "TODDR_B IN 3", "SPDIFIN Capture", - "TODDR_C IN 3", "SPDIFIN Capture", - "TODDR_A IN 4", "PDM Capture", - "TODDR_B IN 4", "PDM Capture", - "TODDR_C IN 4", "PDM Capture", - "TODDR_A IN 6", "TDMIN_LB OUT", - "TODDR_B IN 6", "TDMIN_LB OUT", - "TODDR_C IN 6", "TDMIN_LB OUT", - "Lineout", "Lineout AOUTL", - "Lineout", "Lineout AOUTR", - "Speaker1 Left", "SPK1 OUT_A", - "Speaker1 Left", "SPK1 OUT_B", - "Speaker1 Right", "SPK1 OUT_C", - "Speaker1 Right", "SPK1 OUT_D", - "Linein AINL", "Linein", - "Linein AINR", "Linein"; - assigned-clocks = <&clkc CLKID_HIFI_PLL>, - <&clkc CLKID_MPLL0>, - <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; - assigned-clock-rates = <589824000>, - <270950400>, - <393216000>; - status = "okay"; - - dai-link-0 { - sound-dai = <&frddr_a>; - }; - - dai-link-1 { - sound-dai = <&frddr_b>; - }; - - dai-link-2 { - sound-dai = <&frddr_c>; - }; - - dai-link-3 { - sound-dai = <&toddr_a>; - }; - - dai-link-4 { - sound-dai = <&toddr_b>; - }; - - dai-link-5 { - sound-dai = <&toddr_c>; - }; - - dai-link-6 { - sound-dai = <&tdmif_c>; - dai-format = "i2s"; - dai-tdm-slot-tx-mask-2 = <1 1>; - dai-tdm-slot-rx-mask-1 = <1 1>; - mclk-fs = <256>; - - codec@0 { - sound-dai = <&lineout>; - }; - - codec@1 { - sound-dai = <&speaker_amp1>; - }; - - codec@2 { - sound-dai = <&linein>; - }; - - }; - - dai-link-7 { - sound-dai = <&spdifout>; - - codec { - sound-dai = <&spdif_dit>; - }; - }; - - dai-link-8 { - sound-dai = <&spdifin>; - - codec { - sound-dai = <&spdif_dir>; - }; - }; - - dai-link-9 { - sound-dai = <&pdm>; - - codec { - sound-dai = <&dmics>; - }; - }; - }; - - wifi32k: wifi32k { - compatible = "pwm-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - pwms = <&pwm_ab 0 30518 0>; /* PWM_A at 32.768KHz */ - }; -}; - -ðmac { - status = "okay"; - pinctrl-0 = <ð_rgmii_y_pins>; - pinctrl-names = "default"; - phy-handle = <ð_phy0>; - phy-mode = "rgmii"; - - mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - eth_phy0: ethernet-phy@0 { - /* Realtek RTL8211F (0x001cc916) */ - reg = <0>; - interrupt-parent = <&gpio_intc>; - interrupts = <98 IRQ_TYPE_LEVEL_LOW>; - eee-broken-1000t; - }; - }; -}; - -&frddr_a { - status = "okay"; -}; - -&frddr_b { - status = "okay"; -}; - -&frddr_c { - status = "okay"; -}; - -&ir { - status = "okay"; - pinctrl-0 = <&remote_input_ao_pins>; - pinctrl-names = "default"; -}; - -&i2c1 { - status = "okay"; - pinctrl-0 = <&i2c1_z_pins>; - pinctrl-names = "default"; - - speaker_amp1: audio-codec@1b { - compatible = "ti,tas5707"; - reg = <0x1b>; - reset-gpios = <&gpio_ao GPIOAO_4 GPIO_ACTIVE_LOW>; - #sound-dai-cells = <0>; - AVDD-supply = <&vcc_3v3>; - DVDD-supply = <&vcc_3v3>; - PVDD_A-supply = <&main_12v>; - PVDD_B-supply = <&main_12v>; - PVDD_C-supply = <&main_12v>; - PVDD_D-supply = <&main_12v>; - sound-name-prefix = "SPK1"; - }; -}; - -&i2c_AO { - status = "okay"; - pinctrl-0 = <&i2c_ao_sck_10_pins>, <&i2c_ao_sda_11_pins>; - pinctrl-names = "default"; - - gpio_speaker: gpio-controller@1f { - compatible = "nxp,pca9557"; - reg = <0x1f>; - gpio-controller; - #gpio-cells = <2>; - vcc-supply = <&vddao_3v3>; - }; -}; - -&pdm { - pinctrl-0 = <&pdm_dclk_a14_pins>, <&pdm_din0_pins>, - <&pdm_din1_pins>, <&pdm_din2_pins>, <&pdm_din3_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&pwm_ab { - status = "okay"; - pinctrl-0 = <&pwm_a_x20_pins>; - pinctrl-names = "default"; -}; - -&saradc { - status = "okay"; - vref-supply = <&vddio_ao18>; -}; - -/* wifi module */ -&sd_emmc_b { - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - - pinctrl-0 = <&sdio_pins>; - pinctrl-1 = <&sdio_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - sd-uhs-sdr104; - max-frequency = <200000000>; - non-removable; - disable-wp; - - mmc-pwrseq = <&sdio_pwrseq>; - - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddio_boot>; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - }; -}; - -/* emmc storage */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - max-frequency = <200000000>; - non-removable; - disable-wp; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - - mmc-pwrseq = <&emmc_pwrseq>; - - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&vddio_boot>; -}; - -&spdifin { - pinctrl-0 = <&spdif_in_a19_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&spdifout { - pinctrl-0 = <&spdif_out_a20_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&tdmif_a { - pinctrl-0 = <&tdma_sclk_pins>, <&tdma_fs_pins>, - <&tdma_din0_pins>, <&tdma_dout0_x15_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&tdmif_b { - pinctrl-0 = <&tdmb_sclk_pins>, <&tdmb_fs_pins>, - <&tdmb_din3_pins>, <&mclk_b_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&tdmif_c { - pinctrl-0 = <&tdmc_sclk_pins>, <&tdmc_fs_pins>, - <&tdmc_din1_pins>, <&tdmc_dout2_pins>, - <&mclk_c_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&tdmin_a { - status = "okay"; -}; - -&tdmin_b { - status = "okay"; -}; - -&tdmin_c { - status = "okay"; -}; - -&tdmin_lb { - status = "okay"; -}; - -&tdmout_c { - status = "okay"; -}; - -&toddr_a { - status = "okay"; -}; - -&toddr_b { - status = "okay"; -}; - -&toddr_c { - status = "okay"; -}; - -&uart_A { - status = "okay"; - pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; - pinctrl-names = "default"; - uart-has-rtscts; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - shutdown-gpios = <&gpio GPIOX_21 GPIO_ACTIVE_HIGH>; - }; -}; - -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; diff --git a/sys/gnu/dts/arm64/amlogic/meson-axg.dtsi b/sys/gnu/dts/arm64/amlogic/meson-axg.dtsi deleted file mode 100644 index aace3d32a3d..00000000000 --- a/sys/gnu/dts/arm64/amlogic/meson-axg.dtsi +++ /dev/null @@ -1,1774 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 Amlogic, Inc. All rights reserved. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/ { - compatible = "amlogic,meson-axg"; - - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - tdmif_a: audio-controller-0 { - compatible = "amlogic,axg-tdm-iface"; - #sound-dai-cells = <0>; - sound-name-prefix = "TDM_A"; - clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>, - <&clkc_audio AUD_CLKID_MST_A_SCLK>, - <&clkc_audio AUD_CLKID_MST_A_LRCLK>; - clock-names = "mclk", "sclk", "lrclk"; - status = "disabled"; - }; - - tdmif_b: audio-controller-1 { - compatible = "amlogic,axg-tdm-iface"; - #sound-dai-cells = <0>; - sound-name-prefix = "TDM_B"; - clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>, - <&clkc_audio AUD_CLKID_MST_B_SCLK>, - <&clkc_audio AUD_CLKID_MST_B_LRCLK>; - clock-names = "mclk", "sclk", "lrclk"; - status = "disabled"; - }; - - tdmif_c: audio-controller-2 { - compatible = "amlogic,axg-tdm-iface"; - #sound-dai-cells = <0>; - sound-name-prefix = "TDM_C"; - clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>, - <&clkc_audio AUD_CLKID_MST_C_SCLK>, - <&clkc_audio AUD_CLKID_MST_C_LRCLK>; - clock-names = "mclk", "sclk", "lrclk"; - status = "disabled"; - }; - - arm-pmu { - compatible = "arm,cortex-a53-pmu"; - interrupts = , - , - , - ; - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; - }; - - cpus { - #address-cells = <0x2>; - #size-cells = <0x0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x0>; - enable-method = "psci"; - next-level-cache = <&l2>; - clocks = <&scpi_dvfs 0>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x1>; - enable-method = "psci"; - next-level-cache = <&l2>; - clocks = <&scpi_dvfs 0>; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x2>; - enable-method = "psci"; - next-level-cache = <&l2>; - clocks = <&scpi_dvfs 0>; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x3>; - enable-method = "psci"; - next-level-cache = <&l2>; - clocks = <&scpi_dvfs 0>; - }; - - l2: l2-cache0 { - compatible = "cache"; - }; - }; - - sm: secure-monitor { - compatible = "amlogic,meson-gxbb-sm"; - }; - - efuse: efuse { - compatible = "amlogic,meson-gxbb-efuse"; - clocks = <&clkc CLKID_EFUSE>; - #address-cells = <1>; - #size-cells = <1>; - read-only; - secure-monitor = <&sm>; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - /* 16 MiB reserved for Hardware ROM Firmware */ - hwrom_reserved: hwrom@0 { - reg = <0x0 0x0 0x0 0x1000000>; - no-map; - }; - - /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */ - secmon_reserved: secmon@5000000 { - reg = <0x0 0x05000000 0x0 0x300000>; - no-map; - }; - }; - - scpi { - compatible = "arm,scpi-pre-1.0"; - mboxes = <&mailbox 1 &mailbox 2>; - shmem = <&cpu_scp_lpri &cpu_scp_hpri>; - - scpi_clocks: clocks { - compatible = "arm,scpi-clocks"; - - scpi_dvfs: clock-controller { - compatible = "arm,scpi-dvfs-clocks"; - #clock-cells = <1>; - clock-indices = <0>; - clock-output-names = "vcpu"; - }; - }; - - scpi_sensors: sensors { - compatible = "amlogic,meson-gxbb-scpi-sensors"; - #thermal-sensor-cells = <1>; - }; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - ethmac: ethernet@ff3f0000 { - compatible = "amlogic,meson-axg-dwmac", - "snps,dwmac-3.70a", - "snps,dwmac"; - reg = <0x0 0xff3f0000 0x0 0x10000>, - <0x0 0xff634540 0x0 0x8>; - interrupts = ; - interrupt-names = "macirq"; - clocks = <&clkc CLKID_ETH>, - <&clkc CLKID_FCLK_DIV2>, - <&clkc CLKID_MPLL2>; - clock-names = "stmmaceth", "clkin0", "clkin1"; - rx-fifo-depth = <4096>; - tx-fifo-depth = <2048>; - status = "disabled"; - }; - - pdm: audio-controller@ff632000 { - compatible = "amlogic,axg-pdm"; - reg = <0x0 0xff632000 0x0 0x34>; - #sound-dai-cells = <0>; - sound-name-prefix = "PDM"; - clocks = <&clkc_audio AUD_CLKID_PDM>, - <&clkc_audio AUD_CLKID_PDM_DCLK>, - <&clkc_audio AUD_CLKID_PDM_SYSCLK>; - clock-names = "pclk", "dclk", "sysclk"; - status = "disabled"; - }; - - periphs: bus@ff634000 { - compatible = "simple-bus"; - reg = <0x0 0xff634000 0x0 0x2000>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>; - - hwrng: rng@18 { - compatible = "amlogic,meson-rng"; - reg = <0x0 0x18 0x0 0x4>; - clocks = <&clkc CLKID_RNG0>; - clock-names = "core"; - }; - - pinctrl_periphs: pinctrl@480 { - compatible = "amlogic,meson-axg-periphs-pinctrl"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - gpio: bank@480 { - reg = <0x0 0x00480 0x0 0x40>, - <0x0 0x004e8 0x0 0x14>, - <0x0 0x00520 0x0 0x14>, - <0x0 0x00430 0x0 0x3c>; - reg-names = "mux", "pull", "pull-enable", "gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl_periphs 0 0 86>; - }; - - i2c0_pins: i2c0 { - mux { - groups = "i2c0_sck", - "i2c0_sda"; - function = "i2c0"; - bias-disable; - }; - }; - - i2c1_x_pins: i2c1_x { - mux { - groups = "i2c1_sck_x", - "i2c1_sda_x"; - function = "i2c1"; - bias-disable; - }; - }; - - i2c1_z_pins: i2c1_z { - mux { - groups = "i2c1_sck_z", - "i2c1_sda_z"; - function = "i2c1"; - bias-disable; - }; - }; - - i2c2_a_pins: i2c2_a { - mux { - groups = "i2c2_sck_a", - "i2c2_sda_a"; - function = "i2c2"; - bias-disable; - }; - }; - - i2c2_x_pins: i2c2_x { - mux { - groups = "i2c2_sck_x", - "i2c2_sda_x"; - function = "i2c2"; - bias-disable; - }; - }; - - i2c3_a6_pins: i2c3_a6 { - mux { - groups = "i2c3_sda_a6", - "i2c3_sck_a7"; - function = "i2c3"; - bias-disable; - }; - }; - - i2c3_a12_pins: i2c3_a12 { - mux { - groups = "i2c3_sda_a12", - "i2c3_sck_a13"; - function = "i2c3"; - bias-disable; - }; - }; - - i2c3_a19_pins: i2c3_a19 { - mux { - groups = "i2c3_sda_a19", - "i2c3_sck_a20"; - function = "i2c3"; - bias-disable; - }; - }; - - emmc_pins: emmc { - mux-0 { - groups = "emmc_nand_d0", - "emmc_nand_d1", - "emmc_nand_d2", - "emmc_nand_d3", - "emmc_nand_d4", - "emmc_nand_d5", - "emmc_nand_d6", - "emmc_nand_d7", - "emmc_cmd"; - function = "emmc"; - bias-pull-up; - }; - - mux-1 { - groups = "emmc_clk"; - function = "emmc"; - bias-disable; - }; - }; - - emmc_ds_pins: emmc_ds { - mux { - groups = "emmc_ds"; - function = "emmc"; - bias-pull-down; - }; - }; - - emmc_clk_gate_pins: emmc_clk_gate { - mux { - groups = "BOOT_8"; - function = "gpio_periphs"; - bias-pull-down; - }; - }; - - eth_rgmii_x_pins: eth-x-rgmii { - mux { - groups = "eth_mdio_x", - "eth_mdc_x", - "eth_rgmii_rx_clk_x", - "eth_rx_dv_x", - "eth_rxd0_x", - "eth_rxd1_x", - "eth_rxd2_rgmii", - "eth_rxd3_rgmii", - "eth_rgmii_tx_clk", - "eth_txen_x", - "eth_txd0_x", - "eth_txd1_x", - "eth_txd2_rgmii", - "eth_txd3_rgmii"; - function = "eth"; - bias-disable; - }; - }; - - eth_rgmii_y_pins: eth-y-rgmii { - mux { - groups = "eth_mdio_y", - "eth_mdc_y", - "eth_rgmii_rx_clk_y", - "eth_rx_dv_y", - "eth_rxd0_y", - "eth_rxd1_y", - "eth_rxd2_rgmii", - "eth_rxd3_rgmii", - "eth_rgmii_tx_clk", - "eth_txen_y", - "eth_txd0_y", - "eth_txd1_y", - "eth_txd2_rgmii", - "eth_txd3_rgmii"; - function = "eth"; - bias-disable; - }; - }; - - eth_rmii_x_pins: eth-x-rmii { - mux { - groups = "eth_mdio_x", - "eth_mdc_x", - "eth_rgmii_rx_clk_x", - "eth_rx_dv_x", - "eth_rxd0_x", - "eth_rxd1_x", - "eth_txen_x", - "eth_txd0_x", - "eth_txd1_x"; - function = "eth"; - bias-disable; - }; - }; - - eth_rmii_y_pins: eth-y-rmii { - mux { - groups = "eth_mdio_y", - "eth_mdc_y", - "eth_rgmii_rx_clk_y", - "eth_rx_dv_y", - "eth_rxd0_y", - "eth_rxd1_y", - "eth_txen_y", - "eth_txd0_y", - "eth_txd1_y"; - function = "eth"; - bias-disable; - }; - }; - - mclk_b_pins: mclk_b { - mux { - groups = "mclk_b"; - function = "mclk_b"; - bias-disable; - }; - }; - - mclk_c_pins: mclk_c { - mux { - groups = "mclk_c"; - function = "mclk_c"; - bias-disable; - }; - }; - - pdm_dclk_a14_pins: pdm_dclk_a14 { - mux { - groups = "pdm_dclk_a14"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_dclk_a19_pins: pdm_dclk_a19 { - mux { - groups = "pdm_dclk_a19"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_din0_pins: pdm_din0 { - mux { - groups = "pdm_din0"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_din1_pins: pdm_din1 { - mux { - groups = "pdm_din1"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_din2_pins: pdm_din2 { - mux { - groups = "pdm_din2"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_din3_pins: pdm_din3 { - mux { - groups = "pdm_din3"; - function = "pdm"; - bias-disable; - }; - }; - - pwm_a_a_pins: pwm_a_a { - mux { - groups = "pwm_a_a"; - function = "pwm_a"; - bias-disable; - }; - }; - - pwm_a_x18_pins: pwm_a_x18 { - mux { - groups = "pwm_a_x18"; - function = "pwm_a"; - bias-disable; - }; - }; - - pwm_a_x20_pins: pwm_a_x20 { - mux { - groups = "pwm_a_x20"; - function = "pwm_a"; - bias-disable; - }; - }; - - pwm_a_z_pins: pwm_a_z { - mux { - groups = "pwm_a_z"; - function = "pwm_a"; - bias-disable; - }; - }; - - pwm_b_a_pins: pwm_b_a { - mux { - groups = "pwm_b_a"; - function = "pwm_b"; - bias-disable; - }; - }; - - pwm_b_x_pins: pwm_b_x { - mux { - groups = "pwm_b_x"; - function = "pwm_b"; - bias-disable; - }; - }; - - pwm_b_z_pins: pwm_b_z { - mux { - groups = "pwm_b_z"; - function = "pwm_b"; - bias-disable; - }; - }; - - pwm_c_a_pins: pwm_c_a { - mux { - groups = "pwm_c_a"; - function = "pwm_c"; - bias-disable; - }; - }; - - pwm_c_x10_pins: pwm_c_x10 { - mux { - groups = "pwm_c_x10"; - function = "pwm_c"; - bias-disable; - }; - }; - - pwm_c_x17_pins: pwm_c_x17 { - mux { - groups = "pwm_c_x17"; - function = "pwm_c"; - bias-disable; - }; - }; - - pwm_d_x11_pins: pwm_d_x11 { - mux { - groups = "pwm_d_x11"; - function = "pwm_d"; - bias-disable; - }; - }; - - pwm_d_x16_pins: pwm_d_x16 { - mux { - groups = "pwm_d_x16"; - function = "pwm_d"; - bias-disable; - }; - }; - - sdio_pins: sdio { - mux-0 { - groups = "sdio_d0", - "sdio_d1", - "sdio_d2", - "sdio_d3", - "sdio_cmd"; - function = "sdio"; - bias-pull-up; - }; - - mux-1 { - groups = "sdio_clk"; - function = "sdio"; - bias-disable; - }; - }; - - sdio_clk_gate_pins: sdio_clk_gate { - mux { - groups = "GPIOX_4"; - function = "gpio_periphs"; - bias-pull-down; - }; - }; - - spdif_in_z_pins: spdif_in_z { - mux { - groups = "spdif_in_z"; - function = "spdif_in"; - bias-disable; - }; - }; - - spdif_in_a1_pins: spdif_in_a1 { - mux { - groups = "spdif_in_a1"; - function = "spdif_in"; - bias-disable; - }; - }; - - spdif_in_a7_pins: spdif_in_a7 { - mux { - groups = "spdif_in_a7"; - function = "spdif_in"; - bias-disable; - }; - }; - - spdif_in_a19_pins: spdif_in_a19 { - mux { - groups = "spdif_in_a19"; - function = "spdif_in"; - bias-disable; - }; - }; - - spdif_in_a20_pins: spdif_in_a20 { - mux { - groups = "spdif_in_a20"; - function = "spdif_in"; - bias-disable; - }; - }; - - spdif_out_a1_pins: spdif_out_a1 { - mux { - groups = "spdif_out_a1"; - function = "spdif_out"; - bias-disable; - }; - }; - - spdif_out_a11_pins: spdif_out_a11 { - mux { - groups = "spdif_out_a11"; - function = "spdif_out"; - bias-disable; - }; - }; - - spdif_out_a19_pins: spdif_out_a19 { - mux { - groups = "spdif_out_a19"; - function = "spdif_out"; - bias-disable; - }; - }; - - spdif_out_a20_pins: spdif_out_a20 { - mux { - groups = "spdif_out_a20"; - function = "spdif_out"; - bias-disable; - }; - }; - - spdif_out_z_pins: spdif_out_z { - mux { - groups = "spdif_out_z"; - function = "spdif_out"; - bias-disable; - }; - }; - - spi0_pins: spi0 { - mux { - groups = "spi0_miso", - "spi0_mosi", - "spi0_clk"; - function = "spi0"; - bias-disable; - }; - }; - - spi0_ss0_pins: spi0_ss0 { - mux { - groups = "spi0_ss0"; - function = "spi0"; - bias-disable; - }; - }; - - spi0_ss1_pins: spi0_ss1 { - mux { - groups = "spi0_ss1"; - function = "spi0"; - bias-disable; - }; - }; - - spi0_ss2_pins: spi0_ss2 { - mux { - groups = "spi0_ss2"; - function = "spi0"; - bias-disable; - }; - }; - - spi1_a_pins: spi1_a { - mux { - groups = "spi1_miso_a", - "spi1_mosi_a", - "spi1_clk_a"; - function = "spi1"; - bias-disable; - }; - }; - - spi1_ss0_a_pins: spi1_ss0_a { - mux { - groups = "spi1_ss0_a"; - function = "spi1"; - bias-disable; - }; - }; - - spi1_ss1_pins: spi1_ss1 { - mux { - groups = "spi1_ss1"; - function = "spi1"; - bias-disable; - }; - }; - - spi1_x_pins: spi1_x { - mux { - groups = "spi1_miso_x", - "spi1_mosi_x", - "spi1_clk_x"; - function = "spi1"; - bias-disable; - }; - }; - - spi1_ss0_x_pins: spi1_ss0_x { - mux { - groups = "spi1_ss0_x"; - function = "spi1"; - bias-disable; - }; - }; - - tdma_din0_pins: tdma_din0 { - mux { - groups = "tdma_din0"; - function = "tdma"; - bias-disable; - }; - }; - - tdma_dout0_x14_pins: tdma_dout0_x14 { - mux { - groups = "tdma_dout0_x14"; - function = "tdma"; - bias-disable; - }; - }; - - tdma_dout0_x15_pins: tdma_dout0_x15 { - mux { - groups = "tdma_dout0_x15"; - function = "tdma"; - bias-disable; - }; - }; - - tdma_dout1_pins: tdma_dout1 { - mux { - groups = "tdma_dout1"; - function = "tdma"; - bias-disable; - }; - }; - - tdma_din1_pins: tdma_din1 { - mux { - groups = "tdma_din1"; - function = "tdma"; - bias-disable; - }; - }; - - tdma_fs_pins: tdma_fs { - mux { - groups = "tdma_fs"; - function = "tdma"; - bias-disable; - }; - }; - - tdma_fs_slv_pins: tdma_fs_slv { - mux { - groups = "tdma_fs_slv"; - function = "tdma"; - bias-disable; - }; - }; - - tdma_sclk_pins: tdma_sclk { - mux { - groups = "tdma_sclk"; - function = "tdma"; - bias-disable; - }; - }; - - tdma_sclk_slv_pins: tdma_sclk_slv { - mux { - groups = "tdma_sclk_slv"; - function = "tdma"; - bias-disable; - }; - }; - - tdmb_din0_pins: tdmb_din0 { - mux { - groups = "tdmb_din0"; - function = "tdmb"; - bias-disable; - }; - }; - - tdmb_din1_pins: tdmb_din1 { - mux { - groups = "tdmb_din1"; - function = "tdmb"; - bias-disable; - }; - }; - - tdmb_din2_pins: tdmb_din2 { - mux { - groups = "tdmb_din2"; - function = "tdmb"; - bias-disable; - }; - }; - - tdmb_din3_pins: tdmb_din3 { - mux { - groups = "tdmb_din3"; - function = "tdmb"; - bias-disable; - }; - }; - - tdmb_dout0_pins: tdmb_dout0 { - mux { - groups = "tdmb_dout0"; - function = "tdmb"; - bias-disable; - }; - }; - - tdmb_dout1_pins: tdmb_dout1 { - mux { - groups = "tdmb_dout1"; - function = "tdmb"; - bias-disable; - }; - }; - - tdmb_dout2_pins: tdmb_dout2 { - mux { - groups = "tdmb_dout2"; - function = "tdmb"; - bias-disable; - }; - }; - - tdmb_dout3_pins: tdmb_dout3 { - mux { - groups = "tdmb_dout3"; - function = "tdmb"; - bias-disable; - }; - }; - - tdmb_fs_pins: tdmb_fs { - mux { - groups = "tdmb_fs"; - function = "tdmb"; - bias-disable; - }; - }; - - tdmb_fs_slv_pins: tdmb_fs_slv { - mux { - groups = "tdmb_fs_slv"; - function = "tdmb"; - bias-disable; - }; - }; - - tdmb_sclk_pins: tdmb_sclk { - mux { - groups = "tdmb_sclk"; - function = "tdmb"; - bias-disable; - }; - }; - - tdmb_sclk_slv_pins: tdmb_sclk_slv { - mux { - groups = "tdmb_sclk_slv"; - function = "tdmb"; - bias-disable; - }; - }; - - tdmc_fs_pins: tdmc_fs { - mux { - groups = "tdmc_fs"; - function = "tdmc"; - bias-disable; - }; - }; - - tdmc_fs_slv_pins: tdmc_fs_slv { - mux { - groups = "tdmc_fs_slv"; - function = "tdmc"; - bias-disable; - }; - }; - - tdmc_sclk_pins: tdmc_sclk { - mux { - groups = "tdmc_sclk"; - function = "tdmc"; - bias-disable; - }; - }; - - tdmc_sclk_slv_pins: tdmc_sclk_slv { - mux { - groups = "tdmc_sclk_slv"; - function = "tdmc"; - bias-disable; - }; - }; - - tdmc_din0_pins: tdmc_din0 { - mux { - groups = "tdmc_din0"; - function = "tdmc"; - bias-disable; - }; - }; - - tdmc_din1_pins: tdmc_din1 { - mux { - groups = "tdmc_din1"; - function = "tdmc"; - bias-disable; - }; - }; - - tdmc_din2_pins: tdmc_din2 { - mux { - groups = "tdmc_din2"; - function = "tdmc"; - bias-disable; - }; - }; - - tdmc_din3_pins: tdmc_din3 { - mux { - groups = "tdmc_din3"; - function = "tdmc"; - bias-disable; - }; - }; - - tdmc_dout0_pins: tdmc_dout0 { - mux { - groups = "tdmc_dout0"; - function = "tdmc"; - bias-disable; - }; - }; - - tdmc_dout1_pins: tdmc_dout1 { - mux { - groups = "tdmc_dout1"; - function = "tdmc"; - bias-disable; - }; - }; - - tdmc_dout2_pins: tdmc_dout2 { - mux { - groups = "tdmc_dout2"; - function = "tdmc"; - bias-disable; - }; - }; - - tdmc_dout3_pins: tdmc_dout3 { - mux { - groups = "tdmc_dout3"; - function = "tdmc"; - bias-disable; - }; - }; - - uart_a_pins: uart_a { - mux { - groups = "uart_tx_a", - "uart_rx_a"; - function = "uart_a"; - bias-disable; - }; - }; - - uart_a_cts_rts_pins: uart_a_cts_rts { - mux { - groups = "uart_cts_a", - "uart_rts_a"; - function = "uart_a"; - bias-disable; - }; - }; - - uart_b_x_pins: uart_b_x { - mux { - groups = "uart_tx_b_x", - "uart_rx_b_x"; - function = "uart_b"; - bias-disable; - }; - }; - - uart_b_x_cts_rts_pins: uart_b_x_cts_rts { - mux { - groups = "uart_cts_b_x", - "uart_rts_b_x"; - function = "uart_b"; - bias-disable; - }; - }; - - uart_b_z_pins: uart_b_z { - mux { - groups = "uart_tx_b_z", - "uart_rx_b_z"; - function = "uart_b"; - bias-disable; - }; - }; - - uart_b_z_cts_rts_pins: uart_b_z_cts_rts { - mux { - groups = "uart_cts_b_z", - "uart_rts_b_z"; - function = "uart_b"; - bias-disable; - }; - }; - - uart_ao_b_z_pins: uart_ao_b_z { - mux { - groups = "uart_ao_tx_b_z", - "uart_ao_rx_b_z"; - function = "uart_ao_b_z"; - bias-disable; - }; - }; - - uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts { - mux { - groups = "uart_ao_cts_b_z", - "uart_ao_rts_b_z"; - function = "uart_ao_b_z"; - bias-disable; - }; - }; - }; - }; - - hiubus: bus@ff63c000 { - compatible = "simple-bus"; - reg = <0x0 0xff63c000 0x0 0x1c00>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>; - - sysctrl: system-controller@0 { - compatible = "amlogic,meson-axg-hhi-sysctrl", - "simple-mfd", "syscon"; - reg = <0 0 0 0x400>; - - clkc: clock-controller { - compatible = "amlogic,axg-clkc"; - #clock-cells = <1>; - clocks = <&xtal>; - clock-names = "xtal"; - }; - }; - }; - - mailbox: mailbox@ff63c404 { - compatible = "amlogic,meson-gxbb-mhu"; - reg = <0 0xff63c404 0 0x4c>; - interrupts = , - , - ; - #mbox-cells = <1>; - }; - - audio: bus@ff642000 { - compatible = "simple-bus"; - reg = <0x0 0xff642000 0x0 0x2000>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0xff642000 0x0 0x2000>; - - clkc_audio: clock-controller@0 { - compatible = "amlogic,axg-audio-clkc"; - reg = <0x0 0x0 0x0 0xb4>; - #clock-cells = <1>; - - clocks = <&clkc CLKID_AUDIO>, - <&clkc CLKID_MPLL0>, - <&clkc CLKID_MPLL1>, - <&clkc CLKID_MPLL2>, - <&clkc CLKID_MPLL3>, - <&clkc CLKID_HIFI_PLL>, - <&clkc CLKID_FCLK_DIV3>, - <&clkc CLKID_FCLK_DIV4>, - <&clkc CLKID_GP0_PLL>; - clock-names = "pclk", - "mst_in0", - "mst_in1", - "mst_in2", - "mst_in3", - "mst_in4", - "mst_in5", - "mst_in6", - "mst_in7"; - - resets = <&reset RESET_AUDIO>; - }; - - toddr_a: audio-controller@100 { - compatible = "amlogic,axg-toddr"; - reg = <0x0 0x100 0x0 0x2c>; - #sound-dai-cells = <0>; - sound-name-prefix = "TODDR_A"; - interrupts = ; - clocks = <&clkc_audio AUD_CLKID_TODDR_A>; - resets = <&arb AXG_ARB_TODDR_A>; - amlogic,fifo-depth = <512>; - status = "disabled"; - }; - - toddr_b: audio-controller@140 { - compatible = "amlogic,axg-toddr"; - reg = <0x0 0x140 0x0 0x2c>; - #sound-dai-cells = <0>; - sound-name-prefix = "TODDR_B"; - interrupts = ; - clocks = <&clkc_audio AUD_CLKID_TODDR_B>; - resets = <&arb AXG_ARB_TODDR_B>; - amlogic,fifo-depth = <256>; - status = "disabled"; - }; - - toddr_c: audio-controller@180 { - compatible = "amlogic,axg-toddr"; - reg = <0x0 0x180 0x0 0x2c>; - #sound-dai-cells = <0>; - sound-name-prefix = "TODDR_C"; - interrupts = ; - clocks = <&clkc_audio AUD_CLKID_TODDR_C>; - resets = <&arb AXG_ARB_TODDR_C>; - amlogic,fifo-depth = <256>; - status = "disabled"; - }; - - frddr_a: audio-controller@1c0 { - compatible = "amlogic,axg-frddr"; - reg = <0x0 0x1c0 0x0 0x2c>; - #sound-dai-cells = <0>; - sound-name-prefix = "FRDDR_A"; - interrupts = ; - clocks = <&clkc_audio AUD_CLKID_FRDDR_A>; - resets = <&arb AXG_ARB_FRDDR_A>; - amlogic,fifo-depth = <512>; - status = "disabled"; - }; - - frddr_b: audio-controller@200 { - compatible = "amlogic,axg-frddr"; - reg = <0x0 0x200 0x0 0x2c>; - #sound-dai-cells = <0>; - sound-name-prefix = "FRDDR_B"; - interrupts = ; - clocks = <&clkc_audio AUD_CLKID_FRDDR_B>; - resets = <&arb AXG_ARB_FRDDR_B>; - amlogic,fifo-depth = <256>; - status = "disabled"; - }; - - frddr_c: audio-controller@240 { - compatible = "amlogic,axg-frddr"; - reg = <0x0 0x240 0x0 0x2c>; - #sound-dai-cells = <0>; - sound-name-prefix = "FRDDR_C"; - interrupts = ; - clocks = <&clkc_audio AUD_CLKID_FRDDR_C>; - resets = <&arb AXG_ARB_FRDDR_C>; - amlogic,fifo-depth = <256>; - status = "disabled"; - }; - - arb: reset-controller@280 { - compatible = "amlogic,meson-axg-audio-arb"; - reg = <0x0 0x280 0x0 0x4>; - #reset-cells = <1>; - clocks = <&clkc_audio AUD_CLKID_DDR_ARB>; - }; - - tdmin_a: audio-controller@300 { - compatible = "amlogic,axg-tdmin"; - reg = <0x0 0x300 0x0 0x40>; - sound-name-prefix = "TDMIN_A"; - clocks = <&clkc_audio AUD_CLKID_TDMIN_A>, - <&clkc_audio AUD_CLKID_TDMIN_A_SCLK>, - <&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>, - <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>, - <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>; - clock-names = "pclk", "sclk", "sclk_sel", - "lrclk", "lrclk_sel"; - status = "disabled"; - }; - - tdmin_b: audio-controller@340 { - compatible = "amlogic,axg-tdmin"; - reg = <0x0 0x340 0x0 0x40>; - sound-name-prefix = "TDMIN_B"; - clocks = <&clkc_audio AUD_CLKID_TDMIN_B>, - <&clkc_audio AUD_CLKID_TDMIN_B_SCLK>, - <&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>, - <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>, - <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>; - clock-names = "pclk", "sclk", "sclk_sel", - "lrclk", "lrclk_sel"; - status = "disabled"; - }; - - tdmin_c: audio-controller@380 { - compatible = "amlogic,axg-tdmin"; - reg = <0x0 0x380 0x0 0x40>; - sound-name-prefix = "TDMIN_C"; - clocks = <&clkc_audio AUD_CLKID_TDMIN_C>, - <&clkc_audio AUD_CLKID_TDMIN_C_SCLK>, - <&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>, - <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>, - <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>; - clock-names = "pclk", "sclk", "sclk_sel", - "lrclk", "lrclk_sel"; - status = "disabled"; - }; - - tdmin_lb: audio-controller@3c0 { - compatible = "amlogic,axg-tdmin"; - reg = <0x0 0x3c0 0x0 0x40>; - sound-name-prefix = "TDMIN_LB"; - clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>, - <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>, - <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>, - <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>, - <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>; - clock-names = "pclk", "sclk", "sclk_sel", - "lrclk", "lrclk_sel"; - status = "disabled"; - }; - - spdifin: audio-controller@400 { - compatible = "amlogic,axg-spdifin"; - reg = <0x0 0x400 0x0 0x30>; - #sound-dai-cells = <0>; - sound-name-prefix = "SPDIFIN"; - interrupts = ; - clocks = <&clkc_audio AUD_CLKID_SPDIFIN>, - <&clkc_audio AUD_CLKID_SPDIFIN_CLK>; - clock-names = "pclk", "refclk"; - status = "disabled"; - }; - - spdifout: audio-controller@480 { - compatible = "amlogic,axg-spdifout"; - reg = <0x0 0x480 0x0 0x50>; - #sound-dai-cells = <0>; - sound-name-prefix = "SPDIFOUT"; - clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>, - <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>; - clock-names = "pclk", "mclk"; - status = "disabled"; - }; - - tdmout_a: audio-controller@500 { - compatible = "amlogic,axg-tdmout"; - reg = <0x0 0x500 0x0 0x40>; - sound-name-prefix = "TDMOUT_A"; - clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>, - <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>, - <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>, - <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>, - <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>; - clock-names = "pclk", "sclk", "sclk_sel", - "lrclk", "lrclk_sel"; - status = "disabled"; - }; - - tdmout_b: audio-controller@540 { - compatible = "amlogic,axg-tdmout"; - reg = <0x0 0x540 0x0 0x40>; - sound-name-prefix = "TDMOUT_B"; - clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>, - <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>, - <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>, - <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>, - <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>; - clock-names = "pclk", "sclk", "sclk_sel", - "lrclk", "lrclk_sel"; - status = "disabled"; - }; - - tdmout_c: audio-controller@580 { - compatible = "amlogic,axg-tdmout"; - reg = <0x0 0x580 0x0 0x40>; - sound-name-prefix = "TDMOUT_C"; - clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>, - <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>, - <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>, - <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>, - <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>; - clock-names = "pclk", "sclk", "sclk_sel", - "lrclk", "lrclk_sel"; - status = "disabled"; - }; - }; - - aobus: bus@ff800000 { - compatible = "simple-bus"; - reg = <0x0 0xff800000 0x0 0x100000>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>; - - sysctrl_AO: sys-ctrl@0 { - compatible = "amlogic,meson-axg-ao-sysctrl", "simple-mfd", "syscon"; - reg = <0x0 0x0 0x0 0x100>; - - clkc_AO: clock-controller { - compatible = "amlogic,meson-axg-aoclkc"; - #clock-cells = <1>; - #reset-cells = <1>; - clocks = <&xtal>, <&clkc CLKID_CLK81>; - clock-names = "xtal", "mpeg-clk"; - }; - }; - - pinctrl_aobus: pinctrl@14 { - compatible = "amlogic,meson-axg-aobus-pinctrl"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - gpio_ao: bank@14 { - reg = <0x0 0x00014 0x0 0x8>, - <0x0 0x0002c 0x0 0x4>, - <0x0 0x00024 0x0 0x8>; - reg-names = "mux", "pull", "gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl_aobus 0 0 15>; - }; - - i2c_ao_sck_4_pins: i2c_ao_sck_4 { - mux { - groups = "i2c_ao_sck_4"; - function = "i2c_ao"; - bias-disable; - }; - }; - - i2c_ao_sck_8_pins: i2c_ao_sck_8 { - mux { - groups = "i2c_ao_sck_8"; - function = "i2c_ao"; - bias-disable; - }; - }; - - i2c_ao_sck_10_pins: i2c_ao_sck_10 { - mux { - groups = "i2c_ao_sck_10"; - function = "i2c_ao"; - bias-disable; - }; - }; - - i2c_ao_sda_5_pins: i2c_ao_sda_5 { - mux { - groups = "i2c_ao_sda_5"; - function = "i2c_ao"; - bias-disable; - }; - }; - - i2c_ao_sda_9_pins: i2c_ao_sda_9 { - mux { - groups = "i2c_ao_sda_9"; - function = "i2c_ao"; - bias-disable; - }; - }; - - i2c_ao_sda_11_pins: i2c_ao_sda_11 { - mux { - groups = "i2c_ao_sda_11"; - function = "i2c_ao"; - bias-disable; - }; - }; - - remote_input_ao_pins: remote_input_ao { - mux { - groups = "remote_input_ao"; - function = "remote_input_ao"; - bias-disable; - }; - }; - - uart_ao_a_pins: uart_ao_a { - mux { - groups = "uart_ao_tx_a", - "uart_ao_rx_a"; - function = "uart_ao_a"; - bias-disable; - }; - }; - - uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts { - mux { - groups = "uart_ao_cts_a", - "uart_ao_rts_a"; - function = "uart_ao_a"; - bias-disable; - }; - }; - - uart_ao_b_pins: uart_ao_b { - mux { - groups = "uart_ao_tx_b", - "uart_ao_rx_b"; - function = "uart_ao_b"; - bias-disable; - }; - }; - - uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts { - mux { - groups = "uart_ao_cts_b", - "uart_ao_rts_b"; - function = "uart_ao_b"; - bias-disable; - }; - }; - }; - - sec_AO: ao-secure@140 { - compatible = "amlogic,meson-gx-ao-secure", "syscon"; - reg = <0x0 0x140 0x0 0x140>; - amlogic,has-chip-id; - }; - - pwm_AO_cd: pwm@2000 { - compatible = "amlogic,meson-axg-ao-pwm"; - reg = <0x0 0x02000 0x0 0x20>; - #pwm-cells = <3>; - status = "disabled"; - }; - - uart_AO: serial@3000 { - compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; - reg = <0x0 0x3000 0x0 0x18>; - interrupts = ; - clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>; - clock-names = "xtal", "pclk", "baud"; - status = "disabled"; - }; - - uart_AO_B: serial@4000 { - compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; - reg = <0x0 0x4000 0x0 0x18>; - interrupts = ; - clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>; - clock-names = "xtal", "pclk", "baud"; - status = "disabled"; - }; - - i2c_AO: i2c@5000 { - compatible = "amlogic,meson-axg-i2c"; - reg = <0x0 0x05000 0x0 0x20>; - interrupts = ; - clocks = <&clkc CLKID_AO_I2C>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - pwm_AO_ab: pwm@7000 { - compatible = "amlogic,meson-axg-ao-pwm"; - reg = <0x0 0x07000 0x0 0x20>; - #pwm-cells = <3>; - status = "disabled"; - }; - - ir: ir@8000 { - compatible = "amlogic,meson-gxbb-ir"; - reg = <0x0 0x8000 0x0 0x20>; - interrupts = ; - status = "disabled"; - }; - - saradc: adc@9000 { - compatible = "amlogic,meson-axg-saradc", - "amlogic,meson-saradc"; - reg = <0x0 0x9000 0x0 0x38>; - #io-channel-cells = <1>; - interrupts = ; - clocks = <&xtal>, - <&clkc_AO CLKID_AO_SAR_ADC>, - <&clkc_AO CLKID_AO_SAR_ADC_CLK>, - <&clkc_AO CLKID_AO_SAR_ADC_SEL>; - clock-names = "clkin", "core", "adc_clk", "adc_sel"; - status = "disabled"; - }; - }; - - gic: interrupt-controller@ffc01000 { - compatible = "arm,gic-400"; - reg = <0x0 0xffc01000 0 0x1000>, - <0x0 0xffc02000 0 0x2000>, - <0x0 0xffc04000 0 0x2000>, - <0x0 0xffc06000 0 0x2000>; - interrupt-controller; - interrupts = ; - #interrupt-cells = <3>; - #address-cells = <0>; - }; - - cbus: bus@ffd00000 { - compatible = "simple-bus"; - reg = <0x0 0xffd00000 0x0 0x25000>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>; - - reset: reset-controller@1004 { - compatible = "amlogic,meson-axg-reset"; - reg = <0x0 0x01004 0x0 0x9c>; - #reset-cells = <1>; - }; - - gpio_intc: interrupt-controller@f080 { - compatible = "amlogic,meson-axg-gpio-intc", - "amlogic,meson-gpio-intc"; - reg = <0x0 0xf080 0x0 0x10>; - interrupt-controller; - #interrupt-cells = <2>; - amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>; - }; - - watchdog@f0d0 { - compatible = "amlogic,meson-gxbb-wdt"; - reg = <0x0 0xf0d0 0x0 0x10>; - clocks = <&xtal>; - }; - - pwm_ab: pwm@1b000 { - compatible = "amlogic,meson-axg-ee-pwm"; - reg = <0x0 0x1b000 0x0 0x20>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm_cd: pwm@1a000 { - compatible = "amlogic,meson-axg-ee-pwm"; - reg = <0x0 0x1a000 0x0 0x20>; - #pwm-cells = <3>; - status = "disabled"; - }; - - spicc0: spi@13000 { - compatible = "amlogic,meson-axg-spicc"; - reg = <0x0 0x13000 0x0 0x3c>; - interrupts = ; - clocks = <&clkc CLKID_SPICC0>; - clock-names = "core"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spicc1: spi@15000 { - compatible = "amlogic,meson-axg-spicc"; - reg = <0x0 0x15000 0x0 0x3c>; - interrupts = ; - clocks = <&clkc CLKID_SPICC1>; - clock-names = "core"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - clk_msr: clock-measure@18000 { - compatible = "amlogic,meson-axg-clk-measure"; - reg = <0x0 0x18000 0x0 0x10>; - }; - - i2c3: i2c@1c000 { - compatible = "amlogic,meson-axg-i2c"; - reg = <0x0 0x1c000 0x0 0x20>; - interrupts = ; - clocks = <&clkc CLKID_I2C>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@1d000 { - compatible = "amlogic,meson-axg-i2c"; - reg = <0x0 0x1d000 0x0 0x20>; - interrupts = ; - clocks = <&clkc CLKID_I2C>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c1: i2c@1e000 { - compatible = "amlogic,meson-axg-i2c"; - reg = <0x0 0x1e000 0x0 0x20>; - interrupts = ; - clocks = <&clkc CLKID_I2C>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c0: i2c@1f000 { - compatible = "amlogic,meson-axg-i2c"; - reg = <0x0 0x1f000 0x0 0x20>; - interrupts = ; - clocks = <&clkc CLKID_I2C>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - uart_B: serial@23000 { - compatible = "amlogic,meson-gx-uart"; - reg = <0x0 0x23000 0x0 0x18>; - interrupts = ; - status = "disabled"; - clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; - clock-names = "xtal", "pclk", "baud"; - }; - - uart_A: serial@24000 { - compatible = "amlogic,meson-gx-uart"; - reg = <0x0 0x24000 0x0 0x18>; - interrupts = ; - status = "disabled"; - clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; - clock-names = "xtal", "pclk", "baud"; - }; - }; - - apb: bus@ffe00000 { - compatible = "simple-bus"; - reg = <0x0 0xffe00000 0x0 0x200000>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x200000>; - - sd_emmc_b: sd@5000 { - compatible = "amlogic,meson-axg-mmc"; - reg = <0x0 0x5000 0x0 0x800>; - interrupts = ; - status = "disabled"; - clocks = <&clkc CLKID_SD_EMMC_B>, - <&clkc CLKID_SD_EMMC_B_CLK0>, - <&clkc CLKID_FCLK_DIV2>; - clock-names = "core", "clkin0", "clkin1"; - resets = <&reset RESET_SD_EMMC_B>; - }; - - sd_emmc_c: mmc@7000 { - compatible = "amlogic,meson-axg-mmc"; - reg = <0x0 0x7000 0x0 0x800>; - interrupts = ; - status = "disabled"; - clocks = <&clkc CLKID_SD_EMMC_C>, - <&clkc CLKID_SD_EMMC_C_CLK0>, - <&clkc CLKID_FCLK_DIV2>; - clock-names = "core", "clkin0", "clkin1"; - resets = <&reset RESET_SD_EMMC_C>; - }; - }; - - sram: sram@fffc0000 { - compatible = "amlogic,meson-axg-sram", "mmio-sram"; - reg = <0x0 0xfffc0000 0x0 0x20000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x0 0xfffc0000 0x20000>; - - cpu_scp_lpri: scp-shmem@13000 { - compatible = "amlogic,meson-axg-scp-shmem"; - reg = <0x13000 0x400>; - }; - - cpu_scp_hpri: scp-shmem@13400 { - compatible = "amlogic,meson-axg-scp-shmem"; - reg = <0x13400 0x400>; - }; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - xtal: xtal-clk { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "xtal"; - #clock-cells = <0>; - }; -}; diff --git a/sys/gnu/dts/arm64/amlogic/meson-g12-common.dtsi b/sys/gnu/dts/arm64/amlogic/meson-g12-common.dtsi deleted file mode 100644 index abe04f4ad7d..00000000000 --- a/sys/gnu/dts/arm64/amlogic/meson-g12-common.dtsi +++ /dev/null @@ -1,2275 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2018 Amlogic, Inc. All rights reserved. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -/ { - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - chosen { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - simplefb_cvbs: framebuffer-cvbs { - compatible = "amlogic,simple-framebuffer", - "simple-framebuffer"; - amlogic,pipeline = "vpu-cvbs"; - clocks = <&clkc CLKID_HDMI>, - <&clkc CLKID_HTX_PCLK>, - <&clkc CLKID_VPU_INTR>; - status = "disabled"; - }; - - simplefb_hdmi: framebuffer-hdmi { - compatible = "amlogic,simple-framebuffer", - "simple-framebuffer"; - amlogic,pipeline = "vpu-hdmi"; - clocks = <&clkc CLKID_HDMI>, - <&clkc CLKID_HTX_PCLK>, - <&clkc CLKID_VPU_INTR>; - status = "disabled"; - }; - }; - - efuse: efuse { - compatible = "amlogic,meson-gxbb-efuse"; - clocks = <&clkc CLKID_EFUSE>; - #address-cells = <1>; - #size-cells = <1>; - read-only; - secure-monitor = <&sm>; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - /* 3 MiB reserved for ARM Trusted Firmware (BL31) */ - secmon_reserved: secmon@5000000 { - reg = <0x0 0x05000000 0x0 0x300000>; - no-map; - }; - - linux,cma { - compatible = "shared-dma-pool"; - reusable; - size = <0x0 0x10000000>; - alignment = <0x0 0x400000>; - linux,cma-default; - }; - }; - - sm: secure-monitor { - compatible = "amlogic,meson-gxbb-sm"; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - pcie: pcie@fc000000 { - compatible = "amlogic,g12a-pcie", "snps,dw-pcie"; - reg = <0x0 0xfc000000 0x0 0x400000 - 0x0 0xff648000 0x0 0x2000 - 0x0 0xfc400000 0x0 0x200000>; - reg-names = "elbi", "cfg", "config"; - interrupts = ; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; - bus-range = <0x0 0xff>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges = <0x81000000 0 0 0x0 0xfc600000 0 0x00100000 - 0x82000000 0 0xfc700000 0x0 0xfc700000 0 0x1900000>; - - clocks = <&clkc CLKID_PCIE_PHY - &clkc CLKID_PCIE_COMB - &clkc CLKID_PCIE_PLL>; - clock-names = "general", - "pclk", - "port"; - resets = <&reset RESET_PCIE_CTRL_A>, - <&reset RESET_PCIE_APB>; - reset-names = "port", - "apb"; - num-lanes = <1>; - phys = <&usb3_pcie_phy PHY_TYPE_PCIE>; - phy-names = "pcie"; - status = "disabled"; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay = <1000>; - polling-delay-passive = <100>; - thermal-sensors = <&cpu_temp>; - - trips { - cpu_passive: cpu-passive { - temperature = <85000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - - cpu_hot: cpu-hot { - temperature = <95000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "hot"; - }; - - cpu_critical: cpu-critical { - temperature = <110000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "critical"; - }; - }; - }; - - ddr_thermal: ddr-thermal { - polling-delay = <1000>; - polling-delay-passive = <100>; - thermal-sensors = <&ddr_temp>; - - trips { - ddr_passive: ddr-passive { - temperature = <85000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - - ddr_critical: ddr-critical { - temperature = <110000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "critical"; - }; - }; - - cooling-maps { - map { - trip = <&ddr_passive>; - cooling-device = <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - }; - - ethmac: ethernet@ff3f0000 { - compatible = "amlogic,meson-axg-dwmac", - "snps,dwmac-3.70a", - "snps,dwmac"; - reg = <0x0 0xff3f0000 0x0 0x10000>, - <0x0 0xff634540 0x0 0x8>; - interrupts = ; - interrupt-names = "macirq"; - clocks = <&clkc CLKID_ETH>, - <&clkc CLKID_FCLK_DIV2>, - <&clkc CLKID_MPLL2>; - clock-names = "stmmaceth", "clkin0", "clkin1"; - rx-fifo-depth = <4096>; - tx-fifo-depth = <2048>; - status = "disabled"; - - mdio0: mdio { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - }; - }; - - apb: bus@ff600000 { - compatible = "simple-bus"; - reg = <0x0 0xff600000 0x0 0x200000>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0xff600000 0x0 0x200000>; - - hdmi_tx: hdmi-tx@0 { - compatible = "amlogic,meson-g12a-dw-hdmi"; - reg = <0x0 0x0 0x0 0x10000>; - interrupts = ; - resets = <&reset RESET_HDMITX_CAPB3>, - <&reset RESET_HDMITX_PHY>, - <&reset RESET_HDMITX>; - reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy"; - clocks = <&clkc CLKID_HDMI>, - <&clkc CLKID_HTX_PCLK>, - <&clkc CLKID_VPU_INTR>; - clock-names = "isfr", "iahb", "venci"; - #address-cells = <1>; - #size-cells = <0>; - #sound-dai-cells = <0>; - status = "disabled"; - - /* VPU VENC Input */ - hdmi_tx_venc_port: port@0 { - reg = <0>; - - hdmi_tx_in: endpoint { - remote-endpoint = <&hdmi_tx_out>; - }; - }; - - /* TMDS Output */ - hdmi_tx_tmds_port: port@1 { - reg = <1>; - }; - }; - - apb_efuse: bus@30000 { - compatible = "simple-bus"; - reg = <0x0 0x30000 0x0 0x2000>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0x30000 0x0 0x2000>; - - hwrng: rng@218 { - compatible = "amlogic,meson-rng"; - reg = <0x0 0x218 0x0 0x4>; - }; - }; - - periphs: bus@34400 { - compatible = "simple-bus"; - reg = <0x0 0x34400 0x0 0x400>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0x34400 0x0 0x400>; - - periphs_pinctrl: pinctrl@40 { - compatible = "amlogic,meson-g12a-periphs-pinctrl"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - gpio: bank@40 { - reg = <0x0 0x40 0x0 0x4c>, - <0x0 0xe8 0x0 0x18>, - <0x0 0x120 0x0 0x18>, - <0x0 0x2c0 0x0 0x40>, - <0x0 0x340 0x0 0x1c>; - reg-names = "gpio", - "pull", - "pull-enable", - "mux", - "ds"; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&periphs_pinctrl 0 0 86>; - }; - - cec_ao_a_h_pins: cec_ao_a_h { - mux { - groups = "cec_ao_a_h"; - function = "cec_ao_a_h"; - bias-disable; - }; - }; - - cec_ao_b_h_pins: cec_ao_b_h { - mux { - groups = "cec_ao_b_h"; - function = "cec_ao_b_h"; - bias-disable; - }; - }; - - emmc_pins: emmc { - mux-0 { - groups = "emmc_nand_d0", - "emmc_nand_d1", - "emmc_nand_d2", - "emmc_nand_d3", - "emmc_nand_d4", - "emmc_nand_d5", - "emmc_nand_d6", - "emmc_nand_d7", - "emmc_cmd"; - function = "emmc"; - bias-pull-up; - drive-strength-microamp = <4000>; - }; - - mux-1 { - groups = "emmc_clk"; - function = "emmc"; - bias-disable; - drive-strength-microamp = <4000>; - }; - }; - - emmc_ds_pins: emmc-ds { - mux { - groups = "emmc_nand_ds"; - function = "emmc"; - bias-pull-down; - drive-strength-microamp = <4000>; - }; - }; - - emmc_clk_gate_pins: emmc_clk_gate { - mux { - groups = "BOOT_8"; - function = "gpio_periphs"; - bias-pull-down; - drive-strength-microamp = <4000>; - }; - }; - - hdmitx_ddc_pins: hdmitx_ddc { - mux { - groups = "hdmitx_sda", - "hdmitx_sck"; - function = "hdmitx"; - bias-disable; - drive-strength-microamp = <4000>; - }; - }; - - hdmitx_hpd_pins: hdmitx_hpd { - mux { - groups = "hdmitx_hpd_in"; - function = "hdmitx"; - bias-disable; - }; - }; - - - i2c0_sda_c_pins: i2c0-sda-c { - mux { - groups = "i2c0_sda_c"; - function = "i2c0"; - bias-disable; - drive-strength-microamp = <3000>; - - }; - }; - - i2c0_sck_c_pins: i2c0-sck-c { - mux { - groups = "i2c0_sck_c"; - function = "i2c0"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c0_sda_z0_pins: i2c0-sda-z0 { - mux { - groups = "i2c0_sda_z0"; - function = "i2c0"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c0_sck_z1_pins: i2c0-sck-z1 { - mux { - groups = "i2c0_sck_z1"; - function = "i2c0"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c0_sda_z7_pins: i2c0-sda-z7 { - mux { - groups = "i2c0_sda_z7"; - function = "i2c0"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c0_sda_z8_pins: i2c0-sda-z8 { - mux { - groups = "i2c0_sda_z8"; - function = "i2c0"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c1_sda_x_pins: i2c1-sda-x { - mux { - groups = "i2c1_sda_x"; - function = "i2c1"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c1_sck_x_pins: i2c1-sck-x { - mux { - groups = "i2c1_sck_x"; - function = "i2c1"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c1_sda_h2_pins: i2c1-sda-h2 { - mux { - groups = "i2c1_sda_h2"; - function = "i2c1"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c1_sck_h3_pins: i2c1-sck-h3 { - mux { - groups = "i2c1_sck_h3"; - function = "i2c1"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c1_sda_h6_pins: i2c1-sda-h6 { - mux { - groups = "i2c1_sda_h6"; - function = "i2c1"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c1_sck_h7_pins: i2c1-sck-h7 { - mux { - groups = "i2c1_sck_h7"; - function = "i2c1"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c2_sda_x_pins: i2c2-sda-x { - mux { - groups = "i2c2_sda_x"; - function = "i2c2"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c2_sck_x_pins: i2c2-sck-x { - mux { - groups = "i2c2_sck_x"; - function = "i2c2"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c2_sda_z_pins: i2c2-sda-z { - mux { - groups = "i2c2_sda_z"; - function = "i2c2"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c2_sck_z_pins: i2c2-sck-z { - mux { - groups = "i2c2_sck_z"; - function = "i2c2"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c3_sda_h_pins: i2c3-sda-h { - mux { - groups = "i2c3_sda_h"; - function = "i2c3"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c3_sck_h_pins: i2c3-sck-h { - mux { - groups = "i2c3_sck_h"; - function = "i2c3"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c3_sda_a_pins: i2c3-sda-a { - mux { - groups = "i2c3_sda_a"; - function = "i2c3"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c3_sck_a_pins: i2c3-sck-a { - mux { - groups = "i2c3_sck_a"; - function = "i2c3"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - mclk0_a_pins: mclk0-a { - mux { - groups = "mclk0_a"; - function = "mclk0"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - mclk1_a_pins: mclk1-a { - mux { - groups = "mclk1_a"; - function = "mclk1"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - mclk1_x_pins: mclk1-x { - mux { - groups = "mclk1_x"; - function = "mclk1"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - mclk1_z_pins: mclk1-z { - mux { - groups = "mclk1_z"; - function = "mclk1"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - pdm_din0_a_pins: pdm-din0-a { - mux { - groups = "pdm_din0_a"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_din0_c_pins: pdm-din0-c { - mux { - groups = "pdm_din0_c"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_din0_x_pins: pdm-din0-x { - mux { - groups = "pdm_din0_x"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_din0_z_pins: pdm-din0-z { - mux { - groups = "pdm_din0_z"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_din1_a_pins: pdm-din1-a { - mux { - groups = "pdm_din1_a"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_din1_c_pins: pdm-din1-c { - mux { - groups = "pdm_din1_c"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_din1_x_pins: pdm-din1-x { - mux { - groups = "pdm_din1_x"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_din1_z_pins: pdm-din1-z { - mux { - groups = "pdm_din1_z"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_din2_a_pins: pdm-din2-a { - mux { - groups = "pdm_din2_a"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_din2_c_pins: pdm-din2-c { - mux { - groups = "pdm_din2_c"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_din2_x_pins: pdm-din2-x { - mux { - groups = "pdm_din2_x"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_din2_z_pins: pdm-din2-z { - mux { - groups = "pdm_din2_z"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_din3_a_pins: pdm-din3-a { - mux { - groups = "pdm_din3_a"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_din3_c_pins: pdm-din3-c { - mux { - groups = "pdm_din3_c"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_din3_x_pins: pdm-din3-x { - mux { - groups = "pdm_din3_x"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_din3_z_pins: pdm-din3-z { - mux { - groups = "pdm_din3_z"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_dclk_a_pins: pdm-dclk-a { - mux { - groups = "pdm_dclk_a"; - function = "pdm"; - bias-disable; - drive-strength-microamp = <500>; - }; - }; - - pdm_dclk_c_pins: pdm-dclk-c { - mux { - groups = "pdm_dclk_c"; - function = "pdm"; - bias-disable; - drive-strength-microamp = <500>; - }; - }; - - pdm_dclk_x_pins: pdm-dclk-x { - mux { - groups = "pdm_dclk_x"; - function = "pdm"; - bias-disable; - drive-strength-microamp = <500>; - }; - }; - - pdm_dclk_z_pins: pdm-dclk-z { - mux { - groups = "pdm_dclk_z"; - function = "pdm"; - bias-disable; - drive-strength-microamp = <500>; - }; - }; - - pwm_a_pins: pwm-a { - mux { - groups = "pwm_a"; - function = "pwm_a"; - bias-disable; - }; - }; - - pwm_b_x7_pins: pwm-b-x7 { - mux { - groups = "pwm_b_x7"; - function = "pwm_b"; - bias-disable; - }; - }; - - pwm_b_x19_pins: pwm-b-x19 { - mux { - groups = "pwm_b_x19"; - function = "pwm_b"; - bias-disable; - }; - }; - - pwm_c_c_pins: pwm-c-c { - mux { - groups = "pwm_c_c"; - function = "pwm_c"; - bias-disable; - }; - }; - - pwm_c_x5_pins: pwm-c-x5 { - mux { - groups = "pwm_c_x5"; - function = "pwm_c"; - bias-disable; - }; - }; - - pwm_c_x8_pins: pwm-c-x8 { - mux { - groups = "pwm_c_x8"; - function = "pwm_c"; - bias-disable; - }; - }; - - pwm_d_x3_pins: pwm-d-x3 { - mux { - groups = "pwm_d_x3"; - function = "pwm_d"; - bias-disable; - }; - }; - - pwm_d_x6_pins: pwm-d-x6 { - mux { - groups = "pwm_d_x6"; - function = "pwm_d"; - bias-disable; - }; - }; - - pwm_e_pins: pwm-e { - mux { - groups = "pwm_e"; - function = "pwm_e"; - bias-disable; - }; - }; - - pwm_f_x_pins: pwm-f-x { - mux { - groups = "pwm_f_x"; - function = "pwm_f"; - bias-disable; - }; - }; - - pwm_f_h_pins: pwm-f-h { - mux { - groups = "pwm_f_h"; - function = "pwm_f"; - bias-disable; - }; - }; - - sdcard_c_pins: sdcard_c { - mux-0 { - groups = "sdcard_d0_c", - "sdcard_d1_c", - "sdcard_d2_c", - "sdcard_d3_c", - "sdcard_cmd_c"; - function = "sdcard"; - bias-pull-up; - drive-strength-microamp = <4000>; - }; - - mux-1 { - groups = "sdcard_clk_c"; - function = "sdcard"; - bias-disable; - drive-strength-microamp = <4000>; - }; - }; - - sdcard_clk_gate_c_pins: sdcard_clk_gate_c { - mux { - groups = "GPIOC_4"; - function = "gpio_periphs"; - bias-pull-down; - drive-strength-microamp = <4000>; - }; - }; - - sdcard_z_pins: sdcard_z { - mux-0 { - groups = "sdcard_d0_z", - "sdcard_d1_z", - "sdcard_d2_z", - "sdcard_d3_z", - "sdcard_cmd_z"; - function = "sdcard"; - bias-pull-up; - drive-strength-microamp = <4000>; - }; - - mux-1 { - groups = "sdcard_clk_z"; - function = "sdcard"; - bias-disable; - drive-strength-microamp = <4000>; - }; - }; - - sdcard_clk_gate_z_pins: sdcard_clk_gate_z { - mux { - groups = "GPIOZ_6"; - function = "gpio_periphs"; - bias-pull-down; - drive-strength-microamp = <4000>; - }; - }; - - sdio_pins: sdio { - mux { - groups = "sdio_d0", - "sdio_d1", - "sdio_d2", - "sdio_d3", - "sdio_clk", - "sdio_cmd"; - function = "sdio"; - bias-disable; - drive-strength-microamp = <4000>; - }; - }; - - sdio_clk_gate_pins: sdio_clk_gate { - mux { - groups = "GPIOX_4"; - function = "gpio_periphs"; - bias-pull-down; - drive-strength-microamp = <4000>; - }; - }; - - spdif_in_a10_pins: spdif-in-a10 { - mux { - groups = "spdif_in_a10"; - function = "spdif_in"; - bias-disable; - }; - }; - - spdif_in_a12_pins: spdif-in-a12 { - mux { - groups = "spdif_in_a12"; - function = "spdif_in"; - bias-disable; - }; - }; - - spdif_in_h_pins: spdif-in-h { - mux { - groups = "spdif_in_h"; - function = "spdif_in"; - bias-disable; - }; - }; - - spdif_out_h_pins: spdif-out-h { - mux { - groups = "spdif_out_h"; - function = "spdif_out"; - drive-strength-microamp = <500>; - bias-disable; - }; - }; - - spdif_out_a11_pins: spdif-out-a11 { - mux { - groups = "spdif_out_a11"; - function = "spdif_out"; - drive-strength-microamp = <500>; - bias-disable; - }; - }; - - spdif_out_a13_pins: spdif-out-a13 { - mux { - groups = "spdif_out_a13"; - function = "spdif_out"; - drive-strength-microamp = <500>; - bias-disable; - }; - }; - - tdm_a_din0_pins: tdm-a-din0 { - mux { - groups = "tdm_a_din0"; - function = "tdm_a"; - bias-disable; - }; - }; - - - tdm_a_din1_pins: tdm-a-din1 { - mux { - groups = "tdm_a_din1"; - function = "tdm_a"; - bias-disable; - }; - }; - - tdm_a_dout0_pins: tdm-a-dout0 { - mux { - groups = "tdm_a_dout0"; - function = "tdm_a"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_a_dout1_pins: tdm-a-dout1 { - mux { - groups = "tdm_a_dout1"; - function = "tdm_a"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_a_fs_pins: tdm-a-fs { - mux { - groups = "tdm_a_fs"; - function = "tdm_a"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_a_sclk_pins: tdm-a-sclk { - mux { - groups = "tdm_a_sclk"; - function = "tdm_a"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_a_slv_fs_pins: tdm-a-slv-fs { - mux { - groups = "tdm_a_slv_fs"; - function = "tdm_a"; - bias-disable; - }; - }; - - - tdm_a_slv_sclk_pins: tdm-a-slv-sclk { - mux { - groups = "tdm_a_slv_sclk"; - function = "tdm_a"; - bias-disable; - }; - }; - - tdm_b_din0_pins: tdm-b-din0 { - mux { - groups = "tdm_b_din0"; - function = "tdm_b"; - bias-disable; - }; - }; - - tdm_b_din1_pins: tdm-b-din1 { - mux { - groups = "tdm_b_din1"; - function = "tdm_b"; - bias-disable; - }; - }; - - tdm_b_din2_pins: tdm-b-din2 { - mux { - groups = "tdm_b_din2"; - function = "tdm_b"; - bias-disable; - }; - }; - - tdm_b_din3_a_pins: tdm-b-din3-a { - mux { - groups = "tdm_b_din3_a"; - function = "tdm_b"; - bias-disable; - }; - }; - - tdm_b_din3_h_pins: tdm-b-din3-h { - mux { - groups = "tdm_b_din3_h"; - function = "tdm_b"; - bias-disable; - }; - }; - - tdm_b_dout0_pins: tdm-b-dout0 { - mux { - groups = "tdm_b_dout0"; - function = "tdm_b"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_b_dout1_pins: tdm-b-dout1 { - mux { - groups = "tdm_b_dout1"; - function = "tdm_b"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_b_dout2_pins: tdm-b-dout2 { - mux { - groups = "tdm_b_dout2"; - function = "tdm_b"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_b_dout3_a_pins: tdm-b-dout3-a { - mux { - groups = "tdm_b_dout3_a"; - function = "tdm_b"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_b_dout3_h_pins: tdm-b-dout3-h { - mux { - groups = "tdm_b_dout3_h"; - function = "tdm_b"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_b_fs_pins: tdm-b-fs { - mux { - groups = "tdm_b_fs"; - function = "tdm_b"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_b_sclk_pins: tdm-b-sclk { - mux { - groups = "tdm_b_sclk"; - function = "tdm_b"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_b_slv_fs_pins: tdm-b-slv-fs { - mux { - groups = "tdm_b_slv_fs"; - function = "tdm_b"; - bias-disable; - }; - }; - - tdm_b_slv_sclk_pins: tdm-b-slv-sclk { - mux { - groups = "tdm_b_slv_sclk"; - function = "tdm_b"; - bias-disable; - }; - }; - - tdm_c_din0_a_pins: tdm-c-din0-a { - mux { - groups = "tdm_c_din0_a"; - function = "tdm_c"; - bias-disable; - }; - }; - - tdm_c_din0_z_pins: tdm-c-din0-z { - mux { - groups = "tdm_c_din0_z"; - function = "tdm_c"; - bias-disable; - }; - }; - - tdm_c_din1_a_pins: tdm-c-din1-a { - mux { - groups = "tdm_c_din1_a"; - function = "tdm_c"; - bias-disable; - }; - }; - - tdm_c_din1_z_pins: tdm-c-din1-z { - mux { - groups = "tdm_c_din1_z"; - function = "tdm_c"; - bias-disable; - }; - }; - - tdm_c_din2_a_pins: tdm-c-din2-a { - mux { - groups = "tdm_c_din2_a"; - function = "tdm_c"; - bias-disable; - }; - }; - - eth_leds_pins: eth-leds { - mux { - groups = "eth_link_led", - "eth_act_led"; - function = "eth"; - bias-disable; - }; - }; - - eth_pins: eth { - mux { - groups = "eth_mdio", - "eth_mdc", - "eth_rgmii_rx_clk", - "eth_rx_dv", - "eth_rxd0", - "eth_rxd1", - "eth_txen", - "eth_txd0", - "eth_txd1"; - function = "eth"; - drive-strength-microamp = <4000>; - bias-disable; - }; - }; - - eth_rgmii_pins: eth-rgmii { - mux { - groups = "eth_rxd2_rgmii", - "eth_rxd3_rgmii", - "eth_rgmii_tx_clk", - "eth_txd2_rgmii", - "eth_txd3_rgmii"; - function = "eth"; - drive-strength-microamp = <4000>; - bias-disable; - }; - }; - - tdm_c_din2_z_pins: tdm-c-din2-z { - mux { - groups = "tdm_c_din2_z"; - function = "tdm_c"; - bias-disable; - }; - }; - - tdm_c_din3_a_pins: tdm-c-din3-a { - mux { - groups = "tdm_c_din3_a"; - function = "tdm_c"; - bias-disable; - }; - }; - - tdm_c_din3_z_pins: tdm-c-din3-z { - mux { - groups = "tdm_c_din3_z"; - function = "tdm_c"; - bias-disable; - }; - }; - - tdm_c_dout0_a_pins: tdm-c-dout0-a { - mux { - groups = "tdm_c_dout0_a"; - function = "tdm_c"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_c_dout0_z_pins: tdm-c-dout0-z { - mux { - groups = "tdm_c_dout0_z"; - function = "tdm_c"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_c_dout1_a_pins: tdm-c-dout1-a { - mux { - groups = "tdm_c_dout1_a"; - function = "tdm_c"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_c_dout1_z_pins: tdm-c-dout1-z { - mux { - groups = "tdm_c_dout1_z"; - function = "tdm_c"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_c_dout2_a_pins: tdm-c-dout2-a { - mux { - groups = "tdm_c_dout2_a"; - function = "tdm_c"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_c_dout2_z_pins: tdm-c-dout2-z { - mux { - groups = "tdm_c_dout2_z"; - function = "tdm_c"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_c_dout3_a_pins: tdm-c-dout3-a { - mux { - groups = "tdm_c_dout3_a"; - function = "tdm_c"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_c_dout3_z_pins: tdm-c-dout3-z { - mux { - groups = "tdm_c_dout3_z"; - function = "tdm_c"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_c_fs_a_pins: tdm-c-fs-a { - mux { - groups = "tdm_c_fs_a"; - function = "tdm_c"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_c_fs_z_pins: tdm-c-fs-z { - mux { - groups = "tdm_c_fs_z"; - function = "tdm_c"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_c_sclk_a_pins: tdm-c-sclk-a { - mux { - groups = "tdm_c_sclk_a"; - function = "tdm_c"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_c_sclk_z_pins: tdm-c-sclk-z { - mux { - groups = "tdm_c_sclk_z"; - function = "tdm_c"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_c_slv_fs_a_pins: tdm-c-slv-fs-a { - mux { - groups = "tdm_c_slv_fs_a"; - function = "tdm_c"; - bias-disable; - }; - }; - - tdm_c_slv_fs_z_pins: tdm-c-slv-fs-z { - mux { - groups = "tdm_c_slv_fs_z"; - function = "tdm_c"; - bias-disable; - }; - }; - - tdm_c_slv_sclk_a_pins: tdm-c-slv-sclk-a { - mux { - groups = "tdm_c_slv_sclk_a"; - function = "tdm_c"; - bias-disable; - }; - }; - - tdm_c_slv_sclk_z_pins: tdm-c-slv-sclk-z { - mux { - groups = "tdm_c_slv_sclk_z"; - function = "tdm_c"; - bias-disable; - }; - }; - - uart_a_pins: uart-a { - mux { - groups = "uart_a_tx", - "uart_a_rx"; - function = "uart_a"; - bias-disable; - }; - }; - - uart_a_cts_rts_pins: uart-a-cts-rts { - mux { - groups = "uart_a_cts", - "uart_a_rts"; - function = "uart_a"; - bias-disable; - }; - }; - - uart_b_pins: uart-b { - mux { - groups = "uart_b_tx", - "uart_b_rx"; - function = "uart_b"; - bias-disable; - }; - }; - - uart_c_pins: uart-c { - mux { - groups = "uart_c_tx", - "uart_c_rx"; - function = "uart_c"; - bias-disable; - }; - }; - - uart_c_cts_rts_pins: uart-c-cts-rts { - mux { - groups = "uart_c_cts", - "uart_c_rts"; - function = "uart_c"; - bias-disable; - }; - }; - }; - }; - - cpu_temp: temperature-sensor@34800 { - compatible = "amlogic,g12a-cpu-thermal", - "amlogic,g12a-thermal"; - reg = <0x0 0x34800 0x0 0x50>; - interrupts = ; - clocks = <&clkc CLKID_TS>; - #thermal-sensor-cells = <0>; - amlogic,ao-secure = <&sec_AO>; - }; - - ddr_temp: temperature-sensor@34c00 { - compatible = "amlogic,g12a-ddr-thermal", - "amlogic,g12a-thermal"; - reg = <0x0 0x34c00 0x0 0x50>; - interrupts = ; - clocks = <&clkc CLKID_TS>; - #thermal-sensor-cells = <0>; - amlogic,ao-secure = <&sec_AO>; - }; - - usb2_phy0: phy@36000 { - compatible = "amlogic,g12a-usb2-phy"; - reg = <0x0 0x36000 0x0 0x2000>; - clocks = <&xtal>; - clock-names = "xtal"; - resets = <&reset RESET_USB_PHY20>; - reset-names = "phy"; - #phy-cells = <0>; - }; - - dmc: bus@38000 { - compatible = "simple-bus"; - reg = <0x0 0x38000 0x0 0x400>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0x38000 0x0 0x400>; - - canvas: video-lut@48 { - compatible = "amlogic,canvas"; - reg = <0x0 0x48 0x0 0x14>; - }; - }; - - usb2_phy1: phy@3a000 { - compatible = "amlogic,g12a-usb2-phy"; - reg = <0x0 0x3a000 0x0 0x2000>; - clocks = <&xtal>; - clock-names = "xtal"; - resets = <&reset RESET_USB_PHY21>; - reset-names = "phy"; - #phy-cells = <0>; - }; - - hiu: bus@3c000 { - compatible = "simple-bus"; - reg = <0x0 0x3c000 0x0 0x1400>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0x3c000 0x0 0x1400>; - - hhi: system-controller@0 { - compatible = "amlogic,meson-gx-hhi-sysctrl", - "simple-mfd", "syscon"; - reg = <0 0 0 0x400>; - - clkc: clock-controller { - compatible = "amlogic,g12a-clkc"; - #clock-cells = <1>; - clocks = <&xtal>; - clock-names = "xtal"; - }; - - pwrc: power-controller { - compatible = "amlogic,meson-g12a-pwrc"; - #power-domain-cells = <1>; - amlogic,ao-sysctrl = <&rti>; - resets = <&reset RESET_VIU>, - <&reset RESET_VENC>, - <&reset RESET_VCBUS>, - <&reset RESET_BT656>, - <&reset RESET_RDMA>, - <&reset RESET_VENCI>, - <&reset RESET_VENCP>, - <&reset RESET_VDAC>, - <&reset RESET_VDI6>, - <&reset RESET_VENCL>, - <&reset RESET_VID_LOCK>; - reset-names = "viu", "venc", "vcbus", "bt656", - "rdma", "venci", "vencp", "vdac", - "vdi6", "vencl", "vid_lock"; - clocks = <&clkc CLKID_VPU>, - <&clkc CLKID_VAPB>; - clock-names = "vpu", "vapb"; - /* - * VPU clocking is provided by two identical clock paths - * VPU_0 and VPU_1 muxed to a single clock by a glitch - * free mux to safely change frequency while running. - * Same for VAPB but with a final gate after the glitch free mux. - */ - assigned-clocks = <&clkc CLKID_VPU_0_SEL>, - <&clkc CLKID_VPU_0>, - <&clkc CLKID_VPU>, /* Glitch free mux */ - <&clkc CLKID_VAPB_0_SEL>, - <&clkc CLKID_VAPB_0>, - <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */ - assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>, - <0>, /* Do Nothing */ - <&clkc CLKID_VPU_0>, - <&clkc CLKID_FCLK_DIV4>, - <0>, /* Do Nothing */ - <&clkc CLKID_VAPB_0>; - assigned-clock-rates = <0>, /* Do Nothing */ - <666666666>, - <0>, /* Do Nothing */ - <0>, /* Do Nothing */ - <250000000>, - <0>; /* Do Nothing */ - }; - }; - }; - - usb3_pcie_phy: phy@46000 { - compatible = "amlogic,g12a-usb3-pcie-phy"; - reg = <0x0 0x46000 0x0 0x2000>; - clocks = <&clkc CLKID_PCIE_PLL>; - clock-names = "ref_clk"; - resets = <&reset RESET_PCIE_PHY>; - reset-names = "phy"; - assigned-clocks = <&clkc CLKID_PCIE_PLL>; - assigned-clock-rates = <100000000>; - #phy-cells = <1>; - }; - - eth_phy: mdio-multiplexer@4c000 { - compatible = "amlogic,g12a-mdio-mux"; - reg = <0x0 0x4c000 0x0 0xa4>; - clocks = <&clkc CLKID_ETH_PHY>, - <&xtal>, - <&clkc CLKID_MPLL_50M>; - clock-names = "pclk", "clkin0", "clkin1"; - mdio-parent-bus = <&mdio0>; - #address-cells = <1>; - #size-cells = <0>; - - ext_mdio: mdio@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - }; - - int_mdio: mdio@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - internal_ephy: ethernet_phy@8 { - compatible = "ethernet-phy-id0180.3301", - "ethernet-phy-ieee802.3-c22"; - interrupts = ; - reg = <8>; - max-speed = <100>; - }; - }; - }; - }; - - aobus: bus@ff800000 { - compatible = "simple-bus"; - reg = <0x0 0xff800000 0x0 0x100000>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>; - - rti: sys-ctrl@0 { - compatible = "amlogic,meson-gx-ao-sysctrl", - "simple-mfd", "syscon"; - reg = <0x0 0x0 0x0 0x100>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0x0 0x0 0x100>; - - clkc_AO: clock-controller { - compatible = "amlogic,meson-g12a-aoclkc"; - #clock-cells = <1>; - #reset-cells = <1>; - clocks = <&xtal>, <&clkc CLKID_CLK81>; - clock-names = "xtal", "mpeg-clk"; - }; - - ao_pinctrl: pinctrl@14 { - compatible = "amlogic,meson-g12a-aobus-pinctrl"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - gpio_ao: bank@14 { - reg = <0x0 0x14 0x0 0x8>, - <0x0 0x1c 0x0 0x8>, - <0x0 0x24 0x0 0x14>; - reg-names = "mux", - "ds", - "gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&ao_pinctrl 0 0 15>; - }; - - i2c_ao_sck_pins: i2c_ao_sck_pins { - mux { - groups = "i2c_ao_sck"; - function = "i2c_ao"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c_ao_sda_pins: i2c_ao_sda { - mux { - groups = "i2c_ao_sda"; - function = "i2c_ao"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c_ao_sck_e_pins: i2c_ao_sck_e { - mux { - groups = "i2c_ao_sck_e"; - function = "i2c_ao"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c_ao_sda_e_pins: i2c_ao_sda_e { - mux { - groups = "i2c_ao_sda_e"; - function = "i2c_ao"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - mclk0_ao_pins: mclk0-ao { - mux { - groups = "mclk0_ao"; - function = "mclk0_ao"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_ao_b_din0_pins: tdm-ao-b-din0 { - mux { - groups = "tdm_ao_b_din0"; - function = "tdm_ao_b"; - bias-disable; - }; - }; - - spdif_ao_out_pins: spdif-ao-out { - mux { - groups = "spdif_ao_out"; - function = "spdif_ao_out"; - drive-strength-microamp = <500>; - bias-disable; - }; - }; - - tdm_ao_b_din1_pins: tdm-ao-b-din1 { - mux { - groups = "tdm_ao_b_din1"; - function = "tdm_ao_b"; - bias-disable; - }; - }; - - tdm_ao_b_din2_pins: tdm-ao-b-din2 { - mux { - groups = "tdm_ao_b_din2"; - function = "tdm_ao_b"; - bias-disable; - }; - }; - - tdm_ao_b_dout0_pins: tdm-ao-b-dout0 { - mux { - groups = "tdm_ao_b_dout0"; - function = "tdm_ao_b"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_ao_b_dout1_pins: tdm-ao-b-dout1 { - mux { - groups = "tdm_ao_b_dout1"; - function = "tdm_ao_b"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_ao_b_dout2_pins: tdm-ao-b-dout2 { - mux { - groups = "tdm_ao_b_dout2"; - function = "tdm_ao_b"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_ao_b_fs_pins: tdm-ao-b-fs { - mux { - groups = "tdm_ao_b_fs"; - function = "tdm_ao_b"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_ao_b_sclk_pins: tdm-ao-b-sclk { - mux { - groups = "tdm_ao_b_sclk"; - function = "tdm_ao_b"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_ao_b_slv_fs_pins: tdm-ao-b-slv-fs { - mux { - groups = "tdm_ao_b_slv_fs"; - function = "tdm_ao_b"; - bias-disable; - }; - }; - - tdm_ao_b_slv_sclk_pins: tdm-ao-b-slv-sclk { - mux { - groups = "tdm_ao_b_slv_sclk"; - function = "tdm_ao_b"; - bias-disable; - }; - }; - - uart_ao_a_pins: uart-a-ao { - mux { - groups = "uart_ao_a_tx", - "uart_ao_a_rx"; - function = "uart_ao_a"; - bias-disable; - }; - }; - - uart_ao_a_cts_rts_pins: uart-ao-a-cts-rts { - mux { - groups = "uart_ao_a_cts", - "uart_ao_a_rts"; - function = "uart_ao_a"; - bias-disable; - }; - }; - - pwm_a_e_pins: pwm-a-e { - mux { - groups = "pwm_a_e"; - function = "pwm_a_e"; - bias-disable; - }; - }; - - pwm_ao_a_pins: pwm-ao-a { - mux { - groups = "pwm_ao_a"; - function = "pwm_ao_a"; - bias-disable; - }; - }; - - pwm_ao_b_pins: pwm-ao-b { - mux { - groups = "pwm_ao_b"; - function = "pwm_ao_b"; - bias-disable; - }; - }; - - pwm_ao_c_4_pins: pwm-ao-c-4 { - mux { - groups = "pwm_ao_c_4"; - function = "pwm_ao_c"; - bias-disable; - }; - }; - - pwm_ao_c_6_pins: pwm-ao-c-6 { - mux { - groups = "pwm_ao_c_6"; - function = "pwm_ao_c"; - bias-disable; - }; - }; - - pwm_ao_d_5_pins: pwm-ao-d-5 { - mux { - groups = "pwm_ao_d_5"; - function = "pwm_ao_d"; - bias-disable; - }; - }; - - pwm_ao_d_10_pins: pwm-ao-d-10 { - mux { - groups = "pwm_ao_d_10"; - function = "pwm_ao_d"; - bias-disable; - }; - }; - - pwm_ao_d_e_pins: pwm-ao-d-e { - mux { - groups = "pwm_ao_d_e"; - function = "pwm_ao_d"; - }; - }; - - remote_input_ao_pins: remote-input-ao { - mux { - groups = "remote_ao_input"; - function = "remote_ao_input"; - bias-disable; - }; - }; - }; - }; - - vrtc: rtc@0a8 { - compatible = "amlogic,meson-vrtc"; - reg = <0x0 0x000a8 0x0 0x4>; - }; - - cec_AO: cec@100 { - compatible = "amlogic,meson-gx-ao-cec"; - reg = <0x0 0x00100 0x0 0x14>; - interrupts = ; - clocks = <&clkc_AO CLKID_AO_CEC>; - clock-names = "core"; - status = "disabled"; - }; - - sec_AO: ao-secure@140 { - compatible = "amlogic,meson-gx-ao-secure", "syscon"; - reg = <0x0 0x140 0x0 0x140>; - amlogic,has-chip-id; - }; - - cecb_AO: cec@280 { - compatible = "amlogic,meson-g12a-ao-cec"; - reg = <0x0 0x00280 0x0 0x1c>; - interrupts = ; - clocks = <&clkc_AO CLKID_AO_CTS_OSCIN>; - clock-names = "oscin"; - status = "disabled"; - }; - - pwm_AO_cd: pwm@2000 { - compatible = "amlogic,meson-g12a-ao-pwm-cd"; - reg = <0x0 0x2000 0x0 0x20>; - #pwm-cells = <3>; - status = "disabled"; - }; - - uart_AO: serial@3000 { - compatible = "amlogic,meson-gx-uart", - "amlogic,meson-ao-uart"; - reg = <0x0 0x3000 0x0 0x18>; - interrupts = ; - clocks = <&xtal>, <&clkc_AO CLKID_AO_UART>, <&xtal>; - clock-names = "xtal", "pclk", "baud"; - status = "disabled"; - }; - - uart_AO_B: serial@4000 { - compatible = "amlogic,meson-gx-uart", - "amlogic,meson-ao-uart"; - reg = <0x0 0x4000 0x0 0x18>; - interrupts = ; - clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>; - clock-names = "xtal", "pclk", "baud"; - status = "disabled"; - }; - - i2c_AO: i2c@5000 { - compatible = "amlogic,meson-axg-i2c"; - status = "disabled"; - reg = <0x0 0x05000 0x0 0x20>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clkc CLKID_I2C>; - }; - - pwm_AO_ab: pwm@7000 { - compatible = "amlogic,meson-g12a-ao-pwm-ab"; - reg = <0x0 0x7000 0x0 0x20>; - #pwm-cells = <3>; - status = "disabled"; - }; - - ir: ir@8000 { - compatible = "amlogic,meson-gxbb-ir"; - reg = <0x0 0x8000 0x0 0x20>; - interrupts = ; - status = "disabled"; - }; - - saradc: adc@9000 { - compatible = "amlogic,meson-g12a-saradc", - "amlogic,meson-saradc"; - reg = <0x0 0x9000 0x0 0x48>; - #io-channel-cells = <1>; - interrupts = ; - clocks = <&xtal>, - <&clkc_AO CLKID_AO_SAR_ADC>, - <&clkc_AO CLKID_AO_SAR_ADC_CLK>, - <&clkc_AO CLKID_AO_SAR_ADC_SEL>; - clock-names = "clkin", "core", "adc_clk", "adc_sel"; - status = "disabled"; - }; - }; - - vdec: video-decoder@ff620000 { - compatible = "amlogic,g12a-vdec"; - reg = <0x0 0xff620000 0x0 0x10000>, - <0x0 0xffd0e180 0x0 0xe4>; - reg-names = "dos", "esparser"; - interrupts = , - ; - interrupt-names = "vdec", "esparser"; - - amlogic,ao-sysctrl = <&rti>; - amlogic,canvas = <&canvas>; - - clocks = <&clkc CLKID_PARSER>, - <&clkc CLKID_DOS>, - <&clkc CLKID_VDEC_1>, - <&clkc CLKID_VDEC_HEVC>, - <&clkc CLKID_VDEC_HEVCF>; - clock-names = "dos_parser", "dos", "vdec_1", - "vdec_hevc", "vdec_hevcf"; - resets = <&reset RESET_PARSER>; - reset-names = "esparser"; - }; - - vpu: vpu@ff900000 { - compatible = "amlogic,meson-g12a-vpu"; - reg = <0x0 0xff900000 0x0 0x100000>, - <0x0 0xff63c000 0x0 0x1000>; - reg-names = "vpu", "hhi"; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - amlogic,canvas = <&canvas>; - - /* CVBS VDAC output port */ - cvbs_vdac_port: port@0 { - reg = <0>; - }; - - /* HDMI-TX output port */ - hdmi_tx_port: port@1 { - reg = <1>; - - hdmi_tx_out: endpoint { - remote-endpoint = <&hdmi_tx_in>; - }; - }; - }; - - gic: interrupt-controller@ffc01000 { - compatible = "arm,gic-400"; - reg = <0x0 0xffc01000 0 0x1000>, - <0x0 0xffc02000 0 0x2000>, - <0x0 0xffc04000 0 0x2000>, - <0x0 0xffc06000 0 0x2000>; - interrupt-controller; - interrupts = ; - #interrupt-cells = <3>; - #address-cells = <0>; - }; - - cbus: bus@ffd00000 { - compatible = "simple-bus"; - reg = <0x0 0xffd00000 0x0 0x100000>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x100000>; - - reset: reset-controller@1004 { - compatible = "amlogic,meson-axg-reset"; - reg = <0x0 0x1004 0x0 0x9c>; - #reset-cells = <1>; - }; - - gpio_intc: interrupt-controller@f080 { - compatible = "amlogic,meson-g12a-gpio-intc", - "amlogic,meson-gpio-intc"; - reg = <0x0 0xf080 0x0 0x10>; - interrupt-controller; - #interrupt-cells = <2>; - amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>; - }; - - pwm_ef: pwm@19000 { - compatible = "amlogic,meson-g12a-ee-pwm"; - reg = <0x0 0x19000 0x0 0x20>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm_cd: pwm@1a000 { - compatible = "amlogic,meson-g12a-ee-pwm"; - reg = <0x0 0x1a000 0x0 0x20>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm_ab: pwm@1b000 { - compatible = "amlogic,meson-g12a-ee-pwm"; - reg = <0x0 0x1b000 0x0 0x20>; - #pwm-cells = <3>; - status = "disabled"; - }; - - i2c3: i2c@1c000 { - compatible = "amlogic,meson-axg-i2c"; - status = "disabled"; - reg = <0x0 0x1c000 0x0 0x20>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clkc CLKID_I2C>; - }; - - i2c2: i2c@1d000 { - compatible = "amlogic,meson-axg-i2c"; - status = "disabled"; - reg = <0x0 0x1d000 0x0 0x20>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clkc CLKID_I2C>; - }; - - i2c1: i2c@1e000 { - compatible = "amlogic,meson-axg-i2c"; - status = "disabled"; - reg = <0x0 0x1e000 0x0 0x20>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clkc CLKID_I2C>; - }; - - i2c0: i2c@1f000 { - compatible = "amlogic,meson-axg-i2c"; - status = "disabled"; - reg = <0x0 0x1f000 0x0 0x20>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clkc CLKID_I2C>; - }; - - clk_msr: clock-measure@18000 { - compatible = "amlogic,meson-g12a-clk-measure"; - reg = <0x0 0x18000 0x0 0x10>; - }; - - uart_C: serial@22000 { - compatible = "amlogic,meson-gx-uart"; - reg = <0x0 0x22000 0x0 0x18>; - interrupts = ; - clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>; - clock-names = "xtal", "pclk", "baud"; - status = "disabled"; - }; - - uart_B: serial@23000 { - compatible = "amlogic,meson-gx-uart"; - reg = <0x0 0x23000 0x0 0x18>; - interrupts = ; - clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; - clock-names = "xtal", "pclk", "baud"; - status = "disabled"; - }; - - uart_A: serial@24000 { - compatible = "amlogic,meson-gx-uart"; - reg = <0x0 0x24000 0x0 0x18>; - interrupts = ; - clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; - clock-names = "xtal", "pclk", "baud"; - status = "disabled"; - }; - }; - - sd_emmc_a: sd@ffe03000 { - compatible = "amlogic,meson-axg-mmc"; - reg = <0x0 0xffe03000 0x0 0x800>; - interrupts = ; - status = "disabled"; - clocks = <&clkc CLKID_SD_EMMC_A>, - <&clkc CLKID_SD_EMMC_A_CLK0>, - <&clkc CLKID_FCLK_DIV2>; - clock-names = "core", "clkin0", "clkin1"; - resets = <&reset RESET_SD_EMMC_A>; - }; - - sd_emmc_b: sd@ffe05000 { - compatible = "amlogic,meson-axg-mmc"; - reg = <0x0 0xffe05000 0x0 0x800>; - interrupts = ; - status = "disabled"; - clocks = <&clkc CLKID_SD_EMMC_B>, - <&clkc CLKID_SD_EMMC_B_CLK0>, - <&clkc CLKID_FCLK_DIV2>; - clock-names = "core", "clkin0", "clkin1"; - resets = <&reset RESET_SD_EMMC_B>; - }; - - sd_emmc_c: mmc@ffe07000 { - compatible = "amlogic,meson-axg-mmc"; - reg = <0x0 0xffe07000 0x0 0x800>; - interrupts = ; - status = "disabled"; - clocks = <&clkc CLKID_SD_EMMC_C>, - <&clkc CLKID_SD_EMMC_C_CLK0>, - <&clkc CLKID_FCLK_DIV2>; - clock-names = "core", "clkin0", "clkin1"; - resets = <&reset RESET_SD_EMMC_C>; - }; - - usb: usb@ffe09000 { - status = "disabled"; - compatible = "amlogic,meson-g12a-usb-ctrl"; - reg = <0x0 0xffe09000 0x0 0xa0>; - interrupts = ; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - clocks = <&clkc CLKID_USB>; - resets = <&reset RESET_USB>; - - dr_mode = "otg"; - - phys = <&usb2_phy0>, <&usb2_phy1>, - <&usb3_pcie_phy PHY_TYPE_USB3>; - phy-names = "usb2-phy0", "usb2-phy1", "usb3-phy0"; - - dwc2: usb@ff400000 { - compatible = "amlogic,meson-g12a-usb", "snps,dwc2"; - reg = <0x0 0xff400000 0x0 0x40000>; - interrupts = ; - clocks = <&clkc CLKID_USB1_DDR_BRIDGE>; - clock-names = "ddr"; - phys = <&usb2_phy1>; - phy-names = "usb2-phy"; - dr_mode = "peripheral"; - g-rx-fifo-size = <192>; - g-np-tx-fifo-size = <128>; - g-tx-fifo-size = <128 128 16 16 16>; - }; - - dwc3: usb@ff500000 { - compatible = "snps,dwc3"; - reg = <0x0 0xff500000 0x0 0x100000>; - interrupts = ; - dr_mode = "host"; - snps,dis_u2_susphy_quirk; - snps,quirk-frame-length-adjustment; - }; - }; - - mali: gpu@ffe40000 { - compatible = "amlogic,meson-g12a-mali", "arm,mali-bifrost"; - reg = <0x0 0xffe40000 0x0 0x40000>; - interrupt-parent = <&gic>; - interrupts = , - , - ; - interrupt-names = "job", "mmu", "gpu"; - clocks = <&clkc CLKID_MALI>; - resets = <&reset RESET_DVALIN_CAPB3>, <&reset RESET_DVALIN>; - - /* - * Mali clocking is provided by two identical clock paths - * MALI_0 and MALI_1 muxed to a single clock by a glitch - * free mux to safely change frequency while running. - */ - assigned-clocks = <&clkc CLKID_MALI_0_SEL>, - <&clkc CLKID_MALI_0>, - <&clkc CLKID_MALI>; /* Glitch free mux */ - assigned-clock-parents = <&clkc CLKID_FCLK_DIV2P5>, - <0>, /* Do Nothing */ - <&clkc CLKID_MALI_0>; - assigned-clock-rates = <0>, /* Do Nothing */ - <800000000>, - <0>; /* Do Nothing */ - #cooling-cells = <2>; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - arm,no-tick-in-suspend; - }; - - xtal: xtal-clk { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "xtal"; - #clock-cells = <0>; - }; - -}; diff --git a/sys/gnu/dts/arm64/amlogic/meson-g12.dtsi b/sys/gnu/dts/arm64/amlogic/meson-g12.dtsi deleted file mode 100644 index 03054c47889..00000000000 --- a/sys/gnu/dts/arm64/amlogic/meson-g12.dtsi +++ /dev/null @@ -1,398 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 BayLibre, SAS - * Author: Jerome Brunet - */ - -#include "meson-g12-common.dtsi" -#include -#include -#include -#include - -/ { - tdmif_a: audio-controller-0 { - compatible = "amlogic,axg-tdm-iface"; - #sound-dai-cells = <0>; - sound-name-prefix = "TDM_A"; - clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>, - <&clkc_audio AUD_CLKID_MST_A_SCLK>, - <&clkc_audio AUD_CLKID_MST_A_LRCLK>; - clock-names = "mclk", "sclk", "lrclk"; - status = "disabled"; - }; - - tdmif_b: audio-controller-1 { - compatible = "amlogic,axg-tdm-iface"; - #sound-dai-cells = <0>; - sound-name-prefix = "TDM_B"; - clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>, - <&clkc_audio AUD_CLKID_MST_B_SCLK>, - <&clkc_audio AUD_CLKID_MST_B_LRCLK>; - clock-names = "mclk", "sclk", "lrclk"; - status = "disabled"; - }; - - tdmif_c: audio-controller-2 { - compatible = "amlogic,axg-tdm-iface"; - #sound-dai-cells = <0>; - sound-name-prefix = "TDM_C"; - clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>, - <&clkc_audio AUD_CLKID_MST_C_SCLK>, - <&clkc_audio AUD_CLKID_MST_C_LRCLK>; - clock-names = "mclk", "sclk", "lrclk"; - status = "disabled"; - }; -}; - -&apb { - pdm: audio-controller@40000 { - compatible = "amlogic,g12a-pdm", - "amlogic,axg-pdm"; - reg = <0x0 0x40000 0x0 0x34>; - #sound-dai-cells = <0>; - sound-name-prefix = "PDM"; - clocks = <&clkc_audio AUD_CLKID_PDM>, - <&clkc_audio AUD_CLKID_PDM_DCLK>, - <&clkc_audio AUD_CLKID_PDM_SYSCLK>; - clock-names = "pclk", "dclk", "sysclk"; - status = "disabled"; - }; - - audio: bus@42000 { - compatible = "simple-bus"; - reg = <0x0 0x42000 0x0 0x2000>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0x42000 0x0 0x2000>; - - clkc_audio: clock-controller@0 { - status = "disabled"; - compatible = "amlogic,g12a-audio-clkc"; - reg = <0x0 0x0 0x0 0xb4>; - #clock-cells = <1>; - #reset-cells = <1>; - - clocks = <&clkc CLKID_AUDIO>, - <&clkc CLKID_MPLL0>, - <&clkc CLKID_MPLL1>, - <&clkc CLKID_MPLL2>, - <&clkc CLKID_MPLL3>, - <&clkc CLKID_HIFI_PLL>, - <&clkc CLKID_FCLK_DIV3>, - <&clkc CLKID_FCLK_DIV4>, - <&clkc CLKID_GP0_PLL>; - clock-names = "pclk", - "mst_in0", - "mst_in1", - "mst_in2", - "mst_in3", - "mst_in4", - "mst_in5", - "mst_in6", - "mst_in7"; - - resets = <&reset RESET_AUDIO>; - }; - - toddr_a: audio-controller@100 { - compatible = "amlogic,g12a-toddr", - "amlogic,axg-toddr"; - reg = <0x0 0x100 0x0 0x2c>; - #sound-dai-cells = <0>; - sound-name-prefix = "TODDR_A"; - interrupts = ; - clocks = <&clkc_audio AUD_CLKID_TODDR_A>; - resets = <&arb AXG_ARB_TODDR_A>, - <&clkc_audio AUD_RESET_TODDR_A>; - reset-names = "arb", "rst"; - amlogic,fifo-depth = <512>; - status = "disabled"; - }; - - toddr_b: audio-controller@140 { - compatible = "amlogic,g12a-toddr", - "amlogic,axg-toddr"; - reg = <0x0 0x140 0x0 0x2c>; - #sound-dai-cells = <0>; - sound-name-prefix = "TODDR_B"; - interrupts = ; - clocks = <&clkc_audio AUD_CLKID_TODDR_B>; - resets = <&arb AXG_ARB_TODDR_B>, - <&clkc_audio AUD_RESET_TODDR_B>; - reset-names = "arb", "rst"; - amlogic,fifo-depth = <256>; - status = "disabled"; - }; - - toddr_c: audio-controller@180 { - compatible = "amlogic,g12a-toddr", - "amlogic,axg-toddr"; - reg = <0x0 0x180 0x0 0x2c>; - #sound-dai-cells = <0>; - sound-name-prefix = "TODDR_C"; - interrupts = ; - clocks = <&clkc_audio AUD_CLKID_TODDR_C>; - resets = <&arb AXG_ARB_TODDR_C>, - <&clkc_audio AUD_RESET_TODDR_C>; - reset-names = "arb", "rst"; - amlogic,fifo-depth = <256>; - status = "disabled"; - }; - - frddr_a: audio-controller@1c0 { - compatible = "amlogic,g12a-frddr", - "amlogic,axg-frddr"; - reg = <0x0 0x1c0 0x0 0x2c>; - #sound-dai-cells = <0>; - sound-name-prefix = "FRDDR_A"; - interrupts = ; - clocks = <&clkc_audio AUD_CLKID_FRDDR_A>; - resets = <&arb AXG_ARB_FRDDR_A>, - <&clkc_audio AUD_RESET_FRDDR_A>; - reset-names = "arb", "rst"; - amlogic,fifo-depth = <512>; - status = "disabled"; - }; - - frddr_b: audio-controller@200 { - compatible = "amlogic,g12a-frddr", - "amlogic,axg-frddr"; - reg = <0x0 0x200 0x0 0x2c>; - #sound-dai-cells = <0>; - sound-name-prefix = "FRDDR_B"; - interrupts = ; - clocks = <&clkc_audio AUD_CLKID_FRDDR_B>; - resets = <&arb AXG_ARB_FRDDR_B>, - <&clkc_audio AUD_RESET_FRDDR_B>; - reset-names = "arb", "rst"; - amlogic,fifo-depth = <256>; - status = "disabled"; - }; - - frddr_c: audio-controller@240 { - compatible = "amlogic,g12a-frddr", - "amlogic,axg-frddr"; - reg = <0x0 0x240 0x0 0x2c>; - #sound-dai-cells = <0>; - sound-name-prefix = "FRDDR_C"; - interrupts = ; - clocks = <&clkc_audio AUD_CLKID_FRDDR_C>; - resets = <&arb AXG_ARB_FRDDR_C>, - <&clkc_audio AUD_RESET_FRDDR_C>; - reset-names = "arb", "rst"; - amlogic,fifo-depth = <256>; - status = "disabled"; - }; - - arb: reset-controller@280 { - status = "disabled"; - compatible = "amlogic,meson-axg-audio-arb"; - reg = <0x0 0x280 0x0 0x4>; - #reset-cells = <1>; - clocks = <&clkc_audio AUD_CLKID_DDR_ARB>; - }; - - tdmin_a: audio-controller@300 { - compatible = "amlogic,g12a-tdmin", - "amlogic,axg-tdmin"; - reg = <0x0 0x300 0x0 0x40>; - sound-name-prefix = "TDMIN_A"; - resets = <&clkc_audio AUD_RESET_TDMIN_A>; - clocks = <&clkc_audio AUD_CLKID_TDMIN_A>, - <&clkc_audio AUD_CLKID_TDMIN_A_SCLK>, - <&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>, - <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>, - <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>; - clock-names = "pclk", "sclk", "sclk_sel", - "lrclk", "lrclk_sel"; - status = "disabled"; - }; - - tdmin_b: audio-controller@340 { - compatible = "amlogic,g12a-tdmin", - "amlogic,axg-tdmin"; - reg = <0x0 0x340 0x0 0x40>; - sound-name-prefix = "TDMIN_B"; - resets = <&clkc_audio AUD_RESET_TDMIN_B>; - clocks = <&clkc_audio AUD_CLKID_TDMIN_B>, - <&clkc_audio AUD_CLKID_TDMIN_B_SCLK>, - <&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>, - <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>, - <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>; - clock-names = "pclk", "sclk", "sclk_sel", - "lrclk", "lrclk_sel"; - status = "disabled"; - }; - - tdmin_c: audio-controller@380 { - compatible = "amlogic,g12a-tdmin", - "amlogic,axg-tdmin"; - reg = <0x0 0x380 0x0 0x40>; - sound-name-prefix = "TDMIN_C"; - resets = <&clkc_audio AUD_RESET_TDMIN_C>; - clocks = <&clkc_audio AUD_CLKID_TDMIN_C>, - <&clkc_audio AUD_CLKID_TDMIN_C_SCLK>, - <&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>, - <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>, - <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>; - clock-names = "pclk", "sclk", "sclk_sel", - "lrclk", "lrclk_sel"; - status = "disabled"; - }; - - tdmin_lb: audio-controller@3c0 { - compatible = "amlogic,g12a-tdmin", - "amlogic,axg-tdmin"; - reg = <0x0 0x3c0 0x0 0x40>; - sound-name-prefix = "TDMIN_LB"; - resets = <&clkc_audio AUD_RESET_TDMIN_LB>; - clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>, - <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>, - <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>, - <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>, - <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>; - clock-names = "pclk", "sclk", "sclk_sel", - "lrclk", "lrclk_sel"; - status = "disabled"; - }; - - spdifin: audio-controller@400 { - compatible = "amlogic,g12a-spdifin", - "amlogic,axg-spdifin"; - reg = <0x0 0x400 0x0 0x30>; - #sound-dai-cells = <0>; - sound-name-prefix = "SPDIFIN"; - interrupts = ; - clocks = <&clkc_audio AUD_CLKID_SPDIFIN>, - <&clkc_audio AUD_CLKID_SPDIFIN_CLK>; - clock-names = "pclk", "refclk"; - resets = <&clkc_audio AUD_RESET_SPDIFIN>; - status = "disabled"; - }; - - spdifout: audio-controller@480 { - compatible = "amlogic,g12a-spdifout", - "amlogic,axg-spdifout"; - reg = <0x0 0x480 0x0 0x50>; - #sound-dai-cells = <0>; - sound-name-prefix = "SPDIFOUT"; - clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>, - <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>; - clock-names = "pclk", "mclk"; - resets = <&clkc_audio AUD_RESET_SPDIFOUT>; - status = "disabled"; - }; - - tdmout_a: audio-controller@500 { - compatible = "amlogic,g12a-tdmout"; - reg = <0x0 0x500 0x0 0x40>; - sound-name-prefix = "TDMOUT_A"; - resets = <&clkc_audio AUD_RESET_TDMOUT_A>; - clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>, - <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>, - <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>, - <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>, - <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>; - clock-names = "pclk", "sclk", "sclk_sel", - "lrclk", "lrclk_sel"; - status = "disabled"; - }; - - tdmout_b: audio-controller@540 { - compatible = "amlogic,g12a-tdmout"; - reg = <0x0 0x540 0x0 0x40>; - sound-name-prefix = "TDMOUT_B"; - resets = <&clkc_audio AUD_RESET_TDMOUT_B>; - clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>, - <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>, - <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>, - <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>, - <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>; - clock-names = "pclk", "sclk", "sclk_sel", - "lrclk", "lrclk_sel"; - status = "disabled"; - }; - - tdmout_c: audio-controller@580 { - compatible = "amlogic,g12a-tdmout"; - reg = <0x0 0x580 0x0 0x40>; - sound-name-prefix = "TDMOUT_C"; - resets = <&clkc_audio AUD_RESET_TDMOUT_C>; - clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>, - <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>, - <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>, - <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>, - <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>; - clock-names = "pclk", "sclk", "sclk_sel", - "lrclk", "lrclk_sel"; - status = "disabled"; - }; - - spdifout_b: audio-controller@680 { - compatible = "amlogic,g12a-spdifout", - "amlogic,axg-spdifout"; - reg = <0x0 0x680 0x0 0x50>; - #sound-dai-cells = <0>; - sound-name-prefix = "SPDIFOUT_B"; - clocks = <&clkc_audio AUD_CLKID_SPDIFOUT_B>, - <&clkc_audio AUD_CLKID_SPDIFOUT_B_CLK>; - clock-names = "pclk", "mclk"; - resets = <&clkc_audio AUD_RESET_SPDIFOUT_B>; - status = "disabled"; - }; - - tohdmitx: audio-controller@744 { - compatible = "amlogic,g12a-tohdmitx"; - reg = <0x0 0x744 0x0 0x4>; - #sound-dai-cells = <1>; - sound-name-prefix = "TOHDMITX"; - resets = <&clkc_audio AUD_RESET_TOHDMITX>; - status = "disabled"; - }; - }; -}; - -&cpu_thermal { - cooling-maps { - map0 { - trip = <&cpu_passive>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu102 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu103 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu_hot>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu102 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu103 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; -}; - -ðmac { - power-domains = <&pwrc PWRC_G12A_ETH_ID>; -}; - -&vpu { - power-domains = <&pwrc PWRC_G12A_VPU_ID>; -}; - -&sd_emmc_a { - amlogic,dram-access-quirk; -}; - -&simplefb_cvbs { - power-domains = <&pwrc PWRC_G12A_VPU_ID>; -}; - -&simplefb_hdmi { - power-domains = <&pwrc PWRC_G12A_VPU_ID>; -}; - diff --git a/sys/gnu/dts/arm64/amlogic/meson-g12a-sei510.dts b/sys/gnu/dts/arm64/amlogic/meson-g12a-sei510.dts deleted file mode 100644 index 2ac9e3a43b9..00000000000 --- a/sys/gnu/dts/arm64/amlogic/meson-g12a-sei510.dts +++ /dev/null @@ -1,566 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 BayLibre SAS. All rights reserved. - */ - -/dts-v1/; - -#include "meson-g12a.dtsi" -#include -#include -#include -#include - -/ { - compatible = "seirobotics,sei510", "amlogic,g12a"; - model = "SEI Robotics SEI510"; - - adc_keys { - compatible = "adc-keys"; - io-channels = <&saradc 0>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1800000>; - - button-onoff { - label = "On/Off"; - linux,code = ; - press-threshold-microvolt = <1700000>; - }; - }; - - aliases { - serial0 = &uart_AO; - ethernet0 = ðmac; - }; - - mono_dac: audio-codec-0 { - compatible = "maxim,max98357a"; - #sound-dai-cells = <0>; - sound-name-prefix = "U16"; - sdmode-gpios = <&gpio GPIOX_8 GPIO_ACTIVE_HIGH>; - }; - - dmics: audio-codec-1 { - #sound-dai-cells = <0>; - compatible = "dmic-codec"; - num-channels = <2>; - wakeup-delay-ms = <50>; - status = "okay"; - sound-name-prefix = "MIC"; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - cvbs-connector { - compatible = "composite-video-connector"; - - port { - cvbs_connector_in: endpoint { - remote-endpoint = <&cvbs_vdac_out>; - }; - }; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x40000000>; - }; - - ao_5v: regulator-ao_5v { - compatible = "regulator-fixed"; - regulator-name = "AO_5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&dc_in>; - regulator-always-on; - }; - - dc_in: regulator-dc_in { - compatible = "regulator-fixed"; - regulator-name = "DC_IN"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - emmc_1v8: regulator-emmc_1v8 { - compatible = "regulator-fixed"; - regulator-name = "EMMC_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vddao_3v3>; - regulator-always-on; - }; - - vddao_3v3: regulator-vddao_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&dc_in>; - regulator-always-on; - }; - - vddao_3v3_t: regultor-vddao_3v3_t { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3_T"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vddao_3v3>; - gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>; - enable-active-high; - }; - - vddcpu: regulator-vddcpu { - /* - * SY8120B1ABC DC/DC Regulator. - */ - compatible = "pwm-regulator"; - - regulator-name = "VDDCPU"; - regulator-min-microvolt = <721000>; - regulator-max-microvolt = <1022000>; - - vin-supply = <&dc_in>; - - pwms = <&pwm_AO_cd 1 1250 0>; - pwm-dutycycle-range = <100 0>; - - regulator-boot-on; - regulator-always-on; - }; - - vddio_ao1v8: regulator-vddio_ao1v8 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vddao_3v3>; - regulator-always-on; - }; - - reserved-memory { - /* TEE Reserved Memory */ - bl32_reserved: bl32@5000000 { - reg = <0x0 0x05300000 0x0 0x2000000>; - no-map; - }; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; - clocks = <&wifi32k>; - clock-names = "ext_clock"; - }; - - wifi32k: wifi32k { - compatible = "pwm-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ - }; - - sound { - compatible = "amlogic,axg-sound-card"; - model = "G12A-SEI510"; - audio-aux-devs = <&tdmout_a>, <&tdmout_b>, - <&tdmin_a>, <&tdmin_b>; - audio-routing = "TDMOUT_A IN 0", "FRDDR_A OUT 0", - "TDMOUT_A IN 1", "FRDDR_B OUT 0", - "TDMOUT_A IN 2", "FRDDR_C OUT 0", - "TDM_A Playback", "TDMOUT_A OUT", - "TDMOUT_B IN 0", "FRDDR_A OUT 1", - "TDMOUT_B IN 1", "FRDDR_B OUT 1", - "TDMOUT_B IN 2", "FRDDR_C OUT 1", - "TDM_B Playback", "TDMOUT_B OUT", - "TODDR_A IN 4", "PDM Capture", - "TODDR_B IN 4", "PDM Capture", - "TODDR_C IN 4", "PDM Capture", - "TDMIN_A IN 0", "TDM_A Capture", - "TDMIN_A IN 3", "TDM_A Loopback", - "TDMIN_B IN 0", "TDM_A Capture", - "TDMIN_B IN 3", "TDM_A Loopback", - "TDMIN_A IN 1", "TDM_B Capture", - "TDMIN_A IN 4", "TDM_B Loopback", - "TDMIN_B IN 1", "TDM_B Capture", - "TDMIN_B IN 4", "TDM_B Loopback", - "TODDR_A IN 0", "TDMIN_A OUT", - "TODDR_B IN 0", "TDMIN_A OUT", - "TODDR_C IN 0", "TDMIN_A OUT", - "TODDR_A IN 1", "TDMIN_B OUT", - "TODDR_B IN 1", "TDMIN_B OUT", - "TODDR_C IN 1", "TDMIN_B OUT"; - - assigned-clocks = <&clkc CLKID_MPLL2>, - <&clkc CLKID_MPLL0>, - <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; - assigned-clock-rates = <294912000>, - <270950400>, - <393216000>; - status = "okay"; - - dai-link-0 { - sound-dai = <&frddr_a>; - }; - - dai-link-1 { - sound-dai = <&frddr_b>; - }; - - dai-link-2 { - sound-dai = <&frddr_c>; - }; - - dai-link-3 { - sound-dai = <&toddr_a>; - }; - - dai-link-4 { - sound-dai = <&toddr_b>; - }; - - dai-link-5 { - sound-dai = <&toddr_c>; - }; - - /* internal speaker interface */ - dai-link-6 { - sound-dai = <&tdmif_a>; - dai-format = "i2s"; - dai-tdm-slot-tx-mask-0 = <1 1>; - mclk-fs = <256>; - - codec-0 { - sound-dai = <&mono_dac>; - }; - - codec-1 { - sound-dai = <&tohdmitx TOHDMITX_I2S_IN_A>; - }; - }; - - /* 8ch hdmi interface */ - dai-link-7 { - sound-dai = <&tdmif_b>; - dai-format = "i2s"; - dai-tdm-slot-tx-mask-0 = <1 1>; - dai-tdm-slot-tx-mask-1 = <1 1>; - dai-tdm-slot-tx-mask-2 = <1 1>; - dai-tdm-slot-tx-mask-3 = <1 1>; - mclk-fs = <256>; - - codec@0 { - sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>; - }; - }; - - /* internal digital mics */ - dai-link-8 { - sound-dai = <&pdm>; - - codec { - sound-dai = <&dmics>; - }; - }; - - /* hdmi glue */ - dai-link-9 { - sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; - - codec { - sound-dai = <&hdmi_tx>; - }; - }; - }; -}; - -&arb { - status = "okay"; -}; - -&cec_AO { - pinctrl-0 = <&cec_ao_a_h_pins>; - pinctrl-names = "default"; - status = "disabled"; - hdmi-phandle = <&hdmi_tx>; -}; - -&cecb_AO { - pinctrl-0 = <&cec_ao_b_h_pins>; - pinctrl-names = "default"; - status = "okay"; - hdmi-phandle = <&hdmi_tx>; -}; - -&clkc_audio { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cpu1 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cpu2 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cpu3 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cvbs_vdac_port { - cvbs_vdac_out: endpoint { - remote-endpoint = <&cvbs_connector_in>; - }; -}; - -ðmac { - status = "okay"; - phy-handle = <&internal_ephy>; - phy-mode = "rmii"; -}; - -&frddr_a { - status = "okay"; -}; - -&frddr_b { - status = "okay"; -}; - -&frddr_c { - status = "okay"; -}; - -&hdmi_tx { - status = "okay"; - pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>; - pinctrl-names = "default"; -}; - -&hdmi_tx_tmds_port { - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; -}; - -&i2c3 { - status = "okay"; - pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>; - pinctrl-names = "default"; -}; - -&ir { - status = "okay"; - pinctrl-0 = <&remote_input_ao_pins>; - pinctrl-names = "default"; -}; - -&pwm_AO_cd { - pinctrl-0 = <&pwm_ao_d_e_pins>; - pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin1"; - status = "okay"; -}; - -&pwm_ef { - status = "okay"; - pinctrl-0 = <&pwm_e_pins>; - pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin0"; -}; - -&pdm { - pinctrl-0 = <&pdm_din0_z_pins>, <&pdm_din1_z_pins>, - <&pdm_din2_z_pins>, <&pdm_din3_z_pins>, - <&pdm_dclk_z_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&saradc { - status = "okay"; - vref-supply = <&vddio_ao1v8>; -}; - -/* SDIO */ -&sd_emmc_a { - status = "okay"; - pinctrl-0 = <&sdio_pins>; - pinctrl-1 = <&sdio_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - #address-cells = <1>; - #size-cells = <0>; - - bus-width = <4>; - cap-sd-highspeed; - sd-uhs-sdr50; - max-frequency = <100000000>; - - non-removable; - disable-wp; - - /* WiFi firmware requires power to be kept while in suspend */ - keep-power-in-suspend; - - mmc-pwrseq = <&sdio_pwrseq>; - - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddio_ao1v8>; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - }; -}; - -/* SD card */ -&sd_emmc_b { - status = "okay"; - pinctrl-0 = <&sdcard_c_pins>; - pinctrl-1 = <&sdcard_clk_gate_c_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <50000000>; - disable-wp; - - cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>; - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddao_3v3>; -}; - -/* eMMC */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - max-frequency = <200000000>; - non-removable; - disable-wp; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&emmc_1v8>; -}; - -&tdmif_a { - pinctrl-0 = <&tdm_a_dout0_pins>, <&tdm_a_fs_pins>, <&tdm_a_sclk_pins>; - pinctrl-names = "default"; - status = "okay"; - - assigned-clocks = <&clkc_audio AUD_CLKID_TDM_SCLK_PAD0>, - <&clkc_audio AUD_CLKID_TDM_LRCLK_PAD0>; - assigned-clock-parents = <&clkc_audio AUD_CLKID_MST_A_SCLK>, - <&clkc_audio AUD_CLKID_MST_A_LRCLK>; - assigned-clock-rates = <0>, <0>; -}; - -&tdmif_b { - status = "okay"; -}; - -&tdmin_a { - status = "okay"; -}; - -&tdmin_b { - status = "okay"; -}; - -&tdmout_a { - status = "okay"; -}; - -&tdmout_b { - status = "okay"; -}; - -&toddr_a { - status = "okay"; -}; - -&toddr_b { - status = "okay"; -}; - -&toddr_c { - status = "okay"; -}; - -&tohdmitx { - status = "okay"; -}; - -&uart_A { - status = "okay"; - pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; - pinctrl-names = "default"; - uart-has-rtscts; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; - max-speed = <2000000>; - clocks = <&wifi32k>; - clock-names = "lpo"; - vbat-supply = <&vddao_3v3>; - vddio-supply = <&vddio_ao1v8>; - }; -}; - -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -&usb { - status = "okay"; - dr_mode = "host"; -}; diff --git a/sys/gnu/dts/arm64/amlogic/meson-g12a-u200.dts b/sys/gnu/dts/arm64/amlogic/meson-g12a-u200.dts deleted file mode 100644 index 2a324f0136e..00000000000 --- a/sys/gnu/dts/arm64/amlogic/meson-g12a-u200.dts +++ /dev/null @@ -1,308 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2018 Amlogic, Inc. All rights reserved. - */ - -/dts-v1/; - -#include "meson-g12a.dtsi" -#include -#include - -/ { - compatible = "amlogic,u200", "amlogic,g12a"; - model = "Amlogic Meson G12A U200 Development Board"; - - aliases { - serial0 = &uart_AO; - ethernet0 = ðmac; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - cvbs-connector { - compatible = "composite-video-connector"; - - port { - cvbs_connector_in: endpoint { - remote-endpoint = <&cvbs_vdac_out>; - }; - }; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x40000000>; - }; - - flash_1v8: regulator-flash_1v8 { - compatible = "regulator-fixed"; - regulator-name = "FLASH_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_3v3>; - regulator-always-on; - }; - - main_12v: regulator-main_12v { - compatible = "regulator-fixed"; - regulator-name = "12V"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-always-on; - }; - - usb_pwr_en: regulator-usb_pwr_en { - compatible = "regulator-fixed"; - regulator-name = "USB_PWR_EN"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc_5v>; - - gpio = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vcc_1v8: regulator-vcc_1v8 { - compatible = "regulator-fixed"; - regulator-name = "VCC_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_3v3>; - regulator-always-on; - }; - - vcc_3v3: regulator-vcc_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vddao_3v3>; - regulator-always-on; - /* FIXME: actually controlled by VDDCPU_B_EN */ - }; - - vcc_5v: regulator-vcc_5v { - compatible = "regulator-fixed"; - regulator-name = "VCC_5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&main_12v>; - - gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>; - enable-active-high; - }; - - vddao_1v8: regulator-vddao_1v8 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vddao_3v3>; - regulator-always-on; - }; - - vddao_3v3: regulator-vddao_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&main_12v>; - regulator-always-on; - }; - - vddcpu: regulator-vddcpu { - /* - * MP8756GD Regulator. - */ - compatible = "pwm-regulator"; - - regulator-name = "VDDCPU"; - regulator-min-microvolt = <721000>; - regulator-max-microvolt = <1022000>; - - vin-supply = <&main_12v>; - - pwms = <&pwm_AO_cd 1 1250 0>; - pwm-dutycycle-range = <100 0>; - - regulator-boot-on; - regulator-always-on; - }; -}; - -&cec_AO { - pinctrl-0 = <&cec_ao_a_h_pins>; - pinctrl-names = "default"; - status = "disabled"; - hdmi-phandle = <&hdmi_tx>; -}; - -&cecb_AO { - pinctrl-0 = <&cec_ao_b_h_pins>; - pinctrl-names = "default"; - status = "okay"; - hdmi-phandle = <&hdmi_tx>; -}; - -&cpu0 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cpu1 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cpu2 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cpu3 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cvbs_vdac_port { - cvbs_vdac_out: endpoint { - remote-endpoint = <&cvbs_connector_in>; - }; -}; - -ðmac { - status = "okay"; - phy-handle = <&internal_ephy>; - phy-mode = "rmii"; -}; - -&hdmi_tx { - status = "okay"; - pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>; - pinctrl-names = "default"; - hdmi-supply = <&vcc_5v>; -}; - -&hdmi_tx_tmds_port { - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; -}; - -&ir { - status = "okay"; - pinctrl-0 = <&remote_input_ao_pins>; - pinctrl-names = "default"; -}; - -/* i2c Touch */ -&i2c0 { - status = "okay"; - pinctrl-0 = <&i2c0_sda_z0_pins>, <&i2c0_sck_z1_pins>; - pinctrl-names = "default"; -}; - -/* i2c CM */ -&i2c2 { - status = "okay"; - pinctrl-0 = <&i2c2_sda_z_pins>, <&i2c2_sck_z_pins>; - pinctrl-names = "default"; -}; - -/* i2c Audio */ -&i2c3 { - status = "okay"; - pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>; - pinctrl-names = "default"; -}; - -&pwm_AO_cd { - pinctrl-0 = <&pwm_ao_d_e_pins>; - pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin1"; - status = "okay"; -}; - -/* SD card */ -&sd_emmc_b { - status = "okay"; - pinctrl-0 = <&sdcard_c_pins>; - pinctrl-1 = <&sdcard_clk_gate_c_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <50000000>; - disable-wp; - - cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>; - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddao_3v3>; -}; - -/* eMMC */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - max-frequency = <200000000>; - non-removable; - disable-wp; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&flash_1v8>; -}; - -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -&usb { - status = "okay"; - vbus-supply = <&usb_pwr_en>; -}; - -&usb2_phy0 { - phy-supply = <&vcc_5v>; -}; - -&usb2_phy1 { - phy-supply = <&vcc_5v>; -}; diff --git a/sys/gnu/dts/arm64/amlogic/meson-g12a-x96-max.dts b/sys/gnu/dts/arm64/amlogic/meson-g12a-x96-max.dts deleted file mode 100644 index 4f2596d8298..00000000000 --- a/sys/gnu/dts/arm64/amlogic/meson-g12a-x96-max.dts +++ /dev/null @@ -1,481 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2018 BayLibre SAS. All rights reserved. - */ - -/dts-v1/; - -#include "meson-g12a.dtsi" -#include -#include -#include - -/ { - compatible = "amediatech,x96-max", "amlogic,g12a"; - model = "Shenzhen Amediatech Technology Co., Ltd X96 Max"; - - aliases { - serial0 = &uart_AO; - ethernet0 = ðmac; - }; - - spdif_dit: audio-codec-1 { - #sound-dai-cells = <0>; - compatible = "linux,spdif-dit"; - status = "okay"; - sound-name-prefix = "DIT"; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x40000000>; - }; - - cvbs-connector { - compatible = "composite-video-connector"; - - port { - cvbs_connector_in: endpoint { - remote-endpoint = <&cvbs_vdac_out>; - }; - }; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; - clocks = <&wifi32k>; - clock-names = "ext_clock"; - }; - - flash_1v8: regulator-flash_1v8 { - compatible = "regulator-fixed"; - regulator-name = "FLASH_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_3v3>; - regulator-always-on; - }; - - dc_in: regulator-dc_in { - compatible = "regulator-fixed"; - regulator-name = "DC_IN"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - vcc_1v8: regulator-vcc_1v8 { - compatible = "regulator-fixed"; - regulator-name = "VCC_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_3v3>; - regulator-always-on; - }; - - vcc_3v3: regulator-vcc_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vddao_3v3>; - regulator-always-on; - /* FIXME: actually controlled by VDDCPU_B_EN */ - }; - - vcc_5v: regulator-vcc_5v { - compatible = "regulator-fixed"; - regulator-name = "VCC_5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&dc_in>; - - gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>; - enable-active-low; - }; - - vddao_1v8: regulator-vddao_1v8 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vddao_3v3>; - regulator-always-on; - }; - - vddao_3v3: regulator-vddao_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&dc_in>; - regulator-always-on; - }; - - vddcpu: regulator-vddcpu { - compatible = "pwm-regulator"; - - regulator-name = "VDDCPU"; - regulator-min-microvolt = <721000>; - regulator-max-microvolt = <1022000>; - - vin-supply = <&dc_in>; - - pwms = <&pwm_AO_cd 1 1250 0>; - pwm-dutycycle-range = <100 0>; - - regulator-boot-on; - regulator-always-on; - }; - - sound { - compatible = "amlogic,axg-sound-card"; - model = "G12A-X96-MAX"; - audio-aux-devs = <&tdmout_b>; - audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1", - "TDMOUT_B IN 1", "FRDDR_B OUT 1", - "TDMOUT_B IN 2", "FRDDR_C OUT 1", - "TDM_B Playback", "TDMOUT_B OUT", - "SPDIFOUT IN 0", "FRDDR_A OUT 3", - "SPDIFOUT IN 1", "FRDDR_B OUT 3", - "SPDIFOUT IN 2", "FRDDR_C OUT 3"; - - assigned-clocks = <&clkc CLKID_MPLL2>, - <&clkc CLKID_MPLL0>, - <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; - assigned-clock-rates = <294912000>, - <270950400>, - <393216000>; - status = "okay"; - - dai-link-0 { - sound-dai = <&frddr_a>; - }; - - dai-link-1 { - sound-dai = <&frddr_b>; - }; - - dai-link-2 { - sound-dai = <&frddr_c>; - }; - - /* 8ch hdmi interface */ - dai-link-3 { - sound-dai = <&tdmif_b>; - dai-format = "i2s"; - dai-tdm-slot-tx-mask-0 = <1 1>; - dai-tdm-slot-tx-mask-1 = <1 1>; - dai-tdm-slot-tx-mask-2 = <1 1>; - dai-tdm-slot-tx-mask-3 = <1 1>; - mclk-fs = <256>; - - codec { - sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>; - }; - }; - - /* spdif hdmi or toslink interface */ - dai-link-4 { - sound-dai = <&spdifout>; - - codec-0 { - sound-dai = <&spdif_dit>; - }; - - codec-1 { - sound-dai = <&tohdmitx TOHDMITX_SPDIF_IN_A>; - }; - }; - - /* spdif hdmi interface */ - dai-link-5 { - sound-dai = <&spdifout_b>; - - codec { - sound-dai = <&tohdmitx TOHDMITX_SPDIF_IN_B>; - }; - }; - - /* hdmi glue */ - dai-link-6 { - sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; - - codec { - sound-dai = <&hdmi_tx>; - }; - }; - }; - - wifi32k: wifi32k { - compatible = "pwm-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ - }; -}; - -&arb { - status = "okay"; -}; - -&cec_AO { - pinctrl-0 = <&cec_ao_a_h_pins>; - pinctrl-names = "default"; - status = "disabled"; - hdmi-phandle = <&hdmi_tx>; -}; - -&cecb_AO { - pinctrl-0 = <&cec_ao_b_h_pins>; - pinctrl-names = "default"; - status = "okay"; - hdmi-phandle = <&hdmi_tx>; -}; - -&clkc_audio { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cpu1 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cpu2 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cpu3 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cvbs_vdac_port { - cvbs_vdac_out: endpoint { - remote-endpoint = <&cvbs_connector_in>; - }; -}; - -&frddr_a { - status = "okay"; -}; - -&frddr_b { - status = "okay"; -}; - -&frddr_c { - status = "okay"; -}; - -&hdmi_tx { - status = "okay"; - pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>; - pinctrl-names = "default"; - hdmi-supply = <&vcc_5v>; -}; - -&hdmi_tx_tmds_port { - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; -}; - -&ir { - status = "okay"; - pinctrl-0 = <&remote_input_ao_pins>; - pinctrl-names = "default"; - linux,rc-map-name = "rc-x96max"; -}; - -&pwm_AO_cd { - pinctrl-0 = <&pwm_ao_d_e_pins>; - pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin1"; - status = "okay"; -}; - -&ext_mdio { - external_phy: ethernet-phy@0 { - /* Realtek RTL8211F (0x001cc916) */ - reg = <0>; - max-speed = <1000>; - eee-broken-1000t; - - reset-assert-us = <10000>; - reset-deassert-us = <30000>; - reset-gpios = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; - - interrupt-parent = <&gpio_intc>; - /* MAC_INTR on GPIOZ_14 */ - interrupts = <26 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -ðmac { - pinctrl-0 = <ð_pins>, <ð_rgmii_pins>; - pinctrl-names = "default"; - status = "okay"; - phy-mode = "rgmii"; - phy-handle = <&external_phy>; - amlogic,tx-delay-ns = <2>; -}; - -&pwm_ef { - status = "okay"; - pinctrl-0 = <&pwm_e_pins>; - pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin0"; -}; - -&uart_A { - status = "okay"; - pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; - pinctrl-names = "default"; - uart-has-rtscts; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; - max-speed = <2000000>; - clocks = <&wifi32k>; - clock-names = "lpo"; - }; -}; - -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -&usb { - status = "okay"; - dr_mode = "host"; -}; - -/* SDIO */ -&sd_emmc_a { - status = "okay"; - pinctrl-0 = <&sdio_pins>; - pinctrl-1 = <&sdio_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - #address-cells = <1>; - #size-cells = <0>; - - bus-width = <4>; - cap-sd-highspeed; - sd-uhs-sdr50; - max-frequency = <100000000>; - - non-removable; - disable-wp; - - /* WiFi firmware requires power to be kept while in suspend */ - keep-power-in-suspend; - - mmc-pwrseq = <&sdio_pwrseq>; - - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddao_1v8>; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - }; -}; - -/* SD card */ -&sd_emmc_b { - status = "okay"; - pinctrl-0 = <&sdcard_c_pins>; - pinctrl-1 = <&sdcard_clk_gate_c_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <100000000>; - disable-wp; - - cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>; - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddao_3v3>; -}; - -/* eMMC */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - max-frequency = <100000000>; - non-removable; - disable-wp; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&flash_1v8>; -}; - -&spdifout { - pinctrl-0 = <&spdif_out_h_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&spdifout_b { - status = "okay"; -}; - -&tdmif_b { - status = "okay"; -}; - -&tdmout_b { - status = "okay"; -}; - -&tohdmitx { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/amlogic/meson-g12a.dtsi b/sys/gnu/dts/arm64/amlogic/meson-g12a.dtsi deleted file mode 100644 index fb0ab27d1f6..00000000000 --- a/sys/gnu/dts/arm64/amlogic/meson-g12a.dtsi +++ /dev/null @@ -1,135 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2018 Amlogic, Inc. All rights reserved. - */ - -#include "meson-g12.dtsi" - -/ { - compatible = "amlogic,g12a"; - - cpus { - #address-cells = <0x2>; - #size-cells = <0x0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x0>; - enable-method = "psci"; - next-level-cache = <&l2>; - #cooling-cells = <2>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x1>; - enable-method = "psci"; - next-level-cache = <&l2>; - #cooling-cells = <2>; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x2>; - enable-method = "psci"; - next-level-cache = <&l2>; - #cooling-cells = <2>; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x3>; - enable-method = "psci"; - next-level-cache = <&l2>; - #cooling-cells = <2>; - }; - - l2: l2-cache0 { - compatible = "cache"; - }; - }; - - cpu_opp_table: opp-table { - compatible = "operating-points-v2"; - opp-shared; - - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - opp-microvolt = <731000>; - }; - - opp-250000000 { - opp-hz = /bits/ 64 <250000000>; - opp-microvolt = <731000>; - }; - - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <731000>; - }; - - opp-667000000 { - opp-hz = /bits/ 64 <666666666>; - opp-microvolt = <731000>; - }; - - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <731000>; - }; - - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <731000>; - }; - - opp-1398000000 { - opp-hz = /bits/ 64 <1398000000>; - opp-microvolt = <761000>; - }; - - opp-1512000000 { - opp-hz = /bits/ 64 <1512000000>; - opp-microvolt = <791000>; - }; - - opp-1608000000 { - opp-hz = /bits/ 64 <1608000000>; - opp-microvolt = <831000>; - }; - - opp-1704000000 { - opp-hz = /bits/ 64 <1704000000>; - opp-microvolt = <861000>; - }; - - opp-1800000000 { - opp-hz = /bits/ 64 <1800000000>; - opp-microvolt = <981000>; - }; - }; -}; - -&cpu_thermal { - cooling-maps { - map0 { - trip = <&cpu_passive>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - - map1 { - trip = <&cpu_hot>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/amlogic/meson-g12b-a311d-khadas-vim3.dts b/sys/gnu/dts/arm64/amlogic/meson-g12b-a311d-khadas-vim3.dts deleted file mode 100644 index 124a8090108..00000000000 --- a/sys/gnu/dts/arm64/amlogic/meson-g12b-a311d-khadas-vim3.dts +++ /dev/null @@ -1,41 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 BayLibre, SAS - * Author: Neil Armstrong - * Copyright (c) 2019 Christian Hewitt - */ - -/dts-v1/; - -#include "meson-g12b-a311d.dtsi" -#include "meson-khadas-vim3.dtsi" -#include "meson-g12b-khadas-vim3.dtsi" - -/ { - compatible = "khadas,vim3", "amlogic,a311d", "amlogic,g12b"; -}; - -/* - * The VIM3 on-board MCU can mux the PCIe/USB3.0 shared differential - * lines using a FUSB340TMX USB 3.1 SuperSpeed Data Switch between - * an USB3.0 Type A connector and a M.2 Key M slot. - * The PHY driving these differential lines is shared between - * the USB3.0 controller and the PCIe Controller, thus only - * a single controller can use it. - * If the MCU is configured to mux the PCIe/USB3.0 differential lines - * to the M.2 Key M slot, uncomment the following block to disable - * USB3.0 from the USB Complex and enable the PCIe controller. - * The End User is not expected to uncomment the following except for - * testing purposes, but instead rely on the firmware/bootloader to - * update these nodes accordingly if PCIe mode is selected by the MCU. - */ -/* -&pcie { - status = "okay"; -}; - -&usb { - phys = <&usb2_phy0>, <&usb2_phy1>; - phy-names = "usb2-phy0", "usb2-phy1"; -}; - */ diff --git a/sys/gnu/dts/arm64/amlogic/meson-g12b-a311d.dtsi b/sys/gnu/dts/arm64/amlogic/meson-g12b-a311d.dtsi deleted file mode 100644 index d61f43052a3..00000000000 --- a/sys/gnu/dts/arm64/amlogic/meson-g12b-a311d.dtsi +++ /dev/null @@ -1,149 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 BayLibre, SAS - * Author: Neil Armstrong - */ - -#include "meson-g12b.dtsi" - -/ { - cpu_opp_table_0: opp-table-0 { - compatible = "operating-points-v2"; - opp-shared; - - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - opp-microvolt = <731000>; - }; - - opp-250000000 { - opp-hz = /bits/ 64 <250000000>; - opp-microvolt = <731000>; - }; - - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <731000>; - }; - - opp-667000000 { - opp-hz = /bits/ 64 <667000000>; - opp-microvolt = <731000>; - }; - - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <761000>; - }; - - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <781000>; - }; - - opp-1398000000 { - opp-hz = /bits/ 64 <1398000000>; - opp-microvolt = <811000>; - }; - - opp-1512000000 { - opp-hz = /bits/ 64 <1512000000>; - opp-microvolt = <861000>; - }; - - opp-1608000000 { - opp-hz = /bits/ 64 <1608000000>; - opp-microvolt = <901000>; - }; - - opp-1704000000 { - opp-hz = /bits/ 64 <1704000000>; - opp-microvolt = <951000>; - }; - - opp-1800000000 { - opp-hz = /bits/ 64 <1800000000>; - opp-microvolt = <1001000>; - }; - }; - - cpub_opp_table_1: opp-table-1 { - compatible = "operating-points-v2"; - opp-shared; - - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - opp-microvolt = <731000>; - }; - - opp-250000000 { - opp-hz = /bits/ 64 <250000000>; - opp-microvolt = <731000>; - }; - - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <731000>; - }; - - opp-667000000 { - opp-hz = /bits/ 64 <667000000>; - opp-microvolt = <731000>; - }; - - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <731000>; - }; - - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <751000>; - }; - - opp-1398000000 { - opp-hz = /bits/ 64 <1398000000>; - opp-microvolt = <771000>; - }; - - opp-1512000000 { - opp-hz = /bits/ 64 <1512000000>; - opp-microvolt = <771000>; - }; - - opp-1608000000 { - opp-hz = /bits/ 64 <1608000000>; - opp-microvolt = <781000>; - }; - - opp-1704000000 { - opp-hz = /bits/ 64 <1704000000>; - opp-microvolt = <791000>; - }; - - opp-1800000000 { - opp-hz = /bits/ 64 <1800000000>; - opp-microvolt = <831000>; - }; - - opp-1908000000 { - opp-hz = /bits/ 64 <1908000000>; - opp-microvolt = <861000>; - }; - - opp-2016000000 { - opp-hz = /bits/ 64 <2016000000>; - opp-microvolt = <911000>; - }; - - opp-2108000000 { - opp-hz = /bits/ 64 <2108000000>; - opp-microvolt = <951000>; - }; - - opp-2208000000 { - opp-hz = /bits/ 64 <2208000000>; - opp-microvolt = <1011000>; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/amlogic/meson-g12b-khadas-vim3.dtsi b/sys/gnu/dts/arm64/amlogic/meson-g12b-khadas-vim3.dtsi deleted file mode 100644 index 554863429aa..00000000000 --- a/sys/gnu/dts/arm64/amlogic/meson-g12b-khadas-vim3.dtsi +++ /dev/null @@ -1,189 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 BayLibre, SAS - * Author: Neil Armstrong - * Copyright (c) 2019 Christian Hewitt - */ - -#include - -/ { - vddcpu_a: regulator-vddcpu-a { - /* - * MP8756GD Regulator. - */ - compatible = "pwm-regulator"; - - regulator-name = "VDDCPU_A"; - regulator-min-microvolt = <690000>; - regulator-max-microvolt = <1050000>; - - vin-supply = <&dc_in>; - - pwms = <&pwm_ab 0 1250 0>; - pwm-dutycycle-range = <100 0>; - - regulator-boot-on; - regulator-always-on; - }; - - vddcpu_b: regulator-vddcpu-b { - /* - * Silergy SY8030DEC Regulator. - */ - compatible = "pwm-regulator"; - - regulator-name = "VDDCPU_B"; - regulator-min-microvolt = <690000>; - regulator-max-microvolt = <1050000>; - - vin-supply = <&vsys_3v3>; - - pwms = <&pwm_AO_cd 1 1250 0>; - pwm-dutycycle-range = <100 0>; - - regulator-boot-on; - regulator-always-on; - }; - - sound { - compatible = "amlogic,axg-sound-card"; - model = "G12A-KHADAS-VIM3"; - audio-aux-devs = <&tdmout_b>; - audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1", - "TDMOUT_B IN 1", "FRDDR_B OUT 1", - "TDMOUT_B IN 2", "FRDDR_C OUT 1", - "TDM_B Playback", "TDMOUT_B OUT"; - - assigned-clocks = <&clkc CLKID_MPLL2>, - <&clkc CLKID_MPLL0>, - <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; - assigned-clock-rates = <294912000>, - <270950400>, - <393216000>; - status = "okay"; - - dai-link-0 { - sound-dai = <&frddr_a>; - }; - - dai-link-1 { - sound-dai = <&frddr_b>; - }; - - dai-link-2 { - sound-dai = <&frddr_c>; - }; - - /* 8ch hdmi interface */ - dai-link-3 { - sound-dai = <&tdmif_b>; - dai-format = "i2s"; - dai-tdm-slot-tx-mask-0 = <1 1>; - dai-tdm-slot-tx-mask-1 = <1 1>; - dai-tdm-slot-tx-mask-2 = <1 1>; - dai-tdm-slot-tx-mask-3 = <1 1>; - mclk-fs = <256>; - - codec { - sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>; - }; - }; - - /* hdmi glue */ - dai-link-4 { - sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; - - codec { - sound-dai = <&hdmi_tx>; - }; - }; - }; -}; - -&arb { - status = "okay"; -}; - -&clkc_audio { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <&vddcpu_b>; - operating-points-v2 = <&cpu_opp_table_0>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cpu1 { - cpu-supply = <&vddcpu_b>; - operating-points-v2 = <&cpu_opp_table_0>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cpu100 { - cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; -}; - -&cpu101 { - cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; -}; - -&cpu102 { - cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; -}; - -&cpu103 { - cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; -}; - -&frddr_b { - status = "okay"; -}; - -&frddr_c { - status = "okay"; -}; - -&pwm_ab { - pinctrl-0 = <&pwm_a_e_pins>; - pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin0"; - status = "okay"; -}; - -&pwm_AO_cd { - pinctrl-0 = <&pwm_ao_d_e_pins>; - pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin1"; - status = "okay"; -}; - -&tdmif_b { - status = "okay"; -}; - -&tdmout_b { - status = "okay"; -}; - -&tohdmitx { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/amlogic/meson-g12b-odroid-n2.dts b/sys/gnu/dts/arm64/amlogic/meson-g12b-odroid-n2.dts deleted file mode 100644 index 0e54c1dc284..00000000000 --- a/sys/gnu/dts/arm64/amlogic/meson-g12b-odroid-n2.dts +++ /dev/null @@ -1,484 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 BayLibre, SAS - * Author: Neil Armstrong - */ - -/dts-v1/; - -#include "meson-g12b-s922x.dtsi" -#include -#include -#include - -/ { - compatible = "hardkernel,odroid-n2", "amlogic,s922x", "amlogic,g12b"; - model = "Hardkernel ODROID-N2"; - - aliases { - serial0 = &uart_AO; - ethernet0 = ðmac; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x40000000>; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>; - }; - - leds { - compatible = "gpio-leds"; - - blue { - label = "n2:blue"; - gpios = <&gpio_ao GPIOAO_11 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - tflash_vdd: regulator-tflash_vdd { - compatible = "regulator-fixed"; - - regulator-name = "TFLASH_VDD"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&gpio_ao GPIOAO_8 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - }; - - tf_io: gpio-regulator-tf_io { - compatible = "regulator-gpio"; - - regulator-name = "TF_IO"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio_ao GPIOAO_9 GPIO_ACTIVE_HIGH>; - gpios-states = <0>; - - states = <3300000 0>, - <1800000 1>; - }; - - flash_1v8: regulator-flash_1v8 { - compatible = "regulator-fixed"; - regulator-name = "FLASH_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_3v3>; - regulator-always-on; - }; - - main_12v: regulator-main_12v { - compatible = "regulator-fixed"; - regulator-name = "12V"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-always-on; - }; - - vcc_5v: regulator-vcc_5v { - compatible = "regulator-fixed"; - regulator-name = "5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - vin-supply = <&main_12v>; - }; - - vcc_1v8: regulator-vcc_1v8 { - compatible = "regulator-fixed"; - regulator-name = "VCC_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_3v3>; - regulator-always-on; - }; - - vcc_3v3: regulator-vcc_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vddao_3v3>; - regulator-always-on; - /* FIXME: actually controlled by VDDCPU_B_EN */ - }; - - vddcpu_a: regulator-vddcpu-a { - /* - * MP8756GD Regulator. - */ - compatible = "pwm-regulator"; - - regulator-name = "VDDCPU_A"; - regulator-min-microvolt = <721000>; - regulator-max-microvolt = <1022000>; - - vin-supply = <&main_12v>; - - pwms = <&pwm_ab 0 1250 0>; - pwm-dutycycle-range = <100 0>; - - regulator-boot-on; - regulator-always-on; - }; - - vddcpu_b: regulator-vddcpu-b { - /* - * Silergy SY8120B1ABC Regulator. - */ - compatible = "pwm-regulator"; - - regulator-name = "VDDCPU_B"; - regulator-min-microvolt = <721000>; - regulator-max-microvolt = <1022000>; - - vin-supply = <&main_12v>; - - pwms = <&pwm_AO_cd 1 1250 0>; - pwm-dutycycle-range = <100 0>; - - regulator-boot-on; - regulator-always-on; - }; - - hub_5v: regulator-hub_5v { - compatible = "regulator-fixed"; - regulator-name = "HUB_5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc_5v>; - - /* Connected to the Hub CHIPENABLE, LOW sets low power state */ - gpio = <&gpio GPIOH_5 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - usb_pwr_en: regulator-usb_pwr_en { - compatible = "regulator-fixed"; - regulator-name = "USB_PWR_EN"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc_5v>; - - /* Connected to the microUSB port power enable */ - gpio = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vddao_1v8: regulator-vddao_1v8 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vddao_3v3>; - regulator-always-on; - }; - - vddao_3v3: regulator-vddao_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&main_12v>; - regulator-always-on; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; - }; - - sound { - compatible = "amlogic,axg-sound-card"; - model = "G12A-ODROIDN2"; - audio-aux-devs = <&tdmout_b>; - audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1", - "TDMOUT_B IN 1", "FRDDR_B OUT 1", - "TDMOUT_B IN 2", "FRDDR_C OUT 1", - "TDM_B Playback", "TDMOUT_B OUT"; - - assigned-clocks = <&clkc CLKID_MPLL2>, - <&clkc CLKID_MPLL0>, - <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; - assigned-clock-rates = <294912000>, - <270950400>, - <393216000>; - status = "okay"; - - dai-link-0 { - sound-dai = <&frddr_a>; - }; - - dai-link-1 { - sound-dai = <&frddr_b>; - }; - - dai-link-2 { - sound-dai = <&frddr_c>; - }; - - /* 8ch hdmi interface */ - dai-link-3 { - sound-dai = <&tdmif_b>; - dai-format = "i2s"; - dai-tdm-slot-tx-mask-0 = <1 1>; - dai-tdm-slot-tx-mask-1 = <1 1>; - dai-tdm-slot-tx-mask-2 = <1 1>; - dai-tdm-slot-tx-mask-3 = <1 1>; - mclk-fs = <256>; - - codec { - sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>; - }; - }; - - /* hdmi glue */ - dai-link-4 { - sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; - - codec { - sound-dai = <&hdmi_tx>; - }; - }; - }; -}; - -&arb { - status = "okay"; -}; - -&cec_AO { - pinctrl-0 = <&cec_ao_a_h_pins>; - pinctrl-names = "default"; - status = "disabled"; - hdmi-phandle = <&hdmi_tx>; -}; - -&cecb_AO { - pinctrl-0 = <&cec_ao_b_h_pins>; - pinctrl-names = "default"; - status = "okay"; - hdmi-phandle = <&hdmi_tx>; -}; - -&clkc_audio { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <&vddcpu_b>; - operating-points-v2 = <&cpu_opp_table_0>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cpu1 { - cpu-supply = <&vddcpu_b>; - operating-points-v2 = <&cpu_opp_table_0>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cpu100 { - cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; -}; - -&cpu101 { - cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; -}; - -&cpu102 { - cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; -}; - -&cpu103 { - cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; -}; - -&ext_mdio { - external_phy: ethernet-phy@0 { - /* Realtek RTL8211F (0x001cc916) */ - reg = <0>; - max-speed = <1000>; - - reset-assert-us = <10000>; - reset-deassert-us = <30000>; - reset-gpios = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; - - interrupt-parent = <&gpio_intc>; - /* MAC_INTR on GPIOZ_14 */ - interrupts = <26 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -ðmac { - pinctrl-0 = <ð_pins>, <ð_rgmii_pins>; - pinctrl-names = "default"; - status = "okay"; - phy-mode = "rgmii"; - phy-handle = <&external_phy>; - amlogic,tx-delay-ns = <2>; -}; - -&frddr_a { - status = "okay"; -}; - -&frddr_b { - status = "okay"; -}; - -&frddr_c { - status = "okay"; -}; - -&gpio { - /* - * WARNING: The USB Hub on the Odroid-N2 needs a reset signal - * to be turned high in order to be detected by the USB Controller - * This signal should be handled by a USB specific power sequence - * in order to reset the Hub when USB bus is powered down. - */ - usb-hub { - gpio-hog; - gpios = ; - output-high; - line-name = "usb-hub-reset"; - }; -}; - -&hdmi_tx { - status = "okay"; - pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>; - pinctrl-names = "default"; - hdmi-supply = <&vcc_5v>; -}; - -&hdmi_tx_tmds_port { - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; -}; - -&ir { - status = "okay"; - pinctrl-0 = <&remote_input_ao_pins>; - pinctrl-names = "default"; - linux,rc-map-name = "rc-odroid"; -}; - -&pwm_ab { - pinctrl-0 = <&pwm_a_e_pins>; - pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin0"; - status = "okay"; -}; - -&pwm_AO_cd { - pinctrl-0 = <&pwm_ao_d_e_pins>; - pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin1"; - status = "okay"; -}; - -/* SD card */ -&sd_emmc_b { - status = "okay"; - pinctrl-0 = <&sdcard_c_pins>; - pinctrl-1 = <&sdcard_clk_gate_c_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <50000000>; - disable-wp; - - cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>; - vmmc-supply = <&tflash_vdd>; - vqmmc-supply = <&tf_io>; - -}; - -/* eMMC */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - max-frequency = <200000000>; - disable-wp; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&flash_1v8>; -}; - -&tdmif_b { - status = "okay"; -}; - -&tdmout_b { - status = "okay"; -}; - -&tohdmitx { - status = "okay"; -}; - -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -&usb { - status = "okay"; - vbus-supply = <&usb_pwr_en>; -}; - -&usb2_phy0 { - phy-supply = <&vcc_5v>; -}; - -&usb2_phy1 { - /* Enable the hub which is connected to this port */ - phy-supply = <&hub_5v>; -}; diff --git a/sys/gnu/dts/arm64/amlogic/meson-g12b-s922x-khadas-vim3.dts b/sys/gnu/dts/arm64/amlogic/meson-g12b-s922x-khadas-vim3.dts deleted file mode 100644 index bba98f982ad..00000000000 --- a/sys/gnu/dts/arm64/amlogic/meson-g12b-s922x-khadas-vim3.dts +++ /dev/null @@ -1,41 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 BayLibre, SAS - * Author: Neil Armstrong - * Copyright (c) 2019 Christian Hewitt - */ - -/dts-v1/; - -#include "meson-g12b-s922x.dtsi" -#include "meson-khadas-vim3.dtsi" -#include "meson-g12b-khadas-vim3.dtsi" - -/ { - compatible = "khadas,vim3", "amlogic,s922x", "amlogic,g12b"; -}; - -/* - * The VIM3 on-board MCU can mux the PCIe/USB3.0 shared differential - * lines using a FUSB340TMX USB 3.1 SuperSpeed Data Switch between - * an USB3.0 Type A connector and a M.2 Key M slot. - * The PHY driving these differential lines is shared between - * the USB3.0 controller and the PCIe Controller, thus only - * a single controller can use it. - * If the MCU is configured to mux the PCIe/USB3.0 differential lines - * to the M.2 Key M slot, uncomment the following block to disable - * USB3.0 from the USB Complex and enable the PCIe controller. - * The End User is not expected to uncomment the following except for - * testing purposes, but instead rely on the firmware/bootloader to - * update these nodes accordingly if PCIe mode is selected by the MCU. - */ -/* -&pcie { - status = "okay"; -}; - -&usb { - phys = <&usb2_phy0>, <&usb2_phy1>; - phy-names = "usb2-phy0", "usb2-phy1"; -}; - */ diff --git a/sys/gnu/dts/arm64/amlogic/meson-g12b-s922x.dtsi b/sys/gnu/dts/arm64/amlogic/meson-g12b-s922x.dtsi deleted file mode 100644 index 046cc332d07..00000000000 --- a/sys/gnu/dts/arm64/amlogic/meson-g12b-s922x.dtsi +++ /dev/null @@ -1,124 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 BayLibre, SAS - * Author: Neil Armstrong - */ - -#include "meson-g12b.dtsi" - -/ { - cpu_opp_table_0: opp-table-0 { - compatible = "operating-points-v2"; - opp-shared; - - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - opp-microvolt = <731000>; - }; - - opp-250000000 { - opp-hz = /bits/ 64 <250000000>; - opp-microvolt = <731000>; - }; - - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <731000>; - }; - - opp-667000000 { - opp-hz = /bits/ 64 <667000000>; - opp-microvolt = <731000>; - }; - - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <731000>; - }; - - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <731000>; - }; - - opp-1398000000 { - opp-hz = /bits/ 64 <1398000000>; - opp-microvolt = <761000>; - }; - - opp-1512000000 { - opp-hz = /bits/ 64 <1512000000>; - opp-microvolt = <791000>; - }; - - opp-1608000000 { - opp-hz = /bits/ 64 <1608000000>; - opp-microvolt = <831000>; - }; - - opp-1704000000 { - opp-hz = /bits/ 64 <1704000000>; - opp-microvolt = <861000>; - }; - - opp-1896000000 { - opp-hz = /bits/ 64 <1896000000>; - opp-microvolt = <981000>; - }; - }; - - cpub_opp_table_1: opp-table-1 { - compatible = "operating-points-v2"; - opp-shared; - - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - opp-microvolt = <751000>; - }; - - opp-250000000 { - opp-hz = /bits/ 64 <250000000>; - opp-microvolt = <751000>; - }; - - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <751000>; - }; - - opp-667000000 { - opp-hz = /bits/ 64 <667000000>; - opp-microvolt = <751000>; - }; - - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <771000>; - }; - - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <771000>; - }; - - opp-1398000000 { - opp-hz = /bits/ 64 <1398000000>; - opp-microvolt = <791000>; - }; - - opp-1512000000 { - opp-hz = /bits/ 64 <1512000000>; - opp-microvolt = <821000>; - }; - - opp-1608000000 { - opp-hz = /bits/ 64 <1608000000>; - opp-microvolt = <861000>; - }; - - opp-1704000000 { - opp-hz = /bits/ 64 <1704000000>; - opp-microvolt = <891000>; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/amlogic/meson-g12b-ugoos-am6.dts b/sys/gnu/dts/arm64/amlogic/meson-g12b-ugoos-am6.dts deleted file mode 100644 index ccd0bced01e..00000000000 --- a/sys/gnu/dts/arm64/amlogic/meson-g12b-ugoos-am6.dts +++ /dev/null @@ -1,557 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 BayLibre, SAS - * Author: Neil Armstrong - * Copyright (c) 2019 Christian Hewitt - */ - -/dts-v1/; - -#include "meson-g12b.dtsi" -#include "meson-g12b-s922x.dtsi" -#include -#include -#include - -/ { - compatible = "ugoos,am6", "amlogic,g12b"; - model = "Ugoos AM6"; - - aliases { - serial0 = &uart_AO; - ethernet0 = ðmac; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x40000000>; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; - clocks = <&wifi32k>; - clock-names = "ext_clock"; - }; - - spdif_dit: audio-codec-1 { - #sound-dai-cells = <0>; - compatible = "linux,spdif-dit"; - status = "okay"; - sound-name-prefix = "DIT"; - }; - - flash_1v8: regulator-flash_1v8 { - compatible = "regulator-fixed"; - regulator-name = "FLASH_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_3v3>; - regulator-always-on; - }; - - main_12v: regulator-main_12v { - compatible = "regulator-fixed"; - regulator-name = "12V"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-always-on; - }; - - vcc_5v: regulator-vcc_5v { - compatible = "regulator-fixed"; - regulator-name = "VCC_5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&main_12v>; - - gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>; - enable-active-high; - }; - - vcc_1v8: regulator-vcc_1v8 { - compatible = "regulator-fixed"; - regulator-name = "VCC_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_3v3>; - regulator-always-on; - }; - - vcc_3v3: regulator-vcc_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vddao_3v3>; - regulator-always-on; - /* FIXME: actually controlled by VDDCPU_B_EN */ - }; - - vddcpu_a: regulator-vddcpu-a { - /* - * MP1653 Regulator. - */ - compatible = "pwm-regulator"; - - regulator-name = "VDDCPU_A"; - regulator-min-microvolt = <721000>; - regulator-max-microvolt = <1022000>; - - vin-supply = <&main_12v>; - - pwms = <&pwm_ab 0 1250 0>; - pwm-dutycycle-range = <100 0>; - - regulator-boot-on; - regulator-always-on; - }; - - vddcpu_b: regulator-vddcpu-b { - /* - * MP1652 Regulator. - */ - compatible = "pwm-regulator"; - - regulator-name = "VDDCPU_B"; - regulator-min-microvolt = <721000>; - regulator-max-microvolt = <1022000>; - - vin-supply = <&main_12v>; - - pwms = <&pwm_AO_cd 1 1250 0>; - pwm-dutycycle-range = <100 0>; - - regulator-boot-on; - regulator-always-on; - }; - - usb1_pow: regulator-usb1-pow { - compatible = "regulator-fixed"; - regulator-name = "USB1_POW"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc_5v>; - - /* connected to SY6280A Power Switch */ - gpio = <&gpio GPIOA_8 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - usb_pwr_en: regulator-usb-pwr-en { - compatible = "regulator-fixed"; - regulator-name = "USB_PWR_EN"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc_5v>; - - /* Connected to USB3 Type-A Port power enable */ - gpio = <&gpio GPIOAO_7 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vddao_1v8: regulator-vddao-1v8 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vddao_3v3>; - regulator-always-on; - }; - - vddao_3v3: regulator-vddao-3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&main_12v>; - regulator-always-on; - }; - - cvbs-connector { - compatible = "composite-video-connector"; - - port { - cvbs_connector_in: endpoint { - remote-endpoint = <&cvbs_vdac_out>; - }; - }; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; - }; - - sound { - compatible = "amlogic,axg-sound-card"; - model = "G12B-UGOOS-AM6"; - audio-aux-devs = <&tdmout_b>; - audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1", - "TDMOUT_B IN 1", "FRDDR_B OUT 1", - "TDMOUT_B IN 2", "FRDDR_C OUT 1", - "TDM_B Playback", "TDMOUT_B OUT", - "SPDIFOUT IN 0", "FRDDR_A OUT 3", - "SPDIFOUT IN 1", "FRDDR_B OUT 3", - "SPDIFOUT IN 2", "FRDDR_C OUT 3"; - - assigned-clocks = <&clkc CLKID_MPLL2>, - <&clkc CLKID_MPLL0>, - <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; - assigned-clock-rates = <294912000>, - <270950400>, - <393216000>; - status = "okay"; - - dai-link-0 { - sound-dai = <&frddr_a>; - }; - - dai-link-1 { - sound-dai = <&frddr_b>; - }; - - dai-link-2 { - sound-dai = <&frddr_c>; - }; - - /* 8ch hdmi interface */ - dai-link-3 { - sound-dai = <&tdmif_b>; - dai-format = "i2s"; - dai-tdm-slot-tx-mask-0 = <1 1>; - dai-tdm-slot-tx-mask-1 = <1 1>; - dai-tdm-slot-tx-mask-2 = <1 1>; - dai-tdm-slot-tx-mask-3 = <1 1>; - mclk-fs = <256>; - - codec { - sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>; - }; - }; - - /* spdif hdmi or toslink interface */ - dai-link-4 { - sound-dai = <&spdifout>; - - codec-0 { - sound-dai = <&spdif_dit>; - }; - - codec-1 { - sound-dai = <&tohdmitx TOHDMITX_SPDIF_IN_A>; - }; - }; - - /* spdif hdmi interface */ - dai-link-5 { - sound-dai = <&spdifout_b>; - - codec { - sound-dai = <&tohdmitx TOHDMITX_SPDIF_IN_B>; - }; - }; - - /* hdmi glue */ - dai-link-6 { - sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; - - codec { - sound-dai = <&hdmi_tx>; - }; - }; - }; - - wifi32k: wifi32k { - compatible = "pwm-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ - }; -}; - -&arb { - status = "okay"; -}; - -&cec_AO { - pinctrl-0 = <&cec_ao_a_h_pins>; - pinctrl-names = "default"; - status = "disabled"; - hdmi-phandle = <&hdmi_tx>; -}; - -&cecb_AO { - pinctrl-0 = <&cec_ao_b_h_pins>; - pinctrl-names = "default"; - status = "okay"; - hdmi-phandle = <&hdmi_tx>; -}; - -&clkc_audio { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <&vddcpu_b>; - operating-points-v2 = <&cpu_opp_table_0>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cpu1 { - cpu-supply = <&vddcpu_b>; - operating-points-v2 = <&cpu_opp_table_0>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cpu100 { - cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; -}; - -&cpu101 { - cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; -}; - -&cpu102 { - cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; -}; - -&cpu103 { - cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; -}; - -&cvbs_vdac_port { - cvbs_vdac_out: endpoint { - remote-endpoint = <&cvbs_connector_in>; - }; -}; - -&ext_mdio { - external_phy: ethernet-phy@0 { - /* Realtek RTL8211F (0x001cc916) */ - reg = <0>; - max-speed = <1000>; - - reset-assert-us = <10000>; - reset-deassert-us = <30000>; - reset-gpios = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; - - interrupt-parent = <&gpio_intc>; - /* MAC_INTR on GPIOZ_14 */ - interrupts = <26 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -ðmac { - pinctrl-0 = <ð_pins>, <ð_rgmii_pins>; - pinctrl-names = "default"; - status = "okay"; - phy-mode = "rgmii"; - phy-handle = <&external_phy>; - amlogic,tx-delay-ns = <2>; -}; - -&frddr_a { - status = "okay"; -}; - -&frddr_b { - status = "okay"; -}; - -&frddr_c { - status = "okay"; -}; - -&hdmi_tx { - status = "okay"; - pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>; - pinctrl-names = "default"; - hdmi-supply = <&vcc_5v>; -}; - -&hdmi_tx_tmds_port { - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; -}; - -&ir { - status = "okay"; - pinctrl-0 = <&remote_input_ao_pins>; - pinctrl-names = "default"; - linux,rc-map-name = "rc-khadas"; -}; - -&pwm_ab { - pinctrl-0 = <&pwm_a_e_pins>; - pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin0"; - status = "okay"; -}; - -&pwm_AO_cd { - pinctrl-0 = <&pwm_ao_d_e_pins>; - pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin1"; - status = "okay"; -}; - -&pwm_ef { - pinctrl-0 = <&pwm_e_pins>; - pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin0"; - status = "okay"; -}; - -/* SDIO */ -&sd_emmc_a { - status = "okay"; - pinctrl-0 = <&sdio_pins>; - pinctrl-1 = <&sdio_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - #address-cells = <1>; - #size-cells = <0>; - - bus-width = <4>; - cap-sd-highspeed; - sd-uhs-sdr50; - max-frequency = <100000000>; - - non-removable; - disable-wp; - - mmc-pwrseq = <&sdio_pwrseq>; - - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddao_1v8>; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - }; -}; - -/* SD card */ -&sd_emmc_b { - status = "okay"; - pinctrl-0 = <&sdcard_c_pins>; - pinctrl-1 = <&sdcard_clk_gate_c_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <50000000>; - disable-wp; - - cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>; - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddao_3v3>; -}; - -/* eMMC */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - max-frequency = <100000000>; - disable-wp; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&flash_1v8>; -}; - -&spdifout { - pinctrl-0 = <&spdif_out_h_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&spdifout_b { - status = "okay"; -}; - -&tdmif_b { - status = "okay"; -}; - -&tdmout_b { - status = "okay"; -}; - -&tohdmitx { - status = "okay"; -}; - -&uart_A { - status = "okay"; - pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; - pinctrl-names = "default"; - uart-has-rtscts; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; - max-speed = <2000000>; - clocks = <&wifi32k>; - clock-names = "lpo"; - }; -}; - -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -&usb { - status = "okay"; - dr_mode = "host"; - vbus-regulator = <&usb_pwr_en>; -}; - -&usb2_phy0 { - phy-supply = <&usb1_pow>; -}; - -&usb2_phy1 { - phy-supply = <&usb1_pow>; -}; diff --git a/sys/gnu/dts/arm64/amlogic/meson-g12b.dtsi b/sys/gnu/dts/arm64/amlogic/meson-g12b.dtsi deleted file mode 100644 index 6dbc3968045..00000000000 --- a/sys/gnu/dts/arm64/amlogic/meson-g12b.dtsi +++ /dev/null @@ -1,115 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 BayLibre, SAS - * Author: Neil Armstrong - */ - -#include "meson-g12.dtsi" - -/ { - compatible = "amlogic,g12b"; - - cpus { - #address-cells = <0x2>; - #size-cells = <0x0>; - - cpu-map { - cluster0 { - core0 { - cpu = <&cpu0>; - }; - - core1 { - cpu = <&cpu1>; - }; - }; - - cluster1 { - core0 { - cpu = <&cpu100>; - }; - - core1 { - cpu = <&cpu101>; - }; - - core2 { - cpu = <&cpu102>; - }; - - core3 { - cpu = <&cpu103>; - }; - }; - }; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x0>; - enable-method = "psci"; - capacity-dmips-mhz = <592>; - next-level-cache = <&l2>; - #cooling-cells = <2>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x1>; - enable-method = "psci"; - capacity-dmips-mhz = <592>; - next-level-cache = <&l2>; - #cooling-cells = <2>; - }; - - cpu100: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a73"; - reg = <0x0 0x100>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - next-level-cache = <&l2>; - #cooling-cells = <2>; - }; - - cpu101: cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a73"; - reg = <0x0 0x101>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - next-level-cache = <&l2>; - #cooling-cells = <2>; - }; - - cpu102: cpu@102 { - device_type = "cpu"; - compatible = "arm,cortex-a73"; - reg = <0x0 0x102>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - next-level-cache = <&l2>; - #cooling-cells = <2>; - }; - - cpu103: cpu@103 { - device_type = "cpu"; - compatible = "arm,cortex-a73"; - reg = <0x0 0x103>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - next-level-cache = <&l2>; - #cooling-cells = <2>; - }; - - l2: l2-cache0 { - compatible = "cache"; - }; - }; -}; - -&clkc { - compatible = "amlogic,g12b-clkc"; -}; - diff --git a/sys/gnu/dts/arm64/amlogic/meson-gx-libretech-pc.dtsi b/sys/gnu/dts/arm64/amlogic/meson-gx-libretech-pc.dtsi deleted file mode 100644 index 248b018c83d..00000000000 --- a/sys/gnu/dts/arm64/amlogic/meson-gx-libretech-pc.dtsi +++ /dev/null @@ -1,375 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2019 BayLibre SAS. - * Author: Jerome Brunet - */ - -/* Libretech Amlogic GX PC form factor - AKA: Tartiflette */ - -#include -#include - -/ { - adc-keys { - compatible = "adc-keys"; - io-channels = <&saradc 0>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1800000>; - - update-button { - label = "update"; - linux,code = ; - press-threshold-microvolt = <1300000>; - }; - }; - - aliases { - serial0 = &uart_AO; - ethernet0 = ðmac; - spi0 = &spifc; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - cvbs-connector { - compatible = "composite-video-connector"; - status = "disabled"; - - port { - cvbs_connector_in: endpoint { - remote-endpoint = <&cvbs_vdac_out>; - }; - }; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - poll-interval = <100>; - - power-button { - label = "power"; - linux,code = ; - gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>; - }; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; - - ao_5v: regulator-ao_5v { - compatible = "regulator-fixed"; - regulator-name = "AO_5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&dc_in>; - regulator-always-on; - }; - - dc_in: regulator-dc_in { - compatible = "regulator-fixed"; - regulator-name = "DC_IN"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - leds { - compatible = "gpio-leds"; - - green { - color = ; - function = LED_FUNCTION_DISK_ACTIVITY; - gpios = <&gpio_ao GPIOAO_9 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "disk-activity"; - }; - - blue { - color = ; - function = LED_FUNCTION_STATUS; - gpios = <&gpio GPIODV_28 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - panic-indicator; - }; - }; - - vcc_card: regulator-vcc_card { - compatible = "regulator-fixed"; - regulator-name = "VCC_CARD"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vddio_ao3v3>; - - gpio = <&gpio GPIODV_4 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vcc5v: regulator-vcc5v { - compatible = "regulator-fixed"; - regulator-name = "VCC5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&ao_5v>; - - gpio = <&gpio GPIOH_3 GPIO_OPEN_DRAIN>; - }; - - vddio_ao18: regulator-vddio_ao18 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&ao_5v>; - regulator-always-on; - }; - - vddio_ao3v3: regulator-vddio_ao3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&ao_5v>; - regulator-always-on; - }; - - vddio_boot: regulator-vddio_boot { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_BOOT"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vddio_ao3v3>; - regulator-always-on; - }; - - vddio_card: regulator-vddio-card { - compatible = "regulator-gpio"; - regulator-name = "VDDIO_CARD"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio GPIODV_5 GPIO_ACTIVE_HIGH>; - gpios-states = <0>; - - states = <3300000 0>, - <1800000 1>; - - regulator-settling-time-up-us = <200>; - regulator-settling-time-down-us = <50000>; - }; -}; - -&cec_AO { - pinctrl-0 = <&ao_cec_pins>; - pinctrl-names = "default"; - hdmi-phandle = <&hdmi_tx>; - status = "okay"; -}; - -&cvbs_vdac_port { - cvbs_vdac_out: endpoint { - remote-endpoint = <&cvbs_connector_in>; - }; -}; - -ðmac { - pinctrl-0 = <ð_pins>, <ð_phy_irq_pins>; - pinctrl-names = "default"; - phy-handle = <&external_phy>; - amlogic,tx-delay-ns = <2>; - phy-mode = "rgmii"; - status = "okay"; -}; - -&external_mdio { - external_phy: ethernet-phy@0 { - reg = <0>; - max-speed = <1000>; - reset-assert-us = <10000>; - reset-deassert-us = <30000>; - reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; - interrupt-parent = <&gpio_intc>; - interrupts = <25 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&pinctrl_periphs { - /* - * Make sure the reset pin of the usb HUB is driven high to take - * it out of reset. - */ - usb1_rst_pins: usb1_rst_irq { - mux { - groups = "GPIODV_3"; - function = "gpio_periphs"; - bias-disable; - output-high; - }; - }; - - /* Make sure the phy irq pin is properly configured as input */ - eth_phy_irq_pins: eth_phy_irq { - mux { - groups = "GPIOZ_15"; - function = "gpio_periphs"; - bias-disable; - output-disable; - }; - }; -}; - -&hdmi_tx { - pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; - pinctrl-names = "default"; - hdmi-supply = <&vcc5v>; - status = "okay"; -}; - -&hdmi_tx_tmds_port { - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; -}; - -&ir { - pinctrl-0 = <&remote_input_ao_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&i2c_C { - pinctrl-0 = <&i2c_c_dv18_pins>; - pinctrl-names = "default"; - status = "okay"; - - rtc: rtc@51 { - reg = <0x51>; - compatible = "nxp,pcf8563"; - #clock-cells = <0>; - clock-output-names = "rtc_clkout"; - }; -}; - -&pwm_AO_ab { - pinctrl-0 = <&pwm_ao_a_3_pins>; - pinctrl-names = "default"; - clocks = <&clkc CLKID_FCLK_DIV4>; - clock-names = "clkin0"; - status = "okay"; -}; - -&pwm_ab { - pinctrl-0 = <&pwm_b_pins>; - pinctrl-names = "default"; - clocks = <&clkc CLKID_FCLK_DIV4>; - clock-names = "clkin0"; - status = "okay"; -}; - -&pwm_ef { - pinctrl-0 = <&pwm_e_pins>, <&pwm_f_clk_pins>; - pinctrl-names = "default"; - clocks = <&clkc CLKID_FCLK_DIV4>; - clock-names = "clkin0"; - status = "okay"; -}; - -&saradc { - vref-supply = <&vddio_ao18>; - status = "okay"; -}; - -/* SD card */ -&sd_emmc_b { - pinctrl-0 = <&sdcard_pins>; - pinctrl-1 = <&sdcard_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-ddr50; - max-frequency = <200000000>; - disable-wp; - - cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; - - vmmc-supply = <&vcc_card>; - vqmmc-supply = <&vddio_card>; - - status = "okay"; -}; - -/* eMMC */ -&sd_emmc_c { - pinctrl-0 = <&emmc_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - max-frequency = <200000000>; - disable-wp; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vddio_ao3v3>; - vqmmc-supply = <&vddio_boot>; - - status = "okay"; -}; - -&spifc { - pinctrl-0 = <&nor_pins>; - pinctrl-names = "default"; - status = "okay"; - - gd25lq128: spi-flash@0 { - compatible = "jedec,spi-nor"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0>; - spi-max-frequency = <12000000>; - }; -}; - -&uart_AO { - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&usb0 { - status = "okay"; -}; - -&usb2_phy0 { - pinctrl-0 = <&usb1_rst_pins>; - pinctrl-names = "default"; - phy-supply = <&vcc5v>; -}; - -&usb2_phy1 { - phy-supply = <&vcc5v>; -}; diff --git a/sys/gnu/dts/arm64/amlogic/meson-gx-p23x-q20x.dtsi b/sys/gnu/dts/arm64/amlogic/meson-gx-p23x-q20x.dtsi deleted file mode 100644 index 12d5e333e5f..00000000000 --- a/sys/gnu/dts/arm64/amlogic/meson-gx-p23x-q20x.dtsi +++ /dev/null @@ -1,228 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Endless Computers, Inc. - * Author: Carlo Caione - */ - -/* Common DTSI for same Amlogic Q200/Q201 and P230/P231 boards using either - * the pin-compatible S912 (GXM) or S905D (GXL) SoCs. - */ - -/ { - aliases { - serial0 = &uart_AO; - ethernet0 = ðmac; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; - - hdmi_5v: regulator-hdmi-5v { - compatible = "regulator-fixed"; - - regulator-name = "HDMI_5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - gpio = <&gpio GPIOH_3 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - }; - - vddio_ao18: regulator-vddio_ao18 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vddio_boot: regulator-vddio_boot { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_BOOT"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vddao_3v3: regulator-vddao_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vcc_3v3: regulator-vcc_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; - }; - - wifi32k: wifi32k { - compatible = "pwm-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; - clocks = <&wifi32k>; - clock-names = "ext_clock"; - }; - - cvbs-connector { - compatible = "composite-video-connector"; - - port { - cvbs_connector_in: endpoint { - remote-endpoint = <&cvbs_vdac_out>; - }; - }; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; - }; -}; - -&cec_AO { - status = "okay"; - pinctrl-0 = <&ao_cec_pins>; - pinctrl-names = "default"; - hdmi-phandle = <&hdmi_tx>; -}; - -&cvbs_vdac_port { - cvbs_vdac_out: endpoint { - remote-endpoint = <&cvbs_connector_in>; - }; -}; - -ðmac { - status = "okay"; -}; - -&hdmi_tx { - status = "okay"; - pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; - pinctrl-names = "default"; - hdmi-supply = <&hdmi_5v>; -}; - -&hdmi_tx_tmds_port { - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; -}; - -&ir { - status = "okay"; - pinctrl-0 = <&remote_input_ao_pins>; - pinctrl-names = "default"; -}; - -&pwm_ef { - status = "okay"; - pinctrl-0 = <&pwm_e_pins>; - pinctrl-names = "default"; - clocks = <&clkc CLKID_FCLK_DIV4>; - clock-names = "clkin0"; -}; - -&saradc { - status = "okay"; - vref-supply = <&vddio_ao18>; -}; - -/* Wireless SDIO Module */ -&sd_emmc_a { - status = "okay"; - pinctrl-0 = <&sdio_pins>; - pinctrl-1 = <&sdio_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - #address-cells = <1>; - #size-cells = <0>; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <50000000>; - - non-removable; - disable-wp; - - /* WiFi firmware requires power to be kept while in suspend */ - keep-power-in-suspend; - - mmc-pwrseq = <&sdio_pwrseq>; - - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddio_boot>; -}; - -/* SD card */ -&sd_emmc_b { - status = "okay"; - pinctrl-0 = <&sdcard_pins>; - pinctrl-1 = <&sdcard_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <50000000>; - disable-wp; - - cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; - - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddio_boot>; -}; - -/* eMMC */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - max-frequency = <200000000>; - non-removable; - disable-wp; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&vddio_boot>; -}; - -/* This UART is brought out to the DB9 connector */ -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -&usb0 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/amlogic/meson-gx.dtsi b/sys/gnu/dts/arm64/amlogic/meson-gx.dtsi deleted file mode 100644 index 40db06e28b6..00000000000 --- a/sys/gnu/dts/arm64/amlogic/meson-gx.dtsi +++ /dev/null @@ -1,594 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Andreas Färber - * - * Copyright (c) 2016 BayLibre, SAS. - * Author: Neil Armstrong - * - * Copyright (c) 2016 Endless Computers, Inc. - * Author: Carlo Caione - */ - -#include -#include -#include - -/ { - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - /* 16 MiB reserved for Hardware ROM Firmware */ - hwrom_reserved: hwrom@0 { - reg = <0x0 0x0 0x0 0x1000000>; - no-map; - }; - - /* 2 MiB reserved for ARM Trusted Firmware (BL31) */ - secmon_reserved: secmon@10000000 { - reg = <0x0 0x10000000 0x0 0x200000>; - no-map; - }; - - /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */ - secmon_reserved_alt: secmon@5000000 { - reg = <0x0 0x05000000 0x0 0x300000>; - no-map; - }; - - linux,cma { - compatible = "shared-dma-pool"; - reusable; - size = <0x0 0x10000000>; - alignment = <0x0 0x400000>; - linux,cma-default; - }; - }; - - chosen { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - simplefb_cvbs: framebuffer-cvbs { - compatible = "amlogic,simple-framebuffer", - "simple-framebuffer"; - amlogic,pipeline = "vpu-cvbs"; - power-domains = <&pwrc_vpu>; - status = "disabled"; - }; - - simplefb_hdmi: framebuffer-hdmi { - compatible = "amlogic,simple-framebuffer", - "simple-framebuffer"; - amlogic,pipeline = "vpu-hdmi"; - power-domains = <&pwrc_vpu>; - status = "disabled"; - }; - }; - - cpus { - #address-cells = <0x2>; - #size-cells = <0x0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x0>; - enable-method = "psci"; - next-level-cache = <&l2>; - clocks = <&scpi_dvfs 0>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x1>; - enable-method = "psci"; - next-level-cache = <&l2>; - clocks = <&scpi_dvfs 0>; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x2>; - enable-method = "psci"; - next-level-cache = <&l2>; - clocks = <&scpi_dvfs 0>; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x3>; - enable-method = "psci"; - next-level-cache = <&l2>; - clocks = <&scpi_dvfs 0>; - }; - - l2: l2-cache0 { - compatible = "cache"; - }; - }; - - arm-pmu { - compatible = "arm,cortex-a53-pmu"; - interrupts = , - , - , - ; - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - xtal: xtal-clk { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "xtal"; - #clock-cells = <0>; - }; - - firmware { - sm: secure-monitor { - compatible = "amlogic,meson-gx-sm", "amlogic,meson-gxbb-sm"; - }; - }; - - efuse: efuse { - compatible = "amlogic,meson-gx-efuse", "amlogic,meson-gxbb-efuse"; - #address-cells = <1>; - #size-cells = <1>; - read-only; - secure-monitor = <&sm>; - - sn: sn@14 { - reg = <0x14 0x10>; - }; - - eth_mac: eth_mac@34 { - reg = <0x34 0x10>; - }; - - bid: bid@46 { - reg = <0x46 0x30>; - }; - }; - - scpi { - compatible = "amlogic,meson-gxbb-scpi", "arm,scpi-pre-1.0"; - mboxes = <&mailbox 1 &mailbox 2>; - shmem = <&cpu_scp_lpri &cpu_scp_hpri>; - - scpi_clocks: clocks { - compatible = "arm,scpi-clocks"; - - scpi_dvfs: scpi_clocks@0 { - compatible = "arm,scpi-dvfs-clocks"; - #clock-cells = <1>; - clock-indices = <0>; - clock-output-names = "vcpu"; - }; - }; - - scpi_sensors: sensors { - compatible = "amlogic,meson-gxbb-scpi-sensors", "arm,scpi-sensors"; - #thermal-sensor-cells = <1>; - }; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - cbus: bus@c1100000 { - compatible = "simple-bus"; - reg = <0x0 0xc1100000 0x0 0x100000>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0xc1100000 0x0 0x100000>; - - gpio_intc: interrupt-controller@9880 { - compatible = "amlogic,meson-gpio-intc"; - reg = <0x0 0x9880 0x0 0x10>; - interrupt-controller; - #interrupt-cells = <2>; - amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>; - status = "disabled"; - }; - - reset: reset-controller@4404 { - compatible = "amlogic,meson-gxbb-reset"; - reg = <0x0 0x04404 0x0 0x9c>; - #reset-cells = <1>; - }; - - uart_A: serial@84c0 { - compatible = "amlogic,meson-gx-uart"; - reg = <0x0 0x84c0 0x0 0x18>; - interrupts = ; - status = "disabled"; - }; - - uart_B: serial@84dc { - compatible = "amlogic,meson-gx-uart"; - reg = <0x0 0x84dc 0x0 0x18>; - interrupts = ; - status = "disabled"; - }; - - i2c_A: i2c@8500 { - compatible = "amlogic,meson-gxbb-i2c"; - reg = <0x0 0x08500 0x0 0x20>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - pwm_ab: pwm@8550 { - compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm"; - reg = <0x0 0x08550 0x0 0x10>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm_cd: pwm@8650 { - compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm"; - reg = <0x0 0x08650 0x0 0x10>; - #pwm-cells = <3>; - status = "disabled"; - }; - - saradc: adc@8680 { - compatible = "amlogic,meson-saradc"; - reg = <0x0 0x8680 0x0 0x34>; - #io-channel-cells = <1>; - interrupts = ; - status = "disabled"; - }; - - pwm_ef: pwm@86c0 { - compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm"; - reg = <0x0 0x086c0 0x0 0x10>; - #pwm-cells = <3>; - status = "disabled"; - }; - - uart_C: serial@8700 { - compatible = "amlogic,meson-gx-uart"; - reg = <0x0 0x8700 0x0 0x18>; - interrupts = ; - status = "disabled"; - }; - - clock-measure@8758 { - compatible = "amlogic,meson-gx-clk-measure"; - reg = <0x0 0x8758 0x0 0x10>; - }; - - i2c_B: i2c@87c0 { - compatible = "amlogic,meson-gxbb-i2c"; - reg = <0x0 0x087c0 0x0 0x20>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c_C: i2c@87e0 { - compatible = "amlogic,meson-gxbb-i2c"; - reg = <0x0 0x087e0 0x0 0x20>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spicc: spi@8d80 { - compatible = "amlogic,meson-gx-spicc"; - reg = <0x0 0x08d80 0x0 0x80>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spifc: spi@8c80 { - compatible = "amlogic,meson-gxbb-spifc"; - reg = <0x0 0x08c80 0x0 0x80>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - watchdog@98d0 { - compatible = "amlogic,meson-gxbb-wdt"; - reg = <0x0 0x098d0 0x0 0x10>; - clocks = <&xtal>; - }; - }; - - gic: interrupt-controller@c4301000 { - compatible = "arm,gic-400"; - reg = <0x0 0xc4301000 0 0x1000>, - <0x0 0xc4302000 0 0x2000>, - <0x0 0xc4304000 0 0x2000>, - <0x0 0xc4306000 0 0x2000>; - interrupt-controller; - interrupts = ; - #interrupt-cells = <3>; - #address-cells = <0>; - }; - - sram: sram@c8000000 { - compatible = "amlogic,meson-gx-sram", "amlogic,meson-gxbb-sram", "mmio-sram"; - reg = <0x0 0xc8000000 0x0 0x14000>; - - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x0 0xc8000000 0x14000>; - - cpu_scp_lpri: scp-shmem@0 { - compatible = "amlogic,meson-gx-scp-shmem", "amlogic,meson-gxbb-scp-shmem"; - reg = <0x13000 0x400>; - }; - - cpu_scp_hpri: scp-shmem@200 { - compatible = "amlogic,meson-gx-scp-shmem", "amlogic,meson-gxbb-scp-shmem"; - reg = <0x13400 0x400>; - }; - }; - - aobus: bus@c8100000 { - compatible = "simple-bus"; - reg = <0x0 0xc8100000 0x0 0x100000>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0xc8100000 0x0 0x100000>; - - sysctrl_AO: sys-ctrl@0 { - compatible = "amlogic,meson-gx-ao-sysctrl", "simple-mfd", "syscon"; - reg = <0x0 0x0 0x0 0x100>; - - pwrc_vpu: power-controller-vpu { - compatible = "amlogic,meson-gx-pwrc-vpu"; - #power-domain-cells = <0>; - amlogic,hhi-sysctrl = <&sysctrl>; - }; - - clkc_AO: clock-controller { - compatible = "amlogic,meson-gx-aoclkc"; - #clock-cells = <1>; - #reset-cells = <1>; - }; - }; - - cec_AO: cec@100 { - compatible = "amlogic,meson-gx-ao-cec"; - reg = <0x0 0x00100 0x0 0x14>; - interrupts = ; - status = "disabled"; - }; - - sec_AO: ao-secure@140 { - compatible = "amlogic,meson-gx-ao-secure", "syscon"; - reg = <0x0 0x140 0x0 0x140>; - amlogic,has-chip-id; - }; - - uart_AO: serial@4c0 { - compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; - reg = <0x0 0x004c0 0x0 0x18>; - interrupts = ; - status = "disabled"; - }; - - uart_AO_B: serial@4e0 { - compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; - reg = <0x0 0x004e0 0x0 0x18>; - interrupts = ; - status = "disabled"; - }; - - i2c_AO: i2c@500 { - compatible = "amlogic,meson-gxbb-i2c"; - reg = <0x0 0x500 0x0 0x20>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - pwm_AO_ab: pwm@550 { - compatible = "amlogic,meson-gx-ao-pwm", "amlogic,meson-gxbb-ao-pwm"; - reg = <0x0 0x00550 0x0 0x10>; - #pwm-cells = <3>; - status = "disabled"; - }; - - ir: ir@580 { - compatible = "amlogic,meson-gx-ir", "amlogic,meson-gxbb-ir"; - reg = <0x0 0x00580 0x0 0x40>; - interrupts = ; - status = "disabled"; - }; - }; - - vdec: video-codec@c8820000 { - compatible = "amlogic,gx-vdec"; - reg = <0x0 0xc8820000 0x0 0x10000>, - <0x0 0xc110a580 0x0 0xe4>; - reg-names = "dos", "esparser"; - - interrupts = , - ; - interrupt-names = "vdec", "esparser"; - - amlogic,ao-sysctrl = <&sysctrl_AO>; - amlogic,canvas = <&canvas>; - }; - - periphs: bus@c8834000 { - compatible = "simple-bus"; - reg = <0x0 0xc8834000 0x0 0x2000>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0xc8834000 0x0 0x2000>; - - hwrng: rng { - compatible = "amlogic,meson-rng"; - reg = <0x0 0x0 0x0 0x4>; - }; - }; - - dmcbus: bus@c8838000 { - compatible = "simple-bus"; - reg = <0x0 0xc8838000 0x0 0x400>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0xc8838000 0x0 0x400>; - - canvas: video-lut@48 { - compatible = "amlogic,canvas"; - reg = <0x0 0x48 0x0 0x14>; - }; - }; - - hiubus: bus@c883c000 { - compatible = "simple-bus"; - reg = <0x0 0xc883c000 0x0 0x2000>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0xc883c000 0x0 0x2000>; - - sysctrl: system-controller@0 { - compatible = "amlogic,meson-gx-hhi-sysctrl", "simple-mfd", "syscon"; - reg = <0 0 0 0x400>; - }; - - mailbox: mailbox@404 { - compatible = "amlogic,meson-gxbb-mhu"; - reg = <0 0x404 0 0x4c>; - interrupts = , - , - ; - #mbox-cells = <1>; - }; - }; - - ethmac: ethernet@c9410000 { - compatible = "amlogic,meson-gxbb-dwmac", - "snps,dwmac-3.70a", - "snps,dwmac"; - reg = <0x0 0xc9410000 0x0 0x10000>, - <0x0 0xc8834540 0x0 0x4>; - interrupts = ; - interrupt-names = "macirq"; - rx-fifo-depth = <4096>; - tx-fifo-depth = <2048>; - status = "disabled"; - }; - - apb: apb@d0000000 { - compatible = "simple-bus"; - reg = <0x0 0xd0000000 0x0 0x200000>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0xd0000000 0x0 0x200000>; - - sd_emmc_a: mmc@70000 { - compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc"; - reg = <0x0 0x70000 0x0 0x800>; - interrupts = ; - status = "disabled"; - }; - - sd_emmc_b: mmc@72000 { - compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc"; - reg = <0x0 0x72000 0x0 0x800>; - interrupts = ; - status = "disabled"; - }; - - sd_emmc_c: mmc@74000 { - compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc"; - reg = <0x0 0x74000 0x0 0x800>; - interrupts = ; - status = "disabled"; - }; - }; - - vpu: vpu@d0100000 { - compatible = "amlogic,meson-gx-vpu"; - reg = <0x0 0xd0100000 0x0 0x100000>, - <0x0 0xc883c000 0x0 0x1000>; - reg-names = "vpu", "hhi"; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - amlogic,canvas = <&canvas>; - - /* CVBS VDAC output port */ - cvbs_vdac_port: port@0 { - reg = <0>; - }; - - /* HDMI-TX output port */ - hdmi_tx_port: port@1 { - reg = <1>; - - hdmi_tx_out: endpoint { - remote-endpoint = <&hdmi_tx_in>; - }; - }; - }; - - hdmi_tx: hdmi-tx@c883a000 { - compatible = "amlogic,meson-gx-dw-hdmi"; - reg = <0x0 0xc883a000 0x0 0x1c>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - /* VPU VENC Input */ - hdmi_tx_venc_port: port@0 { - reg = <0>; - - hdmi_tx_in: endpoint { - remote-endpoint = <&hdmi_tx_out>; - }; - }; - - /* TMDS Output */ - hdmi_tx_tmds_port: port@1 { - reg = <1>; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/amlogic/meson-gxbb-kii-pro.dts b/sys/gnu/dts/arm64/amlogic/meson-gxbb-kii-pro.dts deleted file mode 100644 index 2f1f829450a..00000000000 --- a/sys/gnu/dts/arm64/amlogic/meson-gxbb-kii-pro.dts +++ /dev/null @@ -1,78 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 Mohammad Rasim - */ - -/dts-v1/; - -#include "meson-gxbb-p20x.dtsi" - -#include -#include -#include -/ { - compatible = "videostrong,kii-pro", "amlogic,p201", "amlogic,s905", "amlogic,meson-gxbb"; - model = "Videostrong KII Pro"; - - leds { - compatible = "gpio-leds"; - status { - gpios = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_LOW>; - default-state = "off"; - color = ; - function = LED_FUNCTION_STATUS; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - button-reset { - label = "reset"; - linux,code = ; - gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>; - }; - }; - -}; - - - -&uart_A { - status = "okay"; - pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; - pinctrl-names = "default"; - uart-has-rtscts; - - bluetooth { - compatible = "brcm,bcm4335a0"; - }; -}; - - - -ðmac { - status = "okay"; - pinctrl-0 = <ð_rmii_pins>; - pinctrl-names = "default"; - - phy-handle = <ð_phy0>; - phy-mode = "rmii"; - - mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - eth_phy0: ethernet-phy@0 { - /* IC Plus IP101GR (0x02430c54) */ - reg = <0>; - reset-assert-us = <10000>; - reset-deassert-us = <10000>; - reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/amlogic/meson-gxbb-nanopi-k2.dts b/sys/gnu/dts/arm64/amlogic/meson-gxbb-nanopi-k2.dts deleted file mode 100644 index d6ca684e0e6..00000000000 --- a/sys/gnu/dts/arm64/amlogic/meson-gxbb-nanopi-k2.dts +++ /dev/null @@ -1,375 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 Andreas Färber - */ - -/dts-v1/; - -#include "meson-gxbb.dtsi" -#include - -/ { - compatible = "friendlyarm,nanopi-k2", "amlogic,meson-gxbb"; - model = "FriendlyARM NanoPi K2"; - - aliases { - serial0 = &uart_AO; - ethernet0 = ðmac; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; - - leds { - compatible = "gpio-leds"; - - stat { - label = "nanopi-k2:blue:stat"; - gpios = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_HIGH>; - default-state = "on"; - panic-indicator; - }; - }; - - vdd_5v: regulator-vdd-5v { - compatible = "regulator-fixed"; - regulator-name = "VDD_5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - vddio_ao18: regulator-vddio-ao18 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vddio_ao3v3: regulator-vddio-ao3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vddio_tf: regulator-vddio-tf { - compatible = "regulator-gpio"; - - regulator-name = "VDDIO_TF"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>; - gpios-states = <0>; - - states = <3300000 0>, - <1800000 1>; - - regulator-settling-time-up-us = <100>; - regulator-settling-time-down-us = <5000>; - }; - - wifi_32k: wifi-32k { - compatible = "pwm-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; - clocks = <&wifi_32k>; - clock-names = "ext_clock"; - }; - - vcc1v8: regulator-vcc1v8 { - compatible = "regulator-fixed"; - regulator-name = "VCC1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vcc3v3: regulator-vcc3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; - }; - - /* CVBS is available on CON1 pin 36, disabled by default */ - cvbs-connector { - compatible = "composite-video-connector"; - status = "disabled"; - - port { - cvbs_connector_in: endpoint { - remote-endpoint = <&cvbs_vdac_out>; - }; - }; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; - }; -}; - -&cec_AO { - status = "okay"; - pinctrl-0 = <&ao_cec_pins>; - pinctrl-names = "default"; - hdmi-phandle = <&hdmi_tx>; -}; - -&cvbs_vdac_port { - cvbs_vdac_out: endpoint { - remote-endpoint = <&cvbs_connector_in>; - }; -}; - -ðmac { - status = "okay"; - pinctrl-0 = <ð_rgmii_pins>; - pinctrl-names = "default"; - - phy-handle = <ð_phy0>; - phy-mode = "rgmii"; - - amlogic,tx-delay-ns = <2>; - - mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - eth_phy0: ethernet-phy@0 { - /* Realtek RTL8211F (0x001cc916) */ - reg = <0>; - - reset-assert-us = <10000>; - reset-deassert-us = <30000>; - reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; - - interrupt-parent = <&gpio_intc>; - /* MAC_INTR on GPIOZ_15 */ - interrupts = <29 IRQ_TYPE_LEVEL_LOW>; - }; - }; -}; - -&hdmi_tx { - status = "okay"; - pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; - pinctrl-names = "default"; -}; - -&hdmi_tx_tmds_port { - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; -}; - -&ir { - status = "okay"; - pinctrl-0 = <&remote_input_ao_pins>; - pinctrl-names = "default"; -}; - -&gpio_ao { - gpio-line-names = "UART TX", "UART RX", "Power Control", "Power Key In", - "VCCK En", "CON1 Header Pin31", - "I2S Header Pin6", "IR In", "I2S Header Pin7", - "I2S Header Pin3", "I2S Header Pin4", - "I2S Header Pin5", "HDMI CEC", "SYS LED", - /* GPIO_TEST_N */ - ""; -}; - -&gpio { - gpio-line-names = /* Bank GPIOZ */ - "Eth MDIO", "Eth MDC", "Eth RGMII RX Clk", - "Eth RX DV", "Eth RX D0", "Eth RX D1", "Eth RX D2", - "Eth RX D3", "Eth RGMII TX Clk", "Eth TX En", - "Eth TX D0", "Eth TX D1", "Eth TX D2", "Eth TX D3", - "Eth PHY nRESET", "Eth PHY Intc", - /* Bank GPIOH */ - "HDMI HPD", "HDMI DDC SDA", "HDMI DDC SCL", - "CON1 Header Pin33", - /* Bank BOOT */ - "eMMC D0", "eMMC D1", "eMMC D2", "eMMC D3", "eMMC D4", - "eMMC D5", "eMMC D6", "eMMC D7", "eMMC Clk", - "eMMC Reset", "eMMC CMD", - "", "", "", "", "eMMC DS", - "", "", - /* Bank CARD */ - "SDCard D1", "SDCard D0", "SDCard CLK", "SDCard CMD", - "SDCard D3", "SDCard D2", "SDCard Det", - /* Bank GPIODV */ - "", "", "", "", "", "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", "", "", "", - "I2C A SDA", "I2C A SCK", "I2C B SDA", "I2C B SCK", - "VDDEE Regulator", "VCCK Regulator", - /* Bank GPIOY */ - "CON1 Header Pin7", "CON1 Header Pin11", - "CON1 Header Pin13", "CON1 Header Pin15", - "CON1 Header Pin18", "CON1 Header Pin19", - "CON1 Header Pin22", "CON1 Header Pin21", - "CON1 Header Pin24", "CON1 Header Pin23", - "CON1 Header Pin26", "CON1 Header Pin29", - "CON1 Header Pin32", "CON1 Header Pin8", - "CON1 Header Pin10", "CON1 Header Pin16", - "CON1 Header Pin12", - /* Bank GPIOX */ - "WIFI SDIO D0", "WIFI SDIO D1", "WIFI SDIO D2", - "WIFI SDIO D3", "WIFI SDIO CLK", "WIFI SDIO CMD", - "WIFI Power Enable", "WIFI WAKE HOST", - "Bluetooth PCM DOUT", "Bluetooth PCM DIN", - "Bluetooth PCM SYNC", "Bluetooth PCM CLK", - "Bluetooth UART TX", "Bluetooth UART RX", - "Bluetooth UART CTS", "Bluetooth UART RTS", - "", "", "", "WIFI 32K", "Bluetooth Enable", - "Bluetooth WAKE HOST", "", - /* Bank GPIOCLK */ - "", "CON1 Header Pin35", "", ""; -}; - -&pwm_ef { - status = "okay"; - pinctrl-0 = <&pwm_e_pins>; - pinctrl-names = "default"; - clocks = <&clkc CLKID_FCLK_DIV4>; - clock-names = "clkin0"; -}; - -&saradc { - status = "okay"; - vref-supply = <&vddio_ao18>; -}; - -/* SDIO */ -&sd_emmc_a { - status = "okay"; - pinctrl-0 = <&sdio_pins>, <&sdio_irq_pins>; - pinctrl-1 = <&sdio_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - #address-cells = <1>; - #size-cells = <0>; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <50000000>; - - non-removable; - disable-wp; - - /* WiFi firmware requires power to be kept while in suspend */ - keep-power-in-suspend; - - mmc-pwrseq = <&sdio_pwrseq>; - - vmmc-supply = <&vddio_ao3v3>; - vqmmc-supply = <&vddio_ao18>; - - brcmf: wifi@1 { - compatible = "brcm,bcm4329-fmac"; - reg = <1>; - }; -}; - -/* SD */ -&sd_emmc_b { - status = "okay"; - pinctrl-0 = <&sdcard_pins>; - pinctrl-1 = <&sdcard_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-ddr50; - max-frequency = <100000000>; - disable-wp; - - cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; - - vmmc-supply = <&vddio_ao3v3>; - vqmmc-supply = <&vddio_tf>; -}; - -/* eMMC */ -&sd_emmc_c { - status = "disabled"; - pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - max-frequency = <200000000>; - non-removable; - disable-wp; - cap-mmc-highspeed; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vcc3v3>; - vqmmc-supply = <&vcc1v8>; -}; - -/* DBG_UART */ -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -/* Bluetooth on AP6212 */ -&uart_A { - status = "disabled"; - pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; - pinctrl-names = "default"; -}; - -/* 40-pin CON1 */ -&uart_C { - status = "disabled"; - pinctrl-0 = <&uart_c_pins>; - pinctrl-names = "default"; -}; - -&usb0_phy { - status = "okay"; - phy-supply = <&vdd_5v>; -}; - -&usb1_phy { - status = "okay"; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/amlogic/meson-gxbb-nexbox-a95x.dts b/sys/gnu/dts/arm64/amlogic/meson-gxbb-nexbox-a95x.dts deleted file mode 100644 index 65ec7dea828..00000000000 --- a/sys/gnu/dts/arm64/amlogic/meson-gxbb-nexbox-a95x.dts +++ /dev/null @@ -1,291 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Andreas Färber - * Copyright (c) 2016 BayLibre, Inc. - * Author: Neil Armstrong - */ - -/dts-v1/; - -#include "meson-gxbb.dtsi" -#include -#include - -/ { - compatible = "nexbox,a95x", "amlogic,meson-gxbb"; - model = "NEXBOX A95X"; - - aliases { - serial0 = &uart_AO; - ethernet0 = ðmac; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x40000000>; - }; - - leds { - compatible = "gpio-leds"; - blue { - label = "a95x:system-status"; - gpios = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <100>; - - button@0 { - label = "reset"; - linux,code = ; - gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_LOW>; - }; - }; - - usb_pwr: regulator-usb-pwrs { - compatible = "regulator-fixed"; - - regulator-name = "USB_PWR"; - - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - gpio = <&gpio GPIODV_24 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vddio_card: gpio-regulator { - compatible = "regulator-gpio"; - - regulator-name = "VDDIO_CARD"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>; - gpios-states = <1>; - - /* Based on P200 schematics, signal CARD_1.8V/3.3V_CTR */ - states = <1800000 0>, - <3300000 1>; - }; - - vddio_boot: regulator-vddio_boot { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_BOOT"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vddao_3v3: regulator-vddao_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vcc_3v3: regulator-vcc_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; - }; - - wifi32k: wifi32k { - compatible = "pwm-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; - clocks = <&wifi32k>; - clock-names = "ext_clock"; - }; - - cvbs-connector { - compatible = "composite-video-connector"; - - port { - cvbs_connector_in: endpoint { - remote-endpoint = <&cvbs_vdac_out>; - }; - }; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; - }; -}; - -&cvbs_vdac_port { - cvbs_vdac_out: endpoint { - remote-endpoint = <&cvbs_connector_in>; - }; -}; - -&cec_AO { - status = "okay"; - pinctrl-0 = <&ao_cec_pins>; - pinctrl-names = "default"; - hdmi-phandle = <&hdmi_tx>; -}; - -ðmac { - status = "okay"; - pinctrl-0 = <ð_rmii_pins>; - pinctrl-names = "default"; - - phy-handle = <ð_phy0>; - phy-mode = "rmii"; - - mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - eth_phy0: ethernet-phy@0 { - /* IC Plus IP101GR (0x02430c54) */ - reg = <0>; - - reset-assert-us = <10000>; - reset-deassert-us = <10000>; - reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&hdmi_tx { - status = "okay"; - pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; - pinctrl-names = "default"; -}; - -&hdmi_tx_tmds_port { - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; -}; - -&ir { - status = "okay"; - pinctrl-0 = <&remote_input_ao_pins>; - pinctrl-names = "default"; -}; - -&pwm_ef { - status = "okay"; - pinctrl-0 = <&pwm_e_pins>; - pinctrl-names = "default"; - clocks = <&clkc CLKID_FCLK_DIV4>; - clock-names = "clkin0"; -}; - -/* Wireless SDIO Module */ -&sd_emmc_a { - status = "okay"; - pinctrl-0 = <&sdio_pins>; - pinctrl-1 = <&sdio_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - #address-cells = <1>; - #size-cells = <0>; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <100000000>; - - non-removable; - disable-wp; - - /* WiFi firmware requires power to be kept while in suspend */ - keep-power-in-suspend; - - mmc-pwrseq = <&sdio_pwrseq>; - - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddio_boot>; -}; - -/* SD card */ -&sd_emmc_b { - status = "okay"; - pinctrl-0 = <&sdcard_pins>; - pinctrl-1 = <&sdcard_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <50000000>; - disable-wp; - - cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; - - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddio_card>; -}; - -/* eMMC */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - max-frequency = <200000000>; - non-removable; - disable-wp; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&vddio_boot>; -}; - -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -&usb0_phy { - status = "okay"; - phy-supply = <&usb_pwr>; -}; - -&usb1_phy { - status = "okay"; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/amlogic/meson-gxbb-odroidc2.dts b/sys/gnu/dts/arm64/amlogic/meson-gxbb-odroidc2.dts deleted file mode 100644 index 6ded279c40c..00000000000 --- a/sys/gnu/dts/arm64/amlogic/meson-gxbb-odroidc2.dts +++ /dev/null @@ -1,377 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Andreas Färber - * Copyright (c) 2016 BayLibre, Inc. - * Author: Kevin Hilman - */ - -/dts-v1/; - -#include "meson-gxbb.dtsi" -#include - -/ { - compatible = "hardkernel,odroid-c2", "amlogic,meson-gxbb"; - model = "Hardkernel ODROID-C2"; - - aliases { - serial0 = &uart_AO; - ethernet0 = ðmac; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; - - usb_otg_pwr: regulator-usb-pwrs { - compatible = "regulator-fixed"; - - regulator-name = "USB_OTG_PWR"; - - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - /* - * signal name from schematics: PWREN - */ - gpio = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>; - enable-active-high; - /* - * signal name from schematics: USB_POWER - */ - vin-supply = <&p5v0>; - }; - - leds { - compatible = "gpio-leds"; - blue { - label = "c2:blue:alive"; - gpios = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - }; - - p5v0: regulator-p5v0 { - compatible = "regulator-fixed"; - - regulator-name = "P5V0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - hdmi_p5v0: regulator-hdmi_p5v0 { - compatible = "regulator-fixed"; - regulator-name = "HDMI_P5V0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - /* AP2331SA-7 */ - vin-supply = <&p5v0>; - }; - - tflash_vdd: regulator-tflash_vdd { - compatible = "regulator-fixed"; - - regulator-name = "TFLASH_VDD"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - /* - * signal name from schematics: TFLASH_VDD_EN - */ - gpio = <&gpio GPIOY_12 GPIO_ACTIVE_HIGH>; - enable-active-high; - /* U16 RT9179GB */ - vin-supply = <&vddio_ao3v3>; - }; - - tf_io: gpio-regulator-tf_io { - compatible = "regulator-gpio"; - - regulator-name = "TF_IO"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - /* - * signal name from schematics: TF_3V3N_1V8_EN - */ - gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>; - gpios-states = <0>; - - states = <3300000 0>, - <1800000 1>; - /* U12/U13 RT9179GB */ - vin-supply = <&vddio_ao3v3>; - }; - - vcc1v8: regulator-vcc1v8 { - compatible = "regulator-fixed"; - regulator-name = "VCC1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - /* U18 RT9179GB */ - vin-supply = <&vddio_ao3v3>; - }; - - vcc3v3: regulator-vcc3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vddio_ao1v8: regulator-vddio-ao1v8 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - /* U17 RT9179GB */ - vin-supply = <&p5v0>; - }; - - vddio_ao3v3: regulator-vddio-ao3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - /* U11 MP2161GJ-C499 */ - vin-supply = <&p5v0>; - }; - - ddr3_1v5: regulator-ddr3_1v5 { - compatible = "regulator-fixed"; - regulator-name = "DDR3_1V5"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - /* U15 MP2161GJ-C499 */ - vin-supply = <&p5v0>; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; - }; -}; - -&cec_AO { - status = "okay"; - pinctrl-0 = <&ao_cec_pins>; - pinctrl-names = "default"; - hdmi-phandle = <&hdmi_tx>; -}; - -ðmac { - status = "okay"; - pinctrl-0 = <ð_rgmii_pins>; - pinctrl-names = "default"; - phy-handle = <ð_phy0>; - phy-mode = "rgmii"; - - amlogic,tx-delay-ns = <2>; - - mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - eth_phy0: ethernet-phy@0 { - /* Realtek RTL8211F (0x001cc916) */ - reg = <0>; - - reset-assert-us = <10000>; - reset-deassert-us = <30000>; - reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; - - interrupt-parent = <&gpio_intc>; - /* MAC_INTR on GPIOZ_15 */ - interrupts = <29 IRQ_TYPE_LEVEL_LOW>; - }; - }; -}; - -&gpio_ao { - /* - * WARNING: The USB Hub on the Odroid-C2 needs a reset signal - * to be turned high in order to be detected by the USB Controller - * This signal should be handled by a USB specific power sequence - * in order to reset the Hub when USB bus is powered down. - */ - usb-hub { - gpio-hog; - gpios = ; - output-high; - line-name = "usb-hub-reset"; - }; -}; - -&hdmi_tx { - status = "okay"; - pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; - pinctrl-names = "default"; - hdmi-supply = <&hdmi_p5v0>; -}; - -&hdmi_tx_tmds_port { - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; -}; - -&i2c_A { - status = "okay"; - pinctrl-0 = <&i2c_a_pins>; - pinctrl-names = "default"; -}; - -&ir { - status = "okay"; - pinctrl-0 = <&remote_input_ao_pins>; - pinctrl-names = "default"; -}; - -&gpio_ao { - gpio-line-names = "UART TX", "UART RX", "VCCK En", "TF 3V3/1V8 En", - "USB HUB nRESET", "USB OTG Power En", - "J7 Header Pin2", "IR In", "J7 Header Pin4", - "J7 Header Pin6", "J7 Header Pin5", "J7 Header Pin7", - "HDMI CEC", "SYS LED", - /* GPIO_TEST_N */ - ""; -}; - -&gpio { - gpio-line-names = /* Bank GPIOZ */ - "Eth MDIO", "Eth MDC", "Eth RGMII RX Clk", - "Eth RX DV", "Eth RX D0", "Eth RX D1", "Eth RX D2", - "Eth RX D3", "Eth RGMII TX Clk", "Eth TX En", - "Eth TX D0", "Eth TX D1", "Eth TX D2", "Eth TX D3", - "Eth PHY nRESET", "Eth PHY Intc", - /* Bank GPIOH */ - "HDMI HPD", "HDMI DDC SDA", "HDMI DDC SCL", "", - /* Bank BOOT */ - "eMMC D0", "eMMC D1", "eMMC D2", "eMMC D3", "eMMC D4", - "eMMC D5", "eMMC D6", "eMMC D7", "eMMC Clk", - "eMMC Reset", "eMMC CMD", - "", "", "", "", "", "", "", - /* Bank CARD */ - "SDCard D1", "SDCard D0", "SDCard CLK", "SDCard CMD", - "SDCard D3", "SDCard D2", "SDCard Det", - /* Bank GPIODV */ - "", "", "", "", "", "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", "", "", "", - "I2C A SDA", "I2C A SCK", "I2C B SDA", "I2C B SCK", - "PWM D", "PWM B", - /* Bank GPIOY */ - "Revision Bit0", "Revision Bit1", "", - "J2 Header Pin35", "", "", "", "J2 Header Pin36", - "J2 Header Pin31", "", "", "", "TF VDD En", - "J2 Header Pin32", "J2 Header Pin26", "", "", - /* Bank GPIOX */ - "J2 Header Pin29", "J2 Header Pin24", - "J2 Header Pin23", "J2 Header Pin22", - "J2 Header Pin21", "J2 Header Pin18", - "J2 Header Pin33", "J2 Header Pin19", - "J2 Header Pin16", "J2 Header Pin15", - "J2 Header Pin12", "J2 Header Pin13", - "J2 Header Pin8", "J2 Header Pin10", - "", "", "", "", "", - "J2 Header Pin11", "", "J2 Header Pin7", "", - /* Bank GPIOCLK */ - "", "", "", ""; -}; - -&saradc { - status = "okay"; - vref-supply = <&vcc1v8>; -}; - -&scpi_clocks { - status = "disabled"; -}; - -/* SD */ -&sd_emmc_b { - status = "okay"; - pinctrl-0 = <&sdcard_pins>; - pinctrl-1 = <&sdcard_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-ddr50; - max-frequency = <100000000>; - disable-wp; - - cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; - - vmmc-supply = <&tflash_vdd>; - vqmmc-supply = <&tf_io>; -}; - -/* eMMC */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - max-frequency = <200000000>; - non-removable; - disable-wp; - cap-mmc-highspeed; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vcc3v3>; - vqmmc-supply = <&vcc1v8>; -}; - -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -&usb0_phy { - status = "disabled"; - phy-supply = <&usb_otg_pwr>; -}; - -&usb1_phy { - status = "okay"; - phy-supply = <&usb_otg_pwr>; -}; - -&usb0 { - status = "disabled"; -}; - -&usb1 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/amlogic/meson-gxbb-p200.dts b/sys/gnu/dts/arm64/amlogic/meson-gxbb-p200.dts deleted file mode 100644 index 3c93d1898b4..00000000000 --- a/sys/gnu/dts/arm64/amlogic/meson-gxbb-p200.dts +++ /dev/null @@ -1,100 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Andreas Färber - * Copyright (c) 2016 BayLibre, Inc. - * Author: Kevin Hilman - */ - -/dts-v1/; - -#include "meson-gxbb-p20x.dtsi" -#include - -/ { - compatible = "amlogic,p200", "amlogic,meson-gxbb"; - model = "Amlogic Meson GXBB P200 Development Board"; - - avdd18_usb_adc: regulator-avdd18_usb_adc { - compatible = "regulator-fixed"; - regulator-name = "AVDD18_USB_ADC"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - adc_keys { - compatible = "adc-keys"; - io-channels = <&saradc 0>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1800000>; - - button-home { - label = "Home"; - linux,code = ; - press-threshold-microvolt = <900000>; /* 50% */ - }; - - button-esc { - label = "Esc"; - linux,code = ; - press-threshold-microvolt = <684000>; /* 38% */ - }; - - button-up { - label = "Volume Up"; - linux,code = ; - press-threshold-microvolt = <468000>; /* 26% */ - }; - - button-down { - label = "Volume Down"; - linux,code = ; - press-threshold-microvolt = <252000>; /* 14% */ - }; - - button-menu { - label = "Menu"; - linux,code = ; - press-threshold-microvolt = <0>; /* 0% */ - }; - }; -}; - -ðmac { - status = "okay"; - pinctrl-0 = <ð_rgmii_pins>; - pinctrl-names = "default"; - phy-handle = <ð_phy0>; - phy-mode = "rgmii"; - - amlogic,tx-delay-ns = <2>; - - mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - eth_phy0: ethernet-phy@3 { - /* Micrel KSZ9031 (0x00221620) */ - reg = <3>; - - reset-assert-us = <10000>; - reset-deassert-us = <30000>; - reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; - - interrupt-parent = <&gpio_intc>; - /* MAC_INTR on GPIOZ_15 */ - interrupts = <29 IRQ_TYPE_LEVEL_LOW>; - }; - }; -}; - -&i2c_B { - status = "okay"; - pinctrl-0 = <&i2c_b_pins>; - pinctrl-names = "default"; -}; - -&saradc { - status = "okay"; - vref-supply = <&avdd18_usb_adc>; -}; diff --git a/sys/gnu/dts/arm64/amlogic/meson-gxbb-p201.dts b/sys/gnu/dts/arm64/amlogic/meson-gxbb-p201.dts deleted file mode 100644 index 150a82f3b2d..00000000000 --- a/sys/gnu/dts/arm64/amlogic/meson-gxbb-p201.dts +++ /dev/null @@ -1,26 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Andreas Färber - * Copyright (c) 2016 BayLibre, Inc. - * Author: Kevin Hilman - */ - -/dts-v1/; - -#include "meson-gxbb-p20x.dtsi" - -/ { - compatible = "amlogic,p201", "amlogic,meson-gxbb"; - model = "Amlogic Meson GXBB P201 Development Board"; -}; - -ðmac { - status = "okay"; - pinctrl-0 = <ð_rmii_pins>; - pinctrl-names = "default"; - phy-mode = "rmii"; - - snps,reset-gpio = <&gpio GPIOZ_14 0>; - snps,reset-delays-us = <0>, <10000>, <1000000>; - snps,reset-active-low; -}; diff --git a/sys/gnu/dts/arm64/amlogic/meson-gxbb-p20x.dtsi b/sys/gnu/dts/arm64/amlogic/meson-gxbb-p20x.dtsi deleted file mode 100644 index e803a466fe4..00000000000 --- a/sys/gnu/dts/arm64/amlogic/meson-gxbb-p20x.dtsi +++ /dev/null @@ -1,250 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Andreas Färber - * Copyright (c) 2016 BayLibre, Inc. - * Author: Kevin Hilman - */ - -#include "meson-gxbb.dtsi" - -/ { - aliases { - serial0 = &uart_AO; - ethernet0 = ðmac; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x40000000>; - }; - - usb_pwr: regulator-usb-pwrs { - compatible = "regulator-fixed"; - - regulator-name = "USB_PWR"; - - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - /* signal name in schematic: USB_PWR_EN */ - gpio = <&gpio GPIODV_24 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vddio_card: gpio-regulator { - compatible = "regulator-gpio"; - - regulator-name = "VDDIO_CARD"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>; - gpios-states = <1>; - - /* Based on P200 schematics, signal CARD_1.8V/3.3V_CTR */ - states = <1800000 0>, - <3300000 1>; - - regulator-settling-time-up-us = <10000>; - regulator-settling-time-down-us = <150000>; - }; - - vddio_boot: regulator-vddio_boot { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_BOOT"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vddao_3v3: regulator-vddao_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vcc_3v3: regulator-vcc_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; - }; - - wifi32k: wifi32k { - compatible = "pwm-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; - clocks = <&wifi32k>; - clock-names = "ext_clock"; - }; - - cvbs_connector: cvbs-connector { - compatible = "composite-video-connector"; - - port { - cvbs_connector_in: endpoint { - remote-endpoint = <&cvbs_vdac_out>; - }; - }; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; - }; -}; - -&cec_AO { - status = "okay"; - pinctrl-0 = <&ao_cec_pins>; - pinctrl-names = "default"; - hdmi-phandle = <&hdmi_tx>; -}; - -&cvbs_vdac_port { - cvbs_vdac_out: endpoint { - remote-endpoint = <&cvbs_connector_in>; - }; -}; - -&hdmi_tx { - status = "okay"; - pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; - pinctrl-names = "default"; -}; - -&hdmi_tx_tmds_port { - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; -}; - -&ir { - status = "okay"; - pinctrl-0 = <&remote_input_ao_pins>; - pinctrl-names = "default"; -}; - -&pwm_ef { - status = "okay"; - pinctrl-0 = <&pwm_e_pins>; - pinctrl-names = "default"; - clocks = <&clkc CLKID_FCLK_DIV4>; - clock-names = "clkin0"; -}; - -/* Wireless SDIO Module */ -&sd_emmc_a { - status = "okay"; - pinctrl-0 = <&sdio_pins>; - pinctrl-1 = <&sdio_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - #address-cells = <1>; - #size-cells = <0>; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <50000000>; - - non-removable; - disable-wp; - - /* WiFi firmware requires power to be kept while in suspend */ - keep-power-in-suspend; - - mmc-pwrseq = <&sdio_pwrseq>; - - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddio_boot>; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - }; -}; - -/* SD card */ -&sd_emmc_b { - status = "okay"; - pinctrl-0 = <&sdcard_pins>; - pinctrl-1 = <&sdcard_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - max-frequency = <100000000>; - disable-wp; - - cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; - - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddio_card>; -}; - -/* eMMC */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - max-frequency = <200000000>; - non-removable; - disable-wp; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&vddio_boot>; -}; - -/* This UART is brought out to the DB9 connector */ -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -&usb0_phy { - status = "okay"; - phy-supply = <&usb_pwr>; -}; - -&usb1_phy { - status = "okay"; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/amlogic/meson-gxbb-vega-s95-meta.dts b/sys/gnu/dts/arm64/amlogic/meson-gxbb-vega-s95-meta.dts deleted file mode 100644 index c928adf8538..00000000000 --- a/sys/gnu/dts/arm64/amlogic/meson-gxbb-vega-s95-meta.dts +++ /dev/null @@ -1,18 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Andreas Färber - */ - -/dts-v1/; - -#include "meson-gxbb-vega-s95.dtsi" - -/ { - compatible = "tronsmart,vega-s95-meta", "tronsmart,vega-s95", "amlogic,meson-gxbb"; - model = "Tronsmart Vega S95 Meta"; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; -}; diff --git a/sys/gnu/dts/arm64/amlogic/meson-gxbb-vega-s95-pro.dts b/sys/gnu/dts/arm64/amlogic/meson-gxbb-vega-s95-pro.dts deleted file mode 100644 index e81e1d68b5f..00000000000 --- a/sys/gnu/dts/arm64/amlogic/meson-gxbb-vega-s95-pro.dts +++ /dev/null @@ -1,18 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Andreas Färber - */ - -/dts-v1/; - -#include "meson-gxbb-vega-s95.dtsi" - -/ { - compatible = "tronsmart,vega-s95-pro", "tronsmart,vega-s95", "amlogic,meson-gxbb"; - model = "Tronsmart Vega S95 Pro"; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x40000000>; - }; -}; diff --git a/sys/gnu/dts/arm64/amlogic/meson-gxbb-vega-s95-telos.dts b/sys/gnu/dts/arm64/amlogic/meson-gxbb-vega-s95-telos.dts deleted file mode 100644 index a8fca0c6903..00000000000 --- a/sys/gnu/dts/arm64/amlogic/meson-gxbb-vega-s95-telos.dts +++ /dev/null @@ -1,18 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Andreas Färber - */ - -/dts-v1/; - -#include "meson-gxbb-vega-s95.dtsi" - -/ { - compatible = "tronsmart,vega-s95-telos", "tronsmart,vega-s95", "amlogic,meson-gxbb"; - model = "Tronsmart Vega S95 Telos"; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; -}; diff --git a/sys/gnu/dts/arm64/amlogic/meson-gxbb-vega-s95.dtsi b/sys/gnu/dts/arm64/amlogic/meson-gxbb-vega-s95.dtsi deleted file mode 100644 index 5eab3dfdbd5..00000000000 --- a/sys/gnu/dts/arm64/amlogic/meson-gxbb-vega-s95.dtsi +++ /dev/null @@ -1,273 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Andreas Färber - */ - -#include "meson-gxbb.dtsi" - -/ { - compatible = "tronsmart,vega-s95", "amlogic,meson-gxbb"; - - aliases { - serial0 = &uart_AO; - ethernet0 = ðmac; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - blue { - label = "vega-s95:blue:on"; - gpios = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_HIGH>; - default-state = "on"; - panic-indicator; - }; - }; - - usb_pwr: regulator-usb-pwrs { - compatible = "regulator-fixed"; - - regulator-name = "USB_PWR"; - - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - gpio = <&gpio GPIODV_24 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vddio_boot: regulator-vddio_boot { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_BOOT"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vddao_3v3: regulator-vddao_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vddio_ao18: regulator-vddio_ao18 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vcc_3v3: regulator-vcc_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; - }; - - wifi32k: wifi32k { - compatible = "pwm-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; - clocks = <&wifi32k>; - clock-names = "ext_clock"; - }; -}; - -&cec_AO { - status = "okay"; - pinctrl-0 = <&ao_cec_pins>; - pinctrl-names = "default"; - hdmi-phandle = <&hdmi_tx>; -}; - -ðmac { - status = "okay"; - pinctrl-0 = <ð_rgmii_pins>; - pinctrl-names = "default"; - - phy-handle = <ð_phy0>; - phy-mode = "rgmii"; - - amlogic,tx-delay-ns = <2>; - - mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - eth_phy0: ethernet-phy@0 { - /* Realtek RTL8211F (0x001cc916) */ - reg = <0>; - - reset-assert-us = <10000>; - reset-deassert-us = <30000>; - reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; - - interrupt-parent = <&gpio_intc>; - /* MAC_INTR on GPIOZ_15 */ - interrupts = <29 IRQ_TYPE_LEVEL_LOW>; - }; - }; -}; - -&hdmi_tx { - status = "okay"; - pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; - pinctrl-names = "default"; -}; - -&hdmi_tx_tmds_port { - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; -}; - -&ir { - status = "okay"; - pinctrl-0 = <&remote_input_ao_pins>; - pinctrl-names = "default"; - linux,rc-map-name = "rc-vega-s9x"; -}; - -&pwm_ef { - status = "okay"; - pinctrl-0 = <&pwm_e_pins>; - pinctrl-names = "default"; - clocks = <&clkc CLKID_FCLK_DIV4>; - clock-names = "clkin0"; -}; - -&saradc { - status = "okay"; - vref-supply = <&vddio_ao18>; -}; - -/* Wireless SDIO Module */ -&sd_emmc_a { - status = "okay"; - pinctrl-0 = <&sdio_pins>; - pinctrl-1 = <&sdio_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - #address-cells = <1>; - #size-cells = <0>; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <50000000>; - - non-removable; - disable-wp; - - /* WiFi firmware requires power to be kept while in suspend */ - keep-power-in-suspend; - - mmc-pwrseq = <&sdio_pwrseq>; - - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddio_boot>; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - }; -}; - -/* SD card */ -&sd_emmc_b { - status = "okay"; - pinctrl-0 = <&sdcard_pins>; - pinctrl-1 = <&sdcard_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <50000000>; - disable-wp; - - cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; - - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vcc_3v3>; -}; - -/* eMMC */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - max-frequency = <200000000>; - non-removable; - disable-wp; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&vddio_boot>; -}; - -/* This is connected to the Bluetooth module: */ -&uart_A { - status = "okay"; - pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; - pinctrl-names = "default"; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - shutdown-gpios = <&gpio GPIOX_20 GPIO_ACTIVE_HIGH>; - }; -}; - -/* This UART is brought out to the DB9 connector */ -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -&usb0_phy { - status = "okay"; - phy-supply = <&usb_pwr>; -}; - -&usb1_phy { - status = "okay"; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/amlogic/meson-gxbb-wetek-hub.dts b/sys/gnu/dts/arm64/amlogic/meson-gxbb-wetek-hub.dts deleted file mode 100644 index 83b985bb015..00000000000 --- a/sys/gnu/dts/arm64/amlogic/meson-gxbb-wetek-hub.dts +++ /dev/null @@ -1,18 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 BayLibre, Inc. - * Author: Neil Armstrong - */ - -/dts-v1/; - -#include "meson-gxbb-wetek.dtsi" - -/ { - compatible = "wetek,hub", "amlogic,meson-gxbb"; - model = "WeTek Hub"; -}; - -&ir { - linux,rc-map-name = "rc-wetek-hub"; -}; diff --git a/sys/gnu/dts/arm64/amlogic/meson-gxbb-wetek-play2.dts b/sys/gnu/dts/arm64/amlogic/meson-gxbb-wetek-play2.dts deleted file mode 100644 index 1d32d1f6d03..00000000000 --- a/sys/gnu/dts/arm64/amlogic/meson-gxbb-wetek-play2.dts +++ /dev/null @@ -1,60 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 BayLibre, Inc. - * Author: Neil Armstrong - */ - -/dts-v1/; - -#include "meson-gxbb-wetek.dtsi" -#include - -/ { - compatible = "wetek,play2", "amlogic,meson-gxbb"; - model = "WeTek Play 2"; - - leds { - wifi { - label = "wetek-play:wifi-status"; - gpios = <&gpio GPIODV_26 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - ethernet { - label = "wetek-play:ethernet-status"; - gpios = <&gpio GPIODV_27 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <100>; - - button@0 { - label = "reset"; - linux,code = ; - gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&i2c_A { - status = "okay"; - pinctrl-0 = <&i2c_a_pins>; - pinctrl-names = "default"; -}; - -&usb1_phy { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; - -&ir { - linux,rc-map-name = "rc-wetek-play2"; -}; diff --git a/sys/gnu/dts/arm64/amlogic/meson-gxbb-wetek.dtsi b/sys/gnu/dts/arm64/amlogic/meson-gxbb-wetek.dtsi deleted file mode 100644 index dee51cf9522..00000000000 --- a/sys/gnu/dts/arm64/amlogic/meson-gxbb-wetek.dtsi +++ /dev/null @@ -1,282 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Andreas Färber - * Copyright (c) 2016 BayLibre, Inc. - * Author: Kevin Hilman - */ - -#include "meson-gxbb.dtsi" - -/ { - aliases { - serial0 = &uart_AO; - ethernet0 = ðmac; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x40000000>; - }; - - leds { - compatible = "gpio-leds"; - - system { - label = "wetek-play:system-status"; - gpios = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_HIGH>; - default-state = "on"; - panic-indicator; - }; - }; - - usb_pwr: regulator-usb-pwrs { - compatible = "regulator-fixed"; - - regulator-name = "USB_PWR"; - - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - gpio = <&gpio GPIODV_24 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vddio_boot: regulator-vddio_boot { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_BOOT"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vddao_3v3: regulator-vddao_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vddio_ao18: regulator-vddio_ao18 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vcc_3v3: regulator-vcc_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; - }; - - wifi32k: wifi32k { - compatible = "pwm-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; - clocks = <&wifi32k>; - clock-names = "ext_clock"; - }; - - cvbs-connector { - compatible = "composite-video-connector"; - - port { - cvbs_connector_in: endpoint { - remote-endpoint = <&cvbs_vdac_out>; - }; - }; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; - }; -}; - -&cec_AO { - status = "okay"; - pinctrl-0 = <&ao_cec_pins>; - pinctrl-names = "default"; - hdmi-phandle = <&hdmi_tx>; -}; - -&cvbs_vdac_port { - cvbs_vdac_out: endpoint { - remote-endpoint = <&cvbs_connector_in>; - }; -}; - -ðmac { - status = "okay"; - pinctrl-0 = <ð_rgmii_pins>; - pinctrl-names = "default"; - - phy-handle = <ð_phy0>; - phy-mode = "rgmii"; - - amlogic,tx-delay-ns = <2>; - - mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - eth_phy0: ethernet-phy@0 { - /* Realtek RTL8211F (0x001cc916) */ - reg = <0>; - - reset-assert-us = <10000>; - reset-deassert-us = <30000>; - reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&hdmi_tx { - status = "okay"; - pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; - pinctrl-names = "default"; -}; - -&hdmi_tx_tmds_port { - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; -}; - -&ir { - status = "okay"; - pinctrl-0 = <&remote_input_ao_pins>; - pinctrl-names = "default"; -}; - -&pwm_ef { - status = "okay"; - pinctrl-0 = <&pwm_e_pins>; - pinctrl-names = "default"; - clocks = <&clkc CLKID_FCLK_DIV4>; - clock-names = "clkin0"; -}; - -&saradc { - status = "okay"; - vref-supply = <&vddio_ao18>; -}; - -/* Wireless SDIO Module */ -&sd_emmc_a { - status = "okay"; - pinctrl-0 = <&sdio_pins>; - pinctrl-1 = <&sdio_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - #address-cells = <1>; - #size-cells = <0>; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <50000000>; - - non-removable; - disable-wp; - - /* WiFi firmware requires power to be kept while in suspend */ - keep-power-in-suspend; - - mmc-pwrseq = <&sdio_pwrseq>; - - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddio_boot>; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - }; -}; - -/* SD card */ -&sd_emmc_b { - status = "okay"; - pinctrl-0 = <&sdcard_pins>; - pinctrl-1 = <&sdcard_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <50000000>; - disable-wp; - - cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; - - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vcc_3v3>; -}; - -/* eMMC */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - max-frequency = <200000000>; - non-removable; - disable-wp; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&vddio_boot>; -}; - -/* This is connected to the Bluetooth module: */ -&uart_A { - status = "okay"; - pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; - pinctrl-names = "default"; - uart-has-rtscts; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - shutdown-gpios = <&gpio GPIOX_20 GPIO_ACTIVE_HIGH>; - }; -}; - -/* This UART is brought out to the DB9 connector */ -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -&usb0_phy { - status = "okay"; - phy-supply = <&usb_pwr>; -}; - -&usb0 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/amlogic/meson-gxbb.dtsi b/sys/gnu/dts/arm64/amlogic/meson-gxbb.dtsi deleted file mode 100644 index 0cb40326b0d..00000000000 --- a/sys/gnu/dts/arm64/amlogic/meson-gxbb.dtsi +++ /dev/null @@ -1,858 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Andreas Färber - */ - -#include "meson-gx.dtsi" -#include -#include -#include -#include -#include - -/ { - compatible = "amlogic,meson-gxbb"; - - soc { - usb0_phy: phy@c0000000 { - compatible = "amlogic,meson-gxbb-usb2-phy"; - #phy-cells = <0>; - reg = <0x0 0xc0000000 0x0 0x20>; - resets = <&reset RESET_USB_OTG>; - clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>; - clock-names = "usb_general", "usb"; - status = "disabled"; - }; - - usb1_phy: phy@c0000020 { - compatible = "amlogic,meson-gxbb-usb2-phy"; - #phy-cells = <0>; - reg = <0x0 0xc0000020 0x0 0x20>; - resets = <&reset RESET_USB_OTG>; - clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>; - clock-names = "usb_general", "usb"; - status = "disabled"; - }; - - usb0: usb@c9000000 { - compatible = "amlogic,meson-gxbb-usb", "snps,dwc2"; - reg = <0x0 0xc9000000 0x0 0x40000>; - interrupts = ; - clocks = <&clkc CLKID_USB0_DDR_BRIDGE>; - clock-names = "otg"; - phys = <&usb0_phy>; - phy-names = "usb2-phy"; - dr_mode = "host"; - status = "disabled"; - }; - - usb1: usb@c9100000 { - compatible = "amlogic,meson-gxbb-usb", "snps,dwc2"; - reg = <0x0 0xc9100000 0x0 0x40000>; - interrupts = ; - clocks = <&clkc CLKID_USB1_DDR_BRIDGE>; - clock-names = "otg"; - phys = <&usb1_phy>; - phy-names = "usb2-phy"; - dr_mode = "host"; - status = "disabled"; - }; - }; -}; - -&aobus { - pinctrl_aobus: pinctrl@14 { - compatible = "amlogic,meson-gxbb-aobus-pinctrl"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - gpio_ao: bank@14 { - reg = <0x0 0x00014 0x0 0x8>, - <0x0 0x0002c 0x0 0x4>, - <0x0 0x00024 0x0 0x8>; - reg-names = "mux", "pull", "gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl_aobus 0 0 14>; - }; - - uart_ao_a_pins: uart_ao_a { - mux { - groups = "uart_tx_ao_a", "uart_rx_ao_a"; - function = "uart_ao"; - bias-disable; - }; - }; - - uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts { - mux { - groups = "uart_cts_ao_a", - "uart_rts_ao_a"; - function = "uart_ao"; - bias-disable; - }; - }; - - uart_ao_b_pins: uart_ao_b { - mux { - groups = "uart_tx_ao_b", "uart_rx_ao_b"; - function = "uart_ao_b"; - bias-disable; - }; - }; - - uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts { - mux { - groups = "uart_cts_ao_b", - "uart_rts_ao_b"; - function = "uart_ao_b"; - bias-disable; - }; - }; - - remote_input_ao_pins: remote_input_ao { - mux { - groups = "remote_input_ao"; - function = "remote_input_ao"; - bias-disable; - }; - }; - - i2c_ao_pins: i2c_ao { - mux { - groups = "i2c_sck_ao", - "i2c_sda_ao"; - function = "i2c_ao"; - bias-disable; - }; - }; - - pwm_ao_a_3_pins: pwm_ao_a_3 { - mux { - groups = "pwm_ao_a_3"; - function = "pwm_ao_a_3"; - bias-disable; - }; - }; - - pwm_ao_a_6_pins: pwm_ao_a_6 { - mux { - groups = "pwm_ao_a_6"; - function = "pwm_ao_a_6"; - bias-disable; - }; - }; - - pwm_ao_a_12_pins: pwm_ao_a_12 { - mux { - groups = "pwm_ao_a_12"; - function = "pwm_ao_a_12"; - bias-disable; - }; - }; - - pwm_ao_b_pins: pwm_ao_b { - mux { - groups = "pwm_ao_b"; - function = "pwm_ao_b"; - bias-disable; - }; - }; - - i2s_am_clk_pins: i2s_am_clk { - mux { - groups = "i2s_am_clk"; - function = "i2s_out_ao"; - bias-disable; - }; - }; - - i2s_out_ao_clk_pins: i2s_out_ao_clk { - mux { - groups = "i2s_out_ao_clk"; - function = "i2s_out_ao"; - bias-disable; - }; - }; - - i2s_out_lr_clk_pins: i2s_out_lr_clk { - mux { - groups = "i2s_out_lr_clk"; - function = "i2s_out_ao"; - bias-disable; - }; - }; - - i2s_out_ch01_ao_pins: i2s_out_ch01_ao { - mux { - groups = "i2s_out_ch01_ao"; - function = "i2s_out_ao"; - bias-disable; - }; - }; - - i2s_out_ch23_ao_pins: i2s_out_ch23_ao { - mux { - groups = "i2s_out_ch23_ao"; - function = "i2s_out_ao"; - bias-disable; - }; - }; - - i2s_out_ch45_ao_pins: i2s_out_ch45_ao { - mux { - groups = "i2s_out_ch45_ao"; - function = "i2s_out_ao"; - bias-disable; - }; - }; - - spdif_out_ao_6_pins: spdif_out_ao_6 { - mux { - groups = "spdif_out_ao_6"; - function = "spdif_out_ao"; - }; - }; - - spdif_out_ao_13_pins: spdif_out_ao_13 { - mux { - groups = "spdif_out_ao_13"; - function = "spdif_out_ao"; - bias-disable; - }; - }; - - ao_cec_pins: ao_cec { - mux { - groups = "ao_cec"; - function = "cec_ao"; - bias-disable; - }; - }; - - ee_cec_pins: ee_cec { - mux { - groups = "ee_cec"; - function = "cec_ao"; - bias-disable; - }; - }; - }; -}; - -&apb { - mali: gpu@c0000 { - compatible = "amlogic,meson-gxbb-mali", "arm,mali-450"; - reg = <0x0 0xc0000 0x0 0x40000>; - interrupts = , - , - , - , - , - , - , - , - , - ; - interrupt-names = "gp", "gpmmu", "pp", "pmu", - "pp0", "ppmmu0", "pp1", "ppmmu1", - "pp2", "ppmmu2"; - clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>; - clock-names = "bus", "core"; - - /* - * Mali clocking is provided by two identical clock paths - * MALI_0 and MALI_1 muxed to a single clock by a glitch - * free mux to safely change frequency while running. - */ - assigned-clocks = <&clkc CLKID_GP0_PLL>, - <&clkc CLKID_MALI_0_SEL>, - <&clkc CLKID_MALI_0>, - <&clkc CLKID_MALI>; /* Glitch free mux */ - assigned-clock-parents = <0>, /* Do Nothing */ - <&clkc CLKID_GP0_PLL>, - <0>, /* Do Nothing */ - <&clkc CLKID_MALI_0>; - assigned-clock-rates = <744000000>, - <0>, /* Do Nothing */ - <744000000>, - <0>; /* Do Nothing */ - }; -}; - -&cbus { - spifc: spi@8c80 { - compatible = "amlogic,meson-gxbb-spifc"; - reg = <0x0 0x08c80 0x0 0x80>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clkc CLKID_SPI>; - status = "disabled"; - }; -}; - -&cec_AO { - clocks = <&clkc_AO CLKID_AO_CEC_32K>; - clock-names = "core"; -}; - -&clkc_AO { - compatible = "amlogic,meson-gxbb-aoclkc", "amlogic,meson-gx-aoclkc"; - clocks = <&xtal>, <&clkc CLKID_CLK81>; - clock-names = "xtal", "mpeg-clk"; -}; - -&efuse { - clocks = <&clkc CLKID_EFUSE>; -}; - -ðmac { - clocks = <&clkc CLKID_ETH>, - <&clkc CLKID_FCLK_DIV2>, - <&clkc CLKID_MPLL2>; - clock-names = "stmmaceth", "clkin0", "clkin1"; -}; - -&gpio_intc { - compatible = "amlogic,meson-gpio-intc", - "amlogic,meson-gxbb-gpio-intc"; - status = "okay"; -}; - -&hdmi_tx { - compatible = "amlogic,meson-gxbb-dw-hdmi", "amlogic,meson-gx-dw-hdmi"; - resets = <&reset RESET_HDMITX_CAPB3>, - <&reset RESET_HDMI_SYSTEM_RESET>, - <&reset RESET_HDMI_TX>; - reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy"; - clocks = <&clkc CLKID_HDMI_PCLK>, - <&clkc CLKID_CLK81>, - <&clkc CLKID_GCLK_VENCI_INT0>; - clock-names = "isfr", "iahb", "venci"; -}; - -&sysctrl { - clkc: clock-controller { - compatible = "amlogic,gxbb-clkc"; - #clock-cells = <1>; - clocks = <&xtal>; - clock-names = "xtal"; - }; -}; - -&hwrng { - clocks = <&clkc CLKID_RNG0>; - clock-names = "core"; -}; - -&i2c_A { - clocks = <&clkc CLKID_I2C>; -}; - -&i2c_AO { - clocks = <&clkc CLKID_AO_I2C>; -}; - -&i2c_B { - clocks = <&clkc CLKID_I2C>; -}; - -&i2c_C { - clocks = <&clkc CLKID_I2C>; -}; - -&periphs { - pinctrl_periphs: pinctrl@4b0 { - compatible = "amlogic,meson-gxbb-periphs-pinctrl"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - gpio: bank@4b0 { - reg = <0x0 0x004b0 0x0 0x28>, - <0x0 0x004e8 0x0 0x14>, - <0x0 0x00520 0x0 0x14>, - <0x0 0x00430 0x0 0x40>; - reg-names = "mux", "pull", "pull-enable", "gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl_periphs 0 0 119>; - }; - - emmc_pins: emmc { - mux-0 { - groups = "emmc_nand_d07", - "emmc_cmd"; - function = "emmc"; - bias-pull-up; - }; - - mux-1 { - groups = "emmc_clk"; - function = "emmc"; - bias-disable; - }; - }; - - emmc_ds_pins: emmc-ds { - mux { - groups = "emmc_ds"; - function = "emmc"; - bias-pull-down; - }; - }; - - emmc_clk_gate_pins: emmc_clk_gate { - mux { - groups = "BOOT_8"; - function = "gpio_periphs"; - bias-pull-down; - }; - }; - - nor_pins: nor { - mux { - groups = "nor_d", - "nor_q", - "nor_c", - "nor_cs"; - function = "nor"; - bias-disable; - }; - }; - - spi_pins: spi-pins { - mux { - groups = "spi_miso", - "spi_mosi", - "spi_sclk"; - function = "spi"; - bias-disable; - }; - }; - - spi_ss0_pins: spi-ss0 { - mux { - groups = "spi_ss0"; - function = "spi"; - bias-disable; - }; - }; - - sdcard_pins: sdcard { - mux-0 { - groups = "sdcard_d0", - "sdcard_d1", - "sdcard_d2", - "sdcard_d3", - "sdcard_cmd"; - function = "sdcard"; - bias-pull-up; - }; - - mux-1 { - groups = "sdcard_clk"; - function = "sdcard"; - bias-disable; - }; - }; - - sdcard_clk_gate_pins: sdcard_clk_gate { - mux { - groups = "CARD_2"; - function = "gpio_periphs"; - bias-pull-down; - }; - }; - - sdio_pins: sdio { - mux-0 { - groups = "sdio_d0", - "sdio_d1", - "sdio_d2", - "sdio_d3", - "sdio_cmd"; - function = "sdio"; - bias-pull-up; - }; - - mux-1 { - groups = "sdio_clk"; - function = "sdio"; - bias-disable; - }; - }; - - sdio_clk_gate_pins: sdio_clk_gate { - mux { - groups = "GPIOX_4"; - function = "gpio_periphs"; - bias-pull-down; - }; - }; - - sdio_irq_pins: sdio_irq { - mux { - groups = "sdio_irq"; - function = "sdio"; - bias-disable; - }; - }; - - uart_a_pins: uart_a { - mux { - groups = "uart_tx_a", - "uart_rx_a"; - function = "uart_a"; - bias-disable; - }; - }; - - uart_a_cts_rts_pins: uart_a_cts_rts { - mux { - groups = "uart_cts_a", - "uart_rts_a"; - function = "uart_a"; - bias-disable; - }; - }; - - uart_b_pins: uart_b { - mux { - groups = "uart_tx_b", - "uart_rx_b"; - function = "uart_b"; - bias-disable; - }; - }; - - uart_b_cts_rts_pins: uart_b_cts_rts { - mux { - groups = "uart_cts_b", - "uart_rts_b"; - function = "uart_b"; - bias-disable; - }; - }; - - uart_c_pins: uart_c { - mux { - groups = "uart_tx_c", - "uart_rx_c"; - function = "uart_c"; - bias-disable; - }; - }; - - uart_c_cts_rts_pins: uart_c_cts_rts { - mux { - groups = "uart_cts_c", - "uart_rts_c"; - function = "uart_c"; - bias-disable; - }; - }; - - i2c_a_pins: i2c_a { - mux { - groups = "i2c_sck_a", - "i2c_sda_a"; - function = "i2c_a"; - bias-disable; - }; - }; - - i2c_b_pins: i2c_b { - mux { - groups = "i2c_sck_b", - "i2c_sda_b"; - function = "i2c_b"; - bias-disable; - }; - }; - - i2c_c_pins: i2c_c { - mux { - groups = "i2c_sck_c", - "i2c_sda_c"; - function = "i2c_c"; - bias-disable; - }; - }; - - eth_rgmii_pins: eth-rgmii { - mux { - groups = "eth_mdio", - "eth_mdc", - "eth_clk_rx_clk", - "eth_rx_dv", - "eth_rxd0", - "eth_rxd1", - "eth_rxd2", - "eth_rxd3", - "eth_rgmii_tx_clk", - "eth_tx_en", - "eth_txd0", - "eth_txd1", - "eth_txd2", - "eth_txd3"; - function = "eth"; - bias-disable; - }; - }; - - eth_rmii_pins: eth-rmii { - mux { - groups = "eth_mdio", - "eth_mdc", - "eth_clk_rx_clk", - "eth_rx_dv", - "eth_rxd0", - "eth_rxd1", - "eth_tx_en", - "eth_txd0", - "eth_txd1"; - function = "eth"; - bias-disable; - }; - }; - - pwm_a_x_pins: pwm_a_x { - mux { - groups = "pwm_a_x"; - function = "pwm_a_x"; - bias-disable; - }; - }; - - pwm_a_y_pins: pwm_a_y { - mux { - groups = "pwm_a_y"; - function = "pwm_a_y"; - bias-disable; - }; - }; - - pwm_b_pins: pwm_b { - mux { - groups = "pwm_b"; - function = "pwm_b"; - bias-disable; - }; - }; - - pwm_d_pins: pwm_d { - mux { - groups = "pwm_d"; - function = "pwm_d"; - bias-disable; - }; - }; - - pwm_e_pins: pwm_e { - mux { - groups = "pwm_e"; - function = "pwm_e"; - bias-disable; - }; - }; - - pwm_f_x_pins: pwm_f_x { - mux { - groups = "pwm_f_x"; - function = "pwm_f_x"; - bias-disable; - }; - }; - - pwm_f_y_pins: pwm_f_y { - mux { - groups = "pwm_f_y"; - function = "pwm_f_y"; - bias-disable; - }; - }; - - hdmi_hpd_pins: hdmi_hpd { - mux { - groups = "hdmi_hpd"; - function = "hdmi_hpd"; - bias-disable; - }; - }; - - hdmi_i2c_pins: hdmi_i2c { - mux { - groups = "hdmi_sda", "hdmi_scl"; - function = "hdmi_i2c"; - bias-disable; - }; - }; - - i2sout_ch23_y_pins: i2sout_ch23_y { - mux { - groups = "i2sout_ch23_y"; - function = "i2s_out"; - bias-disable; - }; - }; - - i2sout_ch45_y_pins: i2sout_ch45_y { - mux { - groups = "i2sout_ch45_y"; - function = "i2s_out"; - bias-disable; - }; - }; - - i2sout_ch67_y_pins: i2sout_ch67_y { - mux { - groups = "i2sout_ch67_y"; - function = "i2s_out"; - bias-disable; - }; - }; - - spdif_out_y_pins: spdif_out_y { - mux { - groups = "spdif_out_y"; - function = "spdif_out"; - bias-disable; - }; - }; - }; -}; - -&pwrc_vpu { - resets = <&reset RESET_VIU>, - <&reset RESET_VENC>, - <&reset RESET_VCBUS>, - <&reset RESET_BT656>, - <&reset RESET_DVIN_RESET>, - <&reset RESET_RDMA>, - <&reset RESET_VENCI>, - <&reset RESET_VENCP>, - <&reset RESET_VDAC>, - <&reset RESET_VDI6>, - <&reset RESET_VENCL>, - <&reset RESET_VID_LOCK>; - clocks = <&clkc CLKID_VPU>, - <&clkc CLKID_VAPB>; - clock-names = "vpu", "vapb"; - /* - * VPU clocking is provided by two identical clock paths - * VPU_0 and VPU_1 muxed to a single clock by a glitch - * free mux to safely change frequency while running. - * Same for VAPB but with a final gate after the glitch free mux. - */ - assigned-clocks = <&clkc CLKID_VPU_0_SEL>, - <&clkc CLKID_VPU_0>, - <&clkc CLKID_VPU>, /* Glitch free mux */ - <&clkc CLKID_VAPB_0_SEL>, - <&clkc CLKID_VAPB_0>, - <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */ - assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>, - <0>, /* Do Nothing */ - <&clkc CLKID_VPU_0>, - <&clkc CLKID_FCLK_DIV4>, - <0>, /* Do Nothing */ - <&clkc CLKID_VAPB_0>; - assigned-clock-rates = <0>, /* Do Nothing */ - <666666666>, - <0>, /* Do Nothing */ - <0>, /* Do Nothing */ - <250000000>, - <0>; /* Do Nothing */ -}; - -&saradc { - compatible = "amlogic,meson-gxbb-saradc", "amlogic,meson-saradc"; - clocks = <&xtal>, - <&clkc CLKID_SAR_ADC>, - <&clkc CLKID_SAR_ADC_CLK>, - <&clkc CLKID_SAR_ADC_SEL>; - clock-names = "clkin", "core", "adc_clk", "adc_sel"; -}; - -&sd_emmc_a { - clocks = <&clkc CLKID_SD_EMMC_A>, - <&clkc CLKID_SD_EMMC_A_CLK0>, - <&clkc CLKID_FCLK_DIV2>; - clock-names = "core", "clkin0", "clkin1"; - resets = <&reset RESET_SD_EMMC_A>; -}; - -&sd_emmc_b { - clocks = <&clkc CLKID_SD_EMMC_B>, - <&clkc CLKID_SD_EMMC_B_CLK0>, - <&clkc CLKID_FCLK_DIV2>; - clock-names = "core", "clkin0", "clkin1"; - resets = <&reset RESET_SD_EMMC_B>; -}; - -&sd_emmc_c { - clocks = <&clkc CLKID_SD_EMMC_C>, - <&clkc CLKID_SD_EMMC_C_CLK0>, - <&clkc CLKID_FCLK_DIV2>; - clock-names = "core", "clkin0", "clkin1"; - resets = <&reset RESET_SD_EMMC_C>; -}; - -&simplefb_hdmi { - clocks = <&clkc CLKID_HDMI_PCLK>, - <&clkc CLKID_CLK81>, - <&clkc CLKID_GCLK_VENCI_INT0>; -}; - -&spicc { - clocks = <&clkc CLKID_SPICC>; - clock-names = "core"; - resets = <&reset RESET_PERIPHS_SPICC>; - num-cs = <1>; -}; - -&spifc { - clocks = <&clkc CLKID_SPI>; -}; - -&uart_A { - clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; - clock-names = "xtal", "pclk", "baud"; -}; - -&uart_AO { - clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>; - clock-names = "xtal", "pclk", "baud"; -}; - -&uart_AO_B { - clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>; - clock-names = "xtal", "pclk", "baud"; -}; - -&uart_B { - clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; - clock-names = "xtal", "pclk", "baud"; -}; - -&uart_C { - clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>; - clock-names = "xtal", "pclk", "baud"; -}; - -&vpu { - compatible = "amlogic,meson-gxbb-vpu", "amlogic,meson-gx-vpu"; - power-domains = <&pwrc_vpu>; -}; - -&vdec { - compatible = "amlogic,gxbb-vdec", "amlogic,gx-vdec"; - clocks = <&clkc CLKID_DOS_PARSER>, - <&clkc CLKID_DOS>, - <&clkc CLKID_VDEC_1>, - <&clkc CLKID_VDEC_HEVC>; - clock-names = "dos_parser", "dos", "vdec_1", "vdec_hevc"; - resets = <&reset RESET_PARSER>; - reset-names = "esparser"; -}; diff --git a/sys/gnu/dts/arm64/amlogic/meson-gxl-mali.dtsi b/sys/gnu/dts/arm64/amlogic/meson-gxl-mali.dtsi deleted file mode 100644 index 6aaafff674f..00000000000 --- a/sys/gnu/dts/arm64/amlogic/meson-gxl-mali.dtsi +++ /dev/null @@ -1,45 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 BayLibre SAS - * Author: Neil Armstrong - */ - -&apb { - mali: gpu@c0000 { - compatible = "amlogic,meson-gxl-mali", "arm,mali-450"; - reg = <0x0 0xc0000 0x0 0x40000>; - interrupts = , - , - , - , - , - , - , - , - , - ; - interrupt-names = "gp", "gpmmu", "pp", "pmu", - "pp0", "ppmmu0", "pp1", "ppmmu1", - "pp2", "ppmmu2"; - clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>; - clock-names = "bus", "core"; - - /* - * Mali clocking is provided by two identical clock paths - * MALI_0 and MALI_1 muxed to a single clock by a glitch - * free mux to safely change frequency while running. - */ - assigned-clocks = <&clkc CLKID_GP0_PLL>, - <&clkc CLKID_MALI_0_SEL>, - <&clkc CLKID_MALI_0>, - <&clkc CLKID_MALI>; /* Glitch free mux */ - assigned-clock-parents = <0>, /* Do Nothing */ - <&clkc CLKID_GP0_PLL>, - <0>, /* Do Nothing */ - <&clkc CLKID_MALI_0>; - assigned-clock-rates = <744000000>, - <0>, /* Do Nothing */ - <744000000>, - <0>; /* Do Nothing */ - }; -}; diff --git a/sys/gnu/dts/arm64/amlogic/meson-gxl-s805x-libretech-ac.dts b/sys/gnu/dts/arm64/amlogic/meson-gxl-s805x-libretech-ac.dts deleted file mode 100644 index 4d594949659..00000000000 --- a/sys/gnu/dts/arm64/amlogic/meson-gxl-s805x-libretech-ac.dts +++ /dev/null @@ -1,248 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2018 BayLibre, SAS. - * Author: Neil Armstrong - * Author: Jerome Brunet - */ - -/dts-v1/; - -#include - -#include "meson-gxl-s905x.dtsi" - -/ { - compatible = "libretech,aml-s805x-ac", "amlogic,s805x", - "amlogic,meson-gxl"; - model = "Libre Computer AML-S805X-AC"; - - aliases { - serial0 = &uart_AO; - ethernet0 = ðmac; - spi0 = &spifc; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - cvbs-connector { - /* - * The pads are present but no connector is soldered on - * 2J2, so keep this off by default. - */ - status = "disabled"; - compatible = "composite-video-connector"; - - port { - cvbs_connector_in: endpoint { - remote-endpoint = <&cvbs_vdac_out>; - }; - }; - }; - - dc_5v: regulator-dc_5v { - compatible = "regulator-fixed"; - regulator-name = "DC_5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x20000000>; - }; - - vcck: regulator-vcck { - compatible = "regulator-fixed"; - regulator-name = "VCCK"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&dc_5v>; - - /* - * This is controlled by GPIOAO_9 we reserve this but - * claiming it as done below reset the board anyway - * Need to investigate this - * - * gpio = <&gpio_ao GPIOAO_9 GPIO_ACTIVE_HIGH>; - * enable-active-high; - */ - regulator-always-on; - }; - - vcc_3v3: regulator-vcc_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&dc_5v>; - regulator-always-on; - }; - - vddio_boot: regulator-vddio_boot { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_BOOT"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_3v3>; - regulator-always-on; - }; -}; - -&cec_AO { - status = "okay"; - pinctrl-0 = <&ao_cec_pins>; - pinctrl-names = "default"; - hdmi-phandle = <&hdmi_tx>; -}; - -&cvbs_vdac_port { - cvbs_vdac_out: endpoint { - remote-endpoint = <&cvbs_connector_in>; - }; -}; - -ðmac { - status = "okay"; -}; - -&internal_phy { - pinctrl-0 = <ð_link_led_pins>, <ð_act_led_pins>; - pinctrl-names = "default"; -}; - -&ir { - status = "okay"; - pinctrl-0 = <&remote_input_ao_pins>; - pinctrl-names = "default"; -}; - -&hdmi_tx { - status = "okay"; - pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; - pinctrl-names = "default"; -}; - -&hdmi_tx_tmds_port { - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; -}; - -&gpio_ao { - gpio-line-names = "UART TX", - "UART RX", - "7J1 Header Pin31", - "", "", "", "", - "IR In", - "HDMI CEC", - "5V VCCK Regulator", - /* GPIO_TEST_N */ - ""; -}; - -&gpio { - gpio-line-names = /* Bank GPIOZ */ - "", "", "", "", "", "", "", - "", "", "", "", "", "", "", - "Eth Link LED", "Eth Activity LED", - /* Bank GPIOH */ - "HDMI HPD", "HDMI SDA", "HDMI SCL", - "", "7J1 Header Pin13", - "7J1 Header Pin15", - "7J1 Header Pin7", - "7J1 Header Pin12", - "7J1 Header Pin16", - "7J1 Header Pin18", - /* Bank BOOT */ - "eMMC D0", "eMMC D1", "eMMC D2", "eMMC D3", - "eMMC D4", "eMMC D5", "eMMC D6", "eMMC D7", - "eMMC Clk", "eMMC Reset", "eMMC CMD", - "SPI NOR MOSI", "SPI NOR MISO", "SPI NOR Clk", - "", "SPI NOR Chip Select", - /* Bank CARD */ - "", "", "", "", "", "", "", - /* Bank GPIODV */ - "", "", "", "", "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", "", "", "", "", - "7J1 Header Pin27", "7J1 Header Pin28", "", - "7J1 Header Pin29", - "VCCK Regulator", "VDDEE Regulator", - /* Bank GPIOX */ - "7J1 Header Pin22", "7J1 Header Pin26", - "7J1 Header Pin36", "7J1 Header Pin38", - "7J1 Header Pin40", "7J1 Header Pin37", - "7J1 Header Pin33", "7J1 Header Pin35", - "7J1 Header Pin19", "7J1 Header Pin21", - "7J1 Header Pin24", "7J1 Header Pin23", - "7J1 Header Pin8", "7J1 Header Pin10", - "", "", "7J1 Header Pin32", "", "", - /* Bank GPIOCLK */ - "", ""; -}; - -&saradc { - status = "okay"; - vref-supply = <&vddio_boot>; -}; - -/* eMMC */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - max-frequency = <200000000>; - disable-wp; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&vddio_boot>; -}; - -&spifc { - status = "okay"; - pinctrl-0 = <&nor_pins>; - pinctrl-names = "default"; - - w25q32: spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <3000000>; - }; -}; - -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -&usb0 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/amlogic/meson-gxl-s805x-p241.dts b/sys/gnu/dts/arm64/amlogic/meson-gxl-s805x-p241.dts deleted file mode 100644 index a1119cfb028..00000000000 --- a/sys/gnu/dts/arm64/amlogic/meson-gxl-s805x-p241.dts +++ /dev/null @@ -1,221 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2018 BayLibre, SAS. - * Author: Neil Armstrong - * Author: Jerome Brunet - */ - -/dts-v1/; - -#include - -#include "meson-gxl-s905x.dtsi" - -/ { - compatible = "amlogic,p241", "amlogic,s805x", "amlogic,meson-gxl"; - model = "Amlogic Meson GXL (S805X) P241 Development Board"; - - aliases { - serial0 = &uart_AO; - serial1 = &uart_A; - ethernet0 = ðmac; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - cvbs-connector { - compatible = "composite-video-connector"; - - port { - cvbs_connector_in: endpoint { - remote-endpoint = <&cvbs_vdac_out>; - }; - }; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x20000000>; - }; - - vddio_boot: regulator-vddio_boot { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_BOOT"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vddao_3v3: regulator-vddao_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vddio_ao18: regulator-vddio_ao18 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vcc_3v3: regulator-vcc_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; - }; - - wifi32k: wifi32k { - compatible = "pwm-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; - clocks = <&wifi32k>; - clock-names = "ext_clock"; - }; -}; - -&cec_AO { - status = "okay"; - pinctrl-0 = <&ao_cec_pins>; - pinctrl-names = "default"; - hdmi-phandle = <&hdmi_tx>; -}; - -&cvbs_vdac_port { - cvbs_vdac_out: endpoint { - remote-endpoint = <&cvbs_connector_in>; - }; -}; - -ðmac { - status = "okay"; -}; - -&internal_phy { - pinctrl-0 = <ð_link_led_pins>, <ð_act_led_pins>; - pinctrl-names = "default"; -}; - -&ir { - status = "okay"; - pinctrl-0 = <&remote_input_ao_pins>; - pinctrl-names = "default"; -}; - -&hdmi_tx { - status = "okay"; - pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; - pinctrl-names = "default"; -}; - -&hdmi_tx_tmds_port { - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; -}; - -&saradc { - status = "okay"; - vref-supply = <&vddio_ao18>; -}; - -/* Wireless SDIO Module */ -&sd_emmc_a { - status = "okay"; - pinctrl-0 = <&sdio_pins>; - pinctrl-1 = <&sdio_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - #address-cells = <1>; - #size-cells = <0>; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <50000000>; - - non-removable; - disable-wp; - - /* WiFi firmware requires power to be kept while in suspend */ - keep-power-in-suspend; - - mmc-pwrseq = <&sdio_pwrseq>; - - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddio_boot>; -}; - -/* eMMC */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - max-frequency = <200000000>; - non-removable; - disable-wp; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&vddio_boot>; -}; - -&pwm_ef { - status = "okay"; - pinctrl-0 = <&pwm_e_pins>; - pinctrl-names = "default"; - clocks = <&clkc CLKID_FCLK_DIV4>; - clock-names = "clkin0"; -}; - -/* This is connected to the Bluetooth module: */ -&uart_A { - status = "okay"; - pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; - pinctrl-names = "default"; - uart-has-rtscts; -}; - -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -&usb0 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/amlogic/meson-gxl-s905d-libretech-pc.dts b/sys/gnu/dts/arm64/amlogic/meson-gxl-s905d-libretech-pc.dts deleted file mode 100644 index 100a1cfeea1..00000000000 --- a/sys/gnu/dts/arm64/amlogic/meson-gxl-s905d-libretech-pc.dts +++ /dev/null @@ -1,16 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2019 BayLibre SAS. All rights reserved. - * Author: Jerome Brunet - */ - -/dts-v1/; - -#include "meson-gxl-s905d.dtsi" -#include "meson-gx-libretech-pc.dtsi" - -/ { - compatible = "libretech,aml-s905d-pc", "amlogic,s905d", - "amlogic,meson-gxl"; - model = "Libre Computer AML-S905D-PC"; -}; diff --git a/sys/gnu/dts/arm64/amlogic/meson-gxl-s905d-p230.dts b/sys/gnu/dts/arm64/amlogic/meson-gxl-s905d-p230.dts deleted file mode 100644 index b08c4537f26..00000000000 --- a/sys/gnu/dts/arm64/amlogic/meson-gxl-s905d-p230.dts +++ /dev/null @@ -1,111 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Endless Computers, Inc. - * Author: Carlo Caione - */ - -/dts-v1/; - -#include - -#include "meson-gxl-s905d.dtsi" -#include "meson-gx-p23x-q20x.dtsi" - -/ { - compatible = "amlogic,p230", "amlogic,s905d", "amlogic,meson-gxl"; - model = "Amlogic Meson GXL (S905D) P230 Development Board"; - - adc-keys { - compatible = "adc-keys"; - io-channels = <&saradc 0>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1710000>; - - button-function { - label = "Update"; - linux,code = ; - press-threshold-microvolt = <10000>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <100>; - - button@0 { - label = "power"; - linux,code = ; - gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>; - }; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; - }; -}; - -&cec_AO { - status = "okay"; - pinctrl-0 = <&ao_cec_pins>; - pinctrl-names = "default"; - hdmi-phandle = <&hdmi_tx>; -}; - -/* P230 has exclusive choice between internal or external PHY */ -ðmac { - pinctrl-0 = <ð_pins>; - pinctrl-names = "default"; - - /* Select external PHY by default */ - phy-handle = <&external_phy>; - - amlogic,tx-delay-ns = <2>; - - /* External PHY is in RGMII */ - phy-mode = "rgmii"; -}; - -&external_mdio { - external_phy: ethernet-phy@0 { - /* Realtek RTL8211F (0x001cc916) */ - reg = <0>; - max-speed = <1000>; - - /* External PHY reset is shared with internal PHY Led signal */ - reset-assert-us = <10000>; - reset-deassert-us = <30000>; - reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; - - interrupt-parent = <&gpio_intc>; - interrupts = <29 IRQ_TYPE_LEVEL_LOW>; - eee-broken-1000t; - }; -}; - -&hdmi_tx { - status = "okay"; - pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; - pinctrl-names = "default"; -}; - -&hdmi_tx_tmds_port { - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; -}; - -&sd_emmc_a { - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - }; -}; diff --git a/sys/gnu/dts/arm64/amlogic/meson-gxl-s905d-p231.dts b/sys/gnu/dts/arm64/amlogic/meson-gxl-s905d-p231.dts deleted file mode 100644 index 92c425d0259..00000000000 --- a/sys/gnu/dts/arm64/amlogic/meson-gxl-s905d-p231.dts +++ /dev/null @@ -1,28 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Endless Computers, Inc. - * Author: Carlo Caione - */ - -/dts-v1/; - -#include "meson-gxl-s905d.dtsi" -#include "meson-gx-p23x-q20x.dtsi" - -/ { - compatible = "amlogic,p231", "amlogic,s905d", "amlogic,meson-gxl"; - model = "Amlogic Meson GXL (S905D) P231 Development Board"; -}; - -/* P231 has only internal PHY port */ -ðmac { - phy-mode = "rmii"; - phy-handle = <&internal_phy>; -}; - -&sd_emmc_a { - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - }; -}; diff --git a/sys/gnu/dts/arm64/amlogic/meson-gxl-s905d-phicomm-n1.dts b/sys/gnu/dts/arm64/amlogic/meson-gxl-s905d-phicomm-n1.dts deleted file mode 100644 index b5667f1fb2c..00000000000 --- a/sys/gnu/dts/arm64/amlogic/meson-gxl-s905d-phicomm-n1.dts +++ /dev/null @@ -1,31 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2018 He Yangxuan - */ - -/dts-v1/; - -#include "meson-gxl-s905d-p230.dts" - -/ { - compatible = "phicomm,n1", "amlogic,s905d", "amlogic,meson-gxl"; - model = "Phicomm N1"; - - cvbs-connector { - status = "disabled"; - }; - - leds { - compatible = "gpio-leds"; - - status { - label = "n1:white:status"; - gpios = <&gpio_ao GPIOAO_9 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; -}; - -&cvbs_vdac_port { - status = "disabled"; -}; diff --git a/sys/gnu/dts/arm64/amlogic/meson-gxl-s905d.dtsi b/sys/gnu/dts/arm64/amlogic/meson-gxl-s905d.dtsi deleted file mode 100644 index 43321919547..00000000000 --- a/sys/gnu/dts/arm64/amlogic/meson-gxl-s905d.dtsi +++ /dev/null @@ -1,12 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Endless Computers, Inc. - * Author: Carlo Caione - */ - -#include "meson-gxl.dtsi" -#include "meson-gxl-mali.dtsi" - -/ { - compatible = "amlogic,s905d", "amlogic,meson-gxl"; -}; diff --git a/sys/gnu/dts/arm64/amlogic/meson-gxl-s905w-p281.dts b/sys/gnu/dts/arm64/amlogic/meson-gxl-s905w-p281.dts deleted file mode 100644 index 6509c495095..00000000000 --- a/sys/gnu/dts/arm64/amlogic/meson-gxl-s905w-p281.dts +++ /dev/null @@ -1,22 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2018 Martin Blumenstingl . - * Based on meson-gxl-s905d-p231.dts: - * - Copyright (c) 2016 Endless Computers, Inc. - * Author: Carlo Caione - */ - -/dts-v1/; - -#include "meson-gxl-s905x.dtsi" -#include "meson-gx-p23x-q20x.dtsi" - -/ { - compatible = "amlogic,p281", "amlogic,s905w", "amlogic,meson-gxl"; - model = "Amlogic Meson GXL (S905W) P281 Development Board"; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x40000000>; - }; -}; diff --git a/sys/gnu/dts/arm64/amlogic/meson-gxl-s905w-tx3-mini.dts b/sys/gnu/dts/arm64/amlogic/meson-gxl-s905w-tx3-mini.dts deleted file mode 100644 index dd729ac2300..00000000000 --- a/sys/gnu/dts/arm64/amlogic/meson-gxl-s905w-tx3-mini.dts +++ /dev/null @@ -1,26 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2018 Martin Blumenstingl . - * Based on meson-gxl-s905d-p231.dts: - * - Copyright (c) 2016 Endless Computers, Inc. - * Author: Carlo Caione - */ - -/dts-v1/; - -#include "meson-gxl-s905x.dtsi" -#include "meson-gx-p23x-q20x.dtsi" - -/ { - compatible = "oranth,tx3-mini", "amlogic,s905w", "amlogic,meson-gxl"; - model = "Oranth Tanix TX3 Mini"; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x40000000>; /* 1 GiB or 2 GiB */ - }; -}; - -&ir { - linux,rc-map-name = "rc-tanix-tx3mini"; -}; diff --git a/sys/gnu/dts/arm64/amlogic/meson-gxl-s905x-hwacom-amazetv.dts b/sys/gnu/dts/arm64/amlogic/meson-gxl-s905x-hwacom-amazetv.dts deleted file mode 100644 index c8d74e61dec..00000000000 --- a/sys/gnu/dts/arm64/amlogic/meson-gxl-s905x-hwacom-amazetv.dts +++ /dev/null @@ -1,164 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 Carlo Caione - * Copyright (c) 2016 BayLibre, Inc. - * Author: Neil Armstrong - */ - -/dts-v1/; - -#include "meson-gxl-s905x.dtsi" - -/ { - compatible = "hwacom,amazetv", "amlogic,s905x", "amlogic,meson-gxl"; - model = "Hwacom AmazeTV (S905X)"; - - aliases { - serial0 = &uart_AO; - ethernet0 = ðmac; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; - - vddio_card: gpio-regulator { - compatible = "regulator-gpio"; - - regulator-name = "VDDIO_CARD"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>; - gpios-states = <1>; - - /* Based on P200 schematics, signal CARD_1.8V/3.3V_CTR */ - states = <1800000 0>, - <3300000 1>; - }; - - vddio_boot: regulator-vddio_boot { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_BOOT"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vddao_3v3: regulator-vddao_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vcc_3v3: regulator-vcc_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; - }; - - wifi32k: wifi32k { - compatible = "pwm-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; - clocks = <&wifi32k>; - clock-names = "ext_clock"; - }; - - cvbs-connector { - compatible = "composite-video-connector"; - - port { - cvbs_connector_in: endpoint { - remote-endpoint = <&cvbs_vdac_out>; - }; - }; - }; -}; - -&cvbs_vdac_port { - cvbs_vdac_out: endpoint { - remote-endpoint = <&cvbs_connector_in>; - }; -}; - -ðmac { - status = "okay"; - phy-mode = "rmii"; - phy-handle = <&internal_phy>; -}; - -&ir { - status = "okay"; - pinctrl-0 = <&remote_input_ao_pins>; - pinctrl-names = "default"; -}; - -&pwm_ef { - status = "okay"; - pinctrl-0 = <&pwm_e_pins>; - pinctrl-names = "default"; - clocks = <&clkc CLKID_FCLK_DIV4>; - clock-names = "clkin0"; -}; - -/* SD card */ -&sd_emmc_b { - status = "okay"; - pinctrl-0 = <&sdcard_pins>; - pinctrl-1 = <&sdcard_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <100000000>; - disable-wp; - - cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; - - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddio_card>; -}; - -/* eMMC */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - max-frequency = <100000000>; - non-removable; - disable-wp; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&vddio_boot>; -}; - -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; diff --git a/sys/gnu/dts/arm64/amlogic/meson-gxl-s905x-khadas-vim.dts b/sys/gnu/dts/arm64/amlogic/meson-gxl-s905x-khadas-vim.dts deleted file mode 100644 index 440bc23c734..00000000000 --- a/sys/gnu/dts/arm64/amlogic/meson-gxl-s905x-khadas-vim.dts +++ /dev/null @@ -1,209 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 Martin Blumenstingl . - */ - -/dts-v1/; - -#include - -#include "meson-gxl-s905x-p212.dtsi" - -/ { - compatible = "khadas,vim", "amlogic,s905x", "amlogic,meson-gxl"; - model = "Khadas VIM"; - - adc-keys { - compatible = "adc-keys"; - io-channels = <&saradc 0>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1710000>; - - button-function { - label = "Function"; - linux,code = ; - press-threshold-microvolt = <10000>; - }; - }; - - aliases { - serial2 = &uart_AO_B; - ethernet0 = ðmac; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - poll-interval = <100>; - - power-button { - label = "power"; - linux,code = ; - gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>; - }; - }; - - pwmleds { - compatible = "pwm-leds"; - - power { - label = "vim:red:power"; - pwms = <&pwm_AO_ab 1 7812500 0>; - max-brightness = <255>; - linux,default-trigger = "default-on"; - }; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; - }; -}; - -&cec_AO { - status = "okay"; - pinctrl-0 = <&ao_cec_pins>; - pinctrl-names = "default"; - hdmi-phandle = <&hdmi_tx>; -}; - -&hdmi_tx { - status = "okay"; - pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; - pinctrl-names = "default"; - hdmi-supply = <&hdmi_5v>; -}; - -&hdmi_tx_tmds_port { - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; -}; - -&i2c_A { - status = "okay"; - pinctrl-0 = <&i2c_a_pins>; - pinctrl-names = "default"; -}; - -&i2c_B { - status = "okay"; - pinctrl-0 = <&i2c_b_pins>; - pinctrl-names = "default"; - - rtc: rtc@51 { - /* has to be enabled manually when a battery is connected: */ - status = "disabled"; - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "xin32k"; - }; -}; - -&ir { - linux,rc-map-name = "rc-khadas"; -}; - -&gpio_ao { - gpio-line-names = "UART TX", - "UART RX", - "Power Key In", - "J9 Header Pin35", - "J9 Header Pin16", - "J9 Header Pin15", - "J9 Header Pin33", - "IR In", - "HDMI CEC", - "SYS LED", - /* GPIO_TEST_N */ - ""; -}; - -&gpio { - gpio-line-names = /* Bank GPIOZ */ - "", "", "", "", "", "", "", - "", "", "", "", "", "", "", - "Power OFF", - "VCCK Enable", - /* Bank GPIOH */ - "HDMI HPD", "HDMI SDA", "HDMI SCL", - "HDMI_5V_EN", "SPDIF", - "J9 Header Pin37", - "J9 Header Pin30", - "J9 Header Pin29", - "J9 Header Pin32", - "J9 Header Pin31", - /* Bank BOOT */ - "eMMC D0", "eMMC D1", "eMMC D2", "eMMC D3", - "eMMC D4", "eMMC D5", "eMMC D6", "eMMC D7", - "eMMC Clk", "eMMC Reset", "eMMC CMD", - "", "BOOT_MODE", "", "", "eMMC Data Strobe", - /* Bank CARD */ - "SDCard D1", "SDCard D0", "SDCard CLK", "SDCard CMD", - "SDCard D3", "SDCard D2", "SDCard Det", - /* Bank GPIODV */ - "", "", "", "", "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", "", "", "", "", - "I2C A SDA", "I2C A SCK", "I2C B SDA", "I2C B SCK", - "VCCK Regulator", "VDDEE Regulator", - /* Bank GPIOX */ - "WIFI SDIO D0", "WIFI SDIO D1", "WIFI SDIO D2", - "WIFI SDIO D3", "WIFI SDIO CLK", "WIFI SDIO CMD", - "WIFI Power Enable", "WIFI WAKE HOST", - "Bluetooth PCM DOUT", "Bluetooth PCM DIN", - "Bluetooth PCM SYNC", "Bluetooth PCM CLK", - "Bluetooth UART TX", "Bluetooth UART RX", - "Bluetooth UART CTS", "Bluetooth UART RTS", - "WIFI 32K", "Bluetooth Enable", - "Bluetooth WAKE HOST", - /* Bank GPIOCLK */ - "", "J9 Header Pin39"; -}; - -&pwm_AO_ab { - status = "okay"; - pinctrl-0 = <&pwm_ao_a_3_pins>, <&pwm_ao_b_pins>; - pinctrl-names = "default"; - clocks = <&xtal> , <&xtal>; - clock-names = "clkin0", "clkin1" ; -}; - -&pwm_ef { - pinctrl-0 = <&pwm_e_pins>, <&pwm_f_clk_pins>; -}; - -&sd_emmc_a { - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - }; -}; - -&uart_A { - bluetooth { - compatible = "brcm,bcm43438-bt"; - shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; - max-speed = <2000000>; - clocks = <&wifi32k>; - clock-names = "lpo"; - }; -}; - -/* This is brought out on the Linux_RX (18) and Linux_TX (19) pins: */ -&uart_AO { - status = "okay"; -}; - -/* This is brought out on the UART_RX_AO_B (15) and UART_TX_AO_B (16) pins: */ -&uart_AO_B { - status = "okay"; - pinctrl-0 = <&uart_ao_b_pins>; - pinctrl-names = "default"; -}; diff --git a/sys/gnu/dts/arm64/amlogic/meson-gxl-s905x-libretech-cc.dts b/sys/gnu/dts/arm64/amlogic/meson-gxl-s905x-libretech-cc.dts deleted file mode 100644 index e8348b2728d..00000000000 --- a/sys/gnu/dts/arm64/amlogic/meson-gxl-s905x-libretech-cc.dts +++ /dev/null @@ -1,285 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 BayLibre, SAS. - * Author: Neil Armstrong - * Author: Jerome Brunet - */ - -/dts-v1/; - -#include - -#include "meson-gxl-s905x.dtsi" - -/ { - compatible = "libretech,aml-s905x-cc", "amlogic,s905x", - "amlogic,meson-gxl"; - model = "Libre Computer AML-S905X-CC"; - - aliases { - serial0 = &uart_AO; - ethernet0 = ðmac; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - cvbs-connector { - compatible = "composite-video-connector"; - - port { - cvbs_connector_in: endpoint { - remote-endpoint = <&cvbs_vdac_out>; - }; - }; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - system { - label = "librecomputer:system-status"; - gpios = <&gpio GPIODV_24 GPIO_ACTIVE_HIGH>; - default-state = "on"; - panic-indicator; - }; - - blue { - label = "librecomputer:blue"; - gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; - - hdmi_5v: regulator-hdmi-5v { - compatible = "regulator-fixed"; - - regulator-name = "HDMI_5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - gpio = <&gpio GPIOH_3 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - }; - - vcc_3v3: regulator-vcc_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vcc_card: regulator-vcc-card { - compatible = "regulator-gpio"; - - regulator-name = "VCC_CARD"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>; - gpios-states = <0>; - - states = <3300000 0>, - <1800000 1>; - - regulator-settling-time-up-us = <200>; - regulator-settling-time-down-us = <50000>; - }; - - vddio_ao18: regulator-vddio_ao18 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - /* This is provided by LDOs on the eMMC daugther card */ - vddio_boot: regulator-vddio_boot { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_BOOT"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_3v3>; - }; -}; - -&cec_AO { - status = "okay"; - pinctrl-0 = <&ao_cec_pins>; - pinctrl-names = "default"; - hdmi-phandle = <&hdmi_tx>; -}; - -&cvbs_vdac_port { - cvbs_vdac_out: endpoint { - remote-endpoint = <&cvbs_connector_in>; - }; -}; - -ðmac { - status = "okay"; -}; - -&internal_phy { - pinctrl-0 = <ð_link_led_pins>, <ð_act_led_pins>; - pinctrl-names = "default"; -}; - -&ir { - status = "okay"; - pinctrl-0 = <&remote_input_ao_pins>; - pinctrl-names = "default"; -}; - -&hdmi_tx { - status = "okay"; - pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; - pinctrl-names = "default"; - hdmi-supply = <&hdmi_5v>; -}; - -&hdmi_tx_tmds_port { - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; -}; - -&gpio_ao { - gpio-line-names = "UART TX", - "UART RX", - "Blue LED", - "SDCard Voltage Switch", - "7J1 Header Pin5", - "7J1 Header Pin3", - "7J1 Header Pin12", - "IR In", - "9J3 Switch HDMI CEC/7J1 Header Pin11", - "7J1 Header Pin13", - /* GPIO_TEST_N */ - "7J1 Header Pin15"; -}; - -&gpio { - gpio-line-names = /* Bank GPIOZ */ - "", "", "", "", "", "", "", - "", "", "", "", "", "", "", - "Eth Link LED", "Eth Activity LED", - /* Bank GPIOH */ - "HDMI HPD", "HDMI SDA", "HDMI SCL", - "HDMI_5V_EN", "9J1 Header Pin2", - "Analog Audio Mute", - "2J3 Header Pin6", - "2J3 Header Pin5", - "2J3 Header Pin4", - "2J3 Header Pin3", - /* Bank BOOT */ - "eMMC D0", "eMMC D1", "eMMC D2", "eMMC D3", - "eMMC D4", "eMMC D5", "eMMC D6", "eMMC D7", - "eMMC Clk", "eMMC Reset", "eMMC CMD", - "ALT BOOT MODE", "", "", "", "eMMC Data Strobe", - /* Bank CARD */ - "SDCard D1", "SDCard D0", "SDCard CLK", "SDCard CMD", - "SDCard D3", "SDCard D2", "SDCard Det", - /* Bank GPIODV */ - "", "", "", "", "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", "", "", "", "", - "Green LED", "VCCK Enable", - "7J1 Header Pin27", "7J1 Header Pin28", - "VCCK Regulator", "VDDEE Regulator", - /* Bank GPIOX */ - "7J1 Header Pin22", "7J1 Header Pin26", - "7J1 Header Pin36", "7J1 Header Pin38", - "7J1 Header Pin40", "7J1 Header Pin37", - "7J1 Header Pin33", "7J1 Header Pin35", - "7J1 Header Pin19", "7J1 Header Pin21", - "7J1 Header Pin24", "7J1 Header Pin23", - "7J1 Header Pin8", "7J1 Header Pin10", - "7J1 Header Pin16", "7J1 Header Pin18", - "7J1 Header Pin32", "7J1 Header Pin29", - "7J1 Header Pin31", - /* Bank GPIOCLK */ - "7J1 Header Pin7", ""; -}; - -&saradc { - status = "okay"; - vref-supply = <&vddio_ao18>; -}; - -/* SD card */ -&sd_emmc_b { - status = "okay"; - pinctrl-0 = <&sdcard_pins>; - pinctrl-1 = <&sdcard_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <50000000>; - disable-wp; - - cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; - - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&vcc_card>; -}; - -/* eMMC */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - max-frequency = <200000000>; - disable-wp; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&vddio_boot>; -}; - -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -&usb0 { - status = "okay"; -}; - -&usb2_phy0 { - /* - * even though the schematics don't show it: - * HDMI_5V is also used as supply for the USB VBUS. - */ - phy-supply = <&hdmi_5v>; -}; diff --git a/sys/gnu/dts/arm64/amlogic/meson-gxl-s905x-nexbox-a95x.dts b/sys/gnu/dts/arm64/amlogic/meson-gxl-s905x-nexbox-a95x.dts deleted file mode 100644 index 62dd87821ce..00000000000 --- a/sys/gnu/dts/arm64/amlogic/meson-gxl-s905x-nexbox-a95x.dts +++ /dev/null @@ -1,223 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Andreas Färber - * Copyright (c) 2016 BayLibre, Inc. - * Author: Neil Armstrong - */ - -/dts-v1/; - -#include "meson-gxl-s905x.dtsi" - -/ { - compatible = "nexbox,a95x", "amlogic,s905x", "amlogic,meson-gxl"; - model = "NEXBOX A95X (S905X)"; - - aliases { - serial0 = &uart_AO; - ethernet0 = ðmac; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; - - vddio_card: gpio-regulator { - compatible = "regulator-gpio"; - - regulator-name = "VDDIO_CARD"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>; - gpios-states = <1>; - - /* Based on P200 schematics, signal CARD_1.8V/3.3V_CTR */ - states = <1800000 0>, - <3300000 1>; - }; - - vddio_boot: regulator-vddio_boot { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_BOOT"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vddao_3v3: regulator-vddao_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vcc_3v3: regulator-vcc_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; - }; - - wifi32k: wifi32k { - compatible = "pwm-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; - clocks = <&wifi32k>; - clock-names = "ext_clock"; - }; - - cvbs-connector { - compatible = "composite-video-connector"; - - port { - cvbs_connector_in: endpoint { - remote-endpoint = <&cvbs_vdac_out>; - }; - }; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; - }; -}; - -&cec_AO { - status = "okay"; - pinctrl-0 = <&ao_cec_pins>; - pinctrl-names = "default"; - hdmi-phandle = <&hdmi_tx>; -}; - -&cvbs_vdac_port { - cvbs_vdac_out: endpoint { - remote-endpoint = <&cvbs_connector_in>; - }; -}; - -ðmac { - status = "okay"; - phy-mode = "rmii"; - phy-handle = <&internal_phy>; -}; - -&hdmi_tx { - status = "okay"; - pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; - pinctrl-names = "default"; -}; - -&hdmi_tx_tmds_port { - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; -}; - -&ir { - status = "okay"; - pinctrl-0 = <&remote_input_ao_pins>; - pinctrl-names = "default"; -}; - -&pwm_ef { - status = "okay"; - pinctrl-0 = <&pwm_e_pins>; - pinctrl-names = "default"; - clocks = <&clkc CLKID_FCLK_DIV4>; - clock-names = "clkin0"; -}; - -/* Wireless SDIO Module */ -&sd_emmc_a { - status = "okay"; - pinctrl-0 = <&sdio_pins>; - pinctrl-1 = <&sdio_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - #address-cells = <1>; - #size-cells = <0>; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <100000000>; - - non-removable; - disable-wp; - - /* WiFi firmware requires power to be kept while in suspend */ - keep-power-in-suspend; - - mmc-pwrseq = <&sdio_pwrseq>; - - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddio_boot>; -}; - -/* SD card */ -&sd_emmc_b { - status = "okay"; - pinctrl-0 = <&sdcard_pins>; - pinctrl-1 = <&sdcard_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <50000000>; - disable-wp; - - cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; - - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddio_card>; -}; - -/* eMMC */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - max-frequency = <200000000>; - non-removable; - disable-wp; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&vddio_boot>; -}; - -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -&usb0 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/amlogic/meson-gxl-s905x-p212.dts b/sys/gnu/dts/arm64/amlogic/meson-gxl-s905x-p212.dts deleted file mode 100644 index 2602940c207..00000000000 --- a/sys/gnu/dts/arm64/amlogic/meson-gxl-s905x-p212.dts +++ /dev/null @@ -1,66 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Endless Computers, Inc. - * Author: Carlo Caione - */ - -/dts-v1/; - -#include "meson-gxl-s905x-p212.dtsi" - -/ { - compatible = "amlogic,p212", "amlogic,s905x", "amlogic,meson-gxl"; - model = "Amlogic Meson GXL (S905X) P212 Development Board"; - - cvbs-connector { - compatible = "composite-video-connector"; - - port { - cvbs_connector_in: endpoint { - remote-endpoint = <&cvbs_vdac_out>; - }; - }; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; - }; -}; - -&cec_AO { - status = "okay"; - pinctrl-0 = <&ao_cec_pins>; - pinctrl-names = "default"; - hdmi-phandle = <&hdmi_tx>; -}; - -&cvbs_vdac_port { - cvbs_vdac_out: endpoint { - remote-endpoint = <&cvbs_connector_in>; - }; -}; - -&hdmi_tx { - status = "okay"; - pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; - pinctrl-names = "default"; - hdmi-supply = <&hdmi_5v>; -}; - -&hdmi_tx_tmds_port { - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; -}; - -/* This UART is brought out to the DB9 connector */ -&uart_AO { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/amlogic/meson-gxl-s905x-p212.dtsi b/sys/gnu/dts/arm64/amlogic/meson-gxl-s905x-p212.dtsi deleted file mode 100644 index 43eb7d149e3..00000000000 --- a/sys/gnu/dts/arm64/amlogic/meson-gxl-s905x-p212.dtsi +++ /dev/null @@ -1,200 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Martin Blumenstingl . - * Based on meson-gx-p23x-q20x.dtsi: - * - Copyright (c) 2016 Endless Computers, Inc. - * Author: Carlo Caione - * - Copyright (c) 2016 BayLibre, SAS. - * Author: Neil Armstrong - */ - -/* Common DTSI for devices which are based on the P212 reference board. */ - -#include "meson-gxl-s905x.dtsi" - -/ { - aliases { - serial0 = &uart_AO; - serial1 = &uart_A; - ethernet0 = ðmac; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; - - hdmi_5v: regulator-hdmi-5v { - compatible = "regulator-fixed"; - - regulator-name = "HDMI_5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - gpio = <&gpio GPIOH_3 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - }; - - vddio_boot: regulator-vddio_boot { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_BOOT"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vddao_3v3: regulator-vddao_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vddio_ao18: regulator-vddio_ao18 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vcc_3v3: regulator-vcc_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; - }; - - wifi32k: wifi32k { - compatible = "pwm-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; - clocks = <&wifi32k>; - clock-names = "ext_clock"; - }; -}; - -ðmac { - status = "okay"; -}; - -&ir { - status = "okay"; - pinctrl-0 = <&remote_input_ao_pins>; - pinctrl-names = "default"; -}; - -&saradc { - status = "okay"; - vref-supply = <&vddio_ao18>; -}; - -/* Wireless SDIO Module */ -&sd_emmc_a { - status = "okay"; - pinctrl-0 = <&sdio_pins>; - pinctrl-1 = <&sdio_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - #address-cells = <1>; - #size-cells = <0>; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <50000000>; - - non-removable; - disable-wp; - - /* WiFi firmware requires power to be kept while in suspend */ - keep-power-in-suspend; - - mmc-pwrseq = <&sdio_pwrseq>; - - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddio_boot>; -}; - -/* SD card */ -&sd_emmc_b { - status = "okay"; - pinctrl-0 = <&sdcard_pins>; - pinctrl-1 = <&sdcard_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <50000000>; - disable-wp; - - cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; - - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddio_boot>; -}; - -/* eMMC */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - max-frequency = <200000000>; - non-removable; - disable-wp; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&vddio_boot>; -}; - -&pwm_ef { - status = "okay"; - pinctrl-0 = <&pwm_e_pins>; - pinctrl-names = "default"; - clocks = <&clkc CLKID_FCLK_DIV4>; - clock-names = "clkin0"; -}; - -/* This is connected to the Bluetooth module: */ -&uart_A { - status = "okay"; - pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; - pinctrl-names = "default"; - uart-has-rtscts; -}; - -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -&usb0 { - status = "okay"; -}; - -&usb2_phy0 { - /* - * HDMI_5V is also used as supply for the USB VBUS. - */ - phy-supply = <&hdmi_5v>; -}; diff --git a/sys/gnu/dts/arm64/amlogic/meson-gxl-s905x.dtsi b/sys/gnu/dts/arm64/amlogic/meson-gxl-s905x.dtsi deleted file mode 100644 index 40c19f69e9d..00000000000 --- a/sys/gnu/dts/arm64/amlogic/meson-gxl-s905x.dtsi +++ /dev/null @@ -1,18 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Endless Computers, Inc. - * Author: Carlo Caione - */ - -#include "meson-gxl.dtsi" -#include "meson-gxl-mali.dtsi" - -/ { - compatible = "amlogic,s905x", "amlogic,meson-gxl"; -}; - -/* S905X only has access to its internal PHY */ -ðmac { - phy-mode = "rmii"; - phy-handle = <&internal_phy>; -}; diff --git a/sys/gnu/dts/arm64/amlogic/meson-gxl.dtsi b/sys/gnu/dts/arm64/amlogic/meson-gxl.dtsi deleted file mode 100644 index 259d8639939..00000000000 --- a/sys/gnu/dts/arm64/amlogic/meson-gxl.dtsi +++ /dev/null @@ -1,877 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Endless Computers, Inc. - * Author: Carlo Caione - */ - -#include "meson-gx.dtsi" -#include -#include -#include -#include - -/ { - compatible = "amlogic,meson-gxl"; - - soc { - usb0: usb@c9000000 { - status = "disabled"; - compatible = "amlogic,meson-gxl-dwc3"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - clocks = <&clkc CLKID_USB>; - clock-names = "usb_general"; - resets = <&reset RESET_USB_OTG>; - reset-names = "usb_otg"; - - dwc3: dwc3@c9000000 { - compatible = "snps,dwc3"; - reg = <0x0 0xc9000000 0x0 0x100000>; - interrupts = ; - dr_mode = "host"; - maximum-speed = "high-speed"; - snps,dis_u2_susphy_quirk; - phys = <&usb3_phy>, <&usb2_phy0>, <&usb2_phy1>; - }; - }; - - crypto: crypto@c883e000 { - compatible = "amlogic,gxl-crypto"; - reg = <0x0 0xc883e000 0x0 0x36>; - interrupts = , - ; - clocks = <&clkc CLKID_BLKMV>; - clock-names = "blkmv"; - status = "okay"; - }; - }; -}; - -&apb { - usb2_phy0: phy@78000 { - compatible = "amlogic,meson-gxl-usb2-phy"; - #phy-cells = <0>; - reg = <0x0 0x78000 0x0 0x20>; - clocks = <&clkc CLKID_USB>; - clock-names = "phy"; - resets = <&reset RESET_USB_OTG>; - reset-names = "phy"; - status = "okay"; - }; - - usb2_phy1: phy@78020 { - compatible = "amlogic,meson-gxl-usb2-phy"; - #phy-cells = <0>; - reg = <0x0 0x78020 0x0 0x20>; - clocks = <&clkc CLKID_USB>; - clock-names = "phy"; - resets = <&reset RESET_USB_OTG>; - reset-names = "phy"; - status = "okay"; - }; - - usb3_phy: phy@78080 { - compatible = "amlogic,meson-gxl-usb3-phy"; - #phy-cells = <0>; - reg = <0x0 0x78080 0x0 0x20>; - interrupts = ; - clocks = <&clkc CLKID_USB>, <&clkc_AO CLKID_AO_CEC_32K>; - clock-names = "phy", "peripheral"; - resets = <&reset RESET_USB_OTG>, <&reset RESET_USB_OTG>; - reset-names = "phy", "peripheral"; - status = "okay"; - }; -}; - -&efuse { - clocks = <&clkc CLKID_EFUSE>; -}; - -ðmac { - clocks = <&clkc CLKID_ETH>, - <&clkc CLKID_FCLK_DIV2>, - <&clkc CLKID_MPLL2>; - clock-names = "stmmaceth", "clkin0", "clkin1"; - - mdio0: mdio { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - }; -}; - -&aobus { - pinctrl_aobus: pinctrl@14 { - compatible = "amlogic,meson-gxl-aobus-pinctrl"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - gpio_ao: bank@14 { - reg = <0x0 0x00014 0x0 0x8>, - <0x0 0x0002c 0x0 0x4>, - <0x0 0x00024 0x0 0x8>; - reg-names = "mux", "pull", "gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl_aobus 0 0 14>; - }; - - uart_ao_a_pins: uart_ao_a { - mux { - groups = "uart_tx_ao_a", "uart_rx_ao_a"; - function = "uart_ao"; - bias-disable; - }; - }; - - uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts { - mux { - groups = "uart_cts_ao_a", - "uart_rts_ao_a"; - function = "uart_ao"; - bias-disable; - }; - }; - - uart_ao_b_pins: uart_ao_b { - mux { - groups = "uart_tx_ao_b", "uart_rx_ao_b"; - function = "uart_ao_b"; - bias-disable; - }; - }; - - uart_ao_b_0_1_pins: uart_ao_b_0_1 { - mux { - groups = "uart_tx_ao_b_0", "uart_rx_ao_b_1"; - function = "uart_ao_b"; - bias-disable; - }; - }; - - uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts { - mux { - groups = "uart_cts_ao_b", - "uart_rts_ao_b"; - function = "uart_ao_b"; - bias-disable; - }; - }; - - remote_input_ao_pins: remote_input_ao { - mux { - groups = "remote_input_ao"; - function = "remote_input_ao"; - bias-disable; - }; - }; - - i2c_ao_pins: i2c_ao { - mux { - groups = "i2c_sck_ao", - "i2c_sda_ao"; - function = "i2c_ao"; - bias-disable; - }; - }; - - pwm_ao_a_3_pins: pwm_ao_a_3 { - mux { - groups = "pwm_ao_a_3"; - function = "pwm_ao_a"; - bias-disable; - }; - }; - - pwm_ao_a_8_pins: pwm_ao_a_8 { - mux { - groups = "pwm_ao_a_8"; - function = "pwm_ao_a"; - bias-disable; - }; - }; - - pwm_ao_b_pins: pwm_ao_b { - mux { - groups = "pwm_ao_b"; - function = "pwm_ao_b"; - bias-disable; - }; - }; - - pwm_ao_b_6_pins: pwm_ao_b_6 { - mux { - groups = "pwm_ao_b_6"; - function = "pwm_ao_b"; - bias-disable; - }; - }; - - i2s_out_ch23_ao_pins: i2s_out_ch23_ao { - mux { - groups = "i2s_out_ch23_ao"; - function = "i2s_out_ao"; - bias-disable; - }; - }; - - i2s_out_ch45_ao_pins: i2s_out_ch45_ao { - mux { - groups = "i2s_out_ch45_ao"; - function = "i2s_out_ao"; - bias-disable; - }; - }; - - spdif_out_ao_6_pins: spdif_out_ao_6 { - mux { - groups = "spdif_out_ao_6"; - function = "spdif_out_ao"; - bias-disable; - }; - }; - - spdif_out_ao_9_pins: spdif_out_ao_9 { - mux { - groups = "spdif_out_ao_9"; - function = "spdif_out_ao"; - bias-disable; - }; - }; - - ao_cec_pins: ao_cec { - mux { - groups = "ao_cec"; - function = "cec_ao"; - bias-disable; - }; - }; - - ee_cec_pins: ee_cec { - mux { - groups = "ee_cec"; - function = "cec_ao"; - bias-disable; - }; - }; - }; -}; - -&cec_AO { - clocks = <&clkc_AO CLKID_AO_CEC_32K>; - clock-names = "core"; -}; - -&clkc_AO { - compatible = "amlogic,meson-gxl-aoclkc", "amlogic,meson-gx-aoclkc"; - clocks = <&xtal>, <&clkc CLKID_CLK81>; - clock-names = "xtal", "mpeg-clk"; -}; - -&gpio_intc { - compatible = "amlogic,meson-gpio-intc", - "amlogic,meson-gxl-gpio-intc"; - status = "okay"; -}; - -&hdmi_tx { - compatible = "amlogic,meson-gxl-dw-hdmi", "amlogic,meson-gx-dw-hdmi"; - resets = <&reset RESET_HDMITX_CAPB3>, - <&reset RESET_HDMI_SYSTEM_RESET>, - <&reset RESET_HDMI_TX>; - reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy"; - clocks = <&clkc CLKID_HDMI_PCLK>, - <&clkc CLKID_CLK81>, - <&clkc CLKID_GCLK_VENCI_INT0>; - clock-names = "isfr", "iahb", "venci"; -}; - -&sysctrl { - clkc: clock-controller { - compatible = "amlogic,gxl-clkc"; - #clock-cells = <1>; - clocks = <&xtal>; - clock-names = "xtal"; - }; -}; - -&i2c_A { - clocks = <&clkc CLKID_I2C>; -}; - -&i2c_AO { - clocks = <&clkc CLKID_AO_I2C>; -}; - -&i2c_B { - clocks = <&clkc CLKID_I2C>; -}; - -&i2c_C { - clocks = <&clkc CLKID_I2C>; -}; - -&periphs { - pinctrl_periphs: pinctrl@4b0 { - compatible = "amlogic,meson-gxl-periphs-pinctrl"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - gpio: bank@4b0 { - reg = <0x0 0x004b0 0x0 0x28>, - <0x0 0x004e8 0x0 0x14>, - <0x0 0x00520 0x0 0x14>, - <0x0 0x00430 0x0 0x40>; - reg-names = "mux", "pull", "pull-enable", "gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl_periphs 0 0 100>; - }; - - emmc_pins: emmc { - mux-0 { - groups = "emmc_nand_d07", - "emmc_cmd"; - function = "emmc"; - bias-pull-up; - }; - - mux-1 { - groups = "emmc_clk"; - function = "emmc"; - bias-disable; - }; - }; - - emmc_ds_pins: emmc-ds { - mux { - groups = "emmc_ds"; - function = "emmc"; - bias-pull-down; - }; - }; - - emmc_clk_gate_pins: emmc_clk_gate { - mux { - groups = "BOOT_8"; - function = "gpio_periphs"; - bias-pull-down; - }; - }; - - nor_pins: nor { - mux { - groups = "nor_d", - "nor_q", - "nor_c", - "nor_cs"; - function = "nor"; - bias-disable; - }; - }; - - spi_pins: spi-pins { - mux { - groups = "spi_miso", - "spi_mosi", - "spi_sclk"; - function = "spi"; - bias-disable; - }; - }; - - spi_ss0_pins: spi-ss0 { - mux { - groups = "spi_ss0"; - function = "spi"; - bias-disable; - }; - }; - - sdcard_pins: sdcard { - mux-0 { - groups = "sdcard_d0", - "sdcard_d1", - "sdcard_d2", - "sdcard_d3", - "sdcard_cmd"; - function = "sdcard"; - bias-pull-up; - }; - - mux-1 { - groups = "sdcard_clk"; - function = "sdcard"; - bias-disable; - }; - }; - - sdcard_clk_gate_pins: sdcard_clk_gate { - mux { - groups = "CARD_2"; - function = "gpio_periphs"; - bias-pull-down; - }; - }; - - sdio_pins: sdio { - mux-0 { - groups = "sdio_d0", - "sdio_d1", - "sdio_d2", - "sdio_d3", - "sdio_cmd"; - function = "sdio"; - bias-pull-up; - }; - - mux-1 { - groups = "sdio_clk"; - function = "sdio"; - bias-disable; - }; - }; - - sdio_clk_gate_pins: sdio_clk_gate { - mux { - groups = "GPIOX_4"; - function = "gpio_periphs"; - bias-pull-down; - }; - }; - - sdio_irq_pins: sdio_irq { - mux { - groups = "sdio_irq"; - function = "sdio"; - bias-disable; - }; - }; - - uart_a_pins: uart_a { - mux { - groups = "uart_tx_a", - "uart_rx_a"; - function = "uart_a"; - bias-disable; - }; - }; - - uart_a_cts_rts_pins: uart_a_cts_rts { - mux { - groups = "uart_cts_a", - "uart_rts_a"; - function = "uart_a"; - bias-disable; - }; - }; - - uart_b_pins: uart_b { - mux { - groups = "uart_tx_b", - "uart_rx_b"; - function = "uart_b"; - bias-disable; - }; - }; - - uart_b_cts_rts_pins: uart_b_cts_rts { - mux { - groups = "uart_cts_b", - "uart_rts_b"; - function = "uart_b"; - bias-disable; - }; - }; - - uart_c_pins: uart_c { - mux { - groups = "uart_tx_c", - "uart_rx_c"; - function = "uart_c"; - bias-disable; - }; - }; - - uart_c_cts_rts_pins: uart_c_cts_rts { - mux { - groups = "uart_cts_c", - "uart_rts_c"; - function = "uart_c"; - bias-disable; - }; - }; - - i2c_a_pins: i2c_a { - mux { - groups = "i2c_sck_a", - "i2c_sda_a"; - function = "i2c_a"; - bias-disable; - }; - }; - - i2c_b_pins: i2c_b { - mux { - groups = "i2c_sck_b", - "i2c_sda_b"; - function = "i2c_b"; - bias-disable; - }; - }; - - i2c_c_pins: i2c_c { - mux { - groups = "i2c_sck_c", - "i2c_sda_c"; - function = "i2c_c"; - bias-disable; - }; - }; - - i2c_c_dv18_pins: i2c_c_dv18 { - mux { - groups = "i2c_sck_c_dv19", - "i2c_sda_c_dv18"; - function = "i2c_c"; - bias-disable; - }; - }; - - eth_pins: eth_c { - mux { - groups = "eth_mdio", - "eth_mdc", - "eth_clk_rx_clk", - "eth_rx_dv", - "eth_rxd0", - "eth_rxd1", - "eth_rxd2", - "eth_rxd3", - "eth_rgmii_tx_clk", - "eth_tx_en", - "eth_txd0", - "eth_txd1", - "eth_txd2", - "eth_txd3"; - function = "eth"; - bias-disable; - }; - }; - - eth_link_led_pins: eth_link_led { - mux { - groups = "eth_link_led"; - function = "eth_led"; - bias-disable; - }; - }; - - eth_act_led_pins: eth_act_led { - mux { - groups = "eth_act_led"; - function = "eth_led"; - }; - }; - - pwm_a_pins: pwm_a { - mux { - groups = "pwm_a"; - function = "pwm_a"; - bias-disable; - }; - }; - - pwm_b_pins: pwm_b { - mux { - groups = "pwm_b"; - function = "pwm_b"; - bias-disable; - }; - }; - - pwm_c_pins: pwm_c { - mux { - groups = "pwm_c"; - function = "pwm_c"; - bias-disable; - }; - }; - - pwm_d_pins: pwm_d { - mux { - groups = "pwm_d"; - function = "pwm_d"; - bias-disable; - }; - }; - - pwm_e_pins: pwm_e { - mux { - groups = "pwm_e"; - function = "pwm_e"; - bias-disable; - }; - }; - - pwm_f_clk_pins: pwm_f_clk { - mux { - groups = "pwm_f_clk"; - function = "pwm_f"; - bias-disable; - }; - }; - - pwm_f_x_pins: pwm_f_x { - mux { - groups = "pwm_f_x"; - function = "pwm_f"; - bias-disable; - }; - }; - - hdmi_hpd_pins: hdmi_hpd { - mux { - groups = "hdmi_hpd"; - function = "hdmi_hpd"; - bias-disable; - }; - }; - - hdmi_i2c_pins: hdmi_i2c { - mux { - groups = "hdmi_sda", "hdmi_scl"; - function = "hdmi_i2c"; - bias-disable; - }; - }; - - i2s_am_clk_pins: i2s_am_clk { - mux { - groups = "i2s_am_clk"; - function = "i2s_out"; - bias-disable; - }; - }; - - i2s_out_ao_clk_pins: i2s_out_ao_clk { - mux { - groups = "i2s_out_ao_clk"; - function = "i2s_out"; - bias-disable; - }; - }; - - i2s_out_lr_clk_pins: i2s_out_lr_clk { - mux { - groups = "i2s_out_lr_clk"; - function = "i2s_out"; - bias-disable; - }; - }; - - i2s_out_ch01_pins: i2s_out_ch01 { - mux { - groups = "i2s_out_ch01"; - function = "i2s_out"; - bias-disable; - }; - }; - i2sout_ch23_z_pins: i2sout_ch23_z { - mux { - groups = "i2sout_ch23_z"; - function = "i2s_out"; - bias-disable; - }; - }; - - i2sout_ch45_z_pins: i2sout_ch45_z { - mux { - groups = "i2sout_ch45_z"; - function = "i2s_out"; - bias-disable; - }; - }; - - i2sout_ch67_z_pins: i2sout_ch67_z { - mux { - groups = "i2sout_ch67_z"; - function = "i2s_out"; - bias-disable; - }; - }; - - spdif_out_h_pins: spdif_out_ao_h { - mux { - groups = "spdif_out_h"; - function = "spdif_out"; - bias-disable; - }; - }; - }; - - eth-phy-mux { - compatible = "mdio-mux-mmioreg", "mdio-mux"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x55c 0x0 0x4>; - mux-mask = <0xffffffff>; - mdio-parent-bus = <&mdio0>; - - internal_mdio: mdio@e40908ff { - reg = <0xe40908ff>; - #address-cells = <1>; - #size-cells = <0>; - - internal_phy: ethernet-phy@8 { - compatible = "ethernet-phy-id0181.4400"; - interrupts = ; - reg = <8>; - max-speed = <100>; - }; - }; - - external_mdio: mdio@2009087f { - reg = <0x2009087f>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; -}; - -&pwrc_vpu { - resets = <&reset RESET_VIU>, - <&reset RESET_VENC>, - <&reset RESET_VCBUS>, - <&reset RESET_BT656>, - <&reset RESET_DVIN_RESET>, - <&reset RESET_RDMA>, - <&reset RESET_VENCI>, - <&reset RESET_VENCP>, - <&reset RESET_VDAC>, - <&reset RESET_VDI6>, - <&reset RESET_VENCL>, - <&reset RESET_VID_LOCK>; - clocks = <&clkc CLKID_VPU>, - <&clkc CLKID_VAPB>; - clock-names = "vpu", "vapb"; - /* - * VPU clocking is provided by two identical clock paths - * VPU_0 and VPU_1 muxed to a single clock by a glitch - * free mux to safely change frequency while running. - * Same for VAPB but with a final gate after the glitch free mux. - */ - assigned-clocks = <&clkc CLKID_VPU_0_SEL>, - <&clkc CLKID_VPU_0>, - <&clkc CLKID_VPU>, /* Glitch free mux */ - <&clkc CLKID_VAPB_0_SEL>, - <&clkc CLKID_VAPB_0>, - <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */ - assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>, - <0>, /* Do Nothing */ - <&clkc CLKID_VPU_0>, - <&clkc CLKID_FCLK_DIV4>, - <0>, /* Do Nothing */ - <&clkc CLKID_VAPB_0>; - assigned-clock-rates = <0>, /* Do Nothing */ - <666666666>, - <0>, /* Do Nothing */ - <0>, /* Do Nothing */ - <250000000>, - <0>; /* Do Nothing */ -}; - -&saradc { - compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc"; - clocks = <&xtal>, - <&clkc CLKID_SAR_ADC>, - <&clkc CLKID_SAR_ADC_CLK>, - <&clkc CLKID_SAR_ADC_SEL>; - clock-names = "clkin", "core", "adc_clk", "adc_sel"; -}; - -&sd_emmc_a { - clocks = <&clkc CLKID_SD_EMMC_A>, - <&clkc CLKID_SD_EMMC_A_CLK0>, - <&clkc CLKID_FCLK_DIV2>; - clock-names = "core", "clkin0", "clkin1"; - resets = <&reset RESET_SD_EMMC_A>; -}; - -&sd_emmc_b { - clocks = <&clkc CLKID_SD_EMMC_B>, - <&clkc CLKID_SD_EMMC_B_CLK0>, - <&clkc CLKID_FCLK_DIV2>; - clock-names = "core", "clkin0", "clkin1"; - resets = <&reset RESET_SD_EMMC_B>; -}; - -&sd_emmc_c { - clocks = <&clkc CLKID_SD_EMMC_C>, - <&clkc CLKID_SD_EMMC_C_CLK0>, - <&clkc CLKID_FCLK_DIV2>; - clock-names = "core", "clkin0", "clkin1"; - resets = <&reset RESET_SD_EMMC_C>; -}; - -&simplefb_hdmi { - clocks = <&clkc CLKID_HDMI_PCLK>, - <&clkc CLKID_CLK81>, - <&clkc CLKID_GCLK_VENCI_INT0>; -}; - -&spicc { - clocks = <&clkc CLKID_SPICC>; - clock-names = "core"; - resets = <&reset RESET_PERIPHS_SPICC>; - num-cs = <1>; -}; - -&spifc { - clocks = <&clkc CLKID_SPI>; -}; - -&uart_A { - clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; - clock-names = "xtal", "pclk", "baud"; -}; - -&uart_AO { - clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>; - clock-names = "xtal", "pclk", "baud"; -}; - -&uart_AO_B { - clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>; - clock-names = "xtal", "pclk", "baud"; -}; - -&uart_B { - clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; - clock-names = "xtal", "pclk", "baud"; -}; - -&uart_C { - clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>; - clock-names = "xtal", "pclk", "baud"; -}; - -&vpu { - compatible = "amlogic,meson-gxl-vpu", "amlogic,meson-gx-vpu"; - power-domains = <&pwrc_vpu>; -}; - -&vdec { - compatible = "amlogic,gxl-vdec", "amlogic,gx-vdec"; - clocks = <&clkc CLKID_DOS_PARSER>, - <&clkc CLKID_DOS>, - <&clkc CLKID_VDEC_1>, - <&clkc CLKID_VDEC_HEVC>; - clock-names = "dos_parser", "dos", "vdec_1", "vdec_hevc"; - resets = <&reset RESET_PARSER>; - reset-names = "esparser"; -}; diff --git a/sys/gnu/dts/arm64/amlogic/meson-gxm-khadas-vim2.dts b/sys/gnu/dts/arm64/amlogic/meson-gxm-khadas-vim2.dts deleted file mode 100644 index d5dc12878df..00000000000 --- a/sys/gnu/dts/arm64/amlogic/meson-gxm-khadas-vim2.dts +++ /dev/null @@ -1,442 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 Martin Blumenstingl . - * Copyright (c) 2017 BayLibre, SAS - * Author: Neil Armstrong - */ - -/dts-v1/; - -#include -#include - -#include "meson-gxm.dtsi" - -/ { - compatible = "khadas,vim2", "amlogic,s912", "amlogic,meson-gxm"; - model = "Khadas VIM2"; - - aliases { - serial0 = &uart_AO; - serial2 = &uart_AO_B; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; - - adc-keys { - compatible = "adc-keys"; - io-channels = <&saradc 0>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1710000>; - - button-function { - label = "Function"; - linux,code = ; - press-threshold-microvolt = <10000>; - }; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; - }; - - gpio_fan: gpio-fan { - compatible = "gpio-fan"; - gpios = <&gpio GPIODV_14 GPIO_ACTIVE_HIGH - &gpio GPIODV_15 GPIO_ACTIVE_HIGH>; - /* Dummy RPM values since fan is optional */ - gpio-fan,speed-map = <0 0 - 1 1 - 2 2 - 3 3>; - #cooling-cells = <2>; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - poll-interval = <100>; - - power-button { - label = "power"; - linux,code = ; - gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>; - }; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; - }; - - pwmleds { - compatible = "pwm-leds"; - - power { - label = "vim:red:power"; - pwms = <&pwm_AO_ab 1 7812500 0>; - max-brightness = <255>; - linux,default-trigger = "default-on"; - }; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; - clocks = <&wifi32k>; - clock-names = "ext_clock"; - }; - - thermal-zones { - cpu-thermal { - polling-delay-passive = <250>; /* milliseconds */ - polling-delay = <1000>; /* milliseconds */ - - thermal-sensors = <&scpi_sensors 0>; - - trips { - cpu_alert0: cpu-alert0 { - temperature = <70000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "active"; - }; - - cpu_alert1: cpu-alert1 { - temperature = <80000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu_alert0>; - cooling-device = <&gpio_fan THERMAL_NO_LIMIT 1>; - }; - - map1 { - trip = <&cpu_alert1>; - cooling-device = <&gpio_fan 2 THERMAL_NO_LIMIT>, - <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - }; - - hdmi_5v: regulator-hdmi-5v { - compatible = "regulator-fixed"; - - regulator-name = "HDMI_5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - gpio = <&gpio GPIOH_3 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - }; - - vcc_3v3: regulator-vcc_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vddio_ao18: regulator-vddio_ao18 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vddio_boot: regulator-vddio_boot { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_BOOT"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vddao_3v3: regulator-vddao_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - wifi32k: wifi32k { - compatible = "pwm-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ - }; -}; - -&cec_AO { - status = "okay"; - pinctrl-0 = <&ao_cec_pins>; - pinctrl-names = "default"; - hdmi-phandle = <&hdmi_tx>; -}; - -&cpu0 { - #cooling-cells = <2>; -}; - -&cpu1 { - #cooling-cells = <2>; -}; - -&cpu2 { - #cooling-cells = <2>; -}; - -&cpu3 { - #cooling-cells = <2>; -}; - -&cpu4 { - #cooling-cells = <2>; -}; - -&cpu5 { - #cooling-cells = <2>; -}; - -&cpu6 { - #cooling-cells = <2>; -}; - -&cpu7 { - #cooling-cells = <2>; -}; - -ðmac { - pinctrl-0 = <ð_pins>; - pinctrl-names = "default"; - - /* Select external PHY by default */ - phy-handle = <&external_phy>; - - amlogic,tx-delay-ns = <2>; - - /* External PHY is in RGMII */ - phy-mode = "rgmii"; - - status = "okay"; -}; - -&external_mdio { - external_phy: ethernet-phy@0 { - /* Realtek RTL8211F (0x001cc916) */ - reg = <0>; - - reset-assert-us = <10000>; - reset-deassert-us = <30000>; - reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; - - interrupt-parent = <&gpio_intc>; - /* MAC_INTR on GPIOZ_15 */ - interrupts = <25 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&hdmi_tx { - status = "okay"; - pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; - pinctrl-names = "default"; - hdmi-supply = <&hdmi_5v>; -}; - -&hdmi_tx_tmds_port { - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; -}; - -&i2c_A { - status = "okay"; - pinctrl-0 = <&i2c_a_pins>; - pinctrl-names = "default"; -}; - -&i2c_B { - status = "okay"; - pinctrl-0 = <&i2c_b_pins>; - pinctrl-names = "default"; - - rtc: rtc@51 { - /* has to be enabled manually when a battery is connected: */ - status = "disabled"; - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "xin32k"; - }; -}; - -&ir { - status = "okay"; - pinctrl-0 = <&remote_input_ao_pins>; - pinctrl-names = "default"; - linux,rc-map-name = "rc-khadas"; -}; - -&pwm_AO_ab { - status = "okay"; - pinctrl-0 = <&pwm_ao_a_3_pins>, <&pwm_ao_b_pins>; - pinctrl-names = "default"; - clocks = <&clkc CLKID_FCLK_DIV4>; - clock-names = "clkin0"; -}; - -&pwm_ef { - status = "okay"; - pinctrl-0 = <&pwm_e_pins>, <&pwm_f_clk_pins>; - pinctrl-names = "default"; - clocks = <&clkc CLKID_FCLK_DIV4>; - clock-names = "clkin0"; -}; - -&sd_emmc_a { - status = "okay"; - pinctrl-0 = <&sdio_pins>; - pinctrl-1 = <&sdio_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - #address-cells = <1>; - #size-cells = <0>; - - bus-width = <4>; - max-frequency = <60000000>; - - non-removable; - disable-wp; - - /* WiFi firmware requires power to be kept while in suspend */ - keep-power-in-suspend; - - mmc-pwrseq = <&sdio_pwrseq>; - - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddio_boot>; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - }; -}; - -/* SD card */ -&sd_emmc_b { - status = "okay"; - pinctrl-0 = <&sdcard_pins>; - pinctrl-1 = <&sdcard_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <50000000>; - disable-wp; - - cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; - - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddio_boot>; -}; - -/* eMMC */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - max-frequency = <200000000>; - non-removable; - disable-wp; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&vddio_boot>; -}; - -/* - * EMMC_DS pin is shared between SPI NOR CS and eMMC Data Strobe - * Remove emmc_ds_pins from sd_emmc_c pinctrl-0 then spifc can be enabled - */ -&spifc { - status = "disabled"; - pinctrl-0 = <&nor_pins>; - pinctrl-names = "default"; - - w25q32: spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "winbond,w25q16", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <3000000>; - }; -}; - -/* This one is connected to the Bluetooth module */ -&uart_A { - status = "okay"; - pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; - pinctrl-names = "default"; - uart-has-rtscts; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; - max-speed = <2000000>; - clocks = <&wifi32k>; - clock-names = "lpo"; - }; -}; - -/* This is brought out on the Linux_RX (18) and Linux_TX (19) pins: */ -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -/* This is brought out on the UART_RX_AO_B (15) and UART_TX_AO_B (16) pins: */ -&uart_AO_B { - status = "okay"; - pinctrl-0 = <&uart_ao_b_pins>; - pinctrl-names = "default"; -}; - -&saradc { - status = "okay"; - vref-supply = <&vddio_ao18>; -}; - -&usb0 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/amlogic/meson-gxm-nexbox-a1.dts b/sys/gnu/dts/arm64/amlogic/meson-gxm-nexbox-a1.dts deleted file mode 100644 index c2bd4dbbf38..00000000000 --- a/sys/gnu/dts/arm64/amlogic/meson-gxm-nexbox-a1.dts +++ /dev/null @@ -1,184 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 BayLibre, SAS. - * Author: Neil Armstrong - * - * Copyright (c) 2016 Endless Computers, Inc. - * Author: Carlo Caione - */ - -/dts-v1/; - -#include "meson-gxm.dtsi" - -/ { - compatible = "nexbox,a1", "amlogic,s912", "amlogic,meson-gxm"; - model = "NEXBOX A1"; - - aliases { - serial0 = &uart_AO; - ethernet0 = ðmac; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; - - vddio_boot: regulator-vddio-boot { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_BOOT"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vddao_3v3: regulator-vddao-3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vcc_3v3: regulator-vcc-3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; - }; - - cvbs-connector { - compatible = "composite-video-connector"; - - port { - cvbs_connector_in: endpoint { - remote-endpoint = <&cvbs_vdac_out>; - }; - }; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; - }; -}; - -&cec_AO { - status = "okay"; - pinctrl-0 = <&ao_cec_pins>; - pinctrl-names = "default"; - hdmi-phandle = <&hdmi_tx>; -}; - -&cvbs_vdac_port { - cvbs_vdac_out: endpoint { - remote-endpoint = <&cvbs_connector_in>; - }; -}; - -ðmac { - status = "okay"; - - pinctrl-0 = <ð_pins>; - pinctrl-names = "default"; - - /* Select external PHY by default */ - phy-handle = <&external_phy>; - - amlogic,tx-delay-ns = <2>; - - /* External PHY is in RGMII */ - phy-mode = "rgmii"; -}; - -&external_mdio { - external_phy: ethernet-phy@0 { - /* Realtek RTL8211F (0x001cc916) */ - reg = <0>; - max-speed = <1000>; - - reset-assert-us = <10000>; - reset-deassert-us = <30000>; - reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; - }; -}; - -&hdmi_tx { - status = "okay"; - pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; - pinctrl-names = "default"; -}; - -&hdmi_tx_tmds_port { - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; -}; - -&ir { - status = "okay"; - pinctrl-0 = <&remote_input_ao_pins>; - pinctrl-names = "default"; -}; - -/* SD card */ -&sd_emmc_b { - status = "okay"; - pinctrl-0 = <&sdcard_pins>; - pinctrl-1 = <&sdcard_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <50000000>; - disable-wp; - - cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; - - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddio_boot>; -}; - -/* eMMC */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - max-frequency = <200000000>; - non-removable; - disable-wp; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&vddio_boot>; -}; - -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -&usb0 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/amlogic/meson-gxm-q200.dts b/sys/gnu/dts/arm64/amlogic/meson-gxm-q200.dts deleted file mode 100644 index ea45ae0c71b..00000000000 --- a/sys/gnu/dts/arm64/amlogic/meson-gxm-q200.dts +++ /dev/null @@ -1,81 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Endless Computers, Inc. - * Author: Carlo Caione - */ - -/dts-v1/; - -#include - -#include "meson-gxm.dtsi" -#include "meson-gx-p23x-q20x.dtsi" - -/ { - compatible = "amlogic,q200", "amlogic,s912", "amlogic,meson-gxm"; - model = "Amlogic Meson GXM (S912) Q200 Development Board"; - - adc-keys { - compatible = "adc-keys"; - io-channels = <&saradc 0>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1710000>; - - button-function { - label = "Update"; - linux,code = ; - press-threshold-microvolt = <10000>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <100>; - - button@0 { - label = "power"; - linux,code = ; - gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>; - }; - }; -}; - -/* Q200 has exclusive choice between internal or external PHY */ -ðmac { - pinctrl-0 = <ð_pins>; - pinctrl-names = "default"; - - /* Select external PHY by default */ - phy-handle = <&external_phy>; - - amlogic,tx-delay-ns = <2>; - - /* External PHY is in RGMII */ - phy-mode = "rgmii"; -}; - -&external_mdio { - external_phy: ethernet-phy@0 { - /* Realtek RTL8211F (0x001cc916) */ - reg = <0>; - max-speed = <1000>; - - /* External PHY reset is shared with internal PHY Led signal */ - reset-assert-us = <10000>; - reset-deassert-us = <30000>; - reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; - - interrupt-parent = <&gpio_intc>; - /* MAC_INTR on GPIOZ_15 */ - interrupts = <25 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&sd_emmc_a { - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - }; -}; diff --git a/sys/gnu/dts/arm64/amlogic/meson-gxm-q201.dts b/sys/gnu/dts/arm64/amlogic/meson-gxm-q201.dts deleted file mode 100644 index d02b80d7737..00000000000 --- a/sys/gnu/dts/arm64/amlogic/meson-gxm-q201.dts +++ /dev/null @@ -1,28 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Endless Computers, Inc. - * Author: Carlo Caione - */ - -/dts-v1/; - -#include "meson-gxm.dtsi" -#include "meson-gx-p23x-q20x.dtsi" - -/ { - compatible = "amlogic,q201", "amlogic,s912", "amlogic,meson-gxm"; - model = "Amlogic Meson GXM (S912) Q201 Development Board"; -}; - -/* Q201 has only internal PHY port */ -ðmac { - phy-mode = "rmii"; - phy-handle = <&internal_phy>; -}; - -&sd_emmc_a { - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - }; -}; diff --git a/sys/gnu/dts/arm64/amlogic/meson-gxm-rbox-pro.dts b/sys/gnu/dts/arm64/amlogic/meson-gxm-rbox-pro.dts deleted file mode 100644 index 420a88e9a19..00000000000 --- a/sys/gnu/dts/arm64/amlogic/meson-gxm-rbox-pro.dts +++ /dev/null @@ -1,205 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016-2017 Andreas Färber - * - * Based on nexbox-a1: - * - * Copyright (c) 2016 BayLibre, SAS. - * Author: Neil Armstrong - * - * Copyright (c) 2016 Endless Computers, Inc. - * Author: Carlo Caione - */ - -/dts-v1/; - -#include "meson-gxm.dtsi" - -/ { - compatible = "kingnovel,r-box-pro", "amlogic,s912", "amlogic,meson-gxm"; - model = "R-Box Pro"; - - aliases { - serial0 = &uart_AO; - ethernet0 = ðmac; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; /* 2 GiB or 3 GiB */ - }; - - leds { - compatible = "gpio-leds"; - - blue { - label = "rbox-pro:blue:on"; - gpios = <&gpio_ao GPIOAO_9 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - red { - label = "rbox-pro:red:standby"; - gpios = <&gpio GPIODV_28 GPIO_ACTIVE_HIGH>; - default-state = "off"; - retain-state-suspended; - panic-indicator; - }; - }; - - vddio_boot: regulator-vddio-boot { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_BOOT"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vddao_3v3: regulator-vddao-3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vcc_3v3: regulator-vcc-3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; - }; - - wifi32k: wifi32k { - compatible = "pwm-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; - clocks = <&wifi32k>; - clock-names = "ext_clock"; - }; -}; - -ðmac { - status = "okay"; - - pinctrl-0 = <ð_pins>; - pinctrl-names = "default"; - - /* Select external PHY by default */ - phy-handle = <&external_phy>; - - amlogic,tx-delay-ns = <2>; - - /* External PHY is in RGMII */ - phy-mode = "rgmii"; -}; - -&external_mdio { - external_phy: ethernet-phy@0 { - /* Realtek RTL8211F (0x001cc916) */ - reg = <0>; - max-speed = <1000>; - - reset-assert-us = <10000>; - reset-deassert-us = <30000>; - reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; - }; -}; - -&ir { - status = "okay"; - pinctrl-0 = <&remote_input_ao_pins>; - pinctrl-names = "default"; -}; - -&pwm_ef { - status = "okay"; - pinctrl-0 = <&pwm_e_pins>; - pinctrl-names = "default"; - clocks = <&clkc CLKID_FCLK_DIV4>; - clock-names = "clkin0"; -}; - -/* Wireless SDIO Module */ -&sd_emmc_a { - status = "okay"; - pinctrl-0 = <&sdio_pins>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <50000000>; - - non-removable; - disable-wp; - - /* WiFi firmware requires power to be kept while in suspend */ - keep-power-in-suspend; - - mmc-pwrseq = <&sdio_pwrseq>; - - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddio_boot>; - - brcmf: brcmf@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - }; -}; - -/* SD card */ -&sd_emmc_b { - status = "okay"; - pinctrl-0 = <&sdcard_pins>; - pinctrl-names = "default"; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <50000000>; - disable-wp; - - cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; - - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddio_boot>; -}; - -/* eMMC */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; - pinctrl-names = "default"; - - bus-width = <8>; - cap-mmc-highspeed; - max-frequency = <200000000>; - non-removable; - disable-wp; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&vddio_boot>; -}; - -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; diff --git a/sys/gnu/dts/arm64/amlogic/meson-gxm-s912-libretech-pc.dts b/sys/gnu/dts/arm64/amlogic/meson-gxm-s912-libretech-pc.dts deleted file mode 100644 index 444c249863c..00000000000 --- a/sys/gnu/dts/arm64/amlogic/meson-gxm-s912-libretech-pc.dts +++ /dev/null @@ -1,62 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2019 BayLibre SAS. All rights reserved. - * Author: Jerome Brunet - */ - -/dts-v1/; - -#include "meson-gxm.dtsi" -#include "meson-gx-libretech-pc.dtsi" - -/ { - compatible = "libretech,aml-s912-pc", "amlogic,s912", - "amlogic,meson-gxm"; - model = "Libre Computer AML-S912-PC"; - - typec2_vbus: regulator-typec2_vbus { - compatible = "regulator-fixed"; - regulator-name = "TYPEC2_VBUS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v>; - - gpio = <&gpio GPIODV_1 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&pinctrl_periphs { - /* - * Make sure the irq pin of the TYPE C controller is not driven - * by the SoC. - */ - fusb302_irq_pins: fusb302_irq { - mux { - groups = "GPIODV_0"; - function = "gpio_periphs"; - bias-pull-up; - output-disable; - }; - }; -}; - -&i2c_C { - fusb302@22 { - compatible = "fcs,fusb302"; - reg = <0x22>; - - pinctrl-0 = <&fusb302_irq_pins>; - pinctrl-names = "default"; - interrupt-parent = <&gpio_intc>; - interrupts = <59 IRQ_TYPE_LEVEL_LOW>; - - vbus-supply = <&typec2_vbus>; - - status = "okay"; - }; -}; - -&usb2_phy2 { - phy-supply = <&typec2_vbus>; -}; diff --git a/sys/gnu/dts/arm64/amlogic/meson-gxm-vega-s96.dts b/sys/gnu/dts/arm64/amlogic/meson-gxm-vega-s96.dts deleted file mode 100644 index 0bdf51d041a..00000000000 --- a/sys/gnu/dts/arm64/amlogic/meson-gxm-vega-s96.dts +++ /dev/null @@ -1,41 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 BayLibre, SAS. - * Author: Neil Armstrong - * Copyright (c) 2017 Oleg - */ - -/dts-v1/; - -#include "meson-gxm.dtsi" -#include "meson-gx-p23x-q20x.dtsi" - -/ { - compatible = "tronsmart,vega-s96", "amlogic,s912", "amlogic,meson-gxm"; - model = "Tronsmart Vega S96"; - -}; - -ðmac { - pinctrl-0 = <ð_pins>; - pinctrl-names = "default"; - - /* Select external PHY by default */ - phy-handle = <&external_phy>; - - amlogic,tx-delay-ns = <2>; - - /* External PHY is in RGMII */ - phy-mode = "rgmii"; -}; - -&external_mdio { - external_phy: ethernet-phy@0 { - /* Realtek RTL8211F (0x001cc916) */ - reg = <0>; - }; -}; - -&ir { - linux,rc-map-name = "rc-vega-s9x"; -}; diff --git a/sys/gnu/dts/arm64/amlogic/meson-gxm.dtsi b/sys/gnu/dts/arm64/amlogic/meson-gxm.dtsi deleted file mode 100644 index 5ff64a0d2dc..00000000000 --- a/sys/gnu/dts/arm64/amlogic/meson-gxm.dtsi +++ /dev/null @@ -1,150 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Endless Computers, Inc. - * Author: Carlo Caione - */ - -#include "meson-gxl.dtsi" - -/ { - compatible = "amlogic,meson-gxm"; - - cpus { - cpu-map { - cluster0 { - core0 { - cpu = <&cpu0>; - }; - core1 { - cpu = <&cpu1>; - }; - core2 { - cpu = <&cpu2>; - }; - core3 { - cpu = <&cpu3>; - }; - }; - - cluster1 { - core0 { - cpu = <&cpu4>; - }; - core1 { - cpu = <&cpu5>; - }; - core2 { - cpu = <&cpu6>; - }; - core3 { - cpu = <&cpu7>; - }; - }; - }; - - cpu4: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x100>; - enable-method = "psci"; - next-level-cache = <&l2>; - clocks = <&scpi_dvfs 1>; - }; - - cpu5: cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x101>; - enable-method = "psci"; - next-level-cache = <&l2>; - clocks = <&scpi_dvfs 1>; - }; - - cpu6: cpu@102 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x102>; - enable-method = "psci"; - next-level-cache = <&l2>; - clocks = <&scpi_dvfs 1>; - }; - - cpu7: cpu@103 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x103>; - enable-method = "psci"; - next-level-cache = <&l2>; - clocks = <&scpi_dvfs 1>; - }; - }; -}; - -&apb { - usb2_phy2: phy@78040 { - compatible = "amlogic,meson-gxl-usb2-phy"; - #phy-cells = <0>; - reg = <0x0 0x78040 0x0 0x20>; - clocks = <&clkc CLKID_USB>; - clock-names = "phy"; - resets = <&reset RESET_USB_OTG>; - reset-names = "phy"; - status = "okay"; - }; - - mali: gpu@c0000 { - compatible = "amlogic,meson-gxm-mali", "arm,mali-t820"; - reg = <0x0 0xc0000 0x0 0x40000>; - interrupt-parent = <&gic>; - interrupts = , - , - ; - interrupt-names = "job", "mmu", "gpu"; - clocks = <&clkc CLKID_MALI>; - resets = <&reset RESET_MALI_CAPB3>, <&reset RESET_MALI>; - - /* - * Mali clocking is provided by two identical clock paths - * MALI_0 and MALI_1 muxed to a single clock by a glitch - * free mux to safely change frequency while running. - */ - assigned-clocks = <&clkc CLKID_MALI_0_SEL>, - <&clkc CLKID_MALI_0>, - <&clkc CLKID_MALI>; /* Glitch free mux */ - assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>, - <0>, /* Do Nothing */ - <&clkc CLKID_MALI_0>; - assigned-clock-rates = <0>, /* Do Nothing */ - <666666666>, - <0>; /* Do Nothing */ - }; -}; - -&clkc_AO { - compatible = "amlogic,meson-gxm-aoclkc", "amlogic,meson-gx-aoclkc"; -}; - -&saradc { - compatible = "amlogic,meson-gxm-saradc", "amlogic,meson-saradc"; -}; - -&scpi_dvfs { - clock-indices = <0 1>; - clock-output-names = "vbig", "vlittle"; -}; - -&vpu { - compatible = "amlogic,meson-gxm-vpu", "amlogic,meson-gx-vpu"; -}; - -&hdmi_tx { - compatible = "amlogic,meson-gxm-dw-hdmi", "amlogic,meson-gx-dw-hdmi"; -}; - -&dwc3 { - phys = <&usb3_phy>, <&usb2_phy0>, <&usb2_phy1>, <&usb2_phy2>; -}; - -&vdec { - compatible = "amlogic,gxm-vdec", "amlogic,gx-vdec"; -}; diff --git a/sys/gnu/dts/arm64/amlogic/meson-khadas-vim3.dtsi b/sys/gnu/dts/arm64/amlogic/meson-khadas-vim3.dtsi deleted file mode 100644 index 90815fa25ec..00000000000 --- a/sys/gnu/dts/arm64/amlogic/meson-khadas-vim3.dtsi +++ /dev/null @@ -1,367 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 BayLibre, SAS - * Author: Neil Armstrong - * Copyright (c) 2019 Christian Hewitt - */ - -#include -#include - -/ { - model = "Khadas VIM3"; - - aliases { - serial0 = &uart_AO; - ethernet0 = ðmac; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; - - adc-keys { - compatible = "adc-keys"; - io-channels = <&saradc 2>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1710000>; - - button-function { - label = "Function"; - linux,code = ; - press-threshold-microvolt = <10000>; - }; - }; - - leds { - compatible = "gpio-leds"; - - white { - label = "vim3:white:sys"; - gpios = <&gpio_ao GPIOAO_4 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - }; - - red { - label = "vim3:red"; - gpios = <&gpio_expander 5 GPIO_ACTIVE_LOW>; - }; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - poll-interval = <100>; - - power-button { - label = "power"; - linux,code = ; - gpios = <&gpio_ao GPIOAO_7 GPIO_ACTIVE_LOW>; - }; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; - clocks = <&wifi32k>; - clock-names = "ext_clock"; - }; - - dc_in: regulator-dc_in { - compatible = "regulator-fixed"; - regulator-name = "DC_IN"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - vcc_5v: regulator-vcc_5v { - compatible = "regulator-fixed"; - regulator-name = "VCC_5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&dc_in>; - - gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>; - enable-active-high; - }; - - vcc_1v8: regulator-vcc_1v8 { - compatible = "regulator-fixed"; - regulator-name = "VCC_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_3v3>; - regulator-always-on; - }; - - vcc_3v3: regulator-vcc_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vsys_3v3>; - regulator-always-on; - /* FIXME: actually controlled by VDDCPU_B_EN */ - }; - - vddao_1v8: regulator-vddao_1v8 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vsys_3v3>; - regulator-always-on; - }; - - emmc_1v8: regulator-emmc_1v8 { - compatible = "regulator-fixed"; - regulator-name = "EMMC_AO1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_3v3>; - regulator-always-on; - }; - - vsys_3v3: regulator-vsys_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VSYS_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&dc_in>; - regulator-always-on; - }; - - usb_pwr: regulator-usb_pwr { - compatible = "regulator-fixed"; - regulator-name = "USB_PWR"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc_5v>; - - gpio = <&gpio GPIOA_6 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; - }; - - wifi32k: wifi32k { - compatible = "pwm-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ - }; -}; - -&cec_AO { - pinctrl-0 = <&cec_ao_a_h_pins>; - pinctrl-names = "default"; - status = "disabled"; - hdmi-phandle = <&hdmi_tx>; -}; - -&cecb_AO { - pinctrl-0 = <&cec_ao_b_h_pins>; - pinctrl-names = "default"; - status = "okay"; - hdmi-phandle = <&hdmi_tx>; -}; - -&ext_mdio { - external_phy: ethernet-phy@0 { - /* Realtek RTL8211F (0x001cc916) */ - reg = <0>; - max-speed = <1000>; - - interrupt-parent = <&gpio_intc>; - /* MAC_INTR on GPIOZ_14 */ - interrupts = <26 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -ðmac { - pinctrl-0 = <ð_pins>, <ð_rgmii_pins>; - pinctrl-names = "default"; - status = "okay"; - phy-mode = "rgmii"; - phy-handle = <&external_phy>; - amlogic,tx-delay-ns = <2>; -}; - -&hdmi_tx { - status = "okay"; - pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>; - pinctrl-names = "default"; - hdmi-supply = <&vcc_5v>; -}; - -&hdmi_tx_tmds_port { - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; -}; - -&i2c_AO { - status = "okay"; - pinctrl-0 = <&i2c_ao_sck_pins>, <&i2c_ao_sda_pins>; - pinctrl-names = "default"; - - gpio_expander: gpio-controller@20 { - compatible = "ti,tca6408"; - reg = <0x20>; - vcc-supply = <&vcc_3v3>; - gpio-controller; - #gpio-cells = <2>; - }; - - rtc@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; - }; -}; - -&ir { - status = "okay"; - pinctrl-0 = <&remote_input_ao_pins>; - pinctrl-names = "default"; - linux,rc-map-name = "rc-khadas"; -}; - -&pcie { - reset-gpios = <&gpio GPIOA_8 GPIO_ACTIVE_LOW>; -}; - -&pwm_ef { - status = "okay"; - pinctrl-0 = <&pwm_e_pins>; - pinctrl-names = "default"; -}; - -&saradc { - status = "okay"; - vref-supply = <&vddao_1v8>; -}; - -/* SDIO */ -&sd_emmc_a { - status = "okay"; - pinctrl-0 = <&sdio_pins>; - pinctrl-1 = <&sdio_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - #address-cells = <1>; - #size-cells = <0>; - - bus-width = <4>; - cap-sd-highspeed; - sd-uhs-sdr50; - max-frequency = <100000000>; - - non-removable; - disable-wp; - - /* WiFi firmware requires power to be kept while in suspend */ - keep-power-in-suspend; - - mmc-pwrseq = <&sdio_pwrseq>; - - vmmc-supply = <&vsys_3v3>; - vqmmc-supply = <&vddao_1v8>; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - }; -}; - -/* SD card */ -&sd_emmc_b { - status = "okay"; - pinctrl-0 = <&sdcard_c_pins>; - pinctrl-1 = <&sdcard_clk_gate_c_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <50000000>; - disable-wp; - - cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>; - vmmc-supply = <&vsys_3v3>; - vqmmc-supply = <&vsys_3v3>; -}; - -/* eMMC */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - max-frequency = <200000000>; - disable-wp; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&emmc_1v8>; -}; - -&uart_A { - status = "okay"; - pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; - pinctrl-names = "default"; - uart-has-rtscts; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; - max-speed = <2000000>; - clocks = <&wifi32k>; - clock-names = "lpo"; - }; -}; - -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -&usb2_phy0 { - phy-supply = <&dc_in>; -}; - -&usb2_phy1 { - phy-supply = <&usb_pwr>; -}; - -&usb3_pcie_phy { - phy-supply = <&usb_pwr>; -}; - -&usb { - status = "okay"; - dr_mode = "peripheral"; -}; diff --git a/sys/gnu/dts/arm64/amlogic/meson-sm1-khadas-vim3l.dts b/sys/gnu/dts/arm64/amlogic/meson-sm1-khadas-vim3l.dts deleted file mode 100644 index dbbf29a0dbf..00000000000 --- a/sys/gnu/dts/arm64/amlogic/meson-sm1-khadas-vim3l.dts +++ /dev/null @@ -1,95 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 BayLibre, SAS - * Author: Neil Armstrong - */ - -/dts-v1/; - -#include "meson-sm1.dtsi" -#include "meson-khadas-vim3.dtsi" - -/ { - compatible = "khadas,vim3l", "amlogic,sm1"; - model = "Khadas VIM3L"; - - vddcpu: regulator-vddcpu { - /* - * Silergy SY8030DEC Regulator. - */ - compatible = "pwm-regulator"; - - regulator-name = "VDDCPU"; - regulator-min-microvolt = <690000>; - regulator-max-microvolt = <1050000>; - - vin-supply = <&vsys_3v3>; - - pwms = <&pwm_AO_cd 1 1250 0>; - pwm-dutycycle-range = <100 0>; - - regulator-boot-on; - regulator-always-on; - }; -}; - -&cpu0 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cpu1 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU1_CLK>; - clock-latency = <50000>; -}; - -&cpu2 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU2_CLK>; - clock-latency = <50000>; -}; - -&cpu3 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU3_CLK>; - clock-latency = <50000>; -}; - -&pwm_AO_cd { - pinctrl-0 = <&pwm_ao_d_e_pins>; - pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin1"; - status = "okay"; -}; - -/* - * The VIM3 on-board MCU can mux the PCIe/USB3.0 shared differential - * lines using a FUSB340TMX USB 3.1 SuperSpeed Data Switch between - * an USB3.0 Type A connector and a M.2 Key M slot. - * The PHY driving these differential lines is shared between - * the USB3.0 controller and the PCIe Controller, thus only - * a single controller can use it. - * If the MCU is configured to mux the PCIe/USB3.0 differential lines - * to the M.2 Key M slot, uncomment the following block to disable - * USB3.0 from the USB Complex and enable the PCIe controller. - * The End User is not expected to uncomment the following except for - * testing purposes, but instead rely on the firmware/bootloader to - * update these nodes accordingly if PCIe mode is selected by the MCU. - */ -/* -&pcie { - status = "okay"; -}; - -&usb { - phys = <&usb2_phy0>, <&usb2_phy1>; - phy-names = "usb2-phy0", "usb2-phy1"; -}; - */ diff --git a/sys/gnu/dts/arm64/amlogic/meson-sm1-sei610.dts b/sys/gnu/dts/arm64/amlogic/meson-sm1-sei610.dts deleted file mode 100644 index cb1b48f5b8b..00000000000 --- a/sys/gnu/dts/arm64/amlogic/meson-sm1-sei610.dts +++ /dev/null @@ -1,616 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 BayLibre SAS. All rights reserved. - */ - -/dts-v1/; - -#include "meson-sm1.dtsi" -#include -#include -#include -#include - -/ { - compatible = "seirobotics,sei610", "amlogic,sm1"; - model = "SEI Robotics SEI610"; - - aliases { - serial0 = &uart_AO; - ethernet0 = ðmac; - }; - - mono_dac: audio-codec-0 { - compatible = "maxim,max98357a"; - #sound-dai-cells = <0>; - sound-name-prefix = "U16"; - sdmode-gpios = <&gpio GPIOX_8 GPIO_ACTIVE_HIGH>; - }; - - dmics: audio-codec-1 { - #sound-dai-cells = <0>; - compatible = "dmic-codec"; - num-channels = <2>; - wakeup-delay-ms = <50>; - status = "okay"; - sound-name-prefix = "MIC"; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - key1 { - label = "A"; - linux,code = ; - gpios = <&gpio GPIOH_6 GPIO_ACTIVE_LOW>; - interrupt-parent = <&gpio_intc>; - interrupts = <34 IRQ_TYPE_EDGE_BOTH>; - }; - - key2 { - label = "B"; - linux,code = ; - gpios = <&gpio GPIOH_7 GPIO_ACTIVE_LOW>; - interrupt-parent = <&gpio_intc>; - interrupts = <35 IRQ_TYPE_EDGE_BOTH>; - }; - - key3 { - label = "C"; - linux,code = ; - gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>; - interrupt-parent = <&gpio_intc>; - interrupts = <2 IRQ_TYPE_EDGE_BOTH>; - }; - - mic_mute { - label = "MicMute"; - linux,code = ; - linux,input-type = ; - gpios = <&gpio_ao GPIOE_2 GPIO_ACTIVE_LOW>; - interrupt-parent = <&gpio_intc>; - interrupts = <99 IRQ_TYPE_EDGE_BOTH>; - }; - - power_key { - label = "PowerKey"; - linux,code = ; - gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_LOW>; - interrupt-parent = <&gpio_intc>; - interrupts = <3 IRQ_TYPE_EDGE_BOTH>; - }; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - bluetooth { - label = "sei610:blue:bt"; - gpios = <&gpio GPIOC_7 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; - default-state = "off"; - }; - }; - - pwmleds { - compatible = "pwm-leds"; - - power { - label = "sei610:red:power"; - pwms = <&pwm_AO_ab 0 30518 0>; - max-brightness = <255>; - linux,default-trigger = "default-on"; - active-low; - }; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x40000000>; - }; - - ao_5v: regulator-ao_5v { - compatible = "regulator-fixed"; - regulator-name = "AO_5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&dc_in>; - regulator-always-on; - }; - - dc_in: regulator-dc_in { - compatible = "regulator-fixed"; - regulator-name = "DC_IN"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - emmc_1v8: regulator-emmc_1v8 { - compatible = "regulator-fixed"; - regulator-name = "EMMC_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vddao_3v3>; - regulator-always-on; - }; - - vddao_3v3: regulator-vddao_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&dc_in>; - regulator-always-on; - }; - - /* Used by Tuner, RGB Led & IR Emitter LED array */ - vddao_3v3_t: regulator-vddao_3v3_t { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3_T"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vddao_3v3>; - gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>; - enable-active-low; - regulator-always-on; - }; - - vddcpu: regulator-vddcpu { - /* - * SY8120B1ABC DC/DC Regulator. - */ - compatible = "pwm-regulator"; - - regulator-name = "VDDCPU"; - regulator-min-microvolt = <690000>; - regulator-max-microvolt = <1050000>; - - vin-supply = <&dc_in>; - - pwms = <&pwm_AO_cd 1 1500 0>; - pwm-dutycycle-range = <100 0>; - - regulator-boot-on; - regulator-always-on; - }; - - vddio_ao1v8: regulator-vddio_ao1v8 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vddao_3v3>; - regulator-always-on; - }; - - reserved-memory { - /* TEE Reserved Memory */ - bl32_reserved: bl32@5000000 { - reg = <0x0 0x05300000 0x0 0x2000000>; - no-map; - }; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; - clocks = <&wifi32k>; - clock-names = "ext_clock"; - }; - - sound { - compatible = "amlogic,axg-sound-card"; - model = "SM1-SEI610"; - audio-aux-devs = <&tdmout_a>, <&tdmout_b>, - <&tdmin_a>, <&tdmin_b>; - audio-routing = "TDMOUT_A IN 0", "FRDDR_A OUT 0", - "TDMOUT_A IN 1", "FRDDR_B OUT 0", - "TDMOUT_A IN 2", "FRDDR_C OUT 0", - "TDM_A Playback", "TDMOUT_A OUT", - "TDMOUT_B IN 0", "FRDDR_A OUT 1", - "TDMOUT_B IN 1", "FRDDR_B OUT 1", - "TDMOUT_B IN 2", "FRDDR_C OUT 1", - "TDM_B Playback", "TDMOUT_B OUT", - "TODDR_A IN 4", "PDM Capture", - "TODDR_B IN 4", "PDM Capture", - "TODDR_C IN 4", "PDM Capture", - "TDMIN_A IN 0", "TDM_A Capture", - "TDMIN_A IN 3", "TDM_A Loopback", - "TDMIN_B IN 0", "TDM_A Capture", - "TDMIN_B IN 3", "TDM_A Loopback", - "TDMIN_A IN 1", "TDM_B Capture", - "TDMIN_A IN 4", "TDM_B Loopback", - "TDMIN_B IN 1", "TDM_B Capture", - "TDMIN_B IN 4", "TDM_B Loopback", - "TODDR_A IN 0", "TDMIN_A OUT", - "TODDR_B IN 0", "TDMIN_A OUT", - "TODDR_C IN 0", "TDMIN_A OUT", - "TODDR_A IN 1", "TDMIN_B OUT", - "TODDR_B IN 1", "TDMIN_B OUT", - "TODDR_C IN 1", "TDMIN_B OUT"; - - assigned-clocks = <&clkc CLKID_MPLL2>, - <&clkc CLKID_MPLL0>, - <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; - assigned-clock-rates = <294912000>, - <270950400>, - <393216000>; - status = "okay"; - - dai-link-0 { - sound-dai = <&frddr_a>; - }; - - dai-link-1 { - sound-dai = <&frddr_b>; - }; - - dai-link-2 { - sound-dai = <&frddr_c>; - }; - - dai-link-3 { - sound-dai = <&toddr_a>; - }; - - dai-link-4 { - sound-dai = <&toddr_b>; - }; - - dai-link-5 { - sound-dai = <&toddr_c>; - }; - - /* internal speaker interface */ - dai-link-6 { - sound-dai = <&tdmif_a>; - dai-format = "i2s"; - dai-tdm-slot-tx-mask-0 = <1 1>; - mclk-fs = <256>; - - codec-0 { - sound-dai = <&mono_dac>; - }; - - codec-1 { - sound-dai = <&tohdmitx TOHDMITX_I2S_IN_A>; - }; - }; - - /* 8ch hdmi interface */ - dai-link-7 { - sound-dai = <&tdmif_b>; - dai-format = "i2s"; - dai-tdm-slot-tx-mask-0 = <1 1>; - dai-tdm-slot-tx-mask-1 = <1 1>; - dai-tdm-slot-tx-mask-2 = <1 1>; - dai-tdm-slot-tx-mask-3 = <1 1>; - mclk-fs = <256>; - - codec { - sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>; - }; - }; - - /* internal digital mics */ - dai-link-8 { - sound-dai = <&pdm>; - - codec { - sound-dai = <&dmics>; - }; - }; - - /* hdmi glue */ - dai-link-9 { - sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; - - codec { - sound-dai = <&hdmi_tx>; - }; - }; - }; - - wifi32k: wifi32k { - compatible = "pwm-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ - }; -}; - -&arb { - status = "okay"; -}; - -&cec_AO { - pinctrl-0 = <&cec_ao_a_h_pins>; - pinctrl-names = "default"; - status = "disabled"; - hdmi-phandle = <&hdmi_tx>; -}; - -&cecb_AO { - pinctrl-0 = <&cec_ao_b_h_pins>; - pinctrl-names = "default"; - status = "okay"; - hdmi-phandle = <&hdmi_tx>; -}; - -&clkc_audio { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cpu1 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU1_CLK>; - clock-latency = <50000>; -}; - -&cpu2 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU2_CLK>; - clock-latency = <50000>; -}; - -&cpu3 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU3_CLK>; - clock-latency = <50000>; -}; - -ðmac { - status = "okay"; - phy-handle = <&internal_ephy>; - phy-mode = "rmii"; -}; - -&frddr_a { - status = "okay"; -}; - -&frddr_b { - status = "okay"; -}; - -&frddr_c { - status = "okay"; -}; - -&hdmi_tx { - status = "okay"; - pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>; - pinctrl-names = "default"; -}; - -&hdmi_tx_tmds_port { - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; -}; - -&i2c3 { - status = "okay"; - pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>; - pinctrl-names = "default"; -}; - -&ir { - status = "okay"; - pinctrl-0 = <&remote_input_ao_pins>; - pinctrl-names = "default"; -}; - -&pdm { - pinctrl-0 = <&pdm_din0_z_pins>, <&pdm_dclk_z_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&pwm_AO_ab { - status = "okay"; - pinctrl-0 = <&pwm_ao_a_pins>; - pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin0"; -}; - -&pwm_AO_cd { - pinctrl-0 = <&pwm_ao_d_e_pins>; - pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin1"; - status = "okay"; -}; - -&pwm_ef { - status = "okay"; - pinctrl-0 = <&pwm_e_pins>; - pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin0"; -}; - -&saradc { - status = "okay"; - vref-supply = <&vddio_ao1v8>; -}; - -/* SDIO */ -&sd_emmc_a { - status = "okay"; - pinctrl-0 = <&sdio_pins>; - pinctrl-1 = <&sdio_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - #address-cells = <1>; - #size-cells = <0>; - - bus-width = <4>; - cap-sd-highspeed; - sd-uhs-sdr50; - max-frequency = <100000000>; - - non-removable; - disable-wp; - - /* WiFi firmware requires power to be kept while in suspend */ - keep-power-in-suspend; - - mmc-pwrseq = <&sdio_pwrseq>; - - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddio_ao1v8>; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - }; -}; - -/* SD card */ -&sd_emmc_b { - status = "okay"; - pinctrl-0 = <&sdcard_c_pins>; - pinctrl-1 = <&sdcard_clk_gate_c_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <50000000>; - disable-wp; - - cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>; - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddao_3v3>; -}; - -/* eMMC */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - max-frequency = <200000000>; - non-removable; - disable-wp; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&emmc_1v8>; -}; - -&tdmif_a { - pinctrl-0 = <&tdm_a_dout0_pins>, <&tdm_a_fs_pins>, <&tdm_a_sclk_pins>; - pinctrl-names = "default"; - status = "okay"; - - assigned-clocks = <&clkc_audio AUD_CLKID_TDM_SCLK_PAD0>, - <&clkc_audio AUD_CLKID_TDM_LRCLK_PAD0>; - assigned-clock-parents = <&clkc_audio AUD_CLKID_MST_A_SCLK>, - <&clkc_audio AUD_CLKID_MST_A_LRCLK>; - assigned-clock-rates = <0>, <0>; -}; - -&tdmif_b { - status = "okay"; -}; - -&tdmin_a { - status = "okay"; -}; - -&tdmin_b { - status = "okay"; -}; - -&tdmout_a { - status = "okay"; -}; - -&tdmout_b { - status = "okay"; -}; - -&toddr_a { - status = "okay"; -}; - -&toddr_b { - status = "okay"; -}; - -&toddr_c { - status = "okay"; -}; - -&tohdmitx { - status = "okay"; -}; - -&uart_A { - status = "okay"; - pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; - pinctrl-names = "default"; - uart-has-rtscts; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - interrupt-parent = <&gpio_intc>; - interrupts = <95 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "host-wakeup"; - shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; - max-speed = <2000000>; - clocks = <&wifi32k>; - clock-names = "lpo"; - vbat-supply = <&vddao_3v3>; - vddio-supply = <&vddio_ao1v8>; - }; -}; - -/* Exposed via the on-board USB to Serial FT232RL IC */ -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -&usb { - status = "okay"; - dr_mode = "otg"; -}; diff --git a/sys/gnu/dts/arm64/amlogic/meson-sm1.dtsi b/sys/gnu/dts/arm64/amlogic/meson-sm1.dtsi deleted file mode 100644 index d847a3fcbc8..00000000000 --- a/sys/gnu/dts/arm64/amlogic/meson-sm1.dtsi +++ /dev/null @@ -1,503 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 BayLibre, SAS - * Author: Neil Armstrong - */ - -#include "meson-g12-common.dtsi" -#include -#include -#include -#include - -/ { - compatible = "amlogic,sm1"; - - tdmif_a: audio-controller-0 { - compatible = "amlogic,axg-tdm-iface"; - #sound-dai-cells = <0>; - sound-name-prefix = "TDM_A"; - clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>, - <&clkc_audio AUD_CLKID_MST_A_SCLK>, - <&clkc_audio AUD_CLKID_MST_A_LRCLK>; - clock-names = "mclk", "sclk", "lrclk"; - status = "disabled"; - }; - - tdmif_b: audio-controller-1 { - compatible = "amlogic,axg-tdm-iface"; - #sound-dai-cells = <0>; - sound-name-prefix = "TDM_B"; - clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>, - <&clkc_audio AUD_CLKID_MST_B_SCLK>, - <&clkc_audio AUD_CLKID_MST_B_LRCLK>; - clock-names = "mclk", "sclk", "lrclk"; - status = "disabled"; - }; - - tdmif_c: audio-controller-2 { - compatible = "amlogic,axg-tdm-iface"; - #sound-dai-cells = <0>; - sound-name-prefix = "TDM_C"; - clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>, - <&clkc_audio AUD_CLKID_MST_C_SCLK>, - <&clkc_audio AUD_CLKID_MST_C_LRCLK>; - clock-names = "mclk", "sclk", "lrclk"; - status = "disabled"; - }; - - cpus { - #address-cells = <0x2>; - #size-cells = <0x0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x0 0x0>; - enable-method = "psci"; - next-level-cache = <&l2>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x0 0x1>; - enable-method = "psci"; - next-level-cache = <&l2>; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x0 0x2>; - enable-method = "psci"; - next-level-cache = <&l2>; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x0 0x3>; - enable-method = "psci"; - next-level-cache = <&l2>; - }; - - l2: l2-cache0 { - compatible = "cache"; - }; - }; - - cpu_opp_table: opp-table { - compatible = "operating-points-v2"; - opp-shared; - - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - opp-microvolt = <730000>; - }; - - opp-250000000 { - opp-hz = /bits/ 64 <250000000>; - opp-microvolt = <730000>; - }; - - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <730000>; - }; - - opp-667000000 { - opp-hz = /bits/ 64 <666666666>; - opp-microvolt = <750000>; - }; - - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <770000>; - }; - - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <780000>; - }; - - opp-1404000000 { - opp-hz = /bits/ 64 <1404000000>; - opp-microvolt = <790000>; - }; - - opp-1512000000 { - opp-hz = /bits/ 64 <1500000000>; - opp-microvolt = <800000>; - }; - - opp-1608000000 { - opp-hz = /bits/ 64 <1608000000>; - opp-microvolt = <810000>; - }; - - opp-1704000000 { - opp-hz = /bits/ 64 <1704000000>; - opp-microvolt = <850000>; - }; - - opp-1800000000 { - opp-hz = /bits/ 64 <1800000000>; - opp-microvolt = <900000>; - }; - - opp-1908000000 { - opp-hz = /bits/ 64 <1908000000>; - opp-microvolt = <950000>; - }; - }; -}; - -&apb { - audio: bus@60000 { - compatible = "simple-bus"; - reg = <0x0 0x60000 0x0 0x1000>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0x60000 0x0 0x1000>; - - clkc_audio: clock-controller@0 { - status = "disabled"; - compatible = "amlogic,sm1-audio-clkc"; - reg = <0x0 0x0 0x0 0xb4>; - #clock-cells = <1>; - #reset-cells = <1>; - - clocks = <&clkc CLKID_AUDIO>, - <&clkc CLKID_MPLL0>, - <&clkc CLKID_MPLL1>, - <&clkc CLKID_MPLL2>, - <&clkc CLKID_MPLL3>, - <&clkc CLKID_HIFI_PLL>, - <&clkc CLKID_FCLK_DIV3>, - <&clkc CLKID_FCLK_DIV4>, - <&clkc CLKID_FCLK_DIV5>; - clock-names = "pclk", - "mst_in0", - "mst_in1", - "mst_in2", - "mst_in3", - "mst_in4", - "mst_in5", - "mst_in6", - "mst_in7"; - - resets = <&reset RESET_AUDIO>; - }; - - toddr_a: audio-controller@100 { - compatible = "amlogic,sm1-toddr", - "amlogic,axg-toddr"; - reg = <0x0 0x100 0x0 0x2c>; - #sound-dai-cells = <0>; - sound-name-prefix = "TODDR_A"; - interrupts = ; - clocks = <&clkc_audio AUD_CLKID_TODDR_A>; - resets = <&arb AXG_ARB_TODDR_A>, - <&clkc_audio AUD_RESET_TODDR_A>; - reset-names = "arb", "rst"; - amlogic,fifo-depth = <8192>; - status = "disabled"; - }; - - toddr_b: audio-controller@140 { - compatible = "amlogic,sm1-toddr", - "amlogic,axg-toddr"; - reg = <0x0 0x140 0x0 0x2c>; - #sound-dai-cells = <0>; - sound-name-prefix = "TODDR_B"; - interrupts = ; - clocks = <&clkc_audio AUD_CLKID_TODDR_B>; - resets = <&arb AXG_ARB_TODDR_B>, - <&clkc_audio AUD_RESET_TODDR_B>; - reset-names = "arb", "rst"; - amlogic,fifo-depth = <256>; - status = "disabled"; - }; - - toddr_c: audio-controller@180 { - compatible = "amlogic,sm1-toddr", - "amlogic,axg-toddr"; - reg = <0x0 0x180 0x0 0x2c>; - #sound-dai-cells = <0>; - sound-name-prefix = "TODDR_C"; - interrupts = ; - clocks = <&clkc_audio AUD_CLKID_TODDR_C>; - resets = <&arb AXG_ARB_TODDR_C>, - <&clkc_audio AUD_RESET_TODDR_C>; - reset-names = "arb", "rst"; - amlogic,fifo-depth = <256>; - status = "disabled"; - }; - - frddr_a: audio-controller@1c0 { - compatible = "amlogic,sm1-frddr", - "amlogic,axg-frddr"; - reg = <0x0 0x1c0 0x0 0x2c>; - #sound-dai-cells = <0>; - sound-name-prefix = "FRDDR_A"; - interrupts = ; - clocks = <&clkc_audio AUD_CLKID_FRDDR_A>; - resets = <&arb AXG_ARB_FRDDR_A>, - <&clkc_audio AUD_RESET_FRDDR_A>; - reset-names = "arb", "rst"; - amlogic,fifo-depth = <512>; - status = "disabled"; - }; - - frddr_b: audio-controller@200 { - compatible = "amlogic,sm1-frddr", - "amlogic,axg-frddr"; - reg = <0x0 0x200 0x0 0x2c>; - #sound-dai-cells = <0>; - sound-name-prefix = "FRDDR_B"; - interrupts = ; - clocks = <&clkc_audio AUD_CLKID_FRDDR_B>; - resets = <&arb AXG_ARB_FRDDR_B>, - <&clkc_audio AUD_RESET_FRDDR_B>; - reset-names = "arb", "rst"; - amlogic,fifo-depth = <256>; - status = "disabled"; - }; - - frddr_c: audio-controller@240 { - compatible = "amlogic,sm1-frddr", - "amlogic,axg-frddr"; - reg = <0x0 0x240 0x0 0x2c>; - #sound-dai-cells = <0>; - sound-name-prefix = "FRDDR_C"; - interrupts = ; - clocks = <&clkc_audio AUD_CLKID_FRDDR_C>; - resets = <&arb AXG_ARB_FRDDR_C>, - <&clkc_audio AUD_RESET_FRDDR_C>; - reset-names = "arb", "rst"; - amlogic,fifo-depth = <256>; - status = "disabled"; - }; - - arb: reset-controller@280 { - status = "disabled"; - compatible = "amlogic,meson-sm1-audio-arb"; - reg = <0x0 0x280 0x0 0x4>; - #reset-cells = <1>; - clocks = <&clkc_audio AUD_CLKID_DDR_ARB>; - }; - - tdmin_a: audio-controller@300 { - compatible = "amlogic,sm1-tdmin", - "amlogic,axg-tdmin"; - reg = <0x0 0x300 0x0 0x40>; - sound-name-prefix = "TDMIN_A"; - resets = <&clkc_audio AUD_RESET_TDMIN_A>; - clocks = <&clkc_audio AUD_CLKID_TDMIN_A>, - <&clkc_audio AUD_CLKID_TDMIN_A_SCLK>, - <&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>, - <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>, - <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>; - clock-names = "pclk", "sclk", "sclk_sel", - "lrclk", "lrclk_sel"; - status = "disabled"; - }; - - tdmin_b: audio-controller@340 { - compatible = "amlogic,sm1-tdmin", - "amlogic,axg-tdmin"; - reg = <0x0 0x340 0x0 0x40>; - sound-name-prefix = "TDMIN_B"; - resets = <&clkc_audio AUD_RESET_TDMIN_B>; - clocks = <&clkc_audio AUD_CLKID_TDMIN_B>, - <&clkc_audio AUD_CLKID_TDMIN_B_SCLK>, - <&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>, - <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>, - <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>; - clock-names = "pclk", "sclk", "sclk_sel", - "lrclk", "lrclk_sel"; - status = "disabled"; - }; - - tdmin_c: audio-controller@380 { - compatible = "amlogic,sm1-tdmin", - "amlogic,axg-tdmin"; - reg = <0x0 0x380 0x0 0x40>; - sound-name-prefix = "TDMIN_C"; - resets = <&clkc_audio AUD_RESET_TDMIN_C>; - clocks = <&clkc_audio AUD_CLKID_TDMIN_C>, - <&clkc_audio AUD_CLKID_TDMIN_C_SCLK>, - <&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>, - <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>, - <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>; - clock-names = "pclk", "sclk", "sclk_sel", - "lrclk", "lrclk_sel"; - status = "disabled"; - }; - - tdmin_lb: audio-controller@3c0 { - compatible = "amlogic,sm1-tdmin", - "amlogic,axg-tdmin"; - reg = <0x0 0x3c0 0x0 0x40>; - sound-name-prefix = "TDMIN_LB"; - resets = <&clkc_audio AUD_RESET_TDMIN_LB>; - clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>, - <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>, - <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>, - <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>, - <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>; - clock-names = "pclk", "sclk", "sclk_sel", - "lrclk", "lrclk_sel"; - status = "disabled"; - }; - - tdmout_a: audio-controller@500 { - compatible = "amlogic,sm1-tdmout"; - reg = <0x0 0x500 0x0 0x40>; - sound-name-prefix = "TDMOUT_A"; - resets = <&clkc_audio AUD_RESET_TDMOUT_A>; - clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>, - <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>, - <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>, - <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>, - <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>; - clock-names = "pclk", "sclk", "sclk_sel", - "lrclk", "lrclk_sel"; - status = "disabled"; - }; - - tdmout_b: audio-controller@540 { - compatible = "amlogic,sm1-tdmout"; - reg = <0x0 0x540 0x0 0x40>; - sound-name-prefix = "TDMOUT_B"; - resets = <&clkc_audio AUD_RESET_TDMOUT_B>; - clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>, - <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>, - <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>, - <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>, - <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>; - clock-names = "pclk", "sclk", "sclk_sel", - "lrclk", "lrclk_sel"; - status = "disabled"; - }; - - tdmout_c: audio-controller@580 { - compatible = "amlogic,sm1-tdmout"; - reg = <0x0 0x580 0x0 0x40>; - sound-name-prefix = "TDMOUT_C"; - resets = <&clkc_audio AUD_RESET_TDMOUT_C>; - clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>, - <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>, - <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>, - <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>, - <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>; - clock-names = "pclk", "sclk", "sclk_sel", - "lrclk", "lrclk_sel"; - status = "disabled"; - }; - - tohdmitx: audio-controller@744 { - compatible = "amlogic,sm1-tohdmitx", - "amlogic,g12a-tohdmitx"; - reg = <0x0 0x744 0x0 0x4>; - #sound-dai-cells = <1>; - sound-name-prefix = "TOHDMITX"; - resets = <&clkc_audio AUD_RESET_TOHDMITX>; - status = "disabled"; - }; - - toddr_d: audio-controller@840 { - compatible = "amlogic,sm1-toddr", - "amlogic,axg-toddr"; - reg = <0x0 0x840 0x0 0x2c>; - #sound-dai-cells = <0>; - sound-name-prefix = "TODDR_D"; - interrupts = ; - clocks = <&clkc_audio AUD_CLKID_TODDR_D>; - resets = <&arb AXG_ARB_TODDR_D>, - <&clkc_audio AUD_RESET_TODDR_D>; - reset-names = "arb", "rst"; - amlogic,fifo-depth = <256>; - status = "disabled"; - }; - - frddr_d: audio-controller@880 { - compatible = "amlogic,sm1-frddr", - "amlogic,axg-frddr"; - reg = <0x0 0x880 0x0 0x2c>; - #sound-dai-cells = <0>; - sound-name-prefix = "FRDDR_D"; - interrupts = ; - clocks = <&clkc_audio AUD_CLKID_FRDDR_D>; - resets = <&arb AXG_ARB_FRDDR_D>, - <&clkc_audio AUD_RESET_FRDDR_D>; - reset-names = "arb", "rst"; - amlogic,fifo-depth = <256>; - status = "disabled"; - }; - }; - - pdm: audio-controller@61000 { - compatible = "amlogic,sm1-pdm", - "amlogic,axg-pdm"; - reg = <0x0 0x61000 0x0 0x34>; - #sound-dai-cells = <0>; - sound-name-prefix = "PDM"; - clocks = <&clkc_audio AUD_CLKID_PDM>, - <&clkc_audio AUD_CLKID_PDM_DCLK>, - <&clkc_audio AUD_CLKID_PDM_SYSCLK>; - clock-names = "pclk", "dclk", "sysclk"; - status = "disabled"; - }; -}; - -&cecb_AO { - compatible = "amlogic,meson-sm1-ao-cec"; -}; - -&clk_msr { - compatible = "amlogic,meson-sm1-clk-measure"; -}; - - -&clkc { - compatible = "amlogic,sm1-clkc"; -}; - -ðmac { - power-domains = <&pwrc PWRC_SM1_ETH_ID>; -}; - -&gpio_intc { - compatible = "amlogic,meson-sm1-gpio-intc", - "amlogic,meson-gpio-intc"; -}; - -&pcie { - power-domains = <&pwrc PWRC_SM1_PCIE_ID>; -}; - -&pwrc { - compatible = "amlogic,meson-sm1-pwrc"; -}; - -&simplefb_cvbs { - power-domains = <&pwrc PWRC_SM1_VPU_ID>; -}; - -&simplefb_hdmi { - power-domains = <&pwrc PWRC_SM1_VPU_ID>; -}; - -&vdec { - compatible = "amlogic,sm1-vdec"; -}; - -&vpu { - power-domains = <&pwrc PWRC_SM1_VPU_ID>; -}; - -&usb { - power-domains = <&pwrc PWRC_SM1_USB_ID>; -}; diff --git a/sys/gnu/dts/arm64/apm/apm-merlin.dts b/sys/gnu/dts/arm64/apm/apm-merlin.dts deleted file mode 100644 index 217d7728b63..00000000000 --- a/sys/gnu/dts/arm64/apm/apm-merlin.dts +++ /dev/null @@ -1,87 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * dts file for AppliedMicro (APM) Merlin Board - * - * Copyright (C) 2015, Applied Micro Circuits Corporation - */ - -/dts-v1/; - -/include/ "apm-shadowcat.dtsi" - -/ { - model = "APM X-Gene Merlin board"; - compatible = "apm,merlin", "apm,xgene-shadowcat"; - - chosen { }; - - memory { - device_type = "memory"; - reg = < 0x1 0x00000000 0x0 0x80000000 >; - }; - - gpio-keys { - compatible = "gpio-keys"; - button@1 { - label = "POWER"; - linux,code = <116>; - linux,input-type = <0x1>; - interrupt-parent = <&sbgpio>; - interrupts = <0x0 0x1>; - }; - }; - - poweroff_mbox: poweroff_mbox@10548000 { - compatible = "syscon"; - reg = <0x0 0x10548000 0x0 0x30>; - }; - - poweroff: poweroff@10548010 { - compatible = "syscon-poweroff"; - regmap = <&poweroff_mbox>; - offset = <0x10>; - mask = <0x1>; - }; -}; - -&serial0 { - status = "ok"; -}; - -&sata1 { - status = "ok"; -}; - -&sata2 { - status = "ok"; -}; - -&sata3 { - status = "ok"; -}; - -&sgenet0 { - status = "ok"; -}; - -&xgenet1 { - status = "ok"; -}; - -&mmc0 { - status = "ok"; -}; - -&i2c4 { - rtc68: rtc@68 { - compatible = "dallas,ds1337"; - reg = <0x68>; - status = "ok"; - }; -}; - -&mdio { - sgenet0phy: phy@0 { - reg = <0x0>; - }; -}; diff --git a/sys/gnu/dts/arm64/apm/apm-mustang.dts b/sys/gnu/dts/arm64/apm/apm-mustang.dts deleted file mode 100644 index e927811ade2..00000000000 --- a/sys/gnu/dts/arm64/apm/apm-mustang.dts +++ /dev/null @@ -1,90 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * dts file for AppliedMicro (APM) Mustang Board - * - * Copyright (C) 2013, Applied Micro Circuits Corporation - */ - -/dts-v1/; - -/include/ "apm-storm.dtsi" - -/ { - model = "APM X-Gene Mustang board"; - compatible = "apm,mustang", "apm,xgene-storm"; - - chosen { }; - - memory { - device_type = "memory"; - reg = < 0x1 0x00000000 0x0 0x80000000 >; /* Updated by bootloader */ - }; - - gpio-keys { - compatible = "gpio-keys"; - button@1 { - label = "POWER"; - linux,code = <116>; - linux,input-type = <0x1>; - interrupt-parent = <&sbgpio>; - interrupts = <0x5 0x1>; - }; - }; - - poweroff_mbox: poweroff_mbox@10548000 { - compatible = "syscon"; - reg = <0x0 0x10548000 0x0 0x30>; - }; - - poweroff: poweroff@10548010 { - compatible = "syscon-poweroff"; - regmap = <&poweroff_mbox>; - offset = <0x10>; - mask = <0x1>; - }; -}; - -&pcie0clk { - status = "ok"; -}; - -&pcie0 { - status = "ok"; -}; - -&serial0 { - status = "ok"; -}; - -&menet { - status = "ok"; -}; - -&sgenet0 { - status = "ok"; -}; - -&sgenet1 { - status = "ok"; -}; - -&xgenet { - status = "ok"; - rxlos-gpios = <&sbgpio 12 1>; -}; - -&mmc0 { - status = "ok"; -}; - -&mdio { - menet0phy: phy@3 { - reg = <0x3>; - }; - sgenet0phy: phy@4 { - reg = <0x4>; - }; - sgenet1phy: phy@5 { - reg = <0x5>; - }; -}; diff --git a/sys/gnu/dts/arm64/apm/apm-shadowcat.dtsi b/sys/gnu/dts/arm64/apm/apm-shadowcat.dtsi deleted file mode 100644 index 3feb1881bbc..00000000000 --- a/sys/gnu/dts/arm64/apm/apm-shadowcat.dtsi +++ /dev/null @@ -1,818 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * dts file for AppliedMicro (APM) X-Gene Shadowcat SOC - * - * Copyright (C) 2015, Applied Micro Circuits Corporation - */ - -/ { - compatible = "apm,xgene-shadowcat"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "apm,strega"; - reg = <0x0 0x000>; - enable-method = "spin-table"; - cpu-release-addr = <0x1 0x0000fff8>; - next-level-cache = <&xgene_L2_0>; - #clock-cells = <1>; - clocks = <&pmd0clk 0>; - }; - cpu@1 { - device_type = "cpu"; - compatible = "apm,strega"; - reg = <0x0 0x001>; - enable-method = "spin-table"; - cpu-release-addr = <0x1 0x0000fff8>; - next-level-cache = <&xgene_L2_0>; - #clock-cells = <1>; - clocks = <&pmd0clk 0>; - }; - cpu@100 { - device_type = "cpu"; - compatible = "apm,strega"; - reg = <0x0 0x100>; - enable-method = "spin-table"; - cpu-release-addr = <0x1 0x0000fff8>; - next-level-cache = <&xgene_L2_1>; - #clock-cells = <1>; - clocks = <&pmd1clk 0>; - }; - cpu@101 { - device_type = "cpu"; - compatible = "apm,strega"; - reg = <0x0 0x101>; - enable-method = "spin-table"; - cpu-release-addr = <0x1 0x0000fff8>; - next-level-cache = <&xgene_L2_1>; - #clock-cells = <1>; - clocks = <&pmd1clk 0>; - }; - cpu@200 { - device_type = "cpu"; - compatible = "apm,strega"; - reg = <0x0 0x200>; - enable-method = "spin-table"; - cpu-release-addr = <0x1 0x0000fff8>; - next-level-cache = <&xgene_L2_2>; - #clock-cells = <1>; - clocks = <&pmd2clk 0>; - }; - cpu@201 { - device_type = "cpu"; - compatible = "apm,strega"; - reg = <0x0 0x201>; - enable-method = "spin-table"; - cpu-release-addr = <0x1 0x0000fff8>; - next-level-cache = <&xgene_L2_2>; - #clock-cells = <1>; - clocks = <&pmd2clk 0>; - }; - cpu@300 { - device_type = "cpu"; - compatible = "apm,strega"; - reg = <0x0 0x300>; - enable-method = "spin-table"; - cpu-release-addr = <0x1 0x0000fff8>; - next-level-cache = <&xgene_L2_3>; - #clock-cells = <1>; - clocks = <&pmd3clk 0>; - }; - cpu@301 { - device_type = "cpu"; - compatible = "apm,strega"; - reg = <0x0 0x301>; - enable-method = "spin-table"; - cpu-release-addr = <0x1 0x0000fff8>; - next-level-cache = <&xgene_L2_3>; - #clock-cells = <1>; - clocks = <&pmd3clk 0>; - }; - xgene_L2_0: l2-cache-0 { - compatible = "cache"; - }; - xgene_L2_1: l2-cache-1 { - compatible = "cache"; - }; - xgene_L2_2: l2-cache-2 { - compatible = "cache"; - }; - xgene_L2_3: l2-cache-3 { - compatible = "cache"; - }; - }; - - gic: interrupt-controller@78090000 { - compatible = "arm,cortex-a15-gic"; - #interrupt-cells = <3>; - #address-cells = <2>; - #size-cells = <2>; - interrupt-controller; - interrupts = <1 9 0xf04>; /* GIC Maintenence IRQ */ - ranges = <0 0 0 0x79000000 0x0 0x800000>; /* MSI Range */ - reg = <0x0 0x78090000 0x0 0x10000>, /* GIC Dist */ - <0x0 0x780a0000 0x0 0x20000>, /* GIC CPU */ - <0x0 0x780c0000 0x0 0x10000>, /* GIC VCPU Control */ - <0x0 0x780e0000 0x0 0x20000>; /* GIC VCPU */ - v2m0: v2m@0 { - compatible = "arm,gic-v2m-frame"; - msi-controller; - reg = <0x0 0x0 0x0 0x1000>; - }; - v2m1: v2m@10000 { - compatible = "arm,gic-v2m-frame"; - msi-controller; - reg = <0x0 0x10000 0x0 0x1000>; - }; - v2m2: v2m@20000 { - compatible = "arm,gic-v2m-frame"; - msi-controller; - reg = <0x0 0x20000 0x0 0x1000>; - }; - v2m3: v2m@30000 { - compatible = "arm,gic-v2m-frame"; - msi-controller; - reg = <0x0 0x30000 0x0 0x1000>; - }; - v2m4: v2m@40000 { - compatible = "arm,gic-v2m-frame"; - msi-controller; - reg = <0x0 0x40000 0x0 0x1000>; - }; - v2m5: v2m@50000 { - compatible = "arm,gic-v2m-frame"; - msi-controller; - reg = <0x0 0x50000 0x0 0x1000>; - }; - v2m6: v2m@60000 { - compatible = "arm,gic-v2m-frame"; - msi-controller; - reg = <0x0 0x60000 0x0 0x1000>; - }; - v2m7: v2m@70000 { - compatible = "arm,gic-v2m-frame"; - msi-controller; - reg = <0x0 0x70000 0x0 0x1000>; - }; - v2m8: v2m@80000 { - compatible = "arm,gic-v2m-frame"; - msi-controller; - reg = <0x0 0x80000 0x0 0x1000>; - }; - v2m9: v2m@90000 { - compatible = "arm,gic-v2m-frame"; - msi-controller; - reg = <0x0 0x90000 0x0 0x1000>; - }; - v2m10: v2m@a0000 { - compatible = "arm,gic-v2m-frame"; - msi-controller; - reg = <0x0 0xa0000 0x0 0x1000>; - }; - v2m11: v2m@b0000 { - compatible = "arm,gic-v2m-frame"; - msi-controller; - reg = <0x0 0xb0000 0x0 0x1000>; - }; - v2m12: v2m@c0000 { - compatible = "arm,gic-v2m-frame"; - msi-controller; - reg = <0x0 0xc0000 0x0 0x1000>; - }; - v2m13: v2m@d0000 { - compatible = "arm,gic-v2m-frame"; - msi-controller; - reg = <0x0 0xd0000 0x0 0x1000>; - }; - v2m14: v2m@e0000 { - compatible = "arm,gic-v2m-frame"; - msi-controller; - reg = <0x0 0xe0000 0x0 0x1000>; - }; - v2m15: v2m@f0000 { - compatible = "arm,gic-v2m-frame"; - msi-controller; - reg = <0x0 0xf0000 0x0 0x1000>; - }; - }; - - pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = <1 12 0xff04>; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = <1 0 0xff08>, /* Secure Phys IRQ */ - <1 13 0xff08>, /* Non-secure Phys IRQ */ - <1 14 0xff08>, /* Virt IRQ */ - <1 15 0xff08>; /* Hyp IRQ */ - clock-frequency = <50000000>; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - clocks { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - refclk: refclk { - compatible = "fixed-clock"; - #clock-cells = <1>; - clock-frequency = <100000000>; - clock-output-names = "refclk"; - }; - - pmdpll: pmdpll@170000f0 { - compatible = "apm,xgene-pcppll-v2-clock"; - #clock-cells = <1>; - clocks = <&refclk 0>; - reg = <0x0 0x170000f0 0x0 0x10>; - clock-output-names = "pmdpll"; - }; - - pmd0clk: pmd0clk@7e200200 { - compatible = "apm,xgene-pmd-clock"; - #clock-cells = <1>; - clocks = <&pmdpll 0>; - reg = <0x0 0x7e200200 0x0 0x10>; - clock-output-names = "pmd0clk"; - }; - - pmd1clk: pmd1clk@7e200210 { - compatible = "apm,xgene-pmd-clock"; - #clock-cells = <1>; - clocks = <&pmdpll 0>; - reg = <0x0 0x7e200210 0x0 0x10>; - clock-output-names = "pmd1clk"; - }; - - pmd2clk: pmd2clk@7e200220 { - compatible = "apm,xgene-pmd-clock"; - #clock-cells = <1>; - clocks = <&pmdpll 0>; - reg = <0x0 0x7e200220 0x0 0x10>; - clock-output-names = "pmd2clk"; - }; - - pmd3clk: pmd3clk@7e200230 { - compatible = "apm,xgene-pmd-clock"; - #clock-cells = <1>; - clocks = <&pmdpll 0>; - reg = <0x0 0x7e200230 0x0 0x10>; - clock-output-names = "pmd3clk"; - }; - - socpll: socpll@17000120 { - compatible = "apm,xgene-socpll-v2-clock"; - #clock-cells = <1>; - clocks = <&refclk 0>; - reg = <0x0 0x17000120 0x0 0x1000>; - clock-output-names = "socpll"; - }; - - socplldiv2: socplldiv2 { - compatible = "fixed-factor-clock"; - #clock-cells = <1>; - clocks = <&socpll 0>; - clock-mult = <1>; - clock-div = <2>; - clock-output-names = "socplldiv2"; - }; - - ahbclk: ahbclk@17000000 { - compatible = "apm,xgene-device-clock"; - #clock-cells = <1>; - clocks = <&socplldiv2 0>; - reg = <0x0 0x17000000 0x0 0x2000>; - reg-names = "div-reg"; - divider-offset = <0x164>; - divider-width = <0x5>; - divider-shift = <0x0>; - clock-output-names = "ahbclk"; - }; - - sbapbclk: sbapbclk@1704c000 { - compatible = "apm,xgene-device-clock"; - #clock-cells = <1>; - clocks = <&ahbclk 0>; - reg = <0x0 0x1704c000 0x0 0x2000>; - reg-names = "div-reg"; - divider-offset = <0x10>; - divider-width = <0x2>; - divider-shift = <0x0>; - clock-output-names = "sbapbclk"; - }; - - sdioclk: sdioclk@1f2ac000 { - compatible = "apm,xgene-device-clock"; - #clock-cells = <1>; - clocks = <&socplldiv2 0>; - reg = <0x0 0x1f2ac000 0x0 0x1000 - 0x0 0x17000000 0x0 0x2000>; - reg-names = "csr-reg", "div-reg"; - csr-offset = <0x0>; - csr-mask = <0x2>; - enable-offset = <0x8>; - enable-mask = <0x2>; - divider-offset = <0x178>; - divider-width = <0x8>; - divider-shift = <0x0>; - clock-output-names = "sdioclk"; - }; - - pcie0clk: pcie0clk@1f2bc000 { - compatible = "apm,xgene-device-clock"; - #clock-cells = <1>; - clocks = <&socplldiv2 0>; - reg = <0x0 0x1f2bc000 0x0 0x1000>; - reg-names = "csr-reg"; - clock-output-names = "pcie0clk"; - }; - - pcie1clk: pcie1clk@1f2cc000 { - compatible = "apm,xgene-device-clock"; - #clock-cells = <1>; - clocks = <&socplldiv2 0>; - reg = <0x0 0x1f2cc000 0x0 0x1000>; - reg-names = "csr-reg"; - clock-output-names = "pcie1clk"; - }; - - xge0clk: xge0clk@1f61c000 { - compatible = "apm,xgene-device-clock"; - #clock-cells = <1>; - clocks = <&socplldiv2 0>; - reg = <0x0 0x1f61c000 0x0 0x1000>; - reg-names = "csr-reg"; - enable-mask = <0x3>; - csr-mask = <0x3>; - clock-output-names = "xge0clk"; - }; - - xge1clk: xge1clk@1f62c000 { - compatible = "apm,xgene-device-clock"; - #clock-cells = <1>; - clocks = <&socplldiv2 0>; - reg = <0x0 0x1f62c000 0x0 0x1000>; - reg-names = "csr-reg"; - enable-mask = <0x3>; - csr-mask = <0x3>; - clock-output-names = "xge1clk"; - }; - - rngpkaclk: rngpkaclk@17000000 { - compatible = "apm,xgene-device-clock"; - #clock-cells = <1>; - clocks = <&socplldiv2 0>; - reg = <0x0 0x17000000 0x0 0x2000>; - reg-names = "csr-reg"; - csr-offset = <0xc>; - csr-mask = <0x10>; - enable-offset = <0x10>; - enable-mask = <0x10>; - clock-output-names = "rngpkaclk"; - }; - - i2c4clk: i2c4clk@1704c000 { - compatible = "apm,xgene-device-clock"; - #clock-cells = <1>; - clocks = <&sbapbclk 0>; - reg = <0x0 0x1704c000 0x0 0x1000>; - reg-names = "csr-reg"; - csr-offset = <0x0>; - csr-mask = <0x40>; - enable-offset = <0x8>; - enable-mask = <0x40>; - clock-output-names = "i2c4clk"; - }; - }; - - scu: system-clk-controller@17000000 { - compatible = "apm,xgene-scu","syscon"; - reg = <0x0 0x17000000 0x0 0x400>; - }; - - reboot: reboot@17000014 { - compatible = "syscon-reboot"; - regmap = <&scu>; - offset = <0x14>; - mask = <0x1>; - }; - - csw: csw@7e200000 { - compatible = "apm,xgene-csw", "syscon"; - reg = <0x0 0x7e200000 0x0 0x1000>; - }; - - mcba: mcba@7e700000 { - compatible = "apm,xgene-mcb", "syscon"; - reg = <0x0 0x7e700000 0x0 0x1000>; - }; - - mcbb: mcbb@7e720000 { - compatible = "apm,xgene-mcb", "syscon"; - reg = <0x0 0x7e720000 0x0 0x1000>; - }; - - efuse: efuse@1054a000 { - compatible = "apm,xgene-efuse", "syscon"; - reg = <0x0 0x1054a000 0x0 0x20>; - }; - - edac@78800000 { - compatible = "apm,xgene-edac"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - regmap-csw = <&csw>; - regmap-mcba = <&mcba>; - regmap-mcbb = <&mcbb>; - regmap-efuse = <&efuse>; - reg = <0x0 0x78800000 0x0 0x100>; - interrupts = <0x0 0x20 0x4>, - <0x0 0x21 0x4>, - <0x0 0x27 0x4>; - - edacmc@7e800000 { - compatible = "apm,xgene-edac-mc"; - reg = <0x0 0x7e800000 0x0 0x1000>; - memory-controller = <0>; - }; - - edacmc@7e840000 { - compatible = "apm,xgene-edac-mc"; - reg = <0x0 0x7e840000 0x0 0x1000>; - memory-controller = <1>; - }; - - edacmc@7e880000 { - compatible = "apm,xgene-edac-mc"; - reg = <0x0 0x7e880000 0x0 0x1000>; - memory-controller = <2>; - }; - - edacmc@7e8c0000 { - compatible = "apm,xgene-edac-mc"; - reg = <0x0 0x7e8c0000 0x0 0x1000>; - memory-controller = <3>; - }; - - edacpmd@7c000000 { - compatible = "apm,xgene-edac-pmd"; - reg = <0x0 0x7c000000 0x0 0x200000>; - pmd-controller = <0>; - }; - - edacpmd@7c200000 { - compatible = "apm,xgene-edac-pmd"; - reg = <0x0 0x7c200000 0x0 0x200000>; - pmd-controller = <1>; - }; - - edacpmd@7c400000 { - compatible = "apm,xgene-edac-pmd"; - reg = <0x0 0x7c400000 0x0 0x200000>; - pmd-controller = <2>; - }; - - edacpmd@7c600000 { - compatible = "apm,xgene-edac-pmd"; - reg = <0x0 0x7c600000 0x0 0x200000>; - pmd-controller = <3>; - }; - - edacl3@7e600000 { - compatible = "apm,xgene-edac-l3-v2"; - reg = <0x0 0x7e600000 0x0 0x1000>; - }; - - edacsoc@7e930000 { - compatible = "apm,xgene-edac-soc"; - reg = <0x0 0x7e930000 0x0 0x1000>; - }; - }; - - pmu: pmu@78810000 { - compatible = "apm,xgene-pmu-v2"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - regmap-csw = <&csw>; - regmap-mcba = <&mcba>; - regmap-mcbb = <&mcbb>; - reg = <0x0 0x78810000 0x0 0x1000>; - interrupts = <0x0 0x22 0x4>; - - pmul3c@7e610000 { - compatible = "apm,xgene-pmu-l3c"; - reg = <0x0 0x7e610000 0x0 0x1000>; - }; - - pmuiob@7e940000 { - compatible = "apm,xgene-pmu-iob"; - reg = <0x0 0x7e940000 0x0 0x1000>; - }; - - pmucmcb@7e710000 { - compatible = "apm,xgene-pmu-mcb"; - reg = <0x0 0x7e710000 0x0 0x1000>; - enable-bit-index = <0>; - }; - - pmucmcb@7e730000 { - compatible = "apm,xgene-pmu-mcb"; - reg = <0x0 0x7e730000 0x0 0x1000>; - enable-bit-index = <1>; - }; - - pmucmc@7e810000 { - compatible = "apm,xgene-pmu-mc"; - reg = <0x0 0x7e810000 0x0 0x1000>; - enable-bit-index = <0>; - }; - - pmucmc@7e850000 { - compatible = "apm,xgene-pmu-mc"; - reg = <0x0 0x7e850000 0x0 0x1000>; - enable-bit-index = <1>; - }; - - pmucmc@7e890000 { - compatible = "apm,xgene-pmu-mc"; - reg = <0x0 0x7e890000 0x0 0x1000>; - enable-bit-index = <2>; - }; - - pmucmc@7e8d0000 { - compatible = "apm,xgene-pmu-mc"; - reg = <0x0 0x7e8d0000 0x0 0x1000>; - enable-bit-index = <3>; - }; - }; - - mailbox: mailbox@10540000 { - compatible = "apm,xgene-slimpro-mbox"; - reg = <0x0 0x10540000 0x0 0x8000>; - #mbox-cells = <1>; - interrupts = <0x0 0x0 0x4 - 0x0 0x1 0x4 - 0x0 0x2 0x4 - 0x0 0x3 0x4 - 0x0 0x4 0x4 - 0x0 0x5 0x4 - 0x0 0x6 0x4 - 0x0 0x7 0x4>; - }; - - i2cslimpro { - compatible = "apm,xgene-slimpro-i2c"; - mboxes = <&mailbox 0>; - }; - - hwmonslimpro { - compatible = "apm,xgene-slimpro-hwmon"; - mboxes = <&mailbox 7>; - }; - - serial0: serial@10600000 { - device_type = "serial"; - compatible = "ns16550"; - reg = <0 0x10600000 0x0 0x1000>; - reg-shift = <2>; - clock-frequency = <10000000>; - interrupt-parent = <&gic>; - interrupts = <0x0 0x4c 0x4>; - }; - - /* Do not change dwusb name, coded for backward compatibility */ - usb0: dwusb@19000000 { - status = "disabled"; - compatible = "snps,dwc3"; - reg = <0x0 0x19000000 0x0 0x100000>; - interrupts = <0x0 0x5d 0x4>; - dma-coherent; - dr_mode = "host"; - }; - - pcie0: pcie@1f2b0000 { - status = "disabled"; - device_type = "pci"; - compatible = "apm,xgene-pcie", "apm,xgene2-pcie"; - #interrupt-cells = <1>; - #size-cells = <2>; - #address-cells = <3>; - reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */ - 0xc0 0xd0000000 0x0 0x00040000>; /* PCI config space */ - reg-names = "csr", "cfg"; - ranges = <0x01000000 0x00 0x00000000 0xc0 0x10000000 0x00 0x00010000 /* io */ - 0x02000000 0x00 0x20000000 0xc1 0x20000000 0x00 0x20000000 /* mem */ - 0x43000000 0xe0 0x00000000 0xe0 0x00000000 0x20 0x00000000>; /* mem */ - dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 - 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0x0 0x0 0x0 0x7>; - interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x10 0x4 - 0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 0x11 0x4 - 0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 0x12 0x4 - 0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 0x13 0x4>; - dma-coherent; - clocks = <&pcie0clk 0>; - msi-parent = <&v2m0>; - }; - - pcie1: pcie@1f2c0000 { - status = "disabled"; - device_type = "pci"; - compatible = "apm,xgene-pcie", "apm,xgene2-pcie"; - #interrupt-cells = <1>; - #size-cells = <2>; - #address-cells = <3>; - reg = < 0x00 0x1f2c0000 0x0 0x00010000 /* Controller registers */ - 0xa0 0xd0000000 0x0 0x00040000>; /* PCI config space */ - reg-names = "csr", "cfg"; - ranges = <0x01000000 0x00 0x00000000 0xa0 0x10000000 0x00 0x00010000 /* io */ - 0x02000000 0x00 0x20000000 0xa1 0x20000000 0x00 0x20000000 /* mem */ - 0x43000000 0xb0 0x00000000 0xb0 0x00000000 0x10 0x00000000>; /* mem */ - dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 - 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0x0 0x0 0x0 0x7>; - interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x16 0x4 - 0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 0x17 0x4 - 0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 0x18 0x4 - 0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 0x19 0x4>; - dma-coherent; - clocks = <&pcie1clk 0>; - msi-parent = <&v2m0>; - }; - - sata1: sata@1a000000 { - compatible = "apm,xgene-ahci-v2"; - reg = <0x0 0x1a000000 0x0 0x1000>, - <0x0 0x1f200000 0x0 0x1000>, - <0x0 0x1f20d000 0x0 0x1000>, - <0x0 0x1f20e000 0x0 0x1000>; - interrupts = <0x0 0x5a 0x4>; - dma-coherent; - }; - - sata2: sata@1a200000 { - compatible = "apm,xgene-ahci-v2"; - reg = <0x0 0x1a200000 0x0 0x1000>, - <0x0 0x1f210000 0x0 0x1000>, - <0x0 0x1f21d000 0x0 0x1000>, - <0x0 0x1f21e000 0x0 0x1000>; - interrupts = <0x0 0x5b 0x4>; - dma-coherent; - }; - - sata3: sata@1a400000 { - compatible = "apm,xgene-ahci-v2"; - reg = <0x0 0x1a400000 0x0 0x1000>, - <0x0 0x1f220000 0x0 0x1000>, - <0x0 0x1f22d000 0x0 0x1000>, - <0x0 0x1f22e000 0x0 0x1000>; - interrupts = <0x0 0x5c 0x4>; - dma-coherent; - }; - - mmc0: mmc@1c000000 { - compatible = "arasan,sdhci-4.9a"; - reg = <0x0 0x1c000000 0x0 0x100>; - interrupts = <0x0 0x49 0x4>; - dma-coherent; - no-1-8-v; - clock-names = "clk_xin", "clk_ahb"; - clocks = <&sdioclk 0>, <&ahbclk 0>; - }; - - gfcgpio: gpio@1f63c000 { - compatible = "apm,xgene-gpio"; - reg = <0x0 0x1f63c000 0x0 0x40>; - gpio-controller; - #gpio-cells = <2>; - }; - - dwgpio: gpio@1c024000 { - compatible = "snps,dw-apb-gpio"; - reg = <0x0 0x1c024000 0x0 0x1000>; - reg-io-width = <4>; - #address-cells = <1>; - #size-cells = <0>; - - porta: gpio-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - snps,nr-gpios = <32>; - reg = <0>; - }; - }; - - sbgpio: gpio@17001000{ - compatible = "apm,xgene-gpio-sb"; - reg = <0x0 0x17001000 0x0 0x400>; - #gpio-cells = <2>; - gpio-controller; - interrupts = <0x0 0x28 0x1>, - <0x0 0x29 0x1>, - <0x0 0x2a 0x1>, - <0x0 0x2b 0x1>, - <0x0 0x2c 0x1>, - <0x0 0x2d 0x1>, - <0x0 0x2e 0x1>, - <0x0 0x2f 0x1>; - interrupt-parent = <&gic>; - #interrupt-cells = <2>; - interrupt-controller; - apm,nr-gpios = <22>; - apm,nr-irqs = <8>; - apm,irq-start = <8>; - }; - - mdio: mdio@1f610000 { - compatible = "apm,xgene-mdio-xfi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x1f610000 0x0 0xd100>; - clocks = <&xge0clk 0>; - }; - - sgenet0: ethernet@1f610000 { - compatible = "apm,xgene2-sgenet"; - status = "disabled"; - reg = <0x0 0x1f610000 0x0 0xd100>, - <0x0 0x1f600000 0x0 0xd100>, - <0x0 0x20000000 0x0 0x20000>; - interrupts = <0 96 4>, - <0 97 4>; - dma-coherent; - clocks = <&xge0clk 0>; - local-mac-address = [00 01 73 00 00 01]; - phy-connection-type = "sgmii"; - phy-handle = <&sgenet0phy>; - }; - - xgenet1: ethernet@1f620000 { - compatible = "apm,xgene2-xgenet"; - status = "disabled"; - reg = <0x0 0x1f620000 0x0 0x10000>, - <0x0 0x1f600000 0x0 0xd100>, - <0x0 0x20000000 0x0 0x220000>; - interrupts = <0 108 4>, - <0 109 4>, - <0 110 4>, - <0 111 4>, - <0 112 4>, - <0 113 4>, - <0 114 4>, - <0 115 4>; - channel = <12>; - port-id = <1>; - dma-coherent; - clocks = <&xge1clk 0>; - local-mac-address = [00 01 73 00 00 02]; - phy-connection-type = "xgmii"; - }; - - rng: rng@10520000 { - compatible = "apm,xgene-rng"; - reg = <0x0 0x10520000 0x0 0x100>; - interrupts = <0x0 0x41 0x4>; - clocks = <&rngpkaclk 0>; - }; - - i2c1: i2c@10511000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0x0 0x10511000 0x0 0x1000>; - interrupts = <0 0x45 0x4>; - #clock-cells = <1>; - clocks = <&sbapbclk 0>; - bus_num = <1>; - }; - - i2c4: i2c@10640000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0x0 0x10640000 0x0 0x1000>; - interrupts = <0 0x3a 0x4>; - clocks = <&i2c4clk 0>; - bus_num = <4>; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/apm/apm-storm.dtsi b/sys/gnu/dts/arm64/apm/apm-storm.dtsi deleted file mode 100644 index 8c802d87e75..00000000000 --- a/sys/gnu/dts/arm64/apm/apm-storm.dtsi +++ /dev/null @@ -1,1098 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * dts file for AppliedMicro (APM) X-Gene Storm SOC - * - * Copyright (C) 2013, Applied Micro Circuits Corporation - */ - -/ { - compatible = "apm,xgene-storm"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "apm,potenza"; - reg = <0x0 0x000>; - enable-method = "spin-table"; - cpu-release-addr = <0x1 0x0000fff8>; - next-level-cache = <&xgene_L2_0>; - }; - cpu@1 { - device_type = "cpu"; - compatible = "apm,potenza"; - reg = <0x0 0x001>; - enable-method = "spin-table"; - cpu-release-addr = <0x1 0x0000fff8>; - next-level-cache = <&xgene_L2_0>; - }; - cpu@100 { - device_type = "cpu"; - compatible = "apm,potenza"; - reg = <0x0 0x100>; - enable-method = "spin-table"; - cpu-release-addr = <0x1 0x0000fff8>; - next-level-cache = <&xgene_L2_1>; - }; - cpu@101 { - device_type = "cpu"; - compatible = "apm,potenza"; - reg = <0x0 0x101>; - enable-method = "spin-table"; - cpu-release-addr = <0x1 0x0000fff8>; - next-level-cache = <&xgene_L2_1>; - }; - cpu@200 { - device_type = "cpu"; - compatible = "apm,potenza"; - reg = <0x0 0x200>; - enable-method = "spin-table"; - cpu-release-addr = <0x1 0x0000fff8>; - next-level-cache = <&xgene_L2_2>; - }; - cpu@201 { - device_type = "cpu"; - compatible = "apm,potenza"; - reg = <0x0 0x201>; - enable-method = "spin-table"; - cpu-release-addr = <0x1 0x0000fff8>; - next-level-cache = <&xgene_L2_2>; - }; - cpu@300 { - device_type = "cpu"; - compatible = "apm,potenza"; - reg = <0x0 0x300>; - enable-method = "spin-table"; - cpu-release-addr = <0x1 0x0000fff8>; - next-level-cache = <&xgene_L2_3>; - }; - cpu@301 { - device_type = "cpu"; - compatible = "apm,potenza"; - reg = <0x0 0x301>; - enable-method = "spin-table"; - cpu-release-addr = <0x1 0x0000fff8>; - next-level-cache = <&xgene_L2_3>; - }; - xgene_L2_0: l2-cache-0 { - compatible = "cache"; - }; - xgene_L2_1: l2-cache-1 { - compatible = "cache"; - }; - xgene_L2_2: l2-cache-2 { - compatible = "cache"; - }; - xgene_L2_3: l2-cache-3 { - compatible = "cache"; - }; - }; - - gic: interrupt-controller@78010000 { - compatible = "arm,cortex-a15-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x0 0x78010000 0x0 0x1000>, /* GIC Dist */ - <0x0 0x78020000 0x0 0x1000>, /* GIC CPU */ - <0x0 0x78040000 0x0 0x2000>, /* GIC VCPU Control */ - <0x0 0x78060000 0x0 0x2000>; /* GIC VCPU */ - interrupts = <1 9 0xf04>; /* GIC Maintenence IRQ */ - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = <1 0 0xff08>, /* Secure Phys IRQ */ - <1 13 0xff08>, /* Non-secure Phys IRQ */ - <1 14 0xff08>, /* Virt IRQ */ - <1 15 0xff08>; /* Hyp IRQ */ - clock-frequency = <50000000>; - }; - - pmu { - compatible = "apm,potenza-pmu", "arm,armv8-pmuv3"; - interrupts = <1 12 0xff04>; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - dma-ranges = <0x0 0x0 0x0 0x0 0x400 0x0>; - - clocks { - #address-cells = <2>; - #size-cells = <2>; - ranges; - refclk: refclk { - compatible = "fixed-clock"; - #clock-cells = <1>; - clock-frequency = <100000000>; - clock-output-names = "refclk"; - }; - - pcppll: pcppll@17000100 { - compatible = "apm,xgene-pcppll-clock"; - #clock-cells = <1>; - clocks = <&refclk 0>; - clock-names = "pcppll"; - reg = <0x0 0x17000100 0x0 0x1000>; - clock-output-names = "pcppll"; - type = <0>; - }; - - socpll: socpll@17000120 { - compatible = "apm,xgene-socpll-clock"; - #clock-cells = <1>; - clocks = <&refclk 0>; - clock-names = "socpll"; - reg = <0x0 0x17000120 0x0 0x1000>; - clock-output-names = "socpll"; - type = <1>; - }; - - socplldiv2: socplldiv2 { - compatible = "fixed-factor-clock"; - #clock-cells = <1>; - clocks = <&socpll 0>; - clock-names = "socplldiv2"; - clock-mult = <1>; - clock-div = <2>; - clock-output-names = "socplldiv2"; - }; - - ahbclk: ahbclk@17000000 { - compatible = "apm,xgene-device-clock"; - #clock-cells = <1>; - clocks = <&socplldiv2 0>; - reg = <0x0 0x17000000 0x0 0x2000>; - reg-names = "div-reg"; - divider-offset = <0x164>; - divider-width = <0x5>; - divider-shift = <0x0>; - clock-output-names = "ahbclk"; - }; - - sdioclk: sdioclk@1f2ac000 { - compatible = "apm,xgene-device-clock"; - #clock-cells = <1>; - clocks = <&socplldiv2 0>; - reg = <0x0 0x1f2ac000 0x0 0x1000 - 0x0 0x17000000 0x0 0x2000>; - reg-names = "csr-reg", "div-reg"; - csr-offset = <0x0>; - csr-mask = <0x2>; - enable-offset = <0x8>; - enable-mask = <0x2>; - divider-offset = <0x178>; - divider-width = <0x8>; - divider-shift = <0x0>; - clock-output-names = "sdioclk"; - }; - - ethclk: ethclk { - compatible = "apm,xgene-device-clock"; - #clock-cells = <1>; - clocks = <&socplldiv2 0>; - clock-names = "ethclk"; - reg = <0x0 0x17000000 0x0 0x1000>; - reg-names = "div-reg"; - divider-offset = <0x238>; - divider-width = <0x9>; - divider-shift = <0x0>; - clock-output-names = "ethclk"; - }; - - menetclk: menetclk { - compatible = "apm,xgene-device-clock"; - #clock-cells = <1>; - clocks = <ðclk 0>; - reg = <0x0 0x1702c000 0x0 0x1000>; - reg-names = "csr-reg"; - clock-output-names = "menetclk"; - }; - - sge0clk: sge0clk@1f21c000 { - compatible = "apm,xgene-device-clock"; - #clock-cells = <1>; - clocks = <&socplldiv2 0>; - reg = <0x0 0x1f21c000 0x0 0x1000>; - reg-names = "csr-reg"; - csr-mask = <0xa>; - enable-mask = <0xf>; - clock-output-names = "sge0clk"; - }; - - xge0clk: xge0clk@1f61c000 { - compatible = "apm,xgene-device-clock"; - #clock-cells = <1>; - clocks = <&socplldiv2 0>; - reg = <0x0 0x1f61c000 0x0 0x1000>; - reg-names = "csr-reg"; - csr-mask = <0x3>; - clock-output-names = "xge0clk"; - }; - - xge1clk: xge1clk@1f62c000 { - compatible = "apm,xgene-device-clock"; - status = "disabled"; - #clock-cells = <1>; - clocks = <&socplldiv2 0>; - reg = <0x0 0x1f62c000 0x0 0x1000>; - reg-names = "csr-reg"; - csr-mask = <0x3>; - clock-output-names = "xge1clk"; - }; - - sataphy1clk: sataphy1clk@1f21c000 { - compatible = "apm,xgene-device-clock"; - #clock-cells = <1>; - clocks = <&socplldiv2 0>; - reg = <0x0 0x1f21c000 0x0 0x1000>; - reg-names = "csr-reg"; - clock-output-names = "sataphy1clk"; - status = "disabled"; - csr-offset = <0x4>; - csr-mask = <0x00>; - enable-offset = <0x0>; - enable-mask = <0x06>; - }; - - sataphy2clk: sataphy1clk@1f22c000 { - compatible = "apm,xgene-device-clock"; - #clock-cells = <1>; - clocks = <&socplldiv2 0>; - reg = <0x0 0x1f22c000 0x0 0x1000>; - reg-names = "csr-reg"; - clock-output-names = "sataphy2clk"; - status = "ok"; - csr-offset = <0x4>; - csr-mask = <0x3a>; - enable-offset = <0x0>; - enable-mask = <0x06>; - }; - - sataphy3clk: sataphy1clk@1f23c000 { - compatible = "apm,xgene-device-clock"; - #clock-cells = <1>; - clocks = <&socplldiv2 0>; - reg = <0x0 0x1f23c000 0x0 0x1000>; - reg-names = "csr-reg"; - clock-output-names = "sataphy3clk"; - status = "ok"; - csr-offset = <0x4>; - csr-mask = <0x3a>; - enable-offset = <0x0>; - enable-mask = <0x06>; - }; - - sata01clk: sata01clk@1f21c000 { - compatible = "apm,xgene-device-clock"; - #clock-cells = <1>; - clocks = <&socplldiv2 0>; - reg = <0x0 0x1f21c000 0x0 0x1000>; - reg-names = "csr-reg"; - clock-output-names = "sata01clk"; - csr-offset = <0x4>; - csr-mask = <0x05>; - enable-offset = <0x0>; - enable-mask = <0x39>; - }; - - sata23clk: sata23clk@1f22c000 { - compatible = "apm,xgene-device-clock"; - #clock-cells = <1>; - clocks = <&socplldiv2 0>; - reg = <0x0 0x1f22c000 0x0 0x1000>; - reg-names = "csr-reg"; - clock-output-names = "sata23clk"; - csr-offset = <0x4>; - csr-mask = <0x05>; - enable-offset = <0x0>; - enable-mask = <0x39>; - }; - - sata45clk: sata45clk@1f23c000 { - compatible = "apm,xgene-device-clock"; - #clock-cells = <1>; - clocks = <&socplldiv2 0>; - reg = <0x0 0x1f23c000 0x0 0x1000>; - reg-names = "csr-reg"; - clock-output-names = "sata45clk"; - csr-offset = <0x4>; - csr-mask = <0x05>; - enable-offset = <0x0>; - enable-mask = <0x39>; - }; - - rtcclk: rtcclk@17000000 { - compatible = "apm,xgene-device-clock"; - #clock-cells = <1>; - clocks = <&socplldiv2 0>; - reg = <0x0 0x17000000 0x0 0x2000>; - reg-names = "csr-reg"; - csr-offset = <0xc>; - csr-mask = <0x2>; - enable-offset = <0x10>; - enable-mask = <0x2>; - clock-output-names = "rtcclk"; - }; - - rngpkaclk: rngpkaclk@17000000 { - compatible = "apm,xgene-device-clock"; - #clock-cells = <1>; - clocks = <&socplldiv2 0>; - reg = <0x0 0x17000000 0x0 0x2000>; - reg-names = "csr-reg"; - csr-offset = <0xc>; - csr-mask = <0x10>; - enable-offset = <0x10>; - enable-mask = <0x10>; - clock-output-names = "rngpkaclk"; - }; - - pcie0clk: pcie0clk@1f2bc000 { - status = "disabled"; - compatible = "apm,xgene-device-clock"; - #clock-cells = <1>; - clocks = <&socplldiv2 0>; - reg = <0x0 0x1f2bc000 0x0 0x1000>; - reg-names = "csr-reg"; - clock-output-names = "pcie0clk"; - }; - - pcie1clk: pcie1clk@1f2cc000 { - status = "disabled"; - compatible = "apm,xgene-device-clock"; - #clock-cells = <1>; - clocks = <&socplldiv2 0>; - reg = <0x0 0x1f2cc000 0x0 0x1000>; - reg-names = "csr-reg"; - clock-output-names = "pcie1clk"; - }; - - pcie2clk: pcie2clk@1f2dc000 { - status = "disabled"; - compatible = "apm,xgene-device-clock"; - #clock-cells = <1>; - clocks = <&socplldiv2 0>; - reg = <0x0 0x1f2dc000 0x0 0x1000>; - reg-names = "csr-reg"; - clock-output-names = "pcie2clk"; - }; - - pcie3clk: pcie3clk@1f50c000 { - status = "disabled"; - compatible = "apm,xgene-device-clock"; - #clock-cells = <1>; - clocks = <&socplldiv2 0>; - reg = <0x0 0x1f50c000 0x0 0x1000>; - reg-names = "csr-reg"; - clock-output-names = "pcie3clk"; - }; - - pcie4clk: pcie4clk@1f51c000 { - status = "disabled"; - compatible = "apm,xgene-device-clock"; - #clock-cells = <1>; - clocks = <&socplldiv2 0>; - reg = <0x0 0x1f51c000 0x0 0x1000>; - reg-names = "csr-reg"; - clock-output-names = "pcie4clk"; - }; - - dmaclk: dmaclk@1f27c000 { - compatible = "apm,xgene-device-clock"; - #clock-cells = <1>; - clocks = <&socplldiv2 0>; - reg = <0x0 0x1f27c000 0x0 0x1000>; - reg-names = "csr-reg"; - clock-output-names = "dmaclk"; - }; - }; - - msi: msi@79000000 { - compatible = "apm,xgene1-msi"; - msi-controller; - reg = <0x00 0x79000000 0x0 0x900000>; - interrupts = < 0x0 0x10 0x4 - 0x0 0x11 0x4 - 0x0 0x12 0x4 - 0x0 0x13 0x4 - 0x0 0x14 0x4 - 0x0 0x15 0x4 - 0x0 0x16 0x4 - 0x0 0x17 0x4 - 0x0 0x18 0x4 - 0x0 0x19 0x4 - 0x0 0x1a 0x4 - 0x0 0x1b 0x4 - 0x0 0x1c 0x4 - 0x0 0x1d 0x4 - 0x0 0x1e 0x4 - 0x0 0x1f 0x4>; - }; - - scu: system-clk-controller@17000000 { - compatible = "apm,xgene-scu","syscon"; - reg = <0x0 0x17000000 0x0 0x400>; - }; - - reboot: reboot@17000014 { - compatible = "syscon-reboot"; - regmap = <&scu>; - offset = <0x14>; - mask = <0x1>; - }; - - csw: csw@7e200000 { - compatible = "apm,xgene-csw", "syscon"; - reg = <0x0 0x7e200000 0x0 0x1000>; - }; - - mcba: mcba@7e700000 { - compatible = "apm,xgene-mcb", "syscon"; - reg = <0x0 0x7e700000 0x0 0x1000>; - }; - - mcbb: mcbb@7e720000 { - compatible = "apm,xgene-mcb", "syscon"; - reg = <0x0 0x7e720000 0x0 0x1000>; - }; - - efuse: efuse@1054a000 { - compatible = "apm,xgene-efuse", "syscon"; - reg = <0x0 0x1054a000 0x0 0x20>; - }; - - rb: rb@7e000000 { - compatible = "apm,xgene-rb", "syscon"; - reg = <0x0 0x7e000000 0x0 0x10>; - }; - - edac@78800000 { - compatible = "apm,xgene-edac"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - regmap-csw = <&csw>; - regmap-mcba = <&mcba>; - regmap-mcbb = <&mcbb>; - regmap-efuse = <&efuse>; - regmap-rb = <&rb>; - reg = <0x0 0x78800000 0x0 0x100>; - interrupts = <0x0 0x20 0x4>, - <0x0 0x21 0x4>, - <0x0 0x27 0x4>; - - edacmc@7e800000 { - compatible = "apm,xgene-edac-mc"; - reg = <0x0 0x7e800000 0x0 0x1000>; - memory-controller = <0>; - }; - - edacmc@7e840000 { - compatible = "apm,xgene-edac-mc"; - reg = <0x0 0x7e840000 0x0 0x1000>; - memory-controller = <1>; - }; - - edacmc@7e880000 { - compatible = "apm,xgene-edac-mc"; - reg = <0x0 0x7e880000 0x0 0x1000>; - memory-controller = <2>; - }; - - edacmc@7e8c0000 { - compatible = "apm,xgene-edac-mc"; - reg = <0x0 0x7e8c0000 0x0 0x1000>; - memory-controller = <3>; - }; - - edacpmd@7c000000 { - compatible = "apm,xgene-edac-pmd"; - reg = <0x0 0x7c000000 0x0 0x200000>; - pmd-controller = <0>; - }; - - edacpmd@7c200000 { - compatible = "apm,xgene-edac-pmd"; - reg = <0x0 0x7c200000 0x0 0x200000>; - pmd-controller = <1>; - }; - - edacpmd@7c400000 { - compatible = "apm,xgene-edac-pmd"; - reg = <0x0 0x7c400000 0x0 0x200000>; - pmd-controller = <2>; - }; - - edacpmd@7c600000 { - compatible = "apm,xgene-edac-pmd"; - reg = <0x0 0x7c600000 0x0 0x200000>; - pmd-controller = <3>; - }; - - edacl3@7e600000 { - compatible = "apm,xgene-edac-l3"; - reg = <0x0 0x7e600000 0x0 0x1000>; - }; - - edacsoc@7e930000 { - compatible = "apm,xgene-edac-soc-v1"; - reg = <0x0 0x7e930000 0x0 0x1000>; - }; - }; - - pmu: pmu@78810000 { - compatible = "apm,xgene-pmu-v2"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - regmap-csw = <&csw>; - regmap-mcba = <&mcba>; - regmap-mcbb = <&mcbb>; - reg = <0x0 0x78810000 0x0 0x1000>; - interrupts = <0x0 0x22 0x4>; - - pmul3c@7e610000 { - compatible = "apm,xgene-pmu-l3c"; - reg = <0x0 0x7e610000 0x0 0x1000>; - }; - - pmuiob@7e940000 { - compatible = "apm,xgene-pmu-iob"; - reg = <0x0 0x7e940000 0x0 0x1000>; - }; - - pmucmcb@7e710000 { - compatible = "apm,xgene-pmu-mcb"; - reg = <0x0 0x7e710000 0x0 0x1000>; - enable-bit-index = <0>; - }; - - pmucmcb@7e730000 { - compatible = "apm,xgene-pmu-mcb"; - reg = <0x0 0x7e730000 0x0 0x1000>; - enable-bit-index = <1>; - }; - - pmucmc@7e810000 { - compatible = "apm,xgene-pmu-mc"; - reg = <0x0 0x7e810000 0x0 0x1000>; - enable-bit-index = <0>; - }; - - pmucmc@7e850000 { - compatible = "apm,xgene-pmu-mc"; - reg = <0x0 0x7e850000 0x0 0x1000>; - enable-bit-index = <1>; - }; - - pmucmc@7e890000 { - compatible = "apm,xgene-pmu-mc"; - reg = <0x0 0x7e890000 0x0 0x1000>; - enable-bit-index = <2>; - }; - - pmucmc@7e8d0000 { - compatible = "apm,xgene-pmu-mc"; - reg = <0x0 0x7e8d0000 0x0 0x1000>; - enable-bit-index = <3>; - }; - }; - - pcie0: pcie@1f2b0000 { - status = "disabled"; - device_type = "pci"; - compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie"; - #interrupt-cells = <1>; - #size-cells = <2>; - #address-cells = <3>; - reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */ - 0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */ - reg-names = "csr", "cfg"; - ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000 /* io */ - 0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000 /* mem */ - 0x43000000 0xf0 0x00000000 0xf0 0x00000000 0x10 0x00000000>; /* mem */ - dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 - 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0x0 0x0 0x0 0x7>; - interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x4 - 0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x4 - 0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x4 - 0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x4>; - dma-coherent; - clocks = <&pcie0clk 0>; - msi-parent = <&msi>; - }; - - pcie1: pcie@1f2c0000 { - status = "disabled"; - device_type = "pci"; - compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie"; - #interrupt-cells = <1>; - #size-cells = <2>; - #address-cells = <3>; - reg = < 0x00 0x1f2c0000 0x0 0x00010000 /* Controller registers */ - 0xd0 0xd0000000 0x0 0x00040000>; /* PCI config space */ - reg-names = "csr", "cfg"; - ranges = <0x01000000 0x00 0x00000000 0xd0 0x10000000 0x00 0x00010000 /* io */ - 0x02000000 0x00 0x80000000 0xd1 0x80000000 0x00 0x80000000 /* mem */ - 0x43000000 0xd8 0x00000000 0xd8 0x00000000 0x08 0x00000000>; /* mem */ - dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 - 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0x0 0x0 0x0 0x7>; - interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc8 0x4 - 0x0 0x0 0x0 0x2 &gic 0x0 0xc9 0x4 - 0x0 0x0 0x0 0x3 &gic 0x0 0xca 0x4 - 0x0 0x0 0x0 0x4 &gic 0x0 0xcb 0x4>; - dma-coherent; - clocks = <&pcie1clk 0>; - msi-parent = <&msi>; - }; - - pcie2: pcie@1f2d0000 { - status = "disabled"; - device_type = "pci"; - compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie"; - #interrupt-cells = <1>; - #size-cells = <2>; - #address-cells = <3>; - reg = < 0x00 0x1f2d0000 0x0 0x00010000 /* Controller registers */ - 0x90 0xd0000000 0x0 0x00040000>; /* PCI config space */ - reg-names = "csr", "cfg"; - ranges = <0x01000000 0x00 0x00000000 0x90 0x10000000 0x00 0x00010000 /* io */ - 0x02000000 0x00 0x80000000 0x91 0x80000000 0x00 0x80000000 /* mem */ - 0x43000000 0x94 0x00000000 0x94 0x00000000 0x04 0x00000000>; /* mem */ - dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 - 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0x0 0x0 0x0 0x7>; - interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xce 0x4 - 0x0 0x0 0x0 0x2 &gic 0x0 0xcf 0x4 - 0x0 0x0 0x0 0x3 &gic 0x0 0xd0 0x4 - 0x0 0x0 0x0 0x4 &gic 0x0 0xd1 0x4>; - dma-coherent; - clocks = <&pcie2clk 0>; - msi-parent = <&msi>; - }; - - pcie3: pcie@1f500000 { - status = "disabled"; - device_type = "pci"; - compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie"; - #interrupt-cells = <1>; - #size-cells = <2>; - #address-cells = <3>; - reg = < 0x00 0x1f500000 0x0 0x00010000 /* Controller registers */ - 0xa0 0xd0000000 0x0 0x00040000>; /* PCI config space */ - reg-names = "csr", "cfg"; - ranges = <0x01000000 0x00 0x00000000 0xa0 0x10000000 0x00 0x00010000 /* io */ - 0x02000000 0x00 0x80000000 0xa1 0x80000000 0x00 0x80000000 /* mem */ - 0x43000000 0xb0 0x00000000 0xb0 0x00000000 0x10 0x00000000>; /* mem */ - dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 - 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0x0 0x0 0x0 0x7>; - interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xd4 0x4 - 0x0 0x0 0x0 0x2 &gic 0x0 0xd5 0x4 - 0x0 0x0 0x0 0x3 &gic 0x0 0xd6 0x4 - 0x0 0x0 0x0 0x4 &gic 0x0 0xd7 0x4>; - dma-coherent; - clocks = <&pcie3clk 0>; - msi-parent = <&msi>; - }; - - pcie4: pcie@1f510000 { - status = "disabled"; - device_type = "pci"; - compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie"; - #interrupt-cells = <1>; - #size-cells = <2>; - #address-cells = <3>; - reg = < 0x00 0x1f510000 0x0 0x00010000 /* Controller registers */ - 0xc0 0xd0000000 0x0 0x00200000>; /* PCI config space */ - reg-names = "csr", "cfg"; - ranges = <0x01000000 0x00 0x00000000 0xc0 0x10000000 0x00 0x00010000 /* io */ - 0x02000000 0x00 0x80000000 0xc1 0x80000000 0x00 0x80000000 /* mem */ - 0x43000000 0xc8 0x00000000 0xc8 0x00000000 0x08 0x00000000>; /* mem */ - dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 - 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0x0 0x0 0x0 0x7>; - interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xda 0x4 - 0x0 0x0 0x0 0x2 &gic 0x0 0xdb 0x4 - 0x0 0x0 0x0 0x3 &gic 0x0 0xdc 0x4 - 0x0 0x0 0x0 0x4 &gic 0x0 0xdd 0x4>; - dma-coherent; - clocks = <&pcie4clk 0>; - msi-parent = <&msi>; - }; - - mailbox: mailbox@10540000 { - compatible = "apm,xgene-slimpro-mbox"; - reg = <0x0 0x10540000 0x0 0xa000>; - #mbox-cells = <1>; - interrupts = <0x0 0x0 0x4>, - <0x0 0x1 0x4>, - <0x0 0x2 0x4>, - <0x0 0x3 0x4>, - <0x0 0x4 0x4>, - <0x0 0x5 0x4>, - <0x0 0x6 0x4>, - <0x0 0x7 0x4>; - }; - - i2cslimpro { - compatible = "apm,xgene-slimpro-i2c"; - mboxes = <&mailbox 0>; - }; - - hwmonslimpro { - compatible = "apm,xgene-slimpro-hwmon"; - mboxes = <&mailbox 7>; - }; - - serial0: serial@1c020000 { - status = "disabled"; - device_type = "serial"; - compatible = "ns16550a"; - reg = <0 0x1c020000 0x0 0x1000>; - reg-shift = <2>; - clock-frequency = <10000000>; /* Updated by bootloader */ - interrupt-parent = <&gic>; - interrupts = <0x0 0x4c 0x4>; - }; - - serial1: serial@1c021000 { - status = "disabled"; - device_type = "serial"; - compatible = "ns16550a"; - reg = <0 0x1c021000 0x0 0x1000>; - reg-shift = <2>; - clock-frequency = <10000000>; /* Updated by bootloader */ - interrupt-parent = <&gic>; - interrupts = <0x0 0x4d 0x4>; - }; - - serial2: serial@1c022000 { - status = "disabled"; - device_type = "serial"; - compatible = "ns16550a"; - reg = <0 0x1c022000 0x0 0x1000>; - reg-shift = <2>; - clock-frequency = <10000000>; /* Updated by bootloader */ - interrupt-parent = <&gic>; - interrupts = <0x0 0x4e 0x4>; - }; - - serial3: serial@1c023000 { - status = "disabled"; - device_type = "serial"; - compatible = "ns16550a"; - reg = <0 0x1c023000 0x0 0x1000>; - reg-shift = <2>; - clock-frequency = <10000000>; /* Updated by bootloader */ - interrupt-parent = <&gic>; - interrupts = <0x0 0x4f 0x4>; - }; - - mmc0: mmc@1c000000 { - compatible = "arasan,sdhci-4.9a"; - reg = <0x0 0x1c000000 0x0 0x100>; - interrupts = <0x0 0x49 0x4>; - dma-coherent; - no-1-8-v; - clock-names = "clk_xin", "clk_ahb"; - clocks = <&sdioclk 0>, <&ahbclk 0>; - }; - - gfcgpio: gpio0@1701c000 { - compatible = "apm,xgene-gpio"; - reg = <0x0 0x1701c000 0x0 0x40>; - gpio-controller; - #gpio-cells = <2>; - }; - - dwgpio: gpio@1c024000 { - compatible = "snps,dw-apb-gpio"; - reg = <0x0 0x1c024000 0x0 0x1000>; - reg-io-width = <4>; - #address-cells = <1>; - #size-cells = <0>; - - porta: gpio-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - snps,nr-gpios = <32>; - reg = <0>; - }; - }; - - i2c0: i2c@10512000 { - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0x0 0x10512000 0x0 0x1000>; - interrupts = <0 0x44 0x4>; - #clock-cells = <1>; - clocks = <&ahbclk 0>; - bus_num = <0>; - }; - - phy1: phy@1f21a000 { - compatible = "apm,xgene-phy"; - reg = <0x0 0x1f21a000 0x0 0x100>; - #phy-cells = <1>; - clocks = <&sataphy1clk 0>; - status = "disabled"; - apm,tx-boost-gain = <30 30 30 30 30 30>; - apm,tx-eye-tuning = <2 10 10 2 10 10>; - }; - - phy2: phy@1f22a000 { - compatible = "apm,xgene-phy"; - reg = <0x0 0x1f22a000 0x0 0x100>; - #phy-cells = <1>; - clocks = <&sataphy2clk 0>; - status = "ok"; - apm,tx-boost-gain = <30 30 30 30 30 30>; - apm,tx-eye-tuning = <1 10 10 2 10 10>; - }; - - phy3: phy@1f23a000 { - compatible = "apm,xgene-phy"; - reg = <0x0 0x1f23a000 0x0 0x100>; - #phy-cells = <1>; - clocks = <&sataphy3clk 0>; - status = "ok"; - apm,tx-boost-gain = <31 31 31 31 31 31>; - apm,tx-eye-tuning = <2 10 10 2 10 10>; - }; - - sata1: sata@1a000000 { - compatible = "apm,xgene-ahci"; - reg = <0x0 0x1a000000 0x0 0x1000>, - <0x0 0x1f210000 0x0 0x1000>, - <0x0 0x1f21d000 0x0 0x1000>, - <0x0 0x1f21e000 0x0 0x1000>, - <0x0 0x1f217000 0x0 0x1000>; - interrupts = <0x0 0x86 0x4>; - dma-coherent; - status = "disabled"; - clocks = <&sata01clk 0>; - phys = <&phy1 0>; - phy-names = "sata-phy"; - }; - - sata2: sata@1a400000 { - compatible = "apm,xgene-ahci"; - reg = <0x0 0x1a400000 0x0 0x1000>, - <0x0 0x1f220000 0x0 0x1000>, - <0x0 0x1f22d000 0x0 0x1000>, - <0x0 0x1f22e000 0x0 0x1000>, - <0x0 0x1f227000 0x0 0x1000>; - interrupts = <0x0 0x87 0x4>; - dma-coherent; - status = "ok"; - clocks = <&sata23clk 0>; - phys = <&phy2 0>; - phy-names = "sata-phy"; - }; - - sata3: sata@1a800000 { - compatible = "apm,xgene-ahci"; - reg = <0x0 0x1a800000 0x0 0x1000>, - <0x0 0x1f230000 0x0 0x1000>, - <0x0 0x1f23d000 0x0 0x1000>, - <0x0 0x1f23e000 0x0 0x1000>; - interrupts = <0x0 0x88 0x4>; - dma-coherent; - status = "ok"; - clocks = <&sata45clk 0>; - phys = <&phy3 0>; - phy-names = "sata-phy"; - }; - - /* Do not change dwusb name, coded for backward compatibility */ - usb0: dwusb@19000000 { - status = "disabled"; - compatible = "snps,dwc3"; - reg = <0x0 0x19000000 0x0 0x100000>; - interrupts = <0x0 0x89 0x4>; - dma-coherent; - dr_mode = "host"; - }; - - usb1: dwusb@19800000 { - status = "disabled"; - compatible = "snps,dwc3"; - reg = <0x0 0x19800000 0x0 0x100000>; - interrupts = <0x0 0x8a 0x4>; - dma-coherent; - dr_mode = "host"; - }; - - sbgpio: gpio@17001000{ - compatible = "apm,xgene-gpio-sb"; - reg = <0x0 0x17001000 0x0 0x400>; - #gpio-cells = <2>; - gpio-controller; - interrupts = <0x0 0x28 0x1>, - <0x0 0x29 0x1>, - <0x0 0x2a 0x1>, - <0x0 0x2b 0x1>, - <0x0 0x2c 0x1>, - <0x0 0x2d 0x1>; - interrupt-parent = <&gic>; - #interrupt-cells = <2>; - interrupt-controller; - }; - - rtc: rtc@10510000 { - compatible = "apm,xgene-rtc"; - reg = <0x0 0x10510000 0x0 0x400>; - interrupts = <0x0 0x46 0x4>; - #clock-cells = <1>; - clocks = <&rtcclk 0>; - }; - - mdio: mdio@17020000 { - compatible = "apm,xgene-mdio-rgmii"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x17020000 0x0 0xd100>; - clocks = <&menetclk 0>; - }; - - menet: ethernet@17020000 { - compatible = "apm,xgene-enet"; - status = "disabled"; - reg = <0x0 0x17020000 0x0 0xd100>, - <0x0 0x17030000 0x0 0xc300>, - <0x0 0x10000000 0x0 0x200>; - reg-names = "enet_csr", "ring_csr", "ring_cmd"; - interrupts = <0x0 0x3c 0x4>; - dma-coherent; - clocks = <&menetclk 0>; - /* mac address will be overwritten by the bootloader */ - local-mac-address = [00 00 00 00 00 00]; - phy-connection-type = "rgmii"; - phy-handle = <&menetphy>,<&menet0phy>; - mdio { - compatible = "apm,xgene-mdio"; - #address-cells = <1>; - #size-cells = <0>; - menetphy: menetphy@3 { - compatible = "ethernet-phy-id001c.c915"; - reg = <0x3>; - }; - - }; - }; - - sgenet0: ethernet@1f210000 { - compatible = "apm,xgene1-sgenet"; - status = "disabled"; - reg = <0x0 0x1f210000 0x0 0xd100>, - <0x0 0x1f200000 0x0 0xc300>, - <0x0 0x1b000000 0x0 0x200>; - reg-names = "enet_csr", "ring_csr", "ring_cmd"; - interrupts = <0x0 0xa0 0x4>, - <0x0 0xa1 0x4>; - dma-coherent; - clocks = <&sge0clk 0>; - local-mac-address = [00 00 00 00 00 00]; - phy-connection-type = "sgmii"; - phy-handle = <&sgenet0phy>; - }; - - sgenet1: ethernet@1f210030 { - compatible = "apm,xgene1-sgenet"; - status = "disabled"; - reg = <0x0 0x1f210030 0x0 0xd100>, - <0x0 0x1f200000 0x0 0xc300>, - <0x0 0x1b000000 0x0 0x8000>; - reg-names = "enet_csr", "ring_csr", "ring_cmd"; - interrupts = <0x0 0xac 0x4>, - <0x0 0xad 0x4>; - port-id = <1>; - dma-coherent; - local-mac-address = [00 00 00 00 00 00]; - phy-connection-type = "sgmii"; - phy-handle = <&sgenet1phy>; - }; - - xgenet: ethernet@1f610000 { - compatible = "apm,xgene1-xgenet"; - status = "disabled"; - reg = <0x0 0x1f610000 0x0 0xd100>, - <0x0 0x1f600000 0x0 0xc300>, - <0x0 0x18000000 0x0 0x200>; - reg-names = "enet_csr", "ring_csr", "ring_cmd"; - interrupts = <0x0 0x60 0x4>, - <0x0 0x61 0x4>, - <0x0 0x62 0x4>, - <0x0 0x63 0x4>, - <0x0 0x64 0x4>, - <0x0 0x65 0x4>, - <0x0 0x66 0x4>, - <0x0 0x67 0x4>; - channel = <0>; - dma-coherent; - clocks = <&xge0clk 0>; - /* mac address will be overwritten by the bootloader */ - local-mac-address = [00 00 00 00 00 00]; - phy-connection-type = "xgmii"; - }; - - xgenet1: ethernet@1f620000 { - compatible = "apm,xgene1-xgenet"; - status = "disabled"; - reg = <0x0 0x1f620000 0x0 0xd100>, - <0x0 0x1f600000 0x0 0xc300>, - <0x0 0x18000000 0x0 0x8000>; - reg-names = "enet_csr", "ring_csr", "ring_cmd"; - interrupts = <0x0 0x6c 0x4>, - <0x0 0x6d 0x4>; - port-id = <1>; - dma-coherent; - clocks = <&xge1clk 0>; - /* mac address will be overwritten by the bootloader */ - local-mac-address = [00 00 00 00 00 00]; - phy-connection-type = "xgmii"; - }; - - rng: rng@10520000 { - compatible = "apm,xgene-rng"; - reg = <0x0 0x10520000 0x0 0x100>; - interrupts = <0x0 0x41 0x4>; - clocks = <&rngpkaclk 0>; - }; - - dma: dma@1f270000 { - compatible = "apm,xgene-storm-dma"; - device_type = "dma"; - reg = <0x0 0x1f270000 0x0 0x10000>, - <0x0 0x1f200000 0x0 0x10000>, - <0x0 0x1b000000 0x0 0x400000>, - <0x0 0x1054a000 0x0 0x100>; - interrupts = <0x0 0x82 0x4>, - <0x0 0xb8 0x4>, - <0x0 0xb9 0x4>, - <0x0 0xba 0x4>, - <0x0 0xbb 0x4>; - dma-coherent; - clocks = <&dmaclk 0>; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/arm/foundation-v8-gicv2.dtsi b/sys/gnu/dts/arm64/arm/foundation-v8-gicv2.dtsi deleted file mode 100644 index 15fe81738e9..00000000000 --- a/sys/gnu/dts/arm64/arm/foundation-v8-gicv2.dtsi +++ /dev/null @@ -1,19 +0,0 @@ -/* - * ARM Ltd. - * - * ARMv8 Foundation model DTS (GICv2 configuration) - */ - -/ { - gic: interrupt-controller@2c001000 { - compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <2>; - interrupt-controller; - reg = <0x0 0x2c001000 0 0x1000>, - <0x0 0x2c002000 0 0x2000>, - <0x0 0x2c004000 0 0x2000>, - <0x0 0x2c006000 0 0x2000>; - interrupts = ; - }; -}; diff --git a/sys/gnu/dts/arm64/arm/foundation-v8-gicv3-psci.dts b/sys/gnu/dts/arm64/arm/foundation-v8-gicv3-psci.dts deleted file mode 100644 index e096e670bec..00000000000 --- a/sys/gnu/dts/arm64/arm/foundation-v8-gicv3-psci.dts +++ /dev/null @@ -1,9 +0,0 @@ -/* - * ARM Ltd. - * - * ARMv8 Foundation model DTS (GICv3+PSCI configuration) - */ - -#include "foundation-v8.dtsi" -#include "foundation-v8-gicv3.dtsi" -#include "foundation-v8-psci.dtsi" diff --git a/sys/gnu/dts/arm64/arm/foundation-v8-gicv3.dts b/sys/gnu/dts/arm64/arm/foundation-v8-gicv3.dts deleted file mode 100644 index c87380e87f5..00000000000 --- a/sys/gnu/dts/arm64/arm/foundation-v8-gicv3.dts +++ /dev/null @@ -1,10 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * ARM Ltd. - * - * ARMv8 Foundation model DTS (GICv3 configuration) - */ - -#include "foundation-v8.dtsi" -#include "foundation-v8-gicv3.dtsi" -#include "foundation-v8-spin-table.dtsi" diff --git a/sys/gnu/dts/arm64/arm/foundation-v8-gicv3.dtsi b/sys/gnu/dts/arm64/arm/foundation-v8-gicv3.dtsi deleted file mode 100644 index f2c75c75603..00000000000 --- a/sys/gnu/dts/arm64/arm/foundation-v8-gicv3.dtsi +++ /dev/null @@ -1,28 +0,0 @@ -/* - * ARM Ltd. - * - * ARMv8 Foundation model DTS (GICv3 configuration) - */ - -/ { - gic: interrupt-controller@2f000000 { - compatible = "arm,gic-v3"; - #interrupt-cells = <3>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - interrupt-controller; - reg = <0x0 0x2f000000 0x0 0x10000>, - <0x0 0x2f100000 0x0 0x200000>, - <0x0 0x2c000000 0x0 0x2000>, - <0x0 0x2c010000 0x0 0x2000>, - <0x0 0x2c02f000 0x0 0x2000>; - interrupts = ; - - its: its@2f020000 { - compatible = "arm,gic-v3-its"; - msi-controller; - reg = <0x0 0x2f020000 0x0 0x20000>; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/arm/foundation-v8-psci.dts b/sys/gnu/dts/arm64/arm/foundation-v8-psci.dts deleted file mode 100644 index 723f23c7cd3..00000000000 --- a/sys/gnu/dts/arm64/arm/foundation-v8-psci.dts +++ /dev/null @@ -1,9 +0,0 @@ -/* - * ARM Ltd. - * - * ARMv8 Foundation model DTS (GICv2+PSCI configuration) - */ - -#include "foundation-v8.dtsi" -#include "foundation-v8-gicv2.dtsi" -#include "foundation-v8-psci.dtsi" diff --git a/sys/gnu/dts/arm64/arm/foundation-v8-psci.dtsi b/sys/gnu/dts/arm64/arm/foundation-v8-psci.dtsi deleted file mode 100644 index 16cdf395728..00000000000 --- a/sys/gnu/dts/arm64/arm/foundation-v8-psci.dtsi +++ /dev/null @@ -1,28 +0,0 @@ -/* - * ARM Ltd. - * - * ARMv8 Foundation model DTS (PSCI configuration) - */ - -/ { - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; -}; - -&cpu0 { - enable-method = "psci"; -}; - -&cpu1 { - enable-method = "psci"; -}; - -&cpu2 { - enable-method = "psci"; -}; - -&cpu3 { - enable-method = "psci"; -}; diff --git a/sys/gnu/dts/arm64/arm/foundation-v8-spin-table.dtsi b/sys/gnu/dts/arm64/arm/foundation-v8-spin-table.dtsi deleted file mode 100644 index 4d4186ba0e8..00000000000 --- a/sys/gnu/dts/arm64/arm/foundation-v8-spin-table.dtsi +++ /dev/null @@ -1,25 +0,0 @@ -/* - * ARM Ltd. - * - * ARMv8 Foundation model DTS (spin table configuration) - */ - -&cpu0 { - enable-method = "spin-table"; - cpu-release-addr = <0x0 0x8000fff8>; -}; - -&cpu1 { - enable-method = "spin-table"; - cpu-release-addr = <0x0 0x8000fff8>; -}; - -&cpu2 { - enable-method = "spin-table"; - cpu-release-addr = <0x0 0x8000fff8>; -}; - -&cpu3 { - enable-method = "spin-table"; - cpu-release-addr = <0x0 0x8000fff8>; -}; diff --git a/sys/gnu/dts/arm64/arm/foundation-v8.dts b/sys/gnu/dts/arm64/arm/foundation-v8.dts deleted file mode 100644 index b17347d75ec..00000000000 --- a/sys/gnu/dts/arm64/arm/foundation-v8.dts +++ /dev/null @@ -1,10 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * ARM Ltd. - * - * ARMv8 Foundation model DTS (GICv2 configuration) - */ - -#include "foundation-v8.dtsi" -#include "foundation-v8-gicv2.dtsi" -#include "foundation-v8-spin-table.dtsi" diff --git a/sys/gnu/dts/arm64/arm/foundation-v8.dtsi b/sys/gnu/dts/arm64/arm/foundation-v8.dtsi deleted file mode 100644 index 3f78373f708..00000000000 --- a/sys/gnu/dts/arm64/arm/foundation-v8.dtsi +++ /dev/null @@ -1,231 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * ARM Ltd. - * - * ARMv8 Foundation model DTS - */ - -/dts-v1/; - -#include - -/memreserve/ 0x80000000 0x00010000; - -/ { - model = "Foundation-v8A"; - compatible = "arm,foundation-aarch64", "arm,vexpress"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - chosen { }; - - aliases { - serial0 = &v2m_serial0; - serial1 = &v2m_serial1; - serial2 = &v2m_serial2; - serial3 = &v2m_serial3; - }; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x0>; - next-level-cache = <&L2_0>; - }; - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x1>; - next-level-cache = <&L2_0>; - }; - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x2>; - next-level-cache = <&L2_0>; - }; - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x3>; - next-level-cache = <&L2_0>; - }; - - L2_0: l2-cache0 { - compatible = "cache"; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x00000000 0x80000000 0 0x80000000>, - <0x00000008 0x80000000 0 0x80000000>; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - clock-frequency = <100000000>; - }; - - pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = , - , - , - ; - }; - - watchdog@2a440000 { - compatible = "arm,sbsa-gwdt"; - reg = <0x0 0x2a440000 0 0x1000>, - <0x0 0x2a450000 0 0x1000>; - interrupts = ; - timeout-sec = <30>; - }; - - smb@8000000 { - compatible = "arm,vexpress,v2m-p1", "simple-bus"; - arm,v2m-memory-map = "rs1"; - #address-cells = <2>; /* SMB chipselect number and offset */ - #size-cells = <1>; - - ranges = <0 0 0 0x08000000 0x04000000>, - <1 0 0 0x14000000 0x04000000>, - <2 0 0 0x18000000 0x04000000>, - <3 0 0 0x1c000000 0x04000000>, - <4 0 0 0x0c000000 0x04000000>, - <5 0 0 0x10000000 0x04000000>; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 63>; - interrupt-map = <0 0 0 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, - <0 0 1 &gic 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, - <0 0 2 &gic 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, - <0 0 3 &gic 0 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, - <0 0 4 &gic 0 0 GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, - <0 0 5 &gic 0 0 GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, - <0 0 6 &gic 0 0 GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, - <0 0 7 &gic 0 0 GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, - <0 0 8 &gic 0 0 GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, - <0 0 9 &gic 0 0 GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, - <0 0 10 &gic 0 0 GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, - <0 0 11 &gic 0 0 GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, - <0 0 12 &gic 0 0 GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, - <0 0 13 &gic 0 0 GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, - <0 0 14 &gic 0 0 GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, - <0 0 15 &gic 0 0 GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, - <0 0 16 &gic 0 0 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, - <0 0 17 &gic 0 0 GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, - <0 0 18 &gic 0 0 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, - <0 0 19 &gic 0 0 GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, - <0 0 20 &gic 0 0 GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, - <0 0 21 &gic 0 0 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, - <0 0 22 &gic 0 0 GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, - <0 0 23 &gic 0 0 GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, - <0 0 24 &gic 0 0 GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, - <0 0 25 &gic 0 0 GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, - <0 0 26 &gic 0 0 GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, - <0 0 27 &gic 0 0 GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, - <0 0 28 &gic 0 0 GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, - <0 0 29 &gic 0 0 GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, - <0 0 30 &gic 0 0 GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, - <0 0 31 &gic 0 0 GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, - <0 0 32 &gic 0 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, - <0 0 33 &gic 0 0 GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, - <0 0 34 &gic 0 0 GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, - <0 0 35 &gic 0 0 GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, - <0 0 36 &gic 0 0 GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, - <0 0 37 &gic 0 0 GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, - <0 0 38 &gic 0 0 GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, - <0 0 39 &gic 0 0 GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, - <0 0 40 &gic 0 0 GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, - <0 0 41 &gic 0 0 GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, - <0 0 42 &gic 0 0 GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; - - ethernet@2,02000000 { - compatible = "smsc,lan91c111"; - reg = <2 0x02000000 0x10000>; - interrupts = <15>; - }; - - v2m_clk24mhz: clk24mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "v2m:clk24mhz"; - }; - - v2m_refclk1mhz: refclk1mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <1000000>; - clock-output-names = "v2m:refclk1mhz"; - }; - - v2m_refclk32khz: refclk32khz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "v2m:refclk32khz"; - }; - - iofpga@3,00000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 3 0 0x200000>; - - v2m_sysreg: sysreg@10000 { - compatible = "arm,vexpress-sysreg"; - reg = <0x010000 0x1000>; - }; - - v2m_serial0: uart@90000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x090000 0x1000>; - interrupts = <5>; - clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; - clock-names = "uartclk", "apb_pclk"; - }; - - v2m_serial1: uart@a0000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0a0000 0x1000>; - interrupts = <6>; - clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; - clock-names = "uartclk", "apb_pclk"; - }; - - v2m_serial2: uart@b0000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0b0000 0x1000>; - interrupts = <7>; - clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; - clock-names = "uartclk", "apb_pclk"; - }; - - v2m_serial3: uart@c0000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0c0000 0x1000>; - interrupts = <8>; - clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; - clock-names = "uartclk", "apb_pclk"; - }; - - virtio-block@130000 { - compatible = "virtio,mmio"; - reg = <0x130000 0x200>; - interrupts = <42>; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/arm/fvp-base-revc.dts b/sys/gnu/dts/arm64/arm/fvp-base-revc.dts deleted file mode 100644 index 335fff76245..00000000000 --- a/sys/gnu/dts/arm64/arm/fvp-base-revc.dts +++ /dev/null @@ -1,269 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * ARM Ltd. Fast Models - * - * Architecture Envelope Model (AEM) ARMv8-A - * ARMAEMv8AMPCT - * - * FVP Base RevC - */ - -/dts-v1/; - -#include - -/memreserve/ 0x80000000 0x00010000; - -#include "rtsm_ve-motherboard.dtsi" -#include "rtsm_ve-motherboard-rs2.dtsi" - -/ { - model = "FVP Base RevC"; - compatible = "arm,fvp-base-revc", "arm,vexpress"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - chosen { }; - - aliases { - serial0 = &v2m_serial0; - serial1 = &v2m_serial1; - serial2 = &v2m_serial2; - serial3 = &v2m_serial3; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x000>; - enable-method = "psci"; - }; - cpu1: cpu@100 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x100>; - enable-method = "psci"; - }; - cpu2: cpu@200 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x200>; - enable-method = "psci"; - }; - cpu3: cpu@300 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x300>; - enable-method = "psci"; - }; - cpu4: cpu@10000 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x10000>; - enable-method = "psci"; - }; - cpu5: cpu@10100 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x10100>; - enable-method = "psci"; - }; - cpu6: cpu@10200 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x10200>; - enable-method = "psci"; - }; - cpu7: cpu@10300 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x10300>; - enable-method = "psci"; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x00000000 0x80000000 0 0x80000000>, - <0x00000008 0x80000000 0 0x80000000>; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - /* Chipselect 2,00000000 is physically at 0x18000000 */ - vram: vram@18000000 { - /* 8 MB of designated video RAM */ - compatible = "shared-dma-pool"; - reg = <0x00000000 0x18000000 0 0x00800000>; - no-map; - }; - }; - - gic: interrupt-controller@2f000000 { - compatible = "arm,gic-v3"; - #interrupt-cells = <3>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - interrupt-controller; - reg = <0x0 0x2f000000 0 0x10000>, // GICD - <0x0 0x2f100000 0 0x200000>, // GICR - <0x0 0x2c000000 0 0x2000>, // GICC - <0x0 0x2c010000 0 0x2000>, // GICH - <0x0 0x2c02f000 0 0x2000>; // GICV - interrupts = ; - - its: its@2f020000 { - #msi-cells = <1>; - compatible = "arm,gic-v3-its"; - reg = <0x0 0x2f020000 0x0 0x20000>; // GITS - msi-controller; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = ; - }; - - spe-pmu { - compatible = "arm,statistical-profiling-extension-v1"; - interrupts = ; - }; - - pci: pci@40000000 { - #address-cells = <0x3>; - #size-cells = <0x2>; - #interrupt-cells = <0x1>; - compatible = "pci-host-ecam-generic"; - device_type = "pci"; - bus-range = <0x0 0x1>; - reg = <0x0 0x40000000 0x0 0x10000000>; - ranges = <0x2000000 0x0 0x50000000 0x0 0x50000000 0x0 0x10000000>; - interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &gic 0 0 GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &gic 0 0 GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &gic 0 0 GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; - interrupt-map-mask = <0x0 0x0 0x0 0x7>; - msi-map = <0x0 &its 0x0 0x10000>; - iommu-map = <0x0 &smmu 0x0 0x10000>; - - dma-coherent; - }; - - smmu: smmu@2b400000 { - compatible = "arm,smmu-v3"; - reg = <0x0 0x2b400000 0x0 0x100000>; - interrupts = , - , - , - ; - interrupt-names = "eventq", "priq", "cmdq-sync", "gerror"; - dma-coherent; - #iommu-cells = <1>; - msi-parent = <&its 0x10000>; - }; - - panel { - compatible = "arm,rtsm-display", "panel-dpi"; - port { - panel_in: endpoint { - remote-endpoint = <&clcd_pads>; - }; - }; - - panel-timing { - clock-frequency = <63500127>; - hactive = <1024>; - hback-porch = <152>; - hfront-porch = <48>; - hsync-len = <104>; - vactive = <768>; - vback-porch = <23>; - vfront-porch = <3>; - vsync-len = <4>; - }; - }; - - smb@8000000 { - compatible = "simple-bus"; - - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0 0x08000000 0x04000000>, - <1 0 0 0x14000000 0x04000000>, - <2 0 0 0x18000000 0x04000000>, - <3 0 0 0x1c000000 0x04000000>, - <4 0 0 0x0c000000 0x04000000>, - <5 0 0 0x10000000 0x04000000>; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 63>; - interrupt-map = <0 0 0 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, - <0 0 1 &gic 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, - <0 0 2 &gic 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, - <0 0 3 &gic 0 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, - <0 0 4 &gic 0 0 GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, - <0 0 5 &gic 0 0 GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, - <0 0 6 &gic 0 0 GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, - <0 0 7 &gic 0 0 GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, - <0 0 8 &gic 0 0 GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, - <0 0 9 &gic 0 0 GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, - <0 0 10 &gic 0 0 GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, - <0 0 11 &gic 0 0 GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, - <0 0 12 &gic 0 0 GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, - <0 0 13 &gic 0 0 GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, - <0 0 14 &gic 0 0 GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, - <0 0 15 &gic 0 0 GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, - <0 0 16 &gic 0 0 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, - <0 0 17 &gic 0 0 GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, - <0 0 18 &gic 0 0 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, - <0 0 19 &gic 0 0 GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, - <0 0 20 &gic 0 0 GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, - <0 0 21 &gic 0 0 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, - <0 0 22 &gic 0 0 GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, - <0 0 23 &gic 0 0 GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, - <0 0 24 &gic 0 0 GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, - <0 0 25 &gic 0 0 GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, - <0 0 26 &gic 0 0 GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, - <0 0 27 &gic 0 0 GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, - <0 0 28 &gic 0 0 GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, - <0 0 29 &gic 0 0 GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, - <0 0 30 &gic 0 0 GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, - <0 0 31 &gic 0 0 GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, - <0 0 32 &gic 0 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, - <0 0 33 &gic 0 0 GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, - <0 0 34 &gic 0 0 GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, - <0 0 35 &gic 0 0 GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, - <0 0 36 &gic 0 0 GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, - <0 0 37 &gic 0 0 GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, - <0 0 38 &gic 0 0 GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, - <0 0 39 &gic 0 0 GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, - <0 0 40 &gic 0 0 GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, - <0 0 41 &gic 0 0 GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, - <0 0 42 &gic 0 0 GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, - <0 0 43 &gic 0 0 GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, - <0 0 44 &gic 0 0 GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; - }; -}; diff --git a/sys/gnu/dts/arm64/arm/juno-base.dtsi b/sys/gnu/dts/arm64/arm/juno-base.dtsi deleted file mode 100644 index 1f3c80aafbd..00000000000 --- a/sys/gnu/dts/arm64/arm/juno-base.dtsi +++ /dev/null @@ -1,840 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "juno-clocks.dtsi" -#include "juno-motherboard.dtsi" - -/ { - /* - * Devices shared by all Juno boards - */ - - memtimer: timer@2a810000 { - compatible = "arm,armv7-timer-mem"; - reg = <0x0 0x2a810000 0x0 0x10000>; - clock-frequency = <50000000>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - status = "disabled"; - frame@2a830000 { - frame-number = <1>; - interrupts = ; - reg = <0x0 0x2a830000 0x0 0x10000>; - }; - }; - - mailbox: mhu@2b1f0000 { - compatible = "arm,mhu", "arm,primecell"; - reg = <0x0 0x2b1f0000 0x0 0x1000>; - interrupts = , - ; - interrupt-names = "mhu_lpri_rx", - "mhu_hpri_rx"; - #mbox-cells = <1>; - clocks = <&soc_refclk100mhz>; - clock-names = "apb_pclk"; - }; - - smmu_gpu: iommu@2b400000 { - compatible = "arm,mmu-400", "arm,smmu-v1"; - reg = <0x0 0x2b400000 0x0 0x10000>; - interrupts = , - ; - #iommu-cells = <1>; - #global-interrupts = <1>; - power-domains = <&scpi_devpd 1>; - dma-coherent; - status = "disabled"; - }; - - smmu_pcie: iommu@2b500000 { - compatible = "arm,mmu-401", "arm,smmu-v1"; - reg = <0x0 0x2b500000 0x0 0x10000>; - interrupts = , - ; - #iommu-cells = <1>; - #global-interrupts = <1>; - dma-coherent; - status = "disabled"; - }; - - smmu_etr: iommu@2b600000 { - compatible = "arm,mmu-401", "arm,smmu-v1"; - reg = <0x0 0x2b600000 0x0 0x10000>; - interrupts = , - ; - #iommu-cells = <1>; - #global-interrupts = <1>; - dma-coherent; - power-domains = <&scpi_devpd 0>; - }; - - gic: interrupt-controller@2c010000 { - compatible = "arm,gic-400", "arm,cortex-a15-gic"; - reg = <0x0 0x2c010000 0 0x1000>, - <0x0 0x2c02f000 0 0x2000>, - <0x0 0x2c04f000 0 0x2000>, - <0x0 0x2c06f000 0 0x2000>; - #address-cells = <2>; - #interrupt-cells = <3>; - #size-cells = <2>; - interrupt-controller; - interrupts = ; - ranges = <0 0 0 0x2c1c0000 0 0x40000>; - - v2m_0: v2m@0 { - compatible = "arm,gic-v2m-frame"; - msi-controller; - reg = <0 0 0 0x10000>; - }; - - v2m@10000 { - compatible = "arm,gic-v2m-frame"; - msi-controller; - reg = <0 0x10000 0 0x10000>; - }; - - v2m@20000 { - compatible = "arm,gic-v2m-frame"; - msi-controller; - reg = <0 0x20000 0 0x10000>; - }; - - v2m@30000 { - compatible = "arm,gic-v2m-frame"; - msi-controller; - reg = <0 0x30000 0 0x10000>; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - /* - * Juno TRMs specify the size for these coresight components as 64K. - * The actual size is just 4K though 64K is reserved. Access to the - * unmapped reserved region results in a DECERR response. - */ - etf@20010000 { /* etf0 */ - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0 0x20010000 0 0x1000>; - - clocks = <&soc_smc50mhz>; - clock-names = "apb_pclk"; - power-domains = <&scpi_devpd 0>; - - in-ports { - port { - etf0_in_port: endpoint { - remote-endpoint = <&main_funnel_out_port>; - }; - }; - }; - - out-ports { - port { - etf0_out_port: endpoint { - }; - }; - }; - }; - - tpiu@20030000 { - compatible = "arm,coresight-tpiu", "arm,primecell"; - reg = <0 0x20030000 0 0x1000>; - - clocks = <&soc_smc50mhz>; - clock-names = "apb_pclk"; - power-domains = <&scpi_devpd 0>; - in-ports { - port { - tpiu_in_port: endpoint { - remote-endpoint = <&replicator_out_port0>; - }; - }; - }; - }; - - /* main funnel on Juno r0, cssys0 funnel on Juno r1/r2 as per TRM*/ - main_funnel: funnel@20040000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0x20040000 0 0x1000>; - - clocks = <&soc_smc50mhz>; - clock-names = "apb_pclk"; - power-domains = <&scpi_devpd 0>; - - out-ports { - port { - main_funnel_out_port: endpoint { - remote-endpoint = <&etf0_in_port>; - }; - }; - }; - - main_funnel_in_ports: in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - main_funnel_in_port0: endpoint { - remote-endpoint = <&cluster0_funnel_out_port>; - }; - }; - - port@1 { - reg = <1>; - main_funnel_in_port1: endpoint { - remote-endpoint = <&cluster1_funnel_out_port>; - }; - }; - }; - }; - - etr@20070000 { - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0 0x20070000 0 0x1000>; - iommus = <&smmu_etr 0>; - - clocks = <&soc_smc50mhz>; - clock-names = "apb_pclk"; - power-domains = <&scpi_devpd 0>; - arm,scatter-gather; - in-ports { - port { - etr_in_port: endpoint { - remote-endpoint = <&replicator_out_port1>; - }; - }; - }; - }; - - stm@20100000 { - compatible = "arm,coresight-stm", "arm,primecell"; - reg = <0 0x20100000 0 0x1000>, - <0 0x28000000 0 0x1000000>; - reg-names = "stm-base", "stm-stimulus-base"; - - clocks = <&soc_smc50mhz>; - clock-names = "apb_pclk"; - power-domains = <&scpi_devpd 0>; - out-ports { - port { - stm_out_port: endpoint { - }; - }; - }; - }; - - replicator@20120000 { - compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; - reg = <0 0x20120000 0 0x1000>; - - clocks = <&soc_smc50mhz>; - clock-names = "apb_pclk"; - power-domains = <&scpi_devpd 0>; - - out-ports { - #address-cells = <1>; - #size-cells = <0>; - - /* replicator output ports */ - port@0 { - reg = <0>; - replicator_out_port0: endpoint { - remote-endpoint = <&tpiu_in_port>; - }; - }; - - port@1 { - reg = <1>; - replicator_out_port1: endpoint { - remote-endpoint = <&etr_in_port>; - }; - }; - }; - in-ports { - port { - replicator_in_port0: endpoint { - }; - }; - }; - }; - - cpu_debug0: cpu-debug@22010000 { - compatible = "arm,coresight-cpu-debug", "arm,primecell"; - reg = <0x0 0x22010000 0x0 0x1000>; - - clocks = <&soc_smc50mhz>; - clock-names = "apb_pclk"; - power-domains = <&scpi_devpd 0>; - }; - - etm0: etm@22040000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x22040000 0 0x1000>; - - clocks = <&soc_smc50mhz>; - clock-names = "apb_pclk"; - power-domains = <&scpi_devpd 0>; - out-ports { - port { - cluster0_etm0_out_port: endpoint { - remote-endpoint = <&cluster0_funnel_in_port0>; - }; - }; - }; - }; - - funnel@220c0000 { /* cluster0 funnel */ - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0x220c0000 0 0x1000>; - - clocks = <&soc_smc50mhz>; - clock-names = "apb_pclk"; - power-domains = <&scpi_devpd 0>; - out-ports { - port { - cluster0_funnel_out_port: endpoint { - remote-endpoint = <&main_funnel_in_port0>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - cluster0_funnel_in_port0: endpoint { - remote-endpoint = <&cluster0_etm0_out_port>; - }; - }; - - port@1 { - reg = <1>; - cluster0_funnel_in_port1: endpoint { - remote-endpoint = <&cluster0_etm1_out_port>; - }; - }; - }; - }; - - cpu_debug1: cpu-debug@22110000 { - compatible = "arm,coresight-cpu-debug", "arm,primecell"; - reg = <0x0 0x22110000 0x0 0x1000>; - - clocks = <&soc_smc50mhz>; - clock-names = "apb_pclk"; - power-domains = <&scpi_devpd 0>; - }; - - etm1: etm@22140000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x22140000 0 0x1000>; - - clocks = <&soc_smc50mhz>; - clock-names = "apb_pclk"; - power-domains = <&scpi_devpd 0>; - out-ports { - port { - cluster0_etm1_out_port: endpoint { - remote-endpoint = <&cluster0_funnel_in_port1>; - }; - }; - }; - }; - - cpu_debug2: cpu-debug@23010000 { - compatible = "arm,coresight-cpu-debug", "arm,primecell"; - reg = <0x0 0x23010000 0x0 0x1000>; - - clocks = <&soc_smc50mhz>; - clock-names = "apb_pclk"; - power-domains = <&scpi_devpd 0>; - }; - - etm2: etm@23040000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x23040000 0 0x1000>; - - clocks = <&soc_smc50mhz>; - clock-names = "apb_pclk"; - power-domains = <&scpi_devpd 0>; - out-ports { - port { - cluster1_etm0_out_port: endpoint { - remote-endpoint = <&cluster1_funnel_in_port0>; - }; - }; - }; - }; - - funnel@230c0000 { /* cluster1 funnel */ - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0x230c0000 0 0x1000>; - - clocks = <&soc_smc50mhz>; - clock-names = "apb_pclk"; - power-domains = <&scpi_devpd 0>; - out-ports { - port { - cluster1_funnel_out_port: endpoint { - remote-endpoint = <&main_funnel_in_port1>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - cluster1_funnel_in_port0: endpoint { - remote-endpoint = <&cluster1_etm0_out_port>; - }; - }; - - port@1 { - reg = <1>; - cluster1_funnel_in_port1: endpoint { - remote-endpoint = <&cluster1_etm1_out_port>; - }; - }; - port@2 { - reg = <2>; - cluster1_funnel_in_port2: endpoint { - remote-endpoint = <&cluster1_etm2_out_port>; - }; - }; - port@3 { - reg = <3>; - cluster1_funnel_in_port3: endpoint { - remote-endpoint = <&cluster1_etm3_out_port>; - }; - }; - }; - }; - - cpu_debug3: cpu-debug@23110000 { - compatible = "arm,coresight-cpu-debug", "arm,primecell"; - reg = <0x0 0x23110000 0x0 0x1000>; - - clocks = <&soc_smc50mhz>; - clock-names = "apb_pclk"; - power-domains = <&scpi_devpd 0>; - }; - - etm3: etm@23140000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x23140000 0 0x1000>; - - clocks = <&soc_smc50mhz>; - clock-names = "apb_pclk"; - power-domains = <&scpi_devpd 0>; - out-ports { - port { - cluster1_etm1_out_port: endpoint { - remote-endpoint = <&cluster1_funnel_in_port1>; - }; - }; - }; - }; - - cpu_debug4: cpu-debug@23210000 { - compatible = "arm,coresight-cpu-debug", "arm,primecell"; - reg = <0x0 0x23210000 0x0 0x1000>; - - clocks = <&soc_smc50mhz>; - clock-names = "apb_pclk"; - power-domains = <&scpi_devpd 0>; - }; - - etm4: etm@23240000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x23240000 0 0x1000>; - - clocks = <&soc_smc50mhz>; - clock-names = "apb_pclk"; - power-domains = <&scpi_devpd 0>; - out-ports { - port { - cluster1_etm2_out_port: endpoint { - remote-endpoint = <&cluster1_funnel_in_port2>; - }; - }; - }; - }; - - cpu_debug5: cpu-debug@23310000 { - compatible = "arm,coresight-cpu-debug", "arm,primecell"; - reg = <0x0 0x23310000 0x0 0x1000>; - - clocks = <&soc_smc50mhz>; - clock-names = "apb_pclk"; - power-domains = <&scpi_devpd 0>; - }; - - etm5: etm@23340000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x23340000 0 0x1000>; - - clocks = <&soc_smc50mhz>; - clock-names = "apb_pclk"; - power-domains = <&scpi_devpd 0>; - out-ports { - port { - cluster1_etm3_out_port: endpoint { - remote-endpoint = <&cluster1_funnel_in_port3>; - }; - }; - }; - }; - - gpu: gpu@2d000000 { - compatible = "arm,juno-mali", "arm,mali-t624"; - reg = <0 0x2d000000 0 0x10000>; - interrupts = , - , - ; - interrupt-names = "gpu", "job", "mmu"; - clocks = <&scpi_dvfs 2>; - power-domains = <&scpi_devpd 1>; - dma-coherent; - /* The SMMU is only really of interest to bare-metal hypervisors */ - /* iommus = <&smmu_gpu 0>; */ - status = "disabled"; - }; - - sram: sram@2e000000 { - compatible = "arm,juno-sram-ns", "mmio-sram"; - reg = <0x0 0x2e000000 0x0 0x8000>; - - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x0 0x2e000000 0x8000>; - - cpu_scp_lpri: scp-shmem@0 { - compatible = "arm,juno-scp-shmem"; - reg = <0x0 0x200>; - }; - - cpu_scp_hpri: scp-shmem@200 { - compatible = "arm,juno-scp-shmem"; - reg = <0x200 0x200>; - }; - }; - - pcie_ctlr: pcie@40000000 { - compatible = "arm,juno-r1-pcie", "plda,xpressrich3-axi", "pci-host-ecam-generic"; - device_type = "pci"; - reg = <0 0x40000000 0 0x10000000>; /* ECAM config space */ - bus-range = <0 255>; - linux,pci-domain = <0>; - #address-cells = <3>; - #size-cells = <2>; - dma-coherent; - ranges = <0x01000000 0x00 0x00000000 0x00 0x5f800000 0x0 0x00800000>, - <0x02000000 0x00 0x50000000 0x00 0x50000000 0x0 0x08000000>, - <0x42000000 0x40 0x00000000 0x40 0x00000000 0x1 0x00000000>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &gic 0 0 GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &gic 0 0 GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &gic 0 0 GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; - msi-parent = <&v2m_0>; - status = "disabled"; - iommu-map-mask = <0x0>; /* RC has no means to output PCI RID */ - iommu-map = <0x0 &smmu_pcie 0x0 0x1>; - }; - - scpi { - compatible = "arm,scpi"; - mboxes = <&mailbox 1>; - shmem = <&cpu_scp_hpri>; - - clocks { - compatible = "arm,scpi-clocks"; - - scpi_dvfs: scpi-dvfs { - compatible = "arm,scpi-dvfs-clocks"; - #clock-cells = <1>; - clock-indices = <0>, <1>, <2>; - clock-output-names = "atlclk", "aplclk","gpuclk"; - }; - scpi_clk: scpi-clk { - compatible = "arm,scpi-variable-clocks"; - #clock-cells = <1>; - clock-indices = <3>; - clock-output-names = "pxlclk"; - }; - }; - - scpi_devpd: scpi-power-domains { - compatible = "arm,scpi-power-domains"; - num-domains = <2>; - #power-domain-cells = <1>; - }; - - scpi_sensors0: sensors { - compatible = "arm,scpi-sensors"; - #thermal-sensor-cells = <1>; - }; - }; - - thermal-zones { - pmic { - polling-delay = <1000>; - polling-delay-passive = <100>; - thermal-sensors = <&scpi_sensors0 0>; - }; - - soc { - polling-delay = <1000>; - polling-delay-passive = <100>; - thermal-sensors = <&scpi_sensors0 3>; - }; - - big_cluster_thermal_zone: big-cluster { - polling-delay = <1000>; - polling-delay-passive = <100>; - thermal-sensors = <&scpi_sensors0 21>; - status = "disabled"; - }; - - little_cluster_thermal_zone: little-cluster { - polling-delay = <1000>; - polling-delay-passive = <100>; - thermal-sensors = <&scpi_sensors0 22>; - status = "disabled"; - }; - - gpu0_thermal_zone: gpu0 { - polling-delay = <1000>; - polling-delay-passive = <100>; - thermal-sensors = <&scpi_sensors0 23>; - status = "disabled"; - }; - - gpu1_thermal_zone: gpu1 { - polling-delay = <1000>; - polling-delay-passive = <100>; - thermal-sensors = <&scpi_sensors0 24>; - status = "disabled"; - }; - }; - - smmu_dma: iommu@7fb00000 { - compatible = "arm,mmu-401", "arm,smmu-v1"; - reg = <0x0 0x7fb00000 0x0 0x10000>; - interrupts = , - ; - #iommu-cells = <1>; - #global-interrupts = <1>; - dma-coherent; - status = "disabled"; - }; - - smmu_hdlcd1: iommu@7fb10000 { - compatible = "arm,mmu-401", "arm,smmu-v1"; - reg = <0x0 0x7fb10000 0x0 0x10000>; - interrupts = , - ; - #iommu-cells = <1>; - #global-interrupts = <1>; - }; - - smmu_hdlcd0: iommu@7fb20000 { - compatible = "arm,mmu-401", "arm,smmu-v1"; - reg = <0x0 0x7fb20000 0x0 0x10000>; - interrupts = , - ; - #iommu-cells = <1>; - #global-interrupts = <1>; - }; - - smmu_usb: iommu@7fb30000 { - compatible = "arm,mmu-401", "arm,smmu-v1"; - reg = <0x0 0x7fb30000 0x0 0x10000>; - interrupts = , - ; - #iommu-cells = <1>; - #global-interrupts = <1>; - dma-coherent; - }; - - dma@7ff00000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x0 0x7ff00000 0 0x1000>; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; - interrupts = , - , - , - , - , - , - , - , - ; - iommus = <&smmu_dma 0>, - <&smmu_dma 1>, - <&smmu_dma 2>, - <&smmu_dma 3>, - <&smmu_dma 4>, - <&smmu_dma 5>, - <&smmu_dma 6>, - <&smmu_dma 7>, - <&smmu_dma 8>; - clocks = <&soc_faxiclk>; - clock-names = "apb_pclk"; - }; - - hdlcd@7ff50000 { - compatible = "arm,hdlcd"; - reg = <0 0x7ff50000 0 0x1000>; - interrupts = ; - iommus = <&smmu_hdlcd1 0>; - clocks = <&scpi_clk 3>; - clock-names = "pxlclk"; - - port { - hdlcd1_output: endpoint { - remote-endpoint = <&tda998x_1_input>; - }; - }; - }; - - hdlcd@7ff60000 { - compatible = "arm,hdlcd"; - reg = <0 0x7ff60000 0 0x1000>; - interrupts = ; - iommus = <&smmu_hdlcd0 0>; - clocks = <&scpi_clk 3>; - clock-names = "pxlclk"; - - port { - hdlcd0_output: endpoint { - remote-endpoint = <&tda998x_0_input>; - }; - }; - }; - - soc_uart0: uart@7ff80000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0 0x7ff80000 0x0 0x1000>; - interrupts = ; - clocks = <&soc_uartclk>, <&soc_refclk100mhz>; - clock-names = "uartclk", "apb_pclk"; - }; - - i2c@7ffa0000 { - compatible = "snps,designware-i2c"; - reg = <0x0 0x7ffa0000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clock-frequency = <400000>; - i2c-sda-hold-time-ns = <500>; - clocks = <&soc_smc50mhz>; - - hdmi-transmitter@70 { - compatible = "nxp,tda998x"; - reg = <0x70>; - port { - tda998x_0_input: endpoint { - remote-endpoint = <&hdlcd0_output>; - }; - }; - }; - - hdmi-transmitter@71 { - compatible = "nxp,tda998x"; - reg = <0x71>; - port { - tda998x_1_input: endpoint { - remote-endpoint = <&hdlcd1_output>; - }; - }; - }; - }; - - ohci@7ffb0000 { - compatible = "generic-ohci"; - reg = <0x0 0x7ffb0000 0x0 0x10000>; - interrupts = ; - iommus = <&smmu_usb 0>; - clocks = <&soc_usb48mhz>; - }; - - ehci@7ffc0000 { - compatible = "generic-ehci"; - reg = <0x0 0x7ffc0000 0x0 0x10000>; - interrupts = ; - iommus = <&smmu_usb 0>; - clocks = <&soc_usb48mhz>; - }; - - memory-controller@7ffd0000 { - compatible = "arm,pl354", "arm,primecell"; - reg = <0 0x7ffd0000 0 0x1000>; - interrupts = , - ; - clocks = <&soc_smc50mhz>; - clock-names = "apb_pclk"; - }; - - memory@80000000 { - device_type = "memory"; - /* last 16MB of the first memory area is reserved for secure world use by firmware */ - reg = <0x00000000 0x80000000 0x0 0x7f000000>, - <0x00000008 0x80000000 0x1 0x80000000>; - }; - - smb@8000000 { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0 0x08000000 0x04000000>, - <1 0 0 0x14000000 0x04000000>, - <2 0 0 0x18000000 0x04000000>, - <3 0 0 0x1c000000 0x04000000>, - <4 0 0 0x0c000000 0x04000000>, - <5 0 0 0x10000000 0x04000000>; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 15>; - interrupt-map = <0 0 0 &gic 0 0 GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, - <0 0 1 &gic 0 0 GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, - <0 0 2 &gic 0 0 GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, - <0 0 3 &gic 0 0 GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, - <0 0 4 &gic 0 0 GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, - <0 0 5 &gic 0 0 GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, - <0 0 6 &gic 0 0 GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, - <0 0 7 &gic 0 0 GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, - <0 0 8 &gic 0 0 GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, - <0 0 9 &gic 0 0 GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, - <0 0 10 &gic 0 0 GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, - <0 0 11 &gic 0 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, - <0 0 12 &gic 0 0 GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; - }; - - site2: tlx@60000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x60000000 0x10000000>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0>; - interrupt-map = <0 0 &gic 0 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; - }; -}; diff --git a/sys/gnu/dts/arm64/arm/juno-clocks.dtsi b/sys/gnu/dts/arm64/arm/juno-clocks.dtsi deleted file mode 100644 index 2870b5eeb19..00000000000 --- a/sys/gnu/dts/arm64/arm/juno-clocks.dtsi +++ /dev/null @@ -1,45 +0,0 @@ -/* - * ARM Juno Platform clocks - * - * Copyright (c) 2013-2014 ARM Ltd - * - * This file is licensed under a dual GPLv2 or BSD license. - * - */ -/ { - /* SoC fixed clocks */ - soc_uartclk: refclk7372800hz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <7372800>; - clock-output-names = "juno:uartclk"; - }; - - soc_usb48mhz: clk48mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <48000000>; - clock-output-names = "clk48mhz"; - }; - - soc_smc50mhz: clk50mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <50000000>; - clock-output-names = "smc_clk"; - }; - - soc_refclk100mhz: refclk100mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - clock-output-names = "apb_pclk"; - }; - - soc_faxiclk: refclk400mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <400000000>; - clock-output-names = "faxi_clk"; - }; -}; diff --git a/sys/gnu/dts/arm64/arm/juno-cs-r1r2.dtsi b/sys/gnu/dts/arm64/arm/juno-cs-r1r2.dtsi deleted file mode 100644 index eda3d9e18af..00000000000 --- a/sys/gnu/dts/arm64/arm/juno-cs-r1r2.dtsi +++ /dev/null @@ -1,85 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/ { - funnel@20130000 { /* cssys1 */ - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0x20130000 0 0x1000>; - - clocks = <&soc_smc50mhz>; - clock-names = "apb_pclk"; - power-domains = <&scpi_devpd 0>; - out-ports { - port { - csys1_funnel_out_port: endpoint { - remote-endpoint = <&etf1_in_port>; - }; - }; - }; - in-ports { - port { - csys1_funnel_in_port0: endpoint { - }; - }; - - }; - }; - - etf@20140000 { /* etf1 */ - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0 0x20140000 0 0x1000>; - - clocks = <&soc_smc50mhz>; - clock-names = "apb_pclk"; - power-domains = <&scpi_devpd 0>; - in-ports { - port { - etf1_in_port: endpoint { - remote-endpoint = <&csys1_funnel_out_port>; - }; - }; - }; - out-ports { - port { - etf1_out_port: endpoint { - remote-endpoint = <&csys2_funnel_in_port1>; - }; - }; - }; - }; - - funnel@20150000 { /* cssys2 */ - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0x20150000 0 0x1000>; - - clocks = <&soc_smc50mhz>; - clock-names = "apb_pclk"; - power-domains = <&scpi_devpd 0>; - out-ports { - port { - csys2_funnel_out_port: endpoint { - remote-endpoint = <&replicator_in_port0>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - csys2_funnel_in_port0: endpoint { - slave-mode; - remote-endpoint = <&etf0_out_port>; - }; - }; - - port@1 { - reg = <1>; - csys2_funnel_in_port1: endpoint { - slave-mode; - remote-endpoint = <&etf1_out_port>; - }; - }; - - }; - }; -}; diff --git a/sys/gnu/dts/arm64/arm/juno-motherboard.dtsi b/sys/gnu/dts/arm64/arm/juno-motherboard.dtsi deleted file mode 100644 index 9f60dacb4f8..00000000000 --- a/sys/gnu/dts/arm64/arm/juno-motherboard.dtsi +++ /dev/null @@ -1,295 +0,0 @@ -/* - * ARM Juno Platform motherboard peripherals - * - * Copyright (c) 2013-2014 ARM Ltd - * - * This file is licensed under a dual GPLv2 or BSD license. - * - */ - -/ { - smb@8000000 { - mb_clk24mhz: clk24mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "juno_mb:clk24mhz"; - }; - - mb_clk25mhz: clk25mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - clock-output-names = "juno_mb:clk25mhz"; - }; - - v2m_refclk1mhz: refclk1mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <1000000>; - clock-output-names = "juno_mb:refclk1mhz"; - }; - - v2m_refclk32khz: refclk32khz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "juno_mb:refclk32khz"; - }; - - motherboard { - compatible = "arm,vexpress,v2p-p1", "simple-bus"; - #address-cells = <2>; /* SMB chipselect number and offset */ - #size-cells = <1>; - #interrupt-cells = <1>; - ranges; - model = "V2M-Juno"; - arm,hbi = <0x252>; - arm,vexpress,site = <0>; - arm,v2m-memory-map = "rs1"; - - mb_fixed_3v3: mcc-sb-3v3 { - compatible = "regulator-fixed"; - regulator-name = "MCC_SB_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - gpio-keys { - compatible = "gpio-keys"; - - power-button { - debounce-interval = <50>; - wakeup-source; - linux,code = <116>; - label = "POWER"; - gpios = <&iofpga_gpio0 0 0x4>; - }; - home-button { - debounce-interval = <50>; - wakeup-source; - linux,code = <102>; - label = "HOME"; - gpios = <&iofpga_gpio0 1 0x4>; - }; - rlock-button { - debounce-interval = <50>; - wakeup-source; - linux,code = <152>; - label = "RLOCK"; - gpios = <&iofpga_gpio0 2 0x4>; - }; - vol-up-button { - debounce-interval = <50>; - wakeup-source; - linux,code = <115>; - label = "VOL+"; - gpios = <&iofpga_gpio0 3 0x4>; - }; - vol-down-button { - debounce-interval = <50>; - wakeup-source; - linux,code = <114>; - label = "VOL-"; - gpios = <&iofpga_gpio0 4 0x4>; - }; - nmi-button { - debounce-interval = <50>; - wakeup-source; - linux,code = <99>; - label = "NMI"; - gpios = <&iofpga_gpio0 5 0x4>; - }; - }; - - flash@0,00000000 { - /* 2 * 32MiB NOR Flash memory mounted on CS0 */ - compatible = "arm,vexpress-flash", "cfi-flash"; - reg = <0 0x00000000 0x04000000>; - bank-width = <4>; - /* - * Unfortunately, accessing the flash disturbs - * the CPU idle states (suspend) and CPU - * hotplug of the platform. For this reason, - * flash hardware access is disabled by default. - */ - status = "disabled"; - partitions { - compatible = "arm,arm-firmware-suite"; - }; - }; - - ethernet@2,00000000 { - compatible = "smsc,lan9118", "smsc,lan9115"; - reg = <2 0x00000000 0x10000>; - interrupts = <3>; - phy-mode = "mii"; - reg-io-width = <4>; - smsc,irq-active-high; - smsc,irq-push-pull; - clocks = <&mb_clk25mhz>; - vdd33a-supply = <&mb_fixed_3v3>; - vddvario-supply = <&mb_fixed_3v3>; - }; - - iofpga@3,00000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 3 0 0x200000>; - - v2m_sysctl: sysctl@20000 { - compatible = "arm,sp810", "arm,primecell"; - reg = <0x020000 0x1000>; - clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&mb_clk24mhz>; - clock-names = "refclk", "timclk", "apb_pclk"; - #clock-cells = <1>; - clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3"; - assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>; - assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>; - }; - - apbregs@10000 { - compatible = "syscon", "simple-mfd"; - reg = <0x010000 0x1000>; - - led0 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x01>; - label = "vexpress:0"; - linux,default-trigger = "heartbeat"; - default-state = "on"; - }; - led1 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x02>; - label = "vexpress:1"; - linux,default-trigger = "mmc0"; - default-state = "off"; - }; - led2 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x04>; - label = "vexpress:2"; - linux,default-trigger = "cpu0"; - default-state = "off"; - }; - led3 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x08>; - label = "vexpress:3"; - linux,default-trigger = "cpu1"; - default-state = "off"; - }; - led4 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x10>; - label = "vexpress:4"; - linux,default-trigger = "cpu2"; - default-state = "off"; - }; - led5 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x20>; - label = "vexpress:5"; - linux,default-trigger = "cpu3"; - default-state = "off"; - }; - led6 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x40>; - label = "vexpress:6"; - default-state = "off"; - }; - led7 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x80>; - label = "vexpress:7"; - default-state = "off"; - }; - }; - - mmci@50000 { - compatible = "arm,pl180", "arm,primecell"; - reg = <0x050000 0x1000>; - interrupts = <5>; - /* cd-gpios = <&v2m_mmc_gpios 0 0>; - wp-gpios = <&v2m_mmc_gpios 1 0>; */ - max-frequency = <12000000>; - vmmc-supply = <&mb_fixed_3v3>; - clocks = <&mb_clk24mhz>, <&soc_smc50mhz>; - clock-names = "mclk", "apb_pclk"; - }; - - kmi@60000 { - compatible = "arm,pl050", "arm,primecell"; - reg = <0x060000 0x1000>; - interrupts = <8>; - clocks = <&mb_clk24mhz>, <&soc_smc50mhz>; - clock-names = "KMIREFCLK", "apb_pclk"; - }; - - kmi@70000 { - compatible = "arm,pl050", "arm,primecell"; - reg = <0x070000 0x1000>; - interrupts = <8>; - clocks = <&mb_clk24mhz>, <&soc_smc50mhz>; - clock-names = "KMIREFCLK", "apb_pclk"; - }; - - wdt@f0000 { - compatible = "arm,sp805", "arm,primecell"; - reg = <0x0f0000 0x10000>; - interrupts = <7>; - clocks = <&mb_clk24mhz>, <&soc_smc50mhz>; - clock-names = "wdogclk", "apb_pclk"; - }; - - v2m_timer01: timer@110000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x110000 0x10000>; - interrupts = <9>; - clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&mb_clk24mhz>; - clock-names = "timclken1", "timclken2", "apb_pclk"; - }; - - v2m_timer23: timer@120000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x120000 0x10000>; - interrupts = <9>; - clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&mb_clk24mhz>; - clock-names = "timclken1", "timclken2", "apb_pclk"; - }; - - rtc@170000 { - compatible = "arm,pl031", "arm,primecell"; - reg = <0x170000 0x10000>; - interrupts = <0>; - clocks = <&soc_smc50mhz>; - clock-names = "apb_pclk"; - }; - - iofpga_gpio0: gpio@1d0000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x1d0000 0x1000>; - interrupts = <6>; - clocks = <&soc_smc50mhz>; - clock-names = "apb_pclk"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/arm/juno-r1.dts b/sys/gnu/dts/arm64/arm/juno-r1.dts deleted file mode 100644 index 5f290090b0c..00000000000 --- a/sys/gnu/dts/arm64/arm/juno-r1.dts +++ /dev/null @@ -1,311 +0,0 @@ -/* - * ARM Ltd. Juno Platform - * - * Copyright (c) 2015 ARM Ltd. - * - * This file is licensed under a dual GPLv2 or BSD license. - */ - -/dts-v1/; - -#include -#include "juno-base.dtsi" -#include "juno-cs-r1r2.dtsi" - -/ { - model = "ARM Juno development board (r1)"; - compatible = "arm,juno-r1", "arm,juno", "arm,vexpress"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - serial0 = &soc_uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu-map { - cluster0 { - core0 { - cpu = <&A57_0>; - }; - core1 { - cpu = <&A57_1>; - }; - }; - - cluster1 { - core0 { - cpu = <&A53_0>; - }; - core1 { - cpu = <&A53_1>; - }; - core2 { - cpu = <&A53_2>; - }; - core3 { - cpu = <&A53_3>; - }; - }; - }; - - idle-states { - entry-method = "psci"; - - CPU_SLEEP_0: cpu-sleep-0 { - compatible = "arm,idle-state"; - arm,psci-suspend-param = <0x0010000>; - local-timer-stop; - entry-latency-us = <300>; - exit-latency-us = <1200>; - min-residency-us = <2000>; - }; - - CLUSTER_SLEEP_0: cluster-sleep-0 { - compatible = "arm,idle-state"; - arm,psci-suspend-param = <0x1010000>; - local-timer-stop; - entry-latency-us = <400>; - exit-latency-us = <1200>; - min-residency-us = <2500>; - }; - }; - - A57_0: cpu@0 { - compatible = "arm,cortex-a57"; - reg = <0x0 0x0>; - device_type = "cpu"; - enable-method = "psci"; - i-cache-size = <0xc000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&A57_L2>; - clocks = <&scpi_dvfs 0>; - cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; - capacity-dmips-mhz = <1024>; - }; - - A57_1: cpu@1 { - compatible = "arm,cortex-a57"; - reg = <0x0 0x1>; - device_type = "cpu"; - enable-method = "psci"; - i-cache-size = <0xc000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&A57_L2>; - clocks = <&scpi_dvfs 0>; - cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; - capacity-dmips-mhz = <1024>; - }; - - A53_0: cpu@100 { - compatible = "arm,cortex-a53"; - reg = <0x0 0x100>; - device_type = "cpu"; - enable-method = "psci"; - i-cache-size = <0x8000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - next-level-cache = <&A53_L2>; - clocks = <&scpi_dvfs 1>; - cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; - capacity-dmips-mhz = <578>; - }; - - A53_1: cpu@101 { - compatible = "arm,cortex-a53"; - reg = <0x0 0x101>; - device_type = "cpu"; - enable-method = "psci"; - i-cache-size = <0x8000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - next-level-cache = <&A53_L2>; - clocks = <&scpi_dvfs 1>; - cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; - capacity-dmips-mhz = <578>; - }; - - A53_2: cpu@102 { - compatible = "arm,cortex-a53"; - reg = <0x0 0x102>; - device_type = "cpu"; - enable-method = "psci"; - i-cache-size = <0x8000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - next-level-cache = <&A53_L2>; - clocks = <&scpi_dvfs 1>; - cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; - capacity-dmips-mhz = <578>; - }; - - A53_3: cpu@103 { - compatible = "arm,cortex-a53"; - reg = <0x0 0x103>; - device_type = "cpu"; - enable-method = "psci"; - i-cache-size = <0x8000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - next-level-cache = <&A53_L2>; - clocks = <&scpi_dvfs 1>; - cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; - capacity-dmips-mhz = <578>; - }; - - A57_L2: l2-cache0 { - compatible = "cache"; - cache-size = <0x200000>; - cache-line-size = <64>; - cache-sets = <2048>; - }; - - A53_L2: l2-cache1 { - compatible = "cache"; - cache-size = <0x100000>; - cache-line-size = <64>; - cache-sets = <1024>; - }; - }; - - pmu-a57 { - compatible = "arm,cortex-a57-pmu"; - interrupts = , - ; - interrupt-affinity = <&A57_0>, - <&A57_1>; - }; - - pmu-a53 { - compatible = "arm,cortex-a53-pmu"; - interrupts = , - , - , - ; - interrupt-affinity = <&A53_0>, - <&A53_1>, - <&A53_2>, - <&A53_3>; - }; -}; - -&memtimer { - status = "okay"; -}; - -&pcie_ctlr { - status = "okay"; -}; - -&etm0 { - cpu = <&A57_0>; -}; - -&etm1 { - cpu = <&A57_1>; -}; - -&etm2 { - cpu = <&A53_0>; -}; - -&etm3 { - cpu = <&A53_1>; -}; - -&etm4 { - cpu = <&A53_2>; -}; - -&etm5 { - cpu = <&A53_3>; -}; - -&big_cluster_thermal_zone { - status = "okay"; -}; - -&little_cluster_thermal_zone { - status = "okay"; -}; - -&gpu0_thermal_zone { - status = "okay"; -}; - -&gpu1_thermal_zone { - status = "okay"; -}; - -&etf0_out_port { - remote-endpoint = <&csys2_funnel_in_port0>; -}; - -&replicator_in_port0 { - remote-endpoint = <&csys2_funnel_out_port>; -}; - -&csys1_funnel_in_port0 { - remote-endpoint = <&stm_out_port>; -}; - -&stm_out_port { - remote-endpoint = <&csys1_funnel_in_port0>; -}; - -&cpu_debug0 { - cpu = <&A57_0>; -}; - -&cpu_debug1 { - cpu = <&A57_1>; -}; - -&cpu_debug2 { - cpu = <&A53_0>; -}; - -&cpu_debug3 { - cpu = <&A53_1>; -}; - -&cpu_debug4 { - cpu = <&A53_2>; -}; - -&cpu_debug5 { - cpu = <&A53_3>; -}; diff --git a/sys/gnu/dts/arm64/arm/juno-r2.dts b/sys/gnu/dts/arm64/arm/juno-r2.dts deleted file mode 100644 index 305300dd521..00000000000 --- a/sys/gnu/dts/arm64/arm/juno-r2.dts +++ /dev/null @@ -1,317 +0,0 @@ -/* - * ARM Ltd. Juno Platform - * - * Copyright (c) 2015 ARM Ltd. - * - * This file is licensed under a dual GPLv2 or BSD license. - */ - -/dts-v1/; - -#include -#include "juno-base.dtsi" -#include "juno-cs-r1r2.dtsi" - -/ { - model = "ARM Juno development board (r2)"; - compatible = "arm,juno-r2", "arm,juno", "arm,vexpress"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - serial0 = &soc_uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu-map { - cluster0 { - core0 { - cpu = <&A72_0>; - }; - core1 { - cpu = <&A72_1>; - }; - }; - - cluster1 { - core0 { - cpu = <&A53_0>; - }; - core1 { - cpu = <&A53_1>; - }; - core2 { - cpu = <&A53_2>; - }; - core3 { - cpu = <&A53_3>; - }; - }; - }; - - idle-states { - entry-method = "psci"; - - CPU_SLEEP_0: cpu-sleep-0 { - compatible = "arm,idle-state"; - arm,psci-suspend-param = <0x0010000>; - local-timer-stop; - entry-latency-us = <300>; - exit-latency-us = <1200>; - min-residency-us = <2000>; - }; - - CLUSTER_SLEEP_0: cluster-sleep-0 { - compatible = "arm,idle-state"; - arm,psci-suspend-param = <0x1010000>; - local-timer-stop; - entry-latency-us = <400>; - exit-latency-us = <1200>; - min-residency-us = <2500>; - }; - }; - - A72_0: cpu@0 { - compatible = "arm,cortex-a72"; - reg = <0x0 0x0>; - device_type = "cpu"; - enable-method = "psci"; - i-cache-size = <0xc000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&A72_L2>; - clocks = <&scpi_dvfs 0>; - cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; - capacity-dmips-mhz = <1024>; - dynamic-power-coefficient = <450>; - }; - - A72_1: cpu@1 { - compatible = "arm,cortex-a72"; - reg = <0x0 0x1>; - device_type = "cpu"; - enable-method = "psci"; - i-cache-size = <0xc000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&A72_L2>; - clocks = <&scpi_dvfs 0>; - cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; - capacity-dmips-mhz = <1024>; - dynamic-power-coefficient = <450>; - }; - - A53_0: cpu@100 { - compatible = "arm,cortex-a53"; - reg = <0x0 0x100>; - device_type = "cpu"; - enable-method = "psci"; - i-cache-size = <0x8000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - next-level-cache = <&A53_L2>; - clocks = <&scpi_dvfs 1>; - cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; - capacity-dmips-mhz = <485>; - dynamic-power-coefficient = <140>; - }; - - A53_1: cpu@101 { - compatible = "arm,cortex-a53"; - reg = <0x0 0x101>; - device_type = "cpu"; - enable-method = "psci"; - i-cache-size = <0x8000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - next-level-cache = <&A53_L2>; - clocks = <&scpi_dvfs 1>; - cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; - capacity-dmips-mhz = <485>; - dynamic-power-coefficient = <140>; - }; - - A53_2: cpu@102 { - compatible = "arm,cortex-a53"; - reg = <0x0 0x102>; - device_type = "cpu"; - enable-method = "psci"; - i-cache-size = <0x8000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - next-level-cache = <&A53_L2>; - clocks = <&scpi_dvfs 1>; - cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; - capacity-dmips-mhz = <485>; - dynamic-power-coefficient = <140>; - }; - - A53_3: cpu@103 { - compatible = "arm,cortex-a53"; - reg = <0x0 0x103>; - device_type = "cpu"; - enable-method = "psci"; - i-cache-size = <0x8000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - next-level-cache = <&A53_L2>; - clocks = <&scpi_dvfs 1>; - cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; - capacity-dmips-mhz = <485>; - dynamic-power-coefficient = <140>; - }; - - A72_L2: l2-cache0 { - compatible = "cache"; - cache-size = <0x200000>; - cache-line-size = <64>; - cache-sets = <2048>; - }; - - A53_L2: l2-cache1 { - compatible = "cache"; - cache-size = <0x100000>; - cache-line-size = <64>; - cache-sets = <1024>; - }; - }; - - pmu-a72 { - compatible = "arm,cortex-a72-pmu"; - interrupts = , - ; - interrupt-affinity = <&A72_0>, - <&A72_1>; - }; - - pmu-a53 { - compatible = "arm,cortex-a53-pmu"; - interrupts = , - , - , - ; - interrupt-affinity = <&A53_0>, - <&A53_1>, - <&A53_2>, - <&A53_3>; - }; -}; - -&memtimer { - status = "okay"; -}; - -&pcie_ctlr { - status = "okay"; -}; - -&etm0 { - cpu = <&A72_0>; -}; - -&etm1 { - cpu = <&A72_1>; -}; - -&etm2 { - cpu = <&A53_0>; -}; - -&etm3 { - cpu = <&A53_1>; -}; - -&etm4 { - cpu = <&A53_2>; -}; - -&etm5 { - cpu = <&A53_3>; -}; - -&big_cluster_thermal_zone { - status = "okay"; -}; - -&little_cluster_thermal_zone { - status = "okay"; -}; - -&gpu0_thermal_zone { - status = "okay"; -}; - -&gpu1_thermal_zone { - status = "okay"; -}; - -&etf0_out_port { - remote-endpoint = <&csys2_funnel_in_port0>; -}; - -&replicator_in_port0 { - remote-endpoint = <&csys2_funnel_out_port>; -}; - -&csys1_funnel_in_port0 { - remote-endpoint = <&stm_out_port>; -}; - -&stm_out_port { - remote-endpoint = <&csys1_funnel_in_port0>; -}; - -&cpu_debug0 { - cpu = <&A72_0>; -}; - -&cpu_debug1 { - cpu = <&A72_1>; -}; - -&cpu_debug2 { - cpu = <&A53_0>; -}; - -&cpu_debug3 { - cpu = <&A53_1>; -}; - -&cpu_debug4 { - cpu = <&A53_2>; -}; - -&cpu_debug5 { - cpu = <&A53_3>; -}; diff --git a/sys/gnu/dts/arm64/arm/juno.dts b/sys/gnu/dts/arm64/arm/juno.dts deleted file mode 100644 index f00cffbd032..00000000000 --- a/sys/gnu/dts/arm64/arm/juno.dts +++ /dev/null @@ -1,297 +0,0 @@ -/* - * ARM Ltd. Juno Platform - * - * Copyright (c) 2013-2014 ARM Ltd. - * - * This file is licensed under a dual GPLv2 or BSD license. - */ - -/dts-v1/; - -#include -#include "juno-base.dtsi" - -/ { - model = "ARM Juno development board (r0)"; - compatible = "arm,juno", "arm,vexpress"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - serial0 = &soc_uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu-map { - cluster0 { - core0 { - cpu = <&A57_0>; - }; - core1 { - cpu = <&A57_1>; - }; - }; - - cluster1 { - core0 { - cpu = <&A53_0>; - }; - core1 { - cpu = <&A53_1>; - }; - core2 { - cpu = <&A53_2>; - }; - core3 { - cpu = <&A53_3>; - }; - }; - }; - - idle-states { - entry-method = "psci"; - - CPU_SLEEP_0: cpu-sleep-0 { - compatible = "arm,idle-state"; - arm,psci-suspend-param = <0x0010000>; - local-timer-stop; - entry-latency-us = <300>; - exit-latency-us = <1200>; - min-residency-us = <2000>; - }; - - CLUSTER_SLEEP_0: cluster-sleep-0 { - compatible = "arm,idle-state"; - arm,psci-suspend-param = <0x1010000>; - local-timer-stop; - entry-latency-us = <400>; - exit-latency-us = <1200>; - min-residency-us = <2500>; - }; - }; - - A57_0: cpu@0 { - compatible = "arm,cortex-a57"; - reg = <0x0 0x0>; - device_type = "cpu"; - enable-method = "psci"; - i-cache-size = <0xc000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&A57_L2>; - clocks = <&scpi_dvfs 0>; - cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; - capacity-dmips-mhz = <1024>; - dynamic-power-coefficient = <530>; - }; - - A57_1: cpu@1 { - compatible = "arm,cortex-a57"; - reg = <0x0 0x1>; - device_type = "cpu"; - enable-method = "psci"; - i-cache-size = <0xc000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&A57_L2>; - clocks = <&scpi_dvfs 0>; - cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; - capacity-dmips-mhz = <1024>; - dynamic-power-coefficient = <530>; - }; - - A53_0: cpu@100 { - compatible = "arm,cortex-a53"; - reg = <0x0 0x100>; - device_type = "cpu"; - enable-method = "psci"; - i-cache-size = <0x8000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - next-level-cache = <&A53_L2>; - clocks = <&scpi_dvfs 1>; - cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; - capacity-dmips-mhz = <578>; - dynamic-power-coefficient = <140>; - }; - - A53_1: cpu@101 { - compatible = "arm,cortex-a53"; - reg = <0x0 0x101>; - device_type = "cpu"; - enable-method = "psci"; - i-cache-size = <0x8000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - next-level-cache = <&A53_L2>; - clocks = <&scpi_dvfs 1>; - cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; - capacity-dmips-mhz = <578>; - dynamic-power-coefficient = <140>; - }; - - A53_2: cpu@102 { - compatible = "arm,cortex-a53"; - reg = <0x0 0x102>; - device_type = "cpu"; - enable-method = "psci"; - i-cache-size = <0x8000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - next-level-cache = <&A53_L2>; - clocks = <&scpi_dvfs 1>; - cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; - capacity-dmips-mhz = <578>; - dynamic-power-coefficient = <140>; - }; - - A53_3: cpu@103 { - compatible = "arm,cortex-a53"; - reg = <0x0 0x103>; - device_type = "cpu"; - enable-method = "psci"; - i-cache-size = <0x8000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - next-level-cache = <&A53_L2>; - clocks = <&scpi_dvfs 1>; - cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; - capacity-dmips-mhz = <578>; - dynamic-power-coefficient = <140>; - }; - - A57_L2: l2-cache0 { - compatible = "cache"; - cache-size = <0x200000>; - cache-line-size = <64>; - cache-sets = <2048>; - }; - - A53_L2: l2-cache1 { - compatible = "cache"; - cache-size = <0x100000>; - cache-line-size = <64>; - cache-sets = <1024>; - }; - }; - - pmu-a57 { - compatible = "arm,cortex-a57-pmu"; - interrupts = , - ; - interrupt-affinity = <&A57_0>, - <&A57_1>; - }; - - pmu-a53 { - compatible = "arm,cortex-a53-pmu"; - interrupts = , - , - , - ; - interrupt-affinity = <&A53_0>, - <&A53_1>, - <&A53_2>, - <&A53_3>; - }; -}; - -&etm0 { - cpu = <&A57_0>; -}; - -&etm1 { - cpu = <&A57_1>; -}; - -&etm2 { - cpu = <&A53_0>; -}; - -&etm3 { - cpu = <&A53_1>; -}; - -&etm4 { - cpu = <&A53_2>; -}; - -&etm5 { - cpu = <&A53_3>; -}; - -&etf0_out_port { - remote-endpoint = <&replicator_in_port0>; -}; - -&replicator_in_port0 { - remote-endpoint = <&etf0_out_port>; -}; - -&stm_out_port { - remote-endpoint = <&main_funnel_in_port2>; -}; - -&main_funnel_in_ports { - port@2 { - reg = <2>; - main_funnel_in_port2: endpoint { - remote-endpoint = <&stm_out_port>; - }; - }; -}; - -&cpu_debug0 { - cpu = <&A57_0>; -}; - -&cpu_debug1 { - cpu = <&A57_1>; -}; - -&cpu_debug2 { - cpu = <&A53_0>; -}; - -&cpu_debug3 { - cpu = <&A53_1>; -}; - -&cpu_debug4 { - cpu = <&A53_2>; -}; - -&cpu_debug5 { - cpu = <&A53_3>; -}; diff --git a/sys/gnu/dts/arm64/arm/rtsm_ve-aemv8a.dts b/sys/gnu/dts/arm64/arm/rtsm_ve-aemv8a.dts deleted file mode 100644 index 6e685d88330..00000000000 --- a/sys/gnu/dts/arm64/arm/rtsm_ve-aemv8a.dts +++ /dev/null @@ -1,193 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * ARM Ltd. Fast Models - * - * Architecture Envelope Model (AEM) ARMv8-A - * ARMAEMv8AMPCT - * - * RTSM_VE_AEMv8A.lisa - */ - -/dts-v1/; - -#include - -/memreserve/ 0x80000000 0x00010000; - -#include "rtsm_ve-motherboard.dtsi" - -/ { - model = "RTSM_VE_AEMv8A"; - compatible = "arm,rtsm_ve,aemv8a", "arm,vexpress"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - chosen { }; - - aliases { - serial0 = &v2m_serial0; - serial1 = &v2m_serial1; - serial2 = &v2m_serial2; - serial3 = &v2m_serial3; - }; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x0>; - enable-method = "spin-table"; - cpu-release-addr = <0x0 0x8000fff8>; - next-level-cache = <&L2_0>; - }; - cpu@1 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x1>; - enable-method = "spin-table"; - cpu-release-addr = <0x0 0x8000fff8>; - next-level-cache = <&L2_0>; - }; - cpu@2 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x2>; - enable-method = "spin-table"; - cpu-release-addr = <0x0 0x8000fff8>; - next-level-cache = <&L2_0>; - }; - cpu@3 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x3>; - enable-method = "spin-table"; - cpu-release-addr = <0x0 0x8000fff8>; - next-level-cache = <&L2_0>; - }; - - L2_0: l2-cache0 { - compatible = "cache"; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x00000000 0x80000000 0 0x80000000>, - <0x00000008 0x80000000 0 0x80000000>; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - /* Chipselect 2,00000000 is physically at 0x18000000 */ - vram: vram@18000000 { - /* 8 MB of designated video RAM */ - compatible = "shared-dma-pool"; - reg = <0x00000000 0x18000000 0 0x00800000>; - no-map; - }; - }; - - gic: interrupt-controller@2c001000 { - compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x0 0x2c001000 0 0x1000>, - <0x0 0x2c002000 0 0x2000>, - <0x0 0x2c004000 0 0x2000>, - <0x0 0x2c006000 0 0x2000>; - interrupts = ; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - clock-frequency = <100000000>; - }; - - pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = , - , - , - ; - }; - - panel { - compatible = "arm,rtsm-display"; - port { - panel_in: endpoint { - remote-endpoint = <&clcd_pads>; - }; - }; - }; - - smb@8000000 { - compatible = "simple-bus"; - - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0 0x08000000 0x04000000>, - <1 0 0 0x14000000 0x04000000>, - <2 0 0 0x18000000 0x04000000>, - <3 0 0 0x1c000000 0x04000000>, - <4 0 0 0x0c000000 0x04000000>, - <5 0 0 0x10000000 0x04000000>; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 63>; - interrupt-map = <0 0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, - <0 0 1 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, - <0 0 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, - <0 0 3 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, - <0 0 4 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, - <0 0 5 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, - <0 0 6 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, - <0 0 7 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, - <0 0 8 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, - <0 0 9 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, - <0 0 10 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, - <0 0 11 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, - <0 0 12 &gic GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, - <0 0 13 &gic GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, - <0 0 14 &gic GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, - <0 0 15 &gic GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, - <0 0 16 &gic GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, - <0 0 17 &gic GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, - <0 0 18 &gic GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, - <0 0 19 &gic GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, - <0 0 20 &gic GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, - <0 0 21 &gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, - <0 0 22 &gic GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, - <0 0 23 &gic GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, - <0 0 24 &gic GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, - <0 0 25 &gic GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, - <0 0 26 &gic GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, - <0 0 27 &gic GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, - <0 0 28 &gic GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, - <0 0 29 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, - <0 0 30 &gic GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, - <0 0 31 &gic GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, - <0 0 32 &gic GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, - <0 0 33 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, - <0 0 34 &gic GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, - <0 0 35 &gic GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, - <0 0 36 &gic GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, - <0 0 37 &gic GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, - <0 0 38 &gic GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, - <0 0 39 &gic GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, - <0 0 40 &gic GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, - <0 0 41 &gic GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, - <0 0 42 &gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; - }; -}; diff --git a/sys/gnu/dts/arm64/arm/rtsm_ve-motherboard-rs2.dtsi b/sys/gnu/dts/arm64/arm/rtsm_ve-motherboard-rs2.dtsi deleted file mode 100644 index 57b0b9d7f3f..00000000000 --- a/sys/gnu/dts/arm64/arm/rtsm_ve-motherboard-rs2.dtsi +++ /dev/null @@ -1,27 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * ARM Ltd. Fast Models - * - * "rs2" extension for the v2m motherboard - */ -/ { - smb@8000000 { - motherboard { - arm,v2m-memory-map = "rs2"; - - iofpga@3,00000000 { - virtio-p9@140000 { - compatible = "virtio,mmio"; - reg = <0x140000 0x200>; - interrupts = <43>; - }; - - virtio-net@150000 { - compatible = "virtio,mmio"; - reg = <0x150000 0x200>; - interrupts = <44>; - }; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/arm/rtsm_ve-motherboard.dtsi b/sys/gnu/dts/arm64/arm/rtsm_ve-motherboard.dtsi deleted file mode 100644 index 03a7bf079c8..00000000000 --- a/sys/gnu/dts/arm64/arm/rtsm_ve-motherboard.dtsi +++ /dev/null @@ -1,250 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * ARM Ltd. Fast Models - * - * Versatile Express (VE) system model - * Motherboard component - * - * VEMotherBoard.lisa - */ -/ { - smb@8000000 { - motherboard { - arm,v2m-memory-map = "rs1"; - compatible = "arm,vexpress,v2m-p1", "simple-bus"; - #address-cells = <2>; /* SMB chipselect number and offset */ - #size-cells = <1>; - #interrupt-cells = <1>; - ranges; - - flash@0,00000000 { - compatible = "arm,vexpress-flash", "cfi-flash"; - reg = <0 0x00000000 0x04000000>, - <4 0x00000000 0x04000000>; - bank-width = <4>; - }; - - ethernet@2,02000000 { - compatible = "smsc,lan91c111"; - reg = <2 0x02000000 0x10000>; - interrupts = <15>; - }; - - v2m_clk24mhz: clk24mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "v2m:clk24mhz"; - }; - - v2m_refclk1mhz: refclk1mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <1000000>; - clock-output-names = "v2m:refclk1mhz"; - }; - - v2m_refclk32khz: refclk32khz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "v2m:refclk32khz"; - }; - - iofpga@3,00000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 3 0 0x200000>; - - v2m_sysreg: sysreg@10000 { - compatible = "arm,vexpress-sysreg"; - reg = <0x010000 0x1000>; - gpio-controller; - #gpio-cells = <2>; - }; - - v2m_sysctl: sysctl@20000 { - compatible = "arm,sp810", "arm,primecell"; - reg = <0x020000 0x1000>; - clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&v2m_clk24mhz>; - clock-names = "refclk", "timclk", "apb_pclk"; - #clock-cells = <1>; - clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3"; - assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>; - assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>; - }; - - aaci@40000 { - compatible = "arm,pl041", "arm,primecell"; - reg = <0x040000 0x1000>; - interrupts = <11>; - clocks = <&v2m_clk24mhz>; - clock-names = "apb_pclk"; - }; - - mmci@50000 { - compatible = "arm,pl180", "arm,primecell"; - reg = <0x050000 0x1000>; - interrupts = <9>, <10>; - cd-gpios = <&v2m_sysreg 0 0>; - wp-gpios = <&v2m_sysreg 1 0>; - max-frequency = <12000000>; - vmmc-supply = <&v2m_fixed_3v3>; - clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; - clock-names = "mclk", "apb_pclk"; - }; - - kmi@60000 { - compatible = "arm,pl050", "arm,primecell"; - reg = <0x060000 0x1000>; - interrupts = <12>; - clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; - clock-names = "KMIREFCLK", "apb_pclk"; - }; - - kmi@70000 { - compatible = "arm,pl050", "arm,primecell"; - reg = <0x070000 0x1000>; - interrupts = <13>; - clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; - clock-names = "KMIREFCLK", "apb_pclk"; - }; - - v2m_serial0: uart@90000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x090000 0x1000>; - interrupts = <5>; - clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; - clock-names = "uartclk", "apb_pclk"; - }; - - v2m_serial1: uart@a0000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0a0000 0x1000>; - interrupts = <6>; - clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; - clock-names = "uartclk", "apb_pclk"; - }; - - v2m_serial2: uart@b0000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0b0000 0x1000>; - interrupts = <7>; - clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; - clock-names = "uartclk", "apb_pclk"; - }; - - v2m_serial3: uart@c0000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0c0000 0x1000>; - interrupts = <8>; - clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; - clock-names = "uartclk", "apb_pclk"; - }; - - wdt@f0000 { - compatible = "arm,sp805", "arm,primecell"; - reg = <0x0f0000 0x1000>; - interrupts = <0>; - clocks = <&v2m_refclk32khz>, <&v2m_clk24mhz>; - clock-names = "wdogclk", "apb_pclk"; - }; - - v2m_timer01: timer@110000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x110000 0x1000>; - interrupts = <2>; - clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_clk24mhz>; - clock-names = "timclken1", "timclken2", "apb_pclk"; - }; - - v2m_timer23: timer@120000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x120000 0x1000>; - interrupts = <3>; - clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&v2m_clk24mhz>; - clock-names = "timclken1", "timclken2", "apb_pclk"; - }; - - virtio-block@130000 { - compatible = "virtio,mmio"; - reg = <0x130000 0x200>; - interrupts = <42>; - }; - - rtc@170000 { - compatible = "arm,pl031", "arm,primecell"; - reg = <0x170000 0x1000>; - interrupts = <4>; - clocks = <&v2m_clk24mhz>; - clock-names = "apb_pclk"; - }; - - clcd@1f0000 { - compatible = "arm,pl111", "arm,primecell"; - reg = <0x1f0000 0x1000>; - interrupt-names = "combined"; - interrupts = <14>; - clocks = <&v2m_oscclk1>, <&v2m_clk24mhz>; - clock-names = "clcdclk", "apb_pclk"; - memory-region = <&vram>; - - port { - clcd_pads: endpoint { - remote-endpoint = <&panel_in>; - arm,pl11x,tft-r0g0b0-pads = <0 8 16>; - }; - }; - }; - }; - - v2m_fixed_3v3: v2m-3v3 { - compatible = "regulator-fixed"; - regulator-name = "3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - mcc { - compatible = "arm,vexpress,config-bus"; - arm,vexpress,config-bridge = <&v2m_sysreg>; - - v2m_oscclk1: oscclk1 { - /* CLCD clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 1>; - freq-range = <23750000 63500000>; - #clock-cells = <0>; - clock-output-names = "v2m:oscclk1"; - }; - - reset { - compatible = "arm,vexpress-reset"; - arm,vexpress-sysreg,func = <5 0>; - }; - - muxfpga { - compatible = "arm,vexpress-muxfpga"; - arm,vexpress-sysreg,func = <7 0>; - }; - - shutdown { - compatible = "arm,vexpress-shutdown"; - arm,vexpress-sysreg,func = <8 0>; - }; - - reboot { - compatible = "arm,vexpress-reboot"; - arm,vexpress-sysreg,func = <9 0>; - }; - - dvimode { - compatible = "arm,vexpress-dvimode"; - arm,vexpress-sysreg,func = <11 0>; - }; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/arm/vexpress-v2f-1xv7-ca53x2.dts b/sys/gnu/dts/arm64/arm/vexpress-v2f-1xv7-ca53x2.dts deleted file mode 100644 index 22383c26bb0..00000000000 --- a/sys/gnu/dts/arm64/arm/vexpress-v2f-1xv7-ca53x2.dts +++ /dev/null @@ -1,205 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * ARM Ltd. Versatile Express - * - * LogicTile Express 20MG - * V2F-1XV7 - * - * Cortex-A53 (2 cores) Soft Macrocell Model - * - * HBI-0247C - */ - -/dts-v1/; - -#include -#include "vexpress-v2m-rs1.dtsi" - -/ { - model = "V2F-1XV7 Cortex-A53x2 SMM"; - arm,hbi = <0x247>; - arm,vexpress,site = <0xf>; - compatible = "arm,vexpress,v2f-1xv7,ca53x2", "arm,vexpress,v2f-1xv7", "arm,vexpress"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - chosen { - stdout-path = "serial0:38400n8"; - }; - - aliases { - serial0 = &v2m_serial0; - serial1 = &v2m_serial1; - serial2 = &v2m_serial2; - serial3 = &v2m_serial3; - i2c0 = &v2m_i2c_dvi; - i2c1 = &v2m_i2c_pcie; - }; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0 0>; - next-level-cache = <&L2_0>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0 1>; - next-level-cache = <&L2_0>; - }; - - L2_0: l2-cache0 { - compatible = "cache"; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0 0x80000000 0 0x80000000>; /* 2GB @ 2GB */ - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - /* Chipselect 2 is physically at 0x18000000 */ - vram: vram@18000000 { - /* 8 MB of designated video RAM */ - compatible = "shared-dma-pool"; - reg = <0 0x18000000 0 0x00800000>; - no-map; - }; - }; - - gic: interrupt-controller@2c001000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0 0x2c001000 0 0x1000>, - <0 0x2c002000 0 0x2000>, - <0 0x2c004000 0 0x2000>, - <0 0x2c006000 0 0x2000>; - interrupts = ; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = , - ; - }; - - dcc { - compatible = "arm,vexpress,config-bus"; - arm,vexpress,config-bridge = <&v2m_sysreg>; - - smbclk: smclk { - /* SMC clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 4>; - freq-range = <40000000 40000000>; - #clock-cells = <0>; - clock-output-names = "smclk"; - }; - - volt-vio { - /* VIO to expansion board above */ - compatible = "arm,vexpress-volt"; - arm,vexpress-sysreg,func = <2 0>; - regulator-name = "VIO_UP"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - volt-12v { - /* 12V from power connector J6 */ - compatible = "arm,vexpress-volt"; - arm,vexpress-sysreg,func = <2 1>; - regulator-name = "12"; - regulator-always-on; - }; - - temp-fpga { - /* FPGA temperature */ - compatible = "arm,vexpress-temp"; - arm,vexpress-sysreg,func = <4 0>; - label = "FPGA"; - }; - }; - - smb: smb@8000000 { - compatible = "simple-bus"; - - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0 0x08000000 0x04000000>, - <1 0 0 0x14000000 0x04000000>, - <2 0 0 0x18000000 0x04000000>, - <3 0 0 0x1c000000 0x04000000>, - <4 0 0 0x0c000000 0x04000000>, - <5 0 0 0x10000000 0x04000000>; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 63>; - interrupt-map = <0 0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, - <0 0 1 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, - <0 0 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, - <0 0 3 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, - <0 0 4 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, - <0 0 5 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, - <0 0 6 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, - <0 0 7 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, - <0 0 8 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, - <0 0 9 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, - <0 0 10 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, - <0 0 11 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, - <0 0 12 &gic GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, - <0 0 13 &gic GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, - <0 0 14 &gic GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, - <0 0 15 &gic GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, - <0 0 16 &gic GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, - <0 0 17 &gic GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, - <0 0 18 &gic GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, - <0 0 19 &gic GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, - <0 0 20 &gic GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, - <0 0 21 &gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, - <0 0 22 &gic GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, - <0 0 23 &gic GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, - <0 0 24 &gic GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, - <0 0 25 &gic GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, - <0 0 26 &gic GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, - <0 0 27 &gic GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, - <0 0 28 &gic GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, - <0 0 29 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, - <0 0 30 &gic GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, - <0 0 31 &gic GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, - <0 0 32 &gic GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, - <0 0 33 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, - <0 0 34 &gic GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, - <0 0 35 &gic GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, - <0 0 36 &gic GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, - <0 0 37 &gic GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, - <0 0 38 &gic GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, - <0 0 39 &gic GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, - <0 0 40 &gic GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, - <0 0 41 &gic GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, - <0 0 42 &gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; - }; -}; diff --git a/sys/gnu/dts/arm64/arm/vexpress-v2m-rs1.dtsi b/sys/gnu/dts/arm64/arm/vexpress-v2m-rs1.dtsi deleted file mode 100644 index dfae90adbb7..00000000000 --- a/sys/gnu/dts/arm64/arm/vexpress-v2m-rs1.dtsi +++ /dev/null @@ -1,441 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * ARM Ltd. Versatile Express - * - * Motherboard Express uATX - * V2M-P1 - * - * HBI-0190D - * - * RS1 memory map ("ARM Cortex-A Series memory map" in the board's - * Technical Reference Manual) - * - * WARNING! The hardware described in this file is independent from the - * original variant (vexpress-v2m.dtsi), but there is a strong - * correspondence between the two configurations. - * - * TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT - * CHANGES TO vexpress-v2m.dtsi! - */ - -/ { - smb@8000000 { - motherboard { - model = "V2M-P1"; - arm,hbi = <0x190>; - arm,vexpress,site = <0>; - arm,v2m-memory-map = "rs1"; - compatible = "arm,vexpress,v2m-p1", "simple-bus"; - #address-cells = <2>; /* SMB chipselect number and offset */ - #size-cells = <1>; - #interrupt-cells = <1>; - ranges; - - nor_flash: flash@0,00000000 { - compatible = "arm,vexpress-flash", "cfi-flash"; - reg = <0 0x00000000 0x04000000>, - <4 0x00000000 0x04000000>; - bank-width = <4>; - partitions { - compatible = "arm,arm-firmware-suite"; - }; - }; - - psram@1,00000000 { - compatible = "arm,vexpress-psram", "mtd-ram"; - reg = <1 0x00000000 0x02000000>; - bank-width = <4>; - }; - - ethernet@2,02000000 { - compatible = "smsc,lan9118", "smsc,lan9115"; - reg = <2 0x02000000 0x10000>; - interrupts = <15>; - phy-mode = "mii"; - reg-io-width = <4>; - smsc,irq-active-high; - smsc,irq-push-pull; - vdd33a-supply = <&v2m_fixed_3v3>; - vddvario-supply = <&v2m_fixed_3v3>; - }; - - usb@2,03000000 { - compatible = "nxp,usb-isp1761"; - reg = <2 0x03000000 0x20000>; - interrupts = <16>; - port1-otg; - }; - - iofpga@3,00000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 3 0 0x200000>; - - v2m_sysreg: sysreg@10000 { - compatible = "arm,vexpress-sysreg"; - reg = <0x010000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x10000 0x1000>; - - v2m_led_gpios: gpio@8 { - compatible = "arm,vexpress-sysreg,sys_led"; - reg = <0x008 4>; - gpio-controller; - #gpio-cells = <2>; - }; - - v2m_mmc_gpios: gpio@48 { - compatible = "arm,vexpress-sysreg,sys_mci"; - reg = <0x048 4>; - gpio-controller; - #gpio-cells = <2>; - }; - - v2m_flash_gpios: gpio@4c { - compatible = "arm,vexpress-sysreg,sys_flash"; - reg = <0x04c 4>; - gpio-controller; - #gpio-cells = <2>; - }; - }; - - v2m_sysctl: sysctl@20000 { - compatible = "arm,sp810", "arm,primecell"; - reg = <0x020000 0x1000>; - clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>; - clock-names = "refclk", "timclk", "apb_pclk"; - #clock-cells = <1>; - clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3"; - assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>; - assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>; - }; - - /* PCI-E I2C bus */ - v2m_i2c_pcie: i2c@30000 { - compatible = "arm,versatile-i2c"; - reg = <0x030000 0x1000>; - - #address-cells = <1>; - #size-cells = <0>; - - pcie-switch@60 { - compatible = "idt,89hpes32h8"; - reg = <0x60>; - }; - }; - - aaci@40000 { - compatible = "arm,pl041", "arm,primecell"; - reg = <0x040000 0x1000>; - interrupts = <11>; - clocks = <&smbclk>; - clock-names = "apb_pclk"; - }; - - mmci@50000 { - compatible = "arm,pl180", "arm,primecell"; - reg = <0x050000 0x1000>; - interrupts = <9>, <10>; - cd-gpios = <&v2m_mmc_gpios 0 0>; - wp-gpios = <&v2m_mmc_gpios 1 0>; - max-frequency = <12000000>; - vmmc-supply = <&v2m_fixed_3v3>; - clocks = <&v2m_clk24mhz>, <&smbclk>; - clock-names = "mclk", "apb_pclk"; - }; - - kmi@60000 { - compatible = "arm,pl050", "arm,primecell"; - reg = <0x060000 0x1000>; - interrupts = <12>; - clocks = <&v2m_clk24mhz>, <&smbclk>; - clock-names = "KMIREFCLK", "apb_pclk"; - }; - - kmi@70000 { - compatible = "arm,pl050", "arm,primecell"; - reg = <0x070000 0x1000>; - interrupts = <13>; - clocks = <&v2m_clk24mhz>, <&smbclk>; - clock-names = "KMIREFCLK", "apb_pclk"; - }; - - v2m_serial0: uart@90000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x090000 0x1000>; - interrupts = <5>; - clocks = <&v2m_oscclk2>, <&smbclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - v2m_serial1: uart@a0000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0a0000 0x1000>; - interrupts = <6>; - clocks = <&v2m_oscclk2>, <&smbclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - v2m_serial2: uart@b0000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0b0000 0x1000>; - interrupts = <7>; - clocks = <&v2m_oscclk2>, <&smbclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - v2m_serial3: uart@c0000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0c0000 0x1000>; - interrupts = <8>; - clocks = <&v2m_oscclk2>, <&smbclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - wdt@f0000 { - compatible = "arm,sp805", "arm,primecell"; - reg = <0x0f0000 0x1000>; - interrupts = <0>; - clocks = <&v2m_refclk32khz>, <&smbclk>; - clock-names = "wdogclk", "apb_pclk"; - }; - - v2m_timer01: timer@110000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x110000 0x1000>; - interrupts = <2>; - clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&smbclk>; - clock-names = "timclken1", "timclken2", "apb_pclk"; - }; - - v2m_timer23: timer@120000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x120000 0x1000>; - interrupts = <3>; - clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&smbclk>; - clock-names = "timclken1", "timclken2", "apb_pclk"; - }; - - /* DVI I2C bus */ - v2m_i2c_dvi: i2c@160000 { - compatible = "arm,versatile-i2c"; - reg = <0x160000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - - dvi-transmitter@39 { - compatible = "sil,sii9022-tpi", "sil,sii9022"; - reg = <0x39>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dvi_bridge_in: endpoint { - remote-endpoint = <&clcd_pads>; - }; - }; - }; - }; - - dvi-transmitter@60 { - compatible = "sil,sii9022-cpi", "sil,sii9022"; - reg = <0x60>; - }; - }; - - rtc@170000 { - compatible = "arm,pl031", "arm,primecell"; - reg = <0x170000 0x1000>; - interrupts = <4>; - clocks = <&smbclk>; - clock-names = "apb_pclk"; - }; - - compact-flash@1a0000 { - compatible = "arm,vexpress-cf", "ata-generic"; - reg = <0x1a0000 0x100 - 0x1a0100 0xf00>; - reg-shift = <2>; - }; - - clcd@1f0000 { - compatible = "arm,pl111", "arm,primecell"; - reg = <0x1f0000 0x1000>; - interrupt-names = "combined"; - interrupts = <14>; - clocks = <&v2m_oscclk1>, <&smbclk>; - clock-names = "clcdclk", "apb_pclk"; - /* 800x600 16bpp @36MHz works fine */ - max-memory-bandwidth = <54000000>; - memory-region = <&vram>; - - port { - clcd_pads: endpoint { - remote-endpoint = <&dvi_bridge_in>; - arm,pl11x,tft-r0g0b0-pads = <0 8 16>; - }; - }; - }; - }; - - v2m_fixed_3v3: fixed-regulator-0 { - compatible = "regulator-fixed"; - regulator-name = "3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - v2m_clk24mhz: clk24mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "v2m:clk24mhz"; - }; - - v2m_refclk1mhz: refclk1mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <1000000>; - clock-output-names = "v2m:refclk1mhz"; - }; - - v2m_refclk32khz: refclk32khz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "v2m:refclk32khz"; - }; - - leds { - compatible = "gpio-leds"; - - user1 { - label = "v2m:green:user1"; - gpios = <&v2m_led_gpios 0 0>; - linux,default-trigger = "heartbeat"; - }; - - user2 { - label = "v2m:green:user2"; - gpios = <&v2m_led_gpios 1 0>; - linux,default-trigger = "mmc0"; - }; - - user3 { - label = "v2m:green:user3"; - gpios = <&v2m_led_gpios 2 0>; - linux,default-trigger = "cpu0"; - }; - - user4 { - label = "v2m:green:user4"; - gpios = <&v2m_led_gpios 3 0>; - linux,default-trigger = "cpu1"; - }; - - user5 { - label = "v2m:green:user5"; - gpios = <&v2m_led_gpios 4 0>; - linux,default-trigger = "cpu2"; - }; - - user6 { - label = "v2m:green:user6"; - gpios = <&v2m_led_gpios 5 0>; - linux,default-trigger = "cpu3"; - }; - - user7 { - label = "v2m:green:user7"; - gpios = <&v2m_led_gpios 6 0>; - linux,default-trigger = "cpu4"; - }; - - user8 { - label = "v2m:green:user8"; - gpios = <&v2m_led_gpios 7 0>; - linux,default-trigger = "cpu5"; - }; - }; - - mcc { - compatible = "arm,vexpress,config-bus"; - arm,vexpress,config-bridge = <&v2m_sysreg>; - - oscclk0 { - /* MCC static memory clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 0>; - freq-range = <25000000 60000000>; - #clock-cells = <0>; - clock-output-names = "v2m:oscclk0"; - }; - - v2m_oscclk1: oscclk1 { - /* CLCD clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 1>; - freq-range = <23750000 65000000>; - #clock-cells = <0>; - clock-output-names = "v2m:oscclk1"; - }; - - v2m_oscclk2: oscclk2 { - /* IO FPGA peripheral clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 2>; - freq-range = <24000000 24000000>; - #clock-cells = <0>; - clock-output-names = "v2m:oscclk2"; - }; - - volt-vio { - /* Logic level voltage */ - compatible = "arm,vexpress-volt"; - arm,vexpress-sysreg,func = <2 0>; - regulator-name = "VIO"; - regulator-always-on; - label = "VIO"; - }; - - temp-mcc { - /* MCC internal operating temperature */ - compatible = "arm,vexpress-temp"; - arm,vexpress-sysreg,func = <4 0>; - label = "MCC"; - }; - - reset { - compatible = "arm,vexpress-reset"; - arm,vexpress-sysreg,func = <5 0>; - }; - - muxfpga { - compatible = "arm,vexpress-muxfpga"; - arm,vexpress-sysreg,func = <7 0>; - }; - - shutdown { - compatible = "arm,vexpress-shutdown"; - arm,vexpress-sysreg,func = <8 0>; - }; - - reboot { - compatible = "arm,vexpress-reboot"; - arm,vexpress-sysreg,func = <9 0>; - }; - - dvimode { - compatible = "arm,vexpress-dvimode"; - arm,vexpress-sysreg,func = <11 0>; - }; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/bitmain/bm1880-sophon-edge.dts b/sys/gnu/dts/arm64/bitmain/bm1880-sophon-edge.dts deleted file mode 100644 index 7a2c7f9c266..00000000000 --- a/sys/gnu/dts/arm64/bitmain/bm1880-sophon-edge.dts +++ /dev/null @@ -1,184 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 Linaro Ltd. - * Author: Manivannan Sadhasivam - */ - -/dts-v1/; - -#include "bm1880.dtsi" - -/* - * GPIO name legend: proper name = the GPIO line is used as GPIO - * NC = not connected (pin out but not routed from the chip to - * anything the board) - * "[PER]" = pin is muxed for [peripheral] (not GPIO) - * LSEC = Low Speed External Connector - * HSEC = High Speed External Connector - * - * Line names are taken from the schematic "sophon-edge-schematics" - * version, 1.0210. - * - * For the lines routed to the external connectors the - * lines are named after the 96Boards CE Specification 1.0, - * Appendix "Expansion Connector Signal Description". - * - * When the 96Board naming of a line and the schematic name of - * the same line are in conflict, the 96Board specification - * takes precedence. This is only for the informational - * lines i.e. "[FOO]", the GPIO named lines "GPIO-A" thru "GPIO-L" - * are the only ones actually used for GPIO. - */ - -/ { - compatible = "bitmain,sophon-edge", "bitmain,bm1880"; - model = "Sophon Edge"; - - aliases { - serial0 = &uart0; - serial1 = &uart2; - serial2 = &uart1; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x1 0x00000000 0x0 0x40000000>; // 1GB - }; - - soc { - gpio0: gpio@50027000 { - porta: gpio-controller@0 { - gpio-line-names = - "GPIO-A", /* GPIO0, LSEC pin 23 */ - "GPIO-C", /* GPIO1, LSEC pin 25 */ - "[GPIO2_PHY0_RST]", /* GPIO2 */ - "GPIO-E", /* GPIO3, LSEC pin 27 */ - "[USB_DET]", /* GPIO4 */ - "[EN_P5V]", /* GPIO5 */ - "[VDDIO_MS1_SEL]", /* GPIO6 */ - "GPIO-G", /* GPIO7, LSEC pin 29 */ - "[BM_TUSB_RST_L]", /* GPIO8 */ - "[EN_P5V_USBHUB]", /* GPIO9 */ - "NC", - "LED_WIFI", /* GPIO11 */ - "LED_BT", /* GPIO12 */ - "[BM_BLM8221_EN_L]", /* GPIO13 */ - "NC", /* GPIO14 */ - "NC", /* GPIO15 */ - "NC", /* GPIO16 */ - "NC", /* GPIO17 */ - "NC", /* GPIO18 */ - "NC", /* GPIO19 */ - "NC", /* GPIO20 */ - "NC", /* GPIO21 */ - "NC", /* GPIO22 */ - "NC", /* GPIO23 */ - "NC", /* GPIO24 */ - "NC", /* GPIO25 */ - "NC", /* GPIO26 */ - "NC", /* GPIO27 */ - "NC", /* GPIO28 */ - "NC", /* GPIO29 */ - "NC", /* GPIO30 */ - "NC"; /* GPIO31 */ - }; - }; - - gpio1: gpio@50027400 { - portb: gpio-controller@0 { - gpio-line-names = - "NC", /* GPIO32 */ - "NC", /* GPIO33 */ - "[I2C0_SDA]", /* GPIO34, LSEC pin 17 */ - "[I2C0_SCL]", /* GPIO35, LSEC pin 15 */ - "[JTAG0_TDO]", /* GPIO36 */ - "[JTAG0_TCK]", /* GPIO37 */ - "[JTAG0_TDI]", /* GPIO38 */ - "[JTAG0_TMS]", /* GPIO39 */ - "[JTAG0_TRST_X]", /* GPIO40 */ - "[JTAG1_TDO]", /* GPIO41 */ - "[JTAG1_TCK]", /* GPIO42 */ - "[JTAG1_TDI]", /* GPIO43 */ - "[CPU_TX]", /* GPIO44 */ - "[CPU_RX]", /* GPIO45 */ - "[UART1_TXD]", /* GPIO46 */ - "[UART1_RXD]", /* GPIO47 */ - "[UART0_TXD]", /* GPIO48 */ - "[UART0_RXD]", /* GPIO49 */ - "GPIO-I", /* GPIO50, LSEC pin 31 */ - "GPIO-K", /* GPIO51, LSEC pin 33 */ - "USER_LED2", /* GPIO52 */ - "USER_LED1", /* GPIO53 */ - "[UART0_RTS]", /* GPIO54 */ - "[UART0_CTS]", /* GPIO55 */ - "USER_LED4", /* GPIO56, JTAG1_TRST_X */ - "USER_LED3", /* GPIO57, JTAG1_TMS */ - "[I2S0_SCLK]", /* GPIO58 */ - "[I2S0_FS]", /* GPIO59 */ - "[I2S0_SDI]", /* GPIO60 */ - "[I2S0_SDO]", /* GPIO61 */ - "GPIO-B", /* GPIO62, LSEC pin 24 */ - "GPIO-F"; /* GPIO63, I2S1_SCLK, LSEC pin 28 */ - }; - }; - - gpio2: gpio@50027800 { - portc: gpio-controller@0 { - gpio-line-names = - "GPIO-D", /* GPIO64, I2S1_FS, LSEC pin 26 */ - "GPIO-J", /* GPIO65, I2S1_SDI, LSEC pin 32 */ - "GPIO-H", /* GPIO66, I2S1_SDO, LSEC pin 30 */ - "GPIO-L", /* GPIO67, LSEC pin 34 */ - "[SPI0_CS]", /* GPIO68, SPI1_CS, LSEC pin 12 */ - "[SPI0_DIN]", /* GPIO69, SPI1_SDI, LSEC pin 10 */ - "[SPI0_DOUT]", /* GPIO70, SPI1_SDO, LSEC pin 14 */ - "[SPI0_SCLK]"; /* GPIO71, SPI1_SCK, LSEC pin 8 */ - }; - }; - }; -}; - -&pinctrl { - pinctrl_uart0_default: pinctrl-uart0-default { - pinmux { - groups = "uart0_grp"; - function = "uart0"; - }; - }; - - pinctrl_uart1_default: pinctrl-uart1-default { - pinmux { - groups = "uart1_grp"; - function = "uart1"; - }; - }; - - pinctrl_uart2_default: pinctrl-uart2-default { - pinmux { - groups = "uart2_grp"; - function = "uart2"; - }; - }; -}; - -&uart0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0_default>; -}; - -&uart1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1_default>; -}; - -&uart2 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2_default>; -}; diff --git a/sys/gnu/dts/arm64/bitmain/bm1880.dtsi b/sys/gnu/dts/arm64/bitmain/bm1880.dtsi deleted file mode 100644 index fa6e6905f58..00000000000 --- a/sys/gnu/dts/arm64/bitmain/bm1880.dtsi +++ /dev/null @@ -1,226 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 Linaro Ltd. - * Author: Manivannan Sadhasivam - */ - -#include -#include -#include - -/ { - compatible = "bitmain,bm1880"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0>; - enable-method = "psci"; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x1>; - enable-method = "psci"; - }; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - secmon@100000000 { - reg = <0x1 0x00000000 0x0 0x20000>; - no-map; - }; - - jpu@130000000 { - reg = <0x1 0x30000000 0x0 0x08000000>; // 128M - no-map; - }; - - vpu@138000000 { - reg = <0x1 0x38000000 0x0 0x08000000>; // 128M - no-map; - }; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - osc: osc { - compatible = "fixed-clock"; - clock-frequency = <25000000>; - #clock-cells = <0>; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - gic: interrupt-controller@50001000 { - compatible = "arm,gic-400"; - reg = <0x0 0x50001000 0x0 0x1000>, - <0x0 0x50002000 0x0 0x2000>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <3>; - }; - - sctrl: system-controller@50010000 { - compatible = "bitmain,bm1880-sctrl", "syscon", - "simple-mfd"; - reg = <0x0 0x50010000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x50010000 0x1000>; - - pinctrl: pinctrl@400 { - compatible = "bitmain,bm1880-pinctrl"; - reg = <0x400 0x120>; - }; - - clk: clock-controller@e8 { - compatible = "bitmain,bm1880-clk"; - reg = <0xe8 0x0c>, <0x800 0xb0>; - reg-names = "pll", "sys"; - clocks = <&osc>; - clock-names = "osc"; - #clock-cells = <1>; - }; - - rst: reset-controller@c00 { - compatible = "bitmain,bm1880-reset"; - reg = <0xc00 0x8>; - #reset-cells = <1>; - }; - }; - - gpio0: gpio@50027000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dw-apb-gpio"; - reg = <0x0 0x50027000 0x0 0x400>; - - porta: gpio-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <32>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = ; - }; - }; - - gpio1: gpio@50027400 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dw-apb-gpio"; - reg = <0x0 0x50027400 0x0 0x400>; - - portb: gpio-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <32>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = ; - }; - }; - - gpio2: gpio@50027800 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dw-apb-gpio"; - reg = <0x0 0x50027800 0x0 0x400>; - - portc: gpio-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <8>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = ; - }; - }; - - uart0: serial@58018000 { - compatible = "snps,dw-apb-uart"; - reg = <0x0 0x58018000 0x0 0x2000>; - clocks = <&clk BM1880_CLK_UART_500M>, - <&clk BM1880_CLK_APB_UART>; - clock-names = "baudclk", "apb_pclk"; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - resets = <&rst BM1880_RST_UART0_1_CLK>; - status = "disabled"; - }; - - uart1: serial@5801A000 { - compatible = "snps,dw-apb-uart"; - reg = <0x0 0x5801a000 0x0 0x2000>; - clocks = <&clk BM1880_CLK_UART_500M>, - <&clk BM1880_CLK_APB_UART>; - clock-names = "baudclk", "apb_pclk"; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - resets = <&rst BM1880_RST_UART0_1_ACLK>; - status = "disabled"; - }; - - uart2: serial@5801C000 { - compatible = "snps,dw-apb-uart"; - reg = <0x0 0x5801c000 0x0 0x2000>; - clocks = <&clk BM1880_CLK_UART_500M>, - <&clk BM1880_CLK_APB_UART>; - clock-names = "baudclk", "apb_pclk"; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - resets = <&rst BM1880_RST_UART2_3_CLK>; - status = "disabled"; - }; - - uart3: serial@5801E000 { - compatible = "snps,dw-apb-uart"; - reg = <0x0 0x5801e000 0x0 0x2000>; - clocks = <&clk BM1880_CLK_UART_500M>, - <&clk BM1880_CLK_APB_UART>; - clock-names = "baudclk", "apb_pclk"; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - resets = <&rst BM1880_RST_UART2_3_ACLK>; - status = "disabled"; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/broadcom/bcm2711-rpi-4-b.dts b/sys/gnu/dts/arm64/broadcom/bcm2711-rpi-4-b.dts deleted file mode 100644 index d24c53682e4..00000000000 --- a/sys/gnu/dts/arm64/broadcom/bcm2711-rpi-4-b.dts +++ /dev/null @@ -1,2 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "arm/bcm2711-rpi-4-b.dts" diff --git a/sys/gnu/dts/arm64/broadcom/bcm2837-rpi-3-a-plus.dts b/sys/gnu/dts/arm64/broadcom/bcm2837-rpi-3-a-plus.dts deleted file mode 100644 index f0ec56a1c4d..00000000000 --- a/sys/gnu/dts/arm64/broadcom/bcm2837-rpi-3-a-plus.dts +++ /dev/null @@ -1,2 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "arm/bcm2837-rpi-3-a-plus.dts" diff --git a/sys/gnu/dts/arm64/broadcom/bcm2837-rpi-3-b-plus.dts b/sys/gnu/dts/arm64/broadcom/bcm2837-rpi-3-b-plus.dts deleted file mode 100644 index 46ad2023ccc..00000000000 --- a/sys/gnu/dts/arm64/broadcom/bcm2837-rpi-3-b-plus.dts +++ /dev/null @@ -1,2 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "arm/bcm2837-rpi-3-b-plus.dts" diff --git a/sys/gnu/dts/arm64/broadcom/bcm2837-rpi-3-b.dts b/sys/gnu/dts/arm64/broadcom/bcm2837-rpi-3-b.dts deleted file mode 100644 index 89b78d6c19b..00000000000 --- a/sys/gnu/dts/arm64/broadcom/bcm2837-rpi-3-b.dts +++ /dev/null @@ -1,2 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "arm/bcm2837-rpi-3-b.dts" diff --git a/sys/gnu/dts/arm64/broadcom/bcm2837-rpi-cm3-io3.dts b/sys/gnu/dts/arm64/broadcom/bcm2837-rpi-cm3-io3.dts deleted file mode 100644 index b1c4ab212c6..00000000000 --- a/sys/gnu/dts/arm64/broadcom/bcm2837-rpi-cm3-io3.dts +++ /dev/null @@ -1,2 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "arm/bcm2837-rpi-cm3-io3.dts" diff --git a/sys/gnu/dts/arm64/broadcom/northstar2/ns2-clock.dtsi b/sys/gnu/dts/arm64/broadcom/northstar2/ns2-clock.dtsi deleted file mode 100644 index 99009fdf10a..00000000000 --- a/sys/gnu/dts/arm64/broadcom/northstar2/ns2-clock.dtsi +++ /dev/null @@ -1,105 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright (c) 2016 Broadcom. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include - - osc: oscillator { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <25000000>; - }; - - lcpll_ddr: lcpll_ddr@6501d058 { - #clock-cells = <1>; - compatible = "brcm,ns2-lcpll-ddr"; - reg = <0x6501d058 0x20>, - <0x6501c020 0x4>, - <0x6501d04c 0x4>; - clocks = <&osc>; - clock-output-names = "lcpll_ddr", "pcie_sata_usb", - "ddr", "ddr_ch2_unused", - "ddr_ch3_unused", "ddr_ch4_unused", - "ddr_ch5_unused"; - }; - - lcpll_ports: lcpll_ports@6501d078 { - #clock-cells = <1>; - compatible = "brcm,ns2-lcpll-ports"; - reg = <0x6501d078 0x20>, - <0x6501c020 0x4>, - <0x6501d054 0x4>; - clocks = <&osc>; - clock-output-names = "lcpll_ports", "wan", "rgmii", - "ports_ch2_unused", - "ports_ch3_unused", - "ports_ch4_unused", - "ports_ch5_unused"; - }; - - genpll_scr: genpll_scr@6501d098 { - #clock-cells = <1>; - compatible = "brcm,ns2-genpll-scr"; - reg = <0x6501d098 0x32>, - <0x6501c020 0x4>, - <0x6501d044 0x4>; - clocks = <&osc>; - clock-output-names = "genpll_scr", "scr", "fs", - "audio_ref", "scr_ch3_unused", - "scr_ch4_unused", "scr_ch5_unused"; - }; - - iprocmed: iprocmed { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&genpll_scr BCM_NS2_GENPLL_SCR_SCR_CLK>; - clock-div = <2>; - clock-mult = <1>; - }; - - iprocslow: iprocslow { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&genpll_scr BCM_NS2_GENPLL_SCR_SCR_CLK>; - clock-div = <4>; - clock-mult = <1>; - }; - - genpll_sw: genpll_sw@6501d0c4 { - #clock-cells = <1>; - compatible = "brcm,ns2-genpll-sw"; - reg = <0x6501d0c4 0x32>, - <0x6501c020 0x4>, - <0x6501d044 0x4>; - clocks = <&osc>; - clock-output-names = "genpll_sw", "rpe", "250", "nic", - "chimp", "port", "sdio"; - }; diff --git a/sys/gnu/dts/arm64/broadcom/northstar2/ns2-svk.dts b/sys/gnu/dts/arm64/broadcom/northstar2/ns2-svk.dts deleted file mode 100644 index ec19fbf928a..00000000000 --- a/sys/gnu/dts/arm64/broadcom/northstar2/ns2-svk.dts +++ /dev/null @@ -1,236 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright(c) 2015 Broadcom Corporation. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/dts-v1/; - -#include "ns2.dtsi" - -/ { - model = "Broadcom NS2 SVK"; - compatible = "brcm,ns2-svk", "brcm,ns2"; - - aliases { - serial0 = &uart3; - serial1 = &uart0; - serial2 = &uart1; - serial3 = &uart2; - }; - - chosen { - stdout-path = "serial0:115200n8"; - bootargs = "earlycon=uart8250,mmio32,0x66130000"; - }; - - memory { - device_type = "memory"; - reg = <0x000000000 0x80000000 0x00000000 0x40000000>; - }; -}; - -&enet { - status = "okay"; -}; - -&pci_phy0 { - status = "okay"; -}; - -&pci_phy1 { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; - -&pcie4 { - status = "okay"; -}; - -&pcie8 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; -}; - -&i2c1 { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&ssp0 { - status = "okay"; - - slic@0 { - compatible = "silabs,si3226x"; - reg = <0>; - spi-max-frequency = <5000000>; - spi-cpha = <1>; - spi-cpol = <1>; - pl022,hierarchy = <0>; - pl022,interface = <0>; - pl022,slave-tx-disable = <0>; - pl022,com-mode = <0>; - pl022,rx-level-trig = <1>; - pl022,tx-level-trig = <1>; - pl022,ctrl-len = <11>; - pl022,wait-state = <0>; - pl022,duplex = <0>; - }; -}; - -&ssp1 { - status = "okay"; - - at25@0 { - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <5000000>; - at25,byte-len = <0x8000>; - at25,addr-mode = <2>; - at25,page-size = <64>; - spi-cpha = <1>; - spi-cpol = <1>; - pl022,hierarchy = <0>; - pl022,interface = <0>; - pl022,slave-tx-disable = <0>; - pl022,com-mode = <0>; - pl022,rx-level-trig = <1>; - pl022,tx-level-trig = <1>; - pl022,ctrl-len = <11>; - pl022,wait-state = <0>; - pl022,duplex = <0>; - }; -}; - -&sata_phy0 { - status = "okay"; -}; - -&sata_phy1 { - status = "okay"; -}; - -&sata { - status = "okay"; -}; - -&sdio0 { - status = "okay"; -}; - -&sdio1 { - status = "okay"; -}; - -&nand { - nandcs@0 { - compatible = "brcm,nandcs"; - reg = <0>; - nand-ecc-mode = "hw"; - nand-ecc-strength = <8>; - nand-ecc-step-size = <512>; - nand-bus-width = <16>; - brcm,nand-oob-sector-size = <16>; - #address-cells = <1>; - #size-cells = <1>; - }; -}; - -&mdio_mux_iproc { - mdio@10 { - gphy0: eth-phy@10 { - enet-phy-lane-swap; - reg = <0x10>; - }; - }; -}; - -&pinctrl { - pinctrl-names = "default"; - pinctrl-0 = <&nand_sel>; - nand_sel: nand_sel { - function = "nand"; - groups = "nand_grp"; - }; -}; - -&qspi { - bspi-sel = <0>; - flash: m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "m25p80"; - reg = <0x0>; - spi-max-frequency = <12500000>; - m25p,fast-read; - spi-cpol; - spi-cpha; - - partition@0 { - label = "boot"; - reg = <0x00000000 0x000a0000>; - }; - - partition@a0000 { - label = "env"; - reg = <0x000a0000 0x00060000>; - }; - - partition@100000 { - label = "system"; - reg = <0x00100000 0x00600000>; - }; - - partition@700000 { - label = "rootfs"; - reg = <0x00700000 0x01900000>; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/broadcom/northstar2/ns2-xmc.dts b/sys/gnu/dts/arm64/broadcom/northstar2/ns2-xmc.dts deleted file mode 100644 index f00c21e0767..00000000000 --- a/sys/gnu/dts/arm64/broadcom/northstar2/ns2-xmc.dts +++ /dev/null @@ -1,191 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright(c) 2016 Broadcom. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/dts-v1/; - -#include "ns2.dtsi" - -/ { - model = "Broadcom NS2 XMC"; - compatible = "brcm,ns2-xmc", "brcm,ns2"; - - aliases { - serial0 = &uart3; - }; - - chosen { - stdout-path = "serial0:115200n8"; - bootargs = "earlycon=uart8250,mmio32,0x66130000"; - }; - - memory { - device_type = "memory"; - reg = <0x000000000 0x80000000 0x00000001 0x00000000>; - }; -}; - -&enet { - status = "okay"; -}; - -&i2c0 { - status = "okay"; -}; - -&i2c1 { - status = "okay"; -}; - -&mdio_mux_iproc { - mdio@10 { - gphy0: eth-phy@10 { - reg = <0x10>; - }; - }; -}; - -&nand { - nandcs@0 { - compatible = "brcm,nandcs"; - reg = <0>; - nand-ecc-mode = "hw"; - nand-ecc-strength = <8>; - nand-ecc-step-size = <512>; - nand-bus-width = <16>; - brcm,nand-oob-sector-size = <16>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "nboot"; - reg = <0x00000000 0x00280000>; /* 2.5MB */ - read-only; - }; - - partition@280000 { - label = "nenv"; - reg = <0x00280000 0x00040000>; /* 0.25MB */ - read-only; - }; - - partition@2c0000 { - label = "ndtb"; - reg = <0x002c0000 0x00040000>; /* 0.25MB */ - read-only; - }; - - partition@300000 { - label = "nsystem"; - reg = <0x00300000 0x03d00000>; /* 61MB */ - read-only; - }; - - partition@4000000 { - label = "nrootfs"; - reg = <0x04000000 0x06400000>; /* 100MB */ - }; - - partition@a400000{ - label = "ncustfs"; - reg = <0x0a400000 0x35c00000>; /* 860MB */ - }; - }; -}; - -&pci_phy0 { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; - -&pcie8 { - status = "okay"; -}; - -&sata_phy0 { - status = "okay"; -}; - -&sata_phy1 { - status = "okay"; -}; - -&sata { - status = "okay"; -}; - -&qspi { - flash: m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "m25p80"; - spi-max-frequency = <62500000>; - m25p,default-addr-width = <3>; - reg = <0x0 0x0>; - - partition@0 { - label = "bl0"; - reg = <0x00000000 0x00080000>; /* 512KB */ - }; - - partition@80000 { - label = "fip"; - reg = <0x00080000 0x00150000>; /* 1344KB */ - }; - - partition@1e0000 { - label = "env"; - reg = <0x001e0000 0x00010000>;/* 64KB */ - }; - - partition@1f0000 { - label = "dtb"; - reg = <0x001f0000 0x00010000>; /* 64KB */ - }; - - partition@200000 { - label = "kernel"; - reg = <0x00200000 0x00e00000>; /* 14MB */ - }; - - partition@1000000 { - label = "rootfs"; - reg = <0x01000000 0x01000000>; /* 16MB */ - }; - }; -}; - -&uart3 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/broadcom/northstar2/ns2.dtsi b/sys/gnu/dts/arm64/broadcom/northstar2/ns2.dtsi deleted file mode 100644 index 15f7b0ed383..00000000000 --- a/sys/gnu/dts/arm64/broadcom/northstar2/ns2.dtsi +++ /dev/null @@ -1,765 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright (c) 2015 Broadcom. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/memreserve/ 0x81000000 0x00200000; - -#include -#include - -/ { - compatible = "brcm,ns2"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - A57_0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0 0>; - enable-method = "psci"; - next-level-cache = <&CLUSTER0_L2>; - }; - - A57_1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0 1>; - enable-method = "psci"; - next-level-cache = <&CLUSTER0_L2>; - }; - - A57_2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0 2>; - enable-method = "psci"; - next-level-cache = <&CLUSTER0_L2>; - }; - - A57_3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0 3>; - enable-method = "psci"; - next-level-cache = <&CLUSTER0_L2>; - }; - - CLUSTER0_L2: l2-cache@0 { - compatible = "cache"; - }; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = , - , - , - ; - interrupt-affinity = <&A57_0>, - <&A57_1>, - <&A57_2>, - <&A57_3>; - }; - - pcie0: pcie@20020000 { - compatible = "brcm,iproc-pcie"; - reg = <0 0x20020000 0 0x1000>; - dma-coherent; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>; - - linux,pci-domain = <0>; - - bus-range = <0x00 0xff>; - - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges = <0x83000000 0 0x00000000 0 0x00000000 0 0x20000000>; - - brcm,pcie-ob; - brcm,pcie-ob-oarr-size; - brcm,pcie-ob-axi-offset = <0x00000000>; - brcm,pcie-ob-window-size = <256>; - - status = "disabled"; - - phys = <&pci_phy0>; - phy-names = "pcie-phy"; - - msi-parent = <&v2m0>; - }; - - pcie4: pcie@50020000 { - compatible = "brcm,iproc-pcie"; - reg = <0 0x50020000 0 0x1000>; - dma-coherent; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; - - linux,pci-domain = <4>; - - bus-range = <0x00 0xff>; - - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges = <0x83000000 0 0x00000000 0 0x30000000 0 0x20000000>; - - brcm,pcie-ob; - brcm,pcie-ob-oarr-size; - brcm,pcie-ob-axi-offset = <0x30000000>; - brcm,pcie-ob-window-size = <256>; - - status = "disabled"; - - phys = <&pci_phy1>; - phy-names = "pcie-phy"; - - msi-parent = <&v2m0>; - }; - - pcie8: pcie@60c00000 { - compatible = "brcm,iproc-pcie-paxc"; - reg = <0 0x60c00000 0 0x1000>; - dma-coherent; - linux,pci-domain = <8>; - - bus-range = <0x0 0x1>; - - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges = <0x83000000 0 0x00000000 0 0x60000000 0 0x00c00000>; - - status = "disabled"; - - msi-parent = <&v2m0>; - }; - - soc: soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0 0xffffffff>; - - #include "ns2-clock.dtsi" - - enet: ethernet@61000000 { - compatible = "brcm,ns2-amac"; - reg = <0x61000000 0x1000>, - <0x61090000 0x1000>, - <0x61030000 0x100>; - reg-names = "amac_base", "idm_base", "nicpm_base"; - interrupts = ; - dma-coherent; - phy-handle = <&gphy0>; - phy-mode = "rgmii"; - status = "disabled"; - }; - - pdc0: iproc-pdc0@612c0000 { - compatible = "brcm,iproc-pdc-mbox"; - reg = <0x612c0000 0x445>; /* PDC FS0 regs */ - interrupts = ; - #mbox-cells = <1>; - dma-coherent; - brcm,rx-status-len = <32>; - brcm,use-bcm-hdr; - }; - - crypto0: crypto@612d0000 { - compatible = "brcm,spum-crypto"; - reg = <0x612d0000 0x900>; - mboxes = <&pdc0 0>; - }; - - pdc1: iproc-pdc1@612e0000 { - compatible = "brcm,iproc-pdc-mbox"; - reg = <0x612e0000 0x445>; /* PDC FS1 regs */ - interrupts = ; - #mbox-cells = <1>; - dma-coherent; - brcm,rx-status-len = <32>; - brcm,use-bcm-hdr; - }; - - crypto1: crypto@612f0000 { - compatible = "brcm,spum-crypto"; - reg = <0x612f0000 0x900>; - mboxes = <&pdc1 0>; - }; - - pdc2: iproc-pdc2@61300000 { - compatible = "brcm,iproc-pdc-mbox"; - reg = <0x61300000 0x445>; /* PDC FS2 regs */ - interrupts = ; - #mbox-cells = <1>; - dma-coherent; - brcm,rx-status-len = <32>; - brcm,use-bcm-hdr; - }; - - crypto2: crypto@61310000 { - compatible = "brcm,spum-crypto"; - reg = <0x61310000 0x900>; - mboxes = <&pdc2 0>; - }; - - pdc3: iproc-pdc3@61320000 { - compatible = "brcm,iproc-pdc-mbox"; - reg = <0x61320000 0x445>; /* PDC FS3 regs */ - interrupts = ; - #mbox-cells = <1>; - dma-coherent; - brcm,rx-status-len = <32>; - brcm,use-bcm-hdr; - }; - - crypto3: crypto@61330000 { - compatible = "brcm,spum-crypto"; - reg = <0x61330000 0x900>; - mboxes = <&pdc3 0>; - }; - - dma0: dma@61360000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x61360000 0x1000>; - interrupts = , - , - , - , - , - , - , - , - ; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; - clocks = <&iprocslow>; - clock-names = "apb_pclk"; - }; - - smmu: mmu@64000000 { - compatible = "arm,mmu-500"; - reg = <0x64000000 0x40000>; - #global-interrupts = <2>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - #iommu-cells = <1>; - }; - - pinctrl: pinctrl@6501d130 { - compatible = "brcm,ns2-pinmux"; - reg = <0x6501d130 0x08>, - <0x660a0028 0x04>, - <0x660009b0 0x40>; - }; - - gpio_aon: gpio@65024800 { - compatible = "brcm,iproc-gpio"; - reg = <0x65024800 0x50>, - <0x65024008 0x18>; - ngpios = <6>; - #gpio-cells = <2>; - gpio-controller; - }; - - gic: interrupt-controller@65210000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x65210000 0x1000>, - <0x65220000 0x1000>, - <0x65240000 0x2000>, - <0x65260000 0x1000>; - interrupts = ; - - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x652e0000 0x80000>; - - v2m0: v2m@0 { - compatible = "arm,gic-v2m-frame"; - interrupt-parent = <&gic>; - msi-controller; - reg = <0x00000 0x1000>; - arm,msi-base-spi = <72>; - arm,msi-num-spis = <16>; - }; - - v2m1: v2m@10000 { - compatible = "arm,gic-v2m-frame"; - interrupt-parent = <&gic>; - msi-controller; - reg = <0x10000 0x1000>; - arm,msi-base-spi = <88>; - arm,msi-num-spis = <16>; - }; - - v2m2: v2m@20000 { - compatible = "arm,gic-v2m-frame"; - interrupt-parent = <&gic>; - msi-controller; - reg = <0x20000 0x1000>; - arm,msi-base-spi = <104>; - arm,msi-num-spis = <16>; - }; - - v2m3: v2m@30000 { - compatible = "arm,gic-v2m-frame"; - interrupt-parent = <&gic>; - msi-controller; - reg = <0x30000 0x1000>; - arm,msi-base-spi = <120>; - arm,msi-num-spis = <16>; - }; - - v2m4: v2m@40000 { - compatible = "arm,gic-v2m-frame"; - interrupt-parent = <&gic>; - msi-controller; - reg = <0x40000 0x1000>; - arm,msi-base-spi = <136>; - arm,msi-num-spis = <16>; - }; - - v2m5: v2m@50000 { - compatible = "arm,gic-v2m-frame"; - interrupt-parent = <&gic>; - msi-controller; - reg = <0x50000 0x1000>; - arm,msi-base-spi = <152>; - arm,msi-num-spis = <16>; - }; - - v2m6: v2m@60000 { - compatible = "arm,gic-v2m-frame"; - interrupt-parent = <&gic>; - msi-controller; - reg = <0x60000 0x1000>; - arm,msi-base-spi = <168>; - arm,msi-num-spis = <16>; - }; - - v2m7: v2m@70000 { - compatible = "arm,gic-v2m-frame"; - interrupt-parent = <&gic>; - msi-controller; - reg = <0x70000 0x1000>; - arm,msi-base-spi = <184>; - arm,msi-num-spis = <16>; - }; - }; - - cci@65590000 { - compatible = "arm,cci-400"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x65590000 0x1000>; - ranges = <0 0x65590000 0x10000>; - - pmu@9000 { - compatible = "arm,cci-400-pmu,r1", - "arm,cci-400-pmu"; - reg = <0x9000 0x4000>; - interrupts = , - , - , - , - , - ; - }; - }; - - usbdrd_phy: phy@66000960 { - #phy-cells = <0>; - compatible = "brcm,ns2-drd-phy"; - reg = <0x66000960 0x24>, - <0x67012800 0x4>, - <0x6501d148 0x4>, - <0x664d0700 0x4>; - reg-names = "icfg", "rst-ctrl", - "crmu-ctrl", "usb2-strap"; - id-gpios = <&gpio_g 30 0>; - vbus-gpios = <&gpio_g 31 0>; - status = "disabled"; - }; - - pwm: pwm@66010000 { - compatible = "brcm,iproc-pwm"; - reg = <0x66010000 0x28>; - clocks = <&osc>; - #pwm-cells = <3>; - status = "disabled"; - }; - - mdio_mux_iproc: mdio-mux@66020000 { - compatible = "brcm,mdio-mux-iproc"; - reg = <0x66020000 0x250>; - #address-cells = <1>; - #size-cells = <0>; - - mdio@0 { - reg = <0x0>; - #address-cells = <1>; - #size-cells = <0>; - - pci_phy0: pci-phy@0 { - compatible = "brcm,ns2-pcie-phy"; - reg = <0x0>; - #phy-cells = <0>; - status = "disabled"; - }; - }; - - mdio@7 { - reg = <0x7>; - #address-cells = <1>; - #size-cells = <0>; - - pci_phy1: pci-phy@0 { - compatible = "brcm,ns2-pcie-phy"; - reg = <0x0>; - #phy-cells = <0>; - status = "disabled"; - }; - }; - - mdio@10 { - reg = <0x10>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - timer0: timer@66030000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x66030000 0x1000>; - interrupts = ; - clocks = <&iprocslow>, - <&iprocslow>, - <&iprocslow>; - clock-names = "timer1", "timer2", "apb_pclk"; - }; - - timer1: timer@66040000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x66040000 0x1000>; - interrupts = ; - clocks = <&iprocslow>, - <&iprocslow>, - <&iprocslow>; - clock-names = "timer1", "timer2", "apb_pclk"; - }; - - timer2: timer@66050000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x66050000 0x1000>; - interrupts = ; - clocks = <&iprocslow>, - <&iprocslow>, - <&iprocslow>; - clock-names = "timer1", "timer2", "apb_pclk"; - }; - - timer3: timer@66060000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x66060000 0x1000>; - interrupts = ; - clocks = <&iprocslow>, - <&iprocslow>, - <&iprocslow>; - clock-names = "timer1", "timer2", "apb_pclk"; - }; - - i2c0: i2c@66080000 { - compatible = "brcm,iproc-i2c"; - reg = <0x66080000 0x100>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clock-frequency = <100000>; - status = "disabled"; - }; - - wdt0: watchdog@66090000 { - compatible = "arm,sp805", "arm,primecell"; - reg = <0x66090000 0x1000>; - interrupts = ; - clocks = <&iprocslow>, <&iprocslow>; - clock-names = "wdogclk", "apb_pclk"; - }; - - gpio_g: gpio@660a0000 { - compatible = "brcm,iproc-gpio"; - reg = <0x660a0000 0x50>; - ngpios = <32>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - interrupts = ; - }; - - i2c1: i2c@660b0000 { - compatible = "brcm,iproc-i2c"; - reg = <0x660b0000 0x100>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clock-frequency = <100000>; - status = "disabled"; - }; - - uart0: serial@66100000 { - compatible = "snps,dw-apb-uart"; - reg = <0x66100000 0x100>; - interrupts = ; - clocks = <&iprocslow>; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uart1: serial@66110000 { - compatible = "snps,dw-apb-uart"; - reg = <0x66110000 0x100>; - interrupts = ; - clocks = <&iprocslow>; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uart2: serial@66120000 { - compatible = "snps,dw-apb-uart"; - reg = <0x66120000 0x100>; - interrupts = ; - clocks = <&iprocslow>; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uart3: serial@66130000 { - compatible = "snps,dw-apb-uart"; - reg = <0x66130000 0x100>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&osc>; - status = "disabled"; - }; - - ssp0: spi@66180000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x66180000 0x1000>; - interrupts = ; - clocks = <&iprocslow>, <&iprocslow>; - clock-names = "spiclk", "apb_pclk"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - ssp1: spi@66190000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x66190000 0x1000>; - interrupts = ; - clocks = <&iprocslow>, <&iprocslow>; - clock-names = "spiclk", "apb_pclk"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - hwrng: hwrng@66220000 { - compatible = "brcm,iproc-rng200"; - reg = <0x66220000 0x28>; - }; - - sata_phy: sata_phy@663f0100 { - compatible = "brcm,iproc-ns2-sata-phy"; - reg = <0x663f0100 0x1f00>, - <0x663f004c 0x10>; - reg-names = "phy", "phy-ctrl"; - #address-cells = <1>; - #size-cells = <0>; - - sata_phy0: sata-phy@0 { - reg = <0>; - #phy-cells = <0>; - status = "disabled"; - }; - - sata_phy1: sata-phy@1 { - reg = <1>; - #phy-cells = <0>; - status = "disabled"; - }; - }; - - sata: ahci@663f2000 { - compatible = "brcm,iproc-ahci", "generic-ahci"; - reg = <0x663f2000 0x1000>; - dma-coherent; - reg-names = "ahci"; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - sata0: sata-port@0 { - reg = <0>; - phys = <&sata_phy0>; - phy-names = "sata-phy"; - }; - - sata1: sata-port@1 { - reg = <1>; - phys = <&sata_phy1>; - phy-names = "sata-phy"; - }; - }; - - sdio0: sdhci@66420000 { - compatible = "brcm,sdhci-iproc-cygnus"; - reg = <0x66420000 0x100>; - interrupts = ; - dma-coherent; - bus-width = <8>; - clocks = <&genpll_sw BCM_NS2_GENPLL_SW_SDIO_CLK>; - status = "disabled"; - }; - - sdio1: sdhci@66430000 { - compatible = "brcm,sdhci-iproc-cygnus"; - reg = <0x66430000 0x100>; - interrupts = ; - dma-coherent; - bus-width = <8>; - clocks = <&genpll_sw BCM_NS2_GENPLL_SW_SDIO_CLK>; - status = "disabled"; - }; - - nand: nand@66460000 { - compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1"; - reg = <0x66460000 0x600>, - <0x67015408 0x600>, - <0x66460f00 0x20>; - reg-names = "nand", "iproc-idm", "iproc-ext"; - interrupts = ; - - #address-cells = <1>; - #size-cells = <0>; - - brcm,nand-has-wp; - }; - - qspi: spi@66470200 { - compatible = "brcm,spi-bcm-qspi", "brcm,spi-ns2-qspi"; - reg = <0x66470200 0x184>, - <0x66470000 0x124>, - <0x67017408 0x004>, - <0x664703a0 0x01c>; - reg-names = "mspi", "bspi", "intr_regs", - "intr_status_reg"; - interrupts = ; - interrupt-names = "spi_l1_intr"; - clocks = <&iprocmed>; - clock-names = "iprocmed"; - num-cs = <2>; - #address-cells = <1>; - #size-cells = <0>; - }; - - }; -}; diff --git a/sys/gnu/dts/arm64/broadcom/stingray/bcm958742-base.dtsi b/sys/gnu/dts/arm64/broadcom/stingray/bcm958742-base.dtsi deleted file mode 100644 index a9b92e52d50..00000000000 --- a/sys/gnu/dts/arm64/broadcom/stingray/bcm958742-base.dtsi +++ /dev/null @@ -1,176 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright(c) 2016-2017 Broadcom. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "stingray-board-base.dtsi" - -/ { - sdio0_vddo_ctrl_reg: sdio0_vddo_ctrl { - compatible = "regulator-gpio"; - regulator-name = "sdio0_vddo_ctrl_reg"; - regulator-type = "voltage"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - gpios = <&pca9505 18 0>; - states = <3300000 0x0 - 1800000 0x1>; - }; - - sdio1_vddo_ctrl_reg: sdio1_vddo_ctrl { - compatible = "regulator-gpio"; - regulator-name = "sdio1_vddo_ctrl_reg"; - regulator-type = "voltage"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - gpios = <&pca9505 19 0>; - states = <3300000 0x0 - 1800000 0x1>; - }; -}; - -&sata0 { - status = "okay"; -}; - -&sata_phy0{ - status = "okay"; -}; - -&sata1 { - status = "okay"; -}; - -&sata_phy1{ - status = "okay"; -}; - -&sata2 { - status = "okay"; -}; - -&sata_phy2{ - status = "okay"; -}; - -&sata3 { - status = "okay"; -}; - -&sata_phy3{ - status = "okay"; -}; - -&sata4 { - status = "okay"; -}; - -&sata_phy4{ - status = "okay"; -}; - -&sata5 { - status = "okay"; -}; - -&sata_phy5{ - status = "okay"; -}; - -&sata6 { - status = "okay"; -}; - -&sata_phy6{ - status = "okay"; -}; - -&sata7 { - status = "okay"; -}; - -&sata_phy7{ - status = "okay"; -}; - -&pwm { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - pca9505: pca9505@20 { - compatible = "nxp,pca9505"; - gpio-controller; - #gpio-cells = <2>; - reg = <0x20>; - }; -}; - -&i2c1 { - status = "okay"; - - pcf8574: pcf8574@27 { - compatible = "nxp,pcf8574a"; - gpio-controller; - #gpio-cells = <2>; - reg = <0x27>; - }; -}; - -&enet { - status = "okay"; -}; - -&nand { - status = "ok"; - nandcs@0 { - compatible = "brcm,nandcs"; - reg = <0>; - nand-ecc-mode = "hw"; - nand-ecc-strength = <8>; - nand-ecc-step-size = <512>; - nand-bus-width = <16>; - brcm,nand-oob-sector-size = <16>; - #address-cells = <1>; - #size-cells = <1>; - }; -}; - -&sdio0 { - vqmmc-supply = <&sdio0_vddo_ctrl_reg>; - status = "okay"; -}; - -&sdio1 { - vqmmc-supply = <&sdio1_vddo_ctrl_reg>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/broadcom/stingray/bcm958742k.dts b/sys/gnu/dts/arm64/broadcom/stingray/bcm958742k.dts deleted file mode 100644 index 77efa28c4dd..00000000000 --- a/sys/gnu/dts/arm64/broadcom/stingray/bcm958742k.dts +++ /dev/null @@ -1,86 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright(c) 2016-2017 Broadcom. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/dts-v1/; - -#include "bcm958742-base.dtsi" - -/ { - compatible = "brcm,bcm958742k", "brcm,stingray"; - model = "Stingray Combo SVK (BCM958742K)"; -}; - -&gphy0 { - enet-phy-lane-swap; -}; - -&sdio0 { - mmc-ddr-1_8v; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&ssp0 { - pinctrl-0 = <&spi0_pins>; - pinctrl-names = "default"; - cs-gpios = <&gpio_hsls 34 0>; - status = "okay"; - - spi-flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <20000000>; - #address-cells = <1>; - #size-cells = <1>; - }; -}; - -&ssp1 { - pinctrl-0 = <&spi1_pins>; - pinctrl-names = "default"; - cs-gpios = <&gpio_hsls 96 0>; - status = "okay"; - - spi-flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <20000000>; - #address-cells = <1>; - #size-cells = <1>; - }; -}; diff --git a/sys/gnu/dts/arm64/broadcom/stingray/bcm958742t.dts b/sys/gnu/dts/arm64/broadcom/stingray/bcm958742t.dts deleted file mode 100644 index 55ba495ef56..00000000000 --- a/sys/gnu/dts/arm64/broadcom/stingray/bcm958742t.dts +++ /dev/null @@ -1,48 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright(c) 2017 Broadcom. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/dts-v1/; - -#include "bcm958742-base.dtsi" - -/ { - compatible = "brcm,bcm958742t", "brcm,stingray"; - model = "Stingray SST100 (BCM958742T)"; -}; - -&gphy0 { - enet-phy-lane-swap; -}; - -&sdio0 { - mmc-ddr-1_8v; -}; diff --git a/sys/gnu/dts/arm64/broadcom/stingray/bcm958802a802x.dts b/sys/gnu/dts/arm64/broadcom/stingray/bcm958802a802x.dts deleted file mode 100644 index a41facd7d79..00000000000 --- a/sys/gnu/dts/arm64/broadcom/stingray/bcm958802a802x.dts +++ /dev/null @@ -1,26 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 or BSD-3-Clause) -/* - *Copyright(c) 2018 Broadcom - */ - -/dts-v1/; - -#include "stingray-board-base.dtsi" - -/ { - compatible = "brcm,bcm958802a802x", "brcm,stingray"; - model = "Stingray PS225xx (BCM958802A802x)"; -}; - -&enet { - status = "disabled"; -}; - -&sdio0 { - no-1-8-v; - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/broadcom/stingray/stingray-board-base.dtsi b/sys/gnu/dts/arm64/broadcom/stingray/stingray-board-base.dtsi deleted file mode 100644 index 82a24711d0d..00000000000 --- a/sys/gnu/dts/arm64/broadcom/stingray/stingray-board-base.dtsi +++ /dev/null @@ -1,51 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 or BSD-3-Clause) -/* - * Copyright(c) 2016-2018 Broadcom - */ - -#include "stingray.dtsi" -#include - -/ { - aliases { - serial0 = &uart1; - serial1 = &uart0; - serial2 = &uart2; - serial3 = &uart3; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&memory { /* Default DRAM banks */ - reg = <0x00000000 0x80000000 0x0 0x80000000>, /* 2G @ 2G */ - <0x00000008 0x80000000 0x1 0x80000000>; /* 6G @ 34G */ -}; - -&enet { - phy-mode = "rgmii-id"; - phy-handle = <&gphy0>; -}; - -&uart1 { - status = "okay"; -}; - -&sdio0 { - non-removable; - full-pwr-cycle; -}; - -&sdio1 { - full-pwr-cycle; -}; - -&mdio_mux_iproc { - mdio@10 { - gphy0: eth-phy@10 { - reg = <0x10>; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/broadcom/stingray/stingray-clock.dtsi b/sys/gnu/dts/arm64/broadcom/stingray/stingray-clock.dtsi deleted file mode 100644 index 10a106aca22..00000000000 --- a/sys/gnu/dts/arm64/broadcom/stingray/stingray-clock.dtsi +++ /dev/null @@ -1,182 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright(c) 2016-2017 Broadcom. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include - - osc: oscillator { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <50000000>; - }; - - crmu_ref25m: crmu_ref25m { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&osc>; - clock-div = <2>; - clock-mult = <1>; - }; - - genpll0: genpll0@1d104 { - #clock-cells = <1>; - compatible = "brcm,sr-genpll0"; - reg = <0x0001d104 0x32>, - <0x0001c854 0x4>; - clocks = <&osc>; - clock-output-names = "genpll0", "clk_125m", "clk_scr", - "clk_250", "clk_pcie_axi", - "clk_paxc_axi_x2", - "clk_paxc_axi"; - }; - - genpll2: genpll2@1d1ac { - #clock-cells = <1>; - compatible = "brcm,sr-genpll2"; - reg = <0x0001d1ac 0x32>, - <0x0001c854 0x4>; - clocks = <&osc>; - clock-output-names = "genpll2", "clk_nic", - "clk_ts_500_ref", "clk_125_nitro", - "clk_chimp", "clk_nic_flash", - "clk_fs"; - }; - - genpll3: genpll3@1d1e0 { - #clock-cells = <1>; - compatible = "brcm,sr-genpll3"; - reg = <0x0001d1e0 0x32>, - <0x0001c854 0x4>; - clocks = <&osc>; - clock-output-names = "genpll3", "clk_hsls", - "clk_sdio"; - }; - - genpll4: genpll4@1d214 { - #clock-cells = <1>; - compatible = "brcm,sr-genpll4"; - reg = <0x0001d214 0x32>, - <0x0001c854 0x4>; - clocks = <&osc>; - clock-output-names = "genpll4", "clk_ccn", - "clk_tpiu_pll", "clk_noc", - "clk_chclk_fs4", - "clk_bridge_fscpu"; - }; - - genpll5: genpll5@1d248 { - #clock-cells = <1>; - compatible = "brcm,sr-genpll5"; - reg = <0x0001d248 0x32>, - <0x0001c870 0x4>; - clocks = <&osc>; - clock-output-names = "genpll5", "clk_fs4_hf", - "clk_crypto_ae", "clk_raid_ae"; - }; - - lcpll0: lcpll0@1d0c4 { - #clock-cells = <1>; - compatible = "brcm,sr-lcpll0"; - reg = <0x0001d0c4 0x3c>, - <0x0001c870 0x4>; - clocks = <&osc>; - clock-output-names = "lcpll0", "clk_sata_refp", - "clk_sata_refn", "clk_sata_350", - "clk_sata_500"; - }; - - lcpll1: lcpll1@1d138 { - #clock-cells = <1>; - compatible = "brcm,sr-lcpll1"; - reg = <0x0001d138 0x3c>, - <0x0001c870 0x4>; - clocks = <&osc>; - clock-output-names = "lcpll1", "clk_wan", - "clk_usb_ref", - "clk_crmu_ts"; - }; - - hsls_clk: hsls_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&genpll3 1>; - clock-div = <1>; - clock-mult = <1>; - }; - - hsls_div2_clk: hsls_div2_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&genpll3 BCM_SR_GENPLL3_HSLS_CLK>; - clock-div = <2>; - clock-mult = <1>; - - }; - - hsls_div4_clk: hsls_div4_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&genpll3 BCM_SR_GENPLL3_HSLS_CLK>; - clock-div = <4>; - clock-mult = <1>; - }; - - hsls_25m_clk: hsls_25m_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&crmu_ref25m>; - clock-div = <1>; - clock-mult = <1>; - }; - - hsls_25m_div2_clk: hsls_25m_div2_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&hsls_25m_clk>; - clock-div = <2>; - clock-mult = <1>; - }; - - sdio0_clk: sdio0_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&genpll3 BCM_SR_GENPLL3_SDIO_CLK>; - clock-div = <1>; - clock-mult = <1>; - }; - - sdio1_clk: sdio1_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&genpll3 BCM_SR_GENPLL3_SDIO_CLK>; - clock-div = <1>; - clock-mult = <1>; - }; diff --git a/sys/gnu/dts/arm64/broadcom/stingray/stingray-fs4.dtsi b/sys/gnu/dts/arm64/broadcom/stingray/stingray-fs4.dtsi deleted file mode 100644 index 9666969c8c8..00000000000 --- a/sys/gnu/dts/arm64/broadcom/stingray/stingray-fs4.dtsi +++ /dev/null @@ -1,118 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright(c) 2016-2017 Broadcom. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - - fs4: fs4 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x67000000 0x00800000>; - - crypto_mbox: crypto_mbox@0 { - compatible = "brcm,iproc-flexrm-mbox"; - reg = <0x00000000 0x200000>; - msi-parent = <&gic_its 0x4100>; - #mbox-cells = <3>; - dma-coherent; - }; - - raid_mbox: raid_mbox@400000 { - compatible = "brcm,iproc-flexrm-mbox"; - reg = <0x00400000 0x200000>; - dma-coherent; - msi-parent = <&gic_its 0x4300>; - #mbox-cells = <3>; - }; - - raid0: raid@0 { - compatible = "brcm,iproc-sba-v2"; - mboxes = <&raid_mbox 0 0x1 0xff00>, - <&raid_mbox 1 0x1 0xff00>, - <&raid_mbox 2 0x1 0xff00>, - <&raid_mbox 3 0x1 0xff00>; - }; - - raid1: raid@1 { - compatible = "brcm,iproc-sba-v2"; - mboxes = <&raid_mbox 4 0x1 0xff00>, - <&raid_mbox 5 0x1 0xff00>, - <&raid_mbox 6 0x1 0xff00>, - <&raid_mbox 7 0x1 0xff00>; - }; - - raid2: raid@2 { - compatible = "brcm,iproc-sba-v2"; - mboxes = <&raid_mbox 8 0x1 0xff00>, - <&raid_mbox 9 0x1 0xff00>, - <&raid_mbox 10 0x1 0xff00>, - <&raid_mbox 11 0x1 0xff00>; - }; - - raid3: raid@3 { - compatible = "brcm,iproc-sba-v2"; - mboxes = <&raid_mbox 12 0x1 0xff00>, - <&raid_mbox 13 0x1 0xff00>, - <&raid_mbox 14 0x1 0xff00>, - <&raid_mbox 15 0x1 0xff00>; - }; - - raid4: raid@4 { - compatible = "brcm,iproc-sba-v2"; - mboxes = <&raid_mbox 16 0x1 0xff00>, - <&raid_mbox 17 0x1 0xff00>, - <&raid_mbox 18 0x1 0xff00>, - <&raid_mbox 19 0x1 0xff00>; - }; - - raid5: raid@5 { - compatible = "brcm,iproc-sba-v2"; - mboxes = <&raid_mbox 20 0x1 0xff00>, - <&raid_mbox 21 0x1 0xff00>, - <&raid_mbox 22 0x1 0xff00>, - <&raid_mbox 23 0x1 0xff00>; - }; - - raid6: raid@6 { - compatible = "brcm,iproc-sba-v2"; - mboxes = <&raid_mbox 24 0x1 0xff00>, - <&raid_mbox 25 0x1 0xff00>, - <&raid_mbox 26 0x1 0xff00>, - <&raid_mbox 27 0x1 0xff00>; - }; - - raid7: raid@7 { - compatible = "brcm,iproc-sba-v2"; - mboxes = <&raid_mbox 28 0x1 0xff00>, - <&raid_mbox 29 0x1 0xff00>, - <&raid_mbox 30 0x1 0xff00>, - <&raid_mbox 31 0x1 0xff00>; - }; - }; diff --git a/sys/gnu/dts/arm64/broadcom/stingray/stingray-pcie.dtsi b/sys/gnu/dts/arm64/broadcom/stingray/stingray-pcie.dtsi deleted file mode 100644 index 33a472ab17e..00000000000 --- a/sys/gnu/dts/arm64/broadcom/stingray/stingray-pcie.dtsi +++ /dev/null @@ -1,54 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 or BSD-3-Clause) -/* - *Copyright(c) 2018 Broadcom - */ - -pcie8: pcie@60400000 { - compatible = "brcm,iproc-pcie-paxc-v2"; - reg = <0 0x60400000 0 0x1000>; - linux,pci-domain = <8>; - - bus-range = <0x0 0x1>; - - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges = <0x83000000 0 0x10000000 0 0x10000000 0 0x20000000>; - - dma-coherent; - - msi-map = <0x100 &gic_its 0x2000 0x1>, /* PF0 */ - <0x108 &gic_its 0x2040 0x8>, /* PF0-VF0-7 */ - <0x101 &gic_its 0x2080 0x1>, /* PF1 */ - <0x110 &gic_its 0x20c8 0x8>, /* PF1-VF8-15 */ - <0x102 &gic_its 0x2100 0x1>, /* PF2 */ - <0x118 &gic_its 0x2150 0x8>, /* PF2-VF16-23 */ - <0x103 &gic_its 0x2180 0x1>, /* PF3 */ - <0x120 &gic_its 0x21d8 0x8>, /* PF3-VF24-31 */ - <0x104 &gic_its 0x2200 0x1>, /* PF4 */ - <0x128 &gic_its 0x2260 0x8>, /* PF4-VF32-39 */ - <0x105 &gic_its 0x2280 0x1>, /* PF5 */ - <0x130 &gic_its 0x22e8 0x8>, /* PF5-VF40-47 */ - <0x106 &gic_its 0x2300 0x1>, /* PF6 */ - <0x138 &gic_its 0x2370 0x8>, /* PF6-VF48-55 */ - <0x107 &gic_its 0x2380 0x1>, /* PF7 */ - <0x140 &gic_its 0x23f8 0x8>; /* PF7-VF56-63 */ - - phys = <&pcie_phy 8>; - phy-names = "pcie-phy"; -}; - -pcie-ss { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x40000000 0x800>; - - pcie_phy: phy@0 { - compatible = "brcm,sr-pcie-phy"; - reg = <0x0 0x200>; - brcm,sr-cdru = <&cdru>; - brcm,sr-mhb = <&mhb>; - #phy-cells = <1>; - }; -}; diff --git a/sys/gnu/dts/arm64/broadcom/stingray/stingray-pinctrl.dtsi b/sys/gnu/dts/arm64/broadcom/stingray/stingray-pinctrl.dtsi deleted file mode 100644 index 56789ccf945..00000000000 --- a/sys/gnu/dts/arm64/broadcom/stingray/stingray-pinctrl.dtsi +++ /dev/null @@ -1,346 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright(c) 2016-2017 Broadcom. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include - - pinconf: pinconf@140000 { - compatible = "pinconf-single"; - reg = <0x00140000 0x250>; - pinctrl-single,register-width = <32>; - - /* pinconf functions */ - }; - - pinmux: pinmux@14029c { - compatible = "pinctrl-single"; - reg = <0x0014029c 0x26c>; - #address-cells = <1>; - #size-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0xf>; - pinctrl-single,gpio-range = < - &range 0 91 MODE_GPIO - &range 95 60 MODE_GPIO - >; - range: gpio-range { - #pinctrl-single,gpio-range-cells = <3>; - }; - - /* pinctrl functions */ - tsio_pins: pinmux_gpio_14 { - pinctrl-single,pins = < - 0x038 MODE_NITRO /* tsio_0 */ - 0x03c MODE_NITRO /* tsio_1 */ - >; - }; - - nor_pins: pinmux_pnor_adv_n { - pinctrl-single,pins = < - 0x0ac MODE_PNOR /* nand_ce1_n */ - 0x0b0 MODE_PNOR /* nand_ce0_n */ - 0x0b4 MODE_PNOR /* nand_we_n */ - 0x0b8 MODE_PNOR /* nand_wp_n */ - 0x0bc MODE_PNOR /* nand_re_n */ - 0x0c0 MODE_PNOR /* nand_rdy_bsy_n */ - 0x0c4 MODE_PNOR /* nand_io0_0 */ - 0x0c8 MODE_PNOR /* nand_io1_0 */ - 0x0cc MODE_PNOR /* nand_io2_0 */ - 0x0d0 MODE_PNOR /* nand_io3_0 */ - 0x0d4 MODE_PNOR /* nand_io4_0 */ - 0x0d8 MODE_PNOR /* nand_io5_0 */ - 0x0dc MODE_PNOR /* nand_io6_0 */ - 0x0e0 MODE_PNOR /* nand_io7_0 */ - 0x0e4 MODE_PNOR /* nand_io8_0 */ - 0x0e8 MODE_PNOR /* nand_io9_0 */ - 0x0ec MODE_PNOR /* nand_io10_0 */ - 0x0f0 MODE_PNOR /* nand_io11_0 */ - 0x0f4 MODE_PNOR /* nand_io12_0 */ - 0x0f8 MODE_PNOR /* nand_io13_0 */ - 0x0fc MODE_PNOR /* nand_io14_0 */ - 0x100 MODE_PNOR /* nand_io15_0 */ - 0x104 MODE_PNOR /* nand_ale_0 */ - 0x108 MODE_PNOR /* nand_cle_0 */ - 0x040 MODE_PNOR /* pnor_adv_n */ - 0x044 MODE_PNOR /* pnor_baa_n */ - 0x048 MODE_PNOR /* pnor_bls_0_n */ - 0x04c MODE_PNOR /* pnor_bls_1_n */ - 0x050 MODE_PNOR /* pnor_cre */ - 0x054 MODE_PNOR /* pnor_cs_2_n */ - 0x058 MODE_PNOR /* pnor_cs_1_n */ - 0x05c MODE_PNOR /* pnor_cs_0_n */ - 0x060 MODE_PNOR /* pnor_we_n */ - 0x064 MODE_PNOR /* pnor_oe_n */ - 0x068 MODE_PNOR /* pnor_intr */ - 0x06c MODE_PNOR /* pnor_dat_0 */ - 0x070 MODE_PNOR /* pnor_dat_1 */ - 0x074 MODE_PNOR /* pnor_dat_2 */ - 0x078 MODE_PNOR /* pnor_dat_3 */ - 0x07c MODE_PNOR /* pnor_dat_4 */ - 0x080 MODE_PNOR /* pnor_dat_5 */ - 0x084 MODE_PNOR /* pnor_dat_6 */ - 0x088 MODE_PNOR /* pnor_dat_7 */ - 0x08c MODE_PNOR /* pnor_dat_8 */ - 0x090 MODE_PNOR /* pnor_dat_9 */ - 0x094 MODE_PNOR /* pnor_dat_10 */ - 0x098 MODE_PNOR /* pnor_dat_11 */ - 0x09c MODE_PNOR /* pnor_dat_12 */ - 0x0a0 MODE_PNOR /* pnor_dat_13 */ - 0x0a4 MODE_PNOR /* pnor_dat_14 */ - 0x0a8 MODE_PNOR /* pnor_dat_15 */ - >; - }; - - nand_pins: pinmux_nand_ce1_n { - pinctrl-single,pins = < - 0x0ac MODE_NAND /* nand_ce1_n */ - 0x0b0 MODE_NAND /* nand_ce0_n */ - 0x0b4 MODE_NAND /* nand_we_n */ - 0x0b8 MODE_NAND /* nand_wp_n */ - 0x0bc MODE_NAND /* nand_re_n */ - 0x0c0 MODE_NAND /* nand_rdy_bsy_n */ - 0x0c4 MODE_NAND /* nand_io0_0 */ - 0x0c8 MODE_NAND /* nand_io1_0 */ - 0x0cc MODE_NAND /* nand_io2_0 */ - 0x0d0 MODE_NAND /* nand_io3_0 */ - 0x0d4 MODE_NAND /* nand_io4_0 */ - 0x0d8 MODE_NAND /* nand_io5_0 */ - 0x0dc MODE_NAND /* nand_io6_0 */ - 0x0e0 MODE_NAND /* nand_io7_0 */ - 0x0e4 MODE_NAND /* nand_io8_0 */ - 0x0e8 MODE_NAND /* nand_io9_0 */ - 0x0ec MODE_NAND /* nand_io10_0 */ - 0x0f0 MODE_NAND /* nand_io11_0 */ - 0x0f4 MODE_NAND /* nand_io12_0 */ - 0x0f8 MODE_NAND /* nand_io13_0 */ - 0x0fc MODE_NAND /* nand_io14_0 */ - 0x100 MODE_NAND /* nand_io15_0 */ - 0x104 MODE_NAND /* nand_ale_0 */ - 0x108 MODE_NAND /* nand_cle_0 */ - >; - }; - - pwm0_pins: pinmux_pwm_0 { - pinctrl-single,pins = < - 0x10c MODE_NITRO - >; - }; - - pwm1_pins: pinmux_pwm_1 { - pinctrl-single,pins = < - 0x110 MODE_NITRO - >; - }; - - pwm2_pins: pinmux_pwm_2 { - pinctrl-single,pins = < - 0x114 MODE_NITRO - >; - }; - - pwm3_pins: pinmux_pwm_3 { - pinctrl-single,pins = < - 0x118 MODE_NITRO - >; - }; - - dbu_rxd_pins: pinmux_uart1_sin_nitro { - pinctrl-single,pins = < - 0x11c MODE_NITRO /* dbu_rxd */ - 0x120 MODE_NITRO /* dbu_txd */ - >; - }; - - uart1_pins: pinmux_uart1_sin_nand { - pinctrl-single,pins = < - 0x11c MODE_NAND /* uart1_sin */ - 0x120 MODE_NAND /* uart1_out */ - >; - }; - - uart2_pins: pinmux_uart2_sin { - pinctrl-single,pins = < - 0x124 MODE_NITRO /* uart2_sin */ - 0x128 MODE_NITRO /* uart2_out */ - >; - }; - - uart3_pins: pinmux_uart3_sin { - pinctrl-single,pins = < - 0x12c MODE_NITRO /* uart3_sin */ - 0x130 MODE_NITRO /* uart3_out */ - >; - }; - - i2s_pins: pinmux_i2s_bitclk { - pinctrl-single,pins = < - 0x134 MODE_NITRO /* i2s_bitclk */ - 0x138 MODE_NITRO /* i2s_sdout */ - 0x13c MODE_NITRO /* i2s_sdin */ - 0x140 MODE_NITRO /* i2s_ws */ - 0x144 MODE_NITRO /* i2s_mclk */ - 0x148 MODE_NITRO /* i2s_spdif_out */ - >; - }; - - qspi_pins: pinumx_qspi_hold_n { - pinctrl-single,pins = < - 0x14c MODE_NAND /* qspi_hold_n */ - 0x150 MODE_NAND /* qspi_wp_n */ - 0x154 MODE_NAND /* qspi_sck */ - 0x158 MODE_NAND /* qspi_cs_n */ - 0x15c MODE_NAND /* qspi_mosi */ - 0x160 MODE_NAND /* qspi_miso */ - >; - }; - - mdio_pins: pinumx_ext_mdio { - pinctrl-single,pins = < - 0x164 MODE_NITRO /* ext_mdio */ - 0x168 MODE_NITRO /* ext_mdc */ - >; - }; - - i2c0_pins: pinmux_i2c0_sda { - pinctrl-single,pins = < - 0x16c MODE_NITRO /* i2c0_sda */ - 0x170 MODE_NITRO /* i2c0_scl */ - >; - }; - - i2c1_pins: pinmux_i2c1_sda { - pinctrl-single,pins = < - 0x174 MODE_NITRO /* i2c1_sda */ - 0x178 MODE_NITRO /* i2c1_scl */ - >; - }; - - sdio0_pins: pinmux_sdio0_cd_l { - pinctrl-single,pins = < - 0x17c MODE_NITRO /* sdio0_cd_l */ - 0x180 MODE_NITRO /* sdio0_clk_sdcard */ - 0x184 MODE_NITRO /* sdio0_data0 */ - 0x188 MODE_NITRO /* sdio0_data1 */ - 0x18c MODE_NITRO /* sdio0_data2 */ - 0x190 MODE_NITRO /* sdio0_data3 */ - 0x194 MODE_NITRO /* sdio0_data4 */ - 0x198 MODE_NITRO /* sdio0_data5 */ - 0x19c MODE_NITRO /* sdio0_data6 */ - 0x1a0 MODE_NITRO /* sdio0_data7 */ - 0x1a4 MODE_NITRO /* sdio0_cmd */ - 0x1a8 MODE_NITRO /* sdio0_emmc_rst_n */ - 0x1ac MODE_NITRO /* sdio0_led_on */ - 0x1b0 MODE_NITRO /* sdio0_wp */ - >; - }; - - sdio1_pins: pinmux_sdio1_cd_l { - pinctrl-single,pins = < - 0x1b4 MODE_NITRO /* sdio1_cd_l */ - 0x1b8 MODE_NITRO /* sdio1_clk_sdcard */ - 0x1bc MODE_NITRO /* sdio1_data0 */ - 0x1c0 MODE_NITRO /* sdio1_data1 */ - 0x1c4 MODE_NITRO /* sdio1_data2 */ - 0x1c8 MODE_NITRO /* sdio1_data3 */ - 0x1cc MODE_NITRO /* sdio1_data4 */ - 0x1d0 MODE_NITRO /* sdio1_data5 */ - 0x1d4 MODE_NITRO /* sdio1_data6 */ - 0x1d8 MODE_NITRO /* sdio1_data7 */ - 0x1dc MODE_NITRO /* sdio1_cmd */ - 0x1e0 MODE_NITRO /* sdio1_emmc_rst_n */ - 0x1e4 MODE_NITRO /* sdio1_led_on */ - 0x1e8 MODE_NITRO /* sdio1_wp */ - >; - }; - - spi0_pins: pinmux_spi0_sck_nand { - pinctrl-single,pins = < - 0x1ec MODE_NITRO /* spi0_sck */ - 0x1f0 MODE_NITRO /* spi0_rxd */ - 0x1f4 MODE_NITRO /* spi0_fss */ - 0x1f8 MODE_NITRO /* spi0_txd */ - >; - }; - - spi1_pins: pinmux_spi1_sck_nand { - pinctrl-single,pins = < - 0x1fc MODE_NITRO /* spi1_sck */ - 0x200 MODE_NITRO /* spi1_rxd */ - 0x204 MODE_NITRO /* spi1_fss */ - 0x208 MODE_NITRO /* spi1_txd */ - >; - }; - - nuart_pins: pinmux_uart0_sin_nitro { - pinctrl-single,pins = < - 0x20c MODE_NITRO /* nuart_rxd */ - 0x210 MODE_NITRO /* nuart_txd */ - >; - }; - - uart0_pins: pinumux_uart0_sin_nand { - pinctrl-single,pins = < - 0x20c MODE_NAND /* uart0_sin */ - 0x210 MODE_NAND /* uart0_out */ - 0x214 MODE_NAND /* uart0_rts */ - 0x218 MODE_NAND /* uart0_cts */ - 0x21c MODE_NAND /* uart0_dtr */ - 0x220 MODE_NAND /* uart0_dcd */ - 0x224 MODE_NAND /* uart0_dsr */ - 0x228 MODE_NAND /* uart0_ri */ - >; - }; - - drdu2_pins: pinmux_drdu2_overcurrent { - pinctrl-single,pins = < - 0x22c MODE_NITRO /* drdu2_overcurrent */ - 0x230 MODE_NITRO /* drdu2_vbus_ppc */ - 0x234 MODE_NITRO /* drdu2_vbus_present */ - 0x238 MODE_NITRO /* drdu2_id */ - >; - }; - - drdu3_pins: pinmux_drdu3_overcurrent { - pinctrl-single,pins = < - 0x23c MODE_NITRO /* drdu3_overcurrent */ - 0x240 MODE_NITRO /* drdu3_vbus_ppc */ - 0x244 MODE_NITRO /* drdu3_vbus_present */ - 0x248 MODE_NITRO /* drdu3_id */ - >; - }; - - usb3h_pins: pinmux_usb3h_overcurrent { - pinctrl-single,pins = < - 0x24c MODE_NITRO /* usb3h_overcurrent */ - 0x250 MODE_NITRO /* usb3h_vbus_ppc */ - >; - }; - }; diff --git a/sys/gnu/dts/arm64/broadcom/stingray/stingray-sata.dtsi b/sys/gnu/dts/arm64/broadcom/stingray/stingray-sata.dtsi deleted file mode 100644 index 8c68e0c26f1..00000000000 --- a/sys/gnu/dts/arm64/broadcom/stingray/stingray-sata.dtsi +++ /dev/null @@ -1,278 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright(c) 2016-2017 Broadcom. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - - sata { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x67d00000 0x00800000>; - - sata0: ahci@0 { - compatible = "brcm,iproc-ahci", "generic-ahci"; - reg = <0x00000000 0x1000>; - reg-names = "ahci"; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - sata0_port0: sata-port@0 { - reg = <0>; - phys = <&sata0_phy0>; - phy-names = "sata-phy"; - }; - }; - - sata_phy0: sata_phy@2100 { - compatible = "brcm,iproc-sr-sata-phy"; - reg = <0x00002100 0x1000>; - reg-names = "phy"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - sata0_phy0: sata-phy@0 { - reg = <0>; - #phy-cells = <0>; - }; - }; - - sata1: ahci@10000 { - compatible = "brcm,iproc-ahci", "generic-ahci"; - reg = <0x00010000 0x1000>; - reg-names = "ahci"; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - sata1_port0: sata-port@0 { - reg = <0>; - phys = <&sata1_phy0>; - phy-names = "sata-phy"; - }; - }; - - sata_phy1: sata_phy@12100 { - compatible = "brcm,iproc-sr-sata-phy"; - reg = <0x00012100 0x1000>; - reg-names = "phy"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - sata1_phy0: sata-phy@0 { - reg = <0>; - #phy-cells = <0>; - }; - }; - - sata2: ahci@20000 { - compatible = "brcm,iproc-ahci", "generic-ahci"; - reg = <0x00020000 0x1000>; - reg-names = "ahci"; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - sata2_port0: sata-port@0 { - reg = <0>; - phys = <&sata2_phy0>; - phy-names = "sata-phy"; - }; - }; - - sata_phy2: sata_phy@22100 { - compatible = "brcm,iproc-sr-sata-phy"; - reg = <0x00022100 0x1000>; - reg-names = "phy"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - sata2_phy0: sata-phy@0 { - reg = <0>; - #phy-cells = <0>; - }; - }; - - sata3: ahci@30000 { - compatible = "brcm,iproc-ahci", "generic-ahci"; - reg = <0x00030000 0x1000>; - reg-names = "ahci"; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - sata3_port0: sata-port@0 { - reg = <0>; - phys = <&sata3_phy0>; - phy-names = "sata-phy"; - }; - }; - - sata_phy3: sata_phy@32100 { - compatible = "brcm,iproc-sr-sata-phy"; - reg = <0x00032100 0x1000>; - reg-names = "phy"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - sata3_phy0: sata-phy@0 { - reg = <0>; - #phy-cells = <0>; - }; - }; - - sata4: ahci@100000 { - compatible = "brcm,iproc-ahci", "generic-ahci"; - reg = <0x00100000 0x1000>; - reg-names = "ahci"; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - sata4_port0: sata-port@0 { - reg = <0>; - phys = <&sata4_phy0>; - phy-names = "sata-phy"; - }; - }; - - sata_phy4: sata_phy@102100 { - compatible = "brcm,iproc-sr-sata-phy"; - reg = <0x00102100 0x1000>; - reg-names = "phy"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - sata4_phy0: sata-phy@0 { - reg = <0>; - #phy-cells = <0>; - }; - }; - - sata5: ahci@110000 { - compatible = "brcm,iproc-ahci", "generic-ahci"; - reg = <0x00110000 0x1000>; - reg-names = "ahci"; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - sata5_port0: sata-port@0 { - reg = <0>; - phys = <&sata5_phy0>; - phy-names = "sata-phy"; - }; - }; - - sata_phy5: sata_phy@112100 { - compatible = "brcm,iproc-sr-sata-phy"; - reg = <0x00112100 0x1000>; - reg-names = "phy"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - sata5_phy0: sata-phy@0 { - reg = <0>; - #phy-cells = <0>; - }; - }; - - sata6: ahci@120000 { - compatible = "brcm,iproc-ahci", "generic-ahci"; - reg = <0x00120000 0x1000>; - reg-names = "ahci"; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - sata6_port0: sata-port@0 { - reg = <0>; - phys = <&sata6_phy0>; - phy-names = "sata-phy"; - }; - }; - - sata_phy6: sata_phy@122100 { - compatible = "brcm,iproc-sr-sata-phy"; - reg = <0x00122100 0x1000>; - reg-names = "phy"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - sata6_phy0: sata-phy@0 { - reg = <0>; - #phy-cells = <0>; - }; - }; - - sata7: ahci@130000 { - compatible = "brcm,iproc-ahci", "generic-ahci"; - reg = <0x00130000 0x1000>; - reg-names = "ahci"; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - sata7_port0: sata-port@0 { - reg = <0>; - phys = <&sata7_phy0>; - phy-names = "sata-phy"; - }; - }; - - sata_phy7: sata_phy@132100 { - compatible = "brcm,iproc-sr-sata-phy"; - reg = <0x00132100 0x1000>; - reg-names = "phy"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - sata7_phy0: sata-phy@0 { - reg = <0>; - #phy-cells = <0>; - }; - }; - }; diff --git a/sys/gnu/dts/arm64/broadcom/stingray/stingray-usb.dtsi b/sys/gnu/dts/arm64/broadcom/stingray/stingray-usb.dtsi deleted file mode 100644 index 55259f973b5..00000000000 --- a/sys/gnu/dts/arm64/broadcom/stingray/stingray-usb.dtsi +++ /dev/null @@ -1,72 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 or BSD-3-Clause) -/* - *Copyright(c) 2018 Broadcom - */ - usb { - compatible = "simple-bus"; - dma-ranges; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x68500000 0x00400000>; - - usbphy0: usb-phy@0 { - compatible = "brcm,sr-usb-combo-phy"; - reg = <0x00000000 0x100>; - #phy-cells = <1>; - status = "disabled"; - }; - - xhci0: usb@1000 { - compatible = "generic-xhci"; - reg = <0x00001000 0x1000>; - interrupts = ; - phys = <&usbphy0 1>, <&usbphy0 0>; - phy-names = "phy0", "phy1"; - dma-coherent; - status = "disabled"; - }; - - bdc0: usb@2000 { - compatible = "brcm,bdc-v0.16"; - reg = <0x00002000 0x1000>; - interrupts = ; - phys = <&usbphy0 0>, <&usbphy0 1>; - phy-names = "phy0", "phy1"; - dma-coherent; - status = "disabled"; - }; - - usbphy1: usb-phy@10000 { - compatible = "brcm,sr-usb-combo-phy"; - reg = <0x00010000 0x100>; - #phy-cells = <1>; - status = "disabled"; - }; - - usbphy2: usb-phy@20000 { - compatible = "brcm,sr-usb-hs-phy"; - reg = <0x00020000 0x100>; - #phy-cells = <0>; - status = "disabled"; - }; - - xhci1: usb@11000 { - compatible = "generic-xhci"; - reg = <0x00011000 0x1000>; - interrupts = ; - phys = <&usbphy1 1>, <&usbphy2>, <&usbphy1 0>; - phy-names = "phy0", "phy1", "phy2"; - dma-coherent; - status = "disabled"; - }; - - bdc1: usb@21000 { - compatible = "brcm,bdc-v0.16"; - reg = <0x00021000 0x1000>; - interrupts = ; - phys = <&usbphy2>; - phy-names = "phy0"; - dma-coherent; - status = "disabled"; - }; - }; diff --git a/sys/gnu/dts/arm64/broadcom/stingray/stingray.dtsi b/sys/gnu/dts/arm64/broadcom/stingray/stingray.dtsi deleted file mode 100644 index 0098dfdef96..00000000000 --- a/sys/gnu/dts/arm64/broadcom/stingray/stingray.dtsi +++ /dev/null @@ -1,722 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright(c) 2015-2017 Broadcom. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include - -/ { - compatible = "brcm,stingray"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x0 0x0>; - enable-method = "psci"; - next-level-cache = <&CLUSTER0_L2>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x0 0x1>; - enable-method = "psci"; - next-level-cache = <&CLUSTER0_L2>; - }; - - cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x0 0x100>; - enable-method = "psci"; - next-level-cache = <&CLUSTER1_L2>; - }; - - cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x0 0x101>; - enable-method = "psci"; - next-level-cache = <&CLUSTER1_L2>; - }; - - cpu@200 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x0 0x200>; - enable-method = "psci"; - next-level-cache = <&CLUSTER2_L2>; - }; - - cpu@201 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x0 0x201>; - enable-method = "psci"; - next-level-cache = <&CLUSTER2_L2>; - }; - - cpu@300 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x0 0x300>; - enable-method = "psci"; - next-level-cache = <&CLUSTER3_L2>; - }; - - cpu@301 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x0 0x301>; - enable-method = "psci"; - next-level-cache = <&CLUSTER3_L2>; - }; - - CLUSTER0_L2: l2-cache@0 { - compatible = "cache"; - }; - - CLUSTER1_L2: l2-cache@100 { - compatible = "cache"; - }; - - CLUSTER2_L2: l2-cache@200 { - compatible = "cache"; - }; - - CLUSTER3_L2: l2-cache@300 { - compatible = "cache"; - }; - }; - - memory: memory@80000000 { - device_type = "memory"; - reg = <0x00000000 0x80000000 0 0x40000000>; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = ; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - mhb: syscon@60401000 { - compatible = "brcm,sr-mhb", "syscon"; - reg = <0 0x60401000 0 0x38c>; - }; - - scr { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x61000000 0x05000000>; - - ccn: ccn@0 { - compatible = "arm,ccn-502"; - reg = <0x00000000 0x900000>; - interrupts = ; - }; - - gic: interrupt-controller@2c00000 { - compatible = "arm,gic-v3"; - #interrupt-cells = <3>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - interrupt-controller; - reg = <0x02c00000 0x010000>, /* GICD */ - <0x02e00000 0x600000>; /* GICR */ - interrupts = ; - - gic_its: gic-its@63c20000 { - compatible = "arm,gic-v3-its"; - msi-controller; - #msi-cells = <1>; - reg = <0x02c20000 0x10000>; - }; - }; - - smmu: mmu@3000000 { - compatible = "arm,mmu-500"; - reg = <0x03000000 0x80000>; - #global-interrupts = <1>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - #iommu-cells = <2>; - }; - }; - - crmu: crmu { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x66400000 0x100000>; - - #include "stingray-clock.dtsi" - - otp: otp@1c400 { - compatible = "brcm,ocotp-v2"; - reg = <0x0001c400 0x68>; - brcm,ocotp-size = <2048>; - status = "okay"; - }; - - cdru: syscon@1d000 { - compatible = "brcm,sr-cdru", "syscon"; - reg = <0x0001d000 0x400>; - }; - - gpio_crmu: gpio@24800 { - compatible = "brcm,iproc-gpio"; - reg = <0x00024800 0x4c>; - ngpios = <6>; - #gpio-cells = <2>; - gpio-controller; - }; - }; - - #include "stingray-fs4.dtsi" - #include "stingray-sata.dtsi" - #include "stingray-pcie.dtsi" - #include "stingray-usb.dtsi" - - hsls { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x68900000 0x17700000>; - - #include "stingray-pinctrl.dtsi" - - mdio_mux_iproc: mdio-mux@20000 { - compatible = "brcm,mdio-mux-iproc"; - reg = <0x00020000 0x250>; - #address-cells = <1>; - #size-cells = <0>; - - mdio@0 { /* PCIe serdes */ - reg = <0x0>; - #address-cells = <1>; - #size-cells = <0>; - }; - - mdio@2 { /* SATA */ - reg = <0x2>; - #address-cells = <1>; - #size-cells = <0>; - }; - - mdio@3 { /* USB */ - reg = <0x3>; - #address-cells = <1>; - #size-cells = <0>; - }; - - mdio@10 { /* RGMII */ - reg = <0x10>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - pwm: pwm@10000 { - compatible = "brcm,iproc-pwm"; - reg = <0x00010000 0x1000>; - clocks = <&crmu_ref25m>; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer0: timer@30000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x00030000 0x1000>; - interrupts = ; - clocks = <&hsls_25m_div2_clk>, - <&hsls_25m_div2_clk>, - <&hsls_div4_clk>; - clock-names = "timer1", "timer2", "apb_pclk"; - status = "disabled"; - }; - - timer1: timer@40000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x00040000 0x1000>; - interrupts = ; - clocks = <&hsls_25m_div2_clk>, - <&hsls_25m_div2_clk>, - <&hsls_div4_clk>; - clock-names = "timer1", "timer2", "apb_pclk"; - }; - - timer2: timer@50000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x00050000 0x1000>; - interrupts = ; - clocks = <&hsls_25m_div2_clk>, - <&hsls_25m_div2_clk>, - <&hsls_div4_clk>; - clock-names = "timer1", "timer2", "apb_pclk"; - status = "disabled"; - }; - - timer3: timer@60000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x00060000 0x1000>; - interrupts = ; - clocks = <&hsls_25m_div2_clk>, - <&hsls_25m_div2_clk>, - <&hsls_div4_clk>; - clock-names = "timer1", "timer2", "apb_pclk"; - status = "disabled"; - }; - - timer4: timer@70000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x00070000 0x1000>; - interrupts = ; - clocks = <&hsls_25m_div2_clk>, - <&hsls_25m_div2_clk>, - <&hsls_div4_clk>; - clock-names = "timer1", "timer2", "apb_pclk"; - status = "disabled"; - }; - - timer5: timer@80000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x00080000 0x1000>; - interrupts = ; - clocks = <&hsls_25m_div2_clk>, - <&hsls_25m_div2_clk>, - <&hsls_div4_clk>; - clock-names = "timer1", "timer2", "apb_pclk"; - status = "disabled"; - }; - - timer6: timer@90000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x00090000 0x1000>; - interrupts = ; - clocks = <&hsls_25m_div2_clk>, - <&hsls_25m_div2_clk>, - <&hsls_div4_clk>; - clock-names = "timer1", "timer2", "apb_pclk"; - status = "disabled"; - }; - - timer7: timer@a0000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x000a0000 0x1000>; - interrupts = ; - clocks = <&hsls_25m_div2_clk>, - <&hsls_25m_div2_clk>, - <&hsls_div4_clk>; - clock-names = "timer1", "timer2", "apb_pclk"; - status = "disabled"; - }; - - i2c0: i2c@b0000 { - compatible = "brcm,iproc-i2c"; - reg = <0x000b0000 0x100>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clock-frequency = <100000>; - status = "disabled"; - }; - - wdt0: watchdog@c0000 { - compatible = "arm,sp805", "arm,primecell"; - reg = <0x000c0000 0x1000>; - interrupts = ; - clocks = <&hsls_25m_div2_clk>, <&hsls_div4_clk>; - clock-names = "wdogclk", "apb_pclk"; - timeout-sec = <60>; - }; - - gpio_hsls: gpio@d0000 { - compatible = "brcm,iproc-gpio"; - reg = <0x000d0000 0x864>; - ngpios = <151>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - interrupts = ; - gpio-ranges = <&pinmux 0 0 16>, - <&pinmux 16 71 2>, - <&pinmux 18 131 8>, - <&pinmux 26 83 6>, - <&pinmux 32 123 4>, - <&pinmux 36 43 24>, - <&pinmux 60 89 2>, - <&pinmux 62 73 4>, - <&pinmux 66 95 28>, - <&pinmux 94 127 4>, - <&pinmux 98 139 10>, - <&pinmux 108 16 27>, - <&pinmux 135 77 6>, - <&pinmux 141 67 4>, - <&pinmux 145 149 6>; - }; - - i2c1: i2c@e0000 { - compatible = "brcm,iproc-i2c"; - reg = <0x000e0000 0x100>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clock-frequency = <100000>; - status = "disabled"; - }; - - uart0: uart@100000 { - device_type = "serial"; - compatible = "snps,dw-apb-uart"; - reg = <0x00100000 0x1000>; - reg-shift = <2>; - clock-frequency = <25000000>; - interrupt-parent = <&gic>; - interrupts = ; - status = "disabled"; - }; - - uart1: uart@110000 { - device_type = "serial"; - compatible = "snps,dw-apb-uart"; - reg = <0x00110000 0x1000>; - reg-shift = <2>; - clock-frequency = <25000000>; - interrupt-parent = <&gic>; - interrupts = ; - status = "disabled"; - }; - - uart2: uart@120000 { - device_type = "serial"; - compatible = "snps,dw-apb-uart"; - reg = <0x00120000 0x1000>; - reg-shift = <2>; - clock-frequency = <25000000>; - interrupt-parent = <&gic>; - interrupts = ; - status = "disabled"; - }; - - uart3: uart@130000 { - device_type = "serial"; - compatible = "snps,dw-apb-uart"; - reg = <0x00130000 0x1000>; - reg-shift = <2>; - clock-frequency = <25000000>; - interrupt-parent = <&gic>; - interrupts = ; - status = "disabled"; - }; - - ssp0: spi@180000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x00180000 0x1000>; - interrupts = ; - clocks = <&hsls_div2_clk>, <&hsls_div2_clk>; - clock-names = "spiclk", "apb_pclk"; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - ssp1: spi@190000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x00190000 0x1000>; - interrupts = ; - clocks = <&hsls_div2_clk>, <&hsls_div2_clk>; - clock-names = "spiclk", "apb_pclk"; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - hwrng: hwrng@220000 { - compatible = "brcm,iproc-rng200"; - reg = <0x00220000 0x28>; - }; - - dma0: dma@310000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x00310000 0x1000>; - interrupts = , - , - , - , - , - , - , - , - ; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; - clocks = <&hsls_div2_clk>; - clock-names = "apb_pclk"; - iommus = <&smmu 0x6000 0x0000>; - }; - - enet: ethernet@340000{ - compatible = "brcm,amac"; - reg = <0x00340000 0x1000>; - reg-names = "amac_base"; - dma-coherent; - interrupts = ; - status= "disabled"; - }; - - nand: nand@360000 { - compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1"; - reg = <0x00360000 0x600>, - <0x0050a408 0x600>, - <0x00360f00 0x20>; - reg-names = "nand", "iproc-idm", "iproc-ext"; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - brcm,nand-has-wp; - status = "disabled"; - }; - - sdio0: sdhci@3f1000 { - compatible = "brcm,sdhci-iproc"; - reg = <0x003f1000 0x100>; - interrupts = ; - bus-width = <8>; - clocks = <&sdio0_clk>; - iommus = <&smmu 0x6002 0x0000>; - status = "disabled"; - }; - - sdio1: sdhci@3f2000 { - compatible = "brcm,sdhci-iproc"; - reg = <0x003f2000 0x100>; - interrupts = ; - bus-width = <8>; - clocks = <&sdio1_clk>; - iommus = <&smmu 0x6003 0x0000>; - status = "disabled"; - }; - }; - - tmons { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x8f100000 0x100>; - - tmon: tmon@0 { - compatible = "brcm,sr-thermal"; - reg = <0x0 0x40>; - brcm,tmon-mask = <0x3f>; - #thermal-sensor-cells = <1>; - }; - }; - - thermal-zones { - ihost0_thermal: ihost0-thermal { - polling-delay-passive = <0>; - polling-delay = <1000>; - thermal-sensors = <&tmon 0>; - trips { - cpu-crit { - temperature = <105000>; - hysteresis = <0>; - type = "critical"; - }; - }; - }; - ihost1_thermal: ihost1-thermal { - polling-delay-passive = <0>; - polling-delay = <1000>; - thermal-sensors = <&tmon 1>; - trips { - cpu-crit { - temperature = <105000>; - hysteresis = <0>; - type = "critical"; - }; - }; - }; - ihost2_thermal: ihost2-thermal { - polling-delay-passive = <0>; - polling-delay = <1000>; - thermal-sensors = <&tmon 2>; - trips { - cpu-crit { - temperature = <105000>; - hysteresis = <0>; - type = "critical"; - }; - }; - }; - ihost3_thermal: ihost3-thermal { - polling-delay-passive = <0>; - polling-delay = <1000>; - thermal-sensors = <&tmon 3>; - trips { - cpu-crit { - temperature = <105000>; - hysteresis = <0>; - type = "critical"; - }; - }; - }; - crmu_thermal: crmu-thermal { - polling-delay-passive = <0>; - polling-delay = <1000>; - thermal-sensors = <&tmon 4>; - trips { - cpu-crit { - temperature = <105000>; - hysteresis = <0>; - type = "critical"; - }; - }; - }; - nitro_thermal: nitro-thermal { - polling-delay-passive = <0>; - polling-delay = <1000>; - thermal-sensors = <&tmon 5>; - trips { - cpu-crit { - temperature = <105000>; - hysteresis = <0>; - type = "critical"; - }; - }; - }; - }; - - nic-hsls { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x0 0x7fffffff>; - - nic_i2c0: i2c@60826100 { - compatible = "brcm,iproc-nic-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x60826100 0x100>, - <0x60e00408 0x1000>; - brcm,ape-hsls-addr-mask = <0x03400000>; - clock-frequency = <100000>; - status = "disabled"; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/cavium/thunder-88xx.dts b/sys/gnu/dts/arm64/cavium/thunder-88xx.dts deleted file mode 100644 index 5ec2bfa5f71..00000000000 --- a/sys/gnu/dts/arm64/cavium/thunder-88xx.dts +++ /dev/null @@ -1,67 +0,0 @@ -/* - * Cavium Thunder DTS file - Thunder board description - * - * Copyright (C) 2014, Cavium Inc. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this library; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -/include/ "thunder-88xx.dtsi" - -/ { - model = "Cavium ThunderX CN88XX board"; - compatible = "cavium,thunder-88xx"; - - aliases { - serial0 = &uaa0; - serial1 = &uaa1; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x00000000 0x0 0x80000000>; - }; -}; diff --git a/sys/gnu/dts/arm64/cavium/thunder-88xx.dtsi b/sys/gnu/dts/arm64/cavium/thunder-88xx.dtsi deleted file mode 100644 index e0a71795261..00000000000 --- a/sys/gnu/dts/arm64/cavium/thunder-88xx.dtsi +++ /dev/null @@ -1,415 +0,0 @@ -/* - * Cavium Thunder DTS file - Thunder SoC description - * - * Copyright (C) 2014, Cavium Inc. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this library; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/ { - compatible = "cavium,thunder-88xx"; - interrupt-parent = <&gic0>; - #address-cells = <2>; - #size-cells = <2>; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "cavium,thunder"; - reg = <0x0 0x000>; - enable-method = "psci"; - }; - cpu@1 { - device_type = "cpu"; - compatible = "cavium,thunder"; - reg = <0x0 0x001>; - enable-method = "psci"; - }; - cpu@2 { - device_type = "cpu"; - compatible = "cavium,thunder"; - reg = <0x0 0x002>; - enable-method = "psci"; - }; - cpu@3 { - device_type = "cpu"; - compatible = "cavium,thunder"; - reg = <0x0 0x003>; - enable-method = "psci"; - }; - cpu@4 { - device_type = "cpu"; - compatible = "cavium,thunder"; - reg = <0x0 0x004>; - enable-method = "psci"; - }; - cpu@5 { - device_type = "cpu"; - compatible = "cavium,thunder"; - reg = <0x0 0x005>; - enable-method = "psci"; - }; - cpu@6 { - device_type = "cpu"; - compatible = "cavium,thunder"; - reg = <0x0 0x006>; - enable-method = "psci"; - }; - cpu@7 { - device_type = "cpu"; - compatible = "cavium,thunder"; - reg = <0x0 0x007>; - enable-method = "psci"; - }; - cpu@8 { - device_type = "cpu"; - compatible = "cavium,thunder"; - reg = <0x0 0x008>; - enable-method = "psci"; - }; - cpu@9 { - device_type = "cpu"; - compatible = "cavium,thunder"; - reg = <0x0 0x009>; - enable-method = "psci"; - }; - cpu@a { - device_type = "cpu"; - compatible = "cavium,thunder"; - reg = <0x0 0x00a>; - enable-method = "psci"; - }; - cpu@b { - device_type = "cpu"; - compatible = "cavium,thunder"; - reg = <0x0 0x00b>; - enable-method = "psci"; - }; - cpu@c { - device_type = "cpu"; - compatible = "cavium,thunder"; - reg = <0x0 0x00c>; - enable-method = "psci"; - }; - cpu@d { - device_type = "cpu"; - compatible = "cavium,thunder"; - reg = <0x0 0x00d>; - enable-method = "psci"; - }; - cpu@e { - device_type = "cpu"; - compatible = "cavium,thunder"; - reg = <0x0 0x00e>; - enable-method = "psci"; - }; - cpu@f { - device_type = "cpu"; - compatible = "cavium,thunder"; - reg = <0x0 0x00f>; - enable-method = "psci"; - }; - cpu@100 { - device_type = "cpu"; - compatible = "cavium,thunder"; - reg = <0x0 0x100>; - enable-method = "psci"; - }; - cpu@101 { - device_type = "cpu"; - compatible = "cavium,thunder"; - reg = <0x0 0x101>; - enable-method = "psci"; - }; - cpu@102 { - device_type = "cpu"; - compatible = "cavium,thunder"; - reg = <0x0 0x102>; - enable-method = "psci"; - }; - cpu@103 { - device_type = "cpu"; - compatible = "cavium,thunder"; - reg = <0x0 0x103>; - enable-method = "psci"; - }; - cpu@104 { - device_type = "cpu"; - compatible = "cavium,thunder"; - reg = <0x0 0x104>; - enable-method = "psci"; - }; - cpu@105 { - device_type = "cpu"; - compatible = "cavium,thunder"; - reg = <0x0 0x105>; - enable-method = "psci"; - }; - cpu@106 { - device_type = "cpu"; - compatible = "cavium,thunder"; - reg = <0x0 0x106>; - enable-method = "psci"; - }; - cpu@107 { - device_type = "cpu"; - compatible = "cavium,thunder"; - reg = <0x0 0x107>; - enable-method = "psci"; - }; - cpu@108 { - device_type = "cpu"; - compatible = "cavium,thunder"; - reg = <0x0 0x108>; - enable-method = "psci"; - }; - cpu@109 { - device_type = "cpu"; - compatible = "cavium,thunder"; - reg = <0x0 0x109>; - enable-method = "psci"; - }; - cpu@10a { - device_type = "cpu"; - compatible = "cavium,thunder"; - reg = <0x0 0x10a>; - enable-method = "psci"; - }; - cpu@10b { - device_type = "cpu"; - compatible = "cavium,thunder"; - reg = <0x0 0x10b>; - enable-method = "psci"; - }; - cpu@10c { - device_type = "cpu"; - compatible = "cavium,thunder"; - reg = <0x0 0x10c>; - enable-method = "psci"; - }; - cpu@10d { - device_type = "cpu"; - compatible = "cavium,thunder"; - reg = <0x0 0x10d>; - enable-method = "psci"; - }; - cpu@10e { - device_type = "cpu"; - compatible = "cavium,thunder"; - reg = <0x0 0x10e>; - enable-method = "psci"; - }; - cpu@10f { - device_type = "cpu"; - compatible = "cavium,thunder"; - reg = <0x0 0x10f>; - enable-method = "psci"; - }; - cpu@200 { - device_type = "cpu"; - compatible = "cavium,thunder"; - reg = <0x0 0x200>; - enable-method = "psci"; - }; - cpu@201 { - device_type = "cpu"; - compatible = "cavium,thunder"; - reg = <0x0 0x201>; - enable-method = "psci"; - }; - cpu@202 { - device_type = "cpu"; - compatible = "cavium,thunder"; - reg = <0x0 0x202>; - enable-method = "psci"; - }; - cpu@203 { - device_type = "cpu"; - compatible = "cavium,thunder"; - reg = <0x0 0x203>; - enable-method = "psci"; - }; - cpu@204 { - device_type = "cpu"; - compatible = "cavium,thunder"; - reg = <0x0 0x204>; - enable-method = "psci"; - }; - cpu@205 { - device_type = "cpu"; - compatible = "cavium,thunder"; - reg = <0x0 0x205>; - enable-method = "psci"; - }; - cpu@206 { - device_type = "cpu"; - compatible = "cavium,thunder"; - reg = <0x0 0x206>; - enable-method = "psci"; - }; - cpu@207 { - device_type = "cpu"; - compatible = "cavium,thunder"; - reg = <0x0 0x207>; - enable-method = "psci"; - }; - cpu@208 { - device_type = "cpu"; - compatible = "cavium,thunder"; - reg = <0x0 0x208>; - enable-method = "psci"; - }; - cpu@209 { - device_type = "cpu"; - compatible = "cavium,thunder"; - reg = <0x0 0x209>; - enable-method = "psci"; - }; - cpu@20a { - device_type = "cpu"; - compatible = "cavium,thunder"; - reg = <0x0 0x20a>; - enable-method = "psci"; - }; - cpu@20b { - device_type = "cpu"; - compatible = "cavium,thunder"; - reg = <0x0 0x20b>; - enable-method = "psci"; - }; - cpu@20c { - device_type = "cpu"; - compatible = "cavium,thunder"; - reg = <0x0 0x20c>; - enable-method = "psci"; - }; - cpu@20d { - device_type = "cpu"; - compatible = "cavium,thunder"; - reg = <0x0 0x20d>; - enable-method = "psci"; - }; - cpu@20e { - device_type = "cpu"; - compatible = "cavium,thunder"; - reg = <0x0 0x20e>; - enable-method = "psci"; - }; - cpu@20f { - device_type = "cpu"; - compatible = "cavium,thunder"; - reg = <0x0 0x20f>; - enable-method = "psci"; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = <1 13 4>, - <1 14 4>, - <1 11 4>, - <1 10 4>; - }; - - pmu { - compatible = "cavium,thunder-pmu", "arm,armv8-pmuv3"; - interrupts = <1 7 4>; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - refclk50mhz: refclk50mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <50000000>; - clock-output-names = "refclk50mhz"; - }; - - gic0: interrupt-controller@8010,00000000 { - compatible = "arm,gic-v3"; - #interrupt-cells = <3>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - interrupt-controller; - reg = <0x8010 0x00000000 0x0 0x010000>, /* GICD */ - <0x8010 0x80000000 0x0 0x600000>; /* GICR */ - interrupts = <1 9 0xf04>; - - its: gic-its@8010,00020000 { - compatible = "arm,gic-v3-its"; - msi-controller; - reg = <0x8010 0x20000 0x0 0x200000>; - }; - }; - - uaa0: serial@87e0,24000000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x87e0 0x24000000 0x0 0x1000>; - interrupts = <1 21 4>; - clocks = <&refclk50mhz>; - clock-names = "apb_pclk"; - }; - - uaa1: serial@87e0,25000000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x87e0 0x25000000 0x0 0x1000>; - interrupts = <1 22 4>; - clocks = <&refclk50mhz>; - clock-names = "apb_pclk"; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/cavium/thunder2-99xx.dts b/sys/gnu/dts/arm64/cavium/thunder2-99xx.dts deleted file mode 100644 index d005e1e79c3..00000000000 --- a/sys/gnu/dts/arm64/cavium/thunder2-99xx.dts +++ /dev/null @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * dts file for Cavium ThunderX2 CN99XX Evaluation Platform - * - * Copyright (c) 2017 Cavium Inc. - * Copyright (c) 2013-2016 Broadcom - */ - -/dts-v1/; - -#include "thunder2-99xx.dtsi" - -/ { - model = "Cavium ThunderX2 CN99XX"; - compatible = "cavium,thunderx2-cn9900", "brcm,vulcan-soc"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x80000000 0x0 0x80000000>, /* 2G @ 2G */ - <0x00000008 0x80000000 0x0 0x80000000>; /* 2G @ 34G */ - }; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; diff --git a/sys/gnu/dts/arm64/cavium/thunder2-99xx.dtsi b/sys/gnu/dts/arm64/cavium/thunder2-99xx.dtsi deleted file mode 100644 index dfb41705a9a..00000000000 --- a/sys/gnu/dts/arm64/cavium/thunder2-99xx.dtsi +++ /dev/null @@ -1,145 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * dtsi file for Cavium ThunderX2 CN99XX processor - * - * Copyright (c) 2017 Cavium Inc. - * Copyright (c) 2013-2016 Broadcom - * Author: Zi Shen Lim - */ - -#include - -/ { - model = "Cavium ThunderX2 CN99XX"; - compatible = "cavium,thunderx2-cn9900", "brcm,vulcan-soc"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - /* just 4 cpus now, 128 needed in full config */ - cpus { - #address-cells = <0x2>; - #size-cells = <0x0>; - - cpu@0 { - device_type = "cpu"; - compatible = "cavium,thunder2", "brcm,vulcan"; - reg = <0x0 0x0>; - enable-method = "psci"; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "cavium,thunder2", "brcm,vulcan"; - reg = <0x0 0x1>; - enable-method = "psci"; - }; - - cpu@2 { - device_type = "cpu"; - compatible = "cavium,thunder2", "brcm,vulcan"; - reg = <0x0 0x2>; - enable-method = "psci"; - }; - - cpu@3 { - device_type = "cpu"; - compatible = "cavium,thunder2", "brcm,vulcan"; - reg = <0x0 0x3>; - enable-method = "psci"; - }; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - gic: interrupt-controller@400080000 { - compatible = "arm,gic-v3"; - #interrupt-cells = <3>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - interrupt-controller; - #redistributor-regions = <1>; - reg = <0x04 0x00080000 0x0 0x20000>, /* GICD */ - <0x04 0x01000000 0x0 0x1000000>; /* GICR */ - interrupts = ; - - gicits: gic-its@40010000 { - compatible = "arm,gic-v3-its"; - msi-controller; - reg = <0x04 0x00100000 0x0 0x20000>; /* GIC ITS */ - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - pmu { - compatible = "brcm,vulcan-pmu", "arm,armv8-pmuv3"; - interrupts = ; /* PMU overflow */ - }; - - clk125mhz: uart_clk125mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <125000000>; - clock-output-names = "clk125mhz"; - }; - - pcie@30000000 { - compatible = "pci-host-ecam-generic"; - device_type = "pci"; - #interrupt-cells = <1>; - #address-cells = <3>; - #size-cells = <2>; - - /* ECAM at 0x3000_0000 - 0x4000_0000 */ - reg = <0x0 0x30000000 0x0 0x10000000>; - reg-names = "PCI ECAM"; - - /* - * PCI ranges: - * IO no supported - * MEM 0x4000_0000 - 0x6000_0000 - * MEM64 pref 0x40_0000_0000 - 0x60_0000_0000 - */ - ranges = - <0x02000000 0 0x40000000 0 0x40000000 0 0x20000000 - 0x43000000 0x40 0x00000000 0x40 0x00000000 0x20 0x00000000>; - bus-range = <0 0xff>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = - /* addr pin ic icaddr icintr */ - <0 0 0 1 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH - 0 0 0 2 &gic 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH - 0 0 0 3 &gic 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH - 0 0 0 4 &gic 0 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; - msi-parent = <&gicits>; - dma-coherent; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - uart0: serial@402020000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x04 0x02020000 0x0 0x1000>; - interrupt-parent = <&gic>; - interrupts = ; - clocks = <&clk125mhz>; - clock-names = "apb_pclk"; - }; - }; - -}; diff --git a/sys/gnu/dts/arm64/exynos/exynos5433-bus.dtsi b/sys/gnu/dts/arm64/exynos/exynos5433-bus.dtsi deleted file mode 100644 index d77b88af958..00000000000 --- a/sys/gnu/dts/arm64/exynos/exynos5433-bus.dtsi +++ /dev/null @@ -1,194 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's Exynos5433 SoC Memory interface and AMBA bus device tree source - * - * Copyright (c) 2016 Samsung Electronics Co., Ltd. - * Chanwoo Choi - */ - -&soc { - bus_g2d_400: bus0 { - compatible = "samsung,exynos-bus"; - clocks = <&cmu_top CLK_ACLK_G2D_400>; - clock-names = "bus"; - operating-points-v2 = <&bus_g2d_400_opp_table>; - status = "disabled"; - }; - - bus_g2d_266: bus1 { - compatible = "samsung,exynos-bus"; - clocks = <&cmu_top CLK_ACLK_G2D_266>; - clock-names = "bus"; - operating-points-v2 = <&bus_g2d_266_opp_table>; - status = "disabled"; - }; - - bus_gscl: bus2 { - compatible = "samsung,exynos-bus"; - clocks = <&cmu_top CLK_ACLK_GSCL_333>; - clock-names = "bus"; - operating-points-v2 = <&bus_gscl_opp_table>; - status = "disabled"; - }; - - bus_hevc: bus3 { - compatible = "samsung,exynos-bus"; - clocks = <&cmu_top CLK_ACLK_HEVC_400>; - clock-names = "bus"; - operating-points-v2 = <&bus_hevc_opp_table>; - status = "disabled"; - }; - - bus_jpeg: bus4 { - compatible = "samsung,exynos-bus"; - clocks = <&cmu_top CLK_SCLK_JPEG_MSCL>; - clock-names = "bus"; - operating-points-v2 = <&bus_g2d_400_opp_table>; - status = "disabled"; - }; - - bus_mfc: bus5 { - compatible = "samsung,exynos-bus"; - clocks = <&cmu_top CLK_ACLK_MFC_400>; - clock-names = "bus"; - operating-points-v2 = <&bus_g2d_400_opp_table>; - status = "disabled"; - }; - - bus_mscl: bus6 { - compatible = "samsung,exynos-bus"; - clocks = <&cmu_top CLK_ACLK_MSCL_400>; - clock-names = "bus"; - operating-points-v2 = <&bus_g2d_400_opp_table>; - status = "disabled"; - }; - - bus_noc0: bus7 { - compatible = "samsung,exynos-bus"; - clocks = <&cmu_top CLK_ACLK_BUS0_400>; - clock-names = "bus"; - operating-points-v2 = <&bus_hevc_opp_table>; - status = "disabled"; - }; - - bus_noc1: bus8 { - compatible = "samsung,exynos-bus"; - clocks = <&cmu_top CLK_ACLK_BUS1_400>; - clock-names = "bus"; - operating-points-v2 = <&bus_hevc_opp_table>; - status = "disabled"; - }; - - bus_noc2: bus9 { - compatible = "samsung,exynos-bus"; - clocks = <&cmu_mif CLK_ACLK_BUS2_400>; - clock-names = "bus"; - operating-points-v2 = <&bus_noc2_opp_table>; - status = "disabled"; - }; - - bus_g2d_400_opp_table: opp_table2 { - compatible = "operating-points-v2"; - opp-shared; - - opp-400000000 { - opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <1075000>; - }; - opp-267000000 { - opp-hz = /bits/ 64 <267000000>; - opp-microvolt = <1000000>; - }; - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - opp-microvolt = <975000>; - }; - opp-160000000 { - opp-hz = /bits/ 64 <160000000>; - opp-microvolt = <962500>; - }; - opp-134000000 { - opp-hz = /bits/ 64 <134000000>; - opp-microvolt = <950000>; - }; - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - opp-microvolt = <937500>; - }; - }; - - bus_g2d_266_opp_table: opp_table3 { - compatible = "operating-points-v2"; - - opp-267000000 { - opp-hz = /bits/ 64 <267000000>; - }; - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - }; - opp-160000000 { - opp-hz = /bits/ 64 <160000000>; - }; - opp-134000000 { - opp-hz = /bits/ 64 <134000000>; - }; - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - }; - }; - - bus_gscl_opp_table: opp_table4 { - compatible = "operating-points-v2"; - - opp-333000000 { - opp-hz = /bits/ 64 <333000000>; - }; - opp-222000000 { - opp-hz = /bits/ 64 <222000000>; - }; - opp-166500000 { - opp-hz = /bits/ 64 <166500000>; - }; - }; - - bus_hevc_opp_table: opp_table5 { - compatible = "operating-points-v2"; - opp-shared; - - opp-400000000 { - opp-hz = /bits/ 64 <400000000>; - }; - opp-267000000 { - opp-hz = /bits/ 64 <267000000>; - }; - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - }; - opp-160000000 { - opp-hz = /bits/ 64 <160000000>; - }; - opp-134000000 { - opp-hz = /bits/ 64 <134000000>; - }; - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - }; - }; - - bus_noc2_opp_table: opp_table6 { - compatible = "operating-points-v2"; - - opp-400000000 { - opp-hz = /bits/ 64 <400000000>; - }; - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - }; - opp-134000000 { - opp-hz = /bits/ 64 <134000000>; - }; - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/exynos/exynos5433-pinctrl.dtsi b/sys/gnu/dts/arm64/exynos/exynos5433-pinctrl.dtsi deleted file mode 100644 index 9df7c65593a..00000000000 --- a/sys/gnu/dts/arm64/exynos/exynos5433-pinctrl.dtsi +++ /dev/null @@ -1,790 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's Exynos5433 SoC pin-mux and pin-config device tree source - * - * Copyright (c) 2016 Samsung Electronics Co., Ltd. - * Chanwoo Choi - * - * Samsung's Exynos5433 SoC pin-mux and pin-config options are listed as device - * tree nodes are listed in this file. - */ - -#include - -#define PIN(_func, _pin, _pull, _drv) \ - _pin { \ - samsung,pins = #_pin; \ - samsung,pin-function = ; \ - samsung,pin-pud = ; \ - samsung,pin-drv = ; \ - } - -&pinctrl_alive { - gpa0: gpa0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - interrupt-parent = <&gic>; - interrupts = , - , - , - , - , - , - , - ; - #interrupt-cells = <2>; - }; - - gpa1: gpa1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - interrupt-parent = <&gic>; - interrupts = , - , - , - , - , - , - , - ; - #interrupt-cells = <2>; - }; - - gpa2: gpa2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpa3: gpa3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf1: gpf1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf2: gpf2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf3: gpf3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf4: gpf4 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf5: gpf5 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; -}; - -&pinctrl_aud { - gpz0: gpz0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpz1: gpz1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - i2s0_bus: i2s0-bus { - samsung,pins = "gpz0-0", "gpz0-1", "gpz0-2", "gpz0-3", - "gpz0-4", "gpz0-5", "gpz0-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pcm0_bus: pcm0-bus { - samsung,pins = "gpz1-0", "gpz1-1", "gpz1-2", "gpz1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart_aud_bus: uart-aud-bus { - samsung,pins = "gpz1-3", "gpz1-2", "gpz1-1", "gpz1-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pinctrl_cpif { - gpv6: gpv6 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; -}; - -&pinctrl_ese { - gpj2: gpj2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; -}; - -&pinctrl_finger { - gpd5: gpd5 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - spi2_bus: spi2-bus { - samsung,pins = "gpd5-0", "gpd5-2", "gpd5-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - hs_i2c6_bus: hs-i2c6-bus { - samsung,pins = "gpd5-3", "gpd5-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pinctrl_fsys { - gph1: gph1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpr4: gpr4 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpr0: gpr0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpr1: gpr1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpr2: gpr2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpr3: gpr3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - sd0_clk: sd0-clk { - samsung,pins = "gpr0-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_cmd: sd0-cmd { - samsung,pins = "gpr0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_rdqs: sd0-rdqs { - samsung,pins = "gpr0-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_qrdy: sd0-qrdy { - samsung,pins = "gpr0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus1: sd0-bus-width1 { - samsung,pins = "gpr1-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus4: sd0-bus-width4 { - samsung,pins = "gpr1-1", "gpr1-2", "gpr1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus8: sd0-bus-width8 { - samsung,pins = "gpr1-4", "gpr1-5", "gpr1-6", "gpr1-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_clk: sd1-clk { - samsung,pins = "gpr2-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_cmd: sd1-cmd { - samsung,pins = "gpr2-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_bus1: sd1-bus-width1 { - samsung,pins = "gpr3-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_bus4: sd1-bus-width4 { - samsung,pins = "gpr3-1", "gpr3-2", "gpr3-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_bus8: sd1-bus-width8 { - samsung,pins = "gpr3-4", "gpr3-5", "gpr3-6", "gpr3-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pcie_bus: pcie_bus { - samsung,pins = "gpr3-4", "gpr3-5", "gpr3-6", "gpr3-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - sd2_clk: sd2-clk { - samsung,pins = "gpr4-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_cmd: sd2-cmd { - samsung,pins = "gpr4-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_cd: sd2-cd { - samsung,pins = "gpr4-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_bus1: sd2-bus-width1 { - samsung,pins = "gpr4-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_bus4: sd2-bus-width4 { - samsung,pins = "gpr4-4", "gpr4-5", "gpr4-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_clk_output: sd2-clk-output { - samsung,pins = "gpr4-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_cmd_output: sd2-cmd-output { - samsung,pins = "gpr4-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pinctrl_imem { - gpf0: gpf0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; -}; - -&pinctrl_nfc { - gpj0: gpj0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - hs_i2c4_bus: hs-i2c4-bus { - samsung,pins = "gpj0-1", "gpj0-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pinctrl_peric { - gpv7: gpv7 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpb0: gpb0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc0: gpc0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc1: gpc1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc2: gpc2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc3: gpc3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpg0: gpg0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpd0: gpd0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpd1: gpd1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpd2: gpd2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpd4: gpd4 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpd8: gpd8 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpd6: gpd6 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpd7: gpd7 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpg1: gpg1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpg2: gpg2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpg3: gpg3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - hs_i2c8_bus: hs-i2c8-bus { - samsung,pins = "gpb0-1", "gpb0-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - hs_i2c9_bus: hs-i2c9-bus { - samsung,pins = "gpb0-3", "gpb0-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2s1_bus: i2s1-bus { - samsung,pins = "gpd4-0", "gpd4-1", "gpd4-2", - "gpd4-3", "gpd4-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pcm1_bus: pcm1-bus { - samsung,pins = "gpd4-0", "gpd4-1", "gpd4-2", - "gpd4-3", "gpd4-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spdif_bus: spdif-bus { - samsung,pins = "gpd4-3", "gpd4-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - fimc_is_spi_pin0: fimc-is-spi-pin0 { - samsung,pins = "gpc3-3", "gpc3-2", "gpc3-1", "gpc3-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - fimc_is_spi_pin1: fimc-is-spi-pin1 { - samsung,pins = "gpc3-7", "gpc3-6", "gpc3-5", "gpc3-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart0_bus: uart0-bus { - samsung,pins = "gpd0-3", "gpd0-2", "gpd0-1", "gpd0-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - hs_i2c2_bus: hs-i2c2-bus { - samsung,pins = "gpd0-3", "gpd0-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart2_bus: uart2-bus { - samsung,pins = "gpd1-5", "gpd1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - uart1_bus: uart1-bus { - samsung,pins = "gpd1-3", "gpd1-2", "gpd1-1", "gpd1-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - hs_i2c3_bus: hs-i2c3-bus { - samsung,pins = "gpd1-3", "gpd1-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - hs_i2c0_bus: hs-i2c0-bus { - samsung,pins = "gpd2-1", "gpd2-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - hs_i2c1_bus: hs-i2c1-bus { - samsung,pins = "gpd2-3", "gpd2-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm0_out: pwm0-out { - samsung,pins = "gpd2-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm1_out: pwm1-out { - samsung,pins = "gpd2-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm2_out: pwm2-out { - samsung,pins = "gpd2-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm3_out: pwm3-out { - samsung,pins = "gpd2-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spi1_bus: spi1-bus { - samsung,pins = "gpd6-2", "gpd6-4", "gpd6-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - hs_i2c7_bus: hs-i2c7-bus { - samsung,pins = "gpd2-7", "gpd2-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spi0_bus: spi0-bus { - samsung,pins = "gpd8-0", "gpd6-0", "gpd6-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - hs_i2c10_bus: hs-i2c10-bus { - samsung,pins = "gpg3-1", "gpg3-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - hs_i2c11_bus: hs-i2c11-bus { - samsung,pins = "gpg3-3", "gpg3-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spi3_bus: spi3-bus { - samsung,pins = "gpg3-4", "gpg3-6", "gpg3-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spi4_bus: spi4-bus { - samsung,pins = "gpv7-1", "gpv7-3", "gpv7-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - fimc_is_uart: fimc-is-uart { - samsung,pins = "gpc1-1", "gpc0-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - fimc_is_ch0_i2c: fimc-is-ch0_i2c { - samsung,pins = "gpc2-1", "gpc2-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - fimc_is_ch0_mclk: fimc-is-ch0_mclk { - samsung,pins = "gpd7-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - fimc_is_ch1_i2c: fimc-is-ch1-i2c { - samsung,pins = "gpc2-3", "gpc2-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - fimc_is_ch1_mclk: fimc-is-ch1-mclk { - samsung,pins = "gpd7-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - fimc_is_ch2_i2c: fimc-is-ch2-i2c { - samsung,pins = "gpc2-5", "gpc2-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - fimc_is_ch2_mclk: fimc-is-ch2-mclk { - samsung,pins = "gpd7-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pinctrl_touch { - gpj1: gpj1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - hs_i2c5_bus: hs-i2c5-bus { - samsung,pins = "gpj1-1", "gpj1-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; diff --git a/sys/gnu/dts/arm64/exynos/exynos5433-tm2-common.dtsi b/sys/gnu/dts/arm64/exynos/exynos5433-tm2-common.dtsi deleted file mode 100644 index 250fc01de78..00000000000 --- a/sys/gnu/dts/arm64/exynos/exynos5433-tm2-common.dtsi +++ /dev/null @@ -1,1333 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung Exynos5433 TM2 board device tree source - * - * Copyright (c) 2016 Samsung Electronics Co., Ltd. - * - * Common device tree source file for Samsung's TM2 and TM2E boards - * which are based on Samsung Exynos5433 SoC. - */ - -/dts-v1/; -#include "exynos5433.dtsi" -#include -#include -#include -#include -#include - -/ { - aliases { - gsc0 = &gsc_0; - gsc1 = &gsc_1; - gsc2 = &gsc_2; - pinctrl0 = &pinctrl_alive; - pinctrl1 = &pinctrl_aud; - pinctrl2 = &pinctrl_cpif; - pinctrl3 = &pinctrl_ese; - pinctrl4 = &pinctrl_finger; - pinctrl5 = &pinctrl_fsys; - pinctrl6 = &pinctrl_imem; - pinctrl7 = &pinctrl_nfc; - pinctrl8 = &pinctrl_peric; - pinctrl9 = &pinctrl_touch; - serial0 = &serial_0; - serial1 = &serial_1; - serial2 = &serial_2; - serial3 = &serial_3; - spi0 = &spi_0; - spi1 = &spi_1; - spi2 = &spi_2; - spi3 = &spi_3; - spi4 = &spi_4; - mshc0 = &mshc_0; - mshc2 = &mshc_2; - }; - - chosen { - stdout-path = &serial_1; - }; - - memory@20000000 { - device_type = "memory"; - reg = <0x0 0x20000000 0x0 0xc0000000>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - power-key { - gpios = <&gpa2 7 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "power key"; - debounce-interval = <10>; - }; - - volume-up-key { - gpios = <&gpa2 0 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "volume-up key"; - debounce-interval = <10>; - }; - - volume-down-key { - gpios = <&gpa2 1 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "volume-down key"; - debounce-interval = <10>; - }; - - homepage-key { - gpios = <&gpa0 3 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "homepage key"; - debounce-interval = <10>; - }; - }; - - i2c_max98504: i2c-gpio-0 { - compatible = "i2c-gpio"; - gpios = <&gpd0 1 GPIO_ACTIVE_HIGH /* SPK_AMP_SDA */ - &gpd0 0 GPIO_ACTIVE_HIGH /* SPK_AMP_SCL */ >; - i2c-gpio,delay-us = <2>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - max98504: max98504@31 { - compatible = "maxim,max98504"; - reg = <0x31>; - maxim,rx-path = <1>; - maxim,tx-path = <1>; - maxim,tx-channel-mask = <3>; - maxim,tx-channel-source = <2>; - }; - }; - - irda_regulator: irda-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpr3 3 GPIO_ACTIVE_HIGH>; - regulator-name = "irda_regulator"; - }; - - sound { - compatible = "samsung,tm2-audio"; - audio-codec = <&wm5110>, <&hdmi>; - i2s-controller = <&i2s0 0>, <&i2s1 0>; - audio-amplifier = <&max98504>; - mic-bias-gpios = <&gpr3 2 GPIO_ACTIVE_HIGH>; - model = "wm5110"; - samsung,audio-routing = - /* Headphone */ - "HP", "HPOUT1L", - "HP", "HPOUT1R", - - /* Speaker */ - "SPK", "SPKOUT", - "SPKOUT", "HPOUT2L", - "SPKOUT", "HPOUT2R", - - /* Receiver */ - "RCV", "HPOUT3L", - "RCV", "HPOUT3R"; - status = "okay"; - }; -}; - -&adc { - vdd-supply = <&ldo3_reg>; - status = "okay"; - - thermistor-ap { - compatible = "murata,ncp03wf104"; - pullup-uv = <1800000>; - pullup-ohm = <100000>; - pulldown-ohm = <0>; - io-channels = <&adc 0>; - }; - - thermistor-battery { - compatible = "murata,ncp03wf104"; - pullup-uv = <1800000>; - pullup-ohm = <100000>; - pulldown-ohm = <0>; - io-channels = <&adc 1>; - #thermal-sensor-cells = <0>; - }; - - thermistor-charger { - compatible = "murata,ncp03wf104"; - pullup-uv = <1800000>; - pullup-ohm = <100000>; - pulldown-ohm = <0>; - io-channels = <&adc 2>; - }; -}; - -&bus_g2d_400 { - devfreq-events = <&ppmu_event0_d0_general>, <&ppmu_event0_d1_general>; - vdd-supply = <&buck4_reg>; - exynos,saturation-ratio = <10>; - status = "okay"; -}; - -&bus_g2d_266 { - devfreq = <&bus_g2d_400>; - status = "okay"; -}; - -&bus_gscl { - devfreq = <&bus_g2d_400>; - status = "okay"; -}; - -&bus_hevc { - devfreq = <&bus_g2d_400>; - status = "okay"; -}; - -&bus_jpeg { - devfreq = <&bus_g2d_400>; - status = "okay"; -}; - -&bus_mfc { - devfreq = <&bus_g2d_400>; - status = "okay"; -}; - -&bus_mscl { - devfreq = <&bus_g2d_400>; - status = "okay"; -}; - -&bus_noc0 { - devfreq = <&bus_g2d_400>; - status = "okay"; -}; - -&bus_noc1 { - devfreq = <&bus_g2d_400>; - status = "okay"; -}; - -&bus_noc2 { - devfreq = <&bus_g2d_400>; - status = "okay"; -}; - -&cmu_aud { - assigned-clocks = <&cmu_aud CLK_MOUT_AUD_PLL_USER>, - <&cmu_aud CLK_MOUT_SCLK_AUD_I2S>, - <&cmu_aud CLK_MOUT_SCLK_AUD_PCM>, - <&cmu_top CLK_MOUT_AUD_PLL>, - <&cmu_top CLK_MOUT_AUD_PLL_USER_T>, - <&cmu_top CLK_MOUT_SCLK_AUDIO0>, - <&cmu_top CLK_MOUT_SCLK_AUDIO1>, - <&cmu_top CLK_MOUT_SCLK_SPDIF>, - - <&cmu_aud CLK_DIV_AUD_CA5>, - <&cmu_aud CLK_DIV_ACLK_AUD>, - <&cmu_aud CLK_DIV_PCLK_DBG_AUD>, - <&cmu_aud CLK_DIV_SCLK_AUD_I2S>, - <&cmu_aud CLK_DIV_SCLK_AUD_PCM>, - <&cmu_aud CLK_DIV_SCLK_AUD_SLIMBUS>, - <&cmu_aud CLK_DIV_SCLK_AUD_UART>, - <&cmu_top CLK_DIV_SCLK_AUDIO0>, - <&cmu_top CLK_DIV_SCLK_AUDIO1>, - <&cmu_top CLK_DIV_SCLK_PCM1>, - <&cmu_top CLK_DIV_SCLK_I2S1>; - - assigned-clock-parents = <&cmu_top CLK_FOUT_AUD_PLL>, - <&cmu_aud CLK_MOUT_AUD_PLL_USER>, - <&cmu_aud CLK_MOUT_AUD_PLL_USER>, - <&cmu_top CLK_FOUT_AUD_PLL>, - <&cmu_top CLK_MOUT_AUD_PLL>, - <&cmu_top CLK_MOUT_AUD_PLL_USER_T>, - <&cmu_top CLK_MOUT_AUD_PLL_USER_T>, - <&cmu_top CLK_SCLK_AUDIO0>; - - assigned-clock-rates = <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>, - <196608001>, <65536001>, <32768001>, <49152001>, - <2048001>, <24576001>, <196608001>, - <24576001>, <98304001>, <2048001>, <49152001>; -}; - -&cmu_fsys { - assigned-clocks = <&cmu_top CLK_MOUT_SCLK_USBDRD30>, - <&cmu_top CLK_MOUT_SCLK_USBHOST30>, - <&cmu_fsys CLK_MOUT_SCLK_USBDRD30_USER>, - <&cmu_fsys CLK_MOUT_SCLK_USBHOST30_USER>, - <&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER>, - <&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER>, - <&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER>, - <&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER>, - <&cmu_top CLK_DIV_SCLK_USBDRD30>, - <&cmu_top CLK_DIV_SCLK_USBHOST30>; - assigned-clock-parents = <&cmu_top CLK_MOUT_BUS_PLL_USER>, - <&cmu_top CLK_MOUT_BUS_PLL_USER>, - <&cmu_top CLK_SCLK_USBDRD30_FSYS>, - <&cmu_top CLK_SCLK_USBHOST30_FSYS>, - <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY>, - <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY>, - <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY>, - <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY>; - assigned-clock-rates = <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>, - <66700000>, <66700000>; -}; - -&cmu_gscl { - assigned-clocks = <&cmu_gscl CLK_MOUT_ACLK_GSCL_111_USER>, - <&cmu_gscl CLK_MOUT_ACLK_GSCL_333_USER>; - assigned-clock-parents = <&cmu_top CLK_ACLK_GSCL_111>, - <&cmu_top CLK_ACLK_GSCL_333>; -}; - -&cmu_mfc { - assigned-clocks = <&cmu_mfc CLK_MOUT_ACLK_MFC_400_USER>; - assigned-clock-parents = <&cmu_top CLK_ACLK_MFC_400>; -}; - -&cmu_mif { - assigned-clocks = <&cmu_mif CLK_MOUT_SCLK_DSD_A>, <&cmu_mif CLK_DIV_SCLK_DSD>; - assigned-clock-parents = <&cmu_mif CLK_MOUT_MFC_PLL_DIV2>; - assigned-clock-rates = <0>, <333000000>; -}; - -&cmu_mscl { - assigned-clocks = <&cmu_mscl CLK_MOUT_ACLK_MSCL_400_USER>, - <&cmu_mscl CLK_MOUT_SCLK_JPEG_USER>, - <&cmu_mscl CLK_MOUT_SCLK_JPEG>, - <&cmu_top CLK_MOUT_SCLK_JPEG_A>; - assigned-clock-parents = <&cmu_top CLK_ACLK_MSCL_400>, - <&cmu_top CLK_SCLK_JPEG_MSCL>, - <&cmu_mscl CLK_MOUT_SCLK_JPEG_USER>, - <&cmu_top CLK_MOUT_BUS_PLL_USER>; -}; - -&cmu_top { - assigned-clocks = <&cmu_top CLK_FOUT_AUD_PLL>; - assigned-clock-rates = <196608001>; -}; - -&cpu0 { - cpu-supply = <&buck3_reg>; -}; - -&cpu4 { - cpu-supply = <&buck2_reg>; -}; - -&decon { - status = "okay"; -}; - -&decon_tv { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - tv_to_hdmi: endpoint { - remote-endpoint = <&hdmi_to_tv>; - }; - }; - }; -}; - -&dsi { - status = "okay"; - vddcore-supply = <&ldo6_reg>; - vddio-supply = <&ldo7_reg>; - samsung,burst-clock-frequency = <512000000>; - samsung,esc-clock-frequency = <16000000>; - samsung,pll-clock-frequency = <24000000>; - pinctrl-names = "default"; - pinctrl-0 = <&te_irq>; -}; - -&gpu { - mali-supply = <&buck6_reg>; - status = "okay"; -}; - -&hdmi { - hpd-gpios = <&gpa3 0 GPIO_ACTIVE_HIGH>; - status = "okay"; - vdd-supply = <&ldo6_reg>; - vdd_osc-supply = <&ldo7_reg>; - vdd_pll-supply = <&ldo6_reg>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - hdmi_to_tv: endpoint { - remote-endpoint = <&tv_to_hdmi>; - }; - }; - - port@1 { - reg = <1>; - hdmi_to_mhl: endpoint { - remote-endpoint = <&mhl_to_hdmi>; - }; - }; - }; -}; - -&hsi2c_0 { - status = "okay"; - clock-frequency = <2500000>; - - s2mps13-pmic@66 { - compatible = "samsung,s2mps13-pmic"; - interrupt-parent = <&gpa0>; - interrupts = <7 IRQ_TYPE_NONE>; - reg = <0x66>; - samsung,s2mps11-wrstbi-ground; - - s2mps13_osc: clocks { - compatible = "samsung,s2mps13-clk"; - #clock-cells = <1>; - clock-output-names = "s2mps13_ap", "s2mps13_cp", - "s2mps13_bt"; - }; - - regulators { - ldo1_reg: LDO1 { - regulator-name = "VDD_ALIVE_0.9V_AP"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - regulator-always-on; - }; - - ldo2_reg: LDO2 { - regulator-name = "VDDQ_MMC2_2.8V_AP"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo3_reg: LDO3 { - regulator-name = "VDD1_E_1.8V_AP"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo4_reg: LDO4 { - regulator-name = "VDD10_MIF_PLL_1.0V_AP"; - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo5_reg: LDO5 { - regulator-name = "VDD10_DPLL_1.0V_AP"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo6_reg: LDO6 { - regulator-name = "VDD10_MIPI2L_1.0V_AP"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo7_reg: LDO7 { - regulator-name = "VDD18_MIPI2L_1.8V_AP"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo8_reg: LDO8 { - regulator-name = "VDD18_LLI_1.8V_AP"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo9_reg: LDO9 { - regulator-name = "VDD18_ABB_ETC_1.8V_AP"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo10_reg: LDO10 { - regulator-name = "VDD33_USB30_3.0V_AP"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo11_reg: LDO11 { - regulator-name = "VDD_INT_M_1.0V_AP"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo12_reg: LDO12 { - regulator-name = "VDD_KFC_M_1.1V_AP"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - }; - - ldo13_reg: LDO13 { - regulator-name = "VDD_G3D_M_0.95V_AP"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <950000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo14_reg: LDO14 { - regulator-name = "VDDQ_M1_LDO_1.2V_AP"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo15_reg: LDO15 { - regulator-name = "VDDQ_M2_LDO_1.2V_AP"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo16_reg: LDO16 { - regulator-name = "VDDQ_EFUSE"; - regulator-min-microvolt = <1400000>; - regulator-max-microvolt = <3400000>; - regulator-always-on; - }; - - ldo17_reg: LDO17 { - regulator-name = "V_TFLASH_2.8V_AP"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo18_reg: LDO18 { - regulator-name = "V_CODEC_1.8V_AP"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo19_reg: LDO19 { - regulator-name = "VDDA_1.8V_COMP"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo20_reg: LDO20 { - regulator-name = "VCC_2.8V_AP"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - ldo21_reg: LDO21 { - regulator-name = "VT_CAM_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo22_reg: LDO22 { - regulator-name = "CAM_IO_1.8V_AP"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo23_reg: LDO23 { - regulator-name = "CAM_SEN_CORE_1.05V_AP"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - }; - - ldo24_reg: LDO24 { - regulator-name = "VT_CAM_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - ldo25_reg: LDO25 { - regulator-name = "UNUSED_LDO25"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo26_reg: LDO26 { - regulator-name = "CAM_AF_2.8V_AP"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo27_reg: LDO27 { - regulator-name = "VCC_3.0V_LCD_AP"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - ldo28_reg: LDO28 { - regulator-name = "VCC_1.8V_LCD_AP"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo29_reg: LDO29 { - regulator-name = "VT_CAM_2.8V"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - ldo30_reg: LDO30 { - regulator-name = "TSP_AVDD_3.3V_AP"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo31_reg: LDO31 { - /* - * LDO31 differs from target to target, - * its definition is in the .dts - */ - }; - - ldo32_reg: LDO32 { - regulator-name = "VTOUCH_1.8V_AP"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo33_reg: LDO33 { - regulator-name = "VTOUCH_LED_3.3V"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <12500>; - }; - - ldo34_reg: LDO34 { - regulator-name = "VCC_1.8V_MHL_AP"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <2100000>; - }; - - ldo35_reg: LDO35 { - regulator-name = "OIS_VM_2.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo36_reg: LDO36 { - regulator-name = "VSIL_1.0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - }; - - ldo37_reg: LDO37 { - regulator-name = "VF_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo38_reg: LDO38 { - /* - * LDO38 differs from target to target, - * its definition is in the .dts - */ - }; - - ldo39_reg: LDO39 { - regulator-name = "V_HRM_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo40_reg: LDO40 { - regulator-name = "V_HRM_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - buck1_reg: BUCK1 { - regulator-name = "VDD_MIF_0.9V_AP"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck2_reg: BUCK2 { - regulator-name = "VDD_EGL_1.0V_AP"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck3_reg: BUCK3 { - regulator-name = "VDD_KFC_1.0V_AP"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck4_reg: BUCK4 { - regulator-name = "VDD_INT_0.95V_AP"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck5_reg: BUCK5 { - regulator-name = "VDD_DISP_CAM0_0.9V_AP"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck6_reg: BUCK6 { - regulator-name = "VDD_G3D_0.9V_AP"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck7_reg: BUCK7 { - regulator-name = "VDD_MEM1_1.2V_AP"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - buck8_reg: BUCK8 { - regulator-name = "VDD_LLDO_1.35V_AP"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - buck9_reg: BUCK9 { - regulator-name = "VDD_MLDO_2.0V_AP"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - buck10_reg: BUCK10 { - regulator-name = "vdd_mem2"; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - }; - }; - }; -}; - -&hsi2c_4 { - status = "okay"; - - s3fwrn5: nfc@27 { - compatible = "samsung,s3fwrn5-i2c"; - reg = <0x27>; - interrupt-parent = <&gpa1>; - interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; - s3fwrn5,en-gpios = <&gpf1 4 GPIO_ACTIVE_HIGH>; - s3fwrn5,fw-gpios = <&gpj0 2 GPIO_ACTIVE_HIGH>; - }; -}; - -&hsi2c_5 { - status = "okay"; - - stmfts: touchscreen@49 { - compatible = "st,stmfts"; - reg = <0x49>; - interrupt-parent = <&gpa1>; - interrupts = <1 IRQ_TYPE_LEVEL_LOW>; - avdd-supply = <&ldo30_reg>; - vdd-supply = <&ldo31_reg>; - }; -}; - -&hsi2c_7 { - status = "okay"; - clock-frequency = <1000000>; - - sii8620@39 { - reg = <0x39>; - compatible = "sil,sii8620"; - cvcc10-supply = <&ldo36_reg>; - iovcc18-supply = <&ldo34_reg>; - interrupt-parent = <&gpf0>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; - reset-gpios = <&gpv7 0 GPIO_ACTIVE_LOW>; - clocks = <&pmu_system_controller 0>; - clock-names = "xtal"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - mhl_to_hdmi: endpoint { - remote-endpoint = <&hdmi_to_mhl>; - }; - }; - - port@1 { - reg = <1>; - mhl_to_musb_con: endpoint { - remote-endpoint = <&musb_con_to_mhl>; - }; - }; - }; - }; -}; - -&hsi2c_8 { - status = "okay"; - - max77843@66 { - compatible = "maxim,max77843"; - interrupt-parent = <&gpa1>; - interrupts = <5 IRQ_TYPE_EDGE_FALLING>; - reg = <0x66>; - - muic: max77843-muic { - compatible = "maxim,max77843-muic"; - - musb_con: musb_connector { - compatible = "samsung,usb-connector-11pin", - "usb-b-connector"; - label = "micro-USB"; - type = "micro"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@3 { - reg = <3>; - musb_con_to_mhl: endpoint { - remote-endpoint = <&mhl_to_musb_con>; - }; - }; - }; - }; - - ports { - port { - muic_to_usb: endpoint { - remote-endpoint = <&usb_to_muic>; - }; - }; - }; - }; - - regulators { - compatible = "maxim,max77843-regulator"; - safeout1_reg: SAFEOUT1 { - regulator-name = "SAFEOUT1"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <4950000>; - }; - - safeout2_reg: SAFEOUT2 { - regulator-name = "SAFEOUT2"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <4950000>; - }; - - charger_reg: CHARGER { - regulator-name = "CHARGER"; - regulator-min-microamp = <100000>; - regulator-max-microamp = <3150000>; - }; - }; - - haptic: max77843-haptic { - compatible = "maxim,max77843-haptic"; - haptic-supply = <&ldo38_reg>; - pwms = <&pwm 0 33670 0>; - pwm-names = "haptic"; - }; - }; -}; - -&hsi2c_11 { - status = "okay"; -}; - -&i2s0 { - status = "okay"; -}; - -&i2s1 { - assigned-clocks = <&i2s1 CLK_I2S_RCLK_SRC>; - assigned-clock-parents = <&cmu_peric CLK_SCLK_I2S1>; - status = "okay"; -}; - -&mshc_0 { - status = "okay"; - mmc-hs200-1_8v; - mmc-hs400-1_8v; - cap-mmc-highspeed; - non-removable; - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <0 4>; - samsung,dw-mshc-ddr-timing = <0 2>; - samsung,dw-mshc-hs400-timing = <0 3>; - samsung,read-strobe-delay = <90>; - fifo-depth = <0x80>; - pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_qrdy &sd0_bus1 &sd0_bus4 - &sd0_bus8 &sd0_rdqs>; - bus-width = <8>; - assigned-clocks = <&cmu_top CLK_SCLK_MMC0_FSYS>; - assigned-clock-rates = <800000000>; -}; - -&mshc_2 { - status = "okay"; - cap-sd-highspeed; - disable-wp; - cd-gpios = <&gpa2 4 GPIO_ACTIVE_LOW>; - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <0 4>; - samsung,dw-mshc-ddr-timing = <0 2>; - fifo-depth = <0x80>; - pinctrl-names = "default"; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus1 &sd2_bus4>; - bus-width = <4>; -}; - -&ppmu_d0_general { - status = "okay"; - events { - ppmu_event0_d0_general: ppmu-event0-d0-general { - event-name = "ppmu-event0-d0-general"; - }; - }; -}; - -&ppmu_d1_general { - status = "okay"; - events { - ppmu_event0_d1_general: ppmu-event0-d1-general { - event-name = "ppmu-event0-d1-general"; - }; - }; -}; - -&pinctrl_alive { - pinctrl-names = "default"; - pinctrl-0 = <&initial_alive>; - - initial_alive: initial-state { - PIN(INPUT, gpa0-0, DOWN, FAST_SR1); - PIN(INPUT, gpa0-1, NONE, FAST_SR1); - PIN(INPUT, gpa0-2, DOWN, FAST_SR1); - PIN(INPUT, gpa0-3, NONE, FAST_SR1); - PIN(INPUT, gpa0-4, NONE, FAST_SR1); - PIN(INPUT, gpa0-5, DOWN, FAST_SR1); - PIN(INPUT, gpa0-6, NONE, FAST_SR1); - PIN(INPUT, gpa0-7, NONE, FAST_SR1); - - PIN(INPUT, gpa1-0, UP, FAST_SR1); - PIN(INPUT, gpa1-1, UP, FAST_SR1); - PIN(INPUT, gpa1-2, NONE, FAST_SR1); - PIN(INPUT, gpa1-3, DOWN, FAST_SR1); - PIN(INPUT, gpa1-4, DOWN, FAST_SR1); - PIN(INPUT, gpa1-5, NONE, FAST_SR1); - PIN(INPUT, gpa1-6, NONE, FAST_SR1); - PIN(INPUT, gpa1-7, NONE, FAST_SR1); - - PIN(INPUT, gpa2-0, NONE, FAST_SR1); - PIN(INPUT, gpa2-1, NONE, FAST_SR1); - PIN(INPUT, gpa2-2, NONE, FAST_SR1); - PIN(INPUT, gpa2-3, DOWN, FAST_SR1); - PIN(INPUT, gpa2-4, NONE, FAST_SR1); - PIN(INPUT, gpa2-5, DOWN, FAST_SR1); - PIN(INPUT, gpa2-6, DOWN, FAST_SR1); - PIN(INPUT, gpa2-7, NONE, FAST_SR1); - - PIN(INPUT, gpa3-0, DOWN, FAST_SR1); - PIN(INPUT, gpa3-1, DOWN, FAST_SR1); - PIN(INPUT, gpa3-2, NONE, FAST_SR1); - PIN(INPUT, gpa3-3, DOWN, FAST_SR1); - PIN(INPUT, gpa3-4, NONE, FAST_SR1); - PIN(INPUT, gpa3-5, DOWN, FAST_SR1); - PIN(INPUT, gpa3-6, DOWN, FAST_SR1); - PIN(INPUT, gpa3-7, DOWN, FAST_SR1); - - PIN(INPUT, gpf1-0, NONE, FAST_SR1); - PIN(INPUT, gpf1-1, NONE, FAST_SR1); - PIN(INPUT, gpf1-2, DOWN, FAST_SR1); - PIN(INPUT, gpf1-4, UP, FAST_SR1); - PIN(OUTPUT, gpf1-5, NONE, FAST_SR1); - PIN(INPUT, gpf1-6, DOWN, FAST_SR1); - PIN(INPUT, gpf1-7, DOWN, FAST_SR1); - - PIN(INPUT, gpf2-0, DOWN, FAST_SR1); - PIN(INPUT, gpf2-1, DOWN, FAST_SR1); - PIN(INPUT, gpf2-2, DOWN, FAST_SR1); - PIN(INPUT, gpf2-3, DOWN, FAST_SR1); - - PIN(INPUT, gpf3-0, DOWN, FAST_SR1); - PIN(INPUT, gpf3-1, DOWN, FAST_SR1); - PIN(INPUT, gpf3-2, NONE, FAST_SR1); - PIN(INPUT, gpf3-3, DOWN, FAST_SR1); - - PIN(INPUT, gpf4-0, DOWN, FAST_SR1); - PIN(INPUT, gpf4-1, DOWN, FAST_SR1); - PIN(INPUT, gpf4-2, DOWN, FAST_SR1); - PIN(INPUT, gpf4-3, DOWN, FAST_SR1); - PIN(INPUT, gpf4-4, DOWN, FAST_SR1); - PIN(INPUT, gpf4-5, DOWN, FAST_SR1); - PIN(INPUT, gpf4-6, DOWN, FAST_SR1); - PIN(INPUT, gpf4-7, DOWN, FAST_SR1); - - PIN(INPUT, gpf5-0, DOWN, FAST_SR1); - PIN(INPUT, gpf5-1, DOWN, FAST_SR1); - PIN(INPUT, gpf5-2, DOWN, FAST_SR1); - PIN(INPUT, gpf5-3, DOWN, FAST_SR1); - PIN(OUTPUT, gpf5-4, NONE, FAST_SR1); - PIN(INPUT, gpf5-5, DOWN, FAST_SR1); - PIN(INPUT, gpf5-6, DOWN, FAST_SR1); - PIN(INPUT, gpf5-7, DOWN, FAST_SR1); - }; - - te_irq: te_irq { - samsung,pins = "gpf1-3"; - samsung,pin-function = <0xf>; - }; -}; - -&pinctrl_cpif { - pinctrl-names = "default"; - pinctrl-0 = <&initial_cpif>; - - initial_cpif: initial-state { - PIN(INPUT, gpv6-0, DOWN, FAST_SR1); - PIN(INPUT, gpv6-1, DOWN, FAST_SR1); - }; -}; - -&pinctrl_ese { - pinctrl-names = "default"; - pinctrl-0 = <&initial_ese>; - - initial_ese: initial-state { - PIN(INPUT, gpj2-0, DOWN, FAST_SR1); - PIN(INPUT, gpj2-1, DOWN, FAST_SR1); - PIN(INPUT, gpj2-2, DOWN, FAST_SR1); - }; -}; - -&pinctrl_fsys { - pinctrl-names = "default"; - pinctrl-0 = <&initial_fsys>; - - initial_fsys: initial-state { - PIN(INPUT, gpr3-0, NONE, FAST_SR1); - PIN(INPUT, gpr3-1, DOWN, FAST_SR1); - PIN(INPUT, gpr3-2, DOWN, FAST_SR1); - PIN(INPUT, gpr3-3, DOWN, FAST_SR1); - PIN(INPUT, gpr3-7, NONE, FAST_SR1); - }; -}; - -&pinctrl_imem { - pinctrl-names = "default"; - pinctrl-0 = <&initial_imem>; - - initial_imem: initial-state { - PIN(INPUT, gpf0-0, UP, FAST_SR1); - PIN(INPUT, gpf0-1, UP, FAST_SR1); - PIN(INPUT, gpf0-2, DOWN, FAST_SR1); - PIN(INPUT, gpf0-3, UP, FAST_SR1); - PIN(INPUT, gpf0-4, DOWN, FAST_SR1); - PIN(INPUT, gpf0-5, NONE, FAST_SR1); - PIN(INPUT, gpf0-6, DOWN, FAST_SR1); - PIN(INPUT, gpf0-7, UP, FAST_SR1); - }; -}; - -&pinctrl_nfc { - pinctrl-names = "default"; - pinctrl-0 = <&initial_nfc>; - - initial_nfc: initial-state { - PIN(INPUT, gpj0-2, DOWN, FAST_SR1); - }; -}; - -&pinctrl_peric { - pinctrl-names = "default"; - pinctrl-0 = <&initial_peric>; - - initial_peric: initial-state { - PIN(INPUT, gpv7-0, DOWN, FAST_SR1); - PIN(INPUT, gpv7-1, DOWN, FAST_SR1); - PIN(INPUT, gpv7-2, NONE, FAST_SR1); - PIN(INPUT, gpv7-3, DOWN, FAST_SR1); - PIN(INPUT, gpv7-4, DOWN, FAST_SR1); - PIN(INPUT, gpv7-5, DOWN, FAST_SR1); - - PIN(INPUT, gpb0-4, DOWN, FAST_SR1); - - PIN(INPUT, gpc0-2, DOWN, FAST_SR1); - PIN(INPUT, gpc0-5, DOWN, FAST_SR1); - PIN(INPUT, gpc0-7, DOWN, FAST_SR1); - - PIN(INPUT, gpc1-1, DOWN, FAST_SR1); - - PIN(INPUT, gpc3-4, NONE, FAST_SR1); - PIN(INPUT, gpc3-5, NONE, FAST_SR1); - PIN(INPUT, gpc3-6, NONE, FAST_SR1); - PIN(INPUT, gpc3-7, NONE, FAST_SR1); - - PIN(OUTPUT, gpg0-0, NONE, FAST_SR1); - PIN(2, gpg0-1, DOWN, FAST_SR1); - - PIN(INPUT, gpd2-5, DOWN, FAST_SR1); - - PIN(INPUT, gpd4-0, NONE, FAST_SR1); - PIN(INPUT, gpd4-1, DOWN, FAST_SR1); - PIN(INPUT, gpd4-2, DOWN, FAST_SR1); - PIN(INPUT, gpd4-3, DOWN, FAST_SR1); - PIN(INPUT, gpd4-4, DOWN, FAST_SR1); - - PIN(INPUT, gpd6-3, DOWN, FAST_SR1); - - PIN(INPUT, gpd8-1, UP, FAST_SR1); - - PIN(INPUT, gpg1-0, DOWN, FAST_SR1); - PIN(INPUT, gpg1-1, DOWN, FAST_SR1); - PIN(INPUT, gpg1-2, DOWN, FAST_SR1); - PIN(INPUT, gpg1-3, DOWN, FAST_SR1); - PIN(INPUT, gpg1-4, DOWN, FAST_SR1); - - PIN(INPUT, gpg2-0, DOWN, FAST_SR1); - PIN(INPUT, gpg2-1, DOWN, FAST_SR1); - - PIN(INPUT, gpg3-0, DOWN, FAST_SR1); - PIN(INPUT, gpg3-1, DOWN, FAST_SR1); - PIN(INPUT, gpg3-5, DOWN, FAST_SR1); - }; -}; - -&pinctrl_touch { - pinctrl-names = "default"; - pinctrl-0 = <&initial_touch>; - - initial_touch: initial-state { - PIN(INPUT, gpj1-2, DOWN, FAST_SR1); - }; -}; - -&pwm { - pinctrl-0 = <&pwm0_out>; - pinctrl-names = "default"; - status = "okay"; -}; - -&mic { - status = "okay"; -}; - -&pmu_system_controller { - assigned-clocks = <&pmu_system_controller 0>; - assigned-clock-parents = <&xxti>; -}; - -&serial_1 { - status = "okay"; -}; - -&serial_3 { - status = "okay"; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - max-speed = <3000000>; - shutdown-gpios = <&gpd4 0 GPIO_ACTIVE_HIGH>; - device-wakeup-gpios = <&gpr3 7 GPIO_ACTIVE_HIGH>; - host-wakeup-gpios = <&gpa2 2 GPIO_ACTIVE_HIGH>; - clocks = <&s2mps13_osc S2MPS11_CLK_BT>; - clock-names = "extclk"; - }; -}; - -&spi_1 { - cs-gpios = <&gpd6 3 GPIO_ACTIVE_HIGH>; - status = "okay"; - - wm5110: wm5110-codec@0 { - compatible = "wlf,wm5110"; - reg = <0x0>; - spi-max-frequency = <20000000>; - interrupt-parent = <&gpa0>; - interrupts = <4 IRQ_TYPE_NONE>; - clocks = <&pmu_system_controller 0>, - <&s2mps13_osc S2MPS11_CLK_BT>; - clock-names = "mclk1", "mclk2"; - - gpio-controller; - #gpio-cells = <2>; - - wlf,micd-detect-debounce = <300>; - wlf,micd-bias-start-time = <0x1>; - wlf,micd-rate = <0x7>; - wlf,micd-dbtime = <0x1>; - wlf,micd-force-micbias; - wlf,micd-configs = <0x0 1 0>; - wlf,hpdet-channel = <1>; - wlf,gpsw = <0x1>; - wlf,inmode = <2 0 2 0>; - - wlf,reset = <&gpc0 7 GPIO_ACTIVE_HIGH>; - wlf,ldoena = <&gpf0 0 GPIO_ACTIVE_HIGH>; - - /* core supplies */ - AVDD-supply = <&ldo18_reg>; - DBVDD1-supply = <&ldo18_reg>; - CPVDD-supply = <&ldo18_reg>; - DBVDD2-supply = <&ldo18_reg>; - DBVDD3-supply = <&ldo18_reg>; - - controller-data { - samsung,spi-feedback-delay = <0>; - }; - }; -}; - -&spi_3 { - status = "okay"; - no-cs-readback; - - irled@0 { - compatible = "ir-spi-led"; - reg = <0x0>; - spi-max-frequency = <5000000>; - power-supply = <&irda_regulator>; - duty-cycle = <60>; - led-active-low; - - controller-data { - samsung,spi-feedback-delay = <0>; - }; - }; -}; - -&timer { - clock-frequency = <24000000>; -}; - -&tmu_atlas0 { - vtmu-supply = <&ldo3_reg>; - status = "okay"; -}; - -&tmu_apollo { - vtmu-supply = <&ldo3_reg>; - status = "okay"; -}; - -&tmu_g3d { - vtmu-supply = <&ldo3_reg>; - status = "okay"; -}; - -&usbdrd30 { - vdd33-supply = <&ldo10_reg>; - vdd10-supply = <&ldo6_reg>; - status = "okay"; -}; - -&usbdrd_dwc3 { - dr_mode = "otg"; -}; - -&usbdrd30_phy { - vbus-supply = <&safeout1_reg>; - status = "okay"; - - port { - usb_to_muic: endpoint { - remote-endpoint = <&muic_to_usb>; - }; - }; -}; - -&xxti { - clock-frequency = <24000000>; -}; diff --git a/sys/gnu/dts/arm64/exynos/exynos5433-tm2.dts b/sys/gnu/dts/arm64/exynos/exynos5433-tm2.dts deleted file mode 100644 index fdd0796b29d..00000000000 --- a/sys/gnu/dts/arm64/exynos/exynos5433-tm2.dts +++ /dev/null @@ -1,93 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung Exynos5433 TM2 board device tree source - * - * Copyright (c) 2016 Samsung Electronics Co., Ltd. - * - * Device tree source file for Samsung's TM2 board which is based on - * Samsung Exynos5433 SoC. - */ - -#include "exynos5433-tm2-common.dtsi" - -/ { - model = "Samsung TM2 board"; - compatible = "samsung,tm2", "samsung,exynos5433"; -}; - -&cmu_disp { - /* - * TM2 and TM2e differ only by DISP_PLL rate, but define all assigned - * clocks properties for DISP CMU for each board to keep them together - * for easier review and maintenance. - */ - assigned-clocks = <&cmu_disp CLK_FOUT_DISP_PLL>, - <&cmu_mif CLK_DIV_SCLK_DECON_TV_ECLK>, - <&cmu_disp CLK_MOUT_ACLK_DISP_333_USER>, - <&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>, - <&cmu_disp CLK_MOUT_SCLK_DSIM0>, - <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>, - <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK>, - <&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER>, - <&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER>, - <&cmu_disp CLK_MOUT_DISP_PLL>, - <&cmu_mif CLK_MOUT_SCLK_DECON_TV_ECLK_A>, - <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>, - <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK>, - <&cmu_disp CLK_MOUT_SCLK_DSD_USER>; - assigned-clock-parents = <0>, <0>, - <&cmu_mif CLK_ACLK_DISP_333>, - <&cmu_mif CLK_SCLK_DSIM0_DISP>, - <&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>, - <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>, - <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>, - <&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY>, - <&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY>, - <&cmu_disp CLK_FOUT_DISP_PLL>, - <&cmu_mif CLK_MOUT_BUS_PLL_DIV2>, - <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>, - <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>, - <&cmu_mif CLK_SCLK_DSD_DISP>; - assigned-clock-rates = <250000000>, <400000000>; -}; - -&dsi { - panel@0 { - compatible = "samsung,s6e3ha2"; - reg = <0>; - vdd3-supply = <&ldo27_reg>; - vci-supply = <&ldo28_reg>; - reset-gpios = <&gpg0 0 GPIO_ACTIVE_LOW>; - enable-gpios = <&gpf1 5 GPIO_ACTIVE_HIGH>; - }; -}; - -&hsi2c_9 { - status = "okay"; - - touchkey@20 { - compatible = "cypress,tm2-touchkey"; - reg = <0x20>; - interrupt-parent = <&gpa3>; - interrupts = <2 IRQ_TYPE_EDGE_FALLING>; - vcc-supply = <&ldo32_reg>; - vdd-supply = <&ldo33_reg>; - }; -}; - -&ldo31_reg { - regulator-name = "TSP_VDD_1.85V_AP"; - regulator-min-microvolt = <1850000>; - regulator-max-microvolt = <1850000>; -}; - -&ldo38_reg { - regulator-name = "VCC_3.0V_MOTOR_AP"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; -}; - -&stmfts { - touchscreen-size-x = <1439>; - touchscreen-size-y = <2559>; -}; diff --git a/sys/gnu/dts/arm64/exynos/exynos5433-tm2e.dts b/sys/gnu/dts/arm64/exynos/exynos5433-tm2e.dts deleted file mode 100644 index 089fc7a1af6..00000000000 --- a/sys/gnu/dts/arm64/exynos/exynos5433-tm2e.dts +++ /dev/null @@ -1,80 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung Exynos5433 TM2E board device tree source - * - * Copyright (c) 2016 Samsung Electronics Co., Ltd. - * - * Device tree source file for Samsung's TM2E(TM2 EDGE) board which is based on - * Samsung Exynos5433 SoC. - */ - -#include "exynos5433-tm2-common.dtsi" - -/ { - model = "Samsung TM2E board"; - compatible = "samsung,tm2e", "samsung,exynos5433"; -}; - -&cmu_disp { - /* - * TM2 and TM2e differ only by DISP_PLL rate, but define all assigned - * clocks properties for DISP CMU for each board to keep them together - * for easier review and maintenance. - */ - assigned-clocks = <&cmu_disp CLK_FOUT_DISP_PLL>, - <&cmu_mif CLK_DIV_SCLK_DECON_TV_ECLK>, - <&cmu_disp CLK_MOUT_ACLK_DISP_333_USER>, - <&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>, - <&cmu_disp CLK_MOUT_SCLK_DSIM0>, - <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>, - <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK>, - <&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER>, - <&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER>, - <&cmu_disp CLK_MOUT_DISP_PLL>, - <&cmu_mif CLK_MOUT_SCLK_DECON_TV_ECLK_A>, - <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>, - <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK>; - assigned-clock-parents = <0>, <0>, - <&cmu_mif CLK_ACLK_DISP_333>, - <&cmu_mif CLK_SCLK_DSIM0_DISP>, - <&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>, - <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>, - <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>, - <&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY>, - <&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY>, - <&cmu_disp CLK_FOUT_DISP_PLL>, - <&cmu_mif CLK_MOUT_BUS_PLL_DIV2>, - <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>, - <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>; - assigned-clock-rates = <278000000>, <400000000>; -}; - -&dsi { - panel@0 { - compatible = "samsung,s6e3hf2"; - reg = <0>; - vdd3-supply = <&ldo27_reg>; - vci-supply = <&ldo28_reg>; - reset-gpios = <&gpg0 0 GPIO_ACTIVE_LOW>; - enable-gpios = <&gpf1 5 GPIO_ACTIVE_HIGH>; - }; -}; - -&ldo31_reg { - regulator-name = "TSP_VDD_1.8V_AP"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; -}; - -&ldo38_reg { - regulator-name = "VCC_3.3V_MOTOR_AP"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; -}; - -&stmfts { - touchscreen-size-x = <1599>; - touchscreen-size-y = <2559>; - touch-key-connected; - ledvdd-supply = <&ldo33_reg>; -}; diff --git a/sys/gnu/dts/arm64/exynos/exynos5433-tmu.dtsi b/sys/gnu/dts/arm64/exynos/exynos5433-tmu.dtsi deleted file mode 100644 index 81b72393dd0..00000000000 --- a/sys/gnu/dts/arm64/exynos/exynos5433-tmu.dtsi +++ /dev/null @@ -1,305 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device tree sources for Exynos5433 thermal zone - * - * Copyright (c) 2016 Chanwoo Choi - */ - -#include - -/ { -thermal-zones { - atlas0_thermal: atlas0-thermal { - thermal-sensors = <&tmu_atlas0>; - polling-delay-passive = <0>; - polling-delay = <0>; - trips { - atlas0_alert_0: atlas0-alert-0 { - temperature = <65000>; /* millicelsius */ - hysteresis = <1000>; /* millicelsius */ - type = "active"; - }; - atlas0_alert_1: atlas0-alert-1 { - temperature = <70000>; /* millicelsius */ - hysteresis = <1000>; /* millicelsius */ - type = "active"; - }; - atlas0_alert_2: atlas0-alert-2 { - temperature = <75000>; /* millicelsius */ - hysteresis = <1000>; /* millicelsius */ - type = "active"; - }; - atlas0_alert_3: atlas0-alert-3 { - temperature = <80000>; /* millicelsius */ - hysteresis = <1000>; /* millicelsius */ - type = "active"; - }; - atlas0_alert_4: atlas0-alert-4 { - temperature = <85000>; /* millicelsius */ - hysteresis = <1000>; /* millicelsius */ - type = "active"; - }; - atlas0_alert_5: atlas0-alert-5 { - temperature = <90000>; /* millicelsius */ - hysteresis = <1000>; /* millicelsius */ - type = "active"; - }; - atlas0_alert_6: atlas0-alert-6 { - temperature = <95000>; /* millicelsius */ - hysteresis = <1000>; /* millicelsius */ - type = "active"; - }; - }; - - cooling-maps { - map0 { - /* Set maximum frequency as 1800MHz */ - trip = <&atlas0_alert_0>; - cooling-device = <&cpu4 1 2>, <&cpu5 1 2>, - <&cpu6 1 2>, <&cpu7 1 2>; - }; - map1 { - /* Set maximum frequency as 1700MHz */ - trip = <&atlas0_alert_1>; - cooling-device = <&cpu4 2 3>, <&cpu5 2 3>, - <&cpu6 2 3>, <&cpu7 2 3>; - }; - map2 { - /* Set maximum frequency as 1600MHz */ - trip = <&atlas0_alert_2>; - cooling-device = <&cpu4 3 4>, <&cpu5 3 4>, - <&cpu6 3 4>, <&cpu7 3 4>; - }; - map3 { - /* Set maximum frequency as 1500MHz */ - trip = <&atlas0_alert_3>; - cooling-device = <&cpu4 4 5>, <&cpu5 4 5>, - <&cpu6 4 5>, <&cpu7 4 5>; - }; - map4 { - /* Set maximum frequency as 1400MHz */ - trip = <&atlas0_alert_4>; - cooling-device = <&cpu4 5 7>, <&cpu5 5 7>, - <&cpu6 5 7>, <&cpu7 5 7>; - }; - map5 { - /* Set maximum frequencyas 1200MHz */ - trip = <&atlas0_alert_5>; - cooling-device = <&cpu4 7 9>, <&cpu5 7 9>, - <&cpu6 7 9>, <&cpu7 7 9>; - }; - map6 { - /* Set maximum frequency as 1000MHz */ - trip = <&atlas0_alert_6>; - cooling-device = <&cpu4 9 14>, <&cpu5 9 14>, - <&cpu6 9 14>, <&cpu7 9 14>; - }; - }; - }; - - atlas1_thermal: atlas1-thermal { - thermal-sensors = <&tmu_atlas1>; - polling-delay-passive = <0>; - polling-delay = <0>; - trips { - atlas1_alert_0: atlas1-alert-0 { - temperature = <65000>; /* millicelsius */ - hysteresis = <1000>; /* millicelsius */ - type = "active"; - }; - atlas1_alert_1: atlas1-alert-1 { - temperature = <70000>; /* millicelsius */ - hysteresis = <1000>; /* millicelsius */ - type = "active"; - }; - atlas1_alert_2: atlas1-alert-2 { - temperature = <75000>; /* millicelsius */ - hysteresis = <1000>; /* millicelsius */ - type = "active"; - }; - atlas1_alert_3: atlas1-alert-3 { - temperature = <80000>; /* millicelsius */ - hysteresis = <1000>; /* millicelsius */ - type = "active"; - }; - atlas1_alert_4: atlas1-alert-4 { - temperature = <85000>; /* millicelsius */ - hysteresis = <1000>; /* millicelsius */ - type = "active"; - }; - atlas1_alert_5: atlas1-alert-5 { - temperature = <90000>; /* millicelsius */ - hysteresis = <1000>; /* millicelsius */ - type = "active"; - }; - atlas1_alert_6: atlas1-alert-6 { - temperature = <95000>; /* millicelsius */ - hysteresis = <1000>; /* millicelsius */ - type = "active"; - }; - }; - }; - - g3d_thermal: g3d-thermal { - thermal-sensors = <&tmu_g3d>; - polling-delay-passive = <0>; - polling-delay = <0>; - trips { - g3d_alert_0: g3d-alert-0 { - temperature = <70000>; /* millicelsius */ - hysteresis = <1000>; /* millicelsius */ - type = "active"; - }; - g3d_alert_1: g3d-alert-1 { - temperature = <75000>; /* millicelsius */ - hysteresis = <1000>; /* millicelsius */ - type = "active"; - }; - g3d_alert_2: g3d-alert-2 { - temperature = <80000>; /* millicelsius */ - hysteresis = <1000>; /* millicelsius */ - type = "active"; - }; - g3d_alert_3: g3d-alert-3 { - temperature = <85000>; /* millicelsius */ - hysteresis = <1000>; /* millicelsius */ - type = "active"; - }; - g3d_alert_4: g3d-alert-4 { - temperature = <90000>; /* millicelsius */ - hysteresis = <1000>; /* millicelsius */ - type = "active"; - }; - g3d_alert_5: g3d-alert-5 { - temperature = <95000>; /* millicelsius */ - hysteresis = <1000>; /* millicelsius */ - type = "active"; - }; - g3d_alert_6: g3d-alert-6 { - temperature = <100000>; /* millicelsius */ - hysteresis = <1000>; /* millicelsius */ - type = "active"; - }; - }; - }; - - apollo_thermal: apollo-thermal { - thermal-sensors = <&tmu_apollo>; - polling-delay-passive = <0>; - polling-delay = <0>; - trips { - apollo_alert_0: apollo-alert-0 { - temperature = <65000>; /* millicelsius */ - hysteresis = <1000>; /* millicelsius */ - type = "active"; - }; - apollo_alert_1: apollo-alert-1 { - temperature = <70000>; /* millicelsius */ - hysteresis = <1000>; /* millicelsius */ - type = "active"; - }; - apollo_alert_2: apollo-alert-2 { - temperature = <75000>; /* millicelsius */ - hysteresis = <1000>; /* millicelsius */ - type = "active"; - }; - apollo_alert_3: apollo-alert-3 { - temperature = <80000>; /* millicelsius */ - hysteresis = <1000>; /* millicelsius */ - type = "active"; - }; - apollo_alert_4: apollo-alert-4 { - temperature = <85000>; /* millicelsius */ - hysteresis = <1000>; /* millicelsius */ - type = "active"; - }; - apollo_alert_5: apollo-alert-5 { - temperature = <90000>; /* millicelsius */ - hysteresis = <1000>; /* millicelsius */ - type = "active"; - }; - apollo_alert_6: apollo-alert-6 { - temperature = <95000>; /* millicelsius */ - hysteresis = <1000>; /* millicelsius */ - type = "active"; - }; - }; - - cooling-maps { - map0 { - /* Set maximum frequency as 1200MHz */ - trip = <&apollo_alert_2>; - cooling-device = <&cpu0 1 2>, <&cpu1 1 2>, - <&cpu2 1 2>, <&cpu3 1 2>; - }; - map1 { - /* Set maximum frequency as 1100MHz */ - trip = <&apollo_alert_3>; - cooling-device = <&cpu0 2 3>, <&cpu1 2 3>, - <&cpu2 2 3>, <&cpu3 2 3>; - }; - map2 { - /* Set maximum frequency as 1000MHz */ - trip = <&apollo_alert_4>; - cooling-device = <&cpu0 3 4>, <&cpu1 3 4>, - <&cpu2 3 4>, <&cpu3 3 4>; - }; - map3 { - /* Set maximum frequency as 900MHz */ - trip = <&apollo_alert_5>; - cooling-device = <&cpu0 4 5>, <&cpu1 4 5>, - <&cpu2 4 5>, <&cpu3 4 5>; - }; - map4 { - /* Set maximum frequency as 800MHz */ - trip = <&apollo_alert_6>; - cooling-device = <&cpu0 5 9>, <&cpu1 5 9>, - <&cpu2 5 9>, <&cpu3 5 9>; - }; - }; - }; - - isp_thermal: isp-thermal { - thermal-sensors = <&tmu_isp>; - polling-delay-passive = <0>; - polling-delay = <0>; - trips { - isp_alert_0: isp-alert-0 { - temperature = <80000>; /* millicelsius */ - hysteresis = <1000>; /* millicelsius */ - type = "active"; - }; - isp_alert_1: isp-alert-1 { - temperature = <85000>; /* millicelsius */ - hysteresis = <1000>; /* millicelsius */ - type = "active"; - }; - isp_alert_2: isp-alert-2 { - temperature = <90000>; /* millicelsius */ - hysteresis = <1000>; /* millicelsius */ - type = "active"; - }; - isp_alert_3: isp-alert-3 { - temperature = <95000>; /* millicelsius */ - hysteresis = <1000>; /* millicelsius */ - type = "active"; - }; - isp_alert_4: isp-alert-4 { - temperature = <100000>; /* millicelsius */ - hysteresis = <1000>; /* millicelsius */ - type = "active"; - }; - isp_alert_5: isp-alert-5 { - temperature = <105000>; /* millicelsius */ - hysteresis = <1000>; /* millicelsius */ - type = "active"; - }; - isp_alert_6: isp-alert-6 { - temperature = <110000>; /* millicelsius */ - hysteresis = <1000>; /* millicelsius */ - type = "active"; - }; - }; - }; -}; -}; diff --git a/sys/gnu/dts/arm64/exynos/exynos5433.dtsi b/sys/gnu/dts/arm64/exynos/exynos5433.dtsi deleted file mode 100644 index 6721966140f..00000000000 --- a/sys/gnu/dts/arm64/exynos/exynos5433.dtsi +++ /dev/null @@ -1,1861 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's Exynos5433 SoC device tree source - * - * Copyright (c) 2016 Samsung Electronics Co., Ltd. - * - * Samsung's Exynos5433 SoC device nodes are listed in this file. - * Exynos5433 based board files can include this file and provide - * values for board specific bindings. - * - * Note: This file does not include device nodes for all the controllers in - * Exynos5433 SoC. As device tree coverage for Exynos5433 increases, - * additional nodes can be added to this file. - */ - -#include -#include - -/ { - compatible = "samsung,exynos5433"; - #address-cells = <2>; - #size-cells = <2>; - - interrupt-parent = <&gic>; - - arm_a53_pmu { - compatible = "arm,cortex-a53-pmu", "arm,armv8-pmuv3"; - interrupts = , - , - , - ; - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; - }; - - arm_a57_pmu { - compatible = "arm,cortex-a57-pmu", "arm,armv8-pmuv3"; - interrupts = , - , - , - ; - interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; - }; - - xxti: clock { - /* XXTI */ - compatible = "fixed-clock"; - clock-output-names = "oscclk"; - #clock-cells = <0>; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x100>; - clock-frequency = <1300000000>; - clocks = <&cmu_apollo CLK_SCLK_APOLLO>; - clock-names = "apolloclk"; - operating-points-v2 = <&cluster_a53_opp_table>; - #cooling-cells = <2>; - }; - - cpu1: cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x101>; - clock-frequency = <1300000000>; - operating-points-v2 = <&cluster_a53_opp_table>; - #cooling-cells = <2>; - }; - - cpu2: cpu@102 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x102>; - clock-frequency = <1300000000>; - operating-points-v2 = <&cluster_a53_opp_table>; - #cooling-cells = <2>; - }; - - cpu3: cpu@103 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x103>; - clock-frequency = <1300000000>; - operating-points-v2 = <&cluster_a53_opp_table>; - #cooling-cells = <2>; - }; - - cpu4: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - enable-method = "psci"; - reg = <0x0>; - clock-frequency = <1900000000>; - clocks = <&cmu_atlas CLK_SCLK_ATLAS>; - clock-names = "atlasclk"; - operating-points-v2 = <&cluster_a57_opp_table>; - #cooling-cells = <2>; - }; - - cpu5: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - enable-method = "psci"; - reg = <0x1>; - clock-frequency = <1900000000>; - operating-points-v2 = <&cluster_a57_opp_table>; - #cooling-cells = <2>; - }; - - cpu6: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - enable-method = "psci"; - reg = <0x2>; - clock-frequency = <1900000000>; - operating-points-v2 = <&cluster_a57_opp_table>; - #cooling-cells = <2>; - }; - - cpu7: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - enable-method = "psci"; - reg = <0x3>; - clock-frequency = <1900000000>; - operating-points-v2 = <&cluster_a57_opp_table>; - #cooling-cells = <2>; - }; - }; - - cluster_a53_opp_table: opp_table0 { - compatible = "operating-points-v2"; - opp-shared; - - opp-400000000 { - opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <900000>; - }; - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <925000>; - }; - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <950000>; - }; - opp-700000000 { - opp-hz = /bits/ 64 <700000000>; - opp-microvolt = <975000>; - }; - opp-800000000 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <1000000>; - }; - opp-900000000 { - opp-hz = /bits/ 64 <900000000>; - opp-microvolt = <1050000>; - }; - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <1075000>; - }; - opp-1100000000 { - opp-hz = /bits/ 64 <1100000000>; - opp-microvolt = <1112500>; - }; - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <1112500>; - }; - opp-1300000000 { - opp-hz = /bits/ 64 <1300000000>; - opp-microvolt = <1150000>; - }; - }; - - cluster_a57_opp_table: opp_table1 { - compatible = "operating-points-v2"; - opp-shared; - - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <900000>; - }; - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <900000>; - }; - opp-700000000 { - opp-hz = /bits/ 64 <700000000>; - opp-microvolt = <912500>; - }; - opp-800000000 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <912500>; - }; - opp-900000000 { - opp-hz = /bits/ 64 <900000000>; - opp-microvolt = <937500>; - }; - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <975000>; - }; - opp-1100000000 { - opp-hz = /bits/ 64 <1100000000>; - opp-microvolt = <1012500>; - }; - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <1037500>; - }; - opp-1300000000 { - opp-hz = /bits/ 64 <1300000000>; - opp-microvolt = <1062500>; - }; - opp-1400000000 { - opp-hz = /bits/ 64 <1400000000>; - opp-microvolt = <1087500>; - }; - opp-1500000000 { - opp-hz = /bits/ 64 <1500000000>; - opp-microvolt = <1125000>; - }; - opp-1600000000 { - opp-hz = /bits/ 64 <1600000000>; - opp-microvolt = <1137500>; - }; - opp-1700000000 { - opp-hz = /bits/ 64 <1700000000>; - opp-microvolt = <1175000>; - }; - opp-1800000000 { - opp-hz = /bits/ 64 <1800000000>; - opp-microvolt = <1212500>; - }; - opp-1900000000 { - opp-hz = /bits/ 64 <1900000000>; - opp-microvolt = <1262500>; - }; - }; - - psci { - compatible = "arm,psci"; - method = "smc"; - cpu_off = <0x84000002>; - cpu_on = <0xC4000003>; - }; - - soc: soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x0 0x18000000>; - - chipid@10000000 { - compatible = "samsung,exynos4210-chipid"; - reg = <0x10000000 0x100>; - }; - - cmu_top: clock-controller@10030000 { - compatible = "samsung,exynos5433-cmu-top"; - reg = <0x10030000 0x1000>; - #clock-cells = <1>; - - clock-names = "oscclk", - "sclk_mphy_pll", - "sclk_mfc_pll", - "sclk_bus_pll"; - clocks = <&xxti>, - <&cmu_cpif CLK_SCLK_MPHY_PLL>, - <&cmu_mif CLK_SCLK_MFC_PLL>, - <&cmu_mif CLK_SCLK_BUS_PLL>; - }; - - cmu_cpif: clock-controller@10fc0000 { - compatible = "samsung,exynos5433-cmu-cpif"; - reg = <0x10fc0000 0x1000>; - #clock-cells = <1>; - - clock-names = "oscclk"; - clocks = <&xxti>; - }; - - cmu_mif: clock-controller@105b0000 { - compatible = "samsung,exynos5433-cmu-mif"; - reg = <0x105b0000 0x2000>; - #clock-cells = <1>; - - clock-names = "oscclk", - "sclk_mphy_pll"; - clocks = <&xxti>, - <&cmu_cpif CLK_SCLK_MPHY_PLL>; - }; - - cmu_peric: clock-controller@14c80000 { - compatible = "samsung,exynos5433-cmu-peric"; - reg = <0x14c80000 0x1000>; - #clock-cells = <1>; - }; - - cmu_peris: clock-controller@10040000 { - compatible = "samsung,exynos5433-cmu-peris"; - reg = <0x10040000 0x1000>; - #clock-cells = <1>; - }; - - cmu_fsys: clock-controller@156e0000 { - compatible = "samsung,exynos5433-cmu-fsys"; - reg = <0x156e0000 0x1000>; - #clock-cells = <1>; - - clock-names = "oscclk", - "sclk_ufs_mphy", - "aclk_fsys_200", - "sclk_pcie_100_fsys", - "sclk_ufsunipro_fsys", - "sclk_mmc2_fsys", - "sclk_mmc1_fsys", - "sclk_mmc0_fsys", - "sclk_usbhost30_fsys", - "sclk_usbdrd30_fsys"; - clocks = <&xxti>, - <&cmu_cpif CLK_SCLK_UFS_MPHY>, - <&cmu_top CLK_ACLK_FSYS_200>, - <&cmu_top CLK_SCLK_PCIE_100_FSYS>, - <&cmu_top CLK_SCLK_UFSUNIPRO_FSYS>, - <&cmu_top CLK_SCLK_MMC2_FSYS>, - <&cmu_top CLK_SCLK_MMC1_FSYS>, - <&cmu_top CLK_SCLK_MMC0_FSYS>, - <&cmu_top CLK_SCLK_USBHOST30_FSYS>, - <&cmu_top CLK_SCLK_USBDRD30_FSYS>; - }; - - cmu_g2d: clock-controller@12460000 { - compatible = "samsung,exynos5433-cmu-g2d"; - reg = <0x12460000 0x1000>; - #clock-cells = <1>; - - clock-names = "oscclk", - "aclk_g2d_266", - "aclk_g2d_400"; - clocks = <&xxti>, - <&cmu_top CLK_ACLK_G2D_266>, - <&cmu_top CLK_ACLK_G2D_400>; - power-domains = <&pd_g2d>; - }; - - cmu_disp: clock-controller@13b90000 { - compatible = "samsung,exynos5433-cmu-disp"; - reg = <0x13b90000 0x1000>; - #clock-cells = <1>; - - clock-names = "oscclk", - "sclk_dsim1_disp", - "sclk_dsim0_disp", - "sclk_dsd_disp", - "sclk_decon_tv_eclk_disp", - "sclk_decon_vclk_disp", - "sclk_decon_eclk_disp", - "sclk_decon_tv_vclk_disp", - "aclk_disp_333"; - clocks = <&xxti>, - <&cmu_mif CLK_SCLK_DSIM1_DISP>, - <&cmu_mif CLK_SCLK_DSIM0_DISP>, - <&cmu_mif CLK_SCLK_DSD_DISP>, - <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>, - <&cmu_mif CLK_SCLK_DECON_VCLK_DISP>, - <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>, - <&cmu_mif CLK_SCLK_DECON_TV_VCLK_DISP>, - <&cmu_mif CLK_ACLK_DISP_333>; - power-domains = <&pd_disp>; - }; - - cmu_aud: clock-controller@114c0000 { - compatible = "samsung,exynos5433-cmu-aud"; - reg = <0x114c0000 0x1000>; - #clock-cells = <1>; - clock-names = "oscclk", "fout_aud_pll"; - clocks = <&xxti>, <&cmu_top CLK_FOUT_AUD_PLL>; - power-domains = <&pd_aud>; - }; - - cmu_bus0: clock-controller@13600000 { - compatible = "samsung,exynos5433-cmu-bus0"; - reg = <0x13600000 0x1000>; - #clock-cells = <1>; - - clock-names = "aclk_bus0_400"; - clocks = <&cmu_top CLK_ACLK_BUS0_400>; - }; - - cmu_bus1: clock-controller@14800000 { - compatible = "samsung,exynos5433-cmu-bus1"; - reg = <0x14800000 0x1000>; - #clock-cells = <1>; - - clock-names = "aclk_bus1_400"; - clocks = <&cmu_top CLK_ACLK_BUS1_400>; - }; - - cmu_bus2: clock-controller@13400000 { - compatible = "samsung,exynos5433-cmu-bus2"; - reg = <0x13400000 0x1000>; - #clock-cells = <1>; - - clock-names = "oscclk", "aclk_bus2_400"; - clocks = <&xxti>, <&cmu_mif CLK_ACLK_BUS2_400>; - }; - - cmu_g3d: clock-controller@14aa0000 { - compatible = "samsung,exynos5433-cmu-g3d"; - reg = <0x14aa0000 0x2000>; - #clock-cells = <1>; - - clock-names = "oscclk", "aclk_g3d_400"; - clocks = <&xxti>, <&cmu_top CLK_ACLK_G3D_400>; - power-domains = <&pd_g3d>; - }; - - cmu_gscl: clock-controller@13cf0000 { - compatible = "samsung,exynos5433-cmu-gscl"; - reg = <0x13cf0000 0x1000>; - #clock-cells = <1>; - - clock-names = "oscclk", - "aclk_gscl_111", - "aclk_gscl_333"; - clocks = <&xxti>, - <&cmu_top CLK_ACLK_GSCL_111>, - <&cmu_top CLK_ACLK_GSCL_333>; - power-domains = <&pd_gscl>; - }; - - cmu_apollo: clock-controller@11900000 { - compatible = "samsung,exynos5433-cmu-apollo"; - reg = <0x11900000 0x2000>; - #clock-cells = <1>; - - clock-names = "oscclk", "sclk_bus_pll_apollo"; - clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_APOLLO>; - }; - - cmu_atlas: clock-controller@11800000 { - compatible = "samsung,exynos5433-cmu-atlas"; - reg = <0x11800000 0x2000>; - #clock-cells = <1>; - - clock-names = "oscclk", "sclk_bus_pll_atlas"; - clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_ATLAS>; - }; - - cmu_mscl: clock-controller@150d0000 { - compatible = "samsung,exynos5433-cmu-mscl"; - reg = <0x150d0000 0x1000>; - #clock-cells = <1>; - - clock-names = "oscclk", - "sclk_jpeg_mscl", - "aclk_mscl_400"; - clocks = <&xxti>, - <&cmu_top CLK_SCLK_JPEG_MSCL>, - <&cmu_top CLK_ACLK_MSCL_400>; - power-domains = <&pd_mscl>; - }; - - cmu_mfc: clock-controller@15280000 { - compatible = "samsung,exynos5433-cmu-mfc"; - reg = <0x15280000 0x1000>; - #clock-cells = <1>; - - clock-names = "oscclk", "aclk_mfc_400"; - clocks = <&xxti>, <&cmu_top CLK_ACLK_MFC_400>; - power-domains = <&pd_mfc>; - }; - - cmu_hevc: clock-controller@14f80000 { - compatible = "samsung,exynos5433-cmu-hevc"; - reg = <0x14f80000 0x1000>; - #clock-cells = <1>; - - clock-names = "oscclk", "aclk_hevc_400"; - clocks = <&xxti>, <&cmu_top CLK_ACLK_HEVC_400>; - power-domains = <&pd_hevc>; - }; - - cmu_isp: clock-controller@146d0000 { - compatible = "samsung,exynos5433-cmu-isp"; - reg = <0x146d0000 0x1000>; - #clock-cells = <1>; - - clock-names = "oscclk", - "aclk_isp_dis_400", - "aclk_isp_400"; - clocks = <&xxti>, - <&cmu_top CLK_ACLK_ISP_DIS_400>, - <&cmu_top CLK_ACLK_ISP_400>; - power-domains = <&pd_isp>; - }; - - cmu_cam0: clock-controller@120d0000 { - compatible = "samsung,exynos5433-cmu-cam0"; - reg = <0x120d0000 0x1000>; - #clock-cells = <1>; - - clock-names = "oscclk", - "aclk_cam0_333", - "aclk_cam0_400", - "aclk_cam0_552"; - clocks = <&xxti>, - <&cmu_top CLK_ACLK_CAM0_333>, - <&cmu_top CLK_ACLK_CAM0_400>, - <&cmu_top CLK_ACLK_CAM0_552>; - power-domains = <&pd_cam0>; - }; - - cmu_cam1: clock-controller@145d0000 { - compatible = "samsung,exynos5433-cmu-cam1"; - reg = <0x145d0000 0x1000>; - #clock-cells = <1>; - - clock-names = "oscclk", - "sclk_isp_uart_cam1", - "sclk_isp_spi1_cam1", - "sclk_isp_spi0_cam1", - "aclk_cam1_333", - "aclk_cam1_400", - "aclk_cam1_552"; - clocks = <&xxti>, - <&cmu_top CLK_SCLK_ISP_UART_CAM1>, - <&cmu_top CLK_SCLK_ISP_SPI1_CAM1>, - <&cmu_top CLK_SCLK_ISP_SPI0_CAM1>, - <&cmu_top CLK_ACLK_CAM1_333>, - <&cmu_top CLK_ACLK_CAM1_400>, - <&cmu_top CLK_ACLK_CAM1_552>; - power-domains = <&pd_cam1>; - }; - - cmu_imem: clock-controller@11060000 { - compatible = "samsung,exynos5433-cmu-imem"; - reg = <0x11060000 0x1000>; - #clock-cells = <1>; - - clock-names = "oscclk", - "aclk_imem_sssx_266", - "aclk_imem_266", - "aclk_imem_200"; - clocks = <&xxti>, - <&cmu_top CLK_DIV_ACLK_IMEM_SSSX_266>, - <&cmu_top CLK_DIV_ACLK_IMEM_266>, - <&cmu_top CLK_DIV_ACLK_IMEM_200>; - }; - - slim_sss: slim-sss@11140000 { - compatible = "samsung,exynos5433-slim-sss"; - reg = <0x11140000 0x1000>; - interrupts = ; - clock-names = "aclk", "pclk"; - clocks = <&cmu_imem CLK_ACLK_SLIMSSS>, - <&cmu_imem CLK_PCLK_SLIMSSS>; - }; - - pd_gscl: power-domain@105c4000 { - compatible = "samsung,exynos5433-pd"; - reg = <0x105c4000 0x20>; - #power-domain-cells = <0>; - label = "GSCL"; - }; - - pd_cam0: power-domain@105c4020 { - compatible = "samsung,exynos5433-pd"; - reg = <0x105c4020 0x20>; - #power-domain-cells = <0>; - power-domains = <&pd_cam1>; - label = "CAM0"; - }; - - pd_mscl: power-domain@105c4040 { - compatible = "samsung,exynos5433-pd"; - reg = <0x105c4040 0x20>; - #power-domain-cells = <0>; - label = "MSCL"; - }; - - pd_g3d: power-domain@105c4060 { - compatible = "samsung,exynos5433-pd"; - reg = <0x105c4060 0x20>; - #power-domain-cells = <0>; - label = "G3D"; - }; - - pd_disp: power-domain@105c4080 { - compatible = "samsung,exynos5433-pd"; - reg = <0x105c4080 0x20>; - #power-domain-cells = <0>; - label = "DISP"; - }; - - pd_cam1: power-domain@105c40a0 { - compatible = "samsung,exynos5433-pd"; - reg = <0x105c40a0 0x20>; - #power-domain-cells = <0>; - label = "CAM1"; - }; - - pd_aud: power-domain@105c40c0 { - compatible = "samsung,exynos5433-pd"; - reg = <0x105c40c0 0x20>; - #power-domain-cells = <0>; - label = "AUD"; - }; - - pd_g2d: power-domain@105c4120 { - compatible = "samsung,exynos5433-pd"; - reg = <0x105c4120 0x20>; - #power-domain-cells = <0>; - label = "G2D"; - }; - - pd_isp: power-domain@105c4140 { - compatible = "samsung,exynos5433-pd"; - reg = <0x105c4140 0x20>; - #power-domain-cells = <0>; - power-domains = <&pd_cam0>; - label = "ISP"; - }; - - pd_mfc: power-domain@105c4180 { - compatible = "samsung,exynos5433-pd"; - reg = <0x105c4180 0x20>; - #power-domain-cells = <0>; - label = "MFC"; - }; - - pd_hevc: power-domain@105c41c0 { - compatible = "samsung,exynos5433-pd"; - reg = <0x105c41c0 0x20>; - #power-domain-cells = <0>; - label = "HEVC"; - }; - - tmu_atlas0: tmu@10060000 { - compatible = "samsung,exynos5433-tmu"; - reg = <0x10060000 0x200>; - interrupts = ; - clocks = <&cmu_peris CLK_PCLK_TMU0_APBIF>, - <&cmu_peris CLK_SCLK_TMU0>; - clock-names = "tmu_apbif", "tmu_sclk"; - #thermal-sensor-cells = <0>; - status = "disabled"; - }; - - tmu_atlas1: tmu@10068000 { - compatible = "samsung,exynos5433-tmu"; - reg = <0x10068000 0x200>; - interrupts = ; - clocks = <&cmu_peris CLK_PCLK_TMU0_APBIF>, - <&cmu_peris CLK_SCLK_TMU0>; - clock-names = "tmu_apbif", "tmu_sclk"; - #thermal-sensor-cells = <0>; - status = "disabled"; - }; - - tmu_g3d: tmu@10070000 { - compatible = "samsung,exynos5433-tmu"; - reg = <0x10070000 0x200>; - interrupts = ; - clocks = <&cmu_peris CLK_PCLK_TMU1_APBIF>, - <&cmu_peris CLK_SCLK_TMU1>; - clock-names = "tmu_apbif", "tmu_sclk"; - #thermal-sensor-cells = <0>; - status = "disabled"; - }; - - tmu_apollo: tmu@10078000 { - compatible = "samsung,exynos5433-tmu"; - reg = <0x10078000 0x200>; - interrupts = ; - clocks = <&cmu_peris CLK_PCLK_TMU1_APBIF>, - <&cmu_peris CLK_SCLK_TMU1>; - clock-names = "tmu_apbif", "tmu_sclk"; - #thermal-sensor-cells = <0>; - status = "disabled"; - }; - - tmu_isp: tmu@1007c000 { - compatible = "samsung,exynos5433-tmu"; - reg = <0x1007c000 0x200>; - interrupts = ; - clocks = <&cmu_peris CLK_PCLK_TMU1_APBIF>, - <&cmu_peris CLK_SCLK_TMU1>; - clock-names = "tmu_apbif", "tmu_sclk"; - #thermal-sensor-cells = <0>; - status = "disabled"; - }; - - timer@101c0000 { - compatible = "samsung,exynos4210-mct"; - reg = <0x101c0000 0x800>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - ; - clocks = <&xxti>, <&cmu_peris CLK_PCLK_MCT>; - clock-names = "fin_pll", "mct"; - }; - - ppmu_d0_cpu: ppmu@10480000 { - compatible = "samsung,exynos-ppmu-v2"; - reg = <0x10480000 0x2000>; - status = "disabled"; - }; - - ppmu_d0_general: ppmu@10490000 { - compatible = "samsung,exynos-ppmu-v2"; - reg = <0x10490000 0x2000>; - status = "disabled"; - }; - - ppmu_d1_cpu: ppmu@104b0000 { - compatible = "samsung,exynos-ppmu-v2"; - reg = <0x104b0000 0x2000>; - status = "disabled"; - }; - - ppmu_d1_general: ppmu@104c0000 { - compatible = "samsung,exynos-ppmu-v2"; - reg = <0x104c0000 0x2000>; - status = "disabled"; - }; - - pinctrl_alive: pinctrl@10580000 { - compatible = "samsung,exynos5433-pinctrl"; - reg = <0x10580000 0x1a20>, <0x11090000 0x100>; - - wakeup-interrupt-controller { - compatible = "samsung,exynos7-wakeup-eint"; - interrupts = ; - }; - }; - - pinctrl_aud: pinctrl@114b0000 { - compatible = "samsung,exynos5433-pinctrl"; - reg = <0x114b0000 0x1000>; - interrupts = ; - power-domains = <&pd_aud>; - }; - - pinctrl_cpif: pinctrl@10fe0000 { - compatible = "samsung,exynos5433-pinctrl"; - reg = <0x10fe0000 0x1000>; - interrupts = ; - }; - - pinctrl_ese: pinctrl@14ca0000 { - compatible = "samsung,exynos5433-pinctrl"; - reg = <0x14ca0000 0x1000>; - interrupts = ; - }; - - pinctrl_finger: pinctrl@14cb0000 { - compatible = "samsung,exynos5433-pinctrl"; - reg = <0x14cb0000 0x1000>; - interrupts = ; - }; - - pinctrl_fsys: pinctrl@15690000 { - compatible = "samsung,exynos5433-pinctrl"; - reg = <0x15690000 0x1000>; - interrupts = ; - }; - - pinctrl_imem: pinctrl@11090000 { - compatible = "samsung,exynos5433-pinctrl"; - reg = <0x11090000 0x1000>; - interrupts = ; - }; - - pinctrl_nfc: pinctrl@14cd0000 { - compatible = "samsung,exynos5433-pinctrl"; - reg = <0x14cd0000 0x1000>; - interrupts = ; - }; - - pinctrl_peric: pinctrl@14cc0000 { - compatible = "samsung,exynos5433-pinctrl"; - reg = <0x14cc0000 0x1100>; - interrupts = ; - }; - - pinctrl_touch: pinctrl@14ce0000 { - compatible = "samsung,exynos5433-pinctrl"; - reg = <0x14ce0000 0x1100>; - interrupts = ; - }; - - pmu_system_controller: system-controller@105c0000 { - compatible = "samsung,exynos5433-pmu", "syscon"; - reg = <0x105c0000 0x5008>; - #clock-cells = <1>; - clock-names = "clkout16"; - clocks = <&xxti>; - - reboot: syscon-reboot { - compatible = "syscon-reboot"; - regmap = <&pmu_system_controller>; - offset = <0x400>; /* SWRESET */ - mask = <0x1>; - }; - }; - - gic: interrupt-controller@11001000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x11001000 0x1000>, - <0x11002000 0x2000>, - <0x11004000 0x2000>, - <0x11006000 0x2000>; - interrupts = ; - }; - - mipi_phy: video-phy { - compatible = "samsung,exynos5433-mipi-video-phy"; - #phy-cells = <1>; - samsung,pmu-syscon = <&pmu_system_controller>; - samsung,cam0-sysreg = <&syscon_cam0>; - samsung,cam1-sysreg = <&syscon_cam1>; - samsung,disp-sysreg = <&syscon_disp>; - }; - - decon: decon@13800000 { - compatible = "samsung,exynos5433-decon"; - reg = <0x13800000 0x2104>; - clocks = <&cmu_disp CLK_PCLK_DECON>, - <&cmu_disp CLK_ACLK_DECON>, - <&cmu_disp CLK_ACLK_SMMU_DECON0X>, - <&cmu_disp CLK_ACLK_XIU_DECON0X>, - <&cmu_disp CLK_PCLK_SMMU_DECON0X>, - <&cmu_disp CLK_ACLK_SMMU_DECON1X>, - <&cmu_disp CLK_ACLK_XIU_DECON1X>, - <&cmu_disp CLK_PCLK_SMMU_DECON1X>, - <&cmu_disp CLK_SCLK_DECON_VCLK>, - <&cmu_disp CLK_SCLK_DECON_ECLK>, - <&cmu_disp CLK_SCLK_DSD>; - clock-names = "pclk", "aclk_decon", "aclk_smmu_decon0x", - "aclk_xiu_decon0x", "pclk_smmu_decon0x", - "aclk_smmu_decon1x", "aclk_xiu_decon1x", - "pclk_smmu_decon1x", "sclk_decon_vclk", - "sclk_decon_eclk", "dsd"; - power-domains = <&pd_disp>; - interrupt-names = "fifo", "vsync", "lcd_sys"; - interrupts = , - , - ; - samsung,disp-sysreg = <&syscon_disp>; - status = "disabled"; - iommus = <&sysmmu_decon0x>, <&sysmmu_decon1x>; - iommu-names = "m0", "m1"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - decon_to_mic: endpoint { - remote-endpoint = - <&mic_to_decon>; - }; - }; - }; - }; - - decon_tv: decon@13880000 { - compatible = "samsung,exynos5433-decon-tv"; - reg = <0x13880000 0x20b8>; - clocks = <&cmu_disp CLK_PCLK_DECON_TV>, - <&cmu_disp CLK_ACLK_DECON_TV>, - <&cmu_disp CLK_ACLK_SMMU_TV0X>, - <&cmu_disp CLK_ACLK_XIU_TV0X>, - <&cmu_disp CLK_PCLK_SMMU_TV0X>, - <&cmu_disp CLK_ACLK_SMMU_TV1X>, - <&cmu_disp CLK_ACLK_XIU_TV1X>, - <&cmu_disp CLK_PCLK_SMMU_TV1X>, - <&cmu_disp CLK_SCLK_DECON_TV_VCLK>, - <&cmu_disp CLK_SCLK_DECON_TV_ECLK>, - <&cmu_disp CLK_SCLK_DSD>; - clock-names = "pclk", "aclk_decon", "aclk_smmu_decon0x", - "aclk_xiu_decon0x", "pclk_smmu_decon0x", - "aclk_smmu_decon1x", "aclk_xiu_decon1x", - "pclk_smmu_decon1x", "sclk_decon_vclk", - "sclk_decon_eclk", "dsd"; - samsung,disp-sysreg = <&syscon_disp>; - power-domains = <&pd_disp>; - interrupt-names = "fifo", "vsync", "lcd_sys"; - interrupts = , - , - ; - status = "disabled"; - iommus = <&sysmmu_tv0x>, <&sysmmu_tv1x>; - iommu-names = "m0", "m1"; - }; - - dsi: dsi@13900000 { - compatible = "samsung,exynos5433-mipi-dsi"; - reg = <0x13900000 0xC0>; - interrupts = ; - phys = <&mipi_phy 1>; - phy-names = "dsim"; - clocks = <&cmu_disp CLK_PCLK_DSIM0>, - <&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8>, - <&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0>, - <&cmu_disp CLK_SCLK_RGB_VCLK_TO_DSIM0>, - <&cmu_disp CLK_SCLK_DSIM0>; - clock-names = "bus_clk", - "phyclk_mipidphy0_bitclkdiv8", - "phyclk_mipidphy0_rxclkesc0", - "sclk_rgb_vclk_to_dsim0", - "sclk_mipi"; - power-domains = <&pd_disp>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dsi_to_mic: endpoint { - remote-endpoint = <&mic_to_dsi>; - }; - }; - }; - }; - - mic: mic@13930000 { - compatible = "samsung,exynos5433-mic"; - reg = <0x13930000 0x48>; - clocks = <&cmu_disp CLK_PCLK_MIC0>, - <&cmu_disp CLK_SCLK_RGB_VCLK_TO_MIC0>; - clock-names = "pclk_mic0", "sclk_rgb_vclk_to_mic0"; - power-domains = <&pd_disp>; - samsung,disp-syscon = <&syscon_disp>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - mic_to_decon: endpoint { - remote-endpoint = - <&decon_to_mic>; - }; - }; - - port@1 { - reg = <1>; - mic_to_dsi: endpoint { - remote-endpoint = <&dsi_to_mic>; - }; - }; - }; - }; - - hdmi: hdmi@13970000 { - compatible = "samsung,exynos5433-hdmi"; - reg = <0x13970000 0x70000>; - interrupts = ; - clocks = <&cmu_disp CLK_PCLK_HDMI>, - <&cmu_disp CLK_PCLK_HDMIPHY>, - <&cmu_disp CLK_PHYCLK_HDMIPHY_TMDS_CLKO>, - <&cmu_disp CLK_PHYCLK_HDMI_PIXEL>, - <&cmu_disp CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY>, - <&cmu_disp CLK_MOUT_PHYCLK_HDMIPHY_TMDS_CLKO_USER>, - <&cmu_disp CLK_PHYCLK_HDMIPHY_PIXEL_CLKO_PHY>, - <&cmu_disp CLK_MOUT_PHYCLK_HDMIPHY_PIXEL_CLKO_USER>, - <&xxti>, <&cmu_disp CLK_SCLK_HDMI_SPDIF>; - clock-names = "hdmi_pclk", "hdmi_i_pclk", - "i_tmds_clk", "i_pixel_clk", - "tmds_clko", "tmds_clko_user", - "pixel_clko", "pixel_clko_user", - "oscclk", "i_spdif_clk"; - phy = <&hdmiphy>; - ddc = <&hsi2c_11>; - samsung,syscon-phandle = <&pmu_system_controller>; - samsung,sysreg-phandle = <&syscon_disp>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - hdmiphy: hdmiphy@13af0000 { - reg = <0x13af0000 0x80>; - }; - - syscon_disp: syscon@13b80000 { - compatible = "syscon"; - reg = <0x13b80000 0x1010>; - }; - - syscon_cam0: syscon@120f0000 { - compatible = "syscon"; - reg = <0x120f0000 0x1020>; - }; - - syscon_cam1: syscon@145f0000 { - compatible = "syscon"; - reg = <0x145f0000 0x1038>; - }; - - gsc_0: video-scaler@13c00000 { - compatible = "samsung,exynos5433-gsc"; - reg = <0x13c00000 0x1000>; - interrupts = ; - clock-names = "pclk", "aclk", "aclk_xiu", - "aclk_gsclbend", "gsd"; - clocks = <&cmu_gscl CLK_PCLK_GSCL0>, - <&cmu_gscl CLK_ACLK_GSCL0>, - <&cmu_gscl CLK_ACLK_XIU_GSCLX>, - <&cmu_gscl CLK_ACLK_GSCLBEND_333>, - <&cmu_gscl CLK_ACLK_GSD>; - iommus = <&sysmmu_gscl0>; - power-domains = <&pd_gscl>; - }; - - gsc_1: video-scaler@13c10000 { - compatible = "samsung,exynos5433-gsc"; - reg = <0x13c10000 0x1000>; - interrupts = ; - clock-names = "pclk", "aclk", "aclk_xiu", - "aclk_gsclbend", "gsd"; - clocks = <&cmu_gscl CLK_PCLK_GSCL1>, - <&cmu_gscl CLK_ACLK_GSCL1>, - <&cmu_gscl CLK_ACLK_XIU_GSCLX>, - <&cmu_gscl CLK_ACLK_GSCLBEND_333>, - <&cmu_gscl CLK_ACLK_GSD>; - iommus = <&sysmmu_gscl1>; - power-domains = <&pd_gscl>; - }; - - gsc_2: video-scaler@13c20000 { - compatible = "samsung,exynos5433-gsc"; - reg = <0x13c20000 0x1000>; - interrupts = ; - clock-names = "pclk", "aclk", "aclk_xiu", - "aclk_gsclbend", "gsd"; - clocks = <&cmu_gscl CLK_PCLK_GSCL2>, - <&cmu_gscl CLK_ACLK_GSCL2>, - <&cmu_gscl CLK_ACLK_XIU_GSCLX>, - <&cmu_gscl CLK_ACLK_GSCLBEND_333>, - <&cmu_gscl CLK_ACLK_GSD>; - iommus = <&sysmmu_gscl2>; - power-domains = <&pd_gscl>; - }; - - gpu: gpu@14ac0000 { - compatible = "samsung,exynos5433-mali", "arm,mali-t760"; - reg = <0x14ac0000 0x5000>; - interrupts = , - , - ; - interrupt-names = "job", "mmu", "gpu"; - clocks = <&cmu_g3d CLK_ACLK_G3D>; - clock-names = "core"; - power-domains = <&pd_g3d>; - operating-points-v2 = <&gpu_opp_table>; - status = "disabled"; - - gpu_opp_table: opp_table { - compatible = "operating-points-v2"; - - opp-160000000 { - opp-hz = /bits/ 64 <160000000>; - opp-microvolt = <1000000>; - }; - opp-267000000 { - opp-hz = /bits/ 64 <267000000>; - opp-microvolt = <1000000>; - }; - opp-350000000 { - opp-hz = /bits/ 64 <350000000>; - opp-microvolt = <1025000>; - }; - opp-420000000 { - opp-hz = /bits/ 64 <420000000>; - opp-microvolt = <1025000>; - }; - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <1075000>; - }; - opp-550000000 { - opp-hz = /bits/ 64 <550000000>; - opp-microvolt = <1125000>; - }; - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <1150000>; - }; - opp-700000000 { - opp-hz = /bits/ 64 <700000000>; - opp-microvolt = <1150000>; - }; - }; - }; - - scaler_0: scaler@15000000 { - compatible = "samsung,exynos5433-scaler"; - reg = <0x15000000 0x1294>; - interrupts = <0 402 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "pclk", "aclk", "aclk_xiu"; - clocks = <&cmu_mscl CLK_PCLK_M2MSCALER0>, - <&cmu_mscl CLK_ACLK_M2MSCALER0>, - <&cmu_mscl CLK_ACLK_XIU_MSCLX>; - iommus = <&sysmmu_scaler_0>; - power-domains = <&pd_mscl>; - }; - - scaler_1: scaler@15010000 { - compatible = "samsung,exynos5433-scaler"; - reg = <0x15010000 0x1294>; - interrupts = <0 403 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "pclk", "aclk", "aclk_xiu"; - clocks = <&cmu_mscl CLK_PCLK_M2MSCALER1>, - <&cmu_mscl CLK_ACLK_M2MSCALER1>, - <&cmu_mscl CLK_ACLK_XIU_MSCLX>; - iommus = <&sysmmu_scaler_1>; - power-domains = <&pd_mscl>; - }; - - jpeg: codec@15020000 { - compatible = "samsung,exynos5433-jpeg"; - reg = <0x15020000 0x10000>; - interrupts = ; - clock-names = "pclk", "aclk", "aclk_xiu", "sclk"; - clocks = <&cmu_mscl CLK_PCLK_JPEG>, - <&cmu_mscl CLK_ACLK_JPEG>, - <&cmu_mscl CLK_ACLK_XIU_MSCLX>, - <&cmu_mscl CLK_SCLK_JPEG>; - iommus = <&sysmmu_jpeg>; - power-domains = <&pd_mscl>; - }; - - mfc: codec@152e0000 { - compatible = "samsung,exynos5433-mfc"; - reg = <0x152E0000 0x10000>; - interrupts = ; - clock-names = "pclk", "aclk", "aclk_xiu"; - clocks = <&cmu_mfc CLK_PCLK_MFC>, - <&cmu_mfc CLK_ACLK_MFC>, - <&cmu_mfc CLK_ACLK_XIU_MFCX>; - iommus = <&sysmmu_mfc_0>, <&sysmmu_mfc_1>; - iommu-names = "left", "right"; - power-domains = <&pd_mfc>; - }; - - sysmmu_decon0x: sysmmu@13a00000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x13a00000 0x1000>; - interrupts = ; - clock-names = "aclk", "pclk"; - clocks = <&cmu_disp CLK_ACLK_SMMU_DECON0X>, - <&cmu_disp CLK_PCLK_SMMU_DECON0X>; - power-domains = <&pd_disp>; - #iommu-cells = <0>; - }; - - sysmmu_decon1x: sysmmu@13a10000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x13a10000 0x1000>; - interrupts = ; - clock-names = "aclk", "pclk"; - clocks = <&cmu_disp CLK_ACLK_SMMU_DECON1X>, - <&cmu_disp CLK_PCLK_SMMU_DECON1X>; - #iommu-cells = <0>; - power-domains = <&pd_disp>; - }; - - sysmmu_tv0x: sysmmu@13a20000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x13a20000 0x1000>; - interrupts = ; - clock-names = "aclk", "pclk"; - clocks = <&cmu_disp CLK_ACLK_SMMU_TV0X>, - <&cmu_disp CLK_PCLK_SMMU_TV0X>; - #iommu-cells = <0>; - power-domains = <&pd_disp>; - }; - - sysmmu_tv1x: sysmmu@13a30000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x13a30000 0x1000>; - interrupts = ; - clock-names = "aclk", "pclk"; - clocks = <&cmu_disp CLK_ACLK_SMMU_TV1X>, - <&cmu_disp CLK_PCLK_SMMU_TV1X>; - #iommu-cells = <0>; - power-domains = <&pd_disp>; - }; - - sysmmu_gscl0: sysmmu@13c80000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x13C80000 0x1000>; - interrupts = ; - clock-names = "aclk", "pclk"; - clocks = <&cmu_gscl CLK_ACLK_SMMU_GSCL0>, - <&cmu_gscl CLK_PCLK_SMMU_GSCL0>; - #iommu-cells = <0>; - power-domains = <&pd_gscl>; - }; - - sysmmu_gscl1: sysmmu@13c90000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x13C90000 0x1000>; - interrupts = ; - clock-names = "aclk", "pclk"; - clocks = <&cmu_gscl CLK_ACLK_SMMU_GSCL1>, - <&cmu_gscl CLK_PCLK_SMMU_GSCL1>; - #iommu-cells = <0>; - power-domains = <&pd_gscl>; - }; - - sysmmu_gscl2: sysmmu@13ca0000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x13CA0000 0x1000>; - interrupts = ; - clock-names = "aclk", "pclk"; - clocks = <&cmu_gscl CLK_ACLK_SMMU_GSCL2>, - <&cmu_gscl CLK_PCLK_SMMU_GSCL2>; - #iommu-cells = <0>; - power-domains = <&pd_gscl>; - }; - - sysmmu_scaler_0: sysmmu@15040000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x15040000 0x1000>; - interrupts = ; - clock-names = "aclk", "pclk"; - clocks = <&cmu_mscl CLK_ACLK_SMMU_M2MSCALER0>, - <&cmu_mscl CLK_PCLK_SMMU_M2MSCALER0>; - #iommu-cells = <0>; - power-domains = <&pd_mscl>; - }; - - sysmmu_scaler_1: sysmmu@15050000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x15050000 0x1000>; - interrupts = ; - clock-names = "aclk", "pclk"; - clocks = <&cmu_mscl CLK_ACLK_SMMU_M2MSCALER1>, - <&cmu_mscl CLK_PCLK_SMMU_M2MSCALER1>; - #iommu-cells = <0>; - power-domains = <&pd_mscl>; - }; - - sysmmu_jpeg: sysmmu@15060000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x15060000 0x1000>; - interrupts = ; - clock-names = "aclk", "pclk"; - clocks = <&cmu_mscl CLK_ACLK_SMMU_JPEG>, - <&cmu_mscl CLK_PCLK_SMMU_JPEG>; - #iommu-cells = <0>; - power-domains = <&pd_mscl>; - }; - - sysmmu_mfc_0: sysmmu@15200000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x15200000 0x1000>; - interrupts = ; - clock-names = "aclk", "pclk"; - clocks = <&cmu_mfc CLK_ACLK_SMMU_MFC_0>, - <&cmu_mfc CLK_PCLK_SMMU_MFC_0>; - #iommu-cells = <0>; - power-domains = <&pd_mfc>; - }; - - sysmmu_mfc_1: sysmmu@15210000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x15210000 0x1000>; - interrupts = ; - clock-names = "aclk", "pclk"; - clocks = <&cmu_mfc CLK_ACLK_SMMU_MFC_1>, - <&cmu_mfc CLK_PCLK_SMMU_MFC_1>; - #iommu-cells = <0>; - power-domains = <&pd_mfc>; - }; - - serial_0: serial@14c10000 { - compatible = "samsung,exynos5433-uart"; - reg = <0x14c10000 0x100>; - interrupts = ; - clocks = <&cmu_peric CLK_PCLK_UART0>, - <&cmu_peric CLK_SCLK_UART0>; - clock-names = "uart", "clk_uart_baud0"; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_bus>; - status = "disabled"; - }; - - serial_1: serial@14c20000 { - compatible = "samsung,exynos5433-uart"; - reg = <0x14c20000 0x100>; - interrupts = ; - clocks = <&cmu_peric CLK_PCLK_UART1>, - <&cmu_peric CLK_SCLK_UART1>; - clock-names = "uart", "clk_uart_baud0"; - pinctrl-names = "default"; - pinctrl-0 = <&uart1_bus>; - status = "disabled"; - }; - - serial_2: serial@14c30000 { - compatible = "samsung,exynos5433-uart"; - reg = <0x14c30000 0x100>; - interrupts = ; - clocks = <&cmu_peric CLK_PCLK_UART2>, - <&cmu_peric CLK_SCLK_UART2>; - clock-names = "uart", "clk_uart_baud0"; - pinctrl-names = "default"; - pinctrl-0 = <&uart2_bus>; - status = "disabled"; - }; - - spi_0: spi@14d20000 { - compatible = "samsung,exynos5433-spi"; - reg = <0x14d20000 0x100>; - interrupts = ; - dmas = <&pdma0 9>, <&pdma0 8>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cmu_peric CLK_PCLK_SPI0>, - <&cmu_peric CLK_SCLK_SPI0>, - <&cmu_peric CLK_SCLK_IOCLK_SPI0>; - clock-names = "spi", "spi_busclk0", "spi_ioclk"; - samsung,spi-src-clk = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_bus>; - num-cs = <1>; - status = "disabled"; - }; - - spi_1: spi@14d30000 { - compatible = "samsung,exynos5433-spi"; - reg = <0x14d30000 0x100>; - interrupts = ; - dmas = <&pdma0 11>, <&pdma0 10>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cmu_peric CLK_PCLK_SPI1>, - <&cmu_peric CLK_SCLK_SPI1>, - <&cmu_peric CLK_SCLK_IOCLK_SPI1>; - clock-names = "spi", "spi_busclk0", "spi_ioclk"; - samsung,spi-src-clk = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&spi1_bus>; - num-cs = <1>; - status = "disabled"; - }; - - spi_2: spi@14d40000 { - compatible = "samsung,exynos5433-spi"; - reg = <0x14d40000 0x100>; - interrupts = ; - dmas = <&pdma0 13>, <&pdma0 12>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cmu_peric CLK_PCLK_SPI2>, - <&cmu_peric CLK_SCLK_SPI2>, - <&cmu_peric CLK_SCLK_IOCLK_SPI2>; - clock-names = "spi", "spi_busclk0", "spi_ioclk"; - samsung,spi-src-clk = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&spi2_bus>; - num-cs = <1>; - status = "disabled"; - }; - - spi_3: spi@14d50000 { - compatible = "samsung,exynos5433-spi"; - reg = <0x14d50000 0x100>; - interrupts = ; - dmas = <&pdma0 23>, <&pdma0 22>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cmu_peric CLK_PCLK_SPI3>, - <&cmu_peric CLK_SCLK_SPI3>, - <&cmu_peric CLK_SCLK_IOCLK_SPI3>; - clock-names = "spi", "spi_busclk0", "spi_ioclk"; - samsung,spi-src-clk = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&spi3_bus>; - num-cs = <1>; - status = "disabled"; - }; - - spi_4: spi@14d00000 { - compatible = "samsung,exynos5433-spi"; - reg = <0x14d00000 0x100>; - interrupts = ; - dmas = <&pdma0 25>, <&pdma0 24>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cmu_peric CLK_PCLK_SPI4>, - <&cmu_peric CLK_SCLK_SPI4>, - <&cmu_peric CLK_SCLK_IOCLK_SPI4>; - clock-names = "spi", "spi_busclk0", "spi_ioclk"; - samsung,spi-src-clk = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&spi4_bus>; - num-cs = <1>; - status = "disabled"; - }; - - adc: adc@14d10000 { - compatible = "samsung,exynos7-adc"; - reg = <0x14d10000 0x100>; - interrupts = ; - clock-names = "adc"; - clocks = <&cmu_peric CLK_PCLK_ADCIF>; - #io-channel-cells = <1>; - io-channel-ranges; - status = "disabled"; - }; - - i2s1: i2s@14d60000 { - compatible = "samsung,exynos7-i2s"; - reg = <0x14d60000 0x100>; - dmas = <&pdma0 31>, <&pdma0 30>; - dma-names = "tx", "rx"; - interrupts = ; - clocks = <&cmu_peric CLK_PCLK_I2S1>, - <&cmu_peric CLK_PCLK_I2S1>, - <&cmu_peric CLK_SCLK_I2S1>; - clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; - #clock-cells = <1>; - samsung,supports-6ch; - samsung,supports-rstclr; - samsung,supports-tdm; - samsung,supports-low-rfs; - #sound-dai-cells = <1>; - status = "disabled"; - }; - - pwm: pwm@14dd0000 { - compatible = "samsung,exynos4210-pwm"; - reg = <0x14dd0000 0x100>; - interrupts = , - , - , - , - ; - samsung,pwm-outputs = <0>, <1>, <2>, <3>; - clocks = <&cmu_peric CLK_PCLK_PWM>; - clock-names = "timers"; - #pwm-cells = <3>; - status = "disabled"; - }; - - hsi2c_0: hsi2c@14e40000 { - compatible = "samsung,exynos7-hsi2c"; - reg = <0x14e40000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&hs_i2c0_bus>; - clocks = <&cmu_peric CLK_PCLK_HSI2C0>; - clock-names = "hsi2c"; - status = "disabled"; - }; - - hsi2c_1: hsi2c@14e50000 { - compatible = "samsung,exynos7-hsi2c"; - reg = <0x14e50000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&hs_i2c1_bus>; - clocks = <&cmu_peric CLK_PCLK_HSI2C1>; - clock-names = "hsi2c"; - status = "disabled"; - }; - - hsi2c_2: hsi2c@14e60000 { - compatible = "samsung,exynos7-hsi2c"; - reg = <0x14e60000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&hs_i2c2_bus>; - clocks = <&cmu_peric CLK_PCLK_HSI2C2>; - clock-names = "hsi2c"; - status = "disabled"; - }; - - hsi2c_3: hsi2c@14e70000 { - compatible = "samsung,exynos7-hsi2c"; - reg = <0x14e70000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&hs_i2c3_bus>; - clocks = <&cmu_peric CLK_PCLK_HSI2C3>; - clock-names = "hsi2c"; - status = "disabled"; - }; - - hsi2c_4: hsi2c@14ec0000 { - compatible = "samsung,exynos7-hsi2c"; - reg = <0x14ec0000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&hs_i2c4_bus>; - clocks = <&cmu_peric CLK_PCLK_HSI2C4>; - clock-names = "hsi2c"; - status = "disabled"; - }; - - hsi2c_5: hsi2c@14ed0000 { - compatible = "samsung,exynos7-hsi2c"; - reg = <0x14ed0000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&hs_i2c5_bus>; - clocks = <&cmu_peric CLK_PCLK_HSI2C5>; - clock-names = "hsi2c"; - status = "disabled"; - }; - - hsi2c_6: hsi2c@14ee0000 { - compatible = "samsung,exynos7-hsi2c"; - reg = <0x14ee0000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&hs_i2c6_bus>; - clocks = <&cmu_peric CLK_PCLK_HSI2C6>; - clock-names = "hsi2c"; - status = "disabled"; - }; - - hsi2c_7: hsi2c@14ef0000 { - compatible = "samsung,exynos7-hsi2c"; - reg = <0x14ef0000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&hs_i2c7_bus>; - clocks = <&cmu_peric CLK_PCLK_HSI2C7>; - clock-names = "hsi2c"; - status = "disabled"; - }; - - hsi2c_8: hsi2c@14d90000 { - compatible = "samsung,exynos7-hsi2c"; - reg = <0x14d90000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&hs_i2c8_bus>; - clocks = <&cmu_peric CLK_PCLK_HSI2C8>; - clock-names = "hsi2c"; - status = "disabled"; - }; - - hsi2c_9: hsi2c@14da0000 { - compatible = "samsung,exynos7-hsi2c"; - reg = <0x14da0000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&hs_i2c9_bus>; - clocks = <&cmu_peric CLK_PCLK_HSI2C9>; - clock-names = "hsi2c"; - status = "disabled"; - }; - - hsi2c_10: hsi2c@14de0000 { - compatible = "samsung,exynos7-hsi2c"; - reg = <0x14de0000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&hs_i2c10_bus>; - clocks = <&cmu_peric CLK_PCLK_HSI2C10>; - clock-names = "hsi2c"; - status = "disabled"; - }; - - hsi2c_11: hsi2c@14df0000 { - compatible = "samsung,exynos7-hsi2c"; - reg = <0x14df0000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&hs_i2c11_bus>; - clocks = <&cmu_peric CLK_PCLK_HSI2C11>; - clock-names = "hsi2c"; - status = "disabled"; - }; - - usbdrd30: usbdrd { - compatible = "samsung,exynos5433-dwusb3"; - clocks = <&cmu_fsys CLK_ACLK_USBDRD30>, - <&cmu_fsys CLK_SCLK_USBDRD30>, - <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK>, - <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK>; - clock-names = "aclk", "susp_clk", "phyclk", "pipe_pclk"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - status = "disabled"; - - usbdrd_dwc3: dwc3@15400000 { - compatible = "snps,dwc3"; - clocks = <&cmu_fsys CLK_SCLK_USBDRD30>, - <&cmu_fsys CLK_ACLK_USBDRD30>, - <&cmu_fsys CLK_SCLK_USBDRD30>; - clock-names = "ref", "bus_early", "suspend"; - reg = <0x15400000 0x10000>; - interrupts = ; - phys = <&usbdrd30_phy 0>, <&usbdrd30_phy 1>; - phy-names = "usb2-phy", "usb3-phy"; - }; - }; - - usbdrd30_phy: phy@15500000 { - compatible = "samsung,exynos5433-usbdrd-phy"; - reg = <0x15500000 0x100>; - clocks = <&cmu_fsys CLK_ACLK_USBDRD30>, <&xxti>, - <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK>, - <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK>, - <&cmu_fsys CLK_SCLK_USBDRD30>; - clock-names = "phy", "ref", "phy_utmi", "phy_pipe", - "itp"; - #phy-cells = <1>; - samsung,pmu-syscon = <&pmu_system_controller>; - status = "disabled"; - }; - - usbhost30_phy: phy@15580000 { - compatible = "samsung,exynos5433-usbdrd-phy"; - reg = <0x15580000 0x100>; - clocks = <&cmu_fsys CLK_ACLK_USBHOST30>, <&xxti>, - <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK>, - <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK>, - <&cmu_fsys CLK_SCLK_USBHOST30>; - clock-names = "phy", "ref", "phy_utmi", "phy_pipe", - "itp"; - #phy-cells = <1>; - samsung,pmu-syscon = <&pmu_system_controller>; - status = "disabled"; - }; - - usbhost30: usbhost { - compatible = "samsung,exynos5433-dwusb3"; - clocks = <&cmu_fsys CLK_ACLK_USBHOST30>, - <&cmu_fsys CLK_SCLK_USBHOST30>, - <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK>, - <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK>; - clock-names = "aclk", "susp_clk", "phyclk", "pipe_pclk"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - status = "disabled"; - - usbhost_dwc3: dwc3@15a00000 { - compatible = "snps,dwc3"; - clocks = <&cmu_fsys CLK_SCLK_USBHOST30>, - <&cmu_fsys CLK_ACLK_USBHOST30>, - <&cmu_fsys CLK_SCLK_USBHOST30>; - clock-names = "ref", "bus_early", "suspend"; - reg = <0x15a00000 0x10000>; - interrupts = ; - phys = <&usbhost30_phy 0>, <&usbhost30_phy 1>; - phy-names = "usb2-phy", "usb3-phy"; - }; - }; - - mshc_0: mshc@15540000 { - compatible = "samsung,exynos7-dw-mshc-smu"; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x15540000 0x2000>; - clocks = <&cmu_fsys CLK_ACLK_MMC0>, - <&cmu_fsys CLK_SCLK_MMC0>; - clock-names = "biu", "ciu"; - fifo-depth = <0x40>; - status = "disabled"; - }; - - mshc_1: mshc@15550000 { - compatible = "samsung,exynos7-dw-mshc-smu"; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x15550000 0x2000>; - clocks = <&cmu_fsys CLK_ACLK_MMC1>, - <&cmu_fsys CLK_SCLK_MMC1>; - clock-names = "biu", "ciu"; - fifo-depth = <0x40>; - status = "disabled"; - }; - - mshc_2: mshc@15560000 { - compatible = "samsung,exynos7-dw-mshc-smu"; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x15560000 0x2000>; - clocks = <&cmu_fsys CLK_ACLK_MMC2>, - <&cmu_fsys CLK_SCLK_MMC2>; - clock-names = "biu", "ciu"; - fifo-depth = <0x40>; - status = "disabled"; - }; - - amba { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - pdma0: pdma@15610000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x15610000 0x1000>; - interrupts = ; - clocks = <&cmu_fsys CLK_PDMA0>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; - }; - - pdma1: pdma@15600000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x15600000 0x1000>; - interrupts = ; - clocks = <&cmu_fsys CLK_PDMA1>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; - }; - }; - - audio-subsystem@11400000 { - compatible = "samsung,exynos5433-lpass"; - reg = <0x11400000 0x100>, <0x11500000 0x08>; - clocks = <&cmu_aud CLK_PCLK_SFR0_CTRL>; - clock-names = "sfr0_ctrl"; - samsung,pmu-syscon = <&pmu_system_controller>; - power-domains = <&pd_aud>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - adma: adma@11420000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x11420000 0x1000>; - interrupts = ; - clocks = <&cmu_aud CLK_ACLK_DMAC>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; - power-domains = <&pd_aud>; - }; - - i2s0: i2s@11440000 { - compatible = "samsung,exynos7-i2s"; - reg = <0x11440000 0x100>; - dmas = <&adma 0>, <&adma 2>; - dma-names = "tx", "rx"; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cmu_aud CLK_PCLK_AUD_I2S>, - <&cmu_aud CLK_SCLK_AUD_I2S>, - <&cmu_aud CLK_SCLK_I2S_BCLK>; - clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; - #clock-cells = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_bus>; - power-domains = <&pd_aud>; - #sound-dai-cells = <1>; - status = "disabled"; - }; - - serial_3: serial@11460000 { - compatible = "samsung,exynos5433-uart"; - reg = <0x11460000 0x100>; - interrupts = ; - clocks = <&cmu_aud CLK_PCLK_AUD_UART>, - <&cmu_aud CLK_SCLK_AUD_UART>; - clock-names = "uart", "clk_uart_baud0"; - pinctrl-names = "default"; - pinctrl-0 = <&uart_aud_bus>; - power-domains = <&pd_aud>; - status = "disabled"; - }; - }; - }; - - timer: timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; -}; - -#include "exynos5433-bus.dtsi" -#include "exynos5433-pinctrl.dtsi" -#include "exynos5433-tmu.dtsi" diff --git a/sys/gnu/dts/arm64/exynos/exynos7-espresso.dts b/sys/gnu/dts/arm64/exynos/exynos7-espresso.dts deleted file mode 100644 index 7af288fa947..00000000000 --- a/sys/gnu/dts/arm64/exynos/exynos7-espresso.dts +++ /dev/null @@ -1,412 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung Exynos7 Espresso board device tree source - * - * Copyright (c) 2014 Samsung Electronics Co., Ltd. - * http://www.samsung.com - */ - -/dts-v1/; -#include "exynos7.dtsi" -#include -#include -#include - -/ { - model = "Samsung Exynos7 Espresso board based on Exynos7"; - compatible = "samsung,exynos7-espresso", "samsung,exynos7"; - - aliases { - serial0 = &serial_2; - mshc0 = &mmc_0; - mshc2 = &mmc_2; - }; - - chosen { - stdout-path = &serial_2; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x0 0x40000000 0x0 0xC0000000>; - }; - - usb30_vbus_reg: regulator-usb30 { - compatible = "regulator-fixed"; - regulator-name = "VBUS_5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gph1 1 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&usb30_vbus_en>; - enable-active-high; - }; - - usb3drd_boost_5v: regulator-usb3drd-boost { - compatible = "regulator-fixed"; - regulator-name = "VUSB_VBUS_5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpf4 1 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&usb3drd_boost_en>; - enable-active-high; - }; - -}; - -&fin_pll { - clock-frequency = <24000000>; -}; - -&gpu { - mali-supply = <&buck6_reg>; - status = "okay"; -}; - -&serial_2 { - status = "okay"; -}; - -&rtc { - status = "okay"; - clocks = <&clock_ccore PCLK_RTC>, <&s2mps15_osc S2MPS11_CLK_AP>; - clock-names = "rtc", "rtc_src"; -}; - -&watchdog { - status = "okay"; -}; - -&adc { - status = "okay"; -}; - -&hsi2c_4 { - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <200000>; - status = "okay"; - - s2mps15_pmic@66 { - compatible = "samsung,s2mps15-pmic"; - reg = <0x66>; - interrupts = <2 IRQ_TYPE_NONE>; - interrupt-parent = <&gpa0>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_irq>; - wakeup-source; - - s2mps15_osc: clocks { - compatible = "samsung,s2mps13-clk"; - #clock-cells = <1>; - clock-output-names = "s2mps13_ap", "s2mps13_cp", - "s2mps13_bt"; - }; - - regulators { - ldo1_reg: LDO1 { - regulator-name = "vdd_ldo1"; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <900000>; - regulator-always-on; - regulator-enable-ramp-delay = <125>; - }; - - ldo2_reg: LDO2 { - regulator-name = "vqmmc-sdcard"; - regulator-min-microvolt = <1620000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-enable-ramp-delay = <125>; - }; - - ldo3_reg: LDO3 { - regulator-name = "vdd_ldo3"; - regulator-min-microvolt = <1620000>; - regulator-max-microvolt = <1980000>; - regulator-always-on; - regulator-boot-on; - regulator-enable-ramp-delay = <125>; - }; - - ldo4_reg: LDO4 { - regulator-name = "vdd_ldo4"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1110000>; - regulator-always-on; - regulator-enable-ramp-delay = <125>; - }; - - ldo5_reg: LDO5 { - regulator-name = "vdd_ldo5"; - regulator-min-microvolt = <1620000>; - regulator-max-microvolt = <1980000>; - regulator-always-on; - regulator-enable-ramp-delay = <125>; - }; - - ldo6_reg: LDO6 { - regulator-name = "vdd_ldo6"; - regulator-min-microvolt = <2250000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <125>; - }; - - ldo7_reg: LDO7 { - regulator-name = "vdd_ldo7"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1150000>; - regulator-enable-ramp-delay = <125>; - }; - - ldo8_reg: LDO8 { - regulator-name = "vdd_ldo8"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1000000>; - regulator-enable-ramp-delay = <125>; - }; - - ldo9_reg: LDO9 { - regulator-name = "vdd_ldo9"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1000000>; - regulator-enable-ramp-delay = <125>; - }; - - ldo10_reg: LDO10 { - regulator-name = "vdd_ldo10"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1000000>; - regulator-enable-ramp-delay = <125>; - }; - - ldo11_reg: LDO11 { - regulator-name = "vdd_ldo11"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-enable-ramp-delay = <125>; - }; - - ldo12_reg: LDO12 { - regulator-name = "vdd_ldo12"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1300000>; - regulator-enable-ramp-delay = <125>; - }; - - ldo13_reg: LDO13 { - regulator-name = "vdd_ldo13"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-enable-ramp-delay = <125>; - }; - - ldo14_reg: LDO14 { - regulator-name = "vdd_ldo14"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3375000>; - regulator-enable-ramp-delay = <125>; - }; - - ldo17_reg: LDO17 { - regulator-name = "vmmc-sdcard"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3375000>; - regulator-enable-ramp-delay = <125>; - }; - - ldo18_reg: LDO18 { - regulator-name = "vdd_ldo18"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <2275000>; - regulator-enable-ramp-delay = <125>; - }; - - ldo19_reg: LDO19 { - regulator-name = "vdd_ldo19"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3375000>; - regulator-enable-ramp-delay = <125>; - }; - - ldo21_reg: LDO21 { - regulator-name = "vdd_ldo21"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3375000>; - regulator-enable-ramp-delay = <125>; - }; - - ldo23_reg: LDO23 { - regulator-name = "vdd_ldo23"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <2275000>; - regulator-enable-ramp-delay = <125>; - }; - - ldo25_reg: LDO25 { - regulator-name = "vdd_ldo25"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3375000>; - regulator-enable-ramp-delay = <125>; - }; - - ldo26_reg: LDO26 { - regulator-name = "vdd_ldo26"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1470000>; - regulator-enable-ramp-delay = <125>; - }; - - ldo27_reg: LDO27 { - regulator-name = "vdd_ldo27"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <2275000>; - regulator-enable-ramp-delay = <125>; - }; - - buck1_reg: BUCK1 { - regulator-name = "vdd_mif"; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - regulator-ramp-delay = <25000>; - regulator-enable-ramp-delay = <250>; - }; - - buck2_reg: BUCK2 { - regulator-name = "vdd_atlas"; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - regulator-ramp-delay = <12500>; - regulator-enable-ramp-delay = <250>; - }; - - buck4_reg: BUCK4 { - regulator-name = "vdd_int"; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - regulator-ramp-delay = <12500>; - regulator-enable-ramp-delay = <250>; - }; - - buck5_reg: BUCK5 { - regulator-name = "vdd_buck5"; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1300000>; - regulator-ramp-delay = <25000>; - regulator-enable-ramp-delay = <250>; - }; - - buck6_reg: BUCK6 { - regulator-name = "vdd_g3d"; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1400000>; - regulator-ramp-delay = <12500>; - regulator-enable-ramp-delay = <250>; - }; - - buck7_reg: BUCK7 { - regulator-name = "vdd_buck7"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-ramp-delay = <25000>; - regulator-enable-ramp-delay = <250>; - }; - - buck8_reg: BUCK8 { - regulator-name = "vdd_buck8"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-ramp-delay = <25000>; - regulator-enable-ramp-delay = <250>; - }; - - buck9_reg: BUCK9 { - regulator-name = "vdd_buck9"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2100000>; - regulator-always-on; - regulator-ramp-delay = <25000>; - regulator-enable-ramp-delay = <250>; - }; - - buck10_reg: BUCK10 { - regulator-name = "vdd_buck10"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - regulator-ramp-delay = <25000>; - regulator-enable-ramp-delay = <250>; - }; - }; - }; -}; - -&pinctrl_alive { - pmic_irq: pmic-irq { - samsung,pins = "gpa0-2"; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&mmc_0 { - status = "okay"; - cap-mmc-highspeed; - mmc-hs200-1_8v; - non-removable; - card-detect-delay = <200>; - clock-frequency = <800000000>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <0 4>; - samsung,dw-mshc-ddr-timing = <0 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_qrdy &sd0_bus1 &sd0_bus4 &sd0_bus8>; - bus-width = <8>; -}; - -&mmc_2 { - status = "okay"; - cap-sd-highspeed; - card-detect-delay = <200>; - clock-frequency = <400000000>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>; - bus-width = <4>; - vmmc-supply = <&ldo17_reg>; - vqmmc-supply = <&ldo2_reg>; - disable-wp; -}; - -&pinctrl_bus1 { - usb30_vbus_en: usb30-vbus-en { - samsung,pins = "gph1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - usb3drd_boost_en: usb3drd-boost-en { - samsung,pins = "gpf4-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&usbdrd_phy { - vbus-supply = <&usb30_vbus_reg>; - vbus-boost-supply = <&usb3drd_boost_5v>; -}; diff --git a/sys/gnu/dts/arm64/exynos/exynos7-pinctrl.dtsi b/sys/gnu/dts/arm64/exynos/exynos7-pinctrl.dtsi deleted file mode 100644 index 472dd649aa7..00000000000 --- a/sys/gnu/dts/arm64/exynos/exynos7-pinctrl.dtsi +++ /dev/null @@ -1,702 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's Exynos7 SoC pin-mux and pin-config device tree source - * - * Copyright (c) 2014 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Samsung's Exynos7 SoC pin-mux and pin-config options are listed as - * device tree nodes in this file. - */ - -#include - -&pinctrl_alive { - gpa0: gpa0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - interrupt-parent = <&gic>; - #interrupt-cells = <2>; - interrupts = , - , - , - , - , - , - , - ; - }; - - gpa1: gpa1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - interrupt-parent = <&gic>; - #interrupt-cells = <2>; - interrupts = , - , - , - , - , - , - , - ; - }; - - gpa2: gpa2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpa3: gpa3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; -}; - -&pinctrl_bus0 { - gpb0: gpb0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc0: gpc0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc1: gpc1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc2: gpc2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc3: gpc3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpd0: gpd0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpd1: gpd1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpd2: gpd2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpd4: gpd4 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpd5: gpd5 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpd6: gpd6 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpd7: gpd7 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpd8: gpd8 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpg0: gpg0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpg3: gpg3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - hs_i2c10_bus: hs-i2c10-bus { - samsung,pins = "gpb0-1", "gpb0-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - hs_i2c11_bus: hs-i2c11-bus { - samsung,pins = "gpb0-3", "gpb0-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - hs_i2c2_bus: hs-i2c2-bus { - samsung,pins = "gpd0-3", "gpd0-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart0_data: uart0-data { - samsung,pins = "gpd0-0", "gpd0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart0_fctl: uart0-fctl { - samsung,pins = "gpd0-2", "gpd0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart2_data: uart2-data { - samsung,pins = "gpd1-4", "gpd1-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - hs_i2c3_bus: hs-i2c3-bus { - samsung,pins = "gpd1-3", "gpd1-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart1_data: uart1-data { - samsung,pins = "gpd1-0", "gpd1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart1_fctl: uart1-fctl { - samsung,pins = "gpd1-2", "gpd1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - hs_i2c0_bus: hs-i2c0-bus { - samsung,pins = "gpd2-1", "gpd2-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - hs_i2c1_bus: hs-i2c1-bus { - samsung,pins = "gpd2-3", "gpd2-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - hs_i2c9_bus: hs-i2c9-bus { - samsung,pins = "gpd2-7", "gpd2-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm0_out: pwm0-out { - samsung,pins = "gpd2-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm1_out: pwm1-out { - samsung,pins = "gpd2-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm2_out: pwm2-out { - samsung,pins = "gpd2-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm3_out: pwm3-out { - samsung,pins = "gpd2-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - hs_i2c8_bus: hs-i2c8-bus { - samsung,pins = "gpd5-3", "gpd5-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart3_data: uart3-data { - samsung,pins = "gpd5-0", "gpd5-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spi2_bus: spi2-bus { - samsung,pins = "gpd5-0", "gpd5-1", "gpd5-2", "gpd5-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spi1_bus: spi1-bus { - samsung,pins = "gpd6-2", "gpd6-3", "gpd6-4", "gpd6-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spi0_bus: spi0-bus { - samsung,pins = "gpd8-0", "gpd8-1", "gpd6-0", "gpd6-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - hs_i2c4_bus: hs-i2c4-bus { - samsung,pins = "gpg3-1", "gpg3-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - hs_i2c5_bus: hs-i2c5-bus { - samsung,pins = "gpg3-3", "gpg3-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pinctrl_nfc { - gpj0: gpj0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - hs_i2c6_bus: hs-i2c6-bus { - samsung,pins = "gpj0-1", "gpj0-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pinctrl_touch { - gpj1: gpj1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - hs_i2c7_bus: hs-i2c7-bus { - samsung,pins = "gpj1-1", "gpj1-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pinctrl_ff { - gpg4: gpg4 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - spi3_bus: spi3-bus { - samsung,pins = "gpg4-0", "gpg4-1", "gpg4-2", "gpg4-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pinctrl_ese { - gpv7: gpv7 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - spi4_bus: spi4-bus { - samsung,pins = "gpv7-0", "gpv7-1", "gpv7-2", "gpv7-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pinctrl_fsys0 { - gpr4: gpr4 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - sd2_clk: sd2-clk { - samsung,pins = "gpr4-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_cmd: sd2-cmd { - samsung,pins = "gpr4-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_cd: sd2-cd { - samsung,pins = "gpr4-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_bus1: sd2-bus-width1 { - samsung,pins = "gpr4-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_bus4: sd2-bus-width4 { - samsung,pins = "gpr4-4", "gpr4-5", "gpr4-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pinctrl_fsys1 { - gpr0: gpr0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpr1: gpr1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpr2: gpr2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpr3: gpr3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - sd0_clk: sd0-clk { - samsung,pins = "gpr0-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_cmd: sd0-cmd { - samsung,pins = "gpr0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_ds: sd0-ds { - samsung,pins = "gpr0-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_qrdy: sd0-qrdy { - samsung,pins = "gpr0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus1: sd0-bus-width1 { - samsung,pins = "gpr1-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus4: sd0-bus-width4 { - samsung,pins = "gpr1-1", "gpr1-2", "gpr1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus8: sd0-bus-width8 { - samsung,pins = "gpr1-4", "gpr1-5", "gpr1-6", "gpr1-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_clk: sd1-clk { - samsung,pins = "gpr2-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_cmd: sd1-cmd { - samsung,pins = "gpr2-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_ds: sd1-ds { - samsung,pins = "gpr2-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_qrdy: sd1-qrdy { - samsung,pins = "gpr2-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_int: sd1-int { - samsung,pins = "gpr2-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_bus1: sd1-bus-width1 { - samsung,pins = "gpr3-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_bus4: sd1-bus-width4 { - samsung,pins = "gpr3-1", "gpr3-2", "gpr3-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_bus8: sd1-bus-width8 { - samsung,pins = "gpr3-4", "gpr3-5", "gpr3-6", "gpr3-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pinctrl_bus1 { - gpf0: gpf0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf1: gpf1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf2: gpf2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf3: gpf3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf4: gpf4 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf5: gpf5 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpg1: gpg1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpg2: gpg2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gph1: gph1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpv6: gpv6 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - spi5_bus: spi5-bus { - samsung,pins = "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - ufs_refclk_out: ufs-refclk-out { - samsung,pins = "gpg2-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - ufs_rst_n: ufs-rst-n { - samsung,pins = "gph1-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; diff --git a/sys/gnu/dts/arm64/exynos/exynos7-trip-points.dtsi b/sys/gnu/dts/arm64/exynos/exynos7-trip-points.dtsi deleted file mode 100644 index d3301b8bd36..00000000000 --- a/sys/gnu/dts/arm64/exynos/exynos7-trip-points.dtsi +++ /dev/null @@ -1,50 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device tree sources for default Exynos7 thermal zone definition - * - * Copyright (c) 2016 Samsung Electronics Co., Ltd. - * http://www.samsung.com - */ - -trips { - cpu-alert-0 { - temperature = <75000>; /* millicelsius */ - hysteresis = <10000>; /* millicelsius */ - type = "passive"; - }; - cpu-alert-1 { - temperature = <80000>; /* millicelsius */ - hysteresis = <10000>; /* millicelsius */ - type = "passive"; - }; - cpu-alert-2 { - temperature = <85000>; /* millicelsius */ - hysteresis = <10000>; /* millicelsius */ - type = "passive"; - }; - cpu-alert-3 { - temperature = <90000>; /* millicelsius */ - hysteresis = <10000>; /* millicelsius */ - type = "passive"; - }; - cpu-alert-4 { - temperature = <95000>; /* millicelsius */ - hysteresis = <10000>; /* millicelsius */ - type = "passive"; - }; - cpu-alert-5 { - temperature = <100000>; /* millicelsius */ - hysteresis = <10000>; /* millicelsius */ - type = "passive"; - }; - cpu-alert-6 { - temperature = <110000>; /* millicelsius */ - hysteresis = <10000>; /* millicelsius */ - type = "passive"; - }; - cpu-crit-0 { - temperature = <115000>; /* millicelsius */ - hysteresis = <0>; /* millicelsius */ - type = "critical"; - }; -}; diff --git a/sys/gnu/dts/arm64/exynos/exynos7.dtsi b/sys/gnu/dts/arm64/exynos/exynos7.dtsi deleted file mode 100644 index 5558045637a..00000000000 --- a/sys/gnu/dts/arm64/exynos/exynos7.dtsi +++ /dev/null @@ -1,652 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung Exynos7 SoC device tree source - * - * Copyright (c) 2014 Samsung Electronics Co., Ltd. - * http://www.samsung.com - */ - -#include -#include - -/ { - compatible = "samsung,exynos7"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - pinctrl0 = &pinctrl_alive; - pinctrl1 = &pinctrl_bus0; - pinctrl2 = &pinctrl_nfc; - pinctrl3 = &pinctrl_touch; - pinctrl4 = &pinctrl_ff; - pinctrl5 = &pinctrl_ese; - pinctrl6 = &pinctrl_fsys0; - pinctrl7 = &pinctrl_fsys1; - pinctrl8 = &pinctrl_bus1; - tmuctrl0 = &tmuctrl_0; - }; - - arm-pmu { - compatible = "arm,cortex-a57-pmu", "arm,armv8-pmuv3"; - interrupts = , - , - , - ; - interrupt-affinity = <&cpu_atlas0>, <&cpu_atlas1>, - <&cpu_atlas2>, <&cpu_atlas3>; - }; - - fin_pll: clock { - /* XXTI */ - compatible = "fixed-clock"; - clock-output-names = "fin_pll"; - #clock-cells = <0>; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu_atlas0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0>; - enable-method = "psci"; - }; - - cpu_atlas1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x1>; - enable-method = "psci"; - }; - - cpu_atlas2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x2>; - enable-method = "psci"; - }; - - cpu_atlas3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x3>; - enable-method = "psci"; - }; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - soc: soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0 0x18000000>; - - chipid@10000000 { - compatible = "samsung,exynos4210-chipid"; - reg = <0x10000000 0x100>; - }; - - gic: interrupt-controller@11001000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x11001000 0x1000>, - <0x11002000 0x1000>, - <0x11004000 0x2000>, - <0x11006000 0x2000>; - }; - - amba { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - pdma0: pdma@10e10000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x10E10000 0x1000>; - interrupts = ; - clocks = <&clock_fsys0 ACLK_PDMA0>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; - }; - - pdma1: pdma@10eb0000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x10EB0000 0x1000>; - interrupts = ; - clocks = <&clock_fsys0 ACLK_PDMA1>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; - }; - }; - - clock_topc: clock-controller@10570000 { - compatible = "samsung,exynos7-clock-topc"; - reg = <0x10570000 0x10000>; - #clock-cells = <1>; - }; - - clock_top0: clock-controller@105d0000 { - compatible = "samsung,exynos7-clock-top0"; - reg = <0x105d0000 0xb000>; - #clock-cells = <1>; - clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>, - <&clock_topc DOUT_SCLK_BUS1_PLL>, - <&clock_topc DOUT_SCLK_CC_PLL>, - <&clock_topc DOUT_SCLK_MFC_PLL>; - clock-names = "fin_pll", "dout_sclk_bus0_pll", - "dout_sclk_bus1_pll", "dout_sclk_cc_pll", - "dout_sclk_mfc_pll"; - }; - - clock_top1: clock-controller@105e0000 { - compatible = "samsung,exynos7-clock-top1"; - reg = <0x105e0000 0xb000>; - #clock-cells = <1>; - clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>, - <&clock_topc DOUT_SCLK_BUS1_PLL>, - <&clock_topc DOUT_SCLK_CC_PLL>, - <&clock_topc DOUT_SCLK_MFC_PLL>; - clock-names = "fin_pll", "dout_sclk_bus0_pll", - "dout_sclk_bus1_pll", "dout_sclk_cc_pll", - "dout_sclk_mfc_pll"; - }; - - clock_ccore: clock-controller@105b0000 { - compatible = "samsung,exynos7-clock-ccore"; - reg = <0x105b0000 0xd00>; - #clock-cells = <1>; - clocks = <&fin_pll>, <&clock_topc DOUT_ACLK_CCORE_133>; - clock-names = "fin_pll", "dout_aclk_ccore_133"; - }; - - clock_peric0: clock-controller@13610000 { - compatible = "samsung,exynos7-clock-peric0"; - reg = <0x13610000 0xd00>; - #clock-cells = <1>; - clocks = <&fin_pll>, <&clock_top0 DOUT_ACLK_PERIC0>, - <&clock_top0 CLK_SCLK_UART0>; - clock-names = "fin_pll", "dout_aclk_peric0_66", - "sclk_uart0"; - }; - - clock_peric1: clock-controller@14c80000 { - compatible = "samsung,exynos7-clock-peric1"; - reg = <0x14c80000 0xd00>; - #clock-cells = <1>; - clocks = <&fin_pll>, <&clock_top0 DOUT_ACLK_PERIC1>, - <&clock_top0 CLK_SCLK_UART1>, - <&clock_top0 CLK_SCLK_UART2>, - <&clock_top0 CLK_SCLK_UART3>; - clock-names = "fin_pll", "dout_aclk_peric1_66", - "sclk_uart1", "sclk_uart2", "sclk_uart3"; - }; - - clock_peris: clock-controller@10040000 { - compatible = "samsung,exynos7-clock-peris"; - reg = <0x10040000 0xd00>; - #clock-cells = <1>; - clocks = <&fin_pll>, <&clock_topc DOUT_ACLK_PERIS>; - clock-names = "fin_pll", "dout_aclk_peris_66"; - }; - - clock_fsys0: clock-controller@10e90000 { - compatible = "samsung,exynos7-clock-fsys0"; - reg = <0x10e90000 0xd00>; - #clock-cells = <1>; - clocks = <&fin_pll>, <&clock_top1 DOUT_ACLK_FSYS0_200>, - <&clock_top1 DOUT_SCLK_MMC2>; - clock-names = "fin_pll", "dout_aclk_fsys0_200", - "dout_sclk_mmc2"; - }; - - clock_fsys1: clock-controller@156e0000 { - compatible = "samsung,exynos7-clock-fsys1"; - reg = <0x156e0000 0xd00>; - #clock-cells = <1>; - clocks = <&fin_pll>, <&clock_top1 DOUT_ACLK_FSYS1_200>, - <&clock_top1 DOUT_SCLK_MMC0>, - <&clock_top1 DOUT_SCLK_MMC1>; - clock-names = "fin_pll", "dout_aclk_fsys1_200", - "dout_sclk_mmc0", "dout_sclk_mmc1"; - }; - - serial_0: serial@13630000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x13630000 0x100>; - interrupts = ; - clocks = <&clock_peric0 PCLK_UART0>, - <&clock_peric0 SCLK_UART0>; - clock-names = "uart", "clk_uart_baud0"; - status = "disabled"; - }; - - serial_1: serial@14c20000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x14c20000 0x100>; - interrupts = ; - clocks = <&clock_peric1 PCLK_UART1>, - <&clock_peric1 SCLK_UART1>; - clock-names = "uart", "clk_uart_baud0"; - status = "disabled"; - }; - - serial_2: serial@14c30000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x14c30000 0x100>; - interrupts = ; - clocks = <&clock_peric1 PCLK_UART2>, - <&clock_peric1 SCLK_UART2>; - clock-names = "uart", "clk_uart_baud0"; - status = "disabled"; - }; - - serial_3: serial@14c40000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x14c40000 0x100>; - interrupts = ; - clocks = <&clock_peric1 PCLK_UART3>, - <&clock_peric1 SCLK_UART3>; - clock-names = "uart", "clk_uart_baud0"; - status = "disabled"; - }; - - pinctrl_alive: pinctrl@10580000 { - compatible = "samsung,exynos7-pinctrl"; - reg = <0x10580000 0x1000>; - - wakeup-interrupt-controller { - compatible = "samsung,exynos7-wakeup-eint"; - interrupt-parent = <&gic>; - interrupts = ; - }; - }; - - pinctrl_bus0: pinctrl@13470000 { - compatible = "samsung,exynos7-pinctrl"; - reg = <0x13470000 0x1000>; - interrupts = ; - }; - - pinctrl_nfc: pinctrl@14cd0000 { - compatible = "samsung,exynos7-pinctrl"; - reg = <0x14cd0000 0x1000>; - interrupts = ; - }; - - pinctrl_touch: pinctrl@14ce0000 { - compatible = "samsung,exynos7-pinctrl"; - reg = <0x14ce0000 0x1000>; - interrupts = ; - }; - - pinctrl_ff: pinctrl@14c90000 { - compatible = "samsung,exynos7-pinctrl"; - reg = <0x14c90000 0x1000>; - interrupts = ; - }; - - pinctrl_ese: pinctrl@14ca0000 { - compatible = "samsung,exynos7-pinctrl"; - reg = <0x14ca0000 0x1000>; - interrupts = ; - }; - - pinctrl_fsys0: pinctrl@10e60000 { - compatible = "samsung,exynos7-pinctrl"; - reg = <0x10e60000 0x1000>; - interrupts = ; - }; - - pinctrl_fsys1: pinctrl@15690000 { - compatible = "samsung,exynos7-pinctrl"; - reg = <0x15690000 0x1000>; - interrupts = ; - }; - - pinctrl_bus1: pinctrl@14870000 { - compatible = "samsung,exynos7-pinctrl"; - reg = <0x14870000 0x1000>; - interrupts = ; - }; - - hsi2c_0: hsi2c@13640000 { - compatible = "samsung,exynos7-hsi2c"; - reg = <0x13640000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&hs_i2c0_bus>; - clocks = <&clock_peric0 PCLK_HSI2C0>; - clock-names = "hsi2c"; - status = "disabled"; - }; - - hsi2c_1: hsi2c@13650000 { - compatible = "samsung,exynos7-hsi2c"; - reg = <0x13650000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&hs_i2c1_bus>; - clocks = <&clock_peric0 PCLK_HSI2C1>; - clock-names = "hsi2c"; - status = "disabled"; - }; - - hsi2c_2: hsi2c@14e60000 { - compatible = "samsung,exynos7-hsi2c"; - reg = <0x14e60000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&hs_i2c2_bus>; - clocks = <&clock_peric1 PCLK_HSI2C2>; - clock-names = "hsi2c"; - status = "disabled"; - }; - - hsi2c_3: hsi2c@14e70000 { - compatible = "samsung,exynos7-hsi2c"; - reg = <0x14e70000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&hs_i2c3_bus>; - clocks = <&clock_peric1 PCLK_HSI2C3>; - clock-names = "hsi2c"; - status = "disabled"; - }; - - hsi2c_4: hsi2c@13660000 { - compatible = "samsung,exynos7-hsi2c"; - reg = <0x13660000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&hs_i2c4_bus>; - clocks = <&clock_peric0 PCLK_HSI2C4>; - clock-names = "hsi2c"; - status = "disabled"; - }; - - hsi2c_5: hsi2c@13670000 { - compatible = "samsung,exynos7-hsi2c"; - reg = <0x13670000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&hs_i2c5_bus>; - clocks = <&clock_peric0 PCLK_HSI2C5>; - clock-names = "hsi2c"; - status = "disabled"; - }; - - hsi2c_6: hsi2c@14e00000 { - compatible = "samsung,exynos7-hsi2c"; - reg = <0x14e00000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&hs_i2c6_bus>; - clocks = <&clock_peric1 PCLK_HSI2C6>; - clock-names = "hsi2c"; - status = "disabled"; - }; - - hsi2c_7: hsi2c@13e10000 { - compatible = "samsung,exynos7-hsi2c"; - reg = <0x13e10000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&hs_i2c7_bus>; - clocks = <&clock_peric1 PCLK_HSI2C7>; - clock-names = "hsi2c"; - status = "disabled"; - }; - - hsi2c_8: hsi2c@14e20000 { - compatible = "samsung,exynos7-hsi2c"; - reg = <0x14e20000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&hs_i2c8_bus>; - clocks = <&clock_peric1 PCLK_HSI2C8>; - clock-names = "hsi2c"; - status = "disabled"; - }; - - hsi2c_9: hsi2c@13680000 { - compatible = "samsung,exynos7-hsi2c"; - reg = <0x13680000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&hs_i2c9_bus>; - clocks = <&clock_peric0 PCLK_HSI2C9>; - clock-names = "hsi2c"; - status = "disabled"; - }; - - hsi2c_10: hsi2c@13690000 { - compatible = "samsung,exynos7-hsi2c"; - reg = <0x13690000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&hs_i2c10_bus>; - clocks = <&clock_peric0 PCLK_HSI2C10>; - clock-names = "hsi2c"; - status = "disabled"; - }; - - hsi2c_11: hsi2c@136a0000 { - compatible = "samsung,exynos7-hsi2c"; - reg = <0x136a0000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&hs_i2c11_bus>; - clocks = <&clock_peric0 PCLK_HSI2C11>; - clock-names = "hsi2c"; - status = "disabled"; - }; - - pmu_system_controller: system-controller@105c0000 { - compatible = "samsung,exynos7-pmu", "syscon"; - reg = <0x105c0000 0x5000>; - - reboot: syscon-reboot { - compatible = "syscon-reboot"; - regmap = <&pmu_system_controller>; - offset = <0x0400>; - mask = <0x1>; - }; - }; - - rtc: rtc@10590000 { - compatible = "samsung,s3c6410-rtc"; - reg = <0x10590000 0x100>; - interrupts = , - ; - clocks = <&clock_ccore PCLK_RTC>; - clock-names = "rtc"; - status = "disabled"; - }; - - watchdog: watchdog@101d0000 { - compatible = "samsung,exynos7-wdt"; - reg = <0x101d0000 0x100>; - interrupts = ; - clocks = <&clock_peris PCLK_WDT>; - clock-names = "watchdog"; - samsung,syscon-phandle = <&pmu_system_controller>; - status = "disabled"; - }; - - gpu: gpu@14ac0000 { - compatible = "samsung,exynos5433-mali", "arm,mali-t760"; - reg = <0x14ac0000 0x5000>; - interrupts = , - , - ; - interrupt-names = "job", "mmu", "gpu"; - status = "disabled"; - /* TODO: operating points for DVFS, cooling device */ - }; - - mmc_0: mmc@15740000 { - compatible = "samsung,exynos7-dw-mshc-smu"; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x15740000 0x2000>; - clocks = <&clock_fsys1 ACLK_MMC0>, - <&clock_top1 CLK_SCLK_MMC0>; - clock-names = "biu", "ciu"; - fifo-depth = <0x40>; - status = "disabled"; - }; - - mmc_1: mmc@15750000 { - compatible = "samsung,exynos7-dw-mshc"; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x15750000 0x2000>; - clocks = <&clock_fsys1 ACLK_MMC1>, - <&clock_top1 CLK_SCLK_MMC1>; - clock-names = "biu", "ciu"; - fifo-depth = <0x40>; - status = "disabled"; - }; - - mmc_2: mmc@15560000 { - compatible = "samsung,exynos7-dw-mshc-smu"; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x15560000 0x2000>; - clocks = <&clock_fsys0 ACLK_MMC2>, - <&clock_top1 CLK_SCLK_MMC2>; - clock-names = "biu", "ciu"; - fifo-depth = <0x40>; - status = "disabled"; - }; - - adc: adc@13620000 { - compatible = "samsung,exynos7-adc"; - reg = <0x13620000 0x100>; - interrupts = ; - clocks = <&clock_peric0 PCLK_ADCIF>; - clock-names = "adc"; - #io-channel-cells = <1>; - io-channel-ranges; - status = "disabled"; - }; - - pwm: pwm@136c0000 { - compatible = "samsung,exynos4210-pwm"; - reg = <0x136c0000 0x100>; - samsung,pwm-outputs = <0>, <1>, <2>, <3>; - #pwm-cells = <3>; - clocks = <&clock_peric0 PCLK_PWM>; - clock-names = "timers"; - }; - - tmuctrl_0: tmu@10060000 { - compatible = "samsung,exynos7-tmu"; - reg = <0x10060000 0x200>; - interrupts = ; - clocks = <&clock_peris PCLK_TMU>, - <&clock_peris SCLK_TMU>; - clock-names = "tmu_apbif", "tmu_sclk"; - #thermal-sensor-cells = <0>; - }; - - thermal-zones { - atlas_thermal: cluster0-thermal { - polling-delay-passive = <0>; /* milliseconds */ - polling-delay = <0>; /* milliseconds */ - thermal-sensors = <&tmuctrl_0>; - #include "exynos7-trip-points.dtsi" - }; - }; - - usbdrd_phy: phy@15500000 { - compatible = "samsung,exynos7-usbdrd-phy"; - reg = <0x15500000 0x100>; - clocks = <&clock_fsys0 ACLK_USBDRD300>, - <&clock_fsys0 OSCCLK_PHY_CLKOUT_USB30_PHY>, - <&clock_fsys0 PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER>, - <&clock_fsys0 PHYCLK_USBDRD300_UDRD30_PHYCLK_USER>, - <&clock_fsys0 SCLK_USBDRD300_REFCLK>; - clock-names = "phy", "ref", "phy_pipe", - "phy_utmi", "itp"; - samsung,pmu-syscon = <&pmu_system_controller>; - #phy-cells = <1>; - }; - - usbdrd3 { - compatible = "samsung,exynos7-dwusb3"; - clocks = <&clock_fsys0 ACLK_USBDRD300>, - <&clock_fsys0 SCLK_USBDRD300_SUSPENDCLK>, - <&clock_fsys0 ACLK_AXIUS_USBDRD30X_FSYS0X>; - clock-names = "usbdrd30", "usbdrd30_susp_clk", - "usbdrd30_axius_clk"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - dwc3@15400000 { - compatible = "snps,dwc3"; - reg = <0x15400000 0x10000>; - interrupts = ; - phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>; - phy-names = "usb2-phy", "usb3-phy"; - }; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; -}; - -#include "exynos7-pinctrl.dtsi" diff --git a/sys/gnu/dts/arm64/freescale/fsl-ls1012a-frdm.dts b/sys/gnu/dts/arm64/freescale/fsl-ls1012a-frdm.dts deleted file mode 100644 index f90c040fd5e..00000000000 --- a/sys/gnu/dts/arm64/freescale/fsl-ls1012a-frdm.dts +++ /dev/null @@ -1,83 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for Freescale LS1012A Freedom Board. - * - * Copyright 2016 Freescale Semiconductor, Inc. - * - */ -/dts-v1/; - -#include "fsl-ls1012a.dtsi" - -/ { - model = "LS1012A Freedom Board"; - compatible = "fsl,ls1012a-frdm", "fsl,ls1012a"; - - sys_mclk: clock-mclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-name = "1P8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,widgets = - "Microphone", "Microphone Jack", - "Headphone", "Headphone Jack", - "Speaker", "Speaker Ext", - "Line", "Line In Jack"; - simple-audio-card,routing = - "MIC_IN", "Microphone Jack", - "Microphone Jack", "Mic Bias", - "LINE_IN", "Line In Jack", - "Headphone Jack", "HP_OUT", - "Speaker Ext", "LINE_OUT"; - - simple-audio-card,cpu { - sound-dai = <&sai2>; - frame-master; - bitclock-master; - }; - - simple-audio-card,codec { - sound-dai = <&codec>; - frame-master; - bitclock-master; - system-clock-frequency = <25000000>; - }; - }; -}; - -&duart0 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - codec: sgtl5000@a { - #sound-dai-cells = <0>; - compatible = "fsl,sgtl5000"; - reg = <0xa>; - VDDA-supply = <®_1p8v>; - VDDIO-supply = <®_1p8v>; - clocks = <&sys_mclk>; - }; -}; - -&sai2 { - status = "okay"; -}; - -&sata { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/freescale/fsl-ls1012a-frwy.dts b/sys/gnu/dts/arm64/freescale/fsl-ls1012a-frwy.dts deleted file mode 100644 index 8749634c55e..00000000000 --- a/sys/gnu/dts/arm64/freescale/fsl-ls1012a-frwy.dts +++ /dev/null @@ -1,25 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for Freescale LS1012A FRWY Board. - * - * Copyright 2018 NXP - * - * Pramod Kumar - * - */ -/dts-v1/; - -#include "fsl-ls1012a.dtsi" - -/ { - model = "LS1012A FRWY Board"; - compatible = "fsl,ls1012a-frwy", "fsl,ls1012a"; -}; - -&duart0 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/freescale/fsl-ls1012a-oxalis.dts b/sys/gnu/dts/arm64/freescale/fsl-ls1012a-oxalis.dts deleted file mode 100644 index 9927b096d34..00000000000 --- a/sys/gnu/dts/arm64/freescale/fsl-ls1012a-oxalis.dts +++ /dev/null @@ -1,100 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for Oxalis - * - * Copyright (c) 2019 Manivannan Sadhasivam - * - */ - -/dts-v1/; - -#include "fsl-ls1012a.dtsi" - -/ { - model = "Oxalis"; - compatible = "ebs-systart,oxalis", "fsl,ls1012a"; - - sys_mclk: clock-mclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-name = "1P8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,widgets = - "Microphone", "Microphone Jack", - "Headphone", "Headphone Jack", - "Speaker", "Speaker Ext", - "Line", "Line In Jack"; - simple-audio-card,routing = - "MIC_IN", "Microphone Jack", - "Microphone Jack", "Mic Bias", - "LINE_IN", "Line In Jack", - "Headphone Jack", "HP_OUT", - "Speaker Ext", "LINE_OUT"; - - simple-audio-card,cpu { - sound-dai = <&sai2>; - frame-master; - bitclock-master; - }; - - simple-audio-card,codec { - sound-dai = <&codec>; - frame-master; - bitclock-master; - system-clock-frequency = <25000000>; - }; - }; -}; - -&duart0 { - status = "okay"; -}; - -&duart1 { - status = "okay"; -}; - -&esdhc1 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - codec: audio-codec@a { - #sound-dai-cells = <0>; - compatible = "fsl,sgtl5000"; - reg = <0xa>; - VDDA-supply = <®_1p8v>; - VDDIO-supply = <®_1p8v>; - clocks = <&sys_mclk>; - }; -}; - -&i2c1 { - status = "okay"; -}; - -&pcie { - status = "okay"; -}; - -&sai2 { - status = "okay"; -}; - -&sata { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/freescale/fsl-ls1012a-qds.dts b/sys/gnu/dts/arm64/freescale/fsl-ls1012a-qds.dts deleted file mode 100644 index 2fb1cb1f7d8..00000000000 --- a/sys/gnu/dts/arm64/freescale/fsl-ls1012a-qds.dts +++ /dev/null @@ -1,137 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for Freescale LS1012A QDS Board. - * - * Copyright 2016 Freescale Semiconductor, Inc. - * - */ -/dts-v1/; - -#include "fsl-ls1012a.dtsi" - -/ { - model = "LS1012A QDS Board"; - compatible = "fsl,ls1012a-qds", "fsl,ls1012a"; - - sys_mclk: clock-mclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24576000>; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,widgets = - "Microphone", "Microphone Jack", - "Headphone", "Headphone Jack", - "Speaker", "Speaker Ext", - "Line", "Line In Jack"; - simple-audio-card,routing = - "MIC_IN", "Microphone Jack", - "Microphone Jack", "Mic Bias", - "LINE_IN", "Line In Jack", - "Headphone Jack", "HP_OUT", - "Speaker Ext", "LINE_OUT"; - - simple-audio-card,cpu { - sound-dai = <&sai2>; - frame-master; - bitclock-master; - }; - - simple-audio-card,codec { - sound-dai = <&codec>; - frame-master; - bitclock-master; - system-clock-frequency = <24576000>; - }; - }; -}; - -&dspi { - bus-num = <0>; - status = "okay"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "n25q128a11", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <10000000>; - }; - - flash@1 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "sst25wf040b", "jedec,spi-nor"; - spi-cpol; - spi-cpha; - reg = <1>; - spi-max-frequency = <10000000>; - }; - - flash@2 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "en25s64", "jedec,spi-nor"; - spi-cpol; - spi-cpha; - reg = <2>; - spi-max-frequency = <10000000>; - }; -}; - -&duart0 { - status = "okay"; -}; - -&esdhc0 { - status = "okay"; -}; - -&esdhc1 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - pca9547@77 { - compatible = "nxp,pca9547"; - reg = <0x77>; - #address-cells = <1>; - #size-cells = <0>; - - i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x4>; - - codec: sgtl5000@a { - #sound-dai-cells = <0>; - compatible = "fsl,sgtl5000"; - reg = <0xa>; - VDDA-supply = <®_3p3v>; - VDDIO-supply = <®_3p3v>; - clocks = <&sys_mclk>; - }; - }; - }; -}; - -&sai2 { - status = "okay"; -}; - -&sata { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/freescale/fsl-ls1012a-rdb.dts b/sys/gnu/dts/arm64/freescale/fsl-ls1012a-rdb.dts deleted file mode 100644 index 5edb1e137a5..00000000000 --- a/sys/gnu/dts/arm64/freescale/fsl-ls1012a-rdb.dts +++ /dev/null @@ -1,40 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for Freescale LS1012A RDB Board. - * - * Copyright 2016 Freescale Semiconductor, Inc. - * - */ -/dts-v1/; - -#include "fsl-ls1012a.dtsi" - -/ { - model = "LS1012A RDB Board"; - compatible = "fsl,ls1012a-rdb", "fsl,ls1012a"; -}; - -&duart0 { - status = "okay"; -}; - -&esdhc0 { - sd-uhs-sdr104; - sd-uhs-sdr50; - sd-uhs-sdr25; - sd-uhs-sdr12; - status = "okay"; -}; - -&esdhc1 { - mmc-hs200-1_8v; - status = "okay"; -}; - -&i2c0 { - status = "okay"; -}; - -&sata { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/freescale/fsl-ls1012a.dtsi b/sys/gnu/dts/arm64/freescale/fsl-ls1012a.dtsi deleted file mode 100644 index 337919366dc..00000000000 --- a/sys/gnu/dts/arm64/freescale/fsl-ls1012a.dtsi +++ /dev/null @@ -1,510 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree Include file for Freescale Layerscape-1012A family SoC. - * - * Copyright 2016 Freescale Semiconductor, Inc. - * - */ - -#include -#include - -/ { - compatible = "fsl,ls1012a"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - crypto = &crypto; - rtic-a = &rtic_a; - rtic-b = &rtic_b; - rtic-c = &rtic_c; - rtic-d = &rtic_d; - sec-mon = &sec_mon; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0>; - clocks = <&clockgen 1 0>; - #cooling-cells = <2>; - cpu-idle-states = <&CPU_PH20>; - }; - }; - - idle-states { - /* - * PSCI node is not added default, U-boot will add missing - * parts if it determines to use PSCI. - */ - entry-method = "psci"; - - CPU_PH20: cpu-ph20 { - compatible = "arm,idle-state"; - idle-state-name = "PH20"; - arm,psci-suspend-param = <0x0>; - entry-latency-us = <1000>; - exit-latency-us = <1000>; - min-residency-us = <3000>; - }; - }; - - sysclk: sysclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <125000000>; - clock-output-names = "sysclk"; - }; - - coreclk: coreclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - clock-output-names = "coreclk"; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */ - <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */ - <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */ - <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */ - }; - - pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; - }; - - gic: interrupt-controller@1400000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x0 0x1401000 0 0x1000>, /* GICD */ - <0x0 0x1402000 0 0x2000>, /* GICC */ - <0x0 0x1404000 0 0x2000>, /* GICH */ - <0x0 0x1406000 0 0x2000>; /* GICV */ - interrupts = <1 9 IRQ_TYPE_LEVEL_LOW>; - }; - - reboot { - compatible = "syscon-reboot"; - regmap = <&dcfg>; - offset = <0xb0>; - mask = <0x02>; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <1000>; - polling-delay = <5000>; - thermal-sensors = <&tmu 0>; - - trips { - cpu_alert: cpu-alert { - temperature = <85000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu_crit: cpu-crit { - temperature = <95000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu_alert>; - cooling-device = - <&cpu0 THERMAL_NO_LIMIT - THERMAL_NO_LIMIT>; - }; - }; - }; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - esdhc0: esdhc@1560000 { - compatible = "fsl,ls1012a-esdhc", "fsl,esdhc"; - reg = <0x0 0x1560000 0x0 0x10000>; - interrupts = <0 62 0x4>; - clocks = <&clockgen 4 0>; - voltage-ranges = <1800 1800 3300 3300>; - sdhci,auto-cmd12; - big-endian; - bus-width = <4>; - status = "disabled"; - }; - - scfg: scfg@1570000 { - compatible = "fsl,ls1012a-scfg", "syscon"; - reg = <0x0 0x1570000 0x0 0x10000>; - big-endian; - }; - - esdhc1: esdhc@1580000 { - compatible = "fsl,ls1012a-esdhc", "fsl,esdhc"; - reg = <0x0 0x1580000 0x0 0x10000>; - interrupts = <0 65 0x4>; - clocks = <&clockgen 4 0>; - voltage-ranges = <1800 1800 3300 3300>; - sdhci,auto-cmd12; - big-endian; - broken-cd; - bus-width = <4>; - status = "disabled"; - }; - - crypto: crypto@1700000 { - compatible = "fsl,sec-v5.4", "fsl,sec-v5.0", - "fsl,sec-v4.0"; - fsl,sec-era = <8>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x00 0x1700000 0x100000>; - reg = <0x00 0x1700000 0x0 0x100000>; - interrupts = ; - - sec_jr0: jr@10000 { - compatible = "fsl,sec-v5.4-job-ring", - "fsl,sec-v5.0-job-ring", - "fsl,sec-v4.0-job-ring"; - reg = <0x10000 0x10000>; - interrupts = ; - }; - - sec_jr1: jr@20000 { - compatible = "fsl,sec-v5.4-job-ring", - "fsl,sec-v5.0-job-ring", - "fsl,sec-v4.0-job-ring"; - reg = <0x20000 0x10000>; - interrupts = ; - }; - - sec_jr2: jr@30000 { - compatible = "fsl,sec-v5.4-job-ring", - "fsl,sec-v5.0-job-ring", - "fsl,sec-v4.0-job-ring"; - reg = <0x30000 0x10000>; - interrupts = ; - }; - - sec_jr3: jr@40000 { - compatible = "fsl,sec-v5.4-job-ring", - "fsl,sec-v5.0-job-ring", - "fsl,sec-v4.0-job-ring"; - reg = <0x40000 0x10000>; - interrupts = ; - }; - - rtic@60000 { - compatible = "fsl,sec-v5.4-rtic", - "fsl,sec-v5.0-rtic", - "fsl,sec-v4.0-rtic"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x60000 0x100 0x60e00 0x18>; - ranges = <0x0 0x60100 0x500>; - - rtic_a: rtic-a@0 { - compatible = "fsl,sec-v5.4-rtic-memory", - "fsl,sec-v5.0-rtic-memory", - "fsl,sec-v4.0-rtic-memory"; - reg = <0x00 0x20 0x100 0x100>; - }; - - rtic_b: rtic-b@20 { - compatible = "fsl,sec-v5.4-rtic-memory", - "fsl,sec-v5.0-rtic-memory", - "fsl,sec-v4.0-rtic-memory"; - reg = <0x20 0x20 0x200 0x100>; - }; - - rtic_c: rtic-c@40 { - compatible = "fsl,sec-v5.4-rtic-memory", - "fsl,sec-v5.0-rtic-memory", - "fsl,sec-v4.0-rtic-memory"; - reg = <0x40 0x20 0x300 0x100>; - }; - - rtic_d: rtic-d@60 { - compatible = "fsl,sec-v5.4-rtic-memory", - "fsl,sec-v5.0-rtic-memory", - "fsl,sec-v4.0-rtic-memory"; - reg = <0x60 0x20 0x400 0x100>; - }; - }; - }; - - sec_mon: sec_mon@1e90000 { - compatible = "fsl,sec-v5.4-mon", "fsl,sec-v5.0-mon", - "fsl,sec-v4.0-mon"; - reg = <0x0 0x1e90000 0x0 0x10000>; - interrupts = , - ; - }; - - dcfg: dcfg@1ee0000 { - compatible = "fsl,ls1012a-dcfg", - "syscon"; - reg = <0x0 0x1ee0000 0x0 0x10000>; - big-endian; - }; - - clockgen: clocking@1ee1000 { - compatible = "fsl,ls1012a-clockgen"; - reg = <0x0 0x1ee1000 0x0 0x1000>; - #clock-cells = <2>; - clocks = <&sysclk &coreclk>; - clock-names = "sysclk", "coreclk"; - }; - - tmu: tmu@1f00000 { - compatible = "fsl,qoriq-tmu"; - reg = <0x0 0x1f00000 0x0 0x10000>; - interrupts = <0 33 0x4>; - fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>; - fsl,tmu-calibration = <0x00000000 0x00000026 - 0x00000001 0x0000002d - 0x00000002 0x00000032 - 0x00000003 0x00000039 - 0x00000004 0x0000003f - 0x00000005 0x00000046 - 0x00000006 0x0000004d - 0x00000007 0x00000054 - 0x00000008 0x0000005a - 0x00000009 0x00000061 - 0x0000000a 0x0000006a - 0x0000000b 0x00000071 - - 0x00010000 0x00000025 - 0x00010001 0x0000002c - 0x00010002 0x00000035 - 0x00010003 0x0000003d - 0x00010004 0x00000045 - 0x00010005 0x0000004e - 0x00010006 0x00000057 - 0x00010007 0x00000061 - 0x00010008 0x0000006b - 0x00010009 0x00000076 - - 0x00020000 0x00000029 - 0x00020001 0x00000033 - 0x00020002 0x0000003d - 0x00020003 0x00000049 - 0x00020004 0x00000056 - 0x00020005 0x00000061 - 0x00020006 0x0000006d - - 0x00030000 0x00000021 - 0x00030001 0x0000002a - 0x00030002 0x0000003c - 0x00030003 0x0000004e>; - big-endian; - #thermal-sensor-cells = <1>; - }; - - i2c0: i2c@2180000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2180000 0x0 0x10000>; - interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clockgen 4 3>; - status = "disabled"; - }; - - i2c1: i2c@2190000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2190000 0x0 0x10000>; - interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clockgen 4 3>; - status = "disabled"; - }; - - dspi: spi@2100000 { - compatible = "fsl,ls1012a-dspi", "fsl,ls1021a-v1.0-dspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2100000 0x0 0x10000>; - interrupts = <0 64 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "dspi"; - clocks = <&clockgen 4 0>; - spi-num-chipselects = <5>; - big-endian; - status = "disabled"; - }; - - duart0: serial@21c0500 { - compatible = "fsl,ns16550", "ns16550a"; - reg = <0x00 0x21c0500 0x0 0x100>; - interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clockgen 4 0>; - status = "disabled"; - }; - - duart1: serial@21c0600 { - compatible = "fsl,ns16550", "ns16550a"; - reg = <0x00 0x21c0600 0x0 0x100>; - interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clockgen 4 0>; - status = "disabled"; - }; - - gpio0: gpio@2300000 { - compatible = "fsl,qoriq-gpio"; - reg = <0x0 0x2300000 0x0 0x10000>; - interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio@2310000 { - compatible = "fsl,qoriq-gpio"; - reg = <0x0 0x2310000 0x0 0x10000>; - interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - wdog0: wdog@2ad0000 { - compatible = "fsl,ls1012a-wdt", - "fsl,imx21-wdt"; - reg = <0x0 0x2ad0000 0x0 0x10000>; - interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clockgen 4 0>; - big-endian; - }; - - sai1: sai@2b50000 { - #sound-dai-cells = <0>; - compatible = "fsl,vf610-sai"; - reg = <0x0 0x2b50000 0x0 0x10000>; - interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clockgen 4 3>, <&clockgen 4 3>, - <&clockgen 4 3>, <&clockgen 4 3>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dma-names = "tx", "rx"; - dmas = <&edma0 1 47>, - <&edma0 1 46>; - status = "disabled"; - }; - - sai2: sai@2b60000 { - #sound-dai-cells = <0>; - compatible = "fsl,vf610-sai"; - reg = <0x0 0x2b60000 0x0 0x10000>; - interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clockgen 4 3>, <&clockgen 4 3>, - <&clockgen 4 3>, <&clockgen 4 3>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dma-names = "tx", "rx"; - dmas = <&edma0 1 45>, - <&edma0 1 44>; - status = "disabled"; - }; - - edma0: edma@2c00000 { - #dma-cells = <2>; - compatible = "fsl,vf610-edma"; - reg = <0x0 0x2c00000 0x0 0x10000>, - <0x0 0x2c10000 0x0 0x10000>, - <0x0 0x2c20000 0x0 0x10000>; - interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>, - <0 103 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "edma-tx", "edma-err"; - dma-channels = <32>; - big-endian; - clock-names = "dmamux0", "dmamux1"; - clocks = <&clockgen 4 3>, - <&clockgen 4 3>; - }; - - usb0: usb3@2f00000 { - compatible = "snps,dwc3"; - reg = <0x0 0x2f00000 0x0 0x10000>; - interrupts = <0 60 0x4>; - dr_mode = "host"; - snps,quirk-frame-length-adjustment = <0x20>; - snps,dis_rxdet_inp3_quirk; - snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; - }; - - sata: sata@3200000 { - compatible = "fsl,ls1012a-ahci", "fsl,ls1043a-ahci"; - reg = <0x0 0x3200000 0x0 0x10000>, - <0x0 0x20140520 0x0 0x4>; - reg-names = "ahci", "sata-ecc"; - interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clockgen 4 0>; - dma-coherent; - status = "disabled"; - }; - - usb1: usb2@8600000 { - compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr"; - reg = <0x0 0x8600000 0x0 0x1000>; - interrupts = <0 139 0x4>; - dr_mode = "host"; - phy_type = "ulpi"; - }; - - msi: msi-controller1@1572000 { - compatible = "fsl,ls1012a-msi"; - reg = <0x0 0x1572000 0x0 0x8>; - msi-controller; - interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>; - }; - - pcie: pcie@3400000 { - compatible = "fsl,ls1012a-pcie"; - reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ - 0x40 0x00000000 0x0 0x00002000>; /* configuration space */ - reg-names = "regs", "config"; - interrupts = <0 118 0x4>, /* controller interrupt */ - <0 117 0x4>; /* PME interrupt */ - interrupt-names = "aer", "pme"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - num-viewport = <2>; - bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */ - 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ - msi-parent = <&msi>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0000 0 0 1 &gic 0 110 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 2 &gic 0 111 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 3 &gic 0 112 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 4 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - }; - - firmware { - optee { - compatible = "linaro,optee-tz"; - method = "smc"; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/freescale/fsl-ls1028a-qds.dts b/sys/gnu/dts/arm64/freescale/fsl-ls1028a-qds.dts deleted file mode 100644 index ca409d907b3..00000000000 --- a/sys/gnu/dts/arm64/freescale/fsl-ls1028a-qds.dts +++ /dev/null @@ -1,236 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for NXP LS1028A QDS Board. - * - * Copyright 2018 NXP - * - * Harninder Rai - * - */ - -/dts-v1/; - -#include "fsl-ls1028a.dtsi" - -/ { - model = "LS1028A QDS Board"; - compatible = "fsl,ls1028a-qds", "fsl,ls1028a"; - - aliases { - crypto = &crypto; - gpio0 = &gpio1; - gpio1 = &gpio2; - gpio2 = &gpio3; - serial0 = &duart0; - serial1 = &duart1; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x0 0x80000000 0x1 0x00000000>; - }; - - sys_mclk: clock-mclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-name = "1P8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - sb_3v3: regulator-sb3v3 { - compatible = "regulator-fixed"; - regulator-name = "3v3_vbus"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,widgets = - "Microphone", "Microphone Jack", - "Headphone", "Headphone Jack", - "Speaker", "Speaker Ext", - "Line", "Line In Jack"; - simple-audio-card,routing = - "MIC_IN", "Microphone Jack", - "Microphone Jack", "Mic Bias", - "LINE_IN", "Line In Jack", - "Headphone Jack", "HP_OUT", - "Speaker Ext", "LINE_OUT"; - - simple-audio-card,cpu { - sound-dai = <&sai1>; - frame-master; - bitclock-master; - }; - - simple-audio-card,codec { - sound-dai = <&sgtl5000>; - frame-master; - bitclock-master; - system-clock-frequency = <25000000>; - }; - }; - - mdio-mux { - compatible = "mdio-mux-multiplexer"; - mux-controls = <&mux 0>; - mdio-parent-bus = <&enetc_mdio_pf3>; - #address-cells=<1>; - #size-cells = <0>; - - /* on-board RGMII PHY */ - mdio@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - qds_phy1: ethernet-phy@5 { - /* Atheros 8035 */ - reg = <5>; - }; - }; - }; -}; - -&duart0 { - status = "okay"; -}; - -&duart1 { - status = "okay"; -}; - -&esdhc { - status = "okay"; -}; - -&esdhc1 { - status = "okay"; -}; - -&fspi { - status = "okay"; - - mt35xu02g0: flash@0 { - compatible = "jedec,spi-nor"; - #address-cells = <1>; - #size-cells = <1>; - spi-max-frequency = <50000000>; - /* The following setting enables 1-1-8 (CMD-ADDR-DATA) mode */ - spi-rx-bus-width = <8>; /* 8 SPI Rx lines */ - spi-tx-bus-width = <1>; /* 1 SPI Tx line */ - reg = <0>; - }; -}; - -&i2c0 { - status = "okay"; - - i2c-mux@77 { - compatible = "nxp,pca9547"; - reg = <0x77>; - #address-cells = <1>; - #size-cells = <0>; - - i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x2>; - - current-monitor@40 { - compatible = "ti,ina220"; - reg = <0x40>; - shunt-resistor = <1000>; - }; - - current-monitor@41 { - compatible = "ti,ina220"; - reg = <0x41>; - shunt-resistor = <1000>; - }; - }; - - i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x3>; - - temperature-sensor@4c { - compatible = "nxp,sa56004"; - reg = <0x4c>; - vcc-supply = <&sb_3v3>; - }; - - rtc@51 { - compatible = "nxp,pcf2129"; - reg = <0x51>; - }; - - eeprom@56 { - compatible = "atmel,24c512"; - reg = <0x56>; - }; - - eeprom@57 { - compatible = "atmel,24c512"; - reg = <0x57>; - }; - }; - - i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x5>; - - sgtl5000: audio-codec@a { - #sound-dai-cells = <0>; - compatible = "fsl,sgtl5000"; - reg = <0xa>; - VDDA-supply = <®_1p8v>; - VDDIO-supply = <®_1p8v>; - clocks = <&sys_mclk>; - }; - }; - }; - - fpga@66 { - compatible = "fsl,ls1028aqds-fpga", "fsl,fpga-qixis-i2c", - "simple-mfd"; - reg = <0x66>; - - mux: mux-controller { - compatible = "reg-mux"; - #mux-control-cells = <1>; - mux-reg-masks = <0x54 0xf0>; /* 0: reg 0x54, bits 7:4 */ - }; - }; - -}; - -&enetc_port1 { - phy-handle = <&qds_phy1>; - phy-connection-type = "rgmii-id"; -}; - -&sai1 { - status = "okay"; -}; - -&sata { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/freescale/fsl-ls1028a-rdb.dts b/sys/gnu/dts/arm64/freescale/fsl-ls1028a-rdb.dts deleted file mode 100644 index afb55653850..00000000000 --- a/sys/gnu/dts/arm64/freescale/fsl-ls1028a-rdb.dts +++ /dev/null @@ -1,207 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for NXP LS1028A RDB Board. - * - * Copyright 2018 NXP - * - * Harninder Rai - * - */ - -/dts-v1/; -#include "fsl-ls1028a.dtsi" - -/ { - model = "LS1028A RDB Board"; - compatible = "fsl,ls1028a-rdb", "fsl,ls1028a"; - - aliases { - crypto = &crypto; - serial0 = &duart0; - serial1 = &duart1; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x0 0x80000000 0x1 0x0000000>; - }; - - sys_mclk: clock-mclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-name = "1P8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - sb_3v3: regulator-sb3v3 { - compatible = "regulator-fixed"; - regulator-name = "3v3_vbus"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,widgets = - "Microphone", "Microphone Jack", - "Headphone", "Headphone Jack", - "Speaker", "Speaker Ext", - "Line", "Line In Jack"; - simple-audio-card,routing = - "MIC_IN", "Microphone Jack", - "Microphone Jack", "Mic Bias", - "LINE_IN", "Line In Jack", - "Headphone Jack", "HP_OUT", - "Speaker Ext", "LINE_OUT"; - - simple-audio-card,cpu { - sound-dai = <&sai4>; - frame-master; - bitclock-master; - }; - - simple-audio-card,codec { - sound-dai = <&sgtl5000>; - frame-master; - bitclock-master; - system-clock-frequency = <25000000>; - }; - }; -}; - -&esdhc { - sd-uhs-sdr104; - sd-uhs-sdr50; - sd-uhs-sdr25; - sd-uhs-sdr12; - status = "okay"; -}; - -&esdhc1 { - mmc-hs200-1_8v; - mmc-hs400-1_8v; - bus-width = <8>; - status = "okay"; -}; - -&fspi { - status = "okay"; - - mt35xu02g0: flash@0 { - compatible = "jedec,spi-nor"; - #address-cells = <1>; - #size-cells = <1>; - spi-max-frequency = <50000000>; - /* The following setting enables 1-1-8 (CMD-ADDR-DATA) mode */ - spi-rx-bus-width = <8>; /* 8 SPI Rx lines */ - spi-tx-bus-width = <1>; /* 1 SPI Tx line */ - reg = <0>; - }; -}; - -&i2c0 { - status = "okay"; - - i2c-mux@77 { - compatible = "nxp,pca9847"; - reg = <0x77>; - #address-cells = <1>; - #size-cells = <0>; - - i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x1>; - - sgtl5000: audio-codec@a { - #sound-dai-cells = <0>; - compatible = "fsl,sgtl5000"; - reg = <0xa>; - VDDA-supply = <®_1p8v>; - VDDIO-supply = <®_1p8v>; - clocks = <&sys_mclk>; - sclk-strength = <3>; - }; - }; - - i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x02>; - - current-monitor@40 { - compatible = "ti,ina220"; - reg = <0x40>; - shunt-resistor = <500>; - }; - }; - - i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x3>; - - temperature-sensor@4c { - compatible = "nxp,sa56004"; - reg = <0x4c>; - vcc-supply = <&sb_3v3>; - }; - - rtc@51 { - compatible = "nxp,pcf2129"; - reg = <0x51>; - }; - }; - }; -}; - -&duart0 { - status = "okay"; -}; - -&duart1 { - status = "okay"; -}; - -&enetc_port0 { - phy-handle = <&sgmii_phy0>; - phy-connection-type = "sgmii"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - sgmii_phy0: ethernet-phy@2 { - reg = <0x2>; - }; - }; -}; - -&enetc_port1 { - status = "disabled"; -}; - -&sai4 { - status = "okay"; -}; - -&sata { - status = "okay"; -}; - -&usb1 { - dr_mode = "otg"; -}; diff --git a/sys/gnu/dts/arm64/freescale/fsl-ls1028a.dtsi b/sys/gnu/dts/arm64/freescale/fsl-ls1028a.dtsi deleted file mode 100644 index 55b71bb4baf..00000000000 --- a/sys/gnu/dts/arm64/freescale/fsl-ls1028a.dtsi +++ /dev/null @@ -1,747 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree Include file for NXP Layerscape-1028A family SoC. - * - * Copyright 2018 NXP - * - * Harninder Rai - * - */ - -#include -#include - -/ { - compatible = "fsl,ls1028a"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x0>; - enable-method = "psci"; - clocks = <&clockgen 1 0>; - next-level-cache = <&l2>; - cpu-idle-states = <&CPU_PW20>; - #cooling-cells = <2>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x1>; - enable-method = "psci"; - clocks = <&clockgen 1 0>; - next-level-cache = <&l2>; - cpu-idle-states = <&CPU_PW20>; - #cooling-cells = <2>; - }; - - l2: l2-cache { - compatible = "cache"; - }; - }; - - idle-states { - /* - * PSCI node is not added default, U-boot will add missing - * parts if it determines to use PSCI. - */ - entry-method = "psci"; - - CPU_PW20: cpu-pw20 { - compatible = "arm,idle-state"; - idle-state-name = "PW20"; - arm,psci-suspend-param = <0x0>; - entry-latency-us = <2000>; - exit-latency-us = <2000>; - min-residency-us = <6000>; - }; - }; - - sysclk: clock-sysclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - clock-output-names = "sysclk"; - }; - - osc_27m: clock-osc-27m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <27000000>; - clock-output-names = "phy_27m"; - }; - - dpclk: clock-controller@f1f0000 { - compatible = "fsl,ls1028a-plldig"; - reg = <0x0 0xf1f0000 0x0 0xffff>; - #clock-cells = <0>; - clocks = <&osc_27m>; - }; - - reboot { - compatible ="syscon-reboot"; - regmap = <&rst>; - offset = <0xb0>; - mask = <0x02>; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - pmu { - compatible = "arm,cortex-a72-pmu"; - interrupts = ; - }; - - gic: interrupt-controller@6000000 { - compatible= "arm,gic-v3"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - reg= <0x0 0x06000000 0 0x10000>, /* GIC Dist */ - <0x0 0x06040000 0 0x40000>; /* GIC Redistributor */ - #interrupt-cells= <3>; - interrupt-controller; - interrupts = ; - its: gic-its@6020000 { - compatible = "arm,gic-v3-its"; - msi-controller; - reg = <0x0 0x06020000 0 0x20000>;/* GIC Translater */ - }; - }; - - thermal-zones { - core-cluster { - polling-delay-passive = <1000>; - polling-delay = <5000>; - thermal-sensors = <&tmu 0>; - - trips { - core_cluster_alert: core-cluster-alert { - temperature = <85000>; - hysteresis = <2000>; - type = "passive"; - }; - - core_cluster_crit: core-cluster-crit { - temperature = <95000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&core_cluster_alert>; - cooling-device = - <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - }; - - soc: soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - ddr: memory-controller@1080000 { - compatible = "fsl,qoriq-memory-controller"; - reg = <0x0 0x1080000 0x0 0x1000>; - interrupts = ; - big-endian; - }; - - dcfg: syscon@1e00000 { - compatible = "fsl,ls1028a-dcfg", "syscon"; - reg = <0x0 0x1e00000 0x0 0x10000>; - little-endian; - }; - - rst: syscon@1e60000 { - compatible = "syscon"; - reg = <0x0 0x1e60000 0x0 0x10000>; - little-endian; - }; - - scfg: syscon@1fc0000 { - compatible = "fsl,ls1028a-scfg", "syscon"; - reg = <0x0 0x1fc0000 0x0 0x10000>; - big-endian; - }; - - clockgen: clock-controller@1300000 { - compatible = "fsl,ls1028a-clockgen"; - reg = <0x0 0x1300000 0x0 0xa0000>; - #clock-cells = <2>; - clocks = <&sysclk>; - }; - - i2c0: i2c@2000000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2000000 0x0 0x10000>; - interrupts = ; - clocks = <&clockgen 4 3>; - status = "disabled"; - }; - - i2c1: i2c@2010000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2010000 0x0 0x10000>; - interrupts = ; - clocks = <&clockgen 4 3>; - status = "disabled"; - }; - - i2c2: i2c@2020000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2020000 0x0 0x10000>; - interrupts = ; - clocks = <&clockgen 4 3>; - status = "disabled"; - }; - - i2c3: i2c@2030000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2030000 0x0 0x10000>; - interrupts = ; - clocks = <&clockgen 4 3>; - status = "disabled"; - }; - - i2c4: i2c@2040000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2040000 0x0 0x10000>; - interrupts = ; - clocks = <&clockgen 4 3>; - status = "disabled"; - }; - - i2c5: i2c@2050000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2050000 0x0 0x10000>; - interrupts = ; - clocks = <&clockgen 4 3>; - status = "disabled"; - }; - - i2c6: i2c@2060000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2060000 0x0 0x10000>; - interrupts = ; - clocks = <&clockgen 4 3>; - status = "disabled"; - }; - - i2c7: i2c@2070000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2070000 0x0 0x10000>; - interrupts = ; - clocks = <&clockgen 4 3>; - status = "disabled"; - }; - - fspi: spi@20c0000 { - compatible = "nxp,lx2160a-fspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x20c0000 0x0 0x10000>, - <0x0 0x20000000 0x0 0x10000000>; - reg-names = "fspi_base", "fspi_mmap"; - interrupts = ; - clocks = <&clockgen 4 3>, <&clockgen 4 3>; - clock-names = "fspi_en", "fspi"; - status = "disabled"; - }; - - esdhc: mmc@2140000 { - compatible = "fsl,ls1028a-esdhc", "fsl,esdhc"; - reg = <0x0 0x2140000 0x0 0x10000>; - interrupts = ; - clock-frequency = <0>; /* fixed up by bootloader */ - clocks = <&clockgen 2 1>; - voltage-ranges = <1800 1800 3300 3300>; - sdhci,auto-cmd12; - little-endian; - bus-width = <4>; - status = "disabled"; - }; - - esdhc1: mmc@2150000 { - compatible = "fsl,ls1028a-esdhc", "fsl,esdhc"; - reg = <0x0 0x2150000 0x0 0x10000>; - interrupts = ; - clock-frequency = <0>; /* fixed up by bootloader */ - clocks = <&clockgen 2 1>; - voltage-ranges = <1800 1800 3300 3300>; - sdhci,auto-cmd12; - broken-cd; - little-endian; - bus-width = <4>; - status = "disabled"; - }; - - duart0: serial@21c0500 { - compatible = "fsl,ns16550", "ns16550a"; - reg = <0x00 0x21c0500 0x0 0x100>; - interrupts = ; - clocks = <&clockgen 4 1>; - status = "disabled"; - }; - - duart1: serial@21c0600 { - compatible = "fsl,ns16550", "ns16550a"; - reg = <0x00 0x21c0600 0x0 0x100>; - interrupts = ; - clocks = <&clockgen 4 1>; - status = "disabled"; - }; - - edma0: dma-controller@22c0000 { - #dma-cells = <2>; - compatible = "fsl,ls1028a-edma"; - reg = <0x0 0x22c0000 0x0 0x10000>, - <0x0 0x22d0000 0x0 0x10000>, - <0x0 0x22e0000 0x0 0x10000>; - interrupts = , - ; - interrupt-names = "edma-tx", "edma-err"; - dma-channels = <32>; - clock-names = "dmamux0", "dmamux1"; - clocks = <&clockgen 4 1>, - <&clockgen 4 1>; - }; - - gpio1: gpio@2300000 { - compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; - reg = <0x0 0x2300000 0x0 0x10000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - little-endian; - }; - - gpio2: gpio@2310000 { - compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; - reg = <0x0 0x2310000 0x0 0x10000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - little-endian; - }; - - gpio3: gpio@2320000 { - compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; - reg = <0x0 0x2320000 0x0 0x10000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - little-endian; - }; - - usb0: usb@3100000 { - compatible = "fsl,ls1028a-dwc3", "snps,dwc3"; - reg = <0x0 0x3100000 0x0 0x10000>; - interrupts = ; - dr_mode = "host"; - snps,dis_rxdet_inp3_quirk; - snps,quirk-frame-length-adjustment = <0x20>; - snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; - }; - - usb1: usb@3110000 { - compatible = "fsl,ls1028a-dwc3", "snps,dwc3"; - reg = <0x0 0x3110000 0x0 0x10000>; - interrupts = ; - dr_mode = "host"; - snps,dis_rxdet_inp3_quirk; - snps,quirk-frame-length-adjustment = <0x20>; - snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; - }; - - sata: sata@3200000 { - compatible = "fsl,ls1028a-ahci"; - reg = <0x0 0x3200000 0x0 0x10000>, - <0x7 0x100520 0x0 0x4>; - reg-names = "ahci", "sata-ecc"; - interrupts = ; - clocks = <&clockgen 4 1>; - status = "disabled"; - }; - - smmu: iommu@5000000 { - compatible = "arm,mmu-500"; - reg = <0 0x5000000 0 0x800000>; - #global-interrupts = <8>; - #iommu-cells = <1>; - stream-match-mask = <0x7c00>; - /* global secure fault */ - interrupts = , - /* combined secure interrupt */ - , - /* global non-secure fault */ - , - /* combined non-secure interrupt */ - , - /* performance counter interrupts 0-7 */ - , , - , , - /* per context interrupt, 64 interrupts */ - , , - , , - , , - , , - , , - , , - , , - , , - , , - , , - , , - , , - , , - , , - , , - , , - , , - , , - , , - , , - , , - , , - , , - , , - , , - , , - , , - , , - , , - , , - , , - , ; - }; - - crypto: crypto@8000000 { - compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; - fsl,sec-era = <10>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x00 0x8000000 0x100000>; - reg = <0x00 0x8000000 0x0 0x100000>; - interrupts = ; - dma-coherent; - - sec_jr0: jr@10000 { - compatible = "fsl,sec-v5.0-job-ring", - "fsl,sec-v4.0-job-ring"; - reg = <0x10000 0x10000>; - interrupts = ; - }; - - sec_jr1: jr@20000 { - compatible = "fsl,sec-v5.0-job-ring", - "fsl,sec-v4.0-job-ring"; - reg = <0x20000 0x10000>; - interrupts = ; - }; - - sec_jr2: jr@30000 { - compatible = "fsl,sec-v5.0-job-ring", - "fsl,sec-v4.0-job-ring"; - reg = <0x30000 0x10000>; - interrupts = ; - }; - - sec_jr3: jr@40000 { - compatible = "fsl,sec-v5.0-job-ring", - "fsl,sec-v4.0-job-ring"; - reg = <0x40000 0x10000>; - interrupts = ; - }; - }; - - qdma: dma-controller@8380000 { - compatible = "fsl,ls1028a-qdma", "fsl,ls1021a-qdma"; - reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */ - <0x0 0x8390000 0x0 0x10000>, /* Status regs */ - <0x0 0x83a0000 0x0 0x40000>; /* Block regs */ - interrupts = , - , - , - , - ; - interrupt-names = "qdma-error", "qdma-queue0", - "qdma-queue1", "qdma-queue2", "qdma-queue3"; - dma-channels = <8>; - block-number = <1>; - block-offset = <0x10000>; - fsl,dma-queues = <2>; - status-sizes = <64>; - queue-sizes = <64 64>; - }; - - cluster1_core0_watchdog: watchdog@c000000 { - compatible = "arm,sp805", "arm,primecell"; - reg = <0x0 0xc000000 0x0 0x1000>; - clocks = <&clockgen 4 15>, <&clockgen 4 15>; - clock-names = "apb_pclk", "wdog_clk"; - }; - - cluster1_core1_watchdog: watchdog@c010000 { - compatible = "arm,sp805", "arm,primecell"; - reg = <0x0 0xc010000 0x0 0x1000>; - clocks = <&clockgen 4 15>, <&clockgen 4 15>; - clock-names = "apb_pclk", "wdog_clk"; - }; - - sai1: audio-controller@f100000 { - #sound-dai-cells = <0>; - compatible = "fsl,vf610-sai"; - reg = <0x0 0xf100000 0x0 0x10000>; - interrupts = ; - clocks = <&clockgen 4 1>, <&clockgen 4 1>, - <&clockgen 4 1>, <&clockgen 4 1>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dma-names = "tx", "rx"; - dmas = <&edma0 1 4>, - <&edma0 1 3>; - fsl,sai-asynchronous; - status = "disabled"; - }; - - sai2: audio-controller@f110000 { - #sound-dai-cells = <0>; - compatible = "fsl,vf610-sai"; - reg = <0x0 0xf110000 0x0 0x10000>; - interrupts = ; - clocks = <&clockgen 4 1>, <&clockgen 4 1>, - <&clockgen 4 1>, <&clockgen 4 1>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dma-names = "tx", "rx"; - dmas = <&edma0 1 6>, - <&edma0 1 5>; - fsl,sai-asynchronous; - status = "disabled"; - }; - - sai3: audio-controller@f120000 { - #sound-dai-cells = <0>; - compatible = "fsl,vf610-sai"; - reg = <0x0 0xf120000 0x0 0x10000>; - interrupts = ; - clocks = <&clockgen 4 1>, <&clockgen 4 1>, - <&clockgen 4 1>, <&clockgen 4 1>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dma-names = "tx", "rx"; - dmas = <&edma0 1 8>, - <&edma0 1 7>; - fsl,sai-asynchronous; - status = "disabled"; - }; - - sai4: audio-controller@f130000 { - #sound-dai-cells = <0>; - compatible = "fsl,vf610-sai"; - reg = <0x0 0xf130000 0x0 0x10000>; - interrupts = ; - clocks = <&clockgen 4 1>, <&clockgen 4 1>, - <&clockgen 4 1>, <&clockgen 4 1>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dma-names = "tx", "rx"; - dmas = <&edma0 1 10>, - <&edma0 1 9>; - fsl,sai-asynchronous; - status = "disabled"; - }; - - sai5: audio-controller@f140000 { - #sound-dai-cells = <0>; - compatible = "fsl,vf610-sai"; - reg = <0x0 0xf140000 0x0 0x10000>; - interrupts = ; - clocks = <&clockgen 4 1>, <&clockgen 4 1>, - <&clockgen 4 1>, <&clockgen 4 1>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dma-names = "tx", "rx"; - dmas = <&edma0 1 12>, - <&edma0 1 11>; - fsl,sai-asynchronous; - status = "disabled"; - }; - - sai6: audio-controller@f150000 { - #sound-dai-cells = <0>; - compatible = "fsl,vf610-sai"; - reg = <0x0 0xf150000 0x0 0x10000>; - interrupts = ; - clocks = <&clockgen 4 1>, <&clockgen 4 1>, - <&clockgen 4 1>, <&clockgen 4 1>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dma-names = "tx", "rx"; - dmas = <&edma0 1 14>, - <&edma0 1 13>; - fsl,sai-asynchronous; - status = "disabled"; - }; - - tmu: tmu@1f80000 { - compatible = "fsl,qoriq-tmu"; - reg = <0x0 0x1f80000 0x0 0x10000>; - interrupts = <0 23 0x4>; - fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>; - fsl,tmu-calibration = <0x00000000 0x00000024 - 0x00000001 0x0000002b - 0x00000002 0x00000031 - 0x00000003 0x00000038 - 0x00000004 0x0000003f - 0x00000005 0x00000045 - 0x00000006 0x0000004c - 0x00000007 0x00000053 - 0x00000008 0x00000059 - 0x00000009 0x00000060 - 0x0000000a 0x00000066 - 0x0000000b 0x0000006d - - 0x00010000 0x0000001c - 0x00010001 0x00000024 - 0x00010002 0x0000002c - 0x00010003 0x00000035 - 0x00010004 0x0000003d - 0x00010005 0x00000045 - 0x00010006 0x0000004d - 0x00010007 0x00000055 - 0x00010008 0x0000005e - 0x00010009 0x00000066 - 0x0001000a 0x0000006e - - 0x00020000 0x00000018 - 0x00020001 0x00000022 - 0x00020002 0x0000002d - 0x00020003 0x00000038 - 0x00020004 0x00000043 - 0x00020005 0x0000004d - 0x00020006 0x00000058 - 0x00020007 0x00000063 - 0x00020008 0x0000006e - - 0x00030000 0x00000010 - 0x00030001 0x0000001c - 0x00030002 0x00000029 - 0x00030003 0x00000036 - 0x00030004 0x00000042 - 0x00030005 0x0000004f - 0x00030006 0x0000005b - 0x00030007 0x00000068>; - little-endian; - #thermal-sensor-cells = <1>; - }; - - pcie@1f0000000 { /* Integrated Endpoint Root Complex */ - compatible = "pci-host-ecam-generic"; - reg = <0x01 0xf0000000 0x0 0x100000>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - msi-parent = <&its>; - device_type = "pci"; - bus-range = <0x0 0x0>; - dma-coherent; - msi-map = <0 &its 0x17 0xe>; - iommu-map = <0 &smmu 0x17 0xe>; - /* PF0-6 BAR0 - non-prefetchable memory */ - ranges = <0x82000000 0x0 0x00000000 0x1 0xf8000000 0x0 0x160000 - /* PF0-6 BAR2 - prefetchable memory */ - 0xc2000000 0x0 0x00000000 0x1 0xf8160000 0x0 0x070000 - /* PF0: VF0-1 BAR0 - non-prefetchable memory */ - 0x82000000 0x0 0x00000000 0x1 0xf81d0000 0x0 0x020000 - /* PF0: VF0-1 BAR2 - prefetchable memory */ - 0xc2000000 0x0 0x00000000 0x1 0xf81f0000 0x0 0x020000 - /* PF1: VF0-1 BAR0 - non-prefetchable memory */ - 0x82000000 0x0 0x00000000 0x1 0xf8210000 0x0 0x020000 - /* PF1: VF0-1 BAR2 - prefetchable memory */ - 0xc2000000 0x0 0x00000000 0x1 0xf8230000 0x0 0x020000>; - - enetc_port0: ethernet@0,0 { - compatible = "fsl,enetc"; - reg = <0x000000 0 0 0 0>; - }; - enetc_port1: ethernet@0,1 { - compatible = "fsl,enetc"; - reg = <0x000100 0 0 0 0>; - }; - enetc_mdio_pf3: mdio@0,3 { - compatible = "fsl,enetc-mdio"; - reg = <0x000300 0 0 0 0>; - #address-cells = <1>; - #size-cells = <0>; - }; - ethernet@0,4 { - compatible = "fsl,enetc-ptp"; - reg = <0x000400 0 0 0 0>; - clocks = <&clockgen 4 0>; - little-endian; - }; - }; - }; - - malidp0: display@f080000 { - compatible = "arm,mali-dp500"; - reg = <0x0 0xf080000 0x0 0x10000>; - interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>, - <0 223 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "DE", "SE"; - clocks = <&dpclk>, <&clockgen 2 2>, <&clockgen 2 2>, - <&clockgen 2 2>; - clock-names = "pxlclk", "mclk", "aclk", "pclk"; - arm,malidp-output-port-lines = /bits/ 8 <8 8 8>; - arm,malidp-arqos-value = <0xd000d000>; - - port { - dp0_out: endpoint { - - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/freescale/fsl-ls1043-post.dtsi b/sys/gnu/dts/arm64/freescale/fsl-ls1043-post.dtsi deleted file mode 100644 index d237162a874..00000000000 --- a/sys/gnu/dts/arm64/freescale/fsl-ls1043-post.dtsi +++ /dev/null @@ -1,46 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * QorIQ FMan v3 device tree nodes for ls1043 - * - * Copyright 2015-2016 Freescale Semiconductor Inc. - */ - -&soc { - -/* include used FMan blocks */ -#include "qoriq-fman3-0.dtsi" -#include "qoriq-fman3-0-1g-0.dtsi" -#include "qoriq-fman3-0-1g-1.dtsi" -#include "qoriq-fman3-0-1g-2.dtsi" -#include "qoriq-fman3-0-1g-3.dtsi" -#include "qoriq-fman3-0-1g-4.dtsi" -#include "qoriq-fman3-0-1g-5.dtsi" -#include "qoriq-fman3-0-10g-0.dtsi" - -}; - -&fman0 { - fsl,erratum-a050385; - - /* these aliases provide the FMan ports mapping */ - enet0: ethernet@e0000 { - }; - - enet1: ethernet@e2000 { - }; - - enet2: ethernet@e4000 { - }; - - enet3: ethernet@e6000 { - }; - - enet4: ethernet@e8000 { - }; - - enet5: ethernet@ea000 { - }; - - enet6: ethernet@f0000 { - }; -}; diff --git a/sys/gnu/dts/arm64/freescale/fsl-ls1043a-qds.dts b/sys/gnu/dts/arm64/freescale/fsl-ls1043a-qds.dts deleted file mode 100644 index 1aac81da7e3..00000000000 --- a/sys/gnu/dts/arm64/freescale/fsl-ls1043a-qds.dts +++ /dev/null @@ -1,151 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree Include file for Freescale Layerscape-1043A family SoC. - * - * Copyright 2014-2015 Freescale Semiconductor, Inc. - * Copyright 2018 NXP - * - * Mingkai Hu - */ - -/dts-v1/; -#include "fsl-ls1043a.dtsi" - -/ { - model = "LS1043A QDS Board"; - compatible = "fsl,ls1043a-qds", "fsl,ls1043a"; - - aliases { - gpio0 = &gpio1; - gpio1 = &gpio2; - gpio2 = &gpio3; - gpio3 = &gpio4; - serial0 = &duart0; - serial1 = &duart1; - serial2 = &duart2; - serial3 = &duart3; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&duart0 { - status = "okay"; -}; - -&duart1 { - status = "okay"; -}; - -&ifc { - #address-cells = <2>; - #size-cells = <1>; - /* NOR, NAND Flashes and FPGA on board */ - ranges = <0x0 0x0 0x0 0x60000000 0x08000000 - 0x1 0x0 0x0 0x7e800000 0x00010000 - 0x2 0x0 0x0 0x7fb00000 0x00000100>; - status = "okay"; - - nor@0,0 { - compatible = "cfi-flash"; - reg = <0x0 0x0 0x8000000>; - big-endian; - bank-width = <2>; - device-width = <1>; - }; - - nand@1,0 { - compatible = "fsl,ifc-nand"; - reg = <0x1 0x0 0x10000>; - }; - - fpga: board-control@2,0 { - compatible = "fsl,ls1043aqds-fpga", "fsl,fpga-qixis"; - reg = <0x2 0x0 0x0000100>; - }; -}; - -&i2c0 { - status = "okay"; - - pca9547@77 { - compatible = "nxp,pca9547"; - reg = <0x77>; - #address-cells = <1>; - #size-cells = <0>; - - i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0>; - - rtc@68 { - compatible = "dallas,ds3232"; - reg = <0x68>; - /* IRQ10_B */ - interrupts = <0 150 0x4>; - }; - }; - - i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x2>; - - ina220@40 { - compatible = "ti,ina220"; - reg = <0x40>; - shunt-resistor = <1000>; - }; - - ina220@41 { - compatible = "ti,ina220"; - reg = <0x41>; - shunt-resistor = <1000>; - }; - }; - - i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x3>; - - eeprom@56 { - compatible = "atmel,24c512"; - reg = <0x56>; - }; - - eeprom@57 { - compatible = "atmel,24c512"; - reg = <0x57>; - }; - - temp-sensor@4c { - compatible = "adi,adt7461a"; - reg = <0x4c>; - }; - }; - }; -}; - -&lpuart0 { - status = "okay"; -}; - -&qspi { - status = "okay"; - - qflash0: flash@0 { - compatible = "spansion,m25p80"; - #address-cells = <1>; - #size-cells = <1>; - spi-max-frequency = <20000000>; - spi-rx-bus-width = <4>; - spi-tx-bus-width = <4>; - reg = <0>; - }; -}; - -#include "fsl-ls1043-post.dtsi" diff --git a/sys/gnu/dts/arm64/freescale/fsl-ls1043a-rdb.dts b/sys/gnu/dts/arm64/freescale/fsl-ls1043a-rdb.dts deleted file mode 100644 index dde50c88f5e..00000000000 --- a/sys/gnu/dts/arm64/freescale/fsl-ls1043a-rdb.dts +++ /dev/null @@ -1,178 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree Include file for Freescale Layerscape-1043A family SoC. - * - * Copyright 2014-2015 Freescale Semiconductor, Inc. - * Copyright 2018 NXP - * - * Mingkai Hu - */ - -/dts-v1/; -#include "fsl-ls1043a.dtsi" - -/ { - model = "LS1043A RDB Board"; - - aliases { - serial0 = &duart0; - serial1 = &duart1; - serial2 = &duart2; - serial3 = &duart3; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&i2c0 { - status = "okay"; - ina220@40 { - compatible = "ti,ina220"; - reg = <0x40>; - shunt-resistor = <1000>; - }; - adt7461a@4c { - compatible = "adi,adt7461"; - reg = <0x4c>; - }; - eeprom@52 { - compatible = "atmel,24c512"; - reg = <0x52>; - }; - eeprom@53 { - compatible = "atmel,24c512"; - reg = <0x53>; - }; - rtc@68 { - compatible = "pericom,pt7c4338"; - reg = <0x68>; - }; -}; - -&ifc { - status = "okay"; - #address-cells = <2>; - #size-cells = <1>; - /* NOR, NAND Flashes and FPGA on board */ - ranges = <0x0 0x0 0x0 0x60000000 0x08000000 - 0x1 0x0 0x0 0x7e800000 0x00010000 - 0x2 0x0 0x0 0x7fb00000 0x00000100>; - - nor@0,0 { - compatible = "cfi-flash"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x0 0x0 0x8000000>; - big-endian; - bank-width = <2>; - device-width = <1>; - }; - - nand@1,0 { - compatible = "fsl,ifc-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x1 0x0 0x10000>; - }; - - cpld: board-control@2,0 { - compatible = "fsl,ls1043ardb-cpld"; - reg = <0x2 0x0 0x0000100>; - }; -}; - -&dspi0 { - bus-num = <0>; - status = "okay"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "n25q128a13", "jedec,spi-nor"; /* 16MB */ - reg = <0>; - spi-max-frequency = <1000000>; /* input clock */ - }; -}; - -&duart0 { - status = "okay"; -}; - -&duart1 { - status = "okay"; -}; - -#include "fsl-ls1043-post.dtsi" - -&fman0 { - ethernet@e0000 { - phy-handle = <&qsgmii_phy1>; - phy-connection-type = "qsgmii"; - }; - - ethernet@e2000 { - phy-handle = <&qsgmii_phy2>; - phy-connection-type = "qsgmii"; - }; - - ethernet@e4000 { - phy-handle = <&rgmii_phy1>; - phy-connection-type = "rgmii-id"; - }; - - ethernet@e6000 { - phy-handle = <&rgmii_phy2>; - phy-connection-type = "rgmii-id"; - }; - - ethernet@e8000 { - phy-handle = <&qsgmii_phy3>; - phy-connection-type = "qsgmii"; - }; - - ethernet@ea000 { - phy-handle = <&qsgmii_phy4>; - phy-connection-type = "qsgmii"; - }; - - ethernet@f0000 { /* 10GEC1 */ - phy-handle = <&aqr105_phy>; - phy-connection-type = "xgmii"; - }; - - mdio@fc000 { - rgmii_phy1: ethernet-phy@1 { - reg = <0x1>; - }; - - rgmii_phy2: ethernet-phy@2 { - reg = <0x2>; - }; - - qsgmii_phy1: ethernet-phy@4 { - reg = <0x4>; - }; - - qsgmii_phy2: ethernet-phy@5 { - reg = <0x5>; - }; - - qsgmii_phy3: ethernet-phy@6 { - reg = <0x6>; - }; - - qsgmii_phy4: ethernet-phy@7 { - reg = <0x7>; - }; - }; - - mdio@fd000 { - aqr105_phy: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c45"; - interrupts = <0 132 4>; - reg = <0x1>; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/freescale/fsl-ls1043a.dtsi b/sys/gnu/dts/arm64/freescale/fsl-ls1043a.dtsi deleted file mode 100644 index c084c7a4b6a..00000000000 --- a/sys/gnu/dts/arm64/freescale/fsl-ls1043a.dtsi +++ /dev/null @@ -1,779 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree Include file for Freescale Layerscape-1043A family SoC. - * - * Copyright 2014-2015 Freescale Semiconductor, Inc. - * Copyright 2018 NXP - * - * Mingkai Hu - */ - -#include -#include - -/ { - compatible = "fsl,ls1043a"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - crypto = &crypto; - fman0 = &fman0; - ethernet0 = &enet0; - ethernet1 = &enet1; - ethernet2 = &enet2; - ethernet3 = &enet3; - ethernet4 = &enet4; - ethernet5 = &enet5; - ethernet6 = &enet6; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - /* - * We expect the enable-method for cpu's to be "psci", but this - * is dependent on the SoC FW, which will fill this in. - * - * Currently supported enable-method is psci v0.2 - */ - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0>; - clocks = <&clockgen 1 0>; - next-level-cache = <&l2>; - cpu-idle-states = <&CPU_PH20>; - #cooling-cells = <2>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x1>; - clocks = <&clockgen 1 0>; - next-level-cache = <&l2>; - cpu-idle-states = <&CPU_PH20>; - #cooling-cells = <2>; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x2>; - clocks = <&clockgen 1 0>; - next-level-cache = <&l2>; - cpu-idle-states = <&CPU_PH20>; - #cooling-cells = <2>; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x3>; - clocks = <&clockgen 1 0>; - next-level-cache = <&l2>; - cpu-idle-states = <&CPU_PH20>; - #cooling-cells = <2>; - }; - - l2: l2-cache { - compatible = "cache"; - }; - }; - - idle-states { - /* - * PSCI node is not added default, U-boot will add missing - * parts if it determines to use PSCI. - */ - entry-method = "psci"; - - CPU_PH20: cpu-ph20 { - compatible = "arm,idle-state"; - idle-state-name = "PH20"; - arm,psci-suspend-param = <0x0>; - entry-latency-us = <1000>; - exit-latency-us = <1000>; - min-residency-us = <3000>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x0 0x80000000 0 0x80000000>; - /* DRAM space 1, size: 2GiB DRAM */ - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - bman_fbpr: bman-fbpr { - compatible = "shared-dma-pool"; - size = <0 0x1000000>; - alignment = <0 0x1000000>; - no-map; - }; - - qman_fqd: qman-fqd { - compatible = "shared-dma-pool"; - size = <0 0x400000>; - alignment = <0 0x400000>; - no-map; - }; - - qman_pfdr: qman-pfdr { - compatible = "shared-dma-pool"; - size = <0 0x2000000>; - alignment = <0 0x2000000>; - no-map; - }; - }; - - sysclk: sysclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - clock-output-names = "sysclk"; - }; - - reboot { - compatible ="syscon-reboot"; - regmap = <&dcfg>; - offset = <0xb0>; - mask = <0x02>; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <1000>; - polling-delay = <5000>; - - thermal-sensors = <&tmu 3>; - - trips { - cpu_alert: cpu-alert { - temperature = <85000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu_crit: cpu-crit { - temperature = <95000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu_alert>; - cooling-device = - <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = <1 13 0xf08>, /* Physical Secure PPI */ - <1 14 0xf08>, /* Physical Non-Secure PPI */ - <1 11 0xf08>, /* Virtual PPI */ - <1 10 0xf08>; /* Hypervisor PPI */ - fsl,erratum-a008585; - }; - - pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = <0 106 0x4>, - <0 107 0x4>, - <0 95 0x4>, - <0 97 0x4>; - interrupt-affinity = <&cpu0>, - <&cpu1>, - <&cpu2>, - <&cpu3>; - }; - - gic: interrupt-controller@1400000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x0 0x1401000 0 0x1000>, /* GICD */ - <0x0 0x1402000 0 0x2000>, /* GICC */ - <0x0 0x1404000 0 0x2000>, /* GICH */ - <0x0 0x1406000 0 0x2000>; /* GICV */ - interrupts = <1 9 0xf08>; - }; - - soc: soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - clockgen: clocking@1ee1000 { - compatible = "fsl,ls1043a-clockgen"; - reg = <0x0 0x1ee1000 0x0 0x1000>; - #clock-cells = <2>; - clocks = <&sysclk>; - }; - - scfg: scfg@1570000 { - compatible = "fsl,ls1043a-scfg", "syscon"; - reg = <0x0 0x1570000 0x0 0x10000>; - big-endian; - }; - - crypto: crypto@1700000 { - compatible = "fsl,sec-v5.4", "fsl,sec-v5.0", - "fsl,sec-v4.0"; - fsl,sec-era = <3>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x00 0x1700000 0x100000>; - reg = <0x00 0x1700000 0x0 0x100000>; - interrupts = <0 75 0x4>; - - sec_jr0: jr@10000 { - compatible = "fsl,sec-v5.4-job-ring", - "fsl,sec-v5.0-job-ring", - "fsl,sec-v4.0-job-ring"; - reg = <0x10000 0x10000>; - interrupts = <0 71 0x4>; - }; - - sec_jr1: jr@20000 { - compatible = "fsl,sec-v5.4-job-ring", - "fsl,sec-v5.0-job-ring", - "fsl,sec-v4.0-job-ring"; - reg = <0x20000 0x10000>; - interrupts = <0 72 0x4>; - }; - - sec_jr2: jr@30000 { - compatible = "fsl,sec-v5.4-job-ring", - "fsl,sec-v5.0-job-ring", - "fsl,sec-v4.0-job-ring"; - reg = <0x30000 0x10000>; - interrupts = <0 73 0x4>; - }; - - sec_jr3: jr@40000 { - compatible = "fsl,sec-v5.4-job-ring", - "fsl,sec-v5.0-job-ring", - "fsl,sec-v4.0-job-ring"; - reg = <0x40000 0x10000>; - interrupts = <0 74 0x4>; - }; - }; - - dcfg: dcfg@1ee0000 { - compatible = "fsl,ls1043a-dcfg", "syscon"; - reg = <0x0 0x1ee0000 0x0 0x10000>; - big-endian; - }; - - ifc: ifc@1530000 { - compatible = "fsl,ifc", "simple-bus"; - reg = <0x0 0x1530000 0x0 0x10000>; - interrupts = <0 43 0x4>; - }; - - qspi: spi@1550000 { - compatible = "fsl,ls1043a-qspi", "fsl,ls1021a-qspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x1550000 0x0 0x10000>, - <0x0 0x40000000 0x0 0x4000000>; - reg-names = "QuadSPI", "QuadSPI-memory"; - interrupts = <0 99 0x4>; - clock-names = "qspi_en", "qspi"; - clocks = <&clockgen 4 0>, <&clockgen 4 0>; - status = "disabled"; - }; - - esdhc: esdhc@1560000 { - compatible = "fsl,ls1043a-esdhc", "fsl,esdhc"; - reg = <0x0 0x1560000 0x0 0x10000>; - interrupts = <0 62 0x4>; - clock-frequency = <0>; - voltage-ranges = <1800 1800 3300 3300>; - sdhci,auto-cmd12; - big-endian; - bus-width = <4>; - }; - - ddr: memory-controller@1080000 { - compatible = "fsl,qoriq-memory-controller"; - reg = <0x0 0x1080000 0x0 0x1000>; - interrupts = <0 144 0x4>; - big-endian; - }; - - tmu: tmu@1f00000 { - compatible = "fsl,qoriq-tmu"; - reg = <0x0 0x1f00000 0x0 0x10000>; - interrupts = <0 33 0x4>; - fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>; - fsl,tmu-calibration = <0x00000000 0x00000026 - 0x00000001 0x0000002d - 0x00000002 0x00000032 - 0x00000003 0x00000039 - 0x00000004 0x0000003f - 0x00000005 0x00000046 - 0x00000006 0x0000004d - 0x00000007 0x00000054 - 0x00000008 0x0000005a - 0x00000009 0x00000061 - 0x0000000a 0x0000006a - 0x0000000b 0x00000071 - - 0x00010000 0x00000025 - 0x00010001 0x0000002c - 0x00010002 0x00000035 - 0x00010003 0x0000003d - 0x00010004 0x00000045 - 0x00010005 0x0000004e - 0x00010006 0x00000057 - 0x00010007 0x00000061 - 0x00010008 0x0000006b - 0x00010009 0x00000076 - - 0x00020000 0x00000029 - 0x00020001 0x00000033 - 0x00020002 0x0000003d - 0x00020003 0x00000049 - 0x00020004 0x00000056 - 0x00020005 0x00000061 - 0x00020006 0x0000006d - - 0x00030000 0x00000021 - 0x00030001 0x0000002a - 0x00030002 0x0000003c - 0x00030003 0x0000004e>; - #thermal-sensor-cells = <1>; - }; - - qman: qman@1880000 { - compatible = "fsl,qman"; - reg = <0x0 0x1880000 0x0 0x10000>; - interrupts = ; - memory-region = <&qman_fqd &qman_pfdr>; - }; - - bman: bman@1890000 { - compatible = "fsl,bman"; - reg = <0x0 0x1890000 0x0 0x10000>; - interrupts = ; - memory-region = <&bman_fbpr>; - }; - - bportals: bman-portals@508000000 { - ranges = <0x0 0x5 0x08000000 0x8000000>; - }; - - qportals: qman-portals@500000000 { - ranges = <0x0 0x5 0x00000000 0x8000000>; - }; - - dspi0: spi@2100000 { - compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2100000 0x0 0x10000>; - interrupts = <0 64 0x4>; - clock-names = "dspi"; - clocks = <&clockgen 4 0>; - spi-num-chipselects = <5>; - big-endian; - status = "disabled"; - }; - - dspi1: spi@2110000 { - compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2110000 0x0 0x10000>; - interrupts = <0 65 0x4>; - clock-names = "dspi"; - clocks = <&clockgen 4 0>; - spi-num-chipselects = <5>; - big-endian; - status = "disabled"; - }; - - i2c0: i2c@2180000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2180000 0x0 0x10000>; - interrupts = <0 56 0x4>; - clock-names = "i2c"; - clocks = <&clockgen 4 0>; - dmas = <&edma0 1 39>, - <&edma0 1 38>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - i2c1: i2c@2190000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2190000 0x0 0x10000>; - interrupts = <0 57 0x4>; - clock-names = "i2c"; - clocks = <&clockgen 4 0>; - status = "disabled"; - }; - - i2c2: i2c@21a0000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x21a0000 0x0 0x10000>; - interrupts = <0 58 0x4>; - clock-names = "i2c"; - clocks = <&clockgen 4 0>; - status = "disabled"; - }; - - i2c3: i2c@21b0000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x21b0000 0x0 0x10000>; - interrupts = <0 59 0x4>; - clock-names = "i2c"; - clocks = <&clockgen 4 0>; - status = "disabled"; - }; - - duart0: serial@21c0500 { - compatible = "fsl,ns16550", "ns16550a"; - reg = <0x00 0x21c0500 0x0 0x100>; - interrupts = <0 54 0x4>; - clocks = <&clockgen 4 0>; - }; - - duart1: serial@21c0600 { - compatible = "fsl,ns16550", "ns16550a"; - reg = <0x00 0x21c0600 0x0 0x100>; - interrupts = <0 54 0x4>; - clocks = <&clockgen 4 0>; - }; - - duart2: serial@21d0500 { - compatible = "fsl,ns16550", "ns16550a"; - reg = <0x0 0x21d0500 0x0 0x100>; - interrupts = <0 55 0x4>; - clocks = <&clockgen 4 0>; - }; - - duart3: serial@21d0600 { - compatible = "fsl,ns16550", "ns16550a"; - reg = <0x0 0x21d0600 0x0 0x100>; - interrupts = <0 55 0x4>; - clocks = <&clockgen 4 0>; - }; - - gpio1: gpio@2300000 { - compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio"; - reg = <0x0 0x2300000 0x0 0x10000>; - interrupts = <0 66 0x4>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@2310000 { - compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio"; - reg = <0x0 0x2310000 0x0 0x10000>; - interrupts = <0 67 0x4>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio@2320000 { - compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio"; - reg = <0x0 0x2320000 0x0 0x10000>; - interrupts = <0 68 0x4>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio4: gpio@2330000 { - compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio"; - reg = <0x0 0x2330000 0x0 0x10000>; - interrupts = <0 134 0x4>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - lpuart0: serial@2950000 { - compatible = "fsl,ls1021a-lpuart"; - reg = <0x0 0x2950000 0x0 0x1000>; - interrupts = <0 48 0x4>; - clocks = <&clockgen 0 0>; - clock-names = "ipg"; - status = "disabled"; - }; - - lpuart1: serial@2960000 { - compatible = "fsl,ls1021a-lpuart"; - reg = <0x0 0x2960000 0x0 0x1000>; - interrupts = <0 49 0x4>; - clocks = <&clockgen 4 0>; - clock-names = "ipg"; - status = "disabled"; - }; - - lpuart2: serial@2970000 { - compatible = "fsl,ls1021a-lpuart"; - reg = <0x0 0x2970000 0x0 0x1000>; - interrupts = <0 50 0x4>; - clocks = <&clockgen 4 0>; - clock-names = "ipg"; - status = "disabled"; - }; - - lpuart3: serial@2980000 { - compatible = "fsl,ls1021a-lpuart"; - reg = <0x0 0x2980000 0x0 0x1000>; - interrupts = <0 51 0x4>; - clocks = <&clockgen 4 0>; - clock-names = "ipg"; - status = "disabled"; - }; - - lpuart4: serial@2990000 { - compatible = "fsl,ls1021a-lpuart"; - reg = <0x0 0x2990000 0x0 0x1000>; - interrupts = <0 52 0x4>; - clocks = <&clockgen 4 0>; - clock-names = "ipg"; - status = "disabled"; - }; - - lpuart5: serial@29a0000 { - compatible = "fsl,ls1021a-lpuart"; - reg = <0x0 0x29a0000 0x0 0x1000>; - interrupts = <0 53 0x4>; - clocks = <&clockgen 4 0>; - clock-names = "ipg"; - status = "disabled"; - }; - - wdog0: wdog@2ad0000 { - compatible = "fsl,ls1043a-wdt", "fsl,imx21-wdt"; - reg = <0x0 0x2ad0000 0x0 0x10000>; - interrupts = <0 83 0x4>; - clocks = <&clockgen 4 0>; - clock-names = "wdog"; - big-endian; - }; - - edma0: edma@2c00000 { - #dma-cells = <2>; - compatible = "fsl,vf610-edma"; - reg = <0x0 0x2c00000 0x0 0x10000>, - <0x0 0x2c10000 0x0 0x10000>, - <0x0 0x2c20000 0x0 0x10000>; - interrupts = <0 103 0x4>, - <0 103 0x4>; - interrupt-names = "edma-tx", "edma-err"; - dma-channels = <32>; - big-endian; - clock-names = "dmamux0", "dmamux1"; - clocks = <&clockgen 4 0>, - <&clockgen 4 0>; - }; - - usb0: usb3@2f00000 { - compatible = "snps,dwc3"; - reg = <0x0 0x2f00000 0x0 0x10000>; - interrupts = <0 60 0x4>; - dr_mode = "host"; - snps,quirk-frame-length-adjustment = <0x20>; - snps,dis_rxdet_inp3_quirk; - snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; - }; - - usb1: usb3@3000000 { - compatible = "snps,dwc3"; - reg = <0x0 0x3000000 0x0 0x10000>; - interrupts = <0 61 0x4>; - dr_mode = "host"; - snps,quirk-frame-length-adjustment = <0x20>; - snps,dis_rxdet_inp3_quirk; - snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; - }; - - usb2: usb3@3100000 { - compatible = "snps,dwc3"; - reg = <0x0 0x3100000 0x0 0x10000>; - interrupts = <0 63 0x4>; - dr_mode = "host"; - snps,quirk-frame-length-adjustment = <0x20>; - snps,dis_rxdet_inp3_quirk; - snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; - }; - - sata: sata@3200000 { - compatible = "fsl,ls1043a-ahci"; - reg = <0x0 0x3200000 0x0 0x10000>, - <0x0 0x20140520 0x0 0x4>; - reg-names = "ahci", "sata-ecc"; - interrupts = <0 69 0x4>; - clocks = <&clockgen 4 0>; - dma-coherent; - }; - - msi1: msi-controller1@1571000 { - compatible = "fsl,ls1043a-msi"; - reg = <0x0 0x1571000 0x0 0x8>; - msi-controller; - interrupts = <0 116 0x4>; - }; - - msi2: msi-controller2@1572000 { - compatible = "fsl,ls1043a-msi"; - reg = <0x0 0x1572000 0x0 0x8>; - msi-controller; - interrupts = <0 126 0x4>; - }; - - msi3: msi-controller3@1573000 { - compatible = "fsl,ls1043a-msi"; - reg = <0x0 0x1573000 0x0 0x8>; - msi-controller; - interrupts = <0 160 0x4>; - }; - - pcie@3400000 { - compatible = "fsl,ls1043a-pcie"; - reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ - 0x40 0x00000000 0x0 0x00002000>; /* configuration space */ - reg-names = "regs", "config"; - interrupts = <0 118 0x4>, /* controller interrupt */ - <0 117 0x4>; /* PME interrupt */ - interrupt-names = "intr", "pme"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - dma-coherent; - num-viewport = <6>; - bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */ - 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ - msi-parent = <&msi1>, <&msi2>, <&msi3>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0000 0 0 1 &gic 0 110 0x4>, - <0000 0 0 2 &gic 0 111 0x4>, - <0000 0 0 3 &gic 0 112 0x4>, - <0000 0 0 4 &gic 0 113 0x4>; - status = "disabled"; - }; - - pcie@3500000 { - compatible = "fsl,ls1043a-pcie"; - reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ - 0x48 0x00000000 0x0 0x00002000>; /* configuration space */ - reg-names = "regs", "config"; - interrupts = <0 128 0x4>, - <0 127 0x4>; - interrupt-names = "intr", "pme"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - dma-coherent; - num-viewport = <6>; - bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */ - 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ - msi-parent = <&msi1>, <&msi2>, <&msi3>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0000 0 0 1 &gic 0 120 0x4>, - <0000 0 0 2 &gic 0 121 0x4>, - <0000 0 0 3 &gic 0 122 0x4>, - <0000 0 0 4 &gic 0 123 0x4>; - status = "disabled"; - }; - - pcie@3600000 { - compatible = "fsl,ls1043a-pcie"; - reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ - 0x50 0x00000000 0x0 0x00002000>; /* configuration space */ - reg-names = "regs", "config"; - interrupts = <0 162 0x4>, - <0 161 0x4>; - interrupt-names = "intr", "pme"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - dma-coherent; - num-viewport = <6>; - bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */ - 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ - msi-parent = <&msi1>, <&msi2>, <&msi3>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0000 0 0 1 &gic 0 154 0x4>, - <0000 0 0 2 &gic 0 155 0x4>, - <0000 0 0 3 &gic 0 156 0x4>, - <0000 0 0 4 &gic 0 157 0x4>; - status = "disabled"; - }; - - qdma: dma-controller@8380000 { - compatible = "fsl,ls1021a-qdma", "fsl,ls1043a-qdma"; - reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */ - <0x0 0x8390000 0x0 0x10000>, /* Status regs */ - <0x0 0x83a0000 0x0 0x40000>; /* Block regs */ - interrupts = , - , - , - , - ; - interrupt-names = "qdma-error", "qdma-queue0", - "qdma-queue1", "qdma-queue2", "qdma-queue3"; - dma-channels = <8>; - block-number = <1>; - block-offset = <0x10000>; - fsl,dma-queues = <2>; - status-sizes = <64>; - queue-sizes = <64 64>; - big-endian; - }; - - }; - - firmware { - optee { - compatible = "linaro,optee-tz"; - method = "smc"; - }; - }; - -}; - -#include "qoriq-qman-portals.dtsi" -#include "qoriq-bman-portals.dtsi" diff --git a/sys/gnu/dts/arm64/freescale/fsl-ls1046-post.dtsi b/sys/gnu/dts/arm64/freescale/fsl-ls1046-post.dtsi deleted file mode 100644 index d6caaea57d9..00000000000 --- a/sys/gnu/dts/arm64/freescale/fsl-ls1046-post.dtsi +++ /dev/null @@ -1,48 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * QorIQ FMan v3 device tree nodes for ls1046 - * - * Copyright 2015-2016 Freescale Semiconductor Inc. - * - */ - -&soc { - -/* include used FMan blocks */ -#include "qoriq-fman3-0.dtsi" -#include "qoriq-fman3-0-1g-0.dtsi" -#include "qoriq-fman3-0-1g-1.dtsi" -#include "qoriq-fman3-0-1g-2.dtsi" -#include "qoriq-fman3-0-1g-3.dtsi" -#include "qoriq-fman3-0-1g-4.dtsi" -#include "qoriq-fman3-0-1g-5.dtsi" -#include "qoriq-fman3-0-10g-0.dtsi" -#include "qoriq-fman3-0-10g-1.dtsi" -}; - -&fman0 { - /* these aliases provide the FMan ports mapping */ - enet0: ethernet@e0000 { - }; - - enet1: ethernet@e2000 { - }; - - enet2: ethernet@e4000 { - }; - - enet3: ethernet@e6000 { - }; - - enet4: ethernet@e8000 { - }; - - enet5: ethernet@ea000 { - }; - - enet6: ethernet@f0000 { - }; - - enet7: ethernet@f2000 { - }; -}; diff --git a/sys/gnu/dts/arm64/freescale/fsl-ls1046a-frwy.dts b/sys/gnu/dts/arm64/freescale/fsl-ls1046a-frwy.dts deleted file mode 100644 index db3d303093f..00000000000 --- a/sys/gnu/dts/arm64/freescale/fsl-ls1046a-frwy.dts +++ /dev/null @@ -1,169 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree Include file for Freescale Layerscape-1046A family SoC. - * - * Copyright 2019 NXP. - * - */ - -/dts-v1/; - -#include "fsl-ls1046a.dtsi" - -/ { - model = "LS1046A FRWY Board"; - compatible = "fsl,ls1046a-frwy", "fsl,ls1046a"; - - aliases { - serial0 = &duart0; - serial1 = &duart1; - serial2 = &duart2; - serial3 = &duart3; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - sb_3v3: regulator-sb3v3 { - compatible = "regulator-fixed"; - regulator-name = "LT8642SEV-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; -}; - -&duart0 { - status = "okay"; -}; - -&duart1 { - status = "okay"; -}; - -&duart2 { - status = "okay"; -}; - -&duart3 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - i2c-mux@77 { - compatible = "nxp,pca9546"; - reg = <0x77>; - #address-cells = <1>; - #size-cells = <0>; - - i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - power-monitor@40 { - compatible = "ti,ina220"; - reg = <0x40>; - shunt-resistor = <1000>; - }; - - temperature-sensor@4c { - compatible = "nxp,sa56004"; - reg = <0x4c>; - vcc-supply = <&sb_3v3>; - }; - - rtc@51 { - compatible = "nxp,pcf2129"; - reg = <0x51>; - }; - - eeprom@52 { - compatible = "atmel,24c512"; - reg = <0x52>; - }; - - eeprom@53 { - compatible = "atmel,24c512"; - reg = <0x53>; - }; - - }; - }; -}; - -&ifc { - #address-cells = <2>; - #size-cells = <1>; - /* NAND Flash */ - ranges = <0x0 0x0 0x0 0x7e800000 0x00010000>; - status = "okay"; - - nand@0,0 { - compatible = "fsl,ifc-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x0 0x0 0x10000>; - }; - -}; - -&qspi { - status = "okay"; - - mt25qu512a0: flash@0 { - compatible = "jedec,spi-nor"; - #address-cells = <1>; - #size-cells = <1>; - spi-max-frequency = <50000000>; - spi-rx-bus-width = <4>; - spi-tx-bus-width = <1>; - reg = <0>; - }; -}; - -#include "fsl-ls1046-post.dtsi" - -&fman0 { - ethernet@e0000 { - phy-handle = <&qsgmii_phy4>; - phy-connection-type = "qsgmii"; - }; - - ethernet@e8000 { - phy-handle = <&qsgmii_phy2>; - phy-connection-type = "qsgmii"; - }; - - ethernet@ea000 { - phy-handle = <&qsgmii_phy1>; - phy-connection-type = "qsgmii"; - }; - - ethernet@f2000 { - phy-handle = <&qsgmii_phy3>; - phy-connection-type = "qsgmii"; - }; - - mdio@fd000 { - qsgmii_phy1: ethernet-phy@1c { - reg = <0x1c>; - }; - - qsgmii_phy2: ethernet-phy@1d { - reg = <0x1d>; - }; - - qsgmii_phy3: ethernet-phy@1e { - reg = <0x1e>; - }; - - qsgmii_phy4: ethernet-phy@1f { - reg = <0x1f>; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/freescale/fsl-ls1046a-qds.dts b/sys/gnu/dts/arm64/freescale/fsl-ls1046a-qds.dts deleted file mode 100644 index eec62c63daf..00000000000 --- a/sys/gnu/dts/arm64/freescale/fsl-ls1046a-qds.dts +++ /dev/null @@ -1,179 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree Include file for Freescale Layerscape-1046A family SoC. - * - * Copyright 2016 Freescale Semiconductor, Inc. - * Copyright 2018 NXP - * - * Shaohui Xie - */ - -/dts-v1/; - -#include "fsl-ls1046a.dtsi" - -/ { - model = "LS1046A QDS Board"; - compatible = "fsl,ls1046a-qds", "fsl,ls1046a"; - - aliases { - gpio0 = &gpio0; - gpio1 = &gpio1; - gpio2 = &gpio2; - gpio3 = &gpio3; - serial0 = &duart0; - serial1 = &duart1; - serial2 = &duart2; - serial3 = &duart3; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&dspi { - bus-num = <0>; - status = "okay"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "n25q128a11", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <10000000>; - }; - - flash@1 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "sst25wf040b", "jedec,spi-nor"; - spi-cpol; - spi-cpha; - reg = <1>; - spi-max-frequency = <10000000>; - }; - - flash@2 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "en25s64", "jedec,spi-nor"; - spi-cpol; - spi-cpha; - reg = <2>; - spi-max-frequency = <10000000>; - }; -}; - -&duart0 { - status = "okay"; -}; - -&duart1 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - pca9547@77 { - compatible = "nxp,pca9547"; - reg = <0x77>; - #address-cells = <1>; - #size-cells = <0>; - - i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x2>; - - ina220@40 { - compatible = "ti,ina220"; - reg = <0x40>; - shunt-resistor = <1000>; - }; - - ina220@41 { - compatible = "ti,ina220"; - reg = <0x41>; - shunt-resistor = <1000>; - }; - }; - - i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x3>; - - rtc@51 { - compatible = "nxp,pcf2129"; - reg = <0x51>; - /* IRQ10_B */ - interrupts = <0 150 0x4>; - }; - - eeprom@56 { - compatible = "atmel,24c512"; - reg = <0x56>; - }; - - eeprom@57 { - compatible = "atmel,24c512"; - reg = <0x57>; - }; - - temp-sensor@4c { - compatible = "adi,adt7461a"; - reg = <0x4c>; - }; - }; - }; -}; - -&ifc { - #address-cells = <2>; - #size-cells = <1>; - /* NOR, NAND Flashes and FPGA on board */ - ranges = <0x0 0x0 0x0 0x60000000 0x08000000 - 0x1 0x0 0x0 0x7e800000 0x00010000 - 0x2 0x0 0x0 0x7fb00000 0x00000100>; - status = "okay"; - - nor@0,0 { - compatible = "cfi-flash"; - reg = <0x0 0x0 0x8000000>; - big-endian; - bank-width = <2>; - device-width = <1>; - }; - - nand@1,0 { - compatible = "fsl,ifc-nand"; - reg = <0x1 0x0 0x10000>; - }; - - fpga: board-control@2,0 { - compatible = "fsl,ls1046aqds-fpga", "fsl,fpga-qixis"; - reg = <0x2 0x0 0x0000100>; - }; -}; - -&lpuart0 { - status = "okay"; -}; - -&qspi { - status = "okay"; - - qflash0: flash@0 { - compatible = "spansion,m25p80"; - #address-cells = <1>; - #size-cells = <1>; - spi-max-frequency = <20000000>; - spi-rx-bus-width = <4>; - spi-tx-bus-width = <4>; - reg = <0>; - }; -}; - -#include "fsl-ls1046-post.dtsi" diff --git a/sys/gnu/dts/arm64/freescale/fsl-ls1046a-rdb.dts b/sys/gnu/dts/arm64/freescale/fsl-ls1046a-rdb.dts deleted file mode 100644 index d53ccc56bb6..00000000000 --- a/sys/gnu/dts/arm64/freescale/fsl-ls1046a-rdb.dts +++ /dev/null @@ -1,187 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree Include file for Freescale Layerscape-1046A family SoC. - * - * Copyright 2016 Freescale Semiconductor, Inc. - * - * Mingkai Hu - */ - -/dts-v1/; - -#include "fsl-ls1046a.dtsi" - -/ { - model = "LS1046A RDB Board"; - compatible = "fsl,ls1046a-rdb", "fsl,ls1046a"; - - aliases { - serial0 = &duart0; - serial1 = &duart1; - serial2 = &duart2; - serial3 = &duart3; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&duart0 { - status = "okay"; -}; - -&duart1 { - status = "okay"; -}; - -&esdhc { - mmc-hs200-1_8v; - sd-uhs-sdr104; - sd-uhs-sdr50; - sd-uhs-sdr25; - sd-uhs-sdr12; -}; - -&i2c0 { - status = "okay"; - - ina220@40 { - compatible = "ti,ina220"; - reg = <0x40>; - shunt-resistor = <1000>; - }; - - temp-sensor@4c { - compatible = "adi,adt7461"; - reg = <0x4c>; - }; - - eeprom@52 { - compatible = "atmel,24c512"; - reg = <0x52>; - }; - - eeprom@53 { - compatible = "atmel,24c512"; - reg = <0x53>; - }; -}; - -&i2c3 { - status = "okay"; - - rtc@51 { - compatible = "nxp,pcf2129"; - reg = <0x51>; - }; -}; - -&ifc { - #address-cells = <2>; - #size-cells = <1>; - /* NAND Flashe and CPLD on board */ - ranges = <0x0 0x0 0x0 0x7e800000 0x00010000 - 0x2 0x0 0x0 0x7fb00000 0x00000100>; - status = "okay"; - - nand@0,0 { - compatible = "fsl,ifc-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x0 0x0 0x10000>; - }; - - cpld: board-control@2,0 { - compatible = "fsl,ls1046ardb-cpld"; - reg = <0x2 0x0 0x0000100>; - }; -}; - -&qspi { - status = "okay"; - - s25fs512s0: flash@0 { - compatible = "jedec,spi-nor"; - #address-cells = <1>; - #size-cells = <1>; - spi-max-frequency = <50000000>; - spi-rx-bus-width = <4>; - spi-tx-bus-width = <1>; - reg = <0>; - }; - - s25fs512s1: flash@1 { - compatible = "jedec,spi-nor"; - #address-cells = <1>; - #size-cells = <1>; - spi-max-frequency = <50000000>; - spi-rx-bus-width = <4>; - spi-tx-bus-width = <1>; - reg = <1>; - }; -}; - -&usb1 { - dr_mode = "otg"; -}; - -#include "fsl-ls1046-post.dtsi" - -&fman0 { - ethernet@e4000 { - phy-handle = <&rgmii_phy1>; - phy-connection-type = "rgmii-id"; - }; - - ethernet@e6000 { - phy-handle = <&rgmii_phy2>; - phy-connection-type = "rgmii-id"; - }; - - ethernet@e8000 { - phy-handle = <&sgmii_phy1>; - phy-connection-type = "sgmii"; - }; - - ethernet@ea000 { - phy-handle = <&sgmii_phy2>; - phy-connection-type = "sgmii"; - }; - - ethernet@f0000 { /* 10GEC1 */ - phy-handle = <&aqr106_phy>; - phy-connection-type = "xgmii"; - }; - - ethernet@f2000 { /* 10GEC2 */ - fixed-link = <0 1 1000 0 0>; - phy-connection-type = "xgmii"; - }; - - mdio@fc000 { - rgmii_phy1: ethernet-phy@1 { - reg = <0x1>; - }; - - rgmii_phy2: ethernet-phy@2 { - reg = <0x2>; - }; - - sgmii_phy1: ethernet-phy@3 { - reg = <0x3>; - }; - - sgmii_phy2: ethernet-phy@4 { - reg = <0x4>; - }; - }; - - mdio@fd000 { - aqr106_phy: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c45"; - interrupts = <0 131 4>; - reg = <0x0>; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/freescale/fsl-ls1046a.dtsi b/sys/gnu/dts/arm64/freescale/fsl-ls1046a.dtsi deleted file mode 100644 index d4c1da3d4bd..00000000000 --- a/sys/gnu/dts/arm64/freescale/fsl-ls1046a.dtsi +++ /dev/null @@ -1,806 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree Include file for Freescale Layerscape-1046A family SoC. - * - * Copyright 2016 Freescale Semiconductor, Inc. - * Copyright 2018 NXP - * - * Mingkai Hu - */ - -#include -#include - -/ { - compatible = "fsl,ls1046a"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - crypto = &crypto; - fman0 = &fman0; - ethernet0 = &enet0; - ethernet1 = &enet1; - ethernet2 = &enet2; - ethernet3 = &enet3; - ethernet4 = &enet4; - ethernet5 = &enet5; - ethernet6 = &enet6; - ethernet7 = &enet7; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x0>; - clocks = <&clockgen 1 0>; - next-level-cache = <&l2>; - cpu-idle-states = <&CPU_PH20>; - #cooling-cells = <2>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x1>; - clocks = <&clockgen 1 0>; - next-level-cache = <&l2>; - cpu-idle-states = <&CPU_PH20>; - #cooling-cells = <2>; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x2>; - clocks = <&clockgen 1 0>; - next-level-cache = <&l2>; - cpu-idle-states = <&CPU_PH20>; - #cooling-cells = <2>; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x3>; - clocks = <&clockgen 1 0>; - next-level-cache = <&l2>; - cpu-idle-states = <&CPU_PH20>; - #cooling-cells = <2>; - }; - - l2: l2-cache { - compatible = "cache"; - }; - }; - - idle-states { - /* - * PSCI node is not added default, U-boot will add missing - * parts if it determines to use PSCI. - */ - entry-method = "psci"; - - CPU_PH20: cpu-ph20 { - compatible = "arm,idle-state"; - idle-state-name = "PH20"; - arm,psci-suspend-param = <0x0>; - entry-latency-us = <1000>; - exit-latency-us = <1000>; - min-residency-us = <3000>; - }; - }; - - memory@80000000 { - device_type = "memory"; - /* Real size will be filled by bootloader */ - reg = <0x0 0x80000000 0x0 0x0>; - }; - - sysclk: sysclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - clock-output-names = "sysclk"; - }; - - reboot { - compatible ="syscon-reboot"; - regmap = <&dcfg>; - offset = <0xb0>; - mask = <0x02>; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <1000>; - polling-delay = <5000>; - thermal-sensors = <&tmu 3>; - - trips { - cpu_alert: cpu-alert { - temperature = <85000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu_crit: cpu-crit { - temperature = <95000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu_alert>; - cooling-device = - <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - pmu { - compatible = "arm,cortex-a72-pmu"; - interrupts = , - , - , - ; - interrupt-affinity = <&cpu0>, - <&cpu1>, - <&cpu2>, - <&cpu3>; - }; - - gic: interrupt-controller@1400000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x0 0x1410000 0 0x10000>, /* GICD */ - <0x0 0x1420000 0 0x20000>, /* GICC */ - <0x0 0x1440000 0 0x20000>, /* GICH */ - <0x0 0x1460000 0 0x20000>; /* GICV */ - interrupts = ; - }; - - soc: soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - ddr: memory-controller@1080000 { - compatible = "fsl,qoriq-memory-controller"; - reg = <0x0 0x1080000 0x0 0x1000>; - interrupts = ; - big-endian; - }; - - ifc: ifc@1530000 { - compatible = "fsl,ifc", "simple-bus"; - reg = <0x0 0x1530000 0x0 0x10000>; - interrupts = ; - status = "disabled"; - }; - - qspi: spi@1550000 { - compatible = "fsl,ls1021a-qspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x1550000 0x0 0x10000>, - <0x0 0x40000000 0x0 0x10000000>; - reg-names = "QuadSPI", "QuadSPI-memory"; - interrupts = ; - clock-names = "qspi_en", "qspi"; - clocks = <&clockgen 4 1>, <&clockgen 4 1>; - status = "disabled"; - }; - - esdhc: esdhc@1560000 { - compatible = "fsl,ls1046a-esdhc", "fsl,esdhc"; - reg = <0x0 0x1560000 0x0 0x10000>; - interrupts = ; - clocks = <&clockgen 2 1>; - voltage-ranges = <1800 1800 3300 3300>; - sdhci,auto-cmd12; - big-endian; - bus-width = <4>; - }; - - scfg: scfg@1570000 { - compatible = "fsl,ls1046a-scfg", "syscon"; - reg = <0x0 0x1570000 0x0 0x10000>; - big-endian; - }; - - crypto: crypto@1700000 { - compatible = "fsl,sec-v5.4", "fsl,sec-v5.0", - "fsl,sec-v4.0"; - fsl,sec-era = <8>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x00 0x1700000 0x100000>; - reg = <0x00 0x1700000 0x0 0x100000>; - interrupts = ; - - sec_jr0: jr@10000 { - compatible = "fsl,sec-v5.4-job-ring", - "fsl,sec-v5.0-job-ring", - "fsl,sec-v4.0-job-ring"; - reg = <0x10000 0x10000>; - interrupts = ; - }; - - sec_jr1: jr@20000 { - compatible = "fsl,sec-v5.4-job-ring", - "fsl,sec-v5.0-job-ring", - "fsl,sec-v4.0-job-ring"; - reg = <0x20000 0x10000>; - interrupts = ; - }; - - sec_jr2: jr@30000 { - compatible = "fsl,sec-v5.4-job-ring", - "fsl,sec-v5.0-job-ring", - "fsl,sec-v4.0-job-ring"; - reg = <0x30000 0x10000>; - interrupts = ; - }; - - sec_jr3: jr@40000 { - compatible = "fsl,sec-v5.4-job-ring", - "fsl,sec-v5.0-job-ring", - "fsl,sec-v4.0-job-ring"; - reg = <0x40000 0x10000>; - interrupts = ; - }; - }; - - qman: qman@1880000 { - compatible = "fsl,qman"; - reg = <0x0 0x1880000 0x0 0x10000>; - interrupts = ; - memory-region = <&qman_fqd &qman_pfdr>; - - }; - - bman: bman@1890000 { - compatible = "fsl,bman"; - reg = <0x0 0x1890000 0x0 0x10000>; - interrupts = ; - memory-region = <&bman_fbpr>; - - }; - - qportals: qman-portals@500000000 { - ranges = <0x0 0x5 0x00000000 0x8000000>; - }; - - bportals: bman-portals@508000000 { - ranges = <0x0 0x5 0x08000000 0x8000000>; - }; - - dcfg: dcfg@1ee0000 { - compatible = "fsl,ls1046a-dcfg", "syscon"; - reg = <0x0 0x1ee0000 0x0 0x10000>; - big-endian; - }; - - clockgen: clocking@1ee1000 { - compatible = "fsl,ls1046a-clockgen"; - reg = <0x0 0x1ee1000 0x0 0x1000>; - #clock-cells = <2>; - clocks = <&sysclk>; - }; - - tmu: tmu@1f00000 { - compatible = "fsl,qoriq-tmu"; - reg = <0x0 0x1f00000 0x0 0x10000>; - interrupts = <0 33 0x4>; - fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>; - fsl,tmu-calibration = - /* Calibration data group 1 */ - <0x00000000 0x00000026 - 0x00000001 0x0000002d - 0x00000002 0x00000032 - 0x00000003 0x00000039 - 0x00000004 0x0000003f - 0x00000005 0x00000046 - 0x00000006 0x0000004d - 0x00000007 0x00000054 - 0x00000008 0x0000005a - 0x00000009 0x00000061 - 0x0000000a 0x0000006a - 0x0000000b 0x00000071 - /* Calibration data group 2 */ - 0x00010000 0x00000025 - 0x00010001 0x0000002c - 0x00010002 0x00000035 - 0x00010003 0x0000003d - 0x00010004 0x00000045 - 0x00010005 0x0000004e - 0x00010006 0x00000057 - 0x00010007 0x00000061 - 0x00010008 0x0000006b - 0x00010009 0x00000076 - /* Calibration data group 3 */ - 0x00020000 0x00000029 - 0x00020001 0x00000033 - 0x00020002 0x0000003d - 0x00020003 0x00000049 - 0x00020004 0x00000056 - 0x00020005 0x00000061 - 0x00020006 0x0000006d - /* Calibration data group 4 */ - 0x00030000 0x00000021 - 0x00030001 0x0000002a - 0x00030002 0x0000003c - 0x00030003 0x0000004e>; - big-endian; - #thermal-sensor-cells = <1>; - }; - - dspi: spi@2100000 { - compatible = "fsl,ls1021a-v1.0-dspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2100000 0x0 0x10000>; - interrupts = ; - clock-names = "dspi"; - clocks = <&clockgen 4 1>; - spi-num-chipselects = <5>; - big-endian; - status = "disabled"; - }; - - i2c0: i2c@2180000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2180000 0x0 0x10000>; - interrupts = ; - clocks = <&clockgen 4 1>; - dmas = <&edma0 1 39>, - <&edma0 1 38>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - i2c1: i2c@2190000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2190000 0x0 0x10000>; - interrupts = ; - clocks = <&clockgen 4 1>; - status = "disabled"; - }; - - i2c2: i2c@21a0000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x21a0000 0x0 0x10000>; - interrupts = ; - clocks = <&clockgen 4 1>; - status = "disabled"; - }; - - i2c3: i2c@21b0000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x21b0000 0x0 0x10000>; - interrupts = ; - clocks = <&clockgen 4 1>; - status = "disabled"; - }; - - duart0: serial@21c0500 { - compatible = "fsl,ns16550", "ns16550a"; - reg = <0x00 0x21c0500 0x0 0x100>; - interrupts = ; - clocks = <&clockgen 4 1>; - status = "disabled"; - }; - - duart1: serial@21c0600 { - compatible = "fsl,ns16550", "ns16550a"; - reg = <0x00 0x21c0600 0x0 0x100>; - interrupts = ; - clocks = <&clockgen 4 1>; - status = "disabled"; - }; - - duart2: serial@21d0500 { - compatible = "fsl,ns16550", "ns16550a"; - reg = <0x0 0x21d0500 0x0 0x100>; - interrupts = ; - clocks = <&clockgen 4 1>; - status = "disabled"; - }; - - duart3: serial@21d0600 { - compatible = "fsl,ns16550", "ns16550a"; - reg = <0x0 0x21d0600 0x0 0x100>; - interrupts = ; - clocks = <&clockgen 4 1>; - status = "disabled"; - }; - - gpio0: gpio@2300000 { - compatible = "fsl,qoriq-gpio"; - reg = <0x0 0x2300000 0x0 0x10000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio@2310000 { - compatible = "fsl,qoriq-gpio"; - reg = <0x0 0x2310000 0x0 0x10000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@2320000 { - compatible = "fsl,qoriq-gpio"; - reg = <0x0 0x2320000 0x0 0x10000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio@2330000 { - compatible = "fsl,qoriq-gpio"; - reg = <0x0 0x2330000 0x0 0x10000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - lpuart0: serial@2950000 { - compatible = "fsl,ls1021a-lpuart"; - reg = <0x0 0x2950000 0x0 0x1000>; - interrupts = ; - clocks = <&clockgen 4 0>; - clock-names = "ipg"; - status = "disabled"; - }; - - lpuart1: serial@2960000 { - compatible = "fsl,ls1021a-lpuart"; - reg = <0x0 0x2960000 0x0 0x1000>; - interrupts = ; - clocks = <&clockgen 4 1>; - clock-names = "ipg"; - status = "disabled"; - }; - - lpuart2: serial@2970000 { - compatible = "fsl,ls1021a-lpuart"; - reg = <0x0 0x2970000 0x0 0x1000>; - interrupts = ; - clocks = <&clockgen 4 1>; - clock-names = "ipg"; - status = "disabled"; - }; - - lpuart3: serial@2980000 { - compatible = "fsl,ls1021a-lpuart"; - reg = <0x0 0x2980000 0x0 0x1000>; - interrupts = ; - clocks = <&clockgen 4 1>; - clock-names = "ipg"; - status = "disabled"; - }; - - lpuart4: serial@2990000 { - compatible = "fsl,ls1021a-lpuart"; - reg = <0x0 0x2990000 0x0 0x1000>; - interrupts = ; - clocks = <&clockgen 4 1>; - clock-names = "ipg"; - status = "disabled"; - }; - - lpuart5: serial@29a0000 { - compatible = "fsl,ls1021a-lpuart"; - reg = <0x0 0x29a0000 0x0 0x1000>; - interrupts = ; - clocks = <&clockgen 4 1>; - clock-names = "ipg"; - status = "disabled"; - }; - - wdog0: watchdog@2ad0000 { - compatible = "fsl,imx21-wdt"; - reg = <0x0 0x2ad0000 0x0 0x10000>; - interrupts = ; - clocks = <&clockgen 4 1>; - big-endian; - }; - - edma0: edma@2c00000 { - #dma-cells = <2>; - compatible = "fsl,vf610-edma"; - reg = <0x0 0x2c00000 0x0 0x10000>, - <0x0 0x2c10000 0x0 0x10000>, - <0x0 0x2c20000 0x0 0x10000>; - interrupts = , - ; - interrupt-names = "edma-tx", "edma-err"; - dma-channels = <32>; - big-endian; - clock-names = "dmamux0", "dmamux1"; - clocks = <&clockgen 4 1>, - <&clockgen 4 1>; - }; - - usb0: usb@2f00000 { - compatible = "snps,dwc3"; - reg = <0x0 0x2f00000 0x0 0x10000>; - interrupts = ; - dr_mode = "host"; - snps,quirk-frame-length-adjustment = <0x20>; - snps,dis_rxdet_inp3_quirk; - snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; - }; - - usb1: usb@3000000 { - compatible = "snps,dwc3"; - reg = <0x0 0x3000000 0x0 0x10000>; - interrupts = ; - dr_mode = "host"; - snps,quirk-frame-length-adjustment = <0x20>; - snps,dis_rxdet_inp3_quirk; - snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; - }; - - usb2: usb@3100000 { - compatible = "snps,dwc3"; - reg = <0x0 0x3100000 0x0 0x10000>; - interrupts = ; - dr_mode = "host"; - snps,quirk-frame-length-adjustment = <0x20>; - snps,dis_rxdet_inp3_quirk; - snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; - }; - - sata: sata@3200000 { - compatible = "fsl,ls1046a-ahci"; - reg = <0x0 0x3200000 0x0 0x10000>, - <0x0 0x20140520 0x0 0x4>; - reg-names = "ahci", "sata-ecc"; - interrupts = ; - clocks = <&clockgen 4 1>; - }; - - msi1: msi-controller@1580000 { - compatible = "fsl,ls1046a-msi"; - msi-controller; - reg = <0x0 0x1580000 0x0 0x10000>; - interrupts = , - , - , - ; - }; - - msi2: msi-controller@1590000 { - compatible = "fsl,ls1046a-msi"; - msi-controller; - reg = <0x0 0x1590000 0x0 0x10000>; - interrupts = , - , - , - ; - }; - - msi3: msi-controller@15a0000 { - compatible = "fsl,ls1046a-msi"; - msi-controller; - reg = <0x0 0x15a0000 0x0 0x10000>; - interrupts = , - , - , - ; - }; - - pcie@3400000 { - compatible = "fsl,ls1046a-pcie"; - reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ - 0x40 0x00000000 0x0 0x00002000>; /* configuration space */ - reg-names = "regs", "config"; - interrupts = , /* controller interrupt */ - ; /* PME interrupt */ - interrupt-names = "aer", "pme"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - dma-coherent; - num-viewport = <8>; - bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */ - 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ - msi-parent = <&msi1>, <&msi2>, <&msi3>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0000 0 0 1 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 2 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 3 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 4 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - pcie_ep@3400000 { - compatible = "fsl,ls1046a-pcie-ep","fsl,ls-pcie-ep"; - reg = <0x00 0x03400000 0x0 0x00100000 - 0x40 0x00000000 0x8 0x00000000>; - reg-names = "regs", "addr_space"; - num-ib-windows = <6>; - num-ob-windows = <8>; - status = "disabled"; - }; - - pcie@3500000 { - compatible = "fsl,ls1046a-pcie"; - reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ - 0x48 0x00000000 0x0 0x00002000>; /* configuration space */ - reg-names = "regs", "config"; - interrupts = , /* controller interrupt */ - ; /* PME interrupt */ - interrupt-names = "aer", "pme"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - dma-coherent; - num-viewport = <8>; - bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */ - 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ - msi-parent = <&msi2>, <&msi3>, <&msi1>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0000 0 0 1 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 2 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 3 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 4 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - pcie_ep@3500000 { - compatible = "fsl,ls1046a-pcie-ep","fsl,ls-pcie-ep"; - reg = <0x00 0x03500000 0x0 0x00100000 - 0x48 0x00000000 0x8 0x00000000>; - reg-names = "regs", "addr_space"; - num-ib-windows = <6>; - num-ob-windows = <8>; - status = "disabled"; - }; - - pcie@3600000 { - compatible = "fsl,ls1046a-pcie"; - reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ - 0x50 0x00000000 0x0 0x00002000>; /* configuration space */ - reg-names = "regs", "config"; - interrupts = , /* controller interrupt */ - ; /* PME interrupt */ - interrupt-names = "aer", "pme"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - dma-coherent; - num-viewport = <8>; - bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */ - 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ - msi-parent = <&msi3>, <&msi1>, <&msi2>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0000 0 0 1 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 2 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 3 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 4 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - pcie_ep@3600000 { - compatible = "fsl,ls1046a-pcie-ep", "fsl,ls-pcie-ep"; - reg = <0x00 0x03600000 0x0 0x00100000 - 0x50 0x00000000 0x8 0x00000000>; - reg-names = "regs", "addr_space"; - num-ib-windows = <6>; - num-ob-windows = <8>; - status = "disabled"; - }; - - qdma: dma-controller@8380000 { - compatible = "fsl,ls1046a-qdma", "fsl,ls1021a-qdma"; - reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */ - <0x0 0x8390000 0x0 0x10000>, /* Status regs */ - <0x0 0x83a0000 0x0 0x40000>; /* Block regs */ - interrupts = , - , - , - , - ; - interrupt-names = "qdma-error", "qdma-queue0", - "qdma-queue1", "qdma-queue2", "qdma-queue3"; - dma-channels = <8>; - block-number = <1>; - block-offset = <0x10000>; - fsl,dma-queues = <2>; - status-sizes = <64>; - queue-sizes = <64 64>; - big-endian; - }; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - bman_fbpr: bman-fbpr { - compatible = "shared-dma-pool"; - size = <0 0x1000000>; - alignment = <0 0x1000000>; - no-map; - }; - - qman_fqd: qman-fqd { - compatible = "shared-dma-pool"; - size = <0 0x800000>; - alignment = <0 0x800000>; - no-map; - }; - - qman_pfdr: qman-pfdr { - compatible = "shared-dma-pool"; - size = <0 0x2000000>; - alignment = <0 0x2000000>; - no-map; - }; - }; - - firmware { - optee { - compatible = "linaro,optee-tz"; - method = "smc"; - }; - }; -}; - -#include "qoriq-qman-portals.dtsi" -#include "qoriq-bman-portals.dtsi" diff --git a/sys/gnu/dts/arm64/freescale/fsl-ls1088a-qds.dts b/sys/gnu/dts/arm64/freescale/fsl-ls1088a-qds.dts deleted file mode 100644 index 41d8b15f25a..00000000000 --- a/sys/gnu/dts/arm64/freescale/fsl-ls1088a-qds.dts +++ /dev/null @@ -1,172 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for NXP LS1088A QDS Board. - * - * Copyright 2017 NXP - * - * Harninder Rai - * - */ - -/dts-v1/; - -#include "fsl-ls1088a.dtsi" - -/ { - model = "LS1088A QDS Board"; - compatible = "fsl,ls1088a-qds", "fsl,ls1088a"; -}; - -&dspi { - bus-num = <0>; - status = "okay"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - - flash@1 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - spi-cpol; - spi-cpha; - spi-max-frequency = <3500000>; - reg = <1>; - }; - - flash@2 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - spi-cpol; - spi-cpha; - spi-max-frequency = <3500000>; - reg = <2>; - }; -}; - -&i2c0 { - status = "okay"; - - i2c-switch@77 { - compatible = "nxp,pca9547"; - reg = <0x77>; - #address-cells = <1>; - #size-cells = <0>; - - i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x2>; - - ina220@40 { - compatible = "ti,ina220"; - reg = <0x40>; - shunt-resistor = <1000>; - }; - - ina220@41 { - compatible = "ti,ina220"; - reg = <0x41>; - shunt-resistor = <1000>; - }; - }; - - i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x3>; - - temp-sensor@4c { - compatible = "adi,adt7461a"; - reg = <0x4c>; - }; - - rtc@51 { - compatible = "nxp,pcf2129"; - reg = <0x51>; - /* IRQ10_B */ - interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>; - }; - - eeprom@56 { - compatible = "atmel,24c512"; - reg = <0x56>; - }; - - eeprom@57 { - compatible = "atmel,24c512"; - reg = <0x57>; - }; - }; - }; -}; - -&ifc { - ranges = <0 0 0x5 0x80000000 0x08000000 - 2 0 0x5 0x30000000 0x00010000 - 3 0 0x5 0x20000000 0x00010000>; - status = "okay"; - - nor@0,0 { - compatible = "cfi-flash"; - reg = <0x0 0x0 0x8000000>; - bank-width = <2>; - device-width = <1>; - }; - - nand@2,0 { - compatible = "fsl,ifc-nand"; - reg = <0x2 0x0 0x10000>; - }; - - fpga: board-control@3,0 { - compatible = "fsl,ls1088aqds-fpga", "fsl,fpga-qixis"; - reg = <0x3 0x0 0x0000100>; - }; -}; - -&duart0 { - status = "okay"; -}; - -&duart1 { - status = "okay"; -}; - -&esdhc { - status = "okay"; -}; - -&qspi { - status = "okay"; - - s25fs512s0: flash@0 { - compatible = "jedec,spi-nor"; - #address-cells = <1>; - #size-cells = <1>; - spi-max-frequency = <50000000>; - spi-rx-bus-width = <4>; - spi-tx-bus-width = <1>; - reg = <0>; - }; - - s25fs512s1: flash@1 { - compatible = "jedec,spi-nor"; - #address-cells = <1>; - #size-cells = <1>; - spi-max-frequency = <50000000>; - spi-rx-bus-width = <4>; - spi-tx-bus-width = <1>; - reg = <1>; - }; -}; - -&sata { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/freescale/fsl-ls1088a-rdb.dts b/sys/gnu/dts/arm64/freescale/fsl-ls1088a-rdb.dts deleted file mode 100644 index 4d77b345ceb..00000000000 --- a/sys/gnu/dts/arm64/freescale/fsl-ls1088a-rdb.dts +++ /dev/null @@ -1,124 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for NXP LS1088A RDB Board. - * - * Copyright 2017 NXP - * - * Harninder Rai - * - */ - -/dts-v1/; - -#include "fsl-ls1088a.dtsi" - -/ { - model = "LS1088A RDB Board"; - compatible = "fsl,ls1088a-rdb", "fsl,ls1088a"; -}; - -&i2c0 { - status = "okay"; - - i2c-switch@77 { - compatible = "nxp,pca9547"; - reg = <0x77>; - #address-cells = <1>; - #size-cells = <0>; - - i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x2>; - - ina220@40 { - compatible = "ti,ina220"; - reg = <0x40>; - shunt-resistor = <1000>; - }; - }; - - i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x3>; - - temp-sensor@4c { - compatible = "adi,adt7461a"; - reg = <0x4c>; - }; - - rtc@51 { - compatible = "nxp,pcf2129"; - reg = <0x51>; - /* IRQ10_B */ - interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - }; -}; - -&ifc { - ranges = <0 0 0x5 0x30000000 0x00010000 - 2 0 0x5 0x20000000 0x00010000>; - status = "okay"; - - nand@0,0 { - compatible = "fsl,ifc-nand"; - reg = <0x0 0x0 0x10000>; - }; - - fpga: board-control@2,0 { - compatible = "fsl,ls1088ardb-fpga", "fsl,fpga-qixis"; - reg = <0x2 0x0 0x0000100>; - }; -}; - -&duart0 { - status = "okay"; -}; - -&duart1 { - status = "okay"; -}; - -&esdhc { - status = "okay"; -}; - -&qspi { - status = "okay"; - - s25fs512s0: flash@0 { - compatible = "jedec,spi-nor"; - #address-cells = <1>; - #size-cells = <1>; - spi-max-frequency = <50000000>; - spi-rx-bus-width = <4>; - spi-tx-bus-width = <1>; - reg = <0>; - }; - - s25fs512s1: flash@1 { - compatible = "jedec,spi-nor"; - #address-cells = <1>; - #size-cells = <1>; - spi-max-frequency = <50000000>; - spi-rx-bus-width = <4>; - spi-tx-bus-width = <1>; - reg = <1>; - }; -}; - -&sata { - status = "okay"; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - dr_mode = "otg"; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/freescale/fsl-ls1088a.dtsi b/sys/gnu/dts/arm64/freescale/fsl-ls1088a.dtsi deleted file mode 100644 index 594566265e3..00000000000 --- a/sys/gnu/dts/arm64/freescale/fsl-ls1088a.dtsi +++ /dev/null @@ -1,788 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree Include file for NXP Layerscape-1088A family SoC. - * - * Copyright 2017 NXP - * - * Harninder Rai - * - */ -#include -#include - -/ { - compatible = "fsl,ls1088a"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - crypto = &crypto; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - /* We have 2 clusters having 4 Cortex-A53 cores each */ - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0>; - clocks = <&clockgen 1 0>; - cpu-idle-states = <&CPU_PH20>; - #cooling-cells = <2>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x1>; - clocks = <&clockgen 1 0>; - cpu-idle-states = <&CPU_PH20>; - #cooling-cells = <2>; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x2>; - clocks = <&clockgen 1 0>; - cpu-idle-states = <&CPU_PH20>; - #cooling-cells = <2>; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x3>; - clocks = <&clockgen 1 0>; - cpu-idle-states = <&CPU_PH20>; - #cooling-cells = <2>; - }; - - cpu4: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x100>; - clocks = <&clockgen 1 1>; - cpu-idle-states = <&CPU_PH20>; - #cooling-cells = <2>; - }; - - cpu5: cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x101>; - clocks = <&clockgen 1 1>; - cpu-idle-states = <&CPU_PH20>; - #cooling-cells = <2>; - }; - - cpu6: cpu@102 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x102>; - clocks = <&clockgen 1 1>; - cpu-idle-states = <&CPU_PH20>; - #cooling-cells = <2>; - }; - - cpu7: cpu@103 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x103>; - clocks = <&clockgen 1 1>; - cpu-idle-states = <&CPU_PH20>; - #cooling-cells = <2>; - }; - - CPU_PH20: cpu-ph20 { - compatible = "arm,idle-state"; - idle-state-name = "PH20"; - arm,psci-suspend-param = <0x0>; - entry-latency-us = <1000>; - exit-latency-us = <1000>; - min-residency-us = <3000>; - }; - }; - - gic: interrupt-controller@6000000 { - compatible = "arm,gic-v3"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */ - <0x0 0x06100000 0 0x100000>, /* GICR(RD_base+SGI_base)*/ - <0x0 0x0c0c0000 0 0x2000>, /* GICC */ - <0x0 0x0c0d0000 0 0x1000>, /* GICH */ - <0x0 0x0c0e0000 0 0x20000>; /* GICV */ - interrupts = <1 9 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - its: gic-its@6020000 { - compatible = "arm,gic-v3-its"; - msi-controller; - reg = <0x0 0x6020000 0 0x20000>; - }; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <1000>; - polling-delay = <5000>; - thermal-sensors = <&tmu 0>; - - trips { - cpu_alert: cpu-alert { - temperature = <85000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu_crit: cpu-crit { - temperature = <95000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu_alert>; - cooling-device = - <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */ - <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */ - <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */ - <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */ - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - sysclk: sysclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - clock-output-names = "sysclk"; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>; - - clockgen: clocking@1300000 { - compatible = "fsl,ls1088a-clockgen"; - reg = <0 0x1300000 0 0xa0000>; - #clock-cells = <2>; - clocks = <&sysclk>; - }; - - dcfg: dcfg@1e00000 { - compatible = "fsl,ls1088a-dcfg", "syscon"; - reg = <0x0 0x1e00000 0x0 0x10000>; - little-endian; - }; - - tmu: tmu@1f80000 { - compatible = "fsl,qoriq-tmu"; - reg = <0x0 0x1f80000 0x0 0x10000>; - interrupts = <0 23 0x4>; - fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>; - fsl,tmu-calibration = - /* Calibration data group 1 */ - <0x00000000 0x00000026 - 0x00000001 0x0000002d - 0x00000002 0x00000032 - 0x00000003 0x00000039 - 0x00000004 0x0000003f - 0x00000005 0x00000046 - 0x00000006 0x0000004d - 0x00000007 0x00000054 - 0x00000008 0x0000005a - 0x00000009 0x00000061 - 0x0000000a 0x0000006a - 0x0000000b 0x00000071 - /* Calibration data group 2 */ - 0x00010000 0x00000025 - 0x00010001 0x0000002c - 0x00010002 0x00000035 - 0x00010003 0x0000003d - 0x00010004 0x00000045 - 0x00010005 0x0000004e - 0x00010006 0x00000057 - 0x00010007 0x00000061 - 0x00010008 0x0000006b - 0x00010009 0x00000076 - /* Calibration data group 3 */ - 0x00020000 0x00000029 - 0x00020001 0x00000033 - 0x00020002 0x0000003d - 0x00020003 0x00000049 - 0x00020004 0x00000056 - 0x00020005 0x00000061 - 0x00020006 0x0000006d - /* Calibration data group 4 */ - 0x00030000 0x00000021 - 0x00030001 0x0000002a - 0x00030002 0x0000003c - 0x00030003 0x0000004e>; - little-endian; - #thermal-sensor-cells = <1>; - }; - - dspi: spi@2100000 { - compatible = "fsl,ls1088a-dspi", - "fsl,ls1021a-v1.0-dspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2100000 0x0 0x10000>; - interrupts = ; - clock-names = "dspi"; - clocks = <&clockgen 4 1>; - spi-num-chipselects = <6>; - status = "disabled"; - }; - - duart0: serial@21c0500 { - compatible = "fsl,ns16550", "ns16550a"; - reg = <0x0 0x21c0500 0x0 0x100>; - clocks = <&clockgen 4 3>; - interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - duart1: serial@21c0600 { - compatible = "fsl,ns16550", "ns16550a"; - reg = <0x0 0x21c0600 0x0 0x100>; - clocks = <&clockgen 4 3>; - interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - gpio0: gpio@2300000 { - compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; - reg = <0x0 0x2300000 0x0 0x10000>; - interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>; - little-endian; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio@2310000 { - compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; - reg = <0x0 0x2310000 0x0 0x10000>; - interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>; - little-endian; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@2320000 { - compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; - reg = <0x0 0x2320000 0x0 0x10000>; - interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>; - little-endian; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio@2330000 { - compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; - reg = <0x0 0x2330000 0x0 0x10000>; - interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>; - little-endian; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - ifc: ifc@2240000 { - compatible = "fsl,ifc", "simple-bus"; - reg = <0x0 0x2240000 0x0 0x20000>; - interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>; - little-endian; - #address-cells = <2>; - #size-cells = <1>; - status = "disabled"; - }; - - i2c0: i2c@2000000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2000000 0x0 0x10000>; - interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clockgen 4 7>; - status = "disabled"; - }; - - i2c1: i2c@2010000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2010000 0x0 0x10000>; - interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clockgen 4 7>; - status = "disabled"; - }; - - i2c2: i2c@2020000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2020000 0x0 0x10000>; - interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clockgen 4 7>; - status = "disabled"; - }; - - i2c3: i2c@2030000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2030000 0x0 0x10000>; - interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clockgen 4 7>; - status = "disabled"; - }; - - qspi: spi@20c0000 { - compatible = "fsl,ls2080a-qspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x20c0000 0x0 0x10000>, - <0x0 0x20000000 0x0 0x10000000>; - reg-names = "QuadSPI", "QuadSPI-memory"; - interrupts = ; - clock-names = "qspi_en", "qspi"; - clocks = <&clockgen 4 3>, <&clockgen 4 3>; - status = "disabled"; - }; - - esdhc: esdhc@2140000 { - compatible = "fsl,ls1088a-esdhc", "fsl,esdhc"; - reg = <0x0 0x2140000 0x0 0x10000>; - interrupts = <0 28 0x4>; /* Level high type */ - clock-frequency = <0>; - voltage-ranges = <1800 1800 3300 3300>; - sdhci,auto-cmd12; - little-endian; - bus-width = <4>; - status = "disabled"; - }; - - usb0: usb3@3100000 { - compatible = "snps,dwc3"; - reg = <0x0 0x3100000 0x0 0x10000>; - interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; - dr_mode = "host"; - snps,quirk-frame-length-adjustment = <0x20>; - snps,dis_rxdet_inp3_quirk; - snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; - status = "disabled"; - }; - - usb1: usb3@3110000 { - compatible = "snps,dwc3"; - reg = <0x0 0x3110000 0x0 0x10000>; - interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>; - dr_mode = "host"; - snps,quirk-frame-length-adjustment = <0x20>; - snps,dis_rxdet_inp3_quirk; - status = "disabled"; - }; - - sata: sata@3200000 { - compatible = "fsl,ls1088a-ahci"; - reg = <0x0 0x3200000 0x0 0x10000>, - <0x7 0x100520 0x0 0x4>; - reg-names = "ahci", "sata-ecc"; - interrupts = <0 133 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clockgen 4 3>; - dma-coherent; - status = "disabled"; - }; - - crypto: crypto@8000000 { - compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; - fsl,sec-era = <8>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x00 0x8000000 0x100000>; - reg = <0x00 0x8000000 0x0 0x100000>; - interrupts = ; - dma-coherent; - - sec_jr0: jr@10000 { - compatible = "fsl,sec-v5.0-job-ring", - "fsl,sec-v4.0-job-ring"; - reg = <0x10000 0x10000>; - interrupts = ; - }; - - sec_jr1: jr@20000 { - compatible = "fsl,sec-v5.0-job-ring", - "fsl,sec-v4.0-job-ring"; - reg = <0x20000 0x10000>; - interrupts = ; - }; - - sec_jr2: jr@30000 { - compatible = "fsl,sec-v5.0-job-ring", - "fsl,sec-v4.0-job-ring"; - reg = <0x30000 0x10000>; - interrupts = ; - }; - - sec_jr3: jr@40000 { - compatible = "fsl,sec-v5.0-job-ring", - "fsl,sec-v4.0-job-ring"; - reg = <0x40000 0x10000>; - interrupts = ; - }; - }; - - pcie@3400000 { - compatible = "fsl,ls1088a-pcie"; - reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ - 0x20 0x00000000 0x0 0x00002000>; /* configuration space */ - reg-names = "regs", "config"; - interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ - interrupt-names = "aer"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - dma-coherent; - num-viewport = <256>; - bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 /* downstream I/O */ - 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ - msi-parent = <&its>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - pcie@3500000 { - compatible = "fsl,ls1088a-pcie"; - reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ - 0x28 0x00000000 0x0 0x00002000>; /* configuration space */ - reg-names = "regs", "config"; - interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ - interrupt-names = "aer"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - dma-coherent; - num-viewport = <6>; - bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000 /* downstream I/O */ - 0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ - msi-parent = <&its>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0000 0 0 1 &gic 0 0 0 114 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 2 &gic 0 0 0 115 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 3 &gic 0 0 0 116 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 4 &gic 0 0 0 117 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - pcie@3600000 { - compatible = "fsl,ls1088a-pcie"; - reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ - 0x30 0x00000000 0x0 0x00002000>; /* configuration space */ - reg-names = "regs", "config"; - interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ - interrupt-names = "aer"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - dma-coherent; - num-viewport = <6>; - bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000 /* downstream I/O */ - 0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ - msi-parent = <&its>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0000 0 0 1 &gic 0 0 0 119 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 2 &gic 0 0 0 120 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 3 &gic 0 0 0 121 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 4 &gic 0 0 0 122 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - smmu: iommu@5000000 { - compatible = "arm,mmu-500"; - reg = <0 0x5000000 0 0x800000>; - #iommu-cells = <1>; - stream-match-mask = <0x7C00>; - #global-interrupts = <12>; - // global secure fault - interrupts = , - // combined secure - , - // global non-secure fault - , - // combined non-secure - , - // performance counter interrupts 0-7 - , - , - , - , - , - , - , - , - // per context interrupt, 64 interrupts - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - }; - - console@8340020 { - compatible = "fsl,dpaa2-console"; - reg = <0x00000000 0x08340020 0 0x2>; - }; - - ptp-timer@8b95000 { - compatible = "fsl,dpaa2-ptp"; - reg = <0x0 0x8b95000 0x0 0x100>; - clocks = <&clockgen 4 0>; - little-endian; - fsl,extts-fifo; - }; - - cluster1_core0_watchdog: wdt@c000000 { - compatible = "arm,sp805-wdt", "arm,primecell"; - reg = <0x0 0xc000000 0x0 0x1000>; - clocks = <&clockgen 4 3>, <&clockgen 4 3>; - clock-names = "apb_pclk", "wdog_clk"; - }; - - cluster1_core1_watchdog: wdt@c010000 { - compatible = "arm,sp805-wdt", "arm,primecell"; - reg = <0x0 0xc010000 0x0 0x1000>; - clocks = <&clockgen 4 3>, <&clockgen 4 3>; - clock-names = "apb_pclk", "wdog_clk"; - }; - - cluster1_core2_watchdog: wdt@c020000 { - compatible = "arm,sp805-wdt", "arm,primecell"; - reg = <0x0 0xc020000 0x0 0x1000>; - clocks = <&clockgen 4 3>, <&clockgen 4 3>; - clock-names = "apb_pclk", "wdog_clk"; - }; - - cluster1_core3_watchdog: wdt@c030000 { - compatible = "arm,sp805-wdt", "arm,primecell"; - reg = <0x0 0xc030000 0x0 0x1000>; - clocks = <&clockgen 4 3>, <&clockgen 4 3>; - clock-names = "apb_pclk", "wdog_clk"; - }; - - cluster2_core0_watchdog: wdt@c100000 { - compatible = "arm,sp805-wdt", "arm,primecell"; - reg = <0x0 0xc100000 0x0 0x1000>; - clocks = <&clockgen 4 3>, <&clockgen 4 3>; - clock-names = "apb_pclk", "wdog_clk"; - }; - - cluster2_core1_watchdog: wdt@c110000 { - compatible = "arm,sp805-wdt", "arm,primecell"; - reg = <0x0 0xc110000 0x0 0x1000>; - clocks = <&clockgen 4 3>, <&clockgen 4 3>; - clock-names = "apb_pclk", "wdog_clk"; - }; - - cluster2_core2_watchdog: wdt@c120000 { - compatible = "arm,sp805-wdt", "arm,primecell"; - reg = <0x0 0xc120000 0x0 0x1000>; - clocks = <&clockgen 4 3>, <&clockgen 4 3>; - clock-names = "apb_pclk", "wdog_clk"; - }; - - cluster2_core3_watchdog: wdt@c130000 { - compatible = "arm,sp805-wdt", "arm,primecell"; - reg = <0x0 0xc130000 0x0 0x1000>; - clocks = <&clockgen 4 3>, <&clockgen 4 3>; - clock-names = "apb_pclk", "wdog_clk"; - }; - - fsl_mc: fsl-mc@80c000000 { - compatible = "fsl,qoriq-mc"; - reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */ - <0x00000000 0x08340000 0 0x40000>; /* MC control reg */ - msi-parent = <&its>; - iommu-map = <0 &smmu 0 0>; /* This is fixed-up by u-boot */ - dma-coherent; - #address-cells = <3>; - #size-cells = <1>; - - /* - * Region type 0x0 - MC portals - * Region type 0x1 - QBMAN portals - */ - ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000 - 0x1 0x0 0x0 0x8 0x18000000 0x8000000>; - - dpmacs { - #address-cells = <1>; - #size-cells = <0>; - - dpmac1: dpmac@1 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <1>; - }; - - dpmac2: dpmac@2 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <2>; - }; - - dpmac3: dpmac@3 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <3>; - }; - - dpmac4: dpmac@4 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <4>; - }; - - dpmac5: dpmac@5 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <5>; - }; - - dpmac6: dpmac@6 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <6>; - }; - - dpmac7: dpmac@7 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <7>; - }; - - dpmac8: dpmac@8 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <8>; - }; - - dpmac9: dpmac@9 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <9>; - }; - - dpmac10: dpmac@a { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0xa>; - }; - }; - }; - }; - - firmware { - optee { - compatible = "linaro,optee-tz"; - method = "smc"; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/freescale/fsl-ls2080a-qds.dts b/sys/gnu/dts/arm64/freescale/fsl-ls2080a-qds.dts deleted file mode 100644 index f6c3ee78ace..00000000000 --- a/sys/gnu/dts/arm64/freescale/fsl-ls2080a-qds.dts +++ /dev/null @@ -1,25 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for Freescale LS2080a QDS Board. - * - * Copyright 2015-2016 Freescale Semiconductor, Inc. - * Copyright 2017 NXP - * - * Abhimanyu Saini - * Bhupesh Sharma - * - */ - -/dts-v1/; - -#include "fsl-ls2080a.dtsi" -#include "fsl-ls208xa-qds.dtsi" - -/ { - model = "Freescale Layerscape 2080a QDS Board"; - compatible = "fsl,ls2080a-qds", "fsl,ls2080a"; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; diff --git a/sys/gnu/dts/arm64/freescale/fsl-ls2080a-rdb.dts b/sys/gnu/dts/arm64/freescale/fsl-ls2080a-rdb.dts deleted file mode 100644 index 44894356059..00000000000 --- a/sys/gnu/dts/arm64/freescale/fsl-ls2080a-rdb.dts +++ /dev/null @@ -1,25 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for Freescale LS2080a RDB Board. - * - * Copyright 2016 Freescale Semiconductor, Inc. - * Copyright 2017 NXP - * - * Abhimanyu Saini - * Bhupesh Sharma - * - */ - -/dts-v1/; - -#include "fsl-ls2080a.dtsi" -#include "fsl-ls208xa-rdb.dtsi" - -/ { - model = "Freescale Layerscape 2080a RDB Board"; - compatible = "fsl,ls2080a-rdb", "fsl,ls2080a"; - - chosen { - stdout-path = "serial1:115200n8"; - }; -}; diff --git a/sys/gnu/dts/arm64/freescale/fsl-ls2080a-simu.dts b/sys/gnu/dts/arm64/freescale/fsl-ls2080a-simu.dts deleted file mode 100644 index 5517305039a..00000000000 --- a/sys/gnu/dts/arm64/freescale/fsl-ls2080a-simu.dts +++ /dev/null @@ -1,29 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for Freescale LS2080a software Simulator model - * - * Copyright 2014-2015 Freescale Semiconductor, Inc. - * - * Bhupesh Sharma - * - */ - -/dts-v1/; - -#include "fsl-ls2080a.dtsi" - -/ { - model = "Freescale Layerscape 2080a software Simulator model"; - compatible = "fsl,ls2080a-simu", "fsl,ls2080a"; - - ethernet@2210000 { - compatible = "smsc,lan91c111"; - reg = <0x0 0x2210000 0x0 0x100>; - interrupts = <0 58 0x1>; - }; -}; - -&ifc { - status = "okay"; -}; - diff --git a/sys/gnu/dts/arm64/freescale/fsl-ls2080a.dtsi b/sys/gnu/dts/arm64/freescale/fsl-ls2080a.dtsi deleted file mode 100644 index f9c1d30cf4a..00000000000 --- a/sys/gnu/dts/arm64/freescale/fsl-ls2080a.dtsi +++ /dev/null @@ -1,151 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree Include file for Freescale Layerscape-2080A family SoC. - * - * Copyright 2014-2016 Freescale Semiconductor, Inc. - * - * Abhimanyu Saini - * Bhupesh Sharma - * - */ - -#include "fsl-ls208xa.dtsi" - -&cpu { - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0>; - clocks = <&clockgen 1 0>; - cpu-idle-states = <&CPU_PW20>; - next-level-cache = <&cluster0_l2>; - #cooling-cells = <2>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x1>; - clocks = <&clockgen 1 0>; - cpu-idle-states = <&CPU_PW20>; - next-level-cache = <&cluster0_l2>; - #cooling-cells = <2>; - }; - - cpu2: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x100>; - clocks = <&clockgen 1 1>; - cpu-idle-states = <&CPU_PW20>; - next-level-cache = <&cluster1_l2>; - #cooling-cells = <2>; - }; - - cpu3: cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x101>; - clocks = <&clockgen 1 1>; - cpu-idle-states = <&CPU_PW20>; - next-level-cache = <&cluster1_l2>; - #cooling-cells = <2>; - }; - - cpu4: cpu@200 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x200>; - clocks = <&clockgen 1 2>; - cpu-idle-states = <&CPU_PW20>; - next-level-cache = <&cluster2_l2>; - #cooling-cells = <2>; - }; - - cpu5: cpu@201 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x201>; - clocks = <&clockgen 1 2>; - cpu-idle-states = <&CPU_PW20>; - next-level-cache = <&cluster2_l2>; - #cooling-cells = <2>; - }; - - cpu6: cpu@300 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x300>; - clocks = <&clockgen 1 3>; - next-level-cache = <&cluster3_l2>; - cpu-idle-states = <&CPU_PW20>; - #cooling-cells = <2>; - }; - - cpu7: cpu@301 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x301>; - clocks = <&clockgen 1 3>; - cpu-idle-states = <&CPU_PW20>; - next-level-cache = <&cluster3_l2>; - #cooling-cells = <2>; - }; - - cluster0_l2: l2-cache0 { - compatible = "cache"; - }; - - cluster1_l2: l2-cache1 { - compatible = "cache"; - }; - - cluster2_l2: l2-cache2 { - compatible = "cache"; - }; - - cluster3_l2: l2-cache3 { - compatible = "cache"; - }; - - CPU_PW20: cpu-pw20 { - compatible = "arm,idle-state"; - idle-state-name = "PW20"; - arm,psci-suspend-param = <0x00010000>; - entry-latency-us = <2000>; - exit-latency-us = <2000>; - min-residency-us = <6000>; - }; -}; - -&pcie1 { - reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ - 0x10 0x00000000 0x0 0x00002000>; /* configuration space */ - - ranges = <0x81000000 0x0 0x00000000 0x10 0x00010000 0x0 0x00010000 /* downstream I/O */ - 0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ -}; - -&pcie2 { - reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ - 0x12 0x00000000 0x0 0x00002000>; /* configuration space */ - - ranges = <0x81000000 0x0 0x00000000 0x12 0x00010000 0x0 0x00010000 /* downstream I/O */ - 0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ -}; - -&pcie3 { - reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ - 0x14 0x00000000 0x0 0x00002000>; /* configuration space */ - - ranges = <0x81000000 0x0 0x00000000 0x14 0x00010000 0x0 0x00010000 /* downstream I/O */ - 0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ -}; - -&pcie4 { - reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */ - 0x16 0x00000000 0x0 0x00002000>; /* configuration space */ - - ranges = <0x81000000 0x0 0x00000000 0x16 0x00010000 0x0 0x00010000 /* downstream I/O */ - 0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ -}; diff --git a/sys/gnu/dts/arm64/freescale/fsl-ls2088a-qds.dts b/sys/gnu/dts/arm64/freescale/fsl-ls2088a-qds.dts deleted file mode 100644 index 7c17b1bd452..00000000000 --- a/sys/gnu/dts/arm64/freescale/fsl-ls2088a-qds.dts +++ /dev/null @@ -1,24 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for Freescale LS2088A QDS Board. - * - * Copyright 2016 Freescale Semiconductor, Inc. - * Copyright 2017 NXP - * - * Abhimanyu Saini - * - */ - -/dts-v1/; - -#include "fsl-ls2088a.dtsi" -#include "fsl-ls208xa-qds.dtsi" - -/ { - model = "Freescale Layerscape 2088A QDS Board"; - compatible = "fsl,ls2088a-qds", "fsl,ls2088a"; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; diff --git a/sys/gnu/dts/arm64/freescale/fsl-ls2088a-rdb.dts b/sys/gnu/dts/arm64/freescale/fsl-ls2088a-rdb.dts deleted file mode 100644 index f6b4d75a258..00000000000 --- a/sys/gnu/dts/arm64/freescale/fsl-ls2088a-rdb.dts +++ /dev/null @@ -1,24 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for Freescale LS2088A RDB Board. - * - * Copyright 2016 Freescale Semiconductor, Inc. - * Copyright 2017 NXP - * - * Abhimanyu Saini - * - */ - -/dts-v1/; - -#include "fsl-ls2088a.dtsi" -#include "fsl-ls208xa-rdb.dtsi" - -/ { - model = "Freescale Layerscape 2088A RDB Board"; - compatible = "fsl,ls2088a-rdb", "fsl,ls2088a"; - - chosen { - stdout-path = "serial1:115200n8"; - }; -}; diff --git a/sys/gnu/dts/arm64/freescale/fsl-ls2088a.dtsi b/sys/gnu/dts/arm64/freescale/fsl-ls2088a.dtsi deleted file mode 100644 index a5f668d786b..00000000000 --- a/sys/gnu/dts/arm64/freescale/fsl-ls2088a.dtsi +++ /dev/null @@ -1,155 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree Include file for Freescale Layerscape-2088A family SoC. - * - * Copyright 2016 Freescale Semiconductor, Inc. - * Copyright 2017 NXP - * - * Abhimanyu Saini - * - */ - -#include "fsl-ls208xa.dtsi" - -&cpu { - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x0>; - clocks = <&clockgen 1 0>; - cpu-idle-states = <&CPU_PW20>; - next-level-cache = <&cluster0_l2>; - #cooling-cells = <2>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x1>; - clocks = <&clockgen 1 0>; - cpu-idle-states = <&CPU_PW20>; - next-level-cache = <&cluster0_l2>; - #cooling-cells = <2>; - }; - - cpu2: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x100>; - clocks = <&clockgen 1 1>; - cpu-idle-states = <&CPU_PW20>; - next-level-cache = <&cluster1_l2>; - #cooling-cells = <2>; - }; - - cpu3: cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x101>; - clocks = <&clockgen 1 1>; - cpu-idle-states = <&CPU_PW20>; - next-level-cache = <&cluster1_l2>; - #cooling-cells = <2>; - }; - - cpu4: cpu@200 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x200>; - clocks = <&clockgen 1 2>; - next-level-cache = <&cluster2_l2>; - cpu-idle-states = <&CPU_PW20>; - #cooling-cells = <2>; - }; - - cpu5: cpu@201 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x201>; - clocks = <&clockgen 1 2>; - cpu-idle-states = <&CPU_PW20>; - next-level-cache = <&cluster2_l2>; - #cooling-cells = <2>; - }; - - cpu6: cpu@300 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x300>; - clocks = <&clockgen 1 3>; - cpu-idle-states = <&CPU_PW20>; - next-level-cache = <&cluster3_l2>; - #cooling-cells = <2>; - }; - - cpu7: cpu@301 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x301>; - clocks = <&clockgen 1 3>; - cpu-idle-states = <&CPU_PW20>; - next-level-cache = <&cluster3_l2>; - #cooling-cells = <2>; - }; - - cluster0_l2: l2-cache0 { - compatible = "cache"; - }; - - cluster1_l2: l2-cache1 { - compatible = "cache"; - }; - - cluster2_l2: l2-cache2 { - compatible = "cache"; - }; - - cluster3_l2: l2-cache3 { - compatible = "cache"; - }; - - CPU_PW20: cpu-pw20 { - compatible = "arm,idle-state"; - idle-state-name = "PW20"; - arm,psci-suspend-param = <0x0>; - entry-latency-us = <2000>; - exit-latency-us = <2000>; - min-residency-us = <6000>; - }; -}; - -&pcie1 { - compatible = "fsl,ls2088a-pcie"; - reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ - 0x20 0x00000000 0x0 0x00002000>; /* configuration space */ - - ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 - 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; -}; - -&pcie2 { - compatible = "fsl,ls2088a-pcie"; - reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ - 0x28 0x00000000 0x0 0x00002000>; /* configuration space */ - - ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000 - 0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; -}; - -&pcie3 { - compatible = "fsl,ls2088a-pcie"; - reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ - 0x30 0x00000000 0x0 0x00002000>; /* configuration space */ - - ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000 - 0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; -}; - -&pcie4 { - compatible = "fsl,ls2088a-pcie"; - reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */ - 0x38 0x00000000 0x0 0x00002000>; /* configuration space */ - - ranges = <0x81000000 0x0 0x00000000 0x38 0x00010000 0x0 0x00010000 - 0x82000000 0x0 0x40000000 0x38 0x40000000 0x0 0x40000000>; -}; diff --git a/sys/gnu/dts/arm64/freescale/fsl-ls208xa-qds.dtsi b/sys/gnu/dts/arm64/freescale/fsl-ls208xa-qds.dtsi deleted file mode 100644 index 10d2fe09196..00000000000 --- a/sys/gnu/dts/arm64/freescale/fsl-ls208xa-qds.dtsi +++ /dev/null @@ -1,166 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for Freescale LS2080A QDS Board. - * - * Copyright 2016 Freescale Semiconductor, Inc. - * Copyright 2017 NXP - * - * Abhimanyu Saini - * - */ - -&esdhc { - mmc-hs200-1_8v; - status = "okay"; -}; - -&ifc { - status = "okay"; - #address-cells = <2>; - #size-cells = <1>; - ranges = <0x0 0x0 0x5 0x80000000 0x08000000 - 0x2 0x0 0x5 0x30000000 0x00010000 - 0x3 0x0 0x5 0x20000000 0x00010000>; - - nor@0,0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "cfi-flash"; - reg = <0x0 0x0 0x8000000>; - bank-width = <2>; - device-width = <1>; - }; - - nand@2,0 { - compatible = "fsl,ifc-nand"; - reg = <0x2 0x0 0x10000>; - }; - - cpld@3,0 { - reg = <0x3 0x0 0x10000>; - compatible = "fsl,ls2080aqds-fpga", "fsl,fpga-qixis"; - }; -}; - -&i2c0 { - status = "okay"; - pca9547@77 { - compatible = "nxp,pca9547"; - reg = <0x77>; - #address-cells = <1>; - #size-cells = <0>; - i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x00>; - rtc@68 { - compatible = "dallas,ds3232"; - reg = <0x68>; - }; - }; - - i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x02>; - - ina220@40 { - compatible = "ti,ina220"; - reg = <0x40>; - shunt-resistor = <500>; - }; - - ina220@41 { - compatible = "ti,ina220"; - reg = <0x41>; - shunt-resistor = <1000>; - }; - }; - - i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x3>; - - adt7481@4c { - compatible = "adi,adt7461"; - reg = <0x4c>; - }; - }; - }; -}; - -&i2c1 { - status = "disabled"; -}; - -&i2c2 { - status = "disabled"; -}; - -&i2c3 { - status = "disabled"; -}; - -&dspi { - status = "okay"; - dflash0: n25q128a@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,m25p80"; - spi-max-frequency = <3000000>; - reg = <0>; - }; - dflash1: sst25wf040b@1 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,m25p80"; - spi-max-frequency = <3000000>; - reg = <1>; - }; - dflash2: en25s64@2 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,m25p80"; - spi-max-frequency = <3000000>; - reg = <2>; - }; -}; - -&qspi { - status = "okay"; - flash0: s25fl256s1@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,m25p80"; - spi-max-frequency = <20000000>; - spi-rx-bus-width = <4>; - spi-tx-bus-width = <4>; - reg = <0>; - }; - flash2: s25fl256s1@2 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,m25p80"; - spi-max-frequency = <20000000>; - spi-rx-bus-width = <4>; - spi-tx-bus-width = <4>; - reg = <2>; - }; -}; - -&sata0 { - status = "okay"; -}; - -&sata1 { - status = "okay"; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/freescale/fsl-ls208xa-rdb.dtsi b/sys/gnu/dts/arm64/freescale/fsl-ls208xa-rdb.dtsi deleted file mode 100644 index d0d670227ae..00000000000 --- a/sys/gnu/dts/arm64/freescale/fsl-ls208xa-rdb.dtsi +++ /dev/null @@ -1,136 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for Freescale LS2080A RDB Board. - * - * Copyright 2016 Freescale Semiconductor, Inc. - * Copyright 2017 NXP - * - * Abhimanyu Saini - * - */ - -&esdhc { - status = "okay"; -}; - -&ifc { - status = "okay"; - #address-cells = <2>; - #size-cells = <1>; - ranges = <0x0 0x0 0x5 0x80000000 0x08000000 - 0x2 0x0 0x5 0x30000000 0x00010000 - 0x3 0x0 0x5 0x20000000 0x00010000>; - - nor@0,0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "cfi-flash"; - reg = <0x0 0x0 0x8000000>; - bank-width = <2>; - device-width = <1>; - }; - - nand@2,0 { - compatible = "fsl,ifc-nand"; - reg = <0x2 0x0 0x10000>; - }; - - cpld@3,0 { - reg = <0x3 0x0 0x10000>; - compatible = "fsl,ls2080aqds-fpga", "fsl,fpga-qixis"; - }; - -}; - -&i2c0 { - status = "okay"; - pca9547@75 { - compatible = "nxp,pca9547"; - reg = <0x75>; - #address-cells = <1>; - #size-cells = <0>; - i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x01>; - rtc@68 { - compatible = "dallas,ds3232"; - reg = <0x68>; - }; - }; - - i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x02>; - - ina220@40 { - compatible = "ti,ina220"; - reg = <0x40>; - shunt-resistor = <500>; - }; - }; - - i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x3>; - - adt7481@4c { - compatible = "adi,adt7461"; - reg = <0x4c>; - }; - }; - }; -}; - -&i2c1 { - status = "disabled"; -}; - -&i2c2 { - status = "disabled"; -}; - -&i2c3 { - status = "disabled"; -}; - -&dspi { - status = "okay"; - dflash0: n25q512a@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,m25p80"; - spi-max-frequency = <3000000>; - reg = <0>; - }; -}; - -&qspi { - status = "okay"; - - s25fs512s0: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - spi-max-frequency = <50000000>; - reg = <0>; - }; -}; - -&sata0 { - status = "okay"; -}; - -&sata1 { - status = "okay"; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/freescale/fsl-ls208xa.dtsi b/sys/gnu/dts/arm64/freescale/fsl-ls208xa.dtsi deleted file mode 100644 index f96d06da96b..00000000000 --- a/sys/gnu/dts/arm64/freescale/fsl-ls208xa.dtsi +++ /dev/null @@ -1,784 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree Include file for Freescale Layerscape-2080A family SoC. - * - * Copyright 2016 Freescale Semiconductor, Inc. - * Copyright 2017 NXP - * - * Abhimanyu Saini - * - */ - -#include -#include - -/ { - compatible = "fsl,ls2080a"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - crypto = &crypto; - serial0 = &serial0; - serial1 = &serial1; - serial2 = &serial2; - serial3 = &serial3; - }; - - cpu: cpus { - #address-cells = <1>; - #size-cells = <0>; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x00000000 0x80000000 0 0x80000000>; - /* DRAM space - 1, size : 2 GB DRAM */ - }; - - sysclk: sysclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - clock-output-names = "sysclk"; - }; - - gic: interrupt-controller@6000000 { - compatible = "arm,gic-v3"; - reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */ - <0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */ - <0x0 0x0c0c0000 0 0x2000>, /* GICC */ - <0x0 0x0c0d0000 0 0x1000>, /* GICH */ - <0x0 0x0c0e0000 0 0x20000>; /* GICV */ - #interrupt-cells = <3>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - interrupt-controller; - interrupts = <1 9 0x4>; - - its: gic-its@6020000 { - compatible = "arm,gic-v3-its"; - msi-controller; - reg = <0x0 0x6020000 0 0x20000>; - }; - }; - - rstcr: syscon@1e60000 { - compatible = "fsl,ls2080a-rstcr", "syscon"; - reg = <0x0 0x1e60000 0x0 0x4>; - }; - - reboot { - compatible ="syscon-reboot"; - regmap = <&rstcr>; - offset = <0x0>; - mask = <0x2>; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <1000>; - polling-delay = <5000>; - - thermal-sensors = <&tmu 4>; - - trips { - cpu_alert: cpu-alert { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu_crit: cpu-crit { - temperature = <85000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu_alert>; - cooling-device = - <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = <1 13 4>, /* Physical Secure PPI, active-low */ - <1 14 4>, /* Physical Non-Secure PPI, active-low */ - <1 11 4>, /* Virtual PPI, active-low */ - <1 10 4>; /* Hypervisor PPI, active-low */ - fsl,erratum-a008585; - }; - - pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = <1 7 0x8>; /* PMU PPI, Level low type */ - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>; - - clockgen: clocking@1300000 { - compatible = "fsl,ls2080a-clockgen"; - reg = <0 0x1300000 0 0xa0000>; - #clock-cells = <2>; - clocks = <&sysclk>; - }; - - dcfg: dcfg@1e00000 { - compatible = "fsl,ls2080a-dcfg", "syscon"; - reg = <0x0 0x1e00000 0x0 0x10000>; - little-endian; - }; - - tmu: tmu@1f80000 { - compatible = "fsl,qoriq-tmu"; - reg = <0x0 0x1f80000 0x0 0x10000>; - interrupts = <0 23 0x4>; - fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>; - fsl,tmu-calibration = <0x00000000 0x00000026 - 0x00000001 0x0000002d - 0x00000002 0x00000032 - 0x00000003 0x00000039 - 0x00000004 0x0000003f - 0x00000005 0x00000046 - 0x00000006 0x0000004d - 0x00000007 0x00000054 - 0x00000008 0x0000005a - 0x00000009 0x00000061 - 0x0000000a 0x0000006a - 0x0000000b 0x00000071 - - 0x00010000 0x00000025 - 0x00010001 0x0000002c - 0x00010002 0x00000035 - 0x00010003 0x0000003d - 0x00010004 0x00000045 - 0x00010005 0x0000004e - 0x00010006 0x00000057 - 0x00010007 0x00000061 - 0x00010008 0x0000006b - 0x00010009 0x00000076 - - 0x00020000 0x00000029 - 0x00020001 0x00000033 - 0x00020002 0x0000003d - 0x00020003 0x00000049 - 0x00020004 0x00000056 - 0x00020005 0x00000061 - 0x00020006 0x0000006d - - 0x00030000 0x00000021 - 0x00030001 0x0000002a - 0x00030002 0x0000003c - 0x00030003 0x0000004e>; - little-endian; - #thermal-sensor-cells = <1>; - }; - - serial0: serial@21c0500 { - compatible = "fsl,ns16550", "ns16550a"; - reg = <0x0 0x21c0500 0x0 0x100>; - clocks = <&clockgen 4 3>; - interrupts = <0 32 0x4>; /* Level high type */ - }; - - serial1: serial@21c0600 { - compatible = "fsl,ns16550", "ns16550a"; - reg = <0x0 0x21c0600 0x0 0x100>; - clocks = <&clockgen 4 3>; - interrupts = <0 32 0x4>; /* Level high type */ - }; - - serial2: serial@21d0500 { - compatible = "fsl,ns16550", "ns16550a"; - reg = <0x0 0x21d0500 0x0 0x100>; - clocks = <&clockgen 4 3>; - interrupts = <0 33 0x4>; /* Level high type */ - }; - - serial3: serial@21d0600 { - compatible = "fsl,ns16550", "ns16550a"; - reg = <0x0 0x21d0600 0x0 0x100>; - clocks = <&clockgen 4 3>; - interrupts = <0 33 0x4>; /* Level high type */ - }; - - cluster1_core0_watchdog: wdt@c000000 { - compatible = "arm,sp805-wdt", "arm,primecell"; - reg = <0x0 0xc000000 0x0 0x1000>; - clocks = <&clockgen 4 3>, <&clockgen 4 3>; - clock-names = "apb_pclk", "wdog_clk"; - }; - - cluster1_core1_watchdog: wdt@c010000 { - compatible = "arm,sp805-wdt", "arm,primecell"; - reg = <0x0 0xc010000 0x0 0x1000>; - clocks = <&clockgen 4 3>, <&clockgen 4 3>; - clock-names = "apb_pclk", "wdog_clk"; - }; - - cluster2_core0_watchdog: wdt@c100000 { - compatible = "arm,sp805-wdt", "arm,primecell"; - reg = <0x0 0xc100000 0x0 0x1000>; - clocks = <&clockgen 4 3>, <&clockgen 4 3>; - clock-names = "apb_pclk", "wdog_clk"; - }; - - cluster2_core1_watchdog: wdt@c110000 { - compatible = "arm,sp805-wdt", "arm,primecell"; - reg = <0x0 0xc110000 0x0 0x1000>; - clocks = <&clockgen 4 3>, <&clockgen 4 3>; - clock-names = "apb_pclk", "wdog_clk"; - }; - - cluster3_core0_watchdog: wdt@c200000 { - compatible = "arm,sp805-wdt", "arm,primecell"; - reg = <0x0 0xc200000 0x0 0x1000>; - clocks = <&clockgen 4 3>, <&clockgen 4 3>; - clock-names = "apb_pclk", "wdog_clk"; - }; - - cluster3_core1_watchdog: wdt@c210000 { - compatible = "arm,sp805-wdt", "arm,primecell"; - reg = <0x0 0xc210000 0x0 0x1000>; - clocks = <&clockgen 4 3>, <&clockgen 4 3>; - clock-names = "apb_pclk", "wdog_clk"; - }; - - cluster4_core0_watchdog: wdt@c300000 { - compatible = "arm,sp805-wdt", "arm,primecell"; - reg = <0x0 0xc300000 0x0 0x1000>; - clocks = <&clockgen 4 3>, <&clockgen 4 3>; - clock-names = "apb_pclk", "wdog_clk"; - }; - - cluster4_core1_watchdog: wdt@c310000 { - compatible = "arm,sp805-wdt", "arm,primecell"; - reg = <0x0 0xc310000 0x0 0x1000>; - clocks = <&clockgen 4 3>, <&clockgen 4 3>; - clock-names = "apb_pclk", "wdog_clk"; - }; - - crypto: crypto@8000000 { - compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; - fsl,sec-era = <8>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x00 0x8000000 0x100000>; - reg = <0x00 0x8000000 0x0 0x100000>; - interrupts = ; - dma-coherent; - - sec_jr0: jr@10000 { - compatible = "fsl,sec-v5.0-job-ring", - "fsl,sec-v4.0-job-ring"; - reg = <0x10000 0x10000>; - interrupts = ; - }; - - sec_jr1: jr@20000 { - compatible = "fsl,sec-v5.0-job-ring", - "fsl,sec-v4.0-job-ring"; - reg = <0x20000 0x10000>; - interrupts = ; - }; - - sec_jr2: jr@30000 { - compatible = "fsl,sec-v5.0-job-ring", - "fsl,sec-v4.0-job-ring"; - reg = <0x30000 0x10000>; - interrupts = ; - }; - - sec_jr3: jr@40000 { - compatible = "fsl,sec-v5.0-job-ring", - "fsl,sec-v4.0-job-ring"; - reg = <0x40000 0x10000>; - interrupts = ; - }; - }; - - console@8340020 { - compatible = "fsl,dpaa2-console"; - reg = <0x00000000 0x08340020 0 0x2>; - }; - - ptp-timer@8b95000 { - compatible = "fsl,dpaa2-ptp"; - reg = <0x0 0x8b95000 0x0 0x100>; - clocks = <&clockgen 4 1>; - little-endian; - fsl,extts-fifo; - }; - - fsl_mc: fsl-mc@80c000000 { - compatible = "fsl,qoriq-mc"; - reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */ - <0x00000000 0x08340000 0 0x40000>; /* MC control reg */ - msi-parent = <&its>; - iommu-map = <0 &smmu 0 0>; /* This is fixed-up by u-boot */ - dma-coherent; - #address-cells = <3>; - #size-cells = <1>; - - /* - * Region type 0x0 - MC portals - * Region type 0x1 - QBMAN portals - */ - ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000 - 0x1 0x0 0x0 0x8 0x18000000 0x8000000>; - - /* - * Define the maximum number of MACs present on the SoC. - */ - dpmacs { - #address-cells = <1>; - #size-cells = <0>; - - dpmac1: dpmac@1 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0x1>; - }; - - dpmac2: dpmac@2 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0x2>; - }; - - dpmac3: dpmac@3 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0x3>; - }; - - dpmac4: dpmac@4 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0x4>; - }; - - dpmac5: dpmac@5 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0x5>; - }; - - dpmac6: dpmac@6 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0x6>; - }; - - dpmac7: dpmac@7 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0x7>; - }; - - dpmac8: dpmac@8 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0x8>; - }; - - dpmac9: dpmac@9 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0x9>; - }; - - dpmac10: dpmac@a { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0xa>; - }; - - dpmac11: dpmac@b { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0xb>; - }; - - dpmac12: dpmac@c { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0xc>; - }; - - dpmac13: dpmac@d { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0xd>; - }; - - dpmac14: dpmac@e { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0xe>; - }; - - dpmac15: dpmac@f { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0xf>; - }; - - dpmac16: dpmac@10 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0x10>; - }; - }; - }; - - smmu: iommu@5000000 { - compatible = "arm,mmu-500"; - reg = <0 0x5000000 0 0x800000>; - #global-interrupts = <12>; - #iommu-cells = <1>; - stream-match-mask = <0x7C00>; - dma-coherent; - interrupts = <0 13 4>, /* global secure fault */ - <0 14 4>, /* combined secure interrupt */ - <0 15 4>, /* global non-secure fault */ - <0 16 4>, /* combined non-secure interrupt */ - /* performance counter interrupts 0-7 */ - <0 211 4>, <0 212 4>, - <0 213 4>, <0 214 4>, - <0 215 4>, <0 216 4>, - <0 217 4>, <0 218 4>, - /* per context interrupt, 64 interrupts */ - <0 146 4>, <0 147 4>, - <0 148 4>, <0 149 4>, - <0 150 4>, <0 151 4>, - <0 152 4>, <0 153 4>, - <0 154 4>, <0 155 4>, - <0 156 4>, <0 157 4>, - <0 158 4>, <0 159 4>, - <0 160 4>, <0 161 4>, - <0 162 4>, <0 163 4>, - <0 164 4>, <0 165 4>, - <0 166 4>, <0 167 4>, - <0 168 4>, <0 169 4>, - <0 170 4>, <0 171 4>, - <0 172 4>, <0 173 4>, - <0 174 4>, <0 175 4>, - <0 176 4>, <0 177 4>, - <0 178 4>, <0 179 4>, - <0 180 4>, <0 181 4>, - <0 182 4>, <0 183 4>, - <0 184 4>, <0 185 4>, - <0 186 4>, <0 187 4>, - <0 188 4>, <0 189 4>, - <0 190 4>, <0 191 4>, - <0 192 4>, <0 193 4>, - <0 194 4>, <0 195 4>, - <0 196 4>, <0 197 4>, - <0 198 4>, <0 199 4>, - <0 200 4>, <0 201 4>, - <0 202 4>, <0 203 4>, - <0 204 4>, <0 205 4>, - <0 206 4>, <0 207 4>, - <0 208 4>, <0 209 4>; - }; - - dspi: spi@2100000 { - status = "disabled"; - compatible = "fsl,ls2080a-dspi", "fsl,ls2085a-dspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2100000 0x0 0x10000>; - interrupts = <0 26 0x4>; /* Level high type */ - clocks = <&clockgen 4 3>; - clock-names = "dspi"; - spi-num-chipselects = <5>; - bus-num = <0>; - }; - - esdhc: esdhc@2140000 { - status = "disabled"; - compatible = "fsl,ls2080a-esdhc", "fsl,esdhc"; - reg = <0x0 0x2140000 0x0 0x10000>; - interrupts = <0 28 0x4>; /* Level high type */ - clocks = <&clockgen 4 1>; - voltage-ranges = <1800 1800 3300 3300>; - sdhci,auto-cmd12; - little-endian; - bus-width = <4>; - }; - - gpio0: gpio@2300000 { - compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; - reg = <0x0 0x2300000 0x0 0x10000>; - interrupts = <0 36 0x4>; /* Level high type */ - gpio-controller; - little-endian; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio@2310000 { - compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; - reg = <0x0 0x2310000 0x0 0x10000>; - interrupts = <0 36 0x4>; /* Level high type */ - gpio-controller; - little-endian; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@2320000 { - compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; - reg = <0x0 0x2320000 0x0 0x10000>; - interrupts = <0 37 0x4>; /* Level high type */ - gpio-controller; - little-endian; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio@2330000 { - compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; - reg = <0x0 0x2330000 0x0 0x10000>; - interrupts = <0 37 0x4>; /* Level high type */ - gpio-controller; - little-endian; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - i2c0: i2c@2000000 { - status = "disabled"; - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2000000 0x0 0x10000>; - interrupts = <0 34 0x4>; /* Level high type */ - clock-names = "i2c"; - clocks = <&clockgen 4 3>; - }; - - i2c1: i2c@2010000 { - status = "disabled"; - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2010000 0x0 0x10000>; - interrupts = <0 34 0x4>; /* Level high type */ - clock-names = "i2c"; - clocks = <&clockgen 4 3>; - }; - - i2c2: i2c@2020000 { - status = "disabled"; - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2020000 0x0 0x10000>; - interrupts = <0 35 0x4>; /* Level high type */ - clock-names = "i2c"; - clocks = <&clockgen 4 3>; - }; - - i2c3: i2c@2030000 { - status = "disabled"; - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2030000 0x0 0x10000>; - interrupts = <0 35 0x4>; /* Level high type */ - clock-names = "i2c"; - clocks = <&clockgen 4 3>; - }; - - ifc: ifc@2240000 { - compatible = "fsl,ifc", "simple-bus"; - reg = <0x0 0x2240000 0x0 0x20000>; - interrupts = <0 21 0x4>; /* Level high type */ - little-endian; - #address-cells = <2>; - #size-cells = <1>; - - ranges = <0 0 0x5 0x80000000 0x08000000 - 2 0 0x5 0x30000000 0x00010000 - 3 0 0x5 0x20000000 0x00010000>; - }; - - qspi: spi@20c0000 { - compatible = "fsl,ls2080a-qspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x20c0000 0x0 0x10000>, - <0x0 0x20000000 0x0 0x10000000>; - reg-names = "QuadSPI", "QuadSPI-memory"; - interrupts = ; - clocks = <&clockgen 4 3>, <&clockgen 4 3>; - clock-names = "qspi_en", "qspi"; - status = "disabled"; - }; - - pcie1: pcie@3400000 { - compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie"; - reg-names = "regs", "config"; - interrupts = <0 108 0x4>; /* Level high type */ - interrupt-names = "intr"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - dma-coherent; - num-viewport = <6>; - bus-range = <0x0 0xff>; - msi-parent = <&its>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>, - <0000 0 0 2 &gic 0 0 0 110 4>, - <0000 0 0 3 &gic 0 0 0 111 4>, - <0000 0 0 4 &gic 0 0 0 112 4>; - status = "disabled"; - }; - - pcie2: pcie@3500000 { - compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie"; - reg-names = "regs", "config"; - interrupts = <0 113 0x4>; /* Level high type */ - interrupt-names = "intr"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - dma-coherent; - num-viewport = <6>; - bus-range = <0x0 0xff>; - msi-parent = <&its>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>, - <0000 0 0 2 &gic 0 0 0 115 4>, - <0000 0 0 3 &gic 0 0 0 116 4>, - <0000 0 0 4 &gic 0 0 0 117 4>; - status = "disabled"; - }; - - pcie3: pcie@3600000 { - compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie"; - reg-names = "regs", "config"; - interrupts = <0 118 0x4>; /* Level high type */ - interrupt-names = "intr"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - dma-coherent; - num-viewport = <256>; - bus-range = <0x0 0xff>; - msi-parent = <&its>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>, - <0000 0 0 2 &gic 0 0 0 120 4>, - <0000 0 0 3 &gic 0 0 0 121 4>, - <0000 0 0 4 &gic 0 0 0 122 4>; - status = "disabled"; - }; - - pcie4: pcie@3700000 { - compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie"; - reg-names = "regs", "config"; - interrupts = <0 123 0x4>; /* Level high type */ - interrupt-names = "intr"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - dma-coherent; - num-viewport = <6>; - bus-range = <0x0 0xff>; - msi-parent = <&its>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0000 0 0 1 &gic 0 0 0 124 4>, - <0000 0 0 2 &gic 0 0 0 125 4>, - <0000 0 0 3 &gic 0 0 0 126 4>, - <0000 0 0 4 &gic 0 0 0 127 4>; - status = "disabled"; - }; - - sata0: sata@3200000 { - status = "disabled"; - compatible = "fsl,ls2080a-ahci"; - reg = <0x0 0x3200000 0x0 0x10000>; - interrupts = <0 133 0x4>; /* Level high type */ - clocks = <&clockgen 4 3>; - dma-coherent; - }; - - sata1: sata@3210000 { - status = "disabled"; - compatible = "fsl,ls2080a-ahci"; - reg = <0x0 0x3210000 0x0 0x10000>; - interrupts = <0 136 0x4>; /* Level high type */ - clocks = <&clockgen 4 3>; - dma-coherent; - }; - - usb0: usb3@3100000 { - status = "disabled"; - compatible = "snps,dwc3"; - reg = <0x0 0x3100000 0x0 0x10000>; - interrupts = <0 80 0x4>; /* Level high type */ - dr_mode = "host"; - snps,quirk-frame-length-adjustment = <0x20>; - snps,dis_rxdet_inp3_quirk; - snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; - }; - - usb1: usb3@3110000 { - status = "disabled"; - compatible = "snps,dwc3"; - reg = <0x0 0x3110000 0x0 0x10000>; - interrupts = <0 81 0x4>; /* Level high type */ - dr_mode = "host"; - snps,quirk-frame-length-adjustment = <0x20>; - snps,dis_rxdet_inp3_quirk; - snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; - }; - - ccn@4000000 { - compatible = "arm,ccn-504"; - reg = <0x0 0x04000000 0x0 0x01000000>; - interrupts = <0 12 4>; - }; - }; - - ddr1: memory-controller@1080000 { - compatible = "fsl,qoriq-memory-controller"; - reg = <0x0 0x1080000 0x0 0x1000>; - interrupts = <0 17 0x4>; - little-endian; - }; - - ddr2: memory-controller@1090000 { - compatible = "fsl,qoriq-memory-controller"; - reg = <0x0 0x1090000 0x0 0x1000>; - interrupts = <0 18 0x4>; - little-endian; - }; - - firmware { - optee { - compatible = "linaro,optee-tz"; - method = "smc"; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/freescale/fsl-lx2160a-cex7.dtsi b/sys/gnu/dts/arm64/freescale/fsl-lx2160a-cex7.dtsi deleted file mode 100644 index 071e21678f7..00000000000 --- a/sys/gnu/dts/arm64/freescale/fsl-lx2160a-cex7.dtsi +++ /dev/null @@ -1,127 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -// -// Device Tree file for LX2160A-CEx7 -// -// Copyright 2019 SolidRun Ltd. - -/dts-v1/; - -#include "fsl-lx2160a.dtsi" - -/ { - model = "SolidRun LX2160A COM Express Type 7 module"; - compatible = "solidrun,lx2160a-cex7", "fsl,lx2160a"; - - aliases { - crypto = &crypto; - }; - - sb_3v3: regulator-sb3v3 { - compatible = "regulator-fixed"; - regulator-name = "RT7290"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; -}; - -&crypto { - status = "okay"; -}; - -&dpmac17 { - phy-handle = <&rgmii_phy1>; - phy-connection-type = "rgmii-id"; -}; - -&emdio1 { - status = "okay"; - - rgmii_phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&esdhc1 { - mmc-hs200-1_8v; - mmc-hs400-1_8v; - bus-width = <8>; - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - i2c-switch@77 { - compatible = "nxp,pca9547"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x77>; - - i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - fan-temperature-ctrlr@18 { - compatible = "ti,amc6821"; - reg = <0x18>; - cooling-min-state = <0>; - cooling-max-state = <9>; - #cooling-cells = <2>; - }; - }; - - i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - - temperature-sensor@48 { - compatible = "nxp,sa56004"; - reg = <0x48>; - vcc-supply = <&sb_3v3>; - }; - }; - }; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c4 { - status = "okay"; - - rtc@51 { - compatible = "nxp,pcf2129"; - reg = <0x51>; - // IRQ10_B - interrupts = ; - }; -}; - -&fspi { - status = "okay"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "micron,m25p80"; - m25p,fast-read; - spi-max-frequency = <50000000>; - reg = <0>; - /* The following setting enables 1-1-8 (CMD-ADDR-DATA) mode */ - spi-rx-bus-width = <8>; - spi-tx-bus-width = <1>; - }; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/freescale/fsl-lx2160a-clearfog-cx.dts b/sys/gnu/dts/arm64/freescale/fsl-lx2160a-clearfog-cx.dts deleted file mode 100644 index 86a9b771428..00000000000 --- a/sys/gnu/dts/arm64/freescale/fsl-lx2160a-clearfog-cx.dts +++ /dev/null @@ -1,15 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -// -// Device Tree file for LX2160A Clearfog CX board -// -// Copyright 2019 SolidRun Ltd. - -/dts-v1/; - -#include "fsl-lx2160a-clearfog-itx.dtsi" - -/ { - model = "SolidRun LX2160A Clearfog CX"; - compatible = "solidrun,clearfog-cx", - "solidrun,lx2160a-cex7", "fsl,lx2160a"; -}; diff --git a/sys/gnu/dts/arm64/freescale/fsl-lx2160a-clearfog-itx.dtsi b/sys/gnu/dts/arm64/freescale/fsl-lx2160a-clearfog-itx.dtsi deleted file mode 100644 index f3741a32e86..00000000000 --- a/sys/gnu/dts/arm64/freescale/fsl-lx2160a-clearfog-itx.dtsi +++ /dev/null @@ -1,57 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -// -// Device Tree file for LX2160A Clearfog ITX board; this contains the -// common parts shared between the Clearfog CX and Honeycomb builds. -// -// Copyright 2019 SolidRun Ltd. - -/dts-v1/; - -#include "fsl-lx2160a-cex7.dtsi" - -/ { - aliases { - serial0 = &uart0; - serial1 = &uart1; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&emdio2 { - status = "okay"; -}; - -&esdhc0 { - sd-uhs-sdr104; - sd-uhs-sdr50; - sd-uhs-sdr25; - sd-uhs-sdr12; - status = "okay"; -}; - -&sata0 { - status = "okay"; -}; - -&sata1 { - status = "okay"; -}; - -&sata2 { - status = "okay"; -}; - -&sata3 { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/freescale/fsl-lx2160a-honeycomb.dts b/sys/gnu/dts/arm64/freescale/fsl-lx2160a-honeycomb.dts deleted file mode 100644 index fe19f3009ea..00000000000 --- a/sys/gnu/dts/arm64/freescale/fsl-lx2160a-honeycomb.dts +++ /dev/null @@ -1,15 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -// -// Device Tree file for LX2160A Honeycomb board -// -// Copyright 2019 SolidRun Ltd. - -/dts-v1/; - -#include "fsl-lx2160a-clearfog-itx.dtsi" - -/ { - model = "SolidRun LX2160A Honeycomb"; - compatible = "solidrun,honeycomb", - "solidrun,lx2160a-cex7", "fsl,lx2160a"; -}; diff --git a/sys/gnu/dts/arm64/freescale/fsl-lx2160a-qds.dts b/sys/gnu/dts/arm64/freescale/fsl-lx2160a-qds.dts deleted file mode 100644 index 1a5acf62f23..00000000000 --- a/sys/gnu/dts/arm64/freescale/fsl-lx2160a-qds.dts +++ /dev/null @@ -1,128 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -// -// Device Tree file for LX2160AQDS -// -// Copyright 2018 NXP - -/dts-v1/; - -#include "fsl-lx2160a.dtsi" - -/ { - model = "NXP Layerscape LX2160AQDS"; - compatible = "fsl,lx2160a-qds", "fsl,lx2160a"; - - aliases { - crypto = &crypto; - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - sb_3v3: regulator-sb3v3 { - compatible = "regulator-fixed"; - regulator-name = "MC34717-3.3VSB"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; -}; - -&crypto { - status = "okay"; -}; - -&esdhc0 { - status = "okay"; -}; - -&esdhc1 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - i2c-mux@77 { - compatible = "nxp,pca9547"; - reg = <0x77>; - #address-cells = <1>; - #size-cells = <0>; - - i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x2>; - - power-monitor@40 { - compatible = "ti,ina220"; - reg = <0x40>; - shunt-resistor = <500>; - }; - - power-monitor@41 { - compatible = "ti,ina220"; - reg = <0x41>; - shunt-resistor = <1000>; - }; - }; - - i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x3>; - - temperature-sensor@4c { - compatible = "nxp,sa56004"; - reg = <0x4c>; - vcc-supply = <&sb_3v3>; - }; - - temperature-sensor@4d { - compatible = "nxp,sa56004"; - reg = <0x4d>; - vcc-supply = <&sb_3v3>; - }; - - rtc@51 { - compatible = "nxp,pcf2129"; - reg = <0x51>; - }; - }; - }; -}; - -&sata0 { - status = "okay"; -}; - -&sata1 { - status = "okay"; -}; - -&sata2 { - status = "okay"; -}; - -&sata3 { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/freescale/fsl-lx2160a-rdb.dts b/sys/gnu/dts/arm64/freescale/fsl-lx2160a-rdb.dts deleted file mode 100644 index 51615de102f..00000000000 --- a/sys/gnu/dts/arm64/freescale/fsl-lx2160a-rdb.dts +++ /dev/null @@ -1,189 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -// -// Device Tree file for LX2160ARDB -// -// Copyright 2018 NXP - -/dts-v1/; - -#include "fsl-lx2160a.dtsi" - -/ { - model = "NXP Layerscape LX2160ARDB"; - compatible = "fsl,lx2160a-rdb", "fsl,lx2160a"; - - aliases { - crypto = &crypto; - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - sb_3v3: regulator-sb3v3 { - compatible = "regulator-fixed"; - regulator-name = "MC34717-3.3VSB"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; -}; - -&crypto { - status = "okay"; -}; - -&dpmac17 { - phy-handle = <&rgmii_phy1>; - phy-connection-type = "rgmii-id"; -}; - -&dpmac18 { - phy-handle = <&rgmii_phy2>; - phy-connection-type = "rgmii-id"; -}; - -&emdio1 { - status = "okay"; - - rgmii_phy1: ethernet-phy@1 { - /* AR8035 PHY */ - compatible = "ethernet-phy-id004d.d072"; - reg = <0x1>; - eee-broken-1000t; - }; - - rgmii_phy2: ethernet-phy@2 { - /* AR8035 PHY */ - compatible = "ethernet-phy-id004d.d072"; - reg = <0x2>; - eee-broken-1000t; - }; -}; - -&esdhc0 { - sd-uhs-sdr104; - sd-uhs-sdr50; - sd-uhs-sdr25; - sd-uhs-sdr12; - status = "okay"; -}; - -&esdhc1 { - mmc-hs200-1_8v; - mmc-hs400-1_8v; - bus-width = <8>; - status = "okay"; -}; - -&fspi { - status = "okay"; - - mt35xu512aba0: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "spansion,m25p80"; - m25p,fast-read; - spi-max-frequency = <50000000>; - reg = <0>; - spi-rx-bus-width = <8>; - spi-tx-bus-width = <8>; - }; - - mt35xu512aba1: flash@1 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "spansion,m25p80"; - m25p,fast-read; - spi-max-frequency = <50000000>; - reg = <1>; - spi-rx-bus-width = <8>; - spi-tx-bus-width = <8>; - }; -}; - -&i2c0 { - status = "okay"; - - i2c-mux@77 { - compatible = "nxp,pca9547"; - reg = <0x77>; - #address-cells = <1>; - #size-cells = <0>; - - i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x2>; - - power-monitor@40 { - compatible = "ti,ina220"; - reg = <0x40>; - shunt-resistor = <1000>; - }; - }; - - i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x3>; - - temperature-sensor@4c { - compatible = "nxp,sa56004"; - reg = <0x4c>; - vcc-supply = <&sb_3v3>; - }; - - temperature-sensor@4d { - compatible = "nxp,sa56004"; - reg = <0x4d>; - vcc-supply = <&sb_3v3>; - }; - }; - }; -}; - -&i2c4 { - status = "okay"; - - rtc@51 { - compatible = "nxp,pcf2129"; - reg = <0x51>; - // IRQ10_B - interrupts = <0 150 0x4>; - }; -}; - -&sata0 { - status = "okay"; -}; - -&sata1 { - status = "okay"; -}; - -&sata2 { - status = "okay"; -}; - -&sata3 { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/freescale/fsl-lx2160a.dtsi b/sys/gnu/dts/arm64/freescale/fsl-lx2160a.dtsi deleted file mode 100644 index e5ee5591e52..00000000000 --- a/sys/gnu/dts/arm64/freescale/fsl-lx2160a.dtsi +++ /dev/null @@ -1,1080 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -// -// Device Tree Include file for Layerscape-LX2160A family SoC. -// -// Copyright 2018 NXP - -#include -#include -#include - -/memreserve/ 0x80000000 0x00010000; - -/ { - compatible = "fsl,lx2160a"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - // 8 clusters having 2 Cortex-A72 cores each - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - enable-method = "psci"; - reg = <0x0>; - clocks = <&clockgen 1 0>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - i-cache-size = <0xC000>; - i-cache-line-size = <64>; - i-cache-sets = <192>; - next-level-cache = <&cluster0_l2>; - cpu-idle-states = <&cpu_pw15>; - #cooling-cells = <2>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - enable-method = "psci"; - reg = <0x1>; - clocks = <&clockgen 1 0>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - i-cache-size = <0xC000>; - i-cache-line-size = <64>; - i-cache-sets = <192>; - next-level-cache = <&cluster0_l2>; - cpu-idle-states = <&cpu_pw15>; - #cooling-cells = <2>; - }; - - cpu100: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - enable-method = "psci"; - reg = <0x100>; - clocks = <&clockgen 1 1>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - i-cache-size = <0xC000>; - i-cache-line-size = <64>; - i-cache-sets = <192>; - next-level-cache = <&cluster1_l2>; - cpu-idle-states = <&cpu_pw15>; - #cooling-cells = <2>; - }; - - cpu101: cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - enable-method = "psci"; - reg = <0x101>; - clocks = <&clockgen 1 1>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - i-cache-size = <0xC000>; - i-cache-line-size = <64>; - i-cache-sets = <192>; - next-level-cache = <&cluster1_l2>; - cpu-idle-states = <&cpu_pw15>; - #cooling-cells = <2>; - }; - - cpu200: cpu@200 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - enable-method = "psci"; - reg = <0x200>; - clocks = <&clockgen 1 2>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - i-cache-size = <0xC000>; - i-cache-line-size = <64>; - i-cache-sets = <192>; - next-level-cache = <&cluster2_l2>; - cpu-idle-states = <&cpu_pw15>; - #cooling-cells = <2>; - }; - - cpu201: cpu@201 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - enable-method = "psci"; - reg = <0x201>; - clocks = <&clockgen 1 2>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - i-cache-size = <0xC000>; - i-cache-line-size = <64>; - i-cache-sets = <192>; - next-level-cache = <&cluster2_l2>; - cpu-idle-states = <&cpu_pw15>; - #cooling-cells = <2>; - }; - - cpu300: cpu@300 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - enable-method = "psci"; - reg = <0x300>; - clocks = <&clockgen 1 3>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - i-cache-size = <0xC000>; - i-cache-line-size = <64>; - i-cache-sets = <192>; - next-level-cache = <&cluster3_l2>; - cpu-idle-states = <&cpu_pw15>; - #cooling-cells = <2>; - }; - - cpu301: cpu@301 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - enable-method = "psci"; - reg = <0x301>; - clocks = <&clockgen 1 3>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - i-cache-size = <0xC000>; - i-cache-line-size = <64>; - i-cache-sets = <192>; - next-level-cache = <&cluster3_l2>; - cpu-idle-states = <&cpu_pw15>; - #cooling-cells = <2>; - }; - - cpu400: cpu@400 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - enable-method = "psci"; - reg = <0x400>; - clocks = <&clockgen 1 4>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - i-cache-size = <0xC000>; - i-cache-line-size = <64>; - i-cache-sets = <192>; - next-level-cache = <&cluster4_l2>; - cpu-idle-states = <&cpu_pw15>; - #cooling-cells = <2>; - }; - - cpu401: cpu@401 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - enable-method = "psci"; - reg = <0x401>; - clocks = <&clockgen 1 4>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - i-cache-size = <0xC000>; - i-cache-line-size = <64>; - i-cache-sets = <192>; - next-level-cache = <&cluster4_l2>; - cpu-idle-states = <&cpu_pw15>; - #cooling-cells = <2>; - }; - - cpu500: cpu@500 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - enable-method = "psci"; - reg = <0x500>; - clocks = <&clockgen 1 5>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - i-cache-size = <0xC000>; - i-cache-line-size = <64>; - i-cache-sets = <192>; - next-level-cache = <&cluster5_l2>; - cpu-idle-states = <&cpu_pw15>; - #cooling-cells = <2>; - }; - - cpu501: cpu@501 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - enable-method = "psci"; - reg = <0x501>; - clocks = <&clockgen 1 5>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - i-cache-size = <0xC000>; - i-cache-line-size = <64>; - i-cache-sets = <192>; - next-level-cache = <&cluster5_l2>; - cpu-idle-states = <&cpu_pw15>; - #cooling-cells = <2>; - }; - - cpu600: cpu@600 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - enable-method = "psci"; - reg = <0x600>; - clocks = <&clockgen 1 6>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - i-cache-size = <0xC000>; - i-cache-line-size = <64>; - i-cache-sets = <192>; - next-level-cache = <&cluster6_l2>; - cpu-idle-states = <&cpu_pw15>; - #cooling-cells = <2>; - }; - - cpu601: cpu@601 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - enable-method = "psci"; - reg = <0x601>; - clocks = <&clockgen 1 6>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - i-cache-size = <0xC000>; - i-cache-line-size = <64>; - i-cache-sets = <192>; - next-level-cache = <&cluster6_l2>; - cpu-idle-states = <&cpu_pw15>; - #cooling-cells = <2>; - }; - - cpu700: cpu@700 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - enable-method = "psci"; - reg = <0x700>; - clocks = <&clockgen 1 7>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - i-cache-size = <0xC000>; - i-cache-line-size = <64>; - i-cache-sets = <192>; - next-level-cache = <&cluster7_l2>; - cpu-idle-states = <&cpu_pw15>; - #cooling-cells = <2>; - }; - - cpu701: cpu@701 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - enable-method = "psci"; - reg = <0x701>; - clocks = <&clockgen 1 7>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - i-cache-size = <0xC000>; - i-cache-line-size = <64>; - i-cache-sets = <192>; - next-level-cache = <&cluster7_l2>; - cpu-idle-states = <&cpu_pw15>; - #cooling-cells = <2>; - }; - - cluster0_l2: l2-cache0 { - compatible = "cache"; - cache-size = <0x100000>; - cache-line-size = <64>; - cache-sets = <1024>; - cache-level = <2>; - }; - - cluster1_l2: l2-cache1 { - compatible = "cache"; - cache-size = <0x100000>; - cache-line-size = <64>; - cache-sets = <1024>; - cache-level = <2>; - }; - - cluster2_l2: l2-cache2 { - compatible = "cache"; - cache-size = <0x100000>; - cache-line-size = <64>; - cache-sets = <1024>; - cache-level = <2>; - }; - - cluster3_l2: l2-cache3 { - compatible = "cache"; - cache-size = <0x100000>; - cache-line-size = <64>; - cache-sets = <1024>; - cache-level = <2>; - }; - - cluster4_l2: l2-cache4 { - compatible = "cache"; - cache-size = <0x100000>; - cache-line-size = <64>; - cache-sets = <1024>; - cache-level = <2>; - }; - - cluster5_l2: l2-cache5 { - compatible = "cache"; - cache-size = <0x100000>; - cache-line-size = <64>; - cache-sets = <1024>; - cache-level = <2>; - }; - - cluster6_l2: l2-cache6 { - compatible = "cache"; - cache-size = <0x100000>; - cache-line-size = <64>; - cache-sets = <1024>; - cache-level = <2>; - }; - - cluster7_l2: l2-cache7 { - compatible = "cache"; - cache-size = <0x100000>; - cache-line-size = <64>; - cache-sets = <1024>; - cache-level = <2>; - }; - - cpu_pw15: cpu-pw15 { - compatible = "arm,idle-state"; - idle-state-name = "PW15"; - arm,psci-suspend-param = <0x0>; - entry-latency-us = <2000>; - exit-latency-us = <2000>; - min-residency-us = <6000>; - }; - }; - - gic: interrupt-controller@6000000 { - compatible = "arm,gic-v3"; - reg = <0x0 0x06000000 0 0x10000>, // GIC Dist - <0x0 0x06200000 0 0x200000>, // GICR (RD_base + - // SGI_base) - <0x0 0x0c0c0000 0 0x2000>, // GICC - <0x0 0x0c0d0000 0 0x1000>, // GICH - <0x0 0x0c0e0000 0 0x20000>; // GICV - #interrupt-cells = <3>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - interrupt-controller; - interrupts = ; - - its: gic-its@6020000 { - compatible = "arm,gic-v3-its"; - msi-controller; - reg = <0x0 0x6020000 0 0x20000>; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - pmu { - compatible = "arm,cortex-a72-pmu"; - interrupts = ; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - memory@80000000 { - // DRAM space - 1, size : 2 GB DRAM - device_type = "memory"; - reg = <0x00000000 0x80000000 0 0x80000000>; - }; - - ddr1: memory-controller@1080000 { - compatible = "fsl,qoriq-memory-controller"; - reg = <0x0 0x1080000 0x0 0x1000>; - interrupts = ; - little-endian; - }; - - ddr2: memory-controller@1090000 { - compatible = "fsl,qoriq-memory-controller"; - reg = <0x0 0x1090000 0x0 0x1000>; - interrupts = ; - little-endian; - }; - - // One clock unit-sysclk node which bootloader require during DT fix-up - sysclk: sysclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; // fixed up by bootloader - clock-output-names = "sysclk"; - }; - - thermal-zones { - core_thermal1: core-thermal1 { - polling-delay-passive = <1000>; - polling-delay = <5000>; - thermal-sensors = <&tmu 0>; - - trips { - core_cluster_alert: core-cluster-alert { - temperature = <85000>; - hysteresis = <2000>; - type = "passive"; - }; - - core_cluster_crit: core-cluster-crit { - temperature = <95000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&core_cluster_alert>; - cooling-device = - <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu200 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu201 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu300 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu301 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu400 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu401 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu500 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu501 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu600 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu601 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu700 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu701 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>; - - crypto: crypto@8000000 { - compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; - fsl,sec-era = <10>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x00 0x8000000 0x100000>; - reg = <0x00 0x8000000 0x0 0x100000>; - interrupts = ; - dma-coherent; - status = "disabled"; - - sec_jr0: jr@10000 { - compatible = "fsl,sec-v5.0-job-ring", - "fsl,sec-v4.0-job-ring"; - reg = <0x10000 0x10000>; - interrupts = ; - }; - - sec_jr1: jr@20000 { - compatible = "fsl,sec-v5.0-job-ring", - "fsl,sec-v4.0-job-ring"; - reg = <0x20000 0x10000>; - interrupts = ; - }; - - sec_jr2: jr@30000 { - compatible = "fsl,sec-v5.0-job-ring", - "fsl,sec-v4.0-job-ring"; - reg = <0x30000 0x10000>; - interrupts = ; - }; - - sec_jr3: jr@40000 { - compatible = "fsl,sec-v5.0-job-ring", - "fsl,sec-v4.0-job-ring"; - reg = <0x40000 0x10000>; - interrupts = ; - }; - }; - - clockgen: clock-controller@1300000 { - compatible = "fsl,lx2160a-clockgen"; - reg = <0 0x1300000 0 0xa0000>; - #clock-cells = <2>; - clocks = <&sysclk>; - }; - - dcfg: syscon@1e00000 { - compatible = "fsl,lx2160a-dcfg", "syscon"; - reg = <0x0 0x1e00000 0x0 0x10000>; - little-endian; - }; - - tmu: tmu@1f80000 { - compatible = "fsl,qoriq-tmu"; - reg = <0x0 0x1f80000 0x0 0x10000>; - interrupts = ; - fsl,tmu-range = <0x800000e6 0x8001017d>; - fsl,tmu-calibration = - /* Calibration data group 1 */ - <0x00000000 0x00000035 - /* Calibration data group 2 */ - 0x00010001 0x00000154>; - little-endian; - #thermal-sensor-cells = <1>; - }; - - i2c0: i2c@2000000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2000000 0x0 0x10000>; - interrupts = ; - clock-names = "i2c"; - clocks = <&clockgen 4 15>; - scl-gpio = <&gpio2 15 GPIO_ACTIVE_HIGH>; - status = "disabled"; - }; - - i2c1: i2c@2010000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2010000 0x0 0x10000>; - interrupts = ; - clock-names = "i2c"; - clocks = <&clockgen 4 15>; - status = "disabled"; - }; - - i2c2: i2c@2020000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2020000 0x0 0x10000>; - interrupts = ; - clock-names = "i2c"; - clocks = <&clockgen 4 15>; - status = "disabled"; - }; - - i2c3: i2c@2030000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2030000 0x0 0x10000>; - interrupts = ; - clock-names = "i2c"; - clocks = <&clockgen 4 15>; - status = "disabled"; - }; - - i2c4: i2c@2040000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2040000 0x0 0x10000>; - interrupts = ; - clock-names = "i2c"; - clocks = <&clockgen 4 15>; - scl-gpio = <&gpio2 16 GPIO_ACTIVE_HIGH>; - status = "disabled"; - }; - - i2c5: i2c@2050000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2050000 0x0 0x10000>; - interrupts = ; - clock-names = "i2c"; - clocks = <&clockgen 4 15>; - status = "disabled"; - }; - - i2c6: i2c@2060000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2060000 0x0 0x10000>; - interrupts = ; - clock-names = "i2c"; - clocks = <&clockgen 4 15>; - status = "disabled"; - }; - - i2c7: i2c@2070000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2070000 0x0 0x10000>; - interrupts = ; - clock-names = "i2c"; - clocks = <&clockgen 4 15>; - status = "disabled"; - }; - - fspi: spi@20c0000 { - compatible = "nxp,lx2160a-fspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x20c0000 0x0 0x10000>, - <0x0 0x20000000 0x0 0x10000000>; - reg-names = "fspi_base", "fspi_mmap"; - interrupts = ; - clocks = <&clockgen 4 3>, <&clockgen 4 3>; - clock-names = "fspi_en", "fspi"; - status = "disabled"; - }; - - esdhc0: esdhc@2140000 { - compatible = "fsl,esdhc"; - reg = <0x0 0x2140000 0x0 0x10000>; - interrupts = <0 28 0x4>; /* Level high type */ - clocks = <&clockgen 4 1>; - dma-coherent; - voltage-ranges = <1800 1800 3300 3300>; - sdhci,auto-cmd12; - little-endian; - bus-width = <4>; - status = "disabled"; - }; - - esdhc1: esdhc@2150000 { - compatible = "fsl,esdhc"; - reg = <0x0 0x2150000 0x0 0x10000>; - interrupts = <0 63 0x4>; /* Level high type */ - clocks = <&clockgen 4 1>; - dma-coherent; - voltage-ranges = <1800 1800 3300 3300>; - sdhci,auto-cmd12; - broken-cd; - little-endian; - bus-width = <4>; - status = "disabled"; - }; - - uart0: serial@21c0000 { - compatible = "arm,sbsa-uart","arm,pl011"; - reg = <0x0 0x21c0000 0x0 0x1000>; - interrupts = ; - current-speed = <115200>; - status = "disabled"; - }; - - uart1: serial@21d0000 { - compatible = "arm,sbsa-uart","arm,pl011"; - reg = <0x0 0x21d0000 0x0 0x1000>; - interrupts = ; - current-speed = <115200>; - status = "disabled"; - }; - - uart2: serial@21e0000 { - compatible = "arm,sbsa-uart","arm,pl011"; - reg = <0x0 0x21e0000 0x0 0x1000>; - interrupts = ; - current-speed = <115200>; - status = "disabled"; - }; - - uart3: serial@21f0000 { - compatible = "arm,sbsa-uart","arm,pl011"; - reg = <0x0 0x21f0000 0x0 0x1000>; - interrupts = ; - current-speed = <115200>; - status = "disabled"; - }; - - gpio0: gpio@2300000 { - compatible = "fsl,qoriq-gpio"; - reg = <0x0 0x2300000 0x0 0x10000>; - interrupts = ; - gpio-controller; - little-endian; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio@2310000 { - compatible = "fsl,qoriq-gpio"; - reg = <0x0 0x2310000 0x0 0x10000>; - interrupts = ; - gpio-controller; - little-endian; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@2320000 { - compatible = "fsl,qoriq-gpio"; - reg = <0x0 0x2320000 0x0 0x10000>; - interrupts = ; - gpio-controller; - little-endian; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio@2330000 { - compatible = "fsl,qoriq-gpio"; - reg = <0x0 0x2330000 0x0 0x10000>; - interrupts = ; - gpio-controller; - little-endian; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - watchdog@23a0000 { - compatible = "arm,sbsa-gwdt"; - reg = <0x0 0x23a0000 0 0x1000>, - <0x0 0x2390000 0 0x1000>; - interrupts = ; - timeout-sec = <30>; - }; - - usb0: usb@3100000 { - compatible = "snps,dwc3"; - reg = <0x0 0x3100000 0x0 0x10000>; - interrupts = ; - dr_mode = "host"; - snps,quirk-frame-length-adjustment = <0x20>; - snps,dis_rxdet_inp3_quirk; - snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; - status = "disabled"; - }; - - usb1: usb@3110000 { - compatible = "snps,dwc3"; - reg = <0x0 0x3110000 0x0 0x10000>; - interrupts = ; - dr_mode = "host"; - snps,quirk-frame-length-adjustment = <0x20>; - snps,dis_rxdet_inp3_quirk; - snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; - status = "disabled"; - }; - - sata0: sata@3200000 { - compatible = "fsl,lx2160a-ahci"; - reg = <0x0 0x3200000 0x0 0x10000>, - <0x7 0x100520 0x0 0x4>; - reg-names = "ahci", "sata-ecc"; - interrupts = ; - clocks = <&clockgen 4 3>; - dma-coherent; - status = "disabled"; - }; - - sata1: sata@3210000 { - compatible = "fsl,lx2160a-ahci"; - reg = <0x0 0x3210000 0x0 0x10000>, - <0x7 0x100520 0x0 0x4>; - reg-names = "ahci", "sata-ecc"; - interrupts = ; - clocks = <&clockgen 4 3>; - dma-coherent; - status = "disabled"; - }; - - sata2: sata@3220000 { - compatible = "fsl,lx2160a-ahci"; - reg = <0x0 0x3220000 0x0 0x10000>, - <0x7 0x100520 0x0 0x4>; - reg-names = "ahci", "sata-ecc"; - interrupts = ; - clocks = <&clockgen 4 3>; - dma-coherent; - status = "disabled"; - }; - - sata3: sata@3230000 { - compatible = "fsl,lx2160a-ahci"; - reg = <0x0 0x3230000 0x0 0x10000>, - <0x7 0x100520 0x0 0x4>; - reg-names = "ahci", "sata-ecc"; - interrupts = ; - clocks = <&clockgen 4 3>; - dma-coherent; - status = "disabled"; - }; - - smmu: iommu@5000000 { - compatible = "arm,mmu-500"; - reg = <0 0x5000000 0 0x800000>; - #iommu-cells = <1>; - #global-interrupts = <14>; - // global secure fault - interrupts = , - // combined secure - , - // global non-secure fault - , - // combined non-secure - , - // performance counter interrupts 0-9 - , - , - , - , - , - , - , - , - , - , - // per context interrupt, 64 interrupts - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - dma-coherent; - }; - - console@8340020 { - compatible = "fsl,dpaa2-console"; - reg = <0x00000000 0x08340020 0 0x2>; - }; - - ptp-timer@8b95000 { - compatible = "fsl,dpaa2-ptp"; - reg = <0x0 0x8b95000 0x0 0x100>; - clocks = <&clockgen 4 1>; - little-endian; - fsl,extts-fifo; - }; - - /* WRIOP0: 0x8b8_0000, E-MDIO1: 0x1_6000 */ - emdio1: mdio@8b96000 { - compatible = "fsl,fman-memac-mdio"; - reg = <0x0 0x8b96000 0x0 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - little-endian; - status = "disabled"; - }; - - emdio2: mdio@8b97000 { - compatible = "fsl,fman-memac-mdio"; - reg = <0x0 0x8b97000 0x0 0x1000>; - interrupts = ; - little-endian; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - fsl_mc: fsl-mc@80c000000 { - compatible = "fsl,qoriq-mc"; - reg = <0x00000008 0x0c000000 0 0x40>, - <0x00000000 0x08340000 0 0x40000>; - msi-parent = <&its>; - /* iommu-map property is fixed up by u-boot */ - iommu-map = <0 &smmu 0 0>; - dma-coherent; - #address-cells = <3>; - #size-cells = <1>; - - /* - * Region type 0x0 - MC portals - * Region type 0x1 - QBMAN portals - */ - ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000 - 0x1 0x0 0x0 0x8 0x18000000 0x8000000>; - - /* - * Define the maximum number of MACs present on the SoC. - */ - dpmacs { - #address-cells = <1>; - #size-cells = <0>; - - dpmac1: dpmac@1 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0x1>; - }; - - dpmac2: dpmac@2 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0x2>; - }; - - dpmac3: dpmac@3 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0x3>; - }; - - dpmac4: dpmac@4 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0x4>; - }; - - dpmac5: dpmac@5 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0x5>; - }; - - dpmac6: dpmac@6 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0x6>; - }; - - dpmac7: dpmac@7 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0x7>; - }; - - dpmac8: dpmac@8 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0x8>; - }; - - dpmac9: dpmac@9 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0x9>; - }; - - dpmac10: dpmac@a { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0xa>; - }; - - dpmac11: dpmac@b { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0xb>; - }; - - dpmac12: dpmac@c { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0xc>; - }; - - dpmac13: dpmac@d { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0xd>; - }; - - dpmac14: dpmac@e { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0xe>; - }; - - dpmac15: dpmac@f { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0xf>; - }; - - dpmac16: dpmac@10 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0x10>; - }; - - dpmac17: dpmac@11 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0x11>; - }; - - dpmac18: dpmac@12 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0x12>; - }; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/freescale/imx8mm-evk.dts b/sys/gnu/dts/arm64/freescale/imx8mm-evk.dts deleted file mode 100644 index 9e54747cf4e..00000000000 --- a/sys/gnu/dts/arm64/freescale/imx8mm-evk.dts +++ /dev/null @@ -1,539 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2019 NXP - */ - -/dts-v1/; - -#include -#include "imx8mm.dtsi" - -/ { - model = "FSL i.MX8MM EVK board"; - compatible = "fsl,imx8mm-evk", "fsl,imx8mm"; - - chosen { - stdout-path = &uart2; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x0 0x40000000 0 0x80000000>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_led>; - - status { - label = "status"; - gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; - - reg_usdhc2_vmmc: regulator-usdhc2 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; - regulator-name = "VSD_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - wm8524: audio-codec { - #sound-dai-cells = <0>; - compatible = "wlf,wm8524"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_wlf>; - wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>; - }; - - sound-wm8524 { - compatible = "simple-audio-card"; - simple-audio-card,name = "wm8524-audio"; - simple-audio-card,format = "i2s"; - simple-audio-card,frame-master = <&cpudai>; - simple-audio-card,bitclock-master = <&cpudai>; - simple-audio-card,widgets = - "Line", "Left Line Out Jack", - "Line", "Right Line Out Jack"; - simple-audio-card,routing = - "Left Line Out Jack", "LINEVOUTL", - "Right Line Out Jack", "LINEVOUTR"; - - cpudai: simple-audio-card,cpu { - sound-dai = <&sai3>; - dai-tdm-slot-num = <2>; - dai-tdm-slot-width = <32>; - }; - - simple-audio-card,codec { - sound-dai = <&wm8524>; - clocks = <&clk IMX8MM_CLK_SAI3_ROOT>; - }; - }; -}; - -&A53_0 { - cpu-supply = <&buck2_reg>; -}; - -&ddrc { - operating-points-v2 = <&ddrc_opp_table>; - - ddrc_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-25M { - opp-hz = /bits/ 64 <25000000>; - }; - - opp-100M { - opp-hz = /bits/ 64 <100000000>; - }; - - opp-750M { - opp-hz = /bits/ 64 <750000000>; - }; - }; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy0>; - fsl,magic-packet; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - }; - }; -}; - -&i2c1 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pmic@4b { - compatible = "rohm,bd71847"; - reg = <0x4b>; - pinctrl-0 = <&pinctrl_pmic>; - interrupt-parent = <&gpio1>; - interrupts = <3 GPIO_ACTIVE_LOW>; - rohm,reset-snvs-powered; - - regulators { - buck1_reg: BUCK1 { - regulator-name = "BUCK1"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <1250>; - }; - - buck2_reg: BUCK2 { - regulator-name = "BUCK2"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <1250>; - rohm,dvs-run-voltage = <1000000>; - rohm,dvs-idle-voltage = <900000>; - }; - - buck3_reg: BUCK3 { - // BUCK5 in datasheet - regulator-name = "BUCK3"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1350000>; - regulator-boot-on; - regulator-always-on; - }; - - buck4_reg: BUCK4 { - // BUCK6 in datasheet - regulator-name = "BUCK4"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - buck5_reg: BUCK5 { - // BUCK7 in datasheet - regulator-name = "BUCK5"; - regulator-min-microvolt = <1605000>; - regulator-max-microvolt = <1995000>; - regulator-boot-on; - regulator-always-on; - }; - - buck6_reg: BUCK6 { - // BUCK8 in datasheet - regulator-name = "BUCK6"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1_reg: LDO1 { - regulator-name = "LDO1"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo2_reg: LDO2 { - regulator-name = "LDO2"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo3_reg: LDO3 { - regulator-name = "LDO3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo4_reg: LDO4 { - regulator-name = "LDO4"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo6_reg: LDO6 { - regulator-name = "LDO6"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; -}; - -&i2c2 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - ptn5110: tcpc@50 { - compatible = "nxp,ptn5110"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_typec1>; - reg = <0x50>; - interrupt-parent = <&gpio2>; - interrupts = <11 8>; - status = "okay"; - - port { - typec1_dr_sw: endpoint { - remote-endpoint = <&usb1_drd_sw>; - }; - }; - - typec1_con: connector { - compatible = "usb-c-connector"; - label = "USB-C"; - power-role = "dual"; - data-role = "dual"; - try-power-role = "sink"; - source-pdos = ; - sink-pdos = ; - op-sink-microwatt = <15000000>; - self-powered; - }; - }; -}; - -&i2c3 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - pca6416: gpio@20 { - compatible = "ti,tca6416"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -&sai3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai3>; - assigned-clocks = <&clk IMX8MM_CLK_SAI3>; - assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; - assigned-clock-rates = <24576000>; - status = "okay"; -}; - -&snvs_pwrkey { - status = "okay"; -}; - -&uart2 { /* console */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&usbotg1 { - dr_mode = "otg"; - hnp-disable; - srp-disable; - adp-disable; - usb-role-switch; - status = "okay"; - - port { - usb1_drd_sw: endpoint { - remote-endpoint = <&typec1_dr_sw>; - }; - }; -}; - -&usdhc2 { - assigned-clocks = <&clk IMX8MM_CLK_USDHC2>; - assigned-clock-rates = <200000000>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; - cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; - bus-width = <4>; - vmmc-supply = <®_usdhc2_vmmc>; - status = "okay"; -}; - -&usdhc3 { - assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>; - assigned-clock-rates = <400000000>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - - pinctrl_fec1: fec1grp { - fsl,pins = < - MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 - MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 - MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f - MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f - MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f - MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f - MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 - MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 - MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 - MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 - MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f - MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 - MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 - MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f - MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 - >; - }; - - pinctrl_gpio_led: gpioledgrp { - fsl,pins = < - MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 - >; - }; - - pinctrl_gpio_wlf: gpiowlfgrp { - fsl,pins = < - MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0xd6 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 - MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 - MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 - MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 - >; - }; - - pinctrl_pmic: pmicirq { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 - >; - }; - - pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc { - fsl,pins = < - MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 - >; - }; - - pinctrl_sai3: sai3grp { - fsl,pins = < - MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 - MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 - MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 - MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 - >; - }; - - pinctrl_typec1: typec1grp { - fsl,pins = < - MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x159 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 - MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 - >; - }; - - pinctrl_usdhc2_gpio: usdhc2grpgpio { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2grp100mhz { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2grp200mhz { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3grp100mhz { - fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3grp200mhz { - fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 - >; - }; -}; diff --git a/sys/gnu/dts/arm64/freescale/imx8mm-pinfunc.h b/sys/gnu/dts/arm64/freescale/imx8mm-pinfunc.h deleted file mode 100644 index 5ccc4cc9195..00000000000 --- a/sys/gnu/dts/arm64/freescale/imx8mm-pinfunc.h +++ /dev/null @@ -1,645 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2017-2018 NXP - */ - -#ifndef __DTS_IMX8MM_PINFUNC_H -#define __DTS_IMX8MM_PINFUNC_H - -/* - * The pin function ID is a tuple of - * - */ - -#define MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0 -#define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0x0 -#define MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0 -#define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0 -#define MX8MM_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0x0 -#define MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0 -#define MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0 -#define MX8MM_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0x0 -#define MX8MM_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0x0 -#define MX8MM_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0x0 -#define MX8MM_IOMUXC_GPIO1_IO02_GPIO1_IO2 0x030 0x298 0x000 0x0 0x0 -#define MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x030 0x298 0x000 0x1 0x0 -#define MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x030 0x298 0x000 0x5 0x0 -#define MX8MM_IOMUXC_GPIO1_IO02_SJC_DE_B 0x030 0x298 0x000 0x7 0x0 -#define MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x034 0x29C 0x000 0x0 0x0 -#define MX8MM_IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x034 0x29C 0x000 0x1 0x0 -#define MX8MM_IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x034 0x29C 0x000 0x5 0x0 -#define MX8MM_IOMUXC_GPIO1_IO03_ANAMIX_XTAL_OK 0x034 0x29C 0x000 0x6 0x0 -#define MX8MM_IOMUXC_GPIO1_IO03_SJC_DONE 0x034 0x29C 0x000 0x7 0x0 -#define MX8MM_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x038 0x2A0 0x000 0x0 0x0 -#define MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x038 0x2A0 0x000 0x1 0x0 -#define MX8MM_IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x038 0x2A0 0x000 0x5 0x0 -#define MX8MM_IOMUXC_GPIO1_IO04_ANAMIX_XTAL_OK_LV 0x038 0x2A0 0x000 0x6 0x0 -#define MX8MM_IOMUXC_GPIO1_IO04_USDHC1_TEST_TRIG 0x038 0x2A0 0x000 0x7 0x0 -#define MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x03C 0x2A4 0x000 0x0 0x0 -#define MX8MM_IOMUXC_GPIO1_IO05_M4_NMI 0x03C 0x2A4 0x000 0x1 0x0 -#define MX8MM_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_PMIC_READY 0x03C 0x2A4 0x000 0x5 0x0 -#define MX8MM_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_INT_BOOT 0x03C 0x2A4 0x000 0x6 0x0 -#define MX8MM_IOMUXC_GPIO1_IO05_USDHC2_TEST_TRIG 0x03C 0x2A4 0x000 0x7 0x0 -#define MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x040 0x2A8 0x000 0x0 0x0 -#define MX8MM_IOMUXC_GPIO1_IO06_ENET1_MDC 0x040 0x2A8 0x000 0x1 0x0 -#define MX8MM_IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x040 0x2A8 0x000 0x5 0x0 -#define MX8MM_IOMUXC_GPIO1_IO06_CCMSRCGPCMIX_EXT_CLK3 0x040 0x2A8 0x000 0x6 0x0 -#define MX8MM_IOMUXC_GPIO1_IO06_ECSPI1_TEST_TRIG 0x040 0x2A8 0x000 0x7 0x0 -#define MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x044 0x2AC 0x000 0x0 0x0 -#define MX8MM_IOMUXC_GPIO1_IO07_ENET1_MDIO 0x044 0x2AC 0x000 0x1 0x0 -#define MX8MM_IOMUXC_GPIO1_IO07_USDHC1_WP 0x044 0x2AC 0x000 0x5 0x0 -#define MX8MM_IOMUXC_GPIO1_IO07_CCMSRCGPCMIX_EXT_CLK4 0x044 0x2AC 0x000 0x6 0x0 -#define MX8MM_IOMUXC_GPIO1_IO07_ECSPI2_TEST_TRIG 0x044 0x2AC 0x000 0x7 0x0 -#define MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x048 0x2B0 0x000 0x0 0x0 -#define MX8MM_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x048 0x2B0 0x000 0x1 0x0 -#define MX8MM_IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x048 0x2B0 0x000 0x5 0x0 -#define MX8MM_IOMUXC_GPIO1_IO08_CCMSRCGPCMIX_WAIT 0x048 0x2B0 0x000 0x6 0x0 -#define MX8MM_IOMUXC_GPIO1_IO08_QSPI_TEST_TRIG 0x048 0x2B0 0x000 0x7 0x0 -#define MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x04C 0x2B4 0x000 0x0 0x0 -#define MX8MM_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x04C 0x2B4 0x000 0x1 0x0 -#define MX8MM_IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x04C 0x2B4 0x000 0x5 0x0 -#define MX8MM_IOMUXC_GPIO1_IO09_CCMSRCGPCMIX_STOP 0x04C 0x2B4 0x000 0x6 0x0 -#define MX8MM_IOMUXC_GPIO1_IO09_RAWNAND_TEST_TRIG 0x04C 0x2B4 0x000 0x7 0x0 -#define MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x050 0x2B8 0x000 0x0 0x0 -#define MX8MM_IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x050 0x2B8 0x000 0x1 0x0 -#define MX8MM_IOMUXC_GPIO1_IO10_OCOTP_CTRL_WRAPPER_FUSE_LATCHED 0x050 0x2B8 0x000 0x7 0x0 -#define MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x054 0x2BC 0x000 0x0 0x0 -#define MX8MM_IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x054 0x2BC 0x000 0x1 0x0 -#define MX8MM_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_PMIC_READY 0x054 0x2BC 0x4BC 0x5 0x1 -#define MX8MM_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_OUT0 0x054 0x2BC 0x000 0x6 0x0 -#define MX8MM_IOMUXC_GPIO1_IO11_CAAM_WRAPPER_RNG_OSC_OBS 0x054 0x2BC 0x000 0x7 0x0 -#define MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x058 0x2C0 0x000 0x0 0x0 -#define MX8MM_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x058 0x2C0 0x000 0x1 0x0 -#define MX8MM_IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x058 0x2C0 0x000 0x5 0x0 -#define MX8MM_IOMUXC_GPIO1_IO12_CCMSRCGPCMIX_OUT1 0x058 0x2C0 0x000 0x6 0x0 -#define MX8MM_IOMUXC_GPIO1_IO12_CSU_CSU_ALARM_AUT0 0x058 0x2C0 0x000 0x7 0x0 -#define MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x05C 0x2C4 0x000 0x0 0x0 -#define MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x05C 0x2C4 0x000 0x1 0x0 -#define MX8MM_IOMUXC_GPIO1_IO13_PWM2_OUT 0x05C 0x2C4 0x000 0x5 0x0 -#define MX8MM_IOMUXC_GPIO1_IO13_CCMSRCGPCMIX_OUT2 0x05C 0x2C4 0x000 0x6 0x0 -#define MX8MM_IOMUXC_GPIO1_IO13_CSU_CSU_ALARM_AUT1 0x05C 0x2C4 0x000 0x7 0x0 -#define MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x060 0x2C8 0x000 0x0 0x0 -#define MX8MM_IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x060 0x2C8 0x000 0x1 0x0 -#define MX8MM_IOMUXC_GPIO1_IO14_PWM3_OUT 0x060 0x2C8 0x000 0x5 0x0 -#define MX8MM_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x060 0x2C8 0x000 0x6 0x0 -#define MX8MM_IOMUXC_GPIO1_IO14_CSU_CSU_ALARM_AUT2 0x060 0x2C8 0x000 0x7 0x0 -#define MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x064 0x2CC 0x000 0x0 0x0 -#define MX8MM_IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x064 0x2CC 0x000 0x1 0x0 -#define MX8MM_IOMUXC_GPIO1_IO15_PWM4_OUT 0x064 0x2CC 0x000 0x5 0x0 -#define MX8MM_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x064 0x2CC 0x000 0x6 0x0 -#define MX8MM_IOMUXC_GPIO1_IO15_CSU_CSU_INT_DEB 0x064 0x2CC 0x000 0x7 0x0 -#define MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x068 0x2D0 0x000 0x0 0x0 -#define MX8MM_IOMUXC_ENET_MDC_GPIO1_IO16 0x068 0x2D0 0x000 0x5 0x0 -#define MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x06C 0x2D4 0x4C0 0x0 0x1 -#define MX8MM_IOMUXC_ENET_MDIO_GPIO1_IO17 0x06C 0x2D4 0x000 0x5 0x0 -#define MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x070 0x2D8 0x000 0x0 0x0 -#define MX8MM_IOMUXC_ENET_TD3_GPIO1_IO18 0x070 0x2D8 0x000 0x5 0x0 -#define MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x074 0x2DC 0x000 0x0 0x0 -#define MX8MM_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x074 0x2DC 0x000 0x1 0x0 -#define MX8MM_IOMUXC_ENET_TD2_GPIO1_IO19 0x074 0x2DC 0x000 0x5 0x0 -#define MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x078 0x2E0 0x000 0x0 0x0 -#define MX8MM_IOMUXC_ENET_TD1_GPIO1_IO20 0x078 0x2E0 0x000 0x5 0x0 -#define MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x07C 0x2E4 0x000 0x0 0x0 -#define MX8MM_IOMUXC_ENET_TD0_GPIO1_IO21 0x07C 0x2E4 0x000 0x5 0x0 -#define MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x080 0x2E8 0x000 0x0 0x0 -#define MX8MM_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x080 0x2E8 0x000 0x5 0x0 -#define MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x084 0x2EC 0x000 0x0 0x0 -#define MX8MM_IOMUXC_ENET_TXC_ENET1_TX_ER 0x084 0x2EC 0x000 0x1 0x0 -#define MX8MM_IOMUXC_ENET_TXC_GPIO1_IO23 0x084 0x2EC 0x000 0x5 0x0 -#define MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x088 0x2F0 0x000 0x0 0x0 -#define MX8MM_IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x088 0x2F0 0x000 0x5 0x0 -#define MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x08C 0x2F4 0x000 0x0 0x0 -#define MX8MM_IOMUXC_ENET_RXC_ENET1_RX_ER 0x08C 0x2F4 0x000 0x1 0x0 -#define MX8MM_IOMUXC_ENET_RXC_GPIO1_IO25 0x08C 0x2F4 0x000 0x5 0x0 -#define MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x090 0x2F8 0x000 0x0 0x0 -#define MX8MM_IOMUXC_ENET_RD0_GPIO1_IO26 0x090 0x2F8 0x000 0x5 0x0 -#define MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x094 0x2FC 0x000 0x0 0x0 -#define MX8MM_IOMUXC_ENET_RD1_GPIO1_IO27 0x094 0x2FC 0x000 0x5 0x0 -#define MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x098 0x300 0x000 0x0 0x0 -#define MX8MM_IOMUXC_ENET_RD2_GPIO1_IO28 0x098 0x300 0x000 0x5 0x0 -#define MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x09C 0x304 0x000 0x0 0x0 -#define MX8MM_IOMUXC_ENET_RD3_GPIO1_IO29 0x09C 0x304 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x0A0 0x308 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SD1_CLK_GPIO2_IO0 0x0A0 0x308 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x0A4 0x30C 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SD1_CMD_GPIO2_IO1 0x0A4 0x30C 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0A8 0x310 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SD1_DATA0_GPIO2_IO2 0x0A8 0x31 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0AC 0x314 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SD1_DATA1_GPIO2_IO3 0x0AC 0x314 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0B0 0x318 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SD1_DATA2_GPIO2_IO4 0x0B0 0x318 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x0B4 0x31C 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SD1_DATA3_GPIO2_IO5 0x0B4 0x31C 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x0B8 0x320 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x0B8 0x320 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x0BC 0x324 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x0BC 0x324 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x0C0 0x328 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x0C0 0x328 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x0C4 0x32C 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x0C4 0x32C 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x0C8 0x330 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x0C8 0x330 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x0CC 0x334 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x0CC 0x334 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0D0 0x338 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x0D0 0x338 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x0D4 0x33C 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SD2_CLK_GPIO2_IO13 0x0D4 0x33C 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SD2_CLK_CCMSRCGPCMIX_OBSERVE0 0x0D4 0x33C 0x000 0x6 0x0 -#define MX8MM_IOMUXC_SD2_CLK_OBSERVE_MUX_OUT0 0x0D4 0x33C 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x0D8 0x340 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SD2_CMD_GPIO2_IO14 0x0D8 0x340 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SD2_CMD_CCMSRCGPCMIX_OBSERVE1 0x0D8 0x340 0x000 0x6 0x0 -#define MX8MM_IOMUXC_SD2_CMD_OBSERVE_MUX_OUT1 0x0D8 0x340 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0DC 0x344 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SD2_DATA0_GPIO2_IO15 0x0DC 0x344 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SD2_DATA0_CCMSRCGPCMIX_OBSERVE2 0x0DC 0x344 0x000 0x6 0x0 -#define MX8MM_IOMUXC_SD2_DATA0_OBSERVE_MUX_OUT2 0x0DC 0x344 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0E0 0x348 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SD2_DATA1_GPIO2_IO16 0x0E0 0x348 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SD2_DATA1_CCMSRCGPCMIX_WAIT 0x0E0 0x348 0x000 0x6 0x0 -#define MX8MM_IOMUXC_SD2_DATA1_OBSERVE_MUX_OUT3 0x0E0 0x348 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0E4 0x34C 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SD2_DATA2_GPIO2_IO17 0x0E4 0x34C 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SD2_DATA2_CCMSRCGPCMIX_STOP 0x0E4 0x34C 0x000 0x6 0x0 -#define MX8MM_IOMUXC_SD2_DATA2_OBSERVE_MUX_OUT4 0x0E4 0x34C 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0E8 0x350 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SD2_DATA3_GPIO2_IO18 0x0E8 0x350 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SD2_DATA3_CCMSRCGPCMIX_EARLY_RESET 0x0E8 0x350 0x000 0x6 0x0 -#define MX8MM_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x0EC 0x354 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x0EC 0x354 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SD2_RESET_B_CCMSRCGPCMIX_SYSTEM_RESET 0x0EC 0x354 0x000 0x6 0x0 -#define MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x0F0 0x358 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SD2_WP_GPIO2_IO20 0x0F0 0x358 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SD2_WP_SIM_M_HMASTLOCK 0x0F0 0x358 0x000 0x7 0x0 -#define MX8MM_IOMUXC_NAND_ALE_RAWNAND_ALE 0x0F4 0x35C 0x000 0x0 0x0 -#define MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x0F4 0x35C 0x000 0x1 0x0 -#define MX8MM_IOMUXC_NAND_ALE_GPIO3_IO0 0x0F4 0x35C 0x000 0x5 0x0 -#define MX8MM_IOMUXC_NAND_ALE_SIM_M_HPROT0 0x0F4 0x35C 0x000 0x7 0x0 -#define MX8MM_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x0F8 0x360 0x000 0x0 0x0 -#define MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x0F8 0x360 0x000 0x1 0x0 -#define MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x0F8 0x360 0x000 0x5 0x0 -#define MX8MM_IOMUXC_NAND_CE0_B_SIM_M_HPROT1 0x0F8 0x360 0x000 0x7 0x0 -#define MX8MM_IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x0FC 0x364 0x000 0x0 0x0 -#define MX8MM_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x0FC 0x364 0x000 0x1 0x0 -#define MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x0FC 0x364 0x000 0x2 0x0 -#define MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x0FC 0x364 0x000 0x5 0x0 -#define MX8MM_IOMUXC_NAND_CE1_B_SIM_M_HPROT2 0x0FC 0x364 0x000 0x7 0x0 -#define MX8MM_IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x100 0x368 0x000 0x0 0x0 -#define MX8MM_IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x100 0x368 0x000 0x1 0x0 -#define MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x100 0x368 0x000 0x2 0x0 -#define MX8MM_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x100 0x368 0x000 0x5 0x0 -#define MX8MM_IOMUXC_NAND_CE2_B_SIM_M_HPROT3 0x100 0x368 0x000 0x7 0x0 -#define MX8MM_IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x104 0x36C 0x000 0x0 0x0 -#define MX8MM_IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x104 0x36C 0x000 0x1 0x0 -#define MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x104 0x36C 0x000 0x2 0x0 -#define MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x104 0x36C 0x000 0x5 0x0 -#define MX8MM_IOMUXC_NAND_CE3_B_SIM_M_HADDR0 0x104 0x36C 0x000 0x7 0x0 -#define MX8MM_IOMUXC_NAND_CLE_RAWNAND_CLE 0x108 0x370 0x000 0x0 0x0 -#define MX8MM_IOMUXC_NAND_CLE_QSPI_B_SCLK 0x108 0x370 0x000 0x1 0x0 -#define MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x108 0x370 0x000 0x2 0x0 -#define MX8MM_IOMUXC_NAND_CLE_GPIO3_IO5 0x108 0x370 0x000 0x5 0x0 -#define MX8MM_IOMUXC_NAND_CLE_SIM_M_HADDR1 0x108 0x370 0x000 0x7 0x0 -#define MX8MM_IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x10C 0x374 0x000 0x0 0x0 -#define MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x10C 0x374 0x000 0x1 0x0 -#define MX8MM_IOMUXC_NAND_DATA00_GPIO3_IO6 0x10C 0x374 0x000 0x5 0x0 -#define MX8MM_IOMUXC_NAND_DATA00_SIM_M_HADDR2 0x10C 0x374 0x000 0x7 0x0 -#define MX8MM_IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x110 0x378 0x000 0x0 0x0 -#define MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x110 0x378 0x000 0x1 0x0 -#define MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7 0x110 0x378 0x000 0x5 0x0 -#define MX8MM_IOMUXC_NAND_DATA01_SIM_M_HADDR3 0x110 0x378 0x000 0x7 0x0 -#define MX8MM_IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x114 0x37C 0x000 0x0 0x0 -#define MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x114 0x37C 0x000 0x1 0x0 -#define MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8 0x114 0x37C 0x000 0x5 0x0 -#define MX8MM_IOMUXC_NAND_DATA02_SIM_M_HADDR4 0x114 0x37C 0x000 0x7 0x0 -#define MX8MM_IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x118 0x380 0x000 0x0 0x0 -#define MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x118 0x380 0x000 0x1 0x0 -#define MX8MM_IOMUXC_NAND_DATA03_GPIO3_IO9 0x118 0x380 0x000 0x5 0x0 -#define MX8MM_IOMUXC_NAND_DATA03_SIM_M_HADDR5 0x118 0x380 0x000 0x7 0x0 -#define MX8MM_IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x11C 0x384 0x000 0x0 0x0 -#define MX8MM_IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x11C 0x384 0x000 0x1 0x0 -#define MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x11C 0x384 0x000 0x2 0x0 -#define MX8MM_IOMUXC_NAND_DATA04_GPIO3_IO10 0x11C 0x384 0x000 0x5 0x0 -#define MX8MM_IOMUXC_NAND_DATA04_SIM_M_HADDR6 0x11C 0x384 0x000 0x7 0x0 -#define MX8MM_IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x120 0x388 0x000 0x0 0x0 -#define MX8MM_IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x120 0x388 0x000 0x1 0x0 -#define MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x120 0x388 0x000 0x2 0x0 -#define MX8MM_IOMUXC_NAND_DATA05_GPIO3_IO11 0x120 0x388 0x000 0x5 0x0 -#define MX8MM_IOMUXC_NAND_DATA05_SIM_M_HADDR7 0x120 0x388 0x000 0x7 0x0 -#define MX8MM_IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x124 0x38C 0x000 0x0 0x0 -#define MX8MM_IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x124 0x38C 0x000 0x1 0x0 -#define MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x124 0x38C 0x000 0x2 0x0 -#define MX8MM_IOMUXC_NAND_DATA06_GPIO3_IO12 0x124 0x38C 0x000 0x5 0x0 -#define MX8MM_IOMUXC_NAND_DATA06_SIM_M_HADDR8 0x124 0x38C 0x000 0x7 0x0 -#define MX8MM_IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x128 0x390 0x000 0x0 0x0 -#define MX8MM_IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x128 0x390 0x000 0x1 0x0 -#define MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x128 0x390 0x000 0x2 0x0 -#define MX8MM_IOMUXC_NAND_DATA07_GPIO3_IO13 0x128 0x390 0x000 0x5 0x0 -#define MX8MM_IOMUXC_NAND_DATA07_SIM_M_HADDR9 0x128 0x390 0x000 0x7 0x0 -#define MX8MM_IOMUXC_NAND_DQS_RAWNAND_DQS 0x12C 0x394 0x000 0x0 0x0 -#define MX8MM_IOMUXC_NAND_DQS_QSPI_A_DQS 0x12C 0x394 0x000 0x1 0x0 -#define MX8MM_IOMUXC_NAND_DQS_GPIO3_IO14 0x12C 0x394 0x000 0x5 0x0 -#define MX8MM_IOMUXC_NAND_DQS_SIM_M_HADDR10 0x12C 0x394 0x000 0x7 0x0 -#define MX8MM_IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x130 0x398 0x000 0x0 0x0 -#define MX8MM_IOMUXC_NAND_RE_B_QSPI_B_DQS 0x130 0x398 0x000 0x1 0x0 -#define MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x130 0x398 0x000 0x2 0x0 -#define MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15 0x130 0x398 0x000 0x5 0x0 -#define MX8MM_IOMUXC_NAND_RE_B_SIM_M_HADDR11 0x130 0x398 0x000 0x7 0x0 -#define MX8MM_IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x134 0x39C 0x000 0x0 0x0 -#define MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x134 0x39C 0x000 0x5 0x0 -#define MX8MM_IOMUXC_NAND_READY_B_SIM_M_HADDR12 0x134 0x39C 0x000 0x7 0x0 -#define MX8MM_IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x138 0x3A0 0x000 0x0 0x0 -#define MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x138 0x3A0 0x000 0x12 0x0 -#define MX8MM_IOMUXC_NAND_WE_B_GPIO3_IO17 0x138 0x3A0 0x000 0x5 0x0 -#define MX8MM_IOMUXC_NAND_WE_B_SIM_M_HADDR13 0x138 0x3A0 0x000 0x7 0x0 -#define MX8MM_IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x13C 0x3A4 0x000 0x0 0x0 -#define MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x13C 0x3A4 0x000 0x2 0x0 -#define MX8MM_IOMUXC_NAND_WP_B_GPIO3_IO18 0x13C 0x3A4 0x000 0x5 0x0 -#define MX8MM_IOMUXC_NAND_WP_B_SIM_M_HADDR14 0x13C 0x3A4 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x140 0x3A8 0x4E4 0x0 0x0 -#define MX8MM_IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x140 0x3A8 0x000 0x1 0x0 -#define MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x140 0x3A8 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x144 0x3AC 0x4D0 0x0 0x0 -#define MX8MM_IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x144 0x3AC 0x000 0x1 0x0 -#define MX8MM_IOMUXC_SAI5_RXC_PDM_CLK 0x144 0x3AC 0x000 0x4 0x0 -#define MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x144 0x3AC 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x148 0x3B0 0x4D4 0x0 0x0 -#define MX8MM_IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x148 0x3B0 0x000 0x1 0x0 -#define MX8MM_IOMUXC_SAI5_RXD0_PDM_DATA0 0x148 0x3B0 0x534 0x4 0x0 -#define MX8MM_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x148 0x3B0 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x14C 0x3B4 0x4D8 0x0 0x0 -#define MX8MM_IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x14C 0x3B4 0x000 0x1 0x0 -#define MX8MM_IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x14C 0x3B4 0x4CC 0x2 0x0 -#define MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x14C 0x3B4 0x4EC 0x3 0x0 -#define MX8MM_IOMUXC_SAI5_RXD1_PDM_DATA1 0x14C 0x3B4 0x538 0x4 0x0 -#define MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x14C 0x3B4 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x150 0x3B8 0x4DC 0x0 0x0 -#define MX8MM_IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x150 0x3B8 0x000 0x1 0x0 -#define MX8MM_IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x150 0x3B8 0x4CC 0x2 0x1 -#define MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x150 0x3B8 0x4E8 0x3 0x0 -#define MX8MM_IOMUXC_SAI5_RXD2_PDM_DATA2 0x150 0x3B8 0x53c 0x4 0x0 -#define MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x150 0x3B8 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x154 0x3BC 0x4E0 0x0 0x0 -#define MX8MM_IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x154 0x3BC 0x000 0x1 0x0 -#define MX8MM_IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x154 0x3BC 0x4CC 0x2 0x2 -#define MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x154 0x3BC 0x000 0x3 0x0 -#define MX8MM_IOMUXC_SAI5_RXD3_PDM_DATA3 0x154 0x3BC 0x540 0x4 0x0 -#define MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x154 0x3BC 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI5_MCLK_SAI5_MCLK 0x158 0x3C0 0x52C 0x0 0x0 -#define MX8MM_IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x158 0x3C0 0x4C8 0x1 0x0 -#define MX8MM_IOMUXC_SAI5_MCLK_SAI4_MCLK 0x158 0x3C0 0x000 0x2 0x0 -#define MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x158 0x3C0 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI5_MCLK_CCMSRCGPCMIX_TESTER_ACK 0x158 0x3C0 0x000 0x6 0x0 -#define MX8MM_IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x15C 0x3C4 0x4C4 0x0 0x0 -#define MX8MM_IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x15C 0x3C4 0x4E4 0x1 0x1 -#define MX8MM_IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x15C 0x3C4 0x000 0x4 0x0 -#define MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x15C 0x3C4 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI1_RXFS_SIM_M_HADDR15 0x15C 0x3C4 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x160 0x3C8 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x160 0x3C8 0x4D0 0x1 0x1 -#define MX8MM_IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x160 0x3C8 0x000 0x4 0x0 -#define MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x160 0x3C8 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI1_RXC_SIM_M_HADDR16 0x160 0x3C8 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x164 0x3CC 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x164 0x3CC 0x4D4 0x1 0x1 -#define MX8MM_IOMUXC_SAI1_RXD0_PDM_DATA0 0x164 0x3CC 0x534 0x3 0x1 -#define MX8MM_IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x164 0x3CC 0x000 0x4 0x0 -#define MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x164 0x3CC 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI1_RXD0_CCMSRCGPCMIX_BOOT_CFG0 0x164 0x3CC 0x000 0x6 0x0 -#define MX8MM_IOMUXC_SAI1_RXD0_SIM_M_HADDR17 0x164 0x3CC 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x168 0x3D0 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x168 0x3D0 0x4D8 0x1 0x1 -#define MX8MM_IOMUXC_SAI1_RXD1_PDM_DATA1 0x168 0x3D0 0x538 0x3 0x1 -#define MX8MM_IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x168 0x3D0 0x000 0x4 0x0 -#define MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x168 0x3D0 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI1_RXD1_CCMSRCGPCMIX_BOOT_CFG1 0x168 0x3D0 0x000 0x6 0x0 -#define MX8MM_IOMUXC_SAI1_RXD1_SIM_M_HADDR18 0x168 0x3D0 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x16C 0x3D4 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x16C 0x3D4 0x4DC 0x1 0x1 -#define MX8MM_IOMUXC_SAI1_RXD2_PDM_DATA2 0x16C 0x3D4 0x53C 0x3 0x1 -#define MX8MM_IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x16C 0x3D4 0x000 0x4 0x0 -#define MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x16C 0x3D4 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI1_RXD2_CCMSRCGPCMIX_BOOT_CFG2 0x16C 0x3D4 0x000 0x6 0x0 -#define MX8MM_IOMUXC_SAI1_RXD2_SIM_M_HADDR19 0x16C 0x3D4 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x170 0x3D8 0x4E0 0x0 0x1 -#define MX8MM_IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x170 0x3D8 0x000 0x1 0x0 -#define MX8MM_IOMUXC_SAI1_RXD3_PDM_DATA3 0x170 0x3D8 0x540 0x3 0x1 -#define MX8MM_IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x170 0x3D8 0x000 0x4 0x0 -#define MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x170 0x3D8 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI1_RXD3_CCMSRCGPCMIX_BOOT_CFG3 0x170 0x3D8 0x000 0x6 0x0 -#define MX8MM_IOMUXC_SAI1_RXD3_SIM_M_HADDR20 0x170 0x3D8 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x174 0x3DC 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x174 0x3DC 0x51C 0x1 0x0 -#define MX8MM_IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x174 0x3DC 0x510 0x2 0x0 -#define MX8MM_IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x174 0x3DC 0x000 0x4 0x0 -#define MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x174 0x3DC 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI1_RXD4_CCMSRCGPCMIX_BOOT_CFG4 0x174 0x3DC 0x000 0x6 0x0 -#define MX8MM_IOMUXC_SAI1_RXD4_SIM_M_HADDR21 0x174 0x3DC 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x178 0x3E0 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x178 0x3E0 0x000 0x1 0x0 -#define MX8MM_IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x178 0x3E0 0x514 0x2 0x0 -#define MX8MM_IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x178 0x3E0 0x4C4 0x3 0x1 -#define MX8MM_IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x178 0x3E0 0x000 0x4 0x0 -#define MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x178 0x3E0 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI1_RXD5_CCMSRCGPCMIX_BOOT_CFG5 0x178 0x3E0 0x000 0x6 0x0 -#define MX8MM_IOMUXC_SAI1_RXD5_SIM_M_HADDR22 0x178 0x3E0 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x17C 0x3E4 0x520 0x0 0x0 -#define MX8MM_IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x17C 0x3E4 0x000 0x1 0x0 -#define MX8MM_IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x17C 0x3E4 0x518 0x2 0x0 -#define MX8MM_IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x17C 0x3E4 0x000 0x4 0x0 -#define MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x17C 0x3E4 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI1_RXD6_CCMSRCGPCMIX_BOOT_CFG6 0x17C 0x3E4 0x000 0x6 0x0 -#define MX8MM_IOMUXC_SAI1_RXD6_SIM_M_HADDR23 0x17C 0x3E4 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x180 0x3E8 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SAI1_RXD7_SAI6_MCLK 0x180 0x3E8 0x530 0x1 0x0 -#define MX8MM_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x180 0x3E8 0x4CC 0x2 0x4 -#define MX8MM_IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x180 0x3E8 0x000 0x3 0x0 -#define MX8MM_IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x180 0x3E8 0x000 0x4 0x0 -#define MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x180 0x3E8 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI1_RXD7_CCMSRCGPCMIX_BOOT_CFG7 0x180 0x3E8 0x000 0x6 0x0 -#define MX8MM_IOMUXC_SAI1_RXD7_SIM_M_HADDR24 0x180 0x3E8 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x184 0x3EC 0x4CC 0x0 0x3 -#define MX8MM_IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x184 0x3EC 0x4EC 0x1 0x1 -#define MX8MM_IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x184 0x3EC 0x000 0x4 0x0 -#define MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x184 0x3EC 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI1_TXFS_SIM_M_HADDR25 0x184 0x3EC 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x188 0x3F0 0x4C8 0x0 0x1 -#define MX8MM_IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x188 0x3F0 0x4E8 0x1 0x1 -#define MX8MM_IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x188 0x3F0 0x000 0x4 0x0 -#define MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x188 0x3F0 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI1_TXC_SIM_M_HADDR26 0x188 0x3F0 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x18C 0x3F4 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x18C 0x3F4 0x000 0x1 0x0 -#define MX8MM_IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x18C 0x3F4 0x000 0x4 0x0 -#define MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x18C 0x3F4 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI1_TXD0_CCMSRCGPCMIX_BOOT_CFG8 0x18C 0x3F4 0x000 0x6 0x0 -#define MX8MM_IOMUXC_SAI1_TXD0_SIM_M_HADDR27 0x18C 0x3F4 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x190 0x3F8 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x190 0x3F8 0x000 0x1 0x0 -#define MX8MM_IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x190 0x3F8 0x000 0x4 0x0 -#define MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x190 0x3F8 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI1_TXD1_CCMSRCGPCMIX_BOOT_CFG9 0x190 0x3F8 0x000 0x6 0x0 -#define MX8MM_IOMUXC_SAI1_TXD1_SIM_M_HADDR28 0x190 0x3F8 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x194 0x3FC 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x194 0x3FC 0x000 0x1 0x0 -#define MX8MM_IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x194 0x3FC 0x000 0x4 0x0 -#define MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x194 0x3FC 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI1_TXD2_CCMSRCGPCMIX_BOOT_CFG10 0x194 0x3FC 0x000 0x6 0x0 -#define MX8MM_IOMUXC_SAI1_TXD2_SIM_M_HADDR29 0x194 0x3FC 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x198 0x400 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x198 0x400 0x000 0x1 0x0 -#define MX8MM_IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x198 0x400 0x000 0x4 0x0 -#define MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x198 0x400 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI1_TXD3_CCMSRCGPCMIX_BOOT_CFG11 0x198 0x400 0x000 0x6 0x0 -#define MX8MM_IOMUXC_SAI1_TXD3_SIM_M_HADDR30 0x198 0x400 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x19C 0x404 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x19C 0x404 0x510 0x1 0x1 -#define MX8MM_IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x19C 0x404 0x51C 0x2 0x1 -#define MX8MM_IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x19C 0x404 0x000 0x4 0x0 -#define MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x19C 0x404 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI1_TXD4_CCMSRCGPCMIX_BOOT_CFG12 0x19C 0x404 0x000 0x6 0x0 -#define MX8MM_IOMUXC_SAI1_TXD4_SIM_M_HADDR31 0x19C 0x404 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x1A0 0x408 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x1A0 0x408 0x514 0x1 0x1 -#define MX8MM_IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x1A0 0x408 0x000 0x2 0x0 -#define MX8MM_IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x1A0 0x408 0x000 0x4 0x0 -#define MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x1A0 0x408 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI1_TXD5_CCMSRCGPCMIX_BOOT_CFG13 0x1A0 0x408 0x000 0x6 0x0 -#define MX8MM_IOMUXC_SAI1_TXD5_SIM_M_HBURST0 0x1A0 0x408 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x1A4 0x40C 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x1A4 0x40C 0x518 0x1 0x1 -#define MX8MM_IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x1A4 0x40C 0x520 0x2 0x1 -#define MX8MM_IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x1A4 0x40C 0x000 0x4 0x0 -#define MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x1A4 0x40C 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI1_TXD6_CCMSRCGPCMIX_BOOT_CFG14 0x1A4 0x40C 0x000 0x6 0x0 -#define MX8MM_IOMUXC_SAI1_TXD6_SIM_M_HBURST1 0x1A4 0x40C 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x1A8 0x410 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SAI1_TXD7_SAI6_MCLK 0x1A8 0x410 0x530 0x1 0x1 -#define MX8MM_IOMUXC_SAI1_TXD7_PDM_CLK 0x1A8 0x410 0x000 0x3 0x0 -#define MX8MM_IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x1A8 0x410 0x000 0x4 0x0 -#define MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x1A8 0x410 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI1_TXD7_CCMSRCGPCMIX_BOOT_CFG15 0x1A8 0x410 0x000 0x6 0x0 -#define MX8MM_IOMUXC_SAI1_TXD7_SIM_M_HBURST2 0x1A8 0x410 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI1_MCLK_SAI1_MCLK 0x1AC 0x414 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SAI1_MCLK_SAI5_MCLK 0x1AC 0x414 0x52C 0x1 0x1 -#define MX8MM_IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x1AC 0x414 0x4C8 0x2 0x2 -#define MX8MM_IOMUXC_SAI1_MCLK_PDM_CLK 0x1AC 0x414 0x000 0x3 0x0 -#define MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x1AC 0x414 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI1_MCLK_SIM_M_HRESP 0x1AC 0x414 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x1B0 0x418 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x1B0 0x418 0x4EC 0x1 0x2 -#define MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x1B0 0x418 0x000 0x4 0x0 -#define MX8MM_IOMUXC_SAI2_RXFS_UART1_DTE_RX 0x1B0 0x418 0x4F4 0x4 0x2 -#define MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x1B0 0x418 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI2_RXFS_SIM_M_HSIZE0 0x1B0 0x418 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x1B4 0x41C 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x1B4 0x41C 0x4E8 0x1 0x2 -#define MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x1B4 0x41C 0x4F4 0x4 0x3 -#define MX8MM_IOMUXC_SAI2_RXC_UART1_DTE_TX 0x1B4 0x41C 0x000 0x4 0x0 -#define MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x1B4 0x41C 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI2_RXC_SIM_M_HSIZE1 0x1B4 0x41C 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x1B8 0x420 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x1B8 0x420 0x000 0x1 0x0 -#define MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x1B8 0x420 0x4F0 0x4 0x2 -#define MX8MM_IOMUXC_SAI2_RXD0_UART1_DTE_CTS_B 0x1B8 0x420 0x000 0x4 0x0 -#define MX8MM_IOMUXC_SAI2_RXD0_GPIO4_IO23 0x1B8 0x420 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI2_RXD0_SIM_M_HSIZE2 0x1B8 0x420 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x1BC 0x424 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x1BC 0x424 0x000 0x1 0x0 -#define MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x1BC 0x424 0x000 0x4 0x0 -#define MX8MM_IOMUXC_SAI2_TXFS_UART1_DTE_RTS_B 0x1BC 0x424 0x4F0 0x4 0x3 -#define MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x1BC 0x424 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI2_TXFS_SIM_M_HWRITE 0x1BC 0x424 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x1C0 0x428 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x1C0 0x428 0x000 0x1 0x0 -#define MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 0x1C0 0x428 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI2_TXC_SIM_M_HREADYOUT 0x1C0 0x428 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x1C4 0x42C 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x1C4 0x42C 0x000 0x1 0x0 -#define MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x1C4 0x42C 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI2_TXD0_TPSMP_CLK 0x1C4 0x42C 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI2_MCLK_SAI2_MCLK 0x1C8 0x430 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SAI2_MCLK_SAI5_MCLK 0x1C8 0x430 0x52C 0x1 0x2 -#define MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x1C8 0x430 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI2_MCLK_TPSMP_HDATA_DIR 0x1C8 0x430 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x1CC 0x434 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x1CC 0x434 0x000 0x1 0x0 -#define MX8MM_IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x1CC 0x434 0x4E4 0x2 0x2 -#define MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x1CC 0x434 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI3_RXFS_TPSMP_HTRANS0 0x1CC 0x434 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x1D0 0x438 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SAI3_RXC_GPT1_CLK 0x1D0 0x438 0x000 0x1 0x0 -#define MX8MM_IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x1D0 0x438 0x4D0 0x2 0x2 -#define MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x1D0 0x438 0x000 0x4 0x0 -#define MX8MM_IOMUXC_SAI3_RXC_UART2_DTE_RTS_B 0x1D0 0x438 0x4F8 0x4 0x2 -#define MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29 0x1D0 0x438 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI3_RXC_TPSMP_HTRANS1 0x1D0 0x438 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x1D4 0x43C 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x1D4 0x43C 0x000 0x1 0x0 -#define MX8MM_IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x1D4 0x43C 0x4D4 0x2 0x2 -#define MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x1D4 0x43C 0x4F8 0x4 0x3 -#define MX8MM_IOMUXC_SAI3_RXD_UART2_DTE_CTS_B 0x1D4 0x43C 0x000 0x4 0x0 -#define MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30 0x1D4 0x43C 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI3_RXD_TPSMP_HDATA0 0x1D4 0x43C 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x1D8 0x440 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SAI3_TXFS_GPT1_CAPTURE2 0x1D8 0x440 0x000 0x1 0x0 -#define MX8MM_IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x1D8 0x440 0x4D8 0x2 0x2 -#define MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x1D8 0x440 0x4Fc 0x4 0x2 -#define MX8MM_IOMUXC_SAI3_TXFS_UART2_DTE_TX 0x1D8 0x440 0x000 0x4 0x0 -#define MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x1D8 0x440 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI3_TXFS_TPSMP_HDATA1 0x1D8 0x440 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x1DC 0x444 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x1DC 0x444 0x000 0x1 0x0 -#define MX8MM_IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x1DC 0x444 0x4DC 0x2 0x2 -#define MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x1DC 0x444 0x000 0x4 0x0 -#define MX8MM_IOMUXC_SAI3_TXC_UART2_DTE_RX 0x1DC 0x444 0x4Fc 0x4 0x3 -#define MX8MM_IOMUXC_SAI3_TXC_GPIO5_IO0 0x1DC 0x444 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI3_TXC_TPSMP_HDATA2 0x1DC 0x444 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x1E0 0x448 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x1E0 0x448 0x000 0x1 0x0 -#define MX8MM_IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x1E0 0x448 0x4E0 0x2 0x2 -#define MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x1E0 0x448 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI3_TXD_TPSMP_HDATA3 0x1E0 0x448 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0x1E4 0x44C 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SAI3_MCLK_PWM4_OUT 0x1E4 0x44C 0x000 0x1 0x0 -#define MX8MM_IOMUXC_SAI3_MCLK_SAI5_MCLK 0x1E4 0x44C 0x52C 0x2 0x3 -#define MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x1E4 0x44C 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI3_MCLK_TPSMP_HDATA4 0x1E4 0x44C 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SPDIF_TX_SPDIF1_OUT 0x1E8 0x450 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SPDIF_TX_PWM3_OUT 0x1E8 0x450 0x000 0x1 0x0 -#define MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x1E8 0x450 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SPDIF_TX_TPSMP_HDATA5 0x1E8 0x450 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SPDIF_RX_SPDIF1_IN 0x1EC 0x454 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x1EC 0x454 0x000 0x1 0x0 -#define MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x1EC 0x454 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SPDIF_RX_TPSMP_HDATA6 0x1EC 0x454 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x1F0 0x458 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x1F0 0x458 0x000 0x1 0x0 -#define MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x1F0 0x458 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SPDIF_EXT_CLK_TPSMP_HDATA7 0x1F0 0x458 0x000 0x7 0x0 -#define MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x1F4 0x45C 0x000 0x0 0x0 -#define MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x1F4 0x45C 0x504 0x1 0x0 -#define MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DTE_TX 0x1F4 0x45C 0x000 0x1 0x0 -#define MX8MM_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x1F4 0x45C 0x000 0x5 0x0 -#define MX8MM_IOMUXC_ECSPI1_SCLK_TPSMP_HDATA8 0x1F4 0x45C 0x000 0x7 0x0 -#define MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x1F8 0x460 0x000 0x0 0x0 -#define MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x1F8 0x460 0x000 0x1 0x0 -#define MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DTE_RX 0x1F8 0x460 0x504 0x1 0x1 -#define MX8MM_IOMUXC_ECSPI1_MOSI_GPIO5_IO7 0x1F8 0x460 0x000 0x5 0x0 -#define MX8MM_IOMUXC_ECSPI1_MOSI_TPSMP_HDATA9 0x1F8 0x460 0x000 0x7 0x0 -#define MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x1FC 0x464 0x000 0x0 0x0 -#define MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x1FC 0x464 0x000 0x1 0x0 -#define MX8MM_IOMUXC_ECSPI1_MISO_UART3_DTE_RTS_B 0x1FC 0x464 0x500 0x1 0x0 -#define MX8MM_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x1FC 0x464 0x000 0x5 0x0 -#define MX8MM_IOMUXC_ECSPI1_MISO_TPSMP_HDATA10 0x1FC 0x464 0x000 0x7 0x0 -#define MX8MM_IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x200 0x468 0x000 0x0 0x0 -#define MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x200 0x468 0x500 0x1 0x1 -#define MX8MM_IOMUXC_ECSPI1_SS0_UART3_DTE_CTS_B 0x200 0x468 0x000 0x1 0x0 -#define MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x200 0x468 0x000 0x5 0x0 -#define MX8MM_IOMUXC_ECSPI1_SS0_TPSMP_HDATA11 0x200 0x468 0x000 0x7 0x0 -#define MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x204 0x46C 0x000 0x0 0x0 -#define MX8MM_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x204 0x46C 0x50C 0x1 0x0 -#define MX8MM_IOMUXC_ECSPI2_SCLK_UART4_DTE_TX 0x204 0x46C 0x000 0x1 0x0 -#define MX8MM_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x204 0x46C 0x000 0x5 0x0 -#define MX8MM_IOMUXC_ECSPI2_SCLK_TPSMP_HDATA12 0x204 0x46C 0x000 0x7 0x0 -#define MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x208 0x470 0x000 0x0 0x0 -#define MX8MM_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x208 0x470 0x000 0x1 0x0 -#define MX8MM_IOMUXC_ECSPI2_MOSI_UART4_DTE_RX 0x208 0x470 0x50C 0x1 0x1 -#define MX8MM_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x208 0x470 0x000 0x5 0x0 -#define MX8MM_IOMUXC_ECSPI2_MOSI_TPSMP_HDATA13 0x208 0x470 0x000 0x7 0x0 -#define MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x20C 0x474 0x000 0x0 0x0 -#define MX8MM_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x20C 0x474 0x000 0x1 0x0 -#define MX8MM_IOMUXC_ECSPI2_MISO_UART4_DTE_RTS_B 0x20C 0x474 0x508 0x1 0x0 -#define MX8MM_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x20C 0x474 0x000 0x5 0x0 -#define MX8MM_IOMUXC_ECSPI2_MISO_TPSMP_HDATA14 0x20C 0x474 0x000 0x7 0x0 -#define MX8MM_IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x210 0x478 0x000 0x0 0x0 -#define MX8MM_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x210 0x478 0x508 0x1 0x1 -#define MX8MM_IOMUXC_ECSPI2_SS0_UART4_DTE_CTS_B 0x210 0x478 0x000 0x1 0x0 -#define MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x210 0x478 0x000 0x5 0x0 -#define MX8MM_IOMUXC_ECSPI2_SS0_TPSMP_HDATA15 0x210 0x478 0x000 0x7 0x0 -#define MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x214 0x47C 0x000 0x0 0x0 -#define MX8MM_IOMUXC_I2C1_SCL_ENET1_MDC 0x214 0x47C 0x000 0x1 0x0 -#define MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x214 0x47C 0x000 0x5 0x0 -#define MX8MM_IOMUXC_I2C1_SCL_TPSMP_HDATA16 0x214 0x47C 0x000 0x7 0x0 -#define MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x218 0x480 0x000 0x0 0x0 -#define MX8MM_IOMUXC_I2C1_SDA_ENET1_MDIO 0x218 0x480 0x4C0 0x1 0x2 -#define MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x218 0x480 0x000 0x5 0x0 -#define MX8MM_IOMUXC_I2C1_SDA_TPSMP_HDATA17 0x218 0x480 0x000 0x7 0x0 -#define MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x21C 0x484 0x000 0x0 0x0 -#define MX8MM_IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x21C 0x484 0x000 0x1 0x0 -#define MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x21C 0x484 0x000 0x5 0x0 -#define MX8MM_IOMUXC_I2C2_SCL_TPSMP_HDATA18 0x21C 0x484 0x000 0x7 0x0 -#define MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x220 0x488 0x000 0x0 0x0 -#define MX8MM_IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x220 0x488 0x000 0x1 0x0 -#define MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x220 0x488 0x000 0x5 0x0 -#define MX8MM_IOMUXC_I2C2_SDA_TPSMP_HDATA19 0x220 0x488 0x000 0x7 0x0 -#define MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x224 0x48C 0x000 0x0 0x0 -#define MX8MM_IOMUXC_I2C3_SCL_PWM4_OUT 0x224 0x48C 0x000 0x1 0x0 -#define MX8MM_IOMUXC_I2C3_SCL_GPT2_CLK 0x224 0x48C 0x000 0x2 0x0 -#define MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x224 0x48C 0x000 0x5 0x0 -#define MX8MM_IOMUXC_I2C3_SCL_TPSMP_HDATA20 0x224 0x48C 0x000 0x7 0x0 -#define MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x228 0x490 0x000 0x0 0x0 -#define MX8MM_IOMUXC_I2C3_SDA_PWM3_OUT 0x228 0x490 0x000 0x1 0x0 -#define MX8MM_IOMUXC_I2C3_SDA_GPT3_CLK 0x228 0x490 0x000 0x2 0x0 -#define MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x228 0x490 0x000 0x5 0x0 -#define MX8MM_IOMUXC_I2C3_SDA_TPSMP_HDATA21 0x228 0x490 0x000 0x7 0x0 -#define MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x22C 0x494 0x000 0x0 0x0 -#define MX8MM_IOMUXC_I2C4_SCL_PWM2_OUT 0x22C 0x494 0x000 0x1 0x0 -#define MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x22C 0x494 0x524 0x12 0x0 -#define MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x22C 0x494 0x000 0x5 0x0 -#define MX8MM_IOMUXC_I2C4_SCL_TPSMP_HDATA22 0x22C 0x494 0x000 0x7 0x0 -#define MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x230 0x498 0x000 0x0 0x0 -#define MX8MM_IOMUXC_I2C4_SDA_PWM1_OUT 0x230 0x498 0x000 0x1 0x0 -#define MX8MM_IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x230 0x498 0x528 0x2 0x0 -#define MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x230 0x498 0x000 0x5 0x0 -#define MX8MM_IOMUXC_I2C4_SDA_TPSMP_HDATA23 0x230 0x498 0x000 0x7 0x0 -#define MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x234 0x49C 0x4F4 0x0 0x0 -#define MX8MM_IOMUXC_UART1_RXD_UART1_DTE_TX 0x234 0x49C 0x000 0x0 0x0 -#define MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x234 0x49C 0x000 0x1 0x0 -#define MX8MM_IOMUXC_UART1_RXD_GPIO5_IO22 0x234 0x49C 0x000 0x5 0x0 -#define MX8MM_IOMUXC_UART1_RXD_TPSMP_HDATA24 0x234 0x49C 0x000 0x7 0x0 -#define MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x238 0x4A0 0x000 0x0 0x0 -#define MX8MM_IOMUXC_UART1_TXD_UART1_DTE_RX 0x238 0x4A0 0x4F4 0x0 0x0 -#define MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x238 0x4A0 0x000 0x1 0x0 -#define MX8MM_IOMUXC_UART1_TXD_GPIO5_IO23 0x238 0x4A0 0x000 0x5 0x0 -#define MX8MM_IOMUXC_UART1_TXD_TPSMP_HDATA25 0x238 0x4A0 0x000 0x7 0x0 -#define MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x23C 0x4A4 0x4FC 0x0 0x0 -#define MX8MM_IOMUXC_UART2_RXD_UART2_DTE_TX 0x23C 0x4A4 0x000 0x0 0x0 -#define MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x23C 0x4A4 0x000 0x1 0x0 -#define MX8MM_IOMUXC_UART2_RXD_GPIO5_IO24 0x23C 0x4A4 0x000 0x5 0x0 -#define MX8MM_IOMUXC_UART2_RXD_TPSMP_HDATA26 0x23C 0x4A4 0x000 0x7 0x0 -#define MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x240 0x4A8 0x000 0x0 0x0 -#define MX8MM_IOMUXC_UART2_TXD_UART2_DTE_RX 0x240 0x4A8 0x4FC 0x0 0x1 -#define MX8MM_IOMUXC_UART2_TXD_ECSPI3_SS0 0x240 0x4A8 0x000 0x1 0x0 -#define MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x240 0x4A8 0x000 0x5 0x0 -#define MX8MM_IOMUXC_UART2_TXD_TPSMP_HDATA27 0x240 0x4A8 0x000 0x7 0x0 -#define MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x244 0x4AC 0x504 0x0 0x2 -#define MX8MM_IOMUXC_UART3_RXD_UART3_DTE_TX 0x244 0x4AC 0x000 0x0 0x0 -#define MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x244 0x4AC 0x000 0x1 0x0 -#define MX8MM_IOMUXC_UART3_RXD_UART1_DTE_RTS_B 0x244 0x4AC 0x4F0 0x1 0x0 -#define MX8MM_IOMUXC_UART3_RXD_GPIO5_IO26 0x244 0x4AC 0x000 0x5 0x0 -#define MX8MM_IOMUXC_UART3_RXD_TPSMP_HDATA28 0x244 0x4AC 0x000 0x7 0x0 -#define MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x248 0x4B0 0x000 0x0 0x0 -#define MX8MM_IOMUXC_UART3_TXD_UART3_DTE_RX 0x248 0x4B0 0x504 0x0 0x3 -#define MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x248 0x4B0 0x4F0 0x1 0x1 -#define MX8MM_IOMUXC_UART3_TXD_UART1_DTE_CTS_B 0x248 0x4B0 0x000 0x1 0x0 -#define MX8MM_IOMUXC_UART3_TXD_GPIO5_IO27 0x248 0x4B0 0x000 0x5 0x0 -#define MX8MM_IOMUXC_UART3_TXD_TPSMP_HDATA29 0x248 0x4B0 0x000 0x7 0x0 -#define MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x24C 0x4B4 0x50C 0x0 0x2 -#define MX8MM_IOMUXC_UART4_RXD_UART4_DTE_TX 0x24C 0x4B4 0x000 0x0 0x0 -#define MX8MM_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x24C 0x4B4 0x000 0x1 0x0 -#define MX8MM_IOMUXC_UART4_RXD_UART2_DTE_RTS_B 0x24C 0x4B4 0x4F8 0x1 0x0 -#define MX8MM_IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x24C 0x4B4 0x524 0x2 0x1 -#define MX8MM_IOMUXC_UART4_RXD_GPIO5_IO28 0x24C 0x4B4 0x000 0x5 0x0 -#define MX8MM_IOMUXC_UART4_RXD_TPSMP_HDATA30 0x24C 0x4B4 0x000 0x7 0x0 -#define MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x250 0x4B8 0x000 0x0 0x0 -#define MX8MM_IOMUXC_UART4_TXD_UART4_DTE_RX 0x250 0x4B8 0x50C 0x0 0x3 -#define MX8MM_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x250 0x4B8 0x4F8 0x1 0x1 -#define MX8MM_IOMUXC_UART4_TXD_UART2_DTE_CTS_B 0x250 0x4B8 0x000 0x1 0x0 -#define MX8MM_IOMUXC_UART4_TXD_PCIE2_CLKREQ_B 0x250 0x4B8 0x528 0x2 0x1 -#define MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29 0x250 0x4B8 0x000 0x5 0x0 -#define MX8MM_IOMUXC_UART4_TXD_TPSMP_HDATA31 0x250 0x4B8 0x000 0x7 0x0 - -#endif /* __DTS_IMX8MM_PINFUNC_H */ diff --git a/sys/gnu/dts/arm64/freescale/imx8mm.dtsi b/sys/gnu/dts/arm64/freescale/imx8mm.dtsi deleted file mode 100644 index 1e5e11592f7..00000000000 --- a/sys/gnu/dts/arm64/freescale/imx8mm.dtsi +++ /dev/null @@ -1,903 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2019 NXP - */ - -#include -#include -#include -#include -#include - -#include "imx8mm-pinfunc.h" - -/ { - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - ethernet0 = &fec1; - i2c0 = &i2c1; - i2c1 = &i2c2; - i2c2 = &i2c3; - i2c3 = &i2c4; - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - serial3 = &uart4; - spi0 = &ecspi1; - spi1 = &ecspi2; - spi2 = &ecspi3; - mmc0 = &usdhc1; - mmc1 = &usdhc2; - mmc2 = &usdhc3; - gpio0 = &gpio1; - gpio1 = &gpio2; - gpio2 = &gpio3; - gpio3 = &gpio4; - gpio4 = &gpio5; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - idle-states { - entry-method = "psci"; - - cpu_pd_wait: cpu-pd-wait { - compatible = "arm,idle-state"; - arm,psci-suspend-param = <0x0010033>; - local-timer-stop; - entry-latency-us = <1000>; - exit-latency-us = <700>; - min-residency-us = <2700>; - }; - }; - - A53_0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0>; - clock-latency = <61036>; /* two CLK32 periods */ - clocks = <&clk IMX8MM_CLK_ARM>; - enable-method = "psci"; - next-level-cache = <&A53_L2>; - operating-points-v2 = <&a53_opp_table>; - nvmem-cells = <&cpu_speed_grade>; - nvmem-cell-names = "speed_grade"; - cpu-idle-states = <&cpu_pd_wait>; - }; - - A53_1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x1>; - clock-latency = <61036>; /* two CLK32 periods */ - clocks = <&clk IMX8MM_CLK_ARM>; - enable-method = "psci"; - next-level-cache = <&A53_L2>; - operating-points-v2 = <&a53_opp_table>; - cpu-idle-states = <&cpu_pd_wait>; - }; - - A53_2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x2>; - clock-latency = <61036>; /* two CLK32 periods */ - clocks = <&clk IMX8MM_CLK_ARM>; - enable-method = "psci"; - next-level-cache = <&A53_L2>; - operating-points-v2 = <&a53_opp_table>; - cpu-idle-states = <&cpu_pd_wait>; - }; - - A53_3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x3>; - clock-latency = <61036>; /* two CLK32 periods */ - clocks = <&clk IMX8MM_CLK_ARM>; - enable-method = "psci"; - next-level-cache = <&A53_L2>; - operating-points-v2 = <&a53_opp_table>; - cpu-idle-states = <&cpu_pd_wait>; - }; - - A53_L2: l2-cache0 { - compatible = "cache"; - }; - }; - - a53_opp_table: opp-table { - compatible = "operating-points-v2"; - opp-shared; - - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <850000>; - opp-supported-hw = <0xe>, <0x7>; - clock-latency-ns = <150000>; - opp-suspend; - }; - - opp-1600000000 { - opp-hz = /bits/ 64 <1600000000>; - opp-microvolt = <900000>; - opp-supported-hw = <0xc>, <0x7>; - clock-latency-ns = <150000>; - opp-suspend; - }; - - opp-1800000000 { - opp-hz = /bits/ 64 <1800000000>; - opp-microvolt = <1000000>; - opp-supported-hw = <0x8>, <0x3>; - clock-latency-ns = <150000>; - opp-suspend; - }; - }; - - osc_32k: clock-osc-32k { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "osc_32k"; - }; - - osc_24m: clock-osc-24m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "osc_24m"; - }; - - clk_ext1: clock-ext1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <133000000>; - clock-output-names = "clk_ext1"; - }; - - clk_ext2: clock-ext2 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <133000000>; - clock-output-names = "clk_ext2"; - }; - - clk_ext3: clock-ext3 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <133000000>; - clock-output-names = "clk_ext3"; - }; - - clk_ext4: clock-ext4 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency= <133000000>; - clock-output-names = "clk_ext4"; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = ; - interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , /* Physical Secure */ - , /* Physical Non-Secure */ - , /* Virtual */ - ; /* Hypervisor */ - clock-frequency = <8000000>; - arm,no-tick-in-suspend; - }; - - usbphynop1: usbphynop1 { - compatible = "usb-nop-xceiv"; - clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; - assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; - assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>; - clock-names = "main_clk"; - }; - - usbphynop2: usbphynop2 { - compatible = "usb-nop-xceiv"; - clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; - assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; - assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>; - clock-names = "main_clk"; - }; - - soc@0 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x0 0x3e000000>; - - aips1: bus@30000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x30000000 0x30000000 0x400000>; - - sai1: sai@30010000 { - compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; - reg = <0x30010000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MM_CLK_SAI1_IPG>, - <&clk IMX8MM_CLK_SAI1_ROOT>, - <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - sai2: sai@30020000 { - compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; - reg = <0x30020000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MM_CLK_SAI2_IPG>, - <&clk IMX8MM_CLK_SAI2_ROOT>, - <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - sai3: sai@30030000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; - reg = <0x30030000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MM_CLK_SAI3_IPG>, - <&clk IMX8MM_CLK_SAI3_ROOT>, - <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - sai5: sai@30050000 { - compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; - reg = <0x30050000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MM_CLK_SAI5_IPG>, - <&clk IMX8MM_CLK_SAI5_ROOT>, - <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - sai6: sai@30060000 { - compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; - reg = <0x30060000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MM_CLK_SAI6_IPG>, - <&clk IMX8MM_CLK_SAI6_ROOT>, - <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - gpio1: gpio@30200000 { - compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; - reg = <0x30200000 0x10000>; - interrupts = , - ; - clocks = <&clk IMX8MM_CLK_GPIO1_ROOT>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 10 30>; - }; - - gpio2: gpio@30210000 { - compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; - reg = <0x30210000 0x10000>; - interrupts = , - ; - clocks = <&clk IMX8MM_CLK_GPIO2_ROOT>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 40 21>; - }; - - gpio3: gpio@30220000 { - compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; - reg = <0x30220000 0x10000>; - interrupts = , - ; - clocks = <&clk IMX8MM_CLK_GPIO3_ROOT>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 61 26>; - }; - - gpio4: gpio@30230000 { - compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; - reg = <0x30230000 0x10000>; - interrupts = , - ; - clocks = <&clk IMX8MM_CLK_GPIO4_ROOT>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 87 32>; - }; - - gpio5: gpio@30240000 { - compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; - reg = <0x30240000 0x10000>; - interrupts = , - ; - clocks = <&clk IMX8MM_CLK_GPIO5_ROOT>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 119 30>; - }; - - wdog1: watchdog@30280000 { - compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt"; - reg = <0x30280000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MM_CLK_WDOG1_ROOT>; - status = "disabled"; - }; - - wdog2: watchdog@30290000 { - compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt"; - reg = <0x30290000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MM_CLK_WDOG2_ROOT>; - status = "disabled"; - }; - - wdog3: watchdog@302a0000 { - compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt"; - reg = <0x302a0000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MM_CLK_WDOG3_ROOT>; - status = "disabled"; - }; - - sdma2: dma-controller@302c0000 { - compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma"; - reg = <0x302c0000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MM_CLK_SDMA2_ROOT>, - <&clk IMX8MM_CLK_SDMA2_ROOT>; - clock-names = "ipg", "ahb"; - #dma-cells = <3>; - fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; - }; - - sdma3: dma-controller@302b0000 { - compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma"; - reg = <0x302b0000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MM_CLK_SDMA3_ROOT>, - <&clk IMX8MM_CLK_SDMA3_ROOT>; - clock-names = "ipg", "ahb"; - #dma-cells = <3>; - fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; - }; - - iomuxc: pinctrl@30330000 { - compatible = "fsl,imx8mm-iomuxc"; - reg = <0x30330000 0x10000>; - }; - - gpr: iomuxc-gpr@30340000 { - compatible = "fsl,imx8mm-iomuxc-gpr", "syscon"; - reg = <0x30340000 0x10000>; - }; - - ocotp: ocotp-ctrl@30350000 { - compatible = "fsl,imx8mm-ocotp", "syscon"; - reg = <0x30350000 0x10000>; - clocks = <&clk IMX8MM_CLK_OCOTP_ROOT>; - /* For nvmem subnodes */ - #address-cells = <1>; - #size-cells = <1>; - - cpu_speed_grade: speed-grade@10 { - reg = <0x10 4>; - }; - }; - - anatop: anatop@30360000 { - compatible = "fsl,imx8mm-anatop", "syscon"; - reg = <0x30360000 0x10000>; - }; - - snvs: snvs@30370000 { - compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd"; - reg = <0x30370000 0x10000>; - - snvs_rtc: snvs-rtc-lp { - compatible = "fsl,sec-v4.0-mon-rtc-lp"; - regmap = <&snvs>; - offset = <0x34>; - interrupts = , - ; - clocks = <&clk IMX8MM_CLK_SNVS_ROOT>; - clock-names = "snvs-rtc"; - }; - - snvs_pwrkey: snvs-powerkey { - compatible = "fsl,sec-v4.0-pwrkey"; - regmap = <&snvs>; - interrupts = ; - linux,keycode = ; - wakeup-source; - status = "disabled"; - }; - }; - - clk: clock-controller@30380000 { - compatible = "fsl,imx8mm-ccm"; - reg = <0x30380000 0x10000>; - #clock-cells = <1>; - clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, - <&clk_ext3>, <&clk_ext4>; - clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", - "clk_ext3", "clk_ext4"; - assigned-clocks = <&clk IMX8MM_CLK_NOC>, - <&clk IMX8MM_CLK_AUDIO_AHB>, - <&clk IMX8MM_CLK_IPG_AUDIO_ROOT>, - <&clk IMX8MM_SYS_PLL3>, - <&clk IMX8MM_VIDEO_PLL1>, - <&clk IMX8MM_AUDIO_PLL1>, - <&clk IMX8MM_AUDIO_PLL2>; - assigned-clock-parents = <&clk IMX8MM_SYS_PLL3_OUT>, - <&clk IMX8MM_SYS_PLL1_800M>; - assigned-clock-rates = <0>, - <400000000>, - <400000000>, - <750000000>, - <594000000>, - <393216000>, - <361267200>; - }; - - src: reset-controller@30390000 { - compatible = "fsl,imx8mm-src", "fsl,imx8mq-src", "syscon"; - reg = <0x30390000 0x10000>; - interrupts = ; - #reset-cells = <1>; - }; - }; - - aips2: bus@30400000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x30400000 0x30400000 0x400000>; - - pwm1: pwm@30660000 { - compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm"; - reg = <0x30660000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MM_CLK_PWM1_ROOT>, - <&clk IMX8MM_CLK_PWM1_ROOT>; - clock-names = "ipg", "per"; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm2: pwm@30670000 { - compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm"; - reg = <0x30670000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MM_CLK_PWM2_ROOT>, - <&clk IMX8MM_CLK_PWM2_ROOT>; - clock-names = "ipg", "per"; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm3: pwm@30680000 { - compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm"; - reg = <0x30680000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MM_CLK_PWM3_ROOT>, - <&clk IMX8MM_CLK_PWM3_ROOT>; - clock-names = "ipg", "per"; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm4: pwm@30690000 { - compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm"; - reg = <0x30690000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MM_CLK_PWM4_ROOT>, - <&clk IMX8MM_CLK_PWM4_ROOT>; - clock-names = "ipg", "per"; - #pwm-cells = <2>; - status = "disabled"; - }; - - system_counter: timer@306a0000 { - compatible = "nxp,sysctr-timer"; - reg = <0x306a0000 0x20000>; - interrupts = ; - clocks = <&osc_24m>; - clock-names = "per"; - }; - }; - - aips3: bus@30800000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x30800000 0x30800000 0x400000>; - - ecspi1: spi@30820000 { - compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x30820000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MM_CLK_ECSPI1_ROOT>, - <&clk IMX8MM_CLK_ECSPI1_ROOT>; - clock-names = "ipg", "per"; - dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - ecspi2: spi@30830000 { - compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x30830000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MM_CLK_ECSPI2_ROOT>, - <&clk IMX8MM_CLK_ECSPI2_ROOT>; - clock-names = "ipg", "per"; - dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - ecspi3: spi@30840000 { - compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x30840000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MM_CLK_ECSPI3_ROOT>, - <&clk IMX8MM_CLK_ECSPI3_ROOT>; - clock-names = "ipg", "per"; - dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart1: serial@30860000 { - compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart"; - reg = <0x30860000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MM_CLK_UART1_ROOT>, - <&clk IMX8MM_CLK_UART1_ROOT>; - clock-names = "ipg", "per"; - dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart3: serial@30880000 { - compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart"; - reg = <0x30880000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MM_CLK_UART3_ROOT>, - <&clk IMX8MM_CLK_UART3_ROOT>; - clock-names = "ipg", "per"; - dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart2: serial@30890000 { - compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart"; - reg = <0x30890000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MM_CLK_UART2_ROOT>, - <&clk IMX8MM_CLK_UART2_ROOT>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - crypto: crypto@30900000 { - compatible = "fsl,sec-v4.0"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x30900000 0x40000>; - ranges = <0 0x30900000 0x40000>; - interrupts = ; - clocks = <&clk IMX8MM_CLK_AHB>, - <&clk IMX8MM_CLK_IPG_ROOT>; - clock-names = "aclk", "ipg"; - - sec_jr0: jr@1000 { - compatible = "fsl,sec-v4.0-job-ring"; - reg = <0x1000 0x1000>; - interrupts = ; - }; - - sec_jr1: jr@2000 { - compatible = "fsl,sec-v4.0-job-ring"; - reg = <0x2000 0x1000>; - interrupts = ; - }; - - sec_jr2: jr@3000 { - compatible = "fsl,sec-v4.0-job-ring"; - reg = <0x3000 0x1000>; - interrupts = ; - }; - }; - - i2c1: i2c@30a20000 { - compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x30a20000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MM_CLK_I2C1_ROOT>; - status = "disabled"; - }; - - i2c2: i2c@30a30000 { - compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x30a30000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MM_CLK_I2C2_ROOT>; - status = "disabled"; - }; - - i2c3: i2c@30a40000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c"; - reg = <0x30a40000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MM_CLK_I2C3_ROOT>; - status = "disabled"; - }; - - i2c4: i2c@30a50000 { - compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x30a50000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MM_CLK_I2C4_ROOT>; - status = "disabled"; - }; - - uart4: serial@30a60000 { - compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart"; - reg = <0x30a60000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MM_CLK_UART4_ROOT>, - <&clk IMX8MM_CLK_UART4_ROOT>; - clock-names = "ipg", "per"; - dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - usdhc1: mmc@30b40000 { - compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; - reg = <0x30b40000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MM_CLK_IPG_ROOT>, - <&clk IMX8MM_CLK_NAND_USDHC_BUS>, - <&clk IMX8MM_CLK_USDHC1_ROOT>; - clock-names = "ipg", "ahb", "per"; - fsl,tuning-start-tap = <20>; - fsl,tuning-step= <2>; - bus-width = <4>; - status = "disabled"; - }; - - usdhc2: mmc@30b50000 { - compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; - reg = <0x30b50000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MM_CLK_IPG_ROOT>, - <&clk IMX8MM_CLK_NAND_USDHC_BUS>, - <&clk IMX8MM_CLK_USDHC2_ROOT>; - clock-names = "ipg", "ahb", "per"; - fsl,tuning-start-tap = <20>; - fsl,tuning-step= <2>; - bus-width = <4>; - status = "disabled"; - }; - - usdhc3: mmc@30b60000 { - compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; - reg = <0x30b60000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MM_CLK_IPG_ROOT>, - <&clk IMX8MM_CLK_NAND_USDHC_BUS>, - <&clk IMX8MM_CLK_USDHC3_ROOT>; - clock-names = "ipg", "ahb", "per"; - fsl,tuning-start-tap = <20>; - fsl,tuning-step= <2>; - bus-width = <4>; - status = "disabled"; - }; - - sdma1: dma-controller@30bd0000 { - compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma"; - reg = <0x30bd0000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MM_CLK_SDMA1_ROOT>, - <&clk IMX8MM_CLK_AHB>; - clock-names = "ipg", "ahb"; - #dma-cells = <3>; - fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; - }; - - fec1: ethernet@30be0000 { - compatible = "fsl,imx8mm-fec", "fsl,imx6sx-fec"; - reg = <0x30be0000 0x10000>; - interrupts = , - , - ; - clocks = <&clk IMX8MM_CLK_ENET1_ROOT>, - <&clk IMX8MM_CLK_ENET1_ROOT>, - <&clk IMX8MM_CLK_ENET_TIMER>, - <&clk IMX8MM_CLK_ENET_REF>, - <&clk IMX8MM_CLK_ENET_PHY_REF>; - clock-names = "ipg", "ahb", "ptp", - "enet_clk_ref", "enet_out"; - assigned-clocks = <&clk IMX8MM_CLK_ENET_AXI>, - <&clk IMX8MM_CLK_ENET_TIMER>, - <&clk IMX8MM_CLK_ENET_REF>, - <&clk IMX8MM_CLK_ENET_TIMER>; - assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>, - <&clk IMX8MM_SYS_PLL2_100M>, - <&clk IMX8MM_SYS_PLL2_125M>; - assigned-clock-rates = <0>, <0>, <125000000>, <100000000>; - fsl,num-tx-queues = <3>; - fsl,num-rx-queues = <3>; - status = "disabled"; - }; - - }; - - aips4: bus@32c00000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x32c00000 0x32c00000 0x400000>; - - usbotg1: usb@32e40000 { - compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb"; - reg = <0x32e40000 0x200>; - interrupts = ; - clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>; - clock-names = "usb1_ctrl_root_clk"; - assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>; - assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>; - fsl,usbphy = <&usbphynop1>; - fsl,usbmisc = <&usbmisc1 0>; - status = "disabled"; - }; - - usbmisc1: usbmisc@32e40200 { - compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc"; - #index-cells = <1>; - reg = <0x32e40200 0x200>; - }; - - usbotg2: usb@32e50000 { - compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb"; - reg = <0x32e50000 0x200>; - interrupts = ; - clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>; - clock-names = "usb1_ctrl_root_clk"; - assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>; - assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>; - fsl,usbphy = <&usbphynop2>; - fsl,usbmisc = <&usbmisc2 0>; - status = "disabled"; - }; - - usbmisc2: usbmisc@32e50200 { - compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc"; - #index-cells = <1>; - reg = <0x32e50200 0x200>; - }; - - }; - - dma_apbh: dma-controller@33000000 { - compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh"; - reg = <0x33000000 0x2000>; - interrupts = , - , - , - ; - interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; - #dma-cells = <1>; - dma-channels = <4>; - clocks = <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; - }; - - gpmi: nand-controller@33002000{ - compatible = "fsl,imx8mm-gpmi-nand", "fsl,imx7d-gpmi-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x33002000 0x2000>, <0x33004000 0x4000>; - reg-names = "gpmi-nand", "bch"; - interrupts = ; - interrupt-names = "bch"; - clocks = <&clk IMX8MM_CLK_NAND_ROOT>, - <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; - clock-names = "gpmi_io", "gpmi_bch_apb"; - dmas = <&dma_apbh 0>; - dma-names = "rx-tx"; - status = "disabled"; - }; - - gic: interrupt-controller@38800000 { - compatible = "arm,gic-v3"; - reg = <0x38800000 0x10000>, /* GIC Dist */ - <0x38880000 0xc0000>; /* GICR (RD_base + SGI_base) */ - #interrupt-cells = <3>; - interrupt-controller; - interrupts = ; - }; - - ddrc: memory-controller@3d400000 { - compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc"; - reg = <0x3d400000 0x400000>; - clock-names = "core", "pll", "alt", "apb"; - clocks = <&clk IMX8MM_CLK_DRAM_CORE>, - <&clk IMX8MM_DRAM_PLL>, - <&clk IMX8MM_CLK_DRAM_ALT>, - <&clk IMX8MM_CLK_DRAM_APB>; - }; - - ddr-pmu@3d800000 { - compatible = "fsl,imx8mm-ddr-pmu", "fsl,imx8m-ddr-pmu"; - reg = <0x3d800000 0x400000>; - interrupt-parent = <&gic>; - interrupts = ; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/freescale/imx8mn-ddr4-evk.dts b/sys/gnu/dts/arm64/freescale/imx8mn-ddr4-evk.dts deleted file mode 100644 index 2497eebb573..00000000000 --- a/sys/gnu/dts/arm64/freescale/imx8mn-ddr4-evk.dts +++ /dev/null @@ -1,151 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2019 NXP - */ - -/dts-v1/; - -#include "imx8mn.dtsi" -#include "imx8mn-evk.dtsi" - -/ { - model = "NXP i.MX8MNano DDR4 EVK board"; - compatible = "fsl,imx8mn-ddr4-evk", "fsl,imx8mn"; -}; - -&A53_0 { - cpu-supply = <&buck2_reg>; -}; - -&ddrc { - operating-points-v2 = <&ddrc_opp_table>; - - ddrc_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-25M { - opp-hz = /bits/ 64 <25000000>; - }; - - opp-100M { - opp-hz = /bits/ 64 <100000000>; - }; - - opp-600M { - opp-hz = /bits/ 64 <600000000>; - }; - }; -}; - -&i2c1 { - pmic@4b { - compatible = "rohm,bd71847"; - reg = <0x4b>; - pinctrl-0 = <&pinctrl_pmic>; - interrupt-parent = <&gpio1>; - interrupts = <3 GPIO_ACTIVE_LOW>; - rohm,reset-snvs-powered; - - regulators { - buck1_reg: BUCK1 { - regulator-name = "BUCK1"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <1250>; - }; - - buck2_reg: BUCK2 { - regulator-name = "BUCK2"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <1250>; - }; - - buck3_reg: BUCK3 { - // BUCK5 in datasheet - regulator-name = "BUCK3"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1350000>; - }; - - buck4_reg: BUCK4 { - // BUCK6 in datasheet - regulator-name = "BUCK4"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - buck5_reg: BUCK5 { - // BUCK7 in datasheet - regulator-name = "BUCK5"; - regulator-min-microvolt = <1605000>; - regulator-max-microvolt = <1995000>; - regulator-boot-on; - regulator-always-on; - }; - - buck6_reg: BUCK6 { - // BUCK8 in datasheet - regulator-name = "BUCK6"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1_reg: LDO1 { - regulator-name = "LDO1"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo2_reg: LDO2 { - regulator-name = "LDO2"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo3_reg: LDO3 { - regulator-name = "LDO3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo4_reg: LDO4 { - regulator-name = "LDO4"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo6_reg: LDO6 { - regulator-name = "LDO6"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; -}; - -&iomuxc { - pinctrl_pmic: pmicirq { - fsl,pins = < - MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 - >; - }; -}; diff --git a/sys/gnu/dts/arm64/freescale/imx8mn-evk.dts b/sys/gnu/dts/arm64/freescale/imx8mn-evk.dts deleted file mode 100644 index 61f35195861..00000000000 --- a/sys/gnu/dts/arm64/freescale/imx8mn-evk.dts +++ /dev/null @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2019 NXP - */ - -/dts-v1/; - -#include "imx8mn.dtsi" -#include "imx8mn-evk.dtsi" - -/ { - model = "NXP i.MX8MNano EVK board"; - compatible = "fsl,imx8mn-evk", "fsl,imx8mn"; -}; - -&A53_0 { - /delete-property/operating-points-v2; -}; - -&A53_1 { - /delete-property/operating-points-v2; -}; - -&A53_2 { - /delete-property/operating-points-v2; -}; - -&A53_3 { - /delete-property/operating-points-v2; -}; diff --git a/sys/gnu/dts/arm64/freescale/imx8mn-evk.dtsi b/sys/gnu/dts/arm64/freescale/imx8mn-evk.dtsi deleted file mode 100644 index 0d2ec4a2c7f..00000000000 --- a/sys/gnu/dts/arm64/freescale/imx8mn-evk.dtsi +++ /dev/null @@ -1,319 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2019 NXP - */ - -#include -#include "imx8mn.dtsi" - -/ { - chosen { - stdout-path = &uart2; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_led>; - - status { - label = "yellow:status"; - gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x0 0x40000000 0 0x80000000>; - }; - - reg_usdhc2_vmmc: regulator-usdhc2 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; - regulator-name = "VSD_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy0>; - fsl,magic-packet; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - }; - }; -}; - -&i2c1 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; -}; - -&i2c2 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - ptn5110: tcpc@50 { - compatible = "nxp,ptn5110"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_typec1>; - reg = <0x50>; - interrupt-parent = <&gpio2>; - interrupts = <11 IRQ_TYPE_LEVEL_LOW>; - status = "okay"; - - port { - typec1_dr_sw: endpoint { - remote-endpoint = <&usb1_drd_sw>; - }; - }; - - typec1_con: connector { - compatible = "usb-c-connector"; - label = "USB-C"; - power-role = "dual"; - data-role = "dual"; - try-power-role = "sink"; - source-pdos = ; - sink-pdos = ; - op-sink-microwatt = <15000000>; - self-powered; - }; - }; -}; - -&snvs_pwrkey { - status = "okay"; -}; - -&uart2 { /* console */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&usbotg1 { - dr_mode = "otg"; - hnp-disable; - srp-disable; - adp-disable; - usb-role-switch; - status = "okay"; - - port { - usb1_drd_sw: endpoint { - remote-endpoint = <&typec1_dr_sw>; - }; - }; -}; - -&usdhc2 { - assigned-clocks = <&clk IMX8MN_CLK_USDHC2>; - assigned-clock-rates = <200000000>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; - cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; - bus-width = <4>; - vmmc-supply = <®_usdhc2_vmmc>; - status = "okay"; -}; - -&usdhc3 { - assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>; - assigned-clock-rates = <400000000>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - - pinctrl_fec1: fec1grp { - fsl,pins = < - MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3 - MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 - MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f - MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f - MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f - MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f - MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 - MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 - MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 - MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 - MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f - MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 - MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 - MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f - MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 - >; - }; - - pinctrl_gpio_led: gpioledgrp { - fsl,pins = < - MX8MN_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 - MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 - MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 - >; - }; - - pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc { - fsl,pins = < - MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 - >; - }; - - pinctrl_typec1: typec1grp { - fsl,pins = < - MX8MN_IOMUXC_SD1_STROBE_GPIO2_IO11 0x159 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 - MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 - >; - }; - - pinctrl_usdhc2_gpio: usdhc2grpgpio { - fsl,pins = < - MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 - MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 - MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 - MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 - MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 - MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 - MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2grp100mhz { - fsl,pins = < - MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 - MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 - MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 - MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 - MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 - MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 - MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2grp200mhz { - fsl,pins = < - MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 - MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 - MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 - MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 - MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 - MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 - MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000190 - MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 - MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 - MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 - MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 - MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 - MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 - MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 - MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 - MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 - MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3grp100mhz { - fsl,pins = < - MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000194 - MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 - MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 - MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 - MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 - MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 - MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 - MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 - MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 - MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 - MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3grp200mhz { - fsl,pins = < - MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000196 - MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 - MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 - MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 - MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 - MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 - MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 - MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 - MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 - MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 - MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 - >; - }; -}; diff --git a/sys/gnu/dts/arm64/freescale/imx8mn-pinfunc.h b/sys/gnu/dts/arm64/freescale/imx8mn-pinfunc.h deleted file mode 100644 index faf1e69e742..00000000000 --- a/sys/gnu/dts/arm64/freescale/imx8mn-pinfunc.h +++ /dev/null @@ -1,646 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2018-2019 NXP - */ - -#ifndef __DTS_IMX8MN_PINFUNC_H -#define __DTS_IMX8MN_PINFUNC_H - -/* - * The pin function ID is a tuple of - * - */ - -#define MX8MN_IOMUXC_BOOT_MODE2_CCMSRCGPCMIX_BOOT_MODE2 0x020 0x25C 0x000 0x0 0x0 -#define MX8MN_IOMUXC_BOOT_MODE2_I2C1_SCL 0x020 0x25C 0x55C 0x1 0x3 -#define MX8MN_IOMUXC_BOOT_MODE3_CCMSRCGPCMIX_BOOT_MODE3 0x024 0x260 0x000 0x0 0x0 -#define MX8MN_IOMUXC_BOOT_MODE3_I2C1_SDA 0x024 0x260 0x56C 0x1 0x3 -#define MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0 -#define MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x000 0x1 0x0 -#define MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0 -#define MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0 -#define MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0 -#define MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0 -#define MX8MN_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x000 0x5 0x0 -#define MX8MN_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0x0 -#define MX8MN_IOMUXC_GPIO1_IO02_GPIO1_IO2 0x030 0x298 0x000 0x0 0x0 -#define MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x030 0x298 0x000 0x1 0x0 -#define MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x030 0x298 0x000 0x5 0x0 -#define MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x034 0x29C 0x000 0x0 0x0 -#define MX8MN_IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x034 0x29C 0x000 0x1 0x0 -#define MX8MN_IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x034 0x29C 0x000 0x5 0x0 -#define MX8MN_IOMUXC_GPIO1_IO03_ANAMIX_XTAL_OK 0x034 0x29C 0x000 0x6 0x0 -#define MX8MN_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x038 0x2A0 0x000 0x0 0x0 -#define MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x038 0x2A0 0x000 0x1 0x0 -#define MX8MN_IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x038 0x2A0 0x000 0x5 0x0 -#define MX8MN_IOMUXC_GPIO1_IO04_ANAMIX_XTAL_OK_LV 0x038 0x2A0 0x000 0x6 0x0 -#define MX8MN_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x03C 0x2A4 0x000 0x0 0x0 -#define MX8MN_IOMUXC_GPIO1_IO05_M4_NMI 0x03C 0x2A4 0x000 0x1 0x0 -#define MX8MN_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_PMIC_READY 0x03C 0x2A4 0x4BC 0x5 0x0 -#define MX8MN_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_INT_BOOT 0x03C 0x2A4 0x000 0x6 0x0 -#define MX8MN_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x040 0x2A8 0x000 0x0 0x0 -#define MX8MN_IOMUXC_GPIO1_IO06_ENET1_MDC 0x040 0x2A8 0x000 0x1 0x0 -#define MX8MN_IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x040 0x2A8 0x000 0x5 0x0 -#define MX8MN_IOMUXC_GPIO1_IO06_CCMSRCGPCMIX_EXT_CLK3 0x040 0x2A8 0x000 0x6 0x0 -#define MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x044 0x2AC 0x000 0x0 0x0 -#define MX8MN_IOMUXC_GPIO1_IO07_ENET1_MDIO 0x044 0x2AC 0x4C0 0x1 0x0 -#define MX8MN_IOMUXC_GPIO1_IO07_USDHC1_WP 0x044 0x2AC 0x000 0x5 0x0 -#define MX8MN_IOMUXC_GPIO1_IO07_CCMSRCGPCMIX_EXT_CLK4 0x044 0x2AC 0x000 0x6 0x0 -#define MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x048 0x2B0 0x000 0x0 0x0 -#define MX8MN_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x048 0x2B0 0x000 0x1 0x0 -#define MX8MN_IOMUXC_GPIO1_IO08_PWM1_OUT 0x048 0x2B0 0x000 0x2 0x0 -#define MX8MN_IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x048 0x2B0 0x000 0x5 0x0 -#define MX8MN_IOMUXC_GPIO1_IO08_CCMSRCGPCMIX_WAIT 0x048 0x2B0 0x000 0x6 0x0 -#define MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x04C 0x2B4 0x000 0x0 0x0 -#define MX8MN_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x04C 0x2B4 0x000 0x1 0x0 -#define MX8MN_IOMUXC_GPIO1_IO09_PWM2_OUT 0x04C 0x2B4 0x000 0x2 0x0 -#define MX8MN_IOMUXC_GPIO1_IO09_USDHC3_RESET_B 0x04C 0x2B4 0x000 0x4 0x0 -#define MX8MN_IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x04C 0x2B4 0x000 0x5 0x0 -#define MX8MN_IOMUXC_GPIO1_IO09_CCMSRCGPCMIX_STOP 0x04C 0x2B4 0x000 0x6 0x0 -#define MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x050 0x2B8 0x000 0x0 0x0 -#define MX8MN_IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x050 0x2B8 0x000 0x1 0x0 -#define MX8MN_IOMUXC_GPIO1_IO10_PWM3_OUT 0x050 0x2B8 0x000 0x2 0x0 -#define MX8MN_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x054 0x2BC 0x000 0x0 0x0 -#define MX8MN_IOMUXC_GPIO1_IO11_PWM2_OUT 0x054 0x2BC 0x000 0x1 0x0 -#define MX8MN_IOMUXC_GPIO1_IO11_USDHC3_VSELECT 0x054 0x2BC 0x000 0x4 0x0 -#define MX8MN_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_PMIC_READY 0x054 0x2BC 0x4BC 0x5 0x1 -#define MX8MN_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_OUT0 0x054 0x2BC 0x000 0x6 0x0 -#define MX8MN_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x058 0x2C0 0x000 0x0 0x0 -#define MX8MN_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x058 0x2C0 0x000 0x1 0x0 -#define MX8MN_IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x058 0x2C0 0x000 0x5 0x0 -#define MX8MN_IOMUXC_GPIO1_IO12_CCMSRCGPCMIX_OUT1 0x058 0x2C0 0x000 0x6 0x0 -#define MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x05C 0x2C4 0x000 0x0 0x0 -#define MX8MN_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x05C 0x2C4 0x000 0x1 0x0 -#define MX8MN_IOMUXC_GPIO1_IO13_PWM2_OUT 0x05C 0x2C4 0x000 0x5 0x0 -#define MX8MN_IOMUXC_GPIO1_IO13_CCMSRCGPCMIX_OUT2 0x05C 0x2C4 0x000 0x6 0x0 -#define MX8MN_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x060 0x2C8 0x000 0x0 0x0 -#define MX8MN_IOMUXC_GPIO1_IO14_USDHC3_CD_B 0x060 0x2C8 0x598 0x4 0x2 -#define MX8MN_IOMUXC_GPIO1_IO14_PWM3_OUT 0x060 0x2C8 0x000 0x5 0x0 -#define MX8MN_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x060 0x2C8 0x000 0x6 0x0 -#define MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x064 0x2CC 0x000 0x0 0x0 -#define MX8MN_IOMUXC_GPIO1_IO15_USDHC3_WP 0x064 0x2CC 0x5B8 0x4 0x2 -#define MX8MN_IOMUXC_GPIO1_IO15_PWM4_OUT 0x064 0x2CC 0x000 0x5 0x0 -#define MX8MN_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x064 0x2CC 0x000 0x6 0x0 -#define MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x068 0x2D0 0x000 0x0 0x0 -#define MX8MN_IOMUXC_ENET_MDC_SAI6_TX_DATA0 0x068 0x2D0 0x000 0x2 0x0 -#define MX8MN_IOMUXC_ENET_MDC_PDM_BIT_STREAM3 0x068 0x2D0 0x540 0x3 0x1 -#define MX8MN_IOMUXC_ENET_MDC_SPDIF1_OUT 0x068 0x2D0 0x000 0x4 0x0 -#define MX8MN_IOMUXC_ENET_MDC_GPIO1_IO16 0x068 0x2D0 0x000 0x5 0x0 -#define MX8MN_IOMUXC_ENET_MDC_USDHC3_STROBE 0x068 0x2D0 0x59C 0x6 0x1 -#define MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x06C 0x2D4 0x4C0 0x0 0x1 -#define MX8MN_IOMUXC_ENET_MDIO_SAI6_TX_SYNC 0x06C 0x2D4 0x000 0x2 0x0 -#define MX8MN_IOMUXC_ENET_MDIO_PDM_BIT_STREAM2 0x06C 0x2D4 0x53C 0x3 0x1 -#define MX8MN_IOMUXC_ENET_MDIO_SPDIF1_IN 0x06C 0x2D4 0x5CC 0x4 0x1 -#define MX8MN_IOMUXC_ENET_MDIO_GPIO1_IO17 0x06C 0x2D4 0x000 0x5 0x0 -#define MX8MN_IOMUXC_ENET_MDIO_USDHC3_DATA5 0x06C 0x2D4 0x550 0x6 0x1 -#define MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x070 0x2D8 0x000 0x0 0x0 -#define MX8MN_IOMUXC_ENET_TD3_SAI6_TX_BCLK 0x070 0x2D8 0x000 0x2 0x0 -#define MX8MN_IOMUXC_ENET_TD3_PDM_BIT_STREAM1 0x070 0x2D8 0x538 0x3 0x1 -#define MX8MN_IOMUXC_ENET_TD3_SPDIF1_EXT_CLK 0x070 0x2D8 0x568 0x4 0x1 -#define MX8MN_IOMUXC_ENET_TD3_GPIO1_IO18 0x070 0x2D8 0x000 0x5 0x0 -#define MX8MN_IOMUXC_ENET_TD3_USDHC3_DATA6 0x070 0x2D8 0x584 0x6 0x1 -#define MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x074 0x2DC 0x000 0x0 0x0 -#define MX8MN_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x074 0x2DC 0x5A4 0x1 0x0 -#define MX8MN_IOMUXC_ENET_TD2_CCMSRCGPCMIX_ENET_REF_CLK_ROOT 0x074 0x2DC 0x5A4 0x1 0x0 -#define MX8MN_IOMUXC_ENET_TD2_SAI6_RX_DATA0 0x074 0x2DC 0x000 0x2 0x0 -#define MX8MN_IOMUXC_ENET_TD2_PDM_BIT_STREAM3 0x074 0x2DC 0x540 0x3 0x2 -#define MX8MN_IOMUXC_ENET_TD2_GPIO1_IO19 0x074 0x2DC 0x000 0x5 0x0 -#define MX8MN_IOMUXC_ENET_TD2_USDHC3_DATA7 0x074 0x2DC 0x54C 0x6 0x1 -#define MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x078 0x2E0 0x000 0x0 0x0 -#define MX8MN_IOMUXC_ENET_TD1_SAI6_RX_SYNC 0x078 0x2E0 0x000 0x2 0x0 -#define MX8MN_IOMUXC_ENET_TD1_PDM_BIT_STREAM2 0x078 0x2E0 0x53C 0x3 0x2 -#define MX8MN_IOMUXC_ENET_TD1_GPIO1_IO20 0x078 0x2E0 0x000 0x5 0x0 -#define MX8MN_IOMUXC_ENET_TD1_USDHC3_CD_B 0x078 0x2E0 0x598 0x6 0x3 -#define MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x07C 0x2E4 0x000 0x0 0x0 -#define MX8MN_IOMUXC_ENET_TD0_SAI6_RX_BCLK 0x07C 0x2E4 0x000 0x2 0x0 -#define MX8MN_IOMUXC_ENET_TD0_PDM_BIT_STREAM1 0x07C 0x2E4 0x538 0x3 0x2 -#define MX8MN_IOMUXC_ENET_TD0_GPIO1_IO21 0x07C 0x2E4 0x000 0x5 0x0 -#define MX8MN_IOMUXC_ENET_TD0_USDHC3_WP 0x07C 0x2E4 0x5B8 0x6 0x3 -#define MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x080 0x2E8 0x000 0x0 0x0 -#define MX8MN_IOMUXC_ENET_TX_CTL_SAI6_MCLK 0x080 0x2E8 0x000 0x2 0x0 -#define MX8MN_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x080 0x2E8 0x000 0x5 0x0 -#define MX8MN_IOMUXC_ENET_TX_CTL_USDHC3_DATA0 0x080 0x2E8 0x5B4 0x6 0x1 -#define MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x084 0x2EC 0x000 0x0 0x0 -#define MX8MN_IOMUXC_ENET_TXC_ENET1_TX_ER 0x084 0x2EC 0x000 0x1 0x0 -#define MX8MN_IOMUXC_ENET_TXC_SAI7_TX_DATA0 0x084 0x2EC 0x000 0x2 0x0 -#define MX8MN_IOMUXC_ENET_TXC_GPIO1_IO23 0x084 0x2EC 0x000 0x5 0x0 -#define MX8MN_IOMUXC_ENET_TXC_USDHC3_DATA1 0x084 0x2EC 0x5B0 0x6 0x1 -#define MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x088 0x2F0 0x574 0x0 0x0 -#define MX8MN_IOMUXC_ENET_RX_CTL_SAI7_TX_SYNC 0x088 0x2F0 0x000 0x2 0x0 -#define MX8MN_IOMUXC_ENET_RX_CTL_PDM_BIT_STREAM3 0x088 0x2F0 0x540 0x3 0x3 -#define MX8MN_IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x088 0x2F0 0x000 0x5 0x0 -#define MX8MN_IOMUXC_ENET_RX_CTL_USDHC3_DATA2 0x088 0x2F0 0x5E4 0x6 0x1 -#define MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x08C 0x2F4 0x000 0x0 0x0 -#define MX8MN_IOMUXC_ENET_RXC_ENET1_RX_ER 0x08C 0x2F4 0x5C8 0x1 0x0 -#define MX8MN_IOMUXC_ENET_RXC_SAI7_TX_BCLK 0x08C 0x2F4 0x000 0x2 0x0 -#define MX8MN_IOMUXC_ENET_RXC_PDM_BIT_STREAM2 0x08C 0x2F4 0x53C 0x3 0x3 -#define MX8MN_IOMUXC_ENET_RXC_GPIO1_IO25 0x08C 0x2F4 0x000 0x5 0x0 -#define MX8MN_IOMUXC_ENET_RXC_USDHC3_DATA3 0x08C 0x2F4 0x5E0 0x6 0x1 -#define MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x090 0x2F8 0x57C 0x0 0x0 -#define MX8MN_IOMUXC_ENET_RD0_SAI7_RX_DATA0 0x090 0x2F8 0x000 0x2 0x0 -#define MX8MN_IOMUXC_ENET_RD0_PDM_BIT_STREAM1 0x090 0x2F8 0x538 0x3 0x3 -#define MX8MN_IOMUXC_ENET_RD0_GPIO1_IO26 0x090 0x2F8 0x000 0x5 0x0 -#define MX8MN_IOMUXC_ENET_RD0_USDHC3_DATA4 0x090 0x2F8 0x558 0x6 0x1 -#define MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x094 0x2FC 0x554 0x0 0x0 -#define MX8MN_IOMUXC_ENET_RD1_SAI7_RX_SYNC 0x094 0x2FC 0x000 0x2 0x0 -#define MX8MN_IOMUXC_ENET_RD1_PDM_BIT_STREAM0 0x094 0x2FC 0x534 0x3 0x1 -#define MX8MN_IOMUXC_ENET_RD1_GPIO1_IO27 0x094 0x2FC 0x000 0x5 0x0 -#define MX8MN_IOMUXC_ENET_RD1_USDHC3_RESET_B 0x094 0x2FC 0x000 0x6 0x0 -#define MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x098 0x300 0x000 0x0 0x0 -#define MX8MN_IOMUXC_ENET_RD2_SAI7_RX_BCLK 0x098 0x300 0x000 0x2 0x0 -#define MX8MN_IOMUXC_ENET_RD2_PDM_CLK 0x098 0x300 0x000 0x3 0x0 -#define MX8MN_IOMUXC_ENET_RD2_GPIO1_IO28 0x098 0x300 0x000 0x5 0x0 -#define MX8MN_IOMUXC_ENET_RD2_USDHC3_CLK 0x098 0x300 0x5A0 0x6 0x1 -#define MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x09C 0x304 0x000 0x0 0x0 -#define MX8MN_IOMUXC_ENET_RD3_SAI7_MCLK 0x09C 0x304 0x000 0x2 0x0 -#define MX8MN_IOMUXC_ENET_RD3_SPDIF1_IN 0x09C 0x304 0x5CC 0x3 0x5 -#define MX8MN_IOMUXC_ENET_RD3_GPIO1_IO29 0x09C 0x304 0x000 0x5 0x0 -#define MX8MN_IOMUXC_ENET_RD3_USDHC3_CMD 0x09C 0x304 0x5DC 0x6 0x1 -#define MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x0A0 0x308 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SD1_CLK_ENET1_MDC 0x0A0 0x308 0x000 0x1 0x0 -#define MX8MN_IOMUXC_SD1_CLK_UART1_DCE_TX 0x0A0 0x308 0x000 0x4 0x0 -#define MX8MN_IOMUXC_SD1_CLK_UART1_DTE_RX 0x0A0 0x308 0x4F4 0x4 0x4 -#define MX8MN_IOMUXC_SD1_CLK_GPIO2_IO0 0x0A0 0x308 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x0A4 0x30C 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SD1_CMD_ENET1_MDIO 0x0A4 0x30C 0x4C0 0x1 0x3 -#define MX8MN_IOMUXC_SD1_CMD_UART1_DCE_RX 0x0A4 0x30C 0x4F4 0x4 0x5 -#define MX8MN_IOMUXC_SD1_CMD_UART1_DTE_TX 0x0A4 0x30C 0x000 0x4 0x0 -#define MX8MN_IOMUXC_SD1_CMD_GPIO2_IO1 0x0A4 0x30C 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0A8 0x310 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SD1_DATA0_ENET1_RGMII_TD1 0x0A8 0x310 0x000 0x1 0x0 -#define MX8MN_IOMUXC_SD1_DATA0_UART1_DCE_RTS_B 0x0A8 0x310 0x4F0 0x4 0x4 -#define MX8MN_IOMUXC_SD1_DATA0_UART1_DTE_CTS_B 0x0A8 0x310 0x000 0x4 0x0 -#define MX8MN_IOMUXC_SD1_DATA0_GPIO2_IO2 0x0A8 0x310 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0AC 0x314 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SD1_DATA1_ENET1_RGMII_TD0 0x0AC 0x314 0x000 0x1 0x0 -#define MX8MN_IOMUXC_SD1_DATA1_UART1_DCE_CTS_B 0x0AC 0x314 0x000 0x4 0x0 -#define MX8MN_IOMUXC_SD1_DATA1_UART1_DTE_RTS_B 0x0AC 0x314 0x4F0 0x4 0x5 -#define MX8MN_IOMUXC_SD1_DATA1_GPIO2_IO3 0x0AC 0x314 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0B0 0x318 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SD1_DATA2_ENET1_RGMII_RD0 0x0B0 0x318 0x57C 0x1 0x1 -#define MX8MN_IOMUXC_SD1_DATA2_UART2_DCE_TX 0x0B0 0x318 0x000 0x4 0x0 -#define MX8MN_IOMUXC_SD1_DATA2_UART2_DTE_RX 0x0B0 0x318 0x4FC 0x4 0x4 -#define MX8MN_IOMUXC_SD1_DATA2_GPIO2_IO4 0x0B0 0x318 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x0B4 0x31C 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SD1_DATA3_ENET1_RGMII_RD1 0x0B4 0x31C 0x554 0x1 0x1 -#define MX8MN_IOMUXC_SD1_DATA3_UART2_DCE_RX 0x0B4 0x31C 0x4FC 0x4 0x5 -#define MX8MN_IOMUXC_SD1_DATA3_UART2_DTE_TX 0x0B4 0x31C 0x000 0x4 0x0 -#define MX8MN_IOMUXC_SD1_DATA3_GPIO2_IO5 0x0B4 0x31C 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x0B8 0x320 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SD1_DATA4_ENET1_RGMII_TX_CTL 0x0B8 0x320 0x000 0x1 0x0 -#define MX8MN_IOMUXC_SD1_DATA4_I2C1_SCL 0x0B8 0x320 0x55C 0x3 0x1 -#define MX8MN_IOMUXC_SD1_DATA4_UART2_DCE_RTS_B 0x0B8 0x320 0x4F8 0x4 0x4 -#define MX8MN_IOMUXC_SD1_DATA4_UART2_DTE_CTS_B 0x0B8 0x320 0x000 0x4 0x0 -#define MX8MN_IOMUXC_SD1_DATA4_GPIO2_IO6 0x0B8 0x320 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x0BC 0x324 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SD1_DATA5_ENET1_TX_ER 0x0BC 0x324 0x000 0x1 0x0 -#define MX8MN_IOMUXC_SD1_DATA5_I2C1_SDA 0x0BC 0x324 0x56C 0x3 0x1 -#define MX8MN_IOMUXC_SD1_DATA5_UART2_DCE_CTS_B 0x0BC 0x324 0x000 0x4 0x0 -#define MX8MN_IOMUXC_SD1_DATA5_UART2_DTE_RTS_B 0x0BC 0x324 0x4F8 0x4 0x5 -#define MX8MN_IOMUXC_SD1_DATA5_GPIO2_IO7 0x0BC 0x324 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x0C0 0x328 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SD1_DATA6_ENET1_RGMII_RX_CTL 0x0C0 0x328 0x574 0x1 0x1 -#define MX8MN_IOMUXC_SD1_DATA6_I2C2_SCL 0x0C0 0x328 0x5D0 0x3 0x1 -#define MX8MN_IOMUXC_SD1_DATA6_UART3_DCE_TX 0x0C0 0x328 0x000 0x4 0x0 -#define MX8MN_IOMUXC_SD1_DATA6_UART3_DTE_RX 0x0C0 0x328 0x504 0x4 0x4 -#define MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8 0x0C0 0x328 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x0C4 0x32C 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SD1_DATA7_ENET1_RX_ER 0x0C4 0x32C 0x5C8 0x1 0x1 -#define MX8MN_IOMUXC_SD1_DATA7_I2C2_SDA 0x0C4 0x32C 0x560 0x3 0x1 -#define MX8MN_IOMUXC_SD1_DATA7_UART3_DCE_RX 0x0C4 0x32C 0x504 0x4 0x5 -#define MX8MN_IOMUXC_SD1_DATA7_UART3_DTE_TX 0x0C4 0x32C 0x000 0x4 0x0 -#define MX8MN_IOMUXC_SD1_DATA7_GPIO2_IO9 0x0C4 0x32C 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x0C8 0x330 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SD1_RESET_B_ENET1_TX_CLK 0x0C8 0x330 0x5A4 0x1 0x1 -#define MX8MN_IOMUXC_SD1_RESET_B_CCMSRCGPCMIX_ENET_REF_CLK_ROOT 0x0C8 0x330 0x5A4 0x1 0x0 -#define MX8MN_IOMUXC_SD1_RESET_B_I2C3_SCL 0x0C8 0x330 0x588 0x3 0x1 -#define MX8MN_IOMUXC_SD1_RESET_B_UART3_DCE_RTS_B 0x0C8 0x330 0x500 0x4 0x2 -#define MX8MN_IOMUXC_SD1_RESET_B_UART3_DTE_CTS_B 0x0C8 0x330 0x000 0x4 0x0 -#define MX8MN_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x0C8 0x330 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x0CC 0x334 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SD1_STROBE_I2C3_SDA 0x0CC 0x334 0x5BC 0x3 0x1 -#define MX8MN_IOMUXC_SD1_STROBE_UART3_DCE_CTS_B 0x0CC 0x334 0x000 0x4 0x0 -#define MX8MN_IOMUXC_SD1_STROBE_UART3_DTE_RTS_B 0x0CC 0x334 0x500 0x4 0x3 -#define MX8MN_IOMUXC_SD1_STROBE_GPIO2_IO11 0x0CC 0x334 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0D0 0x338 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SD2_CD_B_GPIO2_IO12 0x0D0 0x338 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SD2_CD_B_CCMSRCGPCMIX_TESTER_ACK 0x0D0 0x338 0x000 0x6 0x0 -#define MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x0D4 0x33C 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SD2_CLK_SAI5_RX_SYNC 0x0D4 0x33C 0x4E4 0x1 0x1 -#define MX8MN_IOMUXC_SD2_CLK_ECSPI2_SCLK 0x0D4 0x33C 0x580 0x2 0x1 -#define MX8MN_IOMUXC_SD2_CLK_UART4_DCE_RX 0x0D4 0x33C 0x50C 0x3 0x4 -#define MX8MN_IOMUXC_SD2_CLK_UART4_DTE_TX 0x0D4 0x33C 0x000 0x3 0x0 -#define MX8MN_IOMUXC_SD2_CLK_SAI5_MCLK 0x0D4 0x33C 0x594 0x4 0x1 -#define MX8MN_IOMUXC_SD2_CLK_GPIO2_IO13 0x0D4 0x33C 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SD2_CLK_CCMSRCGPCMIX_OBSERVE0 0x0D4 0x33C 0x000 0x6 0x0 -#define MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x0D8 0x340 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SD2_CMD_SAI5_RX_BCLK 0x0D8 0x340 0x4D0 0x1 0x1 -#define MX8MN_IOMUXC_SD2_CMD_ECSPI2_MOSI 0x0D8 0x340 0x590 0x2 0x1 -#define MX8MN_IOMUXC_SD2_CMD_UART4_DCE_TX 0x0D8 0x340 0x000 0x3 0x0 -#define MX8MN_IOMUXC_SD2_CMD_UART4_DTE_RX 0x0D8 0x340 0x50C 0x3 0x5 -#define MX8MN_IOMUXC_SD2_CMD_PDM_CLK 0x0D8 0x340 0x000 0x4 0x0 -#define MX8MN_IOMUXC_SD2_CMD_GPIO2_IO14 0x0D8 0x340 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SD2_CMD_CCMSRCGPCMIX_OBSERVE1 0x0D8 0x340 0x000 0x6 0x0 -#define MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0DC 0x344 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SD2_DATA0_SAI5_RX_DATA0 0x0DC 0x344 0x4D4 0x1 0x1 -#define MX8MN_IOMUXC_SD2_DATA0_I2C4_SDA 0x0DC 0x344 0x58C 0x2 0x1 -#define MX8MN_IOMUXC_SD2_DATA0_UART2_DCE_RX 0x0DC 0x344 0x4FC 0x3 0x6 -#define MX8MN_IOMUXC_SD2_DATA0_UART2_DTE_TX 0x0DC 0x344 0x000 0x3 0x0 -#define MX8MN_IOMUXC_SD2_DATA0_PDM_BIT_STREAM0 0x0DC 0x344 0x534 0x4 0x2 -#define MX8MN_IOMUXC_SD2_DATA0_GPIO2_IO15 0x0DC 0x344 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SD2_DATA0_CCMSRCGPCMIX_OBSERVE2 0x0DC 0x344 0x000 0x6 0x0 -#define MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0E0 0x348 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SD2_DATA1_SAI5_TX_SYNC 0x0E0 0x348 0x4EC 0x1 0x1 -#define MX8MN_IOMUXC_SD2_DATA1_I2C4_SCL 0x0E0 0x348 0x5D4 0x2 0x1 -#define MX8MN_IOMUXC_SD2_DATA1_UART2_DCE_TX 0x0E0 0x348 0x000 0x3 0x0 -#define MX8MN_IOMUXC_SD2_DATA1_UART2_DTE_RX 0x0E0 0x348 0x4FC 0x3 0x7 -#define MX8MN_IOMUXC_SD2_DATA1_PDM_BIT_STREAM1 0x0E0 0x348 0x538 0x4 0x4 -#define MX8MN_IOMUXC_SD2_DATA1_GPIO2_IO16 0x0E0 0x348 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SD2_DATA1_CCMSRCGPCMIX_WAIT 0x0E0 0x348 0x000 0x6 0x0 -#define MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0E4 0x34C 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SD2_DATA2_SAI5_TX_BCLK 0x0E4 0x34C 0x4E8 0x1 0x1 -#define MX8MN_IOMUXC_SD2_DATA2_ECSPI2_SS0 0x0E4 0x34C 0x570 0x2 0x2 -#define MX8MN_IOMUXC_SD2_DATA2_SPDIF1_OUT 0x0E4 0x34C 0x000 0x3 0x0 -#define MX8MN_IOMUXC_SD2_DATA2_PDM_BIT_STREAM2 0x0E4 0x34C 0x53C 0x4 0x4 -#define MX8MN_IOMUXC_SD2_DATA2_GPIO2_IO17 0x0E4 0x34C 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SD2_DATA2_CCMSRCGPCMIX_STOP 0x0E4 0x34C 0x000 0x6 0x0 -#define MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0E8 0x350 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SD2_DATA3_SAI5_TX_DATA0 0x0E8 0x350 0x000 0x1 0x0 -#define MX8MN_IOMUXC_SD2_DATA3_ECSPI2_MISO 0x0E8 0x350 0x578 0x2 0x1 -#define MX8MN_IOMUXC_SD2_DATA3_SPDIF1_IN 0x0E8 0x350 0x5CC 0x3 0x2 -#define MX8MN_IOMUXC_SD2_DATA3_PDM_BIT_STREAM3 0x0E8 0x350 0x540 0x4 0x4 -#define MX8MN_IOMUXC_SD2_DATA3_GPIO2_IO18 0x0E8 0x350 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SD2_DATA3_CCMSRCGPCMIX_EARLY_RESET 0x0E8 0x350 0x000 0x6 0x0 -#define MX8MN_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x0EC 0x354 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x0EC 0x354 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SD2_RESET_B_CCMSRCGPCMIX_SYSTEM_RESET 0x0EC 0x354 0x000 0x6 0x0 -#define MX8MN_IOMUXC_SD2_WP_USDHC2_WP 0x0F0 0x358 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SD2_WP_GPIO2_IO20 0x0F0 0x358 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SD2_WP_CORESIGHT_EVENTI 0x0F0 0x358 0x000 0x6 0x0 -#define MX8MN_IOMUXC_NAND_ALE_RAWNAND_ALE 0x0F4 0x35C 0x000 0x0 0x0 -#define MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x0F4 0x35C 0x000 0x1 0x0 -#define MX8MN_IOMUXC_NAND_ALE_PDM_BIT_STREAM0 0x0F4 0x35C 0x534 0x3 0x3 -#define MX8MN_IOMUXC_NAND_ALE_UART3_DCE_RX 0x0F4 0x35C 0x504 0x4 0x6 -#define MX8MN_IOMUXC_NAND_ALE_UART3_DTE_TX 0x0F4 0x35C 0x000 0x4 0x0 -#define MX8MN_IOMUXC_NAND_ALE_GPIO3_IO0 0x0F4 0x35C 0x000 0x5 0x0 -#define MX8MN_IOMUXC_NAND_ALE_CORESIGHT_TRACE_CLK 0x0F4 0x35C 0x000 0x6 0x0 -#define MX8MN_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x0F8 0x360 0x000 0x0 0x0 -#define MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x0F8 0x360 0x000 0x1 0x0 -#define MX8MN_IOMUXC_NAND_CE0_B_PDM_BIT_STREAM1 0x0F8 0x360 0x538 0x3 0x5 -#define MX8MN_IOMUXC_NAND_CE0_B_UART3_DCE_TX 0x0F8 0x360 0x000 0x4 0x0 -#define MX8MN_IOMUXC_NAND_CE0_B_UART3_DTE_RX 0x0F8 0x360 0x504 0x4 0x7 -#define MX8MN_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x0F8 0x360 0x000 0x5 0x0 -#define MX8MN_IOMUXC_NAND_CE0_B_CORESIGHT_TRACE_CTL 0x0F8 0x360 0x000 0x6 0x0 -#define MX8MN_IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x0FC 0x364 0x000 0x0 0x0 -#define MX8MN_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x0FC 0x364 0x000 0x1 0x0 -#define MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x0FC 0x364 0x59C 0x2 0x0 -#define MX8MN_IOMUXC_NAND_CE1_B_PDM_BIT_STREAM0 0x0FC 0x364 0x534 0x3 0x4 -#define MX8MN_IOMUXC_NAND_CE1_B_I2C4_SCL 0x0FC 0x364 0x5D4 0x4 0x2 -#define MX8MN_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x0FC 0x364 0x000 0x5 0x0 -#define MX8MN_IOMUXC_NAND_CE1_B_CORESIGHT_TRACE0 0x0FC 0x364 0x000 0x6 0x0 -#define MX8MN_IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x100 0x368 0x000 0x0 0x0 -#define MX8MN_IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x100 0x368 0x000 0x1 0x0 -#define MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x100 0x368 0x550 0x2 0x0 -#define MX8MN_IOMUXC_NAND_CE2_B_PDM_BIT_STREAM1 0x100 0x368 0x538 0x3 0x6 -#define MX8MN_IOMUXC_NAND_CE2_B_I2C4_SDA 0x100 0x368 0x58C 0x4 0x2 -#define MX8MN_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x100 0x368 0x000 0x5 0x0 -#define MX8MN_IOMUXC_NAND_CE2_B_CORESIGHT_TRACE1 0x100 0x368 0x000 0x6 0x0 -#define MX8MN_IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x104 0x36C 0x000 0x0 0x0 -#define MX8MN_IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x104 0x36C 0x000 0x1 0x0 -#define MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x104 0x36C 0x584 0x2 0x0 -#define MX8MN_IOMUXC_NAND_CE3_B_PDM_BIT_STREAM2 0x104 0x36C 0x53C 0x3 0x5 -#define MX8MN_IOMUXC_NAND_CE3_B_I2C3_SDA 0x104 0x36C 0x5BC 0x4 0x2 -#define MX8MN_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x104 0x36C 0x000 0x5 0x0 -#define MX8MN_IOMUXC_NAND_CE3_B_CORESIGHT_TRACE2 0x104 0x36C 0x000 0x6 0x0 -#define MX8MN_IOMUXC_NAND_CLE_RAWNAND_CLE 0x108 0x370 0x000 0x0 0x0 -#define MX8MN_IOMUXC_NAND_CLE_QSPI_B_SCLK 0x108 0x370 0x000 0x1 0x0 -#define MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x108 0x370 0x54C 0x2 0x0 -#define MX8MN_IOMUXC_NAND_CLE_GPIO3_IO5 0x108 0x370 0x000 0x5 0x0 -#define MX8MN_IOMUXC_NAND_CLE_CORESIGHT_TRACE3 0x108 0x370 0x000 0x6 0x0 -#define MX8MN_IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x10C 0x374 0x000 0x0 0x0 -#define MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x10C 0x374 0x000 0x1 0x0 -#define MX8MN_IOMUXC_NAND_DATA00_PDM_BIT_STREAM2 0x10C 0x374 0x53C 0x3 0x6 -#define MX8MN_IOMUXC_NAND_DATA00_UART4_DCE_RX 0x10C 0x374 0x50C 0x4 0x6 -#define MX8MN_IOMUXC_NAND_DATA00_UART4_DTE_TX 0x10C 0x374 0x000 0x4 0x0 -#define MX8MN_IOMUXC_NAND_DATA00_GPIO3_IO6 0x10C 0x374 0x000 0x5 0x0 -#define MX8MN_IOMUXC_NAND_DATA00_CORESIGHT_TRACE4 0x10C 0x374 0x000 0x6 0x0 -#define MX8MN_IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x110 0x378 0x000 0x0 0x0 -#define MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x110 0x378 0x000 0x1 0x0 -#define MX8MN_IOMUXC_NAND_DATA01_PDM_BIT_STREAM3 0x110 0x378 0x540 0x3 0x5 -#define MX8MN_IOMUXC_NAND_DATA01_UART4_DCE_TX 0x110 0x378 0x000 0x4 0x0 -#define MX8MN_IOMUXC_NAND_DATA01_UART4_DTE_RX 0x110 0x378 0x50C 0x4 0x7 -#define MX8MN_IOMUXC_NAND_DATA01_GPIO3_IO7 0x110 0x378 0x000 0x5 0x0 -#define MX8MN_IOMUXC_NAND_DATA01_CORESIGHT_TRACE5 0x110 0x378 0x000 0x6 0x0 -#define MX8MN_IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x114 0x37C 0x000 0x0 0x0 -#define MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x114 0x37C 0x000 0x1 0x0 -#define MX8MN_IOMUXC_NAND_DATA02_USDHC3_CD_B 0x114 0x37C 0x598 0x2 0x0 -#define MX8MN_IOMUXC_NAND_DATA02_I2C4_SDA 0x114 0x37C 0x58C 0x4 0x3 -#define MX8MN_IOMUXC_NAND_DATA02_GPIO3_IO8 0x114 0x37C 0x000 0x5 0x0 -#define MX8MN_IOMUXC_NAND_DATA02_CORESIGHT_TRACE6 0x114 0x37C 0x000 0x6 0x0 -#define MX8MN_IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x118 0x380 0x000 0x0 0x0 -#define MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x118 0x380 0x000 0x1 0x0 -#define MX8MN_IOMUXC_NAND_DATA03_USDHC3_WP 0x118 0x380 0x5B8 0x2 0x0 -#define MX8MN_IOMUXC_NAND_DATA03_GPIO3_IO9 0x118 0x380 0x000 0x5 0x0 -#define MX8MN_IOMUXC_NAND_DATA03_CORESIGHT_TRACE7 0x118 0x380 0x000 0x6 0x0 -#define MX8MN_IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x11C 0x384 0x000 0x0 0x0 -#define MX8MN_IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x11C 0x384 0x000 0x1 0x0 -#define MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x11C 0x384 0x5B4 0x2 0x0 -#define MX8MN_IOMUXC_NAND_DATA04_GPIO3_IO10 0x11C 0x384 0x000 0x5 0x0 -#define MX8MN_IOMUXC_NAND_DATA04_CORESIGHT_TRACE8 0x11C 0x384 0x000 0x6 0x0 -#define MX8MN_IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x120 0x388 0x000 0x0 0x0 -#define MX8MN_IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x120 0x388 0x000 0x1 0x0 -#define MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x120 0x388 0x5B0 0x2 0x0 -#define MX8MN_IOMUXC_NAND_DATA05_GPIO3_IO11 0x120 0x388 0x000 0x5 0x0 -#define MX8MN_IOMUXC_NAND_DATA05_CORESIGHT_TRACE9 0x120 0x388 0x000 0x6 0x0 -#define MX8MN_IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x124 0x38C 0x000 0x0 0x0 -#define MX8MN_IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x124 0x38C 0x000 0x1 0x0 -#define MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x124 0x38C 0x5E4 0x2 0x0 -#define MX8MN_IOMUXC_NAND_DATA06_GPIO3_IO12 0x124 0x38C 0x000 0x5 0x0 -#define MX8MN_IOMUXC_NAND_DATA06_CORESIGHT_TRACE10 0x124 0x38C 0x000 0x6 0x0 -#define MX8MN_IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x128 0x390 0x000 0x0 0x0 -#define MX8MN_IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x128 0x390 0x000 0x1 0x0 -#define MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x128 0x390 0x5E0 0x2 0x0 -#define MX8MN_IOMUXC_NAND_DATA07_GPIO3_IO13 0x128 0x390 0x000 0x5 0x0 -#define MX8MN_IOMUXC_NAND_DATA07_CORESIGHT_TRACE11 0x128 0x390 0x000 0x6 0x0 -#define MX8MN_IOMUXC_NAND_DQS_RAWNAND_DQS 0x12C 0x394 0x000 0x0 0x0 -#define MX8MN_IOMUXC_NAND_DQS_QSPI_A_DQS 0x12C 0x394 0x000 0x1 0x0 -#define MX8MN_IOMUXC_NAND_DQS_PDM_CLK 0x12C 0x394 0x000 0x3 0x0 -#define MX8MN_IOMUXC_NAND_DQS_I2C3_SCL 0x12C 0x394 0x588 0x4 0x2 -#define MX8MN_IOMUXC_NAND_DQS_GPIO3_IO14 0x12C 0x394 0x000 0x5 0x0 -#define MX8MN_IOMUXC_NAND_DQS_CORESIGHT_TRACE12 0x12C 0x394 0x000 0x6 0x0 -#define MX8MN_IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x130 0x398 0x000 0x0 0x0 -#define MX8MN_IOMUXC_NAND_RE_B_QSPI_B_DQS 0x130 0x398 0x000 0x1 0x0 -#define MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x130 0x398 0x558 0x2 0x0 -#define MX8MN_IOMUXC_NAND_RE_B_PDM_BIT_STREAM1 0x130 0x398 0x538 0x3 0x7 -#define MX8MN_IOMUXC_NAND_RE_B_GPIO3_IO15 0x130 0x398 0x000 0x5 0x0 -#define MX8MN_IOMUXC_NAND_RE_B_CORESIGHT_TRACE13 0x130 0x398 0x000 0x6 0x0 -#define MX8MN_IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x134 0x39C 0x000 0x0 0x0 -#define MX8MN_IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x134 0x39C 0x000 0x2 0x0 -#define MX8MN_IOMUXC_NAND_READY_B_PDM_BIT_STREAM3 0x134 0x39C 0x540 0x3 0x6 -#define MX8MN_IOMUXC_NAND_READY_B_I2C3_SCL 0x134 0x39C 0x588 0x4 0x3 -#define MX8MN_IOMUXC_NAND_READY_B_GPIO3_IO16 0x134 0x39C 0x000 0x5 0x0 -#define MX8MN_IOMUXC_NAND_READY_B_CORESIGHT_TRACE14 0x134 0x39C 0x000 0x6 0x0 -#define MX8MN_IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x138 0x3A0 0x000 0x0 0x0 -#define MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x138 0x3A0 0x5A0 0x2 0x0 -#define MX8MN_IOMUXC_NAND_WE_B_I2C3_SDA 0x138 0x3A0 0x5BC 0x4 0x3 -#define MX8MN_IOMUXC_NAND_WE_B_GPIO3_IO17 0x138 0x3A0 0x000 0x5 0x0 -#define MX8MN_IOMUXC_NAND_WE_B_CORESIGHT_TRACE15 0x138 0x3A0 0x000 0x6 0x0 -#define MX8MN_IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x13C 0x3A4 0x000 0x0 0x0 -#define MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x13C 0x3A4 0x5DC 0x2 0x0 -#define MX8MN_IOMUXC_NAND_WP_B_I2C4_SDA 0x13C 0x3A4 0x58C 0x4 0x4 -#define MX8MN_IOMUXC_NAND_WP_B_GPIO3_IO18 0x13C 0x3A4 0x000 0x5 0x0 -#define MX8MN_IOMUXC_NAND_WP_B_CORESIGHT_EVENTO 0x13C 0x3A4 0x000 0x6 0x0 -#define MX8MN_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x140 0x3A8 0x4E4 0x0 0x0 -#define MX8MN_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x140 0x3A8 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x144 0x3AC 0x4D0 0x0 0x0 -#define MX8MN_IOMUXC_SAI5_RXC_PDM_CLK 0x144 0x3AC 0x000 0x4 0x0 -#define MX8MN_IOMUXC_SAI5_RXC_GPIO3_IO20 0x144 0x3AC 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x148 0x3B0 0x4D4 0x0 0x0 -#define MX8MN_IOMUXC_SAI5_RXD0_PDM_BIT_STREAM0 0x148 0x3B0 0x534 0x4 0x0 -#define MX8MN_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x148 0x3B0 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x14C 0x3B4 0x4D8 0x0 0x0 -#define MX8MN_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x14C 0x3B4 0x4EC 0x3 0x0 -#define MX8MN_IOMUXC_SAI5_RXD1_PDM_BIT_STREAM1 0x14C 0x3B4 0x538 0x4 0x0 -#define MX8MN_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x14C 0x3B4 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x150 0x3B8 0x4DC 0x0 0x0 -#define MX8MN_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x150 0x3B8 0x4E8 0x3 0x0 -#define MX8MN_IOMUXC_SAI5_RXD2_PDM_BIT_STREAM2 0x150 0x3B8 0x53C 0x4 0x0 -#define MX8MN_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x150 0x3B8 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x154 0x3BC 0x4E0 0x0 0x0 -#define MX8MN_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x154 0x3BC 0x000 0x3 0x0 -#define MX8MN_IOMUXC_SAI5_RXD3_PDM_BIT_STREAM3 0x154 0x3BC 0x540 0x4 0x0 -#define MX8MN_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x154 0x3BC 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SAI5_MCLK_SAI5_MCLK 0x158 0x3C0 0x594 0x0 0x0 -#define MX8MN_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x158 0x3C0 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x1B0 0x418 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x1B0 0x418 0x4EC 0x1 0x2 -#define MX8MN_IOMUXC_SAI2_RXFS_SAI5_TX_DATA1 0x1B0 0x418 0x000 0x2 0x0 -#define MX8MN_IOMUXC_SAI2_RXFS_SAI2_RX_DATA1 0x1B0 0x418 0x5AC 0x3 0x0 -#define MX8MN_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x1B0 0x418 0x000 0x4 0x0 -#define MX8MN_IOMUXC_SAI2_RXFS_UART1_DTE_RX 0x1B0 0x418 0x4F4 0x4 0x2 -#define MX8MN_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x1B0 0x418 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SAI2_RXFS_PDM_BIT_STREAM2 0x1B0 0x418 0x53C 0x6 0x7 -#define MX8MN_IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x1B4 0x41C 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x1B4 0x41C 0x4E8 0x1 0x2 -#define MX8MN_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x1B4 0x41C 0x4F4 0x4 0x3 -#define MX8MN_IOMUXC_SAI2_RXC_UART1_DTE_TX 0x1B4 0x41C 0x000 0x4 0x0 -#define MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x1B4 0x41C 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SAI2_RXC_PDM_BIT_STREAM1 0x1B4 0x41C 0x538 0x6 0x8 -#define MX8MN_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x1B8 0x420 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x1B8 0x420 0x000 0x1 0x0 -#define MX8MN_IOMUXC_SAI2_RXD0_SAI2_TX_DATA1 0x1B8 0x420 0x000 0x3 0x0 -#define MX8MN_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x1B8 0x420 0x4F0 0x4 0x2 -#define MX8MN_IOMUXC_SAI2_RXD0_UART1_DTE_CTS_B 0x1B8 0x420 0x000 0x4 0x0 -#define MX8MN_IOMUXC_SAI2_RXD0_GPIO4_IO23 0x1B8 0x420 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SAI2_RXD0_PDM_BIT_STREAM3 0x1B8 0x420 0x540 0x6 0x7 -#define MX8MN_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x1BC 0x424 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x1BC 0x424 0x000 0x1 0x0 -#define MX8MN_IOMUXC_SAI2_TXFS_SAI2_TX_DATA1 0x1BC 0x424 0x000 0x3 0x0 -#define MX8MN_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x1BC 0x424 0x000 0x4 0x0 -#define MX8MN_IOMUXC_SAI2_TXFS_UART1_DTE_RTS_B 0x1BC 0x424 0x4F0 0x4 0x3 -#define MX8MN_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x1BC 0x424 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SAI2_TXFS_PDM_BIT_STREAM2 0x1BC 0x424 0x53C 0x6 0x8 -#define MX8MN_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x1C0 0x428 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x1C0 0x428 0x000 0x1 0x0 -#define MX8MN_IOMUXC_SAI2_TXC_GPIO4_IO25 0x1C0 0x428 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SAI2_TXC_PDM_BIT_STREAM1 0x1C0 0x428 0x538 0x6 0x9 -#define MX8MN_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x1C4 0x42C 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x1C4 0x42C 0x000 0x1 0x0 -#define MX8MN_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x1C4 0x42C 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SAI2_TXD0_CCMSRCGPCMIX_BOOT_MODE4 0x1C4 0x42C 0x540 0x6 0x8 -#define MX8MN_IOMUXC_SAI2_MCLK_SAI2_MCLK 0x1C8 0x430 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SAI2_MCLK_SAI5_MCLK 0x1C8 0x430 0x594 0x1 0x2 -#define MX8MN_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x1C8 0x430 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SAI2_MCLK_SAI3_MCLK 0x1C8 0x430 0x5C0 0x6 0x1 -#define MX8MN_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x1CC 0x434 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x1CC 0x434 0x5F0 0x1 0x0 -#define MX8MN_IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x1CC 0x434 0x4E4 0x2 0x2 -#define MX8MN_IOMUXC_SAI3_RXFS_SAI3_RX_DATA1 0x1CC 0x434 0x000 0x3 0x0 -#define MX8MN_IOMUXC_SAI3_RXFS_SPDIF1_IN 0x1CC 0x434 0x5CC 0x4 0x3 -#define MX8MN_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x1CC 0x434 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SAI3_RXFS_PDM_BIT_STREAM0 0x1CC 0x434 0x534 0x6 0x5 -#define MX8MN_IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x1D0 0x438 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SAI3_RXC_GPT1_CLK 0x1D0 0x438 0x5E8 0x1 0x0 -#define MX8MN_IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x1D0 0x438 0x4D0 0x2 0x2 -#define MX8MN_IOMUXC_SAI3_RXC_SAI2_RX_DATA1 0x1D0 0x438 0x5AC 0x3 0x2 -#define MX8MN_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x1D0 0x438 0x000 0x4 0x0 -#define MX8MN_IOMUXC_SAI3_RXC_UART2_DTE_RTS_B 0x1D0 0x438 0x4F8 0x4 0x2 -#define MX8MN_IOMUXC_SAI3_RXC_GPIO4_IO29 0x1D0 0x438 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SAI3_RXC_PDM_CLK 0x1D0 0x438 0x000 0x6 0x0 -#define MX8MN_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x1D4 0x43C 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x1D4 0x43C 0x000 0x1 0x0 -#define MX8MN_IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x1D4 0x43C 0x4D4 0x2 0x2 -#define MX8MN_IOMUXC_SAI3_RXD_SAI3_TX_DATA1 0x1D4 0x43C 0x000 0x3 0x0 -#define MX8MN_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x1D4 0x43C 0x4F8 0x4 0x3 -#define MX8MN_IOMUXC_SAI3_RXD_UART2_DTE_CTS_B 0x1D4 0x43C 0x000 0x4 0x0 -#define MX8MN_IOMUXC_SAI3_RXD_GPIO4_IO30 0x1D4 0x43C 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SAI3_RXD_PDM_BIT_STREAM1 0x1D4 0x43C 0x538 0x6 0x10 -#define MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x1D8 0x440 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SAI3_TXFS_GPT1_CAPTURE2 0x1D8 0x440 0x5EC 0x1 0x0 -#define MX8MN_IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x1D8 0x440 0x4D8 0x2 0x1 -#define MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_DATA1 0x1D8 0x440 0x000 0x3 0x0 -#define MX8MN_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x1D8 0x440 0x4FC 0x4 0x2 -#define MX8MN_IOMUXC_SAI3_TXFS_UART2_DTE_TX 0x1D8 0x440 0x000 0x4 0x0 -#define MX8MN_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x1D8 0x440 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SAI3_TXFS_PDM_BIT_STREAM3 0x1D8 0x440 0x540 0x6 0x9 -#define MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x1DC 0x444 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x1DC 0x444 0x000 0x1 0x0 -#define MX8MN_IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x1DC 0x444 0x4DC 0x2 0x1 -#define MX8MN_IOMUXC_SAI3_TXC_SAI2_TX_DATA1 0x1DC 0x444 0x000 0x3 0x0 -#define MX8MN_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x1DC 0x444 0x000 0x4 0x0 -#define MX8MN_IOMUXC_SAI3_TXC_UART2_DTE_RX 0x1DC 0x444 0x4FC 0x4 0x3 -#define MX8MN_IOMUXC_SAI3_TXC_GPIO5_IO0 0x1DC 0x444 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SAI3_TXC_PDM_BIT_STREAM2 0x1DC 0x444 0x53C 0x6 0x9 -#define MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x1E0 0x448 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x1E0 0x448 0x000 0x1 0x0 -#define MX8MN_IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x1E0 0x448 0x4E0 0x2 0x1 -#define MX8MN_IOMUXC_SAI3_TXD_SPDIF1_EXT_CLK 0x1E0 0x448 0x568 0x4 0x2 -#define MX8MN_IOMUXC_SAI3_TXD_GPIO5_IO1 0x1E0 0x448 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SAI3_TXD_CCMSRCGPCMIX_BOOT_MODE5 0x1E0 0x448 0x000 0x6 0x0 -#define MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK 0x1E4 0x44C 0x5C0 0x0 0x0 -#define MX8MN_IOMUXC_SAI3_MCLK_PWM4_OUT 0x1E4 0x44C 0x000 0x1 0x0 -#define MX8MN_IOMUXC_SAI3_MCLK_SAI5_MCLK 0x1E4 0x44C 0x594 0x2 0x3 -#define MX8MN_IOMUXC_SAI3_MCLK_SPDIF1_OUT 0x1E4 0x44C 0x000 0x4 0x0 -#define MX8MN_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x1E4 0x44C 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SAI3_MCLK_SPDIF1_IN 0x1E4 0x44C 0x5CC 0x6 0x4 -#define MX8MN_IOMUXC_SPDIF_TX_SPDIF1_OUT 0x1E8 0x450 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SPDIF_TX_PWM3_OUT 0x1E8 0x450 0x000 0x1 0x0 -#define MX8MN_IOMUXC_SPDIF_TX_GPIO5_IO3 0x1E8 0x450 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SPDIF_RX_SPDIF1_IN 0x1EC 0x454 0x5CC 0x0 0x0 -#define MX8MN_IOMUXC_SPDIF_RX_PWM2_OUT 0x1EC 0x454 0x000 0x1 0x0 -#define MX8MN_IOMUXC_SPDIF_RX_GPIO5_IO4 0x1EC 0x454 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x1F0 0x458 0x568 0x0 0x0 -#define MX8MN_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x1F0 0x458 0x000 0x1 0x0 -#define MX8MN_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x1F0 0x458 0x000 0x5 0x0 -#define MX8MN_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x1F4 0x45C 0x5D8 0x0 0x0 -#define MX8MN_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x1F4 0x45C 0x504 0x1 0x0 -#define MX8MN_IOMUXC_ECSPI1_SCLK_UART3_DTE_TX 0x1F4 0x45C 0x000 0x1 0x0 -#define MX8MN_IOMUXC_ECSPI1_SCLK_I2C1_SCL 0x1F4 0x45C 0x55C 0x2 0x2 -#define MX8MN_IOMUXC_ECSPI1_SCLK_SAI5_RX_SYNC 0x1F4 0x45C 0x4DC 0x3 0x2 -#define MX8MN_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x1F4 0x45C 0x000 0x5 0x0 -#define MX8MN_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x1F8 0x460 0x5A8 0x0 0x0 -#define MX8MN_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x1F8 0x460 0x000 0x1 0x0 -#define MX8MN_IOMUXC_ECSPI1_MOSI_UART3_DTE_RX 0x1F8 0x460 0x504 0x1 0x1 -#define MX8MN_IOMUXC_ECSPI1_MOSI_I2C1_SDA 0x1F8 0x460 0x56C 0x2 0x2 -#define MX8MN_IOMUXC_ECSPI1_MOSI_SAI5_RX_BCLK 0x1F8 0x460 0x4D0 0x3 0x3 -#define MX8MN_IOMUXC_ECSPI1_MOSI_GPIO5_IO7 0x1F8 0x460 0x000 0x5 0x0 -#define MX8MN_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x1FC 0x464 0x5C4 0x0 0x0 -#define MX8MN_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x1FC 0x464 0x000 0x1 0x0 -#define MX8MN_IOMUXC_ECSPI1_MISO_UART3_DTE_RTS_B 0x1FC 0x464 0x500 0x1 0x0 -#define MX8MN_IOMUXC_ECSPI1_MISO_I2C2_SCL 0x1FC 0x464 0x5D0 0x2 0x2 -#define MX8MN_IOMUXC_ECSPI1_MISO_SAI5_RX_DATA0 0x1FC 0x464 0x4D4 0x3 0x3 -#define MX8MN_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x1FC 0x464 0x000 0x5 0x0 -#define MX8MN_IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x200 0x468 0x564 0x0 0x0 -#define MX8MN_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x200 0x468 0x500 0x1 0x1 -#define MX8MN_IOMUXC_ECSPI1_SS0_UART3_DTE_CTS_B 0x200 0x468 0x000 0x1 0x0 -#define MX8MN_IOMUXC_ECSPI1_SS0_I2C2_SDA 0x200 0x468 0x560 0x2 0x2 -#define MX8MN_IOMUXC_ECSPI1_SS0_SAI5_RX_DATA1 0x200 0x468 0x4D8 0x3 0x2 -#define MX8MN_IOMUXC_ECSPI1_SS0_SAI5_TX_SYNC 0x200 0x468 0x4EC 0x4 0x3 -#define MX8MN_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x200 0x468 0x000 0x5 0x0 -#define MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x204 0x46C 0x580 0x0 0x0 -#define MX8MN_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x204 0x46C 0x50C 0x1 0x0 -#define MX8MN_IOMUXC_ECSPI2_SCLK_UART4_DTE_TX 0x204 0x46C 0x000 0x1 0x0 -#define MX8MN_IOMUXC_ECSPI2_SCLK_I2C3_SCL 0x204 0x46C 0x588 0x2 0x4 -#define MX8MN_IOMUXC_ECSPI2_SCLK_SAI5_RX_DATA2 0x204 0x46C 0x000 0x3 0x0 -#define MX8MN_IOMUXC_ECSPI2_SCLK_SAI5_TX_BCLK 0x204 0x46C 0x4E8 0x4 0x3 -#define MX8MN_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x204 0x46C 0x000 0x5 0x0 -#define MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x208 0x470 0x590 0x0 0x0 -#define MX8MN_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x208 0x470 0x000 0x1 0x0 -#define MX8MN_IOMUXC_ECSPI2_MOSI_UART4_DTE_RX 0x208 0x470 0x50C 0x1 0x1 -#define MX8MN_IOMUXC_ECSPI2_MOSI_I2C3_SDA 0x208 0x470 0x5BC 0x2 0x4 -#define MX8MN_IOMUXC_ECSPI2_MOSI_SAI5_RX_DATA3 0x208 0x470 0x4E0 0x3 0x2 -#define MX8MN_IOMUXC_ECSPI2_MOSI_SAI5_TX_DATA0 0x208 0x470 0x000 0x4 0x0 -#define MX8MN_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x208 0x470 0x000 0x5 0x0 -#define MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x20C 0x474 0x578 0x0 0x0 -#define MX8MN_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x20C 0x474 0x000 0x1 0x0 -#define MX8MN_IOMUXC_ECSPI2_MISO_UART4_DTE_RTS_B 0x20C 0x474 0x508 0x1 0x0 -#define MX8MN_IOMUXC_ECSPI2_MISO_I2C4_SCL 0x20C 0x474 0x5D4 0x2 0x3 -#define MX8MN_IOMUXC_ECSPI2_MISO_SAI5_MCLK 0x20C 0x474 0x594 0x3 0x4 -#define MX8MN_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x20C 0x474 0x000 0x5 0x0 -#define MX8MN_IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x210 0x478 0x570 0x0 0x0 -#define MX8MN_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x210 0x478 0x508 0x1 0x1 -#define MX8MN_IOMUXC_ECSPI2_SS0_UART4_DTE_CTS_B 0x210 0x478 0x000 0x1 0x0 -#define MX8MN_IOMUXC_ECSPI2_SS0_I2C4_SDA 0x210 0x478 0x58C 0x2 0x5 -#define MX8MN_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x210 0x478 0x000 0x5 0x0 -#define MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x214 0x47C 0x55C 0x0 0x0 -#define MX8MN_IOMUXC_I2C1_SCL_ENET1_MDC 0x214 0x47C 0x000 0x1 0x0 -#define MX8MN_IOMUXC_I2C1_SCL_ECSPI1_SCLK 0x214 0x47C 0x5D8 0x3 0x1 -#define MX8MN_IOMUXC_I2C1_SCL_GPIO5_IO14 0x214 0x47C 0x000 0x5 0x0 -#define MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x218 0x480 0x56C 0x0 0x0 -#define MX8MN_IOMUXC_I2C1_SDA_ENET1_MDIO 0x218 0x480 0x4C0 0x1 0x2 -#define MX8MN_IOMUXC_I2C1_SDA_ECSPI1_MOSI 0x218 0x480 0x5A8 0x3 0x1 -#define MX8MN_IOMUXC_I2C1_SDA_GPIO5_IO15 0x218 0x480 0x000 0x5 0x0 -#define MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x21C 0x484 0x5D0 0x0 0x0 -#define MX8MN_IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x21C 0x484 0x000 0x1 0x0 -#define MX8MN_IOMUXC_I2C2_SCL_USDHC3_CD_B 0x21C 0x484 0x598 0x2 0x1 -#define MX8MN_IOMUXC_I2C2_SCL_ECSPI1_MISO 0x21C 0x484 0x5C4 0x3 0x1 -#define MX8MN_IOMUXC_I2C2_SCL_GPIO5_IO16 0x21C 0x484 0x000 0x5 0x0 -#define MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x220 0x488 0x560 0x0 0x0 -#define MX8MN_IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x220 0x488 0x000 0x1 0x0 -#define MX8MN_IOMUXC_I2C2_SDA_USDHC3_WP 0x220 0x488 0x5B8 0x2 0x1 -#define MX8MN_IOMUXC_I2C2_SDA_ECSPI1_SS0 0x220 0x488 0x564 0x3 0x1 -#define MX8MN_IOMUXC_I2C2_SDA_GPIO5_IO17 0x220 0x488 0x000 0x5 0x0 -#define MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x224 0x48C 0x588 0x0 0x0 -#define MX8MN_IOMUXC_I2C3_SCL_PWM4_OUT 0x224 0x48C 0x000 0x1 0x0 -#define MX8MN_IOMUXC_I2C3_SCL_GPT2_CLK 0x224 0x48C 0x000 0x2 0x0 -#define MX8MN_IOMUXC_I2C3_SCL_ECSPI2_SCLK 0x224 0x48C 0x580 0x3 0x2 -#define MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18 0x224 0x48C 0x000 0x5 0x0 -#define MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x228 0x490 0x5BC 0x0 0x0 -#define MX8MN_IOMUXC_I2C3_SDA_PWM3_OUT 0x228 0x490 0x000 0x1 0x0 -#define MX8MN_IOMUXC_I2C3_SDA_GPT3_CLK 0x228 0x490 0x000 0x2 0x0 -#define MX8MN_IOMUXC_I2C3_SDA_ECSPI2_MOSI 0x228 0x490 0x590 0x3 0x2 -#define MX8MN_IOMUXC_I2C3_SDA_GPIO5_IO19 0x228 0x490 0x000 0x5 0x0 -#define MX8MN_IOMUXC_I2C4_SCL_I2C4_SCL 0x22C 0x494 0x5D4 0x0 0x0 -#define MX8MN_IOMUXC_I2C4_SCL_PWM2_OUT 0x22C 0x494 0x000 0x1 0x0 -#define MX8MN_IOMUXC_I2C4_SCL_ECSPI2_MISO 0x22C 0x494 0x578 0x3 0x2 -#define MX8MN_IOMUXC_I2C4_SCL_GPIO5_IO20 0x22C 0x494 0x000 0x5 0x0 -#define MX8MN_IOMUXC_I2C4_SDA_I2C4_SDA 0x230 0x498 0x58C 0x0 0x0 -#define MX8MN_IOMUXC_I2C4_SDA_PWM1_OUT 0x230 0x498 0x000 0x1 0x0 -#define MX8MN_IOMUXC_I2C4_SDA_ECSPI2_SS0 0x230 0x498 0x570 0x3 0x1 -#define MX8MN_IOMUXC_I2C4_SDA_GPIO5_IO21 0x230 0x498 0x000 0x5 0x0 -#define MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x234 0x49C 0x4F4 0x0 0x0 -#define MX8MN_IOMUXC_UART1_RXD_UART1_DTE_TX 0x234 0x49C 0x000 0x0 0x0 -#define MX8MN_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x234 0x49C 0x000 0x1 0x0 -#define MX8MN_IOMUXC_UART1_RXD_GPIO5_IO22 0x234 0x49C 0x000 0x5 0x0 -#define MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX 0x238 0x4A0 0x000 0x0 0x0 -#define MX8MN_IOMUXC_UART1_TXD_UART1_DTE_RX 0x238 0x4A0 0x4F4 0x0 0x1 -#define MX8MN_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x238 0x4A0 0x000 0x1 0x0 -#define MX8MN_IOMUXC_UART1_TXD_GPIO5_IO23 0x238 0x4A0 0x000 0x5 0x0 -#define MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x23C 0x4A4 0x4FC 0x0 0x0 -#define MX8MN_IOMUXC_UART2_RXD_UART2_DTE_TX 0x23C 0x4A4 0x000 0x0 0x0 -#define MX8MN_IOMUXC_UART2_RXD_ECSPI3_MISO 0x23C 0x4A4 0x000 0x1 0x0 -#define MX8MN_IOMUXC_UART2_RXD_GPT1_COMPARE3 0x23C 0x4A4 0x000 0x3 0x0 -#define MX8MN_IOMUXC_UART2_RXD_GPIO5_IO24 0x23C 0x4A4 0x000 0x5 0x0 -#define MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x240 0x4A8 0x000 0x0 0x0 -#define MX8MN_IOMUXC_UART2_TXD_UART2_DTE_RX 0x240 0x4A8 0x4FC 0x0 0x1 -#define MX8MN_IOMUXC_UART2_TXD_ECSPI3_SS0 0x240 0x4A8 0x000 0x1 0x0 -#define MX8MN_IOMUXC_UART2_TXD_GPT1_COMPARE2 0x240 0x4A8 0x000 0x3 0x0 -#define MX8MN_IOMUXC_UART2_TXD_GPIO5_IO25 0x240 0x4A8 0x000 0x5 0x0 -#define MX8MN_IOMUXC_UART3_RXD_UART3_DCE_RX 0x244 0x4AC 0x504 0x0 0x2 -#define MX8MN_IOMUXC_UART3_RXD_UART3_DTE_TX 0x244 0x4AC 0x000 0x0 0x0 -#define MX8MN_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x244 0x4AC 0x000 0x1 0x0 -#define MX8MN_IOMUXC_UART3_RXD_UART1_DTE_RTS_B 0x244 0x4AC 0x4F0 0x1 0x0 -#define MX8MN_IOMUXC_UART3_RXD_USDHC3_RESET_B 0x244 0x4AC 0x000 0x2 0x0 -#define MX8MN_IOMUXC_UART3_RXD_GPT1_CAPTURE2 0x244 0x4AC 0x5EC 0x3 0x1 -#define MX8MN_IOMUXC_UART3_RXD_GPIO5_IO26 0x244 0x4AC 0x000 0x5 0x0 -#define MX8MN_IOMUXC_UART3_TXD_UART3_DCE_TX 0x248 0x4B0 0x000 0x0 0x0 -#define MX8MN_IOMUXC_UART3_TXD_UART3_DTE_RX 0x248 0x4B0 0x504 0x0 0x3 -#define MX8MN_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x248 0x4B0 0x4F0 0x1 0x1 -#define MX8MN_IOMUXC_UART3_TXD_UART1_DTE_CTS_B 0x248 0x4B0 0x000 0x1 0x0 -#define MX8MN_IOMUXC_UART3_TXD_USDHC3_VSELECT 0x248 0x4B0 0x000 0x2 0x0 -#define MX8MN_IOMUXC_UART3_TXD_GPT1_CLK 0x248 0x4B0 0x5E8 0x3 0x1 -#define MX8MN_IOMUXC_UART3_TXD_GPIO5_IO27 0x248 0x4B0 0x000 0x5 0x0 -#define MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX 0x24C 0x4B4 0x50C 0x0 0x2 -#define MX8MN_IOMUXC_UART4_RXD_UART4_DTE_TX 0x24C 0x4B4 0x000 0x0 0x0 -#define MX8MN_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x24C 0x4B4 0x000 0x1 0x0 -#define MX8MN_IOMUXC_UART4_RXD_UART2_DTE_RTS_B 0x24C 0x4B4 0x4F8 0x1 0x0 -#define MX8MN_IOMUXC_UART4_RXD_GPT1_COMPARE1 0x24C 0x4B4 0x000 0x3 0x0 -#define MX8MN_IOMUXC_UART4_RXD_GPIO5_IO28 0x24C 0x4B4 0x000 0x5 0x0 -#define MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX 0x250 0x4B8 0x000 0x0 0x0 -#define MX8MN_IOMUXC_UART4_TXD_UART4_DTE_RX 0x250 0x4B8 0x50C 0x0 0x3 -#define MX8MN_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x250 0x4B8 0x4F8 0x1 0x1 -#define MX8MN_IOMUXC_UART4_TXD_UART2_DTE_CTS_B 0x250 0x4B8 0x000 0x1 0x0 -#define MX8MN_IOMUXC_UART4_TXD_GPT1_CAPTURE1 0x250 0x4B8 0x5F0 0x3 0x1 -#define MX8MN_IOMUXC_UART4_TXD_GPIO5_IO29 0x250 0x4B8 0x000 0x5 0x0 - -#endif /* __DTS_IMX8MN_PINFUNC_H */ diff --git a/sys/gnu/dts/arm64/freescale/imx8mn.dtsi b/sys/gnu/dts/arm64/freescale/imx8mn.dtsi deleted file mode 100644 index a44b5438e84..00000000000 --- a/sys/gnu/dts/arm64/freescale/imx8mn.dtsi +++ /dev/null @@ -1,817 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2019 NXP - */ - -#include -#include -#include -#include - -#include "imx8mn-pinfunc.h" - -/ { - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - ethernet0 = &fec1; - gpio0 = &gpio1; - gpio1 = &gpio2; - gpio2 = &gpio3; - gpio3 = &gpio4; - gpio4 = &gpio5; - i2c0 = &i2c1; - i2c1 = &i2c2; - i2c2 = &i2c3; - i2c3 = &i2c4; - mmc0 = &usdhc1; - mmc1 = &usdhc2; - mmc2 = &usdhc3; - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - serial3 = &uart4; - spi0 = &ecspi1; - spi1 = &ecspi2; - spi2 = &ecspi3; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - idle-states { - entry-method = "psci"; - - cpu_pd_wait: cpu-pd-wait { - compatible = "arm,idle-state"; - arm,psci-suspend-param = <0x0010033>; - local-timer-stop; - entry-latency-us = <1000>; - exit-latency-us = <700>; - min-residency-us = <2700>; - }; - }; - - A53_0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0>; - clock-latency = <61036>; - clocks = <&clk IMX8MN_CLK_ARM>; - enable-method = "psci"; - next-level-cache = <&A53_L2>; - operating-points-v2 = <&a53_opp_table>; - nvmem-cells = <&cpu_speed_grade>; - nvmem-cell-names = "speed_grade"; - cpu-idle-states = <&cpu_pd_wait>; - }; - - A53_1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x1>; - clock-latency = <61036>; - clocks = <&clk IMX8MN_CLK_ARM>; - enable-method = "psci"; - next-level-cache = <&A53_L2>; - operating-points-v2 = <&a53_opp_table>; - cpu-idle-states = <&cpu_pd_wait>; - }; - - A53_2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x2>; - clock-latency = <61036>; - clocks = <&clk IMX8MN_CLK_ARM>; - enable-method = "psci"; - next-level-cache = <&A53_L2>; - operating-points-v2 = <&a53_opp_table>; - cpu-idle-states = <&cpu_pd_wait>; - }; - - A53_3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x3>; - clock-latency = <61036>; - clocks = <&clk IMX8MN_CLK_ARM>; - enable-method = "psci"; - next-level-cache = <&A53_L2>; - operating-points-v2 = <&a53_opp_table>; - cpu-idle-states = <&cpu_pd_wait>; - }; - - A53_L2: l2-cache0 { - compatible = "cache"; - }; - }; - - a53_opp_table: opp-table { - compatible = "operating-points-v2"; - opp-shared; - - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <850000>; - opp-supported-hw = <0xb00>, <0x7>; - clock-latency-ns = <150000>; - opp-suspend; - }; - - opp-1400000000 { - opp-hz = /bits/ 64 <1400000000>; - opp-microvolt = <950000>; - opp-supported-hw = <0x300>, <0x7>; - clock-latency-ns = <150000>; - opp-suspend; - }; - - opp-1500000000 { - opp-hz = /bits/ 64 <1500000000>; - opp-microvolt = <1000000>; - opp-supported-hw = <0x100>, <0x3>; - clock-latency-ns = <150000>; - opp-suspend; - }; - }; - - osc_32k: clock-osc-32k { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "osc_32k"; - }; - - osc_24m: clock-osc-24m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "osc_24m"; - }; - - clk_ext1: clock-ext1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <133000000>; - clock-output-names = "clk_ext1"; - }; - - clk_ext2: clock-ext2 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <133000000>; - clock-output-names = "clk_ext2"; - }; - - clk_ext3: clock-ext3 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <133000000>; - clock-output-names = "clk_ext3"; - }; - - clk_ext4: clock-ext4 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency= <133000000>; - clock-output-names = "clk_ext4"; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - clock-frequency = <8000000>; - arm,no-tick-in-suspend; - }; - - soc@0 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x0 0x3e000000>; - - aips1: bus@30000000 { - compatible = "simple-bus"; - reg = <0x30000000 0x400000>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gpio1: gpio@30200000 { - compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio"; - reg = <0x30200000 0x10000>; - interrupts = , - ; - clocks = <&clk IMX8MN_CLK_GPIO1_ROOT>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 10 30>; - }; - - gpio2: gpio@30210000 { - compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio"; - reg = <0x30210000 0x10000>; - interrupts = , - ; - clocks = <&clk IMX8MN_CLK_GPIO2_ROOT>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 40 21>; - }; - - gpio3: gpio@30220000 { - compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio"; - reg = <0x30220000 0x10000>; - interrupts = , - ; - clocks = <&clk IMX8MN_CLK_GPIO3_ROOT>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 61 26>; - }; - - gpio4: gpio@30230000 { - compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio"; - reg = <0x30230000 0x10000>; - interrupts = , - ; - clocks = <&clk IMX8MN_CLK_GPIO4_ROOT>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 21 108 11>; - }; - - gpio5: gpio@30240000 { - compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio"; - reg = <0x30240000 0x10000>; - interrupts = , - ; - clocks = <&clk IMX8MN_CLK_GPIO5_ROOT>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 119 30>; - }; - - wdog1: watchdog@30280000 { - compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt"; - reg = <0x30280000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MN_CLK_WDOG1_ROOT>; - status = "disabled"; - }; - - wdog2: watchdog@30290000 { - compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt"; - reg = <0x30290000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MN_CLK_WDOG2_ROOT>; - status = "disabled"; - }; - - wdog3: watchdog@302a0000 { - compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt"; - reg = <0x302a0000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MN_CLK_WDOG3_ROOT>; - status = "disabled"; - }; - - sdma3: dma-controller@302b0000 { - compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma"; - reg = <0x302b0000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MN_CLK_SDMA3_ROOT>, - <&clk IMX8MN_CLK_SDMA3_ROOT>; - clock-names = "ipg", "ahb"; - #dma-cells = <3>; - fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; - }; - - sdma2: dma-controller@302c0000 { - compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma"; - reg = <0x302c0000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MN_CLK_SDMA2_ROOT>, - <&clk IMX8MN_CLK_SDMA2_ROOT>; - clock-names = "ipg", "ahb"; - #dma-cells = <3>; - fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; - }; - - iomuxc: pinctrl@30330000 { - compatible = "fsl,imx8mn-iomuxc"; - reg = <0x30330000 0x10000>; - }; - - gpr: iomuxc-gpr@30340000 { - compatible = "fsl,imx8mn-iomuxc-gpr", "syscon"; - reg = <0x30340000 0x10000>; - }; - - ocotp: ocotp-ctrl@30350000 { - compatible = "fsl,imx8mn-ocotp", "fsl,imx8mm-ocotp", "syscon"; - reg = <0x30350000 0x10000>; - clocks = <&clk IMX8MN_CLK_OCOTP_ROOT>; - #address-cells = <1>; - #size-cells = <1>; - - cpu_speed_grade: speed-grade@10 { - reg = <0x10 4>; - }; - }; - - anatop: anatop@30360000 { - compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop", - "syscon"; - reg = <0x30360000 0x10000>; - }; - - snvs: snvs@30370000 { - compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd"; - reg = <0x30370000 0x10000>; - - snvs_rtc: snvs-rtc-lp { - compatible = "fsl,sec-v4.0-mon-rtc-lp"; - regmap = <&snvs>; - offset = <0x34>; - interrupts = , - ; - clock-names = "snvs-rtc"; - }; - - snvs_pwrkey: snvs-powerkey { - compatible = "fsl,sec-v4.0-pwrkey"; - regmap = <&snvs>; - interrupts = ; - linux,keycode = ; - wakeup-source; - status = "disabled"; - }; - }; - - clk: clock-controller@30380000 { - compatible = "fsl,imx8mn-ccm"; - reg = <0x30380000 0x10000>; - #clock-cells = <1>; - clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, - <&clk_ext3>, <&clk_ext4>; - clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", - "clk_ext3", "clk_ext4"; - }; - - src: reset-controller@30390000 { - compatible = "fsl,imx8mn-src", "fsl,imx8mq-src", "syscon"; - reg = <0x30390000 0x10000>; - interrupts = ; - #reset-cells = <1>; - }; - }; - - aips2: bus@30400000 { - compatible = "simple-bus"; - reg = <0x30400000 0x400000>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - pwm1: pwm@30660000 { - compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm"; - reg = <0x30660000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MN_CLK_PWM1_ROOT>, - <&clk IMX8MN_CLK_PWM1_ROOT>; - clock-names = "ipg", "per"; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm2: pwm@30670000 { - compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm"; - reg = <0x30670000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MN_CLK_PWM2_ROOT>, - <&clk IMX8MN_CLK_PWM2_ROOT>; - clock-names = "ipg", "per"; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm3: pwm@30680000 { - compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm"; - reg = <0x30680000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MN_CLK_PWM3_ROOT>, - <&clk IMX8MN_CLK_PWM3_ROOT>; - clock-names = "ipg", "per"; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm4: pwm@30690000 { - compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm"; - reg = <0x30690000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MN_CLK_PWM4_ROOT>, - <&clk IMX8MN_CLK_PWM4_ROOT>; - clock-names = "ipg", "per"; - #pwm-cells = <2>; - status = "disabled"; - }; - - system_counter: timer@306a0000 { - compatible = "nxp,sysctr-timer"; - reg = <0x306a0000 0x20000>; - interrupts = ; - clocks = <&osc_24m>; - clock-names = "per"; - }; - }; - - aips3: bus@30800000 { - compatible = "simple-bus"; - reg = <0x30800000 0x400000>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - ecspi1: spi@30820000 { - compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x30820000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MN_CLK_ECSPI1_ROOT>, - <&clk IMX8MN_CLK_ECSPI1_ROOT>; - clock-names = "ipg", "per"; - dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - ecspi2: spi@30830000 { - compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x30830000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MN_CLK_ECSPI2_ROOT>, - <&clk IMX8MN_CLK_ECSPI2_ROOT>; - clock-names = "ipg", "per"; - dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - ecspi3: spi@30840000 { - compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x30840000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MN_CLK_ECSPI3_ROOT>, - <&clk IMX8MN_CLK_ECSPI3_ROOT>; - clock-names = "ipg", "per"; - dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart1: serial@30860000 { - compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; - reg = <0x30860000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MN_CLK_UART1_ROOT>, - <&clk IMX8MN_CLK_UART1_ROOT>; - clock-names = "ipg", "per"; - dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart3: serial@30880000 { - compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; - reg = <0x30880000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MN_CLK_UART3_ROOT>, - <&clk IMX8MN_CLK_UART3_ROOT>; - clock-names = "ipg", "per"; - dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart2: serial@30890000 { - compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; - reg = <0x30890000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MN_CLK_UART2_ROOT>, - <&clk IMX8MN_CLK_UART2_ROOT>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - crypto: crypto@30900000 { - compatible = "fsl,sec-v4.0"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x30900000 0x40000>; - ranges = <0 0x30900000 0x40000>; - interrupts = ; - clocks = <&clk IMX8MN_CLK_AHB>, - <&clk IMX8MN_CLK_IPG_ROOT>; - clock-names = "aclk", "ipg"; - - sec_jr0: jr0@1000 { - compatible = "fsl,sec-v4.0-job-ring"; - reg = <0x1000 0x1000>; - interrupts = ; - }; - - sec_jr1: jr1@2000 { - compatible = "fsl,sec-v4.0-job-ring"; - reg = <0x2000 0x1000>; - interrupts = ; - }; - - sec_jr2: jr2@3000 { - compatible = "fsl,sec-v4.0-job-ring"; - reg = <0x3000 0x1000>; - interrupts = ; - }; - }; - - i2c1: i2c@30a20000 { - compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x30a20000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MN_CLK_I2C1_ROOT>; - status = "disabled"; - }; - - i2c2: i2c@30a30000 { - compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x30a30000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MN_CLK_I2C2_ROOT>; - status = "disabled"; - }; - - i2c3: i2c@30a40000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c"; - reg = <0x30a40000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MN_CLK_I2C3_ROOT>; - status = "disabled"; - }; - - i2c4: i2c@30a50000 { - compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x30a50000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MN_CLK_I2C4_ROOT>; - status = "disabled"; - }; - - uart4: serial@30a60000 { - compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; - reg = <0x30a60000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MN_CLK_UART4_ROOT>, - <&clk IMX8MN_CLK_UART4_ROOT>; - clock-names = "ipg", "per"; - dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - usdhc1: mmc@30b40000 { - compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc"; - reg = <0x30b40000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MN_CLK_IPG_ROOT>, - <&clk IMX8MN_CLK_NAND_USDHC_BUS>, - <&clk IMX8MN_CLK_USDHC1_ROOT>; - clock-names = "ipg", "ahb", "per"; - fsl,tuning-start-tap = <20>; - fsl,tuning-step= <2>; - bus-width = <4>; - status = "disabled"; - }; - - usdhc2: mmc@30b50000 { - compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc"; - reg = <0x30b50000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MN_CLK_IPG_ROOT>, - <&clk IMX8MN_CLK_NAND_USDHC_BUS>, - <&clk IMX8MN_CLK_USDHC2_ROOT>; - clock-names = "ipg", "ahb", "per"; - fsl,tuning-start-tap = <20>; - fsl,tuning-step= <2>; - bus-width = <4>; - status = "disabled"; - }; - - usdhc3: mmc@30b60000 { - compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc"; - reg = <0x30b60000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MN_CLK_IPG_ROOT>, - <&clk IMX8MN_CLK_NAND_USDHC_BUS>, - <&clk IMX8MN_CLK_USDHC3_ROOT>; - clock-names = "ipg", "ahb", "per"; - fsl,tuning-start-tap = <20>; - fsl,tuning-step= <2>; - bus-width = <4>; - status = "disabled"; - }; - - sdma1: dma-controller@30bd0000 { - compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma"; - reg = <0x30bd0000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MN_CLK_SDMA1_ROOT>, - <&clk IMX8MN_CLK_SDMA1_ROOT>; - clock-names = "ipg", "ahb"; - #dma-cells = <3>; - fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; - }; - - fec1: ethernet@30be0000 { - compatible = "fsl,imx8mn-fec", "fsl,imx6sx-fec"; - reg = <0x30be0000 0x10000>; - interrupts = , - , - ; - clocks = <&clk IMX8MN_CLK_ENET1_ROOT>, - <&clk IMX8MN_CLK_ENET1_ROOT>, - <&clk IMX8MN_CLK_ENET_TIMER>, - <&clk IMX8MN_CLK_ENET_REF>, - <&clk IMX8MN_CLK_ENET_PHY_REF>; - clock-names = "ipg", "ahb", "ptp", - "enet_clk_ref", "enet_out"; - assigned-clocks = <&clk IMX8MN_CLK_ENET_AXI>, - <&clk IMX8MN_CLK_ENET_TIMER>, - <&clk IMX8MN_CLK_ENET_REF>, - <&clk IMX8MN_CLK_ENET_TIMER>; - assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>, - <&clk IMX8MN_SYS_PLL2_100M>, - <&clk IMX8MN_SYS_PLL2_125M>; - assigned-clock-rates = <0>, <0>, <125000000>, <100000000>; - fsl,num-tx-queues = <3>; - fsl,num-rx-queues = <3>; - status = "disabled"; - }; - - }; - - aips4: bus@32c00000 { - compatible = "simple-bus"; - reg = <0x32c00000 0x400000>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - usbotg1: usb@32e40000 { - compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb"; - reg = <0x32e40000 0x200>; - interrupts = ; - clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>; - clock-names = "usb1_ctrl_root_clk"; - assigned-clocks = <&clk IMX8MN_CLK_USB_BUS>; - assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>; - fsl,usbphy = <&usbphynop1>; - fsl,usbmisc = <&usbmisc1 0>; - status = "disabled"; - }; - - usbmisc1: usbmisc@32e40200 { - compatible = "fsl,imx8mn-usbmisc", "fsl,imx7d-usbmisc"; - #index-cells = <1>; - reg = <0x32e40200 0x200>; - }; - - usbotg2: usb@32e50000 { - compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb"; - reg = <0x32e50000 0x200>; - interrupts = ; - clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>; - clock-names = "usb1_ctrl_root_clk"; - assigned-clocks = <&clk IMX8MN_CLK_USB_BUS>, - <&clk IMX8MN_CLK_USB_CORE_REF>; - assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>, - <&clk IMX8MN_SYS_PLL1_100M>; - fsl,usbphy = <&usbphynop2>; - fsl,usbmisc = <&usbmisc2 0>; - status = "disabled"; - }; - - usbmisc2: usbmisc@32e50200 { - compatible = "fsl,imx8mn-usbmisc", "fsl,imx7d-usbmisc"; - #index-cells = <1>; - reg = <0x32e50200 0x200>; - }; - - }; - - dma_apbh: dma-controller@33000000 { - compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh"; - reg = <0x33000000 0x2000>; - interrupts = , - , - , - ; - interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; - #dma-cells = <1>; - dma-channels = <4>; - clocks = <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; - }; - - gpmi: nand-controller@33002000 { - compatible = "fsl,imx8mn-gpmi-nand", "fsl,imx7d-gpmi-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x33002000 0x2000>, <0x33004000 0x4000>; - reg-names = "gpmi-nand", "bch"; - interrupts = ; - interrupt-names = "bch"; - clocks = <&clk IMX8MN_CLK_NAND_ROOT>, - <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; - clock-names = "gpmi_io", "gpmi_bch_apb"; - dmas = <&dma_apbh 0>; - dma-names = "rx-tx"; - status = "disabled"; - }; - - gic: interrupt-controller@38800000 { - compatible = "arm,gic-v3"; - reg = <0x38800000 0x10000>, - <0x38880000 0xc0000>; - #interrupt-cells = <3>; - interrupt-controller; - interrupts = ; - }; - - ddrc: memory-controller@3d400000 { - compatible = "fsl,imx8mn-ddrc", "fsl,imx8m-ddrc"; - reg = <0x3d400000 0x400000>; - clock-names = "core", "pll", "alt", "apb"; - clocks = <&clk IMX8MN_CLK_DRAM_CORE>, - <&clk IMX8MN_DRAM_PLL>, - <&clk IMX8MN_CLK_DRAM_ALT>, - <&clk IMX8MN_CLK_DRAM_APB>; - }; - - ddr-pmu@3d800000 { - compatible = "fsl,imx8mn-ddr-pmu", "fsl,imx8m-ddr-pmu"; - reg = <0x3d800000 0x400000>; - interrupts = ; - }; - }; - - usbphynop1: usbphynop1 { - compatible = "usb-nop-xceiv"; - clocks = <&clk IMX8MN_CLK_USB_PHY_REF>; - assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>; - assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>; - clock-names = "main_clk"; - }; - - usbphynop2: usbphynop2 { - compatible = "usb-nop-xceiv"; - clocks = <&clk IMX8MN_CLK_USB_PHY_REF>; - assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>; - assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>; - clock-names = "main_clk"; - }; -}; diff --git a/sys/gnu/dts/arm64/freescale/imx8mq-evk.dts b/sys/gnu/dts/arm64/freescale/imx8mq-evk.dts deleted file mode 100644 index 94066d49d6e..00000000000 --- a/sys/gnu/dts/arm64/freescale/imx8mq-evk.dts +++ /dev/null @@ -1,529 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright 2017 NXP - * Copyright (C) 2017-2018 Pengutronix, Lucas Stach - */ - -/dts-v1/; - -#include "imx8mq.dtsi" - -/ { - model = "NXP i.MX8MQ EVK"; - compatible = "fsl,imx8mq-evk", "fsl,imx8mq"; - - chosen { - stdout-path = &uart1; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x00000000 0x40000000 0 0xc0000000>; - }; - - pcie0_refclk: pcie0-refclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - }; - - reg_usdhc2_vmmc: regulator-vsd-3v3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usdhc2>; - compatible = "regulator-fixed"; - regulator-name = "VSD_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - buck2_reg: regulator-buck2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_buck2>; - compatible = "regulator-gpio"; - regulator-name = "vdd_arm"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1000000>; - gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; - states = <1000000 0x0 - 900000 0x1>; - regulator-boot-on; - regulator-always-on; - }; - - ir-receiver { - compatible = "gpio-ir-receiver"; - gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ir>; - }; - - wm8524: audio-codec { - #sound-dai-cells = <0>; - compatible = "wlf,wm8524"; - wlf,mute-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; - }; - - sound-wm8524 { - compatible = "simple-audio-card"; - simple-audio-card,name = "wm8524-audio"; - simple-audio-card,format = "i2s"; - simple-audio-card,frame-master = <&cpudai>; - simple-audio-card,bitclock-master = <&cpudai>; - simple-audio-card,widgets = - "Line", "Left Line Out Jack", - "Line", "Right Line Out Jack"; - simple-audio-card,routing = - "Left Line Out Jack", "LINEVOUTL", - "Right Line Out Jack", "LINEVOUTR"; - - cpudai: simple-audio-card,cpu { - sound-dai = <&sai2>; - }; - - link_codec: simple-audio-card,codec { - sound-dai = <&wm8524>; - clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>; - }; - }; -}; - -&A53_0 { - cpu-supply = <&buck2_reg>; -}; - -&A53_1 { - cpu-supply = <&buck2_reg>; -}; - -&A53_2 { - cpu-supply = <&buck2_reg>; -}; - -&A53_3 { - cpu-supply = <&buck2_reg>; -}; - -&ddrc { - operating-points-v2 = <&ddrc_opp_table>; - - ddrc_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-25M { - opp-hz = /bits/ 64 <25000000>; - }; - - opp-100M { - opp-hz = /bits/ 64 <100000000>; - }; - - /* - * On imx8mq B0 PLL can't be bypassed so low bus is 166M - */ - opp-166M { - opp-hz = /bits/ 64 <166935483>; - }; - - opp-800M { - opp-hz = /bits/ 64 <800000000>; - }; - }; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy0>; - fsl,magic-packet; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - }; - }; -}; - -&gpio5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wifi_reset>; - - wl-reg-on { - gpio-hog; - gpios = <29 GPIO_ACTIVE_HIGH>; - output-high; - }; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pmic@8 { - compatible = "fsl,pfuze100"; - reg = <0x8>; - - regulators { - sw1a_reg: sw1ab { - regulator-min-microvolt = <825000>; - regulator-max-microvolt = <1100000>; - }; - - sw1c_reg: sw1c { - regulator-min-microvolt = <825000>; - regulator-max-microvolt = <1100000>; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - sw3a_reg: sw3ab { - regulator-min-microvolt = <825000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - sw4_reg: sw4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - }; - - snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-always-on; - }; - - vgen1_reg: vgen1 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen2_reg: vgen2 { - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <975000>; - regulator-always-on; - }; - - vgen3_reg: vgen3 { - regulator-min-microvolt = <1675000>; - regulator-max-microvolt = <1975000>; - regulator-always-on; - }; - - vgen4_reg: vgen4 { - regulator-min-microvolt = <1625000>; - regulator-max-microvolt = <1875000>; - regulator-always-on; - }; - - vgen5_reg: vgen5 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3625000>; - regulator-always-on; - }; - - vgen6_reg: vgen6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - }; - }; -}; - -&pcie0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie0>; - reset-gpio = <&gpio5 28 GPIO_ACTIVE_LOW>; - clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>, - <&clk IMX8MQ_CLK_PCIE1_AUX>, - <&clk IMX8MQ_CLK_PCIE1_PHY>, - <&pcie0_refclk>; - clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; - status = "okay"; -}; - -&pgc_gpu { - power-supply = <&sw1a_reg>; -}; - -&qspi0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_qspi>; - status = "okay"; - - n25q256a: flash@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; - compatible = "micron,n25q256a", "jedec,spi-nor"; - spi-max-frequency = <29000000>; - }; -}; - -&sai2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai2>; - assigned-clocks = <&clk IMX8MQ_AUDIO_PLL1_BYPASS>, <&clk IMX8MQ_CLK_SAI2>; - assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1>, <&clk IMX8MQ_AUDIO_PLL1_OUT>; - assigned-clock-rates = <0>, <24576000>; - status = "okay"; -}; - -&snvs_pwrkey { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&usb3_phy1 { - status = "okay"; -}; - -&usb_dwc3_1 { - dr_mode = "host"; - status = "okay"; -}; - -&usdhc1 { - assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>; - assigned-clock-rates = <400000000>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>; - vqmmc-supply = <&sw4_reg>; - bus-width = <8>; - non-removable; - no-sd; - no-sdio; - status = "okay"; -}; - -&usdhc2 { - assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>; - assigned-clock-rates = <200000000>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>; - cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_usdhc2_vmmc>; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl_buck2: vddarmgrp { - fsl,pins = < - MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x19 - >; - - }; - - pinctrl_fec1: fec1grp { - fsl,pins = < - MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 - MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23 - MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f - MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f - MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f - MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f - MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 - MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 - MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 - MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 - MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f - MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 - MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 - MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f - MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f - MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f - >; - }; - - pinctrl_ir: irgrp { - fsl,pins = < - MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x4f - >; - }; - - pinctrl_pcie0: pcie0grp { - fsl,pins = < - MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x76 - MX8MQ_IOMUXC_UART4_RXD_GPIO5_IO28 0x16 - >; - }; - - pinctrl_qspi: qspigrp { - fsl,pins = < - MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82 - MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 - MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 - MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 - MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 - MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 - - >; - }; - - pinctrl_reg_usdhc2: regusdhc2grpgpio { - fsl,pins = < - MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 - >; - }; - - pinctrl_sai2: sai2grp { - fsl,pins = < - MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 - MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 - MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6 - MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 - MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0xd6 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49 - MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 - MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 - MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 - MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 - MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 - MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 - MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 - MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 - MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 - MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 - MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83 - MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1-100grp { - fsl,pins = < - MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d - MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd - MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd - MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd - MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd - MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd - MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd - MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd - MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd - MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd - MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d - MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1-200grp { - fsl,pins = < - MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f - MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf - MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf - MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf - MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf - MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf - MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf - MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf - MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf - MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf - MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f - MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 - MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 - MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 - MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 - MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 - MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 - MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100grp { - fsl,pins = < - MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85 - MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5 - MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5 - MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5 - MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5 - MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5 - MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200grp { - fsl,pins = < - MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87 - MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7 - MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7 - MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7 - MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7 - MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7 - MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 - >; - }; - - pinctrl_wdog: wdog1grp { - fsl,pins = < - MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 - >; - }; - - pinctrl_wifi_reset: wifiresetgrp { - fsl,pins = < - MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29 0x16 - >; - }; -}; diff --git a/sys/gnu/dts/arm64/freescale/imx8mq-hummingboard-pulse.dts b/sys/gnu/dts/arm64/freescale/imx8mq-hummingboard-pulse.dts deleted file mode 100644 index bfd91c1ed6a..00000000000 --- a/sys/gnu/dts/arm64/freescale/imx8mq-hummingboard-pulse.dts +++ /dev/null @@ -1,264 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2018 Jon Nettleton - */ - -/dts-v1/; - -#include "dt-bindings/usb/pd.h" -#include "imx8mq-sr-som.dtsi" - -/ { - model = "SolidRun i.MX8MQ HummingBoard Pulse"; - compatible = "solidrun,hummingboard-pulse", "fsl,imx8mq"; - - chosen { - stdout-path = &uart1; - }; - - reg_usdhc2_vmmc: regulator-usdhc2-vmmc { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2_vmmc>; - regulator-name = "VSD_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio1 13 GPIO_ACTIVE_LOW>; - }; - - reg_v_5v0: regulator-v-5v0 { - compatible = "regulator-fixed"; - regulator-name = "v_5v0"; - regulator-max-microvolt = <5000000>; - regulator-min-microvolt = <5000000>; - regulator-always-on; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - clock-frequency = <100000>; - status = "okay"; - - typec_ptn5100: usb-typec@50 { - compatible = "nxp,ptn5110"; - reg = <0x50>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_typec>; - interrupt-parent = <&gpio1>; - interrupts = <6 IRQ_TYPE_LEVEL_LOW>; - - connector { - compatible = "usb-c-connector"; - label = "USB-C"; - data-role = "dual"; - power-role = "dual"; - try-power-role = "sink"; - source-pdos = ; - sink-pdos = ; - op-sink-microwatt = <9000000>; - - port { - typec1_dr_sw: endpoint { - remote-endpoint = <&usb1_drd_sw>; - }; - }; - }; - }; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - clock-frequency = <100000>; - status = "okay"; - - eeprom@57 { - compatible = "atmel,24c02"; - reg = <0x57>; - status = "okay"; - }; - - rtc@69 { - compatible = "abracon,ab1805"; - reg = <0x69>; - abracon,tc-diode = "schottky"; - abracon,tc-resistor = <3>; - }; -}; - -&uart2 { /* J35 header */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - assigned-clocks = <&clk IMX8MQ_CLK_UART2>; - assigned-clock-parents = <&clk IMX8MQ_CLK_25M>; - status = "okay"; -}; - -&uart3 { /* Mikrobus */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - assigned-clocks = <&clk IMX8MQ_CLK_UART3>; - assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>; - uart-has-rtscts; - status = "okay"; -}; - -&usdhc2 { - assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>; - assigned-clock-rates = <200000000>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; - cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_usdhc2_vmmc>; - status = "okay"; -}; - -&usb_dwc3_0 { - dr_mode = "otg"; - status = "okay"; - - port { - usb1_drd_sw: endpoint { - remote-endpoint = <&typec1_dr_sw>; - }; - }; -}; - -&usb_dwc3_1 { - dr_mode = "host"; - status = "okay"; -}; - -&usb3_phy0 { - status = "okay"; -}; - -&usb3_phy1 { - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_hog: hoggrp { - fsl,pins = < - /* MikroBus Analog */ - MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x41 - /* MikroBus Reset */ - MX8MQ_IOMUXC_SAI2_RXD0_GPIO4_IO23 0x41 - /* - * The following 2 pins need to be commented out and - * reconfigured to enable RTS/CTS on UART3 - */ - /* MikroBus PWM */ - MX8MQ_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x41 - /* MikroBus INT */ - MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x41 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f - MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000007f - MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000007f - >; - }; - - pinctrl_typec: typecgrp { - fsl,pins = < - MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15 0x16 - MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x17059 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49 - MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x49 - MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x49 - /* - * These pins are by default GPIO on the Mikro Bus - * Header. To use RTS/CTS on UART3 comment them out - * of the hoggrp and enable them here - */ - /* MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x49 */ - /* MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x49 */ - >; - }; - - pinctrl_usdhc2_gpio: usdhc2grpgpio { - fsl,pins = < - MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 - >; - }; - - pinctrl_usdhc2_vmmc: usdhc2vmmcgpio { - fsl,pins = < - MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x41 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 - MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 - MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 - MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 - MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 - MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 - MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2grp100mhz { - fsl,pins = < - MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8d - MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd - MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcd - MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcd - MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcd - MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd - MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2grp200mhz { - fsl,pins = < - MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f - MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xdf - MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xdf - MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xdf - MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xdf - MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xdf - MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 - >; - }; -}; diff --git a/sys/gnu/dts/arm64/freescale/imx8mq-librem5-devkit.dts b/sys/gnu/dts/arm64/freescale/imx8mq-librem5-devkit.dts deleted file mode 100644 index 764a4cb4e12..00000000000 --- a/sys/gnu/dts/arm64/freescale/imx8mq-librem5-devkit.dts +++ /dev/null @@ -1,824 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2018-2019 Purism SPC - */ - -/dts-v1/; - -#include "dt-bindings/input/input.h" -#include "dt-bindings/pwm/pwm.h" -#include "dt-bindings/usb/pd.h" -#include "imx8mq.dtsi" - -/ { - model = "Purism Librem 5 devkit"; - compatible = "purism,librem5-devkit", "fsl,imx8mq"; - - backlight_dsi: backlight-dsi { - compatible = "pwm-backlight"; - /* 200 Hz for the PAM2841 */ - pwms = <&pwm1 0 5000000>; - brightness-levels = <0 100>; - num-interpolated-steps = <100>; - /* Default brightness level (index into the array defined by */ - /* the "brightness-levels" property) */ - default-brightness-level = <0>; - power-supply = <®_22v4_p>; - }; - - chosen { - stdout-path = &uart1; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_keys>; - - btn1 { - label = "VOL_UP"; - gpios = <&gpio4 21 GPIO_ACTIVE_LOW>; - wakeup-source; - linux,code = ; - }; - - btn2 { - label = "VOL_DOWN"; - gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; - wakeup-source; - linux,code = ; - }; - - hp-det { - label = "HP_DET"; - gpios = <&gpio3 20 GPIO_ACTIVE_LOW>; - wakeup-source; - linux,code = ; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led1 { - label = "LED 1"; - gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - - pmic_osc: clock-pmic { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "pmic_osc"; - }; - - reg_1v8_p: regulator-1v8-p { - compatible = "regulator-fixed"; - regulator-name = "1v8_p"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <®_pwr_en>; - }; - - reg_2v8_p: regulator-2v8-p { - compatible = "regulator-fixed"; - regulator-name = "2v8_p"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - vin-supply = <®_pwr_en>; - }; - - reg_3v3_p: regulator-3v3-p { - compatible = "regulator-fixed"; - regulator-name = "3v3_p"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <®_pwr_en>; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - reg_5v_p: regulator-5v-p { - compatible = "regulator-fixed"; - regulator-name = "5v_p"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <®_pwr_en>; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - reg_22v4_p: regulator-22v4-p { - compatible = "regulator-fixed"; - regulator-name = "22v4_P"; - regulator-min-microvolt = <22400000>; - regulator-max-microvolt = <22400000>; - vin-supply = <®_pwr_en>; - }; - - reg_pwr_en: regulator-pwr-en { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwr_en>; - regulator-name = "PWR_EN"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - }; - - reg_usdhc2_vmmc: regulator-usdhc2-vmmc { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2_pwr>; - regulator-name = "VSD_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - }; - - vibrator { - compatible = "gpio-vibrator"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_haptic>; - enable-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>; - vcc-supply = <®_3v3_p>; - }; - - wifi_pwr_en: regulator-wifi-en { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wifi_pwr_en>; - regulator-name = "WIFI_EN"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - }; -}; - -&clk { - assigned-clocks = <&clk IMX8MQ_AUDIO_PLL1>, <&clk IMX8MQ_AUDIO_PLL2>; - assigned-clock-rates = <786432000>, <722534400>; -}; - -&dphy { - status = "okay"; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy0>; - fsl,magic-packet; - phy-supply = <®_3v3_p>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; - }; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pmic: pmic@4b { - compatible = "rohm,bd71837"; - reg = <0x4b>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - clocks = <&pmic_osc>; - clock-names = "osc"; - clock-output-names = "pmic_clk"; - interrupt-parent = <&gpio1>; - interrupts = <3 GPIO_ACTIVE_LOW>; - interrupt-names = "irq"; - rohm,reset-snvs-powered; - - regulators { - buck1_reg: BUCK1 { - regulator-name = "buck1"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - regulator-ramp-delay = <1250>; - rohm,dvs-run-voltage = <900000>; - rohm,dvs-idle-voltage = <850000>; - rohm,dvs-suspend-voltage = <800000>; - }; - - buck2_reg: BUCK2 { - regulator-name = "buck2"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - regulator-ramp-delay = <1250>; - rohm,dvs-run-voltage = <1000000>; - rohm,dvs-idle-voltage = <900000>; - }; - - buck3_reg: BUCK3 { - regulator-name = "buck3"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - rohm,dvs-run-voltage = <1000000>; - }; - - buck4_reg: BUCK4 { - regulator-name = "buck4"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - rohm,dvs-run-voltage = <1000000>; - }; - - buck5_reg: BUCK5 { - regulator-name = "buck5"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1350000>; - regulator-boot-on; - }; - - buck6_reg: BUCK6 { - regulator-name = "buck6"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; - - buck7_reg: BUCK7 { - regulator-name = "buck7"; - regulator-min-microvolt = <1605000>; - regulator-max-microvolt = <1995000>; - regulator-boot-on; - }; - - buck8_reg: BUCK8 { - regulator-name = "buck8"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-boot-on; - }; - - ldo1_reg: LDO1 { - regulator-name = "ldo1"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - /* leave on for snvs power button */ - regulator-always-on; - }; - - ldo2_reg: LDO2 { - regulator-name = "ldo2"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - regulator-boot-on; - /* leave on for snvs power button */ - regulator-always-on; - }; - - ldo3_reg: LDO3 { - regulator-name = "ldo3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; - - ldo4_reg: LDO4 { - regulator-name = "ldo4"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - }; - - ldo5_reg: LDO5 { - regulator-name = "ldo5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - ldo6_reg: LDO6 { - regulator-name = "ldo6"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - }; - - ldo7_reg: LDO7 { - regulator-name = "ldo7"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; - }; - }; - - typec_ptn5100: usb_typec@52 { - compatible = "nxp,ptn5110"; - reg = <0x52>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_typec>; - interrupt-parent = <&gpio3>; - interrupts = <1 IRQ_TYPE_LEVEL_LOW>; - - connector { - compatible = "usb-c-connector"; - label = "USB-C"; - data-role = "dual"; - power-role = "dual"; - try-power-role = "sink"; - source-pdos = ; - sink-pdos = ; - op-sink-microwatt = <10000000>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - usb_con_hs: endpoint { - remote-endpoint = <&typec_hs>; - }; - }; - - port@1 { - reg = <1>; - - usb_con_ss: endpoint { - remote-endpoint = <&typec_ss>; - }; - }; - }; - }; - }; - - rtc@68 { - compatible = "microcrystal,rv4162"; - reg = <0x68>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rtc>; - interrupt-parent = <&gpio4>; - interrupts = <29 IRQ_TYPE_LEVEL_LOW>; - }; - - charger@6b { /* bq25896 */ - compatible = "ti,bq25890"; - reg = <0x6b>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_charger>; - interrupt-parent = <&gpio3>; - interrupts = <25 IRQ_TYPE_EDGE_FALLING>; - ti,battery-regulation-voltage = <4192000>; /* 4.192V */ - ti,charge-current = <1600000>; /* 1.6A */ - ti,termination-current = <66000>; /* 66mA */ - ti,precharge-current = <130000>; /* 130mA */ - ti,minimum-sys-voltage = <3000000>; /* 3V */ - ti,boost-voltage = <5000000>; /* 5V */ - ti,boost-max-current = <50000>; /* 50mA */ - }; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - magnetometer@1e { - compatible = "st,lsm9ds1-magn"; - reg = <0x1e>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_imu>; - interrupt-parent = <&gpio3>; - interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; - vdd-supply = <®_3v3_p>; - vddio-supply = <®_3v3_p>; - }; - - touchscreen@5d { - compatible = "goodix,gt5688"; - reg = <0x5d>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ts>; - interrupt-parent = <&gpio3>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - reset-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; - irq-gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>; - touchscreen-size-x = <720>; - touchscreen-size-y = <1440>; - AVDD28-supply = <®_2v8_p>; - VDDIO-supply = <®_1v8_p>; - }; - - accel-gyro@6a { - compatible = "st,lsm9ds1-imu"; - reg = <0x6a>; - vdd-supply = <®_3v3_p>; - vddio-supply = <®_3v3_p>; - }; -}; - -&iomuxc { - pinctrl_bl: blgrp { - fsl,pins = < - MX8MQ_IOMUXC_GPIO1_IO01_PWM1_OUT 0x6 /* DSI_BL_PWM */ - >; - }; - - pinctrl_bt: btgrp { - fsl,pins = < - MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x16 /* nBT_DISABLE */ - MX8MQ_IOMUXC_NAND_DATA01_GPIO3_IO7 0x10 /* BT_HOST_WAKE */ - >; - }; - - pinctrl_charger: chargergrp { - fsl,pins = < - MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x80 /* CHRG_nINT */ - >; - }; - - pinctrl_fec1: fec1grp { - fsl,pins = < - MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 - MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 - MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f - MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f - MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f - MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f - MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 - MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 - MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 - MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 - MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f - MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 - MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 - MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f - MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 - MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x1f - >; - }; - - pinctrl_ts: tsgrp { - fsl,pins = < - MX8MQ_IOMUXC_NAND_ALE_GPIO3_IO0 0x16 /* TOUCH INT */ - MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19 /* TOUCH RST */ - >; - }; - - pinctrl_gpio_leds: gpioledgrp { - fsl,pins = < - MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x16 - >; - }; - - pinctrl_gpio_keys: gpiokeygrp { - fsl,pins = < - MX8MQ_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x16 - MX8MQ_IOMUXC_SAI2_RXC_GPIO4_IO22 0x16 - MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0x180 /* HP_DET */ - >; - }; - - pinctrl_haptic: hapticgrp { - fsl,pins = < - MX8MQ_IOMUXC_SPDIF_RX_GPIO5_IO4 0xc6 /* nHAPTIC */ - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000001f - MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000001f - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000001f - MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000001f - >; - }; - - pinctrl_imu: imugrp { - fsl,pins = < - MX8MQ_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x8 /* IMU_INT */ - >; - }; - - pinctrl_pmic: pmicgrp { - fsl,pins = < - MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x80 /* PMIC intr */ - >; - }; - - pinctrl_pwr_en: pwrengrp { - fsl,pins = < - MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x06 - >; - }; - - pinctrl_rtc: rtcgrp { - fsl,pins = < - MX8MQ_IOMUXC_SAI3_RXC_GPIO4_IO29 0x80 /* RTC intr */ - >; - }; - - pinctrl_typec: typecgrp { - fsl,pins = < - MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0x16 - MX8MQ_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x80 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49 - MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49 - MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49 - MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x49 - MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x49 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x49 - MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x49 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x49 - MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x49 - MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x49 - MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x49 - MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x49 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 - MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 - MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 - MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 - MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 - MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 - MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 - MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 - MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 - MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 - MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83 - MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1grp100mhz { - fsl,pins = < - MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d - MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd - MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd - MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd - MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd - MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd - MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd - MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd - MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd - MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd - MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d - MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1grp200mhz { - fsl,pins = < - MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f - MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf - MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf - MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf - MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf - MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf - MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf - MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf - MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf - MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf - MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f - MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 - >; - }; - - pinctrl_usdhc2_pwr: usdhc2grppwr { - fsl,pins = < - MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 - >; - }; - - pinctrl_usdhc2_gpio: usdhc2grpgpio { - fsl,pins = < - MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x80 /* WIFI_WAKE */ - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 - MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 - MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 - MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 - MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 - MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2grp100mhz { - fsl,pins = < - MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8d - MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd - MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcd - MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcd - MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcd - MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2grp200mhz { - fsl,pins = < - MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f - MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcf - MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcf - MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcf - MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcf - MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcf - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 - >; - }; - - pinctrl_wifi_pwr_en: wifipwrengrp { - fsl,pins = < - MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x06 - >; - }; - - pinctrl_wwan: wwangrp { - fsl,pins = < - MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x09 /* nWWAN_DISABLE */ - MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8 0x80 /* nWoWWAN */ - MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9 0x19 /* WWAN_RESET */ - >; - }; -}; - -&pgc_gpu { - power-supply = <&buck3_reg>; -}; - -&pgc_vpu { - power-supply = <&buck4_reg>; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_bl>; - status = "okay"; -}; - -&snvs_pwrkey { - status = "okay"; -}; - -&uart1 { /* console */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart3 { /* GNSS */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -&uart4 { /* BT */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>, <&pinctrl_bt>; - uart-has-rtscts; - status = "okay"; -}; - -&usb3_phy0 { - status = "okay"; -}; - -&usb3_phy1 { - vbus-supply = <®_5v_p>; - status = "okay"; -}; - -&usb_dwc3_0 { - #address-cells = <1>; - #size-cells = <0>; - dr_mode = "otg"; - status = "okay"; - - port@0 { - reg = <0>; - - typec_hs: endpoint { - remote-endpoint = <&usb_con_hs>; - }; - }; - - port@1 { - reg = <1>; - - typec_ss: endpoint { - remote-endpoint = <&usb_con_ss>; - }; - }; -}; - -&usb_dwc3_1 { - dr_mode = "host"; - status = "okay"; -}; - -&usdhc1 { - assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>; - assigned-clock-rates = <400000000>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&usdhc2 { - assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>; - assigned-clock-rates = <200000000>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>; - bus-width = <4>; - vmmc-supply = <®_usdhc2_vmmc>; - power-supply = <&wifi_pwr_en>; - non-removable; - disable-wp; - cap-sdio-irq; - keep-power-in-suspend; - wakeup-source; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/freescale/imx8mq-nitrogen.dts b/sys/gnu/dts/arm64/freescale/imx8mq-nitrogen.dts deleted file mode 100644 index 81d26929661..00000000000 --- a/sys/gnu/dts/arm64/freescale/imx8mq-nitrogen.dts +++ /dev/null @@ -1,407 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2018 Boundary Devices - */ - -/dts-v1/; - -#include -#include "imx8mq.dtsi" - -/ { - model = "Boundary Devices i.MX8MQ Nitrogen8M"; - compatible = "boundary,imx8mq-nitrogen8m", "fsl,imx8mq"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x00000000 0x40000000 0 0x80000000>; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_keys>; - - power { - label = "Power Button"; - gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - }; - - reg_vref_0v9: regulator-vref-0v9 { - compatible = "regulator-fixed"; - regulator-name = "vref-0v9"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - }; - - reg_vref_1v8: regulator-vref-1v8 { - compatible = "regulator-fixed"; - regulator-name = "vref-1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - reg_vref_2v5: regulator-vref-2v5 { - compatible = "regulator-fixed"; - regulator-name = "vref-2v5"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - }; - - reg_vref_3v3: regulator-vref-3v3 { - compatible = "regulator-fixed"; - regulator-name = "vref-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_vref_5v: regulator-vref-5v { - compatible = "regulator-fixed"; - regulator-name = "vref-5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; -}; - - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy0>; - fsl,magic-packet; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@4 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <4>; - interrupts-extended = <&gpio1 11 IRQ_TYPE_LEVEL_LOW>; - }; - }; -}; - -&i2c1 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - i2cmux@70 { - compatible = "nxp,pca9546"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1_pca9546>; - reg = <0x70>; - reset-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; - #address-cells = <1>; - #size-cells = <0>; - - i2c1a: i2c1@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - reg_arm_dram: regulator@60 { - compatible = "fcs,fan53555"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_arm_dram>; - reg = <0x60>; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - vsel-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>; - }; - }; - - i2c1b: i2c1@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - reg_dram_1p1v: regulator@60 { - compatible = "fcs,fan53555"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_dram_1p1v>; - reg = <0x60>; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - vsel-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>; - }; - }; - - i2c1c: i2c1@2 { - reg = <2>; - #address-cells = <1>; - #size-cells = <0>; - - reg_soc_gpu_vpu: regulator@60 { - compatible = "fcs,fan53555"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_soc_gpu_vpu>; - reg = <0x60>; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - vsel-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; - }; - }; - - i2c1d: i2c1@3 { - reg = <3>; - #address-cells = <1>; - #size-cells = <0>; - - rtc@68 { - compatible = "microcrystal,rv4162"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1d_rv4162>; - reg = <0x68>; - interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_LOW>; - wakeup-source; - }; - }; - }; -}; - -&uart1 { /* console */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - assigned-clocks = <&clk IMX8MQ_CLK_UART1>; - assigned-clock-parents = <&clk IMX8MQ_CLK_25M>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - assigned-clocks = <&clk IMX8MQ_CLK_UART2>; - assigned-clock-parents = <&clk IMX8MQ_CLK_25M>; - status = "okay"; -}; - -&usdhc1 { - assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>; - assigned-clock-rates = <400000000>; - bus-width = <8>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - non-removable; - vmmc-supply = <®_vref_1v8>; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_hog: hoggrp { - fsl,pins = < - /* J17 connector, odd */ - MX8MQ_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x19 /* Pin 19 */ - MX8MQ_IOMUXC_SAI1_RXC_GPIO4_IO1 0x19 /* Pin 21 */ - MX8MQ_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x19 /* Pin 23 */ - MX8MQ_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x19 /* Pin 25 */ - MX8MQ_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x19 /* Pin 27 */ - MX8MQ_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x19 /* Pin 29 */ - MX8MQ_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x19 /* Pin 31 */ - MX8MQ_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x19 /* Pin 33 */ - MX8MQ_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x19 /* Pin 35 */ - MX8MQ_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x19 /* Pin 39 */ - MX8MQ_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x19 /* Pin 41 */ - MX8MQ_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x19 /* Pin 43 */ - MX8MQ_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x19 /* Pin 45 */ - MX8MQ_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x19 /* Pin 47 */ - MX8MQ_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x19 /* Pin 49 */ - MX8MQ_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x19 /* Pin 51 */ - - /* J17 connector, even */ - MX8MQ_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x19 /* Pin 44 */ - MX8MQ_IOMUXC_SAI3_RXC_GPIO4_IO29 0x19 /* Pin 48 */ - MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 /* Pin 50 */ - MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x19 /* Pin 54 */ - MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19 /* Pin 56 */ - - /* J18 connector, odd */ - MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x19 /* Pin 41 */ - MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x19 /* Pin 43 */ - MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 /* Pin 45 */ - MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x19 /* Pin 47 */ - MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18 0x19 /* Pin 49 */ - MX8MQ_IOMUXC_NAND_DQS_GPIO3_IO14 0x19 /* Pin 53 */ - - /* J18 connector, even */ - MX8MQ_IOMUXC_NAND_ALE_GPIO3_IO0 0x19 /* Pin 32 */ - MX8MQ_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x19 /* Pin 36 */ - MX8MQ_IOMUXC_NAND_DATA00_GPIO3_IO6 0x19 /* Pin 38 */ - MX8MQ_IOMUXC_NAND_DATA01_GPIO3_IO7 0x19 /* Pin 40 */ - MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8 0x19 /* Pin 42 */ - MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9 0x19 /* Pin 44 */ - MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10 0x19 /* Pin 46 */ - - /* J13 Pin 2, WL_WAKE */ - MX8MQ_IOMUXC_SAI5_RXD2_GPIO3_IO23 0xd6 - /* J13 Pin 4, WL_IRQ, not needed for Silex */ - MX8MQ_IOMUXC_SAI5_RXD0_GPIO3_IO21 0xd6 - /* J13 pin 9, unused */ - MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19 - /* J13 Pin 41, BT_CLK_REQ */ - MX8MQ_IOMUXC_SAI5_RXD1_GPIO3_IO22 0xd6 - /* J13 Pin 42, BT_HOST_WAKE */ - MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25 0xd6 - - /* Clock for both CSI1 and CSI2 */ - MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x07 - /* test points */ - MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4 0xc1 /* TP87 */ - >; - }; - - pinctrl_fec1: fec1grp { - fsl,pins = < - MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 - MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23 - MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f - MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f - MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f - MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f - MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f - MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f - MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 - MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 - MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 - MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 - MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 - MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 - MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 - MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x59 - >; - }; - - pinctrl_gpio_keys: gpio-keysgrp { - fsl,pins = < - MX8MQ_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 - >; - }; - - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f - MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f - >; - }; - - pinctrl_i2c1_pca9546: i2c1-pca9546grp { - fsl,pins = < - MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x49 - >; - }; - - pinctrl_i2c1d_rv4162: i2c1d-rv4162grp { - fsl,pins = < - MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x49 - >; - }; - - pinctrl_reg_arm_dram: reg-arm-dramgrp { - fsl,pins = < - MX8MQ_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x16 - >; - }; - - pinctrl_reg_dram_1p1v: reg-dram-1p1vgrp { - fsl,pins = < - MX8MQ_IOMUXC_SD1_STROBE_GPIO2_IO11 0x16 - >; - }; - - pinctrl_reg_soc_gpu_vpu: reg-soc-gpu-vpugrp { - fsl,pins = < - MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x16 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x45 - MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x45 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x45 - MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x45 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 - MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 - MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 - MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 - MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 - MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 - MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 - MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 - MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 - MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 - MX8MQ_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41 - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { - fsl,pins = < - MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d - MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd - MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd - MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd - MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd - MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd - MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd - MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd - MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd - MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { - fsl,pins = < - MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f - MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf - MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf - MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf - MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf - MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf - MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf - MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf - MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf - MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 - >; - }; -}; diff --git a/sys/gnu/dts/arm64/freescale/imx8mq-phanbell.dts b/sys/gnu/dts/arm64/freescale/imx8mq-phanbell.dts deleted file mode 100644 index 3f2a489a4ad..00000000000 --- a/sys/gnu/dts/arm64/freescale/imx8mq-phanbell.dts +++ /dev/null @@ -1,376 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright 2017-2019 NXP - */ - -/dts-v1/; - -#include "imx8mq.dtsi" - -/ { - model = "Google i.MX8MQ Phanbell"; - compatible = "google,imx8mq-phanbell", "fsl,imx8mq"; - - chosen { - stdout-path = &uart1; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x00000000 0x40000000 0 0x40000000>; - }; - - pmic_osc: clock-pmic { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "pmic_osc"; - }; - - reg_usdhc2_vmmc: regulator-usdhc2-vmmc { - compatible = "regulator-fixed"; - regulator-name = "VSD_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&A53_0 { - cpu-supply = <&buck2>; -}; - -&A53_1 { - cpu-supply = <&buck2>; -}; - -&A53_2 { - cpu-supply = <&buck2>; -}; - -&A53_3 { - cpu-supply = <&buck2>; -}; - -&i2c1 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pmic: pmic@4b { - compatible = "rohm,bd71837"; - reg = <0x4b>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - #clock-cells = <0>; - clocks = <&pmic_osc>; - clock-output-names = "pmic_clk"; - interrupt-parent = <&gpio1>; - interrupts = <3 GPIO_ACTIVE_LOW>; - - regulators { - buck1: BUCK1 { - regulator-name = "buck1"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <1250>; - rohm,dvs-run-voltage = <900000>; - rohm,dvs-idle-voltage = <900000>; - rohm,dvs-suspend-voltage = <800000>; - }; - - buck2: BUCK2 { - regulator-name = "buck2"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1000000>; - regulator-boot-on; - regulator-always-on; - rohm,dvs-run-voltage = <1000000>; - rohm,dvs-idle-voltage = <900000>; - }; - - buck3: BUCK3 { - regulator-name = "buck3"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - rohm,dvs-run-voltage = <900000>; - }; - - buck4: BUCK4 { - regulator-name = "buck4"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - regulator-always-on; - rohm,dvs-run-voltage = <900000>; - }; - - buck5: BUCK5 { - regulator-name = "buck5"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1350000>; - regulator-boot-on; - regulator-always-on; - }; - - buck6: BUCK6 { - regulator-name = "buck6"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - buck7: BUCK7 { - regulator-name = "buck7"; - regulator-min-microvolt = <1605000>; - regulator-max-microvolt = <1995000>; - regulator-boot-on; - regulator-always-on; - }; - - buck8: BUCK8 { - regulator-name = "buck8"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1: LDO1 { - regulator-name = "ldo1"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo2: LDO2 { - regulator-name = "ldo2"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo3: LDO3 { - regulator-name = "ldo3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo4: LDO4 { - regulator-name = "ldo4"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo5: LDO5 { - regulator-name = "ldo5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo6: LDO6 { - regulator-name = "ldo6"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo7: LDO7 { - regulator-name = "ldo7"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; - bus-width = <4>; - cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_usdhc2_vmmc>; - status = "okay"; -}; - -&usb3_phy0 { - status = "okay"; -}; - -&usb_dwc3_0 { - dr_mode = "otg"; - status = "okay"; -}; - -&usb3_phy1 { - status = "okay"; -}; - -&usb_dwc3_1 { - dr_mode = "host"; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f - MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f - >; - }; - - pinctrl_pmic: pmicirq { - fsl,pins = < - MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49 - MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 - MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 - MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 - MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 - MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 - MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 - MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 - MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 - MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 - MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 - MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83 - MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1grp100mhz { - fsl,pins = < - MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85 - MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5 - MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc5 - MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc5 - MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc5 - MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc5 - MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc5 - MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc5 - MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc5 - MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc5 - MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x85 - MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1grp200mhz { - fsl,pins = < - MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87 - MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7 - MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc7 - MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc7 - MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc7 - MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc7 - MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc7 - MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc7 - MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc7 - MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc7 - MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x87 - MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 - >; - }; - - pinctrl_usdhc2_gpio: usdhc2grpgpio { - fsl,pins = < - MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 - MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 - MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 - MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 - MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 - MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 - MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 - MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2grp100mhz { - fsl,pins = < - MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85 - MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5 - MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5 - MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5 - MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5 - MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5 - MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2grp200mhz { - fsl,pins = < - MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87 - MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7 - MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7 - MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7 - MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7 - MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7 - MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 - >; - }; -}; diff --git a/sys/gnu/dts/arm64/freescale/imx8mq-pico-pi.dts b/sys/gnu/dts/arm64/freescale/imx8mq-pico-pi.dts deleted file mode 100644 index 59da96b7143..00000000000 --- a/sys/gnu/dts/arm64/freescale/imx8mq-pico-pi.dts +++ /dev/null @@ -1,417 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2018 Wandboard, Org. - * Copyright 2017 NXP - * - * Author: Richard Hu - */ - -/dts-v1/; - -#include "imx8mq.dtsi" - -/ { - model = "TechNexion PICO-PI-8M"; - compatible = "technexion,pico-pi-imx8m", "fsl,imx8mq"; - - chosen { - stdout-path = &uart1; - }; - - pmic_osc: clock-pmic { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "pmic_osc"; - }; - - reg_usb_otg_vbus: regulator-usb-otg-vbus { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_otg_vbus>; - compatible = "regulator-fixed"; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 14 GPIO_ACTIVE_LOW>; - }; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1 &pinctrl_enet_3v3>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy0>; - fsl,magic-packet; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; - }; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pmic: pmic@4b { - reg = <0x4b>; - compatible = "rohm,bd71837"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - clocks = <&pmic_osc>; - clock-names = "osc"; - clock-output-names = "pmic_clk"; - interrupt-parent = <&gpio1>; - interrupts = <3 GPIO_ACTIVE_LOW>; - interrupt-names = "irq"; - - regulators { - buck1: BUCK1 { - regulator-name = "buck1"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - regulator-ramp-delay = <1250>; - rohm,dvs-run-voltage = <900000>; - rohm,dvs-idle-voltage = <850000>; - rohm,dvs-suspend-voltage = <800000>; - }; - - buck2: BUCK2 { - regulator-name = "buck2"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - regulator-ramp-delay = <1250>; - rohm,dvs-run-voltage = <1000000>; - rohm,dvs-idle-voltage = <900000>; - }; - - buck3: BUCK3 { - regulator-name = "buck3"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - rohm,dvs-run-voltage = <1000000>; - }; - - buck4: BUCK4 { - regulator-name = "buck4"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - rohm,dvs-run-voltage = <1000000>; - }; - - buck5: BUCK5 { - regulator-name = "buck5"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1350000>; - regulator-boot-on; - }; - - buck6: BUCK6 { - regulator-name = "buck6"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; - - buck7: BUCK7 { - regulator-name = "buck7"; - regulator-min-microvolt = <1605000>; - regulator-max-microvolt = <1995000>; - regulator-boot-on; - }; - - buck8: BUCK8 { - regulator-name = "buck8"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-boot-on; - }; - - ldo1: LDO1 { - regulator-name = "ldo1"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo2: LDO2 { - regulator-name = "ldo2"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo3: LDO3 { - regulator-name = "ldo3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; - - ldo4: LDO4 { - regulator-name = "ldo4"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - }; - - ldo5: LDO5 { - regulator-name = "ldo5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; - - ldo6: LDO6 { - regulator-name = "ldo6"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - }; - - ldo7: LDO7 { - regulator-name = "ldo7"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; - }; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&uart1 { /* console */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&usdhc1 { - assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>; - assigned-clock-rates = <400000000>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&usdhc2 { - assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>; - assigned-clock-rates = <200000000>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; - bus-width = <4>; - cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&usb3_phy0 { - status = "okay"; -}; - -&usb3_phy1 { - status = "okay"; -}; - -&usb_dwc3_1 { - dr_mode = "host"; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl_enet_3v3: enet3v3grp { - fsl,pins = < - MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x19 - >; - }; - - pinctrl_fec1: fec1grp { - fsl,pins = < - MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 - MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23 - MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f - MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f - MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f - MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f - MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 - MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 - MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 - MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 - MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f - MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 - MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 - MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f - MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f - MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f - MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f - >; - }; - - pinctrl_otg_vbus: otgvbusgrp { - fsl,pins = < - MX8MQ_IOMUXC_NAND_DQS_GPIO3_IO14 0x19 /* USB OTG VBUS Enable */ - >; - }; - - pinctrl_pmic: pmicirq { - fsl,pins = < - MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49 - MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49 - MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49 - MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x49 - MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x49 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 - MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 - MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 - MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 - MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 - MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 - MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 - MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 - MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 - MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 - MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83 - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1grp100mhz { - fsl,pins = < - MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85 - MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5 - MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc5 - MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc5 - MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc5 - MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc5 - MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc5 - MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc5 - MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc5 - MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc5 - MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x85 - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1grp200mhz { - fsl,pins = < - MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87 - MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7 - MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc7 - MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc7 - MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc7 - MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc7 - MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc7 - MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc7 - MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc7 - MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc7 - MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x87 - >; - }; - - pinctrl_usdhc2_gpio: usdhc2grpgpio { - fsl,pins = < - MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 - MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 - MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 - MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 - MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 - MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 - MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2grp100mhz { - fsl,pins = < - MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85 - MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5 - MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5 - MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5 - MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5 - MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5 - MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2grp200mhz { - fsl,pins = < - MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87 - MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7 - MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7 - MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7 - MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7 - MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7 - MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 - >; - }; -}; diff --git a/sys/gnu/dts/arm64/freescale/imx8mq-pinfunc.h b/sys/gnu/dts/arm64/freescale/imx8mq-pinfunc.h deleted file mode 100644 index b94b02080a3..00000000000 --- a/sys/gnu/dts/arm64/freescale/imx8mq-pinfunc.h +++ /dev/null @@ -1,623 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2016 Freescale Semiconductor, Inc. - * Copyright 2017 NXP - */ - -#ifndef __DTS_IMX8MQ_PINFUNC_H -#define __DTS_IMX8MQ_PINFUNC_H - -/* - * The pin function ID is a tuple of - * - */ - -#define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO02_GPIO1_IO2 0x030 0x298 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x030 0x298 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x030 0x298 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO02_SJC_DE_B 0x030 0x298 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x034 0x29C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x034 0x29C 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x034 0x29C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO03_ANAMIX_XTAL_OK 0x034 0x29C 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO03_SJC_DONE 0x034 0x29C 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x038 0x2A0 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x038 0x2A0 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x038 0x2A0 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO04_ANAMIX_XTAL_OK_LV 0x038 0x2A0 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO04_USDHC1_TEST_TRIG 0x038 0x2A0 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x03C 0x2A4 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO05_M4_NMI 0x03C 0x2A4 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_PMIC_READY 0x03C 0x2A4 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_INT_BOOT 0x03C 0x2A4 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO05_USDHC2_TEST_TRIG 0x03C 0x2A4 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x040 0x2A8 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO06_ENET1_MDC 0x040 0x2A8 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x040 0x2A8 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO06_CCMSRCGPCMIX_EXT_CLK3 0x040 0x2A8 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO06_ECSPI1_TEST_TRIG 0x040 0x2A8 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x044 0x2AC 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO07_ENET1_MDIO 0x044 0x2AC 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO07_USDHC1_WP 0x044 0x2AC 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO07_CCMSRCGPCMIX_EXT_CLK4 0x044 0x2AC 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO07_ECSPI2_TEST_TRIG 0x044 0x2AC 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x048 0x2B0 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x048 0x2B0 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x048 0x2B0 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO08_CCMSRCGPCMIX_WAIT 0x048 0x2B0 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO08_QSPI_TEST_TRIG 0x048 0x2B0 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x04C 0x2B4 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x04C 0x2B4 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x04C 0x2B4 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO09_CCMSRCGPCMIX_STOP 0x04C 0x2B4 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO09_RAWNAND_TEST_TRIG 0x04C 0x2B4 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x050 0x2B8 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x050 0x2B8 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO10_OCOTP_CTRL_WRAPPER_FUSE_LATCHED 0x050 0x2B8 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x054 0x2BC 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x054 0x2BC 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_PMIC_READY 0x054 0x2BC 0x4BC 0x5 0x1 -#define MX8MQ_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_OUT0 0x054 0x2BC 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO11_CAAM_WRAPPER_RNG_OSC_OBS 0x054 0x2BC 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x058 0x2C0 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x058 0x2C0 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x058 0x2C0 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO12_CCMSRCGPCMIX_OUT1 0x058 0x2C0 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO12_CSU_CSU_ALARM_AUT0 0x058 0x2C0 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x05C 0x2C4 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x05C 0x2C4 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO13_PWM2_OUT 0x05C 0x2C4 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO13_CCMSRCGPCMIX_OUT2 0x05C 0x2C4 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO13_CSU_CSU_ALARM_AUT1 0x05C 0x2C4 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x060 0x2C8 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x060 0x2C8 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO14_PWM3_OUT 0x060 0x2C8 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x060 0x2C8 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO14_CSU_CSU_ALARM_AUT2 0x060 0x2C8 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x064 0x2CC 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x064 0x2CC 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO15_PWM4_OUT 0x064 0x2CC 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x064 0x2CC 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO15_CSU_CSU_INT_DEB 0x064 0x2CC 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x068 0x2D0 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ENET_MDC_GPIO1_IO16 0x068 0x2D0 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x06C 0x2D4 0x4C0 0x0 0x1 -#define MX8MQ_IOMUXC_ENET_MDIO_GPIO1_IO17 0x06C 0x2D4 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x070 0x2D8 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ENET_TD3_GPIO1_IO18 0x070 0x2D8 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x074 0x2DC 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x074 0x2DC 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_ENET_TD2_GPIO1_IO19 0x074 0x2DC 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x078 0x2E0 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ENET_TD1_GPIO1_IO20 0x078 0x2E0 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x07C 0x2E4 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ENET_TD0_GPIO1_IO21 0x07C 0x2E4 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x080 0x2E8 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x080 0x2E8 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x084 0x2EC 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ENET_TXC_ENET1_TX_ER 0x084 0x2EC 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_ENET_TXC_GPIO1_IO23 0x084 0x2EC 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x088 0x2F0 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x088 0x2F0 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x08C 0x2F4 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ENET_RXC_ENET1_RX_ER 0x08C 0x2F4 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_ENET_RXC_GPIO1_IO25 0x08C 0x2F4 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x090 0x2F8 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ENET_RD0_GPIO1_IO26 0x090 0x2F8 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x094 0x2FC 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ENET_RD1_GPIO1_IO27 0x094 0x2FC 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x098 0x300 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ENET_RD2_GPIO1_IO28 0x098 0x300 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x09C 0x304 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ENET_RD3_GPIO1_IO29 0x09C 0x304 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x0A0 0x308 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD1_CLK_GPIO2_IO0 0x0A0 0x308 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0x0A4 0x30C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD1_CMD_GPIO2_IO1 0x0A4 0x30C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0A8 0x310 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD1_DATA0_GPIO2_IO2 0x0A8 0x31 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0AC 0x314 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD1_DATA1_GPIO2_IO3 0x0AC 0x314 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0B0 0x318 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD1_DATA2_GPIO2_IO4 0x0B0 0x318 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x0B4 0x31C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD1_DATA3_GPIO2_IO5 0x0B4 0x31C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x0B8 0x320 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD1_DATA4_GPIO2_IO6 0x0B8 0x320 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x0BC 0x324 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD1_DATA5_GPIO2_IO7 0x0BC 0x324 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x0C0 0x328 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD1_DATA6_GPIO2_IO8 0x0C0 0x328 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x0C4 0x32C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD1_DATA7_GPIO2_IO9 0x0C4 0x32C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x0C8 0x330 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x0C8 0x330 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x0CC 0x334 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD1_STROBE_GPIO2_IO11 0x0CC 0x334 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0D0 0x338 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x0D0 0x338 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x0D4 0x33C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD2_CLK_GPIO2_IO13 0x0D4 0x33C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD2_CLK_CCMSRCGPCMIX_OBSERVE0 0x0D4 0x33C 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SD2_CLK_OBSERVE_MUX_OUT0 0x0D4 0x33C 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0x0D8 0x340 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD2_CMD_GPIO2_IO14 0x0D8 0x340 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD2_CMD_CCMSRCGPCMIX_OBSERVE1 0x0D8 0x340 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SD2_CMD_OBSERVE_MUX_OUT1 0x0D8 0x340 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0DC 0x344 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD2_DATA0_GPIO2_IO15 0x0DC 0x344 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD2_DATA0_CCMSRCGPCMIX_OBSERVE2 0x0DC 0x344 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SD2_DATA0_OBSERVE_MUX_OUT2 0x0DC 0x344 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0E0 0x348 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD2_DATA1_GPIO2_IO16 0x0E0 0x348 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD2_DATA1_CCMSRCGPCMIX_WAIT 0x0E0 0x348 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SD2_DATA1_OBSERVE_MUX_OUT3 0x0E0 0x348 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0E4 0x34C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD2_DATA2_GPIO2_IO17 0x0E4 0x34C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD2_DATA2_CCMSRCGPCMIX_STOP 0x0E4 0x34C 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SD2_DATA2_OBSERVE_MUX_OUT4 0x0E4 0x34C 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0E8 0x350 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD2_DATA3_GPIO2_IO18 0x0E8 0x350 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD2_DATA3_CCMSRCGPCMIX_EARLY_RESET 0x0E8 0x350 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x0EC 0x354 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x0EC 0x354 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD2_RESET_B_CCMSRCGPCMIX_SYSTEM_RESET 0x0EC 0x354 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SD2_WP_USDHC2_WP 0x0F0 0x358 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x0F0 0x358 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD2_WP_SIM_M_HMASTLOCK 0x0F0 0x358 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_NAND_ALE_RAWNAND_ALE 0x0F4 0x35C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x0F4 0x35C 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_NAND_ALE_GPIO3_IO0 0x0F4 0x35C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_NAND_ALE_SIM_M_HPROT0 0x0F4 0x35C 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x0F8 0x360 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x0F8 0x360 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x0F8 0x360 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_NAND_CE0_B_SIM_M_HPROT1 0x0F8 0x360 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x0FC 0x364 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x0FC 0x364 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x0FC 0x364 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_NAND_CE1_B_SIM_M_HPROT2 0x0FC 0x364 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x100 0x368 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x100 0x368 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x100 0x368 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_NAND_CE2_B_SIM_M_HPROT3 0x100 0x368 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x104 0x36C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x104 0x36C 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x104 0x36C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_NAND_CE3_B_SIM_M_HADDR0 0x104 0x36C 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_NAND_CLE_RAWNAND_CLE 0x108 0x370 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_NAND_CLE_QSPI_B_SCLK 0x108 0x370 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x108 0x370 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_NAND_CLE_SIM_M_HADDR1 0x108 0x370 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x10C 0x374 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x10C 0x374 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_NAND_DATA00_GPIO3_IO6 0x10C 0x374 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_NAND_DATA00_SIM_M_HADDR2 0x10C 0x374 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x110 0x378 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x110 0x378 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_NAND_DATA01_GPIO3_IO7 0x110 0x378 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_NAND_DATA01_SIM_M_HADDR3 0x110 0x378 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x114 0x37C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x114 0x37C 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8 0x114 0x37C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_NAND_DATA02_SIM_M_HADDR4 0x114 0x37C 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x118 0x380 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x118 0x380 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9 0x118 0x380 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_NAND_DATA03_SIM_M_HADDR5 0x118 0x380 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x11C 0x384 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x11C 0x384 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10 0x11C 0x384 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_NAND_DATA04_SIM_M_HADDR6 0x11C 0x384 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x120 0x388 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x120 0x388 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x120 0x388 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_NAND_DATA05_SIM_M_HADDR7 0x120 0x388 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x124 0x38C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x124 0x38C 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0x124 0x38C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_NAND_DATA06_SIM_M_HADDR8 0x124 0x38C 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x128 0x390 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x128 0x390 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_NAND_DATA07_GPIO3_IO13 0x128 0x390 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_NAND_DATA07_SIM_M_HADDR9 0x128 0x390 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_NAND_DQS_RAWNAND_DQS 0x12C 0x394 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_NAND_DQS_QSPI_A_DQS 0x12C 0x394 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_NAND_DQS_GPIO3_IO14 0x12C 0x394 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_NAND_DQS_SIM_M_HADDR10 0x12C 0x394 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x130 0x398 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_NAND_RE_B_QSPI_B_DQS 0x130 0x398 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15 0x130 0x398 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_NAND_RE_B_SIM_M_HADDR11 0x130 0x398 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x134 0x39C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16 0x134 0x39C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_NAND_READY_B_SIM_M_HADDR12 0x134 0x39C 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x138 0x3A0 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17 0x138 0x3A0 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_NAND_WE_B_SIM_M_HADDR13 0x138 0x3A0 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x13C 0x3A4 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18 0x13C 0x3A4 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_NAND_WP_B_SIM_M_HADDR14 0x13C 0x3A4 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x140 0x3A8 0x4E4 0x0 0x0 -#define MX8MQ_IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x140 0x3A8 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x140 0x3A8 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x144 0x3AC 0x4D0 0x0 0x0 -#define MX8MQ_IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x144 0x3AC 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0x144 0x3AC 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x148 0x3B0 0x4D4 0x0 0x0 -#define MX8MQ_IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x148 0x3B0 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x148 0x3B0 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x14C 0x3B4 0x4D8 0x0 0x0 -#define MX8MQ_IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x14C 0x3B4 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x14C 0x3B4 0x4CC 0x2 0x0 -#define MX8MQ_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x14C 0x3B4 0x4EC 0x3 0x0 -#define MX8MQ_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x14C 0x3B4 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x150 0x3B8 0x4DC 0x0 0x0 -#define MX8MQ_IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x150 0x3B8 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x150 0x3B8 0x4CC 0x2 0x1 -#define MX8MQ_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x150 0x3B8 0x4E8 0x3 0x0 -#define MX8MQ_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x150 0x3B8 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x154 0x3BC 0x4E0 0x0 0x0 -#define MX8MQ_IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x154 0x3BC 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x154 0x3BC 0x4CC 0x2 0x2 -#define MX8MQ_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x154 0x3BC 0x000 0x3 0x0 -#define MX8MQ_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x154 0x3BC 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI5_MCLK_SAI5_MCLK 0x158 0x3C0 0x52C 0x0 0x0 -#define MX8MQ_IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x158 0x3C0 0x4C8 0x1 0x0 -#define MX8MQ_IOMUXC_SAI5_MCLK_SAI4_MCLK 0x158 0x3C0 0x000 0x2 0x0 -#define MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x158 0x3C0 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI5_MCLK_CCMSRCGPCMIX_TESTER_ACK 0x158 0x3C0 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x15C 0x3C4 0x4C4 0x0 0x0 -#define MX8MQ_IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x15C 0x3C4 0x4E4 0x1 0x1 -#define MX8MQ_IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x15C 0x3C4 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x15C 0x3C4 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_RXFS_SIM_M_HADDR15 0x15C 0x3C4 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x160 0x3C8 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x160 0x3C8 0x4D0 0x1 0x1 -#define MX8MQ_IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x160 0x3C8 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_RXC_GPIO4_IO1 0x160 0x3C8 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_RXC_SIM_M_HADDR16 0x160 0x3C8 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x164 0x3CC 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x164 0x3CC 0x4D4 0x1 0x1 -#define MX8MQ_IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x164 0x3CC 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x164 0x3CC 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD0_CCMSRCGPCMIX_BOOT_CFG0 0x164 0x3CC 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD0_SIM_M_HADDR17 0x164 0x3CC 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x168 0x3D0 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x168 0x3D0 0x4D8 0x1 0x1 -#define MX8MQ_IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x168 0x3D0 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x168 0x3D0 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD1_CCMSRCGPCMIX_BOOT_CFG1 0x168 0x3D0 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD1_SIM_M_HADDR18 0x168 0x3D0 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x16C 0x3D4 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x16C 0x3D4 0x4DC 0x1 0x1 -#define MX8MQ_IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x16C 0x3D4 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x16C 0x3D4 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD2_CCMSRCGPCMIX_BOOT_CFG2 0x16C 0x3D4 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD2_SIM_M_HADDR19 0x16C 0x3D4 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x170 0x3D8 0x4E0 0x0 0x1 -#define MX8MQ_IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x170 0x3D8 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x170 0x3D8 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x170 0x3D8 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD3_CCMSRCGPCMIX_BOOT_CFG3 0x170 0x3D8 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD3_SIM_M_HADDR20 0x170 0x3D8 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x174 0x3DC 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x174 0x3DC 0x51C 0x1 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x174 0x3DC 0x510 0x2 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x174 0x3DC 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x174 0x3DC 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD4_CCMSRCGPCMIX_BOOT_CFG4 0x174 0x3DC 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD4_SIM_M_HADDR21 0x174 0x3DC 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x178 0x3E0 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x178 0x3E0 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x178 0x3E0 0x514 0x2 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x178 0x3E0 0x4C4 0x3 0x1 -#define MX8MQ_IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x178 0x3E0 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x178 0x3E0 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD5_CCMSRCGPCMIX_BOOT_CFG5 0x178 0x3E0 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD5_SIM_M_HADDR22 0x178 0x3E0 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x17C 0x3E4 0x520 0x0 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x17C 0x3E4 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x17C 0x3E4 0x518 0x2 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x17C 0x3E4 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x17C 0x3E4 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD6_CCMSRCGPCMIX_BOOT_CFG6 0x17C 0x3E4 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD6_SIM_M_HADDR23 0x17C 0x3E4 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x180 0x3E8 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD7_SAI6_MCLK 0x180 0x3E8 0x530 0x1 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x180 0x3E8 0x4CC 0x2 0x4 -#define MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x180 0x3E8 0x000 0x3 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x180 0x3E8 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x180 0x3E8 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD7_CCMSRCGPCMIX_BOOT_CFG7 0x180 0x3E8 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD7_SIM_M_HADDR24 0x180 0x3E8 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x184 0x3EC 0x4CC 0x0 0x3 -#define MX8MQ_IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x184 0x3EC 0x4EC 0x1 0x1 -#define MX8MQ_IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x184 0x3EC 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x184 0x3EC 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_TXFS_SIM_M_HADDR25 0x184 0x3EC 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x188 0x3F0 0x4C8 0x0 0x1 -#define MX8MQ_IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x188 0x3F0 0x4E8 0x1 0x1 -#define MX8MQ_IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x188 0x3F0 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_TXC_GPIO4_IO11 0x188 0x3F0 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_TXC_SIM_M_HADDR26 0x188 0x3F0 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x18C 0x3F4 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x18C 0x3F4 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x18C 0x3F4 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x18C 0x3F4 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD0_CCMSRCGPCMIX_BOOT_CFG8 0x18C 0x3F4 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD0_SIM_M_HADDR27 0x18C 0x3F4 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x190 0x3F8 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x190 0x3F8 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x190 0x3F8 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x190 0x3F8 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD1_CCMSRCGPCMIX_BOOT_CFG9 0x190 0x3F8 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD1_SIM_M_HADDR28 0x190 0x3F8 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x194 0x3FC 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x194 0x3FC 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x194 0x3FC 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x194 0x3FC 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD2_CCMSRCGPCMIX_BOOT_CFG10 0x194 0x3FC 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD2_SIM_M_HADDR29 0x194 0x3FC 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x198 0x400 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x198 0x400 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x198 0x400 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x198 0x400 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD3_CCMSRCGPCMIX_BOOT_CFG11 0x198 0x400 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD3_SIM_M_HADDR30 0x198 0x400 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x19C 0x404 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x19C 0x404 0x510 0x1 0x1 -#define MX8MQ_IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x19C 0x404 0x51C 0x2 0x1 -#define MX8MQ_IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x19C 0x404 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x19C 0x404 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD4_CCMSRCGPCMIX_BOOT_CFG12 0x19C 0x404 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD4_SIM_M_HADDR31 0x19C 0x404 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x1A0 0x408 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x1A0 0x408 0x514 0x1 0x1 -#define MX8MQ_IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x1A0 0x408 0x000 0x2 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x1A0 0x408 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x1A0 0x408 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD5_CCMSRCGPCMIX_BOOT_CFG13 0x1A0 0x408 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD5_SIM_M_HBURST0 0x1A0 0x408 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x1A4 0x40C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x1A4 0x40C 0x518 0x1 0x1 -#define MX8MQ_IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x1A4 0x40C 0x520 0x2 0x1 -#define MX8MQ_IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x1A4 0x40C 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x1A4 0x40C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD6_CCMSRCGPCMIX_BOOT_CFG14 0x1A4 0x40C 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD6_SIM_M_HBURST1 0x1A4 0x40C 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x1A8 0x410 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD7_SAI6_MCLK 0x1A8 0x410 0x530 0x1 0x1 -#define MX8MQ_IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x1A8 0x410 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x1A8 0x410 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD7_CCMSRCGPCMIX_BOOT_CFG15 0x1A8 0x410 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD7_SIM_M_HBURST2 0x1A8 0x410 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_MCLK_SAI1_MCLK 0x1AC 0x414 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI1_MCLK_SAI5_MCLK 0x1AC 0x414 0x52C 0x1 0x1 -#define MX8MQ_IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x1AC 0x414 0x4C8 0x2 0x2 -#define MX8MQ_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x1AC 0x414 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_MCLK_SIM_M_HRESP 0x1AC 0x414 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x1B0 0x418 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x1B0 0x418 0x4EC 0x1 0x2 -#define MX8MQ_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x1B0 0x418 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI2_RXFS_SIM_M_HSIZE0 0x1B0 0x418 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x1B4 0x41C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x1B4 0x41C 0x4E8 0x1 0x2 -#define MX8MQ_IOMUXC_SAI2_RXC_GPIO4_IO22 0x1B4 0x41C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI2_RXC_SIM_M_HSIZE1 0x1B4 0x41C 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x1B8 0x420 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x1B8 0x420 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI2_RXD0_GPIO4_IO23 0x1B8 0x420 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI2_RXD0_SIM_M_HSIZE2 0x1B8 0x420 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x1BC 0x424 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x1BC 0x424 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x1BC 0x424 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI2_TXFS_SIM_M_HWRITE 0x1BC 0x424 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x1C0 0x428 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x1C0 0x428 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI2_TXC_GPIO4_IO25 0x1C0 0x428 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI2_TXC_SIM_M_HREADYOUT 0x1C0 0x428 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x1C4 0x42C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x1C4 0x42C 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x1C4 0x42C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI2_TXD0_TPSMP_CLK 0x1C4 0x42C 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0x1C8 0x430 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI2_MCLK_SAI5_MCLK 0x1C8 0x430 0x52C 0x1 0x2 -#define MX8MQ_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x1C8 0x430 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI2_MCLK_TPSMP_HDATA_DIR 0x1C8 0x430 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x1CC 0x434 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x1CC 0x434 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x1CC 0x434 0x4E4 0x2 0x2 -#define MX8MQ_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x1CC 0x434 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI3_RXFS_TPSMP_HTRANS0 0x1CC 0x434 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x1D0 0x438 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI3_RXC_GPT1_CAPTURE2 0x1D0 0x438 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x1D0 0x438 0x4D0 0x2 0x2 -#define MX8MQ_IOMUXC_SAI3_RXC_GPIO4_IO29 0x1D0 0x438 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI3_RXC_TPSMP_HTRANS1 0x1D0 0x438 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x1D4 0x43C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x1D4 0x43C 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x1D4 0x43C 0x4D4 0x2 0x2 -#define MX8MQ_IOMUXC_SAI3_RXD_GPIO4_IO30 0x1D4 0x43C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI3_RXD_TPSMP_HDATA0 0x1D4 0x43C 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x1D8 0x440 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI3_TXFS_GPT1_CLK 0x1D8 0x440 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x1D8 0x440 0x4D8 0x2 0x2 -#define MX8MQ_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x1D8 0x440 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI3_TXFS_TPSMP_HDATA1 0x1D8 0x440 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x1DC 0x444 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x1DC 0x444 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x1DC 0x444 0x4DC 0x2 0x2 -#define MX8MQ_IOMUXC_SAI3_TXC_GPIO5_IO0 0x1DC 0x444 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI3_TXC_TPSMP_HDATA2 0x1DC 0x444 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x1E0 0x448 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x1E0 0x448 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x1E0 0x448 0x4E0 0x2 0x2 -#define MX8MQ_IOMUXC_SAI3_TXD_GPIO5_IO1 0x1E0 0x448 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI3_TXD_TPSMP_HDATA3 0x1E0 0x448 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI3_MCLK_SAI3_MCLK 0x1E4 0x44C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI3_MCLK_PWM4_OUT 0x1E4 0x44C 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI3_MCLK_SAI5_MCLK 0x1E4 0x44C 0x52C 0x2 0x3 -#define MX8MQ_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x1E4 0x44C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI3_MCLK_TPSMP_HDATA4 0x1E4 0x44C 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SPDIF_TX_SPDIF1_OUT 0x1E8 0x450 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SPDIF_TX_PWM3_OUT 0x1E8 0x450 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SPDIF_TX_GPIO5_IO3 0x1E8 0x450 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SPDIF_TX_TPSMP_HDATA5 0x1E8 0x450 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SPDIF_RX_SPDIF1_IN 0x1EC 0x454 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SPDIF_RX_PWM2_OUT 0x1EC 0x454 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SPDIF_RX_GPIO5_IO4 0x1EC 0x454 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SPDIF_RX_TPSMP_HDATA6 0x1EC 0x454 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x1F0 0x458 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x1F0 0x458 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x1F0 0x458 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_TPSMP_HDATA7 0x1F0 0x458 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x1F4 0x45C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x1F4 0x45C 0x504 0x1 0x0 -#define MX8MQ_IOMUXC_ECSPI1_SCLK_UART3_DTE_TX 0x1F4 0x45C 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x1F4 0x45C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ECSPI1_SCLK_TPSMP_HDATA8 0x1F4 0x45C 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x1F8 0x460 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x1F8 0x460 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_ECSPI1_MOSI_UART3_DTE_RX 0x1F8 0x460 0x504 0x1 0x1 -#define MX8MQ_IOMUXC_ECSPI1_MOSI_GPIO5_IO7 0x1F8 0x460 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ECSPI1_MOSI_TPSMP_HDATA9 0x1F8 0x460 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x1FC 0x464 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x1FC 0x464 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DTE_RTS_B 0x1FC 0x464 0x500 0x1 0x0 -#define MX8MQ_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x1FC 0x464 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ECSPI1_MISO_TPSMP_HDATA10 0x1FC 0x464 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x200 0x468 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x200 0x468 0x500 0x1 0x1 -#define MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DTE_CTS_B 0x200 0x468 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x200 0x468 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ECSPI1_SS0_TPSMP_HDATA11 0x200 0x468 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x204 0x46C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x204 0x46C 0x50C 0x1 0x0 -#define MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DTE_TX 0x204 0x46C 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x204 0x46C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ECSPI2_SCLK_TPSMP_HDATA12 0x204 0x46C 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x208 0x470 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x208 0x470 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DTE_RX 0x208 0x470 0x50C 0x1 0x1 -#define MX8MQ_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x208 0x470 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ECSPI2_MOSI_TPSMP_HDATA13 0x208 0x470 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x20C 0x474 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x20C 0x474 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DTE_RTS_B 0x20C 0x474 0x508 0x1 0x0 -#define MX8MQ_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x20C 0x474 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ECSPI2_MISO_TPSMP_HDATA14 0x20C 0x474 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x210 0x478 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x210 0x478 0x508 0x1 0x1 -#define MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DTE_CTS_B 0x210 0x478 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x210 0x478 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ECSPI2_SS0_TPSMP_HDATA15 0x210 0x478 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x214 0x47C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_I2C1_SCL_ENET1_MDC 0x214 0x47C 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_I2C1_SCL_GPIO5_IO14 0x214 0x47C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_I2C1_SCL_TPSMP_HDATA16 0x214 0x47C 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x218 0x480 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_I2C1_SDA_ENET1_MDIO 0x218 0x480 0x4C0 0x1 0x2 -#define MX8MQ_IOMUXC_I2C1_SDA_GPIO5_IO15 0x218 0x480 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_I2C1_SDA_TPSMP_HDATA17 0x218 0x480 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x21C 0x484 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x21C 0x484 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_I2C2_SCL_GPIO5_IO16 0x21C 0x484 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_I2C2_SCL_TPSMP_HDATA18 0x21C 0x484 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x220 0x488 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x220 0x488 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_I2C2_SDA_GPIO5_IO17 0x220 0x488 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_I2C2_SDA_TPSMP_HDATA19 0x220 0x488 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x224 0x48C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_I2C3_SCL_PWM4_OUT 0x224 0x48C 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_I2C3_SCL_GPT2_CLK 0x224 0x48C 0x000 0x2 0x0 -#define MX8MQ_IOMUXC_I2C3_SCL_GPIO5_IO18 0x224 0x48C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_I2C3_SCL_TPSMP_HDATA20 0x224 0x48C 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x228 0x490 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_I2C3_SDA_PWM3_OUT 0x228 0x490 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_I2C3_SDA_GPT3_CLK 0x228 0x490 0x000 0x2 0x0 -#define MX8MQ_IOMUXC_I2C3_SDA_GPIO5_IO19 0x228 0x490 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_I2C3_SDA_TPSMP_HDATA21 0x228 0x490 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x22C 0x494 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_I2C4_SCL_PWM2_OUT 0x22C 0x494 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x22C 0x494 0x524 0x2 0x0 -#define MX8MQ_IOMUXC_I2C4_SCL_GPIO5_IO20 0x22C 0x494 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_I2C4_SCL_TPSMP_HDATA22 0x22C 0x494 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x230 0x498 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_I2C4_SDA_PWM1_OUT 0x230 0x498 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x230 0x498 0x528 0x2 0x0 -#define MX8MQ_IOMUXC_I2C4_SDA_GPIO5_IO21 0x230 0x498 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_I2C4_SDA_TPSMP_HDATA23 0x230 0x498 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x234 0x49C 0x4F4 0x0 0x0 -#define MX8MQ_IOMUXC_UART1_RXD_UART1_DTE_TX 0x234 0x49C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x234 0x49C 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_UART1_RXD_GPIO5_IO22 0x234 0x49C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_UART1_RXD_TPSMP_HDATA24 0x234 0x49C 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x238 0x4A0 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_UART1_TXD_UART1_DTE_RX 0x238 0x4A0 0x4F4 0x0 0x0 -#define MX8MQ_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x238 0x4A0 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_UART1_TXD_GPIO5_IO23 0x238 0x4A0 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_UART1_TXD_TPSMP_HDATA25 0x238 0x4A0 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x23C 0x4A4 0x4FC 0x0 0x0 -#define MX8MQ_IOMUXC_UART2_RXD_UART2_DTE_TX 0x23C 0x4A4 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_UART2_RXD_ECSPI3_MISO 0x23C 0x4A4 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_UART2_RXD_GPIO5_IO24 0x23C 0x4A4 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_UART2_RXD_TPSMP_HDATA26 0x23C 0x4A4 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x240 0x4A8 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_UART2_TXD_UART2_DTE_RX 0x240 0x4A8 0x4FC 0x0 0x1 -#define MX8MQ_IOMUXC_UART2_TXD_ECSPI3_SS0 0x240 0x4A8 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_UART2_TXD_GPIO5_IO25 0x240 0x4A8 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_UART2_TXD_TPSMP_HDATA27 0x240 0x4A8 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x244 0x4AC 0x504 0x0 0x2 -#define MX8MQ_IOMUXC_UART3_RXD_UART3_DTE_TX 0x244 0x4AC 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x244 0x4AC 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_UART3_RXD_UART1_DTE_RTS_B 0x244 0x4AC 0x4F0 0x1 0x0 -#define MX8MQ_IOMUXC_UART3_RXD_GPIO5_IO26 0x244 0x4AC 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_UART3_RXD_TPSMP_HDATA28 0x244 0x4AC 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x248 0x4B0 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_UART3_TXD_UART3_DTE_RX 0x248 0x4B0 0x504 0x0 0x3 -#define MX8MQ_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x248 0x4B0 0x4F0 0x1 0x1 -#define MX8MQ_IOMUXC_UART3_TXD_UART1_DTE_CTS_B 0x248 0x4B0 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_UART3_TXD_GPIO5_IO27 0x248 0x4B0 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_UART3_TXD_TPSMP_HDATA29 0x248 0x4B0 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_UART4_RXD_UART4_DCE_RX 0x24C 0x4B4 0x50C 0x0 0x2 -#define MX8MQ_IOMUXC_UART4_RXD_UART4_DTE_TX 0x24C 0x4B4 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x24C 0x4B4 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_UART4_RXD_UART2_DTE_RTS_B 0x24C 0x4B4 0x4F8 0x1 0x0 -#define MX8MQ_IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x24C 0x4B4 0x524 0x2 0x1 -#define MX8MQ_IOMUXC_UART4_RXD_GPIO5_IO28 0x24C 0x4B4 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_UART4_RXD_TPSMP_HDATA30 0x24C 0x4B4 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_UART4_TXD_UART4_DCE_TX 0x250 0x4B8 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_UART4_TXD_UART4_DTE_RX 0x250 0x4B8 0x50C 0x0 0x3 -#define MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x250 0x4B8 0x4F8 0x1 0x1 -#define MX8MQ_IOMUXC_UART4_TXD_UART2_DTE_CTS_B 0x250 0x4B8 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_UART4_TXD_PCIE2_CLKREQ_B 0x250 0x4B8 0x528 0x2 0x1 -#define MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29 0x250 0x4B8 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_UART4_TXD_TPSMP_HDATA31 0x250 0x4B8 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_TEST_MODE 0x000 0x254 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_BOOT_MODE0 0x000 0x258 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_BOOT_MODE1 0x000 0x25C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_JTAG_MOD 0x000 0x260 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_JTAG_TRST_B 0x000 0x264 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_JTAG_TDI 0x000 0x268 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_JTAG_TMS 0x000 0x26C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_JTAG_TCK 0x000 0x270 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_JTAG_TDO 0x000 0x274 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_RTC 0x000 0x278 0x000 0x0 0x0 - -#endif /* __DTS_IMX8MQ_PINFUNC_H */ diff --git a/sys/gnu/dts/arm64/freescale/imx8mq-sr-som.dtsi b/sys/gnu/dts/arm64/freescale/imx8mq-sr-som.dtsi deleted file mode 100644 index 602c870a7cc..00000000000 --- a/sys/gnu/dts/arm64/freescale/imx8mq-sr-som.dtsi +++ /dev/null @@ -1,317 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2018 Jon Nettleton - */ - -#include "imx8mq.dtsi" - -/ { - reg_vdd_3v3: regulator-vdd-3v3 { - compatible = "regulator-fixed"; - regulator-always-on; - regulator-name = "vdd_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy0>; - phy-reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; - phy-reset-duration = <2>; - fsl,magic-packet; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@4 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <4>; - }; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - clock-frequency = <400000>; - status = "okay"; - - pmic: pmic@8 { - compatible = "fsl,pfuze100"; - reg = <0x08>; - - regulators { - sw1a_reg: sw1ab { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - }; - - sw1c_reg: sw1c { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - sw3a_reg: sw3ab { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-always-on; - }; - - sw4_reg: sw4 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - }; - - snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-always-on; - }; - - vgen1_reg: vgen1 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen2_reg: vgen2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - regulator-always-on; - }; - - vgen3_reg: vgen3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen4_reg: vgen4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen5_reg: vgen5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen6_reg: vgen6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - }; - }; - - eeprom@50 { - compatible = "atmel,24c01"; - reg = <0x50>; - status = "okay"; - }; -}; - -&pgc_gpu{ - power-supply = <&sw1a_reg>; -}; - -&pgc_vpu { - power-supply = <&sw1c_reg>; -}; - -&qspi0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_qspi>; - status = "okay"; - - /* SPI flash; not assembled by default */ - spi_flash: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - reg = <0>; - compatible = "micron,n25q256a", "jedec,spi-nor"; - spi-max-frequency = <29000000>; - status = "disabled"; - }; -}; - -&uart1 { /* console */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - assigned-clocks = <&clk IMX8MQ_CLK_UART1>; - assigned-clock-parents = <&clk IMX8MQ_CLK_25M>; - assigned-clock-rates = <25000000>; - status = "okay"; -}; - -&uart4 { /* ublox BT */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - assigned-clocks = <&clk IMX8MQ_CLK_UART4>; - assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>; - assigned-clock-rates = <80000000>; - status = "okay"; -}; - -&usdhc1 { - assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>; - assigned-clock-rates = <400000000>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl_fec1: fec1grp { - fsl,pins = < - MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 - MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23 - MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f - MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f - MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f - MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f - MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 - MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 - MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 - MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 - MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f - MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 - MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 - MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f - MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f - MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f - >; - }; - - pinctrl_pcie0: pcie0grp { - fsl,pins = < - MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x74 - MX8MQ_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x16 - MX8MQ_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x16 - >; - }; - - pinctrl_qspi: qspigrp { - fsl,pins = < - MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82 - MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 - MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 - MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 - MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 - MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 - - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49 - MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49 - MX8MQ_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x19 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX8MQ_IOMUXC_UART4_TXD_UART4_DCE_TX 0x49 - MX8MQ_IOMUXC_UART4_RXD_UART4_DCE_RX 0x49 - MX8MQ_IOMUXC_SAI3_TXD_GPIO5_IO1 0x19 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 - MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 - MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 - MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 - MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 - MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 - MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 - MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 - MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 - MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 - MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83 - MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1grp100mhz { - fsl,pins = < - MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d - MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd - MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd - MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd - MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd - MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd - MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd - MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd - MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd - MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd - MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d - MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1grp200mhz { - fsl,pins = < - MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f - MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf - MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf - MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf - MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf - MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf - MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf - MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf - MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf - MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf - MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f - MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 - >; - }; -}; diff --git a/sys/gnu/dts/arm64/freescale/imx8mq-thor96.dts b/sys/gnu/dts/arm64/freescale/imx8mq-thor96.dts deleted file mode 100644 index b4795a032fa..00000000000 --- a/sys/gnu/dts/arm64/freescale/imx8mq-thor96.dts +++ /dev/null @@ -1,581 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2019 Einfochips - * Copyright 2019 Linaro Ltd. - */ - -/dts-v1/; - -#include "imx8mq.dtsi" - -/ { - model = "Einfochips i.MX8MQ Thor96"; - compatible = "einfochips,imx8mq-thor96", "fsl,imx8mq"; - - chosen { - stdout-path = &uart1; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x00000000 0x40000000 0 0x80000000>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_leds>; - - user-led1 { - label = "green:user1"; - gpios = <&gpio4 21 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - - user-led2 { - label = "green:user2"; - gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "none"; - }; - - user-led3 { - label = "green:user3"; - gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc1"; - default-state = "off"; - }; - - user-led4 { - label = "green:user4"; - gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>; - panic-indicator; - linux,default-trigger = "none"; - }; - - wlan-active-led { - label = "yellow:wlan"; - gpios = <&gpio4 1 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "phy0tx"; - default-state = "off"; - }; - - bt-active-led { - label = "blue:bt"; - gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "hci0-power"; - default-state = "off"; - }; - }; - - reg_usdhc1_vmmc: reg-usdhc1-vmmc { - compatible = "regulator-fixed"; - regulator-name = "VDD_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_usdhc1_vqmmc: reg-usdhc1-vqmmc { - compatible = "regulator-fixed"; - regulator-name = "VCC_1V8_EXT"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - reg_usdhc2_vmmc: reg-usdhc2-vmmc { - compatible = "regulator-fixed"; - regulator-name = "VSD_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usdhc2>; - gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usdhc2_vqmmc: reg-usdhc2-vqmmc { - compatible = "regulator-fixed"; - regulator-name = "NVCC_SD2"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wifi_reg_on>; - gpio = <&gpio3 3 GPIO_ACTIVE_HIGH>; - }; -}; - -/* LS-SPI0 */ -&ecspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi2>; - status = "okay"; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - phy-mode = "rgmii-id"; - phy-reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; - phy-handle = <ðphy>; - fsl,magic-packet; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy: ethernet-phy@3 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <3>; - }; - }; -}; - -/* LS-I2C0 */ -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pmic@8 { - compatible = "fsl,pfuze100"; - reg = <0x8>; - - regulators { - sw1a_reg: sw1ab { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - }; - - sw1c_reg: sw1c { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - sw3a_reg: sw3ab { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-always-on; - }; - - sw4_reg: sw4 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - }; - - snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-always-on; - }; - - vgen1_reg: vgen1 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen2_reg: vgen2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - regulator-always-on; - }; - - vgen3_reg: vgen3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen4_reg: vgen4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen5_reg: vgen5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen6_reg: vgen6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - }; - }; -}; - -/* LS-I2C1 */ -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - eeprom: eeprom@50 { - compatible = "atmel,24c256"; - reg = <0x50>; - }; -}; - -/* HS-I2C2 */ -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; -}; - -/* HS-I2C3 */ -&i2c4 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4>; - status = "okay"; -}; - -&pgc_gpu { - power-supply = <&sw1a_reg>; -}; - -&pgc_vpu { - power-supply = <&sw1c_reg>; -}; - -&qspi0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_qspi0>; - status = "okay"; - - flash@0 { - compatible = "jedec,spi-nor"; - spi-max-frequency = <100000000>; - reg = <0>; - }; -}; - -/* Debug UART */ -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - assigned-clocks = <&clk IMX8MQ_CLK_UART1>; - assigned-clock-parents = <&clk IMX8MQ_CLK_25M>; - status = "okay"; -}; - -/* LS-UART0 */ -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - assigned-clocks = <&clk IMX8MQ_CLK_UART2>; - assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>; - uart-has-rtscts; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - device-wakeup-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; - host-wakeup-gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; - shutdown-gpios = <&gpio3 5 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_bt_gpios>; - }; -}; - -/* LS-UART1 */ -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - assigned-clocks = <&clk IMX8MQ_CLK_UART3>; - assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>; - status = "okay"; -}; - -&usb3_phy1 { - status = "okay"; -}; - -&usb_dwc3_1 { - dr_mode = "host"; - status = "okay"; -}; - -/* SDIO */ -&usdhc1 { - #address-cells = <0x1>; - #size-cells = <0x0>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>; - vmmc-supply = <®_usdhc1_vmmc>; - vqmmc-supply = <®_usdhc1_vqmmc>; - mmc-pwrseq = <&sdio_pwrseq>; - bus-width = <4>; - non-removable; - no-sd; - no-emmc; - status = "okay"; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - }; -}; - -/* uSD */ -&usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; - vmmc-supply = <®_usdhc2_vmmc>; - vqmmc-supply = <®_usdhc2_vqmmc>; - cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; - bus-width = <4>; - no-sdio; - no-emmc; - disable-wp; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl_bt_gpios: btgpiosgrp { - fsl,pins = < - MX8MQ_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x19 - MX8MQ_IOMUXC_NAND_DQS_GPIO3_IO14 0x19 - MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x19 - >; - }; - - pinctrl_ecspi2: ecspi2grp { - fsl,pins = < - MX8MQ_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x16 - MX8MQ_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x16 - MX8MQ_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x16 - MX8MQ_IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x16 - >; - }; - - pinctrl_fec1: fec1grp { - fsl,pins = < - MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x4 - MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x24 - MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1c - MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1c - MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1c - MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1c - MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 - MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 - MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 - MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 - MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1c - MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 - MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 - MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1c - MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f - MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f - MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000007f - MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000007f - >; - }; - - pinctrl_i2c4: i2c4grp { - fsl,pins = < - MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x4000007f - MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x4000007f - >; - }; - - pinctrl_leds: ledsgrp { - fsl,pins = < - MX8MQ_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x19 - MX8MQ_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 - MX8MQ_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x19 - MX8MQ_IOMUXC_SAI3_RXC_GPIO4_IO29 0x19 - MX8MQ_IOMUXC_SAI1_RXC_GPIO4_IO1 0x19 - MX8MQ_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x19 - >; - }; - - pinctrl_qspi0: qspi0grp { - fsl,pins = < - MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82 - MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 - MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 - MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 - MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 - MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 - - >; - }; - - pinctrl_reg_usdhc2: regusdhc2grp { - fsl,pins = < - MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49 - MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49 - MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49 - MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x49 - MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x49 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x49 - MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x49 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 - MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 - MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 - MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 - MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 - MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 - MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x85 - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { - fsl,pins = < - MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d - MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd - MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd - MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd - MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd - MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd - MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x85 - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { - fsl,pins = < - MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f - MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf - MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf - MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf - MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf - MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf - MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x85 - >; - }; - - pinctrl_usdhc2_gpio: usdhc2gpiogrp { - fsl,pins = < - MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 - MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 - MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 - MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 - MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 - MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 - MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = < - MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8c - MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcc - MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcc - MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcc - MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcc - MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcc - MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = < - MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9c - MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xdc - MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xdc - MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xdc - MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xdc - MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xdc - MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xcc - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 - >; - }; - - pinctrl_wifi_reg_on: wifiregongrp { - fsl,pins = < - MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x17059 - >; - }; -}; diff --git a/sys/gnu/dts/arm64/freescale/imx8mq-zii-ultra-rmb3.dts b/sys/gnu/dts/arm64/freescale/imx8mq-zii-ultra-rmb3.dts deleted file mode 100644 index 6b3581366d6..00000000000 --- a/sys/gnu/dts/arm64/freescale/imx8mq-zii-ultra-rmb3.dts +++ /dev/null @@ -1,95 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2019 Zodiac Inflight Innovations - */ - -/dts-v1/; - -#include "imx8mq-zii-ultra.dtsi" - -/ { - model = "ZII Ultra RMB3 Board"; - compatible = "zii,imx8mq-ultra-rmb3", "zii,imx8mq-ultra", "fsl,imx8mq"; -}; - -&ecspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - cs-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - - nor_flash: flash@0 { - compatible = "st,n25q128a13", "jedec,spi-nor"; - spi-max-frequency = <20000000>; - reg = <0>; - }; -}; - -&i2c2 { - temp-sense@48 { - compatible = "national,lm75"; - reg = <0x48>; - }; -}; - -&i2c4 { - touchscreen@20 { - compatible = "syna,rmi4-i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ts>; - reg = <0x20>; - interrupt-parent = <&gpio1>; - interrupts = <12 IRQ_TYPE_LEVEL_LOW>; - - #address-cells = <1>; - #size-cells = <0>; - - rmi4-f01@1 { - reg = <0x1>; - syna,nosleep-mode = <2>; - }; - - rmi4-f11@11 { - reg = <0x11>; - touchscreen-inverted-x; - touchscreen-swapped-x-y; - syna,sensor-type = <1>; - }; - - rmi4-f12@12 { - reg = <0x12>; - touchscreen-inverted-x; - touchscreen-swapped-x-y; - syna,sensor-type = <1>; - }; - }; - - touchscreen@2a { - compatible = "eeti,exc3000"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ts>; - reg = <0x2a>; - interrupt-parent = <&gpio1>; - interrupts = <12 IRQ_TYPE_LEVEL_LOW>; - touchscreen-inverted-x; - touchscreen-swapped-x-y; - status = "disabled"; - }; -}; - -&usbhub { - swap-dx-lanes = <0>; -}; - -&iomuxc { - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x19 - MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82 - MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82 - MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82 - >; - }; -}; diff --git a/sys/gnu/dts/arm64/freescale/imx8mq-zii-ultra-zest.dts b/sys/gnu/dts/arm64/freescale/imx8mq-zii-ultra-zest.dts deleted file mode 100644 index 173b9e9b2bb..00000000000 --- a/sys/gnu/dts/arm64/freescale/imx8mq-zii-ultra-zest.dts +++ /dev/null @@ -1,24 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2019 Zodiac Inflight Innovations - */ - -/dts-v1/; - -#include "imx8mq-zii-ultra.dtsi" - -/ { - model = "ZII Ultra Zest Board"; - compatible = "zii,imx8mq-ultra-zest", "zii,imx8mq-ultra", "fsl,imx8mq"; -}; - -&i2c4 { - touchscreen@4a { - compatible = "atmel,maxtouch"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ts>; - reg = <0x4a>; - interrupt-parent = <&gpio1>; - interrupts = <12 IRQ_TYPE_LEVEL_LOW>; - }; -}; diff --git a/sys/gnu/dts/arm64/freescale/imx8mq-zii-ultra.dtsi b/sys/gnu/dts/arm64/freescale/imx8mq-zii-ultra.dtsi deleted file mode 100644 index 6a55165bd76..00000000000 --- a/sys/gnu/dts/arm64/freescale/imx8mq-zii-ultra.dtsi +++ /dev/null @@ -1,769 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2019 Zodiac Inflight Innovations - */ - -#include "imx8mq.dtsi" - -/ { - aliases { - mdio-gpio0 = &mdio0; - rtc0 = &ds1341; - }; - - chosen { - stdout-path = &uart1; - }; - - mdio0: bitbang-mdio { - compatible = "virtual,mdio-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mdio_bitbang>, <&pinctrl_fec1_phy_reset>; - gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>, /* MDC */ - <&gpio1 14 GPIO_ACTIVE_HIGH>; /* MDIO */ - #address-cells = <1>; - #size-cells = <0>; - - phy0: ethernet-phy@0 { - reg = <0>; - reset-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; - }; - }; - - pcie0_refclk: clock-pcie0-refclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - }; - - pcie1_refclk: clock-pcie1-refclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - }; - - reg_12p0_main: regulator-12p0-main { - compatible = "regulator-fixed"; - regulator-name = "12V_MAIN"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - reg_5p0_main: regulator-5p0-main { - compatible = "regulator-fixed"; - vin-supply = <®_12p0_main>; - regulator-name = "5V_MAIN"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - reg_3p3_main: regulator-3p3-main { - compatible = "regulator-fixed"; - vin-supply = <®_12p0_main>; - regulator-name = "3V3_MAIN"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_gen_3p3: regulator-gen-3p3 { - compatible = "regulator-fixed"; - vin-supply = <®_3p3_main>; - regulator-name = "GEN_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_usdhc2_vmmc: regulator-vsd-3v3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usdhc2>; - compatible = "regulator-fixed"; - vin-supply = <®_gen_3p3>; - regulator-name = "3V3_SD"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_arm: regulator-arm { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_arm>; - compatible = "regulator-gpio"; - vin-supply = <®_12p0_main>; - regulator-name = "0V9_ARM"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1000000>; - gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; - states = <1000000 0x1 - 900000 0x0>; - regulator-always-on; - }; -}; - -&A53_0 { - cpu-supply = <®_arm>; -}; - -&A53_1 { - cpu-supply = <®_arm>; -}; - -&A53_2 { - cpu-supply = <®_arm>; -}; - -&A53_3 { - cpu-supply = <®_arm>; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - - phy-handle = <&phy0>; - phy-mode = "rmii"; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - switch: switch@0 { - compatible = "marvell,mv88e6085"; - pinctrl-0 = <&pinctrl_switch_irq>; - pinctrl-names = "default"; - reg = <0>; - dsa,member = <0 0>; - eeprom-length = <512>; - interrupt-parent = <&gpio1>; - interrupts = <15 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells = <2>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "gigabit_proc"; - phy-handle = <&switchphy0>; - }; - - port@1 { - reg = <1>; - label = "netaux"; - phy-handle = <&switchphy1>; - }; - - port@2 { - reg = <2>; - label = "cpu"; - ethernet = <&fec1>; - - fixed-link { - speed = <100>; - full-duplex; - }; - }; - - port@3 { - reg = <3>; - label = "netright"; - phy-handle = <&switchphy3>; - }; - - port@4 { - reg = <4>; - label = "netleft"; - phy-handle = <&switchphy4>; - }; - }; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - switchphy0: switchphy@0 { - reg = <0>; - interrupt-parent = <&switch>; - interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; - }; - - switchphy1: switchphy@1 { - reg = <1>; - interrupt-parent = <&switch>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; - }; - - switchphy2: switchphy@2 { - reg = <2>; - interrupt-parent = <&switch>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; - }; - - switchphy3: switchphy@3 { - reg = <3>; - interrupt-parent = <&switch>; - interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; - }; - - switchphy4: switchphy@4 { - reg = <4>; - interrupt-parent = <&switch>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - }; - }; -}; - -&gpio3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio3_hog>; - - usb-emulation { - gpio-hog; - gpios = <10 GPIO_ACTIVE_HIGH>; - output-low; - line-name = "usb-emulation"; - }; - - usb-mode1 { - gpio-hog; - gpios = <11 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "usb-mode1"; - }; - - usb-pwr { - gpio-hog; - gpios = <12 GPIO_ACTIVE_LOW>; - output-high; - line-name = "usb-pwr-ctrl-en-n"; - }; - - usb-mode2 { - gpio-hog; - gpios = <13 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "usb-mode2"; - }; -}; - -&i2c1 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - accelerometer@1c { - compatible = "fsl,mma8451"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_accel>; - reg = <0x1c>; - interrupt-parent = <&gpio3>; - interrupts = <20 IRQ_TYPE_LEVEL_LOW>; - interrupt-names = "INT2"; - vdd-supply = <®_gen_3p3>; - vddio-supply = <®_gen_3p3>; - }; - - ucs1002: charger@32 { - compatible = "microchip,ucs1002"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ucs1002>; - reg = <0x32>; - interrupt-parent = <&gpio3>; - interrupts = <17 IRQ_TYPE_EDGE_BOTH>, - <18 IRQ_TYPE_EDGE_BOTH>; - interrupt-names = "a_det", "alert"; - }; -}; - -&i2c2 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - pmic@8 { - compatible = "fsl,pfuze100"; - reg = <0x8>; - - regulators { - sw1a_reg: sw1ab { - regulator-min-microvolt = <825000>; - regulator-max-microvolt = <1100000>; - }; - - sw1c_reg: sw1c { - regulator-min-microvolt = <825000>; - regulator-max-microvolt = <1100000>; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - sw3a_reg: sw3ab { - regulator-min-microvolt = <825000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - sw4_reg: sw4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - }; - - snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-always-on; - }; - - vgen1_reg: vgen1 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen2_reg: vgen2 { - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <975000>; - regulator-always-on; - }; - - vgen3_reg: vgen3 { - regulator-min-microvolt = <1675000>; - regulator-max-microvolt = <1975000>; - regulator-always-on; - }; - - vgen4_reg: vgen4 { - regulator-min-microvolt = <1625000>; - regulator-max-microvolt = <1875000>; - regulator-always-on; - }; - - vgen5_reg: vgen5 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3625000>; - regulator-always-on; - }; - - vgen6_reg: vgen6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - }; - }; - - eeprom@54 { - compatible = "atmel,24c128"; - reg = <0x54>; - }; - - ds1341: rtc@68 { - compatible = "dallas,ds1341"; - reg = <0x68>; - }; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - usbhub: usbhub@2c { - compatible ="microchip,usb2513b"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbhub>; - reg = <0x2c>; - reset-gpios = <&gpio3 25 GPIO_ACTIVE_LOW>; - }; - - watchdog@38 { - compatible = "zii,rave-wdt"; - reg = <0x38>; - }; -}; - -&i2c4 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; - - rave-sp { - compatible = "zii,rave-sp-rdu2"; - current-speed = <1000000>; - #address-cells = <1>; - #size-cells = <1>; - - watchdog { - compatible = "zii,rave-sp-watchdog"; - }; - - backlight { - compatible = "zii,rave-sp-backlight"; - }; - - pwrbutton { - compatible = "zii,rave-sp-pwrbutton"; - }; - - eeprom@a3 { - compatible = "zii,rave-sp-eeprom"; - reg = <0xa3 0x4000>; - zii,eeprom-name = "dds-eeprom"; - }; - - eeprom@a4 { - compatible = "zii,rave-sp-eeprom"; - reg = <0xa4 0x4000>; - #address-cells = <1>; - #size-cells = <1>; - zii,eeprom-name = "main-eeprom"; - }; - }; -}; - -&usb3_phy0 { - vbus-supply = <&ucs1002>; - status = "okay"; -}; - -&usb_dwc3_0 { - dr_mode = "host"; - status = "okay"; -}; - -&usb3_phy1 { - vbus-supply = <®_5p0_main>; - status = "okay"; -}; - -&usb_dwc3_1 { - dr_mode = "host"; - status = "okay"; -}; - -&pcie0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie0>; - reset-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; - clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>, - <&clk IMX8MQ_CLK_PCIE1_AUX>, - <&clk IMX8MQ_CLK_PCIE1_PHY>, - <&pcie0_refclk>; - clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; - status = "okay"; -}; - -&pcie1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie1>; - reset-gpio = <&gpio1 6 GPIO_ACTIVE_LOW>; - clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>, - <&clk IMX8MQ_CLK_PCIE2_AUX>, - <&clk IMX8MQ_CLK_PCIE2_PHY>, - <&pcie1_refclk>; - clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; - status = "okay"; -}; - -&pgc_gpu { - power-supply = <&sw1a_reg>; -}; - -&pgc_vpu { - power-supply = <&sw1c_reg>; -}; - -&usdhc1 { - assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>; - assigned-clock-rates = <400000000>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>; - vqmmc-supply = <&sw4_reg>; - bus-width = <8>; - non-removable; - no-sd; - no-sdio; - status = "okay"; -}; - -&usdhc2 { - assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>; - assigned-clock-rates = <200000000>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>; - cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_usdhc2_vmmc>; - status = "okay"; -}; - -&snvs_rtc { - status = "disabled"; -}; - -&iomuxc { - pinctrl_accel: accelgrp { - fsl,pins = < - MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0x41 - >; - }; - - pinctrl_fec1: fec1grp { - fsl,pins = < - MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 - MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23 - MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f - MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f - MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 - MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 - MX8MQ_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x1f - MX8MQ_IOMUXC_ENET_RXC_ENET1_RX_ER 0x91 - MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 - MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f - >; - }; - - pinctrl_fec1_phy_reset: fec1phyresetgrp { - fsl,pins = < - MX8MQ_IOMUXC_ENET_RD3_GPIO1_IO29 0x11 - >; - }; - - pinctrl_gpio3_hog: gpio3hoggrp { - fsl,pins = < - MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10 0x6 - MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x6 - MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0x6 - MX8MQ_IOMUXC_NAND_DATA07_GPIO3_IO13 0x6 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f - MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f - MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000007f - MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000007f - >; - }; - - pinctrl_i2c4: i2c4grp { - fsl,pins = < - MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x4000007f - MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x4000007f - >; - }; - - pinctrl_mdio_bitbang: bitbangmdiogrp { - fsl,pins = < - MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x44 - MX8MQ_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x64 - >; - }; - - pinctrl_pcie0: pcie0grp { - fsl,pins = < - MX8MQ_IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x66 - MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x6 - >; - }; - - pinctrl_pcie1: pcie1grp { - fsl,pins = < - MX8MQ_IOMUXC_UART4_TXD_PCIE2_CLKREQ_B 0x66 - MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x6 - >; - }; - - pinctrl_reg_arm: regarmgrp { - fsl,pins = < - MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 - >; - }; - - pinctrl_reg_usdhc2: regusdhc2grp { - fsl,pins = < - MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 - >; - }; - - pinctrl_switch_irq: switchgrp { - fsl,pins = < - MX8MQ_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x41 - >; - }; - - pinctrl_ts: tsgrp { - fsl,pins = < - MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x96 - MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x96 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49 - MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49 - MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49 - >; - }; - - pinctrl_ucs1002: ucs1002grp { - fsl,pins = < - MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17 0x41 - MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18 0x41 - >; - }; - - pinctrl_usbhub: usbhubgrp { - fsl,pins = < - MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x41 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 - MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 - MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 - MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 - MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 - MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 - MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 - MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 - MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 - MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 - MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83 - MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1-100grp { - fsl,pins = < - MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d - MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd - MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd - MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd - MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd - MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd - MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd - MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd - MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd - MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd - MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d - MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1-200grp { - fsl,pins = < - MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f - MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf - MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf - MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf - MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf - MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf - MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf - MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf - MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf - MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf - MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f - MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 - MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 - MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 - MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 - MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 - MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 - MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100grp { - fsl,pins = < - MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85 - MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5 - MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5 - MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5 - MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5 - MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5 - MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200grp { - fsl,pins = < - MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87 - MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7 - MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7 - MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7 - MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7 - MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7 - MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 - >; - }; -}; diff --git a/sys/gnu/dts/arm64/freescale/imx8mq.dtsi b/sys/gnu/dts/arm64/freescale/imx8mq.dtsi deleted file mode 100644 index 6a1e83922c7..00000000000 --- a/sys/gnu/dts/arm64/freescale/imx8mq.dtsi +++ /dev/null @@ -1,1222 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2017 NXP - * Copyright (C) 2017-2018 Pengutronix, Lucas Stach - */ - -#include -#include -#include -#include -#include "dt-bindings/input/input.h" -#include -#include -#include "imx8mq-pinfunc.h" - -/ { - interrupt-parent = <&gpc>; - - #address-cells = <2>; - #size-cells = <2>; - - aliases { - gpio0 = &gpio1; - gpio1 = &gpio2; - gpio2 = &gpio3; - gpio3 = &gpio4; - gpio4 = &gpio5; - i2c0 = &i2c1; - i2c1 = &i2c2; - i2c2 = &i2c3; - i2c3 = &i2c4; - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - serial3 = &uart4; - spi0 = &ecspi1; - spi1 = &ecspi2; - spi2 = &ecspi3; - }; - - ckil: clock-ckil { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "ckil"; - }; - - osc_25m: clock-osc-25m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - clock-output-names = "osc_25m"; - }; - - osc_27m: clock-osc-27m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <27000000>; - clock-output-names = "osc_27m"; - }; - - clk_ext1: clock-ext1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <133000000>; - clock-output-names = "clk_ext1"; - }; - - clk_ext2: clock-ext2 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <133000000>; - clock-output-names = "clk_ext2"; - }; - - clk_ext3: clock-ext3 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <133000000>; - clock-output-names = "clk_ext3"; - }; - - clk_ext4: clock-ext4 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency= <133000000>; - clock-output-names = "clk_ext4"; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - A53_0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0>; - clock-latency = <61036>; /* two CLK32 periods */ - clocks = <&clk IMX8MQ_CLK_ARM>; - enable-method = "psci"; - next-level-cache = <&A53_L2>; - operating-points-v2 = <&a53_opp_table>; - #cooling-cells = <2>; - nvmem-cells = <&cpu_speed_grade>; - nvmem-cell-names = "speed_grade"; - }; - - A53_1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x1>; - clock-latency = <61036>; /* two CLK32 periods */ - clocks = <&clk IMX8MQ_CLK_ARM>; - enable-method = "psci"; - next-level-cache = <&A53_L2>; - operating-points-v2 = <&a53_opp_table>; - #cooling-cells = <2>; - }; - - A53_2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x2>; - clock-latency = <61036>; /* two CLK32 periods */ - clocks = <&clk IMX8MQ_CLK_ARM>; - enable-method = "psci"; - next-level-cache = <&A53_L2>; - operating-points-v2 = <&a53_opp_table>; - #cooling-cells = <2>; - }; - - A53_3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x3>; - clock-latency = <61036>; /* two CLK32 periods */ - clocks = <&clk IMX8MQ_CLK_ARM>; - enable-method = "psci"; - next-level-cache = <&A53_L2>; - operating-points-v2 = <&a53_opp_table>; - #cooling-cells = <2>; - }; - - A53_L2: l2-cache0 { - compatible = "cache"; - }; - }; - - a53_opp_table: opp-table { - compatible = "operating-points-v2"; - opp-shared; - - opp-800000000 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <900000>; - /* Industrial only */ - opp-supported-hw = <0xf>, <0x4>; - clock-latency-ns = <150000>; - opp-suspend; - }; - - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <900000>; - /* Consumer only */ - opp-supported-hw = <0xe>, <0x3>; - clock-latency-ns = <150000>; - opp-suspend; - }; - - opp-1300000000 { - opp-hz = /bits/ 64 <1300000000>; - opp-microvolt = <1000000>; - opp-supported-hw = <0xc>, <0x4>; - clock-latency-ns = <150000>; - opp-suspend; - }; - - opp-1500000000 { - opp-hz = /bits/ 64 <1500000000>; - opp-microvolt = <1000000>; - opp-supported-hw = <0x8>, <0x3>; - clock-latency-ns = <150000>; - opp-suspend; - }; - }; - - pmu { - compatible = "arm,cortex-a53-pmu"; - interrupts = ; - interrupt-parent = <&gic>; - interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - thermal-zones { - cpu-thermal { - polling-delay-passive = <250>; - polling-delay = <2000>; - thermal-sensors = <&tmu 0>; - - trips { - cpu_alert: cpu-alert { - temperature = <80000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu-crit { - temperature = <90000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu_alert>; - cooling-device = - <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - gpu-thermal { - polling-delay-passive = <250>; - polling-delay = <2000>; - thermal-sensors = <&tmu 1>; - - trips { - gpu_alert: gpu-alert { - temperature = <80000>; - hysteresis = <2000>; - type = "passive"; - }; - - gpu-crit { - temperature = <90000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&gpu_alert>; - cooling-device = - <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - vpu-thermal { - polling-delay-passive = <250>; - polling-delay = <2000>; - thermal-sensors = <&tmu 2>; - - trips { - vpu-crit { - temperature = <90000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , /* Physical Secure */ - , /* Physical Non-Secure */ - , /* Virtual */ - ; /* Hypervisor */ - interrupt-parent = <&gic>; - arm,no-tick-in-suspend; - }; - - soc@0 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x0 0x3e000000>; - dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>; - - bus@30000000 { /* AIPS1 */ - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x30000000 0x30000000 0x400000>; - - sai1: sai@30010000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx8mq-sai"; - reg = <0x30010000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MQ_CLK_SAI1_IPG>, - <&clk IMX8MQ_CLK_SAI1_ROOT>, - <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dmas = <&sdma2 8 24 0>, <&sdma1 9 24 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - sai6: sai@30030000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx8mq-sai"; - reg = <0x30030000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MQ_CLK_SAI6_IPG>, - <&clk IMX8MQ_CLK_SAI6_ROOT>, - <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dmas = <&sdma2 4 24 0>, <&sdma2 5 24 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - sai5: sai@30040000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx8mq-sai"; - reg = <0x30040000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MQ_CLK_SAI5_IPG>, - <&clk IMX8MQ_CLK_SAI5_ROOT>, - <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dmas = <&sdma2 2 24 0>, <&sdma2 3 24 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - sai4: sai@30050000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx8mq-sai"; - reg = <0x30050000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MQ_CLK_SAI4_IPG>, - <&clk IMX8MQ_CLK_SAI4_ROOT>, - <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dmas = <&sdma2 0 24 0>, <&sdma2 1 24 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - gpio1: gpio@30200000 { - compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; - reg = <0x30200000 0x10000>; - interrupts = , - ; - clocks = <&clk IMX8MQ_CLK_GPIO1_ROOT>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 10 30>; - }; - - gpio2: gpio@30210000 { - compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; - reg = <0x30210000 0x10000>; - interrupts = , - ; - clocks = <&clk IMX8MQ_CLK_GPIO2_ROOT>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 40 21>; - }; - - gpio3: gpio@30220000 { - compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; - reg = <0x30220000 0x10000>; - interrupts = , - ; - clocks = <&clk IMX8MQ_CLK_GPIO3_ROOT>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 61 26>; - }; - - gpio4: gpio@30230000 { - compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; - reg = <0x30230000 0x10000>; - interrupts = , - ; - clocks = <&clk IMX8MQ_CLK_GPIO4_ROOT>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 87 32>; - }; - - gpio5: gpio@30240000 { - compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; - reg = <0x30240000 0x10000>; - interrupts = , - ; - clocks = <&clk IMX8MQ_CLK_GPIO5_ROOT>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 119 30>; - }; - - tmu: tmu@30260000 { - compatible = "fsl,imx8mq-tmu"; - reg = <0x30260000 0x10000>; - interrupt = ; - clocks = <&clk IMX8MQ_CLK_TMU_ROOT>; - little-endian; - fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>; - fsl,tmu-calibration = <0x00000000 0x00000023 - 0x00000001 0x00000029 - 0x00000002 0x0000002f - 0x00000003 0x00000035 - 0x00000004 0x0000003d - 0x00000005 0x00000043 - 0x00000006 0x0000004b - 0x00000007 0x00000051 - 0x00000008 0x00000057 - 0x00000009 0x0000005f - 0x0000000a 0x00000067 - 0x0000000b 0x0000006f - - 0x00010000 0x0000001b - 0x00010001 0x00000023 - 0x00010002 0x0000002b - 0x00010003 0x00000033 - 0x00010004 0x0000003b - 0x00010005 0x00000043 - 0x00010006 0x0000004b - 0x00010007 0x00000055 - 0x00010008 0x0000005d - 0x00010009 0x00000067 - 0x0001000a 0x00000070 - - 0x00020000 0x00000017 - 0x00020001 0x00000023 - 0x00020002 0x0000002d - 0x00020003 0x00000037 - 0x00020004 0x00000041 - 0x00020005 0x0000004b - 0x00020006 0x00000057 - 0x00020007 0x00000063 - 0x00020008 0x0000006f - - 0x00030000 0x00000015 - 0x00030001 0x00000021 - 0x00030002 0x0000002d - 0x00030003 0x00000039 - 0x00030004 0x00000045 - 0x00030005 0x00000053 - 0x00030006 0x0000005f - 0x00030007 0x00000071>; - #thermal-sensor-cells = <1>; - }; - - wdog1: watchdog@30280000 { - compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt"; - reg = <0x30280000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MQ_CLK_WDOG1_ROOT>; - status = "disabled"; - }; - - wdog2: watchdog@30290000 { - compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt"; - reg = <0x30290000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MQ_CLK_WDOG2_ROOT>; - status = "disabled"; - }; - - wdog3: watchdog@302a0000 { - compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt"; - reg = <0x302a0000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MQ_CLK_WDOG3_ROOT>; - status = "disabled"; - }; - - sdma2: sdma@302c0000 { - compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma"; - reg = <0x302c0000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MQ_CLK_SDMA2_ROOT>, - <&clk IMX8MQ_CLK_SDMA2_ROOT>; - clock-names = "ipg", "ahb"; - #dma-cells = <3>; - fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; - }; - - lcdif: lcd-controller@30320000 { - compatible = "fsl,imx8mq-lcdif", "fsl,imx28-lcdif"; - reg = <0x30320000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL>; - clock-names = "pix"; - assigned-clocks = <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>, - <&clk IMX8MQ_VIDEO_PLL1_BYPASS>, - <&clk IMX8MQ_CLK_LCDIF_PIXEL>, - <&clk IMX8MQ_VIDEO_PLL1>; - assigned-clock-parents = <&clk IMX8MQ_CLK_25M>, - <&clk IMX8MQ_VIDEO_PLL1>, - <&clk IMX8MQ_VIDEO_PLL1_OUT>; - assigned-clock-rates = <0>, <0>, <0>, <594000000>; - status = "disabled"; - }; - - iomuxc: iomuxc@30330000 { - compatible = "fsl,imx8mq-iomuxc"; - reg = <0x30330000 0x10000>; - }; - - iomuxc_gpr: syscon@30340000 { - compatible = "fsl,imx8mq-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr", - "syscon", "simple-mfd"; - reg = <0x30340000 0x10000>; - - mux: mux-controller { - compatible = "mmio-mux"; - #mux-control-cells = <1>; - mux-reg-masks = <0x34 0x00000004>; /* MIPI_MUX_SEL */ - }; - }; - - ocotp: ocotp-ctrl@30350000 { - compatible = "fsl,imx8mq-ocotp", "syscon"; - reg = <0x30350000 0x10000>; - clocks = <&clk IMX8MQ_CLK_OCOTP_ROOT>; - #address-cells = <1>; - #size-cells = <1>; - - cpu_speed_grade: speed-grade@10 { - reg = <0x10 4>; - }; - }; - - anatop: syscon@30360000 { - compatible = "fsl,imx8mq-anatop", "syscon"; - reg = <0x30360000 0x10000>; - interrupts = ; - }; - - snvs: snvs@30370000 { - compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; - reg = <0x30370000 0x10000>; - - snvs_rtc: snvs-rtc-lp{ - compatible = "fsl,sec-v4.0-mon-rtc-lp"; - regmap =<&snvs>; - offset = <0x34>; - interrupts = , - ; - clocks = <&clk IMX8MQ_CLK_SNVS_ROOT>; - clock-names = "snvs-rtc"; - }; - - snvs_pwrkey: snvs-powerkey { - compatible = "fsl,sec-v4.0-pwrkey"; - regmap = <&snvs>; - interrupts = ; - linux,keycode = ; - wakeup-source; - status = "disabled"; - }; - }; - - clk: clock-controller@30380000 { - compatible = "fsl,imx8mq-ccm"; - reg = <0x30380000 0x10000>; - interrupts = , - ; - #clock-cells = <1>; - clocks = <&ckil>, <&osc_25m>, <&osc_27m>, - <&clk_ext1>, <&clk_ext2>, - <&clk_ext3>, <&clk_ext4>; - clock-names = "ckil", "osc_25m", "osc_27m", - "clk_ext1", "clk_ext2", - "clk_ext3", "clk_ext4"; - assigned-clocks = <&clk IMX8MQ_CLK_NOC>; - assigned-clock-rates = <800000000>; - }; - - src: reset-controller@30390000 { - compatible = "fsl,imx8mq-src", "syscon"; - reg = <0x30390000 0x10000>; - #reset-cells = <1>; - }; - - gpc: gpc@303a0000 { - compatible = "fsl,imx8mq-gpc"; - reg = <0x303a0000 0x10000>; - interrupt-parent = <&gic>; - interrupt-controller; - #interrupt-cells = <3>; - - pgc { - #address-cells = <1>; - #size-cells = <0>; - - pgc_mipi: power-domain@0 { - #power-domain-cells = <0>; - reg = ; - }; - - /* - * As per comment in ATF source code: - * - * PCIE1 and PCIE2 share the - * same reset signal, if we - * power down PCIE2, PCIE1 - * will be held in reset too. - * - * So instead of creating two - * separate power domains for - * PCIE1 and PCIE2 we create a - * link between both and use - * it as a shared PCIE power - * domain. - */ - pgc_pcie: power-domain@1 { - #power-domain-cells = <0>; - reg = ; - power-domains = <&pgc_pcie2>; - }; - - pgc_otg1: power-domain@2 { - #power-domain-cells = <0>; - reg = ; - }; - - pgc_otg2: power-domain@3 { - #power-domain-cells = <0>; - reg = ; - }; - - pgc_ddr1: power-domain@4 { - #power-domain-cells = <0>; - reg = ; - }; - - pgc_gpu: power-domain@5 { - #power-domain-cells = <0>; - reg = ; - clocks = <&clk IMX8MQ_CLK_GPU_ROOT>, - <&clk IMX8MQ_CLK_GPU_SHADER_DIV>, - <&clk IMX8MQ_CLK_GPU_AXI>, - <&clk IMX8MQ_CLK_GPU_AHB>; - }; - - pgc_vpu: power-domain@6 { - #power-domain-cells = <0>; - reg = ; - }; - - pgc_disp: power-domain@7 { - #power-domain-cells = <0>; - reg = ; - }; - - pgc_mipi_csi1: power-domain@8 { - #power-domain-cells = <0>; - reg = ; - }; - - pgc_mipi_csi2: power-domain@9 { - #power-domain-cells = <0>; - reg = ; - }; - - pgc_pcie2: power-domain@a { - #power-domain-cells = <0>; - reg = ; - }; - }; - }; - }; - - bus@30400000 { /* AIPS2 */ - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x30400000 0x30400000 0x400000>; - - pwm1: pwm@30660000 { - compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm"; - reg = <0x30660000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MQ_CLK_PWM1_ROOT>, - <&clk IMX8MQ_CLK_PWM1_ROOT>; - clock-names = "ipg", "per"; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm2: pwm@30670000 { - compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm"; - reg = <0x30670000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MQ_CLK_PWM2_ROOT>, - <&clk IMX8MQ_CLK_PWM2_ROOT>; - clock-names = "ipg", "per"; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm3: pwm@30680000 { - compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm"; - reg = <0x30680000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MQ_CLK_PWM3_ROOT>, - <&clk IMX8MQ_CLK_PWM3_ROOT>; - clock-names = "ipg", "per"; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm4: pwm@30690000 { - compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm"; - reg = <0x30690000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MQ_CLK_PWM4_ROOT>, - <&clk IMX8MQ_CLK_PWM4_ROOT>; - clock-names = "ipg", "per"; - #pwm-cells = <2>; - status = "disabled"; - }; - - system_counter: timer@306a0000 { - compatible = "nxp,sysctr-timer"; - reg = <0x306a0000 0x20000>; - interrupts = ; - clocks = <&osc_25m>; - clock-names = "per"; - }; - }; - - bus@30800000 { /* AIPS3 */ - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x30800000 0x30800000 0x400000>, - <0x08000000 0x08000000 0x10000000>; - - ecspi1: spi@30820000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi"; - reg = <0x30820000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MQ_CLK_ECSPI1_ROOT>, - <&clk IMX8MQ_CLK_ECSPI1_ROOT>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - ecspi2: spi@30830000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi"; - reg = <0x30830000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MQ_CLK_ECSPI2_ROOT>, - <&clk IMX8MQ_CLK_ECSPI2_ROOT>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - ecspi3: spi@30840000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi"; - reg = <0x30840000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MQ_CLK_ECSPI3_ROOT>, - <&clk IMX8MQ_CLK_ECSPI3_ROOT>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart1: serial@30860000 { - compatible = "fsl,imx8mq-uart", - "fsl,imx6q-uart"; - reg = <0x30860000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MQ_CLK_UART1_ROOT>, - <&clk IMX8MQ_CLK_UART1_ROOT>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart3: serial@30880000 { - compatible = "fsl,imx8mq-uart", - "fsl,imx6q-uart"; - reg = <0x30880000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MQ_CLK_UART3_ROOT>, - <&clk IMX8MQ_CLK_UART3_ROOT>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart2: serial@30890000 { - compatible = "fsl,imx8mq-uart", - "fsl,imx6q-uart"; - reg = <0x30890000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MQ_CLK_UART2_ROOT>, - <&clk IMX8MQ_CLK_UART2_ROOT>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - sai2: sai@308b0000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx8mq-sai"; - reg = <0x308b0000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MQ_CLK_SAI2_IPG>, - <&clk IMX8MQ_CLK_SAI2_ROOT>, - <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dmas = <&sdma1 10 24 0>, <&sdma1 11 24 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - sai3: sai@308c0000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx8mq-sai"; - reg = <0x308c0000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MQ_CLK_SAI3_IPG>, - <&clk IMX8MQ_CLK_SAI3_ROOT>, - <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dmas = <&sdma1 12 24 0>, <&sdma1 13 24 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - crypto: crypto@30900000 { - compatible = "fsl,sec-v4.0"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x30900000 0x40000>; - ranges = <0 0x30900000 0x40000>; - interrupts = ; - clocks = <&clk IMX8MQ_CLK_AHB>, - <&clk IMX8MQ_CLK_IPG_ROOT>; - clock-names = "aclk", "ipg"; - - sec_jr0: jr@1000 { - compatible = "fsl,sec-v4.0-job-ring"; - reg = <0x1000 0x1000>; - interrupts = ; - }; - - sec_jr1: jr@2000 { - compatible = "fsl,sec-v4.0-job-ring"; - reg = <0x2000 0x1000>; - interrupts = ; - }; - - sec_jr2: jr@3000 { - compatible = "fsl,sec-v4.0-job-ring"; - reg = <0x3000 0x1000>; - interrupts = ; - }; - }; - - dphy: dphy@30a00300 { - compatible = "fsl,imx8mq-mipi-dphy"; - reg = <0x30a00300 0x100>; - clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>; - clock-names = "phy_ref"; - assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>; - assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>; - assigned-clock-rates = <24000000>; - #phy-cells = <0>; - power-domains = <&pgc_mipi>; - status = "disabled"; - }; - - i2c1: i2c@30a20000 { - compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c"; - reg = <0x30a20000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MQ_CLK_I2C1_ROOT>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@30a30000 { - compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c"; - reg = <0x30a30000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MQ_CLK_I2C2_ROOT>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c3: i2c@30a40000 { - compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c"; - reg = <0x30a40000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MQ_CLK_I2C3_ROOT>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c4: i2c@30a50000 { - compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c"; - reg = <0x30a50000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MQ_CLK_I2C4_ROOT>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - uart4: serial@30a60000 { - compatible = "fsl,imx8mq-uart", - "fsl,imx6q-uart"; - reg = <0x30a60000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MQ_CLK_UART4_ROOT>, - <&clk IMX8MQ_CLK_UART4_ROOT>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - usdhc1: mmc@30b40000 { - compatible = "fsl,imx8mq-usdhc", - "fsl,imx7d-usdhc"; - reg = <0x30b40000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, - <&clk IMX8MQ_CLK_NAND_USDHC_BUS>, - <&clk IMX8MQ_CLK_USDHC1_ROOT>; - clock-names = "ipg", "ahb", "per"; - fsl,tuning-start-tap = <20>; - fsl,tuning-step = <2>; - bus-width = <4>; - status = "disabled"; - }; - - usdhc2: mmc@30b50000 { - compatible = "fsl,imx8mq-usdhc", - "fsl,imx7d-usdhc"; - reg = <0x30b50000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, - <&clk IMX8MQ_CLK_NAND_USDHC_BUS>, - <&clk IMX8MQ_CLK_USDHC2_ROOT>; - clock-names = "ipg", "ahb", "per"; - fsl,tuning-start-tap = <20>; - fsl,tuning-step = <2>; - bus-width = <4>; - status = "disabled"; - }; - - qspi0: spi@30bb0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx8mq-qspi", "fsl,imx7d-qspi"; - reg = <0x30bb0000 0x10000>, - <0x08000000 0x10000000>; - reg-names = "QuadSPI", "QuadSPI-memory"; - interrupts = ; - clocks = <&clk IMX8MQ_CLK_QSPI_ROOT>, - <&clk IMX8MQ_CLK_QSPI_ROOT>; - clock-names = "qspi_en", "qspi"; - status = "disabled"; - }; - - sdma1: sdma@30bd0000 { - compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma"; - reg = <0x30bd0000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MQ_CLK_SDMA1_ROOT>, - <&clk IMX8MQ_CLK_AHB>; - clock-names = "ipg", "ahb"; - #dma-cells = <3>; - fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; - }; - - fec1: ethernet@30be0000 { - compatible = "fsl,imx8mq-fec", "fsl,imx6sx-fec"; - reg = <0x30be0000 0x10000>; - interrupts = , - , - ; - clocks = <&clk IMX8MQ_CLK_ENET1_ROOT>, - <&clk IMX8MQ_CLK_ENET1_ROOT>, - <&clk IMX8MQ_CLK_ENET_TIMER>, - <&clk IMX8MQ_CLK_ENET_REF>, - <&clk IMX8MQ_CLK_ENET_PHY_REF>; - clock-names = "ipg", "ahb", "ptp", - "enet_clk_ref", "enet_out"; - fsl,num-tx-queues = <3>; - fsl,num-rx-queues = <3>; - status = "disabled"; - }; - }; - - bus@32c00000 { /* AIPS4 */ - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x32c00000 0x32c00000 0x400000>; - - irqsteer: interrupt-controller@32e2d000 { - compatible = "fsl,imx8m-irqsteer", "fsl,imx-irqsteer"; - reg = <0x32e2d000 0x1000>; - interrupts = ; - clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>; - clock-names = "ipg"; - fsl,channel = <0>; - fsl,num-irqs = <64>; - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - gpu: gpu@38000000 { - compatible = "vivante,gc"; - reg = <0x38000000 0x40000>; - interrupts = ; - clocks = <&clk IMX8MQ_CLK_GPU_ROOT>, - <&clk IMX8MQ_CLK_GPU_SHADER_DIV>, - <&clk IMX8MQ_CLK_GPU_AXI>, - <&clk IMX8MQ_CLK_GPU_AHB>; - clock-names = "core", "shader", "bus", "reg"; - #cooling-cells = <2>; - assigned-clocks = <&clk IMX8MQ_CLK_GPU_CORE_SRC>, - <&clk IMX8MQ_CLK_GPU_SHADER_SRC>, - <&clk IMX8MQ_CLK_GPU_AXI>, - <&clk IMX8MQ_CLK_GPU_AHB>, - <&clk IMX8MQ_GPU_PLL_BYPASS>; - assigned-clock-parents = <&clk IMX8MQ_GPU_PLL_OUT>, - <&clk IMX8MQ_GPU_PLL_OUT>, - <&clk IMX8MQ_GPU_PLL_OUT>, - <&clk IMX8MQ_GPU_PLL_OUT>, - <&clk IMX8MQ_GPU_PLL>; - assigned-clock-rates = <800000000>, <800000000>, - <800000000>, <800000000>, <0>; - power-domains = <&pgc_gpu>; - }; - - usb_dwc3_0: usb@38100000 { - compatible = "fsl,imx8mq-dwc3", "snps,dwc3"; - reg = <0x38100000 0x10000>; - clocks = <&clk IMX8MQ_CLK_USB1_CTRL_ROOT>, - <&clk IMX8MQ_CLK_USB_CORE_REF>, - <&clk IMX8MQ_CLK_32K>; - clock-names = "bus_early", "ref", "suspend"; - assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>, - <&clk IMX8MQ_CLK_USB_CORE_REF>; - assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>, - <&clk IMX8MQ_SYS1_PLL_100M>; - assigned-clock-rates = <500000000>, <100000000>; - interrupts = ; - phys = <&usb3_phy0>, <&usb3_phy0>; - phy-names = "usb2-phy", "usb3-phy"; - power-domains = <&pgc_otg1>; - usb3-resume-missing-cas; - status = "disabled"; - }; - - usb3_phy0: usb-phy@381f0040 { - compatible = "fsl,imx8mq-usb-phy"; - reg = <0x381f0040 0x40>; - clocks = <&clk IMX8MQ_CLK_USB1_PHY_ROOT>; - clock-names = "phy"; - assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>; - assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>; - assigned-clock-rates = <100000000>; - #phy-cells = <0>; - status = "disabled"; - }; - - usb_dwc3_1: usb@38200000 { - compatible = "fsl,imx8mq-dwc3", "snps,dwc3"; - reg = <0x38200000 0x10000>; - clocks = <&clk IMX8MQ_CLK_USB2_CTRL_ROOT>, - <&clk IMX8MQ_CLK_USB_CORE_REF>, - <&clk IMX8MQ_CLK_32K>; - clock-names = "bus_early", "ref", "suspend"; - assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>, - <&clk IMX8MQ_CLK_USB_CORE_REF>; - assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>, - <&clk IMX8MQ_SYS1_PLL_100M>; - assigned-clock-rates = <500000000>, <100000000>; - interrupts = ; - phys = <&usb3_phy1>, <&usb3_phy1>; - phy-names = "usb2-phy", "usb3-phy"; - power-domains = <&pgc_otg2>; - usb3-resume-missing-cas; - status = "disabled"; - }; - - usb3_phy1: usb-phy@382f0040 { - compatible = "fsl,imx8mq-usb-phy"; - reg = <0x382f0040 0x40>; - clocks = <&clk IMX8MQ_CLK_USB2_PHY_ROOT>; - clock-names = "phy"; - assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>; - assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>; - assigned-clock-rates = <100000000>; - #phy-cells = <0>; - status = "disabled"; - }; - - pcie0: pcie@33800000 { - compatible = "fsl,imx8mq-pcie"; - reg = <0x33800000 0x400000>, - <0x1ff00000 0x80000>; - reg-names = "dbi", "config"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - bus-range = <0x00 0xff>; - ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */ - 0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */ - num-lanes = <1>; - num-viewport = <4>; - interrupts = ; - interrupt-names = "msi"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; - fsl,max-link-speed = <2>; - power-domains = <&pgc_pcie>; - resets = <&src IMX8MQ_RESET_PCIEPHY>, - <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>, - <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>; - reset-names = "pciephy", "apps", "turnoff"; - status = "disabled"; - }; - - pcie1: pcie@33c00000 { - compatible = "fsl,imx8mq-pcie"; - reg = <0x33c00000 0x400000>, - <0x27f00000 0x80000>; - reg-names = "dbi", "config"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges = <0x81000000 0 0x00000000 0x27f80000 0 0x00010000 /* downstream I/O 64KB */ - 0x82000000 0 0x20000000 0x20000000 0 0x07f00000>; /* non-prefetchable memory */ - num-lanes = <1>; - num-viewport = <4>; - interrupts = ; - interrupt-names = "msi"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &gic GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &gic GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; - fsl,max-link-speed = <2>; - power-domains = <&pgc_pcie>; - resets = <&src IMX8MQ_RESET_PCIEPHY2>, - <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>, - <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>; - reset-names = "pciephy", "apps", "turnoff"; - status = "disabled"; - }; - - gic: interrupt-controller@38800000 { - compatible = "arm,gic-v3"; - reg = <0x38800000 0x10000>, /* GIC Dist */ - <0x38880000 0xc0000>, /* GICR */ - <0x31000000 0x2000>, /* GICC */ - <0x31010000 0x2000>, /* GICV */ - <0x31020000 0x2000>; /* GICH */ - #interrupt-cells = <3>; - interrupt-controller; - interrupts = ; - interrupt-parent = <&gic>; - }; - - ddrc: memory-controller@3d400000 { - compatible = "fsl,imx8mq-ddrc", "fsl,imx8m-ddrc"; - reg = <0x3d400000 0x400000>; - clock-names = "core", "pll", "alt", "apb"; - clocks = <&clk IMX8MQ_CLK_DRAM_CORE>, - <&clk IMX8MQ_DRAM_PLL_OUT>, - <&clk IMX8MQ_CLK_DRAM_ALT>, - <&clk IMX8MQ_CLK_DRAM_APB>; - }; - - ddr-pmu@3d800000 { - compatible = "fsl,imx8mq-ddr-pmu", "fsl,imx8m-ddr-pmu"; - reg = <0x3d800000 0x400000>; - interrupt-parent = <&gic>; - interrupts = ; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/freescale/imx8qxp-ai_ml.dts b/sys/gnu/dts/arm64/freescale/imx8qxp-ai_ml.dts deleted file mode 100644 index a3f8cf19597..00000000000 --- a/sys/gnu/dts/arm64/freescale/imx8qxp-ai_ml.dts +++ /dev/null @@ -1,253 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2018 Einfochips - * Copyright 2019 Linaro Ltd. - */ - -/dts-v1/; - -#include "imx8qxp.dtsi" - -/ { - model = "Einfochips i.MX8QXP AI_ML"; - compatible = "einfochips,imx8qxp-ai_ml", "fsl,imx8qxp"; - - aliases { - serial1 = &adma_lpuart1; - serial2 = &adma_lpuart2; - serial3 = &adma_lpuart3; - }; - - chosen { - stdout-path = &adma_lpuart2; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x00000000 0x80000000 0 0x80000000>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_leds>; - - user-led1 { - label = "green:user1"; - gpios = <&lsio_gpio4 16 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - - user-led2 { - label = "green:user2"; - gpios = <&lsio_gpio0 6 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "none"; - }; - - user-led3 { - label = "green:user3"; - gpios = <&lsio_gpio0 7 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc1"; - default-state = "off"; - }; - - user-led4 { - label = "green:user4"; - gpios = <&lsio_gpio4 21 GPIO_ACTIVE_HIGH>; - panic-indicator; - linux,default-trigger = "none"; - }; - - wlan-active-led { - label = "yellow:wlan"; - gpios = <&lsio_gpio4 17 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "phy0tx"; - default-state = "off"; - }; - - bt-active-led { - label = "blue:bt"; - gpios = <&lsio_gpio4 18 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "hci0-power"; - default-state = "off"; - }; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wifi_reg_on>; - reset-gpios = <&lsio_gpio3 24 GPIO_ACTIVE_LOW>; - }; -}; - -/* BT */ -&adma_lpuart0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpuart0>; - uart-has-rtscts; - status = "okay"; -}; - -/* LS-UART0 */ -&adma_lpuart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpuart1>; - status = "okay"; -}; - -/* Debug */ -&adma_lpuart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpuart2>; - status = "okay"; -}; - -/* PCI-E UART */ -&adma_lpuart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpuart3>; - status = "okay"; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy0>; - fsl,magic-packet; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - }; - }; -}; - -/* WiFi */ -&usdhc1 { - #address-cells = <1>; - #size-cells = <0>; - assigned-clocks = <&clk IMX_CONN_SDHC0_CLK>; - assigned-clock-rates = <200000000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - bus-width = <4>; - no-sd; - non-removable; - mmc-pwrseq = <&sdio_pwrseq>; - status = "okay"; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - }; -}; - -/* SD */ -&usdhc2 { - assigned-clocks = <&clk IMX_CONN_SDHC1_CLK>; - assigned-clock-rates = <200000000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - bus-width = <4>; - cd-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&iomuxc { - pinctrl_fec1: fec1grp { - fsl,pins = < - IMX8QXP_ENET0_MDC_CONN_ENET0_MDC 0x06000020 - IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 - IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020 - IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020 - IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020 - IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020 - IMX8QXP_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020 - IMX8QXP_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020 - IMX8QXP_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020 - IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020 - IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020 - IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020 - IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020 - IMX8QXP_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020 - >; - }; - - pinctrl_leds: ledsgrp{ - fsl,pins = < - IMX8QXP_ESAI0_TX2_RX3_LSIO_GPIO0_IO06 0x00000021 - IMX8QXP_ESAI0_TX3_RX2_LSIO_GPIO0_IO07 0x00000021 - IMX8QXP_EMMC0_DATA7_LSIO_GPIO4_IO16 0x00000021 - IMX8QXP_USDHC1_WP_LSIO_GPIO4_IO21 0x00000021 - IMX8QXP_EMMC0_STROBE_LSIO_GPIO4_IO17 0x00000021 - IMX8QXP_EMMC0_RESET_B_LSIO_GPIO4_IO18 0x00000021 - >; - }; - - pinctrl_lpuart0: lpuart0grp { - fsl,pins = < - IMX8QXP_UART0_RX_ADMA_UART0_RX 0X06000020 - IMX8QXP_UART0_TX_ADMA_UART0_TX 0X06000020 - IMX8QXP_FLEXCAN0_TX_ADMA_UART0_CTS_B 0x06000020 - IMX8QXP_FLEXCAN0_RX_ADMA_UART0_RTS_B 0x06000020 - >; - }; - - pinctrl_lpuart1: lpuart1grp { - fsl,pins = < - IMX8QXP_UART1_RX_ADMA_UART1_RX 0X06000020 - IMX8QXP_UART1_TX_ADMA_UART1_TX 0X06000020 - >; - }; - - pinctrl_lpuart2: lpuart2grp { - fsl,pins = < - IMX8QXP_UART2_RX_ADMA_UART2_RX 0X06000020 - IMX8QXP_UART2_TX_ADMA_UART2_TX 0X06000020 - >; - }; - - pinctrl_lpuart3: lpuart3grp { - fsl,pins = < - IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX 0X06000020 - IMX8QXP_FLEXCAN2_TX_ADMA_UART3_TX 0X06000020 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 - IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 - IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 - IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 - IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 - IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 - IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 - IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 - IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 - IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 - IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 - IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 - IMX8QXP_USDHC1_CD_B_LSIO_GPIO4_IO22 0x00000021 - >; - }; - - pinctrl_wifi_reg_on: wifiregongrp { - fsl,pins = < - IMX8QXP_QSPI0B_SS1_B_LSIO_GPIO3_IO24 0x00000021 - >; - }; -}; diff --git a/sys/gnu/dts/arm64/freescale/imx8qxp-colibri-eval-v3.dts b/sys/gnu/dts/arm64/freescale/imx8qxp-colibri-eval-v3.dts deleted file mode 100644 index 6b21a295c12..00000000000 --- a/sys/gnu/dts/arm64/freescale/imx8qxp-colibri-eval-v3.dts +++ /dev/null @@ -1,15 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -/* - * Copyright 2019 Toradex - */ - -/dts-v1/; - -#include "imx8qxp-colibri.dtsi" -#include "imx8qxp-colibri-eval-v3.dtsi" - -/ { - model = "Toradex Colibri iMX8QXP/DX on Colibri Evaluation Board V3"; - compatible = "toradex,colibri-imx8x-eval-v3", - "toradex,colibri-imx8x", "fsl,imx8qxp"; -}; diff --git a/sys/gnu/dts/arm64/freescale/imx8qxp-colibri-eval-v3.dtsi b/sys/gnu/dts/arm64/freescale/imx8qxp-colibri-eval-v3.dtsi deleted file mode 100644 index c7336f38760..00000000000 --- a/sys/gnu/dts/arm64/freescale/imx8qxp-colibri-eval-v3.dtsi +++ /dev/null @@ -1,62 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -/* - * Copyright 2019 Toradex - */ - -#include "dt-bindings/input/linux-event-codes.h" - -/ { - aliases { - rtc0 = &rtc_i2c; - rtc1 = &rtc; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpiokeys>; - - wakeup { - label = "Wake-Up"; - gpios = <&lsio_gpio3 10 GPIO_ACTIVE_HIGH>; - linux,code = ; - debounce-interval = <10>; - wakeup-source; - }; - }; -}; - -&adma_i2c1 { - status = "okay"; - - /* M41T0M6 real time clock on carrier board */ - rtc_i2c: rtc@68 { - compatible = "st,m41t0"; - reg = <0x68>; - }; -}; - -/* Colibri UART_B */ -&adma_lpuart0 { - status= "okay"; -}; - -/* Colibri UART_C */ -&adma_lpuart2 { - status= "okay"; -}; - -/* Colibri UART_A */ -&adma_lpuart3 { - status= "okay"; -}; - -/* Colibri FastEthernet */ -&fec1 { - status = "okay"; -}; - -/* Colibri SD/MMC Card */ -&usdhc2 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/freescale/imx8qxp-colibri.dtsi b/sys/gnu/dts/arm64/freescale/imx8qxp-colibri.dtsi deleted file mode 100644 index 75f17a29f81..00000000000 --- a/sys/gnu/dts/arm64/freescale/imx8qxp-colibri.dtsi +++ /dev/null @@ -1,598 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -/* - * Copyright 2019 Toradex - */ - -#include "imx8qxp.dtsi" - -/ { - model = "Toradex Colibri iMX8QXP/DX Module"; - compatible = "toradex,colibri-imx8x", "fsl,imx8qxp"; - - chosen { - stdout-path = &adma_lpuart3; - }; - - reg_module_3v3: regulator-module-3v3 { - compatible = "regulator-fixed"; - regulator-name = "+V3.3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -/* On-module I2C */ -&adma_i2c0 { - #address-cells = <1>; - #size-cells = <0>; - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>, <&pinctrl_sgtl5000_usb_clk>; - status = "okay"; - - /* Touch controller */ - touchscreen@2c { - compatible = "adi,ad7879-1"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ad7879_int>; - reg = <0x2c>; - interrupt-parent = <&lsio_gpio3>; - interrupts = <5 IRQ_TYPE_EDGE_FALLING>; - touchscreen-max-pressure = <4096>; - adi,resistance-plate-x = <120>; - adi,first-conversion-delay = /bits/ 8 <3>; - adi,acquisition-time = /bits/ 8 <1>; - adi,median-filter-size = /bits/ 8 <2>; - adi,averaging = /bits/ 8 <1>; - adi,conversion-interval = /bits/ 8 <255>; - }; -}; - -/* Colibri I2C */ -&adma_i2c1 { - #address-cells = <1>; - #size-cells = <0>; - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; -}; - -/* Colibri UART_B */ -&adma_lpuart0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpuart0>; -}; - -/* Colibri UART_C */ -&adma_lpuart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpuart2>; -}; - -/* Colibri UART_A */ -&adma_lpuart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpuart3>, <&pinctrl_lpuart3_ctrl>; -}; - -/* Colibri FastEthernet */ -&fec1 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&pinctrl_fec1>; - pinctrl-1 = <&pinctrl_fec1_sleep>; - phy-mode = "rmii"; - phy-handle = <ðphy0>; - fsl,magic-packet; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@2 { - compatible = "ethernet-phy-ieee802.3-c22"; - max-speed = <100>; - reg = <2>; - }; - }; -}; - -/* On-module eMMC */ -&usdhc1 { - bus-width = <8>; - non-removable; - no-sd; - no-sdio; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>; - status = "okay"; -}; - -/* Colibri SD/MMC Card */ -&usdhc2 { - bus-width = <4>; - cd-gpios = <&lsio_gpio3 9 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_module_3v3>; - pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>; - disable-wp; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ext_io0>, <&pinctrl_hog0>, <&pinctrl_hog1>; - - /* On-module touch pen-down interrupt */ - pinctrl_ad7879_int: ad7879intgrp { - fsl,pins = < - IMX8QXP_MIPI_CSI0_I2C0_SCL_LSIO_GPIO3_IO05 0x21 - >; - }; - - /* Colibri Analogue Inputs */ - pinctrl_adc0: adc0grp { - fsl,pins = < - IMX8QXP_ADC_IN0_ADMA_ADC_IN0 0x60 /* SODIMM 8 */ - IMX8QXP_ADC_IN1_ADMA_ADC_IN1 0x60 /* SODIMM 6 */ - IMX8QXP_ADC_IN4_ADMA_ADC_IN4 0x60 /* SODIMM 4 */ - IMX8QXP_ADC_IN5_ADMA_ADC_IN5 0x60 /* SODIMM 2 */ - >; - }; - - pinctrl_can_int: canintgrp { - fsl,pins = < - IMX8QXP_QSPI0A_DQS_LSIO_GPIO3_IO13 0x40 /* SODIMM 73 */ - >; - }; - - pinctrl_csi_ctl: csictlgrp { - fsl,pins = < - IMX8QXP_QSPI0A_SS0_B_LSIO_GPIO3_IO14 0x20 /* SODIMM 77 */ - IMX8QXP_QSPI0A_SS1_B_LSIO_GPIO3_IO15 0x20 /* SODIMM 89 */ - >; - }; - - pinctrl_ext_io0: extio0grp { - fsl,pins = < - IMX8QXP_ENET0_RGMII_RXD3_LSIO_GPIO5_IO08 0x06000040 /* SODIMM 135 */ - >; - }; - - /* Colibri Ethernet: On-module 100Mbps PHY Micrel KSZ8041 */ - pinctrl_fec1: fec1grp { - fsl,pins = < - IMX8QXP_ENET0_MDC_CONN_ENET0_MDC 0x06000020 - IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 - IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x61 - IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT 0x06000061 - IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x61 - IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x61 - IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x61 - IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x61 - IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x61 - IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER 0x61 - >; - }; - - pinctrl_fec1_sleep: fec1slpgrp { - fsl,pins = < - IMX8QXP_ENET0_MDC_LSIO_GPIO5_IO11 0x06000041 - IMX8QXP_ENET0_MDIO_LSIO_GPIO5_IO10 0x06000041 - IMX8QXP_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30 0x41 - IMX8QXP_ENET0_RGMII_TXC_LSIO_GPIO4_IO29 0x41 - IMX8QXP_ENET0_RGMII_TXD0_LSIO_GPIO4_IO31 0x41 - IMX8QXP_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00 0x41 - IMX8QXP_ENET0_RGMII_RX_CTL_LSIO_GPIO5_IO04 0x41 - IMX8QXP_ENET0_RGMII_RXD0_LSIO_GPIO5_IO05 0x41 - IMX8QXP_ENET0_RGMII_RXD1_LSIO_GPIO5_IO06 0x41 - IMX8QXP_ENET0_RGMII_RXD2_LSIO_GPIO5_IO07 0x41 - >; - }; - - /* Colibri optional CAN on UART_B RTS/CTS */ - pinctrl_flexcan1: flexcan0grp { - fsl,pins = < - IMX8QXP_FLEXCAN0_TX_ADMA_FLEXCAN0_TX 0x21 /* SODIMM 32 */ - IMX8QXP_FLEXCAN0_RX_ADMA_FLEXCAN0_RX 0x21 /* SODIMM 34 */ - >; - }; - - /* Colibri optional CAN on PS2 */ - pinctrl_flexcan2: flexcan1grp { - fsl,pins = < - IMX8QXP_FLEXCAN1_TX_ADMA_FLEXCAN1_TX 0x21 /* SODIMM 55 */ - IMX8QXP_FLEXCAN1_RX_ADMA_FLEXCAN1_RX 0x21 /* SODIMM 63 */ - >; - }; - - /* Colibri optional CAN on UART_A TXD/RXD */ - pinctrl_flexcan3: flexcan2grp { - fsl,pins = < - IMX8QXP_FLEXCAN2_TX_ADMA_FLEXCAN2_TX 0x21 /* SODIMM 35 */ - IMX8QXP_FLEXCAN2_RX_ADMA_FLEXCAN2_RX 0x21 /* SODIMM 33 */ - >; - }; - - /* Colibri LCD Back-Light GPIO */ - pinctrl_gpio_bl_on: gpioblongrp { - fsl,pins = < - IMX8QXP_QSPI0A_DATA3_LSIO_GPIO3_IO12 0x60 /* SODIMM 71 */ - >; - }; - - pinctrl_gpiokeys: gpiokeysgrp { - fsl,pins = < - IMX8QXP_QSPI0A_DATA1_LSIO_GPIO3_IO10 0x06700041 /* SODIMM 45 */ - >; - }; - - pinctrl_hog0: hog0grp { - fsl,pins = < - IMX8QXP_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02 0x06000020 /* SODIMM 65 */ - IMX8QXP_CSI_D07_CI_PI_D09 0x61 /* SODIMM 65 */ - IMX8QXP_QSPI0A_DATA2_LSIO_GPIO3_IO11 0x20 /* SODIMM 69 */ - IMX8QXP_SAI0_TXC_LSIO_GPIO0_IO26 0x20 /* SODIMM 79 */ - IMX8QXP_CSI_D02_CI_PI_D04 0x61 /* SODIMM 79 */ - IMX8QXP_ENET0_RGMII_RXC_LSIO_GPIO5_IO03 0x06000020 /* SODIMM 85 */ - IMX8QXP_CSI_D06_CI_PI_D08 0x61 /* SODIMM 85 */ - IMX8QXP_QSPI0B_SCLK_LSIO_GPIO3_IO17 0x20 /* SODIMM 95 */ - IMX8QXP_SAI0_RXD_LSIO_GPIO0_IO27 0x20 /* SODIMM 97 */ - IMX8QXP_CSI_D03_CI_PI_D05 0x61 /* SODIMM 97 */ - IMX8QXP_QSPI0B_DATA0_LSIO_GPIO3_IO18 0x20 /* SODIMM 99 */ - IMX8QXP_SAI0_TXFS_LSIO_GPIO0_IO28 0x20 /* SODIMM 101 */ - IMX8QXP_CSI_D00_CI_PI_D02 0x61 /* SODIMM 101 */ - IMX8QXP_SAI0_TXD_LSIO_GPIO0_IO25 0x20 /* SODIMM 103 */ - IMX8QXP_CSI_D01_CI_PI_D03 0x61 /* SODIMM 103 */ - IMX8QXP_QSPI0B_DATA1_LSIO_GPIO3_IO19 0x20 /* SODIMM 105 */ - IMX8QXP_QSPI0B_DATA2_LSIO_GPIO3_IO20 0x20 /* SODIMM 107 */ - IMX8QXP_USB_SS3_TC2_LSIO_GPIO4_IO05 0x20 /* SODIMM 127 */ - IMX8QXP_USB_SS3_TC3_LSIO_GPIO4_IO06 0x20 /* SODIMM 131 */ - IMX8QXP_USB_SS3_TC1_LSIO_GPIO4_IO04 0x20 /* SODIMM 133 */ - IMX8QXP_CSI_PCLK_LSIO_GPIO3_IO00 0x20 /* SODIMM 96 */ - IMX8QXP_QSPI0B_DATA3_LSIO_GPIO3_IO21 0x20 /* SODIMM 98 */ - IMX8QXP_SAI1_RXFS_LSIO_GPIO0_IO31 0x20 /* SODIMM 100 */ - IMX8QXP_QSPI0B_DQS_LSIO_GPIO3_IO22 0x20 /* SODIMM 102 */ - IMX8QXP_QSPI0B_SS0_B_LSIO_GPIO3_IO23 0x20 /* SODIMM 104 */ - IMX8QXP_QSPI0B_SS1_B_LSIO_GPIO3_IO24 0x20 /* SODIMM 106 */ - >; - }; - - pinctrl_hog1: hog1grp { - fsl,pins = < - IMX8QXP_CSI_MCLK_LSIO_GPIO3_IO01 0x20 /* SODIMM 75 */ - IMX8QXP_QSPI0A_SCLK_LSIO_GPIO3_IO16 0x20 /* SODIMM 93 */ - >; - }; - - /* - * This pin is used in the SCFW as a UART. Using it from - * Linux would require rewritting the SCFW board file. - */ - pinctrl_hog_scfw: hogscfwgrp { - fsl,pins = < - IMX8QXP_SCU_GPIO0_00_LSIO_GPIO2_IO03 0x20 /* SODIMM 144 */ - >; - }; - - /* On Module I2C */ - pinctrl_i2c0: i2c0grp { - fsl,pins = < - IMX8QXP_MIPI_CSI0_GPIO0_00_ADMA_I2C0_SCL 0x06000021 - IMX8QXP_MIPI_CSI0_GPIO0_01_ADMA_I2C0_SDA 0x06000021 - >; - }; - - /* MIPI DSI I2C accessible on SODIMM (X1) and FFC (X2) */ - pinctrl_i2c0_mipi_lvds0: i2c0mipilvds0grp { - fsl,pins = < - IMX8QXP_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc6000020 /* SODIMM 140 */ - IMX8QXP_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc6000020 /* SODIMM 142 */ - >; - }; - - /* MIPI CSI I2C accessible on SODIMM (X1) and FFC (X3) */ - pinctrl_i2c0_mipi_lvds1: i2c0mipilvds1grp { - fsl,pins = < - IMX8QXP_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc6000020 /* SODIMM 186 */ - IMX8QXP_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc6000020 /* SODIMM 188 */ - >; - }; - - /* Colibri I2C */ - pinctrl_i2c1: i2c1grp { - fsl,pins = < - IMX8QXP_MIPI_DSI0_GPIO0_00_ADMA_I2C1_SCL 0x06000021 /* SODIMM 196 */ - IMX8QXP_MIPI_DSI0_GPIO0_01_ADMA_I2C1_SDA 0x06000021 /* SODIMM 194 */ - >; - }; - - /* Colibri Parallel RGB LCD Interface */ - pinctrl_lcdif: lcdifgrp { - fsl,pins = < - IMX8QXP_MCLK_OUT0_ADMA_LCDIF_CLK 0x60 /* SODIMM 56 */ - IMX8QXP_SPI3_CS0_ADMA_LCDIF_HSYNC 0x60 /* SODIMM 68 */ - IMX8QXP_MCLK_IN0_ADMA_LCDIF_VSYNC 0x60 /* SODIMM 82 */ - IMX8QXP_MCLK_IN1_ADMA_LCDIF_EN 0x60 /* SODIMM 44 */ - IMX8QXP_USDHC1_RESET_B_LSIO_GPIO4_IO19 0x60 /* SODIMM 44 */ - IMX8QXP_ESAI0_FSR_ADMA_LCDIF_D00 0x60 /* SODIMM 76 */ - IMX8QXP_USDHC1_WP_LSIO_GPIO4_IO21 0x60 /* SODIMM 76 */ - IMX8QXP_ESAI0_FST_ADMA_LCDIF_D01 0x60 /* SODIMM 70 */ - IMX8QXP_ESAI0_SCKR_ADMA_LCDIF_D02 0x60 /* SODIMM 60 */ - IMX8QXP_ESAI0_SCKT_ADMA_LCDIF_D03 0x60 /* SODIMM 58 */ - IMX8QXP_ESAI0_TX0_ADMA_LCDIF_D04 0x60 /* SODIMM 78 */ - IMX8QXP_ESAI0_TX1_ADMA_LCDIF_D05 0x60 /* SODIMM 72 */ - IMX8QXP_ESAI0_TX2_RX3_ADMA_LCDIF_D06 0x60 /* SODIMM 80 */ - IMX8QXP_ESAI0_TX3_RX2_ADMA_LCDIF_D07 0x60 /* SODIMM 46 */ - IMX8QXP_ESAI0_TX4_RX1_ADMA_LCDIF_D08 0x60 /* SODIMM 62 */ - IMX8QXP_ESAI0_TX5_RX0_ADMA_LCDIF_D09 0x60 /* SODIMM 48 */ - IMX8QXP_SPDIF0_RX_ADMA_LCDIF_D10 0x60 /* SODIMM 74 */ - IMX8QXP_SPDIF0_TX_ADMA_LCDIF_D11 0x60 /* SODIMM 50 */ - IMX8QXP_SPDIF0_EXT_CLK_ADMA_LCDIF_D12 0x60 /* SODIMM 52 */ - IMX8QXP_SPI3_SCK_ADMA_LCDIF_D13 0x60 /* SODIMM 54 */ - IMX8QXP_SPI3_SDO_ADMA_LCDIF_D14 0x60 /* SODIMM 66 */ - IMX8QXP_SPI3_SDI_ADMA_LCDIF_D15 0x60 /* SODIMM 64 */ - IMX8QXP_SPI3_CS1_ADMA_LCDIF_D16 0x60 /* SODIMM 57 */ - IMX8QXP_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 0x60 /* SODIMM 57 */ - IMX8QXP_UART1_CTS_B_ADMA_LCDIF_D17 0x60 /* SODIMM 61 */ - >; - }; - - /* Colibri SPI */ - pinctrl_lpspi2: lpspi2grp { - fsl,pins = < - IMX8QXP_SPI2_CS0_LSIO_GPIO1_IO00 0x21 /* SODIMM 86 */ - IMX8QXP_SPI2_SDO_ADMA_SPI2_SDO 0x06000040 /* SODIMM 92 */ - IMX8QXP_SPI2_SDI_ADMA_SPI2_SDI 0x06000040 /* SODIMM 90 */ - IMX8QXP_SPI2_SCK_ADMA_SPI2_SCK 0x06000040 /* SODIMM 88 */ - >; - }; - - /* Colibri UART_B */ - pinctrl_lpuart0: lpuart0grp { - fsl,pins = < - IMX8QXP_UART0_RX_ADMA_UART0_RX 0x06000020 /* SODIMM 36 */ - IMX8QXP_UART0_TX_ADMA_UART0_TX 0x06000020 /* SODIMM 38 */ - IMX8QXP_FLEXCAN0_RX_ADMA_UART0_RTS_B 0x06000020 /* SODIMM 34 */ - IMX8QXP_FLEXCAN0_TX_ADMA_UART0_CTS_B 0x06000020 /* SODIMM 32 */ - >; - }; - - /* Colibri UART_C */ - pinctrl_lpuart2: lpuart2grp { - fsl,pins = < - IMX8QXP_UART2_RX_ADMA_UART2_RX 0x06000020 /* SODIMM 19 */ - IMX8QXP_UART2_TX_ADMA_UART2_TX 0x06000020 /* SODIMM 21 */ - >; - }; - - /* Colibri UART_A */ - pinctrl_lpuart3: lpuart3grp { - fsl,pins = < - IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX 0x06000020 /* SODIMM 33 */ - IMX8QXP_FLEXCAN2_TX_ADMA_UART3_TX 0x06000020 /* SODIMM 35 */ - >; - }; - - /* Colibri UART_A Control */ - pinctrl_lpuart3_ctrl: lpuart3ctrlgrp { - fsl,pins = < - IMX8QXP_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00 0x20 /* SODIMM 23 */ - IMX8QXP_SAI1_RXD_LSIO_GPIO0_IO29 0x20 /* SODIMM 25 */ - IMX8QXP_SAI1_RXC_LSIO_GPIO0_IO30 0x20 /* SODIMM 27 */ - IMX8QXP_CSI_RESET_LSIO_GPIO3_IO03 0x20 /* SODIMM 29 */ - IMX8QXP_USDHC1_CD_B_LSIO_GPIO4_IO22 0x20 /* SODIMM 31 */ - IMX8QXP_CSI_EN_LSIO_GPIO3_IO02 0x20 /* SODIMM 37 */ - >; - }; - - /* On module wifi module */ - pinctrl_pcieb: pciebgrp { - fsl,pins = < - IMX8QXP_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x04000061 /* SODIMM 178 */ - IMX8QXP_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x04000061 /* SODIMM 94 */ - IMX8QXP_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x60 /* SODIMM 81 */ - >; - }; - - /* Colibri PWM_A */ - pinctrl_pwm_a: pwmagrp { - /* both pins are connected together, reserve the unused CSI_D05 */ - fsl,pins = < - IMX8QXP_CSI_D05_CI_PI_D07 0x61 /* SODIMM 59 */ - IMX8QXP_SPI0_CS1_ADMA_LCD_PWM0_OUT 0x60 /* SODIMM 59 */ - >; - }; - - /* Colibri PWM_B */ - pinctrl_pwm_b: pwmbgrp { - fsl,pins = < - IMX8QXP_UART1_TX_LSIO_PWM0_OUT 0x60 /* SODIMM 28 */ - >; - }; - - /* Colibri PWM_C */ - pinctrl_pwm_c: pwmcgrp { - fsl,pins = < - IMX8QXP_UART1_RX_LSIO_PWM1_OUT 0x60 /* SODIMM 30 */ - >; - }; - - /* Colibri PWM_D */ - pinctrl_pwm_d: pwmdgrp { - /* both pins are connected together, reserve the unused CSI_D04 */ - fsl,pins = < - IMX8QXP_CSI_D04_CI_PI_D06 0x61 /* SODIMM 67 */ - IMX8QXP_UART1_RTS_B_LSIO_PWM2_OUT 0x60 /* SODIMM 67 */ - >; - }; - - /* On-module I2S */ - pinctrl_sai0: sai0grp { - fsl,pins = < - IMX8QXP_SPI0_SDI_ADMA_SAI0_TXD 0x06000040 - IMX8QXP_SPI0_CS0_ADMA_SAI0_RXD 0x06000040 - IMX8QXP_SPI0_SCK_ADMA_SAI0_TXC 0x06000040 - IMX8QXP_SPI0_SDO_ADMA_SAI0_TXFS 0x06000040 - >; - }; - - /* Colibri Audio Analogue Microphone GND */ - pinctrl_sgtl5000: sgtl5000grp { - fsl,pins = < - /* MIC GND EN */ - IMX8QXP_MIPI_CSI0_I2C0_SDA_LSIO_GPIO3_IO06 0x41 - >; - }; - - /* On-module SGTL5000 clock */ - pinctrl_sgtl5000_usb_clk: sgtl5000usbclkgrp { - fsl,pins = < - IMX8QXP_ADC_IN3_ADMA_ACM_MCLK_OUT0 0x21 - >; - }; - - /* On-module USB interrupt */ - pinctrl_usb3503a: usb3503agrp { - fsl,pins = < - IMX8QXP_MIPI_CSI0_MCLK_OUT_LSIO_GPIO3_IO04 0x61 - >; - }; - - /* Colibri USB Client Cable Detect */ - pinctrl_usbc_det: usbcdetgrp { - fsl,pins = < - IMX8QXP_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 0x06000040 /* SODIMM 137 */ - >; - }; - - /* USB Host Power Enable */ - pinctrl_usbh1_reg: usbh1reggrp { - fsl,pins = < - IMX8QXP_USB_SS3_TC0_LSIO_GPIO4_IO03 0x06000040 /* SODIMM 129 */ - >; - }; - - /* On-module eMMC */ - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 - IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x21 - IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21 - IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21 - IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21 - IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21 - IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21 - IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21 - IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21 - IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21 - IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41 - IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21 - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1grp100mhz { - fsl,pins = < - IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 - IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x21 - IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21 - IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21 - IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21 - IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21 - IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21 - IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21 - IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21 - IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21 - IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41 - IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21 - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1grp200mhz { - fsl,pins = < - IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 - IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x21 - IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21 - IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21 - IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21 - IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21 - IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21 - IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21 - IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21 - IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21 - IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41 - IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21 - >; - }; - - /* Colibri SD/MMC Card Detect */ - pinctrl_usdhc2_gpio: usdhc2gpiogrp { - fsl,pins = < - IMX8QXP_QSPI0A_DATA0_LSIO_GPIO3_IO09 0x06000021 /* SODIMM 43 */ - >; - }; - - pinctrl_usdhc2_gpio_sleep: usdhc2gpioslpgrp { - fsl,pins = < - IMX8QXP_QSPI0A_DATA0_LSIO_GPIO3_IO09 0x60 /* SODIMM 43 */ - >; - }; - - /* Colibri SD/MMC Card */ - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 /* SODIMM 47 */ - IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x21 /* SODIMM 190 */ - IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21 /* SODIMM 192 */ - IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21 /* SODIMM 49 */ - IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21 /* SODIMM 51 */ - IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21 /* SODIMM 53 */ - IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2grp100mhz { - fsl,pins = < - IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 /* SODIMM 47 */ - IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x21 /* SODIMM 190 */ - IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21 /* SODIMM 192 */ - IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21 /* SODIMM 49 */ - IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21 /* SODIMM 51 */ - IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21 /* SODIMM 53 */ - IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2grp200mhz { - fsl,pins = < - IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 /* SODIMM 47 */ - IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x21 /* SODIMM 190 */ - IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21 /* SODIMM 192 */ - IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21 /* SODIMM 49 */ - IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21 /* SODIMM 51 */ - IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21 /* SODIMM 53 */ - IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21 - >; - }; - - pinctrl_usdhc2_sleep: usdhc2slpgrp { - fsl,pins = < - IMX8QXP_USDHC1_CLK_LSIO_GPIO4_IO23 0x60 /* SODIMM 47 */ - IMX8QXP_USDHC1_CMD_LSIO_GPIO4_IO24 0x60 /* SODIMM 190 */ - IMX8QXP_USDHC1_DATA0_LSIO_GPIO4_IO25 0x60 /* SODIMM 192 */ - IMX8QXP_USDHC1_DATA1_LSIO_GPIO4_IO26 0x60 /* SODIMM 49 */ - IMX8QXP_USDHC1_DATA2_LSIO_GPIO4_IO27 0x60 /* SODIMM 51 */ - IMX8QXP_USDHC1_DATA3_LSIO_GPIO4_IO28 0x60 /* SODIMM 53 */ - IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21 - >; - }; - - pinctrl_wifi: wifigrp { - fsl,pins = < - IMX8QXP_SCU_BOOT_MODE3_SCU_DSC_RTC_CLOCK_OUTPUT_32K 0x20 - >; - }; -}; diff --git a/sys/gnu/dts/arm64/freescale/imx8qxp-mek.dts b/sys/gnu/dts/arm64/freescale/imx8qxp-mek.dts deleted file mode 100644 index 13460a360c6..00000000000 --- a/sys/gnu/dts/arm64/freescale/imx8qxp-mek.dts +++ /dev/null @@ -1,239 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2017~2018 NXP - */ - -/dts-v1/; - -#include "imx8qxp.dtsi" - -/ { - model = "Freescale i.MX8QXP MEK"; - compatible = "fsl,imx8qxp-mek", "fsl,imx8qxp"; - - chosen { - stdout-path = &adma_lpuart0; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x00000000 0x80000000 0 0x40000000>; - }; - - reg_usdhc2_vmmc: usdhc2-vmmc { - compatible = "regulator-fixed"; - regulator-name = "SD1_SPWR"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - gpio = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&adma_lpuart0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpuart0>; - status = "okay"; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy0>; - fsl,magic-packet; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - }; - }; -}; - -&adma_i2c1 { - #address-cells = <1>; - #size-cells = <0>; - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpi2c1 &pinctrl_ioexp_rst>; - status = "okay"; - - i2c-switch@71 { - compatible = "nxp,pca9646", "nxp,pca9546"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x71>; - reset-gpios = <&lsio_gpio1 1 GPIO_ACTIVE_LOW>; - - i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - max7322: gpio@68 { - compatible = "maxim,max7322"; - reg = <0x68>; - gpio-controller; - #gpio-cells = <2>; - }; - }; - - i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - - pressure-sensor@60 { - compatible = "fsl,mpl3115"; - reg = <0x60>; - }; - }; - - i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - - pca9557_a: gpio@1a { - compatible = "nxp,pca9557"; - reg = <0x1a>; - gpio-controller; - #gpio-cells = <2>; - }; - - pca9557_b: gpio@1d { - compatible = "nxp,pca9557"; - reg = <0x1d>; - gpio-controller; - #gpio-cells = <2>; - }; - - light-sensor@44 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_isl29023>; - compatible = "isil,isl29023"; - reg = <0x44>; - interrupt-parent = <&lsio_gpio1>; - interrupts = <2 IRQ_TYPE_EDGE_FALLING>; - }; - }; - }; -}; - -&usdhc1 { - assigned-clocks = <&clk IMX_CONN_SDHC0_CLK>; - assigned-clock-rates = <200000000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - bus-width = <8>; - no-sd; - no-sdio; - non-removable; - status = "okay"; -}; - -&usdhc2 { - assigned-clocks = <&clk IMX_CONN_SDHC1_CLK>; - assigned-clock-rates = <200000000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - bus-width = <4>; - vmmc-supply = <®_usdhc2_vmmc>; - cd-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>; - wp-gpios = <&lsio_gpio4 21 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&iomuxc { - pinctrl_fec1: fec1grp { - fsl,pins = < - IMX8QXP_ENET0_MDC_CONN_ENET0_MDC 0x06000020 - IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 - IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020 - IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020 - IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020 - IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020 - IMX8QXP_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020 - IMX8QXP_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020 - IMX8QXP_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020 - IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020 - IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020 - IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020 - IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020 - IMX8QXP_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020 - >; - }; - - pinctrl_ioexp_rst: ioexp_rst_grp { - fsl,pins = < - IMX8QXP_SPI2_SDO_LSIO_GPIO1_IO01 0x06000021 - >; - }; - - pinctrl_isl29023: isl29023grp { - fsl,pins = < - IMX8QXP_SPI2_SDI_LSIO_GPIO1_IO02 0x00000021 - >; - }; - - pinctrl_lpi2c1: lpi2c1grp { - fsl,pins = < - IMX8QXP_USB_SS3_TC1_ADMA_I2C1_SCL 0x06000021 - IMX8QXP_USB_SS3_TC3_ADMA_I2C1_SDA 0x06000021 - >; - }; - - pinctrl_lpuart0: lpuart0grp { - fsl,pins = < - IMX8QXP_UART0_RX_ADMA_UART0_RX 0x06000020 - IMX8QXP_UART0_TX_ADMA_UART0_TX 0x06000020 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 - IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 - IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 - IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 - IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 - IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 - IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 - IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 - IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 - IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 - IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 - IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 - IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 - IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 - IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 - IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 - IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 - >; - }; -}; - -&adma_dsp { - status = "okay"; -}; - -&scu_key { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/freescale/imx8qxp.dtsi b/sys/gnu/dts/arm64/freescale/imx8qxp.dtsi deleted file mode 100644 index fb5f752b15f..00000000000 --- a/sys/gnu/dts/arm64/freescale/imx8qxp.dtsi +++ /dev/null @@ -1,589 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2016 Freescale Semiconductor, Inc. - * Copyright 2017-2018 NXP - * Dong Aisheng - */ - -#include -#include -#include -#include -#include -#include - -/ { - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - gpio0 = &lsio_gpio0; - gpio1 = &lsio_gpio1; - gpio2 = &lsio_gpio2; - gpio3 = &lsio_gpio3; - gpio4 = &lsio_gpio4; - gpio5 = &lsio_gpio5; - gpio6 = &lsio_gpio6; - gpio7 = &lsio_gpio7; - mmc0 = &usdhc1; - mmc1 = &usdhc2; - mmc2 = &usdhc3; - mu1 = &lsio_mu1; - serial0 = &adma_lpuart0; - serial1 = &adma_lpuart1; - serial2 = &adma_lpuart2; - serial3 = &adma_lpuart3; - }; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - /* We have 1 clusters with 4 Cortex-A35 cores */ - A35_0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a35"; - reg = <0x0 0x0>; - enable-method = "psci"; - next-level-cache = <&A35_L2>; - clocks = <&clk IMX_A35_CLK>; - operating-points-v2 = <&a35_opp_table>; - #cooling-cells = <2>; - }; - - A35_1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a35"; - reg = <0x0 0x1>; - enable-method = "psci"; - next-level-cache = <&A35_L2>; - clocks = <&clk IMX_A35_CLK>; - operating-points-v2 = <&a35_opp_table>; - #cooling-cells = <2>; - }; - - A35_2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a35"; - reg = <0x0 0x2>; - enable-method = "psci"; - next-level-cache = <&A35_L2>; - clocks = <&clk IMX_A35_CLK>; - operating-points-v2 = <&a35_opp_table>; - #cooling-cells = <2>; - }; - - A35_3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a35"; - reg = <0x0 0x3>; - enable-method = "psci"; - next-level-cache = <&A35_L2>; - clocks = <&clk IMX_A35_CLK>; - operating-points-v2 = <&a35_opp_table>; - #cooling-cells = <2>; - }; - - A35_L2: l2-cache0 { - compatible = "cache"; - }; - }; - - a35_opp_table: opp-table { - compatible = "operating-points-v2"; - opp-shared; - - opp-900000000 { - opp-hz = /bits/ 64 <900000000>; - opp-microvolt = <1000000>; - clock-latency-ns = <150000>; - }; - - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <1100000>; - clock-latency-ns = <150000>; - opp-suspend; - }; - }; - - gic: interrupt-controller@51a00000 { - compatible = "arm,gic-v3"; - reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ - <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */ - #interrupt-cells = <3>; - interrupt-controller; - interrupts = ; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - dsp_reserved: dsp@92400000 { - reg = <0 0x92400000 0 0x2000000>; - no-map; - }; - }; - - pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = ; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - scu { - compatible = "fsl,imx-scu"; - mbox-names = "tx0", "tx1", "tx2", "tx3", - "rx0", "rx1", "rx2", "rx3", - "gip3"; - mboxes = <&lsio_mu1 0 0 - &lsio_mu1 0 1 - &lsio_mu1 0 2 - &lsio_mu1 0 3 - &lsio_mu1 1 0 - &lsio_mu1 1 1 - &lsio_mu1 1 2 - &lsio_mu1 1 3 - &lsio_mu1 3 3>; - - clk: clock-controller { - compatible = "fsl,imx8qxp-clk"; - #clock-cells = <1>; - clocks = <&xtal32k &xtal24m>; - clock-names = "xtal_32KHz", "xtal_24Mhz"; - }; - - iomuxc: pinctrl { - compatible = "fsl,imx8qxp-iomuxc"; - }; - - ocotp: imx8qx-ocotp { - compatible = "fsl,imx8qxp-scu-ocotp"; - #address-cells = <1>; - #size-cells = <1>; - }; - - pd: imx8qx-pd { - compatible = "fsl,imx8qxp-scu-pd"; - #power-domain-cells = <1>; - }; - - scu_key: scu-key { - compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key"; - linux,keycodes = ; - status = "disabled"; - }; - - rtc: rtc { - compatible = "fsl,imx8qxp-sc-rtc"; - }; - - watchdog { - compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt"; - timeout-sec = <60>; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , /* Physical Secure */ - , /* Physical Non-Secure */ - , /* Virtual */ - ; /* Hypervisor */ - }; - - xtal32k: clock-xtal32k { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "xtal_32KHz"; - }; - - xtal24m: clock-xtal24m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "xtal_24MHz"; - }; - - adma_subsys: bus@59000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x59000000 0x0 0x59000000 0x2000000>; - - adma_lpcg: clock-controller@59000000 { - compatible = "fsl,imx8qxp-lpcg-adma"; - reg = <0x59000000 0x2000000>; - #clock-cells = <1>; - }; - - adma_dsp: dsp@596e8000 { - compatible = "fsl,imx8qxp-dsp"; - reg = <0x596e8000 0x88000>; - clocks = <&adma_lpcg IMX_ADMA_LPCG_DSP_IPG_CLK>, - <&adma_lpcg IMX_ADMA_LPCG_OCRAM_IPG_CLK>, - <&adma_lpcg IMX_ADMA_LPCG_DSP_CORE_CLK>; - clock-names = "ipg", "ocram", "core"; - power-domains = <&pd IMX_SC_R_MU_13A>, - <&pd IMX_SC_R_MU_13B>, - <&pd IMX_SC_R_DSP>, - <&pd IMX_SC_R_DSP_RAM>; - mbox-names = "txdb0", "txdb1", - "rxdb0", "rxdb1"; - mboxes = <&lsio_mu13 2 0>, - <&lsio_mu13 2 1>, - <&lsio_mu13 3 0>, - <&lsio_mu13 3 1>; - memory-region = <&dsp_reserved>; - status = "disabled"; - }; - - adma_lpuart0: serial@5a060000 { - compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; - reg = <0x5a060000 0x1000>; - interrupts = ; - clocks = <&adma_lpcg IMX_ADMA_LPCG_UART0_IPG_CLK>, - <&adma_lpcg IMX_ADMA_LPCG_UART0_BAUD_CLK>; - clock-names = "ipg", "baud"; - power-domains = <&pd IMX_SC_R_UART_0>; - status = "disabled"; - }; - - adma_lpuart1: serial@5a070000 { - compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; - reg = <0x5a070000 0x1000>; - interrupts = ; - clocks = <&adma_lpcg IMX_ADMA_LPCG_UART1_IPG_CLK>, - <&adma_lpcg IMX_ADMA_LPCG_UART1_BAUD_CLK>; - clock-names = "ipg", "baud"; - power-domains = <&pd IMX_SC_R_UART_1>; - status = "disabled"; - }; - - adma_lpuart2: serial@5a080000 { - compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; - reg = <0x5a080000 0x1000>; - interrupts = ; - clocks = <&adma_lpcg IMX_ADMA_LPCG_UART2_IPG_CLK>, - <&adma_lpcg IMX_ADMA_LPCG_UART2_BAUD_CLK>; - clock-names = "ipg", "baud"; - power-domains = <&pd IMX_SC_R_UART_2>; - status = "disabled"; - }; - - adma_lpuart3: serial@5a090000 { - compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; - reg = <0x5a090000 0x1000>; - interrupts = ; - clocks = <&adma_lpcg IMX_ADMA_LPCG_UART3_IPG_CLK>, - <&adma_lpcg IMX_ADMA_LPCG_UART3_BAUD_CLK>; - clock-names = "ipg", "baud"; - power-domains = <&pd IMX_SC_R_UART_3>; - status = "disabled"; - }; - - adma_i2c0: i2c@5a800000 { - compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; - reg = <0x5a800000 0x4000>; - interrupts = ; - clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C0_CLK>; - clock-names = "per"; - assigned-clocks = <&clk IMX_ADMA_I2C0_CLK>; - assigned-clock-rates = <24000000>; - power-domains = <&pd IMX_SC_R_I2C_0>; - status = "disabled"; - }; - - adma_i2c1: i2c@5a810000 { - compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; - reg = <0x5a810000 0x4000>; - interrupts = ; - clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C1_CLK>; - clock-names = "per"; - assigned-clocks = <&clk IMX_ADMA_I2C1_CLK>; - assigned-clock-rates = <24000000>; - power-domains = <&pd IMX_SC_R_I2C_1>; - status = "disabled"; - }; - - adma_i2c2: i2c@5a820000 { - compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; - reg = <0x5a820000 0x4000>; - interrupts = ; - clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C2_CLK>; - clock-names = "per"; - assigned-clocks = <&clk IMX_ADMA_I2C2_CLK>; - assigned-clock-rates = <24000000>; - power-domains = <&pd IMX_SC_R_I2C_2>; - status = "disabled"; - }; - - adma_i2c3: i2c@5a830000 { - compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; - reg = <0x5a830000 0x4000>; - interrupts = ; - clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C3_CLK>; - clock-names = "per"; - assigned-clocks = <&clk IMX_ADMA_I2C3_CLK>; - assigned-clock-rates = <24000000>; - power-domains = <&pd IMX_SC_R_I2C_3>; - status = "disabled"; - }; - }; - - conn_subsys: bus@5b000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x5b000000 0x0 0x5b000000 0x1000000>; - - conn_lpcg: clock-controller@5b200000 { - compatible = "fsl,imx8qxp-lpcg-conn"; - reg = <0x5b200000 0xb0000>; - #clock-cells = <1>; - }; - - usdhc1: mmc@5b010000 { - compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; - interrupts = ; - reg = <0x5b010000 0x10000>; - clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC0_IPG_CLK>, - <&conn_lpcg IMX_CONN_LPCG_SDHC0_PER_CLK>, - <&conn_lpcg IMX_CONN_LPCG_SDHC0_HCLK>; - clock-names = "ipg", "per", "ahb"; - power-domains = <&pd IMX_SC_R_SDHC_0>; - status = "disabled"; - }; - - usdhc2: mmc@5b020000 { - compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; - interrupts = ; - reg = <0x5b020000 0x10000>; - clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC1_IPG_CLK>, - <&conn_lpcg IMX_CONN_LPCG_SDHC1_PER_CLK>, - <&conn_lpcg IMX_CONN_LPCG_SDHC1_HCLK>; - clock-names = "ipg", "per", "ahb"; - power-domains = <&pd IMX_SC_R_SDHC_1>; - fsl,tuning-start-tap = <20>; - fsl,tuning-step= <2>; - status = "disabled"; - }; - - usdhc3: mmc@5b030000 { - compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; - interrupts = ; - reg = <0x5b030000 0x10000>; - clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC2_IPG_CLK>, - <&conn_lpcg IMX_CONN_LPCG_SDHC2_PER_CLK>, - <&conn_lpcg IMX_CONN_LPCG_SDHC2_HCLK>; - clock-names = "ipg", "per", "ahb"; - power-domains = <&pd IMX_SC_R_SDHC_2>; - status = "disabled"; - }; - - fec1: ethernet@5b040000 { - compatible = "fsl,imx8qxp-fec", "fsl,imx6sx-fec"; - reg = <0x5b040000 0x10000>; - interrupts = , - , - , - ; - clocks = <&conn_lpcg IMX_CONN_LPCG_ENET0_IPG_CLK>, - <&conn_lpcg IMX_CONN_LPCG_ENET0_AHB_CLK>, - <&conn_lpcg IMX_CONN_LPCG_ENET0_TX_CLK>, - <&conn_lpcg IMX_CONN_LPCG_ENET0_ROOT_CLK>; - clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; - fsl,num-tx-queues=<3>; - fsl,num-rx-queues=<3>; - power-domains = <&pd IMX_SC_R_ENET_0>; - status = "disabled"; - }; - - fec2: ethernet@5b050000 { - compatible = "fsl,imx8qxp-fec", "fsl,imx6sx-fec"; - reg = <0x5b050000 0x10000>; - interrupts = , - , - , - ; - clocks = <&conn_lpcg IMX_CONN_LPCG_ENET1_IPG_CLK>, - <&conn_lpcg IMX_CONN_LPCG_ENET1_AHB_CLK>, - <&conn_lpcg IMX_CONN_LPCG_ENET1_TX_CLK>, - <&conn_lpcg IMX_CONN_LPCG_ENET1_ROOT_CLK>; - clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; - fsl,num-tx-queues=<3>; - fsl,num-rx-queues=<3>; - power-domains = <&pd IMX_SC_R_ENET_1>; - status = "disabled"; - }; - }; - - ddr_subsyss: bus@5c000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x5c000000 0x0 0x5c000000 0x1000000>; - - ddr-pmu@5c020000 { - compatible = "fsl,imx8-ddr-pmu"; - reg = <0x5c020000 0x10000>; - interrupts = ; - }; - }; - - lsio_subsys: bus@5d000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x5d000000 0x0 0x5d000000 0x1000000>; - - lsio_gpio0: gpio@5d080000 { - compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; - reg = <0x5d080000 0x10000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - power-domains = <&pd IMX_SC_R_GPIO_0>; - }; - - lsio_gpio1: gpio@5d090000 { - compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; - reg = <0x5d090000 0x10000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - power-domains = <&pd IMX_SC_R_GPIO_1>; - }; - - lsio_gpio2: gpio@5d0a0000 { - compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; - reg = <0x5d0a0000 0x10000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - power-domains = <&pd IMX_SC_R_GPIO_2>; - }; - - lsio_gpio3: gpio@5d0b0000 { - compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; - reg = <0x5d0b0000 0x10000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - power-domains = <&pd IMX_SC_R_GPIO_3>; - }; - - lsio_gpio4: gpio@5d0c0000 { - compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; - reg = <0x5d0c0000 0x10000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - power-domains = <&pd IMX_SC_R_GPIO_4>; - }; - - lsio_gpio5: gpio@5d0d0000 { - compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; - reg = <0x5d0d0000 0x10000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - power-domains = <&pd IMX_SC_R_GPIO_5>; - }; - - lsio_gpio6: gpio@5d0e0000 { - compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; - reg = <0x5d0e0000 0x10000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - power-domains = <&pd IMX_SC_R_GPIO_6>; - }; - - lsio_gpio7: gpio@5d0f0000 { - compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; - reg = <0x5d0f0000 0x10000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - power-domains = <&pd IMX_SC_R_GPIO_7>; - }; - - lsio_mu0: mailbox@5d1b0000 { - compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; - reg = <0x5d1b0000 0x10000>; - interrupts = ; - #mbox-cells = <2>; - status = "disabled"; - }; - - lsio_mu1: mailbox@5d1c0000 { - compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; - reg = <0x5d1c0000 0x10000>; - interrupts = ; - #mbox-cells = <2>; - }; - - lsio_mu2: mailbox@5d1d0000 { - compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; - reg = <0x5d1d0000 0x10000>; - interrupts = ; - #mbox-cells = <2>; - status = "disabled"; - }; - - lsio_mu3: mailbox@5d1e0000 { - compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; - reg = <0x5d1e0000 0x10000>; - interrupts = ; - #mbox-cells = <2>; - status = "disabled"; - }; - - lsio_mu4: mailbox@5d1f0000 { - compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; - reg = <0x5d1f0000 0x10000>; - interrupts = ; - #mbox-cells = <2>; - status = "disabled"; - }; - - lsio_mu13: mailbox@5d280000 { - compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; - reg = <0x5d280000 0x10000>; - interrupts = ; - #mbox-cells = <2>; - power-domains = <&pd IMX_SC_R_MU_13A>; - }; - - lsio_lpcg: clock-controller@5d400000 { - compatible = "fsl,imx8qxp-lpcg-lsio"; - reg = <0x5d400000 0x400000>; - #clock-cells = <1>; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/freescale/qoriq-bman-portals.dtsi b/sys/gnu/dts/arm64/freescale/qoriq-bman-portals.dtsi deleted file mode 100644 index ff1aba5fae7..00000000000 --- a/sys/gnu/dts/arm64/freescale/qoriq-bman-portals.dtsi +++ /dev/null @@ -1,77 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * QorIQ BMan Portals device tree - * - * Copyright 2011-2016 Freescale Semiconductor Inc. - * - */ - -&bportals { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - - bman-portal@0 { - /* - * bootloader fix-ups are expected to provide the - * "fsl,bman-portal-" compatible - */ - compatible = "fsl,bman-portal"; - reg = <0x0 0x4000>, <0x4000000 0x4000>; - interrupts = ; - }; - - bman-portal@10000 { - compatible = "fsl,bman-portal"; - reg = <0x10000 0x4000>, <0x4010000 0x4000>; - interrupts = ; - }; - - bman-portal@20000 { - compatible = "fsl,bman-portal"; - reg = <0x20000 0x4000>, <0x4020000 0x4000>; - interrupts = ; - }; - - bman-portal@30000 { - compatible = "fsl,bman-portal"; - reg = <0x30000 0x4000>, <0x4030000 0x4000>; - interrupts = ; - }; - - bman-portal@40000 { - compatible = "fsl,bman-portal"; - reg = <0x40000 0x4000>, <0x4040000 0x4000>; - interrupts = ; - }; - - bman-portal@50000 { - compatible = "fsl,bman-portal"; - reg = <0x50000 0x4000>, <0x4050000 0x4000>; - interrupts = ; - }; - - bman-portal@60000 { - compatible = "fsl,bman-portal"; - reg = <0x60000 0x4000>, <0x4060000 0x4000>; - interrupts = ; - }; - - bman-portal@70000 { - compatible = "fsl,bman-portal"; - reg = <0x70000 0x4000>, <0x4070000 0x4000>; - interrupts = ; - }; - - bman-portal@80000 { - compatible = "fsl,bman-portal"; - reg = <0x80000 0x4000>, <0x4080000 0x4000>; - interrupts = ; - }; - - bman-portal@90000 { - compatible = "fsl,bman-portal"; - reg = <0x90000 0x4000>, <0x4090000 0x4000>; - interrupts = ; - }; -}; diff --git a/sys/gnu/dts/arm64/freescale/qoriq-fman3-0-10g-0.dtsi b/sys/gnu/dts/arm64/freescale/qoriq-fman3-0-10g-0.dtsi deleted file mode 100644 index dbd2fc3ba79..00000000000 --- a/sys/gnu/dts/arm64/freescale/qoriq-fman3-0-10g-0.dtsi +++ /dev/null @@ -1,42 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * QorIQ FMan v3 10g port #0 device tree - * - * Copyright 2012-2015 Freescale Semiconductor Inc. - * - */ - -fman@1a00000 { - fman0_rx_0x10: port@90000 { - cell-index = <0x10>; - compatible = "fsl,fman-v3-port-rx"; - reg = <0x90000 0x1000>; - fsl,fman-10g-port; - }; - - fman0_tx_0x30: port@b0000 { - cell-index = <0x30>; - compatible = "fsl,fman-v3-port-tx"; - reg = <0xb0000 0x1000>; - fsl,fman-10g-port; - }; - - ethernet@f0000 { - cell-index = <0x8>; - compatible = "fsl,fman-memac"; - reg = <0xf0000 0x1000>; - fsl,fman-ports = <&fman0_rx_0x10 &fman0_tx_0x30>; - pcsphy-handle = <&pcsphy6>; - }; - - mdio@f1000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; - reg = <0xf1000 0x1000>; - - pcsphy6: ethernet-phy@0 { - reg = <0x0>; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/freescale/qoriq-fman3-0-10g-1.dtsi b/sys/gnu/dts/arm64/freescale/qoriq-fman3-0-10g-1.dtsi deleted file mode 100644 index 6fc5d256005..00000000000 --- a/sys/gnu/dts/arm64/freescale/qoriq-fman3-0-10g-1.dtsi +++ /dev/null @@ -1,42 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * QorIQ FMan v3 10g port #1 device tree - * - * Copyright 2012-2015 Freescale Semiconductor Inc. - * - */ - -fman@1a00000 { - fman0_rx_0x11: port@91000 { - cell-index = <0x11>; - compatible = "fsl,fman-v3-port-rx"; - reg = <0x91000 0x1000>; - fsl,fman-10g-port; - }; - - fman0_tx_0x31: port@b1000 { - cell-index = <0x31>; - compatible = "fsl,fman-v3-port-tx"; - reg = <0xb1000 0x1000>; - fsl,fman-10g-port; - }; - - ethernet@f2000 { - cell-index = <0x9>; - compatible = "fsl,fman-memac"; - reg = <0xf2000 0x1000>; - fsl,fman-ports = <&fman0_rx_0x11 &fman0_tx_0x31>; - pcsphy-handle = <&pcsphy7>; - }; - - mdio@f3000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; - reg = <0xf3000 0x1000>; - - pcsphy7: ethernet-phy@0 { - reg = <0x0>; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/freescale/qoriq-fman3-0-1g-0.dtsi b/sys/gnu/dts/arm64/freescale/qoriq-fman3-0-1g-0.dtsi deleted file mode 100644 index 4e02276fcf9..00000000000 --- a/sys/gnu/dts/arm64/freescale/qoriq-fman3-0-1g-0.dtsi +++ /dev/null @@ -1,41 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * QorIQ FMan v3 1g port #0 device tree - * - * Copyright 2012-2015 Freescale Semiconductor Inc. - * - */ - -fman@1a00000 { - fman0_rx_0x08: port@88000 { - cell-index = <0x8>; - compatible = "fsl,fman-v3-port-rx"; - reg = <0x88000 0x1000>; - }; - - fman0_tx_0x28: port@a8000 { - cell-index = <0x28>; - compatible = "fsl,fman-v3-port-tx"; - reg = <0xa8000 0x1000>; - }; - - ethernet@e0000 { - cell-index = <0>; - compatible = "fsl,fman-memac"; - reg = <0xe0000 0x1000>; - fsl,fman-ports = <&fman0_rx_0x08 &fman0_tx_0x28>; - ptp-timer = <&ptp_timer0>; - pcsphy-handle = <&pcsphy0>; - }; - - mdio@e1000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; - reg = <0xe1000 0x1000>; - - pcsphy0: ethernet-phy@0 { - reg = <0x0>; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/freescale/qoriq-fman3-0-1g-1.dtsi b/sys/gnu/dts/arm64/freescale/qoriq-fman3-0-1g-1.dtsi deleted file mode 100644 index 0312fa43fa7..00000000000 --- a/sys/gnu/dts/arm64/freescale/qoriq-fman3-0-1g-1.dtsi +++ /dev/null @@ -1,41 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * QorIQ FMan v3 1g port #1 device tree - * - * Copyright 2012-2015 Freescale Semiconductor Inc. - * - */ - -fman@1a00000 { - fman0_rx_0x09: port@89000 { - cell-index = <0x9>; - compatible = "fsl,fman-v3-port-rx"; - reg = <0x89000 0x1000>; - }; - - fman0_tx_0x29: port@a9000 { - cell-index = <0x29>; - compatible = "fsl,fman-v3-port-tx"; - reg = <0xa9000 0x1000>; - }; - - ethernet@e2000 { - cell-index = <1>; - compatible = "fsl,fman-memac"; - reg = <0xe2000 0x1000>; - fsl,fman-ports = <&fman0_rx_0x09 &fman0_tx_0x29>; - ptp-timer = <&ptp_timer0>; - pcsphy-handle = <&pcsphy1>; - }; - - mdio@e3000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; - reg = <0xe3000 0x1000>; - - pcsphy1: ethernet-phy@0 { - reg = <0x0>; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/freescale/qoriq-fman3-0-1g-2.dtsi b/sys/gnu/dts/arm64/freescale/qoriq-fman3-0-1g-2.dtsi deleted file mode 100644 index af2df07971d..00000000000 --- a/sys/gnu/dts/arm64/freescale/qoriq-fman3-0-1g-2.dtsi +++ /dev/null @@ -1,41 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * QorIQ FMan v3 1g port #2 device tree - * - * Copyright 2012-2015 Freescale Semiconductor Inc. - * - */ - -fman@1a00000 { - fman0_rx_0x0a: port@8a000 { - cell-index = <0xa>; - compatible = "fsl,fman-v3-port-rx"; - reg = <0x8a000 0x1000>; - }; - - fman0_tx_0x2a: port@aa000 { - cell-index = <0x2a>; - compatible = "fsl,fman-v3-port-tx"; - reg = <0xaa000 0x1000>; - }; - - ethernet@e4000 { - cell-index = <2>; - compatible = "fsl,fman-memac"; - reg = <0xe4000 0x1000>; - fsl,fman-ports = <&fman0_rx_0x0a &fman0_tx_0x2a>; - ptp-timer = <&ptp_timer0>; - pcsphy-handle = <&pcsphy2>; - }; - - mdio@e5000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; - reg = <0xe5000 0x1000>; - - pcsphy2: ethernet-phy@0 { - reg = <0x0>; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/freescale/qoriq-fman3-0-1g-3.dtsi b/sys/gnu/dts/arm64/freescale/qoriq-fman3-0-1g-3.dtsi deleted file mode 100644 index 4ac98dc8b22..00000000000 --- a/sys/gnu/dts/arm64/freescale/qoriq-fman3-0-1g-3.dtsi +++ /dev/null @@ -1,41 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * QorIQ FMan v3 1g port #3 device tree - * - * Copyright 2012-2015 Freescale Semiconductor Inc. - * - */ - -fman@1a00000 { - fman0_rx_0x0b: port@8b000 { - cell-index = <0xb>; - compatible = "fsl,fman-v3-port-rx"; - reg = <0x8b000 0x1000>; - }; - - fman0_tx_0x2b: port@ab000 { - cell-index = <0x2b>; - compatible = "fsl,fman-v3-port-tx"; - reg = <0xab000 0x1000>; - }; - - ethernet@e6000 { - cell-index = <3>; - compatible = "fsl,fman-memac"; - reg = <0xe6000 0x1000>; - fsl,fman-ports = <&fman0_rx_0x0b &fman0_tx_0x2b>; - ptp-timer = <&ptp_timer0>; - pcsphy-handle = <&pcsphy3>; - }; - - mdio@e7000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; - reg = <0xe7000 0x1000>; - - pcsphy3: ethernet-phy@0 { - reg = <0x0>; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/freescale/qoriq-fman3-0-1g-4.dtsi b/sys/gnu/dts/arm64/freescale/qoriq-fman3-0-1g-4.dtsi deleted file mode 100644 index bd932d8b016..00000000000 --- a/sys/gnu/dts/arm64/freescale/qoriq-fman3-0-1g-4.dtsi +++ /dev/null @@ -1,41 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * QorIQ FMan v3 1g port #4 device tree - * - * Copyright 2012-2015 Freescale Semiconductor Inc. - * - */ - -fman@1a00000 { - fman0_rx_0x0c: port@8c000 { - cell-index = <0xc>; - compatible = "fsl,fman-v3-port-rx"; - reg = <0x8c000 0x1000>; - }; - - fman0_tx_0x2c: port@ac000 { - cell-index = <0x2c>; - compatible = "fsl,fman-v3-port-tx"; - reg = <0xac000 0x1000>; - }; - - ethernet@e8000 { - cell-index = <4>; - compatible = "fsl,fman-memac"; - reg = <0xe8000 0x1000>; - fsl,fman-ports = <&fman0_rx_0x0c &fman0_tx_0x2c>; - ptp-timer = <&ptp_timer0>; - pcsphy-handle = <&pcsphy4>; - }; - - mdio@e9000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; - reg = <0xe9000 0x1000>; - - pcsphy4: ethernet-phy@0 { - reg = <0x0>; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/freescale/qoriq-fman3-0-1g-5.dtsi b/sys/gnu/dts/arm64/freescale/qoriq-fman3-0-1g-5.dtsi deleted file mode 100644 index 7de1c5203f3..00000000000 --- a/sys/gnu/dts/arm64/freescale/qoriq-fman3-0-1g-5.dtsi +++ /dev/null @@ -1,41 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * QorIQ FMan v3 1g port #5 device tree - * - * Copyright 2012-2015 Freescale Semiconductor Inc. - * - */ - -fman@1a00000 { - fman0_rx_0x0d: port@8d000 { - cell-index = <0xd>; - compatible = "fsl,fman-v3-port-rx"; - reg = <0x8d000 0x1000>; - }; - - fman0_tx_0x2d: port@ad000 { - cell-index = <0x2d>; - compatible = "fsl,fman-v3-port-tx"; - reg = <0xad000 0x1000>; - }; - - ethernet@ea000 { - cell-index = <5>; - compatible = "fsl,fman-memac"; - reg = <0xea000 0x1000>; - fsl,fman-ports = <&fman0_rx_0x0d &fman0_tx_0x2d>; - ptp-timer = <&ptp_timer0>; - pcsphy-handle = <&pcsphy5>; - }; - - mdio@eb000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; - reg = <0xeb000 0x1000>; - - pcsphy5: ethernet-phy@0 { - reg = <0x0>; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/freescale/qoriq-fman3-0.dtsi b/sys/gnu/dts/arm64/freescale/qoriq-fman3-0.dtsi deleted file mode 100644 index 263b972a6d1..00000000000 --- a/sys/gnu/dts/arm64/freescale/qoriq-fman3-0.dtsi +++ /dev/null @@ -1,84 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * QorIQ FMan v3 device tree - * - * Copyright 2012-2015 Freescale Semiconductor Inc. - * - */ - -fman0: fman@1a00000 { - #address-cells = <1>; - #size-cells = <1>; - cell-index = <0>; - compatible = "fsl,fman"; - ranges = <0x0 0x0 0x1a00000 0xfe000>; - reg = <0x0 0x1a00000 0x0 0xfe000>; - interrupts = , - ; - clocks = <&clockgen 3 0>; - clock-names = "fmanclk"; - fsl,qman-channel-range = <0x800 0x10>; - ptimer-handle = <&ptp_timer0>; - - muram@0 { - compatible = "fsl,fman-muram"; - reg = <0x0 0x60000>; - }; - - fman0_oh_0x2: port@82000 { - cell-index = <0x2>; - compatible = "fsl,fman-v3-port-oh"; - reg = <0x82000 0x1000>; - }; - - fman0_oh_0x3: port@83000 { - cell-index = <0x3>; - compatible = "fsl,fman-v3-port-oh"; - reg = <0x83000 0x1000>; - }; - - fman0_oh_0x4: port@84000 { - cell-index = <0x4>; - compatible = "fsl,fman-v3-port-oh"; - reg = <0x84000 0x1000>; - }; - - fman0_oh_0x5: port@85000 { - cell-index = <0x5>; - compatible = "fsl,fman-v3-port-oh"; - reg = <0x85000 0x1000>; - }; - - fman0_oh_0x6: port@86000 { - cell-index = <0x6>; - compatible = "fsl,fman-v3-port-oh"; - reg = <0x86000 0x1000>; - }; - - fman0_oh_0x7: port@87000 { - cell-index = <0x7>; - compatible = "fsl,fman-v3-port-oh"; - reg = <0x87000 0x1000>; - }; - - mdio0: mdio@fc000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; - reg = <0xfc000 0x1000>; - }; - - xmdio0: mdio@fd000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; - reg = <0xfd000 0x1000>; - }; -}; - -ptp_timer0: ptp-timer@1afe000 { - compatible = "fsl,fman-ptp-timer"; - reg = <0x0 0x1afe000 0x0 0x1000>; - interrupts = ; - clocks = <&clockgen 3 0>; -}; diff --git a/sys/gnu/dts/arm64/freescale/qoriq-qman-portals.dtsi b/sys/gnu/dts/arm64/freescale/qoriq-qman-portals.dtsi deleted file mode 100644 index e3bec08b110..00000000000 --- a/sys/gnu/dts/arm64/freescale/qoriq-qman-portals.dtsi +++ /dev/null @@ -1,87 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * QorIQ QMan Portals device tree - * - * Copyright 2011-2016 Freescale Semiconductor Inc. - * - */ - -&qportals { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - - qportal0: qman-portal@0 { - /* - * bootloader fix-ups are expected to provide the - * "fsl,bman-portal-" compatible - */ - compatible = "fsl,qman-portal"; - reg = <0x0 0x4000>, <0x4000000 0x4000>; - interrupts = ; - cell-index = <0>; - }; - - qportal1: qman-portal@10000 { - compatible = "fsl,qman-portal"; - reg = <0x10000 0x4000>, <0x4010000 0x4000>; - interrupts = ; - cell-index = <1>; - }; - - qportal2: qman-portal@20000 { - compatible = "fsl,qman-portal"; - reg = <0x20000 0x4000>, <0x4020000 0x4000>; - interrupts = ; - cell-index = <2>; - }; - - qportal3: qman-portal@30000 { - compatible = "fsl,qman-portal"; - reg = <0x30000 0x4000>, <0x4030000 0x4000>; - interrupts = ; - cell-index = <3>; - }; - - qportal4: qman-portal@40000 { - compatible = "fsl,qman-portal"; - reg = <0x40000 0x4000>, <0x4040000 0x4000>; - interrupts = ; - cell-index = <4>; - }; - - qportal5: qman-portal@50000 { - compatible = "fsl,qman-portal"; - reg = <0x50000 0x4000>, <0x4050000 0x4000>; - interrupts = ; - cell-index = <5>; - }; - - qportal6: qman-portal@60000 { - compatible = "fsl,qman-portal"; - reg = <0x60000 0x4000>, <0x4060000 0x4000>; - interrupts = ; - cell-index = <6>; - }; - - qportal7: qman-portal@70000 { - compatible = "fsl,qman-portal"; - reg = <0x70000 0x4000>, <0x4070000 0x4000>; - interrupts = ; - cell-index = <7>; - }; - - qportal8: qman-portal@80000 { - compatible = "fsl,qman-portal"; - reg = <0x80000 0x4000>, <0x4080000 0x4000>; - interrupts = ; - cell-index = <8>; - }; - - qportal9: qman-portal@90000 { - compatible = "fsl,qman-portal"; - reg = <0x90000 0x4000>, <0x4090000 0x4000>; - interrupts = ; - cell-index = <9>; - }; -}; diff --git a/sys/gnu/dts/arm64/freescale/s32v234-evb.dts b/sys/gnu/dts/arm64/freescale/s32v234-evb.dts deleted file mode 100644 index 4b802518cef..00000000000 --- a/sys/gnu/dts/arm64/freescale/s32v234-evb.dts +++ /dev/null @@ -1,25 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2015-2016 Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - */ - -/dts-v1/; -#include "s32v234.dtsi" - -/ { - model = "NXP S32V234-EVB2 Board"; - compatible = "fsl,s32v234-evb", "fsl,s32v234"; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/freescale/s32v234.dtsi b/sys/gnu/dts/arm64/freescale/s32v234.dtsi deleted file mode 100644 index e746b9c48f7..00000000000 --- a/sys/gnu/dts/arm64/freescale/s32v234.dtsi +++ /dev/null @@ -1,139 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2015-2016 Freescale Semiconductor, Inc. - * Copyright 2016-2018 NXP - */ - -#include - -/memreserve/ 0x80000000 0x00010000; - -/ { - compatible = "fsl,s32v234"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - }; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x0>; - enable-method = "spin-table"; - cpu-release-addr = <0x0 0x80000000>; - next-level-cache = <&cluster0_l2_cache>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x1>; - enable-method = "spin-table"; - cpu-release-addr = <0x0 0x80000000>; - next-level-cache = <&cluster0_l2_cache>; - }; - - cpu2: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x100>; - enable-method = "spin-table"; - cpu-release-addr = <0x0 0x80000000>; - next-level-cache = <&cluster1_l2_cache>; - }; - - cpu3: cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x101>; - enable-method = "spin-table"; - cpu-release-addr = <0x0 0x80000000>; - next-level-cache = <&cluster1_l2_cache>; - }; - - cluster0_l2_cache: l2-cache0 { - compatible = "cache"; - }; - - cluster1_l2_cache: l2-cache1 { - compatible = "cache"; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - /* clock-frequency might be modified by u-boot, depending on the - * chip version. - */ - clock-frequency = <10000000>; - }; - - gic: interrupt-controller@7d001000 { - compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0 0x7d001000 0 0x1000>, - <0 0x7d002000 0 0x2000>, - <0 0x7d004000 0 0x2000>, - <0 0x7d006000 0 0x2000>; - interrupts = ; - }; - - soc { - #address-cells = <2>; - #size-cells = <2>; - compatible = "simple-bus"; - interrupt-parent = <&gic>; - ranges; - - aips0: aips-bus@40000000 { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - interrupt-parent = <&gic>; - reg = <0x0 0x40000000 0x0 0x7d000>; - ranges; - - uart0: serial@40053000 { - compatible = "fsl,s32v234-linflexuart"; - reg = <0x0 0x40053000 0x0 0x1000>; - interrupts = ; - status = "disabled"; - }; - }; - - aips1: aips-bus@40080000 { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - interrupt-parent = <&gic>; - reg = <0x0 0x40080000 0x0 0x70000>; - ranges; - - uart1: serial@400bc000 { - compatible = "fsl,s32v234-linflexuart"; - reg = <0x0 0x400bc000 0x0 0x1000>; - interrupts = ; - status = "disabled"; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/hisilicon/hi3660-coresight.dtsi b/sys/gnu/dts/arm64/hisilicon/hi3660-coresight.dtsi deleted file mode 100644 index d607f2f6698..00000000000 --- a/sys/gnu/dts/arm64/hisilicon/hi3660-coresight.dtsi +++ /dev/null @@ -1,456 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -/* - * dtsi for Hisilicon Hi3660 Coresight - * - * Copyright (C) 2016-2018 Hisilicon Ltd. - * - * Author: Wanglai Shi - * - */ -/ { - soc { - /* A53 cluster internals */ - etm@ecc40000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0xecc40000 0 0x1000>; - clocks = <&crg_ctrl HI3660_PCLK>; - clock-names = "apb_pclk"; - cpu = <&cpu0>; - - out-ports { - port { - etm0_out: endpoint { - remote-endpoint = - <&cluster0_funnel_in0>; - }; - }; - }; - }; - - etm@ecd40000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0xecd40000 0 0x1000>; - clocks = <&crg_ctrl HI3660_PCLK>; - clock-names = "apb_pclk"; - cpu = <&cpu1>; - - out-ports { - port { - etm1_out: endpoint { - remote-endpoint = - <&cluster0_funnel_in1>; - }; - }; - }; - }; - - etm@ece40000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0xece40000 0 0x1000>; - clocks = <&crg_ctrl HI3660_PCLK>; - clock-names = "apb_pclk"; - cpu = <&cpu2>; - - out-ports { - port { - etm2_out: endpoint { - remote-endpoint = - <&cluster0_funnel_in2>; - }; - }; - }; - }; - - etm@ecf40000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0xecf40000 0 0x1000>; - clocks = <&crg_ctrl HI3660_PCLK>; - clock-names = "apb_pclk"; - cpu = <&cpu3>; - - out-ports { - port { - etm3_out: endpoint { - remote-endpoint = - <&cluster0_funnel_in3>; - }; - }; - }; - }; - - funnel@ec801000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0xec801000 0 0x1000>; - clocks = <&crg_ctrl HI3660_PCLK>; - clock-names = "apb_pclk"; - - out-ports { - port { - cluster0_funnel_out: endpoint { - remote-endpoint = - <&cluster0_etf_in>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - cluster0_funnel_in0: endpoint { - remote-endpoint = <&etm0_out>; - }; - }; - - port@1 { - reg = <1>; - cluster0_funnel_in1: endpoint { - remote-endpoint = <&etm1_out>; - }; - }; - - port@2 { - reg = <2>; - cluster0_funnel_in2: endpoint { - remote-endpoint = <&etm2_out>; - }; - }; - - port@3 { - reg = <3>; - cluster0_funnel_in3: endpoint { - remote-endpoint = <&etm3_out>; - }; - }; - }; - }; - - etf@ec802000 { - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0 0xec802000 0 0x1000>; - clocks = <&crg_ctrl HI3660_PCLK>; - clock-names = "apb_pclk"; - - in-ports { - port { - cluster0_etf_in: endpoint { - remote-endpoint = - <&cluster0_funnel_out>; - }; - }; - }; - - out-ports { - port { - cluster0_etf_out: endpoint { - remote-endpoint = - <&combo_funnel_in0>; - }; - }; - }; - }; - - /* A73 cluster internals */ - etm@ed440000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0xed440000 0 0x1000>; - clocks = <&crg_ctrl HI3660_PCLK>; - clock-names = "apb_pclk"; - cpu = <&cpu4>; - - out-ports { - port { - etm4_out: endpoint { - remote-endpoint = - <&cluster1_funnel_in0>; - }; - }; - }; - }; - - etm@ed540000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0xed540000 0 0x1000>; - clocks = <&crg_ctrl HI3660_PCLK>; - clock-names = "apb_pclk"; - cpu = <&cpu5>; - - out-ports { - port { - etm5_out: endpoint { - remote-endpoint = - <&cluster1_funnel_in1>; - }; - }; - }; - }; - - etm@ed640000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0xed640000 0 0x1000>; - clocks = <&crg_ctrl HI3660_PCLK>; - clock-names = "apb_pclk"; - cpu = <&cpu6>; - - out-ports { - port { - etm6_out: endpoint { - remote-endpoint = - <&cluster1_funnel_in2>; - }; - }; - }; - }; - - etm@ed740000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0xed740000 0 0x1000>; - clocks = <&crg_ctrl HI3660_PCLK>; - clock-names = "apb_pclk"; - cpu = <&cpu7>; - - out-ports { - port { - etm7_out: endpoint { - remote-endpoint = - <&cluster1_funnel_in3>; - }; - }; - }; - }; - - funnel@ed001000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0xed001000 0 0x1000>; - clocks = <&crg_ctrl HI3660_PCLK>; - clock-names = "apb_pclk"; - out-ports { - port { - cluster1_funnel_out: endpoint { - remote-endpoint = - <&cluster1_etf_in>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - cluster1_funnel_in0: endpoint { - remote-endpoint = <&etm4_out>; - }; - }; - - port@1 { - reg = <1>; - cluster1_funnel_in1: endpoint { - remote-endpoint = <&etm5_out>; - }; - }; - - port@2 { - reg = <2>; - cluster1_funnel_in2: endpoint { - remote-endpoint = <&etm6_out>; - }; - }; - - port@3 { - reg = <3>; - cluster1_funnel_in3: endpoint { - remote-endpoint = <&etm7_out>; - }; - }; - }; - }; - - etf@ed002000 { - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0 0xed002000 0 0x1000>; - clocks = <&crg_ctrl HI3660_PCLK>; - clock-names = "apb_pclk"; - - in-ports { - port { - cluster1_etf_in: endpoint { - remote-endpoint = - <&cluster1_funnel_out>; - }; - }; - }; - - out-ports { - port { - cluster1_etf_out: endpoint { - remote-endpoint = - <&combo_funnel_in1>; - }; - }; - }; - }; - - /* An invisible combo funnel between clusters and top funnel */ - funnel { - compatible = "arm,coresight-static-funnel"; - clocks = <&crg_ctrl HI3660_PCLK>; - clock-names = "apb_pclk"; - - out-ports { - port { - combo_funnel_out: endpoint { - remote-endpoint = - <&top_funnel_in>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - combo_funnel_in0: endpoint { - remote-endpoint = - <&cluster0_etf_out>; - }; - }; - - port@1 { - reg = <1>; - combo_funnel_in1: endpoint { - remote-endpoint = - <&cluster1_etf_out>; - }; - }; - }; - }; - - /* Top internals */ - funnel@ec031000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0xec031000 0 0x1000>; - clocks = <&crg_ctrl HI3660_PCLK>; - clock-names = "apb_pclk"; - - out-ports { - port { - top_funnel_out: endpoint { - remote-endpoint = - <&top_etf_in>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - top_funnel_in: endpoint { - remote-endpoint = - <&combo_funnel_out>; - }; - }; - }; - }; - - etf@ec036000 { - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0 0xec036000 0 0x1000>; - clocks = <&crg_ctrl HI3660_PCLK>; - clock-names = "apb_pclk"; - - in-ports { - port { - top_etf_in: endpoint { - remote-endpoint = - <&top_funnel_out>; - }; - }; - }; - - out-ports { - port { - top_etf_out: endpoint { - remote-endpoint = - <&replicator_in>; - }; - }; - }; - }; - - replicator { - compatible = "arm,coresight-static-replicator"; - clocks = <&crg_ctrl HI3660_PCLK>; - clock-names = "apb_pclk"; - - in-ports { - port { - replicator_in: endpoint { - remote-endpoint = - <&top_etf_out>; - }; - }; - }; - - out-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - replicator0_out0: endpoint { - remote-endpoint = <&etr_in>; - }; - }; - - port@1 { - reg = <1>; - replicator0_out1: endpoint { - remote-endpoint = <&tpiu_in>; - }; - }; - }; - }; - - etr@ec033000 { - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0 0xec033000 0 0x1000>; - clocks = <&crg_ctrl HI3660_PCLK>; - clock-names = "apb_pclk"; - - in-ports { - port { - etr_in: endpoint { - remote-endpoint = - <&replicator0_out0>; - }; - }; - }; - }; - - tpiu@ec032000 { - compatible = "arm,coresight-tpiu", "arm,primecell"; - reg = <0 0xec032000 0 0x1000>; - clocks = <&crg_ctrl HI3660_PCLK>; - clock-names = "apb_pclk"; - - in-ports { - port { - tpiu_in: endpoint { - remote-endpoint = - <&replicator0_out1>; - }; - }; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/hisilicon/hi3660-hikey960.dts b/sys/gnu/dts/arm64/hisilicon/hi3660-hikey960.dts deleted file mode 100644 index e035cf195b1..00000000000 --- a/sys/gnu/dts/arm64/hisilicon/hi3660-hikey960.dts +++ /dev/null @@ -1,614 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * dts file for Hisilicon HiKey960 Development Board - * - * Copyright (C) 2016, Hisilicon Ltd. - * - */ - -/dts-v1/; - -#include "hi3660.dtsi" -#include "hikey960-pinctrl.dtsi" -#include -#include -#include - -/ { - model = "HiKey960"; - compatible = "hisilicon,hi3660-hikey960", "hisilicon,hi3660"; - - aliases { - mshc1 = &dwmmc1; - mshc2 = &dwmmc2; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - serial4 = &uart4; - serial5 = &uart5; - serial6 = &uart6; - }; - - chosen { - stdout-path = "serial6:115200n8"; - }; - - memory@0 { - device_type = "memory"; - /* rewrite this at bootloader */ - reg = <0x0 0x0 0x0 0x0>; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - ramoops@32000000 { - compatible = "ramoops"; - reg = <0x0 0x32000000 0x0 0x00100000>; - record-size = <0x00020000>; - console-size = <0x00020000>; - ftrace-size = <0x00020000>; - }; - }; - - reboot-mode-syscon@32100000 { - compatible = "syscon", "simple-mfd"; - reg = <0x0 0x32100000 0x0 0x00001000>; - - reboot-mode { - compatible = "syscon-reboot-mode"; - offset = <0x0>; - - mode-normal = <0x77665501>; - mode-bootloader = <0x77665500>; - mode-recovery = <0x77665502>; - }; - }; - - keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pwr_key_pmx_func &pwr_key_cfg_func>; - - power { - wakeup-source; - gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; - label = "GPIO Power"; - linux,code = ; - }; - }; - - leds { - compatible = "gpio-leds"; - - user_led1 { - label = "green:user1"; - /* gpio_150_user_led1 */ - gpios = <&gpio18 6 0>; - linux,default-trigger = "heartbeat"; - }; - - user_led2 { - label = "green:user2"; - /* gpio_151_user_led2 */ - gpios = <&gpio18 7 0>; - linux,default-trigger = "none"; - }; - - user_led3 { - label = "green:user3"; - /* gpio_189_user_led3 */ - gpios = <&gpio23 5 0>; - linux,default-trigger = "mmc0"; - }; - - user_led4 { - label = "green:user4"; - /* gpio_190_user_led4 */ - gpios = <&gpio23 6 0>; - panic-indicator; - linux,default-trigger = "none"; - }; - - wlan_active_led { - label = "yellow:wlan"; - /* gpio_205_wifi_active */ - gpios = <&gpio25 5 0>; - linux,default-trigger = "phy0tx"; - default-state = "off"; - }; - - bt_active_led { - label = "blue:bt"; - gpios = <&gpio25 7 0>; - /* gpio_207_user_led1 */ - linux,default-trigger = "hci0-power"; - default-state = "off"; - }; - }; - - pmic: pmic@fff34000 { - compatible = "hisilicon,hi6421v530-pmic"; - reg = <0x0 0xfff34000 0x0 0x1000>; - interrupt-controller; - #interrupt-cells = <2>; - - regulators { - ldo3: LDO3 { /* HDMI */ - regulator-name = "VOUT3_1V85"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2200000>; - regulator-enable-ramp-delay = <120>; - }; - - ldo9: LDO9 { /* SDCARD I/O */ - regulator-name = "VOUT9_1V8_2V95"; - regulator-min-microvolt = <1750000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <240>; - }; - - ldo11: LDO11 { /* Low Speed Connector */ - regulator-name = "VOUT11_1V8_2V95"; - regulator-min-microvolt = <1750000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <240>; - }; - - ldo15: LDO15 { /* UFS VCC */ - regulator-name = "VOUT15_3V0"; - regulator-min-microvolt = <1750000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - regulator-enable-ramp-delay = <120>; - }; - - ldo16: LDO16 { /* SD VDD */ - regulator-name = "VOUT16_2V95"; - regulator-min-microvolt = <1750000>; - regulator-max-microvolt = <3000000>; - regulator-enable-ramp-delay = <360>; - }; - }; - }; - - wlan_en: wlan-en-1-8v { - compatible = "regulator-fixed"; - regulator-name = "wlan-en-regulator"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - /* GPIO_051_WIFI_EN */ - gpio = <&gpio6 3 0>; - - /* WLAN card specific delay */ - startup-delay-us = <70000>; - enable-active-high; - }; - - firmware { - optee { - compatible = "linaro,optee-tz"; - method = "smc"; - }; - }; -}; - -/* - * Legend: proper name = the GPIO line is used as GPIO - * NC = not connected (pin out but not routed from the chip to - * anything the board) - * "[PER]" = pin is muxed for [peripheral] (not GPIO) - * "" = no idea, schematic doesn't say, could be - * unrouted (not connected to any external pin) - * LSEC = Low Speed External Connector - * HSEC = High Speed External Connector - * - * Line names are taken from "HiKey 960 Board ver A" schematics - * from Huawei. The 40 pin low speed expansion connector is named - * J2002 63453-140LF. - * - * For the lines routed to the external connectors the - * lines are named after the 96Boards CE Specification 1.0, - * Appendix "Expansion Connector Signal Description". - * - * When the 96Board naming of a line and the schematic name of - * the same line are in conflict, the 96Board specification - * takes precedence, which means that the external UART on the - * LSEC is named UART0 while the schematic and SoC names this - * UART3. This is only for the informational lines i.e. "[FOO]", - * the GPIO named lines "GPIO-A" thru "GPIO-L" are the only - * ones actually used for GPIO. - */ -&gpio0 { - /* GPIO_000-GPIO_007 */ - gpio-line-names = - "", - "TP901", /* TEST_MODE connected to TP901 */ - "[PMU0_SSI]", - "[PMU1_SSI]", - "[PMU2_SSI]", - "[PMU0_CLKOUT]", - "[JTAG_TCK]", - "[JTAG_TMS]"; -}; - -&gpio1 { - /* GPIO_008-GPIO_015 */ - gpio-line-names = - "[JTAG_TRST_N]", - "[JTAG_TDI]", - "[JTAG_TDO]", - "NC", "NC", - "[I2C3_SCL]", - "[I2C3_SDA]", - "NC"; -}; - -&gpio2 { - /* GPIO_016-GPIO_023 */ - gpio-line-names = - "NC", "NC", "NC", - "GPIO-J", /* LSEC pin 32: GPIO_019 */ - "GPIO_020_HDMI_SEL", - "GPIO-L", /* LSEC pin 34: GPIO_021 */ - "GPIO_022_UFSBUCK_INT_N", - "GPIO-G"; /* LSEC pin 29: LCD_TE0 */ -}; - -&gpio3 { - /* GPIO_024-GPIO_031 */ - /* The rail from pin BK36 is named LCD_TE0, we assume to be muxed as GPIO for GPIO-G */ - gpio-line-names = - "[CSI0_MCLK]", /* HSEC pin 15: ISP_CCLK0_MCAM */ - "[CSI1_MCLK]", /* HSEC pin 17: ISP_CCLK1_SCAM */ - "NC", - "[I2C2_SCL]", /* HSEC pin 32: ISP_SCL0 */ - "[I2C2_SDA]", /* HSEC pin 34: ISP_SDA0 */ - "[I2C3_SCL]", /* HSEC pin 36: ISP_SCL1 */ - "[I2C3_SDA]", /* HSEC pin 38: ISP_SDA1 */ - "NC"; -}; - -&gpio4 { - /* GPIO_032-GPIO_039 */ - gpio-line-names = - "NC", "NC", - "PWR_BTN_N", /* LSEC pin 4: GPIO_034_PWRON_DET */ - "GPIO_035_PMU2_EN", - "GPIO_036_USB_HUB_RESET", - "NC", "NC", "NC"; -}; - -&gpio5 { - /* GPIO_040-GPIO_047 */ - gpio-line-names = - "GPIO-H", /* LSEC pin 30: GPIO_040_LCD_RST_N */ - "GPIO_041_HDMI_PD", - "TP904", /* Test point */ - "TP905", /* Test point */ - "NC", "NC", - "GPIO_046_HUB_VDD33_EN", - "GPIO_047_PMU1_EN"; -}; - -&gpio6 { - /* GPIO_048-GPIO_055 */ - gpio-line-names = - "NC", "NC", "NC", - "GPIO_051_WIFI_EN", - "GPIO-I", /* LSEC pin 31: GPIO_052_CAM0_RST_N */ - /* - * These two pins should be used for SD(IO) data according to the - * 96boards specification but seems to be repurposed for a IRDA UART. - * They are however named according to the spec. - */ - "[SD_DAT1]", /* HSEC pin 3: UART0_IRDA_RXD */ - "[SD_DAT2]", /* HSEC pin 5: UART0_IRDA_TXD */ - "[UART1_RXD]"; /* LSEC pin 13: DEBUG_UART6_RXD */ -}; - -&gpio7 { - /* GPIO_056-GPIO_063 */ - gpio-line-names = - "[UART1_TXD]", /* LSEC pin 11: DEBUG_UART6_TXD */ - "[UART0_CTS]", /* LSEC pin 3: UART3_CTS_N */ - "[UART0_RTS]", /* LSEC pin 9: UART3_RTS_N */ - "[UART0_RXD]", /* LSEC pin 7: UART3_RXD */ - "[UART0_TXD]", /* LSEC pin 5: UART3_TXD */ - "[SOC_BT_UART4_CTS_N]", - "[SOC_BT_UART4_RTS_N]", - "[SOC_BT_UART4_RXD]"; -}; - -&gpio8 { - /* GPIO_064-GPIO_071 */ - gpio-line-names = - "[SOC_BT_UART4_TXD]", - "NC", - "[PMU_HKADC_SSI]", - "NC", - "GPIO_068_SEL", - "NC", "NC", "NC"; - -}; - -&gpio9 { - /* GPIO_072-GPIO_079 */ - gpio-line-names = - "NC", "NC", "NC", - "GPIO-K", /* LSEC pin 33: GPIO_075_CAM1_RST_N */ - "NC", "NC", "NC", "NC"; -}; - -&gpio10 { - /* GPIO_080-GPIO_087 */ - gpio-line-names = "NC", "NC", "NC", "NC", "NC", "NC", "NC", "NC"; -}; - -&gpio11 { - /* GPIO_088-GPIO_095 */ - gpio-line-names = - "NC", - "[PCIE_PERST_N]", - "NC", "NC", "NC", "NC", "NC", "NC"; -}; - -&gpio12 { - /* GPIO_096-GPIO_103 */ - gpio-line-names = "NC", "NC", "NC", "", "", "", "", "NC"; -}; - -&gpio13 { - /* GPIO_104-GPIO_111 */ - gpio-line-names = "NC", "NC", "NC", "NC", "NC", "NC", "NC", "NC"; -}; - -&gpio14 { - /* GPIO_112-GPIO_119 */ - gpio-line-names = "NC", "NC", "NC", "NC", "NC", "NC", "NC", "NC"; -}; - -&gpio15 { - /* GPIO_120-GPIO_127 */ - gpio-line-names = - "NC", "NC", "NC", "NC", "NC", "NC", - "GPIO_126_BT_EN", - "TP902"; /* GPIO_127_JTAG_SEL0 */ -}; - -&gpio16 { - /* GPIO_128-GPIO_135 */ - gpio-line-names = "", "", "", "", "", "", "", ""; -}; - -&gpio17 { - /* GPIO_136-GPIO_143 */ - gpio-line-names = "", "", "", "", "", "", "", ""; -}; - -&gpio18 { - /* GPIO_144-GPIO_151 */ - gpio-line-names = - "[UFS_REF_CLK]", - "[UFS_RST_N]", - "[SPI1_SCLK]", /* HSEC pin 9: GPIO_146_SPI3_CLK */ - "[SPI1_DIN]", /* HSEC pin 11: GPIO_147_SPI3_DI */ - "[SPI1_DOUT]", /* HSEC pin 1: GPIO_148_SPI3_DO */ - "[SPI1_CS]", /* HSEC pin 7: GPIO_149_SPI3_CS0_N */ - "GPIO_150_USER_LED1", - "GPIO_151_USER_LED2"; -}; - -&gpio19 { - /* GPIO_152-GPIO_159 */ - gpio-line-names = "NC", "NC", "NC", "NC", "", "", "", ""; -}; - -&gpio20 { - /* GPIO_160-GPIO_167 */ - gpio-line-names = - "[SD_CLK]", - "[SD_CMD]", - "[SD_DATA0]", - "[SD_DATA1]", - "[SD_DATA2]", - "[SD_DATA3]", - "", ""; -}; - -&gpio21 { - /* GPIO_168-GPIO_175 */ - gpio-line-names = - "[WL_SDIO_CLK]", - "[WL_SDIO_CMD]", - "[WL_SDIO_DATA0]", - "[WL_SDIO_DATA1]", - "[WL_SDIO_DATA2]", - "[WL_SDIO_DATA3]", - "", ""; -}; - -&gpio22 { - /* GPIO_176-GPIO_183 */ - gpio-line-names = - "[GPIO_176_PMU_PWR_HOLD]", - "NA", - "[SYSCLK_EN]", - "GPIO_179_WL_WAKEUP_AP", - "GPIO_180_HDMI_INT", - "NA", - "GPIO-F", /* LSEC pin 28: LCD_BL_PWM */ - "[I2C0_SCL]"; /* LSEC pin 15 */ -}; - -&gpio23 { - /* GPIO_184-GPIO_191 */ - gpio-line-names = - "[I2C0_SDA]", /* LSEC pin 17 */ - "[I2C1_SCL]", /* Actual SoC I2C1 */ - "[I2C1_SDA]", /* Actual SoC I2C1 */ - "[I2C1_SCL]", /* LSEC pin 19: I2C7_SCL */ - "[I2C1_SDA]", /* LSEC pin 21: I2C7_SDA */ - "GPIO_189_USER_LED3", - "GPIO_190_USER_LED4", - ""; -}; - -&gpio24 { - /* GPIO_192-GPIO_199 */ - gpio-line-names = - "[PCM_DI]", /* LSEC pin 22: GPIO_192_I2S0_DI */ - "[PCM_DO]", /* LSEC pin 20: GPIO_193_I2S0_DO */ - "[PCM_CLK]", /* LSEC pin 18: GPIO_194_I2S0_XCLK */ - "[PCM_FS]", /* LSEC pin 16: GPIO_195_I2S0_XFS */ - "[GPIO_196_I2S2_DI]", - "[GPIO_197_I2S2_DO]", - "[GPIO_198_I2S2_XCLK]", - "[GPIO_199_I2S2_XFS]"; -}; - -&gpio25 { - /* GPIO_200-GPIO_207 */ - gpio-line-names = - "NC", - "NC", - "GPIO_202_VBUS_TYPEC", - "GPIO_203_SD_DET", - "GPIO_204_PMU12_IRQ_N", - "GPIO_205_WIFI_ACTIVE", - "GPIO_206_USBSW_SEL", - "GPIO_207_BT_ACTIVE"; -}; - -&gpio26 { - /* GPIO_208-GPIO_215 */ - gpio-line-names = - "GPIO-A", /* LSEC pin 23: GPIO_208 */ - "GPIO-B", /* LSEC pin 24: GPIO_209 */ - "GPIO-C", /* LSEC pin 25: GPIO_210 */ - "GPIO-D", /* LSEC pin 26: GPIO_211 */ - "GPIO-E", /* LSEC pin 27: GPIO_212 */ - "[PCIE_CLKREQ_N]", - "[PCIE_WAKE_N]", - "[SPI0_CLK]"; /* LSEC pin 8: SPI2_CLK */ -}; - -&gpio27 { - /* GPIO_216-GPIO_223 */ - gpio-line-names = - "[SPI0_DIN]", /* LSEC pin 10: SPI2_DI */ - "[SPI0_DOUT]", /* LSEC pin 14: SPI2_DO */ - "[SPI0_CS]", /* LSEC pin 12: SPI2_CS0_N */ - "GPIO_219_CC_INT", - "NC", - "NC", - "[PMU_INT]", - ""; -}; - -&gpio28 { - /* GPIO_224-GPIO_231 */ - gpio-line-names = - "", "", "", "", "", "", "", ""; -}; - -&i2c0 { - /* On Low speed expansion */ - label = "LS-I2C0"; - status = "okay"; -}; - -&i2c1 { - status = "okay"; - - adv7533: adv7533@39 { - status = "ok"; - compatible = "adi,adv7533"; - reg = <0x39>; - }; -}; - -&i2c7 { - /* On Low speed expansion */ - label = "LS-I2C1"; - status = "okay"; -}; - -&uart3 { - /* On Low speed expansion */ - label = "LS-UART0"; - status = "okay"; -}; - -&uart4 { - status = "okay"; - - bluetooth { - compatible = "ti,wl1837-st"; - enable-gpios = <&gpio15 6 GPIO_ACTIVE_HIGH>; - max-speed = <3000000>; - }; -}; - -&uart6 { - /* On Low speed expansion */ - label = "LS-UART1"; - status = "okay"; -}; - -&spi2 { - /* On Low speed expansion */ - label = "LS-SPI0"; - status = "okay"; -}; - -&spi3 { - /* On High speed expansion */ - label = "HS-SPI1"; - status = "okay"; -}; - -&dwmmc1 { - bus-width = <0x4>; - cap-sd-highspeed; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-sdr104; - disable-wp; - cd-gpios = <&gpio25 3 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&sd_pmx_func - &sd_clk_cfg_func - &sd_cfg_func>; - vmmc-supply = <&ldo16>; - vqmmc-supply = <&ldo9>; - status = "okay"; -}; - -&dwmmc2 { /* WIFI */ - bus-width = <0x4>; - non-removable; - broken-cd; - cap-power-off-card; - pinctrl-names = "default"; - pinctrl-0 = <&sdio_pmx_func - &sdio_clk_cfg_func - &sdio_cfg_func>; - /* WL_EN */ - vmmc-supply = <&wlan_en>; - status = "ok"; - - wlcore: wlcore@2 { - compatible = "ti,wl1837"; - reg = <2>; /* sdio func num */ - /* WL_IRQ, GPIO_179_WL_WAKEUP_AP */ - interrupt-parent = <&gpio22>; - interrupts = <3 IRQ_TYPE_EDGE_RISING>; - }; -}; diff --git a/sys/gnu/dts/arm64/hisilicon/hi3660.dtsi b/sys/gnu/dts/arm64/hisilicon/hi3660.dtsi deleted file mode 100644 index 253cc345f14..00000000000 --- a/sys/gnu/dts/arm64/hisilicon/hi3660.dtsi +++ /dev/null @@ -1,1158 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * dts file for Hisilicon Hi3660 SoC - * - * Copyright (C) 2016, Hisilicon Ltd. - */ - -#include -#include -#include - -/ { - compatible = "hisilicon,hi3660"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu-map { - cluster0 { - core0 { - cpu = <&cpu0>; - }; - core1 { - cpu = <&cpu1>; - }; - core2 { - cpu = <&cpu2>; - }; - core3 { - cpu = <&cpu3>; - }; - }; - cluster1 { - core0 { - cpu = <&cpu4>; - }; - core1 { - cpu = <&cpu5>; - }; - core2 { - cpu = <&cpu6>; - }; - core3 { - cpu = <&cpu7>; - }; - }; - }; - - cpu0: cpu@0 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <0x0 0x0>; - enable-method = "psci"; - next-level-cache = <&A53_L2>; - cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; - capacity-dmips-mhz = <592>; - clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>; - operating-points-v2 = <&cluster0_opp>; - #cooling-cells = <2>; - dynamic-power-coefficient = <110>; - }; - - cpu1: cpu@1 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <0x0 0x1>; - enable-method = "psci"; - next-level-cache = <&A53_L2>; - cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; - capacity-dmips-mhz = <592>; - clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>; - operating-points-v2 = <&cluster0_opp>; - #cooling-cells = <2>; - }; - - cpu2: cpu@2 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <0x0 0x2>; - enable-method = "psci"; - next-level-cache = <&A53_L2>; - cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; - capacity-dmips-mhz = <592>; - clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>; - operating-points-v2 = <&cluster0_opp>; - #cooling-cells = <2>; - }; - - cpu3: cpu@3 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <0x0 0x3>; - enable-method = "psci"; - next-level-cache = <&A53_L2>; - cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; - capacity-dmips-mhz = <592>; - clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>; - operating-points-v2 = <&cluster0_opp>; - #cooling-cells = <2>; - }; - - cpu4: cpu@100 { - compatible = "arm,cortex-a73"; - device_type = "cpu"; - reg = <0x0 0x100>; - enable-method = "psci"; - next-level-cache = <&A73_L2>; - cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_1>; - capacity-dmips-mhz = <1024>; - clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>; - operating-points-v2 = <&cluster1_opp>; - #cooling-cells = <2>; - dynamic-power-coefficient = <550>; - }; - - cpu5: cpu@101 { - compatible = "arm,cortex-a73"; - device_type = "cpu"; - reg = <0x0 0x101>; - enable-method = "psci"; - next-level-cache = <&A73_L2>; - cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_1>; - capacity-dmips-mhz = <1024>; - clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>; - operating-points-v2 = <&cluster1_opp>; - #cooling-cells = <2>; - }; - - cpu6: cpu@102 { - compatible = "arm,cortex-a73"; - device_type = "cpu"; - reg = <0x0 0x102>; - enable-method = "psci"; - next-level-cache = <&A73_L2>; - cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_1>; - capacity-dmips-mhz = <1024>; - clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>; - operating-points-v2 = <&cluster1_opp>; - #cooling-cells = <2>; - }; - - cpu7: cpu@103 { - compatible = "arm,cortex-a73"; - device_type = "cpu"; - reg = <0x0 0x103>; - enable-method = "psci"; - next-level-cache = <&A73_L2>; - cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_1>; - capacity-dmips-mhz = <1024>; - clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>; - operating-points-v2 = <&cluster1_opp>; - #cooling-cells = <2>; - }; - - idle-states { - entry-method = "psci"; - - CPU_SLEEP_0: cpu-sleep-0 { - compatible = "arm,idle-state"; - local-timer-stop; - arm,psci-suspend-param = <0x0010000>; - entry-latency-us = <400>; - exit-latency-us = <650>; - min-residency-us = <1500>; - }; - CLUSTER_SLEEP_0: cluster-sleep-0 { - compatible = "arm,idle-state"; - local-timer-stop; - arm,psci-suspend-param = <0x1010000>; - entry-latency-us = <500>; - exit-latency-us = <1600>; - min-residency-us = <3500>; - }; - - - CPU_SLEEP_1: cpu-sleep-1 { - compatible = "arm,idle-state"; - local-timer-stop; - arm,psci-suspend-param = <0x0010000>; - entry-latency-us = <400>; - exit-latency-us = <550>; - min-residency-us = <1500>; - }; - - CLUSTER_SLEEP_1: cluster-sleep-1 { - compatible = "arm,idle-state"; - local-timer-stop; - arm,psci-suspend-param = <0x1010000>; - entry-latency-us = <800>; - exit-latency-us = <2900>; - min-residency-us = <3500>; - }; - }; - - A53_L2: l2-cache0 { - compatible = "cache"; - }; - - A73_L2: l2-cache1 { - compatible = "cache"; - }; - }; - - cluster0_opp: opp_table0 { - compatible = "operating-points-v2"; - opp-shared; - - opp00 { - opp-hz = /bits/ 64 <533000000>; - opp-microvolt = <700000>; - clock-latency-ns = <300000>; - }; - - opp01 { - opp-hz = /bits/ 64 <999000000>; - opp-microvolt = <800000>; - clock-latency-ns = <300000>; - }; - - opp02 { - opp-hz = /bits/ 64 <1402000000>; - opp-microvolt = <900000>; - clock-latency-ns = <300000>; - }; - - opp03 { - opp-hz = /bits/ 64 <1709000000>; - opp-microvolt = <1000000>; - clock-latency-ns = <300000>; - }; - - opp04 { - opp-hz = /bits/ 64 <1844000000>; - opp-microvolt = <1100000>; - clock-latency-ns = <300000>; - }; - }; - - cluster1_opp: opp_table1 { - compatible = "operating-points-v2"; - opp-shared; - - opp10 { - opp-hz = /bits/ 64 <903000000>; - opp-microvolt = <700000>; - clock-latency-ns = <300000>; - }; - - opp11 { - opp-hz = /bits/ 64 <1421000000>; - opp-microvolt = <800000>; - clock-latency-ns = <300000>; - }; - - opp12 { - opp-hz = /bits/ 64 <1805000000>; - opp-microvolt = <900000>; - clock-latency-ns = <300000>; - }; - - opp13 { - opp-hz = /bits/ 64 <2112000000>; - opp-microvolt = <1000000>; - clock-latency-ns = <300000>; - }; - - opp14 { - opp-hz = /bits/ 64 <2362000000>; - opp-microvolt = <1100000>; - clock-latency-ns = <300000>; - }; - }; - - gic: interrupt-controller@e82b0000 { - compatible = "arm,gic-400"; - reg = <0x0 0xe82b1000 0 0x1000>, /* GICD */ - <0x0 0xe82b2000 0 0x2000>, /* GICC */ - <0x0 0xe82b4000 0 0x2000>, /* GICH */ - <0x0 0xe82b6000 0 0x2000>; /* GICV */ - #address-cells = <0>; - #interrupt-cells = <3>; - interrupt-controller; - interrupts = ; - }; - - a53-pmu { - compatible = "arm,cortex-a53-pmu"; - interrupts = , - , - , - ; - interrupt-affinity = <&cpu0>, - <&cpu1>, - <&cpu2>, - <&cpu3>; - }; - - a73-pmu { - compatible = "arm,cortex-a73-pmu"; - interrupts = , - , - , - ; - interrupt-affinity = <&cpu4>, - <&cpu5>, - <&cpu6>, - <&cpu7>; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupt-parent = <&gic>; - interrupts = , - , - , - ; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - crg_ctrl: crg_ctrl@fff35000 { - compatible = "hisilicon,hi3660-crgctrl", "syscon"; - reg = <0x0 0xfff35000 0x0 0x1000>; - #clock-cells = <1>; - }; - - crg_rst: crg_rst_controller { - compatible = "hisilicon,hi3660-reset"; - #reset-cells = <2>; - hisi,rst-syscon = <&crg_ctrl>; - }; - - - pctrl: pctrl@e8a09000 { - compatible = "hisilicon,hi3660-pctrl", "syscon"; - reg = <0x0 0xe8a09000 0x0 0x2000>; - #clock-cells = <1>; - }; - - pmuctrl: crg_ctrl@fff34000 { - compatible = "hisilicon,hi3660-pmuctrl", "syscon"; - reg = <0x0 0xfff34000 0x0 0x1000>; - #clock-cells = <1>; - }; - - sctrl: sctrl@fff0a000 { - compatible = "hisilicon,hi3660-sctrl", "syscon"; - reg = <0x0 0xfff0a000 0x0 0x1000>; - #clock-cells = <1>; - }; - - iomcu: iomcu@ffd7e000 { - compatible = "hisilicon,hi3660-iomcu", "syscon"; - reg = <0x0 0xffd7e000 0x0 0x1000>; - #clock-cells = <1>; - - }; - - iomcu_rst: reset { - compatible = "hisilicon,hi3660-reset"; - hisi,rst-syscon = <&iomcu>; - #reset-cells = <2>; - }; - - mailbox: mailbox@e896b000 { - compatible = "hisilicon,hi3660-mbox"; - reg = <0x0 0xe896b000 0x0 0x1000>; - interrupts = , - ; - #mbox-cells = <3>; - }; - - stub_clock: stub_clock@e896b500 { - compatible = "hisilicon,hi3660-stub-clk"; - reg = <0x0 0xe896b500 0x0 0x0100>; - #clock-cells = <1>; - mboxes = <&mailbox 13 3 0>; - }; - - dual_timer0: timer@fff14000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x0 0xfff14000 0x0 0x1000>; - interrupts = , - ; - clocks = <&crg_ctrl HI3660_OSC32K>, - <&crg_ctrl HI3660_OSC32K>, - <&crg_ctrl HI3660_OSC32K>; - clock-names = "timer1", "timer2", "apb_pclk"; - }; - - i2c0: i2c@ffd71000 { - compatible = "snps,designware-i2c"; - reg = <0x0 0xffd71000 0x0 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-frequency = <400000>; - clocks = <&crg_ctrl HI3660_CLK_GATE_I2C0>; - resets = <&iomcu_rst 0x20 3>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>; - status = "disabled"; - }; - - i2c1: i2c@ffd72000 { - compatible = "snps,designware-i2c"; - reg = <0x0 0xffd72000 0x0 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-frequency = <400000>; - clocks = <&crg_ctrl HI3660_CLK_GATE_I2C1>; - resets = <&iomcu_rst 0x20 4>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>; - status = "disabled"; - }; - - i2c3: i2c@fdf0c000 { - compatible = "snps,designware-i2c"; - reg = <0x0 0xfdf0c000 0x0 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-frequency = <400000>; - clocks = <&crg_ctrl HI3660_CLK_GATE_I2C3>; - resets = <&crg_rst 0x78 7>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_pmx_func &i2c3_cfg_func>; - status = "disabled"; - }; - - i2c7: i2c@fdf0b000 { - compatible = "snps,designware-i2c"; - reg = <0x0 0xfdf0b000 0x0 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-frequency = <400000>; - clocks = <&crg_ctrl HI3660_CLK_GATE_I2C7>; - resets = <&crg_rst 0x60 14>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c7_pmx_func &i2c7_cfg_func>; - status = "disabled"; - }; - - uart0: serial@fdf02000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0 0xfdf02000 0x0 0x1000>; - interrupts = ; - clocks = <&crg_ctrl HI3660_CLK_MUX_UART0>, - <&crg_ctrl HI3660_PCLK>; - clock-names = "uartclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pmx_func &uart0_cfg_func>; - status = "disabled"; - }; - - uart1: serial@fdf00000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0 0xfdf00000 0x0 0x1000>; - interrupts = ; - dma-names = "rx", "tx"; - dmas = <&dma0 2 &dma0 3>; - clocks = <&crg_ctrl HI3660_CLK_GATE_UART1>, - <&crg_ctrl HI3660_CLK_GATE_UART1>; - clock-names = "uartclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func>; - status = "disabled"; - }; - - uart2: serial@fdf03000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0 0xfdf03000 0x0 0x1000>; - interrupts = ; - dma-names = "rx", "tx"; - dmas = <&dma0 4 &dma0 5>; - clocks = <&crg_ctrl HI3660_CLK_GATE_UART2>, - <&crg_ctrl HI3660_PCLK>; - clock-names = "uartclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>; - status = "disabled"; - }; - - uart3: serial@ffd74000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0 0xffd74000 0x0 0x1000>; - interrupts = ; - clocks = <&crg_ctrl HI3660_FACTOR_UART3>, - <&crg_ctrl HI3660_PCLK>; - clock-names = "uartclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>; - status = "disabled"; - }; - - uart4: serial@fdf01000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0 0xfdf01000 0x0 0x1000>; - interrupts = ; - dma-names = "rx", "tx"; - dmas = <&dma0 6 &dma0 7>; - clocks = <&crg_ctrl HI3660_CLK_GATE_UART4>, - <&crg_ctrl HI3660_CLK_GATE_UART4>; - clock-names = "uartclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>; - status = "disabled"; - }; - - uart5: serial@fdf05000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0 0xfdf05000 0x0 0x1000>; - interrupts = ; - dma-names = "rx", "tx"; - dmas = <&dma0 8 &dma0 9>; - clocks = <&crg_ctrl HI3660_CLK_GATE_UART5>, - <&crg_ctrl HI3660_CLK_GATE_UART5>; - clock-names = "uartclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart5_pmx_func &uart5_cfg_func>; - status = "disabled"; - }; - - uart6: serial@fff32000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0 0xfff32000 0x0 0x1000>; - interrupts = ; - clocks = <&crg_ctrl HI3660_CLK_UART6>, - <&crg_ctrl HI3660_PCLK>; - clock-names = "uartclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart6_pmx_func &uart6_cfg_func>; - status = "disabled"; - }; - - dma0: dma@fdf30000 { - compatible = "hisilicon,k3-dma-1.0"; - reg = <0x0 0xfdf30000 0x0 0x1000>; - #dma-cells = <1>; - dma-channels = <16>; - dma-requests = <32>; - dma-channel-mask = <0xfffe>; - interrupts = ; - clocks = <&crg_ctrl HI3660_CLK_GATE_DMAC>; - dma-no-cci; - dma-type = "hi3660_dma"; - }; - - asp_dmac: dma-controller@e804b000 { - compatible = "hisilicon,hisi-pcm-asp-dma-1.0"; - reg = <0x0 0xe804b000 0x0 0x1000>; - #dma-cells = <1>; - dma-channels = <16>; - dma-requests = <32>; - interrupts = ; - interrupt-names = "asp_dma_irq"; - }; - - rtc0: rtc@fff04000 { - compatible = "arm,pl031", "arm,primecell"; - reg = <0x0 0Xfff04000 0x0 0x1000>; - interrupts = ; - clocks = <&crg_ctrl HI3660_PCLK>; - clock-names = "apb_pclk"; - }; - - gpio0: gpio@e8a0b000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0 0xe8a0b000 0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx0 1 0 7>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&crg_ctrl HI3660_PCLK_GPIO0>; - clock-names = "apb_pclk"; - }; - - gpio1: gpio@e8a0c000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0 0xe8a0c000 0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx0 1 7 7>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&crg_ctrl HI3660_PCLK_GPIO1>; - clock-names = "apb_pclk"; - }; - - gpio2: gpio@e8a0d000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0 0xe8a0d000 0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx0 0 14 8>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&crg_ctrl HI3660_PCLK_GPIO2>; - clock-names = "apb_pclk"; - }; - - gpio3: gpio@e8a0e000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0 0xe8a0e000 0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx0 0 22 8>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&crg_ctrl HI3660_PCLK_GPIO3>; - clock-names = "apb_pclk"; - }; - - gpio4: gpio@e8a0f000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0 0xe8a0f000 0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx0 0 30 8>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&crg_ctrl HI3660_PCLK_GPIO4>; - clock-names = "apb_pclk"; - }; - - gpio5: gpio@e8a10000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0 0xe8a10000 0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx0 0 38 8>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&crg_ctrl HI3660_PCLK_GPIO5>; - clock-names = "apb_pclk"; - }; - - gpio6: gpio@e8a11000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0 0xe8a11000 0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx0 0 46 8>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&crg_ctrl HI3660_PCLK_GPIO6>; - clock-names = "apb_pclk"; - }; - - gpio7: gpio@e8a12000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0 0xe8a12000 0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx0 0 54 8>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&crg_ctrl HI3660_PCLK_GPIO7>; - clock-names = "apb_pclk"; - }; - - gpio8: gpio@e8a13000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0 0xe8a13000 0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx0 0 62 8>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&crg_ctrl HI3660_PCLK_GPIO8>; - clock-names = "apb_pclk"; - }; - - gpio9: gpio@e8a14000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0 0xe8a14000 0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx0 0 70 8>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&crg_ctrl HI3660_PCLK_GPIO9>; - clock-names = "apb_pclk"; - }; - - gpio10: gpio@e8a15000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0 0xe8a15000 0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx0 0 78 8>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&crg_ctrl HI3660_PCLK_GPIO10>; - clock-names = "apb_pclk"; - }; - - gpio11: gpio@e8a16000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0 0xe8a16000 0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx0 0 86 8>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&crg_ctrl HI3660_PCLK_GPIO11>; - clock-names = "apb_pclk"; - }; - - gpio12: gpio@e8a17000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0 0xe8a17000 0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx0 0 94 3 &pmx0 7 101 1>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&crg_ctrl HI3660_PCLK_GPIO12>; - clock-names = "apb_pclk"; - }; - - gpio13: gpio@e8a18000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0 0xe8a18000 0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx0 0 102 8>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&crg_ctrl HI3660_PCLK_GPIO13>; - clock-names = "apb_pclk"; - }; - - gpio14: gpio@e8a19000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0 0xe8a19000 0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx0 0 110 8>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&crg_ctrl HI3660_PCLK_GPIO14>; - clock-names = "apb_pclk"; - }; - - gpio15: gpio@e8a1a000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0 0xe8a1a000 0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx0 0 118 6>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&crg_ctrl HI3660_PCLK_GPIO15>; - clock-names = "apb_pclk"; - }; - - gpio16: gpio@e8a1b000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0 0xe8a1b000 0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&crg_ctrl HI3660_PCLK_GPIO16>; - clock-names = "apb_pclk"; - }; - - gpio17: gpio@e8a1c000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0 0xe8a1c000 0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&crg_ctrl HI3660_PCLK_GPIO17>; - clock-names = "apb_pclk"; - }; - - gpio18: gpio@ff3b4000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0 0xff3b4000 0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx2 0 0 8>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&crg_ctrl HI3660_PCLK_GPIO18>; - clock-names = "apb_pclk"; - }; - - gpio19: gpio@ff3b5000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0 0xff3b5000 0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx2 0 8 4>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&crg_ctrl HI3660_PCLK_GPIO19>; - clock-names = "apb_pclk"; - }; - - gpio20: gpio@e8a1f000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0 0xe8a1f000 0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx1 0 0 6>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&crg_ctrl HI3660_PCLK_GPIO20>; - clock-names = "apb_pclk"; - }; - - gpio21: gpio@e8a20000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0 0xe8a20000 0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&pmx3 0 0 6>; - clocks = <&crg_ctrl HI3660_PCLK_GPIO21>; - clock-names = "apb_pclk"; - }; - - gpio22: gpio@fff0b000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0 0xfff0b000 0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - /* GPIO176 */ - gpio-ranges = <&pmx4 2 0 6>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&sctrl HI3660_PCLK_AO_GPIO0>; - clock-names = "apb_pclk"; - }; - - gpio23: gpio@fff0c000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0 0xfff0c000 0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - /* GPIO184 */ - gpio-ranges = <&pmx4 0 6 7>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&sctrl HI3660_PCLK_AO_GPIO1>; - clock-names = "apb_pclk"; - }; - - gpio24: gpio@fff0d000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0 0xfff0d000 0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - /* GPIO192 */ - gpio-ranges = <&pmx4 0 13 8>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&sctrl HI3660_PCLK_AO_GPIO2>; - clock-names = "apb_pclk"; - }; - - gpio25: gpio@fff0e000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0 0xfff0e000 0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - /* GPIO200 */ - gpio-ranges = <&pmx4 0 21 4 &pmx4 5 25 3>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&sctrl HI3660_PCLK_AO_GPIO3>; - clock-names = "apb_pclk"; - }; - - gpio26: gpio@fff0f000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0 0xfff0f000 0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - /* GPIO208 */ - gpio-ranges = <&pmx4 0 28 8>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&sctrl HI3660_PCLK_AO_GPIO4>; - clock-names = "apb_pclk"; - }; - - gpio27: gpio@fff10000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0 0xfff10000 0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - /* GPIO216 */ - gpio-ranges = <&pmx4 0 36 6>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&sctrl HI3660_PCLK_AO_GPIO5>; - clock-names = "apb_pclk"; - }; - - gpio28: gpio@fff1d000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0 0xfff1d000 0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&sctrl HI3660_PCLK_AO_GPIO6>; - clock-names = "apb_pclk"; - }; - - spi2: spi@ffd68000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x0 0xffd68000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clocks = <&crg_ctrl HI3660_CLK_GATE_SPI2>; - clock-names = "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&spi2_pmx_func>; - num-cs = <1>; - cs-gpios = <&gpio27 2 0>; - status = "disabled"; - }; - - spi3: spi@ff3b3000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x0 0xff3b3000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clocks = <&crg_ctrl HI3660_CLK_GATE_SPI3>; - clock-names = "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&spi3_pmx_func>; - num-cs = <1>; - cs-gpios = <&gpio18 5 0>; - status = "disabled"; - }; - - pcie@f4000000 { - compatible = "hisilicon,kirin960-pcie"; - reg = <0x0 0xf4000000 0x0 0x1000>, - <0x0 0xff3fe000 0x0 0x1000>, - <0x0 0xf3f20000 0x0 0x40000>, - <0x0 0xf5000000 0x0 0x2000>; - reg-names = "dbi", "apb", "phy", "config"; - bus-range = <0x0 0x1>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges = <0x02000000 0x0 0x00000000 - 0x0 0xf6000000 - 0x0 0x02000000>; - num-lanes = <1>; - #interrupt-cells = <1>; - interrupts = <0 283 4>; - interrupt-names = "msi"; - interrupt-map-mask = <0xf800 0 0 7>; - interrupt-map = <0x0 0 0 1 - &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, - <0x0 0 0 2 - &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, - <0x0 0 0 3 - &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, - <0x0 0 0 4 - &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&crg_ctrl HI3660_PCIEPHY_REF>, - <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>, - <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>, - <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>, - <&crg_ctrl HI3660_ACLK_GATE_PCIE>; - clock-names = "pcie_phy_ref", "pcie_aux", - "pcie_apb_phy", "pcie_apb_sys", - "pcie_aclk"; - reset-gpios = <&gpio11 1 0 >; - }; - - /* UFS */ - ufs: ufs@ff3b0000 { - compatible = "hisilicon,hi3660-ufs", "jedec,ufs-1.1"; - /* 0: HCI standard */ - /* 1: UFS SYS CTRL */ - reg = <0x0 0xff3b0000 0x0 0x1000>, - <0x0 0xff3b1000 0x0 0x1000>; - interrupt-parent = <&gic>; - interrupts = ; - clocks = <&crg_ctrl HI3660_CLK_GATE_UFSIO_REF>, - <&crg_ctrl HI3660_CLK_GATE_UFSPHY_CFG>; - clock-names = "ref_clk", "phy_clk"; - freq-table-hz = <0 0>, <0 0>; - /* offset: 0x84; bit: 12 */ - resets = <&crg_rst 0x84 12>; - reset-names = "rst"; - }; - - /* SD */ - dwmmc1: dwmmc1@ff37f000 { - compatible = "hisilicon,hi3660-dw-mshc"; - reg = <0x0 0xff37f000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clocks = <&crg_ctrl HI3660_CLK_GATE_SD>, - <&crg_ctrl HI3660_HCLK_GATE_SD>; - clock-names = "ciu", "biu"; - clock-frequency = <3200000>; - resets = <&crg_rst 0x94 18>; - reset-names = "reset"; - hisilicon,peripheral-syscon = <&sctrl>; - card-detect-delay = <200>; - status = "disabled"; - }; - - /* SDIO */ - dwmmc2: dwmmc2@ff3ff000 { - compatible = "hisilicon,hi3660-dw-mshc"; - reg = <0x0 0xff3ff000 0x0 0x1000>; - #address-cells = <0x1>; - #size-cells = <0x0>; - interrupts = ; - clocks = <&crg_ctrl HI3660_CLK_GATE_SDIO0>, - <&crg_ctrl HI3660_HCLK_GATE_SDIO0>; - clock-names = "ciu", "biu"; - resets = <&crg_rst 0x94 20>; - reset-names = "reset"; - card-detect-delay = <200>; - status = "disabled"; - }; - - watchdog0: watchdog@e8a06000 { - compatible = "arm,sp805-wdt", "arm,primecell"; - reg = <0x0 0xe8a06000 0x0 0x1000>; - interrupts = ; - clocks = <&crg_ctrl HI3660_OSC32K>; - clock-names = "apb_pclk"; - }; - - watchdog1: watchdog@e8a07000 { - compatible = "arm,sp805-wdt", "arm,primecell"; - reg = <0x0 0xe8a07000 0x0 0x1000>; - interrupts = ; - clocks = <&crg_ctrl HI3660_OSC32K>; - clock-names = "apb_pclk"; - }; - - tsensor: tsensor@fff30000 { - compatible = "hisilicon,hi3660-tsensor"; - reg = <0x0 0xfff30000 0x0 0x1000>; - interrupts = ; - #thermal-sensor-cells = <1>; - }; - - thermal-zones { - - cls0: cls0 { - polling-delay = <1000>; - polling-delay-passive = <100>; - sustainable-power = <4500>; - - /* sensor ID */ - thermal-sensors = <&tsensor 1>; - - trips { - threshold: trip-point@0 { - temperature = <65000>; - hysteresis = <1000>; - type = "passive"; - }; - - target: trip-point@1 { - temperature = <75000>; - hysteresis = <1000>; - type = "passive"; - }; - }; - - cooling-maps { - map0 { - trip = <&target>; - contribution = <1024>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&target>; - contribution = <512>; - cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - }; - }; -}; - -#include "hi3660-coresight.dtsi" diff --git a/sys/gnu/dts/arm64/hisilicon/hi3670-hikey970.dts b/sys/gnu/dts/arm64/hisilicon/hi3670-hikey970.dts deleted file mode 100644 index 7dac33d4fd5..00000000000 --- a/sys/gnu/dts/arm64/hisilicon/hi3670-hikey970.dts +++ /dev/null @@ -1,448 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * dts file for Hisilicon HiKey970 Development Board - * - * Copyright (C) 2016, Hisilicon Ltd. - * Copyright (C) 2018, Linaro Ltd. - * - */ - -/dts-v1/; -#include - -#include "hi3670.dtsi" -#include "hikey970-pinctrl.dtsi" - -/ { - model = "HiKey970"; - compatible = "hisilicon,hi3670-hikey970", "hisilicon,hi3670"; - - aliases { - mshc1 = &dwmmc1; - mshc2 = &dwmmc2; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - serial4 = &uart4; - serial5 = &uart5; - serial6 = &uart6; /* console UART */ - }; - - chosen { - stdout-path = "serial6:115200n8"; - }; - - memory@0 { - device_type = "memory"; - /* expect bootloader to fill in this region */ - reg = <0x0 0x0 0x0 0x0>; - }; - - sd_1v8: regulator-1v8 { - compatible = "regulator-fixed"; - regulator-name = "fixed-1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - sd_3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - wlan_en: wlan-en-1-8v { - compatible = "regulator-fixed"; - regulator-name = "wlan-en-regulator"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - /* GPIO_051_WIFI_EN */ - gpio = <&gpio6 3 0>; - - /* WLAN card specific delay */ - startup-delay-us = <70000>; - enable-active-high; - }; -}; - -/* - * Legend: proper name = the GPIO line is used as GPIO - * NC = not connected (pin out but not routed from the chip to - * anything the board) - * "[PER]" = pin is muxed for [peripheral] (not GPIO) - * "" = no idea, schematic doesn't say, could be - * unrouted (not connected to any external pin) - * LSEC = Low Speed External Connector - * HSEC = High Speed External Connector - * - * Line names are taken from "hikey970-schematics.pdf" from HiSilicon. - * - * For the lines routed to the external connectors the - * lines are named after the 96Boards CE Specification 1.0, - * Appendix "Expansion Connector Signal Description". - * - * When the 96Board naming of a line and the schematic name of - * the same line are in conflict, the 96Board specification - * takes precedence, which means that the external UART on the - * LSEC is named UART0 while the schematic and SoC names this - * UART2. This is only for the informational lines i.e. "[FOO]", - * the GPIO named lines "GPIO-A" thru "GPIO-L" are the only - * ones actually used for GPIO. - */ -&gpio0 { - /* GPIO_000-GPIO_007 */ - gpio-line-names = - "", - "TP901", /* TEST_MODE connected to TP901 */ - "", - "GPIO_003_USB_HUB_RESET_N", - "NC", - "[AP_GPS_REF_CLK]", - "[I2C3_SCL]", - "[I2C3_SDA]"; -}; - -&gpio1 { - /* GPIO_008-GPIO_015 */ - gpio-line-names = - "[UART0_CTS]", /* LSEC pin 3: GPIO_008_UART2_CTS_N */ - "[UART0_RTS]", /* LSEC pin 9: GPIO_009_UART2_RTS_N */ - "[UART0_TXD]", /* LSEC pin 5: GPIO_010_UART2_TXD */ - "[UART0_RXD]", /* LSEC pin 7: GPIO_011_UART2_RXD */ - "[USER_LED5]", - "GPIO-I", /* LSEC pin 31: GPIO_013_CAM0_RST_N */ - "[USER_LED3]", - "[USER_LED4]"; -}; - -&gpio2 { - /* GPIO_016-GPIO_023 */ - gpio-line-names = - "GPIO-G", /* LSEC pin 29: GPIO_016_LCD_TE0 */ - "[CSI0_MCLK]", /* HSEC pin 15: ISP_CCLK0_MCAM */ - "[CSI1_MCLK]", /* HSEC pin 17: ISP_CCLK1_SCAM */ - "GPIO_019_BT_ACTIVE", - "[I2C2_SCL]", /* HSEC pin 32: ISP_SCL0 */ - "[I2C2_SDA]", /* HSEC pin 34: ISP_SDA0 */ - "[I2C3_SCL]", /* HSEC pin 36: ISP_SCL1 */ - "[I2C3_SDA]"; /* HSEC pin 38: ISP_SDA1 */ -}; - -&gpio3 { - /* GPIO_024-GPIO_031 */ - gpio-line-names = - "GPIO_024_WIFI_ACTIVE", - "GPIO_025_PERST_M.2", - "[I2C4_SCL]", - "[I2C4_SDA]", - "NC", - "GPIO-H", /* LSEC pin 30: GPIO_029_LCD_RST_N */ - "[USER_LED1]", - "GPIO-L"; /* LSEC pin 34: GPIO_031 */ -}; - -&gpio4 { - /* GPIO_032-GPIO_039 */ - gpio-line-names = - "GPIO-K", /* LSEC pin 33: GPIO_032_CAM1_RST_N */ - "GPIO_033_PMU1_EN", - "GPIO_034_USBSW_SEL", - /* - * These two pins should be used for SD(IO) data according - * to the 96boards specification but seems to be repurposed - * for UART 0. They are however named according to the spec. - */ - "[SD_DAT1]", /* HSEC pin 3: GPIO_035_UART0_RXD */ - "[SD_DAT2]", /* HSEC pin 5: GPIO_036_UART0_TXD */ - "[UART1_RXD]", /* LSEC pin 13: DEBUG_UART6_RXD */ - "[UART1_TXD]", /* LSEC pin 11: DEBUG_UART6_TXD */ - "[SOC_GPS_UART3_CTS_N]"; /* TP2304 */ -}; - -&gpio5 { - /* GPIO_040-GPIO_047 */ - gpio-line-names = - "[SOC_GPS_UART3_RTS_N]", /* TP2302 */ - "[SOC_GPS_UART3_RXD]", /* TP2303 */ - "[SOC_GPS_UART3_TXD]", /* TP2305 */ - "[SOC_BT_UART4_CTS_N]", - "[SOC_BT_UART4_RTS_N]", - "[SOC_BT_UART4_RXD]", - "[SOC_BT_UART4_TXD]", - "NC"; -}; - -&gpio6 { - /* GPIO_048-GPIO_055 */ - gpio-line-names = - "NC", - "GPIO_049_USER_LED6", - "GPIO_050_CAN_RST", - "GPIO_051_WIFI_EN", - "GPIO-D", /* LSEC pin 26 */ - "GPIO-J", /* LSEC pin 32 */ - "GPIO_054_BT_EN", - "[GPIO_055_SEL]"; -}; - -&gpio7 { - /* GPIO_056-GPIO_063 */ - gpio-line-names = - "[PCIE_PERST_L]", "NC", "NC", "NC", "NC", "NC", "NC", "NC"; -}; - -&gpio8 { - /* GPIO_064-GPIO_071 */ - gpio-line-names = "NC", "NC", "NC", "NC", "NC", "NC", "NC", "NC"; -}; - -&gpio9 { - /* GPIO_072-GPIO_079 */ - gpio-line-names = "NC", "NC", "NC", "NC", "NC", "NC", "NC", "NC"; -}; - -&gpio10 { - /* GPIO_080-GPIO_087 */ - gpio-line-names = "NC", "NC", "NC", "NC", "NC", "NC", "NC", "NC"; -}; - -&gpio11 { - /* GPIO_088-GPIO_095 */ - gpio-line-names = "NC", "NC", "NC", "NC", "NC", "NC", "NC", "NC"; -}; - -&gpio12 { - /* GPIO_096-GPIO_103 */ - gpio-line-names = "NC", "", "", "", "", "", "", ""; -}; - -&gpio13 { - /* GPIO_104-GPIO_111 */ - gpio-line-names = "", "", "", "", "", "", "", ""; -}; - -&gpio14 { - /* GPIO_112-GPIO_119 */ - gpio-line-names = "", "", "", "", "", "", "", ""; -}; - -&gpio15 { - /* GPIO_120-GPIO_127 */ - gpio-line-names = "", "", "", "", "", "", "", ""; -}; - -&gpio16 { - /* GPIO_128-GPIO_135 */ - gpio-line-names = - "[WL_SDIO_CLK]", - "[WL_SDIO_CMD]", - "[WL_SDIO_DATA0]", - "[WL_SDIO_DATA1]", - "[WL_SDIO_DATA2]", - "[WL_SDIO_DATA3]", - "[ETH_ISOLATE]", - "NC"; -}; - -&gpio17 { - /* GPIO_136-GPIO_143 */ - gpio-line-names = - "[MINI1CLK_EN]", "NC", "", "", "", "", "", ""; -}; - -&gpio18 { - /* GPIO_144-GPIO_151 */ - gpio-line-names = - "[SPI1_SCLK]", /* HSEC pin 9: GPIO_144_SPI3_CLK */ - "[SPI1_DIN]", /* HSEC pin 11: GPIO_145_SPI3_DI */ - "[SPI1_DOUT]", /* HSEC pin 1: GPIO_146_SPI3_DO */ - "[SPI1_CS]", /* HSEC pin 7: GPIO_147_SPI3_CS0_N */ - "[POWER_INT_N]", - "[CDMA_GPS_SYNC]", - "GPIO_150_PEX_INTA", - "GPIO_151_CAN_INT"; -}; - -&gpio19 { - /* GPIO_152-GPIO_159 */ - gpio-line-names = "", "", "", "", "", "", "", ""; -}; - -&gpio20 { - /* GPIO_160-GPIO_167 */ - gpio-line-names = - "[SD_CLK]", - "[SD_CMD]", - "[SD_DATA0]", - "[SD_DATA1]", - "[SD_DATA2]", - "[SD_DATA3]", - "GPIO_166_ETHCLK_EN", - "GPIO_167_USER_LED2"; -}; - -&gpio21 { - /* GPIO_168-GPIO_175 */ - gpio-line-names = - "GPIO_168_GPS_EN", - "GPIO-C", /* LSEC pin 25: GPIO_169_USIM1_CLK */ - "GPIO-E", /* LSEC pin 27: GPIO_170_USIM1_RST */ - "GPIO-B", /* LSEC pin 24: GPIO_171_USIM1_DATA */ - "", "", "", "", ""; -}; - -&gpio22 { - /* GPIO_176-GPIO_183 */ - gpio-line-names = - "[PMU_PWR_HOLD]", - "GPIO_177_WL_WAKEUP_AP", - "[JTAG_TCK]", - "[JTAG_TMS]", - "[JTAG_TDI]", - "[JTAG_TMS]", - "GPIO_182_FATAL_ERR", - "NC"; -}; - -&gpio23 { - /* GPIO_184-GPIO_191 */ - gpio-line-names = - "GPIO_184_JTAG_SEL", - "GPIO-F", /* LSEC pin 28: GPIO_185_LCD_BL_PWM */ - "[I2C0_SCL]", /* LSEC pin 15: GPIO_186_I2C0_SCL */ - "[I2C0_SDA]", /* LSEC pin 17: GPIO_187_I2C0_SDA */ - "[GPIO_188_I2C1_SCL]", /* Actual SoC I2C1_SCL */ - "[GPIO_189_I2C1_SDA]", /* Actual SoC I2C1_SDA */ - "[I2C1_SCL]", /* LSEC pin 19: GPIO_190_I2C2_SCL */ - "[I2C2_SDA]"; /* LSEC pin 21: GPIO_191_I2C2_SDA */ -}; - -&gpio24 { - /* GPIO_192-GPIO_199 */ - gpio-line-names = - "[SD_LED]", - "NC", - "[PCM_DI]", /* LSEC pin 22: GPIO_194_I2S0_DI */ - "[PCM_DO]", /* LSEC pin 20: GPIO_195_I2S0_DO */ - "[PCM_CLK]", /* LSEC pin 18: GPIO_196_I2S0_XCLK */ - "[PCM_FS]", /* LSEC pin 16: GPIO_197_I2S0_XFS */ - "", - "[I2S2_DO]"; -}; - -&gpio25 { - /* GPIO_200-GPIO_207 */ - gpio-line-names = - "[I2S2_XCLK]", - "[I2S2_XFS]", - "GPIO_202_PERST_ETH", - "GPIO_203_PWRON_DET", - "GPIO_204_PMU1_IRQ_N", - "GPIO_205_SD_DET", - "GPIO_206_GPS_MOTION_INT", - "GPIO_207_HDMI_SEL"; -}; - -&gpio26 { - /* GPIO_208-GPIO_215 */ - gpio-line-names = - "GPIO-A", /* LSEC pin 23: GPIO_208_WAKEUP_SOC */ - "GPIO_209_VBUS_TYPEC", - "NC", - "NC", - "NC", - "[SPI0_SCLK]", /* LSEC pin 8: GPIO_213_SPI2_CLK */ - "[SPI0_DIN]", /* LSEC pin 10: GPIO_214_SPI2_DI */ - "[SPI0_DOUT]"; /* LSEC pin 14: GPIO_215_SPI2_DO */ -}; - -&gpio27 { - /* GPIO_216-GPIO_223 */ - gpio-line-names = - "[SPI0_CS]", /* LSEC pin 12: GPIO_216_SPI2_CS0_N */ - "GPIO_217_HDMI_PD", - "GPIO_218_GPS_WAKEUP_AP", - "GPIO_219_M.2CLK_EN", - "GPIO_220_PERST_MINI", - "GPIO_221_CC_INT", - "[PCIE_CLKREQ_L]", - "NC"; -}; - -&gpio28 { - /* GPIO_224-GPIO_231 */ - gpio-line-names = - "[PMU0_INT]", - "[SPMI_DATA]", - "[SPMI_CLK]", - "[CAN_SPI_CLK]", - "[CAN_SPI_DI]", - "[CAN_SPI_DO]", - "[CAN_SPI_CS]", - "GPIO_231_HDMI_INT"; -}; - -&dwmmc1 { - bus-width = <0x4>; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-sdr104; - cap-sd-highspeed; - disable-wp; - cd-inverted; - cd-gpios = <&gpio25 5 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&sd_pmx_func - &sd_clk_cfg_func - &sd_cfg_func>; - vmmc-supply = <&sd_3v3>; - vqmmc-supply = <&sd_1v8>; - status = "okay"; -}; - -&dwmmc2 { /* WIFI */ - bus-width = <0x4>; - non-removable; - broken-cd; - cap-power-off-card; - pinctrl-names = "default"; - pinctrl-0 = <&sdio_pmx_func - &sdio_clk_cfg_func - &sdio_cfg_func>; - /* WL_EN */ - vmmc-supply = <&wlan_en>; - status = "ok"; - - wlcore: wlcore@2 { - compatible = "ti,wl1837"; - reg = <2>; /* sdio func num */ - /* WL_IRQ, GPIO_177_WL_WAKEUP_AP */ - interrupt-parent = <&gpio22>; - interrupts = <1 IRQ_TYPE_EDGE_RISING>; - }; -}; - -&uart0 { - /* On High speed expansion header */ - label = "HS-UART0"; - status = "okay"; -}; - -&uart2 { - /* On Low speed expansion header */ - label = "LS-UART0"; - status = "okay"; -}; - -&uart6 { - /* On Low speed expansion header */ - label = "LS-UART1"; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/hisilicon/hi3670.dtsi b/sys/gnu/dts/arm64/hisilicon/hi3670.dtsi deleted file mode 100644 index 2dcffa3ed21..00000000000 --- a/sys/gnu/dts/arm64/hisilicon/hi3670.dtsi +++ /dev/null @@ -1,713 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * dts file for Hisilicon Hi3670 SoC - * - * Copyright (C) 2016, Hisilicon Ltd. - * Copyright (C) 2018, Linaro Ltd. - */ - -#include -#include - -/ { - compatible = "hisilicon,hi3670"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu-map { - cluster0 { - core0 { - cpu = <&cpu0>; - }; - core1 { - cpu = <&cpu1>; - }; - core2 { - cpu = <&cpu2>; - }; - core3 { - cpu = <&cpu3>; - }; - }; - cluster1 { - core0 { - cpu = <&cpu4>; - }; - core1 { - cpu = <&cpu5>; - }; - core2 { - cpu = <&cpu6>; - }; - core3 { - cpu = <&cpu7>; - }; - }; - }; - - cpu0: cpu@0 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <0x0 0x0>; - enable-method = "psci"; - }; - - cpu1: cpu@1 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <0x0 0x1>; - enable-method = "psci"; - }; - - cpu2: cpu@2 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <0x0 0x2>; - enable-method = "psci"; - }; - - cpu3: cpu@3 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <0x0 0x3>; - enable-method = "psci"; - }; - - cpu4: cpu@100 { - compatible = "arm,cortex-a73"; - device_type = "cpu"; - reg = <0x0 0x100>; - enable-method = "psci"; - }; - - cpu5: cpu@101 { - compatible = "arm,cortex-a73"; - device_type = "cpu"; - reg = <0x0 0x101>; - enable-method = "psci"; - }; - - cpu6: cpu@102 { - compatible = "arm,cortex-a73"; - device_type = "cpu"; - reg = <0x0 0x102>; - enable-method = "psci"; - }; - - cpu7: cpu@103 { - compatible = "arm,cortex-a73"; - device_type = "cpu"; - reg = <0x0 0x103>; - enable-method = "psci"; - }; - }; - - gic: interrupt-controller@e82b0000 { - compatible = "arm,gic-400"; - reg = <0x0 0xe82b1000 0 0x1000>, /* GICD */ - <0x0 0xe82b2000 0 0x2000>, /* GICC */ - <0x0 0xe82b4000 0 0x2000>, /* GICH */ - <0x0 0xe82b6000 0 0x2000>; /* GICV */ - #interrupt-cells = <3>; - #address-cells = <0>; - interrupts = ; - interrupt-controller; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupt-parent = <&gic>; - interrupts = , - , - , - ; - clock-frequency = <1920000>; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - crg_ctrl: crg_ctrl@fff35000 { - compatible = "hisilicon,hi3670-crgctrl", "syscon"; - reg = <0x0 0xfff35000 0x0 0x1000>; - #clock-cells = <1>; - }; - - crg_rst: crg_rst_controller { - compatible = "hisilicon,hi3670-reset", - "hisilicon,hi3660-reset"; - #reset-cells = <2>; - hisi,rst-syscon = <&crg_ctrl>; - }; - - pctrl: pctrl@e8a09000 { - compatible = "hisilicon,hi3670-pctrl", "syscon"; - reg = <0x0 0xe8a09000 0x0 0x1000>; - #clock-cells = <1>; - }; - - pmuctrl: crg_ctrl@fff34000 { - compatible = "hisilicon,hi3670-pmuctrl", "syscon"; - reg = <0x0 0xfff34000 0x0 0x1000>; - #clock-cells = <1>; - }; - - sctrl: sctrl@fff0a000 { - compatible = "hisilicon,hi3670-sctrl", "syscon"; - reg = <0x0 0xfff0a000 0x0 0x1000>; - #clock-cells = <1>; - }; - - iomcu: iomcu@ffd7e000 { - compatible = "hisilicon,hi3670-iomcu", "syscon"; - reg = <0x0 0xffd7e000 0x0 0x1000>; - #clock-cells = <1>; - }; - - media1_crg: media1_crgctrl@e87ff000 { - compatible = "hisilicon,hi3670-media1-crg", "syscon"; - reg = <0x0 0xe87ff000 0x0 0x1000>; - #clock-cells = <1>; - }; - - media2_crg: media2_crgctrl@e8900000 { - compatible = "hisilicon,hi3670-media2-crg","syscon"; - reg = <0x0 0xe8900000 0x0 0x1000>; - #clock-cells = <1>; - }; - - uart0: serial@fdf02000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0 0xfdf02000 0x0 0x1000>; - interrupts = ; - clocks = <&crg_ctrl HI3670_CLK_GATE_UART0>, - <&crg_ctrl HI3670_PCLK>; - clock-names = "uartclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pmx_func &uart0_cfg_func>; - status = "disabled"; - }; - - uart1: serial@fdf00000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0 0xfdf00000 0x0 0x1000>; - interrupts = ; - clocks = <&crg_ctrl HI3670_CLK_GATE_UART1>, - <&crg_ctrl HI3670_PCLK>; - clock-names = "uartclk", "apb_pclk"; - pinctrl-names = "default"; - status = "disabled"; - }; - - uart2: serial@fdf03000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0 0xfdf03000 0x0 0x1000>; - interrupts = ; - clocks = <&crg_ctrl HI3670_CLK_GATE_UART2>, - <&crg_ctrl HI3670_PCLK>; - clock-names = "uartclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>; - status = "disabled"; - }; - - uart3: serial@ffd74000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0 0xffd74000 0x0 0x1000>; - interrupts = ; - clocks = <&crg_ctrl HI3670_CLK_GATE_UART3>, - <&crg_ctrl HI3670_PCLK>; - clock-names = "uartclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>; - status = "disabled"; - }; - - uart4: serial@fdf01000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0 0xfdf01000 0x0 0x1000>; - interrupts = ; - clocks = <&crg_ctrl HI3670_CLK_GATE_UART4>, - <&crg_ctrl HI3670_PCLK>; - clock-names = "uartclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>; - status = "disabled"; - }; - - uart5: serial@fdf05000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0 0xfdf05000 0x0 0x1000>; - interrupts = ; - clocks = <&crg_ctrl HI3670_CLK_GATE_UART5>, - <&crg_ctrl HI3670_PCLK>; - clock-names = "uartclk", "apb_pclk"; - pinctrl-names = "default"; - status = "disabled"; - }; - - uart6: serial@fff32000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0 0xfff32000 0x0 0x1000>; - interrupts = ; - clocks = <&crg_ctrl HI3670_CLK_UART6>, - <&crg_ctrl HI3670_PCLK>; - clock-names = "uartclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart6_pmx_func &uart6_cfg_func>; - status = "disabled"; - }; - - gpio0: gpio@e8a0b000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xe8a0b000 0x0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx0 1 0 1 &pmx0 3 1 5>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&crg_ctrl HI3670_PCLK_GPIO0>; - clock-names = "apb_pclk"; - }; - - gpio1: gpio@e8a0c000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xe8a0c000 0x0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&crg_ctrl HI3670_PCLK_GPIO1>; - clock-names = "apb_pclk"; - }; - - gpio2: gpio@e8a0d000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xe8a0d000 0x0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx0 1 6 7>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&crg_ctrl HI3670_PCLK_GPIO2>; - clock-names = "apb_pclk"; - }; - - gpio3: gpio@e8a0e000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xe8a0e000 0x0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx0 0 13 4 &pmx0 7 17 1>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&crg_ctrl HI3670_PCLK_GPIO3>; - clock-names = "apb_pclk"; - }; - - gpio4: gpio@e8a0f000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xe8a0f000 0x0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx0 0 18 8>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&crg_ctrl HI3670_PCLK_GPIO4>; - clock-names = "apb_pclk"; - }; - - gpio5: gpio@e8a10000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xe8a10000 0x0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx0 0 26 8>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&crg_ctrl HI3670_PCLK_GPIO5>; - clock-names = "apb_pclk"; - }; - - gpio6: gpio@e8a11000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xe8a11000 0x0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx0 1 34 7>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&crg_ctrl HI3670_PCLK_GPIO6>; - clock-names = "apb_pclk"; - }; - - gpio7: gpio@e8a12000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xe8a12000 0x0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx0 0 41 8>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&crg_ctrl HI3670_PCLK_GPIO7>; - clock-names = "apb_pclk"; - }; - - gpio8: gpio@e8a13000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xe8a13000 0x0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx0 0 49 8>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&crg_ctrl HI3670_PCLK_GPIO8>; - clock-names = "apb_pclk"; - }; - - gpio9: gpio@e8a14000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xe8a14000 0x0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx0 0 57 8>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&crg_ctrl HI3670_PCLK_GPIO9>; - clock-names = "apb_pclk"; - }; - - gpio10: gpio@e8a15000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xe8a15000 0x0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx0 0 65 8>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&crg_ctrl HI3670_PCLK_GPIO10>; - clock-names = "apb_pclk"; - }; - - gpio11: gpio@e8a16000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xe8a16000 0x0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx0 0 73 8>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&crg_ctrl HI3670_PCLK_GPIO11>; - clock-names = "apb_pclk"; - }; - - gpio12: gpio@e8a17000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xe8a17000 0x0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx0 0 81 1>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&crg_ctrl HI3670_PCLK_GPIO12>; - clock-names = "apb_pclk"; - }; - - gpio13: gpio@e8a18000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xe8a18000 0x0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&crg_ctrl HI3670_PCLK_GPIO13>; - clock-names = "apb_pclk"; - }; - - gpio14: gpio@e8a19000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xe8a19000 0x0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&crg_ctrl HI3670_PCLK_GPIO14>; - clock-names = "apb_pclk"; - }; - - gpio15: gpio@e8a1a000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xe8a1a000 0x0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&crg_ctrl HI3670_PCLK_GPIO15>; - clock-names = "apb_pclk"; - }; - - gpio16: gpio@e8a1b000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xe8a1b000 0x0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx5 0 0 8>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&crg_ctrl HI3670_PCLK_GPIO16>; - clock-names = "apb_pclk"; - }; - - gpio17: gpio@e8a1c000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xe8a1c000 0x0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx5 0 8 2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&crg_ctrl HI3670_PCLK_GPIO17>; - clock-names = "apb_pclk"; - }; - - gpio18: gpio@fff28000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xfff28000 0x0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx1 4 42 4>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&sctrl HI3670_PCLK_GPIO18>; - clock-names = "apb_pclk"; - }; - - gpio19: gpio@fff29000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xfff29000 0x0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx1 0 61 2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&sctrl HI3670_PCLK_GPIO19>; - clock-names = "apb_pclk"; - }; - - gpio20: gpio@e8a1f000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xe8a1f000 0x0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx7 0 0 8>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&crg_ctrl HI3670_PCLK_GPIO20>; - clock-names = "apb_pclk"; - }; - - gpio21: gpio@e8a20000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xe8a20000 0x0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx7 0 8 4>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&crg_ctrl HI3670_PCLK_GPIO21>; - clock-names = "apb_pclk"; - }; - - gpio22: gpio@fff0b000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xfff0b000 0x0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - /* GPIO176 */ - gpio-ranges = <&pmx1 2 0 6>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&sctrl HI3670_PCLK_AO_GPIO0>; - clock-names = "apb_pclk"; - }; - - gpio23: gpio@fff0c000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xfff0c000 0x0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - /* GPIO184 */ - gpio-ranges = <&pmx1 0 6 8>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&sctrl HI3670_PCLK_AO_GPIO1>; - clock-names = "apb_pclk"; - }; - - gpio24: gpio@fff0d000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xfff0d000 0x0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - /* GPIO192 */ - gpio-ranges = <&pmx1 0 14 8>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&sctrl HI3670_PCLK_AO_GPIO2>; - clock-names = "apb_pclk"; - }; - - gpio25: gpio@fff0e000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xfff0e000 0x0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - /* GPIO200 */ - gpio-ranges = <&pmx1 0 22 8>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&sctrl HI3670_PCLK_AO_GPIO3>; - clock-names = "apb_pclk"; - }; - - gpio26: gpio@fff0f000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xfff0f000 0x0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - /* GPIO208 */ - gpio-ranges = <&pmx1 0 30 1>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&sctrl HI3670_PCLK_AO_GPIO4>; - clock-names = "apb_pclk"; - }; - - gpio27: gpio@fff10000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xfff10000 0x0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - /* GPIO216 */ - gpio-ranges = <&pmx1 4 31 4>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&sctrl HI3670_PCLK_AO_GPIO5>; - clock-names = "apb_pclk"; - }; - - gpio28: gpio@fff1d000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xfff1d000 0x0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx1 1 35 7>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&sctrl HI3670_PCLK_AO_GPIO6>; - clock-names = "apb_pclk"; - }; - - /* UFS */ - ufs: ufs@ff3c0000 { - compatible = "hisilicon,hi3670-ufs", "jedec,ufs-2.1"; - /* 0: HCI standard */ - /* 1: UFS SYS CTRL */ - reg = <0x0 0xff3c0000 0x0 0x1000>, - <0x0 0xff3e0000 0x0 0x1000>; - interrupt-parent = <&gic>; - interrupts = ; - clocks = <&crg_ctrl HI3670_CLK_GATE_UFSIO_REF>, - <&crg_ctrl HI3670_CLK_GATE_UFS_SUBSYS>; - clock-names = "ref_clk", "phy_clk"; - freq-table-hz = <0 0>, <0 0>; - /* offset: 0x84; bit: 12 */ - resets = <&crg_rst 0x84 12>; - reset-names = "rst"; - }; - - /* SD */ - dwmmc1: dwmmc1@ff37f000 { - compatible = "hisilicon,hi3670-dw-mshc", - "hisilicon,hi3660-dw-mshc"; - reg = <0x0 0xff37f000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clocks = <&crg_ctrl HI3670_CLK_GATE_SD>, - <&crg_ctrl HI3670_HCLK_GATE_SD>; - clock-names = "ciu", "biu"; - clock-frequency = <3200000>; - resets = <&crg_rst 0x94 18>; - reset-names = "reset"; - hisilicon,peripheral-syscon = <&sctrl>; - card-detect-delay = <200>; - status = "disabled"; - }; - - /* SDIO */ - dwmmc2: dwmmc2@fc183000 { - compatible = "hisilicon,hi3670-dw-mshc", - "hisilicon,hi3660-dw-mshc"; - reg = <0x0 0xfc183000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clocks = <&crg_ctrl HI3670_CLK_GATE_SDIO>, - <&crg_ctrl HI3670_HCLK_GATE_SDIO>; - clock-names = "ciu", "biu"; - clock-frequency = <3200000>; - resets = <&crg_rst 0x94 20>; - reset-names = "reset"; - card-detect-delay = <200>; - status = "disabled"; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/hisilicon/hi3798cv200-poplar.dts b/sys/gnu/dts/arm64/hisilicon/hi3798cv200-poplar.dts deleted file mode 100644 index 7d370dac4c8..00000000000 --- a/sys/gnu/dts/arm64/hisilicon/hi3798cv200-poplar.dts +++ /dev/null @@ -1,206 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * DTS File for HiSilicon Poplar Development Board - * - * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd. - */ - -/dts-v1/; - -#include -#include "hi3798cv200.dtsi" -#include "poplar-pinctrl.dtsi" - -/ { - model = "HiSilicon Poplar Development Board"; - compatible = "hisilicon,hi3798cv200-poplar", "hisilicon,hi3798cv200"; - - aliases { - serial0 = &uart0; - serial2 = &uart2; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; - - leds { - compatible = "gpio-leds"; - - user-led0 { - label = "green:user1"; - gpios = <&gpio6 3 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - - user-led1 { - label = "green:user2"; - gpios = <&gpio5 1 GPIO_ACTIVE_LOW>; - linux,default-trigger = "mmc0"; - default-state = "off"; - }; - - user-led2 { - label = "green:user3"; - gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; - linux,default-trigger = "mmc1"; - default-state = "off"; - }; - - user-led3 { - label = "green:user4"; - gpios = <&gpio10 6 GPIO_ACTIVE_LOW>; - linux,default-trigger = "none"; - panic-indicator; - default-state = "off"; - }; - }; - - reg_pcie: regulator-pcie { - compatible = "regulator-fixed"; - regulator-name = "3V3_PCIE0"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio6 7 0>; - enable-active-high; - }; -}; - -&ehci { - status = "okay"; -}; - -&emmc { - pinctrl-names = "default"; - pinctrl-0 = <&emmc_pins_1 &emmc_pins_2 - &emmc_pins_3 &emmc_pins_4>; - fifo-depth = <256>; - clock-frequency = <200000000>; - cap-mmc-highspeed; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - non-removable; - bus-width = <8>; - status = "okay"; -}; - -&gmac1 { - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - phy-handle = <ð_phy1>; - phy-mode = "rgmii"; - hisilicon,phy-reset-delays-us = <10000 10000 30000>; - - eth_phy1: phy@3 { - reg = <3>; - }; -}; - -&gpio1 { - status = "okay"; - gpio-line-names = "GPIO-E", "", - "", "", - "", "GPIO-F", - "", "GPIO-J"; -}; - -&gpio2 { - status = "okay"; - gpio-line-names = "GPIO-H", "GPIO-I", - "GPIO-L", "GPIO-G", - "GPIO-K", "", - "", ""; -}; - -&gpio3 { - status = "okay"; - gpio-line-names = "", "", - "", "", - "GPIO-C", "", - "", "GPIO-B"; -}; - -&gpio4 { - status = "okay"; - gpio-line-names = "", "", - "", "", - "", "GPIO-D", - "", ""; -}; - -&gpio5 { - status = "okay"; - gpio-line-names = "", "USER-LED-1", - "USER-LED-2", "", - "", "GPIO-A", - "", ""; -}; - -&gpio6 { - status = "okay"; - gpio-line-names = "", "", - "", "USER-LED-0", - "", "", - "", ""; -}; - -&gpio10 { - status = "okay"; - gpio-line-names = "", "", - "", "", - "", "", - "USER-LED-3", ""; -}; - -&i2c0 { - status = "okay"; - label = "LS-I2C0"; -}; - -&i2c2 { - status = "okay"; - label = "LS-I2C1"; -}; - -&ir { - linux,rc-map-name = "rc-hisi-poplar"; - status = "okay"; -}; - -&ohci { - status = "okay"; -}; - -&pcie { - reset-gpios = <&gpio4 4 GPIO_ACTIVE_HIGH>; - vpcie-supply = <®_pcie>; - status = "okay"; -}; - -&sd0 { - bus-width = <4>; - cap-sd-highspeed; - status = "okay"; -}; - -&spi0 { - status = "okay"; - label = "LS-SPI0"; -}; - -&uart0 { - status = "okay"; -}; - -&uart2 { - status = "okay"; - label = "LS-UART0"; -}; -/* No optional LS-UART1 on Low Speed Expansion Connector. */ diff --git a/sys/gnu/dts/arm64/hisilicon/hi3798cv200.dtsi b/sys/gnu/dts/arm64/hisilicon/hi3798cv200.dtsi deleted file mode 100644 index 12bc1d3ed42..00000000000 --- a/sys/gnu/dts/arm64/hisilicon/hi3798cv200.dtsi +++ /dev/null @@ -1,620 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * DTS File for HiSilicon Hi3798cv200 SoC. - * - * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd. - */ - -#include -#include -#include -#include -#include - -/ { - compatible = "hisilicon,hi3798cv200"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu@0 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <0x0 0x0>; - enable-method = "psci"; - }; - - cpu@1 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <0x0 0x1>; - enable-method = "psci"; - }; - - cpu@2 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <0x0 0x2>; - enable-method = "psci"; - }; - - cpu@3 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <0x0 0x3>; - enable-method = "psci"; - }; - }; - - gic: interrupt-controller@f1001000 { - compatible = "arm,gic-400"; - reg = <0x0 0xf1001000 0x0 0x1000>, /* GICD */ - <0x0 0xf1002000 0x0 0x100>; /* GICC */ - #address-cells = <0>; - #interrupt-cells = <3>; - interrupt-controller; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - soc: soc@f0000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0xf0000000 0x10000000>; - - crg: clock-reset-controller@8a22000 { - compatible = "hisilicon,hi3798cv200-crg", "syscon", "simple-mfd"; - reg = <0x8a22000 0x1000>; - #clock-cells = <1>; - #reset-cells = <2>; - - gmacphyrst: reset-controller { - compatible = "ti,syscon-reset"; - #reset-cells = <1>; - ti,reset-bits = - <0xcc 12 0xcc 12 0 0 (ASSERT_CLEAR | - DEASSERT_SET|STATUS_NONE)>, - <0xcc 13 0xcc 13 0 0 (ASSERT_CLEAR | - DEASSERT_SET|STATUS_NONE)>; - }; - }; - - sysctrl: system-controller@8000000 { - compatible = "hisilicon,hi3798cv200-sysctrl", "syscon"; - reg = <0x8000000 0x1000>; - #clock-cells = <1>; - #reset-cells = <2>; - }; - - perictrl: peripheral-controller@8a20000 { - compatible = "hisilicon,hi3798cv200-perictrl", "syscon", - "simple-mfd"; - reg = <0x8a20000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x8a20000 0x1000>; - - usb2_phy1: usb2-phy@120 { - compatible = "hisilicon,hi3798cv200-usb2-phy"; - reg = <0x120 0x4>; - clocks = <&crg HISTB_USB2_PHY1_REF_CLK>; - resets = <&crg 0xbc 4>; - #address-cells = <1>; - #size-cells = <0>; - - usb2_phy1_port0: phy@0 { - reg = <0>; - #phy-cells = <0>; - resets = <&crg 0xbc 8>; - }; - - usb2_phy1_port1: phy@1 { - reg = <1>; - #phy-cells = <0>; - resets = <&crg 0xbc 9>; - }; - }; - - usb2_phy2: usb2-phy@124 { - compatible = "hisilicon,hi3798cv200-usb2-phy"; - reg = <0x124 0x4>; - clocks = <&crg HISTB_USB2_PHY2_REF_CLK>; - resets = <&crg 0xbc 6>; - #address-cells = <1>; - #size-cells = <0>; - - usb2_phy2_port0: phy@0 { - reg = <0>; - #phy-cells = <0>; - resets = <&crg 0xbc 10>; - }; - }; - - combphy0: phy@850 { - compatible = "hisilicon,hi3798cv200-combphy"; - reg = <0x850 0x8>; - #phy-cells = <1>; - clocks = <&crg HISTB_COMBPHY0_CLK>; - resets = <&crg 0x188 4>; - assigned-clocks = <&crg HISTB_COMBPHY0_CLK>; - assigned-clock-rates = <100000000>; - hisilicon,fixed-mode = ; - }; - - combphy1: phy@858 { - compatible = "hisilicon,hi3798cv200-combphy"; - reg = <0x858 0x8>; - #phy-cells = <1>; - clocks = <&crg HISTB_COMBPHY1_CLK>; - resets = <&crg 0x188 12>; - assigned-clocks = <&crg HISTB_COMBPHY1_CLK>; - assigned-clock-rates = <100000000>; - hisilicon,mode-select-bits = <0x0008 11 (0x3 << 11)>; - }; - }; - - pmx0: pinconf@8a21000 { - compatible = "pinconf-single"; - reg = <0x8a21000 0x180>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <7>; - pinctrl-single,gpio-range = < - &range 0 8 2 /* GPIO 0 */ - &range 8 1 0 /* GPIO 1 */ - &range 9 4 2 - &range 13 1 0 - &range 14 1 1 - &range 15 1 0 - &range 16 5 0 /* GPIO 2 */ - &range 21 3 1 - &range 24 4 1 /* GPIO 3 */ - &range 28 2 2 - &range 86 1 1 - &range 87 1 0 - &range 30 4 2 /* GPIO 4 */ - &range 34 3 0 - &range 37 1 2 - &range 38 3 2 /* GPIO 6 */ - &range 41 5 0 - &range 46 8 1 /* GPIO 7 */ - &range 54 8 1 /* GPIO 8 */ - &range 64 7 1 /* GPIO 9 */ - &range 71 1 0 - &range 72 6 1 /* GPIO 10 */ - &range 78 1 0 - &range 79 1 1 - &range 80 6 1 /* GPIO 11 */ - &range 70 2 1 - &range 88 8 0 /* GPIO 12 */ - >; - - range: gpio-range { - #pinctrl-single,gpio-range-cells = <3>; - }; - }; - - uart0: serial@8b00000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x8b00000 0x1000>; - interrupts = ; - clocks = <&sysctrl HISTB_UART0_CLK>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - uart2: serial@8b02000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x8b02000 0x1000>; - interrupts = ; - clocks = <&crg HISTB_UART2_CLK>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - i2c0: i2c@8b10000 { - compatible = "hisilicon,hix5hd2-i2c"; - reg = <0x8b10000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clock-frequency = <400000>; - clocks = <&crg HISTB_I2C0_CLK>; - status = "disabled"; - }; - - i2c1: i2c@8b11000 { - compatible = "hisilicon,hix5hd2-i2c"; - reg = <0x8b11000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clock-frequency = <400000>; - clocks = <&crg HISTB_I2C1_CLK>; - status = "disabled"; - }; - - i2c2: i2c@8b12000 { - compatible = "hisilicon,hix5hd2-i2c"; - reg = <0x8b12000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clock-frequency = <400000>; - clocks = <&crg HISTB_I2C2_CLK>; - status = "disabled"; - }; - - i2c3: i2c@8b13000 { - compatible = "hisilicon,hix5hd2-i2c"; - reg = <0x8b13000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clock-frequency = <400000>; - clocks = <&crg HISTB_I2C3_CLK>; - status = "disabled"; - }; - - i2c4: i2c@8b14000 { - compatible = "hisilicon,hix5hd2-i2c"; - reg = <0x8b14000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clock-frequency = <400000>; - clocks = <&crg HISTB_I2C4_CLK>; - status = "disabled"; - }; - - spi0: spi@8b1a000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x8b1a000 0x1000>; - interrupts = ; - num-cs = <1>; - cs-gpios = <&gpio7 1 0>; - clocks = <&crg HISTB_SPI0_CLK>; - clock-names = "apb_pclk"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - sd0: mmc@9820000 { - compatible = "snps,dw-mshc"; - reg = <0x9820000 0x10000>; - interrupts = ; - clocks = <&crg HISTB_SDIO0_CIU_CLK>, - <&crg HISTB_SDIO0_BIU_CLK>; - clock-names = "ciu", "biu"; - resets = <&crg 0x9c 4>; - reset-names = "reset"; - status = "disabled"; - }; - - emmc: mmc@9830000 { - compatible = "hisilicon,hi3798cv200-dw-mshc"; - reg = <0x9830000 0x10000>; - interrupts = ; - clocks = <&crg HISTB_MMC_CIU_CLK>, - <&crg HISTB_MMC_BIU_CLK>, - <&crg HISTB_MMC_SAMPLE_CLK>, - <&crg HISTB_MMC_DRV_CLK>; - clock-names = "ciu", "biu", "ciu-sample", "ciu-drive"; - resets = <&crg 0xa0 4>; - reset-names = "reset"; - status = "disabled"; - }; - - gpio0: gpio@8b20000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x8b20000 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&pmx0 0 0 8>; - clocks = <&crg HISTB_APB_CLK>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - gpio1: gpio@8b21000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x8b21000 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = < - &pmx0 0 8 1 - &pmx0 1 9 4 - &pmx0 5 13 1 - &pmx0 6 14 1 - &pmx0 7 15 1 - >; - clocks = <&crg HISTB_APB_CLK>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - gpio2: gpio@8b22000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x8b22000 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&pmx0 0 16 5 &pmx0 5 21 3>; - clocks = <&crg HISTB_APB_CLK>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - gpio3: gpio@8b23000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x8b23000 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = < - &pmx0 0 24 4 - &pmx0 4 28 2 - &pmx0 6 86 1 - &pmx0 7 87 1 - >; - clocks = <&crg HISTB_APB_CLK>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - gpio4: gpio@8b24000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x8b24000 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&pmx0 0 30 4 &pmx0 4 34 3 &pmx0 7 37 1>; - clocks = <&crg HISTB_APB_CLK>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - gpio5: gpio@8004000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x8004000 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&crg HISTB_APB_CLK>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - gpio6: gpio@8b26000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x8b26000 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&pmx0 0 38 3 &pmx0 0 41 5>; - clocks = <&crg HISTB_APB_CLK>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - gpio7: gpio@8b27000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x8b27000 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&pmx0 0 46 8>; - clocks = <&crg HISTB_APB_CLK>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - gpio8: gpio@8b28000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x8b28000 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&pmx0 0 54 8>; - clocks = <&crg HISTB_APB_CLK>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - gpio9: gpio@8b29000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x8b29000 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&pmx0 0 64 7 &pmx0 71 1>; - clocks = <&crg HISTB_APB_CLK>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - gpio10: gpio@8b2a000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x8b2a000 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&pmx0 0 72 6 &pmx0 6 78 1 &pmx0 7 79 1>; - clocks = <&crg HISTB_APB_CLK>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - gpio11: gpio@8b2b000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x8b2b000 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&pmx0 0 80 6 &pmx0 6 70 2>; - clocks = <&crg HISTB_APB_CLK>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - gpio12: gpio@8b2c000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x8b2c000 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&pmx0 0 88 8>; - clocks = <&crg HISTB_APB_CLK>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - gmac0: ethernet@9840000 { - compatible = "hisilicon,hi3798cv200-gmac", "hisilicon,hisi-gmac-v2"; - reg = <0x9840000 0x1000>, - <0x984300c 0x4>; - interrupts = ; - clocks = <&crg HISTB_ETH0_MAC_CLK>, - <&crg HISTB_ETH0_MACIF_CLK>; - clock-names = "mac_core", "mac_ifc"; - resets = <&crg 0xcc 8>, - <&crg 0xcc 10>, - <&gmacphyrst 0>; - reset-names = "mac_core", "mac_ifc", "phy"; - status = "disabled"; - }; - - gmac1: ethernet@9841000 { - compatible = "hisilicon,hi3798cv200-gmac", "hisilicon,hisi-gmac-v2"; - reg = <0x9841000 0x1000>, - <0x9843010 0x4>; - interrupts = ; - clocks = <&crg HISTB_ETH1_MAC_CLK>, - <&crg HISTB_ETH1_MACIF_CLK>; - clock-names = "mac_core", "mac_ifc"; - resets = <&crg 0xcc 9>, - <&crg 0xcc 11>, - <&gmacphyrst 1>; - reset-names = "mac_core", "mac_ifc", "phy"; - status = "disabled"; - }; - - ir: ir@8001000 { - compatible = "hisilicon,hix5hd2-ir"; - reg = <0x8001000 0x1000>; - interrupts = ; - clocks = <&sysctrl HISTB_IR_CLK>; - status = "disabled"; - }; - - pcie: pcie@9860000 { - compatible = "hisilicon,hi3798cv200-pcie"; - reg = <0x9860000 0x1000>, - <0x0 0x2000>, - <0x2000000 0x01000000>; - reg-names = "control", "rc-dbi", "config"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - bus-range = <0x00 0xff>; - num-lanes = <1>; - ranges = <0x81000000 0x0 0x00000000 0x4f00000 0x0 0x100000 - 0x82000000 0x0 0x3000000 0x3000000 0x0 0x01f00000>; - interrupts = ; - interrupt-names = "msi"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic 0 131 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&crg HISTB_PCIE_AUX_CLK>, - <&crg HISTB_PCIE_PIPE_CLK>, - <&crg HISTB_PCIE_SYS_CLK>, - <&crg HISTB_PCIE_BUS_CLK>; - clock-names = "aux", "pipe", "sys", "bus"; - resets = <&crg 0x18c 6>, <&crg 0x18c 5>, <&crg 0x18c 4>; - reset-names = "soft", "sys", "bus"; - phys = <&combphy1 PHY_TYPE_PCIE>; - phy-names = "phy"; - status = "disabled"; - }; - - ohci: ohci@9880000 { - compatible = "generic-ohci"; - reg = <0x9880000 0x10000>; - interrupts = ; - clocks = <&crg HISTB_USB2_BUS_CLK>, - <&crg HISTB_USB2_12M_CLK>, - <&crg HISTB_USB2_48M_CLK>; - clock-names = "bus", "clk12", "clk48"; - resets = <&crg 0xb8 12>; - reset-names = "bus"; - phys = <&usb2_phy1_port0>; - phy-names = "usb"; - status = "disabled"; - }; - - ehci: ehci@9890000 { - compatible = "generic-ehci"; - reg = <0x9890000 0x10000>; - interrupts = ; - clocks = <&crg HISTB_USB2_BUS_CLK>, - <&crg HISTB_USB2_PHY_CLK>, - <&crg HISTB_USB2_UTMI_CLK>; - clock-names = "bus", "phy", "utmi"; - resets = <&crg 0xb8 12>, - <&crg 0xb8 16>, - <&crg 0xb8 13>; - reset-names = "bus", "phy", "utmi"; - phys = <&usb2_phy1_port0>; - phy-names = "usb"; - status = "disabled"; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/hisilicon/hi6220-coresight.dtsi b/sys/gnu/dts/arm64/hisilicon/hi6220-coresight.dtsi deleted file mode 100644 index 651771a73ed..00000000000 --- a/sys/gnu/dts/arm64/hisilicon/hi6220-coresight.dtsi +++ /dev/null @@ -1,368 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * dtsi file for Hisilicon Hi6220 coresight - * - * Copyright (C) 2017 Hisilicon Ltd. - * - * Author: Pengcheng Li - * Leo Yan - */ - -/ { - soc { - funnel@f6401000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0xf6401000 0 0x1000>; - clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; - clock-names = "apb_pclk"; - - out-ports { - port { - soc_funnel_out: endpoint { - remote-endpoint = - <&etf_in>; - }; - }; - }; - - in-ports { - port { - soc_funnel_in: endpoint { - remote-endpoint = - <&acpu_funnel_out>; - }; - }; - }; - }; - - etf@f6402000 { - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0 0xf6402000 0 0x1000>; - clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; - clock-names = "apb_pclk"; - - in-ports { - port { - etf_in: endpoint { - remote-endpoint = - <&soc_funnel_out>; - }; - }; - }; - - out-ports { - port { - etf_out: endpoint { - remote-endpoint = - <&replicator_in>; - }; - }; - }; - }; - - replicator { - compatible = "arm,coresight-static-replicator"; - clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; - clock-names = "apb_pclk"; - - in-ports { - port { - replicator_in: endpoint { - remote-endpoint = - <&etf_out>; - }; - }; - }; - - out-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - replicator_out0: endpoint { - remote-endpoint = - <&etr_in>; - }; - }; - - port@1 { - reg = <1>; - replicator_out1: endpoint { - remote-endpoint = - <&tpiu_in>; - }; - }; - }; - }; - - etr@f6404000 { - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0 0xf6404000 0 0x1000>; - clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; - clock-names = "apb_pclk"; - - in-ports { - port { - etr_in: endpoint { - remote-endpoint = - <&replicator_out0>; - }; - }; - }; - }; - - tpiu@f6405000 { - compatible = "arm,coresight-tpiu", "arm,primecell"; - reg = <0 0xf6405000 0 0x1000>; - clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; - clock-names = "apb_pclk"; - - in-ports { - port { - tpiu_in: endpoint { - remote-endpoint = - <&replicator_out1>; - }; - }; - }; - }; - - funnel@f6501000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0xf6501000 0 0x1000>; - clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; - clock-names = "apb_pclk"; - - out-ports { - port { - acpu_funnel_out: endpoint { - remote-endpoint = - <&soc_funnel_in>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - acpu_funnel_in0: endpoint { - remote-endpoint = - <&etm0_out>; - }; - }; - - port@1 { - reg = <1>; - acpu_funnel_in1: endpoint { - remote-endpoint = - <&etm1_out>; - }; - }; - - port@2 { - reg = <2>; - acpu_funnel_in2: endpoint { - remote-endpoint = - <&etm2_out>; - }; - }; - - port@3 { - reg = <3>; - acpu_funnel_in3: endpoint { - remote-endpoint = - <&etm3_out>; - }; - }; - - port@4 { - reg = <4>; - acpu_funnel_in4: endpoint { - remote-endpoint = - <&etm4_out>; - }; - }; - - port@5 { - reg = <5>; - acpu_funnel_in5: endpoint { - remote-endpoint = - <&etm5_out>; - }; - }; - - port@6 { - reg = <6>; - acpu_funnel_in6: endpoint { - remote-endpoint = - <&etm6_out>; - }; - }; - - port@7 { - reg = <7>; - acpu_funnel_in7: endpoint { - remote-endpoint = - <&etm7_out>; - }; - }; - }; - }; - - etm@f659c000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0xf659c000 0 0x1000>; - - clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; - clock-names = "apb_pclk"; - - cpu = <&cpu0>; - - out-ports { - port { - etm0_out: endpoint { - remote-endpoint = - <&acpu_funnel_in0>; - }; - }; - }; - }; - - etm@f659d000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0xf659d000 0 0x1000>; - - clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; - clock-names = "apb_pclk"; - - cpu = <&cpu1>; - - out-ports { - port { - etm1_out: endpoint { - remote-endpoint = - <&acpu_funnel_in1>; - }; - }; - }; - }; - - etm@f659e000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0xf659e000 0 0x1000>; - - clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; - clock-names = "apb_pclk"; - - cpu = <&cpu2>; - - out-ports { - port { - etm2_out: endpoint { - remote-endpoint = - <&acpu_funnel_in2>; - }; - }; - }; - }; - - etm@f659f000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0xf659f000 0 0x1000>; - - clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; - clock-names = "apb_pclk"; - - cpu = <&cpu3>; - - out-ports { - port { - etm3_out: endpoint { - remote-endpoint = - <&acpu_funnel_in3>; - }; - }; - }; - }; - - etm@f65dc000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0xf65dc000 0 0x1000>; - - clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; - clock-names = "apb_pclk"; - - cpu = <&cpu4>; - - out-ports { - port { - etm4_out: endpoint { - remote-endpoint = - <&acpu_funnel_in4>; - }; - }; - }; - }; - - etm@f65dd000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0xf65dd000 0 0x1000>; - - clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; - clock-names = "apb_pclk"; - - cpu = <&cpu5>; - - out-ports { - port { - etm5_out: endpoint { - remote-endpoint = - <&acpu_funnel_in5>; - }; - }; - }; - }; - - etm@f65de000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0xf65de000 0 0x1000>; - - clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; - clock-names = "apb_pclk"; - - cpu = <&cpu6>; - - out-ports { - port { - etm6_out: endpoint { - remote-endpoint = - <&acpu_funnel_in6>; - }; - }; - }; - }; - - etm@f65df000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0xf65df000 0 0x1000>; - - clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; - clock-names = "apb_pclk"; - - cpu = <&cpu7>; - - out-ports { - port { - etm7_out: endpoint { - remote-endpoint = - <&acpu_funnel_in7>; - }; - }; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/hisilicon/hi6220-hikey.dts b/sys/gnu/dts/arm64/hisilicon/hi6220-hikey.dts deleted file mode 100644 index c14205cd6bf..00000000000 --- a/sys/gnu/dts/arm64/hisilicon/hi6220-hikey.dts +++ /dev/null @@ -1,551 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * dts file for Hisilicon HiKey Development Board - * - * Copyright (C) 2015, Hisilicon Ltd. - * - */ - -/dts-v1/; -#include "hi6220.dtsi" -#include "hikey-pinctrl.dtsi" -#include - -/ { - model = "HiKey Development Board"; - compatible = "hisilicon,hi6220-hikey", "hisilicon,hi6220"; - - aliases { - serial0 = &uart0; /* On board UART0 */ - serial1 = &uart1; /* BT UART */ - serial2 = &uart2; /* LS Expansion UART0 */ - serial3 = &uart3; /* LS Expansion UART1 */ - }; - - chosen { - stdout-path = "serial3:115200n8"; - }; - - /* - * Reserve below regions from memory node: - * - * 0x05e0,0000 - 0x05ef,ffff: MCU firmware runtime using - * 0x05f0,1000 - 0x05f0,1fff: Reboot reason - * 0x06df,f000 - 0x06df,ffff: Mailbox message data - * 0x0740,f000 - 0x0740,ffff: MCU firmware section - * 0x21f0,0000 - 0x21ff,ffff: pstore/ramoops buffer - * 0x3e00,0000 - 0x3fff,ffff: OP-TEE - */ - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x00000000 0x00000000 0x05e00000>, - <0x00000000 0x05f00000 0x00000000 0x00001000>, - <0x00000000 0x05f02000 0x00000000 0x00efd000>, - <0x00000000 0x06e00000 0x00000000 0x0060f000>, - <0x00000000 0x07410000 0x00000000 0x1aaf0000>, - <0x00000000 0x22000000 0x00000000 0x1c000000>; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - ramoops@21f00000 { - compatible = "ramoops"; - reg = <0x0 0x21f00000 0x0 0x00100000>; - record-size = <0x00020000>; - console-size = <0x00020000>; - ftrace-size = <0x00020000>; - }; - - /* global autoconfigured region for contiguous allocations */ - linux,cma { - compatible = "shared-dma-pool"; - reusable; - size = <0x00000000 0x08000000>; - linux,cma-default; - }; - }; - - reboot-mode-syscon@5f01000 { - compatible = "syscon", "simple-mfd"; - reg = <0x0 0x05f01000 0x0 0x00001000>; - - reboot-mode { - compatible = "syscon-reboot-mode"; - offset = <0x0>; - - mode-normal = <0x77665501>; - mode-bootloader = <0x77665500>; - mode-recovery = <0x77665502>; - }; - }; - - reg_sys_5v: regulator@0 { - compatible = "regulator-fixed"; - regulator-name = "SYS_5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_vdd_3v3: regulator@1 { - compatible = "regulator-fixed"; - regulator-name = "VDD_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - vin-supply = <®_sys_5v>; - }; - - reg_5v_hub: regulator@2 { - compatible = "regulator-fixed"; - regulator-name = "5V_HUB"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - gpio = <&gpio0 7 0>; - regulator-always-on; - vin-supply = <®_sys_5v>; - }; - - wl1835_pwrseq: wl1835-pwrseq { - compatible = "mmc-pwrseq-simple"; - /* WLAN_EN GPIO */ - reset-gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; - clocks = <&pmic>; - clock-names = "ext_clock"; - post-power-on-delay-ms = <10>; - power-off-delay-us = <10>; - }; - - soc { - spi0: spi@f7106000 { - status = "ok"; - }; - - i2c0: i2c@f7100000 { - status = "ok"; - }; - - i2c1: i2c@f7101000 { - status = "ok"; - }; - - uart1: uart@f7111000 { - assigned-clocks = <&sys_ctrl HI6220_UART1_SRC>; - assigned-clock-rates = <150000000>; - status = "ok"; - - bluetooth { - compatible = "ti,wl1835-st"; - enable-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; - clocks = <&pmic>; - clock-names = "ext_clock"; - }; - }; - - uart2: uart@f7112000 { - status = "ok"; - }; - - uart3: uart@f7113000 { - status = "ok"; - }; - - /* - * Legend: proper name = the GPIO line is used as GPIO - * NC = not connected (not routed from the SoC) - * "[PER]" = pin is muxed for peripheral (not GPIO) - * "" = no idea, schematic doesn't say, could be - * unrouted (not connected to any external pin) - * LSEC = Low Speed External Connector - * HSEC = High Speed External Connector - * - * Pin assignments taken from LeMaker and CircuitCo Schematics - * Rev A1. - * - * For the lines routed to the external connectors the - * lines are named after the 96Boards CE Specification 1.0, - * Appendix "Expansion Connector Signal Description". - * - * When the 96Board naming of a line and the schematic name of - * the same line are in conflict, the 96Board specification - * takes precedence, which means that the external UART on the - * LSEC is named UART0 while the schematic and SoC names this - * UART2. This is only for the informational lines i.e. "[FOO]", - * the GPIO named lines "GPIO-A" thru "GPIO-L" are the only - * ones actually used for GPIO. - */ - gpio0: gpio@f8011000 { - gpio-line-names = "PWR_HOLD", "DSI_SEL", - "USB_HUB_RESET_N", "USB_SEL", "HDMI_PD", "WL_REG_ON", - "PWRON_DET", "5V_HUB_EN"; - }; - - gpio1: gpio@f8012000 { - gpio-line-names = "SD_DET", "HDMI_INT", "PMU_IRQ_N", - "WL_HOST_WAKE", "NC", "NC", "NC", "BT_REG_ON"; - }; - - gpio2: gpio@f8013000 { - gpio-line-names = - "GPIO-A", /* LSEC Pin 23: GPIO2_0 */ - "GPIO-B", /* LSEC Pin 24: GPIO2_1 */ - "GPIO-C", /* LSEC Pin 25: GPIO2_2 */ - "GPIO-D", /* LSEC Pin 26: GPIO2_3 */ - "GPIO-E", /* LSEC Pin 27: GPIO2_4 */ - "USB_ID_DET", "USB_VBUS_DET", - "GPIO-H"; /* LSEC Pin 30: GPIO2_7 */ - }; - - gpio3: gpio@f8014000 { - gpio-line-names = "GPIO3_0", "NC", "NC", "", "NC", "", - "WLAN_ACTIVE", "NC", "NC"; - }; - - gpio4: gpio@f7020000 { - gpio-line-names = "USER_LED1", "USER_LED2", "USER_LED3", - "USER_LED4", "SD_SEL", "NC", "NC", "BT_ACTIVE"; - }; - - gpio5: gpio@f7021000 { - gpio-line-names = "NC", "NC", - "[UART1_RxD]", /* LSEC Pin 11: UART3_RX */ - "[UART1_TxD]", /* LSEC Pin 13: UART3_TX */ - "[AUX_SSI1]", "NC", - "[PCM_CLK]", /* LSEC Pin 18: MODEM_PCM_XCLK */ - "[PCM_FS]"; /* LSEC Pin 16: MODEM_PCM_XFS */ - }; - - gpio6: gpio@f7022000 { - gpio-line-names = - "[SPI0_DIN]", /* Pin 10: SPI0_DI */ - "[SPI0_DOUT]", /* Pin 14: SPI0_DO */ - "[SPI0_CS]", /* Pin 12: SPI0_CS_N */ - "[SPI0_SCLK]", /* Pin 8: SPI0_SCLK */ - "NC", "NC", "NC", - "GPIO-G"; /* Pin 29: GPIO6_7_DSI_TE0 */ - }; - - gpio7: gpio@f7023000 { - gpio-line-names = "NC", "NC", "NC", "NC", - "[PCM_DI]", /* Pin 22: MODEM_PCM_DI */ - "[PCM_DO]", /* Pin 20: MODEM_PCM_DO */ - "NC", "NC"; - }; - - gpio8: gpio@f7024000 { - gpio-line-names = "NC", "[CEC_CLK_19_2MHZ]", "NC", - "", "", "", "", "", ""; - }; - - gpio9: gpio@f7025000 { - gpio-line-names = "", - "GPIO-J", /* LSEC Pin 32: ISP_PWDN0_GPIO9_1 */ - "GPIO-L", /* LSEC Pin 34: ISP_PWDN1_GPIO9_2 */ - "NC", "NC", "NC", "NC", "[ISP_CCLK0]"; - }; - - gpio10: gpio@f7026000 { - gpio-line-names = "BOOT_SEL", - "[ISP_CCLK1]", - "GPIO-I", /* LSEC Pin 31: ISP_RSTB0_GPIO10_2 */ - "GPIO-K", /* LSEC Pin 33: ISP_RSTB1_GPIO10_3 */ - "NC", "NC", - "[I2C2_SDA]", /* HSEC Pin 34: ISP0_SDA */ - "[I2C2_SCL]"; /* HSEC Pin 32: ISP0_SCL */ - }; - - gpio11: gpio@f7027000 { - gpio-line-names = - "[I2C3_SDA]", /* HSEC Pin 38: ISP1_SDA */ - "[I2C3_SCL]", /* HSEC Pin 36: ISP1_SCL */ - "", "NC", "NC", "NC", "", ""; - }; - - gpio12: gpio@f7028000 { - gpio-line-names = "[BT_PCM_XFS]", "[BT_PCM_DI]", - "[BT_PCM_DO]", - "NC", "NC", "NC", "NC", - "GPIO-F"; /* LSEC Pin 28: BL_PWM_GPIO12_7 */ - }; - - gpio13: gpio@f7029000 { - gpio-line-names = "[UART0_RX]", "[UART0_TX]", - "[BT_UART1_CTS]", "[BT_UART1_RTS]", - "[BT_UART1_RX]", "[BT_UART1_TX]", - "[UART0_CTS]", /* LSEC Pin 3: UART2_CTS_N */ - "[UART0_RTS]"; /* LSEC Pin 9: UART2_RTS_N */ - }; - - gpio14: gpio@f702a000 { - gpio-line-names = - "[UART0_RxD]", /* LSEC Pin 7: UART2_RX */ - "[UART0_TxD]", /* LSEC Pin 5: UART2_TX */ - "[I2C0_SCL]", /* LSEC Pin 15: I2C0_SCL */ - "[I2C0_SDA]", /* LSEC Pin 17: I2C0_SDA */ - "[I2C1_SCL]", /* LSEC Pin 19: I2C1_SCL */ - "[I2C1_SDA]", /* LSEC Pin 21: I2C1_SDA */ - "[I2C2_SCL]", "[I2C2_SDA]"; - }; - - gpio15: gpio@f702b000 { - gpio-line-names = "", "", "", "", "", "", "NC", ""; - }; - - /* GPIO blocks 16 thru 19 do not appear to be routed to pins */ - - dwmmc_0: dwmmc0@f723d000 { - cap-mmc-highspeed; - non-removable; - bus-width = <0x8>; - vmmc-supply = <&ldo19>; - }; - - dwmmc_1: dwmmc1@f723e000 { - card-detect-delay = <200>; - cap-sd-highspeed; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - vqmmc-supply = <&ldo7>; - vmmc-supply = <&ldo10>; - bus-width = <0x4>; - disable-wp; - cd-gpios = <&gpio1 0 1>; - }; - - dwmmc_2: dwmmc2@f723f000 { - bus-width = <0x4>; - non-removable; - cap-power-off-card; - vmmc-supply = <®_vdd_3v3>; - mmc-pwrseq = <&wl1835_pwrseq>; - - #address-cells = <0x1>; - #size-cells = <0x0>; - wlcore: wlcore@2 { - compatible = "ti,wl1835"; - reg = <2>; /* sdio func num */ - /* WL_IRQ, WL_HOST_WAKE_GPIO1_3 */ - interrupt-parent = <&gpio1>; - interrupts = <3 IRQ_TYPE_EDGE_RISING>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - user_led1 { - label = "green:user1"; - gpios = <&gpio4 0 0>; /* <&gpio_user_led_1>; */ - linux,default-trigger = "heartbeat"; - }; - - user_led2 { - label = "green:user2"; - gpios = <&gpio4 1 0>; /* <&gpio_user_led_2>; */ - linux,default-trigger = "mmc0"; - }; - - user_led3 { - label = "green:user3"; - gpios = <&gpio4 2 0>; /* <&gpio_user_led_3>; */ - linux,default-trigger = "mmc1"; - }; - - user_led4 { - label = "green:user4"; - gpios = <&gpio4 3 0>; /* <&gpio_user_led_4>; */ - panic-indicator; - linux,default-trigger = "none"; - }; - - wlan_active_led { - label = "yellow:wlan"; - gpios = <&gpio3 5 0>; /* <&gpio_wlan_active_led>; */ - linux,default-trigger = "phy0tx"; - default-state = "off"; - }; - - bt_active_led { - label = "blue:bt"; - gpios = <&gpio4 7 0>; /* <&gpio_bt_active_led>; */ - linux,default-trigger = "hci0-power"; - default-state = "off"; - }; - }; - - pmic: pmic@f8000000 { - compatible = "hisilicon,hi655x-pmic"; - reg = <0x0 0xf8000000 0x0 0x1000>; - #clock-cells = <0>; - interrupt-controller; - #interrupt-cells = <2>; - pmic-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; - - regulators { - ldo2: LDO2 { - regulator-name = "LDO2_2V8"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <3200000>; - regulator-enable-ramp-delay = <120>; - }; - - ldo7: LDO7 { - regulator-name = "LDO7_SDIO"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <120>; - }; - - ldo10: LDO10 { - regulator-name = "LDO10_2V85"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3000000>; - regulator-enable-ramp-delay = <360>; - }; - - ldo13: LDO13 { - regulator-name = "LDO13_1V8"; - regulator-min-microvolt = <1600000>; - regulator-max-microvolt = <1950000>; - regulator-enable-ramp-delay = <120>; - }; - - ldo14: LDO14 { - regulator-name = "LDO14_2V8"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <3200000>; - regulator-enable-ramp-delay = <120>; - }; - - ldo15: LDO15 { - regulator-name = "LDO15_1V8"; - regulator-min-microvolt = <1600000>; - regulator-max-microvolt = <1950000>; - regulator-boot-on; - regulator-always-on; - regulator-enable-ramp-delay = <120>; - }; - - ldo17: LDO17 { - regulator-name = "LDO17_2V5"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <3200000>; - regulator-enable-ramp-delay = <120>; - }; - - ldo19: LDO19 { - regulator-name = "LDO19_3V0"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3000000>; - regulator-enable-ramp-delay = <360>; - }; - - ldo21: LDO21 { - regulator-name = "LDO21_1V8"; - regulator-min-microvolt = <1650000>; - regulator-max-microvolt = <2000000>; - regulator-always-on; - regulator-enable-ramp-delay = <120>; - }; - - ldo22: LDO22 { - regulator-name = "LDO22_1V2"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1200000>; - regulator-boot-on; - regulator-always-on; - regulator-enable-ramp-delay = <120>; - }; - }; - }; - - firmware { - optee { - compatible = "linaro,optee-tz"; - method = "smc"; - }; - }; - - sound_card { - compatible = "audio-graph-card"; - dais = <&i2s0_port0>; - }; -}; - -&uart2 { - label = "LS-UART0"; -}; -&uart3 { - label = "LS-UART1"; -}; - -&ade { - status = "ok"; -}; - -&dsi { - status = "ok"; - - ports { - /* 1 for output port */ - port@1 { - reg = <1>; - - dsi_out0: endpoint@0 { - remote-endpoint = <&adv7533_in>; - }; - }; - }; -}; - -&i2c2 { - #address-cells = <1>; - #size-cells = <0>; - status = "ok"; - - adv7533: adv7533@39 { - compatible = "adi,adv7533"; - reg = <0x39>; - interrupt-parent = <&gpio1>; - interrupts = <1 2>; - pd-gpio = <&gpio0 4 0>; - adi,dsi-lanes = <4>; - #sound-dai-cells = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - adv7533_in: endpoint { - remote-endpoint = <&dsi_out0>; - }; - }; - port@2 { - reg = <2>; - codec_endpoint: endpoint { - remote-endpoint = <&i2s0_cpu_endpoint>; - }; - }; - }; - }; -}; - -&i2s0 { - - ports { - i2s0_port0: port@0 { - i2s0_cpu_endpoint: endpoint { - remote-endpoint = <&codec_endpoint>; - dai-format = "i2s"; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/hisilicon/hi6220.dtsi b/sys/gnu/dts/arm64/hisilicon/hi6220.dtsi deleted file mode 100644 index 2072b637b5a..00000000000 --- a/sys/gnu/dts/arm64/hisilicon/hi6220.dtsi +++ /dev/null @@ -1,1065 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * dts file for Hisilicon Hi6220 SoC - * - * Copyright (C) 2015, Hisilicon Ltd. - */ - -#include -#include -#include -#include -#include - -/ { - compatible = "hisilicon,hi6220"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu-map { - cluster0 { - core0 { - cpu = <&cpu0>; - }; - core1 { - cpu = <&cpu1>; - }; - core2 { - cpu = <&cpu2>; - }; - core3 { - cpu = <&cpu3>; - }; - }; - cluster1 { - core0 { - cpu = <&cpu4>; - }; - core1 { - cpu = <&cpu5>; - }; - core2 { - cpu = <&cpu6>; - }; - core3 { - cpu = <&cpu7>; - }; - }; - }; - - idle-states { - entry-method = "psci"; - - CPU_SLEEP: cpu-sleep { - compatible = "arm,idle-state"; - local-timer-stop; - arm,psci-suspend-param = <0x0010000>; - entry-latency-us = <700>; - exit-latency-us = <250>; - min-residency-us = <1000>; - }; - - CLUSTER_SLEEP: cluster-sleep { - compatible = "arm,idle-state"; - local-timer-stop; - arm,psci-suspend-param = <0x1010000>; - entry-latency-us = <1000>; - exit-latency-us = <700>; - min-residency-us = <2700>; - wakeup-latency-us = <1500>; - }; - }; - - cpu0: cpu@0 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <0x0 0x0>; - enable-method = "psci"; - next-level-cache = <&CLUSTER0_L2>; - clocks = <&stub_clock 0>; - operating-points-v2 = <&cpu_opp_table>; - cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; - #cooling-cells = <2>; /* min followed by max */ - dynamic-power-coefficient = <311>; - }; - - cpu1: cpu@1 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <0x0 0x1>; - enable-method = "psci"; - next-level-cache = <&CLUSTER0_L2>; - clocks = <&stub_clock 0>; - operating-points-v2 = <&cpu_opp_table>; - cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; - #cooling-cells = <2>; /* min followed by max */ - dynamic-power-coefficient = <311>; - }; - - cpu2: cpu@2 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <0x0 0x2>; - enable-method = "psci"; - next-level-cache = <&CLUSTER0_L2>; - clocks = <&stub_clock 0>; - operating-points-v2 = <&cpu_opp_table>; - cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; - #cooling-cells = <2>; /* min followed by max */ - dynamic-power-coefficient = <311>; - }; - - cpu3: cpu@3 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <0x0 0x3>; - enable-method = "psci"; - next-level-cache = <&CLUSTER0_L2>; - clocks = <&stub_clock 0>; - operating-points-v2 = <&cpu_opp_table>; - cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; - #cooling-cells = <2>; /* min followed by max */ - dynamic-power-coefficient = <311>; - }; - - cpu4: cpu@100 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <0x0 0x100>; - enable-method = "psci"; - next-level-cache = <&CLUSTER1_L2>; - clocks = <&stub_clock 0>; - operating-points-v2 = <&cpu_opp_table>; - cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; - #cooling-cells = <2>; /* min followed by max */ - dynamic-power-coefficient = <311>; - }; - - cpu5: cpu@101 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <0x0 0x101>; - enable-method = "psci"; - next-level-cache = <&CLUSTER1_L2>; - clocks = <&stub_clock 0>; - operating-points-v2 = <&cpu_opp_table>; - cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; - #cooling-cells = <2>; /* min followed by max */ - dynamic-power-coefficient = <311>; - }; - - cpu6: cpu@102 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <0x0 0x102>; - enable-method = "psci"; - next-level-cache = <&CLUSTER1_L2>; - clocks = <&stub_clock 0>; - operating-points-v2 = <&cpu_opp_table>; - cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; - #cooling-cells = <2>; /* min followed by max */ - dynamic-power-coefficient = <311>; - }; - - cpu7: cpu@103 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <0x0 0x103>; - enable-method = "psci"; - next-level-cache = <&CLUSTER1_L2>; - clocks = <&stub_clock 0>; - operating-points-v2 = <&cpu_opp_table>; - cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; - #cooling-cells = <2>; /* min followed by max */ - dynamic-power-coefficient = <311>; - }; - - CLUSTER0_L2: l2-cache0 { - compatible = "cache"; - }; - - CLUSTER1_L2: l2-cache1 { - compatible = "cache"; - }; - }; - - cpu_opp_table: cpu_opp_table { - compatible = "operating-points-v2"; - opp-shared; - - opp00 { - opp-hz = /bits/ 64 <208000000>; - opp-microvolt = <1040000>; - clock-latency-ns = <500000>; - }; - opp01 { - opp-hz = /bits/ 64 <432000000>; - opp-microvolt = <1040000>; - clock-latency-ns = <500000>; - }; - opp02 { - opp-hz = /bits/ 64 <729000000>; - opp-microvolt = <1090000>; - clock-latency-ns = <500000>; - }; - opp03 { - opp-hz = /bits/ 64 <960000000>; - opp-microvolt = <1180000>; - clock-latency-ns = <500000>; - }; - opp04 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <1330000>; - clock-latency-ns = <500000>; - }; - }; - - gic: interrupt-controller@f6801000 { - compatible = "arm,gic-400"; - reg = <0x0 0xf6801000 0 0x1000>, /* GICD */ - <0x0 0xf6802000 0 0x2000>, /* GICC */ - <0x0 0xf6804000 0 0x2000>, /* GICH */ - <0x0 0xf6806000 0 0x2000>; /* GICV */ - #address-cells = <0>; - #interrupt-cells = <3>; - interrupt-controller; - interrupts = ; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupt-parent = <&gic>; - interrupts = , - , - , - ; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - sram: sram@fff80000 { - compatible = "hisilicon,hi6220-sramctrl", "syscon"; - reg = <0x0 0xfff80000 0x0 0x12000>; - }; - - ao_ctrl: ao_ctrl@f7800000 { - compatible = "hisilicon,hi6220-aoctrl", "syscon"; - reg = <0x0 0xf7800000 0x0 0x2000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - sys_ctrl: sys_ctrl@f7030000 { - compatible = "hisilicon,hi6220-sysctrl", "syscon"; - reg = <0x0 0xf7030000 0x0 0x2000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - media_ctrl: media_ctrl@f4410000 { - compatible = "hisilicon,hi6220-mediactrl", "syscon"; - reg = <0x0 0xf4410000 0x0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - pm_ctrl: pm_ctrl@f7032000 { - compatible = "hisilicon,hi6220-pmctrl", "syscon"; - reg = <0x0 0xf7032000 0x0 0x1000>; - #clock-cells = <1>; - }; - - acpu_sctrl: acpu_sctrl@f6504000 { - compatible = "hisilicon,hi6220-acpu-sctrl", "syscon"; - reg = <0x0 0xf6504000 0x0 0x1000>; - #clock-cells = <1>; - }; - - medianoc_ade: medianoc_ade@f4520000 { - compatible = "syscon"; - reg = <0x0 0xf4520000 0x0 0x4000>; - }; - - stub_clock: stub_clock { - compatible = "hisilicon,hi6220-stub-clk"; - hisilicon,hi6220-clk-sram = <&sram>; - #clock-cells = <1>; - mbox-names = "mbox-tx"; - mboxes = <&mailbox 1 0 11>; - }; - - uart0: uart@f8015000 { /* console */ - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0 0xf8015000 0x0 0x1000>; - interrupts = ; - clocks = <&ao_ctrl HI6220_UART0_PCLK>, - <&ao_ctrl HI6220_UART0_PCLK>; - clock-names = "uartclk", "apb_pclk"; - }; - - uart1: uart@f7111000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0 0xf7111000 0x0 0x1000>; - interrupts = ; - clocks = <&sys_ctrl HI6220_UART1_PCLK>, - <&sys_ctrl HI6220_UART1_PCLK>; - clock-names = "uartclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func1 &uart1_cfg_func2>; - dmas = <&dma0 8 &dma0 9>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart2: uart@f7112000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0 0xf7112000 0x0 0x1000>; - interrupts = ; - clocks = <&sys_ctrl HI6220_UART2_PCLK>, - <&sys_ctrl HI6220_UART2_PCLK>; - clock-names = "uartclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>; - status = "disabled"; - }; - - uart3: uart@f7113000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0 0xf7113000 0x0 0x1000>; - interrupts = ; - clocks = <&sys_ctrl HI6220_UART3_PCLK>, - <&sys_ctrl HI6220_UART3_PCLK>; - clock-names = "uartclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>; - status = "disabled"; - }; - - uart4: uart@f7114000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0 0xf7114000 0x0 0x1000>; - interrupts = ; - clocks = <&sys_ctrl HI6220_UART4_PCLK>, - <&sys_ctrl HI6220_UART4_PCLK>; - clock-names = "uartclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>; - status = "disabled"; - }; - - dma0: dma@f7370000 { - compatible = "hisilicon,k3-dma-1.0"; - reg = <0x0 0xf7370000 0x0 0x1000>; - #dma-cells = <1>; - dma-channels = <15>; - dma-requests = <32>; - interrupts = <0 84 4>; - clocks = <&sys_ctrl HI6220_EDMAC_ACLK>; - dma-no-cci; - dma-type = "hi6220_dma"; - status = "ok"; - }; - - dual_timer0: timer@f8008000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x0 0xf8008000 0x0 0x1000>; - interrupts = , - ; - clocks = <&ao_ctrl HI6220_TIMER0_PCLK>, - <&ao_ctrl HI6220_TIMER0_PCLK>, - <&ao_ctrl HI6220_TIMER0_PCLK>; - clock-names = "timer1", "timer2", "apb_pclk"; - }; - - rtc0: rtc@f8003000 { - compatible = "arm,pl031", "arm,primecell"; - reg = <0x0 0xf8003000 0x0 0x1000>; - interrupts = <0 12 4>; - clocks = <&ao_ctrl HI6220_RTC0_PCLK>; - clock-names = "apb_pclk"; - }; - - rtc1: rtc@f8004000 { - compatible = "arm,pl031", "arm,primecell"; - reg = <0x0 0xf8004000 0x0 0x1000>; - interrupts = <0 8 4>; - clocks = <&ao_ctrl HI6220_RTC1_PCLK>; - clock-names = "apb_pclk"; - }; - - pmx0: pinmux@f7010000 { - compatible = "pinctrl-single"; - reg = <0x0 0xf7010000 0x0 0x27c>; - #address-cells = <1>; - #size-cells = <1>; - #pinctrl-cells = <1>; - #gpio-range-cells = <3>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <7>; - pinctrl-single,gpio-range = < - &range 80 8 MUX_M0 /* gpio 3: [0..7] */ - &range 88 8 MUX_M0 /* gpio 4: [0..7] */ - &range 96 8 MUX_M0 /* gpio 5: [0..7] */ - &range 104 8 MUX_M0 /* gpio 6: [0..7] */ - &range 112 8 MUX_M0 /* gpio 7: [0..7] */ - &range 120 2 MUX_M0 /* gpio 8: [0..1] */ - &range 2 6 MUX_M1 /* gpio 8: [2..7] */ - &range 8 8 MUX_M1 /* gpio 9: [0..7] */ - &range 0 1 MUX_M1 /* gpio 10: [0] */ - &range 16 7 MUX_M1 /* gpio 10: [1..7] */ - &range 23 3 MUX_M1 /* gpio 11: [0..2] */ - &range 28 5 MUX_M1 /* gpio 11: [3..7] */ - &range 33 3 MUX_M1 /* gpio 12: [0..2] */ - &range 43 5 MUX_M1 /* gpio 12: [3..7] */ - &range 48 8 MUX_M1 /* gpio 13: [0..7] */ - &range 56 8 MUX_M1 /* gpio 14: [0..7] */ - &range 74 6 MUX_M1 /* gpio 15: [0..5] */ - &range 122 1 MUX_M1 /* gpio 15: [6] */ - &range 126 1 MUX_M1 /* gpio 15: [7] */ - &range 127 8 MUX_M1 /* gpio 16: [0..7] */ - &range 135 8 MUX_M1 /* gpio 17: [0..7] */ - &range 143 8 MUX_M1 /* gpio 18: [0..7] */ - &range 151 8 MUX_M1 /* gpio 19: [0..7] */ - >; - range: gpio-range { - #pinctrl-single,gpio-range-cells = <3>; - }; - }; - - pmx1: pinmux@f7010800 { - compatible = "pinconf-single"; - reg = <0x0 0xf7010800 0x0 0x28c>; - #address-cells = <1>; - #size-cells = <1>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - }; - - pmx2: pinmux@f8001800 { - compatible = "pinconf-single"; - reg = <0x0 0xf8001800 0x0 0x78>; - #address-cells = <1>; - #size-cells = <1>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - }; - - gpio0: gpio@f8011000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xf8011000 0x0 0x1000>; - interrupts = <0 52 0x4>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&ao_ctrl 2>; - clock-names = "apb_pclk"; - }; - - gpio1: gpio@f8012000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xf8012000 0x0 0x1000>; - interrupts = <0 53 0x4>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&ao_ctrl 2>; - clock-names = "apb_pclk"; - }; - - gpio2: gpio@f8013000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xf8013000 0x0 0x1000>; - interrupts = <0 54 0x4>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&ao_ctrl 2>; - clock-names = "apb_pclk"; - }; - - gpio3: gpio@f8014000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xf8014000 0x0 0x1000>; - interrupts = <0 55 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx0 0 80 8>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&ao_ctrl 2>; - clock-names = "apb_pclk"; - }; - - gpio4: gpio@f7020000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xf7020000 0x0 0x1000>; - interrupts = <0 56 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx0 0 88 8>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&ao_ctrl 2>; - clock-names = "apb_pclk"; - }; - - gpio5: gpio@f7021000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xf7021000 0x0 0x1000>; - interrupts = <0 57 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx0 0 96 8>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&ao_ctrl 2>; - clock-names = "apb_pclk"; - }; - - gpio6: gpio@f7022000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xf7022000 0x0 0x1000>; - interrupts = <0 58 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx0 0 104 8>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&ao_ctrl 2>; - clock-names = "apb_pclk"; - }; - - gpio7: gpio@f7023000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xf7023000 0x0 0x1000>; - interrupts = <0 59 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx0 0 112 8>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&ao_ctrl 2>; - clock-names = "apb_pclk"; - }; - - gpio8: gpio@f7024000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xf7024000 0x0 0x1000>; - interrupts = <0 60 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx0 0 120 2 &pmx0 2 2 6>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&ao_ctrl 2>; - clock-names = "apb_pclk"; - }; - - gpio9: gpio@f7025000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xf7025000 0x0 0x1000>; - interrupts = <0 61 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx0 0 8 8>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&ao_ctrl 2>; - clock-names = "apb_pclk"; - }; - - gpio10: gpio@f7026000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xf7026000 0x0 0x1000>; - interrupts = <0 62 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx0 0 0 1 &pmx0 1 16 7>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&ao_ctrl 2>; - clock-names = "apb_pclk"; - }; - - gpio11: gpio@f7027000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xf7027000 0x0 0x1000>; - interrupts = <0 63 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx0 0 23 3 &pmx0 3 28 5>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&ao_ctrl 2>; - clock-names = "apb_pclk"; - }; - - gpio12: gpio@f7028000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xf7028000 0x0 0x1000>; - interrupts = <0 64 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx0 0 33 3 &pmx0 3 43 5>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&ao_ctrl 2>; - clock-names = "apb_pclk"; - }; - - gpio13: gpio@f7029000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xf7029000 0x0 0x1000>; - interrupts = <0 65 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx0 0 48 8>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&ao_ctrl 2>; - clock-names = "apb_pclk"; - }; - - gpio14: gpio@f702a000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xf702a000 0x0 0x1000>; - interrupts = <0 66 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx0 0 56 8>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&ao_ctrl 2>; - clock-names = "apb_pclk"; - }; - - gpio15: gpio@f702b000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xf702b000 0x0 0x1000>; - interrupts = <0 67 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = < - &pmx0 0 74 6 - &pmx0 6 122 1 - &pmx0 7 126 1 - >; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&ao_ctrl 2>; - clock-names = "apb_pclk"; - }; - - gpio16: gpio@f702c000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xf702c000 0x0 0x1000>; - interrupts = <0 68 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx0 0 127 8>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&ao_ctrl 2>; - clock-names = "apb_pclk"; - }; - - gpio17: gpio@f702d000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xf702d000 0x0 0x1000>; - interrupts = <0 69 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx0 0 135 8>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&ao_ctrl 2>; - clock-names = "apb_pclk"; - }; - - gpio18: gpio@f702e000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xf702e000 0x0 0x1000>; - interrupts = <0 70 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx0 0 143 8>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&ao_ctrl 2>; - clock-names = "apb_pclk"; - }; - - gpio19: gpio@f702f000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xf702f000 0x0 0x1000>; - interrupts = <0 71 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx0 0 151 8>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&ao_ctrl 2>; - clock-names = "apb_pclk"; - }; - - spi0: spi@f7106000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x0 0xf7106000 0x0 0x1000>; - interrupts = <0 50 4>; - bus-id = <0>; - enable-dma = <0>; - clocks = <&sys_ctrl HI6220_SPI_CLK>; - clock-names = "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pmx_func &spi0_cfg_func>; - num-cs = <1>; - cs-gpios = <&gpio6 2 0>; - status = "disabled"; - }; - - i2c0: i2c@f7100000 { - compatible = "snps,designware-i2c"; - reg = <0x0 0xf7100000 0x0 0x1000>; - interrupts = <0 44 4>; - clocks = <&sys_ctrl HI6220_I2C0_CLK>; - i2c-sda-hold-time-ns = <300>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>; - status = "disabled"; - }; - - i2c1: i2c@f7101000 { - compatible = "snps,designware-i2c"; - reg = <0x0 0xf7101000 0x0 0x1000>; - clocks = <&sys_ctrl HI6220_I2C1_CLK>; - interrupts = <0 45 4>; - i2c-sda-hold-time-ns = <300>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>; - status = "disabled"; - }; - - i2c2: i2c@f7102000 { - compatible = "snps,designware-i2c"; - reg = <0x0 0xf7102000 0x0 0x1000>; - clocks = <&sys_ctrl HI6220_I2C2_CLK>; - interrupts = <0 46 4>; - i2c-sda-hold-time-ns = <300>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pmx_func &i2c2_cfg_func>; - status = "disabled"; - }; - - usb_phy: usbphy { - compatible = "hisilicon,hi6220-usb-phy"; - #phy-cells = <0>; - phy-supply = <®_5v_hub>; - hisilicon,peripheral-syscon = <&sys_ctrl>; - }; - - usb: usb@f72c0000 { - compatible = "hisilicon,hi6220-usb"; - reg = <0x0 0xf72c0000 0x0 0x40000>; - phys = <&usb_phy>; - phy-names = "usb2-phy"; - clocks = <&sys_ctrl HI6220_USBOTG_HCLK>; - clock-names = "otg"; - dr_mode = "otg"; - g-rx-fifo-size = <512>; - g-np-tx-fifo-size = <128>; - g-tx-fifo-size = <128 128 128 128 128 128 128 128 - 16 16 16 16 16 16 16>; - interrupts = <0 77 0x4>; - }; - - mailbox: mailbox@f7510000 { - compatible = "hisilicon,hi6220-mbox"; - reg = <0x0 0xf7510000 0x0 0x1000>, /* IPC_S */ - <0x0 0x06dff800 0x0 0x0800>; /* Mailbox buffer */ - interrupts = ; - #mbox-cells = <3>; - }; - - dwmmc_0: dwmmc0@f723d000 { - compatible = "hisilicon,hi6220-dw-mshc"; - reg = <0x0 0xf723d000 0x0 0x1000>; - interrupts = <0x0 0x48 0x4>; - clocks = <&sys_ctrl 2>, <&sys_ctrl 1>; - clock-names = "ciu", "biu"; - resets = <&sys_ctrl PERIPH_RSTDIS0_MMC0>; - reset-names = "reset"; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_pmx_func &emmc_clk_cfg_func - &emmc_cfg_func &emmc_rst_cfg_func>; - }; - - dwmmc_1: dwmmc1@f723e000 { - compatible = "hisilicon,hi6220-dw-mshc"; - hisilicon,peripheral-syscon = <&ao_ctrl>; - reg = <0x0 0xf723e000 0x0 0x1000>; - interrupts = <0x0 0x49 0x4>; - #address-cells = <0x1>; - #size-cells = <0x0>; - clocks = <&sys_ctrl 4>, <&sys_ctrl 3>; - clock-names = "ciu", "biu"; - resets = <&sys_ctrl PERIPH_RSTDIS0_MMC1>; - reset-names = "reset"; - pinctrl-names = "default", "idle"; - pinctrl-0 = <&sd_pmx_func &sd_clk_cfg_func &sd_cfg_func>; - pinctrl-1 = <&sd_pmx_idle &sd_clk_cfg_idle &sd_cfg_idle>; - }; - - dwmmc_2: dwmmc2@f723f000 { - compatible = "hisilicon,hi6220-dw-mshc"; - reg = <0x0 0xf723f000 0x0 0x1000>; - interrupts = <0x0 0x4a 0x4>; - clocks = <&sys_ctrl HI6220_MMC2_CIUCLK>, <&sys_ctrl HI6220_MMC2_CLK>; - clock-names = "ciu", "biu"; - resets = <&sys_ctrl PERIPH_RSTDIS0_MMC2>; - reset-names = "reset"; - pinctrl-names = "default", "idle"; - pinctrl-0 = <&sdio_pmx_func &sdio_clk_cfg_func &sdio_cfg_func>; - pinctrl-1 = <&sdio_pmx_idle &sdio_clk_cfg_idle &sdio_cfg_idle>; - }; - - watchdog0: watchdog@f8005000 { - compatible = "arm,sp805-wdt", "arm,primecell"; - reg = <0x0 0xf8005000 0x0 0x1000>; - interrupts = ; - clocks = <&ao_ctrl HI6220_WDT0_PCLK>; - clock-names = "apb_pclk"; - }; - - tsensor: tsensor@0,f7030700 { - compatible = "hisilicon,tsensor"; - reg = <0x0 0xf7030700 0x0 0x1000>; - interrupts = ; - clocks = <&sys_ctrl 22>; - clock-names = "thermal_clk"; - #thermal-sensor-cells = <1>; - }; - - i2s0: i2s@f7118000{ - compatible = "hisilicon,hi6210-i2s"; - reg = <0x0 0xf7118000 0x0 0x8000>; /* i2s unit */ - interrupts = ; /* 155 "DigACodec_intr"-32 */ - clocks = <&sys_ctrl HI6220_DACODEC_PCLK>, - <&sys_ctrl HI6220_BBPPLL0_DIV>; - clock-names = "dacodec", "i2s-base"; - dmas = <&dma0 15 &dma0 14>; - dma-names = "rx", "tx"; - hisilicon,sysctrl-syscon = <&sys_ctrl>; - #sound-dai-cells = <1>; - }; - - thermal-zones { - - cls0: cls0 { - polling-delay = <1000>; - polling-delay-passive = <100>; - sustainable-power = <3326>; - - /* sensor ID */ - thermal-sensors = <&tsensor 2>; - - trips { - threshold: trip-point@0 { - temperature = <65000>; - hysteresis = <0>; - type = "passive"; - }; - - target: trip-point@1 { - temperature = <75000>; - hysteresis = <0>; - type = "passive"; - }; - }; - - cooling-maps { - map0 { - trip = <&target>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - }; - - ade: ade@f4100000 { - compatible = "hisilicon,hi6220-ade"; - reg = <0x0 0xf4100000 0x0 0x7800>; - reg-names = "ade_base"; - hisilicon,noc-syscon = <&medianoc_ade>; - resets = <&media_ctrl MEDIA_ADE>; - interrupts = <0 115 4>; /* ldi interrupt */ - - clocks = <&media_ctrl HI6220_ADE_CORE>, - <&media_ctrl HI6220_CODEC_JPEG>, - <&media_ctrl HI6220_ADE_PIX_SRC>; - /*clock name*/ - clock-names = "clk_ade_core", - "clk_codec_jpeg", - "clk_ade_pix"; - - assigned-clocks = <&media_ctrl HI6220_ADE_CORE>, - <&media_ctrl HI6220_CODEC_JPEG>; - assigned-clock-rates = <360000000>, <288000000>; - dma-coherent; - status = "disabled"; - - port { - ade_out: endpoint { - remote-endpoint = <&dsi_in>; - }; - }; - }; - - dsi: dsi@f4107800 { - compatible = "hisilicon,hi6220-dsi"; - reg = <0x0 0xf4107800 0x0 0x100>; - clocks = <&media_ctrl HI6220_DSI_PCLK>; - clock-names = "pclk"; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - /* 0 for input port */ - port@0 { - reg = <0>; - dsi_in: endpoint { - remote-endpoint = <&ade_out>; - }; - }; - }; - }; - - debug@f6590000 { - compatible = "arm,coresight-cpu-debug","arm,primecell"; - reg = <0 0xf6590000 0 0x1000>; - clocks = <&sys_ctrl HI6220_DAPB_CLK>; - clock-names = "apb_pclk"; - cpu = <&cpu0>; - }; - - debug@f6592000 { - compatible = "arm,coresight-cpu-debug","arm,primecell"; - reg = <0 0xf6592000 0 0x1000>; - clocks = <&sys_ctrl HI6220_DAPB_CLK>; - clock-names = "apb_pclk"; - cpu = <&cpu1>; - }; - - debug@f6594000 { - compatible = "arm,coresight-cpu-debug","arm,primecell"; - reg = <0 0xf6594000 0 0x1000>; - clocks = <&sys_ctrl HI6220_DAPB_CLK>; - clock-names = "apb_pclk"; - cpu = <&cpu2>; - }; - - debug@f6596000 { - compatible = "arm,coresight-cpu-debug","arm,primecell"; - reg = <0 0xf6596000 0 0x1000>; - clocks = <&sys_ctrl HI6220_DAPB_CLK>; - clock-names = "apb_pclk"; - cpu = <&cpu3>; - }; - - debug@f65d0000 { - compatible = "arm,coresight-cpu-debug","arm,primecell"; - reg = <0 0xf65d0000 0 0x1000>; - clocks = <&sys_ctrl HI6220_DAPB_CLK>; - clock-names = "apb_pclk"; - cpu = <&cpu4>; - }; - - debug@f65d2000 { - compatible = "arm,coresight-cpu-debug","arm,primecell"; - reg = <0 0xf65d2000 0 0x1000>; - clocks = <&sys_ctrl HI6220_DAPB_CLK>; - clock-names = "apb_pclk"; - cpu = <&cpu5>; - }; - - debug@f65d4000 { - compatible = "arm,coresight-cpu-debug","arm,primecell"; - reg = <0 0xf65d4000 0 0x1000>; - clocks = <&sys_ctrl HI6220_DAPB_CLK>; - clock-names = "apb_pclk"; - cpu = <&cpu6>; - }; - - debug@f65d6000 { - compatible = "arm,coresight-cpu-debug","arm,primecell"; - reg = <0 0xf65d6000 0 0x1000>; - clocks = <&sys_ctrl HI6220_DAPB_CLK>; - clock-names = "apb_pclk"; - cpu = <&cpu7>; - }; - - mali: gpu@f4080000 { - compatible = "hisilicon,hi6220-mali", "arm,mali-450"; - reg = <0x0 0xf4080000 0x0 0x00040000>; - interrupt-parent = <&gic>; - interrupts = , - , - , - , - , - , - , - , - , - , - ; - - interrupt-names = "gp", - "gpmmu", - "pp", - "pp0", - "ppmmu0", - "pp1", - "ppmmu1", - "pp2", - "ppmmu2", - "pp3", - "ppmmu3"; - clocks = <&media_ctrl HI6220_G3D_CLK>, - <&media_ctrl HI6220_G3D_PCLK>; - clock-names = "core", "bus"; - assigned-clocks = <&media_ctrl HI6220_G3D_CLK>, - <&media_ctrl HI6220_G3D_PCLK>; - assigned-clock-rates = <500000000>, <144000000>; - reset-names = "ao_g3d", "media_g3d"; - resets = <&ao_ctrl AO_G3D>, <&media_ctrl MEDIA_G3D>; - }; - }; -}; - -#include "hi6220-coresight.dtsi" diff --git a/sys/gnu/dts/arm64/hisilicon/hikey-pinctrl.dtsi b/sys/gnu/dts/arm64/hisilicon/hikey-pinctrl.dtsi deleted file mode 100644 index e7d22619a4c..00000000000 --- a/sys/gnu/dts/arm64/hisilicon/hikey-pinctrl.dtsi +++ /dev/null @@ -1,706 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * pinctrl dts fils for Hislicon HiKey development board - * - */ -#include - -/ { - soc { - pmx0: pinmux@f7010000 { - pinctrl-names = "default"; - pinctrl-0 = < - &boot_sel_pmx_func - &hkadc_ssi_pmx_func - &codec_clk_pmx_func - &pwm_in_pmx_func - &bl_pwm_pmx_func - >; - - boot_sel_pmx_func: boot_sel_pmx_func { - pinctrl-single,pins = < - 0x0 MUX_M0 /* BOOT_SEL (IOMG000) */ - >; - }; - - emmc_pmx_func: emmc_pmx_func { - pinctrl-single,pins = < - 0x100 MUX_M0 /* EMMC_CLK (IOMG064) */ - 0x104 MUX_M0 /* EMMC_CMD (IOMG065) */ - 0x108 MUX_M0 /* EMMC_DATA0 (IOMG066) */ - 0x10c MUX_M0 /* EMMC_DATA1 (IOMG067) */ - 0x110 MUX_M0 /* EMMC_DATA2 (IOMG068) */ - 0x114 MUX_M0 /* EMMC_DATA3 (IOMG069) */ - 0x118 MUX_M0 /* EMMC_DATA4 (IOMG070) */ - 0x11c MUX_M0 /* EMMC_DATA5 (IOMG071) */ - 0x120 MUX_M0 /* EMMC_DATA6 (IOMG072) */ - 0x124 MUX_M0 /* EMMC_DATA7 (IOMG073) */ - >; - }; - - sd_pmx_func: sd_pmx_func { - pinctrl-single,pins = < - 0xc MUX_M0 /* SD_CLK (IOMG003) */ - 0x10 MUX_M0 /* SD_CMD (IOMG004) */ - 0x14 MUX_M0 /* SD_DATA0 (IOMG005) */ - 0x18 MUX_M0 /* SD_DATA1 (IOMG006) */ - 0x1c MUX_M0 /* SD_DATA2 (IOMG007) */ - 0x20 MUX_M0 /* SD_DATA3 (IOMG008) */ - >; - }; - sd_pmx_idle: sd_pmx_idle { - pinctrl-single,pins = < - 0xc MUX_M1 /* SD_CLK (IOMG003) */ - 0x10 MUX_M1 /* SD_CMD (IOMG004) */ - 0x14 MUX_M1 /* SD_DATA0 (IOMG005) */ - 0x18 MUX_M1 /* SD_DATA1 (IOMG006) */ - 0x1c MUX_M1 /* SD_DATA2 (IOMG007) */ - 0x20 MUX_M1 /* SD_DATA3 (IOMG008) */ - >; - }; - - sdio_pmx_func: sdio_pmx_func { - pinctrl-single,pins = < - 0x128 MUX_M0 /* SDIO_CLK (IOMG074) */ - 0x12c MUX_M0 /* SDIO_CMD (IOMG075) */ - 0x130 MUX_M0 /* SDIO_DATA0 (IOMG076) */ - 0x134 MUX_M0 /* SDIO_DATA1 (IOMG077) */ - 0x138 MUX_M0 /* SDIO_DATA2 (IOMG078) */ - 0x13c MUX_M0 /* SDIO_DATA3 (IOMG079) */ - >; - }; - sdio_pmx_idle: sdio_pmx_idle { - pinctrl-single,pins = < - 0x128 MUX_M1 /* SDIO_CLK (IOMG074) */ - 0x12c MUX_M1 /* SDIO_CMD (IOMG075) */ - 0x130 MUX_M1 /* SDIO_DATA0 (IOMG076) */ - 0x134 MUX_M1 /* SDIO_DATA1 (IOMG077) */ - 0x138 MUX_M1 /* SDIO_DATA2 (IOMG078) */ - 0x13c MUX_M1 /* SDIO_DATA3 (IOMG079) */ - >; - }; - - isp_pmx_func: isp_pmx_func { - pinctrl-single,pins = < - 0x24 MUX_M0 /* ISP_PWDN0 (IOMG009) */ - 0x28 MUX_M0 /* ISP_PWDN1 (IOMG010) */ - 0x2c MUX_M0 /* ISP_PWDN2 (IOMG011) */ - 0x30 MUX_M1 /* ISP_SHUTTER0 (IOMG012) */ - 0x34 MUX_M1 /* ISP_SHUTTER1 (IOMG013) */ - 0x38 MUX_M1 /* ISP_PWM (IOMG014) */ - 0x3c MUX_M0 /* ISP_CCLK0 (IOMG015) */ - 0x40 MUX_M0 /* ISP_CCLK1 (IOMG016) */ - 0x44 MUX_M0 /* ISP_RESETB0 (IOMG017) */ - 0x48 MUX_M0 /* ISP_RESETB1 (IOMG018) */ - 0x4c MUX_M1 /* ISP_STROBE0 (IOMG019) */ - 0x50 MUX_M1 /* ISP_STROBE1 (IOMG020) */ - 0x54 MUX_M0 /* ISP_SDA0 (IOMG021) */ - 0x58 MUX_M0 /* ISP_SCL0 (IOMG022) */ - 0x5c MUX_M0 /* ISP_SDA1 (IOMG023) */ - 0x60 MUX_M0 /* ISP_SCL1 (IOMG024) */ - >; - }; - - hkadc_ssi_pmx_func: hkadc_ssi_pmx_func { - pinctrl-single,pins = < - 0x68 MUX_M0 /* HKADC_SSI (IOMG026) */ - >; - }; - - codec_clk_pmx_func: codec_clk_pmx_func { - pinctrl-single,pins = < - 0x6c MUX_M0 /* CODEC_CLK (IOMG027) */ - >; - }; - - codec_pmx_func: codec_pmx_func { - pinctrl-single,pins = < - 0x70 MUX_M1 /* DMIC_CLK (IOMG028) */ - 0x74 MUX_M0 /* CODEC_SYNC (IOMG029) */ - 0x78 MUX_M0 /* CODEC_DI (IOMG030) */ - 0x7c MUX_M0 /* CODEC_DO (IOMG031) */ - >; - }; - - fm_pmx_func: fm_pmx_func { - pinctrl-single,pins = < - 0x80 MUX_M1 /* FM_XCLK (IOMG032) */ - 0x84 MUX_M1 /* FM_XFS (IOMG033) */ - 0x88 MUX_M1 /* FM_DI (IOMG034) */ - 0x8c MUX_M1 /* FM_DO (IOMG035) */ - >; - }; - - bt_pmx_func: bt_pmx_func { - pinctrl-single,pins = < - 0x90 MUX_M0 /* BT_XCLK (IOMG036) */ - 0x94 MUX_M0 /* BT_XFS (IOMG037) */ - 0x98 MUX_M0 /* BT_DI (IOMG038) */ - 0x9c MUX_M0 /* BT_DO (IOMG039) */ - >; - }; - - pwm_in_pmx_func: pwm_in_pmx_func { - pinctrl-single,pins = < - 0xb8 MUX_M1 /* PWM_IN (IOMG046) */ - >; - }; - - bl_pwm_pmx_func: bl_pwm_pmx_func { - pinctrl-single,pins = < - 0xbc MUX_M1 /* BL_PWM (IOMG047) */ - >; - }; - - uart0_pmx_func: uart0_pmx_func { - pinctrl-single,pins = < - 0xc0 MUX_M0 /* UART0_RXD (IOMG048) */ - 0xc4 MUX_M0 /* UART0_TXD (IOMG049) */ - >; - }; - - uart1_pmx_func: uart1_pmx_func { - pinctrl-single,pins = < - 0xc8 MUX_M0 /* UART1_CTS_N (IOMG050) */ - 0xcc MUX_M0 /* UART1_RTS_N (IOMG051) */ - 0xd0 MUX_M0 /* UART1_RXD (IOMG052) */ - 0xd4 MUX_M0 /* UART1_TXD (IOMG053) */ - >; - }; - - uart2_pmx_func: uart2_pmx_func { - pinctrl-single,pins = < - 0xd8 MUX_M0 /* UART2_CTS_N (IOMG054) */ - 0xdc MUX_M0 /* UART2_RTS_N (IOMG055) */ - 0xe0 MUX_M0 /* UART2_RXD (IOMG056) */ - 0xe4 MUX_M0 /* UART2_TXD (IOMG057) */ - >; - }; - - uart3_pmx_func: uart3_pmx_func { - pinctrl-single,pins = < - 0x180 MUX_M1 /* UART3_CTS_N (IOMG096) */ - 0x184 MUX_M1 /* UART3_RTS_N (IOMG097) */ - 0x188 MUX_M1 /* UART3_RXD (IOMG098) */ - 0x18c MUX_M1 /* UART3_TXD (IOMG099) */ - >; - }; - - uart4_pmx_func: uart4_pmx_func { - pinctrl-single,pins = < - 0x1d0 MUX_M1 /* UART4_CTS_N (IOMG116) */ - 0x1d4 MUX_M1 /* UART4_RTS_N (IOMG117) */ - 0x1d8 MUX_M1 /* UART4_RXD (IOMG118) */ - 0x1dc MUX_M1 /* UART4_TXD (IOMG119) */ - >; - }; - - uart5_pmx_func: uart5_pmx_func { - pinctrl-single,pins = < - 0x1c8 MUX_M1 /* UART5_RXD (IOMG114) */ - 0x1cc MUX_M1 /* UART5_TXD (IOMG115) */ - >; - }; - - i2c0_pmx_func: i2c0_pmx_func { - pinctrl-single,pins = < - 0xe8 MUX_M0 /* I2C0_SCL (IOMG058) */ - 0xec MUX_M0 /* I2C0_SDA (IOMG059) */ - >; - }; - - i2c1_pmx_func: i2c1_pmx_func { - pinctrl-single,pins = < - 0xf0 MUX_M0 /* I2C1_SCL (IOMG060) */ - 0xf4 MUX_M0 /* I2C1_SDA (IOMG061) */ - >; - }; - - i2c2_pmx_func: i2c2_pmx_func { - pinctrl-single,pins = < - 0xf8 MUX_M0 /* I2C2_SCL (IOMG062) */ - 0xfc MUX_M0 /* I2C2_SDA (IOMG063) */ - >; - }; - - spi0_pmx_func: spi0_pmx_func { - pinctrl-single,pins = < - 0x1a0 MUX_M1 /* SPI0_DI (IOMG104) */ - 0x1a4 MUX_M1 /* SPI0_DO (IOMG105) */ - 0x1a8 MUX_M1 /* SPI0_CS_N (IOMG106) */ - 0x1ac MUX_M1 /* SPI0_CLK (IOMG107) */ - >; - }; - }; - - pmx1: pinmux@f7010800 { - - pinctrl-names = "default"; - pinctrl-0 = < - &boot_sel_cfg_func - &hkadc_ssi_cfg_func - &codec_clk_cfg_func - &pwm_in_cfg_func - &bl_pwm_cfg_func - >; - - boot_sel_cfg_func: boot_sel_cfg_func { - pinctrl-single,pins = < - 0x0 0x0 /* BOOT_SEL (IOCFG000) */ - >; - pinctrl-single,bias-pulldown = ; - pinctrl-single,bias-pullup = ; - pinctrl-single,drive-strength = ; - }; - - hkadc_ssi_cfg_func: hkadc_ssi_cfg_func { - pinctrl-single,pins = < - 0x6c 0x0 /* HKADC_SSI (IOCFG027) */ - >; - pinctrl-single,bias-pulldown = ; - pinctrl-single,bias-pullup = ; - pinctrl-single,drive-strength = ; - }; - - emmc_clk_cfg_func: emmc_clk_cfg_func { - pinctrl-single,pins = < - 0x104 0x0 /* EMMC_CLK (IOCFG065) */ - >; - pinctrl-single,bias-pulldown = ; - pinctrl-single,bias-pullup = ; - pinctrl-single,drive-strength = ; - }; - - emmc_cfg_func: emmc_cfg_func { - pinctrl-single,pins = < - 0x108 0x0 /* EMMC_CMD (IOCFG066) */ - 0x10c 0x0 /* EMMC_DATA0 (IOCFG067) */ - 0x110 0x0 /* EMMC_DATA1 (IOCFG068) */ - 0x114 0x0 /* EMMC_DATA2 (IOCFG069) */ - 0x118 0x0 /* EMMC_DATA3 (IOCFG070) */ - 0x11c 0x0 /* EMMC_DATA4 (IOCFG071) */ - 0x120 0x0 /* EMMC_DATA5 (IOCFG072) */ - 0x124 0x0 /* EMMC_DATA6 (IOCFG073) */ - 0x128 0x0 /* EMMC_DATA7 (IOCFG074) */ - >; - pinctrl-single,bias-pulldown = ; - pinctrl-single,bias-pullup = ; - pinctrl-single,drive-strength = ; - }; - - emmc_rst_cfg_func: emmc_rst_cfg_func { - pinctrl-single,pins = < - 0x12c 0x0 /* EMMC_RST_N (IOCFG075) */ - >; - pinctrl-single,bias-pulldown = ; - pinctrl-single,bias-pullup = ; - pinctrl-single,drive-strength = ; - }; - - sd_clk_cfg_func: sd_clk_cfg_func { - pinctrl-single,pins = < - 0xc 0x0 /* SD_CLK (IOCFG003) */ - >; - pinctrl-single,bias-pulldown = ; - pinctrl-single,bias-pullup = ; - pinctrl-single,drive-strength = ; - }; - sd_clk_cfg_idle: sd_clk_cfg_idle { - pinctrl-single,pins = < - 0xc 0x0 /* SD_CLK (IOCFG003) */ - >; - pinctrl-single,bias-pulldown = ; - pinctrl-single,bias-pullup = ; - pinctrl-single,drive-strength = ; - }; - - sd_cfg_func: sd_cfg_func { - pinctrl-single,pins = < - 0x10 0x0 /* SD_CMD (IOCFG004) */ - 0x14 0x0 /* SD_DATA0 (IOCFG005) */ - 0x18 0x0 /* SD_DATA1 (IOCFG006) */ - 0x1c 0x0 /* SD_DATA2 (IOCFG007) */ - 0x20 0x0 /* SD_DATA3 (IOCFG008) */ - >; - pinctrl-single,bias-pulldown = ; - pinctrl-single,bias-pullup = ; - pinctrl-single,drive-strength = ; - }; - sd_cfg_idle: sd_cfg_idle { - pinctrl-single,pins = < - 0x10 0x0 /* SD_CMD (IOCFG004) */ - 0x14 0x0 /* SD_DATA0 (IOCFG005) */ - 0x18 0x0 /* SD_DATA1 (IOCFG006) */ - 0x1c 0x0 /* SD_DATA2 (IOCFG007) */ - 0x20 0x0 /* SD_DATA3 (IOCFG008) */ - >; - pinctrl-single,bias-pulldown = ; - pinctrl-single,bias-pullup = ; - pinctrl-single,drive-strength = ; - }; - - sdio_clk_cfg_func: sdio_clk_cfg_func { - pinctrl-single,pins = < - 0x134 0x0 /* SDIO_CLK (IOCFG077) */ - >; - pinctrl-single,bias-pulldown = ; - pinctrl-single,bias-pullup = ; - pinctrl-single,drive-strength = ; - }; - sdio_clk_cfg_idle: sdio_clk_cfg_idle { - pinctrl-single,pins = < - 0x134 0x0 /* SDIO_CLK (IOCFG077) */ - >; - pinctrl-single,bias-pulldown = ; - pinctrl-single,bias-pullup = ; - pinctrl-single,drive-strength = ; - }; - - sdio_cfg_func: sdio_cfg_func { - pinctrl-single,pins = < - 0x138 0x0 /* SDIO_CMD (IOCFG078) */ - 0x13c 0x0 /* SDIO_DATA0 (IOCFG079) */ - 0x140 0x0 /* SDIO_DATA1 (IOCFG080) */ - 0x144 0x0 /* SDIO_DATA2 (IOCFG081) */ - 0x148 0x0 /* SDIO_DATA3 (IOCFG082) */ - >; - pinctrl-single,bias-pulldown = ; - pinctrl-single,bias-pullup = ; - pinctrl-single,drive-strength = ; - }; - sdio_cfg_idle: sdio_cfg_idle { - pinctrl-single,pins = < - 0x138 0x0 /* SDIO_CMD (IOCFG078) */ - 0x13c 0x0 /* SDIO_DATA0 (IOCFG079) */ - 0x140 0x0 /* SDIO_DATA1 (IOCFG080) */ - 0x144 0x0 /* SDIO_DATA2 (IOCFG081) */ - 0x148 0x0 /* SDIO_DATA3 (IOCFG082) */ - >; - pinctrl-single,bias-pulldown = ; - pinctrl-single,bias-pullup = ; - pinctrl-single,drive-strength = ; - }; - - isp_cfg_func1: isp_cfg_func1 { - pinctrl-single,pins = < - 0x28 0x0 /* ISP_PWDN0 (IOCFG010) */ - 0x2c 0x0 /* ISP_PWDN1 (IOCFG011) */ - 0x30 0x0 /* ISP_PWDN2 (IOCFG012) */ - 0x34 0x0 /* ISP_SHUTTER0 (IOCFG013) */ - 0x38 0x0 /* ISP_SHUTTER1 (IOCFG014) */ - 0x3c 0x0 /* ISP_PWM (IOCFG015) */ - 0x40 0x0 /* ISP_CCLK0 (IOCFG016) */ - 0x44 0x0 /* ISP_CCLK1 (IOCFG017) */ - 0x48 0x0 /* ISP_RESETB0 (IOCFG018) */ - 0x4c 0x0 /* ISP_RESETB1 (IOCFG019) */ - 0x50 0x0 /* ISP_STROBE0 (IOCFG020) */ - 0x58 0x0 /* ISP_SDA0 (IOCFG022) */ - 0x5c 0x0 /* ISP_SCL0 (IOCFG023) */ - 0x60 0x0 /* ISP_SDA1 (IOCFG024) */ - 0x64 0x0 /* ISP_SCL1 (IOCFG025) */ - >; - pinctrl-single,bias-pulldown = ; - pinctrl-single,bias-pullup = ; - pinctrl-single,drive-strength = ; - }; - isp_cfg_idle1: isp_cfg_idle1 { - pinctrl-single,pins = < - 0x34 0x0 /* ISP_SHUTTER0 (IOCFG013) */ - 0x38 0x0 /* ISP_SHUTTER1 (IOCFG014) */ - >; - pinctrl-single,bias-pulldown = ; - pinctrl-single,bias-pullup = ; - pinctrl-single,drive-strength = ; - }; - - isp_cfg_func2: isp_cfg_func2 { - pinctrl-single,pins = < - 0x54 0x0 /* ISP_STROBE1 (IOCFG021) */ - >; - pinctrl-single,bias-pulldown = ; - pinctrl-single,bias-pullup = ; - pinctrl-single,drive-strength = ; - }; - - codec_clk_cfg_func: codec_clk_cfg_func { - pinctrl-single,pins = < - 0x70 0x0 /* CODEC_CLK (IOCFG028) */ - >; - pinctrl-single,bias-pulldown = ; - pinctrl-single,bias-pullup = ; - pinctrl-single,drive-strength = ; - }; - codec_clk_cfg_idle: codec_clk_cfg_idle { - pinctrl-single,pins = < - 0x70 0x0 /* CODEC_CLK (IOCFG028) */ - >; - pinctrl-single,bias-pulldown = ; - pinctrl-single,bias-pullup = ; - pinctrl-single,drive-strength = ; - }; - - codec_cfg_func1: codec_cfg_func1 { - pinctrl-single,pins = < - 0x74 0x0 /* DMIC_CLK (IOCFG029) */ - >; - pinctrl-single,bias-pulldown = ; - pinctrl-single,bias-pullup = ; - pinctrl-single,drive-strength = ; - }; - - codec_cfg_func2: codec_cfg_func2 { - pinctrl-single,pins = < - 0x78 0x0 /* CODEC_SYNC (IOCFG030) */ - 0x7c 0x0 /* CODEC_DI (IOCFG031) */ - 0x80 0x0 /* CODEC_DO (IOCFG032) */ - >; - pinctrl-single,bias-pulldown = ; - pinctrl-single,bias-pullup = ; - pinctrl-single,drive-strength = ; - }; - codec_cfg_idle2: codec_cfg_idle2 { - pinctrl-single,pins = < - 0x78 0x0 /* CODEC_SYNC (IOCFG030) */ - 0x7c 0x0 /* CODEC_DI (IOCFG031) */ - 0x80 0x0 /* CODEC_DO (IOCFG032) */ - >; - pinctrl-single,bias-pulldown = ; - pinctrl-single,bias-pullup = ; - pinctrl-single,drive-strength = ; - }; - - fm_cfg_func: fm_cfg_func { - pinctrl-single,pins = < - 0x84 0x0 /* FM_XCLK (IOCFG033) */ - 0x88 0x0 /* FM_XFS (IOCFG034) */ - 0x8c 0x0 /* FM_DI (IOCFG035) */ - 0x90 0x0 /* FM_DO (IOCFG036) */ - >; - pinctrl-single,bias-pulldown = ; - pinctrl-single,bias-pullup = ; - pinctrl-single,drive-strength = ; - }; - - bt_cfg_func: bt_cfg_func { - pinctrl-single,pins = < - 0x94 0x0 /* BT_XCLK (IOCFG037) */ - 0x98 0x0 /* BT_XFS (IOCFG038) */ - 0x9c 0x0 /* BT_DI (IOCFG039) */ - 0xa0 0x0 /* BT_DO (IOCFG040) */ - >; - pinctrl-single,bias-pulldown = ; - pinctrl-single,bias-pullup = ; - pinctrl-single,drive-strength = ; - }; - bt_cfg_idle: bt_cfg_idle { - pinctrl-single,pins = < - 0x94 0x0 /* BT_XCLK (IOCFG037) */ - 0x98 0x0 /* BT_XFS (IOCFG038) */ - 0x9c 0x0 /* BT_DI (IOCFG039) */ - 0xa0 0x0 /* BT_DO (IOCFG040) */ - >; - pinctrl-single,bias-pulldown = ; - pinctrl-single,bias-pullup = ; - pinctrl-single,drive-strength = ; - }; - - pwm_in_cfg_func: pwm_in_cfg_func { - pinctrl-single,pins = < - 0xbc 0x0 /* PWM_IN (IOCFG047) */ - >; - pinctrl-single,bias-pulldown = ; - pinctrl-single,bias-pullup = ; - pinctrl-single,drive-strength = ; - }; - - bl_pwm_cfg_func: bl_pwm_cfg_func { - pinctrl-single,pins = < - 0xc0 0x0 /* BL_PWM (IOCFG048) */ - >; - pinctrl-single,bias-pulldown = ; - pinctrl-single,bias-pullup = ; - pinctrl-single,drive-strength = ; - }; - - uart0_cfg_func1: uart0_cfg_func1 { - pinctrl-single,pins = < - 0xc4 0x0 /* UART0_RXD (IOCFG049) */ - >; - pinctrl-single,bias-pulldown = ; - pinctrl-single,bias-pullup = ; - pinctrl-single,drive-strength = ; - }; - - uart0_cfg_func2: uart0_cfg_func2 { - pinctrl-single,pins = < - 0xc8 0x0 /* UART0_TXD (IOCFG050) */ - >; - pinctrl-single,bias-pulldown = ; - pinctrl-single,bias-pullup = ; - pinctrl-single,drive-strength = ; - }; - - uart1_cfg_func1: uart1_cfg_func1 { - pinctrl-single,pins = < - 0xcc 0x0 /* UART1_CTS_N (IOCFG051) */ - 0xd4 0x0 /* UART1_RXD (IOCFG053) */ - >; - pinctrl-single,bias-pulldown = ; - pinctrl-single,bias-pullup = ; - pinctrl-single,drive-strength = ; - }; - - uart1_cfg_func2: uart1_cfg_func2 { - pinctrl-single,pins = < - 0xd0 0x0 /* UART1_RTS_N (IOCFG052) */ - 0xd8 0x0 /* UART1_TXD (IOCFG054) */ - >; - pinctrl-single,bias-pulldown = ; - pinctrl-single,bias-pullup = ; - pinctrl-single,drive-strength = ; - }; - - uart2_cfg_func: uart2_cfg_func { - pinctrl-single,pins = < - 0xdc 0x0 /* UART2_CTS_N (IOCFG055) */ - 0xe0 0x0 /* UART2_RTS_N (IOCFG056) */ - 0xe4 0x0 /* UART2_RXD (IOCFG057) */ - 0xe8 0x0 /* UART2_TXD (IOCFG058) */ - >; - pinctrl-single,bias-pulldown = ; - pinctrl-single,bias-pullup = ; - pinctrl-single,drive-strength = ; - }; - - uart3_cfg_func: uart3_cfg_func { - pinctrl-single,pins = < - 0x190 0x0 /* UART3_CTS_N (IOCFG100) */ - 0x194 0x0 /* UART3_RTS_N (IOCFG101) */ - 0x198 0x0 /* UART3_RXD (IOCFG102) */ - 0x19c 0x0 /* UART3_TXD (IOCFG103) */ - >; - pinctrl-single,bias-pulldown = ; - pinctrl-single,bias-pullup = ; - pinctrl-single,drive-strength = ; - }; - - uart4_cfg_func: uart4_cfg_func { - pinctrl-single,pins = < - 0x1e0 0x0 /* UART4_CTS_N (IOCFG120) */ - 0x1e4 0x0 /* UART4_RTS_N (IOCFG121) */ - 0x1e8 0x0 /* UART4_RXD (IOCFG122) */ - 0x1ec 0x0 /* UART4_TXD (IOCFG123) */ - >; - pinctrl-single,bias-pulldown = ; - pinctrl-single,bias-pullup = ; - pinctrl-single,drive-strength = ; - }; - - uart5_cfg_func: uart5_cfg_func { - pinctrl-single,pins = < - 0x1d8 0x0 /* UART4_RXD (IOCFG118) */ - 0x1dc 0x0 /* UART4_TXD (IOCFG119) */ - >; - pinctrl-single,bias-pulldown = ; - pinctrl-single,bias-pullup = ; - pinctrl-single,drive-strength = ; - }; - - i2c0_cfg_func: i2c0_cfg_func { - pinctrl-single,pins = < - 0xec 0x0 /* I2C0_SCL (IOCFG059) */ - 0xf0 0x0 /* I2C0_SDA (IOCFG060) */ - >; - pinctrl-single,bias-pulldown = ; - pinctrl-single,bias-pullup = ; - pinctrl-single,drive-strength = ; - }; - - i2c1_cfg_func: i2c1_cfg_func { - pinctrl-single,pins = < - 0xf4 0x0 /* I2C1_SCL (IOCFG061) */ - 0xf8 0x0 /* I2C1_SDA (IOCFG062) */ - >; - pinctrl-single,bias-pulldown = ; - pinctrl-single,bias-pullup = ; - pinctrl-single,drive-strength = ; - }; - - i2c2_cfg_func: i2c2_cfg_func { - pinctrl-single,pins = < - 0xfc 0x0 /* I2C2_SCL (IOCFG063) */ - 0x100 0x0 /* I2C2_SDA (IOCFG064) */ - >; - pinctrl-single,bias-pulldown = ; - pinctrl-single,bias-pullup = ; - pinctrl-single,drive-strength = ; - }; - - spi0_cfg_func: spi0_cfg_func { - pinctrl-single,pins = < - 0x1b0 0x0 /* SPI0_DI (IOCFG108) */ - 0x1b4 0x0 /* SPI0_DO (IOCFG109) */ - 0x1b8 0x0 /* SPI0_CS_N (IOCFG110) */ - 0x1bc 0x0 /* SPI0_CLK (IOCFG111) */ - >; - pinctrl-single,bias-pulldown = ; - pinctrl-single,bias-pullup = ; - pinctrl-single,drive-strength = ; - }; - }; - - pmx2: pinmux@f8001800 { - - pinctrl-names = "default"; - pinctrl-0 = < - &rstout_n_cfg_func - >; - - rstout_n_cfg_func: rstout_n_cfg_func { - pinctrl-single,pins = < - 0x0 0x0 /* RSTOUT_N (IOCFG000) */ - >; - pinctrl-single,bias-pulldown = ; - pinctrl-single,bias-pullup = ; - pinctrl-single,drive-strength = ; - }; - - pmu_peri_en_cfg_func: pmu_peri_en_cfg_func { - pinctrl-single,pins = < - 0x4 0x0 /* PMU_PERI_EN (IOCFG001) */ - >; - pinctrl-single,bias-pulldown = ; - pinctrl-single,bias-pullup = ; - pinctrl-single,drive-strength = ; - }; - - sysclk0_en_cfg_func: sysclk0_en_cfg_func { - pinctrl-single,pins = < - 0x8 0x0 /* SYSCLK0_EN (IOCFG002) */ - >; - pinctrl-single,bias-pulldown = ; - pinctrl-single,bias-pullup = ; - pinctrl-single,drive-strength = ; - }; - - jtag_tdo_cfg_func: jtag_tdo_cfg_func { - pinctrl-single,pins = < - 0xc 0x0 /* JTAG_TDO (IOCFG003) */ - >; - pinctrl-single,bias-pulldown = ; - pinctrl-single,bias-pullup = ; - pinctrl-single,drive-strength = ; - }; - - rf_reset_cfg_func: rf_reset_cfg_func { - pinctrl-single,pins = < - 0x70 0x0 /* RF_RESET0 (IOCFG028) */ - 0x74 0x0 /* RF_RESET1 (IOCFG029) */ - >; - pinctrl-single,bias-pulldown = ; - pinctrl-single,bias-pullup = ; - pinctrl-single,drive-strength = ; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/hisilicon/hikey960-pinctrl.dtsi b/sys/gnu/dts/arm64/hisilicon/hikey960-pinctrl.dtsi deleted file mode 100644 index d11efc81958..00000000000 --- a/sys/gnu/dts/arm64/hisilicon/hikey960-pinctrl.dtsi +++ /dev/null @@ -1,1060 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * pinctrl dts fils for Hislicon HiKey960 development board - * - */ - -#include - -/ { - soc { - /* [IOMG_000, IOMG_123] */ - range: gpio-range { - #pinctrl-single,gpio-range-cells = <3>; - }; - - pmx0: pinmux@e896c000 { - compatible = "pinctrl-single"; - reg = <0x0 0xe896c000 0x0 0x1f0>; - #pinctrl-cells = <1>; - #gpio-range-cells = <0x3>; - pinctrl-single,register-width = <0x20>; - pinctrl-single,function-mask = <0x7>; - /* pin base, nr pins & gpio function */ - pinctrl-single,gpio-range = < - &range 0 7 0 - &range 8 116 0>; - - pmu_pmx_func: pmu_pmx_func { - pinctrl-single,pins = < - 0x008 MUX_M1 /* PMU1_SSI */ - 0x00c MUX_M1 /* PMU2_SSI */ - 0x010 MUX_M1 /* PMU_CLKOUT */ - 0x100 MUX_M1 /* PMU_HKADC_SSI */ - >; - }; - - csi0_pwd_n_pmx_func: csi0_pwd_n_pmx_func { - pinctrl-single,pins = < - 0x044 MUX_M0 /* CSI0_PWD_N */ - >; - }; - - csi1_pwd_n_pmx_func: csi1_pwd_n_pmx_func { - pinctrl-single,pins = < - 0x04c MUX_M0 /* CSI1_PWD_N */ - >; - }; - - isp0_pmx_func: isp0_pmx_func { - pinctrl-single,pins = < - 0x058 MUX_M1 /* ISP_CLK0 */ - 0x064 MUX_M1 /* ISP_SCL0 */ - 0x068 MUX_M1 /* ISP_SDA0 */ - >; - }; - - isp1_pmx_func: isp1_pmx_func { - pinctrl-single,pins = < - 0x05c MUX_M1 /* ISP_CLK1 */ - 0x06c MUX_M1 /* ISP_SCL1 */ - 0x070 MUX_M1 /* ISP_SDA1 */ - >; - }; - - pwr_key_pmx_func: pwr_key_pmx_func { - pinctrl-single,pins = < - 0x080 MUX_M0 /* GPIO_034 */ - >; - }; - - i2c3_pmx_func: i2c3_pmx_func { - pinctrl-single,pins = < - 0x02c MUX_M1 /* I2C3_SCL */ - 0x030 MUX_M1 /* I2C3_SDA */ - >; - }; - - i2c4_pmx_func: i2c4_pmx_func { - pinctrl-single,pins = < - 0x090 MUX_M1 /* I2C4_SCL */ - 0x094 MUX_M1 /* I2C4_SDA */ - >; - }; - - pcie_perstn_pmx_func: pcie_perstn_pmx_func { - pinctrl-single,pins = < - 0x15c MUX_M1 /* PCIE_PERST_N */ - >; - }; - - usbhub5734_pmx_func: usbhub5734_pmx_func { - pinctrl-single,pins = < - 0x11c MUX_M0 /* GPIO_073 */ - 0x120 MUX_M0 /* GPIO_074 */ - >; - }; - - uart0_pmx_func: uart0_pmx_func { - pinctrl-single,pins = < - 0x0cc MUX_M2 /* UART0_RXD */ - 0x0d0 MUX_M2 /* UART0_TXD */ - >; - }; - - uart1_pmx_func: uart1_pmx_func { - pinctrl-single,pins = < - 0x0b0 MUX_M2 /* UART1_CTS_N */ - 0x0b4 MUX_M2 /* UART1_RTS_N */ - 0x0a8 MUX_M2 /* UART1_RXD */ - 0x0ac MUX_M2 /* UART1_TXD */ - >; - }; - - uart2_pmx_func: uart2_pmx_func { - pinctrl-single,pins = < - 0x0bc MUX_M2 /* UART2_CTS_N */ - 0x0c0 MUX_M2 /* UART2_RTS_N */ - 0x0c8 MUX_M2 /* UART2_RXD */ - 0x0c4 MUX_M2 /* UART2_TXD */ - >; - }; - - uart3_pmx_func: uart3_pmx_func { - pinctrl-single,pins = < - 0x0dc MUX_M1 /* UART3_CTS_N */ - 0x0e0 MUX_M1 /* UART3_RTS_N */ - 0x0e4 MUX_M1 /* UART3_RXD */ - 0x0e8 MUX_M1 /* UART3_TXD */ - >; - }; - - uart4_pmx_func: uart4_pmx_func { - pinctrl-single,pins = < - 0x0ec MUX_M1 /* UART4_CTS_N */ - 0x0f0 MUX_M1 /* UART4_RTS_N */ - 0x0f4 MUX_M1 /* UART4_RXD */ - 0x0f8 MUX_M1 /* UART4_TXD */ - >; - }; - - uart5_pmx_func: uart5_pmx_func { - pinctrl-single,pins = < - 0x0c4 MUX_M3 /* UART5_CTS_N */ - 0x0c8 MUX_M3 /* UART5_RTS_N */ - 0x0bc MUX_M3 /* UART5_RXD */ - 0x0c0 MUX_M3 /* UART5_TXD */ - >; - }; - - uart6_pmx_func: uart6_pmx_func { - pinctrl-single,pins = < - 0x0cc MUX_M1 /* UART6_CTS_N */ - 0x0d0 MUX_M1 /* UART6_RTS_N */ - 0x0d4 MUX_M1 /* UART6_RXD */ - 0x0d8 MUX_M1 /* UART6_TXD */ - >; - }; - - cam0_rst_pmx_func: cam0_rst_pmx_func { - pinctrl-single,pins = < - 0x0c8 MUX_M0 /* CAM0_RST */ - >; - }; - - cam1_rst_pmx_func: cam1_rst_pmx_func { - pinctrl-single,pins = < - 0x124 MUX_M0 /* CAM1_RST */ - >; - }; - }; - - /* [IOMG_MMC0_000, IOMG_MMC0_005] */ - pmx1: pinmux@ff37e000 { - compatible = "pinctrl-single"; - reg = <0x0 0xff37e000 0x0 0x18>; - #gpio-range-cells = <0x3>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <0x20>; - pinctrl-single,function-mask = <0x7>; - /* pin base, nr pins & gpio function */ - pinctrl-single,gpio-range = <&range 0 6 0>; - - sd_pmx_func: sd_pmx_func { - pinctrl-single,pins = < - 0x000 MUX_M1 /* SD_CLK */ - 0x004 MUX_M1 /* SD_CMD */ - 0x008 MUX_M1 /* SD_DATA0 */ - 0x00c MUX_M1 /* SD_DATA1 */ - 0x010 MUX_M1 /* SD_DATA2 */ - 0x014 MUX_M1 /* SD_DATA3 */ - >; - }; - }; - - /* [IOMG_FIX_000, IOMG_FIX_011] */ - pmx2: pinmux@ff3b6000 { - compatible = "pinctrl-single"; - reg = <0x0 0xff3b6000 0x0 0x30>; - #pinctrl-cells = <1>; - #gpio-range-cells = <0x3>; - pinctrl-single,register-width = <0x20>; - pinctrl-single,function-mask = <0x7>; - /* pin base, nr pins & gpio function */ - pinctrl-single,gpio-range = <&range 0 12 0>; - - ufs_pmx_func: ufs_pmx_func { - pinctrl-single,pins = < - 0x000 MUX_M1 /* UFS_REF_CLK */ - 0x004 MUX_M1 /* UFS_RST_N */ - >; - }; - - spi3_pmx_func: spi3_pmx_func { - pinctrl-single,pins = < - 0x008 MUX_M1 /* SPI3_CLK */ - 0x00c MUX_M1 /* SPI3_DI */ - 0x010 MUX_M1 /* SPI3_DO */ - 0x014 MUX_M1 /* SPI3_CS0_N */ - >; - }; - }; - - /* [IOMG_MMC1_000, IOMG_MMC1_005] */ - pmx3: pinmux@ff3fd000 { - compatible = "pinctrl-single"; - reg = <0x0 0xff3fd000 0x0 0x18>; - #pinctrl-cells = <1>; - #gpio-range-cells = <0x3>; - pinctrl-single,register-width = <0x20>; - pinctrl-single,function-mask = <0x7>; - /* pin base, nr pins & gpio function */ - pinctrl-single,gpio-range = <&range 0 6 0>; - - sdio_pmx_func: sdio_pmx_func { - pinctrl-single,pins = < - 0x000 MUX_M1 /* SDIO_CLK */ - 0x004 MUX_M1 /* SDIO_CMD */ - 0x008 MUX_M1 /* SDIO_DATA0 */ - 0x00c MUX_M1 /* SDIO_DATA1 */ - 0x010 MUX_M1 /* SDIO_DATA2 */ - 0x014 MUX_M1 /* SDIO_DATA3 */ - >; - }; - }; - - /* [IOMG_AO_000, IOMG_AO_041] */ - pmx4: pinmux@fff11000 { - compatible = "pinctrl-single"; - reg = <0x0 0xfff11000 0x0 0xa8>; - #pinctrl-cells = <1>; - #gpio-range-cells = <0x3>; - pinctrl-single,register-width = <0x20>; - pinctrl-single,function-mask = <0x7>; - /* pin base in node, nr pins & gpio function */ - pinctrl-single,gpio-range = <&range 0 42 0>; - - i2s2_pmx_func: i2s2_pmx_func { - pinctrl-single,pins = < - 0x044 MUX_M1 /* I2S2_DI */ - 0x048 MUX_M1 /* I2S2_DO */ - 0x04c MUX_M1 /* I2S2_XCLK */ - 0x050 MUX_M1 /* I2S2_XFS */ - >; - }; - - slimbus_pmx_func: slimbus_pmx_func { - pinctrl-single,pins = < - 0x02c MUX_M1 /* SLIMBUS_CLK */ - 0x030 MUX_M1 /* SLIMBUS_DATA */ - >; - }; - - i2c0_pmx_func: i2c0_pmx_func { - pinctrl-single,pins = < - 0x014 MUX_M1 /* I2C0_SCL */ - 0x018 MUX_M1 /* I2C0_SDA */ - >; - }; - - i2c1_pmx_func: i2c1_pmx_func { - pinctrl-single,pins = < - 0x01c MUX_M1 /* I2C1_SCL */ - 0x020 MUX_M1 /* I2C1_SDA */ - >; - }; - - i2c7_pmx_func: i2c7_pmx_func { - pinctrl-single,pins = < - 0x024 MUX_M3 /* I2C7_SCL */ - 0x028 MUX_M3 /* I2C7_SDA */ - >; - }; - - pcie_pmx_func: pcie_pmx_func { - pinctrl-single,pins = < - 0x084 MUX_M1 /* PCIE_CLKREQ_N */ - 0x088 MUX_M1 /* PCIE_WAKE_N */ - >; - }; - - spi2_pmx_func: spi2_pmx_func { - pinctrl-single,pins = < - 0x08c MUX_M1 /* SPI2_CLK */ - 0x090 MUX_M1 /* SPI2_DI */ - 0x094 MUX_M1 /* SPI2_DO */ - 0x098 MUX_M1 /* SPI2_CS0_N */ - >; - }; - - i2s0_pmx_func: i2s0_pmx_func { - pinctrl-single,pins = < - 0x034 MUX_M1 /* I2S0_DI */ - 0x038 MUX_M1 /* I2S0_DO */ - 0x03c MUX_M1 /* I2S0_XCLK */ - 0x040 MUX_M1 /* I2S0_XFS */ - >; - }; - }; - - pmx5: pinmux@e896c800 { - compatible = "pinconf-single"; - reg = <0x0 0xe896c800 0x0 0x200>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <0x20>; - - pmu_cfg_func: pmu_cfg_func { - pinctrl-single,pins = < - 0x010 0x0 /* PMU1_SSI */ - 0x014 0x0 /* PMU2_SSI */ - 0x018 0x0 /* PMU_CLKOUT */ - 0x10c 0x0 /* PMU_HKADC_SSI */ - >; - pinctrl-single,bias-pulldown = < - PULL_DIS - PULL_DOWN - PULL_DIS - PULL_DOWN - >; - pinctrl-single,bias-pullup = < - PULL_DIS - PULL_UP - PULL_DIS - PULL_UP - >; - pinctrl-single,drive-strength = < - DRIVE7_06MA DRIVE6_MASK - >; - }; - - i2c3_cfg_func: i2c3_cfg_func { - pinctrl-single,pins = < - 0x038 0x0 /* I2C3_SCL */ - 0x03c 0x0 /* I2C3_SDA */ - >; - pinctrl-single,bias-pulldown = < - PULL_DIS - PULL_DOWN - PULL_DIS - PULL_DOWN - >; - pinctrl-single,bias-pullup = < - PULL_DIS - PULL_UP - PULL_DIS - PULL_UP - >; - pinctrl-single,drive-strength = < - DRIVE7_02MA DRIVE6_MASK - >; - }; - - csi0_pwd_n_cfg_func: csi0_pwd_n_cfg_func { - pinctrl-single,pins = < - 0x050 0x0 /* CSI0_PWD_N */ - >; - pinctrl-single,bias-pulldown = < - PULL_DIS - PULL_DOWN - PULL_DIS - PULL_DOWN - >; - pinctrl-single,bias-pullup = < - PULL_DIS - PULL_UP - PULL_DIS - PULL_UP - >; - pinctrl-single,drive-strength = < - DRIVE7_04MA DRIVE6_MASK - >; - }; - - csi1_pwd_n_cfg_func: csi1_pwd_n_cfg_func { - pinctrl-single,pins = < - 0x058 0x0 /* CSI1_PWD_N */ - >; - pinctrl-single,bias-pulldown = < - PULL_DIS - PULL_DOWN - PULL_DIS - PULL_DOWN - >; - pinctrl-single,bias-pullup = < - PULL_DIS - PULL_UP - PULL_DIS - PULL_UP - >; - pinctrl-single,drive-strength = < - DRIVE7_04MA DRIVE6_MASK - >; - }; - - isp0_cfg_func: isp0_cfg_func { - pinctrl-single,pins = < - 0x064 0x0 /* ISP_CLK0 */ - 0x070 0x0 /* ISP_SCL0 */ - 0x074 0x0 /* ISP_SDA0 */ - >; - pinctrl-single,bias-pulldown = < - PULL_DIS - PULL_DOWN - PULL_DIS - PULL_DOWN - >; - pinctrl-single,bias-pullup = < - PULL_DIS - PULL_UP - PULL_DIS - PULL_UP - >; - pinctrl-single,drive-strength = < - DRIVE7_04MA DRIVE6_MASK>; - }; - - isp1_cfg_func: isp1_cfg_func { - pinctrl-single,pins = < - 0x068 0x0 /* ISP_CLK1 */ - 0x078 0x0 /* ISP_SCL1 */ - 0x07c 0x0 /* ISP_SDA1 */ - >; - pinctrl-single,bias-pulldown = < - PULL_DIS - PULL_DOWN - PULL_DIS - PULL_DOWN - >; - pinctrl-single,bias-pullup = < - PULL_DIS - PULL_UP - PULL_DIS - PULL_UP - >; - pinctrl-single,drive-strength = < - DRIVE7_04MA DRIVE6_MASK - >; - }; - - pwr_key_cfg_func: pwr_key_cfg_func { - pinctrl-single,pins = < - 0x08c 0x0 /* GPIO_034 */ - >; - pinctrl-single,bias-pulldown = < - PULL_DIS - PULL_DOWN - PULL_DIS - PULL_DOWN - >; - pinctrl-single,bias-pullup = < - PULL_DIS - PULL_UP - PULL_DIS - PULL_UP - >; - pinctrl-single,drive-strength = < - DRIVE7_02MA DRIVE6_MASK - >; - }; - - uart1_cfg_func: uart1_cfg_func { - pinctrl-single,pins = < - 0x0b4 0x0 /* UART1_RXD */ - 0x0b8 0x0 /* UART1_TXD */ - 0x0bc 0x0 /* UART1_CTS_N */ - 0x0c0 0x0 /* UART1_RTS_N */ - >; - pinctrl-single,bias-pulldown = < - PULL_DIS - PULL_DOWN - PULL_DIS - PULL_DOWN - >; - pinctrl-single,bias-pullup = < - PULL_DIS - PULL_UP - PULL_DIS - PULL_UP - >; - pinctrl-single,drive-strength = < - DRIVE7_02MA DRIVE6_MASK - >; - }; - - uart2_cfg_func: uart2_cfg_func { - pinctrl-single,pins = < - 0x0c8 0x0 /* UART2_CTS_N */ - 0x0cc 0x0 /* UART2_RTS_N */ - 0x0d0 0x0 /* UART2_TXD */ - 0x0d4 0x0 /* UART2_RXD */ - >; - pinctrl-single,bias-pulldown = < - PULL_DIS - PULL_DOWN - PULL_DIS - PULL_DOWN - >; - pinctrl-single,bias-pullup = < - PULL_DIS - PULL_UP - PULL_DIS - PULL_UP - >; - pinctrl-single,drive-strength = < - DRIVE7_02MA DRIVE6_MASK - >; - }; - - uart5_cfg_func: uart5_cfg_func { - pinctrl-single,pins = < - 0x0c8 0x0 /* UART5_RXD */ - 0x0cc 0x0 /* UART5_TXD */ - 0x0d0 0x0 /* UART5_CTS_N */ - 0x0d4 0x0 /* UART5_RTS_N */ - >; - pinctrl-single,bias-pulldown = < - PULL_DIS - PULL_DOWN - PULL_DIS - PULL_DOWN - >; - pinctrl-single,bias-pullup = < - PULL_DIS - PULL_UP - PULL_DIS - PULL_UP - >; - pinctrl-single,drive-strength = < - DRIVE7_02MA DRIVE6_MASK - >; - }; - - cam0_rst_cfg_func: cam0_rst_cfg_func { - pinctrl-single,pins = < - 0x0d4 0x0 /* CAM0_RST */ - >; - pinctrl-single,bias-pulldown = < - PULL_DIS - PULL_DOWN - PULL_DIS - PULL_DOWN - >; - pinctrl-single,bias-pullup = < - PULL_DIS - PULL_UP - PULL_DIS - PULL_UP - >; - pinctrl-single,drive-strength = < - DRIVE7_04MA DRIVE6_MASK - >; - }; - - uart0_cfg_func: uart0_cfg_func { - pinctrl-single,pins = < - 0x0d8 0x0 /* UART0_RXD */ - 0x0dc 0x0 /* UART0_TXD */ - >; - pinctrl-single,bias-pulldown = < - PULL_DIS - PULL_DOWN - PULL_DIS - PULL_DOWN - >; - pinctrl-single,bias-pullup = < - PULL_DIS - PULL_UP - PULL_DIS - PULL_UP - >; - pinctrl-single,drive-strength = < - DRIVE7_02MA DRIVE6_MASK - >; - }; - - uart6_cfg_func: uart6_cfg_func { - pinctrl-single,pins = < - 0x0d8 0x0 /* UART6_CTS_N */ - 0x0dc 0x0 /* UART6_RTS_N */ - 0x0e0 0x0 /* UART6_RXD */ - 0x0e4 0x0 /* UART6_TXD */ - >; - pinctrl-single,bias-pulldown = < - PULL_DIS - PULL_DOWN - PULL_DIS - PULL_DOWN - >; - pinctrl-single,bias-pullup = < - PULL_DIS - PULL_UP - PULL_DIS - PULL_UP - >; - pinctrl-single,drive-strength = < - DRIVE7_02MA DRIVE6_MASK - >; - }; - - uart3_cfg_func: uart3_cfg_func { - pinctrl-single,pins = < - 0x0e8 0x0 /* UART3_CTS_N */ - 0x0ec 0x0 /* UART3_RTS_N */ - 0x0f0 0x0 /* UART3_RXD */ - 0x0f4 0x0 /* UART3_TXD */ - >; - pinctrl-single,bias-pulldown = < - PULL_DIS - PULL_DOWN - PULL_DIS - PULL_DOWN - >; - pinctrl-single,bias-pullup = < - PULL_DIS - PULL_UP - PULL_DIS - PULL_UP - >; - pinctrl-single,drive-strength = < - DRIVE7_02MA DRIVE6_MASK - >; - }; - - uart4_cfg_func: uart4_cfg_func { - pinctrl-single,pins = < - 0x0f8 0x0 /* UART4_CTS_N */ - 0x0fc 0x0 /* UART4_RTS_N */ - 0x100 0x0 /* UART4_RXD */ - 0x104 0x0 /* UART4_TXD */ - >; - pinctrl-single,bias-pulldown = < - PULL_DIS - PULL_DOWN - PULL_DIS - PULL_DOWN - >; - pinctrl-single,bias-pullup = < - PULL_DIS - PULL_UP - PULL_DIS - PULL_UP - >; - pinctrl-single,drive-strength = < - DRIVE7_02MA DRIVE6_MASK - >; - }; - - cam1_rst_cfg_func: cam1_rst_cfg_func { - pinctrl-single,pins = < - 0x130 0x0 /* CAM1_RST */ - >; - pinctrl-single,bias-pulldown = < - PULL_DIS - PULL_DOWN - PULL_DIS - PULL_DOWN - >; - pinctrl-single,bias-pullup = < - PULL_DIS - PULL_UP - PULL_DIS - PULL_UP - >; - pinctrl-single,drive-strength = < - DRIVE7_04MA DRIVE6_MASK - >; - }; - }; - - pmx6: pinmux@ff3b6800 { - compatible = "pinconf-single"; - reg = <0x0 0xff3b6800 0x0 0x18>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <0x20>; - - ufs_cfg_func: ufs_cfg_func { - pinctrl-single,pins = < - 0x000 0x0 /* UFS_REF_CLK */ - 0x004 0x0 /* UFS_RST_N */ - >; - pinctrl-single,bias-pulldown = < - PULL_DIS - PULL_DOWN - PULL_DIS - PULL_DOWN - >; - pinctrl-single,bias-pullup = < - PULL_DIS - PULL_UP - PULL_DIS - PULL_UP - >; - pinctrl-single,drive-strength = < - DRIVE7_08MA DRIVE6_MASK - >; - }; - - spi3_cfg_func: spi3_cfg_func { - pinctrl-single,pins = < - 0x008 0x0 /* SPI3_CLK */ - 0x0 /* SPI3_DI */ - 0x010 0x0 /* SPI3_DO */ - 0x014 0x0 /* SPI3_CS0_N */ - >; - pinctrl-single,bias-pulldown = < - PULL_DIS - PULL_DOWN - PULL_DIS - PULL_DOWN - >; - pinctrl-single,bias-pullup = < - PULL_DIS - PULL_UP - PULL_DIS - PULL_UP - >; - pinctrl-single,drive-strength = < - DRIVE7_02MA DRIVE6_MASK - >; - }; - }; - - pmx7: pinmux@ff3fd800 { - compatible = "pinconf-single"; - reg = <0x0 0xff3fd800 0x0 0x18>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <0x20>; - - sdio_clk_cfg_func: sdio_clk_cfg_func { - pinctrl-single,pins = < - 0x000 0x0 /* SDIO_CLK */ - >; - pinctrl-single,bias-pulldown = < - PULL_DIS - PULL_DOWN - PULL_DIS - PULL_DOWN - >; - pinctrl-single,bias-pullup = < - PULL_DIS - PULL_UP - PULL_DIS - PULL_UP - >; - pinctrl-single,drive-strength = < - DRIVE6_32MA DRIVE6_MASK - >; - }; - - sdio_cfg_func: sdio_cfg_func { - pinctrl-single,pins = < - 0x004 0x0 /* SDIO_CMD */ - 0x008 0x0 /* SDIO_DATA0 */ - 0x00c 0x0 /* SDIO_DATA1 */ - 0x010 0x0 /* SDIO_DATA2 */ - 0x014 0x0 /* SDIO_DATA3 */ - >; - pinctrl-single,bias-pulldown = < - PULL_DIS - PULL_DOWN - PULL_DIS - PULL_DOWN - >; - pinctrl-single,bias-pullup = < - PULL_UP - PULL_UP - PULL_DIS - PULL_UP - >; - pinctrl-single,drive-strength = < - DRIVE6_19MA DRIVE6_MASK - >; - }; - }; - - pmx8: pinmux@ff37e800 { - compatible = "pinconf-single"; - reg = <0x0 0xff37e800 0x0 0x18>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <0x20>; - - sd_clk_cfg_func: sd_clk_cfg_func { - pinctrl-single,pins = < - 0x000 0x0 /* SD_CLK */ - >; - pinctrl-single,bias-pulldown = < - PULL_DIS - PULL_DOWN - PULL_DIS - PULL_DOWN - >; - pinctrl-single,bias-pullup = < - PULL_DIS - PULL_UP - PULL_DIS - PULL_UP - >; - pinctrl-single,drive-strength = < - DRIVE6_32MA - DRIVE6_MASK - >; - }; - - sd_cfg_func: sd_cfg_func { - pinctrl-single,pins = < - 0x004 0x0 /* SD_CMD */ - 0x008 0x0 /* SD_DATA0 */ - 0x00c 0x0 /* SD_DATA1 */ - 0x010 0x0 /* SD_DATA2 */ - 0x014 0x0 /* SD_DATA3 */ - >; - pinctrl-single,bias-pulldown = < - PULL_DIS - PULL_DOWN - PULL_DIS - PULL_DOWN - >; - pinctrl-single,bias-pullup = < - PULL_UP - PULL_UP - PULL_DIS - PULL_UP - >; - pinctrl-single,drive-strength = < - DRIVE6_19MA - DRIVE6_MASK - >; - }; - }; - - pmx9: pinmux@fff11800 { - compatible = "pinconf-single"; - reg = <0x0 0xfff11800 0x0 0xbc>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <0x20>; - - i2c0_cfg_func: i2c0_cfg_func { - pinctrl-single,pins = < - 0x01c 0x0 /* I2C0_SCL */ - 0x020 0x0 /* I2C0_SDA */ - >; - pinctrl-single,bias-pulldown = < - PULL_DIS - PULL_DOWN - PULL_DIS - PULL_DOWN - >; - pinctrl-single,bias-pullup = < - PULL_UP - PULL_UP - PULL_DIS - PULL_UP - >; - pinctrl-single,drive-strength = < - DRIVE7_02MA DRIVE6_MASK - >; - }; - - i2c1_cfg_func: i2c1_cfg_func { - pinctrl-single,pins = < - 0x024 0x0 /* I2C1_SCL */ - 0x028 0x0 /* I2C1_SDA */ - >; - pinctrl-single,bias-pulldown = < - PULL_DIS - PULL_DOWN - PULL_DIS - PULL_DOWN - >; - pinctrl-single,bias-pullup = < - PULL_UP - PULL_UP - PULL_DIS - PULL_UP - >; - pinctrl-single,drive-strength = < - DRIVE7_02MA DRIVE6_MASK - >; - }; - - i2c7_cfg_func: i2c7_cfg_func { - pinctrl-single,pins = < - 0x02c 0x0 /* I2C7_SCL */ - 0x030 0x0 /* I2C7_SDA */ - >; - pinctrl-single,bias-pulldown = < - PULL_DIS - PULL_DOWN - PULL_DIS - PULL_DOWN - >; - pinctrl-single,bias-pullup = < - PULL_UP - PULL_UP - PULL_DIS - PULL_UP - >; - pinctrl-single,drive-strength = < - DRIVE7_02MA DRIVE6_MASK - >; - }; - - slimbus_cfg_func: slimbus_cfg_func { - pinctrl-single,pins = < - 0x034 0x0 /* SLIMBUS_CLK */ - 0x038 0x0 /* SLIMBUS_DATA */ - >; - pinctrl-single,bias-pulldown = < - PULL_DIS - PULL_DOWN - PULL_DIS - PULL_DOWN - >; - pinctrl-single,bias-pullup = < - PULL_UP - PULL_UP - PULL_DIS - PULL_UP - >; - pinctrl-single,drive-strength = < - DRIVE7_02MA DRIVE6_MASK - >; - }; - - i2s0_cfg_func: i2s0_cfg_func { - pinctrl-single,pins = < - 0x040 0x0 /* I2S0_DI */ - 0x044 0x0 /* I2S0_DO */ - 0x048 0x0 /* I2S0_XCLK */ - 0x04c 0x0 /* I2S0_XFS */ - >; - pinctrl-single,bias-pulldown = < - PULL_DIS - PULL_DOWN - PULL_DIS - PULL_DOWN - >; - pinctrl-single,bias-pullup = < - PULL_UP - PULL_UP - PULL_DIS - PULL_UP - >; - pinctrl-single,drive-strength = < - DRIVE7_02MA DRIVE6_MASK - >; - }; - - i2s2_cfg_func: i2s2_cfg_func { - pinctrl-single,pins = < - 0x050 0x0 /* I2S2_DI */ - 0x054 0x0 /* I2S2_DO */ - 0x058 0x0 /* I2S2_XCLK */ - 0x05c 0x0 /* I2S2_XFS */ - >; - pinctrl-single,bias-pulldown = < - PULL_DIS - PULL_DOWN - PULL_DIS - PULL_DOWN - >; - pinctrl-single,bias-pullup = < - PULL_UP - PULL_UP - PULL_DIS - PULL_UP - >; - pinctrl-single,drive-strength = < - DRIVE7_02MA DRIVE6_MASK - >; - }; - - pcie_cfg_func: pcie_cfg_func { - pinctrl-single,pins = < - 0x094 0x0 /* PCIE_CLKREQ_N */ - 0x098 0x0 /* PCIE_WAKE_N */ - >; - pinctrl-single,bias-pulldown = < - PULL_DIS - PULL_DOWN - PULL_DIS - PULL_DOWN - >; - pinctrl-single,bias-pullup = < - PULL_UP - PULL_UP - PULL_DIS - PULL_UP - >; - pinctrl-single,drive-strength = < - DRIVE7_02MA DRIVE6_MASK - >; - }; - - spi2_cfg_func: spi2_cfg_func { - pinctrl-single,pins = < - 0x09c 0x0 /* SPI2_CLK */ - 0x0a0 0x0 /* SPI2_DI */ - 0x0a4 0x0 /* SPI2_DO */ - 0x0a8 0x0 /* SPI2_CS0_N */ - >; - pinctrl-single,bias-pulldown = < - PULL_DIS - PULL_DOWN - PULL_DIS - PULL_DOWN - >; - pinctrl-single,bias-pullup = < - PULL_UP - PULL_UP - PULL_DIS - PULL_UP - >; - pinctrl-single,drive-strength = < - DRIVE7_02MA DRIVE6_MASK - >; - }; - - usb_cfg_func: usb_cfg_func { - pinctrl-single,pins = < - 0x0ac 0x0 /* GPIO_219 */ - >; - pinctrl-single,bias-pulldown = < - PULL_DIS - PULL_DOWN - PULL_DIS - PULL_DOWN - >; - pinctrl-single,bias-pullup = < - PULL_UP - PULL_UP - PULL_DIS - PULL_UP - >; - pinctrl-single,drive-strength = < - DRIVE7_02MA DRIVE6_MASK - >; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/hisilicon/hikey970-pinctrl.dtsi b/sys/gnu/dts/arm64/hisilicon/hikey970-pinctrl.dtsi deleted file mode 100644 index d456b0aa6f5..00000000000 --- a/sys/gnu/dts/arm64/hisilicon/hikey970-pinctrl.dtsi +++ /dev/null @@ -1,359 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Pinctrl dts file for HiSilicon HiKey970 development board - */ - -#include - -/ { - soc { - range: gpio-range { - #pinctrl-single,gpio-range-cells = <3>; - }; - - pmx0: pinmux@e896c000 { - compatible = "pinctrl-single"; - reg = <0x0 0xe896c000 0x0 0x72c>; - #pinctrl-cells = <1>; - #gpio-range-cells = <0x3>; - pinctrl-single,register-width = <0x20>; - pinctrl-single,function-mask = <0x7>; - /* pin base, nr pins & gpio function */ - pinctrl-single,gpio-range = <&range 0 82 0>; - - uart0_pmx_func: uart0_pmx_func { - pinctrl-single,pins = < - 0x054 MUX_M2 /* UART0_RXD */ - 0x058 MUX_M2 /* UART0_TXD */ - >; - }; - - uart2_pmx_func: uart2_pmx_func { - pinctrl-single,pins = < - 0x700 MUX_M2 /* UART2_CTS_N */ - 0x704 MUX_M2 /* UART2_RTS_N */ - 0x708 MUX_M2 /* UART2_RXD */ - 0x70c MUX_M2 /* UART2_TXD */ - >; - }; - - uart3_pmx_func: uart3_pmx_func { - pinctrl-single,pins = < - 0x064 MUX_M1 /* UART3_CTS_N */ - 0x068 MUX_M1 /* UART3_RTS_N */ - 0x06c MUX_M1 /* UART3_RXD */ - 0x070 MUX_M1 /* UART3_TXD */ - >; - }; - - uart4_pmx_func: uart4_pmx_func { - pinctrl-single,pins = < - 0x074 MUX_M1 /* UART4_CTS_N */ - 0x078 MUX_M1 /* UART4_RTS_N */ - 0x07c MUX_M1 /* UART4_RXD */ - 0x080 MUX_M1 /* UART4_TXD */ - >; - }; - - uart6_pmx_func: uart6_pmx_func { - pinctrl-single,pins = < - 0x05c MUX_M1 /* UART6_RXD */ - 0x060 MUX_M1 /* UART6_TXD */ - >; - }; - }; - - pmx2: pinmux@e896c800 { - compatible = "pinconf-single"; - reg = <0x0 0xe896c800 0x0 0x72c>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <0x20>; - - uart0_cfg_func: uart0_cfg_func { - pinctrl-single,pins = < - 0x058 0x0 /* UART0_RXD */ - 0x05c 0x0 /* UART0_TXD */ - >; - pinctrl-single,bias-pulldown = < - PULL_DIS - PULL_DOWN - PULL_DIS - PULL_DOWN - >; - pinctrl-single,bias-pullup = < - PULL_DIS - PULL_UP - PULL_DIS - PULL_UP - >; - pinctrl-single,drive-strength = < - DRIVE7_04MA DRIVE6_MASK - >; - }; - - uart2_cfg_func: uart2_cfg_func { - pinctrl-single,pins = < - 0x700 0x0 /* UART2_CTS_N */ - 0x704 0x0 /* UART2_RTS_N */ - 0x708 0x0 /* UART2_RXD */ - 0x70c 0x0 /* UART2_TXD */ - >; - pinctrl-single,bias-pulldown = < - PULL_DIS - PULL_DOWN - PULL_DIS - PULL_DOWN - >; - pinctrl-single,bias-pullup = < - PULL_DIS - PULL_UP - PULL_DIS - PULL_UP - >; - pinctrl-single,drive-strength = < - DRIVE7_04MA DRIVE6_MASK - >; - }; - - uart3_cfg_func: uart3_cfg_func { - pinctrl-single,pins = < - 0x068 0x0 /* UART3_CTS_N */ - 0x06c 0x0 /* UART3_RTS_N */ - 0x070 0x0 /* UART3_RXD */ - 0x074 0x0 /* UART3_TXD */ - >; - pinctrl-single,bias-pulldown = < - PULL_DIS - PULL_DOWN - PULL_DIS - PULL_DOWN - >; - pinctrl-single,bias-pullup = < - PULL_DIS - PULL_UP - PULL_DIS - PULL_UP - >; - pinctrl-single,drive-strength = < - DRIVE7_04MA DRIVE6_MASK - >; - }; - - uart4_cfg_func: uart4_cfg_func { - pinctrl-single,pins = < - 0x078 0x0 /* UART4_CTS_N */ - 0x07c 0x0 /* UART4_RTS_N */ - 0x080 0x0 /* UART4_RXD */ - 0x084 0x0 /* UART4_TXD */ - >; - pinctrl-single,bias-pulldown = < - PULL_DIS - PULL_DOWN - PULL_DIS - PULL_DOWN - >; - pinctrl-single,bias-pullup = < - PULL_DIS - PULL_UP - PULL_DIS - PULL_UP - >; - pinctrl-single,drive-strength = < - DRIVE7_04MA DRIVE6_MASK - >; - }; - - uart6_cfg_func: uart6_cfg_func { - pinctrl-single,pins = < - 0x060 0x0 /* UART6_RXD */ - 0x064 0x0 /* UART6_TXD */ - >; - pinctrl-single,bias-pulldown = < - PULL_DIS - PULL_DOWN - PULL_DIS - PULL_DOWN - >; - pinctrl-single,bias-pullup = < - PULL_DIS - PULL_UP - PULL_DIS - PULL_UP - >; - pinctrl-single,drive-strength = < - DRIVE7_02MA DRIVE6_MASK - >; - }; - }; - - pmx5: pinmux@fc182000 { - compatible = "pinctrl-single"; - reg = <0x0 0xfc182000 0x0 0x028>; - #gpio-range-cells = <3>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <0x20>; - pinctrl-single,function-mask = <0x7>; - /* pin base, nr pins & gpio function */ - pinctrl-single,gpio-range = <&range 0 10 0>; - - sdio_pmx_func: sdio_pmx_func { - pinctrl-single,pins = < - 0x000 MUX_M1 /* SDIO_CLK */ - 0x004 MUX_M1 /* SDIO_CMD */ - 0x008 MUX_M1 /* SDIO_DATA0 */ - 0x00c MUX_M1 /* SDIO_DATA1 */ - 0x010 MUX_M1 /* SDIO_DATA2 */ - 0x014 MUX_M1 /* SDIO_DATA3 */ - >; - }; - }; - - pmx6: pinmux@fc182800 { - compatible = "pinconf-single"; - reg = <0x0 0xfc182800 0x0 0x028>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <0x20>; - - sdio_clk_cfg_func: sdio_clk_cfg_func { - pinctrl-single,pins = < - 0x000 0x0 /* SDIO_CLK */ - >; - pinctrl-single,bias-pulldown = < - PULL_DIS - PULL_DOWN - PULL_DIS - PULL_DOWN - >; - pinctrl-single,bias-pullup = < - PULL_DIS - PULL_UP - PULL_DIS - PULL_UP - >; - pinctrl-single,drive-strength = < - DRIVE6_32MA DRIVE6_MASK - >; - }; - - sdio_cfg_func: sdio_cfg_func { - pinctrl-single,pins = < - 0x004 0x0 /* SDIO_CMD */ - 0x008 0x0 /* SDIO_DATA0 */ - 0x00c 0x0 /* SDIO_DATA1 */ - 0x010 0x0 /* SDIO_DATA2 */ - 0x014 0x0 /* SDIO_DATA3 */ - >; - pinctrl-single,bias-pulldown = < - PULL_DIS - PULL_DOWN - PULL_DIS - PULL_DOWN - >; - pinctrl-single,bias-pullup = < - PULL_UP - PULL_UP - PULL_DIS - PULL_UP - >; - pinctrl-single,drive-strength = < - DRIVE6_19MA DRIVE6_MASK - >; - }; - }; - - pmx7: pinmux@ff37e000 { - compatible = "pinctrl-single"; - reg = <0x0 0xff37e000 0x0 0x030>; - #gpio-range-cells = <3>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <0x20>; - pinctrl-single,function-mask = <7>; - /* pin base, nr pins & gpio function */ - pinctrl-single,gpio-range = <&range 0 12 0>; - - sd_pmx_func: sd_pmx_func { - pinctrl-single,pins = < - 0x000 MUX_M1 /* SD_CLK */ - 0x004 MUX_M1 /* SD_CMD */ - 0x008 MUX_M1 /* SD_DATA0 */ - 0x00c MUX_M1 /* SD_DATA1 */ - 0x010 MUX_M1 /* SD_DATA2 */ - 0x014 MUX_M1 /* SD_DATA3 */ - >; - }; - }; - - pmx8: pinmux@ff37e800 { - compatible = "pinconf-single"; - reg = <0x0 0xff37e800 0x0 0x030>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <0x20>; - - sd_clk_cfg_func: sd_clk_cfg_func { - pinctrl-single,pins = < - 0x000 0x0 /* SD_CLK */ - >; - pinctrl-single,bias-pulldown = < - PULL_DIS - PULL_DOWN - PULL_DIS - PULL_DOWN - >; - pinctrl-single,bias-pullup = < - PULL_DIS - PULL_UP - PULL_DIS - PULL_UP - >; - pinctrl-single,drive-strength = < - DRIVE6_32MA - DRIVE6_MASK - >; - }; - - sd_cfg_func: sd_cfg_func { - pinctrl-single,pins = < - 0x004 0x0 /* SD_CMD */ - 0x008 0x0 /* SD_DATA0 */ - 0x00c 0x0 /* SD_DATA1 */ - 0x010 0x0 /* SD_DATA2 */ - 0x014 0x0 /* SD_DATA3 */ - >; - pinctrl-single,bias-pulldown = < - PULL_DIS - PULL_DOWN - PULL_DIS - PULL_DOWN - >; - pinctrl-single,bias-pullup = < - PULL_UP - PULL_UP - PULL_DIS - PULL_UP - >; - pinctrl-single,drive-strength = < - DRIVE6_19MA - DRIVE6_MASK - >; - }; - }; - - pmx1: pinmux@fff11000 { - compatible = "pinctrl-single"; - reg = <0x0 0xfff11000 0x0 0x73c>; - #gpio-range-cells = <0x3>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <0x20>; - pinctrl-single,function-mask = <0x7>; - /* pin base, nr pins & gpio function */ - pinctrl-single,gpio-range = <&range 0 46 0>; - }; - - pmx16: pinmux@fff11800 { - compatible = "pinconf-single"; - reg = <0x0 0xfff11800 0x0 0x73c>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <0x20>; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/hisilicon/hip05-d02.dts b/sys/gnu/dts/arm64/hisilicon/hip05-d02.dts deleted file mode 100644 index e93c65ede06..00000000000 --- a/sys/gnu/dts/arm64/hisilicon/hip05-d02.dts +++ /dev/null @@ -1,84 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/** - * dts file for Hisilicon D02 Development Board - * - * Copyright (C) 2014,2015 Hisilicon Ltd. - */ - -/dts-v1/; - -#include -#include "hip05.dtsi" - -/ { - model = "Hisilicon Hip05 D02 Development Board"; - compatible = "hisilicon,hip05-d02"; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x00000000 0x0 0x80000000>; - }; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - pwrbutton { - label = "Power Button"; - gpios = <&porta 8 GPIO_ACTIVE_LOW>; - linux,code = <116>; - debounce-interval = <0>; - }; - }; -}; - -&uart0 { - status = "ok"; -}; - -&peri_gpio0 { - status = "ok"; -}; - -&lbc { - status = "ok"; - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0x0 0x90000000 0x08000000>, - <1 0 0x0 0x98000000 0x08000000>; - - nor-flash@0,0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "numonyx,js28f00a", "cfi-flash"; - reg = <0 0x0 0x08000000>; - bank-width = <2>; - /* The three parts may not used */ - partition@0 { - label = "BIOS"; - reg = <0x0 0x300000>; - }; - partition@300000 { - label = "Linux"; - reg = <0x300000 0xa00000>; - }; - partition@1000000 { - label = "Rootfs"; - reg = <0x01000000 0x02000000>; - }; - }; - - cpld@1,0 { - compatible = "hisilicon,hip05-cpld"; - reg = <1 0x0 0x100>; - }; -}; diff --git a/sys/gnu/dts/arm64/hisilicon/hip05.dtsi b/sys/gnu/dts/arm64/hisilicon/hip05.dtsi deleted file mode 100644 index bc49955360d..00000000000 --- a/sys/gnu/dts/arm64/hisilicon/hip05.dtsi +++ /dev/null @@ -1,365 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/** - * dts file for Hisilicon D02 Development Board - * - * Copyright (C) 2014,2015 Hisilicon Ltd. - */ - -#include - -/ { - compatible = "hisilicon,hip05-d02"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu-map { - cluster0 { - core0 { - cpu = <&cpu0>; - }; - core1 { - cpu = <&cpu1>; - }; - core2 { - cpu = <&cpu2>; - }; - core3 { - cpu = <&cpu3>; - }; - }; - cluster1 { - core0 { - cpu = <&cpu4>; - }; - core1 { - cpu = <&cpu5>; - }; - core2 { - cpu = <&cpu6>; - }; - core3 { - cpu = <&cpu7>; - }; - }; - cluster2 { - core0 { - cpu = <&cpu8>; - }; - core1 { - cpu = <&cpu9>; - }; - core2 { - cpu = <&cpu10>; - }; - core3 { - cpu = <&cpu11>; - }; - }; - cluster3 { - core0 { - cpu = <&cpu12>; - }; - core1 { - cpu = <&cpu13>; - }; - core2 { - cpu = <&cpu14>; - }; - core3 { - cpu = <&cpu15>; - }; - }; - }; - - cpu0: cpu@20000 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x20000>; - enable-method = "psci"; - next-level-cache = <&cluster0_l2>; - }; - - cpu1: cpu@20001 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x20001>; - enable-method = "psci"; - next-level-cache = <&cluster0_l2>; - }; - - cpu2: cpu@20002 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x20002>; - enable-method = "psci"; - next-level-cache = <&cluster0_l2>; - }; - - cpu3: cpu@20003 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x20003>; - enable-method = "psci"; - next-level-cache = <&cluster0_l2>; - }; - - cpu4: cpu@20100 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x20100>; - enable-method = "psci"; - next-level-cache = <&cluster1_l2>; - }; - - cpu5: cpu@20101 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x20101>; - enable-method = "psci"; - next-level-cache = <&cluster1_l2>; - }; - - cpu6: cpu@20102 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x20102>; - enable-method = "psci"; - next-level-cache = <&cluster1_l2>; - }; - - cpu7: cpu@20103 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x20103>; - enable-method = "psci"; - next-level-cache = <&cluster1_l2>; - }; - - cpu8: cpu@20200 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x20200>; - enable-method = "psci"; - next-level-cache = <&cluster2_l2>; - }; - - cpu9: cpu@20201 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x20201>; - enable-method = "psci"; - next-level-cache = <&cluster2_l2>; - }; - - cpu10: cpu@20202 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x20202>; - enable-method = "psci"; - next-level-cache = <&cluster2_l2>; - }; - - cpu11: cpu@20203 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x20203>; - enable-method = "psci"; - next-level-cache = <&cluster2_l2>; - }; - - cpu12: cpu@20300 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x20300>; - enable-method = "psci"; - next-level-cache = <&cluster3_l2>; - }; - - cpu13: cpu@20301 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x20301>; - enable-method = "psci"; - next-level-cache = <&cluster3_l2>; - }; - - cpu14: cpu@20302 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x20302>; - enable-method = "psci"; - next-level-cache = <&cluster3_l2>; - }; - - cpu15: cpu@20303 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x20303>; - enable-method = "psci"; - next-level-cache = <&cluster3_l2>; - }; - - cluster0_l2: l2-cache0 { - compatible = "cache"; - }; - - cluster1_l2: l2-cache1 { - compatible = "cache"; - }; - - cluster2_l2: l2-cache2 { - compatible = "cache"; - }; - - cluster3_l2: l2-cache3 { - compatible = "cache"; - }; - }; - - gic: interrupt-controller@8d000000 { - compatible = "arm,gic-v3"; - #interrupt-cells = <3>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - interrupt-controller; - #redistributor-regions = <1>; - redistributor-stride = <0x0 0x30000>; - reg = <0x0 0x8d000000 0 0x10000>, /* GICD */ - <0x0 0x8d100000 0 0x300000>, /* GICR */ - <0x0 0xfe000000 0 0x10000>, /* GICC */ - <0x0 0xfe010000 0 0x10000>, /* GICH */ - <0x0 0xfe020000 0 0x10000>; /* GICV */ - interrupts = ; - - its_peri: interrupt-controller@8c000000 { - compatible = "arm,gic-v3-its"; - msi-controller; - #msi-cells = <1>; - reg = <0x0 0x8c000000 0x0 0x40000>; - }; - - its_m3: interrupt-controller@a3000000 { - compatible = "arm,gic-v3-its"; - msi-controller; - #msi-cells = <1>; - reg = <0x0 0xa3000000 0x0 0x40000>; - }; - - its_pcie: interrupt-controller@b7000000 { - compatible = "arm,gic-v3-its"; - msi-controller; - #msi-cells = <1>; - reg = <0x0 0xb7000000 0x0 0x40000>; - }; - - its_dsa: interrupt-controller@c6000000 { - compatible = "arm,gic-v3-its"; - msi-controller; - #msi-cells = <1>; - reg = <0x0 0xc6000000 0x0 0x40000>; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - pmu { - compatible = "arm,cortex-a57-pmu"; - interrupts = ; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - refclk200mhz: refclk200mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <200000000>; - }; - - uart0: uart@80300000 { - compatible = "snps,dw-apb-uart"; - reg = <0x0 0x80300000 0x0 0x10000>; - interrupts = ; - clocks = <&refclk200mhz>; - clock-names = "apb_pclk"; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uart1: uart@80310000 { - compatible = "snps,dw-apb-uart"; - reg = <0x0 0x80310000 0x0 0x10000>; - interrupts = ; - clocks = <&refclk200mhz>; - clock-names = "apb_pclk"; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - lbc: localbus@80380000 { - compatible = "hisilicon,hisi-localbus", "simple-bus"; - reg = <0x0 0x80380000 0x0 0x10000>; - status = "disabled"; - }; - - peri_gpio0: gpio@802e0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dw-apb-gpio"; - reg = <0x0 0x802e0000 0x0 0x10000>; - status = "disabled"; - - porta: gpio-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <32>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = ; - }; - }; - - peri_gpio1: gpio@802f0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dw-apb-gpio"; - reg = <0x0 0x802f0000 0x0 0x10000>; - status = "disabled"; - - portb: gpio-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <32>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = ; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/hisilicon/hip06-d03.dts b/sys/gnu/dts/arm64/hisilicon/hip06-d03.dts deleted file mode 100644 index 677862beebe..00000000000 --- a/sys/gnu/dts/arm64/hisilicon/hip06-d03.dts +++ /dev/null @@ -1,58 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/** - * dts file for Hisilicon D03 Development Board - * - * Copyright (C) 2016 Hisilicon Ltd. - */ - -/dts-v1/; - -#include "hip06.dtsi" - -/ { - model = "Hisilicon Hip06 D03 Development Board"; - compatible = "hisilicon,hip06-d03"; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x00000000 0x0 0x40000000>; - }; - - chosen { }; -}; - -&ipmi0 { - status = "ok"; -}; - -&uart0 { - status = "ok"; -}; - -ð0 { - status = "ok"; -}; - -ð1 { - status = "ok"; -}; - -ð2 { - status = "ok"; -}; - -ð3 { - status = "ok"; -}; - -&sas1 { - status = "ok"; -}; - -&usb_ohci { - status = "ok"; -}; - -&usb_ehci { - status = "ok"; -}; diff --git a/sys/gnu/dts/arm64/hisilicon/hip06.dtsi b/sys/gnu/dts/arm64/hisilicon/hip06.dtsi deleted file mode 100644 index 50ceaa959bd..00000000000 --- a/sys/gnu/dts/arm64/hisilicon/hip06.dtsi +++ /dev/null @@ -1,754 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/** - * dts file for Hisilicon D03 Development Board - * - * Copyright (C) 2016 Hisilicon Ltd. - */ - -#include - -/ { - compatible = "hisilicon,hip06-d03"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu-map { - cluster0 { - core0 { - cpu = <&cpu0>; - }; - core1 { - cpu = <&cpu1>; - }; - core2 { - cpu = <&cpu2>; - }; - core3 { - cpu = <&cpu3>; - }; - }; - cluster1 { - core0 { - cpu = <&cpu4>; - }; - core1 { - cpu = <&cpu5>; - }; - core2 { - cpu = <&cpu6>; - }; - core3 { - cpu = <&cpu7>; - }; - }; - cluster2 { - core0 { - cpu = <&cpu8>; - }; - core1 { - cpu = <&cpu9>; - }; - core2 { - cpu = <&cpu10>; - }; - core3 { - cpu = <&cpu11>; - }; - }; - cluster3 { - core0 { - cpu = <&cpu12>; - }; - core1 { - cpu = <&cpu13>; - }; - core2 { - cpu = <&cpu14>; - }; - core3 { - cpu = <&cpu15>; - }; - }; - }; - - cpu0: cpu@10000 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x10000>; - enable-method = "psci"; - next-level-cache = <&cluster0_l2>; - }; - - cpu1: cpu@10001 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x10001>; - enable-method = "psci"; - next-level-cache = <&cluster0_l2>; - }; - - cpu2: cpu@10002 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x10002>; - enable-method = "psci"; - next-level-cache = <&cluster0_l2>; - }; - - cpu3: cpu@10003 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x10003>; - enable-method = "psci"; - next-level-cache = <&cluster0_l2>; - }; - - cpu4: cpu@10100 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x10100>; - enable-method = "psci"; - next-level-cache = <&cluster1_l2>; - }; - - cpu5: cpu@10101 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x10101>; - enable-method = "psci"; - next-level-cache = <&cluster1_l2>; - }; - - cpu6: cpu@10102 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x10102>; - enable-method = "psci"; - next-level-cache = <&cluster1_l2>; - }; - - cpu7: cpu@10103 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x10103>; - enable-method = "psci"; - next-level-cache = <&cluster1_l2>; - }; - - cpu8: cpu@10200 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x10200>; - enable-method = "psci"; - next-level-cache = <&cluster2_l2>; - }; - - cpu9: cpu@10201 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x10201>; - enable-method = "psci"; - next-level-cache = <&cluster2_l2>; - }; - - cpu10: cpu@10202 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x10202>; - enable-method = "psci"; - next-level-cache = <&cluster2_l2>; - }; - - cpu11: cpu@10203 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x10203>; - enable-method = "psci"; - next-level-cache = <&cluster2_l2>; - }; - - cpu12: cpu@10300 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x10300>; - enable-method = "psci"; - next-level-cache = <&cluster3_l2>; - }; - - cpu13: cpu@10301 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x10301>; - enable-method = "psci"; - next-level-cache = <&cluster3_l2>; - }; - - cpu14: cpu@10302 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x10302>; - enable-method = "psci"; - next-level-cache = <&cluster3_l2>; - }; - - cpu15: cpu@10303 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x10303>; - enable-method = "psci"; - next-level-cache = <&cluster3_l2>; - }; - - cluster0_l2: l2-cache0 { - compatible = "cache"; - }; - - cluster1_l2: l2-cache1 { - compatible = "cache"; - }; - - cluster2_l2: l2-cache2 { - compatible = "cache"; - }; - - cluster3_l2: l2-cache3 { - compatible = "cache"; - }; - }; - - gic: interrupt-controller@4d000000 { - compatible = "arm,gic-v3"; - #interrupt-cells = <3>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - interrupt-controller; - #redistributor-regions = <1>; - redistributor-stride = <0x0 0x30000>; - reg = <0x0 0x4d000000 0 0x10000>, /* GICD */ - <0x0 0x4d100000 0 0x300000>, /* GICR */ - <0x0 0xfe000000 0 0x10000>, /* GICC */ - <0x0 0xfe010000 0 0x10000>, /* GICH */ - <0x0 0xfe020000 0 0x10000>; /* GICV */ - interrupts = ; - - its_dsa: interrupt-controller@c6000000 { - compatible = "arm,gic-v3-its"; - msi-controller; - #msi-cells = <1>; - reg = <0x0 0xc6000000 0x0 0x40000>; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - pmu { - compatible = "arm,cortex-a57-pmu"; - interrupts = ; - }; - - mbigen_pcie@a0080000 { - compatible = "hisilicon,mbigen-v2"; - reg = <0x0 0xa0080000 0x0 0x10000>; - - mbigen_usb: intc_usb { - msi-parent = <&its_dsa 0x40080>; - interrupt-controller; - #interrupt-cells = <2>; - num-pins = <2>; - }; - - mbigen_sas1: intc_sas1 { - msi-parent = <&its_dsa 0x40000>; - interrupt-controller; - #interrupt-cells = <2>; - num-pins = <128>; - }; - - mbigen_sas2: intc_sas2 { - msi-parent = <&its_dsa 0x40040>; - interrupt-controller; - #interrupt-cells = <2>; - num-pins = <128>; - }; - - mbigen_pcie0: intc_pcie0 { - msi-parent = <&its_dsa 0x40085>; - interrupt-controller; - #interrupt-cells = <2>; - num-pins = <10>; - }; - }; - - mbigen_dsa@c0080000 { - compatible = "hisilicon,mbigen-v2"; - reg = <0x0 0xc0080000 0x0 0x10000>; - - mbigen_dsaf0: intc_dsaf0 { - msi-parent = <&its_dsa 0x40800>; - interrupt-controller; - #interrupt-cells = <2>; - num-pins = <409>; - }; - - mbigen_sas0: intc-sas0 { - msi-parent = <&its_dsa 0x40900>; - interrupt-controller; - #interrupt-cells = <2>; - num-pins = <128>; - }; - }; - - /** - * HiSilicon erratum 161010801: This describes the limitation - * of HiSilicon platforms hip06/hip07 to support the SMMUv3 - * mappings for PCIe MSI transactions. - * PCIe controller on these platforms has to differentiate the - * MSI payload against other DMA payload and has to modify the - * MSI payload. This makes it difficult for these platforms to - * have a SMMU translation for MSI. In order to workaround this, - * ARM SMMUv3 driver requires a quirk to treat the MSI regions - * separately. Such a quirk is currently missing for DT based - * systems. Hence please make sure that the smmu pcie node on - * hip06 is disabled as this will break the PCIe functionality - * when iommu-map entry is used along with the PCIe node. - * Refer:https://www.spinics.net/lists/arm-kernel/msg602812.html - */ - smmu0: smmu_pcie { - compatible = "arm,smmu-v3"; - reg = <0x0 0xa0040000 0x0 0x20000>; - #iommu-cells = <1>; - dma-coherent; - smmu-cb-memtype = <0x0 0x1>; - hisilicon,broken-prefetch-cmd; - status = "disabled"; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - isa@a01b0000 { - compatible = "hisilicon,hip06-lpc"; - #size-cells = <1>; - #address-cells = <2>; - reg = <0x0 0xa01b0000 0x0 0x1000>; - - ipmi0: bt@e4 { - compatible = "ipmi-bt"; - device_type = "ipmi"; - reg = <0x01 0xe4 0x04>; - status = "disabled"; - }; - - uart0: lpc-uart@2f8 { - compatible = "ns16550a"; - clock-frequency = <1843200>; - reg = <0x01 0x2f8 0x08>; - status = "disabled"; - }; - }; - - refclk: refclk { - compatible = "fixed-clock"; - clock-frequency = <50000000>; - #clock-cells = <0>; - }; - - usb_ohci: ohci@a7030000 { - compatible = "generic-ohci"; - reg = <0x0 0xa7030000 0x0 0x10000>; - interrupt-parent = <&mbigen_usb>; - interrupts = <640 4>; - dma-coherent; - status = "disabled"; - }; - - usb_ehci: ehci@a7020000 { - compatible = "generic-ehci"; - reg = <0x0 0xa7020000 0x0 0x10000>; - interrupt-parent = <&mbigen_usb>; - interrupts = <641 4>; - dma-coherent; - status = "disabled"; - }; - - peri_c_subctrl: sub_ctrl_c@60000000 { - compatible = "hisilicon,peri-subctrl","syscon"; - reg = <0 0x60000000 0x0 0x10000>; - }; - - dsa_subctrl: dsa_subctrl@c0000000 { - compatible = "hisilicon,dsa-subctrl", "syscon"; - reg = <0x0 0xc0000000 0x0 0x10000>; - }; - - pcie_subctl: pcie_subctl@a0000000 { - compatible = "hisilicon,pcie-sas-subctrl", "syscon"; - reg = <0x0 0xa0000000 0x0 0x10000>; - }; - - serdes_ctrl: sds_ctrl@c2200000 { - compatible = "syscon"; - reg = <0 0xc2200000 0x0 0x80000>; - }; - - mdio@603c0000 { - compatible = "hisilicon,hns-mdio"; - reg = <0x0 0x603c0000 0x0 0x1000>; - subctrl-vbase = <&peri_c_subctrl 0x338 0xa38 0x531c 0x5a1c>; - #address-cells = <1>; - #size-cells = <0>; - - phy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - }; - - phy1: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; - }; - - dsaf0: dsa@c7000000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "hisilicon,hns-dsaf-v2"; - mode = "6port-16rss"; - reg = <0x0 0xc5000000 0x0 0x890000 - 0x0 0xc7000000 0x0 0x600000>; - reg-names = "ppe-base", "dsaf-base"; - interrupt-parent = <&mbigen_dsaf0>; - subctrl-syscon = <&dsa_subctrl>; - reset-field-offset = <0>; - interrupts = - <576 1>, <577 1>, <578 1>, <579 1>, <580 1>, - <581 1>, <582 1>, <583 1>, <584 1>, <585 1>, - <586 1>, <587 1>, <588 1>, <589 1>, <590 1>, - <591 1>, <592 1>, <593 1>, <594 1>, <595 1>, - <596 1>, <597 1>, <598 1>, <599 1>, <600 1>, - <960 1>, <961 1>, <962 1>, <963 1>, <964 1>, - <965 1>, <966 1>, <967 1>, <968 1>, <969 1>, - <970 1>, <971 1>, <972 1>, <973 1>, <974 1>, - <975 1>, <976 1>, <977 1>, <978 1>, <979 1>, - <980 1>, <981 1>, <982 1>, <983 1>, <984 1>, - <985 1>, <986 1>, <987 1>, <988 1>, <989 1>, - <990 1>, <991 1>, <992 1>, <993 1>, <994 1>, - <995 1>, <996 1>, <997 1>, <998 1>, <999 1>, - <1000 1>, <1001 1>, <1002 1>, <1003 1>, <1004 1>, - <1005 1>, <1006 1>, <1007 1>, <1008 1>, <1009 1>, - <1010 1>, <1011 1>, <1012 1>, <1013 1>, <1014 1>, - <1015 1>, <1016 1>, <1017 1>, <1018 1>, <1019 1>, - <1020 1>, <1021 1>, <1022 1>, <1023 1>, <1024 1>, - <1025 1>, <1026 1>, <1027 1>, <1028 1>, <1029 1>, - <1030 1>, <1031 1>, <1032 1>, <1033 1>, <1034 1>, - <1035 1>, <1036 1>, <1037 1>, <1038 1>, <1039 1>, - <1040 1>, <1041 1>, <1042 1>, <1043 1>, <1044 1>, - <1045 1>, <1046 1>, <1047 1>, <1048 1>, <1049 1>, - <1050 1>, <1051 1>, <1052 1>, <1053 1>, <1054 1>, - <1055 1>, <1056 1>, <1057 1>, <1058 1>, <1059 1>, - <1060 1>, <1061 1>, <1062 1>, <1063 1>, <1064 1>, - <1065 1>, <1066 1>, <1067 1>, <1068 1>, <1069 1>, - <1070 1>, <1071 1>, <1072 1>, <1073 1>, <1074 1>, - <1075 1>, <1076 1>, <1077 1>, <1078 1>, <1079 1>, - <1080 1>, <1081 1>, <1082 1>, <1083 1>, <1084 1>, - <1085 1>, <1086 1>, <1087 1>, <1088 1>, <1089 1>, - <1090 1>, <1091 1>, <1092 1>, <1093 1>, <1094 1>, - <1095 1>, <1096 1>, <1097 1>, <1098 1>, <1099 1>, - <1100 1>, <1101 1>, <1102 1>, <1103 1>, <1104 1>, - <1105 1>, <1106 1>, <1107 1>, <1108 1>, <1109 1>, - <1110 1>, <1111 1>, <1112 1>, <1113 1>, <1114 1>, - <1115 1>, <1116 1>, <1117 1>, <1118 1>, <1119 1>, - <1120 1>, <1121 1>, <1122 1>, <1123 1>, <1124 1>, - <1125 1>, <1126 1>, <1127 1>, <1128 1>, <1129 1>, - <1130 1>, <1131 1>, <1132 1>, <1133 1>, <1134 1>, - <1135 1>, <1136 1>, <1137 1>, <1138 1>, <1139 1>, - <1140 1>, <1141 1>, <1142 1>, <1143 1>, <1144 1>, - <1145 1>, <1146 1>, <1147 1>, <1148 1>, <1149 1>, - <1150 1>, <1151 1>, <1152 1>, <1153 1>, <1154 1>, - <1155 1>, <1156 1>, <1157 1>, <1158 1>, <1159 1>, - <1160 1>, <1161 1>, <1162 1>, <1163 1>, <1164 1>, - <1165 1>, <1166 1>, <1167 1>, <1168 1>, <1169 1>, - <1170 1>, <1171 1>, <1172 1>, <1173 1>, <1174 1>, - <1175 1>, <1176 1>, <1177 1>, <1178 1>, <1179 1>, - <1180 1>, <1181 1>, <1182 1>, <1183 1>, <1184 1>, - <1185 1>, <1186 1>, <1187 1>, <1188 1>, <1189 1>, - <1190 1>, <1191 1>, <1192 1>, <1193 1>, <1194 1>, - <1195 1>, <1196 1>, <1197 1>, <1198 1>, <1199 1>, - <1200 1>, <1201 1>, <1202 1>, <1203 1>, <1204 1>, - <1205 1>, <1206 1>, <1207 1>, <1208 1>, <1209 1>, - <1210 1>, <1211 1>, <1212 1>, <1213 1>, <1214 1>, - <1215 1>, <1216 1>, <1217 1>, <1218 1>, <1219 1>, - <1220 1>, <1221 1>, <1222 1>, <1223 1>, <1224 1>, - <1225 1>, <1226 1>, <1227 1>, <1228 1>, <1229 1>, - <1230 1>, <1231 1>, <1232 1>, <1233 1>, <1234 1>, - <1235 1>, <1236 1>, <1237 1>, <1238 1>, <1239 1>, - <1240 1>, <1241 1>, <1242 1>, <1243 1>, <1244 1>, - <1245 1>, <1246 1>, <1247 1>, <1248 1>, <1249 1>, - <1250 1>, <1251 1>, <1252 1>, <1253 1>, <1254 1>, - <1255 1>, <1256 1>, <1257 1>, <1258 1>, <1259 1>, - <1260 1>, <1261 1>, <1262 1>, <1263 1>, <1264 1>, - <1265 1>, <1266 1>, <1267 1>, <1268 1>, <1269 1>, - <1270 1>, <1271 1>, <1272 1>, <1273 1>, <1274 1>, - <1275 1>, <1276 1>, <1277 1>, <1278 1>, <1279 1>, - <1280 1>, <1281 1>, <1282 1>, <1283 1>, <1284 1>, - <1285 1>, <1286 1>, <1287 1>, <1288 1>, <1289 1>, - <1290 1>, <1291 1>, <1292 1>, <1293 1>, <1294 1>, - <1295 1>, <1296 1>, <1297 1>, <1298 1>, <1299 1>, - <1300 1>, <1301 1>, <1302 1>, <1303 1>, <1304 1>, - <1305 1>, <1306 1>, <1307 1>, <1308 1>, <1309 1>, - <1310 1>, <1311 1>, <1312 1>, <1313 1>, <1314 1>, - <1315 1>, <1316 1>, <1317 1>, <1318 1>, <1319 1>, - <1320 1>, <1321 1>, <1322 1>, <1323 1>, <1324 1>, - <1325 1>, <1326 1>, <1327 1>, <1328 1>, <1329 1>, - <1330 1>, <1331 1>, <1332 1>, <1333 1>, <1334 1>, - <1335 1>, <1336 1>, <1337 1>, <1338 1>, <1339 1>, - <1340 1>, <1341 1>, <1342 1>, <1343 1>; - - desc-num = <0x400>; - buf-size = <0x1000>; - dma-coherent; - - port@0 { - reg = <0>; - serdes-syscon = <&serdes_ctrl>; - port-rst-offset = <0>; - port-mode-offset = <0>; - media-type = "fiber"; - }; - - port@1 { - reg = <1>; - serdes-syscon= <&serdes_ctrl>; - port-rst-offset = <1>; - port-mode-offset = <1>; - media-type = "fiber"; - }; - - port@4 { - reg = <4>; - phy-handle = <&phy0>; - serdes-syscon= <&serdes_ctrl>; - port-rst-offset = <4>; - port-mode-offset = <2>; - media-type = "copper"; - }; - - port@5 { - reg = <5>; - phy-handle = <&phy1>; - serdes-syscon= <&serdes_ctrl>; - port-rst-offset = <5>; - port-mode-offset = <3>; - media-type = "copper"; - }; - }; - - eth0: ethernet-4{ - compatible = "hisilicon,hns-nic-v2"; - ae-handle = <&dsaf0>; - port-idx-in-ae = <4>; - local-mac-address = [00 00 00 00 00 00]; - status = "disabled"; - dma-coherent; - }; - - eth1: ethernet-5{ - compatible = "hisilicon,hns-nic-v2"; - ae-handle = <&dsaf0>; - port-idx-in-ae = <5>; - local-mac-address = [00 00 00 00 00 00]; - status = "disabled"; - dma-coherent; - }; - - eth2: ethernet-0{ - compatible = "hisilicon,hns-nic-v2"; - ae-handle = <&dsaf0>; - port-idx-in-ae = <0>; - local-mac-address = [00 00 00 00 00 00]; - status = "disabled"; - dma-coherent; - }; - - eth3: ethernet-1{ - compatible = "hisilicon,hns-nic-v2"; - ae-handle = <&dsaf0>; - port-idx-in-ae = <1>; - local-mac-address = [00 00 00 00 00 00]; - status = "disabled"; - dma-coherent; - }; - - sas0: sas@c3000000 { - compatible = "hisilicon,hip06-sas-v2"; - reg = <0 0xc3000000 0 0x10000>; - sas-addr = [50 01 88 20 16 00 00 00]; - hisilicon,sas-syscon = <&dsa_subctrl>; - ctrl-reset-reg = <0xa60>; - ctrl-reset-sts-reg = <0x5a30>; - ctrl-clock-ena-reg = <0x338>; - clocks = <&refclk 0>; - queue-count = <16>; - phy-count = <8>; - dma-coherent; - interrupt-parent = <&mbigen_sas0>; - interrupts = <64 4>,<65 4>,<66 4>,<67 4>,<68 4>, - <69 4>,<70 4>,<71 4>,<72 4>,<73 4>, - <75 4>,<76 4>,<77 4>,<78 4>,<79 4>, - <80 4>,<81 4>,<82 4>,<83 4>,<84 4>, - <85 4>,<86 4>,<87 4>,<88 4>,<89 4>, - <90 4>,<91 4>,<92 4>,<93 4>,<94 4>, - <95 4>,<96 4>,<97 4>,<98 4>,<99 4>, - <100 4>,<101 4>,<102 4>,<103 4>,<104 4>, - <105 4>,<106 4>,<107 4>,<108 4>,<109 4>, - <110 4>,<111 4>,<112 4>,<113 4>,<114 4>, - <115 4>,<116 4>,<117 4>,<118 4>,<119 4>, - <120 4>,<121 4>,<122 4>,<123 4>,<124 4>, - <125 4>,<126 4>,<127 4>,<128 4>,<129 4>, - <130 4>,<131 4>,<132 4>,<133 4>,<134 4>, - <135 4>,<136 4>,<137 4>,<138 4>,<139 4>, - <140 4>,<141 4>,<142 4>,<143 4>,<144 4>, - <145 4>,<146 4>,<147 4>,<148 4>,<149 4>, - <150 4>,<151 4>,<152 4>,<153 4>,<154 4>, - <155 4>,<156 4>,<157 4>,<158 4>,<159 4>, - <160 4>,<601 1>,<602 1>,<603 1>,<604 1>, - <605 1>,<606 1>,<607 1>,<608 1>,<609 1>, - <610 1>,<611 1>,<612 1>,<613 1>,<614 1>, - <615 1>,<616 1>,<617 1>,<618 1>,<619 1>, - <620 1>,<621 1>,<622 1>,<623 1>,<624 1>, - <625 1>,<626 1>,<627 1>,<628 1>,<629 1>, - <630 1>,<631 1>,<632 1>; - status = "disabled"; - }; - - sas1: sas@a2000000 { - compatible = "hisilicon,hip06-sas-v2"; - reg = <0 0xa2000000 0 0x10000>; - sas-addr = [50 01 88 20 16 00 00 00]; - hisilicon,sas-syscon = <&pcie_subctl>; - hip06-sas-v2-quirk-amt; - ctrl-reset-reg = <0xa18>; - ctrl-reset-sts-reg = <0x5a0c>; - ctrl-clock-ena-reg = <0x318>; - clocks = <&refclk 0>; - queue-count = <16>; - phy-count = <8>; - dma-coherent; - interrupt-parent = <&mbigen_sas1>; - interrupts = <64 4>,<65 4>,<66 4>,<67 4>,<68 4>, - <69 4>,<70 4>,<71 4>,<72 4>,<73 4>, - <74 4>,<75 4>,<76 4>,<77 4>,<78 4>, - <79 4>,<80 4>,<81 4>,<82 4>,<83 4>, - <84 4>,<85 4>,<86 4>,<87 4>,<88 4>, - <89 4>,<90 4>,<91 4>,<92 4>,<93 4>, - <94 4>,<95 4>,<96 4>,<97 4>,<98 4>, - <99 4>,<100 4>,<101 4>,<102 4>,<103 4>, - <104 4>,<105 4>,<106 4>,<107 4>,<108 4>, - <109 4>,<110 4>,<111 4>,<112 4>,<113 4>, - <114 4>,<115 4>,<116 4>,<117 4>,<118 4>, - <119 4>,<120 4>,<121 4>,<122 4>,<123 4>, - <124 4>,<125 4>,<126 4>,<127 4>,<128 4>, - <129 4>,<130 4>,<131 4>,<132 4>,<133 4>, - <134 4>,<135 4>,<136 4>,<137 4>,<138 4>, - <139 4>,<140 4>,<141 4>,<142 4>,<143 4>, - <144 4>,<145 4>,<146 4>,<147 4>,<148 4>, - <149 4>,<150 4>,<151 4>,<152 4>,<153 4>, - <154 4>,<155 4>,<156 4>,<157 4>,<158 4>, - <159 4>,<576 1>,<577 1>,<578 1>,<579 1>, - <580 1>,<581 1>,<582 1>,<583 1>,<584 1>, - <585 1>,<586 1>,<587 1>,<588 1>,<589 1>, - <590 1>,<591 1>,<592 1>,<593 1>,<594 1>, - <595 1>,<596 1>,<597 1>,<598 1>,<599 1>, - <600 1>,<601 1>,<602 1>,<603 1>,<604 1>, - <605 1>,<606 1>,<607 1>; - status = "disabled"; - }; - - sas2: sas@a3000000 { - compatible = "hisilicon,hip06-sas-v2"; - reg = <0 0xa3000000 0 0x10000>; - sas-addr = [50 01 88 20 16 00 00 00]; - hisilicon,sas-syscon = <&pcie_subctl>; - ctrl-reset-reg = <0xae0>; - ctrl-reset-sts-reg = <0x5a70>; - ctrl-clock-ena-reg = <0x3a8>; - clocks = <&refclk 0>; - queue-count = <16>; - phy-count = <9>; - dma-coherent; - interrupt-parent = <&mbigen_sas2>; - interrupts = <192 4>,<193 4>,<194 4>,<195 4>,<196 4>, - <197 4>,<198 4>,<199 4>,<200 4>,<201 4>, - <202 4>,<203 4>,<204 4>,<205 4>,<206 4>, - <207 4>,<208 4>,<209 4>,<210 4>,<211 4>, - <212 4>,<213 4>,<214 4>,<215 4>,<216 4>, - <217 4>,<218 4>,<219 4>,<220 4>,<221 4>, - <222 4>,<223 4>,<224 4>,<225 4>,<226 4>, - <227 4>,<228 4>,<229 4>,<230 4>,<231 4>, - <232 4>,<233 4>,<234 4>,<235 4>,<236 4>, - <237 4>,<238 4>,<239 4>,<240 4>,<241 4>, - <242 4>,<243 4>,<244 4>,<245 4>,<246 4>, - <247 4>,<248 4>,<249 4>,<250 4>,<251 4>, - <252 4>,<253 4>,<254 4>,<255 4>,<256 4>, - <257 4>,<258 4>,<259 4>,<260 4>,<261 4>, - <262 4>,<263 4>,<264 4>,<265 4>,<266 4>, - <267 4>,<268 4>,<269 4>,<270 4>,<271 4>, - <272 4>,<273 4>,<274 4>,<275 4>,<276 4>, - <277 4>,<278 4>,<279 4>,<280 4>,<281 4>, - <282 4>,<283 4>,<284 4>,<285 4>,<286 4>, - <287 4>,<608 1>,<609 1>,<610 1>,<611 1>, - <612 1>,<613 1>,<614 1>,<615 1>,<616 1>, - <617 1>,<618 1>,<619 1>,<620 1>,<621 1>, - <622 1>,<623 1>,<624 1>,<625 1>,<626 1>, - <627 1>,<628 1>,<629 1>,<630 1>,<631 1>, - <632 1>,<633 1>,<634 1>,<635 1>,<636 1>, - <637 1>,<638 1>,<639 1>; - status = "disabled"; - }; - - pcie0: pcie@a0090000 { - compatible = "hisilicon,hip06-pcie-ecam"; - reg = <0 0xb0000000 0 0x2000000>, - <0 0xa0090000 0 0x10000>; - bus-range = <0 31>; - msi-map = <0x0000 &its_dsa 0x0000 0x2000>; - msi-map-mask = <0xffff>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - dma-coherent; - ranges = <0x02000000 0 0xb2000000 0x0 0xb2000000 0 - 0x5ff0000 0x01000000 0 0 0 0xb7ff0000 - 0 0x10000>; - #interrupt-cells = <1>; - interrupt-map-mask = <0xf800 0 0 7>; - interrupt-map = <0x0 0 0 1 &mbigen_pcie0 650 4 - 0x0 0 0 2 &mbigen_pcie0 650 4 - 0x0 0 0 3 &mbigen_pcie0 650 4 - 0x0 0 0 4 &mbigen_pcie0 650 4>; - status = "disabled"; - }; - - }; - -}; diff --git a/sys/gnu/dts/arm64/hisilicon/hip07-d05.dts b/sys/gnu/dts/arm64/hisilicon/hip07-d05.dts deleted file mode 100644 index fcbdffe0868..00000000000 --- a/sys/gnu/dts/arm64/hisilicon/hip07-d05.dts +++ /dev/null @@ -1,90 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/** - * dts file for Hisilicon D05 Development Board - * - * Copyright (C) 2016 Hisilicon Ltd. - */ - -/dts-v1/; - -#include "hip07.dtsi" - -/ { - model = "Hisilicon Hip07 D05 Development Board"; - compatible = "hisilicon,hip07-d05"; - - /* the mem node will be updated by UEFI. */ - memory@0 { - device_type = "memory"; - reg = <0x0 0x00000000 0x0 0x40000000>; - numa-node-id = <0>; - }; - - distance-map { - compatible = "numa-distance-map-v1"; - distance-matrix = <0 0 10>, - <0 1 15>, - <0 2 20>, - <0 3 25>, - <1 0 15>, - <1 1 10>, - <1 2 25>, - <1 3 30>, - <2 0 20>, - <2 1 25>, - <2 2 10>, - <2 3 15>, - <3 0 25>, - <3 1 30>, - <3 2 15>, - <3 3 10>; - }; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&uart0 { - status = "ok"; -}; - -&ipmi0 { - status = "ok"; -}; - -&usb_ohci { - status = "ok"; -}; - -&usb_ehci { - status = "ok"; -}; - -ð0 { - status = "ok"; -}; - -ð1 { - status = "ok"; -}; - -ð2 { - status = "ok"; -}; - -ð3 { - status = "ok"; -}; - -&sas1 { - status = "ok"; -}; - -&p0_pcie2_a { - status = "ok"; -}; diff --git a/sys/gnu/dts/arm64/hisilicon/hip07.dtsi b/sys/gnu/dts/arm64/hisilicon/hip07.dtsi deleted file mode 100644 index 4773a533fce..00000000000 --- a/sys/gnu/dts/arm64/hisilicon/hip07.dtsi +++ /dev/null @@ -1,1887 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/** - * dts file for Hisilicon D05 Development Board - * - * Copyright (C) 2016 Hisilicon Ltd. - */ - -#include - -/ { - compatible = "hisilicon,hip07-d05"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu-map { - cluster0 { - core0 { - cpu = <&cpu0>; - }; - core1 { - cpu = <&cpu1>; - }; - core2 { - cpu = <&cpu2>; - }; - core3 { - cpu = <&cpu3>; - }; - }; - - cluster1 { - core0 { - cpu = <&cpu4>; - }; - core1 { - cpu = <&cpu5>; - }; - core2 { - cpu = <&cpu6>; - }; - core3 { - cpu = <&cpu7>; - }; - }; - - cluster2 { - core0 { - cpu = <&cpu8>; - }; - core1 { - cpu = <&cpu9>; - }; - core2 { - cpu = <&cpu10>; - }; - core3 { - cpu = <&cpu11>; - }; - }; - - cluster3 { - core0 { - cpu = <&cpu12>; - }; - core1 { - cpu = <&cpu13>; - }; - core2 { - cpu = <&cpu14>; - }; - core3 { - cpu = <&cpu15>; - }; - }; - - cluster4 { - core0 { - cpu = <&cpu16>; - }; - core1 { - cpu = <&cpu17>; - }; - core2 { - cpu = <&cpu18>; - }; - core3 { - cpu = <&cpu19>; - }; - }; - - cluster5 { - core0 { - cpu = <&cpu20>; - }; - core1 { - cpu = <&cpu21>; - }; - core2 { - cpu = <&cpu22>; - }; - core3 { - cpu = <&cpu23>; - }; - }; - - cluster6 { - core0 { - cpu = <&cpu24>; - }; - core1 { - cpu = <&cpu25>; - }; - core2 { - cpu = <&cpu26>; - }; - core3 { - cpu = <&cpu27>; - }; - }; - - cluster7 { - core0 { - cpu = <&cpu28>; - }; - core1 { - cpu = <&cpu29>; - }; - core2 { - cpu = <&cpu30>; - }; - core3 { - cpu = <&cpu31>; - }; - }; - - cluster8 { - core0 { - cpu = <&cpu32>; - }; - core1 { - cpu = <&cpu33>; - }; - core2 { - cpu = <&cpu34>; - }; - core3 { - cpu = <&cpu35>; - }; - }; - - cluster9 { - core0 { - cpu = <&cpu36>; - }; - core1 { - cpu = <&cpu37>; - }; - core2 { - cpu = <&cpu38>; - }; - core3 { - cpu = <&cpu39>; - }; - }; - - cluster10 { - core0 { - cpu = <&cpu40>; - }; - core1 { - cpu = <&cpu41>; - }; - core2 { - cpu = <&cpu42>; - }; - core3 { - cpu = <&cpu43>; - }; - }; - - cluster11 { - core0 { - cpu = <&cpu44>; - }; - core1 { - cpu = <&cpu45>; - }; - core2 { - cpu = <&cpu46>; - }; - core3 { - cpu = <&cpu47>; - }; - }; - - cluster12 { - core0 { - cpu = <&cpu48>; - }; - core1 { - cpu = <&cpu49>; - }; - core2 { - cpu = <&cpu50>; - }; - core3 { - cpu = <&cpu51>; - }; - }; - - cluster13 { - core0 { - cpu = <&cpu52>; - }; - core1 { - cpu = <&cpu53>; - }; - core2 { - cpu = <&cpu54>; - }; - core3 { - cpu = <&cpu55>; - }; - }; - - cluster14 { - core0 { - cpu = <&cpu56>; - }; - core1 { - cpu = <&cpu57>; - }; - core2 { - cpu = <&cpu58>; - }; - core3 { - cpu = <&cpu59>; - }; - }; - - cluster15 { - core0 { - cpu = <&cpu60>; - }; - core1 { - cpu = <&cpu61>; - }; - core2 { - cpu = <&cpu62>; - }; - core3 { - cpu = <&cpu63>; - }; - }; - }; - - cpu0: cpu@10000 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x10000>; - enable-method = "psci"; - next-level-cache = <&cluster0_l2>; - numa-node-id = <0>; - }; - - cpu1: cpu@10001 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x10001>; - enable-method = "psci"; - next-level-cache = <&cluster0_l2>; - numa-node-id = <0>; - }; - - cpu2: cpu@10002 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x10002>; - enable-method = "psci"; - next-level-cache = <&cluster0_l2>; - numa-node-id = <0>; - }; - - cpu3: cpu@10003 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x10003>; - enable-method = "psci"; - next-level-cache = <&cluster0_l2>; - numa-node-id = <0>; - }; - - cpu4: cpu@10100 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x10100>; - enable-method = "psci"; - next-level-cache = <&cluster1_l2>; - numa-node-id = <0>; - }; - - cpu5: cpu@10101 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x10101>; - enable-method = "psci"; - next-level-cache = <&cluster1_l2>; - numa-node-id = <0>; - }; - - cpu6: cpu@10102 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x10102>; - enable-method = "psci"; - next-level-cache = <&cluster1_l2>; - numa-node-id = <0>; - }; - - cpu7: cpu@10103 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x10103>; - enable-method = "psci"; - next-level-cache = <&cluster1_l2>; - numa-node-id = <0>; - }; - - cpu8: cpu@10200 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x10200>; - enable-method = "psci"; - next-level-cache = <&cluster2_l2>; - numa-node-id = <0>; - }; - - cpu9: cpu@10201 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x10201>; - enable-method = "psci"; - next-level-cache = <&cluster2_l2>; - numa-node-id = <0>; - }; - - cpu10: cpu@10202 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x10202>; - enable-method = "psci"; - next-level-cache = <&cluster2_l2>; - numa-node-id = <0>; - }; - - cpu11: cpu@10203 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x10203>; - enable-method = "psci"; - next-level-cache = <&cluster2_l2>; - numa-node-id = <0>; - }; - - cpu12: cpu@10300 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x10300>; - enable-method = "psci"; - next-level-cache = <&cluster3_l2>; - numa-node-id = <0>; - }; - - cpu13: cpu@10301 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x10301>; - enable-method = "psci"; - next-level-cache = <&cluster3_l2>; - numa-node-id = <0>; - }; - - cpu14: cpu@10302 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x10302>; - enable-method = "psci"; - next-level-cache = <&cluster3_l2>; - numa-node-id = <0>; - }; - - cpu15: cpu@10303 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x10303>; - enable-method = "psci"; - next-level-cache = <&cluster3_l2>; - numa-node-id = <0>; - }; - - cpu16: cpu@30000 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x30000>; - enable-method = "psci"; - next-level-cache = <&cluster4_l2>; - numa-node-id = <1>; - }; - - cpu17: cpu@30001 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x30001>; - enable-method = "psci"; - next-level-cache = <&cluster4_l2>; - numa-node-id = <1>; - }; - - cpu18: cpu@30002 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x30002>; - enable-method = "psci"; - next-level-cache = <&cluster4_l2>; - numa-node-id = <1>; - }; - - cpu19: cpu@30003 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x30003>; - enable-method = "psci"; - next-level-cache = <&cluster4_l2>; - numa-node-id = <1>; - }; - - cpu20: cpu@30100 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x30100>; - enable-method = "psci"; - next-level-cache = <&cluster5_l2>; - numa-node-id = <1>; - }; - - cpu21: cpu@30101 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x30101>; - enable-method = "psci"; - next-level-cache = <&cluster5_l2>; - numa-node-id = <1>; - }; - - cpu22: cpu@30102 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x30102>; - enable-method = "psci"; - next-level-cache = <&cluster5_l2>; - numa-node-id = <1>; - }; - - cpu23: cpu@30103 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x30103>; - enable-method = "psci"; - next-level-cache = <&cluster5_l2>; - numa-node-id = <1>; - }; - - cpu24: cpu@30200 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x30200>; - enable-method = "psci"; - next-level-cache = <&cluster6_l2>; - numa-node-id = <1>; - }; - - cpu25: cpu@30201 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x30201>; - enable-method = "psci"; - next-level-cache = <&cluster6_l2>; - numa-node-id = <1>; - }; - - cpu26: cpu@30202 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x30202>; - enable-method = "psci"; - next-level-cache = <&cluster6_l2>; - numa-node-id = <1>; - }; - - cpu27: cpu@30203 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x30203>; - enable-method = "psci"; - next-level-cache = <&cluster6_l2>; - numa-node-id = <1>; - }; - - cpu28: cpu@30300 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x30300>; - enable-method = "psci"; - next-level-cache = <&cluster7_l2>; - numa-node-id = <1>; - }; - - cpu29: cpu@30301 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x30301>; - enable-method = "psci"; - next-level-cache = <&cluster7_l2>; - numa-node-id = <1>; - }; - - cpu30: cpu@30302 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x30302>; - enable-method = "psci"; - next-level-cache = <&cluster7_l2>; - numa-node-id = <1>; - }; - - cpu31: cpu@30303 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x30303>; - enable-method = "psci"; - next-level-cache = <&cluster7_l2>; - numa-node-id = <1>; - }; - - cpu32: cpu@50000 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x50000>; - enable-method = "psci"; - next-level-cache = <&cluster8_l2>; - numa-node-id = <2>; - }; - - cpu33: cpu@50001 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x50001>; - enable-method = "psci"; - next-level-cache = <&cluster8_l2>; - numa-node-id = <2>; - }; - - cpu34: cpu@50002 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x50002>; - enable-method = "psci"; - next-level-cache = <&cluster8_l2>; - numa-node-id = <2>; - }; - - cpu35: cpu@50003 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x50003>; - enable-method = "psci"; - next-level-cache = <&cluster8_l2>; - numa-node-id = <2>; - }; - - cpu36: cpu@50100 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x50100>; - enable-method = "psci"; - next-level-cache = <&cluster9_l2>; - numa-node-id = <2>; - }; - - cpu37: cpu@50101 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x50101>; - enable-method = "psci"; - next-level-cache = <&cluster9_l2>; - numa-node-id = <2>; - }; - - cpu38: cpu@50102 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x50102>; - enable-method = "psci"; - next-level-cache = <&cluster9_l2>; - numa-node-id = <2>; - }; - - cpu39: cpu@50103 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x50103>; - enable-method = "psci"; - next-level-cache = <&cluster9_l2>; - numa-node-id = <2>; - }; - - cpu40: cpu@50200 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x50200>; - enable-method = "psci"; - next-level-cache = <&cluster10_l2>; - numa-node-id = <2>; - }; - - cpu41: cpu@50201 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x50201>; - enable-method = "psci"; - next-level-cache = <&cluster10_l2>; - numa-node-id = <2>; - }; - - cpu42: cpu@50202 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x50202>; - enable-method = "psci"; - next-level-cache = <&cluster10_l2>; - numa-node-id = <2>; - }; - - cpu43: cpu@50203 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x50203>; - enable-method = "psci"; - next-level-cache = <&cluster10_l2>; - numa-node-id = <2>; - }; - - cpu44: cpu@50300 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x50300>; - enable-method = "psci"; - next-level-cache = <&cluster11_l2>; - numa-node-id = <2>; - }; - - cpu45: cpu@50301 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x50301>; - enable-method = "psci"; - next-level-cache = <&cluster11_l2>; - numa-node-id = <2>; - }; - - cpu46: cpu@50302 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x50302>; - enable-method = "psci"; - next-level-cache = <&cluster11_l2>; - numa-node-id = <2>; - }; - - cpu47: cpu@50303 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x50303>; - enable-method = "psci"; - next-level-cache = <&cluster11_l2>; - numa-node-id = <2>; - }; - - cpu48: cpu@70000 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x70000>; - enable-method = "psci"; - next-level-cache = <&cluster12_l2>; - numa-node-id = <3>; - }; - - cpu49: cpu@70001 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x70001>; - enable-method = "psci"; - next-level-cache = <&cluster12_l2>; - numa-node-id = <3>; - }; - - cpu50: cpu@70002 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x70002>; - enable-method = "psci"; - next-level-cache = <&cluster12_l2>; - numa-node-id = <3>; - }; - - cpu51: cpu@70003 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x70003>; - enable-method = "psci"; - next-level-cache = <&cluster12_l2>; - numa-node-id = <3>; - }; - - cpu52: cpu@70100 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x70100>; - enable-method = "psci"; - next-level-cache = <&cluster13_l2>; - numa-node-id = <3>; - }; - - cpu53: cpu@70101 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x70101>; - enable-method = "psci"; - next-level-cache = <&cluster13_l2>; - numa-node-id = <3>; - }; - - cpu54: cpu@70102 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x70102>; - enable-method = "psci"; - next-level-cache = <&cluster13_l2>; - numa-node-id = <3>; - }; - - cpu55: cpu@70103 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x70103>; - enable-method = "psci"; - next-level-cache = <&cluster13_l2>; - numa-node-id = <3>; - }; - - cpu56: cpu@70200 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x70200>; - enable-method = "psci"; - next-level-cache = <&cluster14_l2>; - numa-node-id = <3>; - }; - - cpu57: cpu@70201 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x70201>; - enable-method = "psci"; - next-level-cache = <&cluster14_l2>; - numa-node-id = <3>; - }; - - cpu58: cpu@70202 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x70202>; - enable-method = "psci"; - next-level-cache = <&cluster14_l2>; - numa-node-id = <3>; - }; - - cpu59: cpu@70203 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x70203>; - enable-method = "psci"; - next-level-cache = <&cluster14_l2>; - numa-node-id = <3>; - }; - - cpu60: cpu@70300 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x70300>; - enable-method = "psci"; - next-level-cache = <&cluster15_l2>; - numa-node-id = <3>; - }; - - cpu61: cpu@70301 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x70301>; - enable-method = "psci"; - next-level-cache = <&cluster15_l2>; - numa-node-id = <3>; - }; - - cpu62: cpu@70302 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x70302>; - enable-method = "psci"; - next-level-cache = <&cluster15_l2>; - numa-node-id = <3>; - }; - - cpu63: cpu@70303 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x70303>; - enable-method = "psci"; - next-level-cache = <&cluster15_l2>; - numa-node-id = <3>; - }; - - cluster0_l2: l2-cache0 { - compatible = "cache"; - }; - - cluster1_l2: l2-cache1 { - compatible = "cache"; - }; - - cluster2_l2: l2-cache2 { - compatible = "cache"; - }; - - cluster3_l2: l2-cache3 { - compatible = "cache"; - }; - - cluster4_l2: l2-cache4 { - compatible = "cache"; - }; - - cluster5_l2: l2-cache5 { - compatible = "cache"; - }; - - cluster6_l2: l2-cache6 { - compatible = "cache"; - }; - - cluster7_l2: l2-cache7 { - compatible = "cache"; - }; - - cluster8_l2: l2-cache8 { - compatible = "cache"; - }; - - cluster9_l2: l2-cache9 { - compatible = "cache"; - }; - - cluster10_l2: l2-cache10 { - compatible = "cache"; - }; - - cluster11_l2: l2-cache11 { - compatible = "cache"; - }; - - cluster12_l2: l2-cache12 { - compatible = "cache"; - }; - - cluster13_l2: l2-cache13 { - compatible = "cache"; - }; - - cluster14_l2: l2-cache14 { - compatible = "cache"; - }; - - cluster15_l2: l2-cache15 { - compatible = "cache"; - }; - }; - - gic: interrupt-controller@4d000000 { - compatible = "arm,gic-v3"; - #interrupt-cells = <3>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - interrupt-controller; - #redistributor-regions = <4>; - redistributor-stride = <0x0 0x40000>; - reg = <0x0 0x4d000000 0x0 0x10000>, /* GICD */ - <0x0 0x4d100000 0x0 0x400000>, /* p0 GICR node 0 */ - <0x0 0x6d100000 0x0 0x400000>, /* p0 GICR node 1 */ - <0x400 0x4d100000 0x0 0x400000>, /* p1 GICR node 2 */ - <0x400 0x6d100000 0x0 0x400000>, /* p1 GICR node 3 */ - <0x0 0xfe000000 0x0 0x10000>, /* GICC */ - <0x0 0xfe010000 0x0 0x10000>, /* GICH */ - <0x0 0xfe020000 0x0 0x10000>; /* GICV */ - interrupts = ; - - p0_its_peri_a: interrupt-controller@4c000000 { - compatible = "arm,gic-v3-its"; - msi-controller; - #msi-cells = <1>; - reg = <0x0 0x4c000000 0x0 0x40000>; - }; - - p0_its_peri_b: interrupt-controller@6c000000 { - compatible = "arm,gic-v3-its"; - msi-controller; - #msi-cells = <1>; - reg = <0x0 0x6c000000 0x0 0x40000>; - }; - - p0_its_dsa_a: interrupt-controller@c6000000 { - compatible = "arm,gic-v3-its"; - msi-controller; - #msi-cells = <1>; - reg = <0x0 0xc6000000 0x0 0x40000>; - }; - - p0_its_dsa_b: interrupt-controller@8,c6000000 { - compatible = "arm,gic-v3-its"; - msi-controller; - #msi-cells = <1>; - reg = <0x8 0xc6000000 0x0 0x40000>; - }; - - p1_its_peri_a: interrupt-controller@400,4c000000 { - compatible = "arm,gic-v3-its"; - msi-controller; - #msi-cells = <1>; - reg = <0x400 0x4c000000 0x0 0x40000>; - }; - - p1_its_peri_b: interrupt-controller@400,6c000000 { - compatible = "arm,gic-v3-its"; - msi-controller; - #msi-cells = <1>; - reg = <0x400 0x6c000000 0x0 0x40000>; - }; - - p1_its_dsa_a: interrupt-controller@400,c6000000 { - compatible = "arm,gic-v3-its"; - msi-controller; - #msi-cells = <1>; - reg = <0x400 0xc6000000 0x0 0x40000>; - }; - - p1_its_dsa_b: interrupt-controller@408,c6000000 { - compatible = "arm,gic-v3-its"; - msi-controller; - #msi-cells = <1>; - reg = <0x408 0xc6000000 0x0 0x40000>; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - pmu { - compatible = "arm,cortex-a72-pmu"; - interrupts = ; - }; - - p0_mbigen_peri_b: interrupt-controller@60080000 { - compatible = "hisilicon,mbigen-v2"; - reg = <0x0 0x60080000 0x0 0x10000>; - - mbigen_uart: uart_intc { - msi-parent = <&p0_its_peri_b 0x120c7>; - interrupt-controller; - #interrupt-cells = <2>; - num-pins = <1>; - }; - }; - - p0_mbigen_pcie_a: interrupt-controller@a0080000 { - compatible = "hisilicon,mbigen-v2"; - reg = <0x0 0xa0080000 0x0 0x10000>; - - mbigen_pcie2_a: intc_pcie2_a { - msi-parent = <&p0_its_dsa_a 0x40087>; - interrupt-controller; - #interrupt-cells = <2>; - num-pins = <10>; - }; - - mbigen_sas1: intc_sas1 { - msi-parent = <&p0_its_dsa_a 0x40000>; - interrupt-controller; - #interrupt-cells = <2>; - num-pins = <128>; - }; - - mbigen_sas2: intc_sas2 { - msi-parent = <&p0_its_dsa_a 0x40040>; - interrupt-controller; - #interrupt-cells = <2>; - num-pins = <128>; - }; - - mbigen_smmu_pcie: intc_smmu_pcie { - msi-parent = <&p0_its_dsa_a 0x40b0c>; - interrupt-controller; - #interrupt-cells = <2>; - num-pins = <3>; - }; - - mbigen_usb: intc_usb { - msi-parent = <&p0_its_dsa_a 0x40080>; - interrupt-controller; - #interrupt-cells = <2>; - num-pins = <2>; - }; - }; - p0_mbigen_alg_a:interrupt-controller@d0080000 { - compatible = "hisilicon,mbigen-v2"; - reg = <0x0 0xd0080000 0x0 0x10000>; - - p0_mbigen_sec_a: intc_sec { - msi-parent = <&p0_its_dsa_a 0x40400>; - interrupt-controller; - #interrupt-cells = <2>; - num-pins = <33>; - }; - p0_mbigen_smmu_alg_a: intc_smmu_alg { - msi-parent = <&p0_its_dsa_a 0x40b1b>; - interrupt-controller; - #interrupt-cells = <2>; - num-pins = <3>; - }; - }; - p0_mbigen_alg_b:interrupt-controller@8,d0080000 { - compatible = "hisilicon,mbigen-v2"; - reg = <0x8 0xd0080000 0x0 0x10000>; - - p0_mbigen_sec_b: intc_sec { - msi-parent = <&p0_its_dsa_b 0x42400>; - interrupt-controller; - #interrupt-cells = <2>; - num-pins = <33>; - }; - p0_mbigen_smmu_alg_b: intc_smmu_alg { - msi-parent = <&p0_its_dsa_b 0x42b1b>; - interrupt-controller; - #interrupt-cells = <2>; - num-pins = <3>; - }; - }; - p1_mbigen_alg_a:interrupt-controller@400,d0080000 { - compatible = "hisilicon,mbigen-v2"; - reg = <0x400 0xd0080000 0x0 0x10000>; - - p1_mbigen_sec_a: intc_sec { - msi-parent = <&p1_its_dsa_a 0x44400>; - interrupt-controller; - #interrupt-cells = <2>; - num-pins = <33>; - }; - p1_mbigen_smmu_alg_a: intc_smmu_alg { - msi-parent = <&p1_its_dsa_a 0x44b1b>; - interrupt-controller; - #interrupt-cells = <2>; - num-pins = <3>; - }; - }; - p1_mbigen_alg_b:interrupt-controller@408,d0080000 { - compatible = "hisilicon,mbigen-v2"; - reg = <0x408 0xd0080000 0x0 0x10000>; - - p1_mbigen_sec_b: intc_sec { - msi-parent = <&p1_its_dsa_b 0x46400>; - interrupt-controller; - #interrupt-cells = <2>; - num-pins = <33>; - }; - p1_mbigen_smmu_alg_b: intc_smmu_alg { - msi-parent = <&p1_its_dsa_b 0x46b1b>; - interrupt-controller; - #interrupt-cells = <2>; - num-pins = <3>; - }; - }; - p0_mbigen_dsa_a: interrupt-controller@c0080000 { - compatible = "hisilicon,mbigen-v2"; - reg = <0x0 0xc0080000 0x0 0x10000>; - - mbigen_dsaf0: intc_dsaf0 { - msi-parent = <&p0_its_dsa_a 0x40800>; - interrupt-controller; - #interrupt-cells = <2>; - num-pins = <409>; - }; - - mbigen_dsa_roce: intc-roce { - msi-parent = <&p0_its_dsa_a 0x40B1E>; - interrupt-controller; - #interrupt-cells = <2>; - num-pins = <34>; - }; - - mbigen_sas0: intc-sas0 { - msi-parent = <&p0_its_dsa_a 0x40900>; - interrupt-controller; - #interrupt-cells = <2>; - num-pins = <128>; - }; - - mbigen_smmu_dsa: intc_smmu_dsa { - msi-parent = <&p0_its_dsa_a 0x40b20>; - interrupt-controller; - #interrupt-cells = <2>; - num-pins = <3>; - }; - }; - - /** - * HiSilicon erratum 161010801: This describes the limitation - * of HiSilicon platforms hip06/hip07 to support the SMMUv3 - * mappings for PCIe MSI transactions. - * PCIe controller on these platforms has to differentiate the - * MSI payload against other DMA payload and has to modify the - * MSI payload. This makes it difficult for these platforms to - * have a SMMU translation for MSI. In order to workaround this, - * ARM SMMUv3 driver requires a quirk to treat the MSI regions - * separately. Such a quirk is currently missing for DT based - * systems. Hence please make sure that the smmu pcie node on - * hip07 is disabled as this will break the PCIe functionality - * when iommu-map entry is used along with the PCIe node. - * Refer:https://www.spinics.net/lists/arm-kernel/msg602812.html - */ - smmu0: smmu_pcie { - compatible = "arm,smmu-v3"; - reg = <0x0 0xa0040000 0x0 0x20000>; - #iommu-cells = <1>; - dma-coherent; - smmu-cb-memtype = <0x0 0x1>; - hisilicon,broken-prefetch-cmd; - status = "disabled"; - }; - p0_smmu_alg_a: smmu_alg@d0040000 { - compatible = "arm,smmu-v3"; - reg = <0x0 0xd0040000 0x0 0x20000>; - interrupt-parent = <&p0_mbigen_smmu_alg_a>; - interrupts = <733 1>, - <734 1>, - <735 1>; - interrupt-names = "eventq", "gerror", "priq"; - #iommu-cells = <1>; - dma-coherent; - hisilicon,broken-prefetch-cmd; - /* smmu-cb-memtype = <0x0 0x1>;*/ - }; - p0_smmu_alg_b: smmu_alg@8,d0040000 { - compatible = "arm,smmu-v3"; - reg = <0x8 0xd0040000 0x0 0x20000>; - interrupt-parent = <&p0_mbigen_smmu_alg_b>; - interrupts = <733 1>, - <734 1>, - <735 1>; - interrupt-names = "eventq", "gerror", "priq"; - #iommu-cells = <1>; - dma-coherent; - hisilicon,broken-prefetch-cmd; - /* smmu-cb-memtype = <0x0 0x1>;*/ - }; - p1_smmu_alg_a: smmu_alg@400,d0040000 { - compatible = "arm,smmu-v3"; - reg = <0x400 0xd0040000 0x0 0x20000>; - interrupt-parent = <&p1_mbigen_smmu_alg_a>; - interrupts = <733 1>, - <734 1>, - <735 1>; - interrupt-names = "eventq", "gerror", "priq"; - #iommu-cells = <1>; - dma-coherent; - hisilicon,broken-prefetch-cmd; - /* smmu-cb-memtype = <0x0 0x1>;*/ - }; - p1_smmu_alg_b: smmu_alg@408,d0040000 { - compatible = "arm,smmu-v3"; - reg = <0x408 0xd0040000 0x0 0x20000>; - interrupt-parent = <&p1_mbigen_smmu_alg_b>; - interrupts = <733 1>, - <734 1>, - <735 1>; - interrupt-names = "eventq", "gerror", "priq"; - #iommu-cells = <1>; - dma-coherent; - hisilicon,broken-prefetch-cmd; - /* smmu-cb-memtype = <0x0 0x1>;*/ - }; - - soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - isa@a01b0000 { - compatible = "hisilicon,hip07-lpc"; - #size-cells = <1>; - #address-cells = <2>; - reg = <0x0 0xa01b0000 0x0 0x1000>; - - ipmi0: bt@e4 { - compatible = "ipmi-bt"; - device_type = "ipmi"; - reg = <0x01 0xe4 0x04>; - status = "disabled"; - }; - }; - - uart0: uart@602b0000 { - compatible = "arm,sbsa-uart"; - reg = <0x0 0x602b0000 0x0 0x1000>; - interrupt-parent = <&mbigen_uart>; - interrupts = <807 4>; - current-speed = <115200>; - reg-io-width = <4>; - status = "disabled"; - }; - - usb_ohci: ohci@a7030000 { - compatible = "generic-ohci"; - reg = <0x0 0xa7030000 0x0 0x10000>; - interrupt-parent = <&mbigen_usb>; - interrupts = <640 4>; - dma-coherent; - status = "disabled"; - }; - - usb_ehci: ehci@a7020000 { - compatible = "generic-ehci"; - reg = <0x0 0xa7020000 0x0 0x10000>; - interrupt-parent = <&mbigen_usb>; - interrupts = <641 4>; - dma-coherent; - status = "disabled"; - }; - - peri_c_subctrl: sub_ctrl_c@60000000 { - compatible = "hisilicon,peri-subctrl","syscon"; - reg = <0 0x60000000 0x0 0x10000>; - }; - - dsa_subctrl: dsa_subctrl@c0000000 { - compatible = "hisilicon,dsa-subctrl", "syscon"; - reg = <0x0 0xc0000000 0x0 0x10000>; - }; - - dsa_cpld: dsa_cpld@78000010 { - compatible = "syscon"; - reg = <0x0 0x78000010 0x0 0x100>; - reg-io-width = <2>; - }; - - pcie_subctl: pcie_subctl@a0000000 { - compatible = "hisilicon,pcie-sas-subctrl", "syscon"; - reg = <0x0 0xa0000000 0x0 0x10000>; - }; - - serdes_ctrl: sds_ctrl@c2200000 { - compatible = "syscon"; - reg = <0 0xc2200000 0x0 0x80000>; - }; - - mdio@603c0000 { - compatible = "hisilicon,hns-mdio"; - reg = <0x0 0x603c0000 0x0 0x1000>; - subctrl-vbase = <&peri_c_subctrl 0x338 0xa38 - 0x531c 0x5a1c>; - #address-cells = <1>; - #size-cells = <0>; - - phy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - }; - - phy1: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; - }; - - dsaf0: dsa@c7000000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "hisilicon,hns-dsaf-v2"; - mode = "6port-16rss"; - reg = <0x0 0xc5000000 0x0 0x890000 - 0x0 0xc7000000 0x0 0x600000>; - reg-names = "ppe-base", "dsaf-base"; - interrupt-parent = <&mbigen_dsaf0>; - subctrl-syscon = <&dsa_subctrl>; - reset-field-offset = <0>; - interrupts = - <576 1>, <577 1>, <578 1>, <579 1>, <580 1>, - <581 1>, <582 1>, <583 1>, <584 1>, <585 1>, - <586 1>, <587 1>, <588 1>, <589 1>, <590 1>, - <591 1>, <592 1>, <593 1>, <594 1>, <595 1>, - <596 1>, <597 1>, <598 1>, <599 1>, <600 1>, - <960 1>, <961 1>, <962 1>, <963 1>, <964 1>, - <965 1>, <966 1>, <967 1>, <968 1>, <969 1>, - <970 1>, <971 1>, <972 1>, <973 1>, <974 1>, - <975 1>, <976 1>, <977 1>, <978 1>, <979 1>, - <980 1>, <981 1>, <982 1>, <983 1>, <984 1>, - <985 1>, <986 1>, <987 1>, <988 1>, <989 1>, - <990 1>, <991 1>, <992 1>, <993 1>, <994 1>, - <995 1>, <996 1>, <997 1>, <998 1>, <999 1>, - <1000 1>, <1001 1>, <1002 1>, <1003 1>, <1004 1>, - <1005 1>, <1006 1>, <1007 1>, <1008 1>, <1009 1>, - <1010 1>, <1011 1>, <1012 1>, <1013 1>, <1014 1>, - <1015 1>, <1016 1>, <1017 1>, <1018 1>, <1019 1>, - <1020 1>, <1021 1>, <1022 1>, <1023 1>, <1024 1>, - <1025 1>, <1026 1>, <1027 1>, <1028 1>, <1029 1>, - <1030 1>, <1031 1>, <1032 1>, <1033 1>, <1034 1>, - <1035 1>, <1036 1>, <1037 1>, <1038 1>, <1039 1>, - <1040 1>, <1041 1>, <1042 1>, <1043 1>, <1044 1>, - <1045 1>, <1046 1>, <1047 1>, <1048 1>, <1049 1>, - <1050 1>, <1051 1>, <1052 1>, <1053 1>, <1054 1>, - <1055 1>, <1056 1>, <1057 1>, <1058 1>, <1059 1>, - <1060 1>, <1061 1>, <1062 1>, <1063 1>, <1064 1>, - <1065 1>, <1066 1>, <1067 1>, <1068 1>, <1069 1>, - <1070 1>, <1071 1>, <1072 1>, <1073 1>, <1074 1>, - <1075 1>, <1076 1>, <1077 1>, <1078 1>, <1079 1>, - <1080 1>, <1081 1>, <1082 1>, <1083 1>, <1084 1>, - <1085 1>, <1086 1>, <1087 1>, <1088 1>, <1089 1>, - <1090 1>, <1091 1>, <1092 1>, <1093 1>, <1094 1>, - <1095 1>, <1096 1>, <1097 1>, <1098 1>, <1099 1>, - <1100 1>, <1101 1>, <1102 1>, <1103 1>, <1104 1>, - <1105 1>, <1106 1>, <1107 1>, <1108 1>, <1109 1>, - <1110 1>, <1111 1>, <1112 1>, <1113 1>, <1114 1>, - <1115 1>, <1116 1>, <1117 1>, <1118 1>, <1119 1>, - <1120 1>, <1121 1>, <1122 1>, <1123 1>, <1124 1>, - <1125 1>, <1126 1>, <1127 1>, <1128 1>, <1129 1>, - <1130 1>, <1131 1>, <1132 1>, <1133 1>, <1134 1>, - <1135 1>, <1136 1>, <1137 1>, <1138 1>, <1139 1>, - <1140 1>, <1141 1>, <1142 1>, <1143 1>, <1144 1>, - <1145 1>, <1146 1>, <1147 1>, <1148 1>, <1149 1>, - <1150 1>, <1151 1>, <1152 1>, <1153 1>, <1154 1>, - <1155 1>, <1156 1>, <1157 1>, <1158 1>, <1159 1>, - <1160 1>, <1161 1>, <1162 1>, <1163 1>, <1164 1>, - <1165 1>, <1166 1>, <1167 1>, <1168 1>, <1169 1>, - <1170 1>, <1171 1>, <1172 1>, <1173 1>, <1174 1>, - <1175 1>, <1176 1>, <1177 1>, <1178 1>, <1179 1>, - <1180 1>, <1181 1>, <1182 1>, <1183 1>, <1184 1>, - <1185 1>, <1186 1>, <1187 1>, <1188 1>, <1189 1>, - <1190 1>, <1191 1>, <1192 1>, <1193 1>, <1194 1>, - <1195 1>, <1196 1>, <1197 1>, <1198 1>, <1199 1>, - <1200 1>, <1201 1>, <1202 1>, <1203 1>, <1204 1>, - <1205 1>, <1206 1>, <1207 1>, <1208 1>, <1209 1>, - <1210 1>, <1211 1>, <1212 1>, <1213 1>, <1214 1>, - <1215 1>, <1216 1>, <1217 1>, <1218 1>, <1219 1>, - <1220 1>, <1221 1>, <1222 1>, <1223 1>, <1224 1>, - <1225 1>, <1226 1>, <1227 1>, <1228 1>, <1229 1>, - <1230 1>, <1231 1>, <1232 1>, <1233 1>, <1234 1>, - <1235 1>, <1236 1>, <1237 1>, <1238 1>, <1239 1>, - <1240 1>, <1241 1>, <1242 1>, <1243 1>, <1244 1>, - <1245 1>, <1246 1>, <1247 1>, <1248 1>, <1249 1>, - <1250 1>, <1251 1>, <1252 1>, <1253 1>, <1254 1>, - <1255 1>, <1256 1>, <1257 1>, <1258 1>, <1259 1>, - <1260 1>, <1261 1>, <1262 1>, <1263 1>, <1264 1>, - <1265 1>, <1266 1>, <1267 1>, <1268 1>, <1269 1>, - <1270 1>, <1271 1>, <1272 1>, <1273 1>, <1274 1>, - <1275 1>, <1276 1>, <1277 1>, <1278 1>, <1279 1>, - <1280 1>, <1281 1>, <1282 1>, <1283 1>, <1284 1>, - <1285 1>, <1286 1>, <1287 1>, <1288 1>, <1289 1>, - <1290 1>, <1291 1>, <1292 1>, <1293 1>, <1294 1>, - <1295 1>, <1296 1>, <1297 1>, <1298 1>, <1299 1>, - <1300 1>, <1301 1>, <1302 1>, <1303 1>, <1304 1>, - <1305 1>, <1306 1>, <1307 1>, <1308 1>, <1309 1>, - <1310 1>, <1311 1>, <1312 1>, <1313 1>, <1314 1>, - <1315 1>, <1316 1>, <1317 1>, <1318 1>, <1319 1>, - <1320 1>, <1321 1>, <1322 1>, <1323 1>, <1324 1>, - <1325 1>, <1326 1>, <1327 1>, <1328 1>, <1329 1>, - <1330 1>, <1331 1>, <1332 1>, <1333 1>, <1334 1>, - <1335 1>, <1336 1>, <1337 1>, <1338 1>, <1339 1>, - <1340 1>, <1341 1>, <1342 1>, <1343 1>; - - desc-num = <0x400>; - buf-size = <0x1000>; - dma-coherent; - - port@0 { - reg = <0>; - serdes-syscon = <&serdes_ctrl>; - cpld-syscon = <&dsa_cpld 0x0>; - port-rst-offset = <0>; - port-mode-offset = <0>; - mc-mac-mask = [ff f0 00 00 00 00]; - media-type = "fiber"; - }; - - port@1 { - reg = <1>; - serdes-syscon= <&serdes_ctrl>; - cpld-syscon = <&dsa_cpld 0x4>; - port-rst-offset = <1>; - port-mode-offset = <1>; - mc-mac-mask = [ff f0 00 00 00 00]; - media-type = "fiber"; - }; - - port@4 { - reg = <4>; - phy-handle = <&phy0>; - serdes-syscon= <&serdes_ctrl>; - port-rst-offset = <4>; - port-mode-offset = <2>; - mc-mac-mask = [ff f0 00 00 00 00]; - media-type = "copper"; - }; - - port@5 { - reg = <5>; - phy-handle = <&phy1>; - serdes-syscon= <&serdes_ctrl>; - port-rst-offset = <5>; - port-mode-offset = <3>; - mc-mac-mask = [ff f0 00 00 00 00]; - media-type = "copper"; - }; - }; - - eth0: ethernet@4{ - compatible = "hisilicon,hns-nic-v2"; - ae-handle = <&dsaf0>; - port-idx-in-ae = <4>; - local-mac-address = [00 00 00 00 00 00]; - status = "disabled"; - dma-coherent; - }; - - eth1: ethernet@5{ - compatible = "hisilicon,hns-nic-v2"; - ae-handle = <&dsaf0>; - port-idx-in-ae = <5>; - local-mac-address = [00 00 00 00 00 00]; - status = "disabled"; - dma-coherent; - }; - - eth2: ethernet@0{ - compatible = "hisilicon,hns-nic-v2"; - ae-handle = <&dsaf0>; - port-idx-in-ae = <0>; - local-mac-address = [00 00 00 00 00 00]; - status = "disabled"; - dma-coherent; - }; - - eth3: ethernet@1{ - compatible = "hisilicon,hns-nic-v2"; - ae-handle = <&dsaf0>; - port-idx-in-ae = <1>; - local-mac-address = [00 00 00 00 00 00]; - status = "disabled"; - dma-coherent; - }; - - infiniband@c4000000 { - compatible = "hisilicon,hns-roce-v1"; - reg = <0x0 0xc4000000 0x0 0x100000>; - dma-coherent; - eth-handle = <ð2 ð3 0 0 ð0 ð1>; - dsaf-handle = <&dsaf0>; - node-guid = [00 9A CD 00 00 01 02 03]; - #address-cells = <2>; - #size-cells = <2>; - interrupt-parent = <&mbigen_dsa_roce>; - interrupts = <722 1>, - <723 1>, - <724 1>, - <725 1>, - <726 1>, - <727 1>, - <728 1>, - <729 1>, - <730 1>, - <731 1>, - <732 1>, - <733 1>, - <734 1>, - <735 1>, - <736 1>, - <737 1>, - <738 1>, - <739 1>, - <740 1>, - <741 1>, - <742 1>, - <743 1>, - <744 1>, - <745 1>, - <746 1>, - <747 1>, - <748 1>, - <749 1>, - <750 1>, - <751 1>, - <752 1>, - <753 1>, - <785 1>, - <754 4>; - - interrupt-names = "hns-roce-comp-0", - "hns-roce-comp-1", - "hns-roce-comp-2", - "hns-roce-comp-3", - "hns-roce-comp-4", - "hns-roce-comp-5", - "hns-roce-comp-6", - "hns-roce-comp-7", - "hns-roce-comp-8", - "hns-roce-comp-9", - "hns-roce-comp-10", - "hns-roce-comp-11", - "hns-roce-comp-12", - "hns-roce-comp-13", - "hns-roce-comp-14", - "hns-roce-comp-15", - "hns-roce-comp-16", - "hns-roce-comp-17", - "hns-roce-comp-18", - "hns-roce-comp-19", - "hns-roce-comp-20", - "hns-roce-comp-21", - "hns-roce-comp-22", - "hns-roce-comp-23", - "hns-roce-comp-24", - "hns-roce-comp-25", - "hns-roce-comp-26", - "hns-roce-comp-27", - "hns-roce-comp-28", - "hns-roce-comp-29", - "hns-roce-comp-30", - "hns-roce-comp-31", - "hns-roce-async", - "hns-roce-common"; - }; - - sas0: sas@c3000000 { - compatible = "hisilicon,hip07-sas-v2"; - reg = <0 0xc3000000 0 0x10000>; - sas-addr = [50 01 88 20 16 00 00 00]; - hisilicon,sas-syscon = <&dsa_subctrl>; - ctrl-reset-reg = <0xa60>; - ctrl-reset-sts-reg = <0x5a30>; - ctrl-clock-ena-reg = <0x338>; - queue-count = <16>; - phy-count = <8>; - dma-coherent; - interrupt-parent = <&mbigen_sas0>; - interrupts = <64 4>,<65 4>,<66 4>,<67 4>,<68 4>, - <69 4>,<70 4>,<71 4>,<72 4>,<73 4>, - <74 4>,<75 4>,<76 4>,<77 4>,<78 4>, - <79 4>,<80 4>,<81 4>,<82 4>,<83 4>, - <84 4>,<85 4>,<86 4>,<87 4>,<88 4>, - <89 4>,<90 4>,<91 4>,<92 4>,<93 4>, - <94 4>,<95 4>,<96 4>,<97 4>,<98 4>, - <99 4>,<100 4>,<101 4>,<102 4>,<103 4>, - <104 4>,<105 4>,<106 4>,<107 4>,<108 4>, - <109 4>,<110 4>,<111 4>,<112 4>,<113 4>, - <114 4>,<115 4>,<116 4>,<117 4>,<118 4>, - <119 4>,<120 4>,<121 4>,<122 4>,<123 4>, - <124 4>,<125 4>,<126 4>,<127 4>,<128 4>, - <129 4>,<130 4>,<131 4>,<132 4>,<133 4>, - <134 4>,<135 4>,<136 4>,<137 4>,<138 4>, - <139 4>,<140 4>,<141 4>,<142 4>,<143 4>, - <144 4>,<145 4>,<146 4>,<147 4>,<148 4>, - <149 4>,<150 4>,<151 4>,<152 4>,<153 4>, - <154 4>,<155 4>,<156 4>,<157 4>,<158 4>, - <159 4>,<601 1>,<602 1>,<603 1>,<604 1>, - <605 1>,<606 1>,<607 1>,<608 1>,<609 1>, - <610 1>,<611 1>,<612 1>,<613 1>,<614 1>, - <615 1>,<616 1>,<617 1>,<618 1>,<619 1>, - <620 1>,<621 1>,<622 1>,<623 1>,<624 1>, - <625 1>,<626 1>,<627 1>,<628 1>,<629 1>, - <630 1>,<631 1>,<632 1>; - status = "disabled"; - }; - - sas1: sas@a2000000 { - compatible = "hisilicon,hip07-sas-v2"; - reg = <0 0xa2000000 0 0x10000>; - sas-addr = [50 01 88 20 16 00 00 00]; - hisilicon,sas-syscon = <&pcie_subctl>; - hip06-sas-v2-quirk-amt; - ctrl-reset-reg = <0xa18>; - ctrl-reset-sts-reg = <0x5a0c>; - ctrl-clock-ena-reg = <0x318>; - queue-count = <16>; - phy-count = <8>; - dma-coherent; - interrupt-parent = <&mbigen_sas1>; - interrupts = <64 4>,<65 4>,<66 4>,<67 4>,<68 4>, - <69 4>,<70 4>,<71 4>,<72 4>,<73 4>, - <74 4>,<75 4>,<76 4>,<77 4>,<78 4>, - <79 4>,<80 4>,<81 4>,<82 4>,<83 4>, - <84 4>,<85 4>,<86 4>,<87 4>,<88 4>, - <89 4>,<90 4>,<91 4>,<92 4>,<93 4>, - <94 4>,<95 4>,<96 4>,<97 4>,<98 4>, - <99 4>,<100 4>,<101 4>,<102 4>,<103 4>, - <104 4>,<105 4>,<106 4>,<107 4>,<108 4>, - <109 4>,<110 4>,<111 4>,<112 4>,<113 4>, - <114 4>,<115 4>,<116 4>,<117 4>,<118 4>, - <119 4>,<120 4>,<121 4>,<122 4>,<123 4>, - <124 4>,<125 4>,<126 4>,<127 4>,<128 4>, - <129 4>,<130 4>,<131 4>,<132 4>,<133 4>, - <134 4>,<135 4>,<136 4>,<137 4>,<138 4>, - <139 4>,<140 4>,<141 4>,<142 4>,<143 4>, - <144 4>,<145 4>,<146 4>,<147 4>,<148 4>, - <149 4>,<150 4>,<151 4>,<152 4>,<153 4>, - <154 4>,<155 4>,<156 4>,<157 4>,<158 4>, - <159 4>,<576 1>,<577 1>,<578 1>,<579 1>, - <580 1>,<581 1>,<582 1>,<583 1>,<584 1>, - <585 1>,<586 1>,<587 1>,<588 1>,<589 1>, - <590 1>,<591 1>,<592 1>,<593 1>,<594 1>, - <595 1>,<596 1>,<597 1>,<598 1>,<599 1>, - <600 1>,<601 1>,<602 1>,<603 1>,<604 1>, - <605 1>,<606 1>,<607 1>; - status = "disabled"; - }; - - sas2: sas@a3000000 { - compatible = "hisilicon,hip07-sas-v2"; - reg = <0 0xa3000000 0 0x10000>; - sas-addr = [50 01 88 20 16 00 00 00]; - hisilicon,sas-syscon = <&pcie_subctl>; - ctrl-reset-reg = <0xae0>; - ctrl-reset-sts-reg = <0x5a70>; - ctrl-clock-ena-reg = <0x3a8>; - queue-count = <16>; - phy-count = <9>; - dma-coherent; - interrupt-parent = <&mbigen_sas2>; - interrupts = <192 4>,<193 4>,<194 4>,<195 4>,<196 4>, - <197 4>,<198 4>,<199 4>,<200 4>,<201 4>, - <202 4>,<203 4>,<204 4>,<205 4>,<206 4>, - <207 4>,<208 4>,<209 4>,<210 4>,<211 4>, - <212 4>,<213 4>,<214 4>,<215 4>,<216 4>, - <217 4>,<218 4>,<219 4>,<220 4>,<221 4>, - <222 4>,<223 4>,<224 4>,<225 4>,<226 4>, - <227 4>,<228 4>,<229 4>,<230 4>,<231 4>, - <232 4>,<233 4>,<234 4>,<235 4>,<236 4>, - <237 4>,<238 4>,<239 4>,<240 4>,<241 4>, - <242 4>,<243 4>,<244 4>,<245 4>,<246 4>, - <247 4>,<248 4>,<249 4>,<250 4>,<251 4>, - <252 4>,<253 4>,<254 4>,<255 4>,<256 4>, - <257 4>,<258 4>,<259 4>,<260 4>,<261 4>, - <262 4>,<263 4>,<264 4>,<265 4>,<266 4>, - <267 4>,<268 4>,<269 4>,<270 4>,<271 4>, - <272 4>,<273 4>,<274 4>,<275 4>,<276 4>, - <277 4>,<278 4>,<279 4>,<280 4>,<281 4>, - <282 4>,<283 4>,<284 4>,<285 4>,<286 4>, - <287 4>,<608 1>,<609 1>,<610 1>,<611 1>, - <612 1>,<613 1>,<614 1>,<615 1>,<616 1>, - <617 1>,<618 1>,<619 1>,<620 1>,<621 1>, - <622 1>,<623 1>,<624 1>,<625 1>,<626 1>, - <627 1>,<628 1>,<629 1>,<630 1>,<631 1>, - <632 1>,<633 1>,<634 1>,<635 1>,<636 1>, - <637 1>,<638 1>,<639 1>; - status = "disabled"; - }; - - p0_pcie2_a: pcie@a00a0000 { - compatible = "hisilicon,hip07-pcie-ecam"; - reg = <0 0xaf800000 0 0x800000>, - <0 0xa00a0000 0 0x10000>; - bus-range = <0xf8 0xff>; - msi-map = <0xf800 &p0_its_dsa_a 0xf800 0x800>; - msi-map-mask = <0xffff>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - dma-coherent; - ranges = <0x02000000 0 0xa8000000 0 0xa8000000 0 0x77f0000 - 0x01000000 0 0 0 0xaf7f0000 0 0x10000>; - #interrupt-cells = <1>; - interrupt-map-mask = <0xf800 0 0 7>; - interrupt-map = <0x0 0 0 1 &mbigen_pcie2_a 671 4 - 0x0 0 0 2 &mbigen_pcie2_a 671 4 - 0x0 0 0 3 &mbigen_pcie2_a 671 4 - 0x0 0 0 4 &mbigen_pcie2_a 671 4>; - status = "disabled"; - }; - p0_sec_a: crypto@d2000000 { - compatible = "hisilicon,hip07-sec"; - reg = <0x0 0xd0000000 0x0 0x10000 - 0x0 0xd2000000 0x0 0x10000 - 0x0 0xd2010000 0x0 0x10000 - 0x0 0xd2020000 0x0 0x10000 - 0x0 0xd2030000 0x0 0x10000 - 0x0 0xd2040000 0x0 0x10000 - 0x0 0xd2050000 0x0 0x10000 - 0x0 0xd2060000 0x0 0x10000 - 0x0 0xd2070000 0x0 0x10000 - 0x0 0xd2080000 0x0 0x10000 - 0x0 0xd2090000 0x0 0x10000 - 0x0 0xd20a0000 0x0 0x10000 - 0x0 0xd20b0000 0x0 0x10000 - 0x0 0xd20c0000 0x0 0x10000 - 0x0 0xd20d0000 0x0 0x10000 - 0x0 0xd20e0000 0x0 0x10000 - 0x0 0xd20f0000 0x0 0x10000 - 0x0 0xd2100000 0x0 0x10000>; - interrupt-parent = <&p0_mbigen_sec_a>; - iommus = <&p0_smmu_alg_a 0x600>; - dma-coherent; - interrupts = <576 4>, - <577 1>, <578 4>, - <579 1>, <580 4>, - <581 1>, <582 4>, - <583 1>, <584 4>, - <585 1>, <586 4>, - <587 1>, <588 4>, - <589 1>, <590 4>, - <591 1>, <592 4>, - <593 1>, <594 4>, - <595 1>, <596 4>, - <597 1>, <598 4>, - <599 1>, <600 4>, - <601 1>, <602 4>, - <603 1>, <604 4>, - <605 1>, <606 4>, - <607 1>, <608 4>; - }; - p0_sec_b: crypto@8,d2000000 { - compatible = "hisilicon,hip07-sec"; - reg = <0x8 0xd0000000 0x0 0x10000 - 0x8 0xd2000000 0x0 0x10000 - 0x8 0xd2010000 0x0 0x10000 - 0x8 0xd2020000 0x0 0x10000 - 0x8 0xd2030000 0x0 0x10000 - 0x8 0xd2040000 0x0 0x10000 - 0x8 0xd2050000 0x0 0x10000 - 0x8 0xd2060000 0x0 0x10000 - 0x8 0xd2070000 0x0 0x10000 - 0x8 0xd2080000 0x0 0x10000 - 0x8 0xd2090000 0x0 0x10000 - 0x8 0xd20a0000 0x0 0x10000 - 0x8 0xd20b0000 0x0 0x10000 - 0x8 0xd20c0000 0x0 0x10000 - 0x8 0xd20d0000 0x0 0x10000 - 0x8 0xd20e0000 0x0 0x10000 - 0x8 0xd20f0000 0x0 0x10000 - 0x8 0xd2100000 0x0 0x10000>; - interrupt-parent = <&p0_mbigen_sec_b>; - iommus = <&p0_smmu_alg_b 0x600>; - dma-coherent; - interrupts = <576 4>, - <577 1>, <578 4>, - <579 1>, <580 4>, - <581 1>, <582 4>, - <583 1>, <584 4>, - <585 1>, <586 4>, - <587 1>, <588 4>, - <589 1>, <590 4>, - <591 1>, <592 4>, - <593 1>, <594 4>, - <595 1>, <596 4>, - <597 1>, <598 4>, - <599 1>, <600 4>, - <601 1>, <602 4>, - <603 1>, <604 4>, - <605 1>, <606 4>, - <607 1>, <608 4>; - }; - p1_sec_a: crypto@400,d2000000 { - compatible = "hisilicon,hip07-sec"; - reg = <0x400 0xd0000000 0x0 0x10000 - 0x400 0xd2000000 0x0 0x10000 - 0x400 0xd2010000 0x0 0x10000 - 0x400 0xd2020000 0x0 0x10000 - 0x400 0xd2030000 0x0 0x10000 - 0x400 0xd2040000 0x0 0x10000 - 0x400 0xd2050000 0x0 0x10000 - 0x400 0xd2060000 0x0 0x10000 - 0x400 0xd2070000 0x0 0x10000 - 0x400 0xd2080000 0x0 0x10000 - 0x400 0xd2090000 0x0 0x10000 - 0x400 0xd20a0000 0x0 0x10000 - 0x400 0xd20b0000 0x0 0x10000 - 0x400 0xd20c0000 0x0 0x10000 - 0x400 0xd20d0000 0x0 0x10000 - 0x400 0xd20e0000 0x0 0x10000 - 0x400 0xd20f0000 0x0 0x10000 - 0x400 0xd2100000 0x0 0x10000>; - interrupt-parent = <&p1_mbigen_sec_a>; - iommus = <&p1_smmu_alg_a 0x600>; - dma-coherent; - interrupts = <576 4>, - <577 1>, <578 4>, - <579 1>, <580 4>, - <581 1>, <582 4>, - <583 1>, <584 4>, - <585 1>, <586 4>, - <587 1>, <588 4>, - <589 1>, <590 4>, - <591 1>, <592 4>, - <593 1>, <594 4>, - <595 1>, <596 4>, - <597 1>, <598 4>, - <599 1>, <600 4>, - <601 1>, <602 4>, - <603 1>, <604 4>, - <605 1>, <606 4>, - <607 1>, <608 4>; - }; - p1_sec_b: crypto@408,d2000000 { - compatible = "hisilicon,hip07-sec"; - reg = <0x408 0xd0000000 0x0 0x10000 - 0x408 0xd2000000 0x0 0x10000 - 0x408 0xd2010000 0x0 0x10000 - 0x408 0xd2020000 0x0 0x10000 - 0x408 0xd2030000 0x0 0x10000 - 0x408 0xd2040000 0x0 0x10000 - 0x408 0xd2050000 0x0 0x10000 - 0x408 0xd2060000 0x0 0x10000 - 0x408 0xd2070000 0x0 0x10000 - 0x408 0xd2080000 0x0 0x10000 - 0x408 0xd2090000 0x0 0x10000 - 0x408 0xd20a0000 0x0 0x10000 - 0x408 0xd20b0000 0x0 0x10000 - 0x408 0xd20c0000 0x0 0x10000 - 0x408 0xd20d0000 0x0 0x10000 - 0x408 0xd20e0000 0x0 0x10000 - 0x408 0xd20f0000 0x0 0x10000 - 0x408 0xd2100000 0x0 0x10000>; - interrupt-parent = <&p1_mbigen_sec_b>; - iommus = <&p1_smmu_alg_b 0x600>; - dma-coherent; - interrupts = <576 4>, - <577 1>, <578 4>, - <579 1>, <580 4>, - <581 1>, <582 4>, - <583 1>, <584 4>, - <585 1>, <586 4>, - <587 1>, <588 4>, - <589 1>, <590 4>, - <591 1>, <592 4>, - <593 1>, <594 4>, - <595 1>, <596 4>, - <597 1>, <598 4>, - <599 1>, <600 4>, - <601 1>, <602 4>, - <603 1>, <604 4>, - <605 1>, <606 4>, - <607 1>, <608 4>; - }; - - }; -}; diff --git a/sys/gnu/dts/arm64/hisilicon/poplar-pinctrl.dtsi b/sys/gnu/dts/arm64/hisilicon/poplar-pinctrl.dtsi deleted file mode 100644 index 7bb19e4b084..00000000000 --- a/sys/gnu/dts/arm64/hisilicon/poplar-pinctrl.dtsi +++ /dev/null @@ -1,98 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Pinctrl dts file for HiSilicon Poplar board - * - * Copyright (c) 2016-2018 HiSilicon Technologies Co., Ltd. - */ - -#include - -/* value, enable bits, disable bits, mask */ -#define PINCTRL_PULLDOWN(value, enable, disable, mask) \ - (value << 13) (enable << 13) (disable << 13) (mask << 13) -#define PINCTRL_PULLUP(value, enable, disable, mask) \ - (value << 12) (enable << 12) (disable << 12) (mask << 12) -#define PINCTRL_SLEW_RATE(value, mask) (value << 8) (mask << 8) -#define PINCTRL_DRV_STRENGTH(value, mask) (value << 4) (mask << 4) - -&pmx0 { - emmc_pins_1: emmc-pins-1 { - pinctrl-single,pins = < - 0x000 MUX_M2 - 0x004 MUX_M2 - 0x008 MUX_M2 - 0x00c MUX_M2 - 0x010 MUX_M2 - 0x014 MUX_M2 - 0x018 MUX_M2 - 0x01c MUX_M2 - 0x024 MUX_M2 - >; - pinctrl-single,bias-pulldown = < - PINCTRL_PULLDOWN(0, 1, 0, 1) - >; - pinctrl-single,bias-pullup = < - PINCTRL_PULLUP(0, 1, 0, 1) - >; - pinctrl-single,slew-rate = < - PINCTRL_SLEW_RATE(1, 1) - >; - pinctrl-single,drive-strength = < - PINCTRL_DRV_STRENGTH(0xb, 0xf) - >; - }; - - emmc_pins_2: emmc-pins-2 { - pinctrl-single,pins = < - 0x028 MUX_M2 - >; - pinctrl-single,bias-pulldown = < - PINCTRL_PULLDOWN(0, 1, 0, 1) - >; - pinctrl-single,bias-pullup = < - PINCTRL_PULLUP(0, 1, 0, 1) - >; - pinctrl-single,slew-rate = < - PINCTRL_SLEW_RATE(1, 1) - >; - pinctrl-single,drive-strength = < - PINCTRL_DRV_STRENGTH(0x9, 0xf) - >; - }; - - emmc_pins_3: emmc-pins-3 { - pinctrl-single,pins = < - 0x02c MUX_M2 - >; - pinctrl-single,bias-pulldown = < - PINCTRL_PULLDOWN(0, 1, 0, 1) - >; - pinctrl-single,bias-pullup = < - PINCTRL_PULLUP(0, 1, 0, 1) - >; - pinctrl-single,slew-rate = < - PINCTRL_SLEW_RATE(1, 1) - >; - pinctrl-single,drive-strength = < - PINCTRL_DRV_STRENGTH(3, 3) - >; - }; - - emmc_pins_4: emmc-pins-4 { - pinctrl-single,pins = < - 0x030 MUX_M2 - >; - pinctrl-single,bias-pulldown = < - PINCTRL_PULLDOWN(1, 1, 0, 1) - >; - pinctrl-single,bias-pullup = < - PINCTRL_PULLUP(0, 1, 0, 1) - >; - pinctrl-single,slew-rate = < - PINCTRL_SLEW_RATE(1, 1) - >; - pinctrl-single,drive-strength = < - PINCTRL_DRV_STRENGTH(3, 3) - >; - }; -}; diff --git a/sys/gnu/dts/arm64/intel/socfpga_agilex.dtsi b/sys/gnu/dts/arm64/intel/socfpga_agilex.dtsi deleted file mode 100644 index d8c44d3ca15..00000000000 --- a/sys/gnu/dts/arm64/intel/socfpga_agilex.dtsi +++ /dev/null @@ -1,552 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2019, Intel Corporation - */ - -/dts-v1/; -#include -#include - -/ { - compatible = "intel,socfpga-agilex"; - #address-cells = <2>; - #size-cells = <2>; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - service_reserved: svcbuffer@0 { - compatible = "shared-dma-pool"; - reg = <0x0 0x0 0x0 0x1000000>; - alignment = <0x1000>; - no-map; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - enable-method = "psci"; - reg = <0x0>; - }; - - cpu1: cpu@1 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - enable-method = "psci"; - reg = <0x1>; - }; - - cpu2: cpu@2 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - enable-method = "psci"; - reg = <0x2>; - }; - - cpu3: cpu@3 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - enable-method = "psci"; - reg = <0x3>; - }; - }; - - pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = <0 170 4>, - <0 171 4>, - <0 172 4>, - <0 173 4>; - interrupt-affinity = <&cpu0>, - <&cpu1>, - <&cpu2>, - <&cpu3>; - interrupt-parent = <&intc>; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - intc: intc@fffc1000 { - compatible = "arm,gic-400", "arm,cortex-a15-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x0 0xfffc1000 0x0 0x1000>, - <0x0 0xfffc2000 0x0 0x2000>, - <0x0 0xfffc4000 0x0 0x2000>, - <0x0 0xfffc6000 0x0 0x2000>; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - device_type = "soc"; - interrupt-parent = <&intc>; - ranges = <0 0 0 0xffffffff>; - - base_fpga_region { - #address-cells = <0x1>; - #size-cells = <0x1>; - compatible = "fpga-region"; - fpga-mgr = <&fpga_mgr>; - }; - - gmac0: ethernet@ff800000 { - compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac"; - reg = <0xff800000 0x2000>; - interrupts = <0 90 4>; - interrupt-names = "macirq"; - mac-address = [00 00 00 00 00 00]; - resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>; - reset-names = "stmmaceth", "stmmaceth-ocp"; - tx-fifo-depth = <16384>; - rx-fifo-depth = <16384>; - snps,multicast-filter-bins = <256>; - iommus = <&smmu 1>; - altr,sysmgr-syscon = <&sysmgr 0x44 0>; - status = "disabled"; - }; - - gmac1: ethernet@ff802000 { - compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac"; - reg = <0xff802000 0x2000>; - interrupts = <0 91 4>; - interrupt-names = "macirq"; - mac-address = [00 00 00 00 00 00]; - resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>; - reset-names = "stmmaceth", "stmmaceth-ocp"; - tx-fifo-depth = <16384>; - rx-fifo-depth = <16384>; - snps,multicast-filter-bins = <256>; - iommus = <&smmu 2>; - altr,sysmgr-syscon = <&sysmgr 0x48 8>; - status = "disabled"; - }; - - gmac2: ethernet@ff804000 { - compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac"; - reg = <0xff804000 0x2000>; - interrupts = <0 92 4>; - interrupt-names = "macirq"; - mac-address = [00 00 00 00 00 00]; - resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>; - reset-names = "stmmaceth", "stmmaceth-ocp"; - tx-fifo-depth = <16384>; - rx-fifo-depth = <16384>; - snps,multicast-filter-bins = <256>; - iommus = <&smmu 3>; - altr,sysmgr-syscon = <&sysmgr 0x4c 16>; - status = "disabled"; - }; - - gpio0: gpio@ffc03200 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dw-apb-gpio"; - reg = <0xffc03200 0x100>; - resets = <&rst GPIO0_RESET>; - status = "disabled"; - - porta: gpio-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <24>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <0 110 4>; - }; - }; - - gpio1: gpio@ffc03300 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dw-apb-gpio"; - reg = <0xffc03300 0x100>; - resets = <&rst GPIO1_RESET>; - status = "disabled"; - - portb: gpio-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <24>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <0 111 4>; - }; - }; - - i2c0: i2c@ffc02800 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0xffc02800 0x100>; - interrupts = <0 103 4>; - resets = <&rst I2C0_RESET>; - status = "disabled"; - }; - - i2c1: i2c@ffc02900 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0xffc02900 0x100>; - interrupts = <0 104 4>; - resets = <&rst I2C1_RESET>; - status = "disabled"; - }; - - i2c2: i2c@ffc02a00 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0xffc02a00 0x100>; - interrupts = <0 105 4>; - resets = <&rst I2C2_RESET>; - status = "disabled"; - }; - - i2c3: i2c@ffc02b00 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0xffc02b00 0x100>; - interrupts = <0 106 4>; - resets = <&rst I2C3_RESET>; - status = "disabled"; - }; - - i2c4: i2c@ffc02c00 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0xffc02c00 0x100>; - interrupts = <0 107 4>; - resets = <&rst I2C4_RESET>; - status = "disabled"; - }; - - mmc: dwmmc0@ff808000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "altr,socfpga-dw-mshc"; - reg = <0xff808000 0x1000>; - interrupts = <0 96 4>; - fifo-depth = <0x400>; - resets = <&rst SDMMC_RESET>; - reset-names = "reset"; - iommus = <&smmu 5>; - status = "disabled"; - }; - - nand: nand@ffb90000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "altr,socfpga-denali-nand"; - reg = <0xffb90000 0x10000>, - <0xffb80000 0x1000>; - reg-names = "nand_data", "denali_reg"; - interrupts = <0 97 4>; - resets = <&rst NAND_RESET>, <&rst NAND_OCP_RESET>; - status = "disabled"; - }; - - ocram: sram@ffe00000 { - compatible = "mmio-sram"; - reg = <0xffe00000 0x40000>; - }; - - pdma: pdma@ffda0000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0xffda0000 0x1000>; - interrupts = <0 81 4>, - <0 82 4>, - <0 83 4>, - <0 84 4>, - <0 85 4>, - <0 86 4>, - <0 87 4>, - <0 88 4>, - <0 89 4>; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; - resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>; - reset-names = "dma", "dma-ocp"; - }; - - rst: rstmgr@ffd11000 { - #reset-cells = <1>; - compatible = "altr,stratix10-rst-mgr"; - reg = <0xffd11000 0x100>; - }; - - smmu: iommu@fa000000 { - compatible = "arm,mmu-500", "arm,smmu-v2"; - reg = <0xfa000000 0x40000>; - #global-interrupts = <2>; - #iommu-cells = <1>; - interrupt-parent = <&intc>; - interrupts = <0 128 4>, /* Global Secure Fault */ - <0 129 4>, /* Global Non-secure Fault */ - /* Non-secure Context Interrupts (32) */ - <0 138 4>, <0 139 4>, <0 140 4>, <0 141 4>, - <0 142 4>, <0 143 4>, <0 144 4>, <0 145 4>, - <0 146 4>, <0 147 4>, <0 148 4>, <0 149 4>, - <0 150 4>, <0 151 4>, <0 152 4>, <0 153 4>, - <0 154 4>, <0 155 4>, <0 156 4>, <0 157 4>, - <0 158 4>, <0 159 4>, <0 160 4>, <0 161 4>, - <0 162 4>, <0 163 4>, <0 164 4>, <0 165 4>, - <0 166 4>, <0 167 4>, <0 168 4>, <0 169 4>; - stream-match-mask = <0x7ff0>; - status = "disabled"; - }; - - spi0: spi@ffda4000 { - compatible = "snps,dw-apb-ssi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xffda4000 0x1000>; - interrupts = <0 99 4>; - resets = <&rst SPIM0_RESET>; - reg-io-width = <4>; - num-cs = <4>; - status = "disabled"; - }; - - spi1: spi@ffda5000 { - compatible = "snps,dw-apb-ssi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xffda5000 0x1000>; - interrupts = <0 100 4>; - resets = <&rst SPIM1_RESET>; - reg-io-width = <4>; - num-cs = <4>; - status = "disabled"; - }; - - sysmgr: sysmgr@ffd12000 { - compatible = "altr,sys-mgr-s10","altr,sys-mgr"; - reg = <0xffd12000 0x500>; - }; - - /* Local timer */ - timer { - compatible = "arm,armv8-timer"; - interrupts = <1 13 0xf08>, - <1 14 0xf08>, - <1 11 0xf08>, - <1 10 0xf08>; - }; - - timer0: timer0@ffc03000 { - compatible = "snps,dw-apb-timer"; - interrupts = <0 113 4>; - reg = <0xffc03000 0x100>; - }; - - timer1: timer1@ffc03100 { - compatible = "snps,dw-apb-timer"; - interrupts = <0 114 4>; - reg = <0xffc03100 0x100>; - }; - - timer2: timer2@ffd00000 { - compatible = "snps,dw-apb-timer"; - interrupts = <0 115 4>; - reg = <0xffd00000 0x100>; - }; - - timer3: timer3@ffd00100 { - compatible = "snps,dw-apb-timer"; - interrupts = <0 116 4>; - reg = <0xffd00100 0x100>; - }; - - uart0: serial0@ffc02000 { - compatible = "snps,dw-apb-uart"; - reg = <0xffc02000 0x100>; - interrupts = <0 108 4>; - reg-shift = <2>; - reg-io-width = <4>; - resets = <&rst UART0_RESET>; - status = "disabled"; - }; - - uart1: serial1@ffc02100 { - compatible = "snps,dw-apb-uart"; - reg = <0xffc02100 0x100>; - interrupts = <0 109 4>; - reg-shift = <2>; - reg-io-width = <4>; - resets = <&rst UART1_RESET>; - status = "disabled"; - }; - - usbphy0: usbphy@0 { - #phy-cells = <0>; - compatible = "usb-nop-xceiv"; - status = "okay"; - }; - - usb0: usb@ffb00000 { - compatible = "snps,dwc2"; - reg = <0xffb00000 0x40000>; - interrupts = <0 93 4>; - phys = <&usbphy0>; - phy-names = "usb2-phy"; - resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>; - reset-names = "dwc2", "dwc2-ecc"; - iommus = <&smmu 6>; - status = "disabled"; - }; - - usb1: usb@ffb40000 { - compatible = "snps,dwc2"; - reg = <0xffb40000 0x40000>; - interrupts = <0 94 4>; - phys = <&usbphy0>; - phy-names = "usb2-phy"; - resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>; - reset-names = "dwc2", "dwc2-ecc"; - iommus = <&smmu 7>; - status = "disabled"; - }; - - watchdog0: watchdog@ffd00200 { - compatible = "snps,dw-wdt"; - reg = <0xffd00200 0x100>; - interrupts = <0 117 4>; - resets = <&rst WATCHDOG0_RESET>; - status = "disabled"; - }; - - watchdog1: watchdog@ffd00300 { - compatible = "snps,dw-wdt"; - reg = <0xffd00300 0x100>; - interrupts = <0 118 4>; - resets = <&rst WATCHDOG1_RESET>; - status = "disabled"; - }; - - watchdog2: watchdog@ffd00400 { - compatible = "snps,dw-wdt"; - reg = <0xffd00400 0x100>; - interrupts = <0 125 4>; - resets = <&rst WATCHDOG2_RESET>; - status = "disabled"; - }; - - watchdog3: watchdog@ffd00500 { - compatible = "snps,dw-wdt"; - reg = <0xffd00500 0x100>; - interrupts = <0 126 4>; - resets = <&rst WATCHDOG3_RESET>; - status = "disabled"; - }; - - sdr: sdr@f8011100 { - compatible = "altr,sdr-ctl", "syscon"; - reg = <0xf8011100 0xc0>; - }; - - eccmgr { - compatible = "altr,socfpga-s10-ecc-manager", - "altr,socfpga-a10-ecc-manager"; - altr,sysmgr-syscon = <&sysmgr>; - #address-cells = <1>; - #size-cells = <1>; - interrupts = <0 15 4>; - interrupt-controller; - #interrupt-cells = <2>; - ranges; - - sdramedac { - compatible = "altr,sdram-edac-s10"; - altr,sdr-syscon = <&sdr>; - interrupts = <16 4>; - }; - - ocram-ecc@ff8cc000 { - compatible = "altr,socfpga-s10-ocram-ecc", - "altr,socfpga-a10-ocram-ecc"; - reg = <0xff8cc000 0x100>; - altr,ecc-parent = <&ocram>; - interrupts = <1 4>; - }; - - usb0-ecc@ff8c4000 { - compatible = "altr,socfpga-s10-usb-ecc", - "altr,socfpga-usb-ecc"; - reg = <0xff8c4000 0x100>; - altr,ecc-parent = <&usb0>; - interrupts = <2 4>; - }; - - emac0-rx-ecc@ff8c0000 { - compatible = "altr,socfpga-s10-eth-mac-ecc", - "altr,socfpga-eth-mac-ecc"; - reg = <0xff8c0000 0x100>; - altr,ecc-parent = <&gmac0>; - interrupts = <4 4>; - }; - - emac0-tx-ecc@ff8c0400 { - compatible = "altr,socfpga-s10-eth-mac-ecc", - "altr,socfpga-eth-mac-ecc"; - reg = <0xff8c0400 0x100>; - altr,ecc-parent = <&gmac0>; - interrupts = <5 4>; - }; - - sdmmca-ecc@ff8c8c00 { - compatible = "altr,socfpga-s10-sdmmc-ecc", - "altr,socfpga-sdmmc-ecc"; - reg = <0xff8c8c00 0x100>; - altr,ecc-parent = <&mmc>; - interrupts = <14 4>, - <15 4>; - }; - }; - - qspi: spi@ff8d2000 { - compatible = "cdns,qspi-nor"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xff8d2000 0x100>, - <0xff900000 0x100000>; - interrupts = <0 3 4>; - cdns,fifo-depth = <128>; - cdns,fifo-width = <4>; - cdns,trigger-address = <0x00000000>; - - status = "disabled"; - }; - - firmware { - svc { - compatible = "intel,stratix10-svc"; - method = "smc"; - memory-region = <&service_reserved>; - - fpga_mgr: fpga-mgr { - compatible = "intel,stratix10-soc-fpga-mgr"; - }; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/intel/socfpga_agilex_socdk.dts b/sys/gnu/dts/arm64/intel/socfpga_agilex_socdk.dts deleted file mode 100644 index e794a12ba7c..00000000000 --- a/sys/gnu/dts/arm64/intel/socfpga_agilex_socdk.dts +++ /dev/null @@ -1,133 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2019, Intel Corporation - */ -#include "socfpga_agilex.dtsi" - -/ { - model = "SoCFPGA Agilex SoCDK"; - - aliases { - serial0 = &uart0; - ethernet0 = &gmac0; - ethernet1 = &gmac1; - ethernet2 = &gmac2; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - hps0 { - label = "hps_led0"; - gpios = <&portb 20 GPIO_ACTIVE_HIGH>; - }; - - hps1 { - label = "hps_led1"; - gpios = <&portb 19 GPIO_ACTIVE_HIGH>; - }; - - hps2 { - label = "hps_led2"; - gpios = <&portb 21 GPIO_ACTIVE_HIGH>; - }; - }; - - memory { - device_type = "memory"; - /* We expect the bootloader to fill in the reg */ - reg = <0 0 0 0>; - }; -}; - -&gpio1 { - status = "okay"; -}; - -&gmac0 { - status = "okay"; - phy-mode = "rgmii"; - phy-handle = <&phy0>; - - max-frame-size = <9000>; - - mdio0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - phy0: ethernet-phy@0 { - reg = <4>; - - txd0-skew-ps = <0>; /* -420ps */ - txd1-skew-ps = <0>; /* -420ps */ - txd2-skew-ps = <0>; /* -420ps */ - txd3-skew-ps = <0>; /* -420ps */ - rxd0-skew-ps = <420>; /* 0ps */ - rxd1-skew-ps = <420>; /* 0ps */ - rxd2-skew-ps = <420>; /* 0ps */ - rxd3-skew-ps = <420>; /* 0ps */ - txen-skew-ps = <0>; /* -420ps */ - txc-skew-ps = <900>; /* 0ps */ - rxdv-skew-ps = <420>; /* 0ps */ - rxc-skew-ps = <1680>; /* 780ps */ - }; - }; -}; - -&mmc { - status = "okay"; - cap-sd-highspeed; - broken-cd; - bus-width = <4>; -}; - -&uart0 { - status = "okay"; -}; - -&usb0 { - status = "okay"; - disable-over-current; -}; - -&watchdog0 { - status = "okay"; -}; - -&qspi { - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "mt25qu02g"; - reg = <0>; - spi-max-frequency = <100000000>; - - m25p,fast-read; - cdns,page-size = <256>; - cdns,block-size = <16>; - cdns,read-delay = <1>; - cdns,tshsl-ns = <50>; - cdns,tsd2d-ns = <50>; - cdns,tchsh-ns = <4>; - cdns,tslch-ns = <4>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - qspi_boot: partition@0 { - label = "Boot and fpga data"; - reg = <0x0 0x034B0000>; - }; - - qspi_rootfs: partition@34B0000 { - label = "Root Filesystem - JFFS2"; - reg = <0x034B0000 0x0EB50000>; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/intel/socfpga_agilex_socdk_nand.dts b/sys/gnu/dts/arm64/intel/socfpga_agilex_socdk_nand.dts deleted file mode 100644 index 979aa59a6bd..00000000000 --- a/sys/gnu/dts/arm64/intel/socfpga_agilex_socdk_nand.dts +++ /dev/null @@ -1,135 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2019, Intel Corporation - */ -#include "socfpga_agilex.dtsi" - -/ { - model = "SoCFPGA Agilex SoCDK"; - - aliases { - serial0 = &uart0; - ethernet0 = &gmac0; - ethernet1 = &gmac1; - ethernet2 = &gmac2; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - hps0 { - label = "hps_led0"; - gpios = <&portb 20 GPIO_ACTIVE_HIGH>; - }; - - hps1 { - label = "hps_led1"; - gpios = <&portb 19 GPIO_ACTIVE_HIGH>; - }; - - hps2 { - label = "hps_led2"; - gpios = <&portb 21 GPIO_ACTIVE_HIGH>; - }; - }; - - memory { - device_type = "memory"; - /* We expect the bootloader to fill in the reg */ - reg = <0 0 0 0>; - }; - - soc { - clocks { - osc1 { - clock-frequency = <25000000>; - }; - }; - }; -}; - -&gpio1 { - status = "okay"; -}; - -&gmac2 { - status = "okay"; - phy-mode = "rgmii"; - phy-handle = <&phy0>; - - max-frame-size = <9000>; - - mdio0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - phy0: ethernet-phy@0 { - reg = <4>; - - txd0-skew-ps = <0>; /* -420ps */ - txd1-skew-ps = <0>; /* -420ps */ - txd2-skew-ps = <0>; /* -420ps */ - txd3-skew-ps = <0>; /* -420ps */ - rxd0-skew-ps = <420>; /* 0ps */ - rxd1-skew-ps = <420>; /* 0ps */ - rxd2-skew-ps = <420>; /* 0ps */ - rxd3-skew-ps = <420>; /* 0ps */ - txen-skew-ps = <0>; /* -420ps */ - txc-skew-ps = <900>; /* 0ps */ - rxdv-skew-ps = <420>; /* 0ps */ - rxc-skew-ps = <1680>; /* 780ps */ - }; - }; -}; - -&nand { - status = "okay"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - reg = <0>; - nand-bus-width = <16>; - - partition@0 { - label = "u-boot"; - reg = <0 0x200000>; - }; - partition@200000 { - label = "env"; - reg = <0x200000 0x40000>; - }; - partition@240000 { - label = "dtb"; - reg = <0x240000 0x40000>; - }; - partition@280000 { - label = "kernel"; - reg = <0x280000 0x2000000>; - }; - partition@2280000 { - label = "misc"; - reg = <0x2280000 0x2000000>; - }; - partition@4280000 { - label = "rootfs"; - reg = <0x4280000 0x3bd80000>; - }; - }; -}; - -&uart0 { - status = "okay"; -}; - -&usb0 { - status = "okay"; - disable-over-current; -}; - -&watchdog0 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/lg/lg1312-ref.dts b/sys/gnu/dts/arm64/lg/lg1312-ref.dts deleted file mode 100644 index 260a2c5b19e..00000000000 --- a/sys/gnu/dts/arm64/lg/lg1312-ref.dts +++ /dev/null @@ -1,37 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * dts file for lg1312 Reference Board. - * - * Copyright (C) 2016, LG Electronics - */ - -/dts-v1/; - -#include "lg1312.dtsi" - -/ { - #address-cells = <2>; - #size-cells = <1>; - - model = "LG Electronics, DTV SoC LG1312 Reference Board"; - compatible = "lge,lg1312-ref", "lge,lg1312"; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - }; - - memory { - device_type = "memory"; - reg = <0x0 0x00000000 0x20000000>; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/lg/lg1312.dtsi b/sys/gnu/dts/arm64/lg/lg1312.dtsi deleted file mode 100644 index 64f3b135068..00000000000 --- a/sys/gnu/dts/arm64/lg/lg1312.dtsi +++ /dev/null @@ -1,352 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * dts file for lg1312 SoC - * - * Copyright (C) 2016, LG Electronics - */ - -#include -#include - -/ { - #address-cells = <2>; - #size-cells = <2>; - - compatible = "lge,lg1312"; - interrupt-parent = <&gic>; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x0>; - next-level-cache = <&L2_0>; - }; - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x1>; - enable-method = "psci"; - next-level-cache = <&L2_0>; - }; - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x2>; - enable-method = "psci"; - next-level-cache = <&L2_0>; - }; - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x3>; - enable-method = "psci"; - next-level-cache = <&L2_0>; - }; - L2_0: l2-cache0 { - compatible = "cache"; - }; - }; - - psci { - compatible = "arm,psci-0.2", "arm,psci"; - method = "smc"; - cpu_suspend = <0x84000001>; - cpu_off = <0x84000002>; - cpu_on = <0x84000003>; - }; - - gic: interrupt-controller@c0001000 { - #interrupt-cells = <3>; - compatible = "arm,gic-400"; - interrupt-controller; - reg = <0x0 0xc0001000 0x1000>, - <0x0 0xc0002000 0x2000>, - <0x0 0xc0004000 0x2000>, - <0x0 0xc0006000 0x2000>; - }; - - pmu { - compatible = "arm,cortex-a53-pmu"; - interrupts = , - , - , - ; - interrupt-affinity = <&cpu0>, - <&cpu1>, - <&cpu2>, - <&cpu3>; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - clk_bus: clk_bus { - #clock-cells = <0>; - - compatible = "fixed-clock"; - clock-frequency = <198000000>; - clock-output-names = "BUSCLK"; - }; - - soc { - #address-cells = <2>; - #size-cells = <1>; - - compatible = "simple-bus"; - interrupt-parent = <&gic>; - ranges; - - eth0: ethernet@c1b00000 { - compatible = "cdns,gem"; - reg = <0x0 0xc1b00000 0x1000>; - interrupts = ; - clocks = <&clk_bus>, <&clk_bus>; - clock-names = "hclk", "pclk"; - phy-mode = "rmii"; - /* Filled in by boot */ - mac-address = [ 00 00 00 00 00 00 ]; - }; - }; - - amba { - #address-cells = <2>; - #size-cells = <1>; - #interrupt-cells = <3>; - - compatible = "simple-bus"; - interrupt-parent = <&gic>; - ranges; - - timers: timer@fd100000 { - compatible = "arm,sp804"; - reg = <0x0 0xfd100000 0x1000>; - interrupts = ; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - }; - wdog: watchdog@fd200000 { - compatible = "arm,sp805", "arm,primecell"; - reg = <0x0 0xfd200000 0x1000>; - interrupts = ; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - }; - uart0: serial@fe000000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0 0xfe000000 0x1000>; - interrupts = ; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - status="disabled"; - }; - uart1: serial@fe100000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0 0xfe100000 0x1000>; - interrupts = ; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - status="disabled"; - }; - uart2: serial@fe200000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0 0xfe200000 0x1000>; - interrupts = ; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - status="disabled"; - }; - spi0: spi@fe800000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x0 0xfe800000 0x1000>; - interrupts = ; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - }; - spi1: spi@fe900000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x0 0xfe900000 0x1000>; - interrupts = ; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - }; - dmac0: dma@c1128000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x0 0xc1128000 0x1000>; - interrupts = ; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - }; - gpio0: gpio@fd400000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0x0 0xfd400000 0x1000>; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - status="disabled"; - }; - gpio1: gpio@fd410000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0x0 0xfd410000 0x1000>; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - status="disabled"; - }; - gpio2: gpio@fd420000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0x0 0xfd420000 0x1000>; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - status="disabled"; - }; - gpio3: gpio@fd430000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0x0 0xfd430000 0x1000>; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - }; - gpio4: gpio@fd440000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0x0 0xfd440000 0x1000>; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - status="disabled"; - }; - gpio5: gpio@fd450000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0x0 0xfd450000 0x1000>; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - status="disabled"; - }; - gpio6: gpio@fd460000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0x0 0xfd460000 0x1000>; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - status="disabled"; - }; - gpio7: gpio@fd470000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0x0 0xfd470000 0x1000>; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - status="disabled"; - }; - gpio8: gpio@fd480000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0x0 0xfd480000 0x1000>; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - status="disabled"; - }; - gpio9: gpio@fd490000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0x0 0xfd490000 0x1000>; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - status="disabled"; - }; - gpio10: gpio@fd4a0000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0x0 0xfd4a0000 0x1000>; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - status="disabled"; - }; - gpio11: gpio@fd4b0000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0x0 0xfd4b0000 0x1000>; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - }; - gpio12: gpio@fd4c0000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0x0 0xfd4c0000 0x1000>; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - status="disabled"; - }; - gpio13: gpio@fd4d0000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0x0 0xfd4d0000 0x1000>; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - status="disabled"; - }; - gpio14: gpio@fd4e0000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0x0 0xfd4e0000 0x1000>; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - status="disabled"; - }; - gpio15: gpio@fd4f0000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0x0 0xfd4f0000 0x1000>; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - status="disabled"; - }; - gpio16: gpio@fd500000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0x0 0xfd500000 0x1000>; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - status="disabled"; - }; - gpio17: gpio@fd510000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0x0 0xfd510000 0x1000>; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/lg/lg1313-ref.dts b/sys/gnu/dts/arm64/lg/lg1313-ref.dts deleted file mode 100644 index e89ae853788..00000000000 --- a/sys/gnu/dts/arm64/lg/lg1313-ref.dts +++ /dev/null @@ -1,37 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * dts file for lg1313 Reference Board. - * - * Copyright (C) 2016, LG Electronics - */ - -/dts-v1/; - -#include "lg1313.dtsi" - -/ { - #address-cells = <2>; - #size-cells = <1>; - - model = "LG Electronics, DTV SoC LG1313 Reference Board"; - compatible = "lge,lg1313-ref", "lge,lg1313"; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - }; - - memory { - device_type = "memory"; - reg = <0x0 0x00000000 0x20000000>; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/lg/lg1313.dtsi b/sys/gnu/dts/arm64/lg/lg1313.dtsi deleted file mode 100644 index ac23592ab01..00000000000 --- a/sys/gnu/dts/arm64/lg/lg1313.dtsi +++ /dev/null @@ -1,352 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * dts file for lg1313 SoC - * - * Copyright (C) 2016, LG Electronics - */ - -#include -#include - -/ { - #address-cells = <2>; - #size-cells = <2>; - - compatible = "lge,lg1313"; - interrupt-parent = <&gic>; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x0>; - next-level-cache = <&L2_0>; - }; - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x1>; - enable-method = "psci"; - next-level-cache = <&L2_0>; - }; - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x2>; - enable-method = "psci"; - next-level-cache = <&L2_0>; - }; - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x3>; - enable-method = "psci"; - next-level-cache = <&L2_0>; - }; - L2_0: l2-cache0 { - compatible = "cache"; - }; - }; - - psci { - compatible = "arm,psci-0.2", "arm,psci"; - method = "smc"; - cpu_suspend = <0x84000001>; - cpu_off = <0x84000002>; - cpu_on = <0x84000003>; - }; - - gic: interrupt-controller@c0001000 { - #interrupt-cells = <3>; - compatible = "arm,gic-400"; - interrupt-controller; - reg = <0x0 0xc0001000 0x1000>, - <0x0 0xc0002000 0x2000>, - <0x0 0xc0004000 0x2000>, - <0x0 0xc0006000 0x2000>; - }; - - pmu { - compatible = "arm,cortex-a53-pmu"; - interrupts = , - , - , - ; - interrupt-affinity = <&cpu0>, - <&cpu1>, - <&cpu2>, - <&cpu3>; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - clk_bus: clk_bus { - #clock-cells = <0>; - - compatible = "fixed-clock"; - clock-frequency = <198000000>; - clock-output-names = "BUSCLK"; - }; - - soc { - #address-cells = <2>; - #size-cells = <1>; - - compatible = "simple-bus"; - interrupt-parent = <&gic>; - ranges; - - eth0: ethernet@c3700000 { - compatible = "cdns,gem"; - reg = <0x0 0xc3700000 0x1000>; - interrupts = ; - clocks = <&clk_bus>, <&clk_bus>; - clock-names = "hclk", "pclk"; - phy-mode = "rmii"; - /* Filled in by boot */ - mac-address = [ 00 00 00 00 00 00 ]; - }; - }; - - amba { - #address-cells = <2>; - #size-cells = <1>; - #interrupt-cells = <3>; - - compatible = "simple-bus"; - interrupt-parent = <&gic>; - ranges; - - timers: timer@fd100000 { - compatible = "arm,sp804"; - reg = <0x0 0xfd100000 0x1000>; - interrupts = ; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - }; - wdog: watchdog@fd200000 { - compatible = "arm,sp805", "arm,primecell"; - reg = <0x0 0xfd200000 0x1000>; - interrupts = ; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - }; - uart0: serial@fe000000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0 0xfe000000 0x1000>; - interrupts = ; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - status="disabled"; - }; - uart1: serial@fe100000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0 0xfe100000 0x1000>; - interrupts = ; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - status="disabled"; - }; - uart2: serial@fe200000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0 0xfe200000 0x1000>; - interrupts = ; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - status="disabled"; - }; - spi0: spi@fe800000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x0 0xfe800000 0x1000>; - interrupts = ; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - }; - spi1: spi@fe900000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x0 0xfe900000 0x1000>; - interrupts = ; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - }; - dmac0: dma@c1128000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x0 0xc1128000 0x1000>; - interrupts = ; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - }; - gpio0: gpio@fd400000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0x0 0xfd400000 0x1000>; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - status="disabled"; - }; - gpio1: gpio@fd410000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0x0 0xfd410000 0x1000>; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - status="disabled"; - }; - gpio2: gpio@fd420000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0x0 0xfd420000 0x1000>; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - status="disabled"; - }; - gpio3: gpio@fd430000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0x0 0xfd430000 0x1000>; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - }; - gpio4: gpio@fd440000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0x0 0xfd440000 0x1000>; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - status="disabled"; - }; - gpio5: gpio@fd450000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0x0 0xfd450000 0x1000>; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - status="disabled"; - }; - gpio6: gpio@fd460000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0x0 0xfd460000 0x1000>; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - status="disabled"; - }; - gpio7: gpio@fd470000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0x0 0xfd470000 0x1000>; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - status="disabled"; - }; - gpio8: gpio@fd480000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0x0 0xfd480000 0x1000>; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - status="disabled"; - }; - gpio9: gpio@fd490000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0x0 0xfd490000 0x1000>; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - status="disabled"; - }; - gpio10: gpio@fd4a0000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0x0 0xfd4a0000 0x1000>; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - status="disabled"; - }; - gpio11: gpio@fd4b0000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0x0 0xfd4b0000 0x1000>; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - }; - gpio12: gpio@fd4c0000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0x0 0xfd4c0000 0x1000>; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - status="disabled"; - }; - gpio13: gpio@fd4d0000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0x0 0xfd4d0000 0x1000>; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - status="disabled"; - }; - gpio14: gpio@fd4e0000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0x0 0xfd4e0000 0x1000>; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - status="disabled"; - }; - gpio15: gpio@fd4f0000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0x0 0xfd4f0000 0x1000>; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - status="disabled"; - }; - gpio16: gpio@fd500000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0x0 0xfd500000 0x1000>; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - status="disabled"; - }; - gpio17: gpio@fd510000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0x0 0xfd510000 0x1000>; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/marvell/armada-371x.dtsi b/sys/gnu/dts/arm64/marvell/armada-371x.dtsi deleted file mode 100644 index dc1182ec9fa..00000000000 --- a/sys/gnu/dts/arm64/marvell/armada-371x.dtsi +++ /dev/null @@ -1,17 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree Include file for Marvell Armada 371x family of SoCs - * (also named 88F3710) - * - * Copyright (C) 2016 Marvell - * - * Gregory CLEMENT - * - */ - -#include "armada-37xx.dtsi" - -/ { - model = "Marvell Armada 3710 SoC"; - compatible = "marvell,armada3710", "marvell,armada3700"; -}; diff --git a/sys/gnu/dts/arm64/marvell/armada-3720-db.dts b/sys/gnu/dts/arm64/marvell/armada-3720-db.dts deleted file mode 100644 index f2cc00594d6..00000000000 --- a/sys/gnu/dts/arm64/marvell/armada-3720-db.dts +++ /dev/null @@ -1,217 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for Marvell Armada 3720 development board - * (DB-88F3720-DDR3) - * Copyright (C) 2016 Marvell - * - * Gregory CLEMENT - * - * This file is compatible with the version 1.4 and the version 2.0 of - * the board, however the CON numbers are different between the 2 - * version - */ - -/dts-v1/; - -#include -#include "armada-372x.dtsi" - -/ { - model = "Marvell Armada 3720 Development Board DB-88F3720-DDR3"; - compatible = "marvell,armada-3720-db", "marvell,armada3720", "marvell,armada3710"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x00000000 0x00000000 0x20000000>; - }; - - exp_usb3_vbus: usb3-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb3-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - gpio = <&gpio_exp 1 GPIO_ACTIVE_HIGH>; - }; - - usb3_phy: usb3-phy { - compatible = "usb-nop-xceiv"; - vcc-supply = <&exp_usb3_vbus>; - }; - - vcc_sd_reg1: regulator { - compatible = "regulator-gpio"; - regulator-name = "vcc_sd1"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - - gpios = <&gpiosb 23 GPIO_ACTIVE_HIGH>; - gpios-states = <0>; - states = <1800000 0x1 - 3300000 0x0>; - enable-active-high; - }; - - vcc_sd_reg2: regulator-vmcc { - compatible = "regulator-fixed"; - regulator-name = "vcc_sd2"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - enable-active-high; - gpio = <&gpio_exp 4 GPIO_ACTIVE_HIGH>; - }; -}; - -/* Gigabit module on CON19(V2.0)/CON21(V1.4) */ -ð0 { - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - phy-mode = "rgmii-id"; - phy = <&phy0>; - status = "okay"; -}; - -/* Gigabit module on CON18(V2.0)/CON20(V1.4) */ -ð1 { - phy-mode = "sgmii"; - phy = <&phy1>; - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - status = "okay"; - - gpio_exp: pca9555@22 { - compatible = "nxp,pca9555"; - gpio-controller; - #gpio-cells = <2>; - - reg = <0x22>; - /* - * IO0_0: PWR_EN_USB2 IO1_0: PWR_EN_VTT - * IO0_1: PWR_EN_USB23 IO1_1: MPCIE_WDISABLE - * IO0_2: PWR_EN_SATA IO1_2: RGMII_DEV_RSTN - * IO0_3: PWR_EN_PCIE IO1_3: SGMII_DEV_RSTN - * IO0_4: PWR_EN_SD - * IO0_5: PWR_EN_EMMC - * IO0_6: PWR_EN_RGMII IO1_6: SATA_USB3.0_SEL - * IO0_7: PWR_EN_SGMII IO1_7: PWR_MCI_PS - */ - }; - - rtc@68 { - /* PT7C4337A from pericom fully compatible with the ds1337 */ - compatible = "dallas,ds1337"; - reg = <0x68>; - }; -}; - -&mdio { - status = "okay"; - phy0: ethernet-phy@0 { - reg = <0>; - }; - - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -/* CON15(V2.0)/CON17(V1.4) : PCIe / CON15(V2.0)/CON12(V1.4) :mini-PCIe */ -&pcie0 { - status = "okay"; -}; - -/* CON3 */ -&sata { - status = "okay"; -}; - -&sdhci0 { - non-removable; - bus-width = <8>; - mmc-ddr-1_8v; - mmc-hs400-1_8v; - marvell,pad-type = "fixed-1-8v"; - status = "okay"; -}; - -/* SD slot module on CON14(V2.0)/CON15(V1.4) */ -&sdhci1 { - wp-inverted; - cd-gpios = <&gpiosb 2 GPIO_ACTIVE_LOW>; - bus-width = <4>; - marvell,pad-type = "sd"; - vqmmc-supply = <&vcc_sd_reg1>; - vmmc-supply = <&vcc_sd_reg2>; - status = "okay"; -}; - -&spi0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&spi_quad_pins>; - - m25p80@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <108000000>; - spi-rx-bus-width = <4>; - spi-tx-bus-width = <4>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - partition@0 { - label = "bootloader"; - reg = <0x0 0x200000>; - }; - partition@200000 { - label = "U-boot Env"; - reg = <0x200000 0x10000>; - }; - partition@210000 { - label = "Linux"; - reg = <0x210000 0xDF0000>; - }; - }; - }; -}; - -/* - * Exported on the micro USB connector CON30(V2.0)/CON32(V1.4) through - * an FTDI (also on CON24(V2.0)/CON26(V1.4)). - */ -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; - status = "okay"; -}; - -/* CON26(V2.0)/CON28(V1.4) */ -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; - status = "okay"; -}; - -/* CON27(V2.0)/CON29(V1.4) */ -&usb2 { - status = "okay"; -}; - -/* CON29(V2.0)/CON31(V1.4) */ -&usb3 { - status = "okay"; - usb-phy = <&usb3_phy>; -}; diff --git a/sys/gnu/dts/arm64/marvell/armada-3720-espressobin-emmc.dts b/sys/gnu/dts/arm64/marvell/armada-3720-espressobin-emmc.dts deleted file mode 100644 index bd9ed9dc9c3..00000000000 --- a/sys/gnu/dts/arm64/marvell/armada-3720-espressobin-emmc.dts +++ /dev/null @@ -1,42 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for Globalscale Marvell ESPRESSOBin Board with eMMC - * Copyright (C) 2018 Marvell - * - * Romain Perier - * Konstantin Porotchkin - * - */ -/* - * Schematic available at http://espressobin.net/wp-content/uploads/2017/08/ESPRESSObin_V5_Schematics.pdf - */ - -#include "armada-3720-espressobin.dtsi" - -/ { - model = "Globalscale Marvell ESPRESSOBin Board (eMMC)"; - compatible = "globalscale,espressobin-emmc", "globalscale,espressobin", - "marvell,armada3720", "marvell,armada3710"; -}; - -/* U11 */ -&sdhci0 { - non-removable; - bus-width = <8>; - mmc-ddr-1_8v; - mmc-hs400-1_8v; - marvell,xenon-emmc; - marvell,xenon-tun-count = <9>; - marvell,pad-type = "fixed-1-8v"; - - pinctrl-names = "default"; - pinctrl-0 = <&mmc_pins>; - status = "okay"; - - #address-cells = <1>; - #size-cells = <0>; - mmccard: mmccard@0 { - compatible = "mmc-card"; - reg = <0>; - }; -}; diff --git a/sys/gnu/dts/arm64/marvell/armada-3720-espressobin-v7-emmc.dts b/sys/gnu/dts/arm64/marvell/armada-3720-espressobin-v7-emmc.dts deleted file mode 100644 index 6e876a6d953..00000000000 --- a/sys/gnu/dts/arm64/marvell/armada-3720-espressobin-v7-emmc.dts +++ /dev/null @@ -1,59 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for Globalscale Marvell ESPRESSOBin Board V7 with eMMC - * Copyright (C) 2018 Marvell - * - * Romain Perier - * Konstantin Porotchkin - * - */ -/* - * Schematic available at http://wiki.espressobin.net/tiki-download_file.php?fileId=200 - */ - -#include "armada-3720-espressobin.dtsi" - -/ { - model = "Globalscale Marvell ESPRESSOBin Board V7 (eMMC)"; - compatible = "globalscale,espressobin-v7-emmc", "globalscale,espressobin-v7", - "globalscale,espressobin", "marvell,armada3720", - "marvell,armada3710"; -}; - -&switch0 { - ports { - port@1 { - reg = <1>; - label = "lan1"; - phy-handle = <&switch0phy0>; - }; - - port@3 { - reg = <3>; - label = "wan"; - phy-handle = <&switch0phy2>; - }; - }; -}; - -/* U11 */ -&sdhci0 { - non-removable; - bus-width = <8>; - mmc-ddr-1_8v; - mmc-hs400-1_8v; - marvell,xenon-emmc; - marvell,xenon-tun-count = <9>; - marvell,pad-type = "fixed-1-8v"; - - pinctrl-names = "default"; - pinctrl-0 = <&mmc_pins>; - status = "okay"; - - #address-cells = <1>; - #size-cells = <0>; - mmccard: mmccard@0 { - compatible = "mmc-card"; - reg = <0>; - }; -}; diff --git a/sys/gnu/dts/arm64/marvell/armada-3720-espressobin-v7.dts b/sys/gnu/dts/arm64/marvell/armada-3720-espressobin-v7.dts deleted file mode 100644 index 0f8405d085f..00000000000 --- a/sys/gnu/dts/arm64/marvell/armada-3720-espressobin-v7.dts +++ /dev/null @@ -1,36 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for Globalscale Marvell ESPRESSOBin Board V7 - * Copyright (C) 2018 Marvell - * - * Romain Perier - * Konstantin Porotchkin - * - */ -/* - * Schematic available at http://wiki.espressobin.net/tiki-download_file.php?fileId=200 - */ - -#include "armada-3720-espressobin.dtsi" - -/ { - model = "Globalscale Marvell ESPRESSOBin Board V7"; - compatible = "globalscale,espressobin-v7", "globalscale,espressobin", - "marvell,armada3720", "marvell,armada3710"; -}; - -&switch0 { - ports { - port@1 { - reg = <1>; - label = "lan1"; - phy-handle = <&switch0phy0>; - }; - - port@3 { - reg = <3>; - label = "wan"; - phy-handle = <&switch0phy2>; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/marvell/armada-3720-espressobin.dts b/sys/gnu/dts/arm64/marvell/armada-3720-espressobin.dts deleted file mode 100644 index 1542d836c09..00000000000 --- a/sys/gnu/dts/arm64/marvell/armada-3720-espressobin.dts +++ /dev/null @@ -1,20 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for Globalscale Marvell ESPRESSOBin Board - * Copyright (C) 2016 Marvell - * - * Romain Perier - * - */ -/* - * Schematic available at http://espressobin.net/wp-content/uploads/2017/08/ESPRESSObin_V5_Schematics.pdf - */ - -/dts-v1/; - -#include "armada-3720-espressobin.dtsi" - -/ { - model = "Globalscale Marvell ESPRESSOBin Board"; - compatible = "globalscale,espressobin", "marvell,armada3720", "marvell,armada3710"; -}; diff --git a/sys/gnu/dts/arm64/marvell/armada-3720-espressobin.dtsi b/sys/gnu/dts/arm64/marvell/armada-3720-espressobin.dtsi deleted file mode 100644 index 53b8ac55a7f..00000000000 --- a/sys/gnu/dts/arm64/marvell/armada-3720-espressobin.dtsi +++ /dev/null @@ -1,177 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for Globalscale Marvell ESPRESSOBin Board - * Copyright (C) 2016 Marvell - * - * Romain Perier - * - */ - -/dts-v1/; - -#include -#include "armada-372x.dtsi" - -/ { - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x00000000 0x00000000 0x20000000>; - }; - - vcc_sd_reg1: regulator { - compatible = "regulator-gpio"; - regulator-name = "vcc_sd1"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - - gpios = <&gpionb 4 GPIO_ACTIVE_HIGH>; - gpios-states = <0>; - states = <1800000 0x1 - 3300000 0x0>; - enable-active-high; - }; -}; - -/* J9 */ -&pcie0 { - status = "okay"; - phys = <&comphy1 0>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>; -}; - -/* J6 */ -&sata { - status = "okay"; - phys = <&comphy2 0>; - phy-names = "sata-phy"; -}; - -/* J1 */ -&sdhci1 { - wp-inverted; - bus-width = <4>; - cd-gpios = <&gpionb 3 GPIO_ACTIVE_LOW>; - marvell,pad-type = "sd"; - vqmmc-supply = <&vcc_sd_reg1>; - - pinctrl-names = "default"; - pinctrl-0 = <&sdio_pins>; - status = "okay"; -}; - -&spi0 { - status = "okay"; - - flash@0 { - reg = <0>; - compatible = "jedec,spi-nor"; - spi-max-frequency = <104000000>; - m25p,fast-read; - }; -}; - -/* Exported on the micro USB connector J5 through an FTDI */ -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; - status = "okay"; -}; - -/* - * Connector J17 and J18 expose a number of different features. Some pins are - * multiplexed. This is the case for instance for the following features: - * - UART1 (pin 24 = RX, pin 26 = TX). See armada-3720-db.dts for an example of - * how to enable it. Beware that the signals are 1.8V TTL. - * - I2C - * - SPI - * - MMC - */ - -/* J7 */ -&usb3 { - status = "okay"; -}; - -/* J8 */ -&usb2 { - status = "okay"; -}; - -&mdio { - switch0: switch0@1 { - compatible = "marvell,mv88e6085"; - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - dsa,member = <0 0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "cpu"; - ethernet = <ð0>; - phy-mode = "rgmii-id"; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - - port@1 { - reg = <1>; - label = "wan"; - phy-handle = <&switch0phy0>; - }; - - port@2 { - reg = <2>; - label = "lan0"; - phy-handle = <&switch0phy1>; - }; - - port@3 { - reg = <3>; - label = "lan1"; - phy-handle = <&switch0phy2>; - }; - - }; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - switch0phy0: switch0phy0@11 { - reg = <0x11>; - }; - switch0phy1: switch0phy1@12 { - reg = <0x12>; - }; - switch0phy2: switch0phy2@13 { - reg = <0x13>; - }; - }; - }; -}; - -ð0 { - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>, <&smi_pins>; - phy-mode = "rgmii-id"; - status = "okay"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; diff --git a/sys/gnu/dts/arm64/marvell/armada-3720-turris-mox.dts b/sys/gnu/dts/arm64/marvell/armada-3720-turris-mox.dts deleted file mode 100644 index bb42d1e6a4e..00000000000 --- a/sys/gnu/dts/arm64/marvell/armada-3720-turris-mox.dts +++ /dev/null @@ -1,849 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for CZ.NIC Turris Mox Board - * 2019 by Marek Behun - */ - -/dts-v1/; - -#include -#include -#include -#include "armada-372x.dtsi" - -/ { - model = "CZ.NIC Turris Mox Board"; - compatible = "cznic,turris-mox", "marvell,armada3720", - "marvell,armada3710"; - - aliases { - spi0 = &spi0; - ethernet1 = ð1; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x00000000 0x00000000 0x20000000>; - }; - - leds { - compatible = "gpio-leds"; - red { - label = "mox:red:activity"; - gpios = <&gpiosb 21 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-on"; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - reset { - label = "reset"; - linux,code = ; - gpios = <&gpiosb 20 GPIO_ACTIVE_LOW>; - debounce-interval = <60>; - }; - }; - - exp_usb3_vbus: usb3-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb3-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - gpio = <&gpiosb 0 GPIO_ACTIVE_HIGH>; - }; - - vsdc_reg: vsdc-reg { - compatible = "regulator-gpio"; - regulator-name = "vsdc"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - - gpios = <&gpiosb 23 GPIO_ACTIVE_HIGH>; - gpios-states = <0>; - states = <1800000 0x1 - 3300000 0x0>; - enable-active-high; - }; - - vsdio_reg: vsdio-reg { - compatible = "regulator-gpio"; - regulator-name = "vsdio"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - - gpios = <&gpiosb 22 GPIO_ACTIVE_HIGH>; - gpios-states = <0>; - states = <1800000 0x1 - 3300000 0x0>; - enable-active-high; - }; - - sdhci1_pwrseq: sdhci1-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpionb 19 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - sfp: sfp { - compatible = "sff,sfp+"; - i2c-bus = <&i2c0>; - los-gpio = <&moxtet_sfp 0 GPIO_ACTIVE_HIGH>; - tx-fault-gpio = <&moxtet_sfp 1 GPIO_ACTIVE_HIGH>; - mod-def0-gpio = <&moxtet_sfp 2 GPIO_ACTIVE_LOW>; - tx-disable-gpio = <&moxtet_sfp 4 GPIO_ACTIVE_HIGH>; - rate-select0-gpio = <&moxtet_sfp 5 GPIO_ACTIVE_HIGH>; - - /* enabled by U-Boot if SFP module is present */ - status = "disabled"; - }; - - firmware { - turris-mox-rwtm { - compatible = "cznic,turris-mox-rwtm"; - mboxes = <&rwtm 0>; - status = "okay"; - }; - }; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - clock-frequency = <100000>; - status = "okay"; - - rtc@6f { - compatible = "microchip,mcp7940x"; - reg = <0x6f>; - }; -}; - -&pcie_reset_pins { - function = "gpio"; -}; - -&pcie0 { - pinctrl-names = "default"; - pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>; - status = "okay"; - max-link-speed = <2>; - reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>; - phys = <&comphy1 0>; - - /* enabled by U-Boot if PCIe module is present */ - status = "disabled"; -}; - -&uart0 { - status = "okay"; -}; - -ð0 { - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - phy-mode = "rgmii-id"; - phy = <&phy1>; - status = "okay"; -}; - -ð1 { - phy-mode = "2500base-x"; - managed = "in-band-status"; - phys = <&comphy0 1>; -}; - -&sdhci0 { - wp-inverted; - bus-width = <4>; - cd-gpios = <&gpionb 10 GPIO_ACTIVE_HIGH>; - vqmmc-supply = <&vsdc_reg>; - marvell,pad-type = "sd"; - status = "okay"; -}; - -&sdhci1 { - pinctrl-names = "default"; - pinctrl-0 = <&sdio_pins>; - non-removable; - bus-width = <4>; - marvell,pad-type = "sd"; - vqmmc-supply = <&vsdio_reg>; - mmc-pwrseq = <&sdhci1_pwrseq>; - status = "okay"; -}; - -&spi0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&spi_quad_pins &spi_cs1_pins>; - assigned-clocks = <&nb_periph_clk 7>; - assigned-clock-parents = <&tbg 1>; - assigned-clock-rates = <20000000>; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <20000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "secure-firmware"; - reg = <0x0 0x20000>; - }; - - partition@20000 { - label = "u-boot"; - reg = <0x20000 0x160000>; - }; - - partition@180000 { - label = "u-boot-env"; - reg = <0x180000 0x10000>; - }; - - partition@190000 { - label = "Rescue system"; - reg = <0x190000 0x660000>; - }; - - partition@7f0000 { - label = "dtb"; - reg = <0x7f0000 0x10000>; - }; - }; - }; - - moxtet: moxtet@1 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "cznic,moxtet"; - reg = <1>; - reset-gpios = <&gpiosb 2 GPIO_ACTIVE_LOW>; - spi-max-frequency = <10000000>; - spi-cpol; - spi-cpha; - interrupt-controller; - #interrupt-cells = <1>; - interrupt-parent = <&gpiosb>; - interrupts = <5 IRQ_TYPE_EDGE_FALLING>; - status = "okay"; - - moxtet_sfp: gpio@0 { - compatible = "cznic,moxtet-gpio"; - gpio-controller; - #gpio-cells = <2>; - reg = <0>; - status = "disabled"; - }; - }; -}; - -&usb2 { - status = "okay"; -}; - -&comphy2 { - connector { - compatible = "usb-a-connector"; - phy-supply = <&exp_usb3_vbus>; - }; -}; - -&usb3 { - status = "okay"; - phys = <&comphy2 0>; -}; - -&mdio { - pinctrl-names = "default"; - pinctrl-0 = <&smi_pins>; - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - }; - - /* switch nodes are enabled by U-Boot if modules are present */ - switch0@10 { - compatible = "marvell,mv88e6190"; - reg = <0x10 0>; - dsa,member = <0 0>; - interrupt-parent = <&moxtet>; - interrupts = ; - status = "disabled"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - switch0phy1: switch0phy1@1 { - reg = <0x1>; - }; - - switch0phy2: switch0phy2@2 { - reg = <0x2>; - }; - - switch0phy3: switch0phy3@3 { - reg = <0x3>; - }; - - switch0phy4: switch0phy4@4 { - reg = <0x4>; - }; - - switch0phy5: switch0phy5@5 { - reg = <0x5>; - }; - - switch0phy6: switch0phy6@6 { - reg = <0x6>; - }; - - switch0phy7: switch0phy7@7 { - reg = <0x7>; - }; - - switch0phy8: switch0phy8@8 { - reg = <0x8>; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <0x1>; - label = "lan1"; - phy-handle = <&switch0phy1>; - }; - - port@2 { - reg = <0x2>; - label = "lan2"; - phy-handle = <&switch0phy2>; - }; - - port@3 { - reg = <0x3>; - label = "lan3"; - phy-handle = <&switch0phy3>; - }; - - port@4 { - reg = <0x4>; - label = "lan4"; - phy-handle = <&switch0phy4>; - }; - - port@5 { - reg = <0x5>; - label = "lan5"; - phy-handle = <&switch0phy5>; - }; - - port@6 { - reg = <0x6>; - label = "lan6"; - phy-handle = <&switch0phy6>; - }; - - port@7 { - reg = <0x7>; - label = "lan7"; - phy-handle = <&switch0phy7>; - }; - - port@8 { - reg = <0x8>; - label = "lan8"; - phy-handle = <&switch0phy8>; - }; - - port@9 { - reg = <0x9>; - label = "cpu"; - ethernet = <ð1>; - phy-mode = "2500base-x"; - managed = "in-band-status"; - }; - - switch0port10: port@a { - reg = <0xa>; - label = "dsa"; - phy-mode = "2500base-x"; - managed = "in-band-status"; - link = <&switch1port9 &switch2port9>; - status = "disabled"; - }; - - port-sfp@a { - reg = <0xa>; - label = "sfp"; - sfp = <&sfp>; - phy-mode = "sgmii"; - managed = "in-band-status"; - status = "disabled"; - }; - }; - }; - - switch0@2 { - compatible = "marvell,mv88e6085"; - reg = <0x2 0>; - dsa,member = <0 0>; - interrupt-parent = <&moxtet>; - interrupts = ; - status = "disabled"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - switch0phy1_topaz: switch0phy1@11 { - reg = <0x11>; - }; - - switch0phy2_topaz: switch0phy2@12 { - reg = <0x12>; - }; - - switch0phy3_topaz: switch0phy3@13 { - reg = <0x13>; - }; - - switch0phy4_topaz: switch0phy4@14 { - reg = <0x14>; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <0x1>; - label = "lan1"; - phy-handle = <&switch0phy1_topaz>; - }; - - port@2 { - reg = <0x2>; - label = "lan2"; - phy-handle = <&switch0phy2_topaz>; - }; - - port@3 { - reg = <0x3>; - label = "lan3"; - phy-handle = <&switch0phy3_topaz>; - }; - - port@4 { - reg = <0x4>; - label = "lan4"; - phy-handle = <&switch0phy4_topaz>; - }; - - port@5 { - reg = <0x5>; - label = "cpu"; - phy-mode = "2500base-x"; - managed = "in-band-status"; - ethernet = <ð1>; - }; - }; - }; - - switch1@11 { - compatible = "marvell,mv88e6190"; - reg = <0x11 0>; - dsa,member = <0 1>; - interrupt-parent = <&moxtet>; - interrupts = ; - status = "disabled"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - switch1phy1: switch1phy1@1 { - reg = <0x1>; - }; - - switch1phy2: switch1phy2@2 { - reg = <0x2>; - }; - - switch1phy3: switch1phy3@3 { - reg = <0x3>; - }; - - switch1phy4: switch1phy4@4 { - reg = <0x4>; - }; - - switch1phy5: switch1phy5@5 { - reg = <0x5>; - }; - - switch1phy6: switch1phy6@6 { - reg = <0x6>; - }; - - switch1phy7: switch1phy7@7 { - reg = <0x7>; - }; - - switch1phy8: switch1phy8@8 { - reg = <0x8>; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <0x1>; - label = "lan9"; - phy-handle = <&switch1phy1>; - }; - - port@2 { - reg = <0x2>; - label = "lan10"; - phy-handle = <&switch1phy2>; - }; - - port@3 { - reg = <0x3>; - label = "lan11"; - phy-handle = <&switch1phy3>; - }; - - port@4 { - reg = <0x4>; - label = "lan12"; - phy-handle = <&switch1phy4>; - }; - - port@5 { - reg = <0x5>; - label = "lan13"; - phy-handle = <&switch1phy5>; - }; - - port@6 { - reg = <0x6>; - label = "lan14"; - phy-handle = <&switch1phy6>; - }; - - port@7 { - reg = <0x7>; - label = "lan15"; - phy-handle = <&switch1phy7>; - }; - - port@8 { - reg = <0x8>; - label = "lan16"; - phy-handle = <&switch1phy8>; - }; - - switch1port9: port@9 { - reg = <0x9>; - label = "dsa"; - phy-mode = "2500base-x"; - managed = "in-band-status"; - link = <&switch0port10>; - }; - - switch1port10: port@a { - reg = <0xa>; - label = "dsa"; - phy-mode = "2500base-x"; - managed = "in-band-status"; - link = <&switch2port9>; - status = "disabled"; - }; - - port-sfp@a { - reg = <0xa>; - label = "sfp"; - sfp = <&sfp>; - phy-mode = "sgmii"; - managed = "in-band-status"; - status = "disabled"; - }; - }; - }; - - switch1@2 { - compatible = "marvell,mv88e6085"; - reg = <0x2 0>; - dsa,member = <0 1>; - interrupt-parent = <&moxtet>; - interrupts = ; - status = "disabled"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - switch1phy1_topaz: switch1phy1@11 { - reg = <0x11>; - }; - - switch1phy2_topaz: switch1phy2@12 { - reg = <0x12>; - }; - - switch1phy3_topaz: switch1phy3@13 { - reg = <0x13>; - }; - - switch1phy4_topaz: switch1phy4@14 { - reg = <0x14>; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <0x1>; - label = "lan9"; - phy-handle = <&switch1phy1_topaz>; - }; - - port@2 { - reg = <0x2>; - label = "lan10"; - phy-handle = <&switch1phy2_topaz>; - }; - - port@3 { - reg = <0x3>; - label = "lan11"; - phy-handle = <&switch1phy3_topaz>; - }; - - port@4 { - reg = <0x4>; - label = "lan12"; - phy-handle = <&switch1phy4_topaz>; - }; - - port@5 { - reg = <0x5>; - label = "dsa"; - phy-mode = "2500base-x"; - managed = "in-band-status"; - link = <&switch0port10>; - }; - }; - }; - - switch2@12 { - compatible = "marvell,mv88e6190"; - reg = <0x12 0>; - dsa,member = <0 2>; - interrupt-parent = <&moxtet>; - interrupts = ; - status = "disabled"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - switch2phy1: switch2phy1@1 { - reg = <0x1>; - }; - - switch2phy2: switch2phy2@2 { - reg = <0x2>; - }; - - switch2phy3: switch2phy3@3 { - reg = <0x3>; - }; - - switch2phy4: switch2phy4@4 { - reg = <0x4>; - }; - - switch2phy5: switch2phy5@5 { - reg = <0x5>; - }; - - switch2phy6: switch2phy6@6 { - reg = <0x6>; - }; - - switch2phy7: switch2phy7@7 { - reg = <0x7>; - }; - - switch2phy8: switch2phy8@8 { - reg = <0x8>; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <0x1>; - label = "lan17"; - phy-handle = <&switch2phy1>; - }; - - port@2 { - reg = <0x2>; - label = "lan18"; - phy-handle = <&switch2phy2>; - }; - - port@3 { - reg = <0x3>; - label = "lan19"; - phy-handle = <&switch2phy3>; - }; - - port@4 { - reg = <0x4>; - label = "lan20"; - phy-handle = <&switch2phy4>; - }; - - port@5 { - reg = <0x5>; - label = "lan21"; - phy-handle = <&switch2phy5>; - }; - - port@6 { - reg = <0x6>; - label = "lan22"; - phy-handle = <&switch2phy6>; - }; - - port@7 { - reg = <0x7>; - label = "lan23"; - phy-handle = <&switch2phy7>; - }; - - port@8 { - reg = <0x8>; - label = "lan24"; - phy-handle = <&switch2phy8>; - }; - - switch2port9: port@9 { - reg = <0x9>; - label = "dsa"; - phy-mode = "2500base-x"; - managed = "in-band-status"; - link = <&switch1port10 &switch0port10>; - }; - - port-sfp@a { - reg = <0xa>; - label = "sfp"; - sfp = <&sfp>; - phy-mode = "sgmii"; - managed = "in-band-status"; - status = "disabled"; - }; - }; - }; - - switch2@2 { - compatible = "marvell,mv88e6085"; - reg = <0x2 0>; - dsa,member = <0 2>; - interrupt-parent = <&moxtet>; - interrupts = ; - status = "disabled"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - switch2phy1_topaz: switch2phy1@11 { - reg = <0x11>; - }; - - switch2phy2_topaz: switch2phy2@12 { - reg = <0x12>; - }; - - switch2phy3_topaz: switch2phy3@13 { - reg = <0x13>; - }; - - switch2phy4_topaz: switch2phy4@14 { - reg = <0x14>; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <0x1>; - label = "lan17"; - phy-handle = <&switch2phy1_topaz>; - }; - - port@2 { - reg = <0x2>; - label = "lan18"; - phy-handle = <&switch2phy2_topaz>; - }; - - port@3 { - reg = <0x3>; - label = "lan19"; - phy-handle = <&switch2phy3_topaz>; - }; - - port@4 { - reg = <0x4>; - label = "lan20"; - phy-handle = <&switch2phy4_topaz>; - }; - - port@5 { - reg = <0x5>; - label = "dsa"; - phy-mode = "2500base-x"; - managed = "in-band-status"; - link = <&switch1port10 &switch0port10>; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/marvell/armada-3720-uDPU.dts b/sys/gnu/dts/arm64/marvell/armada-3720-uDPU.dts deleted file mode 100644 index 7eb6c1796ce..00000000000 --- a/sys/gnu/dts/arm64/marvell/armada-3720-uDPU.dts +++ /dev/null @@ -1,170 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device tree for the uDPU board. - * Based on Marvell Armada 3720 development board (DB-88F3720-DDR3) - * Copyright (C) 2016 Marvell - * Copyright (C) 2019 Methode Electronics - * Copyright (C) 2019 Telus - * - * Vladimir Vid - */ - -/dts-v1/; - -#include -#include "armada-372x.dtsi" - -/ { - model = "Methode uDPU Board"; - compatible = "methode,udpu", "marvell,armada3720"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x00000000 0x00000000 0x20000000>; - }; - - leds { - pinctrl-names = "default"; - compatible = "gpio-leds"; - - power1 { - label = "udpu:green:power"; - gpios = <&gpionb 11 GPIO_ACTIVE_LOW>; - }; - - power2 { - label = "udpu:red:power"; - gpios = <&gpionb 12 GPIO_ACTIVE_LOW>; - }; - - network1 { - label = "udpu:green:network"; - gpios = <&gpionb 13 GPIO_ACTIVE_LOW>; - }; - - network2 { - label = "udpu:red:network"; - gpios = <&gpionb 14 GPIO_ACTIVE_LOW>; - }; - - alarm1 { - label = "udpu:green:alarm"; - gpios = <&gpionb 15 GPIO_ACTIVE_LOW>; - }; - - alarm2 { - label = "udpu:red:alarm"; - gpios = <&gpionb 16 GPIO_ACTIVE_LOW>; - }; - }; - - sfp_eth0: sfp-eth0 { - compatible = "sff,sfp"; - i2c-bus = <&i2c0>; - los-gpio = <&gpiosb 2 GPIO_ACTIVE_HIGH>; - mod-def0-gpio = <&gpiosb 3 GPIO_ACTIVE_LOW>; - tx-disable-gpio = <&gpiosb 4 GPIO_ACTIVE_HIGH>; - tx-fault-gpio = <&gpiosb 5 GPIO_ACTIVE_HIGH>; - maximum-power-milliwatt = <3000>; - }; - - sfp_eth1: sfp-eth1 { - compatible = "sff,sfp"; - i2c-bus = <&i2c1>; - los-gpio = <&gpiosb 7 GPIO_ACTIVE_HIGH>; - mod-def0-gpio = <&gpiosb 8 GPIO_ACTIVE_LOW>; - tx-disable-gpio = <&gpiosb 9 GPIO_ACTIVE_HIGH>; - tx-fault-gpio = <&gpiosb 10 GPIO_ACTIVE_HIGH>; - maximum-power-milliwatt = <3000>; - }; -}; - -&sdhci0 { - status = "okay"; - bus-width = <8>; - mmc-ddr-1_8v; - mmc-hs400-1_8v; - marvell,pad-type = "fixed-1-8v"; - non-removable; - no-sd; - no-sdio; -}; - -&spi0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&spi_quad_pins>; - - m25p80@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <54000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - /* only bootloader is located on the SPI */ - partition@0 { - label = "uboot"; - reg = <0 0x400000>; - }; - }; - }; -}; - -&i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - /delete-property/mrvl,i2c-fast-mode; -}; - -&i2c1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - /delete-property/mrvl,i2c-fast-mode; - - lm75@48 { - status = "okay"; - compatible = "lm75"; - reg = <0x48>; - }; - - lm75@49 { - status = "okay"; - compatible = "lm75"; - reg = <0x49>; - }; -}; - -ð0 { - phy-mode = "sgmii"; - status = "okay"; - managed = "in-band-status"; - phys = <&comphy1 0>; - sfp = <&sfp_eth0>; -}; - -ð1 { - phy-mode = "sgmii"; - status = "okay"; - managed = "in-band-status"; - phys = <&comphy0 1>; - sfp = <&sfp_eth1>; -}; - -&usb3 { - status = "okay"; - phys = <&usb2_utmi_otg_phy>; - phy-names = "usb2-utmi-otg-phy"; -}; - -&uart0 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/marvell/armada-372x.dtsi b/sys/gnu/dts/arm64/marvell/armada-372x.dtsi deleted file mode 100644 index 5ce55bdbb99..00000000000 --- a/sys/gnu/dts/arm64/marvell/armada-372x.dtsi +++ /dev/null @@ -1,27 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree Include file for Marvell Armada 372x family of SoCs - * (also named 88F3720) - * - * Copyright (C) 2016 Marvell - * - * Gregory CLEMENT - * - */ - -#include "armada-37xx.dtsi" - -/ { - model = "Marvell Armada 3720 SoC"; - compatible = "marvell,armada3720", "marvell,armada3710"; - - cpus { - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x1>; - clocks = <&nb_periph_clk 16>; - enable-method = "psci"; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/marvell/armada-37xx.dtsi b/sys/gnu/dts/arm64/marvell/armada-37xx.dtsi deleted file mode 100644 index 000c135e39b..00000000000 --- a/sys/gnu/dts/arm64/marvell/armada-37xx.dtsi +++ /dev/null @@ -1,502 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree Include file for Marvell Armada 37xx family of SoCs. - * - * Copyright (C) 2016 Marvell - * - * Gregory CLEMENT - * - */ - -#include - -/ { - model = "Marvell Armada 37xx SoC"; - compatible = "marvell,armada3700"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - /* - * The PSCI firmware region depicted below is the default one - * and should be updated by the bootloader. - */ - psci-area@4000000 { - reg = <0 0x4000000 0 0x200000>; - no-map; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0>; - clocks = <&nb_periph_clk 16>; - enable-method = "psci"; - }; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = ; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - internal-regs@d0000000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - /* 32M internal register @ 0xd000_0000 */ - ranges = <0x0 0x0 0xd0000000 0x2000000>; - - wdt: watchdog@8300 { - compatible = "marvell,armada-3700-wdt"; - reg = <0x8300 0x40>; - marvell,system-controller = <&cpu_misc>; - clocks = <&xtalclk>; - }; - - cpu_misc: system-controller@d000 { - compatible = "marvell,armada-3700-cpu-misc", - "syscon"; - reg = <0xd000 0x1000>; - }; - - spi0: spi@10600 { - compatible = "marvell,armada-3700-spi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x10600 0xA00>; - clocks = <&nb_periph_clk 7>; - interrupts = ; - num-cs = <4>; - status = "disabled"; - }; - - i2c0: i2c@11000 { - compatible = "marvell,armada-3700-i2c"; - reg = <0x11000 0x24>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&nb_periph_clk 10>; - interrupts = ; - mrvl,i2c-fast-mode; - status = "disabled"; - }; - - i2c1: i2c@11080 { - compatible = "marvell,armada-3700-i2c"; - reg = <0x11080 0x24>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&nb_periph_clk 9>; - interrupts = ; - mrvl,i2c-fast-mode; - status = "disabled"; - }; - - avs: avs@11500 { - compatible = "marvell,armada-3700-avs", - "syscon"; - reg = <0x11500 0x40>; - }; - - uart0: serial@12000 { - compatible = "marvell,armada-3700-uart"; - reg = <0x12000 0x200>; - clocks = <&xtalclk>; - interrupts = - , - , - ; - interrupt-names = "uart-sum", "uart-tx", "uart-rx"; - status = "disabled"; - }; - - uart1: serial@12200 { - compatible = "marvell,armada-3700-uart-ext"; - reg = <0x12200 0x30>; - clocks = <&xtalclk>; - interrupts = - , - ; - interrupt-names = "uart-tx", "uart-rx"; - status = "disabled"; - }; - - nb_periph_clk: nb-periph-clk@13000 { - compatible = "marvell,armada-3700-periph-clock-nb"; - reg = <0x13000 0x100>; - clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>, - <&tbg 3>, <&xtalclk>; - #clock-cells = <1>; - }; - - sb_periph_clk: sb-periph-clk@18000 { - compatible = "marvell,armada-3700-periph-clock-sb"; - reg = <0x18000 0x100>; - clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>, - <&tbg 3>, <&xtalclk>; - #clock-cells = <1>; - }; - - tbg: tbg@13200 { - compatible = "marvell,armada-3700-tbg-clock"; - reg = <0x13200 0x100>; - clocks = <&xtalclk>; - #clock-cells = <1>; - }; - - pinctrl_nb: pinctrl@13800 { - compatible = "marvell,armada3710-nb-pinctrl", - "syscon", "simple-mfd"; - reg = <0x13800 0x100>, <0x13C00 0x20>; - /* MPP1[19:0] */ - gpionb: gpio { - #gpio-cells = <2>; - gpio-ranges = <&pinctrl_nb 0 0 36>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = - , - , - , - , - , - , - , - , - , - , - , - ; - }; - - xtalclk: xtal-clk { - compatible = "marvell,armada-3700-xtal-clock"; - clock-output-names = "xtal"; - #clock-cells = <0>; - }; - - spi_quad_pins: spi-quad-pins { - groups = "spi_quad"; - function = "spi"; - }; - - spi_cs1_pins: spi-cs1-pins { - groups = "spi_cs1"; - function = "spi"; - }; - - i2c1_pins: i2c1-pins { - groups = "i2c1"; - function = "i2c"; - }; - - i2c2_pins: i2c2-pins { - groups = "i2c2"; - function = "i2c"; - }; - - uart1_pins: uart1-pins { - groups = "uart1"; - function = "uart"; - }; - - uart2_pins: uart2-pins { - groups = "uart2"; - function = "uart"; - }; - - mmc_pins: mmc-pins { - groups = "emmc_nb"; - function = "emmc"; - }; - }; - - nb_pm: syscon@14000 { - compatible = "marvell,armada-3700-nb-pm", - "syscon"; - reg = <0x14000 0x60>; - }; - - comphy: phy@18300 { - compatible = "marvell,comphy-a3700"; - reg = <0x18300 0x300>, - <0x1F000 0x400>, - <0x5C000 0x400>, - <0xe0178 0x8>; - reg-names = "comphy", - "lane1_pcie_gbe", - "lane0_usb3_gbe", - "lane2_sata_usb3"; - #address-cells = <1>; - #size-cells = <0>; - - comphy0: phy@0 { - reg = <0>; - #phy-cells = <1>; - }; - - comphy1: phy@1 { - reg = <1>; - #phy-cells = <1>; - }; - - comphy2: phy@2 { - reg = <2>; - #phy-cells = <1>; - }; - }; - - pinctrl_sb: pinctrl@18800 { - compatible = "marvell,armada3710-sb-pinctrl", - "syscon", "simple-mfd"; - reg = <0x18800 0x100>, <0x18C00 0x20>; - /* MPP2[23:0] */ - gpiosb: gpio { - #gpio-cells = <2>; - gpio-ranges = <&pinctrl_sb 0 0 30>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = - , - , - , - , - ; - }; - - rgmii_pins: mii-pins { - groups = "rgmii"; - function = "mii"; - }; - - smi_pins: smi-pins { - groups = "smi"; - function = "smi"; - }; - - sdio_pins: sdio-pins { - groups = "sdio_sb"; - function = "sdio"; - }; - - pcie_reset_pins: pcie-reset-pins { - groups = "pcie1"; - function = "pcie"; - }; - - pcie_clkreq_pins: pcie-clkreq-pins { - groups = "pcie1_clkreq"; - function = "pcie"; - }; - }; - - eth0: ethernet@30000 { - compatible = "marvell,armada-3700-neta"; - reg = <0x30000 0x4000>; - interrupts = ; - clocks = <&sb_periph_clk 8>; - status = "disabled"; - }; - - mdio: mdio@32004 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "marvell,orion-mdio"; - reg = <0x32004 0x4>; - }; - - eth1: ethernet@40000 { - compatible = "marvell,armada-3700-neta"; - reg = <0x40000 0x4000>; - interrupts = ; - clocks = <&sb_periph_clk 7>; - status = "disabled"; - }; - - usb3: usb@58000 { - compatible = "marvell,armada3700-xhci", - "generic-xhci"; - reg = <0x58000 0x4000>; - marvell,usb-misc-reg = <&usb32_syscon>; - interrupts = ; - clocks = <&sb_periph_clk 12>; - phys = <&comphy0 0>, <&usb2_utmi_otg_phy>; - phy-names = "usb3-phy", "usb2-utmi-otg-phy"; - status = "disabled"; - }; - - usb2_utmi_otg_phy: phy@5d000 { - compatible = "marvell,a3700-utmi-otg-phy"; - reg = <0x5d000 0x800>; - marvell,usb-misc-reg = <&usb32_syscon>; - #phy-cells = <0>; - }; - - usb32_syscon: system-controller@5d800 { - compatible = "marvell,armada-3700-usb2-host-device-misc", - "syscon"; - reg = <0x5d800 0x800>; - }; - - usb2: usb@5e000 { - compatible = "marvell,armada-3700-ehci"; - reg = <0x5e000 0x1000>; - marvell,usb-misc-reg = <&usb2_syscon>; - interrupts = ; - phys = <&usb2_utmi_host_phy>; - phy-names = "usb2-utmi-host-phy"; - status = "disabled"; - }; - - usb2_utmi_host_phy: phy@5f000 { - compatible = "marvell,a3700-utmi-host-phy"; - reg = <0x5f000 0x800>; - marvell,usb-misc-reg = <&usb2_syscon>; - #phy-cells = <0>; - }; - - usb2_syscon: system-controller@5f800 { - compatible = "marvell,armada-3700-usb2-host-misc", - "syscon"; - reg = <0x5f800 0x800>; - }; - - xor@60900 { - compatible = "marvell,armada-3700-xor"; - reg = <0x60900 0x100>, - <0x60b00 0x100>; - - xor10 { - interrupts = ; - }; - xor11 { - interrupts = ; - }; - }; - - crypto: crypto@90000 { - compatible = "inside-secure,safexcel-eip97ies"; - reg = <0x90000 0x20000>; - interrupts = , - , - , - , - , - ; - interrupt-names = "mem", "ring0", "ring1", - "ring2", "ring3", "eip"; - clocks = <&nb_periph_clk 15>; - }; - - rwtm: mailbox@b0000 { - compatible = "marvell,armada-3700-rwtm-mailbox"; - reg = <0xb0000 0x100>; - interrupts = ; - #mbox-cells = <1>; - }; - - sdhci1: sdhci@d0000 { - compatible = "marvell,armada-3700-sdhci", - "marvell,sdhci-xenon"; - reg = <0xd0000 0x300>, - <0x1e808 0x4>; - interrupts = ; - clocks = <&nb_periph_clk 0>; - clock-names = "core"; - status = "disabled"; - }; - - sdhci0: sdhci@d8000 { - compatible = "marvell,armada-3700-sdhci", - "marvell,sdhci-xenon"; - reg = <0xd8000 0x300>, - <0x17808 0x4>; - interrupts = ; - clocks = <&nb_periph_clk 0>; - clock-names = "core"; - status = "disabled"; - }; - - sata: sata@e0000 { - compatible = "marvell,armada-3700-ahci"; - reg = <0xe0000 0x178>; - interrupts = ; - clocks = <&nb_periph_clk 1>; - status = "disabled"; - }; - - gic: interrupt-controller@1d00000 { - compatible = "arm,gic-v3"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x1d00000 0x10000>, /* GICD */ - <0x1d40000 0x40000>, /* GICR */ - <0x1d80000 0x2000>, /* GICC */ - <0x1d90000 0x2000>, /* GICH */ - <0x1da0000 0x20000>; /* GICV */ - interrupts = ; - }; - }; - - pcie0: pcie@d0070000 { - compatible = "marvell,armada-3700-pcie"; - device_type = "pci"; - status = "disabled"; - reg = <0 0xd0070000 0 0x20000>; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x00 0xff>; - interrupts = ; - #interrupt-cells = <1>; - msi-parent = <&pcie0>; - msi-controller; - ranges = <0x82000000 0 0xe8000000 0 0xe8000000 0 0x1000000 /* Port 0 MEM */ - 0x81000000 0 0xe9000000 0 0xe9000000 0 0x10000>; /* Port 0 IO*/ - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie_intc 0>, - <0 0 0 2 &pcie_intc 1>, - <0 0 0 3 &pcie_intc 2>, - <0 0 0 4 &pcie_intc 3>; - pcie_intc: interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/marvell/armada-7020.dtsi b/sys/gnu/dts/arm64/marvell/armada-7020.dtsi deleted file mode 100644 index 4e46326dd12..00000000000 --- a/sys/gnu/dts/arm64/marvell/armada-7020.dtsi +++ /dev/null @@ -1,16 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2016 Marvell Technology Group Ltd. - * - * Device Tree file for the Armada 7020 SoC, made of an AP806 Dual and - * one CP110. - */ - -#include "armada-ap806-dual.dtsi" -#include "armada-70x0.dtsi" - -/ { - model = "Marvell Armada 7020"; - compatible = "marvell,armada7020", "marvell,armada-ap806-dual", - "marvell,armada-ap806"; -}; diff --git a/sys/gnu/dts/arm64/marvell/armada-7040-db.dts b/sys/gnu/dts/arm64/marvell/armada-7040-db.dts deleted file mode 100644 index a7eb4e7697a..00000000000 --- a/sys/gnu/dts/arm64/marvell/armada-7040-db.dts +++ /dev/null @@ -1,302 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2016 Marvell Technology Group Ltd. - * - * Device Tree file for Marvell Armada 7040 Development board platform - */ - -#include -#include "armada-7040.dtsi" - -/ { - model = "Marvell Armada 7040 DB board"; - compatible = "marvell,armada7040-db", "marvell,armada7040", - "marvell,armada-ap806-quad", "marvell,armada-ap806"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; - - aliases { - ethernet0 = &cp0_eth0; - ethernet1 = &cp0_eth1; - ethernet2 = &cp0_eth2; - }; - - cp0_exp_usb3_0_current_regulator: gpio-regulator { - compatible = "regulator-gpio"; - regulator-name = "cp0-usb3-0-current-regulator"; - regulator-type = "current"; - regulator-min-microamp = <500000>; - regulator-max-microamp = <900000>; - gpios = <&expander0 4 GPIO_ACTIVE_HIGH>; - states = <500000 0x0 - 900000 0x1>; - enable-active-high; - gpios-states = <0>; - }; - - cp0_exp_usb3_1_current_regulator: gpio-regulator { - compatible = "regulator-gpio"; - regulator-name = "cp0-usb3-1-current-regulator"; - regulator-type = "current"; - regulator-min-microamp = <500000>; - regulator-max-microamp = <900000>; - gpios = <&expander0 5 GPIO_ACTIVE_HIGH>; - states = <500000 0x0 - 900000 0x1>; - enable-active-high; - gpios-states = <0>; - }; - - cp0_reg_usb3_0_vbus: cp0-usb3-0-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb3h0-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&expander0 0 GPIO_ACTIVE_HIGH>; - vin-supply = <&cp0_exp_usb3_0_current_regulator>; - }; - - cp0_reg_usb3_1_vbus: cp0-usb3-1-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb3h1-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&expander0 1 GPIO_ACTIVE_HIGH>; - vin-supply = <&cp0_exp_usb3_1_current_regulator>; - }; -}; - -&i2c0 { - status = "okay"; - clock-frequency = <100000>; -}; - -&spi0 { - status = "okay"; - - spi-flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <10000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "U-Boot"; - reg = <0 0x200000>; - }; - partition@400000 { - label = "Filesystem"; - reg = <0x200000 0xce0000>; - }; - }; - }; -}; - -&uart0 { - status = "okay"; - pinctrl-0 = <&uart0_pins>; - pinctrl-names = "default"; -}; - - -&cp0_pcie2 { - status = "okay"; - phys = <&cp0_comphy5 2>; - phy-names = "cp0-pcie2-x1-phy"; -}; - -&cp0_i2c0 { - status = "okay"; - clock-frequency = <100000>; - - expander0: pca9555@21 { - compatible = "nxp,pca9555"; - pinctrl-names = "default"; - gpio-controller; - #gpio-cells = <2>; - reg = <0x21>; - /* - * IO0_0: USB3_PWR_EN0 IO1_0: USB_3_1_Dev_Detect - * IO0_1: USB3_PWR_EN1 IO1_1: USB2_1_current_limit - * IO0_2: DDR3_4_Detect IO1_2: Hcon_IO_RstN - * IO0_3: USB2_DEVICE_DETECT - * IO0_4: GPIO_0 IO1_4: SD_Status - * IO0_5: GPIO_1 IO1_5: LDO_5V_Enable - * IO0_6: IHB_5V_Enable IO1_6: PWR_EN_eMMC - * IO0_7: IO1_7: SDIO_Vcntrl - */ - }; -}; - -&cp0_nand_controller { - /* - * SPI on CPM and NAND have common pins on this board. We can - * use only one at a time. To enable the NAND (which will - * disable the SPI), the "status = "okay";" line have to be - * added here. - */ - pinctrl-0 = <&nand_pins>, <&nand_rb>; - pinctrl-names = "default"; - - nand@0 { - reg = <0>; - label = "pxa3xx_nand-0"; - nand-rb = <0>; - nand-on-flash-bbt; - nand-ecc-strength = <4>; - nand-ecc-step-size = <512>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "U-Boot"; - reg = <0 0x200000>; - }; - - partition@200000 { - label = "Linux"; - reg = <0x200000 0xe00000>; - }; - - partition@1000000 { - label = "Filesystem"; - reg = <0x1000000 0x3f000000>; - }; - - }; - }; -}; - -&cp0_spi1 { - status = "okay"; - - spi-flash@0 { - compatible = "jedec,spi-nor"; - reg = <0x0>; - spi-max-frequency = <20000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "U-Boot"; - reg = <0x0 0x200000>; - }; - - partition@400000 { - label = "Filesystem"; - reg = <0x200000 0xe00000>; - }; - }; - }; -}; - -&cp0_sata0 { - status = "okay"; - - sata-port@1 { - phys = <&cp0_comphy3 1>; - phy-names = "cp0-sata0-1-phy"; - }; -}; - -&cp0_comphy1 { - cp0_usbh0_con: connector { - compatible = "usb-a-connector"; - phy-supply = <&cp0_reg_usb3_0_vbus>; - }; -}; - -&cp0_usb3_0 { - phys = <&cp0_comphy1 0>; - phy-names = "cp0-usb3h0-comphy"; - status = "okay"; -}; - -&cp0_comphy4 { - cp0_usbh1_con: connector { - compatible = "usb-a-connector"; - phy-supply = <&cp0_reg_usb3_1_vbus>; - }; -}; - -&cp0_usb3_1 { - phys = <&cp0_comphy4 1>; - phy-names = "cp0-usb3h1-comphy"; - status = "okay"; -}; - -&ap_sdhci0 { - status = "okay"; - bus-width = <4>; - no-1-8-v; - non-removable; -}; - -&cp0_sdhci0 { - status = "okay"; - bus-width = <4>; - no-1-8-v; - cd-gpios = <&expander0 12 GPIO_ACTIVE_LOW>; -}; - -&cp0_mdio { - status = "okay"; - - phy0: ethernet-phy@0 { - reg = <0>; - }; - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&cp0_ethernet { - status = "okay"; -}; - -&cp0_eth0 { - status = "okay"; - /* Network PHY */ - phy-mode = "10gbase-kr"; - /* Generic PHY, providing serdes lanes */ - phys = <&cp0_comphy2 0>; - - fixed-link { - speed = <10000>; - full-duplex; - }; -}; - -&cp0_eth1 { - status = "okay"; - /* Network PHY */ - phy = <&phy0>; - phy-mode = "sgmii"; - /* Generic PHY, providing serdes lanes */ - phys = <&cp0_comphy0 1>; -}; - -&cp0_eth2 { - status = "okay"; - phy = <&phy1>; - phy-mode = "rgmii-id"; -}; diff --git a/sys/gnu/dts/arm64/marvell/armada-7040.dtsi b/sys/gnu/dts/arm64/marvell/armada-7040.dtsi deleted file mode 100644 index 47247215770..00000000000 --- a/sys/gnu/dts/arm64/marvell/armada-7040.dtsi +++ /dev/null @@ -1,16 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2016 Marvell Technology Group Ltd. - * - * Device Tree file for the Armada 7040 SoC, made of an AP806 Quad and - * one CP110. - */ - -#include "armada-ap806-quad.dtsi" -#include "armada-70x0.dtsi" - -/ { - model = "Marvell Armada 7040"; - compatible = "marvell,armada7040", "marvell,armada-ap806-quad", - "marvell,armada-ap806"; -}; diff --git a/sys/gnu/dts/arm64/marvell/armada-70x0.dtsi b/sys/gnu/dts/arm64/marvell/armada-70x0.dtsi deleted file mode 100644 index 293403a1a33..00000000000 --- a/sys/gnu/dts/arm64/marvell/armada-70x0.dtsi +++ /dev/null @@ -1,64 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2017 Marvell Technology Group Ltd. - * - * Device Tree file for the Armada 70x0 SoC - */ - -/ { - aliases { - gpio1 = &cp0_gpio1; - gpio2 = &cp0_gpio2; - spi1 = &cp0_spi0; - spi2 = &cp0_spi1; - }; -}; - -/* - * Instantiate the CP110 - */ -#define CP11X_NAME cp0 -#define CP11X_BASE f2000000 -#define CP11X_PCIEx_MEM_BASE(iface) (0xf6000000 + (iface * 0x1000000)) -#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000 -#define CP11X_PCIE0_BASE f2600000 -#define CP11X_PCIE1_BASE f2620000 -#define CP11X_PCIE2_BASE f2640000 - -#include "armada-cp110.dtsi" - -#undef CP11X_NAME -#undef CP11X_BASE -#undef CP11X_PCIEx_MEM_BASE -#undef CP11X_PCIEx_MEM_SIZE -#undef CP11X_PCIE0_BASE -#undef CP11X_PCIE1_BASE -#undef CP11X_PCIE2_BASE - -&cp0_gpio1 { - status = "okay"; -}; - -&cp0_gpio2 { - status = "okay"; -}; - -&cp0_syscon0 { - cp0_pinctrl: pinctrl { - compatible = "marvell,armada-7k-pinctrl"; - - nand_pins: nand-pins { - marvell,pins = - "mpp15", "mpp16", "mpp17", "mpp18", - "mpp19", "mpp20", "mpp21", "mpp22", - "mpp23", "mpp24", "mpp25", "mpp26", - "mpp27"; - marvell,function = "dev"; - }; - - nand_rb: nand-rb { - marvell,pins = "mpp13"; - marvell,function = "nf"; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/marvell/armada-8020.dtsi b/sys/gnu/dts/arm64/marvell/armada-8020.dtsi deleted file mode 100644 index ba1307c0fad..00000000000 --- a/sys/gnu/dts/arm64/marvell/armada-8020.dtsi +++ /dev/null @@ -1,26 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2016 Marvell Technology Group Ltd. - * - * Device Tree file for the Armada 8020 SoC, made of an AP806 Dual and - * two CP110. - */ - -#include "armada-ap806-dual.dtsi" -#include "armada-80x0.dtsi" - -/ { - model = "Marvell Armada 8020"; - compatible = "marvell,armada8020", "marvell,armada-ap806-dual", - "marvell,armada-ap806"; -}; - -/* The RTC requires external oscillator. But on Aramda 80x0, the RTC clock - * in CP master is not connected (by package) to the oscillator. So - * disable it. However, the RTC clock in CP slave is connected to the - * oscillator so this one is let enabled. - */ - -&cp0_rtc { - status = "disabled"; -}; diff --git a/sys/gnu/dts/arm64/marvell/armada-8040-clearfog-gt-8k.dts b/sys/gnu/dts/arm64/marvell/armada-8040-clearfog-gt-8k.dts deleted file mode 100644 index a211a046b2f..00000000000 --- a/sys/gnu/dts/arm64/marvell/armada-8040-clearfog-gt-8k.dts +++ /dev/null @@ -1,485 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2018 SolidRun ltd. - * Based on Marvell MACCHIATOBin board - * - * Device Tree file for SolidRun's ClearFog GT 8K - */ - -#include "armada-8040.dtsi" - -#include -#include - -/ { - model = "SolidRun ClearFog GT 8K"; - compatible = "solidrun,clearfog-gt-8k", "marvell,armada8040", - "marvell,armada-ap806-quad", "marvell,armada-ap806"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@00000000 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; - - aliases { - ethernet0 = &cp1_eth1; - ethernet1 = &cp0_eth0; - ethernet2 = &cp1_eth2; - }; - - v_3_3: regulator-3-3v { - compatible = "regulator-fixed"; - regulator-name = "v_3_3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - status = "okay"; - }; - - v_5v0_usb3_hst_vbus: regulator-usb3-vbus0 { - compatible = "regulator-fixed"; - gpio = <&cp0_gpio2 15 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&cp0_xhci_vbus_pins>; - regulator-name = "v_5v0_usb3_hst_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - status = "okay"; - }; - - sfp_cp0_eth0: sfp-cp0-eth0 { - compatible = "sff,sfp"; - i2c-bus = <&cp0_i2c1>; - mod-def0-gpio = <&cp0_gpio2 17 GPIO_ACTIVE_LOW>; - tx-disable-gpio = <&cp1_gpio1 29 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&cp0_sfp_present_pins &cp1_sfp_tx_disable_pins>; - maximum-power-milliwatt = <2000>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-0 = <&cp0_led0_pins - &cp0_led1_pins>; - pinctrl-names = "default"; - /* No designated function for these LEDs at the moment */ - led0 { - label = "clearfog-gt-8k:green:led0"; - gpios = <&cp0_gpio2 8 GPIO_ACTIVE_LOW>; - default-state = "on"; - }; - led1 { - label = "clearfog-gt-8k:green:led1"; - gpios = <&cp0_gpio2 9 GPIO_ACTIVE_LOW>; - default-state = "on"; - }; - }; - - keys { - compatible = "gpio-keys"; - pinctrl-0 = <&cp0_gpio_reset_pins &cp1_wps_button_pins>; - pinctrl-names = "default"; - - button_0 { - /* The rear button */ - label = "Rear Button"; - gpios = <&cp0_gpio2 7 GPIO_ACTIVE_LOW>; - linux,can-disable; - linux,code = ; - }; - - button_1 { - /* The wps button */ - label = "WPS Button"; - gpios = <&cp1_gpio1 30 GPIO_ACTIVE_LOW>; - linux,can-disable; - linux,code = ; - }; - }; -}; - -&uart0 { - status = "okay"; - pinctrl-0 = <&uart0_pins>; - pinctrl-names = "default"; -}; - -&ap_sdhci0 { - bus-width = <8>; - no-1-8-v; - no-sd; - no-sdio; - non-removable; - status = "okay"; - vqmmc-supply = <&v_3_3>; -}; - -&cp0_i2c0 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&cp0_i2c0_pins>; - status = "okay"; -}; - -&cp0_i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&cp0_i2c1_pins>; - status = "okay"; -}; - -&cp0_pinctrl { - /* - * MPP Bus: - * [0-31] = 0xff: Keep default CP0_shared_pins: - * [11] CLKOUT_MPP_11 (out) - * [23] LINK_RD_IN_CP2CP (in) - * [25] CLKOUT_MPP_25 (out) - * [29] AVS_FB_IN_CP2CP (in) - * [32, 33, 34] pci0/1/2 reset - * [35-38] CP0 I2C1 and I2C0 - * [39] GPIO reset button - * [40,41] LED0 and LED1 - * [43] 1512 phy reset - * [47] USB VBUS EN (active low) - * [48] FAN PWM - * [49] SFP+ present signal - * [50] TPM interrupt - * [51] WLAN0 disable - * [52] WLAN1 disable - * [53] LTE disable - * [54] NFC reset - * [55] Micro SD card detect - * [56-61] Micro SD - */ - - cp0_pci0_reset_pins: pci0-reset-pins { - marvell,pins = "mpp32"; - marvell,function = "gpio"; - }; - - cp0_pci1_reset_pins: pci1-reset-pins { - marvell,pins = "mpp33"; - marvell,function = "gpio"; - }; - - cp0_pci2_reset_pins: pci2-reset-pins { - marvell,pins = "mpp34"; - marvell,function = "gpio"; - }; - - cp0_i2c1_pins: i2c1-pins { - marvell,pins = "mpp35", "mpp36"; - marvell,function = "i2c1"; - }; - - cp0_i2c0_pins: i2c0-pins { - marvell,pins = "mpp37", "mpp38"; - marvell,function = "i2c0"; - }; - - cp0_gpio_reset_pins: gpio-reset-pins { - marvell,pins = "mpp39"; - marvell,function = "gpio"; - }; - - cp0_led0_pins: led0-pins { - marvell,pins = "mpp40"; - marvell,function = "gpio"; - }; - - cp0_led1_pins: led1-pins { - marvell,pins = "mpp41"; - marvell,function = "gpio"; - }; - - cp0_copper_eth_phy_reset: copper-eth-phy-reset { - marvell,pins = "mpp43"; - marvell,function = "gpio"; - }; - - cp0_xhci_vbus_pins: xhci0-vbus-pins { - marvell,pins = "mpp47"; - marvell,function = "gpio"; - }; - - cp0_fan_pwm_pins: fan-pwm-pins { - marvell,pins = "mpp48"; - marvell,function = "gpio"; - }; - - cp0_sfp_present_pins: sfp-present-pins { - marvell,pins = "mpp49"; - marvell,function = "gpio"; - }; - - cp0_tpm_irq_pins: tpm-irq-pins { - marvell,pins = "mpp50"; - marvell,function = "gpio"; - }; - - cp0_wlan_disable_pins: wlan-disable-pins { - marvell,pins = "mpp51"; - marvell,function = "gpio"; - }; - - cp0_sdhci_pins: sdhci-pins { - marvell,pins = "mpp55", "mpp56", "mpp57", "mpp58", "mpp59", - "mpp60", "mpp61"; - marvell,function = "sdio"; - }; -}; - -&cp0_pcie0 { - pinctrl-names = "default"; - pinctrl-0 = <&cp0_pci0_reset_pins &cp0_wlan_disable_pins>; - reset-gpios = <&cp0_gpio2 0 GPIO_ACTIVE_LOW>; - phys = <&cp0_comphy0 0>; - phy-names = "cp0-pcie0-x1-phy"; - status = "okay"; -}; - -&cp0_gpio2 { - sata_reset { - gpio-hog; - gpios = <1 GPIO_ACTIVE_HIGH>; - output-high; - }; - - lte_reset { - gpio-hog; - gpios = <2 GPIO_ACTIVE_LOW>; - output-low; - }; - - wlan_disable { - gpio-hog; - gpios = <19 GPIO_ACTIVE_LOW>; - output-low; - }; - - lte_disable { - gpio-hog; - gpios = <21 GPIO_ACTIVE_LOW>; - output-low; - }; -}; - -&cp0_ethernet { - status = "okay"; -}; - -/* SFP */ -&cp0_eth0 { - status = "okay"; - phy-mode = "10gbase-kr"; - managed = "in-band-status"; - phys = <&cp0_comphy2 0>; - sfp = <&sfp_cp0_eth0>; -}; - -&cp0_sdhci0 { - broken-cd; - bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&cp0_sdhci_pins>; - status = "okay"; - vqmmc-supply = <&v_3_3>; -}; - -&cp0_usb3_1 { - status = "okay"; -}; - -&cp1_pinctrl { - /* - * MPP Bus: - * [0-5] TDM - * [6] VHV Enable - * [7] CP1 SPI0 CSn1 (FXS) - * [8] CP1 SPI0 CSn0 (TPM) - * [9.11]CP1 SPI0 MOSI/MISO/CLK - * [13] CP1 SPI1 MISO (TDM and SPI ROM shared) - * [14] CP1 SPI1 CS0n (64Mb SPI ROM) - * [15] CP1 SPI1 MOSI (TDM and SPI ROM shared) - * [16] CP1 SPI1 CLK (TDM and SPI ROM shared) - * [24] Topaz switch reset - * [26] Buzzer - * [27] CP1 SMI MDIO - * [28] CP1 SMI MDC - * [29] CP0 10G SFP TX Disable - * [30] WPS button - * [31] Front panel button - */ - - cp1_spi1_pins: spi1-pins { - marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16"; - marvell,function = "spi1"; - }; - - cp1_switch_reset_pins: switch-reset-pins { - marvell,pins = "mpp24"; - marvell,function = "gpio"; - }; - - cp1_ge_mdio_pins: ge-mdio-pins { - marvell,pins = "mpp27", "mpp28"; - marvell,function = "ge"; - }; - - cp1_sfp_tx_disable_pins: sfp-tx-disable-pins { - marvell,pins = "mpp29"; - marvell,function = "gpio"; - }; - - cp1_wps_button_pins: wps-button-pins { - marvell,pins = "mpp30"; - marvell,function = "gpio"; - }; -}; - -&cp1_sata0 { - pinctrl-0 = <&cp0_pci1_reset_pins>; - status = "okay"; - - sata-port@1 { - phys = <&cp1_comphy0 1>; - phy-names = "cp1-sata0-1-phy"; - }; -}; - -&cp1_mdio { - pinctrl-names = "default"; - pinctrl-0 = <&cp1_ge_mdio_pins>; - status = "okay"; - - ge_phy: ethernet-phy@0 { - /* LED0 - GB link - * LED1 - on: link, blink: activity - */ - marvell,reg-init = <3 16 0 0x1017>; - reg = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&cp0_copper_eth_phy_reset>; - reset-gpios = <&cp0_gpio2 11 GPIO_ACTIVE_LOW>; - reset-assert-us = <10000>; - }; - - switch0: switch0@4 { - compatible = "marvell,mv88e6085"; - reg = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&cp1_switch_reset_pins>; - reset-gpios = <&cp1_gpio1 24 GPIO_ACTIVE_LOW>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - label = "lan2"; - phy-handle = <&switch0phy0>; - }; - - port@2 { - reg = <2>; - label = "lan1"; - phy-handle = <&switch0phy1>; - }; - - port@3 { - reg = <3>; - label = "lan4"; - phy-handle = <&switch0phy2>; - }; - - port@4 { - reg = <4>; - label = "lan3"; - phy-handle = <&switch0phy3>; - }; - - port@5 { - reg = <5>; - label = "cpu"; - ethernet = <&cp1_eth2>; - phy-mode = "2500base-x"; - managed = "in-band-status"; - }; - }; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - switch0phy0: switch0phy0@11 { - reg = <0x11>; - }; - - switch0phy1: switch0phy1@12 { - reg = <0x12>; - }; - - switch0phy2: switch0phy2@13 { - reg = <0x13>; - }; - - switch0phy3: switch0phy3@14 { - reg = <0x14>; - }; - }; - }; -}; - -&cp1_ethernet { - status = "okay"; -}; - -/* 1G copper */ -&cp1_eth1 { - status = "okay"; - phy-mode = "sgmii"; - phy = <&ge_phy>; - phys = <&cp1_comphy3 1>; -}; - -/* Switch uplink */ -&cp1_eth2 { - status = "okay"; - phy-mode = "2500base-x"; - phys = <&cp1_comphy5 2>; - fixed-link { - speed = <2500>; - full-duplex; - }; -}; - -&cp1_spi1 { - pinctrl-names = "default"; - pinctrl-0 = <&cp1_spi1_pins>; - status = "okay"; - - spi-flash@0 { - compatible = "st,w25q32"; - spi-max-frequency = <50000000>; - reg = <0>; - }; -}; - -&cp1_comphy2 { - cp1_usbh0_con: connector { - compatible = "usb-a-connector"; - phy-supply = <&v_5v0_usb3_hst_vbus>; - }; -}; - -&cp1_usb3_0 { - phys = <&cp1_comphy2 0>; - phy-names = "cp1-usb3h0-comphy"; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/marvell/armada-8040-db.dts b/sys/gnu/dts/arm64/marvell/armada-8040-db.dts deleted file mode 100644 index 09fb5256f1d..00000000000 --- a/sys/gnu/dts/arm64/marvell/armada-8040-db.dts +++ /dev/null @@ -1,358 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2016 Marvell Technology Group Ltd. - * - * Device Tree file for Marvell Armada 8040 Development board platform - */ - -#include -#include "armada-8040.dtsi" - -/ { - model = "Marvell Armada 8040 DB board"; - compatible = "marvell,armada8040-db", "marvell,armada8040", - "marvell,armada-ap806-quad", "marvell,armada-ap806"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; - - aliases { - ethernet0 = &cp0_eth0; - ethernet1 = &cp0_eth2; - ethernet2 = &cp1_eth0; - ethernet3 = &cp1_eth1; - i2c1 = &cp0_i2c0; - i2c2 = &cp1_i2c0; - }; - - cp0_reg_usb3_0_vbus: cp0-usb3-0-vbus { - compatible = "regulator-fixed"; - regulator-name = "cp0-usb3h0-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&expander0 0 GPIO_ACTIVE_HIGH>; - }; - - cp0_reg_usb3_1_vbus: cp0-usb3-1-vbus { - compatible = "regulator-fixed"; - regulator-name = "cp0-usb3h1-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&expander0 1 GPIO_ACTIVE_HIGH>; - }; - - cp0_usb3_0_phy: cp0-usb3-0-phy { - compatible = "usb-nop-xceiv"; - vcc-supply = <&cp0_reg_usb3_0_vbus>; - }; - - cp1_reg_usb3_0_vbus: cp1-usb3-0-vbus { - compatible = "regulator-fixed"; - regulator-name = "cp1-usb3h0-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&expander1 0 GPIO_ACTIVE_HIGH>; - }; - - cp1_usb3_0_phy: cp1-usb3-0-phy { - compatible = "usb-nop-xceiv"; - vcc-supply = <&cp1_reg_usb3_0_vbus>; - }; -}; - -&spi0 { - status = "okay"; - - spi-flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <10000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "U-Boot"; - reg = <0 0x200000>; - }; - partition@400000 { - label = "Filesystem"; - reg = <0x200000 0xce0000>; - }; - }; - }; -}; - -/* Accessible over the mini-USB CON9 connector on the main board */ -&uart0 { - status = "okay"; - pinctrl-0 = <&uart0_pins>; - pinctrl-names = "default"; -}; - -/* CON6 on CP0 expansion */ -&cp0_pcie0 { - phys = <&cp0_comphy0 0>; - phy-names = "cp0-pcie0-x1-phy"; - status = "okay"; -}; - -/* CON5 on CP0 expansion */ -&cp0_pcie2 { - phys = <&cp0_comphy5 2>; - phy-names = "cp0-pcie2-x1-phy"; - status = "okay"; -}; - -&cp0_i2c0 { - status = "okay"; - clock-frequency = <100000>; - - /* U31 */ - expander0: pca9555@21 { - compatible = "nxp,pca9555"; - pinctrl-names = "default"; - gpio-controller; - #gpio-cells = <2>; - reg = <0x21>; - }; - - /* U25 */ - expander1: pca9555@25 { - compatible = "nxp,pca9555"; - pinctrl-names = "default"; - gpio-controller; - #gpio-cells = <2>; - reg = <0x25>; - }; - -}; - -/* CON4 on CP0 expansion */ -&cp0_sata0 { - status = "okay"; - - sata-port@0 { - phys = <&cp0_comphy1 0>; - phy-names = "cp0-sata0-0-phy"; - }; - sata-port@1 { - phys = <&cp0_comphy3 1>; - phy-names = "cp0-sata0-1-phy"; - }; -}; - -/* CON9 on CP0 expansion */ -&cp0_usb3_0 { - usb-phy = <&cp0_usb3_0_phy>; - status = "okay"; -}; - -&cp0_comphy4 { - cp0_usbh1_con: connector { - compatible = "usb-a-connector"; - phy-supply = <&cp0_reg_usb3_1_vbus>; - }; -}; - -/* CON10 on CP0 expansion */ -&cp0_usb3_1 { - phys = <&cp0_comphy4 1>; - phy-names = "cp0-usb3h1-comphy"; - status = "okay"; -}; - -&cp0_mdio { - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&cp0_ethernet { - status = "okay"; -}; - -&cp0_eth0 { - status = "okay"; - phy-mode = "10gbase-kr"; - - fixed-link { - speed = <10000>; - full-duplex; - }; -}; - -&cp0_eth2 { - status = "okay"; - phy = <&phy1>; - phy-mode = "rgmii-id"; -}; - -/* CON6 on CP1 expansion */ -&cp1_pcie0 { - phys = <&cp1_comphy0 0>; - phy-names = "cp1-pcie0-x1-phy"; - status = "okay"; -}; - -/* CON7 on CP1 expansion */ -&cp1_pcie1 { - phys = <&cp1_comphy4 1>; - phy-names = "cp1-pcie1-x1-phy"; - status = "okay"; -}; - -/* CON5 on CP1 expansion */ -&cp1_pcie2 { - phys = <&cp1_comphy5 2>; - phy-names = "cp1-pcie2-x1-phy"; - status = "okay"; -}; - -&cp1_i2c0 { - status = "okay"; - clock-frequency = <100000>; -}; - -&cp1_spi1 { - status = "okay"; - - spi-flash@0 { - compatible = "jedec,spi-nor"; - reg = <0x0>; - spi-max-frequency = <20000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "Boot"; - reg = <0x0 0x200000>; - }; - partition@200000 { - label = "Filesystem"; - reg = <0x200000 0xd00000>; - }; - partition@f00000 { - label = "Boot_2nd"; - reg = <0xf00000 0x100000>; - }; - }; - }; -}; - -/* - * Proper NAND usage will require DPR-76 to be in position 1-2, which disables - * MDIO signal of CP1. - */ -&cp1_nand_controller { - pinctrl-0 = <&nand_pins>, <&nand_rb>; - pinctrl-names = "default"; - - nand@0 { - reg = <0>; - nand-rb = <0>; - nand-on-flash-bbt; - nand-ecc-strength = <4>; - nand-ecc-step-size = <512>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "U-Boot"; - reg = <0 0x200000>; - }; - partition@200000 { - label = "Linux"; - reg = <0x200000 0xe00000>; - }; - partition@1000000 { - label = "Filesystem"; - reg = <0x1000000 0x3f000000>; - }; - }; - }; -}; - -/* CON4 on CP1 expansion */ -&cp1_sata0 { - status = "okay"; - - sata-port@0 { - phys = <&cp1_comphy1 0>; - phy-names = "cp1-sata0-0-phy"; - }; - sata-port@1 { - phys = <&cp1_comphy3 1>; - phy-names = "cp1-sata0-1-phy"; - }; -}; - -/* CON9 on CP1 expansion */ -&cp1_usb3_0 { - usb-phy = <&cp1_usb3_0_phy>; - status = "okay"; -}; - -/* CON10 on CP1 expansion */ -&cp1_usb3_1 { - status = "okay"; -}; - -&cp1_mdio { - status = "okay"; - - phy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -&cp1_ethernet { - status = "okay"; -}; - -&cp1_eth0 { - status = "okay"; - phy-mode = "10gbase-kr"; - - fixed-link { - speed = <10000>; - full-duplex; - }; -}; - -&cp1_eth1 { - status = "okay"; - phy = <&phy0>; - phy-mode = "rgmii-id"; -}; - -&ap_sdhci0 { - status = "okay"; - bus-width = <4>; - non-removable; -}; - -&cp0_sdhci0 { - status = "okay"; - bus-width = <8>; - non-removable; -}; diff --git a/sys/gnu/dts/arm64/marvell/armada-8040-mcbin-singleshot.dts b/sys/gnu/dts/arm64/marvell/armada-8040-mcbin-singleshot.dts deleted file mode 100644 index c3e18fd5bc2..00000000000 --- a/sys/gnu/dts/arm64/marvell/armada-8040-mcbin-singleshot.dts +++ /dev/null @@ -1,29 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2016 Marvell Technology Group Ltd. - * - * Device Tree file for MACCHIATOBin Armada 8040 community board platform - */ - -#include "armada-8040-mcbin.dtsi" - -/ { - model = "Marvell 8040 MACCHIATOBin Single-shot"; - compatible = "marvell,armada8040-mcbin-singleshot", - "marvell,armada8040-mcbin", "marvell,armada8040", - "marvell,armada-ap806-quad", "marvell,armada-ap806"; -}; - -&cp0_eth0 { - status = "okay"; - phy-mode = "10gbase-kr"; - managed = "in-band-status"; - sfp = <&sfp_eth0>; -}; - -&cp1_eth0 { - status = "okay"; - phy-mode = "10gbase-kr"; - managed = "in-band-status"; - sfp = <&sfp_eth1>; -}; diff --git a/sys/gnu/dts/arm64/marvell/armada-8040-mcbin.dts b/sys/gnu/dts/arm64/marvell/armada-8040-mcbin.dts deleted file mode 100644 index d06f5ab7dda..00000000000 --- a/sys/gnu/dts/arm64/marvell/armada-8040-mcbin.dts +++ /dev/null @@ -1,45 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2016 Marvell Technology Group Ltd. - * - * Device Tree file for MACCHIATOBin Armada 8040 community board platform - */ - -#include "armada-8040-mcbin.dtsi" - -/ { - model = "Marvell 8040 MACCHIATOBin Double-shot"; - compatible = "marvell,armada8040-mcbin-doubleshot", - "marvell,armada8040-mcbin", "marvell,armada8040", - "marvell,armada-ap806-quad", "marvell,armada-ap806"; -}; - -&cp0_xmdio { - status = "okay"; - - phy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c45"; - reg = <0>; - sfp = <&sfp_eth0>; - }; - - phy8: ethernet-phy@8 { - compatible = "ethernet-phy-ieee802.3-c45"; - reg = <8>; - sfp = <&sfp_eth1>; - }; -}; - -&cp0_eth0 { - status = "okay"; - /* Network PHY */ - phy = <&phy0>; - phy-mode = "10gbase-kr"; -}; - -&cp1_eth0 { - status = "okay"; - /* Network PHY */ - phy = <&phy8>; - phy-mode = "10gbase-kr"; -}; diff --git a/sys/gnu/dts/arm64/marvell/armada-8040-mcbin.dtsi b/sys/gnu/dts/arm64/marvell/armada-8040-mcbin.dtsi deleted file mode 100644 index 572e2610e0a..00000000000 --- a/sys/gnu/dts/arm64/marvell/armada-8040-mcbin.dtsi +++ /dev/null @@ -1,369 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2016 Marvell Technology Group Ltd. - * - * Device Tree file for MACCHIATOBin Armada 8040 community board platform - */ - -#include "armada-8040.dtsi" - -#include - -/ { - model = "Marvell 8040 MACCHIATOBin"; - compatible = "marvell,armada8040-mcbin", "marvell,armada8040", - "marvell,armada-ap806-quad", "marvell,armada-ap806"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; - - aliases { - ethernet0 = &cp0_eth0; - ethernet1 = &cp1_eth0; - ethernet2 = &cp1_eth1; - ethernet3 = &cp1_eth2; - }; - - /* Regulator labels correspond with schematics */ - v_3_3: regulator-3-3v { - compatible = "regulator-fixed"; - regulator-name = "v_3_3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - status = "okay"; - }; - - v_vddo_h: regulator-1-8v { - compatible = "regulator-fixed"; - regulator-name = "v_vddo_h"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - status = "okay"; - }; - - v_5v0_usb3_hst_vbus: regulator-usb3-vbus0 { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&cp0_gpio2 15 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&cp0_xhci_vbus_pins>; - regulator-name = "v_5v0_usb3_hst_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - status = "okay"; - }; - - sfp_eth0: sfp-eth0 { - /* CON15,16 - CPM lane 4 */ - compatible = "sff,sfp"; - i2c-bus = <&sfpp0_i2c>; - los-gpio = <&cp1_gpio1 28 GPIO_ACTIVE_HIGH>; - mod-def0-gpio = <&cp1_gpio1 27 GPIO_ACTIVE_LOW>; - tx-disable-gpio = <&cp1_gpio1 29 GPIO_ACTIVE_HIGH>; - tx-fault-gpio = <&cp1_gpio1 26 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&cp1_sfpp0_pins>; - }; - - sfp_eth1: sfp-eth1 { - /* CON17,18 - CPS lane 4 */ - compatible = "sff,sfp"; - i2c-bus = <&sfpp1_i2c>; - los-gpio = <&cp1_gpio1 8 GPIO_ACTIVE_HIGH>; - mod-def0-gpio = <&cp1_gpio1 11 GPIO_ACTIVE_LOW>; - tx-disable-gpio = <&cp1_gpio1 10 GPIO_ACTIVE_HIGH>; - tx-fault-gpio = <&cp0_gpio2 30 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&cp1_sfpp1_pins &cp0_sfpp1_pins>; - }; - - sfp_eth3: sfp-eth3 { - /* CON13,14 - CPS lane 5 */ - compatible = "sff,sfp"; - i2c-bus = <&sfp_1g_i2c>; - los-gpio = <&cp0_gpio2 22 GPIO_ACTIVE_HIGH>; - mod-def0-gpio = <&cp0_gpio2 21 GPIO_ACTIVE_LOW>; - tx-disable-gpio = <&cp1_gpio1 24 GPIO_ACTIVE_HIGH>; - tx-fault-gpio = <&cp0_gpio2 19 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&cp0_sfp_1g_pins &cp1_sfp_1g_pins>; - }; -}; - -&uart0 { - status = "okay"; - pinctrl-0 = <&uart0_pins>; - pinctrl-names = "default"; -}; - -&ap_sdhci0 { - bus-width = <8>; - /* - * Not stable in HS modes - phy needs "more calibration", so add - * the "slow-mode" and disable SDR104, SDR50 and DDR50 modes. - */ - marvell,xenon-phy-slow-mode; - no-1-8-v; - no-sd; - no-sdio; - non-removable; - status = "okay"; - vqmmc-supply = <&v_vddo_h>; -}; - -&cp0_i2c0 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&cp0_i2c0_pins>; - status = "okay"; -}; - -&cp0_i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&cp0_i2c1_pins>; - status = "okay"; - - i2c-switch@70 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x70>; - - sfpp0_i2c: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - sfpp1_i2c: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - sfp_1g_i2c: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - }; -}; - -/* J25 UART header */ -&cp0_uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&cp0_uart1_pins>; - status = "okay"; -}; - -&cp0_mdio { - pinctrl-names = "default"; - pinctrl-0 = <&cp0_ge_mdio_pins>; - status = "okay"; - - ge_phy: ethernet-phy@0 { - reg = <0>; - }; -}; - -&cp0_pcie0 { - pinctrl-names = "default"; - pinctrl-0 = <&cp0_pcie_pins>; - num-lanes = <4>; - num-viewport = <8>; - reset-gpios = <&cp0_gpio2 20 GPIO_ACTIVE_LOW>; - ranges = <0x82000000 0x0 0xc0000000 0x0 0xc0000000 0x0 0x20000000>; - phys = <&cp0_comphy0 0>, <&cp0_comphy1 0>, - <&cp0_comphy2 0>, <&cp0_comphy3 0>; - phy-names = "cp0-pcie0-x4-lane0-phy", "cp0-pcie0-x4-lane1-phy", - "cp0-pcie0-x4-lane2-phy", "cp0-pcie0-x4-lane3-phy"; - status = "okay"; -}; - -&cp0_pinctrl { - cp0_ge_mdio_pins: ge-mdio-pins { - marvell,pins = "mpp32", "mpp34"; - marvell,function = "ge"; - }; - cp0_i2c1_pins: i2c1-pins { - marvell,pins = "mpp35", "mpp36"; - marvell,function = "i2c1"; - }; - cp0_i2c0_pins: i2c0-pins { - marvell,pins = "mpp37", "mpp38"; - marvell,function = "i2c0"; - }; - cp0_uart1_pins: uart1-pins { - marvell,pins = "mpp40", "mpp41"; - marvell,function = "uart1"; - }; - cp0_xhci_vbus_pins: xhci0-vbus-pins { - marvell,pins = "mpp47"; - marvell,function = "gpio"; - }; - cp0_sfp_1g_pins: sfp-1g-pins { - marvell,pins = "mpp51", "mpp53", "mpp54"; - marvell,function = "gpio"; - }; - cp0_pcie_pins: pcie-pins { - marvell,pins = "mpp52"; - marvell,function = "gpio"; - }; - cp0_sdhci_pins: sdhci-pins { - marvell,pins = "mpp55", "mpp56", "mpp57", "mpp58", "mpp59", - "mpp60", "mpp61"; - marvell,function = "sdio"; - }; - cp0_sfpp1_pins: sfpp1-pins { - marvell,pins = "mpp62"; - marvell,function = "gpio"; - }; -}; - -&cp0_ethernet { - status = "okay"; -}; - -&cp0_eth0 { - /* Generic PHY, providing serdes lanes */ - phys = <&cp0_comphy4 0>; -}; - -&cp0_sata0 { - status = "okay"; - - /* CPM Lane 5 - U29 */ - sata-port@1 { - phys = <&cp0_comphy5 1>; - phy-names = "cp0-sata0-1-phy"; - }; -}; - -&cp0_sdhci0 { - /* U6 */ - broken-cd; - bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&cp0_sdhci_pins>; - status = "okay"; - vqmmc-supply = <&v_3_3>; -}; - -&cp0_usb3_0 { - /* J38? - USB2.0 only */ - status = "okay"; -}; - -&cp0_usb3_1 { - /* J38? - USB2.0 only */ - status = "okay"; -}; - -&cp1_ethernet { - status = "okay"; -}; - -&cp1_eth0 { - /* Generic PHY, providing serdes lanes */ - phys = <&cp1_comphy4 0>; -}; - -&cp1_eth1 { - /* CPS Lane 0 - J5 (Gigabit RJ45) */ - status = "okay"; - /* Network PHY */ - phy = <&ge_phy>; - phy-mode = "sgmii"; - /* Generic PHY, providing serdes lanes */ - phys = <&cp1_comphy0 1>; -}; - -&cp1_eth2 { - /* CPS Lane 5 */ - status = "okay"; - /* Network PHY */ - phy-mode = "2500base-x"; - managed = "in-band-status"; - /* Generic PHY, providing serdes lanes */ - phys = <&cp1_comphy5 2>; - sfp = <&sfp_eth3>; -}; - -&cp1_pinctrl { - cp1_sfpp1_pins: sfpp1-pins { - marvell,pins = "mpp8", "mpp10", "mpp11"; - marvell,function = "gpio"; - }; - cp1_spi1_pins: spi1-pins { - marvell,pins = "mpp12", "mpp13", "mpp14", "mpp15", "mpp16"; - marvell,function = "spi1"; - }; - cp1_uart0_pins: uart0-pins { - marvell,pins = "mpp6", "mpp7"; - marvell,function = "uart0"; - }; - cp1_sfp_1g_pins: sfp-1g-pins { - marvell,pins = "mpp24"; - marvell,function = "gpio"; - }; - cp1_sfpp0_pins: sfpp0-pins { - marvell,pins = "mpp26", "mpp27", "mpp28", "mpp29"; - marvell,function = "gpio"; - }; -}; - -/* J27 UART header */ -&cp1_uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&cp1_uart0_pins>; - status = "okay"; -}; - -&cp1_sata0 { - status = "okay"; - - /* CPS Lane 1 - U32 */ - sata-port@0 { - phys = <&cp1_comphy1 0>; - phy-names = "cp1-sata0-0-phy"; - }; - - /* CPS Lane 3 - U31 */ - sata-port@1 { - phys = <&cp1_comphy3 1>; - phy-names = "cp1-sata0-1-phy"; - }; -}; - -&cp1_spi1 { - pinctrl-names = "default"; - pinctrl-0 = <&cp1_spi1_pins>; - status = "okay"; - - spi-flash@0 { - compatible = "st,w25q32"; - spi-max-frequency = <50000000>; - reg = <0>; - }; -}; - -&cp1_comphy2 { - cp1_usbh0_con: connector { - compatible = "usb-a-connector"; - phy-supply = <&v_5v0_usb3_hst_vbus>; - }; -}; - -&cp1_usb3_0 { - /* CPS Lane 2 - CON7 */ - phys = <&cp1_comphy2 0>; - phy-names = "cp1-usb3h0-comphy"; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/marvell/armada-8040.dtsi b/sys/gnu/dts/arm64/marvell/armada-8040.dtsi deleted file mode 100644 index 7699b19224c..00000000000 --- a/sys/gnu/dts/arm64/marvell/armada-8040.dtsi +++ /dev/null @@ -1,25 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2016 Marvell Technology Group Ltd. - * - * Device Tree file for the Armada 8040 SoC, made of an AP806 Quad and - * two CP110. - */ - -#include "armada-ap806-quad.dtsi" -#include "armada-80x0.dtsi" - -/ { - model = "Marvell Armada 8040"; - compatible = "marvell,armada8040", "marvell,armada-ap806-quad", - "marvell,armada-ap806"; -}; - -/* The RTC requires external oscillator. But on Aramda 80x0, the RTC clock - * in CP master is not connected (by package) to the oscillator. So - * disable it. However, the RTC clock in CP slave is connected to the - * oscillator so this one is let enabled. - */ -&cp0_rtc { - status = "disabled"; -}; diff --git a/sys/gnu/dts/arm64/marvell/armada-8080-db.dts b/sys/gnu/dts/arm64/marvell/armada-8080-db.dts deleted file mode 100644 index 4ba158f415c..00000000000 --- a/sys/gnu/dts/arm64/marvell/armada-8080-db.dts +++ /dev/null @@ -1,28 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2017 Marvell Technology Group Ltd. - * - * Device Tree file for Marvell Armada-8080 Development board platform - */ - -#include "armada-8080.dtsi" - -/ { - model = "Marvell 8080 board"; - compatible = "marvell,armada-8080-db", "marvell,armada-8080", - "marvell,armada-ap810-octa", "marvell,armada-ap810"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; -}; - -&uart0_ap0 { - clock-frequency = <384000>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/marvell/armada-8080.dtsi b/sys/gnu/dts/arm64/marvell/armada-8080.dtsi deleted file mode 100644 index 299e814d1de..00000000000 --- a/sys/gnu/dts/arm64/marvell/armada-8080.dtsi +++ /dev/null @@ -1,14 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2017 Marvell Technology Group Ltd. - * - * Device Tree file for Marvell Armada-8080 SoC, made of an AP810 OCTA. - */ - -#include "armada-ap810-ap0-octa-core.dtsi" - -/ { - model = "Marvell 8080 board"; - compatible = "marvell,armada-8080", "marvell,armada-ap810-octa", - "marvell,armada-ap810"; -}; diff --git a/sys/gnu/dts/arm64/marvell/armada-80x0.dtsi b/sys/gnu/dts/arm64/marvell/armada-80x0.dtsi deleted file mode 100644 index ee67c70bf02..00000000000 --- a/sys/gnu/dts/arm64/marvell/armada-80x0.dtsi +++ /dev/null @@ -1,108 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2017 Marvell Technology Group Ltd. - * - * Device Tree file for the Armada 80x0 SoC family - */ - -/ { - aliases { - gpio1 = &cp1_gpio1; - gpio2 = &cp0_gpio2; - spi1 = &cp0_spi0; - spi2 = &cp0_spi1; - spi3 = &cp1_spi0; - spi4 = &cp1_spi1; - }; -}; - -/* - * Instantiate the master CP110 - */ -#define CP11X_NAME cp0 -#define CP11X_BASE f2000000 -#define CP11X_PCIEx_MEM_BASE(iface) (0xf6000000 + (iface * 0x1000000)) -#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000 -#define CP11X_PCIE0_BASE f2600000 -#define CP11X_PCIE1_BASE f2620000 -#define CP11X_PCIE2_BASE f2640000 - -#include "armada-cp110.dtsi" - -#undef CP11X_NAME -#undef CP11X_BASE -#undef CP11X_PCIEx_MEM_BASE -#undef CP11X_PCIEx_MEM_SIZE -#undef CP11X_PCIE0_BASE -#undef CP11X_PCIE1_BASE -#undef CP11X_PCIE2_BASE - -/* - * Instantiate the slave CP110 - */ -#define CP11X_NAME cp1 -#define CP11X_BASE f4000000 -#define CP11X_PCIEx_MEM_BASE(iface) (0xfa000000 + (iface * 0x1000000)) -#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000 -#define CP11X_PCIE0_BASE f4600000 -#define CP11X_PCIE1_BASE f4620000 -#define CP11X_PCIE2_BASE f4640000 - -#include "armada-cp110.dtsi" - -#undef CP11X_NAME -#undef CP11X_BASE -#undef CP11X_PCIEx_MEM_BASE -#undef CP11X_PCIEx_MEM_SIZE -#undef CP11X_PCIE0_BASE -#undef CP11X_PCIE1_BASE -#undef CP11X_PCIE2_BASE - -/* The 80x0 has two CP blocks, but uses only one block from each. */ -&cp1_gpio1 { - status = "okay"; -}; - -&cp0_gpio2 { - status = "okay"; -}; - -&cp0_syscon0 { - cp0_pinctrl: pinctrl { - compatible = "marvell,armada-8k-cpm-pinctrl"; - }; -}; - -&cp1_syscon0 { - cp1_pinctrl: pinctrl { - compatible = "marvell,armada-8k-cps-pinctrl"; - - nand_pins: nand-pins { - marvell,pins = - "mpp0", "mpp1", "mpp2", "mpp3", - "mpp4", "mpp5", "mpp6", "mpp7", - "mpp8", "mpp9", "mpp10", "mpp11", - "mpp15", "mpp16", "mpp17", "mpp18", - "mpp19", "mpp20", "mpp21", "mpp22", - "mpp23", "mpp24", "mpp25", "mpp26", - "mpp27"; - marvell,function = "dev"; - }; - - nand_rb: nand-rb { - marvell,pins = "mpp13", "mpp12"; - marvell,function = "nf"; - }; - }; -}; - -&cp1_crypto { - /* - * The cryptographic engine found on the cp110 - * master is enabled by default at the SoC - * level. Because it is not possible as of now - * to enable two cryptographic engines in - * parallel, disable this one by default. - */ - status = "disabled"; -}; diff --git a/sys/gnu/dts/arm64/marvell/armada-ap806-dual.dtsi b/sys/gnu/dts/arm64/marvell/armada-ap806-dual.dtsi deleted file mode 100644 index 09849558a77..00000000000 --- a/sys/gnu/dts/arm64/marvell/armada-ap806-dual.dtsi +++ /dev/null @@ -1,56 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2016 Marvell Technology Group Ltd. - * - * Device Tree file for Marvell Armada AP806. - */ - -#include "armada-ap806.dtsi" - -/ { - model = "Marvell Armada AP806 Dual"; - compatible = "marvell,armada-ap806-dual", "marvell,armada-ap806"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x000>; - enable-method = "psci"; - #cooling-cells = <2>; - clocks = <&cpu_clk 0>; - i-cache-size = <0xc000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&l2>; - }; - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x001>; - enable-method = "psci"; - #cooling-cells = <2>; - clocks = <&cpu_clk 0>; - i-cache-size = <0xc000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&l2>; - }; - - l2: l2-cache { - compatible = "cache"; - cache-size = <0x80000>; - cache-line-size = <64>; - cache-sets = <512>; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/marvell/armada-ap806-quad.dtsi b/sys/gnu/dts/arm64/marvell/armada-ap806-quad.dtsi deleted file mode 100644 index 3db427122f9..00000000000 --- a/sys/gnu/dts/arm64/marvell/armada-ap806-quad.dtsi +++ /dev/null @@ -1,93 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2016 Marvell Technology Group Ltd. - * - * Device Tree file for Marvell Armada AP806. - */ - -#include "armada-ap806.dtsi" - -/ { - model = "Marvell Armada AP806 Quad"; - compatible = "marvell,armada-ap806-quad", "marvell,armada-ap806"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x000>; - enable-method = "psci"; - #cooling-cells = <2>; - clocks = <&cpu_clk 0>; - i-cache-size = <0xc000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&l2_0>; - }; - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x001>; - enable-method = "psci"; - #cooling-cells = <2>; - clocks = <&cpu_clk 0>; - i-cache-size = <0xc000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&l2_0>; - }; - cpu2: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x100>; - enable-method = "psci"; - #cooling-cells = <2>; - clocks = <&cpu_clk 1>; - i-cache-size = <0xc000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&l2_1>; - }; - cpu3: cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x101>; - enable-method = "psci"; - #cooling-cells = <2>; - clocks = <&cpu_clk 1>; - i-cache-size = <0xc000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&l2_1>; - }; - - l2_0: l2-cache0 { - compatible = "cache"; - cache-size = <0x80000>; - cache-line-size = <64>; - cache-sets = <512>; - }; - - l2_1: l2-cache1 { - compatible = "cache"; - cache-size = <0x80000>; - cache-line-size = <64>; - cache-sets = <512>; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/marvell/armada-ap806.dtsi b/sys/gnu/dts/arm64/marvell/armada-ap806.dtsi deleted file mode 100644 index 866628679ac..00000000000 --- a/sys/gnu/dts/arm64/marvell/armada-ap806.dtsi +++ /dev/null @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2016 Marvell Technology Group Ltd. - * - * Device Tree file for Marvell Armada AP806. - */ - -#define AP_NAME ap806 -#include "armada-ap80x.dtsi" - -/ { - model = "Marvell Armada AP806"; - compatible = "marvell,armada-ap806"; -}; - -&ap_syscon0 { - ap_clk: clock { - compatible = "marvell,ap806-clock"; - #clock-cells = <1>; - }; -}; - -&ap_syscon1 { - cpu_clk: clock-cpu@278 { - compatible = "marvell,ap806-cpu-clock"; - clocks = <&ap_clk 0>, <&ap_clk 1>; - #clock-cells = <1>; - reg = <0x278 0xa30>; - }; -}; diff --git a/sys/gnu/dts/arm64/marvell/armada-ap807-quad.dtsi b/sys/gnu/dts/arm64/marvell/armada-ap807-quad.dtsi deleted file mode 100644 index 840466e143b..00000000000 --- a/sys/gnu/dts/arm64/marvell/armada-ap807-quad.dtsi +++ /dev/null @@ -1,93 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for Marvell Armada AP807 Quad - * - * Copyright (C) 2019 Marvell Technology Group Ltd. - */ - -#include "armada-ap807.dtsi" - -/ { - model = "Marvell Armada AP807 Quad"; - compatible = "marvell,armada-ap807-quad", "marvell,armada-ap807"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; - reg = <0x000>; - enable-method = "psci"; - #cooling-cells = <2>; - clocks = <&cpu_clk 0>; - i-cache-size = <0xc000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&l2_0>; - }; - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; - reg = <0x001>; - enable-method = "psci"; - #cooling-cells = <2>; - clocks = <&cpu_clk 0>; - i-cache-size = <0xc000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&l2_0>; - }; - cpu2: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; - reg = <0x100>; - enable-method = "psci"; - #cooling-cells = <2>; - clocks = <&cpu_clk 1>; - i-cache-size = <0xc000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&l2_1>; - }; - cpu3: cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; - reg = <0x101>; - enable-method = "psci"; - #cooling-cells = <2>; - clocks = <&cpu_clk 1>; - i-cache-size = <0xc000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&l2_1>; - }; - - l2_0: l2-cache0 { - compatible = "cache"; - cache-size = <0x80000>; - cache-line-size = <64>; - cache-sets = <512>; - }; - - l2_1: l2-cache1 { - compatible = "cache"; - cache-size = <0x80000>; - cache-line-size = <64>; - cache-sets = <512>; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/marvell/armada-ap807.dtsi b/sys/gnu/dts/arm64/marvell/armada-ap807.dtsi deleted file mode 100644 index 623010f3ca8..00000000000 --- a/sys/gnu/dts/arm64/marvell/armada-ap807.dtsi +++ /dev/null @@ -1,29 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for Marvell Armada AP807 - * - * Copyright (C) 2019 Marvell Technology Group Ltd. - */ - -#define AP_NAME ap807 -#include "armada-ap80x.dtsi" - -/ { - model = "Marvell Armada AP807"; - compatible = "marvell,armada-ap807"; -}; - -&ap_syscon0 { - ap_clk: clock { - compatible = "marvell,ap807-clock"; - #clock-cells = <1>; - }; -}; - -&ap_syscon1 { - cpu_clk: clock-cpu { - compatible = "marvell,ap807-cpu-clock"; - clocks = <&ap_clk 0>, <&ap_clk 1>; - #clock-cells = <1>; - }; -}; diff --git a/sys/gnu/dts/arm64/marvell/armada-ap80x.dtsi b/sys/gnu/dts/arm64/marvell/armada-ap80x.dtsi deleted file mode 100644 index e7438c21cce..00000000000 --- a/sys/gnu/dts/arm64/marvell/armada-ap80x.dtsi +++ /dev/null @@ -1,444 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2019 Marvell Technology Group Ltd. - * - * Device Tree file for Marvell Armada AP80x. - */ - -#include -#include - -/dts-v1/; - -/ { - #address-cells = <2>; - #size-cells = <2>; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - gpio0 = &ap_gpio; - spi0 = &spi0; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - /* - * This area matches the mapping done with a - * mainline U-Boot, and should be updated by the - * bootloader. - */ - - psci-area@4000000 { - reg = <0x0 0x4000000 0x0 0x200000>; - no-map; - }; - }; - - AP_NAME { - #address-cells = <2>; - #size-cells = <2>; - compatible = "simple-bus"; - interrupt-parent = <&gic>; - ranges; - - config-space@f0000000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0x0 0x0 0xf0000000 0x1000000>; - - gic: interrupt-controller@210000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - interrupt-controller; - interrupts = ; - reg = <0x210000 0x10000>, - <0x220000 0x20000>, - <0x240000 0x20000>, - <0x260000 0x20000>; - - gic_v2m0: v2m@280000 { - compatible = "arm,gic-v2m-frame"; - msi-controller; - reg = <0x280000 0x1000>; - arm,msi-base-spi = <160>; - arm,msi-num-spis = <32>; - }; - gic_v2m1: v2m@290000 { - compatible = "arm,gic-v2m-frame"; - msi-controller; - reg = <0x290000 0x1000>; - arm,msi-base-spi = <192>; - arm,msi-num-spis = <32>; - }; - gic_v2m2: v2m@2a0000 { - compatible = "arm,gic-v2m-frame"; - msi-controller; - reg = <0x2a0000 0x1000>; - arm,msi-base-spi = <224>; - arm,msi-num-spis = <32>; - }; - gic_v2m3: v2m@2b0000 { - compatible = "arm,gic-v2m-frame"; - msi-controller; - reg = <0x2b0000 0x1000>; - arm,msi-base-spi = <256>; - arm,msi-num-spis = <32>; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - pmu { - compatible = "arm,cortex-a72-pmu"; - interrupt-parent = <&pic>; - interrupts = <17>; - }; - - odmi: odmi@300000 { - compatible = "marvell,odmi-controller"; - interrupt-controller; - msi-controller; - marvell,odmi-frames = <4>; - reg = <0x300000 0x4000>, - <0x304000 0x4000>, - <0x308000 0x4000>, - <0x30C000 0x4000>; - marvell,spi-base = <128>, <136>, <144>, <152>; - }; - - gicp: gicp@3f0040 { - compatible = "marvell,ap806-gicp"; - reg = <0x3f0040 0x10>; - marvell,spi-ranges = <64 64>, <288 64>; - msi-controller; - }; - - pic: interrupt-controller@3f0100 { - compatible = "marvell,armada-8k-pic"; - reg = <0x3f0100 0x10>; - #interrupt-cells = <1>; - interrupt-controller; - interrupts = ; - }; - - sei: interrupt-controller@3f0200 { - compatible = "marvell,ap806-sei"; - reg = <0x3f0200 0x40>; - interrupts = ; - #interrupt-cells = <1>; - interrupt-controller; - msi-controller; - }; - - xor@400000 { - compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; - reg = <0x400000 0x1000>, - <0x410000 0x1000>; - msi-parent = <&gic_v2m0>; - clocks = <&ap_clk 3>; - dma-coherent; - }; - - xor@420000 { - compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; - reg = <0x420000 0x1000>, - <0x430000 0x1000>; - msi-parent = <&gic_v2m0>; - clocks = <&ap_clk 3>; - dma-coherent; - }; - - xor@440000 { - compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; - reg = <0x440000 0x1000>, - <0x450000 0x1000>; - msi-parent = <&gic_v2m0>; - clocks = <&ap_clk 3>; - dma-coherent; - }; - - xor@460000 { - compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; - reg = <0x460000 0x1000>, - <0x470000 0x1000>; - msi-parent = <&gic_v2m0>; - clocks = <&ap_clk 3>; - dma-coherent; - }; - - spi0: spi@510600 { - compatible = "marvell,armada-380-spi"; - reg = <0x510600 0x50>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clocks = <&ap_clk 3>; - status = "disabled"; - }; - - i2c0: i2c@511000 { - compatible = "marvell,mv78230-i2c"; - reg = <0x511000 0x20>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - timeout-ms = <1000>; - clocks = <&ap_clk 3>; - status = "disabled"; - }; - - uart0: serial@512000 { - compatible = "snps,dw-apb-uart"; - reg = <0x512000 0x100>; - reg-shift = <2>; - interrupts = ; - reg-io-width = <1>; - clocks = <&ap_clk 3>; - status = "disabled"; - }; - - uart1: serial@512100 { - compatible = "snps,dw-apb-uart"; - reg = <0x512100 0x100>; - reg-shift = <2>; - interrupts = ; - reg-io-width = <1>; - clocks = <&ap_clk 3>; - status = "disabled"; - - }; - - watchdog: watchdog@610000 { - compatible = "arm,sbsa-gwdt"; - reg = <0x610000 0x1000>, <0x600000 0x1000>; - interrupts = ; - }; - - ap_sdhci0: sdhci@6e0000 { - compatible = "marvell,armada-ap806-sdhci"; - reg = <0x6e0000 0x300>; - interrupts = ; - clock-names = "core"; - clocks = <&ap_clk 4>; - dma-coherent; - marvell,xenon-phy-slow-mode; - status = "disabled"; - }; - - ap_syscon0: system-controller@6f4000 { - compatible = "syscon", "simple-mfd"; - reg = <0x6f4000 0x2000>; - - ap_pinctrl: pinctrl { - compatible = "marvell,ap806-pinctrl"; - - uart0_pins: uart0-pins { - marvell,pins = "mpp11", "mpp19"; - marvell,function = "uart0"; - }; - }; - - ap_gpio: gpio@1040 { - compatible = "marvell,armada-8k-gpio"; - offset = <0x1040>; - ngpios = <20>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&ap_pinctrl 0 0 20>; - }; - }; - - ap_syscon1: system-controller@6f8000 { - compatible = "syscon", "simple-mfd"; - reg = <0x6f8000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - - ap_thermal: thermal-sensor@80 { - compatible = "marvell,armada-ap806-thermal"; - reg = <0x80 0x10>; - interrupt-parent = <&sei>; - interrupts = <18>; - #thermal-sensor-cells = <1>; - }; - }; - }; - }; - - /* - * The thermal IP features one internal sensor plus, if applicable, one - * remote channel wired to one sensor per CPU. - * - * Only one thermal zone per AP/CP may trigger interrupts at a time, the - * first one that will have a critical trip point will be chosen. - */ - thermal-zones { - ap_thermal_ic: ap-thermal-ic { - polling-delay-passive = <0>; /* Interrupt driven */ - polling-delay = <0>; /* Interrupt driven */ - - thermal-sensors = <&ap_thermal 0>; - - trips { - ap_crit: ap-crit { - temperature = <100000>; /* mC degrees */ - hysteresis = <2000>; /* mC degrees */ - type = "critical"; - }; - }; - - cooling-maps { }; - }; - - ap_thermal_cpu0: ap-thermal-cpu0 { - polling-delay-passive = <1000>; - polling-delay = <1000>; - - thermal-sensors = <&ap_thermal 1>; - - trips { - cpu0_hot: cpu0-hot { - temperature = <85000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu0_emerg: cpu0-emerg { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - }; - - cooling-maps { - map0_hot: map0-hot { - trip = <&cpu0_hot>; - cooling-device = <&cpu0 1 2>, - <&cpu1 1 2>; - }; - map0_emerg: map0-ermerg { - trip = <&cpu0_emerg>; - cooling-device = <&cpu0 3 3>, - <&cpu1 3 3>; - }; - }; - }; - - ap_thermal_cpu1: ap-thermal-cpu1 { - polling-delay-passive = <1000>; - polling-delay = <1000>; - - thermal-sensors = <&ap_thermal 2>; - - trips { - cpu1_hot: cpu1-hot { - temperature = <85000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu1_emerg: cpu1-emerg { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - }; - - cooling-maps { - map1_hot: map1-hot { - trip = <&cpu1_hot>; - cooling-device = <&cpu0 1 2>, - <&cpu1 1 2>; - }; - map1_emerg: map1-emerg { - trip = <&cpu1_emerg>; - cooling-device = <&cpu0 3 3>, - <&cpu1 3 3>; - }; - }; - }; - - ap_thermal_cpu2: ap-thermal-cpu2 { - polling-delay-passive = <1000>; - polling-delay = <1000>; - - thermal-sensors = <&ap_thermal 3>; - - trips { - cpu2_hot: cpu2-hot { - temperature = <85000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu2_emerg: cpu2-emerg { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - }; - - cooling-maps { - map2_hot: map2-hot { - trip = <&cpu2_hot>; - cooling-device = <&cpu2 1 2>, - <&cpu3 1 2>; - }; - map2_emerg: map2-emerg { - trip = <&cpu2_emerg>; - cooling-device = <&cpu2 3 3>, - <&cpu3 3 3>; - }; - }; - }; - - ap_thermal_cpu3: ap-thermal-cpu3 { - polling-delay-passive = <1000>; - polling-delay = <1000>; - - thermal-sensors = <&ap_thermal 4>; - - trips { - cpu3_hot: cpu3-hot { - temperature = <85000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu3_emerg: cpu3-emerg { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - }; - - cooling-maps { - map3_hot: map3-bhot { - trip = <&cpu3_hot>; - cooling-device = <&cpu2 1 2>, - <&cpu3 1 2>; - }; - map3_emerg: map3-emerg { - trip = <&cpu3_emerg>; - cooling-device = <&cpu2 3 3>, - <&cpu3 3 3>; - }; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/marvell/armada-ap810-ap0-octa-core.dtsi b/sys/gnu/dts/arm64/marvell/armada-ap810-ap0-octa-core.dtsi deleted file mode 100644 index d1a7143ef3d..00000000000 --- a/sys/gnu/dts/arm64/marvell/armada-ap810-ap0-octa-core.dtsi +++ /dev/null @@ -1,65 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2017 Marvell Technology Group Ltd. - * - * Device Tree file for Marvell Armada AP810 OCTA cores. - */ - -#include "armada-ap810-ap0.dtsi" - -/ { - cpus { - #address-cells = <1>; - #size-cells = <0>; - compatible = "marvell,armada-ap810-octa"; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x000>; - enable-method = "psci"; - }; - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x001>; - enable-method = "psci"; - }; - cpu2: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x100>; - enable-method = "psci"; - }; - cpu3: cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x101>; - enable-method = "psci"; - }; - cpu4: cpu@200 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x200>; - enable-method = "psci"; - }; - cpu5: cpu@201 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x201>; - enable-method = "psci"; - }; - cpu6: cpu@300 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x300>; - enable-method = "psci"; - }; - cpu7: cpu@301 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x301>; - enable-method = "psci"; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/marvell/armada-ap810-ap0.dtsi b/sys/gnu/dts/arm64/marvell/armada-ap810-ap0.dtsi deleted file mode 100644 index 8107d120a8a..00000000000 --- a/sys/gnu/dts/arm64/marvell/armada-ap810-ap0.dtsi +++ /dev/null @@ -1,124 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2017 Marvell Technology Group Ltd. - * - * Device Tree file for Marvell Armada AP810. - */ - -#include - -/dts-v1/; - -/ { - model = "Marvell Armada AP810"; - compatible = "marvell,armada-ap810"; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - serial0 = &uart0_ap0; - serial1 = &uart1_ap0; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - ap810-ap0 { - #address-cells = <2>; - #size-cells = <2>; - compatible = "simple-bus"; - interrupt-parent = <&gic>; - ranges; - - config-space@e8000000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0x0 0x0 0xe8000000 0x4000000>; - interrupt-parent = <&gic>; - - gic: interrupt-controller@3000000 { - compatible = "arm,gic-v3"; - #interrupt-cells = <3>; - #address-cells = <1>; - #size-cells = <1>; - interrupt-controller; - interrupts = ; - ranges; - - reg = <0x3000000 0x10000>, /* GICD */ - <0x3060000 0x100000>, /* GICR */ - <0x00c0000 0x2000>, /* GICC */ - <0x00d0000 0x1000>, /* GICH */ - <0x00e0000 0x2000>; /* GICV */ - - gic_its_ap0: interrupt-controller@3040000 { - compatible = "arm,gic-v3-its"; - msi-controller; - #msi-cells = <1>; - reg = <0x3040000 0x20000>; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - xor@400000 { - compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; - reg = <0x400000 0x1000>, - <0x410000 0x1000>; - msi-parent = <&gic_its_ap0 0xa0>; - dma-coherent; - }; - - xor@420000 { - compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; - reg = <0x420000 0x1000>, - <0x430000 0x1000>; - msi-parent = <&gic_its_ap0 0xa1>; - dma-coherent; - }; - - xor@440000 { - compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; - reg = <0x440000 0x1000>, - <0x450000 0x1000>; - msi-parent = <&gic_its_ap0 0xa2>; - dma-coherent; - }; - - xor@460000 { - compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; - reg = <0x460000 0x1000>, - <0x470000 0x1000>; - msi-parent = <&gic_its_ap0 0xa3>; - dma-coherent; - }; - - uart0_ap0: serial@512000 { - compatible = "snps,dw-apb-uart"; - reg = <0x512000 0x100>; - reg-shift = <2>; - interrupts = ; - reg-io-width = <1>; - status = "disabled"; - }; - - uart1_ap0: serial@512100 { - compatible = "snps,dw-apb-uart"; - reg = <0x512100 0x100>; - reg-shift = <2>; - interrupts = ; - reg-io-width = <1>; - status = "disabled"; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/marvell/armada-common.dtsi b/sys/gnu/dts/arm64/marvell/armada-common.dtsi deleted file mode 100644 index c04c6c47502..00000000000 --- a/sys/gnu/dts/arm64/marvell/armada-common.dtsi +++ /dev/null @@ -1,11 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2016 Marvell Technology Group Ltd. - */ - -/* Common definitions used by Armada 7K/8K DTs */ -#define PASTER(x, y) x ## y -#define EVALUATOR(x, y) PASTER(x, y) -#define CP11X_LABEL(name) EVALUATOR(CP11X_NAME, EVALUATOR(_, name)) -#define CP11X_NODE_NAME(name) EVALUATOR(CP11X_NAME, EVALUATOR(-, name)) -#define ADDRESSIFY(addr) EVALUATOR(0x, addr) diff --git a/sys/gnu/dts/arm64/marvell/armada-cp110.dtsi b/sys/gnu/dts/arm64/marvell/armada-cp110.dtsi deleted file mode 100644 index 4fd33b0fa56..00000000000 --- a/sys/gnu/dts/arm64/marvell/armada-cp110.dtsi +++ /dev/null @@ -1,12 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2019 Marvell Technology Group Ltd. - * - * Device Tree file for Marvell Armada CP110. - */ - -#define CP11X_TYPE cp110 - -#include "armada-cp11x.dtsi" - -#undef CP11X_TYPE diff --git a/sys/gnu/dts/arm64/marvell/armada-cp115.dtsi b/sys/gnu/dts/arm64/marvell/armada-cp115.dtsi deleted file mode 100644 index 1d0a9653e68..00000000000 --- a/sys/gnu/dts/arm64/marvell/armada-cp115.dtsi +++ /dev/null @@ -1,12 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2019 Marvell Technology Group Ltd. - * - * Device Tree file for Marvell Armada CP115. - */ - -#define CP11X_TYPE cp115 - -#include "armada-cp11x.dtsi" - -#undef CP11X_TYPE diff --git a/sys/gnu/dts/arm64/marvell/armada-cp11x.dtsi b/sys/gnu/dts/arm64/marvell/armada-cp11x.dtsi deleted file mode 100644 index 9dcf16beabf..00000000000 --- a/sys/gnu/dts/arm64/marvell/armada-cp11x.dtsi +++ /dev/null @@ -1,568 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2016 Marvell Technology Group Ltd. - * - * Device Tree file for Marvell Armada CP11x. - */ - -#include -#include - -#include "armada-common.dtsi" - -#define CP11X_PCIEx_CONF_BASE(iface) (CP11X_PCIEx_MEM_BASE(iface) + CP11X_PCIEx_MEM_SIZE(iface)) - -/ { - /* - * The contents of the node are defined below, in order to - * save one indentation level - */ - CP11X_NAME: CP11X_NAME { }; - - /* - * CPs only have one sensor in the thermal IC. - * - * The cooling maps are empty as there are no cooling devices. - */ - thermal-zones { - CP11X_LABEL(thermal_ic): CP11X_NODE_NAME(thermal-ic) { - polling-delay-passive = <0>; /* Interrupt driven */ - polling-delay = <0>; /* Interrupt driven */ - - thermal-sensors = <&CP11X_LABEL(thermal) 0>; - - trips { - CP11X_LABEL(crit): crit { - temperature = <100000>; /* mC degrees */ - hysteresis = <2000>; /* mC degrees */ - type = "critical"; - }; - }; - - cooling-maps { }; - }; - }; -}; - -&CP11X_NAME { - #address-cells = <2>; - #size-cells = <2>; - compatible = "simple-bus"; - interrupt-parent = <&CP11X_LABEL(icu_nsr)>; - ranges; - - config-space@CP11X_BASE { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0x0 0x0 ADDRESSIFY(CP11X_BASE) 0x2000000>; - - CP11X_LABEL(ethernet): ethernet@0 { - compatible = "marvell,armada-7k-pp22"; - reg = <0x0 0x100000>, <0x129000 0xb000>; - clocks = <&CP11X_LABEL(clk) 1 3>, <&CP11X_LABEL(clk) 1 9>, - <&CP11X_LABEL(clk) 1 5>, <&CP11X_LABEL(clk) 1 6>, - <&CP11X_LABEL(clk) 1 18>; - clock-names = "pp_clk", "gop_clk", - "mg_clk", "mg_core_clk", "axi_clk"; - marvell,system-controller = <&CP11X_LABEL(syscon0)>; - status = "disabled"; - dma-coherent; - - CP11X_LABEL(eth0): eth0 { - interrupts = <39 IRQ_TYPE_LEVEL_HIGH>, - <43 IRQ_TYPE_LEVEL_HIGH>, - <47 IRQ_TYPE_LEVEL_HIGH>, - <51 IRQ_TYPE_LEVEL_HIGH>, - <55 IRQ_TYPE_LEVEL_HIGH>, - <59 IRQ_TYPE_LEVEL_HIGH>, - <63 IRQ_TYPE_LEVEL_HIGH>, - <67 IRQ_TYPE_LEVEL_HIGH>, - <71 IRQ_TYPE_LEVEL_HIGH>, - <129 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "hif0", "hif1", "hif2", - "hif3", "hif4", "hif5", "hif6", "hif7", - "hif8", "link"; - port-id = <0>; - gop-port-id = <0>; - status = "disabled"; - }; - - CP11X_LABEL(eth1): eth1 { - interrupts = <40 IRQ_TYPE_LEVEL_HIGH>, - <44 IRQ_TYPE_LEVEL_HIGH>, - <48 IRQ_TYPE_LEVEL_HIGH>, - <52 IRQ_TYPE_LEVEL_HIGH>, - <56 IRQ_TYPE_LEVEL_HIGH>, - <60 IRQ_TYPE_LEVEL_HIGH>, - <64 IRQ_TYPE_LEVEL_HIGH>, - <68 IRQ_TYPE_LEVEL_HIGH>, - <72 IRQ_TYPE_LEVEL_HIGH>, - <128 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "hif0", "hif1", "hif2", - "hif3", "hif4", "hif5", "hif6", "hif7", - "hif8", "link"; - port-id = <1>; - gop-port-id = <2>; - status = "disabled"; - }; - - CP11X_LABEL(eth2): eth2 { - interrupts = <41 IRQ_TYPE_LEVEL_HIGH>, - <45 IRQ_TYPE_LEVEL_HIGH>, - <49 IRQ_TYPE_LEVEL_HIGH>, - <53 IRQ_TYPE_LEVEL_HIGH>, - <57 IRQ_TYPE_LEVEL_HIGH>, - <61 IRQ_TYPE_LEVEL_HIGH>, - <65 IRQ_TYPE_LEVEL_HIGH>, - <69 IRQ_TYPE_LEVEL_HIGH>, - <73 IRQ_TYPE_LEVEL_HIGH>, - <127 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "hif0", "hif1", "hif2", - "hif3", "hif4", "hif5", "hif6", "hif7", - "hif8", "link"; - port-id = <2>; - gop-port-id = <3>; - status = "disabled"; - }; - }; - - CP11X_LABEL(comphy): phy@120000 { - compatible = "marvell,comphy-cp110"; - reg = <0x120000 0x6000>; - marvell,system-controller = <&CP11X_LABEL(syscon0)>; - clocks = <&CP11X_LABEL(clk) 1 5>, <&CP11X_LABEL(clk) 1 6>, - <&CP11X_LABEL(clk) 1 18>; - clock-names = "mg_clk", "mg_core_clk", "axi_clk"; - #address-cells = <1>; - #size-cells = <0>; - - CP11X_LABEL(comphy0): phy@0 { - reg = <0>; - #phy-cells = <1>; - }; - - CP11X_LABEL(comphy1): phy@1 { - reg = <1>; - #phy-cells = <1>; - }; - - CP11X_LABEL(comphy2): phy@2 { - reg = <2>; - #phy-cells = <1>; - }; - - CP11X_LABEL(comphy3): phy@3 { - reg = <3>; - #phy-cells = <1>; - }; - - CP11X_LABEL(comphy4): phy@4 { - reg = <4>; - #phy-cells = <1>; - }; - - CP11X_LABEL(comphy5): phy@5 { - reg = <5>; - #phy-cells = <1>; - }; - }; - - CP11X_LABEL(mdio): mdio@12a200 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "marvell,orion-mdio"; - reg = <0x12a200 0x10>; - clocks = <&CP11X_LABEL(clk) 1 9>, <&CP11X_LABEL(clk) 1 5>, - <&CP11X_LABEL(clk) 1 6>, <&CP11X_LABEL(clk) 1 18>; - status = "disabled"; - }; - - CP11X_LABEL(xmdio): mdio@12a600 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "marvell,xmdio"; - reg = <0x12a600 0x10>; - clocks = <&CP11X_LABEL(clk) 1 5>, - <&CP11X_LABEL(clk) 1 6>, <&CP11X_LABEL(clk) 1 18>; - status = "disabled"; - }; - - CP11X_LABEL(icu): interrupt-controller@1e0000 { - compatible = "marvell,cp110-icu"; - reg = <0x1e0000 0x440>; - #address-cells = <1>; - #size-cells = <1>; - - CP11X_LABEL(icu_nsr): interrupt-controller@10 { - compatible = "marvell,cp110-icu-nsr"; - reg = <0x10 0x20>; - #interrupt-cells = <2>; - interrupt-controller; - msi-parent = <&gicp>; - }; - - CP11X_LABEL(icu_sei): interrupt-controller@50 { - compatible = "marvell,cp110-icu-sei"; - reg = <0x50 0x10>; - #interrupt-cells = <2>; - interrupt-controller; - msi-parent = <&sei>; - }; - }; - - CP11X_LABEL(rtc): rtc@284000 { - compatible = "marvell,armada-8k-rtc"; - reg = <0x284000 0x20>, <0x284080 0x24>; - reg-names = "rtc", "rtc-soc"; - interrupts = <77 IRQ_TYPE_LEVEL_HIGH>; - }; - - CP11X_LABEL(syscon0): system-controller@440000 { - compatible = "syscon", "simple-mfd"; - reg = <0x440000 0x2000>; - - CP11X_LABEL(clk): clock { - compatible = "marvell,cp110-clock"; - #clock-cells = <2>; - }; - - CP11X_LABEL(gpio1): gpio@100 { - compatible = "marvell,armada-8k-gpio"; - offset = <0x100>; - ngpios = <32>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&CP11X_LABEL(pinctrl) 0 0 32>; - interrupt-controller; - interrupts = <86 IRQ_TYPE_LEVEL_HIGH>, - <85 IRQ_TYPE_LEVEL_HIGH>, - <84 IRQ_TYPE_LEVEL_HIGH>, - <83 IRQ_TYPE_LEVEL_HIGH>; - #interrupt-cells = <2>; - status = "disabled"; - }; - - CP11X_LABEL(gpio2): gpio@140 { - compatible = "marvell,armada-8k-gpio"; - offset = <0x140>; - ngpios = <31>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&CP11X_LABEL(pinctrl) 0 32 31>; - interrupt-controller; - interrupts = <82 IRQ_TYPE_LEVEL_HIGH>, - <81 IRQ_TYPE_LEVEL_HIGH>, - <80 IRQ_TYPE_LEVEL_HIGH>, - <79 IRQ_TYPE_LEVEL_HIGH>; - #interrupt-cells = <2>; - status = "disabled"; - }; - }; - - CP11X_LABEL(syscon1): system-controller@400000 { - compatible = "syscon", "simple-mfd"; - reg = <0x400000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - - CP11X_LABEL(thermal): thermal-sensor@70 { - compatible = "marvell,armada-cp110-thermal"; - reg = <0x70 0x10>; - interrupts-extended = - <&CP11X_LABEL(icu_sei) 116 IRQ_TYPE_LEVEL_HIGH>; - #thermal-sensor-cells = <1>; - }; - }; - - CP11X_LABEL(usb3_0): usb3@500000 { - compatible = "marvell,armada-8k-xhci", - "generic-xhci"; - reg = <0x500000 0x4000>; - dma-coherent; - interrupts = <106 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "core", "reg"; - clocks = <&CP11X_LABEL(clk) 1 22>, - <&CP11X_LABEL(clk) 1 16>; - status = "disabled"; - }; - - CP11X_LABEL(usb3_1): usb3@510000 { - compatible = "marvell,armada-8k-xhci", - "generic-xhci"; - reg = <0x510000 0x4000>; - dma-coherent; - interrupts = <105 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "core", "reg"; - clocks = <&CP11X_LABEL(clk) 1 23>, - <&CP11X_LABEL(clk) 1 16>; - status = "disabled"; - }; - - CP11X_LABEL(sata0): sata@540000 { - compatible = "marvell,armada-8k-ahci", - "generic-ahci"; - reg = <0x540000 0x30000>; - dma-coherent; - interrupts = <107 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&CP11X_LABEL(clk) 1 15>, - <&CP11X_LABEL(clk) 1 16>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - sata-port@0 { - reg = <0>; - }; - - sata-port@1 { - reg = <1>; - }; - }; - - CP11X_LABEL(xor0): xor@6a0000 { - compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; - reg = <0x6a0000 0x1000>, <0x6b0000 0x1000>; - dma-coherent; - msi-parent = <&gic_v2m0>; - clock-names = "core", "reg"; - clocks = <&CP11X_LABEL(clk) 1 8>, - <&CP11X_LABEL(clk) 1 14>; - }; - - CP11X_LABEL(xor1): xor@6c0000 { - compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; - reg = <0x6c0000 0x1000>, <0x6d0000 0x1000>; - dma-coherent; - msi-parent = <&gic_v2m0>; - clock-names = "core", "reg"; - clocks = <&CP11X_LABEL(clk) 1 7>, - <&CP11X_LABEL(clk) 1 14>; - }; - - CP11X_LABEL(spi0): spi@700600 { - compatible = "marvell,armada-380-spi"; - reg = <0x700600 0x50>; - #address-cells = <0x1>; - #size-cells = <0x0>; - clock-names = "core", "axi"; - clocks = <&CP11X_LABEL(clk) 1 21>, - <&CP11X_LABEL(clk) 1 17>; - status = "disabled"; - }; - - CP11X_LABEL(spi1): spi@700680 { - compatible = "marvell,armada-380-spi"; - reg = <0x700680 0x50>; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "core", "axi"; - clocks = <&CP11X_LABEL(clk) 1 21>, - <&CP11X_LABEL(clk) 1 17>; - status = "disabled"; - }; - - CP11X_LABEL(i2c0): i2c@701000 { - compatible = "marvell,mv78230-i2c"; - reg = <0x701000 0x20>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <120 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "core", "reg"; - clocks = <&CP11X_LABEL(clk) 1 21>, - <&CP11X_LABEL(clk) 1 17>; - status = "disabled"; - }; - - CP11X_LABEL(i2c1): i2c@701100 { - compatible = "marvell,mv78230-i2c"; - reg = <0x701100 0x20>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <121 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "core", "reg"; - clocks = <&CP11X_LABEL(clk) 1 21>, - <&CP11X_LABEL(clk) 1 17>; - status = "disabled"; - }; - - CP11X_LABEL(uart0): serial@702000 { - compatible = "snps,dw-apb-uart"; - reg = <0x702000 0x100>; - reg-shift = <2>; - interrupts = <122 IRQ_TYPE_LEVEL_HIGH>; - reg-io-width = <1>; - clock-names = "baudclk", "apb_pclk"; - clocks = <&CP11X_LABEL(clk) 1 21>, - <&CP11X_LABEL(clk) 1 17>; - status = "disabled"; - }; - - CP11X_LABEL(uart1): serial@702100 { - compatible = "snps,dw-apb-uart"; - reg = <0x702100 0x100>; - reg-shift = <2>; - interrupts = <123 IRQ_TYPE_LEVEL_HIGH>; - reg-io-width = <1>; - clock-names = "baudclk", "apb_pclk"; - clocks = <&CP11X_LABEL(clk) 1 21>, - <&CP11X_LABEL(clk) 1 17>; - status = "disabled"; - }; - - CP11X_LABEL(uart2): serial@702200 { - compatible = "snps,dw-apb-uart"; - reg = <0x702200 0x100>; - reg-shift = <2>; - interrupts = <124 IRQ_TYPE_LEVEL_HIGH>; - reg-io-width = <1>; - clock-names = "baudclk", "apb_pclk"; - clocks = <&CP11X_LABEL(clk) 1 21>, - <&CP11X_LABEL(clk) 1 17>; - status = "disabled"; - }; - - CP11X_LABEL(uart3): serial@702300 { - compatible = "snps,dw-apb-uart"; - reg = <0x702300 0x100>; - reg-shift = <2>; - interrupts = <125 IRQ_TYPE_LEVEL_HIGH>; - reg-io-width = <1>; - clock-names = "baudclk", "apb_pclk"; - clocks = <&CP11X_LABEL(clk) 1 21>, - <&CP11X_LABEL(clk) 1 17>; - status = "disabled"; - }; - - CP11X_LABEL(nand_controller): nand@720000 { - /* - * Due to the limitation of the pins available - * this controller is only usable on the CPM - * for A7K and on the CPS for A8K. - */ - compatible = "marvell,armada-8k-nand-controller", - "marvell,armada370-nand-controller"; - reg = <0x720000 0x54>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <115 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "core", "reg"; - clocks = <&CP11X_LABEL(clk) 1 2>, - <&CP11X_LABEL(clk) 1 17>; - marvell,system-controller = <&CP11X_LABEL(syscon0)>; - status = "disabled"; - }; - - CP11X_LABEL(trng): trng@760000 { - compatible = "marvell,armada-8k-rng", - "inside-secure,safexcel-eip76"; - reg = <0x760000 0x7d>; - interrupts = <95 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "core", "reg"; - clocks = <&CP11X_LABEL(clk) 1 25>, - <&CP11X_LABEL(clk) 1 17>; - status = "okay"; - }; - - CP11X_LABEL(sdhci0): sdhci@780000 { - compatible = "marvell,armada-cp110-sdhci"; - reg = <0x780000 0x300>; - interrupts = <27 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "core", "axi"; - clocks = <&CP11X_LABEL(clk) 1 4>, <&CP11X_LABEL(clk) 1 18>; - dma-coherent; - status = "disabled"; - }; - - CP11X_LABEL(crypto): crypto@800000 { - compatible = "inside-secure,safexcel-eip197b"; - reg = <0x800000 0x200000>; - interrupts = <87 IRQ_TYPE_LEVEL_HIGH>, - <88 IRQ_TYPE_LEVEL_HIGH>, - <89 IRQ_TYPE_LEVEL_HIGH>, - <90 IRQ_TYPE_LEVEL_HIGH>, - <91 IRQ_TYPE_LEVEL_HIGH>, - <92 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "mem", "ring0", "ring1", - "ring2", "ring3", "eip"; - clock-names = "core", "reg"; - clocks = <&CP11X_LABEL(clk) 1 26>, - <&CP11X_LABEL(clk) 1 17>; - dma-coherent; - }; - }; - - CP11X_LABEL(pcie0): pcie@CP11X_PCIE0_BASE { - compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; - reg = <0 ADDRESSIFY(CP11X_PCIE0_BASE) 0 0x10000>, - <0 CP11X_PCIEx_CONF_BASE(0) 0 0x80000>; - reg-names = "ctrl", "config"; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - device_type = "pci"; - dma-coherent; - msi-parent = <&gic_v2m0>; - - bus-range = <0 0xff>; - /* non-prefetchable memory */ - ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(0) 0 CP11X_PCIEx_MEM_BASE(0) 0 CP11X_PCIEx_MEM_SIZE(0)>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 22 IRQ_TYPE_LEVEL_HIGH>; - interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; - num-lanes = <1>; - clock-names = "core", "reg"; - clocks = <&CP11X_LABEL(clk) 1 13>, <&CP11X_LABEL(clk) 1 14>; - status = "disabled"; - }; - - CP11X_LABEL(pcie1): pcie@CP11X_PCIE1_BASE { - compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; - reg = <0 ADDRESSIFY(CP11X_PCIE1_BASE) 0 0x10000>, - <0 CP11X_PCIEx_CONF_BASE(1) 0 0x80000>; - reg-names = "ctrl", "config"; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - device_type = "pci"; - dma-coherent; - msi-parent = <&gic_v2m0>; - - bus-range = <0 0xff>; - /* non-prefetchable memory */ - ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(1) 0 CP11X_PCIEx_MEM_BASE(1) 0 CP11X_PCIEx_MEM_SIZE(1)>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 24 IRQ_TYPE_LEVEL_HIGH>; - interrupts = <24 IRQ_TYPE_LEVEL_HIGH>; - - num-lanes = <1>; - clock-names = "core", "reg"; - clocks = <&CP11X_LABEL(clk) 1 11>, <&CP11X_LABEL(clk) 1 14>; - status = "disabled"; - }; - - CP11X_LABEL(pcie2): pcie@CP11X_PCIE2_BASE { - compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; - reg = <0 ADDRESSIFY(CP11X_PCIE2_BASE) 0 0x10000>, - <0 CP11X_PCIEx_CONF_BASE(2) 0 0x80000>; - reg-names = "ctrl", "config"; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - device_type = "pci"; - dma-coherent; - msi-parent = <&gic_v2m0>; - - bus-range = <0 0xff>; - /* non-prefetchable memory */ - ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(2) 0 CP11X_PCIEx_MEM_BASE(2) 0 CP11X_PCIEx_MEM_SIZE(2)>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 23 IRQ_TYPE_LEVEL_HIGH>; - interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; - - num-lanes = <1>; - clock-names = "core", "reg"; - clocks = <&CP11X_LABEL(clk) 1 12>, <&CP11X_LABEL(clk) 1 14>; - status = "disabled"; - }; -}; diff --git a/sys/gnu/dts/arm64/marvell/cn9130-db.dts b/sys/gnu/dts/arm64/marvell/cn9130-db.dts deleted file mode 100644 index ce49a70d88a..00000000000 --- a/sys/gnu/dts/arm64/marvell/cn9130-db.dts +++ /dev/null @@ -1,403 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2019 Marvell International Ltd. - * - * Device tree for the CN9130-DB board. - */ - -#include "cn9130.dtsi" - -#include - -/ { - model = "Marvell Armada CN9130-DB"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - aliases { - gpio1 = &cp0_gpio1; - gpio2 = &cp0_gpio2; - i2c0 = &cp0_i2c0; - ethernet0 = &cp0_eth0; - ethernet1 = &cp0_eth1; - ethernet2 = &cp0_eth2; - spi1 = &cp0_spi0; - spi2 = &cp0_spi1; - }; - - memory@00000000 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; - - ap0_reg_sd_vccq: ap0_sd_vccq@0 { - compatible = "regulator-gpio"; - regulator-name = "ap0_sd_vccq"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - gpios = <&expander0 8 GPIO_ACTIVE_HIGH>; - states = <1800000 0x1 3300000 0x0>; - }; - - cp0_reg_usb3_vbus0: cp0_usb3_vbus@0 { - compatible = "regulator-fixed"; - regulator-name = "cp0-xhci0-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&expander0 0 GPIO_ACTIVE_HIGH>; - }; - - cp0_usb3_0_phy0: cp0_usb3_phy@0 { - compatible = "usb-nop-xceiv"; - vcc-supply = <&cp0_reg_usb3_vbus0>; - }; - - cp0_reg_usb3_vbus1: cp0_usb3_vbus@1 { - compatible = "regulator-fixed"; - regulator-name = "cp0-xhci1-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&expander0 1 GPIO_ACTIVE_HIGH>; - }; - - cp0_usb3_0_phy1: cp0_usb3_phy@1 { - compatible = "usb-nop-xceiv"; - vcc-supply = <&cp0_reg_usb3_vbus1>; - }; - - cp0_reg_sd_vccq: cp0_sd_vccq@0 { - compatible = "regulator-gpio"; - regulator-name = "cp0_sd_vccq"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - gpios = <&expander0 15 GPIO_ACTIVE_HIGH>; - states = <1800000 0x1 - 3300000 0x0>; - }; - - cp0_reg_sd_vcc: cp0_sd_vcc@0 { - compatible = "regulator-fixed"; - regulator-name = "cp0_sd_vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&expander0 14 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - }; - - cp0_sfp_eth0: sfp-eth@0 { - compatible = "sff,sfp"; - i2c-bus = <&cp0_sfpp0_i2c>; - los-gpio = <&cp0_module_expander1 11 GPIO_ACTIVE_HIGH>; - mod-def0-gpio = <&cp0_module_expander1 10 GPIO_ACTIVE_LOW>; - tx-disable-gpio = <&cp0_module_expander1 9 GPIO_ACTIVE_HIGH>; - tx-fault-gpio = <&cp0_module_expander1 8 GPIO_ACTIVE_HIGH>; - /* - * SFP cages are unconnected on early PCBs because of an the I2C - * lanes not being connected. Prevent the port for being - * unusable by disabling the SFP node. - */ - status = "disabled"; - }; -}; - -&uart0 { - status = "okay"; -}; - -/* on-board eMMC - U9 */ -&ap_sdhci0 { - pinctrl-names = "default"; - bus-width = <8>; - vqmmc-supply = <&ap0_reg_sd_vccq>; - status = "okay"; -}; - -&cp0_crypto { - status = "disabled"; -}; - -&cp0_ethernet { - status = "okay"; -}; - -/* SLM-1521-V2, CON9 */ -&cp0_eth0 { - status = "disabled"; - phy-mode = "10gbase-kr"; - /* Generic PHY, providing serdes lanes */ - phys = <&cp0_comphy4 0>; - managed = "in-band-status"; - sfp = <&cp0_sfp_eth0>; -}; - -/* CON56 */ -&cp0_eth1 { - status = "okay"; - phy = <&phy0>; - phy-mode = "rgmii-id"; -}; - -/* CON57 */ -&cp0_eth2 { - status = "okay"; - phy = <&phy1>; - phy-mode = "rgmii-id"; -}; - -&cp0_gpio1 { - status = "okay"; -}; - -&cp0_gpio2 { - status = "okay"; -}; - -&cp0_i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&cp0_i2c0_pins>; - clock-frequency = <100000>; - - /* U36 */ - expander0: pca953x@21 { - compatible = "nxp,pca9555"; - pinctrl-names = "default"; - gpio-controller; - #gpio-cells = <2>; - reg = <0x21>; - status = "okay"; - }; - - /* U42 */ - eeprom0: eeprom@50 { - compatible = "atmel,24c64"; - reg = <0x50>; - pagesize = <0x20>; - }; - - /* U38 */ - eeprom1: eeprom@57 { - compatible = "atmel,24c64"; - reg = <0x57>; - pagesize = <0x20>; - }; -}; - -&cp0_i2c1 { - status = "okay"; - clock-frequency = <100000>; - - /* SLM-1521-V2 - U3 */ - i2c-mux@72 { /* verify address - depends on dpr */ - compatible = "nxp,pca9544"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x72>; - cp0_sfpp0_i2c: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - /* U12 */ - cp0_module_expander1: pca9555@21 { - compatible = "nxp,pca9555"; - pinctrl-names = "default"; - gpio-controller; - #gpio-cells = <2>; - reg = <0x21>; - }; - - }; - }; -}; - -&cp0_mdio { - status = "okay"; - - phy0: ethernet-phy@0 { - reg = <0>; - }; - - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -/* U54 */ -&cp0_nand_controller { - pinctrl-names = "default"; - pinctrl-0 = <&nand_pins &nand_rb>; - - nand@0 { - reg = <0>; - label = "main-storage"; - nand-rb = <0>; - nand-ecc-mode = "hw"; - nand-on-flash-bbt; - nand-ecc-strength = <8>; - nand-ecc-step-size = <512>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "U-Boot"; - reg = <0 0x200000>; - }; - partition@200000 { - label = "Linux"; - reg = <0x200000 0xd00000>; - }; - partition@1000000 { - label = "Filesystem"; - reg = <0x1000000 0x3f000000>; - }; - }; - }; -}; - -/* SLM-1521-V2, CON6 */ -&cp0_pcie0 { - status = "okay"; - num-lanes = <4>; - num-viewport = <8>; - /* Generic PHY, providing serdes lanes */ - phys = <&cp0_comphy0 0 - &cp0_comphy1 0 - &cp0_comphy2 0 - &cp0_comphy3 0>; -}; - -&cp0_sata0 { - status = "okay"; - - /* SLM-1521-V2, CON2 */ - sata-port@1 { - status = "okay"; - /* Generic PHY, providing serdes lanes */ - phys = <&cp0_comphy5 1>; - }; -}; - -/* CON 28 */ -&cp0_sdhci0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&cp0_sdhci_pins - &cp0_sdhci_cd_pins>; - bus-width = <4>; - cd-gpios = <&cp0_gpio2 11 GPIO_ACTIVE_LOW>; - no-1-8-v; - vqmmc-supply = <&cp0_reg_sd_vccq>; - vmmc-supply = <&cp0_reg_sd_vcc>; -}; - -/* U55 */ -&cp0_spi1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&cp0_spi0_pins>; - reg = <0x700680 0x50>; - - spi-flash@0 { - #address-cells = <0x1>; - #size-cells = <0x1>; - compatible = "jedec,spi-nor"; - reg = <0x0>; - /* On-board MUX does not allow higher frequencies */ - spi-max-frequency = <40000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "U-Boot-0"; - reg = <0x0 0x200000>; - }; - - partition@400000 { - label = "Filesystem-0"; - reg = <0x200000 0xe00000>; - }; - }; - }; -}; - -&cp0_syscon0 { - cp0_pinctrl: pinctrl { - compatible = "marvell,cp115-standalone-pinctrl"; - - cp0_i2c0_pins: cp0-i2c-pins-0 { - marvell,pins = "mpp37", "mpp38"; - marvell,function = "i2c0"; - }; - cp0_i2c1_pins: cp0-i2c-pins-1 { - marvell,pins = "mpp35", "mpp36"; - marvell,function = "i2c1"; - }; - cp0_ge1_rgmii_pins: cp0-ge-rgmii-pins-0 { - marvell,pins = "mpp0", "mpp1", "mpp2", - "mpp3", "mpp4", "mpp5", - "mpp6", "mpp7", "mpp8", - "mpp9", "mpp10", "mpp11"; - marvell,function = "ge0"; - }; - cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-1 { - marvell,pins = "mpp44", "mpp45", "mpp46", - "mpp47", "mpp48", "mpp49", - "mpp50", "mpp51", "mpp52", - "mpp53", "mpp54", "mpp55"; - marvell,function = "ge1"; - }; - cp0_sdhci_cd_pins: cp0-sdhci-cd-pins-0 { - marvell,pins = "mpp43"; - marvell,function = "gpio"; - }; - cp0_sdhci_pins: cp0-sdhi-pins-0 { - marvell,pins = "mpp56", "mpp57", "mpp58", - "mpp59", "mpp60", "mpp61"; - marvell,function = "sdio"; - }; - cp0_spi0_pins: cp0-spi-pins-0 { - marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16"; - marvell,function = "spi1"; - }; - nand_pins: nand-pins { - marvell,pins = "mpp15", "mpp16", "mpp17", "mpp18", - "mpp19", "mpp20", "mpp21", "mpp22", - "mpp23", "mpp24", "mpp25", "mpp26", - "mpp27"; - marvell,function = "dev"; - }; - nand_rb: nand-rb { - marvell,pins = "mpp13"; - marvell,function = "nf"; - }; - }; -}; - -&cp0_usb3_0 { - status = "okay"; - usb-phy = <&cp0_usb3_0_phy0>; - phy-names = "usb"; -}; - -&cp0_usb3_1 { - status = "okay"; - usb-phy = <&cp0_usb3_0_phy1>; - phy-names = "usb"; -}; diff --git a/sys/gnu/dts/arm64/marvell/cn9130.dtsi b/sys/gnu/dts/arm64/marvell/cn9130.dtsi deleted file mode 100644 index a2b7e5ec979..00000000000 --- a/sys/gnu/dts/arm64/marvell/cn9130.dtsi +++ /dev/null @@ -1,37 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2019 Marvell International Ltd. - * - * Device tree for the CN9130 SoC. - */ - -#include "armada-ap807-quad.dtsi" - -/ { - model = "Marvell Armada CN9130 SoC"; - compatible = "marvell,cn9130", "marvell,armada-ap807-quad", - "marvell,armada-ap807"; -}; - -/* - * Instantiate the internal CP115 - */ - -#define CP11X_NAME cp0 -#define CP11X_BASE f2000000 -#define CP11X_PCIEx_MEM_BASE(iface) ((iface == 0) ? 0xc0000000 : \ - 0xe0000000 + ((iface - 1) * 0x1000000)) -#define CP11X_PCIEx_MEM_SIZE(iface) ((iface == 0) ? 0x1ff00000 : 0xf00000) -#define CP11X_PCIE0_BASE f2600000 -#define CP11X_PCIE1_BASE f2620000 -#define CP11X_PCIE2_BASE f2640000 - -#include "armada-cp115.dtsi" - -#undef CP11X_NAME -#undef CP11X_BASE -#undef CP11X_PCIEx_MEM_BASE -#undef CP11X_PCIEx_MEM_SIZE -#undef CP11X_PCIE0_BASE -#undef CP11X_PCIE1_BASE -#undef CP11X_PCIE2_BASE diff --git a/sys/gnu/dts/arm64/marvell/cn9131-db.dts b/sys/gnu/dts/arm64/marvell/cn9131-db.dts deleted file mode 100644 index 3c975f98b2a..00000000000 --- a/sys/gnu/dts/arm64/marvell/cn9131-db.dts +++ /dev/null @@ -1,202 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2019 Marvell International Ltd. - * - * Device tree for the CN9131-DB board. - */ - -#include "cn9130-db.dts" - -/ { - model = "Marvell Armada CN9131-DB"; - compatible = "marvell,cn9131", "marvell,cn9130", - "marvell,armada-ap807-quad", "marvell,armada-ap807"; - - aliases { - gpio3 = &cp1_gpio1; - gpio4 = &cp1_gpio2; - ethernet3 = &cp1_eth0; - ethernet4 = &cp1_eth1; - }; - - cp1_reg_usb3_vbus0: cp1_usb3_vbus@0 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&cp1_xhci0_vbus_pins>; - regulator-name = "cp1-xhci0-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&cp1_gpio1 3 GPIO_ACTIVE_HIGH>; - }; - - cp1_usb3_0_phy0: cp1_usb3_phy0 { - compatible = "usb-nop-xceiv"; - vcc-supply = <&cp1_reg_usb3_vbus0>; - }; - - cp1_sfp_eth1: sfp-eth1 { - compatible = "sff,sfp"; - i2c-bus = <&cp1_i2c0>; - los-gpio = <&cp1_gpio1 11 GPIO_ACTIVE_HIGH>; - mod-def0-gpio = <&cp1_gpio1 10 GPIO_ACTIVE_LOW>; - tx-disable-gpio = <&cp1_gpio1 9 GPIO_ACTIVE_HIGH>; - tx-fault-gpio = <&cp1_gpio1 8 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&cp1_sfp_pins>; - /* - * SFP cages are unconnected on early PCBs because of an the I2C - * lanes not being connected. Prevent the port for being - * unusable by disabling the SFP node. - */ - status = "disabled"; - }; -}; - -/* - * Instantiate the first slave CP115 - */ - -#define CP11X_NAME cp1 -#define CP11X_BASE f4000000 -#define CP11X_PCIEx_MEM_BASE(iface) (0xe2000000 + (iface * 0x1000000)) -#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000 -#define CP11X_PCIE0_BASE f4600000 -#define CP11X_PCIE1_BASE f4620000 -#define CP11X_PCIE2_BASE f4640000 - -#include "armada-cp115.dtsi" - -#undef CP11X_NAME -#undef CP11X_BASE -#undef CP11X_PCIEx_MEM_BASE -#undef CP11X_PCIEx_MEM_SIZE -#undef CP11X_PCIE0_BASE -#undef CP11X_PCIE1_BASE -#undef CP11X_PCIE2_BASE - -&cp1_crypto { - status = "disabled"; -}; - -&cp1_ethernet { - status = "okay"; -}; - -/* CON50 */ -&cp1_eth0 { - status = "disabled"; - phy-mode = "10gbase-kr"; - /* Generic PHY, providing serdes lanes */ - phys = <&cp1_comphy4 0>; - managed = "in-band-status"; - sfp = <&cp1_sfp_eth1>; -}; - -&cp1_gpio1 { - status = "okay"; -}; - -&cp1_gpio2 { - status = "okay"; -}; - -&cp1_i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&cp1_i2c0_pins>; - clock-frequency = <100000>; -}; - -/* CON40 */ -&cp1_pcie0 { - pinctrl-names = "default"; - pinctrl-0 = <&cp1_pcie_reset_pins>; - num-lanes = <2>; - num-viewport = <8>; - marvell,reset-gpio = <&cp1_gpio1 0 GPIO_ACTIVE_HIGH>; - status = "okay"; - /* Generic PHY, providing serdes lanes */ - phys = <&cp1_comphy0 0 - &cp1_comphy1 0>; -}; - -&cp1_sata0 { - status = "okay"; - - /* CON32 */ - sata-port@1 { - /* Generic PHY, providing serdes lanes */ - phys = <&cp1_comphy5 1>; - }; -}; - -/* U24 */ -&cp1_spi1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&cp1_spi0_pins>; - reg = <0x700680 0x50>; - - spi-flash@0 { - #address-cells = <0x1>; - #size-cells = <0x1>; - compatible = "jedec,spi-nor"; - reg = <0x0>; - /* On-board MUX does not allow higher frequencies */ - spi-max-frequency = <40000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "U-Boot-1"; - reg = <0x0 0x200000>; - }; - - partition@400000 { - label = "Filesystem-1"; - reg = <0x200000 0xe00000>; - }; - }; - }; - -}; - -&cp1_syscon0 { - cp1_pinctrl: pinctrl { - compatible = "marvell,cp115-standalone-pinctrl"; - - cp1_i2c0_pins: cp1-i2c-pins-0 { - marvell,pins = "mpp37", "mpp38"; - marvell,function = "i2c0"; - }; - cp1_spi0_pins: cp1-spi-pins-0 { - marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16"; - marvell,function = "spi1"; - }; - cp1_xhci0_vbus_pins: cp1-xhci0-vbus-pins { - marvell,pins = "mpp3"; - marvell,function = "gpio"; - }; - cp1_sfp_pins: sfp-pins { - marvell,pins = "mpp8", "mpp9", "mpp10", "mpp11"; - marvell,function = "gpio"; - }; - cp1_pcie_reset_pins: cp1-pcie-reset-pins { - marvell,pins = "mpp0"; - marvell,function = "gpio"; - }; - }; -}; - -/* CON58 */ -&cp1_usb3_1 { - status = "okay"; - usb-phy = <&cp1_usb3_0_phy0>; - /* Generic PHY, providing serdes lanes */ - phys = <&cp1_comphy3 1>; - phy-names = "usb"; -}; diff --git a/sys/gnu/dts/arm64/marvell/cn9132-db.dts b/sys/gnu/dts/arm64/marvell/cn9132-db.dts deleted file mode 100644 index 4ef0df3097c..00000000000 --- a/sys/gnu/dts/arm64/marvell/cn9132-db.dts +++ /dev/null @@ -1,221 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2019 Marvell International Ltd. - * - * Device tree for the CN9132-DB board. - */ - -#include "cn9131-db.dts" - -/ { - model = "Marvell Armada CN9132-DB"; - compatible = "marvell,cn9132", "marvell,cn9131", "marvell,cn9130", - "marvell,armada-ap807-quad", "marvell,armada-ap807"; - - aliases { - gpio5 = &cp2_gpio1; - gpio6 = &cp2_gpio2; - ethernet5 = &cp2_eth0; - }; - - cp2_reg_usb3_vbus0: cp2_usb3_vbus@0 { - compatible = "regulator-fixed"; - regulator-name = "cp2-xhci0-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&cp2_gpio1 2 GPIO_ACTIVE_HIGH>; - }; - - cp2_usb3_0_phy0: cp2_usb3_phy0 { - compatible = "usb-nop-xceiv"; - vcc-supply = <&cp2_reg_usb3_vbus0>; - }; - - cp2_reg_usb3_vbus1: cp2_usb3_vbus@1 { - compatible = "regulator-fixed"; - regulator-name = "cp2-xhci1-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&cp2_gpio1 3 GPIO_ACTIVE_HIGH>; - }; - - cp2_usb3_0_phy1: cp2_usb3_phy1 { - compatible = "usb-nop-xceiv"; - vcc-supply = <&cp2_reg_usb3_vbus1>; - }; - - cp2_reg_sd_vccq: cp2_sd_vccq@0 { - compatible = "regulator-gpio"; - regulator-name = "cp2_sd_vcc"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - gpios = <&cp2_gpio2 17 GPIO_ACTIVE_HIGH>; - states = <1800000 0x1 3300000 0x0>; - }; - - cp2_sfp_eth0: sfp-eth0 { - compatible = "sff,sfp"; - i2c-bus = <&cp2_sfpp0_i2c>; - los-gpio = <&cp2_module_expander1 11 GPIO_ACTIVE_HIGH>; - mod-def0-gpio = <&cp2_module_expander1 10 GPIO_ACTIVE_LOW>; - tx-disable-gpio = <&cp2_module_expander1 9 GPIO_ACTIVE_HIGH>; - tx-fault-gpio = <&cp2_module_expander1 8 GPIO_ACTIVE_HIGH>; - /* - * SFP cages are unconnected on early PCBs because of an the I2C - * lanes not being connected. Prevent the port for being - * unusable by disabling the SFP node. - */ - status = "disabled"; - }; -}; - -/* - * Instantiate the second slave CP115 - */ - -#define CP11X_NAME cp2 -#define CP11X_BASE f6000000 -#define CP11X_PCIEx_MEM_BASE(iface) (0xe5000000 + (iface * 0x1000000)) -#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000 -#define CP11X_PCIE0_BASE f6600000 -#define CP11X_PCIE1_BASE f6620000 -#define CP11X_PCIE2_BASE f6640000 - -#include "armada-cp115.dtsi" - -#undef CP11X_NAME -#undef CP11X_BASE -#undef CP11X_PCIEx_MEM_BASE -#undef CP11X_PCIEx_MEM_SIZE -#undef CP11X_PCIE0_BASE -#undef CP11X_PCIE1_BASE -#undef CP11X_PCIE2_BASE - -&cp2_crypto { - status = "disabled"; -}; - -&cp2_ethernet { - status = "okay"; -}; - -/* SLM-1521-V2, CON9 */ -&cp2_eth0 { - status = "disabled"; - phy-mode = "10gbase-kr"; - /* Generic PHY, providing serdes lanes */ - phys = <&cp2_comphy4 0>; - managed = "in-band-status"; - sfp = <&cp2_sfp_eth0>; -}; - -&cp2_gpio1 { - status = "okay"; -}; - -&cp2_gpio2 { - status = "okay"; -}; - -&cp2_i2c0 { - clock-frequency = <100000>; - - /* SLM-1521-V2 - U3 */ - i2c-mux@72 { - compatible = "nxp,pca9544"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x72>; - cp2_sfpp0_i2c: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - /* U12 */ - cp2_module_expander1: pca9555@21 { - compatible = "nxp,pca9555"; - pinctrl-names = "default"; - gpio-controller; - #gpio-cells = <2>; - reg = <0x21>; - }; - }; - }; -}; - -/* SLM-1521-V2, CON6 */ -&cp2_pcie0 { - status = "okay"; - num-lanes = <2>; - num-viewport = <8>; - /* Generic PHY, providing serdes lanes */ - phys = <&cp2_comphy0 0 - &cp2_comphy1 0>; -}; - -/* SLM-1521-V2, CON8 */ -&cp2_pcie2 { - status = "okay"; - num-lanes = <1>; - num-viewport = <8>; - /* Generic PHY, providing serdes lanes */ - phys = <&cp2_comphy5 2>; -}; - -&cp2_sata0 { - status = "okay"; - - /* SLM-1521-V2, CON4 */ - sata-port@0 { - /* Generic PHY, providing serdes lanes */ - phys = <&cp2_comphy2 0>; - }; -}; - -/* CON 2 on SLM-1683 - microSD */ -&cp2_sdhci0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&cp2_sdhci_pins>; - bus-width = <4>; - cd-gpios = <&cp2_gpio2 23 GPIO_ACTIVE_LOW>; - vqmmc-supply = <&cp2_reg_sd_vccq>; -}; - -&cp2_syscon0 { - cp2_pinctrl: pinctrl { - compatible = "marvell,cp115-standalone-pinctrl"; - - cp2_i2c0_pins: cp2-i2c-pins-0 { - marvell,pins = "mpp37", "mpp38"; - marvell,function = "i2c0"; - }; - cp2_sdhci_pins: cp2-sdhi-pins-0 { - marvell,pins = "mpp56", "mpp57", "mpp58", - "mpp59", "mpp60", "mpp61"; - marvell,function = "sdio"; - }; - }; -}; - -&cp2_usb3_0 { - status = "okay"; - usb-phy = <&cp2_usb3_0_phy0>; - phy-names = "usb"; -}; - -/* SLM-1521-V2, CON11 */ -&cp2_usb3_1 { - status = "okay"; - usb-phy = <&cp2_usb3_0_phy1>; - phy-names = "usb"; - /* Generic PHY, providing serdes lanes */ - phys = <&cp2_comphy3 1>; -}; diff --git a/sys/gnu/dts/arm64/mediatek/mt2712-evb.dts b/sys/gnu/dts/arm64/mediatek/mt2712-evb.dts deleted file mode 100644 index 2b91daf5c1a..00000000000 --- a/sys/gnu/dts/arm64/mediatek/mt2712-evb.dts +++ /dev/null @@ -1,161 +0,0 @@ -/* - * Copyright (c) 2017 MediaTek Inc. - * Author: YT Shen - * - * SPDX-License-Identifier: (GPL-2.0 OR MIT) - */ - -/dts-v1/; -#include -#include "mt2712e.dtsi" - -/ { - model = "MediaTek MT2712 evaluation board"; - compatible = "mediatek,mt2712-evb", "mediatek,mt2712"; - - aliases { - serial0 = &uart0; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0 0x40000000 0 0x80000000>; - }; - - chosen { - stdout-path = "serial0:921600n8"; - }; - - cpus_fixed_vproc0: fixedregulator@0 { - compatible = "regulator-fixed"; - regulator-name = "vproc_buck0"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - }; - - cpus_fixed_vproc1: fixedregulator@1 { - compatible = "regulator-fixed"; - regulator-name = "vproc_buck1"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - }; - - extcon_usb: extcon_iddig { - compatible = "linux,extcon-usb-gpio"; - id-gpio = <&pio 12 GPIO_ACTIVE_HIGH>; - }; - - extcon_usb1: extcon_iddig1 { - compatible = "linux,extcon-usb-gpio"; - id-gpio = <&pio 14 GPIO_ACTIVE_HIGH>; - }; - - usb_p0_vbus: regulator@2 { - compatible = "regulator-fixed"; - regulator-name = "p0_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&pio 13 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - usb_p1_vbus: regulator@3 { - compatible = "regulator-fixed"; - regulator-name = "p1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&pio 15 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - usb_p2_vbus: regulator@4 { - compatible = "regulator-fixed"; - regulator-name = "p2_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&pio 16 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - usb_p3_vbus: regulator@5 { - compatible = "regulator-fixed"; - regulator-name = "p3_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&pio 17 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - }; - -}; - -&auxadc { - status = "okay"; -}; - -&cpu0 { - proc-supply = <&cpus_fixed_vproc0>; -}; - -&cpu1 { - proc-supply = <&cpus_fixed_vproc0>; -}; - -&cpu2 { - proc-supply = <&cpus_fixed_vproc1>; -}; - -&pio { - usb0_id_pins_float: usb0_iddig { - pins_iddig { - pinmux = ; - bias-pull-up; - }; - }; - - usb1_id_pins_float: usb1_iddig { - pins_iddig { - pinmux = ; - bias-pull-up; - }; - }; -}; - -&ssusb { - vbus-supply = <&usb_p0_vbus>; - extcon = <&extcon_usb>; - dr_mode = "otg"; - wakeup-source; - mediatek,u3p-dis-msk = <0x1>; - //enable-manual-drd; - //maximum-speed = "full-speed"; - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_pins_float>; - status = "okay"; -}; - -&ssusb1 { - vbus-supply = <&usb_p1_vbus>; - extcon = <&extcon_usb1>; - dr_mode = "otg"; - //mediatek,u3p-dis-msk = <0x1>; - enable-manual-drd; - wakeup-source; - //maximum-speed = "full-speed"; - pinctrl-names = "default"; - pinctrl-0 = <&usb1_id_pins_float>; - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&usb_host0 { - vbus-supply = <&usb_p2_vbus>; - status = "okay"; -}; - -&usb_host1 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/mediatek/mt2712-pinfunc.h b/sys/gnu/dts/arm64/mediatek/mt2712-pinfunc.h deleted file mode 100644 index 385c455a7c9..00000000000 --- a/sys/gnu/dts/arm64/mediatek/mt2712-pinfunc.h +++ /dev/null @@ -1,1123 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2018 MediaTek Inc. - * Author: Zhiyong Tao - * - */ -#ifndef __DTS_MT2712_PINFUNC_H -#define __DTS_MT2712_PINFUNC_H - -#include - -#define MT2712_PIN_0_EINT0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) -#define MT2712_PIN_0_EINT0__FUNC_EINT0 (MTK_PIN_NO(0) | 1) -#define MT2712_PIN_0_EINT0__FUNC_MBIST_DIAG_SCANOUT (MTK_PIN_NO(0) | 2) -#define MT2712_PIN_0_EINT0__FUNC_DSIA_TE (MTK_PIN_NO(0) | 3) -#define MT2712_PIN_0_EINT0__FUNC_DSIC_TE (MTK_PIN_NO(0) | 4) -#define MT2712_PIN_0_EINT0__FUNC_DIN_D3 (MTK_PIN_NO(0) | 5) -#define MT2712_PIN_0_EINT0__FUNC_PURE_HW_PROTECT (MTK_PIN_NO(0) | 6) - -#define MT2712_PIN_1_EINT1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) -#define MT2712_PIN_1_EINT1__FUNC_EINT1 (MTK_PIN_NO(1) | 1) -#define MT2712_PIN_1_EINT1__FUNC_IR_IN (MTK_PIN_NO(1) | 2) -#define MT2712_PIN_1_EINT1__FUNC_DSIB_TE (MTK_PIN_NO(1) | 3) -#define MT2712_PIN_1_EINT1__FUNC_DSID_TE (MTK_PIN_NO(1) | 4) -#define MT2712_PIN_1_EINT1__FUNC_DIN_D4 (MTK_PIN_NO(1) | 5) - -#define MT2712_PIN_2_EINT2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) -#define MT2712_PIN_2_EINT2__FUNC_EINT2 (MTK_PIN_NO(2) | 1) -#define MT2712_PIN_2_EINT2__FUNC_IR_IN (MTK_PIN_NO(2) | 2) -#define MT2712_PIN_2_EINT2__FUNC_LCM_RST1 (MTK_PIN_NO(2) | 3) -#define MT2712_PIN_2_EINT2__FUNC_DIN_D5 (MTK_PIN_NO(2) | 5) - -#define MT2712_PIN_3_EINT3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) -#define MT2712_PIN_3_EINT3__FUNC_EINT3 (MTK_PIN_NO(3) | 1) -#define MT2712_PIN_3_EINT3__FUNC_IR_IN (MTK_PIN_NO(3) | 2) -#define MT2712_PIN_3_EINT3__FUNC_LCM_RST0 (MTK_PIN_NO(3) | 3) -#define MT2712_PIN_3_EINT3__FUNC_DIN_D6 (MTK_PIN_NO(3) | 5) - -#define MT2712_PIN_4_PWM0__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) -#define MT2712_PIN_4_PWM0__FUNC_PWM0 (MTK_PIN_NO(4) | 1) -#define MT2712_PIN_4_PWM0__FUNC_DISP0_PWM (MTK_PIN_NO(4) | 2) -#define MT2712_PIN_4_PWM0__FUNC_DISP1_PWM (MTK_PIN_NO(4) | 3) -#define MT2712_PIN_4_PWM0__FUNC_DIN_CLK (MTK_PIN_NO(4) | 5) - -#define MT2712_PIN_5_PWM1__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) -#define MT2712_PIN_5_PWM1__FUNC_PWM1 (MTK_PIN_NO(5) | 1) -#define MT2712_PIN_5_PWM1__FUNC_DISP1_PWM (MTK_PIN_NO(5) | 2) -#define MT2712_PIN_5_PWM1__FUNC_DISP0_PWM (MTK_PIN_NO(5) | 3) -#define MT2712_PIN_5_PWM1__FUNC_DIN_VSYNC (MTK_PIN_NO(5) | 5) - -#define MT2712_PIN_6_PWM2__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) -#define MT2712_PIN_6_PWM2__FUNC_PWM2 (MTK_PIN_NO(6) | 1) -#define MT2712_PIN_6_PWM2__FUNC_DISP0_PWM (MTK_PIN_NO(6) | 2) -#define MT2712_PIN_6_PWM2__FUNC_DISP1_PWM (MTK_PIN_NO(6) | 3) -#define MT2712_PIN_6_PWM2__FUNC_DISP2_PWM (MTK_PIN_NO(6) | 4) -#define MT2712_PIN_6_PWM2__FUNC_DIN_HSYNC (MTK_PIN_NO(6) | 5) - -#define MT2712_PIN_7_PWM3__FUNC_GPIO7 (MTK_PIN_NO(7) | 0) -#define MT2712_PIN_7_PWM3__FUNC_PWM3 (MTK_PIN_NO(7) | 1) -#define MT2712_PIN_7_PWM3__FUNC_DISP1_PWM (MTK_PIN_NO(7) | 2) -#define MT2712_PIN_7_PWM3__FUNC_DISP0_PWM (MTK_PIN_NO(7) | 3) -#define MT2712_PIN_7_PWM3__FUNC_LCM_RST2 (MTK_PIN_NO(7) | 4) -#define MT2712_PIN_7_PWM3__FUNC_DIN_D0 (MTK_PIN_NO(7) | 5) - -#define MT2712_PIN_8_PWM4__FUNC_GPIO8 (MTK_PIN_NO(8) | 0) -#define MT2712_PIN_8_PWM4__FUNC_PWM4 (MTK_PIN_NO(8) | 1) -#define MT2712_PIN_8_PWM4__FUNC_DISP0_PWM (MTK_PIN_NO(8) | 2) -#define MT2712_PIN_8_PWM4__FUNC_DISP1_PWM (MTK_PIN_NO(8) | 3) -#define MT2712_PIN_8_PWM4__FUNC_DSIA_TE (MTK_PIN_NO(8) | 4) -#define MT2712_PIN_8_PWM4__FUNC_DIN_D1 (MTK_PIN_NO(8) | 5) - -#define MT2712_PIN_9_PWM5__FUNC_GPIO9 (MTK_PIN_NO(9) | 0) -#define MT2712_PIN_9_PWM5__FUNC_PWM5 (MTK_PIN_NO(9) | 1) -#define MT2712_PIN_9_PWM5__FUNC_DISP1_PWM (MTK_PIN_NO(9) | 2) -#define MT2712_PIN_9_PWM5__FUNC_DISP0_PWM (MTK_PIN_NO(9) | 3) -#define MT2712_PIN_9_PWM5__FUNC_DSIB_TE (MTK_PIN_NO(9) | 4) -#define MT2712_PIN_9_PWM5__FUNC_DIN_D2 (MTK_PIN_NO(9) | 5) - -#define MT2712_PIN_10_PWM6__FUNC_GPIO10 (MTK_PIN_NO(10) | 0) -#define MT2712_PIN_10_PWM6__FUNC_PWM6 (MTK_PIN_NO(10) | 1) -#define MT2712_PIN_10_PWM6__FUNC_DISP0_PWM (MTK_PIN_NO(10) | 2) -#define MT2712_PIN_10_PWM6__FUNC_DISP1_PWM (MTK_PIN_NO(10) | 3) -#define MT2712_PIN_10_PWM6__FUNC_LCM_RST0 (MTK_PIN_NO(10) | 4) - -#define MT2712_PIN_11_PWM7__FUNC_GPIO11 (MTK_PIN_NO(11) | 0) -#define MT2712_PIN_11_PWM7__FUNC_PWM7 (MTK_PIN_NO(11) | 1) -#define MT2712_PIN_11_PWM7__FUNC_DISP1_PWM (MTK_PIN_NO(11) | 2) -#define MT2712_PIN_11_PWM7__FUNC_DISP0_PWM (MTK_PIN_NO(11) | 3) -#define MT2712_PIN_11_PWM7__FUNC_LCM_RST1 (MTK_PIN_NO(11) | 4) - -#define MT2712_PIN_12_IDDIG_P0__FUNC_GPIO12 (MTK_PIN_NO(12) | 0) -#define MT2712_PIN_12_IDDIG_P0__FUNC_IDDIG_A (MTK_PIN_NO(12) | 1) -#define MT2712_PIN_12_IDDIG_P0__FUNC_DIN_D7 (MTK_PIN_NO(12) | 5) - -#define MT2712_PIN_13_DRV_VBUS_P0__FUNC_GPIO13 (MTK_PIN_NO(13) | 0) -#define MT2712_PIN_13_DRV_VBUS_P0__FUNC_DRV_VBUS_A (MTK_PIN_NO(13) | 1) - -#define MT2712_PIN_14_IDDIG_P1__FUNC_GPIO14 (MTK_PIN_NO(14) | 0) -#define MT2712_PIN_14_IDDIG_P1__FUNC_IDDIG_B (MTK_PIN_NO(14) | 1) - -#define MT2712_PIN_15_DRV_VBUS_P1__FUNC_GPIO15 (MTK_PIN_NO(15) | 0) -#define MT2712_PIN_15_DRV_VBUS_P1__FUNC_DRV_VBUS_B (MTK_PIN_NO(15) | 1) - -#define MT2712_PIN_16_DRV_VBUS_P2__FUNC_GPIO16 (MTK_PIN_NO(16) | 0) -#define MT2712_PIN_16_DRV_VBUS_P2__FUNC_DRV_VBUS_C (MTK_PIN_NO(16) | 1) - -#define MT2712_PIN_17_DRV_VBUS_P3__FUNC_GPIO17 (MTK_PIN_NO(17) | 0) -#define MT2712_PIN_17_DRV_VBUS_P3__FUNC_DRV_VBUS_D (MTK_PIN_NO(17) | 1) - -#define MT2712_PIN_18_KPROW0__FUNC_GPIO18 (MTK_PIN_NO(18) | 0) -#define MT2712_PIN_18_KPROW0__FUNC_KROW0 (MTK_PIN_NO(18) | 1) - -#define MT2712_PIN_19_KPCOL0__FUNC_GPIO19 (MTK_PIN_NO(19) | 0) -#define MT2712_PIN_19_KPCOL0__FUNC_KCOL0 (MTK_PIN_NO(19) | 1) - -#define MT2712_PIN_20_KPROW1__FUNC_GPIO20 (MTK_PIN_NO(20) | 0) -#define MT2712_PIN_20_KPROW1__FUNC_KROW1 (MTK_PIN_NO(20) | 1) - -#define MT2712_PIN_21_KPCOL1__FUNC_GPIO21 (MTK_PIN_NO(21) | 0) -#define MT2712_PIN_21_KPCOL1__FUNC_KCOL1 (MTK_PIN_NO(21) | 1) - -#define MT2712_PIN_22_KPROW2__FUNC_GPIO22 (MTK_PIN_NO(22) | 0) -#define MT2712_PIN_22_KPROW2__FUNC_KROW2 (MTK_PIN_NO(22) | 1) -#define MT2712_PIN_22_KPROW2__FUNC_DISP1_PWM (MTK_PIN_NO(22) | 2) - -#define MT2712_PIN_23_KPCOL2__FUNC_GPIO23 (MTK_PIN_NO(23) | 0) -#define MT2712_PIN_23_KPCOL2__FUNC_KCOL2 (MTK_PIN_NO(23) | 1) -#define MT2712_PIN_23_KPCOL2__FUNC_DISP0_PWM (MTK_PIN_NO(23) | 2) - -#define MT2712_PIN_24_CMMCLK__FUNC_GPIO24 (MTK_PIN_NO(24) | 0) -#define MT2712_PIN_24_CMMCLK__FUNC_CMMCLK (MTK_PIN_NO(24) | 1) -#define MT2712_PIN_24_CMMCLK__FUNC_DBG_MON_A_1_ (MTK_PIN_NO(24) | 7) - -#define MT2712_PIN_25_CM2MCLK__FUNC_GPIO25 (MTK_PIN_NO(25) | 0) -#define MT2712_PIN_25_CM2MCLK__FUNC_CM2MCLK (MTK_PIN_NO(25) | 1) -#define MT2712_PIN_25_CM2MCLK__FUNC_DBG_MON_A_2_ (MTK_PIN_NO(25) | 7) - -#define MT2712_PIN_26_PCM_TX__FUNC_GPIO26 (MTK_PIN_NO(26) | 0) -#define MT2712_PIN_26_PCM_TX__FUNC_PCM1_DO (MTK_PIN_NO(26) | 1) -#define MT2712_PIN_26_PCM_TX__FUNC_MRG_TX (MTK_PIN_NO(26) | 2) -#define MT2712_PIN_26_PCM_TX__FUNC_DAI_TX (MTK_PIN_NO(26) | 3) -#define MT2712_PIN_26_PCM_TX__FUNC_MRG_RX (MTK_PIN_NO(26) | 4) -#define MT2712_PIN_26_PCM_TX__FUNC_DAI_RX (MTK_PIN_NO(26) | 5) -#define MT2712_PIN_26_PCM_TX__FUNC_PCM1_DI (MTK_PIN_NO(26) | 6) -#define MT2712_PIN_26_PCM_TX__FUNC_DBG_MON_A_3_ (MTK_PIN_NO(26) | 7) - -#define MT2712_PIN_27_PCM_CLK__FUNC_GPIO27 (MTK_PIN_NO(27) | 0) -#define MT2712_PIN_27_PCM_CLK__FUNC_PCM1_CLK (MTK_PIN_NO(27) | 1) -#define MT2712_PIN_27_PCM_CLK__FUNC_MRG_CLK (MTK_PIN_NO(27) | 2) -#define MT2712_PIN_27_PCM_CLK__FUNC_DAI_CLK (MTK_PIN_NO(27) | 3) -#define MT2712_PIN_27_PCM_CLK__FUNC_DBG_MON_A_4_ (MTK_PIN_NO(27) | 7) - -#define MT2712_PIN_28_PCM_RX__FUNC_GPIO28 (MTK_PIN_NO(28) | 0) -#define MT2712_PIN_28_PCM_RX__FUNC_PCM1_DI (MTK_PIN_NO(28) | 1) -#define MT2712_PIN_28_PCM_RX__FUNC_MRG_RX (MTK_PIN_NO(28) | 2) -#define MT2712_PIN_28_PCM_RX__FUNC_DAI_RX (MTK_PIN_NO(28) | 3) -#define MT2712_PIN_28_PCM_RX__FUNC_MRG_TX (MTK_PIN_NO(28) | 4) -#define MT2712_PIN_28_PCM_RX__FUNC_DAI_TX (MTK_PIN_NO(28) | 5) -#define MT2712_PIN_28_PCM_RX__FUNC_PCM1_DO (MTK_PIN_NO(28) | 6) -#define MT2712_PIN_28_PCM_RX__FUNC_DBG_MON_A_5_ (MTK_PIN_NO(28) | 7) - -#define MT2712_PIN_29_PCM_SYNC__FUNC_GPIO29 (MTK_PIN_NO(29) | 0) -#define MT2712_PIN_29_PCM_SYNC__FUNC_PCM1_SYNC (MTK_PIN_NO(29) | 1) -#define MT2712_PIN_29_PCM_SYNC__FUNC_MRG_SYNC (MTK_PIN_NO(29) | 2) -#define MT2712_PIN_29_PCM_SYNC__FUNC_DAI_SYNC (MTK_PIN_NO(29) | 3) -#define MT2712_PIN_29_PCM_SYNC__FUNC_DBG_MON_A_6_ (MTK_PIN_NO(29) | 7) - -#define MT2712_PIN_30_NCEB0__FUNC_GPIO30 (MTK_PIN_NO(30) | 0) -#define MT2712_PIN_30_NCEB0__FUNC_NCEB0 (MTK_PIN_NO(30) | 1) -#define MT2712_PIN_30_NCEB0__FUNC_USB0_FT_SDA (MTK_PIN_NO(30) | 2) -#define MT2712_PIN_30_NCEB0__FUNC_DBG_MON_A_7_ (MTK_PIN_NO(30) | 7) - -#define MT2712_PIN_31_NCEB1__FUNC_GPIO31 (MTK_PIN_NO(31) | 0) -#define MT2712_PIN_31_NCEB1__FUNC_NCEB1 (MTK_PIN_NO(31) | 1) -#define MT2712_PIN_31_NCEB1__FUNC_USB1_FT_SCL (MTK_PIN_NO(31) | 2) -#define MT2712_PIN_31_NCEB1__FUNC_DBG_MON_A_8_ (MTK_PIN_NO(31) | 7) - -#define MT2712_PIN_32_NF_DQS__FUNC_GPIO32 (MTK_PIN_NO(32) | 0) -#define MT2712_PIN_32_NF_DQS__FUNC_NF_DQS (MTK_PIN_NO(32) | 1) -#define MT2712_PIN_32_NF_DQS__FUNC_USB1_FT_SDA (MTK_PIN_NO(32) | 2) -#define MT2712_PIN_32_NF_DQS__FUNC_DBG_MON_A_9_ (MTK_PIN_NO(32) | 7) - -#define MT2712_PIN_33_NWEB__FUNC_GPIO33 (MTK_PIN_NO(33) | 0) -#define MT2712_PIN_33_NWEB__FUNC_NWEB (MTK_PIN_NO(33) | 1) -#define MT2712_PIN_33_NWEB__FUNC_USB2_FT_SCL (MTK_PIN_NO(33) | 2) -#define MT2712_PIN_33_NWEB__FUNC_DBG_MON_A_10_ (MTK_PIN_NO(33) | 7) - -#define MT2712_PIN_34_NREB__FUNC_GPIO34 (MTK_PIN_NO(34) | 0) -#define MT2712_PIN_34_NREB__FUNC_NREB (MTK_PIN_NO(34) | 1) -#define MT2712_PIN_34_NREB__FUNC_USB2_FT_SDA (MTK_PIN_NO(34) | 2) -#define MT2712_PIN_34_NREB__FUNC_DBG_MON_A_11_ (MTK_PIN_NO(34) | 7) - -#define MT2712_PIN_35_NCLE__FUNC_GPIO35 (MTK_PIN_NO(35) | 0) -#define MT2712_PIN_35_NCLE__FUNC_NCLE (MTK_PIN_NO(35) | 1) -#define MT2712_PIN_35_NCLE__FUNC_USB3_FT_SCL (MTK_PIN_NO(35) | 2) -#define MT2712_PIN_35_NCLE__FUNC_DBG_MON_A_12_ (MTK_PIN_NO(35) | 7) - -#define MT2712_PIN_36_NALE__FUNC_GPIO36 (MTK_PIN_NO(36) | 0) -#define MT2712_PIN_36_NALE__FUNC_NALE (MTK_PIN_NO(36) | 1) -#define MT2712_PIN_36_NALE__FUNC_USB3_FT_SDA (MTK_PIN_NO(36) | 2) -#define MT2712_PIN_36_NALE__FUNC_DBG_MON_A_13_ (MTK_PIN_NO(36) | 7) - -#define MT2712_PIN_37_MSDC0E_CLK__FUNC_GPIO37 (MTK_PIN_NO(37) | 0) -#define MT2712_PIN_37_MSDC0E_CLK__FUNC_MSDC0_CLK (MTK_PIN_NO(37) | 1) -#define MT2712_PIN_37_MSDC0E_CLK__FUNC_USB0_FT_SCL (MTK_PIN_NO(37) | 2) -#define MT2712_PIN_37_MSDC0E_CLK__FUNC_DBG_MON_A_0_ (MTK_PIN_NO(37) | 7) - -#define MT2712_PIN_38_MSDC0E_DAT7__FUNC_GPIO38 (MTK_PIN_NO(38) | 0) -#define MT2712_PIN_38_MSDC0E_DAT7__FUNC_MSDC0_DAT7 (MTK_PIN_NO(38) | 1) -#define MT2712_PIN_38_MSDC0E_DAT7__FUNC_NAND_ND7 (MTK_PIN_NO(38) | 2) -#define MT2712_PIN_38_MSDC0E_DAT7__FUNC_DBG_MON_A_14_ (MTK_PIN_NO(38) | 7) - -#define MT2712_PIN_39_MSDC0E_DAT6__FUNC_GPIO39 (MTK_PIN_NO(39) | 0) -#define MT2712_PIN_39_MSDC0E_DAT6__FUNC_MSDC0_DAT6 (MTK_PIN_NO(39) | 1) -#define MT2712_PIN_39_MSDC0E_DAT6__FUNC_NAND_ND6 (MTK_PIN_NO(39) | 2) -#define MT2712_PIN_39_MSDC0E_DAT6__FUNC_DBG_MON_A_15_ (MTK_PIN_NO(39) | 7) - -#define MT2712_PIN_40_MSDC0E_DAT5__FUNC_GPIO40 (MTK_PIN_NO(40) | 0) -#define MT2712_PIN_40_MSDC0E_DAT5__FUNC_MSDC0_DAT5 (MTK_PIN_NO(40) | 1) -#define MT2712_PIN_40_MSDC0E_DAT5__FUNC_NAND_ND5 (MTK_PIN_NO(40) | 2) -#define MT2712_PIN_40_MSDC0E_DAT5__FUNC_DBG_MON_A_16_ (MTK_PIN_NO(40) | 7) - -#define MT2712_PIN_41_MSDC0E_DAT4__FUNC_GPIO41 (MTK_PIN_NO(41) | 0) -#define MT2712_PIN_41_MSDC0E_DAT4__FUNC_MSDC0_DAT4 (MTK_PIN_NO(41) | 1) -#define MT2712_PIN_41_MSDC0E_DAT4__FUNC_NAND_ND4 (MTK_PIN_NO(41) | 2) -#define MT2712_PIN_41_MSDC0E_DAT4__FUNC_DBG_MON_A_17_ (MTK_PIN_NO(41) | 7) - -#define MT2712_PIN_42_MSDC0E_DAT3__FUNC_GPIO42 (MTK_PIN_NO(42) | 0) -#define MT2712_PIN_42_MSDC0E_DAT3__FUNC_MSDC0_DAT3 (MTK_PIN_NO(42) | 1) -#define MT2712_PIN_42_MSDC0E_DAT3__FUNC_NAND_ND3 (MTK_PIN_NO(42) | 2) -#define MT2712_PIN_42_MSDC0E_DAT3__FUNC_DBG_MON_A_18_ (MTK_PIN_NO(42) | 7) - -#define MT2712_PIN_43_MSDC0E_DAT2__FUNC_GPIO43 (MTK_PIN_NO(43) | 0) -#define MT2712_PIN_43_MSDC0E_DAT2__FUNC_MSDC0_DAT2 (MTK_PIN_NO(43) | 1) -#define MT2712_PIN_43_MSDC0E_DAT2__FUNC_NAND_ND2 (MTK_PIN_NO(43) | 2) -#define MT2712_PIN_43_MSDC0E_DAT2__FUNC_DBG_MON_A_19_ (MTK_PIN_NO(43) | 7) - -#define MT2712_PIN_44_MSDC0E_DAT1__FUNC_GPIO44 (MTK_PIN_NO(44) | 0) -#define MT2712_PIN_44_MSDC0E_DAT1__FUNC_MSDC0_DAT1 (MTK_PIN_NO(44) | 1) -#define MT2712_PIN_44_MSDC0E_DAT1__FUNC_NAND_ND1 (MTK_PIN_NO(44) | 2) -#define MT2712_PIN_44_MSDC0E_DAT1__FUNC_DBG_MON_A_20_ (MTK_PIN_NO(44) | 7) - -#define MT2712_PIN_45_MSDC0E_DAT0__FUNC_GPIO45 (MTK_PIN_NO(45) | 0) -#define MT2712_PIN_45_MSDC0E_DAT0__FUNC_MSDC0_DAT0 (MTK_PIN_NO(45) | 1) -#define MT2712_PIN_45_MSDC0E_DAT0__FUNC_NAND_ND0 (MTK_PIN_NO(45) | 2) -#define MT2712_PIN_45_MSDC0E_DAT0__FUNC_DBG_MON_A_21_ (MTK_PIN_NO(45) | 7) - -#define MT2712_PIN_46_MSDC0E_CMD__FUNC_GPIO46 (MTK_PIN_NO(46) | 0) -#define MT2712_PIN_46_MSDC0E_CMD__FUNC_MSDC0_CMD (MTK_PIN_NO(46) | 1) -#define MT2712_PIN_46_MSDC0E_CMD__FUNC_NAND_NRNB (MTK_PIN_NO(46) | 2) -#define MT2712_PIN_46_MSDC0E_CMD__FUNC_DBG_MON_A_22_ (MTK_PIN_NO(46) | 7) - -#define MT2712_PIN_47_MSDC0E_DSL__FUNC_GPIO47 (MTK_PIN_NO(47) | 0) -#define MT2712_PIN_47_MSDC0E_DSL__FUNC_MSDC0_DSL (MTK_PIN_NO(47) | 1) -#define MT2712_PIN_47_MSDC0E_DSL__FUNC_DBG_MON_A_23_ (MTK_PIN_NO(47) | 7) - -#define MT2712_PIN_48_MSDC0E_RSTB__FUNC_GPIO48 (MTK_PIN_NO(48) | 0) -#define MT2712_PIN_48_MSDC0E_RSTB__FUNC_MSDC0_RSTB (MTK_PIN_NO(48) | 1) -#define MT2712_PIN_48_MSDC0E_RSTB__FUNC_DBG_MON_A_24_ (MTK_PIN_NO(48) | 7) - -#define MT2712_PIN_49_MSDC3_DAT3__FUNC_GPIO49 (MTK_PIN_NO(49) | 0) -#define MT2712_PIN_49_MSDC3_DAT3__FUNC_MSDC3_DAT3 (MTK_PIN_NO(49) | 1) -#define MT2712_PIN_49_MSDC3_DAT3__FUNC_DBG_MON_A_25_ (MTK_PIN_NO(49) | 7) - -#define MT2712_PIN_50_MSDC3_DAT2__FUNC_GPIO50 (MTK_PIN_NO(50) | 0) -#define MT2712_PIN_50_MSDC3_DAT2__FUNC_MSDC3_DAT2 (MTK_PIN_NO(50) | 1) -#define MT2712_PIN_50_MSDC3_DAT2__FUNC_DBG_MON_A_26_ (MTK_PIN_NO(50) | 7) - -#define MT2712_PIN_51_MSDC3_DAT1__FUNC_GPIO51 (MTK_PIN_NO(51) | 0) -#define MT2712_PIN_51_MSDC3_DAT1__FUNC_MSDC3_DAT1 (MTK_PIN_NO(51) | 1) -#define MT2712_PIN_51_MSDC3_DAT1__FUNC_DBG_MON_A_27_ (MTK_PIN_NO(51) | 7) - -#define MT2712_PIN_52_MSDC3_DAT0__FUNC_GPIO52 (MTK_PIN_NO(52) | 0) -#define MT2712_PIN_52_MSDC3_DAT0__FUNC_MSDC3_DAT0 (MTK_PIN_NO(52) | 1) -#define MT2712_PIN_52_MSDC3_DAT0__FUNC_DBG_MON_A_28_ (MTK_PIN_NO(52) | 7) - -#define MT2712_PIN_53_MSDC3_CMD__FUNC_GPIO53 (MTK_PIN_NO(53) | 0) -#define MT2712_PIN_53_MSDC3_CMD__FUNC_MSDC3_CMD (MTK_PIN_NO(53) | 1) -#define MT2712_PIN_53_MSDC3_CMD__FUNC_DBG_MON_A_29_ (MTK_PIN_NO(53) | 7) - -#define MT2712_PIN_54_MSDC3_INS__FUNC_GPIO54 (MTK_PIN_NO(54) | 0) -#define MT2712_PIN_54_MSDC3_INS__FUNC_MSDC3_INS (MTK_PIN_NO(54) | 1) -#define MT2712_PIN_54_MSDC3_INS__FUNC_DBG_MON_A_30_ (MTK_PIN_NO(54) | 7) - -#define MT2712_PIN_55_MSDC3_DSL__FUNC_GPIO55 (MTK_PIN_NO(55) | 0) -#define MT2712_PIN_55_MSDC3_DSL__FUNC_MSDC3_DSL (MTK_PIN_NO(55) | 1) -#define MT2712_PIN_55_MSDC3_DSL__FUNC_DBG_MON_A_31_ (MTK_PIN_NO(55) | 7) - -#define MT2712_PIN_56_MSDC3_CLK__FUNC_GPIO56 (MTK_PIN_NO(56) | 0) -#define MT2712_PIN_56_MSDC3_CLK__FUNC_MSDC3_CLK (MTK_PIN_NO(56) | 1) -#define MT2712_PIN_56_MSDC3_CLK__FUNC_DBG_MON_A_32_ (MTK_PIN_NO(56) | 7) - -#define MT2712_PIN_57_NOR_CS__FUNC_GPIO57 (MTK_PIN_NO(57) | 0) -#define MT2712_PIN_57_NOR_CS__FUNC_NOR_CS (MTK_PIN_NO(57) | 1) - -#define MT2712_PIN_58_NOR_CK__FUNC_GPIO58 (MTK_PIN_NO(58) | 0) -#define MT2712_PIN_58_NOR_CK__FUNC_NOR_CK (MTK_PIN_NO(58) | 1) - -#define MT2712_PIN_59_NOR_IO0__FUNC_GPIO59 (MTK_PIN_NO(59) | 0) -#define MT2712_PIN_59_NOR_IO0__FUNC_NOR_IO0 (MTK_PIN_NO(59) | 1) - -#define MT2712_PIN_60_NOR_IO1__FUNC_GPIO60 (MTK_PIN_NO(60) | 0) -#define MT2712_PIN_60_NOR_IO1__FUNC_NOR_IO1 (MTK_PIN_NO(60) | 1) - -#define MT2712_PIN_61_NOR_IO2__FUNC_GPIO61 (MTK_PIN_NO(61) | 0) -#define MT2712_PIN_61_NOR_IO2__FUNC_NOR_IO2 (MTK_PIN_NO(61) | 1) - -#define MT2712_PIN_62_NOR_IO3__FUNC_GPIO62 (MTK_PIN_NO(62) | 0) -#define MT2712_PIN_62_NOR_IO3__FUNC_NOR_IO3 (MTK_PIN_NO(62) | 1) - -#define MT2712_PIN_63_MSDC1_CLK__FUNC_GPIO63 (MTK_PIN_NO(63) | 0) -#define MT2712_PIN_63_MSDC1_CLK__FUNC_MSDC1_CLK (MTK_PIN_NO(63) | 1) -#define MT2712_PIN_63_MSDC1_CLK__FUNC_UDI_TCK (MTK_PIN_NO(63) | 2) - -#define MT2712_PIN_64_MSDC1_DAT3__FUNC_GPIO64 (MTK_PIN_NO(64) | 0) -#define MT2712_PIN_64_MSDC1_DAT3__FUNC_MSDC1_DAT3 (MTK_PIN_NO(64) | 1) -#define MT2712_PIN_64_MSDC1_DAT3__FUNC_UDI_TDI (MTK_PIN_NO(64) | 2) - -#define MT2712_PIN_65_MSDC1_DAT1__FUNC_GPIO65 (MTK_PIN_NO(65) | 0) -#define MT2712_PIN_65_MSDC1_DAT1__FUNC_MSDC1_DAT1 (MTK_PIN_NO(65) | 1) -#define MT2712_PIN_65_MSDC1_DAT1__FUNC_UDI_TMS (MTK_PIN_NO(65) | 2) - -#define MT2712_PIN_66_MSDC1_DAT2__FUNC_GPIO66 (MTK_PIN_NO(66) | 0) -#define MT2712_PIN_66_MSDC1_DAT2__FUNC_MSDC1_DAT2 (MTK_PIN_NO(66) | 1) -#define MT2712_PIN_66_MSDC1_DAT2__FUNC_UDI_TDO (MTK_PIN_NO(66) | 2) - -#define MT2712_PIN_67_MSDC1_PSW__FUNC_GPIO67 (MTK_PIN_NO(67) | 0) -#define MT2712_PIN_67_MSDC1_PSW__FUNC_UDI_NTRST (MTK_PIN_NO(67) | 2) - -#define MT2712_PIN_68_MSDC1_DAT0__FUNC_GPIO68 (MTK_PIN_NO(68) | 0) -#define MT2712_PIN_68_MSDC1_DAT0__FUNC_MSDC1_DAT0 (MTK_PIN_NO(68) | 1) - -#define MT2712_PIN_69_MSDC1_CMD__FUNC_GPIO69 (MTK_PIN_NO(69) | 0) -#define MT2712_PIN_69_MSDC1_CMD__FUNC_MSDC1_CMD (MTK_PIN_NO(69) | 1) - -#define MT2712_PIN_70_MSDC1_INS__FUNC_GPIO70 (MTK_PIN_NO(70) | 0) - -#define MT2712_PIN_71_GBE_TXD3__FUNC_GPIO71 (MTK_PIN_NO(71) | 0) -#define MT2712_PIN_71_GBE_TXD3__FUNC_GBE_TXD3 (MTK_PIN_NO(71) | 1) -#define MT2712_PIN_71_GBE_TXD3__FUNC_DBG_MON_B_0_ (MTK_PIN_NO(71) | 7) - -#define MT2712_PIN_72_GBE_TXD2__FUNC_GPIO72 (MTK_PIN_NO(72) | 0) -#define MT2712_PIN_72_GBE_TXD2__FUNC_GBE_TXD2 (MTK_PIN_NO(72) | 1) -#define MT2712_PIN_72_GBE_TXD2__FUNC_DBG_MON_B_1_ (MTK_PIN_NO(72) | 7) - -#define MT2712_PIN_73_GBE_TXD1__FUNC_GPIO73 (MTK_PIN_NO(73) | 0) -#define MT2712_PIN_73_GBE_TXD1__FUNC_GBE_TXD1 (MTK_PIN_NO(73) | 1) -#define MT2712_PIN_73_GBE_TXD1__FUNC_DBG_MON_B_2_ (MTK_PIN_NO(73) | 7) - -#define MT2712_PIN_74_GBE_TXD0__FUNC_GPIO74 (MTK_PIN_NO(74) | 0) -#define MT2712_PIN_74_GBE_TXD0__FUNC_GBE_TXD0 (MTK_PIN_NO(74) | 1) -#define MT2712_PIN_74_GBE_TXD0__FUNC_DBG_MON_B_3_ (MTK_PIN_NO(74) | 7) - -#define MT2712_PIN_75_GBE_TXC__FUNC_GPIO75 (MTK_PIN_NO(75) | 0) -#define MT2712_PIN_75_GBE_TXC__FUNC_GBE_TXC (MTK_PIN_NO(75) | 1) -#define MT2712_PIN_75_GBE_TXC__FUNC_DBG_MON_B_4_ (MTK_PIN_NO(75) | 7) - -#define MT2712_PIN_76_GBE_TXEN__FUNC_GPIO76 (MTK_PIN_NO(76) | 0) -#define MT2712_PIN_76_GBE_TXEN__FUNC_GBE_TXEN (MTK_PIN_NO(76) | 1) -#define MT2712_PIN_76_GBE_TXEN__FUNC_DBG_MON_B_5_ (MTK_PIN_NO(76) | 7) - -#define MT2712_PIN_77_GBE_TXER__FUNC_GPIO77 (MTK_PIN_NO(77) | 0) -#define MT2712_PIN_77_GBE_TXER__FUNC_GBE_TXER (MTK_PIN_NO(77) | 1) -#define MT2712_PIN_77_GBE_TXER__FUNC_DBG_MON_B_6_ (MTK_PIN_NO(77) | 7) - -#define MT2712_PIN_78_GBE_RXD3__FUNC_GPIO78 (MTK_PIN_NO(78) | 0) -#define MT2712_PIN_78_GBE_RXD3__FUNC_GBE_RXD3 (MTK_PIN_NO(78) | 1) -#define MT2712_PIN_78_GBE_RXD3__FUNC_DBG_MON_B_7_ (MTK_PIN_NO(78) | 7) - -#define MT2712_PIN_79_GBE_RXD2__FUNC_GPIO79 (MTK_PIN_NO(79) | 0) -#define MT2712_PIN_79_GBE_RXD2__FUNC_GBE_RXD2 (MTK_PIN_NO(79) | 1) -#define MT2712_PIN_79_GBE_RXD2__FUNC_DBG_MON_B_8_ (MTK_PIN_NO(79) | 7) - -#define MT2712_PIN_80_GBE_RXD1__FUNC_GPIO80 (MTK_PIN_NO(80) | 0) -#define MT2712_PIN_80_GBE_RXD1__FUNC_GBE_RXD1 (MTK_PIN_NO(80) | 1) -#define MT2712_PIN_80_GBE_RXD1__FUNC_DBG_MON_B_9_ (MTK_PIN_NO(80) | 7) - -#define MT2712_PIN_81_GBE_RXD0__FUNC_GPIO81 (MTK_PIN_NO(81) | 0) -#define MT2712_PIN_81_GBE_RXD0__FUNC_GBE_RXD0 (MTK_PIN_NO(81) | 1) -#define MT2712_PIN_81_GBE_RXD0__FUNC_DBG_MON_B_10_ (MTK_PIN_NO(81) | 7) - -#define MT2712_PIN_82_GBE_RXDV__FUNC_GPIO82 (MTK_PIN_NO(82) | 0) -#define MT2712_PIN_82_GBE_RXDV__FUNC_GBE_RXDV (MTK_PIN_NO(82) | 1) -#define MT2712_PIN_82_GBE_RXDV__FUNC_DBG_MON_B_11_ (MTK_PIN_NO(82) | 7) - -#define MT2712_PIN_83_GBE_RXER__FUNC_GPIO83 (MTK_PIN_NO(83) | 0) -#define MT2712_PIN_83_GBE_RXER__FUNC_GBE_RXER (MTK_PIN_NO(83) | 1) -#define MT2712_PIN_83_GBE_RXER__FUNC_DBG_MON_B_12_ (MTK_PIN_NO(83) | 7) - -#define MT2712_PIN_84_GBE_RXC__FUNC_GPIO84 (MTK_PIN_NO(84) | 0) -#define MT2712_PIN_84_GBE_RXC__FUNC_GBE_RXC (MTK_PIN_NO(84) | 1) -#define MT2712_PIN_84_GBE_RXC__FUNC_DBG_MON_B_13_ (MTK_PIN_NO(84) | 7) - -#define MT2712_PIN_85_GBE_MDC__FUNC_GPIO85 (MTK_PIN_NO(85) | 0) -#define MT2712_PIN_85_GBE_MDC__FUNC_GBE_MDC (MTK_PIN_NO(85) | 1) -#define MT2712_PIN_85_GBE_MDC__FUNC_DBG_MON_B_14_ (MTK_PIN_NO(85) | 7) - -#define MT2712_PIN_86_GBE_MDIO__FUNC_GPIO86 (MTK_PIN_NO(86) | 0) -#define MT2712_PIN_86_GBE_MDIO__FUNC_GBE_MDIO (MTK_PIN_NO(86) | 1) -#define MT2712_PIN_86_GBE_MDIO__FUNC_DBG_MON_B_15_ (MTK_PIN_NO(86) | 7) - -#define MT2712_PIN_87_GBE_COL__FUNC_GPIO87 (MTK_PIN_NO(87) | 0) -#define MT2712_PIN_87_GBE_COL__FUNC_GBE_COL (MTK_PIN_NO(87) | 1) -#define MT2712_PIN_87_GBE_COL__FUNC_DBG_MON_B_16_ (MTK_PIN_NO(87) | 7) - -#define MT2712_PIN_88_GBE_INTR__FUNC_GPIO88 (MTK_PIN_NO(88) | 0) -#define MT2712_PIN_88_GBE_INTR__FUNC_GBE_INTR (MTK_PIN_NO(88) | 1) -#define MT2712_PIN_88_GBE_INTR__FUNC_GBE_CRS (MTK_PIN_NO(88) | 2) -#define MT2712_PIN_88_GBE_INTR__FUNC_DBG_MON_B_17_ (MTK_PIN_NO(88) | 7) - -#define MT2712_PIN_89_MSDC2_CLK__FUNC_GPIO89 (MTK_PIN_NO(89) | 0) -#define MT2712_PIN_89_MSDC2_CLK__FUNC_MSDC2_CLK (MTK_PIN_NO(89) | 1) -#define MT2712_PIN_89_MSDC2_CLK__FUNC_DBG_MON_B_18_ (MTK_PIN_NO(89) | 7) - -#define MT2712_PIN_90_MSDC2_DAT3__FUNC_GPIO90 (MTK_PIN_NO(90) | 0) -#define MT2712_PIN_90_MSDC2_DAT3__FUNC_MSDC2_DAT3 (MTK_PIN_NO(90) | 1) -#define MT2712_PIN_90_MSDC2_DAT3__FUNC_DBG_MON_B_19_ (MTK_PIN_NO(90) | 7) - -#define MT2712_PIN_91_MSDC2_DAT2__FUNC_GPIO91 (MTK_PIN_NO(91) | 0) -#define MT2712_PIN_91_MSDC2_DAT2__FUNC_MSDC2_DAT2 (MTK_PIN_NO(91) | 1) -#define MT2712_PIN_91_MSDC2_DAT2__FUNC_DBG_MON_B_20_ (MTK_PIN_NO(91) | 7) - -#define MT2712_PIN_92_MSDC2_DAT1__FUNC_GPIO92 (MTK_PIN_NO(92) | 0) -#define MT2712_PIN_92_MSDC2_DAT1__FUNC_MSDC2_DAT1 (MTK_PIN_NO(92) | 1) -#define MT2712_PIN_92_MSDC2_DAT1__FUNC_DBG_MON_B_21_ (MTK_PIN_NO(92) | 7) - -#define MT2712_PIN_93_MSDC2_DAT0__FUNC_GPIO93 (MTK_PIN_NO(93) | 0) -#define MT2712_PIN_93_MSDC2_DAT0__FUNC_MSDC2_DAT0 (MTK_PIN_NO(93) | 1) -#define MT2712_PIN_93_MSDC2_DAT0__FUNC_DBG_MON_B_22_ (MTK_PIN_NO(93) | 7) - -#define MT2712_PIN_94_MSDC2_INS__FUNC_GPIO94 (MTK_PIN_NO(94) | 0) -#define MT2712_PIN_94_MSDC2_INS__FUNC_DBG_MON_B_23_ (MTK_PIN_NO(94) | 7) - -#define MT2712_PIN_95_MSDC2_CMD__FUNC_GPIO95 (MTK_PIN_NO(95) | 0) -#define MT2712_PIN_95_MSDC2_CMD__FUNC_MSDC2_CMD (MTK_PIN_NO(95) | 1) -#define MT2712_PIN_95_MSDC2_CMD__FUNC_DBG_MON_B_24_ (MTK_PIN_NO(95) | 7) - -#define MT2712_PIN_96_MSDC2_PSW__FUNC_GPIO96 (MTK_PIN_NO(96) | 0) -#define MT2712_PIN_96_MSDC2_PSW__FUNC_DBG_MON_B_25_ (MTK_PIN_NO(96) | 7) - -#define MT2712_PIN_97_URXD4__FUNC_GPIO97 (MTK_PIN_NO(97) | 0) -#define MT2712_PIN_97_URXD4__FUNC_URXD4 (MTK_PIN_NO(97) | 1) -#define MT2712_PIN_97_URXD4__FUNC_UTXD4 (MTK_PIN_NO(97) | 2) -#define MT2712_PIN_97_URXD4__FUNC_MRG_CLK (MTK_PIN_NO(97) | 3) -#define MT2712_PIN_97_URXD4__FUNC_PCM1_CLK (MTK_PIN_NO(97) | 4) -#define MT2712_PIN_97_URXD4__FUNC_I2S_IQ2_SDQB (MTK_PIN_NO(97) | 5) -#define MT2712_PIN_97_URXD4__FUNC_I2SO1_WS (MTK_PIN_NO(97) | 6) -#define MT2712_PIN_97_URXD4__FUNC_DBG_MON_B_26_ (MTK_PIN_NO(97) | 7) - -#define MT2712_PIN_98_URTS4__FUNC_GPIO98 (MTK_PIN_NO(98) | 0) -#define MT2712_PIN_98_URTS4__FUNC_URTS4 (MTK_PIN_NO(98) | 1) -#define MT2712_PIN_98_URTS4__FUNC_UCTS4 (MTK_PIN_NO(98) | 2) -#define MT2712_PIN_98_URTS4__FUNC_MRG_RX (MTK_PIN_NO(98) | 3) -#define MT2712_PIN_98_URTS4__FUNC_PCM1_DI (MTK_PIN_NO(98) | 4) -#define MT2712_PIN_98_URTS4__FUNC_I2S_IQ1_SDIB (MTK_PIN_NO(98) | 5) -#define MT2712_PIN_98_URTS4__FUNC_I2SO1_MCK (MTK_PIN_NO(98) | 6) -#define MT2712_PIN_98_URTS4__FUNC_DBG_MON_B_27_ (MTK_PIN_NO(98) | 7) - -#define MT2712_PIN_99_UTXD4__FUNC_GPIO99 (MTK_PIN_NO(99) | 0) -#define MT2712_PIN_99_UTXD4__FUNC_UTXD4 (MTK_PIN_NO(99) | 1) -#define MT2712_PIN_99_UTXD4__FUNC_URXD4 (MTK_PIN_NO(99) | 2) -#define MT2712_PIN_99_UTXD4__FUNC_MRG_SYNC (MTK_PIN_NO(99) | 3) -#define MT2712_PIN_99_UTXD4__FUNC_PCM1_SYNC (MTK_PIN_NO(99) | 4) -#define MT2712_PIN_99_UTXD4__FUNC_I2S_IQ0_SDQB (MTK_PIN_NO(99) | 5) -#define MT2712_PIN_99_UTXD4__FUNC_I2SO1_BCK (MTK_PIN_NO(99) | 6) -#define MT2712_PIN_99_UTXD4__FUNC_DBG_MON_B_28_ (MTK_PIN_NO(99) | 7) - -#define MT2712_PIN_100_UCTS4__FUNC_GPIO100 (MTK_PIN_NO(100) | 0) -#define MT2712_PIN_100_UCTS4__FUNC_UCTS4 (MTK_PIN_NO(100) | 1) -#define MT2712_PIN_100_UCTS4__FUNC_URTS4 (MTK_PIN_NO(100) | 2) -#define MT2712_PIN_100_UCTS4__FUNC_MRG_TX (MTK_PIN_NO(100) | 3) -#define MT2712_PIN_100_UCTS4__FUNC_PCM1_DO (MTK_PIN_NO(100) | 4) -#define MT2712_PIN_100_UCTS4__FUNC_I2S_IQ0_SDIB (MTK_PIN_NO(100) | 5) -#define MT2712_PIN_100_UCTS4__FUNC_I2SO1_DO (MTK_PIN_NO(100) | 6) -#define MT2712_PIN_100_UCTS4__FUNC_DBG_MON_B_29_ (MTK_PIN_NO(100) | 7) - -#define MT2712_PIN_101_URXD5__FUNC_GPIO101 (MTK_PIN_NO(101) | 0) -#define MT2712_PIN_101_URXD5__FUNC_URXD5 (MTK_PIN_NO(101) | 1) -#define MT2712_PIN_101_URXD5__FUNC_UTXD5 (MTK_PIN_NO(101) | 2) -#define MT2712_PIN_101_URXD5__FUNC_I2SO3_WS (MTK_PIN_NO(101) | 3) -#define MT2712_PIN_101_URXD5__FUNC_TDMIN_LRCK (MTK_PIN_NO(101) | 4) -#define MT2712_PIN_101_URXD5__FUNC_I2SO0_WS (MTK_PIN_NO(101) | 6) -#define MT2712_PIN_101_URXD5__FUNC_DBG_MON_B_30_ (MTK_PIN_NO(101) | 7) - -#define MT2712_PIN_102_URTS5__FUNC_GPIO102 (MTK_PIN_NO(102) | 0) -#define MT2712_PIN_102_URTS5__FUNC_URTS5 (MTK_PIN_NO(102) | 1) -#define MT2712_PIN_102_URTS5__FUNC_UCTS5 (MTK_PIN_NO(102) | 2) -#define MT2712_PIN_102_URTS5__FUNC_I2SO3_MCK (MTK_PIN_NO(102) | 3) -#define MT2712_PIN_102_URTS5__FUNC_TDMIN_MCLK (MTK_PIN_NO(102) | 4) -#define MT2712_PIN_102_URTS5__FUNC_IR_IN (MTK_PIN_NO(102) | 5) -#define MT2712_PIN_102_URTS5__FUNC_I2SO0_MCK (MTK_PIN_NO(102) | 6) -#define MT2712_PIN_102_URTS5__FUNC_DBG_MON_B_31_ (MTK_PIN_NO(102) | 7) - -#define MT2712_PIN_103_UTXD5__FUNC_GPIO103 (MTK_PIN_NO(103) | 0) -#define MT2712_PIN_103_UTXD5__FUNC_UTXD5 (MTK_PIN_NO(103) | 1) -#define MT2712_PIN_103_UTXD5__FUNC_URXD5 (MTK_PIN_NO(103) | 2) -#define MT2712_PIN_103_UTXD5__FUNC_I2SO3_BCK (MTK_PIN_NO(103) | 3) -#define MT2712_PIN_103_UTXD5__FUNC_TDMIN_BCK (MTK_PIN_NO(103) | 4) -#define MT2712_PIN_103_UTXD5__FUNC_I2SO0_BCK (MTK_PIN_NO(103) | 6) -#define MT2712_PIN_103_UTXD5__FUNC_DBG_MON_B_32_ (MTK_PIN_NO(103) | 7) - -#define MT2712_PIN_104_UCTS5__FUNC_GPIO104 (MTK_PIN_NO(104) | 0) -#define MT2712_PIN_104_UCTS5__FUNC_UCTS5 (MTK_PIN_NO(104) | 1) -#define MT2712_PIN_104_UCTS5__FUNC_URTS5 (MTK_PIN_NO(104) | 2) -#define MT2712_PIN_104_UCTS5__FUNC_I2SO0_DO1 (MTK_PIN_NO(104) | 3) -#define MT2712_PIN_104_UCTS5__FUNC_TDMIN_DI (MTK_PIN_NO(104) | 4) -#define MT2712_PIN_104_UCTS5__FUNC_IR_IN (MTK_PIN_NO(104) | 5) -#define MT2712_PIN_104_UCTS5__FUNC_I2SO0_DO0 (MTK_PIN_NO(104) | 6) - -#define MT2712_PIN_105_I2C_SDA0__FUNC_GPIO105 (MTK_PIN_NO(105) | 0) -#define MT2712_PIN_105_I2C_SDA0__FUNC_SDA0 (MTK_PIN_NO(105) | 1) - -#define MT2712_PIN_106_I2C_SDA1__FUNC_GPIO106 (MTK_PIN_NO(106) | 0) -#define MT2712_PIN_106_I2C_SDA1__FUNC_SDA1 (MTK_PIN_NO(106) | 1) - -#define MT2712_PIN_107_I2C_SDA2__FUNC_GPIO107 (MTK_PIN_NO(107) | 0) -#define MT2712_PIN_107_I2C_SDA2__FUNC_SDA2 (MTK_PIN_NO(107) | 1) - -#define MT2712_PIN_108_I2C_SDA3__FUNC_GPIO108 (MTK_PIN_NO(108) | 0) -#define MT2712_PIN_108_I2C_SDA3__FUNC_SDA3 (MTK_PIN_NO(108) | 1) - -#define MT2712_PIN_109_I2C_SDA4__FUNC_GPIO109 (MTK_PIN_NO(109) | 0) -#define MT2712_PIN_109_I2C_SDA4__FUNC_SDA4 (MTK_PIN_NO(109) | 1) - -#define MT2712_PIN_110_I2C_SDA5__FUNC_GPIO110 (MTK_PIN_NO(110) | 0) -#define MT2712_PIN_110_I2C_SDA5__FUNC_SDA5 (MTK_PIN_NO(110) | 1) - -#define MT2712_PIN_111_I2C_SCL0__FUNC_GPIO111 (MTK_PIN_NO(111) | 0) -#define MT2712_PIN_111_I2C_SCL0__FUNC_SCL0 (MTK_PIN_NO(111) | 1) - -#define MT2712_PIN_112_I2C_SCL1__FUNC_GPIO112 (MTK_PIN_NO(112) | 0) -#define MT2712_PIN_112_I2C_SCL1__FUNC_SCL1 (MTK_PIN_NO(112) | 1) - -#define MT2712_PIN_113_I2C_SCL2__FUNC_GPIO113 (MTK_PIN_NO(113) | 0) -#define MT2712_PIN_113_I2C_SCL2__FUNC_SCL2 (MTK_PIN_NO(113) | 1) - -#define MT2712_PIN_114_I2C_SCL3__FUNC_GPIO114 (MTK_PIN_NO(114) | 0) -#define MT2712_PIN_114_I2C_SCL3__FUNC_SCL3 (MTK_PIN_NO(114) | 1) - -#define MT2712_PIN_115_I2C_SCL4__FUNC_GPIO115 (MTK_PIN_NO(115) | 0) -#define MT2712_PIN_115_I2C_SCL4__FUNC_SCL4 (MTK_PIN_NO(115) | 1) - -#define MT2712_PIN_116_I2C_SCL5__FUNC_GPIO116 (MTK_PIN_NO(116) | 0) -#define MT2712_PIN_116_I2C_SCL5__FUNC_SCL5 (MTK_PIN_NO(116) | 1) - -#define MT2712_PIN_117_URXD0__FUNC_GPIO117 (MTK_PIN_NO(117) | 0) -#define MT2712_PIN_117_URXD0__FUNC_URXD0 (MTK_PIN_NO(117) | 1) -#define MT2712_PIN_117_URXD0__FUNC_UTXD0 (MTK_PIN_NO(117) | 2) - -#define MT2712_PIN_118_URXD1__FUNC_GPIO118 (MTK_PIN_NO(118) | 0) -#define MT2712_PIN_118_URXD1__FUNC_URXD1 (MTK_PIN_NO(118) | 1) -#define MT2712_PIN_118_URXD1__FUNC_UTXD1 (MTK_PIN_NO(118) | 2) - -#define MT2712_PIN_119_URXD2__FUNC_GPIO119 (MTK_PIN_NO(119) | 0) -#define MT2712_PIN_119_URXD2__FUNC_URXD2 (MTK_PIN_NO(119) | 1) -#define MT2712_PIN_119_URXD2__FUNC_UTXD2 (MTK_PIN_NO(119) | 2) - -#define MT2712_PIN_120_UTXD0__FUNC_GPIO120 (MTK_PIN_NO(120) | 0) -#define MT2712_PIN_120_UTXD0__FUNC_UTXD0 (MTK_PIN_NO(120) | 1) -#define MT2712_PIN_120_UTXD0__FUNC_URXD0 (MTK_PIN_NO(120) | 2) - -#define MT2712_PIN_121_UTXD1__FUNC_GPIO121 (MTK_PIN_NO(121) | 0) -#define MT2712_PIN_121_UTXD1__FUNC_UTXD1 (MTK_PIN_NO(121) | 1) -#define MT2712_PIN_121_UTXD1__FUNC_URXD1 (MTK_PIN_NO(121) | 2) - -#define MT2712_PIN_122_UTXD2__FUNC_GPIO122 (MTK_PIN_NO(122) | 0) -#define MT2712_PIN_122_UTXD2__FUNC_UTXD2 (MTK_PIN_NO(122) | 1) -#define MT2712_PIN_122_UTXD2__FUNC_URXD2 (MTK_PIN_NO(122) | 2) - -#define MT2712_PIN_123_URXD3__FUNC_GPIO123 (MTK_PIN_NO(123) | 0) -#define MT2712_PIN_123_URXD3__FUNC_URXD3 (MTK_PIN_NO(123) | 1) -#define MT2712_PIN_123_URXD3__FUNC_UTXD3 (MTK_PIN_NO(123) | 2) -#define MT2712_PIN_123_URXD3__FUNC_PURE_HW_PROTECT (MTK_PIN_NO(123) | 3) - -#define MT2712_PIN_124_UTXD3__FUNC_GPIO124 (MTK_PIN_NO(124) | 0) -#define MT2712_PIN_124_UTXD3__FUNC_UTXD3 (MTK_PIN_NO(124) | 1) -#define MT2712_PIN_124_UTXD3__FUNC_URXD3 (MTK_PIN_NO(124) | 2) -#define MT2712_PIN_124_UTXD3__FUNC_PURE_HW_PROTECT (MTK_PIN_NO(124) | 3) - -#define MT2712_PIN_125_URTS3__FUNC_GPIO125 (MTK_PIN_NO(125) | 0) -#define MT2712_PIN_125_URTS3__FUNC_URTS3 (MTK_PIN_NO(125) | 1) -#define MT2712_PIN_125_URTS3__FUNC_UCTS3 (MTK_PIN_NO(125) | 2) -#define MT2712_PIN_125_URTS3__FUNC_WATCH_DOG (MTK_PIN_NO(125) | 3) - -#define MT2712_PIN_126_UCTS3__FUNC_GPIO126 (MTK_PIN_NO(126) | 0) -#define MT2712_PIN_126_UCTS3__FUNC_UCTS3 (MTK_PIN_NO(126) | 1) -#define MT2712_PIN_126_UCTS3__FUNC_URTS3 (MTK_PIN_NO(126) | 2) -#define MT2712_PIN_126_UCTS3__FUNC_SRCLKENA0 (MTK_PIN_NO(126) | 3) - -#define MT2712_PIN_127_SPI2_CSN__FUNC_GPIO127 (MTK_PIN_NO(127) | 0) -#define MT2712_PIN_127_SPI2_CSN__FUNC_SPI_CS_2_ (MTK_PIN_NO(127) | 1) -#define MT2712_PIN_127_SPI2_CSN__FUNC_SPI_CS_1_ (MTK_PIN_NO(127) | 2) - -#define MT2712_PIN_128_SPI2_MO__FUNC_GPIO128 (MTK_PIN_NO(128) | 0) -#define MT2712_PIN_128_SPI2_MO__FUNC_SPI_MO_2_ (MTK_PIN_NO(128) | 1) -#define MT2712_PIN_128_SPI2_MO__FUNC_SPI_SO_1_ (MTK_PIN_NO(128) | 2) - -#define MT2712_PIN_129_SPI2_MI__FUNC_GPIO129 (MTK_PIN_NO(129) | 0) -#define MT2712_PIN_129_SPI2_MI__FUNC_SPI_MI_2_ (MTK_PIN_NO(129) | 1) -#define MT2712_PIN_129_SPI2_MI__FUNC_SPI_SI_1_ (MTK_PIN_NO(129) | 2) - -#define MT2712_PIN_130_SPI2_CK__FUNC_GPIO130 (MTK_PIN_NO(130) | 0) -#define MT2712_PIN_130_SPI2_CK__FUNC_SPI_CK_2_ (MTK_PIN_NO(130) | 1) -#define MT2712_PIN_130_SPI2_CK__FUNC_SPI_CK_1_ (MTK_PIN_NO(130) | 2) - -#define MT2712_PIN_131_SPI3_CSN__FUNC_GPIO131 (MTK_PIN_NO(131) | 0) -#define MT2712_PIN_131_SPI3_CSN__FUNC_SPI_CS_3_ (MTK_PIN_NO(131) | 1) - -#define MT2712_PIN_132_SPI3_MO__FUNC_GPIO132 (MTK_PIN_NO(132) | 0) -#define MT2712_PIN_132_SPI3_MO__FUNC_SPI_MO_3_ (MTK_PIN_NO(132) | 1) - -#define MT2712_PIN_133_SPI3_MI__FUNC_GPIO133 (MTK_PIN_NO(133) | 0) -#define MT2712_PIN_133_SPI3_MI__FUNC_SPI_MI_3_ (MTK_PIN_NO(133) | 1) - -#define MT2712_PIN_134_SPI3_CK__FUNC_GPIO134 (MTK_PIN_NO(134) | 0) -#define MT2712_PIN_134_SPI3_CK__FUNC_SPI_CK_3_ (MTK_PIN_NO(134) | 1) - -#define MT2712_PIN_135_KPROW3__FUNC_GPIO135 (MTK_PIN_NO(135) | 0) -#define MT2712_PIN_135_KPROW3__FUNC_KROW3 (MTK_PIN_NO(135) | 1) -#define MT2712_PIN_135_KPROW3__FUNC_DSIC_TE (MTK_PIN_NO(135) | 2) - -#define MT2712_PIN_136_KPROW4__FUNC_GPIO136 (MTK_PIN_NO(136) | 0) -#define MT2712_PIN_136_KPROW4__FUNC_KROW4 (MTK_PIN_NO(136) | 1) -#define MT2712_PIN_136_KPROW4__FUNC_DSID_TE (MTK_PIN_NO(136) | 2) - -#define MT2712_PIN_137_KPCOL3__FUNC_GPIO137 (MTK_PIN_NO(137) | 0) -#define MT2712_PIN_137_KPCOL3__FUNC_KCOL3 (MTK_PIN_NO(137) | 1) -#define MT2712_PIN_137_KPCOL3__FUNC_DISP2_PWM (MTK_PIN_NO(137) | 2) - -#define MT2712_PIN_138_KPCOL4__FUNC_GPIO138 (MTK_PIN_NO(138) | 0) -#define MT2712_PIN_138_KPCOL4__FUNC_KCOL4 (MTK_PIN_NO(138) | 1) -#define MT2712_PIN_138_KPCOL4__FUNC_LCM_RST2 (MTK_PIN_NO(138) | 2) - -#define MT2712_PIN_139_KPCOL5__FUNC_GPIO139 (MTK_PIN_NO(139) | 0) -#define MT2712_PIN_139_KPCOL5__FUNC_KCOL5 (MTK_PIN_NO(139) | 1) -#define MT2712_PIN_139_KPCOL5__FUNC_DSIA_TE (MTK_PIN_NO(139) | 3) -#define MT2712_PIN_139_KPCOL5__FUNC_PURE_HW_PROTECT (MTK_PIN_NO(139) | 4) - -#define MT2712_PIN_140_KPCOL6__FUNC_GPIO140 (MTK_PIN_NO(140) | 0) -#define MT2712_PIN_140_KPCOL6__FUNC_KCOL6 (MTK_PIN_NO(140) | 1) -#define MT2712_PIN_140_KPCOL6__FUNC_WATCH_DOG (MTK_PIN_NO(140) | 2) -#define MT2712_PIN_140_KPCOL6__FUNC_LCM_RST1 (MTK_PIN_NO(140) | 3) - -#define MT2712_PIN_141_KPROW5__FUNC_GPIO141 (MTK_PIN_NO(141) | 0) -#define MT2712_PIN_141_KPROW5__FUNC_KROW5 (MTK_PIN_NO(141) | 1) -#define MT2712_PIN_141_KPROW5__FUNC_LCM_RST0 (MTK_PIN_NO(141) | 3) -#define MT2712_PIN_141_KPROW5__FUNC_PURE_HW_PROTECT (MTK_PIN_NO(141) | 4) - -#define MT2712_PIN_142_KPROW6__FUNC_GPIO142 (MTK_PIN_NO(142) | 0) -#define MT2712_PIN_142_KPROW6__FUNC_KROW6 (MTK_PIN_NO(142) | 1) -#define MT2712_PIN_142_KPROW6__FUNC_SRCLKENA0 (MTK_PIN_NO(142) | 2) -#define MT2712_PIN_142_KPROW6__FUNC_DSIB_TE (MTK_PIN_NO(142) | 3) - -#define MT2712_PIN_143_JTDO_ICE__FUNC_GPIO143 (MTK_PIN_NO(143) | 0) -#define MT2712_PIN_143_JTDO_ICE__FUNC_JTDO_ICE (MTK_PIN_NO(143) | 1) -#define MT2712_PIN_143_JTDO_ICE__FUNC_DFD_TDO (MTK_PIN_NO(143) | 3) - -#define MT2712_PIN_144_JTCK_ICE__FUNC_GPIO144 (MTK_PIN_NO(144) | 0) -#define MT2712_PIN_144_JTCK_ICE__FUNC_JTCK_ICE (MTK_PIN_NO(144) | 1) -#define MT2712_PIN_144_JTCK_ICE__FUNC_DFD_TCK (MTK_PIN_NO(144) | 3) - -#define MT2712_PIN_145_JTDI_ICE__FUNC_GPIO145 (MTK_PIN_NO(145) | 0) -#define MT2712_PIN_145_JTDI_ICE__FUNC_JTDI_ICE (MTK_PIN_NO(145) | 1) -#define MT2712_PIN_145_JTDI_ICE__FUNC_DFD_TDI (MTK_PIN_NO(145) | 3) - -#define MT2712_PIN_146_JTMS_ICE__FUNC_GPIO146 (MTK_PIN_NO(146) | 0) -#define MT2712_PIN_146_JTMS_ICE__FUNC_JTMS_ICE (MTK_PIN_NO(146) | 1) -#define MT2712_PIN_146_JTMS_ICE__FUNC_DFD_TMS (MTK_PIN_NO(146) | 3) - -#define MT2712_PIN_147_JTRSTB_ICE__FUNC_GPIO147 (MTK_PIN_NO(147) | 0) -#define MT2712_PIN_147_JTRSTB_ICE__FUNC_JTRST_B_ICE (MTK_PIN_NO(147) | 1) -#define MT2712_PIN_147_JTRSTB_ICE__FUNC_DFD_NTRST (MTK_PIN_NO(147) | 3) - -#define MT2712_PIN_148_GPIO148__FUNC_GPIO148 (MTK_PIN_NO(148) | 0) -#define MT2712_PIN_148_GPIO148__FUNC_JTRSTB_CM4 (MTK_PIN_NO(148) | 1) -#define MT2712_PIN_148_GPIO148__FUNC_DFD_NTRST (MTK_PIN_NO(148) | 3) - -#define MT2712_PIN_149_GPIO149__FUNC_GPIO149 (MTK_PIN_NO(149) | 0) -#define MT2712_PIN_149_GPIO149__FUNC_JTCK_CM4 (MTK_PIN_NO(149) | 1) -#define MT2712_PIN_149_GPIO149__FUNC_DFD_TCK (MTK_PIN_NO(149) | 3) - -#define MT2712_PIN_150_GPIO150__FUNC_GPIO150 (MTK_PIN_NO(150) | 0) -#define MT2712_PIN_150_GPIO150__FUNC_JTMS_CM4 (MTK_PIN_NO(150) | 1) -#define MT2712_PIN_150_GPIO150__FUNC_DFD_TMS (MTK_PIN_NO(150) | 3) - -#define MT2712_PIN_151_GPIO151__FUNC_GPIO151 (MTK_PIN_NO(151) | 0) -#define MT2712_PIN_151_GPIO151__FUNC_JTDI_CM4 (MTK_PIN_NO(151) | 1) -#define MT2712_PIN_151_GPIO151__FUNC_DFD_TDI (MTK_PIN_NO(151) | 3) - -#define MT2712_PIN_152_GPIO152__FUNC_GPIO152 (MTK_PIN_NO(152) | 0) -#define MT2712_PIN_152_GPIO152__FUNC_JTDO_CM4 (MTK_PIN_NO(152) | 1) -#define MT2712_PIN_152_GPIO152__FUNC_DFD_TDO (MTK_PIN_NO(152) | 3) - -#define MT2712_PIN_153_SPI0_CSN__FUNC_GPIO153 (MTK_PIN_NO(153) | 0) -#define MT2712_PIN_153_SPI0_CSN__FUNC_SPI_CS_0_ (MTK_PIN_NO(153) | 1) -#define MT2712_PIN_153_SPI0_CSN__FUNC_SRCLKENA0 (MTK_PIN_NO(153) | 2) -#define MT2712_PIN_153_SPI0_CSN__FUNC_UTXD0 (MTK_PIN_NO(153) | 3) -#define MT2712_PIN_153_SPI0_CSN__FUNC_I2SO0_DO1 (MTK_PIN_NO(153) | 4) -#define MT2712_PIN_153_SPI0_CSN__FUNC_TDMO0_DATA1 (MTK_PIN_NO(153) | 6) -#define MT2712_PIN_153_SPI0_CSN__FUNC_I2S_IQ2_SDQB (MTK_PIN_NO(153) | 7) - -#define MT2712_PIN_154_SPI0_MI__FUNC_GPIO154 (MTK_PIN_NO(154) | 0) -#define MT2712_PIN_154_SPI0_MI__FUNC_SPI_MI_0_ (MTK_PIN_NO(154) | 1) -#define MT2712_PIN_154_SPI0_MI__FUNC_SRCLKENA0 (MTK_PIN_NO(154) | 2) -#define MT2712_PIN_154_SPI0_MI__FUNC_URXD0 (MTK_PIN_NO(154) | 3) -#define MT2712_PIN_154_SPI0_MI__FUNC_I2SO0_DO0 (MTK_PIN_NO(154) | 4) -#define MT2712_PIN_154_SPI0_MI__FUNC_I2SO1_DO (MTK_PIN_NO(154) | 5) -#define MT2712_PIN_154_SPI0_MI__FUNC_TDMO0_DATA (MTK_PIN_NO(154) | 6) -#define MT2712_PIN_154_SPI0_MI__FUNC_I2S_IQ1_SDIB (MTK_PIN_NO(154) | 7) - -#define MT2712_PIN_155_SPI0_CK__FUNC_GPIO155 (MTK_PIN_NO(155) | 0) -#define MT2712_PIN_155_SPI0_CK__FUNC_SPI_CK_0_ (MTK_PIN_NO(155) | 1) -#define MT2712_PIN_155_SPI0_CK__FUNC_SC_APBIAS_OFF (MTK_PIN_NO(155) | 2) -#define MT2712_PIN_155_SPI0_CK__FUNC_UTXD1 (MTK_PIN_NO(155) | 3) -#define MT2712_PIN_155_SPI0_CK__FUNC_I2SO0_BCK (MTK_PIN_NO(155) | 4) -#define MT2712_PIN_155_SPI0_CK__FUNC_I2SO1_BCK (MTK_PIN_NO(155) | 5) -#define MT2712_PIN_155_SPI0_CK__FUNC_TDMO0_BCK (MTK_PIN_NO(155) | 6) -#define MT2712_PIN_155_SPI0_CK__FUNC_I2S_IQ0_SDQB (MTK_PIN_NO(155) | 7) - -#define MT2712_PIN_156_SPI0_MO__FUNC_GPIO156 (MTK_PIN_NO(156) | 0) -#define MT2712_PIN_156_SPI0_MO__FUNC_SPI_MO_0_ (MTK_PIN_NO(156) | 1) -#define MT2712_PIN_156_SPI0_MO__FUNC_SC_APBIAS_OFF (MTK_PIN_NO(156) | 2) -#define MT2712_PIN_156_SPI0_MO__FUNC_URXD1 (MTK_PIN_NO(156) | 3) -#define MT2712_PIN_156_SPI0_MO__FUNC_I2SO0_WS (MTK_PIN_NO(156) | 4) -#define MT2712_PIN_156_SPI0_MO__FUNC_I2SO1_WS (MTK_PIN_NO(156) | 5) -#define MT2712_PIN_156_SPI0_MO__FUNC_TDMO0_LRCK (MTK_PIN_NO(156) | 6) -#define MT2712_PIN_156_SPI0_MO__FUNC_I2S_IQ0_SDIB (MTK_PIN_NO(156) | 7) - -#define MT2712_PIN_157_SPI5_CSN__FUNC_GPIO157 (MTK_PIN_NO(157) | 0) -#define MT2712_PIN_157_SPI5_CSN__FUNC_SPI_CS_5_ (MTK_PIN_NO(157) | 1) -#define MT2712_PIN_157_SPI5_CSN__FUNC_LCM_RST0 (MTK_PIN_NO(157) | 2) -#define MT2712_PIN_157_SPI5_CSN__FUNC_UTXD2 (MTK_PIN_NO(157) | 3) -#define MT2712_PIN_157_SPI5_CSN__FUNC_I2SO0_MCK (MTK_PIN_NO(157) | 4) -#define MT2712_PIN_157_SPI5_CSN__FUNC_I2SO1_MCK (MTK_PIN_NO(157) | 5) -#define MT2712_PIN_157_SPI5_CSN__FUNC_TDMO0_MCLK (MTK_PIN_NO(157) | 6) - -#define MT2712_PIN_158_SPI5_MI__FUNC_GPIO158 (MTK_PIN_NO(158) | 0) -#define MT2712_PIN_158_SPI5_MI__FUNC_SPI_MI_5_ (MTK_PIN_NO(158) | 1) -#define MT2712_PIN_158_SPI5_MI__FUNC_DSIA_TE (MTK_PIN_NO(158) | 2) -#define MT2712_PIN_158_SPI5_MI__FUNC_URXD2 (MTK_PIN_NO(158) | 3) - -#define MT2712_PIN_159_SPI5_MO__FUNC_GPIO159 (MTK_PIN_NO(159) | 0) -#define MT2712_PIN_159_SPI5_MO__FUNC_SPI_MO_5_ (MTK_PIN_NO(159) | 1) -#define MT2712_PIN_159_SPI5_MO__FUNC_DSIB_TE (MTK_PIN_NO(159) | 2) -#define MT2712_PIN_159_SPI5_MO__FUNC_UTXD3 (MTK_PIN_NO(159) | 3) - -#define MT2712_PIN_160_SPI5_CK__FUNC_GPIO160 (MTK_PIN_NO(160) | 0) -#define MT2712_PIN_160_SPI5_CK__FUNC_SPI_CK_5_ (MTK_PIN_NO(160) | 1) -#define MT2712_PIN_160_SPI5_CK__FUNC_LCM_RST1 (MTK_PIN_NO(160) | 2) -#define MT2712_PIN_160_SPI5_CK__FUNC_URXD3 (MTK_PIN_NO(160) | 3) - -#define MT2712_PIN_161_SPI1_CSN__FUNC_GPIO161 (MTK_PIN_NO(161) | 0) -#define MT2712_PIN_161_SPI1_CSN__FUNC_SPI_CS_1_ (MTK_PIN_NO(161) | 1) -#define MT2712_PIN_161_SPI1_CSN__FUNC_SPI_CS_4_ (MTK_PIN_NO(161) | 2) -#define MT2712_PIN_161_SPI1_CSN__FUNC_I2S_IQ2_SDQB (MTK_PIN_NO(161) | 4) -#define MT2712_PIN_161_SPI1_CSN__FUNC_I2SO2_DO (MTK_PIN_NO(161) | 5) -#define MT2712_PIN_161_SPI1_CSN__FUNC_TDMO0_DATA1 (MTK_PIN_NO(161) | 6) -#define MT2712_PIN_161_SPI1_CSN__FUNC_I2SO0_DO1 (MTK_PIN_NO(161) | 7) - -#define MT2712_PIN_162_SPI1_SI__FUNC_GPIO162 (MTK_PIN_NO(162) | 0) -#define MT2712_PIN_162_SPI1_SI__FUNC_SPI_SI_1_ (MTK_PIN_NO(162) | 1) -#define MT2712_PIN_162_SPI1_SI__FUNC_SPI_MI_4_ (MTK_PIN_NO(162) | 2) -#define MT2712_PIN_162_SPI1_SI__FUNC_I2S_IQ1_SDIB (MTK_PIN_NO(162) | 4) -#define MT2712_PIN_162_SPI1_SI__FUNC_I2SO2_BCK (MTK_PIN_NO(162) | 5) -#define MT2712_PIN_162_SPI1_SI__FUNC_TDMO0_DATA (MTK_PIN_NO(162) | 6) -#define MT2712_PIN_162_SPI1_SI__FUNC_I2SO0_DO0 (MTK_PIN_NO(162) | 7) - -#define MT2712_PIN_163_SPI1_CK__FUNC_GPIO163 (MTK_PIN_NO(163) | 0) -#define MT2712_PIN_163_SPI1_CK__FUNC_SPI_CK_1_ (MTK_PIN_NO(163) | 1) -#define MT2712_PIN_163_SPI1_CK__FUNC_SPI_CK_4_ (MTK_PIN_NO(163) | 2) -#define MT2712_PIN_163_SPI1_CK__FUNC_I2S_IQ0_SDQB (MTK_PIN_NO(163) | 4) -#define MT2712_PIN_163_SPI1_CK__FUNC_I2SO2_WS (MTK_PIN_NO(163) | 5) -#define MT2712_PIN_163_SPI1_CK__FUNC_TDMO0_BCK (MTK_PIN_NO(163) | 6) -#define MT2712_PIN_163_SPI1_CK__FUNC_I2SO0_BCK (MTK_PIN_NO(163) | 7) - -#define MT2712_PIN_164_SPI1_SO__FUNC_GPIO164 (MTK_PIN_NO(164) | 0) -#define MT2712_PIN_164_SPI1_SO__FUNC_SPI_SO_1_ (MTK_PIN_NO(164) | 1) -#define MT2712_PIN_164_SPI1_SO__FUNC_SPI_MO_4_ (MTK_PIN_NO(164) | 2) -#define MT2712_PIN_164_SPI1_SO__FUNC_I2S_IQ0_SDIB (MTK_PIN_NO(164) | 4) -#define MT2712_PIN_164_SPI1_SO__FUNC_I2SO2_MCK (MTK_PIN_NO(164) | 5) -#define MT2712_PIN_164_SPI1_SO__FUNC_TDMO0_LRCK (MTK_PIN_NO(164) | 6) -#define MT2712_PIN_164_SPI1_SO__FUNC_I2SO0_WS (MTK_PIN_NO(164) | 7) - -#define MT2712_PIN_165_SPI4_CSN__FUNC_GPIO165 (MTK_PIN_NO(165) | 0) -#define MT2712_PIN_165_SPI4_CSN__FUNC_SPI_CS_4_ (MTK_PIN_NO(165) | 1) -#define MT2712_PIN_165_SPI4_CSN__FUNC_LCM_RST0 (MTK_PIN_NO(165) | 2) -#define MT2712_PIN_165_SPI4_CSN__FUNC_SPI_CS_1_ (MTK_PIN_NO(165) | 3) -#define MT2712_PIN_165_SPI4_CSN__FUNC_UTXD4 (MTK_PIN_NO(165) | 4) -#define MT2712_PIN_165_SPI4_CSN__FUNC_I2SO1_DO (MTK_PIN_NO(165) | 5) -#define MT2712_PIN_165_SPI4_CSN__FUNC_TDMO0_MCLK (MTK_PIN_NO(165) | 6) -#define MT2712_PIN_165_SPI4_CSN__FUNC_I2SO0_MCK (MTK_PIN_NO(165) | 7) - -#define MT2712_PIN_166_SPI4_MI__FUNC_GPIO166 (MTK_PIN_NO(166) | 0) -#define MT2712_PIN_166_SPI4_MI__FUNC_SPI_MI_4_ (MTK_PIN_NO(166) | 1) -#define MT2712_PIN_166_SPI4_MI__FUNC_DSIA_TE (MTK_PIN_NO(166) | 2) -#define MT2712_PIN_166_SPI4_MI__FUNC_SPI_SI_1_ (MTK_PIN_NO(166) | 3) -#define MT2712_PIN_166_SPI4_MI__FUNC_URXD4 (MTK_PIN_NO(166) | 4) -#define MT2712_PIN_166_SPI4_MI__FUNC_I2SO1_BCK (MTK_PIN_NO(166) | 5) - -#define MT2712_PIN_167_SPI4_MO__FUNC_GPIO167 (MTK_PIN_NO(167) | 0) -#define MT2712_PIN_167_SPI4_MO__FUNC_SPI_MO_4_ (MTK_PIN_NO(167) | 1) -#define MT2712_PIN_167_SPI4_MO__FUNC_DSIB_TE (MTK_PIN_NO(167) | 2) -#define MT2712_PIN_167_SPI4_MO__FUNC_SPI_SO_1_ (MTK_PIN_NO(167) | 3) -#define MT2712_PIN_167_SPI4_MO__FUNC_UTXD5 (MTK_PIN_NO(167) | 4) -#define MT2712_PIN_167_SPI4_MO__FUNC_I2SO1_WS (MTK_PIN_NO(167) | 5) - -#define MT2712_PIN_168_SPI4_CK__FUNC_GPIO168 (MTK_PIN_NO(168) | 0) -#define MT2712_PIN_168_SPI4_CK__FUNC_SPI_CK_4_ (MTK_PIN_NO(168) | 1) -#define MT2712_PIN_168_SPI4_CK__FUNC_LCM_RST1 (MTK_PIN_NO(168) | 2) -#define MT2712_PIN_168_SPI4_CK__FUNC_SPI_CK_1_ (MTK_PIN_NO(168) | 3) -#define MT2712_PIN_168_SPI4_CK__FUNC_URXD5 (MTK_PIN_NO(168) | 4) -#define MT2712_PIN_168_SPI4_CK__FUNC_I2SO1_MCK (MTK_PIN_NO(168) | 5) - -#define MT2712_PIN_169_I2SI0_DATA__FUNC_GPIO169 (MTK_PIN_NO(169) | 0) -#define MT2712_PIN_169_I2SI0_DATA__FUNC_I2SI0_DI (MTK_PIN_NO(169) | 1) -#define MT2712_PIN_169_I2SI0_DATA__FUNC_I2SI1_DI (MTK_PIN_NO(169) | 2) -#define MT2712_PIN_169_I2SI0_DATA__FUNC_I2SI2_DI (MTK_PIN_NO(169) | 3) -#define MT2712_PIN_169_I2SI0_DATA__FUNC_TDMIN_DI (MTK_PIN_NO(169) | 4) - -#define MT2712_PIN_170_I2SI0_LRCK__FUNC_GPIO170 (MTK_PIN_NO(170) | 0) -#define MT2712_PIN_170_I2SI0_LRCK__FUNC_I2SI0_WS (MTK_PIN_NO(170) | 1) -#define MT2712_PIN_170_I2SI0_LRCK__FUNC_I2SI1_WS (MTK_PIN_NO(170) | 2) -#define MT2712_PIN_170_I2SI0_LRCK__FUNC_I2SI2_WS (MTK_PIN_NO(170) | 3) -#define MT2712_PIN_170_I2SI0_LRCK__FUNC_TDMIN_LRCK (MTK_PIN_NO(170) | 4) -#define MT2712_PIN_170_I2SI0_LRCK__FUNC_TDMO0_DATA3 (MTK_PIN_NO(170) | 5) -#define MT2712_PIN_170_I2SI0_LRCK__FUNC_TDMO1_DATA3 (MTK_PIN_NO(170) | 6) - -#define MT2712_PIN_171_I2SI0_MCLK__FUNC_GPIO171 (MTK_PIN_NO(171) | 0) -#define MT2712_PIN_171_I2SI0_MCLK__FUNC_I2SI0_MCK (MTK_PIN_NO(171) | 1) -#define MT2712_PIN_171_I2SI0_MCLK__FUNC_I2SI1_MCK (MTK_PIN_NO(171) | 2) -#define MT2712_PIN_171_I2SI0_MCLK__FUNC_I2SI2_MCK (MTK_PIN_NO(171) | 3) -#define MT2712_PIN_171_I2SI0_MCLK__FUNC_TDMIN_MCLK (MTK_PIN_NO(171) | 4) -#define MT2712_PIN_171_I2SI0_MCLK__FUNC_TDMO0_DATA2 (MTK_PIN_NO(171) | 5) -#define MT2712_PIN_171_I2SI0_MCLK__FUNC_TDMO1_DATA2 (MTK_PIN_NO(171) | 6) - -#define MT2712_PIN_172_I2SI0_BCK__FUNC_GPIO172 (MTK_PIN_NO(172) | 0) -#define MT2712_PIN_172_I2SI0_BCK__FUNC_I2SI0_BCK (MTK_PIN_NO(172) | 1) -#define MT2712_PIN_172_I2SI0_BCK__FUNC_I2SI1_BCK (MTK_PIN_NO(172) | 2) -#define MT2712_PIN_172_I2SI0_BCK__FUNC_I2SI2_BCK (MTK_PIN_NO(172) | 3) -#define MT2712_PIN_172_I2SI0_BCK__FUNC_TDMIN_BCK (MTK_PIN_NO(172) | 4) -#define MT2712_PIN_172_I2SI0_BCK__FUNC_TDMO0_DATA1 (MTK_PIN_NO(172) | 5) -#define MT2712_PIN_172_I2SI0_BCK__FUNC_TDMO1_DATA1 (MTK_PIN_NO(172) | 6) - -#define MT2712_PIN_173_I2SI2_DATA__FUNC_GPIO173 (MTK_PIN_NO(173) | 0) -#define MT2712_PIN_173_I2SI2_DATA__FUNC_I2SI2_DI (MTK_PIN_NO(173) | 1) -#define MT2712_PIN_173_I2SI2_DATA__FUNC_I2SI0_DI (MTK_PIN_NO(173) | 2) -#define MT2712_PIN_173_I2SI2_DATA__FUNC_I2SI1_DI (MTK_PIN_NO(173) | 3) -#define MT2712_PIN_173_I2SI2_DATA__FUNC_PCM1_DI (MTK_PIN_NO(173) | 4) -#define MT2712_PIN_173_I2SI2_DATA__FUNC_TDMIN_DI (MTK_PIN_NO(173) | 5) -#define MT2712_PIN_173_I2SI2_DATA__FUNC_PCM1_DO (MTK_PIN_NO(173) | 6) - -#define MT2712_PIN_174_I2SI2_MCLK__FUNC_GPIO174 (MTK_PIN_NO(174) | 0) -#define MT2712_PIN_174_I2SI2_MCLK__FUNC_I2SI2_MCK (MTK_PIN_NO(174) | 1) -#define MT2712_PIN_174_I2SI2_MCLK__FUNC_I2SI0_MCK (MTK_PIN_NO(174) | 2) -#define MT2712_PIN_174_I2SI2_MCLK__FUNC_I2SI1_MCK (MTK_PIN_NO(174) | 3) -#define MT2712_PIN_174_I2SI2_MCLK__FUNC_PCM1_DO (MTK_PIN_NO(174) | 4) -#define MT2712_PIN_174_I2SI2_MCLK__FUNC_TDMIN_MCLK (MTK_PIN_NO(174) | 5) -#define MT2712_PIN_174_I2SI2_MCLK__FUNC_PCM1_DI (MTK_PIN_NO(174) | 6) -#define MT2712_PIN_174_I2SI2_MCLK__FUNC_I2S_IQ2_SDQB (MTK_PIN_NO(174) | 7) - -#define MT2712_PIN_175_I2SI2_BCK__FUNC_GPIO175 (MTK_PIN_NO(175) | 0) -#define MT2712_PIN_175_I2SI2_BCK__FUNC_I2SI2_BCK (MTK_PIN_NO(175) | 1) -#define MT2712_PIN_175_I2SI2_BCK__FUNC_I2SI0_BCK (MTK_PIN_NO(175) | 2) -#define MT2712_PIN_175_I2SI2_BCK__FUNC_I2SI1_BCK (MTK_PIN_NO(175) | 3) -#define MT2712_PIN_175_I2SI2_BCK__FUNC_PCM1_CLK (MTK_PIN_NO(175) | 4) -#define MT2712_PIN_175_I2SI2_BCK__FUNC_TDMIN_BCK (MTK_PIN_NO(175) | 5) - -#define MT2712_PIN_176_I2SI2_LRCK__FUNC_GPIO176 (MTK_PIN_NO(176) | 0) -#define MT2712_PIN_176_I2SI2_LRCK__FUNC_I2SI2_WS (MTK_PIN_NO(176) | 1) -#define MT2712_PIN_176_I2SI2_LRCK__FUNC_I2SI0_WS (MTK_PIN_NO(176) | 2) -#define MT2712_PIN_176_I2SI2_LRCK__FUNC_I2SI1_WS (MTK_PIN_NO(176) | 3) -#define MT2712_PIN_176_I2SI2_LRCK__FUNC_PCM1_SYNC (MTK_PIN_NO(176) | 4) -#define MT2712_PIN_176_I2SI2_LRCK__FUNC_TDMIN_LRCK (MTK_PIN_NO(176) | 5) - -#define MT2712_PIN_177_I2SI1_DATA__FUNC_GPIO177 (MTK_PIN_NO(177) | 0) -#define MT2712_PIN_177_I2SI1_DATA__FUNC_I2SI1_DI (MTK_PIN_NO(177) | 1) -#define MT2712_PIN_177_I2SI1_DATA__FUNC_I2SI0_DI (MTK_PIN_NO(177) | 2) -#define MT2712_PIN_177_I2SI1_DATA__FUNC_I2SI2_DI (MTK_PIN_NO(177) | 3) -#define MT2712_PIN_177_I2SI1_DATA__FUNC_TDMIN_DI (MTK_PIN_NO(177) | 4) - -#define MT2712_PIN_178_I2SI1_BCK__FUNC_GPIO178 (MTK_PIN_NO(178) | 0) -#define MT2712_PIN_178_I2SI1_BCK__FUNC_I2SI1_BCK (MTK_PIN_NO(178) | 1) -#define MT2712_PIN_178_I2SI1_BCK__FUNC_I2SI0_BCK (MTK_PIN_NO(178) | 2) -#define MT2712_PIN_178_I2SI1_BCK__FUNC_I2SI2_BCK (MTK_PIN_NO(178) | 3) -#define MT2712_PIN_178_I2SI1_BCK__FUNC_TDMIN_BCK (MTK_PIN_NO(178) | 4) -#define MT2712_PIN_178_I2SI1_BCK__FUNC_TDMO0_DATA3 (MTK_PIN_NO(178) | 5) -#define MT2712_PIN_178_I2SI1_BCK__FUNC_TDMO1_DATA3 (MTK_PIN_NO(178) | 6) - -#define MT2712_PIN_179_I2SI1_LRCK__FUNC_GPIO179 (MTK_PIN_NO(179) | 0) -#define MT2712_PIN_179_I2SI1_LRCK__FUNC_I2SI1_WS (MTK_PIN_NO(179) | 1) -#define MT2712_PIN_179_I2SI1_LRCK__FUNC_I2SI0_WS (MTK_PIN_NO(179) | 2) -#define MT2712_PIN_179_I2SI1_LRCK__FUNC_I2SI2_WS (MTK_PIN_NO(179) | 3) -#define MT2712_PIN_179_I2SI1_LRCK__FUNC_TDMIN_LRCK (MTK_PIN_NO(179) | 4) -#define MT2712_PIN_179_I2SI1_LRCK__FUNC_TDMO0_DATA2 (MTK_PIN_NO(179) | 5) -#define MT2712_PIN_179_I2SI1_LRCK__FUNC_TDMO1_DATA2 (MTK_PIN_NO(179) | 6) - -#define MT2712_PIN_180_I2SI1_MCLK__FUNC_GPIO180 (MTK_PIN_NO(180) | 0) -#define MT2712_PIN_180_I2SI1_MCLK__FUNC_I2SI1_MCK (MTK_PIN_NO(180) | 1) -#define MT2712_PIN_180_I2SI1_MCLK__FUNC_I2SI0_MCK (MTK_PIN_NO(180) | 2) -#define MT2712_PIN_180_I2SI1_MCLK__FUNC_I2SI2_MCK (MTK_PIN_NO(180) | 3) -#define MT2712_PIN_180_I2SI1_MCLK__FUNC_TDMIN_MCLK (MTK_PIN_NO(180) | 4) -#define MT2712_PIN_180_I2SI1_MCLK__FUNC_TDMO0_DATA1 (MTK_PIN_NO(180) | 5) -#define MT2712_PIN_180_I2SI1_MCLK__FUNC_TDMO1_DATA1 (MTK_PIN_NO(180) | 6) -#define MT2712_PIN_180_I2SI1_MCLK__FUNC_I2S_IQ2_SDIB (MTK_PIN_NO(180) | 7) - -#define MT2712_PIN_181_I2SO1_DATA0__FUNC_GPIO181 (MTK_PIN_NO(181) | 0) -#define MT2712_PIN_181_I2SO1_DATA0__FUNC_I2SO1_DO (MTK_PIN_NO(181) | 1) -#define MT2712_PIN_181_I2SO1_DATA0__FUNC_I2SO0_DO0 (MTK_PIN_NO(181) | 2) -#define MT2712_PIN_181_I2SO1_DATA0__FUNC_I2SO2_DO (MTK_PIN_NO(181) | 3) -#define MT2712_PIN_181_I2SO1_DATA0__FUNC_DAI_TX (MTK_PIN_NO(181) | 4) -#define MT2712_PIN_181_I2SO1_DATA0__FUNC_TDMIN_MCLK (MTK_PIN_NO(181) | 5) -#define MT2712_PIN_181_I2SO1_DATA0__FUNC_I2S_IQ2_SDIA (MTK_PIN_NO(181) | 7) - -#define MT2712_PIN_182_I2SO1_BCK__FUNC_GPIO182 (MTK_PIN_NO(182) | 0) -#define MT2712_PIN_182_I2SO1_BCK__FUNC_I2SO1_BCK (MTK_PIN_NO(182) | 1) -#define MT2712_PIN_182_I2SO1_BCK__FUNC_I2SO0_BCK (MTK_PIN_NO(182) | 2) -#define MT2712_PIN_182_I2SO1_BCK__FUNC_I2SO2_BCK (MTK_PIN_NO(182) | 3) -#define MT2712_PIN_182_I2SO1_BCK__FUNC_DAI_SYNC (MTK_PIN_NO(182) | 4) -#define MT2712_PIN_182_I2SO1_BCK__FUNC_TDMIN_BCK (MTK_PIN_NO(182) | 5) -#define MT2712_PIN_182_I2SO1_BCK__FUNC_TDMO0_DATA3 (MTK_PIN_NO(182) | 6) -#define MT2712_PIN_182_I2SO1_BCK__FUNC_I2S_IQ2_BCK (MTK_PIN_NO(182) | 7) - -#define MT2712_PIN_183_I2SO1_LRCK__FUNC_GPIO183 (MTK_PIN_NO(183) | 0) -#define MT2712_PIN_183_I2SO1_LRCK__FUNC_I2SO1_WS (MTK_PIN_NO(183) | 1) -#define MT2712_PIN_183_I2SO1_LRCK__FUNC_I2SO0_WS (MTK_PIN_NO(183) | 2) -#define MT2712_PIN_183_I2SO1_LRCK__FUNC_I2SO2_WS (MTK_PIN_NO(183) | 3) -#define MT2712_PIN_183_I2SO1_LRCK__FUNC_DAI_CLK (MTK_PIN_NO(183) | 4) -#define MT2712_PIN_183_I2SO1_LRCK__FUNC_TDMIN_DI (MTK_PIN_NO(183) | 5) -#define MT2712_PIN_183_I2SO1_LRCK__FUNC_TDMO0_DATA2 (MTK_PIN_NO(183) | 6) -#define MT2712_PIN_183_I2SO1_LRCK__FUNC_I2S_IQ2_WS (MTK_PIN_NO(183) | 7) - -#define MT2712_PIN_184_I2SO1_MCLK__FUNC_GPIO184 (MTK_PIN_NO(184) | 0) -#define MT2712_PIN_184_I2SO1_MCLK__FUNC_I2SO1_MCK (MTK_PIN_NO(184) | 1) -#define MT2712_PIN_184_I2SO1_MCLK__FUNC_I2SO0_MCK (MTK_PIN_NO(184) | 2) -#define MT2712_PIN_184_I2SO1_MCLK__FUNC_I2SO2_MCK (MTK_PIN_NO(184) | 3) -#define MT2712_PIN_184_I2SO1_MCLK__FUNC_DAI_RX (MTK_PIN_NO(184) | 4) -#define MT2712_PIN_184_I2SO1_MCLK__FUNC_TDMIN_LRCK (MTK_PIN_NO(184) | 5) -#define MT2712_PIN_184_I2SO1_MCLK__FUNC_TDMO0_DATA1 (MTK_PIN_NO(184) | 6) -#define MT2712_PIN_184_I2SO1_MCLK__FUNC_I2S_IQ2_SDQA (MTK_PIN_NO(184) | 7) - -#define MT2712_PIN_185_AUD_EXT_CK2__FUNC_GPIO185 (MTK_PIN_NO(185) | 0) -#define MT2712_PIN_185_AUD_EXT_CK2__FUNC_AUD_EXT_CK2 (MTK_PIN_NO(185) | 1) -#define MT2712_PIN_185_AUD_EXT_CK2__FUNC_AUD_EXT_CK1 (MTK_PIN_NO(185) | 2) -#define MT2712_PIN_185_AUD_EXT_CK2__FUNC_I2SO1_DO (MTK_PIN_NO(185) | 3) -#define MT2712_PIN_185_AUD_EXT_CK2__FUNC_I2SI2_DI (MTK_PIN_NO(185) | 4) -#define MT2712_PIN_185_AUD_EXT_CK2__FUNC_MRG_RX (MTK_PIN_NO(185) | 5) -#define MT2712_PIN_185_AUD_EXT_CK2__FUNC_PCM1_DI (MTK_PIN_NO(185) | 6) -#define MT2712_PIN_185_AUD_EXT_CK2__FUNC_I2S_IQ0_SDQB (MTK_PIN_NO(185) | 7) - -#define MT2712_PIN_186_AUD_EXT_CK1__FUNC_GPIO186 (MTK_PIN_NO(186) | 0) -#define MT2712_PIN_186_AUD_EXT_CK1__FUNC_AUD_EXT_CK1 (MTK_PIN_NO(186) | 1) -#define MT2712_PIN_186_AUD_EXT_CK1__FUNC_AUD_EXT_CK2 (MTK_PIN_NO(186) | 2) -#define MT2712_PIN_186_AUD_EXT_CK1__FUNC_I2SO0_DO1 (MTK_PIN_NO(186) | 3) -#define MT2712_PIN_186_AUD_EXT_CK1__FUNC_I2SI1_DI (MTK_PIN_NO(186) | 4) -#define MT2712_PIN_186_AUD_EXT_CK1__FUNC_MRG_TX (MTK_PIN_NO(186) | 5) -#define MT2712_PIN_186_AUD_EXT_CK1__FUNC_PCM1_DO (MTK_PIN_NO(186) | 6) -#define MT2712_PIN_186_AUD_EXT_CK1__FUNC_I2S_IQ0_SDIB (MTK_PIN_NO(186) | 7) - -#define MT2712_PIN_187_I2SO2_BCK__FUNC_GPIO187 (MTK_PIN_NO(187) | 0) -#define MT2712_PIN_187_I2SO2_BCK__FUNC_I2SO2_BCK (MTK_PIN_NO(187) | 1) -#define MT2712_PIN_187_I2SO2_BCK__FUNC_I2SO0_BCK (MTK_PIN_NO(187) | 2) -#define MT2712_PIN_187_I2SO2_BCK__FUNC_I2SO1_BCK (MTK_PIN_NO(187) | 3) -#define MT2712_PIN_187_I2SO2_BCK__FUNC_PCM1_CLK (MTK_PIN_NO(187) | 4) -#define MT2712_PIN_187_I2SO2_BCK__FUNC_MRG_SYNC (MTK_PIN_NO(187) | 5) -#define MT2712_PIN_187_I2SO2_BCK__FUNC_TDMO1_DATA3 (MTK_PIN_NO(187) | 6) -#define MT2712_PIN_187_I2SO2_BCK__FUNC_I2S_IQ0_BCK (MTK_PIN_NO(187) | 7) - -#define MT2712_PIN_188_I2SO2_LRCK__FUNC_GPIO188 (MTK_PIN_NO(188) | 0) -#define MT2712_PIN_188_I2SO2_LRCK__FUNC_I2SO2_WS (MTK_PIN_NO(188) | 1) -#define MT2712_PIN_188_I2SO2_LRCK__FUNC_I2SO0_WS (MTK_PIN_NO(188) | 2) -#define MT2712_PIN_188_I2SO2_LRCK__FUNC_I2SO1_WS (MTK_PIN_NO(188) | 3) -#define MT2712_PIN_188_I2SO2_LRCK__FUNC_PCM1_SYNC (MTK_PIN_NO(188) | 4) -#define MT2712_PIN_188_I2SO2_LRCK__FUNC_MRG_CLK (MTK_PIN_NO(188) | 5) -#define MT2712_PIN_188_I2SO2_LRCK__FUNC_TDMO1_DATA2 (MTK_PIN_NO(188) | 6) -#define MT2712_PIN_188_I2SO2_LRCK__FUNC_I2S_IQ0_WS (MTK_PIN_NO(188) | 7) - -#define MT2712_PIN_189_I2SO2_MCLK__FUNC_GPIO189 (MTK_PIN_NO(189) | 0) -#define MT2712_PIN_189_I2SO2_MCLK__FUNC_I2SO2_MCK (MTK_PIN_NO(189) | 1) -#define MT2712_PIN_189_I2SO2_MCLK__FUNC_I2SO0_MCK (MTK_PIN_NO(189) | 2) -#define MT2712_PIN_189_I2SO2_MCLK__FUNC_I2SO1_MCK (MTK_PIN_NO(189) | 3) -#define MT2712_PIN_189_I2SO2_MCLK__FUNC_PCM1_DO (MTK_PIN_NO(189) | 4) -#define MT2712_PIN_189_I2SO2_MCLK__FUNC_MRG_RX (MTK_PIN_NO(189) | 5) -#define MT2712_PIN_189_I2SO2_MCLK__FUNC_TDMO1_DATA1 (MTK_PIN_NO(189) | 6) -#define MT2712_PIN_189_I2SO2_MCLK__FUNC_I2S_IQ0_SDQA (MTK_PIN_NO(189) | 7) - -#define MT2712_PIN_190_I2SO2_DATA0__FUNC_GPIO190 (MTK_PIN_NO(190) | 0) -#define MT2712_PIN_190_I2SO2_DATA0__FUNC_I2SO2_DO (MTK_PIN_NO(190) | 1) -#define MT2712_PIN_190_I2SO2_DATA0__FUNC_I2SO0_DO0 (MTK_PIN_NO(190) | 2) -#define MT2712_PIN_190_I2SO2_DATA0__FUNC_I2SO1_DO (MTK_PIN_NO(190) | 3) -#define MT2712_PIN_190_I2SO2_DATA0__FUNC_PCM1_DI (MTK_PIN_NO(190) | 4) -#define MT2712_PIN_190_I2SO2_DATA0__FUNC_MRG_TX (MTK_PIN_NO(190) | 5) -#define MT2712_PIN_190_I2SO2_DATA0__FUNC_PCM1_DO (MTK_PIN_NO(190) | 6) -#define MT2712_PIN_190_I2SO2_DATA0__FUNC_I2S_IQ0_SDIA (MTK_PIN_NO(190) | 7) - -#define MT2712_PIN_191_I2SO0_DATA1__FUNC_GPIO191 (MTK_PIN_NO(191) | 0) -#define MT2712_PIN_191_I2SO0_DATA1__FUNC_I2SO0_DO1 (MTK_PIN_NO(191) | 1) -#define MT2712_PIN_191_I2SO0_DATA1__FUNC_I2SI0_DI (MTK_PIN_NO(191) | 2) -#define MT2712_PIN_191_I2SO0_DATA1__FUNC_I2SI1_DI (MTK_PIN_NO(191) | 3) -#define MT2712_PIN_191_I2SO0_DATA1__FUNC_I2SI2_DI (MTK_PIN_NO(191) | 4) -#define MT2712_PIN_191_I2SO0_DATA1__FUNC_DAI_TX (MTK_PIN_NO(191) | 5) -#define MT2712_PIN_191_I2SO0_DATA1__FUNC_I2S_IQ0_SDQB (MTK_PIN_NO(191) | 6) -#define MT2712_PIN_191_I2SO0_DATA1__FUNC_I2S_IQ1_SDQB (MTK_PIN_NO(191) | 7) - -#define MT2712_PIN_192_I2SO0_MCLK__FUNC_GPIO192 (MTK_PIN_NO(192) | 0) -#define MT2712_PIN_192_I2SO0_MCLK__FUNC_I2SO0_MCK (MTK_PIN_NO(192) | 1) -#define MT2712_PIN_192_I2SO0_MCLK__FUNC_I2SO1_MCK (MTK_PIN_NO(192) | 2) -#define MT2712_PIN_192_I2SO0_MCLK__FUNC_I2SO2_MCK (MTK_PIN_NO(192) | 3) -#define MT2712_PIN_192_I2SO0_MCLK__FUNC_USB4_FT_SCL (MTK_PIN_NO(192) | 4) -#define MT2712_PIN_192_I2SO0_MCLK__FUNC_TDMO1_DATA3 (MTK_PIN_NO(192) | 5) -#define MT2712_PIN_192_I2SO0_MCLK__FUNC_I2S_IQ0_SDIB (MTK_PIN_NO(192) | 6) -#define MT2712_PIN_192_I2SO0_MCLK__FUNC_I2S_IQ1_SDQA (MTK_PIN_NO(192) | 7) - -#define MT2712_PIN_193_I2SO0_DATA0__FUNC_GPIO193 (MTK_PIN_NO(193) | 0) -#define MT2712_PIN_193_I2SO0_DATA0__FUNC_I2SO0_DO0 (MTK_PIN_NO(193) | 1) -#define MT2712_PIN_193_I2SO0_DATA0__FUNC_I2SO1_DO (MTK_PIN_NO(193) | 2) -#define MT2712_PIN_193_I2SO0_DATA0__FUNC_I2SO2_DO (MTK_PIN_NO(193) | 3) -#define MT2712_PIN_193_I2SO0_DATA0__FUNC_USB4_FT_SDA (MTK_PIN_NO(193) | 4) -#define MT2712_PIN_193_I2SO0_DATA0__FUNC_I2S_IQ1_SDIA (MTK_PIN_NO(193) | 7) - -#define MT2712_PIN_194_I2SO0_LRCK__FUNC_GPIO194 (MTK_PIN_NO(194) | 0) -#define MT2712_PIN_194_I2SO0_LRCK__FUNC_I2SO0_WS (MTK_PIN_NO(194) | 1) -#define MT2712_PIN_194_I2SO0_LRCK__FUNC_I2SO1_WS (MTK_PIN_NO(194) | 2) -#define MT2712_PIN_194_I2SO0_LRCK__FUNC_I2SO2_WS (MTK_PIN_NO(194) | 3) -#define MT2712_PIN_194_I2SO0_LRCK__FUNC_USB5_FT_SCL (MTK_PIN_NO(194) | 4) -#define MT2712_PIN_194_I2SO0_LRCK__FUNC_TDMO1_DATA2 (MTK_PIN_NO(194) | 5) -#define MT2712_PIN_194_I2SO0_LRCK__FUNC_I2S_IQ1_WS (MTK_PIN_NO(194) | 7) - -#define MT2712_PIN_195_I2SO0_BCK__FUNC_GPIO195 (MTK_PIN_NO(195) | 0) -#define MT2712_PIN_195_I2SO0_BCK__FUNC_I2SO0_BCK (MTK_PIN_NO(195) | 1) -#define MT2712_PIN_195_I2SO0_BCK__FUNC_I2SO1_BCK (MTK_PIN_NO(195) | 2) -#define MT2712_PIN_195_I2SO0_BCK__FUNC_I2SO2_BCK (MTK_PIN_NO(195) | 3) -#define MT2712_PIN_195_I2SO0_BCK__FUNC_USB5_FT_SDA (MTK_PIN_NO(195) | 4) -#define MT2712_PIN_195_I2SO0_BCK__FUNC_TDMO1_DATA1 (MTK_PIN_NO(195) | 5) -#define MT2712_PIN_195_I2SO0_BCK__FUNC_I2S_IQ1_BCK (MTK_PIN_NO(195) | 7) - -#define MT2712_PIN_196_TDMO1_MCLK__FUNC_GPIO196 (MTK_PIN_NO(196) | 0) -#define MT2712_PIN_196_TDMO1_MCLK__FUNC_TDMO1_MCLK (MTK_PIN_NO(196) | 1) -#define MT2712_PIN_196_TDMO1_MCLK__FUNC_TDMO0_MCLK (MTK_PIN_NO(196) | 2) -#define MT2712_PIN_196_TDMO1_MCLK__FUNC_TDMIN_MCLK (MTK_PIN_NO(196) | 3) -#define MT2712_PIN_196_TDMO1_MCLK__FUNC_I2SO0_DO1 (MTK_PIN_NO(196) | 6) -#define MT2712_PIN_196_TDMO1_MCLK__FUNC_I2S_IQ1_SDIB (MTK_PIN_NO(196) | 7) - -#define MT2712_PIN_197_TDMO1_LRCK__FUNC_GPIO197 (MTK_PIN_NO(197) | 0) -#define MT2712_PIN_197_TDMO1_LRCK__FUNC_TDMO1_LRCK (MTK_PIN_NO(197) | 1) -#define MT2712_PIN_197_TDMO1_LRCK__FUNC_TDMO0_LRCK (MTK_PIN_NO(197) | 2) -#define MT2712_PIN_197_TDMO1_LRCK__FUNC_TDMIN_LRCK (MTK_PIN_NO(197) | 3) -#define MT2712_PIN_197_TDMO1_LRCK__FUNC_TDMO0_DATA3 (MTK_PIN_NO(197) | 4) -#define MT2712_PIN_197_TDMO1_LRCK__FUNC_TDMO1_DATA3 (MTK_PIN_NO(197) | 5) -#define MT2712_PIN_197_TDMO1_LRCK__FUNC_I2SO3_MCK (MTK_PIN_NO(197) | 6) -#define MT2712_PIN_197_TDMO1_LRCK__FUNC_TDMO1_DATA2 (MTK_PIN_NO(197) | 7) - -#define MT2712_PIN_198_TDMO1_BCK__FUNC_GPIO198 (MTK_PIN_NO(198) | 0) -#define MT2712_PIN_198_TDMO1_BCK__FUNC_TDMO1_BCK (MTK_PIN_NO(198) | 1) -#define MT2712_PIN_198_TDMO1_BCK__FUNC_TDMO0_BCK (MTK_PIN_NO(198) | 2) -#define MT2712_PIN_198_TDMO1_BCK__FUNC_TDMIN_BCK (MTK_PIN_NO(198) | 3) -#define MT2712_PIN_198_TDMO1_BCK__FUNC_TDMO0_DATA2 (MTK_PIN_NO(198) | 4) -#define MT2712_PIN_198_TDMO1_BCK__FUNC_TDMO1_DATA2 (MTK_PIN_NO(198) | 5) -#define MT2712_PIN_198_TDMO1_BCK__FUNC_I2SO3_BCK (MTK_PIN_NO(198) | 6) -#define MT2712_PIN_198_TDMO1_BCK__FUNC_TDMO1_DATA1 (MTK_PIN_NO(198) | 7) - -#define MT2712_PIN_199_TDMO1_DATA__FUNC_GPIO199 (MTK_PIN_NO(199) | 0) -#define MT2712_PIN_199_TDMO1_DATA__FUNC_TDMO1_DATA (MTK_PIN_NO(199) | 1) -#define MT2712_PIN_199_TDMO1_DATA__FUNC_TDMO0_DATA (MTK_PIN_NO(199) | 2) -#define MT2712_PIN_199_TDMO1_DATA__FUNC_TDMIN_DI (MTK_PIN_NO(199) | 3) -#define MT2712_PIN_199_TDMO1_DATA__FUNC_TDMO0_DATA1 (MTK_PIN_NO(199) | 4) -#define MT2712_PIN_199_TDMO1_DATA__FUNC_TDMO1_DATA1 (MTK_PIN_NO(199) | 5) -#define MT2712_PIN_199_TDMO1_DATA__FUNC_I2SO3_WS (MTK_PIN_NO(199) | 6) - -#define MT2712_PIN_200_TDMO0_MCLK__FUNC_GPIO200 (MTK_PIN_NO(200) | 0) -#define MT2712_PIN_200_TDMO0_MCLK__FUNC_TDMO0_MCLK0 (MTK_PIN_NO(200) | 1) -#define MT2712_PIN_200_TDMO0_MCLK__FUNC_TDMO1_MCLK0 (MTK_PIN_NO(200) | 2) -#define MT2712_PIN_200_TDMO0_MCLK__FUNC_PCM1_DI (MTK_PIN_NO(200) | 3) -#define MT2712_PIN_200_TDMO0_MCLK__FUNC_TDMO0_MCLK1 (MTK_PIN_NO(200) | 4) -#define MT2712_PIN_200_TDMO0_MCLK__FUNC_TDMO1_MCLK1 (MTK_PIN_NO(200) | 5) -#define MT2712_PIN_200_TDMO0_MCLK__FUNC_MRG_TX (MTK_PIN_NO(200) | 6) -#define MT2712_PIN_200_TDMO0_MCLK__FUNC_I2SO2_MCK (MTK_PIN_NO(200) | 7) - -#define MT2712_PIN_201_TDMO0_LRCK__FUNC_GPIO201 (MTK_PIN_NO(201) | 0) -#define MT2712_PIN_201_TDMO0_LRCK__FUNC_TDMO0_LRCK0 (MTK_PIN_NO(201) | 1) -#define MT2712_PIN_201_TDMO0_LRCK__FUNC_TDMO1_LRCK0 (MTK_PIN_NO(201) | 2) -#define MT2712_PIN_201_TDMO0_LRCK__FUNC_PCM1_SYNC (MTK_PIN_NO(201) | 3) -#define MT2712_PIN_201_TDMO0_LRCK__FUNC_TDMO0_LRCK1 (MTK_PIN_NO(201) | 4) -#define MT2712_PIN_201_TDMO0_LRCK__FUNC_TDMO1_LRCK1 (MTK_PIN_NO(201) | 5) -#define MT2712_PIN_201_TDMO0_LRCK__FUNC_MRG_RX (MTK_PIN_NO(201) | 6) -#define MT2712_PIN_201_TDMO0_LRCK__FUNC_I2SO2_WS (MTK_PIN_NO(201) | 7) - -#define MT2712_PIN_202_TDMO0_BCK__FUNC_GPIO202 (MTK_PIN_NO(202) | 0) -#define MT2712_PIN_202_TDMO0_BCK__FUNC_TDMO0_BCK0 (MTK_PIN_NO(202) | 1) -#define MT2712_PIN_202_TDMO0_BCK__FUNC_TDMO1_BCK0 (MTK_PIN_NO(202) | 2) -#define MT2712_PIN_202_TDMO0_BCK__FUNC_PCM1_CLK (MTK_PIN_NO(202) | 3) -#define MT2712_PIN_202_TDMO0_BCK__FUNC_TDMO0_BCK1 (MTK_PIN_NO(202) | 4) -#define MT2712_PIN_202_TDMO0_BCK__FUNC_TDMO1_BCK1 (MTK_PIN_NO(202) | 5) -#define MT2712_PIN_202_TDMO0_BCK__FUNC_MRG_SYNC (MTK_PIN_NO(202) | 6) -#define MT2712_PIN_202_TDMO0_BCK__FUNC_I2SO2_BCK (MTK_PIN_NO(202) | 7) - -#define MT2712_PIN_203_TDMO0_DATA__FUNC_GPIO203 (MTK_PIN_NO(203) | 0) -#define MT2712_PIN_203_TDMO0_DATA__FUNC_TDMO0_DATA0 (MTK_PIN_NO(203) | 1) -#define MT2712_PIN_203_TDMO0_DATA__FUNC_TDMO1_DATA0 (MTK_PIN_NO(203) | 2) -#define MT2712_PIN_203_TDMO0_DATA__FUNC_PCM1_DO (MTK_PIN_NO(203) | 3) -#define MT2712_PIN_203_TDMO0_DATA__FUNC_TDMO0_DATA1 (MTK_PIN_NO(203) | 4) -#define MT2712_PIN_203_TDMO0_DATA__FUNC_TDMO1_DATA1 (MTK_PIN_NO(203) | 5) -#define MT2712_PIN_203_TDMO0_DATA__FUNC_MRG_CLK (MTK_PIN_NO(203) | 6) -#define MT2712_PIN_203_TDMO0_DATA__FUNC_I2SO2_DO (MTK_PIN_NO(203) | 7) - -#define MT2712_PIN_204_PERSTB_P0__FUNC_GPIO204 (MTK_PIN_NO(204) | 0) -#define MT2712_PIN_204_PERSTB_P0__FUNC_PERST_B_P0 (MTK_PIN_NO(204) | 1) - -#define MT2712_PIN_205_CLKREQN_P0__FUNC_GPIO205 (MTK_PIN_NO(205) | 0) -#define MT2712_PIN_205_CLKREQN_P0__FUNC_CLKREQ_N_P0 (MTK_PIN_NO(205) | 1) - -#define MT2712_PIN_206_WAKEEN_P0__FUNC_GPIO206 (MTK_PIN_NO(206) | 0) -#define MT2712_PIN_206_WAKEEN_P0__FUNC_WAKE_EN_P0 (MTK_PIN_NO(206) | 1) - -#define MT2712_PIN_207_PERSTB_P1__FUNC_GPIO207 (MTK_PIN_NO(207) | 0) -#define MT2712_PIN_207_PERSTB_P1__FUNC_PERST_B_P1 (MTK_PIN_NO(207) | 1) - -#define MT2712_PIN_208_CLKREQN_P1__FUNC_GPIO208 (MTK_PIN_NO(208) | 0) -#define MT2712_PIN_208_CLKREQN_P1__FUNC_CLKREQ_N_P1 (MTK_PIN_NO(208) | 1) - -#define MT2712_PIN_209_WAKEEN_P1__FUNC_GPIO209 (MTK_PIN_NO(209) | 0) -#define MT2712_PIN_209_WAKEEN_P1__FUNC_WAKE_EN_P1 (MTK_PIN_NO(209) | 1) - -#endif /* __DTS_MT2712_PINFUNC_H */ diff --git a/sys/gnu/dts/arm64/mediatek/mt2712e.dtsi b/sys/gnu/dts/arm64/mediatek/mt2712e.dtsi deleted file mode 100644 index 43307bad3f0..00000000000 --- a/sys/gnu/dts/arm64/mediatek/mt2712e.dtsi +++ /dev/null @@ -1,1003 +0,0 @@ -/* - * Copyright (c) 2017 MediaTek Inc. - * Author: YT Shen - * - * SPDX-License-Identifier: (GPL-2.0 OR MIT) - */ - -#include -#include -#include -#include -#include -#include -#include "mt2712-pinfunc.h" - -/ { - compatible = "mediatek,mt2712"; - interrupt-parent = <&sysirq>; - #address-cells = <2>; - #size-cells = <2>; - - cluster0_opp: opp_table0 { - compatible = "operating-points-v2"; - opp-shared; - opp00 { - opp-hz = /bits/ 64 <598000000>; - opp-microvolt = <1000000>; - }; - opp01 { - opp-hz = /bits/ 64 <702000000>; - opp-microvolt = <1000000>; - }; - opp02 { - opp-hz = /bits/ 64 <793000000>; - opp-microvolt = <1000000>; - }; - }; - - cluster1_opp: opp_table1 { - compatible = "operating-points-v2"; - opp-shared; - opp00 { - opp-hz = /bits/ 64 <598000000>; - opp-microvolt = <1000000>; - }; - opp01 { - opp-hz = /bits/ 64 <702000000>; - opp-microvolt = <1000000>; - }; - opp02 { - opp-hz = /bits/ 64 <793000000>; - opp-microvolt = <1000000>; - }; - opp03 { - opp-hz = /bits/ 64 <897000000>; - opp-microvolt = <1000000>; - }; - opp04 { - opp-hz = /bits/ 64 <1001000000>; - opp-microvolt = <1000000>; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu-map { - cluster0 { - core0 { - cpu = <&cpu0>; - }; - core1 { - cpu = <&cpu1>; - }; - }; - - cluster1 { - core0 { - cpu = <&cpu2>; - }; - }; - }; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a35"; - reg = <0x000>; - clocks = <&mcucfg CLK_MCU_MP0_SEL>, - <&topckgen CLK_TOP_F_MP0_PLL1>; - clock-names = "cpu", "intermediate"; - proc-supply = <&cpus_fixed_vproc0>; - operating-points-v2 = <&cluster0_opp>; - cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a35"; - reg = <0x001>; - enable-method = "psci"; - clocks = <&mcucfg CLK_MCU_MP0_SEL>, - <&topckgen CLK_TOP_F_MP0_PLL1>; - clock-names = "cpu", "intermediate"; - proc-supply = <&cpus_fixed_vproc0>; - operating-points-v2 = <&cluster0_opp>; - cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; - }; - - cpu2: cpu@200 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x200>; - enable-method = "psci"; - clocks = <&mcucfg CLK_MCU_MP2_SEL>, - <&topckgen CLK_TOP_F_BIG_PLL1>; - clock-names = "cpu", "intermediate"; - proc-supply = <&cpus_fixed_vproc1>; - operating-points-v2 = <&cluster1_opp>; - cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; - }; - - idle-states { - entry-method = "psci"; - - CPU_SLEEP_0: cpu-sleep-0 { - compatible = "arm,idle-state"; - local-timer-stop; - entry-latency-us = <100>; - exit-latency-us = <80>; - min-residency-us = <2000>; - arm,psci-suspend-param = <0x0010000>; - }; - - CLUSTER_SLEEP_0: cluster-sleep-0 { - compatible = "arm,idle-state"; - local-timer-stop; - entry-latency-us = <350>; - exit-latency-us = <80>; - min-residency-us = <3000>; - arm,psci-suspend-param = <0x1010000>; - }; - }; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - baud_clk: dummy26m { - compatible = "fixed-clock"; - clock-frequency = <26000000>; - #clock-cells = <0>; - }; - - sys_clk: dummyclk { - compatible = "fixed-clock"; - clock-frequency = <26000000>; - #clock-cells = <0>; - }; - - clk26m: oscillator@0 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <26000000>; - clock-output-names = "clk26m"; - }; - - clk32k: oscillator@1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "clk32k"; - }; - - clkfpc: oscillator@2 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <50000000>; - clock-output-names = "clkfpc"; - }; - - clkaud_ext_i_0: oscillator@3 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <6500000>; - clock-output-names = "clkaud_ext_i_0"; - }; - - clkaud_ext_i_1: oscillator@4 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <196608000>; - clock-output-names = "clkaud_ext_i_1"; - }; - - clkaud_ext_i_2: oscillator@5 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <180633600>; - clock-output-names = "clkaud_ext_i_2"; - }; - - clki2si0_mck_i: oscillator@6 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <30000000>; - clock-output-names = "clki2si0_mck_i"; - }; - - clki2si1_mck_i: oscillator@7 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <30000000>; - clock-output-names = "clki2si1_mck_i"; - }; - - clki2si2_mck_i: oscillator@8 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <30000000>; - clock-output-names = "clki2si2_mck_i"; - }; - - clktdmin_mclk_i: oscillator@9 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <30000000>; - clock-output-names = "clktdmin_mclk_i"; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupt-parent = <&gic>; - interrupts = , - , - , - ; - }; - - topckgen: syscon@10000000 { - compatible = "mediatek,mt2712-topckgen", "syscon"; - reg = <0 0x10000000 0 0x1000>; - #clock-cells = <1>; - }; - - infracfg: syscon@10001000 { - compatible = "mediatek,mt2712-infracfg", "syscon"; - reg = <0 0x10001000 0 0x1000>; - #clock-cells = <1>; - }; - - pericfg: syscon@10003000 { - compatible = "mediatek,mt2712-pericfg", "syscon"; - reg = <0 0x10003000 0 0x1000>; - #clock-cells = <1>; - }; - - syscfg_pctl_a: syscfg_pctl_a@10005000 { - compatible = "mediatek,mt2712-pctl-a-syscfg", "syscon"; - reg = <0 0x10005000 0 0x1000>; - }; - - pio: pinctrl@10005000 { - compatible = "mediatek,mt2712-pinctrl"; - reg = <0 0x1000b000 0 0x1000>; - mediatek,pctl-regmap = <&syscfg_pctl_a>; - pins-are-numbered; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = ; - }; - - scpsys: scpsys@10006000 { - compatible = "mediatek,mt2712-scpsys", "syscon"; - #power-domain-cells = <1>; - reg = <0 0x10006000 0 0x1000>; - clocks = <&topckgen CLK_TOP_MM_SEL>, - <&topckgen CLK_TOP_MFG_SEL>, - <&topckgen CLK_TOP_VENC_SEL>, - <&topckgen CLK_TOP_JPGDEC_SEL>, - <&topckgen CLK_TOP_A1SYS_HP_SEL>, - <&topckgen CLK_TOP_VDEC_SEL>; - clock-names = "mm", "mfg", "venc", - "jpgdec", "audio", "vdec"; - infracfg = <&infracfg>; - }; - - uart5: serial@1000f000 { - compatible = "mediatek,mt2712-uart", - "mediatek,mt6577-uart"; - reg = <0 0x1000f000 0 0x400>; - interrupts = ; - clocks = <&baud_clk>, <&sys_clk>; - clock-names = "baud", "bus"; - status = "disabled"; - }; - - spis1: spi@10013000 { - compatible = "mediatek,mt2712-spi-slave"; - reg = <0 0x10013000 0 0x100>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_AO_SPI1>; - clock-names = "spi"; - assigned-clocks = <&topckgen CLK_TOP_SPISLV_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>; - status = "disabled"; - }; - - iommu0: iommu@10205000 { - compatible = "mediatek,mt2712-m4u"; - reg = <0 0x10205000 0 0x1000>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_M4U>; - clock-names = "bclk"; - mediatek,larbs = <&larb0 &larb1 &larb2 - &larb3 &larb6>; - #iommu-cells = <1>; - }; - - apmixedsys: syscon@10209000 { - compatible = "mediatek,mt2712-apmixedsys", "syscon"; - reg = <0 0x10209000 0 0x1000>; - #clock-cells = <1>; - }; - - iommu1: iommu@1020a000 { - compatible = "mediatek,mt2712-m4u"; - reg = <0 0x1020a000 0 0x1000>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_M4U>; - clock-names = "bclk"; - mediatek,larbs = <&larb4 &larb5 &larb7>; - #iommu-cells = <1>; - }; - - mcucfg: syscon@10220000 { - compatible = "mediatek,mt2712-mcucfg", "syscon"; - reg = <0 0x10220000 0 0x1000>; - #clock-cells = <1>; - }; - - sysirq: interrupt-controller@10220a80 { - compatible = "mediatek,mt2712-sysirq", - "mediatek,mt6577-sysirq"; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - reg = <0 0x10220a80 0 0x40>; - }; - - gic: interrupt-controller@10510000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - interrupt-controller; - reg = <0 0x10510000 0 0x10000>, - <0 0x10520000 0 0x20000>, - <0 0x10540000 0 0x20000>, - <0 0x10560000 0 0x20000>; - interrupts = ; - }; - - auxadc: adc@11001000 { - compatible = "mediatek,mt2712-auxadc"; - reg = <0 0x11001000 0 0x1000>; - clocks = <&pericfg CLK_PERI_AUXADC>; - clock-names = "main"; - #io-channel-cells = <1>; - status = "disabled"; - }; - - uart0: serial@11002000 { - compatible = "mediatek,mt2712-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11002000 0 0x400>; - interrupts = ; - clocks = <&baud_clk>, <&sys_clk>; - clock-names = "baud", "bus"; - status = "disabled"; - }; - - uart1: serial@11003000 { - compatible = "mediatek,mt2712-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11003000 0 0x400>; - interrupts = ; - clocks = <&baud_clk>, <&sys_clk>; - clock-names = "baud", "bus"; - status = "disabled"; - }; - - uart2: serial@11004000 { - compatible = "mediatek,mt2712-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11004000 0 0x400>; - interrupts = ; - clocks = <&baud_clk>, <&sys_clk>; - clock-names = "baud", "bus"; - status = "disabled"; - }; - - uart3: serial@11005000 { - compatible = "mediatek,mt2712-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11005000 0 0x400>; - interrupts = ; - clocks = <&baud_clk>, <&sys_clk>; - clock-names = "baud", "bus"; - status = "disabled"; - }; - - pwm: pwm@11006000 { - compatible = "mediatek,mt2712-pwm"; - reg = <0 0x11006000 0 0x1000>; - #pwm-cells = <2>; - interrupts = ; - clocks = <&topckgen CLK_TOP_PWM_SEL>, - <&pericfg CLK_PERI_PWM>, - <&pericfg CLK_PERI_PWM0>, - <&pericfg CLK_PERI_PWM1>, - <&pericfg CLK_PERI_PWM2>, - <&pericfg CLK_PERI_PWM3>, - <&pericfg CLK_PERI_PWM4>, - <&pericfg CLK_PERI_PWM5>, - <&pericfg CLK_PERI_PWM6>, - <&pericfg CLK_PERI_PWM7>; - clock-names = "top", - "main", - "pwm1", - "pwm2", - "pwm3", - "pwm4", - "pwm5", - "pwm6", - "pwm7", - "pwm8"; - status = "disabled"; - }; - - i2c0: i2c@11007000 { - compatible = "mediatek,mt2712-i2c"; - reg = <0 0x11007000 0 0x90>, - <0 0x11000180 0 0x80>; - interrupts = ; - clock-div = <4>; - clocks = <&pericfg CLK_PERI_I2C0>, - <&pericfg CLK_PERI_AP_DMA>; - clock-names = "main", - "dma"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c1: i2c@11008000 { - compatible = "mediatek,mt2712-i2c"; - reg = <0 0x11008000 0 0x90>, - <0 0x11000200 0 0x80>; - interrupts = ; - clock-div = <4>; - clocks = <&pericfg CLK_PERI_I2C1>, - <&pericfg CLK_PERI_AP_DMA>; - clock-names = "main", - "dma"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@11009000 { - compatible = "mediatek,mt2712-i2c"; - reg = <0 0x11009000 0 0x90>, - <0 0x11000280 0 0x80>; - interrupts = ; - clock-div = <4>; - clocks = <&pericfg CLK_PERI_I2C2>, - <&pericfg CLK_PERI_AP_DMA>; - clock-names = "main", - "dma"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi0: spi@1100a000 { - compatible = "mediatek,mt2712-spi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0 0x1100a000 0 0x100>; - interrupts = ; - clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>, - <&topckgen CLK_TOP_SPI_SEL>, - <&pericfg CLK_PERI_SPI0>; - clock-names = "parent-clk", "sel-clk", "spi-clk"; - status = "disabled"; - }; - - nandc: nfi@1100e000 { - compatible = "mediatek,mt2712-nfc"; - reg = <0 0x1100e000 0 0x1000>; - interrupts = ; - clocks = <&topckgen CLK_TOP_NFI2X_EN>, <&pericfg CLK_PERI_NFI>; - clock-names = "nfi_clk", "pad_clk"; - ecc-engine = <&bch>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - bch: ecc@1100f000 { - compatible = "mediatek,mt2712-ecc"; - reg = <0 0x1100f000 0 0x1000>; - interrupts = ; - clocks = <&topckgen CLK_TOP_NFI1X_CK_EN>; - clock-names = "nfiecc_clk"; - status = "disabled"; - }; - - i2c3: i2c@11010000 { - compatible = "mediatek,mt2712-i2c"; - reg = <0 0x11010000 0 0x90>, - <0 0x11000300 0 0x80>; - interrupts = ; - clock-div = <4>; - clocks = <&pericfg CLK_PERI_I2C3>, - <&pericfg CLK_PERI_AP_DMA>; - clock-names = "main", - "dma"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c4: i2c@11011000 { - compatible = "mediatek,mt2712-i2c"; - reg = <0 0x11011000 0 0x90>, - <0 0x11000380 0 0x80>; - interrupts = ; - clock-div = <4>; - clocks = <&pericfg CLK_PERI_I2C4>, - <&pericfg CLK_PERI_AP_DMA>; - clock-names = "main", - "dma"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c5: i2c@11013000 { - compatible = "mediatek,mt2712-i2c"; - reg = <0 0x11013000 0 0x90>, - <0 0x11000100 0 0x80>; - interrupts = ; - clock-div = <4>; - clocks = <&pericfg CLK_PERI_I2C5>, - <&pericfg CLK_PERI_AP_DMA>; - clock-names = "main", - "dma"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi2: spi@11015000 { - compatible = "mediatek,mt2712-spi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0 0x11015000 0 0x100>; - interrupts = ; - clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>, - <&topckgen CLK_TOP_SPI_SEL>, - <&pericfg CLK_PERI_SPI2>; - clock-names = "parent-clk", "sel-clk", "spi-clk"; - status = "disabled"; - }; - - spi3: spi@11016000 { - compatible = "mediatek,mt2712-spi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0 0x11016000 0 0x100>; - interrupts = ; - clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>, - <&topckgen CLK_TOP_SPI_SEL>, - <&pericfg CLK_PERI_SPI3>; - clock-names = "parent-clk", "sel-clk", "spi-clk"; - status = "disabled"; - }; - - spi4: spi@10012000 { - compatible = "mediatek,mt2712-spi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0 0x10012000 0 0x100>; - interrupts = ; - clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>, - <&topckgen CLK_TOP_SPI_SEL>, - <&infracfg CLK_INFRA_AO_SPI0>; - clock-names = "parent-clk", "sel-clk", "spi-clk"; - status = "disabled"; - }; - - spi5: spi@11018000 { - compatible = "mediatek,mt2712-spi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0 0x11018000 0 0x100>; - interrupts = ; - clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>, - <&topckgen CLK_TOP_SPI_SEL>, - <&pericfg CLK_PERI_SPI5>; - clock-names = "parent-clk", "sel-clk", "spi-clk"; - status = "disabled"; - }; - - uart4: serial@11019000 { - compatible = "mediatek,mt2712-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11019000 0 0x400>; - interrupts = ; - clocks = <&baud_clk>, <&sys_clk>; - clock-names = "baud", "bus"; - status = "disabled"; - }; - - mmc0: mmc@11230000 { - compatible = "mediatek,mt2712-mmc"; - reg = <0 0x11230000 0 0x1000>; - interrupts = ; - clocks = <&pericfg CLK_PERI_MSDC30_0>, - <&pericfg CLK_PERI_MSDC50_0_HCLK_EN>, - <&pericfg CLK_PERI_MSDC30_0_QTR_EN>, - <&pericfg CLK_PERI_MSDC50_0_EN>; - clock-names = "source", "hclk", "bus_clk", "source_cg"; - status = "disabled"; - }; - - mmc1: mmc@11240000 { - compatible = "mediatek,mt2712-mmc"; - reg = <0 0x11240000 0 0x1000>; - interrupts = ; - clocks = <&pericfg CLK_PERI_MSDC30_1>, - <&topckgen CLK_TOP_AXI_SEL>, - <&pericfg CLK_PERI_MSDC30_1_EN>; - clock-names = "source", "hclk", "source_cg"; - status = "disabled"; - }; - - mmc2: mmc@11250000 { - compatible = "mediatek,mt2712-mmc"; - reg = <0 0x11250000 0 0x1000>; - interrupts = ; - clocks = <&pericfg CLK_PERI_MSDC30_2>, - <&topckgen CLK_TOP_AXI_SEL>, - <&pericfg CLK_PERI_MSDC30_2_EN>; - clock-names = "source", "hclk", "source_cg"; - status = "disabled"; - }; - - ssusb: usb@11271000 { - compatible = "mediatek,mt2712-mtu3", "mediatek,mtu3"; - reg = <0 0x11271000 0 0x3000>, - <0 0x11280700 0 0x0100>; - reg-names = "mac", "ippc"; - interrupts = ; - phys = <&u2port0 PHY_TYPE_USB2>, - <&u2port1 PHY_TYPE_USB2>; - power-domains = <&scpsys MT2712_POWER_DOMAIN_USB>; - clocks = <&topckgen CLK_TOP_USB30_SEL>; - clock-names = "sys_ck"; - mediatek,syscon-wakeup = <&pericfg 0x510 2>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - status = "disabled"; - - usb_host0: xhci@11270000 { - compatible = "mediatek,mt2712-xhci", - "mediatek,mtk-xhci"; - reg = <0 0x11270000 0 0x1000>; - reg-names = "mac"; - interrupts = ; - power-domains = <&scpsys MT2712_POWER_DOMAIN_USB>; - clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>; - clock-names = "sys_ck", "ref_ck"; - status = "disabled"; - }; - }; - - u3phy0: usb-phy@11290000 { - compatible = "mediatek,mt2712-u3phy"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - status = "okay"; - - u2port0: usb-phy@11290000 { - reg = <0 0x11290000 0 0x700>; - clocks = <&clk26m>; - clock-names = "ref"; - #phy-cells = <1>; - status = "okay"; - }; - - u2port1: usb-phy@11298000 { - reg = <0 0x11298000 0 0x700>; - clocks = <&clk26m>; - clock-names = "ref"; - #phy-cells = <1>; - status = "okay"; - }; - - u3port0: usb-phy@11298700 { - reg = <0 0x11298700 0 0x900>; - clocks = <&clk26m>; - clock-names = "ref"; - #phy-cells = <1>; - status = "okay"; - }; - }; - - ssusb1: usb@112c1000 { - compatible = "mediatek,mt2712-mtu3", "mediatek,mtu3"; - reg = <0 0x112c1000 0 0x3000>, - <0 0x112d0700 0 0x0100>; - reg-names = "mac", "ippc"; - interrupts = ; - phys = <&u2port2 PHY_TYPE_USB2>, - <&u2port3 PHY_TYPE_USB2>, - <&u3port1 PHY_TYPE_USB3>; - power-domains = <&scpsys MT2712_POWER_DOMAIN_USB2>; - clocks = <&topckgen CLK_TOP_USB30_SEL>; - clock-names = "sys_ck"; - mediatek,syscon-wakeup = <&pericfg 0x514 2>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - status = "disabled"; - - usb_host1: xhci@112c0000 { - compatible = "mediatek,mt2712-xhci", - "mediatek,mtk-xhci"; - reg = <0 0x112c0000 0 0x1000>; - reg-names = "mac"; - interrupts = ; - power-domains = <&scpsys MT2712_POWER_DOMAIN_USB2>; - clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>; - clock-names = "sys_ck", "ref_ck"; - status = "disabled"; - }; - }; - - u3phy1: usb-phy@112e0000 { - compatible = "mediatek,mt2712-u3phy"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - status = "okay"; - - u2port2: usb-phy@112e0000 { - reg = <0 0x112e0000 0 0x700>; - clocks = <&clk26m>; - clock-names = "ref"; - #phy-cells = <1>; - status = "okay"; - }; - - u2port3: usb-phy@112e8000 { - reg = <0 0x112e8000 0 0x700>; - clocks = <&clk26m>; - clock-names = "ref"; - #phy-cells = <1>; - status = "okay"; - }; - - u3port1: usb-phy@112e8700 { - reg = <0 0x112e8700 0 0x900>; - clocks = <&clk26m>; - clock-names = "ref"; - #phy-cells = <1>; - status = "okay"; - }; - }; - - pcie: pcie@11700000 { - compatible = "mediatek,mt2712-pcie"; - device_type = "pci"; - reg = <0 0x11700000 0 0x1000>, - <0 0x112ff000 0 0x1000>; - reg-names = "port0", "port1"; - #address-cells = <3>; - #size-cells = <2>; - interrupts = , - ; - clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>, - <&topckgen CLK_TOP_PE2_MAC_P1_SEL>, - <&pericfg CLK_PERI_PCIE0>, - <&pericfg CLK_PERI_PCIE1>; - clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1"; - phys = <&u3port0 PHY_TYPE_PCIE>, <&u3port1 PHY_TYPE_PCIE>; - phy-names = "pcie-phy0", "pcie-phy1"; - bus-range = <0x00 0xff>; - ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>; - - pcie0: pcie@0,0 { - device_type = "pci"; - status = "disabled"; - reg = <0x0000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie_intc0 0>, - <0 0 0 2 &pcie_intc0 1>, - <0 0 0 3 &pcie_intc0 2>, - <0 0 0 4 &pcie_intc0 3>; - pcie_intc0: interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - }; - }; - - pcie1: pcie@1,0 { - device_type = "pci"; - status = "disabled"; - reg = <0x0800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie_intc1 0>, - <0 0 0 2 &pcie_intc1 1>, - <0 0 0 3 &pcie_intc1 2>, - <0 0 0 4 &pcie_intc1 3>; - pcie_intc1: interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - }; - }; - }; - - mfgcfg: syscon@13000000 { - compatible = "mediatek,mt2712-mfgcfg", "syscon"; - reg = <0 0x13000000 0 0x1000>; - #clock-cells = <1>; - }; - - mmsys: syscon@14000000 { - compatible = "mediatek,mt2712-mmsys", "syscon"; - reg = <0 0x14000000 0 0x1000>; - #clock-cells = <1>; - }; - - larb0: larb@14021000 { - compatible = "mediatek,mt2712-smi-larb"; - reg = <0 0x14021000 0 0x1000>; - mediatek,smi = <&smi_common0>; - mediatek,larb-id = <0>; - power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>; - clocks = <&mmsys CLK_MM_SMI_LARB0>, - <&mmsys CLK_MM_SMI_LARB0>; - clock-names = "apb", "smi"; - }; - - smi_common0: smi@14022000 { - compatible = "mediatek,mt2712-smi-common"; - reg = <0 0x14022000 0 0x1000>; - power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>; - clocks = <&mmsys CLK_MM_SMI_COMMON>, - <&mmsys CLK_MM_SMI_COMMON>; - clock-names = "apb", "smi"; - }; - - larb4: larb@14027000 { - compatible = "mediatek,mt2712-smi-larb"; - reg = <0 0x14027000 0 0x1000>; - mediatek,smi = <&smi_common1>; - mediatek,larb-id = <4>; - power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>; - clocks = <&mmsys CLK_MM_SMI_LARB4>, - <&mmsys CLK_MM_SMI_LARB4>; - clock-names = "apb", "smi"; - }; - - larb5: larb@14030000 { - compatible = "mediatek,mt2712-smi-larb"; - reg = <0 0x14030000 0 0x1000>; - mediatek,smi = <&smi_common1>; - mediatek,larb-id = <5>; - power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>; - clocks = <&mmsys CLK_MM_SMI_LARB5>, - <&mmsys CLK_MM_SMI_LARB5>; - clock-names = "apb", "smi"; - }; - - smi_common1: smi@14031000 { - compatible = "mediatek,mt2712-smi-common"; - reg = <0 0x14031000 0 0x1000>; - power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>; - clocks = <&mmsys CLK_MM_SMI_COMMON1>, - <&mmsys CLK_MM_SMI_COMMON1>; - clock-names = "apb", "smi"; - }; - - larb7: larb@14032000 { - compatible = "mediatek,mt2712-smi-larb"; - reg = <0 0x14032000 0 0x1000>; - mediatek,smi = <&smi_common1>; - mediatek,larb-id = <7>; - power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>; - clocks = <&mmsys CLK_MM_SMI_LARB7>, - <&mmsys CLK_MM_SMI_LARB7>; - clock-names = "apb", "smi"; - }; - - imgsys: syscon@15000000 { - compatible = "mediatek,mt2712-imgsys", "syscon"; - reg = <0 0x15000000 0 0x1000>; - #clock-cells = <1>; - }; - - larb2: larb@15001000 { - compatible = "mediatek,mt2712-smi-larb"; - reg = <0 0x15001000 0 0x1000>; - mediatek,smi = <&smi_common0>; - mediatek,larb-id = <2>; - power-domains = <&scpsys MT2712_POWER_DOMAIN_ISP>; - clocks = <&imgsys CLK_IMG_SMI_LARB2>, - <&imgsys CLK_IMG_SMI_LARB2>; - clock-names = "apb", "smi"; - }; - - bdpsys: syscon@15010000 { - compatible = "mediatek,mt2712-bdpsys", "syscon"; - reg = <0 0x15010000 0 0x1000>; - #clock-cells = <1>; - }; - - vdecsys: syscon@16000000 { - compatible = "mediatek,mt2712-vdecsys", "syscon"; - reg = <0 0x16000000 0 0x1000>; - #clock-cells = <1>; - }; - - larb1: larb@16010000 { - compatible = "mediatek,mt2712-smi-larb"; - reg = <0 0x16010000 0 0x1000>; - mediatek,smi = <&smi_common0>; - mediatek,larb-id = <1>; - power-domains = <&scpsys MT2712_POWER_DOMAIN_VDEC>; - clocks = <&vdecsys CLK_VDEC_CKEN>, - <&vdecsys CLK_VDEC_LARB1_CKEN>; - clock-names = "apb", "smi"; - }; - - vencsys: syscon@18000000 { - compatible = "mediatek,mt2712-vencsys", "syscon"; - reg = <0 0x18000000 0 0x1000>; - #clock-cells = <1>; - }; - - larb3: larb@18001000 { - compatible = "mediatek,mt2712-smi-larb"; - reg = <0 0x18001000 0 0x1000>; - mediatek,smi = <&smi_common0>; - mediatek,larb-id = <3>; - power-domains = <&scpsys MT2712_POWER_DOMAIN_VENC>; - clocks = <&vencsys CLK_VENC_SMI_COMMON_CON>, - <&vencsys CLK_VENC_VENC>; - clock-names = "apb", "smi"; - }; - - larb6: larb@18002000 { - compatible = "mediatek,mt2712-smi-larb"; - reg = <0 0x18002000 0 0x1000>; - mediatek,smi = <&smi_common0>; - mediatek,larb-id = <6>; - power-domains = <&scpsys MT2712_POWER_DOMAIN_VENC>; - clocks = <&vencsys CLK_VENC_SMI_COMMON_CON>, - <&vencsys CLK_VENC_VENC>; - clock-names = "apb", "smi"; - }; - - jpgdecsys: syscon@19000000 { - compatible = "mediatek,mt2712-jpgdecsys", "syscon"; - reg = <0 0x19000000 0 0x1000>; - #clock-cells = <1>; - }; -}; - diff --git a/sys/gnu/dts/arm64/mediatek/mt6380.dtsi b/sys/gnu/dts/arm64/mediatek/mt6380.dtsi deleted file mode 100644 index 53b335d2de5..00000000000 --- a/sys/gnu/dts/arm64/mediatek/mt6380.dtsi +++ /dev/null @@ -1,86 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * dts file for MediaTek MT6380 regulator - * - * Copyright (c) 2018 MediaTek Inc. - * Author: Chenglin Xu - * Sean Wang - */ - -&pwrap { - regulators { - compatible = "mediatek,mt6380-regulator"; - - mt6380_vcpu_reg: buck-vcore1 { - regulator-name = "vcore1"; - regulator-min-microvolt = < 600000>; - regulator-max-microvolt = <1393750>; - regulator-ramp-delay = <6250>; - regulator-always-on; - regulator-boot-on; - }; - - mt6380_vcore_reg: buck-vcore { - regulator-name = "vcore"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1393750>; - regulator-ramp-delay = <6250>; - regulator-always-on; - regulator-boot-on; - }; - - mt6380_vrf_reg: buck-vrf { - regulator-name = "vrf"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1575000>; - regulator-ramp-delay = <0>; - regulator-always-on; - regulator-boot-on; - }; - - mt6380_vm_reg: ldo-vm { - regulator-name = "vm"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1400000>; - regulator-ramp-delay = <0>; - regulator-always-on; - regulator-boot-on; - }; - - mt6380_va_reg: ldo-va { - regulator-name = "va"; - regulator-min-microvolt = <2200000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <0>; - regulator-always-on; - regulator-boot-on; - }; - - mt6380_vphy_reg: ldo-vphy { - regulator-name = "vphy"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-ramp-delay = <0>; - regulator-always-on; - regulator-boot-on; - }; - - mt6380_vddr_reg: ldo-vddr { - regulator-name = "vddr"; - regulator-min-microvolt = <1240000>; - regulator-max-microvolt = <1840000>; - regulator-ramp-delay = <0>; - regulator-always-on; - regulator-boot-on; - }; - - mt6380_vt_reg: ldo-vt { - regulator-name = "vt"; - regulator-min-microvolt = <2200000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <0>; - regulator-always-on; - regulator-boot-on; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/mediatek/mt6755-evb.dts b/sys/gnu/dts/arm64/mediatek/mt6755-evb.dts deleted file mode 100644 index e079b7932ba..00000000000 --- a/sys/gnu/dts/arm64/mediatek/mt6755-evb.dts +++ /dev/null @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2016 MediaTek Inc. - * Author: Mars.C - */ - -/dts-v1/; -#include "mt6755.dtsi" - -/ { - model = "MediaTek MT6755 EVB"; - compatible = "mediatek,mt6755-evb", "mediatek,mt6755"; - - aliases { - serial0 = &uart0; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0 0x40000000 0 0x1e800000>; - }; - - chosen { - stdout-path = "serial0:921600n8"; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/mediatek/mt6755.dtsi b/sys/gnu/dts/arm64/mediatek/mt6755.dtsi deleted file mode 100644 index 01ba7766971..00000000000 --- a/sys/gnu/dts/arm64/mediatek/mt6755.dtsi +++ /dev/null @@ -1,145 +0,0 @@ -/* - * Copyright (c) 2016 MediaTek Inc. - * Author: Mars.C - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include - -/ { - compatible = "mediatek,mt6755"; - interrupt-parent = <&sysirq>; - #address-cells = <2>; - #size-cells = <2>; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x000>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x001>; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x002>; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x003>; - }; - - cpu4: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x100>; - }; - - cpu5: cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x101>; - }; - - cpu6: cpu@102 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x102>; - }; - - cpu7: cpu@103 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x103>; - }; - }; - - uart_clk: dummy26m { - compatible = "fixed-clock"; - clock-frequency = <26000000>; - #clock-cells = <0>; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupt-parent = <&gic>; - interrupts = , - , - , - ; - }; - - sysirq: intpol-controller@10200620 { - compatible = "mediatek,mt6755-sysirq", - "mediatek,mt6577-sysirq"; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - reg = <0 0x10200620 0 0x20>; - }; - - gic: interrupt-controller@10231000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - interrupt-controller; - reg = <0 0x10231000 0 0x1000>, - <0 0x10232000 0 0x2000>, - <0 0x10234000 0 0x2000>, - <0 0x10236000 0 0x2000>; - }; - - uart0: serial@11002000 { - compatible = "mediatek,mt6755-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11002000 0 0x400>; - interrupts = ; - clocks = <&uart_clk>; - status = "disabled"; - }; - - uart1: serial@11003000 { - compatible = "mediatek,mt6755-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11003000 0 0x400>; - interrupts = ; - clocks = <&uart_clk>; - status = "disabled"; - }; -}; diff --git a/sys/gnu/dts/arm64/mediatek/mt6795-evb.dts b/sys/gnu/dts/arm64/mediatek/mt6795-evb.dts deleted file mode 100644 index 1ed2f81edef..00000000000 --- a/sys/gnu/dts/arm64/mediatek/mt6795-evb.dts +++ /dev/null @@ -1,33 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2015 MediaTek Inc. - * Author: Mars.C - */ - -/dts-v1/; -#include "mt6795.dtsi" - -/ { - model = "MediaTek MT6795 Evaluation Board"; - compatible = "mediatek,mt6795-evb", "mediatek,mt6795"; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0 0x40000000 0 0x1e800000>; - }; - - chosen { - stdout-path = "serial0:921600n8"; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/mediatek/mt6795.dtsi b/sys/gnu/dts/arm64/mediatek/mt6795.dtsi deleted file mode 100644 index c85659d0ff5..00000000000 --- a/sys/gnu/dts/arm64/mediatek/mt6795.dtsi +++ /dev/null @@ -1,175 +0,0 @@ -/* - * Copyright (c) 2015 MediaTek Inc. - * Author: Mars.C - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include - -/ { - compatible = "mediatek,mt6795"; - interrupt-parent = <&sysirq>; - #address-cells = <2>; - #size-cells = <2>; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x000>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x001>; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x002>; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x003>; - }; - - cpu4: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x100>; - }; - - cpu5: cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x101>; - }; - - cpu6: cpu@102 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x102>; - }; - - cpu7: cpu@103 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x103>; - }; - }; - - system_clk: dummy13m { - compatible = "fixed-clock"; - clock-frequency = <13000000>; - #clock-cells = <0>; - }; - - rtc_clk: dummy32k { - compatible = "fixed-clock"; - clock-frequency = <32000>; - #clock-cells = <0>; - }; - - uart_clk: dummy26m { - compatible = "fixed-clock"; - clock-frequency = <26000000>; - #clock-cells = <0>; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupt-parent = <&gic>; - interrupts = , - , - , - ; - }; - - sysirq: intpol-controller@10200620 { - compatible = "mediatek,mt6795-sysirq", - "mediatek,mt6577-sysirq"; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - reg = <0 0x10200620 0 0x20>; - }; - - gic: interrupt-controller@10221000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - interrupt-controller; - reg = <0 0x10221000 0 0x1000>, - <0 0x10222000 0 0x2000>, - <0 0x10224000 0 0x2000>, - <0 0x10226000 0 0x2000>; - }; - - uart0: serial@11002000 { - compatible = "mediatek,mt6795-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11002000 0 0x400>; - interrupts = ; - clocks = <&uart_clk>; - status = "disabled"; - }; - - uart1: serial@11003000 { - compatible = "mediatek,mt6795-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11003000 0 0x400>; - interrupts = ; - clocks = <&uart_clk>; - status = "disabled"; - }; - - uart2: serial@11004000 { - compatible = "mediatek,mt6795-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11004000 0 0x400>; - interrupts = ; - clocks = <&uart_clk>; - status = "disabled"; - }; - - uart3: serial@11005000 { - compatible = "mediatek,mt6795-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11005000 0 0x400>; - interrupts = ; - clocks = <&uart_clk>; - status = "disabled"; - }; -}; diff --git a/sys/gnu/dts/arm64/mediatek/mt6797-evb.dts b/sys/gnu/dts/arm64/mediatek/mt6797-evb.dts deleted file mode 100644 index 2327e752d16..00000000000 --- a/sys/gnu/dts/arm64/mediatek/mt6797-evb.dts +++ /dev/null @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2017 MediaTek Inc. - * Author: Mars.C - */ - -/dts-v1/; -#include "mt6797.dtsi" - -/ { - model = "MediaTek MT6797 Evaluation Board"; - compatible = "mediatek,mt6797-evb", "mediatek,mt6797"; - - aliases { - serial0 = &uart0; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0 0x40000000 0 0x1e800000>; - }; - - chosen {}; -}; - -&uart0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; -}; diff --git a/sys/gnu/dts/arm64/mediatek/mt6797-x20-dev.dts b/sys/gnu/dts/arm64/mediatek/mt6797-x20-dev.dts deleted file mode 100644 index 13939d55b85..00000000000 --- a/sys/gnu/dts/arm64/mediatek/mt6797-x20-dev.dts +++ /dev/null @@ -1,35 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for MediaTek X20 Development Board - * - * Copyright (C) 2018, Linaro Ltd. - * - */ - -/dts-v1/; - -#include "mt6797.dtsi" - -/ { - model = "Mediatek X20 Development Board"; - compatible = "archermind,mt6797-x20-dev", "mediatek,mt6797"; - - aliases { - serial0 = &uart1; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0 0x40000000 0 0x80000000>; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&uart1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins_a>; -}; diff --git a/sys/gnu/dts/arm64/mediatek/mt6797.dtsi b/sys/gnu/dts/arm64/mediatek/mt6797.dtsi deleted file mode 100644 index 2b2a69c7567..00000000000 --- a/sys/gnu/dts/arm64/mediatek/mt6797.dtsi +++ /dev/null @@ -1,270 +0,0 @@ -/* - * Copyright (c) 2017 MediaTek Inc. - * Author: Mars.C - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include - -/ { - compatible = "mediatek,mt6797"; - interrupt-parent = <&sysirq>; - #address-cells = <2>; - #size-cells = <2>; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x000>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x001>; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x002>; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x003>; - }; - - cpu4: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x100>; - }; - - cpu5: cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x101>; - }; - - cpu6: cpu@102 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x102>; - }; - - cpu7: cpu@103 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x103>; - }; - - cpu8: cpu@200 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - enable-method = "psci"; - reg = <0x200>; - }; - - cpu9: cpu@201 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - enable-method = "psci"; - reg = <0x201>; - }; - }; - - clk26m: oscillator@0 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <26000000>; - clock-output-names = "clk26m"; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupt-parent = <&gic>; - interrupts = , - , - , - ; - }; - - topckgen: topckgen@10000000 { - compatible = "mediatek,mt6797-topckgen"; - reg = <0 0x10000000 0 0x1000>; - #clock-cells = <1>; - }; - - infrasys: infracfg_ao@10001000 { - compatible = "mediatek,mt6797-infracfg", "syscon"; - reg = <0 0x10001000 0 0x1000>; - #clock-cells = <1>; - }; - - pio: pinctrl@10005000 { - compatible = "mediatek,mt6797-pinctrl"; - reg = <0 0x10005000 0 0x1000>, - <0 0x10002000 0 0x400>, - <0 0x10002400 0 0x400>, - <0 0x10002800 0 0x400>, - <0 0x10002C00 0 0x400>; - reg-names = "gpio", "iocfgl", "iocfgb", - "iocfgr", "iocfgt"; - gpio-controller; - #gpio-cells = <2>; - - uart0_pins_a: uart0 { - pins0 { - pinmux = , - ; - }; - }; - - uart1_pins_a: uart1 { - pins1 { - pinmux = , - ; - }; - }; - }; - - scpsys: scpsys@10006000 { - compatible = "mediatek,mt6797-scpsys"; - #power-domain-cells = <1>; - reg = <0 0x10006000 0 0x1000>; - clocks = <&topckgen CLK_TOP_MUX_MFG>, - <&topckgen CLK_TOP_MUX_MM>, - <&topckgen CLK_TOP_MUX_VDEC>; - clock-names = "mfg", "mm", "vdec"; - infracfg = <&infrasys>; - }; - - watchdog: watchdog@10007000 { - compatible = "mediatek,mt6797-wdt", "mediatek,mt6589-wdt"; - reg = <0 0x10007000 0 0x100>; - }; - - apmixedsys: apmixed@1000c000 { - compatible = "mediatek,mt6797-apmixedsys"; - reg = <0 0x1000c000 0 0x1000>; - #clock-cells = <1>; - }; - - sysirq: intpol-controller@10200620 { - compatible = "mediatek,mt6797-sysirq", - "mediatek,mt6577-sysirq"; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - reg = <0 0x10220620 0 0x20>, - <0 0x10220690 0 0x10>; - }; - - uart0: serial@11002000 { - compatible = "mediatek,mt6797-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11002000 0 0x400>; - interrupts = ; - clocks = <&infrasys CLK_INFRA_UART0>, - <&infrasys CLK_INFRA_AP_DMA>; - clock-names = "baud", "bus"; - status = "disabled"; - }; - - uart1: serial@11003000 { - compatible = "mediatek,mt6797-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11003000 0 0x400>; - interrupts = ; - clocks = <&infrasys CLK_INFRA_UART1>, - <&infrasys CLK_INFRA_AP_DMA>; - clock-names = "baud", "bus"; - status = "disabled"; - }; - - uart2: serial@11004000 { - compatible = "mediatek,mt6797-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11004000 0 0x400>; - interrupts = ; - clocks = <&infrasys CLK_INFRA_UART2>, - <&infrasys CLK_INFRA_AP_DMA>; - clock-names = "baud", "bus"; - status = "disabled"; - }; - - uart3: serial@11005000 { - compatible = "mediatek,mt6797-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11005000 0 0x400>; - interrupts = ; - clocks = <&infrasys CLK_INFRA_UART3>, - <&infrasys CLK_INFRA_AP_DMA>; - clock-names = "baud", "bus"; - status = "disabled"; - }; - - mmsys: mmsys_config@14000000 { - compatible = "mediatek,mt6797-mmsys", "syscon"; - reg = <0 0x14000000 0 0x1000>; - #clock-cells = <1>; - }; - - imgsys: imgsys_config@15000000 { - compatible = "mediatek,mt6797-imgsys", "syscon"; - reg = <0 0x15000000 0 0x1000>; - #clock-cells = <1>; - }; - - vdecsys: vdec_gcon@16000000 { - compatible = "mediatek,mt6797-vdecsys", "syscon"; - reg = <0 0x16000000 0 0x10000>; - #clock-cells = <1>; - }; - - vencsys: venc_gcon@17000000 { - compatible = "mediatek,mt6797-vencsys", "syscon"; - reg = <0 0x17000000 0 0x1000>; - #clock-cells = <1>; - }; - - gic: interrupt-controller@19000000 { - compatible = "arm,gic-v3"; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - interrupts = ; - interrupt-controller; - reg = <0 0x19000000 0 0x10000>, /* GICD */ - <0 0x19200000 0 0x200000>, /* GICR */ - <0 0x10240000 0 0x2000>; /* GICC */ - }; -}; diff --git a/sys/gnu/dts/arm64/mediatek/mt7622-bananapi-bpi-r64.dts b/sys/gnu/dts/arm64/mediatek/mt7622-bananapi-bpi-r64.dts deleted file mode 100644 index 83e10591e0e..00000000000 --- a/sys/gnu/dts/arm64/mediatek/mt7622-bananapi-bpi-r64.dts +++ /dev/null @@ -1,545 +0,0 @@ -/* - * Copyright (c) 2018 MediaTek Inc. - * Author: Ryder Lee - * - * SPDX-License-Identifier: (GPL-2.0 OR MIT) - */ - -/dts-v1/; -#include -#include - -#include "mt7622.dtsi" -#include "mt6380.dtsi" - -/ { - model = "Bananapi BPI-R64"; - compatible = "bananapi,bpi-r64", "mediatek,mt7622"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512"; - }; - - cpus { - cpu@0 { - proc-supply = <&mt6380_vcpu_reg>; - sram-supply = <&mt6380_vm_reg>; - }; - - cpu@1 { - proc-supply = <&mt6380_vcpu_reg>; - sram-supply = <&mt6380_vm_reg>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - factory { - label = "factory"; - linux,code = ; - gpios = <&pio 0 GPIO_ACTIVE_HIGH>; - }; - - wps { - label = "wps"; - linux,code = ; - gpios = <&pio 102 GPIO_ACTIVE_HIGH>; - }; - }; - - leds { - compatible = "gpio-leds"; - - green { - label = "bpi-r64:pio:green"; - gpios = <&pio 89 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - red { - label = "bpi-r64:pio:red"; - gpios = <&pio 88 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - - memory { - reg = <0 0x40000000 0 0x40000000>; - }; - - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-name = "fixed-1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_5v: regulator-5v { - compatible = "regulator-fixed"; - regulator-name = "fixed-5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - regulator-always-on; - }; -}; - -&bch { - status = "disabled"; -}; - -&btif { - status = "okay"; -}; - -&cir { - pinctrl-names = "default"; - pinctrl-0 = <&irrx_pins>; - status = "okay"; -}; - -ð { - status = "okay"; - gmac0: mac@0 { - compatible = "mediatek,eth-mac"; - reg = <0>; - phy-mode = "2500base-x"; - - fixed-link { - speed = <2500>; - full-duplex; - pause; - }; - }; - - gmac1: mac@1 { - compatible = "mediatek,eth-mac"; - reg = <1>; - phy-mode = "rgmii"; - - fixed-link { - speed = <1000>; - full-duplex; - pause; - }; - }; - - mdio: mdio-bus { - #address-cells = <1>; - #size-cells = <0>; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - status = "okay"; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - status = "okay"; -}; - -&mmc0 { - pinctrl-names = "default", "state_uhs"; - pinctrl-0 = <&emmc_pins_default>; - pinctrl-1 = <&emmc_pins_uhs>; - status = "okay"; - bus-width = <8>; - max-frequency = <50000000>; - cap-mmc-highspeed; - mmc-hs200-1_8v; - vmmc-supply = <®_3p3v>; - vqmmc-supply = <®_1p8v>; - assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>; - non-removable; -}; - -&mmc1 { - pinctrl-names = "default", "state_uhs"; - pinctrl-0 = <&sd0_pins_default>; - pinctrl-1 = <&sd0_pins_uhs>; - status = "okay"; - bus-width = <4>; - max-frequency = <50000000>; - cap-sd-highspeed; - r_smpl = <1>; - cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_3p3v>; - vqmmc-supply = <®_3p3v>; - assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>; -}; - -&nandc { - pinctrl-names = "default"; - pinctrl-0 = <¶llel_nand_pins>; - status = "disabled"; -}; - -&nor_flash { - pinctrl-names = "default"; - pinctrl-0 = <&spi_nor_pins>; - status = "disabled"; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - }; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>; - status = "okay"; - - pcie@0,0 { - status = "okay"; - }; - - pcie@1,0 { - status = "okay"; - }; -}; - -&pio { - /* Attention: GPIO 90 is used to switch between PCIe@1,0 and - * SATA functions. i.e. output-high: PCIe, output-low: SATA - */ - asm_sel { - gpio-hog; - gpios = <90 GPIO_ACTIVE_HIGH>; - output-high; - }; - - /* eMMC is shared pin with parallel NAND */ - emmc_pins_default: emmc-pins-default { - mux { - function = "emmc", "emmc_rst"; - groups = "emmc"; - }; - - /* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7", - * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4, - * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively - */ - conf-cmd-dat { - pins = "NDL0", "NDL1", "NDL2", - "NDL3", "NDL4", "NDL5", - "NDL6", "NDL7", "NRB"; - input-enable; - bias-pull-up; - }; - - conf-clk { - pins = "NCLE"; - bias-pull-down; - }; - }; - - emmc_pins_uhs: emmc-pins-uhs { - mux { - function = "emmc"; - groups = "emmc"; - }; - - conf-cmd-dat { - pins = "NDL0", "NDL1", "NDL2", - "NDL3", "NDL4", "NDL5", - "NDL6", "NDL7", "NRB"; - input-enable; - drive-strength = <4>; - bias-pull-up; - }; - - conf-clk { - pins = "NCLE"; - drive-strength = <4>; - bias-pull-down; - }; - }; - - eth_pins: eth-pins { - mux { - function = "eth"; - groups = "mdc_mdio", "rgmii_via_gmac2"; - }; - }; - - i2c1_pins: i2c1-pins { - mux { - function = "i2c"; - groups = "i2c1_0"; - }; - }; - - i2c2_pins: i2c2-pins { - mux { - function = "i2c"; - groups = "i2c2_0"; - }; - }; - - i2s1_pins: i2s1-pins { - mux { - function = "i2s"; - groups = "i2s_out_mclk_bclk_ws", - "i2s1_in_data", - "i2s1_out_data"; - }; - - conf { - pins = "I2S1_IN", "I2S1_OUT", "I2S_BCLK", - "I2S_WS", "I2S_MCLK"; - drive-strength = <12>; - bias-pull-down; - }; - }; - - irrx_pins: irrx-pins { - mux { - function = "ir"; - groups = "ir_1_rx"; - }; - }; - - irtx_pins: irtx-pins { - mux { - function = "ir"; - groups = "ir_1_tx"; - }; - }; - - /* Parallel nand is shared pin with eMMC */ - parallel_nand_pins: parallel-nand-pins { - mux { - function = "flash"; - groups = "par_nand"; - }; - }; - - pcie0_pins: pcie0-pins { - mux { - function = "pcie"; - groups = "pcie0_pad_perst", - "pcie0_1_waken", - "pcie0_1_clkreq"; - }; - }; - - pcie1_pins: pcie1-pins { - mux { - function = "pcie"; - groups = "pcie1_pad_perst", - "pcie1_0_waken", - "pcie1_0_clkreq"; - }; - }; - - pmic_bus_pins: pmic-bus-pins { - mux { - function = "pmic"; - groups = "pmic_bus"; - }; - }; - - pwm7_pins: pwm1-2-pins { - mux { - function = "pwm"; - groups = "pwm_ch7_2"; - }; - }; - - wled_pins: wled-pins { - mux { - function = "led"; - groups = "wled"; - }; - }; - - sd0_pins_default: sd0-pins-default { - mux { - function = "sd"; - groups = "sd_0"; - }; - - /* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN", - * "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1, - * DAT2, DAT3, CMD, CLK for SD respectively. - */ - conf-cmd-data { - pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN", - "I2S2_IN","I2S4_OUT"; - input-enable; - drive-strength = <8>; - bias-pull-up; - }; - conf-clk { - pins = "I2S3_OUT"; - drive-strength = <12>; - bias-pull-down; - }; - conf-cd { - pins = "TXD3"; - bias-pull-up; - }; - }; - - sd0_pins_uhs: sd0-pins-uhs { - mux { - function = "sd"; - groups = "sd_0"; - }; - - conf-cmd-data { - pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN", - "I2S2_IN","I2S4_OUT"; - input-enable; - bias-pull-up; - }; - - conf-clk { - pins = "I2S3_OUT"; - bias-pull-down; - }; - }; - - /* Serial NAND is shared pin with SPI-NOR */ - serial_nand_pins: serial-nand-pins { - mux { - function = "flash"; - groups = "snfi"; - }; - }; - - spic0_pins: spic0-pins { - mux { - function = "spi"; - groups = "spic0_0"; - }; - }; - - spic1_pins: spic1-pins { - mux { - function = "spi"; - groups = "spic1_0"; - }; - }; - - /* SPI-NOR is shared pin with serial NAND */ - spi_nor_pins: spi-nor-pins { - mux { - function = "flash"; - groups = "spi_nor"; - }; - }; - - /* serial NAND is shared pin with SPI-NOR */ - serial_nand_pins: serial-nand-pins { - mux { - function = "flash"; - groups = "snfi"; - }; - }; - - uart0_pins: uart0-pins { - mux { - function = "uart"; - groups = "uart0_0_tx_rx" ; - }; - }; - - uart2_pins: uart2-pins { - mux { - function = "uart"; - groups = "uart2_1_tx_rx" ; - }; - }; - - watchdog_pins: watchdog-pins { - mux { - function = "watchdog"; - groups = "watchdog"; - }; - }; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm7_pins>; - status = "okay"; -}; - -&pwrap { - pinctrl-names = "default"; - pinctrl-0 = <&pmic_bus_pins>; - - status = "okay"; -}; - -&sata { - status = "disable"; -}; - -&sata_phy { - status = "disable"; -}; - -&spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spic0_pins>; - status = "okay"; -}; - -&spi1 { - pinctrl-names = "default"; - pinctrl-0 = <&spic1_pins>; - status = "okay"; -}; - -&ssusb { - vusb33-supply = <®_3p3v>; - vbus-supply = <®_5v>; - status = "okay"; -}; - -&u3phy { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; - status = "okay"; -}; - -&watchdog { - pinctrl-names = "default"; - pinctrl-0 = <&watchdog_pins>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/mediatek/mt7622-rfb1.dts b/sys/gnu/dts/arm64/mediatek/mt7622-rfb1.dts deleted file mode 100644 index 3f783348c66..00000000000 --- a/sys/gnu/dts/arm64/mediatek/mt7622-rfb1.dts +++ /dev/null @@ -1,508 +0,0 @@ -/* - * Copyright (c) 2017 MediaTek Inc. - * Author: Ming Huang - * Sean Wang - * - * SPDX-License-Identifier: (GPL-2.0 OR MIT) - */ - -/dts-v1/; -#include -#include - -#include "mt7622.dtsi" -#include "mt6380.dtsi" - -/ { - model = "MediaTek MT7622 RFB1 board"; - compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512"; - }; - - cpus { - cpu@0 { - proc-supply = <&mt6380_vcpu_reg>; - sram-supply = <&mt6380_vm_reg>; - }; - - cpu@1 { - proc-supply = <&mt6380_vcpu_reg>; - sram-supply = <&mt6380_vm_reg>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - poll-interval = <100>; - - factory { - label = "factory"; - linux,code = ; - gpios = <&pio 0 0>; - }; - - wps { - label = "wps"; - linux,code = ; - gpios = <&pio 102 0>; - }; - }; - - memory { - reg = <0 0x40000000 0 0x20000000>; - }; - - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-name = "fixed-1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_5v: regulator-5v { - compatible = "regulator-fixed"; - regulator-name = "fixed-5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - regulator-always-on; - }; -}; - -&bch { - status = "disabled"; -}; - -&btif { - status = "okay"; -}; - -&cir { - pinctrl-names = "default"; - pinctrl-0 = <&irrx_pins>; - status = "okay"; -}; - -ð { - pinctrl-names = "default"; - pinctrl-0 = <ð_pins>; - status = "okay"; - - gmac1: mac@1 { - compatible = "mediatek,eth-mac"; - reg = <1>; - phy-handle = <&phy5>; - }; - - mdio-bus { - #address-cells = <1>; - #size-cells = <0>; - - phy5: ethernet-phy@5 { - reg = <5>; - phy-mode = "sgmii"; - }; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - status = "okay"; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - status = "okay"; -}; - -&mmc0 { - pinctrl-names = "default", "state_uhs"; - pinctrl-0 = <&emmc_pins_default>; - pinctrl-1 = <&emmc_pins_uhs>; - status = "okay"; - bus-width = <8>; - max-frequency = <50000000>; - cap-mmc-highspeed; - mmc-hs200-1_8v; - vmmc-supply = <®_3p3v>; - vqmmc-supply = <®_1p8v>; - assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>; - non-removable; -}; - -&mmc1 { - pinctrl-names = "default", "state_uhs"; - pinctrl-0 = <&sd0_pins_default>; - pinctrl-1 = <&sd0_pins_uhs>; - status = "okay"; - bus-width = <4>; - max-frequency = <50000000>; - cap-sd-highspeed; - r_smpl = <1>; - cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_3p3v>; - vqmmc-supply = <®_3p3v>; - assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>; -}; - -&nandc { - pinctrl-names = "default"; - pinctrl-0 = <¶llel_nand_pins>; - status = "disabled"; -}; - -&nor_flash { - pinctrl-names = "default"; - pinctrl-0 = <&spi_nor_pins>; - status = "disabled"; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - }; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pcie0_pins>; - status = "okay"; - - pcie@0,0 { - status = "okay"; - }; -}; - -&pio { - /* eMMC is shared pin with parallel NAND */ - emmc_pins_default: emmc-pins-default { - mux { - function = "emmc", "emmc_rst"; - groups = "emmc"; - }; - - /* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7", - * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4, - * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively - */ - conf-cmd-dat { - pins = "NDL0", "NDL1", "NDL2", - "NDL3", "NDL4", "NDL5", - "NDL6", "NDL7", "NRB"; - input-enable; - bias-pull-up; - }; - - conf-clk { - pins = "NCLE"; - bias-pull-down; - }; - }; - - emmc_pins_uhs: emmc-pins-uhs { - mux { - function = "emmc"; - groups = "emmc"; - }; - - conf-cmd-dat { - pins = "NDL0", "NDL1", "NDL2", - "NDL3", "NDL4", "NDL5", - "NDL6", "NDL7", "NRB"; - input-enable; - drive-strength = <4>; - bias-pull-up; - }; - - conf-clk { - pins = "NCLE"; - drive-strength = <4>; - bias-pull-down; - }; - }; - - eth_pins: eth-pins { - mux { - function = "eth"; - groups = "mdc_mdio", "rgmii_via_gmac2"; - }; - }; - - i2c1_pins: i2c1-pins { - mux { - function = "i2c"; - groups = "i2c1_0"; - }; - }; - - i2c2_pins: i2c2-pins { - mux { - function = "i2c"; - groups = "i2c2_0"; - }; - }; - - i2s1_pins: i2s1-pins { - mux { - function = "i2s"; - groups = "i2s_out_mclk_bclk_ws", - "i2s1_in_data", - "i2s1_out_data"; - }; - - conf { - pins = "I2S1_IN", "I2S1_OUT", "I2S_BCLK", - "I2S_WS", "I2S_MCLK"; - drive-strength = <12>; - bias-pull-down; - }; - }; - - irrx_pins: irrx-pins { - mux { - function = "ir"; - groups = "ir_1_rx"; - }; - }; - - irtx_pins: irtx-pins { - mux { - function = "ir"; - groups = "ir_1_tx"; - }; - }; - - /* Parallel nand is shared pin with eMMC */ - parallel_nand_pins: parallel-nand-pins { - mux { - function = "flash"; - groups = "par_nand"; - }; - }; - - pcie0_pins: pcie0-pins { - mux { - function = "pcie"; - groups = "pcie0_pad_perst", - "pcie0_1_waken", - "pcie0_1_clkreq"; - }; - }; - - pcie1_pins: pcie1-pins { - mux { - function = "pcie"; - groups = "pcie1_pad_perst", - "pcie1_0_waken", - "pcie1_0_clkreq"; - }; - }; - - pmic_bus_pins: pmic-bus-pins { - mux { - function = "pmic"; - groups = "pmic_bus"; - }; - }; - - pwm7_pins: pwm1-2-pins { - mux { - function = "pwm"; - groups = "pwm_ch7_2"; - }; - }; - - wled_pins: wled-pins { - mux { - function = "led"; - groups = "wled"; - }; - }; - - sd0_pins_default: sd0-pins-default { - mux { - function = "sd"; - groups = "sd_0"; - }; - - /* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN", - * "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1, - * DAT2, DAT3, CMD, CLK for SD respectively. - */ - conf-cmd-data { - pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN", - "I2S2_IN","I2S4_OUT"; - input-enable; - drive-strength = <8>; - bias-pull-up; - }; - conf-clk { - pins = "I2S3_OUT"; - drive-strength = <12>; - bias-pull-down; - }; - conf-cd { - pins = "TXD3"; - bias-pull-up; - }; - }; - - sd0_pins_uhs: sd0-pins-uhs { - mux { - function = "sd"; - groups = "sd_0"; - }; - - conf-cmd-data { - pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN", - "I2S2_IN","I2S4_OUT"; - input-enable; - bias-pull-up; - }; - - conf-clk { - pins = "I2S3_OUT"; - bias-pull-down; - }; - }; - - /* Serial NAND is shared pin with SPI-NOR */ - serial_nand_pins: serial-nand-pins { - mux { - function = "flash"; - groups = "snfi"; - }; - }; - - spic0_pins: spic0-pins { - mux { - function = "spi"; - groups = "spic0_0"; - }; - }; - - spic1_pins: spic1-pins { - mux { - function = "spi"; - groups = "spic1_0"; - }; - }; - - /* SPI-NOR is shared pin with serial NAND */ - spi_nor_pins: spi-nor-pins { - mux { - function = "flash"; - groups = "spi_nor"; - }; - }; - - /* serial NAND is shared pin with SPI-NOR */ - serial_nand_pins: serial-nand-pins { - mux { - function = "flash"; - groups = "snfi"; - }; - }; - - uart0_pins: uart0-pins { - mux { - function = "uart"; - groups = "uart0_0_tx_rx" ; - }; - }; - - uart2_pins: uart2-pins { - mux { - function = "uart"; - groups = "uart2_1_tx_rx" ; - }; - }; - - watchdog_pins: watchdog-pins { - mux { - function = "watchdog"; - groups = "watchdog"; - }; - }; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm7_pins>; - status = "okay"; -}; - -&pwrap { - pinctrl-names = "default"; - pinctrl-0 = <&pmic_bus_pins>; - - status = "okay"; -}; - -&sata { - status = "okay"; -}; - -&sata_phy { - status = "okay"; -}; - -&spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spic0_pins>; - status = "okay"; -}; - -&spi1 { - pinctrl-names = "default"; - pinctrl-0 = <&spic1_pins>; - status = "okay"; -}; - -&ssusb { - vusb33-supply = <®_3p3v>; - vbus-supply = <®_5v>; - status = "okay"; -}; - -&u3phy { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; - status = "okay"; -}; - -&watchdog { - pinctrl-names = "default"; - pinctrl-0 = <&watchdog_pins>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/mediatek/mt7622.dtsi b/sys/gnu/dts/arm64/mediatek/mt7622.dtsi deleted file mode 100644 index dac51e98204..00000000000 --- a/sys/gnu/dts/arm64/mediatek/mt7622.dtsi +++ /dev/null @@ -1,935 +0,0 @@ -/* - * Copyright (c) 2017 MediaTek Inc. - * Author: Ming Huang - * Sean Wang - * - * SPDX-License-Identifier: (GPL-2.0 OR MIT) - */ - -#include -#include -#include -#include -#include -#include -#include - -/ { - compatible = "mediatek,mt7622"; - interrupt-parent = <&sysirq>; - #address-cells = <2>; - #size-cells = <2>; - - cpu_opp_table: opp-table { - compatible = "operating-points-v2"; - opp-shared; - opp-300000000 { - opp-hz = /bits/ 64 <30000000>; - opp-microvolt = <950000>; - }; - - opp-437500000 { - opp-hz = /bits/ 64 <437500000>; - opp-microvolt = <1000000>; - }; - - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <1050000>; - }; - - opp-812500000 { - opp-hz = /bits/ 64 <812500000>; - opp-microvolt = <1100000>; - }; - - opp-1025000000 { - opp-hz = /bits/ 64 <1025000000>; - opp-microvolt = <1150000>; - }; - - opp-1137500000 { - opp-hz = /bits/ 64 <1137500000>; - opp-microvolt = <1200000>; - }; - - opp-1262500000 { - opp-hz = /bits/ 64 <1262500000>; - opp-microvolt = <1250000>; - }; - - opp-1350000000 { - opp-hz = /bits/ 64 <1350000000>; - opp-microvolt = <1310000>; - }; - }; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x0>; - clocks = <&infracfg CLK_INFRA_MUX1_SEL>, - <&apmixedsys CLK_APMIXED_MAIN_CORE_EN>; - clock-names = "cpu", "intermediate"; - operating-points-v2 = <&cpu_opp_table>; - #cooling-cells = <2>; - enable-method = "psci"; - clock-frequency = <1300000000>; - cci-control-port = <&cci_control2>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x1>; - clocks = <&infracfg CLK_INFRA_MUX1_SEL>, - <&apmixedsys CLK_APMIXED_MAIN_CORE_EN>; - clock-names = "cpu", "intermediate"; - operating-points-v2 = <&cpu_opp_table>; - #cooling-cells = <2>; - enable-method = "psci"; - clock-frequency = <1300000000>; - cci-control-port = <&cci_control2>; - }; - }; - - pwrap_clk: dummy40m { - compatible = "fixed-clock"; - clock-frequency = <40000000>; - #clock-cells = <0>; - }; - - clk25m: oscillator { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - clock-output-names = "clkxtal"; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - pmu { - compatible = "arm,cortex-a53-pmu"; - interrupts = , - ; - interrupt-affinity = <&cpu0>, <&cpu1>; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ - secmon_reserved: secmon@43000000 { - reg = <0 0x43000000 0 0x30000>; - no-map; - }; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <1000>; - polling-delay = <1000>; - - thermal-sensors = <&thermal 0>; - - trips { - cpu_passive: cpu-passive { - temperature = <47000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu_active: cpu-active { - temperature = <67000>; - hysteresis = <2000>; - type = "active"; - }; - - cpu_hot: cpu-hot { - temperature = <87000>; - hysteresis = <2000>; - type = "hot"; - }; - - cpu-crit { - temperature = <107000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu_passive>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - - map1 { - trip = <&cpu_active>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - - map2 { - trip = <&cpu_hot>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupt-parent = <&gic>; - interrupts = , - , - , - ; - }; - - infracfg: infracfg@10000000 { - compatible = "mediatek,mt7622-infracfg", - "syscon"; - reg = <0 0x10000000 0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - pwrap: pwrap@10001000 { - compatible = "mediatek,mt7622-pwrap"; - reg = <0 0x10001000 0 0x250>; - reg-names = "pwrap"; - clocks = <&infracfg CLK_INFRA_PMIC_PD>, <&pwrap_clk>; - clock-names = "spi", "wrap"; - resets = <&infracfg MT7622_INFRA_PMIC_WRAP_RST>; - reset-names = "pwrap"; - interrupts = ; - status = "disabled"; - }; - - pericfg: pericfg@10002000 { - compatible = "mediatek,mt7622-pericfg", - "syscon"; - reg = <0 0x10002000 0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - scpsys: scpsys@10006000 { - compatible = "mediatek,mt7622-scpsys", - "syscon"; - #power-domain-cells = <1>; - reg = <0 0x10006000 0 0x1000>; - interrupts = , - , - , - ; - infracfg = <&infracfg>; - clocks = <&topckgen CLK_TOP_HIF_SEL>; - clock-names = "hif_sel"; - }; - - cir: cir@10009000 { - compatible = "mediatek,mt7622-cir"; - reg = <0 0x10009000 0 0x1000>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_IRRX_PD>, - <&topckgen CLK_TOP_AXI_SEL>; - clock-names = "clk", "bus"; - status = "disabled"; - }; - - sysirq: interrupt-controller@10200620 { - compatible = "mediatek,mt7622-sysirq", - "mediatek,mt6577-sysirq"; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - reg = <0 0x10200620 0 0x20>; - }; - - efuse: efuse@10206000 { - compatible = "mediatek,mt7622-efuse", - "mediatek,efuse"; - reg = <0 0x10206000 0 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - - thermal_calibration: calib@198 { - reg = <0x198 0xc>; - }; - }; - - apmixedsys: apmixedsys@10209000 { - compatible = "mediatek,mt7622-apmixedsys", - "syscon"; - reg = <0 0x10209000 0 0x1000>; - #clock-cells = <1>; - }; - - topckgen: topckgen@10210000 { - compatible = "mediatek,mt7622-topckgen", - "syscon"; - reg = <0 0x10210000 0 0x1000>; - #clock-cells = <1>; - }; - - rng: rng@1020f000 { - compatible = "mediatek,mt7622-rng", - "mediatek,mt7623-rng"; - reg = <0 0x1020f000 0 0x1000>; - clocks = <&infracfg CLK_INFRA_TRNG>; - clock-names = "rng"; - }; - - pio: pinctrl@10211000 { - compatible = "mediatek,mt7622-pinctrl"; - reg = <0 0x10211000 0 0x1000>, - <0 0x10005000 0 0x1000>; - reg-names = "base", "eint"; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pio 0 0 103>; - interrupt-controller; - interrupts = ; - interrupt-parent = <&gic>; - #interrupt-cells = <2>; - }; - - watchdog: watchdog@10212000 { - compatible = "mediatek,mt7622-wdt", - "mediatek,mt6589-wdt"; - reg = <0 0x10212000 0 0x800>; - }; - - rtc: rtc@10212800 { - compatible = "mediatek,mt7622-rtc", - "mediatek,soc-rtc"; - reg = <0 0x10212800 0 0x200>; - interrupts = ; - clocks = <&topckgen CLK_TOP_RTC>; - clock-names = "rtc"; - }; - - gic: interrupt-controller@10300000 { - compatible = "arm,gic-400"; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - reg = <0 0x10310000 0 0x1000>, - <0 0x10320000 0 0x1000>, - <0 0x10340000 0 0x2000>, - <0 0x10360000 0 0x2000>; - }; - - cci: cci@10390000 { - compatible = "arm,cci-400"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0 0x10390000 0 0x1000>; - ranges = <0 0 0x10390000 0x10000>; - - cci_control0: slave-if@1000 { - compatible = "arm,cci-400-ctrl-if"; - interface-type = "ace-lite"; - reg = <0x1000 0x1000>; - }; - - cci_control1: slave-if@4000 { - compatible = "arm,cci-400-ctrl-if"; - interface-type = "ace"; - reg = <0x4000 0x1000>; - }; - - cci_control2: slave-if@5000 { - compatible = "arm,cci-400-ctrl-if"; - interface-type = "ace"; - reg = <0x5000 0x1000>; - }; - - pmu@9000 { - compatible = "arm,cci-400-pmu,r1"; - reg = <0x9000 0x5000>; - interrupts = , - , - , - , - ; - }; - }; - - auxadc: adc@11001000 { - compatible = "mediatek,mt7622-auxadc"; - reg = <0 0x11001000 0 0x1000>; - clocks = <&pericfg CLK_PERI_AUXADC_PD>; - clock-names = "main"; - #io-channel-cells = <1>; - }; - - uart0: serial@11002000 { - compatible = "mediatek,mt7622-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11002000 0 0x400>; - interrupts = ; - clocks = <&topckgen CLK_TOP_UART_SEL>, - <&pericfg CLK_PERI_UART0_PD>; - clock-names = "baud", "bus"; - status = "disabled"; - }; - - uart1: serial@11003000 { - compatible = "mediatek,mt7622-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11003000 0 0x400>; - interrupts = ; - clocks = <&topckgen CLK_TOP_UART_SEL>, - <&pericfg CLK_PERI_UART1_PD>; - clock-names = "baud", "bus"; - status = "disabled"; - }; - - uart2: serial@11004000 { - compatible = "mediatek,mt7622-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11004000 0 0x400>; - interrupts = ; - clocks = <&topckgen CLK_TOP_UART_SEL>, - <&pericfg CLK_PERI_UART2_PD>; - clock-names = "baud", "bus"; - status = "disabled"; - }; - - uart3: serial@11005000 { - compatible = "mediatek,mt7622-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11005000 0 0x400>; - interrupts = ; - clocks = <&topckgen CLK_TOP_UART_SEL>, - <&pericfg CLK_PERI_UART3_PD>; - clock-names = "baud", "bus"; - status = "disabled"; - }; - - pwm: pwm@11006000 { - compatible = "mediatek,mt7622-pwm"; - reg = <0 0x11006000 0 0x1000>; - interrupts = ; - clocks = <&topckgen CLK_TOP_PWM_SEL>, - <&pericfg CLK_PERI_PWM_PD>, - <&pericfg CLK_PERI_PWM1_PD>, - <&pericfg CLK_PERI_PWM2_PD>, - <&pericfg CLK_PERI_PWM3_PD>, - <&pericfg CLK_PERI_PWM4_PD>, - <&pericfg CLK_PERI_PWM5_PD>, - <&pericfg CLK_PERI_PWM6_PD>; - clock-names = "top", "main", "pwm1", "pwm2", "pwm3", "pwm4", - "pwm5", "pwm6"; - status = "disabled"; - }; - - i2c0: i2c@11007000 { - compatible = "mediatek,mt7622-i2c"; - reg = <0 0x11007000 0 0x90>, - <0 0x11000100 0 0x80>; - interrupts = ; - clock-div = <16>; - clocks = <&pericfg CLK_PERI_I2C0_PD>, - <&pericfg CLK_PERI_AP_DMA_PD>; - clock-names = "main", "dma"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c1: i2c@11008000 { - compatible = "mediatek,mt7622-i2c"; - reg = <0 0x11008000 0 0x90>, - <0 0x11000180 0 0x80>; - interrupts = ; - clock-div = <16>; - clocks = <&pericfg CLK_PERI_I2C1_PD>, - <&pericfg CLK_PERI_AP_DMA_PD>; - clock-names = "main", "dma"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@11009000 { - compatible = "mediatek,mt7622-i2c"; - reg = <0 0x11009000 0 0x90>, - <0 0x11000200 0 0x80>; - interrupts = ; - clock-div = <16>; - clocks = <&pericfg CLK_PERI_I2C2_PD>, - <&pericfg CLK_PERI_AP_DMA_PD>; - clock-names = "main", "dma"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi0: spi@1100a000 { - compatible = "mediatek,mt7622-spi"; - reg = <0 0x1100a000 0 0x100>; - interrupts = ; - clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, - <&topckgen CLK_TOP_SPI0_SEL>, - <&pericfg CLK_PERI_SPI0_PD>; - clock-names = "parent-clk", "sel-clk", "spi-clk"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - thermal: thermal@1100b000 { - #thermal-sensor-cells = <1>; - compatible = "mediatek,mt7622-thermal"; - reg = <0 0x1100b000 0 0x1000>; - interrupts = <0 78 IRQ_TYPE_LEVEL_LOW>; - clocks = <&pericfg CLK_PERI_THERM_PD>, - <&pericfg CLK_PERI_AUXADC_PD>; - clock-names = "therm", "auxadc"; - resets = <&pericfg MT7622_PERI_THERM_SW_RST>; - reset-names = "therm"; - mediatek,auxadc = <&auxadc>; - mediatek,apmixedsys = <&apmixedsys>; - nvmem-cells = <&thermal_calibration>; - nvmem-cell-names = "calibration-data"; - }; - - btif: serial@1100c000 { - compatible = "mediatek,mt7622-btif", - "mediatek,mtk-btif"; - reg = <0 0x1100c000 0 0x1000>; - interrupts = ; - clocks = <&pericfg CLK_PERI_BTIF_PD>; - clock-names = "main"; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - - bluetooth { - compatible = "mediatek,mt7622-bluetooth"; - power-domains = <&scpsys MT7622_POWER_DOMAIN_WB>; - clocks = <&clk25m>; - clock-names = "ref"; - }; - }; - - nandc: nfi@1100d000 { - compatible = "mediatek,mt7622-nfc"; - reg = <0 0x1100D000 0 0x1000>; - interrupts = ; - clocks = <&pericfg CLK_PERI_NFI_PD>, - <&pericfg CLK_PERI_SNFI_PD>; - clock-names = "nfi_clk", "pad_clk"; - ecc-engine = <&bch>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - bch: ecc@1100e000 { - compatible = "mediatek,mt7622-ecc"; - reg = <0 0x1100e000 0 0x1000>; - interrupts = ; - clocks = <&pericfg CLK_PERI_NFIECC_PD>; - clock-names = "nfiecc_clk"; - status = "disabled"; - }; - - nor_flash: spi@11014000 { - compatible = "mediatek,mt7622-nor", - "mediatek,mt8173-nor"; - reg = <0 0x11014000 0 0xe0>; - clocks = <&pericfg CLK_PERI_FLASH_PD>, - <&topckgen CLK_TOP_FLASH_SEL>; - clock-names = "spi", "sf"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi1: spi@11016000 { - compatible = "mediatek,mt7622-spi"; - reg = <0 0x11016000 0 0x100>; - interrupts = ; - clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, - <&topckgen CLK_TOP_SPI1_SEL>, - <&pericfg CLK_PERI_SPI1_PD>; - clock-names = "parent-clk", "sel-clk", "spi-clk"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - uart4: serial@11019000 { - compatible = "mediatek,mt7622-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11019000 0 0x400>; - interrupts = ; - clocks = <&topckgen CLK_TOP_UART_SEL>, - <&pericfg CLK_PERI_UART4_PD>; - clock-names = "baud", "bus"; - status = "disabled"; - }; - - audsys: clock-controller@11220000 { - compatible = "mediatek,mt7622-audsys", "syscon"; - reg = <0 0x11220000 0 0x2000>; - #clock-cells = <1>; - - afe: audio-controller { - compatible = "mediatek,mt7622-audio"; - interrupts = , - ; - interrupt-names = "afe", "asys"; - - clocks = <&infracfg CLK_INFRA_AUDIO_PD>, - <&topckgen CLK_TOP_AUD1_SEL>, - <&topckgen CLK_TOP_AUD2_SEL>, - <&topckgen CLK_TOP_A1SYS_HP_DIV_PD>, - <&topckgen CLK_TOP_A2SYS_HP_DIV_PD>, - <&topckgen CLK_TOP_I2S0_MCK_SEL>, - <&topckgen CLK_TOP_I2S1_MCK_SEL>, - <&topckgen CLK_TOP_I2S2_MCK_SEL>, - <&topckgen CLK_TOP_I2S3_MCK_SEL>, - <&topckgen CLK_TOP_I2S0_MCK_DIV>, - <&topckgen CLK_TOP_I2S1_MCK_DIV>, - <&topckgen CLK_TOP_I2S2_MCK_DIV>, - <&topckgen CLK_TOP_I2S3_MCK_DIV>, - <&topckgen CLK_TOP_I2S0_MCK_DIV_PD>, - <&topckgen CLK_TOP_I2S1_MCK_DIV_PD>, - <&topckgen CLK_TOP_I2S2_MCK_DIV_PD>, - <&topckgen CLK_TOP_I2S3_MCK_DIV_PD>, - <&audsys CLK_AUDIO_I2SO1>, - <&audsys CLK_AUDIO_I2SO2>, - <&audsys CLK_AUDIO_I2SO3>, - <&audsys CLK_AUDIO_I2SO4>, - <&audsys CLK_AUDIO_I2SIN1>, - <&audsys CLK_AUDIO_I2SIN2>, - <&audsys CLK_AUDIO_I2SIN3>, - <&audsys CLK_AUDIO_I2SIN4>, - <&audsys CLK_AUDIO_ASRCO1>, - <&audsys CLK_AUDIO_ASRCO2>, - <&audsys CLK_AUDIO_ASRCO3>, - <&audsys CLK_AUDIO_ASRCO4>, - <&audsys CLK_AUDIO_AFE>, - <&audsys CLK_AUDIO_AFE_CONN>, - <&audsys CLK_AUDIO_A1SYS>, - <&audsys CLK_AUDIO_A2SYS>; - - clock-names = "infra_sys_audio_clk", - "top_audio_mux1_sel", - "top_audio_mux2_sel", - "top_audio_a1sys_hp", - "top_audio_a2sys_hp", - "i2s0_src_sel", - "i2s1_src_sel", - "i2s2_src_sel", - "i2s3_src_sel", - "i2s0_src_div", - "i2s1_src_div", - "i2s2_src_div", - "i2s3_src_div", - "i2s0_mclk_en", - "i2s1_mclk_en", - "i2s2_mclk_en", - "i2s3_mclk_en", - "i2so0_hop_ck", - "i2so1_hop_ck", - "i2so2_hop_ck", - "i2so3_hop_ck", - "i2si0_hop_ck", - "i2si1_hop_ck", - "i2si2_hop_ck", - "i2si3_hop_ck", - "asrc0_out_ck", - "asrc1_out_ck", - "asrc2_out_ck", - "asrc3_out_ck", - "audio_afe_pd", - "audio_afe_conn_pd", - "audio_a1sys_pd", - "audio_a2sys_pd"; - - assigned-clocks = <&topckgen CLK_TOP_A1SYS_HP_SEL>, - <&topckgen CLK_TOP_A2SYS_HP_SEL>, - <&topckgen CLK_TOP_A1SYS_HP_DIV>, - <&topckgen CLK_TOP_A2SYS_HP_DIV>; - assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL>, - <&topckgen CLK_TOP_AUD2PLL>; - assigned-clock-rates = <0>, <0>, <49152000>, <45158400>; - }; - }; - - mmc0: mmc@11230000 { - compatible = "mediatek,mt7622-mmc"; - reg = <0 0x11230000 0 0x1000>; - interrupts = ; - clocks = <&pericfg CLK_PERI_MSDC30_0_PD>, - <&topckgen CLK_TOP_MSDC50_0_SEL>; - clock-names = "source", "hclk"; - status = "disabled"; - }; - - mmc1: mmc@11240000 { - compatible = "mediatek,mt7622-mmc"; - reg = <0 0x11240000 0 0x1000>; - interrupts = ; - clocks = <&pericfg CLK_PERI_MSDC30_1_PD>, - <&topckgen CLK_TOP_AXI_SEL>; - clock-names = "source", "hclk"; - status = "disabled"; - }; - - ssusbsys: ssusbsys@1a000000 { - compatible = "mediatek,mt7622-ssusbsys", - "syscon"; - reg = <0 0x1a000000 0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - ssusb: usb@1a0c0000 { - compatible = "mediatek,mt7622-xhci", - "mediatek,mtk-xhci"; - reg = <0 0x1a0c0000 0 0x01000>, - <0 0x1a0c4700 0 0x0100>; - reg-names = "mac", "ippc"; - interrupts = ; - power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF1>; - clocks = <&ssusbsys CLK_SSUSB_SYS_EN>, - <&ssusbsys CLK_SSUSB_REF_EN>, - <&ssusbsys CLK_SSUSB_MCU_EN>, - <&ssusbsys CLK_SSUSB_DMA_EN>; - clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck"; - phys = <&u2port0 PHY_TYPE_USB2>, - <&u3port0 PHY_TYPE_USB3>, - <&u2port1 PHY_TYPE_USB2>; - - status = "disabled"; - }; - - u3phy: usb-phy@1a0c4000 { - compatible = "mediatek,mt7622-u3phy", - "mediatek,generic-tphy-v1"; - reg = <0 0x1a0c4000 0 0x700>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - status = "disabled"; - - u2port0: usb-phy@1a0c4800 { - reg = <0 0x1a0c4800 0 0x0100>; - #phy-cells = <1>; - clocks = <&ssusbsys CLK_SSUSB_U2_PHY_EN>; - clock-names = "ref"; - }; - - u3port0: usb-phy@1a0c4900 { - reg = <0 0x1a0c4900 0 0x0700>; - #phy-cells = <1>; - clocks = <&clk25m>; - clock-names = "ref"; - }; - - u2port1: usb-phy@1a0c5000 { - reg = <0 0x1a0c5000 0 0x0100>; - #phy-cells = <1>; - clocks = <&ssusbsys CLK_SSUSB_U2_PHY_1P_EN>; - clock-names = "ref"; - }; - }; - - pciesys: pciesys@1a100800 { - compatible = "mediatek,mt7622-pciesys", - "syscon"; - reg = <0 0x1a100800 0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - pcie: pcie@1a140000 { - compatible = "mediatek,mt7622-pcie"; - device_type = "pci"; - reg = <0 0x1a140000 0 0x1000>, - <0 0x1a143000 0 0x1000>, - <0 0x1a145000 0 0x1000>; - reg-names = "subsys", "port0", "port1"; - #address-cells = <3>; - #size-cells = <2>; - interrupts = , - ; - clocks = <&pciesys CLK_PCIE_P0_MAC_EN>, - <&pciesys CLK_PCIE_P1_MAC_EN>, - <&pciesys CLK_PCIE_P0_AHB_EN>, - <&pciesys CLK_PCIE_P0_AHB_EN>, - <&pciesys CLK_PCIE_P0_AUX_EN>, - <&pciesys CLK_PCIE_P1_AUX_EN>, - <&pciesys CLK_PCIE_P0_AXI_EN>, - <&pciesys CLK_PCIE_P1_AXI_EN>, - <&pciesys CLK_PCIE_P0_OBFF_EN>, - <&pciesys CLK_PCIE_P1_OBFF_EN>, - <&pciesys CLK_PCIE_P0_PIPE_EN>, - <&pciesys CLK_PCIE_P1_PIPE_EN>; - clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1", - "aux_ck0", "aux_ck1", "axi_ck0", "axi_ck1", - "obff_ck0", "obff_ck1", "pipe_ck0", "pipe_ck1"; - power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>; - bus-range = <0x00 0xff>; - ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>; - status = "disabled"; - - pcie0: pcie@0,0 { - reg = <0x0000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges; - status = "disabled"; - - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie_intc0 0>, - <0 0 0 2 &pcie_intc0 1>, - <0 0 0 3 &pcie_intc0 2>, - <0 0 0 4 &pcie_intc0 3>; - pcie_intc0: interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - }; - }; - - pcie1: pcie@1,0 { - reg = <0x0800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges; - status = "disabled"; - - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie_intc1 0>, - <0 0 0 2 &pcie_intc1 1>, - <0 0 0 3 &pcie_intc1 2>, - <0 0 0 4 &pcie_intc1 3>; - pcie_intc1: interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - }; - }; - }; - - sata: sata@1a200000 { - compatible = "mediatek,mt7622-ahci", - "mediatek,mtk-ahci"; - reg = <0 0x1a200000 0 0x1100>; - interrupts = ; - interrupt-names = "hostc"; - clocks = <&pciesys CLK_SATA_AHB_EN>, - <&pciesys CLK_SATA_AXI_EN>, - <&pciesys CLK_SATA_ASIC_EN>, - <&pciesys CLK_SATA_RBC_EN>, - <&pciesys CLK_SATA_PM_EN>; - clock-names = "ahb", "axi", "asic", "rbc", "pm"; - phys = <&sata_port PHY_TYPE_SATA>; - phy-names = "sata-phy"; - ports-implemented = <0x1>; - power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>; - resets = <&pciesys MT7622_SATA_AXI_BUS_RST>, - <&pciesys MT7622_SATA_PHY_SW_RST>, - <&pciesys MT7622_SATA_PHY_REG_RST>; - reset-names = "axi", "sw", "reg"; - mediatek,phy-mode = <&pciesys>; - status = "disabled"; - }; - - sata_phy: sata-phy@1a243000 { - compatible = "mediatek,generic-tphy-v1"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - status = "disabled"; - - sata_port: sata-phy@1a243000 { - reg = <0 0x1a243000 0 0x0100>; - clocks = <&topckgen CLK_TOP_ETH_500M>; - clock-names = "ref"; - #phy-cells = <1>; - }; - }; - - ethsys: syscon@1b000000 { - compatible = "mediatek,mt7622-ethsys", - "syscon"; - reg = <0 0x1b000000 0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - hsdma: dma-controller@1b007000 { - compatible = "mediatek,mt7622-hsdma"; - reg = <0 0x1b007000 0 0x1000>; - interrupts = ; - clocks = <ðsys CLK_ETH_HSDMA_EN>; - clock-names = "hsdma"; - power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>; - #dma-cells = <1>; - }; - - eth: ethernet@1b100000 { - compatible = "mediatek,mt7622-eth", - "mediatek,mt2701-eth", - "syscon"; - reg = <0 0x1b100000 0 0x20000>; - interrupts = , - , - ; - clocks = <&topckgen CLK_TOP_ETH_SEL>, - <ðsys CLK_ETH_ESW_EN>, - <ðsys CLK_ETH_GP0_EN>, - <ðsys CLK_ETH_GP1_EN>, - <ðsys CLK_ETH_GP2_EN>, - <&sgmiisys CLK_SGMII_TX250M_EN>, - <&sgmiisys CLK_SGMII_RX250M_EN>, - <&sgmiisys CLK_SGMII_CDR_REF>, - <&sgmiisys CLK_SGMII_CDR_FB>, - <&topckgen CLK_TOP_SGMIIPLL>, - <&apmixedsys CLK_APMIXED_ETH2PLL>; - clock-names = "ethif", "esw", "gp0", "gp1", "gp2", - "sgmii_tx250m", "sgmii_rx250m", - "sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck", - "eth2pll"; - power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>; - mediatek,ethsys = <ðsys>; - mediatek,sgmiisys = <&sgmiisys>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - sgmiisys: sgmiisys@1b128000 { - compatible = "mediatek,mt7622-sgmiisys", - "syscon"; - reg = <0 0x1b128000 0 0x3000>; - #clock-cells = <1>; - }; -}; diff --git a/sys/gnu/dts/arm64/mediatek/mt8173-evb.dts b/sys/gnu/dts/arm64/mediatek/mt8173-evb.dts deleted file mode 100644 index 6dffada2e66..00000000000 --- a/sys/gnu/dts/arm64/mediatek/mt8173-evb.dts +++ /dev/null @@ -1,534 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2014 MediaTek Inc. - * Author: Eddie Huang - */ - -/dts-v1/; -#include -#include "mt8173.dtsi" - -/ { - model = "MediaTek MT8173 evaluation board"; - compatible = "mediatek,mt8173-evb", "mediatek,mt8173"; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0 0x40000000 0 0x80000000>; - }; - - chosen { }; - - connector { - compatible = "hdmi-connector"; - label = "hdmi"; - type = "d"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi0_out>; - }; - }; - }; - - extcon_usb: extcon_iddig { - compatible = "linux,extcon-usb-gpio"; - id-gpio = <&pio 16 GPIO_ACTIVE_HIGH>; - }; - - usb_p1_vbus: regulator@0 { - compatible = "regulator-fixed"; - regulator-name = "usb_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&pio 130 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - usb_p0_vbus: regulator@1 { - compatible = "regulator-fixed"; - regulator-name = "vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&pio 9 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&cec { - status = "okay"; -}; - -&cpu0 { - proc-supply = <&mt6397_vpca15_reg>; -}; - -&cpu1 { - proc-supply = <&mt6397_vpca15_reg>; -}; - -&cpu2 { - proc-supply = <&da9211_vcpu_reg>; - sram-supply = <&mt6397_vsramca7_reg>; -}; - -&cpu3 { - proc-supply = <&da9211_vcpu_reg>; - sram-supply = <&mt6397_vsramca7_reg>; -}; - -&dpi0 { - status = "okay"; -}; - -&hdmi_phy { - status = "okay"; -}; - -&hdmi0 { - status = "okay"; - - ports { - port@1 { - reg = <1>; - - hdmi0_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; - }; - }; -}; - -&i2c1 { - status = "okay"; - - buck: da9211@68 { - compatible = "dlg,da9211"; - reg = <0x68>; - - regulators { - da9211_vcpu_reg: BUCKA { - regulator-name = "VBUCKA"; - regulator-min-microvolt = < 700000>; - regulator-max-microvolt = <1310000>; - regulator-min-microamp = <2000000>; - regulator-max-microamp = <4400000>; - regulator-ramp-delay = <10000>; - regulator-always-on; - }; - - da9211_vgpu_reg: BUCKB { - regulator-name = "VBUCKB"; - regulator-min-microvolt = < 700000>; - regulator-max-microvolt = <1310000>; - regulator-min-microamp = <2000000>; - regulator-max-microamp = <3000000>; - regulator-ramp-delay = <10000>; - }; - }; - }; -}; - -&mmc0 { - status = "okay"; - pinctrl-names = "default", "state_uhs"; - pinctrl-0 = <&mmc0_pins_default>; - pinctrl-1 = <&mmc0_pins_uhs>; - bus-width = <8>; - max-frequency = <50000000>; - cap-mmc-highspeed; - mediatek,hs200-cmd-int-delay=<26>; - mediatek,hs400-cmd-int-delay=<14>; - mediatek,hs400-cmd-resp-sel-rising; - vmmc-supply = <&mt6397_vemc_3v3_reg>; - vqmmc-supply = <&mt6397_vio18_reg>; - non-removable; -}; - -&mmc1 { - status = "okay"; - pinctrl-names = "default", "state_uhs"; - pinctrl-0 = <&mmc1_pins_default>; - pinctrl-1 = <&mmc1_pins_uhs>; - bus-width = <4>; - max-frequency = <50000000>; - cap-sd-highspeed; - sd-uhs-sdr25; - cd-gpios = <&pio 132 0>; - vmmc-supply = <&mt6397_vmch_reg>; - vqmmc-supply = <&mt6397_vmc_reg>; -}; - -&pio { - disp_pwm0_pins: disp_pwm0_pins { - pins1 { - pinmux = ; - output-low; - }; - }; - - mmc0_pins_default: mmc0default { - pins_cmd_dat { - pinmux = , - , - , - , - , - , - , - , - ; - input-enable; - bias-pull-up; - }; - - pins_clk { - pinmux = ; - bias-pull-down; - }; - - pins_rst { - pinmux = ; - bias-pull-up; - }; - }; - - mmc1_pins_default: mmc1default { - pins_cmd_dat { - pinmux = , - , - , - , - ; - input-enable; - drive-strength = ; - bias-pull-up = ; - }; - - pins_clk { - pinmux = ; - bias-pull-down; - drive-strength = ; - }; - - pins_insert { - pinmux = ; - bias-pull-up; - }; - }; - - mmc0_pins_uhs: mmc0 { - pins_cmd_dat { - pinmux = , - , - , - , - , - , - , - , - ; - input-enable; - drive-strength = ; - bias-pull-up = ; - }; - - pins_clk { - pinmux = ; - drive-strength = ; - bias-pull-down = ; - }; - - pins_rst { - pinmux = ; - bias-pull-up; - }; - }; - - mmc1_pins_uhs: mmc1 { - pins_cmd_dat { - pinmux = , - , - , - , - ; - input-enable; - drive-strength = ; - bias-pull-up = ; - }; - - pins_clk { - pinmux = ; - drive-strength = ; - bias-pull-down = ; - }; - }; - - usb_id_pins_float: usb_iddig_pull_up { - pins_iddig { - pinmux = ; - bias-pull-up; - }; - }; - - usb_id_pins_ground: usb_iddig_pull_down { - pins_iddig { - pinmux = ; - bias-pull-down; - }; - }; -}; - -&pwm0 { - pinctrl-names = "default"; - pinctrl-0 = <&disp_pwm0_pins>; - status = "okay"; -}; - -&pwrap { - /* Only MT8173 E1 needs USB power domain */ - power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>; - - pmic: mt6397 { - compatible = "mediatek,mt6397"; - interrupt-parent = <&pio>; - interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - #interrupt-cells = <2>; - - mt6397regulator: mt6397regulator { - compatible = "mediatek,mt6397-regulator"; - - mt6397_vpca15_reg: buck_vpca15 { - regulator-compatible = "buck_vpca15"; - regulator-name = "vpca15"; - regulator-min-microvolt = < 700000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <12500>; - regulator-always-on; - }; - - mt6397_vpca7_reg: buck_vpca7 { - regulator-compatible = "buck_vpca7"; - regulator-name = "vpca7"; - regulator-min-microvolt = < 700000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <12500>; - regulator-enable-ramp-delay = <115>; - }; - - mt6397_vsramca15_reg: buck_vsramca15 { - regulator-compatible = "buck_vsramca15"; - regulator-name = "vsramca15"; - regulator-min-microvolt = < 700000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <12500>; - regulator-always-on; - }; - - mt6397_vsramca7_reg: buck_vsramca7 { - regulator-compatible = "buck_vsramca7"; - regulator-name = "vsramca7"; - regulator-min-microvolt = < 700000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <12500>; - regulator-always-on; - }; - - mt6397_vcore_reg: buck_vcore { - regulator-compatible = "buck_vcore"; - regulator-name = "vcore"; - regulator-min-microvolt = < 700000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <12500>; - regulator-always-on; - }; - - mt6397_vgpu_reg: buck_vgpu { - regulator-compatible = "buck_vgpu"; - regulator-name = "vgpu"; - regulator-min-microvolt = < 700000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <12500>; - regulator-enable-ramp-delay = <115>; - }; - - mt6397_vdrm_reg: buck_vdrm { - regulator-compatible = "buck_vdrm"; - regulator-name = "vdrm"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1400000>; - regulator-ramp-delay = <12500>; - regulator-always-on; - }; - - mt6397_vio18_reg: buck_vio18 { - regulator-compatible = "buck_vio18"; - regulator-name = "vio18"; - regulator-min-microvolt = <1620000>; - regulator-max-microvolt = <1980000>; - regulator-ramp-delay = <12500>; - regulator-always-on; - }; - - mt6397_vtcxo_reg: ldo_vtcxo { - regulator-compatible = "ldo_vtcxo"; - regulator-name = "vtcxo"; - regulator-always-on; - }; - - mt6397_va28_reg: ldo_va28 { - regulator-compatible = "ldo_va28"; - regulator-name = "va28"; - regulator-always-on; - }; - - mt6397_vcama_reg: ldo_vcama { - regulator-compatible = "ldo_vcama"; - regulator-name = "vcama"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <2800000>; - regulator-enable-ramp-delay = <218>; - }; - - mt6397_vio28_reg: ldo_vio28 { - regulator-compatible = "ldo_vio28"; - regulator-name = "vio28"; - regulator-always-on; - }; - - mt6397_vusb_reg: ldo_vusb { - regulator-compatible = "ldo_vusb"; - regulator-name = "vusb"; - }; - - mt6397_vmc_reg: ldo_vmc { - regulator-compatible = "ldo_vmc"; - regulator-name = "vmc"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <218>; - }; - - mt6397_vmch_reg: ldo_vmch { - regulator-compatible = "ldo_vmch"; - regulator-name = "vmch"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <218>; - }; - - mt6397_vemc_3v3_reg: ldo_vemc3v3 { - regulator-compatible = "ldo_vemc3v3"; - regulator-name = "vemc_3v3"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <218>; - }; - - mt6397_vgp1_reg: ldo_vgp1 { - regulator-compatible = "ldo_vgp1"; - regulator-name = "vcamd"; - regulator-min-microvolt = <1220000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <240>; - }; - - mt6397_vgp2_reg: ldo_vgp2 { - regulator-compatible = "ldo_vgp2"; - regulator-name = "vcamio"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <218>; - }; - - mt6397_vgp3_reg: ldo_vgp3 { - regulator-compatible = "ldo_vgp3"; - regulator-name = "vcamaf"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <218>; - }; - - mt6397_vgp4_reg: ldo_vgp4 { - regulator-compatible = "ldo_vgp4"; - regulator-name = "vgp4"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <218>; - }; - - mt6397_vgp5_reg: ldo_vgp5 { - regulator-compatible = "ldo_vgp5"; - regulator-name = "vgp5"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3000000>; - regulator-enable-ramp-delay = <218>; - }; - - mt6397_vgp6_reg: ldo_vgp6 { - regulator-compatible = "ldo_vgp6"; - regulator-name = "vgp6"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <218>; - }; - - mt6397_vibr_reg: ldo_vibr { - regulator-compatible = "ldo_vibr"; - regulator-name = "vibr"; - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <218>; - }; - }; - }; -}; - -&pio { - spi_pins_a: spi0 { - pins_spi { - pinmux = , - , - , - ; - }; - }; -}; - -&spi { - pinctrl-names = "default"; - pinctrl-0 = <&spi_pins_a>; - mediatek,pad-select = <0>; - status = "okay"; -}; - -&ssusb { - vusb33-supply = <&mt6397_vusb_reg>; - vbus-supply = <&usb_p0_vbus>; - extcon = <&extcon_usb>; - dr_mode = "otg"; - wakeup-source; - pinctrl-names = "default", "id_float", "id_ground"; - pinctrl-0 = <&usb_id_pins_float>; - pinctrl-1 = <&usb_id_pins_float>; - pinctrl-2 = <&usb_id_pins_ground>; - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&usb_host { - vusb33-supply = <&mt6397_vusb_reg>; - vbus-supply = <&usb_p1_vbus>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/mediatek/mt8173-pinfunc.h b/sys/gnu/dts/arm64/mediatek/mt8173-pinfunc.h deleted file mode 100644 index a5e308dc854..00000000000 --- a/sys/gnu/dts/arm64/mediatek/mt8173-pinfunc.h +++ /dev/null @@ -1,674 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2014 MediaTek Inc. - * Author: Hongzhou.Yang - */ - -#ifndef __DTS_MT8173_PINFUNC_H -#define __DTS_MT8173_PINFUNC_H - -#include - -#define MT8173_PIN_0_EINT0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) -#define MT8173_PIN_0_EINT0__FUNC_IRDA_PDN (MTK_PIN_NO(0) | 1) -#define MT8173_PIN_0_EINT0__FUNC_I2S1_WS (MTK_PIN_NO(0) | 2) -#define MT8173_PIN_0_EINT0__FUNC_AUD_SPDIF (MTK_PIN_NO(0) | 3) -#define MT8173_PIN_0_EINT0__FUNC_UTXD0 (MTK_PIN_NO(0) | 4) -#define MT8173_PIN_0_EINT0__FUNC_DBG_MON_A_20_ (MTK_PIN_NO(0) | 7) - -#define MT8173_PIN_1_EINT1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) -#define MT8173_PIN_1_EINT1__FUNC_IRDA_RXD (MTK_PIN_NO(1) | 1) -#define MT8173_PIN_1_EINT1__FUNC_I2S1_BCK (MTK_PIN_NO(1) | 2) -#define MT8173_PIN_1_EINT1__FUNC_SDA5 (MTK_PIN_NO(1) | 3) -#define MT8173_PIN_1_EINT1__FUNC_URXD0 (MTK_PIN_NO(1) | 4) -#define MT8173_PIN_1_EINT1__FUNC_DBG_MON_A_21_ (MTK_PIN_NO(1) | 7) - -#define MT8173_PIN_2_EINT2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) -#define MT8173_PIN_2_EINT2__FUNC_IRDA_TXD (MTK_PIN_NO(2) | 1) -#define MT8173_PIN_2_EINT2__FUNC_I2S1_MCK (MTK_PIN_NO(2) | 2) -#define MT8173_PIN_2_EINT2__FUNC_SCL5 (MTK_PIN_NO(2) | 3) -#define MT8173_PIN_2_EINT2__FUNC_UTXD3 (MTK_PIN_NO(2) | 4) -#define MT8173_PIN_2_EINT2__FUNC_DBG_MON_A_22_ (MTK_PIN_NO(2) | 7) - -#define MT8173_PIN_3_EINT3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) -#define MT8173_PIN_3_EINT3__FUNC_DSI1_TE (MTK_PIN_NO(3) | 1) -#define MT8173_PIN_3_EINT3__FUNC_I2S1_DO_1 (MTK_PIN_NO(3) | 2) -#define MT8173_PIN_3_EINT3__FUNC_SDA3 (MTK_PIN_NO(3) | 3) -#define MT8173_PIN_3_EINT3__FUNC_URXD3 (MTK_PIN_NO(3) | 4) -#define MT8173_PIN_3_EINT3__FUNC_DBG_MON_A_23_ (MTK_PIN_NO(3) | 7) - -#define MT8173_PIN_4_EINT4__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) -#define MT8173_PIN_4_EINT4__FUNC_DISP_PWM1 (MTK_PIN_NO(4) | 1) -#define MT8173_PIN_4_EINT4__FUNC_I2S1_DO_2 (MTK_PIN_NO(4) | 2) -#define MT8173_PIN_4_EINT4__FUNC_SCL3 (MTK_PIN_NO(4) | 3) -#define MT8173_PIN_4_EINT4__FUNC_UCTS3 (MTK_PIN_NO(4) | 4) -#define MT8173_PIN_4_EINT4__FUNC_SFWP_B (MTK_PIN_NO(4) | 6) - -#define MT8173_PIN_5_EINT5__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) -#define MT8173_PIN_5_EINT5__FUNC_PCM1_CLK (MTK_PIN_NO(5) | 1) -#define MT8173_PIN_5_EINT5__FUNC_I2S2_WS (MTK_PIN_NO(5) | 2) -#define MT8173_PIN_5_EINT5__FUNC_SPI_CK_3_ (MTK_PIN_NO(5) | 3) -#define MT8173_PIN_5_EINT5__FUNC_URTS3 (MTK_PIN_NO(5) | 4) -#define MT8173_PIN_5_EINT5__FUNC_AP_MD32_JTAG_TMS (MTK_PIN_NO(5) | 5) -#define MT8173_PIN_5_EINT5__FUNC_SFOUT (MTK_PIN_NO(5) | 6) - -#define MT8173_PIN_6_EINT6__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) -#define MT8173_PIN_6_EINT6__FUNC_PCM1_SYNC (MTK_PIN_NO(6) | 1) -#define MT8173_PIN_6_EINT6__FUNC_I2S2_BCK (MTK_PIN_NO(6) | 2) -#define MT8173_PIN_6_EINT6__FUNC_SPI_MI_3_ (MTK_PIN_NO(6) | 3) -#define MT8173_PIN_6_EINT6__FUNC_AP_MD32_JTAG_TCK (MTK_PIN_NO(6) | 5) -#define MT8173_PIN_6_EINT6__FUNC_SFCS0 (MTK_PIN_NO(6) | 6) - -#define MT8173_PIN_7_EINT7__FUNC_GPIO7 (MTK_PIN_NO(7) | 0) -#define MT8173_PIN_7_EINT7__FUNC_PCM1_DI (MTK_PIN_NO(7) | 1) -#define MT8173_PIN_7_EINT7__FUNC_I2S2_DI_1 (MTK_PIN_NO(7) | 2) -#define MT8173_PIN_7_EINT7__FUNC_SPI_MO_3_ (MTK_PIN_NO(7) | 3) -#define MT8173_PIN_7_EINT7__FUNC_AP_MD32_JTAG_TDI (MTK_PIN_NO(7) | 5) -#define MT8173_PIN_7_EINT7__FUNC_SFHOLD (MTK_PIN_NO(7) | 6) - -#define MT8173_PIN_8_EINT8__FUNC_GPIO8 (MTK_PIN_NO(8) | 0) -#define MT8173_PIN_8_EINT8__FUNC_PCM1_DO (MTK_PIN_NO(8) | 1) -#define MT8173_PIN_8_EINT8__FUNC_I2S2_DI_2 (MTK_PIN_NO(8) | 2) -#define MT8173_PIN_8_EINT8__FUNC_SPI_CS_3_ (MTK_PIN_NO(8) | 3) -#define MT8173_PIN_8_EINT8__FUNC_AUD_SPDIF (MTK_PIN_NO(8) | 4) -#define MT8173_PIN_8_EINT8__FUNC_AP_MD32_JTAG_TDO (MTK_PIN_NO(8) | 5) -#define MT8173_PIN_8_EINT8__FUNC_SFIN (MTK_PIN_NO(8) | 6) - -#define MT8173_PIN_9_EINT9__FUNC_GPIO9 (MTK_PIN_NO(9) | 0) -#define MT8173_PIN_9_EINT9__FUNC_USB_DRVVBUS_P0 (MTK_PIN_NO(9) | 1) -#define MT8173_PIN_9_EINT9__FUNC_I2S2_MCK (MTK_PIN_NO(9) | 2) -#define MT8173_PIN_9_EINT9__FUNC_USB_DRVVBUS_P1 (MTK_PIN_NO(9) | 4) -#define MT8173_PIN_9_EINT9__FUNC_AP_MD32_JTAG_TRST (MTK_PIN_NO(9) | 5) -#define MT8173_PIN_9_EINT9__FUNC_SFCK (MTK_PIN_NO(9) | 6) - -#define MT8173_PIN_10_EINT10__FUNC_GPIO10 (MTK_PIN_NO(10) | 0) -#define MT8173_PIN_10_EINT10__FUNC_CLKM0 (MTK_PIN_NO(10) | 1) -#define MT8173_PIN_10_EINT10__FUNC_DSI1_TE (MTK_PIN_NO(10) | 2) -#define MT8173_PIN_10_EINT10__FUNC_DISP_PWM1 (MTK_PIN_NO(10) | 3) -#define MT8173_PIN_10_EINT10__FUNC_PWM4 (MTK_PIN_NO(10) | 4) -#define MT8173_PIN_10_EINT10__FUNC_IRDA_RXD (MTK_PIN_NO(10) | 5) - -#define MT8173_PIN_11_EINT11__FUNC_GPIO11 (MTK_PIN_NO(11) | 0) -#define MT8173_PIN_11_EINT11__FUNC_CLKM1 (MTK_PIN_NO(11) | 1) -#define MT8173_PIN_11_EINT11__FUNC_I2S3_WS (MTK_PIN_NO(11) | 2) -#define MT8173_PIN_11_EINT11__FUNC_USB_DRVVBUS_P0 (MTK_PIN_NO(11) | 3) -#define MT8173_PIN_11_EINT11__FUNC_PWM5 (MTK_PIN_NO(11) | 4) -#define MT8173_PIN_11_EINT11__FUNC_IRDA_TXD (MTK_PIN_NO(11) | 5) -#define MT8173_PIN_11_EINT11__FUNC_USB_DRVVBUS_P1 (MTK_PIN_NO(11) | 6) -#define MT8173_PIN_11_EINT11__FUNC_DBG_MON_B_30_ (MTK_PIN_NO(11) | 7) - -#define MT8173_PIN_12_EINT12__FUNC_GPIO12 (MTK_PIN_NO(12) | 0) -#define MT8173_PIN_12_EINT12__FUNC_CLKM2 (MTK_PIN_NO(12) | 1) -#define MT8173_PIN_12_EINT12__FUNC_I2S3_BCK (MTK_PIN_NO(12) | 2) -#define MT8173_PIN_12_EINT12__FUNC_SRCLKENA0 (MTK_PIN_NO(12) | 3) -#define MT8173_PIN_12_EINT12__FUNC_I2S2_WS (MTK_PIN_NO(12) | 5) -#define MT8173_PIN_12_EINT12__FUNC_DBG_MON_B_32_ (MTK_PIN_NO(12) | 7) - -#define MT8173_PIN_13_EINT13__FUNC_GPIO13 (MTK_PIN_NO(13) | 0) -#define MT8173_PIN_13_EINT13__FUNC_CLKM3 (MTK_PIN_NO(13) | 1) -#define MT8173_PIN_13_EINT13__FUNC_I2S3_MCK (MTK_PIN_NO(13) | 2) -#define MT8173_PIN_13_EINT13__FUNC_SRCLKENA0 (MTK_PIN_NO(13) | 3) -#define MT8173_PIN_13_EINT13__FUNC_I2S2_BCK (MTK_PIN_NO(13) | 5) -#define MT8173_PIN_13_EINT13__FUNC_DBG_MON_A_32_ (MTK_PIN_NO(13) | 7) - -#define MT8173_PIN_14_EINT14__FUNC_GPIO14 (MTK_PIN_NO(14) | 0) -#define MT8173_PIN_14_EINT14__FUNC_CMDAT0 (MTK_PIN_NO(14) | 1) -#define MT8173_PIN_14_EINT14__FUNC_CMCSD0 (MTK_PIN_NO(14) | 2) -#define MT8173_PIN_14_EINT14__FUNC_CLKM2 (MTK_PIN_NO(14) | 4) -#define MT8173_PIN_14_EINT14__FUNC_DBG_MON_B_6_ (MTK_PIN_NO(14) | 7) - -#define MT8173_PIN_15_EINT15__FUNC_GPIO15 (MTK_PIN_NO(15) | 0) -#define MT8173_PIN_15_EINT15__FUNC_CMDAT1 (MTK_PIN_NO(15) | 1) -#define MT8173_PIN_15_EINT15__FUNC_CMCSD1 (MTK_PIN_NO(15) | 2) -#define MT8173_PIN_15_EINT15__FUNC_CMFLASH (MTK_PIN_NO(15) | 3) -#define MT8173_PIN_15_EINT15__FUNC_CLKM3 (MTK_PIN_NO(15) | 4) -#define MT8173_PIN_15_EINT15__FUNC_DBG_MON_B_29_ (MTK_PIN_NO(15) | 7) - -#define MT8173_PIN_16_IDDIG__FUNC_GPIO16 (MTK_PIN_NO(16) | 0) -#define MT8173_PIN_16_IDDIG__FUNC_IDDIG (MTK_PIN_NO(16) | 1) -#define MT8173_PIN_16_IDDIG__FUNC_CMFLASH (MTK_PIN_NO(16) | 2) -#define MT8173_PIN_16_IDDIG__FUNC_PWM5 (MTK_PIN_NO(16) | 4) - -#define MT8173_PIN_17_WATCHDOG__FUNC_GPIO17 (MTK_PIN_NO(17) | 0) -#define MT8173_PIN_17_WATCHDOG__FUNC_WATCHDOG_AO (MTK_PIN_NO(17) | 1) - -#define MT8173_PIN_18_CEC__FUNC_GPIO18 (MTK_PIN_NO(18) | 0) -#define MT8173_PIN_18_CEC__FUNC_CEC (MTK_PIN_NO(18) | 1) - -#define MT8173_PIN_19_HDMISCK__FUNC_GPIO19 (MTK_PIN_NO(19) | 0) -#define MT8173_PIN_19_HDMISCK__FUNC_HDMISCK (MTK_PIN_NO(19) | 1) -#define MT8173_PIN_19_HDMISCK__FUNC_HDCP_SCL (MTK_PIN_NO(19) | 2) - -#define MT8173_PIN_20_HDMISD__FUNC_GPIO20 (MTK_PIN_NO(20) | 0) -#define MT8173_PIN_20_HDMISD__FUNC_HDMISD (MTK_PIN_NO(20) | 1) -#define MT8173_PIN_20_HDMISD__FUNC_HDCP_SDA (MTK_PIN_NO(20) | 2) - -#define MT8173_PIN_21_HTPLG__FUNC_GPIO21 (MTK_PIN_NO(21) | 0) -#define MT8173_PIN_21_HTPLG__FUNC_HTPLG (MTK_PIN_NO(21) | 1) - -#define MT8173_PIN_22_MSDC3_DAT0__FUNC_GPIO22 (MTK_PIN_NO(22) | 0) -#define MT8173_PIN_22_MSDC3_DAT0__FUNC_MSDC3_DAT0 (MTK_PIN_NO(22) | 1) - -#define MT8173_PIN_23_MSDC3_DAT1__FUNC_GPIO23 (MTK_PIN_NO(23) | 0) -#define MT8173_PIN_23_MSDC3_DAT1__FUNC_MSDC3_DAT1 (MTK_PIN_NO(23) | 1) - -#define MT8173_PIN_24_MSDC3_DAT2__FUNC_GPIO24 (MTK_PIN_NO(24) | 0) -#define MT8173_PIN_24_MSDC3_DAT2__FUNC_MSDC3_DAT2 (MTK_PIN_NO(24) | 1) - -#define MT8173_PIN_25_MSDC3_DAT3__FUNC_GPIO25 (MTK_PIN_NO(25) | 0) -#define MT8173_PIN_25_MSDC3_DAT3__FUNC_MSDC3_DAT3 (MTK_PIN_NO(25) | 1) - -#define MT8173_PIN_26_MSDC3_CLK__FUNC_GPIO26 (MTK_PIN_NO(26) | 0) -#define MT8173_PIN_26_MSDC3_CLK__FUNC_MSDC3_CLK (MTK_PIN_NO(26) | 1) - -#define MT8173_PIN_27_MSDC3_CMD__FUNC_GPIO27 (MTK_PIN_NO(27) | 0) -#define MT8173_PIN_27_MSDC3_CMD__FUNC_MSDC3_CMD (MTK_PIN_NO(27) | 1) - -#define MT8173_PIN_28_MSDC3_DSL__FUNC_GPIO28 (MTK_PIN_NO(28) | 0) -#define MT8173_PIN_28_MSDC3_DSL__FUNC_MSDC3_DSL (MTK_PIN_NO(28) | 1) - -#define MT8173_PIN_29_UCTS2__FUNC_GPIO29 (MTK_PIN_NO(29) | 0) -#define MT8173_PIN_29_UCTS2__FUNC_UCTS2 (MTK_PIN_NO(29) | 1) - -#define MT8173_PIN_30_URTS2__FUNC_GPIO30 (MTK_PIN_NO(30) | 0) -#define MT8173_PIN_30_URTS2__FUNC_URTS2 (MTK_PIN_NO(30) | 1) - -#define MT8173_PIN_31_URXD2__FUNC_GPIO31 (MTK_PIN_NO(31) | 0) -#define MT8173_PIN_31_URXD2__FUNC_URXD2 (MTK_PIN_NO(31) | 1) -#define MT8173_PIN_31_URXD2__FUNC_UTXD2 (MTK_PIN_NO(31) | 2) - -#define MT8173_PIN_32_UTXD2__FUNC_GPIO32 (MTK_PIN_NO(32) | 0) -#define MT8173_PIN_32_UTXD2__FUNC_UTXD2 (MTK_PIN_NO(32) | 1) -#define MT8173_PIN_32_UTXD2__FUNC_URXD2 (MTK_PIN_NO(32) | 2) - -#define MT8173_PIN_33_DAICLK__FUNC_GPIO33 (MTK_PIN_NO(33) | 0) -#define MT8173_PIN_33_DAICLK__FUNC_MRG_CLK (MTK_PIN_NO(33) | 1) -#define MT8173_PIN_33_DAICLK__FUNC_PCM0_CLK (MTK_PIN_NO(33) | 2) - -#define MT8173_PIN_34_DAIPCMIN__FUNC_GPIO34 (MTK_PIN_NO(34) | 0) -#define MT8173_PIN_34_DAIPCMIN__FUNC_MRG_DI (MTK_PIN_NO(34) | 1) -#define MT8173_PIN_34_DAIPCMIN__FUNC_PCM0_DI (MTK_PIN_NO(34) | 2) - -#define MT8173_PIN_35_DAIPCMOUT__FUNC_GPIO35 (MTK_PIN_NO(35) | 0) -#define MT8173_PIN_35_DAIPCMOUT__FUNC_MRG_DO (MTK_PIN_NO(35) | 1) -#define MT8173_PIN_35_DAIPCMOUT__FUNC_PCM0_DO (MTK_PIN_NO(35) | 2) - -#define MT8173_PIN_36_DAISYNC__FUNC_GPIO36 (MTK_PIN_NO(36) | 0) -#define MT8173_PIN_36_DAISYNC__FUNC_MRG_SYNC (MTK_PIN_NO(36) | 1) -#define MT8173_PIN_36_DAISYNC__FUNC_PCM0_SYNC (MTK_PIN_NO(36) | 2) - -#define MT8173_PIN_37_EINT16__FUNC_GPIO37 (MTK_PIN_NO(37) | 0) -#define MT8173_PIN_37_EINT16__FUNC_USB_DRVVBUS_P0 (MTK_PIN_NO(37) | 1) -#define MT8173_PIN_37_EINT16__FUNC_USB_DRVVBUS_P1 (MTK_PIN_NO(37) | 2) -#define MT8173_PIN_37_EINT16__FUNC_PWM0 (MTK_PIN_NO(37) | 3) -#define MT8173_PIN_37_EINT16__FUNC_PWM1 (MTK_PIN_NO(37) | 4) -#define MT8173_PIN_37_EINT16__FUNC_PWM2 (MTK_PIN_NO(37) | 5) -#define MT8173_PIN_37_EINT16__FUNC_CLKM0 (MTK_PIN_NO(37) | 6) - -#define MT8173_PIN_38_CONN_RST__FUNC_GPIO38 (MTK_PIN_NO(38) | 0) -#define MT8173_PIN_38_CONN_RST__FUNC_USB_DRVVBUS_P0 (MTK_PIN_NO(38) | 1) -#define MT8173_PIN_38_CONN_RST__FUNC_USB_DRVVBUS_P1 (MTK_PIN_NO(38) | 2) -#define MT8173_PIN_38_CONN_RST__FUNC_CLKM1 (MTK_PIN_NO(38) | 6) - -#define MT8173_PIN_39_CM2MCLK__FUNC_GPIO39 (MTK_PIN_NO(39) | 0) -#define MT8173_PIN_39_CM2MCLK__FUNC_CM2MCLK (MTK_PIN_NO(39) | 1) -#define MT8173_PIN_39_CM2MCLK__FUNC_CMCSD0 (MTK_PIN_NO(39) | 2) -#define MT8173_PIN_39_CM2MCLK__FUNC_DBG_MON_A_17_ (MTK_PIN_NO(39) | 7) - -#define MT8173_PIN_40_CMPCLK__FUNC_GPIO40 (MTK_PIN_NO(40) | 0) -#define MT8173_PIN_40_CMPCLK__FUNC_CMPCLK (MTK_PIN_NO(40) | 1) -#define MT8173_PIN_40_CMPCLK__FUNC_CMCSK (MTK_PIN_NO(40) | 2) -#define MT8173_PIN_40_CMPCLK__FUNC_CMCSD2 (MTK_PIN_NO(40) | 3) -#define MT8173_PIN_40_CMPCLK__FUNC_DBG_MON_A_18_ (MTK_PIN_NO(40) | 7) - -#define MT8173_PIN_41_CMMCLK__FUNC_GPIO41 (MTK_PIN_NO(41) | 0) -#define MT8173_PIN_41_CMMCLK__FUNC_CMMCLK (MTK_PIN_NO(41) | 1) -#define MT8173_PIN_41_CMMCLK__FUNC_DBG_MON_A_19_ (MTK_PIN_NO(41) | 7) - -#define MT8173_PIN_42_DSI_TE__FUNC_GPIO42 (MTK_PIN_NO(42) | 0) -#define MT8173_PIN_42_DSI_TE__FUNC_DSI_TE (MTK_PIN_NO(42) | 1) - -#define MT8173_PIN_43_SDA2__FUNC_GPIO43 (MTK_PIN_NO(43) | 0) -#define MT8173_PIN_43_SDA2__FUNC_SDA2 (MTK_PIN_NO(43) | 1) - -#define MT8173_PIN_44_SCL2__FUNC_GPIO44 (MTK_PIN_NO(44) | 0) -#define MT8173_PIN_44_SCL2__FUNC_SCL2 (MTK_PIN_NO(44) | 1) - -#define MT8173_PIN_45_SDA0__FUNC_GPIO45 (MTK_PIN_NO(45) | 0) -#define MT8173_PIN_45_SDA0__FUNC_SDA0 (MTK_PIN_NO(45) | 1) - -#define MT8173_PIN_46_SCL0__FUNC_GPIO46 (MTK_PIN_NO(46) | 0) -#define MT8173_PIN_46_SCL0__FUNC_SCL0 (MTK_PIN_NO(46) | 1) - -#define MT8173_PIN_47_RDN0_A__FUNC_GPIO47 (MTK_PIN_NO(47) | 0) -#define MT8173_PIN_47_RDN0_A__FUNC_CMDAT2 (MTK_PIN_NO(47) | 1) - -#define MT8173_PIN_48_RDP0_A__FUNC_GPIO48 (MTK_PIN_NO(48) | 0) -#define MT8173_PIN_48_RDP0_A__FUNC_CMDAT3 (MTK_PIN_NO(48) | 1) - -#define MT8173_PIN_49_RDN1_A__FUNC_GPIO49 (MTK_PIN_NO(49) | 0) -#define MT8173_PIN_49_RDN1_A__FUNC_CMDAT4 (MTK_PIN_NO(49) | 1) - -#define MT8173_PIN_50_RDP1_A__FUNC_GPIO50 (MTK_PIN_NO(50) | 0) -#define MT8173_PIN_50_RDP1_A__FUNC_CMDAT5 (MTK_PIN_NO(50) | 1) - -#define MT8173_PIN_51_RCN_A__FUNC_GPIO51 (MTK_PIN_NO(51) | 0) -#define MT8173_PIN_51_RCN_A__FUNC_CMDAT6 (MTK_PIN_NO(51) | 1) - -#define MT8173_PIN_52_RCP_A__FUNC_GPIO52 (MTK_PIN_NO(52) | 0) -#define MT8173_PIN_52_RCP_A__FUNC_CMDAT7 (MTK_PIN_NO(52) | 1) - -#define MT8173_PIN_53_RDN2_A__FUNC_GPIO53 (MTK_PIN_NO(53) | 0) -#define MT8173_PIN_53_RDN2_A__FUNC_CMDAT8 (MTK_PIN_NO(53) | 1) -#define MT8173_PIN_53_RDN2_A__FUNC_CMCSD3 (MTK_PIN_NO(53) | 2) - -#define MT8173_PIN_54_RDP2_A__FUNC_GPIO54 (MTK_PIN_NO(54) | 0) -#define MT8173_PIN_54_RDP2_A__FUNC_CMDAT9 (MTK_PIN_NO(54) | 1) -#define MT8173_PIN_54_RDP2_A__FUNC_CMCSD2 (MTK_PIN_NO(54) | 2) - -#define MT8173_PIN_55_RDN3_A__FUNC_GPIO55 (MTK_PIN_NO(55) | 0) -#define MT8173_PIN_55_RDN3_A__FUNC_CMHSYNC (MTK_PIN_NO(55) | 1) -#define MT8173_PIN_55_RDN3_A__FUNC_CMCSD1 (MTK_PIN_NO(55) | 2) - -#define MT8173_PIN_56_RDP3_A__FUNC_GPIO56 (MTK_PIN_NO(56) | 0) -#define MT8173_PIN_56_RDP3_A__FUNC_CMVSYNC (MTK_PIN_NO(56) | 1) -#define MT8173_PIN_56_RDP3_A__FUNC_CMCSD0 (MTK_PIN_NO(56) | 2) - -#define MT8173_PIN_57_MSDC0_DAT0__FUNC_GPIO57 (MTK_PIN_NO(57) | 0) -#define MT8173_PIN_57_MSDC0_DAT0__FUNC_MSDC0_DAT0 (MTK_PIN_NO(57) | 1) -#define MT8173_PIN_57_MSDC0_DAT0__FUNC_I2S1_WS (MTK_PIN_NO(57) | 2) -#define MT8173_PIN_57_MSDC0_DAT0__FUNC_DBG_MON_B_7_ (MTK_PIN_NO(57) | 7) - -#define MT8173_PIN_58_MSDC0_DAT1__FUNC_GPIO58 (MTK_PIN_NO(58) | 0) -#define MT8173_PIN_58_MSDC0_DAT1__FUNC_MSDC0_DAT1 (MTK_PIN_NO(58) | 1) -#define MT8173_PIN_58_MSDC0_DAT1__FUNC_I2S1_BCK (MTK_PIN_NO(58) | 2) -#define MT8173_PIN_58_MSDC0_DAT1__FUNC_DBG_MON_B_8_ (MTK_PIN_NO(58) | 7) - -#define MT8173_PIN_59_MSDC0_DAT2__FUNC_GPIO59 (MTK_PIN_NO(59) | 0) -#define MT8173_PIN_59_MSDC0_DAT2__FUNC_MSDC0_DAT2 (MTK_PIN_NO(59) | 1) -#define MT8173_PIN_59_MSDC0_DAT2__FUNC_I2S1_MCK (MTK_PIN_NO(59) | 2) -#define MT8173_PIN_59_MSDC0_DAT2__FUNC_DBG_MON_B_9_ (MTK_PIN_NO(59) | 7) - -#define MT8173_PIN_60_MSDC0_DAT3__FUNC_GPIO60 (MTK_PIN_NO(60) | 0) -#define MT8173_PIN_60_MSDC0_DAT3__FUNC_MSDC0_DAT3 (MTK_PIN_NO(60) | 1) -#define MT8173_PIN_60_MSDC0_DAT3__FUNC_I2S1_DO_1 (MTK_PIN_NO(60) | 2) -#define MT8173_PIN_60_MSDC0_DAT3__FUNC_DBG_MON_B_10_ (MTK_PIN_NO(60) | 7) - -#define MT8173_PIN_61_MSDC0_DAT4__FUNC_GPIO61 (MTK_PIN_NO(61) | 0) -#define MT8173_PIN_61_MSDC0_DAT4__FUNC_MSDC0_DAT4 (MTK_PIN_NO(61) | 1) -#define MT8173_PIN_61_MSDC0_DAT4__FUNC_I2S1_DO_2 (MTK_PIN_NO(61) | 2) -#define MT8173_PIN_61_MSDC0_DAT4__FUNC_DBG_MON_B_11_ (MTK_PIN_NO(61) | 7) - -#define MT8173_PIN_62_MSDC0_DAT5__FUNC_GPIO62 (MTK_PIN_NO(62) | 0) -#define MT8173_PIN_62_MSDC0_DAT5__FUNC_MSDC0_DAT5 (MTK_PIN_NO(62) | 1) -#define MT8173_PIN_62_MSDC0_DAT5__FUNC_I2S2_WS (MTK_PIN_NO(62) | 2) -#define MT8173_PIN_62_MSDC0_DAT5__FUNC_DBG_MON_B_12_ (MTK_PIN_NO(62) | 7) - -#define MT8173_PIN_63_MSDC0_DAT6__FUNC_GPIO63 (MTK_PIN_NO(63) | 0) -#define MT8173_PIN_63_MSDC0_DAT6__FUNC_MSDC0_DAT6 (MTK_PIN_NO(63) | 1) -#define MT8173_PIN_63_MSDC0_DAT6__FUNC_I2S2_BCK (MTK_PIN_NO(63) | 2) -#define MT8173_PIN_63_MSDC0_DAT6__FUNC_DBG_MON_B_13_ (MTK_PIN_NO(63) | 7) - -#define MT8173_PIN_64_MSDC0_DAT7__FUNC_GPIO64 (MTK_PIN_NO(64) | 0) -#define MT8173_PIN_64_MSDC0_DAT7__FUNC_MSDC0_DAT7 (MTK_PIN_NO(64) | 1) -#define MT8173_PIN_64_MSDC0_DAT7__FUNC_I2S2_DI_1 (MTK_PIN_NO(64) | 2) -#define MT8173_PIN_64_MSDC0_DAT7__FUNC_DBG_MON_B_14_ (MTK_PIN_NO(64) | 7) - -#define MT8173_PIN_65_MSDC0_CLK__FUNC_GPIO65 (MTK_PIN_NO(65) | 0) -#define MT8173_PIN_65_MSDC0_CLK__FUNC_MSDC0_CLK (MTK_PIN_NO(65) | 1) -#define MT8173_PIN_65_MSDC0_CLK__FUNC_DBG_MON_B_16_ (MTK_PIN_NO(65) | 7) - -#define MT8173_PIN_66_MSDC0_CMD__FUNC_GPIO66 (MTK_PIN_NO(66) | 0) -#define MT8173_PIN_66_MSDC0_CMD__FUNC_MSDC0_CMD (MTK_PIN_NO(66) | 1) -#define MT8173_PIN_66_MSDC0_CMD__FUNC_I2S2_DI_2 (MTK_PIN_NO(66) | 2) -#define MT8173_PIN_66_MSDC0_CMD__FUNC_DBG_MON_B_15_ (MTK_PIN_NO(66) | 7) - -#define MT8173_PIN_67_MSDC0_DSL__FUNC_GPIO67 (MTK_PIN_NO(67) | 0) -#define MT8173_PIN_67_MSDC0_DSL__FUNC_MSDC0_DSL (MTK_PIN_NO(67) | 1) -#define MT8173_PIN_67_MSDC0_DSL__FUNC_DBG_MON_B_17_ (MTK_PIN_NO(67) | 7) - -#define MT8173_PIN_68_MSDC0_RST___FUNC_GPIO68 (MTK_PIN_NO(68) | 0) -#define MT8173_PIN_68_MSDC0_RST___FUNC_MSDC0_RSTB (MTK_PIN_NO(68) | 1) -#define MT8173_PIN_68_MSDC0_RST___FUNC_I2S2_MCK (MTK_PIN_NO(68) | 2) -#define MT8173_PIN_68_MSDC0_RST___FUNC_DBG_MON_B_18_ (MTK_PIN_NO(68) | 7) - -#define MT8173_PIN_69_SPI_CK__FUNC_GPIO69 (MTK_PIN_NO(69) | 0) -#define MT8173_PIN_69_SPI_CK__FUNC_SPI_CK_0_ (MTK_PIN_NO(69) | 1) -#define MT8173_PIN_69_SPI_CK__FUNC_I2S3_DO_1 (MTK_PIN_NO(69) | 2) -#define MT8173_PIN_69_SPI_CK__FUNC_PWM0 (MTK_PIN_NO(69) | 3) -#define MT8173_PIN_69_SPI_CK__FUNC_PWM5 (MTK_PIN_NO(69) | 4) -#define MT8173_PIN_69_SPI_CK__FUNC_I2S2_MCK (MTK_PIN_NO(69) | 5) -#define MT8173_PIN_69_SPI_CK__FUNC_DBG_MON_B_19_ (MTK_PIN_NO(69) | 7) - -#define MT8173_PIN_70_SPI_MI__FUNC_GPIO70 (MTK_PIN_NO(70) | 0) -#define MT8173_PIN_70_SPI_MI__FUNC_SPI_MI_0_ (MTK_PIN_NO(70) | 1) -#define MT8173_PIN_70_SPI_MI__FUNC_I2S3_DO_2 (MTK_PIN_NO(70) | 2) -#define MT8173_PIN_70_SPI_MI__FUNC_PWM1 (MTK_PIN_NO(70) | 3) -#define MT8173_PIN_70_SPI_MI__FUNC_SPI_MO_0_ (MTK_PIN_NO(70) | 4) -#define MT8173_PIN_70_SPI_MI__FUNC_I2S2_DI_1 (MTK_PIN_NO(70) | 5) -#define MT8173_PIN_70_SPI_MI__FUNC_DSI1_TE (MTK_PIN_NO(70) | 6) -#define MT8173_PIN_70_SPI_MI__FUNC_DBG_MON_B_20_ (MTK_PIN_NO(70) | 7) - -#define MT8173_PIN_71_SPI_MO__FUNC_GPIO71 (MTK_PIN_NO(71) | 0) -#define MT8173_PIN_71_SPI_MO__FUNC_SPI_MO_0_ (MTK_PIN_NO(71) | 1) -#define MT8173_PIN_71_SPI_MO__FUNC_I2S3_DO_3 (MTK_PIN_NO(71) | 2) -#define MT8173_PIN_71_SPI_MO__FUNC_PWM2 (MTK_PIN_NO(71) | 3) -#define MT8173_PIN_71_SPI_MO__FUNC_SPI_MI_0_ (MTK_PIN_NO(71) | 4) -#define MT8173_PIN_71_SPI_MO__FUNC_I2S2_DI_2 (MTK_PIN_NO(71) | 5) -#define MT8173_PIN_71_SPI_MO__FUNC_DBG_MON_B_21_ (MTK_PIN_NO(71) | 7) - -#define MT8173_PIN_72_SPI_CS__FUNC_GPIO72 (MTK_PIN_NO(72) | 0) -#define MT8173_PIN_72_SPI_CS__FUNC_SPI_CS_0_ (MTK_PIN_NO(72) | 1) -#define MT8173_PIN_72_SPI_CS__FUNC_I2S3_DO_4 (MTK_PIN_NO(72) | 2) -#define MT8173_PIN_72_SPI_CS__FUNC_PWM3 (MTK_PIN_NO(72) | 3) -#define MT8173_PIN_72_SPI_CS__FUNC_PWM6 (MTK_PIN_NO(72) | 4) -#define MT8173_PIN_72_SPI_CS__FUNC_DISP_PWM1 (MTK_PIN_NO(72) | 5) -#define MT8173_PIN_72_SPI_CS__FUNC_DBG_MON_B_22_ (MTK_PIN_NO(72) | 7) - -#define MT8173_PIN_73_MSDC1_DAT0__FUNC_GPIO73 (MTK_PIN_NO(73) | 0) -#define MT8173_PIN_73_MSDC1_DAT0__FUNC_MSDC1_DAT0 (MTK_PIN_NO(73) | 1) -#define MT8173_PIN_73_MSDC1_DAT0__FUNC_DBG_MON_B_24_ (MTK_PIN_NO(73) | 7) - -#define MT8173_PIN_74_MSDC1_DAT1__FUNC_GPIO74 (MTK_PIN_NO(74) | 0) -#define MT8173_PIN_74_MSDC1_DAT1__FUNC_MSDC1_DAT1 (MTK_PIN_NO(74) | 1) -#define MT8173_PIN_74_MSDC1_DAT1__FUNC_DBG_MON_B_25_ (MTK_PIN_NO(74) | 7) - -#define MT8173_PIN_75_MSDC1_DAT2__FUNC_GPIO75 (MTK_PIN_NO(75) | 0) -#define MT8173_PIN_75_MSDC1_DAT2__FUNC_MSDC1_DAT2 (MTK_PIN_NO(75) | 1) -#define MT8173_PIN_75_MSDC1_DAT2__FUNC_DBG_MON_B_26_ (MTK_PIN_NO(75) | 7) - -#define MT8173_PIN_76_MSDC1_DAT3__FUNC_GPIO76 (MTK_PIN_NO(76) | 0) -#define MT8173_PIN_76_MSDC1_DAT3__FUNC_MSDC1_DAT3 (MTK_PIN_NO(76) | 1) -#define MT8173_PIN_76_MSDC1_DAT3__FUNC_DBG_MON_B_27_ (MTK_PIN_NO(76) | 7) - -#define MT8173_PIN_77_MSDC1_CLK__FUNC_GPIO77 (MTK_PIN_NO(77) | 0) -#define MT8173_PIN_77_MSDC1_CLK__FUNC_MSDC1_CLK (MTK_PIN_NO(77) | 1) -#define MT8173_PIN_77_MSDC1_CLK__FUNC_DBG_MON_B_28_ (MTK_PIN_NO(77) | 7) - -#define MT8173_PIN_78_MSDC1_CMD__FUNC_GPIO78 (MTK_PIN_NO(78) | 0) -#define MT8173_PIN_78_MSDC1_CMD__FUNC_MSDC1_CMD (MTK_PIN_NO(78) | 1) -#define MT8173_PIN_78_MSDC1_CMD__FUNC_DBG_MON_B_23_ (MTK_PIN_NO(78) | 7) - -#define MT8173_PIN_79_PWRAP_SPI0_MI__FUNC_GPIO79 (MTK_PIN_NO(79) | 0) -#define MT8173_PIN_79_PWRAP_SPI0_MI__FUNC_PWRAP_SPIMI (MTK_PIN_NO(79) | 1) -#define MT8173_PIN_79_PWRAP_SPI0_MI__FUNC_PWRAP_SPIMO (MTK_PIN_NO(79) | 2) - -#define MT8173_PIN_80_PWRAP_SPI0_MO__FUNC_GPIO80 (MTK_PIN_NO(80) | 0) -#define MT8173_PIN_80_PWRAP_SPI0_MO__FUNC_PWRAP_SPIMO (MTK_PIN_NO(80) | 1) -#define MT8173_PIN_80_PWRAP_SPI0_MO__FUNC_PWRAP_SPIMI (MTK_PIN_NO(80) | 2) - -#define MT8173_PIN_81_PWRAP_SPI0_CK__FUNC_GPIO81 (MTK_PIN_NO(81) | 0) -#define MT8173_PIN_81_PWRAP_SPI0_CK__FUNC_PWRAP_SPICK (MTK_PIN_NO(81) | 1) - -#define MT8173_PIN_82_PWRAP_SPI0_CSN__FUNC_GPIO82 (MTK_PIN_NO(82) | 0) -#define MT8173_PIN_82_PWRAP_SPI0_CSN__FUNC_PWRAP_SPICS (MTK_PIN_NO(82) | 1) - -#define MT8173_PIN_83_AUD_CLK_MOSI__FUNC_GPIO83 (MTK_PIN_NO(83) | 0) -#define MT8173_PIN_83_AUD_CLK_MOSI__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(83) | 1) - -#define MT8173_PIN_84_AUD_DAT_MISO__FUNC_GPIO84 (MTK_PIN_NO(84) | 0) -#define MT8173_PIN_84_AUD_DAT_MISO__FUNC_AUD_DAT_MISO (MTK_PIN_NO(84) | 1) -#define MT8173_PIN_84_AUD_DAT_MISO__FUNC_AUD_DAT_MOSI (MTK_PIN_NO(84) | 2) - -#define MT8173_PIN_85_AUD_DAT_MOSI__FUNC_GPIO85 (MTK_PIN_NO(85) | 0) -#define MT8173_PIN_85_AUD_DAT_MOSI__FUNC_AUD_DAT_MOSI (MTK_PIN_NO(85) | 1) -#define MT8173_PIN_85_AUD_DAT_MOSI__FUNC_AUD_DAT_MISO (MTK_PIN_NO(85) | 2) - -#define MT8173_PIN_86_RTC32K_CK__FUNC_GPIO86 (MTK_PIN_NO(86) | 0) -#define MT8173_PIN_86_RTC32K_CK__FUNC_RTC32K_CK (MTK_PIN_NO(86) | 1) - -#define MT8173_PIN_87_DISP_PWM0__FUNC_GPIO87 (MTK_PIN_NO(87) | 0) -#define MT8173_PIN_87_DISP_PWM0__FUNC_DISP_PWM0 (MTK_PIN_NO(87) | 1) -#define MT8173_PIN_87_DISP_PWM0__FUNC_DISP_PWM1 (MTK_PIN_NO(87) | 2) -#define MT8173_PIN_87_DISP_PWM0__FUNC_DBG_MON_B_31_ (MTK_PIN_NO(87) | 7) - -#define MT8173_PIN_88_SRCLKENAI__FUNC_GPIO88 (MTK_PIN_NO(88) | 0) -#define MT8173_PIN_88_SRCLKENAI__FUNC_SRCLKENAI (MTK_PIN_NO(88) | 1) - -#define MT8173_PIN_89_SRCLKENAI2__FUNC_GPIO89 (MTK_PIN_NO(89) | 0) -#define MT8173_PIN_89_SRCLKENAI2__FUNC_SRCLKENAI2 (MTK_PIN_NO(89) | 1) - -#define MT8173_PIN_90_SRCLKENA0__FUNC_GPIO90 (MTK_PIN_NO(90) | 0) -#define MT8173_PIN_90_SRCLKENA0__FUNC_SRCLKENA0 (MTK_PIN_NO(90) | 1) - -#define MT8173_PIN_91_SRCLKENA1__FUNC_GPIO91 (MTK_PIN_NO(91) | 0) -#define MT8173_PIN_91_SRCLKENA1__FUNC_SRCLKENA1 (MTK_PIN_NO(91) | 1) - -#define MT8173_PIN_92_PCM_CLK__FUNC_GPIO92 (MTK_PIN_NO(92) | 0) -#define MT8173_PIN_92_PCM_CLK__FUNC_PCM1_CLK (MTK_PIN_NO(92) | 1) -#define MT8173_PIN_92_PCM_CLK__FUNC_I2S0_BCK (MTK_PIN_NO(92) | 2) -#define MT8173_PIN_92_PCM_CLK__FUNC_DBG_MON_A_24_ (MTK_PIN_NO(92) | 7) - -#define MT8173_PIN_93_PCM_SYNC__FUNC_GPIO93 (MTK_PIN_NO(93) | 0) -#define MT8173_PIN_93_PCM_SYNC__FUNC_PCM1_SYNC (MTK_PIN_NO(93) | 1) -#define MT8173_PIN_93_PCM_SYNC__FUNC_I2S0_WS (MTK_PIN_NO(93) | 2) -#define MT8173_PIN_93_PCM_SYNC__FUNC_DBG_MON_A_25_ (MTK_PIN_NO(93) | 7) - -#define MT8173_PIN_94_PCM_RX__FUNC_GPIO94 (MTK_PIN_NO(94) | 0) -#define MT8173_PIN_94_PCM_RX__FUNC_PCM1_DI (MTK_PIN_NO(94) | 1) -#define MT8173_PIN_94_PCM_RX__FUNC_I2S0_DI (MTK_PIN_NO(94) | 2) -#define MT8173_PIN_94_PCM_RX__FUNC_DBG_MON_A_26_ (MTK_PIN_NO(94) | 7) - -#define MT8173_PIN_95_PCM_TX__FUNC_GPIO95 (MTK_PIN_NO(95) | 0) -#define MT8173_PIN_95_PCM_TX__FUNC_PCM1_DO (MTK_PIN_NO(95) | 1) -#define MT8173_PIN_95_PCM_TX__FUNC_I2S0_DO (MTK_PIN_NO(95) | 2) -#define MT8173_PIN_95_PCM_TX__FUNC_DBG_MON_A_27_ (MTK_PIN_NO(95) | 7) - -#define MT8173_PIN_96_URXD1__FUNC_GPIO96 (MTK_PIN_NO(96) | 0) -#define MT8173_PIN_96_URXD1__FUNC_URXD1 (MTK_PIN_NO(96) | 1) -#define MT8173_PIN_96_URXD1__FUNC_UTXD1 (MTK_PIN_NO(96) | 2) -#define MT8173_PIN_96_URXD1__FUNC_DBG_MON_A_28_ (MTK_PIN_NO(96) | 7) - -#define MT8173_PIN_97_UTXD1__FUNC_GPIO97 (MTK_PIN_NO(97) | 0) -#define MT8173_PIN_97_UTXD1__FUNC_UTXD1 (MTK_PIN_NO(97) | 1) -#define MT8173_PIN_97_UTXD1__FUNC_URXD1 (MTK_PIN_NO(97) | 2) -#define MT8173_PIN_97_UTXD1__FUNC_DBG_MON_A_29_ (MTK_PIN_NO(97) | 7) - -#define MT8173_PIN_98_URTS1__FUNC_GPIO98 (MTK_PIN_NO(98) | 0) -#define MT8173_PIN_98_URTS1__FUNC_URTS1 (MTK_PIN_NO(98) | 1) -#define MT8173_PIN_98_URTS1__FUNC_UCTS1 (MTK_PIN_NO(98) | 2) -#define MT8173_PIN_98_URTS1__FUNC_DBG_MON_A_30_ (MTK_PIN_NO(98) | 7) - -#define MT8173_PIN_99_UCTS1__FUNC_GPIO99 (MTK_PIN_NO(99) | 0) -#define MT8173_PIN_99_UCTS1__FUNC_UCTS1 (MTK_PIN_NO(99) | 1) -#define MT8173_PIN_99_UCTS1__FUNC_URTS1 (MTK_PIN_NO(99) | 2) -#define MT8173_PIN_99_UCTS1__FUNC_DBG_MON_A_31_ (MTK_PIN_NO(99) | 7) - -#define MT8173_PIN_100_MSDC2_DAT0__FUNC_GPIO100 (MTK_PIN_NO(100) | 0) -#define MT8173_PIN_100_MSDC2_DAT0__FUNC_MSDC2_DAT0 (MTK_PIN_NO(100) | 1) -#define MT8173_PIN_100_MSDC2_DAT0__FUNC_USB_DRVVBUS_P0 (MTK_PIN_NO(100) | 3) -#define MT8173_PIN_100_MSDC2_DAT0__FUNC_SDA5 (MTK_PIN_NO(100) | 4) -#define MT8173_PIN_100_MSDC2_DAT0__FUNC_USB_DRVVBUS_P1 (MTK_PIN_NO(100) | 5) -#define MT8173_PIN_100_MSDC2_DAT0__FUNC_DBG_MON_B_0_ (MTK_PIN_NO(100) | 7) - -#define MT8173_PIN_101_MSDC2_DAT1__FUNC_GPIO101 (MTK_PIN_NO(101) | 0) -#define MT8173_PIN_101_MSDC2_DAT1__FUNC_MSDC2_DAT1 (MTK_PIN_NO(101) | 1) -#define MT8173_PIN_101_MSDC2_DAT1__FUNC_AUD_SPDIF (MTK_PIN_NO(101) | 3) -#define MT8173_PIN_101_MSDC2_DAT1__FUNC_SCL5 (MTK_PIN_NO(101) | 4) -#define MT8173_PIN_101_MSDC2_DAT1__FUNC_DBG_MON_B_1_ (MTK_PIN_NO(101) | 7) - -#define MT8173_PIN_102_MSDC2_DAT2__FUNC_GPIO102 (MTK_PIN_NO(102) | 0) -#define MT8173_PIN_102_MSDC2_DAT2__FUNC_MSDC2_DAT2 (MTK_PIN_NO(102) | 1) -#define MT8173_PIN_102_MSDC2_DAT2__FUNC_UTXD0 (MTK_PIN_NO(102) | 3) -#define MT8173_PIN_102_MSDC2_DAT2__FUNC_PWM0 (MTK_PIN_NO(102) | 5) -#define MT8173_PIN_102_MSDC2_DAT2__FUNC_SPI_CK_1_ (MTK_PIN_NO(102) | 6) -#define MT8173_PIN_102_MSDC2_DAT2__FUNC_DBG_MON_B_2_ (MTK_PIN_NO(102) | 7) - -#define MT8173_PIN_103_MSDC2_DAT3__FUNC_GPIO103 (MTK_PIN_NO(103) | 0) -#define MT8173_PIN_103_MSDC2_DAT3__FUNC_MSDC2_DAT3 (MTK_PIN_NO(103) | 1) -#define MT8173_PIN_103_MSDC2_DAT3__FUNC_URXD0 (MTK_PIN_NO(103) | 3) -#define MT8173_PIN_103_MSDC2_DAT3__FUNC_PWM1 (MTK_PIN_NO(103) | 5) -#define MT8173_PIN_103_MSDC2_DAT3__FUNC_SPI_MI_1_ (MTK_PIN_NO(103) | 6) -#define MT8173_PIN_103_MSDC2_DAT3__FUNC_DBG_MON_B_3_ (MTK_PIN_NO(103) | 7) - -#define MT8173_PIN_104_MSDC2_CLK__FUNC_GPIO104 (MTK_PIN_NO(104) | 0) -#define MT8173_PIN_104_MSDC2_CLK__FUNC_MSDC2_CLK (MTK_PIN_NO(104) | 1) -#define MT8173_PIN_104_MSDC2_CLK__FUNC_UTXD3 (MTK_PIN_NO(104) | 3) -#define MT8173_PIN_104_MSDC2_CLK__FUNC_SDA3 (MTK_PIN_NO(104) | 4) -#define MT8173_PIN_104_MSDC2_CLK__FUNC_PWM2 (MTK_PIN_NO(104) | 5) -#define MT8173_PIN_104_MSDC2_CLK__FUNC_SPI_MO_1_ (MTK_PIN_NO(104) | 6) -#define MT8173_PIN_104_MSDC2_CLK__FUNC_DBG_MON_B_4_ (MTK_PIN_NO(104) | 7) - -#define MT8173_PIN_105_MSDC2_CMD__FUNC_GPIO105 (MTK_PIN_NO(105) | 0) -#define MT8173_PIN_105_MSDC2_CMD__FUNC_MSDC2_CMD (MTK_PIN_NO(105) | 1) -#define MT8173_PIN_105_MSDC2_CMD__FUNC_URXD3 (MTK_PIN_NO(105) | 3) -#define MT8173_PIN_105_MSDC2_CMD__FUNC_SCL3 (MTK_PIN_NO(105) | 4) -#define MT8173_PIN_105_MSDC2_CMD__FUNC_PWM3 (MTK_PIN_NO(105) | 5) -#define MT8173_PIN_105_MSDC2_CMD__FUNC_SPI_CS_1_ (MTK_PIN_NO(105) | 6) -#define MT8173_PIN_105_MSDC2_CMD__FUNC_DBG_MON_B_5_ (MTK_PIN_NO(105) | 7) - -#define MT8173_PIN_106_SDA3__FUNC_GPIO106 (MTK_PIN_NO(106) | 0) -#define MT8173_PIN_106_SDA3__FUNC_SDA3 (MTK_PIN_NO(106) | 1) - -#define MT8173_PIN_107_SCL3__FUNC_GPIO107 (MTK_PIN_NO(107) | 0) -#define MT8173_PIN_107_SCL3__FUNC_SCL3 (MTK_PIN_NO(107) | 1) - -#define MT8173_PIN_108_JTMS__FUNC_GPIO108 (MTK_PIN_NO(108) | 0) -#define MT8173_PIN_108_JTMS__FUNC_JTMS (MTK_PIN_NO(108) | 1) -#define MT8173_PIN_108_JTMS__FUNC_MFG_JTAG_TMS (MTK_PIN_NO(108) | 2) -#define MT8173_PIN_108_JTMS__FUNC_AP_MD32_JTAG_TMS (MTK_PIN_NO(108) | 5) -#define MT8173_PIN_108_JTMS__FUNC_DFD_TMS (MTK_PIN_NO(108) | 6) - -#define MT8173_PIN_109_JTCK__FUNC_GPIO109 (MTK_PIN_NO(109) | 0) -#define MT8173_PIN_109_JTCK__FUNC_JTCK (MTK_PIN_NO(109) | 1) -#define MT8173_PIN_109_JTCK__FUNC_MFG_JTAG_TCK (MTK_PIN_NO(109) | 2) -#define MT8173_PIN_109_JTCK__FUNC_AP_MD32_JTAG_TCK (MTK_PIN_NO(109) | 5) -#define MT8173_PIN_109_JTCK__FUNC_DFD_TCK (MTK_PIN_NO(109) | 6) - -#define MT8173_PIN_110_JTDI__FUNC_GPIO110 (MTK_PIN_NO(110) | 0) -#define MT8173_PIN_110_JTDI__FUNC_JTDI (MTK_PIN_NO(110) | 1) -#define MT8173_PIN_110_JTDI__FUNC_MFG_JTAG_TDI (MTK_PIN_NO(110) | 2) -#define MT8173_PIN_110_JTDI__FUNC_AP_MD32_JTAG_TDI (MTK_PIN_NO(110) | 5) -#define MT8173_PIN_110_JTDI__FUNC_DFD_TDI (MTK_PIN_NO(110) | 6) - -#define MT8173_PIN_111_JTDO__FUNC_GPIO111 (MTK_PIN_NO(111) | 0) -#define MT8173_PIN_111_JTDO__FUNC_JTDO (MTK_PIN_NO(111) | 1) -#define MT8173_PIN_111_JTDO__FUNC_MFG_JTAG_TDO (MTK_PIN_NO(111) | 2) -#define MT8173_PIN_111_JTDO__FUNC_AP_MD32_JTAG_TDO (MTK_PIN_NO(111) | 5) -#define MT8173_PIN_111_JTDO__FUNC_DFD_TDO (MTK_PIN_NO(111) | 6) - -#define MT8173_PIN_112_JTRST_B__FUNC_GPIO112 (MTK_PIN_NO(112) | 0) -#define MT8173_PIN_112_JTRST_B__FUNC_JTRST_B (MTK_PIN_NO(112) | 1) -#define MT8173_PIN_112_JTRST_B__FUNC_MFG_JTAG_TRSTN (MTK_PIN_NO(112) | 2) -#define MT8173_PIN_112_JTRST_B__FUNC_AP_MD32_JTAG_TRST (MTK_PIN_NO(112) | 5) -#define MT8173_PIN_112_JTRST_B__FUNC_DFD_NTRST (MTK_PIN_NO(112) | 6) - -#define MT8173_PIN_113_URXD0__FUNC_GPIO113 (MTK_PIN_NO(113) | 0) -#define MT8173_PIN_113_URXD0__FUNC_URXD0 (MTK_PIN_NO(113) | 1) -#define MT8173_PIN_113_URXD0__FUNC_UTXD0 (MTK_PIN_NO(113) | 2) -#define MT8173_PIN_113_URXD0__FUNC_I2S2_WS (MTK_PIN_NO(113) | 6) -#define MT8173_PIN_113_URXD0__FUNC_DBG_MON_A_0_ (MTK_PIN_NO(113) | 7) - -#define MT8173_PIN_114_UTXD0__FUNC_GPIO114 (MTK_PIN_NO(114) | 0) -#define MT8173_PIN_114_UTXD0__FUNC_UTXD0 (MTK_PIN_NO(114) | 1) -#define MT8173_PIN_114_UTXD0__FUNC_URXD0 (MTK_PIN_NO(114) | 2) -#define MT8173_PIN_114_UTXD0__FUNC_I2S2_BCK (MTK_PIN_NO(114) | 6) -#define MT8173_PIN_114_UTXD0__FUNC_DBG_MON_A_1_ (MTK_PIN_NO(114) | 7) - -#define MT8173_PIN_115_URTS0__FUNC_GPIO115 (MTK_PIN_NO(115) | 0) -#define MT8173_PIN_115_URTS0__FUNC_URTS0 (MTK_PIN_NO(115) | 1) -#define MT8173_PIN_115_URTS0__FUNC_UCTS0 (MTK_PIN_NO(115) | 2) -#define MT8173_PIN_115_URTS0__FUNC_I2S2_MCK (MTK_PIN_NO(115) | 6) -#define MT8173_PIN_115_URTS0__FUNC_DBG_MON_A_2_ (MTK_PIN_NO(115) | 7) - -#define MT8173_PIN_116_UCTS0__FUNC_GPIO116 (MTK_PIN_NO(116) | 0) -#define MT8173_PIN_116_UCTS0__FUNC_UCTS0 (MTK_PIN_NO(116) | 1) -#define MT8173_PIN_116_UCTS0__FUNC_URTS0 (MTK_PIN_NO(116) | 2) -#define MT8173_PIN_116_UCTS0__FUNC_I2S2_DI_1 (MTK_PIN_NO(116) | 6) -#define MT8173_PIN_116_UCTS0__FUNC_DBG_MON_A_3_ (MTK_PIN_NO(116) | 7) - -#define MT8173_PIN_117_URXD3__FUNC_GPIO117 (MTK_PIN_NO(117) | 0) -#define MT8173_PIN_117_URXD3__FUNC_URXD3 (MTK_PIN_NO(117) | 1) -#define MT8173_PIN_117_URXD3__FUNC_UTXD3 (MTK_PIN_NO(117) | 2) -#define MT8173_PIN_117_URXD3__FUNC_DBG_MON_A_9_ (MTK_PIN_NO(117) | 7) - -#define MT8173_PIN_118_UTXD3__FUNC_GPIO118 (MTK_PIN_NO(118) | 0) -#define MT8173_PIN_118_UTXD3__FUNC_UTXD3 (MTK_PIN_NO(118) | 1) -#define MT8173_PIN_118_UTXD3__FUNC_URXD3 (MTK_PIN_NO(118) | 2) -#define MT8173_PIN_118_UTXD3__FUNC_DBG_MON_A_10_ (MTK_PIN_NO(118) | 7) - -#define MT8173_PIN_119_KPROW0__FUNC_GPIO119 (MTK_PIN_NO(119) | 0) -#define MT8173_PIN_119_KPROW0__FUNC_KROW0 (MTK_PIN_NO(119) | 1) -#define MT8173_PIN_119_KPROW0__FUNC_DBG_MON_A_11_ (MTK_PIN_NO(119) | 7) - -#define MT8173_PIN_120_KPROW1__FUNC_GPIO120 (MTK_PIN_NO(120) | 0) -#define MT8173_PIN_120_KPROW1__FUNC_KROW1 (MTK_PIN_NO(120) | 1) -#define MT8173_PIN_120_KPROW1__FUNC_PWM6 (MTK_PIN_NO(120) | 3) -#define MT8173_PIN_120_KPROW1__FUNC_DBG_MON_A_12_ (MTK_PIN_NO(120) | 7) - -#define MT8173_PIN_121_KPROW2__FUNC_GPIO121 (MTK_PIN_NO(121) | 0) -#define MT8173_PIN_121_KPROW2__FUNC_KROW2 (MTK_PIN_NO(121) | 1) -#define MT8173_PIN_121_KPROW2__FUNC_IRDA_PDN (MTK_PIN_NO(121) | 2) -#define MT8173_PIN_121_KPROW2__FUNC_USB_DRVVBUS_P0 (MTK_PIN_NO(121) | 3) -#define MT8173_PIN_121_KPROW2__FUNC_PWM4 (MTK_PIN_NO(121) | 4) -#define MT8173_PIN_121_KPROW2__FUNC_USB_DRVVBUS_P1 (MTK_PIN_NO(121) | 5) -#define MT8173_PIN_121_KPROW2__FUNC_DBG_MON_A_13_ (MTK_PIN_NO(121) | 7) - -#define MT8173_PIN_122_KPCOL0__FUNC_GPIO122 (MTK_PIN_NO(122) | 0) -#define MT8173_PIN_122_KPCOL0__FUNC_KCOL0 (MTK_PIN_NO(122) | 1) -#define MT8173_PIN_122_KPCOL0__FUNC_DBG_MON_A_14_ (MTK_PIN_NO(122) | 7) - -#define MT8173_PIN_123_KPCOL1__FUNC_GPIO123 (MTK_PIN_NO(123) | 0) -#define MT8173_PIN_123_KPCOL1__FUNC_KCOL1 (MTK_PIN_NO(123) | 1) -#define MT8173_PIN_123_KPCOL1__FUNC_IRDA_RXD (MTK_PIN_NO(123) | 2) -#define MT8173_PIN_123_KPCOL1__FUNC_PWM5 (MTK_PIN_NO(123) | 3) -#define MT8173_PIN_123_KPCOL1__FUNC_DBG_MON_A_15_ (MTK_PIN_NO(123) | 7) - -#define MT8173_PIN_124_KPCOL2__FUNC_GPIO124 (MTK_PIN_NO(124) | 0) -#define MT8173_PIN_124_KPCOL2__FUNC_KCOL2 (MTK_PIN_NO(124) | 1) -#define MT8173_PIN_124_KPCOL2__FUNC_IRDA_TXD (MTK_PIN_NO(124) | 2) -#define MT8173_PIN_124_KPCOL2__FUNC_USB_DRVVBUS_P0 (MTK_PIN_NO(124) | 3) -#define MT8173_PIN_124_KPCOL2__FUNC_PWM3 (MTK_PIN_NO(124) | 4) -#define MT8173_PIN_124_KPCOL2__FUNC_USB_DRVVBUS_P1 (MTK_PIN_NO(124) | 5) -#define MT8173_PIN_124_KPCOL2__FUNC_DBG_MON_A_16_ (MTK_PIN_NO(124) | 7) - -#define MT8173_PIN_125_SDA1__FUNC_GPIO125 (MTK_PIN_NO(125) | 0) -#define MT8173_PIN_125_SDA1__FUNC_SDA1 (MTK_PIN_NO(125) | 1) - -#define MT8173_PIN_126_SCL1__FUNC_GPIO126 (MTK_PIN_NO(126) | 0) -#define MT8173_PIN_126_SCL1__FUNC_SCL1 (MTK_PIN_NO(126) | 1) - -#define MT8173_PIN_127_LCM_RST__FUNC_GPIO127 (MTK_PIN_NO(127) | 0) -#define MT8173_PIN_127_LCM_RST__FUNC_LCM_RST (MTK_PIN_NO(127) | 1) - -#define MT8173_PIN_128_I2S0_LRCK__FUNC_GPIO128 (MTK_PIN_NO(128) | 0) -#define MT8173_PIN_128_I2S0_LRCK__FUNC_I2S0_WS (MTK_PIN_NO(128) | 1) -#define MT8173_PIN_128_I2S0_LRCK__FUNC_I2S1_WS (MTK_PIN_NO(128) | 2) -#define MT8173_PIN_128_I2S0_LRCK__FUNC_I2S2_WS (MTK_PIN_NO(128) | 3) -#define MT8173_PIN_128_I2S0_LRCK__FUNC_SPI_CK_2_ (MTK_PIN_NO(128) | 5) -#define MT8173_PIN_128_I2S0_LRCK__FUNC_DBG_MON_A_4_ (MTK_PIN_NO(128) | 7) - -#define MT8173_PIN_129_I2S0_BCK__FUNC_GPIO129 (MTK_PIN_NO(129) | 0) -#define MT8173_PIN_129_I2S0_BCK__FUNC_I2S0_BCK (MTK_PIN_NO(129) | 1) -#define MT8173_PIN_129_I2S0_BCK__FUNC_I2S1_BCK (MTK_PIN_NO(129) | 2) -#define MT8173_PIN_129_I2S0_BCK__FUNC_I2S2_BCK (MTK_PIN_NO(129) | 3) -#define MT8173_PIN_129_I2S0_BCK__FUNC_SPI_MI_2_ (MTK_PIN_NO(129) | 5) -#define MT8173_PIN_129_I2S0_BCK__FUNC_DBG_MON_A_5_ (MTK_PIN_NO(129) | 7) - -#define MT8173_PIN_130_I2S0_MCK__FUNC_GPIO130 (MTK_PIN_NO(130) | 0) -#define MT8173_PIN_130_I2S0_MCK__FUNC_I2S0_MCK (MTK_PIN_NO(130) | 1) -#define MT8173_PIN_130_I2S0_MCK__FUNC_I2S1_MCK (MTK_PIN_NO(130) | 2) -#define MT8173_PIN_130_I2S0_MCK__FUNC_I2S2_MCK (MTK_PIN_NO(130) | 3) -#define MT8173_PIN_130_I2S0_MCK__FUNC_SPI_MO_2_ (MTK_PIN_NO(130) | 5) -#define MT8173_PIN_130_I2S0_MCK__FUNC_DBG_MON_A_6_ (MTK_PIN_NO(130) | 7) - -#define MT8173_PIN_131_I2S0_DATA0__FUNC_GPIO131 (MTK_PIN_NO(131) | 0) -#define MT8173_PIN_131_I2S0_DATA0__FUNC_I2S0_DO (MTK_PIN_NO(131) | 1) -#define MT8173_PIN_131_I2S0_DATA0__FUNC_I2S1_DO_1 (MTK_PIN_NO(131) | 2) -#define MT8173_PIN_131_I2S0_DATA0__FUNC_I2S2_DI_1 (MTK_PIN_NO(131) | 3) -#define MT8173_PIN_131_I2S0_DATA0__FUNC_SPI_CS_2_ (MTK_PIN_NO(131) | 5) -#define MT8173_PIN_131_I2S0_DATA0__FUNC_DBG_MON_A_7_ (MTK_PIN_NO(131) | 7) - -#define MT8173_PIN_132_I2S0_DATA1__FUNC_GPIO132 (MTK_PIN_NO(132) | 0) -#define MT8173_PIN_132_I2S0_DATA1__FUNC_I2S0_DI (MTK_PIN_NO(132) | 1) -#define MT8173_PIN_132_I2S0_DATA1__FUNC_I2S1_DO_2 (MTK_PIN_NO(132) | 2) -#define MT8173_PIN_132_I2S0_DATA1__FUNC_I2S2_DI_2 (MTK_PIN_NO(132) | 3) -#define MT8173_PIN_132_I2S0_DATA1__FUNC_DBG_MON_A_8_ (MTK_PIN_NO(132) | 7) - -#define MT8173_PIN_133_SDA4__FUNC_GPIO133 (MTK_PIN_NO(133) | 0) -#define MT8173_PIN_133_SDA4__FUNC_SDA4 (MTK_PIN_NO(133) | 1) - -#define MT8173_PIN_134_SCL4__FUNC_GPIO134 (MTK_PIN_NO(134) | 0) -#define MT8173_PIN_134_SCL4__FUNC_SCL4 (MTK_PIN_NO(134) | 1) - -#endif /* __DTS_MT8173_PINFUNC_H */ diff --git a/sys/gnu/dts/arm64/mediatek/mt8173.dtsi b/sys/gnu/dts/arm64/mediatek/mt8173.dtsi deleted file mode 100644 index 8b4e806d511..00000000000 --- a/sys/gnu/dts/arm64/mediatek/mt8173.dtsi +++ /dev/null @@ -1,1439 +0,0 @@ -/* - * Copyright (c) 2014 MediaTek Inc. - * Author: Eddie Huang - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include "mt8173-pinfunc.h" - -/ { - compatible = "mediatek,mt8173"; - interrupt-parent = <&sysirq>; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - ovl0 = &ovl0; - ovl1 = &ovl1; - rdma0 = &rdma0; - rdma1 = &rdma1; - rdma2 = &rdma2; - wdma0 = &wdma0; - wdma1 = &wdma1; - color0 = &color0; - color1 = &color1; - split0 = &split0; - split1 = &split1; - dpi0 = &dpi0; - dsi0 = &dsi0; - dsi1 = &dsi1; - mdp_rdma0 = &mdp_rdma0; - mdp_rdma1 = &mdp_rdma1; - mdp_rsz0 = &mdp_rsz0; - mdp_rsz1 = &mdp_rsz1; - mdp_rsz2 = &mdp_rsz2; - mdp_wdma0 = &mdp_wdma0; - mdp_wrot0 = &mdp_wrot0; - mdp_wrot1 = &mdp_wrot1; - }; - - cluster0_opp: opp_table0 { - compatible = "operating-points-v2"; - opp-shared; - opp-507000000 { - opp-hz = /bits/ 64 <507000000>; - opp-microvolt = <859000>; - }; - opp-702000000 { - opp-hz = /bits/ 64 <702000000>; - opp-microvolt = <908000>; - }; - opp-1001000000 { - opp-hz = /bits/ 64 <1001000000>; - opp-microvolt = <983000>; - }; - opp-1105000000 { - opp-hz = /bits/ 64 <1105000000>; - opp-microvolt = <1009000>; - }; - opp-1209000000 { - opp-hz = /bits/ 64 <1209000000>; - opp-microvolt = <1034000>; - }; - opp-1300000000 { - opp-hz = /bits/ 64 <1300000000>; - opp-microvolt = <1057000>; - }; - opp-1508000000 { - opp-hz = /bits/ 64 <1508000000>; - opp-microvolt = <1109000>; - }; - opp-1703000000 { - opp-hz = /bits/ 64 <1703000000>; - opp-microvolt = <1125000>; - }; - }; - - cluster1_opp: opp_table1 { - compatible = "operating-points-v2"; - opp-shared; - opp-507000000 { - opp-hz = /bits/ 64 <507000000>; - opp-microvolt = <828000>; - }; - opp-702000000 { - opp-hz = /bits/ 64 <702000000>; - opp-microvolt = <867000>; - }; - opp-1001000000 { - opp-hz = /bits/ 64 <1001000000>; - opp-microvolt = <927000>; - }; - opp-1209000000 { - opp-hz = /bits/ 64 <1209000000>; - opp-microvolt = <968000>; - }; - opp-1404000000 { - opp-hz = /bits/ 64 <1404000000>; - opp-microvolt = <1007000>; - }; - opp-1612000000 { - opp-hz = /bits/ 64 <1612000000>; - opp-microvolt = <1049000>; - }; - opp-1807000000 { - opp-hz = /bits/ 64 <1807000000>; - opp-microvolt = <1089000>; - }; - opp-2106000000 { - opp-hz = /bits/ 64 <2106000000>; - opp-microvolt = <1125000>; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu-map { - cluster0 { - core0 { - cpu = <&cpu0>; - }; - core1 { - cpu = <&cpu1>; - }; - }; - - cluster1 { - core0 { - cpu = <&cpu2>; - }; - core1 { - cpu = <&cpu3>; - }; - }; - }; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x000>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - #cooling-cells = <2>; - dynamic-power-coefficient = <263>; - clocks = <&infracfg CLK_INFRA_CA53SEL>, - <&apmixedsys CLK_APMIXED_MAINPLL>; - clock-names = "cpu", "intermediate"; - operating-points-v2 = <&cluster0_opp>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x001>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - #cooling-cells = <2>; - dynamic-power-coefficient = <263>; - clocks = <&infracfg CLK_INFRA_CA53SEL>, - <&apmixedsys CLK_APMIXED_MAINPLL>; - clock-names = "cpu", "intermediate"; - operating-points-v2 = <&cluster0_opp>; - }; - - cpu2: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x100>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - #cooling-cells = <2>; - dynamic-power-coefficient = <530>; - clocks = <&infracfg CLK_INFRA_CA72SEL>, - <&apmixedsys CLK_APMIXED_MAINPLL>; - clock-names = "cpu", "intermediate"; - operating-points-v2 = <&cluster1_opp>; - }; - - cpu3: cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x101>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - #cooling-cells = <2>; - dynamic-power-coefficient = <530>; - clocks = <&infracfg CLK_INFRA_CA72SEL>, - <&apmixedsys CLK_APMIXED_MAINPLL>; - clock-names = "cpu", "intermediate"; - operating-points-v2 = <&cluster1_opp>; - }; - - idle-states { - entry-method = "psci"; - - CPU_SLEEP_0: cpu-sleep-0 { - compatible = "arm,idle-state"; - local-timer-stop; - entry-latency-us = <639>; - exit-latency-us = <680>; - min-residency-us = <1088>; - arm,psci-suspend-param = <0x0010000>; - }; - }; - }; - - pmu_a53 { - compatible = "arm,cortex-a53-pmu"; - interrupts = , - ; - interrupt-affinity = <&cpu0>, <&cpu1>; - }; - - pmu_a72 { - compatible = "arm,cortex-a72-pmu"; - interrupts = , - ; - interrupt-affinity = <&cpu2>, <&cpu3>; - }; - - psci { - compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; - method = "smc"; - cpu_suspend = <0x84000001>; - cpu_off = <0x84000002>; - cpu_on = <0x84000003>; - }; - - clk26m: oscillator@0 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <26000000>; - clock-output-names = "clk26m"; - }; - - clk32k: oscillator@1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32000>; - clock-output-names = "clk32k"; - }; - - cpum_ck: oscillator@2 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - clock-output-names = "cpum_ck"; - }; - - thermal-zones { - cpu_thermal: cpu_thermal { - polling-delay-passive = <1000>; /* milliseconds */ - polling-delay = <1000>; /* milliseconds */ - - thermal-sensors = <&thermal>; - sustainable-power = <1500>; /* milliwatts */ - - trips { - threshold: trip-point@0 { - temperature = <68000>; - hysteresis = <2000>; - type = "passive"; - }; - - target: trip-point@1 { - temperature = <85000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu_crit: cpu_crit@0 { - temperature = <115000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map@0 { - trip = <&target>; - cooling-device = <&cpu0 0 0>, - <&cpu1 0 0>; - contribution = <3072>; - }; - map@1 { - trip = <&target>; - cooling-device = <&cpu2 0 0>, - <&cpu3 0 0>; - contribution = <1024>; - }; - }; - }; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - vpu_dma_reserved: vpu_dma_mem_region { - compatible = "shared-dma-pool"; - reg = <0 0xb7000000 0 0x500000>; - alignment = <0x1000>; - no-map; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupt-parent = <&gic>; - interrupts = , - , - , - ; - }; - - soc { - #address-cells = <2>; - #size-cells = <2>; - compatible = "simple-bus"; - ranges; - - topckgen: clock-controller@10000000 { - compatible = "mediatek,mt8173-topckgen"; - reg = <0 0x10000000 0 0x1000>; - #clock-cells = <1>; - }; - - infracfg: power-controller@10001000 { - compatible = "mediatek,mt8173-infracfg", "syscon"; - reg = <0 0x10001000 0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - pericfg: power-controller@10003000 { - compatible = "mediatek,mt8173-pericfg", "syscon"; - reg = <0 0x10003000 0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - syscfg_pctl_a: syscfg_pctl_a@10005000 { - compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon"; - reg = <0 0x10005000 0 0x1000>; - }; - - pio: pinctrl@10005000 { - compatible = "mediatek,mt8173-pinctrl"; - reg = <0 0x1000b000 0 0x1000>; - mediatek,pctl-regmap = <&syscfg_pctl_a>; - pins-are-numbered; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = , - , - ; - - hdmi_pin: xxx { - - /*hdmi htplg pin*/ - pins1 { - pinmux = ; - input-enable; - bias-pull-down; - }; - }; - - i2c0_pins_a: i2c0 { - pins1 { - pinmux = , - ; - bias-disable; - }; - }; - - i2c1_pins_a: i2c1 { - pins1 { - pinmux = , - ; - bias-disable; - }; - }; - - i2c2_pins_a: i2c2 { - pins1 { - pinmux = , - ; - bias-disable; - }; - }; - - i2c3_pins_a: i2c3 { - pins1 { - pinmux = , - ; - bias-disable; - }; - }; - - i2c4_pins_a: i2c4 { - pins1 { - pinmux = , - ; - bias-disable; - }; - }; - - i2c6_pins_a: i2c6 { - pins1 { - pinmux = , - ; - bias-disable; - }; - }; - }; - - scpsys: scpsys@10006000 { - compatible = "mediatek,mt8173-scpsys"; - #power-domain-cells = <1>; - reg = <0 0x10006000 0 0x1000>; - clocks = <&clk26m>, - <&topckgen CLK_TOP_MM_SEL>, - <&topckgen CLK_TOP_VENC_SEL>, - <&topckgen CLK_TOP_VENC_LT_SEL>; - clock-names = "mfg", "mm", "venc", "venc_lt"; - infracfg = <&infracfg>; - }; - - watchdog: watchdog@10007000 { - compatible = "mediatek,mt8173-wdt", - "mediatek,mt6589-wdt"; - reg = <0 0x10007000 0 0x100>; - }; - - timer: timer@10008000 { - compatible = "mediatek,mt8173-timer", - "mediatek,mt6577-timer"; - reg = <0 0x10008000 0 0x1000>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_CLK_13M>, - <&topckgen CLK_TOP_RTC_SEL>; - }; - - pwrap: pwrap@1000d000 { - compatible = "mediatek,mt8173-pwrap"; - reg = <0 0x1000d000 0 0x1000>; - reg-names = "pwrap"; - interrupts = ; - resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>; - reset-names = "pwrap"; - clocks = <&infracfg CLK_INFRA_PMICSPI>, <&infracfg CLK_INFRA_PMICWRAP>; - clock-names = "spi", "wrap"; - }; - - cec: cec@10013000 { - compatible = "mediatek,mt8173-cec"; - reg = <0 0x10013000 0 0xbc>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_CEC>; - status = "disabled"; - }; - - vpu: vpu@10020000 { - compatible = "mediatek,mt8173-vpu"; - reg = <0 0x10020000 0 0x30000>, - <0 0x10050000 0 0x100>; - reg-names = "tcm", "cfg_reg"; - interrupts = ; - clocks = <&topckgen CLK_TOP_SCP_SEL>; - clock-names = "main"; - memory-region = <&vpu_dma_reserved>; - }; - - sysirq: intpol-controller@10200620 { - compatible = "mediatek,mt8173-sysirq", - "mediatek,mt6577-sysirq"; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - reg = <0 0x10200620 0 0x20>; - }; - - iommu: iommu@10205000 { - compatible = "mediatek,mt8173-m4u"; - reg = <0 0x10205000 0 0x1000>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_M4U>; - clock-names = "bclk"; - mediatek,larbs = <&larb0 &larb1 &larb2 - &larb3 &larb4 &larb5>; - #iommu-cells = <1>; - }; - - efuse: efuse@10206000 { - compatible = "mediatek,mt8173-efuse"; - reg = <0 0x10206000 0 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - thermal_calibration: calib@528 { - reg = <0x528 0xc>; - }; - }; - - apmixedsys: clock-controller@10209000 { - compatible = "mediatek,mt8173-apmixedsys"; - reg = <0 0x10209000 0 0x1000>; - #clock-cells = <1>; - }; - - hdmi_phy: hdmi-phy@10209100 { - compatible = "mediatek,mt8173-hdmi-phy"; - reg = <0 0x10209100 0 0x24>; - clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>; - clock-names = "pll_ref"; - clock-output-names = "hdmitx_dig_cts"; - mediatek,ibias = <0xa>; - mediatek,ibias_up = <0x1c>; - #clock-cells = <0>; - #phy-cells = <0>; - status = "disabled"; - }; - - gce: mailbox@10212000 { - compatible = "mediatek,mt8173-gce"; - reg = <0 0x10212000 0 0x1000>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_GCE>; - clock-names = "gce"; - #mbox-cells = <3>; - }; - - mipi_tx0: mipi-dphy@10215000 { - compatible = "mediatek,mt8173-mipi-tx"; - reg = <0 0x10215000 0 0x1000>; - clocks = <&clk26m>; - clock-output-names = "mipi_tx0_pll"; - #clock-cells = <0>; - #phy-cells = <0>; - status = "disabled"; - }; - - mipi_tx1: mipi-dphy@10216000 { - compatible = "mediatek,mt8173-mipi-tx"; - reg = <0 0x10216000 0 0x1000>; - clocks = <&clk26m>; - clock-output-names = "mipi_tx1_pll"; - #clock-cells = <0>; - #phy-cells = <0>; - status = "disabled"; - }; - - gic: interrupt-controller@10220000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - interrupt-controller; - reg = <0 0x10221000 0 0x1000>, - <0 0x10222000 0 0x2000>, - <0 0x10224000 0 0x2000>, - <0 0x10226000 0 0x2000>; - interrupts = ; - }; - - auxadc: auxadc@11001000 { - compatible = "mediatek,mt8173-auxadc"; - reg = <0 0x11001000 0 0x1000>; - clocks = <&pericfg CLK_PERI_AUXADC>; - clock-names = "main"; - #io-channel-cells = <1>; - }; - - uart0: serial@11002000 { - compatible = "mediatek,mt8173-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11002000 0 0x400>; - interrupts = ; - clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>; - clock-names = "baud", "bus"; - status = "disabled"; - }; - - uart1: serial@11003000 { - compatible = "mediatek,mt8173-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11003000 0 0x400>; - interrupts = ; - clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>; - clock-names = "baud", "bus"; - status = "disabled"; - }; - - uart2: serial@11004000 { - compatible = "mediatek,mt8173-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11004000 0 0x400>; - interrupts = ; - clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>; - clock-names = "baud", "bus"; - status = "disabled"; - }; - - uart3: serial@11005000 { - compatible = "mediatek,mt8173-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11005000 0 0x400>; - interrupts = ; - clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>; - clock-names = "baud", "bus"; - status = "disabled"; - }; - - i2c0: i2c@11007000 { - compatible = "mediatek,mt8173-i2c"; - reg = <0 0x11007000 0 0x70>, - <0 0x11000100 0 0x80>; - interrupts = ; - clock-div = <16>; - clocks = <&pericfg CLK_PERI_I2C0>, - <&pericfg CLK_PERI_AP_DMA>; - clock-names = "main", "dma"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c1: i2c@11008000 { - compatible = "mediatek,mt8173-i2c"; - reg = <0 0x11008000 0 0x70>, - <0 0x11000180 0 0x80>; - interrupts = ; - clock-div = <16>; - clocks = <&pericfg CLK_PERI_I2C1>, - <&pericfg CLK_PERI_AP_DMA>; - clock-names = "main", "dma"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@11009000 { - compatible = "mediatek,mt8173-i2c"; - reg = <0 0x11009000 0 0x70>, - <0 0x11000200 0 0x80>; - interrupts = ; - clock-div = <16>; - clocks = <&pericfg CLK_PERI_I2C2>, - <&pericfg CLK_PERI_AP_DMA>; - clock-names = "main", "dma"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi: spi@1100a000 { - compatible = "mediatek,mt8173-spi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0 0x1100a000 0 0x1000>; - interrupts = ; - clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, - <&topckgen CLK_TOP_SPI_SEL>, - <&pericfg CLK_PERI_SPI0>; - clock-names = "parent-clk", "sel-clk", "spi-clk"; - status = "disabled"; - }; - - thermal: thermal@1100b000 { - #thermal-sensor-cells = <0>; - compatible = "mediatek,mt8173-thermal"; - reg = <0 0x1100b000 0 0x1000>; - interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>; - clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>; - clock-names = "therm", "auxadc"; - resets = <&pericfg MT8173_PERI_THERM_SW_RST>; - mediatek,auxadc = <&auxadc>; - mediatek,apmixedsys = <&apmixedsys>; - nvmem-cells = <&thermal_calibration>; - nvmem-cell-names = "calibration-data"; - }; - - nor_flash: spi@1100d000 { - compatible = "mediatek,mt8173-nor"; - reg = <0 0x1100d000 0 0xe0>; - clocks = <&pericfg CLK_PERI_SPI>, - <&topckgen CLK_TOP_SPINFI_IFR_SEL>; - clock-names = "spi", "sf"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c3: i2c@11010000 { - compatible = "mediatek,mt8173-i2c"; - reg = <0 0x11010000 0 0x70>, - <0 0x11000280 0 0x80>; - interrupts = ; - clock-div = <16>; - clocks = <&pericfg CLK_PERI_I2C3>, - <&pericfg CLK_PERI_AP_DMA>; - clock-names = "main", "dma"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_pins_a>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c4: i2c@11011000 { - compatible = "mediatek,mt8173-i2c"; - reg = <0 0x11011000 0 0x70>, - <0 0x11000300 0 0x80>; - interrupts = ; - clock-div = <16>; - clocks = <&pericfg CLK_PERI_I2C4>, - <&pericfg CLK_PERI_AP_DMA>; - clock-names = "main", "dma"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_pins_a>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - hdmiddc0: i2c@11012000 { - compatible = "mediatek,mt8173-hdmi-ddc"; - interrupts = ; - reg = <0 0x11012000 0 0x1C>; - clocks = <&pericfg CLK_PERI_I2C5>; - clock-names = "ddc-i2c"; - }; - - i2c6: i2c@11013000 { - compatible = "mediatek,mt8173-i2c"; - reg = <0 0x11013000 0 0x70>, - <0 0x11000080 0 0x80>; - interrupts = ; - clock-div = <16>; - clocks = <&pericfg CLK_PERI_I2C6>, - <&pericfg CLK_PERI_AP_DMA>; - clock-names = "main", "dma"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c6_pins_a>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - afe: audio-controller@11220000 { - compatible = "mediatek,mt8173-afe-pcm"; - reg = <0 0x11220000 0 0x1000>; - interrupts = ; - power-domains = <&scpsys MT8173_POWER_DOMAIN_AUDIO>; - clocks = <&infracfg CLK_INFRA_AUDIO>, - <&topckgen CLK_TOP_AUDIO_SEL>, - <&topckgen CLK_TOP_AUD_INTBUS_SEL>, - <&topckgen CLK_TOP_APLL1_DIV0>, - <&topckgen CLK_TOP_APLL2_DIV0>, - <&topckgen CLK_TOP_I2S0_M_SEL>, - <&topckgen CLK_TOP_I2S1_M_SEL>, - <&topckgen CLK_TOP_I2S2_M_SEL>, - <&topckgen CLK_TOP_I2S3_M_SEL>, - <&topckgen CLK_TOP_I2S3_B_SEL>; - clock-names = "infra_sys_audio_clk", - "top_pdn_audio", - "top_pdn_aud_intbus", - "bck0", - "bck1", - "i2s0_m", - "i2s1_m", - "i2s2_m", - "i2s3_m", - "i2s3_b"; - assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>, - <&topckgen CLK_TOP_AUD_2_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_APLL1>, - <&topckgen CLK_TOP_APLL2>; - }; - - mmc0: mmc@11230000 { - compatible = "mediatek,mt8173-mmc"; - reg = <0 0x11230000 0 0x1000>; - interrupts = ; - clocks = <&pericfg CLK_PERI_MSDC30_0>, - <&topckgen CLK_TOP_MSDC50_0_H_SEL>; - clock-names = "source", "hclk"; - status = "disabled"; - }; - - mmc1: mmc@11240000 { - compatible = "mediatek,mt8173-mmc"; - reg = <0 0x11240000 0 0x1000>; - interrupts = ; - clocks = <&pericfg CLK_PERI_MSDC30_1>, - <&topckgen CLK_TOP_AXI_SEL>; - clock-names = "source", "hclk"; - status = "disabled"; - }; - - mmc2: mmc@11250000 { - compatible = "mediatek,mt8173-mmc"; - reg = <0 0x11250000 0 0x1000>; - interrupts = ; - clocks = <&pericfg CLK_PERI_MSDC30_2>, - <&topckgen CLK_TOP_AXI_SEL>; - clock-names = "source", "hclk"; - status = "disabled"; - }; - - mmc3: mmc@11260000 { - compatible = "mediatek,mt8173-mmc"; - reg = <0 0x11260000 0 0x1000>; - interrupts = ; - clocks = <&pericfg CLK_PERI_MSDC30_3>, - <&topckgen CLK_TOP_MSDC50_2_H_SEL>; - clock-names = "source", "hclk"; - status = "disabled"; - }; - - ssusb: usb@11271000 { - compatible = "mediatek,mt8173-mtu3"; - reg = <0 0x11271000 0 0x3000>, - <0 0x11280700 0 0x0100>; - reg-names = "mac", "ippc"; - interrupts = ; - phys = <&u2port0 PHY_TYPE_USB2>, - <&u3port0 PHY_TYPE_USB3>, - <&u2port1 PHY_TYPE_USB2>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>; - clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>; - clock-names = "sys_ck", "ref_ck"; - mediatek,syscon-wakeup = <&pericfg 0x400 1>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - status = "disabled"; - - usb_host: xhci@11270000 { - compatible = "mediatek,mt8173-xhci"; - reg = <0 0x11270000 0 0x1000>; - reg-names = "mac"; - interrupts = ; - power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>; - clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>; - clock-names = "sys_ck", "ref_ck"; - status = "disabled"; - }; - }; - - u3phy: usb-phy@11290000 { - compatible = "mediatek,mt8173-u3phy"; - reg = <0 0x11290000 0 0x800>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - status = "okay"; - - u2port0: usb-phy@11290800 { - reg = <0 0x11290800 0 0x100>; - clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>; - clock-names = "ref"; - #phy-cells = <1>; - status = "okay"; - }; - - u3port0: usb-phy@11290900 { - reg = <0 0x11290900 0 0x700>; - clocks = <&clk26m>; - clock-names = "ref"; - #phy-cells = <1>; - status = "okay"; - }; - - u2port1: usb-phy@11291000 { - reg = <0 0x11291000 0 0x100>; - clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>; - clock-names = "ref"; - #phy-cells = <1>; - status = "okay"; - }; - }; - - mmsys: clock-controller@14000000 { - compatible = "mediatek,mt8173-mmsys", "syscon"; - reg = <0 0x14000000 0 0x1000>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - assigned-clocks = <&topckgen CLK_TOP_MM_SEL>; - assigned-clock-rates = <400000000>; - #clock-cells = <1>; - }; - - mdp_rdma0: rdma@14001000 { - compatible = "mediatek,mt8173-mdp-rdma", - "mediatek,mt8173-mdp"; - reg = <0 0x14001000 0 0x1000>; - clocks = <&mmsys CLK_MM_MDP_RDMA0>, - <&mmsys CLK_MM_MUTEX_32K>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - iommus = <&iommu M4U_PORT_MDP_RDMA0>; - mediatek,larb = <&larb0>; - mediatek,vpu = <&vpu>; - }; - - mdp_rdma1: rdma@14002000 { - compatible = "mediatek,mt8173-mdp-rdma"; - reg = <0 0x14002000 0 0x1000>; - clocks = <&mmsys CLK_MM_MDP_RDMA1>, - <&mmsys CLK_MM_MUTEX_32K>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - iommus = <&iommu M4U_PORT_MDP_RDMA1>; - mediatek,larb = <&larb4>; - }; - - mdp_rsz0: rsz@14003000 { - compatible = "mediatek,mt8173-mdp-rsz"; - reg = <0 0x14003000 0 0x1000>; - clocks = <&mmsys CLK_MM_MDP_RSZ0>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - }; - - mdp_rsz1: rsz@14004000 { - compatible = "mediatek,mt8173-mdp-rsz"; - reg = <0 0x14004000 0 0x1000>; - clocks = <&mmsys CLK_MM_MDP_RSZ1>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - }; - - mdp_rsz2: rsz@14005000 { - compatible = "mediatek,mt8173-mdp-rsz"; - reg = <0 0x14005000 0 0x1000>; - clocks = <&mmsys CLK_MM_MDP_RSZ2>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - }; - - mdp_wdma0: wdma@14006000 { - compatible = "mediatek,mt8173-mdp-wdma"; - reg = <0 0x14006000 0 0x1000>; - clocks = <&mmsys CLK_MM_MDP_WDMA>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - iommus = <&iommu M4U_PORT_MDP_WDMA>; - mediatek,larb = <&larb0>; - }; - - mdp_wrot0: wrot@14007000 { - compatible = "mediatek,mt8173-mdp-wrot"; - reg = <0 0x14007000 0 0x1000>; - clocks = <&mmsys CLK_MM_MDP_WROT0>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - iommus = <&iommu M4U_PORT_MDP_WROT0>; - mediatek,larb = <&larb0>; - }; - - mdp_wrot1: wrot@14008000 { - compatible = "mediatek,mt8173-mdp-wrot"; - reg = <0 0x14008000 0 0x1000>; - clocks = <&mmsys CLK_MM_MDP_WROT1>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - iommus = <&iommu M4U_PORT_MDP_WROT1>; - mediatek,larb = <&larb4>; - }; - - ovl0: ovl@1400c000 { - compatible = "mediatek,mt8173-disp-ovl"; - reg = <0 0x1400c000 0 0x1000>; - interrupts = ; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - clocks = <&mmsys CLK_MM_DISP_OVL0>; - iommus = <&iommu M4U_PORT_DISP_OVL0>; - mediatek,larb = <&larb0>; - }; - - ovl1: ovl@1400d000 { - compatible = "mediatek,mt8173-disp-ovl"; - reg = <0 0x1400d000 0 0x1000>; - interrupts = ; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - clocks = <&mmsys CLK_MM_DISP_OVL1>; - iommus = <&iommu M4U_PORT_DISP_OVL1>; - mediatek,larb = <&larb4>; - }; - - rdma0: rdma@1400e000 { - compatible = "mediatek,mt8173-disp-rdma"; - reg = <0 0x1400e000 0 0x1000>; - interrupts = ; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - clocks = <&mmsys CLK_MM_DISP_RDMA0>; - iommus = <&iommu M4U_PORT_DISP_RDMA0>; - mediatek,larb = <&larb0>; - }; - - rdma1: rdma@1400f000 { - compatible = "mediatek,mt8173-disp-rdma"; - reg = <0 0x1400f000 0 0x1000>; - interrupts = ; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - clocks = <&mmsys CLK_MM_DISP_RDMA1>; - iommus = <&iommu M4U_PORT_DISP_RDMA1>; - mediatek,larb = <&larb4>; - }; - - rdma2: rdma@14010000 { - compatible = "mediatek,mt8173-disp-rdma"; - reg = <0 0x14010000 0 0x1000>; - interrupts = ; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - clocks = <&mmsys CLK_MM_DISP_RDMA2>; - iommus = <&iommu M4U_PORT_DISP_RDMA2>; - mediatek,larb = <&larb4>; - }; - - wdma0: wdma@14011000 { - compatible = "mediatek,mt8173-disp-wdma"; - reg = <0 0x14011000 0 0x1000>; - interrupts = ; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - clocks = <&mmsys CLK_MM_DISP_WDMA0>; - iommus = <&iommu M4U_PORT_DISP_WDMA0>; - mediatek,larb = <&larb0>; - }; - - wdma1: wdma@14012000 { - compatible = "mediatek,mt8173-disp-wdma"; - reg = <0 0x14012000 0 0x1000>; - interrupts = ; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - clocks = <&mmsys CLK_MM_DISP_WDMA1>; - iommus = <&iommu M4U_PORT_DISP_WDMA1>; - mediatek,larb = <&larb4>; - }; - - color0: color@14013000 { - compatible = "mediatek,mt8173-disp-color"; - reg = <0 0x14013000 0 0x1000>; - interrupts = ; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - clocks = <&mmsys CLK_MM_DISP_COLOR0>; - }; - - color1: color@14014000 { - compatible = "mediatek,mt8173-disp-color"; - reg = <0 0x14014000 0 0x1000>; - interrupts = ; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - clocks = <&mmsys CLK_MM_DISP_COLOR1>; - }; - - aal@14015000 { - compatible = "mediatek,mt8173-disp-aal"; - reg = <0 0x14015000 0 0x1000>; - interrupts = ; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - clocks = <&mmsys CLK_MM_DISP_AAL>; - }; - - gamma@14016000 { - compatible = "mediatek,mt8173-disp-gamma"; - reg = <0 0x14016000 0 0x1000>; - interrupts = ; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - clocks = <&mmsys CLK_MM_DISP_GAMMA>; - }; - - merge@14017000 { - compatible = "mediatek,mt8173-disp-merge"; - reg = <0 0x14017000 0 0x1000>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - clocks = <&mmsys CLK_MM_DISP_MERGE>; - }; - - split0: split@14018000 { - compatible = "mediatek,mt8173-disp-split"; - reg = <0 0x14018000 0 0x1000>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - clocks = <&mmsys CLK_MM_DISP_SPLIT0>; - }; - - split1: split@14019000 { - compatible = "mediatek,mt8173-disp-split"; - reg = <0 0x14019000 0 0x1000>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - clocks = <&mmsys CLK_MM_DISP_SPLIT1>; - }; - - ufoe@1401a000 { - compatible = "mediatek,mt8173-disp-ufoe"; - reg = <0 0x1401a000 0 0x1000>; - interrupts = ; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - clocks = <&mmsys CLK_MM_DISP_UFOE>; - }; - - dsi0: dsi@1401b000 { - compatible = "mediatek,mt8173-dsi"; - reg = <0 0x1401b000 0 0x1000>; - interrupts = ; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - clocks = <&mmsys CLK_MM_DSI0_ENGINE>, - <&mmsys CLK_MM_DSI0_DIGITAL>, - <&mipi_tx0>; - clock-names = "engine", "digital", "hs"; - phys = <&mipi_tx0>; - phy-names = "dphy"; - status = "disabled"; - }; - - dsi1: dsi@1401c000 { - compatible = "mediatek,mt8173-dsi"; - reg = <0 0x1401c000 0 0x1000>; - interrupts = ; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - clocks = <&mmsys CLK_MM_DSI1_ENGINE>, - <&mmsys CLK_MM_DSI1_DIGITAL>, - <&mipi_tx1>; - clock-names = "engine", "digital", "hs"; - phy = <&mipi_tx1>; - phy-names = "dphy"; - status = "disabled"; - }; - - dpi0: dpi@1401d000 { - compatible = "mediatek,mt8173-dpi"; - reg = <0 0x1401d000 0 0x1000>; - interrupts = ; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - clocks = <&mmsys CLK_MM_DPI_PIXEL>, - <&mmsys CLK_MM_DPI_ENGINE>, - <&apmixedsys CLK_APMIXED_TVDPLL>; - clock-names = "pixel", "engine", "pll"; - status = "disabled"; - - port { - dpi0_out: endpoint { - remote-endpoint = <&hdmi0_in>; - }; - }; - }; - - pwm0: pwm@1401e000 { - compatible = "mediatek,mt8173-disp-pwm", - "mediatek,mt6595-disp-pwm"; - reg = <0 0x1401e000 0 0x1000>; - #pwm-cells = <2>; - clocks = <&mmsys CLK_MM_DISP_PWM026M>, - <&mmsys CLK_MM_DISP_PWM0MM>; - clock-names = "main", "mm"; - status = "disabled"; - }; - - pwm1: pwm@1401f000 { - compatible = "mediatek,mt8173-disp-pwm", - "mediatek,mt6595-disp-pwm"; - reg = <0 0x1401f000 0 0x1000>; - #pwm-cells = <2>; - clocks = <&mmsys CLK_MM_DISP_PWM126M>, - <&mmsys CLK_MM_DISP_PWM1MM>; - clock-names = "main", "mm"; - status = "disabled"; - }; - - mutex: mutex@14020000 { - compatible = "mediatek,mt8173-disp-mutex"; - reg = <0 0x14020000 0 0x1000>; - interrupts = ; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - clocks = <&mmsys CLK_MM_MUTEX_32K>; - }; - - larb0: larb@14021000 { - compatible = "mediatek,mt8173-smi-larb"; - reg = <0 0x14021000 0 0x1000>; - mediatek,smi = <&smi_common>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - clocks = <&mmsys CLK_MM_SMI_LARB0>, - <&mmsys CLK_MM_SMI_LARB0>; - clock-names = "apb", "smi"; - }; - - smi_common: smi@14022000 { - compatible = "mediatek,mt8173-smi-common"; - reg = <0 0x14022000 0 0x1000>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - clocks = <&mmsys CLK_MM_SMI_COMMON>, - <&mmsys CLK_MM_SMI_COMMON>; - clock-names = "apb", "smi"; - }; - - od@14023000 { - compatible = "mediatek,mt8173-disp-od"; - reg = <0 0x14023000 0 0x1000>; - clocks = <&mmsys CLK_MM_DISP_OD>; - }; - - hdmi0: hdmi@14025000 { - compatible = "mediatek,mt8173-hdmi"; - reg = <0 0x14025000 0 0x400>; - interrupts = ; - clocks = <&mmsys CLK_MM_HDMI_PIXEL>, - <&mmsys CLK_MM_HDMI_PLLCK>, - <&mmsys CLK_MM_HDMI_AUDIO>, - <&mmsys CLK_MM_HDMI_SPDIF>; - clock-names = "pixel", "pll", "bclk", "spdif"; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_pin>; - phys = <&hdmi_phy>; - phy-names = "hdmi"; - mediatek,syscon-hdmi = <&mmsys 0x900>; - assigned-clocks = <&topckgen CLK_TOP_HDMI_SEL>; - assigned-clock-parents = <&hdmi_phy>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - hdmi0_in: endpoint { - remote-endpoint = <&dpi0_out>; - }; - }; - }; - }; - - larb4: larb@14027000 { - compatible = "mediatek,mt8173-smi-larb"; - reg = <0 0x14027000 0 0x1000>; - mediatek,smi = <&smi_common>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - clocks = <&mmsys CLK_MM_SMI_LARB4>, - <&mmsys CLK_MM_SMI_LARB4>; - clock-names = "apb", "smi"; - }; - - imgsys: clock-controller@15000000 { - compatible = "mediatek,mt8173-imgsys", "syscon"; - reg = <0 0x15000000 0 0x1000>; - #clock-cells = <1>; - }; - - larb2: larb@15001000 { - compatible = "mediatek,mt8173-smi-larb"; - reg = <0 0x15001000 0 0x1000>; - mediatek,smi = <&smi_common>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_ISP>; - clocks = <&imgsys CLK_IMG_LARB2_SMI>, - <&imgsys CLK_IMG_LARB2_SMI>; - clock-names = "apb", "smi"; - }; - - vdecsys: clock-controller@16000000 { - compatible = "mediatek,mt8173-vdecsys", "syscon"; - reg = <0 0x16000000 0 0x1000>; - #clock-cells = <1>; - }; - - vcodec_dec: vcodec@16000000 { - compatible = "mediatek,mt8173-vcodec-dec"; - reg = <0 0x16000000 0 0x100>, /* VDEC_SYS */ - <0 0x16020000 0 0x1000>, /* VDEC_MISC */ - <0 0x16021000 0 0x800>, /* VDEC_LD */ - <0 0x16021800 0 0x800>, /* VDEC_TOP */ - <0 0x16022000 0 0x1000>, /* VDEC_CM */ - <0 0x16023000 0 0x1000>, /* VDEC_AD */ - <0 0x16024000 0 0x1000>, /* VDEC_AV */ - <0 0x16025000 0 0x1000>, /* VDEC_PP */ - <0 0x16026800 0 0x800>, /* VDEC_HWD */ - <0 0x16027000 0 0x800>, /* VDEC_HWQ */ - <0 0x16027800 0 0x800>, /* VDEC_HWB */ - <0 0x16028400 0 0x400>; /* VDEC_HWG */ - interrupts = ; - mediatek,larb = <&larb1>; - iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>, - <&iommu M4U_PORT_HW_VDEC_PP_EXT>, - <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>, - <&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>, - <&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>, - <&iommu M4U_PORT_HW_VDEC_UFO_EXT>, - <&iommu M4U_PORT_HW_VDEC_VLD_EXT>, - <&iommu M4U_PORT_HW_VDEC_VLD2_EXT>; - mediatek,vpu = <&vpu>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>; - clocks = <&apmixedsys CLK_APMIXED_VCODECPLL>, - <&topckgen CLK_TOP_UNIVPLL_D2>, - <&topckgen CLK_TOP_CCI400_SEL>, - <&topckgen CLK_TOP_VDEC_SEL>, - <&topckgen CLK_TOP_VCODECPLL>, - <&apmixedsys CLK_APMIXED_VENCPLL>, - <&topckgen CLK_TOP_VENC_LT_SEL>, - <&topckgen CLK_TOP_VCODECPLL_370P5>; - clock-names = "vcodecpll", - "univpll_d2", - "clk_cci400_sel", - "vdec_sel", - "vdecpll", - "vencpll", - "venc_lt_sel", - "vdec_bus_clk_src"; - assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>, - <&topckgen CLK_TOP_CCI400_SEL>, - <&topckgen CLK_TOP_VDEC_SEL>, - <&apmixedsys CLK_APMIXED_VCODECPLL>, - <&apmixedsys CLK_APMIXED_VENCPLL>; - assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>, - <&topckgen CLK_TOP_UNIVPLL_D2>, - <&topckgen CLK_TOP_VCODECPLL>; - assigned-clock-rates = <0>, <0>, <0>, <1482000000>, <800000000>; - }; - - larb1: larb@16010000 { - compatible = "mediatek,mt8173-smi-larb"; - reg = <0 0x16010000 0 0x1000>; - mediatek,smi = <&smi_common>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>; - clocks = <&vdecsys CLK_VDEC_CKEN>, - <&vdecsys CLK_VDEC_LARB_CKEN>; - clock-names = "apb", "smi"; - }; - - vencsys: clock-controller@18000000 { - compatible = "mediatek,mt8173-vencsys", "syscon"; - reg = <0 0x18000000 0 0x1000>; - #clock-cells = <1>; - }; - - larb3: larb@18001000 { - compatible = "mediatek,mt8173-smi-larb"; - reg = <0 0x18001000 0 0x1000>; - mediatek,smi = <&smi_common>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC>; - clocks = <&vencsys CLK_VENC_CKE1>, - <&vencsys CLK_VENC_CKE0>; - clock-names = "apb", "smi"; - }; - - vcodec_enc: vcodec@18002000 { - compatible = "mediatek,mt8173-vcodec-enc"; - reg = <0 0x18002000 0 0x1000>, /* VENC_SYS */ - <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */ - interrupts = , - ; - mediatek,larb = <&larb3>, - <&larb5>; - iommus = <&iommu M4U_PORT_VENC_RCPU>, - <&iommu M4U_PORT_VENC_REC>, - <&iommu M4U_PORT_VENC_BSDMA>, - <&iommu M4U_PORT_VENC_SV_COMV>, - <&iommu M4U_PORT_VENC_RD_COMV>, - <&iommu M4U_PORT_VENC_CUR_LUMA>, - <&iommu M4U_PORT_VENC_CUR_CHROMA>, - <&iommu M4U_PORT_VENC_REF_LUMA>, - <&iommu M4U_PORT_VENC_REF_CHROMA>, - <&iommu M4U_PORT_VENC_NBM_RDMA>, - <&iommu M4U_PORT_VENC_NBM_WDMA>, - <&iommu M4U_PORT_VENC_RCPU_SET2>, - <&iommu M4U_PORT_VENC_REC_FRM_SET2>, - <&iommu M4U_PORT_VENC_BSDMA_SET2>, - <&iommu M4U_PORT_VENC_SV_COMA_SET2>, - <&iommu M4U_PORT_VENC_RD_COMA_SET2>, - <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>, - <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>, - <&iommu M4U_PORT_VENC_REF_LUMA_SET2>, - <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>; - mediatek,vpu = <&vpu>; - clocks = <&topckgen CLK_TOP_VENCPLL_D2>, - <&topckgen CLK_TOP_VENC_SEL>, - <&topckgen CLK_TOP_UNIVPLL1_D2>, - <&topckgen CLK_TOP_VENC_LT_SEL>; - clock-names = "venc_sel_src", - "venc_sel", - "venc_lt_sel_src", - "venc_lt_sel"; - assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>, - <&topckgen CLK_TOP_VENC_LT_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_VENCPLL_D2>, - <&topckgen CLK_TOP_UNIVPLL1_D2>; - }; - - jpegdec: jpegdec@18004000 { - compatible = "mediatek,mt8173-jpgdec"; - reg = <0 0x18004000 0 0x1000>; - interrupts = ; - clocks = <&vencsys CLK_VENC_CKE0>, - <&vencsys CLK_VENC_CKE3>; - clock-names = "jpgdec-smi", - "jpgdec"; - power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC>; - mediatek,larb = <&larb3>; - iommus = <&iommu M4U_PORT_JPGDEC_WDMA>, - <&iommu M4U_PORT_JPGDEC_BSDMA>; - }; - - vencltsys: clock-controller@19000000 { - compatible = "mediatek,mt8173-vencltsys", "syscon"; - reg = <0 0x19000000 0 0x1000>; - #clock-cells = <1>; - }; - - larb5: larb@19001000 { - compatible = "mediatek,mt8173-smi-larb"; - reg = <0 0x19001000 0 0x1000>; - mediatek,smi = <&smi_common>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC_LT>; - clocks = <&vencltsys CLK_VENCLT_CKE1>, - <&vencltsys CLK_VENCLT_CKE0>; - clock-names = "apb", "smi"; - }; - }; -}; - diff --git a/sys/gnu/dts/arm64/mediatek/mt8183-evb.dts b/sys/gnu/dts/arm64/mediatek/mt8183-evb.dts deleted file mode 100644 index 1fb195c683c..00000000000 --- a/sys/gnu/dts/arm64/mediatek/mt8183-evb.dts +++ /dev/null @@ -1,236 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (c) 2018 MediaTek Inc. - * Author: Ben Ho - * Erin Lo - */ - -/dts-v1/; -#include "mt8183.dtsi" - -/ { - model = "MediaTek MT8183 evaluation board"; - compatible = "mediatek,mt8183-evb", "mediatek,mt8183"; - - aliases { - serial0 = &uart0; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0 0x40000000 0 0x80000000>; - }; - - chosen { - stdout-path = "serial0:921600n8"; - }; -}; - -&auxadc { - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c_pins_0>; - status = "okay"; - clock-frequency = <100000>; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c_pins_1>; - status = "okay"; - clock-frequency = <100000>; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c_pins_2>; - status = "okay"; - clock-frequency = <100000>; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c_pins_3>; - status = "okay"; - clock-frequency = <100000>; -}; - -&i2c4 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c_pins_4>; - status = "okay"; - clock-frequency = <1000000>; -}; - -&i2c5 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c_pins_5>; - status = "okay"; - clock-frequency = <1000000>; -}; - -&pio { - i2c_pins_0: i2c0{ - pins_i2c{ - pinmux = , - ; - mediatek,pull-up-adv = <3>; - mediatek,drive-strength-adv = <00>; - }; - }; - - i2c_pins_1: i2c1{ - pins_i2c{ - pinmux = , - ; - mediatek,pull-up-adv = <3>; - mediatek,drive-strength-adv = <00>; - }; - }; - - i2c_pins_2: i2c2{ - pins_i2c{ - pinmux = , - ; - mediatek,pull-up-adv = <3>; - mediatek,drive-strength-adv = <00>; - }; - }; - - i2c_pins_3: i2c3{ - pins_i2c{ - pinmux = , - ; - mediatek,pull-up-adv = <3>; - mediatek,drive-strength-adv = <00>; - }; - }; - - i2c_pins_4: i2c4{ - pins_i2c{ - pinmux = , - ; - mediatek,pull-up-adv = <3>; - mediatek,drive-strength-adv = <00>; - }; - }; - - i2c_pins_5: i2c5{ - pins_i2c{ - pinmux = , - ; - mediatek,pull-up-adv = <3>; - mediatek,drive-strength-adv = <00>; - }; - }; - - spi_pins_0: spi0{ - pins_spi{ - pinmux = , - , - , - ; - bias-disable; - }; - }; - - spi_pins_1: spi1{ - pins_spi{ - pinmux = , - , - , - ; - bias-disable; - }; - }; - - spi_pins_2: spi2{ - pins_spi{ - pinmux = , - , - , - ; - bias-disable; - }; - }; - - spi_pins_3: spi3{ - pins_spi{ - pinmux = , - , - , - ; - bias-disable; - }; - }; - - spi_pins_4: spi4{ - pins_spi{ - pinmux = , - , - , - ; - bias-disable; - }; - }; - - spi_pins_5: spi5{ - pins_spi{ - pinmux = , - , - , - ; - bias-disable; - }; - }; -}; - -&spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi_pins_0>; - mediatek,pad-select = <0>; - status = "okay"; -}; - -&spi1 { - pinctrl-names = "default"; - pinctrl-0 = <&spi_pins_1>; - mediatek,pad-select = <0>; - status = "okay"; -}; - -&spi2 { - pinctrl-names = "default"; - pinctrl-0 = <&spi_pins_2>; - mediatek,pad-select = <0>; - status = "okay"; -}; - -&spi3 { - pinctrl-names = "default"; - pinctrl-0 = <&spi_pins_3>; - mediatek,pad-select = <0>; - status = "okay"; -}; - -&spi4 { - pinctrl-names = "default"; - pinctrl-0 = <&spi_pins_4>; - mediatek,pad-select = <0>; - status = "okay"; -}; - -&spi5 { - pinctrl-names = "default"; - pinctrl-0 = <&spi_pins_5>; - mediatek,pad-select = <0>; - status = "okay"; - -}; - -&uart0 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/mediatek/mt8183-pinfunc.h b/sys/gnu/dts/arm64/mediatek/mt8183-pinfunc.h deleted file mode 100644 index 6221cd71271..00000000000 --- a/sys/gnu/dts/arm64/mediatek/mt8183-pinfunc.h +++ /dev/null @@ -1,1120 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2018 MediaTek Inc. - * Author: Zhiyong Tao - * - */ - -#ifndef __MT8183_PINFUNC_H -#define __MT8183_PINFUNC_H - -#include - -#define PINMUX_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) -#define PINMUX_GPIO0__FUNC_MRG_SYNC (MTK_PIN_NO(0) | 1) -#define PINMUX_GPIO0__FUNC_PCM0_SYNC (MTK_PIN_NO(0) | 2) -#define PINMUX_GPIO0__FUNC_TP_GPIO0_AO (MTK_PIN_NO(0) | 3) -#define PINMUX_GPIO0__FUNC_SRCLKENAI0 (MTK_PIN_NO(0) | 4) -#define PINMUX_GPIO0__FUNC_SCP_SPI2_CS (MTK_PIN_NO(0) | 5) -#define PINMUX_GPIO0__FUNC_I2S3_MCK (MTK_PIN_NO(0) | 6) -#define PINMUX_GPIO0__FUNC_SPI2_CSB (MTK_PIN_NO(0) | 7) - -#define PINMUX_GPIO1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) -#define PINMUX_GPIO1__FUNC_MRG_CLK (MTK_PIN_NO(1) | 1) -#define PINMUX_GPIO1__FUNC_PCM0_CLK (MTK_PIN_NO(1) | 2) -#define PINMUX_GPIO1__FUNC_TP_GPIO1_AO (MTK_PIN_NO(1) | 3) -#define PINMUX_GPIO1__FUNC_CLKM3 (MTK_PIN_NO(1) | 4) -#define PINMUX_GPIO1__FUNC_SCP_SPI2_MO (MTK_PIN_NO(1) | 5) -#define PINMUX_GPIO1__FUNC_I2S3_BCK (MTK_PIN_NO(1) | 6) -#define PINMUX_GPIO1__FUNC_SPI2_MO (MTK_PIN_NO(1) | 7) - -#define PINMUX_GPIO2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) -#define PINMUX_GPIO2__FUNC_MRG_DO (MTK_PIN_NO(2) | 1) -#define PINMUX_GPIO2__FUNC_PCM0_DO (MTK_PIN_NO(2) | 2) -#define PINMUX_GPIO2__FUNC_TP_GPIO2_AO (MTK_PIN_NO(2) | 3) -#define PINMUX_GPIO2__FUNC_SCL6 (MTK_PIN_NO(2) | 4) -#define PINMUX_GPIO2__FUNC_SCP_SPI2_CK (MTK_PIN_NO(2) | 5) -#define PINMUX_GPIO2__FUNC_I2S3_LRCK (MTK_PIN_NO(2) | 6) -#define PINMUX_GPIO2__FUNC_SPI2_CLK (MTK_PIN_NO(2) | 7) - -#define PINMUX_GPIO3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) -#define PINMUX_GPIO3__FUNC_MRG_DI (MTK_PIN_NO(3) | 1) -#define PINMUX_GPIO3__FUNC_PCM0_DI (MTK_PIN_NO(3) | 2) -#define PINMUX_GPIO3__FUNC_TP_GPIO3_AO (MTK_PIN_NO(3) | 3) -#define PINMUX_GPIO3__FUNC_SDA6 (MTK_PIN_NO(3) | 4) -#define PINMUX_GPIO3__FUNC_TDM_MCK (MTK_PIN_NO(3) | 5) -#define PINMUX_GPIO3__FUNC_I2S3_DO (MTK_PIN_NO(3) | 6) -#define PINMUX_GPIO3__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(3) | 7) - -#define PINMUX_GPIO4__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) -#define PINMUX_GPIO4__FUNC_PWM_B (MTK_PIN_NO(4) | 1) -#define PINMUX_GPIO4__FUNC_I2S0_MCK (MTK_PIN_NO(4) | 2) -#define PINMUX_GPIO4__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(4) | 3) -#define PINMUX_GPIO4__FUNC_MD_URXD1 (MTK_PIN_NO(4) | 4) -#define PINMUX_GPIO4__FUNC_TDM_BCK (MTK_PIN_NO(4) | 5) -#define PINMUX_GPIO4__FUNC_TP_GPIO4_AO (MTK_PIN_NO(4) | 6) -#define PINMUX_GPIO4__FUNC_DAP_MD32_SWD (MTK_PIN_NO(4) | 7) - -#define PINMUX_GPIO5__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) -#define PINMUX_GPIO5__FUNC_PWM_C (MTK_PIN_NO(5) | 1) -#define PINMUX_GPIO5__FUNC_I2S0_BCK (MTK_PIN_NO(5) | 2) -#define PINMUX_GPIO5__FUNC_SSPM_URXD_AO (MTK_PIN_NO(5) | 3) -#define PINMUX_GPIO5__FUNC_MD_UTXD1 (MTK_PIN_NO(5) | 4) -#define PINMUX_GPIO5__FUNC_TDM_LRCK (MTK_PIN_NO(5) | 5) -#define PINMUX_GPIO5__FUNC_TP_GPIO5_AO (MTK_PIN_NO(5) | 6) -#define PINMUX_GPIO5__FUNC_DAP_MD32_SWCK (MTK_PIN_NO(5) | 7) - -#define PINMUX_GPIO6__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) -#define PINMUX_GPIO6__FUNC_PWM_A (MTK_PIN_NO(6) | 1) -#define PINMUX_GPIO6__FUNC_I2S0_LRCK (MTK_PIN_NO(6) | 2) -#define PINMUX_GPIO6__FUNC_IDDIG (MTK_PIN_NO(6) | 3) -#define PINMUX_GPIO6__FUNC_MD_URXD0 (MTK_PIN_NO(6) | 4) -#define PINMUX_GPIO6__FUNC_TDM_DATA0 (MTK_PIN_NO(6) | 5) -#define PINMUX_GPIO6__FUNC_TP_GPIO6_AO (MTK_PIN_NO(6) | 6) -#define PINMUX_GPIO6__FUNC_CMFLASH (MTK_PIN_NO(6) | 7) - -#define PINMUX_GPIO7__FUNC_GPIO7 (MTK_PIN_NO(7) | 0) -#define PINMUX_GPIO7__FUNC_SPI1_B_MI (MTK_PIN_NO(7) | 1) -#define PINMUX_GPIO7__FUNC_I2S0_DI (MTK_PIN_NO(7) | 2) -#define PINMUX_GPIO7__FUNC_USB_DRVVBUS (MTK_PIN_NO(7) | 3) -#define PINMUX_GPIO7__FUNC_MD_UTXD0 (MTK_PIN_NO(7) | 4) -#define PINMUX_GPIO7__FUNC_TDM_DATA1 (MTK_PIN_NO(7) | 5) -#define PINMUX_GPIO7__FUNC_TP_GPIO7_AO (MTK_PIN_NO(7) | 6) -#define PINMUX_GPIO7__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(7) | 7) - -#define PINMUX_GPIO8__FUNC_GPIO8 (MTK_PIN_NO(8) | 0) -#define PINMUX_GPIO8__FUNC_SPI1_B_CSB (MTK_PIN_NO(8) | 1) -#define PINMUX_GPIO8__FUNC_ANT_SEL3 (MTK_PIN_NO(8) | 2) -#define PINMUX_GPIO8__FUNC_SCL7 (MTK_PIN_NO(8) | 3) -#define PINMUX_GPIO8__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(8) | 4) -#define PINMUX_GPIO8__FUNC_TDM_DATA2 (MTK_PIN_NO(8) | 5) -#define PINMUX_GPIO8__FUNC_MD_INT0 (MTK_PIN_NO(8) | 6) -#define PINMUX_GPIO8__FUNC_JTRSTN_SEL1 (MTK_PIN_NO(8) | 7) - -#define PINMUX_GPIO9__FUNC_GPIO9 (MTK_PIN_NO(9) | 0) -#define PINMUX_GPIO9__FUNC_SPI1_B_MO (MTK_PIN_NO(9) | 1) -#define PINMUX_GPIO9__FUNC_ANT_SEL4 (MTK_PIN_NO(9) | 2) -#define PINMUX_GPIO9__FUNC_CMMCLK2 (MTK_PIN_NO(9) | 3) -#define PINMUX_GPIO9__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(9) | 4) -#define PINMUX_GPIO9__FUNC_SSPM_JTAG_TRSTN (MTK_PIN_NO(9) | 5) -#define PINMUX_GPIO9__FUNC_IO_JTAG_TRSTN (MTK_PIN_NO(9) | 6) -#define PINMUX_GPIO9__FUNC_DBG_MON_B10 (MTK_PIN_NO(9) | 7) - -#define PINMUX_GPIO10__FUNC_GPIO10 (MTK_PIN_NO(10) | 0) -#define PINMUX_GPIO10__FUNC_SPI1_B_CLK (MTK_PIN_NO(10) | 1) -#define PINMUX_GPIO10__FUNC_ANT_SEL5 (MTK_PIN_NO(10) | 2) -#define PINMUX_GPIO10__FUNC_CMMCLK3 (MTK_PIN_NO(10) | 3) -#define PINMUX_GPIO10__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(10) | 4) -#define PINMUX_GPIO10__FUNC_TDM_DATA3 (MTK_PIN_NO(10) | 5) -#define PINMUX_GPIO10__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(10) | 6) -#define PINMUX_GPIO10__FUNC_DBG_MON_B11 (MTK_PIN_NO(10) | 7) - -#define PINMUX_GPIO11__FUNC_GPIO11 (MTK_PIN_NO(11) | 0) -#define PINMUX_GPIO11__FUNC_TP_URXD1_AO (MTK_PIN_NO(11) | 1) -#define PINMUX_GPIO11__FUNC_IDDIG (MTK_PIN_NO(11) | 2) -#define PINMUX_GPIO11__FUNC_SCL6 (MTK_PIN_NO(11) | 3) -#define PINMUX_GPIO11__FUNC_UCTS1 (MTK_PIN_NO(11) | 4) -#define PINMUX_GPIO11__FUNC_UCTS0 (MTK_PIN_NO(11) | 5) -#define PINMUX_GPIO11__FUNC_SRCLKENAI1 (MTK_PIN_NO(11) | 6) -#define PINMUX_GPIO11__FUNC_I2S5_MCK (MTK_PIN_NO(11) | 7) - -#define PINMUX_GPIO12__FUNC_GPIO12 (MTK_PIN_NO(12) | 0) -#define PINMUX_GPIO12__FUNC_TP_UTXD1_AO (MTK_PIN_NO(12) | 1) -#define PINMUX_GPIO12__FUNC_USB_DRVVBUS (MTK_PIN_NO(12) | 2) -#define PINMUX_GPIO12__FUNC_SDA6 (MTK_PIN_NO(12) | 3) -#define PINMUX_GPIO12__FUNC_URTS1 (MTK_PIN_NO(12) | 4) -#define PINMUX_GPIO12__FUNC_URTS0 (MTK_PIN_NO(12) | 5) -#define PINMUX_GPIO12__FUNC_I2S2_DI2 (MTK_PIN_NO(12) | 6) -#define PINMUX_GPIO12__FUNC_I2S5_BCK (MTK_PIN_NO(12) | 7) - -#define PINMUX_GPIO13__FUNC_GPIO13 (MTK_PIN_NO(13) | 0) -#define PINMUX_GPIO13__FUNC_DBPI_D0 (MTK_PIN_NO(13) | 1) -#define PINMUX_GPIO13__FUNC_SPI5_MI (MTK_PIN_NO(13) | 2) -#define PINMUX_GPIO13__FUNC_PCM0_SYNC (MTK_PIN_NO(13) | 3) -#define PINMUX_GPIO13__FUNC_MD_URXD0 (MTK_PIN_NO(13) | 4) -#define PINMUX_GPIO13__FUNC_ANT_SEL3 (MTK_PIN_NO(13) | 5) -#define PINMUX_GPIO13__FUNC_I2S0_MCK (MTK_PIN_NO(13) | 6) -#define PINMUX_GPIO13__FUNC_DBG_MON_B15 (MTK_PIN_NO(13) | 7) - -#define PINMUX_GPIO14__FUNC_GPIO14 (MTK_PIN_NO(14) | 0) -#define PINMUX_GPIO14__FUNC_DBPI_D1 (MTK_PIN_NO(14) | 1) -#define PINMUX_GPIO14__FUNC_SPI5_CSB (MTK_PIN_NO(14) | 2) -#define PINMUX_GPIO14__FUNC_PCM0_CLK (MTK_PIN_NO(14) | 3) -#define PINMUX_GPIO14__FUNC_MD_UTXD0 (MTK_PIN_NO(14) | 4) -#define PINMUX_GPIO14__FUNC_ANT_SEL4 (MTK_PIN_NO(14) | 5) -#define PINMUX_GPIO14__FUNC_I2S0_BCK (MTK_PIN_NO(14) | 6) -#define PINMUX_GPIO14__FUNC_DBG_MON_B16 (MTK_PIN_NO(14) | 7) - -#define PINMUX_GPIO15__FUNC_GPIO15 (MTK_PIN_NO(15) | 0) -#define PINMUX_GPIO15__FUNC_DBPI_D2 (MTK_PIN_NO(15) | 1) -#define PINMUX_GPIO15__FUNC_SPI5_MO (MTK_PIN_NO(15) | 2) -#define PINMUX_GPIO15__FUNC_PCM0_DO (MTK_PIN_NO(15) | 3) -#define PINMUX_GPIO15__FUNC_MD_URXD1 (MTK_PIN_NO(15) | 4) -#define PINMUX_GPIO15__FUNC_ANT_SEL5 (MTK_PIN_NO(15) | 5) -#define PINMUX_GPIO15__FUNC_I2S0_LRCK (MTK_PIN_NO(15) | 6) -#define PINMUX_GPIO15__FUNC_DBG_MON_B17 (MTK_PIN_NO(15) | 7) - -#define PINMUX_GPIO16__FUNC_GPIO16 (MTK_PIN_NO(16) | 0) -#define PINMUX_GPIO16__FUNC_DBPI_D3 (MTK_PIN_NO(16) | 1) -#define PINMUX_GPIO16__FUNC_SPI5_CLK (MTK_PIN_NO(16) | 2) -#define PINMUX_GPIO16__FUNC_PCM0_DI (MTK_PIN_NO(16) | 3) -#define PINMUX_GPIO16__FUNC_MD_UTXD1 (MTK_PIN_NO(16) | 4) -#define PINMUX_GPIO16__FUNC_ANT_SEL6 (MTK_PIN_NO(16) | 5) -#define PINMUX_GPIO16__FUNC_I2S0_DI (MTK_PIN_NO(16) | 6) -#define PINMUX_GPIO16__FUNC_DBG_MON_B23 (MTK_PIN_NO(16) | 7) - -#define PINMUX_GPIO17__FUNC_GPIO17 (MTK_PIN_NO(17) | 0) -#define PINMUX_GPIO17__FUNC_DBPI_D4 (MTK_PIN_NO(17) | 1) -#define PINMUX_GPIO17__FUNC_SPI4_MI (MTK_PIN_NO(17) | 2) -#define PINMUX_GPIO17__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(17) | 3) -#define PINMUX_GPIO17__FUNC_MD_INT0 (MTK_PIN_NO(17) | 4) -#define PINMUX_GPIO17__FUNC_ANT_SEL7 (MTK_PIN_NO(17) | 5) -#define PINMUX_GPIO17__FUNC_I2S3_MCK (MTK_PIN_NO(17) | 6) -#define PINMUX_GPIO17__FUNC_DBG_MON_A1 (MTK_PIN_NO(17) | 7) - -#define PINMUX_GPIO18__FUNC_GPIO18 (MTK_PIN_NO(18) | 0) -#define PINMUX_GPIO18__FUNC_DBPI_D5 (MTK_PIN_NO(18) | 1) -#define PINMUX_GPIO18__FUNC_SPI4_CSB (MTK_PIN_NO(18) | 2) -#define PINMUX_GPIO18__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(18) | 3) -#define PINMUX_GPIO18__FUNC_MD_INT0 (MTK_PIN_NO(18) | 4) -#define PINMUX_GPIO18__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(18) | 5) -#define PINMUX_GPIO18__FUNC_I2S3_BCK (MTK_PIN_NO(18) | 6) -#define PINMUX_GPIO18__FUNC_DBG_MON_A2 (MTK_PIN_NO(18) | 7) - -#define PINMUX_GPIO19__FUNC_GPIO19 (MTK_PIN_NO(19) | 0) -#define PINMUX_GPIO19__FUNC_DBPI_D6 (MTK_PIN_NO(19) | 1) -#define PINMUX_GPIO19__FUNC_SPI4_MO (MTK_PIN_NO(19) | 2) -#define PINMUX_GPIO19__FUNC_CONN_MCU_TDO (MTK_PIN_NO(19) | 3) -#define PINMUX_GPIO19__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(19) | 4) -#define PINMUX_GPIO19__FUNC_URXD1 (MTK_PIN_NO(19) | 5) -#define PINMUX_GPIO19__FUNC_I2S3_LRCK (MTK_PIN_NO(19) | 6) -#define PINMUX_GPIO19__FUNC_DBG_MON_A3 (MTK_PIN_NO(19) | 7) - -#define PINMUX_GPIO20__FUNC_GPIO20 (MTK_PIN_NO(20) | 0) -#define PINMUX_GPIO20__FUNC_DBPI_D7 (MTK_PIN_NO(20) | 1) -#define PINMUX_GPIO20__FUNC_SPI4_CLK (MTK_PIN_NO(20) | 2) -#define PINMUX_GPIO20__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(20) | 3) -#define PINMUX_GPIO20__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(20) | 4) -#define PINMUX_GPIO20__FUNC_UTXD1 (MTK_PIN_NO(20) | 5) -#define PINMUX_GPIO20__FUNC_I2S3_DO (MTK_PIN_NO(20) | 6) -#define PINMUX_GPIO20__FUNC_DBG_MON_A19 (MTK_PIN_NO(20) | 7) - -#define PINMUX_GPIO21__FUNC_GPIO21 (MTK_PIN_NO(21) | 0) -#define PINMUX_GPIO21__FUNC_DBPI_D8 (MTK_PIN_NO(21) | 1) -#define PINMUX_GPIO21__FUNC_SPI3_MI (MTK_PIN_NO(21) | 2) -#define PINMUX_GPIO21__FUNC_CONN_MCU_TMS (MTK_PIN_NO(21) | 3) -#define PINMUX_GPIO21__FUNC_DAP_MD32_SWD (MTK_PIN_NO(21) | 4) -#define PINMUX_GPIO21__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(21) | 5) -#define PINMUX_GPIO21__FUNC_I2S2_MCK (MTK_PIN_NO(21) | 6) -#define PINMUX_GPIO21__FUNC_DBG_MON_B5 (MTK_PIN_NO(21) | 7) - -#define PINMUX_GPIO22__FUNC_GPIO22 (MTK_PIN_NO(22) | 0) -#define PINMUX_GPIO22__FUNC_DBPI_D9 (MTK_PIN_NO(22) | 1) -#define PINMUX_GPIO22__FUNC_SPI3_CSB (MTK_PIN_NO(22) | 2) -#define PINMUX_GPIO22__FUNC_CONN_MCU_TCK (MTK_PIN_NO(22) | 3) -#define PINMUX_GPIO22__FUNC_DAP_MD32_SWCK (MTK_PIN_NO(22) | 4) -#define PINMUX_GPIO22__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(22) | 5) -#define PINMUX_GPIO22__FUNC_I2S2_BCK (MTK_PIN_NO(22) | 6) -#define PINMUX_GPIO22__FUNC_DBG_MON_B6 (MTK_PIN_NO(22) | 7) - -#define PINMUX_GPIO23__FUNC_GPIO23 (MTK_PIN_NO(23) | 0) -#define PINMUX_GPIO23__FUNC_DBPI_D10 (MTK_PIN_NO(23) | 1) -#define PINMUX_GPIO23__FUNC_SPI3_MO (MTK_PIN_NO(23) | 2) -#define PINMUX_GPIO23__FUNC_CONN_MCU_TDI (MTK_PIN_NO(23) | 3) -#define PINMUX_GPIO23__FUNC_UCTS1 (MTK_PIN_NO(23) | 4) -#define PINMUX_GPIO23__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(23) | 5) -#define PINMUX_GPIO23__FUNC_I2S2_LRCK (MTK_PIN_NO(23) | 6) -#define PINMUX_GPIO23__FUNC_DBG_MON_B7 (MTK_PIN_NO(23) | 7) - -#define PINMUX_GPIO24__FUNC_GPIO24 (MTK_PIN_NO(24) | 0) -#define PINMUX_GPIO24__FUNC_DBPI_D11 (MTK_PIN_NO(24) | 1) -#define PINMUX_GPIO24__FUNC_SPI3_CLK (MTK_PIN_NO(24) | 2) -#define PINMUX_GPIO24__FUNC_SRCLKENAI0 (MTK_PIN_NO(24) | 3) -#define PINMUX_GPIO24__FUNC_URTS1 (MTK_PIN_NO(24) | 4) -#define PINMUX_GPIO24__FUNC_IO_JTAG_TCK (MTK_PIN_NO(24) | 5) -#define PINMUX_GPIO24__FUNC_I2S2_DI (MTK_PIN_NO(24) | 6) -#define PINMUX_GPIO24__FUNC_DBG_MON_B31 (MTK_PIN_NO(24) | 7) - -#define PINMUX_GPIO25__FUNC_GPIO25 (MTK_PIN_NO(25) | 0) -#define PINMUX_GPIO25__FUNC_DBPI_HSYNC (MTK_PIN_NO(25) | 1) -#define PINMUX_GPIO25__FUNC_ANT_SEL0 (MTK_PIN_NO(25) | 2) -#define PINMUX_GPIO25__FUNC_SCL6 (MTK_PIN_NO(25) | 3) -#define PINMUX_GPIO25__FUNC_KPCOL2 (MTK_PIN_NO(25) | 4) -#define PINMUX_GPIO25__FUNC_IO_JTAG_TMS (MTK_PIN_NO(25) | 5) -#define PINMUX_GPIO25__FUNC_I2S1_MCK (MTK_PIN_NO(25) | 6) -#define PINMUX_GPIO25__FUNC_DBG_MON_B0 (MTK_PIN_NO(25) | 7) - -#define PINMUX_GPIO26__FUNC_GPIO26 (MTK_PIN_NO(26) | 0) -#define PINMUX_GPIO26__FUNC_DBPI_VSYNC (MTK_PIN_NO(26) | 1) -#define PINMUX_GPIO26__FUNC_ANT_SEL1 (MTK_PIN_NO(26) | 2) -#define PINMUX_GPIO26__FUNC_SDA6 (MTK_PIN_NO(26) | 3) -#define PINMUX_GPIO26__FUNC_KPROW2 (MTK_PIN_NO(26) | 4) -#define PINMUX_GPIO26__FUNC_IO_JTAG_TDI (MTK_PIN_NO(26) | 5) -#define PINMUX_GPIO26__FUNC_I2S1_BCK (MTK_PIN_NO(26) | 6) -#define PINMUX_GPIO26__FUNC_DBG_MON_B1 (MTK_PIN_NO(26) | 7) - -#define PINMUX_GPIO27__FUNC_GPIO27 (MTK_PIN_NO(27) | 0) -#define PINMUX_GPIO27__FUNC_DBPI_DE (MTK_PIN_NO(27) | 1) -#define PINMUX_GPIO27__FUNC_ANT_SEL2 (MTK_PIN_NO(27) | 2) -#define PINMUX_GPIO27__FUNC_SCL7 (MTK_PIN_NO(27) | 3) -#define PINMUX_GPIO27__FUNC_DMIC_CLK (MTK_PIN_NO(27) | 4) -#define PINMUX_GPIO27__FUNC_IO_JTAG_TDO (MTK_PIN_NO(27) | 5) -#define PINMUX_GPIO27__FUNC_I2S1_LRCK (MTK_PIN_NO(27) | 6) -#define PINMUX_GPIO27__FUNC_DBG_MON_B9 (MTK_PIN_NO(27) | 7) - -#define PINMUX_GPIO28__FUNC_GPIO28 (MTK_PIN_NO(28) | 0) -#define PINMUX_GPIO28__FUNC_DBPI_CK (MTK_PIN_NO(28) | 1) -#define PINMUX_GPIO28__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(28) | 2) -#define PINMUX_GPIO28__FUNC_SDA7 (MTK_PIN_NO(28) | 3) -#define PINMUX_GPIO28__FUNC_DMIC_DAT (MTK_PIN_NO(28) | 4) -#define PINMUX_GPIO28__FUNC_IO_JTAG_TRSTN (MTK_PIN_NO(28) | 5) -#define PINMUX_GPIO28__FUNC_I2S1_DO (MTK_PIN_NO(28) | 6) -#define PINMUX_GPIO28__FUNC_DBG_MON_B32 (MTK_PIN_NO(28) | 7) - -#define PINMUX_GPIO29__FUNC_GPIO29 (MTK_PIN_NO(29) | 0) -#define PINMUX_GPIO29__FUNC_MSDC1_CLK (MTK_PIN_NO(29) | 1) -#define PINMUX_GPIO29__FUNC_IO_JTAG_TCK (MTK_PIN_NO(29) | 2) -#define PINMUX_GPIO29__FUNC_UDI_TCK (MTK_PIN_NO(29) | 3) -#define PINMUX_GPIO29__FUNC_CONN_DSP_JCK (MTK_PIN_NO(29) | 4) -#define PINMUX_GPIO29__FUNC_SSPM_JTAG_TCK (MTK_PIN_NO(29) | 5) -#define PINMUX_GPIO29__FUNC_PCM1_CLK (MTK_PIN_NO(29) | 6) -#define PINMUX_GPIO29__FUNC_DBG_MON_A6 (MTK_PIN_NO(29) | 7) - -#define PINMUX_GPIO30__FUNC_GPIO30 (MTK_PIN_NO(30) | 0) -#define PINMUX_GPIO30__FUNC_MSDC1_DAT3 (MTK_PIN_NO(30) | 1) -#define PINMUX_GPIO30__FUNC_DAP_MD32_SWD (MTK_PIN_NO(30) | 2) -#define PINMUX_GPIO30__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(30) | 3) -#define PINMUX_GPIO30__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(30) | 4) -#define PINMUX_GPIO30__FUNC_SSPM_JTAG_TRSTN (MTK_PIN_NO(30) | 5) -#define PINMUX_GPIO30__FUNC_PCM1_DI (MTK_PIN_NO(30) | 6) -#define PINMUX_GPIO30__FUNC_DBG_MON_A7 (MTK_PIN_NO(30) | 7) - -#define PINMUX_GPIO31__FUNC_GPIO31 (MTK_PIN_NO(31) | 0) -#define PINMUX_GPIO31__FUNC_MSDC1_CMD (MTK_PIN_NO(31) | 1) -#define PINMUX_GPIO31__FUNC_IO_JTAG_TMS (MTK_PIN_NO(31) | 2) -#define PINMUX_GPIO31__FUNC_UDI_TMS (MTK_PIN_NO(31) | 3) -#define PINMUX_GPIO31__FUNC_CONN_DSP_JMS (MTK_PIN_NO(31) | 4) -#define PINMUX_GPIO31__FUNC_SSPM_JTAG_TMS (MTK_PIN_NO(31) | 5) -#define PINMUX_GPIO31__FUNC_PCM1_SYNC (MTK_PIN_NO(31) | 6) -#define PINMUX_GPIO31__FUNC_DBG_MON_A8 (MTK_PIN_NO(31) | 7) - -#define PINMUX_GPIO32__FUNC_GPIO32 (MTK_PIN_NO(32) | 0) -#define PINMUX_GPIO32__FUNC_MSDC1_DAT0 (MTK_PIN_NO(32) | 1) -#define PINMUX_GPIO32__FUNC_IO_JTAG_TDI (MTK_PIN_NO(32) | 2) -#define PINMUX_GPIO32__FUNC_UDI_TDI (MTK_PIN_NO(32) | 3) -#define PINMUX_GPIO32__FUNC_CONN_DSP_JDI (MTK_PIN_NO(32) | 4) -#define PINMUX_GPIO32__FUNC_SSPM_JTAG_TDI (MTK_PIN_NO(32) | 5) -#define PINMUX_GPIO32__FUNC_PCM1_DO0 (MTK_PIN_NO(32) | 6) -#define PINMUX_GPIO32__FUNC_DBG_MON_A9 (MTK_PIN_NO(32) | 7) - -#define PINMUX_GPIO33__FUNC_GPIO33 (MTK_PIN_NO(33) | 0) -#define PINMUX_GPIO33__FUNC_MSDC1_DAT2 (MTK_PIN_NO(33) | 1) -#define PINMUX_GPIO33__FUNC_IO_JTAG_TRSTN (MTK_PIN_NO(33) | 2) -#define PINMUX_GPIO33__FUNC_UDI_NTRST (MTK_PIN_NO(33) | 3) -#define PINMUX_GPIO33__FUNC_DAP_MD32_SWCK (MTK_PIN_NO(33) | 4) -#define PINMUX_GPIO33__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(33) | 5) -#define PINMUX_GPIO33__FUNC_PCM1_DO2 (MTK_PIN_NO(33) | 6) -#define PINMUX_GPIO33__FUNC_DBG_MON_A10 (MTK_PIN_NO(33) | 7) - -#define PINMUX_GPIO34__FUNC_GPIO34 (MTK_PIN_NO(34) | 0) -#define PINMUX_GPIO34__FUNC_MSDC1_DAT1 (MTK_PIN_NO(34) | 1) -#define PINMUX_GPIO34__FUNC_IO_JTAG_TDO (MTK_PIN_NO(34) | 2) -#define PINMUX_GPIO34__FUNC_UDI_TDO (MTK_PIN_NO(34) | 3) -#define PINMUX_GPIO34__FUNC_CONN_DSP_JDO (MTK_PIN_NO(34) | 4) -#define PINMUX_GPIO34__FUNC_SSPM_JTAG_TDO (MTK_PIN_NO(34) | 5) -#define PINMUX_GPIO34__FUNC_PCM1_DO1 (MTK_PIN_NO(34) | 6) -#define PINMUX_GPIO34__FUNC_DBG_MON_A11 (MTK_PIN_NO(34) | 7) - -#define PINMUX_GPIO35__FUNC_GPIO35 (MTK_PIN_NO(35) | 0) -#define PINMUX_GPIO35__FUNC_MD1_SIM2_SIO (MTK_PIN_NO(35) | 1) -#define PINMUX_GPIO35__FUNC_CCU_JTAG_TDO (MTK_PIN_NO(35) | 2) -#define PINMUX_GPIO35__FUNC_MD1_SIM1_SIO (MTK_PIN_NO(35) | 3) -#define PINMUX_GPIO35__FUNC_SCP_JTAG_TDO (MTK_PIN_NO(35) | 5) -#define PINMUX_GPIO35__FUNC_CONN_DSP_JMS (MTK_PIN_NO(35) | 6) -#define PINMUX_GPIO35__FUNC_DBG_MON_A28 (MTK_PIN_NO(35) | 7) - -#define PINMUX_GPIO36__FUNC_GPIO36 (MTK_PIN_NO(36) | 0) -#define PINMUX_GPIO36__FUNC_MD1_SIM2_SRST (MTK_PIN_NO(36) | 1) -#define PINMUX_GPIO36__FUNC_CCU_JTAG_TMS (MTK_PIN_NO(36) | 2) -#define PINMUX_GPIO36__FUNC_MD1_SIM1_SRST (MTK_PIN_NO(36) | 3) -#define PINMUX_GPIO36__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(36) | 4) -#define PINMUX_GPIO36__FUNC_SCP_JTAG_TMS (MTK_PIN_NO(36) | 5) -#define PINMUX_GPIO36__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(36) | 6) -#define PINMUX_GPIO36__FUNC_DBG_MON_A29 (MTK_PIN_NO(36) | 7) - -#define PINMUX_GPIO37__FUNC_GPIO37 (MTK_PIN_NO(37) | 0) -#define PINMUX_GPIO37__FUNC_MD1_SIM2_SCLK (MTK_PIN_NO(37) | 1) -#define PINMUX_GPIO37__FUNC_CCU_JTAG_TDI (MTK_PIN_NO(37) | 2) -#define PINMUX_GPIO37__FUNC_MD1_SIM1_SCLK (MTK_PIN_NO(37) | 3) -#define PINMUX_GPIO37__FUNC_SCP_JTAG_TDI (MTK_PIN_NO(37) | 5) -#define PINMUX_GPIO37__FUNC_CONN_DSP_JDO (MTK_PIN_NO(37) | 6) -#define PINMUX_GPIO37__FUNC_DBG_MON_A30 (MTK_PIN_NO(37) | 7) - -#define PINMUX_GPIO38__FUNC_GPIO38 (MTK_PIN_NO(38) | 0) -#define PINMUX_GPIO38__FUNC_MD1_SIM1_SCLK (MTK_PIN_NO(38) | 1) -#define PINMUX_GPIO38__FUNC_MD1_SIM2_SCLK (MTK_PIN_NO(38) | 3) -#define PINMUX_GPIO38__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(38) | 4) -#define PINMUX_GPIO38__FUNC_DBG_MON_A20 (MTK_PIN_NO(38) | 7) - -#define PINMUX_GPIO39__FUNC_GPIO39 (MTK_PIN_NO(39) | 0) -#define PINMUX_GPIO39__FUNC_MD1_SIM1_SRST (MTK_PIN_NO(39) | 1) -#define PINMUX_GPIO39__FUNC_CCU_JTAG_TCK (MTK_PIN_NO(39) | 2) -#define PINMUX_GPIO39__FUNC_MD1_SIM2_SRST (MTK_PIN_NO(39) | 3) -#define PINMUX_GPIO39__FUNC_SCP_JTAG_TCK (MTK_PIN_NO(39) | 5) -#define PINMUX_GPIO39__FUNC_CONN_DSP_JCK (MTK_PIN_NO(39) | 6) -#define PINMUX_GPIO39__FUNC_DBG_MON_A31 (MTK_PIN_NO(39) | 7) - -#define PINMUX_GPIO40__FUNC_GPIO40 (MTK_PIN_NO(40) | 0) -#define PINMUX_GPIO40__FUNC_MD1_SIM1_SIO (MTK_PIN_NO(40) | 1) -#define PINMUX_GPIO40__FUNC_CCU_JTAG_TRST (MTK_PIN_NO(40) | 2) -#define PINMUX_GPIO40__FUNC_MD1_SIM2_SIO (MTK_PIN_NO(40) | 3) -#define PINMUX_GPIO40__FUNC_SCP_JTAG_TRSTN (MTK_PIN_NO(40) | 5) -#define PINMUX_GPIO40__FUNC_CONN_DSP_JDI (MTK_PIN_NO(40) | 6) -#define PINMUX_GPIO40__FUNC_DBG_MON_A32 (MTK_PIN_NO(40) | 7) - -#define PINMUX_GPIO41__FUNC_GPIO41 (MTK_PIN_NO(41) | 0) -#define PINMUX_GPIO41__FUNC_IDDIG (MTK_PIN_NO(41) | 1) -#define PINMUX_GPIO41__FUNC_URXD1 (MTK_PIN_NO(41) | 2) -#define PINMUX_GPIO41__FUNC_UCTS0 (MTK_PIN_NO(41) | 3) -#define PINMUX_GPIO41__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(41) | 4) -#define PINMUX_GPIO41__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(41) | 5) -#define PINMUX_GPIO41__FUNC_DMIC_CLK (MTK_PIN_NO(41) | 6) - -#define PINMUX_GPIO42__FUNC_GPIO42 (MTK_PIN_NO(42) | 0) -#define PINMUX_GPIO42__FUNC_USB_DRVVBUS (MTK_PIN_NO(42) | 1) -#define PINMUX_GPIO42__FUNC_UTXD1 (MTK_PIN_NO(42) | 2) -#define PINMUX_GPIO42__FUNC_URTS0 (MTK_PIN_NO(42) | 3) -#define PINMUX_GPIO42__FUNC_SSPM_URXD_AO (MTK_PIN_NO(42) | 4) -#define PINMUX_GPIO42__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(42) | 5) -#define PINMUX_GPIO42__FUNC_DMIC_DAT (MTK_PIN_NO(42) | 6) - -#define PINMUX_GPIO43__FUNC_GPIO43 (MTK_PIN_NO(43) | 0) -#define PINMUX_GPIO43__FUNC_DISP_PWM (MTK_PIN_NO(43) | 1) - -#define PINMUX_GPIO44__FUNC_GPIO44 (MTK_PIN_NO(44) | 0) -#define PINMUX_GPIO44__FUNC_DSI_TE (MTK_PIN_NO(44) | 1) - -#define PINMUX_GPIO45__FUNC_GPIO45 (MTK_PIN_NO(45) | 0) -#define PINMUX_GPIO45__FUNC_LCM_RST (MTK_PIN_NO(45) | 1) - -#define PINMUX_GPIO46__FUNC_GPIO46 (MTK_PIN_NO(46) | 0) -#define PINMUX_GPIO46__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(46) | 1) -#define PINMUX_GPIO46__FUNC_URXD1 (MTK_PIN_NO(46) | 2) -#define PINMUX_GPIO46__FUNC_UCTS1 (MTK_PIN_NO(46) | 3) -#define PINMUX_GPIO46__FUNC_CCU_UTXD_AO (MTK_PIN_NO(46) | 4) -#define PINMUX_GPIO46__FUNC_TP_UCTS1_AO (MTK_PIN_NO(46) | 5) -#define PINMUX_GPIO46__FUNC_IDDIG (MTK_PIN_NO(46) | 6) -#define PINMUX_GPIO46__FUNC_I2S5_LRCK (MTK_PIN_NO(46) | 7) - -#define PINMUX_GPIO47__FUNC_GPIO47 (MTK_PIN_NO(47) | 0) -#define PINMUX_GPIO47__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(47) | 1) -#define PINMUX_GPIO47__FUNC_UTXD1 (MTK_PIN_NO(47) | 2) -#define PINMUX_GPIO47__FUNC_URTS1 (MTK_PIN_NO(47) | 3) -#define PINMUX_GPIO47__FUNC_CCU_URXD_AO (MTK_PIN_NO(47) | 4) -#define PINMUX_GPIO47__FUNC_TP_URTS1_AO (MTK_PIN_NO(47) | 5) -#define PINMUX_GPIO47__FUNC_USB_DRVVBUS (MTK_PIN_NO(47) | 6) -#define PINMUX_GPIO47__FUNC_I2S5_DO (MTK_PIN_NO(47) | 7) - -#define PINMUX_GPIO48__FUNC_GPIO48 (MTK_PIN_NO(48) | 0) -#define PINMUX_GPIO48__FUNC_SCL5 (MTK_PIN_NO(48) | 1) - -#define PINMUX_GPIO49__FUNC_GPIO49 (MTK_PIN_NO(49) | 0) -#define PINMUX_GPIO49__FUNC_SDA5 (MTK_PIN_NO(49) | 1) - -#define PINMUX_GPIO50__FUNC_GPIO50 (MTK_PIN_NO(50) | 0) -#define PINMUX_GPIO50__FUNC_SCL3 (MTK_PIN_NO(50) | 1) - -#define PINMUX_GPIO51__FUNC_GPIO51 (MTK_PIN_NO(51) | 0) -#define PINMUX_GPIO51__FUNC_SDA3 (MTK_PIN_NO(51) | 1) - -#define PINMUX_GPIO52__FUNC_GPIO52 (MTK_PIN_NO(52) | 0) -#define PINMUX_GPIO52__FUNC_BPI_ANT2 (MTK_PIN_NO(52) | 1) - -#define PINMUX_GPIO53__FUNC_GPIO53 (MTK_PIN_NO(53) | 0) -#define PINMUX_GPIO53__FUNC_BPI_ANT0 (MTK_PIN_NO(53) | 1) - -#define PINMUX_GPIO54__FUNC_GPIO54 (MTK_PIN_NO(54) | 0) -#define PINMUX_GPIO54__FUNC_BPI_OLAT1 (MTK_PIN_NO(54) | 1) - -#define PINMUX_GPIO55__FUNC_GPIO55 (MTK_PIN_NO(55) | 0) -#define PINMUX_GPIO55__FUNC_BPI_BUS8 (MTK_PIN_NO(55) | 1) - -#define PINMUX_GPIO56__FUNC_GPIO56 (MTK_PIN_NO(56) | 0) -#define PINMUX_GPIO56__FUNC_BPI_BUS9 (MTK_PIN_NO(56) | 1) -#define PINMUX_GPIO56__FUNC_SCL_6306 (MTK_PIN_NO(56) | 2) - -#define PINMUX_GPIO57__FUNC_GPIO57 (MTK_PIN_NO(57) | 0) -#define PINMUX_GPIO57__FUNC_BPI_BUS10 (MTK_PIN_NO(57) | 1) -#define PINMUX_GPIO57__FUNC_SDA_6306 (MTK_PIN_NO(57) | 2) - -#define PINMUX_GPIO58__FUNC_GPIO58 (MTK_PIN_NO(58) | 0) -#define PINMUX_GPIO58__FUNC_RFIC0_BSI_D2 (MTK_PIN_NO(58) | 1) -#define PINMUX_GPIO58__FUNC_SPM_BSI_D2 (MTK_PIN_NO(58) | 2) -#define PINMUX_GPIO58__FUNC_PWM_B (MTK_PIN_NO(58) | 3) - -#define PINMUX_GPIO59__FUNC_GPIO59 (MTK_PIN_NO(59) | 0) -#define PINMUX_GPIO59__FUNC_RFIC0_BSI_D1 (MTK_PIN_NO(59) | 1) -#define PINMUX_GPIO59__FUNC_SPM_BSI_D1 (MTK_PIN_NO(59) | 2) - -#define PINMUX_GPIO60__FUNC_GPIO60 (MTK_PIN_NO(60) | 0) -#define PINMUX_GPIO60__FUNC_RFIC0_BSI_D0 (MTK_PIN_NO(60) | 1) -#define PINMUX_GPIO60__FUNC_SPM_BSI_D0 (MTK_PIN_NO(60) | 2) - -#define PINMUX_GPIO61__FUNC_GPIO61 (MTK_PIN_NO(61) | 0) -#define PINMUX_GPIO61__FUNC_MIPI1_SDATA (MTK_PIN_NO(61) | 1) - -#define PINMUX_GPIO62__FUNC_GPIO62 (MTK_PIN_NO(62) | 0) -#define PINMUX_GPIO62__FUNC_MIPI1_SCLK (MTK_PIN_NO(62) | 1) - -#define PINMUX_GPIO63__FUNC_GPIO63 (MTK_PIN_NO(63) | 0) -#define PINMUX_GPIO63__FUNC_MIPI0_SDATA (MTK_PIN_NO(63) | 1) - -#define PINMUX_GPIO64__FUNC_GPIO64 (MTK_PIN_NO(64) | 0) -#define PINMUX_GPIO64__FUNC_MIPI0_SCLK (MTK_PIN_NO(64) | 1) - -#define PINMUX_GPIO65__FUNC_GPIO65 (MTK_PIN_NO(65) | 0) -#define PINMUX_GPIO65__FUNC_MIPI3_SDATA (MTK_PIN_NO(65) | 1) -#define PINMUX_GPIO65__FUNC_BPI_OLAT2 (MTK_PIN_NO(65) | 2) - -#define PINMUX_GPIO66__FUNC_GPIO66 (MTK_PIN_NO(66) | 0) -#define PINMUX_GPIO66__FUNC_MIPI3_SCLK (MTK_PIN_NO(66) | 1) -#define PINMUX_GPIO66__FUNC_BPI_OLAT3 (MTK_PIN_NO(66) | 2) - -#define PINMUX_GPIO67__FUNC_GPIO67 (MTK_PIN_NO(67) | 0) -#define PINMUX_GPIO67__FUNC_MIPI2_SDATA (MTK_PIN_NO(67) | 1) - -#define PINMUX_GPIO68__FUNC_GPIO68 (MTK_PIN_NO(68) | 0) -#define PINMUX_GPIO68__FUNC_MIPI2_SCLK (MTK_PIN_NO(68) | 1) - -#define PINMUX_GPIO69__FUNC_GPIO69 (MTK_PIN_NO(69) | 0) -#define PINMUX_GPIO69__FUNC_BPI_BUS7 (MTK_PIN_NO(69) | 1) - -#define PINMUX_GPIO70__FUNC_GPIO70 (MTK_PIN_NO(70) | 0) -#define PINMUX_GPIO70__FUNC_BPI_BUS6 (MTK_PIN_NO(70) | 1) - -#define PINMUX_GPIO71__FUNC_GPIO71 (MTK_PIN_NO(71) | 0) -#define PINMUX_GPIO71__FUNC_BPI_BUS5 (MTK_PIN_NO(71) | 1) - -#define PINMUX_GPIO72__FUNC_GPIO72 (MTK_PIN_NO(72) | 0) -#define PINMUX_GPIO72__FUNC_BPI_BUS4 (MTK_PIN_NO(72) | 1) - -#define PINMUX_GPIO73__FUNC_GPIO73 (MTK_PIN_NO(73) | 0) -#define PINMUX_GPIO73__FUNC_BPI_BUS3 (MTK_PIN_NO(73) | 1) - -#define PINMUX_GPIO74__FUNC_GPIO74 (MTK_PIN_NO(74) | 0) -#define PINMUX_GPIO74__FUNC_BPI_BUS2 (MTK_PIN_NO(74) | 1) - -#define PINMUX_GPIO75__FUNC_GPIO75 (MTK_PIN_NO(75) | 0) -#define PINMUX_GPIO75__FUNC_BPI_BUS1 (MTK_PIN_NO(75) | 1) - -#define PINMUX_GPIO76__FUNC_GPIO76 (MTK_PIN_NO(76) | 0) -#define PINMUX_GPIO76__FUNC_BPI_BUS0 (MTK_PIN_NO(76) | 1) - -#define PINMUX_GPIO77__FUNC_GPIO77 (MTK_PIN_NO(77) | 0) -#define PINMUX_GPIO77__FUNC_BPI_ANT1 (MTK_PIN_NO(77) | 1) - -#define PINMUX_GPIO78__FUNC_GPIO78 (MTK_PIN_NO(78) | 0) -#define PINMUX_GPIO78__FUNC_BPI_OLAT0 (MTK_PIN_NO(78) | 1) - -#define PINMUX_GPIO79__FUNC_GPIO79 (MTK_PIN_NO(79) | 0) -#define PINMUX_GPIO79__FUNC_BPI_PA_VM1 (MTK_PIN_NO(79) | 1) -#define PINMUX_GPIO79__FUNC_MIPI4_SDATA (MTK_PIN_NO(79) | 2) - -#define PINMUX_GPIO80__FUNC_GPIO80 (MTK_PIN_NO(80) | 0) -#define PINMUX_GPIO80__FUNC_BPI_PA_VM0 (MTK_PIN_NO(80) | 1) -#define PINMUX_GPIO80__FUNC_MIPI4_SCLK (MTK_PIN_NO(80) | 2) - -#define PINMUX_GPIO81__FUNC_GPIO81 (MTK_PIN_NO(81) | 0) -#define PINMUX_GPIO81__FUNC_SDA1 (MTK_PIN_NO(81) | 1) - -#define PINMUX_GPIO82__FUNC_GPIO82 (MTK_PIN_NO(82) | 0) -#define PINMUX_GPIO82__FUNC_SDA0 (MTK_PIN_NO(82) | 1) - -#define PINMUX_GPIO83__FUNC_GPIO83 (MTK_PIN_NO(83) | 0) -#define PINMUX_GPIO83__FUNC_SCL0 (MTK_PIN_NO(83) | 1) - -#define PINMUX_GPIO84__FUNC_GPIO84 (MTK_PIN_NO(84) | 0) -#define PINMUX_GPIO84__FUNC_SCL1 (MTK_PIN_NO(84) | 1) - -#define PINMUX_GPIO85__FUNC_GPIO85 (MTK_PIN_NO(85) | 0) -#define PINMUX_GPIO85__FUNC_SPI0_MI (MTK_PIN_NO(85) | 1) -#define PINMUX_GPIO85__FUNC_SCP_SPI0_MI (MTK_PIN_NO(85) | 2) -#define PINMUX_GPIO85__FUNC_CLKM3 (MTK_PIN_NO(85) | 3) -#define PINMUX_GPIO85__FUNC_I2S1_BCK (MTK_PIN_NO(85) | 4) -#define PINMUX_GPIO85__FUNC_MFG_DFD_JTAG_TDO (MTK_PIN_NO(85) | 5) -#define PINMUX_GPIO85__FUNC_DFD_TDO (MTK_PIN_NO(85) | 6) -#define PINMUX_GPIO85__FUNC_JTDO_SEL1 (MTK_PIN_NO(85) | 7) - -#define PINMUX_GPIO86__FUNC_GPIO86 (MTK_PIN_NO(86) | 0) -#define PINMUX_GPIO86__FUNC_SPI0_CSB (MTK_PIN_NO(86) | 1) -#define PINMUX_GPIO86__FUNC_SCP_SPI0_CS (MTK_PIN_NO(86) | 2) -#define PINMUX_GPIO86__FUNC_CLKM0 (MTK_PIN_NO(86) | 3) -#define PINMUX_GPIO86__FUNC_I2S1_LRCK (MTK_PIN_NO(86) | 4) -#define PINMUX_GPIO86__FUNC_MFG_DFD_JTAG_TMS (MTK_PIN_NO(86) | 5) -#define PINMUX_GPIO86__FUNC_DFD_TMS (MTK_PIN_NO(86) | 6) -#define PINMUX_GPIO86__FUNC_JTMS_SEL1 (MTK_PIN_NO(86) | 7) - -#define PINMUX_GPIO87__FUNC_GPIO87 (MTK_PIN_NO(87) | 0) -#define PINMUX_GPIO87__FUNC_SPI0_MO (MTK_PIN_NO(87) | 1) -#define PINMUX_GPIO87__FUNC_SCP_SPI0_MO (MTK_PIN_NO(87) | 2) -#define PINMUX_GPIO87__FUNC_SDA1 (MTK_PIN_NO(87) | 3) -#define PINMUX_GPIO87__FUNC_I2S1_DO (MTK_PIN_NO(87) | 4) -#define PINMUX_GPIO87__FUNC_MFG_DFD_JTAG_TDI (MTK_PIN_NO(87) | 5) -#define PINMUX_GPIO87__FUNC_DFD_TDI (MTK_PIN_NO(87) | 6) -#define PINMUX_GPIO87__FUNC_JTDI_SEL1 (MTK_PIN_NO(87) | 7) - -#define PINMUX_GPIO88__FUNC_GPIO88 (MTK_PIN_NO(88) | 0) -#define PINMUX_GPIO88__FUNC_SPI0_CLK (MTK_PIN_NO(88) | 1) -#define PINMUX_GPIO88__FUNC_SCP_SPI0_CK (MTK_PIN_NO(88) | 2) -#define PINMUX_GPIO88__FUNC_SCL1 (MTK_PIN_NO(88) | 3) -#define PINMUX_GPIO88__FUNC_I2S1_MCK (MTK_PIN_NO(88) | 4) -#define PINMUX_GPIO88__FUNC_MFG_DFD_JTAG_TCK (MTK_PIN_NO(88) | 5) -#define PINMUX_GPIO88__FUNC_DFD_TCK_XI (MTK_PIN_NO(88) | 6) -#define PINMUX_GPIO88__FUNC_JTCK_SEL1 (MTK_PIN_NO(88) | 7) - -#define PINMUX_GPIO89__FUNC_GPIO89 (MTK_PIN_NO(89) | 0) -#define PINMUX_GPIO89__FUNC_SRCLKENAI0 (MTK_PIN_NO(89) | 1) -#define PINMUX_GPIO89__FUNC_PWM_C (MTK_PIN_NO(89) | 2) -#define PINMUX_GPIO89__FUNC_I2S5_BCK (MTK_PIN_NO(89) | 3) -#define PINMUX_GPIO89__FUNC_ANT_SEL6 (MTK_PIN_NO(89) | 4) -#define PINMUX_GPIO89__FUNC_SDA8 (MTK_PIN_NO(89) | 5) -#define PINMUX_GPIO89__FUNC_CMVREF0 (MTK_PIN_NO(89) | 6) -#define PINMUX_GPIO89__FUNC_DBG_MON_A21 (MTK_PIN_NO(89) | 7) - -#define PINMUX_GPIO90__FUNC_GPIO90 (MTK_PIN_NO(90) | 0) -#define PINMUX_GPIO90__FUNC_PWM_A (MTK_PIN_NO(90) | 1) -#define PINMUX_GPIO90__FUNC_CMMCLK2 (MTK_PIN_NO(90) | 2) -#define PINMUX_GPIO90__FUNC_I2S5_LRCK (MTK_PIN_NO(90) | 3) -#define PINMUX_GPIO90__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(90) | 4) -#define PINMUX_GPIO90__FUNC_SCL8 (MTK_PIN_NO(90) | 5) -#define PINMUX_GPIO90__FUNC_PTA_RXD (MTK_PIN_NO(90) | 6) -#define PINMUX_GPIO90__FUNC_DBG_MON_A22 (MTK_PIN_NO(90) | 7) - -#define PINMUX_GPIO91__FUNC_GPIO91 (MTK_PIN_NO(91) | 0) -#define PINMUX_GPIO91__FUNC_KPROW1 (MTK_PIN_NO(91) | 1) -#define PINMUX_GPIO91__FUNC_PWM_B (MTK_PIN_NO(91) | 2) -#define PINMUX_GPIO91__FUNC_I2S5_DO (MTK_PIN_NO(91) | 3) -#define PINMUX_GPIO91__FUNC_ANT_SEL7 (MTK_PIN_NO(91) | 4) -#define PINMUX_GPIO91__FUNC_CMMCLK3 (MTK_PIN_NO(91) | 5) -#define PINMUX_GPIO91__FUNC_PTA_TXD (MTK_PIN_NO(91) | 6) - -#define PINMUX_GPIO92__FUNC_GPIO92 (MTK_PIN_NO(92) | 0) -#define PINMUX_GPIO92__FUNC_KPROW0 (MTK_PIN_NO(92) | 1) - -#define PINMUX_GPIO93__FUNC_GPIO93 (MTK_PIN_NO(93) | 0) -#define PINMUX_GPIO93__FUNC_KPCOL0 (MTK_PIN_NO(93) | 1) -#define PINMUX_GPIO93__FUNC_DBG_MON_B27 (MTK_PIN_NO(93) | 7) - -#define PINMUX_GPIO94__FUNC_GPIO94 (MTK_PIN_NO(94) | 0) -#define PINMUX_GPIO94__FUNC_KPCOL1 (MTK_PIN_NO(94) | 1) -#define PINMUX_GPIO94__FUNC_I2S2_DI2 (MTK_PIN_NO(94) | 2) -#define PINMUX_GPIO94__FUNC_I2S5_MCK (MTK_PIN_NO(94) | 3) -#define PINMUX_GPIO94__FUNC_CMMCLK2 (MTK_PIN_NO(94) | 4) -#define PINMUX_GPIO94__FUNC_SCP_SPI2_MI (MTK_PIN_NO(94) | 5) -#define PINMUX_GPIO94__FUNC_SRCLKENAI1 (MTK_PIN_NO(94) | 6) -#define PINMUX_GPIO94__FUNC_SPI2_MI (MTK_PIN_NO(94) | 7) - -#define PINMUX_GPIO95__FUNC_GPIO95 (MTK_PIN_NO(95) | 0) -#define PINMUX_GPIO95__FUNC_URXD0 (MTK_PIN_NO(95) | 1) -#define PINMUX_GPIO95__FUNC_UTXD0 (MTK_PIN_NO(95) | 2) -#define PINMUX_GPIO95__FUNC_MD_URXD0 (MTK_PIN_NO(95) | 3) -#define PINMUX_GPIO95__FUNC_MD_URXD1 (MTK_PIN_NO(95) | 4) -#define PINMUX_GPIO95__FUNC_SSPM_URXD_AO (MTK_PIN_NO(95) | 5) -#define PINMUX_GPIO95__FUNC_CCU_URXD_AO (MTK_PIN_NO(95) | 6) - -#define PINMUX_GPIO96__FUNC_GPIO96 (MTK_PIN_NO(96) | 0) -#define PINMUX_GPIO96__FUNC_UTXD0 (MTK_PIN_NO(96) | 1) -#define PINMUX_GPIO96__FUNC_URXD0 (MTK_PIN_NO(96) | 2) -#define PINMUX_GPIO96__FUNC_MD_UTXD0 (MTK_PIN_NO(96) | 3) -#define PINMUX_GPIO96__FUNC_MD_UTXD1 (MTK_PIN_NO(96) | 4) -#define PINMUX_GPIO96__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(96) | 5) -#define PINMUX_GPIO96__FUNC_CCU_UTXD_AO (MTK_PIN_NO(96) | 6) -#define PINMUX_GPIO96__FUNC_DBG_MON_B2 (MTK_PIN_NO(96) | 7) - -#define PINMUX_GPIO97__FUNC_GPIO97 (MTK_PIN_NO(97) | 0) -#define PINMUX_GPIO97__FUNC_UCTS0 (MTK_PIN_NO(97) | 1) -#define PINMUX_GPIO97__FUNC_I2S2_MCK (MTK_PIN_NO(97) | 2) -#define PINMUX_GPIO97__FUNC_IDDIG (MTK_PIN_NO(97) | 3) -#define PINMUX_GPIO97__FUNC_CONN_MCU_TDO (MTK_PIN_NO(97) | 4) -#define PINMUX_GPIO97__FUNC_SSPM_JTAG_TDO (MTK_PIN_NO(97) | 5) -#define PINMUX_GPIO97__FUNC_IO_JTAG_TDO (MTK_PIN_NO(97) | 6) -#define PINMUX_GPIO97__FUNC_DBG_MON_B3 (MTK_PIN_NO(97) | 7) - -#define PINMUX_GPIO98__FUNC_GPIO98 (MTK_PIN_NO(98) | 0) -#define PINMUX_GPIO98__FUNC_URTS0 (MTK_PIN_NO(98) | 1) -#define PINMUX_GPIO98__FUNC_I2S2_BCK (MTK_PIN_NO(98) | 2) -#define PINMUX_GPIO98__FUNC_USB_DRVVBUS (MTK_PIN_NO(98) | 3) -#define PINMUX_GPIO98__FUNC_CONN_MCU_TMS (MTK_PIN_NO(98) | 4) -#define PINMUX_GPIO98__FUNC_SSPM_JTAG_TMS (MTK_PIN_NO(98) | 5) -#define PINMUX_GPIO98__FUNC_IO_JTAG_TMS (MTK_PIN_NO(98) | 6) -#define PINMUX_GPIO98__FUNC_DBG_MON_B4 (MTK_PIN_NO(98) | 7) - -#define PINMUX_GPIO99__FUNC_GPIO99 (MTK_PIN_NO(99) | 0) -#define PINMUX_GPIO99__FUNC_CMMCLK0 (MTK_PIN_NO(99) | 1) -#define PINMUX_GPIO99__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(99) | 4) -#define PINMUX_GPIO99__FUNC_DBG_MON_B28 (MTK_PIN_NO(99) | 7) - -#define PINMUX_GPIO100__FUNC_GPIO100 (MTK_PIN_NO(100) | 0) -#define PINMUX_GPIO100__FUNC_CMMCLK1 (MTK_PIN_NO(100) | 1) -#define PINMUX_GPIO100__FUNC_PWM_C (MTK_PIN_NO(100) | 2) -#define PINMUX_GPIO100__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(100) | 3) -#define PINMUX_GPIO100__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(100) | 4) -#define PINMUX_GPIO100__FUNC_DBG_MON_B29 (MTK_PIN_NO(100) | 7) - -#define PINMUX_GPIO101__FUNC_GPIO101 (MTK_PIN_NO(101) | 0) -#define PINMUX_GPIO101__FUNC_CLKM2 (MTK_PIN_NO(101) | 1) -#define PINMUX_GPIO101__FUNC_I2S2_LRCK (MTK_PIN_NO(101) | 2) -#define PINMUX_GPIO101__FUNC_CMVREF1 (MTK_PIN_NO(101) | 3) -#define PINMUX_GPIO101__FUNC_CONN_MCU_TCK (MTK_PIN_NO(101) | 4) -#define PINMUX_GPIO101__FUNC_SSPM_JTAG_TCK (MTK_PIN_NO(101) | 5) -#define PINMUX_GPIO101__FUNC_IO_JTAG_TCK (MTK_PIN_NO(101) | 6) - -#define PINMUX_GPIO102__FUNC_GPIO102 (MTK_PIN_NO(102) | 0) -#define PINMUX_GPIO102__FUNC_CLKM1 (MTK_PIN_NO(102) | 1) -#define PINMUX_GPIO102__FUNC_I2S2_DI (MTK_PIN_NO(102) | 2) -#define PINMUX_GPIO102__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(102) | 3) -#define PINMUX_GPIO102__FUNC_CONN_MCU_TDI (MTK_PIN_NO(102) | 4) -#define PINMUX_GPIO102__FUNC_SSPM_JTAG_TDI (MTK_PIN_NO(102) | 5) -#define PINMUX_GPIO102__FUNC_IO_JTAG_TDI (MTK_PIN_NO(102) | 6) -#define PINMUX_GPIO102__FUNC_DBG_MON_B8 (MTK_PIN_NO(102) | 7) - -#define PINMUX_GPIO103__FUNC_GPIO103 (MTK_PIN_NO(103) | 0) -#define PINMUX_GPIO103__FUNC_SCL2 (MTK_PIN_NO(103) | 1) - -#define PINMUX_GPIO104__FUNC_GPIO104 (MTK_PIN_NO(104) | 0) -#define PINMUX_GPIO104__FUNC_SDA2 (MTK_PIN_NO(104) | 1) - -#define PINMUX_GPIO105__FUNC_GPIO105 (MTK_PIN_NO(105) | 0) -#define PINMUX_GPIO105__FUNC_SCL4 (MTK_PIN_NO(105) | 1) - -#define PINMUX_GPIO106__FUNC_GPIO106 (MTK_PIN_NO(106) | 0) -#define PINMUX_GPIO106__FUNC_SDA4 (MTK_PIN_NO(106) | 1) - -#define PINMUX_GPIO107__FUNC_GPIO107 (MTK_PIN_NO(107) | 0) -#define PINMUX_GPIO107__FUNC_DMIC_CLK (MTK_PIN_NO(107) | 1) -#define PINMUX_GPIO107__FUNC_ANT_SEL0 (MTK_PIN_NO(107) | 2) -#define PINMUX_GPIO107__FUNC_CLKM0 (MTK_PIN_NO(107) | 3) -#define PINMUX_GPIO107__FUNC_SDA7 (MTK_PIN_NO(107) | 4) -#define PINMUX_GPIO107__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(107) | 5) -#define PINMUX_GPIO107__FUNC_PWM_A (MTK_PIN_NO(107) | 6) -#define PINMUX_GPIO107__FUNC_DBG_MON_B12 (MTK_PIN_NO(107) | 7) - -#define PINMUX_GPIO108__FUNC_GPIO108 (MTK_PIN_NO(108) | 0) -#define PINMUX_GPIO108__FUNC_CMMCLK2 (MTK_PIN_NO(108) | 1) -#define PINMUX_GPIO108__FUNC_ANT_SEL1 (MTK_PIN_NO(108) | 2) -#define PINMUX_GPIO108__FUNC_CLKM1 (MTK_PIN_NO(108) | 3) -#define PINMUX_GPIO108__FUNC_SCL8 (MTK_PIN_NO(108) | 4) -#define PINMUX_GPIO108__FUNC_DAP_MD32_SWD (MTK_PIN_NO(108) | 5) -#define PINMUX_GPIO108__FUNC_PWM_B (MTK_PIN_NO(108) | 6) -#define PINMUX_GPIO108__FUNC_DBG_MON_B13 (MTK_PIN_NO(108) | 7) - -#define PINMUX_GPIO109__FUNC_GPIO109 (MTK_PIN_NO(109) | 0) -#define PINMUX_GPIO109__FUNC_DMIC_DAT (MTK_PIN_NO(109) | 1) -#define PINMUX_GPIO109__FUNC_ANT_SEL2 (MTK_PIN_NO(109) | 2) -#define PINMUX_GPIO109__FUNC_CLKM2 (MTK_PIN_NO(109) | 3) -#define PINMUX_GPIO109__FUNC_SDA8 (MTK_PIN_NO(109) | 4) -#define PINMUX_GPIO109__FUNC_DAP_MD32_SWCK (MTK_PIN_NO(109) | 5) -#define PINMUX_GPIO109__FUNC_PWM_C (MTK_PIN_NO(109) | 6) -#define PINMUX_GPIO109__FUNC_DBG_MON_B14 (MTK_PIN_NO(109) | 7) - -#define PINMUX_GPIO110__FUNC_GPIO110 (MTK_PIN_NO(110) | 0) -#define PINMUX_GPIO110__FUNC_SCL7 (MTK_PIN_NO(110) | 1) -#define PINMUX_GPIO110__FUNC_ANT_SEL0 (MTK_PIN_NO(110) | 2) -#define PINMUX_GPIO110__FUNC_TP_URXD1_AO (MTK_PIN_NO(110) | 3) -#define PINMUX_GPIO110__FUNC_USB_DRVVBUS (MTK_PIN_NO(110) | 4) -#define PINMUX_GPIO110__FUNC_SRCLKENAI1 (MTK_PIN_NO(110) | 5) -#define PINMUX_GPIO110__FUNC_KPCOL2 (MTK_PIN_NO(110) | 6) -#define PINMUX_GPIO110__FUNC_URXD1 (MTK_PIN_NO(110) | 7) - -#define PINMUX_GPIO111__FUNC_GPIO111 (MTK_PIN_NO(111) | 0) -#define PINMUX_GPIO111__FUNC_CMMCLK3 (MTK_PIN_NO(111) | 1) -#define PINMUX_GPIO111__FUNC_ANT_SEL1 (MTK_PIN_NO(111) | 2) -#define PINMUX_GPIO111__FUNC_SRCLKENAI0 (MTK_PIN_NO(111) | 3) -#define PINMUX_GPIO111__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(111) | 4) -#define PINMUX_GPIO111__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(111) | 5) -#define PINMUX_GPIO111__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(111) | 7) - -#define PINMUX_GPIO112__FUNC_GPIO112 (MTK_PIN_NO(112) | 0) -#define PINMUX_GPIO112__FUNC_SDA7 (MTK_PIN_NO(112) | 1) -#define PINMUX_GPIO112__FUNC_ANT_SEL2 (MTK_PIN_NO(112) | 2) -#define PINMUX_GPIO112__FUNC_TP_UTXD1_AO (MTK_PIN_NO(112) | 3) -#define PINMUX_GPIO112__FUNC_IDDIG (MTK_PIN_NO(112) | 4) -#define PINMUX_GPIO112__FUNC_AGPS_SYNC (MTK_PIN_NO(112) | 5) -#define PINMUX_GPIO112__FUNC_KPROW2 (MTK_PIN_NO(112) | 6) -#define PINMUX_GPIO112__FUNC_UTXD1 (MTK_PIN_NO(112) | 7) - -#define PINMUX_GPIO113__FUNC_GPIO113 (MTK_PIN_NO(113) | 0) -#define PINMUX_GPIO113__FUNC_CONN_TOP_CLK (MTK_PIN_NO(113) | 1) -#define PINMUX_GPIO113__FUNC_SCL6 (MTK_PIN_NO(113) | 3) -#define PINMUX_GPIO113__FUNC_AUXIF_CLK0 (MTK_PIN_NO(113) | 4) -#define PINMUX_GPIO113__FUNC_TP_UCTS1_AO (MTK_PIN_NO(113) | 6) - -#define PINMUX_GPIO114__FUNC_GPIO114 (MTK_PIN_NO(114) | 0) -#define PINMUX_GPIO114__FUNC_CONN_TOP_DATA (MTK_PIN_NO(114) | 1) -#define PINMUX_GPIO114__FUNC_SDA6 (MTK_PIN_NO(114) | 3) -#define PINMUX_GPIO114__FUNC_AUXIF_ST0 (MTK_PIN_NO(114) | 4) -#define PINMUX_GPIO114__FUNC_TP_URTS1_AO (MTK_PIN_NO(114) | 6) - -#define PINMUX_GPIO115__FUNC_GPIO115 (MTK_PIN_NO(115) | 0) -#define PINMUX_GPIO115__FUNC_CONN_BT_CLK (MTK_PIN_NO(115) | 1) -#define PINMUX_GPIO115__FUNC_UTXD1 (MTK_PIN_NO(115) | 2) -#define PINMUX_GPIO115__FUNC_PTA_TXD (MTK_PIN_NO(115) | 3) -#define PINMUX_GPIO115__FUNC_AUXIF_CLK1 (MTK_PIN_NO(115) | 4) -#define PINMUX_GPIO115__FUNC_DAP_MD32_SWD (MTK_PIN_NO(115) | 5) -#define PINMUX_GPIO115__FUNC_TP_UTXD1_AO (MTK_PIN_NO(115) | 6) - -#define PINMUX_GPIO116__FUNC_GPIO116 (MTK_PIN_NO(116) | 0) -#define PINMUX_GPIO116__FUNC_CONN_BT_DATA (MTK_PIN_NO(116) | 1) -#define PINMUX_GPIO116__FUNC_IPU_JTAG_TRST (MTK_PIN_NO(116) | 2) -#define PINMUX_GPIO116__FUNC_AUXIF_ST1 (MTK_PIN_NO(116) | 4) -#define PINMUX_GPIO116__FUNC_DAP_MD32_SWCK (MTK_PIN_NO(116) | 5) -#define PINMUX_GPIO116__FUNC_TP_URXD2_AO (MTK_PIN_NO(116) | 6) -#define PINMUX_GPIO116__FUNC_DBG_MON_A0 (MTK_PIN_NO(116) | 7) - -#define PINMUX_GPIO117__FUNC_GPIO117 (MTK_PIN_NO(117) | 0) -#define PINMUX_GPIO117__FUNC_CONN_WF_HB0 (MTK_PIN_NO(117) | 1) -#define PINMUX_GPIO117__FUNC_IPU_JTAG_TDO (MTK_PIN_NO(117) | 2) -#define PINMUX_GPIO117__FUNC_TP_UTXD2_AO (MTK_PIN_NO(117) | 6) -#define PINMUX_GPIO117__FUNC_DBG_MON_A4 (MTK_PIN_NO(117) | 7) - -#define PINMUX_GPIO118__FUNC_GPIO118 (MTK_PIN_NO(118) | 0) -#define PINMUX_GPIO118__FUNC_CONN_WF_HB1 (MTK_PIN_NO(118) | 1) -#define PINMUX_GPIO118__FUNC_IPU_JTAG_TDI (MTK_PIN_NO(118) | 2) -#define PINMUX_GPIO118__FUNC_SSPM_URXD_AO (MTK_PIN_NO(118) | 5) -#define PINMUX_GPIO118__FUNC_TP_UCTS2_AO (MTK_PIN_NO(118) | 6) -#define PINMUX_GPIO118__FUNC_DBG_MON_A5 (MTK_PIN_NO(118) | 7) - -#define PINMUX_GPIO119__FUNC_GPIO119 (MTK_PIN_NO(119) | 0) -#define PINMUX_GPIO119__FUNC_CONN_WF_HB2 (MTK_PIN_NO(119) | 1) -#define PINMUX_GPIO119__FUNC_IPU_JTAG_TCK (MTK_PIN_NO(119) | 2) -#define PINMUX_GPIO119__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(119) | 5) -#define PINMUX_GPIO119__FUNC_TP_URTS2_AO (MTK_PIN_NO(119) | 6) - -#define PINMUX_GPIO120__FUNC_GPIO120 (MTK_PIN_NO(120) | 0) -#define PINMUX_GPIO120__FUNC_CONN_WB_PTA (MTK_PIN_NO(120) | 1) -#define PINMUX_GPIO120__FUNC_IPU_JTAG_TMS (MTK_PIN_NO(120) | 2) -#define PINMUX_GPIO120__FUNC_CCU_URXD_AO (MTK_PIN_NO(120) | 5) - -#define PINMUX_GPIO121__FUNC_GPIO121 (MTK_PIN_NO(121) | 0) -#define PINMUX_GPIO121__FUNC_CONN_HRST_B (MTK_PIN_NO(121) | 1) -#define PINMUX_GPIO121__FUNC_URXD1 (MTK_PIN_NO(121) | 2) -#define PINMUX_GPIO121__FUNC_PTA_RXD (MTK_PIN_NO(121) | 3) -#define PINMUX_GPIO121__FUNC_CCU_UTXD_AO (MTK_PIN_NO(121) | 5) -#define PINMUX_GPIO121__FUNC_TP_URXD1_AO (MTK_PIN_NO(121) | 6) - -#define PINMUX_GPIO122__FUNC_GPIO122 (MTK_PIN_NO(122) | 0) -#define PINMUX_GPIO122__FUNC_MSDC0_CMD (MTK_PIN_NO(122) | 1) -#define PINMUX_GPIO122__FUNC_SSPM_URXD2_AO (MTK_PIN_NO(122) | 2) -#define PINMUX_GPIO122__FUNC_ANT_SEL1 (MTK_PIN_NO(122) | 3) -#define PINMUX_GPIO122__FUNC_DBG_MON_A12 (MTK_PIN_NO(122) | 7) - -#define PINMUX_GPIO123__FUNC_GPIO123 (MTK_PIN_NO(123) | 0) -#define PINMUX_GPIO123__FUNC_MSDC0_DAT0 (MTK_PIN_NO(123) | 1) -#define PINMUX_GPIO123__FUNC_ANT_SEL0 (MTK_PIN_NO(123) | 3) -#define PINMUX_GPIO123__FUNC_DBG_MON_A13 (MTK_PIN_NO(123) | 7) - -#define PINMUX_GPIO124__FUNC_GPIO124 (MTK_PIN_NO(124) | 0) -#define PINMUX_GPIO124__FUNC_MSDC0_CLK (MTK_PIN_NO(124) | 1) -#define PINMUX_GPIO124__FUNC_DBG_MON_A14 (MTK_PIN_NO(124) | 7) - -#define PINMUX_GPIO125__FUNC_GPIO125 (MTK_PIN_NO(125) | 0) -#define PINMUX_GPIO125__FUNC_MSDC0_DAT2 (MTK_PIN_NO(125) | 1) -#define PINMUX_GPIO125__FUNC_MRG_CLK (MTK_PIN_NO(125) | 3) -#define PINMUX_GPIO125__FUNC_DBG_MON_A15 (MTK_PIN_NO(125) | 7) - -#define PINMUX_GPIO126__FUNC_GPIO126 (MTK_PIN_NO(126) | 0) -#define PINMUX_GPIO126__FUNC_MSDC0_DAT4 (MTK_PIN_NO(126) | 1) -#define PINMUX_GPIO126__FUNC_ANT_SEL5 (MTK_PIN_NO(126) | 3) -#define PINMUX_GPIO126__FUNC_UFS_MPHY_SCL (MTK_PIN_NO(126) | 6) -#define PINMUX_GPIO126__FUNC_DBG_MON_A16 (MTK_PIN_NO(126) | 7) - -#define PINMUX_GPIO127__FUNC_GPIO127 (MTK_PIN_NO(127) | 0) -#define PINMUX_GPIO127__FUNC_MSDC0_DAT6 (MTK_PIN_NO(127) | 1) -#define PINMUX_GPIO127__FUNC_ANT_SEL4 (MTK_PIN_NO(127) | 3) -#define PINMUX_GPIO127__FUNC_UFS_MPHY_SDA (MTK_PIN_NO(127) | 6) -#define PINMUX_GPIO127__FUNC_DBG_MON_A17 (MTK_PIN_NO(127) | 7) - -#define PINMUX_GPIO128__FUNC_GPIO128 (MTK_PIN_NO(128) | 0) -#define PINMUX_GPIO128__FUNC_MSDC0_DAT1 (MTK_PIN_NO(128) | 1) -#define PINMUX_GPIO128__FUNC_ANT_SEL2 (MTK_PIN_NO(128) | 3) -#define PINMUX_GPIO128__FUNC_UFS_UNIPRO_SDA (MTK_PIN_NO(128) | 6) -#define PINMUX_GPIO128__FUNC_DBG_MON_A18 (MTK_PIN_NO(128) | 7) - -#define PINMUX_GPIO129__FUNC_GPIO129 (MTK_PIN_NO(129) | 0) -#define PINMUX_GPIO129__FUNC_MSDC0_DAT5 (MTK_PIN_NO(129) | 1) -#define PINMUX_GPIO129__FUNC_ANT_SEL3 (MTK_PIN_NO(129) | 3) -#define PINMUX_GPIO129__FUNC_UFS_UNIPRO_SCL (MTK_PIN_NO(129) | 6) -#define PINMUX_GPIO129__FUNC_DBG_MON_A23 (MTK_PIN_NO(129) | 7) - -#define PINMUX_GPIO130__FUNC_GPIO130 (MTK_PIN_NO(130) | 0) -#define PINMUX_GPIO130__FUNC_MSDC0_DAT7 (MTK_PIN_NO(130) | 1) -#define PINMUX_GPIO130__FUNC_MRG_DO (MTK_PIN_NO(130) | 3) -#define PINMUX_GPIO130__FUNC_DBG_MON_A24 (MTK_PIN_NO(130) | 7) - -#define PINMUX_GPIO131__FUNC_GPIO131 (MTK_PIN_NO(131) | 0) -#define PINMUX_GPIO131__FUNC_MSDC0_DSL (MTK_PIN_NO(131) | 1) -#define PINMUX_GPIO131__FUNC_MRG_SYNC (MTK_PIN_NO(131) | 3) -#define PINMUX_GPIO131__FUNC_DBG_MON_A25 (MTK_PIN_NO(131) | 7) - -#define PINMUX_GPIO132__FUNC_GPIO132 (MTK_PIN_NO(132) | 0) -#define PINMUX_GPIO132__FUNC_MSDC0_DAT3 (MTK_PIN_NO(132) | 1) -#define PINMUX_GPIO132__FUNC_MRG_DI (MTK_PIN_NO(132) | 3) -#define PINMUX_GPIO132__FUNC_DBG_MON_A26 (MTK_PIN_NO(132) | 7) - -#define PINMUX_GPIO133__FUNC_GPIO133 (MTK_PIN_NO(133) | 0) -#define PINMUX_GPIO133__FUNC_MSDC0_RSTB (MTK_PIN_NO(133) | 1) -#define PINMUX_GPIO133__FUNC_AGPS_SYNC (MTK_PIN_NO(133) | 3) -#define PINMUX_GPIO133__FUNC_DBG_MON_A27 (MTK_PIN_NO(133) | 7) - -#define PINMUX_GPIO134__FUNC_GPIO134 (MTK_PIN_NO(134) | 0) -#define PINMUX_GPIO134__FUNC_RTC32K_CK (MTK_PIN_NO(134) | 1) - -#define PINMUX_GPIO135__FUNC_GPIO135 (MTK_PIN_NO(135) | 0) -#define PINMUX_GPIO135__FUNC_WATCHDOG (MTK_PIN_NO(135) | 1) - -#define PINMUX_GPIO136__FUNC_GPIO136 (MTK_PIN_NO(136) | 0) -#define PINMUX_GPIO136__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(136) | 1) -#define PINMUX_GPIO136__FUNC_AUD_CLK_MISO (MTK_PIN_NO(136) | 2) -#define PINMUX_GPIO136__FUNC_I2S1_MCK (MTK_PIN_NO(136) | 3) -#define PINMUX_GPIO136__FUNC_UFS_UNIPRO_SCL (MTK_PIN_NO(136) | 6) - -#define PINMUX_GPIO137__FUNC_GPIO137 (MTK_PIN_NO(137) | 0) -#define PINMUX_GPIO137__FUNC_AUD_SYNC_MOSI (MTK_PIN_NO(137) | 1) -#define PINMUX_GPIO137__FUNC_AUD_SYNC_MISO (MTK_PIN_NO(137) | 2) -#define PINMUX_GPIO137__FUNC_I2S1_BCK (MTK_PIN_NO(137) | 3) - -#define PINMUX_GPIO138__FUNC_GPIO138 (MTK_PIN_NO(138) | 0) -#define PINMUX_GPIO138__FUNC_AUD_DAT_MOSI0 (MTK_PIN_NO(138) | 1) -#define PINMUX_GPIO138__FUNC_AUD_DAT_MISO0 (MTK_PIN_NO(138) | 2) -#define PINMUX_GPIO138__FUNC_I2S1_LRCK (MTK_PIN_NO(138) | 3) -#define PINMUX_GPIO138__FUNC_DBG_MON_B24 (MTK_PIN_NO(138) | 7) - -#define PINMUX_GPIO139__FUNC_GPIO139 (MTK_PIN_NO(139) | 0) -#define PINMUX_GPIO139__FUNC_AUD_DAT_MOSI1 (MTK_PIN_NO(139) | 1) -#define PINMUX_GPIO139__FUNC_AUD_DAT_MISO1 (MTK_PIN_NO(139) | 2) -#define PINMUX_GPIO139__FUNC_I2S1_DO (MTK_PIN_NO(139) | 3) -#define PINMUX_GPIO139__FUNC_UFS_MPHY_SDA (MTK_PIN_NO(139) | 6) - -#define PINMUX_GPIO140__FUNC_GPIO140 (MTK_PIN_NO(140) | 0) -#define PINMUX_GPIO140__FUNC_AUD_CLK_MISO (MTK_PIN_NO(140) | 1) -#define PINMUX_GPIO140__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(140) | 2) -#define PINMUX_GPIO140__FUNC_I2S0_MCK (MTK_PIN_NO(140) | 3) -#define PINMUX_GPIO140__FUNC_UFS_UNIPRO_SDA (MTK_PIN_NO(140) | 6) - -#define PINMUX_GPIO141__FUNC_GPIO141 (MTK_PIN_NO(141) | 0) -#define PINMUX_GPIO141__FUNC_AUD_SYNC_MISO (MTK_PIN_NO(141) | 1) -#define PINMUX_GPIO141__FUNC_AUD_SYNC_MOSI (MTK_PIN_NO(141) | 2) -#define PINMUX_GPIO141__FUNC_I2S0_BCK (MTK_PIN_NO(141) | 3) - -#define PINMUX_GPIO142__FUNC_GPIO142 (MTK_PIN_NO(142) | 0) -#define PINMUX_GPIO142__FUNC_AUD_DAT_MISO0 (MTK_PIN_NO(142) | 1) -#define PINMUX_GPIO142__FUNC_AUD_DAT_MOSI0 (MTK_PIN_NO(142) | 2) -#define PINMUX_GPIO142__FUNC_I2S0_LRCK (MTK_PIN_NO(142) | 3) -#define PINMUX_GPIO142__FUNC_VOW_DAT_MISO (MTK_PIN_NO(142) | 4) -#define PINMUX_GPIO142__FUNC_DBG_MON_B25 (MTK_PIN_NO(142) | 7) - -#define PINMUX_GPIO143__FUNC_GPIO143 (MTK_PIN_NO(143) | 0) -#define PINMUX_GPIO143__FUNC_AUD_DAT_MISO1 (MTK_PIN_NO(143) | 1) -#define PINMUX_GPIO143__FUNC_AUD_DAT_MOSI1 (MTK_PIN_NO(143) | 2) -#define PINMUX_GPIO143__FUNC_I2S0_DI (MTK_PIN_NO(143) | 3) -#define PINMUX_GPIO143__FUNC_VOW_CLK_MISO (MTK_PIN_NO(143) | 4) -#define PINMUX_GPIO143__FUNC_UFS_MPHY_SCL (MTK_PIN_NO(143) | 6) -#define PINMUX_GPIO143__FUNC_DBG_MON_B26 (MTK_PIN_NO(143) | 7) - -#define PINMUX_GPIO144__FUNC_GPIO144 (MTK_PIN_NO(144) | 0) -#define PINMUX_GPIO144__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(144) | 1) -#define PINMUX_GPIO144__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(144) | 2) - -#define PINMUX_GPIO145__FUNC_GPIO145 (MTK_PIN_NO(145) | 0) -#define PINMUX_GPIO145__FUNC_PWRAP_SPI0_CSN (MTK_PIN_NO(145) | 1) - -#define PINMUX_GPIO146__FUNC_GPIO146 (MTK_PIN_NO(146) | 0) -#define PINMUX_GPIO146__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(146) | 1) -#define PINMUX_GPIO146__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(146) | 2) - -#define PINMUX_GPIO147__FUNC_GPIO147 (MTK_PIN_NO(147) | 0) -#define PINMUX_GPIO147__FUNC_PWRAP_SPI0_CK (MTK_PIN_NO(147) | 1) - -#define PINMUX_GPIO148__FUNC_GPIO148 (MTK_PIN_NO(148) | 0) -#define PINMUX_GPIO148__FUNC_SRCLKENA0 (MTK_PIN_NO(148) | 1) - -#define PINMUX_GPIO149__FUNC_GPIO149 (MTK_PIN_NO(149) | 0) -#define PINMUX_GPIO149__FUNC_SRCLKENA1 (MTK_PIN_NO(149) | 1) - -#define PINMUX_GPIO150__FUNC_GPIO150 (MTK_PIN_NO(150) | 0) -#define PINMUX_GPIO150__FUNC_PWM_A (MTK_PIN_NO(150) | 1) -#define PINMUX_GPIO150__FUNC_CMFLASH (MTK_PIN_NO(150) | 2) -#define PINMUX_GPIO150__FUNC_CLKM0 (MTK_PIN_NO(150) | 3) -#define PINMUX_GPIO150__FUNC_DBG_MON_B30 (MTK_PIN_NO(150) | 7) - -#define PINMUX_GPIO151__FUNC_GPIO151 (MTK_PIN_NO(151) | 0) -#define PINMUX_GPIO151__FUNC_PWM_B (MTK_PIN_NO(151) | 1) -#define PINMUX_GPIO151__FUNC_CMVREF0 (MTK_PIN_NO(151) | 2) -#define PINMUX_GPIO151__FUNC_CLKM1 (MTK_PIN_NO(151) | 3) -#define PINMUX_GPIO151__FUNC_DBG_MON_B20 (MTK_PIN_NO(151) | 7) - -#define PINMUX_GPIO152__FUNC_GPIO152 (MTK_PIN_NO(152) | 0) -#define PINMUX_GPIO152__FUNC_PWM_C (MTK_PIN_NO(152) | 1) -#define PINMUX_GPIO152__FUNC_CMFLASH (MTK_PIN_NO(152) | 2) -#define PINMUX_GPIO152__FUNC_CLKM2 (MTK_PIN_NO(152) | 3) -#define PINMUX_GPIO152__FUNC_DBG_MON_B21 (MTK_PIN_NO(152) | 7) - -#define PINMUX_GPIO153__FUNC_GPIO153 (MTK_PIN_NO(153) | 0) -#define PINMUX_GPIO153__FUNC_PWM_A (MTK_PIN_NO(153) | 1) -#define PINMUX_GPIO153__FUNC_CMVREF0 (MTK_PIN_NO(153) | 2) -#define PINMUX_GPIO153__FUNC_CLKM3 (MTK_PIN_NO(153) | 3) -#define PINMUX_GPIO153__FUNC_DBG_MON_B22 (MTK_PIN_NO(153) | 7) - -#define PINMUX_GPIO154__FUNC_GPIO154 (MTK_PIN_NO(154) | 0) -#define PINMUX_GPIO154__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(154) | 1) -#define PINMUX_GPIO154__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(154) | 2) -#define PINMUX_GPIO154__FUNC_DBG_MON_B18 (MTK_PIN_NO(154) | 7) - -#define PINMUX_GPIO155__FUNC_GPIO155 (MTK_PIN_NO(155) | 0) -#define PINMUX_GPIO155__FUNC_ANT_SEL0 (MTK_PIN_NO(155) | 1) -#define PINMUX_GPIO155__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(155) | 2) -#define PINMUX_GPIO155__FUNC_CMVREF1 (MTK_PIN_NO(155) | 3) -#define PINMUX_GPIO155__FUNC_SCP_JTAG_TDI (MTK_PIN_NO(155) | 7) - -#define PINMUX_GPIO156__FUNC_GPIO156 (MTK_PIN_NO(156) | 0) -#define PINMUX_GPIO156__FUNC_ANT_SEL1 (MTK_PIN_NO(156) | 1) -#define PINMUX_GPIO156__FUNC_SRCLKENAI0 (MTK_PIN_NO(156) | 2) -#define PINMUX_GPIO156__FUNC_SCL6 (MTK_PIN_NO(156) | 3) -#define PINMUX_GPIO156__FUNC_KPCOL2 (MTK_PIN_NO(156) | 4) -#define PINMUX_GPIO156__FUNC_IDDIG (MTK_PIN_NO(156) | 5) -#define PINMUX_GPIO156__FUNC_SCP_JTAG_TCK (MTK_PIN_NO(156) | 7) - -#define PINMUX_GPIO157__FUNC_GPIO157 (MTK_PIN_NO(157) | 0) -#define PINMUX_GPIO157__FUNC_ANT_SEL2 (MTK_PIN_NO(157) | 1) -#define PINMUX_GPIO157__FUNC_SRCLKENAI1 (MTK_PIN_NO(157) | 2) -#define PINMUX_GPIO157__FUNC_SDA6 (MTK_PIN_NO(157) | 3) -#define PINMUX_GPIO157__FUNC_KPROW2 (MTK_PIN_NO(157) | 4) -#define PINMUX_GPIO157__FUNC_USB_DRVVBUS (MTK_PIN_NO(157) | 5) -#define PINMUX_GPIO157__FUNC_SCP_JTAG_TRSTN (MTK_PIN_NO(157) | 7) - -#define PINMUX_GPIO158__FUNC_GPIO158 (MTK_PIN_NO(158) | 0) -#define PINMUX_GPIO158__FUNC_ANT_SEL3 (MTK_PIN_NO(158) | 1) - -#define PINMUX_GPIO159__FUNC_GPIO159 (MTK_PIN_NO(159) | 0) -#define PINMUX_GPIO159__FUNC_ANT_SEL4 (MTK_PIN_NO(159) | 1) - -#define PINMUX_GPIO160__FUNC_GPIO160 (MTK_PIN_NO(160) | 0) -#define PINMUX_GPIO160__FUNC_ANT_SEL5 (MTK_PIN_NO(160) | 1) - -#define PINMUX_GPIO161__FUNC_GPIO161 (MTK_PIN_NO(161) | 0) -#define PINMUX_GPIO161__FUNC_SPI1_A_MI (MTK_PIN_NO(161) | 1) -#define PINMUX_GPIO161__FUNC_SCP_SPI1_MI (MTK_PIN_NO(161) | 2) -#define PINMUX_GPIO161__FUNC_IDDIG (MTK_PIN_NO(161) | 3) -#define PINMUX_GPIO161__FUNC_ANT_SEL6 (MTK_PIN_NO(161) | 4) -#define PINMUX_GPIO161__FUNC_KPCOL2 (MTK_PIN_NO(161) | 5) -#define PINMUX_GPIO161__FUNC_PTA_RXD (MTK_PIN_NO(161) | 6) -#define PINMUX_GPIO161__FUNC_DBG_MON_B19 (MTK_PIN_NO(161) | 7) - -#define PINMUX_GPIO162__FUNC_GPIO162 (MTK_PIN_NO(162) | 0) -#define PINMUX_GPIO162__FUNC_SPI1_A_CSB (MTK_PIN_NO(162) | 1) -#define PINMUX_GPIO162__FUNC_SCP_SPI1_CS (MTK_PIN_NO(162) | 2) -#define PINMUX_GPIO162__FUNC_USB_DRVVBUS (MTK_PIN_NO(162) | 3) -#define PINMUX_GPIO162__FUNC_ANT_SEL5 (MTK_PIN_NO(162) | 4) -#define PINMUX_GPIO162__FUNC_KPROW2 (MTK_PIN_NO(162) | 5) -#define PINMUX_GPIO162__FUNC_PTA_TXD (MTK_PIN_NO(162) | 6) - -#define PINMUX_GPIO163__FUNC_GPIO163 (MTK_PIN_NO(163) | 0) -#define PINMUX_GPIO163__FUNC_SPI1_A_MO (MTK_PIN_NO(163) | 1) -#define PINMUX_GPIO163__FUNC_SCP_SPI1_MO (MTK_PIN_NO(163) | 2) -#define PINMUX_GPIO163__FUNC_SDA1 (MTK_PIN_NO(163) | 3) -#define PINMUX_GPIO163__FUNC_ANT_SEL4 (MTK_PIN_NO(163) | 4) -#define PINMUX_GPIO163__FUNC_CMMCLK2 (MTK_PIN_NO(163) | 5) -#define PINMUX_GPIO163__FUNC_DMIC_CLK (MTK_PIN_NO(163) | 6) - -#define PINMUX_GPIO164__FUNC_GPIO164 (MTK_PIN_NO(164) | 0) -#define PINMUX_GPIO164__FUNC_SPI1_A_CLK (MTK_PIN_NO(164) | 1) -#define PINMUX_GPIO164__FUNC_SCP_SPI1_CK (MTK_PIN_NO(164) | 2) -#define PINMUX_GPIO164__FUNC_SCL1 (MTK_PIN_NO(164) | 3) -#define PINMUX_GPIO164__FUNC_ANT_SEL3 (MTK_PIN_NO(164) | 4) -#define PINMUX_GPIO164__FUNC_CMMCLK3 (MTK_PIN_NO(164) | 5) -#define PINMUX_GPIO164__FUNC_DMIC_DAT (MTK_PIN_NO(164) | 6) - -#define PINMUX_GPIO165__FUNC_GPIO165 (MTK_PIN_NO(165) | 0) -#define PINMUX_GPIO165__FUNC_PWM_B (MTK_PIN_NO(165) | 1) -#define PINMUX_GPIO165__FUNC_CMMCLK2 (MTK_PIN_NO(165) | 2) -#define PINMUX_GPIO165__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(165) | 3) -#define PINMUX_GPIO165__FUNC_TDM_MCK_2ND (MTK_PIN_NO(165) | 6) -#define PINMUX_GPIO165__FUNC_SCP_JTAG_TDO (MTK_PIN_NO(165) | 7) - -#define PINMUX_GPIO166__FUNC_GPIO166 (MTK_PIN_NO(166) | 0) -#define PINMUX_GPIO166__FUNC_ANT_SEL6 (MTK_PIN_NO(166) | 1) - -#define PINMUX_GPIO167__FUNC_GPIO167 (MTK_PIN_NO(167) | 0) -#define PINMUX_GPIO167__FUNC_RFIC0_BSI_EN (MTK_PIN_NO(167) | 1) -#define PINMUX_GPIO167__FUNC_SPM_BSI_EN (MTK_PIN_NO(167) | 2) - -#define PINMUX_GPIO168__FUNC_GPIO168 (MTK_PIN_NO(168) | 0) -#define PINMUX_GPIO168__FUNC_RFIC0_BSI_CK (MTK_PIN_NO(168) | 1) -#define PINMUX_GPIO168__FUNC_SPM_BSI_CK (MTK_PIN_NO(168) | 2) - -#define PINMUX_GPIO169__FUNC_GPIO169 (MTK_PIN_NO(169) | 0) -#define PINMUX_GPIO169__FUNC_PWM_C (MTK_PIN_NO(169) | 1) -#define PINMUX_GPIO169__FUNC_CMMCLK3 (MTK_PIN_NO(169) | 2) -#define PINMUX_GPIO169__FUNC_CMVREF1 (MTK_PIN_NO(169) | 3) -#define PINMUX_GPIO169__FUNC_ANT_SEL7 (MTK_PIN_NO(169) | 4) -#define PINMUX_GPIO169__FUNC_AGPS_SYNC (MTK_PIN_NO(169) | 5) -#define PINMUX_GPIO169__FUNC_TDM_BCK_2ND (MTK_PIN_NO(169) | 6) -#define PINMUX_GPIO169__FUNC_SCP_JTAG_TMS (MTK_PIN_NO(169) | 7) - -#define PINMUX_GPIO170__FUNC_GPIO170 (MTK_PIN_NO(170) | 0) -#define PINMUX_GPIO170__FUNC_I2S1_BCK (MTK_PIN_NO(170) | 1) -#define PINMUX_GPIO170__FUNC_I2S3_BCK (MTK_PIN_NO(170) | 2) -#define PINMUX_GPIO170__FUNC_SCL7 (MTK_PIN_NO(170) | 3) -#define PINMUX_GPIO170__FUNC_I2S5_BCK (MTK_PIN_NO(170) | 4) -#define PINMUX_GPIO170__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(170) | 5) -#define PINMUX_GPIO170__FUNC_TDM_LRCK_2ND (MTK_PIN_NO(170) | 6) -#define PINMUX_GPIO170__FUNC_ANT_SEL3 (MTK_PIN_NO(170) | 7) - -#define PINMUX_GPIO171__FUNC_GPIO171 (MTK_PIN_NO(171) | 0) -#define PINMUX_GPIO171__FUNC_I2S1_LRCK (MTK_PIN_NO(171) | 1) -#define PINMUX_GPIO171__FUNC_I2S3_LRCK (MTK_PIN_NO(171) | 2) -#define PINMUX_GPIO171__FUNC_SDA7 (MTK_PIN_NO(171) | 3) -#define PINMUX_GPIO171__FUNC_I2S5_LRCK (MTK_PIN_NO(171) | 4) -#define PINMUX_GPIO171__FUNC_URXD1 (MTK_PIN_NO(171) | 5) -#define PINMUX_GPIO171__FUNC_TDM_DATA0_2ND (MTK_PIN_NO(171) | 6) -#define PINMUX_GPIO171__FUNC_ANT_SEL4 (MTK_PIN_NO(171) | 7) - -#define PINMUX_GPIO172__FUNC_GPIO172 (MTK_PIN_NO(172) | 0) -#define PINMUX_GPIO172__FUNC_I2S1_DO (MTK_PIN_NO(172) | 1) -#define PINMUX_GPIO172__FUNC_I2S3_DO (MTK_PIN_NO(172) | 2) -#define PINMUX_GPIO172__FUNC_SCL8 (MTK_PIN_NO(172) | 3) -#define PINMUX_GPIO172__FUNC_I2S5_DO (MTK_PIN_NO(172) | 4) -#define PINMUX_GPIO172__FUNC_UTXD1 (MTK_PIN_NO(172) | 5) -#define PINMUX_GPIO172__FUNC_TDM_DATA1_2ND (MTK_PIN_NO(172) | 6) -#define PINMUX_GPIO172__FUNC_ANT_SEL5 (MTK_PIN_NO(172) | 7) - -#define PINMUX_GPIO173__FUNC_GPIO173 (MTK_PIN_NO(173) | 0) -#define PINMUX_GPIO173__FUNC_I2S1_MCK (MTK_PIN_NO(173) | 1) -#define PINMUX_GPIO173__FUNC_I2S3_MCK (MTK_PIN_NO(173) | 2) -#define PINMUX_GPIO173__FUNC_SDA8 (MTK_PIN_NO(173) | 3) -#define PINMUX_GPIO173__FUNC_I2S5_MCK (MTK_PIN_NO(173) | 4) -#define PINMUX_GPIO173__FUNC_UCTS0 (MTK_PIN_NO(173) | 5) -#define PINMUX_GPIO173__FUNC_TDM_DATA2_2ND (MTK_PIN_NO(173) | 6) -#define PINMUX_GPIO173__FUNC_ANT_SEL6 (MTK_PIN_NO(173) | 7) - -#define PINMUX_GPIO174__FUNC_GPIO174 (MTK_PIN_NO(174) | 0) -#define PINMUX_GPIO174__FUNC_I2S2_DI (MTK_PIN_NO(174) | 1) -#define PINMUX_GPIO174__FUNC_I2S0_DI (MTK_PIN_NO(174) | 2) -#define PINMUX_GPIO174__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(174) | 3) -#define PINMUX_GPIO174__FUNC_I2S2_DI2 (MTK_PIN_NO(174) | 4) -#define PINMUX_GPIO174__FUNC_URTS0 (MTK_PIN_NO(174) | 5) -#define PINMUX_GPIO174__FUNC_TDM_DATA3_2ND (MTK_PIN_NO(174) | 6) -#define PINMUX_GPIO174__FUNC_ANT_SEL7 (MTK_PIN_NO(174) | 7) - -#define PINMUX_GPIO175__FUNC_GPIO175 (MTK_PIN_NO(175) | 0) -#define PINMUX_GPIO175__FUNC_ANT_SEL7 (MTK_PIN_NO(175) | 1) - -#define PINMUX_GPIO176__FUNC_GPIO176 (MTK_PIN_NO(176) | 0) - -#define PINMUX_GPIO177__FUNC_GPIO177 (MTK_PIN_NO(177) | 0) - -#define PINMUX_GPIO178__FUNC_GPIO178 (MTK_PIN_NO(178) | 0) - -#define PINMUX_GPIO179__FUNC_GPIO179 (MTK_PIN_NO(179) | 0) - -#endif /* __MT8183-PINFUNC_H */ diff --git a/sys/gnu/dts/arm64/mediatek/mt8183.dtsi b/sys/gnu/dts/arm64/mediatek/mt8183.dtsi deleted file mode 100644 index 124f9d3e09f..00000000000 --- a/sys/gnu/dts/arm64/mediatek/mt8183.dtsi +++ /dev/null @@ -1,656 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (c) 2018 MediaTek Inc. - * Author: Ben Ho - * Erin Lo - */ - -#include -#include -#include -#include -#include "mt8183-pinfunc.h" - -/ { - compatible = "mediatek,mt8183"; - interrupt-parent = <&sysirq>; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - i2c6 = &i2c6; - i2c7 = &i2c7; - i2c8 = &i2c8; - i2c9 = &i2c9; - i2c10 = &i2c10; - i2c11 = &i2c11; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu-map { - cluster0 { - core0 { - cpu = <&cpu0>; - }; - core1 { - cpu = <&cpu1>; - }; - core2 { - cpu = <&cpu2>; - }; - core3 { - cpu = <&cpu3>; - }; - }; - - cluster1 { - core0 { - cpu = <&cpu4>; - }; - core1 { - cpu = <&cpu5>; - }; - core2 { - cpu = <&cpu6>; - }; - core3 { - cpu = <&cpu7>; - }; - }; - }; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x000>; - enable-method = "psci"; - capacity-dmips-mhz = <741>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x001>; - enable-method = "psci"; - capacity-dmips-mhz = <741>; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x002>; - enable-method = "psci"; - capacity-dmips-mhz = <741>; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x003>; - enable-method = "psci"; - capacity-dmips-mhz = <741>; - }; - - cpu4: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a73"; - reg = <0x100>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - }; - - cpu5: cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a73"; - reg = <0x101>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - }; - - cpu6: cpu@102 { - device_type = "cpu"; - compatible = "arm,cortex-a73"; - reg = <0x102>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - }; - - cpu7: cpu@103 { - device_type = "cpu"; - compatible = "arm,cortex-a73"; - reg = <0x103>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - }; - }; - - pmu-a53 { - compatible = "arm,cortex-a53-pmu"; - interrupt-parent = <&gic>; - interrupts = ; - }; - - pmu-a73 { - compatible = "arm,cortex-a73-pmu"; - interrupt-parent = <&gic>; - interrupts = ; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - clk26m: oscillator { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <26000000>; - clock-output-names = "clk26m"; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupt-parent = <&gic>; - interrupts = , - , - , - ; - }; - - soc { - #address-cells = <2>; - #size-cells = <2>; - compatible = "simple-bus"; - ranges; - - soc_data: soc_data@8000000 { - compatible = "mediatek,mt8183-efuse", - "mediatek,efuse"; - reg = <0 0x08000000 0 0x0010>; - #address-cells = <1>; - #size-cells = <1>; - status = "disabled"; - }; - - gic: interrupt-controller@c000000 { - compatible = "arm,gic-v3"; - #interrupt-cells = <4>; - interrupt-parent = <&gic>; - interrupt-controller; - reg = <0 0x0c000000 0 0x40000>, /* GICD */ - <0 0x0c100000 0 0x200000>, /* GICR */ - <0 0x0c400000 0 0x2000>, /* GICC */ - <0 0x0c410000 0 0x1000>, /* GICH */ - <0 0x0c420000 0 0x2000>; /* GICV */ - - interrupts = ; - ppi-partitions { - ppi_cluster0: interrupt-partition-0 { - affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; - }; - ppi_cluster1: interrupt-partition-1 { - affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; - }; - }; - }; - - mcucfg: syscon@c530000 { - compatible = "mediatek,mt8183-mcucfg", "syscon"; - reg = <0 0x0c530000 0 0x1000>; - #clock-cells = <1>; - }; - - sysirq: interrupt-controller@c530a80 { - compatible = "mediatek,mt8183-sysirq", - "mediatek,mt6577-sysirq"; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - reg = <0 0x0c530a80 0 0x50>; - }; - - topckgen: syscon@10000000 { - compatible = "mediatek,mt8183-topckgen", "syscon"; - reg = <0 0x10000000 0 0x1000>; - #clock-cells = <1>; - }; - - infracfg: syscon@10001000 { - compatible = "mediatek,mt8183-infracfg", "syscon"; - reg = <0 0x10001000 0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - pio: pinctrl@10005000 { - compatible = "mediatek,mt8183-pinctrl"; - reg = <0 0x10005000 0 0x1000>, - <0 0x11f20000 0 0x1000>, - <0 0x11e80000 0 0x1000>, - <0 0x11e70000 0 0x1000>, - <0 0x11e90000 0 0x1000>, - <0 0x11d30000 0 0x1000>, - <0 0x11d20000 0 0x1000>, - <0 0x11c50000 0 0x1000>, - <0 0x11f30000 0 0x1000>, - <0 0x1000b000 0 0x1000>; - reg-names = "iocfg0", "iocfg1", "iocfg2", - "iocfg3", "iocfg4", "iocfg5", - "iocfg6", "iocfg7", "iocfg8", - "eint"; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pio 0 0 192>; - interrupt-controller; - interrupts = ; - #interrupt-cells = <2>; - }; - - apmixedsys: syscon@1000c000 { - compatible = "mediatek,mt8183-apmixedsys", "syscon"; - reg = <0 0x1000c000 0 0x1000>; - #clock-cells = <1>; - }; - - pwrap: pwrap@1000d000 { - compatible = "mediatek,mt8183-pwrap"; - reg = <0 0x1000d000 0 0x1000>; - reg-names = "pwrap"; - interrupts = ; - clocks = <&topckgen CLK_TOP_MUX_PMICSPI>, - <&infracfg CLK_INFRA_PMIC_AP>; - clock-names = "spi", "wrap"; - }; - - systimer: timer@10017000 { - compatible = "mediatek,mt8183-timer", - "mediatek,mt6765-timer"; - reg = <0 0x10017000 0 0x1000>; - interrupts = ; - clocks = <&topckgen CLK_TOP_CLK13M>; - clock-names = "clk13m"; - }; - - gce: mailbox@10238000 { - compatible = "mediatek,mt8183-gce"; - reg = <0 0x10238000 0 0x4000>; - interrupts = ; - #mbox-cells = <3>; - clocks = <&infracfg CLK_INFRA_GCE>; - clock-names = "gce"; - }; - - auxadc: auxadc@11001000 { - compatible = "mediatek,mt8183-auxadc", - "mediatek,mt8173-auxadc"; - reg = <0 0x11001000 0 0x1000>; - clocks = <&infracfg CLK_INFRA_AUXADC>; - clock-names = "main"; - #io-channel-cells = <1>; - status = "disabled"; - }; - - uart0: serial@11002000 { - compatible = "mediatek,mt8183-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11002000 0 0x1000>; - interrupts = ; - clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>; - clock-names = "baud", "bus"; - status = "disabled"; - }; - - uart1: serial@11003000 { - compatible = "mediatek,mt8183-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11003000 0 0x1000>; - interrupts = ; - clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>; - clock-names = "baud", "bus"; - status = "disabled"; - }; - - uart2: serial@11004000 { - compatible = "mediatek,mt8183-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11004000 0 0x1000>; - interrupts = ; - clocks = <&clk26m>, <&infracfg CLK_INFRA_UART2>; - clock-names = "baud", "bus"; - status = "disabled"; - }; - - i2c6: i2c@11005000 { - compatible = "mediatek,mt8183-i2c"; - reg = <0 0x11005000 0 0x1000>, - <0 0x11000600 0 0x80>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_I2C6>, - <&infracfg CLK_INFRA_AP_DMA>; - clock-names = "main", "dma"; - clock-div = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c0: i2c@11007000 { - compatible = "mediatek,mt8183-i2c"; - reg = <0 0x11007000 0 0x1000>, - <0 0x11000080 0 0x80>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_I2C0>, - <&infracfg CLK_INFRA_AP_DMA>; - clock-names = "main", "dma"; - clock-div = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c4: i2c@11008000 { - compatible = "mediatek,mt8183-i2c"; - reg = <0 0x11008000 0 0x1000>, - <0 0x11000100 0 0x80>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_I2C1>, - <&infracfg CLK_INFRA_AP_DMA>, - <&infracfg CLK_INFRA_I2C1_ARBITER>; - clock-names = "main", "dma","arb"; - clock-div = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@11009000 { - compatible = "mediatek,mt8183-i2c"; - reg = <0 0x11009000 0 0x1000>, - <0 0x11000280 0 0x80>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_I2C2>, - <&infracfg CLK_INFRA_AP_DMA>, - <&infracfg CLK_INFRA_I2C2_ARBITER>; - clock-names = "main", "dma", "arb"; - clock-div = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi0: spi@1100a000 { - compatible = "mediatek,mt8183-spi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0 0x1100a000 0 0x1000>; - interrupts = ; - clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, - <&topckgen CLK_TOP_MUX_SPI>, - <&infracfg CLK_INFRA_SPI0>; - clock-names = "parent-clk", "sel-clk", "spi-clk"; - status = "disabled"; - }; - - i2c3: i2c@1100f000 { - compatible = "mediatek,mt8183-i2c"; - reg = <0 0x1100f000 0 0x1000>, - <0 0x11000400 0 0x80>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_I2C3>, - <&infracfg CLK_INFRA_AP_DMA>; - clock-names = "main", "dma"; - clock-div = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi1: spi@11010000 { - compatible = "mediatek,mt8183-spi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0 0x11010000 0 0x1000>; - interrupts = ; - clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, - <&topckgen CLK_TOP_MUX_SPI>, - <&infracfg CLK_INFRA_SPI1>; - clock-names = "parent-clk", "sel-clk", "spi-clk"; - status = "disabled"; - }; - - i2c1: i2c@11011000 { - compatible = "mediatek,mt8183-i2c"; - reg = <0 0x11011000 0 0x1000>, - <0 0x11000480 0 0x80>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_I2C4>, - <&infracfg CLK_INFRA_AP_DMA>; - clock-names = "main", "dma"; - clock-div = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi2: spi@11012000 { - compatible = "mediatek,mt8183-spi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0 0x11012000 0 0x1000>; - interrupts = ; - clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, - <&topckgen CLK_TOP_MUX_SPI>, - <&infracfg CLK_INFRA_SPI2>; - clock-names = "parent-clk", "sel-clk", "spi-clk"; - status = "disabled"; - }; - - spi3: spi@11013000 { - compatible = "mediatek,mt8183-spi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0 0x11013000 0 0x1000>; - interrupts = ; - clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, - <&topckgen CLK_TOP_MUX_SPI>, - <&infracfg CLK_INFRA_SPI3>; - clock-names = "parent-clk", "sel-clk", "spi-clk"; - status = "disabled"; - }; - - i2c9: i2c@11014000 { - compatible = "mediatek,mt8183-i2c"; - reg = <0 0x11014000 0 0x1000>, - <0 0x11000180 0 0x80>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_I2C1_IMM>, - <&infracfg CLK_INFRA_AP_DMA>, - <&infracfg CLK_INFRA_I2C1_ARBITER>; - clock-names = "main", "dma", "arb"; - clock-div = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c10: i2c@11015000 { - compatible = "mediatek,mt8183-i2c"; - reg = <0 0x11015000 0 0x1000>, - <0 0x11000300 0 0x80>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_I2C2_IMM>, - <&infracfg CLK_INFRA_AP_DMA>, - <&infracfg CLK_INFRA_I2C2_ARBITER>; - clock-names = "main", "dma", "arb"; - clock-div = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c5: i2c@11016000 { - compatible = "mediatek,mt8183-i2c"; - reg = <0 0x11016000 0 0x1000>, - <0 0x11000500 0 0x80>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_I2C5>, - <&infracfg CLK_INFRA_AP_DMA>, - <&infracfg CLK_INFRA_I2C5_ARBITER>; - clock-names = "main", "dma", "arb"; - clock-div = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c11: i2c@11017000 { - compatible = "mediatek,mt8183-i2c"; - reg = <0 0x11017000 0 0x1000>, - <0 0x11000580 0 0x80>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_I2C5_IMM>, - <&infracfg CLK_INFRA_AP_DMA>, - <&infracfg CLK_INFRA_I2C5_ARBITER>; - clock-names = "main", "dma", "arb"; - clock-div = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi4: spi@11018000 { - compatible = "mediatek,mt8183-spi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0 0x11018000 0 0x1000>; - interrupts = ; - clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, - <&topckgen CLK_TOP_MUX_SPI>, - <&infracfg CLK_INFRA_SPI4>; - clock-names = "parent-clk", "sel-clk", "spi-clk"; - status = "disabled"; - }; - - spi5: spi@11019000 { - compatible = "mediatek,mt8183-spi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0 0x11019000 0 0x1000>; - interrupts = ; - clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, - <&topckgen CLK_TOP_MUX_SPI>, - <&infracfg CLK_INFRA_SPI5>; - clock-names = "parent-clk", "sel-clk", "spi-clk"; - status = "disabled"; - }; - - i2c7: i2c@1101a000 { - compatible = "mediatek,mt8183-i2c"; - reg = <0 0x1101a000 0 0x1000>, - <0 0x11000680 0 0x80>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_I2C7>, - <&infracfg CLK_INFRA_AP_DMA>; - clock-names = "main", "dma"; - clock-div = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c8: i2c@1101b000 { - compatible = "mediatek,mt8183-i2c"; - reg = <0 0x1101b000 0 0x1000>, - <0 0x11000700 0 0x80>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_I2C8>, - <&infracfg CLK_INFRA_AP_DMA>; - clock-names = "main", "dma"; - clock-div = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - audiosys: syscon@11220000 { - compatible = "mediatek,mt8183-audiosys", "syscon"; - reg = <0 0x11220000 0 0x1000>; - #clock-cells = <1>; - }; - - efuse: efuse@11f10000 { - compatible = "mediatek,mt8183-efuse", - "mediatek,efuse"; - reg = <0 0x11f10000 0 0x1000>; - }; - - mfgcfg: syscon@13000000 { - compatible = "mediatek,mt8183-mfgcfg", "syscon"; - reg = <0 0x13000000 0 0x1000>; - #clock-cells = <1>; - }; - - mmsys: syscon@14000000 { - compatible = "mediatek,mt8183-mmsys", "syscon"; - reg = <0 0x14000000 0 0x1000>; - #clock-cells = <1>; - }; - - imgsys: syscon@15020000 { - compatible = "mediatek,mt8183-imgsys", "syscon"; - reg = <0 0x15020000 0 0x1000>; - #clock-cells = <1>; - }; - - vdecsys: syscon@16000000 { - compatible = "mediatek,mt8183-vdecsys", "syscon"; - reg = <0 0x16000000 0 0x1000>; - #clock-cells = <1>; - }; - - vencsys: syscon@17000000 { - compatible = "mediatek,mt8183-vencsys", "syscon"; - reg = <0 0x17000000 0 0x1000>; - #clock-cells = <1>; - }; - - ipu_conn: syscon@19000000 { - compatible = "mediatek,mt8183-ipu_conn", "syscon"; - reg = <0 0x19000000 0 0x1000>; - #clock-cells = <1>; - }; - - ipu_adl: syscon@19010000 { - compatible = "mediatek,mt8183-ipu_adl", "syscon"; - reg = <0 0x19010000 0 0x1000>; - #clock-cells = <1>; - }; - - ipu_core0: syscon@19180000 { - compatible = "mediatek,mt8183-ipu_core0", "syscon"; - reg = <0 0x19180000 0 0x1000>; - #clock-cells = <1>; - }; - - ipu_core1: syscon@19280000 { - compatible = "mediatek,mt8183-ipu_core1", "syscon"; - reg = <0 0x19280000 0 0x1000>; - #clock-cells = <1>; - }; - - camsys: syscon@1a000000 { - compatible = "mediatek,mt8183-camsys", "syscon"; - reg = <0 0x1a000000 0 0x1000>; - #clock-cells = <1>; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/nvidia/tegra132-norrin.dts b/sys/gnu/dts/arm64/nvidia/tegra132-norrin.dts deleted file mode 100644 index a0385a386a3..00000000000 --- a/sys/gnu/dts/arm64/nvidia/tegra132-norrin.dts +++ /dev/null @@ -1,1136 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include -#include "tegra132.dtsi" - -/ { - model = "NVIDIA Tegra132 Norrin"; - compatible = "nvidia,norrin", "nvidia,tegra132", "nvidia,tegra124"; - - aliases { - rtc0 = "/i2c@7000d000/as3722@40"; - rtc1 = "/rtc@7000e000"; - serial0 = &uarta; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - device_type = "memory"; - reg = <0x0 0x80000000 0x0 0x80000000>; - }; - - host1x@50000000 { - hdmi@54280000 { - status = "disabled"; - - vdd-supply = <&vdd_3v3_hdmi>; - pll-supply = <&vdd_hdmi_pll>; - hdmi-supply = <&vdd_5v0_hdmi>; - - nvidia,ddc-i2c-bus = <&hdmi_ddc>; - nvidia,hpd-gpio = - <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; - }; - - sor@54540000 { - status = "okay"; - - nvidia,dpaux = <&dpaux>; - nvidia,panel = <&panel>; - }; - - dpaux: dpaux@545c0000 { - vdd-supply = <&vdd_3v3_panel>; - status = "okay"; - }; - }; - - gpu@57000000 { - status = "okay"; - - vdd-supply = <&vdd_gpu>; - }; - - pinmux@70000868 { - pinctrl-names = "default"; - pinctrl-0 = <&pinmux_default>; - - pinmux_default: pinmux@0 { - dap_mclk1_pw4 { - nvidia,pins = "dap_mclk1_pw4"; - nvidia,function = "extperiph1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap2_din_pa4 { - nvidia,pins = "dap2_din_pa4"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap2_dout_pa5 { - nvidia,pins = "dap2_dout_pa5", - "dap2_fs_pa2", - "dap2_sclk_pa3"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3_dout_pp2 { - nvidia,pins = "dap3_dout_pp2"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dvfs_pwm_px0 { - nvidia,pins = "dvfs_pwm_px0", - "dvfs_clk_px2"; - nvidia,function = "cldvfs"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_clk_py0 { - nvidia,pins = "ulpi_clk_py0", - "ulpi_nxt_py2", - "ulpi_stp_py3"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_dir_py1 { - nvidia,pins = "ulpi_dir_py1"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - cam_i2c_scl_pbb1 { - nvidia,pins = "cam_i2c_scl_pbb1", - "cam_i2c_sda_pbb2"; - nvidia,function = "i2c3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,lock = ; - nvidia,open-drain = ; - }; - gen2_i2c_scl_pt5 { - nvidia,pins = "gen2_i2c_scl_pt5", - "gen2_i2c_sda_pt6"; - nvidia,function = "i2c2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,lock = ; - nvidia,open-drain = ; - }; - pj7 { - nvidia,pins = "pj7"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - spdif_in_pk6 { - nvidia,pins = "spdif_in_pk6"; - nvidia,function = "spdif"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pk7 { - nvidia,pins = "pk7"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg4 { - nvidia,pins = "pg4", - "pg5", - "pg6", - "pi3"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg7 { - nvidia,pins = "pg7"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph1 { - nvidia,pins = "ph1"; - nvidia,function = "pwm1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pk0 { - nvidia,pins = "pk0", - "kb_row15_ps7", - "clk_32k_out_pa0"; - nvidia,function = "soc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_clk_pz0 { - nvidia,pins = "sdmmc1_clk_pz0"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_cmd_pz1 { - nvidia,pins = "sdmmc1_cmd_pz1", - "sdmmc1_dat0_py7", - "sdmmc1_dat1_py6", - "sdmmc1_dat2_py5", - "sdmmc1_dat3_py4"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_clk_pa6 { - nvidia,pins = "sdmmc3_clk_pa6"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_cmd_pa7 { - nvidia,pins = "sdmmc3_cmd_pa7", - "sdmmc3_dat0_pb7", - "sdmmc3_dat1_pb6", - "sdmmc3_dat2_pb5", - "sdmmc3_dat3_pb4", - "kb_col4_pq4", - "sdmmc3_clk_lb_out_pee4", - "sdmmc3_clk_lb_in_pee5", - "sdmmc3_cd_n_pv2"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_clk_pcc4 { - nvidia,pins = "sdmmc4_clk_pcc4"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_cmd_pt7 { - nvidia,pins = "sdmmc4_cmd_pt7", - "sdmmc4_dat0_paa0", - "sdmmc4_dat1_paa1", - "sdmmc4_dat2_paa2", - "sdmmc4_dat3_paa3", - "sdmmc4_dat4_paa4", - "sdmmc4_dat5_paa5", - "sdmmc4_dat6_paa6", - "sdmmc4_dat7_paa7"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - mic_det_l { - nvidia,pins = "kb_row7_pr7"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row10_ps2 { - nvidia,pins = "kb_row10_ps2"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row9_ps1 { - nvidia,pins = "kb_row9_ps1"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pwr_i2c_scl_pz6 { - nvidia,pins = "pwr_i2c_scl_pz6", - "pwr_i2c_sda_pz7"; - nvidia,function = "i2cpwr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,lock = ; - nvidia,open-drain = ; - }; - jtag_rtck { - nvidia,pins = "jtag_rtck"; - nvidia,function = "rtck"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk_32k_in { - nvidia,pins = "clk_32k_in"; - nvidia,function = "clk"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - core_pwr_req { - nvidia,pins = "core_pwr_req"; - nvidia,function = "pwron"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - cpu_pwr_req { - nvidia,pins = "cpu_pwr_req"; - nvidia,function = "cpu"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col0_ap { - nvidia,pins = "kb_col0_pq0"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - en_vdd_sd { - nvidia,pins = "kb_row0_pr0"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lid_open { - nvidia,pins = "kb_row4_pr4"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pwr_int_n { - nvidia,pins = "pwr_int_n"; - nvidia,function = "pmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - reset_out_n { - nvidia,pins = "reset_out_n"; - nvidia,function = "reset_out_n"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk3_out_pee0 { - nvidia,pins = "clk3_out_pee0"; - nvidia,function = "extperiph3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gen1_i2c_scl_pc4 { - nvidia,pins = "gen1_i2c_scl_pc4", - "gen1_i2c_sda_pc5"; - nvidia,function = "i2c1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,lock = ; - nvidia,open-drain = ; - }; - hdmi_cec_pee3 { - nvidia,pins = "hdmi_cec_pee3"; - nvidia,function = "cec"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,lock = ; - nvidia,open-drain = ; - }; - hdmi_int_pn7 { - nvidia,pins = "hdmi_int_pn7"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ddc_scl_pv4 { - nvidia,pins = "ddc_scl_pv4", - "ddc_sda_pv5"; - nvidia,function = "i2c4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,lock = ; - nvidia,rcv-sel = ; - }; - usb_vbus_en0_pn4 { - nvidia,pins = "usb_vbus_en0_pn4", - "usb_vbus_en1_pn5", - "usb_vbus_en2_pff1"; - nvidia,function = "usb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,lock = ; - nvidia,open-drain = ; - }; - drive_sdio1 { - nvidia,pins = "drive_sdio1"; - nvidia,high-speed-mode = ; - nvidia,schmitt = ; - nvidia,pull-down-strength = <36>; - nvidia,pull-up-strength = <20>; - nvidia,slew-rate-rising = ; - nvidia,slew-rate-falling = ; - }; - drive_sdio3 { - nvidia,pins = "drive_sdio3"; - nvidia,high-speed-mode = ; - nvidia,schmitt = ; - nvidia,pull-down-strength = <22>; - nvidia,pull-up-strength = <36>; - nvidia,slew-rate-rising = ; - nvidia,slew-rate-falling = ; - }; - drive_gma { - nvidia,pins = "drive_gma"; - nvidia,high-speed-mode = ; - nvidia,schmitt = ; - nvidia,pull-down-strength = <2>; - nvidia,pull-up-strength = <1>; - nvidia,slew-rate-rising = ; - nvidia,slew-rate-falling = ; - nvidia,drive-type = <1>; - }; - ac_ok { - nvidia,pins = "pj0"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - codec_irq_l { - nvidia,pins = "ph4"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_bl_en { - nvidia,pins = "ph2"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - touch_irq_l { - nvidia,pins = "gpio_w3_aud_pw3"; - nvidia,function = "spi6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - tpm_davint_l { - nvidia,pins = "ph6"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ts_irq_l { - nvidia,pins = "pk2"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ts_reset_l { - nvidia,pins = "pk4"; - nvidia,function = "gmi"; - nvidia,pull = <1>; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ts_shdn_l { - nvidia,pins = "pk1"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph7 { - nvidia,pins = "ph7"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sensor_irq_l { - nvidia,pins = "pi6"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - wifi_en { - nvidia,pins = "gpio_x7_aud_px7"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - chromeos_write_protect { - nvidia,pins = "kb_row1_pr1"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - hp_det_l { - nvidia,pins = "pi7"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - soc_warm_reset_l { - nvidia,pins = "pi5"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - }; - }; - - serial@70006000 { - status = "okay"; - }; - - pwm: pwm@7000a000 { - status = "okay"; - }; - - /* HDMI DDC */ - hdmi_ddc: i2c@7000c700 { - status = "okay"; - clock-frequency = <100000>; - }; - - i2c@7000d000 { - status = "okay"; - clock-frequency = <400000>; - - as3722: pmic@40 { - compatible = "ams,as3722"; - reg = <0x40>; - interrupts = ; - - ams,system-power-controller; - - #interrupt-cells = <2>; - interrupt-controller; - - #gpio-cells = <2>; - gpio-controller; - - pinctrl-names = "default"; - pinctrl-0 = <&as3722_default>; - - as3722_default: pinmux@0 { - gpio0 { - pins = "gpio0"; - function = "gpio"; - bias-pull-down; - }; - - gpio1 { - pins = "gpio1"; - function = "gpio"; - bias-pull-up; - }; - - gpio2_4_7 { - pins = "gpio2", "gpio4", "gpio7"; - function = "gpio"; - bias-pull-up; - }; - - gpio3 { - pins = "gpio3"; - function = "gpio"; - bias-high-impedance; - }; - - gpio5 { - pins = "gpio5"; - function = "clk32k-out"; - bias-pull-down; - }; - - gpio6 { - pins = "gpio6"; - function = "clk32k-out"; - bias-pull-down; - }; - }; - - regulators { - vsup-sd2-supply = <&vdd_5v0_sys>; - vsup-sd3-supply = <&vdd_5v0_sys>; - vsup-sd4-supply = <&vdd_5v0_sys>; - vsup-sd5-supply = <&vdd_5v0_sys>; - vin-ldo0-supply = <&vdd_1v35_lp0>; - vin-ldo1-6-supply = <&vdd_3v3_sys>; - vin-ldo2-5-7-supply = <&vddio_1v8>; - vin-ldo3-4-supply = <&vdd_3v3_sys>; - vin-ldo9-10-supply = <&vdd_5v0_sys>; - vin-ldo11-supply = <&vdd_3v3_run>; - - sd0 { - regulator-name = "+VDD_CPU_AP"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1350000>; - regulator-max-microamp = <3500000>; - regulator-always-on; - regulator-boot-on; - ams,ext-control = <2>; - }; - - sd1 { - regulator-name = "+VDD_CORE"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1350000>; - regulator-max-microamp = <4000000>; - regulator-always-on; - regulator-boot-on; - ams,ext-control = <1>; - }; - - vdd_1v35_lp0: sd2 { - regulator-name = "+1.35V_LP0(sd2)"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - - sd3 { - regulator-name = "+1.35V_LP0(sd3)"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_1v05_run: sd4 { - regulator-name = "+1.05V_RUN"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - }; - - vddio_1v8: sd5 { - regulator-name = "+1.8V_VDDIO"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_gpu: sd6 { - regulator-name = "+VDD_GPU_AP"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1200000>; - regulator-min-microamp = <3500000>; - regulator-max-microamp = <3500000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo0 { - regulator-name = "+1.05_RUN_AVDD"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - regulator-always-on; - regulator-boot-on; - ams,ext-control = <1>; - }; - - ldo1 { - regulator-name = "+1.8V_RUN_CAM"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo2 { - regulator-name = "+1.2V_GEN_AVDD"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo3 { - regulator-name = "+1.00V_LP0_VDD_RTC"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-boot-on; - ams,enable-tracking; - }; - - vdd_run_cam: ldo4 { - regulator-name = "+2.8V_RUN_CAM"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo5 { - regulator-name = "+1.2V_RUN_CAM_FRONT"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - vddio_sdmmc3: ldo6 { - regulator-name = "+VDDIO_SDMMC3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - ldo7 { - regulator-name = "+1.05V_RUN_CAM_REAR"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - }; - - ldo9 { - regulator-name = "+2.8V_RUN_TOUCH"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo10 { - regulator-name = "+2.8V_RUN_CAM_AF"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo11 { - regulator-name = "+1.8V_RUN_VPP_FUSE"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - }; - }; - }; - - spi@7000d400 { - status = "okay"; - - ec: cros-ec@0 { - compatible = "google,cros-ec-spi"; - spi-max-frequency = <3000000>; - interrupt-parent = <&gpio>; - interrupts = ; - reg = <0>; - - google,cros-ec-spi-msg-delay = <2000>; - - i2c_20: i2c-tunnel { - compatible = "google,cros-ec-i2c-tunnel"; - #address-cells = <1>; - #size-cells = <0>; - - google,remote-bus = <0>; - - charger: bq24735 { - compatible = "ti,bq24735"; - reg = <0x9>; - interrupt-parent = <&gpio>; - interrupts = ; - ti,ac-detect-gpios = <&gpio - TEGRA_GPIO(J, 0) - GPIO_ACTIVE_HIGH>; - }; - - battery: smart-battery { - compatible = "sbs,sbs-battery"; - reg = <0xb>; - battery-name = "battery"; - sbs,i2c-retry-count = <2>; - sbs,poll-retry-count = <10>; - /* power-supplies = <&charger>; */ - }; - }; - - keyboard-controller { - compatible = "google,cros-ec-keyb"; - keypad,num-rows = <8>; - keypad,num-columns = <13>; - google,needs-ghost-filter; - linux,keymap = - ; - }; - }; - }; - - pmc@7000e400 { - nvidia,invert-interrupt; - nvidia,suspend-mode = <0>; - #wake-cells = <3>; - nvidia,cpu-pwr-good-time = <500>; - nvidia,cpu-pwr-off-time = <300>; - nvidia,core-pwr-good-time = <641 3845>; - nvidia,core-pwr-off-time = <61036>; - nvidia,core-power-req-active-high; - nvidia,sys-clock-req-active-high; - nvidia,reset-gpio = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; - }; - - /* WIFI/BT module */ - sdhci@700b0000 { - status = "disabled"; - }; - - /* external SD/MMC */ - sdhci@700b0400 { - cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; - power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; - wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_HIGH>; - status = "okay"; - bus-width = <4>; - vqmmc-supply = <&vddio_sdmmc3>; - }; - - /* EMMC 4.51 */ - sdhci@700b0600 { - status = "okay"; - bus-width = <8>; - non-removable; - }; - - usb@7d000000 { - status = "okay"; - }; - - usb-phy@7d000000 { - status = "okay"; - vbus-supply = <&vdd_usb1_vbus>; - }; - - usb@7d004000 { - status = "okay"; - }; - - usb-phy@7d004000 { - status = "okay"; - vbus-supply = <&vdd_run_cam>; - }; - - usb@7d008000 { - status = "okay"; - }; - - usb-phy@7d008000 { - status = "okay"; - vbus-supply = <&vdd_usb3_vbus>; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - - enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; - power-supply = <&vdd_led>; - pwms = <&pwm 1 1000000>; - - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - - backlight-boot-off; - }; - - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock@0 { - compatible = "fixed-clock"; - reg=<0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - lid { - label = "Lid"; - gpios = <&gpio TEGRA_GPIO(R, 4) GPIO_ACTIVE_LOW>; - linux,input-type = <5>; - linux,code = <0>; - debounce-interval = <1>; - wakeup-source; - }; - - power { - label = "Power"; - gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <10>; - wakeup-source; - }; - }; - - panel: panel { - compatible = "innolux,n116bge", "simple-panel"; - backlight = <&backlight>; - ddc-i2c-bus = <&dpaux>; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - vdd_mux: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "+VDD_MUX"; - regulator-min-microvolt = <19000000>; - regulator-max-microvolt = <19000000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_5v0_sys: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "+5V_SYS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vdd_mux>; - }; - - vdd_3v3_sys: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "+3.3V_SYS"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vdd_mux>; - }; - - vdd_3v3_run: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "+3.3V_RUN"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - gpio = <&as3722 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_3v3_sys>; - }; - - vdd_3v3_hdmi: regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "+3.3V_AVDD_HDMI_AP_GATED"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vdd_3v3_run>; - }; - - vdd_led: regulator@5 { - compatible = "regulator-fixed"; - reg = <5>; - regulator-name = "+VDD_LED"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_mux>; - }; - - vdd_usb1_vbus: regulator@6 { - compatible = "regulator-fixed"; - reg = <6>; - regulator-name = "+5V_USB_HS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; - enable-active-high; - gpio-open-drain; - vin-supply = <&vdd_5v0_sys>; - }; - - vdd_usb3_vbus: regulator@7 { - compatible = "regulator-fixed"; - reg = <7>; - regulator-name = "+5V_USB_SS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>; - enable-active-high; - gpio-open-drain; - vin-supply = <&vdd_5v0_sys>; - }; - - vdd_3v3_panel: regulator@8 { - compatible = "regulator-fixed"; - reg = <8>; - regulator-name = "+3.3V_PANEL"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&as3722 4 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_3v3_sys>; - }; - - vdd_hdmi_pll: regulator@9 { - compatible = "regulator-fixed"; - reg = <9>; - regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL_AP_GATE"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>; - vin-supply = <&vdd_1v05_run>; - }; - - vdd_5v0_hdmi: regulator@10 { - compatible = "regulator-fixed"; - reg = <10>; - regulator-name = "+5V_HDMI_CON"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_5v0_sys>; - }; - - vdd_5v0_ts: regulator@11 { - compatible = "regulator-fixed"; - reg = <11>; - regulator-name = "+5V_VDD_TS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/nvidia/tegra132.dtsi b/sys/gnu/dts/arm64/nvidia/tegra132.dtsi deleted file mode 100644 index 6238e6e274b..00000000000 --- a/sys/gnu/dts/arm64/nvidia/tegra132.dtsi +++ /dev/null @@ -1,1110 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include -#include -#include -#include -#include -#include -#include - -/ { - compatible = "nvidia,tegra132", "nvidia,tegra124"; - interrupt-parent = <&lic>; - #address-cells = <2>; - #size-cells = <2>; - - pcie@1003000 { - compatible = "nvidia,tegra124-pcie"; - device_type = "pci"; - reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */ - 0x0 0x01003800 0x0 0x00000800 /* AFI registers */ - 0x0 0x02000000 0x0 0x10000000>; /* configuration space */ - reg-names = "pads", "afi", "cs"; - interrupts = , /* controller interrupt */ - ; /* MSI interrupt */ - interrupt-names = "intr", "msi"; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; - - bus-range = <0x00 0xff>; - #address-cells = <3>; - #size-cells = <2>; - - ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */ - 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */ - 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */ - 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */ - 0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ - - clocks = <&tegra_car TEGRA124_CLK_PCIE>, - <&tegra_car TEGRA124_CLK_AFI>, - <&tegra_car TEGRA124_CLK_PLL_E>, - <&tegra_car TEGRA124_CLK_CML0>; - clock-names = "pex", "afi", "pll_e", "cml"; - resets = <&tegra_car 70>, - <&tegra_car 72>, - <&tegra_car 74>; - reset-names = "pex", "afi", "pcie_x"; - status = "disabled"; - - phys = <&padctl TEGRA_XUSB_PADCTL_PCIE>; - phy-names = "pcie"; - - pci@1,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>; - reg = <0x000800 0 0 0 0>; - bus-range = <0x00 0xff>; - status = "disabled"; - - #address-cells = <3>; - #size-cells = <2>; - ranges; - - nvidia,num-lanes = <2>; - }; - - pci@2,0 { - device_type = "pci"; - assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>; - reg = <0x001000 0 0 0 0>; - bus-range = <0x00 0xff>; - status = "disabled"; - - #address-cells = <3>; - #size-cells = <2>; - ranges; - - nvidia,num-lanes = <1>; - }; - }; - - host1x@50000000 { - compatible = "nvidia,tegra124-host1x", "simple-bus"; - reg = <0x0 0x50000000 0x0 0x00034000>; - interrupts = , /* syncpt */ - ; /* general */ - clocks = <&tegra_car TEGRA124_CLK_HOST1X>; - clock-names = "host1x"; - resets = <&tegra_car 28>; - reset-names = "host1x"; - - #address-cells = <2>; - #size-cells = <2>; - - ranges = <0 0x54000000 0 0x54000000 0 0x01000000>; - - dc@54200000 { - compatible = "nvidia,tegra124-dc"; - reg = <0x0 0x54200000 0x0 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_DISP1>, - <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "dc", "parent"; - resets = <&tegra_car 27>; - reset-names = "dc"; - - iommus = <&mc TEGRA_SWGROUP_DC>; - - nvidia,head = <0>; - }; - - dc@54240000 { - compatible = "nvidia,tegra124-dc"; - reg = <0x0 0x54240000 0x0 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_DISP2>, - <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "dc", "parent"; - resets = <&tegra_car 26>; - reset-names = "dc"; - - iommus = <&mc TEGRA_SWGROUP_DCB>; - - nvidia,head = <1>; - }; - - hdmi@54280000 { - compatible = "nvidia,tegra124-hdmi"; - reg = <0x0 0x54280000 0x0 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_HDMI>, - <&tegra_car TEGRA124_CLK_PLL_D2_OUT0>; - clock-names = "hdmi", "parent"; - resets = <&tegra_car 51>; - reset-names = "hdmi"; - status = "disabled"; - }; - - sor@54540000 { - compatible = "nvidia,tegra124-sor"; - reg = <0x0 0x54540000 0x0 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_SOR0>, - <&tegra_car TEGRA124_CLK_PLL_D_OUT0>, - <&tegra_car TEGRA124_CLK_PLL_DP>, - <&tegra_car TEGRA124_CLK_CLK_M>; - clock-names = "sor", "parent", "dp", "safe"; - resets = <&tegra_car 182>; - reset-names = "sor"; - status = "disabled"; - }; - - dpaux: dpaux@545c0000 { - compatible = "nvidia,tegra124-dpaux"; - reg = <0x0 0x545c0000 0x0 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_DPAUX>, - <&tegra_car TEGRA124_CLK_PLL_DP>; - clock-names = "dpaux", "parent"; - resets = <&tegra_car 181>; - reset-names = "dpaux"; - status = "disabled"; - }; - }; - - gic: interrupt-controller@50041000 { - compatible = "arm,cortex-a15-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x0 0x50041000 0x0 0x1000>, - <0x0 0x50042000 0x0 0x2000>, - <0x0 0x50044000 0x0 0x2000>, - <0x0 0x50046000 0x0 0x2000>; - interrupts = ; - interrupt-parent = <&gic>; - }; - - gpu@57000000 { - compatible = "nvidia,gk20a"; - reg = <0x0 0x57000000 0x0 0x01000000>, - <0x0 0x58000000 0x0 0x01000000>; - interrupts = , - ; - interrupt-names = "stall", "nonstall"; - clocks = <&tegra_car TEGRA124_CLK_GPU>, - <&tegra_car TEGRA124_CLK_PLL_P_OUT5>; - clock-names = "gpu", "pwr"; - resets = <&tegra_car 184>; - reset-names = "gpu"; - status = "disabled"; - }; - - lic: interrupt-controller@60004000 { - compatible = "nvidia,tegra124-ictlr", "nvidia,tegra30-ictlr"; - reg = <0x0 0x60004000 0x0 0x100>, - <0x0 0x60004100 0x0 0x100>, - <0x0 0x60004200 0x0 0x100>, - <0x0 0x60004300 0x0 0x100>, - <0x0 0x60004400 0x0 0x100>; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - }; - - timer@60005000 { - compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer"; - reg = <0x0 0x60005000 0x0 0x400>; - interrupts = , - , - , - , - , - ; - clocks = <&tegra_car TEGRA124_CLK_TIMER>; - clock-names = "timer"; - }; - - tegra_car: clock@60006000 { - compatible = "nvidia,tegra132-car"; - reg = <0x0 0x60006000 0x0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - nvidia,external-memory-controller = <&emc>; - }; - - flow-controller@60007000 { - compatible = "nvidia,tegra132-flowctrl", "nvidia,tegra124-flowctrl"; - reg = <0x0 0x60007000 0x0 0x1000>; - }; - - actmon@6000c800 { - compatible = "nvidia,tegra124-actmon"; - reg = <0x0 0x6000c800 0x0 0x400>; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_ACTMON>, - <&tegra_car TEGRA124_CLK_EMC>; - clock-names = "actmon", "emc"; - resets = <&tegra_car 119>; - reset-names = "actmon"; - }; - - gpio: gpio@6000d000 { - compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio"; - reg = <0x0 0x6000d000 0x0 0x1000>; - interrupts = , - , - , - , - , - , - , - ; - #gpio-cells = <2>; - gpio-controller; - #interrupt-cells = <2>; - interrupt-controller; - }; - - apbdma: dma@60020000 { - compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma"; - reg = <0x0 0x60020000 0x0 0x1400>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - clocks = <&tegra_car TEGRA124_CLK_APBDMA>; - clock-names = "dma"; - resets = <&tegra_car 34>; - reset-names = "dma"; - #dma-cells = <1>; - }; - - apbmisc@70000800 { - compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc"; - reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */ - <0x0 0x7000e864 0x0 0x04>; /* Strapping options */ - }; - - pinmux: pinmux@70000868 { - compatible = "nvidia,tegra124-pinmux"; - reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */ - <0x0 0x70003000 0x0 0x434>, /* Mux registers */ - <0x0 0x70000820 0x0 0x008>; /* MIPI pad control */ - }; - - /* - * There are two serial driver i.e. 8250 based simple serial - * driver and APB DMA based serial driver for higher baudrate - * and performance. To enable the 8250 based driver, the compatible - * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable - * the APB DMA based serial driver, the compatible is - * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". - */ - uarta: serial@70006000 { - compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; - reg = <0x0 0x70006000 0x0 0x40>; - reg-shift = <2>; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_UARTA>; - clock-names = "serial"; - resets = <&tegra_car 6>; - reset-names = "serial"; - dmas = <&apbdma 8>, <&apbdma 8>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uartb: serial@70006040 { - compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; - reg = <0x0 0x70006040 0x0 0x40>; - reg-shift = <2>; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_UARTB>; - clock-names = "serial"; - resets = <&tegra_car 7>; - reset-names = "serial"; - dmas = <&apbdma 9>, <&apbdma 9>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uartc: serial@70006200 { - compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; - reg = <0x0 0x70006200 0x0 0x40>; - reg-shift = <2>; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_UARTC>; - clock-names = "serial"; - resets = <&tegra_car 55>; - reset-names = "serial"; - dmas = <&apbdma 10>, <&apbdma 10>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uartd: serial@70006300 { - compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; - reg = <0x0 0x70006300 0x0 0x40>; - reg-shift = <2>; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_UARTD>; - clock-names = "serial"; - resets = <&tegra_car 65>; - reset-names = "serial"; - dmas = <&apbdma 19>, <&apbdma 19>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - pwm: pwm@7000a000 { - compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm"; - reg = <0x0 0x7000a000 0x0 0x100>; - #pwm-cells = <2>; - clocks = <&tegra_car TEGRA124_CLK_PWM>; - clock-names = "pwm"; - resets = <&tegra_car 17>; - reset-names = "pwm"; - status = "disabled"; - }; - - i2c@7000c000 { - compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; - reg = <0x0 0x7000c000 0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA124_CLK_I2C1>; - clock-names = "div-clk"; - resets = <&tegra_car 12>; - reset-names = "i2c"; - dmas = <&apbdma 21>, <&apbdma 21>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c@7000c400 { - compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; - reg = <0x0 0x7000c400 0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA124_CLK_I2C2>; - clock-names = "div-clk"; - resets = <&tegra_car 54>; - reset-names = "i2c"; - dmas = <&apbdma 22>, <&apbdma 22>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c@7000c500 { - compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; - reg = <0x0 0x7000c500 0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA124_CLK_I2C3>; - clock-names = "div-clk"; - resets = <&tegra_car 67>; - reset-names = "i2c"; - dmas = <&apbdma 23>, <&apbdma 23>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c@7000c700 { - compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; - reg = <0x0 0x7000c700 0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA124_CLK_I2C4>; - clock-names = "div-clk"; - resets = <&tegra_car 103>; - reset-names = "i2c"; - dmas = <&apbdma 26>, <&apbdma 26>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c@7000d000 { - compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; - reg = <0x0 0x7000d000 0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA124_CLK_I2C5>; - clock-names = "div-clk"; - resets = <&tegra_car 47>; - reset-names = "i2c"; - dmas = <&apbdma 24>, <&apbdma 24>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c@7000d100 { - compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; - reg = <0x0 0x7000d100 0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA124_CLK_I2C6>; - clock-names = "div-clk"; - resets = <&tegra_car 166>; - reset-names = "i2c"; - dmas = <&apbdma 30>, <&apbdma 30>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi@7000d400 { - compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; - reg = <0x0 0x7000d400 0x0 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA124_CLK_SBC1>; - clock-names = "spi"; - resets = <&tegra_car 41>; - reset-names = "spi"; - dmas = <&apbdma 15>, <&apbdma 15>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi@7000d600 { - compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; - reg = <0x0 0x7000d600 0x0 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA124_CLK_SBC2>; - clock-names = "spi"; - resets = <&tegra_car 44>; - reset-names = "spi"; - dmas = <&apbdma 16>, <&apbdma 16>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi@7000d800 { - compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; - reg = <0x0 0x7000d800 0x0 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA124_CLK_SBC3>; - clock-names = "spi"; - resets = <&tegra_car 46>; - reset-names = "spi"; - dmas = <&apbdma 17>, <&apbdma 17>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi@7000da00 { - compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; - reg = <0x0 0x7000da00 0x0 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA124_CLK_SBC4>; - clock-names = "spi"; - resets = <&tegra_car 68>; - reset-names = "spi"; - dmas = <&apbdma 18>, <&apbdma 18>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi@7000dc00 { - compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; - reg = <0x0 0x7000dc00 0x0 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA124_CLK_SBC5>; - clock-names = "spi"; - resets = <&tegra_car 104>; - reset-names = "spi"; - dmas = <&apbdma 27>, <&apbdma 27>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi@7000de00 { - compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; - reg = <0x0 0x7000de00 0x0 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA124_CLK_SBC6>; - clock-names = "spi"; - resets = <&tegra_car 105>; - reset-names = "spi"; - dmas = <&apbdma 28>, <&apbdma 28>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - rtc@7000e000 { - compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc"; - reg = <0x0 0x7000e000 0x0 0x100>; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_RTC>; - clock-names = "rtc"; - }; - - pmc@7000e400 { - compatible = "nvidia,tegra124-pmc"; - reg = <0x0 0x7000e400 0x0 0x400>; - clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>; - clock-names = "pclk", "clk32k_in"; - }; - - fuse@7000f800 { - compatible = "nvidia,tegra124-efuse"; - reg = <0x0 0x7000f800 0x0 0x400>; - clocks = <&tegra_car TEGRA124_CLK_FUSE>; - clock-names = "fuse"; - resets = <&tegra_car 39>; - reset-names = "fuse"; - }; - - mc: memory-controller@70019000 { - compatible = "nvidia,tegra132-mc"; - reg = <0x0 0x70019000 0x0 0x1000>; - clocks = <&tegra_car TEGRA124_CLK_MC>; - clock-names = "mc"; - - interrupts = ; - - #iommu-cells = <1>; - }; - - emc: external-memory-controller@7001b000 { - compatible = "nvidia,tegra132-emc", "nvidia,tegra124-emc"; - reg = <0x0 0x7001b000 0x0 0x1000>; - clocks = <&tegra_car TEGRA124_CLK_EMC>; - clock-names = "emc"; - - nvidia,memory-controller = <&mc>; - }; - - sata@70020000 { - compatible = "nvidia,tegra124-ahci"; - reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */ - <0x0 0x70020000 0x0 0x7000>; /* SATA */ - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_SATA>, - <&tegra_car TEGRA124_CLK_SATA_OOB>, - <&tegra_car TEGRA124_CLK_CML1>, - <&tegra_car TEGRA124_CLK_PLL_E>; - clock-names = "sata", "sata-oob", "cml1", "pll_e"; - resets = <&tegra_car 124>, - <&tegra_car 123>, - <&tegra_car 129>; - reset-names = "sata", "sata-oob", "sata-cold"; - phys = <&padctl TEGRA_XUSB_PADCTL_SATA>; - phy-names = "sata-phy"; - status = "disabled"; - }; - - hda@70030000 { - compatible = "nvidia,tegra132-hda", "nvidia,tegra124-hda", - "nvidia,tegra30-hda"; - reg = <0x0 0x70030000 0x0 0x10000>; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_HDA>, - <&tegra_car TEGRA124_CLK_HDA2HDMI>, - <&tegra_car TEGRA124_CLK_HDA2CODEC_2X>; - clock-names = "hda", "hda2hdmi", "hda2codec_2x"; - resets = <&tegra_car 125>, /* hda */ - <&tegra_car 128>, /* hda2hdmi */ - <&tegra_car 111>; /* hda2codec_2x */ - reset-names = "hda", "hda2hdmi", "hda2codec_2x"; - status = "disabled"; - }; - - padctl: padctl@7009f000 { - compatible = "nvidia,tegra132-xusb-padctl", - "nvidia,tegra124-xusb-padctl"; - reg = <0x0 0x7009f000 0x0 0x1000>; - resets = <&tegra_car 142>; - reset-names = "padctl"; - - #phy-cells = <1>; - - phys { - pcie-0 { - status = "disabled"; - }; - - sata-0 { - status = "disabled"; - }; - - usb3-0 { - status = "disabled"; - }; - - usb3-1 { - status = "disabled"; - }; - - utmi-0 { - status = "disabled"; - }; - - utmi-1 { - status = "disabled"; - }; - - utmi-2 { - status = "disabled"; - }; - }; - }; - - sdhci@700b0000 { - compatible = "nvidia,tegra124-sdhci"; - reg = <0x0 0x700b0000 0x0 0x200>; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_SDMMC1>; - clock-names = "sdhci"; - resets = <&tegra_car 14>; - reset-names = "sdhci"; - status = "disabled"; - }; - - sdhci@700b0200 { - compatible = "nvidia,tegra124-sdhci"; - reg = <0x0 0x700b0200 0x0 0x200>; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_SDMMC2>; - clock-names = "sdhci"; - resets = <&tegra_car 9>; - reset-names = "sdhci"; - status = "disabled"; - }; - - sdhci@700b0400 { - compatible = "nvidia,tegra124-sdhci"; - reg = <0x0 0x700b0400 0x0 0x200>; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_SDMMC3>; - clock-names = "sdhci"; - resets = <&tegra_car 69>; - reset-names = "sdhci"; - status = "disabled"; - }; - - sdhci@700b0600 { - compatible = "nvidia,tegra124-sdhci"; - reg = <0x0 0x700b0600 0x0 0x200>; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_SDMMC4>; - clock-names = "sdhci"; - resets = <&tegra_car 15>; - reset-names = "sdhci"; - status = "disabled"; - }; - - soctherm: thermal-sensor@700e2000 { - compatible = "nvidia,tegra132-soctherm"; - reg = <0x0 0x700e2000 0x0 0x600 /* 0: SOC_THERM reg_base */ - 0x0 0x70040000 0x0 0x200>; /* 2: CCROC reg_base */ - reg-names = "soctherm-reg", "ccroc-reg"; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_TSENSOR>, - <&tegra_car TEGRA124_CLK_SOC_THERM>; - clock-names = "tsensor", "soctherm"; - resets = <&tegra_car 78>; - reset-names = "soctherm"; - #thermal-sensor-cells = <1>; - - throttle-cfgs { - throttle_heavy: heavy { - nvidia,priority = <100>; - nvidia,cpu-throt-level = ; - - #cooling-cells = <2>; - }; - }; - }; - - thermal-zones { - cpu { - polling-delay-passive = <1000>; - polling-delay = <0>; - - thermal-sensors = - <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>; - - trips { - cpu_shutdown_trip { - temperature = <105000>; - hysteresis = <1000>; - type = "critical"; - }; - - cpu_throttle_trip: throttle-trip { - temperature = <102000>; - hysteresis = <1000>; - type = "hot"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu_throttle_trip>; - cooling-device = <&throttle_heavy 1 1>; - }; - }; - }; - mem { - polling-delay-passive = <0>; - polling-delay = <0>; - - thermal-sensors = - <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>; - - trips { - mem_shutdown_trip { - temperature = <101000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - /* - * There are currently no cooling maps, - * because there are no cooling devices. - */ - }; - }; - gpu { - polling-delay-passive = <1000>; - polling-delay = <0>; - - thermal-sensors = - <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>; - - trips { - gpu_shutdown_trip { - temperature = <101000>; - hysteresis = <1000>; - type = "critical"; - }; - - gpu_throttle_trip: throttle-trip { - temperature = <99000>; - hysteresis = <1000>; - type = "hot"; - }; - }; - - cooling-maps { - map0 { - trip = <&gpu_throttle_trip>; - cooling-device = <&throttle_heavy 1 1>; - }; - }; - }; - pllx { - polling-delay-passive = <0>; - polling-delay = <0>; - - thermal-sensors = - <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>; - - trips { - pllx_shutdown_trip { - temperature = <105000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - /* - * There are currently no cooling maps, - * because there are no cooling devices. - */ - }; - }; - }; - - ahub@70300000 { - compatible = "nvidia,tegra124-ahub"; - reg = <0x0 0x70300000 0x0 0x200>, - <0x0 0x70300800 0x0 0x800>, - <0x0 0x70300200 0x0 0x600>; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>, - <&tegra_car TEGRA124_CLK_APBIF>; - clock-names = "d_audio", "apbif"; - resets = <&tegra_car 106>, /* d_audio */ - <&tegra_car 107>, /* apbif */ - <&tegra_car 30>, /* i2s0 */ - <&tegra_car 11>, /* i2s1 */ - <&tegra_car 18>, /* i2s2 */ - <&tegra_car 101>, /* i2s3 */ - <&tegra_car 102>, /* i2s4 */ - <&tegra_car 108>, /* dam0 */ - <&tegra_car 109>, /* dam1 */ - <&tegra_car 110>, /* dam2 */ - <&tegra_car 10>, /* spdif */ - <&tegra_car 153>, /* amx */ - <&tegra_car 185>, /* amx1 */ - <&tegra_car 154>, /* adx */ - <&tegra_car 180>, /* adx1 */ - <&tegra_car 186>, /* afc0 */ - <&tegra_car 187>, /* afc1 */ - <&tegra_car 188>, /* afc2 */ - <&tegra_car 189>, /* afc3 */ - <&tegra_car 190>, /* afc4 */ - <&tegra_car 191>; /* afc5 */ - reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", - "i2s3", "i2s4", "dam0", "dam1", "dam2", - "spdif", "amx", "amx1", "adx", "adx1", - "afc0", "afc1", "afc2", "afc3", "afc4", "afc5"; - dmas = <&apbdma 1>, <&apbdma 1>, - <&apbdma 2>, <&apbdma 2>, - <&apbdma 3>, <&apbdma 3>, - <&apbdma 4>, <&apbdma 4>, - <&apbdma 6>, <&apbdma 6>, - <&apbdma 7>, <&apbdma 7>, - <&apbdma 12>, <&apbdma 12>, - <&apbdma 13>, <&apbdma 13>, - <&apbdma 14>, <&apbdma 14>, - <&apbdma 29>, <&apbdma 29>; - dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2", - "rx3", "tx3", "rx4", "tx4", "rx5", "tx5", - "rx6", "tx6", "rx7", "tx7", "rx8", "tx8", - "rx9", "tx9"; - ranges; - #address-cells = <2>; - #size-cells = <2>; - - tegra_i2s0: i2s@70301000 { - compatible = "nvidia,tegra124-i2s"; - reg = <0x0 0x70301000 0x0 0x100>; - nvidia,ahub-cif-ids = <4 4>; - clocks = <&tegra_car TEGRA124_CLK_I2S0>; - clock-names = "i2s"; - resets = <&tegra_car 30>; - reset-names = "i2s"; - status = "disabled"; - }; - - tegra_i2s1: i2s@70301100 { - compatible = "nvidia,tegra124-i2s"; - reg = <0x0 0x70301100 0x0 0x100>; - nvidia,ahub-cif-ids = <5 5>; - clocks = <&tegra_car TEGRA124_CLK_I2S1>; - clock-names = "i2s"; - resets = <&tegra_car 11>; - reset-names = "i2s"; - status = "disabled"; - }; - - tegra_i2s2: i2s@70301200 { - compatible = "nvidia,tegra124-i2s"; - reg = <0x0 0x70301200 0x0 0x100>; - nvidia,ahub-cif-ids = <6 6>; - clocks = <&tegra_car TEGRA124_CLK_I2S2>; - clock-names = "i2s"; - resets = <&tegra_car 18>; - reset-names = "i2s"; - status = "disabled"; - }; - - tegra_i2s3: i2s@70301300 { - compatible = "nvidia,tegra124-i2s"; - reg = <0x0 0x70301300 0x0 0x100>; - nvidia,ahub-cif-ids = <7 7>; - clocks = <&tegra_car TEGRA124_CLK_I2S3>; - clock-names = "i2s"; - resets = <&tegra_car 101>; - reset-names = "i2s"; - status = "disabled"; - }; - - tegra_i2s4: i2s@70301400 { - compatible = "nvidia,tegra124-i2s"; - reg = <0x0 0x70301400 0x0 0x100>; - nvidia,ahub-cif-ids = <8 8>; - clocks = <&tegra_car TEGRA124_CLK_I2S4>; - clock-names = "i2s"; - resets = <&tegra_car 102>; - reset-names = "i2s"; - status = "disabled"; - }; - }; - - usb@7d000000 { - compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; - reg = <0x0 0x7d000000 0x0 0x4000>; - interrupts = ; - phy_type = "utmi"; - clocks = <&tegra_car TEGRA124_CLK_USBD>; - clock-names = "usb"; - resets = <&tegra_car 22>; - reset-names = "usb"; - nvidia,phy = <&phy1>; - status = "disabled"; - }; - - phy1: usb-phy@7d000000 { - compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; - reg = <0x0 0x7d000000 0x0 0x4000>, - <0x0 0x7d000000 0x0 0x4000>; - phy_type = "utmi"; - clocks = <&tegra_car TEGRA124_CLK_USBD>, - <&tegra_car TEGRA124_CLK_PLL_U>, - <&tegra_car TEGRA124_CLK_USBD>; - clock-names = "reg", "pll_u", "utmi-pads"; - resets = <&tegra_car 22>, <&tegra_car 22>; - reset-names = "usb", "utmi-pads"; - nvidia,hssync-start-delay = <0>; - nvidia,idle-wait-delay = <17>; - nvidia,elastic-limit = <16>; - nvidia,term-range-adj = <6>; - nvidia,xcvr-setup = <9>; - nvidia,xcvr-lsfslew = <0>; - nvidia,xcvr-lsrslew = <3>; - nvidia,hssquelch-level = <2>; - nvidia,hsdiscon-level = <5>; - nvidia,xcvr-hsslew = <12>; - nvidia,has-utmi-pad-registers; - status = "disabled"; - }; - - usb@7d004000 { - compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; - reg = <0x0 0x7d004000 0x0 0x4000>; - interrupts = ; - phy_type = "utmi"; - clocks = <&tegra_car TEGRA124_CLK_USB2>; - clock-names = "usb"; - resets = <&tegra_car 58>; - reset-names = "usb"; - nvidia,phy = <&phy2>; - status = "disabled"; - }; - - phy2: usb-phy@7d004000 { - compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; - reg = <0x0 0x7d004000 0x0 0x4000>, - <0x0 0x7d000000 0x0 0x4000>; - phy_type = "utmi"; - clocks = <&tegra_car TEGRA124_CLK_USB2>, - <&tegra_car TEGRA124_CLK_PLL_U>, - <&tegra_car TEGRA124_CLK_USBD>; - clock-names = "reg", "pll_u", "utmi-pads"; - resets = <&tegra_car 58>, <&tegra_car 22>; - reset-names = "usb", "utmi-pads"; - nvidia,hssync-start-delay = <0>; - nvidia,idle-wait-delay = <17>; - nvidia,elastic-limit = <16>; - nvidia,term-range-adj = <6>; - nvidia,xcvr-setup = <9>; - nvidia,xcvr-lsfslew = <0>; - nvidia,xcvr-lsrslew = <3>; - nvidia,hssquelch-level = <2>; - nvidia,hsdiscon-level = <5>; - nvidia,xcvr-hsslew = <12>; - status = "disabled"; - }; - - usb@7d008000 { - compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; - reg = <0x0 0x7d008000 0x0 0x4000>; - interrupts = ; - phy_type = "utmi"; - clocks = <&tegra_car TEGRA124_CLK_USB3>; - clock-names = "usb"; - resets = <&tegra_car 59>; - reset-names = "usb"; - nvidia,phy = <&phy3>; - status = "disabled"; - }; - - phy3: usb-phy@7d008000 { - compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; - reg = <0x0 0x7d008000 0x0 0x4000>, - <0x0 0x7d000000 0x0 0x4000>; - phy_type = "utmi"; - clocks = <&tegra_car TEGRA124_CLK_USB3>, - <&tegra_car TEGRA124_CLK_PLL_U>, - <&tegra_car TEGRA124_CLK_USBD>; - clock-names = "reg", "pll_u", "utmi-pads"; - resets = <&tegra_car 59>, <&tegra_car 22>; - reset-names = "usb", "utmi-pads"; - nvidia,hssync-start-delay = <0>; - nvidia,idle-wait-delay = <17>; - nvidia,elastic-limit = <16>; - nvidia,term-range-adj = <6>; - nvidia,xcvr-setup = <9>; - nvidia,xcvr-lsfslew = <0>; - nvidia,xcvr-lsrslew = <3>; - nvidia,hssquelch-level = <2>; - nvidia,hsdiscon-level = <5>; - nvidia,xcvr-hsslew = <12>; - status = "disabled"; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "nvidia,denver"; - reg = <0>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "nvidia,denver"; - reg = <1>; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; - interrupt-parent = <&gic>; - }; -}; diff --git a/sys/gnu/dts/arm64/nvidia/tegra186-p2771-0000.dts b/sys/gnu/dts/arm64/nvidia/tegra186-p2771-0000.dts deleted file mode 100644 index f1de4ff6230..00000000000 --- a/sys/gnu/dts/arm64/nvidia/tegra186-p2771-0000.dts +++ /dev/null @@ -1,374 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include -#include - -#include "tegra186-p3310.dtsi" - -/ { - model = "NVIDIA Jetson TX2 Developer Kit"; - compatible = "nvidia,p2771-0000", "nvidia,tegra186"; - - aconnect { - status = "okay"; - - dma-controller@2930000 { - status = "okay"; - }; - - interrupt-controller@2a40000 { - status = "okay"; - }; - }; - - i2c@3160000 { - power-monitor@42 { - compatible = "ti,ina3221"; - reg = <0x42>; - #address-cells = <1>; - #size-cells = <0>; - - channel@0 { - reg = <0x0>; - label = "VDD_MUX"; - shunt-resistor-micro-ohms = <20000>; - }; - - channel@1 { - reg = <0x1>; - label = "VDD_5V0_IO_SYS"; - shunt-resistor-micro-ohms = <5000>; - }; - - channel@2 { - reg = <0x2>; - label = "VDD_3V3_SYS"; - shunt-resistor-micro-ohms = <10000>; - }; - }; - - power-monitor@43 { - compatible = "ti,ina3221"; - reg = <0x43>; - #address-cells = <1>; - #size-cells = <0>; - - channel@0 { - reg = <0x0>; - label = "VDD_3V3_IO_SLP"; - shunt-resistor-micro-ohms = <10000>; - }; - - channel@1 { - reg = <0x1>; - label = "VDD_1V8_IO"; - shunt-resistor-micro-ohms = <10000>; - }; - - channel@2 { - reg = <0x2>; - label = "VDD_M2_IN"; - shunt-resistor-micro-ohms = <10000>; - }; - }; - - exp1: gpio@74 { - compatible = "ti,tca9539"; - reg = <0x74>; - - interrupt-parent = <&gpio>; - interrupts = ; - - #gpio-cells = <2>; - gpio-controller; - - vcc-supply = <&vdd_3v3_sys>; - }; - - exp2: gpio@77 { - compatible = "ti,tca9539"; - reg = <0x77>; - - interrupt-parent = <&gpio>; - interrupts = ; - - #gpio-cells = <2>; - gpio-controller; - - vcc-supply = <&vdd_1v8>; - }; - }; - - /* SDMMC1 (SD/MMC) */ - sdhci@3400000 { - status = "okay"; - - vmmc-supply = <&vdd_sd>; - }; - - hda@3510000 { - nvidia,model = "jetson-tx2-hda"; - status = "okay"; - }; - - padctl@3520000 { - status = "okay"; - - avdd-pll-erefeut-supply = <&vdd_1v8_pll>; - avdd-usb-supply = <&vdd_3v3_sys>; - dvdd-pex-supply = <&vdd_pex>; - dvdd-pex-pll-supply = <&vdd_pex>; - hvdd-pex-supply = <&vdd_1v8>; - hvdd-pex-pll-supply = <&vdd_1v8>; - vclamp-usb-supply = <&vdd_1v8>; - vddio-hsic-supply = <&gnd>; - - pads { - usb2 { - status = "okay"; - - lanes { - usb2-0 { - nvidia,function = "xusb"; - status = "okay"; - }; - - usb2-1 { - nvidia,function = "xusb"; - status = "okay"; - }; - - usb2-2 { - nvidia,function = "xusb"; - status = "okay"; - }; - }; - }; - - usb3 { - status = "okay"; - - lanes { - usb3-0 { - nvidia,function = "xusb"; - status = "okay"; - }; - - usb3-1 { - nvidia,function = "xusb"; - status = "okay"; - }; - - usb3-2 { - nvidia,function = "xusb"; - status = "okay"; - }; - }; - }; - }; - - ports { - usb2-0 { - status = "okay"; - mode = "otg"; - - vbus-supply = <&vdd_usb0>; - }; - - usb2-1 { - status = "okay"; - mode = "host"; - - vbus-supply = <&vdd_usb1>; - }; - - usb3-0 { - nvidia,usb2-companion = <1>; - status = "okay"; - }; - }; - }; - - usb@3530000 { - status = "okay"; - - phys = <&{/padctl@3520000/pads/usb2/lanes/usb2-0}>, - <&{/padctl@3520000/pads/usb2/lanes/usb2-1}>, - <&{/padctl@3520000/pads/usb3/lanes/usb3-0}>; - phy-names = "usb2-0", "usb2-1", "usb3-0"; - }; - - i2c@c250000 { - /* carrier board ID EEPROM */ - eeprom@57 { - compatible = "atmel,24c02"; - reg = <0x57>; - - address-bits = <8>; - page-size = <8>; - size = <256>; - read-only; - }; - }; - - pcie@10003000 { - status = "okay"; - - dvdd-pex-supply = <&vdd_pex>; - hvdd-pex-pll-supply = <&vdd_1v8>; - hvdd-pex-supply = <&vdd_1v8>; - vddio-pexctl-aud-supply = <&vdd_1v8>; - - pci@1,0 { - nvidia,num-lanes = <4>; - status = "okay"; - }; - - pci@2,0 { - nvidia,num-lanes = <0>; - status = "disabled"; - }; - - pci@3,0 { - nvidia,num-lanes = <1>; - status = "disabled"; - }; - }; - - host1x@13e00000 { - status = "okay"; - - dpaux@15040000 { - status = "okay"; - }; - - display-hub@15200000 { - status = "okay"; - }; - - dsi@15300000 { - status = "disabled"; - }; - - /* DP on E3320 */ - sor@15540000 { - status = "okay"; - - avdd-io-hdmi-dp-supply = <&vdd_hdmi_1v05>; - vdd-hdmi-dp-pll = <&vdd_1v8_ap>; - - nvidia,dpaux = <&dpaux>; - }; - - sor@15580000 { - status = "okay"; - - avdd-io-supply = <&vdd_hdmi_1v05>; - vdd-pll-supply = <&vdd_1v8_ap>; - hdmi-supply = <&vdd_hdmi>; - - nvidia,ddc-i2c-bus = <&ddc>; - nvidia,hpd-gpio = <&gpio TEGRA186_MAIN_GPIO(P, 1) - GPIO_ACTIVE_LOW>; - }; - - dpaux@155c0000 { - status = "okay"; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - power { - label = "Power"; - gpios = <&gpio_aon TEGRA186_AON_GPIO(FF, 0) - GPIO_ACTIVE_LOW>; - linux,input-type = ; - linux,code = ; - debounce-interval = <10>; - wakeup-event-action = ; - wakeup-source; - }; - - volume-up { - label = "Volume Up"; - gpios = <&gpio_aon TEGRA186_AON_GPIO(FF, 1) - GPIO_ACTIVE_LOW>; - linux,input-type = ; - linux,code = ; - debounce-interval = <10>; - }; - - volume-down { - label = "Volume Down"; - gpios = <&gpio_aon TEGRA186_AON_GPIO(FF, 2) - GPIO_ACTIVE_LOW>; - linux,input-type = ; - linux,code = ; - debounce-interval = <10>; - }; - }; - - regulators { - vdd_sd: regulator@100 { - compatible = "regulator-fixed"; - reg = <100>; - - regulator-name = "SD_CARD_SW_PWR"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&gpio TEGRA186_MAIN_GPIO(P, 6) - GPIO_ACTIVE_HIGH>; - enable-active-high; - - vin-supply = <&vdd_3v3_sys>; - }; - - vdd_hdmi: regulator@101 { - compatible = "regulator-fixed"; - reg = <101>; - - regulator-name = "VDD_HDMI_5V0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - gpio = <&exp1 14 GPIO_ACTIVE_HIGH>; - enable-active-high; - - vin-supply = <&vdd_5v0_sys>; - }; - - vdd_usb0: regulator@102 { - compatible = "regulator-fixed"; - reg = <102>; - - regulator-name = "VDD_USB0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - gpio = <&gpio TEGRA186_MAIN_GPIO(L, 4) GPIO_ACTIVE_HIGH>; - enable-active-high; - - vin-supply = <&vdd_5v0_sys>; - }; - - vdd_usb1: regulator@103 { - compatible = "regulator-fixed"; - reg = <103>; - - regulator-name = "VDD_USB1"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - gpio = <&gpio TEGRA186_MAIN_GPIO(L, 5) GPIO_ACTIVE_HIGH>; - enable-active-high; - - vin-supply = <&vdd_5v0_sys>; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/nvidia/tegra186-p3310.dtsi b/sys/gnu/dts/arm64/nvidia/tegra186-p3310.dtsi deleted file mode 100644 index 947744d0f04..00000000000 --- a/sys/gnu/dts/arm64/nvidia/tegra186-p3310.dtsi +++ /dev/null @@ -1,432 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "tegra186.dtsi" - -#include - -/ { - model = "NVIDIA Jetson TX2"; - compatible = "nvidia,p3310", "nvidia,tegra186"; - - aliases { - ethernet0 = "/ethernet@2490000"; - sdhci0 = "/sdhci@3460000"; - sdhci1 = "/sdhci@3400000"; - serial0 = &uarta; - i2c0 = "/bpmp/i2c"; - i2c1 = "/i2c@3160000"; - i2c2 = "/i2c@c240000"; - i2c3 = "/i2c@3180000"; - i2c4 = "/i2c@3190000"; - i2c5 = "/i2c@31c0000"; - i2c6 = "/i2c@c250000"; - i2c7 = "/i2c@31e0000"; - }; - - chosen { - bootargs = "earlycon console=ttyS0,115200n8"; - stdout-path = "serial0:115200n8"; - }; - - memory { - device_type = "memory"; - reg = <0x0 0x80000000 0x2 0x00000000>; - }; - - ethernet@2490000 { - status = "okay"; - - phy-reset-gpios = <&gpio TEGRA186_MAIN_GPIO(M, 4) - GPIO_ACTIVE_LOW>; - phy-handle = <&phy>; - phy-mode = "rgmii"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - phy: phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0x0>; - interrupt-parent = <&gpio>; - interrupts = ; - }; - }; - }; - - memory-controller@2c00000 { - status = "okay"; - }; - - serial@3100000 { - status = "okay"; - }; - - i2c@3160000 { - status = "okay"; - - power-monitor@40 { - compatible = "ti,ina3221"; - reg = <0x40>; - #address-cells = <1>; - #size-cells = <0>; - - channel@0 { - reg = <0x0>; - label = "VDD_SYS_GPU"; - shunt-resistor-micro-ohms = <10000>; - }; - - channel@1 { - reg = <0x1>; - label = "VDD_SYS_SOC"; - shunt-resistor-micro-ohms = <10000>; - }; - - channel@2 { - reg = <0x2>; - label = "VDD_3V8_WIFI"; - shunt-resistor-micro-ohms = <10000>; - }; - }; - - power-monitor@41 { - compatible = "ti,ina3221"; - reg = <0x41>; - #address-cells = <1>; - #size-cells = <0>; - - channel@0 { - reg = <0x0>; - label = "VDD_IN"; - shunt-resistor-micro-ohms = <5000>; - }; - - channel@1 { - reg = <0x1>; - label = "VDD_SYS_CPU"; - shunt-resistor-micro-ohms = <10000>; - }; - - channel@2 { - reg = <0x2>; - label = "VDD_5V0_DDR"; - shunt-resistor-micro-ohms = <10000>; - }; - }; - }; - - i2c@3180000 { - status = "okay"; - }; - - ddc: i2c@3190000 { - status = "okay"; - }; - - i2c@31c0000 { - status = "okay"; - }; - - i2c@31e0000 { - status = "okay"; - }; - - /* SDMMC1 (SD/MMC) */ - sdhci@3400000 { - cd-gpios = <&gpio TEGRA186_MAIN_GPIO(P, 5) GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio TEGRA186_MAIN_GPIO(P, 4) GPIO_ACTIVE_HIGH>; - - vqmmc-supply = <&vddio_sdmmc1>; - }; - - /* SDMMC3 (SDIO) */ - sdhci@3440000 { - status = "okay"; - }; - - /* SDMMC4 (eMMC) */ - sdhci@3460000 { - status = "okay"; - bus-width = <8>; - non-removable; - - vqmmc-supply = <&vdd_1v8_ap>; - vmmc-supply = <&vdd_3v3_sys>; - }; - - hsp@3c00000 { - status = "okay"; - }; - - i2c@c240000 { - status = "okay"; - }; - - i2c@c250000 { - status = "okay"; - - /* module ID EEPROM */ - eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - - address-bits = <8>; - page-size = <8>; - size = <256>; - read-only; - }; - }; - - rtc@c2a0000 { - status = "okay"; - }; - - pmc@c360000 { - nvidia,invert-interrupt; - }; - - cpus { - cpu@0 { - enable-method = "psci"; - }; - - cpu@1 { - enable-method = "psci"; - }; - - cpu@2 { - enable-method = "psci"; - }; - - cpu@3 { - enable-method = "psci"; - }; - - cpu@4 { - enable-method = "psci"; - }; - - cpu@5 { - enable-method = "psci"; - }; - }; - - bpmp { - i2c { - status = "okay"; - - pmic: pmic@3c { - compatible = "maxim,max77620"; - reg = <0x3c>; - - interrupts = ; - #interrupt-cells = <2>; - interrupt-controller; - - #gpio-cells = <2>; - gpio-controller; - - pinctrl-names = "default"; - pinctrl-0 = <&max77620_default>; - - max77620_default: pinmux { - gpio0 { - pins = "gpio0"; - function = "gpio"; - }; - - gpio1 { - pins = "gpio1"; - function = "fps-out"; - maxim,active-fps-source = ; - }; - - gpio2 { - pins = "gpio2"; - function = "fps-out"; - maxim,active-fps-source = ; - }; - - gpio3 { - pins = "gpio3"; - function = "fps-out"; - maxim,active-fps-source = ; - }; - - gpio4 { - pins = "gpio4"; - function = "32k-out1"; - drive-push-pull = <1>; - }; - - gpio5 { - pins = "gpio5"; - function = "gpio"; - drive-push-pull = <0>; - }; - - gpio6 { - pins = "gpio6"; - function = "gpio"; - drive-push-pull = <1>; - }; - - gpio7 { - pins = "gpio7"; - function = "gpio"; - drive-push-pull = <0>; - }; - }; - - fps { - fps0 { - maxim,fps-event-source = ; - maxim,shutdown-fps-time-period-us = <640>; - }; - - fps1 { - maxim,fps-event-source = ; - maxim,shutdown-fps-time-period-us = <640>; - }; - - fps2 { - maxim,fps-event-source = ; - maxim,shutdown-fps-time-period-us = <640>; - }; - }; - - regulators { - in-sd0-supply = <&vdd_5v0_sys>; - in-sd1-supply = <&vdd_5v0_sys>; - in-sd2-supply = <&vdd_5v0_sys>; - in-sd3-supply = <&vdd_5v0_sys>; - - in-ldo0-1-supply = <&vdd_5v0_sys>; - in-ldo2-supply = <&vdd_5v0_sys>; - in-ldo3-5-supply = <&vdd_5v0_sys>; - in-ldo4-6-supply = <&vdd_1v8>; - in-ldo7-8-supply = <&avdd_dsi_csi>; - - sd0 { - regulator-name = "VDD_DDR_1V1_PMIC"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - regulator-boot-on; - }; - - avdd_dsi_csi: sd1 { - regulator-name = "AVDD_DSI_CSI_1V2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - vdd_1v8: sd2 { - regulator-name = "VDD_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vdd_3v3_sys: sd3 { - regulator-name = "VDD_3V3_SYS"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vdd_1v8_pll: ldo0 { - regulator-name = "VDD_1V8_AP_PLL"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo2 { - regulator-name = "VDDIO_3V3_AOHV"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - vddio_sdmmc1: ldo3 { - regulator-name = "VDDIO_SDMMC1_AP"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - ldo4 { - regulator-name = "VDD_RTC"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - }; - - vddio_sdmmc3: ldo5 { - regulator-name = "VDDIO_SDMMC3_AP"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - vdd_hdmi_1v05: ldo7 { - regulator-name = "VDD_HDMI_1V05"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - }; - - vdd_pex: ldo8 { - regulator-name = "VDD_PEX_1V05"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - }; - }; - }; - }; - }; - - psci { - compatible = "arm,psci-1.0"; - status = "okay"; - method = "smc"; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - gnd: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - - regulator-name = "GND"; - regulator-min-microvolt = <0>; - regulator-max-microvolt = <0>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_5v0_sys: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - - regulator-name = "VDD_5V0_SYS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_1v8_ap: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - - regulator-name = "VDD_1V8_AP"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - - vin-supply = <&vdd_1v8>; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/nvidia/tegra186.dtsi b/sys/gnu/dts/arm64/nvidia/tegra186.dtsi deleted file mode 100644 index c905527c26e..00000000000 --- a/sys/gnu/dts/arm64/nvidia/tegra186.dtsi +++ /dev/null @@ -1,1454 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/ { - compatible = "nvidia,tegra186"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - misc@100000 { - compatible = "nvidia,tegra186-misc"; - reg = <0x0 0x00100000 0x0 0xf000>, - <0x0 0x0010f000 0x0 0x1000>; - }; - - gpio: gpio@2200000 { - compatible = "nvidia,tegra186-gpio"; - reg-names = "security", "gpio"; - reg = <0x0 0x2200000 0x0 0x10000>, - <0x0 0x2210000 0x0 0x10000>; - interrupts = , - , - , - , - , - ; - #interrupt-cells = <2>; - interrupt-controller; - #gpio-cells = <2>; - gpio-controller; - }; - - ethernet@2490000 { - compatible = "nvidia,tegra186-eqos", - "snps,dwc-qos-ethernet-4.10"; - reg = <0x0 0x02490000 0x0 0x10000>; - interrupts = , /* common */ - , /* power */ - , /* rx0 */ - , /* tx0 */ - , /* rx1 */ - , /* tx1 */ - , /* rx2 */ - , /* tx2 */ - , /* rx3 */ - ; /* tx3 */ - clocks = <&bpmp TEGRA186_CLK_AXI_CBB>, - <&bpmp TEGRA186_CLK_EQOS_AXI>, - <&bpmp TEGRA186_CLK_EQOS_RX>, - <&bpmp TEGRA186_CLK_EQOS_TX>, - <&bpmp TEGRA186_CLK_EQOS_PTP_REF>; - clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; - resets = <&bpmp TEGRA186_RESET_EQOS>; - reset-names = "eqos"; - iommus = <&smmu TEGRA186_SID_EQOS>; - status = "disabled"; - - snps,write-requests = <1>; - snps,read-requests = <3>; - snps,burst-map = <0x7>; - snps,txpbl = <32>; - snps,rxpbl = <8>; - }; - - aconnect { - compatible = "nvidia,tegra186-aconnect", - "nvidia,tegra210-aconnect"; - clocks = <&bpmp TEGRA186_CLK_APE>, - <&bpmp TEGRA186_CLK_APB2APE>; - clock-names = "ape", "apb2ape"; - power-domains = <&bpmp TEGRA186_POWER_DOMAIN_AUD>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x02900000 0x0 0x02900000 0x200000>; - status = "disabled"; - - dma-controller@2930000 { - compatible = "nvidia,tegra186-adma"; - reg = <0x02930000 0x20000>; - interrupt-parent = <&agic>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - #dma-cells = <1>; - clocks = <&bpmp TEGRA186_CLK_AHUB>; - clock-names = "d_audio"; - status = "disabled"; - }; - - agic: interrupt-controller@2a40000 { - compatible = "nvidia,tegra186-agic", - "nvidia,tegra210-agic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x02a41000 0x1000>, - <0x02a42000 0x2000>; - interrupts = ; - clocks = <&bpmp TEGRA186_CLK_APE>; - clock-names = "clk"; - status = "disabled"; - }; - }; - - memory-controller@2c00000 { - compatible = "nvidia,tegra186-mc"; - reg = <0x0 0x02c00000 0x0 0xb0000>; - interrupts = ; - status = "disabled"; - - #address-cells = <2>; - #size-cells = <2>; - - ranges = <0x0 0x02c00000 0x0 0x02c00000 0x0 0xb0000>; - - /* - * Memory clients have access to all 40 bits that the memory - * controller can address. - */ - dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; - - emc: external-memory-controller@2c60000 { - compatible = "nvidia,tegra186-emc"; - reg = <0x0 0x02c60000 0x0 0x50000>; - interrupts = ; - clocks = <&bpmp TEGRA186_CLK_EMC>; - clock-names = "emc"; - - nvidia,bpmp = <&bpmp>; - }; - }; - - uarta: serial@3100000 { - compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; - reg = <0x0 0x03100000 0x0 0x40>; - reg-shift = <2>; - interrupts = ; - clocks = <&bpmp TEGRA186_CLK_UARTA>; - clock-names = "serial"; - resets = <&bpmp TEGRA186_RESET_UARTA>; - reset-names = "serial"; - status = "disabled"; - }; - - uartb: serial@3110000 { - compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; - reg = <0x0 0x03110000 0x0 0x40>; - reg-shift = <2>; - interrupts = ; - clocks = <&bpmp TEGRA186_CLK_UARTB>; - clock-names = "serial"; - resets = <&bpmp TEGRA186_RESET_UARTB>; - reset-names = "serial"; - status = "disabled"; - }; - - uartd: serial@3130000 { - compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; - reg = <0x0 0x03130000 0x0 0x40>; - reg-shift = <2>; - interrupts = ; - clocks = <&bpmp TEGRA186_CLK_UARTD>; - clock-names = "serial"; - resets = <&bpmp TEGRA186_RESET_UARTD>; - reset-names = "serial"; - status = "disabled"; - }; - - uarte: serial@3140000 { - compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; - reg = <0x0 0x03140000 0x0 0x40>; - reg-shift = <2>; - interrupts = ; - clocks = <&bpmp TEGRA186_CLK_UARTE>; - clock-names = "serial"; - resets = <&bpmp TEGRA186_RESET_UARTE>; - reset-names = "serial"; - status = "disabled"; - }; - - uartf: serial@3150000 { - compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; - reg = <0x0 0x03150000 0x0 0x40>; - reg-shift = <2>; - interrupts = ; - clocks = <&bpmp TEGRA186_CLK_UARTF>; - clock-names = "serial"; - resets = <&bpmp TEGRA186_RESET_UARTF>; - reset-names = "serial"; - status = "disabled"; - }; - - gen1_i2c: i2c@3160000 { - compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; - reg = <0x0 0x03160000 0x0 0x10000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&bpmp TEGRA186_CLK_I2C1>; - clock-names = "div-clk"; - resets = <&bpmp TEGRA186_RESET_I2C1>; - reset-names = "i2c"; - status = "disabled"; - }; - - cam_i2c: i2c@3180000 { - compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; - reg = <0x0 0x03180000 0x0 0x10000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&bpmp TEGRA186_CLK_I2C3>; - clock-names = "div-clk"; - resets = <&bpmp TEGRA186_RESET_I2C3>; - reset-names = "i2c"; - status = "disabled"; - }; - - /* shares pads with dpaux1 */ - dp_aux_ch1_i2c: i2c@3190000 { - compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; - reg = <0x0 0x03190000 0x0 0x10000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&bpmp TEGRA186_CLK_I2C4>; - clock-names = "div-clk"; - resets = <&bpmp TEGRA186_RESET_I2C4>; - reset-names = "i2c"; - pinctrl-names = "default", "idle"; - pinctrl-0 = <&state_dpaux1_i2c>; - pinctrl-1 = <&state_dpaux1_off>; - status = "disabled"; - }; - - /* controlled by BPMP, should not be enabled */ - pwr_i2c: i2c@31a0000 { - compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; - reg = <0x0 0x031a0000 0x0 0x10000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&bpmp TEGRA186_CLK_I2C5>; - clock-names = "div-clk"; - resets = <&bpmp TEGRA186_RESET_I2C5>; - reset-names = "i2c"; - status = "disabled"; - }; - - /* shares pads with dpaux0 */ - dp_aux_ch0_i2c: i2c@31b0000 { - compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; - reg = <0x0 0x031b0000 0x0 0x10000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&bpmp TEGRA186_CLK_I2C6>; - clock-names = "div-clk"; - resets = <&bpmp TEGRA186_RESET_I2C6>; - reset-names = "i2c"; - pinctrl-names = "default", "idle"; - pinctrl-0 = <&state_dpaux_i2c>; - pinctrl-1 = <&state_dpaux_off>; - status = "disabled"; - }; - - gen7_i2c: i2c@31c0000 { - compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; - reg = <0x0 0x031c0000 0x0 0x10000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&bpmp TEGRA186_CLK_I2C7>; - clock-names = "div-clk"; - resets = <&bpmp TEGRA186_RESET_I2C7>; - reset-names = "i2c"; - status = "disabled"; - }; - - gen9_i2c: i2c@31e0000 { - compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; - reg = <0x0 0x031e0000 0x0 0x10000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&bpmp TEGRA186_CLK_I2C9>; - clock-names = "div-clk"; - resets = <&bpmp TEGRA186_RESET_I2C9>; - reset-names = "i2c"; - status = "disabled"; - }; - - sdmmc1: sdhci@3400000 { - compatible = "nvidia,tegra186-sdhci"; - reg = <0x0 0x03400000 0x0 0x10000>; - interrupts = ; - clocks = <&bpmp TEGRA186_CLK_SDMMC1>; - clock-names = "sdhci"; - resets = <&bpmp TEGRA186_RESET_SDMMC1>; - reset-names = "sdhci"; - iommus = <&smmu TEGRA186_SID_SDMMC1>; - pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; - pinctrl-0 = <&sdmmc1_3v3>; - pinctrl-1 = <&sdmmc1_1v8>; - nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; - nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; - nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; - nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; - nvidia,pad-autocal-pull-up-offset-sdr104 = <0x03>; - nvidia,pad-autocal-pull-down-offset-sdr104 = <0x05>; - nvidia,default-tap = <0x5>; - nvidia,default-trim = <0xb>; - assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC1>, - <&bpmp TEGRA186_CLK_PLLP_OUT0>; - assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>; - status = "disabled"; - }; - - sdmmc2: sdhci@3420000 { - compatible = "nvidia,tegra186-sdhci"; - reg = <0x0 0x03420000 0x0 0x10000>; - interrupts = ; - clocks = <&bpmp TEGRA186_CLK_SDMMC2>; - clock-names = "sdhci"; - resets = <&bpmp TEGRA186_RESET_SDMMC2>; - reset-names = "sdhci"; - iommus = <&smmu TEGRA186_SID_SDMMC2>; - pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; - pinctrl-0 = <&sdmmc2_3v3>; - pinctrl-1 = <&sdmmc2_1v8>; - nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; - nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; - nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; - nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; - nvidia,default-tap = <0x5>; - nvidia,default-trim = <0xb>; - status = "disabled"; - }; - - sdmmc3: sdhci@3440000 { - compatible = "nvidia,tegra186-sdhci"; - reg = <0x0 0x03440000 0x0 0x10000>; - interrupts = ; - clocks = <&bpmp TEGRA186_CLK_SDMMC3>; - clock-names = "sdhci"; - resets = <&bpmp TEGRA186_RESET_SDMMC3>; - reset-names = "sdhci"; - iommus = <&smmu TEGRA186_SID_SDMMC3>; - pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; - pinctrl-0 = <&sdmmc3_3v3>; - pinctrl-1 = <&sdmmc3_1v8>; - nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; - nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; - nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; - nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; - nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; - nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; - nvidia,default-tap = <0x5>; - nvidia,default-trim = <0xb>; - status = "disabled"; - }; - - sdmmc4: sdhci@3460000 { - compatible = "nvidia,tegra186-sdhci"; - reg = <0x0 0x03460000 0x0 0x10000>; - interrupts = ; - clocks = <&bpmp TEGRA186_CLK_SDMMC4>; - clock-names = "sdhci"; - assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC4>, - <&bpmp TEGRA186_CLK_PLLC4_VCO>; - assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>; - resets = <&bpmp TEGRA186_RESET_SDMMC4>; - reset-names = "sdhci"; - iommus = <&smmu TEGRA186_SID_SDMMC4>; - nvidia,pad-autocal-pull-up-offset-hs400 = <0x05>; - nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>; - nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; - nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; - nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; - nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>; - nvidia,default-tap = <0x9>; - nvidia,default-trim = <0x5>; - nvidia,dqs-trim = <63>; - mmc-hs400-1_8v; - supports-cqe; - status = "disabled"; - }; - - hda@3510000 { - compatible = "nvidia,tegra186-hda", "nvidia,tegra30-hda"; - reg = <0x0 0x03510000 0x0 0x10000>; - interrupts = ; - clocks = <&bpmp TEGRA186_CLK_HDA>, - <&bpmp TEGRA186_CLK_HDA2HDMICODEC>, - <&bpmp TEGRA186_CLK_HDA2CODEC_2X>; - clock-names = "hda", "hda2hdmi", "hda2codec_2x"; - resets = <&bpmp TEGRA186_RESET_HDA>, - <&bpmp TEGRA186_RESET_HDA2HDMICODEC>, - <&bpmp TEGRA186_RESET_HDA2CODEC_2X>; - reset-names = "hda", "hda2hdmi", "hda2codec_2x"; - power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; - iommus = <&smmu TEGRA186_SID_HDA>; - status = "disabled"; - }; - - padctl: padctl@3520000 { - compatible = "nvidia,tegra186-xusb-padctl"; - reg = <0x0 0x03520000 0x0 0x1000>, - <0x0 0x03540000 0x0 0x1000>; - reg-names = "padctl", "ao"; - - resets = <&bpmp TEGRA186_RESET_XUSB_PADCTL>; - reset-names = "padctl"; - - status = "disabled"; - - pads { - usb2 { - clocks = <&bpmp TEGRA186_CLK_USB2_TRK>; - clock-names = "trk"; - status = "disabled"; - - lanes { - usb2-0 { - status = "disabled"; - #phy-cells = <0>; - }; - - usb2-1 { - status = "disabled"; - #phy-cells = <0>; - }; - - usb2-2 { - status = "disabled"; - #phy-cells = <0>; - }; - }; - }; - - hsic { - clocks = <&bpmp TEGRA186_CLK_HSIC_TRK>; - clock-names = "trk"; - status = "disabled"; - - lanes { - hsic-0 { - status = "disabled"; - #phy-cells = <0>; - }; - }; - }; - - usb3 { - status = "disabled"; - - lanes { - usb3-0 { - status = "disabled"; - #phy-cells = <0>; - }; - - usb3-1 { - status = "disabled"; - #phy-cells = <0>; - }; - - usb3-2 { - status = "disabled"; - #phy-cells = <0>; - }; - }; - }; - }; - - ports { - usb2-0 { - status = "disabled"; - }; - - usb2-1 { - status = "disabled"; - }; - - usb2-2 { - status = "disabled"; - }; - - hsic-0 { - status = "disabled"; - }; - - usb3-0 { - status = "disabled"; - }; - - usb3-1 { - status = "disabled"; - }; - - usb3-2 { - status = "disabled"; - }; - }; - }; - - usb@3530000 { - compatible = "nvidia,tegra186-xusb"; - reg = <0x0 0x03530000 0x0 0x8000>, - <0x0 0x03538000 0x0 0x1000>; - reg-names = "hcd", "fpci"; - interrupts = , - , - ; - clocks = <&bpmp TEGRA186_CLK_XUSB_HOST>, - <&bpmp TEGRA186_CLK_XUSB_FALCON>, - <&bpmp TEGRA186_CLK_XUSB_SS>, - <&bpmp TEGRA186_CLK_XUSB_CORE_SS>, - <&bpmp TEGRA186_CLK_CLK_M>, - <&bpmp TEGRA186_CLK_XUSB_FS>, - <&bpmp TEGRA186_CLK_PLLU>, - <&bpmp TEGRA186_CLK_CLK_M>, - <&bpmp TEGRA186_CLK_PLLE>; - clock-names = "xusb_host", "xusb_falcon_src", "xusb_ss", - "xusb_ss_src", "xusb_hs_src", "xusb_fs_src", - "pll_u_480m", "clk_m", "pll_e"; - power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBC>, - <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>; - power-domain-names = "xusb_host", "xusb_ss"; - iommus = <&smmu TEGRA186_SID_XUSB_HOST>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - nvidia,xusb-padctl = <&padctl>; - }; - - fuse@3820000 { - compatible = "nvidia,tegra186-efuse"; - reg = <0x0 0x03820000 0x0 0x10000>; - clocks = <&bpmp TEGRA186_CLK_FUSE>; - clock-names = "fuse"; - }; - - gic: interrupt-controller@3881000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x0 0x03881000 0x0 0x1000>, - <0x0 0x03882000 0x0 0x2000>; - interrupts = ; - interrupt-parent = <&gic>; - }; - - cec@3960000 { - compatible = "nvidia,tegra186-cec"; - reg = <0x0 0x03960000 0x0 0x10000>; - interrupts = ; - clocks = <&bpmp TEGRA186_CLK_CEC>; - clock-names = "cec"; - status = "disabled"; - }; - - hsp_top0: hsp@3c00000 { - compatible = "nvidia,tegra186-hsp"; - reg = <0x0 0x03c00000 0x0 0xa0000>; - interrupts = ; - interrupt-names = "doorbell"; - #mbox-cells = <2>; - status = "disabled"; - }; - - gen2_i2c: i2c@c240000 { - compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; - reg = <0x0 0x0c240000 0x0 0x10000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&bpmp TEGRA186_CLK_I2C2>; - clock-names = "div-clk"; - resets = <&bpmp TEGRA186_RESET_I2C2>; - reset-names = "i2c"; - status = "disabled"; - }; - - gen8_i2c: i2c@c250000 { - compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; - reg = <0x0 0x0c250000 0x0 0x10000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&bpmp TEGRA186_CLK_I2C8>; - clock-names = "div-clk"; - resets = <&bpmp TEGRA186_RESET_I2C8>; - reset-names = "i2c"; - status = "disabled"; - }; - - uartc: serial@c280000 { - compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; - reg = <0x0 0x0c280000 0x0 0x40>; - reg-shift = <2>; - interrupts = ; - clocks = <&bpmp TEGRA186_CLK_UARTC>; - clock-names = "serial"; - resets = <&bpmp TEGRA186_RESET_UARTC>; - reset-names = "serial"; - status = "disabled"; - }; - - uartg: serial@c290000 { - compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; - reg = <0x0 0x0c290000 0x0 0x40>; - reg-shift = <2>; - interrupts = ; - clocks = <&bpmp TEGRA186_CLK_UARTG>; - clock-names = "serial"; - resets = <&bpmp TEGRA186_RESET_UARTG>; - reset-names = "serial"; - status = "disabled"; - }; - - rtc: rtc@c2a0000 { - compatible = "nvidia,tegra186-rtc", "nvidia,tegra20-rtc"; - reg = <0 0x0c2a0000 0 0x10000>; - interrupt-parent = <&pmc>; - interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&bpmp TEGRA186_CLK_CLK_32K>; - clock-names = "rtc"; - status = "disabled"; - }; - - gpio_aon: gpio@c2f0000 { - compatible = "nvidia,tegra186-gpio-aon"; - reg-names = "security", "gpio"; - reg = <0x0 0xc2f0000 0x0 0x1000>, - <0x0 0xc2f1000 0x0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - pmc: pmc@c360000 { - compatible = "nvidia,tegra186-pmc"; - reg = <0 0x0c360000 0 0x10000>, - <0 0x0c370000 0 0x10000>, - <0 0x0c380000 0 0x10000>, - <0 0x0c390000 0 0x10000>; - reg-names = "pmc", "wake", "aotag", "scratch"; - - #interrupt-cells = <2>; - interrupt-controller; - - sdmmc1_3v3: sdmmc1-3v3 { - pins = "sdmmc1-hv"; - power-source = ; - }; - - sdmmc1_1v8: sdmmc1-1v8 { - pins = "sdmmc1-hv"; - power-source = ; - }; - - sdmmc2_3v3: sdmmc2-3v3 { - pins = "sdmmc2-hv"; - power-source = ; - }; - - sdmmc2_1v8: sdmmc2-1v8 { - pins = "sdmmc2-hv"; - power-source = ; - }; - - sdmmc3_3v3: sdmmc3-3v3 { - pins = "sdmmc3-hv"; - power-source = ; - }; - - sdmmc3_1v8: sdmmc3-1v8 { - pins = "sdmmc3-hv"; - power-source = ; - }; - }; - - ccplex@e000000 { - compatible = "nvidia,tegra186-ccplex-cluster"; - reg = <0x0 0x0e000000 0x0 0x3fffff>; - - nvidia,bpmp = <&bpmp>; - }; - - pcie@10003000 { - compatible = "nvidia,tegra186-pcie"; - power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>; - device_type = "pci"; - reg = <0x0 0x10003000 0x0 0x00000800 /* PADS registers */ - 0x0 0x10003800 0x0 0x00000800 /* AFI registers */ - 0x0 0x40000000 0x0 0x10000000>; /* configuration space */ - reg-names = "pads", "afi", "cs"; - - interrupts = , /* controller interrupt */ - ; /* MSI interrupt */ - interrupt-names = "intr", "msi"; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; - - bus-range = <0x00 0xff>; - #address-cells = <3>; - #size-cells = <2>; - - ranges = <0x82000000 0 0x10000000 0x0 0x10000000 0 0x00001000 /* port 0 configuration space */ - 0x82000000 0 0x10001000 0x0 0x10001000 0 0x00001000 /* port 1 configuration space */ - 0x82000000 0 0x10004000 0x0 0x10004000 0 0x00001000 /* port 2 configuration space */ - 0x81000000 0 0x0 0x0 0x50000000 0 0x00010000 /* downstream I/O (64 KiB) */ - 0x82000000 0 0x50100000 0x0 0x50100000 0 0x07F00000 /* non-prefetchable memory (127 MiB) */ - 0xc2000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */ - - clocks = <&bpmp TEGRA186_CLK_AFI>, - <&bpmp TEGRA186_CLK_PCIE>, - <&bpmp TEGRA186_CLK_PLLE>; - clock-names = "afi", "pex", "pll_e"; - - resets = <&bpmp TEGRA186_RESET_AFI>, - <&bpmp TEGRA186_RESET_PCIE>, - <&bpmp TEGRA186_RESET_PCIEXCLK>; - reset-names = "afi", "pex", "pcie_x"; - - iommus = <&smmu TEGRA186_SID_AFI>; - iommu-map = <0x0 &smmu TEGRA186_SID_AFI 0x1000>; - iommu-map-mask = <0x0>; - - status = "disabled"; - - pci@1,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>; - reg = <0x000800 0 0 0 0>; - status = "disabled"; - - #address-cells = <3>; - #size-cells = <2>; - ranges; - - nvidia,num-lanes = <2>; - }; - - pci@2,0 { - device_type = "pci"; - assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>; - reg = <0x001000 0 0 0 0>; - status = "disabled"; - - #address-cells = <3>; - #size-cells = <2>; - ranges; - - nvidia,num-lanes = <1>; - }; - - pci@3,0 { - device_type = "pci"; - assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>; - reg = <0x001800 0 0 0 0>; - status = "disabled"; - - #address-cells = <3>; - #size-cells = <2>; - ranges; - - nvidia,num-lanes = <1>; - }; - }; - - smmu: iommu@12000000 { - compatible = "arm,mmu-500"; - reg = <0 0x12000000 0 0x800000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - stream-match-mask = <0x7f80>; - #global-interrupts = <1>; - #iommu-cells = <1>; - }; - - host1x@13e00000 { - compatible = "nvidia,tegra186-host1x", "simple-bus"; - reg = <0x0 0x13e00000 0x0 0x10000>, - <0x0 0x13e10000 0x0 0x10000>; - reg-names = "hypervisor", "vm"; - interrupts = , - ; - clocks = <&bpmp TEGRA186_CLK_HOST1X>; - clock-names = "host1x"; - resets = <&bpmp TEGRA186_RESET_HOST1X>; - reset-names = "host1x"; - - #address-cells = <1>; - #size-cells = <1>; - - ranges = <0x15000000 0x0 0x15000000 0x01000000>; - iommus = <&smmu TEGRA186_SID_HOST1X>; - - dpaux1: dpaux@15040000 { - compatible = "nvidia,tegra186-dpaux"; - reg = <0x15040000 0x10000>; - interrupts = ; - clocks = <&bpmp TEGRA186_CLK_DPAUX1>, - <&bpmp TEGRA186_CLK_PLLDP>; - clock-names = "dpaux", "parent"; - resets = <&bpmp TEGRA186_RESET_DPAUX1>; - reset-names = "dpaux"; - status = "disabled"; - - power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; - - state_dpaux1_aux: pinmux-aux { - groups = "dpaux-io"; - function = "aux"; - }; - - state_dpaux1_i2c: pinmux-i2c { - groups = "dpaux-io"; - function = "i2c"; - }; - - state_dpaux1_off: pinmux-off { - groups = "dpaux-io"; - function = "off"; - }; - - i2c-bus { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - display-hub@15200000 { - compatible = "nvidia,tegra186-display", "simple-bus"; - reg = <0x15200000 0x00040000>; - resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>, - <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>, - <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>, - <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>, - <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>, - <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>, - <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>; - reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", - "wgrp3", "wgrp4", "wgrp5"; - clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>, - <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>, - <&bpmp TEGRA186_CLK_NVDISPLAYHUB>; - clock-names = "disp", "dsc", "hub"; - status = "disabled"; - - power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; - - #address-cells = <1>; - #size-cells = <1>; - - ranges = <0x15200000 0x15200000 0x40000>; - - display@15200000 { - compatible = "nvidia,tegra186-dc"; - reg = <0x15200000 0x10000>; - interrupts = ; - clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>; - clock-names = "dc"; - resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>; - reset-names = "dc"; - - power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; - iommus = <&smmu TEGRA186_SID_NVDISPLAY>; - - nvidia,outputs = <&dsia &dsib &sor0 &sor1>; - nvidia,head = <0>; - }; - - display@15210000 { - compatible = "nvidia,tegra186-dc"; - reg = <0x15210000 0x10000>; - interrupts = ; - clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>; - clock-names = "dc"; - resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>; - reset-names = "dc"; - - power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>; - iommus = <&smmu TEGRA186_SID_NVDISPLAY>; - - nvidia,outputs = <&dsia &dsib &sor0 &sor1>; - nvidia,head = <1>; - }; - - display@15220000 { - compatible = "nvidia,tegra186-dc"; - reg = <0x15220000 0x10000>; - interrupts = ; - clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>; - clock-names = "dc"; - resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>; - reset-names = "dc"; - - power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>; - iommus = <&smmu TEGRA186_SID_NVDISPLAY>; - - nvidia,outputs = <&sor0 &sor1>; - nvidia,head = <2>; - }; - }; - - dsia: dsi@15300000 { - compatible = "nvidia,tegra186-dsi"; - reg = <0x15300000 0x10000>; - interrupts = ; - clocks = <&bpmp TEGRA186_CLK_DSI>, - <&bpmp TEGRA186_CLK_DSIA_LP>, - <&bpmp TEGRA186_CLK_PLLD>; - clock-names = "dsi", "lp", "parent"; - resets = <&bpmp TEGRA186_RESET_DSI>; - reset-names = "dsi"; - status = "disabled"; - - power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; - }; - - vic@15340000 { - compatible = "nvidia,tegra186-vic"; - reg = <0x15340000 0x40000>; - interrupts = ; - clocks = <&bpmp TEGRA186_CLK_VIC>; - clock-names = "vic"; - resets = <&bpmp TEGRA186_RESET_VIC>; - reset-names = "vic"; - - power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>; - iommus = <&smmu TEGRA186_SID_VIC>; - }; - - dsib: dsi@15400000 { - compatible = "nvidia,tegra186-dsi"; - reg = <0x15400000 0x10000>; - interrupts = ; - clocks = <&bpmp TEGRA186_CLK_DSIB>, - <&bpmp TEGRA186_CLK_DSIB_LP>, - <&bpmp TEGRA186_CLK_PLLD>; - clock-names = "dsi", "lp", "parent"; - resets = <&bpmp TEGRA186_RESET_DSIB>; - reset-names = "dsi"; - status = "disabled"; - - power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; - }; - - sor0: sor@15540000 { - compatible = "nvidia,tegra186-sor"; - reg = <0x15540000 0x10000>; - interrupts = ; - clocks = <&bpmp TEGRA186_CLK_SOR0>, - <&bpmp TEGRA186_CLK_SOR0_OUT>, - <&bpmp TEGRA186_CLK_PLLD2>, - <&bpmp TEGRA186_CLK_PLLDP>, - <&bpmp TEGRA186_CLK_SOR_SAFE>, - <&bpmp TEGRA186_CLK_SOR0_PAD_CLKOUT>; - clock-names = "sor", "out", "parent", "dp", "safe", - "pad"; - resets = <&bpmp TEGRA186_RESET_SOR0>; - reset-names = "sor"; - pinctrl-0 = <&state_dpaux_aux>; - pinctrl-1 = <&state_dpaux_i2c>; - pinctrl-2 = <&state_dpaux_off>; - pinctrl-names = "aux", "i2c", "off"; - status = "disabled"; - - power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; - nvidia,interface = <0>; - }; - - sor1: sor@15580000 { - compatible = "nvidia,tegra186-sor"; - reg = <0x15580000 0x10000>; - interrupts = ; - clocks = <&bpmp TEGRA186_CLK_SOR1>, - <&bpmp TEGRA186_CLK_SOR1_OUT>, - <&bpmp TEGRA186_CLK_PLLD3>, - <&bpmp TEGRA186_CLK_PLLDP>, - <&bpmp TEGRA186_CLK_SOR_SAFE>, - <&bpmp TEGRA186_CLK_SOR1_PAD_CLKOUT>; - clock-names = "sor", "out", "parent", "dp", "safe", - "pad"; - resets = <&bpmp TEGRA186_RESET_SOR1>; - reset-names = "sor"; - pinctrl-0 = <&state_dpaux1_aux>; - pinctrl-1 = <&state_dpaux1_i2c>; - pinctrl-2 = <&state_dpaux1_off>; - pinctrl-names = "aux", "i2c", "off"; - status = "disabled"; - - power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; - nvidia,interface = <1>; - }; - - dpaux: dpaux@155c0000 { - compatible = "nvidia,tegra186-dpaux"; - reg = <0x155c0000 0x10000>; - interrupts = ; - clocks = <&bpmp TEGRA186_CLK_DPAUX>, - <&bpmp TEGRA186_CLK_PLLDP>; - clock-names = "dpaux", "parent"; - resets = <&bpmp TEGRA186_RESET_DPAUX>; - reset-names = "dpaux"; - status = "disabled"; - - power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; - - state_dpaux_aux: pinmux-aux { - groups = "dpaux-io"; - function = "aux"; - }; - - state_dpaux_i2c: pinmux-i2c { - groups = "dpaux-io"; - function = "i2c"; - }; - - state_dpaux_off: pinmux-off { - groups = "dpaux-io"; - function = "off"; - }; - - i2c-bus { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - padctl@15880000 { - compatible = "nvidia,tegra186-dsi-padctl"; - reg = <0x15880000 0x10000>; - resets = <&bpmp TEGRA186_RESET_DSI>; - reset-names = "dsi"; - status = "disabled"; - }; - - dsic: dsi@15900000 { - compatible = "nvidia,tegra186-dsi"; - reg = <0x15900000 0x10000>; - interrupts = ; - clocks = <&bpmp TEGRA186_CLK_DSIC>, - <&bpmp TEGRA186_CLK_DSIC_LP>, - <&bpmp TEGRA186_CLK_PLLD>; - clock-names = "dsi", "lp", "parent"; - resets = <&bpmp TEGRA186_RESET_DSIC>; - reset-names = "dsi"; - status = "disabled"; - - power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; - }; - - dsid: dsi@15940000 { - compatible = "nvidia,tegra186-dsi"; - reg = <0x15940000 0x10000>; - interrupts = ; - clocks = <&bpmp TEGRA186_CLK_DSID>, - <&bpmp TEGRA186_CLK_DSID_LP>, - <&bpmp TEGRA186_CLK_PLLD>; - clock-names = "dsi", "lp", "parent"; - resets = <&bpmp TEGRA186_RESET_DSID>; - reset-names = "dsi"; - status = "disabled"; - - power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; - }; - }; - - gpu@17000000 { - compatible = "nvidia,gp10b"; - reg = <0x0 0x17000000 0x0 0x1000000>, - <0x0 0x18000000 0x0 0x1000000>; - interrupts = ; - interrupt-names = "stall", "nonstall"; - - clocks = <&bpmp TEGRA186_CLK_GPCCLK>, - <&bpmp TEGRA186_CLK_GPU>; - clock-names = "gpu", "pwr"; - resets = <&bpmp TEGRA186_RESET_GPU>; - reset-names = "gpu"; - status = "disabled"; - - power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>; - }; - - sysram@30000000 { - compatible = "nvidia,tegra186-sysram", "mmio-sram"; - reg = <0x0 0x30000000 0x0 0x50000>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>; - - cpu_bpmp_tx: shmem@4e000 { - compatible = "nvidia,tegra186-bpmp-shmem"; - reg = <0x0 0x4e000 0x0 0x1000>; - label = "cpu-bpmp-tx"; - pool; - }; - - cpu_bpmp_rx: shmem@4f000 { - compatible = "nvidia,tegra186-bpmp-shmem"; - reg = <0x0 0x4f000 0x0 0x1000>; - label = "cpu-bpmp-rx"; - pool; - }; - }; - - bpmp: bpmp { - compatible = "nvidia,tegra186-bpmp"; - iommus = <&smmu TEGRA186_SID_BPMP>; - mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB - TEGRA_HSP_DB_MASTER_BPMP>; - shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - - bpmp_i2c: i2c { - compatible = "nvidia,tegra186-bpmp-i2c"; - nvidia,bpmp-bus-id = <5>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - bpmp_thermal: thermal { - compatible = "nvidia,tegra186-bpmp-thermal"; - #thermal-sensor-cells = <1>; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "nvidia,tegra186-denver"; - device_type = "cpu"; - i-cache-size = <0x20000>; - i-cache-line-size = <64>; - i-cache-sets = <512>; - d-cache-size = <0x10000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&L2_DENVER>; - reg = <0x000>; - }; - - cpu@1 { - compatible = "nvidia,tegra186-denver"; - device_type = "cpu"; - i-cache-size = <0x20000>; - i-cache-line-size = <64>; - i-cache-sets = <512>; - d-cache-size = <0x10000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&L2_DENVER>; - reg = <0x001>; - }; - - cpu@2 { - compatible = "arm,cortex-a57"; - device_type = "cpu"; - i-cache-size = <0xC000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&L2_A57>; - reg = <0x100>; - }; - - cpu@3 { - compatible = "arm,cortex-a57"; - device_type = "cpu"; - i-cache-size = <0xC000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&L2_A57>; - reg = <0x101>; - }; - - cpu@4 { - compatible = "arm,cortex-a57"; - device_type = "cpu"; - i-cache-size = <0xC000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&L2_A57>; - reg = <0x102>; - }; - - cpu@5 { - compatible = "arm,cortex-a57"; - device_type = "cpu"; - i-cache-size = <0xC000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&L2_A57>; - reg = <0x103>; - }; - - L2_DENVER: l2-cache0 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - cache-size = <0x200000>; - cache-line-size = <64>; - cache-sets = <2048>; - }; - - L2_A57: l2-cache1 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - cache-size = <0x200000>; - cache-line-size = <64>; - cache-sets = <2048>; - }; - }; - - thermal-zones { - a57 { - polling-delay = <0>; - polling-delay-passive = <1000>; - - thermal-sensors = - <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>; - - trips { - critical { - temperature = <101000>; - hysteresis = <0>; - type = "critical"; - }; - }; - - cooling-maps { - }; - }; - - denver { - polling-delay = <0>; - polling-delay-passive = <1000>; - - thermal-sensors = - <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>; - - trips { - critical { - temperature = <101000>; - hysteresis = <0>; - type = "critical"; - }; - }; - - cooling-maps { - }; - }; - - gpu { - polling-delay = <0>; - polling-delay-passive = <1000>; - - thermal-sensors = - <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>; - - trips { - critical { - temperature = <101000>; - hysteresis = <0>; - type = "critical"; - }; - }; - - cooling-maps { - }; - }; - - pll { - polling-delay = <0>; - polling-delay-passive = <1000>; - - thermal-sensors = - <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>; - - trips { - critical { - temperature = <101000>; - hysteresis = <0>; - type = "critical"; - }; - }; - - cooling-maps { - }; - }; - - always_on { - polling-delay = <0>; - polling-delay-passive = <1000>; - - thermal-sensors = - <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>; - - trips { - critical { - temperature = <101000>; - hysteresis = <0>; - type = "critical"; - }; - }; - - cooling-maps { - }; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - interrupt-parent = <&gic>; - always-on; - }; -}; diff --git a/sys/gnu/dts/arm64/nvidia/tegra194-p2888.dtsi b/sys/gnu/dts/arm64/nvidia/tegra194-p2888.dtsi deleted file mode 100644 index bdd33ff4e32..00000000000 --- a/sys/gnu/dts/arm64/nvidia/tegra194-p2888.dtsi +++ /dev/null @@ -1,321 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "tegra194.dtsi" - -#include - -/ { - model = "NVIDIA Jetson AGX Xavier"; - compatible = "nvidia,p2888", "nvidia,tegra194"; - - aliases { - ethernet0 = "/cbb@0/ethernet@2490000"; - sdhci0 = "/cbb@0/sdhci@3460000"; - sdhci1 = "/cbb@0/sdhci@3400000"; - serial0 = &tcu; - i2c0 = "/bpmp/i2c"; - i2c1 = "/cbb@0/i2c@3160000"; - i2c2 = "/cbb@0/i2c@c240000"; - i2c3 = "/cbb@0/i2c@3180000"; - i2c4 = "/cbb@0/i2c@3190000"; - i2c5 = "/cbb@0/i2c@31c0000"; - i2c6 = "/cbb@0/i2c@c250000"; - i2c7 = "/cbb@0/i2c@31e0000"; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = "serial0:115200n8"; - }; - - cbb@0 { - ethernet@2490000 { - status = "okay"; - - phy-reset-gpios = <&gpio TEGRA194_MAIN_GPIO(G, 5) GPIO_ACTIVE_LOW>; - phy-handle = <&phy>; - phy-mode = "rgmii"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - phy: phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0x0>; - interrupt-parent = <&gpio>; - interrupts = ; - }; - }; - }; - - memory-controller@2c00000 { - status = "okay"; - }; - - serial@3110000 { - status = "okay"; - }; - - /* SDMMC1 (SD/MMC) */ - sdhci@3400000 { - cd-gpios = <&gpio TEGRA194_MAIN_GPIO(A, 0) GPIO_ACTIVE_LOW>; - }; - - /* SDMMC4 (eMMC) */ - sdhci@3460000 { - status = "okay"; - bus-width = <8>; - non-removable; - - vqmmc-supply = <&vdd_1v8ls>; - vmmc-supply = <&vdd_emmc_3v3>; - }; - - rtc@c2a0000 { - status = "okay"; - }; - - pmc@c360000 { - nvidia,invert-interrupt; - }; - }; - - bpmp { - i2c { - status = "okay"; - - pmic: pmic@3c { - compatible = "maxim,max20024"; - reg = <0x3c>; - - interrupts = ; - #interrupt-cells = <2>; - interrupt-controller; - - #gpio-cells = <2>; - gpio-controller; - - pinctrl-names = "default"; - pinctrl-0 = <&max20024_default>; - - max20024_default: pinmux { - gpio0 { - pins = "gpio0"; - function = "gpio"; - }; - - gpio1 { - pins = "gpio1"; - function = "fps-out"; - maxim,active-fps-source = ; - }; - - gpio2 { - pins = "gpio2"; - function = "fps-out"; - maxim,active-fps-source = ; - }; - - gpio3 { - pins = "gpio3"; - function = "fps-out"; - maxim,active-fps-source = ; - }; - - gpio4 { - pins = "gpio4"; - function = "32k-out1"; - drive-push-pull = <1>; - }; - - gpio6 { - pins = "gpio6"; - function = "gpio"; - drive-push-pull = <1>; - }; - - gpio7 { - pins = "gpio7"; - function = "gpio"; - drive-push-pull = <0>; - }; - }; - - fps { - fps0 { - maxim,fps-event-source = ; - maxim,shutdown-fps-time-period-us = <640>; - }; - - fps1 { - maxim,fps-event-source = ; - maxim,shutdown-fps-time-period-us = <640>; - maxim,device-state-on-disabled-event = ; - }; - - fps2 { - maxim,fps-event-source = ; - maxim,shutdown-fps-time-period-us = <640>; - }; - }; - - regulators { - in-sd0-supply = <&vdd_5v0_sys>; - in-sd1-supply = <&vdd_5v0_sys>; - in-sd2-supply = <&vdd_5v0_sys>; - in-sd3-supply = <&vdd_5v0_sys>; - in-sd4-supply = <&vdd_5v0_sys>; - - in-ldo0-1-supply = <&vdd_5v0_sys>; - in-ldo2-supply = <&vdd_5v0_sys>; - in-ldo3-5-supply = <&vdd_5v0_sys>; - in-ldo4-6-supply = <&vdd_5v0_sys>; - in-ldo7-8-supply = <&vdd_1v8ls>; - - vdd_1v0: sd0 { - regulator-name = "VDDIO_SYS_1V0"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_1v8hs: sd1 { - regulator-name = "VDDIO_SYS_1V8HS"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_1v8ls: sd2 { - regulator-name = "VDDIO_SYS_1V8LS"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_1v8ao: sd3 { - regulator-name = "VDDIO_AO_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - sd4 { - regulator-name = "VDD_DDR_1V1"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo0 { - regulator-name = "VDD_RTC"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo2 { - regulator-name = "VDDIO_AO_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_emmc_3v3: ldo3 { - regulator-name = "VDD_EMMC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo5 { - regulator-name = "VDD_USB_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo6 { - regulator-name = "VDD_SDIO_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo7 { - regulator-name = "AVDD_CSI_1V2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - }; - }; - - temperature-sensor@4c { - compatible = "ti,tmp451"; - reg = <0x4c>; - - interrupt-parent = <&gpio>; - interrupts = ; - vcc-supply = <&vdd_1v8ls>; - - #thermal-sensor-cells = <1>; - }; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - vdd_5v0_sys: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - - regulator-name = "VIN_SYS_5V0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_hdmi: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - - regulator-name = "VDD_5V0_HDMI_CON"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA194_MAIN_GPIO(A, 3) GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vdd_3v3_pcie: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - - regulator-name = "PEX_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio TEGRA194_MAIN_GPIO(Z, 2) GPIO_ACTIVE_HIGH>; - regulator-boot-on; - enable-active-high; - }; - - vdd_12v_pcie: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - - regulator-name = "VDD_12V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - gpio = <&gpio TEGRA194_MAIN_GPIO(A, 1) GPIO_ACTIVE_HIGH>; - regulator-boot-on; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/nvidia/tegra194-p2972-0000.dts b/sys/gnu/dts/arm64/nvidia/tegra194-p2972-0000.dts deleted file mode 100644 index 985e7d84f16..00000000000 --- a/sys/gnu/dts/arm64/nvidia/tegra194-p2972-0000.dts +++ /dev/null @@ -1,254 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include -#include - -#include "tegra194-p2888.dtsi" - -/ { - model = "NVIDIA Jetson AGX Xavier Developer Kit"; - compatible = "nvidia,p2972-0000", "nvidia,tegra194"; - - cbb@0 { - aconnect@2900000 { - status = "okay"; - - dma-controller@2930000 { - status = "okay"; - }; - - interrupt-controller@2a40000 { - status = "okay"; - }; - }; - - ddc: i2c@31c0000 { - status = "okay"; - }; - - /* SDMMC1 (SD/MMC) */ - sdhci@3400000 { - status = "okay"; - }; - - hda@3510000 { - nvidia,model = "jetson-xavier-hda"; - status = "okay"; - }; - - pwm@c340000 { - status = "okay"; - }; - - host1x@13e00000 { - display-hub@15200000 { - status = "okay"; - }; - - dpaux@155c0000 { - status = "okay"; - }; - - dpaux@155d0000 { - status = "okay"; - }; - - dpaux@155e0000 { - status = "okay"; - }; - - /* DP0 */ - sor@15b00000 { - status = "okay"; - - avdd-io-hdmi-dp-supply = <&vdd_1v0>; - vdd-hdmi-dp-pll-supply = <&vdd_1v8hs>; - - nvidia,dpaux = <&dpaux0>; - }; - - /* DP1 */ - sor@15b40000 { - status = "okay"; - - avdd-io-hdmi-dp-supply = <&vdd_1v0>; - vdd-hdmi-dp-pll-supply = <&vdd_1v8hs>; - - nvidia,dpaux = <&dpaux1>; - }; - - /* HDMI */ - sor@15b80000 { - status = "okay"; - - avdd-io-supply = <&vdd_1v0>; - vdd-pll-supply = <&vdd_1v8hs>; - hdmi-supply = <&vdd_hdmi>; - - nvidia,ddc-i2c-bus = <&ddc>; - nvidia,hpd-gpio = <&gpio TEGRA194_MAIN_GPIO(M, 2) - GPIO_ACTIVE_LOW>; - }; - }; - }; - - pcie@14100000 { - status = "okay"; - - vddio-pex-ctl-supply = <&vdd_1v8ao>; - - phys = <&p2u_hsio_0>; - phy-names = "p2u-0"; - }; - - pcie@14140000 { - status = "okay"; - - vddio-pex-ctl-supply = <&vdd_1v8ao>; - - phys = <&p2u_hsio_7>; - phy-names = "p2u-0"; - }; - - pcie@14180000 { - status = "okay"; - - vddio-pex-ctl-supply = <&vdd_1v8ao>; - - phys = <&p2u_hsio_2>, <&p2u_hsio_3>, <&p2u_hsio_4>, - <&p2u_hsio_5>; - phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3"; - }; - - pcie@141a0000 { - status = "okay"; - - vddio-pex-ctl-supply = <&vdd_1v8ao>; - vpcie3v3-supply = <&vdd_3v3_pcie>; - vpcie12v-supply = <&vdd_12v_pcie>; - - phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>, - <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>, - <&p2u_nvhs_6>, <&p2u_nvhs_7>; - - phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4", - "p2u-5", "p2u-6", "p2u-7"; - }; - - fan: fan { - compatible = "pwm-fan"; - pwms = <&pwm4 0 45334>; - - cooling-levels = <0 64 128 255>; - #cooling-cells = <2>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - force-recovery { - label = "Force Recovery"; - gpios = <&gpio TEGRA194_MAIN_GPIO(G, 0) - GPIO_ACTIVE_LOW>; - linux,input-type = ; - linux,code = ; - debounce-interval = <10>; - }; - - power { - label = "Power"; - gpios = <&gpio_aon TEGRA194_AON_GPIO(EE, 4) - GPIO_ACTIVE_LOW>; - linux,input-type = ; - linux,code = ; - debounce-interval = <10>; - wakeup-event-action = ; - wakeup-source; - }; - }; - - thermal-zones { - cpu { - polling-delay = <0>; - polling-delay-passive = <500>; - status = "okay"; - - trips { - cpu_trip_critical: critical { - temperature = <96500>; - hysteresis = <0>; - type = "critical"; - }; - - cpu_trip_hot: hot { - temperature = <70000>; - hysteresis = <2000>; - type = "hot"; - }; - - cpu_trip_active: active { - temperature = <50000>; - hysteresis = <2000>; - type = "active"; - }; - - cpu_trip_passive: passive { - temperature = <30000>; - hysteresis = <2000>; - type = "passive"; - }; - }; - - cooling-maps { - cpu-critical { - cooling-device = <&fan 3 3>; - trip = <&cpu_trip_critical>; - }; - - cpu-hot { - cooling-device = <&fan 2 2>; - trip = <&cpu_trip_hot>; - }; - - cpu-active { - cooling-device = <&fan 1 1>; - trip = <&cpu_trip_active>; - }; - - cpu-passive { - cooling-device = <&fan 0 0>; - trip = <&cpu_trip_passive>; - }; - }; - }; - - gpu { - polling-delay = <0>; - polling-delay-passive = <500>; - status = "okay"; - - trips { - gpu_alert0: critical { - temperature = <99000>; - hysteresis = <0>; - type = "critical"; - }; - }; - }; - - aux { - polling-delay = <0>; - polling-delay-passive = <500>; - status = "okay"; - - trips { - aux_alert0: critical { - temperature = <90000>; - hysteresis = <0>; - type = "critical"; - }; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/nvidia/tegra194.dtsi b/sys/gnu/dts/arm64/nvidia/tegra194.dtsi deleted file mode 100644 index ccac43be12a..00000000000 --- a/sys/gnu/dts/arm64/nvidia/tegra194.dtsi +++ /dev/null @@ -1,1785 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/ { - compatible = "nvidia,tegra194"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - /* control backbone */ - cbb@0 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x0 0x40000000>; - - misc@100000 { - compatible = "nvidia,tegra194-misc"; - reg = <0x00100000 0xf000>, - <0x0010f000 0x1000>; - }; - - gpio: gpio@2200000 { - compatible = "nvidia,tegra194-gpio"; - reg-names = "security", "gpio"; - reg = <0x2200000 0x10000>, - <0x2210000 0x10000>; - interrupts = , - , - , - , - , - ; - #interrupt-cells = <2>; - interrupt-controller; - #gpio-cells = <2>; - gpio-controller; - }; - - ethernet@2490000 { - compatible = "nvidia,tegra194-eqos", - "nvidia,tegra186-eqos", - "snps,dwc-qos-ethernet-4.10"; - reg = <0x02490000 0x10000>; - interrupts = ; - clocks = <&bpmp TEGRA194_CLK_AXI_CBB>, - <&bpmp TEGRA194_CLK_EQOS_AXI>, - <&bpmp TEGRA194_CLK_EQOS_RX>, - <&bpmp TEGRA194_CLK_EQOS_TX>, - <&bpmp TEGRA194_CLK_EQOS_PTP_REF>; - clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; - resets = <&bpmp TEGRA194_RESET_EQOS>; - reset-names = "eqos"; - status = "disabled"; - - snps,write-requests = <1>; - snps,read-requests = <3>; - snps,burst-map = <0x7>; - snps,txpbl = <16>; - snps,rxpbl = <8>; - }; - - aconnect@2900000 { - compatible = "nvidia,tegra194-aconnect", - "nvidia,tegra210-aconnect"; - clocks = <&bpmp TEGRA194_CLK_APE>, - <&bpmp TEGRA194_CLK_APB2APE>; - clock-names = "ape", "apb2ape"; - power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x02900000 0x02900000 0x200000>; - status = "disabled"; - - dma-controller@2930000 { - compatible = "nvidia,tegra194-adma", - "nvidia,tegra186-adma"; - reg = <0x02930000 0x20000>; - interrupt-parent = <&agic>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - #dma-cells = <1>; - clocks = <&bpmp TEGRA194_CLK_AHUB>; - clock-names = "d_audio"; - status = "disabled"; - }; - - agic: interrupt-controller@2a40000 { - compatible = "nvidia,tegra194-agic", - "nvidia,tegra210-agic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x02a41000 0x1000>, - <0x02a42000 0x2000>; - interrupts = ; - clocks = <&bpmp TEGRA194_CLK_APE>; - clock-names = "clk"; - status = "disabled"; - }; - }; - - pinmux: pinmux@2430000 { - compatible = "nvidia,tegra194-pinmux"; - reg = <0x2430000 0x17000 - 0xc300000 0x4000>; - - status = "okay"; - - pex_rst_c5_out_state: pex_rst_c5_out { - pex_rst { - nvidia,pins = "pex_l5_rst_n_pgg1"; - nvidia,schmitt = ; - nvidia,lpdr = ; - nvidia,enable-input = ; - nvidia,io-high-voltage = ; - nvidia,tristate = ; - nvidia,pull = ; - }; - }; - - clkreq_c5_bi_dir_state: clkreq_c5_bi_dir { - clkreq { - nvidia,pins = "pex_l5_clkreq_n_pgg0"; - nvidia,schmitt = ; - nvidia,lpdr = ; - nvidia,enable-input = ; - nvidia,io-high-voltage = ; - nvidia,tristate = ; - nvidia,pull = ; - }; - }; - }; - - mc: memory-controller@2c00000 { - compatible = "nvidia,tegra194-mc"; - reg = <0x02c00000 0x100000>, - <0x02b80000 0x040000>, - <0x01700000 0x100000>; - status = "disabled"; - - #address-cells = <2>; - #size-cells = <2>; - - ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>, - <0x02b80000 0x0 0x02b80000 0x0 0x040000>, - <0x02c00000 0x0 0x02c00000 0x0 0x100000>; - - /* - * Bit 39 of addresses passing through the memory - * controller selects the XBAR format used when memory - * is accessed. This is used to transparently access - * memory in the XBAR format used by the discrete GPU - * (bit 39 set) or Tegra (bit 39 clear). - * - * As a consequence, the operating system must ensure - * that bit 39 is never used implicitly, for example - * via an I/O virtual address mapping of an IOMMU. If - * devices require access to the XBAR switch, their - * drivers must set this bit explicitly. - * - * Limit the DMA range for memory clients to [38:0]. - */ - dma-ranges = <0x0 0x0 0x0 0x80 0x0>; - - emc: external-memory-controller@2c60000 { - compatible = "nvidia,tegra194-emc"; - reg = <0x0 0x02c60000 0x0 0x90000>, - <0x0 0x01780000 0x0 0x80000>; - clocks = <&bpmp TEGRA194_CLK_EMC>; - clock-names = "emc"; - - nvidia,bpmp = <&bpmp>; - }; - }; - - uarta: serial@3100000 { - compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; - reg = <0x03100000 0x40>; - reg-shift = <2>; - interrupts = ; - clocks = <&bpmp TEGRA194_CLK_UARTA>; - clock-names = "serial"; - resets = <&bpmp TEGRA194_RESET_UARTA>; - reset-names = "serial"; - status = "disabled"; - }; - - uartb: serial@3110000 { - compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; - reg = <0x03110000 0x40>; - reg-shift = <2>; - interrupts = ; - clocks = <&bpmp TEGRA194_CLK_UARTB>; - clock-names = "serial"; - resets = <&bpmp TEGRA194_RESET_UARTB>; - reset-names = "serial"; - status = "disabled"; - }; - - uartd: serial@3130000 { - compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; - reg = <0x03130000 0x40>; - reg-shift = <2>; - interrupts = ; - clocks = <&bpmp TEGRA194_CLK_UARTD>; - clock-names = "serial"; - resets = <&bpmp TEGRA194_RESET_UARTD>; - reset-names = "serial"; - status = "disabled"; - }; - - uarte: serial@3140000 { - compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; - reg = <0x03140000 0x40>; - reg-shift = <2>; - interrupts = ; - clocks = <&bpmp TEGRA194_CLK_UARTE>; - clock-names = "serial"; - resets = <&bpmp TEGRA194_RESET_UARTE>; - reset-names = "serial"; - status = "disabled"; - }; - - uartf: serial@3150000 { - compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; - reg = <0x03150000 0x40>; - reg-shift = <2>; - interrupts = ; - clocks = <&bpmp TEGRA194_CLK_UARTF>; - clock-names = "serial"; - resets = <&bpmp TEGRA194_RESET_UARTF>; - reset-names = "serial"; - status = "disabled"; - }; - - gen1_i2c: i2c@3160000 { - compatible = "nvidia,tegra194-i2c"; - reg = <0x03160000 0x10000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&bpmp TEGRA194_CLK_I2C1>; - clock-names = "div-clk"; - resets = <&bpmp TEGRA194_RESET_I2C1>; - reset-names = "i2c"; - status = "disabled"; - }; - - uarth: serial@3170000 { - compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; - reg = <0x03170000 0x40>; - reg-shift = <2>; - interrupts = ; - clocks = <&bpmp TEGRA194_CLK_UARTH>; - clock-names = "serial"; - resets = <&bpmp TEGRA194_RESET_UARTH>; - reset-names = "serial"; - status = "disabled"; - }; - - cam_i2c: i2c@3180000 { - compatible = "nvidia,tegra194-i2c"; - reg = <0x03180000 0x10000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&bpmp TEGRA194_CLK_I2C3>; - clock-names = "div-clk"; - resets = <&bpmp TEGRA194_RESET_I2C3>; - reset-names = "i2c"; - status = "disabled"; - }; - - /* shares pads with dpaux1 */ - dp_aux_ch1_i2c: i2c@3190000 { - compatible = "nvidia,tegra194-i2c"; - reg = <0x03190000 0x10000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&bpmp TEGRA194_CLK_I2C4>; - clock-names = "div-clk"; - resets = <&bpmp TEGRA194_RESET_I2C4>; - reset-names = "i2c"; - status = "disabled"; - }; - - /* shares pads with dpaux0 */ - dp_aux_ch0_i2c: i2c@31b0000 { - compatible = "nvidia,tegra194-i2c"; - reg = <0x031b0000 0x10000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&bpmp TEGRA194_CLK_I2C6>; - clock-names = "div-clk"; - resets = <&bpmp TEGRA194_RESET_I2C6>; - reset-names = "i2c"; - status = "disabled"; - }; - - gen7_i2c: i2c@31c0000 { - compatible = "nvidia,tegra194-i2c"; - reg = <0x031c0000 0x10000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&bpmp TEGRA194_CLK_I2C7>; - clock-names = "div-clk"; - resets = <&bpmp TEGRA194_RESET_I2C7>; - reset-names = "i2c"; - status = "disabled"; - }; - - gen9_i2c: i2c@31e0000 { - compatible = "nvidia,tegra194-i2c"; - reg = <0x031e0000 0x10000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&bpmp TEGRA194_CLK_I2C9>; - clock-names = "div-clk"; - resets = <&bpmp TEGRA194_RESET_I2C9>; - reset-names = "i2c"; - status = "disabled"; - }; - - pwm1: pwm@3280000 { - compatible = "nvidia,tegra194-pwm", - "nvidia,tegra186-pwm"; - reg = <0x3280000 0x10000>; - clocks = <&bpmp TEGRA194_CLK_PWM1>; - clock-names = "pwm"; - resets = <&bpmp TEGRA194_RESET_PWM1>; - reset-names = "pwm"; - status = "disabled"; - #pwm-cells = <2>; - }; - - pwm2: pwm@3290000 { - compatible = "nvidia,tegra194-pwm", - "nvidia,tegra186-pwm"; - reg = <0x3290000 0x10000>; - clocks = <&bpmp TEGRA194_CLK_PWM2>; - clock-names = "pwm"; - resets = <&bpmp TEGRA194_RESET_PWM2>; - reset-names = "pwm"; - status = "disabled"; - #pwm-cells = <2>; - }; - - pwm3: pwm@32a0000 { - compatible = "nvidia,tegra194-pwm", - "nvidia,tegra186-pwm"; - reg = <0x32a0000 0x10000>; - clocks = <&bpmp TEGRA194_CLK_PWM3>; - clock-names = "pwm"; - resets = <&bpmp TEGRA194_RESET_PWM3>; - reset-names = "pwm"; - status = "disabled"; - #pwm-cells = <2>; - }; - - pwm5: pwm@32c0000 { - compatible = "nvidia,tegra194-pwm", - "nvidia,tegra186-pwm"; - reg = <0x32c0000 0x10000>; - clocks = <&bpmp TEGRA194_CLK_PWM5>; - clock-names = "pwm"; - resets = <&bpmp TEGRA194_RESET_PWM5>; - reset-names = "pwm"; - status = "disabled"; - #pwm-cells = <2>; - }; - - pwm6: pwm@32d0000 { - compatible = "nvidia,tegra194-pwm", - "nvidia,tegra186-pwm"; - reg = <0x32d0000 0x10000>; - clocks = <&bpmp TEGRA194_CLK_PWM6>; - clock-names = "pwm"; - resets = <&bpmp TEGRA194_RESET_PWM6>; - reset-names = "pwm"; - status = "disabled"; - #pwm-cells = <2>; - }; - - pwm7: pwm@32e0000 { - compatible = "nvidia,tegra194-pwm", - "nvidia,tegra186-pwm"; - reg = <0x32e0000 0x10000>; - clocks = <&bpmp TEGRA194_CLK_PWM7>; - clock-names = "pwm"; - resets = <&bpmp TEGRA194_RESET_PWM7>; - reset-names = "pwm"; - status = "disabled"; - #pwm-cells = <2>; - }; - - pwm8: pwm@32f0000 { - compatible = "nvidia,tegra194-pwm", - "nvidia,tegra186-pwm"; - reg = <0x32f0000 0x10000>; - clocks = <&bpmp TEGRA194_CLK_PWM8>; - clock-names = "pwm"; - resets = <&bpmp TEGRA194_RESET_PWM8>; - reset-names = "pwm"; - status = "disabled"; - #pwm-cells = <2>; - }; - - sdmmc1: sdhci@3400000 { - compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci"; - reg = <0x03400000 0x10000>; - interrupts = ; - clocks = <&bpmp TEGRA194_CLK_SDMMC1>; - clock-names = "sdhci"; - resets = <&bpmp TEGRA194_RESET_SDMMC1>; - reset-names = "sdhci"; - nvidia,pad-autocal-pull-up-offset-3v3-timeout = - <0x07>; - nvidia,pad-autocal-pull-down-offset-3v3-timeout = - <0x07>; - nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; - nvidia,pad-autocal-pull-down-offset-1v8-timeout = - <0x07>; - nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; - nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; - nvidia,default-tap = <0x9>; - nvidia,default-trim = <0x5>; - status = "disabled"; - }; - - sdmmc3: sdhci@3440000 { - compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci"; - reg = <0x03440000 0x10000>; - interrupts = ; - clocks = <&bpmp TEGRA194_CLK_SDMMC3>; - clock-names = "sdhci"; - resets = <&bpmp TEGRA194_RESET_SDMMC3>; - reset-names = "sdhci"; - nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; - nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; - nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; - nvidia,pad-autocal-pull-down-offset-3v3-timeout = - <0x07>; - nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; - nvidia,pad-autocal-pull-down-offset-1v8-timeout = - <0x07>; - nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; - nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; - nvidia,default-tap = <0x9>; - nvidia,default-trim = <0x5>; - status = "disabled"; - }; - - sdmmc4: sdhci@3460000 { - compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci"; - reg = <0x03460000 0x10000>; - interrupts = ; - clocks = <&bpmp TEGRA194_CLK_SDMMC4>; - clock-names = "sdhci"; - assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>, - <&bpmp TEGRA194_CLK_PLLC4>; - assigned-clock-parents = - <&bpmp TEGRA194_CLK_PLLC4>; - resets = <&bpmp TEGRA194_RESET_SDMMC4>; - reset-names = "sdhci"; - nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; - nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; - nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; - nvidia,pad-autocal-pull-down-offset-1v8-timeout = - <0x0a>; - nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; - nvidia,pad-autocal-pull-down-offset-3v3-timeout = - <0x0a>; - nvidia,default-tap = <0x8>; - nvidia,default-trim = <0x14>; - nvidia,dqs-trim = <40>; - supports-cqe; - status = "disabled"; - }; - - hda@3510000 { - compatible = "nvidia,tegra194-hda", "nvidia,tegra30-hda"; - reg = <0x3510000 0x10000>; - interrupts = ; - clocks = <&bpmp TEGRA194_CLK_HDA>, - <&bpmp TEGRA194_CLK_HDA2CODEC_2X>, - <&bpmp TEGRA194_CLK_HDA2HDMICODEC>; - clock-names = "hda", "hda2codec_2x", "hda2hdmi"; - resets = <&bpmp TEGRA194_RESET_HDA>, - <&bpmp TEGRA194_RESET_HDA2CODEC_2X>, - <&bpmp TEGRA194_RESET_HDA2HDMICODEC>; - reset-names = "hda", "hda2codec_2x", "hda2hdmi"; - power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; - status = "disabled"; - }; - - fuse@3820000 { - compatible = "nvidia,tegra194-efuse"; - reg = <0x03820000 0x10000>; - clocks = <&bpmp TEGRA194_CLK_FUSE>; - clock-names = "fuse"; - }; - - gic: interrupt-controller@3881000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x03881000 0x1000>, - <0x03882000 0x2000>, - <0x03884000 0x2000>, - <0x03886000 0x2000>; - interrupts = ; - interrupt-parent = <&gic>; - }; - - cec@3960000 { - compatible = "nvidia,tegra194-cec"; - reg = <0x03960000 0x10000>; - interrupts = ; - clocks = <&bpmp TEGRA194_CLK_CEC>; - clock-names = "cec"; - status = "disabled"; - }; - - hsp_top0: hsp@3c00000 { - compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"; - reg = <0x03c00000 0xa0000>; - interrupts = , - , - , - , - , - , - , - , - ; - interrupt-names = "doorbell", "shared0", "shared1", "shared2", - "shared3", "shared4", "shared5", "shared6", - "shared7"; - #mbox-cells = <2>; - }; - - p2u_hsio_0: phy@3e10000 { - compatible = "nvidia,tegra194-p2u"; - reg = <0x03e10000 0x10000>; - reg-names = "ctl"; - - #phy-cells = <0>; - }; - - p2u_hsio_1: phy@3e20000 { - compatible = "nvidia,tegra194-p2u"; - reg = <0x03e20000 0x10000>; - reg-names = "ctl"; - - #phy-cells = <0>; - }; - - p2u_hsio_2: phy@3e30000 { - compatible = "nvidia,tegra194-p2u"; - reg = <0x03e30000 0x10000>; - reg-names = "ctl"; - - #phy-cells = <0>; - }; - - p2u_hsio_3: phy@3e40000 { - compatible = "nvidia,tegra194-p2u"; - reg = <0x03e40000 0x10000>; - reg-names = "ctl"; - - #phy-cells = <0>; - }; - - p2u_hsio_4: phy@3e50000 { - compatible = "nvidia,tegra194-p2u"; - reg = <0x03e50000 0x10000>; - reg-names = "ctl"; - - #phy-cells = <0>; - }; - - p2u_hsio_5: phy@3e60000 { - compatible = "nvidia,tegra194-p2u"; - reg = <0x03e60000 0x10000>; - reg-names = "ctl"; - - #phy-cells = <0>; - }; - - p2u_hsio_6: phy@3e70000 { - compatible = "nvidia,tegra194-p2u"; - reg = <0x03e70000 0x10000>; - reg-names = "ctl"; - - #phy-cells = <0>; - }; - - p2u_hsio_7: phy@3e80000 { - compatible = "nvidia,tegra194-p2u"; - reg = <0x03e80000 0x10000>; - reg-names = "ctl"; - - #phy-cells = <0>; - }; - - p2u_hsio_8: phy@3e90000 { - compatible = "nvidia,tegra194-p2u"; - reg = <0x03e90000 0x10000>; - reg-names = "ctl"; - - #phy-cells = <0>; - }; - - p2u_hsio_9: phy@3ea0000 { - compatible = "nvidia,tegra194-p2u"; - reg = <0x03ea0000 0x10000>; - reg-names = "ctl"; - - #phy-cells = <0>; - }; - - p2u_nvhs_0: phy@3eb0000 { - compatible = "nvidia,tegra194-p2u"; - reg = <0x03eb0000 0x10000>; - reg-names = "ctl"; - - #phy-cells = <0>; - }; - - p2u_nvhs_1: phy@3ec0000 { - compatible = "nvidia,tegra194-p2u"; - reg = <0x03ec0000 0x10000>; - reg-names = "ctl"; - - #phy-cells = <0>; - }; - - p2u_nvhs_2: phy@3ed0000 { - compatible = "nvidia,tegra194-p2u"; - reg = <0x03ed0000 0x10000>; - reg-names = "ctl"; - - #phy-cells = <0>; - }; - - p2u_nvhs_3: phy@3ee0000 { - compatible = "nvidia,tegra194-p2u"; - reg = <0x03ee0000 0x10000>; - reg-names = "ctl"; - - #phy-cells = <0>; - }; - - p2u_nvhs_4: phy@3ef0000 { - compatible = "nvidia,tegra194-p2u"; - reg = <0x03ef0000 0x10000>; - reg-names = "ctl"; - - #phy-cells = <0>; - }; - - p2u_nvhs_5: phy@3f00000 { - compatible = "nvidia,tegra194-p2u"; - reg = <0x03f00000 0x10000>; - reg-names = "ctl"; - - #phy-cells = <0>; - }; - - p2u_nvhs_6: phy@3f10000 { - compatible = "nvidia,tegra194-p2u"; - reg = <0x03f10000 0x10000>; - reg-names = "ctl"; - - #phy-cells = <0>; - }; - - p2u_nvhs_7: phy@3f20000 { - compatible = "nvidia,tegra194-p2u"; - reg = <0x03f20000 0x10000>; - reg-names = "ctl"; - - #phy-cells = <0>; - }; - - p2u_hsio_10: phy@3f30000 { - compatible = "nvidia,tegra194-p2u"; - reg = <0x03f30000 0x10000>; - reg-names = "ctl"; - - #phy-cells = <0>; - }; - - p2u_hsio_11: phy@3f40000 { - compatible = "nvidia,tegra194-p2u"; - reg = <0x03f40000 0x10000>; - reg-names = "ctl"; - - #phy-cells = <0>; - }; - - hsp_aon: hsp@c150000 { - compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"; - reg = <0x0c150000 0xa0000>; - interrupts = , - , - , - ; - /* - * Shared interrupt 0 is routed only to AON/SPE, so - * we only have 4 shared interrupts for the CCPLEX. - */ - interrupt-names = "shared1", "shared2", "shared3", "shared4"; - #mbox-cells = <2>; - }; - - gen2_i2c: i2c@c240000 { - compatible = "nvidia,tegra194-i2c"; - reg = <0x0c240000 0x10000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&bpmp TEGRA194_CLK_I2C2>; - clock-names = "div-clk"; - resets = <&bpmp TEGRA194_RESET_I2C2>; - reset-names = "i2c"; - status = "disabled"; - }; - - gen8_i2c: i2c@c250000 { - compatible = "nvidia,tegra194-i2c"; - reg = <0x0c250000 0x10000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&bpmp TEGRA194_CLK_I2C8>; - clock-names = "div-clk"; - resets = <&bpmp TEGRA194_RESET_I2C8>; - reset-names = "i2c"; - status = "disabled"; - }; - - uartc: serial@c280000 { - compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; - reg = <0x0c280000 0x40>; - reg-shift = <2>; - interrupts = ; - clocks = <&bpmp TEGRA194_CLK_UARTC>; - clock-names = "serial"; - resets = <&bpmp TEGRA194_RESET_UARTC>; - reset-names = "serial"; - status = "disabled"; - }; - - uartg: serial@c290000 { - compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; - reg = <0x0c290000 0x40>; - reg-shift = <2>; - interrupts = ; - clocks = <&bpmp TEGRA194_CLK_UARTG>; - clock-names = "serial"; - resets = <&bpmp TEGRA194_RESET_UARTG>; - reset-names = "serial"; - status = "disabled"; - }; - - rtc: rtc@c2a0000 { - compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc"; - reg = <0x0c2a0000 0x10000>; - interrupt-parent = <&pmc>; - interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&bpmp TEGRA194_CLK_CLK_32K>; - clock-names = "rtc"; - status = "disabled"; - }; - - gpio_aon: gpio@c2f0000 { - compatible = "nvidia,tegra194-gpio-aon"; - reg-names = "security", "gpio"; - reg = <0xc2f0000 0x1000>, - <0xc2f1000 0x1000>; - interrupts = , - , - , - ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - pwm4: pwm@c340000 { - compatible = "nvidia,tegra194-pwm", - "nvidia,tegra186-pwm"; - reg = <0xc340000 0x10000>; - clocks = <&bpmp TEGRA194_CLK_PWM4>; - clock-names = "pwm"; - resets = <&bpmp TEGRA194_RESET_PWM4>; - reset-names = "pwm"; - status = "disabled"; - #pwm-cells = <2>; - }; - - pmc: pmc@c360000 { - compatible = "nvidia,tegra194-pmc"; - reg = <0x0c360000 0x10000>, - <0x0c370000 0x10000>, - <0x0c380000 0x10000>, - <0x0c390000 0x10000>, - <0x0c3a0000 0x10000>; - reg-names = "pmc", "wake", "aotag", "scratch", "misc"; - - #interrupt-cells = <2>; - interrupt-controller; - }; - - host1x@13e00000 { - compatible = "nvidia,tegra194-host1x", "simple-bus"; - reg = <0x13e00000 0x10000>, - <0x13e10000 0x10000>; - reg-names = "hypervisor", "vm"; - interrupts = , - ; - clocks = <&bpmp TEGRA194_CLK_HOST1X>; - clock-names = "host1x"; - resets = <&bpmp TEGRA194_RESET_HOST1X>; - reset-names = "host1x"; - - #address-cells = <1>; - #size-cells = <1>; - - ranges = <0x15000000 0x15000000 0x01000000>; - - display-hub@15200000 { - compatible = "nvidia,tegra194-display", "simple-bus"; - reg = <0x15200000 0x00040000>; - resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>, - <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>, - <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>, - <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>, - <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>, - <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>, - <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>; - reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", - "wgrp3", "wgrp4", "wgrp5"; - clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>, - <&bpmp TEGRA194_CLK_NVDISPLAYHUB>; - clock-names = "disp", "hub"; - status = "disabled"; - - power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; - - #address-cells = <1>; - #size-cells = <1>; - - ranges = <0x15200000 0x15200000 0x40000>; - - display@15200000 { - compatible = "nvidia,tegra194-dc"; - reg = <0x15200000 0x10000>; - interrupts = ; - clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>; - clock-names = "dc"; - resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>; - reset-names = "dc"; - - power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; - - nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; - nvidia,head = <0>; - }; - - display@15210000 { - compatible = "nvidia,tegra194-dc"; - reg = <0x15210000 0x10000>; - interrupts = ; - clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>; - clock-names = "dc"; - resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>; - reset-names = "dc"; - - power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>; - - nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; - nvidia,head = <1>; - }; - - display@15220000 { - compatible = "nvidia,tegra194-dc"; - reg = <0x15220000 0x10000>; - interrupts = ; - clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>; - clock-names = "dc"; - resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>; - reset-names = "dc"; - - power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; - - nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; - nvidia,head = <2>; - }; - - display@15230000 { - compatible = "nvidia,tegra194-dc"; - reg = <0x15230000 0x10000>; - interrupts = ; - clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>; - clock-names = "dc"; - resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>; - reset-names = "dc"; - - power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; - - nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; - nvidia,head = <3>; - }; - }; - - vic@15340000 { - compatible = "nvidia,tegra194-vic"; - reg = <0x15340000 0x00040000>; - interrupts = ; - clocks = <&bpmp TEGRA194_CLK_VIC>; - clock-names = "vic"; - resets = <&bpmp TEGRA194_RESET_VIC>; - reset-names = "vic"; - - power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>; - }; - - dpaux0: dpaux@155c0000 { - compatible = "nvidia,tegra194-dpaux"; - reg = <0x155c0000 0x10000>; - interrupts = ; - clocks = <&bpmp TEGRA194_CLK_DPAUX>, - <&bpmp TEGRA194_CLK_PLLDP>; - clock-names = "dpaux", "parent"; - resets = <&bpmp TEGRA194_RESET_DPAUX>; - reset-names = "dpaux"; - status = "disabled"; - - power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; - - state_dpaux0_aux: pinmux-aux { - groups = "dpaux-io"; - function = "aux"; - }; - - state_dpaux0_i2c: pinmux-i2c { - groups = "dpaux-io"; - function = "i2c"; - }; - - state_dpaux0_off: pinmux-off { - groups = "dpaux-io"; - function = "off"; - }; - - i2c-bus { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - dpaux1: dpaux@155d0000 { - compatible = "nvidia,tegra194-dpaux"; - reg = <0x155d0000 0x10000>; - interrupts = ; - clocks = <&bpmp TEGRA194_CLK_DPAUX1>, - <&bpmp TEGRA194_CLK_PLLDP>; - clock-names = "dpaux", "parent"; - resets = <&bpmp TEGRA194_RESET_DPAUX1>; - reset-names = "dpaux"; - status = "disabled"; - - power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; - - state_dpaux1_aux: pinmux-aux { - groups = "dpaux-io"; - function = "aux"; - }; - - state_dpaux1_i2c: pinmux-i2c { - groups = "dpaux-io"; - function = "i2c"; - }; - - state_dpaux1_off: pinmux-off { - groups = "dpaux-io"; - function = "off"; - }; - - i2c-bus { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - dpaux2: dpaux@155e0000 { - compatible = "nvidia,tegra194-dpaux"; - reg = <0x155e0000 0x10000>; - interrupts = ; - clocks = <&bpmp TEGRA194_CLK_DPAUX2>, - <&bpmp TEGRA194_CLK_PLLDP>; - clock-names = "dpaux", "parent"; - resets = <&bpmp TEGRA194_RESET_DPAUX2>; - reset-names = "dpaux"; - status = "disabled"; - - power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; - - state_dpaux2_aux: pinmux-aux { - groups = "dpaux-io"; - function = "aux"; - }; - - state_dpaux2_i2c: pinmux-i2c { - groups = "dpaux-io"; - function = "i2c"; - }; - - state_dpaux2_off: pinmux-off { - groups = "dpaux-io"; - function = "off"; - }; - - i2c-bus { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - dpaux3: dpaux@155f0000 { - compatible = "nvidia,tegra194-dpaux"; - reg = <0x155f0000 0x10000>; - interrupts = ; - clocks = <&bpmp TEGRA194_CLK_DPAUX3>, - <&bpmp TEGRA194_CLK_PLLDP>; - clock-names = "dpaux", "parent"; - resets = <&bpmp TEGRA194_RESET_DPAUX3>; - reset-names = "dpaux"; - status = "disabled"; - - power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; - - state_dpaux3_aux: pinmux-aux { - groups = "dpaux-io"; - function = "aux"; - }; - - state_dpaux3_i2c: pinmux-i2c { - groups = "dpaux-io"; - function = "i2c"; - }; - - state_dpaux3_off: pinmux-off { - groups = "dpaux-io"; - function = "off"; - }; - - i2c-bus { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - sor0: sor@15b00000 { - compatible = "nvidia,tegra194-sor"; - reg = <0x15b00000 0x40000>; - interrupts = ; - clocks = <&bpmp TEGRA194_CLK_SOR0_REF>, - <&bpmp TEGRA194_CLK_SOR0_OUT>, - <&bpmp TEGRA194_CLK_PLLD>, - <&bpmp TEGRA194_CLK_PLLDP>, - <&bpmp TEGRA194_CLK_SOR_SAFE>, - <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>; - clock-names = "sor", "out", "parent", "dp", "safe", - "pad"; - resets = <&bpmp TEGRA194_RESET_SOR0>; - reset-names = "sor"; - pinctrl-0 = <&state_dpaux0_aux>; - pinctrl-1 = <&state_dpaux0_i2c>; - pinctrl-2 = <&state_dpaux0_off>; - pinctrl-names = "aux", "i2c", "off"; - status = "disabled"; - - power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; - nvidia,interface = <0>; - }; - - sor1: sor@15b40000 { - compatible = "nvidia,tegra194-sor"; - reg = <0x15b40000 0x40000>; - interrupts = ; - clocks = <&bpmp TEGRA194_CLK_SOR1_REF>, - <&bpmp TEGRA194_CLK_SOR1_OUT>, - <&bpmp TEGRA194_CLK_PLLD2>, - <&bpmp TEGRA194_CLK_PLLDP>, - <&bpmp TEGRA194_CLK_SOR_SAFE>, - <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>; - clock-names = "sor", "out", "parent", "dp", "safe", - "pad"; - resets = <&bpmp TEGRA194_RESET_SOR1>; - reset-names = "sor"; - pinctrl-0 = <&state_dpaux1_aux>; - pinctrl-1 = <&state_dpaux1_i2c>; - pinctrl-2 = <&state_dpaux1_off>; - pinctrl-names = "aux", "i2c", "off"; - status = "disabled"; - - power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; - nvidia,interface = <1>; - }; - - sor2: sor@15b80000 { - compatible = "nvidia,tegra194-sor"; - reg = <0x15b80000 0x40000>; - interrupts = ; - clocks = <&bpmp TEGRA194_CLK_SOR2_REF>, - <&bpmp TEGRA194_CLK_SOR2_OUT>, - <&bpmp TEGRA194_CLK_PLLD3>, - <&bpmp TEGRA194_CLK_PLLDP>, - <&bpmp TEGRA194_CLK_SOR_SAFE>, - <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>; - clock-names = "sor", "out", "parent", "dp", "safe", - "pad"; - resets = <&bpmp TEGRA194_RESET_SOR2>; - reset-names = "sor"; - pinctrl-0 = <&state_dpaux2_aux>; - pinctrl-1 = <&state_dpaux2_i2c>; - pinctrl-2 = <&state_dpaux2_off>; - pinctrl-names = "aux", "i2c", "off"; - status = "disabled"; - - power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; - nvidia,interface = <2>; - }; - - sor3: sor@15bc0000 { - compatible = "nvidia,tegra194-sor"; - reg = <0x15bc0000 0x40000>; - interrupts = ; - clocks = <&bpmp TEGRA194_CLK_SOR3_REF>, - <&bpmp TEGRA194_CLK_SOR3_OUT>, - <&bpmp TEGRA194_CLK_PLLD4>, - <&bpmp TEGRA194_CLK_PLLDP>, - <&bpmp TEGRA194_CLK_SOR_SAFE>, - <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>; - clock-names = "sor", "out", "parent", "dp", "safe", - "pad"; - resets = <&bpmp TEGRA194_RESET_SOR3>; - reset-names = "sor"; - pinctrl-0 = <&state_dpaux3_aux>; - pinctrl-1 = <&state_dpaux3_i2c>; - pinctrl-2 = <&state_dpaux3_off>; - pinctrl-names = "aux", "i2c", "off"; - status = "disabled"; - - power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; - nvidia,interface = <3>; - }; - }; - }; - - pcie@14100000 { - compatible = "nvidia,tegra194-pcie", "snps,dw-pcie"; - power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; - reg = <0x00 0x14100000 0x0 0x00020000 /* appl registers (128K) */ - 0x00 0x30000000 0x0 0x00040000 /* configuration space (256K) */ - 0x00 0x30040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ - 0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */ - reg-names = "appl", "config", "atu_dma", "dbi"; - - status = "disabled"; - - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - num-lanes = <1>; - num-viewport = <8>; - linux,pci-domain = <1>; - - clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>; - clock-names = "core"; - - resets = <&bpmp TEGRA194_RESET_PEX0_CORE_1_APB>, - <&bpmp TEGRA194_RESET_PEX0_CORE_1>; - reset-names = "apb", "core"; - - interrupts = , /* controller interrupt */ - ; /* MSI interrupt */ - interrupt-names = "intr", "msi"; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; - - nvidia,bpmp = <&bpmp 1>; - - nvidia,aspm-cmrt-us = <60>; - nvidia,aspm-pwr-on-t-us = <20>; - nvidia,aspm-l0s-entrance-latency-us = <3>; - - bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x30100000 0x0 0x30100000 0x0 0x00100000 /* downstream I/O (1MB) */ - 0xc2000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000 /* prefetchable memory (768MB) */ - 0x82000000 0x0 0x40000000 0x12 0x30000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */ - }; - - pcie@14120000 { - compatible = "nvidia,tegra194-pcie", "snps,dw-pcie"; - power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; - reg = <0x00 0x14120000 0x0 0x00020000 /* appl registers (128K) */ - 0x00 0x32000000 0x0 0x00040000 /* configuration space (256K) */ - 0x00 0x32040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ - 0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */ - reg-names = "appl", "config", "atu_dma", "dbi"; - - status = "disabled"; - - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - num-lanes = <1>; - num-viewport = <8>; - linux,pci-domain = <2>; - - clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>; - clock-names = "core"; - - resets = <&bpmp TEGRA194_RESET_PEX0_CORE_2_APB>, - <&bpmp TEGRA194_RESET_PEX0_CORE_2>; - reset-names = "apb", "core"; - - interrupts = , /* controller interrupt */ - ; /* MSI interrupt */ - interrupt-names = "intr", "msi"; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; - - nvidia,bpmp = <&bpmp 2>; - - nvidia,aspm-cmrt-us = <60>; - nvidia,aspm-pwr-on-t-us = <20>; - nvidia,aspm-l0s-entrance-latency-us = <3>; - - bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x32100000 0x0 0x32100000 0x0 0x00100000 /* downstream I/O (1MB) */ - 0xc2000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000 /* prefetchable memory (768MB) */ - 0x82000000 0x0 0x40000000 0x12 0x70000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */ - }; - - pcie@14140000 { - compatible = "nvidia,tegra194-pcie", "snps,dw-pcie"; - power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; - reg = <0x00 0x14140000 0x0 0x00020000 /* appl registers (128K) */ - 0x00 0x34000000 0x0 0x00040000 /* configuration space (256K) */ - 0x00 0x34040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ - 0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */ - reg-names = "appl", "config", "atu_dma", "dbi"; - - status = "disabled"; - - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - num-lanes = <1>; - num-viewport = <8>; - linux,pci-domain = <3>; - - clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>; - clock-names = "core"; - - resets = <&bpmp TEGRA194_RESET_PEX0_CORE_3_APB>, - <&bpmp TEGRA194_RESET_PEX0_CORE_3>; - reset-names = "apb", "core"; - - interrupts = , /* controller interrupt */ - ; /* MSI interrupt */ - interrupt-names = "intr", "msi"; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; - - nvidia,bpmp = <&bpmp 3>; - - nvidia,aspm-cmrt-us = <60>; - nvidia,aspm-pwr-on-t-us = <20>; - nvidia,aspm-l0s-entrance-latency-us = <3>; - - bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x34100000 0x0 0x34100000 0x0 0x00100000 /* downstream I/O (1MB) */ - 0xc2000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000 /* prefetchable memory (768MB) */ - 0x82000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */ - }; - - pcie@14160000 { - compatible = "nvidia,tegra194-pcie", "snps,dw-pcie"; - power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; - reg = <0x00 0x14160000 0x0 0x00020000 /* appl registers (128K) */ - 0x00 0x36000000 0x0 0x00040000 /* configuration space (256K) */ - 0x00 0x36040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ - 0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */ - reg-names = "appl", "config", "atu_dma", "dbi"; - - status = "disabled"; - - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - num-lanes = <4>; - num-viewport = <8>; - linux,pci-domain = <4>; - - clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; - clock-names = "core"; - - resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, - <&bpmp TEGRA194_RESET_PEX0_CORE_4>; - reset-names = "apb", "core"; - - interrupts = , /* controller interrupt */ - ; /* MSI interrupt */ - interrupt-names = "intr", "msi"; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; - - nvidia,bpmp = <&bpmp 4>; - - nvidia,aspm-cmrt-us = <60>; - nvidia,aspm-pwr-on-t-us = <20>; - nvidia,aspm-l0s-entrance-latency-us = <3>; - - bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x36100000 0x0 0x36100000 0x0 0x00100000 /* downstream I/O (1MB) */ - 0xc2000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */ - 0x82000000 0x0 0x40000000 0x17 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */ - }; - - pcie@14180000 { - compatible = "nvidia,tegra194-pcie", "snps,dw-pcie"; - power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; - reg = <0x00 0x14180000 0x0 0x00020000 /* appl registers (128K) */ - 0x00 0x38000000 0x0 0x00040000 /* configuration space (256K) */ - 0x00 0x38040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ - 0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */ - reg-names = "appl", "config", "atu_dma", "dbi"; - - status = "disabled"; - - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - num-lanes = <8>; - num-viewport = <8>; - linux,pci-domain = <0>; - - clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; - clock-names = "core"; - - resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, - <&bpmp TEGRA194_RESET_PEX0_CORE_0>; - reset-names = "apb", "core"; - - interrupts = , /* controller interrupt */ - ; /* MSI interrupt */ - interrupt-names = "intr", "msi"; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; - - nvidia,bpmp = <&bpmp 0>; - - nvidia,aspm-cmrt-us = <60>; - nvidia,aspm-pwr-on-t-us = <20>; - nvidia,aspm-l0s-entrance-latency-us = <3>; - - bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x38100000 0x0 0x38100000 0x0 0x00100000 /* downstream I/O (1MB) */ - 0xc2000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */ - 0x82000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */ - }; - - pcie@141a0000 { - compatible = "nvidia,tegra194-pcie", "snps,dw-pcie"; - power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; - reg = <0x00 0x141a0000 0x0 0x00020000 /* appl registers (128K) */ - 0x00 0x3a000000 0x0 0x00040000 /* configuration space (256K) */ - 0x00 0x3a040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ - 0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */ - reg-names = "appl", "config", "atu_dma", "dbi"; - - status = "disabled"; - - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - num-lanes = <8>; - num-viewport = <8>; - linux,pci-domain = <5>; - - pinctrl-names = "default"; - pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>; - - clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>, - <&bpmp TEGRA194_CLK_PEX1_CORE_5M>; - clock-names = "core", "core_m"; - - resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, - <&bpmp TEGRA194_RESET_PEX1_CORE_5>; - reset-names = "apb", "core"; - - interrupts = , /* controller interrupt */ - ; /* MSI interrupt */ - interrupt-names = "intr", "msi"; - - nvidia,bpmp = <&bpmp 5>; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; - - nvidia,aspm-cmrt-us = <60>; - nvidia,aspm-pwr-on-t-us = <20>; - nvidia,aspm-l0s-entrance-latency-us = <3>; - - bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x3a100000 0x0 0x3a100000 0x0 0x00100000 /* downstream I/O (1MB) */ - 0xc2000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */ - 0x82000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */ - }; - - sysram@40000000 { - compatible = "nvidia,tegra194-sysram", "mmio-sram"; - reg = <0x0 0x40000000 0x0 0x50000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x40000000 0x50000>; - - cpu_bpmp_tx: shmem@4e000 { - compatible = "nvidia,tegra194-bpmp-shmem"; - reg = <0x4e000 0x1000>; - label = "cpu-bpmp-tx"; - pool; - }; - - cpu_bpmp_rx: shmem@4f000 { - compatible = "nvidia,tegra194-bpmp-shmem"; - reg = <0x4f000 0x1000>; - label = "cpu-bpmp-rx"; - pool; - }; - }; - - bpmp: bpmp { - compatible = "nvidia,tegra186-bpmp"; - mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB - TEGRA_HSP_DB_MASTER_BPMP>; - shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - - bpmp_i2c: i2c { - compatible = "nvidia,tegra186-bpmp-i2c"; - nvidia,bpmp-bus-id = <5>; - #address-cells = <1>; - #size-cells = <0>; - }; - - bpmp_thermal: thermal { - compatible = "nvidia,tegra186-bpmp-thermal"; - #thermal-sensor-cells = <1>; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0_0: cpu@0 { - compatible = "nvidia,tegra194-carmel"; - device_type = "cpu"; - reg = <0x000>; - enable-method = "psci"; - i-cache-size = <131072>; - i-cache-line-size = <64>; - i-cache-sets = <512>; - d-cache-size = <65536>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&l2c_0>; - }; - - cpu0_1: cpu@1 { - compatible = "nvidia,tegra194-carmel"; - device_type = "cpu"; - reg = <0x001>; - enable-method = "psci"; - i-cache-size = <131072>; - i-cache-line-size = <64>; - i-cache-sets = <512>; - d-cache-size = <65536>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&l2c_0>; - }; - - cpu1_0: cpu@100 { - compatible = "nvidia,tegra194-carmel"; - device_type = "cpu"; - reg = <0x100>; - enable-method = "psci"; - i-cache-size = <131072>; - i-cache-line-size = <64>; - i-cache-sets = <512>; - d-cache-size = <65536>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&l2c_1>; - }; - - cpu1_1: cpu@101 { - compatible = "nvidia,tegra194-carmel"; - device_type = "cpu"; - reg = <0x101>; - enable-method = "psci"; - i-cache-size = <131072>; - i-cache-line-size = <64>; - i-cache-sets = <512>; - d-cache-size = <65536>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&l2c_1>; - }; - - cpu2_0: cpu@200 { - compatible = "nvidia,tegra194-carmel"; - device_type = "cpu"; - reg = <0x200>; - enable-method = "psci"; - i-cache-size = <131072>; - i-cache-line-size = <64>; - i-cache-sets = <512>; - d-cache-size = <65536>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&l2c_2>; - }; - - cpu2_1: cpu@201 { - compatible = "nvidia,tegra194-carmel"; - device_type = "cpu"; - reg = <0x201>; - enable-method = "psci"; - i-cache-size = <131072>; - i-cache-line-size = <64>; - i-cache-sets = <512>; - d-cache-size = <65536>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&l2c_2>; - }; - - cpu3_0: cpu@300 { - compatible = "nvidia,tegra194-carmel"; - device_type = "cpu"; - reg = <0x300>; - enable-method = "psci"; - i-cache-size = <131072>; - i-cache-line-size = <64>; - i-cache-sets = <512>; - d-cache-size = <65536>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&l2c_3>; - }; - - cpu3_1: cpu@301 { - compatible = "nvidia,tegra194-carmel"; - device_type = "cpu"; - reg = <0x301>; - enable-method = "psci"; - i-cache-size = <131072>; - i-cache-line-size = <64>; - i-cache-sets = <512>; - d-cache-size = <65536>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&l2c_3>; - }; - - cpu-map { - cluster0 { - core0 { - cpu = <&cpu0_0>; - }; - - core1 { - cpu = <&cpu0_1>; - }; - }; - - cluster1 { - core0 { - cpu = <&cpu1_0>; - }; - - core1 { - cpu = <&cpu1_1>; - }; - }; - - cluster2 { - core0 { - cpu = <&cpu2_0>; - }; - - core1 { - cpu = <&cpu2_1>; - }; - }; - - cluster3 { - core0 { - cpu = <&cpu3_0>; - }; - - core1 { - cpu = <&cpu3_1>; - }; - }; - }; - - l2c_0: l2-cache0 { - cache-size = <2097152>; - cache-line-size = <64>; - cache-sets = <2048>; - next-level-cache = <&l3c>; - }; - - l2c_1: l2-cache1 { - cache-size = <2097152>; - cache-line-size = <64>; - cache-sets = <2048>; - next-level-cache = <&l3c>; - }; - - l2c_2: l2-cache2 { - cache-size = <2097152>; - cache-line-size = <64>; - cache-sets = <2048>; - next-level-cache = <&l3c>; - }; - - l2c_3: l2-cache3 { - cache-size = <2097152>; - cache-line-size = <64>; - cache-sets = <2048>; - next-level-cache = <&l3c>; - }; - - l3c: l3-cache { - cache-size = <4194304>; - cache-line-size = <64>; - cache-sets = <4096>; - }; - }; - - psci { - compatible = "arm,psci-1.0"; - status = "okay"; - method = "smc"; - }; - - tcu: tcu { - compatible = "nvidia,tegra194-tcu"; - mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, - <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; - mbox-names = "rx", "tx"; - }; - - thermal-zones { - cpu { - thermal-sensors = <&{/bpmp/thermal} - TEGRA194_BPMP_THERMAL_ZONE_CPU>; - status = "disabled"; - }; - - gpu { - thermal-sensors = <&{/bpmp/thermal} - TEGRA194_BPMP_THERMAL_ZONE_GPU>; - status = "disabled"; - }; - - aux { - thermal-sensors = <&{/bpmp/thermal} - TEGRA194_BPMP_THERMAL_ZONE_AUX>; - status = "disabled"; - }; - - pllx { - thermal-sensors = <&{/bpmp/thermal} - TEGRA194_BPMP_THERMAL_ZONE_PLLX>; - status = "disabled"; - }; - - ao { - thermal-sensors = <&{/bpmp/thermal} - TEGRA194_BPMP_THERMAL_ZONE_AO>; - status = "disabled"; - }; - - tj { - thermal-sensors = <&{/bpmp/thermal} - TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>; - status = "disabled"; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - interrupt-parent = <&gic>; - always-on; - }; -}; diff --git a/sys/gnu/dts/arm64/nvidia/tegra210-p2180.dtsi b/sys/gnu/dts/arm64/nvidia/tegra210-p2180.dtsi deleted file mode 100644 index cb58f79deb4..00000000000 --- a/sys/gnu/dts/arm64/nvidia/tegra210-p2180.dtsi +++ /dev/null @@ -1,355 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include - -#include "tegra210.dtsi" - -/ { - model = "NVIDIA Jetson TX1"; - compatible = "nvidia,p2180", "nvidia,tegra210"; - - aliases { - rtc0 = "/i2c@7000d000/pmic@3c"; - rtc1 = "/rtc@7000e000"; - serial0 = &uarta; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - device_type = "memory"; - reg = <0x0 0x80000000 0x1 0x0>; - }; - - gpu@57000000 { - vdd-supply = <&vdd_gpu>; - }; - - /* debug port */ - serial@70006000 { - status = "okay"; - }; - - i2c@7000d000 { - status = "okay"; - clock-frequency = <400000>; - - pmic: pmic@3c { - compatible = "maxim,max77620"; - reg = <0x3c>; - interrupts = ; - - #interrupt-cells = <2>; - interrupt-controller; - - #gpio-cells = <2>; - gpio-controller; - - pinctrl-names = "default"; - pinctrl-0 = <&max77620_default>; - - max77620_default: pinmux { - gpio0 { - pins = "gpio0"; - function = "gpio"; - }; - - gpio1 { - pins = "gpio1"; - function = "fps-out"; - drive-push-pull = <1>; - maxim,active-fps-source = ; - maxim,active-fps-power-up-slot = <7>; - maxim,active-fps-power-down-slot = <0>; - }; - - gpio2_3 { - pins = "gpio2", "gpio3"; - function = "fps-out"; - drive-open-drain = <1>; - maxim,active-fps-source = ; - }; - - gpio4 { - pins = "gpio4"; - function = "32k-out1"; - }; - - gpio5_6_7 { - pins = "gpio5", "gpio6", "gpio7"; - function = "gpio"; - drive-push-pull = <1>; - }; - }; - - fps { - fps0 { - maxim,fps-event-source = ; - maxim,suspend-fps-time-period-us = <1280>; - }; - - fps1 { - maxim,fps-event-source = ; - maxim,suspend-fps-time-period-us = <1280>; - }; - - fps2 { - maxim,fps-event-source = ; - }; - }; - - regulators { - in-ldo0-1-supply = <&vdd_pre>; - in-ldo7-8-supply = <&vdd_pre>; - in-sd3-supply = <&vdd_5v0_sys>; - - vdd_soc: sd0 { - regulator-name = "VDD_SOC"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-boot-on; - - regulator-enable-ramp-delay = <146>; - regulator-ramp-delay = <27500>; - - maxim,active-fps-source = ; - }; - - vdd_ddr: sd1 { - regulator-name = "VDD_DDR_1V1_PMIC"; - regulator-always-on; - regulator-boot-on; - - regulator-enable-ramp-delay = <130>; - regulator-ramp-delay = <27500>; - - maxim,active-fps-source = ; - }; - - vdd_pre: sd2 { - regulator-name = "VDD_PRE_REG_1V35"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - - regulator-enable-ramp-delay = <176>; - regulator-ramp-delay = <27500>; - - maxim,active-fps-source = ; - }; - - vdd_1v8: sd3 { - regulator-name = "VDD_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - - regulator-enable-ramp-delay = <242>; - regulator-ramp-delay = <27500>; - - maxim,active-fps-source = ; - }; - - vdd_sys_1v2: ldo0 { - regulator-name = "AVDD_SYS_1V2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - - regulator-enable-ramp-delay = <26>; - regulator-ramp-delay = <100000>; - - maxim,active-fps-source = ; - }; - - vdd_pex_1v05: ldo1 { - regulator-name = "VDD_PEX_1V05"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - - regulator-enable-ramp-delay = <22>; - regulator-ramp-delay = <100000>; - - maxim,active-fps-source = ; - }; - - vddio_sdmmc: ldo2 { - regulator-name = "VDDIO_SDMMC"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - - regulator-enable-ramp-delay = <62>; - regulator-ramp-delay = <100000>; - - maxim,active-fps-source = ; - }; - - vdd_cam_hv: ldo3 { - regulator-name = "VDD_CAM_HV"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - - regulator-enable-ramp-delay = <50>; - regulator-ramp-delay = <100000>; - - maxim,active-fps-source = ; - }; - - vdd_rtc: ldo4 { - regulator-name = "VDD_RTC"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - regulator-always-on; - regulator-boot-on; - - regulator-enable-ramp-delay = <22>; - regulator-ramp-delay = <100000>; - - maxim,active-fps-source = ; - }; - - vdd_ts_hv: ldo5 { - regulator-name = "VDD_TS_HV"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-enable-ramp-delay = <62>; - regulator-ramp-delay = <100000>; - - maxim,active-fps-source = ; - }; - - vdd_ts: ldo6 { - regulator-name = "VDD_TS_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-enable-ramp-delay = <36>; - regulator-ramp-delay = <100000>; - - maxim,active-fps-source = ; - maxim,active-fps-power-up-slot = <7>; - maxim,active-fps-power-down-slot = <0>; - }; - - avdd_1v05_pll: ldo7 { - regulator-name = "AVDD_1V05_PLL"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - regulator-always-on; - regulator-boot-on; - - regulator-enable-ramp-delay = <24>; - regulator-ramp-delay = <100000>; - - maxim,active-fps-source = ; - }; - - avdd_1v05: ldo8 { - regulator-name = "AVDD_SATA_HDMI_DP_1V05"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - - regulator-enable-ramp-delay = <22>; - regulator-ramp-delay = <100000>; - - maxim,active-fps-source = ; - }; - }; - }; - }; - - i2c@7000c500 { - /* module ID EEPROM */ - eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - - address-bits = <8>; - page-size = <8>; - size = <256>; - read-only; - }; - }; - - pmc@7000e400 { - nvidia,invert-interrupt; - nvidia,suspend-mode = <0>; - nvidia,cpu-pwr-good-time = <0>; - nvidia,cpu-pwr-off-time = <0>; - nvidia,core-pwr-good-time = <4587 3876>; - nvidia,core-pwr-off-time = <39065>; - nvidia,core-power-req-active-high; - nvidia,sys-clock-req-active-high; - }; - - /* eMMC */ - sdhci@700b0600 { - status = "okay"; - bus-width = <8>; - non-removable; - vqmmc-supply = <&vdd_1v8>; - }; - - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - cpus { - cpu@0 { - enable-method = "psci"; - }; - - cpu@1 { - enable-method = "psci"; - }; - - cpu@2 { - enable-method = "psci"; - }; - - cpu@3 { - enable-method = "psci"; - }; - - idle-states { - cpu-sleep { - status = "okay"; - }; - }; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - regulators { - vdd_gpu: regulator@100 { - compatible = "pwm-regulator"; - reg = <100>; - pwms = <&pwm 1 4880>; - regulator-name = "VDD_GPU"; - regulator-min-microvolt = <710000>; - regulator-max-microvolt = <1320000>; - enable-gpios = <&pmic 6 GPIO_ACTIVE_HIGH>; - regulator-ramp-delay = <80>; - regulator-enable-ramp-delay = <2000>; - regulator-settling-time-us = <160>; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/nvidia/tegra210-p2371-0000.dts b/sys/gnu/dts/arm64/nvidia/tegra210-p2371-0000.dts deleted file mode 100644 index 21c6d3749bc..00000000000 --- a/sys/gnu/dts/arm64/nvidia/tegra210-p2371-0000.dts +++ /dev/null @@ -1,10 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "tegra210-p2530.dtsi" -#include "tegra210-p2595.dtsi" - -/ { - model = "NVIDIA Tegra210 P2371 (P2530/P2595) reference design"; - compatible = "nvidia,p2371-0000", "nvidia,tegra210"; -}; diff --git a/sys/gnu/dts/arm64/nvidia/tegra210-p2371-2180.dts b/sys/gnu/dts/arm64/nvidia/tegra210-p2371-2180.dts deleted file mode 100644 index a3cafe39ba4..00000000000 --- a/sys/gnu/dts/arm64/nvidia/tegra210-p2371-2180.dts +++ /dev/null @@ -1,127 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "tegra210-p2180.dtsi" -#include "tegra210-p2597.dtsi" - -/ { - model = "NVIDIA Jetson TX1 Developer Kit"; - compatible = "nvidia,p2371-2180", "nvidia,tegra210"; - - pcie@1003000 { - status = "okay"; - - avdd-pll-uerefe-supply = <&avdd_1v05_pll>; - hvddio-pex-supply = <&vdd_1v8>; - dvddio-pex-supply = <&vdd_pex_1v05>; - dvdd-pex-pll-supply = <&vdd_pex_1v05>; - hvdd-pex-pll-e-supply = <&vdd_1v8>; - vddio-pex-ctl-supply = <&vdd_1v8>; - - pci@1,0 { - phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>, - <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>, - <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>, - <&{/padctl@7009f000/pads/pcie/lanes/pcie-3}>; - phy-names = "pcie-0", "pcie-1", "pcie-2", "pcie-3"; - status = "okay"; - }; - - pci@2,0 { - phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>; - phy-names = "pcie-0"; - status = "okay"; - }; - }; - - host1x@50000000 { - dsi@54300000 { - status = "okay"; - - avdd-dsi-csi-supply = <&vdd_dsi_csi>; - - panel@0 { - compatible = "auo,b080uan01"; - reg = <0>; - - enable-gpios = <&gpio TEGRA_GPIO(V, 2) - GPIO_ACTIVE_HIGH>; - power-supply = <&vdd_5v0_io>; - backlight = <&backlight>; - }; - }; - }; - - i2c@7000c400 { - backlight: backlight@2c { - compatible = "ti,lp8557"; - reg = <0x2c>; - - dev-ctrl = /bits/ 8 <0x80>; - init-brt = /bits/ 8 <0xff>; - - pwm-period = <29334>; - - pwms = <&pwm 0 29334>; - pwm-names = "lp8557"; - - /* 3 LED string */ - rom_14h { - rom-addr = /bits/ 8 <0x14>; - rom-val = /bits/ 8 <0x87>; - }; - - /* boost frequency 1 MHz */ - rom_13h { - rom-addr = /bits/ 8 <0x13>; - rom-val = /bits/ 8 <0x01>; - }; - }; - }; - - i2c@7000c500 { - /* carrier board ID EEPROM */ - eeprom@57 { - compatible = "atmel,24c02"; - reg = <0x57>; - - address-bits = <8>; - page-size = <8>; - size = <256>; - read-only; - }; - }; - - clock@70110000 { - status = "okay"; - - nvidia,cf = <6>; - nvidia,ci = <0>; - nvidia,cg = <2>; - nvidia,droop-ctrl = <0x00000f00>; - nvidia,force-mode = <1>; - nvidia,sample-rate = <25000>; - - nvidia,pwm-min-microvolts = <708000>; - nvidia,pwm-period-nanoseconds = <2500>; /* 2.5us */ - nvidia,pwm-to-pmic; - nvidia,pwm-tristate-microvolts = <1000000>; - nvidia,pwm-voltage-step-microvolts = <19200>; - - pinctrl-names = "dvfs_pwm_enable", "dvfs_pwm_disable"; - pinctrl-0 = <&dvfs_pwm_active_state>; - pinctrl-1 = <&dvfs_pwm_inactive_state>; - }; - - aconnect@702c0000 { - status = "okay"; - - dma@702e2000 { - status = "okay"; - }; - - agic@702f9000 { - status = "okay"; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/nvidia/tegra210-p2530.dtsi b/sys/gnu/dts/arm64/nvidia/tegra210-p2530.dtsi deleted file mode 100644 index d0dc0392372..00000000000 --- a/sys/gnu/dts/arm64/nvidia/tegra210-p2530.dtsi +++ /dev/null @@ -1,78 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "tegra210.dtsi" - -/ { - model = "NVIDIA Tegra210 P2530 main board"; - compatible = "nvidia,p2530", "nvidia,tegra210"; - - aliases { - rtc1 = "/rtc@7000e000"; - serial0 = &uarta; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - device_type = "memory"; - reg = <0x0 0x80000000 0x0 0xc0000000>; - }; - - /* debug port */ - serial@70006000 { - status = "okay"; - }; - - i2c@7000d000 { - status = "okay"; - clock-frequency = <400000>; - }; - - pmc@7000e400 { - nvidia,invert-interrupt; - }; - - /* eMMC */ - sdhci@700b0600 { - status = "okay"; - bus-width = <8>; - non-removable; - }; - - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - cpus { - cpu@0 { - enable-method = "psci"; - }; - - cpu@1 { - enable-method = "psci"; - }; - - cpu@2 { - enable-method = "psci"; - }; - - cpu@3 { - enable-method = "psci"; - }; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; -}; diff --git a/sys/gnu/dts/arm64/nvidia/tegra210-p2571.dts b/sys/gnu/dts/arm64/nvidia/tegra210-p2571.dts deleted file mode 100644 index e2a347e5721..00000000000 --- a/sys/gnu/dts/arm64/nvidia/tegra210-p2571.dts +++ /dev/null @@ -1,1303 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include -#include "tegra210-p2530.dtsi" - -/ { - model = "NVIDIA Tegra210 P2571 reference design"; - compatible = "nvidia,p2571", "nvidia,tegra210"; - - pinmux: pinmux@700008d4 { - pinctrl-names = "boot"; - pinctrl-0 = <&state_boot>; - - state_boot: pinmux { - pex_l0_rst_n_pa0 { - nvidia,pins = "pex_l0_rst_n_pa0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - pex_l0_clkreq_n_pa1 { - nvidia,pins = "pex_l0_clkreq_n_pa1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - pex_wake_n_pa2 { - nvidia,pins = "pex_wake_n_pa2"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - pex_l1_rst_n_pa3 { - nvidia,pins = "pex_l1_rst_n_pa3"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - pex_l1_clkreq_n_pa4 { - nvidia,pins = "pex_l1_clkreq_n_pa4"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - sata_led_active_pa5 { - nvidia,pins = "sata_led_active_pa5"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pa6 { - nvidia,pins = "pa6"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap1_fs_pb0 { - nvidia,pins = "dap1_fs_pb0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap1_din_pb1 { - nvidia,pins = "dap1_din_pb1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap1_dout_pb2 { - nvidia,pins = "dap1_dout_pb2"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap1_sclk_pb3 { - nvidia,pins = "dap1_sclk_pb3"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi2_mosi_pb4 { - nvidia,pins = "spi2_mosi_pb4"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi2_miso_pb5 { - nvidia,pins = "spi2_miso_pb5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi2_sck_pb6 { - nvidia,pins = "spi2_sck_pb6"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi2_cs0_pb7 { - nvidia,pins = "spi2_cs0_pb7"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi1_mosi_pc0 { - nvidia,pins = "spi1_mosi_pc0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi1_miso_pc1 { - nvidia,pins = "spi1_miso_pc1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi1_sck_pc2 { - nvidia,pins = "spi1_sck_pc2"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi1_cs0_pc3 { - nvidia,pins = "spi1_cs0_pc3"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi1_cs1_pc4 { - nvidia,pins = "spi1_cs1_pc4"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi4_sck_pc5 { - nvidia,pins = "spi4_sck_pc5"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi4_cs0_pc6 { - nvidia,pins = "spi4_cs0_pc6"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi4_mosi_pc7 { - nvidia,pins = "spi4_mosi_pc7"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi4_miso_pd0 { - nvidia,pins = "spi4_miso_pd0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart3_tx_pd1 { - nvidia,pins = "uart3_tx_pd1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart3_rx_pd2 { - nvidia,pins = "uart3_rx_pd2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart3_rts_pd3 { - nvidia,pins = "uart3_rts_pd3"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart3_cts_pd4 { - nvidia,pins = "uart3_cts_pd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dmic1_clk_pe0 { - nvidia,pins = "dmic1_clk_pe0"; - nvidia,function = "i2s3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dmic1_dat_pe1 { - nvidia,pins = "dmic1_dat_pe1"; - nvidia,function = "i2s3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dmic2_clk_pe2 { - nvidia,pins = "dmic2_clk_pe2"; - nvidia,function = "i2s3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dmic2_dat_pe3 { - nvidia,pins = "dmic2_dat_pe3"; - nvidia,function = "i2s3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dmic3_clk_pe4 { - nvidia,pins = "dmic3_clk_pe4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dmic3_dat_pe5 { - nvidia,pins = "dmic3_dat_pe5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pe6 { - nvidia,pins = "pe6"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pe7 { - nvidia,pins = "pe7"; - nvidia,function = "pwm3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gen3_i2c_scl_pf0 { - nvidia,pins = "gen3_i2c_scl_pf0"; - nvidia,function = "i2c3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - gen3_i2c_sda_pf1 { - nvidia,pins = "gen3_i2c_sda_pf1"; - nvidia,function = "i2c3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - uart2_tx_pg0 { - nvidia,pins = "uart2_tx_pg0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart2_rx_pg1 { - nvidia,pins = "uart2_rx_pg1"; - nvidia,function = "uartb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart2_rts_pg2 { - nvidia,pins = "uart2_rts_pg2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart2_cts_pg3 { - nvidia,pins = "uart2_cts_pg3"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - wifi_en_ph0 { - nvidia,pins = "wifi_en_ph0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - wifi_rst_ph1 { - nvidia,pins = "wifi_rst_ph1"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - wifi_wake_ap_ph2 { - nvidia,pins = "wifi_wake_ap_ph2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - ap_wake_bt_ph3 { - nvidia,pins = "ap_wake_bt_ph3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - bt_rst_ph4 { - nvidia,pins = "bt_rst_ph4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - bt_wake_ap_ph5 { - nvidia,pins = "bt_wake_ap_ph5"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - ph6 { - nvidia,pins = "ph6"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - ap_wake_nfc_ph7 { - nvidia,pins = "ap_wake_nfc_ph7"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - nfc_en_pi0 { - nvidia,pins = "nfc_en_pi0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - nfc_int_pi1 { - nvidia,pins = "nfc_int_pi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gps_en_pi2 { - nvidia,pins = "gps_en_pi2"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gps_rst_pi3 { - nvidia,pins = "gps_rst_pi3"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart4_tx_pi4 { - nvidia,pins = "uart4_tx_pi4"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart4_rx_pi5 { - nvidia,pins = "uart4_rx_pi5"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart4_rts_pi6 { - nvidia,pins = "uart4_rts_pi6"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart4_cts_pi7 { - nvidia,pins = "uart4_cts_pi7"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gen1_i2c_sda_pj0 { - nvidia,pins = "gen1_i2c_sda_pj0"; - nvidia,function = "i2c1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - gen1_i2c_scl_pj1 { - nvidia,pins = "gen1_i2c_scl_pj1"; - nvidia,function = "i2c1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - gen2_i2c_scl_pj2 { - nvidia,pins = "gen2_i2c_scl_pj2"; - nvidia,function = "i2c2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - gen2_i2c_sda_pj3 { - nvidia,pins = "gen2_i2c_sda_pj3"; - nvidia,function = "i2c2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - dap4_fs_pj4 { - nvidia,pins = "dap4_fs_pj4"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap4_din_pj5 { - nvidia,pins = "dap4_din_pj5"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap4_dout_pj6 { - nvidia,pins = "dap4_dout_pj6"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap4_sclk_pj7 { - nvidia,pins = "dap4_sclk_pj7"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pk0 { - nvidia,pins = "pk0"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pk1 { - nvidia,pins = "pk1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pk2 { - nvidia,pins = "pk2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pk3 { - nvidia,pins = "pk3"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pk4 { - nvidia,pins = "pk4"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pk5 { - nvidia,pins = "pk5"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pk6 { - nvidia,pins = "pk6"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pk7 { - nvidia,pins = "pk7"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pl0 { - nvidia,pins = "pl0"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pl1 { - nvidia,pins = "pl1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc1_clk_pm0 { - nvidia,pins = "sdmmc1_clk_pm0"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc1_cmd_pm1 { - nvidia,pins = "sdmmc1_cmd_pm1"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc1_dat3_pm2 { - nvidia,pins = "sdmmc1_dat3_pm2"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc1_dat2_pm3 { - nvidia,pins = "sdmmc1_dat2_pm3"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc1_dat1_pm4 { - nvidia,pins = "sdmmc1_dat1_pm4"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc1_dat0_pm5 { - nvidia,pins = "sdmmc1_dat0_pm5"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc3_clk_pp0 { - nvidia,pins = "sdmmc3_clk_pp0"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc3_cmd_pp1 { - nvidia,pins = "sdmmc3_cmd_pp1"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc3_dat3_pp2 { - nvidia,pins = "sdmmc3_dat3_pp2"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc3_dat2_pp3 { - nvidia,pins = "sdmmc3_dat2_pp3"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc3_dat1_pp4 { - nvidia,pins = "sdmmc3_dat1_pp4"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc3_dat0_pp5 { - nvidia,pins = "sdmmc3_dat0_pp5"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam1_mclk_ps0 { - nvidia,pins = "cam1_mclk_ps0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam2_mclk_ps1 { - nvidia,pins = "cam2_mclk_ps1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam_i2c_scl_ps2 { - nvidia,pins = "cam_i2c_scl_ps2"; - nvidia,function = "i2cvi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - cam_i2c_sda_ps3 { - nvidia,pins = "cam_i2c_sda_ps3"; - nvidia,function = "i2cvi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - cam_rst_ps4 { - nvidia,pins = "cam_rst_ps4"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam_af_en_ps5 { - nvidia,pins = "cam_af_en_ps5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam_flash_en_ps6 { - nvidia,pins = "cam_flash_en_ps6"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam1_pwdn_ps7 { - nvidia,pins = "cam1_pwdn_ps7"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam2_pwdn_pt0 { - nvidia,pins = "cam2_pwdn_pt0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam1_strobe_pt1 { - nvidia,pins = "cam1_strobe_pt1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart1_tx_pu0 { - nvidia,pins = "uart1_tx_pu0"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart1_rx_pu1 { - nvidia,pins = "uart1_rx_pu1"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart1_rts_pu2 { - nvidia,pins = "uart1_rts_pu2"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart1_cts_pu3 { - nvidia,pins = "uart1_cts_pu3"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - lcd_bl_pwm_pv0 { - nvidia,pins = "lcd_bl_pwm_pv0"; - nvidia,function = "pwm0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - lcd_bl_en_pv1 { - nvidia,pins = "lcd_bl_en_pv1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - lcd_rst_pv2 { - nvidia,pins = "lcd_rst_pv2"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - lcd_gpio1_pv3 { - nvidia,pins = "lcd_gpio1_pv3"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - lcd_gpio2_pv4 { - nvidia,pins = "lcd_gpio2_pv4"; - nvidia,function = "pwm1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - ap_ready_pv5 { - nvidia,pins = "ap_ready_pv5"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - touch_rst_pv6 { - nvidia,pins = "touch_rst_pv6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - touch_clk_pv7 { - nvidia,pins = "touch_clk_pv7"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - modem_wake_ap_px0 { - nvidia,pins = "modem_wake_ap_px0"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - touch_int_px1 { - nvidia,pins = "touch_int_px1"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - motion_int_px2 { - nvidia,pins = "motion_int_px2"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - als_prox_int_px3 { - nvidia,pins = "als_prox_int_px3"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - temp_alert_px4 { - nvidia,pins = "temp_alert_px4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - button_power_on_px5 { - nvidia,pins = "button_power_on_px5"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - button_vol_up_px6 { - nvidia,pins = "button_vol_up_px6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - button_vol_down_px7 { - nvidia,pins = "button_vol_down_px7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - button_slide_sw_py0 { - nvidia,pins = "button_slide_sw_py0"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - button_home_py1 { - nvidia,pins = "button_home_py1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - lcd_te_py2 { - nvidia,pins = "lcd_te_py2"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pwr_i2c_scl_py3 { - nvidia,pins = "pwr_i2c_scl_py3"; - nvidia,function = "i2cpmu"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - pwr_i2c_sda_py4 { - nvidia,pins = "pwr_i2c_sda_py4"; - nvidia,function = "i2cpmu"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - clk_32k_out_py5 { - nvidia,pins = "clk_32k_out_py5"; - nvidia,function = "soc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pz0 { - nvidia,pins = "pz0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pz1 { - nvidia,pins = "pz1"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pz2 { - nvidia,pins = "pz2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pz3 { - nvidia,pins = "pz3"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pz4 { - nvidia,pins = "pz4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pz5 { - nvidia,pins = "pz5"; - nvidia,function = "soc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap2_fs_paa0 { - nvidia,pins = "dap2_fs_paa0"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap2_sclk_paa1 { - nvidia,pins = "dap2_sclk_paa1"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap2_din_paa2 { - nvidia,pins = "dap2_din_paa2"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap2_dout_paa3 { - nvidia,pins = "dap2_dout_paa3"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - aud_mclk_pbb0 { - nvidia,pins = "aud_mclk_pbb0"; - nvidia,function = "aud"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dvfs_pwm_pbb1 { - nvidia,pins = "dvfs_pwm_pbb1"; - nvidia,function = "cldvfs"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dvfs_clk_pbb2 { - nvidia,pins = "dvfs_clk_pbb2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gpio_x1_aud_pbb3 { - nvidia,pins = "gpio_x1_aud_pbb3"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gpio_x3_aud_pbb4 { - nvidia,pins = "gpio_x3_aud_pbb4"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - hdmi_cec_pcc0 { - nvidia,pins = "hdmi_cec_pcc0"; - nvidia,function = "cec"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - hdmi_int_dp_hpd_pcc1 { - nvidia,pins = "hdmi_int_dp_hpd_pcc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - spdif_out_pcc2 { - nvidia,pins = "spdif_out_pcc2"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spdif_in_pcc3 { - nvidia,pins = "spdif_in_pcc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - usb_vbus_en0_pcc4 { - nvidia,pins = "usb_vbus_en0_pcc4"; - nvidia,function = "usb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - usb_vbus_en1_pcc5 { - nvidia,pins = "usb_vbus_en1_pcc5"; - nvidia,function = "usb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - dp_hpd0_pcc6 { - nvidia,pins = "dp_hpd0_pcc6"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pcc7 { - nvidia,pins = "pcc7"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - spi2_cs1_pdd0 { - nvidia,pins = "spi2_cs1_pdd0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - qspi_sck_pee0 { - nvidia,pins = "qspi_sck_pee0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - qspi_cs_n_pee1 { - nvidia,pins = "qspi_cs_n_pee1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - qspi_io0_pee2 { - nvidia,pins = "qspi_io0_pee2"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - qspi_io1_pee3 { - nvidia,pins = "qspi_io1_pee3"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - qspi_io2_pee4 { - nvidia,pins = "qspi_io2_pee4"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - qspi_io3_pee5 { - nvidia,pins = "qspi_io3_pee5"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - core_pwr_req { - nvidia,pins = "core_pwr_req"; - nvidia,function = "core"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cpu_pwr_req { - nvidia,pins = "cpu_pwr_req"; - nvidia,function = "cpu"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pwr_int_n { - nvidia,pins = "pwr_int_n"; - nvidia,function = "pmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - clk_32k_in { - nvidia,pins = "clk_32k_in"; - nvidia,function = "clk"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - jtag_rtck { - nvidia,pins = "jtag_rtck"; - nvidia,function = "jtag"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - clk_req { - nvidia,pins = "clk_req"; - nvidia,function = "sys"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - shutdown { - nvidia,pins = "shutdown"; - nvidia,function = "shutdown"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/nvidia/tegra210-p2595.dtsi b/sys/gnu/dts/arm64/nvidia/tegra210-p2595.dtsi deleted file mode 100644 index 6ae292da729..00000000000 --- a/sys/gnu/dts/arm64/nvidia/tegra210-p2595.dtsi +++ /dev/null @@ -1,1273 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/ { - model = "NVIDIA Tegra210 P2595 I/O board"; - compatible = "nvidia,p2595", "nvidia,tegra210"; - - pinmux: pinmux@700008d4 { - pinctrl-names = "boot"; - pinctrl-0 = <&state_boot>; - - state_boot: pinmux { - pex_l0_rst_n_pa0 { - nvidia,pins = "pex_l0_rst_n_pa0"; - nvidia,function = "pe0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - pex_l0_clkreq_n_pa1 { - nvidia,pins = "pex_l0_clkreq_n_pa1"; - nvidia,function = "pe0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - pex_wake_n_pa2 { - nvidia,pins = "pex_wake_n_pa2"; - nvidia,function = "pe"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - pex_l1_rst_n_pa3 { - nvidia,pins = "pex_l1_rst_n_pa3"; - nvidia,function = "pe1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - pex_l1_clkreq_n_pa4 { - nvidia,pins = "pex_l1_clkreq_n_pa4"; - nvidia,function = "pe1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - sata_led_active_pa5 { - nvidia,pins = "sata_led_active_pa5"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pa6 { - nvidia,pins = "pa6"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap1_fs_pb0 { - nvidia,pins = "dap1_fs_pb0"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap1_din_pb1 { - nvidia,pins = "dap1_din_pb1"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap1_dout_pb2 { - nvidia,pins = "dap1_dout_pb2"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap1_sclk_pb3 { - nvidia,pins = "dap1_sclk_pb3"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi2_mosi_pb4 { - nvidia,pins = "spi2_mosi_pb4"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi2_miso_pb5 { - nvidia,pins = "spi2_miso_pb5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi2_sck_pb6 { - nvidia,pins = "spi2_sck_pb6"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi2_cs0_pb7 { - nvidia,pins = "spi2_cs0_pb7"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi1_mosi_pc0 { - nvidia,pins = "spi1_mosi_pc0"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi1_miso_pc1 { - nvidia,pins = "spi1_miso_pc1"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi1_sck_pc2 { - nvidia,pins = "spi1_sck_pc2"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi1_cs0_pc3 { - nvidia,pins = "spi1_cs0_pc3"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi1_cs1_pc4 { - nvidia,pins = "spi1_cs1_pc4"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi4_sck_pc5 { - nvidia,pins = "spi4_sck_pc5"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi4_cs0_pc6 { - nvidia,pins = "spi4_cs0_pc6"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi4_mosi_pc7 { - nvidia,pins = "spi4_mosi_pc7"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi4_miso_pd0 { - nvidia,pins = "spi4_miso_pd0"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart3_tx_pd1 { - nvidia,pins = "uart3_tx_pd1"; - nvidia,function = "uartc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart3_rx_pd2 { - nvidia,pins = "uart3_rx_pd2"; - nvidia,function = "uartc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart3_rts_pd3 { - nvidia,pins = "uart3_rts_pd3"; - nvidia,function = "uartc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart3_cts_pd4 { - nvidia,pins = "uart3_cts_pd4"; - nvidia,function = "uartc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dmic1_clk_pe0 { - nvidia,pins = "dmic1_clk_pe0"; - nvidia,function = "dmic1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dmic1_dat_pe1 { - nvidia,pins = "dmic1_dat_pe1"; - nvidia,function = "dmic1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dmic2_clk_pe2 { - nvidia,pins = "dmic2_clk_pe2"; - nvidia,function = "dmic2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dmic2_dat_pe3 { - nvidia,pins = "dmic2_dat_pe3"; - nvidia,function = "dmic2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dmic3_clk_pe4 { - nvidia,pins = "dmic3_clk_pe4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dmic3_dat_pe5 { - nvidia,pins = "dmic3_dat_pe5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pe6 { - nvidia,pins = "pe6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pe7 { - nvidia,pins = "pe7"; - nvidia,function = "pwm3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gen3_i2c_scl_pf0 { - nvidia,pins = "gen3_i2c_scl_pf0"; - nvidia,function = "i2c3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - gen3_i2c_sda_pf1 { - nvidia,pins = "gen3_i2c_sda_pf1"; - nvidia,function = "i2c3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - uart2_tx_pg0 { - nvidia,pins = "uart2_tx_pg0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart2_rx_pg1 { - nvidia,pins = "uart2_rx_pg1"; - nvidia,function = "uartb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart2_rts_pg2 { - nvidia,pins = "uart2_rts_pg2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart2_cts_pg3 { - nvidia,pins = "uart2_cts_pg3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - wifi_en_ph0 { - nvidia,pins = "wifi_en_ph0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - wifi_rst_ph1 { - nvidia,pins = "wifi_rst_ph1"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - wifi_wake_ap_ph2 { - nvidia,pins = "wifi_wake_ap_ph2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - ap_wake_bt_ph3 { - nvidia,pins = "ap_wake_bt_ph3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - bt_rst_ph4 { - nvidia,pins = "bt_rst_ph4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - bt_wake_ap_ph5 { - nvidia,pins = "bt_wake_ap_ph5"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - ph6 { - nvidia,pins = "ph6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - ap_wake_nfc_ph7 { - nvidia,pins = "ap_wake_nfc_ph7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - nfc_en_pi0 { - nvidia,pins = "nfc_en_pi0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - nfc_int_pi1 { - nvidia,pins = "nfc_int_pi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gps_en_pi2 { - nvidia,pins = "gps_en_pi2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gps_rst_pi3 { - nvidia,pins = "gps_rst_pi3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart4_tx_pi4 { - nvidia,pins = "uart4_tx_pi4"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart4_rx_pi5 { - nvidia,pins = "uart4_rx_pi5"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart4_rts_pi6 { - nvidia,pins = "uart4_rts_pi6"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart4_cts_pi7 { - nvidia,pins = "uart4_cts_pi7"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gen1_i2c_sda_pj0 { - nvidia,pins = "gen1_i2c_sda_pj0"; - nvidia,function = "i2c1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - gen1_i2c_scl_pj1 { - nvidia,pins = "gen1_i2c_scl_pj1"; - nvidia,function = "i2c1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - gen2_i2c_scl_pj2 { - nvidia,pins = "gen2_i2c_scl_pj2"; - nvidia,function = "i2c2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - gen2_i2c_sda_pj3 { - nvidia,pins = "gen2_i2c_sda_pj3"; - nvidia,function = "i2c2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - dap4_fs_pj4 { - nvidia,pins = "dap4_fs_pj4"; - nvidia,function = "i2s4b"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap4_din_pj5 { - nvidia,pins = "dap4_din_pj5"; - nvidia,function = "i2s4b"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap4_dout_pj6 { - nvidia,pins = "dap4_dout_pj6"; - nvidia,function = "i2s4b"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap4_sclk_pj7 { - nvidia,pins = "dap4_sclk_pj7"; - nvidia,function = "i2s4b"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pk0 { - nvidia,pins = "pk0"; - nvidia,function = "i2s5b"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pk1 { - nvidia,pins = "pk1"; - nvidia,function = "i2s5b"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pk2 { - nvidia,pins = "pk2"; - nvidia,function = "i2s5b"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pk3 { - nvidia,pins = "pk3"; - nvidia,function = "i2s5b"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pk4 { - nvidia,pins = "pk4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pk5 { - nvidia,pins = "pk5"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pk6 { - nvidia,pins = "pk6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pk7 { - nvidia,pins = "pk7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pl0 { - nvidia,pins = "pl0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pl1 { - nvidia,pins = "pl1"; - nvidia,function = "soc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc1_clk_pm0 { - nvidia,pins = "sdmmc1_clk_pm0"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc1_cmd_pm1 { - nvidia,pins = "sdmmc1_cmd_pm1"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc1_dat3_pm2 { - nvidia,pins = "sdmmc1_dat3_pm2"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc1_dat2_pm3 { - nvidia,pins = "sdmmc1_dat2_pm3"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc1_dat1_pm4 { - nvidia,pins = "sdmmc1_dat1_pm4"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc1_dat0_pm5 { - nvidia,pins = "sdmmc1_dat0_pm5"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc3_clk_pp0 { - nvidia,pins = "sdmmc3_clk_pp0"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc3_cmd_pp1 { - nvidia,pins = "sdmmc3_cmd_pp1"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc3_dat3_pp2 { - nvidia,pins = "sdmmc3_dat3_pp2"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc3_dat2_pp3 { - nvidia,pins = "sdmmc3_dat2_pp3"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc3_dat1_pp4 { - nvidia,pins = "sdmmc3_dat1_pp4"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc3_dat0_pp5 { - nvidia,pins = "sdmmc3_dat0_pp5"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam1_mclk_ps0 { - nvidia,pins = "cam1_mclk_ps0"; - nvidia,function = "extperiph3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam2_mclk_ps1 { - nvidia,pins = "cam2_mclk_ps1"; - nvidia,function = "extperiph3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam_i2c_scl_ps2 { - nvidia,pins = "cam_i2c_scl_ps2"; - nvidia,function = "i2cvi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - cam_i2c_sda_ps3 { - nvidia,pins = "cam_i2c_sda_ps3"; - nvidia,function = "i2cvi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - cam_rst_ps4 { - nvidia,pins = "cam_rst_ps4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam_af_en_ps5 { - nvidia,pins = "cam_af_en_ps5"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam_flash_en_ps6 { - nvidia,pins = "cam_flash_en_ps6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam1_pwdn_ps7 { - nvidia,pins = "cam1_pwdn_ps7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam2_pwdn_pt0 { - nvidia,pins = "cam2_pwdn_pt0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam1_strobe_pt1 { - nvidia,pins = "cam1_strobe_pt1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart1_tx_pu0 { - nvidia,pins = "uart1_tx_pu0"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart1_rx_pu1 { - nvidia,pins = "uart1_rx_pu1"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart1_rts_pu2 { - nvidia,pins = "uart1_rts_pu2"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart1_cts_pu3 { - nvidia,pins = "uart1_cts_pu3"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - lcd_bl_pwm_pv0 { - nvidia,pins = "lcd_bl_pwm_pv0"; - nvidia,function = "pwm0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - lcd_bl_en_pv1 { - nvidia,pins = "lcd_bl_en_pv1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - lcd_rst_pv2 { - nvidia,pins = "lcd_rst_pv2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - lcd_gpio1_pv3 { - nvidia,pins = "lcd_gpio1_pv3"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - lcd_gpio2_pv4 { - nvidia,pins = "lcd_gpio2_pv4"; - nvidia,function = "pwm1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - ap_ready_pv5 { - nvidia,pins = "ap_ready_pv5"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - touch_rst_pv6 { - nvidia,pins = "touch_rst_pv6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - touch_clk_pv7 { - nvidia,pins = "touch_clk_pv7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - modem_wake_ap_px0 { - nvidia,pins = "modem_wake_ap_px0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - touch_int_px1 { - nvidia,pins = "touch_int_px1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - motion_int_px2 { - nvidia,pins = "motion_int_px2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - als_prox_int_px3 { - nvidia,pins = "als_prox_int_px3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - temp_alert_px4 { - nvidia,pins = "temp_alert_px4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - button_power_on_px5 { - nvidia,pins = "button_power_on_px5"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - button_vol_up_px6 { - nvidia,pins = "button_vol_up_px6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - button_vol_down_px7 { - nvidia,pins = "button_vol_down_px7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - button_slide_sw_py0 { - nvidia,pins = "button_slide_sw_py0"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - button_home_py1 { - nvidia,pins = "button_home_py1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - lcd_te_py2 { - nvidia,pins = "lcd_te_py2"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pwr_i2c_scl_py3 { - nvidia,pins = "pwr_i2c_scl_py3"; - nvidia,function = "i2cpmu"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - pwr_i2c_sda_py4 { - nvidia,pins = "pwr_i2c_sda_py4"; - nvidia,function = "i2cpmu"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - clk_32k_out_py5 { - nvidia,pins = "clk_32k_out_py5"; - nvidia,function = "soc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pz0 { - nvidia,pins = "pz0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pz1 { - nvidia,pins = "pz1"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pz2 { - nvidia,pins = "pz2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pz3 { - nvidia,pins = "pz3"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pz4 { - nvidia,pins = "pz4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pz5 { - nvidia,pins = "pz5"; - nvidia,function = "soc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap2_fs_paa0 { - nvidia,pins = "dap2_fs_paa0"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap2_sclk_paa1 { - nvidia,pins = "dap2_sclk_paa1"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap2_din_paa2 { - nvidia,pins = "dap2_din_paa2"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap2_dout_paa3 { - nvidia,pins = "dap2_dout_paa3"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - aud_mclk_pbb0 { - nvidia,pins = "aud_mclk_pbb0"; - nvidia,function = "aud"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dvfs_pwm_pbb1 { - nvidia,pins = "dvfs_pwm_pbb1"; - nvidia,function = "cldvfs"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dvfs_clk_pbb2 { - nvidia,pins = "dvfs_clk_pbb2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gpio_x1_aud_pbb3 { - nvidia,pins = "gpio_x1_aud_pbb3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gpio_x3_aud_pbb4 { - nvidia,pins = "gpio_x3_aud_pbb4"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - hdmi_cec_pcc0 { - nvidia,pins = "hdmi_cec_pcc0"; - nvidia,function = "cec"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - hdmi_int_dp_hpd_pcc1 { - nvidia,pins = "hdmi_int_dp_hpd_pcc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - spdif_out_pcc2 { - nvidia,pins = "spdif_out_pcc2"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spdif_in_pcc3 { - nvidia,pins = "spdif_in_pcc3"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - usb_vbus_en0_pcc4 { - nvidia,pins = "usb_vbus_en0_pcc4"; - nvidia,function = "usb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - usb_vbus_en1_pcc5 { - nvidia,pins = "usb_vbus_en1_pcc5"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - dp_hpd0_pcc6 { - nvidia,pins = "dp_hpd0_pcc6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pcc7 { - nvidia,pins = "pcc7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - spi2_cs1_pdd0 { - nvidia,pins = "spi2_cs1_pdd0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - qspi_sck_pee0 { - nvidia,pins = "qspi_sck_pee0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - qspi_cs_n_pee1 { - nvidia,pins = "qspi_cs_n_pee1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - qspi_io0_pee2 { - nvidia,pins = "qspi_io0_pee2"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - qspi_io1_pee3 { - nvidia,pins = "qspi_io1_pee3"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - qspi_io2_pee4 { - nvidia,pins = "qspi_io2_pee4"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - qspi_io3_pee5 { - nvidia,pins = "qspi_io3_pee5"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - core_pwr_req { - nvidia,pins = "core_pwr_req"; - nvidia,function = "core"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cpu_pwr_req { - nvidia,pins = "cpu_pwr_req"; - nvidia,function = "cpu"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pwr_int_n { - nvidia,pins = "pwr_int_n"; - nvidia,function = "pmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - clk_32k_in { - nvidia,pins = "clk_32k_in"; - nvidia,function = "clk"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - jtag_rtck { - nvidia,pins = "jtag_rtck"; - nvidia,function = "jtag"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - clk_req { - nvidia,pins = "clk_req"; - nvidia,function = "sys"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - shutdown { - nvidia,pins = "shutdown"; - nvidia,function = "shutdown"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/nvidia/tegra210-p2597.dtsi b/sys/gnu/dts/arm64/nvidia/tegra210-p2597.dtsi deleted file mode 100644 index b0095072bc2..00000000000 --- a/sys/gnu/dts/arm64/nvidia/tegra210-p2597.dtsi +++ /dev/null @@ -1,1644 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include - -/ { - model = "NVIDIA Tegra210 P2597 I/O board"; - compatible = "nvidia,p2597", "nvidia,tegra210"; - - host1x@50000000 { - dpaux@54040000 { - status = "okay"; - }; - - sor@54580000 { - status = "okay"; - - avdd-io-supply = <&avdd_1v05>; - vdd-pll-supply = <&vdd_1v8>; - hdmi-supply = <&vdd_hdmi>; - - nvidia,ddc-i2c-bus = <&hdmi_ddc>; - nvidia,hpd-gpio = <&gpio TEGRA_GPIO(CC, 1) - GPIO_ACTIVE_LOW>; - }; - }; - - pinmux: pinmux@700008d4 { - pinctrl-names = "boot"; - pinctrl-0 = <&state_boot>; - - state_boot: pinmux { - pex_l0_rst_n_pa0 { - nvidia,pins = "pex_l0_rst_n_pa0"; - nvidia,function = "pe0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - pex_l0_clkreq_n_pa1 { - nvidia,pins = "pex_l0_clkreq_n_pa1"; - nvidia,function = "pe0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - pex_wake_n_pa2 { - nvidia,pins = "pex_wake_n_pa2"; - nvidia,function = "pe"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - pex_l1_rst_n_pa3 { - nvidia,pins = "pex_l1_rst_n_pa3"; - nvidia,function = "pe1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - pex_l1_clkreq_n_pa4 { - nvidia,pins = "pex_l1_clkreq_n_pa4"; - nvidia,function = "pe1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - sata_led_active_pa5 { - nvidia,pins = "sata_led_active_pa5"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pa6 { - nvidia,pins = "pa6"; - nvidia,function = "sata"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap1_fs_pb0 { - nvidia,pins = "dap1_fs_pb0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap1_din_pb1 { - nvidia,pins = "dap1_din_pb1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap1_dout_pb2 { - nvidia,pins = "dap1_dout_pb2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap1_sclk_pb3 { - nvidia,pins = "dap1_sclk_pb3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi2_mosi_pb4 { - nvidia,pins = "spi2_mosi_pb4"; - nvidia,function = "spi2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi2_miso_pb5 { - nvidia,pins = "spi2_miso_pb5"; - nvidia,function = "spi2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi2_sck_pb6 { - nvidia,pins = "spi2_sck_pb6"; - nvidia,function = "spi2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi2_cs0_pb7 { - nvidia,pins = "spi2_cs0_pb7"; - nvidia,function = "spi2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi1_mosi_pc0 { - nvidia,pins = "spi1_mosi_pc0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi1_miso_pc1 { - nvidia,pins = "spi1_miso_pc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi1_sck_pc2 { - nvidia,pins = "spi1_sck_pc2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi1_cs0_pc3 { - nvidia,pins = "spi1_cs0_pc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi1_cs1_pc4 { - nvidia,pins = "spi1_cs1_pc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi4_sck_pc5 { - nvidia,pins = "spi4_sck_pc5"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi4_cs0_pc6 { - nvidia,pins = "spi4_cs0_pc6"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi4_mosi_pc7 { - nvidia,pins = "spi4_mosi_pc7"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi4_miso_pd0 { - nvidia,pins = "spi4_miso_pd0"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart3_tx_pd1 { - nvidia,pins = "uart3_tx_pd1"; - nvidia,function = "uartc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart3_rx_pd2 { - nvidia,pins = "uart3_rx_pd2"; - nvidia,function = "uartc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart3_rts_pd3 { - nvidia,pins = "uart3_rts_pd3"; - nvidia,function = "uartc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart3_cts_pd4 { - nvidia,pins = "uart3_cts_pd4"; - nvidia,function = "uartc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dmic1_clk_pe0 { - nvidia,pins = "dmic1_clk_pe0"; - nvidia,function = "i2s3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dmic1_dat_pe1 { - nvidia,pins = "dmic1_dat_pe1"; - nvidia,function = "i2s3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dmic2_clk_pe2 { - nvidia,pins = "dmic2_clk_pe2"; - nvidia,function = "i2s3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dmic2_dat_pe3 { - nvidia,pins = "dmic2_dat_pe3"; - nvidia,function = "i2s3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dmic3_clk_pe4 { - nvidia,pins = "dmic3_clk_pe4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dmic3_dat_pe5 { - nvidia,pins = "dmic3_dat_pe5"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pe6 { - nvidia,pins = "pe6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pe7 { - nvidia,pins = "pe7"; - nvidia,function = "pwm3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gen3_i2c_scl_pf0 { - nvidia,pins = "gen3_i2c_scl_pf0"; - nvidia,function = "i2c3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - gen3_i2c_sda_pf1 { - nvidia,pins = "gen3_i2c_sda_pf1"; - nvidia,function = "i2c3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - uart2_tx_pg0 { - nvidia,pins = "uart2_tx_pg0"; - nvidia,function = "uartb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart2_rx_pg1 { - nvidia,pins = "uart2_rx_pg1"; - nvidia,function = "uartb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart2_rts_pg2 { - nvidia,pins = "uart2_rts_pg2"; - nvidia,function = "uartb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart2_cts_pg3 { - nvidia,pins = "uart2_cts_pg3"; - nvidia,function = "uartb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - wifi_en_ph0 { - nvidia,pins = "wifi_en_ph0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - wifi_rst_ph1 { - nvidia,pins = "wifi_rst_ph1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - wifi_wake_ap_ph2 { - nvidia,pins = "wifi_wake_ap_ph2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - ap_wake_bt_ph3 { - nvidia,pins = "ap_wake_bt_ph3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - bt_rst_ph4 { - nvidia,pins = "bt_rst_ph4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - bt_wake_ap_ph5 { - nvidia,pins = "bt_wake_ap_ph5"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - ph6 { - nvidia,pins = "ph6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - ap_wake_nfc_ph7 { - nvidia,pins = "ap_wake_nfc_ph7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - nfc_en_pi0 { - nvidia,pins = "nfc_en_pi0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - nfc_int_pi1 { - nvidia,pins = "nfc_int_pi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gps_en_pi2 { - nvidia,pins = "gps_en_pi2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gps_rst_pi3 { - nvidia,pins = "gps_rst_pi3"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart4_tx_pi4 { - nvidia,pins = "uart4_tx_pi4"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart4_rx_pi5 { - nvidia,pins = "uart4_rx_pi5"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart4_rts_pi6 { - nvidia,pins = "uart4_rts_pi6"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart4_cts_pi7 { - nvidia,pins = "uart4_cts_pi7"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gen1_i2c_sda_pj0 { - nvidia,pins = "gen1_i2c_sda_pj0"; - nvidia,function = "i2c1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - gen1_i2c_scl_pj1 { - nvidia,pins = "gen1_i2c_scl_pj1"; - nvidia,function = "i2c1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - gen2_i2c_scl_pj2 { - nvidia,pins = "gen2_i2c_scl_pj2"; - nvidia,function = "i2c2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - gen2_i2c_sda_pj3 { - nvidia,pins = "gen2_i2c_sda_pj3"; - nvidia,function = "i2c2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - dap4_fs_pj4 { - nvidia,pins = "dap4_fs_pj4"; - nvidia,function = "i2s4b"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap4_din_pj5 { - nvidia,pins = "dap4_din_pj5"; - nvidia,function = "i2s4b"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap4_dout_pj6 { - nvidia,pins = "dap4_dout_pj6"; - nvidia,function = "i2s4b"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap4_sclk_pj7 { - nvidia,pins = "dap4_sclk_pj7"; - nvidia,function = "i2s4b"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pk0 { - nvidia,pins = "pk0"; - nvidia,function = "i2s5b"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pk1 { - nvidia,pins = "pk1"; - nvidia,function = "i2s5b"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pk2 { - nvidia,pins = "pk2"; - nvidia,function = "i2s5b"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pk3 { - nvidia,pins = "pk3"; - nvidia,function = "i2s5b"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pk4 { - nvidia,pins = "pk4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pk5 { - nvidia,pins = "pk5"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pk6 { - nvidia,pins = "pk6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pk7 { - nvidia,pins = "pk7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pl0 { - nvidia,pins = "pl0"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pl1 { - nvidia,pins = "pl1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc1_clk_pm0 { - nvidia,pins = "sdmmc1_clk_pm0"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc1_cmd_pm1 { - nvidia,pins = "sdmmc1_cmd_pm1"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc1_dat3_pm2 { - nvidia,pins = "sdmmc1_dat3_pm2"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc1_dat2_pm3 { - nvidia,pins = "sdmmc1_dat2_pm3"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc1_dat1_pm4 { - nvidia,pins = "sdmmc1_dat1_pm4"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc1_dat0_pm5 { - nvidia,pins = "sdmmc1_dat0_pm5"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc3_clk_pp0 { - nvidia,pins = "sdmmc3_clk_pp0"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc3_cmd_pp1 { - nvidia,pins = "sdmmc3_cmd_pp1"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc3_dat3_pp2 { - nvidia,pins = "sdmmc3_dat3_pp2"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc3_dat2_pp3 { - nvidia,pins = "sdmmc3_dat2_pp3"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc3_dat1_pp4 { - nvidia,pins = "sdmmc3_dat1_pp4"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc3_dat0_pp5 { - nvidia,pins = "sdmmc3_dat0_pp5"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam1_mclk_ps0 { - nvidia,pins = "cam1_mclk_ps0"; - nvidia,function = "extperiph3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam2_mclk_ps1 { - nvidia,pins = "cam2_mclk_ps1"; - nvidia,function = "extperiph3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam_i2c_scl_ps2 { - nvidia,pins = "cam_i2c_scl_ps2"; - nvidia,function = "i2cvi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - cam_i2c_sda_ps3 { - nvidia,pins = "cam_i2c_sda_ps3"; - nvidia,function = "i2cvi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - cam_rst_ps4 { - nvidia,pins = "cam_rst_ps4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam_af_en_ps5 { - nvidia,pins = "cam_af_en_ps5"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam_flash_en_ps6 { - nvidia,pins = "cam_flash_en_ps6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam1_pwdn_ps7 { - nvidia,pins = "cam1_pwdn_ps7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam2_pwdn_pt0 { - nvidia,pins = "cam2_pwdn_pt0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam1_strobe_pt1 { - nvidia,pins = "cam1_strobe_pt1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart1_tx_pu0 { - nvidia,pins = "uart1_tx_pu0"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart1_rx_pu1 { - nvidia,pins = "uart1_rx_pu1"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart1_rts_pu2 { - nvidia,pins = "uart1_rts_pu2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart1_cts_pu3 { - nvidia,pins = "uart1_cts_pu3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - lcd_bl_pwm_pv0 { - nvidia,pins = "lcd_bl_pwm_pv0"; - nvidia,function = "pwm0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - lcd_bl_en_pv1 { - nvidia,pins = "lcd_bl_en_pv1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - lcd_rst_pv2 { - nvidia,pins = "lcd_rst_pv2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - lcd_gpio1_pv3 { - nvidia,pins = "lcd_gpio1_pv3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - lcd_gpio2_pv4 { - nvidia,pins = "lcd_gpio2_pv4"; - nvidia,function = "pwm1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - ap_ready_pv5 { - nvidia,pins = "ap_ready_pv5"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - touch_rst_pv6 { - nvidia,pins = "touch_rst_pv6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - touch_clk_pv7 { - nvidia,pins = "touch_clk_pv7"; - nvidia,function = "touch"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - modem_wake_ap_px0 { - nvidia,pins = "modem_wake_ap_px0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - touch_int_px1 { - nvidia,pins = "touch_int_px1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - motion_int_px2 { - nvidia,pins = "motion_int_px2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - als_prox_int_px3 { - nvidia,pins = "als_prox_int_px3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - temp_alert_px4 { - nvidia,pins = "temp_alert_px4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - button_power_on_px5 { - nvidia,pins = "button_power_on_px5"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - button_vol_up_px6 { - nvidia,pins = "button_vol_up_px6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - button_vol_down_px7 { - nvidia,pins = "button_vol_down_px7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - button_slide_sw_py0 { - nvidia,pins = "button_slide_sw_py0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - button_home_py1 { - nvidia,pins = "button_home_py1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - lcd_te_py2 { - nvidia,pins = "lcd_te_py2"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pwr_i2c_scl_py3 { - nvidia,pins = "pwr_i2c_scl_py3"; - nvidia,function = "i2cpmu"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - pwr_i2c_sda_py4 { - nvidia,pins = "pwr_i2c_sda_py4"; - nvidia,function = "i2cpmu"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - clk_32k_out_py5 { - nvidia,pins = "clk_32k_out_py5"; - nvidia,function = "soc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pz0 { - nvidia,pins = "pz0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pz1 { - nvidia,pins = "pz1"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pz2 { - nvidia,pins = "pz2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pz3 { - nvidia,pins = "pz3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pz4 { - nvidia,pins = "pz4"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pz5 { - nvidia,pins = "pz5"; - nvidia,function = "soc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap2_fs_paa0 { - nvidia,pins = "dap2_fs_paa0"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap2_sclk_paa1 { - nvidia,pins = "dap2_sclk_paa1"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap2_din_paa2 { - nvidia,pins = "dap2_din_paa2"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap2_dout_paa3 { - nvidia,pins = "dap2_dout_paa3"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - aud_mclk_pbb0 { - nvidia,pins = "aud_mclk_pbb0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dvfs_pwm_pbb1 { - nvidia,pins = "dvfs_pwm_pbb1"; - nvidia,function = "cldvfs"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dvfs_clk_pbb2 { - nvidia,pins = "dvfs_clk_pbb2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gpio_x1_aud_pbb3 { - nvidia,pins = "gpio_x1_aud_pbb3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gpio_x3_aud_pbb4 { - nvidia,pins = "gpio_x3_aud_pbb4"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - hdmi_cec_pcc0 { - nvidia,pins = "hdmi_cec_pcc0"; - nvidia,function = "cec"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - hdmi_int_dp_hpd_pcc1 { - nvidia,pins = "hdmi_int_dp_hpd_pcc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - spdif_out_pcc2 { - nvidia,pins = "spdif_out_pcc2"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spdif_in_pcc3 { - nvidia,pins = "spdif_in_pcc3"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - usb_vbus_en0_pcc4 { - nvidia,pins = "usb_vbus_en0_pcc4"; - nvidia,function = "usb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - usb_vbus_en1_pcc5 { - nvidia,pins = "usb_vbus_en1_pcc5"; - nvidia,function = "usb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - dp_hpd0_pcc6 { - nvidia,pins = "dp_hpd0_pcc6"; - nvidia,function = "dp"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pcc7 { - nvidia,pins = "pcc7"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - spi2_cs1_pdd0 { - nvidia,pins = "spi2_cs1_pdd0"; - nvidia,function = "spi2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - qspi_sck_pee0 { - nvidia,pins = "qspi_sck_pee0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - qspi_cs_n_pee1 { - nvidia,pins = "qspi_cs_n_pee1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - qspi_io0_pee2 { - nvidia,pins = "qspi_io0_pee2"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - qspi_io1_pee3 { - nvidia,pins = "qspi_io1_pee3"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - qspi_io2_pee4 { - nvidia,pins = "qspi_io2_pee4"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - qspi_io3_pee5 { - nvidia,pins = "qspi_io3_pee5"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - core_pwr_req { - nvidia,pins = "core_pwr_req"; - nvidia,function = "core"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cpu_pwr_req { - nvidia,pins = "cpu_pwr_req"; - nvidia,function = "cpu"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pwr_int_n { - nvidia,pins = "pwr_int_n"; - nvidia,function = "pmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - clk_32k_in { - nvidia,pins = "clk_32k_in"; - nvidia,function = "clk"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - jtag_rtck { - nvidia,pins = "jtag_rtck"; - nvidia,function = "jtag"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - clk_req { - nvidia,pins = "clk_req"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - shutdown { - nvidia,pins = "shutdown"; - nvidia,function = "shutdown"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - }; - - dvfs_pwm_active_state: dvfs_pwm_active { - dvfs_pwm_pbb1 { - nvidia,pins = "dvfs_pwm_pbb1"; - nvidia,tristate = ; - }; - }; - - dvfs_pwm_inactive_state: dvfs_pwm_inactive { - dvfs_pwm_pbb1 { - nvidia,pins = "dvfs_pwm_pbb1"; - nvidia,tristate = ; - }; - }; - }; - - pwm@7000a000 { - status = "okay"; - }; - - i2c@7000c400 { - status = "okay"; - clock-frequency = <100000>; - - exp1: gpio@74 { - compatible = "ti,tca9539"; - reg = <0x74>; - - #gpio-cells = <2>; - gpio-controller; - }; - }; - - /* HDMI DDC */ - hdmi_ddc: i2c@7000c700 { - status = "okay"; - clock-frequency = <100000>; - }; - - sata@70020000 { - status = "okay"; - phys = <&{/padctl@7009f000/pads/sata/lanes/sata-0}>; - }; - - hda@70030000 { - nvidia,model = "jetson-tx1-hda"; - status = "okay"; - }; - - usb@70090000 { - phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>, - <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>, - <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>, - <&{/padctl@7009f000/pads/usb2/lanes/usb2-3}>, - <&{/padctl@7009f000/pads/pcie/lanes/pcie-6}>, - <&{/padctl@7009f000/pads/pcie/lanes/pcie-5}>; - phy-names = "usb2-0", "usb2-1", "usb2-2", "usb2-3", "usb3-0", - "usb3-1"; - - dvddio-pex-supply = <&vdd_pex_1v05>; - hvddio-pex-supply = <&vdd_1v8>; - avdd-usb-supply = <&vdd_3v3_sys>; - /* XXX what are these? */ - avdd-pll-utmip-supply = <&vdd_1v8>; - avdd-pll-uerefe-supply = <&vdd_pex_1v05>; - dvdd-usb-ss-pll-supply = <&vdd_pex_1v05>; - hvdd-usb-ss-pll-e-supply = <&vdd_1v8>; - - status = "okay"; - }; - - padctl@7009f000 { - status = "okay"; - - avdd-pll-utmip-supply = <&vdd_1v8>; - avdd-pll-uerefe-supply = <&avdd_1v05_pll>; - dvdd-pex-pll-supply = <&vdd_pex_1v05>; - hvdd-pex-pll-e-supply = <&vdd_1v8>; - - pads { - usb2 { - status = "okay"; - - lanes { - usb2-0 { - nvidia,function = "xusb"; - status = "okay"; - }; - - usb2-1 { - nvidia,function = "xusb"; - status = "okay"; - }; - - usb2-2 { - nvidia,function = "xusb"; - status = "okay"; - }; - - usb2-3 { - nvidia,function = "xusb"; - status = "okay"; - }; - }; - }; - - pcie { - status = "okay"; - - lanes { - pcie-0 { - nvidia,function = "pcie-x1"; - status = "okay"; - }; - - pcie-1 { - nvidia,function = "pcie-x4"; - status = "okay"; - }; - - pcie-2 { - nvidia,function = "pcie-x4"; - status = "okay"; - }; - - pcie-3 { - nvidia,function = "pcie-x4"; - status = "okay"; - }; - - pcie-4 { - nvidia,function = "pcie-x4"; - status = "okay"; - }; - - pcie-5 { - nvidia,function = "usb3-ss"; - status = "okay"; - }; - - pcie-6 { - nvidia,function = "usb3-ss"; - status = "okay"; - }; - }; - }; - - sata { - status = "okay"; - - lanes { - sata-0 { - nvidia,function = "sata"; - status = "okay"; - }; - }; - }; - }; - - ports { - usb2-0 { - status = "okay"; - mode = "otg"; - }; - - usb2-1 { - status = "okay"; - vbus-supply = <&vdd_5v0_rtl>; - mode = "host"; - }; - - usb2-2 { - status = "okay"; - vbus-supply = <&vdd_usb_vbus>; - mode = "host"; - }; - - usb2-3 { - status = "okay"; - mode = "host"; - }; - - usb3-0 { - nvidia,usb2-companion = <1>; - status = "okay"; - }; - - usb3-1 { - nvidia,usb2-companion = <2>; - status = "okay"; - }; - }; - }; - - /* MMC/SD */ - sdhci@700b0000 { - status = "okay"; - bus-width = <4>; - - cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>; - - vqmmc-supply = <&vddio_sdmmc>; - vmmc-supply = <&vdd_3v3_sd>; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - vdd_sys_mux: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "VDD_SYS_MUX"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_5v0_sys: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "VDD_5V0_SYS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_sys_mux>; - }; - - vdd_3v3_sys: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "VDD_3V3_SYS"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - gpio = <&pmic 3 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_sys_mux>; - - regulator-enable-ramp-delay = <160>; - regulator-disable-ramp-delay = <10000>; - }; - - vdd_5v0_io: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "VDD_5V0_IO_SYS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_3v3_sd: regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "VDD_3V3_SD"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio TEGRA_GPIO(Z, 4) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_3v3_sys>; - - regulator-enable-ramp-delay = <472>; - regulator-disable-ramp-delay = <4880>; - }; - - vdd_dsi_csi: regulator@5 { - compatible = "regulator-fixed"; - reg = <5>; - regulator-name = "AVDD_DSI_CSI_1V2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - vin-supply = <&vdd_sys_1v2>; - }; - - vdd_3v3_dis: regulator@6 { - compatible = "regulator-fixed"; - reg = <6>; - regulator-name = "VDD_DIS_3V3_LCD"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - gpio = <&exp1 3 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_3v3_sys>; - }; - - vdd_1v8_dis: regulator@7 { - compatible = "regulator-fixed"; - reg = <7>; - regulator-name = "VDD_LCD_1V8_DIS"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - gpio = <&exp1 14 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_1v8>; - }; - - vdd_5v0_rtl: regulator@8 { - compatible = "regulator-fixed"; - reg = <8>; - regulator-name = "RTL_5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_5v0_sys>; - }; - - vdd_usb_vbus: regulator@9 { - compatible = "regulator-fixed"; - reg = <9>; - regulator-name = "USB_VBUS_EN1"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(CC, 5) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_5v0_sys>; - }; - - vdd_hdmi: regulator@10 { - compatible = "regulator-fixed"; - reg = <10>; - regulator-name = "VDD_HDMI_5V0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&exp1 12 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_5v0_sys>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - label = "gpio-keys"; - - power { - label = "Power"; - gpios = <&gpio TEGRA_GPIO(X, 5) GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - - volume_down { - label = "Volume Down"; - gpios = <&gpio TEGRA_GPIO(Y, 0) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - volume_up { - label = "Volume Up"; - gpios = <&gpio TEGRA_GPIO(X, 6) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/nvidia/tegra210-p2894-0050-a08.dts b/sys/gnu/dts/arm64/nvidia/tegra210-p2894-0050-a08.dts deleted file mode 100644 index 7ffb351b588..00000000000 --- a/sys/gnu/dts/arm64/nvidia/tegra210-p2894-0050-a08.dts +++ /dev/null @@ -1,9 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "tegra210-p2894.dtsi" - -/ { - model = "NVIDIA Shield TV"; - compatible = "nvidia,p2894-0050-a08", "nvidia,darcy", "nvidia,tegra210"; -}; diff --git a/sys/gnu/dts/arm64/nvidia/tegra210-p2894.dtsi b/sys/gnu/dts/arm64/nvidia/tegra210-p2894.dtsi deleted file mode 100644 index 88a4b9333d8..00000000000 --- a/sys/gnu/dts/arm64/nvidia/tegra210-p2894.dtsi +++ /dev/null @@ -1,1864 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -#include -#include -#include -#include -#include "tegra210.dtsi" - -/ { - aliases { - serial0 = &uarta; - }; - - chosen { - bootargs = "earlycon"; - stdout-path = "serial0:115200n8"; - }; - - memory { - device_type = "memory"; - reg = <0x0 0x80000000 0x0 0xc0000000>; - }; - - pinmux: pinmux@700008d4 { - status = "okay"; - pinctrl-names = "boot"; - pinctrl-0 = <&state_boot>; - - state_boot: pinmux { - pex_l0_rst_n_pa0 { - nvidia,pins = "pex_l0_rst_n_pa0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - pex_l0_clkreq_n_pa1 { - nvidia,pins = "pex_l0_clkreq_n_pa1"; - nvidia,function = "pe0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - pex_wake_n_pa2 { - nvidia,pins = "pex_wake_n_pa2"; - nvidia,function = "pe"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - pex_l1_rst_n_pa3 { - nvidia,pins = "pex_l1_rst_n_pa3"; - nvidia,function = "pe1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - pex_l1_clkreq_n_pa4 { - nvidia,pins = "pex_l1_clkreq_n_pa4"; - nvidia,function = "pe1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - sata_led_active_pa5 { - nvidia,pins = "sata_led_active_pa5"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pa6 { - nvidia,pins = "pa6"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap1_fs_pb0 { - nvidia,pins = "dap1_fs_pb0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap1_din_pb1 { - nvidia,pins = "dap1_din_pb1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap1_dout_pb2 { - nvidia,pins = "dap1_dout_pb2"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap1_sclk_pb3 { - nvidia,pins = "dap1_sclk_pb3"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi2_mosi_pb4 { - nvidia,pins = "spi2_mosi_pb4"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi2_miso_pb5 { - nvidia,pins = "spi2_miso_pb5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi2_sck_pb6 { - nvidia,pins = "spi2_sck_pb6"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi2_cs0_pb7 { - nvidia,pins = "spi2_cs0_pb7"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi1_mosi_pc0 { - nvidia,pins = "spi1_mosi_pc0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi1_miso_pc1 { - nvidia,pins = "spi1_miso_pc1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi1_sck_pc2 { - nvidia,pins = "spi1_sck_pc2"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi1_cs0_pc3 { - nvidia,pins = "spi1_cs0_pc3"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi1_cs1_pc4 { - nvidia,pins = "spi1_cs1_pc4"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi4_sck_pc5 { - nvidia,pins = "spi4_sck_pc5"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi4_cs0_pc6 { - nvidia,pins = "spi4_cs0_pc6"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi4_mosi_pc7 { - nvidia,pins = "spi4_mosi_pc7"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi4_miso_pd0 { - nvidia,pins = "spi4_miso_pd0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart3_tx_pd1 { - nvidia,pins = "uart3_tx_pd1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart3_rx_pd2 { - nvidia,pins = "uart3_rx_pd2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart3_rts_pd3 { - nvidia,pins = "uart3_rts_pd3"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart3_cts_pd4 { - nvidia,pins = "uart3_cts_pd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dmic1_clk_pe0 { - nvidia,pins = "dmic1_clk_pe0"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dmic1_dat_pe1 { - nvidia,pins = "dmic1_dat_pe1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dmic2_clk_pe2 { - nvidia,pins = "dmic2_clk_pe2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dmic2_dat_pe3 { - nvidia,pins = "dmic2_dat_pe3"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dmic3_clk_pe4 { - nvidia,pins = "dmic3_clk_pe4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dmic3_dat_pe5 { - nvidia,pins = "dmic3_dat_pe5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pe6 { - nvidia,pins = "pe6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pe7 { - nvidia,pins = "pe7"; - nvidia,function = "pwm3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gen3_i2c_scl_pf0 { - nvidia,pins = "gen3_i2c_scl_pf0"; - nvidia,function = "i2c3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - gen3_i2c_sda_pf1 { - nvidia,pins = "gen3_i2c_sda_pf1"; - nvidia,function = "i2c3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - uart2_tx_pg0 { - nvidia,pins = "uart2_tx_pg0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart2_rx_pg1 { - nvidia,pins = "uart2_rx_pg1"; - nvidia,function = "uartb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart2_rts_pg2 { - nvidia,pins = "uart2_rts_pg2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart2_cts_pg3 { - nvidia,pins = "uart2_cts_pg3"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - wifi_en_ph0 { - nvidia,pins = "wifi_en_ph0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - wifi_rst_ph1 { - nvidia,pins = "wifi_rst_ph1"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - wifi_wake_ap_ph2 { - nvidia,pins = "wifi_wake_ap_ph2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - ap_wake_bt_ph3 { - nvidia,pins = "ap_wake_bt_ph3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - bt_rst_ph4 { - nvidia,pins = "bt_rst_ph4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - bt_wake_ap_ph5 { - nvidia,pins = "bt_wake_ap_ph5"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - ph6 { - nvidia,pins = "ph6"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - ap_wake_nfc_ph7 { - nvidia,pins = "ap_wake_nfc_ph7"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - nfc_en_pi0 { - nvidia,pins = "nfc_en_pi0"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - nfc_int_pi1 { - nvidia,pins = "nfc_int_pi1"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gps_en_pi2 { - nvidia,pins = "gps_en_pi2"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gps_rst_pi3 { - nvidia,pins = "gps_rst_pi3"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart4_tx_pi4 { - nvidia,pins = "uart4_tx_pi4"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart4_rx_pi5 { - nvidia,pins = "uart4_rx_pi5"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart4_rts_pi6 { - nvidia,pins = "uart4_rts_pi6"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart4_cts_pi7 { - nvidia,pins = "uart4_cts_pi7"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gen1_i2c_sda_pj0 { - nvidia,pins = "gen1_i2c_sda_pj0"; - nvidia,function = "i2c1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - gen1_i2c_scl_pj1 { - nvidia,pins = "gen1_i2c_scl_pj1"; - nvidia,function = "i2c1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - gen2_i2c_scl_pj2 { - nvidia,pins = "gen2_i2c_scl_pj2"; - nvidia,function = "i2c2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - gen2_i2c_sda_pj3 { - nvidia,pins = "gen2_i2c_sda_pj3"; - nvidia,function = "i2c2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - dap4_fs_pj4 { - nvidia,pins = "dap4_fs_pj4"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap4_din_pj5 { - nvidia,pins = "dap4_din_pj5"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap4_dout_pj6 { - nvidia,pins = "dap4_dout_pj6"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap4_sclk_pj7 { - nvidia,pins = "dap4_sclk_pj7"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pk0 { - nvidia,pins = "pk0"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pk1 { - nvidia,pins = "pk1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pk2 { - nvidia,pins = "pk2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pk3 { - nvidia,pins = "pk3"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pk4 { - nvidia,pins = "pk4"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pk5 { - nvidia,pins = "pk5"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pk6 { - nvidia,pins = "pk6"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pk7 { - nvidia,pins = "pk7"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pl0 { - nvidia,pins = "pl0"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pl1 { - nvidia,pins = "pl1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc1_clk_pm0 { - nvidia,pins = "sdmmc1_clk_pm0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc1_cmd_pm1 { - nvidia,pins = "sdmmc1_cmd_pm1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc1_dat3_pm2 { - nvidia,pins = "sdmmc1_dat3_pm2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc1_dat2_pm3 { - nvidia,pins = "sdmmc1_dat2_pm3"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc1_dat1_pm4 { - nvidia,pins = "sdmmc1_dat1_pm4"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc1_dat0_pm5 { - nvidia,pins = "sdmmc1_dat0_pm5"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc3_clk_pp0 { - nvidia,pins = "sdmmc3_clk_pp0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc3_cmd_pp1 { - nvidia,pins = "sdmmc3_cmd_pp1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc3_dat3_pp2 { - nvidia,pins = "sdmmc3_dat3_pp2"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc3_dat2_pp3 { - nvidia,pins = "sdmmc3_dat2_pp3"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc3_dat1_pp4 { - nvidia,pins = "sdmmc3_dat1_pp4"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc3_dat0_pp5 { - nvidia,pins = "sdmmc3_dat0_pp5"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam1_mclk_ps0 { - nvidia,pins = "cam1_mclk_ps0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam2_mclk_ps1 { - nvidia,pins = "cam2_mclk_ps1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam_i2c_scl_ps2 { - nvidia,pins = "cam_i2c_scl_ps2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - cam_i2c_sda_ps3 { - nvidia,pins = "cam_i2c_sda_ps3"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - cam_rst_ps4 { - nvidia,pins = "cam_rst_ps4"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam_af_en_ps5 { - nvidia,pins = "cam_af_en_ps5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam_flash_en_ps6 { - nvidia,pins = "cam_flash_en_ps6"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam1_pwdn_ps7 { - nvidia,pins = "cam1_pwdn_ps7"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam2_pwdn_pt0 { - nvidia,pins = "cam2_pwdn_pt0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam1_strobe_pt1 { - nvidia,pins = "cam1_strobe_pt1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart1_tx_pu0 { - nvidia,pins = "uart1_tx_pu0"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart1_rx_pu1 { - nvidia,pins = "uart1_rx_pu1"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart1_rts_pu2 { - nvidia,pins = "uart1_rts_pu2"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart1_cts_pu3 { - nvidia,pins = "uart1_cts_pu3"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - lcd_bl_pwm_pv0 { - nvidia,pins = "lcd_bl_pwm_pv0"; - nvidia,function = "pwm0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - lcd_bl_en_pv1 { - nvidia,pins = "lcd_bl_en_pv1"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - lcd_rst_pv2 { - nvidia,pins = "lcd_rst_pv2"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - lcd_gpio1_pv3 { - nvidia,pins = "lcd_gpio1_pv3"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - lcd_gpio2_pv4 { - nvidia,pins = "lcd_gpio2_pv4"; - nvidia,function = "pwm1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - ap_ready_pv5 { - nvidia,pins = "ap_ready_pv5"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - touch_rst_pv6 { - nvidia,pins = "touch_rst_pv6"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - touch_clk_pv7 { - nvidia,pins = "touch_clk_pv7"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - modem_wake_ap_px0 { - nvidia,pins = "modem_wake_ap_px0"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - touch_int_px1 { - nvidia,pins = "touch_int_px1"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - motion_int_px2 { - nvidia,pins = "motion_int_px2"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - als_prox_int_px3 { - nvidia,pins = "als_prox_int_px3"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - temp_alert_px4 { - nvidia,pins = "temp_alert_px4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - button_power_on_px5 { - nvidia,pins = "button_power_on_px5"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - button_vol_up_px6 { - nvidia,pins = "button_vol_up_px6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - button_vol_down_px7 { - nvidia,pins = "button_vol_down_px7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - button_slide_sw_py0 { - nvidia,pins = "button_slide_sw_py0"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - button_home_py1 { - nvidia,pins = "button_home_py1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - lcd_te_py2 { - nvidia,pins = "lcd_te_py2"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pwr_i2c_scl_py3 { - nvidia,pins = "pwr_i2c_scl_py3"; - nvidia,function = "i2cpmu"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - pwr_i2c_sda_py4 { - nvidia,pins = "pwr_i2c_sda_py4"; - nvidia,function = "i2cpmu"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - clk_32k_out_py5 { - nvidia,pins = "clk_32k_out_py5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pz0 { - nvidia,pins = "pz0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pz1 { - nvidia,pins = "pz1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pz2 { - nvidia,pins = "pz2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pz3 { - nvidia,pins = "pz3"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pz4 { - nvidia,pins = "pz4"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pz5 { - nvidia,pins = "pz5"; - nvidia,function = "soc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap2_fs_paa0 { - nvidia,pins = "dap2_fs_paa0"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap2_sclk_paa1 { - nvidia,pins = "dap2_sclk_paa1"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap2_din_paa2 { - nvidia,pins = "dap2_din_paa2"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap2_dout_paa3 { - nvidia,pins = "dap2_dout_paa3"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - aud_mclk_pbb0 { - nvidia,pins = "aud_mclk_pbb0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dvfs_pwm_pbb1 { - nvidia,pins = "dvfs_pwm_pbb1"; - nvidia,function = "cldvfs"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dvfs_clk_pbb2 { - nvidia,pins = "dvfs_clk_pbb2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gpio_x1_aud_pbb3 { - nvidia,pins = "gpio_x1_aud_pbb3"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gpio_x3_aud_pbb4 { - nvidia,pins = "gpio_x3_aud_pbb4"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - hdmi_cec_pcc0 { - nvidia,pins = "hdmi_cec_pcc0"; - nvidia,function = "cec"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - hdmi_int_dp_hpd_pcc1 { - nvidia,pins = "hdmi_int_dp_hpd_pcc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - spdif_out_pcc2 { - nvidia,pins = "spdif_out_pcc2"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spdif_in_pcc3 { - nvidia,pins = "spdif_in_pcc3"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - usb_vbus_en0_pcc4 { - nvidia,pins = "usb_vbus_en0_pcc4"; - nvidia,function = "usb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - usb_vbus_en1_pcc5 { - nvidia,pins = "usb_vbus_en1_pcc5"; - nvidia,function = "usb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - dp_hpd0_pcc6 { - nvidia,pins = "dp_hpd0_pcc6"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pcc7 { - nvidia,pins = "pcc7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - spi2_cs1_pdd0 { - nvidia,pins = "spi2_cs1_pdd0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - qspi_sck_pee0 { - nvidia,pins = "qspi_sck_pee0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - qspi_cs_n_pee1 { - nvidia,pins = "qspi_cs_n_pee1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - qspi_io0_pee2 { - nvidia,pins = "qspi_io0_pee2"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - qspi_io1_pee3 { - nvidia,pins = "qspi_io1_pee3"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - qspi_io2_pee4 { - nvidia,pins = "qspi_io2_pee4"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - qspi_io3_pee5 { - nvidia,pins = "qspi_io3_pee5"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - core_pwr_req { - nvidia,pins = "core_pwr_req"; - nvidia,function = "core"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cpu_pwr_req { - nvidia,pins = "cpu_pwr_req"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pwr_int_n { - nvidia,pins = "pwr_int_n"; - nvidia,function = "pmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - clk_32k_in { - nvidia,pins = "clk_32k_in"; - nvidia,function = "clk"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - jtag_rtck { - nvidia,pins = "jtag_rtck"; - nvidia,function = "jtag"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - clk_req { - nvidia,pins = "clk_req"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - shutdown { - nvidia,pins = "shutdown"; - nvidia,function = "shutdown"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - }; - }; - - serial@70006000 { - status = "okay"; - }; - - i2c@7000d000 { - status = "okay"; - clock-frequency = <400000>; - - max77620: max77620@3c { - compatible = "maxim,max77620"; - reg = <0x3c>; - interrupts = ; - - #interrupt-cells = <2>; - interrupt-controller; - - gpio-controller; - #gpio-cells = <2>; - - pinctrl-names = "default"; - pinctrl-0 = <&max77620_default>; - - max77620_default: pinmux@0 { - pin_gpio0 { - pins = "gpio0"; - function = "gpio"; - }; - - pin_gpio1 { - pins = "gpio1"; - function = "fps-out"; - drive-push-pull = <1>; - maxim,active-fps-source = ; - maxim,active-fps-power-up-slot = <7>; - maxim,active-fps-power-down-slot = <0>; - }; - - pin_gpio2_3 { - pins = "gpio2", "gpio3"; - function = "fps-out"; - drive-open-drain = <1>; - maxim,active-fps-source = ; - }; - - pin_gpio4 { - pins = "gpio4"; - function = "32k-out1"; - }; - - pin_gpio5_6_7 { - pins = "gpio5", "gpio6", "gpio7"; - function = "gpio"; - drive-push-pull = <1>; - }; - - pin_gpio2 { - maxim,active-fps-source = ; - }; - - pin_gpio3 { - maxim,active-fps-source = ; - }; - }; - - spmic-default-output-high { - gpio-hog; - output-high; - gpios = <2 GPIO_ACTIVE_HIGH 7 GPIO_ACTIVE_HIGH>; - }; - - fps { - #address-cells = <1>; - #size-cells = <0>; - - fps0 { - reg = <0>; - maxim,fps-event-source = ; - }; - - fps1 { - reg = <1>; - maxim,fps-event-source = ; - maxim,device-state-on-disabled-event = ; - }; - - fps2 { - reg = <2>; - maxim,fps-event-source = ; - }; - }; - - regulators { - in-ldo0-1-supply = <&max77620_sd2>; - in-ldo7-8-supply = <&max77620_sd2>; - - max77620_sd0: sd0 { - regulator-name = "vdd-core"; - regulator-enable-ramp-delay = <146>; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1400000>; - regulator-ramp-delay = <27500>; - regulator-always-on; - regulator-boot-on; - - maxim,active-fps-power-up-slot = <0>; - maxim,active-fps-source = ; - }; - - max77620_sd1: sd1 { - regulator-name = "vddio-ddr"; - regulator-enable-ramp-delay = <130>; - regulator-ramp-delay = <27500>; - regulator-always-on; - regulator-boot-on; - - maxim,active-fps-source = ; - }; - - max77620_sd2: sd2 { - regulator-name = "vdd-pre-reg"; - regulator-enable-ramp-delay = <176>; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-ramp-delay = <27500>; - regulator-always-on; - regulator-boot-on; - - maxim,active-fps-source = ; - maxim,suspend-fps-source = ; - }; - - max77620_sd3: sd3 { - regulator-name = "vdd-1v8"; - regulator-enable-ramp-delay = <242>; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-ramp-delay = <27500>; - regulator-always-on; - regulator-boot-on; - - maxim,active-fps-source = ; - }; - - max77620_ldo0: ldo0 { - regulator-name = "avdd-sys"; - regulator-enable-ramp-delay = <26>; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-ramp-delay = <100000>; - regulator-boot-on; - - maxim,active-fps-source = ; - }; - - max77620_ldo1: ldo1 { - regulator-name = "vdd-pex"; - regulator-enable-ramp-delay = <22>; - regulator-min-microvolt = <1075000>; - regulator-max-microvolt = <1075000>; - regulator-ramp-delay = <100000>; - regulator-always-on; - - maxim,active-fps-source = ; - }; - - max77620_ldo2: ldo2 { - regulator-name = "vddio-sdmmc3"; - regulator-enable-ramp-delay = <62>; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <100000>; - - maxim,active-fps-source = ; - }; - - max77620_ldo3: ldo3 { - regulator-name = "vdd-3v3-eth"; - regulator-enable-ramp-delay = <50>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <100000>; - regulator-always-on; - regulator-boot-on; - - maxim,active-fps-source = ; - }; - - max77620_ldo4: ldo4 { - regulator-name = "vdd-rtc"; - regulator-enable-ramp-delay = <22>; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - regulator-ramp-delay = <100000>; - regulator-always-on; - regulator-boot-on; - - maxim,active-fps-source = ; - }; - - max77620_ldo5: ldo5 { - regulator-name = "avdd-ts-hv"; - regulator-enable-ramp-delay = <62>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <100000>; - - maxim,active-fps-source = ; - }; - - max77620_ldo6: ldo6 { - regulator-name = "vdd-ts"; - regulator-enable-ramp-delay = <36>; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-ramp-delay = <100000>; - regulator-boot-on; - - maxim,active-fps-source = ; - }; - - max77620_ldo7: ldo7 { - regulator-name = "vdd-gen-pll-edp"; - regulator-enable-ramp-delay = <24>; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <100000>; - regulator-always-on; - regulator-boot-on; - - maxim,active-fps-source = ; - maxim,suspend-fps-source = ; - }; - - max77620_ldo8: ldo8 { - regulator-name = "vdd-hdmi-dp"; - regulator-enable-ramp-delay = <22>; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <100000>; - regulator-always-on; - regulator-boot-on; - - maxim,active-fps-source = ; - }; - }; - }; - }; - - pmc@7000e400 { - nvidia,invert-interrupt; - nvidia,suspend-mode = <0>; - nvidia,cpu-pwr-good-time = <0>; - nvidia,cpu-pwr-off-time = <0>; - nvidia,core-pwr-good-time = <4587 3876>; - nvidia,core-pwr-off-time = <39065>; - nvidia,core-power-req-active-high; - nvidia,sys-clock-req-active-high; - status = "okay"; - }; - - sdhci@700b0600 { - bus-width = <8>; - non-removable; - status = "okay"; - }; - - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - status = "okay"; - - power { - debounce-interval = <30>; - gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>; - label = "Power"; - linux,code = ; - wakeup-event-action = ; - wakeup-source; - }; - }; - - cpus { - cpu@0 { - enable-method = "psci"; - }; - - cpu@1 { - enable-method = "psci"; - }; - - cpu@2 { - enable-method = "psci"; - }; - - cpu@3 { - enable-method = "psci"; - }; - - idle-states { - cpu-sleep { - status = "okay"; - }; - }; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - regulators { - compatible = "simple-bus"; - device_type = "fixed-regulators"; - #address-cells = <1>; - #size-cells = <0>; - - battery_reg: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "vdd-ac-bat"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - vdd_3v3: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "vdd-3v3"; - regulator-enable-ramp-delay = <160>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - - gpio = <&max77620 3 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - max77620_gpio7: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "max77620-gpio7"; - regulator-enable-ramp-delay = <240>; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - vin-supply = <&max77620_ldo0>; - regulator-always-on; - regulator-boot-on; - - gpio = <&max77620 7 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - lcd_bl_en: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "lcd-bl-en"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - - gpio = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - en_vdd_sd: regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "en-vdd-sd"; - regulator-enable-ramp-delay = <472>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vdd_3v3>; - - gpio = <&gpio TEGRA_GPIO(Z, 4) GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - en_vdd_cam: regulator@5 { - compatible = "regulator-fixed"; - reg = <5>; - regulator-name = "en-vdd-cam"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - gpio = <&gpio TEGRA_GPIO(S, 4) GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vdd_sys_boost: regulator@6 { - compatible = "regulator-fixed"; - reg = <6>; - regulator-name = "vdd-sys-boost"; - regulator-enable-ramp-delay = <3090>; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - - gpio = <&max77620 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vdd_hdmi: regulator@7 { - compatible = "regulator-fixed"; - reg = <7>; - regulator-name = "vdd-hdmi"; - regulator-enable-ramp-delay = <468>; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vdd_sys_boost>; - regulator-boot-on; - - gpio = <&gpio TEGRA_GPIO(CC, 7) GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - en_vdd_cpu_fixed: regulator@8 { - compatible = "regulator-fixed"; - reg = <8>; - regulator-name = "vdd-cpu-fixed"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - }; - - vdd_aux_3v3: regulator@9 { - compatible = "regulator-fixed"; - reg = <9>; - regulator-name = "aux-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vdd_snsr_pm: regulator@10 { - compatible = "regulator-fixed"; - reg = <10>; - regulator-name = "snsr_pm"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - enable-active-high; - }; - - vdd_usb_5v0: regulator@11 { - compatible = "regulator-fixed"; - reg = <11>; - status = "disabled"; - regulator-name = "vdd-usb-5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vdd_3v3>; - - enable-active-high; - }; - - vdd_cdc_1v2_aud: regulator@101 { - compatible = "regulator-fixed"; - reg = <101>; - status = "disabled"; - regulator-name = "vdd_cdc_1v2_aud"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - startup-delay-us = <250000>; - - enable-active-high; - }; - - vdd_disp_3v0: regulator@12 { - compatible = "regulator-fixed"; - reg = <12>; - regulator-name = "vdd-disp-3v0"; - regulator-enable-ramp-delay = <232>; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - - gpio = <&gpio TEGRA_GPIO(I, 3) GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vdd_fan: regulator@13 { - compatible = "regulator-fixed"; - reg = <13>; - regulator-name = "vdd-fan"; - regulator-enable-ramp-delay = <284>; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - gpio = <&gpio TEGRA_GPIO(E, 4) GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - usb_vbus1: regulator@14 { - compatible = "regulator-fixed"; - reg = <14>; - regulator-name = "usb-vbus1"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - gpio = <&gpio TEGRA_GPIO(CC, 5) GPIO_ACTIVE_HIGH>; - enable-active-high; - gpio-open-drain; - }; - - usb_vbus2: regulator@15 { - compatible = "regulator-fixed"; - reg = <15>; - regulator-name = "usb-vbus2"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - gpio = <&gpio TEGRA_GPIO(CC, 4) GPIO_ACTIVE_HIGH>; - enable-active-high; - gpio-open-drain; - }; - - vdd_3v3_eth: regulator@16 { - compatible = "regulator-fixed"; - reg = <16>; - regulator-name = "vdd-3v3-eth-a02"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - - gpio = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>; - enable-active-high; - gpio-open-drain; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/nvidia/tegra210-p3450-0000.dts b/sys/gnu/dts/arm64/nvidia/tegra210-p3450-0000.dts deleted file mode 100644 index 9101d3a39cd..00000000000 --- a/sys/gnu/dts/arm64/nvidia/tegra210-p3450-0000.dts +++ /dev/null @@ -1,792 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include -#include -#include - -#include "tegra210.dtsi" - -/ { - model = "NVIDIA Jetson Nano Developer Kit"; - compatible = "nvidia,p3450-0000", "nvidia,tegra210"; - - aliases { - ethernet = "/pcie@1003000/pci@2,0/ethernet@0,0"; - rtc0 = "/i2c@7000d000/pmic@3c"; - rtc1 = "/rtc@7000e000"; - serial0 = &uarta; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - device_type = "memory"; - reg = <0x0 0x80000000 0x1 0x0>; - }; - - pcie@1003000 { - status = "okay"; - - avdd-pll-uerefe-supply = <&vdd_pex_1v05>; - hvddio-pex-supply = <&vdd_1v8>; - dvddio-pex-supply = <&vdd_pex_1v05>; - dvdd-pex-pll-supply = <&vdd_pex_1v05>; - hvdd-pex-pll-e-supply = <&vdd_1v8>; - vddio-pex-ctl-supply = <&vdd_1v8>; - - pci@1,0 { - phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>, - <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>, - <&{/padctl@7009f000/pads/pcie/lanes/pcie-3}>, - <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>; - phy-names = "pcie-0", "pcie-1", "pcie-2", "pcie-3"; - nvidia,num-lanes = <4>; - status = "okay"; - }; - - pci@2,0 { - phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>; - phy-names = "pcie-0"; - status = "okay"; - - ethernet@0,0 { - reg = <0x000000 0 0 0 0>; - local-mac-address = [ 00 00 00 00 00 00 ]; - }; - }; - }; - - host1x@50000000 { - dpaux@54040000 { - status = "okay"; - }; - - sor@54540000 { - status = "okay"; - - avdd-io-hdmi-dp-supply = <&avdd_io_edp_1v05>; - vdd-hdmi-dp-pll-supply = <&vdd_1v8>; - - nvidia,xbar-cfg = <2 1 0 3 4>; - nvidia,dpaux = <&dpaux>; - }; - - sor@54580000 { - status = "okay"; - - avdd-io-supply = <&avdd_1v05>; - vdd-pll-supply = <&vdd_1v8>; - hdmi-supply = <&vdd_hdmi>; - - nvidia,ddc-i2c-bus = <&hdmi_ddc>; - nvidia,hpd-gpio = <&gpio TEGRA_GPIO(CC, 1) - GPIO_ACTIVE_LOW>; - nvidia,xbar-cfg = <0 1 2 3 4>; - }; - - dpaux@545c0000 { - status = "okay"; - }; - }; - - gpu@57000000 { - vdd-supply = <&vdd_gpu>; - status = "okay"; - }; - - /* debug port */ - serial@70006000 { - status = "okay"; - }; - - pwm@7000a000 { - status = "okay"; - }; - - i2c@7000c500 { - status = "okay"; - clock-frequency = <100000>; - - eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - - address-bits = <8>; - page-size = <8>; - size = <256>; - read-only; - }; - - eeprom@57 { - compatible = "atmel,24c02"; - reg = <0x57>; - - address-bits = <8>; - page-size = <8>; - size = <256>; - read-only; - }; - }; - - hdmi_ddc: i2c@7000c700 { - status = "okay"; - clock-frequency = <100000>; - }; - - i2c@7000d000 { - status = "okay"; - clock-frequency = <400000>; - - pmic: pmic@3c { - compatible = "maxim,max77620"; - reg = <0x3c>; - interrupts = ; - - #interrupt-cells = <2>; - interrupt-controller; - - #gpio-cells = <2>; - gpio-controller; - - pinctrl-names = "default"; - pinctrl-0 = <&max77620_default>; - - max77620_default: pinmux { - gpio0 { - pins = "gpio0"; - function = "gpio"; - }; - - gpio1 { - pins = "gpio1"; - function = "fps-out"; - drive-push-pull = <1>; - maxim,active-fps-source = ; - maxim,active-fps-power-up-slot = <0>; - maxim,active-fps-power-down-slot = <7>; - }; - - gpio2 { - pins = "gpio2"; - function = "fps-out"; - drive-open-drain = <1>; - maxim,active-fps-source = ; - maxim,active-fps-power-up-slot = <0>; - maxim,active-fps-power-down-slot = <7>; - }; - - gpio3 { - pins = "gpio3"; - function = "fps-out"; - drive-open-drain = <1>; - maxim,active-fps-source = ; - maxim,active-fps-power-up-slot = <4>; - maxim,active-fps-power-down-slot = <3>; - }; - - gpio4 { - pins = "gpio4"; - function = "32k-out1"; - }; - - gpio5_6_7 { - pins = "gpio5", "gpio6", "gpio7"; - function = "gpio"; - drive-push-pull = <1>; - }; - }; - - fps { - fps0 { - maxim,fps-event-source = ; - maxim,suspend-fps-time-period-us = <5120>; - }; - - fps1 { - maxim,fps-event-source = ; - maxim,suspend-fps-time-period-us = <5120>; - }; - - fps2 { - maxim,fps-event-source = ; - }; - }; - - regulators { - in-ldo0-1-supply = <&vdd_pre>; - in-ldo2-supply = <&vdd_3v3_sys>; - in-ldo3-5-supply = <&vdd_1v8>; - in-ldo4-6-supply = <&vdd_5v0_sys>; - in-ldo7-8-supply = <&vdd_pre>; - in-sd0-supply = <&vdd_5v0_sys>; - in-sd1-supply = <&vdd_5v0_sys>; - in-sd2-supply = <&vdd_5v0_sys>; - in-sd3-supply = <&vdd_5v0_sys>; - - vdd_soc: sd0 { - regulator-name = "VDD_SOC"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1170000>; - regulator-enable-ramp-delay = <146>; - regulator-disable-ramp-delay = <4080>; - regulator-ramp-delay = <27500>; - regulator-ramp-delay-scale = <300>; - regulator-always-on; - regulator-boot-on; - - maxim,active-fps-source = ; - maxim,active-fps-power-up-slot = <1>; - maxim,active-fps-power-down-slot = <6>; - }; - - vdd_ddr: sd1 { - regulator-name = "VDD_DDR_1V1_PMIC"; - regulator-min-microvolt = <1150000>; - regulator-max-microvolt = <1150000>; - regulator-enable-ramp-delay = <176>; - regulator-disable-ramp-delay = <145800>; - regulator-ramp-delay = <27500>; - regulator-ramp-delay-scale = <300>; - regulator-always-on; - regulator-boot-on; - - maxim,active-fps-source = ; - maxim,active-fps-power-up-slot = <5>; - maxim,active-fps-power-down-slot = <2>; - }; - - vdd_pre: sd2 { - regulator-name = "VDD_PRE_REG_1V35"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-enable-ramp-delay = <176>; - regulator-disable-ramp-delay = <32000>; - regulator-ramp-delay = <27500>; - regulator-ramp-delay-scale = <350>; - regulator-always-on; - regulator-boot-on; - - maxim,active-fps-source = ; - maxim,active-fps-power-up-slot = <2>; - maxim,active-fps-power-down-slot = <5>; - }; - - vdd_1v8: sd3 { - regulator-name = "VDD_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-enable-ramp-delay = <242>; - regulator-disable-ramp-delay = <118000>; - regulator-ramp-delay = <27500>; - regulator-ramp-delay-scale = <360>; - regulator-always-on; - regulator-boot-on; - - maxim,active-fps-source = ; - maxim,active-fps-power-up-slot = <3>; - maxim,active-fps-power-down-slot = <4>; - }; - - vdd_sys_1v2: ldo0 { - regulator-name = "AVDD_SYS_1V2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-enable-ramp-delay = <26>; - regulator-disable-ramp-delay = <626>; - regulator-ramp-delay = <100000>; - regulator-ramp-delay-scale = <200>; - regulator-always-on; - regulator-boot-on; - - maxim,active-fps-source = ; - maxim,active-fps-power-up-slot = <0>; - maxim,active-fps-power-down-slot = <7>; - }; - - vdd_pex_1v05: ldo1 { - regulator-name = "VDD_PEX_1V05"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - regulator-enable-ramp-delay = <22>; - regulator-disable-ramp-delay = <650>; - regulator-ramp-delay = <100000>; - regulator-ramp-delay-scale = <200>; - - maxim,active-fps-source = ; - maxim,active-fps-power-up-slot = <0>; - maxim,active-fps-power-down-slot = <7>; - }; - - vddio_sdmmc: ldo2 { - regulator-name = "VDDIO_SDMMC"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <62>; - regulator-disable-ramp-delay = <650>; - regulator-ramp-delay = <100000>; - regulator-ramp-delay-scale = <200>; - - maxim,active-fps-source = ; - maxim,active-fps-power-up-slot = <0>; - maxim,active-fps-power-down-slot = <7>; - }; - - ldo3 { - status = "disabled"; - }; - - vdd_rtc: ldo4 { - regulator-name = "VDD_RTC"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1100000>; - regulator-enable-ramp-delay = <22>; - regulator-disable-ramp-delay = <610>; - regulator-ramp-delay = <100000>; - regulator-ramp-delay-scale = <200>; - regulator-disable-active-discharge; - regulator-always-on; - regulator-boot-on; - - maxim,active-fps-source = ; - maxim,active-fps-power-up-slot = <1>; - maxim,active-fps-power-down-slot = <6>; - }; - - ldo5 { - status = "disabled"; - }; - - ldo6 { - status = "disabled"; - }; - - avdd_1v05_pll: ldo7 { - regulator-name = "AVDD_1V05_PLL"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - regulator-enable-ramp-delay = <24>; - regulator-disable-ramp-delay = <2768>; - regulator-ramp-delay = <100000>; - regulator-ramp-delay-scale = <200>; - - maxim,active-fps-source = ; - maxim,active-fps-power-up-slot = <3>; - maxim,active-fps-power-down-slot = <4>; - }; - - avdd_1v05: ldo8 { - regulator-name = "AVDD_SATA_HDMI_DP_1V05"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - regulator-enable-ramp-delay = <22>; - regulator-disable-ramp-delay = <1160>; - regulator-ramp-delay = <100000>; - regulator-ramp-delay-scale = <200>; - - maxim,active-fps-source = ; - maxim,active-fps-power-up-slot = <6>; - maxim,active-fps-power-down-slot = <1>; - }; - }; - }; - }; - - pmc@7000e400 { - nvidia,invert-interrupt; - nvidia,suspend-mode = <0>; - nvidia,cpu-pwr-good-time = <0>; - nvidia,cpu-pwr-off-time = <0>; - nvidia,core-pwr-good-time = <4587 3876>; - nvidia,core-pwr-off-time = <39065>; - nvidia,core-power-req-active-high; - nvidia,sys-clock-req-active-high; - }; - - hda@70030000 { - nvidia,model = "jetson-nano-hda"; - - status = "okay"; - }; - - usb@70090000 { - phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>, - <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>, - <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>, - <&{/padctl@7009f000/pads/pcie/lanes/pcie-6}>; - phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-0"; - - avdd-usb-supply = <&vdd_3v3_sys>; - dvddio-pex-supply = <&vdd_pex_1v05>; - hvddio-pex-supply = <&vdd_1v8>; - /* these really belong to the XUSB pad controller */ - avdd-pll-utmip-supply = <&vdd_1v8>; - avdd-pll-uerefe-supply = <&vdd_pex_1v05>; - dvdd-usb-ss-pll-supply = <&vdd_pex_1v05>; - hvdd-usb-ss-pll-e-supply = <&vdd_1v8>; - - status = "okay"; - }; - - padctl@7009f000 { - status = "okay"; - - avdd-pll-utmip-supply = <&vdd_1v8>; - avdd-pll-uerefe-supply = <&vdd_pex_1v05>; - dvdd-pex-pll-supply = <&vdd_pex_1v05>; - hvdd-pex-pll-e-supply = <&vdd_1v8>; - - pads { - usb2 { - status = "okay"; - - lanes { - usb2-0 { - nvidia,function = "xusb"; - status = "okay"; - }; - - usb2-1 { - nvidia,function = "xusb"; - status = "okay"; - }; - - usb2-2 { - nvidia,function = "xusb"; - status = "okay"; - }; - }; - }; - - pcie { - status = "okay"; - - lanes { - pcie-0 { - nvidia,function = "pcie-x1"; - status = "okay"; - }; - - pcie-1 { - nvidia,function = "pcie-x4"; - status = "okay"; - }; - - pcie-2 { - nvidia,function = "pcie-x4"; - status = "okay"; - }; - - pcie-3 { - nvidia,function = "pcie-x4"; - status = "okay"; - }; - - pcie-4 { - nvidia,function = "pcie-x4"; - status = "okay"; - }; - - pcie-5 { - nvidia,function = "usb3-ss"; - status = "okay"; - }; - - pcie-6 { - nvidia,function = "usb3-ss"; - status = "okay"; - }; - }; - }; - }; - - ports { - usb2-0 { - status = "okay"; - mode = "otg"; - }; - - usb2-1 { - status = "okay"; - mode = "host"; - }; - - usb2-2 { - status = "okay"; - mode = "host"; - }; - - usb3-0 { - status = "okay"; - nvidia,usb2-companion = <1>; - vbus-supply = <&vdd_hub_3v3>; - }; - }; - }; - - sdhci@700b0000 { - status = "okay"; - bus-width = <4>; - - cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>; - - vqmmc-supply = <&vddio_sdmmc>; - vmmc-supply = <&vdd_3v3_sd>; - }; - - sdhci@700b0400 { - status = "okay"; - bus-width = <4>; - - vqmmc-supply = <&vdd_1v8>; - vmmc-supply = <&vdd_3v3_sys>; - - non-removable; - cap-sdio-irq; - keep-power-in-suspend; - wakeup-source; - }; - - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - cpus { - cpu@0 { - enable-method = "psci"; - }; - - cpu@1 { - enable-method = "psci"; - }; - - cpu@2 { - enable-method = "psci"; - }; - - cpu@3 { - enable-method = "psci"; - }; - - idle-states { - cpu-sleep { - status = "okay"; - }; - }; - }; - - fan: fan { - compatible = "pwm-fan"; - pwms = <&pwm 3 45334>; - - cooling-levels = <0 64 128 255>; - #cooling-cells = <2>; - }; - - thermal-zones { - cpu { - trips { - cpu_trip_critical: critical { - temperature = <96500>; - hysteresis = <0>; - type = "critical"; - }; - - cpu_trip_hot: hot { - temperature = <70000>; - hysteresis = <2000>; - type = "hot"; - }; - - cpu_trip_active: active { - temperature = <50000>; - hysteresis = <2000>; - type = "active"; - }; - - cpu_trip_passive: passive { - temperature = <30000>; - hysteresis = <2000>; - type = "passive"; - }; - }; - - cooling-maps { - cpu-critical { - cooling-device = <&fan 3 3>; - trip = <&cpu_trip_critical>; - }; - - cpu-hot { - cooling-device = <&fan 2 2>; - trip = <&cpu_trip_hot>; - }; - - cpu-active { - cooling-device = <&fan 1 1>; - trip = <&cpu_trip_active>; - }; - - cpu-passive { - cooling-device = <&fan 0 0>; - trip = <&cpu_trip_passive>; - }; - }; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - power { - label = "Power"; - gpios = <&gpio TEGRA_GPIO(X, 5) GPIO_ACTIVE_LOW>; - linux,input-type = ; - linux,code = ; - debounce-interval = <30>; - wakeup-event-action = ; - wakeup-source; - }; - - force-recovery { - label = "Force Recovery"; - gpios = <&gpio TEGRA_GPIO(X, 6) GPIO_ACTIVE_LOW>; - linux,input-type = ; - linux,code = ; - debounce-interval = <30>; - }; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - vdd_5v0_sys: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - - regulator-name = "VDD_5V0_SYS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_3v3_sys: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "VDD_3V3_SYS"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <240>; - regulator-disable-ramp-delay = <11340>; - regulator-always-on; - regulator-boot-on; - - gpio = <&pmic 3 GPIO_ACTIVE_HIGH>; - enable-active-high; - - vin-supply = <&vdd_5v0_sys>; - }; - - vdd_3v3_sd: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - - regulator-name = "VDD_3V3_SD"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&gpio TEGRA_GPIO(Z, 3) GPIO_ACTIVE_HIGH>; - enable-active-high; - - vin-supply = <&vdd_3v3_sys>; - }; - - vdd_hdmi: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - - regulator-name = "VDD_HDMI_5V0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - vin-supply = <&vdd_5v0_sys>; - }; - - vdd_hub_3v3: regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - - regulator-name = "VDD_HUB_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&gpio TEGRA_GPIO(A, 6) GPIO_ACTIVE_HIGH>; - enable-active-high; - - vin-supply = <&vdd_5v0_sys>; - }; - - vdd_cpu: regulator@5 { - compatible = "regulator-fixed"; - reg = <5>; - - regulator-name = "VDD_CPU"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - - gpio = <&pmic 5 GPIO_ACTIVE_HIGH>; - enable-active-high; - - vin-supply = <&vdd_5v0_sys>; - }; - - vdd_gpu: regulator@6 { - compatible = "pwm-regulator"; - reg = <6>; - pwms = <&pwm 1 4880>; - regulator-name = "VDD_GPU"; - regulator-min-microvolt = <710000>; - regulator-max-microvolt = <1320000>; - regulator-ramp-delay = <80>; - regulator-enable-ramp-delay = <2000>; - regulator-settling-time-us = <160>; - enable-gpios = <&pmic 6 GPIO_ACTIVE_HIGH>; - vin-supply = <&vdd_5v0_sys>; - }; - - avdd_io_edp_1v05: regulator@7 { - compatible = "regulator-fixed"; - reg = <7>; - - regulator-name = "AVDD_IO_EDP_1V05"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - - gpio = <&pmic 7 GPIO_ACTIVE_HIGH>; - enable-active-high; - - vin-supply = <&avdd_1v05_pll>; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/nvidia/tegra210-smaug.dts b/sys/gnu/dts/arm64/nvidia/tegra210-smaug.dts deleted file mode 100644 index 72c7a04ac1d..00000000000 --- a/sys/gnu/dts/arm64/nvidia/tegra210-smaug.dts +++ /dev/null @@ -1,1902 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include -#include -#include - -#include "tegra210.dtsi" - -/ { - model = "Google Pixel C"; - compatible = "google,smaug-rev8", "google,smaug-rev7", - "google,smaug-rev6", "google,smaug-rev5", - "google,smaug-rev4", "google,smaug-rev3", - "google,smaug-rev2", "google,smaug-rev1", - "google,smaug", "nvidia,tegra210"; - - aliases { - serial0 = &uarta; - }; - - chosen { - bootargs = "earlycon"; - stdout-path = "serial0:115200n8"; - }; - - memory { - device_type = "memory"; - reg = <0x0 0x80000000 0x0 0xc0000000>; - }; - - host1x@50000000 { - dpaux: dpaux@545c0000 { - status = "okay"; - }; - }; - - pinmux: pinmux@700008d4 { - pinctrl-names = "boot"; - pinctrl-0 = <&state_boot>; - - state_boot: pinmux { - pex_l0_rst_n_pa0 { - nvidia,pins = "pex_l0_rst_n_pa0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - pex_l0_clkreq_n_pa1 { - nvidia,pins = "pex_l0_clkreq_n_pa1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - pex_wake_n_pa2 { - nvidia,pins = "pex_wake_n_pa2"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - pex_l1_rst_n_pa3 { - nvidia,pins = "pex_l1_rst_n_pa3"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - pex_l1_clkreq_n_pa4 { - nvidia,pins = "pex_l1_clkreq_n_pa4"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - sata_led_active_pa5 { - nvidia,pins = "sata_led_active_pa5"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pa6 { - nvidia,pins = "pa6"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap1_fs_pb0 { - nvidia,pins = "dap1_fs_pb0"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap1_din_pb1 { - nvidia,pins = "dap1_din_pb1"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap1_dout_pb2 { - nvidia,pins = "dap1_dout_pb2"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap1_sclk_pb3 { - nvidia,pins = "dap1_sclk_pb3"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi2_mosi_pb4 { - nvidia,pins = "spi2_mosi_pb4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi2_miso_pb5 { - nvidia,pins = "spi2_miso_pb5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi2_sck_pb6 { - nvidia,pins = "spi2_sck_pb6"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi2_cs0_pb7 { - nvidia,pins = "spi2_cs0_pb7"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi1_mosi_pc0 { - nvidia,pins = "spi1_mosi_pc0"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi1_miso_pc1 { - nvidia,pins = "spi1_miso_pc1"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi1_sck_pc2 { - nvidia,pins = "spi1_sck_pc2"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi1_cs0_pc3 { - nvidia,pins = "spi1_cs0_pc3"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi1_cs1_pc4 { - nvidia,pins = "spi1_cs1_pc4"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi4_sck_pc5 { - nvidia,pins = "spi4_sck_pc5"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi4_cs0_pc6 { - nvidia,pins = "spi4_cs0_pc6"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi4_mosi_pc7 { - nvidia,pins = "spi4_mosi_pc7"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi4_miso_pd0 { - nvidia,pins = "spi4_miso_pd0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart3_tx_pd1 { - nvidia,pins = "uart3_tx_pd1"; - nvidia,function = "uartc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart3_rx_pd2 { - nvidia,pins = "uart3_rx_pd2"; - nvidia,function = "uartc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart3_rts_pd3 { - nvidia,pins = "uart3_rts_pd3"; - nvidia,function = "uartc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart3_cts_pd4 { - nvidia,pins = "uart3_cts_pd4"; - nvidia,function = "uartc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dmic1_clk_pe0 { - nvidia,pins = "dmic1_clk_pe0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dmic1_dat_pe1 { - nvidia,pins = "dmic1_dat_pe1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dmic2_clk_pe2 { - nvidia,pins = "dmic2_clk_pe2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dmic2_dat_pe3 { - nvidia,pins = "dmic2_dat_pe3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dmic3_clk_pe4 { - nvidia,pins = "dmic3_clk_pe4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dmic3_dat_pe5 { - nvidia,pins = "dmic3_dat_pe5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pe6 { - nvidia,pins = "pe6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pe7 { - nvidia,pins = "pe7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gen3_i2c_scl_pf0 { - nvidia,pins = "gen3_i2c_scl_pf0"; - nvidia,function = "i2c3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - gen3_i2c_sda_pf1 { - nvidia,pins = "gen3_i2c_sda_pf1"; - nvidia,function = "i2c3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - uart2_tx_pg0 { - nvidia,pins = "uart2_tx_pg0"; - nvidia,function = "uartb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart2_rx_pg1 { - nvidia,pins = "uart2_rx_pg1"; - nvidia,function = "uartb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart2_rts_pg2 { - nvidia,pins = "uart2_rts_pg2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart2_cts_pg3 { - nvidia,pins = "uart2_cts_pg3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - wifi_en_ph0 { - nvidia,pins = "wifi_en_ph0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - wifi_rst_ph1 { - nvidia,pins = "wifi_rst_ph1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - wifi_wake_ap_ph2 { - nvidia,pins = "wifi_wake_ap_ph2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - ap_wake_bt_ph3 { - nvidia,pins = "ap_wake_bt_ph3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - bt_rst_ph4 { - nvidia,pins = "bt_rst_ph4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - bt_wake_ap_ph5 { - nvidia,pins = "bt_wake_ap_ph5"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - ph6 { - nvidia,pins = "ph6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - ap_wake_nfc_ph7 { - nvidia,pins = "ap_wake_nfc_ph7"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - nfc_en_pi0 { - nvidia,pins = "nfc_en_pi0"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - nfc_int_pi1 { - nvidia,pins = "nfc_int_pi1"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gps_en_pi2 { - nvidia,pins = "gps_en_pi2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gps_rst_pi3 { - nvidia,pins = "gps_rst_pi3"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart4_tx_pi4 { - nvidia,pins = "uart4_tx_pi4"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart4_rx_pi5 { - nvidia,pins = "uart4_rx_pi5"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart4_rts_pi6 { - nvidia,pins = "uart4_rts_pi6"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart4_cts_pi7 { - nvidia,pins = "uart4_cts_pi7"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gen1_i2c_sda_pj0 { - nvidia,pins = "gen1_i2c_sda_pj0"; - nvidia,function = "i2c1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - gen1_i2c_scl_pj1 { - nvidia,pins = "gen1_i2c_scl_pj1"; - nvidia,function = "i2c1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - gen2_i2c_scl_pj2 { - nvidia,pins = "gen2_i2c_scl_pj2"; - nvidia,function = "i2c2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - gen2_i2c_sda_pj3 { - nvidia,pins = "gen2_i2c_sda_pj3"; - nvidia,function = "i2c2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - dap4_fs_pj4 { - nvidia,pins = "dap4_fs_pj4"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap4_din_pj5 { - nvidia,pins = "dap4_din_pj5"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap4_dout_pj6 { - nvidia,pins = "dap4_dout_pj6"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap4_sclk_pj7 { - nvidia,pins = "dap4_sclk_pj7"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pk0 { - nvidia,pins = "pk0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pk1 { - nvidia,pins = "pk1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pk2 { - nvidia,pins = "pk2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pk3 { - nvidia,pins = "pk3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pk4 { - nvidia,pins = "pk4"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pk5 { - nvidia,pins = "pk5"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pk6 { - nvidia,pins = "pk6"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pk7 { - nvidia,pins = "pk7"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pl0 { - nvidia,pins = "pl0"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pl1 { - nvidia,pins = "pl1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc1_clk_pm0 { - nvidia,pins = "sdmmc1_clk_pm0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc1_cmd_pm1 { - nvidia,pins = "sdmmc1_cmd_pm1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc1_dat3_pm2 { - nvidia,pins = "sdmmc1_dat3_pm2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc1_dat2_pm3 { - nvidia,pins = "sdmmc1_dat2_pm3"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc1_dat1_pm4 { - nvidia,pins = "sdmmc1_dat1_pm4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc1_dat0_pm5 { - nvidia,pins = "sdmmc1_dat0_pm5"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc3_clk_pp0 { - nvidia,pins = "sdmmc3_clk_pp0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc3_cmd_pp1 { - nvidia,pins = "sdmmc3_cmd_pp1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc3_dat3_pp2 { - nvidia,pins = "sdmmc3_dat3_pp2"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc3_dat2_pp3 { - nvidia,pins = "sdmmc3_dat2_pp3"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc3_dat1_pp4 { - nvidia,pins = "sdmmc3_dat1_pp4"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc3_dat0_pp5 { - nvidia,pins = "sdmmc3_dat0_pp5"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam1_mclk_ps0 { - nvidia,pins = "cam1_mclk_ps0"; - nvidia,function = "extperiph3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam2_mclk_ps1 { - nvidia,pins = "cam2_mclk_ps1"; - nvidia,function = "extperiph3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam_i2c_scl_ps2 { - nvidia,pins = "cam_i2c_scl_ps2"; - nvidia,function = "i2cvi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - cam_i2c_sda_ps3 { - nvidia,pins = "cam_i2c_sda_ps3"; - nvidia,function = "i2cvi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - cam_rst_ps4 { - nvidia,pins = "cam_rst_ps4"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam_af_en_ps5 { - nvidia,pins = "cam_af_en_ps5"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam_flash_en_ps6 { - nvidia,pins = "cam_flash_en_ps6"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam1_pwdn_ps7 { - nvidia,pins = "cam1_pwdn_ps7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam2_pwdn_pt0 { - nvidia,pins = "cam2_pwdn_pt0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam1_strobe_pt1 { - nvidia,pins = "cam1_strobe_pt1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart1_tx_pu0 { - nvidia,pins = "uart1_tx_pu0"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart1_rx_pu1 { - nvidia,pins = "uart1_rx_pu1"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart1_rts_pu2 { - nvidia,pins = "uart1_rts_pu2"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart1_cts_pu3 { - nvidia,pins = "uart1_cts_pu3"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - lcd_bl_pwm_pv0 { - nvidia,pins = "lcd_bl_pwm_pv0"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - lcd_bl_en_pv1 { - nvidia,pins = "lcd_bl_en_pv1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - lcd_rst_pv2 { - nvidia,pins = "lcd_rst_pv2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - lcd_gpio1_pv3 { - nvidia,pins = "lcd_gpio1_pv3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - lcd_gpio2_pv4 { - nvidia,pins = "lcd_gpio2_pv4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - ap_ready_pv5 { - nvidia,pins = "ap_ready_pv5"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - touch_rst_pv6 { - nvidia,pins = "touch_rst_pv6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - touch_clk_pv7 { - nvidia,pins = "touch_clk_pv7"; - nvidia,function = "touch"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - modem_wake_ap_px0 { - nvidia,pins = "modem_wake_ap_px0"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - touch_int_px1 { - nvidia,pins = "touch_int_px1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - motion_int_px2 { - nvidia,pins = "motion_int_px2"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - als_prox_int_px3 { - nvidia,pins = "als_prox_int_px3"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - temp_alert_px4 { - nvidia,pins = "temp_alert_px4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - button_power_on_px5 { - nvidia,pins = "button_power_on_px5"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - button_vol_up_px6 { - nvidia,pins = "button_vol_up_px6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - button_vol_down_px7 { - nvidia,pins = "button_vol_down_px7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - button_slide_sw_py0 { - nvidia,pins = "button_slide_sw_py0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - button_home_py1 { - nvidia,pins = "button_home_py1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - lcd_te_py2 { - nvidia,pins = "lcd_te_py2"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pwr_i2c_scl_py3 { - nvidia,pins = "pwr_i2c_scl_py3"; - nvidia,function = "i2cpmu"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - pwr_i2c_sda_py4 { - nvidia,pins = "pwr_i2c_sda_py4"; - nvidia,function = "i2cpmu"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - clk_32k_out_py5 { - nvidia,pins = "clk_32k_out_py5"; - nvidia,function = "soc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pz0 { - nvidia,pins = "pz0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pz1 { - nvidia,pins = "pz1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pz2 { - nvidia,pins = "pz2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pz3 { - nvidia,pins = "pz3"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pz4 { - nvidia,pins = "pz4"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pz5 { - nvidia,pins = "pz5"; - nvidia,function = "soc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap2_fs_paa0 { - nvidia,pins = "dap2_fs_paa0"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap2_sclk_paa1 { - nvidia,pins = "dap2_sclk_paa1"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap2_din_paa2 { - nvidia,pins = "dap2_din_paa2"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap2_dout_paa3 { - nvidia,pins = "dap2_dout_paa3"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - aud_mclk_pbb0 { - nvidia,pins = "aud_mclk_pbb0"; - nvidia,function = "aud"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dvfs_pwm_pbb1 { - nvidia,pins = "dvfs_pwm_pbb1"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dvfs_clk_pbb2 { - nvidia,pins = "dvfs_clk_pbb2"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gpio_x1_aud_pbb3 { - nvidia,pins = "gpio_x1_aud_pbb3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gpio_x3_aud_pbb4 { - nvidia,pins = "gpio_x3_aud_pbb4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - hdmi_cec_pcc0 { - nvidia,pins = "hdmi_cec_pcc0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - hdmi_int_dp_hpd_pcc1 { - nvidia,pins = "hdmi_int_dp_hpd_pcc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - spdif_out_pcc2 { - nvidia,pins = "spdif_out_pcc2"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spdif_in_pcc3 { - nvidia,pins = "spdif_in_pcc3"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - usb_vbus_en0_pcc4 { - nvidia,pins = "usb_vbus_en0_pcc4"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - usb_vbus_en1_pcc5 { - nvidia,pins = "usb_vbus_en1_pcc5"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - dp_hpd0_pcc6 { - nvidia,pins = "dp_hpd0_pcc6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pcc7 { - nvidia,pins = "pcc7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - spi2_cs1_pdd0 { - nvidia,pins = "spi2_cs1_pdd0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - qspi_sck_pee0 { - nvidia,pins = "qspi_sck_pee0"; - nvidia,function = "qspi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - qspi_cs_n_pee1 { - nvidia,pins = "qspi_cs_n_pee1"; - nvidia,function = "qspi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - qspi_io0_pee2 { - nvidia,pins = "qspi_io0_pee2"; - nvidia,function = "qspi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - qspi_io1_pee3 { - nvidia,pins = "qspi_io1_pee3"; - nvidia,function = "qspi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - qspi_io2_pee4 { - nvidia,pins = "qspi_io2_pee4"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - qspi_io3_pee5 { - nvidia,pins = "qspi_io3_pee5"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - core_pwr_req { - nvidia,pins = "core_pwr_req"; - nvidia,function = "core"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cpu_pwr_req { - nvidia,pins = "cpu_pwr_req"; - nvidia,function = "cpu"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pwr_int_n { - nvidia,pins = "pwr_int_n"; - nvidia,function = "pmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - clk_32k_in { - nvidia,pins = "clk_32k_in"; - nvidia,function = "clk"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - jtag_rtck { - nvidia,pins = "jtag_rtck"; - nvidia,function = "jtag"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - clk_req { - nvidia,pins = "clk_req"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - shutdown { - nvidia,pins = "shutdown"; - nvidia,function = "shutdown"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - }; - }; - - serial@70006000 { - status = "okay"; - }; - - i2c@7000c400 { - status = "okay"; - clock-frequency = <1000000>; - - ec@1e { - compatible = "google,cros-ec-i2c"; - reg = <0x1e>; - interrupt-parent = <&gpio>; - interrupts = ; - wakeup-source; - - ec_i2c_0: i2c-tunnel { - compatible = "google,cros-ec-i2c-tunnel"; - #address-cells = <1>; - #size-cells = <0>; - - google,remote-bus = <0>; - - battery: bq27742@55 { - compatible = "ti,bq27742"; - reg = <0x55>; - battery-name = "battery"; - }; - }; - }; - }; - - i2c@7000d000 { - status = "okay"; - clock-frequency = <1000000>; - - max77621_cpu: max77621@1b { - compatible = "maxim,max77621"; - reg = <0x1b>; - interrupt-parent = <&gpio>; - interrupts = ; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1231250>; - regulator-name = "PPVAR_CPU"; - regulator-ramp-delay = <12500>; - maxim,dvs-default-state = <1>; - maxim,enable-active-discharge; - maxim,enable-bias-control; - maxim,enable-etr; - maxim,enable-gpio = <&max77620 5 0>; - maxim,externally-enable; - }; - - max77620: max77620@3c { - compatible = "maxim,max77620"; - reg = <0x3c>; - interrupts = ; - - #interrupt-cells = <2>; - interrupt-controller; - - gpio-controller; - #gpio-cells = <2>; - - pinctrl-names = "default"; - pinctrl-0 = <&max77620_default>; - - max77620_default: pinmux@0 { - pin_gpio { - pins = "gpio0", "gpio1", "gpio2", "gpio7"; - function = "gpio"; - }; - - /* - * GPIO3 is used to en_pp3300, and it is part of power - * sequence, So it must be sequenced up (automatically - * set by OTP) and down properly. - */ - pin_gpio3 { - pins = "gpio3"; - function = "fps-out"; - drive-open-drain = <1>; - maxim,active-fps-source = ; - maxim,active-fps-power-up-slot = <4>; - maxim,active-fps-power-down-slot = <2>; - }; - - pin_gpio5_6 { - pins = "gpio5", "gpio6"; - function = "gpio"; - drive-push-pull = <1>; - }; - - pin_32k { - pins = "gpio4"; - function = "32k-out1"; - }; - }; - - fps { - fps0 { - maxim,shutdown-fps-time-period-us = <5120>; - maxim,fps-event-source = ; - }; - - fps1 { - maxim,shutdown-fps-time-period-us = <5120>; - maxim,fps-event-source = ; - maxim,device-state-on-disabled-event = ; - }; - - fps2 { - maxim,fps-event-source = ; - }; - }; - - regulators { - in-ldo0-1-supply = <&pp1350>; - in-ldo2-supply = <&pp3300>; - in-ldo3-5-supply = <&pp3300>; - in-ldo7-8-supply = <&pp1350>; - - ppvar_soc: sd0 { - regulator-name = "PPVAR_SOC"; - regulator-min-microvolt = <825000>; - regulator-max-microvolt = <1125000>; - regulator-always-on; - regulator-boot-on; - maxim,active-fps-source = ; - maxim,active-fps-power-up-slot = <1>; - maxim,active-fps-power-down-slot = <7>; - }; - - pp1100_sd1: sd1 { - regulator-name = "PP1100"; - regulator-min-microvolt = <1125000>; - regulator-max-microvolt = <1125000>; - regulator-always-on; - regulator-boot-on; - maxim,active-fps-source = ; - maxim,active-fps-power-up-slot = <5>; - maxim,active-fps-power-down-slot = <1>; - }; - - pp1350: sd2 { - regulator-name = "PP1350"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - maxim,active-fps-source = ; - maxim,active-fps-power-up-slot = <2>; - maxim,active-fps-power-down-slot = <5>; - }; - - pp1800: sd3 { - regulator-name = "PP1800"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - maxim,active-fps-source = ; - maxim,active-fps-power-up-slot = <3>; - maxim,active-fps-power-down-slot = <3>; - }; - - pp1200_avdd: ldo0 { - regulator-name = "PP1200_AVDD"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-enable-ramp-delay = <26>; - regulator-ramp-delay = <100000>; - regulator-boot-on; - maxim,active-fps-source = ; - maxim,active-fps-power-up-slot = <0>; - maxim,active-fps-power-down-slot = <7>; - }; - - pp1200_rcam: ldo1 { - regulator-name = "PP1200_RCAM"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-enable-ramp-delay = <22>; - regulator-ramp-delay = <100000>; - maxim,active-fps-source = ; - maxim,active-fps-power-up-slot = <0>; - maxim,active-fps-power-down-slot = <7>; - }; - - pp_ldo2: ldo2 { - regulator-name = "PP_LDO2"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-enable-ramp-delay = <62>; - regulator-ramp-delay = <11000>; - regulator-always-on; - regulator-boot-on; - maxim,active-fps-source = ; - maxim,active-fps-power-up-slot = <0>; - maxim,active-fps-power-down-slot = <7>; - }; - - pp2800l_rcam: ldo3 { - regulator-name = "PP2800L_RCAM"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-enable-ramp-delay = <50>; - regulator-ramp-delay = <100000>; - maxim,active-fps-source = ; - maxim,active-fps-power-up-slot = <0>; - maxim,active-fps-power-down-slot = <7>; - }; - - pp100_soc_rtc: ldo4 { - regulator-name = "PP1100_SOC_RTC"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - regulator-enable-ramp-delay = <22>; - regulator-ramp-delay = <100000>; - regulator-always-on; /* Check this */ - regulator-boot-on; - maxim,active-fps-source = ; - maxim,active-fps-power-up-slot = <1>; - maxim,active-fps-power-down-slot = <7>; - }; - - pp2800l_fcam: ldo5 { - regulator-name = "PP2800L_FCAM"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-enable-ramp-delay = <62>; - regulator-ramp-delay = <100000>; - maxim,active-fps-source = ; - maxim,active-fps-power-up-slot = <0>; - maxim,active-fps-power-down-slot = <7>; - }; - - ldo6 { - /* Unused. */ - regulator-name = "PP_LDO6"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-enable-ramp-delay = <36>; - regulator-ramp-delay = <100000>; - maxim,active-fps-source = ; - maxim,active-fps-power-up-slot = <0>; - maxim,active-fps-power-down-slot = <7>; - }; - - pp1050_avdd: ldo7 { - regulator-name = "PP1050_AVDD"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - regulator-enable-ramp-delay = <24>; - regulator-ramp-delay = <100000>; - regulator-always-on; - regulator-boot-on; - maxim,active-fps-source = ; - maxim,active-fps-power-up-slot = <3>; - maxim,active-fps-power-down-slot = <4>; - }; - - avddio_1v05: ldo8 { - regulator-name = "AVDDIO_1V05"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - regulator-enable-ramp-delay = <22>; - regulator-ramp-delay = <100000>; - regulator-boot-on; - maxim,active-fps-source = ; - maxim,active-fps-power-up-slot = <0>; - maxim,active-fps-power-down-slot = <7>; - }; - }; - }; - }; - - i2c@7000d100 { - status = "okay"; - clock-frequency = <400000>; - - nau8825@1a { - compatible = "nuvoton,nau8825"; - reg = <0x1a>; - interrupt-parent = <&gpio>; - interrupts = ; - clocks = <&tegra_car TEGRA210_CLK_CLK_OUT_2>; - clock-names = "mclk"; - - nuvoton,jkdet-enable; - nuvoton,jkdet-polarity = ; - nuvoton,vref-impedance = <2>; - nuvoton,micbias-voltage = <6>; - nuvoton,sar-threshold-num = <4>; - nuvoton,sar-threshold = <0xc 0x1e 0x38 0x60>; - nuvoton,sar-hysteresis = <1>; - nuvoton,sar-voltage = <0>; - nuvoton,sar-compare-time = <0>; - nuvoton,sar-sampling-time = <0>; - nuvoton,short-key-debounce = <2>; - nuvoton,jack-insert-debounce = <7>; - nuvoton,jack-eject-debounce = <7>; - status = "okay"; - }; - - audio-codec@2d { - compatible = "realtek,rt5677"; - reg = <0x2d>; - interrupt-parent = <&gpio>; - interrupts = ; - realtek,reset-gpio = <&gpio TEGRA_GPIO(BB, 3) GPIO_ACTIVE_LOW>; - gpio-controller; - #gpio-cells = <2>; - status = "okay"; - }; - }; - - pmc@7000e400 { - nvidia,invert-interrupt; - nvidia,suspend-mode = <0>; - nvidia,cpu-pwr-good-time = <0>; - nvidia,cpu-pwr-off-time = <0>; - nvidia,core-pwr-good-time = <12000 6000>; - nvidia,core-pwr-off-time = <39053>; - nvidia,core-power-req-active-high; - nvidia,sys-clock-req-active-high; - status = "okay"; - }; - - usb@70090000 { - phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>, - <&{/padctl@7009f000/pads/pcie/lanes/pcie-6}>; - phy-names = "usb2-0", "usb3-0"; - - dvddio-pex-supply = <&avddio_1v05>; - hvddio-pex-supply = <&pp1800>; - avdd-usb-supply = <&pp3300>; - avdd-pll-utmip-supply = <&pp1800>; - avdd-pll-uerefe-supply = <&pp1050_avdd>; - dvdd-pex-pll-supply = <&avddio_1v05>; - hvdd-pex-pll-e-supply = <&pp1800>; - - status = "okay"; - }; - - padctl@7009f000 { - status = "okay"; - - avdd-pll-utmip-supply = <&pp1800>; - avdd-pll-uerefe-supply = <&pp1050_avdd>; - dvdd-pex-pll-supply = <&avddio_1v05>; - hvdd-pex-pll-e-supply = <&pp1800>; - - pads { - usb2 { - status = "okay"; - - lanes { - usb2-0 { - nvidia,function = "xusb"; - status = "okay"; - }; - }; - }; - - pcie { - status = "okay"; - - lanes { - pcie-6 { - nvidia,function = "usb3-ss"; - status = "okay"; - }; - }; - }; - }; - - ports { - usb2-0 { - status = "okay"; - vbus-supply = <&usbc_vbus>; - mode = "otg"; - }; - - usb3-0 { - nvidia,usb2-companion = <0>; - status = "okay"; - }; - }; - }; - - sdhci@700b0600 { - bus-width = <8>; - non-removable; - status = "okay"; - }; - - clock@70110000 { - status = "okay"; - nvidia,cf = <6>; - nvidia,ci = <0>; - nvidia,cg = <2>; - nvidia,droop-ctrl = <0x00000f00>; - nvidia,force-mode = <1>; - nvidia,i2c-fs-rate = <400000>; - nvidia,sample-rate = <12500>; - vdd-cpu-supply = <&max77621_cpu>; - }; - - aconnect@702c0000 { - status = "okay"; - - dma@702e2000 { - status = "okay"; - }; - - agic@702f9000 { - status = "okay"; - }; - }; - - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - cpus { - cpu@0 { - enable-method = "psci"; - }; - - cpu@1 { - enable-method = "psci"; - }; - - cpu@2 { - enable-method = "psci"; - }; - - cpu@3 { - enable-method = "psci"; - }; - - idle-states { - cpu-sleep { - arm,psci-suspend-param = <0x00010007>; - status = "okay"; - }; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - power { - label = "Power"; - gpios = <&gpio TEGRA_GPIO(X, 5) GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <30>; - wakeup-source; - }; - - lid { - label = "Lid"; - gpios = <&gpio TEGRA_GPIO(B, 4) GPIO_ACTIVE_LOW>; - linux,input-type = ; - linux,code = ; - wakeup-source; - }; - - tablet_mode { - label = "Tablet Mode"; - gpios = <&gpio TEGRA_GPIO(Z, 2) GPIO_ACTIVE_HIGH>; - linux,input-type = ; - linux,code = ; - wakeup-source; - }; - - volume_down { - label = "Volume Down"; - gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - volume_up { - label = "Volume Up"; - gpios = <&gpio TEGRA_GPIO(M, 4) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - max98357a { - compatible = "maxim,max98357a"; - status = "okay"; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - regulators { - compatible = "simple-bus"; - device_type = "fixed-regulators"; - #address-cells = <1>; - #size-cells = <0>; - - ppvar_sys: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "PPVAR_SYS"; - regulator-min-microvolt = <4400000>; - regulator-max-microvolt = <4400000>; - regulator-always-on; - }; - - pplcd_vdd: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "PPLCD_VDD"; - regulator-min-microvolt = <4400000>; - regulator-max-microvolt = <4400000>; - gpio = <&gpio TEGRA_GPIO(V, 4) 0>; - enable-active-high; - regulator-boot-on; - }; - - pp3000_always: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "PP3000_ALWAYS"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - }; - - pp3300: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "PP3300"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - enable-active-high; - }; - - pp5000: regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "PP5000"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - pp1800_lcdio: regulator@5 { - compatible = "regulator-fixed"; - reg = <5>; - regulator-name = "PP1800_LCDIO"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio TEGRA_GPIO(V, 3) 0>; - enable-active-high; - regulator-boot-on; - }; - - pp1800_cam: regulator@6 { - compatible = "regulator-fixed"; - reg= <6>; - regulator-name = "PP1800_CAM"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio TEGRA_GPIO(K, 3) 0>; - enable-active-high; - }; - - usbc_vbus: regulator@7 { - compatible = "regulator-fixed"; - reg = <7>; - regulator-name = "USBC_VBUS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/nvidia/tegra210.dtsi b/sys/gnu/dts/arm64/nvidia/tegra210.dtsi deleted file mode 100644 index 48c63256ba7..00000000000 --- a/sys/gnu/dts/arm64/nvidia/tegra210.dtsi +++ /dev/null @@ -1,1599 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include -#include -#include -#include -#include -#include -#include -#include - -/ { - compatible = "nvidia,tegra210"; - interrupt-parent = <&lic>; - #address-cells = <2>; - #size-cells = <2>; - - pcie@1003000 { - compatible = "nvidia,tegra210-pcie"; - device_type = "pci"; - reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */ - 0x0 0x01003800 0x0 0x00000800 /* AFI registers */ - 0x0 0x02000000 0x0 0x10000000>; /* configuration space */ - reg-names = "pads", "afi", "cs"; - interrupts = , /* controller interrupt */ - ; /* MSI interrupt */ - interrupt-names = "intr", "msi"; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; - - bus-range = <0x00 0xff>; - #address-cells = <3>; - #size-cells = <2>; - - ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */ - 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */ - 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */ - 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */ - 0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ - - clocks = <&tegra_car TEGRA210_CLK_PCIE>, - <&tegra_car TEGRA210_CLK_AFI>, - <&tegra_car TEGRA210_CLK_PLL_E>, - <&tegra_car TEGRA210_CLK_CML0>; - clock-names = "pex", "afi", "pll_e", "cml"; - resets = <&tegra_car 70>, - <&tegra_car 72>, - <&tegra_car 74>; - reset-names = "pex", "afi", "pcie_x"; - - pinctrl-names = "default", "idle"; - pinctrl-0 = <&pex_dpd_disable>; - pinctrl-1 = <&pex_dpd_enable>; - - status = "disabled"; - - pci@1,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>; - reg = <0x000800 0 0 0 0>; - bus-range = <0x00 0xff>; - status = "disabled"; - - #address-cells = <3>; - #size-cells = <2>; - ranges; - - nvidia,num-lanes = <4>; - }; - - pci@2,0 { - device_type = "pci"; - assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>; - reg = <0x001000 0 0 0 0>; - bus-range = <0x00 0xff>; - status = "disabled"; - - #address-cells = <3>; - #size-cells = <2>; - ranges; - - nvidia,num-lanes = <1>; - }; - }; - - host1x@50000000 { - compatible = "nvidia,tegra210-host1x", "simple-bus"; - reg = <0x0 0x50000000 0x0 0x00034000>; - interrupts = , /* syncpt */ - ; /* general */ - clocks = <&tegra_car TEGRA210_CLK_HOST1X>; - clock-names = "host1x"; - resets = <&tegra_car 28>; - reset-names = "host1x"; - - #address-cells = <2>; - #size-cells = <2>; - - ranges = <0x0 0x54000000 0x0 0x54000000 0x0 0x01000000>; - - iommus = <&mc TEGRA_SWGROUP_HC>; - - dpaux1: dpaux@54040000 { - compatible = "nvidia,tegra210-dpaux"; - reg = <0x0 0x54040000 0x0 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA210_CLK_DPAUX1>, - <&tegra_car TEGRA210_CLK_PLL_DP>; - clock-names = "dpaux", "parent"; - resets = <&tegra_car 207>; - reset-names = "dpaux"; - power-domains = <&pd_sor>; - status = "disabled"; - - state_dpaux1_aux: pinmux-aux { - groups = "dpaux-io"; - function = "aux"; - }; - - state_dpaux1_i2c: pinmux-i2c { - groups = "dpaux-io"; - function = "i2c"; - }; - - state_dpaux1_off: pinmux-off { - groups = "dpaux-io"; - function = "off"; - }; - - i2c-bus { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - vi@54080000 { - compatible = "nvidia,tegra210-vi"; - reg = <0x0 0x54080000 0x0 0x00040000>; - interrupts = ; - status = "disabled"; - }; - - tsec@54100000 { - compatible = "nvidia,tegra210-tsec"; - reg = <0x0 0x54100000 0x0 0x00040000>; - }; - - dc@54200000 { - compatible = "nvidia,tegra210-dc"; - reg = <0x0 0x54200000 0x0 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA210_CLK_DISP1>, - <&tegra_car TEGRA210_CLK_PLL_P>; - clock-names = "dc", "parent"; - resets = <&tegra_car 27>; - reset-names = "dc"; - - iommus = <&mc TEGRA_SWGROUP_DC>; - - nvidia,head = <0>; - }; - - dc@54240000 { - compatible = "nvidia,tegra210-dc"; - reg = <0x0 0x54240000 0x0 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA210_CLK_DISP2>, - <&tegra_car TEGRA210_CLK_PLL_P>; - clock-names = "dc", "parent"; - resets = <&tegra_car 26>; - reset-names = "dc"; - - iommus = <&mc TEGRA_SWGROUP_DCB>; - - nvidia,head = <1>; - }; - - dsi@54300000 { - compatible = "nvidia,tegra210-dsi"; - reg = <0x0 0x54300000 0x0 0x00040000>; - clocks = <&tegra_car TEGRA210_CLK_DSIA>, - <&tegra_car TEGRA210_CLK_DSIALP>, - <&tegra_car TEGRA210_CLK_PLL_D_OUT0>; - clock-names = "dsi", "lp", "parent"; - resets = <&tegra_car 48>; - reset-names = "dsi"; - power-domains = <&pd_sor>; - nvidia,mipi-calibrate = <&mipi 0x0c0>; /* DSIA & DSIB pads */ - - status = "disabled"; - - #address-cells = <1>; - #size-cells = <0>; - }; - - vic@54340000 { - compatible = "nvidia,tegra210-vic"; - reg = <0x0 0x54340000 0x0 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA210_CLK_VIC03>; - clock-names = "vic"; - resets = <&tegra_car 178>; - reset-names = "vic"; - - iommus = <&mc TEGRA_SWGROUP_VIC>; - power-domains = <&pd_vic>; - }; - - nvjpg@54380000 { - compatible = "nvidia,tegra210-nvjpg"; - reg = <0x0 0x54380000 0x0 0x00040000>; - status = "disabled"; - }; - - dsi@54400000 { - compatible = "nvidia,tegra210-dsi"; - reg = <0x0 0x54400000 0x0 0x00040000>; - clocks = <&tegra_car TEGRA210_CLK_DSIB>, - <&tegra_car TEGRA210_CLK_DSIBLP>, - <&tegra_car TEGRA210_CLK_PLL_D_OUT0>; - clock-names = "dsi", "lp", "parent"; - resets = <&tegra_car 82>; - reset-names = "dsi"; - power-domains = <&pd_sor>; - nvidia,mipi-calibrate = <&mipi 0x300>; /* DSIC & DSID pads */ - - status = "disabled"; - - #address-cells = <1>; - #size-cells = <0>; - }; - - nvdec@54480000 { - compatible = "nvidia,tegra210-nvdec"; - reg = <0x0 0x54480000 0x0 0x00040000>; - status = "disabled"; - }; - - nvenc@544c0000 { - compatible = "nvidia,tegra210-nvenc"; - reg = <0x0 0x544c0000 0x0 0x00040000>; - status = "disabled"; - }; - - tsec@54500000 { - compatible = "nvidia,tegra210-tsec"; - reg = <0x0 0x54500000 0x0 0x00040000>; - status = "disabled"; - }; - - sor@54540000 { - compatible = "nvidia,tegra210-sor"; - reg = <0x0 0x54540000 0x0 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA210_CLK_SOR0>, - <&tegra_car TEGRA210_CLK_SOR0_OUT>, - <&tegra_car TEGRA210_CLK_PLL_D_OUT0>, - <&tegra_car TEGRA210_CLK_PLL_DP>, - <&tegra_car TEGRA210_CLK_SOR_SAFE>; - clock-names = "sor", "out", "parent", "dp", "safe"; - resets = <&tegra_car 182>; - reset-names = "sor"; - pinctrl-0 = <&state_dpaux_aux>; - pinctrl-1 = <&state_dpaux_i2c>; - pinctrl-2 = <&state_dpaux_off>; - pinctrl-names = "aux", "i2c", "off"; - power-domains = <&pd_sor>; - status = "disabled"; - }; - - sor@54580000 { - compatible = "nvidia,tegra210-sor1"; - reg = <0x0 0x54580000 0x0 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA210_CLK_SOR1>, - <&tegra_car TEGRA210_CLK_SOR1_OUT>, - <&tegra_car TEGRA210_CLK_PLL_D2_OUT0>, - <&tegra_car TEGRA210_CLK_PLL_DP>, - <&tegra_car TEGRA210_CLK_SOR_SAFE>; - clock-names = "sor", "out", "parent", "dp", "safe"; - resets = <&tegra_car 183>; - reset-names = "sor"; - pinctrl-0 = <&state_dpaux1_aux>; - pinctrl-1 = <&state_dpaux1_i2c>; - pinctrl-2 = <&state_dpaux1_off>; - pinctrl-names = "aux", "i2c", "off"; - power-domains = <&pd_sor>; - status = "disabled"; - }; - - dpaux: dpaux@545c0000 { - compatible = "nvidia,tegra124-dpaux"; - reg = <0x0 0x545c0000 0x0 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA210_CLK_DPAUX>, - <&tegra_car TEGRA210_CLK_PLL_DP>; - clock-names = "dpaux", "parent"; - resets = <&tegra_car 181>; - reset-names = "dpaux"; - power-domains = <&pd_sor>; - status = "disabled"; - - state_dpaux_aux: pinmux-aux { - groups = "dpaux-io"; - function = "aux"; - }; - - state_dpaux_i2c: pinmux-i2c { - groups = "dpaux-io"; - function = "i2c"; - }; - - state_dpaux_off: pinmux-off { - groups = "dpaux-io"; - function = "off"; - }; - - i2c-bus { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - isp@54600000 { - compatible = "nvidia,tegra210-isp"; - reg = <0x0 0x54600000 0x0 0x00040000>; - interrupts = ; - status = "disabled"; - }; - - isp@54680000 { - compatible = "nvidia,tegra210-isp"; - reg = <0x0 0x54680000 0x0 0x00040000>; - interrupts = ; - status = "disabled"; - }; - - i2c@546c0000 { - compatible = "nvidia,tegra210-i2c-vi"; - reg = <0x0 0x546c0000 0x0 0x00040000>; - interrupts = ; - status = "disabled"; - }; - }; - - gic: interrupt-controller@50041000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x0 0x50041000 0x0 0x1000>, - <0x0 0x50042000 0x0 0x2000>, - <0x0 0x50044000 0x0 0x2000>, - <0x0 0x50046000 0x0 0x2000>; - interrupts = ; - interrupt-parent = <&gic>; - }; - - gpu@57000000 { - compatible = "nvidia,gm20b"; - reg = <0x0 0x57000000 0x0 0x01000000>, - <0x0 0x58000000 0x0 0x01000000>; - interrupts = , - ; - interrupt-names = "stall", "nonstall"; - clocks = <&tegra_car TEGRA210_CLK_GPU>, - <&tegra_car TEGRA210_CLK_PLL_P_OUT5>, - <&tegra_car TEGRA210_CLK_PLL_G_REF>; - clock-names = "gpu", "pwr", "ref"; - resets = <&tegra_car 184>; - reset-names = "gpu"; - - iommus = <&mc TEGRA_SWGROUP_GPU>; - - status = "disabled"; - }; - - lic: interrupt-controller@60004000 { - compatible = "nvidia,tegra210-ictlr"; - reg = <0x0 0x60004000 0x0 0x40>, /* primary controller */ - <0x0 0x60004100 0x0 0x40>, /* secondary controller */ - <0x0 0x60004200 0x0 0x40>, /* tertiary controller */ - <0x0 0x60004300 0x0 0x40>, /* quaternary controller */ - <0x0 0x60004400 0x0 0x40>, /* quinary controller */ - <0x0 0x60004500 0x0 0x40>; /* senary controller */ - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - }; - - timer@60005000 { - compatible = "nvidia,tegra210-timer"; - reg = <0x0 0x60005000 0x0 0x400>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - ; - clocks = <&tegra_car TEGRA210_CLK_TIMER>; - clock-names = "timer"; - }; - - tegra_car: clock@60006000 { - compatible = "nvidia,tegra210-car"; - reg = <0x0 0x60006000 0x0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - flow-controller@60007000 { - compatible = "nvidia,tegra210-flowctrl"; - reg = <0x0 0x60007000 0x0 0x1000>; - }; - - gpio: gpio@6000d000 { - compatible = "nvidia,tegra210-gpio", "nvidia,tegra30-gpio"; - reg = <0x0 0x6000d000 0x0 0x1000>; - interrupts = , - , - , - , - , - , - , - ; - #gpio-cells = <2>; - gpio-controller; - #interrupt-cells = <2>; - interrupt-controller; - }; - - apbdma: dma@60020000 { - compatible = "nvidia,tegra210-apbdma", "nvidia,tegra148-apbdma"; - reg = <0x0 0x60020000 0x0 0x1400>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - clocks = <&tegra_car TEGRA210_CLK_APBDMA>; - clock-names = "dma"; - resets = <&tegra_car 34>; - reset-names = "dma"; - #dma-cells = <1>; - }; - - apbmisc@70000800 { - compatible = "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc"; - reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */ - <0x0 0x70000008 0x0 0x04>; /* Strapping options */ - }; - - pinmux: pinmux@700008d4 { - compatible = "nvidia,tegra210-pinmux"; - reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */ - <0x0 0x70003000 0x0 0x294>; /* Mux registers */ - sdmmc1_3v3_drv: sdmmc1-3v3-drv { - sdmmc1 { - nvidia,pins = "drive_sdmmc1"; - nvidia,pull-down-strength = <0x8>; - nvidia,pull-up-strength = <0x8>; - }; - }; - sdmmc1_1v8_drv: sdmmc1-1v8-drv { - sdmmc1 { - nvidia,pins = "drive_sdmmc1"; - nvidia,pull-down-strength = <0x4>; - nvidia,pull-up-strength = <0x3>; - }; - }; - sdmmc2_1v8_drv: sdmmc2-1v8-drv { - sdmmc2 { - nvidia,pins = "drive_sdmmc2"; - nvidia,pull-down-strength = <0x10>; - nvidia,pull-up-strength = <0x10>; - }; - }; - sdmmc3_3v3_drv: sdmmc3-3v3-drv { - sdmmc3 { - nvidia,pins = "drive_sdmmc3"; - nvidia,pull-down-strength = <0x8>; - nvidia,pull-up-strength = <0x8>; - }; - }; - sdmmc3_1v8_drv: sdmmc3-1v8-drv { - sdmmc3 { - nvidia,pins = "drive_sdmmc3"; - nvidia,pull-down-strength = <0x4>; - nvidia,pull-up-strength = <0x3>; - }; - }; - sdmmc4_1v8_drv: sdmmc4-1v8-drv { - sdmmc4 { - nvidia,pins = "drive_sdmmc4"; - nvidia,pull-down-strength = <0x10>; - nvidia,pull-up-strength = <0x10>; - }; - }; - }; - - /* - * There are two serial driver i.e. 8250 based simple serial - * driver and APB DMA based serial driver for higher baudrate - * and performance. To enable the 8250 based driver, the compatible - * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable - * the APB DMA based serial driver, the compatible is - * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". - */ - uarta: serial@70006000 { - compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; - reg = <0x0 0x70006000 0x0 0x40>; - reg-shift = <2>; - interrupts = ; - clocks = <&tegra_car TEGRA210_CLK_UARTA>; - clock-names = "serial"; - resets = <&tegra_car 6>; - reset-names = "serial"; - dmas = <&apbdma 8>, <&apbdma 8>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uartb: serial@70006040 { - compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; - reg = <0x0 0x70006040 0x0 0x40>; - reg-shift = <2>; - interrupts = ; - clocks = <&tegra_car TEGRA210_CLK_UARTB>; - clock-names = "serial"; - resets = <&tegra_car 7>; - reset-names = "serial"; - dmas = <&apbdma 9>, <&apbdma 9>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uartc: serial@70006200 { - compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; - reg = <0x0 0x70006200 0x0 0x40>; - reg-shift = <2>; - interrupts = ; - clocks = <&tegra_car TEGRA210_CLK_UARTC>; - clock-names = "serial"; - resets = <&tegra_car 55>; - reset-names = "serial"; - dmas = <&apbdma 10>, <&apbdma 10>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uartd: serial@70006300 { - compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; - reg = <0x0 0x70006300 0x0 0x40>; - reg-shift = <2>; - interrupts = ; - clocks = <&tegra_car TEGRA210_CLK_UARTD>; - clock-names = "serial"; - resets = <&tegra_car 65>; - reset-names = "serial"; - dmas = <&apbdma 19>, <&apbdma 19>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - pwm: pwm@7000a000 { - compatible = "nvidia,tegra210-pwm", "nvidia,tegra20-pwm"; - reg = <0x0 0x7000a000 0x0 0x100>; - #pwm-cells = <2>; - clocks = <&tegra_car TEGRA210_CLK_PWM>; - clock-names = "pwm"; - resets = <&tegra_car 17>; - reset-names = "pwm"; - status = "disabled"; - }; - - i2c@7000c000 { - compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; - reg = <0x0 0x7000c000 0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA210_CLK_I2C1>; - clock-names = "div-clk"; - resets = <&tegra_car 12>; - reset-names = "i2c"; - dmas = <&apbdma 21>, <&apbdma 21>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c@7000c400 { - compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; - reg = <0x0 0x7000c400 0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA210_CLK_I2C2>; - clock-names = "div-clk"; - resets = <&tegra_car 54>; - reset-names = "i2c"; - dmas = <&apbdma 22>, <&apbdma 22>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c@7000c500 { - compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; - reg = <0x0 0x7000c500 0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA210_CLK_I2C3>; - clock-names = "div-clk"; - resets = <&tegra_car 67>; - reset-names = "i2c"; - dmas = <&apbdma 23>, <&apbdma 23>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c@7000c700 { - compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; - reg = <0x0 0x7000c700 0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA210_CLK_I2C4>; - clock-names = "div-clk"; - resets = <&tegra_car 103>; - reset-names = "i2c"; - dmas = <&apbdma 26>, <&apbdma 26>; - dma-names = "rx", "tx"; - pinctrl-0 = <&state_dpaux1_i2c>; - pinctrl-1 = <&state_dpaux1_off>; - pinctrl-names = "default", "idle"; - status = "disabled"; - }; - - i2c@7000d000 { - compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; - reg = <0x0 0x7000d000 0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA210_CLK_I2C5>; - clock-names = "div-clk"; - resets = <&tegra_car 47>; - reset-names = "i2c"; - dmas = <&apbdma 24>, <&apbdma 24>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c@7000d100 { - compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; - reg = <0x0 0x7000d100 0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA210_CLK_I2C6>; - clock-names = "div-clk"; - resets = <&tegra_car 166>; - reset-names = "i2c"; - dmas = <&apbdma 30>, <&apbdma 30>; - dma-names = "rx", "tx"; - pinctrl-0 = <&state_dpaux_i2c>; - pinctrl-1 = <&state_dpaux_off>; - pinctrl-names = "default", "idle"; - status = "disabled"; - }; - - spi@7000d400 { - compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; - reg = <0x0 0x7000d400 0x0 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA210_CLK_SBC1>; - clock-names = "spi"; - resets = <&tegra_car 41>; - reset-names = "spi"; - dmas = <&apbdma 15>, <&apbdma 15>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi@7000d600 { - compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; - reg = <0x0 0x7000d600 0x0 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA210_CLK_SBC2>; - clock-names = "spi"; - resets = <&tegra_car 44>; - reset-names = "spi"; - dmas = <&apbdma 16>, <&apbdma 16>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi@7000d800 { - compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; - reg = <0x0 0x7000d800 0x0 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA210_CLK_SBC3>; - clock-names = "spi"; - resets = <&tegra_car 46>; - reset-names = "spi"; - dmas = <&apbdma 17>, <&apbdma 17>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi@7000da00 { - compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; - reg = <0x0 0x7000da00 0x0 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA210_CLK_SBC4>; - clock-names = "spi"; - resets = <&tegra_car 68>; - reset-names = "spi"; - dmas = <&apbdma 18>, <&apbdma 18>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - rtc@7000e000 { - compatible = "nvidia,tegra210-rtc", "nvidia,tegra20-rtc"; - reg = <0x0 0x7000e000 0x0 0x100>; - interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; - interrupt-parent = <&pmc>; - clocks = <&tegra_car TEGRA210_CLK_RTC>; - clock-names = "rtc"; - }; - - pmc: pmc@7000e400 { - compatible = "nvidia,tegra210-pmc"; - reg = <0x0 0x7000e400 0x0 0x400>; - clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; - clock-names = "pclk", "clk32k_in"; - #interrupt-cells = <2>; - interrupt-controller; - - powergates { - pd_audio: aud { - clocks = <&tegra_car TEGRA210_CLK_APE>, - <&tegra_car TEGRA210_CLK_APB2APE>; - resets = <&tegra_car 198>; - #power-domain-cells = <0>; - }; - - pd_sor: sor { - clocks = <&tegra_car TEGRA210_CLK_SOR0>, - <&tegra_car TEGRA210_CLK_SOR1>, - <&tegra_car TEGRA210_CLK_CSI>, - <&tegra_car TEGRA210_CLK_DSIA>, - <&tegra_car TEGRA210_CLK_DSIB>, - <&tegra_car TEGRA210_CLK_DPAUX>, - <&tegra_car TEGRA210_CLK_DPAUX1>, - <&tegra_car TEGRA210_CLK_MIPI_CAL>; - resets = <&tegra_car TEGRA210_CLK_SOR0>, - <&tegra_car TEGRA210_CLK_SOR1>, - <&tegra_car TEGRA210_CLK_CSI>, - <&tegra_car TEGRA210_CLK_DSIA>, - <&tegra_car TEGRA210_CLK_DSIB>, - <&tegra_car TEGRA210_CLK_DPAUX>, - <&tegra_car TEGRA210_CLK_DPAUX1>, - <&tegra_car TEGRA210_CLK_MIPI_CAL>; - #power-domain-cells = <0>; - }; - - pd_xusbss: xusba { - clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>; - resets = <&tegra_car TEGRA210_CLK_XUSB_SS>; - #power-domain-cells = <0>; - }; - - pd_xusbdev: xusbb { - clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>; - resets = <&tegra_car 95>; - #power-domain-cells = <0>; - }; - - pd_xusbhost: xusbc { - clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>; - resets = <&tegra_car TEGRA210_CLK_XUSB_HOST>; - #power-domain-cells = <0>; - }; - - pd_vic: vic { - clocks = <&tegra_car TEGRA210_CLK_VIC03>; - clock-names = "vic"; - resets = <&tegra_car 178>; - reset-names = "vic"; - #power-domain-cells = <0>; - }; - }; - - sdmmc1_3v3: sdmmc1-3v3 { - pins = "sdmmc1"; - power-source = ; - }; - - sdmmc1_1v8: sdmmc1-1v8 { - pins = "sdmmc1"; - power-source = ; - }; - - sdmmc3_3v3: sdmmc3-3v3 { - pins = "sdmmc3"; - power-source = ; - }; - - sdmmc3_1v8: sdmmc3-1v8 { - pins = "sdmmc3"; - power-source = ; - }; - - pex_dpd_disable: pex_en { - pex-dpd-disable { - pins = "pex-bias", "pex-clk1", "pex-clk2"; - low-power-disable; - }; - }; - - pex_dpd_enable: pex_dis { - pex-dpd-enable { - pins = "pex-bias", "pex-clk1", "pex-clk2"; - low-power-enable; - }; - }; - }; - - fuse@7000f800 { - compatible = "nvidia,tegra210-efuse"; - reg = <0x0 0x7000f800 0x0 0x400>; - clocks = <&tegra_car TEGRA210_CLK_FUSE>; - clock-names = "fuse"; - resets = <&tegra_car 39>; - reset-names = "fuse"; - }; - - mc: memory-controller@70019000 { - compatible = "nvidia,tegra210-mc"; - reg = <0x0 0x70019000 0x0 0x1000>; - clocks = <&tegra_car TEGRA210_CLK_MC>; - clock-names = "mc"; - - interrupts = ; - - #iommu-cells = <1>; - }; - - sata@70020000 { - compatible = "nvidia,tegra210-ahci"; - reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */ - <0x0 0x70020000 0x0 0x7000>, /* SATA */ - <0x0 0x70001100 0x0 0x1000>; /* SATA AUX */ - interrupts = ; - clocks = <&tegra_car TEGRA210_CLK_SATA>, - <&tegra_car TEGRA210_CLK_SATA_OOB>; - clock-names = "sata", "sata-oob"; - resets = <&tegra_car 124>, - <&tegra_car 123>, - <&tegra_car 129>; - reset-names = "sata", "sata-oob", "sata-cold"; - status = "disabled"; - }; - - hda@70030000 { - compatible = "nvidia,tegra210-hda", "nvidia,tegra30-hda"; - reg = <0x0 0x70030000 0x0 0x10000>; - interrupts = ; - clocks = <&tegra_car TEGRA210_CLK_HDA>, - <&tegra_car TEGRA210_CLK_HDA2HDMI>, - <&tegra_car TEGRA210_CLK_HDA2CODEC_2X>; - clock-names = "hda", "hda2hdmi", "hda2codec_2x"; - resets = <&tegra_car 125>, /* hda */ - <&tegra_car 128>, /* hda2hdmi */ - <&tegra_car 111>; /* hda2codec_2x */ - reset-names = "hda", "hda2hdmi", "hda2codec_2x"; - status = "disabled"; - }; - - usb@70090000 { - compatible = "nvidia,tegra210-xusb"; - reg = <0x0 0x70090000 0x0 0x8000>, - <0x0 0x70098000 0x0 0x1000>, - <0x0 0x70099000 0x0 0x1000>; - reg-names = "hcd", "fpci", "ipfs"; - - interrupts = , - ; - - clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>, - <&tegra_car TEGRA210_CLK_XUSB_HOST_SRC>, - <&tegra_car TEGRA210_CLK_XUSB_FALCON_SRC>, - <&tegra_car TEGRA210_CLK_XUSB_SS>, - <&tegra_car TEGRA210_CLK_XUSB_SS_DIV2>, - <&tegra_car TEGRA210_CLK_XUSB_SS_SRC>, - <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>, - <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>, - <&tegra_car TEGRA210_CLK_PLL_U_480M>, - <&tegra_car TEGRA210_CLK_CLK_M>, - <&tegra_car TEGRA210_CLK_PLL_E>; - clock-names = "xusb_host", "xusb_host_src", - "xusb_falcon_src", "xusb_ss", - "xusb_ss_div2", "xusb_ss_src", - "xusb_hs_src", "xusb_fs_src", - "pll_u_480m", "clk_m", "pll_e"; - resets = <&tegra_car 89>, <&tegra_car 156>, - <&tegra_car 143>; - reset-names = "xusb_host", "xusb_ss", "xusb_src"; - power-domains = <&pd_xusbhost>, <&pd_xusbss>; - power-domain-names = "xusb_host", "xusb_ss"; - - nvidia,xusb-padctl = <&padctl>; - - status = "disabled"; - }; - - padctl: padctl@7009f000 { - compatible = "nvidia,tegra210-xusb-padctl"; - reg = <0x0 0x7009f000 0x0 0x1000>; - resets = <&tegra_car 142>; - reset-names = "padctl"; - - status = "disabled"; - - pads { - usb2 { - clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>; - clock-names = "trk"; - status = "disabled"; - - lanes { - usb2-0 { - status = "disabled"; - #phy-cells = <0>; - }; - - usb2-1 { - status = "disabled"; - #phy-cells = <0>; - }; - - usb2-2 { - status = "disabled"; - #phy-cells = <0>; - }; - - usb2-3 { - status = "disabled"; - #phy-cells = <0>; - }; - }; - }; - - hsic { - clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>; - clock-names = "trk"; - status = "disabled"; - - lanes { - hsic-0 { - status = "disabled"; - #phy-cells = <0>; - }; - - hsic-1 { - status = "disabled"; - #phy-cells = <0>; - }; - }; - }; - - pcie { - clocks = <&tegra_car TEGRA210_CLK_PLL_E>; - clock-names = "pll"; - resets = <&tegra_car 205>; - reset-names = "phy"; - status = "disabled"; - - lanes { - pcie-0 { - status = "disabled"; - #phy-cells = <0>; - }; - - pcie-1 { - status = "disabled"; - #phy-cells = <0>; - }; - - pcie-2 { - status = "disabled"; - #phy-cells = <0>; - }; - - pcie-3 { - status = "disabled"; - #phy-cells = <0>; - }; - - pcie-4 { - status = "disabled"; - #phy-cells = <0>; - }; - - pcie-5 { - status = "disabled"; - #phy-cells = <0>; - }; - - pcie-6 { - status = "disabled"; - #phy-cells = <0>; - }; - }; - }; - - sata { - clocks = <&tegra_car TEGRA210_CLK_PLL_E>; - clock-names = "pll"; - resets = <&tegra_car 204>; - reset-names = "phy"; - status = "disabled"; - - lanes { - sata-0 { - status = "disabled"; - #phy-cells = <0>; - }; - }; - }; - }; - - ports { - usb2-0 { - status = "disabled"; - }; - - usb2-1 { - status = "disabled"; - }; - - usb2-2 { - status = "disabled"; - }; - - usb2-3 { - status = "disabled"; - }; - - hsic-0 { - status = "disabled"; - }; - - usb3-0 { - status = "disabled"; - }; - - usb3-1 { - status = "disabled"; - }; - - usb3-2 { - status = "disabled"; - }; - - usb3-3 { - status = "disabled"; - }; - }; - }; - - sdhci@700b0000 { - compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; - reg = <0x0 0x700b0000 0x0 0x200>; - interrupts = ; - clocks = <&tegra_car TEGRA210_CLK_SDMMC1>; - clock-names = "sdhci"; - resets = <&tegra_car 14>; - reset-names = "sdhci"; - pinctrl-names = "sdmmc-3v3", "sdmmc-1v8", - "sdmmc-3v3-drv", "sdmmc-1v8-drv"; - pinctrl-0 = <&sdmmc1_3v3>; - pinctrl-1 = <&sdmmc1_1v8>; - pinctrl-2 = <&sdmmc1_3v3_drv>; - pinctrl-3 = <&sdmmc1_1v8_drv>; - nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>; - nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>; - nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>; - nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>; - nvidia,default-tap = <0x2>; - nvidia,default-trim = <0x4>; - assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>, - <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>, - <&tegra_car TEGRA210_CLK_PLL_C4>; - assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; - assigned-clock-rates = <200000000>, <1000000000>, <1000000000>; - status = "disabled"; - }; - - sdhci@700b0200 { - compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; - reg = <0x0 0x700b0200 0x0 0x200>; - interrupts = ; - clocks = <&tegra_car TEGRA210_CLK_SDMMC2>; - clock-names = "sdhci"; - resets = <&tegra_car 9>; - reset-names = "sdhci"; - pinctrl-names = "sdmmc-1v8-drv"; - pinctrl-0 = <&sdmmc2_1v8_drv>; - nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>; - nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>; - nvidia,default-tap = <0x8>; - nvidia,default-trim = <0x0>; - status = "disabled"; - }; - - sdhci@700b0400 { - compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; - reg = <0x0 0x700b0400 0x0 0x200>; - interrupts = ; - clocks = <&tegra_car TEGRA210_CLK_SDMMC3>; - clock-names = "sdhci"; - resets = <&tegra_car 69>; - reset-names = "sdhci"; - pinctrl-names = "sdmmc-3v3", "sdmmc-1v8", - "sdmmc-3v3-drv", "sdmmc-1v8-drv"; - pinctrl-0 = <&sdmmc3_3v3>; - pinctrl-1 = <&sdmmc3_1v8>; - pinctrl-2 = <&sdmmc3_3v3_drv>; - pinctrl-3 = <&sdmmc3_1v8_drv>; - nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>; - nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>; - nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>; - nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>; - nvidia,default-tap = <0x3>; - nvidia,default-trim = <0x3>; - status = "disabled"; - }; - - sdhci@700b0600 { - compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; - reg = <0x0 0x700b0600 0x0 0x200>; - interrupts = ; - clocks = <&tegra_car TEGRA210_CLK_SDMMC4>; - clock-names = "sdhci"; - resets = <&tegra_car 15>; - reset-names = "sdhci"; - pinctrl-names = "sdmmc-3v3-drv", "sdmmc-1v8-drv"; - pinctrl-0 = <&sdmmc4_1v8_drv>; - pinctrl-1 = <&sdmmc4_1v8_drv>; - nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>; - nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>; - nvidia,default-tap = <0x8>; - nvidia,default-trim = <0x0>; - assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>, - <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; - assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; - nvidia,dqs-trim = <40>; - mmc-hs400-1_8v; - status = "disabled"; - }; - - mipi: mipi@700e3000 { - compatible = "nvidia,tegra210-mipi"; - reg = <0x0 0x700e3000 0x0 0x100>; - clocks = <&tegra_car TEGRA210_CLK_MIPI_CAL>; - clock-names = "mipi-cal"; - power-domains = <&pd_sor>; - #nvidia,mipi-calibrate-cells = <1>; - }; - - dfll: clock@70110000 { - compatible = "nvidia,tegra210-dfll"; - reg = <0 0x70110000 0 0x100>, /* DFLL control */ - <0 0x70110000 0 0x100>, /* I2C output control */ - <0 0x70110100 0 0x100>, /* Integrated I2C controller */ - <0 0x70110200 0 0x100>; /* Look-up table RAM */ - interrupts = ; - clocks = <&tegra_car TEGRA210_CLK_DFLL_SOC>, - <&tegra_car TEGRA210_CLK_DFLL_REF>, - <&tegra_car TEGRA210_CLK_I2C5>; - clock-names = "soc", "ref", "i2c"; - resets = <&tegra_car TEGRA210_RST_DFLL_DVCO>; - reset-names = "dvco"; - #clock-cells = <0>; - clock-output-names = "dfllCPU_out"; - status = "disabled"; - }; - - aconnect@702c0000 { - compatible = "nvidia,tegra210-aconnect"; - clocks = <&tegra_car TEGRA210_CLK_APE>, - <&tegra_car TEGRA210_CLK_APB2APE>; - clock-names = "ape", "apb2ape"; - power-domains = <&pd_audio>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x702c0000 0x0 0x702c0000 0x00040000>; - status = "disabled"; - - adma: dma@702e2000 { - compatible = "nvidia,tegra210-adma"; - reg = <0x702e2000 0x2000>; - interrupt-parent = <&agic>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - #dma-cells = <1>; - clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>; - clock-names = "d_audio"; - status = "disabled"; - }; - - agic: agic@702f9000 { - compatible = "nvidia,tegra210-agic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x702f9000 0x1000>, - <0x702fa000 0x2000>; - interrupts = ; - clocks = <&tegra_car TEGRA210_CLK_APE>; - clock-names = "clk"; - status = "disabled"; - }; - }; - - spi@70410000 { - compatible = "nvidia,tegra210-qspi"; - reg = <0x0 0x70410000 0x0 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA210_CLK_QSPI>; - clock-names = "qspi"; - resets = <&tegra_car 211>; - reset-names = "qspi"; - dmas = <&apbdma 5>, <&apbdma 5>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - usb@7d000000 { - compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci"; - reg = <0x0 0x7d000000 0x0 0x4000>; - interrupts = ; - phy_type = "utmi"; - clocks = <&tegra_car TEGRA210_CLK_USBD>; - clock-names = "usb"; - resets = <&tegra_car 22>; - reset-names = "usb"; - nvidia,phy = <&phy1>; - status = "disabled"; - }; - - phy1: usb-phy@7d000000 { - compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy"; - reg = <0x0 0x7d000000 0x0 0x4000>, - <0x0 0x7d000000 0x0 0x4000>; - phy_type = "utmi"; - clocks = <&tegra_car TEGRA210_CLK_USBD>, - <&tegra_car TEGRA210_CLK_PLL_U>, - <&tegra_car TEGRA210_CLK_USBD>; - clock-names = "reg", "pll_u", "utmi-pads"; - resets = <&tegra_car 22>, <&tegra_car 22>; - reset-names = "usb", "utmi-pads"; - nvidia,hssync-start-delay = <0>; - nvidia,idle-wait-delay = <17>; - nvidia,elastic-limit = <16>; - nvidia,term-range-adj = <6>; - nvidia,xcvr-setup = <9>; - nvidia,xcvr-lsfslew = <0>; - nvidia,xcvr-lsrslew = <3>; - nvidia,hssquelch-level = <2>; - nvidia,hsdiscon-level = <5>; - nvidia,xcvr-hsslew = <12>; - nvidia,has-utmi-pad-registers; - status = "disabled"; - }; - - usb@7d004000 { - compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci"; - reg = <0x0 0x7d004000 0x0 0x4000>; - interrupts = ; - phy_type = "utmi"; - clocks = <&tegra_car TEGRA210_CLK_USB2>; - clock-names = "usb"; - resets = <&tegra_car 58>; - reset-names = "usb"; - nvidia,phy = <&phy2>; - status = "disabled"; - }; - - phy2: usb-phy@7d004000 { - compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy"; - reg = <0x0 0x7d004000 0x0 0x4000>, - <0x0 0x7d000000 0x0 0x4000>; - phy_type = "utmi"; - clocks = <&tegra_car TEGRA210_CLK_USB2>, - <&tegra_car TEGRA210_CLK_PLL_U>, - <&tegra_car TEGRA210_CLK_USBD>; - clock-names = "reg", "pll_u", "utmi-pads"; - resets = <&tegra_car 58>, <&tegra_car 22>; - reset-names = "usb", "utmi-pads"; - nvidia,hssync-start-delay = <0>; - nvidia,idle-wait-delay = <17>; - nvidia,elastic-limit = <16>; - nvidia,term-range-adj = <6>; - nvidia,xcvr-setup = <9>; - nvidia,xcvr-lsfslew = <0>; - nvidia,xcvr-lsrslew = <3>; - nvidia,hssquelch-level = <2>; - nvidia,hsdiscon-level = <5>; - nvidia,xcvr-hsslew = <12>; - status = "disabled"; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0>; - clocks = <&tegra_car TEGRA210_CLK_CCLK_G>, - <&tegra_car TEGRA210_CLK_PLL_X>, - <&tegra_car TEGRA210_CLK_PLL_P_OUT4>, - <&dfll>; - clock-names = "cpu_g", "pll_x", "pll_p", "dfll"; - clock-latency = <300000>; - cpu-idle-states = <&CPU_SLEEP>; - next-level-cache = <&L2>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <1>; - cpu-idle-states = <&CPU_SLEEP>; - next-level-cache = <&L2>; - }; - - cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <2>; - cpu-idle-states = <&CPU_SLEEP>; - next-level-cache = <&L2>; - }; - - cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <3>; - cpu-idle-states = <&CPU_SLEEP>; - next-level-cache = <&L2>; - }; - - idle-states { - entry-method = "psci"; - - CPU_SLEEP: cpu-sleep { - compatible = "arm,idle-state"; - arm,psci-suspend-param = <0x40000007>; - entry-latency-us = <100>; - exit-latency-us = <30>; - min-residency-us = <1000>; - wakeup-latency-us = <130>; - idle-state-name = "cpu-sleep"; - status = "disabled"; - }; - }; - - L2: l2-cache { - compatible = "cache"; - }; - }; - - pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = , - , - , - ; - interrupt-affinity = <&{/cpus/cpu@0} &{/cpus/cpu@1} - &{/cpus/cpu@2} &{/cpus/cpu@3}>; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - interrupt-parent = <&gic>; - arm,no-tick-in-suspend; - }; - - soctherm: thermal-sensor@700e2000 { - compatible = "nvidia,tegra210-soctherm"; - reg = <0x0 0x700e2000 0x0 0x600 /* SOC_THERM reg_base */ - 0x0 0x60006000 0x0 0x400>; /* CAR reg_base */ - reg-names = "soctherm-reg", "car-reg"; - interrupts = , - ; - interrupt-names = "thermal", "edp"; - clocks = <&tegra_car TEGRA210_CLK_TSENSOR>, - <&tegra_car TEGRA210_CLK_SOC_THERM>; - clock-names = "tsensor", "soctherm"; - resets = <&tegra_car 78>; - reset-names = "soctherm"; - #thermal-sensor-cells = <1>; - - throttle-cfgs { - throttle_heavy: heavy { - nvidia,priority = <100>; - nvidia,cpu-throt-percent = <85>; - - #cooling-cells = <2>; - }; - }; - }; - - thermal-zones { - cpu { - polling-delay-passive = <1000>; - polling-delay = <0>; - - thermal-sensors = - <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>; - - trips { - cpu-shutdown-trip { - temperature = <102500>; - hysteresis = <0>; - type = "critical"; - }; - - cpu_throttle_trip: throttle-trip { - temperature = <98500>; - hysteresis = <1000>; - type = "hot"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu_throttle_trip>; - cooling-device = <&throttle_heavy 1 1>; - }; - }; - }; - - mem { - polling-delay-passive = <0>; - polling-delay = <0>; - - thermal-sensors = - <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>; - - trips { - mem-shutdown-trip { - temperature = <103000>; - hysteresis = <0>; - type = "critical"; - }; - }; - - cooling-maps { - /* - * There are currently no cooling maps, - * because there are no cooling devices. - */ - }; - }; - - gpu { - polling-delay-passive = <1000>; - polling-delay = <0>; - - thermal-sensors = - <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>; - - trips { - gpu-shutdown-trip { - temperature = <103000>; - hysteresis = <0>; - type = "critical"; - }; - - gpu_throttle_trip: throttle-trip { - temperature = <100000>; - hysteresis = <1000>; - type = "hot"; - }; - }; - - cooling-maps { - map0 { - trip = <&gpu_throttle_trip>; - cooling-device = <&throttle_heavy 1 1>; - }; - }; - }; - - pllx { - polling-delay-passive = <0>; - polling-delay = <0>; - - thermal-sensors = - <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>; - - trips { - pllx-shutdown-trip { - temperature = <103000>; - hysteresis = <0>; - type = "critical"; - }; - }; - - cooling-maps { - /* - * There are currently no cooling maps, - * because there are no cooling devices. - */ - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/qcom/apq8016-sbc-pmic-pins.dtsi b/sys/gnu/dts/arm64/qcom/apq8016-sbc-pmic-pins.dtsi deleted file mode 100644 index aff218c1b7b..00000000000 --- a/sys/gnu/dts/arm64/qcom/apq8016-sbc-pmic-pins.dtsi +++ /dev/null @@ -1,74 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include -#include - -&pm8916_gpios { - - usb_hub_reset_pm: usb_hub_reset_pm { - pinconf { - pins = "gpio3"; - function = PMIC_GPIO_FUNC_NORMAL; - input-disable; - output-high; - }; - }; - - usb_hub_reset_pm_device: usb_hub_reset_pm_device { - pinconf { - pins = "gpio3"; - function = PMIC_GPIO_FUNC_NORMAL; - output-low; - }; - }; - - usb_sw_sel_pm: usb_sw_sel_pm { - pinconf { - pins = "gpio4"; - function = PMIC_GPIO_FUNC_NORMAL; - power-source = ; - input-disable; - output-high; - }; - }; - - usb_sw_sel_pm_device: usb_sw_sel_pm_device { - pinconf { - pins = "gpio4"; - function = PMIC_GPIO_FUNC_NORMAL; - power-source = ; - input-disable; - output-low; - }; - }; - - pm8916_gpios_leds: pm8916_gpios_leds { - pinconf { - pins = "gpio1", "gpio2"; - function = PMIC_GPIO_FUNC_NORMAL; - output-low; - }; - }; -}; - -&pm8916_mpps { - - pinctrl-names = "default"; - pinctrl-0 = <&ls_exp_gpio_f>; - - ls_exp_gpio_f: pm8916_mpp4 { - pinconf { - pins = "mpp4"; - function = "digital"; - output-low; - power-source = ; // 1.8V - }; - }; - - pm8916_mpps_leds: pm8916_mpps_leds { - pinconf { - pins = "mpp2", "mpp3"; - function = "digital"; - output-low; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/qcom/apq8016-sbc-soc-pins.dtsi b/sys/gnu/dts/arm64/qcom/apq8016-sbc-soc-pins.dtsi deleted file mode 100644 index 21d0822f1ca..00000000000 --- a/sys/gnu/dts/arm64/qcom/apq8016-sbc-soc-pins.dtsi +++ /dev/null @@ -1,89 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -#include - -&msmgpio { - - msmgpio_leds: msmgpio_leds { - pinconf { - pins = "gpio21", "gpio120"; - function = "gpio"; - output-low; - }; - }; - - usb_id_default: usb-id-default { - pinmux { - function = "gpio"; - pins = "gpio121"; - }; - - pinconf { - pins = "gpio121"; - drive-strength = <8>; - input-enable; - bias-pull-up; - }; - }; - - adv7533_int_active: adv533_int_active { - pinmux { - function = "gpio"; - pins = "gpio31"; - }; - pinconf { - pins = "gpio31"; - drive-strength = <16>; - bias-disable; - }; - }; - - adv7533_int_suspend: adv7533_int_suspend { - pinmux { - function = "gpio"; - pins = "gpio31"; - }; - pinconf { - pins = "gpio31"; - drive-strength = <2>; - bias-disable; - }; - }; - - adv7533_switch_active: adv7533_switch_active { - pinmux { - function = "gpio"; - pins = "gpio32"; - }; - pinconf { - pins = "gpio32"; - drive-strength = <16>; - bias-disable; - }; - }; - - adv7533_switch_suspend: adv7533_switch_suspend { - pinmux { - function = "gpio"; - pins = "gpio32"; - }; - pinconf { - pins = "gpio32"; - drive-strength = <2>; - bias-disable; - }; - }; - - msm_key_volp_n_default: msm_key_volp_n_default { - pinmux { - function = "gpio"; - pins = "gpio107"; - }; - pinconf { - pins = "gpio107"; - drive-strength = <8>; - input-enable; - bias-pull-up; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/qcom/apq8016-sbc.dts b/sys/gnu/dts/arm64/qcom/apq8016-sbc.dts deleted file mode 100644 index 48bd1c2874d..00000000000 --- a/sys/gnu/dts/arm64/qcom/apq8016-sbc.dts +++ /dev/null @@ -1,13 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2015, The Linux Foundation. All rights reserved. - */ - -/dts-v1/; - -#include "apq8016-sbc.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. APQ 8016 SBC"; - compatible = "qcom,apq8016-sbc", "qcom,apq8016", "qcom,sbc"; -}; diff --git a/sys/gnu/dts/arm64/qcom/apq8016-sbc.dtsi b/sys/gnu/dts/arm64/qcom/apq8016-sbc.dtsi deleted file mode 100644 index 037e26b3f8d..00000000000 --- a/sys/gnu/dts/arm64/qcom/apq8016-sbc.dtsi +++ /dev/null @@ -1,683 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2015, The Linux Foundation. All rights reserved. - */ - -#include "msm8916.dtsi" -#include "pm8916.dtsi" -#include "apq8016-sbc-soc-pins.dtsi" -#include "apq8016-sbc-pmic-pins.dtsi" -#include -#include -#include - -/* - * GPIO name legend: proper name = the GPIO line is used as GPIO - * NC = not connected (pin out but not routed from the chip to - * anything the board) - * "[PER]" = pin is muxed for [peripheral] (not GPIO) - * LSEC = Low Speed External Connector - * HSEC = High Speed External Connector - * - * Line names are taken from the schematic "DragonBoard410c" - * dated monday, august 31, 2015. Page 5 in particular. - * - * For the lines routed to the external connectors the - * lines are named after the 96Boards CE Specification 1.0, - * Appendix "Expansion Connector Signal Description". - * - * When the 96Board naming of a line and the schematic name of - * the same line are in conflict, the 96Board specification - * takes precedence, which means that the external UART on the - * LSEC is named UART0 while the schematic and SoC names this - * UART3. This is only for the informational lines i.e. "[FOO]", - * the GPIO named lines "GPIO-A" thru "GPIO-L" are the only - * ones actually used for GPIO. - */ - -/ { - aliases { - serial0 = &blsp1_uart2; - serial1 = &blsp1_uart1; - usid0 = &pm8916_0; - i2c0 = &blsp_i2c2; - i2c1 = &blsp_i2c6; - i2c3 = &blsp_i2c4; - spi0 = &blsp_spi5; - spi1 = &blsp_spi3; - }; - - chosen { - stdout-path = "serial0"; - }; - - reserved-memory { - ramoops@bff00000{ - compatible = "ramoops"; - reg = <0x0 0xbff00000 0x0 0x100000>; - - record-size = <0x20000>; - console-size = <0x20000>; - ftrace-size = <0x20000>; - }; - }; - - soc { - pinctrl@1000000 { - gpio-line-names = - "[UART0_TX]", /* GPIO_0, LSEC pin 5 */ - "[UART0_RX]", /* GPIO_1, LSEC pin 7 */ - "[UART0_CTS_N]", /* GPIO_2, LSEC pin 3 */ - "[UART0_RTS_N]", /* GPIO_3, LSEC pin 9 */ - "[UART1_TX]", /* GPIO_4, LSEC pin 11 */ - "[UART1_RX]", /* GPIO_5, LSEC pin 13 */ - "[I2C0_SDA]", /* GPIO_8, LSEC pin 17 */ - "[I2C0_SCL]", /* GPIO_7, LSEC pin 15 */ - "[SPI1_DOUT]", /* SPI1_MOSI, HSEC pin 1 */ - "[SPI1_DIN]", /* SPI1_MISO, HSEC pin 11 */ - "[SPI1_CS]", /* SPI1_CS_N, HSEC pin 7 */ - "[SPI1_SCLK]", /* SPI1_CLK, HSEC pin 9 */ - "GPIO-B", /* LS_EXP_GPIO_B, LSEC pin 24 */ - "GPIO-C", /* LS_EXP_GPIO_C, LSEC pin 25 */ - "[I2C3_SDA]", /* HSEC pin 38 */ - "[I2C3_SCL]", /* HSEC pin 36 */ - "[SPI0_MOSI]", /* LSEC pin 14 */ - "[SPI0_MISO]", /* LSEC pin 10 */ - "[SPI0_CS_N]", /* LSEC pin 12 */ - "[SPI0_CLK]", /* LSEC pin 8 */ - "HDMI_HPD_N", /* GPIO 20 */ - "USR_LED_1_CTRL", - "[I2C1_SDA]", /* GPIO_22, LSEC pin 21 */ - "[I2C1_SCL]", /* GPIO_23, LSEC pin 19 */ - "GPIO-G", /* LS_EXP_GPIO_G, LSEC pin 29 */ - "GPIO-H", /* LS_EXP_GPIO_H, LSEC pin 30 */ - "[CSI0_MCLK]", /* HSEC pin 15 */ - "[CSI1_MCLK]", /* HSEC pin 17 */ - "GPIO-K", /* LS_EXP_GPIO_K, LSEC pin 33 */ - "[I2C2_SDA]", /* HSEC pin 34 */ - "[I2C2_SCL]", /* HSEC pin 32 */ - "DSI2HDMI_INT_N", - "DSI_SW_SEL_APQ", - "GPIO-L", /* LS_EXP_GPIO_L, LSEC pin 34 */ - "GPIO-J", /* LS_EXP_GPIO_J, LSEC pin 32 */ - "GPIO-I", /* LS_EXP_GPIO_I, LSEC pin 31 */ - "GPIO-A", /* LS_EXP_GPIO_A, LSEC pin 23 */ - "FORCED_USB_BOOT", - "SD_CARD_DET_N", - "[WCSS_BT_SSBI]", - "[WCSS_WLAN_DATA_2]", /* GPIO 40 */ - "[WCSS_WLAN_DATA_1]", - "[WCSS_WLAN_DATA_0]", - "[WCSS_WLAN_SET]", - "[WCSS_WLAN_CLK]", - "[WCSS_FM_SSBI]", - "[WCSS_FM_SDI]", - "[WCSS_BT_DAT_CTL]", - "[WCSS_BT_DAT_STB]", - "NC", - "NC", /* GPIO 50 */ - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", /* GPIO 60 */ - "NC", - "NC", - "[CDC_PDM0_CLK]", - "[CDC_PDM0_SYNC]", - "[CDC_PDM0_TX0]", - "[CDC_PDM0_RX0]", - "[CDC_PDM0_RX1]", - "[CDC_PDM0_RX2]", - "GPIO-D", /* LS_EXP_GPIO_D, LSEC pin 26 */ - "NC", /* GPIO 70 */ - "NC", - "NC", - "NC", - "NC", /* GPIO 74 */ - "NC", - "NC", - "NC", - "NC", - "NC", - "BOOT_CONFIG_0", /* GPIO 80 */ - "BOOT_CONFIG_1", - "BOOT_CONFIG_2", - "BOOT_CONFIG_3", - "NC", - "NC", - "BOOT_CONFIG_5", - "NC", - "NC", - "NC", - "NC", /* GPIO 90 */ - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", /* GPIO 100 */ - "NC", - "NC", - "NC", - "SSBI_GPS", - "NC", - "NC", - "KEY_VOLP_N", - "NC", - "NC", - "[LS_EXP_MI2S_WS]", /* GPIO 110 */ - "NC", - "NC", - "[LS_EXP_MI2S_SCK]", - "[LS_EXP_MI2S_DATA0]", - "GPIO-E", /* LS_EXP_GPIO_E, LSEC pin 27 */ - "NC", - "[DSI2HDMI_MI2S_WS]", - "[DSI2HDMI_MI2S_SCK]", - "[DSI2HDMI_MI2S_DATA0]", - "USR_LED_2_CTRL", /* GPIO 120 */ - "SB_HS_ID"; - }; - - dma@7884000 { - status = "okay"; - }; - - serial@78af000 { - label = "LS-UART0"; - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp1_uart1_default>; - pinctrl-1 = <&blsp1_uart1_sleep>; - }; - - serial@78b0000 { - label = "LS-UART1"; - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp1_uart2_default>; - pinctrl-1 = <&blsp1_uart2_sleep>; - }; - - i2c@78b6000 { - /* On Low speed expansion */ - label = "LS-I2C0"; - status = "okay"; - }; - - i2c@78b8000 { - /* On High speed expansion */ - label = "HS-I2C2"; - status = "okay"; - - adv_bridge: bridge@39 { - status = "okay"; - - compatible = "adi,adv7533"; - reg = <0x39>; - - interrupt-parent = <&msmgpio>; - interrupts = <31 2>; - - adi,dsi-lanes = <4>; - clocks = <&rpmcc RPM_SMD_BB_CLK2>; - clock-names = "cec"; - - pd-gpios = <&msmgpio 32 0>; - - avdd-supply = <&pm8916_l6>; - v1p2-supply = <&pm8916_l6>; - v3p3-supply = <&pm8916_l17>; - - pinctrl-names = "default","sleep"; - pinctrl-0 = <&adv7533_int_active &adv7533_switch_active>; - pinctrl-1 = <&adv7533_int_suspend &adv7533_switch_suspend>; - #sound-dai-cells = <1>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7533_in: endpoint { - remote-endpoint = <&dsi0_out>; - }; - }; - - port@1 { - reg = <1>; - adv7533_out: endpoint { - remote-endpoint = <&hdmi_con>; - }; - }; - }; - }; - }; - - i2c@78ba000 { - /* On Low speed expansion */ - label = "LS-I2C1"; - status = "okay"; - }; - - spi@78b7000 { - /* On High speed expansion */ - label = "HS-SPI1"; - status = "okay"; - }; - - spi@78b9000 { - /* On Low speed expansion */ - label = "LS-SPI0"; - status = "okay"; - }; - - leds { - pinctrl-names = "default"; - pinctrl-0 = <&msmgpio_leds>, - <&pm8916_gpios_leds>, - <&pm8916_mpps_leds>; - - compatible = "gpio-leds"; - - led@1 { - label = "apq8016-sbc:green:user1"; - gpios = <&msmgpio 21 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - - led@2 { - label = "apq8016-sbc:green:user2"; - gpios = <&msmgpio 120 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc0"; - default-state = "off"; - }; - - led@3 { - label = "apq8016-sbc:green:user3"; - gpios = <&pm8916_gpios 1 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc1"; - default-state = "off"; - }; - - led@4 { - label = "apq8016-sbc:green:user4"; - gpios = <&pm8916_gpios 2 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "none"; - panic-indicator; - default-state = "off"; - }; - - led@5 { - label = "apq8016-sbc:yellow:wlan"; - gpios = <&pm8916_mpps 2 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "phy0tx"; - default-state = "off"; - }; - - led@6 { - label = "apq8016-sbc:blue:bt"; - gpios = <&pm8916_mpps 3 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "bluetooth-power"; - default-state = "off"; - }; - }; - - sdhci@7824000 { - vmmc-supply = <&pm8916_l8>; - vqmmc-supply = <&pm8916_l5>; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>; - pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>; - status = "okay"; - }; - - sdhci@7864000 { - vmmc-supply = <&pm8916_l11>; - vqmmc-supply = <&pm8916_l12>; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; - pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; - - cd-gpios = <&msmgpio 38 0x1>; - status = "okay"; - }; - - usb@78d9000 { - extcon = <&usb_id>, <&usb_id>; - status = "okay"; - adp-disable; - hnp-disable; - srp-disable; - dr_mode = "otg"; - pinctrl-names = "default", "device"; - pinctrl-0 = <&usb_sw_sel_pm &usb_hub_reset_pm>; - pinctrl-1 = <&usb_sw_sel_pm_device &usb_hub_reset_pm_device>; - ulpi { - phy { - v1p8-supply = <&pm8916_l7>; - v3p3-supply = <&pm8916_l13>; - extcon = <&usb_id>; - }; - }; - }; - - lpass@7708000 { - status = "okay"; - }; - - mdss@1a00000 { - status = "okay"; - - mdp@1a01000 { - status = "okay"; - }; - - dsi@1a98000 { - status = "okay"; - - vdda-supply = <&pm8916_l2>; - vddio-supply = <&pm8916_l6>; - - ports { - port@1 { - endpoint { - remote-endpoint = <&adv7533_in>; - data-lanes = <0 1 2 3>; - }; - }; - }; - }; - - dsi-phy@1a98300 { - status = "okay"; - - vddio-supply = <&pm8916_l6>; - }; - }; - - lpass_codec: codec{ - status = "okay"; - }; - - /* - Internal Codec - playback - Primary MI2S - capture - Ter MI2S - - External Primary: - playback - secondary MI2S - capture - Quat MI2S - - External Secondary: - playback - Quat MI2S - capture - Quat MI2S - - */ - - sound: sound { - compatible = "qcom,apq8016-sbc-sndcard"; - reg = <0x07702000 0x4>, <0x07702004 0x4>; - reg-names = "mic-iomux", "spkr-iomux"; - - status = "okay"; - pinctrl-0 = <&cdc_pdm_lines_act &ext_sec_tlmm_lines_act &ext_mclk_tlmm_lines_act>; - pinctrl-1 = <&cdc_pdm_lines_sus &ext_sec_tlmm_lines_sus &ext_mclk_tlmm_lines_sus>; - pinctrl-names = "default", "sleep"; - qcom,model = "DB410c"; - qcom,audio-routing = - "AMIC2", "MIC BIAS Internal2", - "AMIC3", "MIC BIAS External1"; - external-dai-link@0 { - link-name = "ADV7533"; - cpu { /* QUAT */ - sound-dai = <&lpass MI2S_QUATERNARY>; - }; - codec { - sound-dai = <&adv_bridge 0>; - }; - }; - - internal-codec-playback-dai-link@0 { /* I2S - Internal codec */ - link-name = "WCD"; - cpu { /* PRIMARY */ - sound-dai = <&lpass MI2S_PRIMARY>; - }; - codec { - sound-dai = <&lpass_codec 0>, <&wcd_codec 0>; - }; - }; - - internal-codec-capture-dai-link@0 { /* I2S - Internal codec */ - link-name = "WCD-Capture"; - cpu { /* PRIMARY */ - sound-dai = <&lpass MI2S_TERTIARY>; - }; - codec { - sound-dai = <&lpass_codec 1>, <&wcd_codec 1>; - }; - }; - }; - - spmi@200f000 { - pm8916@0 { - gpios@c000 { - gpio-line-names = - "USR_LED_3_CTRL", - "USR_LED_4_CTRL", - "USB_HUB_RESET_N_PM", - "USB_SW_SEL_PM"; - }; - mpps@a000 { - gpio-line-names = - "VDD_PX_BIAS", - "WLAN_LED_CTRL", - "BT_LED_CTRL", - "GPIO-F"; /* LS_EXP_GPIO_F, LSEC pin 28 */ - }; - }; - }; - - wcnss@a21b000 { - status = "okay"; - }; - }; - - usb2513 { - compatible = "smsc,usb3503"; - reset-gpios = <&pm8916_gpios 3 GPIO_ACTIVE_LOW>; - initial-mode = <1>; - }; - - usb_id: usb-id { - compatible = "linux,extcon-usb-gpio"; - id-gpio = <&msmgpio 121 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&usb_id_default>; - }; - - hdmi-out { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con: endpoint { - remote-endpoint = <&adv7533_out>; - }; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - autorepeat; - - pinctrl-names = "default"; - pinctrl-0 = <&msm_key_volp_n_default>; - - button@0 { - label = "Volume Up"; - linux,code = ; - gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&spmi_bus { - pm8916_0: pm8916@0 { - pon@800 { - resin { - compatible = "qcom,pm8941-resin"; - interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>; - debounce = <15625>; - bias-pull-up; - linux,code = ; - }; - }; - }; -}; - -&wcd_codec { - status = "okay"; - clocks = <&gcc GCC_CODEC_DIGCODEC_CLK>; - clock-names = "mclk"; - qcom,mbhc-vthreshold-low = <75 150 237 450 500>; - qcom,mbhc-vthreshold-high = <75 150 237 450 500>; -}; - -&smd_rpm_regulators { - vdd_l1_l2_l3-supply = <&pm8916_s3>; - vdd_l5-supply = <&pm8916_s3>; - vdd_l4_l5_l6-supply = <&pm8916_s4>; - vdd_l7-supply = <&pm8916_s4>; - - s1 { - regulator-min-microvolt = <375000>; - regulator-max-microvolt = <1562000>; - }; - - s3 { - regulator-min-microvolt = <375000>; - regulator-max-microvolt = <1562000>; - }; - - s4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-always-on; - regulator-boot-on; - }; - - l1 { - regulator-min-microvolt = <375000>; - regulator-max-microvolt = <1525000>; - }; - - l2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - l3 { - regulator-min-microvolt = <375000>; - regulator-max-microvolt = <1525000>; - }; - - l4 { - regulator-min-microvolt = <1750000>; - regulator-max-microvolt = <3337000>; - }; - - l5 { - regulator-min-microvolt = <1750000>; - regulator-max-microvolt = <3337000>; - }; - - l6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l7 { - regulator-min-microvolt = <1750000>; - regulator-max-microvolt = <3337000>; - }; - - l8 { - regulator-min-microvolt = <1750000>; - regulator-max-microvolt = <3337000>; - }; - - l9 { - regulator-min-microvolt = <1750000>; - regulator-max-microvolt = <3337000>; - }; - - l10 { - regulator-min-microvolt = <1750000>; - regulator-max-microvolt = <3337000>; - }; - - l11 { - regulator-min-microvolt = <1750000>; - regulator-max-microvolt = <3337000>; - regulator-allow-set-load; - regulator-system-load = <200000>; - }; - - l12 { - regulator-min-microvolt = <1750000>; - regulator-max-microvolt = <3337000>; - }; - - l13 { - regulator-min-microvolt = <1750000>; - regulator-max-microvolt = <3337000>; - }; - - l14 { - regulator-min-microvolt = <1750000>; - regulator-max-microvolt = <3337000>; - }; - - /** - * 1.8v required on LS expansion - * for mezzanine boards - */ - l15 { - regulator-min-microvolt = <1750000>; - regulator-max-microvolt = <3337000>; - regulator-always-on; - }; - - l16 { - regulator-min-microvolt = <1750000>; - regulator-max-microvolt = <3337000>; - }; - - l17 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - l18 { - regulator-min-microvolt = <1750000>; - regulator-max-microvolt = <3337000>; - }; -}; diff --git a/sys/gnu/dts/arm64/qcom/apq8096-db820c.dts b/sys/gnu/dts/arm64/qcom/apq8096-db820c.dts deleted file mode 100644 index 757afa27424..00000000000 --- a/sys/gnu/dts/arm64/qcom/apq8096-db820c.dts +++ /dev/null @@ -1,13 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2014-2016, The Linux Foundation. All rights reserved. - */ - -/dts-v1/; - -#include "apq8096-db820c.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. DB820c"; - compatible = "arrow,apq8096-db820c", "qcom,apq8096-sbc", "qcom,apq8096"; -}; diff --git a/sys/gnu/dts/arm64/qcom/apq8096-db820c.dtsi b/sys/gnu/dts/arm64/qcom/apq8096-db820c.dtsi deleted file mode 100644 index fff6115f267..00000000000 --- a/sys/gnu/dts/arm64/qcom/apq8096-db820c.dtsi +++ /dev/null @@ -1,1062 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2014-2016, The Linux Foundation. All rights reserved. - */ - -#include "msm8996.dtsi" -#include "pm8994.dtsi" -#include "pmi8994.dtsi" -#include -#include -#include -#include -#include - -/* - * GPIO name legend: proper name = the GPIO line is used as GPIO - * NC = not connected (pin out but not routed from the chip to - * anything the board) - * "[PER]" = pin is muxed for [peripheral] (not GPIO) - * LSEC = Low Speed External Connector - * P HSEC = Primary High Speed External Connector - * S HSEC = Secondary High Speed External Connector - * J14 = Camera Connector - * TP = Test Points - * - * Line names are taken from the schematic "DragonBoard 820c", - * drawing no: LM25-P2751-1 - * - * For the lines routed to the external connectors the - * lines are named after the 96Boards CE Specification 1.0, - * Appendix "Expansion Connector Signal Description". - * - * When the 96Board naming of a line and the schematic name of - * the same line are in conflict, the 96Board specification - * takes precedence, which means that the external UART on the - * LSEC is named UART0 while the schematic and SoC names this - * UART3. This is only for the informational lines i.e. "[FOO]", - * the GPIO named lines "GPIO-A" thru "GPIO-L" are the only - * ones actually used for GPIO. - */ - -/ { - aliases { - serial0 = &blsp2_uart1; - serial1 = &blsp2_uart2; - serial2 = &blsp1_uart1; - i2c0 = &blsp1_i2c2; - i2c1 = &blsp2_i2c1; - i2c2 = &blsp2_i2c0; - spi0 = &blsp1_spi0; - spi1 = &blsp2_spi5; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - clocks { - compatible = "simple-bus"; - divclk4: divclk4 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "divclk4"; - - pinctrl-names = "default"; - pinctrl-0 = <&divclk4_pin_a>; - }; - - div1_mclk: divclk1 { - compatible = "gpio-gate-clock"; - pinctrl-0 = <&audio_mclk>; - pinctrl-names = "default"; - clocks = <&rpmcc RPM_SMD_DIV_CLK1>; - #clock-cells = <0>; - enable-gpios = <&pm8994_gpios 15 0>; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - autorepeat; - - pinctrl-names = "default"; - pinctrl-0 = <&volume_up_gpio>; - - button@0 { - label = "Volume Up"; - linux,code = ; - gpios = <&pm8994_gpios 2 GPIO_ACTIVE_LOW>; - }; - }; - - usb2_id: usb2-id { - compatible = "linux,extcon-usb-gpio"; - id-gpio = <&pmi8994_gpios 6 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&usb2_vbus_det_gpio>; - }; - - usb3_id: usb3-id { - compatible = "linux,extcon-usb-gpio"; - id-gpio = <&pm8994_gpios 22 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&usb3_vbus_det_gpio>; - }; - - vph_pwr: vph-pwr-regulator { - compatible = "regulator-fixed"; - regulator-name = "vph_pwr"; - regulator-always-on; - regulator-boot-on; - - regulator-min-microvolt = <3700000>; - regulator-max-microvolt = <3700000>; - }; - - vreg_s8a_l3a_input: vreg-s8a-l3a-input { - compatible = "regulator-fixed"; - regulator-name = "vreg_s8a_l3a_input"; - regulator-always-on; - regulator-boot-on; - - regulator-min-microvolt = <0>; - regulator-max-microvolt = <0>; - }; - - wlan_en: wlan-en-1-8v { - pinctrl-names = "default"; - pinctrl-0 = <&wlan_en_gpios>; - compatible = "regulator-fixed"; - regulator-name = "wlan-en-regulator"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - gpio = <&pm8994_gpios 8 0>; - - /* WLAN card specific delay */ - startup-delay-us = <70000>; - enable-active-high; - }; -}; - -&blsp1_i2c2 { - /* On Low speed expansion */ - label = "LS-I2C0"; - status = "okay"; -}; - -&blsp1_spi0 { - /* On Low speed expansion */ - label = "LS-SPI0"; - status = "okay"; -}; - -&blsp1_uart1 { - label = "BT-UART"; - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp1_uart1_default>; - pinctrl-1 = <&blsp1_uart1_sleep>; - - bluetooth { - compatible = "qcom,qca6174-bt"; - - /* bt_disable_n gpio */ - enable-gpios = <&pm8994_gpios 19 GPIO_ACTIVE_HIGH>; - - clocks = <&divclk4>; - }; -}; - -&blsp2_i2c0 { - /* On High speed expansion */ - label = "HS-I2C2"; - status = "okay"; -}; - -&blsp2_i2c1 { - /* On Low speed expansion */ - label = "LS-I2C1"; - status = "okay"; -}; - -&blsp2_spi5 { - /* On High speed expansion */ - label = "HS-SPI1"; - status = "okay"; -}; - -&blsp2_uart1 { - label = "LS-UART1"; - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp2_uart1_2pins_default>; - pinctrl-1 = <&blsp2_uart1_2pins_sleep>; -}; - -&blsp2_uart2 { - label = "LS-UART0"; - status = "disabled"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp2_uart2_4pins_default>; - pinctrl-1 = <&blsp2_uart2_4pins_sleep>; -}; - -&camss { - vdda-supply = <&vreg_l2a_1p25>; -}; - -&hdmi { - status = "okay"; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&hdmi_hpd_active &hdmi_ddc_active>; - pinctrl-1 = <&hdmi_hpd_suspend &hdmi_ddc_suspend>; - - core-vdda-supply = <&vreg_l12a_1p8>; - core-vcc-supply = <&vreg_s4a_1p8>; -}; - -&hdmi_phy { - status = "okay"; - - vddio-supply = <&vreg_l12a_1p8>; - vcca-supply = <&vreg_l28a_0p925>; - #phy-cells = <0>; -}; - -&hsusb_phy1 { - status = "okay"; - - vdda-pll-supply = <&vreg_l12a_1p8>; - vdda-phy-dpdm-supply = <&vreg_l24a_3p075>; -}; - -&hsusb_phy2 { - status = "okay"; - - vdda-pll-supply = <&vreg_l12a_1p8>; - vdda-phy-dpdm-supply = <&vreg_l24a_3p075>; -}; - -&mdp { - status = "okay"; -}; - -&mdss { - status = "okay"; -}; - -&msmgpio { - gpio-line-names = - "[SPI0_DOUT]", /* GPIO_0, BLSP1_SPI_MOSI, LSEC pin 14 */ - "[SPI0_DIN]", /* GPIO_1, BLSP1_SPI_MISO, LSEC pin 10 */ - "[SPI0_CS]", /* GPIO_2, BLSP1_SPI_CS_N, LSEC pin 12 */ - "[SPI0_SCLK]", /* GPIO_3, BLSP1_SPI_CLK, LSEC pin 8 */ - "[UART1_TxD]", /* GPIO_4, BLSP8_UART_TX, LSEC pin 11 */ - "[UART1_RxD]", /* GPIO_5, BLSP8_UART_RX, LSEC pin 13 */ - "[I2C1_SDA]", /* GPIO_6, BLSP8_I2C_SDA, LSEC pin 21 */ - "[I2C1_SCL]", /* GPIO_7, BLSP8_I2C_SCL, LSEC pin 19 */ - "GPIO-H", /* GPIO_8, LCD0_RESET_N, LSEC pin 30 */ - "TP93", /* GPIO_9 */ - "GPIO-G", /* GPIO_10, MDP_VSYNC_P, LSEC pin 29 */ - "[MDP_VSYNC_S]", /* GPIO_11, S HSEC pin 55 */ - "NC", /* GPIO_12 */ - "[CSI0_MCLK]", /* GPIO_13, CAM_MCLK0, P HSEC pin 15 */ - "[CAM_MCLK1]", /* GPIO_14, J14 pin 11 */ - "[CSI1_MCLK]", /* GPIO_15, CAM_MCLK2, P HSEC pin 17 */ - "TP99", /* GPIO_16 */ - "[I2C2_SDA]", /* GPIO_17, CCI_I2C_SDA0, P HSEC pin 34 */ - "[I2C2_SCL]", /* GPIO_18, CCI_I2C_SCL0, P HSEC pin 32 */ - "[CCI_I2C_SDA1]", /* GPIO_19, S HSEC pin 38 */ - "[CCI_I2C_SCL1]", /* GPIO_20, S HSEC pin 36 */ - "FLASH_STROBE_EN", /* GPIO_21, S HSEC pin 5 */ - "FLASH_STROBE_TRIG", /* GPIO_22, S HSEC pin 1 */ - "GPIO-K", /* GPIO_23, CAM2_RST_N, LSEC pin 33 */ - "GPIO-D", /* GPIO_24, LSEC pin 26 */ - "GPIO-I", /* GPIO_25, CAM0_RST_N, LSEC pin 31 */ - "GPIO-J", /* GPIO_26, CAM0_STANDBY_N, LSEC pin 32 */ - "BLSP6_I2C_SDA", /* GPIO_27 */ - "BLSP6_I2C_SCL", /* GPIO_28 */ - "GPIO-B", /* GPIO_29, TS0_RESET_N, LSEC pin 24 */ - "GPIO30", /* GPIO_30, S HSEC pin 4 */ - "HDMI_CEC", /* GPIO_31 */ - "HDMI_DDC_CLOCK", /* GPIO_32 */ - "HDMI_DDC_DATA", /* GPIO_33 */ - "HDMI_HOT_PLUG_DETECT", /* GPIO_34 */ - "PCIE0_RST_N", /* GPIO_35 */ - "PCIE0_CLKREQ_N", /* GPIO_36 */ - "PCIE0_WAKE", /* GPIO_37 */ - "SD_CARD_DET_N", /* GPIO_38 */ - "TSIF1_SYNC", /* GPIO_39, S HSEC pin 48 */ - "W_DISABLE_N", /* GPIO_40 */ - "[BLSP9_UART_TX]", /* GPIO_41 */ - "[BLSP9_UART_RX]", /* GPIO_42 */ - "[BLSP2_UART_CTS_N]", /* GPIO_43 */ - "[BLSP2_UART_RFR_N]", /* GPIO_44 */ - "[BLSP3_UART_TX]", /* GPIO_45 */ - "[BLSP3_UART_RX]", /* GPIO_46 */ - "[I2C0_SDA]", /* GPIO_47, LS_I2C0_SDA, LSEC pin 17 */ - "[I2C0_SCL]", /* GPIO_48, LS_I2C0_SCL, LSEC pin 15 */ - "[UART0_TxD]", /* GPIO_49, BLSP9_UART_TX, LSEC pin 5 */ - "[UART0_RxD]", /* GPIO_50, BLSP9_UART_RX, LSEC pin 7 */ - "[UART0_CTS]", /* GPIO_51, BLSP9_UART_CTS_N, LSEC pin 3 */ - "[UART0_RTS]", /* GPIO_52, BLSP9_UART_RFR_N, LSEC pin 9 */ - "[CODEC_INT1_N]", /* GPIO_53 */ - "[CODEC_INT2_N]", /* GPIO_54 */ - "[BLSP7_I2C_SDA]", /* GPIO_55 */ - "[BLSP7_I2C_SCL]", /* GPIO_56 */ - "MI2S_MCLK", /* GPIO_57, S HSEC pin 3 */ - "[PCM_CLK]", /* GPIO_58, QUA_MI2S_SCK, LSEC pin 18 */ - "[PCM_FS]", /* GPIO_59, QUA_MI2S_WS, LSEC pin 16 */ - "[PCM_DO]", /* GPIO_60, QUA_MI2S_DATA0, LSEC pin 20 */ - "[PCM_DI]", /* GPIO_61, QUA_MI2S_DATA1, LSEC pin 22 */ - "GPIO-E", /* GPIO_62, LSEC pin 27 */ - "TP87", /* GPIO_63 */ - "[CODEC_RST_N]", /* GPIO_64 */ - "[PCM1_CLK]", /* GPIO_65 */ - "[PCM1_SYNC]", /* GPIO_66 */ - "[PCM1_DIN]", /* GPIO_67 */ - "[PCM1_DOUT]", /* GPIO_68 */ - "AUDIO_REF_CLK", /* GPIO_69 */ - "SLIMBUS_CLK", /* GPIO_70 */ - "SLIMBUS_DATA0", /* GPIO_71 */ - "SLIMBUS_DATA1", /* GPIO_72 */ - "NC", /* GPIO_73 */ - "NC", /* GPIO_74 */ - "NC", /* GPIO_75 */ - "NC", /* GPIO_76 */ - "TP94", /* GPIO_77 */ - "NC", /* GPIO_78 */ - "TP95", /* GPIO_79 */ - "GPIO-A", /* GPIO_80, MEMS_RESET_N, LSEC pin 23 */ - "TP88", /* GPIO_81 */ - "TP89", /* GPIO_82 */ - "TP90", /* GPIO_83 */ - "TP91", /* GPIO_84 */ - "[SD_DAT0]", /* GPIO_85, BLSP12_SPI_MOSI, P HSEC pin 1 */ - "[SD_CMD]", /* GPIO_86, BLSP12_SPI_MISO, P HSEC pin 11 */ - "[SD_DAT3]", /* GPIO_87, BLSP12_SPI_CS_N, P HSEC pin 7 */ - "[SD_SCLK]", /* GPIO_88, BLSP12_SPI_CLK, P HSEC pin 9 */ - "TSIF1_CLK", /* GPIO_89, S HSEC pin 42 */ - "TSIF1_EN", /* GPIO_90, S HSEC pin 46 */ - "TSIF1_DATA", /* GPIO_91, S HSEC pin 44 */ - "NC", /* GPIO_92 */ - "TSIF2_CLK", /* GPIO_93, S HSEC pin 52 */ - "TSIF2_EN", /* GPIO_94, S HSEC pin 56 */ - "TSIF2_DATA", /* GPIO_95, S HSEC pin 54 */ - "TSIF2_SYNC", /* GPIO_96, S HSEC pin 58 */ - "NC", /* GPIO_97 */ - "CAM1_STANDBY_N", /* GPIO_98 */ - "NC", /* GPIO_99 */ - "NC", /* GPIO_100 */ - "[LCD1_RESET_N]", /* GPIO_101, S HSEC pin 51 */ - "BOOT_CONFIG1", /* GPIO_102 */ - "USB_HUB_RESET", /* GPIO_103 */ - "CAM1_RST_N", /* GPIO_104 */ - "NC", /* GPIO_105 */ - "NC", /* GPIO_106 */ - "NC", /* GPIO_107 */ - "NC", /* GPIO_108 */ - "NC", /* GPIO_109 */ - "NC", /* GPIO_110 */ - "NC", /* GPIO_111 */ - "NC", /* GPIO_112 */ - "PMI8994_BUA", /* GPIO_113 */ - "PCIE2_RST_N", /* GPIO_114 */ - "PCIE2_CLKREQ_N", /* GPIO_115 */ - "PCIE2_WAKE", /* GPIO_116 */ - "SSC_IRQ_0", /* GPIO_117 */ - "SSC_IRQ_1", /* GPIO_118 */ - "SSC_IRQ_2", /* GPIO_119 */ - "NC", /* GPIO_120 */ - "GPIO121", /* GPIO_121, S HSEC pin 2 */ - "NC", /* GPIO_122 */ - "SSC_IRQ_6", /* GPIO_123 */ - "SSC_IRQ_7", /* GPIO_124 */ - "GPIO-C", /* GPIO_125, TS_INT0, LSEC pin 25 */ - "BOOT_CONFIG5", /* GPIO_126 */ - "NC", /* GPIO_127 */ - "NC", /* GPIO_128 */ - "BOOT_CONFIG7", /* GPIO_129 */ - "PCIE1_RST_N", /* GPIO_130 */ - "PCIE1_CLKREQ_N", /* GPIO_131 */ - "PCIE1_WAKE", /* GPIO_132 */ - "GPIO-L", /* GPIO_133, CAM2_STANDBY_N, LSEC pin 34 */ - "NC", /* GPIO_134 */ - "NC", /* GPIO_135 */ - "BOOT_CONFIG8", /* GPIO_136 */ - "NC", /* GPIO_137 */ - "NC", /* GPIO_138 */ - "GPS_SSBI2", /* GPIO_139 */ - "GPS_SSBI1", /* GPIO_140 */ - "NC", /* GPIO_141 */ - "NC", /* GPIO_142 */ - "NC", /* GPIO_143 */ - "BOOT_CONFIG6", /* GPIO_144 */ - "NC", /* GPIO_145 */ - "NC", /* GPIO_146 */ - "NC", /* GPIO_147 */ - "NC", /* GPIO_148 */ - "NC"; /* GPIO_149 */ - - sdc2_cd_on: sdc2_cd_on { - mux { - pins = "gpio38"; - function = "gpio"; - }; - - config { - pins = "gpio38"; - bias-pull-up; /* pull up */ - drive-strength = <16>; /* 16 MA */ - }; - }; - - sdc2_cd_off: sdc2_cd_off { - mux { - pins = "gpio38"; - function = "gpio"; - }; - - config { - pins = "gpio38"; - bias-pull-up; /* pull up */ - drive-strength = <2>; /* 2 MA */ - }; - }; - - blsp1_uart1_default: blsp1_uart1_default { - mux { - pins = "gpio41", "gpio42", "gpio43", "gpio44"; - function = "blsp_uart2"; - }; - - config { - pins = "gpio41", "gpio42", "gpio43", "gpio44"; - drive-strength = <16>; - bias-disable; - }; - }; - - blsp1_uart1_sleep: blsp1_uart1_sleep { - mux { - pins = "gpio41", "gpio42", "gpio43", "gpio44"; - function = "gpio"; - }; - - config { - pins = "gpio41", "gpio42", "gpio43", "gpio44"; - drive-strength = <2>; - bias-disable; - }; - }; - - hdmi_hpd_active: hdmi_hpd_active { - mux { - pins = "gpio34"; - function = "hdmi_hot"; - }; - - config { - pins = "gpio34"; - bias-pull-down; - drive-strength = <16>; - }; - }; - - hdmi_hpd_suspend: hdmi_hpd_suspend { - mux { - pins = "gpio34"; - function = "hdmi_hot"; - }; - - config { - pins = "gpio34"; - bias-pull-down; - drive-strength = <2>; - }; - }; - - hdmi_ddc_active: hdmi_ddc_active { - mux { - pins = "gpio32", "gpio33"; - function = "hdmi_ddc"; - }; - - config { - pins = "gpio32", "gpio33"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - hdmi_ddc_suspend: hdmi_ddc_suspend { - mux { - pins = "gpio32", "gpio33"; - function = "hdmi_ddc"; - }; - - config { - pins = "gpio32", "gpio33"; - drive-strength = <2>; - bias-pull-down; - }; - }; -}; - -&pcie0 { - status = "okay"; - perst-gpio = <&msmgpio 35 GPIO_ACTIVE_LOW>; - vddpe-3v3-supply = <&wlan_en>; - vdda-supply = <&vreg_l28a_0p925>; -}; - -&pcie1 { - status = "okay"; - perst-gpio = <&msmgpio 130 GPIO_ACTIVE_LOW>; - vdda-supply = <&vreg_l28a_0p925>; -}; - -&pcie2 { - status = "okay"; - perst-gpio = <&msmgpio 114 GPIO_ACTIVE_LOW>; - vdda-supply = <&vreg_l28a_0p925>; -}; - -&pcie_phy { - status = "okay"; - - vdda-phy-supply = <&vreg_l28a_0p925>; - vdda-pll-supply = <&vreg_l12a_1p8>; -}; - -&pm8994_gpios { - gpio-line-names = - "NC", - "KEY_VOLP_N", - "NC", - "BL1_PWM", - "GPIO-F", /* BL0_PWM, LSEC pin 28 */ - "BL1_EN", - "NC", - "WLAN_EN", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "DIVCLK1", - "DIVCLK2", - "DIVCLK3", - "DIVCLK4", - "BT_EN", - "PMIC_SLB", - "PMIC_BUA", - "USB_VBUS_DET"; - - pinctrl-names = "default"; - pinctrl-0 = <&ls_exp_gpio_f &bt_en_gpios>; - - ls_exp_gpio_f: pm8994_gpio5 { - pinconf { - pins = "gpio5"; - output-low; - power-source = <2>; // PM8994_GPIO_S4, 1.8V - }; - }; - - bt_en_gpios: bt_en_gpios { - pinconf { - pins = "gpio19"; - function = PMIC_GPIO_FUNC_NORMAL; - output-low; - power-source = ; // 1.8V - qcom,drive-strength = ; - bias-pull-down; - }; - }; - - wlan_en_gpios: wlan_en_gpios { - pinconf { - pins = "gpio8"; - function = PMIC_GPIO_FUNC_NORMAL; - output-low; - power-source = ; // 1.8V - qcom,drive-strength = ; - bias-pull-down; - }; - }; - - audio_mclk: clk_div1 { - pinconf { - pins = "gpio15"; - function = "func1"; - power-source = ; // 1.8V - }; - }; - - volume_up_gpio: pm8996_gpio2 { - pinconf { - pins = "gpio2"; - function = "normal"; - input-enable; - drive-push-pull; - bias-pull-up; - qcom,drive-strength = ; - power-source = ; // 1.8V - }; - }; - - divclk4_pin_a: divclk4 { - pinconf { - pins = "gpio18"; - function = PMIC_GPIO_FUNC_FUNC2; - - bias-disable; - power-source = ; - }; - }; - - usb3_vbus_det_gpio: pm8996_gpio22 { - pinconf { - pins = "gpio22"; - function = PMIC_GPIO_FUNC_NORMAL; - input-enable; - bias-pull-down; - qcom,drive-strength = ; - power-source = ; // 1.8V - }; - }; -}; - -&pm8994_mpps { - gpio-line-names = - "VDDPX_BIAS", - "WIFI_LED", - "NC", - "BT_LED", - "PM_MPP05", - "PM_MPP06", - "PM_MPP07", - "NC"; -}; - -&pm8994_spmi_regulators { - qcom,saw-reg = <&saw3>; - s9 { - qcom,saw-slave; - }; - s10 { - qcom,saw-slave; - }; - s11 { - qcom,saw-leader; - regulator-always-on; - regulator-min-microvolt = <1230000>; - regulator-max-microvolt = <1230000>; - }; -}; - -&pmi8994_gpios { - gpio-line-names = - "NC", - "SPKR_AMP_EN1", - "SPKR_AMP_EN2", - "TP61", - "NC", - "USB2_VBUS_DET", - "NC", - "NC", - "NC", - "NC"; - - usb2_vbus_det_gpio: pmi8996_gpio6 { - pinconf { - pins = "gpio6"; - function = PMIC_GPIO_FUNC_NORMAL; - input-enable; - bias-pull-down; - qcom,drive-strength = ; - power-source = ; // 1.8V - }; - }; -}; - -&rpm_requests { - pm8994-regulators { - compatible = "qcom,rpm-pm8994-regulators"; - - vdd_s1-supply = <&vph_pwr>; - vdd_s2-supply = <&vph_pwr>; - vdd_s3-supply = <&vph_pwr>; - vdd_s4-supply = <&vph_pwr>; - vdd_s5-supply = <&vph_pwr>; - vdd_s6-supply = <&vph_pwr>; - vdd_s7-supply = <&vph_pwr>; - vdd_s8-supply = <&vph_pwr>; - vdd_s9-supply = <&vph_pwr>; - vdd_s10-supply = <&vph_pwr>; - vdd_s11-supply = <&vph_pwr>; - vdd_s12-supply = <&vph_pwr>; - vdd_l2_l26_l28-supply = <&vreg_s3a_1p3>; - vdd_l3_l11-supply = <&vreg_s8a_l3a_input>; - vdd_l4_l27_l31-supply = <&vreg_s3a_1p3>; - vdd_l5_l7-supply = <&vreg_s5a_2p15>; - vdd_l6_l12_l32-supply = <&vreg_s5a_2p15>; - vdd_l8_l16_l30-supply = <&vph_pwr>; - vdd_l14_l15-supply = <&vreg_s5a_2p15>; - vdd_l25-supply = <&vreg_s3a_1p3>; - vdd_lvs1_2-supply = <&vreg_s4a_1p8>; - - vreg_s3a_1p3: s3 { - regulator-name = "vreg_s3a_1p3"; - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - }; - - /** - * 1.8v required on LS expansion - * for mezzanine boards - */ - vreg_s4a_1p8: s4 { - regulator-name = "vreg_s4a_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - vreg_s5a_2p15: s5 { - regulator-name = "vreg_s5a_2p15"; - regulator-min-microvolt = <2150000>; - regulator-max-microvolt = <2150000>; - }; - vreg_s7a_1p0: s7 { - regulator-name = "vreg_s7a_1p0"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <800000>; - }; - - vreg_l1a_1p0: l1 { - regulator-name = "vreg_l1a_1p0"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - }; - vreg_l2a_1p25: l2 { - regulator-name = "vreg_l2a_1p25"; - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1250000>; - }; - vreg_l3a_0p875: l3 { - regulator-name = "vreg_l3a_0p875"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - }; - vreg_l4a_1p225: l4 { - regulator-name = "vreg_l4a_1p225"; - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - vreg_l6a_1p2: l6 { - regulator-name = "vreg_l6a_1p2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - vreg_l8a_1p8: l8 { - regulator-name = "vreg_l8a_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - vreg_l9a_1p8: l9 { - regulator-name = "vreg_l9a_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - vreg_l10a_1p8: l10 { - regulator-name = "vreg_l10a_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - vreg_l11a_1p15: l11 { - regulator-name = "vreg_l11a_1p15"; - regulator-min-microvolt = <1150000>; - regulator-max-microvolt = <1150000>; - }; - vreg_l12a_1p8: l12 { - regulator-name = "vreg_l12a_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - vreg_l13a_2p95: l13 { - regulator-name = "vreg_l13a_2p95"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - vreg_l14a_1p8: l14 { - regulator-name = "vreg_l14a_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - vreg_l15a_1p8: l15 { - regulator-name = "vreg_l15a_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - vreg_l16a_2p7: l16 { - regulator-name = "vreg_l16a_2p7"; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; - vreg_l17a_2p8: l17 { - regulator-name = "vreg_l17a_2p8"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - }; - vreg_l18a_2p85: l18 { - regulator-name = "vreg_l18a_2p85"; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2900000>; - }; - vreg_l19a_2p8: l19 { - regulator-name = "vreg_l19a_2p8"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - vreg_l20a_2p95: l20 { - regulator-name = "vreg_l20a_2p95"; - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - regulator-allow-set-load; - }; - vreg_l21a_2p95: l21 { - regulator-name = "vreg_l21a_2p95"; - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - regulator-allow-set-load; - regulator-system-load = <200000>; - }; - vreg_l22a_3p0: l22 { - regulator-name = "vreg_l22a_3p0"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - vreg_l23a_2p8: l23 { - regulator-name = "vreg_l23a_2p8"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - vreg_l24a_3p075: l24 { - regulator-name = "vreg_l24a_3p075"; - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3075000>; - }; - vreg_l25a_1p2: l25 { - regulator-name = "vreg_l25a_1p2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-allow-set-load; - }; - vreg_l26a_0p8: l27 { - regulator-name = "vreg_l26a_0p8"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - }; - vreg_l28a_0p925: l28 { - regulator-name = "vreg_l28a_0p925"; - regulator-min-microvolt = <925000>; - regulator-max-microvolt = <925000>; - regulator-allow-set-load; - }; - vreg_l29a_2p8: l29 { - regulator-name = "vreg_l29a_2p8"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - vreg_l30a_1p8: l30 { - regulator-name = "vreg_l30a_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - vreg_l32a_1p8: l32 { - regulator-name = "vreg_l32a_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vreg_lvs1a_1p8: lvs1 { - regulator-name = "vreg_lvs1a_1p8"; - }; - - vreg_lvs2a_1p8: lvs2 { - regulator-name = "vreg_lvs2a_1p8"; - }; - }; -}; - -&sdhc2 { - /* External SD card */ - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; - pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; - cd-gpios = <&msmgpio 38 0x1>; - vmmc-supply = <&vreg_l21a_2p95>; - vqmmc-supply = <&vreg_l13a_2p95>; - status = "okay"; -}; - -&sound { - compatible = "qcom,apq8096-sndcard"; - model = "DB820c"; - audio-routing = "RX_BIAS", "MCLK"; - - mm1-dai-link { - link-name = "MultiMedia1"; - cpu { - sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA1>; - }; - }; - - mm2-dai-link { - link-name = "MultiMedia2"; - cpu { - sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA2>; - }; - }; - - mm3-dai-link { - link-name = "MultiMedia3"; - cpu { - sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA3>; - }; - }; - - hdmi-dai-link { - link-name = "HDMI"; - cpu { - sound-dai = <&q6afedai HDMI_RX>; - }; - - platform { - sound-dai = <&q6routing>; - }; - - codec { - sound-dai = <&hdmi 0>; - }; - }; - - slim-dai-link { - link-name = "SLIM Playback"; - cpu { - sound-dai = <&q6afedai SLIMBUS_6_RX>; - }; - - platform { - sound-dai = <&q6routing>; - }; - - codec { - sound-dai = <&wcd9335 6>; - }; - }; - - slimcap-dai-link { - link-name = "SLIM Capture"; - cpu { - sound-dai = <&q6afedai SLIMBUS_0_TX>; - }; - - platform { - sound-dai = <&q6routing>; - }; - - codec { - sound-dai = <&wcd9335 1>; - }; - }; -}; - -&spmi_bus { - pmic@0 { - pon@800 { - resin { - compatible = "qcom,pm8941-resin"; - interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>; - debounce = <15625>; - bias-pull-up; - linux,code = ; - }; - }; - }; -}; - -&ufsphy { - status = "okay"; - - vdda-phy-supply = <&vreg_l28a_0p925>; - vdda-pll-supply = <&vreg_l12a_1p8>; - - vdda-phy-max-microamp = <18380>; - vdda-pll-max-microamp = <9440>; - - vddp-ref-clk-supply = <&vreg_l25a_1p2>; - vddp-ref-clk-max-microamp = <100>; - vddp-ref-clk-always-on; -}; - -&ufshc { - status = "okay"; - - vcc-supply = <&vreg_l20a_2p95>; - vccq-supply = <&vreg_l25a_1p2>; - vccq2-supply = <&vreg_s4a_1p8>; - - vcc-max-microamp = <600000>; - vccq-max-microamp = <450000>; - vccq2-max-microamp = <450000>; -}; - -&usb2 { - status = "okay"; - extcon = <&usb2_id>; - - dwc3@7600000 { - extcon = <&usb2_id>; - dr_mode = "otg"; - maximum-speed = "high-speed"; - }; -}; - -&usb3 { - status = "okay"; - extcon = <&usb3_id>; - - dwc3@6a00000 { - extcon = <&usb3_id>; - dr_mode = "otg"; - }; -}; - -&usb3phy { - status = "okay"; - - vdda-phy-supply = <&vreg_l28a_0p925>; - vdda-pll-supply = <&vreg_l12a_1p8>; - -}; - -&wcd9335 { - clock-names = "mclk", "slimbus"; - clocks = <&div1_mclk>, - <&rpmcc RPM_SMD_BB_CLK1>; - - vdd-buck-supply = <&vreg_s4a_1p8>; - vdd-buck-sido-supply = <&vreg_s4a_1p8>; - vdd-tx-supply = <&vreg_s4a_1p8>; - vdd-rx-supply = <&vreg_s4a_1p8>; - vdd-io-supply = <&vreg_s4a_1p8>; -}; diff --git a/sys/gnu/dts/arm64/qcom/apq8096-ifc6640.dts b/sys/gnu/dts/arm64/qcom/apq8096-ifc6640.dts deleted file mode 100644 index f6ddf17ada8..00000000000 --- a/sys/gnu/dts/arm64/qcom/apq8096-ifc6640.dts +++ /dev/null @@ -1,385 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause - -/dts-v1/; - -#include "msm8996.dtsi" -#include "pm8994.dtsi" -#include "pmi8994.dtsi" -#include -#include -#include - -/ { - model = "Inforce 6640 Single Board Computer"; - compatible = "inforce,ifc6640", "qcom,apq8096-sbc", "qcom,apq8096"; - - qcom,msm-id = <291 0x00030001>; - qcom,board-id = <0x00010018 0>; - - aliases { - serial0 = &blsp2_uart1; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - v1p05: v1p05-regulator { - compatible = "regulator-fixed"; - reglator-name = "v1p05"; - regulator-always-on; - regulator-boot-on; - - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - - vin-supply = <&v5p0>; - }; - - v12_poe: v12-poe-regulator { - compatible = "regulator-fixed"; - reglator-name = "v12_poe"; - regulator-always-on; - regulator-boot-on; - - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - v3p3: v3p3-regulator { - compatible = "regulator-fixed"; - regulator-name = "v3p3"; - regulator-always-on; - regulator-boot-on; - - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - vin-supply = <&v12_poe>; - }; - - v5p0: v5p0-regulator { - compatible = "regulator-fixed"; - regulator-name = "v5p0"; - regulator-always-on; - regulator-boot-on; - - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - vin-supply = <&v12_poe>; - }; - - vph_pwr: vph-pwr-regulator { - compatible = "regulator-fixed"; - regulator-name = "vph_pwr"; - regulator-always-on; - regulator-boot-on; - - regulator-min-microvolt = <3800000>; - regulator-max-microvolt = <3800000>; - }; -}; - -&blsp2_uart1 { - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp2_uart1_2pins_default>; - pinctrl-1 = <&blsp2_uart1_2pins_sleep>; -}; - -&msmgpio { - sdc2_pins_default: sdc2-pins-default { - clk { - pins = "sdc2_clk"; - bias-disable; - drive-strength = <16>; - }; - - cmd { - pins = "sdc2_cmd"; - bias-pull-up; - drive-strength = <10>; - }; - - data { - pins = "sdc2_data"; - bias-pull-up; - drive-strength = <10>; - }; - - cd { - pins = "gpio38"; - function = "gpio"; - - bias-pull-up; - drive-strength = <16>; - }; - }; - - sdc2_pins_sleep: sdc2-pins-sleep { - clk { - pins = "sdc2_clk"; - bias-disable; - drive-strength = <2>; - }; - - cmd { - pins = "sdc2_cmd"; - bias-pull-up; - drive-strength = <2>; - }; - - data { - pins = "sdc2_data"; - bias-pull-up; - drive-strength = <2>; - }; - - cd { - pins = "gpio38"; - function = "gpio"; - bias-pull-up; - drive-strength = <2>; - }; - }; -}; - -&rpm_requests { - pm8994-regulators { - compatible = "qcom,rpm-pm8994-regulators"; - - vdd_s1-supply = <&vph_pwr>; - vdd_s2-supply = <&vph_pwr>; - vdd_s3-supply = <&vph_pwr>; - vdd_s4-supply = <&vph_pwr>; - vdd_s5-supply = <&vph_pwr>; - vdd_s6-supply = <&vph_pwr>; - vdd_s7-supply = <&vph_pwr>; - vdd_s8-supply = <&vph_pwr>; - vdd_s9-supply = <&vph_pwr>; - vdd_s10-supply = <&vph_pwr>; - vdd_s11-supply = <&vph_pwr>; - vdd_s12-supply = <&vph_pwr>; - vdd_l2_l26_l28-supply = <&vreg_s3a_1p3>; - vdd_l3_l11-supply = <&vreg_s3a_1p3>; - vdd_l4_l27_l31-supply = <&vreg_s3a_1p3>; - vdd_l5_l7-supply = <&vreg_s5a_2p15>; - vdd_l6_l12_l32-supply = <&vreg_s5a_2p15>; - vdd_l8_l16_l30-supply = <&vph_pwr>; - vdd_l25-supply = <&vreg_s3a_1p3>; - vdd_lvs1_2-supply = <&vreg_s4a_1p8>; - - vreg_s3a_1p3: s3 { - regulator-name = "vreg_s3a_1p3"; - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - }; - - vreg_s4a_1p8: s4 { - regulator-name = "vreg_s4a_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - vreg_s5a_2p15: s5 { - regulator-name = "vreg_s5a_2p15"; - regulator-min-microvolt = <2150000>; - regulator-max-microvolt = <2150000>; - }; - vreg_s7a_1p0: s7 { - regulator-name = "vreg_s7a_1p0"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <800000>; - }; - - vreg_l1a_1p0: l1 { - regulator-name = "vreg_l1a_1p0"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - }; - vreg_l2a_1p25: l2 { - regulator-name = "vreg_l2a_1p25"; - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1250000>; - }; - vreg_l3a_0p875: l3 { - regulator-name = "vreg_l3a_0p875"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - }; - vreg_l4a_1p225: l4 { - regulator-name = "vreg_l4a_1p225"; - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - vreg_l6a_1p2: l6 { - regulator-name = "vreg_l6a_1p2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - vreg_l8a_1p8: l8 { - regulator-name = "vreg_l8a_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - vreg_l9a_1p8: l9 { - regulator-name = "vreg_l9a_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - vreg_l10a_1p8: l10 { - regulator-name = "vreg_l10a_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - vreg_l11a_1p15: l11 { - regulator-name = "vreg_l11a_1p15"; - regulator-min-microvolt = <1150000>; - regulator-max-microvolt = <1150000>; - }; - vreg_l12a_1p8: l12 { - regulator-name = "vreg_l12a_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - vreg_l13a_2p95: l13 { - regulator-name = "vreg_l13a_2p95"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - vreg_l14a_1p8: l14 { - regulator-name = "vreg_l14a_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - vreg_l15a_1p8: l15 { - regulator-name = "vreg_l15a_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - vreg_l16a_2p7: l16 { - regulator-name = "vreg_l16a_2p7"; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; - vreg_l17a_2p8: l17 { - regulator-name = "vreg_l17a_2p8"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - }; - vreg_l18a_2p85: l18 { - regulator-name = "vreg_l18a_2p85"; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2900000>; - }; - vreg_l19a_2p8: l19 { - regulator-name = "vreg_l19a_2p8"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - vreg_l20a_2p95: l20 { - regulator-name = "vreg_l20a_2p95"; - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - regulator-allow-set-load; - }; - vreg_l21a_2p95: l21 { - regulator-name = "vreg_l21a_2p95"; - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - }; - vreg_l22a_3p0: l22 { - regulator-name = "vreg_l22a_3p0"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - vreg_l23a_2p8: l23 { - regulator-name = "vreg_l23a_2p8"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - vreg_l24a_3p075: l24 { - regulator-name = "vreg_l24a_3p075"; - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3075000>; - }; - vreg_l25a_1p2: l25 { - regulator-name = "vreg_l25a_1p2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-allow-set-load; - }; - vreg_l26a_0p8: l27 { - regulator-name = "vreg_l26a_0p8"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - }; - vreg_l28a_0p925: l28 { - regulator-name = "vreg_l28a_0p925"; - regulator-min-microvolt = <925000>; - regulator-max-microvolt = <925000>; - regulator-allow-set-load; - }; - vreg_l29a_2p8: l29 { - regulator-name = "vreg_l29a_2p8"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - vreg_l30a_1p8: l30 { - regulator-name = "vreg_l30a_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - vreg_l32a_1p8: l32 { - regulator-name = "vreg_l32a_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vreg_lvs1a_1p8: lvs1 { - regulator-name = "vreg_lvs1a_1p8"; - }; - - vreg_lvs2a_1p8: lvs2 { - regulator-name = "vreg_lvs2a_1p8"; - }; - }; -}; - -&sdhc2 { - status = "okay"; - - bus-width = <4>; - - cd-gpios = <&msmgpio 38 0x1>; - - vmmc-supply = <&vreg_l21a_2p95>; - vqmmc-supply = <&vreg_l13a_2p95>; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc2_pins_default>; - pinctrl-1 = <&sdc2_pins_sleep>; -}; - -&ufshc { - status = "okay"; - - vcc-supply = <&vreg_l20a_2p95>; - vccq-supply = <&vreg_l25a_1p2>; - vccq2-supply = <&vreg_s4a_1p8>; - - vcc-max-microamp = <600000>; - vccq-max-microamp = <450000>; - vccq2-max-microamp = <450000>; -}; - -&ufsphy { - status = "okay"; - - vdda-phy-supply = <&vreg_l28a_0p925>; - vdda-pll-supply = <&vreg_l12a_1p8>; - - vdda-phy-max-microamp = <18380>; - vdda-pll-max-microamp = <9440>; -}; diff --git a/sys/gnu/dts/arm64/qcom/ipq8074-hk01.dts b/sys/gnu/dts/arm64/qcom/ipq8074-hk01.dts deleted file mode 100644 index 70be3f95209..00000000000 --- a/sys/gnu/dts/arm64/qcom/ipq8074-hk01.dts +++ /dev/null @@ -1,86 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/dts-v1/; -/* Copyright (c) 2017, The Linux Foundation. All rights reserved. - */ -#include "ipq8074.dtsi" - -/ { - #address-cells = <0x2>; - #size-cells = <0x2>; - model = "Qualcomm Technologies, Inc. IPQ8074-HK01"; - compatible = "qcom,ipq8074-hk01", "qcom,ipq8074"; - interrupt-parent = <&intc>; - - aliases { - serial0 = &blsp1_uart5; - serial1 = &blsp1_uart3; - }; - - chosen { - stdout-path = "serial0"; - }; - - memory { - device_type = "memory"; - reg = <0x0 0x40000000 0x0 0x20000000>; - }; - - soc { - serial@78b3000 { - status = "ok"; - }; - - spi@78b5000 { - status = "ok"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <50000000>; - }; - }; - - serial@78b1000 { - status = "ok"; - }; - - i2c@78b6000 { - status = "ok"; - }; - - dma@7984000 { - status = "ok"; - }; - - nand@79b0000 { - status = "ok"; - - nand@0 { - reg = <0>; - nand-ecc-strength = <4>; - nand-ecc-step-size = <512>; - nand-bus-width = <8>; - }; - }; - - phy@86000 { - status = "ok"; - }; - - phy@8e000 { - status = "ok"; - }; - - pci@20000000 { - status = "ok"; - perst-gpio = <&tlmm 58 0x1>; - }; - - pci@10000000 { - status = "ok"; - perst-gpio = <&tlmm 61 0x1>; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/qcom/ipq8074.dtsi b/sys/gnu/dts/arm64/qcom/ipq8074.dtsi deleted file mode 100644 index 67ee5f56010..00000000000 --- a/sys/gnu/dts/arm64/qcom/ipq8074.dtsi +++ /dev/null @@ -1,495 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2017, The Linux Foundation. All rights reserved. - */ - -#include -#include - -/ { - model = "Qualcomm Technologies, Inc. IPQ8074"; - compatible = "qcom,ipq8074"; - - soc: soc { - #address-cells = <0x1>; - #size-cells = <0x1>; - ranges = <0 0 0 0xffffffff>; - compatible = "simple-bus"; - - tlmm: pinctrl@1000000 { - compatible = "qcom,ipq8074-pinctrl"; - reg = <0x1000000 0x300000>; - interrupts = ; - gpio-controller; - #gpio-cells = <0x2>; - interrupt-controller; - #interrupt-cells = <0x2>; - - serial_4_pins: serial4-pinmux { - pins = "gpio23", "gpio24"; - function = "blsp4_uart1"; - drive-strength = <8>; - bias-disable; - }; - - i2c_0_pins: i2c-0-pinmux { - pins = "gpio42", "gpio43"; - function = "blsp1_i2c"; - drive-strength = <8>; - bias-disable; - }; - - spi_0_pins: spi-0-pins { - pins = "gpio38", "gpio39", "gpio40", "gpio41"; - function = "blsp0_spi"; - drive-strength = <8>; - bias-disable; - }; - - hsuart_pins: hsuart-pins { - pins = "gpio46", "gpio47", "gpio48", "gpio49"; - function = "blsp2_uart"; - drive-strength = <8>; - bias-disable; - }; - - qpic_pins: qpic-pins { - pins = "gpio1", "gpio3", "gpio4", - "gpio5", "gpio6", "gpio7", - "gpio8", "gpio10", "gpio11", - "gpio12", "gpio13", "gpio14", - "gpio15", "gpio16", "gpio17"; - function = "qpic"; - drive-strength = <8>; - bias-disable; - }; - }; - - intc: interrupt-controller@b000000 { - compatible = "qcom,msm-qgic2"; - interrupt-controller; - #interrupt-cells = <0x3>; - reg = <0xb000000 0x1000>, <0xb002000 0x1000>; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - timer@b120000 { - #address-cells = <1>; - #size-cells = <1>; - ranges; - compatible = "arm,armv7-timer-mem"; - reg = <0xb120000 0x1000>; - clock-frequency = <19200000>; - - frame@b120000 { - frame-number = <0>; - interrupts = , - ; - reg = <0xb121000 0x1000>, - <0xb122000 0x1000>; - }; - - frame@b123000 { - frame-number = <1>; - interrupts = ; - reg = <0xb123000 0x1000>; - status = "disabled"; - }; - - frame@b124000 { - frame-number = <2>; - interrupts = ; - reg = <0xb124000 0x1000>; - status = "disabled"; - }; - - frame@b125000 { - frame-number = <3>; - interrupts = ; - reg = <0xb125000 0x1000>; - status = "disabled"; - }; - - frame@b126000 { - frame-number = <4>; - interrupts = ; - reg = <0xb126000 0x1000>; - status = "disabled"; - }; - - frame@b127000 { - frame-number = <5>; - interrupts = ; - reg = <0xb127000 0x1000>; - status = "disabled"; - }; - - frame@b128000 { - frame-number = <6>; - interrupts = ; - reg = <0xb128000 0x1000>; - status = "disabled"; - }; - }; - - gcc: gcc@1800000 { - compatible = "qcom,gcc-ipq8074"; - reg = <0x1800000 0x80000>; - #clock-cells = <0x1>; - #reset-cells = <0x1>; - }; - - blsp1_uart5: serial@78b3000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0x78b3000 0x200>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - pinctrl-0 = <&serial_4_pins>; - pinctrl-names = "default"; - status = "disabled"; - }; - - blsp_dma: dma@7884000 { - compatible = "qcom,bam-v1.7.0"; - reg = <0x7884000 0x2b000>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "bam_clk"; - #dma-cells = <1>; - qcom,ee = <0>; - }; - - blsp1_uart1: serial@78af000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0x78af000 0x200>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - - blsp1_uart3: serial@78b1000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0x78b1000 0x200>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - dmas = <&blsp_dma 4>, - <&blsp_dma 5>; - dma-names = "tx", "rx"; - pinctrl-0 = <&hsuart_pins>; - pinctrl-names = "default"; - status = "disabled"; - }; - - blsp1_spi1: spi@78b5000 { - compatible = "qcom,spi-qup-v2.2.1"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x78b5000 0x600>; - interrupts = ; - spi-max-frequency = <50000000>; - clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - dmas = <&blsp_dma 12>, <&blsp_dma 13>; - dma-names = "tx", "rx"; - pinctrl-0 = <&spi_0_pins>; - pinctrl-names = "default"; - status = "disabled"; - }; - - blsp1_i2c2: i2c@78b6000 { - compatible = "qcom,i2c-qup-v2.2.1"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x78b6000 0x600>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; - clock-names = "iface", "core"; - clock-frequency = <400000>; - dmas = <&blsp_dma 15>, <&blsp_dma 14>; - dma-names = "rx", "tx"; - pinctrl-0 = <&i2c_0_pins>; - pinctrl-names = "default"; - status = "disabled"; - }; - - blsp1_i2c3: i2c@78b7000 { - compatible = "qcom,i2c-qup-v2.2.1"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x78b7000 0x600>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; - clock-names = "iface", "core"; - clock-frequency = <100000>; - dmas = <&blsp_dma 17>, <&blsp_dma 16>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - qpic_bam: dma@7984000 { - compatible = "qcom,bam-v1.7.0"; - reg = <0x7984000 0x1a000>; - interrupts = ; - clocks = <&gcc GCC_QPIC_AHB_CLK>; - clock-names = "bam_clk"; - #dma-cells = <1>; - qcom,ee = <0>; - status = "disabled"; - }; - - qpic_nand: nand@79b0000 { - compatible = "qcom,ipq8074-nand"; - reg = <0x79b0000 0x10000>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&gcc GCC_QPIC_CLK>, - <&gcc GCC_QPIC_AHB_CLK>; - clock-names = "core", "aon"; - - dmas = <&qpic_bam 0>, - <&qpic_bam 1>, - <&qpic_bam 2>; - dma-names = "tx", "rx", "cmd"; - pinctrl-0 = <&qpic_pins>; - pinctrl-names = "default"; - status = "disabled"; - }; - - pcie_phy0: phy@86000 { - compatible = "qcom,ipq8074-qmp-pcie-phy"; - reg = <0x86000 0x1000>; - #phy-cells = <0>; - clocks = <&gcc GCC_PCIE0_PIPE_CLK>; - clock-names = "pipe_clk"; - clock-output-names = "pcie20_phy0_pipe_clk"; - - resets = <&gcc GCC_PCIE0_PHY_BCR>, - <&gcc GCC_PCIE0PHY_PHY_BCR>; - reset-names = "phy", - "common"; - status = "disabled"; - }; - - pcie0: pci@20000000 { - compatible = "qcom,pcie-ipq8074"; - reg = <0x20000000 0xf1d - 0x20000f20 0xa8 - 0x80000 0x2000 - 0x20100000 0x1000>; - reg-names = "dbi", "elbi", "parf", "config"; - device_type = "pci"; - linux,pci-domain = <0>; - bus-range = <0x00 0xff>; - num-lanes = <1>; - #address-cells = <3>; - #size-cells = <2>; - - phys = <&pcie_phy0>; - phy-names = "pciephy"; - - ranges = <0x81000000 0 0x20200000 0x20200000 - 0 0x100000 /* downstream I/O */ - 0x82000000 0 0x20300000 0x20300000 - 0 0xd00000>; /* non-prefetchable memory */ - - interrupts = ; - interrupt-names = "msi"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 75 - IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 78 - IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 79 - IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 83 - IRQ_TYPE_LEVEL_HIGH>; /* int_d */ - - clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>, - <&gcc GCC_PCIE0_AXI_M_CLK>, - <&gcc GCC_PCIE0_AXI_S_CLK>, - <&gcc GCC_PCIE0_AHB_CLK>, - <&gcc GCC_PCIE0_AUX_CLK>; - - clock-names = "iface", - "axi_m", - "axi_s", - "ahb", - "aux"; - resets = <&gcc GCC_PCIE0_PIPE_ARES>, - <&gcc GCC_PCIE0_SLEEP_ARES>, - <&gcc GCC_PCIE0_CORE_STICKY_ARES>, - <&gcc GCC_PCIE0_AXI_MASTER_ARES>, - <&gcc GCC_PCIE0_AXI_SLAVE_ARES>, - <&gcc GCC_PCIE0_AHB_ARES>, - <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>; - reset-names = "pipe", - "sleep", - "sticky", - "axi_m", - "axi_s", - "ahb", - "axi_m_sticky"; - status = "disabled"; - }; - - pcie_phy1: phy@8e000 { - compatible = "qcom,ipq8074-qmp-pcie-phy"; - reg = <0x8e000 0x1000>; - #phy-cells = <0>; - clocks = <&gcc GCC_PCIE1_PIPE_CLK>; - clock-names = "pipe_clk"; - clock-output-names = "pcie20_phy1_pipe_clk"; - - resets = <&gcc GCC_PCIE1_PHY_BCR>, - <&gcc GCC_PCIE1PHY_PHY_BCR>; - reset-names = "phy", - "common"; - status = "disabled"; - }; - - pcie1: pci@10000000 { - compatible = "qcom,pcie-ipq8074"; - reg = <0x10000000 0xf1d - 0x10000f20 0xa8 - 0x88000 0x2000 - 0x10100000 0x1000>; - reg-names = "dbi", "elbi", "parf", "config"; - device_type = "pci"; - linux,pci-domain = <1>; - bus-range = <0x00 0xff>; - num-lanes = <1>; - #address-cells = <3>; - #size-cells = <2>; - - phys = <&pcie_phy1>; - phy-names = "pciephy"; - - ranges = <0x81000000 0 0x10200000 0x10200000 - 0 0x100000 /* downstream I/O */ - 0x82000000 0 0x10300000 0x10300000 - 0 0xd00000>; /* non-prefetchable memory */ - - interrupts = ; - interrupt-names = "msi"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 142 - IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 143 - IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 144 - IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 145 - IRQ_TYPE_LEVEL_HIGH>; /* int_d */ - - clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>, - <&gcc GCC_PCIE1_AXI_M_CLK>, - <&gcc GCC_PCIE1_AXI_S_CLK>, - <&gcc GCC_PCIE1_AHB_CLK>, - <&gcc GCC_PCIE1_AUX_CLK>; - clock-names = "iface", - "axi_m", - "axi_s", - "ahb", - "aux"; - resets = <&gcc GCC_PCIE1_PIPE_ARES>, - <&gcc GCC_PCIE1_SLEEP_ARES>, - <&gcc GCC_PCIE1_CORE_STICKY_ARES>, - <&gcc GCC_PCIE1_AXI_MASTER_ARES>, - <&gcc GCC_PCIE1_AXI_SLAVE_ARES>, - <&gcc GCC_PCIE1_AHB_ARES>, - <&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>; - reset-names = "pipe", - "sleep", - "sticky", - "axi_m", - "axi_s", - "ahb", - "axi_m_sticky"; - status = "disabled"; - }; - }; - - cpus { - #address-cells = <0x1>; - #size-cells = <0x0>; - - CPU0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - CPU1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x1>; - next-level-cache = <&L2_0>; - }; - - CPU2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x2>; - next-level-cache = <&L2_0>; - }; - - CPU3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x3>; - next-level-cache = <&L2_0>; - }; - - L2_0: l2-cache { - compatible = "cache"; - cache-level = <0x2>; - }; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = ; - }; - - clocks { - sleep_clk: sleep_clk { - compatible = "fixed-clock"; - clock-frequency = <32000>; - #clock-cells = <0>; - }; - - xo: xo { - compatible = "fixed-clock"; - clock-frequency = <19200000>; - #clock-cells = <0>; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/qcom/msm8916-longcheer-l8150.dts b/sys/gnu/dts/arm64/qcom/msm8916-longcheer-l8150.dts deleted file mode 100644 index d1ccb9472c8..00000000000 --- a/sys/gnu/dts/arm64/qcom/msm8916-longcheer-l8150.dts +++ /dev/null @@ -1,283 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only - -/dts-v1/; - -#include "msm8916.dtsi" -#include "pm8916.dtsi" -#include -#include - -/ { - model = "Longcheer L8150"; - compatible = "longcheer,l8150", "qcom,msm8916-v1-qrd/9-v1", "qcom,msm8916"; - - aliases { - serial0 = &blsp1_uart2; - }; - - chosen { - stdout-path = "serial0"; - }; - - reserved-memory { - // wcnss.mdt is not relocatable, so it must be loaded at 0x8b600000 - /delete-node/ wcnss@89300000; - - wcnss_mem: wcnss@8b600000 { - reg = <0x0 0x8b600000 0x0 0x600000>; - no-map; - }; - }; - - soc { - sdhci@7824000 { - status = "okay"; - - vmmc-supply = <&pm8916_l8>; - vqmmc-supply = <&pm8916_l5>; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>; - pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>; - }; - - sdhci@7864000 { - status = "okay"; - - vmmc-supply = <&pm8916_l11>; - vqmmc-supply = <&pm8916_l12>; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>; - pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>; - - non-removable; - }; - - serial@78b0000 { - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp1_uart2_default>; - pinctrl-1 = <&blsp1_uart2_sleep>; - }; - - usb@78d9000 { - status = "okay"; - dr_mode = "peripheral"; - extcon = <&usb_vbus>; - - hnp-disable; - srp-disable; - adp-disable; - - ulpi { - phy { - extcon = <&usb_vbus>; - v1p8-supply = <&pm8916_l7>; - v3p3-supply = <&pm8916_l13>; - }; - }; - }; - - wcnss@a21b000 { - status = "okay"; - }; - - /* - * Attempting to enable these devices causes a "synchronous - * external abort". Suspected cause is that the debug power - * domain is not enabled by default on this device. - * Disable these devices for now to avoid the crash. - * - * See: https://lore.kernel.org/linux-arm-msm/20190618202623.GA53651@gerhold.net/ - */ - tpiu@820000 { status = "disabled"; }; - funnel@821000 { status = "disabled"; }; - replicator@824000 { status = "disabled"; }; - etf@825000 { status = "disabled"; }; - etr@826000 { status = "disabled"; }; - funnel@841000 { status = "disabled"; }; - debug@850000 { status = "disabled"; }; - debug@852000 { status = "disabled"; }; - debug@854000 { status = "disabled"; }; - debug@856000 { status = "disabled"; }; - etm@85c000 { status = "disabled"; }; - etm@85d000 { status = "disabled"; }; - etm@85e000 { status = "disabled"; }; - etm@85f000 { status = "disabled"; }; - }; - - // FIXME: Use extcon device provided by charger driver when available - usb_vbus: usb-vbus { - compatible = "linux,extcon-usb-gpio"; - vbus-gpio = <&msmgpio 62 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&usb_vbus_default>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - pinctrl-names = "default"; - pinctrl-0 = <&gpio_keys_default>; - - label = "GPIO Buttons"; - - volume-up { - label = "Volume Up"; - gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; -}; - -&msmgpio { - gpio_keys_default: gpio_keys_default { - pinmux { - function = "gpio"; - pins = "gpio107"; - }; - pinconf { - pins = "gpio107"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - usb_vbus_default: usb-vbus-default { - pinmux { - function = "gpio"; - pins = "gpio62"; - }; - pinconf { - pins = "gpio62"; - bias-pull-up; - }; - }; -}; - -&spmi_bus { - pm8916@0 { - pon@800 { - volume-down { - compatible = "qcom,pm8941-resin"; - interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>; - bias-pull-up; - linux,code = ; - }; - }; - }; -}; - -&smd_rpm_regulators { - vdd_l1_l2_l3-supply = <&pm8916_s3>; - vdd_l4_l5_l6-supply = <&pm8916_s4>; - vdd_l7-supply = <&pm8916_s4>; - - s1 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1300000>; - }; - - s3 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1300000>; - }; - - s4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2100000>; - }; - - l1 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - - l2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - l3 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1287500>; - }; - - l4 { - regulator-min-microvolt = <2050000>; - regulator-max-microvolt = <2050000>; - }; - - l5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l8 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2900000>; - }; - - l9 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - l10 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2800000>; - }; - - l11 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - regulator-allow-set-load; - regulator-system-load = <200000>; - }; - - l12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - l13 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3075000>; - }; - - l14 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - l15 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - l16 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - l17 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - l18 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; -}; diff --git a/sys/gnu/dts/arm64/qcom/msm8916-mtp.dts b/sys/gnu/dts/arm64/qcom/msm8916-mtp.dts deleted file mode 100644 index c3f88592312..00000000000 --- a/sys/gnu/dts/arm64/qcom/msm8916-mtp.dts +++ /dev/null @@ -1,14 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. - */ - -/dts-v1/; - -#include "msm8916-mtp.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. MSM 8916 MTP"; - compatible = "qcom,msm8916-mtp", "qcom,msm8916-mtp/1", - "qcom,msm8916", "qcom,mtp"; -}; diff --git a/sys/gnu/dts/arm64/qcom/msm8916-mtp.dtsi b/sys/gnu/dts/arm64/qcom/msm8916-mtp.dtsi deleted file mode 100644 index 0c6e81fb8c0..00000000000 --- a/sys/gnu/dts/arm64/qcom/msm8916-mtp.dtsi +++ /dev/null @@ -1,27 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. - */ - -#include "msm8916.dtsi" -#include "pm8916.dtsi" - -/ { - aliases { - serial0 = &blsp1_uart2; - usid0 = &pm8916_0; - }; - - chosen { - stdout-path = "serial0"; - }; - - soc { - serial@78b0000 { - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp1_uart2_default>; - pinctrl-1 = <&blsp1_uart2_sleep>; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/qcom/msm8916-pins.dtsi b/sys/gnu/dts/arm64/qcom/msm8916-pins.dtsi deleted file mode 100644 index 242aaea6880..00000000000 --- a/sys/gnu/dts/arm64/qcom/msm8916-pins.dtsi +++ /dev/null @@ -1,760 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. - */ - -&msmgpio { - - blsp1_uart1_default: blsp1_uart1_default { - pinmux { - function = "blsp_uart1"; - // TX, RX, CTS_N, RTS_N - pins = "gpio0", "gpio1", - "gpio2", "gpio3"; - }; - pinconf { - pins = "gpio0", "gpio1", - "gpio2", "gpio3"; - drive-strength = <16>; - bias-disable; - }; - }; - - blsp1_uart1_sleep: blsp1_uart1_sleep { - pinmux { - function = "gpio"; - pins = "gpio0", "gpio1", - "gpio2", "gpio3"; - }; - pinconf { - pins = "gpio0", "gpio1", - "gpio2", "gpio3"; - drive-strength = <2>; - bias-pull-down; - }; - }; - - blsp1_uart2_default: blsp1_uart2_default { - pinmux { - function = "blsp_uart2"; - pins = "gpio4", "gpio5"; - }; - pinconf { - pins = "gpio4", "gpio5"; - drive-strength = <16>; - bias-disable; - }; - }; - - blsp1_uart2_sleep: blsp1_uart2_sleep { - pinmux { - function = "gpio"; - pins = "gpio4", "gpio5"; - }; - pinconf { - pins = "gpio4", "gpio5"; - drive-strength = <2>; - bias-pull-down; - }; - }; - - spi1_default: spi1_default { - pinmux { - function = "blsp_spi1"; - pins = "gpio0", "gpio1", "gpio3"; - }; - pinmux_cs { - function = "gpio"; - pins = "gpio2"; - }; - pinconf { - pins = "gpio0", "gpio1", "gpio3"; - drive-strength = <12>; - bias-disable; - }; - pinconf_cs { - pins = "gpio2"; - drive-strength = <16>; - bias-disable; - output-high; - }; - }; - - spi1_sleep: spi1_sleep { - pinmux { - function = "gpio"; - pins = "gpio0", "gpio1", "gpio2", "gpio3"; - }; - pinconf { - pins = "gpio0", "gpio1", "gpio2", "gpio3"; - drive-strength = <2>; - bias-pull-down; - }; - }; - - spi2_default: spi2_default { - pinmux { - function = "blsp_spi2"; - pins = "gpio4", "gpio5", "gpio7"; - }; - pinmux_cs { - function = "gpio"; - pins = "gpio6"; - }; - pinconf { - pins = "gpio4", "gpio5", "gpio7"; - drive-strength = <12>; - bias-disable; - }; - pinconf_cs { - pins = "gpio6"; - drive-strength = <16>; - bias-disable; - output-high; - }; - }; - - spi2_sleep: spi2_sleep { - pinmux { - function = "gpio"; - pins = "gpio4", "gpio5", "gpio6", "gpio7"; - }; - pinconf { - pins = "gpio4", "gpio5", "gpio6", "gpio7"; - drive-strength = <2>; - bias-pull-down; - }; - }; - - spi3_default: spi3_default { - pinmux { - function = "blsp_spi3"; - pins = "gpio8", "gpio9", "gpio11"; - }; - pinmux_cs { - function = "gpio"; - pins = "gpio10"; - }; - pinconf { - pins = "gpio8", "gpio9", "gpio11"; - drive-strength = <12>; - bias-disable; - }; - pinconf_cs { - pins = "gpio10"; - drive-strength = <16>; - bias-disable; - output-high; - }; - }; - - spi3_sleep: spi3_sleep { - pinmux { - function = "gpio"; - pins = "gpio8", "gpio9", "gpio10", "gpio11"; - }; - pinconf { - pins = "gpio8", "gpio9", "gpio10", "gpio11"; - drive-strength = <2>; - bias-pull-down; - }; - }; - - spi4_default: spi4_default { - pinmux { - function = "blsp_spi4"; - pins = "gpio12", "gpio13", "gpio15"; - }; - pinmux_cs { - function = "gpio"; - pins = "gpio14"; - }; - pinconf { - pins = "gpio12", "gpio13", "gpio15"; - drive-strength = <12>; - bias-disable; - }; - pinconf_cs { - pins = "gpio14"; - drive-strength = <16>; - bias-disable; - output-high; - }; - }; - - spi4_sleep: spi4_sleep { - pinmux { - function = "gpio"; - pins = "gpio12", "gpio13", "gpio14", "gpio15"; - }; - pinconf { - pins = "gpio12", "gpio13", "gpio14", "gpio15"; - drive-strength = <2>; - bias-pull-down; - }; - }; - - spi5_default: spi5_default { - pinmux { - function = "blsp_spi5"; - pins = "gpio16", "gpio17", "gpio19"; - }; - pinmux_cs { - function = "gpio"; - pins = "gpio18"; - }; - pinconf { - pins = "gpio16", "gpio17", "gpio19"; - drive-strength = <12>; - bias-disable; - }; - pinconf_cs { - pins = "gpio18"; - drive-strength = <16>; - bias-disable; - output-high; - }; - }; - - spi5_sleep: spi5_sleep { - pinmux { - function = "gpio"; - pins = "gpio16", "gpio17", "gpio18", "gpio19"; - }; - pinconf { - pins = "gpio16", "gpio17", "gpio18", "gpio19"; - drive-strength = <2>; - bias-pull-down; - }; - }; - - spi6_default: spi6_default { - pinmux { - function = "blsp_spi6"; - pins = "gpio20", "gpio21", "gpio23"; - }; - pinmux_cs { - function = "gpio"; - pins = "gpio22"; - }; - pinconf { - pins = "gpio20", "gpio21", "gpio23"; - drive-strength = <12>; - bias-disable; - }; - pinconf_cs { - pins = "gpio22"; - drive-strength = <16>; - bias-disable; - output-high; - }; - }; - - spi6_sleep: spi6_sleep { - pinmux { - function = "gpio"; - pins = "gpio20", "gpio21", "gpio22", "gpio23"; - }; - pinconf { - pins = "gpio20", "gpio21", "gpio22", "gpio23"; - drive-strength = <2>; - bias-pull-down; - }; - }; - - i2c2_default: i2c2_default { - pinmux { - function = "blsp_i2c2"; - pins = "gpio6", "gpio7"; - }; - pinconf { - pins = "gpio6", "gpio7"; - drive-strength = <16>; - bias-disable; - }; - }; - - i2c2_sleep: i2c2_sleep { - pinmux { - function = "gpio"; - pins = "gpio6", "gpio7"; - }; - pinconf { - pins = "gpio6", "gpio7"; - drive-strength = <2>; - bias-disable; - }; - }; - - i2c4_default: i2c4_default { - pinmux { - function = "blsp_i2c4"; - pins = "gpio14", "gpio15"; - }; - pinconf { - pins = "gpio14", "gpio15"; - drive-strength = <16>; - bias-disable; - }; - }; - - i2c4_sleep: i2c4_sleep { - pinmux { - function = "gpio"; - pins = "gpio14", "gpio15"; - }; - pinconf { - pins = "gpio14", "gpio15"; - drive-strength = <2>; - bias-disable; - }; - }; - - i2c6_default: i2c6_default { - pinmux { - function = "blsp_i2c6"; - pins = "gpio22", "gpio23"; - }; - pinconf { - pins = "gpio22", "gpio23"; - drive-strength = <16>; - bias-disable; - }; - }; - - i2c6_sleep: i2c6_sleep { - pinmux { - function = "gpio"; - pins = "gpio22", "gpio23"; - }; - pinconf { - pins = "gpio22", "gpio23"; - drive-strength = <2>; - bias-disable; - }; - }; - - pmx_sdc1_clk { - sdc1_clk_on: clk_on { - pinmux { - pins = "sdc1_clk"; - }; - pinconf { - pins = "sdc1_clk"; - bias-disable; - drive-strength = <16>; - }; - }; - sdc1_clk_off: clk_off { - pinmux { - pins = "sdc1_clk"; - }; - pinconf { - pins = "sdc1_clk"; - bias-disable; - drive-strength = <2>; - }; - }; - }; - - pmx_sdc1_cmd { - sdc1_cmd_on: cmd_on { - pinmux { - pins = "sdc1_cmd"; - }; - pinconf { - pins = "sdc1_cmd"; - bias-pull-up; - drive-strength = <10>; - }; - }; - sdc1_cmd_off: cmd_off { - pinmux { - pins = "sdc1_cmd"; - }; - pinconf { - pins = "sdc1_cmd"; - bias-pull-up; - drive-strength = <2>; - }; - }; - }; - - pmx_sdc1_data { - sdc1_data_on: data_on { - pinmux { - pins = "sdc1_data"; - }; - pinconf { - pins = "sdc1_data"; - bias-pull-up; - drive-strength = <10>; - }; - }; - sdc1_data_off: data_off { - pinmux { - pins = "sdc1_data"; - }; - pinconf { - pins = "sdc1_data"; - bias-pull-up; - drive-strength = <2>; - }; - }; - }; - - pmx_sdc2_clk { - sdc2_clk_on: clk_on { - pinmux { - pins = "sdc2_clk"; - }; - pinconf { - pins = "sdc2_clk"; - bias-disable; - drive-strength = <16>; - }; - }; - sdc2_clk_off: clk_off { - pinmux { - pins = "sdc2_clk"; - }; - pinconf { - pins = "sdc2_clk"; - bias-disable; - drive-strength = <2>; - }; - }; - }; - - pmx_sdc2_cmd { - sdc2_cmd_on: cmd_on { - pinmux { - pins = "sdc2_cmd"; - }; - pinconf { - pins = "sdc2_cmd"; - bias-pull-up; - drive-strength = <10>; - }; - }; - sdc2_cmd_off: cmd_off { - pinmux { - pins = "sdc2_cmd"; - }; - pinconf { - pins = "sdc2_cmd"; - bias-pull-up; - drive-strength = <2>; - }; - }; - }; - - pmx_sdc2_data { - sdc2_data_on: data_on { - pinmux { - pins = "sdc2_data"; - }; - pinconf { - pins = "sdc2_data"; - bias-pull-up; - drive-strength = <10>; - }; - }; - sdc2_data_off: data_off { - pinmux { - pins = "sdc2_data"; - }; - pinconf { - pins = "sdc2_data"; - bias-pull-up; - drive-strength = <2>; - }; - }; - }; - - pmx_sdc2_cd_pin { - sdc2_cd_on: cd_on { - pinmux { - function = "gpio"; - pins = "gpio38"; - }; - pinconf { - pins = "gpio38"; - drive-strength = <2>; - bias-pull-up; - }; - }; - sdc2_cd_off: cd_off { - pinmux { - function = "gpio"; - pins = "gpio38"; - }; - pinconf { - pins = "gpio38"; - drive-strength = <2>; - bias-disable; - }; - }; - }; - - cdc-pdm-lines { - cdc_pdm_lines_act: pdm_lines_on { - pinmux { - function = "cdc_pdm0"; - pins = "gpio63", "gpio64", "gpio65", "gpio66", - "gpio67", "gpio68"; - }; - pinconf { - pins = "gpio63", "gpio64", "gpio65", "gpio66", - "gpio67", "gpio68"; - drive-strength = <8>; - bias-pull-none; - }; - }; - cdc_pdm_lines_sus: pdm_lines_off { - pinmux { - function = "cdc_pdm0"; - pins = "gpio63", "gpio64", "gpio65", "gpio66", - "gpio67", "gpio68"; - }; - pinconf { - pins = "gpio63", "gpio64", "gpio65", "gpio66", - "gpio67", "gpio68"; - drive-strength = <2>; - bias-disable; - }; - }; - }; - - ext-pri-tlmm-lines { - ext_pri_tlmm_lines_act: ext_pa_on { - pinmux { - function = "pri_mi2s"; - pins = "gpio113", "gpio114", "gpio115", - "gpio116"; - }; - pinconf { - pins = "gpio113", "gpio114", "gpio115", - "gpio116"; - drive-strength = <8>; - bias-pull-none; - }; - }; - - ext_pri_tlmm_lines_sus: ext_pa_off { - pinmux { - function = "pri_mi2s"; - pins = "gpio113", "gpio114", "gpio115", - "gpio116"; - }; - pinconf { - pins = "gpio113", "gpio114", "gpio115", - "gpio116"; - drive-strength = <2>; - bias-disable; - }; - }; - }; - - ext-pri-ws-line { - ext_pri_ws_act: ext_pa_on { - pinmux { - function = "pri_mi2s_ws"; - pins = "gpio110"; - }; - pinconf { - pins = "gpio110"; - drive-strength = <8>; - bias-pull-none; - }; - }; - - ext_pri_ws_sus: ext_pa_off { - pinmux { - function = "pri_mi2s_ws"; - pins = "gpio110"; - }; - pinconf { - pins = "gpio110"; - drive-strength = <2>; - bias-disable; - }; - }; - }; - - ext-mclk-tlmm-lines { - ext_mclk_tlmm_lines_act: mclk_lines_on { - pinmux { - function = "pri_mi2s"; - pins = "gpio116"; - }; - pinconf { - pins = "gpio116"; - drive-strength = <8>; - bias-pull-none; - }; - }; - ext_mclk_tlmm_lines_sus: mclk_lines_off { - pinmux { - function = "pri_mi2s"; - pins = "gpio116"; - }; - pinconf { - pins = "gpio116"; - drive-strength = <2>; - bias-disable; - }; - }; - }; - - /* secondary Mi2S */ - ext-sec-tlmm-lines { - ext_sec_tlmm_lines_act: tlmm_lines_on { - pinmux { - function = "sec_mi2s"; - pins = "gpio112", "gpio117", "gpio118", - "gpio119"; - }; - pinconf { - pins = "gpio112", "gpio117", "gpio118", - "gpio119"; - drive-strength = <8>; - bias-pull-none; - }; - }; - ext_sec_tlmm_lines_sus: tlmm_lines_off { - pinmux { - function = "sec_mi2s"; - pins = "gpio112", "gpio117", "gpio118", - "gpio119"; - }; - pinconf { - pins = "gpio112", "gpio117", "gpio118", - "gpio119"; - drive-strength = <2>; - bias-disable; - }; - }; - }; - - cdc-dmic-lines { - cdc_dmic_lines_act: dmic_lines_on { - pinmux_dmic0_clk { - function = "dmic0_clk"; - pins = "gpio0"; - }; - pinmux_dmic0_data { - function = "dmic0_data"; - pins = "gpio1"; - }; - pinconf { - pins = "gpio0", "gpio1"; - drive-strength = <8>; - }; - }; - cdc_dmic_lines_sus: dmic_lines_off { - pinmux_dmic0_clk { - function = "dmic0_clk"; - pins = "gpio0"; - }; - pinmux_dmic0_data { - function = "dmic0_data"; - pins = "gpio1"; - }; - pinconf { - pins = "gpio0", "gpio1"; - drive-strength = <2>; - bias-disable; - }; - }; - }; - - wcnss_pin_a: wcnss-active { - pinmux { - pins = "gpio40", "gpio41", "gpio42", "gpio43", "gpio44"; - function = "wcss_wlan"; - }; - - pinconf { - pins = "gpio40", "gpio41", "gpio42", "gpio43", "gpio44"; - drive-strength = <6>; - bias-pull-up; - }; - }; - - cci0_default: cci0_default { - pinmux { - function = "cci_i2c"; - pins = "gpio29", "gpio30"; - }; - pinconf { - pins = "gpio29", "gpio30"; - drive-strength = <16>; - bias-disable; - }; - }; - - camera_front_default: camera_front_default { - pinmux_pwdn { - function = "gpio"; - pins = "gpio33"; - }; - pinconf_pwdn { - pins = "gpio33"; - drive-strength = <16>; - bias-disable; - }; - - pinmux_rst { - function = "gpio"; - pins = "gpio28"; - }; - pinconf_rst { - pins = "gpio28"; - drive-strength = <16>; - bias-disable; - }; - - pinmux_mclk1 { - function = "cam_mclk1"; - pins = "gpio27"; - }; - pinconf_mclk1 { - pins = "gpio27"; - drive-strength = <16>; - bias-disable; - }; - }; - - camera_rear_default: camera_rear_default { - pinmux_pwdn { - function = "gpio"; - pins = "gpio34"; - }; - pinconf_pwdn { - pins = "gpio34"; - drive-strength = <16>; - bias-disable; - }; - - pinmux_rst { - function = "gpio"; - pins = "gpio35"; - }; - pinconf_rst { - pins = "gpio35"; - drive-strength = <16>; - bias-disable; - }; - - pinmux_mclk0 { - function = "cam_mclk0"; - pins = "gpio26"; - }; - pinconf_mclk0 { - pins = "gpio26"; - drive-strength = <16>; - bias-disable; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/qcom/msm8916-samsung-a2015-common.dtsi b/sys/gnu/dts/arm64/qcom/msm8916-samsung-a2015-common.dtsi deleted file mode 100644 index bd1eb3eeca5..00000000000 --- a/sys/gnu/dts/arm64/qcom/msm8916-samsung-a2015-common.dtsi +++ /dev/null @@ -1,316 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only - -#include "msm8916.dtsi" -#include "pm8916.dtsi" -#include -#include -#include - -/ { - aliases { - serial0 = &blsp1_uart2; - }; - - chosen { - stdout-path = "serial0"; - }; - - soc { - sdhci@7824000 { - status = "okay"; - - vmmc-supply = <&pm8916_l8>; - vqmmc-supply = <&pm8916_l5>; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>; - pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>; - }; - - sdhci@7864000 { - status = "okay"; - - vmmc-supply = <&pm8916_l11>; - vqmmc-supply = <&pm8916_l12>; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; - pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; - - cd-gpios = <&msmgpio 38 GPIO_ACTIVE_LOW>; - }; - - serial@78b0000 { - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp1_uart2_default>; - pinctrl-1 = <&blsp1_uart2_sleep>; - }; - - usb@78d9000 { - status = "okay"; - extcon = <&muic>, <&muic>; - - hnp-disable; - srp-disable; - adp-disable; - - ulpi { - phy { - extcon = <&muic>; - v1p8-supply = <&pm8916_l7>; - v3p3-supply = <&pm8916_l13>; - }; - }; - }; - - wcnss@a21b000 { - status = "okay"; - }; - - /* - * Attempting to enable these devices causes a "synchronous - * external abort". Suspected cause is that the debug power - * domain is not enabled by default on this device. - * Disable these devices for now to avoid the crash. - * - * See: https://lore.kernel.org/linux-arm-msm/20190618202623.GA53651@gerhold.net/ - */ - tpiu@820000 { status = "disabled"; }; - funnel@821000 { status = "disabled"; }; - replicator@824000 { status = "disabled"; }; - etf@825000 { status = "disabled"; }; - etr@826000 { status = "disabled"; }; - funnel@841000 { status = "disabled"; }; - debug@850000 { status = "disabled"; }; - debug@852000 { status = "disabled"; }; - debug@854000 { status = "disabled"; }; - debug@856000 { status = "disabled"; }; - etm@85c000 { status = "disabled"; }; - etm@85d000 { status = "disabled"; }; - etm@85e000 { status = "disabled"; }; - etm@85f000 { status = "disabled"; }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - pinctrl-names = "default"; - pinctrl-0 = <&gpio_keys_default>; - - label = "GPIO Buttons"; - - volume-up { - label = "Volume Up"; - gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - home { - label = "Home"; - gpios = <&msmgpio 109 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - gpio-hall-sensor { - compatible = "gpio-keys"; - - pinctrl-names = "default"; - pinctrl-0 = <&gpio_hall_sensor_default>; - - label = "GPIO Hall Effect Sensor"; - - hall-sensor { - label = "Hall Effect Sensor"; - gpios = <&msmgpio 52 GPIO_ACTIVE_LOW>; - linux,input-type = ; - linux,code = ; - linux,can-disable; - }; - }; - - i2c-muic { - compatible = "i2c-gpio"; - sda-gpios = <&msmgpio 105 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - scl-gpios = <&msmgpio 106 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - - #address-cells = <1>; - #size-cells = <0>; - - muic: sm5502@25 { - compatible = "siliconmitus,sm5502-muic"; - - reg = <0x25>; - interrupt-parent = <&msmgpio>; - interrupts = <12 IRQ_TYPE_EDGE_FALLING>; - - pinctrl-names = "default"; - pinctrl-0 = <&muic_int_default>; - }; - }; -}; - -&msmgpio { - gpio_keys_default: gpio_keys_default { - pinmux { - function = "gpio"; - pins = "gpio107", "gpio109"; - }; - pinconf { - pins = "gpio107", "gpio109"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - gpio_hall_sensor_default: gpio_hall_sensor_default { - pinmux { - function = "gpio"; - pins = "gpio52"; - }; - pinconf { - pins = "gpio52"; - drive-strength = <2>; - bias-disable; - }; - }; - - muic_int_default: muic_int_default { - pinmux { - function = "gpio"; - pins = "gpio12"; - }; - pinconf { - pins = "gpio12"; - drive-strength = <2>; - bias-disable; - }; - }; -}; - -&smd_rpm_regulators { - vdd_l1_l2_l3-supply = <&pm8916_s3>; - vdd_l4_l5_l6-supply = <&pm8916_s4>; - vdd_l7-supply = <&pm8916_s4>; - - s1 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1300000>; - }; - - s3 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1300000>; - }; - - s4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2100000>; - }; - - l1 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - - l2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - l3 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1287500>; - }; - - l4 { - regulator-min-microvolt = <2050000>; - regulator-max-microvolt = <2050000>; - }; - - l5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l8 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2900000>; - }; - - l9 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - l10 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2800000>; - }; - - l11 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - regulator-allow-set-load; - regulator-system-load = <200000>; - }; - - l12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - l13 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3075000>; - }; - - l14 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - l15 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - l16 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - l17 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - l18 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; -}; - -&spmi_bus { - pm8916@0 { - pon@800 { - volume-down { - compatible = "qcom,pm8941-resin"; - interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>; - bias-pull-up; - linux,code = ; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/qcom/msm8916-samsung-a3u-eur.dts b/sys/gnu/dts/arm64/qcom/msm8916-samsung-a3u-eur.dts deleted file mode 100644 index d10f7ac5089..00000000000 --- a/sys/gnu/dts/arm64/qcom/msm8916-samsung-a3u-eur.dts +++ /dev/null @@ -1,10 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only - -/dts-v1/; - -#include "msm8916-samsung-a2015-common.dtsi" - -/ { - model = "Samsung Galaxy A3U (EUR)"; - compatible = "samsung,a3u-eur", "qcom,msm8916"; -}; diff --git a/sys/gnu/dts/arm64/qcom/msm8916-samsung-a5u-eur.dts b/sys/gnu/dts/arm64/qcom/msm8916-samsung-a5u-eur.dts deleted file mode 100644 index 6629a621139..00000000000 --- a/sys/gnu/dts/arm64/qcom/msm8916-samsung-a5u-eur.dts +++ /dev/null @@ -1,16 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only - -/dts-v1/; - -#include "msm8916-samsung-a2015-common.dtsi" - -/ { - model = "Samsung Galaxy A5U (EUR)"; - compatible = "samsung,a5u-eur", "qcom,msm8916"; -}; - -&pronto { - iris { - compatible = "qcom,wcn3680"; - }; -}; diff --git a/sys/gnu/dts/arm64/qcom/msm8916.dtsi b/sys/gnu/dts/arm64/qcom/msm8916.dtsi deleted file mode 100644 index 9f31064f237..00000000000 --- a/sys/gnu/dts/arm64/qcom/msm8916.dtsi +++ /dev/null @@ -1,1717 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. - */ - -#include -#include -#include -#include -#include - -/ { - interrupt-parent = <&intc>; - - #address-cells = <2>; - #size-cells = <2>; - - aliases { - sdhc1 = &sdhc_1; /* SDC1 eMMC slot */ - sdhc2 = &sdhc_2; /* SDC2 SD card slot */ - }; - - chosen { }; - - memory { - device_type = "memory"; - /* We expect the bootloader to fill in the reg */ - reg = <0 0 0 0>; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - tz-apps@86000000 { - reg = <0x0 0x86000000 0x0 0x300000>; - no-map; - }; - - smem_mem: smem_region@86300000 { - reg = <0x0 0x86300000 0x0 0x100000>; - no-map; - }; - - hypervisor@86400000 { - reg = <0x0 0x86400000 0x0 0x100000>; - no-map; - }; - - tz@86500000 { - reg = <0x0 0x86500000 0x0 0x180000>; - no-map; - }; - - reserved@8668000 { - reg = <0x0 0x86680000 0x0 0x80000>; - no-map; - }; - - rmtfs@86700000 { - compatible = "qcom,rmtfs-mem"; - reg = <0x0 0x86700000 0x0 0xe0000>; - no-map; - - qcom,client-id = <1>; - }; - - rfsa@867e00000 { - reg = <0x0 0x867e0000 0x0 0x20000>; - no-map; - }; - - mpss_mem: mpss@86800000 { - reg = <0x0 0x86800000 0x0 0x2b00000>; - no-map; - }; - - wcnss_mem: wcnss@89300000 { - reg = <0x0 0x89300000 0x0 0x600000>; - no-map; - }; - - venus_mem: venus@89900000 { - reg = <0x0 0x89900000 0x0 0x600000>; - no-map; - }; - - mba_mem: mba@8ea00000 { - no-map; - reg = <0 0x8ea00000 0 0x100000>; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - CPU0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - clocks = <&apcs>; - operating-points-v2 = <&cpu_opp_table>; - #cooling-cells = <2>; - power-domains = <&CPU_PD0>; - power-domain-names = "psci"; - }; - - CPU1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x1>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - clocks = <&apcs>; - operating-points-v2 = <&cpu_opp_table>; - #cooling-cells = <2>; - power-domains = <&CPU_PD1>; - power-domain-names = "psci"; - }; - - CPU2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x2>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - clocks = <&apcs>; - operating-points-v2 = <&cpu_opp_table>; - #cooling-cells = <2>; - power-domains = <&CPU_PD2>; - power-domain-names = "psci"; - }; - - CPU3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x3>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - clocks = <&apcs>; - operating-points-v2 = <&cpu_opp_table>; - #cooling-cells = <2>; - power-domains = <&CPU_PD3>; - power-domain-names = "psci"; - }; - - L2_0: l2-cache { - compatible = "cache"; - cache-level = <2>; - }; - - idle-states { - entry-method = "psci"; - - CPU_SLEEP_0: cpu-sleep-0 { - compatible = "arm,idle-state"; - idle-state-name = "standalone-power-collapse"; - arm,psci-suspend-param = <0x40000002>; - entry-latency-us = <130>; - exit-latency-us = <150>; - min-residency-us = <2000>; - local-timer-stop; - }; - - CLUSTER_RET: cluster-retention { - compatible = "domain-idle-state"; - arm,psci-suspend-param = <0x41000012>; - entry-latency-us = <500>; - exit-latency-us = <500>; - min-residency-us = <2000>; - }; - - CLUSTER_PWRDN: cluster-gdhs { - compatible = "domain-idle-state"; - arm,psci-suspend-param = <0x41000032>; - entry-latency-us = <2000>; - exit-latency-us = <2000>; - min-residency-us = <6000>; - }; - }; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - - CPU_PD0: cpu-pd0 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&CPU_SLEEP_0>; - }; - - CPU_PD1: cpu-pd1 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&CPU_SLEEP_0>; - }; - - CPU_PD2: cpu-pd2 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&CPU_SLEEP_0>; - }; - - CPU_PD3: cpu-pd3 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&CPU_SLEEP_0>; - }; - - CLUSTER_PD: cluster-pd { - #power-domain-cells = <0>; - domain-idle-states = <&CLUSTER_RET>, <&CLUSTER_PWRDN>; - }; - }; - - pmu { - compatible = "arm,cortex-a53-pmu"; - interrupts = ; - }; - - thermal-zones { - cpu0_1-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 5>; - - trips { - cpu0_1_alert0: trip-point@0 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu0_1_crit: cpu_crit { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu0_1_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu2_3-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 4>; - - trips { - cpu2_3_alert0: trip-point@0 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu2_3_crit: cpu_crit { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu2_3_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - gpu-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 2>; - - trips { - gpu_alert0: trip-point@0 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - gpu_crit: gpu_crit { - temperature = <95000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - camera-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 1>; - - trips { - cam_alert0: trip-point@0 { - temperature = <75000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - modem-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 0>; - - trips { - modem_alert0: trip-point@0 { - temperature = <85000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - }; - - cpu_opp_table: cpu_opp_table { - compatible = "operating-points-v2"; - opp-shared; - - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - }; - opp-400000000 { - opp-hz = /bits/ 64 <400000000>; - }; - opp-800000000 { - opp-hz = /bits/ 64 <800000000>; - }; - opp-998400000 { - opp-hz = /bits/ 64 <998400000>; - }; - }; - - gpu_opp_table: opp_table { - compatible = "operating-points-v2"; - - opp-400000000 { - opp-hz = /bits/ 64 <400000000>; - }; - opp-19200000 { - opp-hz = /bits/ 64 <19200000>; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - clocks { - xo_board: xo_board { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <19200000>; - }; - - sleep_clk: sleep_clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - smem { - compatible = "qcom,smem"; - - memory-region = <&smem_mem>; - qcom,rpm-msg-ram = <&rpm_msg_ram>; - - hwlocks = <&tcsr_mutex 3>; - }; - - firmware { - scm: scm { - compatible = "qcom,scm"; - clocks = <&gcc GCC_CRYPTO_CLK>, <&gcc GCC_CRYPTO_AXI_CLK>, <&gcc GCC_CRYPTO_AHB_CLK>; - clock-names = "core", "bus", "iface"; - #reset-cells = <1>; - - qcom,dload-mode = <&tcsr 0x6100>; - }; - }; - - soc: soc { - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0 0xffffffff>; - compatible = "simple-bus"; - - restart@4ab000 { - compatible = "qcom,pshold"; - reg = <0x4ab000 0x4>; - }; - - msmgpio: pinctrl@1000000 { - compatible = "qcom,msm8916-pinctrl"; - reg = <0x1000000 0x300000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gcc: clock-controller@1800000 { - compatible = "qcom,gcc-msm8916"; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - reg = <0x1800000 0x80000>; - }; - - tcsr_mutex_regs: syscon@1905000 { - compatible = "syscon"; - reg = <0x1905000 0x20000>; - }; - - tcsr: syscon@1937000 { - compatible = "qcom,tcsr-msm8916", "syscon"; - reg = <0x1937000 0x30000>; - }; - - tcsr_mutex: hwlock { - compatible = "qcom,tcsr-mutex"; - syscon = <&tcsr_mutex_regs 0 0x1000>; - #hwlock-cells = <1>; - }; - - rpm_msg_ram: memory@60000 { - compatible = "qcom,rpm-msg-ram"; - reg = <0x60000 0x8000>; - }; - - blsp1_uart1: serial@78af000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0x78af000 0x200>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - dmas = <&blsp_dma 1>, <&blsp_dma 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - a53pll: clock@b016000 { - compatible = "qcom,msm8916-a53pll"; - reg = <0xb016000 0x40>; - #clock-cells = <0>; - }; - - apcs: mailbox@b011000 { - compatible = "qcom,msm8916-apcs-kpss-global", "syscon"; - reg = <0xb011000 0x1000>; - #mbox-cells = <1>; - clocks = <&a53pll>, <&gcc GPLL0_VOTE>; - clock-names = "pll", "aux"; - #clock-cells = <0>; - }; - - blsp1_uart2: serial@78b0000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0x78b0000 0x200>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - dmas = <&blsp_dma 3>, <&blsp_dma 2>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - blsp_dma: dma@7884000 { - compatible = "qcom,bam-v1.7.0"; - reg = <0x07884000 0x23000>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "bam_clk"; - #dma-cells = <1>; - qcom,ee = <0>; - status = "disabled"; - }; - - blsp_spi1: spi@78b5000 { - compatible = "qcom,spi-qup-v2.2.1"; - reg = <0x078b5000 0x500>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - dmas = <&blsp_dma 5>, <&blsp_dma 4>; - dma-names = "rx", "tx"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&spi1_default>; - pinctrl-1 = <&spi1_sleep>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - blsp_spi2: spi@78b6000 { - compatible = "qcom,spi-qup-v2.2.1"; - reg = <0x078b6000 0x500>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - dmas = <&blsp_dma 7>, <&blsp_dma 6>; - dma-names = "rx", "tx"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&spi2_default>; - pinctrl-1 = <&spi2_sleep>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - blsp_spi3: spi@78b7000 { - compatible = "qcom,spi-qup-v2.2.1"; - reg = <0x078b7000 0x500>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - dmas = <&blsp_dma 9>, <&blsp_dma 8>; - dma-names = "rx", "tx"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&spi3_default>; - pinctrl-1 = <&spi3_sleep>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - blsp_spi4: spi@78b8000 { - compatible = "qcom,spi-qup-v2.2.1"; - reg = <0x078b8000 0x500>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - dmas = <&blsp_dma 11>, <&blsp_dma 10>; - dma-names = "rx", "tx"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&spi4_default>; - pinctrl-1 = <&spi4_sleep>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - blsp_spi5: spi@78b9000 { - compatible = "qcom,spi-qup-v2.2.1"; - reg = <0x078b9000 0x500>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - dmas = <&blsp_dma 13>, <&blsp_dma 12>; - dma-names = "rx", "tx"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&spi5_default>; - pinctrl-1 = <&spi5_sleep>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - blsp_spi6: spi@78ba000 { - compatible = "qcom,spi-qup-v2.2.1"; - reg = <0x078ba000 0x500>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - dmas = <&blsp_dma 15>, <&blsp_dma 14>; - dma-names = "rx", "tx"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&spi6_default>; - pinctrl-1 = <&spi6_sleep>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - blsp_i2c2: i2c@78b6000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x078b6000 0x500>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; - clock-names = "iface", "core"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c2_default>; - pinctrl-1 = <&i2c2_sleep>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - blsp_i2c4: i2c@78b8000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x078b8000 0x500>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>; - clock-names = "iface", "core"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c4_default>; - pinctrl-1 = <&i2c4_sleep>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - blsp_i2c6: i2c@78ba000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x078ba000 0x500>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>; - clock-names = "iface", "core"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c6_default>; - pinctrl-1 = <&i2c6_sleep>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - lpass: lpass@7708000 { - status = "disabled"; - compatible = "qcom,lpass-cpu-apq8016"; - clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>, - <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>, - <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>, - <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>, - <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>, - <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>, - <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>; - - clock-names = "ahbix-clk", - "pcnoc-mport-clk", - "pcnoc-sway-clk", - "mi2s-bit-clk0", - "mi2s-bit-clk1", - "mi2s-bit-clk2", - "mi2s-bit-clk3"; - #sound-dai-cells = <1>; - - interrupts = <0 160 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "lpass-irq-lpaif"; - reg = <0x07708000 0x10000>; - reg-names = "lpass-lpaif"; - }; - - lpass_codec: codec{ - compatible = "qcom,msm8916-wcd-digital-codec"; - reg = <0x0771c000 0x400>; - clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>, - <&gcc GCC_CODEC_DIGCODEC_CLK>; - clock-names = "ahbix-clk", "mclk"; - #sound-dai-cells = <1>; - }; - - sdhc_1: sdhci@7824000 { - compatible = "qcom,sdhci-msm-v4"; - reg = <0x07824900 0x11c>, <0x07824000 0x800>; - reg-names = "hc_mem", "core_mem"; - - interrupts = <0 123 IRQ_TYPE_LEVEL_HIGH>, <0 138 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC1_APPS_CLK>, - <&gcc GCC_SDCC1_AHB_CLK>, - <&xo_board>; - clock-names = "core", "iface", "xo"; - mmc-ddr-1_8v; - bus-width = <8>; - non-removable; - status = "disabled"; - }; - - sdhc_2: sdhci@7864000 { - compatible = "qcom,sdhci-msm-v4"; - reg = <0x07864900 0x11c>, <0x07864000 0x800>; - reg-names = "hc_mem", "core_mem"; - - interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>, <0 221 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC2_APPS_CLK>, - <&gcc GCC_SDCC2_AHB_CLK>, - <&xo_board>; - clock-names = "core", "iface", "xo"; - bus-width = <4>; - status = "disabled"; - }; - - otg: usb@78d9000 { - compatible = "qcom,ci-hdrc"; - reg = <0x78d9000 0x200>, - <0x78d9200 0x200>; - interrupts = , - ; - clocks = <&gcc GCC_USB_HS_AHB_CLK>, - <&gcc GCC_USB_HS_SYSTEM_CLK>; - clock-names = "iface", "core"; - assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>; - assigned-clock-rates = <80000000>; - resets = <&gcc GCC_USB_HS_BCR>; - reset-names = "core"; - phy_type = "ulpi"; - dr_mode = "otg"; - ahb-burst-config = <0>; - phy-names = "usb-phy"; - phys = <&usb_hs_phy>; - status = "disabled"; - #reset-cells = <1>; - - ulpi { - usb_hs_phy: phy { - compatible = "qcom,usb-hs-phy-msm8916", - "qcom,usb-hs-phy"; - #phy-cells = <0>; - clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>; - clock-names = "ref", "sleep"; - resets = <&gcc GCC_USB2A_PHY_BCR>, <&otg 0>; - reset-names = "phy", "por"; - qcom,init-seq = /bits/ 8 <0x0 0x44 - 0x1 0x6b 0x2 0x24 0x3 0x13>; - }; - }; - }; - - intc: interrupt-controller@b000000 { - compatible = "qcom,msm-qgic2"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>; - }; - - timer@b020000 { - #address-cells = <1>; - #size-cells = <1>; - ranges; - compatible = "arm,armv7-timer-mem"; - reg = <0xb020000 0x1000>; - clock-frequency = <19200000>; - - frame@b021000 { - frame-number = <0>; - interrupts = , - ; - reg = <0xb021000 0x1000>, - <0xb022000 0x1000>; - }; - - frame@b023000 { - frame-number = <1>; - interrupts = ; - reg = <0xb023000 0x1000>; - status = "disabled"; - }; - - frame@b024000 { - frame-number = <2>; - interrupts = ; - reg = <0xb024000 0x1000>; - status = "disabled"; - }; - - frame@b025000 { - frame-number = <3>; - interrupts = ; - reg = <0xb025000 0x1000>; - status = "disabled"; - }; - - frame@b026000 { - frame-number = <4>; - interrupts = ; - reg = <0xb026000 0x1000>; - status = "disabled"; - }; - - frame@b027000 { - frame-number = <5>; - interrupts = ; - reg = <0xb027000 0x1000>; - status = "disabled"; - }; - - frame@b028000 { - frame-number = <6>; - interrupts = ; - reg = <0xb028000 0x1000>; - status = "disabled"; - }; - }; - - spmi_bus: spmi@200f000 { - compatible = "qcom,spmi-pmic-arb"; - reg = <0x200f000 0x001000>, - <0x2400000 0x400000>, - <0x2c00000 0x400000>, - <0x3800000 0x200000>, - <0x200a000 0x002100>; - reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; - interrupt-names = "periph_irq"; - interrupts = ; - qcom,ee = <0>; - qcom,channel = <0>; - #address-cells = <2>; - #size-cells = <0>; - interrupt-controller; - #interrupt-cells = <4>; - }; - - rng@22000 { - compatible = "qcom,prng"; - reg = <0x00022000 0x200>; - clocks = <&gcc GCC_PRNG_AHB_CLK>; - clock-names = "core"; - }; - - qfprom: qfprom@5c000 { - compatible = "qcom,qfprom"; - reg = <0x5c000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - tsens_caldata: caldata@d0 { - reg = <0xd0 0x8>; - }; - tsens_calsel: calsel@ec { - reg = <0xec 0x4>; - }; - }; - - tsens: thermal-sensor@4a9000 { - compatible = "qcom,msm8916-tsens"; - reg = <0x4a9000 0x1000>, /* TM */ - <0x4a8000 0x1000>; /* SROT */ - nvmem-cells = <&tsens_caldata>, <&tsens_calsel>; - nvmem-cell-names = "calib", "calib_sel"; - #qcom,sensors = <5>; - interrupts = ; - interrupt-names = "uplow"; - #thermal-sensor-cells = <1>; - }; - - apps_iommu: iommu@1ef0000 { - #address-cells = <1>; - #size-cells = <1>; - #iommu-cells = <1>; - compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1"; - ranges = <0 0x1e20000 0x40000>; - reg = <0x1ef0000 0x3000>; - clocks = <&gcc GCC_SMMU_CFG_CLK>, - <&gcc GCC_APSS_TCU_CLK>; - clock-names = "iface", "bus"; - qcom,iommu-secure-id = <17>; - - // vfe: - iommu-ctx@3000 { - compatible = "qcom,msm-iommu-v1-sec"; - reg = <0x3000 0x1000>; - interrupts = ; - }; - - // mdp_0: - iommu-ctx@4000 { - compatible = "qcom,msm-iommu-v1-ns"; - reg = <0x4000 0x1000>; - interrupts = ; - }; - - // venus_ns: - iommu-ctx@5000 { - compatible = "qcom,msm-iommu-v1-sec"; - reg = <0x5000 0x1000>; - interrupts = ; - }; - }; - - gpu_iommu: iommu@1f08000 { - #address-cells = <1>; - #size-cells = <1>; - #iommu-cells = <1>; - compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1"; - ranges = <0 0x1f08000 0x10000>; - clocks = <&gcc GCC_SMMU_CFG_CLK>, - <&gcc GCC_GFX_TCU_CLK>; - clock-names = "iface", "bus"; - qcom,iommu-secure-id = <18>; - - // gfx3d_user: - iommu-ctx@1000 { - compatible = "qcom,msm-iommu-v1-ns"; - reg = <0x1000 0x1000>; - interrupts = ; - }; - - // gfx3d_priv: - iommu-ctx@2000 { - compatible = "qcom,msm-iommu-v1-ns"; - reg = <0x2000 0x1000>; - interrupts = ; - }; - }; - - gpu@1c00000 { - compatible = "qcom,adreno-306.0", "qcom,adreno"; - reg = <0x01c00000 0x20000>; - reg-names = "kgsl_3d0_reg_memory"; - interrupts = ; - interrupt-names = "kgsl_3d0_irq"; - clock-names = - "core", - "iface", - "mem", - "mem_iface", - "alt_mem_iface", - "gfx3d"; - clocks = - <&gcc GCC_OXILI_GFX3D_CLK>, - <&gcc GCC_OXILI_AHB_CLK>, - <&gcc GCC_OXILI_GMEM_CLK>, - <&gcc GCC_BIMC_GFX_CLK>, - <&gcc GCC_BIMC_GPU_CLK>, - <&gcc GFX3D_CLK_SRC>; - power-domains = <&gcc OXILI_GDSC>; - operating-points-v2 = <&gpu_opp_table>; - iommus = <&gpu_iommu 1>, <&gpu_iommu 2>; - }; - - mdss: mdss@1a00000 { - compatible = "qcom,mdss"; - reg = <0x1a00000 0x1000>, - <0x1ac8000 0x3000>; - reg-names = "mdss_phys", "vbif_phys"; - - power-domains = <&gcc MDSS_GDSC>; - - clocks = <&gcc GCC_MDSS_AHB_CLK>, - <&gcc GCC_MDSS_AXI_CLK>, - <&gcc GCC_MDSS_VSYNC_CLK>; - clock-names = "iface", - "bus", - "vsync"; - - interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>; - - interrupt-controller; - #interrupt-cells = <1>; - - #address-cells = <1>; - #size-cells = <1>; - ranges; - - mdp: mdp@1a01000 { - compatible = "qcom,mdp5"; - reg = <0x1a01000 0x89000>; - reg-names = "mdp_phys"; - - interrupt-parent = <&mdss>; - interrupts = <0 0>; - - clocks = <&gcc GCC_MDSS_AHB_CLK>, - <&gcc GCC_MDSS_AXI_CLK>, - <&gcc GCC_MDSS_MDP_CLK>, - <&gcc GCC_MDSS_VSYNC_CLK>; - clock-names = "iface", - "bus", - "core", - "vsync"; - - iommus = <&apps_iommu 4>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - mdp5_intf1_out: endpoint { - remote-endpoint = <&dsi0_in>; - }; - }; - }; - }; - - dsi0: dsi@1a98000 { - compatible = "qcom,mdss-dsi-ctrl"; - reg = <0x1a98000 0x25c>; - reg-names = "dsi_ctrl"; - - interrupt-parent = <&mdss>; - interrupts = <4 0>; - - assigned-clocks = <&gcc BYTE0_CLK_SRC>, - <&gcc PCLK0_CLK_SRC>; - assigned-clock-parents = <&dsi_phy0 0>, - <&dsi_phy0 1>; - - clocks = <&gcc GCC_MDSS_MDP_CLK>, - <&gcc GCC_MDSS_AHB_CLK>, - <&gcc GCC_MDSS_AXI_CLK>, - <&gcc GCC_MDSS_BYTE0_CLK>, - <&gcc GCC_MDSS_PCLK0_CLK>, - <&gcc GCC_MDSS_ESC0_CLK>; - clock-names = "mdp_core", - "iface", - "bus", - "byte", - "pixel", - "core"; - phys = <&dsi_phy0>; - phy-names = "dsi-phy"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dsi0_in: endpoint { - remote-endpoint = <&mdp5_intf1_out>; - }; - }; - - port@1 { - reg = <1>; - dsi0_out: endpoint { - }; - }; - }; - }; - - dsi_phy0: dsi-phy@1a98300 { - compatible = "qcom,dsi-phy-28nm-lp"; - reg = <0x1a98300 0xd4>, - <0x1a98500 0x280>, - <0x1a98780 0x30>; - reg-names = "dsi_pll", - "dsi_phy", - "dsi_phy_regulator"; - - #clock-cells = <1>; - #phy-cells = <0>; - - clocks = <&gcc GCC_MDSS_AHB_CLK>, - <&xo_board>; - clock-names = "iface", "ref"; - }; - }; - - - hexagon@4080000 { - compatible = "qcom,q6v5-pil"; - reg = <0x04080000 0x100>, - <0x04020000 0x040>; - - reg-names = "qdsp6", "rmb"; - - interrupts-extended = <&intc 0 24 1>, - <&hexagon_smp2p_in 0 0>, - <&hexagon_smp2p_in 1 0>, - <&hexagon_smp2p_in 2 0>, - <&hexagon_smp2p_in 3 0>; - interrupt-names = "wdog", "fatal", "ready", - "handover", "stop-ack"; - - clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, - <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, - <&gcc GCC_BOOT_ROM_AHB_CLK>, - <&xo_board>; - clock-names = "iface", "bus", "mem", "xo"; - - qcom,smem-states = <&hexagon_smp2p_out 0>; - qcom,smem-state-names = "stop"; - - resets = <&scm 0>; - reset-names = "mss_restart"; - - cx-supply = <&pm8916_s1>; - mx-supply = <&pm8916_l3>; - pll-supply = <&pm8916_l7>; - - qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>; - - status = "disabled"; - - mba { - memory-region = <&mba_mem>; - }; - - mpss { - memory-region = <&mpss_mem>; - }; - - smd-edge { - interrupts = <0 25 IRQ_TYPE_EDGE_RISING>; - - qcom,smd-edge = <0>; - qcom,ipc = <&apcs 8 12>; - qcom,remote-pid = <1>; - - label = "hexagon"; - }; - }; - - pronto: wcnss@a21b000 { - compatible = "qcom,pronto-v2-pil", "qcom,pronto"; - reg = <0x0a204000 0x2000>, <0x0a202000 0x1000>, <0x0a21b000 0x3000>; - reg-names = "ccu", "dxe", "pmu"; - - memory-region = <&wcnss_mem>; - - interrupts-extended = <&intc 0 149 IRQ_TYPE_EDGE_RISING>, - <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, - <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, - <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; - - vddmx-supply = <&pm8916_l3>; - vddpx-supply = <&pm8916_l7>; - - qcom,state = <&wcnss_smp2p_out 0>; - qcom,state-names = "stop"; - - pinctrl-names = "default"; - pinctrl-0 = <&wcnss_pin_a>; - - status = "disabled"; - - iris { - compatible = "qcom,wcn3620"; - - clocks = <&rpmcc RPM_SMD_RF_CLK2>; - clock-names = "xo"; - - vddxo-supply = <&pm8916_l7>; - vddrfa-supply = <&pm8916_s3>; - vddpa-supply = <&pm8916_l9>; - vdddig-supply = <&pm8916_l5>; - }; - - smd-edge { - interrupts = <0 142 1>; - - qcom,ipc = <&apcs 8 17>; - qcom,smd-edge = <6>; - qcom,remote-pid = <4>; - - label = "pronto"; - - wcnss { - compatible = "qcom,wcnss"; - qcom,smd-channels = "WCNSS_CTRL"; - - qcom,mmio = <&pronto>; - - bt { - compatible = "qcom,wcnss-bt"; - }; - - wifi { - compatible = "qcom,wcnss-wlan"; - - interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>, - <0 146 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "tx", "rx"; - - qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>; - qcom,smem-state-names = "tx-enable", "tx-rings-empty"; - }; - }; - }; - }; - - tpiu@820000 { - compatible = "arm,coresight-tpiu", "arm,primecell"; - reg = <0x820000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - in-ports { - port { - tpiu_in: endpoint { - remote-endpoint = <&replicator_out1>; - }; - }; - }; - }; - - funnel@821000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0x821000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - /* - * Not described input ports: - * 0 - connected to Resource and Power Manger CPU ETM - * 1 - not-connected - * 2 - connected to Modem CPU ETM - * 3 - not-connected - * 5 - not-connected - * 6 - connected trought funnel to Wireless CPU ETM - * 7 - connected to STM component - */ - - port@4 { - reg = <4>; - funnel0_in4: endpoint { - remote-endpoint = <&funnel1_out>; - }; - }; - }; - - out-ports { - port { - funnel0_out: endpoint { - remote-endpoint = <&etf_in>; - }; - }; - }; - }; - - replicator@824000 { - compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; - reg = <0x824000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - out-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - replicator_out0: endpoint { - remote-endpoint = <&etr_in>; - }; - }; - port@1 { - reg = <1>; - replicator_out1: endpoint { - remote-endpoint = <&tpiu_in>; - }; - }; - }; - - in-ports { - port { - replicator_in: endpoint { - remote-endpoint = <&etf_out>; - }; - }; - }; - }; - - etf@825000 { - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0x825000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - in-ports { - port { - etf_in: endpoint { - remote-endpoint = <&funnel0_out>; - }; - }; - }; - - out-ports { - port { - etf_out: endpoint { - remote-endpoint = <&replicator_in>; - }; - }; - }; - }; - - etr@826000 { - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0x826000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - in-ports { - port { - etr_in: endpoint { - remote-endpoint = <&replicator_out0>; - }; - }; - }; - }; - - funnel@841000 { /* APSS funnel only 4 inputs are used */ - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0x841000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - funnel1_in0: endpoint { - remote-endpoint = <&etm0_out>; - }; - }; - port@1 { - reg = <1>; - funnel1_in1: endpoint { - remote-endpoint = <&etm1_out>; - }; - }; - port@2 { - reg = <2>; - funnel1_in2: endpoint { - remote-endpoint = <&etm2_out>; - }; - }; - port@3 { - reg = <3>; - funnel1_in3: endpoint { - remote-endpoint = <&etm3_out>; - }; - }; - }; - - out-ports { - port { - funnel1_out: endpoint { - remote-endpoint = <&funnel0_in4>; - }; - }; - }; - }; - - debug@850000 { - compatible = "arm,coresight-cpu-debug","arm,primecell"; - reg = <0x850000 0x1000>; - clocks = <&rpmcc RPM_QDSS_CLK>; - clock-names = "apb_pclk"; - cpu = <&CPU0>; - }; - - debug@852000 { - compatible = "arm,coresight-cpu-debug","arm,primecell"; - reg = <0x852000 0x1000>; - clocks = <&rpmcc RPM_QDSS_CLK>; - clock-names = "apb_pclk"; - cpu = <&CPU1>; - }; - - debug@854000 { - compatible = "arm,coresight-cpu-debug","arm,primecell"; - reg = <0x854000 0x1000>; - clocks = <&rpmcc RPM_QDSS_CLK>; - clock-names = "apb_pclk"; - cpu = <&CPU2>; - }; - - debug@856000 { - compatible = "arm,coresight-cpu-debug","arm,primecell"; - reg = <0x856000 0x1000>; - clocks = <&rpmcc RPM_QDSS_CLK>; - clock-names = "apb_pclk"; - cpu = <&CPU3>; - }; - - etm@85c000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0x85c000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - cpu = <&CPU0>; - - out-ports { - port { - etm0_out: endpoint { - remote-endpoint = <&funnel1_in0>; - }; - }; - }; - }; - - etm@85d000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0x85d000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - cpu = <&CPU1>; - - out-ports { - port { - etm1_out: endpoint { - remote-endpoint = <&funnel1_in1>; - }; - }; - }; - }; - - etm@85e000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0x85e000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - cpu = <&CPU2>; - - out-ports { - port { - etm2_out: endpoint { - remote-endpoint = <&funnel1_in2>; - }; - }; - }; - }; - - etm@85f000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0x85f000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - cpu = <&CPU3>; - - out-ports { - port { - etm3_out: endpoint { - remote-endpoint = <&funnel1_in3>; - }; - }; - }; - }; - - venus: video-codec@1d00000 { - compatible = "qcom,msm8916-venus"; - reg = <0x01d00000 0xff000>; - interrupts = ; - power-domains = <&gcc VENUS_GDSC>; - clocks = <&gcc GCC_VENUS0_VCODEC0_CLK>, - <&gcc GCC_VENUS0_AHB_CLK>, - <&gcc GCC_VENUS0_AXI_CLK>; - clock-names = "core", "iface", "bus"; - iommus = <&apps_iommu 5>; - memory-region = <&venus_mem>; - status = "okay"; - - video-decoder { - compatible = "venus-decoder"; - }; - - video-encoder { - compatible = "venus-encoder"; - }; - }; - - camss: camss@1b00000 { - compatible = "qcom,msm8916-camss"; - reg = <0x1b0ac00 0x200>, - <0x1b00030 0x4>, - <0x1b0b000 0x200>, - <0x1b00038 0x4>, - <0x1b08000 0x100>, - <0x1b08400 0x100>, - <0x1b0a000 0x500>, - <0x1b00020 0x10>, - <0x1b10000 0x1000>; - reg-names = "csiphy0", - "csiphy0_clk_mux", - "csiphy1", - "csiphy1_clk_mux", - "csid0", - "csid1", - "ispif", - "csi_clk_mux", - "vfe0"; - interrupts = , - , - , - , - , - ; - interrupt-names = "csiphy0", - "csiphy1", - "csid0", - "csid1", - "ispif", - "vfe0"; - power-domains = <&gcc VFE_GDSC>; - clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, - <&gcc GCC_CAMSS_ISPIF_AHB_CLK>, - <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>, - <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>, - <&gcc GCC_CAMSS_CSI0_AHB_CLK>, - <&gcc GCC_CAMSS_CSI0_CLK>, - <&gcc GCC_CAMSS_CSI0PHY_CLK>, - <&gcc GCC_CAMSS_CSI0PIX_CLK>, - <&gcc GCC_CAMSS_CSI0RDI_CLK>, - <&gcc GCC_CAMSS_CSI1_AHB_CLK>, - <&gcc GCC_CAMSS_CSI1_CLK>, - <&gcc GCC_CAMSS_CSI1PHY_CLK>, - <&gcc GCC_CAMSS_CSI1PIX_CLK>, - <&gcc GCC_CAMSS_CSI1RDI_CLK>, - <&gcc GCC_CAMSS_AHB_CLK>, - <&gcc GCC_CAMSS_VFE0_CLK>, - <&gcc GCC_CAMSS_CSI_VFE0_CLK>, - <&gcc GCC_CAMSS_VFE_AHB_CLK>, - <&gcc GCC_CAMSS_VFE_AXI_CLK>; - clock-names = "top_ahb", - "ispif_ahb", - "csiphy0_timer", - "csiphy1_timer", - "csi0_ahb", - "csi0", - "csi0_phy", - "csi0_pix", - "csi0_rdi", - "csi1_ahb", - "csi1", - "csi1_phy", - "csi1_pix", - "csi1_rdi", - "ahb", - "vfe0", - "csi_vfe0", - "vfe_ahb", - "vfe_axi"; - vdda-supply = <&pm8916_l2>; - iommus = <&apps_iommu 3>; - status = "disabled"; - ports { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - }; - - smd { - compatible = "qcom,smd"; - - rpm { - interrupts = ; - qcom,ipc = <&apcs 8 0>; - qcom,smd-edge = <15>; - - rpm_requests { - compatible = "qcom,rpm-msm8916"; - qcom,smd-channels = "rpm_requests"; - - rpmcc: qcom,rpmcc { - compatible = "qcom,rpmcc-msm8916"; - #clock-cells = <1>; - }; - - smd_rpm_regulators: pm8916-regulators { - compatible = "qcom,rpm-pm8916-regulators"; - - pm8916_s1: s1 {}; - pm8916_s3: s3 {}; - pm8916_s4: s4 {}; - - pm8916_l1: l1 {}; - pm8916_l2: l2 {}; - pm8916_l3: l3 {}; - pm8916_l4: l4 {}; - pm8916_l5: l5 {}; - pm8916_l6: l6 {}; - pm8916_l7: l7 {}; - pm8916_l8: l8 {}; - pm8916_l9: l9 {}; - pm8916_l10: l10 {}; - pm8916_l11: l11 {}; - pm8916_l12: l12 {}; - pm8916_l13: l13 {}; - pm8916_l14: l14 {}; - pm8916_l15: l15 {}; - pm8916_l16: l16 {}; - pm8916_l17: l17 {}; - pm8916_l18: l18 {}; - }; - }; - }; - }; - - hexagon-smp2p { - compatible = "qcom,smp2p"; - qcom,smem = <435>, <428>; - - interrupts = <0 27 IRQ_TYPE_EDGE_RISING>; - - qcom,ipc = <&apcs 8 14>; - - qcom,local-pid = <0>; - qcom,remote-pid = <1>; - - hexagon_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; - - #qcom,smem-state-cells = <1>; - }; - - hexagon_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - wcnss-smp2p { - compatible = "qcom,smp2p"; - qcom,smem = <451>, <431>; - - interrupts = <0 143 IRQ_TYPE_EDGE_RISING>; - - qcom,ipc = <&apcs 8 18>; - - qcom,local-pid = <0>; - qcom,remote-pid = <4>; - - wcnss_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; - - #qcom,smem-state-cells = <1>; - }; - - wcnss_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - smsm { - compatible = "qcom,smsm"; - - #address-cells = <1>; - #size-cells = <0>; - - qcom,ipc-1 = <&apcs 8 13>; - qcom,ipc-3 = <&apcs 8 19>; - - apps_smsm: apps@0 { - reg = <0>; - - #qcom,smem-state-cells = <1>; - }; - - hexagon_smsm: hexagon@1 { - reg = <1>; - interrupts = <0 26 IRQ_TYPE_EDGE_RISING>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - wcnss_smsm: wcnss@6 { - reg = <6>; - interrupts = <0 144 IRQ_TYPE_EDGE_RISING>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - }; -}; - -#include "msm8916-pins.dtsi" diff --git a/sys/gnu/dts/arm64/qcom/msm8992-bullhead-rev-101.dts b/sys/gnu/dts/arm64/qcom/msm8992-bullhead-rev-101.dts deleted file mode 100644 index 32670d5afdd..00000000000 --- a/sys/gnu/dts/arm64/qcom/msm8992-bullhead-rev-101.dts +++ /dev/null @@ -1,50 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* Copyright (c) 2015, LGE Inc. All rights reserved. - * Copyright (c) 2016, The Linux Foundation. All rights reserved. - */ - -/dts-v1/; - -#include "msm8992.dtsi" - -/ { - model = "LG Nexus 5X"; - compatible = "lg,bullhead", "qcom,msm8992"; - /* required for bootloader to select correct board */ - qcom,board-id = <0xb64 0>; - qcom,pmic-id = <0x10009 0x1000A 0x0 0x0>; - - aliases { - serial0 = &blsp1_uart2; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - soc { - serial@f991e000 { - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp1_uart2_default>; - pinctrl-1 = <&blsp1_uart2_sleep>; - }; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - ramoops@1ff00000 { - compatible = "ramoops"; - reg = <0x0 0x1ff00000 0x0 0x40000>; - console-size = <0x10000>; - record-size = <0x10000>; - ftrace-size = <0x10000>; - pmsg-size = <0x20000>; - }; - }; -}; - -#include "msm8994-smd-rpm.dtsi" diff --git a/sys/gnu/dts/arm64/qcom/msm8992-pins.dtsi b/sys/gnu/dts/arm64/qcom/msm8992-pins.dtsi deleted file mode 100644 index c543c718c22..00000000000 --- a/sys/gnu/dts/arm64/qcom/msm8992-pins.dtsi +++ /dev/null @@ -1,90 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. - */ - -&msmgpio { - blsp1_uart2_default: blsp1_uart2_default { - pinmux { - function = "blsp_uart2"; - pins = "gpio4", "gpio5"; - }; - pinconf { - pins = "gpio4", "gpio5"; - drive-strength = <16>; - bias-disable; - }; - }; - - blsp1_uart2_sleep: blsp1_uart2_sleep { - pinmux { - function = "gpio"; - pins = "gpio4", "gpio5"; - }; - pinconf { - pins = "gpio4", "gpio5"; - drive-strength = <2>; - bias-pull-down; - }; - }; - - /* 0-3 for sdc1 4-6 for sdc2 */ - /* Order of pins */ - /* SDC1: CLK -> 0, CMD -> 1, DATA -> 2, RCLK -> 3 */ - /* SDC2: CLK -> 4, CMD -> 5, DATA -> 6 */ - sdc1_clk_on: clk-on { - pinconf { - pins = "sdc1_clk"; - bias-disable = <0>; /* No pull */ - drive-strength = <16>; /* 16mA */ - }; - }; - - sdc1_clk_off: clk-off { - pinconf { - pins = "sdc1_clk"; - bias-disable = <0>; /* No pull */ - drive-strength = <2>; /* 2mA */ - }; - }; - - sdc1_cmd_on: cmd-on { - pinconf { - pins = "sdc1_cmd"; - bias-pull-up; - drive-strength = <8>; - }; - }; - - sdc1_cmd_off: cmd-off { - pinconf { - pins = "sdc1_cmd"; - bias-pull-up = <0x3>; /* same as 3.10 ?? */ - drive-strength = <2>; /* 2mA */ - }; - }; - - sdc1_data_on: data-on { - pinconf { - pins = "sdc1_data"; - bias-pull-up; - drive-strength = <8>; /* 8mA */ - }; - }; - - sdc1_data_off: data-off { - pinconf { - pins = "sdc1_data"; - bias-pull-up; - drive-strength = <2>; - }; - }; - - sdc1_rclk_on: rclk-on { - bias-pull-down; /* pull down */ - }; - - sdc1_rclk_off: rclk-off { - bias-pull-down; /* pull down */ - }; -}; diff --git a/sys/gnu/dts/arm64/qcom/msm8992.dtsi b/sys/gnu/dts/arm64/qcom/msm8992.dtsi deleted file mode 100644 index 8be60c08a9a..00000000000 --- a/sys/gnu/dts/arm64/qcom/msm8992.dtsi +++ /dev/null @@ -1,314 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. - */ - -#include -#include - -/ { - model = "Qualcomm Technologies, Inc. MSM 8992"; - compatible = "qcom,msm8992"; - // msm-id needed by bootloader for selecting correct blob - qcom,msm-id = <251 0>, <252 0>; - interrupt-parent = <&intc>; - - #address-cells = <2>; - #size-cells = <2>; - - chosen { }; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - cpu-map { - cluster0 { - core0 { - cpu = <&CPU0>; - }; - }; - }; - - CPU0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x0>; - next-level-cache = <&L2_0>; - L2_0: l2-cache { - compatible = "cache"; - cache-level = <2>; - }; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - xo_board: xo_board { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <19200000>; - }; - - sleep_clk: sleep_clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - - vreg_vph_pwr: vreg-vph-pwr { - compatible = "regulator-fixed"; - status = "okay"; - regulator-name = "vph-pwr"; - - regulator-min-microvolt = <3600000>; - regulator-max-microvolt = <3600000>; - - regulator-always-on; - }; - - sfpb_mutex: hwmutex { - compatible = "qcom,sfpb-mutex"; - syscon = <&sfpb_mutex_regs 0x0 0x100>; - #hwlock-cells = <1>; - }; - - smem { - compatible = "qcom,smem"; - memory-region = <&smem_region>; - qcom,rpm-msg-ram = <&rpm_msg_ram>; - hwlocks = <&sfpb_mutex 3>; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0 0xffffffff>; - compatible = "simple-bus"; - - intc: interrupt-controller@f9000000 { - compatible = "qcom,msm-qgic2"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0xf9000000 0x1000>, - <0xf9002000 0x1000>; - }; - - apcs: syscon@f900d000 { - compatible = "syscon"; - reg = <0xf900d000 0x2000>; - }; - - timer@f9020000 { - #address-cells = <1>; - #size-cells = <1>; - ranges; - compatible = "arm,armv7-timer-mem"; - reg = <0xf9020000 0x1000>; - - frame@f9021000 { - frame-number = <0>; - interrupts = , - ; - reg = <0xf9021000 0x1000>, - <0xf9022000 0x1000>; - }; - - frame@f9023000 { - frame-number = <1>; - interrupts = ; - reg = <0xf9023000 0x1000>; - status = "disabled"; - }; - - frame@f9024000 { - frame-number = <2>; - interrupts = ; - reg = <0xf9024000 0x1000>; - status = "disabled"; - }; - - frame@f9025000 { - frame-number = <3>; - interrupts = ; - reg = <0xf9025000 0x1000>; - status = "disabled"; - }; - - frame@f9026000 { - frame-number = <4>; - interrupts = ; - reg = <0xf9026000 0x1000>; - status = "disabled"; - }; - - frame@f9027000 { - frame-number = <5>; - interrupts = ; - reg = <0xf9027000 0x1000>; - status = "disabled"; - }; - - frame@f9028000 { - frame-number = <6>; - interrupts = ; - reg = <0xf9028000 0x1000>; - status = "disabled"; - }; - }; - - restart@fc4ab000 { - compatible = "qcom,pshold"; - reg = <0xfc4ab000 0x4>; - }; - - msmgpio: pinctrl@fd510000 { - compatible = "qcom,msm8994-pinctrl"; - reg = <0xfd510000 0x4000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - blsp1_uart2: serial@f991e000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0xf991e000 0x1000>; - interrupts = ; - status = "disabled"; - clock-names = "core", "iface"; - clocks = <&clock_gcc GCC_BLSP1_UART2_APPS_CLK>, - <&clock_gcc GCC_BLSP1_AHB_CLK>; - }; - - clock_gcc: clock-controller@fc400000 { - compatible = "qcom,gcc-msm8994"; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - reg = <0xfc400000 0x2000>; - }; - - sdhci1: mmc@f9824900 { - compatible = "qcom,sdhci-msm-v4"; - reg = <0xf9824900 0x1a0>, <0xf9824000 0x800>; - reg-names = "hc_mem", "core_mem"; - - interrupts = , - ; - interrupt-names = "hc_irq", "pwr_irq"; - - clocks = <&clock_gcc GCC_SDCC1_APPS_CLK>, - <&clock_gcc GCC_SDCC1_AHB_CLK>; - clock-names = "core", "iface"; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on - &sdc1_rclk_on>; - pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off - &sdc1_rclk_off>; - - regulator-always-on; - bus-width = <8>; - mmc-hs400-1_8v; - status = "okay"; - }; - - rpm_msg_ram: memory@fc428000 { - compatible = "qcom,rpm-msg-ram"; - reg = <0xfc428000 0x4000>; - }; - - sfpb_mutex_regs: syscon@fd484000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "syscon"; - reg = <0xfd484000 0x400>; - }; - }; - - memory { - device_type = "memory"; - reg = <0 0 0 0>; // bootloader will update - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - smem_region: smem@6a00000 { - reg = <0x0 0x6a00000 0x0 0x200000>; - no-map; - }; - }; - - smd_rpm: smd { - compatible = "qcom,smd"; - rpm { - interrupts = ; - qcom,ipc = <&apcs 8 0>; - qcom,smd-edge = <15>; - qcom,local-pid = <0>; - qcom,remote-pid = <6>; - - rpm-requests { - compatible = "qcom,rpm-msm8994"; - qcom,smd-channels = "rpm_requests"; - - pm8994-regulators { - compatible = "qcom,rpm-pm8994-regulators"; - - pm8994_s1: s1 {}; - pm8994_s2: s2 {}; - pm8994_s3: s3 {}; - pm8994_s4: s4 {}; - pm8994_s5: s5 {}; - pm8994_s6: s6 {}; - pm8994_s7: s7 {}; - - pm8994_l1: l1 {}; - pm8994_l2: l2 {}; - pm8994_l3: l3 {}; - pm8994_l4: l4 {}; - pm8994_l6: l6 {}; - pm8994_l8: l8 {}; - pm8994_l9: l9 {}; - pm8994_l10: l10 {}; - pm8994_l11: l11 {}; - pm8994_l12: l12 {}; - pm8994_l13: l13 {}; - pm8994_l14: l14 {}; - pm8994_l15: l15 {}; - pm8994_l16: l16 {}; - pm8994_l17: l17 {}; - pm8994_l18: l18 {}; - pm8994_l19: l19 {}; - pm8994_l20: l20 {}; - pm8994_l21: l21 {}; - pm8994_l22: l22 {}; - pm8994_l23: l23 {}; - pm8994_l24: l24 {}; - pm8994_l25: l25 {}; - pm8994_l26: l26 {}; - pm8994_l27: l27 {}; - pm8994_l28: l28 {}; - pm8994_l29: l29 {}; - pm8994_l30: l30 {}; - pm8994_l31: l31 {}; - pm8994_l32: l32 {}; - - pm8994_lvs1: lvs1 {}; - pm8994_lvs2: lvs2 {}; - }; - }; - }; - }; -}; - -#include "msm8992-pins.dtsi" diff --git a/sys/gnu/dts/arm64/qcom/msm8994-angler-rev-101.dts b/sys/gnu/dts/arm64/qcom/msm8994-angler-rev-101.dts deleted file mode 100644 index a5f9a6ab512..00000000000 --- a/sys/gnu/dts/arm64/qcom/msm8994-angler-rev-101.dts +++ /dev/null @@ -1,32 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* Copyright (c) 2015, Huawei Inc. All rights reserved. - * Copyright (c) 2016, The Linux Foundation. All rights reserved. - */ - -/dts-v1/; - -#include "msm8994.dtsi" - -/ { - model = "Huawei Nexus 6P"; - compatible = "huawei,angler", "qcom,msm8994"; - /* required for bootloader to select correct board */ - qcom,board-id = <8026 0>; - - aliases { - serial0 = &blsp1_uart2; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - soc { - serial@f991e000 { - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp1_uart2_default>; - pinctrl-1 = <&blsp1_uart2_sleep>; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/qcom/msm8994-pins.dtsi b/sys/gnu/dts/arm64/qcom/msm8994-pins.dtsi deleted file mode 100644 index 2e118d967f5..00000000000 --- a/sys/gnu/dts/arm64/qcom/msm8994-pins.dtsi +++ /dev/null @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. - */ - -&msmgpio { - blsp1_uart2_default: blsp1_uart2_default { - pinmux { - function = "blsp_uart2"; - pins = "gpio4", "gpio5"; - }; - pinconf { - pins = "gpio4", "gpio5"; - drive-strength = <16>; - bias-disable; - }; - }; - - blsp1_uart2_sleep: blsp1_uart2_sleep { - pinmux { - function = "gpio"; - pins = "gpio4", "gpio5"; - }; - pinconf { - pins = "gpio4", "gpio5"; - drive-strength = <2>; - bias-pull-down; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/qcom/msm8994-smd-rpm.dtsi b/sys/gnu/dts/arm64/qcom/msm8994-smd-rpm.dtsi deleted file mode 100644 index 31e3eb6ab51..00000000000 --- a/sys/gnu/dts/arm64/qcom/msm8994-smd-rpm.dtsi +++ /dev/null @@ -1,268 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* Copyright (c) 2015, LGE Inc. All rights reserved. - * Copyright (c) 2016, The Linux Foundation. All rights reserved. - */ - -&smd_rpm { - rpm { - rpm_requests { - pm8994-regulators { - - vdd_l1-supply = <&pm8994_s1>; - vdd_l2_26_28-supply = <&pm8994_s3>; - vdd_l3_11-supply = <&pm8994_s3>; - vdd_l4_27_31-supply = <&pm8994_s3>; - vdd_l5_7-supply = <&pm8994_s3>; - vdd_l6_12_32-supply = <&pm8994_s5>; - vdd_l8_16_30-supply = <&vreg_vph_pwr>; - vdd_l9_10_18_22-supply = <&vreg_vph_pwr>; - vdd_l13_19_23_24-supply = <&vreg_vph_pwr>; - vdd_l14_15-supply = <&pm8994_s5>; - vdd_l17_29-supply = <&vreg_vph_pwr>; - vdd_l20_21-supply = <&vreg_vph_pwr>; - vdd_l25-supply = <&pm8994_s5>; - vdd_lvs1_2 = <&pm8994_s4>; - - s1 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <800000>; - }; - - s2 { - /* TODO */ - }; - - s3 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - }; - - s4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-allow-set-load; - regulator-system-load = <325000>; - }; - - s5 { - regulator-min-microvolt = <2150000>; - regulator-max-microvolt = <2150000>; - }; - - s7 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - }; - - l1 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - }; - - l2 { - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1250000>; - }; - - l3 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - l4 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - - l5 { - /* TODO */ - }; - - l6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l7 { - /* TODO */ - }; - - l8 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l9 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l10 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - qcom,init-voltage = <1800000>; - }; - - l11 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - qcom,init-voltage = <1200000>; - }; - - l12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - qcom,init-voltage = <1800000>; - proxy-supply = <&pm8994_l12>; - qcom,proxy-consumer-enable; - qcom,proxy-consumer-current = <10000>; - status = "okay"; - }; - - l13 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - qcom,init-voltage = <2950000>; - status = "okay"; - }; - - l14 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - qcom,init-voltage = <1200000>; - proxy-supply = <&pm8994_l14>; - qcom,proxy-consumer-enable; - qcom,proxy-consumer-current = <10000>; - status = "okay"; - }; - - l15 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - qcom,init-voltage = <1800000>; - status = "okay"; - }; - - l16 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - qcom,init-voltage = <2700000>; - status = "okay"; - }; - - l17 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - qcom,init-voltage = <2700000>; - status = "okay"; - }; - - l18 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - qcom,init-voltage = <3000000>; - qcom,init-ldo-mode = <1>; - }; - - l19 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - qcom,init-voltage = <1800000>; - status = "okay"; - }; - - l20 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - regulator-always-on; - regulator-boot-on; - regulator-allow-set-load; - regulator-system-load = <570000>; - }; - - l21 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - qcom,init-voltage = <1800000>; - }; - - l22 { - regulator-min-microvolt = <3100000>; - regulator-max-microvolt = <3100000>; - qcom,init-voltage = <3100000>; - }; - - l23 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - qcom,init-voltage = <2800000>; - }; - - l24 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3150000>; - qcom,init-voltage = <3075000>; - }; - - l25 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - qcom,init-voltage = <1800000>; - }; - - l26 { - /* TODO: value from downstream - regulator-min-microvolt = <987500>; - fails to apply */ - }; - - l27 { - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - qcom,init-voltage = <1050000>; - }; - - l28 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - qcom,init-voltage = <1000000>; - proxy-supply = <&pm8994_l28>; - qcom,proxy-consumer-enable; - qcom,proxy-consumer-current = <10000>; - }; - - l29 { - /* TODO: Unsupported voltage range. - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - qcom,init-voltage = <2800000>; - */ - }; - - l30 { - /* TODO: get this verified - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - qcom,init-voltage = <1800000>; - */ - }; - - l31 { - regulator-min-microvolt = <1262500>; - regulator-max-microvolt = <1262500>; - qcom,init-voltage = <1262500>; - }; - - l32 { - /* TODO: get this verified - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - qcom,init-voltage = <1800000>; - */ - }; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/qcom/msm8994.dtsi b/sys/gnu/dts/arm64/qcom/msm8994.dtsi deleted file mode 100644 index 3932757f78b..00000000000 --- a/sys/gnu/dts/arm64/qcom/msm8994.dtsi +++ /dev/null @@ -1,208 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. - */ - -#include -#include - -/ { - model = "Qualcomm Technologies, Inc. MSM 8994"; - compatible = "qcom,msm8994"; - // msm-id and pmic-id are required by bootloader for - // proper selection of dt blob - qcom,msm-id = <207 0x20000>; - qcom,pmic-id = <0x10009 0x1000A 0x0 0x0>; - interrupt-parent = <&intc>; - - #address-cells = <2>; - #size-cells = <2>; - - chosen { }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu-map { - cluster0 { - core0 { - cpu = <&CPU0>; - }; - }; - }; - - CPU0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0>; - next-level-cache = <&L2_0>; - L2_0: l2-cache { - compatible = "cache"; - cache-level = <2>; - }; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = <1 2 0xff08>, - <1 3 0xff08>, - <1 4 0xff08>, - <1 1 0xff08>; - }; - - soc: soc { - - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0 0xffffffff>; - compatible = "simple-bus"; - - intc: interrupt-controller@f9000000 { - compatible = "qcom,msm-qgic2"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0xf9000000 0x1000>, - <0xf9002000 0x1000>; - }; - - timer@f9020000 { - #address-cells = <1>; - #size-cells = <1>; - ranges; - compatible = "arm,armv7-timer-mem"; - reg = <0xf9020000 0x1000>; - - frame@f9021000 { - frame-number = <0>; - interrupts = , - ; - reg = <0xf9021000 0x1000>, - <0xf9022000 0x1000>; - }; - - frame@f9023000 { - frame-number = <1>; - interrupts = ; - reg = <0xf9023000 0x1000>; - status = "disabled"; - }; - - frame@f9024000 { - frame-number = <2>; - interrupts = ; - reg = <0xf9024000 0x1000>; - status = "disabled"; - }; - - frame@f9025000 { - frame-number = <3>; - interrupts = ; - reg = <0xf9025000 0x1000>; - status = "disabled"; - }; - - frame@f9026000 { - frame-number = <4>; - interrupts = ; - reg = <0xf9026000 0x1000>; - status = "disabled"; - }; - - frame@f9027000 { - frame-number = <5>; - interrupts = ; - reg = <0xf9027000 0x1000>; - status = "disabled"; - }; - - frame@f9028000 { - frame-number = <6>; - interrupts = ; - reg = <0xf9028000 0x1000>; - status = "disabled"; - }; - }; - - restart@fc4ab000 { - compatible = "qcom,pshold"; - reg = <0xfc4ab000 0x4>; - }; - - msmgpio: pinctrl@fd510000 { - compatible = "qcom,msm8994-pinctrl"; - reg = <0xfd510000 0x4000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - blsp1_uart2: serial@f991e000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0xf991e000 0x1000>; - interrupts = ; - status = "disabled"; - clock-names = "core", "iface"; - clocks = <&clock_gcc GCC_BLSP1_UART2_APPS_CLK>, - <&clock_gcc GCC_BLSP1_AHB_CLK>; - }; - - tcsr_mutex_regs: syscon@fd484000 { - compatible = "syscon"; - reg = <0xfd484000 0x2000>; - }; - - clock_gcc: clock-controller@fc400000 { - compatible = "qcom,gcc-msm8994"; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - reg = <0xfc400000 0x2000>; - }; - }; - - memory { - device_type = "memory"; - // We expect the bootloader to fill in the reg - reg = <0 0 0 0>; - }; - - xo_board: xo_board { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <19200000>; - }; - - sleep_clk: sleep_clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - smem_mem: smem_region@6a00000 { - reg = <0x0 0x6a00000 0x0 0x200000>; - no-map; - }; - }; - - tcsr_mutex: hwlock { - compatible = "qcom,tcsr-mutex"; - syscon = <&tcsr_mutex_regs 0 0x80>; - #hwlock-cells = <1>; - }; - - qcom,smem@6a00000 { - compatible = "qcom,smem"; - memory-region = <&smem_mem>; - hwlocks = <&tcsr_mutex 3>; - }; -}; - - -#include "msm8994-pins.dtsi" diff --git a/sys/gnu/dts/arm64/qcom/msm8996-mtp.dts b/sys/gnu/dts/arm64/qcom/msm8996-mtp.dts deleted file mode 100644 index 45ed594c1b9..00000000000 --- a/sys/gnu/dts/arm64/qcom/msm8996-mtp.dts +++ /dev/null @@ -1,13 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. - */ - -/dts-v1/; - -#include "msm8996-mtp.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. MSM 8996 MTP"; - compatible = "qcom,msm8996-mtp"; -}; diff --git a/sys/gnu/dts/arm64/qcom/msm8996-mtp.dtsi b/sys/gnu/dts/arm64/qcom/msm8996-mtp.dtsi deleted file mode 100644 index 5f46a1427f1..00000000000 --- a/sys/gnu/dts/arm64/qcom/msm8996-mtp.dtsi +++ /dev/null @@ -1,22 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. - */ - -#include "msm8996.dtsi" - -/ { - aliases { - serial0 = &blsp2_uart1; - }; - - chosen { - stdout-path = "serial0"; - }; - - soc { - serial@75b0000 { - status = "okay"; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/qcom/msm8996-pins.dtsi b/sys/gnu/dts/arm64/qcom/msm8996-pins.dtsi deleted file mode 100644 index ac1ede57936..00000000000 --- a/sys/gnu/dts/arm64/qcom/msm8996-pins.dtsi +++ /dev/null @@ -1,653 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. - */ - -&msmgpio { - - wcd9xxx_intr { - wcd_intr_default: wcd_intr_default{ - mux { - pins = "gpio54"; - function = "gpio"; - }; - - config { - pins = "gpio54"; - drive-strength = <2>; /* 2 mA */ - bias-pull-down; /* pull down */ - input-enable; - }; - }; - }; - - cdc_reset_ctrl { - cdc_reset_sleep: cdc_reset_sleep { - mux { - pins = "gpio64"; - function = "gpio"; - }; - config { - pins = "gpio64"; - drive-strength = <16>; - bias-disable; - output-low; - }; - }; - cdc_reset_active:cdc_reset_active { - mux { - pins = "gpio64"; - function = "gpio"; - }; - config { - pins = "gpio64"; - drive-strength = <16>; - bias-pull-down; - output-high; - }; - }; - }; - - blsp1_spi0_default: blsp1_spi0_default { - pinmux { - function = "blsp_spi1"; - pins = "gpio0", "gpio1", "gpio3"; - }; - pinmux_cs { - function = "gpio"; - pins = "gpio2"; - }; - pinconf { - pins = "gpio0", "gpio1", "gpio3"; - drive-strength = <12>; - bias-disable; - }; - pinconf_cs { - pins = "gpio2"; - drive-strength = <16>; - bias-disable; - output-high; - }; - }; - - blsp1_spi0_sleep: blsp1_spi0_sleep { - pinmux { - function = "gpio"; - pins = "gpio0", "gpio1", "gpio2", "gpio3"; - }; - pinconf { - pins = "gpio0", "gpio1", "gpio2", "gpio3"; - drive-strength = <2>; - bias-pull-down; - }; - }; - - blsp1_i2c2_default: blsp1_i2c2_default { - pinmux { - function = "blsp_i2c3"; - pins = "gpio47", "gpio48"; - }; - pinconf { - pins = "gpio47", "gpio48"; - drive-strength = <16>; - bias-disable = <0>; - }; - }; - - blsp1_i2c2_sleep: blsp1_i2c2_sleep { - pinmux { - function = "gpio"; - pins = "gpio47", "gpio48"; - }; - pinconf { - pins = "gpio47", "gpio48"; - drive-strength = <2>; - bias-disable = <0>; - }; - }; - - blsp2_i2c0_default: blsp2_i2c0 { - pinmux { - function = "blsp_i2c7"; - pins = "gpio55", "gpio56"; - }; - pinconf { - pins = "gpio55", "gpio56"; - drive-strength = <16>; - bias-disable; - }; - }; - - blsp2_i2c0_sleep: blsp2_i2c0_sleep { - pinmux { - function = "gpio"; - pins = "gpio55", "gpio56"; - }; - pinconf { - pins = "gpio55", "gpio56"; - drive-strength = <2>; - bias-disable; - }; - }; - - blsp2_uart1_2pins_default: blsp2_uart1_2pins { - pinmux { - function = "blsp_uart8"; - pins = "gpio4", "gpio5"; - }; - pinconf { - pins = "gpio4", "gpio5"; - drive-strength = <16>; - bias-disable; - }; - }; - - blsp2_uart1_2pins_sleep: blsp2_uart1_2pins_sleep { - pinmux { - function = "gpio"; - pins = "gpio4", "gpio5"; - }; - pinconf { - pins = "gpio4", "gpio5"; - drive-strength = <2>; - bias-disable; - }; - }; - - blsp2_uart1_4pins_default: blsp2_uart1_4pins { - pinmux { - function = "blsp_uart8"; - pins = "gpio4", "gpio5", "gpio6", "gpio7"; - }; - - pinconf { - pins = "gpio4", "gpio5", "gpio6", "gpio7"; - drive-strength = <16>; - bias-disable; - }; - }; - - blsp2_uart1_4pins_sleep: blsp2_uart1_4pins_sleep { - pinmux { - function = "gpio"; - pins = "gpio4", "gpio5", "gpio6", "gpio7"; - }; - - pinconf { - pins = "gpio4", "gpio5", "gpio6", "gpio7"; - drive-strength = <2>; - bias-disable; - }; - }; - - blsp2_i2c1_default: blsp2_i2c1 { - pinmux { - function = "blsp_i2c8"; - pins = "gpio6", "gpio7"; - }; - pinconf { - pins = "gpio6", "gpio7"; - drive-strength = <16>; - bias-disable; - }; - }; - - blsp2_i2c1_sleep: blsp2_i2c1_sleep { - pinmux { - function = "gpio"; - pins = "gpio6", "gpio7"; - }; - pinconf { - pins = "gpio6", "gpio7"; - drive-strength = <2>; - bias-disable; - }; - }; - - blsp2_uart2_2pins_default: blsp2_uart2_2pins { - pinmux { - function = "blsp_uart9"; - pins = "gpio49", "gpio50"; - }; - pinconf { - pins = "gpio49", "gpio50"; - drive-strength = <16>; - bias-disable; - }; - }; - - blsp2_uart2_2pins_sleep: blsp2_uart2_2pins_sleep { - pinmux { - function = "gpio"; - pins = "gpio49", "gpio50"; - }; - pinconf { - pins = "gpio49", "gpio50"; - drive-strength = <2>; - bias-disable; - }; - }; - - blsp2_uart2_4pins_default: blsp2_uart2_4pins { - pinmux { - function = "blsp_uart9"; - pins = "gpio49", "gpio50", "gpio51", "gpio52"; - }; - - pinconf { - pins = "gpio49", "gpio50", "gpio51", "gpio52"; - drive-strength = <16>; - bias-disable; - }; - }; - - blsp2_uart2_4pins_sleep: blsp2_uart2_4pins_sleep { - pinmux { - function = "gpio"; - pins = "gpio49", "gpio50", "gpio51", "gpio52"; - }; - - pinconf { - pins = "gpio49", "gpio50", "gpio51", "gpio52"; - drive-strength = <2>; - bias-disable; - }; - }; - - blsp2_spi5_default: blsp2_spi5_default { - pinmux { - function = "blsp_spi12"; - pins = "gpio85", "gpio86", "gpio88"; - }; - pinmux_cs { - function = "gpio"; - pins = "gpio87"; - }; - pinconf { - pins = "gpio85", "gpio86", "gpio88"; - drive-strength = <12>; - bias-disable; - }; - pinconf_cs { - pins = "gpio87"; - drive-strength = <16>; - bias-disable; - output-high; - }; - }; - - blsp2_spi5_sleep: blsp2_spi5_sleep { - pinmux { - function = "gpio"; - pins = "gpio85", "gpio86", "gpio87", "gpio88"; - }; - pinconf { - pins = "gpio85", "gpio86", "gpio87", "gpio88"; - drive-strength = <2>; - bias-pull-down; - }; - }; - - sdc2_clk_on: sdc2_clk_on { - config { - pins = "sdc2_clk"; - bias-disable; /* NO pull */ - drive-strength = <16>; /* 16 MA */ - }; - }; - - sdc2_clk_off: sdc2_clk_off { - config { - pins = "sdc2_clk"; - bias-disable; /* NO pull */ - drive-strength = <2>; /* 2 MA */ - }; - }; - - sdc2_cmd_on: sdc2_cmd_on { - config { - pins = "sdc2_cmd"; - bias-pull-up; /* pull up */ - drive-strength = <10>; /* 10 MA */ - }; - }; - - sdc2_cmd_off: sdc2_cmd_off { - config { - pins = "sdc2_cmd"; - bias-pull-up; /* pull up */ - drive-strength = <2>; /* 2 MA */ - }; - }; - - sdc2_data_on: sdc2_data_on { - config { - pins = "sdc2_data"; - bias-pull-up; /* pull up */ - drive-strength = <10>; /* 10 MA */ - }; - }; - - sdc2_data_off: sdc2_data_off { - config { - pins = "sdc2_data"; - bias-pull-up; /* pull up */ - drive-strength = <2>; /* 2 MA */ - }; - }; - - pcie0_clkreq_default: pcie0_clkreq_default { - mux { - pins = "gpio36"; - function = "pci_e0"; - }; - - config { - pins = "gpio36"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - pcie0_perst_default: pcie0_perst_default { - mux { - pins = "gpio35"; - function = "gpio"; - }; - - config { - pins = "gpio35"; - drive-strength = <2>; - bias-pull-down; - }; - }; - - pcie0_wake_default: pcie0_wake_default { - mux { - pins = "gpio37"; - function = "gpio"; - }; - - config { - pins = "gpio37"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - pcie0_clkreq_sleep: pcie0_clkreq_sleep { - mux { - pins = "gpio36"; - function = "gpio"; - }; - - config { - pins = "gpio36"; - drive-strength = <2>; - bias-disable; - }; - }; - - pcie0_wake_sleep: pcie0_wake_sleep { - mux { - pins = "gpio37"; - function = "gpio"; - }; - - config { - pins = "gpio37"; - drive-strength = <2>; - bias-disable; - }; - }; - - pcie1_clkreq_default: pcie1_clkreq_default { - mux { - pins = "gpio131"; - function = "pci_e1"; - }; - - config { - pins = "gpio131"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - pcie1_perst_default: pcie1_perst_default { - mux { - pins = "gpio130"; - function = "gpio"; - }; - - config { - pins = "gpio130"; - drive-strength = <2>; - bias-pull-down; - }; - }; - - pcie1_wake_default: pcie1_wake_default { - mux { - pins = "gpio132"; - function = "gpio"; - }; - - config { - pins = "gpio132"; - drive-strength = <2>; - bias-pull-down; - }; - }; - - pcie1_clkreq_sleep: pcie1_clkreq_sleep { - mux { - pins = "gpio131"; - function = "gpio"; - }; - - config { - pins = "gpio131"; - drive-strength = <2>; - bias-disable; - }; - }; - - pcie1_wake_sleep: pcie1_wake_sleep { - mux { - pins = "gpio132"; - function = "gpio"; - }; - - config { - pins = "gpio132"; - drive-strength = <2>; - bias-disable; - }; - }; - - pcie2_clkreq_default: pcie2_clkreq_default { - mux { - pins = "gpio115"; - function = "pci_e2"; - }; - - config { - pins = "gpio115"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - pcie2_perst_default: pcie2_perst_default { - mux { - pins = "gpio114"; - function = "gpio"; - }; - - config { - pins = "gpio114"; - drive-strength = <2>; - bias-pull-down; - }; - }; - - pcie2_wake_default: pcie2_wake_default { - mux { - pins = "gpio116"; - function = "gpio"; - }; - - config { - pins = "gpio116"; - drive-strength = <2>; - bias-pull-down; - }; - }; - - pcie2_clkreq_sleep: pcie2_clkreq_sleep { - mux { - pins = "gpio115"; - function = "gpio"; - }; - - config { - pins = "gpio115"; - drive-strength = <2>; - bias-disable; - }; - }; - - pcie2_wake_sleep: pcie2_wake_sleep { - mux { - pins = "gpio116"; - function = "gpio"; - }; - - config { - pins = "gpio116"; - drive-strength = <2>; - bias-disable; - }; - }; - - cci0_default: cci0_default { - pinmux { - function = "cci_i2c"; - pins = "gpio17", "gpio18"; - }; - pinconf { - pins = "gpio17", "gpio18"; - drive-strength = <16>; - bias-disable; - }; - }; - - cci1_default: cci1_default { - pinmux { - function = "cci_i2c"; - pins = "gpio19", "gpio20"; - }; - pinconf { - pins = "gpio19", "gpio20"; - drive-strength = <16>; - bias-disable; - }; - }; - - camera_board_default: camera_board_default { - mux_pwdn { - function = "gpio"; - pins = "gpio98"; - }; - config_pwdn { - pins = "gpio98"; - drive-strength = <16>; - bias-disable; - }; - - mux_rst { - function = "gpio"; - pins = "gpio104"; - }; - config_rst { - pins = "gpio104"; - drive-strength = <16>; - bias-disable; - }; - - mux_mclk1 { - function = "cam_mclk"; - pins = "gpio14"; - }; - config_mclk1 { - pins = "gpio14"; - drive-strength = <16>; - bias-disable; - }; - }; - - camera_front_default: camera_front_default { - mux_pwdn { - function = "gpio"; - pins = "gpio133"; - }; - config_pwdn { - pins = "gpio133"; - drive-strength = <16>; - bias-disable; - }; - - mux_rst { - function = "gpio"; - pins = "gpio23"; - }; - config_rst { - pins = "gpio23"; - drive-strength = <16>; - bias-disable; - }; - - mux_mclk2 { - function = "cam_mclk"; - pins = "gpio15"; - }; - config_mclk2 { - pins = "gpio15"; - drive-strength = <16>; - bias-disable; - }; - }; - - camera_rear_default: camera_rear_default { - mux_pwdn { - function = "gpio"; - pins = "gpio26"; - }; - config_pwdn { - pins = "gpio26"; - drive-strength = <16>; - bias-disable; - }; - - mux_rst { - function = "gpio"; - pins = "gpio25"; - }; - config_rst { - pins = "gpio25"; - drive-strength = <16>; - bias-disable; - }; - - mux_mclk0 { - function = "cam_mclk"; - pins = "gpio13"; - }; - config_mclk0 { - pins = "gpio13"; - drive-strength = <16>; - bias-disable; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/qcom/msm8996.dtsi b/sys/gnu/dts/arm64/qcom/msm8996.dtsi deleted file mode 100644 index 7ae082ea14e..00000000000 --- a/sys/gnu/dts/arm64/qcom/msm8996.dtsi +++ /dev/null @@ -1,2404 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. - */ - -#include -#include -#include -#include -#include - -/ { - interrupt-parent = <&intc>; - - #address-cells = <2>; - #size-cells = <2>; - - chosen { }; - - clocks { - xo_board: xo_board { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <19200000>; - clock-output-names = "xo_board"; - }; - - sleep_clk: sleep_clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32764>; - clock-output-names = "sleep_clk"; - }; - }; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - CPU0: cpu@0 { - device_type = "cpu"; - compatible = "qcom,kryo"; - reg = <0x0 0x0>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - capacity-dmips-mhz = <1024>; - next-level-cache = <&L2_0>; - L2_0: l2-cache { - compatible = "cache"; - cache-level = <2>; - }; - }; - - CPU1: cpu@1 { - device_type = "cpu"; - compatible = "qcom,kryo"; - reg = <0x0 0x1>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - capacity-dmips-mhz = <1024>; - next-level-cache = <&L2_0>; - }; - - CPU2: cpu@100 { - device_type = "cpu"; - compatible = "qcom,kryo"; - reg = <0x0 0x100>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - capacity-dmips-mhz = <1024>; - next-level-cache = <&L2_1>; - L2_1: l2-cache { - compatible = "cache"; - cache-level = <2>; - }; - }; - - CPU3: cpu@101 { - device_type = "cpu"; - compatible = "qcom,kryo"; - reg = <0x0 0x101>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - capacity-dmips-mhz = <1024>; - next-level-cache = <&L2_1>; - }; - - cpu-map { - cluster0 { - core0 { - cpu = <&CPU0>; - }; - - core1 { - cpu = <&CPU1>; - }; - }; - - cluster1 { - core0 { - cpu = <&CPU2>; - }; - - core1 { - cpu = <&CPU3>; - }; - }; - }; - - idle-states { - entry-method = "psci"; - - CPU_SLEEP_0: cpu-sleep-0 { - compatible = "arm,idle-state"; - idle-state-name = "standalone-power-collapse"; - arm,psci-suspend-param = <0x00000004>; - entry-latency-us = <130>; - exit-latency-us = <80>; - min-residency-us = <300>; - }; - }; - }; - - firmware { - scm { - compatible = "qcom,scm-msm8996"; - qcom,dload-mode = <&tcsr 0x13000>; - }; - }; - - tcsr_mutex: hwlock { - compatible = "qcom,tcsr-mutex"; - syscon = <&tcsr_mutex_regs 0 0x1000>; - #hwlock-cells = <1>; - }; - - memory { - device_type = "memory"; - /* We expect the bootloader to fill in the reg */ - reg = <0 0 0 0>; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - mba_region: mba@91500000 { - reg = <0x0 0x91500000 0x0 0x200000>; - no-map; - }; - - slpi_region: slpi@90b00000 { - reg = <0x0 0x90b00000 0x0 0xa00000>; - no-map; - }; - - venus_region: venus@90400000 { - reg = <0x0 0x90400000 0x0 0x700000>; - no-map; - }; - - adsp_region: adsp@8ea00000 { - reg = <0x0 0x8ea00000 0x0 0x1a00000>; - no-map; - }; - - mpss_region: mpss@88800000 { - reg = <0x0 0x88800000 0x0 0x6200000>; - no-map; - }; - - smem_mem: smem-mem@86000000 { - reg = <0x0 0x86000000 0x0 0x200000>; - no-map; - }; - - memory@85800000 { - reg = <0x0 0x85800000 0x0 0x800000>; - no-map; - }; - - memory@86200000 { - reg = <0x0 0x86200000 0x0 0x2600000>; - no-map; - }; - - rmtfs@86700000 { - compatible = "qcom,rmtfs-mem"; - - size = <0x0 0x200000>; - alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>; - no-map; - - qcom,client-id = <1>; - qcom,vmid = <15>; - }; - - zap_shader_region: gpu@8f200000 { - compatible = "shared-dma-pool"; - reg = <0x0 0x90b00000 0x0 0xa00000>; - no-map; - }; - }; - - rpm-glink { - compatible = "qcom,glink-rpm"; - - interrupts = ; - - qcom,rpm-msg-ram = <&rpm_msg_ram>; - - mboxes = <&apcs_glb 0>; - - rpm_requests: rpm-requests { - compatible = "qcom,rpm-msm8996"; - qcom,glink-channels = "rpm_requests"; - - rpmcc: qcom,rpmcc { - compatible = "qcom,rpmcc-msm8996"; - #clock-cells = <1>; - }; - - rpmpd: power-controller { - compatible = "qcom,msm8996-rpmpd"; - #power-domain-cells = <1>; - operating-points-v2 = <&rpmpd_opp_table>; - - rpmpd_opp_table: opp-table { - compatible = "operating-points-v2"; - - rpmpd_opp1: opp1 { - opp-level = <1>; - }; - - rpmpd_opp2: opp2 { - opp-level = <2>; - }; - - rpmpd_opp3: opp3 { - opp-level = <3>; - }; - - rpmpd_opp4: opp4 { - opp-level = <4>; - }; - - rpmpd_opp5: opp5 { - opp-level = <5>; - }; - - rpmpd_opp6: opp6 { - opp-level = <6>; - }; - }; - }; - }; - }; - - smem { - compatible = "qcom,smem"; - memory-region = <&smem_mem>; - hwlocks = <&tcsr_mutex 3>; - }; - - smp2p-adsp { - compatible = "qcom,smp2p"; - qcom,smem = <443>, <429>; - - interrupts = <0 158 IRQ_TYPE_EDGE_RISING>; - - mboxes = <&apcs_glb 10>; - - qcom,local-pid = <0>; - qcom,remote-pid = <2>; - - smp2p_adsp_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - smp2p_adsp_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - smp2p-modem { - compatible = "qcom,smp2p"; - qcom,smem = <435>, <428>; - - interrupts = ; - - mboxes = <&apcs_glb 14>; - - qcom,local-pid = <0>; - qcom,remote-pid = <1>; - - modem_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - modem_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - smp2p-slpi { - compatible = "qcom,smp2p"; - qcom,smem = <481>, <430>; - - interrupts = ; - - mboxes = <&apcs_glb 26>; - - qcom,local-pid = <0>; - qcom,remote-pid = <3>; - - smp2p_slpi_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - interrupt-controller; - #interrupt-cells = <2>; - }; - - smp2p_slpi_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - }; - - soc: soc { - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0 0xffffffff>; - compatible = "simple-bus"; - - pcie_phy: phy@34000 { - compatible = "qcom,msm8996-qmp-pcie-phy"; - reg = <0x00034000 0x488>; - #clock-cells = <1>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, - <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>, - <&gcc GCC_PCIE_CLKREF_CLK>; - clock-names = "aux", "cfg_ahb", "ref"; - - resets = <&gcc GCC_PCIE_PHY_BCR>, - <&gcc GCC_PCIE_PHY_COM_BCR>, - <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>; - reset-names = "phy", "common", "cfg"; - status = "disabled"; - - pciephy_0: lane@35000 { - reg = <0x00035000 0x130>, - <0x00035200 0x200>, - <0x00035400 0x1dc>; - #phy-cells = <0>; - - clock-output-names = "pcie_0_pipe_clk_src"; - clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; - clock-names = "pipe0"; - resets = <&gcc GCC_PCIE_0_PHY_BCR>; - reset-names = "lane0"; - }; - - pciephy_1: lane@36000 { - reg = <0x00036000 0x130>, - <0x00036200 0x200>, - <0x00036400 0x1dc>; - #phy-cells = <0>; - - clock-output-names = "pcie_1_pipe_clk_src"; - clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; - clock-names = "pipe1"; - resets = <&gcc GCC_PCIE_1_PHY_BCR>; - reset-names = "lane1"; - }; - - pciephy_2: lane@37000 { - reg = <0x00037000 0x130>, - <0x00037200 0x200>, - <0x00037400 0x1dc>; - #phy-cells = <0>; - - clock-output-names = "pcie_2_pipe_clk_src"; - clocks = <&gcc GCC_PCIE_2_PIPE_CLK>; - clock-names = "pipe2"; - resets = <&gcc GCC_PCIE_2_PHY_BCR>; - reset-names = "lane2"; - }; - }; - - rpm_msg_ram: memory@68000 { - compatible = "qcom,rpm-msg-ram"; - reg = <0x00068000 0x6000>; - }; - - qfprom@74000 { - compatible = "qcom,qfprom"; - reg = <0x00074000 0x8ff>; - #address-cells = <1>; - #size-cells = <1>; - - qusb2p_hstx_trim: hstx_trim@24e { - reg = <0x24e 0x2>; - bits = <5 4>; - }; - - qusb2s_hstx_trim: hstx_trim@24f { - reg = <0x24f 0x1>; - bits = <1 4>; - }; - - gpu_speed_bin: gpu_speed_bin@133 { - reg = <0x133 0x1>; - bits = <5 3>; - }; - }; - - rng: rng@83000 { - compatible = "qcom,prng-ee"; - reg = <0x00083000 0x1000>; - clocks = <&gcc GCC_PRNG_AHB_CLK>; - clock-names = "core"; - }; - - gcc: clock-controller@300000 { - compatible = "qcom,gcc-msm8996"; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - reg = <0x00300000 0x90000>; - }; - - tsens0: thermal-sensor@4a9000 { - compatible = "qcom,msm8996-tsens"; - reg = <0x004a9000 0x1000>, /* TM */ - <0x004a8000 0x1000>; /* SROT */ - #qcom,sensors = <13>; - interrupts = , - ; - interrupt-names = "uplow", "critical"; - #thermal-sensor-cells = <1>; - }; - - tsens1: thermal-sensor@4ad000 { - compatible = "qcom,msm8996-tsens"; - reg = <0x004ad000 0x1000>, /* TM */ - <0x004ac000 0x1000>; /* SROT */ - #qcom,sensors = <8>; - interrupts = , - ; - interrupt-names = "uplow", "critical"; - #thermal-sensor-cells = <1>; - }; - - tcsr_mutex_regs: syscon@740000 { - compatible = "syscon"; - reg = <0x00740000 0x20000>; - }; - - tcsr: syscon@7a0000 { - compatible = "qcom,tcsr-msm8996", "syscon"; - reg = <0x007a0000 0x18000>; - }; - - mmcc: clock-controller@8c0000 { - compatible = "qcom,mmcc-msm8996"; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - reg = <0x008c0000 0x40000>; - assigned-clocks = <&mmcc MMPLL9_PLL>, - <&mmcc MMPLL1_PLL>, - <&mmcc MMPLL3_PLL>, - <&mmcc MMPLL4_PLL>, - <&mmcc MMPLL5_PLL>; - assigned-clock-rates = <624000000>, - <810000000>, - <980000000>, - <960000000>, - <825000000>; - }; - - mdss: mdss@900000 { - compatible = "qcom,mdss"; - - reg = <0x00900000 0x1000>, - <0x009b0000 0x1040>, - <0x009b8000 0x1040>; - reg-names = "mdss_phys", - "vbif_phys", - "vbif_nrt_phys"; - - power-domains = <&mmcc MDSS_GDSC>; - interrupts = ; - - interrupt-controller; - #interrupt-cells = <1>; - - clocks = <&mmcc MDSS_AHB_CLK>; - clock-names = "iface"; - - #address-cells = <1>; - #size-cells = <1>; - ranges; - - mdp: mdp@901000 { - compatible = "qcom,mdp5"; - reg = <0x00901000 0x90000>; - reg-names = "mdp_phys"; - - interrupt-parent = <&mdss>; - interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; - - clocks = <&mmcc MDSS_AHB_CLK>, - <&mmcc MDSS_AXI_CLK>, - <&mmcc MDSS_MDP_CLK>, - <&mmcc SMMU_MDP_AXI_CLK>, - <&mmcc MDSS_VSYNC_CLK>; - clock-names = "iface", - "bus", - "core", - "iommu", - "vsync"; - - iommus = <&mdp_smmu 0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - mdp5_intf3_out: endpoint { - remote-endpoint = <&hdmi_in>; - }; - }; - }; - }; - - hdmi: hdmi-tx@9a0000 { - compatible = "qcom,hdmi-tx-8996"; - reg = <0x009a0000 0x50c>, - <0x00070000 0x6158>, - <0x009e0000 0xfff>; - reg-names = "core_physical", - "qfprom_physical", - "hdcp_physical"; - - interrupt-parent = <&mdss>; - interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; - - clocks = <&mmcc MDSS_MDP_CLK>, - <&mmcc MDSS_AHB_CLK>, - <&mmcc MDSS_HDMI_CLK>, - <&mmcc MDSS_HDMI_AHB_CLK>, - <&mmcc MDSS_EXTPCLK_CLK>; - clock-names = - "mdp_core", - "iface", - "core", - "alt_iface", - "extp"; - - phys = <&hdmi_phy>; - phy-names = "hdmi_phy"; - #sound-dai-cells = <1>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - hdmi_in: endpoint { - remote-endpoint = <&mdp5_intf3_out>; - }; - }; - }; - }; - - hdmi_phy: hdmi-phy@9a0600 { - #phy-cells = <0>; - compatible = "qcom,hdmi-phy-8996"; - reg = <0x009a0600 0x1c4>, - <0x009a0a00 0x124>, - <0x009a0c00 0x124>, - <0x009a0e00 0x124>, - <0x009a1000 0x124>, - <0x009a1200 0x0c8>; - reg-names = "hdmi_pll", - "hdmi_tx_l0", - "hdmi_tx_l1", - "hdmi_tx_l2", - "hdmi_tx_l3", - "hdmi_phy"; - - clocks = <&mmcc MDSS_AHB_CLK>, - <&gcc GCC_HDMI_CLKREF_CLK>; - clock-names = "iface", - "ref"; - }; - }; - gpu@b00000 { - compatible = "qcom,adreno-530.2", "qcom,adreno"; - #stream-id-cells = <16>; - - reg = <0x00b00000 0x3f000>; - reg-names = "kgsl_3d0_reg_memory"; - - interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>; - - clocks = <&mmcc GPU_GX_GFX3D_CLK>, - <&mmcc GPU_AHB_CLK>, - <&mmcc GPU_GX_RBBMTIMER_CLK>, - <&gcc GCC_BIMC_GFX_CLK>, - <&gcc GCC_MMSS_BIMC_GFX_CLK>; - - clock-names = "core", - "iface", - "rbbmtimer", - "mem", - "mem_iface"; - - power-domains = <&mmcc GPU_GDSC>; - iommus = <&adreno_smmu 0>; - - nvmem-cells = <&gpu_speed_bin>; - nvmem-cell-names = "speed_bin"; - - qcom,gpu-quirk-two-pass-use-wfi; - qcom,gpu-quirk-fault-detect-mask; - - operating-points-v2 = <&gpu_opp_table>; - - gpu_opp_table: opp-table { - compatible ="operating-points-v2"; - - /* - * 624Mhz and 560Mhz are only available on speed - * bin (1 << 0). All the rest are available on - * all bins of the hardware - */ - opp-624000000 { - opp-hz = /bits/ 64 <624000000>; - opp-supported-hw = <0x01>; - }; - opp-560000000 { - opp-hz = /bits/ 64 <560000000>; - opp-supported-hw = <0x01>; - }; - opp-510000000 { - opp-hz = /bits/ 64 <510000000>; - opp-supported-hw = <0xFF>; - }; - opp-401800000 { - opp-hz = /bits/ 64 <401800000>; - opp-supported-hw = <0xFF>; - }; - opp-315000000 { - opp-hz = /bits/ 64 <315000000>; - opp-supported-hw = <0xFF>; - }; - opp-214000000 { - opp-hz = /bits/ 64 <214000000>; - opp-supported-hw = <0xFF>; - }; - opp-133000000 { - opp-hz = /bits/ 64 <133000000>; - opp-supported-hw = <0xFF>; - }; - }; - - zap-shader { - memory-region = <&zap_shader_region>; - }; - }; - - msmgpio: pinctrl@1010000 { - compatible = "qcom,msm8996-pinctrl"; - reg = <0x01010000 0x300000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - spmi_bus: qcom,spmi@400f000 { - compatible = "qcom,spmi-pmic-arb"; - reg = <0x0400f000 0x1000>, - <0x04400000 0x800000>, - <0x04c00000 0x800000>, - <0x05800000 0x200000>, - <0x0400a000 0x002100>; - reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; - interrupt-names = "periph_irq"; - interrupts = ; - qcom,ee = <0>; - qcom,channel = <0>; - #address-cells = <2>; - #size-cells = <0>; - interrupt-controller; - #interrupt-cells = <4>; - }; - - agnoc@0 { - power-domains = <&gcc AGGRE0_NOC_GDSC>; - compatible = "simple-pm-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - pcie0: pcie@600000 { - compatible = "qcom,pcie-msm8996", "snps,dw-pcie"; - status = "disabled"; - power-domains = <&gcc PCIE0_GDSC>; - bus-range = <0x00 0xff>; - num-lanes = <1>; - - reg = <0x00600000 0x2000>, - <0x0c000000 0xf1d>, - <0x0c000f20 0xa8>, - <0x0c100000 0x100000>; - reg-names = "parf", "dbi", "elbi","config"; - - phys = <&pciephy_0>; - phy-names = "pciephy"; - - #address-cells = <3>; - #size-cells = <2>; - ranges = <0x01000000 0x0 0x0c200000 0x0c200000 0x0 0x100000>, - <0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>; - - interrupts = ; - interrupt-names = "msi"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&pcie0_clkreq_default &pcie0_perst_default &pcie0_wake_default>; - pinctrl-1 = <&pcie0_clkreq_sleep &pcie0_perst_default &pcie0_wake_sleep>; - - linux,pci-domain = <0>; - - clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, - <&gcc GCC_PCIE_0_AUX_CLK>, - <&gcc GCC_PCIE_0_CFG_AHB_CLK>, - <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, - <&gcc GCC_PCIE_0_SLV_AXI_CLK>; - - clock-names = "pipe", - "aux", - "cfg", - "bus_master", - "bus_slave"; - - }; - - pcie1: pcie@608000 { - compatible = "qcom,pcie-msm8996", "snps,dw-pcie"; - power-domains = <&gcc PCIE1_GDSC>; - bus-range = <0x00 0xff>; - num-lanes = <1>; - - status = "disabled"; - - reg = <0x00608000 0x2000>, - <0x0d000000 0xf1d>, - <0x0d000f20 0xa8>, - <0x0d100000 0x100000>; - - reg-names = "parf", "dbi", "elbi","config"; - - phys = <&pciephy_1>; - phy-names = "pciephy"; - - #address-cells = <3>; - #size-cells = <2>; - ranges = <0x01000000 0x0 0x0d200000 0x0d200000 0x0 0x100000>, - <0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>; - - interrupts = ; - interrupt-names = "msi"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&pcie1_clkreq_default &pcie1_perst_default &pcie1_wake_default>; - pinctrl-1 = <&pcie1_clkreq_sleep &pcie1_perst_default &pcie1_wake_sleep>; - - linux,pci-domain = <1>; - - clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, - <&gcc GCC_PCIE_1_AUX_CLK>, - <&gcc GCC_PCIE_1_CFG_AHB_CLK>, - <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, - <&gcc GCC_PCIE_1_SLV_AXI_CLK>; - - clock-names = "pipe", - "aux", - "cfg", - "bus_master", - "bus_slave"; - }; - - pcie2: pcie@610000 { - compatible = "qcom,pcie-msm8996", "snps,dw-pcie"; - power-domains = <&gcc PCIE2_GDSC>; - bus-range = <0x00 0xff>; - num-lanes = <1>; - status = "disabled"; - reg = <0x00610000 0x2000>, - <0x0e000000 0xf1d>, - <0x0e000f20 0xa8>, - <0x0e100000 0x100000>; - - reg-names = "parf", "dbi", "elbi","config"; - - phys = <&pciephy_2>; - phy-names = "pciephy"; - - #address-cells = <3>; - #size-cells = <2>; - ranges = <0x01000000 0x0 0x0e200000 0x0e200000 0x0 0x100000>, - <0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>; - - device_type = "pci"; - - interrupts = ; - interrupt-names = "msi"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&pcie2_clkreq_default &pcie2_perst_default &pcie2_wake_default>; - pinctrl-1 = <&pcie2_clkreq_sleep &pcie2_perst_default &pcie2_wake_sleep >; - - linux,pci-domain = <2>; - clocks = <&gcc GCC_PCIE_2_PIPE_CLK>, - <&gcc GCC_PCIE_2_AUX_CLK>, - <&gcc GCC_PCIE_2_CFG_AHB_CLK>, - <&gcc GCC_PCIE_2_MSTR_AXI_CLK>, - <&gcc GCC_PCIE_2_SLV_AXI_CLK>; - - clock-names = "pipe", - "aux", - "cfg", - "bus_master", - "bus_slave"; - }; - }; - - ufshc: ufshc@624000 { - compatible = "qcom,ufshc"; - reg = <0x00624000 0x2500>; - interrupts = ; - - phys = <&ufsphy>; - phy-names = "ufsphy"; - - power-domains = <&gcc UFS_GDSC>; - - clock-names = - "core_clk_src", - "core_clk", - "bus_clk", - "bus_aggr_clk", - "iface_clk", - "core_clk_unipro_src", - "core_clk_unipro", - "core_clk_ice", - "ref_clk", - "tx_lane0_sync_clk", - "rx_lane0_sync_clk"; - clocks = - <&gcc UFS_AXI_CLK_SRC>, - <&gcc GCC_UFS_AXI_CLK>, - <&gcc GCC_SYS_NOC_UFS_AXI_CLK>, - <&gcc GCC_AGGRE2_UFS_AXI_CLK>, - <&gcc GCC_UFS_AHB_CLK>, - <&gcc UFS_ICE_CORE_CLK_SRC>, - <&gcc GCC_UFS_UNIPRO_CORE_CLK>, - <&gcc GCC_UFS_ICE_CORE_CLK>, - <&rpmcc RPM_SMD_LN_BB_CLK>, - <&gcc GCC_UFS_TX_SYMBOL_0_CLK>, - <&gcc GCC_UFS_RX_SYMBOL_0_CLK>; - freq-table-hz = - <100000000 200000000>, - <0 0>, - <0 0>, - <0 0>, - <0 0>, - <150000000 300000000>, - <0 0>, - <0 0>, - <0 0>, - <0 0>, - <0 0>; - - lanes-per-direction = <1>; - #reset-cells = <1>; - status = "disabled"; - - ufs_variant { - compatible = "qcom,ufs_variant"; - }; - }; - - ufsphy: phy@627000 { - compatible = "qcom,msm8996-ufs-phy-qmp-14nm"; - reg = <0x00627000 0xda8>; - reg-names = "phy_mem"; - #phy-cells = <0>; - - clock-names = "ref_clk_src", "ref_clk"; - clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, - <&gcc GCC_UFS_CLKREF_CLK>; - resets = <&ufshc 0>; - status = "disabled"; - }; - - camss: camss@a00000 { - compatible = "qcom,msm8996-camss"; - reg = <0x00a34000 0x1000>, - <0x00a00030 0x4>, - <0x00a35000 0x1000>, - <0x00a00038 0x4>, - <0x00a36000 0x1000>, - <0x00a00040 0x4>, - <0x00a30000 0x100>, - <0x00a30400 0x100>, - <0x00a30800 0x100>, - <0x00a30c00 0x100>, - <0x00a31000 0x500>, - <0x00a00020 0x10>, - <0x00a10000 0x1000>, - <0x00a14000 0x1000>; - reg-names = "csiphy0", - "csiphy0_clk_mux", - "csiphy1", - "csiphy1_clk_mux", - "csiphy2", - "csiphy2_clk_mux", - "csid0", - "csid1", - "csid2", - "csid3", - "ispif", - "csi_clk_mux", - "vfe0", - "vfe1"; - interrupts = , - , - , - , - , - , - , - , - , - ; - interrupt-names = "csiphy0", - "csiphy1", - "csiphy2", - "csid0", - "csid1", - "csid2", - "csid3", - "ispif", - "vfe0", - "vfe1"; - power-domains = <&mmcc VFE0_GDSC>; - clocks = <&mmcc CAMSS_TOP_AHB_CLK>, - <&mmcc CAMSS_ISPIF_AHB_CLK>, - <&mmcc CAMSS_CSI0PHYTIMER_CLK>, - <&mmcc CAMSS_CSI1PHYTIMER_CLK>, - <&mmcc CAMSS_CSI2PHYTIMER_CLK>, - <&mmcc CAMSS_CSI0_AHB_CLK>, - <&mmcc CAMSS_CSI0_CLK>, - <&mmcc CAMSS_CSI0PHY_CLK>, - <&mmcc CAMSS_CSI0PIX_CLK>, - <&mmcc CAMSS_CSI0RDI_CLK>, - <&mmcc CAMSS_CSI1_AHB_CLK>, - <&mmcc CAMSS_CSI1_CLK>, - <&mmcc CAMSS_CSI1PHY_CLK>, - <&mmcc CAMSS_CSI1PIX_CLK>, - <&mmcc CAMSS_CSI1RDI_CLK>, - <&mmcc CAMSS_CSI2_AHB_CLK>, - <&mmcc CAMSS_CSI2_CLK>, - <&mmcc CAMSS_CSI2PHY_CLK>, - <&mmcc CAMSS_CSI2PIX_CLK>, - <&mmcc CAMSS_CSI2RDI_CLK>, - <&mmcc CAMSS_CSI3_AHB_CLK>, - <&mmcc CAMSS_CSI3_CLK>, - <&mmcc CAMSS_CSI3PHY_CLK>, - <&mmcc CAMSS_CSI3PIX_CLK>, - <&mmcc CAMSS_CSI3RDI_CLK>, - <&mmcc CAMSS_AHB_CLK>, - <&mmcc CAMSS_VFE0_CLK>, - <&mmcc CAMSS_CSI_VFE0_CLK>, - <&mmcc CAMSS_VFE0_AHB_CLK>, - <&mmcc CAMSS_VFE0_STREAM_CLK>, - <&mmcc CAMSS_VFE1_CLK>, - <&mmcc CAMSS_CSI_VFE1_CLK>, - <&mmcc CAMSS_VFE1_AHB_CLK>, - <&mmcc CAMSS_VFE1_STREAM_CLK>, - <&mmcc CAMSS_VFE_AHB_CLK>, - <&mmcc CAMSS_VFE_AXI_CLK>; - clock-names = "top_ahb", - "ispif_ahb", - "csiphy0_timer", - "csiphy1_timer", - "csiphy2_timer", - "csi0_ahb", - "csi0", - "csi0_phy", - "csi0_pix", - "csi0_rdi", - "csi1_ahb", - "csi1", - "csi1_phy", - "csi1_pix", - "csi1_rdi", - "csi2_ahb", - "csi2", - "csi2_phy", - "csi2_pix", - "csi2_rdi", - "csi3_ahb", - "csi3", - "csi3_phy", - "csi3_pix", - "csi3_rdi", - "ahb", - "vfe0", - "csi_vfe0", - "vfe0_ahb", - "vfe0_stream", - "vfe1", - "csi_vfe1", - "vfe1_ahb", - "vfe1_stream", - "vfe_ahb", - "vfe_axi"; - iommus = <&vfe_smmu 0>, - <&vfe_smmu 1>, - <&vfe_smmu 2>, - <&vfe_smmu 3>; - status = "disabled"; - ports { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - adreno_smmu: iommu@b40000 { - compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; - reg = <0x00b40000 0x10000>; - - #global-interrupts = <1>; - interrupts = , - , - ; - #iommu-cells = <1>; - - clocks = <&mmcc GPU_AHB_CLK>, - <&gcc GCC_MMSS_BIMC_GFX_CLK>; - clock-names = "iface", "bus"; - - power-domains = <&mmcc GPU_GDSC>; - }; - - video-codec@c00000 { - compatible = "qcom,msm8996-venus"; - reg = <0x00c00000 0xff000>; - interrupts = ; - power-domains = <&mmcc VENUS_GDSC>; - clocks = <&mmcc VIDEO_CORE_CLK>, - <&mmcc VIDEO_AHB_CLK>, - <&mmcc VIDEO_AXI_CLK>, - <&mmcc VIDEO_MAXI_CLK>; - clock-names = "core", "iface", "bus", "mbus"; - iommus = <&venus_smmu 0x00>, - <&venus_smmu 0x01>, - <&venus_smmu 0x0a>, - <&venus_smmu 0x07>, - <&venus_smmu 0x0e>, - <&venus_smmu 0x0f>, - <&venus_smmu 0x08>, - <&venus_smmu 0x09>, - <&venus_smmu 0x0b>, - <&venus_smmu 0x0c>, - <&venus_smmu 0x0d>, - <&venus_smmu 0x10>, - <&venus_smmu 0x11>, - <&venus_smmu 0x21>, - <&venus_smmu 0x28>, - <&venus_smmu 0x29>, - <&venus_smmu 0x2b>, - <&venus_smmu 0x2c>, - <&venus_smmu 0x2d>, - <&venus_smmu 0x31>; - memory-region = <&venus_region>; - status = "okay"; - - video-decoder { - compatible = "venus-decoder"; - clocks = <&mmcc VIDEO_SUBCORE0_CLK>; - clock-names = "core"; - power-domains = <&mmcc VENUS_CORE0_GDSC>; - }; - - video-encoder { - compatible = "venus-encoder"; - clocks = <&mmcc VIDEO_SUBCORE1_CLK>; - clock-names = "core"; - power-domains = <&mmcc VENUS_CORE1_GDSC>; - }; - }; - - mdp_smmu: iommu@d00000 { - compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; - reg = <0x00d00000 0x10000>; - - #global-interrupts = <1>; - interrupts = , - , - ; - #iommu-cells = <1>; - clocks = <&mmcc SMMU_MDP_AHB_CLK>, - <&mmcc SMMU_MDP_AXI_CLK>; - clock-names = "iface", "bus"; - - power-domains = <&mmcc MDSS_GDSC>; - }; - - venus_smmu: iommu@d40000 { - compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; - reg = <0x00d40000 0x20000>; - #global-interrupts = <1>; - interrupts = , - , - , - , - , - , - , - ; - power-domains = <&mmcc MMAGIC_VIDEO_GDSC>; - clocks = <&mmcc SMMU_VIDEO_AHB_CLK>, - <&mmcc SMMU_VIDEO_AXI_CLK>; - clock-names = "iface", "bus"; - #iommu-cells = <1>; - status = "okay"; - }; - - vfe_smmu: iommu@da0000 { - compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; - reg = <0x00da0000 0x10000>; - - #global-interrupts = <1>; - interrupts = , - , - ; - power-domains = <&mmcc MMAGIC_CAMSS_GDSC>; - clocks = <&mmcc SMMU_VFE_AHB_CLK>, - <&mmcc SMMU_VFE_AXI_CLK>; - clock-names = "iface", - "bus"; - #iommu-cells = <1>; - }; - - lpass_q6_smmu: iommu@1600000 { - compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; - reg = <0x01600000 0x20000>; - #iommu-cells = <1>; - power-domains = <&gcc HLOS1_VOTE_LPASS_CORE_GDSC>; - - #global-interrupts = <1>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - ; - - clocks = <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>, - <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>; - clock-names = "iface", "bus"; - }; - - stm@3002000 { - compatible = "arm,coresight-stm", "arm,primecell"; - reg = <0x3002000 0x1000>, - <0x8280000 0x180000>; - reg-names = "stm-base", "stm-stimulus-base"; - - clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - out-ports { - port { - stm_out: endpoint { - remote-endpoint = - <&funnel0_in>; - }; - }; - }; - }; - - tpiu@3020000 { - compatible = "arm,coresight-tpiu", "arm,primecell"; - reg = <0x3020000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - in-ports { - port { - tpiu_in: endpoint { - remote-endpoint = - <&replicator_out1>; - }; - }; - }; - }; - - funnel@3021000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0x3021000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@7 { - reg = <7>; - funnel0_in: endpoint { - remote-endpoint = - <&stm_out>; - }; - }; - }; - - out-ports { - port { - funnel0_out: endpoint { - remote-endpoint = - <&merge_funnel_in0>; - }; - }; - }; - }; - - funnel@3022000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0x3022000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@6 { - reg = <6>; - funnel1_in: endpoint { - remote-endpoint = - <&apss_merge_funnel_out>; - }; - }; - }; - - out-ports { - port { - funnel1_out: endpoint { - remote-endpoint = - <&merge_funnel_in1>; - }; - }; - }; - }; - - funnel@3023000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0x3023000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - - out-ports { - port { - funnel2_out: endpoint { - remote-endpoint = - <&merge_funnel_in2>; - }; - }; - }; - }; - - funnel@3025000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0x3025000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - merge_funnel_in0: endpoint { - remote-endpoint = - <&funnel0_out>; - }; - }; - - port@1 { - reg = <1>; - merge_funnel_in1: endpoint { - remote-endpoint = - <&funnel1_out>; - }; - }; - - port@2 { - reg = <2>; - merge_funnel_in2: endpoint { - remote-endpoint = - <&funnel2_out>; - }; - }; - }; - - out-ports { - port { - merge_funnel_out: endpoint { - remote-endpoint = - <&etf_in>; - }; - }; - }; - }; - - replicator@3026000 { - compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; - reg = <0x3026000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - in-ports { - port { - replicator_in: endpoint { - remote-endpoint = - <&etf_out>; - }; - }; - }; - - out-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - replicator_out0: endpoint { - remote-endpoint = - <&etr_in>; - }; - }; - - port@1 { - reg = <1>; - replicator_out1: endpoint { - remote-endpoint = - <&tpiu_in>; - }; - }; - }; - }; - - etf@3027000 { - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0x3027000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - in-ports { - port { - etf_in: endpoint { - remote-endpoint = - <&merge_funnel_out>; - }; - }; - }; - - out-ports { - port { - etf_out: endpoint { - remote-endpoint = - <&replicator_in>; - }; - }; - }; - }; - - etr@3028000 { - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0x3028000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - arm,scatter-gather; - - in-ports { - port { - etr_in: endpoint { - remote-endpoint = - <&replicator_out0>; - }; - }; - }; - }; - - debug@3810000 { - compatible = "arm,coresight-cpu-debug", "arm,primecell"; - reg = <0x3810000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>; - clock-names = "apb_pclk"; - - cpu = <&CPU0>; - }; - - etm@3840000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0x3840000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - cpu = <&CPU0>; - - out-ports { - port { - etm0_out: endpoint { - remote-endpoint = - <&apss_funnel0_in0>; - }; - }; - }; - }; - - debug@3910000 { - compatible = "arm,coresight-cpu-debug", "arm,primecell"; - reg = <0x3910000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>; - clock-names = "apb_pclk"; - - cpu = <&CPU1>; - }; - - etm@3940000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0x3940000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - cpu = <&CPU1>; - - out-ports { - port { - etm1_out: endpoint { - remote-endpoint = - <&apss_funnel0_in1>; - }; - }; - }; - }; - - funnel@39b0000 { /* APSS Funnel 0 */ - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0x39b0000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - apss_funnel0_in0: endpoint { - remote-endpoint = <&etm0_out>; - }; - }; - - port@1 { - reg = <1>; - apss_funnel0_in1: endpoint { - remote-endpoint = <&etm1_out>; - }; - }; - }; - - out-ports { - port { - apss_funnel0_out: endpoint { - remote-endpoint = - <&apss_merge_funnel_in0>; - }; - }; - }; - }; - - debug@3a10000 { - compatible = "arm,coresight-cpu-debug", "arm,primecell"; - reg = <0x3a10000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>; - clock-names = "apb_pclk"; - - cpu = <&CPU2>; - }; - - etm@3a40000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0x3a40000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - cpu = <&CPU2>; - - out-ports { - port { - etm2_out: endpoint { - remote-endpoint = - <&apss_funnel1_in0>; - }; - }; - }; - }; - - debug@3b10000 { - compatible = "arm,coresight-cpu-debug", "arm,primecell"; - reg = <0x3b10000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>; - clock-names = "apb_pclk"; - - cpu = <&CPU3>; - }; - - etm@3b40000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0x3b40000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - cpu = <&CPU3>; - - out-ports { - port { - etm3_out: endpoint { - remote-endpoint = - <&apss_funnel1_in1>; - }; - }; - }; - }; - - funnel@3bb0000 { /* APSS Funnel 1 */ - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0x3bb0000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - apss_funnel1_in0: endpoint { - remote-endpoint = <&etm2_out>; - }; - }; - - port@1 { - reg = <1>; - apss_funnel1_in1: endpoint { - remote-endpoint = <&etm3_out>; - }; - }; - }; - - out-ports { - port { - apss_funnel1_out: endpoint { - remote-endpoint = - <&apss_merge_funnel_in1>; - }; - }; - }; - }; - - funnel@3bc0000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0x3bc0000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - apss_merge_funnel_in0: endpoint { - remote-endpoint = - <&apss_funnel0_out>; - }; - }; - - port@1 { - reg = <1>; - apss_merge_funnel_in1: endpoint { - remote-endpoint = - <&apss_funnel1_out>; - }; - }; - }; - - out-ports { - port { - apss_merge_funnel_out: endpoint { - remote-endpoint = - <&funnel1_in>; - }; - }; - }; - }; - kryocc: clock-controller@6400000 { - compatible = "qcom,apcc-msm8996"; - reg = <0x06400000 0x90000>; - #clock-cells = <1>; - }; - - usb3: usb@6af8800 { - compatible = "qcom,msm8996-dwc3", "qcom,dwc3"; - reg = <0x06af8800 0x400>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>, - <&gcc GCC_USB30_MASTER_CLK>, - <&gcc GCC_AGGRE2_USB3_AXI_CLK>, - <&gcc GCC_USB30_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_SLEEP_CLK>, - <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>; - - assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_MASTER_CLK>; - assigned-clock-rates = <19200000>, <120000000>; - - power-domains = <&gcc USB30_GDSC>; - status = "disabled"; - - dwc3@6a00000 { - compatible = "snps,dwc3"; - reg = <0x06a00000 0xcc00>; - interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>; - phys = <&hsusb_phy1>, <&ssusb_phy_0>; - phy-names = "usb2-phy", "usb3-phy"; - snps,dis_u2_susphy_quirk; - snps,dis_enblslpm_quirk; - }; - }; - - usb3phy: phy@7410000 { - compatible = "qcom,msm8996-qmp-usb3-phy"; - reg = <0x07410000 0x1c4>; - #clock-cells = <1>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - clocks = <&gcc GCC_USB3_PHY_AUX_CLK>, - <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, - <&gcc GCC_USB3_CLKREF_CLK>; - clock-names = "aux", "cfg_ahb", "ref"; - - resets = <&gcc GCC_USB3_PHY_BCR>, - <&gcc GCC_USB3PHY_PHY_BCR>; - reset-names = "phy", "common"; - status = "disabled"; - - ssusb_phy_0: lane@7410200 { - reg = <0x07410200 0x200>, - <0x07410400 0x130>, - <0x07410600 0x1a8>; - #phy-cells = <0>; - - clock-output-names = "usb3_phy_pipe_clk_src"; - clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>; - clock-names = "pipe0"; - }; - }; - - hsusb_phy1: phy@7411000 { - compatible = "qcom,msm8996-qusb2-phy"; - reg = <0x07411000 0x180>; - #phy-cells = <0>; - - clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, - <&gcc GCC_RX1_USB2_CLKREF_CLK>; - clock-names = "cfg_ahb", "ref"; - - resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; - nvmem-cells = <&qusb2p_hstx_trim>; - status = "disabled"; - }; - - hsusb_phy2: phy@7412000 { - compatible = "qcom,msm8996-qusb2-phy"; - reg = <0x07412000 0x180>; - #phy-cells = <0>; - - clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, - <&gcc GCC_RX2_USB2_CLKREF_CLK>; - clock-names = "cfg_ahb", "ref"; - - resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; - nvmem-cells = <&qusb2s_hstx_trim>; - status = "disabled"; - }; - - sdhc2: sdhci@74a4900 { - status = "disabled"; - compatible = "qcom,sdhci-msm-v4"; - reg = <0x074a4900 0x314>, <0x074a4000 0x800>; - reg-names = "hc_mem", "core_mem"; - - interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>, - <0 221 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "hc_irq", "pwr_irq"; - - clock-names = "iface", "core", "xo"; - clocks = <&gcc GCC_SDCC2_AHB_CLK>, - <&gcc GCC_SDCC2_APPS_CLK>, - <&xo_board>; - bus-width = <4>; - }; - - blsp1_uart1: serial@7570000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0x07570000 0x1000>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - - blsp1_spi0: spi@7575000 { - compatible = "qcom,spi-qup-v2.2.1"; - reg = <0x07575000 0x600>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp1_spi0_default>; - pinctrl-1 = <&blsp1_spi0_sleep>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - blsp1_i2c2: i2c@7577000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x07577000 0x1000>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; - clock-names = "iface", "core"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp1_i2c2_default>; - pinctrl-1 = <&blsp1_i2c2_sleep>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - blsp2_uart1: serial@75b0000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0x075b0000 0x1000>; - interrupts = ; - clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, - <&gcc GCC_BLSP2_AHB_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - - blsp2_uart2: serial@75b1000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0x075b1000 0x1000>; - interrupts = ; - clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>, - <&gcc GCC_BLSP2_AHB_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - - blsp2_i2c0: i2c@75b5000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x075b5000 0x1000>; - interrupts = ; - clocks = <&gcc GCC_BLSP2_AHB_CLK>, - <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>; - clock-names = "iface", "core"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp2_i2c0_default>; - pinctrl-1 = <&blsp2_i2c0_sleep>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - blsp2_i2c1: i2c@75b6000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x075b6000 0x1000>; - interrupts = ; - clocks = <&gcc GCC_BLSP2_AHB_CLK>, - <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>; - clock-names = "iface", "core"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp2_i2c1_default>; - pinctrl-1 = <&blsp2_i2c1_sleep>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - blsp2_spi5: spi@75ba000{ - compatible = "qcom,spi-qup-v2.2.1"; - reg = <0x075ba000 0x600>; - interrupts = ; - clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>, - <&gcc GCC_BLSP2_AHB_CLK>; - clock-names = "core", "iface"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp2_spi5_default>; - pinctrl-1 = <&blsp2_spi5_sleep>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - usb2: usb@76f8800 { - compatible = "qcom,msm8996-dwc3", "qcom,dwc3"; - reg = <0x076f8800 0x400>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>, - <&gcc GCC_USB20_MASTER_CLK>, - <&gcc GCC_USB20_MOCK_UTMI_CLK>, - <&gcc GCC_USB20_SLEEP_CLK>, - <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>; - - assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, - <&gcc GCC_USB20_MASTER_CLK>; - assigned-clock-rates = <19200000>, <60000000>; - - power-domains = <&gcc USB30_GDSC>; - status = "disabled"; - - dwc3@7600000 { - compatible = "snps,dwc3"; - reg = <0x07600000 0xcc00>; - interrupts = <0 138 IRQ_TYPE_LEVEL_HIGH>; - phys = <&hsusb_phy2>; - phy-names = "usb2-phy"; - snps,dis_u2_susphy_quirk; - snps,dis_enblslpm_quirk; - }; - }; - - slimbam: dma@9184000 { - compatible = "qcom,bam-v1.7.0"; - qcom,controlled-remotely; - reg = <0x09184000 0x32000>; - num-channels = <31>; - interrupts = <0 164 IRQ_TYPE_LEVEL_HIGH>; - #dma-cells = <1>; - qcom,ee = <1>; - qcom,num-ees = <2>; - }; - - slim_msm: slim@91c0000 { - compatible = "qcom,slim-ngd-v1.5.0"; - reg = <0x091c0000 0x2C000>; - reg-names = "ctrl"; - interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&slimbam 3>, <&slimbam 4>, - <&slimbam 5>, <&slimbam 6>; - dma-names = "rx", "tx", "tx2", "rx2"; - #address-cells = <1>; - #size-cells = <0>; - ngd@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <1>; - - tasha_ifd: tas-ifd { - compatible = "slim217,1a0"; - reg = <0 0>; - }; - - wcd9335: codec@1{ - pinctrl-0 = <&cdc_reset_active &wcd_intr_default>; - pinctrl-names = "default"; - - compatible = "slim217,1a0"; - reg = <1 0>; - - interrupt-parent = <&msmgpio>; - interrupts = <54 IRQ_TYPE_LEVEL_HIGH>, - <53 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "intr1", "intr2"; - interrupt-controller; - #interrupt-cells = <1>; - reset-gpios = <&msmgpio 64 0>; - - slim-ifc-dev = <&tasha_ifd>; - - #sound-dai-cells = <1>; - }; - }; - }; - - adsp_pil: remoteproc@9300000 { - compatible = "qcom,msm8996-adsp-pil"; - reg = <0x09300000 0x80000>; - - interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>, - <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, - <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, - <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, - <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", - "handover", "stop-ack"; - - clocks = <&xo_board>; - clock-names = "xo"; - - memory-region = <&adsp_region>; - - qcom,smem-states = <&smp2p_adsp_out 0>; - qcom,smem-state-names = "stop"; - - smd-edge { - interrupts = ; - - label = "lpass"; - mboxes = <&apcs_glb 8>; - qcom,smd-edge = <1>; - qcom,remote-pid = <2>; - #address-cells = <1>; - #size-cells = <0>; - apr { - power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>; - compatible = "qcom,apr-v2"; - qcom,smd-channels = "apr_audio_svc"; - qcom,apr-domain = ; - #address-cells = <1>; - #size-cells = <0>; - - q6core { - reg = ; - compatible = "qcom,q6core"; - }; - - q6afe: q6afe { - compatible = "qcom,q6afe"; - reg = ; - q6afedai: dais { - compatible = "qcom,q6afe-dais"; - #address-cells = <1>; - #size-cells = <0>; - #sound-dai-cells = <1>; - hdmi@1 { - reg = <1>; - }; - }; - }; - - q6asm: q6asm { - compatible = "qcom,q6asm"; - reg = ; - q6asmdai: dais { - compatible = "qcom,q6asm-dais"; - #sound-dai-cells = <1>; - iommus = <&lpass_q6_smmu 1>; - }; - }; - - q6adm: q6adm { - compatible = "qcom,q6adm"; - reg = ; - q6routing: routing { - compatible = "qcom,q6adm-routing"; - #sound-dai-cells = <0>; - }; - }; - }; - - }; - }; - - apcs_glb: mailbox@9820000 { - compatible = "qcom,msm8996-apcs-hmss-global"; - reg = <0x09820000 0x1000>; - - #mbox-cells = <1>; - }; - - timer@9840000 { - #address-cells = <1>; - #size-cells = <1>; - ranges; - compatible = "arm,armv7-timer-mem"; - reg = <0x09840000 0x1000>; - clock-frequency = <19200000>; - - frame@9850000 { - frame-number = <0>; - interrupts = , - ; - reg = <0x09850000 0x1000>, - <0x09860000 0x1000>; - }; - - frame@9870000 { - frame-number = <1>; - interrupts = ; - reg = <0x09870000 0x1000>; - status = "disabled"; - }; - - frame@9880000 { - frame-number = <2>; - interrupts = ; - reg = <0x09880000 0x1000>; - status = "disabled"; - }; - - frame@9890000 { - frame-number = <3>; - interrupts = ; - reg = <0x09890000 0x1000>; - status = "disabled"; - }; - - frame@98a0000 { - frame-number = <4>; - interrupts = ; - reg = <0x098a0000 0x1000>; - status = "disabled"; - }; - - frame@98b0000 { - frame-number = <5>; - interrupts = ; - reg = <0x098b0000 0x1000>; - status = "disabled"; - }; - - frame@98c0000 { - frame-number = <6>; - interrupts = ; - reg = <0x098c0000 0x1000>; - status = "disabled"; - }; - }; - - saw3: syscon@9a10000 { - compatible = "syscon"; - reg = <0x09a10000 0x1000>; - }; - - intc: interrupt-controller@9bc0000 { - compatible = "qcom,msm8996-gic-v3", "arm,gic-v3"; - #interrupt-cells = <3>; - interrupt-controller; - #redistributor-regions = <1>; - redistributor-stride = <0x0 0x40000>; - reg = <0x09bc0000 0x10000>, - <0x09c00000 0x100000>; - interrupts = ; - }; - }; - - sound: sound { - }; - - thermal-zones { - cpu0-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 3>; - - trips { - cpu0_alert0: trip-point@0 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu0_crit: cpu_crit { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - cpu1-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 5>; - - trips { - cpu1_alert0: trip-point@0 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu1_crit: cpu_crit { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - cpu2-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 8>; - - trips { - cpu2_alert0: trip-point@0 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu2_crit: cpu_crit { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - cpu3-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 10>; - - trips { - cpu3_alert0: trip-point@0 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu3_crit: cpu_crit { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - gpu-thermal-top { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 6>; - - trips { - gpu1_alert0: trip-point@0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - gpu-thermal-bottom { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 7>; - - trips { - gpu2_alert0: trip-point@0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - m4m-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 1>; - - trips { - m4m_alert0: trip-point@0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - l3-or-venus-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 2>; - - trips { - l3_or_venus_alert0: trip-point@0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - cluster0-l2-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 7>; - - trips { - cluster0_l2_alert0: trip-point@0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - cluster1-l2-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 12>; - - trips { - cluster1_l2_alert0: trip-point@0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - camera-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 1>; - - trips { - camera_alert0: trip-point@0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - q6-dsp-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 2>; - - trips { - q6_dsp_alert0: trip-point@0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - mem-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 3>; - - trips { - mem_alert0: trip-point@0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - modemtx-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 4>; - - trips { - modemtx_alert0: trip-point@0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; -}; -#include "msm8996-pins.dtsi" diff --git a/sys/gnu/dts/arm64/qcom/msm8998-asus-novago-tp370ql.dts b/sys/gnu/dts/arm64/qcom/msm8998-asus-novago-tp370ql.dts deleted file mode 100644 index db5821be1e2..00000000000 --- a/sys/gnu/dts/arm64/qcom/msm8998-asus-novago-tp370ql.dts +++ /dev/null @@ -1,47 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* Copyright (c) 2019, Jeffrey Hugo. All rights reserved. */ - -/dts-v1/; - -#include "msm8998-clamshell.dtsi" - -/ { - model = "Asus NovaGo TP370QL"; - compatible = "asus,novago-tp370ql", "qcom,msm8998"; -}; - -&blsp1_i2c6 { - status = "okay"; - - touchpad@15 { - compatible = "hid-over-i2c"; - interrupt-parent = <&tlmm>; - interrupts = <0x7b IRQ_TYPE_LEVEL_LOW>; - reg = <0x15>; - hid-descr-addr = <0x0001>; - - pinctrl-names = "default"; - pinctrl-0 = <&touchpad>; - }; - - keyboard@3a { - compatible = "hid-over-i2c"; - interrupt-parent = <&tlmm>; - interrupts = <0x25 IRQ_TYPE_LEVEL_LOW>; - reg = <0x3a>; - hid-descr-addr = <0x0001>; - }; -}; - -&sdhc2 { - cd-gpios = <&tlmm 95 GPIO_ACTIVE_HIGH>; -}; - -&tlmm { - touchpad: touchpad { - config { - pins = "gpio123"; - bias-pull-up; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/qcom/msm8998-clamshell.dtsi b/sys/gnu/dts/arm64/qcom/msm8998-clamshell.dtsi deleted file mode 100644 index 6ab830d0186..00000000000 --- a/sys/gnu/dts/arm64/qcom/msm8998-clamshell.dtsi +++ /dev/null @@ -1,343 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* Copyright (c) 2019, Jeffrey Hugo. All rights reserved. */ - -/* - * Common include for MSM8998 clamshell devices, ie the Lenovo Miix 630, - * Asus NovaGo TP370QL, and HP Envy x2. All three devices are basically the - * same, with differences in peripherals. - */ - -#include "msm8998.dtsi" -#include "pm8998.dtsi" -#include "pm8005.dtsi" - -/ { - chosen { - }; - - vph_pwr: vph-pwr-regulator { - compatible = "regulator-fixed"; - regulator-name = "vph_pwr"; - regulator-always-on; - regulator-boot-on; - }; -}; - -&blsp1_uart3 { - status = "okay"; - - bluetooth { - compatible = "qcom,wcn3990-bt"; - - vddio-supply = <&vreg_s4a_1p8>; - vddxo-supply = <&vreg_l7a_1p8>; - vddrf-supply = <&vreg_l17a_1p3>; - vddch0-supply = <&vreg_l25a_3p3>; - max-speed = <3200000>; - }; -}; - -/* - * The laptop FW does not appear to support the retention state as it is - * not advertised as enabled in ACPI, and enabling it in DT can cause boot - * hangs. - */ -&CPU0 { - cpu-idle-states = <&LITTLE_CPU_SLEEP_1>; -}; - -&CPU1 { - cpu-idle-states = <&LITTLE_CPU_SLEEP_1>; -}; - -&CPU2 { - cpu-idle-states = <&LITTLE_CPU_SLEEP_1>; -}; - -&CPU3 { - cpu-idle-states = <&LITTLE_CPU_SLEEP_1>; -}; - -&CPU4 { - cpu-idle-states = <&BIG_CPU_SLEEP_1>; -}; - -&CPU5 { - cpu-idle-states = <&BIG_CPU_SLEEP_1>; -}; - -&CPU6 { - cpu-idle-states = <&BIG_CPU_SLEEP_1>; -}; - -&CPU7 { - cpu-idle-states = <&BIG_CPU_SLEEP_1>; -}; - -&pm8005_lsid1 { - pm8005-regulators { - compatible = "qcom,pm8005-regulators"; - - vdd_s1-supply = <&vph_pwr>; - - pm8005_s1: s1 { /* VDD_GFX supply */ - regulator-min-microvolt = <524000>; - regulator-max-microvolt = <1100000>; - regulator-enable-ramp-delay = <500>; - - /* hack until we rig up the gpu consumer */ - regulator-always-on; - }; - }; -}; - -&qusb2phy { - status = "okay"; - - vdda-pll-supply = <&vreg_l12a_1p8>; - vdda-phy-dpdm-supply = <&vreg_l24a_3p075>; -}; - -&rpm_requests { - pm8998-regulators { - compatible = "qcom,rpm-pm8998-regulators"; - - vdd_s1-supply = <&vph_pwr>; - vdd_s2-supply = <&vph_pwr>; - vdd_s3-supply = <&vph_pwr>; - vdd_s4-supply = <&vph_pwr>; - vdd_s5-supply = <&vph_pwr>; - vdd_s6-supply = <&vph_pwr>; - vdd_s7-supply = <&vph_pwr>; - vdd_s8-supply = <&vph_pwr>; - vdd_s9-supply = <&vph_pwr>; - vdd_s10-supply = <&vph_pwr>; - vdd_s11-supply = <&vph_pwr>; - vdd_s12-supply = <&vph_pwr>; - vdd_s13-supply = <&vph_pwr>; - vdd_l1_l27-supply = <&vreg_s7a_1p025>; - vdd_l2_l8_l17-supply = <&vreg_s3a_1p35>; - vdd_l3_l11-supply = <&vreg_s7a_1p025>; - vdd_l4_l5-supply = <&vreg_s7a_1p025>; - vdd_l6-supply = <&vreg_s5a_2p04>; - vdd_l7_l12_l14_l15-supply = <&vreg_s5a_2p04>; - vdd_l9-supply = <&vph_pwr>; - vdd_l10_l23_l25-supply = <&vph_pwr>; - vdd_l13_l19_l21-supply = <&vph_pwr>; - vdd_l16_l28-supply = <&vph_pwr>; - vdd_l18_l22-supply = <&vph_pwr>; - vdd_l20_l24-supply = <&vph_pwr>; - vdd_l26-supply = <&vreg_s3a_1p35>; - vdd_lvs1_lvs2-supply = <&vreg_s4a_1p8>; - - vreg_s3a_1p35: s3 { - regulator-min-microvolt = <1352000>; - regulator-max-microvolt = <1352000>; - }; - vreg_s4a_1p8: s4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-allow-set-load; - }; - vreg_s5a_2p04: s5 { - regulator-min-microvolt = <1904000>; - regulator-max-microvolt = <2040000>; - }; - vreg_s7a_1p025: s7 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1028000>; - }; - vreg_l1a_0p875: l1 { - regulator-min-microvolt = <880000>; - regulator-max-microvolt = <880000>; - regulator-allow-set-load; - }; - vreg_l2a_1p2: l2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-allow-set-load; - }; - vreg_l3a_1p0: l3 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - }; - vreg_l5a_0p8: l5 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <800000>; - }; - vreg_l6a_1p8: l6 { - regulator-min-microvolt = <1808000>; - regulator-max-microvolt = <1808000>; - }; - vreg_l7a_1p8: l7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-allow-set-load; - }; - vreg_l8a_1p2: l8 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - vreg_l9a_1p8: l9 { - regulator-min-microvolt = <1808000>; - regulator-max-microvolt = <2960000>; - }; - vreg_l10a_1p8: l10 { - regulator-min-microvolt = <1808000>; - regulator-max-microvolt = <2960000>; - }; - vreg_l11a_1p0: l11 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - }; - vreg_l12a_1p8: l12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - vreg_l13a_2p95: l13 { - regulator-min-microvolt = <1808000>; - regulator-max-microvolt = <2960000>; - }; - vreg_l14a_1p88: l14 { - regulator-min-microvolt = <1880000>; - regulator-max-microvolt = <1880000>; - }; - vreg_15a_1p8: l15 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - vreg_l16a_2p7: l16 { - regulator-min-microvolt = <2704000>; - regulator-max-microvolt = <2704000>; - }; - vreg_l17a_1p3: l17 { - regulator-min-microvolt = <1304000>; - regulator-max-microvolt = <1304000>; - regulator-allow-set-load; - }; - vreg_l18a_2p7: l18 { - regulator-min-microvolt = <2704000>; - regulator-max-microvolt = <2704000>; - }; - vreg_l19a_3p0: l19 { - regulator-min-microvolt = <3008000>; - regulator-max-microvolt = <3008000>; - }; - vreg_l20a_2p95: l20 { - regulator-min-microvolt = <2960000>; - regulator-max-microvolt = <2960000>; - regulator-allow-set-load; - }; - vreg_l21a_2p95: l21 { - regulator-min-microvolt = <2960000>; - regulator-max-microvolt = <2960000>; - regulator-allow-set-load; - regulator-system-load = <800000>; - }; - vreg_l22a_2p85: l22 { - regulator-min-microvolt = <2864000>; - regulator-max-microvolt = <2864000>; - }; - vreg_l23a_3p3: l23 { - regulator-min-microvolt = <3312000>; - regulator-max-microvolt = <3312000>; - }; - vreg_l24a_3p075: l24 { - regulator-min-microvolt = <3088000>; - regulator-max-microvolt = <3088000>; - }; - vreg_l25a_3p3: l25 { - regulator-min-microvolt = <3104000>; - regulator-max-microvolt = <3312000>; - regulator-allow-set-load; - }; - vreg_l26a_1p2: l26 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - vreg_l28_3p0: l28 { - regulator-min-microvolt = <3008000>; - regulator-max-microvolt = <3008000>; - }; - - vreg_lvs1a_1p8: lvs1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vreg_lvs2a_1p8: lvs2 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - }; -}; - -&tlmm { - gpio-reserved-ranges = <0 4>, <81 4>; - - touchpad: touchpad { - config { - pins = "gpio123"; - bias-pull-up; /* pull up */ - }; - }; -}; - -&sdhc2 { - status = "okay"; - - vmmc-supply = <&vreg_l21a_2p95>; - vqmmc-supply = <&vreg_l13a_2p95>; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; - pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; -}; - -&usb3 { - status = "okay"; -}; - -&usb3_dwc3 { - dr_mode = "host"; /* Force to host until we have Type-C hooked up */ -}; - -&usb3phy { - status = "okay"; - - vdda-phy-supply = <&vreg_l1a_0p875>; - vdda-pll-supply = <&vreg_l2a_1p2>; -}; - -&wifi { - status = "okay"; - - vdd-0.8-cx-mx-supply = <&vreg_l5a_0p8>; - vdd-1.8-xo-supply = <&vreg_l7a_1p8>; - vdd-1.3-rfa-supply = <&vreg_l17a_1p3>; - vdd-3.3-ch0-supply = <&vreg_l25a_3p3>; -}; - -/* PINCTRL - board-specific pinctrl */ -&blsp1_uart3_on { - rx { - /delete-property/ bias-disable; - /* - * Configure a pull-up on 45 (RX). This is needed to - * avoid garbage data when the TX pin of the Bluetooth - * module is in tri-state (module powered off or not - * driving the signal yet). - */ - bias-pull-up; - }; - - cts { - /delete-property/ bias-disable; - /* - * Configure a pull-down on 47 (CTS) to match the pull - * of the Bluetooth module. - */ - bias-pull-down; - }; -}; diff --git a/sys/gnu/dts/arm64/qcom/msm8998-hp-envy-x2.dts b/sys/gnu/dts/arm64/qcom/msm8998-hp-envy-x2.dts deleted file mode 100644 index 24073127091..00000000000 --- a/sys/gnu/dts/arm64/qcom/msm8998-hp-envy-x2.dts +++ /dev/null @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* Copyright (c) 2019, Jeffrey Hugo. All rights reserved. */ - -/dts-v1/; - -#include "msm8998-clamshell.dtsi" - -/ { - model = "HP Envy x2"; - compatible = "hp,envy-x2", "qcom,msm8998"; -}; - -&blsp1_i2c6 { - status = "okay"; - - keyboard@3a { - compatible = "hid-over-i2c"; - interrupt-parent = <&tlmm>; - interrupts = <0x79 IRQ_TYPE_LEVEL_LOW>; - reg = <0x3a>; - hid-descr-addr = <0x0001>; - - pinctrl-names = "default"; - pinctrl-0 = <&touchpad>; - }; -}; - -&sdhc2 { - cd-gpios = <&tlmm 95 GPIO_ACTIVE_LOW>; -}; diff --git a/sys/gnu/dts/arm64/qcom/msm8998-lenovo-miix-630.dts b/sys/gnu/dts/arm64/qcom/msm8998-lenovo-miix-630.dts deleted file mode 100644 index 407c6a32911..00000000000 --- a/sys/gnu/dts/arm64/qcom/msm8998-lenovo-miix-630.dts +++ /dev/null @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* Copyright (c) 2019, Jeffrey Hugo. All rights reserved. */ - -/dts-v1/; - -#include "msm8998-clamshell.dtsi" - -/ { - model = "Lenovo Miix 630"; - compatible = "lenovo,miix-630", "qcom,msm8998"; -}; - -&blsp1_i2c6 { - status = "okay"; - - keyboard@3a { - compatible = "hid-over-i2c"; - interrupt-parent = <&tlmm>; - interrupts = <0x79 IRQ_TYPE_LEVEL_LOW>; - reg = <0x3a>; - hid-descr-addr = <0x0001>; - - pinctrl-names = "default"; - pinctrl-0 = <&touchpad>; - }; -}; - -&sdhc2 { - cd-gpios = <&tlmm 95 GPIO_ACTIVE_HIGH>; -}; diff --git a/sys/gnu/dts/arm64/qcom/msm8998-mtp.dts b/sys/gnu/dts/arm64/qcom/msm8998-mtp.dts deleted file mode 100644 index 66540d2ca13..00000000000 --- a/sys/gnu/dts/arm64/qcom/msm8998-mtp.dts +++ /dev/null @@ -1,13 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* Copyright (c) 2016, The Linux Foundation. All rights reserved. */ - -/dts-v1/; - -#include "msm8998-mtp.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. MSM8998 v1 MTP"; - compatible = "qcom,msm8998-mtp"; - - qcom,board-id = <8 0>; -}; diff --git a/sys/gnu/dts/arm64/qcom/msm8998-mtp.dtsi b/sys/gnu/dts/arm64/qcom/msm8998-mtp.dtsi deleted file mode 100644 index 0e0b9bc1294..00000000000 --- a/sys/gnu/dts/arm64/qcom/msm8998-mtp.dtsi +++ /dev/null @@ -1,407 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* Copyright (c) 2016, The Linux Foundation. All rights reserved. */ - -#include "msm8998.dtsi" -#include "pm8998.dtsi" -#include "pmi8998.dtsi" -#include "pm8005.dtsi" - -/ { - aliases { - serial0 = &blsp2_uart1; - serial1 = &blsp1_uart3; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - vph_pwr: vph-pwr-regulator { - compatible = "regulator-fixed"; - regulator-name = "vph_pwr"; - regulator-always-on; - regulator-boot-on; - }; -}; - -&blsp1_uart3 { - status = "okay"; - - bluetooth { - compatible = "qcom,wcn3990-bt"; - - vddio-supply = <&vreg_s4a_1p8>; - vddxo-supply = <&vreg_l7a_1p8>; - vddrf-supply = <&vreg_l17a_1p3>; - vddch0-supply = <&vreg_l25a_3p3>; - max-speed = <3200000>; - }; -}; - -&blsp2_uart1 { - status = "okay"; -}; - -&etf { - status = "okay"; -}; - -&etm1 { - status = "okay"; -}; - -&etm2 { - status = "okay"; -}; - -&etm3 { - status = "okay"; -}; - -&etm4 { - status = "okay"; -}; - -&etm5 { - status = "okay"; -}; - -&etm6 { - status = "okay"; -}; - -&etm7 { - status = "okay"; -}; - -&etm8 { - status = "okay"; -}; - -&etr { - status = "okay"; -}; - -&funnel1 { - status = "okay"; -}; - -&funnel2 { - status = "okay"; -}; - -&funnel3 { - status = "okay"; -}; - -&funnel4 { - status = "okay"; -}; - -&funnel5 { - status = "okay"; -}; - -&pm8005_lsid1 { - pm8005-regulators { - compatible = "qcom,pm8005-regulators"; - - vdd_s1-supply = <&vph_pwr>; - - pm8005_s1: s1 { /* VDD_GFX supply */ - regulator-min-microvolt = <524000>; - regulator-max-microvolt = <1100000>; - regulator-enable-ramp-delay = <500>; - - /* hack until we rig up the gpu consumer */ - regulator-always-on; - }; - }; -}; - -&qusb2phy { - status = "okay"; - - vdda-pll-supply = <&vreg_l12a_1p8>; - vdda-phy-dpdm-supply = <&vreg_l24a_3p075>; -}; - -&replicator1 { - status = "okay"; -}; - -&rpm_requests { - pm8998-regulators { - compatible = "qcom,rpm-pm8998-regulators"; - - vdd_s1-supply = <&vph_pwr>; - vdd_s2-supply = <&vph_pwr>; - vdd_s3-supply = <&vph_pwr>; - vdd_s4-supply = <&vph_pwr>; - vdd_s5-supply = <&vph_pwr>; - vdd_s6-supply = <&vph_pwr>; - vdd_s7-supply = <&vph_pwr>; - vdd_s8-supply = <&vph_pwr>; - vdd_s9-supply = <&vph_pwr>; - vdd_s10-supply = <&vph_pwr>; - vdd_s11-supply = <&vph_pwr>; - vdd_s12-supply = <&vph_pwr>; - vdd_s13-supply = <&vph_pwr>; - vdd_l1_l27-supply = <&vreg_s7a_1p025>; - vdd_l2_l8_l17-supply = <&vreg_s3a_1p35>; - vdd_l3_l11-supply = <&vreg_s7a_1p025>; - vdd_l4_l5-supply = <&vreg_s7a_1p025>; - vdd_l6-supply = <&vreg_s5a_2p04>; - vdd_l7_l12_l14_l15-supply = <&vreg_s5a_2p04>; - vdd_l9-supply = <&vreg_bob>; - vdd_l10_l23_l25-supply = <&vreg_bob>; - vdd_l13_l19_l21-supply = <&vreg_bob>; - vdd_l16_l28-supply = <&vreg_bob>; - vdd_l18_l22-supply = <&vreg_bob>; - vdd_l20_l24-supply = <&vreg_bob>; - vdd_l26-supply = <&vreg_s3a_1p35>; - vdd_lvs1_lvs2-supply = <&vreg_s4a_1p8>; - - vreg_s3a_1p35: s3 { - regulator-min-microvolt = <1352000>; - regulator-max-microvolt = <1352000>; - }; - vreg_s4a_1p8: s4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-allow-set-load; - }; - vreg_s5a_2p04: s5 { - regulator-min-microvolt = <1904000>; - regulator-max-microvolt = <2040000>; - }; - vreg_s7a_1p025: s7 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1028000>; - }; - vreg_l1a_0p875: l1 { - regulator-min-microvolt = <880000>; - regulator-max-microvolt = <880000>; - }; - vreg_l2a_1p2: l2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - vreg_l3a_1p0: l3 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - }; - vreg_l5a_0p8: l5 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <800000>; - }; - vreg_l6a_1p8: l6 { - regulator-min-microvolt = <1808000>; - regulator-max-microvolt = <1808000>; - }; - vreg_l7a_1p8: l7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - vreg_l8a_1p2: l8 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - vreg_l9a_1p8: l9 { - regulator-min-microvolt = <1808000>; - regulator-max-microvolt = <2960000>; - }; - vreg_l10a_1p8: l10 { - regulator-min-microvolt = <1808000>; - regulator-max-microvolt = <2960000>; - }; - vreg_l11a_1p0: l11 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - }; - vreg_l12a_1p8: l12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - vreg_l13a_2p95: l13 { - regulator-min-microvolt = <1808000>; - regulator-max-microvolt = <2960000>; - }; - vreg_l14a_1p88: l14 { - regulator-min-microvolt = <1880000>; - regulator-max-microvolt = <1880000>; - }; - vreg_15a_1p8: l15 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - vreg_l16a_2p7: l16 { - regulator-min-microvolt = <2704000>; - regulator-max-microvolt = <2704000>; - }; - vreg_l17a_1p3: l17 { - regulator-min-microvolt = <1304000>; - regulator-max-microvolt = <1304000>; - }; - vreg_l18a_2p7: l18 { - regulator-min-microvolt = <2704000>; - regulator-max-microvolt = <2704000>; - }; - vreg_l19a_3p0: l19 { - regulator-min-microvolt = <3008000>; - regulator-max-microvolt = <3008000>; - }; - vreg_l20a_2p95: l20 { - regulator-min-microvolt = <2960000>; - regulator-max-microvolt = <2960000>; - regulator-allow-set-load; - }; - vreg_l21a_2p95: l21 { - regulator-min-microvolt = <2960000>; - regulator-max-microvolt = <2960000>; - regulator-allow-set-load; - regulator-system-load = <800000>; - }; - vreg_l22a_2p85: l22 { - regulator-min-microvolt = <2864000>; - regulator-max-microvolt = <2864000>; - }; - vreg_l23a_3p3: l23 { - regulator-min-microvolt = <3312000>; - regulator-max-microvolt = <3312000>; - }; - vreg_l24a_3p075: l24 { - regulator-min-microvolt = <3088000>; - regulator-max-microvolt = <3088000>; - }; - vreg_l25a_3p3: l25 { - regulator-min-microvolt = <3104000>; - regulator-max-microvolt = <3312000>; - }; - vreg_l26a_1p2: l26 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-allow-set-load; - }; - vreg_l28_3p0: l28 { - regulator-min-microvolt = <3008000>; - regulator-max-microvolt = <3008000>; - }; - - vreg_lvs1a_1p8: lvs1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vreg_lvs2a_1p8: lvs2 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - }; - - pmi8998-regulators { - compatible = "qcom,rpm-pmi8998-regulators"; - - vdd_bob-supply = <&vph_pwr>; - - vreg_bob: bob { - regulator-min-microvolt = <3312000>; - regulator-max-microvolt = <3600000>; - }; - }; -}; - -&remoteproc_adsp { - status = "okay"; -}; - -&remoteproc_slpi { - status = "okay"; -}; - -&tlmm { - gpio-reserved-ranges = <0 4>, <81 4>; -}; - -&sdhc2 { - status = "okay"; - cd-gpios = <&tlmm 95 GPIO_ACTIVE_LOW>; - - vmmc-supply = <&vreg_l21a_2p95>; - vqmmc-supply = <&vreg_l13a_2p95>; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; - pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; -}; - -&stm { - status = "okay"; -}; - -&ufshc { - vcc-supply = <&vreg_l20a_2p95>; - vccq-supply = <&vreg_l26a_1p2>; - vccq2-supply = <&vreg_s4a_1p8>; - vcc-max-microamp = <750000>; - vccq-max-microamp = <560000>; - vccq2-max-microamp = <750000>; -}; - -&ufsphy { - vdda-phy-supply = <&vreg_l1a_0p875>; - vdda-pll-supply = <&vreg_l2a_1p2>; - vddp-ref-clk-supply = <&vreg_l26a_1p2>; - vdda-phy-max-microamp = <51400>; - vdda-pll-max-microamp = <14600>; - vddp-ref-clk-max-microamp = <100>; - vddp-ref-clk-always-on; -}; - -&usb3 { - status = "okay"; -}; - -&usb3_dwc3 { - dr_mode = "host"; /* Force to host until we have Type-C hooked up */ -}; - -&usb3phy { - status = "okay"; - - vdda-phy-supply = <&vreg_l1a_0p875>; - vdda-pll-supply = <&vreg_l2a_1p2>; -}; - -&wifi { - status = "okay"; - - vdd-0.8-cx-mx-supply = <&vreg_l5a_0p8>; - vdd-1.8-xo-supply = <&vreg_l7a_1p8>; - vdd-1.3-rfa-supply = <&vreg_l17a_1p3>; - vdd-3.3-ch0-supply = <&vreg_l25a_3p3>; -}; - -/* PINCTRL - board-specific pinctrl */ -&blsp1_uart3_on { - rx { - /delete-property/ bias-disable; - /* - * Configure a pull-up on 45 (RX). This is needed to - * avoid garbage data when the TX pin of the Bluetooth - * module is in tri-state (module powered off or not - * driving the signal yet). - */ - bias-pull-up; - }; - - cts { - /delete-property/ bias-disable; - /* - * Configure a pull-down on 47 (CTS) to match the pull - * of the Bluetooth module. - */ - bias-pull-down; - }; -}; diff --git a/sys/gnu/dts/arm64/qcom/msm8998-pins.dtsi b/sys/gnu/dts/arm64/qcom/msm8998-pins.dtsi deleted file mode 100644 index 7c222cbf19d..00000000000 --- a/sys/gnu/dts/arm64/qcom/msm8998-pins.dtsi +++ /dev/null @@ -1,108 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* Copyright (c) 2018, The Linux Foundation. All rights reserved. */ - -&tlmm { - sdc2_clk_on: sdc2_clk_on { - config { - pins = "sdc2_clk"; - bias-disable; /* NO pull */ - drive-strength = <16>; /* 16 mA */ - }; - }; - - sdc2_clk_off: sdc2_clk_off { - config { - pins = "sdc2_clk"; - bias-disable; /* NO pull */ - drive-strength = <2>; /* 2 mA */ - }; - }; - - sdc2_cmd_on: sdc2_cmd_on { - config { - pins = "sdc2_cmd"; - bias-pull-up; /* pull up */ - drive-strength = <10>; /* 10 mA */ - }; - }; - - sdc2_cmd_off: sdc2_cmd_off { - config { - pins = "sdc2_cmd"; - bias-pull-up; /* pull up */ - drive-strength = <2>; /* 2 mA */ - }; - }; - - sdc2_data_on: sdc2_data_on { - config { - pins = "sdc2_data"; - bias-pull-up; /* pull up */ - drive-strength = <10>; /* 10 mA */ - }; - }; - - sdc2_data_off: sdc2_data_off { - config { - pins = "sdc2_data"; - bias-pull-up; /* pull up */ - drive-strength = <2>; /* 2 mA */ - }; - }; - - sdc2_cd_on: sdc2_cd_on { - mux { - pins = "gpio95"; - function = "gpio"; - }; - - config { - pins = "gpio95"; - bias-pull-up; /* pull up */ - drive-strength = <2>; /* 2 mA */ - }; - }; - - sdc2_cd_off: sdc2_cd_off { - mux { - pins = "gpio95"; - function = "gpio"; - }; - - config { - pins = "gpio95"; - bias-pull-up; /* pull up */ - drive-strength = <2>; /* 2 mA */ - }; - }; - - blsp1_uart3_on: blsp1_uart3_on { - tx { - pins = "gpio45"; - function = "blsp_uart3_a"; - drive-strength = <2>; - bias-disable; - }; - - rx { - pins = "gpio46"; - function = "blsp_uart3_a"; - drive-strength = <2>; - bias-disable; - }; - - cts { - pins = "gpio47"; - function = "blsp_uart3_a"; - drive-strength = <2>; - bias-disable; - }; - - rfr { - pins = "gpio48"; - function = "blsp_uart3_a"; - drive-strength = <2>; - bias-disable; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/qcom/msm8998.dtsi b/sys/gnu/dts/arm64/qcom/msm8998.dtsi deleted file mode 100644 index 91f7f2d0759..00000000000 --- a/sys/gnu/dts/arm64/qcom/msm8998.dtsi +++ /dev/null @@ -1,2114 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* Copyright (c) 2016, The Linux Foundation. All rights reserved. */ - -#include -#include -#include -#include -#include -#include - -/ { - interrupt-parent = <&intc>; - - qcom,msm-id = <292 0x0>; - - #address-cells = <2>; - #size-cells = <2>; - - chosen { }; - - memory { - device_type = "memory"; - /* We expect the bootloader to fill in the reg */ - reg = <0 0 0 0>; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - hyp_mem: memory@85800000 { - reg = <0x0 0x85800000 0x0 0x600000>; - no-map; - }; - - xbl_mem: memory@85e00000 { - reg = <0x0 0x85e00000 0x0 0x100000>; - no-map; - }; - - smem_mem: smem-mem@86000000 { - reg = <0x0 0x86000000 0x0 0x200000>; - no-map; - }; - - tz_mem: memory@86200000 { - reg = <0x0 0x86200000 0x0 0x2d00000>; - no-map; - }; - - rmtfs_mem: memory@88f00000 { - compatible = "qcom,rmtfs-mem"; - reg = <0x0 0x88f00000 0x0 0x200000>; - no-map; - - qcom,client-id = <1>; - qcom,vmid = <15>; - }; - - spss_mem: memory@8ab00000 { - reg = <0x0 0x8ab00000 0x0 0x700000>; - no-map; - }; - - adsp_mem: memory@8b200000 { - reg = <0x0 0x8b200000 0x0 0x1a00000>; - no-map; - }; - - mpss_mem: memory@8cc00000 { - reg = <0x0 0x8cc00000 0x0 0x7000000>; - no-map; - }; - - venus_mem: memory@93c00000 { - reg = <0x0 0x93c00000 0x0 0x500000>; - no-map; - }; - - mba_mem: memory@94100000 { - reg = <0x0 0x94100000 0x0 0x200000>; - no-map; - }; - - slpi_mem: memory@94300000 { - reg = <0x0 0x94300000 0x0 0xf00000>; - no-map; - }; - - ipa_fw_mem: memory@95200000 { - reg = <0x0 0x95200000 0x0 0x10000>; - no-map; - }; - - ipa_gsi_mem: memory@95210000 { - reg = <0x0 0x95210000 0x0 0x5000>; - no-map; - }; - - gpu_mem: memory@95600000 { - reg = <0x0 0x95600000 0x0 0x100000>; - no-map; - }; - - wlan_msa_mem: memory@95700000 { - reg = <0x0 0x95700000 0x0 0x100000>; - no-map; - }; - }; - - clocks { - xo: xo-board { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <19200000>; - clock-output-names = "xo_board"; - }; - - sleep_clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32764>; - }; - }; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - CPU0: cpu@0 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x0>; - enable-method = "psci"; - cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; - next-level-cache = <&L2_0>; - L2_0: l2-cache { - compatible = "arm,arch-cache"; - cache-level = <2>; - }; - L1_I_0: l1-icache { - compatible = "arm,arch-cache"; - }; - L1_D_0: l1-dcache { - compatible = "arm,arch-cache"; - }; - }; - - CPU1: cpu@1 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x1>; - enable-method = "psci"; - cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; - next-level-cache = <&L2_0>; - L1_I_1: l1-icache { - compatible = "arm,arch-cache"; - }; - L1_D_1: l1-dcache { - compatible = "arm,arch-cache"; - }; - }; - - CPU2: cpu@2 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x2>; - enable-method = "psci"; - cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; - next-level-cache = <&L2_0>; - L1_I_2: l1-icache { - compatible = "arm,arch-cache"; - }; - L1_D_2: l1-dcache { - compatible = "arm,arch-cache"; - }; - }; - - CPU3: cpu@3 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x3>; - enable-method = "psci"; - cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; - next-level-cache = <&L2_0>; - L1_I_3: l1-icache { - compatible = "arm,arch-cache"; - }; - L1_D_3: l1-dcache { - compatible = "arm,arch-cache"; - }; - }; - - CPU4: cpu@100 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x100>; - enable-method = "psci"; - cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; - next-level-cache = <&L2_1>; - L2_1: l2-cache { - compatible = "arm,arch-cache"; - cache-level = <2>; - }; - L1_I_100: l1-icache { - compatible = "arm,arch-cache"; - }; - L1_D_100: l1-dcache { - compatible = "arm,arch-cache"; - }; - }; - - CPU5: cpu@101 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x101>; - enable-method = "psci"; - cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; - next-level-cache = <&L2_1>; - L1_I_101: l1-icache { - compatible = "arm,arch-cache"; - }; - L1_D_101: l1-dcache { - compatible = "arm,arch-cache"; - }; - }; - - CPU6: cpu@102 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x102>; - enable-method = "psci"; - cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; - next-level-cache = <&L2_1>; - L1_I_102: l1-icache { - compatible = "arm,arch-cache"; - }; - L1_D_102: l1-dcache { - compatible = "arm,arch-cache"; - }; - }; - - CPU7: cpu@103 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x103>; - enable-method = "psci"; - cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; - next-level-cache = <&L2_1>; - L1_I_103: l1-icache { - compatible = "arm,arch-cache"; - }; - L1_D_103: l1-dcache { - compatible = "arm,arch-cache"; - }; - }; - - cpu-map { - cluster0 { - core0 { - cpu = <&CPU0>; - }; - - core1 { - cpu = <&CPU1>; - }; - - core2 { - cpu = <&CPU2>; - }; - - core3 { - cpu = <&CPU3>; - }; - }; - - cluster1 { - core0 { - cpu = <&CPU4>; - }; - - core1 { - cpu = <&CPU5>; - }; - - core2 { - cpu = <&CPU6>; - }; - - core3 { - cpu = <&CPU7>; - }; - }; - }; - - idle-states { - entry-method = "psci"; - - LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { - compatible = "arm,idle-state"; - idle-state-name = "little-retention"; - arm,psci-suspend-param = <0x00000002>; - entry-latency-us = <81>; - exit-latency-us = <86>; - min-residency-us = <200>; - }; - - LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { - compatible = "arm,idle-state"; - idle-state-name = "little-power-collapse"; - arm,psci-suspend-param = <0x40000003>; - entry-latency-us = <273>; - exit-latency-us = <612>; - min-residency-us = <1000>; - local-timer-stop; - }; - - BIG_CPU_SLEEP_0: cpu-sleep-1-0 { - compatible = "arm,idle-state"; - idle-state-name = "big-retention"; - arm,psci-suspend-param = <0x00000002>; - entry-latency-us = <79>; - exit-latency-us = <82>; - min-residency-us = <200>; - }; - - BIG_CPU_SLEEP_1: cpu-sleep-1-1 { - compatible = "arm,idle-state"; - idle-state-name = "big-power-collapse"; - arm,psci-suspend-param = <0x40000003>; - entry-latency-us = <336>; - exit-latency-us = <525>; - min-residency-us = <1000>; - local-timer-stop; - }; - }; - }; - - firmware { - scm { - compatible = "qcom,scm-msm8998", "qcom,scm"; - }; - }; - - tcsr_mutex: hwlock { - compatible = "qcom,tcsr-mutex"; - syscon = <&tcsr_mutex_regs 0 0x1000>; - #hwlock-cells = <1>; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - rpm-glink { - compatible = "qcom,glink-rpm"; - - interrupts = ; - qcom,rpm-msg-ram = <&rpm_msg_ram>; - mboxes = <&apcs_glb 0>; - - rpm_requests: rpm-requests { - compatible = "qcom,rpm-msm8998"; - qcom,glink-channels = "rpm_requests"; - - rpmcc: clock-controller { - compatible = "qcom,rpmcc-msm8998", "qcom,rpmcc"; - #clock-cells = <1>; - }; - - rpmpd: power-controller { - compatible = "qcom,msm8998-rpmpd"; - #power-domain-cells = <1>; - operating-points-v2 = <&rpmpd_opp_table>; - - rpmpd_opp_table: opp-table { - compatible = "operating-points-v2"; - - rpmpd_opp_ret: opp1 { - opp-level = <16>; - }; - - rpmpd_opp_ret_plus: opp2 { - opp-level = <32>; - }; - - rpmpd_opp_min_svs: opp3 { - opp-level = <48>; - }; - - rpmpd_opp_low_svs: opp4 { - opp-level = <64>; - }; - - rpmpd_opp_svs: opp5 { - opp-level = <128>; - }; - - rpmpd_opp_svs_plus: opp6 { - opp-level = <192>; - }; - - rpmpd_opp_nom: opp7 { - opp-level = <256>; - }; - - rpmpd_opp_nom_plus: opp8 { - opp-level = <320>; - }; - - rpmpd_opp_turbo: opp9 { - opp-level = <384>; - }; - - rpmpd_opp_turbo_plus: opp10 { - opp-level = <512>; - }; - }; - }; - }; - }; - - smem { - compatible = "qcom,smem"; - memory-region = <&smem_mem>; - hwlocks = <&tcsr_mutex 3>; - }; - - smp2p-lpass { - compatible = "qcom,smp2p"; - qcom,smem = <443>, <429>; - - interrupts = ; - - mboxes = <&apcs_glb 10>; - - qcom,local-pid = <0>; - qcom,remote-pid = <2>; - - adsp_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - adsp_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - smp2p-mpss { - compatible = "qcom,smp2p"; - qcom,smem = <435>, <428>; - interrupts = ; - mboxes = <&apcs_glb 14>; - qcom,local-pid = <0>; - qcom,remote-pid = <1>; - - modem_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - modem_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - smp2p-slpi { - compatible = "qcom,smp2p"; - qcom,smem = <481>, <430>; - interrupts = ; - mboxes = <&apcs_glb 26>; - qcom,local-pid = <0>; - qcom,remote-pid = <3>; - - slpi_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - slpi_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - thermal-zones { - cpu0-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 1>; - - trips { - cpu0_alert0: trip-point@0 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu0_crit: cpu_crit { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - cpu1-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 2>; - - trips { - cpu1_alert0: trip-point@0 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu1_crit: cpu_crit { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - cpu2-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 3>; - - trips { - cpu2_alert0: trip-point@0 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu2_crit: cpu_crit { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - cpu3-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 4>; - - trips { - cpu3_alert0: trip-point@0 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu3_crit: cpu_crit { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - cpu4-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 7>; - - trips { - cpu4_alert0: trip-point@0 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu4_crit: cpu_crit { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - cpu5-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 8>; - - trips { - cpu5_alert0: trip-point@0 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu5_crit: cpu_crit { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - cpu6-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 9>; - - trips { - cpu6_alert0: trip-point@0 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu6_crit: cpu_crit { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - cpu7-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 10>; - - trips { - cpu7_alert0: trip-point@0 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu7_crit: cpu_crit { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - gpu-thermal-bottom { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 12>; - - trips { - gpu1_alert0: trip-point@0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - gpu-thermal-top { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 13>; - - trips { - gpu2_alert0: trip-point@0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - clust0-mhm-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 5>; - - trips { - cluster0_mhm_alert0: trip-point@0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - clust1-mhm-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 6>; - - trips { - cluster1_mhm_alert0: trip-point@0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - cluster1-l2-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 11>; - - trips { - cluster1_l2_alert0: trip-point@0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - modem-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 1>; - - trips { - modem_alert0: trip-point@0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - mem-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 2>; - - trips { - mem_alert0: trip-point@0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - wlan-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 3>; - - trips { - wlan_alert0: trip-point@0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - q6-dsp-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 4>; - - trips { - q6_dsp_alert0: trip-point@0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - camera-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 5>; - - trips { - camera_alert0: trip-point@0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - multimedia-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 6>; - - trips { - multimedia_alert0: trip-point@0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - soc: soc { - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0 0xffffffff>; - compatible = "simple-bus"; - - gcc: clock-controller@100000 { - compatible = "qcom,gcc-msm8998"; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - reg = <0x00100000 0xb0000>; - }; - - rpm_msg_ram: memory@778000 { - compatible = "qcom,rpm-msg-ram"; - reg = <0x00778000 0x7000>; - }; - - qfprom: qfprom@780000 { - compatible = "qcom,qfprom"; - reg = <0x00780000 0x621c>; - #address-cells = <1>; - #size-cells = <1>; - - qusb2_hstx_trim: hstx-trim@423a { - reg = <0x423a 0x1>; - bits = <0 4>; - }; - }; - - tsens0: thermal@10ab000 { - compatible = "qcom,msm8998-tsens", "qcom,tsens-v2"; - reg = <0x010ab000 0x1000>, /* TM */ - <0x010aa000 0x1000>; /* SROT */ - #qcom,sensors = <14>; - interrupts = , - ; - interrupt-names = "uplow", "critical"; - #thermal-sensor-cells = <1>; - }; - - tsens1: thermal@10ae000 { - compatible = "qcom,msm8998-tsens", "qcom,tsens-v2"; - reg = <0x010ae000 0x1000>, /* TM */ - <0x010ad000 0x1000>; /* SROT */ - #qcom,sensors = <8>; - interrupts = , - ; - interrupt-names = "uplow", "critical"; - #thermal-sensor-cells = <1>; - }; - - anoc1_smmu: iommu@1680000 { - compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2"; - reg = <0x01680000 0x10000>; - #iommu-cells = <1>; - - #global-interrupts = <0>; - interrupts = - , - , - , - , - , - ; - }; - - anoc2_smmu: iommu@16c0000 { - compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2"; - reg = <0x016c0000 0x40000>; - #iommu-cells = <1>; - - #global-interrupts = <0>; - interrupts = - , - , - , - , - , - , - , - , - , - ; - }; - - pcie0: pci@1c00000 { - compatible = "qcom,pcie-msm8996"; - reg = <0x01c00000 0x2000>, - <0x1b000000 0xf1d>, - <0x1b000f20 0xa8>, - <0x1b100000 0x100000>; - reg-names = "parf", "dbi", "elbi", "config"; - device_type = "pci"; - linux,pci-domain = <0>; - bus-range = <0x00 0xff>; - #address-cells = <3>; - #size-cells = <2>; - num-lanes = <1>; - phys = <&pciephy>; - phy-names = "pciephy"; - - ranges = <0x01000000 0x0 0x1b200000 0x1b200000 0x0 0x100000>, - <0x02000000 0x0 0x1b300000 0x1b300000 0x0 0xd00000>; - - #interrupt-cells = <1>; - interrupts = ; - interrupt-names = "msi"; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 135 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &intc 0 136 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &intc 0 138 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &intc 0 139 IRQ_TYPE_LEVEL_HIGH>; - - clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, - <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, - <&gcc GCC_PCIE_0_SLV_AXI_CLK>, - <&gcc GCC_PCIE_0_CFG_AHB_CLK>, - <&gcc GCC_PCIE_0_AUX_CLK>; - clock-names = "pipe", "bus_master", "bus_slave", "cfg", "aux"; - - power-domains = <&gcc PCIE_0_GDSC>; - iommu-map = <0x100 &anoc1_smmu 0x1480 1>; - perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; - }; - - phy@1c06000 { - compatible = "qcom,msm8998-qmp-pcie-phy"; - reg = <0x01c06000 0x18c>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, - <&gcc GCC_PCIE_0_CFG_AHB_CLK>, - <&gcc GCC_PCIE_CLKREF_CLK>; - clock-names = "aux", "cfg_ahb", "ref"; - - resets = <&gcc GCC_PCIE_0_PHY_BCR>, <&gcc GCC_PCIE_PHY_BCR>; - reset-names = "phy", "common"; - - vdda-phy-supply = <&vreg_l1a_0p875>; - vdda-pll-supply = <&vreg_l2a_1p2>; - - pciephy: lane@1c06800 { - reg = <0x01c06200 0x128>, <0x01c06400 0x1fc>, <0x01c06800 0x20c>; - #phy-cells = <0>; - - clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; - clock-names = "pipe0"; - clock-output-names = "pcie_0_pipe_clk_src"; - #clock-cells = <0>; - }; - }; - - ufshc: ufshc@1da4000 { - compatible = "qcom,msm8998-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; - reg = <0x01da4000 0x2500>; - interrupts = ; - phys = <&ufsphy_lanes>; - phy-names = "ufsphy"; - lanes-per-direction = <2>; - power-domains = <&gcc UFS_GDSC>; - #reset-cells = <1>; - - clock-names = - "core_clk", - "bus_aggr_clk", - "iface_clk", - "core_clk_unipro", - "ref_clk", - "tx_lane0_sync_clk", - "rx_lane0_sync_clk", - "rx_lane1_sync_clk"; - clocks = - <&gcc GCC_UFS_AXI_CLK>, - <&gcc GCC_AGGRE1_UFS_AXI_CLK>, - <&gcc GCC_UFS_AHB_CLK>, - <&gcc GCC_UFS_UNIPRO_CORE_CLK>, - <&rpmcc RPM_SMD_LN_BB_CLK1>, - <&gcc GCC_UFS_TX_SYMBOL_0_CLK>, - <&gcc GCC_UFS_RX_SYMBOL_0_CLK>, - <&gcc GCC_UFS_RX_SYMBOL_1_CLK>; - freq-table-hz = - <50000000 200000000>, - <0 0>, - <0 0>, - <37500000 150000000>, - <0 0>, - <0 0>, - <0 0>, - <0 0>; - - resets = <&gcc GCC_UFS_BCR>; - reset-names = "rst"; - }; - - ufsphy: phy@1da7000 { - compatible = "qcom,msm8998-qmp-ufs-phy"; - reg = <0x01da7000 0x18c>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - clock-names = - "ref", - "ref_aux"; - clocks = - <&gcc GCC_UFS_CLKREF_CLK>, - <&gcc GCC_UFS_PHY_AUX_CLK>; - - reset-names = "ufsphy"; - resets = <&ufshc 0>; - - ufsphy_lanes: lanes@1da7400 { - reg = <0x01da7400 0x128>, - <0x01da7600 0x1fc>, - <0x01da7c00 0x1dc>, - <0x01da7800 0x128>, - <0x01da7a00 0x1fc>; - #phy-cells = <0>; - }; - }; - - tcsr_mutex_regs: syscon@1f40000 { - compatible = "syscon"; - reg = <0x01f40000 0x40000>; - }; - - tlmm: pinctrl@3400000 { - compatible = "qcom,msm8998-pinctrl"; - reg = <0x03400000 0xc00000>; - interrupts = ; - gpio-controller; - #gpio-cells = <0x2>; - interrupt-controller; - #interrupt-cells = <0x2>; - }; - - remoteproc_mss: remoteproc@4080000 { - compatible = "qcom,msm8998-mss-pil"; - reg = <0x04080000 0x100>, <0x04180000 0x20>; - reg-names = "qdsp6", "rmb"; - - interrupts-extended = - <&intc GIC_SPI 448 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", - "handover", "stop-ack", - "shutdown-ack"; - - clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, - <&gcc GCC_BIMC_MSS_Q6_AXI_CLK>, - <&gcc GCC_BOOT_ROM_AHB_CLK>, - <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>, - <&gcc GCC_MSS_SNOC_AXI_CLK>, - <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>, - <&rpmcc RPM_SMD_QDSS_CLK>, - <&rpmcc RPM_SMD_XO_CLK_SRC>; - clock-names = "iface", "bus", "mem", "gpll0_mss", - "snoc_axi", "mnoc_axi", "qdss", "xo"; - - qcom,smem-states = <&modem_smp2p_out 0>; - qcom,smem-state-names = "stop"; - - resets = <&gcc GCC_MSS_RESTART>; - reset-names = "mss_restart"; - - qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>; - - power-domains = <&rpmpd MSM8998_VDDCX>, - <&rpmpd MSM8998_VDDMX>; - power-domain-names = "cx", "mx"; - - mba { - memory-region = <&mba_mem>; - }; - - mpss { - memory-region = <&mpss_mem>; - }; - - glink-edge { - interrupts = ; - label = "modem"; - qcom,remote-pid = <1>; - mboxes = <&apcs_glb 15>; - }; - }; - - gpucc: clock-controller@5065000 { - compatible = "qcom,msm8998-gpucc"; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - reg = <0x05065000 0x9000>; - - clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, - <&gcc GPLL0_OUT_MAIN>; - clock-names = "xo", - "gpll0"; - }; - - remoteproc_slpi: remoteproc@5800000 { - compatible = "qcom,msm8998-slpi-pas"; - reg = <0x05800000 0x4040>; - - interrupts-extended = <&intc GIC_SPI 390 IRQ_TYPE_EDGE_RISING>, - <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, - <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, - <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", - "handover", "stop-ack"; - - px-supply = <&vreg_lvs2a_1p8>; - - clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, - <&rpmcc RPM_SMD_AGGR2_NOC_CLK>; - clock-names = "xo", "aggre2"; - - memory-region = <&slpi_mem>; - - qcom,smem-states = <&slpi_smp2p_out 0>; - qcom,smem-state-names = "stop"; - - power-domains = <&rpmpd MSM8998_SSCCX>; - power-domain-names = "ssc_cx"; - - status = "disabled"; - - glink-edge { - interrupts = ; - label = "dsps"; - qcom,remote-pid = <3>; - mboxes = <&apcs_glb 27>; - }; - }; - - stm: stm@6002000 { - compatible = "arm,coresight-stm", "arm,primecell"; - reg = <0x06002000 0x1000>, - <0x16280000 0x180000>; - reg-names = "stm-base", "stm-data-base"; - status = "disabled"; - - clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - out-ports { - port { - stm_out: endpoint { - remote-endpoint = <&funnel0_in7>; - }; - }; - }; - }; - - funnel1: funnel@6041000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0x06041000 0x1000>; - status = "disabled"; - - clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - out-ports { - port { - funnel0_out: endpoint { - remote-endpoint = - <&merge_funnel_in0>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@7 { - reg = <7>; - funnel0_in7: endpoint { - remote-endpoint = <&stm_out>; - }; - }; - }; - }; - - funnel2: funnel@6042000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0x06042000 0x1000>; - status = "disabled"; - - clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - out-ports { - port { - funnel1_out: endpoint { - remote-endpoint = - <&merge_funnel_in1>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@6 { - reg = <6>; - funnel1_in6: endpoint { - remote-endpoint = - <&apss_merge_funnel_out>; - }; - }; - }; - }; - - funnel3: funnel@6045000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0x06045000 0x1000>; - status = "disabled"; - - clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - out-ports { - port { - merge_funnel_out: endpoint { - remote-endpoint = - <&etf_in>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - merge_funnel_in0: endpoint { - remote-endpoint = - <&funnel0_out>; - }; - }; - - port@1 { - reg = <1>; - merge_funnel_in1: endpoint { - remote-endpoint = - <&funnel1_out>; - }; - }; - }; - }; - - replicator1: replicator@6046000 { - compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; - reg = <0x06046000 0x1000>; - status = "disabled"; - - clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - out-ports { - port { - replicator_out: endpoint { - remote-endpoint = <&etr_in>; - }; - }; - }; - - in-ports { - port { - replicator_in: endpoint { - remote-endpoint = <&etf_out>; - }; - }; - }; - }; - - etf: etf@6047000 { - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0x06047000 0x1000>; - status = "disabled"; - - clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - out-ports { - port { - etf_out: endpoint { - remote-endpoint = - <&replicator_in>; - }; - }; - }; - - in-ports { - port { - etf_in: endpoint { - remote-endpoint = - <&merge_funnel_out>; - }; - }; - }; - }; - - etr: etr@6048000 { - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0x06048000 0x1000>; - status = "disabled"; - - clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - arm,scatter-gather; - - in-ports { - port { - etr_in: endpoint { - remote-endpoint = - <&replicator_out>; - }; - }; - }; - }; - - etm1: etm@7840000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0x07840000 0x1000>; - status = "disabled"; - - clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - cpu = <&CPU0>; - - out-ports { - port { - etm0_out: endpoint { - remote-endpoint = - <&apss_funnel_in0>; - }; - }; - }; - }; - - etm2: etm@7940000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0x07940000 0x1000>; - status = "disabled"; - - clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - cpu = <&CPU1>; - - out-ports { - port { - etm1_out: endpoint { - remote-endpoint = - <&apss_funnel_in1>; - }; - }; - }; - }; - - etm3: etm@7a40000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0x07a40000 0x1000>; - status = "disabled"; - - clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - cpu = <&CPU2>; - - out-ports { - port { - etm2_out: endpoint { - remote-endpoint = - <&apss_funnel_in2>; - }; - }; - }; - }; - - etm4: etm@7b40000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0x07b40000 0x1000>; - status = "disabled"; - - clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - cpu = <&CPU3>; - - out-ports { - port { - etm3_out: endpoint { - remote-endpoint = - <&apss_funnel_in3>; - }; - }; - }; - }; - - funnel4: funnel@7b60000 { /* APSS Funnel */ - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0x07b60000 0x1000>; - status = "disabled"; - - clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - out-ports { - port { - apss_funnel_out: endpoint { - remote-endpoint = - <&apss_merge_funnel_in>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - apss_funnel_in0: endpoint { - remote-endpoint = - <&etm0_out>; - }; - }; - - port@1 { - reg = <1>; - apss_funnel_in1: endpoint { - remote-endpoint = - <&etm1_out>; - }; - }; - - port@2 { - reg = <2>; - apss_funnel_in2: endpoint { - remote-endpoint = - <&etm2_out>; - }; - }; - - port@3 { - reg = <3>; - apss_funnel_in3: endpoint { - remote-endpoint = - <&etm3_out>; - }; - }; - - port@4 { - reg = <4>; - apss_funnel_in4: endpoint { - remote-endpoint = - <&etm4_out>; - }; - }; - - port@5 { - reg = <5>; - apss_funnel_in5: endpoint { - remote-endpoint = - <&etm5_out>; - }; - }; - - port@6 { - reg = <6>; - apss_funnel_in6: endpoint { - remote-endpoint = - <&etm6_out>; - }; - }; - - port@7 { - reg = <7>; - apss_funnel_in7: endpoint { - remote-endpoint = - <&etm7_out>; - }; - }; - }; - }; - - funnel5: funnel@7b70000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0x07b70000 0x1000>; - status = "disabled"; - - clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - out-ports { - port { - apss_merge_funnel_out: endpoint { - remote-endpoint = - <&funnel1_in6>; - }; - }; - }; - - in-ports { - port { - apss_merge_funnel_in: endpoint { - remote-endpoint = - <&apss_funnel_out>; - }; - }; - }; - }; - - etm5: etm@7c40000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0x07c40000 0x1000>; - status = "disabled"; - - clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - cpu = <&CPU4>; - - port{ - etm4_out: endpoint { - remote-endpoint = <&apss_funnel_in4>; - }; - }; - }; - - etm6: etm@7d40000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0x07d40000 0x1000>; - status = "disabled"; - - clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - cpu = <&CPU5>; - - port{ - etm5_out: endpoint { - remote-endpoint = <&apss_funnel_in5>; - }; - }; - }; - - etm7: etm@7e40000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0x07e40000 0x1000>; - status = "disabled"; - - clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - cpu = <&CPU6>; - - port{ - etm6_out: endpoint { - remote-endpoint = <&apss_funnel_in6>; - }; - }; - }; - - etm8: etm@7f40000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0x07f40000 0x1000>; - status = "disabled"; - - clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - cpu = <&CPU7>; - - port{ - etm7_out: endpoint { - remote-endpoint = <&apss_funnel_in7>; - }; - }; - }; - - spmi_bus: spmi@800f000 { - compatible = "qcom,spmi-pmic-arb"; - reg = <0x0800f000 0x1000>, - <0x08400000 0x1000000>, - <0x09400000 0x1000000>, - <0x0a400000 0x220000>, - <0x0800a000 0x3000>; - reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; - interrupt-names = "periph_irq"; - interrupts = ; - qcom,ee = <0>; - qcom,channel = <0>; - #address-cells = <2>; - #size-cells = <0>; - interrupt-controller; - #interrupt-cells = <4>; - cell-index = <0>; - }; - - usb3: usb@a8f8800 { - compatible = "qcom,msm8998-dwc3", "qcom,dwc3"; - reg = <0x0a8f8800 0x400>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - clocks = <&gcc GCC_CFG_NOC_USB3_AXI_CLK>, - <&gcc GCC_USB30_MASTER_CLK>, - <&gcc GCC_AGGRE1_USB3_AXI_CLK>, - <&gcc GCC_USB30_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_SLEEP_CLK>; - clock-names = "cfg_noc", "core", "iface", "mock_utmi", - "sleep"; - - assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_MASTER_CLK>; - assigned-clock-rates = <19200000>, <120000000>; - - interrupts = , - ; - interrupt-names = "hs_phy_irq", "ss_phy_irq"; - - power-domains = <&gcc USB_30_GDSC>; - - resets = <&gcc GCC_USB_30_BCR>; - - usb3_dwc3: dwc3@a800000 { - compatible = "snps,dwc3"; - reg = <0x0a800000 0xcd00>; - interrupts = ; - snps,dis_u2_susphy_quirk; - snps,dis_enblslpm_quirk; - phys = <&qusb2phy>, <&usb1_ssphy>; - phy-names = "usb2-phy", "usb3-phy"; - snps,has-lpm-erratum; - snps,hird-threshold = /bits/ 8 <0x10>; - }; - }; - - usb3phy: phy@c010000 { - compatible = "qcom,msm8998-qmp-usb3-phy"; - reg = <0x0c010000 0x18c>; - status = "disabled"; - #clock-cells = <1>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - clocks = <&gcc GCC_USB3_PHY_AUX_CLK>, - <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, - <&gcc GCC_USB3_CLKREF_CLK>; - clock-names = "aux", "cfg_ahb", "ref"; - - resets = <&gcc GCC_USB3_PHY_BCR>, - <&gcc GCC_USB3PHY_PHY_BCR>; - reset-names = "phy", "common"; - - usb1_ssphy: lane@c010200 { - reg = <0xc010200 0x128>, - <0xc010400 0x200>, - <0xc010c00 0x20c>, - <0xc010600 0x128>, - <0xc010800 0x200>; - #phy-cells = <0>; - clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>; - clock-names = "pipe0"; - clock-output-names = "usb3_phy_pipe_clk_src"; - }; - }; - - qusb2phy: phy@c012000 { - compatible = "qcom,msm8998-qusb2-phy"; - reg = <0x0c012000 0x2a8>; - status = "disabled"; - #phy-cells = <0>; - - clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, - <&gcc GCC_RX1_USB2_CLKREF_CLK>; - clock-names = "cfg_ahb", "ref"; - - resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; - - nvmem-cells = <&qusb2_hstx_trim>; - }; - - sdhc2: sdhci@c0a4900 { - compatible = "qcom,sdhci-msm-v4"; - reg = <0x0c0a4900 0x314>, <0x0c0a4000 0x800>; - reg-names = "hc_mem", "core_mem"; - - interrupts = , - ; - interrupt-names = "hc_irq", "pwr_irq"; - - clock-names = "iface", "core", "xo"; - clocks = <&gcc GCC_SDCC2_AHB_CLK>, - <&gcc GCC_SDCC2_APPS_CLK>, - <&xo>; - bus-width = <4>; - status = "disabled"; - }; - - blsp1_dma: dma@c144000 { - compatible = "qcom,bam-v1.7.0"; - reg = <0x0c144000 0x25000>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "bam_clk"; - #dma-cells = <1>; - qcom,ee = <0>; - qcom,controlled-remotely; - num-channels = <18>; - qcom,num-ees = <4>; - }; - - blsp1_uart3: serial@c171000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0x0c171000 0x1000>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - dmas = <&blsp1_dma 4>, <&blsp1_dma 5>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&blsp1_uart3_on>; - status = "disabled"; - }; - - blsp1_i2c1: i2c@c175000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x0c175000 0x600>; - interrupts = ; - - clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - clock-frequency = <400000>; - - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - blsp1_i2c2: i2c@c176000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x0c176000 0x600>; - interrupts = ; - - clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - clock-frequency = <400000>; - - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - blsp1_i2c3: i2c@c177000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x0c177000 0x600>; - interrupts = ; - - clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - clock-frequency = <400000>; - - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - blsp1_i2c4: i2c@c178000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x0c178000 0x600>; - interrupts = ; - - clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - clock-frequency = <400000>; - - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - blsp1_i2c5: i2c@c179000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x0c179000 0x600>; - interrupts = ; - - clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - clock-frequency = <400000>; - - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - blsp1_i2c6: i2c@c17a000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x0c17a000 0x600>; - interrupts = ; - - clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - clock-frequency = <400000>; - - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - blsp2_uart1: serial@c1b0000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0x0c1b0000 0x1000>; - interrupts = ; - clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, - <&gcc GCC_BLSP2_AHB_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - - blsp2_i2c0: i2c@c1b5000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x0c1b5000 0x600>; - interrupts = ; - - clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, - <&gcc GCC_BLSP2_AHB_CLK>; - clock-names = "core", "iface"; - clock-frequency = <400000>; - - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - blsp2_i2c1: i2c@c1b6000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x0c1b6000 0x600>; - interrupts = ; - - clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, - <&gcc GCC_BLSP2_AHB_CLK>; - clock-names = "core", "iface"; - clock-frequency = <400000>; - - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - blsp2_i2c2: i2c@c1b7000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x0c1b7000 0x600>; - interrupts = ; - - clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>, - <&gcc GCC_BLSP2_AHB_CLK>; - clock-names = "core", "iface"; - clock-frequency = <400000>; - - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - blsp2_i2c3: i2c@c1b8000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x0c1b8000 0x600>; - interrupts = ; - - clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>, - <&gcc GCC_BLSP2_AHB_CLK>; - clock-names = "core", "iface"; - clock-frequency = <400000>; - - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - blsp2_i2c4: i2c@c1b9000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x0c1b9000 0x600>; - interrupts = ; - - clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, - <&gcc GCC_BLSP2_AHB_CLK>; - clock-names = "core", "iface"; - clock-frequency = <400000>; - - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - blsp2_i2c5: i2c@c1ba000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x0c1ba000 0x600>; - interrupts = ; - - clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, - <&gcc GCC_BLSP2_AHB_CLK>; - clock-names = "core", "iface"; - clock-frequency = <400000>; - - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - remoteproc_adsp: remoteproc@17300000 { - compatible = "qcom,msm8998-adsp-pas"; - reg = <0x17300000 0x4040>; - - interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", - "handover", "stop-ack"; - - clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; - clock-names = "xo"; - - memory-region = <&adsp_mem>; - - qcom,smem-states = <&adsp_smp2p_out 0>; - qcom,smem-state-names = "stop"; - - power-domains = <&rpmpd MSM8998_VDDCX>; - power-domain-names = "cx"; - - status = "disabled"; - - glink-edge { - interrupts = ; - label = "lpass"; - qcom,remote-pid = <2>; - mboxes = <&apcs_glb 9>; - }; - }; - - apcs_glb: mailbox@17911000 { - compatible = "qcom,msm8998-apcs-hmss-global"; - reg = <0x17911000 0x1000>; - - #mbox-cells = <1>; - }; - - timer@17920000 { - #address-cells = <1>; - #size-cells = <1>; - ranges; - compatible = "arm,armv7-timer-mem"; - reg = <0x17920000 0x1000>; - - frame@17921000 { - frame-number = <0>; - interrupts = , - ; - reg = <0x17921000 0x1000>, - <0x17922000 0x1000>; - }; - - frame@17923000 { - frame-number = <1>; - interrupts = ; - reg = <0x17923000 0x1000>; - status = "disabled"; - }; - - frame@17924000 { - frame-number = <2>; - interrupts = ; - reg = <0x17924000 0x1000>; - status = "disabled"; - }; - - frame@17925000 { - frame-number = <3>; - interrupts = ; - reg = <0x17925000 0x1000>; - status = "disabled"; - }; - - frame@17926000 { - frame-number = <4>; - interrupts = ; - reg = <0x17926000 0x1000>; - status = "disabled"; - }; - - frame@17927000 { - frame-number = <5>; - interrupts = ; - reg = <0x17927000 0x1000>; - status = "disabled"; - }; - - frame@17928000 { - frame-number = <6>; - interrupts = ; - reg = <0x17928000 0x1000>; - status = "disabled"; - }; - }; - - intc: interrupt-controller@17a00000 { - compatible = "arm,gic-v3"; - reg = <0x17a00000 0x10000>, /* GICD */ - <0x17b00000 0x100000>; /* GICR * 8 */ - #interrupt-cells = <3>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - interrupt-controller; - #redistributor-regions = <1>; - redistributor-stride = <0x0 0x20000>; - interrupts = ; - }; - - wifi: wifi@18800000 { - compatible = "qcom,wcn3990-wifi"; - status = "disabled"; - reg = <0x18800000 0x800000>; - reg-names = "membase"; - memory-region = <&wlan_msa_mem>; - clocks = <&rpmcc RPM_SMD_RF_CLK2_PIN>; - clock-names = "cxo_ref_clk_pin"; - interrupts = - , - , - , - , - , - , - , - , - , - , - , - ; - iommus = <&anoc2_smmu 0x1900>, - <&anoc2_smmu 0x1901>; - qcom,snoc-host-cap-8bit-quirk; - }; - }; -}; - -#include "msm8998-pins.dtsi" diff --git a/sys/gnu/dts/arm64/qcom/pm6150.dtsi b/sys/gnu/dts/arm64/qcom/pm6150.dtsi deleted file mode 100644 index 23534639f45..00000000000 --- a/sys/gnu/dts/arm64/qcom/pm6150.dtsi +++ /dev/null @@ -1,72 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -// Copyright (c) 2019, The Linux Foundation. All rights reserved. - -#include -#include -#include -#include -#include - -&spmi_bus { - pm6150_lsid0: pmic@0 { - compatible = "qcom,pm6150", "qcom,spmi-pmic"; - reg = <0x0 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - - pm6150_pon: pon@800 { - compatible = "qcom,pm8998-pon"; - reg = <0x800>; - mode-bootloader = <0x2>; - mode-recovery = <0x1>; - - pwrkey { - compatible = "qcom,pm8941-pwrkey"; - interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>; - debounce = <15625>; - bias-pull-up; - linux,code = ; - }; - }; - - pm6150_temp: temp-alarm@2400 { - compatible = "qcom,spmi-temp-alarm"; - reg = <0x2400>; - interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_RISING>; - io-channels = <&pm6150_adc ADC5_DIE_TEMP>; - io-channel-names = "thermal"; - #thermal-sensor-cells = <0>; - }; - - pm6150_adc: adc@3100 { - compatible = "qcom,spmi-adc5"; - reg = <0x3100>; - interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; - #address-cells = <1>; - #size-cells = <0>; - #io-channel-cells = <1>; - - adc-chan@6 { - reg = ; - label = "die_temp"; - }; - }; - - pm6150_gpio: gpios@c000 { - compatible = "qcom,pm6150-gpio", "qcom,spmi-gpio"; - reg = <0xc000>; - gpio-controller; - gpio-ranges = <&pm6150_gpio 0 0 10>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - pm6150_lsid1: pmic@1 { - compatible = "qcom,pm6150", "qcom,spmi-pmic"; - reg = <0x1 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - }; -}; diff --git a/sys/gnu/dts/arm64/qcom/pm6150l.dtsi b/sys/gnu/dts/arm64/qcom/pm6150l.dtsi deleted file mode 100644 index f84027b505d..00000000000 --- a/sys/gnu/dts/arm64/qcom/pm6150l.dtsi +++ /dev/null @@ -1,31 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -// Copyright (c) 2019, The Linux Foundation. All rights reserved. - -#include -#include - -&spmi_bus { - pm6150l_lsid4: pmic@4 { - compatible = "qcom,pm6150l", "qcom,spmi-pmic"; - reg = <0x4 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - - pm6150l_gpio: gpios@c000 { - compatible = "qcom,pm6150l-gpio", "qcom,spmi-gpio"; - reg = <0xc000>; - gpio-controller; - gpio-ranges = <&pm6150l_gpio 0 0 12>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - pm6150l_lsid5: pmic@5 { - compatible = "qcom,pm6150l", "qcom,spmi-pmic"; - reg = <0x5 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - }; -}; diff --git a/sys/gnu/dts/arm64/qcom/pm8004.dtsi b/sys/gnu/dts/arm64/qcom/pm8004.dtsi deleted file mode 100644 index 0abd1abe12f..00000000000 --- a/sys/gnu/dts/arm64/qcom/pm8004.dtsi +++ /dev/null @@ -1,26 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include -#include - -&spmi_bus { - - pm8004_lsid4: pmic@4 { - compatible = "qcom,pm8004", "qcom,spmi-pmic"; - reg = <0x4 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - pm8004_lsid5: pmic@5 { - compatible = "qcom,pm8004", "qcom,spmi-pmic"; - reg = <0x5 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - pm8004_spmi_regulators: regulators { - compatible = "qcom,pm8004-regulators"; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/qcom/pm8005.dtsi b/sys/gnu/dts/arm64/qcom/pm8005.dtsi deleted file mode 100644 index 3f97607d8ba..00000000000 --- a/sys/gnu/dts/arm64/qcom/pm8005.dtsi +++ /dev/null @@ -1,32 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* Copyright 2018 Google LLC. */ - -#include -#include - -&spmi_bus { - pm8005_lsid0: pmic@4 { - compatible = "qcom,pm8005", "qcom,spmi-pmic"; - reg = <0x4 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - - pm8005_gpio: gpios@c000 { - compatible = "qcom,pm8005-gpio", "qcom,spmi-gpio"; - reg = <0xc000>; - gpio-controller; - gpio-ranges = <&pm8005_gpio 0 0 4>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - }; - - pm8005_lsid1: pmic@5 { - compatible = "qcom,pm8005", "qcom,spmi-pmic"; - reg = <0x5 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - }; -}; diff --git a/sys/gnu/dts/arm64/qcom/pm8150.dtsi b/sys/gnu/dts/arm64/qcom/pm8150.dtsi deleted file mode 100644 index b6e304748a5..00000000000 --- a/sys/gnu/dts/arm64/qcom/pm8150.dtsi +++ /dev/null @@ -1,97 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. - * Copyright (c) 2019, Linaro Limited - */ - -#include -#include -#include -#include - -&spmi_bus { - pm8150_0: pmic@0 { - compatible = "qcom,pm8150", "qcom,spmi-pmic"; - reg = <0x0 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - - pon: power-on@800 { - compatible = "qcom,pm8916-pon"; - reg = <0x0800>; - pwrkey { - compatible = "qcom,pm8941-pwrkey"; - interrupts = <0x0 0x8 0x0 IRQ_TYPE_EDGE_BOTH>; - debounce = <15625>; - bias-pull-up; - linux,code = ; - - status = "disabled"; - }; - }; - - pm8150_adc: adc@3100 { - compatible = "qcom,spmi-adc5"; - reg = <0x3100>; - #address-cells = <1>; - #size-cells = <0>; - #io-channel-cells = <1>; - interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; - - status = "disabled"; - - ref-gnd@0 { - reg = ; - qcom,pre-scaling = <1 1>; - label = "ref_gnd"; - }; - - vref-1p25@1 { - reg = ; - qcom,pre-scaling = <1 1>; - label = "vref_1p25"; - }; - - die-temp@6 { - reg = ; - qcom,pre-scaling = <1 1>; - label = "die_temp"; - }; - }; - - rtc@6000 { - compatible = "qcom,pm8941-rtc"; - reg = <0x6000>; - reg-names = "rtc", "alarm"; - interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>; - - status = "disabled"; - }; - - pm8150_gpios: gpio@c000 { - compatible = "qcom,pm8150-gpio"; - reg = <0xc000>; - gpio-controller; - #gpio-cells = <2>; - interrupts = <0x0 0xc0 0x0 IRQ_TYPE_NONE>, - <0x0 0xc1 0x0 IRQ_TYPE_NONE>, - <0x0 0xc2 0x0 IRQ_TYPE_NONE>, - <0x0 0xc3 0x0 IRQ_TYPE_NONE>, - <0x0 0xc4 0x0 IRQ_TYPE_NONE>, - <0x0 0xc5 0x0 IRQ_TYPE_NONE>, - <0x0 0xc6 0x0 IRQ_TYPE_NONE>, - <0x0 0xc7 0x0 IRQ_TYPE_NONE>, - <0x0 0xc8 0x0 IRQ_TYPE_NONE>, - <0x0 0xc9 0x0 IRQ_TYPE_NONE>, - <0x0 0xca 0x0 IRQ_TYPE_NONE>, - <0x0 0xcb 0x0 IRQ_TYPE_NONE>; - }; - }; - - pmic@1 { - compatible = "qcom,pm8150", "qcom,spmi-pmic"; - reg = <0x1 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - }; -}; diff --git a/sys/gnu/dts/arm64/qcom/pm8150b.dtsi b/sys/gnu/dts/arm64/qcom/pm8150b.dtsi deleted file mode 100644 index 322379d5c31..00000000000 --- a/sys/gnu/dts/arm64/qcom/pm8150b.dtsi +++ /dev/null @@ -1,86 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. - * Copyright (c) 2019, Linaro Limited - */ - -#include -#include -#include - -&spmi_bus { - pmic@2 { - compatible = "qcom,pm8150b", "qcom,spmi-pmic"; - reg = <0x2 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - - power-on@800 { - compatible = "qcom,pm8916-pon"; - reg = <0x0800>; - - status = "disabled"; - }; - - adc@3100 { - compatible = "qcom,spmi-adc5"; - reg = <0x3100>; - #address-cells = <1>; - #size-cells = <0>; - #io-channel-cells = <1>; - interrupts = <0x2 0x31 0x0 IRQ_TYPE_EDGE_RISING>; - - status = "disabled"; - - ref-gnd@0 { - reg = ; - qcom,pre-scaling = <1 1>; - label = "ref_gnd"; - }; - - vref-1p25@1 { - reg = ; - qcom,pre-scaling = <1 1>; - label = "vref_1p25"; - }; - - die-temp@6 { - reg = ; - qcom,pre-scaling = <1 1>; - label = "die_temp"; - }; - - chg-temp@9 { - reg = ; - qcom,pre-scaling = <1 1>; - label = "chg_temp"; - }; - }; - - pm8150b_gpios: gpio@c000 { - compatible = "qcom,pm8150b-gpio"; - reg = <0xc000>; - gpio-controller; - #gpio-cells = <2>; - interrupts = <0x2 0xc0 0x0 IRQ_TYPE_NONE>, - <0x2 0xc1 0x0 IRQ_TYPE_NONE>, - <0x2 0xc2 0x0 IRQ_TYPE_NONE>, - <0x2 0xc3 0x0 IRQ_TYPE_NONE>, - <0x2 0xc4 0x0 IRQ_TYPE_NONE>, - <0x2 0xc5 0x0 IRQ_TYPE_NONE>, - <0x2 0xc6 0x0 IRQ_TYPE_NONE>, - <0x2 0xc7 0x0 IRQ_TYPE_NONE>, - <0x2 0xc8 0x0 IRQ_TYPE_NONE>, - <0x2 0xc9 0x0 IRQ_TYPE_NONE>, - <0x2 0xca 0x0 IRQ_TYPE_NONE>, - <0x2 0xcb 0x0 IRQ_TYPE_NONE>; - }; - }; - - pmic@3 { - compatible = "qcom,pm8150b", "qcom,spmi-pmic"; - reg = <0x3 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - }; -}; diff --git a/sys/gnu/dts/arm64/qcom/pm8150l.dtsi b/sys/gnu/dts/arm64/qcom/pm8150l.dtsi deleted file mode 100644 index eb0e9a090e4..00000000000 --- a/sys/gnu/dts/arm64/qcom/pm8150l.dtsi +++ /dev/null @@ -1,80 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. - * Copyright (c) 2019, Linaro Limited - */ - -#include -#include -#include - -&spmi_bus { - pmic@4 { - compatible = "qcom,pm8150l", "qcom,spmi-pmic"; - reg = <0x4 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - - power-on@800 { - compatible = "qcom,pm8916-pon"; - reg = <0x0800>; - - status = "disabled"; - }; - - adc@3100 { - compatible = "qcom,spmi-adc5"; - reg = <0x3100>; - #address-cells = <1>; - #size-cells = <0>; - #io-channel-cells = <1>; - interrupts = <0x4 0x31 0x0 IRQ_TYPE_EDGE_RISING>; - - status = "disabled"; - - ref-gnd@0 { - reg = ; - qcom,pre-scaling = <1 1>; - label = "ref_gnd"; - }; - - vref-1p25@1 { - reg = ; - qcom,pre-scaling = <1 1>; - label = "vref_1p25"; - }; - - die-temp@6 { - reg = ; - qcom,pre-scaling = <1 1>; - label = "die_temp"; - }; - }; - - pm8150l_gpios: gpio@c000 { - compatible = "qcom,pm8150l-gpio"; - reg = <0xc000>; - gpio-controller; - #gpio-cells = <2>; - interrupts = <0x4 0xc0 0x0 IRQ_TYPE_NONE>, - <0x4 0xc1 0x0 IRQ_TYPE_NONE>, - <0x4 0xc2 0x0 IRQ_TYPE_NONE>, - <0x4 0xc3 0x0 IRQ_TYPE_NONE>, - <0x4 0xc4 0x0 IRQ_TYPE_NONE>, - <0x4 0xc5 0x0 IRQ_TYPE_NONE>, - <0x4 0xc6 0x0 IRQ_TYPE_NONE>, - <0x4 0xc7 0x0 IRQ_TYPE_NONE>, - <0x4 0xc8 0x0 IRQ_TYPE_NONE>, - <0x4 0xc9 0x0 IRQ_TYPE_NONE>, - <0x4 0xca 0x0 IRQ_TYPE_NONE>, - <0x4 0xcb 0x0 IRQ_TYPE_NONE>; - }; - }; - - pmic@5 { - compatible = "qcom,pm8150l", "qcom,spmi-pmic"; - reg = <0x5 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - }; -}; diff --git a/sys/gnu/dts/arm64/qcom/pm8916.dtsi b/sys/gnu/dts/arm64/qcom/pm8916.dtsi deleted file mode 100644 index 0bcdf047110..00000000000 --- a/sys/gnu/dts/arm64/qcom/pm8916.dtsi +++ /dev/null @@ -1,161 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include -#include -#include -#include - -&spmi_bus { - - pm8916_0: pm8916@0 { - compatible = "qcom,pm8916", "qcom,spmi-pmic"; - reg = <0x0 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - - rtc@6000 { - compatible = "qcom,pm8941-rtc"; - reg = <0x6000>; - reg-names = "rtc", "alarm"; - interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>; - }; - - pon@800 { - compatible = "qcom,pm8916-pon"; - reg = <0x800>; - mode-bootloader = <0x2>; - mode-recovery = <0x1>; - - pwrkey { - compatible = "qcom,pm8941-pwrkey"; - interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>; - debounce = <15625>; - bias-pull-up; - linux,code = ; - }; - - watchdog { - compatible = "qcom,pm8916-wdt"; - interrupts = <0x0 0x8 6 IRQ_TYPE_EDGE_RISING>; - timeout-sec = <60>; - }; - }; - - pm8916_gpios: gpios@c000 { - compatible = "qcom,pm8916-gpio"; - reg = <0xc000>; - gpio-controller; - #gpio-cells = <2>; - interrupts = <0 0xc0 0 IRQ_TYPE_NONE>, - <0 0xc1 0 IRQ_TYPE_NONE>, - <0 0xc2 0 IRQ_TYPE_NONE>, - <0 0xc3 0 IRQ_TYPE_NONE>; - }; - - pm8916_mpps: mpps@a000 { - compatible = "qcom,pm8916-mpp"; - reg = <0xa000>; - gpio-controller; - #gpio-cells = <2>; - interrupts = <0 0xa0 0 IRQ_TYPE_NONE>, - <0 0xa1 0 IRQ_TYPE_NONE>, - <0 0xa2 0 IRQ_TYPE_NONE>, - <0 0xa3 0 IRQ_TYPE_NONE>; - }; - - pm8916_temp: temp-alarm@2400 { - compatible = "qcom,spmi-temp-alarm"; - reg = <0x2400>; - interrupts = <0 0x24 0 IRQ_TYPE_EDGE_RISING>; - io-channels = <&pm8916_vadc VADC_DIE_TEMP>; - io-channel-names = "thermal"; - #thermal-sensor-cells = <0>; - }; - - pm8916_vadc: vadc@3100 { - compatible = "qcom,spmi-vadc"; - reg = <0x3100>; - interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; - #address-cells = <1>; - #size-cells = <0>; - #io-channel-cells = <1>; - - usb_in { - reg = ; - qcom,pre-scaling = <1 10>; - }; - vph_pwr { - reg = ; - qcom,pre-scaling = <1 3>; - }; - die_temp { - reg = ; - }; - ref_625mv { - reg = ; - }; - ref_1250v { - reg = ; - }; - ref_gnd { - reg = ; - }; - ref_vdd { - reg = ; - }; - }; - }; - - pm8916_1: pm8916@1 { - compatible = "qcom,pm8916", "qcom,spmi-pmic"; - reg = <0x1 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - - pm8916_vib: vibrator@c000 { - compatible = "qcom,pm8916-vib"; - reg = <0xc000>; - status = "disabled"; - }; - - wcd_codec: codec@f000 { - compatible = "qcom,pm8916-wcd-analog-codec"; - reg = <0xf000 0x200>; - reg-names = "pmic-codec-core"; - clocks = <&gcc GCC_CODEC_DIGCODEC_CLK>; - clock-names = "mclk"; - interrupt-parent = <&spmi_bus>; - interrupts = <0x1 0xf0 0x0 IRQ_TYPE_NONE>, - <0x1 0xf0 0x1 IRQ_TYPE_NONE>, - <0x1 0xf0 0x2 IRQ_TYPE_NONE>, - <0x1 0xf0 0x3 IRQ_TYPE_NONE>, - <0x1 0xf0 0x4 IRQ_TYPE_NONE>, - <0x1 0xf0 0x5 IRQ_TYPE_NONE>, - <0x1 0xf0 0x6 IRQ_TYPE_NONE>, - <0x1 0xf0 0x7 IRQ_TYPE_NONE>, - <0x1 0xf1 0x0 IRQ_TYPE_NONE>, - <0x1 0xf1 0x1 IRQ_TYPE_NONE>, - <0x1 0xf1 0x2 IRQ_TYPE_NONE>, - <0x1 0xf1 0x3 IRQ_TYPE_NONE>, - <0x1 0xf1 0x4 IRQ_TYPE_NONE>, - <0x1 0xf1 0x5 IRQ_TYPE_NONE>; - interrupt-names = "cdc_spk_cnp_int", - "cdc_spk_clip_int", - "cdc_spk_ocp_int", - "mbhc_ins_rem_det1", - "mbhc_but_rel_det", - "mbhc_but_press_det", - "mbhc_ins_rem_det", - "mbhc_switch_int", - "cdc_ear_ocp_int", - "cdc_hphr_ocp_int", - "cdc_hphl_ocp_det", - "cdc_ear_cnp_int", - "cdc_hphr_cnp_int", - "cdc_hphl_cnp_int"; - vdd-cdc-io-supply = <&pm8916_l5>; - vdd-cdc-tx-rx-cx-supply = <&pm8916_l5>; - vdd-micbias-supply = <&pm8916_l13>; - #sound-dai-cells = <1>; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/qcom/pm8994.dtsi b/sys/gnu/dts/arm64/qcom/pm8994.dtsi deleted file mode 100644 index 7e4f777746c..00000000000 --- a/sys/gnu/dts/arm64/qcom/pm8994.dtsi +++ /dev/null @@ -1,93 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include -#include -#include - -&spmi_bus { - - pmic@0 { - compatible = "qcom,pm8994", "qcom,spmi-pmic"; - reg = <0x0 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - - rtc@6000 { - compatible = "qcom,pm8941-rtc"; - reg = <0x6000>, <0x6100>; - reg-names = "rtc", "alarm"; - interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>; - }; - - pon@800 { - compatible = "qcom,pm8916-pon"; - - reg = <0x800>; - mode-bootloader = <0x2>; - mode-recovery = <0x1>; - - pwrkey { - compatible = "qcom,pm8941-pwrkey"; - interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>; - debounce = <15625>; - bias-pull-up; - linux,code = ; - }; - - }; - - pm8994_gpios: gpios@c000 { - compatible = "qcom,pm8994-gpio"; - reg = <0xc000>; - gpio-controller; - #gpio-cells = <2>; - interrupts = <0 0xc0 0 IRQ_TYPE_NONE>, - <0 0xc1 0 IRQ_TYPE_NONE>, - <0 0xc2 0 IRQ_TYPE_NONE>, - <0 0xc3 0 IRQ_TYPE_NONE>, - <0 0xc4 0 IRQ_TYPE_NONE>, - <0 0xc5 0 IRQ_TYPE_NONE>, - <0 0xc6 0 IRQ_TYPE_NONE>, - <0 0xc7 0 IRQ_TYPE_NONE>, - <0 0xc8 0 IRQ_TYPE_NONE>, - <0 0xc9 0 IRQ_TYPE_NONE>, - <0 0xca 0 IRQ_TYPE_NONE>, - <0 0xcb 0 IRQ_TYPE_NONE>, - <0 0xcc 0 IRQ_TYPE_NONE>, - <0 0xcd 0 IRQ_TYPE_NONE>, - <0 0xce 0 IRQ_TYPE_NONE>, - <0 0xcf 0 IRQ_TYPE_NONE>, - <0 0xd0 0 IRQ_TYPE_NONE>, - <0 0xd1 0 IRQ_TYPE_NONE>, - <0 0xd2 0 IRQ_TYPE_NONE>, - <0 0xd3 0 IRQ_TYPE_NONE>, - <0 0xd4 0 IRQ_TYPE_NONE>, - <0 0xd5 0 IRQ_TYPE_NONE>; - }; - - pm8994_mpps: mpps@a000 { - compatible = "qcom,pm8994-mpp"; - reg = <0xa000>; - gpio-controller; - #gpio-cells = <2>; - interrupts = <0 0xa0 0 IRQ_TYPE_NONE>, - <0 0xa1 0 IRQ_TYPE_NONE>, - <0 0xa2 0 IRQ_TYPE_NONE>, - <0 0xa3 0 IRQ_TYPE_NONE>, - <0 0xa4 0 IRQ_TYPE_NONE>, - <0 0xa5 0 IRQ_TYPE_NONE>, - <0 0xa6 0 IRQ_TYPE_NONE>, - <0 0xa7 0 IRQ_TYPE_NONE>; - }; - }; - - pmic@1 { - compatible = "qcom,pm8994", "qcom,spmi-pmic"; - reg = <0x1 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - - pm8994_spmi_regulators: regulators { - compatible = "qcom,pm8994-regulators"; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/qcom/pm8998.dtsi b/sys/gnu/dts/arm64/qcom/pm8998.dtsi deleted file mode 100644 index dc2ce23cde0..00000000000 --- a/sys/gnu/dts/arm64/qcom/pm8998.dtsi +++ /dev/null @@ -1,112 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* Copyright 2018 Google LLC. */ - -#include -#include -#include -#include -#include - -/ { - thermal-zones { - pm8998 { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&pm8998_temp>; - - trips { - pm8998_alert0: pm8998-alert0 { - temperature = <105000>; - hysteresis = <2000>; - type = "passive"; - }; - pm8998_crit: pm8998-crit { - temperature = <125000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - }; -}; - -&spmi_bus { - pm8998_lsid0: pmic@0 { - compatible = "qcom,pm8998", "qcom,spmi-pmic"; - reg = <0x0 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - - pm8998_pon: pon@800 { - compatible = "qcom,pm8998-pon"; - - reg = <0x800>; - mode-bootloader = <0x2>; - mode-recovery = <0x1>; - - pwrkey { - compatible = "qcom,pm8941-pwrkey"; - interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>; - debounce = <15625>; - bias-pull-up; - linux,code = ; - }; - }; - - pm8998_temp: temp-alarm@2400 { - compatible = "qcom,spmi-temp-alarm"; - reg = <0x2400>; - interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_RISING>; - io-channels = <&pm8998_adc ADC5_DIE_TEMP>; - io-channel-names = "thermal"; - #thermal-sensor-cells = <0>; - }; - - pm8998_coincell: coincell@2800 { - compatible = "qcom,pm8941-coincell"; - reg = <0x2800>; - - status = "disabled"; - }; - - pm8998_adc: adc@3100 { - compatible = "qcom,spmi-adc-rev2"; - reg = <0x3100>; - interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; - #address-cells = <1>; - #size-cells = <0>; - #io-channel-cells = <1>; - - adc-chan@6 { - reg = ; - label = "die_temp"; - }; - }; - - rtc@6000 { - compatible = "qcom,pm8941-rtc"; - reg = <0x6000>, <0x6100>; - reg-names = "rtc", "alarm"; - interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>; - }; - - pm8998_gpio: gpios@c000 { - compatible = "qcom,pm8998-gpio", "qcom,spmi-gpio"; - reg = <0xc000>; - gpio-controller; - gpio-ranges = <&pm8998_gpio 0 0 26>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - }; - - pm8998_lsid1: pmic@1 { - compatible = "qcom,pm8998", "qcom,spmi-pmic"; - reg = <0x1 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - }; -}; diff --git a/sys/gnu/dts/arm64/qcom/pmi8994.dtsi b/sys/gnu/dts/arm64/qcom/pmi8994.dtsi deleted file mode 100644 index 21e05215abe..00000000000 --- a/sys/gnu/dts/arm64/qcom/pmi8994.dtsi +++ /dev/null @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include -#include - -&spmi_bus { - - pmic@2 { - compatible = "qcom,pmi8994", "qcom,spmi-pmic"; - reg = <0x2 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - - pmi8994_gpios: gpios@c000 { - compatible = "qcom,pmi8994-gpio", "qcom,spmi-gpio"; - reg = <0xc000>; - gpio-controller; - gpio-ranges = <&pmi8994_gpios 0 0 10>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - pmic@3 { - compatible = "qcom,pmi8994", "qcom,spmi-pmic"; - reg = <0x3 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - }; -}; diff --git a/sys/gnu/dts/arm64/qcom/pmi8998.dtsi b/sys/gnu/dts/arm64/qcom/pmi8998.dtsi deleted file mode 100644 index 23f9146a161..00000000000 --- a/sys/gnu/dts/arm64/qcom/pmi8998.dtsi +++ /dev/null @@ -1,29 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include -#include - -&spmi_bus { - pmi8998_lsid0: pmic@2 { - compatible = "qcom,pmi8998", "qcom,spmi-pmic"; - reg = <0x2 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - - pmi8998_gpio: gpios@c000 { - compatible = "qcom,pmi8998-gpio", "qcom,spmi-gpio"; - reg = <0xc000>; - gpio-controller; - gpio-ranges = <&pmi8998_gpio 0 0 14>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - pmi8998_lsid1: pmic@3 { - compatible = "qcom,pmi8998", "qcom,spmi-pmic"; - reg = <0x3 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - }; -}; diff --git a/sys/gnu/dts/arm64/qcom/pms405.dtsi b/sys/gnu/dts/arm64/qcom/pms405.dtsi deleted file mode 100644 index ff400518689..00000000000 --- a/sys/gnu/dts/arm64/qcom/pms405.dtsi +++ /dev/null @@ -1,149 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (c) 2018, Linaro Limited - -#include -#include -#include -#include - -/ { - thermal-zones { - pms405 { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&pms405_temp>; - - trips { - pms405_alert0: pms405-alert0 { - temperature = <105000>; - hysteresis = <2000>; - type = "passive"; - }; - pms405_crit: pms405-crit { - temperature = <125000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - }; -}; - -&spmi_bus { - pms405_0: pms405@0 { - compatible = "qcom,spmi-pmic"; - reg = <0x0 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - - pms405_gpios: gpio@c000 { - compatible = "qcom,pms405-gpio"; - reg = <0xc000>; - gpio-controller; - #gpio-cells = <2>; - interrupts = <0 0xc0 0 IRQ_TYPE_NONE>, - <0 0xc1 0 IRQ_TYPE_NONE>, - <0 0xc2 0 IRQ_TYPE_NONE>, - <0 0xc3 0 IRQ_TYPE_NONE>, - <0 0xc4 0 IRQ_TYPE_NONE>, - <0 0xc5 0 IRQ_TYPE_NONE>, - <0 0xc6 0 IRQ_TYPE_NONE>, - <0 0xc7 0 IRQ_TYPE_NONE>, - <0 0xc8 0 IRQ_TYPE_NONE>, - <0 0xc9 0 IRQ_TYPE_NONE>, - <0 0xca 0 IRQ_TYPE_NONE>, - <0 0xcb 0 IRQ_TYPE_NONE>; - }; - - pon@800 { - compatible = "qcom,pms405-pon"; - reg = <0x0800>; - mode-bootloader = <0x2>; - mode-recovery = <0x1>; - - pwrkey { - compatible = "qcom,pm8941-pwrkey"; - interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>; - debounce = <15625>; - bias-pull-up; - linux,code = ; - }; - }; - - pms405_temp: temp-alarm@2400 { - compatible = "qcom,spmi-temp-alarm"; - reg = <0x2400>; - interrupts = <0 0x24 0 IRQ_TYPE_EDGE_RISING>; - io-channels = <&pms405_adc ADC5_DIE_TEMP>; - io-channel-names = "thermal"; - #thermal-sensor-cells = <0>; - }; - - pms405_adc: adc@3100 { - compatible = "qcom,pms405-adc", "qcom,spmi-adc-rev2"; - reg = <0x3100>; - interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; - #address-cells = <1>; - #size-cells = <0>; - #io-channel-cells = <1>; - - ref_gnd@0 { - reg = ; - qcom,pre-scaling = <1 1>; - }; - - vref_1p25@1 { - reg = ; - qcom,pre-scaling = <1 1>; - }; - - pon_1: vph_pwr@131 { - reg = ; - qcom,pre-scaling = <1 3>; - }; - - die_temp@6 { - reg = ; - qcom,pre-scaling = <1 1>; - }; - - pa_therm1: thermistor1@77 { - reg = ; - qcom,ratiometric; - qcom,hw-settle-time = <200>; - qcom,pre-scaling = <1 1>; - }; - - pa_therm3: thermistor3@79 { - reg = ; - qcom,ratiometric; - qcom,hw-settle-time = <200>; - qcom,pre-scaling = <1 1>; - }; - - xo_therm: xo_temp@76 { - reg = ; - qcom,ratiometric; - qcom,hw-settle-time = <200>; - qcom,pre-scaling = <1 1>; - }; - }; - - rtc@6000 { - compatible = "qcom,pm8941-rtc"; - reg = <0x6000>; - reg-names = "rtc", "alarm"; - interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>; - }; - }; - - pms405_1: pms405@1 { - compatible = "qcom,spmi-pmic"; - reg = <0x1 SPMI_USID>; - - pms405_spmi_regulators: regulators { - compatible = "qcom,pms405-regulators"; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/qcom/qcs404-evb-1000.dts b/sys/gnu/dts/arm64/qcom/qcs404-evb-1000.dts deleted file mode 100644 index 937eb4555ff..00000000000 --- a/sys/gnu/dts/arm64/qcom/qcs404-evb-1000.dts +++ /dev/null @@ -1,12 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (c) 2018, Linaro Limited - -/dts-v1/; - -#include "qcs404-evb.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. QCS404 EVB 1000"; - compatible = "qcom,qcs404-evb-1000", "qcom,qcs404-evb", - "qcom,qcs404"; -}; diff --git a/sys/gnu/dts/arm64/qcom/qcs404-evb-4000.dts b/sys/gnu/dts/arm64/qcom/qcs404-evb-4000.dts deleted file mode 100644 index 479ad3ac6c2..00000000000 --- a/sys/gnu/dts/arm64/qcom/qcs404-evb-4000.dts +++ /dev/null @@ -1,94 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (c) 2018, Linaro Limited - -/dts-v1/; - -#include -#include "qcs404-evb.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. QCS404 EVB 4000"; - compatible = "qcom,qcs404-evb-4000", "qcom,qcs404-evb", - "qcom,qcs404"; -}; - -ðernet { - status = "ok"; - - snps,reset-gpio = <&tlmm 60 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 10000>; - - pinctrl-names = "default"; - pinctrl-0 = <ðernet_defaults>; - - phy-handle = <&phy1>; - phy-mode = "rgmii"; - mdio { - #address-cells = <0x1>; - #size-cells = <0x0>; - compatible = "snps,dwmac-mdio"; - phy1: phy@4 { - compatible = "ethernet-phy-ieee802.3-c22"; - device_type = "ethernet-phy"; - reg = <0x4>; - }; - }; -}; - -&tlmm { - ethernet_defaults: ethernet-defaults { - int { - pins = "gpio61"; - function = "rgmii_int"; - bias-disable; - drive-strength = <2>; - }; - mdc { - pins = "gpio76"; - function = "rgmii_mdc"; - bias-pull-up; - }; - mdio { - pins = "gpio75"; - function = "rgmii_mdio"; - bias-pull-up; - }; - tx { - pins = "gpio67", "gpio66", "gpio65", "gpio64"; - function = "rgmii_tx"; - bias-pull-up; - drive-strength = <16>; - }; - rx { - pins = "gpio73", "gpio72", "gpio71", "gpio70"; - function = "rgmii_rx"; - bias-disable; - drive-strength = <2>; - }; - tx-ctl { - pins = "gpio68"; - function = "rgmii_ctl"; - bias-pull-up; - drive-strength = <16>; - }; - rx-ctl { - pins = "gpio74"; - function = "rgmii_ctl"; - bias-disable; - drive-strength = <2>; - }; - tx-ck { - pins = "gpio63"; - function = "rgmii_ck"; - bias-pull-up; - drive-strength = <16>; - }; - rx-ck { - pins = "gpio69"; - function = "rgmii_ck"; - bias-disable; - drive-strength = <2>; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/qcom/qcs404-evb.dtsi b/sys/gnu/dts/arm64/qcom/qcs404-evb.dtsi deleted file mode 100644 index 522d3ef72df..00000000000 --- a/sys/gnu/dts/arm64/qcom/qcs404-evb.dtsi +++ /dev/null @@ -1,311 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (c) 2018, Linaro Limited - -#include -#include "qcs404.dtsi" -#include "pms405.dtsi" - -/ { - aliases { - serial0 = &blsp1_uart2; - serial1 = &blsp1_uart3; - }; - - chosen { - stdout-path = "serial0"; - }; - - vph_pwr: vph-pwr-regulator { - compatible = "regulator-fixed"; - regulator-name = "vph_pwr"; - regulator-always-on; - regulator-boot-on; - }; - - vdd_ch0_3p3: - vdd_esmps3_3p3: vdd-esmps3-3p3-regulator { - compatible = "regulator-fixed"; - regulator-name = "eSMPS3_3P3"; - - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; -}; - -&blsp1_uart3 { - status = "okay"; - - bluetooth { - compatible = "qcom,wcn3990-bt"; - vddio-supply = <&vreg_l6_1p8>; - vddxo-supply = <&vreg_l5_1p8>; - vddrf-supply = <&vreg_l1_1p3>; - vddch0-supply = <&vdd_ch0_3p3>; - - local-bd-address = [ 02 00 00 00 5a ad ]; - - max-speed = <3200000>; - }; -}; - -&blsp1_dma { - qcom,controlled-remotely; -}; - -&blsp2_dma { - qcom,controlled-remotely; -}; - -&gcc { - protected-clocks = , - , - , - , - <141>, /* GCC_WCSS_Q6_AHB_CLK */ - <142>; /* GCC_WCSS_Q6_AXIM_CLK */ -}; - -&pms405_spmi_regulators { - vdd_s3-supply = <&vph_pwr>; - - pms405_s3: s3 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vdd_apc"; - regulator-initial-mode = <1>; - regulator-min-microvolt = <1048000>; - regulator-max-microvolt = <1384000>; - }; -}; - -&pcie { - status = "ok"; - - perst-gpio = <&tlmm 43 GPIO_ACTIVE_LOW>; - - pinctrl-names = "default"; - pinctrl-0 = <&perst_state>; -}; - -&pcie_phy { - status = "ok"; - - vdda-vp-supply = <&vreg_l3_1p05>; - vdda-vph-supply = <&vreg_l5_1p8>; -}; - -&remoteproc_adsp { - status = "ok"; -}; - -&remoteproc_cdsp { - status = "ok"; -}; - -&remoteproc_wcss { - status = "ok"; -}; - -&rpm_requests { - pms405-regulators { - compatible = "qcom,rpm-pms405-regulators"; - - vdd_s1-supply = <&vph_pwr>; - vdd_s2-supply = <&vph_pwr>; - vdd_s3-supply = <&vph_pwr>; - vdd_s4-supply = <&vph_pwr>; - vdd_s5-supply = <&vph_pwr>; - vdd_l1_l2-supply = <&vreg_s5_1p35>; - vdd_l3_l8-supply = <&vreg_s5_1p35>; - vdd_l4-supply = <&vreg_s5_1p35>; - vdd_l5_l6-supply = <&vreg_s4_1p8>; - vdd_l7-supply = <&vph_pwr>; - vdd_l9-supply = <&vreg_s5_1p35>; - vdd_l10_l11_l12_l13-supply = <&vph_pwr>; - - vreg_s4_1p8: s4 { - regulator-min-microvolt = <1728000>; - regulator-max-microvolt = <1920000>; - }; - - vreg_s5_1p35: s5 { - regulator-min-microvolt = <1352000>; - regulator-max-microvolt = <1352000>; - }; - - vreg_l1_1p3: l1 { - regulator-min-microvolt = <1240000>; - regulator-max-microvolt = <1352000>; - }; - - vreg_l2_1p275: l2 { - regulator-min-microvolt = <1048000>; - regulator-max-microvolt = <1280000>; - }; - - vreg_l3_1p05: l3 { - regulator-min-microvolt = <1048000>; - regulator-max-microvolt = <1160000>; - }; - - vreg_l4_1p2: l4 { - regulator-min-microvolt = <1144000>; - regulator-max-microvolt = <1256000>; - }; - - vreg_l5_1p8: l5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vreg_l6_1p8: l6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vreg_l7_1p8: l7 { - regulator-min-microvolt = <1616000>; - regulator-max-microvolt = <3000000>; - }; - - vreg_l8_1p2: l8 { - regulator-min-microvolt = <1136000>; - regulator-max-microvolt = <1352000>; - }; - - vreg_l10_3p3: l10 { - regulator-min-microvolt = <2936000>; - regulator-max-microvolt = <3088000>; - }; - - vreg_l11_sdc2: l11 { - regulator-min-microvolt = <2696000>; - regulator-max-microvolt = <3304000>; - }; - - vreg_l12_3p3: l12 { - regulator-min-microvolt = <2968000>; - regulator-max-microvolt = <3300000>; - }; - - vreg_l13_3p3: l13 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - }; - }; -}; - -&sdcc1 { - status = "ok"; - - mmc-ddr-1_8v; - mmc-hs400-1_8v; - bus-width = <8>; - non-removable; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc1_on>; - pinctrl-1 = <&sdc1_off>; -}; - -&tlmm { - perst_state: perst { - pins = "gpio43"; - function = "gpio"; - - drive-strength = <2>; - bias-disable; - output-low; - }; - - sdc1_on: sdc1-on { - clk { - pins = "sdc1_clk"; - bias-disable; - drive-strength = <16>; - }; - - cmd { - pins = "sdc1_cmd"; - bias-pull-up; - drive-strength = <10>; - }; - - data { - pins = "sdc1_data"; - bias-pull-up; - drive-strength = <10>; - }; - - rclk { - pins = "sdc1_rclk"; - bias-pull-down; - }; - }; - - sdc1_off: sdc1-off { - clk { - pins = "sdc1_clk"; - bias-disable; - drive-strength = <2>; - }; - - cmd { - pins = "sdc1_cmd"; - bias-pull-up; - drive-strength = <2>; - }; - - data { - pins = "sdc1_data"; - bias-pull-up; - drive-strength = <2>; - }; - - rclk { - pins = "sdc1_rclk"; - bias-pull-down; - }; - }; -}; - -&wifi { - status = "okay"; - vdd-0.8-cx-mx-supply = <&vreg_l2_1p275>; - vdd-1.8-xo-supply = <&vreg_l5_1p8>; - vdd-1.3-rfa-supply = <&vreg_l1_1p3>; -}; - -/* PINCTRL - additions to nodes defined in qcs404.dtsi */ - -&blsp1_uart2_default { - rx { - drive-strength = <2>; - bias-disable; - }; - - tx { - drive-strength = <2>; - bias-disable; - }; -}; - -&blsp1_uart3_default { - cts { - pins = "gpio84"; - bias-disable; - }; - - rts-tx { - pins = "gpio85", "gpio82"; - drive-strength = <2>; - bias-disable; - }; - - rx { - pins = "gpio83"; - bias-pull-up; - }; -}; diff --git a/sys/gnu/dts/arm64/qcom/qcs404.dtsi b/sys/gnu/dts/arm64/qcom/qcs404.dtsi deleted file mode 100644 index 4ee1e3d5f12..00000000000 --- a/sys/gnu/dts/arm64/qcom/qcs404.dtsi +++ /dev/null @@ -1,1527 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (c) 2018, Linaro Limited - -#include -#include -#include -#include -#include -#include - -/ { - interrupt-parent = <&intc>; - - #address-cells = <2>; - #size-cells = <2>; - - chosen { }; - - clocks { - xo_board: xo-board { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <19200000>; - }; - - sleep_clk: sleep-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - CPU0: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x100>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - next-level-cache = <&L2_0>; - #cooling-cells = <2>; - clocks = <&apcs_glb>; - operating-points-v2 = <&cpu_opp_table>; - power-domains = <&cpr>; - power-domain-names = "cpr"; - }; - - CPU1: cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x101>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - next-level-cache = <&L2_0>; - #cooling-cells = <2>; - clocks = <&apcs_glb>; - operating-points-v2 = <&cpu_opp_table>; - power-domains = <&cpr>; - power-domain-names = "cpr"; - }; - - CPU2: cpu@102 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x102>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - next-level-cache = <&L2_0>; - #cooling-cells = <2>; - clocks = <&apcs_glb>; - operating-points-v2 = <&cpu_opp_table>; - power-domains = <&cpr>; - power-domain-names = "cpr"; - }; - - CPU3: cpu@103 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x103>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - next-level-cache = <&L2_0>; - #cooling-cells = <2>; - clocks = <&apcs_glb>; - operating-points-v2 = <&cpu_opp_table>; - power-domains = <&cpr>; - power-domain-names = "cpr"; - }; - - L2_0: l2-cache { - compatible = "cache"; - cache-level = <2>; - }; - - idle-states { - entry-method = "psci"; - - CPU_SLEEP_0: cpu-sleep-0 { - compatible = "arm,idle-state"; - idle-state-name = "standalone-power-collapse"; - arm,psci-suspend-param = <0x40000003>; - entry-latency-us = <125>; - exit-latency-us = <180>; - min-residency-us = <595>; - local-timer-stop; - }; - }; - }; - - cpu_opp_table: cpu-opp-table { - compatible = "operating-points-v2-kryo-cpu"; - opp-shared; - - opp-1094400000 { - opp-hz = /bits/ 64 <1094400000>; - required-opps = <&cpr_opp1>; - }; - opp-1248000000 { - opp-hz = /bits/ 64 <1248000000>; - required-opps = <&cpr_opp2>; - }; - opp-1401600000 { - opp-hz = /bits/ 64 <1401600000>; - required-opps = <&cpr_opp3>; - }; - }; - - cpr_opp_table: cpr-opp-table { - compatible = "operating-points-v2-qcom-level"; - - cpr_opp1: opp1 { - opp-level = <1>; - qcom,opp-fuse-level = <1>; - }; - cpr_opp2: opp2 { - opp-level = <2>; - qcom,opp-fuse-level = <2>; - }; - cpr_opp3: opp3 { - opp-level = <3>; - qcom,opp-fuse-level = <3>; - }; - }; - - firmware { - scm: scm { - compatible = "qcom,scm-qcs404", "qcom,scm"; - #reset-cells = <1>; - }; - }; - - memory@80000000 { - device_type = "memory"; - /* We expect the bootloader to fill in the size */ - reg = <0 0x80000000 0 0>; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - tz_apps_mem: memory@85900000 { - reg = <0 0x85900000 0 0x500000>; - no-map; - }; - - xbl_mem: memory@85e00000 { - reg = <0 0x85e00000 0 0x100000>; - no-map; - }; - - smem_region: memory@85f00000 { - reg = <0 0x85f00000 0 0x200000>; - no-map; - }; - - tz_mem: memory@86100000 { - reg = <0 0x86100000 0 0x300000>; - no-map; - }; - - wlan_fw_mem: memory@86400000 { - reg = <0 0x86400000 0 0x1100000>; - no-map; - }; - - adsp_fw_mem: memory@87500000 { - reg = <0 0x87500000 0 0x1a00000>; - no-map; - }; - - cdsp_fw_mem: memory@88f00000 { - reg = <0 0x88f00000 0 0x600000>; - no-map; - }; - - wlan_msa_mem: memory@89500000 { - reg = <0 0x89500000 0 0x100000>; - no-map; - }; - - uefi_mem: memory@9f800000 { - reg = <0 0x9f800000 0 0x800000>; - no-map; - }; - }; - - rpm-glink { - compatible = "qcom,glink-rpm"; - - interrupts = ; - qcom,rpm-msg-ram = <&rpm_msg_ram>; - mboxes = <&apcs_glb 0>; - - rpm_requests: glink-channel { - compatible = "qcom,rpm-qcs404"; - qcom,glink-channels = "rpm_requests"; - - rpmcc: clock-controller { - compatible = "qcom,rpmcc-qcs404"; - #clock-cells = <1>; - }; - - rpmpd: power-controller { - compatible = "qcom,qcs404-rpmpd"; - #power-domain-cells = <1>; - operating-points-v2 = <&rpmpd_opp_table>; - - rpmpd_opp_table: opp-table { - compatible = "operating-points-v2"; - - rpmpd_opp_ret: opp1 { - opp-level = <16>; - }; - - rpmpd_opp_ret_plus: opp2 { - opp-level = <32>; - }; - - rpmpd_opp_min_svs: opp3 { - opp-level = <48>; - }; - - rpmpd_opp_low_svs: opp4 { - opp-level = <64>; - }; - - rpmpd_opp_svs: opp5 { - opp-level = <128>; - }; - - rpmpd_opp_svs_plus: opp6 { - opp-level = <192>; - }; - - rpmpd_opp_nom: opp7 { - opp-level = <256>; - }; - - rpmpd_opp_nom_plus: opp8 { - opp-level = <320>; - }; - - rpmpd_opp_turbo: opp9 { - opp-level = <384>; - }; - - rpmpd_opp_turbo_no_cpr: opp10 { - opp-level = <416>; - }; - - rpmpd_opp_turbo_plus: opp11 { - opp-level = <512>; - }; - }; - }; - }; - }; - - smem { - compatible = "qcom,smem"; - - memory-region = <&smem_region>; - qcom,rpm-msg-ram = <&rpm_msg_ram>; - - hwlocks = <&tcsr_mutex 3>; - }; - - tcsr_mutex: hwlock { - compatible = "qcom,tcsr-mutex"; - syscon = <&tcsr_mutex_regs 0 0x1000>; - #hwlock-cells = <1>; - }; - - soc: soc@0 { - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0 0xffffffff>; - compatible = "simple-bus"; - - turingcc: clock-controller@800000 { - compatible = "qcom,qcs404-turingcc"; - reg = <0x00800000 0x30000>; - clocks = <&gcc GCC_CDSP_CFG_AHB_CLK>; - - #clock-cells = <1>; - #reset-cells = <1>; - - status = "disabled"; - }; - - rpm_msg_ram: memory@60000 { - compatible = "qcom,rpm-msg-ram"; - reg = <0x00060000 0x6000>; - }; - - qfprom: qfprom@a4000 { - compatible = "qcom,qfprom"; - reg = <0x000a4000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - tsens_caldata: caldata@d0 { - reg = <0x1f8 0x14>; - }; - cpr_efuse_speedbin: speedbin@13c { - reg = <0x13c 0x4>; - bits = <2 3>; - }; - cpr_efuse_quot_offset1: qoffset1@231 { - reg = <0x231 0x4>; - bits = <4 7>; - }; - cpr_efuse_quot_offset2: qoffset2@232 { - reg = <0x232 0x4>; - bits = <3 7>; - }; - cpr_efuse_quot_offset3: qoffset3@233 { - reg = <0x233 0x4>; - bits = <2 7>; - }; - cpr_efuse_init_voltage1: ivoltage1@229 { - reg = <0x229 0x4>; - bits = <4 6>; - }; - cpr_efuse_init_voltage2: ivoltage2@22a { - reg = <0x22a 0x4>; - bits = <2 6>; - }; - cpr_efuse_init_voltage3: ivoltage3@22b { - reg = <0x22b 0x4>; - bits = <0 6>; - }; - cpr_efuse_quot1: quot1@22b { - reg = <0x22b 0x4>; - bits = <6 12>; - }; - cpr_efuse_quot2: quot2@22d { - reg = <0x22d 0x4>; - bits = <2 12>; - }; - cpr_efuse_quot3: quot3@230 { - reg = <0x230 0x4>; - bits = <0 12>; - }; - cpr_efuse_ring1: ring1@228 { - reg = <0x228 0x4>; - bits = <0 3>; - }; - cpr_efuse_ring2: ring2@228 { - reg = <0x228 0x4>; - bits = <4 3>; - }; - cpr_efuse_ring3: ring3@229 { - reg = <0x229 0x4>; - bits = <0 3>; - }; - cpr_efuse_revision: revision@218 { - reg = <0x218 0x4>; - bits = <3 3>; - }; - }; - - rng: rng@e3000 { - compatible = "qcom,prng-ee"; - reg = <0x000e3000 0x1000>; - clocks = <&gcc GCC_PRNG_AHB_CLK>; - clock-names = "core"; - }; - - bimc: interconnect@400000 { - reg = <0x00400000 0x80000>; - compatible = "qcom,qcs404-bimc"; - #interconnect-cells = <1>; - clock-names = "bus", "bus_a"; - clocks = <&rpmcc RPM_SMD_BIMC_CLK>, - <&rpmcc RPM_SMD_BIMC_A_CLK>; - }; - - tsens: thermal-sensor@4a9000 { - compatible = "qcom,qcs404-tsens", "qcom,tsens-v1"; - reg = <0x004a9000 0x1000>, /* TM */ - <0x004a8000 0x1000>; /* SROT */ - nvmem-cells = <&tsens_caldata>; - nvmem-cell-names = "calib"; - #qcom,sensors = <10>; - interrupts = ; - interrupt-names = "uplow"; - #thermal-sensor-cells = <1>; - }; - - pcnoc: interconnect@500000 { - reg = <0x00500000 0x15080>; - compatible = "qcom,qcs404-pcnoc"; - #interconnect-cells = <1>; - clock-names = "bus", "bus_a"; - clocks = <&rpmcc RPM_SMD_PNOC_CLK>, - <&rpmcc RPM_SMD_PNOC_A_CLK>; - }; - - snoc: interconnect@580000 { - reg = <0x00580000 0x23080>; - compatible = "qcom,qcs404-snoc"; - #interconnect-cells = <1>; - clock-names = "bus", "bus_a"; - clocks = <&rpmcc RPM_SMD_SNOC_CLK>, - <&rpmcc RPM_SMD_SNOC_A_CLK>; - }; - - remoteproc_cdsp: remoteproc@b00000 { - compatible = "qcom,qcs404-cdsp-pas"; - reg = <0x00b00000 0x4040>; - - interrupts-extended = <&intc GIC_SPI 229 IRQ_TYPE_EDGE_RISING>, - <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, - <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, - <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", - "handover", "stop-ack"; - - clocks = <&xo_board>, - <&gcc GCC_CDSP_CFG_AHB_CLK>, - <&gcc GCC_CDSP_TBU_CLK>, - <&gcc GCC_BIMC_CDSP_CLK>, - <&turingcc TURING_WRAPPER_AON_CLK>, - <&turingcc TURING_Q6SS_AHBS_AON_CLK>, - <&turingcc TURING_Q6SS_AHBM_AON_CLK>, - <&turingcc TURING_Q6SS_Q6_AXIM_CLK>; - clock-names = "xo", - "sway", - "tbu", - "bimc", - "ahb_aon", - "q6ss_slave", - "q6ss_master", - "q6_axim"; - - resets = <&gcc GCC_CDSP_RESTART>; - reset-names = "restart"; - - qcom,halt-regs = <&tcsr 0x19004>; - - memory-region = <&cdsp_fw_mem>; - - qcom,smem-states = <&cdsp_smp2p_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - glink-edge { - interrupts = ; - - qcom,remote-pid = <5>; - mboxes = <&apcs_glb 12>; - - label = "cdsp"; - }; - }; - - tlmm: pinctrl@1000000 { - compatible = "qcom,qcs404-pinctrl"; - reg = <0x01000000 0x200000>, - <0x01300000 0x200000>, - <0x07b00000 0x200000>; - reg-names = "south", "north", "east"; - interrupts = ; - gpio-ranges = <&tlmm 0 0 120>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - - blsp1_i2c0_default: blsp1-i2c0-default { - pins = "gpio32", "gpio33"; - function = "blsp_i2c0"; - }; - - blsp1_i2c1_default: blsp1-i2c1-default { - pins = "gpio24", "gpio25"; - function = "blsp_i2c1"; - }; - - blsp1_i2c2_default: blsp1-i2c2-default { - sda { - pins = "gpio19"; - function = "blsp_i2c_sda_a2"; - }; - - scl { - pins = "gpio20"; - function = "blsp_i2c_scl_a2"; - }; - }; - - blsp1_i2c3_default: blsp1-i2c3-default { - pins = "gpio84", "gpio85"; - function = "blsp_i2c3"; - }; - - blsp1_i2c4_default: blsp1-i2c4-default { - pins = "gpio117", "gpio118"; - function = "blsp_i2c4"; - }; - - blsp1_uart0_default: blsp1-uart0-default { - pins = "gpio30", "gpio31", "gpio32", "gpio33"; - function = "blsp_uart0"; - }; - - blsp1_uart1_default: blsp1-uart1-default { - pins = "gpio22", "gpio23"; - function = "blsp_uart1"; - }; - - blsp1_uart2_default: blsp1-uart2-default { - rx { - pins = "gpio18"; - function = "blsp_uart_rx_a2"; - }; - - tx { - pins = "gpio17"; - function = "blsp_uart_tx_a2"; - }; - }; - - blsp1_uart3_default: blsp1-uart3-default { - pins = "gpio82", "gpio83", "gpio84", "gpio85"; - function = "blsp_uart3"; - }; - - blsp2_i2c0_default: blsp2-i2c0-default { - pins = "gpio28", "gpio29"; - function = "blsp_i2c5"; - }; - - blsp1_spi0_default: blsp1-spi0-default { - pins = "gpio30", "gpio31", "gpio32", "gpio33"; - function = "blsp_spi0"; - }; - - blsp1_spi1_default: blsp1-spi1-default { - pins = "gpio22", "gpio23", "gpio24", "gpio25"; - function = "blsp_spi1"; - }; - - blsp1_spi2_default: blsp1-spi2-default { - pins = "gpio17", "gpio18", "gpio19", "gpio20"; - function = "blsp_spi2"; - }; - - blsp1_spi3_default: blsp1-spi3-default { - pins = "gpio82", "gpio83", "gpio84", "gpio85"; - function = "blsp_spi3"; - }; - - blsp1_spi4_default: blsp1-spi4-default { - pins = "gpio37", "gpio38", "gpio117", "gpio118"; - function = "blsp_spi4"; - }; - - blsp2_spi0_default: blsp2-spi0-default { - pins = "gpio26", "gpio27", "gpio28", "gpio29"; - function = "blsp_spi5"; - }; - - blsp2_uart0_default: blsp2-uart0-default { - pins = "gpio26", "gpio27", "gpio28", "gpio29"; - function = "blsp_uart5"; - }; - }; - - gcc: clock-controller@1800000 { - compatible = "qcom,gcc-qcs404"; - reg = <0x01800000 0x80000>; - #clock-cells = <1>; - #reset-cells = <1>; - - assigned-clocks = <&gcc GCC_APSS_AHB_CLK_SRC>; - assigned-clock-rates = <19200000>; - }; - - tcsr_mutex_regs: syscon@1905000 { - compatible = "syscon"; - reg = <0x01905000 0x20000>; - }; - - tcsr: syscon@1937000 { - compatible = "syscon"; - reg = <0x01937000 0x25000>; - }; - - spmi_bus: spmi@200f000 { - compatible = "qcom,spmi-pmic-arb"; - reg = <0x0200f000 0x001000>, - <0x02400000 0x800000>, - <0x02c00000 0x800000>, - <0x03800000 0x200000>, - <0x0200a000 0x002100>; - reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; - interrupt-names = "periph_irq"; - interrupts = ; - qcom,ee = <0>; - qcom,channel = <0>; - #address-cells = <2>; - #size-cells = <0>; - interrupt-controller; - #interrupt-cells = <4>; - }; - - remoteproc_wcss: remoteproc@7400000 { - compatible = "qcom,qcs404-wcss-pas"; - reg = <0x07400000 0x4040>; - - interrupts-extended = <&intc GIC_SPI 153 IRQ_TYPE_EDGE_RISING>, - <&wcss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&wcss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, - <&wcss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, - <&wcss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", - "handover", "stop-ack"; - - clocks = <&xo_board>; - clock-names = "xo"; - - memory-region = <&wlan_fw_mem>; - - qcom,smem-states = <&wcss_smp2p_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - glink-edge { - interrupts = ; - - qcom,remote-pid = <1>; - mboxes = <&apcs_glb 16>; - - label = "wcss"; - }; - }; - - pcie_phy: phy@7786000 { - compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy"; - reg = <0x07786000 0xb8>; - - clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; - resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>, - <&gcc 21>; - reset-names = "phy", "pipe"; - - clock-output-names = "pcie_0_pipe_clk"; - #phy-cells = <0>; - - status = "disabled"; - }; - - sdcc1: sdcc@7804000 { - compatible = "qcom,sdhci-msm-v5"; - reg = <0x07804000 0x1000>, <0x7805000 0x1000>; - reg-names = "hc_mem", "cmdq_mem"; - - interrupts = , - ; - interrupt-names = "hc_irq", "pwr_irq"; - - clocks = <&gcc GCC_SDCC1_APPS_CLK>, - <&gcc GCC_SDCC1_AHB_CLK>, - <&xo_board>; - clock-names = "core", "iface", "xo"; - - status = "disabled"; - }; - - blsp1_dma: dma@7884000 { - compatible = "qcom,bam-v1.7.0"; - reg = <0x07884000 0x25000>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "bam_clk"; - #dma-cells = <1>; - qcom,ee = <0>; - status = "okay"; - }; - - blsp1_uart0: serial@78af000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0x078af000 0x200>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_UART0_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - dmas = <&blsp1_dma 1>, <&blsp1_dma 0>; - dma-names = "rx", "tx"; - pinctrl-names = "default"; - pinctrl-0 = <&blsp1_uart0_default>; - status = "disabled"; - }; - - blsp1_uart1: serial@78b0000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0x078b0000 0x200>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - dmas = <&blsp1_dma 3>, <&blsp1_dma 2>; - dma-names = "rx", "tx"; - pinctrl-names = "default"; - pinctrl-0 = <&blsp1_uart1_default>; - status = "disabled"; - }; - - blsp1_uart2: serial@78b1000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0x078b1000 0x200>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - dmas = <&blsp1_dma 5>, <&blsp1_dma 4>; - dma-names = "rx", "tx"; - pinctrl-names = "default"; - pinctrl-0 = <&blsp1_uart2_default>; - status = "okay"; - }; - - ethernet: ethernet@7a80000 { - compatible = "qcom,qcs404-ethqos"; - reg = <0x07a80000 0x10000>, - <0x07a96000 0x100>; - reg-names = "stmmaceth", "rgmii"; - clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii"; - clocks = <&gcc GCC_ETH_AXI_CLK>, - <&gcc GCC_ETH_SLAVE_AHB_CLK>, - <&gcc GCC_ETH_PTP_CLK>, - <&gcc GCC_ETH_RGMII_CLK>; - interrupts = , - ; - interrupt-names = "macirq", "eth_lpi"; - - snps,tso; - rx-fifo-depth = <4096>; - tx-fifo-depth = <4096>; - - status = "disabled"; - }; - - wifi: wifi@a000000 { - compatible = "qcom,wcn3990-wifi"; - reg = <0xa000000 0x800000>; - reg-names = "membase"; - memory-region = <&wlan_msa_mem>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - ; - status = "disabled"; - }; - - blsp1_uart3: serial@78b2000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0x078b2000 0x200>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - dmas = <&blsp1_dma 7>, <&blsp1_dma 6>; - dma-names = "rx", "tx"; - pinctrl-names = "default"; - pinctrl-0 = <&blsp1_uart3_default>; - status = "disabled"; - }; - - blsp1_i2c0: i2c@78b5000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x078b5000 0x600>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP0_I2C_APPS_CLK>; - clock-names = "iface", "core"; - pinctrl-names = "default"; - pinctrl-0 = <&blsp1_i2c0_default>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - blsp1_spi0: spi@78b5000 { - compatible = "qcom,spi-qup-v2.2.1"; - reg = <0x078b5000 0x600>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP0_SPI_APPS_CLK>; - clock-names = "iface", "core"; - pinctrl-names = "default"; - pinctrl-0 = <&blsp1_spi0_default>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - blsp1_i2c1: i2c@78b6000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x078b6000 0x600>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>; - clock-names = "iface", "core"; - pinctrl-names = "default"; - pinctrl-0 = <&blsp1_i2c1_default>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - blsp1_spi1: spi@78b6000 { - compatible = "qcom,spi-qup-v2.2.1"; - reg = <0x078b6000 0x600>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>; - clock-names = "iface", "core"; - pinctrl-names = "default"; - pinctrl-0 = <&blsp1_spi1_default>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - blsp1_i2c2: i2c@78b7000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x078b7000 0x600>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; - clock-names = "iface", "core"; - pinctrl-names = "default"; - pinctrl-0 = <&blsp1_i2c2_default>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - blsp1_spi2: spi@78b7000 { - compatible = "qcom,spi-qup-v2.2.1"; - reg = <0x078b7000 0x600>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>; - clock-names = "iface", "core"; - pinctrl-names = "default"; - pinctrl-0 = <&blsp1_spi2_default>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - blsp1_i2c3: i2c@78b8000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x078b8000 0x600>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; - clock-names = "iface", "core"; - pinctrl-names = "default"; - pinctrl-0 = <&blsp1_i2c3_default>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - blsp1_spi3: spi@78b8000 { - compatible = "qcom,spi-qup-v2.2.1"; - reg = <0x078b8000 0x600>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>; - clock-names = "iface", "core"; - pinctrl-names = "default"; - pinctrl-0 = <&blsp1_spi3_default>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - blsp1_i2c4: i2c@78b9000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x078b9000 0x600>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>; - clock-names = "iface", "core"; - pinctrl-names = "default"; - pinctrl-0 = <&blsp1_i2c4_default>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - blsp1_spi4: spi@78b9000 { - compatible = "qcom,spi-qup-v2.2.1"; - reg = <0x078b9000 0x600>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>; - clock-names = "iface", "core"; - pinctrl-names = "default"; - pinctrl-0 = <&blsp1_spi4_default>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - blsp2_dma: dma@7ac4000 { - compatible = "qcom,bam-v1.7.0"; - reg = <0x07ac4000 0x17000>; - interrupts = ; - clocks = <&gcc GCC_BLSP2_AHB_CLK>; - clock-names = "bam_clk"; - #dma-cells = <1>; - qcom,ee = <0>; - status = "disabled"; - }; - - blsp2_uart0: serial@7aef000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0x07aef000 0x200>; - interrupts = ; - clocks = <&gcc GCC_BLSP2_UART0_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; - clock-names = "core", "iface"; - dmas = <&blsp2_dma 1>, <&blsp2_dma 0>; - dma-names = "rx", "tx"; - pinctrl-names = "default"; - pinctrl-0 = <&blsp2_uart0_default>; - status = "disabled"; - }; - - blsp2_i2c0: i2c@7af5000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x07af5000 0x600>; - interrupts = ; - clocks = <&gcc GCC_BLSP2_AHB_CLK>, - <&gcc GCC_BLSP2_QUP0_I2C_APPS_CLK>; - clock-names = "iface", "core"; - pinctrl-names = "default"; - pinctrl-0 = <&blsp2_i2c0_default>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - blsp2_spi0: spi@7af5000 { - compatible = "qcom,spi-qup-v2.2.1"; - reg = <0x07af5000 0x600>; - interrupts = ; - clocks = <&gcc GCC_BLSP2_AHB_CLK>, - <&gcc GCC_BLSP2_QUP0_SPI_APPS_CLK>; - clock-names = "iface", "core"; - pinctrl-names = "default"; - pinctrl-0 = <&blsp2_spi0_default>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - intc: interrupt-controller@b000000 { - compatible = "qcom,msm-qgic2"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0x0b000000 0x1000>, - <0x0b002000 0x1000>; - }; - - apcs_glb: mailbox@b011000 { - compatible = "qcom,qcs404-apcs-apps-global", "syscon"; - reg = <0x0b011000 0x1000>; - #mbox-cells = <1>; - clocks = <&apcs_hfpll>, <&gcc GCC_GPLL0_AO_OUT_MAIN>; - clock-names = "pll", "aux"; - #clock-cells = <0>; - }; - - apcs_hfpll: clock-controller@b016000 { - compatible = "qcom,hfpll"; - reg = <0x0b016000 0x30>; - #clock-cells = <0>; - clock-output-names = "apcs_hfpll"; - clocks = <&xo_board>; - clock-names = "xo"; - }; - - watchdog@b017000 { - compatible = "qcom,apss-wdt-qcs404", "qcom,kpss-wdt"; - reg = <0x0b017000 0x1000>; - clocks = <&sleep_clk>; - }; - - cpr: power-controller@b018000 { - compatible = "qcom,qcs404-cpr", "qcom,cpr"; - reg = <0x0b018000 0x1000>; - interrupts = <0 15 IRQ_TYPE_EDGE_RISING>; - clocks = <&xo_board>; - clock-names = "ref"; - vdd-apc-supply = <&pms405_s3>; - #power-domain-cells = <0>; - operating-points-v2 = <&cpr_opp_table>; - acc-syscon = <&tcsr>; - - nvmem-cells = <&cpr_efuse_quot_offset1>, - <&cpr_efuse_quot_offset2>, - <&cpr_efuse_quot_offset3>, - <&cpr_efuse_init_voltage1>, - <&cpr_efuse_init_voltage2>, - <&cpr_efuse_init_voltage3>, - <&cpr_efuse_quot1>, - <&cpr_efuse_quot2>, - <&cpr_efuse_quot3>, - <&cpr_efuse_ring1>, - <&cpr_efuse_ring2>, - <&cpr_efuse_ring3>, - <&cpr_efuse_revision>; - nvmem-cell-names = "cpr_quotient_offset1", - "cpr_quotient_offset2", - "cpr_quotient_offset3", - "cpr_init_voltage1", - "cpr_init_voltage2", - "cpr_init_voltage3", - "cpr_quotient1", - "cpr_quotient2", - "cpr_quotient3", - "cpr_ring_osc1", - "cpr_ring_osc2", - "cpr_ring_osc3", - "cpr_fuse_revision"; - }; - - timer@b120000 { - #address-cells = <1>; - #size-cells = <1>; - ranges; - compatible = "arm,armv7-timer-mem"; - reg = <0x0b120000 0x1000>; - clock-frequency = <19200000>; - - frame@b121000 { - frame-number = <0>; - interrupts = , - ; - reg = <0x0b121000 0x1000>, - <0x0b122000 0x1000>; - }; - - frame@b123000 { - frame-number = <1>; - interrupts = ; - reg = <0x0b123000 0x1000>; - status = "disabled"; - }; - - frame@b124000 { - frame-number = <2>; - interrupts = ; - reg = <0x0b124000 0x1000>; - status = "disabled"; - }; - - frame@b125000 { - frame-number = <3>; - interrupts = ; - reg = <0x0b125000 0x1000>; - status = "disabled"; - }; - - frame@b126000 { - frame-number = <4>; - interrupts = ; - reg = <0x0b126000 0x1000>; - status = "disabled"; - }; - - frame@b127000 { - frame-number = <5>; - interrupts = ; - reg = <0xb127000 0x1000>; - status = "disabled"; - }; - - frame@b128000 { - frame-number = <6>; - interrupts = ; - reg = <0x0b128000 0x1000>; - status = "disabled"; - }; - }; - - remoteproc_adsp: remoteproc@c700000 { - compatible = "qcom,qcs404-adsp-pas"; - reg = <0x0c700000 0x4040>; - - interrupts-extended = <&intc GIC_SPI 293 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", - "handover", "stop-ack"; - - clocks = <&xo_board>; - clock-names = "xo"; - - memory-region = <&adsp_fw_mem>; - - qcom,smem-states = <&adsp_smp2p_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - glink-edge { - interrupts = ; - - qcom,remote-pid = <2>; - mboxes = <&apcs_glb 8>; - - label = "adsp"; - }; - }; - - pcie: pci@10000000 { - compatible = "qcom,pcie-qcs404", "snps,dw-pcie"; - reg = <0x10000000 0xf1d>, - <0x10000f20 0xa8>, - <0x07780000 0x2000>, - <0x10001000 0x2000>; - reg-names = "dbi", "elbi", "parf", "config"; - device_type = "pci"; - linux,pci-domain = <0>; - bus-range = <0x00 0xff>; - num-lanes = <1>; - #address-cells = <3>; - #size-cells = <2>; - - ranges = <0x81000000 0 0 0x10003000 0 0x00010000>, /* I/O */ - <0x82000000 0 0x10013000 0x10013000 0 0x007ed000>; /* memory */ - - interrupts = ; - interrupt-names = "msi"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ - clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>, - <&gcc GCC_PCIE_0_AUX_CLK>, - <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, - <&gcc GCC_PCIE_0_SLV_AXI_CLK>; - clock-names = "iface", "aux", "master_bus", "slave_bus"; - - resets = <&gcc 18>, - <&gcc 17>, - <&gcc 15>, - <&gcc 19>, - <&gcc GCC_PCIE_0_BCR>, - <&gcc 16>; - reset-names = "axi_m", - "axi_s", - "axi_m_sticky", - "pipe_sticky", - "pwr", - "ahb"; - - phys = <&pcie_phy>; - phy-names = "pciephy"; - - status = "disabled"; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - smp2p-adsp { - compatible = "qcom,smp2p"; - qcom,smem = <443>, <429>; - interrupts = ; - mboxes = <&apcs_glb 10>; - qcom,local-pid = <0>; - qcom,remote-pid = <2>; - - adsp_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - adsp_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - smp2p-cdsp { - compatible = "qcom,smp2p"; - qcom,smem = <94>, <432>; - interrupts = ; - mboxes = <&apcs_glb 14>; - qcom,local-pid = <0>; - qcom,remote-pid = <5>; - - cdsp_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - cdsp_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - smp2p-wcss { - compatible = "qcom,smp2p"; - qcom,smem = <435>, <428>; - interrupts = ; - mboxes = <&apcs_glb 18>; - qcom,local-pid = <0>; - qcom,remote-pid = <1>; - - wcss_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - wcss_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - thermal-zones { - aoss-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 0>; - - trips { - aoss_alert0: trip-point0 { - temperature = <105000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - q6-hvx-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 1>; - - trips { - q6_hvx_alert0: trip-point0 { - temperature = <105000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - lpass-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 2>; - - trips { - lpass_alert0: trip-point0 { - temperature = <105000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - wlan-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 3>; - - trips { - wlan_alert0: trip-point0 { - temperature = <105000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - cluster-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 4>; - - trips { - cluster_alert0: trip-point0 { - temperature = <95000>; - hysteresis = <2000>; - type = "hot"; - }; - cluster_alert1: trip-point1 { - temperature = <105000>; - hysteresis = <2000>; - type = "passive"; - }; - cluster_crit: cluster_crit { - temperature = <120000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - cooling-maps { - map0 { - trip = <&cluster_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu0-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 5>; - - trips { - cpu0_alert0: trip-point0 { - temperature = <95000>; - hysteresis = <2000>; - type = "hot"; - }; - cpu0_alert1: trip-point1 { - temperature = <105000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu0_crit: cpu_crit { - temperature = <120000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - cooling-maps { - map0 { - trip = <&cpu0_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu1-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 6>; - - trips { - cpu1_alert0: trip-point0 { - temperature = <95000>; - hysteresis = <2000>; - type = "hot"; - }; - cpu1_alert1: trip-point1 { - temperature = <105000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu1_crit: cpu_crit { - temperature = <120000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - cooling-maps { - map0 { - trip = <&cpu1_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu2-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 7>; - - trips { - cpu2_alert0: trip-point0 { - temperature = <95000>; - hysteresis = <2000>; - type = "hot"; - }; - cpu2_alert1: trip-point1 { - temperature = <105000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu2_crit: cpu_crit { - temperature = <120000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - cooling-maps { - map0 { - trip = <&cpu2_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu3-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 8>; - - trips { - cpu3_alert0: trip-point0 { - temperature = <95000>; - hysteresis = <2000>; - type = "hot"; - }; - cpu3_alert1: trip-point1 { - temperature = <105000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu3_crit: cpu_crit { - temperature = <120000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - cooling-maps { - map0 { - trip = <&cpu3_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - gpu-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 9>; - - trips { - gpu_alert0: trip-point0 { - temperature = <95000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/qcom/sc7180-idp.dts b/sys/gnu/dts/arm64/qcom/sc7180-idp.dts deleted file mode 100644 index 388f50ad4fd..00000000000 --- a/sys/gnu/dts/arm64/qcom/sc7180-idp.dts +++ /dev/null @@ -1,430 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * SC7180 IDP board device tree source - * - * Copyright (c) 2019, The Linux Foundation. All rights reserved. - */ - -/dts-v1/; - -#include -#include "sc7180.dtsi" -#include "pm6150.dtsi" -#include "pm6150l.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. SC7180 IDP"; - compatible = "qcom,sc7180-idp", "qcom,sc7180"; - - aliases { - hsuart0 = &uart3; - serial0 = &uart8; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&apps_rsc { - pm6150-rpmh-regulators { - compatible = "qcom,pm6150-rpmh-regulators"; - qcom,pmic-id = "a"; - - vreg_s1a_1p1: smps1 { - regulator-min-microvolt = <1128000>; - regulator-max-microvolt = <1128000>; - }; - - vreg_s4a_1p0: smps4 { - regulator-min-microvolt = <824000>; - regulator-max-microvolt = <1120000>; - }; - - vreg_s5a_2p0: smps5 { - regulator-min-microvolt = <1744000>; - regulator-max-microvolt = <2040000>; - }; - - vreg_l1a_1p2: ldo1 { - regulator-min-microvolt = <1178000>; - regulator-max-microvolt = <1256000>; - regulator-initial-mode = ; - }; - - vreg_l2a_1p0: ldo2 { - regulator-min-microvolt = <944000>; - regulator-max-microvolt = <1056000>; - regulator-initial-mode = ; - }; - - vreg_l3a_1p0: ldo3 { - regulator-min-microvolt = <968000>; - regulator-max-microvolt = <1064000>; - regulator-initial-mode = ; - }; - - vreg_l4a_0p8: ldo4 { - regulator-min-microvolt = <824000>; - regulator-max-microvolt = <928000>; - regulator-initial-mode = ; - }; - - vreg_l5a_2p7: ldo5 { - regulator-min-microvolt = <2496000>; - regulator-max-microvolt = <3000000>; - regulator-initial-mode = ; - }; - - vreg_l6a_0p6: ldo6 { - regulator-min-microvolt = <568000>; - regulator-max-microvolt = <648000>; - regulator-initial-mode = ; - }; - - vreg_l9a_0p6: ldo9 { - regulator-min-microvolt = <488000>; - regulator-max-microvolt = <800000>; - regulator-initial-mode = ; - }; - - vreg_l10a_1p8: ldo10 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1832000>; - regulator-initial-mode = ; - }; - - vreg_l11a_1p8: ldo11 { - regulator-min-microvolt = <1696000>; - regulator-max-microvolt = <1904000>; - regulator-initial-mode = ; - }; - - vreg_l12a_1p8: ldo12 { - regulator-min-microvolt = <1696000>; - regulator-max-microvolt = <1952000>; - regulator-initial-mode = ; - }; - - vreg_l13a_1p8: ldo13 { - regulator-min-microvolt = <1696000>; - regulator-max-microvolt = <1904000>; - regulator-initial-mode = ; - }; - - vreg_l14a_1p8: ldo14 { - regulator-min-microvolt = <1728000>; - regulator-max-microvolt = <1832000>; - regulator-initial-mode = ; - }; - - vreg_l15a_1p8: ldo15 { - regulator-min-microvolt = <1696000>; - regulator-max-microvolt = <1904000>; - regulator-initial-mode = ; - }; - - vreg_l16a_2p7: ldo16 { - regulator-min-microvolt = <2496000>; - regulator-max-microvolt = <3304000>; - regulator-initial-mode = ; - }; - - vreg_l17a_3p0: ldo17 { - regulator-min-microvolt = <2920000>; - regulator-max-microvolt = <3232000>; - regulator-initial-mode = ; - }; - - vreg_l18a_2p8: ldo18 { - regulator-min-microvolt = <2496000>; - regulator-max-microvolt = <3304000>; - regulator-initial-mode = ; - }; - - vreg_l19a_2p9: ldo19 { - regulator-min-microvolt = <2696000>; - regulator-max-microvolt = <3304000>; - regulator-initial-mode = ; - }; - }; - - pm6150l-rpmh-regulators { - compatible = "qcom,pm6150l-rpmh-regulators"; - qcom,pmic-id = "c"; - - vreg_s8c_1p3: smps8 { - regulator-min-microvolt = <1120000>; - regulator-max-microvolt = <1408000>; - }; - - vreg_l1c_1p8: ldo1 { - regulator-min-microvolt = <1616000>; - regulator-max-microvolt = <1984000>; - regulator-initial-mode = ; - }; - - vreg_l2c_1p3: ldo2 { - regulator-min-microvolt = <1168000>; - regulator-max-microvolt = <1304000>; - regulator-initial-mode = ; - }; - - vreg_l3c_1p2: ldo3 { - regulator-min-microvolt = <1144000>; - regulator-max-microvolt = <1304000>; - regulator-initial-mode = ; - }; - - vreg_l4c_1p8: ldo4 { - regulator-min-microvolt = <1648000>; - regulator-max-microvolt = <3304000>; - regulator-initial-mode = ; - }; - - vreg_l5c_1p8: ldo5 { - regulator-min-microvolt = <1648000>; - regulator-max-microvolt = <3304000>; - regulator-initial-mode = ; - }; - - vreg_l6c_2p9: ldo6 { - regulator-min-microvolt = <2696000>; - regulator-max-microvolt = <3304000>; - regulator-initial-mode = ; - }; - - vreg_l7c_3p0: ldo7 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3312000>; - regulator-initial-mode = ; - }; - - vreg_l8c_1p8: ldo8 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1904000>; - regulator-initial-mode = ; - }; - - vreg_l9c_2p9: ldo9 { - regulator-min-microvolt = <2952000>; - regulator-max-microvolt = <3304000>; - regulator-initial-mode = ; - }; - - vreg_l10c_3p3: ldo10 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3400000>; - regulator-initial-mode = ; - }; - - vreg_l11c_3p3: ldo11 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3400000>; - regulator-initial-mode = ; - }; - - vreg_bob: bob { - regulator-min-microvolt = <3008000>; - regulator-max-microvolt = <3960000>; - regulator-initial-mode = ; - }; - }; -}; - -&qspi { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&qspi_clk &qspi_cs0 &qspi_data01>; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <25000000>; - spi-tx-bus-width = <2>; - spi-rx-bus-width = <2>; - }; -}; - -&qupv3_id_0 { - status = "okay"; -}; - -&qupv3_id_1 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&uart8 { - status = "okay"; -}; - -&usb_1 { - status = "okay"; -}; - -&usb_1_dwc3 { - dr_mode = "host"; -}; - -&usb_1_hsphy { - status = "okay"; - vdd-supply = <&vreg_l4a_0p8>; - vdda-pll-supply = <&vreg_l11a_1p8>; - vdda-phy-dpdm-supply = <&vreg_l17a_3p0>; - qcom,imp-res-offset-value = <8>; - qcom,hstx-trim-value = ; - qcom,preemphasis-level = ; - qcom,preemphasis-width = ; -}; - -&usb_1_qmpphy { - status = "okay"; - vdda-phy-supply = <&vreg_l3c_1p2>; - vdda-pll-supply = <&vreg_l4a_0p8>; -}; - -/* PINCTRL - additions to nodes defined in sc7180.dtsi */ - -&qspi_clk { - pinconf { - pins = "gpio63"; - bias-disable; - }; -}; - -&qspi_cs0 { - pinconf { - pins = "gpio68"; - bias-disable; - }; -}; - -&qspi_data01 { - pinconf { - pins = "gpio64", "gpio65"; - - /* High-Z when no transfers; nice to park the lines */ - bias-pull-up; - }; -}; - -&qup_i2c2_default { - pinconf { - pins = "gpio15", "gpio16"; - drive-strength = <2>; - - /* Has external pullup */ - bias-disable; - }; -}; - -&qup_i2c4_default { - pinconf { - pins = "gpio115", "gpio116"; - drive-strength = <2>; - - /* Has external pullup */ - bias-disable; - }; -}; - -&qup_i2c7_default { - pinconf { - pins = "gpio6", "gpio7"; - drive-strength = <2>; - - /* Has external pullup */ - bias-disable; - }; -}; - -&qup_i2c9_default { - pinconf { - pins = "gpio46", "gpio47"; - drive-strength = <2>; - - /* Has external pullup */ - bias-disable; - }; -}; - -&qup_uart3_default { - pinconf-cts { - /* - * Configure a pull-down on 38 (CTS) to match the pull of - * the Bluetooth module. - */ - pins = "gpio38"; - bias-pull-down; - output-high; - }; - - pinconf-rts { - /* We'll drive 39 (RTS), so no pull */ - pins = "gpio39"; - drive-strength = <2>; - bias-disable; - }; - - pinconf-tx { - /* We'll drive 40 (TX), so no pull */ - pins = "gpio40"; - drive-strength = <2>; - bias-disable; - output-high; - }; - - pinconf-rx { - /* - * Configure a pull-up on 41 (RX). This is needed to avoid - * garbage data when the TX pin of the Bluetooth module is - * in tri-state (module powered off or not driving the - * signal yet). - */ - pins = "gpio41"; - bias-pull-up; - }; -}; - -&qup_uart8_default { - pinconf-tx { - pins = "gpio44"; - drive-strength = <2>; - bias-disable; - }; - - pinconf-rx { - pins = "gpio45"; - drive-strength = <2>; - bias-pull-up; - }; -}; - -&qup_spi0_default { - pinconf { - pins = "gpio34", "gpio35", "gpio36", "gpio37"; - drive-strength = <2>; - bias-disable; - }; -}; - -&qup_spi6_default { - pinconf { - pins = "gpio59", "gpio60", "gpio61", "gpio62"; - drive-strength = <2>; - bias-disable; - }; -}; - -&qup_spi10_default { - pinconf { - pins = "gpio86", "gpio87", "gpio88", "gpio89"; - drive-strength = <2>; - bias-disable; - }; -}; - diff --git a/sys/gnu/dts/arm64/qcom/sc7180.dtsi b/sys/gnu/dts/arm64/qcom/sc7180.dtsi deleted file mode 100644 index 8011c5fe2a3..00000000000 --- a/sys/gnu/dts/arm64/qcom/sc7180.dtsi +++ /dev/null @@ -1,2187 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * SC7180 SoC device tree source - * - * Copyright (c) 2019, The Linux Foundation. All rights reserved. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/ { - interrupt-parent = <&intc>; - - #address-cells = <2>; - #size-cells = <2>; - - chosen { }; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - i2c6 = &i2c6; - i2c7 = &i2c7; - i2c8 = &i2c8; - i2c9 = &i2c9; - i2c10 = &i2c10; - i2c11 = &i2c11; - spi0 = &spi0; - spi1 = &spi1; - spi3 = &spi3; - spi5 = &spi5; - spi6 = &spi6; - spi8 = &spi8; - spi10 = &spi10; - spi11 = &spi11; - }; - - clocks { - xo_board: xo-board { - compatible = "fixed-clock"; - clock-frequency = <38400000>; - #clock-cells = <0>; - }; - - sleep_clk: sleep-clk { - compatible = "fixed-clock"; - clock-frequency = <32764>; - #clock-cells = <0>; - }; - }; - - reserved_memory: reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - aop_cmd_db_mem: memory@80820000 { - reg = <0x0 0x80820000 0x0 0x20000>; - compatible = "qcom,cmd-db"; - }; - - smem_mem: memory@80900000 { - reg = <0x0 0x80900000 0x0 0x200000>; - no-map; - }; - }; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - CPU0: cpu@0 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x0>; - enable-method = "psci"; - next-level-cache = <&L2_0>; - #cooling-cells = <2>; - qcom,freq-domain = <&cpufreq_hw 0>; - L2_0: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - L3_0: l3-cache { - compatible = "cache"; - }; - }; - }; - - CPU1: cpu@100 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x100>; - enable-method = "psci"; - next-level-cache = <&L2_100>; - #cooling-cells = <2>; - qcom,freq-domain = <&cpufreq_hw 0>; - L2_100: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU2: cpu@200 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x200>; - enable-method = "psci"; - next-level-cache = <&L2_200>; - #cooling-cells = <2>; - qcom,freq-domain = <&cpufreq_hw 0>; - L2_200: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU3: cpu@300 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x300>; - enable-method = "psci"; - next-level-cache = <&L2_300>; - #cooling-cells = <2>; - qcom,freq-domain = <&cpufreq_hw 0>; - L2_300: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU4: cpu@400 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x400>; - enable-method = "psci"; - next-level-cache = <&L2_400>; - #cooling-cells = <2>; - qcom,freq-domain = <&cpufreq_hw 0>; - L2_400: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU5: cpu@500 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x500>; - enable-method = "psci"; - next-level-cache = <&L2_500>; - #cooling-cells = <2>; - qcom,freq-domain = <&cpufreq_hw 0>; - L2_500: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU6: cpu@600 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x600>; - enable-method = "psci"; - next-level-cache = <&L2_600>; - #cooling-cells = <2>; - qcom,freq-domain = <&cpufreq_hw 1>; - L2_600: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU7: cpu@700 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x700>; - enable-method = "psci"; - next-level-cache = <&L2_700>; - #cooling-cells = <2>; - qcom,freq-domain = <&cpufreq_hw 1>; - L2_700: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - }; - - memory@80000000 { - device_type = "memory"; - /* We expect the bootloader to fill in the size */ - reg = <0 0x80000000 0 0>; - }; - - pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = ; - }; - - firmware { - scm { - compatible = "qcom,scm-sc7180", "qcom,scm"; - }; - }; - - tcsr_mutex: hwlock { - compatible = "qcom,tcsr-mutex"; - syscon = <&tcsr_mutex_regs 0 0x1000>; - #hwlock-cells = <1>; - }; - - smem { - compatible = "qcom,smem"; - memory-region = <&smem_mem>; - hwlocks = <&tcsr_mutex 3>; - }; - - smp2p-cdsp { - compatible = "qcom,smp2p"; - qcom,smem = <94>, <432>; - - interrupts = ; - - mboxes = <&apss_shared 6>; - - qcom,local-pid = <0>; - qcom,remote-pid = <5>; - - cdsp_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - cdsp_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - smp2p-lpass { - compatible = "qcom,smp2p"; - qcom,smem = <443>, <429>; - - interrupts = ; - - mboxes = <&apss_shared 10>; - - qcom,local-pid = <0>; - qcom,remote-pid = <2>; - - adsp_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - adsp_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - smp2p-mpss { - compatible = "qcom,smp2p"; - qcom,smem = <435>, <428>; - interrupts = ; - mboxes = <&apss_shared 14>; - qcom,local-pid = <0>; - qcom,remote-pid = <1>; - - modem_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - modem_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - soc: soc { - #address-cells = <2>; - #size-cells = <2>; - ranges = <0 0 0 0 0x10 0>; - dma-ranges = <0 0 0 0 0x10 0>; - compatible = "simple-bus"; - - gcc: clock-controller@100000 { - compatible = "qcom,gcc-sc7180"; - reg = <0 0x00100000 0 0x1f0000>; - clocks = <&rpmhcc RPMH_CXO_CLK>, - <&rpmhcc RPMH_CXO_CLK_A>; - clock-names = "bi_tcxo", "bi_tcxo_ao"; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - }; - - qfprom@784000 { - compatible = "qcom,qfprom"; - reg = <0 0x00784000 0 0x8ff>; - #address-cells = <1>; - #size-cells = <1>; - - qusb2p_hstx_trim: hstx-trim-primary@25b { - reg = <0x25b 0x1>; - bits = <1 3>; - }; - }; - - qupv3_id_0: geniqup@8c0000 { - compatible = "qcom,geni-se-qup"; - reg = <0 0x008c0000 0 0x6000>; - clock-names = "m-ahb", "s-ahb"; - clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, - <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - status = "disabled"; - - i2c0: i2c@880000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00880000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c0_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi0: spi@880000 { - compatible = "qcom,geni-spi"; - reg = <0 0x00880000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi0_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - uart0: serial@880000 { - compatible = "qcom,geni-uart"; - reg = <0 0x00880000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_uart0_default>; - interrupts = ; - status = "disabled"; - }; - - i2c1: i2c@884000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00884000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c1_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi1: spi@884000 { - compatible = "qcom,geni-spi"; - reg = <0 0x00884000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi1_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - uart1: serial@884000 { - compatible = "qcom,geni-uart"; - reg = <0 0x00884000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_uart1_default>; - interrupts = ; - status = "disabled"; - }; - - i2c2: i2c@888000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00888000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c2_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - uart2: serial@888000 { - compatible = "qcom,geni-uart"; - reg = <0 0x00888000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_uart2_default>; - interrupts = ; - status = "disabled"; - }; - - i2c3: i2c@88c000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x0088c000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c3_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi3: spi@88c000 { - compatible = "qcom,geni-spi"; - reg = <0 0x0088c000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi3_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - uart3: serial@88c000 { - compatible = "qcom,geni-uart"; - reg = <0 0x0088c000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_uart3_default>; - interrupts = ; - status = "disabled"; - }; - - i2c4: i2c@890000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00890000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c4_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - uart4: serial@890000 { - compatible = "qcom,geni-uart"; - reg = <0 0x00890000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_uart4_default>; - interrupts = ; - status = "disabled"; - }; - - i2c5: i2c@894000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00894000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c5_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi5: spi@894000 { - compatible = "qcom,geni-spi"; - reg = <0 0x00894000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi5_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - uart5: serial@894000 { - compatible = "qcom,geni-uart"; - reg = <0 0x00894000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_uart5_default>; - interrupts = ; - status = "disabled"; - }; - }; - - qupv3_id_1: geniqup@ac0000 { - compatible = "qcom,geni-se-qup"; - reg = <0 0x00ac0000 0 0x6000>; - clock-names = "m-ahb", "s-ahb"; - clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, - <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - status = "disabled"; - - i2c6: i2c@a80000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00a80000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c6_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi6: spi@a80000 { - compatible = "qcom,geni-spi"; - reg = <0 0x00a80000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi6_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - uart6: serial@a80000 { - compatible = "qcom,geni-uart"; - reg = <0 0x00a80000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_uart6_default>; - interrupts = ; - status = "disabled"; - }; - - i2c7: i2c@a84000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00a84000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c7_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - uart7: serial@a84000 { - compatible = "qcom,geni-uart"; - reg = <0 0x00a84000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_uart7_default>; - interrupts = ; - status = "disabled"; - }; - - i2c8: i2c@a88000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00a88000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c8_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi8: spi@a88000 { - compatible = "qcom,geni-spi"; - reg = <0 0x00a88000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi8_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - uart8: serial@a88000 { - compatible = "qcom,geni-debug-uart"; - reg = <0 0x00a88000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_uart8_default>; - interrupts = ; - status = "disabled"; - }; - - i2c9: i2c@a8c000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00a8c000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c9_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - uart9: serial@a8c000 { - compatible = "qcom,geni-uart"; - reg = <0 0x00a8c000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_uart9_default>; - interrupts = ; - status = "disabled"; - }; - - i2c10: i2c@a90000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00a90000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c10_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi10: spi@a90000 { - compatible = "qcom,geni-spi"; - reg = <0 0x00a90000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi10_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - uart10: serial@a90000 { - compatible = "qcom,geni-uart"; - reg = <0 0x00a90000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_uart10_default>; - interrupts = ; - status = "disabled"; - }; - - i2c11: i2c@a94000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00a94000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c11_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi11: spi@a94000 { - compatible = "qcom,geni-spi"; - reg = <0 0x00a94000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi11_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - uart11: serial@a94000 { - compatible = "qcom,geni-uart"; - reg = <0 0x00a94000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_uart11_default>; - interrupts = ; - status = "disabled"; - }; - }; - - tcsr_mutex_regs: syscon@1f40000 { - compatible = "syscon"; - reg = <0 0x01f40000 0 0x40000>; - }; - - tlmm: pinctrl@3500000 { - compatible = "qcom,sc7180-pinctrl"; - reg = <0 0x03500000 0 0x300000>, - <0 0x03900000 0 0x300000>, - <0 0x03d00000 0 0x300000>; - reg-names = "west", "north", "south"; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&tlmm 0 0 120>; - wakeup-parent = <&pdc>; - - qspi_clk: qspi-clk { - pinmux { - pins = "gpio63"; - function = "qspi_clk"; - }; - }; - - qspi_cs0: qspi-cs0 { - pinmux { - pins = "gpio68"; - function = "qspi_cs"; - }; - }; - - qspi_cs1: qspi-cs1 { - pinmux { - pins = "gpio72"; - function = "qspi_cs"; - }; - }; - - qspi_data01: qspi-data01 { - pinmux-data { - pins = "gpio64", "gpio65"; - function = "qspi_data"; - }; - }; - - qspi_data12: qspi-data12 { - pinmux-data { - pins = "gpio66", "gpio67"; - function = "qspi_data"; - }; - }; - - qup_i2c0_default: qup-i2c0-default { - pinmux { - pins = "gpio34", "gpio35"; - function = "qup00"; - }; - }; - - qup_i2c1_default: qup-i2c1-default { - pinmux { - pins = "gpio0", "gpio1"; - function = "qup01"; - }; - }; - - qup_i2c2_default: qup-i2c2-default { - pinmux { - pins = "gpio15", "gpio16"; - function = "qup02_i2c"; - }; - }; - - qup_i2c3_default: qup-i2c3-default { - pinmux { - pins = "gpio38", "gpio39"; - function = "qup03"; - }; - }; - - qup_i2c4_default: qup-i2c4-default { - pinmux { - pins = "gpio115", "gpio116"; - function = "qup04_i2c"; - }; - }; - - qup_i2c5_default: qup-i2c5-default { - pinmux { - pins = "gpio25", "gpio26"; - function = "qup05"; - }; - }; - - qup_i2c6_default: qup-i2c6-default { - pinmux { - pins = "gpio59", "gpio60"; - function = "qup10"; - }; - }; - - qup_i2c7_default: qup-i2c7-default { - pinmux { - pins = "gpio6", "gpio7"; - function = "qup11_i2c"; - }; - }; - - qup_i2c8_default: qup-i2c8-default { - pinmux { - pins = "gpio42", "gpio43"; - function = "qup12"; - }; - }; - - qup_i2c9_default: qup-i2c9-default { - pinmux { - pins = "gpio46", "gpio47"; - function = "qup13_i2c"; - }; - }; - - qup_i2c10_default: qup-i2c10-default { - pinmux { - pins = "gpio86", "gpio87"; - function = "qup14"; - }; - }; - - qup_i2c11_default: qup-i2c11-default { - pinmux { - pins = "gpio53", "gpio54"; - function = "qup15"; - }; - }; - - qup_spi0_default: qup-spi0-default { - pinmux { - pins = "gpio34", "gpio35", - "gpio36", "gpio37"; - function = "qup00"; - }; - }; - - qup_spi1_default: qup-spi1-default { - pinmux { - pins = "gpio0", "gpio1", - "gpio2", "gpio3"; - function = "qup01"; - }; - }; - - qup_spi3_default: qup-spi3-default { - pinmux { - pins = "gpio38", "gpio39", - "gpio40", "gpio41"; - function = "qup03"; - }; - }; - - qup_spi5_default: qup-spi5-default { - pinmux { - pins = "gpio25", "gpio26", - "gpio27", "gpio28"; - function = "qup05"; - }; - }; - - qup_spi6_default: qup-spi6-default { - pinmux { - pins = "gpio59", "gpio60", - "gpio61", "gpio62"; - function = "qup10"; - }; - }; - - qup_spi8_default: qup-spi8-default { - pinmux { - pins = "gpio42", "gpio43", - "gpio44", "gpio45"; - function = "qup12"; - }; - }; - - qup_spi10_default: qup-spi10-default { - pinmux { - pins = "gpio86", "gpio87", - "gpio88", "gpio89"; - function = "qup14"; - }; - }; - - qup_spi11_default: qup-spi11-default { - pinmux { - pins = "gpio53", "gpio54", - "gpio55", "gpio56"; - function = "qup15"; - }; - }; - - qup_uart0_default: qup-uart0-default { - pinmux { - pins = "gpio34", "gpio35", - "gpio36", "gpio37"; - function = "qup00"; - }; - }; - - qup_uart1_default: qup-uart1-default { - pinmux { - pins = "gpio0", "gpio1", - "gpio2", "gpio3"; - function = "qup01"; - }; - }; - - qup_uart2_default: qup-uart2-default { - pinmux { - pins = "gpio15", "gpio16"; - function = "qup02_uart"; - }; - }; - - qup_uart3_default: qup-uart3-default { - pinmux { - pins = "gpio38", "gpio39", - "gpio40", "gpio41"; - function = "qup03"; - }; - }; - - qup_uart4_default: qup-uart4-default { - pinmux { - pins = "gpio115", "gpio116"; - function = "qup04_uart"; - }; - }; - - qup_uart5_default: qup-uart5-default { - pinmux { - pins = "gpio25", "gpio26", - "gpio27", "gpio28"; - function = "qup05"; - }; - }; - - qup_uart6_default: qup-uart6-default { - pinmux { - pins = "gpio59", "gpio60", - "gpio61", "gpio62"; - function = "qup10"; - }; - }; - - qup_uart7_default: qup-uart7-default { - pinmux { - pins = "gpio6", "gpio7"; - function = "qup11_uart"; - }; - }; - - qup_uart8_default: qup-uart8-default { - pinmux { - pins = "gpio44", "gpio45"; - function = "qup12"; - }; - }; - - qup_uart9_default: qup-uart9-default { - pinmux { - pins = "gpio46", "gpio47"; - function = "qup13_uart"; - }; - }; - - qup_uart10_default: qup-uart10-default { - pinmux { - pins = "gpio86", "gpio87", - "gpio88", "gpio89"; - function = "qup14"; - }; - }; - - qup_uart11_default: qup-uart11-default { - pinmux { - pins = "gpio53", "gpio54", - "gpio55", "gpio56"; - function = "qup15"; - }; - }; - }; - - qspi: spi@88dc000 { - compatible = "qcom,qspi-v1"; - reg = <0 0x088dc000 0 0x600>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, - <&gcc GCC_QSPI_CORE_CLK>; - clock-names = "iface", "core"; - status = "disabled"; - }; - - usb_1_hsphy: phy@88e3000 { - compatible = "qcom,sc7180-qusb2-phy"; - reg = <0 0x088e3000 0 0x400>; - status = "disabled"; - #phy-cells = <0>; - clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, - <&rpmhcc RPMH_CXO_CLK>; - clock-names = "cfg_ahb", "ref"; - resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; - - nvmem-cells = <&qusb2p_hstx_trim>; - }; - - usb_1_qmpphy: phy-wrapper@88e9000 { - compatible = "qcom,sc7180-qmp-usb3-phy"; - reg = <0 0x088e9000 0 0x18c>, - <0 0x088e8000 0 0x38>; - reg-names = "reg-base", "dp_com"; - status = "disabled"; - #clock-cells = <1>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, - <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, - <&gcc GCC_USB3_PRIM_CLKREF_CLK>, - <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; - clock-names = "aux", "cfg_ahb", "ref", "com_aux"; - - resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, - <&gcc GCC_USB3_PHY_PRIM_BCR>; - reset-names = "phy", "common"; - - usb_1_ssphy: phy@88e9200 { - reg = <0 0x088e9200 0 0x128>, - <0 0x088e9400 0 0x200>, - <0 0x088e9c00 0 0x218>, - <0 0x088e9600 0 0x128>, - <0 0x088e9800 0 0x200>, - <0 0x088e9a00 0 0x18>; - #clock-cells = <0>; - #phy-cells = <0>; - clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; - clock-names = "pipe0"; - clock-output-names = "usb3_phy_pipe_clk_src"; - }; - }; - - system-cache-controller@9200000 { - compatible = "qcom,sc7180-llcc"; - reg = <0 0x09200000 0 0x200000>, <0 0x09600000 0 0x50000>; - reg-names = "llcc_base", "llcc_broadcast_base"; - interrupts = ; - }; - - usb_1: usb@a6f8800 { - compatible = "qcom,sc7180-dwc3", "qcom,dwc3"; - reg = <0 0x0a6f8800 0 0x400>; - status = "disabled"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - dma-ranges; - - clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, - <&gcc GCC_USB30_PRIM_MASTER_CLK>, - <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, - <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_PRIM_SLEEP_CLK>; - clock-names = "cfg_noc", "core", "iface", "mock_utmi", - "sleep"; - - assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_PRIM_MASTER_CLK>; - assigned-clock-rates = <19200000>, <150000000>; - - interrupts = , - , - , - ; - interrupt-names = "hs_phy_irq", "ss_phy_irq", - "dm_hs_phy_irq", "dp_hs_phy_irq"; - - power-domains = <&gcc USB30_PRIM_GDSC>; - - resets = <&gcc GCC_USB30_PRIM_BCR>; - - usb_1_dwc3: dwc3@a600000 { - compatible = "snps,dwc3"; - reg = <0 0x0a600000 0 0xe000>; - interrupts = ; - iommus = <&apps_smmu 0x540 0>; - snps,dis_u2_susphy_quirk; - snps,dis_enblslpm_quirk; - phys = <&usb_1_hsphy>, <&usb_1_ssphy>; - phy-names = "usb2-phy", "usb3-phy"; - }; - }; - - pdc: interrupt-controller@b220000 { - compatible = "qcom,sc7180-pdc", "qcom,pdc"; - reg = <0 0x0b220000 0 0x30000>; - qcom,pdc-ranges = <0 480 15>, <17 497 98>, - <119 634 4>, <124 639 1>; - #interrupt-cells = <2>; - interrupt-parent = <&intc>; - interrupt-controller; - }; - - pdc_reset: reset-controller@b2e0000 { - compatible = "qcom,sc7180-pdc-global", "qcom,sdm845-pdc-global"; - reg = <0 0x0b2e0000 0 0x20000>; - #reset-cells = <1>; - }; - - tsens0: thermal-sensor@c263000 { - compatible = "qcom,sc7180-tsens","qcom,tsens-v2"; - reg = <0 0x0c263000 0 0x1ff>, /* TM */ - <0 0x0c222000 0 0x1ff>; /* SROT */ - #qcom,sensors = <15>; - interrupts = , - ; - interrupt-names = "uplow","critical"; - #thermal-sensor-cells = <1>; - }; - - tsens1: thermal-sensor@c265000 { - compatible = "qcom,sc7180-tsens","qcom,tsens-v2"; - reg = <0 0x0c265000 0 0x1ff>, /* TM */ - <0 0x0c223000 0 0x1ff>; /* SROT */ - #qcom,sensors = <10>; - interrupts = , - ; - interrupt-names = "uplow","critical"; - #thermal-sensor-cells = <1>; - }; - - aoss_reset: reset-controller@c2a0000 { - compatible = "qcom,sc7180-aoss-cc", "qcom,sdm845-aoss-cc"; - reg = <0 0x0c2a0000 0 0x31000>; - #reset-cells = <1>; - }; - - aoss_qmp: qmp@c300000 { - compatible = "qcom,sc7180-aoss-qmp"; - reg = <0 0x0c300000 0 0x100000>; - interrupts = ; - mboxes = <&apss_shared 0>; - - #clock-cells = <0>; - #power-domain-cells = <1>; - }; - - spmi_bus: spmi@c440000 { - compatible = "qcom,spmi-pmic-arb"; - reg = <0 0x0c440000 0 0x1100>, - <0 0x0c600000 0 0x2000000>, - <0 0x0e600000 0 0x100000>, - <0 0x0e700000 0 0xa0000>, - <0 0x0c40a000 0 0x26000>; - reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; - interrupt-names = "periph_irq"; - interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; - qcom,ee = <0>; - qcom,channel = <0>; - #address-cells = <1>; - #size-cells = <1>; - interrupt-controller; - #interrupt-cells = <4>; - cell-index = <0>; - }; - - apps_smmu: iommu@15000000 { - compatible = "qcom,sc7180-smmu-500", "arm,mmu-500"; - reg = <0 0x15000000 0 0x100000>; - #iommu-cells = <2>; - #global-interrupts = <1>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - }; - - intc: interrupt-controller@17a00000 { - compatible = "arm,gic-v3"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0 0x17a00000 0 0x10000>, /* GICD */ - <0 0x17a60000 0 0x100000>; /* GICR * 8 */ - interrupts = ; - - msi-controller@17a40000 { - compatible = "arm,gic-v3-its"; - msi-controller; - #msi-cells = <1>; - reg = <0 0x17a40000 0 0x20000>; - status = "disabled"; - }; - }; - - apss_shared: mailbox@17c00000 { - compatible = "qcom,sc7180-apss-shared"; - reg = <0 0x17c00000 0 0x10000>; - #mbox-cells = <1>; - }; - - watchdog@17c10000 { - compatible = "qcom,apss-wdt-sc7180", "qcom,kpss-wdt"; - reg = <0 0x17c10000 0 0x1000>; - clocks = <&sleep_clk>; - }; - - timer@17c20000{ - #address-cells = <2>; - #size-cells = <2>; - ranges; - compatible = "arm,armv7-timer-mem"; - reg = <0 0x17c20000 0 0x1000>; - - frame@17c21000 { - frame-number = <0>; - interrupts = , - ; - reg = <0 0x17c21000 0 0x1000>, - <0 0x17c22000 0 0x1000>; - }; - - frame@17c23000 { - frame-number = <1>; - interrupts = ; - reg = <0 0x17c23000 0 0x1000>; - status = "disabled"; - }; - - frame@17c25000 { - frame-number = <2>; - interrupts = ; - reg = <0 0x17c25000 0 0x1000>; - status = "disabled"; - }; - - frame@17c27000 { - frame-number = <3>; - interrupts = ; - reg = <0 0x17c27000 0 0x1000>; - status = "disabled"; - }; - - frame@17c29000 { - frame-number = <4>; - interrupts = ; - reg = <0 0x17c29000 0 0x1000>; - status = "disabled"; - }; - - frame@17c2b000 { - frame-number = <5>; - interrupts = ; - reg = <0 0x17c2b000 0 0x1000>; - status = "disabled"; - }; - - frame@17c2d000 { - frame-number = <6>; - interrupts = ; - reg = <0 0x17c2d000 0 0x1000>; - status = "disabled"; - }; - }; - - apps_rsc: rsc@18200000 { - compatible = "qcom,rpmh-rsc"; - reg = <0 0x18200000 0 0x10000>, - <0 0x18210000 0 0x10000>, - <0 0x18220000 0 0x10000>; - reg-names = "drv-0", "drv-1", "drv-2"; - interrupts = , - , - ; - qcom,tcs-offset = <0xd00>; - qcom,drv-id = <2>; - qcom,tcs-config = , - , - , - ; - - rpmhcc: clock-controller { - compatible = "qcom,sc7180-rpmh-clk"; - clocks = <&xo_board>; - clock-names = "xo"; - #clock-cells = <1>; - }; - - rpmhpd: power-controller { - compatible = "qcom,sc7180-rpmhpd"; - #power-domain-cells = <1>; - operating-points-v2 = <&rpmhpd_opp_table>; - - rpmhpd_opp_table: opp-table { - compatible = "operating-points-v2"; - - rpmhpd_opp_ret: opp1 { - opp-level = ; - }; - - rpmhpd_opp_min_svs: opp2 { - opp-level = ; - }; - - rpmhpd_opp_low_svs: opp3 { - opp-level = ; - }; - - rpmhpd_opp_svs: opp4 { - opp-level = ; - }; - - rpmhpd_opp_svs_l1: opp5 { - opp-level = ; - }; - - rpmhpd_opp_svs_l2: opp6 { - opp-level = <224>; - }; - - rpmhpd_opp_nom: opp7 { - opp-level = ; - }; - - rpmhpd_opp_nom_l1: opp8 { - opp-level = ; - }; - - rpmhpd_opp_nom_l2: opp9 { - opp-level = ; - }; - - rpmhpd_opp_turbo: opp10 { - opp-level = ; - }; - - rpmhpd_opp_turbo_l1: opp11 { - opp-level = ; - }; - }; - }; - }; - - cpufreq_hw: cpufreq@18323000 { - compatible = "qcom,cpufreq-hw"; - reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>; - reg-names = "freq-domain0", "freq-domain1"; - - clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; - clock-names = "xo", "alternate"; - - #freq-domain-cells = <1>; - }; - }; - - thermal-zones { - cpu0-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 1>; - - trips { - cpu0_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu0_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu0_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu0_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu0_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu1-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 2>; - - trips { - cpu1_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu1_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu1_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu1_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu1_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu2-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 3>; - - trips { - cpu2_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu2_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu2_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu2_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu2_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu3-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 4>; - - trips { - cpu3_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu3_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu3_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu3_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu3_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu4-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 5>; - - trips { - cpu4_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu4_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu4_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu4_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu4_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu5-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 6>; - - trips { - cpu5_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu5_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu5_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu5_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu5_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu6-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 9>; - - trips { - cpu6_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu6_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu6_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu6_alert0>; - cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu6_alert1>; - cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu7-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 10>; - - trips { - cpu7_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu7_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu7_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu7_alert0>; - cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu7_alert1>; - cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu8-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 11>; - - trips { - cpu8_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu8_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu8_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu8_alert0>; - cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu8_alert1>; - cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu9-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 12>; - - trips { - cpu9_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu9_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu9_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu9_alert0>; - cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu9_alert1>; - cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - aoss0-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 0>; - - trips { - aoss0_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - cpuss0-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 7>; - - trips { - cpuss0_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - cpuss0_crit: cluster0_crit { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - cpuss1-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 8>; - - trips { - cpuss1_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - cpuss1_crit: cluster0_crit { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - gpuss0-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 13>; - - trips { - gpuss0_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - gpuss1-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 14>; - - trips { - gpuss1_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - aoss1-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 0>; - - trips { - aoss1_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - cwlan-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 1>; - - trips { - cwlan_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - audio-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 2>; - - trips { - audio_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - ddr-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 3>; - - trips { - ddr_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - q6-hvx-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 4>; - - trips { - q6_hvx_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - camera-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 5>; - - trips { - camera_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - mdm-core-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 6>; - - trips { - mdm_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - mdm-dsp-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 7>; - - trips { - mdm_dsp_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - npu-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 8>; - - trips { - npu_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - video-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 9>; - - trips { - video_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; -}; diff --git a/sys/gnu/dts/arm64/qcom/sdm845-cheza-r1.dts b/sys/gnu/dts/arm64/qcom/sdm845-cheza-r1.dts deleted file mode 100644 index bd7c25bb8d3..00000000000 --- a/sys/gnu/dts/arm64/qcom/sdm845-cheza-r1.dts +++ /dev/null @@ -1,238 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Cheza board device tree source - * - * Copyright 2018 Google LLC. - */ - -/dts-v1/; - -#include "sdm845-cheza.dtsi" - -/ { - model = "Google Cheza (rev1)"; - compatible = "google,cheza-rev1", "qcom,sdm845"; - - /* - * FIXED REGULATORS (not in sdm845-cheza.dtsi) - parents above children - */ - - /* - * NOTE: Technically pp3500_a is not the exact same signal as - * pp3500_a_vbob (there's a load switch between them and the EC can - * control pp3500_a via "en_pp3300_a"), but from the AP's point of - * view they are the same. - */ - pp3500_a: - pp3500_a_vbob: pp3500-a-vbob-regulator { - compatible = "regulator-fixed"; - regulator-name = "vreg_bob"; - - /* - * Comes on automatically when pp5000_ldo comes on, which - * comes on automatically when ppvar_sys comes on - */ - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3500000>; - regulator-max-microvolt = <3500000>; - - vin-supply = <&ppvar_sys>; - }; - - pp3300_dx_edp: pp3300-dx-edp-regulator { - /* Yes, it's really 3.5 despite the name of the signal */ - regulator-min-microvolt = <3500000>; - regulator-max-microvolt = <3500000>; - - vin-supply = <&pp3500_a>; - }; -}; - -/* FIXED REGULATOR OVERRIDES (modifications to sdm845-cheza.dtsi) */ - -/* - * L19 and L28 technically go to 3.3V, but most boards have old AOP firmware - * that limits them to 3.0, and trying to run at 3.3V with that old firmware - * prevents the system from booting. - */ -&src_pp3000_l19a { - regulator-min-microvolt = <3008000>; - regulator-max-microvolt = <3008000>; -}; - -&src_pp3300_l22a { - /delete-property/regulator-boot-on; - /delete-property/regulator-always-on; -}; - -&src_pp3300_l28a { - regulator-min-microvolt = <3008000>; - regulator-max-microvolt = <3008000>; -}; - -&src_vreg_bob { - regulator-min-microvolt = <3500000>; - regulator-max-microvolt = <3500000>; - vin-supply = <&pp3500_a_vbob>; -}; - -/* - * NON-REGULATOR OVERRIDES - * (modifications to sdm845-cheza.dtsi) - alphabetized by dtsi label - */ - -/* PINCTRL - board-specific pinctrl */ - -&tlmm { - gpio-line-names = "AP_SPI_FP_MISO", - "AP_SPI_FP_MOSI", - "AP_SPI_FP_CLK", - "AP_SPI_FP_CS_L", - "UART_AP_TX_DBG_RX", - "UART_DBG_TX_AP_RX", - "", - "FP_RST_L", - "FCAM_EN", - "", - "EDP_BRIJ_IRQ", - "EC_IN_RW_ODL", - "", - "RCAM_MCLK", - "FCAM_MCLK", - "", - "RCAM_EN", - "CCI0_SDA", - "CCI0_SCL", - "CCI1_SDA", - "CCI1_SCL", - "FCAM_RST_L", - "", - "PEN_RST_L", - "PEN_IRQ_L", - "", - "RCAM_VSYNC", - "ESIM_MISO", - "ESIM_MOSI", - "ESIM_CLK", - "ESIM_CS_L", - "AP_PEN_1V8_SDA", - "AP_PEN_1V8_SCL", - "AP_TS_I2C_SDA", - "AP_TS_I2C_SCL", - "RCAM_RST_L", - "", - "AP_EDP_BKLTEN", - "AP_BRD_ID1", - "BOOT_CONFIG_4", - "AMP_IRQ_L", - "EDP_BRIJ_I2C_SDA", - "EDP_BRIJ_I2C_SCL", - "EN_PP3300_DX_EDP", - "SD_CD_ODL", - "BT_UART_RTS", - "BT_UART_CTS", - "BT_UART_RXD", - "BT_UART_TXD", - "AMP_I2C_SDA", - "AMP_I2C_SCL", - "AP_BRD_ID3", - "", - "AP_EC_SPI_CLK", - "AP_EC_SPI_CS_L", - "AP_EC_SPI_MISO", - "AP_EC_SPI_MOSI", - "FORCED_USB_BOOT", - "AMP_BCLK", - "AMP_LRCLK", - "AMP_DOUT", - "AMP_DIN", - "AP_BRD_ID2", - "PEN_PDCT_L", - "HP_MCLK", - "HP_BCLK", - "HP_LRCLK", - "HP_DOUT", - "HP_DIN", - "", - "", - "", - "", - "BT_SLIMBUS_DATA", - "BT_SLIMBUS_CLK", - "AMP_RESET_L", - "", - "FCAM_VSYNC", - "", - "AP_SKU_ID1", - "EC_WOV_BCLK", - "EC_WOV_LRCLK", - "EC_WOV_DOUT", - "", - "", - "AP_H1_SPI_MISO", - "AP_H1_SPI_MOSI", - "AP_H1_SPI_CLK", - "AP_H1_SPI_CS_L", - "", - "AP_SPI_CS0_L", - "AP_SPI_MOSI", - "AP_SPI_MISO", - "", - "", - "AP_SPI_CLK", - "", - "RFFE6_CLK", - "RFFE6_DATA", - "BOOT_CONFIG_1", - "BOOT_CONFIG_2", - "BOOT_CONFIG_0", - "EDP_BRIJ_EN", - "", - "USB_HS_TX_EN", - "UIM2_DATA", - "UIM2_CLK", - "UIM2_RST", - "UIM2_PRESENT", - "UIM1_DATA", - "UIM1_CLK", - "UIM1_RST", - "", - "AP_SKU_ID2", - "SDM_GRFC_8", - "SDM_GRFC_9", - "AP_RST_REQ", - "HP_IRQ", - "TS_RESET_L", - "PEN_EJECT_ODL", - "HUB_RST_L", - "FP_TO_AP_IRQ", - "AP_EC_INT_L", - "", - "", - "TS_INT_L", - "AP_SUSPEND_L", - "SDM_GRFC_3", - "", - "H1_AP_INT_ODL", - "QLINK_REQ", - "QLINK_EN", - "SDM_GRFC_2", - "BOOT_CONFIG_3", - "WMSS_RESET_L", - "SDM_GRFC_0", - "SDM_GRFC_1", - "RFFE3_DATA", - "RFFE3_CLK", - "RFFE4_DATA", - "RFFE4_CLK", - "RFFE5_DATA", - "RFFE5_CLK", - "GNSS_EN", - "WCI2_LTE_COEX_RXD", - "WCI2_LTE_COEX_TXD", - "AP_RAM_ID1", - "AP_RAM_ID2", - "RFFE1_DATA", - "RFFE1_CLK"; -}; diff --git a/sys/gnu/dts/arm64/qcom/sdm845-cheza-r2.dts b/sys/gnu/dts/arm64/qcom/sdm845-cheza-r2.dts deleted file mode 100644 index 2b7230594ec..00000000000 --- a/sys/gnu/dts/arm64/qcom/sdm845-cheza-r2.dts +++ /dev/null @@ -1,238 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Cheza board device tree source - * - * Copyright 2018 Google LLC. - */ - -/dts-v1/; - -#include "sdm845-cheza.dtsi" - -/ { - model = "Google Cheza (rev2)"; - compatible = "google,cheza-rev2", "qcom,sdm845"; - - /* - * FIXED REGULATORS (not in sdm845-cheza.dtsi) - parents above children - */ - - /* - * NOTE: Technically pp3500_a is not the exact same signal as - * pp3500_a_vbob (there's a load switch between them and the EC can - * control pp3500_a via "en_pp3300_a"), but from the AP's point of - * view they are the same. - */ - pp3500_a: - pp3500_a_vbob: pp3500-a-vbob-regulator { - compatible = "regulator-fixed"; - regulator-name = "vreg_bob"; - - /* - * Comes on automatically when pp5000_ldo comes on, which - * comes on automatically when ppvar_sys comes on - */ - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3500000>; - regulator-max-microvolt = <3500000>; - - vin-supply = <&ppvar_sys>; - }; - - pp3300_dx_edp: pp3300-dx-edp-regulator { - /* Yes, it's really 3.5 despite the name of the signal */ - regulator-min-microvolt = <3500000>; - regulator-max-microvolt = <3500000>; - - vin-supply = <&pp3500_a>; - }; -}; - -/* FIXED REGULATOR OVERRIDES (modifications to sdm845-cheza.dtsi) */ - -/* - * L19 and L28 technically go to 3.3V, but most boards have old AOP firmware - * that limits them to 3.0, and trying to run at 3.3V with that old firmware - * prevents the system from booting. - */ -&src_pp3000_l19a { - regulator-min-microvolt = <3008000>; - regulator-max-microvolt = <3008000>; -}; - -&src_pp3300_l22a { - /delete-property/regulator-boot-on; - /delete-property/regulator-always-on; -}; - -&src_pp3300_l28a { - regulator-min-microvolt = <3008000>; - regulator-max-microvolt = <3008000>; -}; - -&src_vreg_bob { - regulator-min-microvolt = <3500000>; - regulator-max-microvolt = <3500000>; - vin-supply = <&pp3500_a_vbob>; -}; - -/* - * NON-REGULATOR OVERRIDES - * (modifications to sdm845-cheza.dtsi) - alphabetized by dtsi label - */ - -/* PINCTRL - board-specific pinctrl */ - -&tlmm { - gpio-line-names = "AP_SPI_FP_MISO", - "AP_SPI_FP_MOSI", - "AP_SPI_FP_CLK", - "AP_SPI_FP_CS_L", - "UART_AP_TX_DBG_RX", - "UART_DBG_TX_AP_RX", - "BRIJ_SUSPEND", - "FP_RST_L", - "FCAM_EN", - "", - "EDP_BRIJ_IRQ", - "EC_IN_RW_ODL", - "", - "RCAM_MCLK", - "FCAM_MCLK", - "", - "RCAM_EN", - "CCI0_SDA", - "CCI0_SCL", - "CCI1_SDA", - "CCI1_SCL", - "FCAM_RST_L", - "FPMCU_BOOT0", - "PEN_RST_L", - "PEN_IRQ_L", - "FPMCU_SEL_OD", - "RCAM_VSYNC", - "ESIM_MISO", - "ESIM_MOSI", - "ESIM_CLK", - "ESIM_CS_L", - "AP_PEN_1V8_SDA", - "AP_PEN_1V8_SCL", - "AP_TS_I2C_SDA", - "AP_TS_I2C_SCL", - "RCAM_RST_L", - "", - "AP_EDP_BKLTEN", - "AP_BRD_ID1", - "BOOT_CONFIG_4", - "AMP_IRQ_L", - "EDP_BRIJ_I2C_SDA", - "EDP_BRIJ_I2C_SCL", - "EN_PP3300_DX_EDP", - "SD_CD_ODL", - "BT_UART_RTS", - "BT_UART_CTS", - "BT_UART_RXD", - "BT_UART_TXD", - "AMP_I2C_SDA", - "AMP_I2C_SCL", - "AP_BRD_ID3", - "", - "AP_EC_SPI_CLK", - "AP_EC_SPI_CS_L", - "AP_EC_SPI_MISO", - "AP_EC_SPI_MOSI", - "FORCED_USB_BOOT", - "AMP_BCLK", - "AMP_LRCLK", - "AMP_DOUT", - "AMP_DIN", - "AP_BRD_ID2", - "PEN_PDCT_L", - "HP_MCLK", - "HP_BCLK", - "HP_LRCLK", - "HP_DOUT", - "HP_DIN", - "", - "", - "", - "", - "BT_SLIMBUS_DATA", - "BT_SLIMBUS_CLK", - "AMP_RESET_L", - "", - "FCAM_VSYNC", - "", - "AP_SKU_ID1", - "EC_WOV_BCLK", - "EC_WOV_LRCLK", - "EC_WOV_DOUT", - "", - "", - "AP_H1_SPI_MISO", - "AP_H1_SPI_MOSI", - "AP_H1_SPI_CLK", - "AP_H1_SPI_CS_L", - "", - "AP_SPI_CS0_L", - "AP_SPI_MOSI", - "AP_SPI_MISO", - "", - "", - "AP_SPI_CLK", - "", - "RFFE6_CLK", - "RFFE6_DATA", - "BOOT_CONFIG_1", - "BOOT_CONFIG_2", - "BOOT_CONFIG_0", - "EDP_BRIJ_EN", - "", - "USB_HS_TX_EN", - "UIM2_DATA", - "UIM2_CLK", - "UIM2_RST", - "UIM2_PRESENT", - "UIM1_DATA", - "UIM1_CLK", - "UIM1_RST", - "", - "AP_SKU_ID2", - "SDM_GRFC_8", - "SDM_GRFC_9", - "AP_RST_REQ", - "HP_IRQ", - "TS_RESET_L", - "PEN_EJECT_ODL", - "HUB_RST_L", - "FP_TO_AP_IRQ", - "AP_EC_INT_L", - "", - "", - "TS_INT_L", - "AP_SUSPEND_L", - "SDM_GRFC_3", - "", - "H1_AP_INT_ODL", - "QLINK_REQ", - "QLINK_EN", - "SDM_GRFC_2", - "BOOT_CONFIG_3", - "WMSS_RESET_L", - "SDM_GRFC_0", - "SDM_GRFC_1", - "RFFE3_DATA", - "RFFE3_CLK", - "RFFE4_DATA", - "RFFE4_CLK", - "RFFE5_DATA", - "RFFE5_CLK", - "GNSS_EN", - "WCI2_LTE_COEX_RXD", - "WCI2_LTE_COEX_TXD", - "AP_RAM_ID1", - "AP_RAM_ID2", - "RFFE1_DATA", - "RFFE1_CLK"; -}; diff --git a/sys/gnu/dts/arm64/qcom/sdm845-cheza-r3.dts b/sys/gnu/dts/arm64/qcom/sdm845-cheza-r3.dts deleted file mode 100644 index 1ba67be08f8..00000000000 --- a/sys/gnu/dts/arm64/qcom/sdm845-cheza-r3.dts +++ /dev/null @@ -1,174 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Cheza board device tree source - * - * Copyright 2018 Google LLC. - */ - -/dts-v1/; - -#include "sdm845-cheza.dtsi" - -/ { - model = "Google Cheza (rev3+)"; - compatible = "google,cheza", "qcom,sdm845"; -}; - -/* PINCTRL - board-specific pinctrl */ - -&tlmm { - gpio-line-names = "AP_SPI_FP_MISO", - "AP_SPI_FP_MOSI", - "AP_SPI_FP_CLK", - "AP_SPI_FP_CS_L", - "UART_AP_TX_DBG_RX", - "UART_DBG_TX_AP_RX", - "BRIJ_SUSPEND", - "FP_RST_L", - "FCAM_EN", - "", - "EDP_BRIJ_IRQ", - "EC_IN_RW_ODL", - "", - "RCAM_MCLK", - "FCAM_MCLK", - "", - "RCAM_EN", - "CCI0_SDA", - "CCI0_SCL", - "CCI1_SDA", - "CCI1_SCL", - "FCAM_RST_L", - "FPMCU_BOOT0", - "PEN_RST_L", - "PEN_IRQ_L", - "FPMCU_SEL_OD", - "RCAM_VSYNC", - "ESIM_MISO", - "ESIM_MOSI", - "ESIM_CLK", - "ESIM_CS_L", - "AP_PEN_1V8_SDA", - "AP_PEN_1V8_SCL", - "AP_TS_I2C_SDA", - "AP_TS_I2C_SCL", - "RCAM_RST_L", - "", - "AP_EDP_BKLTEN", - "AP_BRD_ID0", - "BOOT_CONFIG_4", - "AMP_IRQ_L", - "EDP_BRIJ_I2C_SDA", - "EDP_BRIJ_I2C_SCL", - "EN_PP3300_DX_EDP", - "SD_CD_ODL", - "BT_UART_RTS", - "BT_UART_CTS", - "BT_UART_RXD", - "BT_UART_TXD", - "AMP_I2C_SDA", - "AMP_I2C_SCL", - "AP_BRD_ID2", - "", - "AP_EC_SPI_CLK", - "AP_EC_SPI_CS_L", - "AP_EC_SPI_MISO", - "AP_EC_SPI_MOSI", - "FORCED_USB_BOOT", - "AMP_BCLK", - "AMP_LRCLK", - "AMP_DOUT", - "AMP_DIN", - "AP_BRD_ID1", - "PEN_PDCT_L", - "HP_MCLK", - "HP_BCLK", - "HP_LRCLK", - "HP_DOUT", - "HP_DIN", - "", - "", - "", - "", - "BT_SLIMBUS_DATA", - "BT_SLIMBUS_CLK", - "AMP_RESET_L", - "", - "FCAM_VSYNC", - "", - "AP_SKU_ID0", - "EC_WOV_BCLK", - "EC_WOV_LRCLK", - "EC_WOV_DOUT", - "", - "", - "AP_H1_SPI_MISO", - "AP_H1_SPI_MOSI", - "AP_H1_SPI_CLK", - "AP_H1_SPI_CS_L", - "", - "AP_SPI_CS0_L", - "AP_SPI_MOSI", - "AP_SPI_MISO", - "", - "", - "AP_SPI_CLK", - "", - "RFFE6_CLK", - "RFFE6_DATA", - "BOOT_CONFIG_1", - "BOOT_CONFIG_2", - "BOOT_CONFIG_0", - "EDP_BRIJ_EN", - "", - "USB_HS_TX_EN", - "UIM2_DATA", - "UIM2_CLK", - "UIM2_RST", - "UIM2_PRESENT", - "UIM1_DATA", - "UIM1_CLK", - "UIM1_RST", - "", - "AP_SKU_ID1", - "SDM_GRFC_8", - "SDM_GRFC_9", - "AP_RST_REQ", - "HP_IRQ", - "TS_RESET_L", - "PEN_EJECT_ODL", - "HUB_RST_L", - "FP_TO_AP_IRQ", - "AP_EC_INT_L", - "", - "", - "TS_INT_L", - "AP_SUSPEND_L", - "SDM_GRFC_3", - /* - * AP_FLASH_WP_L is crossystem ABI. Rev3 schematics - * call it BIOS_FLASH_WP_R_L. - */ - "AP_FLASH_WP_L", - "H1_AP_INT_ODL", - "QLINK_REQ", - "QLINK_EN", - "SDM_GRFC_2", - "BOOT_CONFIG_3", - "WMSS_RESET_L", - "SDM_GRFC_0", - "SDM_GRFC_1", - "RFFE3_DATA", - "RFFE3_CLK", - "RFFE4_DATA", - "RFFE4_CLK", - "RFFE5_DATA", - "RFFE5_CLK", - "GNSS_EN", - "WCI2_LTE_COEX_RXD", - "WCI2_LTE_COEX_TXD", - "AP_RAM_ID0", - "AP_RAM_ID1", - "RFFE1_DATA", - "RFFE1_CLK"; -}; diff --git a/sys/gnu/dts/arm64/qcom/sdm845-cheza.dtsi b/sys/gnu/dts/arm64/qcom/sdm845-cheza.dtsi deleted file mode 100644 index 7b53b3c7ffe..00000000000 --- a/sys/gnu/dts/arm64/qcom/sdm845-cheza.dtsi +++ /dev/null @@ -1,1294 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Cheza device tree source (common between revisions) - * - * Copyright 2018 Google LLC. - */ - -#include -#include -#include -#include "sdm845.dtsi" - -/* PMICs depend on spmi_bus label and so must come after SoC */ -#include "pm8005.dtsi" -#include "pm8998.dtsi" - -/ { - aliases { - bluetooth0 = &bluetooth; - hsuart0 = &uart6; - serial0 = &uart9; - wifi0 = &wifi; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&cros_ec_pwm 0>; - enable-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>; - power-supply = <&ppvar_sys>; - pinctrl-names = "default"; - pinctrl-0 = <&ap_edp_bklten>; - }; - - /* FIXED REGULATORS - parents above children */ - - /* This is the top level supply and variable voltage */ - ppvar_sys: ppvar-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "ppvar_sys"; - regulator-always-on; - regulator-boot-on; - }; - - /* This divides ppvar_sys by 2, so voltage is variable */ - src_vph_pwr: src-vph-pwr-regulator { - compatible = "regulator-fixed"; - regulator-name = "src_vph_pwr"; - - /* EC turns on with switchcap_on_l; always on for AP */ - regulator-always-on; - regulator-boot-on; - - vin-supply = <&ppvar_sys>; - }; - - pp5000_a: pp5000-a-regulator { - compatible = "regulator-fixed"; - regulator-name = "pp5000_a"; - - /* EC turns on with en_pp5000_a; always on for AP */ - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - vin-supply = <&ppvar_sys>; - }; - - src_vreg_bob: src-vreg-bob-regulator { - compatible = "regulator-fixed"; - regulator-name = "src_vreg_bob"; - - /* EC turns on with vbob_en; always on for AP */ - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3600000>; - regulator-max-microvolt = <3600000>; - - vin-supply = <&ppvar_sys>; - }; - - pp3300_dx_edp: pp3300-dx-edp-regulator { - compatible = "regulator-fixed"; - regulator-name = "pp3300_dx_edp"; - - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&tlmm 43 GPIO_ACTIVE_HIGH>; - enable-active-high; - pinctrl-names = "default"; - pinctrl-0 = <&en_pp3300_dx_edp>; - }; - - /* - * Apparently RPMh does not provide support for PM8998 S4 because it - * is always-on; model it as a fixed regulator. - */ - src_pp1800_s4a: pm8998-smps4 { - compatible = "regulator-fixed"; - regulator-name = "src_pp1800_s4a"; - - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-always-on; - regulator-boot-on; - - vin-supply = <&src_vph_pwr>; - }; - - /* BOARD-SPECIFIC TOP LEVEL NODES */ - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pen_eject_odl>; - - pen-insert { - label = "Pen Insert"; - /* Insert = low, eject = high */ - gpios = <&tlmm 119 GPIO_ACTIVE_LOW>; - linux,code = ; - linux,input-type = ; - wakeup-source; - }; - }; - - panel: panel { - compatible ="innolux,p120zdg-bf1"; - power-supply = <&pp3300_dx_edp>; - backlight = <&backlight>; - no-hpd; - - ports { - panel_in: port { - panel_in_edp: endpoint { - remote-endpoint = <&sn65dsi86_out>; - }; - }; - }; - }; -}; - -/* - * Reserved memory changes - * - * Putting this all together (out of order with the rest of the file) to keep - * all modifications to the memory map (from sdm845.dtsi) in one place. - */ - -/* - * Our mpss_region is 8MB bigger than the default one and that conflicts - * with venus_mem and cdsp_mem. - * - * For venus_mem we'll delete and re-create at a different address. - * - * cdsp_mem isn't used on cheza right now so we won't bother re-creating it; but - * that also means we need to delete cdsp_pas. - */ -/delete-node/ &venus_mem; -/delete-node/ &cdsp_mem; -/delete-node/ &cdsp_pas; -/delete-node/ &gpu_mem; - -/* Increase the size from 120 MB to 128 MB */ -&mpss_region { - reg = <0 0x8e000000 0 0x8000000>; -}; - -/* Increase the size from 2MB to 8MB */ -&rmtfs_mem { - reg = <0 0x88f00000 0 0x800000>; -}; - -/ { - reserved-memory { - venus_mem: memory@96000000 { - reg = <0 0x96000000 0 0x500000>; - no-map; - }; - }; -}; - -&qspi { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&qspi_clk &qspi_cs0 &qspi_data01>; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - - /* - * In theory chip supports up to 104 MHz and controller up - * to 80 MHz, but above 25 MHz wasn't reliable so we'll use - * that for now. b:117440651 - */ - spi-max-frequency = <25000000>; - spi-tx-bus-width = <2>; - spi-rx-bus-width = <2>; - }; -}; - - -&apps_rsc { - pm8998-rpmh-regulators { - compatible = "qcom,pm8998-rpmh-regulators"; - qcom,pmic-id = "a"; - - vdd-s1-supply = <&src_vph_pwr>; - vdd-s2-supply = <&src_vph_pwr>; - vdd-s3-supply = <&src_vph_pwr>; - vdd-s4-supply = <&src_vph_pwr>; - vdd-s5-supply = <&src_vph_pwr>; - vdd-s6-supply = <&src_vph_pwr>; - vdd-s7-supply = <&src_vph_pwr>; - vdd-s8-supply = <&src_vph_pwr>; - vdd-s9-supply = <&src_vph_pwr>; - vdd-s10-supply = <&src_vph_pwr>; - vdd-s11-supply = <&src_vph_pwr>; - vdd-s12-supply = <&src_vph_pwr>; - vdd-s13-supply = <&src_vph_pwr>; - vdd-l1-l27-supply = <&src_pp1025_s7a>; - vdd-l2-l8-l17-supply = <&src_pp1350_s3a>; - vdd-l3-l11-supply = <&src_pp1025_s7a>; - vdd-l4-l5-supply = <&src_pp1025_s7a>; - vdd-l6-supply = <&src_vph_pwr>; - vdd-l7-l12-l14-l15-supply = <&src_pp2040_s5a>; - vdd-l9-supply = <&src_pp2040_s5a>; - vdd-l10-l23-l25-supply = <&src_vreg_bob>; - vdd-l13-l19-l21-supply = <&src_vreg_bob>; - vdd-l16-l28-supply = <&src_vreg_bob>; - vdd-l18-l22-supply = <&src_vreg_bob>; - vdd-l20-l24-supply = <&src_vreg_bob>; - vdd-l26-supply = <&src_pp1350_s3a>; - vin-lvs-1-2-supply = <&src_pp1800_s4a>; - - src_pp1125_s2a: smps2 { - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - }; - - src_pp1350_s3a: smps3 { - regulator-min-microvolt = <1352000>; - regulator-max-microvolt = <1352000>; - }; - - src_pp2040_s5a: smps5 { - regulator-min-microvolt = <1904000>; - regulator-max-microvolt = <2040000>; - }; - - src_pp1025_s7a: smps7 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1028000>; - }; - - vdd_qusb_hs0: - vdda_hp_pcie_core: - vdda_mipi_csi0_0p9: - vdda_mipi_csi1_0p9: - vdda_mipi_csi2_0p9: - vdda_mipi_dsi0_pll: - vdda_mipi_dsi1_pll: - vdda_qlink_lv: - vdda_qlink_lv_ck: - vdda_qrefs_0p875: - vdda_pcie_core: - vdda_pll_cc_ebi01: - vdda_pll_cc_ebi23: - vdda_sp_sensor: - vdda_ufs1_core: - vdda_ufs2_core: - vdda_usb1_ss_core: - vdda_usb2_ss_core: - src_pp875_l1a: ldo1 { - regulator-min-microvolt = <880000>; - regulator-max-microvolt = <880000>; - regulator-initial-mode = ; - }; - - vddpx_10: - src_pp1200_l2a: ldo2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - - /* TODO: why??? */ - regulator-always-on; - }; - - pp1000_l3a_sdr845: ldo3 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-initial-mode = ; - }; - - vdd_wcss_cx: - vdd_wcss_mx: - vdda_wcss_pll: - src_pp800_l5a: ldo5 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <800000>; - regulator-initial-mode = ; - }; - - vddpx_13: - src_pp1800_l6a: ldo6 { - regulator-min-microvolt = <1856000>; - regulator-max-microvolt = <1856000>; - regulator-initial-mode = ; - }; - - pp1800_l7a_wcn3990: ldo7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - src_pp1200_l8a: ldo8 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1248000>; - regulator-initial-mode = ; - }; - - pp1800_dx_pen: - src_pp1800_l9a: ldo9 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - src_pp1800_l10a: ldo10 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - pp1000_l11a_sdr845: ldo11 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1048000>; - regulator-initial-mode = ; - }; - - vdd_qfprom: - vdd_qfprom_sp: - vdda_apc1_cs_1p8: - vdda_gfx_cs_1p8: - vdda_qrefs_1p8: - vdda_qusb_hs0_1p8: - vddpx_11: - src_pp1800_l12a: ldo12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vddpx_2: - src_pp2950_l13a: ldo13 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = ; - }; - - src_pp1800_l14a: ldo14 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - src_pp1800_l15a: ldo15 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - pp2700_l16a: ldo16 { - regulator-min-microvolt = <2704000>; - regulator-max-microvolt = <2704000>; - regulator-initial-mode = ; - }; - - src_pp1300_l17a: ldo17 { - regulator-min-microvolt = <1304000>; - regulator-max-microvolt = <1304000>; - regulator-initial-mode = ; - }; - - pp2700_l18a: ldo18 { - regulator-min-microvolt = <2704000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = ; - }; - - /* - * NOTE: this rail should have been called - * src_pp3300_l19a in the schematic - */ - src_pp3000_l19a: ldo19 { - regulator-min-microvolt = <3304000>; - regulator-max-microvolt = <3304000>; - - regulator-initial-mode = ; - }; - - src_pp2950_l20a: ldo20 { - regulator-min-microvolt = <2704000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = ; - }; - - src_pp2950_l21a: ldo21 { - regulator-min-microvolt = <2704000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = ; - }; - - pp3300_hub: - src_pp3300_l22a: ldo22 { - regulator-min-microvolt = <3304000>; - regulator-max-microvolt = <3304000>; - regulator-initial-mode = ; - /* - * HACK: Should add a usb hub node and driver - * to turn this on and off at suspend/resume time - */ - regulator-boot-on; - regulator-always-on; - }; - - pp3300_l23a_ch1_wcn3990: ldo23 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3312000>; - regulator-initial-mode = ; - }; - - vdda_qusb_hs0_3p1: - src_pp3075_l24a: ldo24 { - regulator-min-microvolt = <3088000>; - regulator-max-microvolt = <3088000>; - regulator-initial-mode = ; - }; - - pp3300_l25a_ch0_wcn3990: ldo25 { - regulator-min-microvolt = <3304000>; - regulator-max-microvolt = <3304000>; - regulator-initial-mode = ; - }; - - pp1200_hub: - vdda_hp_pcie_1p2: - vdda_hv_ebi0: - vdda_hv_ebi1: - vdda_hv_ebi2: - vdda_hv_ebi3: - vdda_mipi_csi_1p25: - vdda_mipi_dsi0_1p2: - vdda_mipi_dsi1_1p2: - vdda_pcie_1p2: - vdda_ufs1_1p2: - vdda_ufs2_1p2: - vdda_usb1_ss_1p2: - vdda_usb2_ss_1p2: - src_pp1200_l26a: ldo26 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - }; - - pp3300_dx_pen: - src_pp3300_l28a: ldo28 { - regulator-min-microvolt = <3304000>; - regulator-max-microvolt = <3304000>; - regulator-initial-mode = ; - }; - - src_pp1800_lvs1: lvs1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - src_pp1800_lvs2: lvs2 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - }; - - pm8005-rpmh-regulators { - compatible = "qcom,pm8005-rpmh-regulators"; - qcom,pmic-id = "c"; - - vdd-s1-supply = <&src_vph_pwr>; - vdd-s2-supply = <&src_vph_pwr>; - vdd-s3-supply = <&src_vph_pwr>; - vdd-s4-supply = <&src_vph_pwr>; - - src_pp600_s3c: smps3 { - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <600000>; - }; - }; -}; - -&dsi0 { - status = "okay"; - vdda-supply = <&vdda_mipi_dsi0_1p2>; - - ports { - port@1 { - endpoint { - remote-endpoint = <&sn65dsi86_in>; - data-lanes = <0 1 2 3>; - }; - }; - }; -}; - -&dsi0_phy { - status = "okay"; - vdds-supply = <&vdda_mipi_dsi0_pll>; -}; - -edp_brij_i2c: &i2c3 { - status = "okay"; - clock-frequency = <400000>; - - sn65dsi86_bridge: bridge@2d { - compatible = "ti,sn65dsi86"; - reg = <0x2d>; - pinctrl-names = "default"; - pinctrl-0 = <&edp_brij_en &edp_brij_irq>; - - interrupt-parent = <&tlmm>; - interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; - - enable-gpios = <&tlmm 102 GPIO_ACTIVE_HIGH>; - - vpll-supply = <&src_pp1800_s4a>; - vccio-supply = <&src_pp1800_s4a>; - vcca-supply = <&src_pp1200_l2a>; - vcc-supply = <&src_pp1200_l2a>; - - clocks = <&rpmhcc RPMH_LN_BB_CLK2>; - clock-names = "refclk"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - sn65dsi86_in: endpoint { - remote-endpoint = <&dsi0_out>; - }; - }; - - port@1 { - reg = <1>; - sn65dsi86_out: endpoint { - remote-endpoint = <&panel_in_edp>; - }; - }; - }; - }; -}; - -ap_pen_1v8: &i2c11 { - status = "okay"; - clock-frequency = <400000>; - - digitizer@9 { - compatible = "wacom,w9013", "hid-over-i2c"; - reg = <0x9>; - pinctrl-names = "default"; - pinctrl-0 = <&pen_irq_l>, <&pen_pdct_l>, <&pen_rst_l>; - - vdd-supply = <&pp3300_dx_pen>; - vddl-supply = <&pp1800_dx_pen>; - post-power-on-delay-ms = <100>; - - interrupt-parent = <&tlmm>; - interrupts = <24 IRQ_TYPE_LEVEL_LOW>; - - hid-descr-addr = <0x1>; - }; -}; - -amp_i2c: &i2c12 { - status = "okay"; - clock-frequency = <400000>; -}; - -ap_ts_i2c: &i2c14 { - status = "okay"; - clock-frequency = <400000>; - - touchscreen@10 { - compatible = "elan,ekth3500"; - reg = <0x10>; - pinctrl-names = "default"; - pinctrl-0 = <&ts_int_l &ts_reset_l>; - - interrupt-parent = <&tlmm>; - interrupts = <125 IRQ_TYPE_LEVEL_LOW>; - - vcc33-supply = <&src_pp3300_l28a>; - - reset-gpios = <&tlmm 118 GPIO_ACTIVE_LOW>; - }; -}; - -&lpasscc { - status = "okay"; -}; - -&mdss { - status = "okay"; -}; - -&mdss_mdp { - status = "okay"; -}; - -&qupv3_id_0 { - status = "okay"; -}; - -&qupv3_id_1 { - status = "okay"; -}; - -&sdhc_2 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&sdc2_clk &sdc2_cmd &sdc2_data &sd_cd_odl>; - - vmmc-supply = <&src_pp2950_l21a>; - vqmmc-supply = <&vddpx_2>; - - cd-gpios = <&tlmm 44 GPIO_ACTIVE_LOW>; -}; - -&spi0 { - status = "okay"; -}; - -&spi5 { - status = "okay"; - - tpm@0 { - compatible = "google,cr50"; - reg = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&h1_ap_int_odl>; - spi-max-frequency = <800000>; - interrupt-parent = <&tlmm>; - interrupts = <129 IRQ_TYPE_EDGE_RISING>; - }; -}; - -&spi10 { - status = "okay"; - - cros_ec: ec@0 { - compatible = "google,cros-ec-spi"; - reg = <0>; - interrupt-parent = <&tlmm>; - interrupts = <122 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&ec_ap_int_l>; - spi-max-frequency = <3000000>; - - cros_ec_pwm: ec-pwm { - compatible = "google,cros-ec-pwm"; - #pwm-cells = <1>; - }; - - i2c_tunnel: i2c-tunnel { - compatible = "google,cros-ec-i2c-tunnel"; - google,remote-bus = <0>; - #address-cells = <1>; - #size-cells = <0>; - }; - - pdupdate { - compatible = "google,cros-ec-pd-update"; - }; - }; -}; - -#include -#include - -&uart6 { - status = "okay"; - - bluetooth: wcn3990-bt { - compatible = "qcom,wcn3990-bt"; - vddio-supply = <&src_pp1800_s4a>; - vddxo-supply = <&pp1800_l7a_wcn3990>; - vddrf-supply = <&src_pp1300_l17a>; - vddch0-supply = <&pp3300_l25a_ch0_wcn3990>; - max-speed = <3200000>; - }; -}; - -&uart9 { - status = "okay"; -}; - -&ufs_mem_hc { - status = "okay"; - - reset-gpios = <&tlmm 150 GPIO_ACTIVE_LOW>; - - vcc-supply = <&src_pp2950_l20a>; - vcc-max-microamp = <600000>; -}; - -&ufs_mem_phy { - status = "okay"; - - vdda-phy-supply = <&vdda_ufs1_core>; - vdda-pll-supply = <&vdda_ufs1_1p2>; -}; - -&usb_1 { - status = "okay"; - - /* We'll use this as USB 2.0 only */ - qcom,select-utmi-as-pipe-clk; -}; - -&usb_1_dwc3 { - /* - * The hardware design intends this port to be hooked up in peripheral - * mode, so we'll hardcode it here. Some details: - * - SDM845 expects only a single Type C connector so it has only one - * native Type C port but cheza has two Type C connectors. - * - The only source of DP is the single native Type C port. - * - On cheza we want to be able to hook DP up to _either_ of the - * two Type C connectors and want to be able to achieve 4 lanes of DP. - * - When you configure a Type C port for 4 lanes of DP you lose USB3. - * - In order to make everything work, the native Type C port is always - * configured as 4-lanes DP so it's always available. - * - The extra USB3 port on SDM845 goes to a USB 3 hub which is then - * sent to the two Type C connectors. - * - The extra USB2 lines from the native Type C port are always - * setup as "peripheral" so that we can mux them over to one connector - * or the other if someone needs the connector configured as a gadget - * (but they only get USB2 speeds). - * - * All the hardware muxes would allow us to hook things up in different - * ways to some potential benefit for static configurations (you could - * achieve extra USB2 bandwidth by using two different ports for the - * two connectors or possibly even get USB3 peripheral mode), but in - * each case you end up forcing to disconnect/reconnect an in-use - * USB session in some cases depending on what you hotplug into the - * other connector. Thus hardcoding this as peripheral makes sense. - */ - dr_mode = "peripheral"; - - /* - * We always need the high speed pins as 4-lanes DP in case someone - * hotplugs a DP peripheral. Thus limit this port to a max of high - * speed. - */ - maximum-speed = "high-speed"; - - /* - * We don't need the usb3-phy since we run in highspeed mode always, so - * re-define these properties removing the superspeed USB PHY reference. - */ - phys = <&usb_1_hsphy>; - phy-names = "usb2-phy"; -}; - -&usb_1_hsphy { - status = "okay"; - - vdd-supply = <&vdda_usb1_ss_core>; - vdda-pll-supply = <&vdda_qusb_hs0_1p8>; - vdda-phy-dpdm-supply = <&vdda_qusb_hs0_3p1>; - - qcom,imp-res-offset-value = <8>; - qcom,hstx-trim-value = ; - qcom,preemphasis-level = ; - qcom,preemphasis-width = ; -}; - -&usb_2 { - status = "okay"; -}; - -&usb_2_dwc3 { - /* We have this hooked up to a hub and we always use in host mode */ - dr_mode = "host"; -}; - -&usb_2_hsphy { - status = "okay"; - - vdd-supply = <&vdda_usb2_ss_core>; - vdda-pll-supply = <&vdda_qusb_hs0_1p8>; - vdda-phy-dpdm-supply = <&vdda_qusb_hs0_3p1>; - - qcom,imp-res-offset-value = <8>; - qcom,hstx-trim-value = ; -}; - -&usb_2_qmpphy { - status = "okay"; - - vdda-phy-supply = <&vdda_usb2_ss_1p2>; - vdda-pll-supply = <&vdda_usb2_ss_core>; -}; - -&wifi { - status = "okay"; - - vdd-0.8-cx-mx-supply = <&src_pp800_l5a >; - vdd-1.8-xo-supply = <&pp1800_l7a_wcn3990>; - vdd-1.3-rfa-supply = <&src_pp1300_l17a>; - vdd-3.3-ch0-supply = <&pp3300_l25a_ch0_wcn3990>; -}; - -/* PINCTRL - additions to nodes defined in sdm845.dtsi */ - -&qspi_cs0 { - pinconf { - pins = "gpio90"; - bias-disable; - }; -}; - -&qspi_clk { - pinconf { - pins = "gpio95"; - bias-disable; - }; -}; - -&qspi_data01 { - pinconf { - pins = "gpio91", "gpio92"; - - /* High-Z when no transfers; nice to park the lines */ - bias-pull-up; - }; -}; - -&qup_i2c3_default { - pinconf { - pins = "gpio41", "gpio42"; - drive-strength = <2>; - - /* Has external pullup */ - bias-disable; - }; -}; - -&qup_i2c11_default { - pinconf { - pins = "gpio31", "gpio32"; - drive-strength = <2>; - - /* Has external pullup */ - bias-disable; - }; -}; - -&qup_i2c12_default { - pinconf { - pins = "gpio49", "gpio50"; - drive-strength = <2>; - - /* Has external pullup */ - bias-disable; - }; -}; - -&qup_i2c14_default { - pinconf { - pins = "gpio33", "gpio34"; - drive-strength = <2>; - - /* Has external pullup */ - bias-disable; - }; -}; - -&qup_spi0_default { - pinconf { - pins = "gpio0", "gpio1", "gpio2", "gpio3"; - drive-strength = <2>; - bias-disable; - }; -}; - -&qup_spi5_default { - pinconf { - pins = "gpio85", "gpio86", "gpio87", "gpio88"; - drive-strength = <2>; - bias-disable; - }; -}; - -&qup_spi10_default { - pinconf { - pins = "gpio53", "gpio54", "gpio55", "gpio56"; - drive-strength = <2>; - bias-disable; - }; -}; - -&qup_uart6_default { - /* Change pinmux to all 4 pins since CTS and RTS are connected */ - pinmux { - pins = "gpio45", "gpio46", - "gpio47", "gpio48"; - }; - - pinconf-cts { - /* - * Configure a pull-down on 45 (CTS) to match the pull of - * the Bluetooth module. - */ - pins = "gpio45"; - bias-pull-down; - }; - - pinconf-rts-tx { - /* We'll drive 46 (RTS) and 47 (TX), so no pull */ - pins = "gpio46", "gpio47"; - drive-strength = <2>; - bias-disable; - }; - - pinconf-rx { - /* - * Configure a pull-up on 48 (RX). This is needed to avoid - * garbage data when the TX pin of the Bluetooth module is - * in tri-state (module powered off or not driving the - * signal yet). - */ - pins = "gpio48"; - bias-pull-up; - }; -}; - -&qup_uart9_default { - pinconf-tx { - pins = "gpio4"; - drive-strength = <2>; - bias-disable; - }; - - pinconf-rx { - pins = "gpio5"; - drive-strength = <2>; - bias-pull-up; - }; -}; - -/* PINCTRL - board-specific pinctrl */ -&pm8005_gpio { - gpio-line-names = "", - "", - "SLB", - ""; -}; - -&pm8998_adc { - adc-chan@4d { - reg = ; - label = "sdm_temp"; - }; - - adc-chan@4e { - reg = ; - label = "quiet_temp"; - }; - - adc-chan@4f { - reg = ; - label = "lte_temp_1"; - }; - - adc-chan@50 { - reg = ; - label = "lte_temp_2"; - }; - - adc-chan@51 { - reg = ; - label = "charger_temp"; - }; -}; - -&pm8998_gpio { - gpio-line-names = "", - "", - "SW_CTRL", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "CFG_OPT1", - "WCSS_PWR_REQ", - "", - "CFG_OPT2", - "SLB"; -}; - -&tlmm { - /* - * pinctrl settings for pins that have no real owners. - */ - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&bios_flash_wp_r_l>, - <&ap_suspend_l_deassert>; - - pinctrl-1 = <&bios_flash_wp_r_l>, - <&ap_suspend_l_assert>; - - /* - * Hogs prevent usermode from changing the value. A GPIO can be both - * here and in the pinctrl section. - */ - ap-suspend-l-hog { - gpio-hog; - gpios = <126 GPIO_ACTIVE_LOW>; - output-low; - }; - - ap_edp_bklten: ap-edp-bklten { - pinmux { - pins = "gpio37"; - function = "gpio"; - }; - - pinconf { - pins = "gpio37"; - drive-strength = <2>; - bias-disable; - }; - }; - - bios_flash_wp_r_l: bios-flash-wp-r-l { - pinmux { - pins = "gpio128"; - function = "gpio"; - input-enable; - }; - - pinconf { - pins = "gpio128"; - bias-disable; - }; - }; - - ec_ap_int_l: ec-ap-int-l { - pinmux { - pins = "gpio122"; - function = "gpio"; - input-enable; - }; - - pinconf { - pins = "gpio122"; - bias-pull-up; - }; - }; - - edp_brij_en: edp-brij-en { - pinmux { - pins = "gpio102"; - function = "gpio"; - }; - - pinconf { - pins = "gpio102"; - drive-strength = <2>; - bias-disable; - }; - }; - - edp_brij_irq: edp-brij-irq { - pinmux { - pins = "gpio10"; - function = "gpio"; - }; - - pinconf { - pins = "gpio10"; - drive-strength = <2>; - bias-pull-down; - }; - }; - - en_pp3300_dx_edp: en-pp3300-dx-edp { - pinmux { - pins = "gpio43"; - function = "gpio"; - }; - - pinconf { - pins = "gpio43"; - drive-strength = <2>; - bias-disable; - }; - }; - - h1_ap_int_odl: h1-ap-int-odl { - pinmux { - pins = "gpio129"; - function = "gpio"; - input-enable; - }; - - pinconf { - pins = "gpio129"; - bias-pull-up; - }; - }; - - pen_eject_odl: pen-eject-odl { - pinmux { - pins = "gpio119"; - function = "gpio"; - bias-pull-up; - }; - }; - - pen_irq_l: pen-irq-l { - pinmux { - pins = "gpio24"; - function = "gpio"; - }; - - pinconf { - pins = "gpio24"; - - /* Has external pullup */ - bias-disable; - }; - }; - - pen_pdct_l: pen-pdct-l { - pinmux { - pins = "gpio63"; - function = "gpio"; - }; - - pinconf { - pins = "gpio63"; - - /* Has external pullup */ - bias-disable; - }; - }; - - pen_rst_l: pen-rst-l { - pinmux { - pins = "gpio23"; - function = "gpio"; - }; - - pinconf { - pins = "gpio23"; - bias-disable; - drive-strength = <2>; - - /* - * The pen driver doesn't currently support - * driving this reset line. By specifying - * output-high here we're relying on the fact - * that this pin has a default pulldown at boot - * (which makes sure the pen was in reset if it - * was powered) and then we set it high here to - * take it out of reset. Better would be if the - * pen driver could control this and we could - * remove "output-high" here. - */ - output-high; - }; - }; - - sdc2_clk: sdc2-clk { - pinconf { - pins = "sdc2_clk"; - bias-disable; - - /* - * It seems that mmc_test reports errors if drive - * strength is not 16. - */ - drive-strength = <16>; - }; - }; - - sdc2_cmd: sdc2-cmd { - pinconf { - pins = "sdc2_cmd"; - bias-pull-up; - drive-strength = <16>; - }; - }; - - sdc2_data: sdc2-data { - pinconf { - pins = "sdc2_data"; - bias-pull-up; - drive-strength = <16>; - }; - }; - - sd_cd_odl: sd-cd-odl { - pinmux { - pins = "gpio44"; - function = "gpio"; - }; - - pinconf { - pins = "gpio44"; - bias-pull-up; - }; - }; - - ts_int_l: ts-int-l { - pinmux { - pins = "gpio125"; - function = "gpio"; - }; - - pinconf { - pins = "gpio125"; - bias-pull-up; - }; - }; - - ts_reset_l: ts-reset-l { - pinmux { - pins = "gpio118"; - function = "gpio"; - }; - - pinconf { - pins = "gpio118"; - bias-disable; - drive-strength = <2>; - }; - }; - - ap_suspend_l_assert: ap_suspend_l_assert { - config { - pins = "gpio126"; - function = "gpio"; - bias-no-pull; - drive-strength = <2>; - output-low; - }; - }; - - ap_suspend_l_deassert: ap_suspend_l_deassert { - config { - pins = "gpio126"; - function = "gpio"; - bias-no-pull; - drive-strength = <2>; - output-high; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/qcom/sdm845-db845c.dts b/sys/gnu/dts/arm64/qcom/sdm845-db845c.dts deleted file mode 100644 index eb77aaa6a81..00000000000 --- a/sys/gnu/dts/arm64/qcom/sdm845-db845c.dts +++ /dev/null @@ -1,585 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2019, Linaro Ltd. - */ - -/dts-v1/; - -#include -#include -#include -#include "sdm845.dtsi" -#include "pm8998.dtsi" -#include "pmi8998.dtsi" - -/ { - model = "Thundercomm Dragonboard 845c"; - compatible = "thundercomm,db845c", "qcom,sdm845"; - - aliases { - serial0 = &uart9; - hsuart0 = &uart6; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - dc12v: dc12v-regulator { - compatible = "regulator-fixed"; - regulator-name = "DC12V"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-always-on; - }; - - gpio_keys { - compatible = "gpio-keys"; - autorepeat; - - pinctrl-names = "default"; - pinctrl-0 = <&vol_up_pin_a>; - - vol-up { - label = "Volume Up"; - linux,code = ; - gpios = <&pm8998_gpio 6 GPIO_ACTIVE_LOW>; - }; - }; - - leds { - compatible = "gpio-leds"; - - user4 { - label = "green:user4"; - gpios = <&pm8998_gpio 13 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "panic-indicator"; - default-state = "off"; - }; - - wlan { - label = "yellow:wlan"; - gpios = <&pm8998_gpio 9 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "phy0tx"; - default-state = "off"; - }; - - bt { - label = "blue:bt"; - gpios = <&pm8998_gpio 5 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "bluetooth-power"; - default-state = "off"; - }; - }; - - lt9611_1v8: lt9611-vdd18-regulator { - compatible = "regulator-fixed"; - regulator-name = "LT9611_1V8"; - - vin-supply = <&vdc_5v>; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - gpio = <&tlmm 89 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - lt9611_3v3: lt9611-3v3 { - compatible = "regulator-fixed"; - regulator-name = "LT9611_3V3"; - - vin-supply = <&vdc_3v3>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - // TODO: make it possible to drive same GPIO from two clients - // gpio = <&tlmm 89 GPIO_ACTIVE_HIGH>; - // enable-active-high; - }; - - pcie0_1p05v: pcie-0-1p05v-regulator { - compatible = "regulator-fixed"; - regulator-name = "PCIE0_1.05V"; - - vin-supply = <&vbat>; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - - // TODO: make it possible to drive same GPIO from two clients - // gpio = <&tlmm 90 GPIO_ACTIVE_HIGH>; - // enable-active-high; - }; - - pcie0_3p3v_dual: vldo-3v3-regulator { - compatible = "regulator-fixed"; - regulator-name = "VLDO_3V3"; - - vin-supply = <&vbat>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&tlmm 90 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-names = "default"; - pinctrl-0 = <&pcie0_pwren_state>; - }; - - v5p0_hdmiout: v5p0-hdmiout-regulator { - compatible = "regulator-fixed"; - regulator-name = "V5P0_HDMIOUT"; - - vin-supply = <&vdc_5v>; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <500000>; - - // TODO: make it possible to drive same GPIO from two clients - // gpio = <&tlmm 89 GPIO_ACTIVE_HIGH>; - // enable-active-high; - }; - - vbat: vbat-regulator { - compatible = "regulator-fixed"; - regulator-name = "VBAT"; - - vin-supply = <&dc12v>; - regulator-min-microvolt = <4200000>; - regulator-max-microvolt = <4200000>; - regulator-always-on; - }; - - vbat_som: vbat-som-regulator { - compatible = "regulator-fixed"; - regulator-name = "VBAT_SOM"; - - vin-supply = <&dc12v>; - regulator-min-microvolt = <4200000>; - regulator-max-microvolt = <4200000>; - regulator-always-on; - }; - - vdc_3v3: vdc-3v3-regulator { - compatible = "regulator-fixed"; - regulator-name = "VDC_3V3"; - vin-supply = <&dc12v>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdc_5v: vdc-5v-regulator { - compatible = "regulator-fixed"; - regulator-name = "VDC_5V"; - - vin-supply = <&dc12v>; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <500000>; - regulator-always-on; - }; - - vreg_s4a_1p8: vreg-s4a-1p8 { - compatible = "regulator-fixed"; - regulator-name = "vreg_s4a_1p8"; - - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vph_pwr: vph-pwr-regulator { - compatible = "regulator-fixed"; - regulator-name = "vph_pwr"; - - vin-supply = <&vbat_som>; - }; -}; - -&adsp_pas { - status = "okay"; - - firmware-name = "qcom/sdm845/adsp.mdt"; -}; - -&apps_rsc { - pm8998-rpmh-regulators { - compatible = "qcom,pm8998-rpmh-regulators"; - qcom,pmic-id = "a"; - vdd-s1-supply = <&vph_pwr>; - vdd-s2-supply = <&vph_pwr>; - vdd-s3-supply = <&vph_pwr>; - vdd-s4-supply = <&vph_pwr>; - vdd-s5-supply = <&vph_pwr>; - vdd-s6-supply = <&vph_pwr>; - vdd-s7-supply = <&vph_pwr>; - vdd-s8-supply = <&vph_pwr>; - vdd-s9-supply = <&vph_pwr>; - vdd-s10-supply = <&vph_pwr>; - vdd-s11-supply = <&vph_pwr>; - vdd-s12-supply = <&vph_pwr>; - vdd-s13-supply = <&vph_pwr>; - vdd-l1-l27-supply = <&vreg_s7a_1p025>; - vdd-l2-l8-l17-supply = <&vreg_s3a_1p35>; - vdd-l3-l11-supply = <&vreg_s7a_1p025>; - vdd-l4-l5-supply = <&vreg_s7a_1p025>; - vdd-l6-supply = <&vph_pwr>; - vdd-l7-l12-l14-l15-supply = <&vreg_s5a_2p04>; - vdd-l9-supply = <&vreg_bob>; - vdd-l10-l23-l25-supply = <&vreg_bob>; - vdd-l13-l19-l21-supply = <&vreg_bob>; - vdd-l16-l28-supply = <&vreg_bob>; - vdd-l18-l22-supply = <&vreg_bob>; - vdd-l20-l24-supply = <&vreg_bob>; - vdd-l26-supply = <&vreg_s3a_1p35>; - vin-lvs-1-2-supply = <&vreg_s4a_1p8>; - - vreg_s3a_1p35: smps3 { - regulator-min-microvolt = <1352000>; - regulator-max-microvolt = <1352000>; - }; - - vreg_s5a_2p04: smps5 { - regulator-min-microvolt = <1904000>; - regulator-max-microvolt = <2040000>; - }; - - vreg_s7a_1p025: smps7 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1028000>; - }; - - vreg_l1a_0p875: ldo1 { - regulator-min-microvolt = <880000>; - regulator-max-microvolt = <880000>; - regulator-initial-mode = ; - }; - - vreg_l5a_0p8: ldo5 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <800000>; - regulator-initial-mode = ; - }; - - vreg_l12a_1p8: ldo12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vreg_l7a_1p8: ldo7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vreg_l13a_2p95: ldo13 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = ; - }; - - vreg_l17a_1p3: ldo17 { - regulator-min-microvolt = <1304000>; - regulator-max-microvolt = <1304000>; - regulator-initial-mode = ; - }; - - vreg_l20a_2p95: ldo20 { - regulator-min-microvolt = <2960000>; - regulator-max-microvolt = <2968000>; - regulator-initial-mode = ; - }; - - vreg_l21a_2p95: ldo21 { - regulator-min-microvolt = <2960000>; - regulator-max-microvolt = <2968000>; - regulator-initial-mode = ; - }; - - vreg_l24a_3p075: ldo24 { - regulator-min-microvolt = <3088000>; - regulator-max-microvolt = <3088000>; - regulator-initial-mode = ; - }; - - vreg_l25a_3p3: ldo25 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3312000>; - regulator-initial-mode = ; - }; - - vreg_l26a_1p2: ldo26 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - }; - - vreg_lvs1a_1p8: lvs1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vreg_lvs2a_1p8: lvs2 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - }; - - pmi8998-rpmh-regulators { - compatible = "qcom,pmi8998-rpmh-regulators"; - qcom,pmic-id = "b"; - - vdd-bob-supply = <&vph_pwr>; - - vreg_bob: bob { - regulator-min-microvolt = <3312000>; - regulator-max-microvolt = <3600000>; - regulator-initial-mode = ; - regulator-allow-bypass; - }; - }; -}; - -&cdsp_pas { - status = "okay"; - firmware-name = "qcom/sdm845/cdsp.mdt"; -}; - -&gcc { - protected-clocks = , - , - ; -}; - -&gpu { - zap-shader { - memory-region = <&gpu_mem>; - firmware-name = "qcom/sdm845/a630_zap.mbn"; - }; -}; - -&mss_pil { - status = "okay"; - firmware-name = "qcom/sdm845/mba.mbn", "qcom/sdm845/modem.mbn"; -}; - -&pm8998_gpio { - vol_up_pin_a: vol-up-active { - pins = "gpio6"; - function = "normal"; - input-enable; - bias-pull-up; - qcom,drive-strength = ; - }; -}; - -&pm8998_pon { - resin { - compatible = "qcom,pm8941-resin"; - interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>; - debounce = <15625>; - bias-pull-up; - linux,code = ; - }; -}; - -&qupv3_id_0 { - status = "okay"; -}; - -&qupv3_id_1 { - status = "okay"; -}; - -&sdhc_2 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&sdc2_default_state &sdc2_card_det_n>; - - vmmc-supply = <&vreg_l21a_2p95>; - vqmmc-supply = <&vreg_l13a_2p95>; - - bus-width = <4>; - cd-gpios = <&tlmm 126 GPIO_ACTIVE_LOW>; -}; - -&tlmm { - pcie0_pwren_state: pcie0-pwren { - pins = "gpio90"; - function = "gpio"; - - drive-strength = <2>; - bias-disable; - }; - - sdc2_default_state: sdc2-default { - clk { - pins = "sdc2_clk"; - bias-disable; - - /* - * It seems that mmc_test reports errors if drive - * strength is not 16 on clk, cmd, and data pins. - */ - drive-strength = <16>; - }; - - cmd { - pins = "sdc2_cmd"; - bias-pull-up; - drive-strength = <10>; - }; - - data { - pins = "sdc2_data"; - bias-pull-up; - drive-strength = <10>; - }; - }; - - sdc2_card_det_n: sd-card-det-n { - pins = "gpio126"; - function = "gpio"; - bias-pull-up; - }; -}; - -&uart6 { - status = "okay"; - - bluetooth { - compatible = "qcom,wcn3990-bt"; - - vddio-supply = <&vreg_s4a_1p8>; - vddxo-supply = <&vreg_l7a_1p8>; - vddrf-supply = <&vreg_l17a_1p3>; - vddch0-supply = <&vreg_l25a_3p3>; - max-speed = <3200000>; - }; -}; - -&uart9 { - status = "okay"; -}; - -&usb_1 { - status = "okay"; -}; - -&usb_1_dwc3 { - dr_mode = "peripheral"; -}; - -&usb_1_hsphy { - status = "okay"; - - vdd-supply = <&vreg_l1a_0p875>; - vdda-pll-supply = <&vreg_l12a_1p8>; - vdda-phy-dpdm-supply = <&vreg_l24a_3p075>; - - qcom,imp-res-offset-value = <8>; - qcom,hstx-trim-value = ; - qcom,preemphasis-level = ; - qcom,preemphasis-width = ; -}; - -&usb_1_qmpphy { - status = "okay"; - - vdda-phy-supply = <&vreg_l26a_1p2>; - vdda-pll-supply = <&vreg_l1a_0p875>; -}; - -&usb_2 { - status = "okay"; -}; - -&usb_2_dwc3 { - dr_mode = "host"; -}; - -&usb_2_hsphy { - status = "okay"; - - vdd-supply = <&vreg_l1a_0p875>; - vdda-pll-supply = <&vreg_l12a_1p8>; - vdda-phy-dpdm-supply = <&vreg_l24a_3p075>; - - qcom,imp-res-offset-value = <8>; - qcom,hstx-trim-value = ; -}; - -&usb_2_qmpphy { - status = "okay"; - - vdda-phy-supply = <&vreg_l26a_1p2>; - vdda-pll-supply = <&vreg_l1a_0p875>; -}; - -&ufs_mem_hc { - status = "okay"; - - reset-gpios = <&tlmm 150 GPIO_ACTIVE_LOW>; - - vcc-supply = <&vreg_l20a_2p95>; - vcc-max-microamp = <800000>; -}; - -&ufs_mem_phy { - status = "okay"; - - vdda-phy-supply = <&vreg_l1a_0p875>; - vdda-pll-supply = <&vreg_l26a_1p2>; -}; - -&wifi { - status = "okay"; - - vdd-0.8-cx-mx-supply = <&vreg_l5a_0p8>; - vdd-1.8-xo-supply = <&vreg_l7a_1p8>; - vdd-1.3-rfa-supply = <&vreg_l17a_1p3>; - vdd-3.3-ch0-supply = <&vreg_l25a_3p3>; - - qcom,snoc-host-cap-8bit-quirk; -}; - -/* PINCTRL - additions to nodes defined in sdm845.dtsi */ - -&qup_uart6_default { - pinmux { - pins = "gpio45", "gpio46", "gpio47", "gpio48"; - function = "qup6"; - }; - - cts { - pins = "gpio45"; - bias-disable; - }; - - rts-tx { - pins = "gpio46", "gpio47"; - drive-strength = <2>; - bias-disable; - }; - - rx { - pins = "gpio48"; - bias-pull-up; - }; -}; - -&qup_uart9_default { - pinconf-tx { - pins = "gpio4"; - drive-strength = <2>; - bias-disable; - }; - - pinconf-rx { - pins = "gpio5"; - drive-strength = <2>; - bias-pull-up; - }; -}; diff --git a/sys/gnu/dts/arm64/qcom/sdm845-mtp.dts b/sys/gnu/dts/arm64/qcom/sdm845-mtp.dts deleted file mode 100644 index 09ad37b0dd7..00000000000 --- a/sys/gnu/dts/arm64/qcom/sdm845-mtp.dts +++ /dev/null @@ -1,547 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * SDM845 MTP board device tree source - * - * Copyright (c) 2018, The Linux Foundation. All rights reserved. - */ - -/dts-v1/; - -#include -#include -#include "sdm845.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. SDM845 MTP"; - compatible = "qcom,sdm845-mtp"; - - aliases { - serial0 = &uart9; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - vph_pwr: vph-pwr-regulator { - compatible = "regulator-fixed"; - regulator-name = "vph_pwr"; - regulator-min-microvolt = <3700000>; - regulator-max-microvolt = <3700000>; - }; - - /* - * Apparently RPMh does not provide support for PM8998 S4 because it - * is always-on; model it as a fixed regulator. - */ - vreg_s4a_1p8: pm8998-smps4 { - compatible = "regulator-fixed"; - regulator-name = "vreg_s4a_1p8"; - - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-always-on; - regulator-boot-on; - - vin-supply = <&vph_pwr>; - }; -}; - -&adsp_pas { - status = "okay"; -}; - -&apps_rsc { - pm8998-rpmh-regulators { - compatible = "qcom,pm8998-rpmh-regulators"; - qcom,pmic-id = "a"; - - vdd-s1-supply = <&vph_pwr>; - vdd-s2-supply = <&vph_pwr>; - vdd-s3-supply = <&vph_pwr>; - vdd-s4-supply = <&vph_pwr>; - vdd-s5-supply = <&vph_pwr>; - vdd-s6-supply = <&vph_pwr>; - vdd-s7-supply = <&vph_pwr>; - vdd-s8-supply = <&vph_pwr>; - vdd-s9-supply = <&vph_pwr>; - vdd-s10-supply = <&vph_pwr>; - vdd-s11-supply = <&vph_pwr>; - vdd-s12-supply = <&vph_pwr>; - vdd-s13-supply = <&vph_pwr>; - vdd-l1-l27-supply = <&vreg_s7a_1p025>; - vdd-l2-l8-l17-supply = <&vreg_s3a_1p35>; - vdd-l3-l11-supply = <&vreg_s7a_1p025>; - vdd-l4-l5-supply = <&vreg_s7a_1p025>; - vdd-l6-supply = <&vph_pwr>; - vdd-l7-l12-l14-l15-supply = <&vreg_s5a_2p04>; - vdd-l9-supply = <&vreg_bob>; - vdd-l10-l23-l25-supply = <&vreg_bob>; - vdd-l13-l19-l21-supply = <&vreg_bob>; - vdd-l16-l28-supply = <&vreg_bob>; - vdd-l18-l22-supply = <&vreg_bob>; - vdd-l20-l24-supply = <&vreg_bob>; - vdd-l26-supply = <&vreg_s3a_1p35>; - vin-lvs-1-2-supply = <&vreg_s4a_1p8>; - - vreg_s2a_1p125: smps2 { - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - }; - - vreg_s3a_1p35: smps3 { - regulator-min-microvolt = <1352000>; - regulator-max-microvolt = <1352000>; - }; - - vreg_s5a_2p04: smps5 { - regulator-min-microvolt = <1904000>; - regulator-max-microvolt = <2040000>; - }; - - vreg_s7a_1p025: smps7 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1028000>; - }; - - vdd_qusb_hs0: - vdda_hp_pcie_core: - vdda_mipi_csi0_0p9: - vdda_mipi_csi1_0p9: - vdda_mipi_csi2_0p9: - vdda_mipi_dsi0_pll: - vdda_mipi_dsi1_pll: - vdda_qlink_lv: - vdda_qlink_lv_ck: - vdda_qrefs_0p875: - vdda_pcie_core: - vdda_pll_cc_ebi01: - vdda_pll_cc_ebi23: - vdda_sp_sensor: - vdda_ufs1_core: - vdda_ufs2_core: - vdda_usb1_ss_core: - vdda_usb2_ss_core: - vreg_l1a_0p875: ldo1 { - regulator-min-microvolt = <880000>; - regulator-max-microvolt = <880000>; - regulator-initial-mode = ; - }; - - vddpx_10: - vreg_l2a_1p2: ldo2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - regulator-always-on; - }; - - vreg_l3a_1p0: ldo3 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-initial-mode = ; - }; - - vdd_wcss_cx: - vdd_wcss_mx: - vdda_wcss_pll: - vreg_l5a_0p8: ldo5 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <800000>; - regulator-initial-mode = ; - }; - - vddpx_13: - vreg_l6a_1p8: ldo6 { - regulator-min-microvolt = <1856000>; - regulator-max-microvolt = <1856000>; - regulator-initial-mode = ; - }; - - vreg_l7a_1p8: ldo7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vreg_l8a_1p2: ldo8 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1248000>; - regulator-initial-mode = ; - }; - - vreg_l9a_1p8: ldo9 { - regulator-min-microvolt = <1704000>; - regulator-max-microvolt = <2928000>; - regulator-initial-mode = ; - }; - - vreg_l10a_1p8: ldo10 { - regulator-min-microvolt = <1704000>; - regulator-max-microvolt = <2928000>; - regulator-initial-mode = ; - }; - - vreg_l11a_1p0: ldo11 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1048000>; - regulator-initial-mode = ; - }; - - vdd_qfprom: - vdd_qfprom_sp: - vdda_apc1_cs_1p8: - vdda_gfx_cs_1p8: - vdda_qrefs_1p8: - vdda_qusb_hs0_1p8: - vddpx_11: - vreg_l12a_1p8: ldo12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vddpx_2: - vreg_l13a_2p95: ldo13 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = ; - }; - - vreg_l14a_1p88: ldo14 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vreg_l15a_1p8: ldo15 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vreg_l16a_2p7: ldo16 { - regulator-min-microvolt = <2704000>; - regulator-max-microvolt = <2704000>; - regulator-initial-mode = ; - }; - - vreg_l17a_1p3: ldo17 { - regulator-min-microvolt = <1304000>; - regulator-max-microvolt = <1304000>; - regulator-initial-mode = ; - }; - - vreg_l18a_2p7: ldo18 { - regulator-min-microvolt = <2704000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = ; - }; - - vreg_l19a_3p0: ldo19 { - regulator-min-microvolt = <2856000>; - regulator-max-microvolt = <3104000>; - regulator-initial-mode = ; - }; - - vreg_l20a_2p95: ldo20 { - regulator-min-microvolt = <2704000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = ; - }; - - vreg_l21a_2p95: ldo21 { - regulator-min-microvolt = <2704000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = ; - }; - - vreg_l22a_2p85: ldo22 { - regulator-min-microvolt = <2864000>; - regulator-max-microvolt = <3312000>; - regulator-initial-mode = ; - }; - - vreg_l23a_3p3: ldo23 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3312000>; - regulator-initial-mode = ; - }; - - vdda_qusb_hs0_3p1: - vreg_l24a_3p075: ldo24 { - regulator-min-microvolt = <3088000>; - regulator-max-microvolt = <3088000>; - regulator-initial-mode = ; - }; - - vreg_l25a_3p3: ldo25 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3312000>; - regulator-initial-mode = ; - }; - - vdda_hp_pcie_1p2: - vdda_hv_ebi0: - vdda_hv_ebi1: - vdda_hv_ebi2: - vdda_hv_ebi3: - vdda_mipi_csi_1p25: - vdda_mipi_dsi0_1p2: - vdda_mipi_dsi1_1p2: - vdda_pcie_1p2: - vdda_ufs1_1p2: - vdda_ufs2_1p2: - vdda_usb1_ss_1p2: - vdda_usb2_ss_1p2: - vreg_l26a_1p2: ldo26 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - }; - - vreg_l28a_3p0: ldo28 { - regulator-min-microvolt = <2856000>; - regulator-max-microvolt = <3008000>; - regulator-initial-mode = ; - }; - - vreg_lvs1a_1p8: lvs1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vreg_lvs2a_1p8: lvs2 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - }; - - pmi8998-rpmh-regulators { - compatible = "qcom,pmi8998-rpmh-regulators"; - qcom,pmic-id = "b"; - - vdd-bob-supply = <&vph_pwr>; - - vreg_bob: bob { - regulator-min-microvolt = <3312000>; - regulator-max-microvolt = <3600000>; - regulator-initial-mode = ; - regulator-allow-bypass; - }; - }; - - pm8005-rpmh-regulators { - compatible = "qcom,pm8005-rpmh-regulators"; - qcom,pmic-id = "c"; - - vdd-s1-supply = <&vph_pwr>; - vdd-s2-supply = <&vph_pwr>; - vdd-s3-supply = <&vph_pwr>; - vdd-s4-supply = <&vph_pwr>; - - vreg_s3c_0p6: smps3 { - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <600000>; - }; - }; -}; - -&cdsp_pas { - status = "okay"; -}; - -&gcc { - protected-clocks = , - , - , - , - ; -}; - -&gpu { - zap-shader { - memory-region = <&gpu_mem>; - firmware-name = "qcom/sdm845/a630_zap.mbn"; - }; -}; - -&i2c10 { - status = "okay"; - clock-frequency = <400000>; -}; - -&qupv3_id_1 { - status = "okay"; -}; - -&sdhc_2 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&sdc2_clk &sdc2_cmd &sdc2_data &sd_card_det_n>; - - vmmc-supply = <&vreg_l21a_2p95>; - vqmmc-supply = <&vddpx_2>; - - cd-gpios = <&tlmm 126 GPIO_ACTIVE_LOW>; -}; - -&uart9 { - status = "okay"; -}; - -&ufs_mem_hc { - status = "okay"; - - reset-gpios = <&tlmm 150 GPIO_ACTIVE_LOW>; - - vcc-supply = <&vreg_l20a_2p95>; - vcc-max-microamp = <600000>; -}; - -&ufs_mem_phy { - status = "okay"; - - vdda-phy-supply = <&vdda_ufs1_core>; - vdda-pll-supply = <&vdda_ufs1_1p2>; -}; - -&usb_1 { - status = "okay"; -}; - -&usb_1_dwc3 { - /* Until we have Type C hooked up we'll force this as peripheral. */ - dr_mode = "peripheral"; -}; - -&usb_1_hsphy { - status = "okay"; - - vdd-supply = <&vdda_usb1_ss_core>; - vdda-pll-supply = <&vdda_qusb_hs0_1p8>; - vdda-phy-dpdm-supply = <&vdda_qusb_hs0_3p1>; - - qcom,imp-res-offset-value = <8>; - qcom,hstx-trim-value = ; - qcom,preemphasis-level = ; - qcom,preemphasis-width = ; -}; - -&usb_1_qmpphy { - status = "okay"; - - vdda-phy-supply = <&vdda_usb1_ss_1p2>; - vdda-pll-supply = <&vdda_usb1_ss_core>; -}; - -&usb_2 { - status = "okay"; -}; - -&usb_2_dwc3 { - /* - * Though the USB block on SDM845 can support host, there's no vbus - * signal for this port on MTP. Thus (unless you have a non-compliant - * hub that works without vbus) the only sensible thing is to force - * peripheral mode. - */ - dr_mode = "peripheral"; -}; - -&usb_2_hsphy { - status = "okay"; - - vdd-supply = <&vdda_usb2_ss_core>; - vdda-pll-supply = <&vdda_qusb_hs0_1p8>; - vdda-phy-dpdm-supply = <&vdda_qusb_hs0_3p1>; - - qcom,imp-res-offset-value = <8>; - qcom,hstx-trim-value = ; -}; - -&usb_2_qmpphy { - status = "okay"; - - vdda-phy-supply = <&vdda_usb2_ss_1p2>; - vdda-pll-supply = <&vdda_usb2_ss_core>; -}; - -&wifi { - status = "okay"; - vdd-0.8-cx-mx-supply = <&vreg_l5a_0p8>; - vdd-1.8-xo-supply = <&vreg_l7a_1p8>; - vdd-1.3-rfa-supply = <&vreg_l17a_1p3>; - vdd-3.3-ch0-supply = <&vreg_l25a_3p3>; -}; - -/* PINCTRL - additions to nodes defined in sdm845.dtsi */ - -&qup_i2c10_default { - pinconf { - pins = "gpio55", "gpio56"; - drive-strength = <2>; - bias-disable; - }; -}; - -&qup_uart9_default { - pinconf-tx { - pins = "gpio4"; - drive-strength = <2>; - bias-disable; - }; - - pinconf-rx { - pins = "gpio5"; - drive-strength = <2>; - bias-pull-up; - }; -}; - -&tlmm { - gpio-reserved-ranges = <0 4>, <81 4>; - - sdc2_clk: sdc2-clk { - pinconf { - pins = "sdc2_clk"; - bias-disable; - - /* - * It seems that mmc_test reports errors if drive - * strength is not 16 on clk, cmd, and data pins. - */ - drive-strength = <16>; - }; - }; - - sdc2_cmd: sdc2-cmd { - pinconf { - pins = "sdc2_cmd"; - bias-pull-up; - drive-strength = <16>; - }; - }; - - sdc2_data: sdc2-data { - pinconf { - pins = "sdc2_data"; - bias-pull-up; - drive-strength = <16>; - }; - }; - - sd_card_det_n: sd-card-det-n { - pinmux { - pins = "gpio126"; - function = "gpio"; - }; - - pinconf { - pins = "gpio126"; - bias-pull-up; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/qcom/sdm845.dtsi b/sys/gnu/dts/arm64/qcom/sdm845.dtsi deleted file mode 100644 index d42302b8889..00000000000 --- a/sys/gnu/dts/arm64/qcom/sdm845.dtsi +++ /dev/null @@ -1,3865 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * SDM845 SoC device tree source - * - * Copyright (c) 2018, The Linux Foundation. All rights reserved. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/ { - interrupt-parent = <&intc>; - - #address-cells = <2>; - #size-cells = <2>; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - i2c6 = &i2c6; - i2c7 = &i2c7; - i2c8 = &i2c8; - i2c9 = &i2c9; - i2c10 = &i2c10; - i2c11 = &i2c11; - i2c12 = &i2c12; - i2c13 = &i2c13; - i2c14 = &i2c14; - i2c15 = &i2c15; - spi0 = &spi0; - spi1 = &spi1; - spi2 = &spi2; - spi3 = &spi3; - spi4 = &spi4; - spi5 = &spi5; - spi6 = &spi6; - spi7 = &spi7; - spi8 = &spi8; - spi9 = &spi9; - spi10 = &spi10; - spi11 = &spi11; - spi12 = &spi12; - spi13 = &spi13; - spi14 = &spi14; - spi15 = &spi15; - }; - - chosen { }; - - memory@80000000 { - device_type = "memory"; - /* We expect the bootloader to fill in the size */ - reg = <0 0x80000000 0 0>; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - hyp_mem: memory@85700000 { - reg = <0 0x85700000 0 0x600000>; - no-map; - }; - - xbl_mem: memory@85e00000 { - reg = <0 0x85e00000 0 0x100000>; - no-map; - }; - - aop_mem: memory@85fc0000 { - reg = <0 0x85fc0000 0 0x20000>; - no-map; - }; - - aop_cmd_db_mem: memory@85fe0000 { - compatible = "qcom,cmd-db"; - reg = <0x0 0x85fe0000 0 0x20000>; - no-map; - }; - - smem_mem: memory@86000000 { - reg = <0x0 0x86000000 0 0x200000>; - no-map; - }; - - tz_mem: memory@86200000 { - reg = <0 0x86200000 0 0x2d00000>; - no-map; - }; - - rmtfs_mem: memory@88f00000 { - compatible = "qcom,rmtfs-mem"; - reg = <0 0x88f00000 0 0x200000>; - no-map; - - qcom,client-id = <1>; - qcom,vmid = <15>; - }; - - qseecom_mem: memory@8ab00000 { - reg = <0 0x8ab00000 0 0x1400000>; - no-map; - }; - - camera_mem: memory@8bf00000 { - reg = <0 0x8bf00000 0 0x500000>; - no-map; - }; - - ipa_fw_mem: memory@8c400000 { - reg = <0 0x8c400000 0 0x10000>; - no-map; - }; - - ipa_gsi_mem: memory@8c410000 { - reg = <0 0x8c410000 0 0x5000>; - no-map; - }; - - gpu_mem: memory@8c415000 { - reg = <0 0x8c415000 0 0x2000>; - no-map; - }; - - adsp_mem: memory@8c500000 { - reg = <0 0x8c500000 0 0x1a00000>; - no-map; - }; - - wlan_msa_mem: memory@8df00000 { - reg = <0 0x8df00000 0 0x100000>; - no-map; - }; - - mpss_region: memory@8e000000 { - reg = <0 0x8e000000 0 0x7800000>; - no-map; - }; - - venus_mem: memory@95800000 { - reg = <0 0x95800000 0 0x500000>; - no-map; - }; - - cdsp_mem: memory@95d00000 { - reg = <0 0x95d00000 0 0x800000>; - no-map; - }; - - mba_region: memory@96500000 { - reg = <0 0x96500000 0 0x200000>; - no-map; - }; - - slpi_mem: memory@96700000 { - reg = <0 0x96700000 0 0x1400000>; - no-map; - }; - - spss_mem: memory@97b00000 { - reg = <0 0x97b00000 0 0x100000>; - no-map; - }; - }; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - CPU0: cpu@0 { - device_type = "cpu"; - compatible = "qcom,kryo385"; - reg = <0x0 0x0>; - enable-method = "psci"; - cpu-idle-states = <&LITTLE_CPU_SLEEP_0 - &LITTLE_CPU_SLEEP_1 - &CLUSTER_SLEEP_0>; - capacity-dmips-mhz = <607>; - dynamic-power-coefficient = <100>; - qcom,freq-domain = <&cpufreq_hw 0>; - #cooling-cells = <2>; - next-level-cache = <&L2_0>; - L2_0: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - L3_0: l3-cache { - compatible = "cache"; - }; - }; - }; - - CPU1: cpu@100 { - device_type = "cpu"; - compatible = "qcom,kryo385"; - reg = <0x0 0x100>; - enable-method = "psci"; - cpu-idle-states = <&LITTLE_CPU_SLEEP_0 - &LITTLE_CPU_SLEEP_1 - &CLUSTER_SLEEP_0>; - capacity-dmips-mhz = <607>; - dynamic-power-coefficient = <100>; - qcom,freq-domain = <&cpufreq_hw 0>; - #cooling-cells = <2>; - next-level-cache = <&L2_100>; - L2_100: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU2: cpu@200 { - device_type = "cpu"; - compatible = "qcom,kryo385"; - reg = <0x0 0x200>; - enable-method = "psci"; - cpu-idle-states = <&LITTLE_CPU_SLEEP_0 - &LITTLE_CPU_SLEEP_1 - &CLUSTER_SLEEP_0>; - capacity-dmips-mhz = <607>; - dynamic-power-coefficient = <100>; - qcom,freq-domain = <&cpufreq_hw 0>; - #cooling-cells = <2>; - next-level-cache = <&L2_200>; - L2_200: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU3: cpu@300 { - device_type = "cpu"; - compatible = "qcom,kryo385"; - reg = <0x0 0x300>; - enable-method = "psci"; - cpu-idle-states = <&LITTLE_CPU_SLEEP_0 - &LITTLE_CPU_SLEEP_1 - &CLUSTER_SLEEP_0>; - capacity-dmips-mhz = <607>; - dynamic-power-coefficient = <100>; - qcom,freq-domain = <&cpufreq_hw 0>; - #cooling-cells = <2>; - next-level-cache = <&L2_300>; - L2_300: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU4: cpu@400 { - device_type = "cpu"; - compatible = "qcom,kryo385"; - reg = <0x0 0x400>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - cpu-idle-states = <&BIG_CPU_SLEEP_0 - &BIG_CPU_SLEEP_1 - &CLUSTER_SLEEP_0>; - dynamic-power-coefficient = <396>; - qcom,freq-domain = <&cpufreq_hw 1>; - #cooling-cells = <2>; - next-level-cache = <&L2_400>; - L2_400: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU5: cpu@500 { - device_type = "cpu"; - compatible = "qcom,kryo385"; - reg = <0x0 0x500>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - cpu-idle-states = <&BIG_CPU_SLEEP_0 - &BIG_CPU_SLEEP_1 - &CLUSTER_SLEEP_0>; - dynamic-power-coefficient = <396>; - qcom,freq-domain = <&cpufreq_hw 1>; - #cooling-cells = <2>; - next-level-cache = <&L2_500>; - L2_500: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU6: cpu@600 { - device_type = "cpu"; - compatible = "qcom,kryo385"; - reg = <0x0 0x600>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - cpu-idle-states = <&BIG_CPU_SLEEP_0 - &BIG_CPU_SLEEP_1 - &CLUSTER_SLEEP_0>; - dynamic-power-coefficient = <396>; - qcom,freq-domain = <&cpufreq_hw 1>; - #cooling-cells = <2>; - next-level-cache = <&L2_600>; - L2_600: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU7: cpu@700 { - device_type = "cpu"; - compatible = "qcom,kryo385"; - reg = <0x0 0x700>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - cpu-idle-states = <&BIG_CPU_SLEEP_0 - &BIG_CPU_SLEEP_1 - &CLUSTER_SLEEP_0>; - dynamic-power-coefficient = <396>; - qcom,freq-domain = <&cpufreq_hw 1>; - #cooling-cells = <2>; - next-level-cache = <&L2_700>; - L2_700: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - cpu-map { - cluster0 { - core0 { - cpu = <&CPU0>; - }; - - core1 { - cpu = <&CPU1>; - }; - - core2 { - cpu = <&CPU2>; - }; - - core3 { - cpu = <&CPU3>; - }; - - core4 { - cpu = <&CPU4>; - }; - - core5 { - cpu = <&CPU5>; - }; - - core6 { - cpu = <&CPU6>; - }; - - core7 { - cpu = <&CPU7>; - }; - }; - }; - - idle-states { - entry-method = "psci"; - - LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { - compatible = "arm,idle-state"; - idle-state-name = "little-power-down"; - arm,psci-suspend-param = <0x40000003>; - entry-latency-us = <350>; - exit-latency-us = <461>; - min-residency-us = <1890>; - local-timer-stop; - }; - - LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { - compatible = "arm,idle-state"; - idle-state-name = "little-rail-power-down"; - arm,psci-suspend-param = <0x40000004>; - entry-latency-us = <360>; - exit-latency-us = <531>; - min-residency-us = <3934>; - local-timer-stop; - }; - - BIG_CPU_SLEEP_0: cpu-sleep-1-0 { - compatible = "arm,idle-state"; - idle-state-name = "big-power-down"; - arm,psci-suspend-param = <0x40000003>; - entry-latency-us = <264>; - exit-latency-us = <621>; - min-residency-us = <952>; - local-timer-stop; - }; - - BIG_CPU_SLEEP_1: cpu-sleep-1-1 { - compatible = "arm,idle-state"; - idle-state-name = "big-rail-power-down"; - arm,psci-suspend-param = <0x40000004>; - entry-latency-us = <702>; - exit-latency-us = <1061>; - min-residency-us = <4488>; - local-timer-stop; - }; - - CLUSTER_SLEEP_0: cluster-sleep-0 { - compatible = "arm,idle-state"; - idle-state-name = "cluster-power-down"; - arm,psci-suspend-param = <0x400000F4>; - entry-latency-us = <3263>; - exit-latency-us = <6562>; - min-residency-us = <9987>; - local-timer-stop; - }; - }; - }; - - pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = ; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - clocks { - xo_board: xo-board { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <38400000>; - clock-output-names = "xo_board"; - }; - - sleep_clk: sleep-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32764>; - }; - }; - - firmware { - scm { - compatible = "qcom,scm-sdm845", "qcom,scm"; - }; - }; - - adsp_pas: remoteproc-adsp { - compatible = "qcom,sdm845-adsp-pas"; - - interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", - "handover", "stop-ack"; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "xo"; - - memory-region = <&adsp_mem>; - - qcom,smem-states = <&adsp_smp2p_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - glink-edge { - interrupts = ; - label = "lpass"; - qcom,remote-pid = <2>; - mboxes = <&apss_shared 8>; - fastrpc { - compatible = "qcom,fastrpc"; - qcom,glink-channels = "fastrpcglink-apps-dsp"; - label = "adsp"; - #address-cells = <1>; - #size-cells = <0>; - - compute-cb@3 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <3>; - iommus = <&apps_smmu 0x1823 0x0>; - }; - - compute-cb@4 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <4>; - iommus = <&apps_smmu 0x1824 0x0>; - }; - }; - }; - }; - - cdsp_pas: remoteproc-cdsp { - compatible = "qcom,sdm845-cdsp-pas"; - - interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, - <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, - <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, - <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", - "handover", "stop-ack"; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "xo"; - - memory-region = <&cdsp_mem>; - - qcom,smem-states = <&cdsp_smp2p_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - glink-edge { - interrupts = ; - label = "turing"; - qcom,remote-pid = <5>; - mboxes = <&apss_shared 4>; - fastrpc { - compatible = "qcom,fastrpc"; - qcom,glink-channels = "fastrpcglink-apps-dsp"; - label = "cdsp"; - #address-cells = <1>; - #size-cells = <0>; - - compute-cb@1 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <1>; - iommus = <&apps_smmu 0x1401 0x30>; - }; - - compute-cb@2 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <2>; - iommus = <&apps_smmu 0x1402 0x30>; - }; - - compute-cb@3 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <3>; - iommus = <&apps_smmu 0x1403 0x30>; - }; - - compute-cb@4 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <4>; - iommus = <&apps_smmu 0x1404 0x30>; - }; - - compute-cb@5 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <5>; - iommus = <&apps_smmu 0x1405 0x30>; - }; - - compute-cb@6 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <6>; - iommus = <&apps_smmu 0x1406 0x30>; - }; - - compute-cb@7 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <7>; - iommus = <&apps_smmu 0x1407 0x30>; - }; - - compute-cb@8 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <8>; - iommus = <&apps_smmu 0x1408 0x30>; - }; - }; - }; - }; - - tcsr_mutex: hwlock { - compatible = "qcom,tcsr-mutex"; - syscon = <&tcsr_mutex_regs 0 0x1000>; - #hwlock-cells = <1>; - }; - - smem { - compatible = "qcom,smem"; - memory-region = <&smem_mem>; - hwlocks = <&tcsr_mutex 3>; - }; - - smp2p-cdsp { - compatible = "qcom,smp2p"; - qcom,smem = <94>, <432>; - - interrupts = ; - - mboxes = <&apss_shared 6>; - - qcom,local-pid = <0>; - qcom,remote-pid = <5>; - - cdsp_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - cdsp_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - smp2p-lpass { - compatible = "qcom,smp2p"; - qcom,smem = <443>, <429>; - - interrupts = ; - - mboxes = <&apss_shared 10>; - - qcom,local-pid = <0>; - qcom,remote-pid = <2>; - - adsp_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - adsp_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - smp2p-mpss { - compatible = "qcom,smp2p"; - qcom,smem = <435>, <428>; - interrupts = ; - mboxes = <&apss_shared 14>; - qcom,local-pid = <0>; - qcom,remote-pid = <1>; - - modem_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - modem_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - smp2p-slpi { - compatible = "qcom,smp2p"; - qcom,smem = <481>, <430>; - interrupts = ; - mboxes = <&apss_shared 26>; - qcom,local-pid = <0>; - qcom,remote-pid = <3>; - - slpi_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - slpi_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - soc: soc@0 { - #address-cells = <2>; - #size-cells = <2>; - ranges = <0 0 0 0 0x10 0>; - dma-ranges = <0 0 0 0 0x10 0>; - compatible = "simple-bus"; - - gcc: clock-controller@100000 { - compatible = "qcom,gcc-sdm845"; - reg = <0 0x00100000 0 0x1f0000>; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - }; - - qfprom@784000 { - compatible = "qcom,qfprom"; - reg = <0 0x00784000 0 0x8ff>; - #address-cells = <1>; - #size-cells = <1>; - - qusb2p_hstx_trim: hstx-trim-primary@1eb { - reg = <0x1eb 0x1>; - bits = <1 4>; - }; - - qusb2s_hstx_trim: hstx-trim-secondary@1eb { - reg = <0x1eb 0x2>; - bits = <6 4>; - }; - }; - - rng: rng@793000 { - compatible = "qcom,prng-ee"; - reg = <0 0x00793000 0 0x1000>; - clocks = <&gcc GCC_PRNG_AHB_CLK>; - clock-names = "core"; - }; - - qupv3_id_0: geniqup@8c0000 { - compatible = "qcom,geni-se-qup"; - reg = <0 0x008c0000 0 0x6000>; - clock-names = "m-ahb", "s-ahb"; - clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, - <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - status = "disabled"; - - i2c0: i2c@880000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00880000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c0_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi0: spi@880000 { - compatible = "qcom,geni-spi"; - reg = <0 0x00880000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi0_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - uart0: serial@880000 { - compatible = "qcom,geni-uart"; - reg = <0 0x00880000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_uart0_default>; - interrupts = ; - status = "disabled"; - }; - - i2c1: i2c@884000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00884000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c1_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi1: spi@884000 { - compatible = "qcom,geni-spi"; - reg = <0 0x00884000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi1_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - uart1: serial@884000 { - compatible = "qcom,geni-uart"; - reg = <0 0x00884000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_uart1_default>; - interrupts = ; - status = "disabled"; - }; - - i2c2: i2c@888000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00888000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c2_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi2: spi@888000 { - compatible = "qcom,geni-spi"; - reg = <0 0x00888000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi2_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - uart2: serial@888000 { - compatible = "qcom,geni-uart"; - reg = <0 0x00888000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_uart2_default>; - interrupts = ; - status = "disabled"; - }; - - i2c3: i2c@88c000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x0088c000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c3_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi3: spi@88c000 { - compatible = "qcom,geni-spi"; - reg = <0 0x0088c000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi3_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - uart3: serial@88c000 { - compatible = "qcom,geni-uart"; - reg = <0 0x0088c000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_uart3_default>; - interrupts = ; - status = "disabled"; - }; - - i2c4: i2c@890000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00890000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c4_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi4: spi@890000 { - compatible = "qcom,geni-spi"; - reg = <0 0x00890000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi4_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - uart4: serial@890000 { - compatible = "qcom,geni-uart"; - reg = <0 0x00890000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_uart4_default>; - interrupts = ; - status = "disabled"; - }; - - i2c5: i2c@894000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00894000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c5_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi5: spi@894000 { - compatible = "qcom,geni-spi"; - reg = <0 0x00894000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi5_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - uart5: serial@894000 { - compatible = "qcom,geni-uart"; - reg = <0 0x00894000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_uart5_default>; - interrupts = ; - status = "disabled"; - }; - - i2c6: i2c@898000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00898000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c6_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi6: spi@898000 { - compatible = "qcom,geni-spi"; - reg = <0 0x00898000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi6_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - uart6: serial@898000 { - compatible = "qcom,geni-uart"; - reg = <0 0x00898000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_uart6_default>; - interrupts = ; - status = "disabled"; - }; - - i2c7: i2c@89c000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x0089c000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c7_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi7: spi@89c000 { - compatible = "qcom,geni-spi"; - reg = <0 0x0089c000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi7_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - uart7: serial@89c000 { - compatible = "qcom,geni-uart"; - reg = <0 0x0089c000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_uart7_default>; - interrupts = ; - status = "disabled"; - }; - }; - - qupv3_id_1: geniqup@ac0000 { - compatible = "qcom,geni-se-qup"; - reg = <0 0x00ac0000 0 0x6000>; - clock-names = "m-ahb", "s-ahb"; - clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, - <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - status = "disabled"; - - i2c8: i2c@a80000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00a80000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c8_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi8: spi@a80000 { - compatible = "qcom,geni-spi"; - reg = <0 0x00a80000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi8_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - uart8: serial@a80000 { - compatible = "qcom,geni-uart"; - reg = <0 0x00a80000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_uart8_default>; - interrupts = ; - status = "disabled"; - }; - - i2c9: i2c@a84000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00a84000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c9_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi9: spi@a84000 { - compatible = "qcom,geni-spi"; - reg = <0 0x00a84000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi9_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - uart9: serial@a84000 { - compatible = "qcom,geni-debug-uart"; - reg = <0 0x00a84000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_uart9_default>; - interrupts = ; - status = "disabled"; - }; - - i2c10: i2c@a88000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00a88000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c10_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi10: spi@a88000 { - compatible = "qcom,geni-spi"; - reg = <0 0x00a88000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi10_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - uart10: serial@a88000 { - compatible = "qcom,geni-uart"; - reg = <0 0x00a88000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_uart10_default>; - interrupts = ; - status = "disabled"; - }; - - i2c11: i2c@a8c000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00a8c000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c11_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi11: spi@a8c000 { - compatible = "qcom,geni-spi"; - reg = <0 0x00a8c000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi11_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - uart11: serial@a8c000 { - compatible = "qcom,geni-uart"; - reg = <0 0x00a8c000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_uart11_default>; - interrupts = ; - status = "disabled"; - }; - - i2c12: i2c@a90000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00a90000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c12_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi12: spi@a90000 { - compatible = "qcom,geni-spi"; - reg = <0 0x00a90000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi12_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - uart12: serial@a90000 { - compatible = "qcom,geni-uart"; - reg = <0 0x00a90000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_uart12_default>; - interrupts = ; - status = "disabled"; - }; - - i2c13: i2c@a94000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00a94000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c13_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi13: spi@a94000 { - compatible = "qcom,geni-spi"; - reg = <0 0x00a94000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi13_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - uart13: serial@a94000 { - compatible = "qcom,geni-uart"; - reg = <0 0x00a94000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_uart13_default>; - interrupts = ; - status = "disabled"; - }; - - i2c14: i2c@a98000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00a98000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c14_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi14: spi@a98000 { - compatible = "qcom,geni-spi"; - reg = <0 0x00a98000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi14_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - uart14: serial@a98000 { - compatible = "qcom,geni-uart"; - reg = <0 0x00a98000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_uart14_default>; - interrupts = ; - status = "disabled"; - }; - - i2c15: i2c@a9c000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00a9c000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c15_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi15: spi@a9c000 { - compatible = "qcom,geni-spi"; - reg = <0 0x00a9c000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi15_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - uart15: serial@a9c000 { - compatible = "qcom,geni-uart"; - reg = <0 0x00a9c000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_uart15_default>; - interrupts = ; - status = "disabled"; - }; - }; - - system-cache-controller@1100000 { - compatible = "qcom,sdm845-llcc"; - reg = <0 0x01100000 0 0x200000>, <0 0x01300000 0 0x50000>; - reg-names = "llcc_base", "llcc_broadcast_base"; - interrupts = ; - }; - - ufs_mem_hc: ufshc@1d84000 { - compatible = "qcom,sdm845-ufshc", "qcom,ufshc", - "jedec,ufs-2.0"; - reg = <0 0x01d84000 0 0x2500>; - interrupts = ; - phys = <&ufs_mem_phy_lanes>; - phy-names = "ufsphy"; - lanes-per-direction = <2>; - power-domains = <&gcc UFS_PHY_GDSC>; - #reset-cells = <1>; - resets = <&gcc GCC_UFS_PHY_BCR>; - reset-names = "rst"; - - iommus = <&apps_smmu 0x100 0xf>; - - clock-names = - "core_clk", - "bus_aggr_clk", - "iface_clk", - "core_clk_unipro", - "ref_clk", - "tx_lane0_sync_clk", - "rx_lane0_sync_clk", - "rx_lane1_sync_clk"; - clocks = - <&gcc GCC_UFS_PHY_AXI_CLK>, - <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, - <&gcc GCC_UFS_PHY_AHB_CLK>, - <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, - <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, - <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, - <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; - freq-table-hz = - <50000000 200000000>, - <0 0>, - <0 0>, - <37500000 150000000>, - <0 0>, - <0 0>, - <0 0>, - <0 0>; - - status = "disabled"; - }; - - ufs_mem_phy: phy@1d87000 { - compatible = "qcom,sdm845-qmp-ufs-phy"; - reg = <0 0x01d87000 0 0x18c>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - clock-names = "ref", - "ref_aux"; - clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, - <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; - - resets = <&ufs_mem_hc 0>; - reset-names = "ufsphy"; - status = "disabled"; - - ufs_mem_phy_lanes: lanes@1d87400 { - reg = <0 0x01d87400 0 0x108>, - <0 0x01d87600 0 0x1e0>, - <0 0x01d87c00 0 0x1dc>, - <0 0x01d87800 0 0x108>, - <0 0x01d87a00 0 0x1e0>; - #phy-cells = <0>; - }; - }; - - tcsr_mutex_regs: syscon@1f40000 { - compatible = "syscon"; - reg = <0 0x01f40000 0 0x40000>; - }; - - tlmm: pinctrl@3400000 { - compatible = "qcom,sdm845-pinctrl"; - reg = <0 0x03400000 0 0xc00000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&tlmm 0 0 150>; - wakeup-parent = <&pdc_intc>; - - qspi_clk: qspi-clk { - pinmux { - pins = "gpio95"; - function = "qspi_clk"; - }; - }; - - qspi_cs0: qspi-cs0 { - pinmux { - pins = "gpio90"; - function = "qspi_cs"; - }; - }; - - qspi_cs1: qspi-cs1 { - pinmux { - pins = "gpio89"; - function = "qspi_cs"; - }; - }; - - qspi_data01: qspi-data01 { - pinmux-data { - pins = "gpio91", "gpio92"; - function = "qspi_data"; - }; - }; - - qspi_data12: qspi-data12 { - pinmux-data { - pins = "gpio93", "gpio94"; - function = "qspi_data"; - }; - }; - - qup_i2c0_default: qup-i2c0-default { - pinmux { - pins = "gpio0", "gpio1"; - function = "qup0"; - }; - }; - - qup_i2c1_default: qup-i2c1-default { - pinmux { - pins = "gpio17", "gpio18"; - function = "qup1"; - }; - }; - - qup_i2c2_default: qup-i2c2-default { - pinmux { - pins = "gpio27", "gpio28"; - function = "qup2"; - }; - }; - - qup_i2c3_default: qup-i2c3-default { - pinmux { - pins = "gpio41", "gpio42"; - function = "qup3"; - }; - }; - - qup_i2c4_default: qup-i2c4-default { - pinmux { - pins = "gpio89", "gpio90"; - function = "qup4"; - }; - }; - - qup_i2c5_default: qup-i2c5-default { - pinmux { - pins = "gpio85", "gpio86"; - function = "qup5"; - }; - }; - - qup_i2c6_default: qup-i2c6-default { - pinmux { - pins = "gpio45", "gpio46"; - function = "qup6"; - }; - }; - - qup_i2c7_default: qup-i2c7-default { - pinmux { - pins = "gpio93", "gpio94"; - function = "qup7"; - }; - }; - - qup_i2c8_default: qup-i2c8-default { - pinmux { - pins = "gpio65", "gpio66"; - function = "qup8"; - }; - }; - - qup_i2c9_default: qup-i2c9-default { - pinmux { - pins = "gpio6", "gpio7"; - function = "qup9"; - }; - }; - - qup_i2c10_default: qup-i2c10-default { - pinmux { - pins = "gpio55", "gpio56"; - function = "qup10"; - }; - }; - - qup_i2c11_default: qup-i2c11-default { - pinmux { - pins = "gpio31", "gpio32"; - function = "qup11"; - }; - }; - - qup_i2c12_default: qup-i2c12-default { - pinmux { - pins = "gpio49", "gpio50"; - function = "qup12"; - }; - }; - - qup_i2c13_default: qup-i2c13-default { - pinmux { - pins = "gpio105", "gpio106"; - function = "qup13"; - }; - }; - - qup_i2c14_default: qup-i2c14-default { - pinmux { - pins = "gpio33", "gpio34"; - function = "qup14"; - }; - }; - - qup_i2c15_default: qup-i2c15-default { - pinmux { - pins = "gpio81", "gpio82"; - function = "qup15"; - }; - }; - - qup_spi0_default: qup-spi0-default { - pinmux { - pins = "gpio0", "gpio1", - "gpio2", "gpio3"; - function = "qup0"; - }; - }; - - qup_spi1_default: qup-spi1-default { - pinmux { - pins = "gpio17", "gpio18", - "gpio19", "gpio20"; - function = "qup1"; - }; - }; - - qup_spi2_default: qup-spi2-default { - pinmux { - pins = "gpio27", "gpio28", - "gpio29", "gpio30"; - function = "qup2"; - }; - }; - - qup_spi3_default: qup-spi3-default { - pinmux { - pins = "gpio41", "gpio42", - "gpio43", "gpio44"; - function = "qup3"; - }; - }; - - qup_spi4_default: qup-spi4-default { - pinmux { - pins = "gpio89", "gpio90", - "gpio91", "gpio92"; - function = "qup4"; - }; - }; - - qup_spi5_default: qup-spi5-default { - pinmux { - pins = "gpio85", "gpio86", - "gpio87", "gpio88"; - function = "qup5"; - }; - }; - - qup_spi6_default: qup-spi6-default { - pinmux { - pins = "gpio45", "gpio46", - "gpio47", "gpio48"; - function = "qup6"; - }; - }; - - qup_spi7_default: qup-spi7-default { - pinmux { - pins = "gpio93", "gpio94", - "gpio95", "gpio96"; - function = "qup7"; - }; - }; - - qup_spi8_default: qup-spi8-default { - pinmux { - pins = "gpio65", "gpio66", - "gpio67", "gpio68"; - function = "qup8"; - }; - }; - - qup_spi9_default: qup-spi9-default { - pinmux { - pins = "gpio6", "gpio7", - "gpio4", "gpio5"; - function = "qup9"; - }; - }; - - qup_spi10_default: qup-spi10-default { - pinmux { - pins = "gpio55", "gpio56", - "gpio53", "gpio54"; - function = "qup10"; - }; - }; - - qup_spi11_default: qup-spi11-default { - pinmux { - pins = "gpio31", "gpio32", - "gpio33", "gpio34"; - function = "qup11"; - }; - }; - - qup_spi12_default: qup-spi12-default { - pinmux { - pins = "gpio49", "gpio50", - "gpio51", "gpio52"; - function = "qup12"; - }; - }; - - qup_spi13_default: qup-spi13-default { - pinmux { - pins = "gpio105", "gpio106", - "gpio107", "gpio108"; - function = "qup13"; - }; - }; - - qup_spi14_default: qup-spi14-default { - pinmux { - pins = "gpio33", "gpio34", - "gpio31", "gpio32"; - function = "qup14"; - }; - }; - - qup_spi15_default: qup-spi15-default { - pinmux { - pins = "gpio81", "gpio82", - "gpio83", "gpio84"; - function = "qup15"; - }; - }; - - qup_uart0_default: qup-uart0-default { - pinmux { - pins = "gpio2", "gpio3"; - function = "qup0"; - }; - }; - - qup_uart1_default: qup-uart1-default { - pinmux { - pins = "gpio19", "gpio20"; - function = "qup1"; - }; - }; - - qup_uart2_default: qup-uart2-default { - pinmux { - pins = "gpio29", "gpio30"; - function = "qup2"; - }; - }; - - qup_uart3_default: qup-uart3-default { - pinmux { - pins = "gpio43", "gpio44"; - function = "qup3"; - }; - }; - - qup_uart4_default: qup-uart4-default { - pinmux { - pins = "gpio91", "gpio92"; - function = "qup4"; - }; - }; - - qup_uart5_default: qup-uart5-default { - pinmux { - pins = "gpio87", "gpio88"; - function = "qup5"; - }; - }; - - qup_uart6_default: qup-uart6-default { - pinmux { - pins = "gpio47", "gpio48"; - function = "qup6"; - }; - }; - - qup_uart7_default: qup-uart7-default { - pinmux { - pins = "gpio95", "gpio96"; - function = "qup7"; - }; - }; - - qup_uart8_default: qup-uart8-default { - pinmux { - pins = "gpio67", "gpio68"; - function = "qup8"; - }; - }; - - qup_uart9_default: qup-uart9-default { - pinmux { - pins = "gpio4", "gpio5"; - function = "qup9"; - }; - }; - - qup_uart10_default: qup-uart10-default { - pinmux { - pins = "gpio53", "gpio54"; - function = "qup10"; - }; - }; - - qup_uart11_default: qup-uart11-default { - pinmux { - pins = "gpio33", "gpio34"; - function = "qup11"; - }; - }; - - qup_uart12_default: qup-uart12-default { - pinmux { - pins = "gpio51", "gpio52"; - function = "qup12"; - }; - }; - - qup_uart13_default: qup-uart13-default { - pinmux { - pins = "gpio107", "gpio108"; - function = "qup13"; - }; - }; - - qup_uart14_default: qup-uart14-default { - pinmux { - pins = "gpio31", "gpio32"; - function = "qup14"; - }; - }; - - qup_uart15_default: qup-uart15-default { - pinmux { - pins = "gpio83", "gpio84"; - function = "qup15"; - }; - }; - }; - - mss_pil: remoteproc@4080000 { - compatible = "qcom,sdm845-mss-pil"; - reg = <0 0x04080000 0 0x408>, <0 0x04180000 0 0x48>; - reg-names = "qdsp6", "rmb"; - - interrupts-extended = - <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", - "handover", "stop-ack", - "shutdown-ack"; - - clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, - <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>, - <&gcc GCC_BOOT_ROM_AHB_CLK>, - <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>, - <&gcc GCC_MSS_SNOC_AXI_CLK>, - <&gcc GCC_MSS_MFAB_AXIS_CLK>, - <&gcc GCC_PRNG_AHB_CLK>, - <&rpmhcc RPMH_CXO_CLK>; - clock-names = "iface", "bus", "mem", "gpll0_mss", - "snoc_axi", "mnoc_axi", "prng", "xo"; - - qcom,smem-states = <&modem_smp2p_out 0>; - qcom,smem-state-names = "stop"; - - resets = <&aoss_reset AOSS_CC_MSS_RESTART>, - <&pdc_reset PDC_MODEM_SYNC_RESET>; - reset-names = "mss_restart", "pdc_reset"; - - qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>; - - power-domains = <&aoss_qmp 2>, - <&rpmhpd SDM845_CX>, - <&rpmhpd SDM845_MX>, - <&rpmhpd SDM845_MSS>; - power-domain-names = "load_state", "cx", "mx", "mss"; - - mba { - memory-region = <&mba_region>; - }; - - mpss { - memory-region = <&mpss_region>; - }; - - glink-edge { - interrupts = ; - label = "modem"; - qcom,remote-pid = <1>; - mboxes = <&apss_shared 12>; - }; - }; - - gpucc: clock-controller@5090000 { - compatible = "qcom,sdm845-gpucc"; - reg = <0 0x05090000 0 0x9000>; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "xo"; - }; - - stm@6002000 { - compatible = "arm,coresight-stm", "arm,primecell"; - reg = <0 0x06002000 0 0x1000>, - <0 0x16280000 0 0x180000>; - reg-names = "stm-base", "stm-stimulus-base"; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - port { - stm_out: endpoint { - remote-endpoint = - <&funnel0_in7>; - }; - }; - }; - }; - - funnel@6041000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0x06041000 0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - port { - funnel0_out: endpoint { - remote-endpoint = - <&merge_funnel_in0>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@7 { - reg = <7>; - funnel0_in7: endpoint { - remote-endpoint = <&stm_out>; - }; - }; - }; - }; - - funnel@6043000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0x06043000 0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - port { - funnel2_out: endpoint { - remote-endpoint = - <&merge_funnel_in2>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@5 { - reg = <5>; - funnel2_in5: endpoint { - remote-endpoint = - <&apss_merge_funnel_out>; - }; - }; - }; - }; - - funnel@6045000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0x06045000 0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - port { - merge_funnel_out: endpoint { - remote-endpoint = <&etf_in>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - merge_funnel_in0: endpoint { - remote-endpoint = - <&funnel0_out>; - }; - }; - - port@2 { - reg = <2>; - merge_funnel_in2: endpoint { - remote-endpoint = - <&funnel2_out>; - }; - }; - }; - }; - - replicator@6046000 { - compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; - reg = <0 0x06046000 0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - port { - replicator_out: endpoint { - remote-endpoint = <&etr_in>; - }; - }; - }; - - in-ports { - port { - replicator_in: endpoint { - remote-endpoint = <&etf_out>; - }; - }; - }; - }; - - etf@6047000 { - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0 0x06047000 0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - port { - etf_out: endpoint { - remote-endpoint = - <&replicator_in>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - etf_in: endpoint { - remote-endpoint = - <&merge_funnel_out>; - }; - }; - }; - }; - - etr@6048000 { - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0 0x06048000 0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - arm,scatter-gather; - - in-ports { - port { - etr_in: endpoint { - remote-endpoint = - <&replicator_out>; - }; - }; - }; - }; - - etm@7040000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x07040000 0 0x1000>; - - cpu = <&CPU0>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - port { - etm0_out: endpoint { - remote-endpoint = - <&apss_funnel_in0>; - }; - }; - }; - }; - - etm@7140000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x07140000 0 0x1000>; - - cpu = <&CPU1>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - port { - etm1_out: endpoint { - remote-endpoint = - <&apss_funnel_in1>; - }; - }; - }; - }; - - etm@7240000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x07240000 0 0x1000>; - - cpu = <&CPU2>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - port { - etm2_out: endpoint { - remote-endpoint = - <&apss_funnel_in2>; - }; - }; - }; - }; - - etm@7340000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x07340000 0 0x1000>; - - cpu = <&CPU3>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - port { - etm3_out: endpoint { - remote-endpoint = - <&apss_funnel_in3>; - }; - }; - }; - }; - - etm@7440000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x07440000 0 0x1000>; - - cpu = <&CPU4>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - port { - etm4_out: endpoint { - remote-endpoint = - <&apss_funnel_in4>; - }; - }; - }; - }; - - etm@7540000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x07540000 0 0x1000>; - - cpu = <&CPU5>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - port { - etm5_out: endpoint { - remote-endpoint = - <&apss_funnel_in5>; - }; - }; - }; - }; - - etm@7640000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x07640000 0 0x1000>; - - cpu = <&CPU6>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - port { - etm6_out: endpoint { - remote-endpoint = - <&apss_funnel_in6>; - }; - }; - }; - }; - - etm@7740000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x07740000 0 0x1000>; - - cpu = <&CPU7>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - port { - etm7_out: endpoint { - remote-endpoint = - <&apss_funnel_in7>; - }; - }; - }; - }; - - funnel@7800000 { /* APSS Funnel */ - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0x07800000 0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - port { - apss_funnel_out: endpoint { - remote-endpoint = - <&apss_merge_funnel_in>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - apss_funnel_in0: endpoint { - remote-endpoint = - <&etm0_out>; - }; - }; - - port@1 { - reg = <1>; - apss_funnel_in1: endpoint { - remote-endpoint = - <&etm1_out>; - }; - }; - - port@2 { - reg = <2>; - apss_funnel_in2: endpoint { - remote-endpoint = - <&etm2_out>; - }; - }; - - port@3 { - reg = <3>; - apss_funnel_in3: endpoint { - remote-endpoint = - <&etm3_out>; - }; - }; - - port@4 { - reg = <4>; - apss_funnel_in4: endpoint { - remote-endpoint = - <&etm4_out>; - }; - }; - - port@5 { - reg = <5>; - apss_funnel_in5: endpoint { - remote-endpoint = - <&etm5_out>; - }; - }; - - port@6 { - reg = <6>; - apss_funnel_in6: endpoint { - remote-endpoint = - <&etm6_out>; - }; - }; - - port@7 { - reg = <7>; - apss_funnel_in7: endpoint { - remote-endpoint = - <&etm7_out>; - }; - }; - }; - }; - - funnel@7810000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0x07810000 0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - port { - apss_merge_funnel_out: endpoint { - remote-endpoint = - <&funnel2_in5>; - }; - }; - }; - - in-ports { - port { - apss_merge_funnel_in: endpoint { - remote-endpoint = - <&apss_funnel_out>; - }; - }; - }; - }; - - sdhc_2: sdhci@8804000 { - compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5"; - reg = <0 0x08804000 0 0x1000>; - - interrupts = , - ; - interrupt-names = "hc_irq", "pwr_irq"; - - clocks = <&gcc GCC_SDCC2_AHB_CLK>, - <&gcc GCC_SDCC2_APPS_CLK>; - clock-names = "iface", "core"; - iommus = <&apps_smmu 0xa0 0xf>; - - status = "disabled"; - }; - - qspi: spi@88df000 { - compatible = "qcom,sdm845-qspi", "qcom,qspi-v1"; - reg = <0 0x088df000 0 0x600>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, - <&gcc GCC_QSPI_CORE_CLK>; - clock-names = "iface", "core"; - status = "disabled"; - }; - - usb_1_hsphy: phy@88e2000 { - compatible = "qcom,sdm845-qusb2-phy"; - reg = <0 0x088e2000 0 0x400>; - status = "disabled"; - #phy-cells = <0>; - - clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, - <&rpmhcc RPMH_CXO_CLK>; - clock-names = "cfg_ahb", "ref"; - - resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; - - nvmem-cells = <&qusb2p_hstx_trim>; - }; - - usb_2_hsphy: phy@88e3000 { - compatible = "qcom,sdm845-qusb2-phy"; - reg = <0 0x088e3000 0 0x400>; - status = "disabled"; - #phy-cells = <0>; - - clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, - <&rpmhcc RPMH_CXO_CLK>; - clock-names = "cfg_ahb", "ref"; - - resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; - - nvmem-cells = <&qusb2s_hstx_trim>; - }; - - usb_1_qmpphy: phy@88e9000 { - compatible = "qcom,sdm845-qmp-usb3-phy"; - reg = <0 0x088e9000 0 0x18c>, - <0 0x088e8000 0 0x10>; - reg-names = "reg-base", "dp_com"; - status = "disabled"; - #clock-cells = <1>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, - <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, - <&gcc GCC_USB3_PRIM_CLKREF_CLK>, - <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; - clock-names = "aux", "cfg_ahb", "ref", "com_aux"; - - resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, - <&gcc GCC_USB3_PHY_PRIM_BCR>; - reset-names = "phy", "common"; - - usb_1_ssphy: lanes@88e9200 { - reg = <0 0x088e9200 0 0x128>, - <0 0x088e9400 0 0x200>, - <0 0x088e9c00 0 0x218>, - <0 0x088e9600 0 0x128>, - <0 0x088e9800 0 0x200>, - <0 0x088e9a00 0 0x100>; - #phy-cells = <0>; - clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; - clock-names = "pipe0"; - clock-output-names = "usb3_phy_pipe_clk_src"; - }; - }; - - usb_2_qmpphy: phy@88eb000 { - compatible = "qcom,sdm845-qmp-usb3-uni-phy"; - reg = <0 0x088eb000 0 0x18c>; - status = "disabled"; - #clock-cells = <1>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, - <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, - <&gcc GCC_USB3_SEC_CLKREF_CLK>, - <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; - clock-names = "aux", "cfg_ahb", "ref", "com_aux"; - - resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, - <&gcc GCC_USB3_PHY_SEC_BCR>; - reset-names = "phy", "common"; - - usb_2_ssphy: lane@88eb200 { - reg = <0 0x088eb200 0 0x128>, - <0 0x088eb400 0 0x1fc>, - <0 0x088eb800 0 0x218>, - <0 0x088eb600 0 0x70>; - #phy-cells = <0>; - clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; - clock-names = "pipe0"; - clock-output-names = "usb3_uni_phy_pipe_clk_src"; - }; - }; - - usb_1: usb@a6f8800 { - compatible = "qcom,sdm845-dwc3", "qcom,dwc3"; - reg = <0 0x0a6f8800 0 0x400>; - status = "disabled"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - dma-ranges; - - clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, - <&gcc GCC_USB30_PRIM_MASTER_CLK>, - <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, - <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_PRIM_SLEEP_CLK>; - clock-names = "cfg_noc", "core", "iface", "mock_utmi", - "sleep"; - - assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_PRIM_MASTER_CLK>; - assigned-clock-rates = <19200000>, <150000000>; - - interrupts = , - , - , - ; - interrupt-names = "hs_phy_irq", "ss_phy_irq", - "dm_hs_phy_irq", "dp_hs_phy_irq"; - - power-domains = <&gcc USB30_PRIM_GDSC>; - - resets = <&gcc GCC_USB30_PRIM_BCR>; - - usb_1_dwc3: dwc3@a600000 { - compatible = "snps,dwc3"; - reg = <0 0x0a600000 0 0xcd00>; - interrupts = ; - iommus = <&apps_smmu 0x740 0>; - snps,dis_u2_susphy_quirk; - snps,dis_enblslpm_quirk; - phys = <&usb_1_hsphy>, <&usb_1_ssphy>; - phy-names = "usb2-phy", "usb3-phy"; - }; - }; - - usb_2: usb@a8f8800 { - compatible = "qcom,sdm845-dwc3", "qcom,dwc3"; - reg = <0 0x0a8f8800 0 0x400>; - status = "disabled"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - dma-ranges; - - clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, - <&gcc GCC_USB30_SEC_MASTER_CLK>, - <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, - <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_SEC_SLEEP_CLK>; - clock-names = "cfg_noc", "core", "iface", "mock_utmi", - "sleep"; - - assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_SEC_MASTER_CLK>; - assigned-clock-rates = <19200000>, <150000000>; - - interrupts = , - , - , - ; - interrupt-names = "hs_phy_irq", "ss_phy_irq", - "dm_hs_phy_irq", "dp_hs_phy_irq"; - - power-domains = <&gcc USB30_SEC_GDSC>; - - resets = <&gcc GCC_USB30_SEC_BCR>; - - usb_2_dwc3: dwc3@a800000 { - compatible = "snps,dwc3"; - reg = <0 0x0a800000 0 0xcd00>; - interrupts = ; - iommus = <&apps_smmu 0x760 0>; - snps,dis_u2_susphy_quirk; - snps,dis_enblslpm_quirk; - phys = <&usb_2_hsphy>, <&usb_2_ssphy>; - phy-names = "usb2-phy", "usb3-phy"; - }; - }; - - video-codec@aa00000 { - compatible = "qcom,sdm845-venus"; - reg = <0 0x0aa00000 0 0xff000>; - interrupts = ; - power-domains = <&videocc VENUS_GDSC>; - clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>, - <&videocc VIDEO_CC_VENUS_AHB_CLK>, - <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>; - clock-names = "core", "iface", "bus"; - iommus = <&apps_smmu 0x10a0 0x8>, - <&apps_smmu 0x10b0 0x0>; - memory-region = <&venus_mem>; - - video-core0 { - compatible = "venus-decoder"; - clocks = <&videocc VIDEO_CC_VCODEC0_CORE_CLK>, - <&videocc VIDEO_CC_VCODEC0_AXI_CLK>; - clock-names = "core", "bus"; - power-domains = <&videocc VCODEC0_GDSC>; - }; - - video-core1 { - compatible = "venus-encoder"; - clocks = <&videocc VIDEO_CC_VCODEC1_CORE_CLK>, - <&videocc VIDEO_CC_VCODEC1_AXI_CLK>; - clock-names = "core", "bus"; - power-domains = <&videocc VCODEC1_GDSC>; - }; - }; - - videocc: clock-controller@ab00000 { - compatible = "qcom,sdm845-videocc"; - reg = <0 0x0ab00000 0 0x10000>; - #clock-cells = <1>; - #power-domain-cells = <1>; - #reset-cells = <1>; - }; - - mdss: mdss@ae00000 { - compatible = "qcom,sdm845-mdss"; - reg = <0 0x0ae00000 0 0x1000>; - reg-names = "mdss"; - - power-domains = <&dispcc MDSS_GDSC>; - - clocks = <&gcc GCC_DISP_AHB_CLK>, - <&gcc GCC_DISP_AXI_CLK>, - <&dispcc DISP_CC_MDSS_MDP_CLK>; - clock-names = "iface", "bus", "core"; - - assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; - assigned-clock-rates = <300000000>; - - interrupts = ; - interrupt-controller; - #interrupt-cells = <1>; - - iommus = <&apps_smmu 0x880 0x8>, - <&apps_smmu 0xc80 0x8>; - - status = "disabled"; - - #address-cells = <2>; - #size-cells = <2>; - ranges; - - mdss_mdp: mdp@ae01000 { - compatible = "qcom,sdm845-dpu"; - reg = <0 0x0ae01000 0 0x8f000>, - <0 0x0aeb0000 0 0x2008>; - reg-names = "mdp", "vbif"; - - clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, - <&dispcc DISP_CC_MDSS_AXI_CLK>, - <&dispcc DISP_CC_MDSS_MDP_CLK>, - <&dispcc DISP_CC_MDSS_VSYNC_CLK>; - clock-names = "iface", "bus", "core", "vsync"; - - assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, - <&dispcc DISP_CC_MDSS_VSYNC_CLK>; - assigned-clock-rates = <300000000>, - <19200000>; - - interrupt-parent = <&mdss>; - interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; - - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dpu_intf1_out: endpoint { - remote-endpoint = <&dsi0_in>; - }; - }; - - port@1 { - reg = <1>; - dpu_intf2_out: endpoint { - remote-endpoint = <&dsi1_in>; - }; - }; - }; - }; - - dsi0: dsi@ae94000 { - compatible = "qcom,mdss-dsi-ctrl"; - reg = <0 0x0ae94000 0 0x400>; - reg-names = "dsi_ctrl"; - - interrupt-parent = <&mdss>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; - - clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, - <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, - <&dispcc DISP_CC_MDSS_PCLK0_CLK>, - <&dispcc DISP_CC_MDSS_ESC0_CLK>, - <&dispcc DISP_CC_MDSS_AHB_CLK>, - <&dispcc DISP_CC_MDSS_AXI_CLK>; - clock-names = "byte", - "byte_intf", - "pixel", - "core", - "iface", - "bus"; - - phys = <&dsi0_phy>; - phy-names = "dsi"; - - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dsi0_in: endpoint { - remote-endpoint = <&dpu_intf1_out>; - }; - }; - - port@1 { - reg = <1>; - dsi0_out: endpoint { - }; - }; - }; - }; - - dsi0_phy: dsi-phy@ae94400 { - compatible = "qcom,dsi-phy-10nm"; - reg = <0 0x0ae94400 0 0x200>, - <0 0x0ae94600 0 0x280>, - <0 0x0ae94a00 0 0x1e0>; - reg-names = "dsi_phy", - "dsi_phy_lane", - "dsi_pll"; - - #clock-cells = <1>; - #phy-cells = <0>; - - clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, - <&rpmhcc RPMH_CXO_CLK>; - clock-names = "iface", "ref"; - - status = "disabled"; - }; - - dsi1: dsi@ae96000 { - compatible = "qcom,mdss-dsi-ctrl"; - reg = <0 0x0ae96000 0 0x400>; - reg-names = "dsi_ctrl"; - - interrupt-parent = <&mdss>; - interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; - - clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, - <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, - <&dispcc DISP_CC_MDSS_PCLK1_CLK>, - <&dispcc DISP_CC_MDSS_ESC1_CLK>, - <&dispcc DISP_CC_MDSS_AHB_CLK>, - <&dispcc DISP_CC_MDSS_AXI_CLK>; - clock-names = "byte", - "byte_intf", - "pixel", - "core", - "iface", - "bus"; - - phys = <&dsi1_phy>; - phy-names = "dsi"; - - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dsi1_in: endpoint { - remote-endpoint = <&dpu_intf2_out>; - }; - }; - - port@1 { - reg = <1>; - dsi1_out: endpoint { - }; - }; - }; - }; - - dsi1_phy: dsi-phy@ae96400 { - compatible = "qcom,dsi-phy-10nm"; - reg = <0 0x0ae96400 0 0x200>, - <0 0x0ae96600 0 0x280>, - <0 0x0ae96a00 0 0x10e>; - reg-names = "dsi_phy", - "dsi_phy_lane", - "dsi_pll"; - - #clock-cells = <1>; - #phy-cells = <0>; - - clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, - <&rpmhcc RPMH_CXO_CLK>; - clock-names = "iface", "ref"; - - status = "disabled"; - }; - }; - - gpu: gpu@5000000 { - compatible = "qcom,adreno-630.2", "qcom,adreno"; - #stream-id-cells = <16>; - - reg = <0 0x5000000 0 0x40000>, <0 0x509e000 0 0x10>; - reg-names = "kgsl_3d0_reg_memory", "cx_mem"; - - /* - * Look ma, no clocks! The GPU clocks and power are - * controlled entirely by the GMU - */ - - interrupts = ; - - iommus = <&adreno_smmu 0>; - - operating-points-v2 = <&gpu_opp_table>; - - qcom,gmu = <&gmu>; - - gpu_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-710000000 { - opp-hz = /bits/ 64 <710000000>; - opp-level = ; - }; - - opp-675000000 { - opp-hz = /bits/ 64 <675000000>; - opp-level = ; - }; - - opp-596000000 { - opp-hz = /bits/ 64 <596000000>; - opp-level = ; - }; - - opp-520000000 { - opp-hz = /bits/ 64 <520000000>; - opp-level = ; - }; - - opp-414000000 { - opp-hz = /bits/ 64 <414000000>; - opp-level = ; - }; - - opp-342000000 { - opp-hz = /bits/ 64 <342000000>; - opp-level = ; - }; - - opp-257000000 { - opp-hz = /bits/ 64 <257000000>; - opp-level = ; - }; - }; - }; - - adreno_smmu: iommu@5040000 { - compatible = "qcom,sdm845-smmu-v2", "qcom,smmu-v2"; - reg = <0 0x5040000 0 0x10000>; - #iommu-cells = <1>; - #global-interrupts = <2>; - interrupts = , - , - , - , - , - , - , - , - , - ; - clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, - <&gcc GCC_GPU_CFG_AHB_CLK>; - clock-names = "bus", "iface"; - - power-domains = <&gpucc GPU_CX_GDSC>; - }; - - gmu: gmu@506a000 { - compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu"; - - reg = <0 0x506a000 0 0x30000>, - <0 0xb280000 0 0x10000>, - <0 0xb480000 0 0x10000>; - reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; - - interrupts = , - ; - interrupt-names = "hfi", "gmu"; - - clocks = <&gpucc GPU_CC_CX_GMU_CLK>, - <&gpucc GPU_CC_CXO_CLK>, - <&gcc GCC_DDRSS_GPU_AXI_CLK>, - <&gcc GCC_GPU_MEMNOC_GFX_CLK>; - clock-names = "gmu", "cxo", "axi", "memnoc"; - - power-domains = <&gpucc GPU_CX_GDSC>, - <&gpucc GPU_GX_GDSC>; - power-domain-names = "cx", "gx"; - - iommus = <&adreno_smmu 5>; - - operating-points-v2 = <&gmu_opp_table>; - - gmu_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-400000000 { - opp-hz = /bits/ 64 <400000000>; - opp-level = ; - }; - - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - opp-level = ; - }; - }; - }; - - dispcc: clock-controller@af00000 { - compatible = "qcom,sdm845-dispcc"; - reg = <0 0x0af00000 0 0x10000>; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - }; - - pdc_intc: interrupt-controller@b220000 { - compatible = "qcom,sdm845-pdc", "qcom,pdc"; - reg = <0 0x0b220000 0 0x30000>; - qcom,pdc-ranges = <0 480 94>, <94 609 15>, <115 630 7>; - #interrupt-cells = <2>; - interrupt-parent = <&intc>; - interrupt-controller; - }; - - pdc_reset: reset-controller@b2e0000 { - compatible = "qcom,sdm845-pdc-global"; - reg = <0 0x0b2e0000 0 0x20000>; - #reset-cells = <1>; - }; - - tsens0: thermal-sensor@c263000 { - compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; - reg = <0 0x0c263000 0 0x1ff>, /* TM */ - <0 0x0c222000 0 0x1ff>; /* SROT */ - #qcom,sensors = <13>; - interrupts = , - ; - interrupt-names = "uplow", "critical"; - #thermal-sensor-cells = <1>; - }; - - tsens1: thermal-sensor@c265000 { - compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; - reg = <0 0x0c265000 0 0x1ff>, /* TM */ - <0 0x0c223000 0 0x1ff>; /* SROT */ - #qcom,sensors = <8>; - interrupts = , - ; - interrupt-names = "uplow", "critical"; - #thermal-sensor-cells = <1>; - }; - - aoss_reset: reset-controller@c2a0000 { - compatible = "qcom,sdm845-aoss-cc"; - reg = <0 0x0c2a0000 0 0x31000>; - #reset-cells = <1>; - }; - - aoss_qmp: qmp@c300000 { - compatible = "qcom,sdm845-aoss-qmp"; - reg = <0 0x0c300000 0 0x100000>; - interrupts = ; - mboxes = <&apss_shared 0>; - - #clock-cells = <0>; - #power-domain-cells = <1>; - - cx_cdev: cx { - #cooling-cells = <2>; - }; - - ebi_cdev: ebi { - #cooling-cells = <2>; - }; - }; - - spmi_bus: spmi@c440000 { - compatible = "qcom,spmi-pmic-arb"; - reg = <0 0x0c440000 0 0x1100>, - <0 0x0c600000 0 0x2000000>, - <0 0x0e600000 0 0x100000>, - <0 0x0e700000 0 0xa0000>, - <0 0x0c40a000 0 0x26000>; - reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; - interrupt-names = "periph_irq"; - interrupts = ; - qcom,ee = <0>; - qcom,channel = <0>; - #address-cells = <2>; - #size-cells = <0>; - interrupt-controller; - #interrupt-cells = <4>; - cell-index = <0>; - }; - - apps_smmu: iommu@15000000 { - compatible = "qcom,sdm845-smmu-500", "arm,mmu-500"; - reg = <0 0x15000000 0 0x80000>; - #iommu-cells = <2>; - #global-interrupts = <1>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - }; - - lpasscc: clock-controller@17014000 { - compatible = "qcom,sdm845-lpasscc"; - reg = <0 0x17014000 0 0x1f004>, <0 0x17300000 0 0x200>; - reg-names = "cc", "qdsp6ss"; - #clock-cells = <1>; - status = "disabled"; - }; - - watchdog@17980000 { - compatible = "qcom,apss-wdt-sdm845", "qcom,kpss-wdt"; - reg = <0 0x17980000 0 0x1000>; - clocks = <&sleep_clk>; - }; - - apss_shared: mailbox@17990000 { - compatible = "qcom,sdm845-apss-shared"; - reg = <0 0x17990000 0 0x1000>; - #mbox-cells = <1>; - }; - - apps_rsc: rsc@179c0000 { - label = "apps_rsc"; - compatible = "qcom,rpmh-rsc"; - reg = <0 0x179c0000 0 0x10000>, - <0 0x179d0000 0 0x10000>, - <0 0x179e0000 0 0x10000>; - reg-names = "drv-0", "drv-1", "drv-2"; - interrupts = , - , - ; - qcom,tcs-offset = <0xd00>; - qcom,drv-id = <2>; - qcom,tcs-config = , - , - , - ; - - rpmhcc: clock-controller { - compatible = "qcom,sdm845-rpmh-clk"; - #clock-cells = <1>; - clock-names = "xo"; - clocks = <&xo_board>; - }; - - rpmhpd: power-controller { - compatible = "qcom,sdm845-rpmhpd"; - #power-domain-cells = <1>; - operating-points-v2 = <&rpmhpd_opp_table>; - - rpmhpd_opp_table: opp-table { - compatible = "operating-points-v2"; - - rpmhpd_opp_ret: opp1 { - opp-level = ; - }; - - rpmhpd_opp_min_svs: opp2 { - opp-level = ; - }; - - rpmhpd_opp_low_svs: opp3 { - opp-level = ; - }; - - rpmhpd_opp_svs: opp4 { - opp-level = ; - }; - - rpmhpd_opp_svs_l1: opp5 { - opp-level = ; - }; - - rpmhpd_opp_nom: opp6 { - opp-level = ; - }; - - rpmhpd_opp_nom_l1: opp7 { - opp-level = ; - }; - - rpmhpd_opp_nom_l2: opp8 { - opp-level = ; - }; - - rpmhpd_opp_turbo: opp9 { - opp-level = ; - }; - - rpmhpd_opp_turbo_l1: opp10 { - opp-level = ; - }; - }; - }; - - rsc_hlos: interconnect { - compatible = "qcom,sdm845-rsc-hlos"; - #interconnect-cells = <1>; - }; - }; - - intc: interrupt-controller@17a00000 { - compatible = "arm,gic-v3"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0 0x17a00000 0 0x10000>, /* GICD */ - <0 0x17a60000 0 0x100000>; /* GICR * 8 */ - interrupts = ; - - msi-controller@17a40000 { - compatible = "arm,gic-v3-its"; - msi-controller; - #msi-cells = <1>; - reg = <0 0x17a40000 0 0x20000>; - status = "disabled"; - }; - }; - - timer@17c90000 { - #address-cells = <2>; - #size-cells = <2>; - ranges; - compatible = "arm,armv7-timer-mem"; - reg = <0 0x17c90000 0 0x1000>; - - frame@17ca0000 { - frame-number = <0>; - interrupts = , - ; - reg = <0 0x17ca0000 0 0x1000>, - <0 0x17cb0000 0 0x1000>; - }; - - frame@17cc0000 { - frame-number = <1>; - interrupts = ; - reg = <0 0x17cc0000 0 0x1000>; - status = "disabled"; - }; - - frame@17cd0000 { - frame-number = <2>; - interrupts = ; - reg = <0 0x17cd0000 0 0x1000>; - status = "disabled"; - }; - - frame@17ce0000 { - frame-number = <3>; - interrupts = ; - reg = <0 0x17ce0000 0 0x1000>; - status = "disabled"; - }; - - frame@17cf0000 { - frame-number = <4>; - interrupts = ; - reg = <0 0x17cf0000 0 0x1000>; - status = "disabled"; - }; - - frame@17d00000 { - frame-number = <5>; - interrupts = ; - reg = <0 0x17d00000 0 0x1000>; - status = "disabled"; - }; - - frame@17d10000 { - frame-number = <6>; - interrupts = ; - reg = <0 0x17d10000 0 0x1000>; - status = "disabled"; - }; - }; - - cpufreq_hw: cpufreq@17d43000 { - compatible = "qcom,cpufreq-hw"; - reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>; - reg-names = "freq-domain0", "freq-domain1"; - - clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; - clock-names = "xo", "alternate"; - - #freq-domain-cells = <1>; - }; - - wifi: wifi@18800000 { - compatible = "qcom,wcn3990-wifi"; - status = "disabled"; - reg = <0 0x18800000 0 0x800000>; - reg-names = "membase"; - memory-region = <&wlan_msa_mem>; - clock-names = "cxo_ref_clk_pin"; - clocks = <&rpmhcc RPMH_RF_CLK2>; - interrupts = - , - , - , - , - , - , - , - , - , - , - , - ; - iommus = <&apps_smmu 0x0040 0x1>; - }; - }; - - thermal-zones { - cpu0-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 1>; - - trips { - cpu0_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu0_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu0_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu0_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu0_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu1-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 2>; - - trips { - cpu1_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu1_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu1_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu1_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu1_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu2-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 3>; - - trips { - cpu2_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu2_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu2_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu2_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu2_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu3-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 4>; - - trips { - cpu3_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu3_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu3_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu3_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu3_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu4-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 7>; - - trips { - cpu4_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu4_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu4_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu4_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu4_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu5-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 8>; - - trips { - cpu5_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu5_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu5_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu5_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu5_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu6-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 9>; - - trips { - cpu6_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu6_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu6_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu6_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu6_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu7-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 10>; - - trips { - cpu7_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu7_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu7_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu7_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu7_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - aoss0-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 0>; - - trips { - aoss0_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - cluster0-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 5>; - - trips { - cluster0_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - cluster0_crit: cluster0_crit { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - cluster1-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 6>; - - trips { - cluster1_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - cluster1_crit: cluster1_crit { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - gpu-thermal-top { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 11>; - - trips { - gpu1_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - gpu-thermal-bottom { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 12>; - - trips { - gpu2_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - aoss1-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 0>; - - trips { - aoss1_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - q6-modem-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 1>; - - trips { - q6_modem_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - mem-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 2>; - - trips { - mem_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - wlan-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 3>; - - trips { - wlan_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - q6-hvx-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 4>; - - trips { - q6_hvx_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - camera-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 5>; - - trips { - camera_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - video-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 6>; - - trips { - video_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - modem-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 7>; - - trips { - modem_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/qcom/sdm850-lenovo-yoga-c630.dts b/sys/gnu/dts/arm64/qcom/sdm850-lenovo-yoga-c630.dts deleted file mode 100644 index b255be3a4a0..00000000000 --- a/sys/gnu/dts/arm64/qcom/sdm850-lenovo-yoga-c630.dts +++ /dev/null @@ -1,467 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Lenovo Yoga C630 - * - * Copyright (c) 2019, Linaro Ltd. - */ - -/dts-v1/; - -#include -#include "sdm845.dtsi" -#include "pm8998.dtsi" - -/ { - model = "Lenovo Yoga C630"; - compatible = "lenovo,yoga-c630", "qcom,sdm845"; - - aliases { - hsuart0 = &uart6; - }; -}; - -&adsp_pas { - firmware-name = "qcom/LENOVO/81JL/qcadsp850.mbn"; - status = "okay"; -}; - -&apps_rsc { - pm8998-rpmh-regulators { - compatible = "qcom,pm8998-rpmh-regulators"; - qcom,pmic-id = "a"; - - vdd-l2-l8-l17-supply = <&vreg_s3a_1p35>; - vdd-l7-l12-l14-l15-supply = <&vreg_s5a_2p04>; - - vreg_s2a_1p125: smps2 { - }; - - vreg_s3a_1p35: smps3 { - regulator-min-microvolt = <1352000>; - regulator-max-microvolt = <1352000>; - regulator-initial-mode = ; - }; - - vreg_s4a_1p8: smps4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vreg_s5a_2p04: smps5 { - regulator-min-microvolt = <2040000>; - regulator-max-microvolt = <2040000>; - regulator-initial-mode = ; - }; - - vreg_s7a_1p025: smps7 { - }; - - vdd_qusb_hs0: - vdda_hp_pcie_core: - vdda_mipi_csi0_0p9: - vdda_mipi_csi1_0p9: - vdda_mipi_csi2_0p9: - vdda_mipi_dsi0_pll: - vdda_mipi_dsi1_pll: - vdda_qlink_lv: - vdda_qlink_lv_ck: - vdda_qrefs_0p875: - vdda_pcie_core: - vdda_pll_cc_ebi01: - vdda_pll_cc_ebi23: - vdda_sp_sensor: - vdda_ufs1_core: - vdda_ufs2_core: - vdda_usb1_ss_core: - vdda_usb2_ss_core: - vreg_l1a_0p875: ldo1 { - regulator-min-microvolt = <880000>; - regulator-max-microvolt = <880000>; - regulator-initial-mode = ; - }; - - vddpx_10: - vreg_l2a_1p2: ldo2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - regulator-always-on; - }; - - vreg_l3a_1p0: ldo3 { - }; - - vdd_wcss_cx: - vdd_wcss_mx: - vdda_wcss_pll: - vreg_l5a_0p8: ldo5 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <800000>; - regulator-initial-mode = ; - }; - - vddpx_13: - vreg_l6a_1p8: ldo6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vreg_l7a_1p8: ldo7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vreg_l8a_1p2: ldo8 { - }; - - vreg_l9a_1p8: ldo9 { - }; - - vreg_l10a_1p8: ldo10 { - }; - - vreg_l11a_1p0: ldo11 { - }; - - vdd_qfprom: - vdd_qfprom_sp: - vdda_apc1_cs_1p8: - vdda_gfx_cs_1p8: - vdda_qrefs_1p8: - vdda_qusb_hs0_1p8: - vddpx_11: - vreg_l12a_1p8: ldo12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vddpx_2: - vreg_l13a_2p95: ldo13 { - }; - - vreg_l14a_1p88: ldo14 { - regulator-min-microvolt = <1880000>; - regulator-max-microvolt = <1880000>; - regulator-initial-mode = ; - regulator-always-on; - }; - - vreg_l15a_1p8: ldo15 { - }; - - vreg_l16a_2p7: ldo16 { - }; - - vreg_l17a_1p3: ldo17 { - regulator-min-microvolt = <1304000>; - regulator-max-microvolt = <1304000>; - regulator-initial-mode = ; - }; - - vreg_l18a_2p7: ldo18 { - }; - - vreg_l19a_3p0: ldo19 { - regulator-min-microvolt = <3100000>; - regulator-max-microvolt = <3108000>; - regulator-initial-mode = ; - }; - - vreg_l20a_2p95: ldo20 { - regulator-min-microvolt = <2960000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = ; - }; - - vreg_l21a_2p95: ldo21 { - }; - - vreg_l22a_2p85: ldo22 { - }; - - vreg_l23a_3p3: ldo23 { - }; - - vdda_qusb_hs0_3p1: - vreg_l24a_3p075: ldo24 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3083000>; - regulator-initial-mode = ; - }; - - vreg_l25a_3p3: ldo25 { - regulator-min-microvolt = <3104000>; - regulator-max-microvolt = <3112000>; - regulator-initial-mode = ; - }; - - vdda_hp_pcie_1p2: - vdda_hv_ebi0: - vdda_hv_ebi1: - vdda_hv_ebi2: - vdda_hv_ebi3: - vdda_mipi_csi_1p25: - vdda_mipi_dsi0_1p2: - vdda_mipi_dsi1_1p2: - vdda_pcie_1p2: - vdda_ufs1_1p2: - vdda_ufs2_1p2: - vdda_usb1_ss_1p2: - vdda_usb2_ss_1p2: - vreg_l26a_1p2: ldo26 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1208000>; - regulator-initial-mode = ; - }; - - vreg_l28a_3p0: ldo28 { - }; - - vreg_lvs1a_1p8: lvs1 { - }; - - vreg_lvs2a_1p8: lvs2 { - }; - }; -}; - -&apps_smmu { - /* TODO: Figure out how to survive booting with this enabled */ - status = "disabled"; -}; - -&cdsp_pas { - firmware-name = "qcom/LENOVO/81JL/qccdsp850.mbn"; - status = "okay"; -}; - -&gcc { - protected-clocks = , - , - ; -}; - -&gpu { - zap-shader { - memory-region = <&gpu_mem>; - firmware-name = "qcom/LENOVO/81JL/qcdxkmsuc850.mbn"; - }; -}; - -&i2c1 { - status = "okay"; - clock-frequency = <400000>; -}; - -&i2c3 { - status = "okay"; - clock-frequency = <400000>; - - hid@15 { - compatible = "hid-over-i2c"; - reg = <0x15>; - hid-descr-addr = <0x1>; - - interrupts-extended = <&tlmm 37 IRQ_TYPE_EDGE_RISING>; - }; - - hid@2c { - compatible = "hid-over-i2c"; - reg = <0x2c>; - hid-descr-addr = <0x20>; - - interrupts-extended = <&tlmm 37 IRQ_TYPE_EDGE_RISING>; - - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_hid_active>; - }; -}; - -&i2c5 { - status = "okay"; - clock-frequency = <400000>; - - hid@10 { - compatible = "hid-over-i2c"; - reg = <0x10>; - hid-descr-addr = <0x1>; - - interrupts-extended = <&tlmm 125 IRQ_TYPE_EDGE_FALLING>; - - pinctrl-names = "default"; - pinctrl-0 = <&i2c6_hid_active>; - }; -}; - -&i2c11 { - status = "okay"; - clock-frequency = <400000>; - - hid@5c { - compatible = "hid-over-i2c"; - reg = <0x5c>; - hid-descr-addr = <0x1>; - - interrupts-extended = <&tlmm 92 IRQ_TYPE_LEVEL_LOW>; - - pinctrl-names = "default"; - pinctrl-0 = <&i2c12_hid_active>; - }; -}; - -&mss_pil { - firmware-name = "qcom/LENOVO/81JL/qcdsp1v2850.mbn", "qcom/LENOVO/81JL/qcdsp2850.mbn"; -}; - -&qup_i2c12_default { - drive-strength = <2>; - bias-disable; -}; - -&qup_uart6_default { - pinmux { - pins = "gpio45", "gpio46", "gpio47", "gpio48"; - function = "qup6"; - }; - - cts { - pins = "gpio45"; - bias-pull-down; - }; - - rts-tx { - pins = "gpio46", "gpio47"; - drive-strength = <2>; - bias-disable; - }; - - rx { - pins = "gpio48"; - bias-pull-up; - }; -}; - -&qupv3_id_0 { - status = "okay"; -}; - -&qupv3_id_1 { - status = "okay"; -}; - -&tlmm { - gpio-reserved-ranges = <0 4>, <81 4>; - - i2c2_hid_active: i2c2-hid-active { - pins = <37>; - function = "gpio"; - - input-enable; - bias-pull-up; - drive-strength = <2>; - }; - - i2c6_hid_active: i2c6-hid-active { - pins = <125>; - function = "gpio"; - - input-enable; - bias-pull-up; - drive-strength = <2>; - }; - - i2c12_hid_active: i2c12-hid-active { - pins = <92>; - function = "gpio"; - - input-enable; - bias-pull-up; - drive-strength = <2>; - }; -}; - -&uart6 { - status = "okay"; - - bluetooth { - compatible = "qcom,wcn3990-bt"; - - vddio-supply = <&vreg_s4a_1p8>; - vddxo-supply = <&vreg_l7a_1p8>; - vddrf-supply = <&vreg_l17a_1p3>; - vddch0-supply = <&vreg_l25a_3p3>; - max-speed = <3200000>; - }; -}; - -&ufs_mem_hc { - status = "okay"; - - vcc-supply = <&vreg_l20a_2p95>; - vcc-max-microamp = <600000>; -}; - -&ufs_mem_phy { - status = "okay"; - - vdda-phy-supply = <&vdda_ufs1_core>; - vdda-pll-supply = <&vdda_ufs1_1p2>; -}; - -&usb_1 { - status = "okay"; -}; - -&usb_1_dwc3 { - dr_mode = "host"; -}; - -&usb_1_hsphy { - status = "okay"; - - vdd-supply = <&vdda_usb1_ss_core>; - vdda-pll-supply = <&vdda_qusb_hs0_1p8>; - vdda-phy-dpdm-supply = <&vdda_qusb_hs0_3p1>; - - qcom,imp-res-offset-value = <8>; - qcom,hstx-trim-value = ; - qcom,preemphasis-level = ; - qcom,preemphasis-width = ; -}; - -&usb_1_qmpphy { - status = "okay"; - - vdda-phy-supply = <&vdda_usb1_ss_1p2>; - vdda-pll-supply = <&vdda_usb1_ss_core>; -}; - -&usb_2 { - status = "okay"; -}; - -&usb_2_dwc3 { - dr_mode = "host"; -}; - -&usb_2_hsphy { - status = "okay"; - - vdd-supply = <&vdda_usb2_ss_core>; - vdda-pll-supply = <&vdda_qusb_hs0_1p8>; - vdda-phy-dpdm-supply = <&vdda_qusb_hs0_3p1>; - - qcom,imp-res-offset-value = <8>; - qcom,hstx-trim-value = ; -}; - -&usb_2_qmpphy { - status = "okay"; - - vdda-phy-supply = <&vdda_usb2_ss_1p2>; - vdda-pll-supply = <&vdda_usb2_ss_core>; -}; diff --git a/sys/gnu/dts/arm64/qcom/sm8150-mtp.dts b/sys/gnu/dts/arm64/qcom/sm8150-mtp.dts deleted file mode 100644 index 8ab16611ebe..00000000000 --- a/sys/gnu/dts/arm64/qcom/sm8150-mtp.dts +++ /dev/null @@ -1,410 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. - * Copyright (c) 2019, Linaro Limited - */ - -/dts-v1/; - -#include -#include -#include "sm8150.dtsi" -#include "pm8150.dtsi" -#include "pm8150b.dtsi" -#include "pm8150l.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. SM8150 MTP"; - compatible = "qcom,sm8150-mtp"; - - aliases { - serial0 = &uart2; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - vph_pwr: vph-pwr-regulator { - compatible = "regulator-fixed"; - regulator-name = "vph_pwr"; - regulator-min-microvolt = <3700000>; - regulator-max-microvolt = <3700000>; - }; - - /* - * Apparently RPMh does not provide support for PM8150 S4 because it - * is always-on; model it as a fixed regulator. - */ - vreg_s4a_1p8: pm8150-s4 { - compatible = "regulator-fixed"; - regulator-name = "vreg_s4a_1p8"; - - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-always-on; - regulator-boot-on; - - vin-supply = <&vph_pwr>; - }; -}; - -&apps_rsc { - pm8150-rpmh-regulators { - compatible = "qcom,pm8150-rpmh-regulators"; - qcom,pmic-id = "a"; - - vdd-s1-supply = <&vph_pwr>; - vdd-s2-supply = <&vph_pwr>; - vdd-s3-supply = <&vph_pwr>; - vdd-s4-supply = <&vph_pwr>; - vdd-s5-supply = <&vph_pwr>; - vdd-s6-supply = <&vph_pwr>; - vdd-s7-supply = <&vph_pwr>; - vdd-s8-supply = <&vph_pwr>; - vdd-s9-supply = <&vph_pwr>; - vdd-s10-supply = <&vph_pwr>; - - vdd-l1-l8-l11-supply = <&vreg_s6a_0p9>; - vdd-l2-l10-supply = <&vreg_bob>; - vdd-l3-l4-l5-l18-supply = <&vreg_s6a_0p9>; - vdd-l6-l9-supply = <&vreg_s8c_1p3>; - vdd-l7-l12-l14-l15-supply = <&vreg_s5a_2p0>; - vdd-l13-l16-l17-supply = <&vreg_bob>; - - vreg_s5a_2p0: smps5 { - regulator-min-microvolt = <1904000>; - regulator-max-microvolt = <2000000>; - }; - - vreg_s6a_0p9: smps6 { - regulator-min-microvolt = <920000>; - regulator-max-microvolt = <1128000>; - }; - - vdda_wcss_pll: - vreg_l1a_0p75: ldo1 { - regulator-min-microvolt = <752000>; - regulator-max-microvolt = <752000>; - regulator-initial-mode = ; - }; - - vdd_pdphy: - vdda_usb_hs_3p1: - vreg_l2a_3p1: ldo2 { - regulator-min-microvolt = <3072000>; - regulator-max-microvolt = <3072000>; - regulator-initial-mode = ; - }; - - vreg_l3a_0p8: ldo3 { - regulator-min-microvolt = <480000>; - regulator-max-microvolt = <932000>; - regulator-initial-mode = ; - }; - - vdd_usb_hs_core: - vdda_csi_0_0p9: - vdda_csi_1_0p9: - vdda_csi_2_0p9: - vdda_csi_3_0p9: - vdda_dsi_0_0p9: - vdda_dsi_1_0p9: - vdda_dsi_0_pll_0p9: - vdda_dsi_1_pll_0p9: - vdda_pcie_1ln_core: - vdda_pcie_2ln_core: - vdda_pll_hv_cc_ebi01: - vdda_pll_hv_cc_ebi23: - vdda_qrefs_0p875_5: - vdda_sp_sensor: - vdda_ufs_2ln_core_1: - vdda_ufs_2ln_core_2: - vdda_usb_ss_dp_core_1: - vdda_usb_ss_dp_core_2: - vdda_qlink_lv: - vdda_qlink_lv_ck: - vreg_l5a_0p875: ldo5 { - regulator-min-microvolt = <880000>; - regulator-max-microvolt = <880000>; - regulator-initial-mode = ; - }; - - vreg_l6a_1p2: ldo6 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - }; - - vreg_l7a_1p8: ldo7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vddpx_10: - vreg_l9a_1p2: ldo9 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - }; - - vreg_l10a_2p5: ldo10 { - regulator-min-microvolt = <2504000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = ; - }; - - vreg_l11a_0p8: ldo11 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <800000>; - regulator-initial-mode = ; - }; - - vdd_qfprom: - vdd_qfprom_sp: - vdda_apc_cs_1p8: - vdda_gfx_cs_1p8: - vdda_usb_hs_1p8: - vdda_qrefs_vref_1p8: - vddpx_10_a: - vreg_l12a_1p8: ldo12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vreg_l13a_2p7: ldo13 { - regulator-min-microvolt = <2704000>; - regulator-max-microvolt = <2704000>; - regulator-initial-mode = ; - }; - - vreg_l14a_1p8: ldo14 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1880000>; - regulator-initial-mode = ; - }; - - vreg_l15a_1p7: ldo15 { - regulator-min-microvolt = <1704000>; - regulator-max-microvolt = <1704000>; - regulator-initial-mode = ; - }; - - vreg_l16a_2p7: ldo16 { - regulator-min-microvolt = <2704000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = ; - }; - - vreg_l17a_3p0: ldo17 { - regulator-min-microvolt = <2856000>; - regulator-max-microvolt = <3008000>; - regulator-initial-mode = ; - }; - }; - - pm8150l-rpmh-regulators { - compatible = "qcom,pm8150l-rpmh-regulators"; - qcom,pmic-id = "c"; - - vdd-s1-supply = <&vph_pwr>; - vdd-s2-supply = <&vph_pwr>; - vdd-s3-supply = <&vph_pwr>; - vdd-s4-supply = <&vph_pwr>; - vdd-s5-supply = <&vph_pwr>; - vdd-s6-supply = <&vph_pwr>; - vdd-s7-supply = <&vph_pwr>; - vdd-s8-supply = <&vph_pwr>; - - vdd-l1-l8-supply = <&vreg_s4a_1p8>; - vdd-l2-l3-supply = <&vreg_s8c_1p3>; - vdd-l4-l5-l6-supply = <&vreg_bob>; - vdd-l7-l11-supply = <&vreg_bob>; - vdd-l9-l10-supply = <&vreg_bob>; - - vdd-bob-supply = <&vph_pwr>; - vdd-flash-supply = <&vreg_bob>; - vdd-rgb-supply = <&vreg_bob>; - - vreg_bob: bob { - regulator-min-microvolt = <3008000>; - regulator-max-microvolt = <4000000>; - regulator-initial-mode = ; - regulator-allow-bypass; - }; - - vreg_s8c_1p3: smps8 { - regulator-min-microvolt = <1352000>; - regulator-max-microvolt = <1352000>; - }; - - vreg_l1c_1p8: ldo1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vdda_wcss_adcdac_1: - vdda_wcss_adcdac_22: - vreg_l2c_1p3: ldo2 { - regulator-min-microvolt = <1304000>; - regulator-max-microvolt = <1304000>; - regulator-initial-mode = ; - }; - - vdda_hv_ebi0: - vdda_hv_ebi1: - vdda_hv_ebi2: - vdda_hv_ebi3: - vdda_hv_refgen0: - vdda_qlink_hv_ck: - vreg_l3c_1p2: ldo3 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - }; - - vddpx_5: - vreg_l4c_1p8: ldo4 { - regulator-min-microvolt = <1704000>; - regulator-max-microvolt = <2928000>; - regulator-initial-mode = ; - }; - - vddpx_6: - vreg_l5c_1p8: ldo5 { - regulator-min-microvolt = <1704000>; - regulator-max-microvolt = <2928000>; - regulator-initial-mode = ; - }; - - vddpx_2: - vreg_l6c_2p9: ldo6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = ; - }; - - vreg_l7c_3p0: ldo7 { - regulator-min-microvolt = <2856000>; - regulator-max-microvolt = <3104000>; - regulator-initial-mode = ; - }; - - vreg_l8c_1p8: ldo8 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vreg_l9c_2p9: ldo9 { - regulator-min-microvolt = <2704000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = ; - }; - - vreg_l10c_3p3: ldo10 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3312000>; - regulator-initial-mode = ; - }; - - vreg_l11c_3p3: ldo11 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3312000>; - regulator-initial-mode = ; - }; - }; - - pm8009-rpmh-regulators { - compatible = "qcom,pm8009-rpmh-regulators"; - qcom,pmic-id = "f"; - - vdd-s1-supply = <&vph_pwr>; - vdd-s2-supply = <&vreg_bob>; - - vdd-l2-supply = <&vreg_s8c_1p3>; - vdd-l5-l6-supply = <&vreg_bob>; - - vreg_l2f_1p2: ldo2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - }; - - vreg_l5f_2p85: ldo5 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-initial-mode = ; - }; - - vreg_l6f_2p85: ldo6 { - regulator-initial-mode = ; - regulator-min-microvolt = <2856000>; - regulator-max-microvolt = <2856000>; - }; - }; -}; - -&qupv3_id_1 { - status = "okay"; -}; - -&pon { - pwrkey { - status = "okay"; - }; - - resin { - compatible = "qcom,pm8941-resin"; - interrupts = <0x0 0x8 0x1 IRQ_TYPE_EDGE_BOTH>; - debounce = <15625>; - bias-pull-up; - linux,code = ; - }; -}; - -&remoteproc_adsp { - status = "okay"; -}; - -&remoteproc_cdsp { - status = "okay"; -}; - -&remoteproc_slpi { - status = "okay"; -}; - -&tlmm { - gpio-reserved-ranges = <0 4>, <126 4>; -}; - -&uart2 { - status = "okay"; -}; - -&ufs_mem_hc { - status = "okay"; - - reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>; - - vcc-supply = <&vreg_l10a_2p5>; - vcc-max-microamp = <750000>; - vccq-supply = <&vreg_l9a_1p2>; - vccq-max-microamp = <700000>; - vccq2-supply = <&vreg_s4a_1p8>; - vccq2-max-microamp = <750000>; -}; - -&ufs_mem_phy { - status = "okay"; - - vdda-phy-supply = <&vdda_ufs_2ln_core_1>; - vdda-max-microamp = <90200>; - vdda-pll-supply = <&vreg_l3c_1p2>; - vdda-pll-max-microamp = <19000>; -}; diff --git a/sys/gnu/dts/arm64/qcom/sm8150.dtsi b/sys/gnu/dts/arm64/qcom/sm8150.dtsi deleted file mode 100644 index 141c21dfa68..00000000000 --- a/sys/gnu/dts/arm64/qcom/sm8150.dtsi +++ /dev/null @@ -1,867 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. - * Copyright (c) 2019, Linaro Limited - */ - -#include -#include -#include -#include -#include -#include - -/ { - interrupt-parent = <&intc>; - - #address-cells = <2>; - #size-cells = <2>; - - chosen { }; - - clocks { - xo_board: xo-board { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <38400000>; - clock-output-names = "xo_board"; - }; - - sleep_clk: sleep-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32764>; - clock-output-names = "sleep_clk"; - }; - }; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - CPU0: cpu@0 { - device_type = "cpu"; - compatible = "qcom,kryo485"; - reg = <0x0 0x0>; - enable-method = "psci"; - next-level-cache = <&L2_0>; - qcom,freq-domain = <&cpufreq_hw 0>; - L2_0: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - L3_0: l3-cache { - compatible = "cache"; - }; - }; - }; - - CPU1: cpu@100 { - device_type = "cpu"; - compatible = "qcom,kryo485"; - reg = <0x0 0x100>; - enable-method = "psci"; - next-level-cache = <&L2_100>; - qcom,freq-domain = <&cpufreq_hw 0>; - L2_100: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - - }; - - CPU2: cpu@200 { - device_type = "cpu"; - compatible = "qcom,kryo485"; - reg = <0x0 0x200>; - enable-method = "psci"; - next-level-cache = <&L2_200>; - qcom,freq-domain = <&cpufreq_hw 0>; - L2_200: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU3: cpu@300 { - device_type = "cpu"; - compatible = "qcom,kryo485"; - reg = <0x0 0x300>; - enable-method = "psci"; - next-level-cache = <&L2_300>; - qcom,freq-domain = <&cpufreq_hw 0>; - L2_300: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU4: cpu@400 { - device_type = "cpu"; - compatible = "qcom,kryo485"; - reg = <0x0 0x400>; - enable-method = "psci"; - next-level-cache = <&L2_400>; - qcom,freq-domain = <&cpufreq_hw 1>; - L2_400: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU5: cpu@500 { - device_type = "cpu"; - compatible = "qcom,kryo485"; - reg = <0x0 0x500>; - enable-method = "psci"; - next-level-cache = <&L2_500>; - qcom,freq-domain = <&cpufreq_hw 1>; - L2_500: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU6: cpu@600 { - device_type = "cpu"; - compatible = "qcom,kryo485"; - reg = <0x0 0x600>; - enable-method = "psci"; - next-level-cache = <&L2_600>; - qcom,freq-domain = <&cpufreq_hw 1>; - L2_600: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU7: cpu@700 { - device_type = "cpu"; - compatible = "qcom,kryo485"; - reg = <0x0 0x700>; - enable-method = "psci"; - next-level-cache = <&L2_700>; - qcom,freq-domain = <&cpufreq_hw 2>; - L2_700: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - }; - - firmware { - scm: scm { - compatible = "qcom,scm-sm8150", "qcom,scm"; - #reset-cells = <1>; - }; - }; - - tcsr_mutex: hwlock { - compatible = "qcom,tcsr-mutex"; - syscon = <&tcsr_mutex_regs 0 0x1000>; - #hwlock-cells = <1>; - }; - - memory@80000000 { - device_type = "memory"; - /* We expect the bootloader to fill in the size */ - reg = <0x0 0x80000000 0x0 0x0>; - }; - - pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = ; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - hyp_mem: memory@85700000 { - reg = <0x0 0x85700000 0x0 0x600000>; - no-map; - }; - - xbl_mem: memory@85d00000 { - reg = <0x0 0x85d00000 0x0 0x140000>; - no-map; - }; - - aop_mem: memory@85f00000 { - reg = <0x0 0x85f00000 0x0 0x20000>; - no-map; - }; - - aop_cmd_db: memory@85f20000 { - compatible = "qcom,cmd-db"; - reg = <0x0 0x85f20000 0x0 0x20000>; - no-map; - }; - - smem_mem: memory@86000000 { - reg = <0x0 0x86000000 0x0 0x200000>; - no-map; - }; - - tz_mem: memory@86200000 { - reg = <0x0 0x86200000 0x0 0x3900000>; - no-map; - }; - - rmtfs_mem: memory@89b00000 { - compatible = "qcom,rmtfs-mem"; - reg = <0x0 0x89b00000 0x0 0x200000>; - no-map; - - qcom,client-id = <1>; - qcom,vmid = <15>; - }; - - camera_mem: memory@8b700000 { - reg = <0x0 0x8b700000 0x0 0x500000>; - no-map; - }; - - wlan_mem: memory@8bc00000 { - reg = <0x0 0x8bc00000 0x0 0x180000>; - no-map; - }; - - npu_mem: memory@8bd80000 { - reg = <0x0 0x8bd80000 0x0 0x80000>; - no-map; - }; - - adsp_mem: memory@8be00000 { - reg = <0x0 0x8be00000 0x0 0x1a00000>; - no-map; - }; - - mpss_mem: memory@8d800000 { - reg = <0x0 0x8d800000 0x0 0x9600000>; - no-map; - }; - - venus_mem: memory@96e00000 { - reg = <0x0 0x96e00000 0x0 0x500000>; - no-map; - }; - - slpi_mem: memory@97300000 { - reg = <0x0 0x97300000 0x0 0x1400000>; - no-map; - }; - - ipa_fw_mem: memory@98700000 { - reg = <0x0 0x98700000 0x0 0x10000>; - no-map; - }; - - ipa_gsi_mem: memory@98710000 { - reg = <0x0 0x98710000 0x0 0x5000>; - no-map; - }; - - gpu_mem: memory@98715000 { - reg = <0x0 0x98715000 0x0 0x2000>; - no-map; - }; - - spss_mem: memory@98800000 { - reg = <0x0 0x98800000 0x0 0x100000>; - no-map; - }; - - cdsp_mem: memory@98900000 { - reg = <0x0 0x98900000 0x0 0x1400000>; - no-map; - }; - - qseecom_mem: memory@9e400000 { - reg = <0x0 0x9e400000 0x0 0x1400000>; - no-map; - }; - }; - - smem { - compatible = "qcom,smem"; - memory-region = <&smem_mem>; - hwlocks = <&tcsr_mutex 3>; - }; - - smp2p-cdsp { - compatible = "qcom,smp2p"; - qcom,smem = <94>, <432>; - - interrupts = ; - - mboxes = <&apss_shared 6>; - - qcom,local-pid = <0>; - qcom,remote-pid = <5>; - - cdsp_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - cdsp_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - smp2p-lpass { - compatible = "qcom,smp2p"; - qcom,smem = <443>, <429>; - - interrupts = ; - - mboxes = <&apss_shared 10>; - - qcom,local-pid = <0>; - qcom,remote-pid = <2>; - - adsp_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - adsp_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - smp2p-mpss { - compatible = "qcom,smp2p"; - qcom,smem = <435>, <428>; - - interrupts = ; - - mboxes = <&apss_shared 14>; - - qcom,local-pid = <0>; - qcom,remote-pid = <1>; - - modem_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - modem_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - smp2p-slpi { - compatible = "qcom,smp2p"; - qcom,smem = <481>, <430>; - - interrupts = ; - - mboxes = <&apss_shared 26>; - - qcom,local-pid = <0>; - qcom,remote-pid = <3>; - - slpi_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - slpi_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - soc: soc@0 { - #address-cells = <2>; - #size-cells = <2>; - ranges = <0 0 0 0 0x10 0>; - dma-ranges = <0 0 0 0 0x10 0>; - compatible = "simple-bus"; - - gcc: clock-controller@100000 { - compatible = "qcom,gcc-sm8150"; - reg = <0x0 0x00100000 0x0 0x1f0000>; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - clock-names = "bi_tcxo", - "sleep_clk"; - clocks = <&rpmhcc RPMH_CXO_CLK>, - <&sleep_clk>; - }; - - qupv3_id_1: geniqup@ac0000 { - compatible = "qcom,geni-se-qup"; - reg = <0x0 0x00ac0000 0x0 0x6000>; - clock-names = "m-ahb", "s-ahb"; - clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, - <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - status = "disabled"; - - uart2: serial@a90000 { - compatible = "qcom,geni-debug-uart"; - reg = <0x0 0x00a90000 0x0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; - interrupts = ; - status = "disabled"; - }; - }; - - ufs_mem_hc: ufshc@1d84000 { - compatible = "qcom,sm8150-ufshc", "qcom,ufshc", - "jedec,ufs-2.0"; - reg = <0 0x01d84000 0 0x2500>; - interrupts = ; - phys = <&ufs_mem_phy_lanes>; - phy-names = "ufsphy"; - lanes-per-direction = <2>; - #reset-cells = <1>; - resets = <&gcc GCC_UFS_PHY_BCR>; - reset-names = "rst"; - - clock-names = - "core_clk", - "bus_aggr_clk", - "iface_clk", - "core_clk_unipro", - "ref_clk", - "tx_lane0_sync_clk", - "rx_lane0_sync_clk", - "rx_lane1_sync_clk"; - clocks = - <&gcc GCC_UFS_PHY_AXI_CLK>, - <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, - <&gcc GCC_UFS_PHY_AHB_CLK>, - <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, - <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, - <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, - <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; - freq-table-hz = - <37500000 300000000>, - <0 0>, - <0 0>, - <37500000 300000000>, - <0 0>, - <0 0>, - <0 0>, - <0 0>; - - status = "disabled"; - }; - - ufs_mem_phy: phy@1d87000 { - compatible = "qcom,sm8150-qmp-ufs-phy"; - reg = <0 0x01d87000 0 0x1c0>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - clock-names = "ref", - "ref_aux"; - clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, - <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; - - resets = <&ufs_mem_hc 0>; - reset-names = "ufsphy"; - status = "disabled"; - - ufs_mem_phy_lanes: lanes@1d87400 { - reg = <0 0x01d87400 0 0x108>, - <0 0x01d87600 0 0x1e0>, - <0 0x01d87c00 0 0x1dc>, - <0 0x01d87800 0 0x108>, - <0 0x01d87a00 0 0x1e0>; - #phy-cells = <0>; - }; - }; - - tcsr_mutex_regs: syscon@1f40000 { - compatible = "syscon"; - reg = <0x0 0x01f40000 0x0 0x40000>; - }; - - remoteproc_slpi: remoteproc@2400000 { - compatible = "qcom,sm8150-slpi-pas"; - reg = <0x0 0x02400000 0x0 0x4040>; - - interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>, - <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, - <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, - <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", - "handover", "stop-ack"; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "xo"; - - power-domains = <&aoss_qmp AOSS_QMP_LS_SLPI>, - <&rpmhpd 3>, - <&rpmhpd 2>; - power-domain-names = "load_state", "lcx", "lmx"; - - memory-region = <&slpi_mem>; - - qcom,smem-states = <&slpi_smp2p_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - glink-edge { - interrupts = ; - label = "dsps"; - qcom,remote-pid = <3>; - mboxes = <&apss_shared 24>; - }; - }; - - tlmm: pinctrl@3100000 { - compatible = "qcom,sm8150-pinctrl"; - reg = <0x0 0x03100000 0x0 0x300000>, - <0x0 0x03500000 0x0 0x300000>, - <0x0 0x03900000 0x0 0x300000>, - <0x0 0x03D00000 0x0 0x300000>; - reg-names = "west", "east", "north", "south"; - interrupts = ; - gpio-ranges = <&tlmm 0 0 175>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - remoteproc_mpss: remoteproc@4080000 { - compatible = "qcom,sm8150-mpss-pas"; - reg = <0x0 0x04080000 0x0 0x4040>; - - interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", "handover", - "stop-ack", "shutdown-ack"; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "xo"; - - power-domains = <&aoss_qmp AOSS_QMP_LS_MODEM>, - <&rpmhpd 7>, - <&rpmhpd 0>; - power-domain-names = "load_state", "cx", "mss"; - - memory-region = <&mpss_mem>; - - qcom,smem-states = <&modem_smp2p_out 0>; - qcom,smem-state-names = "stop"; - - glink-edge { - interrupts = ; - label = "modem"; - qcom,remote-pid = <1>; - mboxes = <&apss_shared 12>; - }; - }; - - remoteproc_cdsp: remoteproc@8300000 { - compatible = "qcom,sm8150-cdsp-pas"; - reg = <0x0 0x08300000 0x0 0x4040>; - - interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, - <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, - <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, - <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", - "handover", "stop-ack"; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "xo"; - - power-domains = <&aoss_qmp AOSS_QMP_LS_CDSP>, - <&rpmhpd 7>; - power-domain-names = "load_state", "cx"; - - memory-region = <&cdsp_mem>; - - qcom,smem-states = <&cdsp_smp2p_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - glink-edge { - interrupts = ; - label = "cdsp"; - qcom,remote-pid = <5>; - mboxes = <&apss_shared 4>; - }; - }; - - aoss_qmp: power-controller@c300000 { - compatible = "qcom,sm8150-aoss-qmp"; - reg = <0x0 0x0c300000 0x0 0x100000>; - interrupts = ; - mboxes = <&apss_shared 0>; - - #clock-cells = <0>; - #power-domain-cells = <1>; - }; - - spmi_bus: spmi@c440000 { - compatible = "qcom,spmi-pmic-arb"; - reg = <0x0 0x0c440000 0x0 0x0001100>, - <0x0 0x0c600000 0x0 0x2000000>, - <0x0 0x0e600000 0x0 0x0100000>, - <0x0 0x0e700000 0x0 0x00a0000>, - <0x0 0x0c40a000 0x0 0x0026000>; - reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; - interrupt-names = "periph_irq"; - interrupts = ; - qcom,ee = <0>; - qcom,channel = <0>; - #address-cells = <2>; - #size-cells = <0>; - interrupt-controller; - #interrupt-cells = <4>; - cell-index = <0>; - }; - - remoteproc_adsp: remoteproc@17300000 { - compatible = "qcom,sm8150-adsp-pas"; - reg = <0x0 0x17300000 0x0 0x4040>; - - interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", - "handover", "stop-ack"; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "xo"; - - power-domains = <&aoss_qmp AOSS_QMP_LS_LPASS>, - <&rpmhpd 7>; - power-domain-names = "load_state", "cx"; - - memory-region = <&adsp_mem>; - - qcom,smem-states = <&adsp_smp2p_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - glink-edge { - interrupts = ; - label = "lpass"; - qcom,remote-pid = <2>; - mboxes = <&apss_shared 8>; - }; - }; - - intc: interrupt-controller@17a00000 { - compatible = "arm,gic-v3"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ - <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ - interrupts = ; - }; - - apss_shared: mailbox@17c00000 { - compatible = "qcom,sm8150-apss-shared"; - reg = <0x0 0x17c00000 0x0 0x1000>; - #mbox-cells = <1>; - }; - - watchdog@17c10000 { - compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt"; - reg = <0 0x17c10000 0 0x1000>; - clocks = <&sleep_clk>; - }; - - timer@17c20000 { - #address-cells = <2>; - #size-cells = <2>; - ranges; - compatible = "arm,armv7-timer-mem"; - reg = <0x0 0x17c20000 0x0 0x1000>; - clock-frequency = <19200000>; - - frame@17c21000{ - frame-number = <0>; - interrupts = , - ; - reg = <0x0 0x17c21000 0x0 0x1000>, - <0x0 0x17c22000 0x0 0x1000>; - }; - - frame@17c23000 { - frame-number = <1>; - interrupts = ; - reg = <0x0 0x17c23000 0x0 0x1000>; - status = "disabled"; - }; - - frame@17c25000 { - frame-number = <2>; - interrupts = ; - reg = <0x0 0x17c25000 0x0 0x1000>; - status = "disabled"; - }; - - frame@17c27000 { - frame-number = <3>; - interrupts = ; - reg = <0x0 0x17c26000 0x0 0x1000>; - status = "disabled"; - }; - - frame@17c29000 { - frame-number = <4>; - interrupts = ; - reg = <0x0 0x17c29000 0x0 0x1000>; - status = "disabled"; - }; - - frame@17c2b000 { - frame-number = <5>; - interrupts = ; - reg = <0x0 0x17c2b000 0x0 0x1000>; - status = "disabled"; - }; - - frame@17c2d000 { - frame-number = <6>; - interrupts = ; - reg = <0x0 0x17c2d000 0x0 0x1000>; - status = "disabled"; - }; - }; - - apps_rsc: rsc@18200000 { - label = "apps_rsc"; - compatible = "qcom,rpmh-rsc"; - reg = <0x0 0x18200000 0x0 0x10000>, - <0x0 0x18210000 0x0 0x10000>, - <0x0 0x18220000 0x0 0x10000>; - reg-names = "drv-0", "drv-1", "drv-2"; - interrupts = , - , - ; - qcom,tcs-offset = <0xd00>; - qcom,drv-id = <2>; - qcom,tcs-config = , - , - , - ; - - rpmhcc: clock-controller { - compatible = "qcom,sm8150-rpmh-clk"; - #clock-cells = <1>; - clock-names = "xo"; - clocks = <&xo_board>; - }; - - rpmhpd: power-controller { - compatible = "qcom,sm8150-rpmhpd"; - #power-domain-cells = <1>; - operating-points-v2 = <&rpmhpd_opp_table>; - - rpmhpd_opp_table: opp-table { - compatible = "operating-points-v2"; - - rpmhpd_opp_ret: opp1 { - opp-level = ; - }; - - rpmhpd_opp_min_svs: opp2 { - opp-level = ; - }; - - rpmhpd_opp_low_svs: opp3 { - opp-level = ; - }; - - rpmhpd_opp_svs: opp4 { - opp-level = ; - }; - - rpmhpd_opp_svs_l1: opp5 { - opp-level = ; - }; - - rpmhpd_opp_svs_l2: opp6 { - opp-level = <224>; - }; - - rpmhpd_opp_nom: opp7 { - opp-level = ; - }; - - rpmhpd_opp_nom_l1: opp8 { - opp-level = ; - }; - - rpmhpd_opp_nom_l2: opp9 { - opp-level = ; - }; - - rpmhpd_opp_turbo: opp10 { - opp-level = ; - }; - - rpmhpd_opp_turbo_l1: opp11 { - opp-level = ; - }; - }; - }; - }; - - cpufreq_hw: cpufreq@18323000 { - compatible = "qcom,cpufreq-hw"; - reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>, - <0 0x18327800 0 0x1400>; - reg-names = "freq-domain0", "freq-domain1", - "freq-domain2"; - - clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; - clock-names = "xo", "alternate"; - - #freq-domain-cells = <1>; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; -}; diff --git a/sys/gnu/dts/arm64/realtek/rtd1293-ds418j.dts b/sys/gnu/dts/arm64/realtek/rtd1293-ds418j.dts deleted file mode 100644 index b2dd583146b..00000000000 --- a/sys/gnu/dts/arm64/realtek/rtd1293-ds418j.dts +++ /dev/null @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) -/* - * Copyright (c) 2017 Andreas Färber - */ - -/dts-v1/; - -#include "rtd1293.dtsi" - -/ { - compatible = "synology,ds418j", "realtek,rtd1293"; - model = "Synology DiskStation DS418j"; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x40000000>; - }; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/realtek/rtd1293.dtsi b/sys/gnu/dts/arm64/realtek/rtd1293.dtsi deleted file mode 100644 index bd4e22723f7..00000000000 --- a/sys/gnu/dts/arm64/realtek/rtd1293.dtsi +++ /dev/null @@ -1,51 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) -/* - * Realtek RTD1293 SoC - * - * Copyright (c) 2017-2019 Andreas Färber - */ - -#include "rtd129x.dtsi" - -/ { - compatible = "realtek,rtd1293"; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x0>; - next-level-cache = <&l2>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x1>; - next-level-cache = <&l2>; - }; - - l2: l2-cache { - compatible = "cache"; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; -}; - -&arm_pmu { - interrupt-affinity = <&cpu0>, <&cpu1>; -}; diff --git a/sys/gnu/dts/arm64/realtek/rtd1295-mele-v9.dts b/sys/gnu/dts/arm64/realtek/rtd1295-mele-v9.dts deleted file mode 100644 index bd584e99fff..00000000000 --- a/sys/gnu/dts/arm64/realtek/rtd1295-mele-v9.dts +++ /dev/null @@ -1,31 +0,0 @@ -/* - * Copyright (c) 2017 Andreas Färber - * - * SPDX-License-Identifier: (GPL-2.0+ OR MIT) - */ - -/dts-v1/; - -#include "rtd1295.dtsi" - -/ { - compatible = "mele,v9", "realtek,rtd1295"; - model = "MeLE V9"; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x80000000>; - }; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/realtek/rtd1295-probox2-ava.dts b/sys/gnu/dts/arm64/realtek/rtd1295-probox2-ava.dts deleted file mode 100644 index 8e2b0e75298..00000000000 --- a/sys/gnu/dts/arm64/realtek/rtd1295-probox2-ava.dts +++ /dev/null @@ -1,31 +0,0 @@ -/* - * Copyright (c) 2017 Andreas Färber - * - * SPDX-License-Identifier: (GPL-2.0+ OR MIT) - */ - -/dts-v1/; - -#include "rtd1295.dtsi" - -/ { - compatible = "probox2,ava", "realtek,rtd1295"; - model = "PROBOX2 AVA"; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x80000000>; - }; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/realtek/rtd1295-zidoo-x9s.dts b/sys/gnu/dts/arm64/realtek/rtd1295-zidoo-x9s.dts deleted file mode 100644 index e98e508b951..00000000000 --- a/sys/gnu/dts/arm64/realtek/rtd1295-zidoo-x9s.dts +++ /dev/null @@ -1,35 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) -/* - * Copyright (c) 2016-2017 Andreas Färber - */ - -/dts-v1/; - -#include "rtd1295.dtsi" - -/ { - compatible = "zidoo,x9s", "realtek,rtd1295"; - model = "Zidoo X9S"; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x80000000>; - }; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/realtek/rtd1295.dtsi b/sys/gnu/dts/arm64/realtek/rtd1295.dtsi deleted file mode 100644 index 93f0e1d9772..00000000000 --- a/sys/gnu/dts/arm64/realtek/rtd1295.dtsi +++ /dev/null @@ -1,76 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) -/* - * Realtek RTD1295 SoC - * - * Copyright (c) 2016-2017 Andreas Färber - */ - -#include "rtd129x.dtsi" - -/ { - compatible = "realtek,rtd1295"; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x0>; - next-level-cache = <&l2>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x1>; - next-level-cache = <&l2>; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x2>; - next-level-cache = <&l2>; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x3>; - next-level-cache = <&l2>; - }; - - l2: l2-cache { - compatible = "cache"; - }; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - tee@10100000 { - reg = <0x10100000 0xf00000>; - no-map; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; -}; - -&arm_pmu { - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; -}; diff --git a/sys/gnu/dts/arm64/realtek/rtd1296-ds418.dts b/sys/gnu/dts/arm64/realtek/rtd1296-ds418.dts deleted file mode 100644 index 5a051a52bf8..00000000000 --- a/sys/gnu/dts/arm64/realtek/rtd1296-ds418.dts +++ /dev/null @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) -/* - * Copyright (c) 2017-2019 Andreas Färber - */ - -/dts-v1/; - -#include "rtd1296.dtsi" - -/ { - compatible = "synology,ds418", "realtek,rtd1296"; - model = "Synology DiskStation DS418"; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x80000000>; - }; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/realtek/rtd1296.dtsi b/sys/gnu/dts/arm64/realtek/rtd1296.dtsi deleted file mode 100644 index 0f9e59cac08..00000000000 --- a/sys/gnu/dts/arm64/realtek/rtd1296.dtsi +++ /dev/null @@ -1,65 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) -/* - * Realtek RTD1296 SoC - * - * Copyright (c) 2017-2019 Andreas Färber - */ - -#include "rtd129x.dtsi" - -/ { - compatible = "realtek,rtd1296"; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x0>; - next-level-cache = <&l2>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x1>; - next-level-cache = <&l2>; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x2>; - next-level-cache = <&l2>; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x3>; - next-level-cache = <&l2>; - }; - - l2: l2-cache { - compatible = "cache"; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; -}; - -&arm_pmu { - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; -}; diff --git a/sys/gnu/dts/arm64/realtek/rtd129x.dtsi b/sys/gnu/dts/arm64/realtek/rtd129x.dtsi deleted file mode 100644 index 4433114476f..00000000000 --- a/sys/gnu/dts/arm64/realtek/rtd129x.dtsi +++ /dev/null @@ -1,118 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) -/* - * Realtek RTD1293/RTD1295/RTD1296 SoC - * - * Copyright (c) 2016-2017 Andreas Färber - */ - -/memreserve/ 0x0000000000000000 0x0000000000030000; -/memreserve/ 0x000000000001f000 0x0000000000001000; -/memreserve/ 0x0000000000030000 0x00000000000d0000; -/memreserve/ 0x0000000001b00000 0x00000000004be000; -/memreserve/ 0x0000000001ffe000 0x0000000000004000; - -#include -#include - -/ { - interrupt-parent = <&gic>; - #address-cells = <1>; - #size-cells = <1>; - - arm_pmu: arm-pmu { - compatible = "arm,cortex-a53-pmu"; - interrupts = ; - }; - - osc27M: osc { - compatible = "fixed-clock"; - clock-frequency = <27000000>; - #clock-cells = <0>; - clock-output-names = "osc27M"; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - /* Exclude up to 2 GiB of RAM */ - ranges = <0x80000000 0x80000000 0x80000000>; - - reset1: reset-controller@98000000 { - compatible = "snps,dw-low-reset"; - reg = <0x98000000 0x4>; - #reset-cells = <1>; - }; - - reset2: reset-controller@98000004 { - compatible = "snps,dw-low-reset"; - reg = <0x98000004 0x4>; - #reset-cells = <1>; - }; - - reset3: reset-controller@98000008 { - compatible = "snps,dw-low-reset"; - reg = <0x98000008 0x4>; - #reset-cells = <1>; - }; - - reset4: reset-controller@98000050 { - compatible = "snps,dw-low-reset"; - reg = <0x98000050 0x4>; - #reset-cells = <1>; - }; - - iso_reset: reset-controller@98007088 { - compatible = "snps,dw-low-reset"; - reg = <0x98007088 0x4>; - #reset-cells = <1>; - }; - - wdt: watchdog@98007680 { - compatible = "realtek,rtd1295-watchdog"; - reg = <0x98007680 0x100>; - clocks = <&osc27M>; - }; - - uart0: serial@98007800 { - compatible = "snps,dw-apb-uart"; - reg = <0x98007800 0x400>; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <27000000>; - resets = <&iso_reset RTD1295_ISO_RSTN_UR0>; - status = "disabled"; - }; - - uart1: serial@9801b200 { - compatible = "snps,dw-apb-uart"; - reg = <0x9801b200 0x100>; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <432000000>; - resets = <&reset2 RTD1295_RSTN_UR1>; - status = "disabled"; - }; - - uart2: serial@9801b400 { - compatible = "snps,dw-apb-uart"; - reg = <0x9801b400 0x100>; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <432000000>; - resets = <&reset2 RTD1295_RSTN_UR2>; - status = "disabled"; - }; - - gic: interrupt-controller@ff011000 { - compatible = "arm,gic-400"; - reg = <0xff011000 0x1000>, - <0xff012000 0x2000>, - <0xff014000 0x2000>, - <0xff016000 0x2000>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <3>; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/renesas/cat875.dtsi b/sys/gnu/dts/arm64/renesas/cat875.dtsi deleted file mode 100644 index aaefc3ae56d..00000000000 --- a/sys/gnu/dts/arm64/renesas/cat875.dtsi +++ /dev/null @@ -1,66 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the Silicon Linux sub board for CAT874 (CAT875) - * - * Copyright (C) 2019 Renesas Electronics Corp. - */ - -/ { - model = "Silicon Linux sub board for CAT874 (CAT875)"; - - aliases { - ethernet0 = &avb; - }; -}; - -&avb { - pinctrl-0 = <&avb_pins>; - pinctrl-names = "default"; - renesas,no-ether-link; - phy-handle = <&phy0>; - phy-mode = "rgmii"; - status = "okay"; - - phy0: ethernet-phy@0 { - rxc-skew-ps = <1500>; - reg = <0>; - interrupt-parent = <&gpio2>; - interrupts = <21 IRQ_TYPE_LEVEL_LOW>; - reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; - }; -}; - -&can0 { - pinctrl-0 = <&can0_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&can1 { - pinctrl-0 = <&can1_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&pciec0 { - status = "okay"; -}; - -&pfc { - avb_pins: avb { - mux { - groups = "avb_mii"; - function = "avb"; - }; - }; - - can0_pins: can0 { - groups = "can0_data"; - function = "can0"; - }; - - can1_pins: can1 { - groups = "can1_data"; - function = "can1"; - }; -}; diff --git a/sys/gnu/dts/arm64/renesas/hihope-common.dtsi b/sys/gnu/dts/arm64/renesas/hihope-common.dtsi deleted file mode 100644 index bd056904e8b..00000000000 --- a/sys/gnu/dts/arm64/renesas/hihope-common.dtsi +++ /dev/null @@ -1,440 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the HiHope RZ/G2[MN] main board common parts - * - * Copyright (C) 2019 Renesas Electronics Corp. - */ - -#include - -/ { - aliases { - serial0 = &scif2; - serial1 = &hscif0; - }; - - chosen { - bootargs = "ignore_loglevel"; - stdout-path = "serial0:115200n8"; - }; - - hdmi0-out { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi0_con: endpoint { - remote-endpoint = <&rcar_dw_hdmi0_out>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - bt_active_led { - label = "blue:bt"; - gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "hci0-power"; - default-state = "off"; - }; - - led0 { - gpios = <&gpio6 11 GPIO_ACTIVE_HIGH>; - }; - - led1 { - gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>; - }; - - led2 { - gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>; - }; - - led3 { - gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>; - }; - - wlan_active_led { - label = "yellow:wlan"; - gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "phy0tx"; - default-state = "off"; - }; - }; - - reg_1p8v: regulator0 { - compatible = "regulator-fixed"; - regulator-name = "fixed-1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_3p3v: regulator1 { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - sound_card: sound { - compatible = "audio-graph-card"; - - label = "rcar-sound"; - - dais = <&rsnd_port>; - }; - - vbus0_usb2: regulator-vbus0-usb2 { - compatible = "regulator-fixed"; - - regulator-name = "USB20_VBUS0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - gpio = <&gpio6 16 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vccq_sdhi0: regulator-vccq-sdhi0 { - compatible = "regulator-gpio"; - - regulator-name = "SDHI0 VccQ"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio6 30 GPIO_ACTIVE_HIGH>; - gpios-states = <1>; - states = <3300000 1>, <1800000 0>; - }; - - wlan_en_reg: regulator-wlan_en { - compatible = "regulator-fixed"; - regulator-name = "wlan-en-regulator"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - startup-delay-us = <70000>; - - gpio = <&gpio_expander 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - x302_clk: x302-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <33000000>; - }; - - x304_clk: x304-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; -}; - -&audio_clk_a { - clock-frequency = <22579200>; -}; - -&du { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&extal_clk { - clock-frequency = <16666666>; -}; - -&extalr_clk { - clock-frequency = <32768>; -}; - -&gpio6 { - usb1-reset { - gpio-hog; - gpios = <10 GPIO_ACTIVE_LOW>; - output-low; - line-name = "usb1-reset"; - }; -}; - -&hdmi0 { - status = "okay"; - - ports { - port@1 { - reg = <1>; - rcar_dw_hdmi0_out: endpoint { - remote-endpoint = <&hdmi0_con>; - }; - }; - port@2 { - reg = <2>; - dw_hdmi0_snd_in: endpoint { - remote-endpoint = <&rsnd_endpoint>; - }; - }; - }; -}; - -&hscif0 { - pinctrl-0 = <&hscif0_pins>; - pinctrl-names = "default"; - - uart-has-rtscts; - status = "okay"; - - bluetooth { - compatible = "ti,wl1837-st"; - enable-gpios = <&gpio_expander 2 GPIO_ACTIVE_HIGH>; - }; -}; - -&hsusb { - dr_mode = "otg"; - status = "okay"; -}; - -&i2c4 { - clock-frequency = <400000>; - status = "okay"; - - gpio_expander: gpio@20 { - compatible = "onnn,pca9654"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - }; - - versaclock5: clock-generator@6a { - compatible = "idt,5p49v5923"; - reg = <0x6a>; - #clock-cells = <1>; - clocks = <&x304_clk>; - clock-names = "xin"; - }; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&pcie_bus_clk { - clock-frequency = <100000000>; -}; - -&pfc { - pinctrl-0 = <&scif_clk_pins>; - pinctrl-names = "default"; - - hscif0_pins: hscif0 { - groups = "hscif0_data", "hscif0_ctrl"; - function = "hscif0"; - }; - - scif2_pins: scif2 { - groups = "scif2_data_a"; - function = "scif2"; - }; - - scif_clk_pins: scif_clk { - groups = "scif_clk_a"; - function = "scif_clk"; - }; - - sdhi0_pins: sd0 { - groups = "sdhi0_data4", "sdhi0_ctrl"; - function = "sdhi0"; - power-source = <3300>; - }; - - sdhi0_pins_uhs: sd0_uhs { - groups = "sdhi0_data4", "sdhi0_ctrl"; - function = "sdhi0"; - power-source = <1800>; - }; - - sdhi2_pins: sd2 { - groups = "sdhi2_data4", "sdhi2_ctrl"; - function = "sdhi2"; - power-source = <1800>; - }; - - sdhi3_pins: sd3 { - groups = "sdhi3_data8", "sdhi3_ctrl", "sdhi3_ds"; - function = "sdhi3"; - power-source = <1800>; - }; - - sound_clk_pins: sound_clk { - groups = "audio_clk_a_a"; - function = "audio_clk"; - }; - - usb0_pins: usb0 { - groups = "usb0"; - function = "usb0"; - }; - - usb1_pins: usb1 { - mux { - groups = "usb1"; - function = "usb1"; - }; - - ovc { - pins = "GP_6_27"; - bias-pull-up; - }; - }; - - usb30_pins: usb30 { - groups = "usb30"; - function = "usb30"; - }; -}; - -&rcar_sound { - pinctrl-0 = <&sound_clk_pins>; - pinctrl-names = "default"; - - status = "okay"; - - /* Single DAI */ - #sound-dai-cells = <0>; - - rsnd_port: port { - rsnd_endpoint: endpoint { - remote-endpoint = <&dw_hdmi0_snd_in>; - - dai-format = "i2s"; - bitclock-master = <&rsnd_endpoint>; - frame-master = <&rsnd_endpoint>; - - playback = <&ssi2>; - }; - }; -}; - -&rwdt { - timeout-sec = <60>; - status = "okay"; -}; - -&scif2 { - pinctrl-0 = <&scif2_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&scif_clk { - clock-frequency = <14745600>; -}; - -&sdhi0 { - pinctrl-0 = <&sdhi0_pins>; - pinctrl-1 = <&sdhi0_pins_uhs>; - pinctrl-names = "default", "state_uhs"; - - vmmc-supply = <®_3p3v>; - vqmmc-supply = <&vccq_sdhi0>; - cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; - bus-width = <4>; - sd-uhs-sdr50; - sd-uhs-sdr104; - status = "okay"; -}; - -&sdhi2 { - status = "okay"; - pinctrl-0 = <&sdhi2_pins>; - pinctrl-names = "default"; - - vmmc-supply = <&wlan_en_reg>; - bus-width = <4>; - non-removable; - cap-power-off-card; - keep-power-in-suspend; - - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@2 { - compatible = "ti,wl1837"; - reg = <2>; - interrupt-parent = <&gpio2>; - interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; - }; -}; - -&sdhi3 { - pinctrl-0 = <&sdhi3_pins>; - pinctrl-1 = <&sdhi3_pins>; - pinctrl-names = "default", "state_uhs"; - - vmmc-supply = <®_3p3v>; - vqmmc-supply = <®_1p8v>; - bus-width = <8>; - mmc-hs200-1_8v; - non-removable; - fixed-emmc-driver-type = <1>; - status = "okay"; -}; - -&usb_extal_clk { - clock-frequency = <50000000>; -}; - -&usb2_phy0 { - pinctrl-0 = <&usb0_pins>; - pinctrl-names = "default"; - - vbus-supply = <&vbus0_usb2>; - status = "okay"; -}; - -&usb2_phy1 { - pinctrl-0 = <&usb1_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&usb3_peri0 { - phys = <&usb3_phy0>; - phy-names = "usb"; - - companion = <&xhci0>; - - status = "okay"; -}; - -&usb3_phy0 { - status = "okay"; -}; - -&usb3s0_clk { - clock-frequency = <100000000>; -}; - -&xhci0 { - pinctrl-0 = <&usb30_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/renesas/hihope-rzg2-ex.dtsi b/sys/gnu/dts/arm64/renesas/hihope-rzg2-ex.dtsi deleted file mode 100644 index 28fe17e3bc4..00000000000 --- a/sys/gnu/dts/arm64/renesas/hihope-rzg2-ex.dtsi +++ /dev/null @@ -1,130 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the RZ/G2[MN] HiHope sub board common parts - * - * Copyright (C) 2019 Renesas Electronics Corp. - */ - -/ { - aliases { - ethernet0 = &avb; - }; - - chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm0 0 50000>; - - brightness-levels = <0 2 8 16 32 64 128 255>; - default-brightness-level = <6>; - }; -}; - -&avb { - pinctrl-0 = <&avb_pins>; - pinctrl-names = "default"; - phy-handle = <&phy0>; - phy-mode = "rgmii-txid"; - status = "okay"; - - phy0: ethernet-phy@0 { - rxc-skew-ps = <1500>; - reg = <0>; - interrupt-parent = <&gpio2>; - interrupts = <11 IRQ_TYPE_LEVEL_LOW>; - reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; - }; -}; - -&can0 { - pinctrl-0 = <&can0_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&can1 { - pinctrl-0 = <&can1_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&gpio1 { - /* - * When GP1_20 is LOW LVDS0 is connected to the LVDS connector - * When GP1_20 is HIGH LVDS0 is connected to the LT8918L - */ - lvds-connector-en-gpio { - gpio-hog; - gpios = <20 GPIO_ACTIVE_HIGH>; - output-low; - line-name = "lvds-connector-en-gpio"; - }; -}; - -&lvds0 { - /* - * Please include the LVDS panel .dtsi file and uncomment the below line - * to enable LVDS panel connected to RZ/G2[MN] boards. - */ - - /* status = "okay"; */ - - ports { - port@1 { - lvds_connector: endpoint { - }; - }; - }; -}; - -&pciec0 { - status = "okay"; -}; - -&pfc { - pinctrl-0 = <&scif_clk_pins>; - pinctrl-names = "default"; - - avb_pins: avb { - mux { - groups = "avb_link", "avb_mdio", "avb_mii"; - function = "avb"; - }; - - pins_mdio { - groups = "avb_mdio"; - drive-strength = <24>; - }; - - pins_mii_tx { - pins = "PIN_AVB_TX_CTL", "PIN_AVB_TXC", "PIN_AVB_TD0", - "PIN_AVB_TD1", "PIN_AVB_TD2", "PIN_AVB_TD3"; - drive-strength = <12>; - }; - }; - - can0_pins: can0 { - groups = "can0_data_a"; - function = "can0"; - }; - - can1_pins: can1 { - groups = "can1_data"; - function = "can1"; - }; - - pwm0_pins: pwm0 { - groups = "pwm0"; - function = "pwm0"; - }; -}; - -&pwm0 { - pinctrl-0 = <&pwm0_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/renesas/r8a774a1-hihope-rzg2m-ex.dts b/sys/gnu/dts/arm64/renesas/r8a774a1-hihope-rzg2m-ex.dts deleted file mode 100644 index c754fca239d..00000000000 --- a/sys/gnu/dts/arm64/renesas/r8a774a1-hihope-rzg2m-ex.dts +++ /dev/null @@ -1,19 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the HiHope RZ/G2M sub board - * - * Copyright (C) 2019 Renesas Electronics Corp. - */ - -#include "r8a774a1-hihope-rzg2m.dts" -#include "hihope-rzg2-ex.dtsi" - -/ { - model = "HopeRun HiHope RZ/G2M with sub board"; - compatible = "hoperun,hihope-rzg2-ex", "hoperun,hihope-rzg2m", - "renesas,r8a774a1"; -}; - -&pciec1 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/renesas/r8a774a1-hihope-rzg2m.dts b/sys/gnu/dts/arm64/renesas/r8a774a1-hihope-rzg2m.dts deleted file mode 100644 index 96f2fb080a1..00000000000 --- a/sys/gnu/dts/arm64/renesas/r8a774a1-hihope-rzg2m.dts +++ /dev/null @@ -1,37 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the HiHope RZ/G2M main board - * - * Copyright (C) 2019 Renesas Electronics Corp. - */ - -/dts-v1/; -#include "r8a774a1.dtsi" -#include "hihope-common.dtsi" - -/ { - model = "HopeRun HiHope RZ/G2M main board based on r8a774a1"; - compatible = "hoperun,hihope-rzg2m", "renesas,r8a774a1"; - - memory@48000000 { - device_type = "memory"; - /* first 128MB is reserved for secure area. */ - reg = <0x0 0x48000000 0x0 0x78000000>; - }; - - memory@600000000 { - device_type = "memory"; - reg = <0x6 0x00000000 0x0 0x80000000>; - }; -}; - -&du { - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>, - <&cpg CPG_MOD 722>, - <&versaclock5 1>, - <&x302_clk>, - <&versaclock5 2>; - clock-names = "du.0", "du.1", "du.2", - "dclkin.0", "dclkin.1", "dclkin.2"; -}; diff --git a/sys/gnu/dts/arm64/renesas/r8a774a1.dtsi b/sys/gnu/dts/arm64/renesas/r8a774a1.dtsi deleted file mode 100644 index 8f950dabca5..00000000000 --- a/sys/gnu/dts/arm64/renesas/r8a774a1.dtsi +++ /dev/null @@ -1,2786 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the r8a774a1 SoC - * - * Copyright (C) 2018 Renesas Electronics Corp. - */ - -#include -#include -#include -#include - -/ { - compatible = "renesas,r8a774a1"; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - i2c6 = &i2c6; - i2c7 = &i2c_dvfs; - }; - - /* - * The external audio clocks are configured as 0 Hz fixed frequency - * clocks by default. - * Boards that provide audio clocks should override them. - */ - audio_clk_a: audio_clk_a { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - audio_clk_b: audio_clk_b { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - audio_clk_c: audio_clk_c { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - /* External CAN clock - to be overridden by boards that provide it */ - can_clk: can { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - cluster0_opp: opp_table0 { - compatible = "operating-points-v2"; - opp-shared; - - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <820000>; - clock-latency-ns = <300000>; - }; - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <820000>; - clock-latency-ns = <300000>; - }; - opp-1500000000 { - opp-hz = /bits/ 64 <1500000000>; - opp-microvolt = <820000>; - clock-latency-ns = <300000>; - }; - }; - - cluster1_opp: opp_table1 { - compatible = "operating-points-v2"; - opp-shared; - - opp-800000000 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <820000>; - clock-latency-ns = <300000>; - }; - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <820000>; - clock-latency-ns = <300000>; - }; - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <820000>; - clock-latency-ns = <300000>; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu-map { - cluster0 { - core0 { - cpu = <&a57_0>; - }; - core1 { - cpu = <&a57_1>; - }; - }; - - cluster1 { - core0 { - cpu = <&a53_0>; - }; - core1 { - cpu = <&a53_1>; - }; - core2 { - cpu = <&a53_2>; - }; - core3 { - cpu = <&a53_3>; - }; - }; - }; - - a57_0: cpu@0 { - compatible = "arm,cortex-a57"; - reg = <0x0>; - device_type = "cpu"; - power-domains = <&sysc R8A774A1_PD_CA57_CPU0>; - next-level-cache = <&L2_CA57>; - enable-method = "psci"; - dynamic-power-coefficient = <854>; - clocks = <&cpg CPG_CORE R8A774A1_CLK_Z>; - operating-points-v2 = <&cluster0_opp>; - capacity-dmips-mhz = <1024>; - #cooling-cells = <2>; - }; - - a57_1: cpu@1 { - compatible = "arm,cortex-a57"; - reg = <0x1>; - device_type = "cpu"; - power-domains = <&sysc R8A774A1_PD_CA57_CPU1>; - next-level-cache = <&L2_CA57>; - enable-method = "psci"; - clocks = <&cpg CPG_CORE R8A774A1_CLK_Z>; - operating-points-v2 = <&cluster0_opp>; - capacity-dmips-mhz = <1024>; - #cooling-cells = <2>; - }; - - a53_0: cpu@100 { - compatible = "arm,cortex-a53"; - reg = <0x100>; - device_type = "cpu"; - power-domains = <&sysc R8A774A1_PD_CA53_CPU0>; - next-level-cache = <&L2_CA53>; - enable-method = "psci"; - #cooling-cells = <2>; - dynamic-power-coefficient = <277>; - clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>; - operating-points-v2 = <&cluster1_opp>; - capacity-dmips-mhz = <560>; - }; - - a53_1: cpu@101 { - compatible = "arm,cortex-a53"; - reg = <0x101>; - device_type = "cpu"; - power-domains = <&sysc R8A774A1_PD_CA53_CPU1>; - next-level-cache = <&L2_CA53>; - enable-method = "psci"; - clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>; - operating-points-v2 = <&cluster1_opp>; - capacity-dmips-mhz = <560>; - }; - - a53_2: cpu@102 { - compatible = "arm,cortex-a53"; - reg = <0x102>; - device_type = "cpu"; - power-domains = <&sysc R8A774A1_PD_CA53_CPU2>; - next-level-cache = <&L2_CA53>; - enable-method = "psci"; - clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>; - operating-points-v2 = <&cluster1_opp>; - capacity-dmips-mhz = <560>; - }; - - a53_3: cpu@103 { - compatible = "arm,cortex-a53"; - reg = <0x103>; - device_type = "cpu"; - power-domains = <&sysc R8A774A1_PD_CA53_CPU3>; - next-level-cache = <&L2_CA53>; - enable-method = "psci"; - clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>; - operating-points-v2 = <&cluster1_opp>; - capacity-dmips-mhz = <560>; - }; - - L2_CA57: cache-controller-0 { - compatible = "cache"; - power-domains = <&sysc R8A774A1_PD_CA57_SCU>; - cache-unified; - cache-level = <2>; - }; - - L2_CA53: cache-controller-1 { - compatible = "cache"; - power-domains = <&sysc R8A774A1_PD_CA53_SCU>; - cache-unified; - cache-level = <2>; - }; - }; - - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board */ - clock-frequency = <0>; - }; - - extalr_clk: extalr { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board */ - clock-frequency = <0>; - }; - - /* External PCIe clock - can be overridden by the board */ - pcie_bus_clk: pcie_bus { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - pmu_a53 { - compatible = "arm,cortex-a53-pmu"; - interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>; - }; - - pmu_a57 { - compatible = "arm,cortex-a57-pmu"; - interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&a57_0>, <&a57_1>; - }; - - psci { - compatible = "arm,psci-1.0", "arm,psci-0.2"; - method = "smc"; - }; - - /* External SCIF clock - to be overridden by boards that provide it */ - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - soc { - compatible = "simple-bus"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - rwdt: watchdog@e6020000 { - compatible = "renesas,r8a774a1-wdt", - "renesas,rcar-gen3-wdt"; - reg = <0 0xe6020000 0 0x0c>; - clocks = <&cpg CPG_MOD 402>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 402>; - status = "disabled"; - }; - - gpio0: gpio@e6050000 { - compatible = "renesas,gpio-r8a774a1", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6050000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 0 16>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 912>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 912>; - }; - - gpio1: gpio@e6051000 { - compatible = "renesas,gpio-r8a774a1", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6051000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 32 29>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 911>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 911>; - }; - - gpio2: gpio@e6052000 { - compatible = "renesas,gpio-r8a774a1", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6052000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 64 15>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 910>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 910>; - }; - - gpio3: gpio@e6053000 { - compatible = "renesas,gpio-r8a774a1", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6053000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 96 16>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 909>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 909>; - }; - - gpio4: gpio@e6054000 { - compatible = "renesas,gpio-r8a774a1", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6054000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 128 18>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 908>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 908>; - }; - - gpio5: gpio@e6055000 { - compatible = "renesas,gpio-r8a774a1", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6055000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 160 26>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 907>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 907>; - }; - - gpio6: gpio@e6055400 { - compatible = "renesas,gpio-r8a774a1", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6055400 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 192 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 906>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 906>; - }; - - gpio7: gpio@e6055800 { - compatible = "renesas,gpio-r8a774a1", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6055800 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 224 4>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 905>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 905>; - }; - - pfc: pin-controller@e6060000 { - compatible = "renesas,pfc-r8a774a1"; - reg = <0 0xe6060000 0 0x50c>; - }; - - cmt0: timer@e60f0000 { - compatible = "renesas,r8a774a1-cmt0", - "renesas,rcar-gen3-cmt0"; - reg = <0 0xe60f0000 0 0x1004>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 303>; - clock-names = "fck"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 303>; - status = "disabled"; - }; - - cmt1: timer@e6130000 { - compatible = "renesas,r8a774a1-cmt1", - "renesas,rcar-gen3-cmt1"; - reg = <0 0xe6130000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 302>; - clock-names = "fck"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 302>; - status = "disabled"; - }; - - cmt2: timer@e6140000 { - compatible = "renesas,r8a774a1-cmt1", - "renesas,rcar-gen3-cmt1"; - reg = <0 0xe6140000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 301>; - clock-names = "fck"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 301>; - status = "disabled"; - }; - - cmt3: timer@e6148000 { - compatible = "renesas,r8a774a1-cmt1", - "renesas,rcar-gen3-cmt1"; - reg = <0 0xe6148000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 300>; - clock-names = "fck"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 300>; - status = "disabled"; - }; - - cpg: clock-controller@e6150000 { - compatible = "renesas,r8a774a1-cpg-mssr"; - reg = <0 0xe6150000 0 0x0bb0>; - clocks = <&extal_clk>, <&extalr_clk>; - clock-names = "extal", "extalr"; - #clock-cells = <2>; - #power-domain-cells = <0>; - #reset-cells = <1>; - }; - - rst: reset-controller@e6160000 { - compatible = "renesas,r8a774a1-rst"; - reg = <0 0xe6160000 0 0x018c>; - }; - - sysc: system-controller@e6180000 { - compatible = "renesas,r8a774a1-sysc"; - reg = <0 0xe6180000 0 0x0400>; - #power-domain-cells = <1>; - }; - - tsc: thermal@e6198000 { - compatible = "renesas,r8a774a1-thermal"; - reg = <0 0xe6198000 0 0x100>, - <0 0xe61a0000 0 0x100>, - <0 0xe61a8000 0 0x100>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 522>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 522>; - #thermal-sensor-cells = <1>; - }; - - intc_ex: interrupt-controller@e61c0000 { - compatible = "renesas,intc-ex-r8a774a1", "renesas,irqc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0 0xe61c0000 0 0x200>; - interrupts = , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 407>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 407>; - }; - - tmu0: timer@e61e0000 { - compatible = "renesas,tmu-r8a774a1", "renesas,tmu"; - reg = <0 0xe61e0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 125>; - clock-names = "fck"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 125>; - status = "disabled"; - }; - - tmu1: timer@e6fc0000 { - compatible = "renesas,tmu-r8a774a1", "renesas,tmu"; - reg = <0 0xe6fc0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 124>; - clock-names = "fck"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 124>; - status = "disabled"; - }; - - tmu2: timer@e6fd0000 { - compatible = "renesas,tmu-r8a774a1", "renesas,tmu"; - reg = <0 0xe6fd0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 123>; - clock-names = "fck"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 123>; - status = "disabled"; - }; - - tmu3: timer@e6fe0000 { - compatible = "renesas,tmu-r8a774a1", "renesas,tmu"; - reg = <0 0xe6fe0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 122>; - clock-names = "fck"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 122>; - status = "disabled"; - }; - - tmu4: timer@ffc00000 { - compatible = "renesas,tmu-r8a774a1", "renesas,tmu"; - reg = <0 0xffc00000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 121>; - clock-names = "fck"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 121>; - status = "disabled"; - }; - - i2c0: i2c@e6500000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a774a1", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6500000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 931>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 931>; - dmas = <&dmac1 0x91>, <&dmac1 0x90>, - <&dmac2 0x91>, <&dmac2 0x90>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c1: i2c@e6508000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a774a1", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6508000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 930>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 930>; - dmas = <&dmac1 0x93>, <&dmac1 0x92>, - <&dmac2 0x93>, <&dmac2 0x92>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c2: i2c@e6510000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a774a1", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6510000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 929>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 929>; - dmas = <&dmac1 0x95>, <&dmac1 0x94>, - <&dmac2 0x95>, <&dmac2 0x94>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c3: i2c@e66d0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a774a1", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66d0000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 928>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 928>; - dmas = <&dmac0 0x97>, <&dmac0 0x96>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c4: i2c@e66d8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a774a1", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66d8000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 927>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 927>; - dmas = <&dmac0 0x99>, <&dmac0 0x98>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c5: i2c@e66e0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a774a1", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66e0000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 919>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 919>; - dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c6: i2c@e66e8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a774a1", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66e8000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 918>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 918>; - dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c_dvfs: i2c@e60b0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a774a1", - "renesas,rcar-gen3-iic", - "renesas,rmobile-iic"; - reg = <0 0xe60b0000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 926>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 926>; - dmas = <&dmac0 0x11>, <&dmac0 0x10>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - hscif0: serial@e6540000 { - compatible = "renesas,hscif-r8a774a1", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6540000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 520>, - <&cpg CPG_CORE R8A774A1_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x31>, <&dmac1 0x30>, - <&dmac2 0x31>, <&dmac2 0x30>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 520>; - status = "disabled"; - }; - - hscif1: serial@e6550000 { - compatible = "renesas,hscif-r8a774a1", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6550000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 519>, - <&cpg CPG_CORE R8A774A1_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x33>, <&dmac1 0x32>, - <&dmac2 0x33>, <&dmac2 0x32>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 519>; - status = "disabled"; - }; - - hscif2: serial@e6560000 { - compatible = "renesas,hscif-r8a774a1", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6560000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 518>, - <&cpg CPG_CORE R8A774A1_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x35>, <&dmac1 0x34>, - <&dmac2 0x35>, <&dmac2 0x34>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 518>; - status = "disabled"; - }; - - hscif3: serial@e66a0000 { - compatible = "renesas,hscif-r8a774a1", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe66a0000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 517>, - <&cpg CPG_CORE R8A774A1_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x37>, <&dmac0 0x36>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 517>; - status = "disabled"; - }; - - hscif4: serial@e66b0000 { - compatible = "renesas,hscif-r8a774a1", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe66b0000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 516>, - <&cpg CPG_CORE R8A774A1_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x39>, <&dmac0 0x38>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 516>; - status = "disabled"; - }; - - hsusb: usb@e6590000 { - compatible = "renesas,usbhs-r8a774a1", - "renesas,rcar-gen3-usbhs"; - reg = <0 0xe6590000 0 0x200>; - interrupts = ; - clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>; - dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, - <&usb_dmac1 0>, <&usb_dmac1 1>; - dma-names = "ch0", "ch1", "ch2", "ch3"; - renesas,buswait = <11>; - phys = <&usb2_phy0 3>; - phy-names = "usb"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 704>, <&cpg 703>; - status = "disabled"; - }; - - usb_dmac0: dma-controller@e65a0000 { - compatible = "renesas,r8a774a1-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65a0000 0 0x100>; - interrupts = , - ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 330>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 330>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - usb_dmac1: dma-controller@e65b0000 { - compatible = "renesas,r8a774a1-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65b0000 0 0x100>; - interrupts = , - ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 331>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 331>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - usb3_phy0: usb-phy@e65ee000 { - compatible = "renesas,r8a774a1-usb3-phy", - "renesas,rcar-gen3-usb3-phy"; - reg = <0 0xe65ee000 0 0x90>; - clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, - <&usb_extal_clk>; - clock-names = "usb3-if", "usb3s_clk", "usb_extal"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 328>; - #phy-cells = <0>; - status = "disabled"; - }; - - dmac0: dma-controller@e6700000 { - compatible = "renesas,dmac-r8a774a1", - "renesas,rcar-dmac"; - reg = <0 0xe6700000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 219>; - clock-names = "fck"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 219>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, - <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, - <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, - <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, - <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, - <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, - <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, - <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; - }; - - dmac1: dma-controller@e7300000 { - compatible = "renesas,dmac-r8a774a1", - "renesas,rcar-dmac"; - reg = <0 0xe7300000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 218>; - clock-names = "fck"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 218>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, - <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, - <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, - <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, - <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, - <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, - <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, - <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; - }; - - dmac2: dma-controller@e7310000 { - compatible = "renesas,dmac-r8a774a1", - "renesas,rcar-dmac"; - reg = <0 0xe7310000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 217>; - clock-names = "fck"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 217>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, - <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, - <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, - <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, - <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, - <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, - <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, - <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; - }; - - ipmmu_ds0: mmu@e6740000 { - compatible = "renesas,ipmmu-r8a774a1"; - reg = <0 0xe6740000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 0>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_ds1: mmu@e7740000 { - compatible = "renesas,ipmmu-r8a774a1"; - reg = <0 0xe7740000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 1>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_hc: mmu@e6570000 { - compatible = "renesas,ipmmu-r8a774a1"; - reg = <0 0xe6570000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 2>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_mm: mmu@e67b0000 { - compatible = "renesas,ipmmu-r8a774a1"; - reg = <0 0xe67b0000 0 0x1000>; - interrupts = , - ; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_mp: mmu@ec670000 { - compatible = "renesas,ipmmu-r8a774a1"; - reg = <0 0xec670000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 4>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_pv0: mmu@fd800000 { - compatible = "renesas,ipmmu-r8a774a1"; - reg = <0 0xfd800000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 5>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_pv1: mmu@fd950000 { - compatible = "renesas,ipmmu-r8a774a1"; - reg = <0 0xfd950000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 6>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_vc0: mmu@fe6b0000 { - compatible = "renesas,ipmmu-r8a774a1"; - reg = <0 0xfe6b0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 8>; - power-domains = <&sysc R8A774A1_PD_A3VC>; - #iommu-cells = <1>; - }; - - ipmmu_vi0: mmu@febd0000 { - compatible = "renesas,ipmmu-r8a774a1"; - reg = <0 0xfebd0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 9>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - avb: ethernet@e6800000 { - compatible = "renesas,etheravb-r8a774a1", - "renesas,etheravb-rcar-gen3"; - reg = <0 0xe6800000 0 0x800>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15", - "ch16", "ch17", "ch18", "ch19", - "ch20", "ch21", "ch22", "ch23", - "ch24"; - clocks = <&cpg CPG_MOD 812>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 812>; - phy-mode = "rgmii"; - iommus = <&ipmmu_ds0 16>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - can0: can@e6c30000 { - compatible = "renesas,can-r8a774a1", - "renesas,rcar-gen3-can"; - reg = <0 0xe6c30000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 916>, - <&cpg CPG_CORE R8A774A1_CLK_CANFD>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A774A1_CLK_CANFD>; - assigned-clock-rates = <40000000>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 916>; - status = "disabled"; - }; - - can1: can@e6c38000 { - compatible = "renesas,can-r8a774a1", - "renesas,rcar-gen3-can"; - reg = <0 0xe6c38000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 915>, - <&cpg CPG_CORE R8A774A1_CLK_CANFD>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A774A1_CLK_CANFD>; - assigned-clock-rates = <40000000>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 915>; - status = "disabled"; - }; - - canfd: can@e66c0000 { - compatible = "renesas,r8a774a1-canfd", - "renesas,rcar-gen3-canfd"; - reg = <0 0xe66c0000 0 0x8000>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 914>, - <&cpg CPG_CORE R8A774A1_CLK_CANFD>, - <&can_clk>; - clock-names = "fck", "canfd", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A774A1_CLK_CANFD>; - assigned-clock-rates = <40000000>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 914>; - status = "disabled"; - - channel0 { - status = "disabled"; - }; - - channel1 { - status = "disabled"; - }; - }; - - pwm0: pwm@e6e30000 { - compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; - reg = <0 0xe6e30000 0 0x8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pwm1: pwm@e6e31000 { - compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; - reg = <0 0xe6e31000 0 0x8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pwm2: pwm@e6e32000 { - compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; - reg = <0 0xe6e32000 0 0x8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pwm3: pwm@e6e33000 { - compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; - reg = <0 0xe6e33000 0 0x8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pwm4: pwm@e6e34000 { - compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; - reg = <0 0xe6e34000 0 0x8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pwm5: pwm@e6e35000 { - compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; - reg = <0 0xe6e35000 0 0x8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pwm6: pwm@e6e36000 { - compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; - reg = <0 0xe6e36000 0 0x8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - status = "disabled"; - }; - - scif0: serial@e6e60000 { - compatible = "renesas,scif-r8a774a1", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e60000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 207>, - <&cpg CPG_CORE R8A774A1_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x51>, <&dmac1 0x50>, - <&dmac2 0x51>, <&dmac2 0x50>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 207>; - status = "disabled"; - }; - - scif1: serial@e6e68000 { - compatible = "renesas,scif-r8a774a1", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e68000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 206>, - <&cpg CPG_CORE R8A774A1_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x53>, <&dmac1 0x52>, - <&dmac2 0x53>, <&dmac2 0x52>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 206>; - status = "disabled"; - }; - - scif2: serial@e6e88000 { - compatible = "renesas,scif-r8a774a1", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e88000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 310>, - <&cpg CPG_CORE R8A774A1_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x13>, <&dmac1 0x12>, - <&dmac2 0x13>, <&dmac2 0x12>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 310>; - status = "disabled"; - }; - - scif3: serial@e6c50000 { - compatible = "renesas,scif-r8a774a1", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6c50000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 204>, - <&cpg CPG_CORE R8A774A1_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x57>, <&dmac0 0x56>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 204>; - status = "disabled"; - }; - - scif4: serial@e6c40000 { - compatible = "renesas,scif-r8a774a1", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6c40000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 203>, - <&cpg CPG_CORE R8A774A1_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x59>, <&dmac0 0x58>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 203>; - status = "disabled"; - }; - - scif5: serial@e6f30000 { - compatible = "renesas,scif-r8a774a1", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6f30000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 202>, - <&cpg CPG_CORE R8A774A1_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, - <&dmac2 0x5b>, <&dmac2 0x5a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 202>; - status = "disabled"; - }; - - msiof0: spi@e6e90000 { - compatible = "renesas,msiof-r8a774a1", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6e90000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 211>; - dmas = <&dmac1 0x41>, <&dmac1 0x40>, - <&dmac2 0x41>, <&dmac2 0x40>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 211>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof1: spi@e6ea0000 { - compatible = "renesas,msiof-r8a774a1", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6ea0000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 210>; - dmas = <&dmac1 0x43>, <&dmac1 0x42>, - <&dmac2 0x43>, <&dmac2 0x42>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 210>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof2: spi@e6c00000 { - compatible = "renesas,msiof-r8a774a1", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6c00000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 209>; - dmas = <&dmac0 0x45>, <&dmac0 0x44>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 209>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof3: spi@e6c10000 { - compatible = "renesas,msiof-r8a774a1", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6c10000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 208>; - dmas = <&dmac0 0x47>, <&dmac0 0x46>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 208>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - vin0: video@e6ef0000 { - compatible = "renesas,vin-r8a774a1"; - reg = <0 0xe6ef0000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 811>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 811>; - renesas,id = <0>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin0csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin0>; - }; - vin0csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin0>; - }; - }; - }; - }; - - vin1: video@e6ef1000 { - compatible = "renesas,vin-r8a774a1"; - reg = <0 0xe6ef1000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 810>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 810>; - renesas,id = <1>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin1csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin1>; - }; - vin1csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin1>; - }; - }; - }; - }; - - vin2: video@e6ef2000 { - compatible = "renesas,vin-r8a774a1"; - reg = <0 0xe6ef2000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 809>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 809>; - renesas,id = <2>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin2csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin2>; - }; - vin2csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin2>; - }; - }; - }; - }; - - vin3: video@e6ef3000 { - compatible = "renesas,vin-r8a774a1"; - reg = <0 0xe6ef3000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 808>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 808>; - renesas,id = <3>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin3csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin3>; - }; - vin3csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin3>; - }; - }; - }; - }; - - vin4: video@e6ef4000 { - compatible = "renesas,vin-r8a774a1"; - reg = <0 0xe6ef4000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 807>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 807>; - renesas,id = <4>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin4csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin4>; - }; - vin4csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin4>; - }; - }; - }; - }; - - vin5: video@e6ef5000 { - compatible = "renesas,vin-r8a774a1"; - reg = <0 0xe6ef5000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 806>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 806>; - renesas,id = <5>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin5csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin5>; - }; - vin5csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin5>; - }; - }; - }; - }; - - vin6: video@e6ef6000 { - compatible = "renesas,vin-r8a774a1"; - reg = <0 0xe6ef6000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 805>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 805>; - renesas,id = <6>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin6csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin6>; - }; - vin6csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin6>; - }; - }; - }; - }; - - vin7: video@e6ef7000 { - compatible = "renesas,vin-r8a774a1"; - reg = <0 0xe6ef7000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 804>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 804>; - renesas,id = <7>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin7csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin7>; - }; - vin7csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin7>; - }; - }; - }; - }; - - rcar_sound: sound@ec500000 { - /* - * #sound-dai-cells is required - * - * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; - * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; - */ - /* - * #clock-cells is required for audio_clkout0/1/2/3 - * - * clkout : #clock-cells = <0>; <&rcar_sound>; - * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; - */ - compatible = "renesas,rcar_sound-r8a774a1", "renesas,rcar_sound-gen3"; - reg = <0 0xec500000 0 0x1000>, /* SCU */ - <0 0xec5a0000 0 0x100>, /* ADG */ - <0 0xec540000 0 0x1000>, /* SSIU */ - <0 0xec541000 0 0x280>, /* SSI */ - <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ - reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; - - clocks = <&cpg CPG_MOD 1005>, - <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, - <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, - <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, - <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, - <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, - <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, - <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, - <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, - <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, - <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, - <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, - <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, - <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, - <&audio_clk_a>, <&audio_clk_b>, - <&audio_clk_c>, - <&cpg CPG_CORE R8A774A1_CLK_S0D4>; - clock-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", - "ssi.5", "ssi.4", "ssi.3", "ssi.2", - "ssi.1", "ssi.0", - "src.9", "src.8", "src.7", "src.6", - "src.5", "src.4", "src.3", "src.2", - "src.1", "src.0", - "mix.1", "mix.0", - "ctu.1", "ctu.0", - "dvc.0", "dvc.1", - "clk_a", "clk_b", "clk_c", "clk_i"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 1005>, - <&cpg 1006>, <&cpg 1007>, - <&cpg 1008>, <&cpg 1009>, - <&cpg 1010>, <&cpg 1011>, - <&cpg 1012>, <&cpg 1013>, - <&cpg 1014>, <&cpg 1015>; - reset-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", - "ssi.5", "ssi.4", "ssi.3", "ssi.2", - "ssi.1", "ssi.0"; - status = "disabled"; - - rcar_sound,ctu { - ctu00: ctu-0 { }; - ctu01: ctu-1 { }; - ctu02: ctu-2 { }; - ctu03: ctu-3 { }; - ctu10: ctu-4 { }; - ctu11: ctu-5 { }; - ctu12: ctu-6 { }; - ctu13: ctu-7 { }; - }; - - rcar_sound,dvc { - dvc0: dvc-0 { - dmas = <&audma1 0xbc>; - dma-names = "tx"; - }; - dvc1: dvc-1 { - dmas = <&audma1 0xbe>; - dma-names = "tx"; - }; - }; - - rcar_sound,mix { - mix0: mix-0 { }; - mix1: mix-1 { }; - }; - - rcar_sound,src { - src0: src-0 { - interrupts = ; - dmas = <&audma0 0x85>, <&audma1 0x9a>; - dma-names = "rx", "tx"; - }; - src1: src-1 { - interrupts = ; - dmas = <&audma0 0x87>, <&audma1 0x9c>; - dma-names = "rx", "tx"; - }; - src2: src-2 { - interrupts = ; - dmas = <&audma0 0x89>, <&audma1 0x9e>; - dma-names = "rx", "tx"; - }; - src3: src-3 { - interrupts = ; - dmas = <&audma0 0x8b>, <&audma1 0xa0>; - dma-names = "rx", "tx"; - }; - src4: src-4 { - interrupts = ; - dmas = <&audma0 0x8d>, <&audma1 0xb0>; - dma-names = "rx", "tx"; - }; - src5: src-5 { - interrupts = ; - dmas = <&audma0 0x8f>, <&audma1 0xb2>; - dma-names = "rx", "tx"; - }; - src6: src-6 { - interrupts = ; - dmas = <&audma0 0x91>, <&audma1 0xb4>; - dma-names = "rx", "tx"; - }; - src7: src-7 { - interrupts = ; - dmas = <&audma0 0x93>, <&audma1 0xb6>; - dma-names = "rx", "tx"; - }; - src8: src-8 { - interrupts = ; - dmas = <&audma0 0x95>, <&audma1 0xb8>; - dma-names = "rx", "tx"; - }; - src9: src-9 { - interrupts = ; - dmas = <&audma0 0x97>, <&audma1 0xba>; - dma-names = "rx", "tx"; - }; - }; - - rcar_sound,ssi { - ssi0: ssi-0 { - interrupts = ; - dmas = <&audma0 0x01>, <&audma1 0x02>; - dma-names = "rx", "tx"; - }; - ssi1: ssi-1 { - interrupts = ; - dmas = <&audma0 0x03>, <&audma1 0x04>; - dma-names = "rx", "tx"; - }; - ssi2: ssi-2 { - interrupts = ; - dmas = <&audma0 0x05>, <&audma1 0x06>; - dma-names = "rx", "tx"; - }; - ssi3: ssi-3 { - interrupts = ; - dmas = <&audma0 0x07>, <&audma1 0x08>; - dma-names = "rx", "tx"; - }; - ssi4: ssi-4 { - interrupts = ; - dmas = <&audma0 0x09>, <&audma1 0x0a>; - dma-names = "rx", "tx"; - }; - ssi5: ssi-5 { - interrupts = ; - dmas = <&audma0 0x0b>, <&audma1 0x0c>; - dma-names = "rx", "tx"; - }; - ssi6: ssi-6 { - interrupts = ; - dmas = <&audma0 0x0d>, <&audma1 0x0e>; - dma-names = "rx", "tx"; - }; - ssi7: ssi-7 { - interrupts = ; - dmas = <&audma0 0x0f>, <&audma1 0x10>; - dma-names = "rx", "tx"; - }; - ssi8: ssi-8 { - interrupts = ; - dmas = <&audma0 0x11>, <&audma1 0x12>; - dma-names = "rx", "tx"; - }; - ssi9: ssi-9 { - interrupts = ; - dmas = <&audma0 0x13>, <&audma1 0x14>; - dma-names = "rx", "tx"; - }; - }; - - rcar_sound,ssiu { - ssiu00: ssiu-0 { - dmas = <&audma0 0x15>, <&audma1 0x16>; - dma-names = "rx", "tx"; - }; - ssiu01: ssiu-1 { - dmas = <&audma0 0x35>, <&audma1 0x36>; - dma-names = "rx", "tx"; - }; - ssiu02: ssiu-2 { - dmas = <&audma0 0x37>, <&audma1 0x38>; - dma-names = "rx", "tx"; - }; - ssiu03: ssiu-3 { - dmas = <&audma0 0x47>, <&audma1 0x48>; - dma-names = "rx", "tx"; - }; - ssiu04: ssiu-4 { - dmas = <&audma0 0x3F>, <&audma1 0x40>; - dma-names = "rx", "tx"; - }; - ssiu05: ssiu-5 { - dmas = <&audma0 0x43>, <&audma1 0x44>; - dma-names = "rx", "tx"; - }; - ssiu06: ssiu-6 { - dmas = <&audma0 0x4F>, <&audma1 0x50>; - dma-names = "rx", "tx"; - }; - ssiu07: ssiu-7 { - dmas = <&audma0 0x53>, <&audma1 0x54>; - dma-names = "rx", "tx"; - }; - ssiu10: ssiu-8 { - dmas = <&audma0 0x49>, <&audma1 0x4a>; - dma-names = "rx", "tx"; - }; - ssiu11: ssiu-9 { - dmas = <&audma0 0x4B>, <&audma1 0x4C>; - dma-names = "rx", "tx"; - }; - ssiu12: ssiu-10 { - dmas = <&audma0 0x57>, <&audma1 0x58>; - dma-names = "rx", "tx"; - }; - ssiu13: ssiu-11 { - dmas = <&audma0 0x59>, <&audma1 0x5A>; - dma-names = "rx", "tx"; - }; - ssiu14: ssiu-12 { - dmas = <&audma0 0x5F>, <&audma1 0x60>; - dma-names = "rx", "tx"; - }; - ssiu15: ssiu-13 { - dmas = <&audma0 0xC3>, <&audma1 0xC4>; - dma-names = "rx", "tx"; - }; - ssiu16: ssiu-14 { - dmas = <&audma0 0xC7>, <&audma1 0xC8>; - dma-names = "rx", "tx"; - }; - ssiu17: ssiu-15 { - dmas = <&audma0 0xCB>, <&audma1 0xCC>; - dma-names = "rx", "tx"; - }; - ssiu20: ssiu-16 { - dmas = <&audma0 0x63>, <&audma1 0x64>; - dma-names = "rx", "tx"; - }; - ssiu21: ssiu-17 { - dmas = <&audma0 0x67>, <&audma1 0x68>; - dma-names = "rx", "tx"; - }; - ssiu22: ssiu-18 { - dmas = <&audma0 0x6B>, <&audma1 0x6C>; - dma-names = "rx", "tx"; - }; - ssiu23: ssiu-19 { - dmas = <&audma0 0x6D>, <&audma1 0x6E>; - dma-names = "rx", "tx"; - }; - ssiu24: ssiu-20 { - dmas = <&audma0 0xCF>, <&audma1 0xCE>; - dma-names = "rx", "tx"; - }; - ssiu25: ssiu-21 { - dmas = <&audma0 0xEB>, <&audma1 0xEC>; - dma-names = "rx", "tx"; - }; - ssiu26: ssiu-22 { - dmas = <&audma0 0xED>, <&audma1 0xEE>; - dma-names = "rx", "tx"; - }; - ssiu27: ssiu-23 { - dmas = <&audma0 0xEF>, <&audma1 0xF0>; - dma-names = "rx", "tx"; - }; - ssiu30: ssiu-24 { - dmas = <&audma0 0x6f>, <&audma1 0x70>; - dma-names = "rx", "tx"; - }; - ssiu31: ssiu-25 { - dmas = <&audma0 0x21>, <&audma1 0x22>; - dma-names = "rx", "tx"; - }; - ssiu32: ssiu-26 { - dmas = <&audma0 0x23>, <&audma1 0x24>; - dma-names = "rx", "tx"; - }; - ssiu33: ssiu-27 { - dmas = <&audma0 0x25>, <&audma1 0x26>; - dma-names = "rx", "tx"; - }; - ssiu34: ssiu-28 { - dmas = <&audma0 0x27>, <&audma1 0x28>; - dma-names = "rx", "tx"; - }; - ssiu35: ssiu-29 { - dmas = <&audma0 0x29>, <&audma1 0x2A>; - dma-names = "rx", "tx"; - }; - ssiu36: ssiu-30 { - dmas = <&audma0 0x2B>, <&audma1 0x2C>; - dma-names = "rx", "tx"; - }; - ssiu37: ssiu-31 { - dmas = <&audma0 0x2D>, <&audma1 0x2E>; - dma-names = "rx", "tx"; - }; - ssiu40: ssiu-32 { - dmas = <&audma0 0x71>, <&audma1 0x72>; - dma-names = "rx", "tx"; - }; - ssiu41: ssiu-33 { - dmas = <&audma0 0x17>, <&audma1 0x18>; - dma-names = "rx", "tx"; - }; - ssiu42: ssiu-34 { - dmas = <&audma0 0x19>, <&audma1 0x1A>; - dma-names = "rx", "tx"; - }; - ssiu43: ssiu-35 { - dmas = <&audma0 0x1B>, <&audma1 0x1C>; - dma-names = "rx", "tx"; - }; - ssiu44: ssiu-36 { - dmas = <&audma0 0x1D>, <&audma1 0x1E>; - dma-names = "rx", "tx"; - }; - ssiu45: ssiu-37 { - dmas = <&audma0 0x1F>, <&audma1 0x20>; - dma-names = "rx", "tx"; - }; - ssiu46: ssiu-38 { - dmas = <&audma0 0x31>, <&audma1 0x32>; - dma-names = "rx", "tx"; - }; - ssiu47: ssiu-39 { - dmas = <&audma0 0x33>, <&audma1 0x34>; - dma-names = "rx", "tx"; - }; - ssiu50: ssiu-40 { - dmas = <&audma0 0x73>, <&audma1 0x74>; - dma-names = "rx", "tx"; - }; - ssiu60: ssiu-41 { - dmas = <&audma0 0x75>, <&audma1 0x76>; - dma-names = "rx", "tx"; - }; - ssiu70: ssiu-42 { - dmas = <&audma0 0x79>, <&audma1 0x7a>; - dma-names = "rx", "tx"; - }; - ssiu80: ssiu-43 { - dmas = <&audma0 0x7b>, <&audma1 0x7c>; - dma-names = "rx", "tx"; - }; - ssiu90: ssiu-44 { - dmas = <&audma0 0x7d>, <&audma1 0x7e>; - dma-names = "rx", "tx"; - }; - ssiu91: ssiu-45 { - dmas = <&audma0 0x7F>, <&audma1 0x80>; - dma-names = "rx", "tx"; - }; - ssiu92: ssiu-46 { - dmas = <&audma0 0x81>, <&audma1 0x82>; - dma-names = "rx", "tx"; - }; - ssiu93: ssiu-47 { - dmas = <&audma0 0x83>, <&audma1 0x84>; - dma-names = "rx", "tx"; - }; - ssiu94: ssiu-48 { - dmas = <&audma0 0xA3>, <&audma1 0xA4>; - dma-names = "rx", "tx"; - }; - ssiu95: ssiu-49 { - dmas = <&audma0 0xA5>, <&audma1 0xA6>; - dma-names = "rx", "tx"; - }; - ssiu96: ssiu-50 { - dmas = <&audma0 0xA7>, <&audma1 0xA8>; - dma-names = "rx", "tx"; - }; - ssiu97: ssiu-51 { - dmas = <&audma0 0xA9>, <&audma1 0xAA>; - dma-names = "rx", "tx"; - }; - }; - }; - - audma0: dma-controller@ec700000 { - compatible = "renesas,dmac-r8a774a1", - "renesas,rcar-dmac"; - reg = <0 0xec700000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 502>; - clock-names = "fck"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 502>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>, - <&ipmmu_mp 2>, <&ipmmu_mp 3>, - <&ipmmu_mp 4>, <&ipmmu_mp 5>, - <&ipmmu_mp 6>, <&ipmmu_mp 7>, - <&ipmmu_mp 8>, <&ipmmu_mp 9>, - <&ipmmu_mp 10>, <&ipmmu_mp 11>, - <&ipmmu_mp 12>, <&ipmmu_mp 13>, - <&ipmmu_mp 14>, <&ipmmu_mp 15>; - }; - - audma1: dma-controller@ec720000 { - compatible = "renesas,dmac-r8a774a1", - "renesas,rcar-dmac"; - reg = <0 0xec720000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 501>; - clock-names = "fck"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 501>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_mp 16>, <&ipmmu_mp 17>, - <&ipmmu_mp 18>, <&ipmmu_mp 19>, - <&ipmmu_mp 20>, <&ipmmu_mp 21>, - <&ipmmu_mp 22>, <&ipmmu_mp 23>, - <&ipmmu_mp 24>, <&ipmmu_mp 25>, - <&ipmmu_mp 26>, <&ipmmu_mp 27>, - <&ipmmu_mp 28>, <&ipmmu_mp 29>, - <&ipmmu_mp 30>, <&ipmmu_mp 31>; - }; - - xhci0: usb@ee000000 { - compatible = "renesas,xhci-r8a774a1", - "renesas,rcar-gen3-xhci"; - reg = <0 0xee000000 0 0xc00>; - interrupts = ; - clocks = <&cpg CPG_MOD 328>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 328>; - status = "disabled"; - }; - - usb3_peri0: usb@ee020000 { - compatible = "renesas,r8a774a1-usb3-peri", - "renesas,rcar-gen3-usb3-peri"; - reg = <0 0xee020000 0 0x400>; - interrupts = ; - clocks = <&cpg CPG_MOD 328>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 328>; - status = "disabled"; - }; - - ohci0: usb@ee080000 { - compatible = "generic-ohci"; - reg = <0 0xee080000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; - phys = <&usb2_phy0 1>; - phy-names = "usb"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 703>, <&cpg 704>; - status = "disabled"; - }; - - ohci1: usb@ee0a0000 { - compatible = "generic-ohci"; - reg = <0 0xee0a0000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 702>; - phys = <&usb2_phy1 1>; - phy-names = "usb"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 702>; - status = "disabled"; - }; - - ehci0: usb@ee080100 { - compatible = "generic-ehci"; - reg = <0 0xee080100 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; - phys = <&usb2_phy0 2>; - phy-names = "usb"; - companion = <&ohci0>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 703>, <&cpg 704>; - status = "disabled"; - }; - - ehci1: usb@ee0a0100 { - compatible = "generic-ehci"; - reg = <0 0xee0a0100 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 702>; - phys = <&usb2_phy1 2>; - phy-names = "usb"; - companion = <&ohci1>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 702>; - status = "disabled"; - }; - - usb2_phy0: usb-phy@ee080200 { - compatible = "renesas,usb2-phy-r8a774a1", - "renesas,rcar-gen3-usb2-phy"; - reg = <0 0xee080200 0 0x700>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 703>, <&cpg 704>; - #phy-cells = <1>; - status = "disabled"; - }; - - usb2_phy1: usb-phy@ee0a0200 { - compatible = "renesas,usb2-phy-r8a774a1", - "renesas,rcar-gen3-usb2-phy"; - reg = <0 0xee0a0200 0 0x700>; - clocks = <&cpg CPG_MOD 702>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 702>; - #phy-cells = <1>; - status = "disabled"; - }; - - sdhi0: sd@ee100000 { - compatible = "renesas,sdhi-r8a774a1", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee100000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 314>; - max-frequency = <200000000>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 314>; - status = "disabled"; - }; - - sdhi1: sd@ee120000 { - compatible = "renesas,sdhi-r8a774a1", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee120000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 313>; - max-frequency = <200000000>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 313>; - status = "disabled"; - }; - - sdhi2: sd@ee140000 { - compatible = "renesas,sdhi-r8a774a1", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee140000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 312>; - max-frequency = <200000000>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 312>; - status = "disabled"; - }; - - sdhi3: sd@ee160000 { - compatible = "renesas,sdhi-r8a774a1", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee160000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 311>; - max-frequency = <200000000>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 311>; - status = "disabled"; - }; - - gic: interrupt-controller@f1010000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x0 0xf1010000 0 0x1000>, - <0x0 0xf1020000 0 0x20000>, - <0x0 0xf1040000 0 0x20000>, - <0x0 0xf1060000 0 0x20000>; - interrupts = ; - clocks = <&cpg CPG_MOD 408>; - clock-names = "clk"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 408>; - }; - - pciec0: pcie@fe000000 { - compatible = "renesas,pcie-r8a774a1", - "renesas,pcie-rcar-gen3"; - reg = <0 0xfe000000 0 0x80000>; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x00 0xff>; - device_type = "pci"; - ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, - <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, - <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, - <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; - interrupts = , - , - ; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; - clock-names = "pcie", "pcie_bus"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 319>; - status = "disabled"; - }; - - pciec1: pcie@ee800000 { - compatible = "renesas,pcie-r8a774a1", - "renesas,pcie-rcar-gen3"; - reg = <0 0xee800000 0 0x80000>; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x00 0xff>; - device_type = "pci"; - ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>, - <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>, - <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>, - <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; - interrupts = , - , - ; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>; - clock-names = "pcie", "pcie_bus"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 318>; - status = "disabled"; - }; - - fdp1@fe940000 { - compatible = "renesas,fdp1"; - reg = <0 0xfe940000 0 0x2400>; - interrupts = ; - clocks = <&cpg CPG_MOD 119>; - power-domains = <&sysc R8A774A1_PD_A3VC>; - resets = <&cpg 119>; - renesas,fcp = <&fcpf0>; - }; - - fcpf0: fcp@fe950000 { - compatible = "renesas,fcpf"; - reg = <0 0xfe950000 0 0x200>; - clocks = <&cpg CPG_MOD 615>; - power-domains = <&sysc R8A774A1_PD_A3VC>; - resets = <&cpg 615>; - }; - - fcpvb0: fcp@fe96f000 { - compatible = "renesas,fcpv"; - reg = <0 0xfe96f000 0 0x200>; - clocks = <&cpg CPG_MOD 607>; - power-domains = <&sysc R8A774A1_PD_A3VC>; - resets = <&cpg 607>; - }; - - fcpvd0: fcp@fea27000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea27000 0 0x200>; - clocks = <&cpg CPG_MOD 603>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 603>; - iommus = <&ipmmu_vi0 8>; - }; - - fcpvd1: fcp@fea2f000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea2f000 0 0x200>; - clocks = <&cpg CPG_MOD 602>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 602>; - iommus = <&ipmmu_vi0 9>; - }; - - fcpvd2: fcp@fea37000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea37000 0 0x200>; - clocks = <&cpg CPG_MOD 601>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 601>; - iommus = <&ipmmu_vi0 10>; - }; - - fcpvi0: fcp@fe9af000 { - compatible = "renesas,fcpv"; - reg = <0 0xfe9af000 0 0x200>; - clocks = <&cpg CPG_MOD 611>; - power-domains = <&sysc R8A774A1_PD_A3VC>; - resets = <&cpg 611>; - iommus = <&ipmmu_vc0 19>; - }; - - vspb: vsp@fe960000 { - compatible = "renesas,vsp2"; - reg = <0 0xfe960000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 626>; - power-domains = <&sysc R8A774A1_PD_A3VC>; - resets = <&cpg 626>; - - renesas,fcp = <&fcpvb0>; - }; - - vspd0: vsp@fea20000 { - compatible = "renesas,vsp2"; - reg = <0 0xfea20000 0 0x5000>; - interrupts = ; - clocks = <&cpg CPG_MOD 623>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 623>; - - renesas,fcp = <&fcpvd0>; - }; - - vspd1: vsp@fea28000 { - compatible = "renesas,vsp2"; - reg = <0 0xfea28000 0 0x5000>; - interrupts = ; - clocks = <&cpg CPG_MOD 622>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 622>; - - renesas,fcp = <&fcpvd1>; - }; - - vspd2: vsp@fea30000 { - compatible = "renesas,vsp2"; - reg = <0 0xfea30000 0 0x5000>; - interrupts = ; - clocks = <&cpg CPG_MOD 621>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 621>; - - renesas,fcp = <&fcpvd2>; - }; - - vspi0: vsp@fe9a0000 { - compatible = "renesas,vsp2"; - reg = <0 0xfe9a0000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 631>; - power-domains = <&sysc R8A774A1_PD_A3VC>; - resets = <&cpg 631>; - - renesas,fcp = <&fcpvi0>; - }; - - csi20: csi2@fea80000 { - compatible = "renesas,r8a774a1-csi2"; - reg = <0 0xfea80000 0 0x10000>; - interrupts = ; - clocks = <&cpg CPG_MOD 714>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 714>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - csi20vin0: endpoint@0 { - reg = <0>; - remote-endpoint = <&vin0csi20>; - }; - csi20vin1: endpoint@1 { - reg = <1>; - remote-endpoint = <&vin1csi20>; - }; - csi20vin2: endpoint@2 { - reg = <2>; - remote-endpoint = <&vin2csi20>; - }; - csi20vin3: endpoint@3 { - reg = <3>; - remote-endpoint = <&vin3csi20>; - }; - csi20vin4: endpoint@4 { - reg = <4>; - remote-endpoint = <&vin4csi20>; - }; - csi20vin5: endpoint@5 { - reg = <5>; - remote-endpoint = <&vin5csi20>; - }; - csi20vin6: endpoint@6 { - reg = <6>; - remote-endpoint = <&vin6csi20>; - }; - csi20vin7: endpoint@7 { - reg = <7>; - remote-endpoint = <&vin7csi20>; - }; - }; - }; - }; - - csi40: csi2@feaa0000 { - compatible = "renesas,r8a774a1-csi2"; - reg = <0 0xfeaa0000 0 0x10000>; - interrupts = ; - clocks = <&cpg CPG_MOD 716>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 716>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - csi40vin0: endpoint@0 { - reg = <0>; - remote-endpoint = <&vin0csi40>; - }; - csi40vin1: endpoint@1 { - reg = <1>; - remote-endpoint = <&vin1csi40>; - }; - csi40vin2: endpoint@2 { - reg = <2>; - remote-endpoint = <&vin2csi40>; - }; - csi40vin3: endpoint@3 { - reg = <3>; - remote-endpoint = <&vin3csi40>; - }; - csi40vin4: endpoint@4 { - reg = <4>; - remote-endpoint = <&vin4csi40>; - }; - csi40vin5: endpoint@5 { - reg = <5>; - remote-endpoint = <&vin5csi40>; - }; - csi40vin6: endpoint@6 { - reg = <6>; - remote-endpoint = <&vin6csi40>; - }; - csi40vin7: endpoint@7 { - reg = <7>; - remote-endpoint = <&vin7csi40>; - }; - }; - - }; - }; - - hdmi0: hdmi@fead0000 { - compatible = "renesas,r8a774a1-hdmi", - "renesas,rcar-gen3-hdmi"; - reg = <0 0xfead0000 0 0x10000>; - interrupts = ; - clocks = <&cpg CPG_MOD 729>, - <&cpg CPG_CORE R8A774A1_CLK_HDMI>; - clock-names = "iahb", "isfr"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 729>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - dw_hdmi0_in: endpoint { - remote-endpoint = <&du_out_hdmi0>; - }; - }; - port@1 { - reg = <1>; - }; - port@2 { - /* HDMI sound */ - reg = <2>; - }; - }; - }; - - du: display@feb00000 { - compatible = "renesas,du-r8a774a1"; - reg = <0 0xfeb00000 0 0x70000>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>, - <&cpg CPG_MOD 722>; - clock-names = "du.0", "du.1", "du.2"; - status = "disabled"; - - vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - du_out_rgb: endpoint { - }; - }; - port@1 { - reg = <1>; - du_out_hdmi0: endpoint { - remote-endpoint = <&dw_hdmi0_in>; - }; - }; - port@2 { - reg = <2>; - du_out_lvds0: endpoint { - remote-endpoint = <&lvds0_in>; - }; - }; - }; - }; - - lvds0: lvds@feb90000 { - compatible = "renesas,r8a774a1-lvds"; - reg = <0 0xfeb90000 0 0x14>; - clocks = <&cpg CPG_MOD 727>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 727>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - lvds0_in: endpoint { - remote-endpoint = <&du_out_lvds0>; - }; - }; - port@1 { - reg = <1>; - lvds0_out: endpoint { - }; - }; - }; - }; - - prr: chipid@fff00044 { - compatible = "renesas,prr"; - reg = <0 0xfff00044 0 4>; - }; - }; - - thermal-zones { - sensor_thermal1: sensor-thermal1 { - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&tsc 0>; - sustainable-power = <3874>; - - trips { - sensor1_crit: sensor1-crit { - temperature = <120000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - sensor_thermal2: sensor-thermal2 { - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&tsc 1>; - sustainable-power = <3874>; - - trips { - sensor2_crit: sensor2-crit { - temperature = <120000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - sensor_thermal3: sensor-thermal3 { - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&tsc 2>; - sustainable-power = <3874>; - - cooling-maps { - map0 { - trip = <&target>; - cooling-device = <&a57_0 0 2>; - contribution = <1024>; - }; - map1 { - trip = <&target>; - cooling-device = <&a53_0 0 2>; - contribution = <1024>; - }; - }; - trips { - target: trip-point1 { - temperature = <100000>; - hysteresis = <1000>; - type = "passive"; - }; - - sensor3_crit: sensor3-crit { - temperature = <120000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; - }; - - /* External USB clocks - can be overridden by the board */ - usb3s0_clk: usb3s0 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - usb_extal_clk: usb_extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; -}; diff --git a/sys/gnu/dts/arm64/renesas/r8a774b1-hihope-rzg2n-ex.dts b/sys/gnu/dts/arm64/renesas/r8a774b1-hihope-rzg2n-ex.dts deleted file mode 100644 index ab47c0bd9c1..00000000000 --- a/sys/gnu/dts/arm64/renesas/r8a774b1-hihope-rzg2n-ex.dts +++ /dev/null @@ -1,15 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the HiHope RZ/G2N sub board - * - * Copyright (C) 2019 Renesas Electronics Corp. - */ - -#include "r8a774b1-hihope-rzg2n.dts" -#include "hihope-rzg2-ex.dtsi" - -/ { - model = "HopeRun HiHope RZ/G2N with sub board"; - compatible = "hoperun,hihope-rzg2-ex", "hoperun,hihope-rzg2n", - "renesas,r8a774b1"; -}; diff --git a/sys/gnu/dts/arm64/renesas/r8a774b1-hihope-rzg2n.dts b/sys/gnu/dts/arm64/renesas/r8a774b1-hihope-rzg2n.dts deleted file mode 100644 index 9910c1aa0a6..00000000000 --- a/sys/gnu/dts/arm64/renesas/r8a774b1-hihope-rzg2n.dts +++ /dev/null @@ -1,41 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the HiHope RZ/G2N main board - * - * Copyright (C) 2019 Renesas Electronics Corp. - */ - -/dts-v1/; -#include "r8a774b1.dtsi" -#include "hihope-common.dtsi" - -/ { - model = "HopeRun HiHope RZ/G2N main board based on r8a774b1"; - compatible = "hoperun,hihope-rzg2n", "renesas,r8a774b1"; - - memory@48000000 { - device_type = "memory"; - /* first 128MB is reserved for secure area. */ - reg = <0x0 0x48000000 0x0 0x78000000>; - }; - - memory@480000000 { - device_type = "memory"; - reg = <0x4 0x80000000 0x0 0x80000000>; - }; -}; - -&du { - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>, - <&cpg CPG_MOD 721>, - <&versaclock5 1>, - <&x302_clk>, - <&versaclock5 2>; - clock-names = "du.0", "du.1", "du.3", - "dclkin.0", "dclkin.1", "dclkin.3"; -}; - -&sdhi3 { - mmc-hs400-1_8v; -}; diff --git a/sys/gnu/dts/arm64/renesas/r8a774b1.dtsi b/sys/gnu/dts/arm64/renesas/r8a774b1.dtsi deleted file mode 100644 index c40ea300968..00000000000 --- a/sys/gnu/dts/arm64/renesas/r8a774b1.dtsi +++ /dev/null @@ -1,2627 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the r8a774b1 SoC - * - * Copyright (C) 2019 Renesas Electronics Corp. - */ - -#include -#include -#include -#include - -/ { - compatible = "renesas,r8a774b1"; - #address-cells = <2>; - #size-cells = <2>; - - /* - * The external audio clocks are configured as 0 Hz fixed frequency - * clocks by default. - * Boards that provide audio clocks should override them. - */ - audio_clk_a: audio_clk_a { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - audio_clk_b: audio_clk_b { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - audio_clk_c: audio_clk_c { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - /* External CAN clock - to be overridden by boards that provide it */ - can_clk: can { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - cluster0_opp: opp_table0 { - compatible = "operating-points-v2"; - opp-shared; - - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <830000>; - clock-latency-ns = <300000>; - }; - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <830000>; - clock-latency-ns = <300000>; - }; - opp-1500000000 { - opp-hz = /bits/ 64 <1500000000>; - opp-microvolt = <830000>; - clock-latency-ns = <300000>; - opp-suspend; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - a57_0: cpu@0 { - compatible = "arm,cortex-a57"; - reg = <0x0>; - device_type = "cpu"; - power-domains = <&sysc R8A774B1_PD_CA57_CPU0>; - next-level-cache = <&L2_CA57>; - enable-method = "psci"; - #cooling-cells = <2>; - dynamic-power-coefficient = <854>; - clocks = <&cpg CPG_CORE R8A774B1_CLK_Z>; - operating-points-v2 = <&cluster0_opp>; - }; - - a57_1: cpu@1 { - compatible = "arm,cortex-a57"; - reg = <0x1>; - device_type = "cpu"; - power-domains = <&sysc R8A774B1_PD_CA57_CPU1>; - next-level-cache = <&L2_CA57>; - enable-method = "psci"; - clocks = <&cpg CPG_CORE R8A774B1_CLK_Z>; - operating-points-v2 = <&cluster0_opp>; - }; - - L2_CA57: cache-controller-0 { - compatible = "cache"; - power-domains = <&sysc R8A774B1_PD_CA57_SCU>; - cache-unified; - cache-level = <2>; - }; - }; - - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board */ - clock-frequency = <0>; - }; - - extalr_clk: extalr { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board */ - clock-frequency = <0>; - }; - - /* External PCIe clock - can be overridden by the board */ - pcie_bus_clk: pcie_bus { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - pmu_a57 { - compatible = "arm,cortex-a57-pmu"; - interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&a57_0>, <&a57_1>; - }; - - psci { - compatible = "arm,psci-1.0", "arm,psci-0.2"; - method = "smc"; - }; - - /* External SCIF clock - to be overridden by boards that provide it */ - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - soc { - compatible = "simple-bus"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - rwdt: watchdog@e6020000 { - compatible = "renesas,r8a774b1-wdt", - "renesas,rcar-gen3-wdt"; - reg = <0 0xe6020000 0 0x0c>; - clocks = <&cpg CPG_MOD 402>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 402>; - status = "disabled"; - }; - - gpio0: gpio@e6050000 { - compatible = "renesas,gpio-r8a774b1", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6050000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 0 16>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 912>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 912>; - }; - - gpio1: gpio@e6051000 { - compatible = "renesas,gpio-r8a774b1", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6051000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 32 29>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 911>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 911>; - }; - - gpio2: gpio@e6052000 { - compatible = "renesas,gpio-r8a774b1", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6052000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 64 15>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 910>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 910>; - }; - - gpio3: gpio@e6053000 { - compatible = "renesas,gpio-r8a774b1", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6053000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 96 16>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 909>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 909>; - }; - - gpio4: gpio@e6054000 { - compatible = "renesas,gpio-r8a774b1", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6054000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 128 18>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 908>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 908>; - }; - - gpio5: gpio@e6055000 { - compatible = "renesas,gpio-r8a774b1", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6055000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 160 26>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 907>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 907>; - }; - - gpio6: gpio@e6055400 { - compatible = "renesas,gpio-r8a774b1", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6055400 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 192 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 906>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 906>; - }; - - gpio7: gpio@e6055800 { - compatible = "renesas,gpio-r8a774b1", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6055800 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 224 4>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 905>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 905>; - }; - - pfc: pin-controller@e6060000 { - compatible = "renesas,pfc-r8a774b1"; - reg = <0 0xe6060000 0 0x50c>; - }; - - cmt0: timer@e60f0000 { - compatible = "renesas,r8a774b1-cmt0", - "renesas,rcar-gen3-cmt0"; - reg = <0 0xe60f0000 0 0x1004>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 303>; - clock-names = "fck"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 303>; - status = "disabled"; - }; - - cmt1: timer@e6130000 { - compatible = "renesas,r8a774b1-cmt1", - "renesas,rcar-gen3-cmt1"; - reg = <0 0xe6130000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 302>; - clock-names = "fck"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 302>; - status = "disabled"; - }; - - cmt2: timer@e6140000 { - compatible = "renesas,r8a774b1-cmt1", - "renesas,rcar-gen3-cmt1"; - reg = <0 0xe6140000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 301>; - clock-names = "fck"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 301>; - status = "disabled"; - }; - - cmt3: timer@e6148000 { - compatible = "renesas,r8a774b1-cmt1", - "renesas,rcar-gen3-cmt1"; - reg = <0 0xe6148000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 300>; - clock-names = "fck"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 300>; - status = "disabled"; - }; - - cpg: clock-controller@e6150000 { - compatible = "renesas,r8a774b1-cpg-mssr"; - reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk>, <&extalr_clk>; - clock-names = "extal", "extalr"; - #clock-cells = <2>; - #power-domain-cells = <0>; - #reset-cells = <1>; - }; - - rst: reset-controller@e6160000 { - compatible = "renesas,r8a774b1-rst"; - reg = <0 0xe6160000 0 0x0200>; - }; - - sysc: system-controller@e6180000 { - compatible = "renesas,r8a774b1-sysc"; - reg = <0 0xe6180000 0 0x0400>; - #power-domain-cells = <1>; - }; - - tsc: thermal@e6198000 { - compatible = "renesas,r8a774b1-thermal"; - reg = <0 0xe6198000 0 0x100>, - <0 0xe61a0000 0 0x100>, - <0 0xe61a8000 0 0x100>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 522>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 522>; - #thermal-sensor-cells = <1>; - }; - - intc_ex: interrupt-controller@e61c0000 { - compatible = "renesas,intc-ex-r8a774b1", "renesas,irqc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0 0xe61c0000 0 0x200>; - interrupts = , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 407>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 407>; - }; - - tmu0: timer@e61e0000 { - compatible = "renesas,tmu-r8a774b1", "renesas,tmu"; - reg = <0 0xe61e0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 125>; - clock-names = "fck"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 125>; - status = "disabled"; - }; - - tmu1: timer@e6fc0000 { - compatible = "renesas,tmu-r8a774b1", "renesas,tmu"; - reg = <0 0xe6fc0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 124>; - clock-names = "fck"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 124>; - status = "disabled"; - }; - - tmu2: timer@e6fd0000 { - compatible = "renesas,tmu-r8a774b1", "renesas,tmu"; - reg = <0 0xe6fd0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 123>; - clock-names = "fck"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 123>; - status = "disabled"; - }; - - tmu3: timer@e6fe0000 { - compatible = "renesas,tmu-r8a774b1", "renesas,tmu"; - reg = <0 0xe6fe0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 122>; - clock-names = "fck"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 122>; - status = "disabled"; - }; - - tmu4: timer@ffc00000 { - compatible = "renesas,tmu-r8a774b1", "renesas,tmu"; - reg = <0 0xffc00000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 121>; - clock-names = "fck"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 121>; - status = "disabled"; - }; - - i2c0: i2c@e6500000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a774b1", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6500000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 931>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 931>; - dmas = <&dmac1 0x91>, <&dmac1 0x90>, - <&dmac2 0x91>, <&dmac2 0x90>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c1: i2c@e6508000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a774b1", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6508000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 930>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 930>; - dmas = <&dmac1 0x93>, <&dmac1 0x92>, - <&dmac2 0x93>, <&dmac2 0x92>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c2: i2c@e6510000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a774b1", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6510000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 929>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 929>; - dmas = <&dmac1 0x95>, <&dmac1 0x94>, - <&dmac2 0x95>, <&dmac2 0x94>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c3: i2c@e66d0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a774b1", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66d0000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 928>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 928>; - dmas = <&dmac0 0x97>, <&dmac0 0x96>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c4: i2c@e66d8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a774b1", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66d8000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 927>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 927>; - dmas = <&dmac0 0x99>, <&dmac0 0x98>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c5: i2c@e66e0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a774b1", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66e0000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 919>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 919>; - dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c6: i2c@e66e8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a774b1", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66e8000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 918>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 918>; - dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c_dvfs: i2c@e60b0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a774b1", - "renesas,rcar-gen3-iic", - "renesas,rmobile-iic"; - reg = <0 0xe60b0000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 926>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 926>; - dmas = <&dmac0 0x11>, <&dmac0 0x10>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - hscif0: serial@e6540000 { - compatible = "renesas,hscif-r8a774b1", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6540000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 520>, - <&cpg CPG_CORE R8A774B1_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x31>, <&dmac1 0x30>, - <&dmac2 0x31>, <&dmac2 0x30>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 520>; - status = "disabled"; - }; - - hscif1: serial@e6550000 { - compatible = "renesas,hscif-r8a774b1", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6550000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 519>, - <&cpg CPG_CORE R8A774B1_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x33>, <&dmac1 0x32>, - <&dmac2 0x33>, <&dmac2 0x32>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 519>; - status = "disabled"; - }; - - hscif2: serial@e6560000 { - compatible = "renesas,hscif-r8a774b1", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6560000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 518>, - <&cpg CPG_CORE R8A774B1_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x35>, <&dmac1 0x34>, - <&dmac2 0x35>, <&dmac2 0x34>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 518>; - status = "disabled"; - }; - - hscif3: serial@e66a0000 { - compatible = "renesas,hscif-r8a774b1", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe66a0000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 517>, - <&cpg CPG_CORE R8A774B1_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x37>, <&dmac0 0x36>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 517>; - status = "disabled"; - }; - - hscif4: serial@e66b0000 { - compatible = "renesas,hscif-r8a774b1", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe66b0000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 516>, - <&cpg CPG_CORE R8A774B1_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x39>, <&dmac0 0x38>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 516>; - status = "disabled"; - }; - - hsusb: usb@e6590000 { - compatible = "renesas,usbhs-r8a774b1", - "renesas,rcar-gen3-usbhs"; - reg = <0 0xe6590000 0 0x200>; - interrupts = ; - clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>; - dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, - <&usb_dmac1 0>, <&usb_dmac1 1>; - dma-names = "ch0", "ch1", "ch2", "ch3"; - renesas,buswait = <11>; - phys = <&usb2_phy0 3>; - phy-names = "usb"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 704>, <&cpg 703>; - status = "disabled"; - }; - - usb_dmac0: dma-controller@e65a0000 { - compatible = "renesas,r8a774b1-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65a0000 0 0x100>; - interrupts = , - ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 330>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 330>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - usb_dmac1: dma-controller@e65b0000 { - compatible = "renesas,r8a774b1-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65b0000 0 0x100>; - interrupts = , - ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 331>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 331>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - usb3_phy0: usb-phy@e65ee000 { - compatible = "renesas,r8a774b1-usb3-phy", - "renesas,rcar-gen3-usb3-phy"; - reg = <0 0xe65ee000 0 0x90>; - clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, - <&usb_extal_clk>; - clock-names = "usb3-if", "usb3s_clk", "usb_extal"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 328>; - #phy-cells = <0>; - status = "disabled"; - }; - - dmac0: dma-controller@e6700000 { - compatible = "renesas,dmac-r8a774b1", - "renesas,rcar-dmac"; - reg = <0 0xe6700000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 219>; - clock-names = "fck"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 219>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, - <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, - <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, - <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, - <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, - <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, - <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, - <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; - }; - - dmac1: dma-controller@e7300000 { - compatible = "renesas,dmac-r8a774b1", - "renesas,rcar-dmac"; - reg = <0 0xe7300000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 218>; - clock-names = "fck"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 218>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, - <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, - <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, - <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, - <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, - <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, - <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, - <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; - }; - - dmac2: dma-controller@e7310000 { - compatible = "renesas,dmac-r8a774b1", - "renesas,rcar-dmac"; - reg = <0 0xe7310000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 217>; - clock-names = "fck"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 217>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, - <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, - <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, - <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, - <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, - <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, - <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, - <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; - }; - - ipmmu_ds0: mmu@e6740000 { - compatible = "renesas,ipmmu-r8a774b1"; - reg = <0 0xe6740000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 0>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_ds1: mmu@e7740000 { - compatible = "renesas,ipmmu-r8a774b1"; - reg = <0 0xe7740000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 1>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_hc: mmu@e6570000 { - compatible = "renesas,ipmmu-r8a774b1"; - reg = <0 0xe6570000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 2>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_mm: mmu@e67b0000 { - compatible = "renesas,ipmmu-r8a774b1"; - reg = <0 0xe67b0000 0 0x1000>; - interrupts = , - ; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_mp: mmu@ec670000 { - compatible = "renesas,ipmmu-r8a774b1"; - reg = <0 0xec670000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 4>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_pv0: mmu@fd800000 { - compatible = "renesas,ipmmu-r8a774b1"; - reg = <0 0xfd800000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 6>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_vc0: mmu@fe6b0000 { - compatible = "renesas,ipmmu-r8a774b1"; - reg = <0 0xfe6b0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 12>; - power-domains = <&sysc R8A774B1_PD_A3VC>; - #iommu-cells = <1>; - }; - - ipmmu_vi0: mmu@febd0000 { - compatible = "renesas,ipmmu-r8a774b1"; - reg = <0 0xfebd0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 14>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_vp0: mmu@fe990000 { - compatible = "renesas,ipmmu-r8a774b1"; - reg = <0 0xfe990000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 16>; - power-domains = <&sysc R8A774B1_PD_A3VP>; - #iommu-cells = <1>; - }; - - avb: ethernet@e6800000 { - compatible = "renesas,etheravb-r8a774b1", - "renesas,etheravb-rcar-gen3"; - reg = <0 0xe6800000 0 0x800>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15", - "ch16", "ch17", "ch18", "ch19", - "ch20", "ch21", "ch22", "ch23", - "ch24"; - clocks = <&cpg CPG_MOD 812>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 812>; - phy-mode = "rgmii"; - iommus = <&ipmmu_ds0 16>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - can0: can@e6c30000 { - compatible = "renesas,can-r8a774b1", - "renesas,rcar-gen3-can"; - reg = <0 0xe6c30000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 916>, - <&cpg CPG_CORE R8A774B1_CLK_CANFD>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A774B1_CLK_CANFD>; - assigned-clock-rates = <40000000>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 916>; - status = "disabled"; - }; - - can1: can@e6c38000 { - compatible = "renesas,can-r8a774b1", - "renesas,rcar-gen3-can"; - reg = <0 0xe6c38000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 915>, - <&cpg CPG_CORE R8A774B1_CLK_CANFD>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A774B1_CLK_CANFD>; - assigned-clock-rates = <40000000>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 915>; - status = "disabled"; - }; - - canfd: can@e66c0000 { - compatible = "renesas,r8a774b1-canfd", - "renesas,rcar-gen3-canfd"; - reg = <0 0xe66c0000 0 0x8000>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 914>, - <&cpg CPG_CORE R8A774B1_CLK_CANFD>, - <&can_clk>; - clock-names = "fck", "canfd", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A774B1_CLK_CANFD>; - assigned-clock-rates = <40000000>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 914>; - status = "disabled"; - - channel0 { - status = "disabled"; - }; - - channel1 { - status = "disabled"; - }; - }; - - pwm0: pwm@e6e30000 { - compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar"; - reg = <0 0xe6e30000 0 0x8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pwm1: pwm@e6e31000 { - compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar"; - reg = <0 0xe6e31000 0 0x8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pwm2: pwm@e6e32000 { - compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar"; - reg = <0 0xe6e32000 0 0x8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pwm3: pwm@e6e33000 { - compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar"; - reg = <0 0xe6e33000 0 0x8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pwm4: pwm@e6e34000 { - compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar"; - reg = <0 0xe6e34000 0 0x8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pwm5: pwm@e6e35000 { - compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar"; - reg = <0 0xe6e35000 0 0x8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pwm6: pwm@e6e36000 { - compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar"; - reg = <0 0xe6e36000 0 0x8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - status = "disabled"; - }; - - scif0: serial@e6e60000 { - compatible = "renesas,scif-r8a774b1", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e60000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 207>, - <&cpg CPG_CORE R8A774B1_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x51>, <&dmac1 0x50>, - <&dmac2 0x51>, <&dmac2 0x50>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 207>; - status = "disabled"; - }; - - scif1: serial@e6e68000 { - compatible = "renesas,scif-r8a774b1", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e68000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 206>, - <&cpg CPG_CORE R8A774B1_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x53>, <&dmac1 0x52>, - <&dmac2 0x53>, <&dmac2 0x52>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 206>; - status = "disabled"; - }; - - scif2: serial@e6e88000 { - compatible = "renesas,scif-r8a774b1", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e88000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 310>, - <&cpg CPG_CORE R8A774B1_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x13>, <&dmac1 0x12>, - <&dmac2 0x13>, <&dmac2 0x12>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 310>; - status = "disabled"; - }; - - scif3: serial@e6c50000 { - compatible = "renesas,scif-r8a774b1", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6c50000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 204>, - <&cpg CPG_CORE R8A774B1_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x57>, <&dmac0 0x56>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 204>; - status = "disabled"; - }; - - scif4: serial@e6c40000 { - compatible = "renesas,scif-r8a774b1", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6c40000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 203>, - <&cpg CPG_CORE R8A774B1_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x59>, <&dmac0 0x58>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 203>; - status = "disabled"; - }; - - scif5: serial@e6f30000 { - compatible = "renesas,scif-r8a774b1", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6f30000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 202>, - <&cpg CPG_CORE R8A774B1_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, - <&dmac2 0x5b>, <&dmac2 0x5a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 202>; - status = "disabled"; - }; - - msiof0: spi@e6e90000 { - compatible = "renesas,msiof-r8a774b1", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6e90000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 211>; - dmas = <&dmac1 0x41>, <&dmac1 0x40>, - <&dmac2 0x41>, <&dmac2 0x40>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 211>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof1: spi@e6ea0000 { - compatible = "renesas,msiof-r8a774b1", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6ea0000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 210>; - dmas = <&dmac1 0x43>, <&dmac1 0x42>, - <&dmac2 0x43>, <&dmac2 0x42>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 210>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof2: spi@e6c00000 { - compatible = "renesas,msiof-r8a774b1", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6c00000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 209>; - dmas = <&dmac0 0x45>, <&dmac0 0x44>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 209>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof3: spi@e6c10000 { - compatible = "renesas,msiof-r8a774b1", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6c10000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 208>; - dmas = <&dmac0 0x47>, <&dmac0 0x46>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 208>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - vin0: video@e6ef0000 { - compatible = "renesas,vin-r8a774b1"; - reg = <0 0xe6ef0000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 811>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 811>; - renesas,id = <0>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin0csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin0>; - }; - vin0csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin0>; - }; - }; - }; - }; - - vin1: video@e6ef1000 { - compatible = "renesas,vin-r8a774b1"; - reg = <0 0xe6ef1000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 810>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 810>; - renesas,id = <1>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin1csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin1>; - }; - vin1csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin1>; - }; - }; - }; - }; - - vin2: video@e6ef2000 { - compatible = "renesas,vin-r8a774b1"; - reg = <0 0xe6ef2000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 809>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 809>; - renesas,id = <2>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin2csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin2>; - }; - vin2csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin2>; - }; - }; - }; - }; - - vin3: video@e6ef3000 { - compatible = "renesas,vin-r8a774b1"; - reg = <0 0xe6ef3000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 808>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 808>; - renesas,id = <3>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin3csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin3>; - }; - vin3csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin3>; - }; - }; - }; - }; - - vin4: video@e6ef4000 { - compatible = "renesas,vin-r8a774b1"; - reg = <0 0xe6ef4000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 807>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 807>; - renesas,id = <4>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin4csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin4>; - }; - vin4csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin4>; - }; - }; - }; - }; - - vin5: video@e6ef5000 { - compatible = "renesas,vin-r8a774b1"; - reg = <0 0xe6ef5000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 806>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 806>; - renesas,id = <5>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin5csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin5>; - }; - vin5csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin5>; - }; - }; - }; - }; - - vin6: video@e6ef6000 { - compatible = "renesas,vin-r8a774b1"; - reg = <0 0xe6ef6000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 805>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 805>; - renesas,id = <6>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin6csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin6>; - }; - vin6csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin6>; - }; - }; - }; - }; - - vin7: video@e6ef7000 { - compatible = "renesas,vin-r8a774b1"; - reg = <0 0xe6ef7000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 804>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 804>; - renesas,id = <7>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin7csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin7>; - }; - vin7csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin7>; - }; - }; - }; - }; - - rcar_sound: sound@ec500000 { - /* - * #sound-dai-cells is required - * - * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; - * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; - */ - /* - * #clock-cells is required for audio_clkout0/1/2/3 - * - * clkout : #clock-cells = <0>; <&rcar_sound>; - * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; - */ - compatible = "renesas,rcar_sound-r8a774b1", "renesas,rcar_sound-gen3"; - reg = <0 0xec500000 0 0x1000>, /* SCU */ - <0 0xec5a0000 0 0x100>, /* ADG */ - <0 0xec540000 0 0x1000>, /* SSIU */ - <0 0xec541000 0 0x280>, /* SSI */ - <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ - reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; - - clocks = <&cpg CPG_MOD 1005>, - <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, - <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, - <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, - <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, - <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, - <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, - <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, - <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, - <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, - <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, - <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, - <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, - <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, - <&audio_clk_a>, <&audio_clk_b>, - <&audio_clk_c>, - <&cpg CPG_CORE R8A774B1_CLK_S0D4>; - clock-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", - "ssi.5", "ssi.4", "ssi.3", "ssi.2", - "ssi.1", "ssi.0", - "src.9", "src.8", "src.7", "src.6", - "src.5", "src.4", "src.3", "src.2", - "src.1", "src.0", - "mix.1", "mix.0", - "ctu.1", "ctu.0", - "dvc.0", "dvc.1", - "clk_a", "clk_b", "clk_c", "clk_i"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 1005>, - <&cpg 1006>, <&cpg 1007>, - <&cpg 1008>, <&cpg 1009>, - <&cpg 1010>, <&cpg 1011>, - <&cpg 1012>, <&cpg 1013>, - <&cpg 1014>, <&cpg 1015>; - reset-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", - "ssi.5", "ssi.4", "ssi.3", "ssi.2", - "ssi.1", "ssi.0"; - status = "disabled"; - - rcar_sound,ctu { - ctu00: ctu-0 { }; - ctu01: ctu-1 { }; - ctu02: ctu-2 { }; - ctu03: ctu-3 { }; - ctu10: ctu-4 { }; - ctu11: ctu-5 { }; - ctu12: ctu-6 { }; - ctu13: ctu-7 { }; - }; - - rcar_sound,dvc { - dvc0: dvc-0 { - dmas = <&audma1 0xbc>; - dma-names = "tx"; - }; - dvc1: dvc-1 { - dmas = <&audma1 0xbe>; - dma-names = "tx"; - }; - }; - - rcar_sound,mix { - mix0: mix-0 { }; - mix1: mix-1 { }; - }; - - rcar_sound,src { - src0: src-0 { - interrupts = ; - dmas = <&audma0 0x85>, <&audma1 0x9a>; - dma-names = "rx", "tx"; - }; - src1: src-1 { - interrupts = ; - dmas = <&audma0 0x87>, <&audma1 0x9c>; - dma-names = "rx", "tx"; - }; - src2: src-2 { - interrupts = ; - dmas = <&audma0 0x89>, <&audma1 0x9e>; - dma-names = "rx", "tx"; - }; - src3: src-3 { - interrupts = ; - dmas = <&audma0 0x8b>, <&audma1 0xa0>; - dma-names = "rx", "tx"; - }; - src4: src-4 { - interrupts = ; - dmas = <&audma0 0x8d>, <&audma1 0xb0>; - dma-names = "rx", "tx"; - }; - src5: src-5 { - interrupts = ; - dmas = <&audma0 0x8f>, <&audma1 0xb2>; - dma-names = "rx", "tx"; - }; - src6: src-6 { - interrupts = ; - dmas = <&audma0 0x91>, <&audma1 0xb4>; - dma-names = "rx", "tx"; - }; - src7: src-7 { - interrupts = ; - dmas = <&audma0 0x93>, <&audma1 0xb6>; - dma-names = "rx", "tx"; - }; - src8: src-8 { - interrupts = ; - dmas = <&audma0 0x95>, <&audma1 0xb8>; - dma-names = "rx", "tx"; - }; - src9: src-9 { - interrupts = ; - dmas = <&audma0 0x97>, <&audma1 0xba>; - dma-names = "rx", "tx"; - }; - }; - - rcar_sound,ssi { - ssi0: ssi-0 { - interrupts = ; - dmas = <&audma0 0x01>, <&audma1 0x02>; - dma-names = "rx", "tx"; - }; - ssi1: ssi-1 { - interrupts = ; - dmas = <&audma0 0x03>, <&audma1 0x04>; - dma-names = "rx", "tx"; - }; - ssi2: ssi-2 { - interrupts = ; - dmas = <&audma0 0x05>, <&audma1 0x06>; - dma-names = "rx", "tx"; - }; - ssi3: ssi-3 { - interrupts = ; - dmas = <&audma0 0x07>, <&audma1 0x08>; - dma-names = "rx", "tx"; - }; - ssi4: ssi-4 { - interrupts = ; - dmas = <&audma0 0x09>, <&audma1 0x0a>; - dma-names = "rx", "tx"; - }; - ssi5: ssi-5 { - interrupts = ; - dmas = <&audma0 0x0b>, <&audma1 0x0c>; - dma-names = "rx", "tx"; - }; - ssi6: ssi-6 { - interrupts = ; - dmas = <&audma0 0x0d>, <&audma1 0x0e>; - dma-names = "rx", "tx"; - }; - ssi7: ssi-7 { - interrupts = ; - dmas = <&audma0 0x0f>, <&audma1 0x10>; - dma-names = "rx", "tx"; - }; - ssi8: ssi-8 { - interrupts = ; - dmas = <&audma0 0x11>, <&audma1 0x12>; - dma-names = "rx", "tx"; - }; - ssi9: ssi-9 { - interrupts = ; - dmas = <&audma0 0x13>, <&audma1 0x14>; - dma-names = "rx", "tx"; - }; - }; - - rcar_sound,ssiu { - ssiu00: ssiu-0 { - dmas = <&audma0 0x15>, <&audma1 0x16>; - dma-names = "rx", "tx"; - }; - ssiu01: ssiu-1 { - dmas = <&audma0 0x35>, <&audma1 0x36>; - dma-names = "rx", "tx"; - }; - ssiu02: ssiu-2 { - dmas = <&audma0 0x37>, <&audma1 0x38>; - dma-names = "rx", "tx"; - }; - ssiu03: ssiu-3 { - dmas = <&audma0 0x47>, <&audma1 0x48>; - dma-names = "rx", "tx"; - }; - ssiu04: ssiu-4 { - dmas = <&audma0 0x3F>, <&audma1 0x40>; - dma-names = "rx", "tx"; - }; - ssiu05: ssiu-5 { - dmas = <&audma0 0x43>, <&audma1 0x44>; - dma-names = "rx", "tx"; - }; - ssiu06: ssiu-6 { - dmas = <&audma0 0x4F>, <&audma1 0x50>; - dma-names = "rx", "tx"; - }; - ssiu07: ssiu-7 { - dmas = <&audma0 0x53>, <&audma1 0x54>; - dma-names = "rx", "tx"; - }; - ssiu10: ssiu-8 { - dmas = <&audma0 0x49>, <&audma1 0x4a>; - dma-names = "rx", "tx"; - }; - ssiu11: ssiu-9 { - dmas = <&audma0 0x4B>, <&audma1 0x4C>; - dma-names = "rx", "tx"; - }; - ssiu12: ssiu-10 { - dmas = <&audma0 0x57>, <&audma1 0x58>; - dma-names = "rx", "tx"; - }; - ssiu13: ssiu-11 { - dmas = <&audma0 0x59>, <&audma1 0x5A>; - dma-names = "rx", "tx"; - }; - ssiu14: ssiu-12 { - dmas = <&audma0 0x5F>, <&audma1 0x60>; - dma-names = "rx", "tx"; - }; - ssiu15: ssiu-13 { - dmas = <&audma0 0xC3>, <&audma1 0xC4>; - dma-names = "rx", "tx"; - }; - ssiu16: ssiu-14 { - dmas = <&audma0 0xC7>, <&audma1 0xC8>; - dma-names = "rx", "tx"; - }; - ssiu17: ssiu-15 { - dmas = <&audma0 0xCB>, <&audma1 0xCC>; - dma-names = "rx", "tx"; - }; - ssiu20: ssiu-16 { - dmas = <&audma0 0x63>, <&audma1 0x64>; - dma-names = "rx", "tx"; - }; - ssiu21: ssiu-17 { - dmas = <&audma0 0x67>, <&audma1 0x68>; - dma-names = "rx", "tx"; - }; - ssiu22: ssiu-18 { - dmas = <&audma0 0x6B>, <&audma1 0x6C>; - dma-names = "rx", "tx"; - }; - ssiu23: ssiu-19 { - dmas = <&audma0 0x6D>, <&audma1 0x6E>; - dma-names = "rx", "tx"; - }; - ssiu24: ssiu-20 { - dmas = <&audma0 0xCF>, <&audma1 0xCE>; - dma-names = "rx", "tx"; - }; - ssiu25: ssiu-21 { - dmas = <&audma0 0xEB>, <&audma1 0xEC>; - dma-names = "rx", "tx"; - }; - ssiu26: ssiu-22 { - dmas = <&audma0 0xED>, <&audma1 0xEE>; - dma-names = "rx", "tx"; - }; - ssiu27: ssiu-23 { - dmas = <&audma0 0xEF>, <&audma1 0xF0>; - dma-names = "rx", "tx"; - }; - ssiu30: ssiu-24 { - dmas = <&audma0 0x6f>, <&audma1 0x70>; - dma-names = "rx", "tx"; - }; - ssiu31: ssiu-25 { - dmas = <&audma0 0x21>, <&audma1 0x22>; - dma-names = "rx", "tx"; - }; - ssiu32: ssiu-26 { - dmas = <&audma0 0x23>, <&audma1 0x24>; - dma-names = "rx", "tx"; - }; - ssiu33: ssiu-27 { - dmas = <&audma0 0x25>, <&audma1 0x26>; - dma-names = "rx", "tx"; - }; - ssiu34: ssiu-28 { - dmas = <&audma0 0x27>, <&audma1 0x28>; - dma-names = "rx", "tx"; - }; - ssiu35: ssiu-29 { - dmas = <&audma0 0x29>, <&audma1 0x2A>; - dma-names = "rx", "tx"; - }; - ssiu36: ssiu-30 { - dmas = <&audma0 0x2B>, <&audma1 0x2C>; - dma-names = "rx", "tx"; - }; - ssiu37: ssiu-31 { - dmas = <&audma0 0x2D>, <&audma1 0x2E>; - dma-names = "rx", "tx"; - }; - ssiu40: ssiu-32 { - dmas = <&audma0 0x71>, <&audma1 0x72>; - dma-names = "rx", "tx"; - }; - ssiu41: ssiu-33 { - dmas = <&audma0 0x17>, <&audma1 0x18>; - dma-names = "rx", "tx"; - }; - ssiu42: ssiu-34 { - dmas = <&audma0 0x19>, <&audma1 0x1A>; - dma-names = "rx", "tx"; - }; - ssiu43: ssiu-35 { - dmas = <&audma0 0x1B>, <&audma1 0x1C>; - dma-names = "rx", "tx"; - }; - ssiu44: ssiu-36 { - dmas = <&audma0 0x1D>, <&audma1 0x1E>; - dma-names = "rx", "tx"; - }; - ssiu45: ssiu-37 { - dmas = <&audma0 0x1F>, <&audma1 0x20>; - dma-names = "rx", "tx"; - }; - ssiu46: ssiu-38 { - dmas = <&audma0 0x31>, <&audma1 0x32>; - dma-names = "rx", "tx"; - }; - ssiu47: ssiu-39 { - dmas = <&audma0 0x33>, <&audma1 0x34>; - dma-names = "rx", "tx"; - }; - ssiu50: ssiu-40 { - dmas = <&audma0 0x73>, <&audma1 0x74>; - dma-names = "rx", "tx"; - }; - ssiu60: ssiu-41 { - dmas = <&audma0 0x75>, <&audma1 0x76>; - dma-names = "rx", "tx"; - }; - ssiu70: ssiu-42 { - dmas = <&audma0 0x79>, <&audma1 0x7a>; - dma-names = "rx", "tx"; - }; - ssiu80: ssiu-43 { - dmas = <&audma0 0x7b>, <&audma1 0x7c>; - dma-names = "rx", "tx"; - }; - ssiu90: ssiu-44 { - dmas = <&audma0 0x7d>, <&audma1 0x7e>; - dma-names = "rx", "tx"; - }; - ssiu91: ssiu-45 { - dmas = <&audma0 0x7F>, <&audma1 0x80>; - dma-names = "rx", "tx"; - }; - ssiu92: ssiu-46 { - dmas = <&audma0 0x81>, <&audma1 0x82>; - dma-names = "rx", "tx"; - }; - ssiu93: ssiu-47 { - dmas = <&audma0 0x83>, <&audma1 0x84>; - dma-names = "rx", "tx"; - }; - ssiu94: ssiu-48 { - dmas = <&audma0 0xA3>, <&audma1 0xA4>; - dma-names = "rx", "tx"; - }; - ssiu95: ssiu-49 { - dmas = <&audma0 0xA5>, <&audma1 0xA6>; - dma-names = "rx", "tx"; - }; - ssiu96: ssiu-50 { - dmas = <&audma0 0xA7>, <&audma1 0xA8>; - dma-names = "rx", "tx"; - }; - ssiu97: ssiu-51 { - dmas = <&audma0 0xA9>, <&audma1 0xAA>; - dma-names = "rx", "tx"; - }; - }; - }; - - audma0: dma-controller@ec700000 { - compatible = "renesas,dmac-r8a774b1", - "renesas,rcar-dmac"; - reg = <0 0xec700000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 502>; - clock-names = "fck"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 502>; - #dma-cells = <1>; - dma-channels = <16>; - }; - - audma1: dma-controller@ec720000 { - compatible = "renesas,dmac-r8a774b1", - "renesas,rcar-dmac"; - reg = <0 0xec720000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 501>; - clock-names = "fck"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 501>; - #dma-cells = <1>; - dma-channels = <16>; - }; - - xhci0: usb@ee000000 { - compatible = "renesas,xhci-r8a774b1", - "renesas,rcar-gen3-xhci"; - reg = <0 0xee000000 0 0xc00>; - interrupts = ; - clocks = <&cpg CPG_MOD 328>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 328>; - status = "disabled"; - }; - - usb3_peri0: usb@ee020000 { - compatible = "renesas,r8a774b1-usb3-peri", - "renesas,rcar-gen3-usb3-peri"; - reg = <0 0xee020000 0 0x400>; - interrupts = ; - clocks = <&cpg CPG_MOD 328>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 328>; - status = "disabled"; - }; - - ohci0: usb@ee080000 { - compatible = "generic-ohci"; - reg = <0 0xee080000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; - phys = <&usb2_phy0 1>; - phy-names = "usb"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 703>, <&cpg 704>; - status = "disabled"; - }; - - ohci1: usb@ee0a0000 { - compatible = "generic-ohci"; - reg = <0 0xee0a0000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 702>; - phys = <&usb2_phy1 1>; - phy-names = "usb"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 702>; - status = "disabled"; - }; - - ehci0: usb@ee080100 { - compatible = "generic-ehci"; - reg = <0 0xee080100 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; - phys = <&usb2_phy0 2>; - phy-names = "usb"; - companion = <&ohci0>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 703>, <&cpg 704>; - status = "disabled"; - }; - - ehci1: usb@ee0a0100 { - compatible = "generic-ehci"; - reg = <0 0xee0a0100 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 702>; - phys = <&usb2_phy1 2>; - phy-names = "usb"; - companion = <&ohci1>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 702>; - status = "disabled"; - }; - - usb2_phy0: usb-phy@ee080200 { - compatible = "renesas,usb2-phy-r8a774b1", - "renesas,rcar-gen3-usb2-phy"; - reg = <0 0xee080200 0 0x700>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 703>, <&cpg 704>; - #phy-cells = <1>; - status = "disabled"; - }; - - usb2_phy1: usb-phy@ee0a0200 { - compatible = "renesas,usb2-phy-r8a774b1", - "renesas,rcar-gen3-usb2-phy"; - reg = <0 0xee0a0200 0 0x700>; - clocks = <&cpg CPG_MOD 702>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 702>; - #phy-cells = <1>; - status = "disabled"; - }; - - sdhi0: sd@ee100000 { - compatible = "renesas,sdhi-r8a774b1", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee100000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 314>; - max-frequency = <200000000>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 314>; - status = "disabled"; - }; - - sdhi1: sd@ee120000 { - compatible = "renesas,sdhi-r8a774b1", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee120000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 313>; - max-frequency = <200000000>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 313>; - status = "disabled"; - }; - - sdhi2: sd@ee140000 { - compatible = "renesas,sdhi-r8a774b1", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee140000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 312>; - max-frequency = <200000000>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 312>; - status = "disabled"; - }; - - sdhi3: sd@ee160000 { - compatible = "renesas,sdhi-r8a774b1", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee160000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 311>; - max-frequency = <200000000>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 311>; - status = "disabled"; - }; - - sata: sata@ee300000 { - compatible = "renesas,sata-r8a774b1", - "renesas,rcar-gen3-sata"; - reg = <0 0xee300000 0 0x200000>; - interrupts = ; - clocks = <&cpg CPG_MOD 815>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 815>; - status = "disabled"; - }; - - gic: interrupt-controller@f1010000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x0 0xf1010000 0 0x1000>, - <0x0 0xf1020000 0 0x20000>, - <0x0 0xf1040000 0 0x20000>, - <0x0 0xf1060000 0 0x20000>; - interrupts = ; - clocks = <&cpg CPG_MOD 408>; - clock-names = "clk"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 408>; - }; - - pciec0: pcie@fe000000 { - compatible = "renesas,pcie-r8a774b1", - "renesas,pcie-rcar-gen3"; - reg = <0 0xfe000000 0 0x80000>; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x00 0xff>; - device_type = "pci"; - ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, - <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, - <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, - <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; - interrupts = , - , - ; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; - clock-names = "pcie", "pcie_bus"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 319>; - status = "disabled"; - }; - - pciec1: pcie@ee800000 { - compatible = "renesas,pcie-r8a774b1", - "renesas,pcie-rcar-gen3"; - reg = <0 0xee800000 0 0x80000>; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x00 0xff>; - device_type = "pci"; - ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>, - <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>, - <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>, - <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; - interrupts = , - , - ; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>; - clock-names = "pcie", "pcie_bus"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 318>; - status = "disabled"; - }; - - fdp1@fe940000 { - compatible = "renesas,fdp1"; - reg = <0 0xfe940000 0 0x2400>; - interrupts = ; - clocks = <&cpg CPG_MOD 119>; - power-domains = <&sysc R8A774B1_PD_A3VP>; - resets = <&cpg 119>; - renesas,fcp = <&fcpf0>; - }; - - fcpf0: fcp@fe950000 { - compatible = "renesas,fcpf"; - reg = <0 0xfe950000 0 0x200>; - clocks = <&cpg CPG_MOD 615>; - power-domains = <&sysc R8A774B1_PD_A3VP>; - resets = <&cpg 615>; - }; - - vspb: vsp@fe960000 { - compatible = "renesas,vsp2"; - reg = <0 0xfe960000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 626>; - power-domains = <&sysc R8A774B1_PD_A3VP>; - resets = <&cpg 626>; - - renesas,fcp = <&fcpvb0>; - }; - - vspi0: vsp@fe9a0000 { - compatible = "renesas,vsp2"; - reg = <0 0xfe9a0000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 631>; - power-domains = <&sysc R8A774B1_PD_A3VP>; - resets = <&cpg 631>; - - renesas,fcp = <&fcpvi0>; - }; - - vspd0: vsp@fea20000 { - compatible = "renesas,vsp2"; - reg = <0 0xfea20000 0 0x5000>; - interrupts = ; - clocks = <&cpg CPG_MOD 623>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 623>; - - renesas,fcp = <&fcpvd0>; - }; - - vspd1: vsp@fea28000 { - compatible = "renesas,vsp2"; - reg = <0 0xfea28000 0 0x5000>; - interrupts = ; - clocks = <&cpg CPG_MOD 622>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 622>; - - renesas,fcp = <&fcpvd1>; - }; - - fcpvb0: fcp@fe96f000 { - compatible = "renesas,fcpv"; - reg = <0 0xfe96f000 0 0x200>; - clocks = <&cpg CPG_MOD 607>; - power-domains = <&sysc R8A774B1_PD_A3VP>; - resets = <&cpg 607>; - }; - - fcpvd0: fcp@fea27000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea27000 0 0x200>; - clocks = <&cpg CPG_MOD 603>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 603>; - }; - - fcpvd1: fcp@fea2f000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea2f000 0 0x200>; - clocks = <&cpg CPG_MOD 602>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 602>; - }; - - fcpvi0: fcp@fe9af000 { - compatible = "renesas,fcpv"; - reg = <0 0xfe9af000 0 0x200>; - clocks = <&cpg CPG_MOD 611>; - power-domains = <&sysc R8A774B1_PD_A3VP>; - resets = <&cpg 611>; - }; - - csi20: csi2@fea80000 { - compatible = "renesas,r8a774b1-csi2"; - reg = <0 0xfea80000 0 0x10000>; - interrupts = ; - clocks = <&cpg CPG_MOD 714>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 714>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - csi20vin0: endpoint@0 { - reg = <0>; - remote-endpoint = <&vin0csi20>; - }; - csi20vin1: endpoint@1 { - reg = <1>; - remote-endpoint = <&vin1csi20>; - }; - csi20vin2: endpoint@2 { - reg = <2>; - remote-endpoint = <&vin2csi20>; - }; - csi20vin3: endpoint@3 { - reg = <3>; - remote-endpoint = <&vin3csi20>; - }; - csi20vin4: endpoint@4 { - reg = <4>; - remote-endpoint = <&vin4csi20>; - }; - csi20vin5: endpoint@5 { - reg = <5>; - remote-endpoint = <&vin5csi20>; - }; - csi20vin6: endpoint@6 { - reg = <6>; - remote-endpoint = <&vin6csi20>; - }; - csi20vin7: endpoint@7 { - reg = <7>; - remote-endpoint = <&vin7csi20>; - }; - }; - }; - }; - - csi40: csi2@feaa0000 { - compatible = "renesas,r8a774b1-csi2"; - reg = <0 0xfeaa0000 0 0x10000>; - interrupts = ; - clocks = <&cpg CPG_MOD 716>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 716>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - csi40vin0: endpoint@0 { - reg = <0>; - remote-endpoint = <&vin0csi40>; - }; - csi40vin1: endpoint@1 { - reg = <1>; - remote-endpoint = <&vin1csi40>; - }; - csi40vin2: endpoint@2 { - reg = <2>; - remote-endpoint = <&vin2csi40>; - }; - csi40vin3: endpoint@3 { - reg = <3>; - remote-endpoint = <&vin3csi40>; - }; - csi40vin4: endpoint@4 { - reg = <4>; - remote-endpoint = <&vin4csi40>; - }; - csi40vin5: endpoint@5 { - reg = <5>; - remote-endpoint = <&vin5csi40>; - }; - csi40vin6: endpoint@6 { - reg = <6>; - remote-endpoint = <&vin6csi40>; - }; - csi40vin7: endpoint@7 { - reg = <7>; - remote-endpoint = <&vin7csi40>; - }; - }; - }; - }; - - hdmi0: hdmi@fead0000 { - compatible = "renesas,r8a774b1-hdmi", - "renesas,rcar-gen3-hdmi"; - reg = <0 0xfead0000 0 0x10000>; - interrupts = ; - clocks = <&cpg CPG_MOD 729>, - <&cpg CPG_CORE R8A774B1_CLK_HDMI>; - clock-names = "iahb", "isfr"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 729>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dw_hdmi0_in: endpoint { - remote-endpoint = <&du_out_hdmi0>; - }; - }; - port@1 { - reg = <1>; - }; - port@2 { - /* HDMI sound */ - reg = <2>; - }; - }; - }; - - du: display@feb00000 { - compatible = "renesas,du-r8a774b1"; - reg = <0 0xfeb00000 0 0x80000>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>, - <&cpg CPG_MOD 721>; - clock-names = "du.0", "du.1", "du.3"; - status = "disabled"; - - vsps = <&vspd0 0>, <&vspd1 0>, <&vspd0 1>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - du_out_rgb: endpoint { - }; - }; - port@1 { - reg = <1>; - du_out_hdmi0: endpoint { - remote-endpoint = <&dw_hdmi0_in>; - }; - }; - port@2 { - reg = <2>; - du_out_lvds0: endpoint { - remote-endpoint = <&lvds0_in>; - }; - }; - }; - }; - - lvds0: lvds@feb90000 { - compatible = "renesas,r8a774b1-lvds"; - reg = <0 0xfeb90000 0 0x14>; - clocks = <&cpg CPG_MOD 727>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 727>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - lvds0_in: endpoint { - remote-endpoint = <&du_out_lvds0>; - }; - }; - port@1 { - reg = <1>; - lvds0_out: endpoint { - }; - }; - }; - }; - - prr: chipid@fff00044 { - compatible = "renesas,prr"; - reg = <0 0xfff00044 0 4>; - }; - }; - - thermal-zones { - sensor_thermal1: sensor-thermal1 { - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&tsc 0>; - sustainable-power = <2439>; - - trips { - sensor1_crit: sensor1-crit { - temperature = <120000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - sensor_thermal2: sensor-thermal2 { - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&tsc 1>; - sustainable-power = <2439>; - - trips { - sensor2_crit: sensor2-crit { - temperature = <120000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - sensor_thermal3: sensor-thermal3 { - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&tsc 2>; - sustainable-power = <2439>; - - cooling-maps { - map0 { - trip = <&target>; - cooling-device = <&a57_0 0 2>; - contribution = <1024>; - }; - }; - trips { - target: trip-point1 { - temperature = <100000>; - hysteresis = <1000>; - type = "passive"; - }; - - sensor3_crit: sensor3-crit { - temperature = <120000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; - }; - - /* External USB clocks - can be overridden by the board */ - usb3s0_clk: usb3s0 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - usb_extal_clk: usb_extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; -}; diff --git a/sys/gnu/dts/arm64/renesas/r8a774c0-cat874.dts b/sys/gnu/dts/arm64/renesas/r8a774c0-cat874.dts deleted file mode 100644 index 26aee004a44..00000000000 --- a/sys/gnu/dts/arm64/renesas/r8a774c0-cat874.dts +++ /dev/null @@ -1,420 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the Silicon Linux RZ/G2E 96board platform (CAT874) - * - * Copyright (C) 2019 Renesas Electronics Corp. - */ - -/dts-v1/; -#include "r8a774c0.dtsi" -#include -#include - -/ { - model = "Silicon Linux RZ/G2E 96board platform (CAT874)"; - compatible = "si-linux,cat874", "renesas,r8a774c0"; - - aliases { - serial0 = &scif2; - serial1 = &hscif2; - }; - - chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; - stdout-path = "serial0:115200n8"; - }; - - hdmi-out { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_out: endpoint { - remote-endpoint = <&tda19988_out>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - led0 { - gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>; - label = "LED0"; - }; - - led1 { - gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; - label = "LED1"; - }; - - led2 { - gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>; - label = "LED2"; - }; - - led3 { - gpios = <&gpio6 4 GPIO_ACTIVE_HIGH>; - label = "LED3"; - }; - }; - - memory@48000000 { - device_type = "memory"; - /* first 128MB is reserved for secure area. */ - reg = <0x0 0x48000000 0x0 0x78000000>; - }; - - reg_12p0v: regulator-12p0v { - compatible = "regulator-fixed"; - regulator-name = "D12.0V"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-boot-on; - regulator-always-on; - }; - - sound: sound { - compatible = "simple-audio-card"; - - simple-audio-card,name = "CAT874 HDMI sound"; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&sndcpu>; - simple-audio-card,frame-master = <&sndcpu>; - - sndcodec: simple-audio-card,codec { - sound-dai = <&tda19988>; - }; - - sndcpu: simple-audio-card,cpu { - sound-dai = <&rcar_sound>; - }; - }; - - vcc_sdhi0: regulator-vcc-sdhi0 { - compatible = "regulator-fixed"; - - regulator-name = "SDHI0 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - vccq_sdhi0: regulator-vccq-sdhi0 { - compatible = "regulator-gpio"; - - regulator-name = "SDHI0 VccQ"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; - gpios-states = <1>; - states = <3300000 1>, <1800000 0>; - }; - - wlan_en_reg: fixedregulator { - compatible = "regulator-fixed"; - regulator-name = "wlan-en-regulator"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - startup-delay-us = <70000>; - - gpio = <&gpio2 25 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - x13_clk: x13 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <74250000>; - }; -}; - -&audio_clk_a { - clock-frequency = <22579200>; -}; - -&du { - pinctrl-0 = <&du_pins>; - pinctrl-names = "default"; - status = "okay"; - - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>, - <&x13_clk>; - clock-names = "du.0", "du.1", "dclkin.0"; - - ports { - port@0 { - endpoint { - remote-endpoint = <&tda19988_in>; - }; - }; - }; -}; - -&ehci0 { - dr_mode = "host"; - status = "okay"; -}; - -&extal_clk { - clock-frequency = <48000000>; -}; - -&hscif2 { - pinctrl-0 = <&hscif2_pins>; - pinctrl-names = "default"; - - uart-has-rtscts; - status = "okay"; - - bluetooth { - compatible = "ti,wl1837-st"; - enable-gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; - }; -}; - -&i2c0 { - status = "okay"; - clock-frequency = <100000>; - - hd3ss3220@47 { - compatible = "ti,hd3ss3220"; - reg = <0x47>; - interrupt-parent = <&gpio6>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - - connector { - compatible = "usb-c-connector"; - label = "USB-C"; - data-role = "dual"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - hd3ss3220_ep: endpoint { - remote-endpoint = <&usb3_role_switch>; - }; - }; - }; - }; - }; - - tda19988: tda19988@70 { - compatible = "nxp,tda998x"; - reg = <0x70>; - interrupt-parent = <&gpio1>; - interrupts = <1 IRQ_TYPE_LEVEL_LOW>; - - video-ports = <0x234501>; - - #sound-dai-cells = <0>; - audio-ports = ; - clocks = <&rcar_sound 1>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - tda19988_in: endpoint { - remote-endpoint = <&du_out_rgb>; - }; - }; - - port@1 { - reg = <1>; - tda19988_out: endpoint { - remote-endpoint = <&hdmi_con_out>; - }; - }; - }; - }; -}; - -&i2c1 { - pinctrl-0 = <&i2c1_pins>; - pinctrl-names = "default"; - - status = "okay"; - clock-frequency = <400000>; - - rtc@32 { - compatible = "epson,rx8571"; - reg = <0x32>; - }; -}; - -&lvds0 { - status = "okay"; - - clocks = <&cpg CPG_MOD 727>, <&x13_clk>, <&extal_clk>; - clock-names = "fck", "dclkin.0", "extal"; -}; - -&ohci0 { - dr_mode = "host"; - status = "okay"; -}; - -&pcie_bus_clk { - clock-frequency = <100000000>; -}; - -&pciec0 { - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; -}; - -&pfc { - du_pins: du { - groups = "du_rgb888", "du_clk_out_0", "du_sync", "du_disp", - "du_clk_in_0"; - function = "du"; - }; - - hscif2_pins: hscif2 { - groups = "hscif2_data_a", "hscif2_ctrl_a"; - function = "hscif2"; - }; - - i2c1_pins: i2c1 { - groups = "i2c1_b"; - function = "i2c1"; - }; - - scif2_pins: scif2 { - groups = "scif2_data_a"; - function = "scif2"; - }; - - sdhi0_pins: sd0 { - groups = "sdhi0_data4", "sdhi0_ctrl"; - function = "sdhi0"; - power-source = <3300>; - }; - - sdhi0_pins_uhs: sd0_uhs { - groups = "sdhi0_data4", "sdhi0_ctrl"; - function = "sdhi0"; - power-source = <1800>; - }; - - sdhi3_pins: sd3 { - groups = "sdhi3_data4", "sdhi3_ctrl"; - function = "sdhi3"; - power-source = <1800>; - }; - - sound_clk_pins: sound_clk { - groups = "audio_clkout1_a"; - function = "audio_clk"; - }; - - sound_pins: sound { - groups = "ssi01239_ctrl", "ssi0_data"; - function = "ssi"; - }; - - usb30_pins: usb30 { - groups = "usb30", "usb30_id"; - function = "usb30"; - }; -}; - -&rcar_sound { - pinctrl-0 = <&sound_pins &sound_clk_pins>; - pinctrl-names = "default"; - - /* Single DAI */ - #sound-dai-cells = <0>; - - /* audio_clkout0/1/2/3 */ - #clock-cells = <1>; - clock-frequency = <11289600>; - - status = "okay"; - - rcar_sound,dai { - dai0 { - playback = <&ssi0 &src0 &dvc0>; - }; - }; -}; - -&rwdt { - timeout-sec = <60>; - status = "okay"; -}; - -&scif2 { - pinctrl-0 = <&scif2_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&sdhi0 { - pinctrl-0 = <&sdhi0_pins>; - pinctrl-1 = <&sdhi0_pins_uhs>; - pinctrl-names = "default", "state_uhs"; - - vmmc-supply = <&vcc_sdhi0>; - vqmmc-supply = <&vccq_sdhi0>; - cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; - bus-width = <4>; - sd-uhs-sdr50; - sd-uhs-sdr104; - status = "okay"; -}; - -&sdhi3 { - status = "okay"; - pinctrl-0 = <&sdhi3_pins>; - pinctrl-names = "default"; - - vmmc-supply = <&wlan_en_reg>; - bus-width = <4>; - non-removable; - cap-power-off-card; - keep-power-in-suspend; - - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@2 { - compatible = "ti,wl1837"; - reg = <2>; - interrupt-parent = <&gpio1>; - interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; - }; -}; - -&usb2_phy0 { - renesas,no-otg-pins; - status = "okay"; -}; - -&usb3_peri0 { - companion = <&xhci0>; - status = "okay"; - usb-role-switch; - - port { - usb3_role_switch: endpoint { - remote-endpoint = <&hd3ss3220_ep>; - }; - }; -}; - -&xhci0 { - pinctrl-0 = <&usb30_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/renesas/r8a774c0-ek874-idk-2121wr.dts b/sys/gnu/dts/arm64/renesas/r8a774c0-ek874-idk-2121wr.dts deleted file mode 100644 index a7b27d09f6c..00000000000 --- a/sys/gnu/dts/arm64/renesas/r8a774c0-ek874-idk-2121wr.dts +++ /dev/null @@ -1,116 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the Silicon Linux RZ/G2E evaluation kit (EK874), - * connected to an Advantech IDK-2121WR 21.5" LVDS panel - * - * Copyright (C) 2019 Renesas Electronics Corp. - */ - -#include "r8a774c0-ek874.dts" - -/ { - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm5 0 50000>; - - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - - power-supply = <®_12p0v>; - enable-gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>; - }; - - panel-lvds { - compatible = "advantech,idk-2121wr", "panel-lvds"; - - width-mm = <476>; - height-mm = <268>; - - data-mapping = "vesa-24"; - - panel-timing { - clock-frequency = <148500000>; - hactive = <1920>; - vactive = <1080>; - hsync-len = <44>; - hfront-porch = <88>; - hback-porch = <148>; - vfront-porch = <4>; - vback-porch = <36>; - vsync-len = <5>; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dual-lvds-odd-pixels; - panel_in0: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - - port@1 { - reg = <1>; - dual-lvds-even-pixels; - panel_in1: endpoint { - remote-endpoint = <&lvds1_out>; - }; - }; - }; - }; -}; - -&gpio0 { - /* - * When GP0_17 is low LVDS[01] are connected to the LVDS connector - * When GP0_17 is high LVDS[01] are connected to the LT8918L - */ - lvds-connector-en-gpio{ - gpio-hog; - gpios = <17 GPIO_ACTIVE_HIGH>; - output-low; - line-name = "lvds-connector-en-gpio"; - }; -}; - -&lvds0 { - ports { - port@1 { - lvds0_out: endpoint { - remote-endpoint = <&panel_in0>; - }; - }; - }; -}; - -&lvds1 { - status = "okay"; - - clocks = <&cpg CPG_MOD 727>, <&x13_clk>, <&extal_clk>; - clock-names = "fck", "dclkin.0", "extal"; - - ports { - port@1 { - lvds1_out: endpoint { - remote-endpoint = <&panel_in1>; - }; - }; - }; -}; - -&pfc { - pwm5_pins: pwm5 { - groups = "pwm5_a"; - function = "pwm5"; - }; -}; - -&pwm5 { - pinctrl-0 = <&pwm5_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/renesas/r8a774c0-ek874.dts b/sys/gnu/dts/arm64/renesas/r8a774c0-ek874.dts deleted file mode 100644 index e7b6619ab22..00000000000 --- a/sys/gnu/dts/arm64/renesas/r8a774c0-ek874.dts +++ /dev/null @@ -1,14 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the Silicon Linux RZ/G2E evaluation kit (EK874) - * - * Copyright (C) 2019 Renesas Electronics Corp. - */ - -#include "r8a774c0-cat874.dts" -#include "cat875.dtsi" - -/ { - model = "Silicon Linux RZ/G2E evaluation kit EK874 (CAT874 + CAT875)"; - compatible = "si-linux,cat875", "si-linux,cat874", "renesas,r8a774c0"; -}; diff --git a/sys/gnu/dts/arm64/renesas/r8a774c0.dtsi b/sys/gnu/dts/arm64/renesas/r8a774c0.dtsi deleted file mode 100644 index a53cd5fcc40..00000000000 --- a/sys/gnu/dts/arm64/renesas/r8a774c0.dtsi +++ /dev/null @@ -1,1958 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the RZ/G2E (R8A774C0) SoC - * - * Copyright (C) 2018-2019 Renesas Electronics Corp. - */ - -#include -#include -#include - -/ { - compatible = "renesas,r8a774c0"; - #address-cells = <2>; - #size-cells = <2>; - - /* - * The external audio clocks are configured as 0 Hz fixed frequency - * clocks by default. - * Boards that provide audio clocks should override them. - */ - audio_clk_a: audio_clk_a { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - audio_clk_b: audio_clk_b { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - audio_clk_c: audio_clk_c { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - /* External CAN clock - to be overridden by boards that provide it */ - can_clk: can { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - cluster1_opp: opp_table10 { - compatible = "operating-points-v2"; - opp-shared; - opp-800000000 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <820000>; - clock-latency-ns = <300000>; - }; - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <820000>; - clock-latency-ns = <300000>; - }; - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <820000>; - clock-latency-ns = <300000>; - opp-suspend; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - a53_0: cpu@0 { - compatible = "arm,cortex-a53"; - reg = <0>; - device_type = "cpu"; - #cooling-cells = <2>; - power-domains = <&sysc R8A774C0_PD_CA53_CPU0>; - next-level-cache = <&L2_CA53>; - enable-method = "psci"; - dynamic-power-coefficient = <277>; - clocks = <&cpg CPG_CORE R8A774C0_CLK_Z2>; - operating-points-v2 = <&cluster1_opp>; - }; - - a53_1: cpu@1 { - compatible = "arm,cortex-a53"; - reg = <1>; - device_type = "cpu"; - power-domains = <&sysc R8A774C0_PD_CA53_CPU1>; - next-level-cache = <&L2_CA53>; - enable-method = "psci"; - clocks = <&cpg CPG_CORE R8A774C0_CLK_Z2>; - operating-points-v2 = <&cluster1_opp>; - }; - - L2_CA53: cache-controller-0 { - compatible = "cache"; - power-domains = <&sysc R8A774C0_PD_CA53_SCU>; - cache-unified; - cache-level = <2>; - }; - }; - - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board */ - clock-frequency = <0>; - }; - - /* External PCIe clock - can be overridden by the board */ - pcie_bus_clk: pcie_bus { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - pmu_a53 { - compatible = "arm,cortex-a53-pmu"; - interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&a53_0>, <&a53_1>; - }; - - psci { - compatible = "arm,psci-1.0", "arm,psci-0.2"; - method = "smc"; - }; - - /* External SCIF clock - to be overridden by boards that provide it */ - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - soc: soc { - compatible = "simple-bus"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - rwdt: watchdog@e6020000 { - compatible = "renesas,r8a774c0-wdt", - "renesas,rcar-gen3-wdt"; - reg = <0 0xe6020000 0 0x0c>; - clocks = <&cpg CPG_MOD 402>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 402>; - status = "disabled"; - }; - - gpio0: gpio@e6050000 { - compatible = "renesas,gpio-r8a774c0", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6050000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 0 18>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 912>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 912>; - }; - - gpio1: gpio@e6051000 { - compatible = "renesas,gpio-r8a774c0", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6051000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 32 23>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 911>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 911>; - }; - - gpio2: gpio@e6052000 { - compatible = "renesas,gpio-r8a774c0", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6052000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 64 26>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 910>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 910>; - }; - - gpio3: gpio@e6053000 { - compatible = "renesas,gpio-r8a774c0", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6053000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 96 16>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 909>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 909>; - }; - - gpio4: gpio@e6054000 { - compatible = "renesas,gpio-r8a774c0", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6054000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 128 11>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 908>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 908>; - }; - - gpio5: gpio@e6055000 { - compatible = "renesas,gpio-r8a774c0", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6055000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 160 20>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 907>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 907>; - }; - - gpio6: gpio@e6055400 { - compatible = "renesas,gpio-r8a774c0", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6055400 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 192 18>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 906>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 906>; - }; - - pfc: pin-controller@e6060000 { - compatible = "renesas,pfc-r8a774c0"; - reg = <0 0xe6060000 0 0x508>; - }; - - cmt0: timer@e60f0000 { - compatible = "renesas,r8a774c0-cmt0", - "renesas,rcar-gen3-cmt0"; - reg = <0 0xe60f0000 0 0x1004>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 303>; - clock-names = "fck"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 303>; - status = "disabled"; - }; - - cmt1: timer@e6130000 { - compatible = "renesas,r8a774c0-cmt1", - "renesas,rcar-gen3-cmt1"; - reg = <0 0xe6130000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 302>; - clock-names = "fck"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 302>; - status = "disabled"; - }; - - cmt2: timer@e6140000 { - compatible = "renesas,r8a774c0-cmt1", - "renesas,rcar-gen3-cmt1"; - reg = <0 0xe6140000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 301>; - clock-names = "fck"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 301>; - status = "disabled"; - }; - - cmt3: timer@e6148000 { - compatible = "renesas,r8a774c0-cmt1", - "renesas,rcar-gen3-cmt1"; - reg = <0 0xe6148000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 300>; - clock-names = "fck"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 300>; - status = "disabled"; - }; - - cpg: clock-controller@e6150000 { - compatible = "renesas,r8a774c0-cpg-mssr"; - reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk>; - clock-names = "extal"; - #clock-cells = <2>; - #power-domain-cells = <0>; - #reset-cells = <1>; - }; - - rst: reset-controller@e6160000 { - compatible = "renesas,r8a774c0-rst"; - reg = <0 0xe6160000 0 0x0200>; - }; - - sysc: system-controller@e6180000 { - compatible = "renesas,r8a774c0-sysc"; - reg = <0 0xe6180000 0 0x0400>; - #power-domain-cells = <1>; - }; - - thermal: thermal@e6190000 { - compatible = "renesas,thermal-r8a774c0"; - reg = <0 0xe6190000 0 0x10>, <0 0xe6190100 0 0x38>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 522>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 522>; - #thermal-sensor-cells = <0>; - }; - - intc_ex: interrupt-controller@e61c0000 { - compatible = "renesas,intc-ex-r8a774c0", "renesas,irqc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0 0xe61c0000 0 0x200>; - interrupts = , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 407>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 407>; - }; - - tmu0: timer@e61e0000 { - compatible = "renesas,tmu-r8a774c0", "renesas,tmu"; - reg = <0 0xe61e0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 125>; - clock-names = "fck"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 125>; - status = "disabled"; - }; - - tmu1: timer@e6fc0000 { - compatible = "renesas,tmu-r8a774c0", "renesas,tmu"; - reg = <0 0xe6fc0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 124>; - clock-names = "fck"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 124>; - status = "disabled"; - }; - - tmu2: timer@e6fd0000 { - compatible = "renesas,tmu-r8a774c0", "renesas,tmu"; - reg = <0 0xe6fd0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 123>; - clock-names = "fck"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 123>; - status = "disabled"; - }; - - tmu3: timer@e6fe0000 { - compatible = "renesas,tmu-r8a774c0", "renesas,tmu"; - reg = <0 0xe6fe0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 122>; - clock-names = "fck"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 122>; - status = "disabled"; - }; - - tmu4: timer@ffc00000 { - compatible = "renesas,tmu-r8a774c0", "renesas,tmu"; - reg = <0 0xffc00000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 121>; - clock-names = "fck"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 121>; - status = "disabled"; - }; - - i2c0: i2c@e6500000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a774c0", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6500000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 931>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 931>; - dmas = <&dmac1 0x91>, <&dmac1 0x90>, - <&dmac2 0x91>, <&dmac2 0x90>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c1: i2c@e6508000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a774c0", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6508000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 930>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 930>; - dmas = <&dmac1 0x93>, <&dmac1 0x92>, - <&dmac2 0x93>, <&dmac2 0x92>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c2: i2c@e6510000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a774c0", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6510000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 929>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 929>; - dmas = <&dmac1 0x95>, <&dmac1 0x94>, - <&dmac2 0x95>, <&dmac2 0x94>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c3: i2c@e66d0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a774c0", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66d0000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 928>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 928>; - dmas = <&dmac0 0x97>, <&dmac0 0x96>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c4: i2c@e66d8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a774c0", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66d8000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 927>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 927>; - dmas = <&dmac0 0x99>, <&dmac0 0x98>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c5: i2c@e66e0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a774c0", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66e0000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 919>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 919>; - dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c6: i2c@e66e8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a774c0", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66e8000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 918>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 918>; - dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c7: i2c@e6690000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a774c0", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6690000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 1003>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 1003>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c_dvfs: i2c@e60b0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a774c0"; - reg = <0 0xe60b0000 0 0x15>; - interrupts = ; - clocks = <&cpg CPG_MOD 926>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 926>; - dmas = <&dmac0 0x11>, <&dmac0 0x10>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - hscif0: serial@e6540000 { - compatible = "renesas,hscif-r8a774c0", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6540000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 520>, - <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x31>, <&dmac1 0x30>, - <&dmac2 0x31>, <&dmac2 0x30>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 520>; - status = "disabled"; - }; - - hscif1: serial@e6550000 { - compatible = "renesas,hscif-r8a774c0", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6550000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 519>, - <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x33>, <&dmac1 0x32>, - <&dmac2 0x33>, <&dmac2 0x32>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 519>; - status = "disabled"; - }; - - hscif2: serial@e6560000 { - compatible = "renesas,hscif-r8a774c0", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6560000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 518>, - <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x35>, <&dmac1 0x34>, - <&dmac2 0x35>, <&dmac2 0x34>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 518>; - status = "disabled"; - }; - - hscif3: serial@e66a0000 { - compatible = "renesas,hscif-r8a774c0", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe66a0000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 517>, - <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x37>, <&dmac0 0x36>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 517>; - status = "disabled"; - }; - - hscif4: serial@e66b0000 { - compatible = "renesas,hscif-r8a774c0", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe66b0000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 516>, - <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x39>, <&dmac0 0x38>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 516>; - status = "disabled"; - }; - - hsusb: usb@e6590000 { - compatible = "renesas,usbhs-r8a774c0", - "renesas,rcar-gen3-usbhs"; - reg = <0 0xe6590000 0 0x200>; - interrupts = ; - clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>; - dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, - <&usb_dmac1 0>, <&usb_dmac1 1>; - dma-names = "ch0", "ch1", "ch2", "ch3"; - renesas,buswait = <11>; - phys = <&usb2_phy0 3>; - phy-names = "usb"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 704>, <&cpg 703>; - status = "disabled"; - }; - - usb_dmac0: dma-controller@e65a0000 { - compatible = "renesas,r8a774c0-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65a0000 0 0x100>; - interrupts = , - ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 330>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 330>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - usb_dmac1: dma-controller@e65b0000 { - compatible = "renesas,r8a774c0-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65b0000 0 0x100>; - interrupts = , - ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 331>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 331>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - dmac0: dma-controller@e6700000 { - compatible = "renesas,dmac-r8a774c0", - "renesas,rcar-dmac"; - reg = <0 0xe6700000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 219>; - clock-names = "fck"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 219>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, - <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, - <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, - <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, - <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, - <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, - <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, - <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; - }; - - dmac1: dma-controller@e7300000 { - compatible = "renesas,dmac-r8a774c0", - "renesas,rcar-dmac"; - reg = <0 0xe7300000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 218>; - clock-names = "fck"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 218>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, - <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, - <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, - <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, - <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, - <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, - <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, - <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; - }; - - dmac2: dma-controller@e7310000 { - compatible = "renesas,dmac-r8a774c0", - "renesas,rcar-dmac"; - reg = <0 0xe7310000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 217>; - clock-names = "fck"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 217>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, - <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, - <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, - <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, - <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, - <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, - <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, - <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; - }; - - ipmmu_ds0: mmu@e6740000 { - compatible = "renesas,ipmmu-r8a774c0"; - reg = <0 0xe6740000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 0>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_ds1: mmu@e7740000 { - compatible = "renesas,ipmmu-r8a774c0"; - reg = <0 0xe7740000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 1>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_hc: mmu@e6570000 { - compatible = "renesas,ipmmu-r8a774c0"; - reg = <0 0xe6570000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 2>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_mm: mmu@e67b0000 { - compatible = "renesas,ipmmu-r8a774c0"; - reg = <0 0xe67b0000 0 0x1000>; - interrupts = , - ; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_mp: mmu@ec670000 { - compatible = "renesas,ipmmu-r8a774c0"; - reg = <0 0xec670000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 4>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_pv0: mmu@fd800000 { - compatible = "renesas,ipmmu-r8a774c0"; - reg = <0 0xfd800000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 6>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_vc0: mmu@fe6b0000 { - compatible = "renesas,ipmmu-r8a774c0"; - reg = <0 0xfe6b0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 12>; - power-domains = <&sysc R8A774C0_PD_A3VC>; - #iommu-cells = <1>; - }; - - ipmmu_vi0: mmu@febd0000 { - compatible = "renesas,ipmmu-r8a774c0"; - reg = <0 0xfebd0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 14>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_vp0: mmu@fe990000 { - compatible = "renesas,ipmmu-r8a774c0"; - reg = <0 0xfe990000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 16>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - avb: ethernet@e6800000 { - compatible = "renesas,etheravb-r8a774c0", - "renesas,etheravb-rcar-gen3"; - reg = <0 0xe6800000 0 0x800>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15", - "ch16", "ch17", "ch18", "ch19", - "ch20", "ch21", "ch22", "ch23", - "ch24"; - clocks = <&cpg CPG_MOD 812>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 812>; - phy-mode = "rgmii"; - iommus = <&ipmmu_ds0 16>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - can0: can@e6c30000 { - compatible = "renesas,can-r8a774c0", - "renesas,rcar-gen3-can"; - reg = <0 0xe6c30000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 916>, - <&cpg CPG_CORE R8A774C0_CLK_CANFD>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A774C0_CLK_CANFD>; - assigned-clock-rates = <40000000>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 916>; - status = "disabled"; - }; - - can1: can@e6c38000 { - compatible = "renesas,can-r8a774c0", - "renesas,rcar-gen3-can"; - reg = <0 0xe6c38000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 915>, - <&cpg CPG_CORE R8A774C0_CLK_CANFD>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A774C0_CLK_CANFD>; - assigned-clock-rates = <40000000>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 915>; - status = "disabled"; - }; - - canfd: can@e66c0000 { - compatible = "renesas,r8a774c0-canfd", - "renesas,rcar-gen3-canfd"; - reg = <0 0xe66c0000 0 0x8000>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 914>, - <&cpg CPG_CORE R8A774C0_CLK_CANFD>, - <&can_clk>; - clock-names = "fck", "canfd", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A774C0_CLK_CANFD>; - assigned-clock-rates = <40000000>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 914>; - status = "disabled"; - - channel0 { - status = "disabled"; - }; - - channel1 { - status = "disabled"; - }; - }; - - pwm0: pwm@e6e30000 { - compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar"; - reg = <0 0xe6e30000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm1: pwm@e6e31000 { - compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar"; - reg = <0 0xe6e31000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm2: pwm@e6e32000 { - compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar"; - reg = <0 0xe6e32000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm3: pwm@e6e33000 { - compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar"; - reg = <0 0xe6e33000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm4: pwm@e6e34000 { - compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar"; - reg = <0 0xe6e34000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm5: pwm@e6e35000 { - compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar"; - reg = <0 0xe6e35000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm6: pwm@e6e36000 { - compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar"; - reg = <0 0xe6e36000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - scif0: serial@e6e60000 { - compatible = "renesas,scif-r8a774c0", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e60000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 207>, - <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x51>, <&dmac1 0x50>, - <&dmac2 0x51>, <&dmac2 0x50>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 207>; - status = "disabled"; - }; - - scif1: serial@e6e68000 { - compatible = "renesas,scif-r8a774c0", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e68000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 206>, - <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x53>, <&dmac1 0x52>, - <&dmac2 0x53>, <&dmac2 0x52>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 206>; - status = "disabled"; - }; - - scif2: serial@e6e88000 { - compatible = "renesas,scif-r8a774c0", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e88000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 310>, - <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x13>, <&dmac1 0x12>, - <&dmac2 0x13>, <&dmac2 0x12>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 310>; - status = "disabled"; - }; - - scif3: serial@e6c50000 { - compatible = "renesas,scif-r8a774c0", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6c50000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 204>, - <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x57>, <&dmac0 0x56>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 204>; - status = "disabled"; - }; - - scif4: serial@e6c40000 { - compatible = "renesas,scif-r8a774c0", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6c40000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 203>, - <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x59>, <&dmac0 0x58>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 203>; - status = "disabled"; - }; - - scif5: serial@e6f30000 { - compatible = "renesas,scif-r8a774c0", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6f30000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 202>, - <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x5b>, <&dmac0 0x5a>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 202>; - status = "disabled"; - }; - - msiof0: spi@e6e90000 { - compatible = "renesas,msiof-r8a774c0", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6e90000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 211>; - dmas = <&dmac1 0x41>, <&dmac1 0x40>, - <&dmac2 0x41>, <&dmac2 0x40>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 211>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof1: spi@e6ea0000 { - compatible = "renesas,msiof-r8a774c0", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6ea0000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 210>; - dmas = <&dmac1 0x43>, <&dmac1 0x42>, - <&dmac2 0x43>, <&dmac2 0x42>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 210>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof2: spi@e6c00000 { - compatible = "renesas,msiof-r8a774c0", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6c00000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 209>; - dmas = <&dmac0 0x45>, <&dmac0 0x44>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 209>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof3: spi@e6c10000 { - compatible = "renesas,msiof-r8a774c0", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6c10000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 208>; - dmas = <&dmac0 0x47>, <&dmac0 0x46>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 208>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - vin4: video@e6ef4000 { - compatible = "renesas,vin-r8a774c0"; - reg = <0 0xe6ef4000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 807>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 807>; - renesas,id = <4>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin4csi40: endpoint@2 { - reg = <2>; - remote-endpoint= <&csi40vin4>; - }; - }; - }; - }; - - vin5: video@e6ef5000 { - compatible = "renesas,vin-r8a774c0"; - reg = <0 0xe6ef5000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 806>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 806>; - renesas,id = <5>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin5csi40: endpoint@2 { - reg = <2>; - remote-endpoint= <&csi40vin5>; - }; - }; - }; - }; - - rcar_sound: sound@ec500000 { - /* - * #sound-dai-cells is required - * - * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; - * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; - */ - /* - * #clock-cells is required for audio_clkout0/1/2/3 - * - * clkout : #clock-cells = <0>; <&rcar_sound>; - * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; - */ - compatible = "renesas,rcar_sound-r8a774c0", - "renesas,rcar_sound-gen3"; - reg = <0 0xec500000 0 0x1000>, /* SCU */ - <0 0xec5a0000 0 0x100>, /* ADG */ - <0 0xec540000 0 0x1000>, /* SSIU */ - <0 0xec541000 0 0x280>, /* SSI */ - <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ - reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; - - clocks = <&cpg CPG_MOD 1005>, - <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, - <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, - <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, - <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, - <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, - <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, - <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, - <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, - <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, - <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, - <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, - <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, - <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, - <&audio_clk_a>, <&audio_clk_b>, - <&audio_clk_c>, - <&cpg CPG_CORE R8A774C0_CLK_ZA2>; - clock-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", - "ssi.5", "ssi.4", "ssi.3", "ssi.2", - "ssi.1", "ssi.0", - "src.9", "src.8", "src.7", "src.6", - "src.5", "src.4", "src.3", "src.2", - "src.1", "src.0", - "mix.1", "mix.0", - "ctu.1", "ctu.0", - "dvc.0", "dvc.1", - "clk_a", "clk_b", "clk_c", "clk_i"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 1005>, - <&cpg 1006>, <&cpg 1007>, - <&cpg 1008>, <&cpg 1009>, - <&cpg 1010>, <&cpg 1011>, - <&cpg 1012>, <&cpg 1013>, - <&cpg 1014>, <&cpg 1015>; - reset-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", - "ssi.5", "ssi.4", "ssi.3", "ssi.2", - "ssi.1", "ssi.0"; - status = "disabled"; - - rcar_sound,ctu { - ctu00: ctu-0 { }; - ctu01: ctu-1 { }; - ctu02: ctu-2 { }; - ctu03: ctu-3 { }; - ctu10: ctu-4 { }; - ctu11: ctu-5 { }; - ctu12: ctu-6 { }; - ctu13: ctu-7 { }; - }; - - rcar_sound,dvc { - dvc0: dvc-0 { - dmas = <&audma0 0xbc>; - dma-names = "tx"; - }; - dvc1: dvc-1 { - dmas = <&audma0 0xbe>; - dma-names = "tx"; - }; - }; - - rcar_sound,mix { - mix0: mix-0 { }; - mix1: mix-1 { }; - }; - - rcar_sound,src { - src0: src-0 { - interrupts = ; - dmas = <&audma0 0x85>, <&audma0 0x9a>; - dma-names = "rx", "tx"; - }; - src1: src-1 { - interrupts = ; - dmas = <&audma0 0x87>, <&audma0 0x9c>; - dma-names = "rx", "tx"; - }; - src2: src-2 { - interrupts = ; - dmas = <&audma0 0x89>, <&audma0 0x9e>; - dma-names = "rx", "tx"; - }; - src3: src-3 { - interrupts = ; - dmas = <&audma0 0x8b>, <&audma0 0xa0>; - dma-names = "rx", "tx"; - }; - src4: src-4 { - interrupts = ; - dmas = <&audma0 0x8d>, <&audma0 0xb0>; - dma-names = "rx", "tx"; - }; - src5: src-5 { - interrupts = ; - dmas = <&audma0 0x8f>, <&audma0 0xb2>; - dma-names = "rx", "tx"; - }; - src6: src-6 { - interrupts = ; - dmas = <&audma0 0x91>, <&audma0 0xb4>; - dma-names = "rx", "tx"; - }; - src7: src-7 { - interrupts = ; - dmas = <&audma0 0x93>, <&audma0 0xb6>; - dma-names = "rx", "tx"; - }; - src8: src-8 { - interrupts = ; - dmas = <&audma0 0x95>, <&audma0 0xb8>; - dma-names = "rx", "tx"; - }; - src9: src-9 { - interrupts = ; - dmas = <&audma0 0x97>, <&audma0 0xba>; - dma-names = "rx", "tx"; - }; - }; - - rcar_sound,ssi { - ssi0: ssi-0 { - interrupts = ; - dmas = <&audma0 0x01>, <&audma0 0x02>, - <&audma0 0x15>, <&audma0 0x16>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi1: ssi-1 { - interrupts = ; - dmas = <&audma0 0x03>, <&audma0 0x04>, - <&audma0 0x49>, <&audma0 0x4a>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi2: ssi-2 { - interrupts = ; - dmas = <&audma0 0x05>, <&audma0 0x06>, - <&audma0 0x63>, <&audma0 0x64>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi3: ssi-3 { - interrupts = ; - dmas = <&audma0 0x07>, <&audma0 0x08>, - <&audma0 0x6f>, <&audma0 0x70>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi4: ssi-4 { - interrupts = ; - dmas = <&audma0 0x09>, <&audma0 0x0a>, - <&audma0 0x71>, <&audma0 0x72>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi5: ssi-5 { - interrupts = ; - dmas = <&audma0 0x0b>, <&audma0 0x0c>, - <&audma0 0x73>, <&audma0 0x74>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi6: ssi-6 { - interrupts = ; - dmas = <&audma0 0x0d>, <&audma0 0x0e>, - <&audma0 0x75>, <&audma0 0x76>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi7: ssi-7 { - interrupts = ; - dmas = <&audma0 0x0f>, <&audma0 0x10>, - <&audma0 0x79>, <&audma0 0x7a>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi8: ssi-8 { - interrupts = ; - dmas = <&audma0 0x11>, <&audma0 0x12>, - <&audma0 0x7b>, <&audma0 0x7c>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi9: ssi-9 { - interrupts = ; - dmas = <&audma0 0x13>, <&audma0 0x14>, - <&audma0 0x7d>, <&audma0 0x7e>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - }; - }; - - audma0: dma-controller@ec700000 { - compatible = "renesas,dmac-r8a774c0", - "renesas,rcar-dmac"; - reg = <0 0xec700000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 502>; - clock-names = "fck"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 502>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>, - <&ipmmu_mp 2>, <&ipmmu_mp 3>, - <&ipmmu_mp 4>, <&ipmmu_mp 5>, - <&ipmmu_mp 6>, <&ipmmu_mp 7>, - <&ipmmu_mp 8>, <&ipmmu_mp 9>, - <&ipmmu_mp 10>, <&ipmmu_mp 11>, - <&ipmmu_mp 12>, <&ipmmu_mp 13>, - <&ipmmu_mp 14>, <&ipmmu_mp 15>; - }; - - xhci0: usb@ee000000 { - compatible = "renesas,xhci-r8a774c0", - "renesas,rcar-gen3-xhci"; - reg = <0 0xee000000 0 0xc00>; - interrupts = ; - clocks = <&cpg CPG_MOD 328>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 328>; - status = "disabled"; - }; - - usb3_peri0: usb@ee020000 { - compatible = "renesas,r8a774c0-usb3-peri", - "renesas,rcar-gen3-usb3-peri"; - reg = <0 0xee020000 0 0x400>; - interrupts = ; - clocks = <&cpg CPG_MOD 328>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 328>; - status = "disabled"; - }; - - ohci0: usb@ee080000 { - compatible = "generic-ohci"; - reg = <0 0xee080000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; - phys = <&usb2_phy0 1>; - phy-names = "usb"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 703>, <&cpg 704>; - status = "disabled"; - }; - - ehci0: usb@ee080100 { - compatible = "generic-ehci"; - reg = <0 0xee080100 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; - phys = <&usb2_phy0 2>; - phy-names = "usb"; - companion = <&ohci0>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 703>, <&cpg 704>; - status = "disabled"; - }; - - usb2_phy0: usb-phy@ee080200 { - compatible = "renesas,usb2-phy-r8a774c0", - "renesas,rcar-gen3-usb2-phy"; - reg = <0 0xee080200 0 0x700>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 703>, <&cpg 704>; - #phy-cells = <1>; - status = "disabled"; - }; - - sdhi0: sd@ee100000 { - compatible = "renesas,sdhi-r8a774c0", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee100000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 314>; - max-frequency = <200000000>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 314>; - status = "disabled"; - }; - - sdhi1: sd@ee120000 { - compatible = "renesas,sdhi-r8a774c0", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee120000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 313>; - max-frequency = <200000000>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 313>; - status = "disabled"; - }; - - sdhi3: sd@ee160000 { - compatible = "renesas,sdhi-r8a774c0", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee160000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 311>; - max-frequency = <200000000>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 311>; - status = "disabled"; - }; - - gic: interrupt-controller@f1010000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x0 0xf1010000 0 0x1000>, - <0x0 0xf1020000 0 0x20000>, - <0x0 0xf1040000 0 0x20000>, - <0x0 0xf1060000 0 0x20000>; - interrupts = ; - clocks = <&cpg CPG_MOD 408>; - clock-names = "clk"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 408>; - }; - - pciec0: pcie@fe000000 { - compatible = "renesas,pcie-r8a774c0", - "renesas,pcie-rcar-gen3"; - reg = <0 0xfe000000 0 0x80000>; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x00 0xff>; - device_type = "pci"; - ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, - <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, - <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, - <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>; - interrupts = , - , - ; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; - clock-names = "pcie", "pcie_bus"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 319>; - status = "disabled"; - }; - - vspb0: vsp@fe960000 { - compatible = "renesas,vsp2"; - reg = <0 0xfe960000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 626>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 626>; - renesas,fcp = <&fcpvb0>; - }; - - vspd0: vsp@fea20000 { - compatible = "renesas,vsp2"; - reg = <0 0xfea20000 0 0x7000>; - interrupts = ; - clocks = <&cpg CPG_MOD 623>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 623>; - renesas,fcp = <&fcpvd0>; - }; - - vspd1: vsp@fea28000 { - compatible = "renesas,vsp2"; - reg = <0 0xfea28000 0 0x7000>; - interrupts = ; - clocks = <&cpg CPG_MOD 622>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 622>; - renesas,fcp = <&fcpvd1>; - }; - - vspi0: vsp@fe9a0000 { - compatible = "renesas,vsp2"; - reg = <0 0xfe9a0000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 631>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 631>; - renesas,fcp = <&fcpvi0>; - }; - - fcpvb0: fcp@fe96f000 { - compatible = "renesas,fcpv"; - reg = <0 0xfe96f000 0 0x200>; - clocks = <&cpg CPG_MOD 607>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 607>; - iommus = <&ipmmu_vp0 5>; - }; - - fcpvd0: fcp@fea27000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea27000 0 0x200>; - clocks = <&cpg CPG_MOD 603>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 603>; - iommus = <&ipmmu_vi0 8>; - }; - - fcpvd1: fcp@fea2f000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea2f000 0 0x200>; - clocks = <&cpg CPG_MOD 602>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 602>; - iommus = <&ipmmu_vi0 9>; - }; - - fcpvi0: fcp@fe9af000 { - compatible = "renesas,fcpv"; - reg = <0 0xfe9af000 0 0x200>; - clocks = <&cpg CPG_MOD 611>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 611>; - iommus = <&ipmmu_vp0 8>; - }; - - csi40: csi2@feaa0000 { - compatible = "renesas,r8a774c0-csi2"; - reg = <0 0xfeaa0000 0 0x10000>; - interrupts = ; - clocks = <&cpg CPG_MOD 716>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 716>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - csi40vin4: endpoint@0 { - reg = <0>; - remote-endpoint = <&vin4csi40>; - }; - csi40vin5: endpoint@1 { - reg = <1>; - remote-endpoint = <&vin5csi40>; - }; - }; - }; - }; - - du: display@feb00000 { - compatible = "renesas,du-r8a774c0"; - reg = <0 0xfeb00000 0 0x40000>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>; - clock-names = "du.0", "du.1"; - vsps = <&vspd0 0>, <&vspd1 0>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - du_out_rgb: endpoint { - }; - }; - - port@1 { - reg = <1>; - du_out_lvds0: endpoint { - remote-endpoint = <&lvds0_in>; - }; - }; - - port@2 { - reg = <2>; - du_out_lvds1: endpoint { - remote-endpoint = <&lvds1_in>; - }; - }; - }; - }; - - lvds0: lvds-encoder@feb90000 { - compatible = "renesas,r8a774c0-lvds"; - reg = <0 0xfeb90000 0 0x20>; - clocks = <&cpg CPG_MOD 727>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 727>; - status = "disabled"; - - renesas,companion = <&lvds1>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - lvds0_in: endpoint { - remote-endpoint = <&du_out_lvds0>; - }; - }; - - port@1 { - reg = <1>; - lvds0_out: endpoint { - }; - }; - }; - }; - - lvds1: lvds-encoder@feb90100 { - compatible = "renesas,r8a774c0-lvds"; - reg = <0 0xfeb90100 0 0x20>; - clocks = <&cpg CPG_MOD 727>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 726>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - lvds1_in: endpoint { - remote-endpoint = <&du_out_lvds1>; - }; - }; - - port@1 { - reg = <1>; - lvds1_out: endpoint { - }; - }; - }; - }; - - prr: chipid@fff00044 { - compatible = "renesas,prr"; - reg = <0 0xfff00044 0 4>; - }; - }; - - thermal-zones { - cpu-thermal { - polling-delay-passive = <250>; - polling-delay = <0>; - thermal-sensors = <&thermal 0>; - sustainable-power = <717>; - - cooling-maps { - map0 { - trip = <&target>; - cooling-device = <&a53_0 0 2>; - contribution = <1024>; - }; - }; - - trips { - sensor1_crit: sensor1-crit { - temperature = <120000>; - hysteresis = <2000>; - type = "critical"; - }; - - target: trip-point1 { - temperature = <100000>; - hysteresis = <2000>; - type = "passive"; - }; - }; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; - }; - - /* External USB clocks - can be overridden by the board */ - usb3s0_clk: usb3s0 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - usb_extal_clk: usb_extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; -}; diff --git a/sys/gnu/dts/arm64/renesas/r8a77950-salvator-x.dts b/sys/gnu/dts/arm64/renesas/r8a77950-salvator-x.dts deleted file mode 100644 index 2438825c9b2..00000000000 --- a/sys/gnu/dts/arm64/renesas/r8a77950-salvator-x.dts +++ /dev/null @@ -1,157 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the Salvator-X board with R-Car H3 ES1.x - * - * Copyright (C) 2015 Renesas Electronics Corp. - */ - -/dts-v1/; -#include "r8a77950.dtsi" -#include "salvator-x.dtsi" - -/ { - model = "Renesas Salvator-X board based on r8a77950"; - compatible = "renesas,salvator-x", "renesas,r8a7795"; - - memory@48000000 { - device_type = "memory"; - /* first 128MB is reserved for secure area. */ - reg = <0x0 0x48000000 0x0 0x38000000>; - }; - - memory@500000000 { - device_type = "memory"; - reg = <0x5 0x00000000 0x0 0x40000000>; - }; - - memory@600000000 { - device_type = "memory"; - reg = <0x6 0x00000000 0x0 0x40000000>; - }; - - memory@700000000 { - device_type = "memory"; - reg = <0x7 0x00000000 0x0 0x40000000>; - }; -}; - -&du { - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>, - <&cpg CPG_MOD 722>, - <&cpg CPG_MOD 721>, - <&versaclock5 1>, - <&x21_clk>, - <&x22_clk>, - <&versaclock5 2>; - clock-names = "du.0", "du.1", "du.2", "du.3", - "dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3"; -}; - -&ehci2 { - status = "okay"; -}; - -&hdmi0 { - status = "okay"; - - ports { - port@1 { - reg = <1>; - rcar_dw_hdmi0_out: endpoint { - remote-endpoint = <&hdmi0_con>; - }; - }; - port@2 { - reg = <2>; - dw_hdmi0_snd_in: endpoint { - remote-endpoint = <&rsnd_endpoint1>; - }; - }; - }; -}; - -&hdmi0_con { - remote-endpoint = <&rcar_dw_hdmi0_out>; -}; - -&hdmi1 { - status = "okay"; - - ports { - port@1 { - reg = <1>; - rcar_dw_hdmi1_out: endpoint { - remote-endpoint = <&hdmi1_con>; - }; - }; - port@2 { - reg = <2>; - dw_hdmi1_snd_in: endpoint { - remote-endpoint = <&rsnd_endpoint2>; - }; - }; - }; -}; - -&hdmi1_con { - remote-endpoint = <&rcar_dw_hdmi1_out>; -}; - -&ohci2 { - status = "okay"; -}; - -&pfc { - usb2_pins: usb2 { - groups = "usb2"; - function = "usb2"; - }; -}; - -&rcar_sound { - ports { - /* rsnd_port0 is on salvator-common */ - rsnd_port1: port@1 { - reg = <1>; - rsnd_endpoint1: endpoint { - remote-endpoint = <&dw_hdmi0_snd_in>; - - dai-format = "i2s"; - bitclock-master = <&rsnd_endpoint1>; - frame-master = <&rsnd_endpoint1>; - - playback = <&ssi2>; - }; - }; - rsnd_port2: port@2 { - reg = <2>; - rsnd_endpoint2: endpoint { - remote-endpoint = <&dw_hdmi1_snd_in>; - - dai-format = "i2s"; - bitclock-master = <&rsnd_endpoint2>; - frame-master = <&rsnd_endpoint2>; - - playback = <&ssi3>; - }; - }; - }; -}; - -&sata { - status = "okay"; -}; - -&sound_card { - dais = <&rsnd_port0 /* ak4613 */ - &rsnd_port1 /* HDMI0 */ - &rsnd_port2>; /* HDMI1 */ -}; - -&usb2_phy2 { - pinctrl-0 = <&usb2_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/renesas/r8a77950-ulcb-kf.dts b/sys/gnu/dts/arm64/renesas/r8a77950-ulcb-kf.dts deleted file mode 100644 index dcaaf12cec4..00000000000 --- a/sys/gnu/dts/arm64/renesas/r8a77950-ulcb-kf.dts +++ /dev/null @@ -1,16 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the H3ULCB Kingfisher board - * - * Copyright (C) 2017 Renesas Electronics Corp. - * Copyright (C) 2017 Cogent Embedded, Inc. - */ - -#include "r8a77950-ulcb.dts" -#include "ulcb-kf.dtsi" - -/ { - model = "Renesas H3ULCB Kingfisher board based on r8a77950"; - compatible = "shimafuji,kingfisher", "renesas,h3ulcb", - "renesas,r8a7795"; -}; diff --git a/sys/gnu/dts/arm64/renesas/r8a77950-ulcb.dts b/sys/gnu/dts/arm64/renesas/r8a77950-ulcb.dts deleted file mode 100644 index 38a6d6a108d..00000000000 --- a/sys/gnu/dts/arm64/renesas/r8a77950-ulcb.dts +++ /dev/null @@ -1,37 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the H3ULCB (R-Car Starter Kit Premier) board - * - * Copyright (C) 2016 Renesas Electronics Corp. - * Copyright (C) 2016 Cogent Embedded, Inc. - */ - -/dts-v1/; -#include "r8a77950.dtsi" -#include "ulcb.dtsi" - -/ { - model = "Renesas H3ULCB board based on r8a77950"; - compatible = "renesas,h3ulcb", "renesas,r8a7795"; - - memory@48000000 { - device_type = "memory"; - /* first 128MB is reserved for secure area. */ - reg = <0x0 0x48000000 0x0 0x38000000>; - }; - - memory@500000000 { - device_type = "memory"; - reg = <0x5 0x00000000 0x0 0x40000000>; - }; - - memory@600000000 { - device_type = "memory"; - reg = <0x6 0x00000000 0x0 0x40000000>; - }; - - memory@700000000 { - device_type = "memory"; - reg = <0x7 0x00000000 0x0 0x40000000>; - }; -}; diff --git a/sys/gnu/dts/arm64/renesas/r8a77950.dtsi b/sys/gnu/dts/arm64/renesas/r8a77950.dtsi deleted file mode 100644 index 15216495e1c..00000000000 --- a/sys/gnu/dts/arm64/renesas/r8a77950.dtsi +++ /dev/null @@ -1,319 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the R-Car H3 (R8A77950) SoC - * - * Copyright (C) 2015 Renesas Electronics Corp. - */ - -#include "r8a77951.dtsi" - -&audma0 { - iommus = <&ipmmu_mp1 0>, <&ipmmu_mp1 1>, - <&ipmmu_mp1 2>, <&ipmmu_mp1 3>, - <&ipmmu_mp1 4>, <&ipmmu_mp1 5>, - <&ipmmu_mp1 6>, <&ipmmu_mp1 7>, - <&ipmmu_mp1 8>, <&ipmmu_mp1 9>, - <&ipmmu_mp1 10>, <&ipmmu_mp1 11>, - <&ipmmu_mp1 12>, <&ipmmu_mp1 13>, - <&ipmmu_mp1 14>, <&ipmmu_mp1 15>; -}; - -&audma1 { - iommus = <&ipmmu_mp1 16>, <&ipmmu_mp1 17>, - <&ipmmu_mp1 18>, <&ipmmu_mp1 19>, - <&ipmmu_mp1 20>, <&ipmmu_mp1 21>, - <&ipmmu_mp1 22>, <&ipmmu_mp1 23>, - <&ipmmu_mp1 24>, <&ipmmu_mp1 25>, - <&ipmmu_mp1 26>, <&ipmmu_mp1 27>, - <&ipmmu_mp1 28>, <&ipmmu_mp1 29>, - <&ipmmu_mp1 30>, <&ipmmu_mp1 31>; -}; - -&du { - vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>, <&vspd3 0>; -}; - -&fcpvb1 { - iommus = <&ipmmu_vp0 7>; -}; - -&fcpf1 { - iommus = <&ipmmu_vp0 1>; -}; - -&fcpvi1 { - iommus = <&ipmmu_vp0 9>; -}; - -&fcpvd2 { - iommus = <&ipmmu_vi0 10>; -}; - -&gpio1 { - gpio-ranges = <&pfc 0 32 28>; -}; - -&ipmmu_vi0 { - renesas,ipmmu-main = <&ipmmu_mm 11>; -}; - -&ipmmu_vp0 { - renesas,ipmmu-main = <&ipmmu_mm 12>; -}; - -&ipmmu_vc0 { - renesas,ipmmu-main = <&ipmmu_mm 9>; -}; - -&ipmmu_vc1 { - renesas,ipmmu-main = <&ipmmu_mm 10>; -}; - -&ipmmu_rt { - renesas,ipmmu-main = <&ipmmu_mm 7>; -}; - -&soc { - /delete-node/ dma-controller@e6460000; - /delete-node/ dma-controller@e6470000; - - ipmmu_mp1: mmu@ec680000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xec680000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 5>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_sy: mmu@e7730000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xe7730000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 8>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - /delete-node/ mmu@fd950000; - /delete-node/ mmu@fd960000; - /delete-node/ mmu@fd970000; - /delete-node/ mmu@febe0000; - /delete-node/ mmu@fe980000; - - xhci1: usb@ee040000 { - compatible = "renesas,xhci-r8a7795", "renesas,rcar-gen3-xhci"; - reg = <0 0xee040000 0 0xc00>; - interrupts = ; - clocks = <&cpg CPG_MOD 327>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 327>; - status = "disabled"; - }; - - /delete-node/ usb@e659c000; - /delete-node/ usb@ee0e0000; - /delete-node/ usb@ee0e0100; - - /delete-node/ usb-phy@ee0e0200; - - fdp1@fe948000 { - compatible = "renesas,fdp1"; - reg = <0 0xfe948000 0 0x2400>; - interrupts = ; - clocks = <&cpg CPG_MOD 117>; - power-domains = <&sysc R8A7795_PD_A3VP>; - resets = <&cpg 117>; - renesas,fcp = <&fcpf2>; - }; - - fcpf2: fcp@fe952000 { - compatible = "renesas,fcpf"; - reg = <0 0xfe952000 0 0x200>; - clocks = <&cpg CPG_MOD 613>; - power-domains = <&sysc R8A7795_PD_A3VP>; - resets = <&cpg 613>; - iommus = <&ipmmu_vp0 2>; - }; - - fcpvd3: fcp@fea3f000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea3f000 0 0x200>; - clocks = <&cpg CPG_MOD 600>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 600>; - iommus = <&ipmmu_vi0 11>; - }; - - fcpvi2: fcp@fe9cf000 { - compatible = "renesas,fcpv"; - reg = <0 0xfe9cf000 0 0x200>; - clocks = <&cpg CPG_MOD 609>; - power-domains = <&sysc R8A7795_PD_A3VP>; - resets = <&cpg 609>; - iommus = <&ipmmu_vp0 10>; - }; - - vspd3: vsp@fea38000 { - compatible = "renesas,vsp2"; - reg = <0 0xfea38000 0 0x5000>; - interrupts = ; - clocks = <&cpg CPG_MOD 620>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 620>; - - renesas,fcp = <&fcpvd3>; - }; - - vspi2: vsp@fe9c0000 { - compatible = "renesas,vsp2"; - reg = <0 0xfe9c0000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 629>; - power-domains = <&sysc R8A7795_PD_A3VP>; - resets = <&cpg 629>; - - renesas,fcp = <&fcpvi2>; - }; - - csi21: csi2@fea90000 { - compatible = "renesas,r8a7795-csi2"; - reg = <0 0xfea90000 0 0x10000>; - interrupts = ; - clocks = <&cpg CPG_MOD 713>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 713>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - csi21vin0: endpoint@0 { - reg = <0>; - remote-endpoint = <&vin0csi21>; - }; - csi21vin1: endpoint@1 { - reg = <1>; - remote-endpoint = <&vin1csi21>; - }; - csi21vin2: endpoint@2 { - reg = <2>; - remote-endpoint = <&vin2csi21>; - }; - csi21vin3: endpoint@3 { - reg = <3>; - remote-endpoint = <&vin3csi21>; - }; - csi21vin4: endpoint@4 { - reg = <4>; - remote-endpoint = <&vin4csi21>; - }; - csi21vin5: endpoint@5 { - reg = <5>; - remote-endpoint = <&vin5csi21>; - }; - csi21vin6: endpoint@6 { - reg = <6>; - remote-endpoint = <&vin6csi21>; - }; - csi21vin7: endpoint@7 { - reg = <7>; - remote-endpoint = <&vin7csi21>; - }; - }; - }; - }; -}; - -&vin0 { - ports { - port@1 { - vin0csi21: endpoint@1 { - reg = <1>; - remote-endpoint = <&csi21vin0>; - }; - }; - }; -}; - -&vin1 { - ports { - port@1 { - vin1csi21: endpoint@1 { - reg = <1>; - remote-endpoint = <&csi21vin1>; - }; - }; - }; -}; - -&vin2 { - ports { - port@1 { - vin2csi21: endpoint@1 { - reg = <1>; - remote-endpoint = <&csi21vin2>; - }; - }; - }; -}; - -&vin3 { - ports { - port@1 { - vin3csi21: endpoint@1 { - reg = <1>; - remote-endpoint = <&csi21vin3>; - }; - }; - }; -}; - -&vin4 { - ports { - port@1 { - vin4csi21: endpoint@1 { - reg = <1>; - remote-endpoint = <&csi21vin4>; - }; - }; - }; -}; - -&vin5 { - ports { - port@1 { - vin5csi21: endpoint@1 { - reg = <1>; - remote-endpoint = <&csi21vin5>; - }; - }; - }; -}; - -&vin6 { - ports { - port@1 { - vin6csi21: endpoint@1 { - reg = <1>; - remote-endpoint = <&csi21vin6>; - }; - }; - }; -}; - -&vin7 { - ports { - port@1 { - vin7csi21: endpoint@1 { - reg = <1>; - remote-endpoint = <&csi21vin7>; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/renesas/r8a77951-salvator-x.dts b/sys/gnu/dts/arm64/renesas/r8a77951-salvator-x.dts deleted file mode 100644 index a402a2fb6e3..00000000000 --- a/sys/gnu/dts/arm64/renesas/r8a77951-salvator-x.dts +++ /dev/null @@ -1,157 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the Salvator-X board with R-Car H3 ES2.0 - * - * Copyright (C) 2015 Renesas Electronics Corp. - */ - -/dts-v1/; -#include "r8a77951.dtsi" -#include "salvator-x.dtsi" - -/ { - model = "Renesas Salvator-X board based on r8a77951"; - compatible = "renesas,salvator-x", "renesas,r8a7795"; - - memory@48000000 { - device_type = "memory"; - /* first 128MB is reserved for secure area. */ - reg = <0x0 0x48000000 0x0 0x38000000>; - }; - - memory@500000000 { - device_type = "memory"; - reg = <0x5 0x00000000 0x0 0x40000000>; - }; - - memory@600000000 { - device_type = "memory"; - reg = <0x6 0x00000000 0x0 0x40000000>; - }; - - memory@700000000 { - device_type = "memory"; - reg = <0x7 0x00000000 0x0 0x40000000>; - }; -}; - -&du { - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>, - <&cpg CPG_MOD 722>, - <&cpg CPG_MOD 721>, - <&versaclock5 1>, - <&x21_clk>, - <&x22_clk>, - <&versaclock5 2>; - clock-names = "du.0", "du.1", "du.2", "du.3", - "dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3"; -}; - -&ehci2 { - status = "okay"; -}; - -&hdmi0 { - status = "okay"; - - ports { - port@1 { - reg = <1>; - rcar_dw_hdmi0_out: endpoint { - remote-endpoint = <&hdmi0_con>; - }; - }; - port@2 { - reg = <2>; - dw_hdmi0_snd_in: endpoint { - remote-endpoint = <&rsnd_endpoint1>; - }; - }; - }; -}; - -&hdmi0_con { - remote-endpoint = <&rcar_dw_hdmi0_out>; -}; - -&hdmi1 { - status = "okay"; - - ports { - port@1 { - reg = <1>; - rcar_dw_hdmi1_out: endpoint { - remote-endpoint = <&hdmi1_con>; - }; - }; - port@2 { - reg = <2>; - dw_hdmi1_snd_in: endpoint { - remote-endpoint = <&rsnd_endpoint2>; - }; - }; - }; -}; - -&hdmi1_con { - remote-endpoint = <&rcar_dw_hdmi1_out>; -}; - -&ohci2 { - status = "okay"; -}; - -&pfc { - usb2_pins: usb2 { - groups = "usb2"; - function = "usb2"; - }; -}; - -&rcar_sound { - ports { - /* rsnd_port0 is on salvator-common */ - rsnd_port1: port@1 { - reg = <1>; - rsnd_endpoint1: endpoint { - remote-endpoint = <&dw_hdmi0_snd_in>; - - dai-format = "i2s"; - bitclock-master = <&rsnd_endpoint1>; - frame-master = <&rsnd_endpoint1>; - - playback = <&ssi2>; - }; - }; - rsnd_port2: port@2 { - reg = <2>; - rsnd_endpoint2: endpoint { - remote-endpoint = <&dw_hdmi1_snd_in>; - - dai-format = "i2s"; - bitclock-master = <&rsnd_endpoint2>; - frame-master = <&rsnd_endpoint2>; - - playback = <&ssi3>; - }; - }; - }; -}; - -&sata { - status = "okay"; -}; - -&sound_card { - dais = <&rsnd_port0 /* ak4613 */ - &rsnd_port1 /* HDMI0 */ - &rsnd_port2>; /* HDMI1 */ -}; - -&usb2_phy2 { - pinctrl-0 = <&usb2_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/renesas/r8a77951-salvator-xs.dts b/sys/gnu/dts/arm64/renesas/r8a77951-salvator-xs.dts deleted file mode 100644 index cef9da4376a..00000000000 --- a/sys/gnu/dts/arm64/renesas/r8a77951-salvator-xs.dts +++ /dev/null @@ -1,206 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the Salvator-X 2nd version board with R-Car H3 ES2.0+ - * - * Copyright (C) 2015-2017 Renesas Electronics Corp. - */ - -/dts-v1/; -#include "r8a77951.dtsi" -#include "salvator-xs.dtsi" - -/ { - model = "Renesas Salvator-X 2nd version board based on r8a77951"; - compatible = "renesas,salvator-xs", "renesas,r8a7795"; - - memory@48000000 { - device_type = "memory"; - /* first 128MB is reserved for secure area. */ - reg = <0x0 0x48000000 0x0 0x38000000>; - }; - - memory@500000000 { - device_type = "memory"; - reg = <0x5 0x00000000 0x0 0x40000000>; - }; - - memory@600000000 { - device_type = "memory"; - reg = <0x6 0x00000000 0x0 0x40000000>; - }; - - memory@700000000 { - device_type = "memory"; - reg = <0x7 0x00000000 0x0 0x40000000>; - }; -}; - -&du { - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>, - <&cpg CPG_MOD 722>, - <&cpg CPG_MOD 721>, - <&versaclock6 1>, - <&x21_clk>, - <&x22_clk>, - <&versaclock6 2>; - clock-names = "du.0", "du.1", "du.2", "du.3", - "dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3"; -}; - -&ehci2 { - status = "okay"; -}; - -&ehci3 { - dr_mode = "otg"; - status = "okay"; -}; - -&hdmi0 { - status = "okay"; - - ports { - port@1 { - reg = <1>; - rcar_dw_hdmi0_out: endpoint { - remote-endpoint = <&hdmi0_con>; - }; - }; - port@2 { - reg = <2>; - dw_hdmi0_snd_in: endpoint { - remote-endpoint = <&rsnd_endpoint1>; - }; - }; - }; -}; - -&hdmi0_con { - remote-endpoint = <&rcar_dw_hdmi0_out>; -}; - -&hdmi1 { - status = "okay"; - - ports { - port@1 { - reg = <1>; - rcar_dw_hdmi1_out: endpoint { - remote-endpoint = <&hdmi1_con>; - }; - }; - port@2 { - reg = <2>; - dw_hdmi1_snd_in: endpoint { - remote-endpoint = <&rsnd_endpoint2>; - }; - }; - }; -}; - -&hdmi1_con { - remote-endpoint = <&rcar_dw_hdmi1_out>; -}; - -&hsusb3 { - dr_mode = "otg"; - status = "okay"; -}; - -&ohci2 { - status = "okay"; -}; - -&ohci3 { - dr_mode = "otg"; - status = "okay"; -}; - -&pca9654 { - pcie_sata_switch { - gpio-hog; - gpios = <7 GPIO_ACTIVE_HIGH>; - output-low; /* enable SATA by default */ - line-name = "PCIE/SATA switch"; - }; -}; - -&pfc { - usb2_pins: usb2 { - groups = "usb2"; - function = "usb2"; - }; - - /* - * - On Salvator-X[S], GP6_3[01] are connected to ADV7482 as irq pins - * (when SW31 is the default setting on Salvator-XS). - * - If SW31 is the default setting, you cannot use USB2.0 ch3 on - * r8a77951 with Salvator-XS. - * Hence the SW31 setting must be changed like 2) below. - * 1) Default setting of SW31: ON-ON-OFF-OFF-OFF-OFF: - * - Connect GP6_3[01] to ADV7842. - * 2) Changed setting of SW31: OFF-OFF-ON-ON-ON-ON: - * - Connect GP6_3[01] to BD082065 (USB2.0 ch3's host power). - * - Connect GP6_{04,21} to ADV7842. - */ - usb2_ch3_pins: usb2_ch3 { - groups = "usb2_ch3"; - function = "usb2_ch3"; - }; -}; - -&rcar_sound { - ports { - /* rsnd_port0 is on salvator-common */ - rsnd_port1: port@1 { - reg = <1>; - rsnd_endpoint1: endpoint { - remote-endpoint = <&dw_hdmi0_snd_in>; - - dai-format = "i2s"; - bitclock-master = <&rsnd_endpoint1>; - frame-master = <&rsnd_endpoint1>; - - playback = <&ssi2>; - }; - }; - rsnd_port2: port@2 { - reg = <2>; - rsnd_endpoint2: endpoint { - remote-endpoint = <&dw_hdmi1_snd_in>; - - dai-format = "i2s"; - bitclock-master = <&rsnd_endpoint2>; - frame-master = <&rsnd_endpoint2>; - - playback = <&ssi3>; - }; - }; - }; -}; - -/* SW12-7 must be set 'Off' (MD12 set to 1) which is not the default! */ -&sata { - status = "okay"; -}; - -&sound_card { - dais = <&rsnd_port0 /* ak4613 */ - &rsnd_port1 /* HDMI0 */ - &rsnd_port2>; /* HDMI1 */ -}; - -&usb2_phy2 { - pinctrl-0 = <&usb2_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&usb2_phy3 { - pinctrl-0 = <&usb2_ch3_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/renesas/r8a77951-ulcb-kf.dts b/sys/gnu/dts/arm64/renesas/r8a77951-ulcb-kf.dts deleted file mode 100644 index 11f943a6770..00000000000 --- a/sys/gnu/dts/arm64/renesas/r8a77951-ulcb-kf.dts +++ /dev/null @@ -1,16 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the H3ULCB Kingfisher board - * - * Copyright (C) 2017 Renesas Electronics Corp. - * Copyright (C) 2017 Cogent Embedded, Inc. - */ - -#include "r8a77951-ulcb.dts" -#include "ulcb-kf.dtsi" - -/ { - model = "Renesas H3ULCB Kingfisher board based on r8a77951"; - compatible = "shimafuji,kingfisher", "renesas,h3ulcb", - "renesas,r8a7795"; -}; diff --git a/sys/gnu/dts/arm64/renesas/r8a77951-ulcb.dts b/sys/gnu/dts/arm64/renesas/r8a77951-ulcb.dts deleted file mode 100644 index 8ad8f2a5397..00000000000 --- a/sys/gnu/dts/arm64/renesas/r8a77951-ulcb.dts +++ /dev/null @@ -1,50 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the H3ULCB (R-Car Starter Kit Premier) board - * - * Copyright (C) 2016 Renesas Electronics Corp. - * Copyright (C) 2016 Cogent Embedded, Inc. - */ - -/dts-v1/; -#include "r8a77951.dtsi" -#include "ulcb.dtsi" - -/ { - model = "Renesas H3ULCB board based on r8a77951"; - compatible = "renesas,h3ulcb", "renesas,r8a7795"; - - memory@48000000 { - device_type = "memory"; - /* first 128MB is reserved for secure area. */ - reg = <0x0 0x48000000 0x0 0x38000000>; - }; - - memory@500000000 { - device_type = "memory"; - reg = <0x5 0x00000000 0x0 0x40000000>; - }; - - memory@600000000 { - device_type = "memory"; - reg = <0x6 0x00000000 0x0 0x40000000>; - }; - - memory@700000000 { - device_type = "memory"; - reg = <0x7 0x00000000 0x0 0x40000000>; - }; -}; - -&du { - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>, - <&cpg CPG_MOD 722>, - <&cpg CPG_MOD 721>, - <&versaclock5 1>, - <&versaclock5 3>, - <&versaclock5 4>, - <&versaclock5 2>; - clock-names = "du.0", "du.1", "du.2", "du.3", - "dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3"; -}; diff --git a/sys/gnu/dts/arm64/renesas/r8a77951.dtsi b/sys/gnu/dts/arm64/renesas/r8a77951.dtsi deleted file mode 100644 index a8729eb744d..00000000000 --- a/sys/gnu/dts/arm64/renesas/r8a77951.dtsi +++ /dev/null @@ -1,3339 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the R-Car H3 (R8A77951) SoC - * - * Copyright (C) 2015 Renesas Electronics Corp. - */ - -#include -#include -#include - -#define CPG_AUDIO_CLK_I R8A7795_CLK_S0D4 - -/ { - compatible = "renesas,r8a7795"; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - i2c6 = &i2c6; - i2c7 = &i2c_dvfs; - }; - - /* - * The external audio clocks are configured as 0 Hz fixed frequency - * clocks by default. - * Boards that provide audio clocks should override them. - */ - audio_clk_a: audio_clk_a { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - audio_clk_b: audio_clk_b { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - audio_clk_c: audio_clk_c { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - /* External CAN clock - to be overridden by boards that provide it */ - can_clk: can { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - cluster0_opp: opp_table0 { - compatible = "operating-points-v2"; - opp-shared; - - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <830000>; - clock-latency-ns = <300000>; - }; - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <830000>; - clock-latency-ns = <300000>; - }; - opp-1500000000 { - opp-hz = /bits/ 64 <1500000000>; - opp-microvolt = <830000>; - clock-latency-ns = <300000>; - opp-suspend; - }; - opp-1600000000 { - opp-hz = /bits/ 64 <1600000000>; - opp-microvolt = <900000>; - clock-latency-ns = <300000>; - turbo-mode; - }; - opp-1700000000 { - opp-hz = /bits/ 64 <1700000000>; - opp-microvolt = <960000>; - clock-latency-ns = <300000>; - turbo-mode; - }; - }; - - cluster1_opp: opp_table1 { - compatible = "operating-points-v2"; - opp-shared; - - opp-800000000 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <820000>; - clock-latency-ns = <300000>; - }; - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <820000>; - clock-latency-ns = <300000>; - }; - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <820000>; - clock-latency-ns = <300000>; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu-map { - cluster0 { - core0 { - cpu = <&a57_0>; - }; - core1 { - cpu = <&a57_1>; - }; - core2 { - cpu = <&a57_2>; - }; - core3 { - cpu = <&a57_3>; - }; - }; - - cluster1 { - core0 { - cpu = <&a53_0>; - }; - core1 { - cpu = <&a53_1>; - }; - core2 { - cpu = <&a53_2>; - }; - core3 { - cpu = <&a53_3>; - }; - }; - }; - - a57_0: cpu@0 { - compatible = "arm,cortex-a57"; - reg = <0x0>; - device_type = "cpu"; - power-domains = <&sysc R8A7795_PD_CA57_CPU0>; - next-level-cache = <&L2_CA57>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - dynamic-power-coefficient = <854>; - clocks = <&cpg CPG_CORE R8A7795_CLK_Z>; - operating-points-v2 = <&cluster0_opp>; - capacity-dmips-mhz = <1024>; - #cooling-cells = <2>; - }; - - a57_1: cpu@1 { - compatible = "arm,cortex-a57"; - reg = <0x1>; - device_type = "cpu"; - power-domains = <&sysc R8A7795_PD_CA57_CPU1>; - next-level-cache = <&L2_CA57>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - clocks = <&cpg CPG_CORE R8A7795_CLK_Z>; - operating-points-v2 = <&cluster0_opp>; - capacity-dmips-mhz = <1024>; - #cooling-cells = <2>; - }; - - a57_2: cpu@2 { - compatible = "arm,cortex-a57"; - reg = <0x2>; - device_type = "cpu"; - power-domains = <&sysc R8A7795_PD_CA57_CPU2>; - next-level-cache = <&L2_CA57>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - clocks = <&cpg CPG_CORE R8A7795_CLK_Z>; - operating-points-v2 = <&cluster0_opp>; - capacity-dmips-mhz = <1024>; - #cooling-cells = <2>; - }; - - a57_3: cpu@3 { - compatible = "arm,cortex-a57"; - reg = <0x3>; - device_type = "cpu"; - power-domains = <&sysc R8A7795_PD_CA57_CPU3>; - next-level-cache = <&L2_CA57>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - clocks = <&cpg CPG_CORE R8A7795_CLK_Z>; - operating-points-v2 = <&cluster0_opp>; - capacity-dmips-mhz = <1024>; - #cooling-cells = <2>; - }; - - a53_0: cpu@100 { - compatible = "arm,cortex-a53"; - reg = <0x100>; - device_type = "cpu"; - power-domains = <&sysc R8A7795_PD_CA53_CPU0>; - next-level-cache = <&L2_CA53>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_1>; - #cooling-cells = <2>; - dynamic-power-coefficient = <277>; - clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>; - operating-points-v2 = <&cluster1_opp>; - capacity-dmips-mhz = <535>; - }; - - a53_1: cpu@101 { - compatible = "arm,cortex-a53"; - reg = <0x101>; - device_type = "cpu"; - power-domains = <&sysc R8A7795_PD_CA53_CPU1>; - next-level-cache = <&L2_CA53>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_1>; - clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>; - operating-points-v2 = <&cluster1_opp>; - capacity-dmips-mhz = <535>; - }; - - a53_2: cpu@102 { - compatible = "arm,cortex-a53"; - reg = <0x102>; - device_type = "cpu"; - power-domains = <&sysc R8A7795_PD_CA53_CPU2>; - next-level-cache = <&L2_CA53>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_1>; - clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>; - operating-points-v2 = <&cluster1_opp>; - capacity-dmips-mhz = <535>; - }; - - a53_3: cpu@103 { - compatible = "arm,cortex-a53"; - reg = <0x103>; - device_type = "cpu"; - power-domains = <&sysc R8A7795_PD_CA53_CPU3>; - next-level-cache = <&L2_CA53>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_1>; - clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>; - operating-points-v2 = <&cluster1_opp>; - capacity-dmips-mhz = <535>; - }; - - L2_CA57: cache-controller-0 { - compatible = "cache"; - power-domains = <&sysc R8A7795_PD_CA57_SCU>; - cache-unified; - cache-level = <2>; - }; - - L2_CA53: cache-controller-1 { - compatible = "cache"; - power-domains = <&sysc R8A7795_PD_CA53_SCU>; - cache-unified; - cache-level = <2>; - }; - - idle-states { - entry-method = "psci"; - - CPU_SLEEP_0: cpu-sleep-0 { - compatible = "arm,idle-state"; - arm,psci-suspend-param = <0x0010000>; - local-timer-stop; - entry-latency-us = <400>; - exit-latency-us = <500>; - min-residency-us = <4000>; - }; - - CPU_SLEEP_1: cpu-sleep-1 { - compatible = "arm,idle-state"; - arm,psci-suspend-param = <0x0010000>; - local-timer-stop; - entry-latency-us = <700>; - exit-latency-us = <700>; - min-residency-us = <5000>; - }; - }; - }; - - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board */ - clock-frequency = <0>; - }; - - extalr_clk: extalr { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board */ - clock-frequency = <0>; - }; - - /* External PCIe clock - can be overridden by the board */ - pcie_bus_clk: pcie_bus { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - pmu_a53 { - compatible = "arm,cortex-a53-pmu"; - interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&a53_0>, - <&a53_1>, - <&a53_2>, - <&a53_3>; - }; - - pmu_a57 { - compatible = "arm,cortex-a57-pmu"; - interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&a57_0>, - <&a57_1>, - <&a57_2>, - <&a57_3>; - }; - - psci { - compatible = "arm,psci-1.0", "arm,psci-0.2"; - method = "smc"; - }; - - /* External SCIF clock - to be overridden by boards that provide it */ - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - soc: soc { - compatible = "simple-bus"; - interrupt-parent = <&gic>; - - #address-cells = <2>; - #size-cells = <2>; - ranges; - - rwdt: watchdog@e6020000 { - compatible = "renesas,r8a7795-wdt", "renesas,rcar-gen3-wdt"; - reg = <0 0xe6020000 0 0x0c>; - clocks = <&cpg CPG_MOD 402>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 402>; - status = "disabled"; - }; - - gpio0: gpio@e6050000 { - compatible = "renesas,gpio-r8a7795", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6050000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 0 16>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 912>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 912>; - }; - - gpio1: gpio@e6051000 { - compatible = "renesas,gpio-r8a7795", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6051000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 32 29>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 911>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 911>; - }; - - gpio2: gpio@e6052000 { - compatible = "renesas,gpio-r8a7795", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6052000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 64 15>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 910>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 910>; - }; - - gpio3: gpio@e6053000 { - compatible = "renesas,gpio-r8a7795", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6053000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 96 16>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 909>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 909>; - }; - - gpio4: gpio@e6054000 { - compatible = "renesas,gpio-r8a7795", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6054000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 128 18>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 908>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 908>; - }; - - gpio5: gpio@e6055000 { - compatible = "renesas,gpio-r8a7795", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6055000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 160 26>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 907>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 907>; - }; - - gpio6: gpio@e6055400 { - compatible = "renesas,gpio-r8a7795", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6055400 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 192 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 906>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 906>; - }; - - gpio7: gpio@e6055800 { - compatible = "renesas,gpio-r8a7795", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6055800 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 224 4>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 905>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 905>; - }; - - pfc: pin-controller@e6060000 { - compatible = "renesas,pfc-r8a7795"; - reg = <0 0xe6060000 0 0x50c>; - }; - - cmt0: timer@e60f0000 { - compatible = "renesas,r8a7795-cmt0", - "renesas,rcar-gen3-cmt0"; - reg = <0 0xe60f0000 0 0x1004>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 303>; - clock-names = "fck"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 303>; - status = "disabled"; - }; - - cmt1: timer@e6130000 { - compatible = "renesas,r8a7795-cmt1", - "renesas,rcar-gen3-cmt1"; - reg = <0 0xe6130000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 302>; - clock-names = "fck"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 302>; - status = "disabled"; - }; - - cmt2: timer@e6140000 { - compatible = "renesas,r8a7795-cmt1", - "renesas,rcar-gen3-cmt1"; - reg = <0 0xe6140000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 301>; - clock-names = "fck"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 301>; - status = "disabled"; - }; - - cmt3: timer@e6148000 { - compatible = "renesas,r8a7795-cmt1", - "renesas,rcar-gen3-cmt1"; - reg = <0 0xe6148000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 300>; - clock-names = "fck"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 300>; - status = "disabled"; - }; - - cpg: clock-controller@e6150000 { - compatible = "renesas,r8a7795-cpg-mssr"; - reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk>, <&extalr_clk>; - clock-names = "extal", "extalr"; - #clock-cells = <2>; - #power-domain-cells = <0>; - #reset-cells = <1>; - }; - - rst: reset-controller@e6160000 { - compatible = "renesas,r8a7795-rst"; - reg = <0 0xe6160000 0 0x0200>; - }; - - sysc: system-controller@e6180000 { - compatible = "renesas,r8a7795-sysc"; - reg = <0 0xe6180000 0 0x0400>; - #power-domain-cells = <1>; - }; - - tsc: thermal@e6198000 { - compatible = "renesas,r8a7795-thermal"; - reg = <0 0xe6198000 0 0x100>, - <0 0xe61a0000 0 0x100>, - <0 0xe61a8000 0 0x100>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 522>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 522>; - #thermal-sensor-cells = <1>; - }; - - intc_ex: interrupt-controller@e61c0000 { - compatible = "renesas,intc-ex-r8a7795", "renesas,irqc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0 0xe61c0000 0 0x200>; - interrupts = , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 407>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 407>; - }; - - i2c0: i2c@e6500000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7795", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6500000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 931>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 931>; - dmas = <&dmac1 0x91>, <&dmac1 0x90>, - <&dmac2 0x91>, <&dmac2 0x90>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c1: i2c@e6508000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7795", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6508000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 930>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 930>; - dmas = <&dmac1 0x93>, <&dmac1 0x92>, - <&dmac2 0x93>, <&dmac2 0x92>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c2: i2c@e6510000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7795", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6510000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 929>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 929>; - dmas = <&dmac1 0x95>, <&dmac1 0x94>, - <&dmac2 0x95>, <&dmac2 0x94>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c3: i2c@e66d0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7795", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66d0000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 928>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 928>; - dmas = <&dmac0 0x97>, <&dmac0 0x96>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c4: i2c@e66d8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7795", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66d8000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 927>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 927>; - dmas = <&dmac0 0x99>, <&dmac0 0x98>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c5: i2c@e66e0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7795", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66e0000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 919>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 919>; - dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c6: i2c@e66e8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7795", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66e8000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 918>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 918>; - dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c_dvfs: i2c@e60b0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7795", - "renesas,rcar-gen3-iic", - "renesas,rmobile-iic"; - reg = <0 0xe60b0000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 926>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 926>; - dmas = <&dmac0 0x11>, <&dmac0 0x10>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - hscif0: serial@e6540000 { - compatible = "renesas,hscif-r8a7795", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6540000 0 96>; - interrupts = ; - clocks = <&cpg CPG_MOD 520>, - <&cpg CPG_CORE R8A7795_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x31>, <&dmac1 0x30>, - <&dmac2 0x31>, <&dmac2 0x30>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 520>; - status = "disabled"; - }; - - hscif1: serial@e6550000 { - compatible = "renesas,hscif-r8a7795", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6550000 0 96>; - interrupts = ; - clocks = <&cpg CPG_MOD 519>, - <&cpg CPG_CORE R8A7795_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x33>, <&dmac1 0x32>, - <&dmac2 0x33>, <&dmac2 0x32>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 519>; - status = "disabled"; - }; - - hscif2: serial@e6560000 { - compatible = "renesas,hscif-r8a7795", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6560000 0 96>; - interrupts = ; - clocks = <&cpg CPG_MOD 518>, - <&cpg CPG_CORE R8A7795_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x35>, <&dmac1 0x34>, - <&dmac2 0x35>, <&dmac2 0x34>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 518>; - status = "disabled"; - }; - - hscif3: serial@e66a0000 { - compatible = "renesas,hscif-r8a7795", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe66a0000 0 96>; - interrupts = ; - clocks = <&cpg CPG_MOD 517>, - <&cpg CPG_CORE R8A7795_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x37>, <&dmac0 0x36>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 517>; - status = "disabled"; - }; - - hscif4: serial@e66b0000 { - compatible = "renesas,hscif-r8a7795", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe66b0000 0 96>; - interrupts = ; - clocks = <&cpg CPG_MOD 516>, - <&cpg CPG_CORE R8A7795_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x39>, <&dmac0 0x38>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 516>; - status = "disabled"; - }; - - hsusb: usb@e6590000 { - compatible = "renesas,usbhs-r8a7795", - "renesas,rcar-gen3-usbhs"; - reg = <0 0xe6590000 0 0x200>; - interrupts = ; - clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>; - dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, - <&usb_dmac1 0>, <&usb_dmac1 1>; - dma-names = "ch0", "ch1", "ch2", "ch3"; - renesas,buswait = <11>; - phys = <&usb2_phy0 3>; - phy-names = "usb"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 704>, <&cpg 703>; - status = "disabled"; - }; - - hsusb3: usb@e659c000 { - compatible = "renesas,usbhs-r8a7795", - "renesas,rcar-gen3-usbhs"; - reg = <0 0xe659c000 0 0x200>; - interrupts = ; - clocks = <&cpg CPG_MOD 705>, <&cpg CPG_MOD 700>; - dmas = <&usb_dmac2 0>, <&usb_dmac2 1>, - <&usb_dmac3 0>, <&usb_dmac3 1>; - dma-names = "ch0", "ch1", "ch2", "ch3"; - renesas,buswait = <11>; - phys = <&usb2_phy3 3>; - phy-names = "usb"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 705>, <&cpg 700>; - status = "disabled"; - }; - - usb_dmac0: dma-controller@e65a0000 { - compatible = "renesas,r8a7795-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65a0000 0 0x100>; - interrupts = , - ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 330>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 330>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - usb_dmac1: dma-controller@e65b0000 { - compatible = "renesas,r8a7795-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65b0000 0 0x100>; - interrupts = , - ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 331>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 331>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - usb_dmac2: dma-controller@e6460000 { - compatible = "renesas,r8a7795-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe6460000 0 0x100>; - interrupts = , - ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 326>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 326>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - usb_dmac3: dma-controller@e6470000 { - compatible = "renesas,r8a7795-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe6470000 0 0x100>; - interrupts = , - ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 329>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 329>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - usb3_phy0: usb-phy@e65ee000 { - compatible = "renesas,r8a7795-usb3-phy", - "renesas,rcar-gen3-usb3-phy"; - reg = <0 0xe65ee000 0 0x90>; - clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, - <&usb_extal_clk>; - clock-names = "usb3-if", "usb3s_clk", "usb_extal"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 328>; - #phy-cells = <0>; - status = "disabled"; - }; - - arm_cc630p: crypto@e6601000 { - compatible = "arm,cryptocell-630p-ree"; - interrupts = ; - reg = <0x0 0xe6601000 0 0x1000>; - clocks = <&cpg CPG_MOD 229>; - resets = <&cpg 229>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - }; - - dmac0: dma-controller@e6700000 { - compatible = "renesas,dmac-r8a7795", - "renesas,rcar-dmac"; - reg = <0 0xe6700000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 219>; - clock-names = "fck"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 219>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, - <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, - <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, - <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, - <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, - <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, - <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, - <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; - }; - - dmac1: dma-controller@e7300000 { - compatible = "renesas,dmac-r8a7795", - "renesas,rcar-dmac"; - reg = <0 0xe7300000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 218>; - clock-names = "fck"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 218>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, - <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, - <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, - <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, - <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, - <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, - <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, - <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; - }; - - dmac2: dma-controller@e7310000 { - compatible = "renesas,dmac-r8a7795", - "renesas,rcar-dmac"; - reg = <0 0xe7310000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 217>; - clock-names = "fck"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 217>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, - <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, - <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, - <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, - <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, - <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, - <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, - <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; - }; - - ipmmu_ds0: mmu@e6740000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xe6740000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 0>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_ds1: mmu@e7740000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xe7740000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 1>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_hc: mmu@e6570000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xe6570000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 2>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_ir: mmu@ff8b0000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xff8b0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 3>; - power-domains = <&sysc R8A7795_PD_A3IR>; - #iommu-cells = <1>; - }; - - ipmmu_mm: mmu@e67b0000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xe67b0000 0 0x1000>; - interrupts = , - ; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_mp0: mmu@ec670000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xec670000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 4>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_pv0: mmu@fd800000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xfd800000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 6>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_pv1: mmu@fd950000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xfd950000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 7>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_pv2: mmu@fd960000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xfd960000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 8>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_pv3: mmu@fd970000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xfd970000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 9>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_rt: mmu@ffc80000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xffc80000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 10>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_vc0: mmu@fe6b0000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xfe6b0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 12>; - power-domains = <&sysc R8A7795_PD_A3VC>; - #iommu-cells = <1>; - }; - - ipmmu_vc1: mmu@fe6f0000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xfe6f0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 13>; - power-domains = <&sysc R8A7795_PD_A3VC>; - #iommu-cells = <1>; - }; - - ipmmu_vi0: mmu@febd0000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xfebd0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 14>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_vi1: mmu@febe0000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xfebe0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 15>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_vp0: mmu@fe990000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xfe990000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 16>; - power-domains = <&sysc R8A7795_PD_A3VP>; - #iommu-cells = <1>; - }; - - ipmmu_vp1: mmu@fe980000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xfe980000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 17>; - power-domains = <&sysc R8A7795_PD_A3VP>; - #iommu-cells = <1>; - }; - - avb: ethernet@e6800000 { - compatible = "renesas,etheravb-r8a7795", - "renesas,etheravb-rcar-gen3"; - reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15", - "ch16", "ch17", "ch18", "ch19", - "ch20", "ch21", "ch22", "ch23", - "ch24"; - clocks = <&cpg CPG_MOD 812>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 812>; - phy-mode = "rgmii"; - iommus = <&ipmmu_ds0 16>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - can0: can@e6c30000 { - compatible = "renesas,can-r8a7795", - "renesas,rcar-gen3-can"; - reg = <0 0xe6c30000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 916>, - <&cpg CPG_CORE R8A7795_CLK_CANFD>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>; - assigned-clock-rates = <40000000>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 916>; - status = "disabled"; - }; - - can1: can@e6c38000 { - compatible = "renesas,can-r8a7795", - "renesas,rcar-gen3-can"; - reg = <0 0xe6c38000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 915>, - <&cpg CPG_CORE R8A7795_CLK_CANFD>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>; - assigned-clock-rates = <40000000>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 915>; - status = "disabled"; - }; - - canfd: can@e66c0000 { - compatible = "renesas,r8a7795-canfd", - "renesas,rcar-gen3-canfd"; - reg = <0 0xe66c0000 0 0x8000>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 914>, - <&cpg CPG_CORE R8A7795_CLK_CANFD>, - <&can_clk>; - clock-names = "fck", "canfd", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>; - assigned-clock-rates = <40000000>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 914>; - status = "disabled"; - - channel0 { - status = "disabled"; - }; - - channel1 { - status = "disabled"; - }; - }; - - pwm0: pwm@e6e30000 { - compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; - reg = <0 0xe6e30000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm1: pwm@e6e31000 { - compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; - reg = <0 0xe6e31000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm2: pwm@e6e32000 { - compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; - reg = <0 0xe6e32000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm3: pwm@e6e33000 { - compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; - reg = <0 0xe6e33000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm4: pwm@e6e34000 { - compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; - reg = <0 0xe6e34000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm5: pwm@e6e35000 { - compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; - reg = <0 0xe6e35000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm6: pwm@e6e36000 { - compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; - reg = <0 0xe6e36000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - scif0: serial@e6e60000 { - compatible = "renesas,scif-r8a7795", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e60000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 207>, - <&cpg CPG_CORE R8A7795_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x51>, <&dmac1 0x50>, - <&dmac2 0x51>, <&dmac2 0x50>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 207>; - status = "disabled"; - }; - - scif1: serial@e6e68000 { - compatible = "renesas,scif-r8a7795", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e68000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 206>, - <&cpg CPG_CORE R8A7795_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x53>, <&dmac1 0x52>, - <&dmac2 0x53>, <&dmac2 0x52>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 206>; - status = "disabled"; - }; - - scif2: serial@e6e88000 { - compatible = "renesas,scif-r8a7795", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e88000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 310>, - <&cpg CPG_CORE R8A7795_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x13>, <&dmac1 0x12>, - <&dmac2 0x13>, <&dmac2 0x12>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 310>; - status = "disabled"; - }; - - scif3: serial@e6c50000 { - compatible = "renesas,scif-r8a7795", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6c50000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 204>, - <&cpg CPG_CORE R8A7795_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x57>, <&dmac0 0x56>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 204>; - status = "disabled"; - }; - - scif4: serial@e6c40000 { - compatible = "renesas,scif-r8a7795", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6c40000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 203>, - <&cpg CPG_CORE R8A7795_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x59>, <&dmac0 0x58>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 203>; - status = "disabled"; - }; - - scif5: serial@e6f30000 { - compatible = "renesas,scif-r8a7795", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6f30000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 202>, - <&cpg CPG_CORE R8A7795_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, - <&dmac2 0x5b>, <&dmac2 0x5a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 202>; - status = "disabled"; - }; - - tpu: pwm@e6e80000 { - compatible = "renesas,tpu-r8a7795", "renesas,tpu"; - reg = <0 0xe6e80000 0 0x148>; - interrupts = ; - clocks = <&cpg CPG_MOD 304>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 304>; - #pwm-cells = <3>; - status = "disabled"; - }; - - msiof0: spi@e6e90000 { - compatible = "renesas,msiof-r8a7795", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6e90000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 211>; - dmas = <&dmac1 0x41>, <&dmac1 0x40>, - <&dmac2 0x41>, <&dmac2 0x40>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 211>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof1: spi@e6ea0000 { - compatible = "renesas,msiof-r8a7795", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6ea0000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 210>; - dmas = <&dmac1 0x43>, <&dmac1 0x42>, - <&dmac2 0x43>, <&dmac2 0x42>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 210>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof2: spi@e6c00000 { - compatible = "renesas,msiof-r8a7795", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6c00000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 209>; - dmas = <&dmac0 0x45>, <&dmac0 0x44>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 209>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof3: spi@e6c10000 { - compatible = "renesas,msiof-r8a7795", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6c10000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 208>; - dmas = <&dmac0 0x47>, <&dmac0 0x46>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 208>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - vin0: video@e6ef0000 { - compatible = "renesas,vin-r8a7795"; - reg = <0 0xe6ef0000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 811>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 811>; - renesas,id = <0>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin0csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin0>; - }; - vin0csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin0>; - }; - }; - }; - }; - - vin1: video@e6ef1000 { - compatible = "renesas,vin-r8a7795"; - reg = <0 0xe6ef1000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 810>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 810>; - renesas,id = <1>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin1csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin1>; - }; - vin1csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin1>; - }; - }; - }; - }; - - vin2: video@e6ef2000 { - compatible = "renesas,vin-r8a7795"; - reg = <0 0xe6ef2000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 809>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 809>; - renesas,id = <2>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin2csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin2>; - }; - vin2csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin2>; - }; - }; - }; - }; - - vin3: video@e6ef3000 { - compatible = "renesas,vin-r8a7795"; - reg = <0 0xe6ef3000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 808>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 808>; - renesas,id = <3>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin3csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin3>; - }; - vin3csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin3>; - }; - }; - }; - }; - - vin4: video@e6ef4000 { - compatible = "renesas,vin-r8a7795"; - reg = <0 0xe6ef4000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 807>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 807>; - renesas,id = <4>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin4csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin4>; - }; - vin4csi41: endpoint@3 { - reg = <3>; - remote-endpoint = <&csi41vin4>; - }; - }; - }; - }; - - vin5: video@e6ef5000 { - compatible = "renesas,vin-r8a7795"; - reg = <0 0xe6ef5000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 806>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 806>; - renesas,id = <5>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin5csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin5>; - }; - vin5csi41: endpoint@3 { - reg = <3>; - remote-endpoint = <&csi41vin5>; - }; - }; - }; - }; - - vin6: video@e6ef6000 { - compatible = "renesas,vin-r8a7795"; - reg = <0 0xe6ef6000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 805>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 805>; - renesas,id = <6>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin6csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin6>; - }; - vin6csi41: endpoint@3 { - reg = <3>; - remote-endpoint = <&csi41vin6>; - }; - }; - }; - }; - - vin7: video@e6ef7000 { - compatible = "renesas,vin-r8a7795"; - reg = <0 0xe6ef7000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 804>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 804>; - renesas,id = <7>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin7csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin7>; - }; - vin7csi41: endpoint@3 { - reg = <3>; - remote-endpoint = <&csi41vin7>; - }; - }; - }; - }; - - drif00: rif@e6f40000 { - compatible = "renesas,r8a7795-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6f40000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 515>; - clock-names = "fck"; - dmas = <&dmac1 0x20>, <&dmac2 0x20>; - dma-names = "rx", "rx"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 515>; - renesas,bonding = <&drif01>; - status = "disabled"; - }; - - drif01: rif@e6f50000 { - compatible = "renesas,r8a7795-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6f50000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 514>; - clock-names = "fck"; - dmas = <&dmac1 0x22>, <&dmac2 0x22>; - dma-names = "rx", "rx"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 514>; - renesas,bonding = <&drif00>; - status = "disabled"; - }; - - drif10: rif@e6f60000 { - compatible = "renesas,r8a7795-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6f60000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 513>; - clock-names = "fck"; - dmas = <&dmac1 0x24>, <&dmac2 0x24>; - dma-names = "rx", "rx"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 513>; - renesas,bonding = <&drif11>; - status = "disabled"; - }; - - drif11: rif@e6f70000 { - compatible = "renesas,r8a7795-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6f70000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 512>; - clock-names = "fck"; - dmas = <&dmac1 0x26>, <&dmac2 0x26>; - dma-names = "rx", "rx"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 512>; - renesas,bonding = <&drif10>; - status = "disabled"; - }; - - drif20: rif@e6f80000 { - compatible = "renesas,r8a7795-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6f80000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 511>; - clock-names = "fck"; - dmas = <&dmac1 0x28>, <&dmac2 0x28>; - dma-names = "rx", "rx"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 511>; - renesas,bonding = <&drif21>; - status = "disabled"; - }; - - drif21: rif@e6f90000 { - compatible = "renesas,r8a7795-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6f90000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 510>; - clock-names = "fck"; - dmas = <&dmac1 0x2a>, <&dmac2 0x2a>; - dma-names = "rx", "rx"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 510>; - renesas,bonding = <&drif20>; - status = "disabled"; - }; - - drif30: rif@e6fa0000 { - compatible = "renesas,r8a7795-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6fa0000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 509>; - clock-names = "fck"; - dmas = <&dmac1 0x2c>, <&dmac2 0x2c>; - dma-names = "rx", "rx"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 509>; - renesas,bonding = <&drif31>; - status = "disabled"; - }; - - drif31: rif@e6fb0000 { - compatible = "renesas,r8a7795-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6fb0000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 508>; - clock-names = "fck"; - dmas = <&dmac1 0x2e>, <&dmac2 0x2e>; - dma-names = "rx", "rx"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 508>; - renesas,bonding = <&drif30>; - status = "disabled"; - }; - - rcar_sound: sound@ec500000 { - /* - * #sound-dai-cells is required - * - * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; - * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; - */ - /* - * #clock-cells is required for audio_clkout0/1/2/3 - * - * clkout : #clock-cells = <0>; <&rcar_sound>; - * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; - */ - compatible = "renesas,rcar_sound-r8a7795", "renesas,rcar_sound-gen3"; - reg = <0 0xec500000 0 0x1000>, /* SCU */ - <0 0xec5a0000 0 0x100>, /* ADG */ - <0 0xec540000 0 0x1000>, /* SSIU */ - <0 0xec541000 0 0x280>, /* SSI */ - <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ - reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; - - clocks = <&cpg CPG_MOD 1005>, - <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, - <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, - <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, - <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, - <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, - <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, - <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, - <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, - <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, - <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, - <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, - <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, - <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, - <&audio_clk_a>, <&audio_clk_b>, - <&audio_clk_c>, - <&cpg CPG_CORE R8A7795_CLK_S0D4>; - clock-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", - "ssi.5", "ssi.4", "ssi.3", "ssi.2", - "ssi.1", "ssi.0", - "src.9", "src.8", "src.7", "src.6", - "src.5", "src.4", "src.3", "src.2", - "src.1", "src.0", - "mix.1", "mix.0", - "ctu.1", "ctu.0", - "dvc.0", "dvc.1", - "clk_a", "clk_b", "clk_c", "clk_i"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 1005>, - <&cpg 1006>, <&cpg 1007>, - <&cpg 1008>, <&cpg 1009>, - <&cpg 1010>, <&cpg 1011>, - <&cpg 1012>, <&cpg 1013>, - <&cpg 1014>, <&cpg 1015>; - reset-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", - "ssi.5", "ssi.4", "ssi.3", "ssi.2", - "ssi.1", "ssi.0"; - status = "disabled"; - - rcar_sound,dvc { - dvc0: dvc-0 { - dmas = <&audma1 0xbc>; - dma-names = "tx"; - }; - dvc1: dvc-1 { - dmas = <&audma1 0xbe>; - dma-names = "tx"; - }; - }; - - rcar_sound,mix { - mix0: mix-0 { }; - mix1: mix-1 { }; - }; - - rcar_sound,ctu { - ctu00: ctu-0 { }; - ctu01: ctu-1 { }; - ctu02: ctu-2 { }; - ctu03: ctu-3 { }; - ctu10: ctu-4 { }; - ctu11: ctu-5 { }; - ctu12: ctu-6 { }; - ctu13: ctu-7 { }; - }; - - rcar_sound,src { - src0: src-0 { - interrupts = ; - dmas = <&audma0 0x85>, <&audma1 0x9a>; - dma-names = "rx", "tx"; - }; - src1: src-1 { - interrupts = ; - dmas = <&audma0 0x87>, <&audma1 0x9c>; - dma-names = "rx", "tx"; - }; - src2: src-2 { - interrupts = ; - dmas = <&audma0 0x89>, <&audma1 0x9e>; - dma-names = "rx", "tx"; - }; - src3: src-3 { - interrupts = ; - dmas = <&audma0 0x8b>, <&audma1 0xa0>; - dma-names = "rx", "tx"; - }; - src4: src-4 { - interrupts = ; - dmas = <&audma0 0x8d>, <&audma1 0xb0>; - dma-names = "rx", "tx"; - }; - src5: src-5 { - interrupts = ; - dmas = <&audma0 0x8f>, <&audma1 0xb2>; - dma-names = "rx", "tx"; - }; - src6: src-6 { - interrupts = ; - dmas = <&audma0 0x91>, <&audma1 0xb4>; - dma-names = "rx", "tx"; - }; - src7: src-7 { - interrupts = ; - dmas = <&audma0 0x93>, <&audma1 0xb6>; - dma-names = "rx", "tx"; - }; - src8: src-8 { - interrupts = ; - dmas = <&audma0 0x95>, <&audma1 0xb8>; - dma-names = "rx", "tx"; - }; - src9: src-9 { - interrupts = ; - dmas = <&audma0 0x97>, <&audma1 0xba>; - dma-names = "rx", "tx"; - }; - }; - - rcar_sound,ssiu { - ssiu00: ssiu-0 { - dmas = <&audma0 0x15>, <&audma1 0x16>; - dma-names = "rx", "tx"; - }; - ssiu01: ssiu-1 { - dmas = <&audma0 0x35>, <&audma1 0x36>; - dma-names = "rx", "tx"; - }; - ssiu02: ssiu-2 { - dmas = <&audma0 0x37>, <&audma1 0x38>; - dma-names = "rx", "tx"; - }; - ssiu03: ssiu-3 { - dmas = <&audma0 0x47>, <&audma1 0x48>; - dma-names = "rx", "tx"; - }; - ssiu04: ssiu-4 { - dmas = <&audma0 0x3F>, <&audma1 0x40>; - dma-names = "rx", "tx"; - }; - ssiu05: ssiu-5 { - dmas = <&audma0 0x43>, <&audma1 0x44>; - dma-names = "rx", "tx"; - }; - ssiu06: ssiu-6 { - dmas = <&audma0 0x4F>, <&audma1 0x50>; - dma-names = "rx", "tx"; - }; - ssiu07: ssiu-7 { - dmas = <&audma0 0x53>, <&audma1 0x54>; - dma-names = "rx", "tx"; - }; - ssiu10: ssiu-8 { - dmas = <&audma0 0x49>, <&audma1 0x4a>; - dma-names = "rx", "tx"; - }; - ssiu11: ssiu-9 { - dmas = <&audma0 0x4B>, <&audma1 0x4C>; - dma-names = "rx", "tx"; - }; - ssiu12: ssiu-10 { - dmas = <&audma0 0x57>, <&audma1 0x58>; - dma-names = "rx", "tx"; - }; - ssiu13: ssiu-11 { - dmas = <&audma0 0x59>, <&audma1 0x5A>; - dma-names = "rx", "tx"; - }; - ssiu14: ssiu-12 { - dmas = <&audma0 0x5F>, <&audma1 0x60>; - dma-names = "rx", "tx"; - }; - ssiu15: ssiu-13 { - dmas = <&audma0 0xC3>, <&audma1 0xC4>; - dma-names = "rx", "tx"; - }; - ssiu16: ssiu-14 { - dmas = <&audma0 0xC7>, <&audma1 0xC8>; - dma-names = "rx", "tx"; - }; - ssiu17: ssiu-15 { - dmas = <&audma0 0xCB>, <&audma1 0xCC>; - dma-names = "rx", "tx"; - }; - ssiu20: ssiu-16 { - dmas = <&audma0 0x63>, <&audma1 0x64>; - dma-names = "rx", "tx"; - }; - ssiu21: ssiu-17 { - dmas = <&audma0 0x67>, <&audma1 0x68>; - dma-names = "rx", "tx"; - }; - ssiu22: ssiu-18 { - dmas = <&audma0 0x6B>, <&audma1 0x6C>; - dma-names = "rx", "tx"; - }; - ssiu23: ssiu-19 { - dmas = <&audma0 0x6D>, <&audma1 0x6E>; - dma-names = "rx", "tx"; - }; - ssiu24: ssiu-20 { - dmas = <&audma0 0xCF>, <&audma1 0xCE>; - dma-names = "rx", "tx"; - }; - ssiu25: ssiu-21 { - dmas = <&audma0 0xEB>, <&audma1 0xEC>; - dma-names = "rx", "tx"; - }; - ssiu26: ssiu-22 { - dmas = <&audma0 0xED>, <&audma1 0xEE>; - dma-names = "rx", "tx"; - }; - ssiu27: ssiu-23 { - dmas = <&audma0 0xEF>, <&audma1 0xF0>; - dma-names = "rx", "tx"; - }; - ssiu30: ssiu-24 { - dmas = <&audma0 0x6f>, <&audma1 0x70>; - dma-names = "rx", "tx"; - }; - ssiu31: ssiu-25 { - dmas = <&audma0 0x21>, <&audma1 0x22>; - dma-names = "rx", "tx"; - }; - ssiu32: ssiu-26 { - dmas = <&audma0 0x23>, <&audma1 0x24>; - dma-names = "rx", "tx"; - }; - ssiu33: ssiu-27 { - dmas = <&audma0 0x25>, <&audma1 0x26>; - dma-names = "rx", "tx"; - }; - ssiu34: ssiu-28 { - dmas = <&audma0 0x27>, <&audma1 0x28>; - dma-names = "rx", "tx"; - }; - ssiu35: ssiu-29 { - dmas = <&audma0 0x29>, <&audma1 0x2A>; - dma-names = "rx", "tx"; - }; - ssiu36: ssiu-30 { - dmas = <&audma0 0x2B>, <&audma1 0x2C>; - dma-names = "rx", "tx"; - }; - ssiu37: ssiu-31 { - dmas = <&audma0 0x2D>, <&audma1 0x2E>; - dma-names = "rx", "tx"; - }; - ssiu40: ssiu-32 { - dmas = <&audma0 0x71>, <&audma1 0x72>; - dma-names = "rx", "tx"; - }; - ssiu41: ssiu-33 { - dmas = <&audma0 0x17>, <&audma1 0x18>; - dma-names = "rx", "tx"; - }; - ssiu42: ssiu-34 { - dmas = <&audma0 0x19>, <&audma1 0x1A>; - dma-names = "rx", "tx"; - }; - ssiu43: ssiu-35 { - dmas = <&audma0 0x1B>, <&audma1 0x1C>; - dma-names = "rx", "tx"; - }; - ssiu44: ssiu-36 { - dmas = <&audma0 0x1D>, <&audma1 0x1E>; - dma-names = "rx", "tx"; - }; - ssiu45: ssiu-37 { - dmas = <&audma0 0x1F>, <&audma1 0x20>; - dma-names = "rx", "tx"; - }; - ssiu46: ssiu-38 { - dmas = <&audma0 0x31>, <&audma1 0x32>; - dma-names = "rx", "tx"; - }; - ssiu47: ssiu-39 { - dmas = <&audma0 0x33>, <&audma1 0x34>; - dma-names = "rx", "tx"; - }; - ssiu50: ssiu-40 { - dmas = <&audma0 0x73>, <&audma1 0x74>; - dma-names = "rx", "tx"; - }; - ssiu60: ssiu-41 { - dmas = <&audma0 0x75>, <&audma1 0x76>; - dma-names = "rx", "tx"; - }; - ssiu70: ssiu-42 { - dmas = <&audma0 0x79>, <&audma1 0x7a>; - dma-names = "rx", "tx"; - }; - ssiu80: ssiu-43 { - dmas = <&audma0 0x7b>, <&audma1 0x7c>; - dma-names = "rx", "tx"; - }; - ssiu90: ssiu-44 { - dmas = <&audma0 0x7d>, <&audma1 0x7e>; - dma-names = "rx", "tx"; - }; - ssiu91: ssiu-45 { - dmas = <&audma0 0x7F>, <&audma1 0x80>; - dma-names = "rx", "tx"; - }; - ssiu92: ssiu-46 { - dmas = <&audma0 0x81>, <&audma1 0x82>; - dma-names = "rx", "tx"; - }; - ssiu93: ssiu-47 { - dmas = <&audma0 0x83>, <&audma1 0x84>; - dma-names = "rx", "tx"; - }; - ssiu94: ssiu-48 { - dmas = <&audma0 0xA3>, <&audma1 0xA4>; - dma-names = "rx", "tx"; - }; - ssiu95: ssiu-49 { - dmas = <&audma0 0xA5>, <&audma1 0xA6>; - dma-names = "rx", "tx"; - }; - ssiu96: ssiu-50 { - dmas = <&audma0 0xA7>, <&audma1 0xA8>; - dma-names = "rx", "tx"; - }; - ssiu97: ssiu-51 { - dmas = <&audma0 0xA9>, <&audma1 0xAA>; - dma-names = "rx", "tx"; - }; - }; - - rcar_sound,ssi { - ssi0: ssi-0 { - interrupts = ; - dmas = <&audma0 0x01>, <&audma1 0x02>; - dma-names = "rx", "tx"; - }; - ssi1: ssi-1 { - interrupts = ; - dmas = <&audma0 0x03>, <&audma1 0x04>; - dma-names = "rx", "tx"; - }; - ssi2: ssi-2 { - interrupts = ; - dmas = <&audma0 0x05>, <&audma1 0x06>; - dma-names = "rx", "tx"; - }; - ssi3: ssi-3 { - interrupts = ; - dmas = <&audma0 0x07>, <&audma1 0x08>; - dma-names = "rx", "tx"; - }; - ssi4: ssi-4 { - interrupts = ; - dmas = <&audma0 0x09>, <&audma1 0x0a>; - dma-names = "rx", "tx"; - }; - ssi5: ssi-5 { - interrupts = ; - dmas = <&audma0 0x0b>, <&audma1 0x0c>; - dma-names = "rx", "tx"; - }; - ssi6: ssi-6 { - interrupts = ; - dmas = <&audma0 0x0d>, <&audma1 0x0e>; - dma-names = "rx", "tx"; - }; - ssi7: ssi-7 { - interrupts = ; - dmas = <&audma0 0x0f>, <&audma1 0x10>; - dma-names = "rx", "tx"; - }; - ssi8: ssi-8 { - interrupts = ; - dmas = <&audma0 0x11>, <&audma1 0x12>; - dma-names = "rx", "tx"; - }; - ssi9: ssi-9 { - interrupts = ; - dmas = <&audma0 0x13>, <&audma1 0x14>; - dma-names = "rx", "tx"; - }; - }; - }; - - audma0: dma-controller@ec700000 { - compatible = "renesas,dmac-r8a7795", - "renesas,rcar-dmac"; - reg = <0 0xec700000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 502>; - clock-names = "fck"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 502>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_mp0 0>, <&ipmmu_mp0 1>, - <&ipmmu_mp0 2>, <&ipmmu_mp0 3>, - <&ipmmu_mp0 4>, <&ipmmu_mp0 5>, - <&ipmmu_mp0 6>, <&ipmmu_mp0 7>, - <&ipmmu_mp0 8>, <&ipmmu_mp0 9>, - <&ipmmu_mp0 10>, <&ipmmu_mp0 11>, - <&ipmmu_mp0 12>, <&ipmmu_mp0 13>, - <&ipmmu_mp0 14>, <&ipmmu_mp0 15>; - }; - - audma1: dma-controller@ec720000 { - compatible = "renesas,dmac-r8a7795", - "renesas,rcar-dmac"; - reg = <0 0xec720000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 501>; - clock-names = "fck"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 501>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_mp0 16>, <&ipmmu_mp0 17>, - <&ipmmu_mp0 18>, <&ipmmu_mp0 19>, - <&ipmmu_mp0 20>, <&ipmmu_mp0 21>, - <&ipmmu_mp0 22>, <&ipmmu_mp0 23>, - <&ipmmu_mp0 24>, <&ipmmu_mp0 25>, - <&ipmmu_mp0 26>, <&ipmmu_mp0 27>, - <&ipmmu_mp0 28>, <&ipmmu_mp0 29>, - <&ipmmu_mp0 30>, <&ipmmu_mp0 31>; - }; - - xhci0: usb@ee000000 { - compatible = "renesas,xhci-r8a7795", "renesas,rcar-gen3-xhci"; - reg = <0 0xee000000 0 0xc00>; - interrupts = ; - clocks = <&cpg CPG_MOD 328>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 328>; - status = "disabled"; - }; - - usb3_peri0: usb@ee020000 { - compatible = "renesas,r8a7795-usb3-peri", - "renesas,rcar-gen3-usb3-peri"; - reg = <0 0xee020000 0 0x400>; - interrupts = ; - clocks = <&cpg CPG_MOD 328>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 328>; - status = "disabled"; - }; - - ohci0: usb@ee080000 { - compatible = "generic-ohci"; - reg = <0 0xee080000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; - phys = <&usb2_phy0 1>; - phy-names = "usb"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 703>, <&cpg 704>; - status = "disabled"; - }; - - ohci1: usb@ee0a0000 { - compatible = "generic-ohci"; - reg = <0 0xee0a0000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 702>; - phys = <&usb2_phy1 1>; - phy-names = "usb"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 702>; - status = "disabled"; - }; - - ohci2: usb@ee0c0000 { - compatible = "generic-ohci"; - reg = <0 0xee0c0000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 701>; - phys = <&usb2_phy2 1>; - phy-names = "usb"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 701>; - status = "disabled"; - }; - - ohci3: usb@ee0e0000 { - compatible = "generic-ohci"; - reg = <0 0xee0e0000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 700>, <&cpg CPG_MOD 705>; - phys = <&usb2_phy3 1>; - phy-names = "usb"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 700>, <&cpg 705>; - status = "disabled"; - }; - - ehci0: usb@ee080100 { - compatible = "generic-ehci"; - reg = <0 0xee080100 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; - phys = <&usb2_phy0 2>; - phy-names = "usb"; - companion = <&ohci0>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 703>, <&cpg 704>; - status = "disabled"; - }; - - ehci1: usb@ee0a0100 { - compatible = "generic-ehci"; - reg = <0 0xee0a0100 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 702>; - phys = <&usb2_phy1 2>; - phy-names = "usb"; - companion = <&ohci1>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 702>; - status = "disabled"; - }; - - ehci2: usb@ee0c0100 { - compatible = "generic-ehci"; - reg = <0 0xee0c0100 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 701>; - phys = <&usb2_phy2 2>; - phy-names = "usb"; - companion = <&ohci2>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 701>; - status = "disabled"; - }; - - ehci3: usb@ee0e0100 { - compatible = "generic-ehci"; - reg = <0 0xee0e0100 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 700>, <&cpg CPG_MOD 705>; - phys = <&usb2_phy3 2>; - phy-names = "usb"; - companion = <&ohci3>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 700>, <&cpg 705>; - status = "disabled"; - }; - - usb2_phy0: usb-phy@ee080200 { - compatible = "renesas,usb2-phy-r8a7795", - "renesas,rcar-gen3-usb2-phy"; - reg = <0 0xee080200 0 0x700>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 703>, <&cpg 704>; - #phy-cells = <1>; - status = "disabled"; - }; - - usb2_phy1: usb-phy@ee0a0200 { - compatible = "renesas,usb2-phy-r8a7795", - "renesas,rcar-gen3-usb2-phy"; - reg = <0 0xee0a0200 0 0x700>; - clocks = <&cpg CPG_MOD 702>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 702>; - #phy-cells = <1>; - status = "disabled"; - }; - - usb2_phy2: usb-phy@ee0c0200 { - compatible = "renesas,usb2-phy-r8a7795", - "renesas,rcar-gen3-usb2-phy"; - reg = <0 0xee0c0200 0 0x700>; - clocks = <&cpg CPG_MOD 701>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 701>; - #phy-cells = <1>; - status = "disabled"; - }; - - usb2_phy3: usb-phy@ee0e0200 { - compatible = "renesas,usb2-phy-r8a7795", - "renesas,rcar-gen3-usb2-phy"; - reg = <0 0xee0e0200 0 0x700>; - interrupts = ; - clocks = <&cpg CPG_MOD 700>, <&cpg CPG_MOD 705>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 700>, <&cpg 705>; - #phy-cells = <1>; - status = "disabled"; - }; - - sdhi0: sd@ee100000 { - compatible = "renesas,sdhi-r8a7795", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee100000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 314>; - max-frequency = <200000000>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 314>; - iommus = <&ipmmu_ds1 32>; - status = "disabled"; - }; - - sdhi1: sd@ee120000 { - compatible = "renesas,sdhi-r8a7795", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee120000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 313>; - max-frequency = <200000000>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 313>; - iommus = <&ipmmu_ds1 33>; - status = "disabled"; - }; - - sdhi2: sd@ee140000 { - compatible = "renesas,sdhi-r8a7795", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee140000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 312>; - max-frequency = <200000000>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 312>; - iommus = <&ipmmu_ds1 34>; - status = "disabled"; - }; - - sdhi3: sd@ee160000 { - compatible = "renesas,sdhi-r8a7795", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee160000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 311>; - max-frequency = <200000000>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 311>; - iommus = <&ipmmu_ds1 35>; - status = "disabled"; - }; - - sata: sata@ee300000 { - compatible = "renesas,sata-r8a7795", - "renesas,rcar-gen3-sata"; - reg = <0 0xee300000 0 0x200000>; - interrupts = ; - clocks = <&cpg CPG_MOD 815>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 815>; - status = "disabled"; - iommus = <&ipmmu_hc 2>; - }; - - gic: interrupt-controller@f1010000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x0 0xf1010000 0 0x1000>, - <0x0 0xf1020000 0 0x20000>, - <0x0 0xf1040000 0 0x20000>, - <0x0 0xf1060000 0 0x20000>; - interrupts = ; - clocks = <&cpg CPG_MOD 408>; - clock-names = "clk"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 408>; - }; - - pciec0: pcie@fe000000 { - compatible = "renesas,pcie-r8a7795", - "renesas,pcie-rcar-gen3"; - reg = <0 0xfe000000 0 0x80000>; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x00 0xff>; - device_type = "pci"; - ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, - <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, - <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, - <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>; - interrupts = , - , - ; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; - clock-names = "pcie", "pcie_bus"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 319>; - status = "disabled"; - }; - - pciec1: pcie@ee800000 { - compatible = "renesas,pcie-r8a7795", - "renesas,pcie-rcar-gen3"; - reg = <0 0xee800000 0 0x80000>; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x00 0xff>; - device_type = "pci"; - ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>, - <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>, - <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>, - <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>; - interrupts = , - , - ; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>; - clock-names = "pcie", "pcie_bus"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 318>; - status = "disabled"; - }; - - imr-lx4@fe860000 { - compatible = "renesas,r8a7795-imr-lx4", - "renesas,imr-lx4"; - reg = <0 0xfe860000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 823>; - power-domains = <&sysc R8A7795_PD_A3VC>; - resets = <&cpg 823>; - }; - - imr-lx4@fe870000 { - compatible = "renesas,r8a7795-imr-lx4", - "renesas,imr-lx4"; - reg = <0 0xfe870000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 822>; - power-domains = <&sysc R8A7795_PD_A3VC>; - resets = <&cpg 822>; - }; - - imr-lx4@fe880000 { - compatible = "renesas,r8a7795-imr-lx4", - "renesas,imr-lx4"; - reg = <0 0xfe880000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 821>; - power-domains = <&sysc R8A7795_PD_A3VC>; - resets = <&cpg 821>; - }; - - imr-lx4@fe890000 { - compatible = "renesas,r8a7795-imr-lx4", - "renesas,imr-lx4"; - reg = <0 0xfe890000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 820>; - power-domains = <&sysc R8A7795_PD_A3VC>; - resets = <&cpg 820>; - }; - - vspbc: vsp@fe920000 { - compatible = "renesas,vsp2"; - reg = <0 0xfe920000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 624>; - power-domains = <&sysc R8A7795_PD_A3VP>; - resets = <&cpg 624>; - - renesas,fcp = <&fcpvb1>; - }; - - vspbd: vsp@fe960000 { - compatible = "renesas,vsp2"; - reg = <0 0xfe960000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 626>; - power-domains = <&sysc R8A7795_PD_A3VP>; - resets = <&cpg 626>; - - renesas,fcp = <&fcpvb0>; - }; - - vspd0: vsp@fea20000 { - compatible = "renesas,vsp2"; - reg = <0 0xfea20000 0 0x5000>; - interrupts = ; - clocks = <&cpg CPG_MOD 623>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 623>; - - renesas,fcp = <&fcpvd0>; - }; - - vspd1: vsp@fea28000 { - compatible = "renesas,vsp2"; - reg = <0 0xfea28000 0 0x5000>; - interrupts = ; - clocks = <&cpg CPG_MOD 622>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 622>; - - renesas,fcp = <&fcpvd1>; - }; - - vspd2: vsp@fea30000 { - compatible = "renesas,vsp2"; - reg = <0 0xfea30000 0 0x5000>; - interrupts = ; - clocks = <&cpg CPG_MOD 621>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 621>; - - renesas,fcp = <&fcpvd2>; - }; - - vspi0: vsp@fe9a0000 { - compatible = "renesas,vsp2"; - reg = <0 0xfe9a0000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 631>; - power-domains = <&sysc R8A7795_PD_A3VP>; - resets = <&cpg 631>; - - renesas,fcp = <&fcpvi0>; - }; - - vspi1: vsp@fe9b0000 { - compatible = "renesas,vsp2"; - reg = <0 0xfe9b0000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 630>; - power-domains = <&sysc R8A7795_PD_A3VP>; - resets = <&cpg 630>; - - renesas,fcp = <&fcpvi1>; - }; - - fdp1@fe940000 { - compatible = "renesas,fdp1"; - reg = <0 0xfe940000 0 0x2400>; - interrupts = ; - clocks = <&cpg CPG_MOD 119>; - power-domains = <&sysc R8A7795_PD_A3VP>; - resets = <&cpg 119>; - renesas,fcp = <&fcpf0>; - }; - - fdp1@fe944000 { - compatible = "renesas,fdp1"; - reg = <0 0xfe944000 0 0x2400>; - interrupts = ; - clocks = <&cpg CPG_MOD 118>; - power-domains = <&sysc R8A7795_PD_A3VP>; - resets = <&cpg 118>; - renesas,fcp = <&fcpf1>; - }; - - fcpf0: fcp@fe950000 { - compatible = "renesas,fcpf"; - reg = <0 0xfe950000 0 0x200>; - clocks = <&cpg CPG_MOD 615>; - power-domains = <&sysc R8A7795_PD_A3VP>; - resets = <&cpg 615>; - iommus = <&ipmmu_vp0 0>; - }; - - fcpf1: fcp@fe951000 { - compatible = "renesas,fcpf"; - reg = <0 0xfe951000 0 0x200>; - clocks = <&cpg CPG_MOD 614>; - power-domains = <&sysc R8A7795_PD_A3VP>; - resets = <&cpg 614>; - iommus = <&ipmmu_vp1 1>; - }; - - fcpvb0: fcp@fe96f000 { - compatible = "renesas,fcpv"; - reg = <0 0xfe96f000 0 0x200>; - clocks = <&cpg CPG_MOD 607>; - power-domains = <&sysc R8A7795_PD_A3VP>; - resets = <&cpg 607>; - iommus = <&ipmmu_vp0 5>; - }; - - fcpvb1: fcp@fe92f000 { - compatible = "renesas,fcpv"; - reg = <0 0xfe92f000 0 0x200>; - clocks = <&cpg CPG_MOD 606>; - power-domains = <&sysc R8A7795_PD_A3VP>; - resets = <&cpg 606>; - iommus = <&ipmmu_vp1 7>; - }; - - fcpvi0: fcp@fe9af000 { - compatible = "renesas,fcpv"; - reg = <0 0xfe9af000 0 0x200>; - clocks = <&cpg CPG_MOD 611>; - power-domains = <&sysc R8A7795_PD_A3VP>; - resets = <&cpg 611>; - iommus = <&ipmmu_vp0 8>; - }; - - fcpvi1: fcp@fe9bf000 { - compatible = "renesas,fcpv"; - reg = <0 0xfe9bf000 0 0x200>; - clocks = <&cpg CPG_MOD 610>; - power-domains = <&sysc R8A7795_PD_A3VP>; - resets = <&cpg 610>; - iommus = <&ipmmu_vp1 9>; - }; - - fcpvd0: fcp@fea27000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea27000 0 0x200>; - clocks = <&cpg CPG_MOD 603>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 603>; - iommus = <&ipmmu_vi0 8>; - }; - - fcpvd1: fcp@fea2f000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea2f000 0 0x200>; - clocks = <&cpg CPG_MOD 602>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 602>; - iommus = <&ipmmu_vi0 9>; - }; - - fcpvd2: fcp@fea37000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea37000 0 0x200>; - clocks = <&cpg CPG_MOD 601>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 601>; - iommus = <&ipmmu_vi1 10>; - }; - - cmm0: cmm@fea40000 { - compatible = "renesas,r8a7795-cmm", - "renesas,rcar-gen3-cmm"; - reg = <0 0xfea40000 0 0x1000>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - clocks = <&cpg CPG_MOD 711>; - resets = <&cpg 711>; - }; - - cmm1: cmm@fea50000 { - compatible = "renesas,r8a7795-cmm", - "renesas,rcar-gen3-cmm"; - reg = <0 0xfea50000 0 0x1000>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - clocks = <&cpg CPG_MOD 710>; - resets = <&cpg 710>; - }; - - cmm2: cmm@fea60000 { - compatible = "renesas,r8a7795-cmm", - "renesas,rcar-gen3-cmm"; - reg = <0 0xfea60000 0 0x1000>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - clocks = <&cpg CPG_MOD 709>; - resets = <&cpg 709>; - }; - - cmm3: cmm@fea70000 { - compatible = "renesas,r8a7795-cmm", - "renesas,rcar-gen3-cmm"; - reg = <0 0xfea70000 0 0x1000>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - clocks = <&cpg CPG_MOD 708>; - resets = <&cpg 708>; - }; - - csi20: csi2@fea80000 { - compatible = "renesas,r8a7795-csi2"; - reg = <0 0xfea80000 0 0x10000>; - interrupts = ; - clocks = <&cpg CPG_MOD 714>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 714>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - csi20vin0: endpoint@0 { - reg = <0>; - remote-endpoint = <&vin0csi20>; - }; - csi20vin1: endpoint@1 { - reg = <1>; - remote-endpoint = <&vin1csi20>; - }; - csi20vin2: endpoint@2 { - reg = <2>; - remote-endpoint = <&vin2csi20>; - }; - csi20vin3: endpoint@3 { - reg = <3>; - remote-endpoint = <&vin3csi20>; - }; - csi20vin4: endpoint@4 { - reg = <4>; - remote-endpoint = <&vin4csi20>; - }; - csi20vin5: endpoint@5 { - reg = <5>; - remote-endpoint = <&vin5csi20>; - }; - csi20vin6: endpoint@6 { - reg = <6>; - remote-endpoint = <&vin6csi20>; - }; - csi20vin7: endpoint@7 { - reg = <7>; - remote-endpoint = <&vin7csi20>; - }; - }; - }; - }; - - csi40: csi2@feaa0000 { - compatible = "renesas,r8a7795-csi2"; - reg = <0 0xfeaa0000 0 0x10000>; - interrupts = ; - clocks = <&cpg CPG_MOD 716>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 716>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - csi40vin0: endpoint@0 { - reg = <0>; - remote-endpoint = <&vin0csi40>; - }; - csi40vin1: endpoint@1 { - reg = <1>; - remote-endpoint = <&vin1csi40>; - }; - csi40vin2: endpoint@2 { - reg = <2>; - remote-endpoint = <&vin2csi40>; - }; - csi40vin3: endpoint@3 { - reg = <3>; - remote-endpoint = <&vin3csi40>; - }; - }; - }; - }; - - csi41: csi2@feab0000 { - compatible = "renesas,r8a7795-csi2"; - reg = <0 0xfeab0000 0 0x10000>; - interrupts = ; - clocks = <&cpg CPG_MOD 715>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 715>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - csi41vin4: endpoint@0 { - reg = <0>; - remote-endpoint = <&vin4csi41>; - }; - csi41vin5: endpoint@1 { - reg = <1>; - remote-endpoint = <&vin5csi41>; - }; - csi41vin6: endpoint@2 { - reg = <2>; - remote-endpoint = <&vin6csi41>; - }; - csi41vin7: endpoint@3 { - reg = <3>; - remote-endpoint = <&vin7csi41>; - }; - }; - }; - }; - - hdmi0: hdmi@fead0000 { - compatible = "renesas,r8a7795-hdmi", "renesas,rcar-gen3-hdmi"; - reg = <0 0xfead0000 0 0x10000>; - interrupts = ; - clocks = <&cpg CPG_MOD 729>, <&cpg CPG_CORE R8A7795_CLK_HDMI>; - clock-names = "iahb", "isfr"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 729>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - dw_hdmi0_in: endpoint { - remote-endpoint = <&du_out_hdmi0>; - }; - }; - port@1 { - reg = <1>; - }; - port@2 { - /* HDMI sound */ - reg = <2>; - }; - }; - }; - - hdmi1: hdmi@feae0000 { - compatible = "renesas,r8a7795-hdmi", "renesas,rcar-gen3-hdmi"; - reg = <0 0xfeae0000 0 0x10000>; - interrupts = ; - clocks = <&cpg CPG_MOD 728>, <&cpg CPG_CORE R8A7795_CLK_HDMI>; - clock-names = "iahb", "isfr"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 728>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - dw_hdmi1_in: endpoint { - remote-endpoint = <&du_out_hdmi1>; - }; - }; - port@1 { - reg = <1>; - }; - port@2 { - /* HDMI sound */ - reg = <2>; - }; - }; - }; - - du: display@feb00000 { - compatible = "renesas,du-r8a7795"; - reg = <0 0xfeb00000 0 0x80000>; - interrupts = , - , - , - ; - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>, - <&cpg CPG_MOD 722>, - <&cpg CPG_MOD 721>; - clock-names = "du.0", "du.1", "du.2", "du.3"; - - renesas,cmms = <&cmm0>, <&cmm1>, <&cmm2>, <&cmm3>; - vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>, <&vspd0 1>; - - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - du_out_rgb: endpoint { - }; - }; - port@1 { - reg = <1>; - du_out_hdmi0: endpoint { - remote-endpoint = <&dw_hdmi0_in>; - }; - }; - port@2 { - reg = <2>; - du_out_hdmi1: endpoint { - remote-endpoint = <&dw_hdmi1_in>; - }; - }; - port@3 { - reg = <3>; - du_out_lvds0: endpoint { - remote-endpoint = <&lvds0_in>; - }; - }; - }; - }; - - lvds0: lvds@feb90000 { - compatible = "renesas,r8a7795-lvds"; - reg = <0 0xfeb90000 0 0x14>; - clocks = <&cpg CPG_MOD 727>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 727>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - lvds0_in: endpoint { - remote-endpoint = <&du_out_lvds0>; - }; - }; - port@1 { - reg = <1>; - lvds0_out: endpoint { - }; - }; - }; - }; - - prr: chipid@fff00044 { - compatible = "renesas,prr"; - reg = <0 0xfff00044 0 4>; - }; - }; - - thermal-zones { - sensor_thermal1: sensor-thermal1 { - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&tsc 0>; - sustainable-power = <6313>; - - trips { - sensor1_crit: sensor1-crit { - temperature = <120000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - sensor_thermal2: sensor-thermal2 { - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&tsc 1>; - sustainable-power = <6313>; - - trips { - sensor2_crit: sensor2-crit { - temperature = <120000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - sensor_thermal3: sensor-thermal3 { - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&tsc 2>; - - trips { - target: trip-point1 { - temperature = <100000>; - hysteresis = <1000>; - type = "passive"; - }; - - sensor3_crit: sensor3-crit { - temperature = <120000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&target>; - cooling-device = <&a57_0 2 4>; - contribution = <1024>; - }; - - map1 { - trip = <&target>; - cooling-device = <&a53_0 0 2>; - contribution = <1024>; - }; - }; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; - }; - - /* External USB clocks - can be overridden by the board */ - usb3s0_clk: usb3s0 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - usb_extal_clk: usb_extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; -}; diff --git a/sys/gnu/dts/arm64/renesas/r8a77960-salvator-x.dts b/sys/gnu/dts/arm64/renesas/r8a77960-salvator-x.dts deleted file mode 100644 index ecfbeafeaf3..00000000000 --- a/sys/gnu/dts/arm64/renesas/r8a77960-salvator-x.dts +++ /dev/null @@ -1,83 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the Salvator-X board with R-Car M3-W - * - * Copyright (C) 2016 Renesas Electronics Corp. - */ - -/dts-v1/; -#include "r8a77960.dtsi" -#include "salvator-x.dtsi" - -/ { - model = "Renesas Salvator-X board based on r8a77960"; - compatible = "renesas,salvator-x", "renesas,r8a7796"; - - memory@48000000 { - device_type = "memory"; - /* first 128MB is reserved for secure area. */ - reg = <0x0 0x48000000 0x0 0x78000000>; - }; - - memory@600000000 { - device_type = "memory"; - reg = <0x6 0x00000000 0x0 0x80000000>; - }; -}; - -&du { - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>, - <&cpg CPG_MOD 722>, - <&versaclock5 1>, - <&x21_clk>, - <&versaclock5 2>; - clock-names = "du.0", "du.1", "du.2", - "dclkin.0", "dclkin.1", "dclkin.2"; -}; - -&hdmi0 { - status = "okay"; - - ports { - port@1 { - reg = <1>; - rcar_dw_hdmi0_out: endpoint { - remote-endpoint = <&hdmi0_con>; - }; - }; - port@2 { - reg = <2>; - dw_hdmi0_snd_in: endpoint { - remote-endpoint = <&rsnd_endpoint1>; - }; - }; - }; -}; - -&hdmi0_con { - remote-endpoint = <&rcar_dw_hdmi0_out>; -}; - -&rcar_sound { - ports { - /* rsnd_port0 is on salvator-common */ - rsnd_port1: port@1 { - reg = <1>; - rsnd_endpoint1: endpoint { - remote-endpoint = <&dw_hdmi0_snd_in>; - - dai-format = "i2s"; - bitclock-master = <&rsnd_endpoint1>; - frame-master = <&rsnd_endpoint1>; - - playback = <&ssi2>; - }; - }; - }; -}; - -&sound_card { - dais = <&rsnd_port0 /* ak4613 */ - &rsnd_port1>; /* HDMI0 */ -}; diff --git a/sys/gnu/dts/arm64/renesas/r8a77960-salvator-xs.dts b/sys/gnu/dts/arm64/renesas/r8a77960-salvator-xs.dts deleted file mode 100644 index 249896a38fd..00000000000 --- a/sys/gnu/dts/arm64/renesas/r8a77960-salvator-xs.dts +++ /dev/null @@ -1,83 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the Salvator-X 2nd version board with R-Car M3-W - * - * Copyright (C) 2015-2017 Renesas Electronics Corp. - */ - -/dts-v1/; -#include "r8a77960.dtsi" -#include "salvator-xs.dtsi" - -/ { - model = "Renesas Salvator-X 2nd version board based on r8a77960"; - compatible = "renesas,salvator-xs", "renesas,r8a7796"; - - memory@48000000 { - device_type = "memory"; - /* first 128MB is reserved for secure area. */ - reg = <0x0 0x48000000 0x0 0x78000000>; - }; - - memory@600000000 { - device_type = "memory"; - reg = <0x6 0x00000000 0x0 0x80000000>; - }; -}; - -&du { - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>, - <&cpg CPG_MOD 722>, - <&versaclock6 1>, - <&x21_clk>, - <&versaclock6 2>; - clock-names = "du.0", "du.1", "du.2", - "dclkin.0", "dclkin.1", "dclkin.2"; -}; - -&hdmi0 { - status = "okay"; - - ports { - port@1 { - reg = <1>; - rcar_dw_hdmi0_out: endpoint { - remote-endpoint = <&hdmi0_con>; - }; - }; - port@2 { - reg = <2>; - dw_hdmi0_snd_in: endpoint { - remote-endpoint = <&rsnd_endpoint1>; - }; - }; - }; -}; - -&hdmi0_con { - remote-endpoint = <&rcar_dw_hdmi0_out>; -}; - -&rcar_sound { - ports { - /* rsnd_port0 is on salvator-common */ - rsnd_port1: port@1 { - reg = <1>; - rsnd_endpoint1: endpoint { - remote-endpoint = <&dw_hdmi0_snd_in>; - - dai-format = "i2s"; - bitclock-master = <&rsnd_endpoint1>; - frame-master = <&rsnd_endpoint1>; - - playback = <&ssi2>; - }; - }; - }; -}; - -&sound_card { - dais = <&rsnd_port0 /* ak4613 */ - &rsnd_port1>; /* HDMI0 */ -}; diff --git a/sys/gnu/dts/arm64/renesas/r8a77960-ulcb-kf.dts b/sys/gnu/dts/arm64/renesas/r8a77960-ulcb-kf.dts deleted file mode 100644 index 2151c37d77a..00000000000 --- a/sys/gnu/dts/arm64/renesas/r8a77960-ulcb-kf.dts +++ /dev/null @@ -1,16 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the M3ULCB Kingfisher board - * - * Copyright (C) 2017 Renesas Electronics Corp. - * Copyright (C) 2017 Cogent Embedded, Inc. - */ - -#include "r8a77960-ulcb.dts" -#include "ulcb-kf.dtsi" - -/ { - model = "Renesas M3ULCB Kingfisher board based on r8a77960"; - compatible = "shimafuji,kingfisher", "renesas,m3ulcb", - "renesas,r8a7796"; -}; diff --git a/sys/gnu/dts/arm64/renesas/r8a77960-ulcb.dts b/sys/gnu/dts/arm64/renesas/r8a77960-ulcb.dts deleted file mode 100644 index d041042a561..00000000000 --- a/sys/gnu/dts/arm64/renesas/r8a77960-ulcb.dts +++ /dev/null @@ -1,38 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the M3ULCB (R-Car Starter Kit Pro) board - * - * Copyright (C) 2016 Renesas Electronics Corp. - * Copyright (C) 2016 Cogent Embedded, Inc. - */ - -/dts-v1/; -#include "r8a77960.dtsi" -#include "ulcb.dtsi" - -/ { - model = "Renesas M3ULCB board based on r8a77960"; - compatible = "renesas,m3ulcb", "renesas,r8a7796"; - - memory@48000000 { - device_type = "memory"; - /* first 128MB is reserved for secure area. */ - reg = <0x0 0x48000000 0x0 0x38000000>; - }; - - memory@600000000 { - device_type = "memory"; - reg = <0x6 0x00000000 0x0 0x40000000>; - }; -}; - -&du { - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>, - <&cpg CPG_MOD 722>, - <&versaclock5 1>, - <&versaclock5 3>, - <&versaclock5 2>; - clock-names = "du.0", "du.1", "du.2", - "dclkin.0", "dclkin.1", "dclkin.2"; -}; diff --git a/sys/gnu/dts/arm64/renesas/r8a77960.dtsi b/sys/gnu/dts/arm64/renesas/r8a77960.dtsi deleted file mode 100644 index 60f156cfd2d..00000000000 --- a/sys/gnu/dts/arm64/renesas/r8a77960.dtsi +++ /dev/null @@ -1,2972 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the R-Car M3-W (R8A77960) SoC - * - * Copyright (C) 2016-2017 Renesas Electronics Corp. - */ - -#include -#include -#include - -#define CPG_AUDIO_CLK_I R8A7796_CLK_S0D4 - -/ { - compatible = "renesas,r8a7796"; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - i2c6 = &i2c6; - i2c7 = &i2c_dvfs; - }; - - /* - * The external audio clocks are configured as 0 Hz fixed frequency - * clocks by default. - * Boards that provide audio clocks should override them. - */ - audio_clk_a: audio_clk_a { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - audio_clk_b: audio_clk_b { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - audio_clk_c: audio_clk_c { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - /* External CAN clock - to be overridden by boards that provide it */ - can_clk: can { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - cluster0_opp: opp_table0 { - compatible = "operating-points-v2"; - opp-shared; - - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <820000>; - clock-latency-ns = <300000>; - }; - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <820000>; - clock-latency-ns = <300000>; - }; - opp-1500000000 { - opp-hz = /bits/ 64 <1500000000>; - opp-microvolt = <820000>; - clock-latency-ns = <300000>; - }; - opp-1600000000 { - opp-hz = /bits/ 64 <1600000000>; - opp-microvolt = <900000>; - clock-latency-ns = <300000>; - turbo-mode; - }; - opp-1700000000 { - opp-hz = /bits/ 64 <1700000000>; - opp-microvolt = <900000>; - clock-latency-ns = <300000>; - turbo-mode; - }; - opp-1800000000 { - opp-hz = /bits/ 64 <1800000000>; - opp-microvolt = <960000>; - clock-latency-ns = <300000>; - turbo-mode; - }; - }; - - cluster1_opp: opp_table1 { - compatible = "operating-points-v2"; - opp-shared; - - opp-800000000 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <820000>; - clock-latency-ns = <300000>; - }; - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <820000>; - clock-latency-ns = <300000>; - }; - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <820000>; - clock-latency-ns = <300000>; - }; - opp-1300000000 { - opp-hz = /bits/ 64 <1300000000>; - opp-microvolt = <820000>; - clock-latency-ns = <300000>; - turbo-mode; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu-map { - cluster0 { - core0 { - cpu = <&a57_0>; - }; - core1 { - cpu = <&a57_1>; - }; - }; - - cluster1 { - core0 { - cpu = <&a53_0>; - }; - core1 { - cpu = <&a53_1>; - }; - core2 { - cpu = <&a53_2>; - }; - core3 { - cpu = <&a53_3>; - }; - }; - }; - - a57_0: cpu@0 { - compatible = "arm,cortex-a57"; - reg = <0x0>; - device_type = "cpu"; - power-domains = <&sysc R8A7796_PD_CA57_CPU0>; - next-level-cache = <&L2_CA57>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - dynamic-power-coefficient = <854>; - clocks = <&cpg CPG_CORE R8A7796_CLK_Z>; - operating-points-v2 = <&cluster0_opp>; - capacity-dmips-mhz = <1024>; - #cooling-cells = <2>; - }; - - a57_1: cpu@1 { - compatible = "arm,cortex-a57"; - reg = <0x1>; - device_type = "cpu"; - power-domains = <&sysc R8A7796_PD_CA57_CPU1>; - next-level-cache = <&L2_CA57>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - clocks = <&cpg CPG_CORE R8A7796_CLK_Z>; - operating-points-v2 = <&cluster0_opp>; - capacity-dmips-mhz = <1024>; - #cooling-cells = <2>; - }; - - a53_0: cpu@100 { - compatible = "arm,cortex-a53"; - reg = <0x100>; - device_type = "cpu"; - power-domains = <&sysc R8A7796_PD_CA53_CPU0>; - next-level-cache = <&L2_CA53>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_1>; - #cooling-cells = <2>; - dynamic-power-coefficient = <277>; - clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>; - operating-points-v2 = <&cluster1_opp>; - capacity-dmips-mhz = <535>; - }; - - a53_1: cpu@101 { - compatible = "arm,cortex-a53"; - reg = <0x101>; - device_type = "cpu"; - power-domains = <&sysc R8A7796_PD_CA53_CPU1>; - next-level-cache = <&L2_CA53>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_1>; - clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>; - operating-points-v2 = <&cluster1_opp>; - capacity-dmips-mhz = <535>; - }; - - a53_2: cpu@102 { - compatible = "arm,cortex-a53"; - reg = <0x102>; - device_type = "cpu"; - power-domains = <&sysc R8A7796_PD_CA53_CPU2>; - next-level-cache = <&L2_CA53>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_1>; - clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>; - operating-points-v2 = <&cluster1_opp>; - capacity-dmips-mhz = <535>; - }; - - a53_3: cpu@103 { - compatible = "arm,cortex-a53"; - reg = <0x103>; - device_type = "cpu"; - power-domains = <&sysc R8A7796_PD_CA53_CPU3>; - next-level-cache = <&L2_CA53>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_1>; - clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>; - operating-points-v2 = <&cluster1_opp>; - capacity-dmips-mhz = <535>; - }; - - L2_CA57: cache-controller-0 { - compatible = "cache"; - power-domains = <&sysc R8A7796_PD_CA57_SCU>; - cache-unified; - cache-level = <2>; - }; - - L2_CA53: cache-controller-1 { - compatible = "cache"; - power-domains = <&sysc R8A7796_PD_CA53_SCU>; - cache-unified; - cache-level = <2>; - }; - - idle-states { - entry-method = "psci"; - - CPU_SLEEP_0: cpu-sleep-0 { - compatible = "arm,idle-state"; - arm,psci-suspend-param = <0x0010000>; - local-timer-stop; - entry-latency-us = <400>; - exit-latency-us = <500>; - min-residency-us = <4000>; - }; - - CPU_SLEEP_1: cpu-sleep-1 { - compatible = "arm,idle-state"; - arm,psci-suspend-param = <0x0010000>; - local-timer-stop; - entry-latency-us = <700>; - exit-latency-us = <700>; - min-residency-us = <5000>; - }; - }; - }; - - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board */ - clock-frequency = <0>; - }; - - extalr_clk: extalr { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board */ - clock-frequency = <0>; - }; - - /* External PCIe clock - can be overridden by the board */ - pcie_bus_clk: pcie_bus { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - pmu_a53 { - compatible = "arm,cortex-a53-pmu"; - interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>; - }; - - pmu_a57 { - compatible = "arm,cortex-a57-pmu"; - interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&a57_0>, <&a57_1>; - }; - - psci { - compatible = "arm,psci-1.0", "arm,psci-0.2"; - method = "smc"; - }; - - /* External SCIF clock - to be overridden by boards that provide it */ - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - soc { - compatible = "simple-bus"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - rwdt: watchdog@e6020000 { - compatible = "renesas,r8a7796-wdt", - "renesas,rcar-gen3-wdt"; - reg = <0 0xe6020000 0 0x0c>; - clocks = <&cpg CPG_MOD 402>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 402>; - status = "disabled"; - }; - - gpio0: gpio@e6050000 { - compatible = "renesas,gpio-r8a7796", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6050000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 0 16>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 912>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 912>; - }; - - gpio1: gpio@e6051000 { - compatible = "renesas,gpio-r8a7796", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6051000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 32 29>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 911>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 911>; - }; - - gpio2: gpio@e6052000 { - compatible = "renesas,gpio-r8a7796", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6052000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 64 15>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 910>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 910>; - }; - - gpio3: gpio@e6053000 { - compatible = "renesas,gpio-r8a7796", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6053000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 96 16>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 909>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 909>; - }; - - gpio4: gpio@e6054000 { - compatible = "renesas,gpio-r8a7796", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6054000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 128 18>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 908>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 908>; - }; - - gpio5: gpio@e6055000 { - compatible = "renesas,gpio-r8a7796", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6055000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 160 26>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 907>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 907>; - }; - - gpio6: gpio@e6055400 { - compatible = "renesas,gpio-r8a7796", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6055400 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 192 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 906>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 906>; - }; - - gpio7: gpio@e6055800 { - compatible = "renesas,gpio-r8a7796", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6055800 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 224 4>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 905>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 905>; - }; - - pfc: pin-controller@e6060000 { - compatible = "renesas,pfc-r8a7796"; - reg = <0 0xe6060000 0 0x50c>; - }; - - cmt0: timer@e60f0000 { - compatible = "renesas,r8a7796-cmt0", - "renesas,rcar-gen3-cmt0"; - reg = <0 0xe60f0000 0 0x1004>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 303>; - clock-names = "fck"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 303>; - status = "disabled"; - }; - - cmt1: timer@e6130000 { - compatible = "renesas,r8a7796-cmt1", - "renesas,rcar-gen3-cmt1"; - reg = <0 0xe6130000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 302>; - clock-names = "fck"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 302>; - status = "disabled"; - }; - - cmt2: timer@e6140000 { - compatible = "renesas,r8a7796-cmt1", - "renesas,rcar-gen3-cmt1"; - reg = <0 0xe6140000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 301>; - clock-names = "fck"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 301>; - status = "disabled"; - }; - - cmt3: timer@e6148000 { - compatible = "renesas,r8a7796-cmt1", - "renesas,rcar-gen3-cmt1"; - reg = <0 0xe6148000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 300>; - clock-names = "fck"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 300>; - status = "disabled"; - }; - - cpg: clock-controller@e6150000 { - compatible = "renesas,r8a7796-cpg-mssr"; - reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk>, <&extalr_clk>; - clock-names = "extal", "extalr"; - #clock-cells = <2>; - #power-domain-cells = <0>; - #reset-cells = <1>; - }; - - rst: reset-controller@e6160000 { - compatible = "renesas,r8a7796-rst"; - reg = <0 0xe6160000 0 0x0200>; - }; - - sysc: system-controller@e6180000 { - compatible = "renesas,r8a7796-sysc"; - reg = <0 0xe6180000 0 0x0400>; - #power-domain-cells = <1>; - }; - - tsc: thermal@e6198000 { - compatible = "renesas,r8a7796-thermal"; - reg = <0 0xe6198000 0 0x100>, - <0 0xe61a0000 0 0x100>, - <0 0xe61a8000 0 0x100>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 522>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 522>; - #thermal-sensor-cells = <1>; - }; - - intc_ex: interrupt-controller@e61c0000 { - compatible = "renesas,intc-ex-r8a7796", "renesas,irqc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0 0xe61c0000 0 0x200>; - interrupts = , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 407>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 407>; - }; - - i2c0: i2c@e6500000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7796", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6500000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 931>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 931>; - dmas = <&dmac1 0x91>, <&dmac1 0x90>, - <&dmac2 0x91>, <&dmac2 0x90>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c1: i2c@e6508000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7796", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6508000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 930>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 930>; - dmas = <&dmac1 0x93>, <&dmac1 0x92>, - <&dmac2 0x93>, <&dmac2 0x92>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c2: i2c@e6510000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7796", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6510000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 929>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 929>; - dmas = <&dmac1 0x95>, <&dmac1 0x94>, - <&dmac2 0x95>, <&dmac2 0x94>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c3: i2c@e66d0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7796", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66d0000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 928>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 928>; - dmas = <&dmac0 0x97>, <&dmac0 0x96>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c4: i2c@e66d8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7796", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66d8000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 927>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 927>; - dmas = <&dmac0 0x99>, <&dmac0 0x98>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c5: i2c@e66e0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7796", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66e0000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 919>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 919>; - dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c6: i2c@e66e8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7796", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66e8000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 918>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 918>; - dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c_dvfs: i2c@e60b0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7796", - "renesas,rcar-gen3-iic", - "renesas,rmobile-iic"; - reg = <0 0xe60b0000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 926>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 926>; - dmas = <&dmac0 0x11>, <&dmac0 0x10>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - hscif0: serial@e6540000 { - compatible = "renesas,hscif-r8a7796", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6540000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 520>, - <&cpg CPG_CORE R8A7796_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x31>, <&dmac1 0x30>, - <&dmac2 0x31>, <&dmac2 0x30>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 520>; - status = "disabled"; - }; - - hscif1: serial@e6550000 { - compatible = "renesas,hscif-r8a7796", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6550000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 519>, - <&cpg CPG_CORE R8A7796_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x33>, <&dmac1 0x32>, - <&dmac2 0x33>, <&dmac2 0x32>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 519>; - status = "disabled"; - }; - - hscif2: serial@e6560000 { - compatible = "renesas,hscif-r8a7796", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6560000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 518>, - <&cpg CPG_CORE R8A7796_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x35>, <&dmac1 0x34>, - <&dmac2 0x35>, <&dmac2 0x34>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 518>; - status = "disabled"; - }; - - hscif3: serial@e66a0000 { - compatible = "renesas,hscif-r8a7796", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe66a0000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 517>, - <&cpg CPG_CORE R8A7796_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x37>, <&dmac0 0x36>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 517>; - status = "disabled"; - }; - - hscif4: serial@e66b0000 { - compatible = "renesas,hscif-r8a7796", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe66b0000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 516>, - <&cpg CPG_CORE R8A7796_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x39>, <&dmac0 0x38>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 516>; - status = "disabled"; - }; - - hsusb: usb@e6590000 { - compatible = "renesas,usbhs-r8a7796", - "renesas,rcar-gen3-usbhs"; - reg = <0 0xe6590000 0 0x200>; - interrupts = ; - clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>; - dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, - <&usb_dmac1 0>, <&usb_dmac1 1>; - dma-names = "ch0", "ch1", "ch2", "ch3"; - renesas,buswait = <11>; - phys = <&usb2_phy0 3>; - phy-names = "usb"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 704>, <&cpg 703>; - status = "disabled"; - }; - - usb_dmac0: dma-controller@e65a0000 { - compatible = "renesas,r8a7796-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65a0000 0 0x100>; - interrupts = , - ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 330>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 330>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - usb_dmac1: dma-controller@e65b0000 { - compatible = "renesas,r8a7796-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65b0000 0 0x100>; - interrupts = , - ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 331>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 331>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - usb3_phy0: usb-phy@e65ee000 { - compatible = "renesas,r8a7796-usb3-phy", - "renesas,rcar-gen3-usb3-phy"; - reg = <0 0xe65ee000 0 0x90>; - clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, - <&usb_extal_clk>; - clock-names = "usb3-if", "usb3s_clk", "usb_extal"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 328>; - #phy-cells = <0>; - status = "disabled"; - }; - - dmac0: dma-controller@e6700000 { - compatible = "renesas,dmac-r8a7796", - "renesas,rcar-dmac"; - reg = <0 0xe6700000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 219>; - clock-names = "fck"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 219>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, - <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, - <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, - <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, - <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, - <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, - <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, - <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; - }; - - dmac1: dma-controller@e7300000 { - compatible = "renesas,dmac-r8a7796", - "renesas,rcar-dmac"; - reg = <0 0xe7300000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 218>; - clock-names = "fck"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 218>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, - <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, - <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, - <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, - <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, - <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, - <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, - <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; - }; - - dmac2: dma-controller@e7310000 { - compatible = "renesas,dmac-r8a7796", - "renesas,rcar-dmac"; - reg = <0 0xe7310000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 217>; - clock-names = "fck"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 217>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, - <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, - <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, - <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, - <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, - <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, - <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, - <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; - }; - - ipmmu_ds0: mmu@e6740000 { - compatible = "renesas,ipmmu-r8a7796"; - reg = <0 0xe6740000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 0>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_ds1: mmu@e7740000 { - compatible = "renesas,ipmmu-r8a7796"; - reg = <0 0xe7740000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 1>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_hc: mmu@e6570000 { - compatible = "renesas,ipmmu-r8a7796"; - reg = <0 0xe6570000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 2>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_ir: mmu@ff8b0000 { - compatible = "renesas,ipmmu-r8a7796"; - reg = <0 0xff8b0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 3>; - power-domains = <&sysc R8A7796_PD_A3IR>; - #iommu-cells = <1>; - }; - - ipmmu_mm: mmu@e67b0000 { - compatible = "renesas,ipmmu-r8a7796"; - reg = <0 0xe67b0000 0 0x1000>; - interrupts = , - ; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_mp: mmu@ec670000 { - compatible = "renesas,ipmmu-r8a7796"; - reg = <0 0xec670000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 4>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_pv0: mmu@fd800000 { - compatible = "renesas,ipmmu-r8a7796"; - reg = <0 0xfd800000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 5>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_pv1: mmu@fd950000 { - compatible = "renesas,ipmmu-r8a7796"; - reg = <0 0xfd950000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 6>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_rt: mmu@ffc80000 { - compatible = "renesas,ipmmu-r8a7796"; - reg = <0 0xffc80000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 7>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_vc0: mmu@fe6b0000 { - compatible = "renesas,ipmmu-r8a7796"; - reg = <0 0xfe6b0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 8>; - power-domains = <&sysc R8A7796_PD_A3VC>; - #iommu-cells = <1>; - }; - - ipmmu_vi0: mmu@febd0000 { - compatible = "renesas,ipmmu-r8a7796"; - reg = <0 0xfebd0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 9>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - avb: ethernet@e6800000 { - compatible = "renesas,etheravb-r8a7796", - "renesas,etheravb-rcar-gen3"; - reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15", - "ch16", "ch17", "ch18", "ch19", - "ch20", "ch21", "ch22", "ch23", - "ch24"; - clocks = <&cpg CPG_MOD 812>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 812>; - phy-mode = "rgmii"; - iommus = <&ipmmu_ds0 16>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - can0: can@e6c30000 { - compatible = "renesas,can-r8a7796", - "renesas,rcar-gen3-can"; - reg = <0 0xe6c30000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 916>, - <&cpg CPG_CORE R8A7796_CLK_CANFD>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>; - assigned-clock-rates = <40000000>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 916>; - status = "disabled"; - }; - - can1: can@e6c38000 { - compatible = "renesas,can-r8a7796", - "renesas,rcar-gen3-can"; - reg = <0 0xe6c38000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 915>, - <&cpg CPG_CORE R8A7796_CLK_CANFD>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>; - assigned-clock-rates = <40000000>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 915>; - status = "disabled"; - }; - - canfd: can@e66c0000 { - compatible = "renesas,r8a7796-canfd", - "renesas,rcar-gen3-canfd"; - reg = <0 0xe66c0000 0 0x8000>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 914>, - <&cpg CPG_CORE R8A7796_CLK_CANFD>, - <&can_clk>; - clock-names = "fck", "canfd", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>; - assigned-clock-rates = <40000000>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 914>; - status = "disabled"; - - channel0 { - status = "disabled"; - }; - - channel1 { - status = "disabled"; - }; - }; - - pwm0: pwm@e6e30000 { - compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar"; - reg = <0 0xe6e30000 0 8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pwm1: pwm@e6e31000 { - compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar"; - reg = <0 0xe6e31000 0 8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pwm2: pwm@e6e32000 { - compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar"; - reg = <0 0xe6e32000 0 8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pwm3: pwm@e6e33000 { - compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar"; - reg = <0 0xe6e33000 0 8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pwm4: pwm@e6e34000 { - compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar"; - reg = <0 0xe6e34000 0 8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pwm5: pwm@e6e35000 { - compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar"; - reg = <0 0xe6e35000 0 8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pwm6: pwm@e6e36000 { - compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar"; - reg = <0 0xe6e36000 0 8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - status = "disabled"; - }; - - scif0: serial@e6e60000 { - compatible = "renesas,scif-r8a7796", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e60000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 207>, - <&cpg CPG_CORE R8A7796_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x51>, <&dmac1 0x50>, - <&dmac2 0x51>, <&dmac2 0x50>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 207>; - status = "disabled"; - }; - - scif1: serial@e6e68000 { - compatible = "renesas,scif-r8a7796", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e68000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 206>, - <&cpg CPG_CORE R8A7796_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x53>, <&dmac1 0x52>, - <&dmac2 0x53>, <&dmac2 0x52>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 206>; - status = "disabled"; - }; - - scif2: serial@e6e88000 { - compatible = "renesas,scif-r8a7796", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e88000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 310>, - <&cpg CPG_CORE R8A7796_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x13>, <&dmac1 0x12>, - <&dmac2 0x13>, <&dmac2 0x12>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 310>; - status = "disabled"; - }; - - scif3: serial@e6c50000 { - compatible = "renesas,scif-r8a7796", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6c50000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 204>, - <&cpg CPG_CORE R8A7796_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x57>, <&dmac0 0x56>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 204>; - status = "disabled"; - }; - - scif4: serial@e6c40000 { - compatible = "renesas,scif-r8a7796", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6c40000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 203>, - <&cpg CPG_CORE R8A7796_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x59>, <&dmac0 0x58>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 203>; - status = "disabled"; - }; - - scif5: serial@e6f30000 { - compatible = "renesas,scif-r8a7796", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6f30000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 202>, - <&cpg CPG_CORE R8A7796_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, - <&dmac2 0x5b>, <&dmac2 0x5a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 202>; - status = "disabled"; - }; - - tpu: pwm@e6e80000 { - compatible = "renesas,tpu-r8a7796", "renesas,tpu"; - reg = <0 0xe6e80000 0 0x148>; - interrupts = ; - clocks = <&cpg CPG_MOD 304>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 304>; - #pwm-cells = <3>; - status = "disabled"; - }; - - msiof0: spi@e6e90000 { - compatible = "renesas,msiof-r8a7796", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6e90000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 211>; - dmas = <&dmac1 0x41>, <&dmac1 0x40>, - <&dmac2 0x41>, <&dmac2 0x40>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 211>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof1: spi@e6ea0000 { - compatible = "renesas,msiof-r8a7796", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6ea0000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 210>; - dmas = <&dmac1 0x43>, <&dmac1 0x42>, - <&dmac2 0x43>, <&dmac2 0x42>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 210>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof2: spi@e6c00000 { - compatible = "renesas,msiof-r8a7796", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6c00000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 209>; - dmas = <&dmac0 0x45>, <&dmac0 0x44>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 209>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof3: spi@e6c10000 { - compatible = "renesas,msiof-r8a7796", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6c10000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 208>; - dmas = <&dmac0 0x47>, <&dmac0 0x46>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 208>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - vin0: video@e6ef0000 { - compatible = "renesas,vin-r8a7796"; - reg = <0 0xe6ef0000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 811>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 811>; - renesas,id = <0>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin0csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin0>; - }; - vin0csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin0>; - }; - }; - }; - }; - - vin1: video@e6ef1000 { - compatible = "renesas,vin-r8a7796"; - reg = <0 0xe6ef1000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 810>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 810>; - renesas,id = <1>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin1csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin1>; - }; - vin1csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin1>; - }; - }; - }; - }; - - vin2: video@e6ef2000 { - compatible = "renesas,vin-r8a7796"; - reg = <0 0xe6ef2000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 809>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 809>; - renesas,id = <2>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin2csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin2>; - }; - vin2csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin2>; - }; - }; - }; - }; - - vin3: video@e6ef3000 { - compatible = "renesas,vin-r8a7796"; - reg = <0 0xe6ef3000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 808>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 808>; - renesas,id = <3>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin3csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin3>; - }; - vin3csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin3>; - }; - }; - }; - }; - - vin4: video@e6ef4000 { - compatible = "renesas,vin-r8a7796"; - reg = <0 0xe6ef4000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 807>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 807>; - renesas,id = <4>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin4csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin4>; - }; - vin4csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin4>; - }; - }; - }; - }; - - vin5: video@e6ef5000 { - compatible = "renesas,vin-r8a7796"; - reg = <0 0xe6ef5000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 806>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 806>; - renesas,id = <5>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin5csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin5>; - }; - vin5csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin5>; - }; - }; - }; - }; - - vin6: video@e6ef6000 { - compatible = "renesas,vin-r8a7796"; - reg = <0 0xe6ef6000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 805>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 805>; - renesas,id = <6>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin6csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin6>; - }; - vin6csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin6>; - }; - }; - }; - }; - - vin7: video@e6ef7000 { - compatible = "renesas,vin-r8a7796"; - reg = <0 0xe6ef7000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 804>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 804>; - renesas,id = <7>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin7csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin7>; - }; - vin7csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin7>; - }; - }; - }; - }; - - drif00: rif@e6f40000 { - compatible = "renesas,r8a7796-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6f40000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 515>; - clock-names = "fck"; - dmas = <&dmac1 0x20>, <&dmac2 0x20>; - dma-names = "rx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 515>; - renesas,bonding = <&drif01>; - status = "disabled"; - }; - - drif01: rif@e6f50000 { - compatible = "renesas,r8a7796-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6f50000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 514>; - clock-names = "fck"; - dmas = <&dmac1 0x22>, <&dmac2 0x22>; - dma-names = "rx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 514>; - renesas,bonding = <&drif00>; - status = "disabled"; - }; - - drif10: rif@e6f60000 { - compatible = "renesas,r8a7796-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6f60000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 513>; - clock-names = "fck"; - dmas = <&dmac1 0x24>, <&dmac2 0x24>; - dma-names = "rx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 513>; - renesas,bonding = <&drif11>; - status = "disabled"; - }; - - drif11: rif@e6f70000 { - compatible = "renesas,r8a7796-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6f70000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 512>; - clock-names = "fck"; - dmas = <&dmac1 0x26>, <&dmac2 0x26>; - dma-names = "rx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 512>; - renesas,bonding = <&drif10>; - status = "disabled"; - }; - - drif20: rif@e6f80000 { - compatible = "renesas,r8a7796-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6f80000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 511>; - clock-names = "fck"; - dmas = <&dmac1 0x28>, <&dmac2 0x28>; - dma-names = "rx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 511>; - renesas,bonding = <&drif21>; - status = "disabled"; - }; - - drif21: rif@e6f90000 { - compatible = "renesas,r8a7796-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6f90000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 510>; - clock-names = "fck"; - dmas = <&dmac1 0x2a>, <&dmac2 0x2a>; - dma-names = "rx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 510>; - renesas,bonding = <&drif20>; - status = "disabled"; - }; - - drif30: rif@e6fa0000 { - compatible = "renesas,r8a7796-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6fa0000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 509>; - clock-names = "fck"; - dmas = <&dmac1 0x2c>, <&dmac2 0x2c>; - dma-names = "rx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 509>; - renesas,bonding = <&drif31>; - status = "disabled"; - }; - - drif31: rif@e6fb0000 { - compatible = "renesas,r8a7796-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6fb0000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 508>; - clock-names = "fck"; - dmas = <&dmac1 0x2e>, <&dmac2 0x2e>; - dma-names = "rx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 508>; - renesas,bonding = <&drif30>; - status = "disabled"; - }; - - rcar_sound: sound@ec500000 { - /* - * #sound-dai-cells is required - * - * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; - * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; - */ - /* - * #clock-cells is required for audio_clkout0/1/2/3 - * - * clkout : #clock-cells = <0>; <&rcar_sound>; - * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; - */ - compatible = "renesas,rcar_sound-r8a7796", "renesas,rcar_sound-gen3"; - reg = <0 0xec500000 0 0x1000>, /* SCU */ - <0 0xec5a0000 0 0x100>, /* ADG */ - <0 0xec540000 0 0x1000>, /* SSIU */ - <0 0xec541000 0 0x280>, /* SSI */ - <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ - reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; - - clocks = <&cpg CPG_MOD 1005>, - <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, - <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, - <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, - <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, - <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, - <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, - <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, - <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, - <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, - <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, - <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, - <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, - <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, - <&audio_clk_a>, <&audio_clk_b>, - <&audio_clk_c>, - <&cpg CPG_CORE R8A7796_CLK_S0D4>; - clock-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", - "ssi.5", "ssi.4", "ssi.3", "ssi.2", - "ssi.1", "ssi.0", - "src.9", "src.8", "src.7", "src.6", - "src.5", "src.4", "src.3", "src.2", - "src.1", "src.0", - "mix.1", "mix.0", - "ctu.1", "ctu.0", - "dvc.0", "dvc.1", - "clk_a", "clk_b", "clk_c", "clk_i"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 1005>, - <&cpg 1006>, <&cpg 1007>, - <&cpg 1008>, <&cpg 1009>, - <&cpg 1010>, <&cpg 1011>, - <&cpg 1012>, <&cpg 1013>, - <&cpg 1014>, <&cpg 1015>; - reset-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", - "ssi.5", "ssi.4", "ssi.3", "ssi.2", - "ssi.1", "ssi.0"; - status = "disabled"; - - rcar_sound,ctu { - ctu00: ctu-0 { }; - ctu01: ctu-1 { }; - ctu02: ctu-2 { }; - ctu03: ctu-3 { }; - ctu10: ctu-4 { }; - ctu11: ctu-5 { }; - ctu12: ctu-6 { }; - ctu13: ctu-7 { }; - }; - - rcar_sound,dvc { - dvc0: dvc-0 { - dmas = <&audma1 0xbc>; - dma-names = "tx"; - }; - dvc1: dvc-1 { - dmas = <&audma1 0xbe>; - dma-names = "tx"; - }; - }; - - rcar_sound,mix { - mix0: mix-0 { }; - mix1: mix-1 { }; - }; - - rcar_sound,src { - src0: src-0 { - interrupts = ; - dmas = <&audma0 0x85>, <&audma1 0x9a>; - dma-names = "rx", "tx"; - }; - src1: src-1 { - interrupts = ; - dmas = <&audma0 0x87>, <&audma1 0x9c>; - dma-names = "rx", "tx"; - }; - src2: src-2 { - interrupts = ; - dmas = <&audma0 0x89>, <&audma1 0x9e>; - dma-names = "rx", "tx"; - }; - src3: src-3 { - interrupts = ; - dmas = <&audma0 0x8b>, <&audma1 0xa0>; - dma-names = "rx", "tx"; - }; - src4: src-4 { - interrupts = ; - dmas = <&audma0 0x8d>, <&audma1 0xb0>; - dma-names = "rx", "tx"; - }; - src5: src-5 { - interrupts = ; - dmas = <&audma0 0x8f>, <&audma1 0xb2>; - dma-names = "rx", "tx"; - }; - src6: src-6 { - interrupts = ; - dmas = <&audma0 0x91>, <&audma1 0xb4>; - dma-names = "rx", "tx"; - }; - src7: src-7 { - interrupts = ; - dmas = <&audma0 0x93>, <&audma1 0xb6>; - dma-names = "rx", "tx"; - }; - src8: src-8 { - interrupts = ; - dmas = <&audma0 0x95>, <&audma1 0xb8>; - dma-names = "rx", "tx"; - }; - src9: src-9 { - interrupts = ; - dmas = <&audma0 0x97>, <&audma1 0xba>; - dma-names = "rx", "tx"; - }; - }; - - rcar_sound,ssi { - ssi0: ssi-0 { - interrupts = ; - dmas = <&audma0 0x01>, <&audma1 0x02>; - dma-names = "rx", "tx"; - }; - ssi1: ssi-1 { - interrupts = ; - dmas = <&audma0 0x03>, <&audma1 0x04>; - dma-names = "rx", "tx"; - }; - ssi2: ssi-2 { - interrupts = ; - dmas = <&audma0 0x05>, <&audma1 0x06>; - dma-names = "rx", "tx"; - }; - ssi3: ssi-3 { - interrupts = ; - dmas = <&audma0 0x07>, <&audma1 0x08>; - dma-names = "rx", "tx"; - }; - ssi4: ssi-4 { - interrupts = ; - dmas = <&audma0 0x09>, <&audma1 0x0a>; - dma-names = "rx", "tx"; - }; - ssi5: ssi-5 { - interrupts = ; - dmas = <&audma0 0x0b>, <&audma1 0x0c>; - dma-names = "rx", "tx"; - }; - ssi6: ssi-6 { - interrupts = ; - dmas = <&audma0 0x0d>, <&audma1 0x0e>; - dma-names = "rx", "tx"; - }; - ssi7: ssi-7 { - interrupts = ; - dmas = <&audma0 0x0f>, <&audma1 0x10>; - dma-names = "rx", "tx"; - }; - ssi8: ssi-8 { - interrupts = ; - dmas = <&audma0 0x11>, <&audma1 0x12>; - dma-names = "rx", "tx"; - }; - ssi9: ssi-9 { - interrupts = ; - dmas = <&audma0 0x13>, <&audma1 0x14>; - dma-names = "rx", "tx"; - }; - }; - - rcar_sound,ssiu { - ssiu00: ssiu-0 { - dmas = <&audma0 0x15>, <&audma1 0x16>; - dma-names = "rx", "tx"; - }; - ssiu01: ssiu-1 { - dmas = <&audma0 0x35>, <&audma1 0x36>; - dma-names = "rx", "tx"; - }; - ssiu02: ssiu-2 { - dmas = <&audma0 0x37>, <&audma1 0x38>; - dma-names = "rx", "tx"; - }; - ssiu03: ssiu-3 { - dmas = <&audma0 0x47>, <&audma1 0x48>; - dma-names = "rx", "tx"; - }; - ssiu04: ssiu-4 { - dmas = <&audma0 0x3F>, <&audma1 0x40>; - dma-names = "rx", "tx"; - }; - ssiu05: ssiu-5 { - dmas = <&audma0 0x43>, <&audma1 0x44>; - dma-names = "rx", "tx"; - }; - ssiu06: ssiu-6 { - dmas = <&audma0 0x4F>, <&audma1 0x50>; - dma-names = "rx", "tx"; - }; - ssiu07: ssiu-7 { - dmas = <&audma0 0x53>, <&audma1 0x54>; - dma-names = "rx", "tx"; - }; - ssiu10: ssiu-8 { - dmas = <&audma0 0x49>, <&audma1 0x4a>; - dma-names = "rx", "tx"; - }; - ssiu11: ssiu-9 { - dmas = <&audma0 0x4B>, <&audma1 0x4C>; - dma-names = "rx", "tx"; - }; - ssiu12: ssiu-10 { - dmas = <&audma0 0x57>, <&audma1 0x58>; - dma-names = "rx", "tx"; - }; - ssiu13: ssiu-11 { - dmas = <&audma0 0x59>, <&audma1 0x5A>; - dma-names = "rx", "tx"; - }; - ssiu14: ssiu-12 { - dmas = <&audma0 0x5F>, <&audma1 0x60>; - dma-names = "rx", "tx"; - }; - ssiu15: ssiu-13 { - dmas = <&audma0 0xC3>, <&audma1 0xC4>; - dma-names = "rx", "tx"; - }; - ssiu16: ssiu-14 { - dmas = <&audma0 0xC7>, <&audma1 0xC8>; - dma-names = "rx", "tx"; - }; - ssiu17: ssiu-15 { - dmas = <&audma0 0xCB>, <&audma1 0xCC>; - dma-names = "rx", "tx"; - }; - ssiu20: ssiu-16 { - dmas = <&audma0 0x63>, <&audma1 0x64>; - dma-names = "rx", "tx"; - }; - ssiu21: ssiu-17 { - dmas = <&audma0 0x67>, <&audma1 0x68>; - dma-names = "rx", "tx"; - }; - ssiu22: ssiu-18 { - dmas = <&audma0 0x6B>, <&audma1 0x6C>; - dma-names = "rx", "tx"; - }; - ssiu23: ssiu-19 { - dmas = <&audma0 0x6D>, <&audma1 0x6E>; - dma-names = "rx", "tx"; - }; - ssiu24: ssiu-20 { - dmas = <&audma0 0xCF>, <&audma1 0xCE>; - dma-names = "rx", "tx"; - }; - ssiu25: ssiu-21 { - dmas = <&audma0 0xEB>, <&audma1 0xEC>; - dma-names = "rx", "tx"; - }; - ssiu26: ssiu-22 { - dmas = <&audma0 0xED>, <&audma1 0xEE>; - dma-names = "rx", "tx"; - }; - ssiu27: ssiu-23 { - dmas = <&audma0 0xEF>, <&audma1 0xF0>; - dma-names = "rx", "tx"; - }; - ssiu30: ssiu-24 { - dmas = <&audma0 0x6f>, <&audma1 0x70>; - dma-names = "rx", "tx"; - }; - ssiu31: ssiu-25 { - dmas = <&audma0 0x21>, <&audma1 0x22>; - dma-names = "rx", "tx"; - }; - ssiu32: ssiu-26 { - dmas = <&audma0 0x23>, <&audma1 0x24>; - dma-names = "rx", "tx"; - }; - ssiu33: ssiu-27 { - dmas = <&audma0 0x25>, <&audma1 0x26>; - dma-names = "rx", "tx"; - }; - ssiu34: ssiu-28 { - dmas = <&audma0 0x27>, <&audma1 0x28>; - dma-names = "rx", "tx"; - }; - ssiu35: ssiu-29 { - dmas = <&audma0 0x29>, <&audma1 0x2A>; - dma-names = "rx", "tx"; - }; - ssiu36: ssiu-30 { - dmas = <&audma0 0x2B>, <&audma1 0x2C>; - dma-names = "rx", "tx"; - }; - ssiu37: ssiu-31 { - dmas = <&audma0 0x2D>, <&audma1 0x2E>; - dma-names = "rx", "tx"; - }; - ssiu40: ssiu-32 { - dmas = <&audma0 0x71>, <&audma1 0x72>; - dma-names = "rx", "tx"; - }; - ssiu41: ssiu-33 { - dmas = <&audma0 0x17>, <&audma1 0x18>; - dma-names = "rx", "tx"; - }; - ssiu42: ssiu-34 { - dmas = <&audma0 0x19>, <&audma1 0x1A>; - dma-names = "rx", "tx"; - }; - ssiu43: ssiu-35 { - dmas = <&audma0 0x1B>, <&audma1 0x1C>; - dma-names = "rx", "tx"; - }; - ssiu44: ssiu-36 { - dmas = <&audma0 0x1D>, <&audma1 0x1E>; - dma-names = "rx", "tx"; - }; - ssiu45: ssiu-37 { - dmas = <&audma0 0x1F>, <&audma1 0x20>; - dma-names = "rx", "tx"; - }; - ssiu46: ssiu-38 { - dmas = <&audma0 0x31>, <&audma1 0x32>; - dma-names = "rx", "tx"; - }; - ssiu47: ssiu-39 { - dmas = <&audma0 0x33>, <&audma1 0x34>; - dma-names = "rx", "tx"; - }; - ssiu50: ssiu-40 { - dmas = <&audma0 0x73>, <&audma1 0x74>; - dma-names = "rx", "tx"; - }; - ssiu60: ssiu-41 { - dmas = <&audma0 0x75>, <&audma1 0x76>; - dma-names = "rx", "tx"; - }; - ssiu70: ssiu-42 { - dmas = <&audma0 0x79>, <&audma1 0x7a>; - dma-names = "rx", "tx"; - }; - ssiu80: ssiu-43 { - dmas = <&audma0 0x7b>, <&audma1 0x7c>; - dma-names = "rx", "tx"; - }; - ssiu90: ssiu-44 { - dmas = <&audma0 0x7d>, <&audma1 0x7e>; - dma-names = "rx", "tx"; - }; - ssiu91: ssiu-45 { - dmas = <&audma0 0x7F>, <&audma1 0x80>; - dma-names = "rx", "tx"; - }; - ssiu92: ssiu-46 { - dmas = <&audma0 0x81>, <&audma1 0x82>; - dma-names = "rx", "tx"; - }; - ssiu93: ssiu-47 { - dmas = <&audma0 0x83>, <&audma1 0x84>; - dma-names = "rx", "tx"; - }; - ssiu94: ssiu-48 { - dmas = <&audma0 0xA3>, <&audma1 0xA4>; - dma-names = "rx", "tx"; - }; - ssiu95: ssiu-49 { - dmas = <&audma0 0xA5>, <&audma1 0xA6>; - dma-names = "rx", "tx"; - }; - ssiu96: ssiu-50 { - dmas = <&audma0 0xA7>, <&audma1 0xA8>; - dma-names = "rx", "tx"; - }; - ssiu97: ssiu-51 { - dmas = <&audma0 0xA9>, <&audma1 0xAA>; - dma-names = "rx", "tx"; - }; - }; - }; - - audma0: dma-controller@ec700000 { - compatible = "renesas,dmac-r8a7796", - "renesas,rcar-dmac"; - reg = <0 0xec700000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 502>; - clock-names = "fck"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 502>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>, - <&ipmmu_mp 2>, <&ipmmu_mp 3>, - <&ipmmu_mp 4>, <&ipmmu_mp 5>, - <&ipmmu_mp 6>, <&ipmmu_mp 7>, - <&ipmmu_mp 8>, <&ipmmu_mp 9>, - <&ipmmu_mp 10>, <&ipmmu_mp 11>, - <&ipmmu_mp 12>, <&ipmmu_mp 13>, - <&ipmmu_mp 14>, <&ipmmu_mp 15>; - }; - - audma1: dma-controller@ec720000 { - compatible = "renesas,dmac-r8a7796", - "renesas,rcar-dmac"; - reg = <0 0xec720000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 501>; - clock-names = "fck"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 501>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_mp 16>, <&ipmmu_mp 17>, - <&ipmmu_mp 18>, <&ipmmu_mp 19>, - <&ipmmu_mp 20>, <&ipmmu_mp 21>, - <&ipmmu_mp 22>, <&ipmmu_mp 23>, - <&ipmmu_mp 24>, <&ipmmu_mp 25>, - <&ipmmu_mp 26>, <&ipmmu_mp 27>, - <&ipmmu_mp 28>, <&ipmmu_mp 29>, - <&ipmmu_mp 30>, <&ipmmu_mp 31>; - }; - - xhci0: usb@ee000000 { - compatible = "renesas,xhci-r8a7796", - "renesas,rcar-gen3-xhci"; - reg = <0 0xee000000 0 0xc00>; - interrupts = ; - clocks = <&cpg CPG_MOD 328>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 328>; - status = "disabled"; - }; - - usb3_peri0: usb@ee020000 { - compatible = "renesas,r8a7796-usb3-peri", - "renesas,rcar-gen3-usb3-peri"; - reg = <0 0xee020000 0 0x400>; - interrupts = ; - clocks = <&cpg CPG_MOD 328>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 328>; - status = "disabled"; - }; - - ohci0: usb@ee080000 { - compatible = "generic-ohci"; - reg = <0 0xee080000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; - phys = <&usb2_phy0 1>; - phy-names = "usb"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 703>, <&cpg 704>; - status = "disabled"; - }; - - ohci1: usb@ee0a0000 { - compatible = "generic-ohci"; - reg = <0 0xee0a0000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 702>; - phys = <&usb2_phy1 1>; - phy-names = "usb"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 702>; - status = "disabled"; - }; - - ehci0: usb@ee080100 { - compatible = "generic-ehci"; - reg = <0 0xee080100 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; - phys = <&usb2_phy0 2>; - phy-names = "usb"; - companion = <&ohci0>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 703>, <&cpg 704>; - status = "disabled"; - }; - - ehci1: usb@ee0a0100 { - compatible = "generic-ehci"; - reg = <0 0xee0a0100 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 702>; - phys = <&usb2_phy1 2>; - phy-names = "usb"; - companion = <&ohci1>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 702>; - status = "disabled"; - }; - - usb2_phy0: usb-phy@ee080200 { - compatible = "renesas,usb2-phy-r8a7796", - "renesas,rcar-gen3-usb2-phy"; - reg = <0 0xee080200 0 0x700>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 703>, <&cpg 704>; - #phy-cells = <1>; - status = "disabled"; - }; - - usb2_phy1: usb-phy@ee0a0200 { - compatible = "renesas,usb2-phy-r8a7796", - "renesas,rcar-gen3-usb2-phy"; - reg = <0 0xee0a0200 0 0x700>; - clocks = <&cpg CPG_MOD 702>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 702>; - #phy-cells = <1>; - status = "disabled"; - }; - - sdhi0: sd@ee100000 { - compatible = "renesas,sdhi-r8a7796", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee100000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 314>; - max-frequency = <200000000>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 314>; - iommus = <&ipmmu_ds1 32>; - status = "disabled"; - }; - - sdhi1: sd@ee120000 { - compatible = "renesas,sdhi-r8a7796", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee120000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 313>; - max-frequency = <200000000>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 313>; - iommus = <&ipmmu_ds1 33>; - status = "disabled"; - }; - - sdhi2: sd@ee140000 { - compatible = "renesas,sdhi-r8a7796", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee140000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 312>; - max-frequency = <200000000>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 312>; - iommus = <&ipmmu_ds1 34>; - status = "disabled"; - }; - - sdhi3: sd@ee160000 { - compatible = "renesas,sdhi-r8a7796", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee160000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 311>; - max-frequency = <200000000>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 311>; - iommus = <&ipmmu_ds1 35>; - status = "disabled"; - }; - - gic: interrupt-controller@f1010000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x0 0xf1010000 0 0x1000>, - <0x0 0xf1020000 0 0x20000>, - <0x0 0xf1040000 0 0x20000>, - <0x0 0xf1060000 0 0x20000>; - interrupts = ; - clocks = <&cpg CPG_MOD 408>; - clock-names = "clk"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 408>; - }; - - pciec0: pcie@fe000000 { - compatible = "renesas,pcie-r8a7796", - "renesas,pcie-rcar-gen3"; - reg = <0 0xfe000000 0 0x80000>; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x00 0xff>; - device_type = "pci"; - ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, - <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, - <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, - <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; - interrupts = , - , - ; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; - clock-names = "pcie", "pcie_bus"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 319>; - status = "disabled"; - }; - - pciec1: pcie@ee800000 { - compatible = "renesas,pcie-r8a7796", - "renesas,pcie-rcar-gen3"; - reg = <0 0xee800000 0 0x80000>; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x00 0xff>; - device_type = "pci"; - ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>, - <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>, - <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>, - <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; - interrupts = , - , - ; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>; - clock-names = "pcie", "pcie_bus"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 318>; - status = "disabled"; - }; - - imr-lx4@fe860000 { - compatible = "renesas,r8a7796-imr-lx4", - "renesas,imr-lx4"; - reg = <0 0xfe860000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 823>; - power-domains = <&sysc R8A7796_PD_A3VC>; - resets = <&cpg 823>; - }; - - imr-lx4@fe870000 { - compatible = "renesas,r8a7796-imr-lx4", - "renesas,imr-lx4"; - reg = <0 0xfe870000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 822>; - power-domains = <&sysc R8A7796_PD_A3VC>; - resets = <&cpg 822>; - }; - - fdp1@fe940000 { - compatible = "renesas,fdp1"; - reg = <0 0xfe940000 0 0x2400>; - interrupts = ; - clocks = <&cpg CPG_MOD 119>; - power-domains = <&sysc R8A7796_PD_A3VC>; - resets = <&cpg 119>; - renesas,fcp = <&fcpf0>; - }; - - fcpf0: fcp@fe950000 { - compatible = "renesas,fcpf"; - reg = <0 0xfe950000 0 0x200>; - clocks = <&cpg CPG_MOD 615>; - power-domains = <&sysc R8A7796_PD_A3VC>; - resets = <&cpg 615>; - }; - - fcpvb0: fcp@fe96f000 { - compatible = "renesas,fcpv"; - reg = <0 0xfe96f000 0 0x200>; - clocks = <&cpg CPG_MOD 607>; - power-domains = <&sysc R8A7796_PD_A3VC>; - resets = <&cpg 607>; - }; - - fcpvi0: fcp@fe9af000 { - compatible = "renesas,fcpv"; - reg = <0 0xfe9af000 0 0x200>; - clocks = <&cpg CPG_MOD 611>; - power-domains = <&sysc R8A7796_PD_A3VC>; - resets = <&cpg 611>; - iommus = <&ipmmu_vc0 19>; - }; - - fcpvd0: fcp@fea27000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea27000 0 0x200>; - clocks = <&cpg CPG_MOD 603>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 603>; - iommus = <&ipmmu_vi0 8>; - }; - - fcpvd1: fcp@fea2f000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea2f000 0 0x200>; - clocks = <&cpg CPG_MOD 602>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 602>; - iommus = <&ipmmu_vi0 9>; - }; - - fcpvd2: fcp@fea37000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea37000 0 0x200>; - clocks = <&cpg CPG_MOD 601>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 601>; - iommus = <&ipmmu_vi0 10>; - }; - - vspb: vsp@fe960000 { - compatible = "renesas,vsp2"; - reg = <0 0xfe960000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 626>; - power-domains = <&sysc R8A7796_PD_A3VC>; - resets = <&cpg 626>; - - renesas,fcp = <&fcpvb0>; - }; - - vspd0: vsp@fea20000 { - compatible = "renesas,vsp2"; - reg = <0 0xfea20000 0 0x5000>; - interrupts = ; - clocks = <&cpg CPG_MOD 623>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 623>; - - renesas,fcp = <&fcpvd0>; - }; - - vspd1: vsp@fea28000 { - compatible = "renesas,vsp2"; - reg = <0 0xfea28000 0 0x5000>; - interrupts = ; - clocks = <&cpg CPG_MOD 622>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 622>; - - renesas,fcp = <&fcpvd1>; - }; - - vspd2: vsp@fea30000 { - compatible = "renesas,vsp2"; - reg = <0 0xfea30000 0 0x5000>; - interrupts = ; - clocks = <&cpg CPG_MOD 621>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 621>; - - renesas,fcp = <&fcpvd2>; - }; - - vspi0: vsp@fe9a0000 { - compatible = "renesas,vsp2"; - reg = <0 0xfe9a0000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 631>; - power-domains = <&sysc R8A7796_PD_A3VC>; - resets = <&cpg 631>; - - renesas,fcp = <&fcpvi0>; - }; - - cmm0: cmm@fea40000 { - compatible = "renesas,r8a7796-cmm", - "renesas,rcar-gen3-cmm"; - reg = <0 0xfea40000 0 0x1000>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - clocks = <&cpg CPG_MOD 711>; - resets = <&cpg 711>; - }; - - cmm1: cmm@fea50000 { - compatible = "renesas,r8a7796-cmm", - "renesas,rcar-gen3-cmm"; - reg = <0 0xfea50000 0 0x1000>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - clocks = <&cpg CPG_MOD 710>; - resets = <&cpg 710>; - }; - - cmm2: cmm@fea60000 { - compatible = "renesas,r8a7796-cmm", - "renesas,rcar-gen3-cmm"; - reg = <0 0xfea60000 0 0x1000>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - clocks = <&cpg CPG_MOD 709>; - resets = <&cpg 709>; - }; - - csi20: csi2@fea80000 { - compatible = "renesas,r8a7796-csi2"; - reg = <0 0xfea80000 0 0x10000>; - interrupts = ; - clocks = <&cpg CPG_MOD 714>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 714>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - csi20vin0: endpoint@0 { - reg = <0>; - remote-endpoint = <&vin0csi20>; - }; - csi20vin1: endpoint@1 { - reg = <1>; - remote-endpoint = <&vin1csi20>; - }; - csi20vin2: endpoint@2 { - reg = <2>; - remote-endpoint = <&vin2csi20>; - }; - csi20vin3: endpoint@3 { - reg = <3>; - remote-endpoint = <&vin3csi20>; - }; - csi20vin4: endpoint@4 { - reg = <4>; - remote-endpoint = <&vin4csi20>; - }; - csi20vin5: endpoint@5 { - reg = <5>; - remote-endpoint = <&vin5csi20>; - }; - csi20vin6: endpoint@6 { - reg = <6>; - remote-endpoint = <&vin6csi20>; - }; - csi20vin7: endpoint@7 { - reg = <7>; - remote-endpoint = <&vin7csi20>; - }; - }; - }; - }; - - csi40: csi2@feaa0000 { - compatible = "renesas,r8a7796-csi2"; - reg = <0 0xfeaa0000 0 0x10000>; - interrupts = ; - clocks = <&cpg CPG_MOD 716>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 716>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - csi40vin0: endpoint@0 { - reg = <0>; - remote-endpoint = <&vin0csi40>; - }; - csi40vin1: endpoint@1 { - reg = <1>; - remote-endpoint = <&vin1csi40>; - }; - csi40vin2: endpoint@2 { - reg = <2>; - remote-endpoint = <&vin2csi40>; - }; - csi40vin3: endpoint@3 { - reg = <3>; - remote-endpoint = <&vin3csi40>; - }; - csi40vin4: endpoint@4 { - reg = <4>; - remote-endpoint = <&vin4csi40>; - }; - csi40vin5: endpoint@5 { - reg = <5>; - remote-endpoint = <&vin5csi40>; - }; - csi40vin6: endpoint@6 { - reg = <6>; - remote-endpoint = <&vin6csi40>; - }; - csi40vin7: endpoint@7 { - reg = <7>; - remote-endpoint = <&vin7csi40>; - }; - }; - - }; - }; - - hdmi0: hdmi@fead0000 { - compatible = "renesas,r8a7796-hdmi", "renesas,rcar-gen3-hdmi"; - reg = <0 0xfead0000 0 0x10000>; - interrupts = ; - clocks = <&cpg CPG_MOD 729>, <&cpg CPG_CORE R8A7796_CLK_HDMI>; - clock-names = "iahb", "isfr"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 729>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - dw_hdmi0_in: endpoint { - remote-endpoint = <&du_out_hdmi0>; - }; - }; - port@1 { - reg = <1>; - }; - port@2 { - /* HDMI sound */ - reg = <2>; - }; - }; - }; - - du: display@feb00000 { - compatible = "renesas,du-r8a7796"; - reg = <0 0xfeb00000 0 0x70000>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>, - <&cpg CPG_MOD 722>; - clock-names = "du.0", "du.1", "du.2"; - - renesas,cmms = <&cmm0>, <&cmm1>, <&cmm2>; - vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>; - - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - du_out_rgb: endpoint { - }; - }; - port@1 { - reg = <1>; - du_out_hdmi0: endpoint { - remote-endpoint = <&dw_hdmi0_in>; - }; - }; - port@2 { - reg = <2>; - du_out_lvds0: endpoint { - remote-endpoint = <&lvds0_in>; - }; - }; - }; - }; - - lvds0: lvds@feb90000 { - compatible = "renesas,r8a7796-lvds"; - reg = <0 0xfeb90000 0 0x14>; - clocks = <&cpg CPG_MOD 727>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 727>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - lvds0_in: endpoint { - remote-endpoint = <&du_out_lvds0>; - }; - }; - port@1 { - reg = <1>; - lvds0_out: endpoint { - }; - }; - }; - }; - - prr: chipid@fff00044 { - compatible = "renesas,prr"; - reg = <0 0xfff00044 0 4>; - }; - }; - - thermal-zones { - sensor_thermal1: sensor-thermal1 { - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&tsc 0>; - sustainable-power = <3874>; - - trips { - sensor1_crit: sensor1-crit { - temperature = <120000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - sensor_thermal2: sensor-thermal2 { - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&tsc 1>; - sustainable-power = <3874>; - - trips { - sensor2_crit: sensor2-crit { - temperature = <120000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - sensor_thermal3: sensor-thermal3 { - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&tsc 2>; - sustainable-power = <3874>; - - cooling-maps { - map0 { - trip = <&target>; - cooling-device = <&a57_0 2 4>; - contribution = <1024>; - }; - map1 { - trip = <&target>; - cooling-device = <&a53_0 0 2>; - contribution = <1024>; - }; - }; - trips { - target: trip-point1 { - temperature = <100000>; - hysteresis = <1000>; - type = "passive"; - }; - - sensor3_crit: sensor3-crit { - temperature = <120000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; - }; - - /* External USB clocks - can be overridden by the board */ - usb3s0_clk: usb3s0 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - usb_extal_clk: usb_extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; -}; diff --git a/sys/gnu/dts/arm64/renesas/r8a77961-salvator-xs.dts b/sys/gnu/dts/arm64/renesas/r8a77961-salvator-xs.dts deleted file mode 100644 index 4abd78ac1cd..00000000000 --- a/sys/gnu/dts/arm64/renesas/r8a77961-salvator-xs.dts +++ /dev/null @@ -1,31 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the Salvator-X 2nd version board with R-Car M3-W+ - * - * Copyright (C) 2018 Renesas Electronics Corp. - */ - -/dts-v1/; -#include "r8a77961.dtsi" -#include "salvator-xs.dtsi" - -/ { - model = "Renesas Salvator-X 2nd version board based on r8a77961"; - compatible = "renesas,salvator-xs", "renesas,r8a77961"; - - memory@48000000 { - device_type = "memory"; - /* first 128MB is reserved for secure area. */ - reg = <0x0 0x48000000 0x0 0x78000000>; - }; - - memory@400000000 { - device_type = "memory"; - reg = <0x4 0x80000000 0x0 0x80000000>; - }; - - memory@600000000 { - device_type = "memory"; - reg = <0x6 0x00000000 0x1 0x00000000>; - }; -}; diff --git a/sys/gnu/dts/arm64/renesas/r8a77961.dtsi b/sys/gnu/dts/arm64/renesas/r8a77961.dtsi deleted file mode 100644 index be3824bda63..00000000000 --- a/sys/gnu/dts/arm64/renesas/r8a77961.dtsi +++ /dev/null @@ -1,1087 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the R-Car M3-W+ (R8A77961) SoC - * - * Copyright (C) 2016-2017 Renesas Electronics Corp. - */ - -#include -#include -#include - -#define CPG_AUDIO_CLK_I R8A77961_CLK_S0D4 - -/ { - compatible = "renesas,r8a77961"; - #address-cells = <2>; - #size-cells = <2>; - - /* - * The external audio clocks are configured as 0 Hz fixed frequency - * clocks by default. - * Boards that provide audio clocks should override them. - */ - audio_clk_a: audio_clk_a { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - audio_clk_b: audio_clk_b { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - audio_clk_c: audio_clk_c { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - /* External CAN clock - to be overridden by boards that provide it */ - can_clk: can { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - cluster0_opp: opp_table0 { - compatible = "operating-points-v2"; - opp-shared; - - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <820000>; - clock-latency-ns = <300000>; - }; - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <820000>; - clock-latency-ns = <300000>; - }; - opp-1500000000 { - opp-hz = /bits/ 64 <1500000000>; - opp-microvolt = <820000>; - clock-latency-ns = <300000>; - }; - opp-1600000000 { - opp-hz = /bits/ 64 <1600000000>; - opp-microvolt = <900000>; - clock-latency-ns = <300000>; - turbo-mode; - }; - opp-1700000000 { - opp-hz = /bits/ 64 <1700000000>; - opp-microvolt = <900000>; - clock-latency-ns = <300000>; - turbo-mode; - }; - opp-1800000000 { - opp-hz = /bits/ 64 <1800000000>; - opp-microvolt = <960000>; - clock-latency-ns = <300000>; - turbo-mode; - }; - }; - - cluster1_opp: opp_table1 { - compatible = "operating-points-v2"; - opp-shared; - - opp-800000000 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <820000>; - clock-latency-ns = <300000>; - }; - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <820000>; - clock-latency-ns = <300000>; - }; - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <820000>; - clock-latency-ns = <300000>; - }; - opp-1300000000 { - opp-hz = /bits/ 64 <1300000000>; - opp-microvolt = <820000>; - clock-latency-ns = <300000>; - turbo-mode; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu-map { - cluster0 { - core0 { - cpu = <&a57_0>; - }; - core1 { - cpu = <&a57_1>; - }; - }; - - cluster1 { - core0 { - cpu = <&a53_0>; - }; - core1 { - cpu = <&a53_1>; - }; - core2 { - cpu = <&a53_2>; - }; - core3 { - cpu = <&a53_3>; - }; - }; - }; - - a57_0: cpu@0 { - compatible = "arm,cortex-a57"; - reg = <0x0>; - device_type = "cpu"; - power-domains = <&sysc R8A77961_PD_CA57_CPU0>; - next-level-cache = <&L2_CA57>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - dynamic-power-coefficient = <854>; - clocks = <&cpg CPG_CORE R8A77961_CLK_Z>; - operating-points-v2 = <&cluster0_opp>; - capacity-dmips-mhz = <1024>; - #cooling-cells = <2>; - }; - - a57_1: cpu@1 { - compatible = "arm,cortex-a57"; - reg = <0x1>; - device_type = "cpu"; - power-domains = <&sysc R8A77961_PD_CA57_CPU1>; - next-level-cache = <&L2_CA57>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - clocks = <&cpg CPG_CORE R8A77961_CLK_Z>; - operating-points-v2 = <&cluster0_opp>; - capacity-dmips-mhz = <1024>; - #cooling-cells = <2>; - }; - - a53_0: cpu@100 { - compatible = "arm,cortex-a53"; - reg = <0x100>; - device_type = "cpu"; - power-domains = <&sysc R8A77961_PD_CA53_CPU0>; - next-level-cache = <&L2_CA53>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_1>; - #cooling-cells = <2>; - dynamic-power-coefficient = <277>; - clocks = <&cpg CPG_CORE R8A77961_CLK_Z2>; - operating-points-v2 = <&cluster1_opp>; - capacity-dmips-mhz = <535>; - }; - - a53_1: cpu@101 { - compatible = "arm,cortex-a53"; - reg = <0x101>; - device_type = "cpu"; - power-domains = <&sysc R8A77961_PD_CA53_CPU1>; - next-level-cache = <&L2_CA53>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_1>; - clocks = <&cpg CPG_CORE R8A77961_CLK_Z2>; - operating-points-v2 = <&cluster1_opp>; - capacity-dmips-mhz = <535>; - }; - - a53_2: cpu@102 { - compatible = "arm,cortex-a53"; - reg = <0x102>; - device_type = "cpu"; - power-domains = <&sysc R8A77961_PD_CA53_CPU2>; - next-level-cache = <&L2_CA53>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_1>; - clocks = <&cpg CPG_CORE R8A77961_CLK_Z2>; - operating-points-v2 = <&cluster1_opp>; - capacity-dmips-mhz = <535>; - }; - - a53_3: cpu@103 { - compatible = "arm,cortex-a53"; - reg = <0x103>; - device_type = "cpu"; - power-domains = <&sysc R8A77961_PD_CA53_CPU3>; - next-level-cache = <&L2_CA53>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_1>; - clocks = <&cpg CPG_CORE R8A77961_CLK_Z2>; - operating-points-v2 = <&cluster1_opp>; - capacity-dmips-mhz = <535>; - }; - - L2_CA57: cache-controller-0 { - compatible = "cache"; - power-domains = <&sysc R8A77961_PD_CA57_SCU>; - cache-unified; - cache-level = <2>; - }; - - L2_CA53: cache-controller-1 { - compatible = "cache"; - power-domains = <&sysc R8A77961_PD_CA53_SCU>; - cache-unified; - cache-level = <2>; - }; - - idle-states { - entry-method = "psci"; - - CPU_SLEEP_0: cpu-sleep-0 { - compatible = "arm,idle-state"; - arm,psci-suspend-param = <0x0010000>; - local-timer-stop; - entry-latency-us = <400>; - exit-latency-us = <500>; - min-residency-us = <4000>; - }; - - CPU_SLEEP_1: cpu-sleep-1 { - compatible = "arm,idle-state"; - arm,psci-suspend-param = <0x0010000>; - local-timer-stop; - entry-latency-us = <700>; - exit-latency-us = <700>; - min-residency-us = <5000>; - }; - }; - }; - - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board */ - clock-frequency = <0>; - }; - - extalr_clk: extalr { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board */ - clock-frequency = <0>; - }; - - /* External PCIe clock - can be overridden by the board */ - pcie_bus_clk: pcie_bus { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - pmu_a53 { - compatible = "arm,cortex-a53-pmu"; - interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>; - }; - - pmu_a57 { - compatible = "arm,cortex-a57-pmu"; - interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&a57_0>, <&a57_1>; - }; - - psci { - compatible = "arm,psci-1.0", "arm,psci-0.2"; - method = "smc"; - }; - - /* External SCIF clock - to be overridden by boards that provide it */ - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - soc { - compatible = "simple-bus"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - rwdt: watchdog@e6020000 { - compatible = "renesas,r8a77961-wdt", - "renesas,rcar-gen3-wdt"; - reg = <0 0xe6020000 0 0x0c>; - clocks = <&cpg CPG_MOD 402>; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - resets = <&cpg 402>; - status = "disabled"; - }; - - gpio0: gpio@e6050000 { - compatible = "renesas,gpio-r8a77961", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6050000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 0 16>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 912>; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - resets = <&cpg 912>; - }; - - gpio1: gpio@e6051000 { - compatible = "renesas,gpio-r8a77961", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6051000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 32 29>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 911>; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - resets = <&cpg 911>; - }; - - gpio2: gpio@e6052000 { - compatible = "renesas,gpio-r8a77961", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6052000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 64 15>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 910>; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - resets = <&cpg 910>; - }; - - gpio3: gpio@e6053000 { - compatible = "renesas,gpio-r8a77961", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6053000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 96 16>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 909>; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - resets = <&cpg 909>; - }; - - gpio4: gpio@e6054000 { - compatible = "renesas,gpio-r8a77961", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6054000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 128 18>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 908>; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - resets = <&cpg 908>; - }; - - gpio5: gpio@e6055000 { - compatible = "renesas,gpio-r8a77961", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6055000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 160 26>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 907>; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - resets = <&cpg 907>; - }; - - gpio6: gpio@e6055400 { - compatible = "renesas,gpio-r8a77961", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6055400 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 192 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 906>; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - resets = <&cpg 906>; - }; - - gpio7: gpio@e6055800 { - compatible = "renesas,gpio-r8a77961", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6055800 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 224 4>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 905>; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - resets = <&cpg 905>; - }; - - pfc: pin-controller@e6060000 { - compatible = "renesas,pfc-r8a77961"; - reg = <0 0xe6060000 0 0x50c>; - }; - - cpg: clock-controller@e6150000 { - compatible = "renesas,r8a77961-cpg-mssr"; - reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk>, <&extalr_clk>; - clock-names = "extal", "extalr"; - #clock-cells = <2>; - #power-domain-cells = <0>; - #reset-cells = <1>; - }; - - rst: reset-controller@e6160000 { - compatible = "renesas,r8a77961-rst"; - reg = <0 0xe6160000 0 0x0200>; - }; - - sysc: system-controller@e6180000 { - compatible = "renesas,r8a77961-sysc"; - reg = <0 0xe6180000 0 0x0400>; - #power-domain-cells = <1>; - }; - - intc_ex: interrupt-controller@e61c0000 { - #interrupt-cells = <2>; - interrupt-controller; - reg = <0 0xe61c0000 0 0x200>; - /* placeholder */ - }; - - i2c0: i2c@e6500000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a77961", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6500000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 931>; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - resets = <&cpg 931>; - dmas = <&dmac1 0x91>, <&dmac1 0x90>, - <&dmac2 0x91>, <&dmac2 0x90>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c1: i2c@e6508000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a77961", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6508000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 930>; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - resets = <&cpg 930>; - dmas = <&dmac1 0x93>, <&dmac1 0x92>, - <&dmac2 0x93>, <&dmac2 0x92>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c2: i2c@e6510000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a77961", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6510000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 929>; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - resets = <&cpg 929>; - dmas = <&dmac1 0x95>, <&dmac1 0x94>, - <&dmac2 0x95>, <&dmac2 0x94>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c3: i2c@e66d0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a77961", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66d0000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 928>; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - resets = <&cpg 928>; - dmas = <&dmac0 0x97>, <&dmac0 0x96>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c4: i2c@e66d8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a77961", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66d8000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 927>; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - resets = <&cpg 927>; - dmas = <&dmac0 0x99>, <&dmac0 0x98>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c5: i2c@e66e0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a77961", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66e0000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 919>; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - resets = <&cpg 919>; - dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c6: i2c@e66e8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a77961", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66e8000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 918>; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - resets = <&cpg 918>; - dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c_dvfs: i2c@e60b0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a77961", - "renesas,rcar-gen3-iic", - "renesas,rmobile-iic"; - reg = <0 0xe60b0000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 926>; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - resets = <&cpg 926>; - dmas = <&dmac0 0x11>, <&dmac0 0x10>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - - hscif1: serial@e6550000 { - reg = <0 0xe6550000 0 0x60>; - /* placeholder */ - }; - - hsusb: usb@e6590000 { - reg = <0 0xe6590000 0 0x200>; - /* placeholder */ - }; - - usb3_phy0: usb-phy@e65ee000 { - reg = <0 0xe65ee000 0 0x90>; - #phy-cells = <0>; - /* placeholder */ - }; - - dmac0: dma-controller@e6700000 { - compatible = "renesas,dmac-r8a77961", - "renesas,rcar-dmac"; - reg = <0 0xe6700000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 219>; - clock-names = "fck"; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - resets = <&cpg 219>; - #dma-cells = <1>; - dma-channels = <16>; - }; - - dmac1: dma-controller@e7300000 { - compatible = "renesas,dmac-r8a77961", - "renesas,rcar-dmac"; - reg = <0 0xe7300000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 218>; - clock-names = "fck"; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - resets = <&cpg 218>; - #dma-cells = <1>; - dma-channels = <16>; - }; - - dmac2: dma-controller@e7310000 { - compatible = "renesas,dmac-r8a77961", - "renesas,rcar-dmac"; - reg = <0 0xe7310000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 217>; - clock-names = "fck"; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - resets = <&cpg 217>; - #dma-cells = <1>; - dma-channels = <16>; - }; - - avb: ethernet@e6800000 { - compatible = "renesas,etheravb-r8a77961", - "renesas,etheravb-rcar-gen3"; - reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15", - "ch16", "ch17", "ch18", "ch19", - "ch20", "ch21", "ch22", "ch23", - "ch24"; - clocks = <&cpg CPG_MOD 812>; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - resets = <&cpg 812>; - phy-mode = "rgmii"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - pwm1: pwm@e6e31000 { - reg = <0 0xe6e31000 0 8>; - #pwm-cells = <2>; - /* placeholder */ - }; - - scif1: serial@e6e68000 { - reg = <0 0xe6e68000 0 64>; - /* placeholder */ - }; - - scif2: serial@e6e88000 { - compatible = "renesas,scif-r8a77961", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e88000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 310>, - <&cpg CPG_CORE R8A77961_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - resets = <&cpg 310>; - status = "disabled"; - }; - - vin0: video@e6ef0000 { - reg = <0 0xe6ef0000 0 0x1000>; - /* placeholder */ - }; - - vin1: video@e6ef1000 { - reg = <0 0xe6ef1000 0 0x1000>; - /* placeholder */ - }; - - vin2: video@e6ef2000 { - reg = <0 0xe6ef2000 0 0x1000>; - /* placeholder */ - }; - - vin3: video@e6ef3000 { - reg = <0 0xe6ef3000 0 0x1000>; - /* placeholder */ - }; - - vin4: video@e6ef4000 { - reg = <0 0xe6ef4000 0 0x1000>; - /* placeholder */ - }; - - vin5: video@e6ef5000 { - reg = <0 0xe6ef5000 0 0x1000>; - /* placeholder */ - }; - - vin6: video@e6ef6000 { - reg = <0 0xe6ef6000 0 0x1000>; - /* placeholder */ - }; - - vin7: video@e6ef7000 { - reg = <0 0xe6ef7000 0 0x1000>; - /* placeholder */ - }; - - rcar_sound: sound@ec500000 { - reg = <0 0xec500000 0 0x1000>, /* SCU */ - <0 0xec5a0000 0 0x100>, /* ADG */ - <0 0xec540000 0 0x1000>, /* SSIU */ - <0 0xec541000 0 0x280>, /* SSI */ - <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ - /* placeholder */ - rcar_sound,dvc { - dvc0: dvc-0 { }; - dvc1: dvc-1 { }; - }; - - rcar_sound,src { - src0: src-0 { }; - src1: src-1 { }; - }; - - rcar_sound,ssi { - ssi0: ssi-0 { }; - ssi1: ssi-1 { }; - }; - }; - - xhci0: usb@ee000000 { - reg = <0 0xee000000 0 0xc00>; - /* placeholder */ - }; - - usb3_peri0: usb@ee020000 { - reg = <0 0xee020000 0 0x400>; - /* placeholder */ - }; - - ohci0: usb@ee080000 { - reg = <0 0xee080000 0 0x100>; - /* placeholder */ - }; - - ohci1: usb@ee0a0000 { - reg = <0 0xee0a0000 0 0x100>; - /* placeholder */ - }; - - ehci0: usb@ee080100 { - reg = <0 0xee080100 0 0x100>; - /* placeholder */ - }; - - ehci1: usb@ee0a0100 { - reg = <0 0xee0a0100 0 0x100>; - /* placeholder */ - }; - - usb2_phy0: usb-phy@ee080200 { - reg = <0 0xee080200 0 0x700>; - /* placeholder */ - }; - - usb2_phy1: usb-phy@ee0a0200 { - reg = <0 0xee0a0200 0 0x700>; - /* placeholder */ - }; - - sdhi0: sd@ee100000 { - compatible = "renesas,sdhi-r8a77961", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee100000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 314>; - max-frequency = <200000000>; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - resets = <&cpg 314>; - status = "disabled"; - }; - - sdhi1: sd@ee120000 { - compatible = "renesas,sdhi-r8a77961", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee120000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 313>; - max-frequency = <200000000>; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - resets = <&cpg 313>; - status = "disabled"; - }; - - sdhi2: sd@ee140000 { - compatible = "renesas,sdhi-r8a77961", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee140000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 312>; - max-frequency = <200000000>; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - resets = <&cpg 312>; - status = "disabled"; - }; - - sdhi3: sd@ee160000 { - compatible = "renesas,sdhi-r8a77961", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee160000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 311>; - max-frequency = <200000000>; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - resets = <&cpg 311>; - status = "disabled"; - }; - - gic: interrupt-controller@f1010000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x0 0xf1010000 0 0x1000>, - <0x0 0xf1020000 0 0x20000>, - <0x0 0xf1040000 0 0x20000>, - <0x0 0xf1060000 0 0x20000>; - interrupts = ; - clocks = <&cpg CPG_MOD 408>; - clock-names = "clk"; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - resets = <&cpg 408>; - }; - - pciec0: pcie@fe000000 { - reg = <0 0xfe000000 0 0x80000>; - /* placeholder */ - }; - - pciec1: pcie@ee800000 { - reg = <0 0xee800000 0 0x80000>; - /* placeholder */ - }; - - csi20: csi2@fea80000 { - reg = <0 0xfea80000 0 0x10000>; - /* placeholder */ - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - }; - }; - - csi40: csi2@feaa0000 { - reg = <0 0xfeaa0000 0 0x10000>; - /* placeholder */ - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - }; - }; - }; - - hdmi0: hdmi@fead0000 { - reg = <0 0xfead0000 0 0x10000>; - /* placeholder */ - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - }; - port@1 { - reg = <1>; - }; - port@2 { - /* HDMI sound */ - reg = <2>; - }; - }; - }; - - du: display@feb00000 { - reg = <0 0xfeb00000 0 0x70000>; - /* placeholder */ - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - du_out_rgb: endpoint { - }; - }; - port@1 { - reg = <1>; - du_out_hdmi0: endpoint { - }; - }; - port@2 { - reg = <2>; - du_out_lvds0: endpoint { - }; - }; - }; - }; - - prr: chipid@fff00044 { - compatible = "renesas,prr"; - reg = <0 0xfff00044 0 4>; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; - }; - - /* External USB clocks - can be overridden by the board */ - usb3s0_clk: usb3s0 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - usb_extal_clk: usb_extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; -}; diff --git a/sys/gnu/dts/arm64/renesas/r8a77965-salvator-x.dts b/sys/gnu/dts/arm64/renesas/r8a77965-salvator-x.dts deleted file mode 100644 index 660a0240eec..00000000000 --- a/sys/gnu/dts/arm64/renesas/r8a77965-salvator-x.dts +++ /dev/null @@ -1,77 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the Salvator-X board with R-Car M3-N - * - * Copyright (C) 2018 Jacopo Mondi - */ - -/dts-v1/; -#include "r8a77965.dtsi" -#include "salvator-x.dtsi" - -/ { - model = "Renesas Salvator-X board based on r8a77965"; - compatible = "renesas,salvator-x", "renesas,r8a77965"; - - memory@48000000 { - device_type = "memory"; - /* first 128MB is reserved for secure area. */ - reg = <0x0 0x48000000 0x0 0x78000000>; - }; -}; - -&du { - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>, - <&cpg CPG_MOD 721>, - <&versaclock5 1>, - <&x21_clk>, - <&versaclock5 2>; - clock-names = "du.0", "du.1", "du.3", - "dclkin.0", "dclkin.1", "dclkin.3"; -}; - -&hdmi0 { - status = "okay"; - - ports { - port@1 { - reg = <1>; - rcar_dw_hdmi0_out: endpoint { - remote-endpoint = <&hdmi0_con>; - }; - }; - port@2 { - reg = <2>; - dw_hdmi0_snd_in: endpoint { - remote-endpoint = <&rsnd_endpoint1>; - }; - }; - }; -}; - -&hdmi0_con { - remote-endpoint = <&rcar_dw_hdmi0_out>; -}; - -&rcar_sound { - ports { - rsnd_port1: port@1 { - reg = <1>; - rsnd_endpoint1: endpoint { - remote-endpoint = <&dw_hdmi0_snd_in>; - - dai-format = "i2s"; - bitclock-master = <&rsnd_endpoint1>; - frame-master = <&rsnd_endpoint1>; - - playback = <&ssi2>; - }; - }; - }; -}; - -&sound_card { - dais = <&rsnd_port0 /* ak4613 */ - &rsnd_port1>; /* HDMI0 */ -}; diff --git a/sys/gnu/dts/arm64/renesas/r8a77965-salvator-xs.dts b/sys/gnu/dts/arm64/renesas/r8a77965-salvator-xs.dts deleted file mode 100644 index 5cef6460546..00000000000 --- a/sys/gnu/dts/arm64/renesas/r8a77965-salvator-xs.dts +++ /dev/null @@ -1,91 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the Salvator-X 2nd version board with R-Car M3-N - * - * Copyright (C) 2017 Renesas Electronics Corp. - */ - -/dts-v1/; -#include "r8a77965.dtsi" -#include "salvator-xs.dtsi" - -/ { - model = "Renesas Salvator-X 2nd version board based on r8a77965"; - compatible = "renesas,salvator-xs", "renesas,r8a77965"; - - memory@48000000 { - device_type = "memory"; - /* first 128MB is reserved for secure area. */ - reg = <0x0 0x48000000 0x0 0x78000000>; - }; -}; - -&du { - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>, - <&cpg CPG_MOD 721>, - <&versaclock6 1>, - <&x21_clk>, - <&versaclock6 2>; - clock-names = "du.0", "du.1", "du.3", - "dclkin.0", "dclkin.1", "dclkin.3"; -}; - -&hdmi0 { - status = "okay"; - - ports { - port@1 { - reg = <1>; - rcar_dw_hdmi0_out: endpoint { - remote-endpoint = <&hdmi0_con>; - }; - }; - port@2 { - reg = <2>; - dw_hdmi0_snd_in: endpoint { - remote-endpoint = <&rsnd_endpoint1>; - }; - }; - }; -}; - -&hdmi0_con { - remote-endpoint = <&rcar_dw_hdmi0_out>; -}; - -&pca9654 { - pcie_sata_switch { - gpio-hog; - gpios = <7 GPIO_ACTIVE_HIGH>; - output-low; /* enable SATA by default */ - line-name = "PCIE/SATA switch"; - }; -}; - -&rcar_sound { - ports { - rsnd_port1: port@1 { - reg = <1>; - rsnd_endpoint1: endpoint { - remote-endpoint = <&dw_hdmi0_snd_in>; - - dai-format = "i2s"; - bitclock-master = <&rsnd_endpoint1>; - frame-master = <&rsnd_endpoint1>; - - playback = <&ssi2>; - }; - }; - }; -}; - -/* SW12-7 must be set 'Off' (MD12 set to 1) which is not the default! */ -&sata { - status = "okay"; -}; - -&sound_card { - dais = <&rsnd_port0 /* ak4613 */ - &rsnd_port1>; /* HDMI0 */ -}; diff --git a/sys/gnu/dts/arm64/renesas/r8a77965-ulcb-kf.dts b/sys/gnu/dts/arm64/renesas/r8a77965-ulcb-kf.dts deleted file mode 100644 index 12aa08fd6fd..00000000000 --- a/sys/gnu/dts/arm64/renesas/r8a77965-ulcb-kf.dts +++ /dev/null @@ -1,16 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the M3NULCB Kingfisher board - * - * Copyright (C) 2018 Renesas Electronics Corp. - * Copyright (C) 2018 Cogent Embedded, Inc. - */ - -#include "r8a77965-ulcb.dts" -#include "ulcb-kf.dtsi" - -/ { - model = "Renesas M3NULCB Kingfisher board based on r8a77965"; - compatible = "shimafuji,kingfisher", "renesas,m3nulcb", - "renesas,r8a77965"; -}; diff --git a/sys/gnu/dts/arm64/renesas/r8a77965-ulcb.dts b/sys/gnu/dts/arm64/renesas/r8a77965-ulcb.dts deleted file mode 100644 index 964078b6cc4..00000000000 --- a/sys/gnu/dts/arm64/renesas/r8a77965-ulcb.dts +++ /dev/null @@ -1,33 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the M3NULCB (R-Car Starter Kit Pro) board - * - * Copyright (C) 2018 Renesas Electronics Corp. - * Copyright (C) 2018 Cogent Embedded, Inc. - */ - -/dts-v1/; -#include "r8a77965.dtsi" -#include "ulcb.dtsi" - -/ { - model = "Renesas M3NULCB board based on r8a77965"; - compatible = "renesas,m3nulcb", "renesas,r8a77965"; - - memory@48000000 { - device_type = "memory"; - /* first 128MB is reserved for secure area. */ - reg = <0x0 0x48000000 0x0 0x78000000>; - }; -}; - -&du { - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>, - <&cpg CPG_MOD 721>, - <&versaclock5 1>, - <&versaclock5 3>, - <&versaclock5 2>; - clock-names = "du.0", "du.1", "du.3", - "dclkin.0", "dclkin.1", "dclkin.3"; -}; diff --git a/sys/gnu/dts/arm64/renesas/r8a77965.dtsi b/sys/gnu/dts/arm64/renesas/r8a77965.dtsi deleted file mode 100644 index c17d90bd160..00000000000 --- a/sys/gnu/dts/arm64/renesas/r8a77965.dtsi +++ /dev/null @@ -1,2645 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the R-Car M3-N (R8A77965) SoC - * - * Copyright (C) 2018 Jacopo Mondi - * - * Based on r8a7796.dtsi - * Copyright (C) 2016 Renesas Electronics Corp. - */ - -#include -#include -#include - -#define CPG_AUDIO_CLK_I R8A77965_CLK_S0D4 - -/ { - compatible = "renesas,r8a77965"; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - i2c6 = &i2c6; - i2c7 = &i2c_dvfs; - }; - - /* - * The external audio clocks are configured as 0 Hz fixed frequency - * clocks by default. - * Boards that provide audio clocks should override them. - */ - audio_clk_a: audio_clk_a { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - audio_clk_b: audio_clk_b { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - audio_clk_c: audio_clk_c { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - /* External CAN clock - to be overridden by boards that provide it */ - can_clk: can { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - cluster0_opp: opp_table0 { - compatible = "operating-points-v2"; - opp-shared; - - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <830000>; - clock-latency-ns = <300000>; - }; - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <830000>; - clock-latency-ns = <300000>; - }; - opp-1500000000 { - opp-hz = /bits/ 64 <1500000000>; - opp-microvolt = <830000>; - clock-latency-ns = <300000>; - opp-suspend; - }; - opp-1600000000 { - opp-hz = /bits/ 64 <1600000000>; - opp-microvolt = <900000>; - clock-latency-ns = <300000>; - turbo-mode; - }; - opp-1700000000 { - opp-hz = /bits/ 64 <1700000000>; - opp-microvolt = <900000>; - clock-latency-ns = <300000>; - turbo-mode; - }; - opp-1800000000 { - opp-hz = /bits/ 64 <1800000000>; - opp-microvolt = <960000>; - clock-latency-ns = <300000>; - turbo-mode; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - a57_0: cpu@0 { - compatible = "arm,cortex-a57"; - reg = <0x0>; - device_type = "cpu"; - power-domains = <&sysc R8A77965_PD_CA57_CPU0>; - next-level-cache = <&L2_CA57>; - enable-method = "psci"; - #cooling-cells = <2>; - dynamic-power-coefficient = <854>; - clocks = <&cpg CPG_CORE R8A77965_CLK_Z>; - operating-points-v2 = <&cluster0_opp>; - }; - - a57_1: cpu@1 { - compatible = "arm,cortex-a57"; - reg = <0x1>; - device_type = "cpu"; - power-domains = <&sysc R8A77965_PD_CA57_CPU1>; - next-level-cache = <&L2_CA57>; - enable-method = "psci"; - clocks = <&cpg CPG_CORE R8A77965_CLK_Z>; - operating-points-v2 = <&cluster0_opp>; - }; - - L2_CA57: cache-controller-0 { - compatible = "cache"; - power-domains = <&sysc R8A77965_PD_CA57_SCU>; - cache-unified; - cache-level = <2>; - }; - }; - - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board */ - clock-frequency = <0>; - }; - - extalr_clk: extalr { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board */ - clock-frequency = <0>; - }; - - /* External PCIe clock - can be overridden by the board */ - pcie_bus_clk: pcie_bus { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - pmu_a57 { - compatible = "arm,cortex-a57-pmu"; - interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&a57_0>, - <&a57_1>; - }; - - psci { - compatible = "arm,psci-1.0", "arm,psci-0.2"; - method = "smc"; - }; - - /* External SCIF clock - to be overridden by boards that provide it */ - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - soc { - compatible = "simple-bus"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - rwdt: watchdog@e6020000 { - compatible = "renesas,r8a77965-wdt", - "renesas,rcar-gen3-wdt"; - reg = <0 0xe6020000 0 0x0c>; - clocks = <&cpg CPG_MOD 402>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 402>; - status = "disabled"; - }; - - gpio0: gpio@e6050000 { - compatible = "renesas,gpio-r8a77965", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6050000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 0 16>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 912>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 912>; - }; - - gpio1: gpio@e6051000 { - compatible = "renesas,gpio-r8a77965", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6051000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 32 29>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 911>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 911>; - }; - - gpio2: gpio@e6052000 { - compatible = "renesas,gpio-r8a77965", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6052000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 64 15>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 910>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 910>; - }; - - gpio3: gpio@e6053000 { - compatible = "renesas,gpio-r8a77965", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6053000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 96 16>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 909>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 909>; - }; - - gpio4: gpio@e6054000 { - compatible = "renesas,gpio-r8a77965", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6054000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 128 18>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 908>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 908>; - }; - - gpio5: gpio@e6055000 { - compatible = "renesas,gpio-r8a77965", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6055000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 160 26>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 907>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 907>; - }; - - gpio6: gpio@e6055400 { - compatible = "renesas,gpio-r8a77965", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6055400 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 192 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 906>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 906>; - }; - - gpio7: gpio@e6055800 { - compatible = "renesas,gpio-r8a77965", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6055800 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 224 4>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 905>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 905>; - }; - - pfc: pin-controller@e6060000 { - compatible = "renesas,pfc-r8a77965"; - reg = <0 0xe6060000 0 0x50c>; - }; - - cmt0: timer@e60f0000 { - compatible = "renesas,r8a77965-cmt0", - "renesas,rcar-gen3-cmt0"; - reg = <0 0xe60f0000 0 0x1004>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 303>; - clock-names = "fck"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 303>; - status = "disabled"; - }; - - cmt1: timer@e6130000 { - compatible = "renesas,r8a77965-cmt1", - "renesas,rcar-gen3-cmt1"; - reg = <0 0xe6130000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 302>; - clock-names = "fck"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 302>; - status = "disabled"; - }; - - cmt2: timer@e6140000 { - compatible = "renesas,r8a77965-cmt1", - "renesas,rcar-gen3-cmt1"; - reg = <0 0xe6140000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 301>; - clock-names = "fck"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 301>; - status = "disabled"; - }; - - cmt3: timer@e6148000 { - compatible = "renesas,r8a77965-cmt1", - "renesas,rcar-gen3-cmt1"; - reg = <0 0xe6148000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 300>; - clock-names = "fck"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 300>; - status = "disabled"; - }; - - cpg: clock-controller@e6150000 { - compatible = "renesas,r8a77965-cpg-mssr"; - reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk>, <&extalr_clk>; - clock-names = "extal", "extalr"; - #clock-cells = <2>; - #power-domain-cells = <0>; - #reset-cells = <1>; - }; - - rst: reset-controller@e6160000 { - compatible = "renesas,r8a77965-rst"; - reg = <0 0xe6160000 0 0x0200>; - }; - - sysc: system-controller@e6180000 { - compatible = "renesas,r8a77965-sysc"; - reg = <0 0xe6180000 0 0x0400>; - #power-domain-cells = <1>; - }; - - tsc: thermal@e6198000 { - compatible = "renesas,r8a77965-thermal"; - reg = <0 0xe6198000 0 0x100>, - <0 0xe61a0000 0 0x100>, - <0 0xe61a8000 0 0x100>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 522>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 522>; - #thermal-sensor-cells = <1>; - }; - - intc_ex: interrupt-controller@e61c0000 { - compatible = "renesas,intc-ex-r8a77965", "renesas,irqc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0 0xe61c0000 0 0x200>; - interrupts = , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 407>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 407>; - }; - - i2c0: i2c@e6500000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a77965", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6500000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 931>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 931>; - dmas = <&dmac1 0x91>, <&dmac1 0x90>, - <&dmac2 0x91>, <&dmac2 0x90>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c1: i2c@e6508000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a77965", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6508000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 930>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 930>; - dmas = <&dmac1 0x93>, <&dmac1 0x92>, - <&dmac2 0x93>, <&dmac2 0x92>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c2: i2c@e6510000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a77965", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6510000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 929>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 929>; - dmas = <&dmac1 0x95>, <&dmac1 0x94>, - <&dmac2 0x95>, <&dmac2 0x94>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c3: i2c@e66d0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a77965", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66d0000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 928>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 928>; - dmas = <&dmac0 0x97>, <&dmac0 0x96>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c4: i2c@e66d8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a77965", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66d8000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 927>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 927>; - dmas = <&dmac0 0x99>, <&dmac0 0x98>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c5: i2c@e66e0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a77965", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66e0000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 919>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 919>; - dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c6: i2c@e66e8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a77965", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66e8000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 918>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 918>; - dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c_dvfs: i2c@e60b0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a77965", - "renesas,rcar-gen3-iic", - "renesas,rmobile-iic"; - reg = <0 0xe60b0000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 926>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 926>; - dmas = <&dmac0 0x11>, <&dmac0 0x10>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - hscif0: serial@e6540000 { - compatible = "renesas,hscif-r8a77965", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6540000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 520>, - <&cpg CPG_CORE R8A77965_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x31>, <&dmac1 0x30>, - <&dmac2 0x31>, <&dmac2 0x30>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 520>; - status = "disabled"; - }; - - hscif1: serial@e6550000 { - compatible = "renesas,hscif-r8a77965", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6550000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 519>, - <&cpg CPG_CORE R8A77965_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x33>, <&dmac1 0x32>, - <&dmac2 0x33>, <&dmac2 0x32>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 519>; - status = "disabled"; - }; - - hscif2: serial@e6560000 { - compatible = "renesas,hscif-r8a77965", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6560000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 518>, - <&cpg CPG_CORE R8A77965_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x35>, <&dmac1 0x34>, - <&dmac2 0x35>, <&dmac2 0x34>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 518>; - status = "disabled"; - }; - - hscif3: serial@e66a0000 { - compatible = "renesas,hscif-r8a77965", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe66a0000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 517>, - <&cpg CPG_CORE R8A77965_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x37>, <&dmac0 0x36>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 517>; - status = "disabled"; - }; - - hscif4: serial@e66b0000 { - compatible = "renesas,hscif-r8a77965", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe66b0000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 516>, - <&cpg CPG_CORE R8A77965_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x39>, <&dmac0 0x38>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 516>; - status = "disabled"; - }; - - hsusb: usb@e6590000 { - compatible = "renesas,usbhs-r8a77965", - "renesas,rcar-gen3-usbhs"; - reg = <0 0xe6590000 0 0x200>; - interrupts = ; - clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>; - dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, - <&usb_dmac1 0>, <&usb_dmac1 1>; - dma-names = "ch0", "ch1", "ch2", "ch3"; - renesas,buswait = <11>; - phys = <&usb2_phy0 3>; - phy-names = "usb"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 704>, <&cpg 703>; - status = "disabled"; - }; - - usb_dmac0: dma-controller@e65a0000 { - compatible = "renesas,r8a77965-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65a0000 0 0x100>; - interrupts = , - ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 330>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 330>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - usb_dmac1: dma-controller@e65b0000 { - compatible = "renesas,r8a77965-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65b0000 0 0x100>; - interrupts = , - ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 331>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 331>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - usb3_phy0: usb-phy@e65ee000 { - compatible = "renesas,r8a77965-usb3-phy", - "renesas,rcar-gen3-usb3-phy"; - reg = <0 0xe65ee000 0 0x90>; - clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, - <&usb_extal_clk>; - clock-names = "usb3-if", "usb3s_clk", "usb_extal"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 328>; - #phy-cells = <0>; - status = "disabled"; - }; - - dmac0: dma-controller@e6700000 { - compatible = "renesas,dmac-r8a77965", - "renesas,rcar-dmac"; - reg = <0 0xe6700000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 219>; - clock-names = "fck"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 219>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, - <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, - <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, - <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, - <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, - <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, - <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, - <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; - }; - - dmac1: dma-controller@e7300000 { - compatible = "renesas,dmac-r8a77965", - "renesas,rcar-dmac"; - reg = <0 0xe7300000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 218>; - clock-names = "fck"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 218>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, - <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, - <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, - <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, - <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, - <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, - <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, - <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; - }; - - dmac2: dma-controller@e7310000 { - compatible = "renesas,dmac-r8a77965", - "renesas,rcar-dmac"; - reg = <0 0xe7310000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 217>; - clock-names = "fck"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 217>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, - <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, - <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, - <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, - <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, - <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, - <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, - <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; - }; - - ipmmu_ds0: mmu@e6740000 { - compatible = "renesas,ipmmu-r8a77965"; - reg = <0 0xe6740000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 0>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_ds1: mmu@e7740000 { - compatible = "renesas,ipmmu-r8a77965"; - reg = <0 0xe7740000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 1>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_hc: mmu@e6570000 { - compatible = "renesas,ipmmu-r8a77965"; - reg = <0 0xe6570000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 2>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_mm: mmu@e67b0000 { - compatible = "renesas,ipmmu-r8a77965"; - reg = <0 0xe67b0000 0 0x1000>; - interrupts = , - ; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_mp: mmu@ec670000 { - compatible = "renesas,ipmmu-r8a77965"; - reg = <0 0xec670000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 4>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_pv0: mmu@fd800000 { - compatible = "renesas,ipmmu-r8a77965"; - reg = <0 0xfd800000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 6>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_rt: mmu@ffc80000 { - compatible = "renesas,ipmmu-r8a77965"; - reg = <0 0xffc80000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 10>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_vc0: mmu@fe6b0000 { - compatible = "renesas,ipmmu-r8a77965"; - reg = <0 0xfe6b0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 12>; - power-domains = <&sysc R8A77965_PD_A3VC>; - #iommu-cells = <1>; - }; - - ipmmu_vi0: mmu@febd0000 { - compatible = "renesas,ipmmu-r8a77965"; - reg = <0 0xfebd0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 14>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_vp0: mmu@fe990000 { - compatible = "renesas,ipmmu-r8a77965"; - reg = <0 0xfe990000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 16>; - power-domains = <&sysc R8A77965_PD_A3VP>; - #iommu-cells = <1>; - }; - - avb: ethernet@e6800000 { - compatible = "renesas,etheravb-r8a77965", - "renesas,etheravb-rcar-gen3"; - reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15", - "ch16", "ch17", "ch18", "ch19", - "ch20", "ch21", "ch22", "ch23", - "ch24"; - clocks = <&cpg CPG_MOD 812>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 812>; - phy-mode = "rgmii"; - iommus = <&ipmmu_ds0 16>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - can0: can@e6c30000 { - compatible = "renesas,can-r8a77965", - "renesas,rcar-gen3-can"; - reg = <0 0xe6c30000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 916>, - <&cpg CPG_CORE R8A77965_CLK_CANFD>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A77965_CLK_CANFD>; - assigned-clock-rates = <40000000>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 916>; - status = "disabled"; - }; - - can1: can@e6c38000 { - compatible = "renesas,can-r8a77965", - "renesas,rcar-gen3-can"; - reg = <0 0xe6c38000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 915>, - <&cpg CPG_CORE R8A77965_CLK_CANFD>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A77965_CLK_CANFD>; - assigned-clock-rates = <40000000>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 915>; - status = "disabled"; - }; - - canfd: can@e66c0000 { - compatible = "renesas,r8a77965-canfd", - "renesas,rcar-gen3-canfd"; - reg = <0 0xe66c0000 0 0x8000>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 914>, - <&cpg CPG_CORE R8A77965_CLK_CANFD>, - <&can_clk>; - clock-names = "fck", "canfd", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A77965_CLK_CANFD>; - assigned-clock-rates = <40000000>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 914>; - status = "disabled"; - - channel0 { - status = "disabled"; - }; - - channel1 { - status = "disabled"; - }; - }; - - pwm0: pwm@e6e30000 { - compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar"; - reg = <0 0xe6e30000 0 8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pwm1: pwm@e6e31000 { - compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar"; - reg = <0 0xe6e31000 0 8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pwm2: pwm@e6e32000 { - compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar"; - reg = <0 0xe6e32000 0 8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pwm3: pwm@e6e33000 { - compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar"; - reg = <0 0xe6e33000 0 8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pwm4: pwm@e6e34000 { - compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar"; - reg = <0 0xe6e34000 0 8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pwm5: pwm@e6e35000 { - compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar"; - reg = <0 0xe6e35000 0 8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pwm6: pwm@e6e36000 { - compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar"; - reg = <0 0xe6e36000 0 8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - status = "disabled"; - }; - - scif0: serial@e6e60000 { - compatible = "renesas,scif-r8a77965", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e60000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 207>, - <&cpg CPG_CORE R8A77965_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x51>, <&dmac1 0x50>, - <&dmac2 0x51>, <&dmac2 0x50>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 207>; - status = "disabled"; - }; - - scif1: serial@e6e68000 { - compatible = "renesas,scif-r8a77965", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e68000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 206>, - <&cpg CPG_CORE R8A77965_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x53>, <&dmac1 0x52>, - <&dmac2 0x53>, <&dmac2 0x52>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 206>; - status = "disabled"; - }; - - scif2: serial@e6e88000 { - compatible = "renesas,scif-r8a77965", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e88000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 310>, - <&cpg CPG_CORE R8A77965_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x13>, <&dmac1 0x12>, - <&dmac2 0x13>, <&dmac2 0x12>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 310>; - status = "disabled"; - }; - - scif3: serial@e6c50000 { - compatible = "renesas,scif-r8a77965", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6c50000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 204>, - <&cpg CPG_CORE R8A77965_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x57>, <&dmac0 0x56>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 204>; - status = "disabled"; - }; - - scif4: serial@e6c40000 { - compatible = "renesas,scif-r8a77965", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6c40000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 203>, - <&cpg CPG_CORE R8A77965_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x59>, <&dmac0 0x58>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 203>; - status = "disabled"; - }; - - scif5: serial@e6f30000 { - compatible = "renesas,scif-r8a77965", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6f30000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 202>, - <&cpg CPG_CORE R8A77965_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, - <&dmac2 0x5b>, <&dmac2 0x5a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 202>; - status = "disabled"; - }; - - tpu: pwm@e6e80000 { - compatible = "renesas,tpu-r8a77965", "renesas,tpu"; - reg = <0 0xe6e80000 0 0x148>; - interrupts = ; - clocks = <&cpg CPG_MOD 304>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 304>; - #pwm-cells = <3>; - status = "disabled"; - }; - - msiof0: spi@e6e90000 { - compatible = "renesas,msiof-r8a77965", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6e90000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 211>; - dmas = <&dmac1 0x41>, <&dmac1 0x40>, - <&dmac2 0x41>, <&dmac2 0x40>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 211>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof1: spi@e6ea0000 { - compatible = "renesas,msiof-r8a77965", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6ea0000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 210>; - dmas = <&dmac1 0x43>, <&dmac1 0x42>, - <&dmac2 0x43>, <&dmac2 0x42>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 210>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof2: spi@e6c00000 { - compatible = "renesas,msiof-r8a77965", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6c00000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 209>; - dmas = <&dmac0 0x45>, <&dmac0 0x44>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 209>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof3: spi@e6c10000 { - compatible = "renesas,msiof-r8a77965", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6c10000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 208>; - dmas = <&dmac0 0x47>, <&dmac0 0x46>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 208>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - vin0: video@e6ef0000 { - compatible = "renesas,vin-r8a77965"; - reg = <0 0xe6ef0000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 811>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 811>; - renesas,id = <0>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin0csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin0>; - }; - vin0csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin0>; - }; - }; - }; - }; - - vin1: video@e6ef1000 { - compatible = "renesas,vin-r8a77965"; - reg = <0 0xe6ef1000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 810>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 810>; - renesas,id = <1>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin1csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin1>; - }; - vin1csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin1>; - }; - }; - }; - }; - - vin2: video@e6ef2000 { - compatible = "renesas,vin-r8a77965"; - reg = <0 0xe6ef2000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 809>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 809>; - renesas,id = <2>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin2csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin2>; - }; - vin2csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin2>; - }; - }; - }; - }; - - vin3: video@e6ef3000 { - compatible = "renesas,vin-r8a77965"; - reg = <0 0xe6ef3000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 808>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 808>; - renesas,id = <3>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin3csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin3>; - }; - vin3csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin3>; - }; - }; - }; - }; - - vin4: video@e6ef4000 { - compatible = "renesas,vin-r8a77965"; - reg = <0 0xe6ef4000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 807>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 807>; - renesas,id = <4>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin4csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin4>; - }; - vin4csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin4>; - }; - }; - }; - }; - - vin5: video@e6ef5000 { - compatible = "renesas,vin-r8a77965"; - reg = <0 0xe6ef5000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 806>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 806>; - renesas,id = <5>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin5csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin5>; - }; - vin5csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin5>; - }; - }; - }; - }; - - vin6: video@e6ef6000 { - compatible = "renesas,vin-r8a77965"; - reg = <0 0xe6ef6000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 805>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 805>; - renesas,id = <6>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin6csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin6>; - }; - vin6csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin6>; - }; - }; - }; - }; - - vin7: video@e6ef7000 { - compatible = "renesas,vin-r8a77965"; - reg = <0 0xe6ef7000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 804>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 804>; - renesas,id = <7>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin7csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin7>; - }; - vin7csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin7>; - }; - }; - }; - }; - - rcar_sound: sound@ec500000 { - /* - * #sound-dai-cells is required - * - * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; - * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; - */ - /* - * #clock-cells is required for audio_clkout0/1/2/3 - * - * clkout : #clock-cells = <0>; <&rcar_sound>; - * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; - */ - compatible = "renesas,rcar_sound-r8a77965", "renesas,rcar_sound-gen3"; - reg = <0 0xec500000 0 0x1000>, /* SCU */ - <0 0xec5a0000 0 0x100>, /* ADG */ - <0 0xec540000 0 0x1000>, /* SSIU */ - <0 0xec541000 0 0x280>, /* SSI */ - <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ - reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; - - clocks = <&cpg CPG_MOD 1005>, - <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, - <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, - <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, - <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, - <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, - <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, - <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, - <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, - <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, - <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, - <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, - <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, - <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, - <&audio_clk_a>, <&audio_clk_b>, - <&audio_clk_c>, - <&cpg CPG_CORE R8A77965_CLK_S0D4>; - clock-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", - "ssi.5", "ssi.4", "ssi.3", "ssi.2", - "ssi.1", "ssi.0", - "src.9", "src.8", "src.7", "src.6", - "src.5", "src.4", "src.3", "src.2", - "src.1", "src.0", - "mix.1", "mix.0", - "ctu.1", "ctu.0", - "dvc.0", "dvc.1", - "clk_a", "clk_b", "clk_c", "clk_i"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 1005>, - <&cpg 1006>, <&cpg 1007>, - <&cpg 1008>, <&cpg 1009>, - <&cpg 1010>, <&cpg 1011>, - <&cpg 1012>, <&cpg 1013>, - <&cpg 1014>, <&cpg 1015>; - reset-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", - "ssi.5", "ssi.4", "ssi.3", "ssi.2", - "ssi.1", "ssi.0"; - status = "disabled"; - - rcar_sound,dvc { - dvc0: dvc-0 { - dmas = <&audma1 0xbc>; - dma-names = "tx"; - }; - dvc1: dvc-1 { - dmas = <&audma1 0xbe>; - dma-names = "tx"; - }; - }; - - rcar_sound,mix { - mix0: mix-0 { }; - mix1: mix-1 { }; - }; - - rcar_sound,ctu { - ctu00: ctu-0 { }; - ctu01: ctu-1 { }; - ctu02: ctu-2 { }; - ctu03: ctu-3 { }; - ctu10: ctu-4 { }; - ctu11: ctu-5 { }; - ctu12: ctu-6 { }; - ctu13: ctu-7 { }; - }; - - rcar_sound,src { - src0: src-0 { - interrupts = ; - dmas = <&audma0 0x85>, <&audma1 0x9a>; - dma-names = "rx", "tx"; - }; - src1: src-1 { - interrupts = ; - dmas = <&audma0 0x87>, <&audma1 0x9c>; - dma-names = "rx", "tx"; - }; - src2: src-2 { - interrupts = ; - dmas = <&audma0 0x89>, <&audma1 0x9e>; - dma-names = "rx", "tx"; - }; - src3: src-3 { - interrupts = ; - dmas = <&audma0 0x8b>, <&audma1 0xa0>; - dma-names = "rx", "tx"; - }; - src4: src-4 { - interrupts = ; - dmas = <&audma0 0x8d>, <&audma1 0xb0>; - dma-names = "rx", "tx"; - }; - src5: src-5 { - interrupts = ; - dmas = <&audma0 0x8f>, <&audma1 0xb2>; - dma-names = "rx", "tx"; - }; - src6: src-6 { - interrupts = ; - dmas = <&audma0 0x91>, <&audma1 0xb4>; - dma-names = "rx", "tx"; - }; - src7: src-7 { - interrupts = ; - dmas = <&audma0 0x93>, <&audma1 0xb6>; - dma-names = "rx", "tx"; - }; - src8: src-8 { - interrupts = ; - dmas = <&audma0 0x95>, <&audma1 0xb8>; - dma-names = "rx", "tx"; - }; - src9: src-9 { - interrupts = ; - dmas = <&audma0 0x97>, <&audma1 0xba>; - dma-names = "rx", "tx"; - }; - }; - - rcar_sound,ssiu { - ssiu00: ssiu-0 { - dmas = <&audma0 0x15>, <&audma1 0x16>; - dma-names = "rx", "tx"; - }; - ssiu01: ssiu-1 { - dmas = <&audma0 0x35>, <&audma1 0x36>; - dma-names = "rx", "tx"; - }; - ssiu02: ssiu-2 { - dmas = <&audma0 0x37>, <&audma1 0x38>; - dma-names = "rx", "tx"; - }; - ssiu03: ssiu-3 { - dmas = <&audma0 0x47>, <&audma1 0x48>; - dma-names = "rx", "tx"; - }; - ssiu04: ssiu-4 { - dmas = <&audma0 0x3F>, <&audma1 0x40>; - dma-names = "rx", "tx"; - }; - ssiu05: ssiu-5 { - dmas = <&audma0 0x43>, <&audma1 0x44>; - dma-names = "rx", "tx"; - }; - ssiu06: ssiu-6 { - dmas = <&audma0 0x4F>, <&audma1 0x50>; - dma-names = "rx", "tx"; - }; - ssiu07: ssiu-7 { - dmas = <&audma0 0x53>, <&audma1 0x54>; - dma-names = "rx", "tx"; - }; - ssiu10: ssiu-8 { - dmas = <&audma0 0x49>, <&audma1 0x4a>; - dma-names = "rx", "tx"; - }; - ssiu11: ssiu-9 { - dmas = <&audma0 0x4B>, <&audma1 0x4C>; - dma-names = "rx", "tx"; - }; - ssiu12: ssiu-10 { - dmas = <&audma0 0x57>, <&audma1 0x58>; - dma-names = "rx", "tx"; - }; - ssiu13: ssiu-11 { - dmas = <&audma0 0x59>, <&audma1 0x5A>; - dma-names = "rx", "tx"; - }; - ssiu14: ssiu-12 { - dmas = <&audma0 0x5F>, <&audma1 0x60>; - dma-names = "rx", "tx"; - }; - ssiu15: ssiu-13 { - dmas = <&audma0 0xC3>, <&audma1 0xC4>; - dma-names = "rx", "tx"; - }; - ssiu16: ssiu-14 { - dmas = <&audma0 0xC7>, <&audma1 0xC8>; - dma-names = "rx", "tx"; - }; - ssiu17: ssiu-15 { - dmas = <&audma0 0xCB>, <&audma1 0xCC>; - dma-names = "rx", "tx"; - }; - ssiu20: ssiu-16 { - dmas = <&audma0 0x63>, <&audma1 0x64>; - dma-names = "rx", "tx"; - }; - ssiu21: ssiu-17 { - dmas = <&audma0 0x67>, <&audma1 0x68>; - dma-names = "rx", "tx"; - }; - ssiu22: ssiu-18 { - dmas = <&audma0 0x6B>, <&audma1 0x6C>; - dma-names = "rx", "tx"; - }; - ssiu23: ssiu-19 { - dmas = <&audma0 0x6D>, <&audma1 0x6E>; - dma-names = "rx", "tx"; - }; - ssiu24: ssiu-20 { - dmas = <&audma0 0xCF>, <&audma1 0xCE>; - dma-names = "rx", "tx"; - }; - ssiu25: ssiu-21 { - dmas = <&audma0 0xEB>, <&audma1 0xEC>; - dma-names = "rx", "tx"; - }; - ssiu26: ssiu-22 { - dmas = <&audma0 0xED>, <&audma1 0xEE>; - dma-names = "rx", "tx"; - }; - ssiu27: ssiu-23 { - dmas = <&audma0 0xEF>, <&audma1 0xF0>; - dma-names = "rx", "tx"; - }; - ssiu30: ssiu-24 { - dmas = <&audma0 0x6f>, <&audma1 0x70>; - dma-names = "rx", "tx"; - }; - ssiu31: ssiu-25 { - dmas = <&audma0 0x21>, <&audma1 0x22>; - dma-names = "rx", "tx"; - }; - ssiu32: ssiu-26 { - dmas = <&audma0 0x23>, <&audma1 0x24>; - dma-names = "rx", "tx"; - }; - ssiu33: ssiu-27 { - dmas = <&audma0 0x25>, <&audma1 0x26>; - dma-names = "rx", "tx"; - }; - ssiu34: ssiu-28 { - dmas = <&audma0 0x27>, <&audma1 0x28>; - dma-names = "rx", "tx"; - }; - ssiu35: ssiu-29 { - dmas = <&audma0 0x29>, <&audma1 0x2A>; - dma-names = "rx", "tx"; - }; - ssiu36: ssiu-30 { - dmas = <&audma0 0x2B>, <&audma1 0x2C>; - dma-names = "rx", "tx"; - }; - ssiu37: ssiu-31 { - dmas = <&audma0 0x2D>, <&audma1 0x2E>; - dma-names = "rx", "tx"; - }; - ssiu40: ssiu-32 { - dmas = <&audma0 0x71>, <&audma1 0x72>; - dma-names = "rx", "tx"; - }; - ssiu41: ssiu-33 { - dmas = <&audma0 0x17>, <&audma1 0x18>; - dma-names = "rx", "tx"; - }; - ssiu42: ssiu-34 { - dmas = <&audma0 0x19>, <&audma1 0x1A>; - dma-names = "rx", "tx"; - }; - ssiu43: ssiu-35 { - dmas = <&audma0 0x1B>, <&audma1 0x1C>; - dma-names = "rx", "tx"; - }; - ssiu44: ssiu-36 { - dmas = <&audma0 0x1D>, <&audma1 0x1E>; - dma-names = "rx", "tx"; - }; - ssiu45: ssiu-37 { - dmas = <&audma0 0x1F>, <&audma1 0x20>; - dma-names = "rx", "tx"; - }; - ssiu46: ssiu-38 { - dmas = <&audma0 0x31>, <&audma1 0x32>; - dma-names = "rx", "tx"; - }; - ssiu47: ssiu-39 { - dmas = <&audma0 0x33>, <&audma1 0x34>; - dma-names = "rx", "tx"; - }; - ssiu50: ssiu-40 { - dmas = <&audma0 0x73>, <&audma1 0x74>; - dma-names = "rx", "tx"; - }; - ssiu60: ssiu-41 { - dmas = <&audma0 0x75>, <&audma1 0x76>; - dma-names = "rx", "tx"; - }; - ssiu70: ssiu-42 { - dmas = <&audma0 0x79>, <&audma1 0x7a>; - dma-names = "rx", "tx"; - }; - ssiu80: ssiu-43 { - dmas = <&audma0 0x7b>, <&audma1 0x7c>; - dma-names = "rx", "tx"; - }; - ssiu90: ssiu-44 { - dmas = <&audma0 0x7d>, <&audma1 0x7e>; - dma-names = "rx", "tx"; - }; - ssiu91: ssiu-45 { - dmas = <&audma0 0x7F>, <&audma1 0x80>; - dma-names = "rx", "tx"; - }; - ssiu92: ssiu-46 { - dmas = <&audma0 0x81>, <&audma1 0x82>; - dma-names = "rx", "tx"; - }; - ssiu93: ssiu-47 { - dmas = <&audma0 0x83>, <&audma1 0x84>; - dma-names = "rx", "tx"; - }; - ssiu94: ssiu-48 { - dmas = <&audma0 0xA3>, <&audma1 0xA4>; - dma-names = "rx", "tx"; - }; - ssiu95: ssiu-49 { - dmas = <&audma0 0xA5>, <&audma1 0xA6>; - dma-names = "rx", "tx"; - }; - ssiu96: ssiu-50 { - dmas = <&audma0 0xA7>, <&audma1 0xA8>; - dma-names = "rx", "tx"; - }; - ssiu97: ssiu-51 { - dmas = <&audma0 0xA9>, <&audma1 0xAA>; - dma-names = "rx", "tx"; - }; - }; - - rcar_sound,ssi { - ssi0: ssi-0 { - interrupts = ; - dmas = <&audma0 0x01>, <&audma1 0x02>; - dma-names = "rx", "tx"; - }; - ssi1: ssi-1 { - interrupts = ; - dmas = <&audma0 0x03>, <&audma1 0x04>; - dma-names = "rx", "tx"; - }; - ssi2: ssi-2 { - interrupts = ; - dmas = <&audma0 0x05>, <&audma1 0x06>; - dma-names = "rx", "tx"; - }; - ssi3: ssi-3 { - interrupts = ; - dmas = <&audma0 0x07>, <&audma1 0x08>; - dma-names = "rx", "tx"; - }; - ssi4: ssi-4 { - interrupts = ; - dmas = <&audma0 0x09>, <&audma1 0x0a>; - dma-names = "rx", "tx"; - }; - ssi5: ssi-5 { - interrupts = ; - dmas = <&audma0 0x0b>, <&audma1 0x0c>; - dma-names = "rx", "tx"; - }; - ssi6: ssi-6 { - interrupts = ; - dmas = <&audma0 0x0d>, <&audma1 0x0e>; - dma-names = "rx", "tx"; - }; - ssi7: ssi-7 { - interrupts = ; - dmas = <&audma0 0x0f>, <&audma1 0x10>; - dma-names = "rx", "tx"; - }; - ssi8: ssi-8 { - interrupts = ; - dmas = <&audma0 0x11>, <&audma1 0x12>; - dma-names = "rx", "tx"; - }; - ssi9: ssi-9 { - interrupts = ; - dmas = <&audma0 0x13>, <&audma1 0x14>; - dma-names = "rx", "tx"; - }; - }; - }; - - audma0: dma-controller@ec700000 { - compatible = "renesas,dmac-r8a77965", - "renesas,rcar-dmac"; - reg = <0 0xec700000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 502>; - clock-names = "fck"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 502>; - #dma-cells = <1>; - dma-channels = <16>; - }; - - audma1: dma-controller@ec720000 { - compatible = "renesas,dmac-r8a77965", - "renesas,rcar-dmac"; - reg = <0 0xec720000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 501>; - clock-names = "fck"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 501>; - #dma-cells = <1>; - dma-channels = <16>; - }; - - xhci0: usb@ee000000 { - compatible = "renesas,xhci-r8a77965", - "renesas,rcar-gen3-xhci"; - reg = <0 0xee000000 0 0xc00>; - interrupts = ; - clocks = <&cpg CPG_MOD 328>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 328>; - status = "disabled"; - }; - - usb3_peri0: usb@ee020000 { - compatible = "renesas,r8a77965-usb3-peri", - "renesas,rcar-gen3-usb3-peri"; - reg = <0 0xee020000 0 0x400>; - interrupts = ; - clocks = <&cpg CPG_MOD 328>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 328>; - status = "disabled"; - }; - - ohci0: usb@ee080000 { - compatible = "generic-ohci"; - reg = <0 0xee080000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; - phys = <&usb2_phy0 1>; - phy-names = "usb"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 703>, <&cpg 704>; - status = "disabled"; - }; - - ohci1: usb@ee0a0000 { - compatible = "generic-ohci"; - reg = <0 0xee0a0000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 702>; - phys = <&usb2_phy1 1>; - phy-names = "usb"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 702>; - status = "disabled"; - }; - - ehci0: usb@ee080100 { - compatible = "generic-ehci"; - reg = <0 0xee080100 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; - phys = <&usb2_phy0 2>; - phy-names = "usb"; - companion = <&ohci0>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 703>, <&cpg 704>; - status = "disabled"; - }; - - ehci1: usb@ee0a0100 { - compatible = "generic-ehci"; - reg = <0 0xee0a0100 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 702>; - phys = <&usb2_phy1 2>; - phy-names = "usb"; - companion = <&ohci1>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 702>; - status = "disabled"; - }; - - usb2_phy0: usb-phy@ee080200 { - compatible = "renesas,usb2-phy-r8a77965", - "renesas,rcar-gen3-usb2-phy"; - reg = <0 0xee080200 0 0x700>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 703>, <&cpg 704>; - #phy-cells = <1>; - status = "disabled"; - }; - - usb2_phy1: usb-phy@ee0a0200 { - compatible = "renesas,usb2-phy-r8a77965", - "renesas,rcar-gen3-usb2-phy"; - reg = <0 0xee0a0200 0 0x700>; - clocks = <&cpg CPG_MOD 702>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 702>; - #phy-cells = <1>; - status = "disabled"; - }; - - sdhi0: sd@ee100000 { - compatible = "renesas,sdhi-r8a77965", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee100000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 314>; - max-frequency = <200000000>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 314>; - iommus = <&ipmmu_ds1 32>; - status = "disabled"; - }; - - sdhi1: sd@ee120000 { - compatible = "renesas,sdhi-r8a77965", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee120000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 313>; - max-frequency = <200000000>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 313>; - iommus = <&ipmmu_ds1 33>; - status = "disabled"; - }; - - sdhi2: sd@ee140000 { - compatible = "renesas,sdhi-r8a77965", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee140000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 312>; - max-frequency = <200000000>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 312>; - iommus = <&ipmmu_ds1 34>; - status = "disabled"; - }; - - sdhi3: sd@ee160000 { - compatible = "renesas,sdhi-r8a77965", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee160000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 311>; - max-frequency = <200000000>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 311>; - iommus = <&ipmmu_ds1 35>; - status = "disabled"; - }; - - sata: sata@ee300000 { - compatible = "renesas,sata-r8a77965", - "renesas,rcar-gen3-sata"; - reg = <0 0xee300000 0 0x200000>; - interrupts = ; - clocks = <&cpg CPG_MOD 815>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 815>; - status = "disabled"; - }; - - gic: interrupt-controller@f1010000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x0 0xf1010000 0 0x1000>, - <0x0 0xf1020000 0 0x20000>, - <0x0 0xf1040000 0 0x20000>, - <0x0 0xf1060000 0 0x20000>; - interrupts = ; - clocks = <&cpg CPG_MOD 408>; - clock-names = "clk"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 408>; - }; - - pciec0: pcie@fe000000 { - compatible = "renesas,pcie-r8a77965", - "renesas,pcie-rcar-gen3"; - reg = <0 0xfe000000 0 0x80000>; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x00 0xff>; - device_type = "pci"; - ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, - <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, - <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, - <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; - interrupts = , - , - ; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; - clock-names = "pcie", "pcie_bus"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 319>; - status = "disabled"; - }; - - pciec1: pcie@ee800000 { - compatible = "renesas,pcie-r8a77965", - "renesas,pcie-rcar-gen3"; - reg = <0 0xee800000 0 0x80000>; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x00 0xff>; - device_type = "pci"; - ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>, - <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>, - <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>, - <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; - interrupts = , - , - ; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>; - clock-names = "pcie", "pcie_bus"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 318>; - status = "disabled"; - }; - - fdp1@fe940000 { - compatible = "renesas,fdp1"; - reg = <0 0xfe940000 0 0x2400>; - interrupts = ; - clocks = <&cpg CPG_MOD 119>; - power-domains = <&sysc R8A77965_PD_A3VP>; - resets = <&cpg 119>; - renesas,fcp = <&fcpf0>; - }; - - fcpf0: fcp@fe950000 { - compatible = "renesas,fcpf"; - reg = <0 0xfe950000 0 0x200>; - clocks = <&cpg CPG_MOD 615>; - power-domains = <&sysc R8A77965_PD_A3VP>; - resets = <&cpg 615>; - }; - - vspb: vsp@fe960000 { - compatible = "renesas,vsp2"; - reg = <0 0xfe960000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 626>; - power-domains = <&sysc R8A77965_PD_A3VP>; - resets = <&cpg 626>; - - renesas,fcp = <&fcpvb0>; - }; - - vspi0: vsp@fe9a0000 { - compatible = "renesas,vsp2"; - reg = <0 0xfe9a0000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 631>; - power-domains = <&sysc R8A77965_PD_A3VP>; - resets = <&cpg 631>; - - renesas,fcp = <&fcpvi0>; - }; - - vspd0: vsp@fea20000 { - compatible = "renesas,vsp2"; - reg = <0 0xfea20000 0 0x5000>; - interrupts = ; - clocks = <&cpg CPG_MOD 623>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 623>; - - renesas,fcp = <&fcpvd0>; - }; - - vspd1: vsp@fea28000 { - compatible = "renesas,vsp2"; - reg = <0 0xfea28000 0 0x5000>; - interrupts = ; - clocks = <&cpg CPG_MOD 622>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 622>; - - renesas,fcp = <&fcpvd1>; - }; - - fcpvb0: fcp@fe96f000 { - compatible = "renesas,fcpv"; - reg = <0 0xfe96f000 0 0x200>; - clocks = <&cpg CPG_MOD 607>; - power-domains = <&sysc R8A77965_PD_A3VP>; - resets = <&cpg 607>; - }; - - fcpvd0: fcp@fea27000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea27000 0 0x200>; - clocks = <&cpg CPG_MOD 603>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 603>; - }; - - fcpvd1: fcp@fea2f000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea2f000 0 0x200>; - clocks = <&cpg CPG_MOD 602>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 602>; - }; - - fcpvi0: fcp@fe9af000 { - compatible = "renesas,fcpv"; - reg = <0 0xfe9af000 0 0x200>; - clocks = <&cpg CPG_MOD 611>; - power-domains = <&sysc R8A77965_PD_A3VP>; - resets = <&cpg 611>; - }; - - cmm0: cmm@fea40000 { - compatible = "renesas,r8a77965-cmm", - "renesas,rcar-gen3-cmm"; - reg = <0 0xfea40000 0 0x1000>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - clocks = <&cpg CPG_MOD 711>; - resets = <&cpg 711>; - }; - - cmm1: cmm@fea50000 { - compatible = "renesas,r8a77965-cmm", - "renesas,rcar-gen3-cmm"; - reg = <0 0xfea50000 0 0x1000>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - clocks = <&cpg CPG_MOD 710>; - resets = <&cpg 710>; - }; - - cmm3: cmm@fea70000 { - compatible = "renesas,r8a77965-cmm", - "renesas,rcar-gen3-cmm"; - reg = <0 0xfea70000 0 0x1000>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - clocks = <&cpg CPG_MOD 708>; - resets = <&cpg 708>; - }; - - csi20: csi2@fea80000 { - compatible = "renesas,r8a77965-csi2"; - reg = <0 0xfea80000 0 0x10000>; - interrupts = ; - clocks = <&cpg CPG_MOD 714>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 714>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - csi20vin0: endpoint@0 { - reg = <0>; - remote-endpoint = <&vin0csi20>; - }; - csi20vin1: endpoint@1 { - reg = <1>; - remote-endpoint = <&vin1csi20>; - }; - csi20vin2: endpoint@2 { - reg = <2>; - remote-endpoint = <&vin2csi20>; - }; - csi20vin3: endpoint@3 { - reg = <3>; - remote-endpoint = <&vin3csi20>; - }; - csi20vin4: endpoint@4 { - reg = <4>; - remote-endpoint = <&vin4csi20>; - }; - csi20vin5: endpoint@5 { - reg = <5>; - remote-endpoint = <&vin5csi20>; - }; - csi20vin6: endpoint@6 { - reg = <6>; - remote-endpoint = <&vin6csi20>; - }; - csi20vin7: endpoint@7 { - reg = <7>; - remote-endpoint = <&vin7csi20>; - }; - }; - }; - }; - - csi40: csi2@feaa0000 { - compatible = "renesas,r8a77965-csi2"; - reg = <0 0xfeaa0000 0 0x10000>; - interrupts = ; - clocks = <&cpg CPG_MOD 716>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 716>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - csi40vin0: endpoint@0 { - reg = <0>; - remote-endpoint = <&vin0csi40>; - }; - csi40vin1: endpoint@1 { - reg = <1>; - remote-endpoint = <&vin1csi40>; - }; - csi40vin2: endpoint@2 { - reg = <2>; - remote-endpoint = <&vin2csi40>; - }; - csi40vin3: endpoint@3 { - reg = <3>; - remote-endpoint = <&vin3csi40>; - }; - csi40vin4: endpoint@4 { - reg = <4>; - remote-endpoint = <&vin4csi40>; - }; - csi40vin5: endpoint@5 { - reg = <5>; - remote-endpoint = <&vin5csi40>; - }; - csi40vin6: endpoint@6 { - reg = <6>; - remote-endpoint = <&vin6csi40>; - }; - csi40vin7: endpoint@7 { - reg = <7>; - remote-endpoint = <&vin7csi40>; - }; - }; - }; - }; - - hdmi0: hdmi@fead0000 { - compatible = "renesas,r8a77965-hdmi", - "renesas,rcar-gen3-hdmi"; - reg = <0 0xfead0000 0 0x10000>; - interrupts = ; - clocks = <&cpg CPG_MOD 729>, - <&cpg CPG_CORE R8A77965_CLK_HDMI>; - clock-names = "iahb", "isfr"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 729>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - dw_hdmi0_in: endpoint { - remote-endpoint = <&du_out_hdmi0>; - }; - }; - port@1 { - reg = <1>; - }; - }; - }; - - du: display@feb00000 { - compatible = "renesas,du-r8a77965"; - reg = <0 0xfeb00000 0 0x80000>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>, - <&cpg CPG_MOD 721>; - clock-names = "du.0", "du.1", "du.3"; - - renesas,cmms = <&cmm0>, <&cmm1>, <&cmm3>; - vsps = <&vspd0 0>, <&vspd1 0>, <&vspd0 1>; - - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - du_out_rgb: endpoint { - }; - }; - port@1 { - reg = <1>; - du_out_hdmi0: endpoint { - remote-endpoint = <&dw_hdmi0_in>; - }; - }; - port@2 { - reg = <2>; - du_out_lvds0: endpoint { - remote-endpoint = <&lvds0_in>; - }; - }; - }; - }; - - lvds0: lvds@feb90000 { - compatible = "renesas,r8a77965-lvds"; - reg = <0 0xfeb90000 0 0x14>; - clocks = <&cpg CPG_MOD 727>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 727>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - lvds0_in: endpoint { - remote-endpoint = <&du_out_lvds0>; - }; - }; - port@1 { - reg = <1>; - lvds0_out: endpoint { - }; - }; - }; - }; - - prr: chipid@fff00044 { - compatible = "renesas,prr"; - reg = <0 0xfff00044 0 4>; - }; - }; - - thermal-zones { - sensor_thermal1: sensor-thermal1 { - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&tsc 0>; - sustainable-power = <2439>; - - trips { - sensor1_crit: sensor1-crit { - temperature = <120000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - sensor_thermal2: sensor-thermal2 { - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&tsc 1>; - sustainable-power = <2439>; - - trips { - sensor2_crit: sensor2-crit { - temperature = <120000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - sensor_thermal3: sensor-thermal3 { - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&tsc 2>; - sustainable-power = <2439>; - - trips { - target: trip-point1 { - /* miliCelsius */ - temperature = <100000>; - hysteresis = <1000>; - type = "passive"; - }; - - sensor3_crit: sensor3-crit { - temperature = <120000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&target>; - cooling-device = <&a57_0 2 4>; - contribution = <1024>; - }; - }; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; - }; - - /* External USB clocks - can be overridden by the board */ - usb3s0_clk: usb3s0 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - usb_extal_clk: usb_extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; -}; diff --git a/sys/gnu/dts/arm64/renesas/r8a77970-eagle.dts b/sys/gnu/dts/arm64/renesas/r8a77970-eagle.dts deleted file mode 100644 index 2afb91ec9c8..00000000000 --- a/sys/gnu/dts/arm64/renesas/r8a77970-eagle.dts +++ /dev/null @@ -1,208 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the Eagle board - * - * Copyright (C) 2016-2017 Renesas Electronics Corp. - * Copyright (C) 2017 Cogent Embedded, Inc. - */ - -/dts-v1/; -#include "r8a77970.dtsi" - -/ { - model = "Renesas Eagle board based on r8a77970"; - compatible = "renesas,eagle", "renesas,r8a77970"; - - aliases { - serial0 = &scif0; - ethernet0 = &avb; - }; - - chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; - stdout-path = "serial0:115200n8"; - }; - - d3p3: regulator-fixed { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - hdmi-out { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_out: endpoint { - remote-endpoint = <&adv7511_out>; - }; - }; - }; - - lvds-decoder { - compatible = "thine,thc63lvd1024"; - - vcc-supply = <&d3p3>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - thc63lvd1024_in: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - - port@2 { - reg = <2>; - thc63lvd1024_out: endpoint { - remote-endpoint = <&adv7511_in>; - }; - }; - }; - }; - - memory@48000000 { - device_type = "memory"; - /* first 128MB is reserved for secure area. */ - reg = <0x0 0x48000000 0x0 0x38000000>; - }; -}; - -&avb { - pinctrl-0 = <&avb_pins>; - pinctrl-names = "default"; - - renesas,no-ether-link; - phy-handle = <&phy0>; - phy-mode = "rgmii-id"; - status = "okay"; - - phy0: ethernet-phy@0 { - rxc-skew-ps = <1500>; - reg = <0>; - interrupt-parent = <&gpio1>; - interrupts = <17 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&canfd { - pinctrl-0 = <&canfd0_pins>; - pinctrl-names = "default"; - status = "okay"; - - channel0 { - status = "okay"; - }; -}; - -&du { - status = "okay"; -}; - -&extal_clk { - clock-frequency = <16666666>; -}; - -&extalr_clk { - clock-frequency = <32768>; -}; - -&i2c0 { - pinctrl-0 = <&i2c0_pins>; - pinctrl-names = "default"; - - status = "okay"; - clock-frequency = <400000>; - - io_expander: gpio@20 { - compatible = "onnn,pca9654"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - }; - - hdmi@39 { - compatible = "adi,adv7511w"; - reg = <0x39>; - interrupt-parent = <&gpio1>; - interrupts = <20 IRQ_TYPE_LEVEL_LOW>; - - adi,input-depth = <8>; - adi,input-colorspace = "rgb"; - adi,input-clock = "1x"; - adi,input-style = <1>; - adi,input-justification = "evenly"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7511_in: endpoint { - remote-endpoint = <&thc63lvd1024_out>; - }; - }; - - port@1 { - reg = <1>; - adv7511_out: endpoint { - remote-endpoint = <&hdmi_con_out>; - }; - }; - }; - }; -}; - -&lvds0 { - status = "okay"; - - ports { - port@1 { - lvds0_out: endpoint { - remote-endpoint = <&thc63lvd1024_in>; - }; - }; - }; -}; - -&pfc { - avb_pins: avb0 { - groups = "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk"; - function = "avb0"; - }; - - canfd0_pins: canfd0 { - groups = "canfd0_data_a"; - function = "canfd0"; - }; - - i2c0_pins: i2c0 { - groups = "i2c0"; - function = "i2c0"; - }; - - scif0_pins: scif0 { - groups = "scif0_data"; - function = "scif0"; - }; -}; - -&rwdt { - timeout-sec = <60>; - status = "okay"; -}; - -&scif0 { - pinctrl-0 = <&scif0_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/renesas/r8a77970-v3msk.dts b/sys/gnu/dts/arm64/renesas/r8a77970-v3msk.dts deleted file mode 100644 index d7c7b9156e0..00000000000 --- a/sys/gnu/dts/arm64/renesas/r8a77970-v3msk.dts +++ /dev/null @@ -1,228 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the V3M Starter Kit board - * - * Copyright (C) 2017 Renesas Electronics Corp. - * Copyright (C) 2017 Cogent Embedded, Inc. - */ - -/dts-v1/; -#include "r8a77970.dtsi" - -/ { - model = "Renesas V3M Starter Kit board"; - compatible = "renesas,v3msk", "renesas,r8a77970"; - - aliases { - serial0 = &scif0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - hdmi-out { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con: endpoint { - remote-endpoint = <&adv7511_out>; - }; - }; - }; - - lvds-decoder { - compatible = "thine,thc63lvd1024"; - vcc-supply = <&vcc_d3_3v>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - thc63lvd1024_in: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - - port@2 { - reg = <2>; - thc63lvd1024_out: endpoint { - remote-endpoint = <&adv7511_in>; - }; - }; - }; - }; - - memory@48000000 { - device_type = "memory"; - /* first 128MB is reserved for secure area. */ - reg = <0x0 0x48000000 0x0 0x38000000>; - }; - - osc5_clk: osc5-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <148500000>; - }; - - vcc_d1_8v: regulator-0 { - compatible = "regulator-fixed"; - regulator-name = "VCC_D1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - vcc_d3_3v: regulator-1 { - compatible = "regulator-fixed"; - regulator-name = "VCC_D3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - vcc_vddq_vin0: regulator-2 { - compatible = "regulator-fixed"; - regulator-name = "VCC_VDDQ_VIN0"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; -}; - -&avb { - pinctrl-0 = <&avb_pins>; - pinctrl-names = "default"; - - renesas,no-ether-link; - phy-handle = <&phy0>; - phy-mode = "rgmii-id"; - status = "okay"; - - phy0: ethernet-phy@0 { - rxc-skew-ps = <1500>; - reg = <0>; - interrupt-parent = <&gpio1>; - interrupts = <17 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&du { - clocks = <&cpg CPG_MOD 724>, - <&osc5_clk>; - clock-names = "du.0", "dclkin.0"; - status = "okay"; -}; - -&extal_clk { - clock-frequency = <16666666>; -}; - -&extalr_clk { - clock-frequency = <32768>; -}; - -&i2c0 { - pinctrl-0 = <&i2c0_pins>; - pinctrl-names = "default"; - - status = "okay"; - clock-frequency = <400000>; - - hdmi@39{ - compatible = "adi,adv7511w"; - #sound-dai-cells = <0>; - reg = <0x39>; - interrupt-parent = <&gpio1>; - interrupts = <20 IRQ_TYPE_LEVEL_LOW>; - avdd-supply = <&vcc_d1_8v>; - dvdd-supply = <&vcc_d1_8v>; - pvdd-supply = <&vcc_d1_8v>; - bgvdd-supply = <&vcc_d1_8v>; - dvdd-3v-supply = <&vcc_d3_3v>; - - adi,input-depth = <8>; - adi,input-colorspace = "rgb"; - adi,input-clock = "1x"; - adi,input-style = <1>; - adi,input-justification = "evenly"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7511_in: endpoint { - remote-endpoint = <&thc63lvd1024_out>; - }; - }; - - port@1 { - reg = <1>; - adv7511_out: endpoint { - remote-endpoint = <&hdmi_con>; - }; - }; - }; - }; -}; - -&lvds0 { - status = "okay"; - - ports { - port@1 { - lvds0_out: endpoint { - remote-endpoint = <&thc63lvd1024_in>; - }; - }; - }; -}; - -&mmc0 { - pinctrl-0 = <&mmc_pins>; - pinctrl-names = "default"; - - vmmc-supply = <&vcc_d3_3v>; - vqmmc-supply = <&vcc_vddq_vin0>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&pfc { - avb_pins: avb0 { - groups = "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk"; - function = "avb0"; - }; - - i2c0_pins: i2c0 { - groups = "i2c0"; - function = "i2c0"; - }; - - mmc_pins: mmc_3_3v { - groups = "mmc_data8", "mmc_ctrl"; - function = "mmc"; - power-source = <3300>; - }; - - scif0_pins: scif0 { - groups = "scif0_data"; - function = "scif0"; - }; -}; - -&scif0 { - pinctrl-0 = <&scif0_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/renesas/r8a77970.dtsi b/sys/gnu/dts/arm64/renesas/r8a77970.dtsi deleted file mode 100644 index 664a73a2cc6..00000000000 --- a/sys/gnu/dts/arm64/renesas/r8a77970.dtsi +++ /dev/null @@ -1,1205 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the R-Car V3M (R8A77970) SoC - * - * Copyright (C) 2016-2017 Renesas Electronics Corp. - * Copyright (C) 2017 Cogent Embedded, Inc. - */ - -#include -#include -#include -#include - -/ { - compatible = "renesas,r8a77970"; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - }; - - /* External CAN clock - to be overridden by boards that provide it */ - can_clk: can { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - a53_0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0>; - clocks = <&cpg CPG_CORE R8A77970_CLK_Z2>; - power-domains = <&sysc R8A77970_PD_CA53_CPU0>; - next-level-cache = <&L2_CA53>; - enable-method = "psci"; - }; - - a53_1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <1>; - clocks = <&cpg CPG_CORE R8A77970_CLK_Z2>; - power-domains = <&sysc R8A77970_PD_CA53_CPU1>; - next-level-cache = <&L2_CA53>; - enable-method = "psci"; - }; - - L2_CA53: cache-controller { - compatible = "cache"; - power-domains = <&sysc R8A77970_PD_CA53_SCU>; - cache-unified; - cache-level = <2>; - }; - }; - - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board */ - clock-frequency = <0>; - }; - - extalr_clk: extalr { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board */ - clock-frequency = <0>; - }; - - pmu_a53 { - compatible = "arm,cortex-a53-pmu"; - interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&a53_0>, <&a53_1>; - }; - - psci { - compatible = "arm,psci-1.0", "arm,psci-0.2"; - method = "smc"; - }; - - /* External SCIF clock - to be overridden by boards that provide it */ - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - soc { - compatible = "simple-bus"; - interrupt-parent = <&gic>; - - #address-cells = <2>; - #size-cells = <2>; - ranges; - - rwdt: watchdog@e6020000 { - compatible = "renesas,r8a77970-wdt", - "renesas,rcar-gen3-wdt"; - reg = <0 0xe6020000 0 0x0c>; - clocks = <&cpg CPG_MOD 402>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 402>; - status = "disabled"; - }; - - gpio0: gpio@e6050000 { - compatible = "renesas,gpio-r8a77970", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6050000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 0 22>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 912>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 912>; - }; - - gpio1: gpio@e6051000 { - compatible = "renesas,gpio-r8a77970", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6051000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 32 28>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 911>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 911>; - }; - - gpio2: gpio@e6052000 { - compatible = "renesas,gpio-r8a77970", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6052000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 64 17>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 910>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 910>; - }; - - gpio3: gpio@e6053000 { - compatible = "renesas,gpio-r8a77970", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6053000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 96 17>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 909>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 909>; - }; - - gpio4: gpio@e6054000 { - compatible = "renesas,gpio-r8a77970", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6054000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 128 6>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 908>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 908>; - }; - - gpio5: gpio@e6055000 { - compatible = "renesas,gpio-r8a77970", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6055000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 160 15>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 907>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 907>; - }; - - pfc: pin-controller@e6060000 { - compatible = "renesas,pfc-r8a77970"; - reg = <0 0xe6060000 0 0x504>; - }; - - cmt0: timer@e60f0000 { - compatible = "renesas,r8a77970-cmt0", - "renesas,rcar-gen3-cmt0"; - reg = <0 0xe60f0000 0 0x1004>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 303>; - clock-names = "fck"; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 303>; - status = "disabled"; - }; - - cmt1: timer@e6130000 { - compatible = "renesas,r8a77970-cmt1", - "renesas,rcar-gen3-cmt1"; - reg = <0 0xe6130000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 302>; - clock-names = "fck"; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 302>; - status = "disabled"; - }; - - cmt2: timer@e6140000 { - compatible = "renesas,r8a77970-cmt1", - "renesas,rcar-gen3-cmt1"; - reg = <0 0xe6140000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 301>; - clock-names = "fck"; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 301>; - status = "disabled"; - }; - - cmt3: timer@e6148000 { - compatible = "renesas,r8a77970-cmt1", - "renesas,rcar-gen3-cmt1"; - reg = <0 0xe6148000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 300>; - clock-names = "fck"; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 300>; - status = "disabled"; - }; - - cpg: clock-controller@e6150000 { - compatible = "renesas,r8a77970-cpg-mssr"; - reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk>, <&extalr_clk>; - clock-names = "extal", "extalr"; - #clock-cells = <2>; - #power-domain-cells = <0>; - #reset-cells = <1>; - }; - - rst: reset-controller@e6160000 { - compatible = "renesas,r8a77970-rst"; - reg = <0 0xe6160000 0 0x200>; - }; - - sysc: system-controller@e6180000 { - compatible = "renesas,r8a77970-sysc"; - reg = <0 0xe6180000 0 0x440>; - #power-domain-cells = <1>; - }; - - thermal: thermal@e6190000 { - compatible = "renesas,thermal-r8a77970"; - reg = <0 0xe6190000 0 0x10>, - <0 0xe6190100 0 0x120>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 522>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 522>; - #thermal-sensor-cells = <0>; - }; - - intc_ex: interrupt-controller@e61c0000 { - compatible = "renesas,intc-ex-r8a77970", "renesas,irqc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0 0xe61c0000 0 0x200>; - interrupts = , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 407>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 407>; - }; - - tmu0: timer@e61e0000 { - compatible = "renesas,tmu-r8a77970", "renesas,tmu"; - reg = <0 0xe61e0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 125>; - clock-names = "fck"; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 125>; - status = "disabled"; - }; - - tmu1: timer@e6fc0000 { - compatible = "renesas,tmu-r8a77970", "renesas,tmu"; - reg = <0 0xe6fc0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 124>; - clock-names = "fck"; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 124>; - status = "disabled"; - }; - - tmu2: timer@e6fd0000 { - compatible = "renesas,tmu-r8a77970", "renesas,tmu"; - reg = <0 0xe6fd0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 123>; - clock-names = "fck"; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 123>; - status = "disabled"; - }; - - tmu3: timer@e6fe0000 { - compatible = "renesas,tmu-r8a77970", "renesas,tmu"; - reg = <0 0xe6fe0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 122>; - clock-names = "fck"; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 122>; - status = "disabled"; - }; - - tmu4: timer@ffc00000 { - compatible = "renesas,tmu-r8a77970", "renesas,tmu"; - reg = <0 0xffc00000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 121>; - clock-names = "fck"; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 121>; - status = "disabled"; - }; - - i2c0: i2c@e6500000 { - compatible = "renesas,i2c-r8a77970", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6500000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 931>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 931>; - dmas = <&dmac1 0x91>, <&dmac1 0x90>, - <&dmac2 0x91>, <&dmac2 0x90>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c1: i2c@e6508000 { - compatible = "renesas,i2c-r8a77970", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6508000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 930>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 930>; - dmas = <&dmac1 0x93>, <&dmac1 0x92>, - <&dmac2 0x93>, <&dmac2 0x92>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@e6510000 { - compatible = "renesas,i2c-r8a77970", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6510000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 929>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 929>; - dmas = <&dmac1 0x95>, <&dmac1 0x94>, - <&dmac2 0x95>, <&dmac2 0x94>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c3: i2c@e66d0000 { - compatible = "renesas,i2c-r8a77970", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66d0000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 928>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 928>; - dmas = <&dmac1 0x97>, <&dmac1 0x96>, - <&dmac2 0x97>, <&dmac2 0x96>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c4: i2c@e66d8000 { - compatible = "renesas,i2c-r8a77970", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66d8000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 927>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 927>; - dmas = <&dmac1 0x99>, <&dmac1 0x98>, - <&dmac2 0x99>, <&dmac2 0x98>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - hscif0: serial@e6540000 { - compatible = "renesas,hscif-r8a77970", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6540000 0 96>; - interrupts = ; - clocks = <&cpg CPG_MOD 520>, - <&cpg CPG_CORE R8A77970_CLK_S2D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x31>, <&dmac1 0x30>, - <&dmac2 0x31>, <&dmac2 0x30>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 520>; - status = "disabled"; - }; - - hscif1: serial@e6550000 { - compatible = "renesas,hscif-r8a77970", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6550000 0 96>; - interrupts = ; - clocks = <&cpg CPG_MOD 519>, - <&cpg CPG_CORE R8A77970_CLK_S2D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x33>, <&dmac1 0x32>, - <&dmac2 0x33>, <&dmac2 0x32>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 519>; - status = "disabled"; - }; - - hscif2: serial@e6560000 { - compatible = "renesas,hscif-r8a77970", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6560000 0 96>; - interrupts = ; - clocks = <&cpg CPG_MOD 518>, - <&cpg CPG_CORE R8A77970_CLK_S2D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x35>, <&dmac1 0x34>, - <&dmac2 0x35>, <&dmac2 0x34>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 518>; - status = "disabled"; - }; - - hscif3: serial@e66a0000 { - compatible = "renesas,hscif-r8a77970", - "renesas,rcar-gen3-hscif", "renesas,hscif"; - reg = <0 0xe66a0000 0 96>; - interrupts = ; - clocks = <&cpg CPG_MOD 517>, - <&cpg CPG_CORE R8A77970_CLK_S2D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x37>, <&dmac1 0x36>, - <&dmac2 0x37>, <&dmac2 0x36>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 517>; - status = "disabled"; - }; - - canfd: can@e66c0000 { - compatible = "renesas,r8a77970-canfd", - "renesas,rcar-gen3-canfd"; - reg = <0 0xe66c0000 0 0x8000>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 914>, - <&cpg CPG_CORE R8A77970_CLK_CANFD>, - <&can_clk>; - clock-names = "fck", "canfd", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A77970_CLK_CANFD>; - assigned-clock-rates = <40000000>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 914>; - status = "disabled"; - - channel0 { - status = "disabled"; - }; - - channel1 { - status = "disabled"; - }; - }; - - avb: ethernet@e6800000 { - compatible = "renesas,etheravb-r8a77970", - "renesas,etheravb-rcar-gen3"; - reg = <0 0xe6800000 0 0x800>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15", - "ch16", "ch17", "ch18", "ch19", - "ch20", "ch21", "ch22", "ch23", - "ch24"; - clocks = <&cpg CPG_MOD 812>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 812>; - phy-mode = "rgmii"; - iommus = <&ipmmu_rt 3>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - pwm0: pwm@e6e30000 { - compatible = "renesas,pwm-r8a77970", "renesas,pwm-rcar"; - reg = <0 0xe6e30000 0 8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 523>; - status = "disabled"; - }; - - pwm1: pwm@e6e31000 { - compatible = "renesas,pwm-r8a77970", "renesas,pwm-rcar"; - reg = <0 0xe6e31000 0 8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 523>; - status = "disabled"; - }; - - pwm2: pwm@e6e32000 { - compatible = "renesas,pwm-r8a77970", "renesas,pwm-rcar"; - reg = <0 0xe6e32000 0 8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 523>; - status = "disabled"; - }; - - pwm3: pwm@e6e33000 { - compatible = "renesas,pwm-r8a77970", "renesas,pwm-rcar"; - reg = <0 0xe6e33000 0 8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 523>; - status = "disabled"; - }; - - pwm4: pwm@e6e34000 { - compatible = "renesas,pwm-r8a77970", "renesas,pwm-rcar"; - reg = <0 0xe6e34000 0 8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 523>; - status = "disabled"; - }; - - scif0: serial@e6e60000 { - compatible = "renesas,scif-r8a77970", - "renesas,rcar-gen3-scif", - "renesas,scif"; - reg = <0 0xe6e60000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 207>, - <&cpg CPG_CORE R8A77970_CLK_S2D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x51>, <&dmac1 0x50>, - <&dmac2 0x51>, <&dmac2 0x50>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 207>; - status = "disabled"; - }; - - scif1: serial@e6e68000 { - compatible = "renesas,scif-r8a77970", - "renesas,rcar-gen3-scif", - "renesas,scif"; - reg = <0 0xe6e68000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 206>, - <&cpg CPG_CORE R8A77970_CLK_S2D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x53>, <&dmac1 0x52>, - <&dmac2 0x53>, <&dmac2 0x52>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 206>; - status = "disabled"; - }; - - scif3: serial@e6c50000 { - compatible = "renesas,scif-r8a77970", - "renesas,rcar-gen3-scif", - "renesas,scif"; - reg = <0 0xe6c50000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 204>, - <&cpg CPG_CORE R8A77970_CLK_S2D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x57>, <&dmac1 0x56>, - <&dmac2 0x57>, <&dmac2 0x56>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 204>; - status = "disabled"; - }; - - scif4: serial@e6c40000 { - compatible = "renesas,scif-r8a77970", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6c40000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 203>, - <&cpg CPG_CORE R8A77970_CLK_S2D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x59>, <&dmac1 0x58>, - <&dmac2 0x59>, <&dmac2 0x58>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 203>; - status = "disabled"; - }; - - tpu: pwm@e6e80000 { - compatible = "renesas,tpu-r8a77970", "renesas,tpu"; - reg = <0 0xe6e80000 0 0x148>; - interrupts = ; - clocks = <&cpg CPG_MOD 304>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 304>; - #pwm-cells = <3>; - status = "disabled"; - }; - - msiof0: spi@e6e90000 { - compatible = "renesas,msiof-r8a77970", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6e90000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 211>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 211>; - dmas = <&dmac1 0x41>, <&dmac1 0x40>, - <&dmac2 0x41>, <&dmac2 0x40>; - dma-names = "tx", "rx", "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof1: spi@e6ea0000 { - compatible = "renesas,msiof-r8a77970", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6ea0000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 210>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 210>; - dmas = <&dmac1 0x43>, <&dmac1 0x42>, - <&dmac2 0x43>, <&dmac2 0x42>; - dma-names = "tx", "rx", "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof2: spi@e6c00000 { - compatible = "renesas,msiof-r8a77970", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6c00000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 209>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 209>; - dmas = <&dmac1 0x45>, <&dmac1 0x44>, - <&dmac2 0x45>, <&dmac2 0x44>; - dma-names = "tx", "rx", "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof3: spi@e6c10000 { - compatible = "renesas,msiof-r8a77970", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6c10000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 208>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 208>; - dmas = <&dmac1 0x47>, <&dmac1 0x46>, - <&dmac2 0x47>, <&dmac2 0x46>; - dma-names = "tx", "rx", "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - vin0: video@e6ef0000 { - compatible = "renesas,vin-r8a77970"; - reg = <0 0xe6ef0000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 811>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 811>; - renesas,id = <0>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin0csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin0>; - }; - }; - }; - }; - - vin1: video@e6ef1000 { - compatible = "renesas,vin-r8a77970"; - reg = <0 0xe6ef1000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 810>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 810>; - renesas,id = <1>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin1csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin1>; - }; - }; - }; - }; - - vin2: video@e6ef2000 { - compatible = "renesas,vin-r8a77970"; - reg = <0 0xe6ef2000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 809>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 809>; - renesas,id = <2>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin2csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin2>; - }; - }; - }; - }; - - vin3: video@e6ef3000 { - compatible = "renesas,vin-r8a77970"; - reg = <0 0xe6ef3000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 808>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 808>; - renesas,id = <3>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin3csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin3>; - }; - }; - }; - }; - - dmac1: dma-controller@e7300000 { - compatible = "renesas,dmac-r8a77970", - "renesas,rcar-dmac"; - reg = <0 0xe7300000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7"; - clocks = <&cpg CPG_MOD 218>; - clock-names = "fck"; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 218>; - #dma-cells = <1>; - dma-channels = <8>; - iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, - <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, - <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, - <&ipmmu_ds1 6>, <&ipmmu_ds1 7>; - }; - - dmac2: dma-controller@e7310000 { - compatible = "renesas,dmac-r8a77970", - "renesas,rcar-dmac"; - reg = <0 0xe7310000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7"; - clocks = <&cpg CPG_MOD 217>; - clock-names = "fck"; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 217>; - #dma-cells = <1>; - dma-channels = <8>; - iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, - <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, - <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, - <&ipmmu_ds1 22>, <&ipmmu_ds1 23>; - }; - - ipmmu_ds1: mmu@e7740000 { - compatible = "renesas,ipmmu-r8a77970"; - reg = <0 0xe7740000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 0>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_ir: mmu@ff8b0000 { - compatible = "renesas,ipmmu-r8a77970"; - reg = <0 0xff8b0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 3>; - power-domains = <&sysc R8A77970_PD_A3IR>; - #iommu-cells = <1>; - }; - - ipmmu_mm: mmu@e67b0000 { - compatible = "renesas,ipmmu-r8a77970"; - reg = <0 0xe67b0000 0 0x1000>; - interrupts = , - ; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_rt: mmu@ffc80000 { - compatible = "renesas,ipmmu-r8a77970"; - reg = <0 0xffc80000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 7>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_vi0: mmu@febd0000 { - compatible = "renesas,ipmmu-r8a77970"; - reg = <0 0xfebd0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 9>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - mmc0: mmc@ee140000 { - compatible = "renesas,sdhi-r8a77970", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee140000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 314>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 314>; - max-frequency = <200000000>; - iommus = <&ipmmu_ds1 32>; - status = "disabled"; - }; - - gic: interrupt-controller@f1010000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0 0xf1010000 0 0x1000>, - <0 0xf1020000 0 0x20000>, - <0 0xf1040000 0 0x20000>, - <0 0xf1060000 0 0x20000>; - interrupts = ; - clocks = <&cpg CPG_MOD 408>; - clock-names = "clk"; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 408>; - }; - - vspd0: vsp@fea20000 { - compatible = "renesas,vsp2"; - reg = <0 0xfea20000 0 0x5000>; - interrupts = ; - clocks = <&cpg CPG_MOD 623>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 623>; - renesas,fcp = <&fcpvd0>; - }; - - fcpvd0: fcp@fea27000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea27000 0 0x200>; - clocks = <&cpg CPG_MOD 603>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 603>; - }; - - csi40: csi2@feaa0000 { - compatible = "renesas,r8a77970-csi2"; - reg = <0 0xfeaa0000 0 0x10000>; - interrupts = ; - clocks = <&cpg CPG_MOD 716>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 716>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - csi40vin0: endpoint@0 { - reg = <0>; - remote-endpoint = <&vin0csi40>; - }; - csi40vin1: endpoint@1 { - reg = <1>; - remote-endpoint = <&vin1csi40>; - }; - csi40vin2: endpoint@2 { - reg = <2>; - remote-endpoint = <&vin2csi40>; - }; - csi40vin3: endpoint@3 { - reg = <3>; - remote-endpoint = <&vin3csi40>; - }; - }; - }; - }; - - du: display@feb00000 { - compatible = "renesas,du-r8a77970"; - reg = <0 0xfeb00000 0 0x80000>; - interrupts = ; - clocks = <&cpg CPG_MOD 724>; - clock-names = "du.0"; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 724>; - vsps = <&vspd0 0>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - du_out_rgb: endpoint { - }; - }; - - port@1 { - reg = <1>; - du_out_lvds0: endpoint { - remote-endpoint = <&lvds0_in>; - }; - }; - }; - }; - - lvds0: lvds-encoder@feb90000 { - compatible = "renesas,r8a77970-lvds"; - reg = <0 0xfeb90000 0 0x14>; - clocks = <&cpg CPG_MOD 727>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 727>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - lvds0_in: endpoint { - remote-endpoint = - <&du_out_lvds0>; - }; - }; - port@1 { - reg = <1>; - lvds0_out: endpoint { - }; - }; - }; - }; - - prr: chipid@fff00044 { - compatible = "renesas,prr"; - reg = <0 0xfff00044 0 4>; - }; - }; - - thermal-zones { - cpu-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&thermal>; - - cooling-maps { - }; - - trips { - cpu-crit { - temperature = <120000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; - }; -}; diff --git a/sys/gnu/dts/arm64/renesas/r8a77980-condor.dts b/sys/gnu/dts/arm64/renesas/r8a77980-condor.dts deleted file mode 100644 index 3dde028e22a..00000000000 --- a/sys/gnu/dts/arm64/renesas/r8a77980-condor.dts +++ /dev/null @@ -1,292 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the Condor board - * - * Copyright (C) 2018 Renesas Electronics Corp. - * Copyright (C) 2018 Cogent Embedded, Inc. - */ - -/dts-v1/; -#include "r8a77980.dtsi" - -/ { - model = "Renesas Condor board based on r8a77980"; - compatible = "renesas,condor", "renesas,r8a77980"; - - aliases { - serial0 = &scif0; - ethernet0 = &gether; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - d1_8v: regulator-2 { - compatible = "regulator-fixed"; - regulator-name = "D1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - d3_3v: regulator-0 { - compatible = "regulator-fixed"; - regulator-name = "D3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - hdmi-out { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con: endpoint { - remote-endpoint = <&adv7511_out>; - }; - }; - }; - - lvds-decoder { - compatible = "thine,thc63lvd1024"; - vcc-supply = <&d3_3v>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - thc63lvd1024_in: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - - port@2 { - reg = <2>; - thc63lvd1024_out: endpoint { - remote-endpoint = <&adv7511_in>; - }; - }; - }; - }; - - memory@48000000 { - device_type = "memory"; - /* first 128MB is reserved for secure area. */ - reg = <0 0x48000000 0 0x78000000>; - }; - - vddq_vin01: regulator-1 { - compatible = "regulator-fixed"; - regulator-name = "VDDQ_VIN01"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - x1_clk: x1-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <148500000>; - }; -}; - -&canfd { - pinctrl-0 = <&canfd0_pins>; - pinctrl-names = "default"; - status = "okay"; - - channel0 { - status = "okay"; - }; -}; - -&du { - clocks = <&cpg CPG_MOD 724>, - <&x1_clk>; - clock-names = "du.0", "dclkin.0"; - status = "okay"; -}; - -&extal_clk { - clock-frequency = <16666666>; -}; - -&extalr_clk { - clock-frequency = <32768>; -}; - -&gether { - pinctrl-0 = <&gether_pins>; - pinctrl-names = "default"; - - phy-mode = "rgmii-id"; - phy-handle = <&phy0>; - renesas,no-ether-link; - status = "okay"; - - phy0: ethernet-phy@0 { - rxc-skew-ps = <1500>; - reg = <0>; - interrupt-parent = <&gpio4>; - interrupts = <23 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&i2c0 { - pinctrl-0 = <&i2c0_pins>; - pinctrl-names = "default"; - - status = "okay"; - clock-frequency = <400000>; - - io_expander0: gpio@20 { - compatible = "onnn,pca9654"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - }; - - io_expander1: gpio@21 { - compatible = "onnn,pca9654"; - reg = <0x21>; - gpio-controller; - #gpio-cells = <2>; - }; - - hdmi@39 { - compatible = "adi,adv7511w"; - reg = <0x39>; - interrupt-parent = <&gpio1>; - interrupts = <20 IRQ_TYPE_LEVEL_LOW>; - avdd-supply = <&d1_8v>; - dvdd-supply = <&d1_8v>; - pvdd-supply = <&d1_8v>; - bgvdd-supply = <&d1_8v>; - dvdd-3v-supply = <&d3_3v>; - - adi,input-depth = <8>; - adi,input-colorspace = "rgb"; - adi,input-clock = "1x"; - adi,input-style = <1>; - adi,input-justification = "evenly"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7511_in: endpoint { - remote-endpoint = <&thc63lvd1024_out>; - }; - }; - - port@1 { - reg = <1>; - adv7511_out: endpoint { - remote-endpoint = <&hdmi_con>; - }; - }; - }; - }; -}; - -&lvds0 { - status = "okay"; - - ports { - port@1 { - lvds0_out: endpoint { - remote-endpoint = <&thc63lvd1024_in>; - }; - }; - }; -}; - -&mmc0 { - pinctrl-0 = <&mmc_pins>; - pinctrl-1 = <&mmc_pins_uhs>; - pinctrl-names = "default", "state_uhs"; - - vmmc-supply = <&d3_3v>; - vqmmc-supply = <&vddq_vin01>; - mmc-hs200-1_8v; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&pciec { - status = "okay"; -}; - -&pcie_bus_clk { - clock-frequency = <100000000>; -}; - -&pcie_phy { - status = "okay"; -}; - -&pfc { - canfd0_pins: canfd0 { - groups = "canfd0_data_a"; - function = "canfd0"; - }; - - gether_pins: gether { - groups = "gether_mdio_a", "gether_rgmii", - "gether_txcrefclk", "gether_txcrefclk_mega"; - function = "gether"; - }; - - i2c0_pins: i2c0 { - groups = "i2c0"; - function = "i2c0"; - }; - - mmc_pins: mmc { - groups = "mmc_data8", "mmc_ctrl", "mmc_ds"; - function = "mmc"; - power-source = <3300>; - }; - - mmc_pins_uhs: mmc_uhs { - groups = "mmc_data8", "mmc_ctrl", "mmc_ds"; - function = "mmc"; - power-source = <1800>; - }; - - scif0_pins: scif0 { - groups = "scif0_data"; - function = "scif0"; - }; - - scif_clk_pins: scif_clk { - groups = "scif_clk_b"; - function = "scif_clk"; - }; -}; - -&rwdt { - timeout-sec = <60>; - status = "okay"; -}; - -&scif0 { - pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&scif_clk { - clock-frequency = <14745600>; -}; diff --git a/sys/gnu/dts/arm64/renesas/r8a77980-v3hsk.dts b/sys/gnu/dts/arm64/renesas/r8a77980-v3hsk.dts deleted file mode 100644 index adbfd8f07d0..00000000000 --- a/sys/gnu/dts/arm64/renesas/r8a77980-v3hsk.dts +++ /dev/null @@ -1,217 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the V3H Starter Kit board - * - * Copyright (C) 2018 Renesas Electronics Corp. - * Copyright (C) 2018 Cogent Embedded, Inc. - */ - -/dts-v1/; -#include "r8a77980.dtsi" - -/ { - model = "Renesas V3H Starter Kit board"; - compatible = "renesas,v3hsk", "renesas,r8a77980"; - - aliases { - serial0 = &scif0; - ethernet0 = &gether; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - hdmi-out { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con: endpoint { - remote-endpoint = <&adv7511_out>; - }; - }; - }; - - lvds-decoder { - compatible = "thine,thc63lvd1024"; - vcc-supply = <&vcc3v3_d5>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - thc63lvd1024_in: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - - port@2 { - reg = <2>; - thc63lvd1024_out: endpoint { - remote-endpoint = <&adv7511_in>; - }; - }; - }; - }; - - memory@48000000 { - device_type = "memory"; - /* first 128MB is reserved for secure area. */ - reg = <0 0x48000000 0 0x78000000>; - }; - - osc1_clk: osc1-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <148500000>; - }; - - vcc1v8_d4: regulator-0 { - compatible = "regulator-fixed"; - regulator-name = "VCC1V8_D4"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - vcc3v3_d5: regulator-1 { - compatible = "regulator-fixed"; - regulator-name = "VCC3V3_D5"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; -}; - -&du { - clocks = <&cpg CPG_MOD 724>, - <&osc1_clk>; - clock-names = "du.0", "dclkin.0"; - status = "okay"; -}; - -&extal_clk { - clock-frequency = <16666666>; -}; - -&extalr_clk { - clock-frequency = <32768>; -}; - -&gether { - pinctrl-0 = <&gether_pins>; - pinctrl-names = "default"; - - phy-mode = "rgmii"; - phy-handle = <&phy0>; - renesas,no-ether-link; - status = "okay"; - - phy0: ethernet-phy@0 { - reg = <0>; - interrupt-parent = <&gpio4>; - interrupts = <23 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&i2c0 { - pinctrl-0 = <&i2c0_pins>; - pinctrl-names = "default"; - - status = "okay"; - clock-frequency = <400000>; - - hdmi@39 { - compatible = "adi,adv7511w"; - #sound-dai-cells = <0>; - reg = <0x39>; - interrupt-parent = <&gpio1>; - interrupts = <20 IRQ_TYPE_LEVEL_LOW>; - avdd-supply = <&vcc1v8_d4>; - dvdd-supply = <&vcc1v8_d4>; - pvdd-supply = <&vcc1v8_d4>; - bgvdd-supply = <&vcc1v8_d4>; - dvdd-3v-supply = <&vcc3v3_d5>; - - adi,input-depth = <8>; - adi,input-colorspace = "rgb"; - adi,input-clock = "1x"; - adi,input-style = <1>; - adi,input-justification = "evenly"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7511_in: endpoint { - remote-endpoint = <&thc63lvd1024_out>; - }; - }; - - port@1 { - reg = <1>; - adv7511_out: endpoint { - remote-endpoint = <&hdmi_con>; - }; - }; - }; - }; -}; - -&lvds0 { - status = "okay"; - - ports { - port@1 { - lvds0_out: endpoint { - remote-endpoint = <&thc63lvd1024_in>; - }; - }; - }; -}; - -&pfc { - gether_pins: gether { - groups = "gether_mdio_a", "gether_rgmii", - "gether_txcrefclk", "gether_txcrefclk_mega"; - function = "gether"; - }; - - i2c0_pins: i2c0 { - groups = "i2c0"; - function = "i2c0"; - }; - - scif0_pins: scif0 { - groups = "scif0_data"; - function = "scif0"; - }; - - scif_clk_pins: scif_clk { - groups = "scif_clk_b"; - function = "scif_clk"; - }; -}; - -&rwdt { - timeout-sec = <60>; - status = "okay"; -}; - -&scif0 { - pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&scif_clk { - clock-frequency = <14745600>; -}; diff --git a/sys/gnu/dts/arm64/renesas/r8a77980.dtsi b/sys/gnu/dts/arm64/renesas/r8a77980.dtsi deleted file mode 100644 index b340fb46999..00000000000 --- a/sys/gnu/dts/arm64/renesas/r8a77980.dtsi +++ /dev/null @@ -1,1602 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the R-Car V3H (R8A77980) SoC - * - * Copyright (C) 2018 Renesas Electronics Corp. - * Copyright (C) 2018 Cogent Embedded, Inc. - */ - -#include -#include -#include -#include - -/ { - compatible = "renesas,r8a77980"; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - }; - - /* External CAN clock - to be overridden by boards that provide it */ - can_clk: can { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - a53_0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0>; - clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>; - power-domains = <&sysc R8A77980_PD_CA53_CPU0>; - next-level-cache = <&L2_CA53>; - enable-method = "psci"; - }; - - a53_1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <1>; - clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>; - power-domains = <&sysc R8A77980_PD_CA53_CPU1>; - next-level-cache = <&L2_CA53>; - enable-method = "psci"; - }; - - a53_2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <2>; - clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>; - power-domains = <&sysc R8A77980_PD_CA53_CPU2>; - next-level-cache = <&L2_CA53>; - enable-method = "psci"; - }; - - a53_3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <3>; - clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>; - power-domains = <&sysc R8A77980_PD_CA53_CPU3>; - next-level-cache = <&L2_CA53>; - enable-method = "psci"; - }; - - L2_CA53: cache-controller { - compatible = "cache"; - power-domains = <&sysc R8A77980_PD_CA53_SCU>; - cache-unified; - cache-level = <2>; - }; - }; - - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board */ - clock-frequency = <0>; - }; - - extalr_clk: extalr { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board */ - clock-frequency = <0>; - }; - - /* External PCIe clock - can be overridden by the board */ - pcie_bus_clk: pcie_bus { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - pmu_a53 { - compatible = "arm,cortex-a53-pmu"; - interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>; - }; - - psci { - compatible = "arm,psci-1.0", "arm,psci-0.2"; - method = "smc"; - }; - - /* External SCIF clock - to be overridden by boards that provide it */ - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - soc { - compatible = "simple-bus"; - interrupt-parent = <&gic>; - - #address-cells = <2>; - #size-cells = <2>; - ranges; - - rwdt: watchdog@e6020000 { - compatible = "renesas,r8a77980-wdt", - "renesas,rcar-gen3-wdt"; - reg = <0 0xe6020000 0 0x0c>; - clocks = <&cpg CPG_MOD 402>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 402>; - status = "disabled"; - }; - - gpio0: gpio@e6050000 { - compatible = "renesas,gpio-r8a77980", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6050000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 0 22>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 912>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 912>; - }; - - gpio1: gpio@e6051000 { - compatible = "renesas,gpio-r8a77980", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6051000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 32 28>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 911>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 911>; - }; - - gpio2: gpio@e6052000 { - compatible = "renesas,gpio-r8a77980", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6052000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 64 30>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 910>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 910>; - }; - - gpio3: gpio@e6053000 { - compatible = "renesas,gpio-r8a77980", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6053000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 96 17>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 909>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 909>; - }; - - gpio4: gpio@e6054000 { - compatible = "renesas,gpio-r8a77980", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6054000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 128 25>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 908>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 908>; - }; - - gpio5: gpio@e6055000 { - compatible = "renesas,gpio-r8a77980", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6055000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 160 15>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 907>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 907>; - }; - - pfc: pin-controller@e6060000 { - compatible = "renesas,pfc-r8a77980"; - reg = <0 0xe6060000 0 0x50c>; - }; - - cmt0: timer@e60f0000 { - compatible = "renesas,r8a77980-cmt0", - "renesas,rcar-gen3-cmt0"; - reg = <0 0xe60f0000 0 0x1004>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 303>; - clock-names = "fck"; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 303>; - status = "disabled"; - }; - - cmt1: timer@e6130000 { - compatible = "renesas,r8a77980-cmt1", - "renesas,rcar-gen3-cmt1"; - reg = <0 0xe6130000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 302>; - clock-names = "fck"; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 302>; - status = "disabled"; - }; - - cmt2: timer@e6140000 { - compatible = "renesas,r8a77980-cmt1", - "renesas,rcar-gen3-cmt1"; - reg = <0 0xe6140000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 301>; - clock-names = "fck"; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 301>; - status = "disabled"; - }; - - cmt3: timer@e6148000 { - compatible = "renesas,r8a77980-cmt1", - "renesas,rcar-gen3-cmt1"; - reg = <0 0xe6148000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 300>; - clock-names = "fck"; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 300>; - status = "disabled"; - }; - - cpg: clock-controller@e6150000 { - compatible = "renesas,r8a77980-cpg-mssr"; - reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk>, <&extalr_clk>; - clock-names = "extal", "extalr"; - #clock-cells = <2>; - #power-domain-cells = <0>; - #reset-cells = <1>; - }; - - rst: reset-controller@e6160000 { - compatible = "renesas,r8a77980-rst"; - reg = <0 0xe6160000 0 0x200>; - }; - - sysc: system-controller@e6180000 { - compatible = "renesas,r8a77980-sysc"; - reg = <0 0xe6180000 0 0x440>; - #power-domain-cells = <1>; - }; - - tsc: thermal@e6198000 { - compatible = "renesas,r8a77980-thermal"; - reg = <0 0xe6198000 0 0x100>, - <0 0xe61a0000 0 0x100>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 522>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 522>; - #thermal-sensor-cells = <1>; - }; - - intc_ex: interrupt-controller@e61c0000 { - compatible = "renesas,intc-ex-r8a77980", "renesas,irqc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0 0xe61c0000 0 0x200>; - interrupts = , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 407>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 407>; - }; - - tmu0: timer@e61e0000 { - compatible = "renesas,tmu-r8a77980", "renesas,tmu"; - reg = <0 0xe61e0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 125>; - clock-names = "fck"; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 125>; - status = "disabled"; - }; - - tmu1: timer@e6fc0000 { - compatible = "renesas,tmu-r8a77980", "renesas,tmu"; - reg = <0 0xe6fc0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 124>; - clock-names = "fck"; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 124>; - status = "disabled"; - }; - - tmu2: timer@e6fd0000 { - compatible = "renesas,tmu-r8a77980", "renesas,tmu"; - reg = <0 0xe6fd0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 123>; - clock-names = "fck"; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 123>; - status = "disabled"; - }; - - tmu3: timer@e6fe0000 { - compatible = "renesas,tmu-r8a77980", "renesas,tmu"; - reg = <0 0xe6fe0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 122>; - clock-names = "fck"; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 122>; - status = "disabled"; - }; - - tmu4: timer@ffc00000 { - compatible = "renesas,tmu-r8a77980", "renesas,tmu"; - reg = <0 0xffc00000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 121>; - clock-names = "fck"; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 121>; - status = "disabled"; - }; - - i2c0: i2c@e6500000 { - compatible = "renesas,i2c-r8a77980", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6500000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 931>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 931>; - dmas = <&dmac1 0x91>, <&dmac1 0x90>, - <&dmac2 0x91>, <&dmac2 0x90>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c1: i2c@e6508000 { - compatible = "renesas,i2c-r8a77980", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6508000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 930>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 930>; - dmas = <&dmac1 0x93>, <&dmac1 0x92>, - <&dmac2 0x93>, <&dmac2 0x92>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@e6510000 { - compatible = "renesas,i2c-r8a77980", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6510000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 929>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 929>; - dmas = <&dmac1 0x95>, <&dmac1 0x94>, - <&dmac2 0x95>, <&dmac2 0x94>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c3: i2c@e66d0000 { - compatible = "renesas,i2c-r8a77980", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66d0000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 928>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 928>; - i2c-scl-internal-delay-ns = <6>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c4: i2c@e66d8000 { - compatible = "renesas,i2c-r8a77980", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66d8000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 927>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 927>; - i2c-scl-internal-delay-ns = <6>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c5: i2c@e66e0000 { - compatible = "renesas,i2c-r8a77980", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66e0000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 919>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 919>; - dmas = <&dmac1 0x9b>, <&dmac1 0x9a>, - <&dmac2 0x9b>, <&dmac2 0x9a>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - hscif0: serial@e6540000 { - compatible = "renesas,hscif-r8a77980", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6540000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 520>, - <&cpg CPG_CORE R8A77980_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x31>, <&dmac1 0x30>, - <&dmac2 0x31>, <&dmac2 0x30>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 520>; - status = "disabled"; - }; - - hscif1: serial@e6550000 { - compatible = "renesas,hscif-r8a77980", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6550000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 519>, - <&cpg CPG_CORE R8A77980_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x33>, <&dmac1 0x32>, - <&dmac2 0x33>, <&dmac2 0x32>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 519>; - status = "disabled"; - }; - - hscif2: serial@e6560000 { - compatible = "renesas,hscif-r8a77980", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6560000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 518>, - <&cpg CPG_CORE R8A77980_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x35>, <&dmac1 0x34>, - <&dmac2 0x35>, <&dmac2 0x34>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 518>; - status = "disabled"; - }; - - hscif3: serial@e66a0000 { - compatible = "renesas,hscif-r8a77980", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe66a0000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 517>, - <&cpg CPG_CORE R8A77980_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x37>, <&dmac1 0x36>, - <&dmac2 0x37>, <&dmac2 0x36>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 517>; - status = "disabled"; - }; - - pcie_phy: pcie-phy@e65d0000 { - compatible = "renesas,r8a77980-pcie-phy"; - reg = <0 0xe65d0000 0 0x8000>; - #phy-cells = <0>; - clocks = <&cpg CPG_MOD 319>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 319>; - status = "disabled"; - }; - - canfd: can@e66c0000 { - compatible = "renesas,r8a77980-canfd", - "renesas,rcar-gen3-canfd"; - reg = <0 0xe66c0000 0 0x8000>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 914>, - <&cpg CPG_CORE R8A77980_CLK_CANFD>, - <&can_clk>; - clock-names = "fck", "canfd", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A77980_CLK_CANFD>; - assigned-clock-rates = <40000000>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 914>; - status = "disabled"; - - channel0 { - status = "disabled"; - }; - - channel1 { - status = "disabled"; - }; - }; - - avb: ethernet@e6800000 { - compatible = "renesas,etheravb-r8a77980", - "renesas,etheravb-rcar-gen3"; - reg = <0 0xe6800000 0 0x800>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15", - "ch16", "ch17", "ch18", "ch19", - "ch20", "ch21", "ch22", "ch23", - "ch24"; - clocks = <&cpg CPG_MOD 812>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 812>; - phy-mode = "rgmii"; - iommus = <&ipmmu_ds1 33>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - pwm0: pwm@e6e30000 { - compatible = "renesas,pwm-r8a77980", "renesas,pwm-rcar"; - reg = <0 0xe6e30000 0 0x10>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 523>; - status = "disabled"; - }; - - pwm1: pwm@e6e31000 { - compatible = "renesas,pwm-r8a77980", "renesas,pwm-rcar"; - reg = <0 0xe6e31000 0 0x10>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 523>; - status = "disabled"; - }; - - pwm2: pwm@e6e32000 { - compatible = "renesas,pwm-r8a77980", "renesas,pwm-rcar"; - reg = <0 0xe6e32000 0 0x10>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 523>; - status = "disabled"; - }; - - pwm3: pwm@e6e33000 { - compatible = "renesas,pwm-r8a77980", "renesas,pwm-rcar"; - reg = <0 0xe6e33000 0 0x10>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 523>; - status = "disabled"; - }; - - pwm4: pwm@e6e34000 { - compatible = "renesas,pwm-r8a77980", "renesas,pwm-rcar"; - reg = <0 0xe6e34000 0 0x10>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 523>; - status = "disabled"; - }; - - scif0: serial@e6e60000 { - compatible = "renesas,scif-r8a77980", - "renesas,rcar-gen3-scif", - "renesas,scif"; - reg = <0 0xe6e60000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 207>, - <&cpg CPG_CORE R8A77980_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x51>, <&dmac1 0x50>, - <&dmac2 0x51>, <&dmac2 0x50>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 207>; - status = "disabled"; - }; - - scif1: serial@e6e68000 { - compatible = "renesas,scif-r8a77980", - "renesas,rcar-gen3-scif", - "renesas,scif"; - reg = <0 0xe6e68000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 206>, - <&cpg CPG_CORE R8A77980_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x53>, <&dmac1 0x52>, - <&dmac2 0x53>, <&dmac2 0x52>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 206>; - status = "disabled"; - }; - - scif3: serial@e6c50000 { - compatible = "renesas,scif-r8a77980", - "renesas,rcar-gen3-scif", - "renesas,scif"; - reg = <0 0xe6c50000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 204>, - <&cpg CPG_CORE R8A77980_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x57>, <&dmac1 0x56>, - <&dmac2 0x57>, <&dmac2 0x56>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 204>; - status = "disabled"; - }; - - scif4: serial@e6c40000 { - compatible = "renesas,scif-r8a77980", - "renesas,rcar-gen3-scif", - "renesas,scif"; - reg = <0 0xe6c40000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 203>, - <&cpg CPG_CORE R8A77980_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x59>, <&dmac1 0x58>, - <&dmac2 0x59>, <&dmac2 0x58>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 203>; - status = "disabled"; - }; - - tpu: pwm@e6e80000 { - compatible = "renesas,tpu-r8a77980", "renesas,tpu"; - reg = <0 0xe6e80000 0 0x148>; - interrupts = ; - clocks = <&cpg CPG_MOD 304>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 304>; - #pwm-cells = <3>; - status = "disabled"; - }; - - msiof0: spi@e6e90000 { - compatible = "renesas,msiof-r8a77980", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6e90000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 211>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 211>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof1: spi@e6ea0000 { - compatible = "renesas,msiof-r8a77980", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6ea0000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 210>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 210>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof2: spi@e6c00000 { - compatible = "renesas,msiof-r8a77980", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6c00000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 209>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 209>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof3: spi@e6c10000 { - compatible = "renesas,msiof-r8a77980", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6c10000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 208>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 208>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - vin0: video@e6ef0000 { - compatible = "renesas,vin-r8a77980"; - reg = <0 0xe6ef0000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 811>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 811>; - renesas,id = <0>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin0csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin0>; - }; - }; - }; - }; - - vin1: video@e6ef1000 { - compatible = "renesas,vin-r8a77980"; - reg = <0 0xe6ef1000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 810>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - status = "disabled"; - renesas,id = <1>; - resets = <&cpg 810>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin1csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin1>; - }; - }; - }; - }; - - vin2: video@e6ef2000 { - compatible = "renesas,vin-r8a77980"; - reg = <0 0xe6ef2000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 809>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 809>; - renesas,id = <2>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin2csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin2>; - }; - }; - }; - }; - - vin3: video@e6ef3000 { - compatible = "renesas,vin-r8a77980"; - reg = <0 0xe6ef3000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 808>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 808>; - renesas,id = <3>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin3csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin3>; - }; - }; - }; - }; - - vin4: video@e6ef4000 { - compatible = "renesas,vin-r8a77980"; - reg = <0 0xe6ef4000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 807>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 807>; - renesas,id = <4>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin4csi41: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi41vin4>; - }; - }; - }; - }; - - vin5: video@e6ef5000 { - compatible = "renesas,vin-r8a77980"; - reg = <0 0xe6ef5000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 806>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 806>; - renesas,id = <5>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin5csi41: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi41vin5>; - }; - }; - }; - }; - - vin6: video@e6ef6000 { - compatible = "renesas,vin-r8a77980"; - reg = <0 0xe6ef6000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 805>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 805>; - renesas,id = <6>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin6csi41: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi41vin6>; - }; - }; - }; - }; - - vin7: video@e6ef7000 { - compatible = "renesas,vin-r8a77980"; - reg = <0 0xe6ef7000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 804>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 804>; - renesas,id = <7>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin7csi41: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi41vin7>; - }; - }; - }; - }; - - vin8: video@e6ef8000 { - compatible = "renesas,vin-r8a77980"; - reg = <0 0xe6ef8000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 628>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 628>; - renesas,id = <8>; - status = "disabled"; - }; - - vin9: video@e6ef9000 { - compatible = "renesas,vin-r8a77980"; - reg = <0 0xe6ef9000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 627>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 627>; - renesas,id = <9>; - status = "disabled"; - }; - - vin10: video@e6efa000 { - compatible = "renesas,vin-r8a77980"; - reg = <0 0xe6efa000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 625>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 625>; - renesas,id = <10>; - status = "disabled"; - }; - - vin11: video@e6efb000 { - compatible = "renesas,vin-r8a77980"; - reg = <0 0xe6efb000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 618>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 618>; - renesas,id = <11>; - status = "disabled"; - }; - - vin12: video@e6efc000 { - compatible = "renesas,vin-r8a77980"; - reg = <0 0xe6efc000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 612>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 612>; - renesas,id = <12>; - status = "disabled"; - }; - - vin13: video@e6efd000 { - compatible = "renesas,vin-r8a77980"; - reg = <0 0xe6efd000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 608>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 608>; - renesas,id = <13>; - status = "disabled"; - }; - - vin14: video@e6efe000 { - compatible = "renesas,vin-r8a77980"; - reg = <0 0xe6efe000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 605>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 605>; - renesas,id = <14>; - status = "disabled"; - }; - - vin15: video@e6eff000 { - compatible = "renesas,vin-r8a77980"; - reg = <0 0xe6eff000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 604>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 604>; - renesas,id = <15>; - status = "disabled"; - }; - - dmac1: dma-controller@e7300000 { - compatible = "renesas,dmac-r8a77980", - "renesas,rcar-dmac"; - reg = <0 0xe7300000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 218>; - clock-names = "fck"; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 218>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, - <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, - <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, - <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, - <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, - <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, - <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, - <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; - }; - - dmac2: dma-controller@e7310000 { - compatible = "renesas,dmac-r8a77980", - "renesas,rcar-dmac"; - reg = <0 0xe7310000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 217>; - clock-names = "fck"; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 217>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, - <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, - <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, - <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, - <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, - <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, - <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, - <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; - }; - - gether: ethernet@e7400000 { - compatible = "renesas,gether-r8a77980"; - reg = <0 0xe7400000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 813>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 813>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - ipmmu_ds1: mmu@e7740000 { - compatible = "renesas,ipmmu-r8a77980"; - reg = <0 0xe7740000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 0>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_ir: mmu@ff8b0000 { - compatible = "renesas,ipmmu-r8a77980"; - reg = <0 0xff8b0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 3>; - power-domains = <&sysc R8A77980_PD_A3IR>; - #iommu-cells = <1>; - }; - - ipmmu_mm: mmu@e67b0000 { - compatible = "renesas,ipmmu-r8a77980"; - reg = <0 0xe67b0000 0 0x1000>; - interrupts = , - ; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_rt: mmu@ffc80000 { - compatible = "renesas,ipmmu-r8a77980"; - reg = <0 0xffc80000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 10>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_vc0: mmu@fe990000 { - compatible = "renesas,ipmmu-r8a77980"; - reg = <0 0xfe990000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 12>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_vi0: mmu@febd0000 { - compatible = "renesas,ipmmu-r8a77980"; - reg = <0 0xfebd0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 14>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_vip0: mmu@e7b00000 { - compatible = "renesas,ipmmu-r8a77980"; - reg = <0 0xe7b00000 0 0x1000>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_vip1: mmu@e7960000 { - compatible = "renesas,ipmmu-r8a77980"; - reg = <0 0xe7960000 0 0x1000>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - mmc0: mmc@ee140000 { - compatible = "renesas,sdhi-r8a77980", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee140000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 314>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 314>; - max-frequency = <200000000>; - iommus = <&ipmmu_ds1 32>; - status = "disabled"; - }; - - gic: interrupt-controller@f1010000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x0 0xf1010000 0 0x1000>, - <0x0 0xf1020000 0 0x20000>, - <0x0 0xf1040000 0 0x20000>, - <0x0 0xf1060000 0 0x20000>; - interrupts = ; - clocks = <&cpg CPG_MOD 408>; - clock-names = "clk"; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 408>; - }; - - pciec: pcie@fe000000 { - compatible = "renesas,pcie-r8a77980", - "renesas,pcie-rcar-gen3"; - reg = <0 0xfe000000 0 0x80000>; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x00 0xff>; - device_type = "pci"; - ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x0100000>, - <0x02000000 0 0xfe200000 0 0xfe200000 0 0x0200000>, - <0x02000000 0 0x30000000 0 0x30000000 0 0x8000000>, - <0x42000000 0 0x38000000 0 0x38000000 0 0x8000000>; - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; - interrupts = , - , - ; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; - clock-names = "pcie", "pcie_bus"; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 319>; - phys = <&pcie_phy>; - phy-names = "pcie"; - status = "disabled"; - }; - - vspd0: vsp@fea20000 { - compatible = "renesas,vsp2"; - reg = <0 0xfea20000 0 0x5000>; - interrupts = ; - clocks = <&cpg CPG_MOD 623>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 623>; - renesas,fcp = <&fcpvd0>; - }; - - fcpvd0: fcp@fea27000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea27000 0 0x200>; - clocks = <&cpg CPG_MOD 603>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 603>; - }; - - csi40: csi2@feaa0000 { - compatible = "renesas,r8a77980-csi2"; - reg = <0 0xfeaa0000 0 0x10000>; - interrupts = ; - clocks = <&cpg CPG_MOD 716>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 716>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - csi40vin0: endpoint@0 { - reg = <0>; - remote-endpoint = <&vin0csi40>; - }; - csi40vin1: endpoint@1 { - reg = <1>; - remote-endpoint = <&vin1csi40>; - }; - csi40vin2: endpoint@2 { - reg = <2>; - remote-endpoint = <&vin2csi40>; - }; - csi40vin3: endpoint@3 { - reg = <3>; - remote-endpoint = <&vin3csi40>; - }; - }; - }; - }; - - csi41: csi2@feab0000 { - compatible = "renesas,r8a77980-csi2"; - reg = <0 0xfeab0000 0 0x10000>; - interrupts = ; - clocks = <&cpg CPG_MOD 715>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 715>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - csi41vin4: endpoint@0 { - reg = <0>; - remote-endpoint = <&vin4csi41>; - }; - csi41vin5: endpoint@1 { - reg = <1>; - remote-endpoint = <&vin5csi41>; - }; - csi41vin6: endpoint@2 { - reg = <2>; - remote-endpoint = <&vin6csi41>; - }; - csi41vin7: endpoint@3 { - reg = <3>; - remote-endpoint = <&vin7csi41>; - }; - }; - }; - }; - - du: display@feb00000 { - compatible = "renesas,du-r8a77980", - "renesas,du-r8a77970"; - reg = <0 0xfeb00000 0 0x80000>; - interrupts = ; - clocks = <&cpg CPG_MOD 724>; - clock-names = "du.0"; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 724>; - vsps = <&vspd0 0>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - du_out_rgb: endpoint { - }; - }; - - port@1 { - reg = <1>; - du_out_lvds0: endpoint { - remote-endpoint = <&lvds0_in>; - }; - }; - }; - }; - - lvds0: lvds-encoder@feb90000 { - compatible = "renesas,r8a77980-lvds"; - reg = <0 0xfeb90000 0 0x14>; - clocks = <&cpg CPG_MOD 727>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 727>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - lvds0_in: endpoint { - remote-endpoint = - <&du_out_lvds0>; - }; - }; - - port@1 { - reg = <1>; - lvds0_out: endpoint { - }; - }; - }; - }; - - prr: chipid@fff00044 { - compatible = "renesas,prr"; - reg = <0 0xfff00044 0 4>; - }; - }; - - thermal-zones { - thermal-sensor-1 { - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&tsc 0>; - - trips { - sensor1-passive { - temperature = <95000>; - hysteresis = <1000>; - type = "passive"; - }; - sensor1-critical { - temperature = <120000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - thermal-sensor-2 { - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&tsc 1>; - - trips { - sensor2-passive { - temperature = <95000>; - hysteresis = <1000>; - type = "passive"; - }; - sensor2-critical { - temperature = <120000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | - IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | - IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | - IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | - IRQ_TYPE_LEVEL_LOW)>; - }; -}; diff --git a/sys/gnu/dts/arm64/renesas/r8a77990-ebisu.dts b/sys/gnu/dts/arm64/renesas/r8a77990-ebisu.dts deleted file mode 100644 index 4fd2b14fbb8..00000000000 --- a/sys/gnu/dts/arm64/renesas/r8a77990-ebisu.dts +++ /dev/null @@ -1,753 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the ebisu board - * - * Copyright (C) 2018 Renesas Electronics Corp. - */ - -/dts-v1/; -#include "r8a77990.dtsi" -#include - -/ { - model = "Renesas Ebisu board based on r8a77990"; - compatible = "renesas,ebisu", "renesas,r8a77990"; - - aliases { - serial0 = &scif2; - ethernet0 = &avb; - }; - - chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; - stdout-path = "serial0:115200n8"; - }; - - audio_clkout: audio-clkout { - /* - * This is same as <&rcar_sound 0> - * but needed to avoid cs2000/rcar_sound probe dead-lock - */ - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <11289600>; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm3 0 50000>; - - brightness-levels = <512 511 505 494 473 440 392 327 241 133 0>; - default-brightness-level = <10>; - - power-supply = <®_12p0v>; - }; - - cvbs-in { - compatible = "composite-video-connector"; - label = "CVBS IN"; - - port { - cvbs_con: endpoint { - remote-endpoint = <&adv7482_ain7>; - }; - }; - }; - - hdmi-in { - compatible = "hdmi-connector"; - label = "HDMI IN"; - type = "a"; - - port { - hdmi_in_con: endpoint { - remote-endpoint = <&adv7482_hdmi>; - }; - }; - }; - - hdmi-out { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_out: endpoint { - remote-endpoint = <&adv7511_out>; - }; - }; - }; - - lvds-decoder { - compatible = "thine,thc63lvd1024"; - vcc-supply = <®_3p3v>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - thc63lvd1024_in: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - - port@2 { - reg = <2>; - thc63lvd1024_out: endpoint { - remote-endpoint = <&adv7511_in>; - }; - }; - }; - }; - - memory@48000000 { - device_type = "memory"; - /* first 128MB is reserved for secure area. */ - reg = <0x0 0x48000000 0x0 0x38000000>; - }; - - reg_1p8v: regulator0 { - compatible = "regulator-fixed"; - regulator-name = "fixed-1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_3p3v: regulator1 { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_12p0v: regulator2 { - compatible = "regulator-fixed"; - regulator-name = "D12.0V"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-boot-on; - regulator-always-on; - }; - - rsnd_ak4613: sound { - compatible = "simple-audio-card"; - - simple-audio-card,name = "rsnd-ak4613"; - simple-audio-card,format = "left_j"; - simple-audio-card,bitclock-master = <&sndcpu>; - simple-audio-card,frame-master = <&sndcpu>; - - sndcodec: simple-audio-card,codec { - sound-dai = <&ak4613>; - }; - - sndcpu: simple-audio-card,cpu { - sound-dai = <&rcar_sound>; - }; - }; - - vbus0_usb2: regulator-vbus0-usb2 { - compatible = "regulator-fixed"; - - regulator-name = "USB20_VBUS_CN"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - gpio = <&gpio6 4 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vcc_sdhi0: regulator-vcc-sdhi0 { - compatible = "regulator-fixed"; - - regulator-name = "SDHI0 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&gpio5 17 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vccq_sdhi0: regulator-vccq-sdhi0 { - compatible = "regulator-gpio"; - - regulator-name = "SDHI0 VccQ"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>; - gpios-states = <1>; - states = <3300000 1>, <1800000 0>; - }; - - vcc_sdhi1: regulator-vcc-sdhi1 { - compatible = "regulator-fixed"; - - regulator-name = "SDHI1 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vccq_sdhi1: regulator-vccq-sdhi1 { - compatible = "regulator-gpio"; - - regulator-name = "SDHI1 VccQ"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>; - gpios-states = <1>; - states = <3300000 1>, <1800000 0>; - }; - - vga { - compatible = "vga-connector"; - - port { - vga_in: endpoint { - remote-endpoint = <&adv7123_out>; - }; - }; - }; - - vga-encoder { - compatible = "adi,adv7123"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7123_in: endpoint { - remote-endpoint = <&du_out_rgb>; - }; - }; - port@1 { - reg = <1>; - adv7123_out: endpoint { - remote-endpoint = <&vga_in>; - }; - }; - }; - }; - - x12_clk: x12 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24576000>; - }; - - x13_clk: x13 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <74250000>; - }; -}; - -&audio_clk_a { - clock-frequency = <22579200>; -}; - -&avb { - pinctrl-0 = <&avb_pins>; - pinctrl-names = "default"; - phy-handle = <&phy0>; - status = "okay"; - - phy0: ethernet-phy@0 { - rxc-skew-ps = <1500>; - reg = <0>; - interrupt-parent = <&gpio2>; - interrupts = <21 IRQ_TYPE_LEVEL_LOW>; - reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; - /* - * TX clock internal delay mode is required for reliable - * 1Gbps communication using the KSZ9031RNX phy present on - * the Ebisu board, however, TX clock internal delay mode - * isn't supported on r8a77990. Thus, limit speed to - * 100Mbps for reliable communication. - */ - max-speed = <100>; - }; -}; - -&canfd { - pinctrl-0 = <&canfd0_pins>; - pinctrl-names = "default"; - status = "okay"; - - channel0 { - status = "okay"; - }; -}; - -&csi40 { - status = "okay"; - - ports { - port@0 { - reg = <0>; - - csi40_in: endpoint { - clock-lanes = <0>; - data-lanes = <1 2>; - remote-endpoint = <&adv7482_txa>; - }; - }; - }; -}; - -&du { - pinctrl-0 = <&du_pins>; - pinctrl-names = "default"; - status = "okay"; - - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>, - <&x13_clk>; - clock-names = "du.0", "du.1", "dclkin.0"; - - ports { - port@0 { - endpoint { - remote-endpoint = <&adv7123_in>; - }; - }; - }; -}; - -&ehci0 { - dr_mode = "otg"; - status = "okay"; -}; - -&extal_clk { - clock-frequency = <48000000>; -}; - -&hsusb { - dr_mode = "otg"; - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - io_expander: gpio@20 { - compatible = "onnn,pca9654"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&gpio2>; - interrupts = <22 IRQ_TYPE_LEVEL_LOW>; - }; - - hdmi-encoder@39 { - compatible = "adi,adv7511w"; - reg = <0x39>; - interrupt-parent = <&gpio1>; - interrupts = <1 IRQ_TYPE_LEVEL_LOW>; - - adi,input-depth = <8>; - adi,input-colorspace = "rgb"; - adi,input-clock = "1x"; - adi,input-style = <1>; - adi,input-justification = "evenly"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7511_in: endpoint { - remote-endpoint = <&thc63lvd1024_out>; - }; - }; - - port@1 { - reg = <1>; - adv7511_out: endpoint { - remote-endpoint = <&hdmi_con_out>; - }; - }; - }; - }; - - video-receiver@70 { - compatible = "adi,adv7482"; - reg = <0x70>; - - #address-cells = <1>; - #size-cells = <0>; - - interrupt-parent = <&gpio0>; - interrupt-names = "intrq1", "intrq2"; - interrupts = <7 IRQ_TYPE_LEVEL_LOW>, - <17 IRQ_TYPE_LEVEL_LOW>; - - port@7 { - reg = <7>; - - adv7482_ain7: endpoint { - remote-endpoint = <&cvbs_con>; - }; - }; - - port@8 { - reg = <8>; - - adv7482_hdmi: endpoint { - remote-endpoint = <&hdmi_in_con>; - }; - }; - - port@a { - reg = <10>; - - adv7482_txa: endpoint { - clock-lanes = <0>; - data-lanes = <1 2>; - remote-endpoint = <&csi40_in>; - }; - }; - }; -}; - -&i2c3 { - status = "okay"; - - ak4613: codec@10 { - compatible = "asahi-kasei,ak4613"; - #sound-dai-cells = <0>; - reg = <0x10>; - clocks = <&rcar_sound 3>; - - asahi-kasei,in1-single-end; - asahi-kasei,in2-single-end; - asahi-kasei,out1-single-end; - asahi-kasei,out2-single-end; - asahi-kasei,out3-single-end; - asahi-kasei,out4-single-end; - asahi-kasei,out5-single-end; - asahi-kasei,out6-single-end; - }; - - cs2000: clk-multiplier@4f { - #clock-cells = <0>; - compatible = "cirrus,cs2000-cp"; - reg = <0x4f>; - clocks = <&audio_clkout>, <&x12_clk>; - clock-names = "clk_in", "ref_clk"; - - assigned-clocks = <&cs2000>; - assigned-clock-rates = <24576000>; /* 1/1 divide */ - }; -}; - -&i2c_dvfs { - status = "okay"; - - clock-frequency = <400000>; - - pmic: pmic@30 { - pinctrl-0 = <&irq0_pins>; - pinctrl-names = "default"; - - compatible = "rohm,bd9571mwv"; - reg = <0x30>; - interrupt-parent = <&intc_ex>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - rohm,ddr-backup-power = <0x1>; - rohm,rstbmode-level; - }; -}; - -&lvds0 { - status = "okay"; - - clocks = <&cpg CPG_MOD 727>, - <&x13_clk>, - <&extal_clk>; - clock-names = "fck", "dclkin.0", "extal"; - - ports { - port@1 { - lvds0_out: endpoint { - remote-endpoint = <&thc63lvd1024_in>; - }; - }; - }; -}; - -&lvds1 { - /* - * Even though the LVDS1 output is not connected, the encoder must be - * enabled to supply a pixel clock to the DU for the DPAD output when - * LVDS0 is in use. - */ - status = "okay"; - - clocks = <&cpg CPG_MOD 727>, - <&x13_clk>, - <&extal_clk>; - clock-names = "fck", "dclkin.0", "extal"; -}; - -&ohci0 { - dr_mode = "otg"; - status = "okay"; -}; - -&pcie_bus_clk { - clock-frequency = <100000000>; -}; - -&pciec0 { - status = "okay"; -}; - -&pfc { - avb_pins: avb { - mux { - groups = "avb_link", "avb_mii"; - function = "avb"; - }; - }; - - canfd0_pins: canfd0 { - groups = "canfd0_data"; - function = "canfd0"; - }; - - du_pins: du { - groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0"; - function = "du"; - }; - - irq0_pins: irq0 { - groups = "intc_ex_irq0"; - function = "intc_ex"; - }; - - pwm3_pins: pwm3 { - groups = "pwm3_b"; - function = "pwm3"; - }; - - pwm5_pins: pwm5 { - groups = "pwm5_a"; - function = "pwm5"; - }; - - scif2_pins: scif2 { - groups = "scif2_data_a"; - function = "scif2"; - }; - - sdhi0_pins: sd0 { - groups = "sdhi0_data4", "sdhi0_ctrl"; - function = "sdhi0"; - power-source = <3300>; - }; - - sdhi0_pins_uhs: sd0_uhs { - groups = "sdhi0_data4", "sdhi0_ctrl"; - function = "sdhi0"; - power-source = <1800>; - }; - - sdhi1_pins: sd1 { - groups = "sdhi1_data4", "sdhi1_ctrl"; - function = "sdhi1"; - power-source = <3300>; - }; - - sdhi1_pins_uhs: sd1_uhs { - groups = "sdhi1_data4", "sdhi1_ctrl"; - function = "sdhi1"; - power-source = <1800>; - }; - - sdhi3_pins: sd3 { - groups = "sdhi3_data8", "sdhi3_ctrl", "sdhi3_ds"; - function = "sdhi3"; - power-source = <1800>; - }; - - sound_clk_pins: sound_clk { - groups = "audio_clk_a", "audio_clk_b_a", "audio_clk_c_a", - "audio_clkout_a", "audio_clkout1_a"; - function = "audio_clk"; - }; - - sound_pins: sound { - groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data"; - function = "ssi"; - }; - - usb0_pins: usb { - groups = "usb0_b", "usb0_id"; - function = "usb0"; - }; - - usb30_pins: usb30 { - groups = "usb30"; - function = "usb30"; - }; -}; - -&pwm3 { - pinctrl-0 = <&pwm3_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&pwm5 { - pinctrl-0 = <&pwm5_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&rcar_sound { - pinctrl-0 = <&sound_pins &sound_clk_pins>; - pinctrl-names = "default"; - - /* Single DAI */ - #sound-dai-cells = <0>; - - /* audio_clkout0/1/2/3 */ - #clock-cells = <1>; - clock-frequency = <12288000 11289600>; - - status = "okay"; - - /* update to */ - clocks = <&cpg CPG_MOD 1005>, - <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, - <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, - <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, - <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, - <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, - <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, - <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, - <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, - <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, - <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, - <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, - <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, - <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, - <&audio_clk_a>, <&cs2000>, <&audio_clk_c>, - <&cpg CPG_CORE R8A77990_CLK_ZA2>; - - rcar_sound,dai { - dai0 { - playback = <&ssi0 &src0 &dvc0>; - capture = <&ssi1 &src1 &dvc1>; - }; - }; - -}; - -&rwdt { - timeout-sec = <60>; - status = "okay"; -}; - -&scif2 { - pinctrl-0 = <&scif2_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&sdhi0 { - pinctrl-0 = <&sdhi0_pins>; - pinctrl-1 = <&sdhi0_pins_uhs>; - pinctrl-names = "default", "state_uhs"; - - vmmc-supply = <&vcc_sdhi0>; - vqmmc-supply = <&vccq_sdhi0>; - cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; - bus-width = <4>; - sd-uhs-sdr50; - sd-uhs-sdr104; - status = "okay"; -}; - -&sdhi1 { - pinctrl-0 = <&sdhi1_pins>; - pinctrl-1 = <&sdhi1_pins_uhs>; - pinctrl-names = "default", "state_uhs"; - - vmmc-supply = <&vcc_sdhi1>; - vqmmc-supply = <&vccq_sdhi1>; - cd-gpios = <&gpio3 14 GPIO_ACTIVE_LOW>; - bus-width = <4>; - sd-uhs-sdr50; - sd-uhs-sdr104; - status = "okay"; -}; - -&sdhi3 { - /* used for on-board 8bit eMMC */ - pinctrl-0 = <&sdhi3_pins>; - pinctrl-1 = <&sdhi3_pins>; - pinctrl-names = "default", "state_uhs"; - - vmmc-supply = <®_3p3v>; - vqmmc-supply = <®_1p8v>; - mmc-hs200-1_8v; - mmc-hs400-1_8v; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&ssi1 { - shared-pin; -}; - -&usb2_phy0 { - pinctrl-0 = <&usb0_pins>; - pinctrl-names = "default"; - - vbus-supply = <&vbus0_usb2>; - status = "okay"; -}; - -&usb3_peri0 { - companion = <&xhci0>; - status = "okay"; -}; - -&vin4 { - status = "okay"; -}; - -&vin5 { - status = "okay"; -}; - -&xhci0 { - pinctrl-0 = <&usb30_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/renesas/r8a77990.dtsi b/sys/gnu/dts/arm64/renesas/r8a77990.dtsi deleted file mode 100644 index 32d91f21024..00000000000 --- a/sys/gnu/dts/arm64/renesas/r8a77990.dtsi +++ /dev/null @@ -1,1924 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the R-Car E3 (R8A77990) SoC - * - * Copyright (C) 2018-2019 Renesas Electronics Corp. - */ - -#include -#include -#include - -/ { - compatible = "renesas,r8a77990"; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - i2c6 = &i2c6; - i2c7 = &i2c7; - }; - - /* - * The external audio clocks are configured as 0 Hz fixed frequency - * clocks by default. - * Boards that provide audio clocks should override them. - */ - audio_clk_a: audio_clk_a { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - audio_clk_b: audio_clk_b { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - audio_clk_c: audio_clk_c { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - /* External CAN clock - to be overridden by boards that provide it */ - can_clk: can { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - cluster1_opp: opp_table10 { - compatible = "operating-points-v2"; - opp-shared; - opp-800000000 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <820000>; - clock-latency-ns = <300000>; - }; - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <820000>; - clock-latency-ns = <300000>; - }; - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <820000>; - clock-latency-ns = <300000>; - opp-suspend; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - a53_0: cpu@0 { - compatible = "arm,cortex-a53"; - reg = <0>; - device_type = "cpu"; - #cooling-cells = <2>; - power-domains = <&sysc R8A77990_PD_CA53_CPU0>; - next-level-cache = <&L2_CA53>; - enable-method = "psci"; - dynamic-power-coefficient = <277>; - clocks =<&cpg CPG_CORE R8A77990_CLK_Z2>; - operating-points-v2 = <&cluster1_opp>; - }; - - a53_1: cpu@1 { - compatible = "arm,cortex-a53"; - reg = <1>; - device_type = "cpu"; - power-domains = <&sysc R8A77990_PD_CA53_CPU1>; - next-level-cache = <&L2_CA53>; - enable-method = "psci"; - clocks =<&cpg CPG_CORE R8A77990_CLK_Z2>; - operating-points-v2 = <&cluster1_opp>; - }; - - L2_CA53: cache-controller-0 { - compatible = "cache"; - power-domains = <&sysc R8A77990_PD_CA53_SCU>; - cache-unified; - cache-level = <2>; - }; - }; - - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board */ - clock-frequency = <0>; - }; - - /* External PCIe clock - can be overridden by the board */ - pcie_bus_clk: pcie_bus { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - pmu_a53 { - compatible = "arm,cortex-a53-pmu"; - interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&a53_0>, <&a53_1>; - }; - - psci { - compatible = "arm,psci-1.0", "arm,psci-0.2"; - method = "smc"; - }; - - /* External SCIF clock - to be overridden by boards that provide it */ - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - soc: soc { - compatible = "simple-bus"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - rwdt: watchdog@e6020000 { - compatible = "renesas,r8a77990-wdt", - "renesas,rcar-gen3-wdt"; - reg = <0 0xe6020000 0 0x0c>; - clocks = <&cpg CPG_MOD 402>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 402>; - status = "disabled"; - }; - - gpio0: gpio@e6050000 { - compatible = "renesas,gpio-r8a77990", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6050000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 0 18>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 912>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 912>; - }; - - gpio1: gpio@e6051000 { - compatible = "renesas,gpio-r8a77990", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6051000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 32 23>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 911>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 911>; - }; - - gpio2: gpio@e6052000 { - compatible = "renesas,gpio-r8a77990", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6052000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 64 26>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 910>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 910>; - }; - - gpio3: gpio@e6053000 { - compatible = "renesas,gpio-r8a77990", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6053000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 96 16>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 909>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 909>; - }; - - gpio4: gpio@e6054000 { - compatible = "renesas,gpio-r8a77990", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6054000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 128 11>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 908>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 908>; - }; - - gpio5: gpio@e6055000 { - compatible = "renesas,gpio-r8a77990", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6055000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 160 20>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 907>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 907>; - }; - - gpio6: gpio@e6055400 { - compatible = "renesas,gpio-r8a77990", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6055400 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 192 18>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 906>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 906>; - }; - - pfc: pin-controller@e6060000 { - compatible = "renesas,pfc-r8a77990"; - reg = <0 0xe6060000 0 0x508>; - }; - - i2c_dvfs: i2c@e60b0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a77990"; - reg = <0 0xe60b0000 0 0x15>; - interrupts = ; - clocks = <&cpg CPG_MOD 926>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 926>; - dmas = <&dmac0 0x11>, <&dmac0 0x10>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - cmt0: timer@e60f0000 { - compatible = "renesas,r8a77990-cmt0", - "renesas,rcar-gen3-cmt0"; - reg = <0 0xe60f0000 0 0x1004>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 303>; - clock-names = "fck"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 303>; - status = "disabled"; - }; - - cmt1: timer@e6130000 { - compatible = "renesas,r8a77990-cmt1", - "renesas,rcar-gen3-cmt1"; - reg = <0 0xe6130000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 302>; - clock-names = "fck"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 302>; - status = "disabled"; - }; - - cmt2: timer@e6140000 { - compatible = "renesas,r8a77990-cmt1", - "renesas,rcar-gen3-cmt1"; - reg = <0 0xe6140000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 301>; - clock-names = "fck"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 301>; - status = "disabled"; - }; - - cmt3: timer@e6148000 { - compatible = "renesas,r8a77990-cmt1", - "renesas,rcar-gen3-cmt1"; - reg = <0 0xe6148000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 300>; - clock-names = "fck"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 300>; - status = "disabled"; - }; - - cpg: clock-controller@e6150000 { - compatible = "renesas,r8a77990-cpg-mssr"; - reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk>; - clock-names = "extal"; - #clock-cells = <2>; - #power-domain-cells = <0>; - #reset-cells = <1>; - }; - - rst: reset-controller@e6160000 { - compatible = "renesas,r8a77990-rst"; - reg = <0 0xe6160000 0 0x0200>; - }; - - sysc: system-controller@e6180000 { - compatible = "renesas,r8a77990-sysc"; - reg = <0 0xe6180000 0 0x0400>; - #power-domain-cells = <1>; - }; - - thermal: thermal@e6190000 { - compatible = "renesas,thermal-r8a77990"; - reg = <0 0xe6190000 0 0x10>, <0 0xe6190100 0 0x38>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 522>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 522>; - #thermal-sensor-cells = <0>; - }; - - intc_ex: interrupt-controller@e61c0000 { - compatible = "renesas,intc-ex-r8a77990", "renesas,irqc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0 0xe61c0000 0 0x200>; - interrupts = , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 407>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 407>; - }; - - i2c0: i2c@e6500000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a77990", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6500000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 931>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 931>; - dmas = <&dmac1 0x91>, <&dmac1 0x90>, - <&dmac2 0x91>, <&dmac2 0x90>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c1: i2c@e6508000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a77990", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6508000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 930>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 930>; - dmas = <&dmac1 0x93>, <&dmac1 0x92>, - <&dmac2 0x93>, <&dmac2 0x92>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c2: i2c@e6510000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a77990", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6510000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 929>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 929>; - dmas = <&dmac1 0x95>, <&dmac1 0x94>, - <&dmac2 0x95>, <&dmac2 0x94>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c3: i2c@e66d0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a77990", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66d0000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 928>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 928>; - dmas = <&dmac0 0x97>, <&dmac0 0x96>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c4: i2c@e66d8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a77990", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66d8000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 927>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 927>; - dmas = <&dmac0 0x99>, <&dmac0 0x98>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c5: i2c@e66e0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a77990", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66e0000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 919>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 919>; - dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c6: i2c@e66e8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a77990", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66e8000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 918>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 918>; - dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c7: i2c@e6690000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a77990", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6690000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 1003>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 1003>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - hscif0: serial@e6540000 { - compatible = "renesas,hscif-r8a77990", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6540000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 520>, - <&cpg CPG_CORE R8A77990_CLK_S3D1C>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x31>, <&dmac1 0x30>, - <&dmac2 0x31>, <&dmac2 0x30>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 520>; - status = "disabled"; - }; - - hscif1: serial@e6550000 { - compatible = "renesas,hscif-r8a77990", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6550000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 519>, - <&cpg CPG_CORE R8A77990_CLK_S3D1C>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x33>, <&dmac1 0x32>, - <&dmac2 0x33>, <&dmac2 0x32>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 519>; - status = "disabled"; - }; - - hscif2: serial@e6560000 { - compatible = "renesas,hscif-r8a77990", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6560000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 518>, - <&cpg CPG_CORE R8A77990_CLK_S3D1C>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x35>, <&dmac1 0x34>, - <&dmac2 0x35>, <&dmac2 0x34>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 518>; - status = "disabled"; - }; - - hscif3: serial@e66a0000 { - compatible = "renesas,hscif-r8a77990", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe66a0000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 517>, - <&cpg CPG_CORE R8A77990_CLK_S3D1C>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x37>, <&dmac0 0x36>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 517>; - status = "disabled"; - }; - - hscif4: serial@e66b0000 { - compatible = "renesas,hscif-r8a77990", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe66b0000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 516>, - <&cpg CPG_CORE R8A77990_CLK_S3D1C>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x39>, <&dmac0 0x38>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 516>; - status = "disabled"; - }; - - hsusb: usb@e6590000 { - compatible = "renesas,usbhs-r8a77990", - "renesas,rcar-gen3-usbhs"; - reg = <0 0xe6590000 0 0x200>; - interrupts = ; - clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>; - dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, - <&usb_dmac1 0>, <&usb_dmac1 1>; - dma-names = "ch0", "ch1", "ch2", "ch3"; - renesas,buswait = <11>; - phys = <&usb2_phy0 3>; - phy-names = "usb"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 704>, <&cpg 703>; - status = "disabled"; - }; - - usb_dmac0: dma-controller@e65a0000 { - compatible = "renesas,r8a77990-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65a0000 0 0x100>; - interrupts = , - ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 330>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 330>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - usb_dmac1: dma-controller@e65b0000 { - compatible = "renesas,r8a77990-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65b0000 0 0x100>; - interrupts = , - ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 331>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 331>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - dmac0: dma-controller@e6700000 { - compatible = "renesas,dmac-r8a77990", - "renesas,rcar-dmac"; - reg = <0 0xe6700000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 219>; - clock-names = "fck"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 219>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, - <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, - <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, - <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, - <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, - <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, - <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, - <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; - }; - - dmac1: dma-controller@e7300000 { - compatible = "renesas,dmac-r8a77990", - "renesas,rcar-dmac"; - reg = <0 0xe7300000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 218>; - clock-names = "fck"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 218>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, - <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, - <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, - <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, - <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, - <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, - <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, - <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; - }; - - dmac2: dma-controller@e7310000 { - compatible = "renesas,dmac-r8a77990", - "renesas,rcar-dmac"; - reg = <0 0xe7310000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 217>; - clock-names = "fck"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 217>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, - <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, - <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, - <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, - <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, - <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, - <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, - <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; - }; - - ipmmu_ds0: mmu@e6740000 { - compatible = "renesas,ipmmu-r8a77990"; - reg = <0 0xe6740000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 0>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_ds1: mmu@e7740000 { - compatible = "renesas,ipmmu-r8a77990"; - reg = <0 0xe7740000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 1>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_hc: mmu@e6570000 { - compatible = "renesas,ipmmu-r8a77990"; - reg = <0 0xe6570000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 2>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_mm: mmu@e67b0000 { - compatible = "renesas,ipmmu-r8a77990"; - reg = <0 0xe67b0000 0 0x1000>; - interrupts = , - ; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_mp: mmu@ec670000 { - compatible = "renesas,ipmmu-r8a77990"; - reg = <0 0xec670000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 4>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_pv0: mmu@fd800000 { - compatible = "renesas,ipmmu-r8a77990"; - reg = <0 0xfd800000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 6>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_rt: mmu@ffc80000 { - compatible = "renesas,ipmmu-r8a77990"; - reg = <0 0xffc80000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 10>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_vc0: mmu@fe6b0000 { - compatible = "renesas,ipmmu-r8a77990"; - reg = <0 0xfe6b0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 12>; - power-domains = <&sysc R8A77990_PD_A3VC>; - #iommu-cells = <1>; - }; - - ipmmu_vi0: mmu@febd0000 { - compatible = "renesas,ipmmu-r8a77990"; - reg = <0 0xfebd0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 14>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_vp0: mmu@fe990000 { - compatible = "renesas,ipmmu-r8a77990"; - reg = <0 0xfe990000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 16>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - avb: ethernet@e6800000 { - compatible = "renesas,etheravb-r8a77990", - "renesas,etheravb-rcar-gen3"; - reg = <0 0xe6800000 0 0x800>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15", - "ch16", "ch17", "ch18", "ch19", - "ch20", "ch21", "ch22", "ch23", - "ch24"; - clocks = <&cpg CPG_MOD 812>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 812>; - phy-mode = "rgmii"; - iommus = <&ipmmu_ds0 16>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - can0: can@e6c30000 { - compatible = "renesas,can-r8a77990", - "renesas,rcar-gen3-can"; - reg = <0 0xe6c30000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 916>, - <&cpg CPG_CORE R8A77990_CLK_CANFD>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A77990_CLK_CANFD>; - assigned-clock-rates = <40000000>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 916>; - status = "disabled"; - }; - - can1: can@e6c38000 { - compatible = "renesas,can-r8a77990", - "renesas,rcar-gen3-can"; - reg = <0 0xe6c38000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 915>, - <&cpg CPG_CORE R8A77990_CLK_CANFD>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A77990_CLK_CANFD>; - assigned-clock-rates = <40000000>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 915>; - status = "disabled"; - }; - - canfd: can@e66c0000 { - compatible = "renesas,r8a77990-canfd", - "renesas,rcar-gen3-canfd"; - reg = <0 0xe66c0000 0 0x8000>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 914>, - <&cpg CPG_CORE R8A77990_CLK_CANFD>, - <&can_clk>; - clock-names = "fck", "canfd", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A77990_CLK_CANFD>; - assigned-clock-rates = <40000000>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 914>; - status = "disabled"; - - channel0 { - status = "disabled"; - }; - - channel1 { - status = "disabled"; - }; - }; - - pwm0: pwm@e6e30000 { - compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar"; - reg = <0 0xe6e30000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm1: pwm@e6e31000 { - compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar"; - reg = <0 0xe6e31000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm2: pwm@e6e32000 { - compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar"; - reg = <0 0xe6e32000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm3: pwm@e6e33000 { - compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar"; - reg = <0 0xe6e33000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm4: pwm@e6e34000 { - compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar"; - reg = <0 0xe6e34000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm5: pwm@e6e35000 { - compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar"; - reg = <0 0xe6e35000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm6: pwm@e6e36000 { - compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar"; - reg = <0 0xe6e36000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - scif0: serial@e6e60000 { - compatible = "renesas,scif-r8a77990", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e60000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 207>, - <&cpg CPG_CORE R8A77990_CLK_S3D1C>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x51>, <&dmac1 0x50>, - <&dmac2 0x51>, <&dmac2 0x50>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 207>; - status = "disabled"; - }; - - scif1: serial@e6e68000 { - compatible = "renesas,scif-r8a77990", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e68000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 206>, - <&cpg CPG_CORE R8A77990_CLK_S3D1C>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x53>, <&dmac1 0x52>, - <&dmac2 0x53>, <&dmac2 0x52>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 206>; - status = "disabled"; - }; - - scif2: serial@e6e88000 { - compatible = "renesas,scif-r8a77990", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e88000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 310>, - <&cpg CPG_CORE R8A77990_CLK_S3D1C>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x13>, <&dmac1 0x12>, - <&dmac2 0x13>, <&dmac2 0x12>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 310>; - status = "disabled"; - }; - - scif3: serial@e6c50000 { - compatible = "renesas,scif-r8a77990", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6c50000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 204>, - <&cpg CPG_CORE R8A77990_CLK_S3D1C>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x57>, <&dmac0 0x56>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 204>; - status = "disabled"; - }; - - scif4: serial@e6c40000 { - compatible = "renesas,scif-r8a77990", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6c40000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 203>, - <&cpg CPG_CORE R8A77990_CLK_S3D1C>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x59>, <&dmac0 0x58>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 203>; - status = "disabled"; - }; - - scif5: serial@e6f30000 { - compatible = "renesas,scif-r8a77990", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6f30000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 202>, - <&cpg CPG_CORE R8A77990_CLK_S3D1C>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x5b>, <&dmac0 0x5a>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 202>; - status = "disabled"; - }; - - msiof0: spi@e6e90000 { - compatible = "renesas,msiof-r8a77990", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6e90000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 211>; - dmas = <&dmac1 0x41>, <&dmac1 0x40>, - <&dmac2 0x41>, <&dmac2 0x40>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 211>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof1: spi@e6ea0000 { - compatible = "renesas,msiof-r8a77990", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6ea0000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 210>; - dmas = <&dmac1 0x43>, <&dmac1 0x42>, - <&dmac2 0x43>, <&dmac2 0x42>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 210>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof2: spi@e6c00000 { - compatible = "renesas,msiof-r8a77990", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6c00000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 209>; - dmas = <&dmac0 0x45>, <&dmac0 0x44>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 209>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof3: spi@e6c10000 { - compatible = "renesas,msiof-r8a77990", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6c10000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 208>; - dmas = <&dmac0 0x47>, <&dmac0 0x46>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 208>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - vin4: video@e6ef4000 { - compatible = "renesas,vin-r8a77990"; - reg = <0 0xe6ef4000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 807>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 807>; - renesas,id = <4>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin4csi40: endpoint@2 { - reg = <2>; - remote-endpoint= <&csi40vin4>; - }; - }; - }; - }; - - vin5: video@e6ef5000 { - compatible = "renesas,vin-r8a77990"; - reg = <0 0xe6ef5000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 806>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 806>; - renesas,id = <5>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin5csi40: endpoint@2 { - reg = <2>; - remote-endpoint= <&csi40vin5>; - }; - }; - }; - }; - - rcar_sound: sound@ec500000 { - /* - * #sound-dai-cells is required - * - * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; - * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; - */ - /* - * #clock-cells is required for audio_clkout0/1/2/3 - * - * clkout : #clock-cells = <0>; <&rcar_sound>; - * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; - */ - compatible = "renesas,rcar_sound-r8a77990", "renesas,rcar_sound-gen3"; - reg = <0 0xec500000 0 0x1000>, /* SCU */ - <0 0xec5a0000 0 0x100>, /* ADG */ - <0 0xec540000 0 0x1000>, /* SSIU */ - <0 0xec541000 0 0x280>, /* SSI */ - <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ - reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; - - clocks = <&cpg CPG_MOD 1005>, - <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, - <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, - <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, - <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, - <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, - <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, - <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, - <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, - <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, - <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, - <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, - <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, - <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, - <&audio_clk_a>, <&audio_clk_b>, - <&audio_clk_c>, - <&cpg CPG_CORE R8A77990_CLK_ZA2>; - clock-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", - "ssi.5", "ssi.4", "ssi.3", "ssi.2", - "ssi.1", "ssi.0", - "src.9", "src.8", "src.7", "src.6", - "src.5", "src.4", "src.3", "src.2", - "src.1", "src.0", - "mix.1", "mix.0", - "ctu.1", "ctu.0", - "dvc.0", "dvc.1", - "clk_a", "clk_b", "clk_c", "clk_i"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 1005>, - <&cpg 1006>, <&cpg 1007>, - <&cpg 1008>, <&cpg 1009>, - <&cpg 1010>, <&cpg 1011>, - <&cpg 1012>, <&cpg 1013>, - <&cpg 1014>, <&cpg 1015>; - reset-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", - "ssi.5", "ssi.4", "ssi.3", "ssi.2", - "ssi.1", "ssi.0"; - status = "disabled"; - - rcar_sound,ctu { - ctu00: ctu-0 { }; - ctu01: ctu-1 { }; - ctu02: ctu-2 { }; - ctu03: ctu-3 { }; - ctu10: ctu-4 { }; - ctu11: ctu-5 { }; - ctu12: ctu-6 { }; - ctu13: ctu-7 { }; - }; - - rcar_sound,dvc { - dvc0: dvc-0 { - dmas = <&audma0 0xbc>; - dma-names = "tx"; - }; - dvc1: dvc-1 { - dmas = <&audma0 0xbe>; - dma-names = "tx"; - }; - }; - - rcar_sound,mix { - mix0: mix-0 { }; - mix1: mix-1 { }; - }; - - rcar_sound,src { - src0: src-0 { - interrupts = ; - dmas = <&audma0 0x85>, <&audma0 0x9a>; - dma-names = "rx", "tx"; - }; - src1: src-1 { - interrupts = ; - dmas = <&audma0 0x87>, <&audma0 0x9c>; - dma-names = "rx", "tx"; - }; - src2: src-2 { - interrupts = ; - dmas = <&audma0 0x89>, <&audma0 0x9e>; - dma-names = "rx", "tx"; - }; - src3: src-3 { - interrupts = ; - dmas = <&audma0 0x8b>, <&audma0 0xa0>; - dma-names = "rx", "tx"; - }; - src4: src-4 { - interrupts = ; - dmas = <&audma0 0x8d>, <&audma0 0xb0>; - dma-names = "rx", "tx"; - }; - src5: src-5 { - interrupts = ; - dmas = <&audma0 0x8f>, <&audma0 0xb2>; - dma-names = "rx", "tx"; - }; - src6: src-6 { - interrupts = ; - dmas = <&audma0 0x91>, <&audma0 0xb4>; - dma-names = "rx", "tx"; - }; - src7: src-7 { - interrupts = ; - dmas = <&audma0 0x93>, <&audma0 0xb6>; - dma-names = "rx", "tx"; - }; - src8: src-8 { - interrupts = ; - dmas = <&audma0 0x95>, <&audma0 0xb8>; - dma-names = "rx", "tx"; - }; - src9: src-9 { - interrupts = ; - dmas = <&audma0 0x97>, <&audma0 0xba>; - dma-names = "rx", "tx"; - }; - }; - - rcar_sound,ssi { - ssi0: ssi-0 { - interrupts = ; - dmas = <&audma0 0x01>, <&audma0 0x02>, - <&audma0 0x15>, <&audma0 0x16>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi1: ssi-1 { - interrupts = ; - dmas = <&audma0 0x03>, <&audma0 0x04>, - <&audma0 0x49>, <&audma0 0x4a>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi2: ssi-2 { - interrupts = ; - dmas = <&audma0 0x05>, <&audma0 0x06>, - <&audma0 0x63>, <&audma0 0x64>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi3: ssi-3 { - interrupts = ; - dmas = <&audma0 0x07>, <&audma0 0x08>, - <&audma0 0x6f>, <&audma0 0x70>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi4: ssi-4 { - interrupts = ; - dmas = <&audma0 0x09>, <&audma0 0x0a>, - <&audma0 0x71>, <&audma0 0x72>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi5: ssi-5 { - interrupts = ; - dmas = <&audma0 0x0b>, <&audma0 0x0c>, - <&audma0 0x73>, <&audma0 0x74>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi6: ssi-6 { - interrupts = ; - dmas = <&audma0 0x0d>, <&audma0 0x0e>, - <&audma0 0x75>, <&audma0 0x76>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi7: ssi-7 { - interrupts = ; - dmas = <&audma0 0x0f>, <&audma0 0x10>, - <&audma0 0x79>, <&audma0 0x7a>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi8: ssi-8 { - interrupts = ; - dmas = <&audma0 0x11>, <&audma0 0x12>, - <&audma0 0x7b>, <&audma0 0x7c>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi9: ssi-9 { - interrupts = ; - dmas = <&audma0 0x13>, <&audma0 0x14>, - <&audma0 0x7d>, <&audma0 0x7e>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - }; - }; - - audma0: dma-controller@ec700000 { - compatible = "renesas,dmac-r8a77990", - "renesas,rcar-dmac"; - reg = <0 0xec700000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 502>; - clock-names = "fck"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 502>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>, - <&ipmmu_mp 2>, <&ipmmu_mp 3>, - <&ipmmu_mp 4>, <&ipmmu_mp 5>, - <&ipmmu_mp 6>, <&ipmmu_mp 7>, - <&ipmmu_mp 8>, <&ipmmu_mp 9>, - <&ipmmu_mp 10>, <&ipmmu_mp 11>, - <&ipmmu_mp 12>, <&ipmmu_mp 13>, - <&ipmmu_mp 14>, <&ipmmu_mp 15>; - }; - - xhci0: usb@ee000000 { - compatible = "renesas,xhci-r8a77990", - "renesas,rcar-gen3-xhci"; - reg = <0 0xee000000 0 0xc00>; - interrupts = ; - clocks = <&cpg CPG_MOD 328>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 328>; - status = "disabled"; - }; - - usb3_peri0: usb@ee020000 { - compatible = "renesas,r8a77990-usb3-peri", - "renesas,rcar-gen3-usb3-peri"; - reg = <0 0xee020000 0 0x400>; - interrupts = ; - clocks = <&cpg CPG_MOD 328>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 328>; - status = "disabled"; - }; - - ohci0: usb@ee080000 { - compatible = "generic-ohci"; - reg = <0 0xee080000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; - phys = <&usb2_phy0 1>; - phy-names = "usb"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 703>, <&cpg 704>; - status = "disabled"; - }; - - ehci0: usb@ee080100 { - compatible = "generic-ehci"; - reg = <0 0xee080100 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; - phys = <&usb2_phy0 2>; - phy-names = "usb"; - companion = <&ohci0>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 703>, <&cpg 704>; - status = "disabled"; - }; - - usb2_phy0: usb-phy@ee080200 { - compatible = "renesas,usb2-phy-r8a77990", - "renesas,rcar-gen3-usb2-phy"; - reg = <0 0xee080200 0 0x700>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 703>, <&cpg 704>; - #phy-cells = <1>; - status = "disabled"; - }; - - sdhi0: sd@ee100000 { - compatible = "renesas,sdhi-r8a77990", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee100000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 314>; - max-frequency = <200000000>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 314>; - iommus = <&ipmmu_ds1 32>; - status = "disabled"; - }; - - sdhi1: sd@ee120000 { - compatible = "renesas,sdhi-r8a77990", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee120000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 313>; - max-frequency = <200000000>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 313>; - iommus = <&ipmmu_ds1 33>; - status = "disabled"; - }; - - sdhi3: sd@ee160000 { - compatible = "renesas,sdhi-r8a77990", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee160000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 311>; - max-frequency = <200000000>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 311>; - iommus = <&ipmmu_ds1 35>; - status = "disabled"; - }; - - gic: interrupt-controller@f1010000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x0 0xf1010000 0 0x1000>, - <0x0 0xf1020000 0 0x20000>, - <0x0 0xf1040000 0 0x20000>, - <0x0 0xf1060000 0 0x20000>; - interrupts = ; - clocks = <&cpg CPG_MOD 408>; - clock-names = "clk"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 408>; - }; - - pciec0: pcie@fe000000 { - compatible = "renesas,pcie-r8a77990", - "renesas,pcie-rcar-gen3"; - reg = <0 0xfe000000 0 0x80000>; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x00 0xff>; - device_type = "pci"; - ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, - <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, - <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, - <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>; - interrupts = , - , - ; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; - clock-names = "pcie", "pcie_bus"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 319>; - status = "disabled"; - }; - - vspb0: vsp@fe960000 { - compatible = "renesas,vsp2"; - reg = <0 0xfe960000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 626>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 626>; - renesas,fcp = <&fcpvb0>; - }; - - fcpvb0: fcp@fe96f000 { - compatible = "renesas,fcpv"; - reg = <0 0xfe96f000 0 0x200>; - clocks = <&cpg CPG_MOD 607>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 607>; - iommus = <&ipmmu_vp0 5>; - }; - - vspi0: vsp@fe9a0000 { - compatible = "renesas,vsp2"; - reg = <0 0xfe9a0000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 631>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 631>; - renesas,fcp = <&fcpvi0>; - }; - - fcpvi0: fcp@fe9af000 { - compatible = "renesas,fcpv"; - reg = <0 0xfe9af000 0 0x200>; - clocks = <&cpg CPG_MOD 611>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 611>; - iommus = <&ipmmu_vp0 8>; - }; - - vspd0: vsp@fea20000 { - compatible = "renesas,vsp2"; - reg = <0 0xfea20000 0 0x7000>; - interrupts = ; - clocks = <&cpg CPG_MOD 623>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 623>; - renesas,fcp = <&fcpvd0>; - }; - - fcpvd0: fcp@fea27000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea27000 0 0x200>; - clocks = <&cpg CPG_MOD 603>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 603>; - iommus = <&ipmmu_vi0 8>; - }; - - vspd1: vsp@fea28000 { - compatible = "renesas,vsp2"; - reg = <0 0xfea28000 0 0x7000>; - interrupts = ; - clocks = <&cpg CPG_MOD 622>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 622>; - renesas,fcp = <&fcpvd1>; - }; - - fcpvd1: fcp@fea2f000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea2f000 0 0x200>; - clocks = <&cpg CPG_MOD 602>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 602>; - iommus = <&ipmmu_vi0 9>; - }; - - cmm0: cmm@fea40000 { - compatible = "renesas,r8a77990-cmm", - "renesas,rcar-gen3-cmm"; - reg = <0 0xfea40000 0 0x1000>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - clocks = <&cpg CPG_MOD 711>; - resets = <&cpg 711>; - }; - - cmm1: cmm@fea50000 { - compatible = "renesas,r8a77990-cmm", - "renesas,rcar-gen3-cmm"; - reg = <0 0xfea50000 0 0x1000>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - clocks = <&cpg CPG_MOD 710>; - resets = <&cpg 710>; - }; - - csi40: csi2@feaa0000 { - compatible = "renesas,r8a77990-csi2"; - reg = <0 0xfeaa0000 0 0x10000>; - interrupts = ; - clocks = <&cpg CPG_MOD 716>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 716>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - csi40vin4: endpoint@0 { - reg = <0>; - remote-endpoint = <&vin4csi40>; - }; - csi40vin5: endpoint@1 { - reg = <1>; - remote-endpoint = <&vin5csi40>; - }; - }; - }; - }; - - du: display@feb00000 { - compatible = "renesas,du-r8a77990"; - reg = <0 0xfeb00000 0 0x40000>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>; - clock-names = "du.0", "du.1"; - resets = <&cpg 724>; - reset-names = "du.0"; - - renesas,cmms = <&cmm0>, <&cmm1>; - vsps = <&vspd0 0>, <&vspd1 0>; - - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - du_out_rgb: endpoint { - }; - }; - - port@1 { - reg = <1>; - du_out_lvds0: endpoint { - remote-endpoint = <&lvds0_in>; - }; - }; - - port@2 { - reg = <2>; - du_out_lvds1: endpoint { - remote-endpoint = <&lvds1_in>; - }; - }; - }; - }; - - lvds0: lvds-encoder@feb90000 { - compatible = "renesas,r8a77990-lvds"; - reg = <0 0xfeb90000 0 0x20>; - clocks = <&cpg CPG_MOD 727>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 727>; - status = "disabled"; - - renesas,companion = <&lvds1>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - lvds0_in: endpoint { - remote-endpoint = <&du_out_lvds0>; - }; - }; - - port@1 { - reg = <1>; - lvds0_out: endpoint { - }; - }; - }; - }; - - lvds1: lvds-encoder@feb90100 { - compatible = "renesas,r8a77990-lvds"; - reg = <0 0xfeb90100 0 0x20>; - clocks = <&cpg CPG_MOD 727>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 726>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - lvds1_in: endpoint { - remote-endpoint = <&du_out_lvds1>; - }; - }; - - port@1 { - reg = <1>; - lvds1_out: endpoint { - }; - }; - }; - }; - - prr: chipid@fff00044 { - compatible = "renesas,prr"; - reg = <0 0xfff00044 0 4>; - }; - }; - - thermal-zones { - cpu-thermal { - polling-delay-passive = <250>; - polling-delay = <0>; - thermal-sensors = <&thermal 0>; - sustainable-power = <717>; - - cooling-maps { - map0 { - trip = <&target>; - cooling-device = <&a53_0 0 2>; - contribution = <1024>; - }; - }; - - trips { - sensor1_crit: sensor1-crit { - temperature = <120000>; - hysteresis = <2000>; - type = "critical"; - }; - - target: trip-point1 { - temperature = <100000>; - hysteresis = <2000>; - type = "passive"; - }; - }; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; - }; -}; diff --git a/sys/gnu/dts/arm64/renesas/r8a77995-draak.dts b/sys/gnu/dts/arm64/renesas/r8a77995-draak.dts deleted file mode 100644 index 67634cb01d6..00000000000 --- a/sys/gnu/dts/arm64/renesas/r8a77995-draak.dts +++ /dev/null @@ -1,528 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the Draak board - * - * Copyright (C) 2016-2018 Renesas Electronics Corp. - * Copyright (C) 2017 Glider bvba - */ - -/dts-v1/; -#include "r8a77995.dtsi" -#include - -/ { - model = "Renesas Draak board based on r8a77995"; - compatible = "renesas,draak", "renesas,r8a77995"; - - aliases { - serial0 = &scif2; - ethernet0 = &avb; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 50000>; - - brightness-levels = <512 511 505 494 473 440 392 327 241 133 0>; - default-brightness-level = <10>; - - power-supply = <®_12p0v>; - enable-gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>; - }; - - chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; - stdout-path = "serial0:115200n8"; - }; - - composite-in { - compatible = "composite-video-connector"; - - port { - composite_con_in: endpoint { - remote-endpoint = <&adv7180_in>; - }; - }; - }; - - hdmi-in { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&adv7612_in>; - }; - }; - }; - - hdmi-out { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_out: endpoint { - remote-endpoint = <&adv7511_out>; - }; - }; - }; - - lvds-decoder { - compatible = "thine,thc63lvd1024"; - vcc-supply = <®_3p3v>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - thc63lvd1024_in: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - - port@2 { - reg = <2>; - thc63lvd1024_out: endpoint { - remote-endpoint = <&adv7511_in>; - }; - }; - }; - }; - - memory@48000000 { - device_type = "memory"; - /* first 128MB is reserved for secure area. */ - reg = <0x0 0x48000000 0x0 0x18000000>; - }; - - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-name = "fixed-1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_12p0v: regulator-12p0v { - compatible = "regulator-fixed"; - regulator-name = "D12.0V"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-boot-on; - regulator-always-on; - }; - - vga { - compatible = "vga-connector"; - - port { - vga_in: endpoint { - remote-endpoint = <&adv7123_out>; - }; - }; - }; - - vga-encoder { - compatible = "adi,adv7123"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7123_in: endpoint { - remote-endpoint = <&du_out_rgb>; - }; - }; - port@1 { - reg = <1>; - adv7123_out: endpoint { - remote-endpoint = <&vga_in>; - }; - }; - }; - }; - - x12_clk: x12 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <74250000>; - }; -}; - -&avb { - pinctrl-0 = <&avb0_pins>; - pinctrl-names = "default"; - renesas,no-ether-link; - phy-handle = <&phy0>; - status = "okay"; - - phy0: ethernet-phy@0 { - rxc-skew-ps = <1500>; - reg = <0>; - interrupt-parent = <&gpio5>; - interrupts = <19 IRQ_TYPE_LEVEL_LOW>; - /* - * TX clock internal delay mode is required for reliable - * 1Gbps communication using the KSZ9031RNX phy present on - * the Draak board, however, TX clock internal delay mode - * isn't supported on r8a77995. Thus, limit speed to - * 100Mbps for reliable communication. - */ - max-speed = <100>; - }; -}; - -&can0 { - pinctrl-0 = <&can0_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&can1 { - pinctrl-0 = <&can1_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&du { - pinctrl-0 = <&du_pins>; - pinctrl-names = "default"; - status = "okay"; - - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>, - <&x12_clk>; - clock-names = "du.0", "du.1", "dclkin.0"; - - ports { - port@0 { - endpoint { - remote-endpoint = <&adv7123_in>; - }; - }; - }; -}; - -&ehci0 { - dr_mode = "host"; - status = "okay"; -}; - -&extal_clk { - clock-frequency = <48000000>; -}; - -&hsusb { - dr_mode = "host"; - status = "okay"; -}; - -&i2c0 { - pinctrl-0 = <&i2c0_pins>; - pinctrl-names = "default"; - status = "okay"; - - composite-in@20 { - compatible = "adi,adv7180cp"; - reg = <0x20>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7180_in: endpoint { - remote-endpoint = <&composite_con_in>; - }; - }; - - port@3 { - reg = <3>; - - /* - * The VIN4 video input path is shared between - * CVBS and HDMI inputs through SW[49-53] - * switches. - * - * CVBS is the default selection, link it to - * VIN4 here. - */ - adv7180_out: endpoint { - remote-endpoint = <&vin4_in>; - }; - }; - }; - - }; - - hdmi-encoder@39 { - compatible = "adi,adv7511w"; - reg = <0x39>, <0x3f>, <0x38>, <0x3c>; - reg-names = "main", "edid", "packet", "cec"; - interrupt-parent = <&gpio1>; - interrupts = <28 IRQ_TYPE_LEVEL_LOW>; - - /* Depends on LVDS */ - max-clock = <135000000>; - min-vrefresh = <50>; - - adi,input-depth = <8>; - adi,input-colorspace = "rgb"; - adi,input-clock = "1x"; - adi,input-style = <1>; - adi,input-justification = "evenly"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7511_in: endpoint { - remote-endpoint = <&thc63lvd1024_out>; - }; - }; - - port@1 { - reg = <1>; - adv7511_out: endpoint { - remote-endpoint = <&hdmi_con_out>; - }; - }; - }; - }; - - hdmi-decoder@4c { - compatible = "adi,adv7612"; - reg = <0x4c>; - default-input = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - adv7612_in: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; - }; - - port@2 { - reg = <2>; - - /* - * The VIN4 video input path is shared between - * CVBS and HDMI inputs through SW[49-53] - * switches. - * - * CVBS is the default selection, leave HDMI - * not connected here. - */ - adv7612_out: endpoint { - pclk-sample = <0>; - hsync-active = <0>; - vsync-active = <0>; - }; - }; - }; - }; - - eeprom@50 { - compatible = "rohm,br24t01", "atmel,24c01"; - reg = <0x50>; - pagesize = <8>; - }; -}; - -&i2c1 { - pinctrl-0 = <&i2c1_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&lvds0 { - status = "okay"; - - clocks = <&cpg CPG_MOD 727>, - <&x12_clk>, - <&extal_clk>; - clock-names = "fck", "dclkin.0", "extal"; - - ports { - port@1 { - lvds0_out: endpoint { - remote-endpoint = <&thc63lvd1024_in>; - }; - }; - }; -}; - -&lvds1 { - /* - * Even though the LVDS1 output is not connected, the encoder must be - * enabled to supply a pixel clock to the DU for the DPAD output when - * LVDS0 is in use. - */ - status = "okay"; - - clocks = <&cpg CPG_MOD 727>, - <&x12_clk>, - <&extal_clk>; - clock-names = "fck", "dclkin.0", "extal"; -}; - -&ohci0 { - dr_mode = "host"; - status = "okay"; -}; - -&pfc { - avb0_pins: avb { - mux { - groups = "avb0_link", "avb0_mdio", "avb0_mii"; - function = "avb0"; - }; - }; - - can0_pins: can0 { - groups = "can0_data_a"; - function = "can0"; - }; - - can1_pins: can1 { - groups = "can1_data_a"; - function = "can1"; - }; - - du_pins: du { - groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0"; - function = "du"; - }; - - i2c0_pins: i2c0 { - groups = "i2c0"; - function = "i2c0"; - }; - - i2c1_pins: i2c1 { - groups = "i2c1"; - function = "i2c1"; - }; - - pwm0_pins: pwm0 { - groups = "pwm0_c"; - function = "pwm0"; - }; - - pwm1_pins: pwm1 { - groups = "pwm1_c"; - function = "pwm1"; - }; - - scif2_pins: scif2 { - groups = "scif2_data"; - function = "scif2"; - }; - - sdhi2_pins: sd2 { - groups = "mmc_data8", "mmc_ctrl"; - function = "mmc"; - power-source = <1800>; - }; - - sdhi2_pins_uhs: sd2_uhs { - groups = "mmc_data8", "mmc_ctrl"; - function = "mmc"; - power-source = <1800>; - }; - - usb0_pins: usb0 { - groups = "usb0"; - function = "usb0"; - }; - - vin4_pins_cvbs: vin4 { - groups = "vin4_data8", "vin4_sync", "vin4_clk"; - function = "vin4"; - }; -}; - -&pwm0 { - pinctrl-0 = <&pwm0_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&pwm1 { - pinctrl-0 = <&pwm1_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&rwdt { - timeout-sec = <60>; - status = "okay"; -}; - -&scif2 { - pinctrl-0 = <&scif2_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&sdhi2 { - /* used for on-board eMMC */ - pinctrl-0 = <&sdhi2_pins>; - pinctrl-1 = <&sdhi2_pins_uhs>; - pinctrl-names = "default", "state_uhs"; - - vmmc-supply = <®_3p3v>; - vqmmc-supply = <®_1p8v>; - bus-width = <8>; - mmc-hs200-1_8v; - non-removable; - status = "okay"; -}; - -&usb2_phy0 { - pinctrl-0 = <&usb0_pins>; - pinctrl-names = "default"; - - renesas,no-otg-pins; - status = "okay"; -}; - -&vin4 { - pinctrl-0 = <&vin4_pins_cvbs>; - pinctrl-names = "default"; - - status = "okay"; - - ports { - port { - vin4_in: endpoint { - remote-endpoint = <&adv7180_out>; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/renesas/r8a77995.dtsi b/sys/gnu/dts/arm64/renesas/r8a77995.dtsi deleted file mode 100644 index 9503007c34c..00000000000 --- a/sys/gnu/dts/arm64/renesas/r8a77995.dtsi +++ /dev/null @@ -1,1145 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the R-Car D3 (R8A77995) SoC - * - * Copyright (C) 2016 Renesas Electronics Corp. - * Copyright (C) 2017 Glider bvba - */ - -#include -#include -#include - -/ { - compatible = "renesas,r8a77995"; - #address-cells = <2>; - #size-cells = <2>; - - /* External CAN clock - to be overridden by boards that provide it */ - can_clk: can { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - a53_0: cpu@0 { - compatible = "arm,cortex-a53"; - reg = <0x0>; - device_type = "cpu"; - power-domains = <&sysc R8A77995_PD_CA53_CPU0>; - next-level-cache = <&L2_CA53>; - enable-method = "psci"; - }; - - L2_CA53: cache-controller-1 { - compatible = "cache"; - power-domains = <&sysc R8A77995_PD_CA53_SCU>; - cache-unified; - cache-level = <2>; - }; - }; - - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board */ - clock-frequency = <0>; - }; - - pmu_a53 { - compatible = "arm,cortex-a53-pmu"; - interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; - }; - - psci { - compatible = "arm,psci-1.0", "arm,psci-0.2"; - method = "smc"; - }; - - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - soc { - compatible = "simple-bus"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - rwdt: watchdog@e6020000 { - compatible = "renesas,r8a77995-wdt", - "renesas,rcar-gen3-wdt"; - reg = <0 0xe6020000 0 0x0c>; - clocks = <&cpg CPG_MOD 402>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 402>; - status = "disabled"; - }; - - gpio0: gpio@e6050000 { - compatible = "renesas,gpio-r8a77995", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6050000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 0 9>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 912>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 912>; - }; - - gpio1: gpio@e6051000 { - compatible = "renesas,gpio-r8a77995", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6051000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 32 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 911>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 911>; - }; - - gpio2: gpio@e6052000 { - compatible = "renesas,gpio-r8a77995", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6052000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 64 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 910>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 910>; - }; - - gpio3: gpio@e6053000 { - compatible = "renesas,gpio-r8a77995", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6053000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 96 10>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 909>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 909>; - }; - - gpio4: gpio@e6054000 { - compatible = "renesas,gpio-r8a77995", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6054000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 128 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 908>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 908>; - }; - - gpio5: gpio@e6055000 { - compatible = "renesas,gpio-r8a77995", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6055000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 160 21>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 907>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 907>; - }; - - gpio6: gpio@e6055400 { - compatible = "renesas,gpio-r8a77995", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6055400 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 192 14>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 906>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 906>; - }; - - pfc: pin-controller@e6060000 { - compatible = "renesas,pfc-r8a77995"; - reg = <0 0xe6060000 0 0x508>; - }; - - cpg: clock-controller@e6150000 { - compatible = "renesas,r8a77995-cpg-mssr"; - reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk>; - clock-names = "extal"; - #clock-cells = <2>; - #power-domain-cells = <0>; - #reset-cells = <1>; - }; - - rst: reset-controller@e6160000 { - compatible = "renesas,r8a77995-rst"; - reg = <0 0xe6160000 0 0x0200>; - }; - - sysc: system-controller@e6180000 { - compatible = "renesas,r8a77995-sysc"; - reg = <0 0xe6180000 0 0x0400>; - #power-domain-cells = <1>; - }; - - thermal: thermal@e6190000 { - compatible = "renesas,thermal-r8a77995"; - reg = <0 0xe6190000 0 0x10>, <0 0xe6190100 0 0x38>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 522>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 522>; - #thermal-sensor-cells = <0>; - }; - - intc_ex: interrupt-controller@e61c0000 { - compatible = "renesas,intc-ex-r8a77995", "renesas,irqc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0 0xe61c0000 0 0x200>; - interrupts = , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 407>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 407>; - }; - - i2c0: i2c@e6500000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a77995", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6500000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 931>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 931>; - dmas = <&dmac1 0x91>, <&dmac1 0x90>, - <&dmac2 0x91>, <&dmac2 0x90>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c1: i2c@e6508000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a77995", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6508000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 930>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 930>; - dmas = <&dmac1 0x93>, <&dmac1 0x92>, - <&dmac2 0x93>, <&dmac2 0x92>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c2: i2c@e6510000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a77995", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6510000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 929>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 929>; - dmas = <&dmac1 0x95>, <&dmac1 0x94>, - <&dmac2 0x95>, <&dmac2 0x94>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c3: i2c@e66d0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a77995", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66d0000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 928>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 928>; - dmas = <&dmac0 0x97>, <&dmac0 0x96>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - hscif0: serial@e6540000 { - compatible = "renesas,hscif-r8a77995", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6540000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 520>, - <&cpg CPG_CORE R8A77995_CLK_S3D1C>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x31>, <&dmac1 0x30>, - <&dmac2 0x31>, <&dmac2 0x30>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 520>; - status = "disabled"; - }; - - hscif3: serial@e66a0000 { - compatible = "renesas,hscif-r8a77995", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe66a0000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 517>, - <&cpg CPG_CORE R8A77995_CLK_S3D1C>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x37>, <&dmac0 0x36>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 517>; - status = "disabled"; - }; - - hsusb: usb@e6590000 { - compatible = "renesas,usbhs-r8a77995", - "renesas,rcar-gen3-usbhs"; - reg = <0 0xe6590000 0 0x200>; - interrupts = ; - clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>; - dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, - <&usb_dmac1 0>, <&usb_dmac1 1>; - dma-names = "ch0", "ch1", "ch2", "ch3"; - renesas,buswait = <11>; - phys = <&usb2_phy0 3>; - phy-names = "usb"; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 704>, <&cpg 703>; - status = "disabled"; - }; - - usb_dmac0: dma-controller@e65a0000 { - compatible = "renesas,r8a77995-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65a0000 0 0x100>; - interrupts = , - ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 330>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 330>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - usb_dmac1: dma-controller@e65b0000 { - compatible = "renesas,r8a77995-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65b0000 0 0x100>; - interrupts = , - ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 331>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 331>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - canfd: can@e66c0000 { - compatible = "renesas,r8a77995-canfd", - "renesas,rcar-gen3-canfd"; - reg = <0 0xe66c0000 0 0x8000>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 914>, - <&cpg CPG_CORE R8A77995_CLK_CANFD>, - <&can_clk>; - clock-names = "fck", "canfd", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>; - assigned-clock-rates = <40000000>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 914>; - status = "disabled"; - - channel0 { - status = "disabled"; - }; - - channel1 { - status = "disabled"; - }; - }; - - dmac0: dma-controller@e6700000 { - compatible = "renesas,dmac-r8a77995", - "renesas,rcar-dmac"; - reg = <0 0xe6700000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7"; - clocks = <&cpg CPG_MOD 219>; - clock-names = "fck"; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 219>; - #dma-cells = <1>; - dma-channels = <8>; - iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, - <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, - <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, - <&ipmmu_ds0 6>, <&ipmmu_ds0 7>; - }; - - dmac1: dma-controller@e7300000 { - compatible = "renesas,dmac-r8a77995", - "renesas,rcar-dmac"; - reg = <0 0xe7300000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7"; - clocks = <&cpg CPG_MOD 218>; - clock-names = "fck"; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 218>; - #dma-cells = <1>; - dma-channels = <8>; - iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, - <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, - <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, - <&ipmmu_ds1 6>, <&ipmmu_ds1 7>; - }; - - dmac2: dma-controller@e7310000 { - compatible = "renesas,dmac-r8a77995", - "renesas,rcar-dmac"; - reg = <0 0xe7310000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7"; - clocks = <&cpg CPG_MOD 217>; - clock-names = "fck"; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 217>; - #dma-cells = <1>; - dma-channels = <8>; - iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, - <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, - <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, - <&ipmmu_ds1 22>, <&ipmmu_ds1 23>; - }; - - ipmmu_ds0: mmu@e6740000 { - compatible = "renesas,ipmmu-r8a77995"; - reg = <0 0xe6740000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 0>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_ds1: mmu@e7740000 { - compatible = "renesas,ipmmu-r8a77995"; - reg = <0 0xe7740000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 1>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_hc: mmu@e6570000 { - compatible = "renesas,ipmmu-r8a77995"; - reg = <0 0xe6570000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 2>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_mm: mmu@e67b0000 { - compatible = "renesas,ipmmu-r8a77995"; - reg = <0 0xe67b0000 0 0x1000>; - interrupts = , - ; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_mp: mmu@ec670000 { - compatible = "renesas,ipmmu-r8a77995"; - reg = <0 0xec670000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 4>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_pv0: mmu@fd800000 { - compatible = "renesas,ipmmu-r8a77995"; - reg = <0 0xfd800000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 6>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_rt: mmu@ffc80000 { - compatible = "renesas,ipmmu-r8a77995"; - reg = <0 0xffc80000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 10>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_vc0: mmu@fe6b0000 { - compatible = "renesas,ipmmu-r8a77995"; - reg = <0 0xfe6b0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 12>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_vi0: mmu@febd0000 { - compatible = "renesas,ipmmu-r8a77995"; - reg = <0 0xfebd0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 14>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_vp0: mmu@fe990000 { - compatible = "renesas,ipmmu-r8a77995"; - reg = <0 0xfe990000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 16>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - avb: ethernet@e6800000 { - compatible = "renesas,etheravb-r8a77995", - "renesas,etheravb-rcar-gen3"; - reg = <0 0xe6800000 0 0x800>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15", - "ch16", "ch17", "ch18", "ch19", - "ch20", "ch21", "ch22", "ch23", - "ch24"; - clocks = <&cpg CPG_MOD 812>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 812>; - phy-mode = "rgmii"; - iommus = <&ipmmu_ds0 16>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - can0: can@e6c30000 { - compatible = "renesas,can-r8a77995", - "renesas,rcar-gen3-can"; - reg = <0 0xe6c30000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 916>, - <&cpg CPG_CORE R8A77995_CLK_CANFD>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>; - assigned-clock-rates = <40000000>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 916>; - status = "disabled"; - }; - - can1: can@e6c38000 { - compatible = "renesas,can-r8a77995", - "renesas,rcar-gen3-can"; - reg = <0 0xe6c38000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 915>, - <&cpg CPG_CORE R8A77995_CLK_CANFD>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>; - assigned-clock-rates = <40000000>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 915>; - status = "disabled"; - }; - - pwm0: pwm@e6e30000 { - compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar"; - reg = <0 0xe6e30000 0 0x8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 523>; - status = "disabled"; - }; - - pwm1: pwm@e6e31000 { - compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar"; - reg = <0 0xe6e31000 0 0x8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 523>; - status = "disabled"; - }; - - pwm2: pwm@e6e32000 { - compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar"; - reg = <0 0xe6e32000 0 0x8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 523>; - status = "disabled"; - }; - - pwm3: pwm@e6e33000 { - compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar"; - reg = <0 0xe6e33000 0 0x8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 523>; - status = "disabled"; - }; - - scif0: serial@e6e60000 { - compatible = "renesas,scif-r8a77995", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e60000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 207>, - <&cpg CPG_CORE R8A77995_CLK_S3D1C>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x51>, <&dmac1 0x50>, - <&dmac2 0x51>, <&dmac2 0x50>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 207>; - status = "disabled"; - }; - - scif1: serial@e6e68000 { - compatible = "renesas,scif-r8a77995", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e68000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 206>, - <&cpg CPG_CORE R8A77995_CLK_S3D1C>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x53>, <&dmac1 0x52>, - <&dmac2 0x53>, <&dmac2 0x52>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 206>; - status = "disabled"; - }; - - scif2: serial@e6e88000 { - compatible = "renesas,scif-r8a77995", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e88000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 310>, - <&cpg CPG_CORE R8A77995_CLK_S3D1C>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x13>, <&dmac1 0x12>, - <&dmac2 0x13>, <&dmac2 0x12>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 310>; - status = "disabled"; - }; - - scif3: serial@e6c50000 { - compatible = "renesas,scif-r8a77995", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6c50000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 204>, - <&cpg CPG_CORE R8A77995_CLK_S3D1C>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x57>, <&dmac0 0x56>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 204>; - status = "disabled"; - }; - - scif4: serial@e6c40000 { - compatible = "renesas,scif-r8a77995", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6c40000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 203>, - <&cpg CPG_CORE R8A77995_CLK_S3D1C>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x59>, <&dmac0 0x58>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 203>; - status = "disabled"; - }; - - scif5: serial@e6f30000 { - compatible = "renesas,scif-r8a77995", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6f30000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 202>, - <&cpg CPG_CORE R8A77995_CLK_S3D1C>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, - <&dmac2 0x5b>, <&dmac2 0x5a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 202>; - status = "disabled"; - }; - - msiof0: spi@e6e90000 { - compatible = "renesas,msiof-r8a77995", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6e90000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 211>; - dmas = <&dmac1 0x41>, <&dmac1 0x40>, - <&dmac2 0x41>, <&dmac2 0x40>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 211>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof1: spi@e6ea0000 { - compatible = "renesas,msiof-r8a77995", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6ea0000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 210>; - dmas = <&dmac1 0x43>, <&dmac1 0x42>, - <&dmac2 0x43>, <&dmac2 0x42>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 210>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof2: spi@e6c00000 { - compatible = "renesas,msiof-r8a77995", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6c00000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 209>; - dmas = <&dmac0 0x45>, <&dmac0 0x44>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 209>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof3: spi@e6c10000 { - compatible = "renesas,msiof-r8a77995", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6c10000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 208>; - dmas = <&dmac0 0x47>, <&dmac0 0x46>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 208>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - vin4: video@e6ef4000 { - compatible = "renesas,vin-r8a77995"; - reg = <0 0xe6ef4000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 807>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 807>; - renesas,id = <4>; - status = "disabled"; - }; - - ohci0: usb@ee080000 { - compatible = "generic-ohci"; - reg = <0 0xee080000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; - phys = <&usb2_phy0 1>; - phy-names = "usb"; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 703>, <&cpg 704>; - status = "disabled"; - }; - - ehci0: usb@ee080100 { - compatible = "generic-ehci"; - reg = <0 0xee080100 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; - phys = <&usb2_phy0 2>; - phy-names = "usb"; - companion = <&ohci0>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 703>, <&cpg 704>; - status = "disabled"; - }; - - usb2_phy0: usb-phy@ee080200 { - compatible = "renesas,usb2-phy-r8a77995", - "renesas,rcar-gen3-usb2-phy"; - reg = <0 0xee080200 0 0x700>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 703>, <&cpg 704>; - #phy-cells = <1>; - status = "disabled"; - }; - - sdhi2: sd@ee140000 { - compatible = "renesas,sdhi-r8a77995", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee140000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 312>; - max-frequency = <200000000>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 312>; - iommus = <&ipmmu_ds1 34>; - status = "disabled"; - }; - - gic: interrupt-controller@f1010000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x0 0xf1010000 0 0x1000>, - <0x0 0xf1020000 0 0x20000>, - <0x0 0xf1040000 0 0x20000>, - <0x0 0xf1060000 0 0x20000>; - interrupts = ; - clocks = <&cpg CPG_MOD 408>; - clock-names = "clk"; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 408>; - }; - - vspbs: vsp@fe960000 { - compatible = "renesas,vsp2"; - reg = <0 0xfe960000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 627>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 627>; - renesas,fcp = <&fcpvb0>; - }; - - vspd0: vsp@fea20000 { - compatible = "renesas,vsp2"; - reg = <0 0xfea20000 0 0x5000>; - interrupts = ; - clocks = <&cpg CPG_MOD 623>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 623>; - renesas,fcp = <&fcpvd0>; - }; - - vspd1: vsp@fea28000 { - compatible = "renesas,vsp2"; - reg = <0 0xfea28000 0 0x5000>; - interrupts = ; - clocks = <&cpg CPG_MOD 622>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 622>; - renesas,fcp = <&fcpvd1>; - }; - - fcpvb0: fcp@fe96f000 { - compatible = "renesas,fcpv"; - reg = <0 0xfe96f000 0 0x200>; - clocks = <&cpg CPG_MOD 607>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 607>; - iommus = <&ipmmu_vp0 5>; - }; - - fcpvd0: fcp@fea27000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea27000 0 0x200>; - clocks = <&cpg CPG_MOD 603>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 603>; - iommus = <&ipmmu_vi0 8>; - }; - - fcpvd1: fcp@fea2f000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea2f000 0 0x200>; - clocks = <&cpg CPG_MOD 602>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 602>; - iommus = <&ipmmu_vi0 9>; - }; - - cmm0: cmm@fea40000 { - compatible = "renesas,r8a77995-cmm", - "renesas,rcar-gen3-cmm"; - reg = <0 0xfea40000 0 0x1000>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - clocks = <&cpg CPG_MOD 711>; - resets = <&cpg 711>; - }; - - cmm1: cmm@fea50000 { - compatible = "renesas,r8a77995-cmm", - "renesas,rcar-gen3-cmm"; - reg = <0 0xfea50000 0 0x1000>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - clocks = <&cpg CPG_MOD 710>; - resets = <&cpg 710>; - }; - - du: display@feb00000 { - compatible = "renesas,du-r8a77995"; - reg = <0 0xfeb00000 0 0x40000>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>; - clock-names = "du.0", "du.1"; - resets = <&cpg 724>; - reset-names = "du.0"; - - renesas,cmms = <&cmm0>, <&cmm1>; - vsps = <&vspd0 0>, <&vspd1 0>; - - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - du_out_rgb: endpoint { - }; - }; - - port@1 { - reg = <1>; - du_out_lvds0: endpoint { - remote-endpoint = <&lvds0_in>; - }; - }; - - port@2 { - reg = <2>; - du_out_lvds1: endpoint { - remote-endpoint = <&lvds1_in>; - }; - }; - }; - }; - - lvds0: lvds-encoder@feb90000 { - compatible = "renesas,r8a77995-lvds"; - reg = <0 0xfeb90000 0 0x20>; - clocks = <&cpg CPG_MOD 727>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 727>; - status = "disabled"; - - renesas,companion = <&lvds1>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - lvds0_in: endpoint { - remote-endpoint = <&du_out_lvds0>; - }; - }; - - port@1 { - reg = <1>; - lvds0_out: endpoint { - }; - }; - }; - }; - - lvds1: lvds-encoder@feb90100 { - compatible = "renesas,r8a77995-lvds"; - reg = <0 0xfeb90100 0 0x20>; - clocks = <&cpg CPG_MOD 727>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 726>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - lvds1_in: endpoint { - remote-endpoint = <&du_out_lvds1>; - }; - }; - - port@1 { - reg = <1>; - lvds1_out: endpoint { - }; - }; - }; - }; - - prr: chipid@fff00044 { - compatible = "renesas,prr"; - reg = <0 0xfff00044 0 4>; - }; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&thermal>; - - cooling-maps { - }; - - trips { - cpu-crit { - temperature = <120000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; - }; -}; diff --git a/sys/gnu/dts/arm64/renesas/rzg2-advantech-idk-1110wr-panel.dtsi b/sys/gnu/dts/arm64/renesas/rzg2-advantech-idk-1110wr-panel.dtsi deleted file mode 100644 index bcc21178ae0..00000000000 --- a/sys/gnu/dts/arm64/renesas/rzg2-advantech-idk-1110wr-panel.dtsi +++ /dev/null @@ -1,41 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the Advantech idk-1110wr LVDS panel connected - * to RZ/G2 boards - * - * Copyright (C) 2019 Renesas Electronics Corp. - */ - -/ { - panel-lvds { - compatible = "advantech,idk-1110wr", "panel-lvds"; - - width-mm = <223>; - height-mm = <125>; - - data-mapping = "jeida-24"; - - panel-timing { - /* 1024x600 @60Hz */ - clock-frequency = <51200000>; - hactive = <1024>; - vactive = <600>; - hsync-len = <240>; - hfront-porch = <40>; - hback-porch = <40>; - vfront-porch = <15>; - vback-porch = <10>; - vsync-len = <10>; - }; - - port { - panel_in: endpoint { - remote-endpoint = <&lvds_connector>; - }; - }; - }; -}; - -&lvds_connector { - remote-endpoint = <&panel_in>; -}; diff --git a/sys/gnu/dts/arm64/renesas/salvator-common.dtsi b/sys/gnu/dts/arm64/renesas/salvator-common.dtsi deleted file mode 100644 index 98bbcafc8c0..00000000000 --- a/sys/gnu/dts/arm64/renesas/salvator-common.dtsi +++ /dev/null @@ -1,931 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for common parts of Salvator-X board variants - * - * Copyright (C) 2015-2016 Renesas Electronics Corp. - */ - -/* - * SSI-AK4613 - * - * This command is required when Playback/Capture - * - * amixer set "DVC Out" 100% - * amixer set "DVC In" 100% - * - * You can use Mute - * - * amixer set "DVC Out Mute" on - * amixer set "DVC In Mute" on - * - * You can use Volume Ramp - * - * amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps" - * amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps" - * amixer set "DVC Out Ramp" on - * aplay xxx.wav & - * amixer set "DVC Out" 80% // Volume Down - * amixer set "DVC Out" 100% // Volume Up - */ - -#include -#include - -/ { - aliases { - serial0 = &scif2; - serial1 = &hscif1; - ethernet0 = &avb; - }; - - chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; - stdout-path = "serial0:115200n8"; - }; - - audio_clkout: audio-clkout { - /* - * This is same as <&rcar_sound 0> - * but needed to avoid cs2000/rcar_sound probe dead-lock - */ - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <12288000>; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 50000>; - - brightness-levels = <256 128 64 16 8 4 0>; - default-brightness-level = <6>; - - power-supply = <®_12v>; - enable-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; - }; - - cvbs-in { - compatible = "composite-video-connector"; - label = "CVBS IN"; - - port { - cvbs_con: endpoint { - remote-endpoint = <&adv7482_ain7>; - }; - }; - }; - - hdmi-in { - compatible = "hdmi-connector"; - label = "HDMI IN"; - type = "a"; - - port { - hdmi_in_con: endpoint { - remote-endpoint = <&adv7482_hdmi>; - }; - }; - }; - - hdmi0-out { - compatible = "hdmi-connector"; - label = "HDMI0 OUT"; - type = "a"; - - port { - hdmi0_con: endpoint { - }; - }; - }; - - hdmi1-out { - compatible = "hdmi-connector"; - label = "HDMI1 OUT"; - type = "a"; - - port { - hdmi1_con: endpoint { - }; - }; - }; - - keys { - compatible = "gpio-keys"; - - pinctrl-0 = <&keys_pins>; - pinctrl-names = "default"; - - key-1 { - gpios = <&gpio5 17 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW4-1"; - wakeup-source; - debounce-interval = <20>; - }; - key-2 { - gpios = <&gpio5 20 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW4-2"; - wakeup-source; - debounce-interval = <20>; - }; - key-3 { - gpios = <&gpio5 22 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW4-3"; - wakeup-source; - debounce-interval = <20>; - }; - key-4 { - gpios = <&gpio5 23 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW4-4"; - wakeup-source; - debounce-interval = <20>; - }; - key-a { - gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "TSW0"; - wakeup-source; - debounce-interval = <20>; - }; - key-b { - gpios = <&gpio6 12 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "TSW1"; - wakeup-source; - debounce-interval = <20>; - }; - key-c { - gpios = <&gpio6 13 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "TSW2"; - wakeup-source; - debounce-interval = <20>; - }; - }; - - reg_1p8v: regulator0 { - compatible = "regulator-fixed"; - regulator-name = "fixed-1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_3p3v: regulator1 { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_12v: regulator2 { - compatible = "regulator-fixed"; - regulator-name = "fixed-12V"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-boot-on; - regulator-always-on; - }; - - sound_card: sound { - compatible = "audio-graph-card"; - - label = "rcar-sound"; - - dais = <&rsnd_port0>; - }; - - vbus0_usb2: regulator-vbus0-usb2 { - compatible = "regulator-fixed"; - - regulator-name = "USB20_VBUS0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - gpio = <&gpio6 16 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vcc_sdhi0: regulator-vcc-sdhi0 { - compatible = "regulator-fixed"; - - regulator-name = "SDHI0 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vccq_sdhi0: regulator-vccq-sdhi0 { - compatible = "regulator-gpio"; - - regulator-name = "SDHI0 VccQ"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; - gpios-states = <1>; - states = <3300000 1>, <1800000 0>; - }; - - vcc_sdhi3: regulator-vcc-sdhi3 { - compatible = "regulator-fixed"; - - regulator-name = "SDHI3 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&gpio3 15 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vccq_sdhi3: regulator-vccq-sdhi3 { - compatible = "regulator-gpio"; - - regulator-name = "SDHI3 VccQ"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; - gpios-states = <1>; - states = <3300000 1>, <1800000 0>; - }; - - vga { - compatible = "vga-connector"; - - port { - vga_in: endpoint { - remote-endpoint = <&adv7123_out>; - }; - }; - }; - - vga-encoder { - compatible = "adi,adv7123"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7123_in: endpoint { - remote-endpoint = <&du_out_rgb>; - }; - }; - port@1 { - reg = <1>; - adv7123_out: endpoint { - remote-endpoint = <&vga_in>; - }; - }; - }; - }; - - x12_clk: x12 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24576000>; - }; - - /* External DU dot clocks */ - x21_clk: x21-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <33000000>; - }; - - x22_clk: x22-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <33000000>; - }; - - x23_clk: x23-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; -}; - -&audio_clk_a { - clock-frequency = <22579200>; -}; - -&avb { - pinctrl-0 = <&avb_pins>; - pinctrl-names = "default"; - phy-handle = <&phy0>; - phy-mode = "rgmii-txid"; - status = "okay"; - - phy0: ethernet-phy@0 { - rxc-skew-ps = <1500>; - reg = <0>; - interrupt-parent = <&gpio2>; - interrupts = <11 IRQ_TYPE_LEVEL_LOW>; - reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; - }; -}; - -&csi20 { - status = "okay"; - - ports { - port@0 { - reg = <0>; - csi20_in: endpoint { - clock-lanes = <0>; - data-lanes = <1>; - remote-endpoint = <&adv7482_txb>; - }; - }; - }; -}; - -&csi40 { - status = "okay"; - - ports { - port@0 { - reg = <0>; - - csi40_in: endpoint { - clock-lanes = <0>; - data-lanes = <1 2 3 4>; - remote-endpoint = <&adv7482_txa>; - }; - }; - }; -}; - -&du { - pinctrl-0 = <&du_pins>; - pinctrl-names = "default"; - status = "okay"; - - ports { - port@0 { - endpoint { - remote-endpoint = <&adv7123_in>; - }; - }; - }; -}; - -&ehci0 { - dr_mode = "otg"; - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&extalr_clk { - clock-frequency = <32768>; -}; - -&hscif1 { - pinctrl-0 = <&hscif1_pins>; - pinctrl-names = "default"; - - uart-has-rtscts; - /* Please only enable hscif1 or scif1 */ - status = "okay"; -}; - -&hsusb { - dr_mode = "otg"; - status = "okay"; -}; - -&i2c2 { - pinctrl-0 = <&i2c2_pins>; - pinctrl-names = "default"; - - status = "okay"; - - clock-frequency = <100000>; - - ak4613: codec@10 { - compatible = "asahi-kasei,ak4613"; - #sound-dai-cells = <0>; - reg = <0x10>; - clocks = <&rcar_sound 3>; - - asahi-kasei,in1-single-end; - asahi-kasei,in2-single-end; - asahi-kasei,out1-single-end; - asahi-kasei,out2-single-end; - asahi-kasei,out3-single-end; - asahi-kasei,out4-single-end; - asahi-kasei,out5-single-end; - asahi-kasei,out6-single-end; - - port { - ak4613_endpoint: endpoint { - remote-endpoint = <&rsnd_endpoint0>; - }; - }; - }; - - cs2000: clk_multiplier@4f { - #clock-cells = <0>; - compatible = "cirrus,cs2000-cp"; - reg = <0x4f>; - clocks = <&audio_clkout>, <&x12_clk>; - clock-names = "clk_in", "ref_clk"; - - assigned-clocks = <&cs2000>; - assigned-clock-rates = <24576000>; /* 1/1 divide */ - }; -}; - -&i2c4 { - status = "okay"; - - pca9654: gpio@20 { - compatible = "onnn,pca9654"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - }; - - video-receiver@70 { - compatible = "adi,adv7482"; - reg = <0x70 0x71 0x72 0x73 0x74 0x75 - 0x60 0x61 0x62 0x63 0x64 0x65>; - reg-names = "main", "dpll", "cp", "hdmi", "edid", "repeater", - "infoframe", "cbus", "cec", "sdp", "txa", "txb" ; - - #address-cells = <1>; - #size-cells = <0>; - - interrupt-parent = <&gpio6>; - interrupt-names = "intrq1", "intrq2"; - interrupts = <30 IRQ_TYPE_LEVEL_LOW>, - <31 IRQ_TYPE_LEVEL_LOW>; - - port@7 { - reg = <7>; - - adv7482_ain7: endpoint { - remote-endpoint = <&cvbs_con>; - }; - }; - - port@8 { - reg = <8>; - - adv7482_hdmi: endpoint { - remote-endpoint = <&hdmi_in_con>; - }; - }; - - port@a { - reg = <10>; - - adv7482_txa: endpoint { - clock-lanes = <0>; - data-lanes = <1 2 3 4>; - remote-endpoint = <&csi40_in>; - }; - }; - - port@b { - reg = <11>; - - adv7482_txb: endpoint { - clock-lanes = <0>; - data-lanes = <1>; - remote-endpoint = <&csi20_in>; - }; - }; - }; - - csa_vdd: adc@7c { - compatible = "maxim,max9611"; - reg = <0x7c>; - - shunt-resistor-micro-ohms = <5000>; - }; - - csa_dvfs: adc@7f { - compatible = "maxim,max9611"; - reg = <0x7f>; - - shunt-resistor-micro-ohms = <5000>; - }; -}; - -&i2c_dvfs { - status = "okay"; - - clock-frequency = <400000>; - - pmic: pmic@30 { - pinctrl-0 = <&irq0_pins>; - pinctrl-names = "default"; - - compatible = "rohm,bd9571mwv"; - reg = <0x30>; - interrupt-parent = <&intc_ex>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - rohm,ddr-backup-power = <0xf>; - rohm,rstbmode-level; - - regulators { - dvfs: dvfs { - regulator-name = "dvfs"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1030000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; - - eeprom@50 { - compatible = "rohm,br24t01", "atmel,24c01"; - reg = <0x50>; - pagesize = <8>; - }; -}; - -&ohci0 { - dr_mode = "otg"; - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&pcie_bus_clk { - clock-frequency = <100000000>; -}; - -&pciec0 { - status = "okay"; -}; - -&pciec1 { - status = "okay"; -}; - -&pfc { - pinctrl-0 = <&scif_clk_pins>; - pinctrl-names = "default"; - - avb_pins: avb { - mux { - groups = "avb_link", "avb_mdio", "avb_mii"; - function = "avb"; - }; - - pins_mdio { - groups = "avb_mdio"; - drive-strength = <24>; - }; - - pins_mii_tx { - pins = "PIN_AVB_TX_CTL", "PIN_AVB_TXC", "PIN_AVB_TD0", - "PIN_AVB_TD1", "PIN_AVB_TD2", "PIN_AVB_TD3"; - drive-strength = <12>; - }; - }; - - du_pins: du { - groups = "du_rgb888", "du_sync", "du_oddf", "du_clk_out_0"; - function = "du"; - }; - - hscif1_pins: hscif1 { - groups = "hscif1_data_a", "hscif1_ctrl_a"; - function = "hscif1"; - }; - - i2c2_pins: i2c2 { - groups = "i2c2_a"; - function = "i2c2"; - }; - - irq0_pins: irq0 { - groups = "intc_ex_irq0"; - function = "intc_ex"; - }; - - keys_pins: keys { - pins = "GP_5_17", "GP_5_20", "GP_5_22"; - bias-pull-up; - }; - - pwm1_pins: pwm1 { - groups = "pwm1_a"; - function = "pwm1"; - }; - - scif1_pins: scif1 { - groups = "scif1_data_a", "scif1_ctrl"; - function = "scif1"; - }; - - scif2_pins: scif2 { - groups = "scif2_data_a"; - function = "scif2"; - }; - - scif_clk_pins: scif_clk { - groups = "scif_clk_a"; - function = "scif_clk"; - }; - - sdhi0_pins: sd0 { - groups = "sdhi0_data4", "sdhi0_ctrl"; - function = "sdhi0"; - power-source = <3300>; - }; - - sdhi0_pins_uhs: sd0_uhs { - groups = "sdhi0_data4", "sdhi0_ctrl"; - function = "sdhi0"; - power-source = <1800>; - }; - - sdhi2_pins: sd2 { - groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds"; - function = "sdhi2"; - power-source = <1800>; - }; - - sdhi3_pins: sd3 { - groups = "sdhi3_data4", "sdhi3_ctrl"; - function = "sdhi3"; - power-source = <3300>; - }; - - sdhi3_pins_uhs: sd3_uhs { - groups = "sdhi3_data4", "sdhi3_ctrl"; - function = "sdhi3"; - power-source = <1800>; - }; - - sound_pins: sound { - groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a"; - function = "ssi"; - }; - - sound_clk_pins: sound_clk { - groups = "audio_clk_a_a", "audio_clk_b_a", "audio_clk_c_a", - "audio_clkout_a", "audio_clkout3_a"; - function = "audio_clk"; - }; - - usb0_pins: usb0 { - groups = "usb0"; - function = "usb0"; - }; - - usb1_pins: usb1 { - mux { - groups = "usb1"; - function = "usb1"; - }; - - ovc { - pins = "GP_6_27"; - bias-pull-up; - }; - - pwen { - pins = "GP_6_26"; - bias-pull-down; - }; - }; - - usb30_pins: usb30 { - groups = "usb30"; - function = "usb30"; - }; -}; - -&pwm1 { - pinctrl-0 = <&pwm1_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&rcar_sound { - pinctrl-0 = <&sound_pins &sound_clk_pins>; - pinctrl-names = "default"; - - /* Single DAI */ - #sound-dai-cells = <0>; - - /* audio_clkout0/1/2/3 */ - #clock-cells = <1>; - clock-frequency = <12288000 11289600>; - - status = "okay"; - - /* update to */ - clocks = <&cpg CPG_MOD 1005>, - <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, - <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, - <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, - <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, - <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, - <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, - <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, - <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, - <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, - <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, - <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, - <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, - <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, - <&audio_clk_a>, <&cs2000>, - <&audio_clk_c>, - <&cpg CPG_CORE CPG_AUDIO_CLK_I>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - rsnd_port0: port@0 { - reg = <0>; - rsnd_endpoint0: endpoint { - remote-endpoint = <&ak4613_endpoint>; - - dai-format = "left_j"; - bitclock-master = <&rsnd_endpoint0>; - frame-master = <&rsnd_endpoint0>; - - playback = <&ssi0 &src0 &dvc0>; - capture = <&ssi1 &src1 &dvc1>; - }; - }; - }; -}; - -&rwdt { - timeout-sec = <60>; - status = "okay"; -}; - -&scif1 { - pinctrl-0 = <&scif1_pins>; - pinctrl-names = "default"; - - uart-has-rtscts; - /* Please only enable hscif1 or scif1 */ - /* status = "okay"; */ -}; - -&scif2 { - pinctrl-0 = <&scif2_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&scif_clk { - clock-frequency = <14745600>; -}; - -&sdhi0 { - pinctrl-0 = <&sdhi0_pins>; - pinctrl-1 = <&sdhi0_pins_uhs>; - pinctrl-names = "default", "state_uhs"; - - vmmc-supply = <&vcc_sdhi0>; - vqmmc-supply = <&vccq_sdhi0>; - cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; - bus-width = <4>; - sd-uhs-sdr50; - sd-uhs-sdr104; - status = "okay"; -}; - -&sdhi2 { - /* used for on-board 8bit eMMC */ - pinctrl-0 = <&sdhi2_pins>; - pinctrl-1 = <&sdhi2_pins>; - pinctrl-names = "default", "state_uhs"; - - vmmc-supply = <®_3p3v>; - vqmmc-supply = <®_1p8v>; - bus-width = <8>; - mmc-hs200-1_8v; - mmc-hs400-1_8v; - non-removable; - fixed-emmc-driver-type = <1>; - status = "okay"; -}; - -&sdhi3 { - pinctrl-0 = <&sdhi3_pins>; - pinctrl-1 = <&sdhi3_pins_uhs>; - pinctrl-names = "default", "state_uhs"; - - vmmc-supply = <&vcc_sdhi3>; - vqmmc-supply = <&vccq_sdhi3>; - cd-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>; - bus-width = <4>; - sd-uhs-sdr50; - sd-uhs-sdr104; - status = "okay"; -}; - -&ssi1 { - shared-pin; -}; - -&usb_extal_clk { - clock-frequency = <50000000>; -}; - -&usb2_phy0 { - pinctrl-0 = <&usb0_pins>; - pinctrl-names = "default"; - - vbus-supply = <&vbus0_usb2>; - status = "okay"; -}; - -&usb2_phy1 { - pinctrl-0 = <&usb1_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&usb3_peri0 { - phys = <&usb3_phy0>; - phy-names = "usb"; - - companion = <&xhci0>; - - status = "okay"; -}; - -&usb3_phy0 { - status = "okay"; -}; - -&usb3s0_clk { - clock-frequency = <100000000>; -}; - -&vin0 { - status = "okay"; -}; - -&vin1 { - status = "okay"; -}; - -&vin2 { - status = "okay"; -}; - -&vin3 { - status = "okay"; -}; - -&vin4 { - status = "okay"; -}; - -&vin5 { - status = "okay"; -}; - -&vin6 { - status = "okay"; -}; - -&vin7 { - status = "okay"; -}; - -&xhci0 { - pinctrl-0 = <&usb30_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/renesas/salvator-x.dtsi b/sys/gnu/dts/arm64/renesas/salvator-x.dtsi deleted file mode 100644 index ddee50e6463..00000000000 --- a/sys/gnu/dts/arm64/renesas/salvator-x.dtsi +++ /dev/null @@ -1,29 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the Salvator-X board - * - * Copyright (C) 2015-2016 Renesas Electronics Corp. - */ - -#include "salvator-common.dtsi" - -/ { - model = "Renesas Salvator-X board"; - compatible = "renesas,salvator-x"; -}; - -&extal_clk { - clock-frequency = <16666666>; -}; - -&i2c4 { - clock-frequency = <400000>; - - versaclock5: clock-generator@6a { - compatible = "idt,5p49v5923"; - reg = <0x6a>; - #clock-cells = <1>; - clocks = <&x23_clk>; - clock-names = "xin"; - }; -}; diff --git a/sys/gnu/dts/arm64/renesas/salvator-xs.dtsi b/sys/gnu/dts/arm64/renesas/salvator-xs.dtsi deleted file mode 100644 index 717d42758cb..00000000000 --- a/sys/gnu/dts/arm64/renesas/salvator-xs.dtsi +++ /dev/null @@ -1,29 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the Salvator-X 2nd version board - * - * Copyright (C) 2015-2017 Renesas Electronics Corp. - */ - -#include "salvator-common.dtsi" - -/ { - model = "Renesas Salvator-X 2nd version board"; - compatible = "renesas,salvator-xs"; -}; - -&extal_clk { - clock-frequency = <16640000>; -}; - -&i2c4 { - clock-frequency = <400000>; - - versaclock6: clock-generator@6a { - compatible = "idt,5p49v6901"; - reg = <0x6a>; - #clock-cells = <1>; - clocks = <&x23_clk>; - clock-names = "xin"; - }; -}; diff --git a/sys/gnu/dts/arm64/renesas/ulcb-kf.dtsi b/sys/gnu/dts/arm64/renesas/ulcb-kf.dtsi deleted file mode 100644 index 202177706cd..00000000000 --- a/sys/gnu/dts/arm64/renesas/ulcb-kf.dtsi +++ /dev/null @@ -1,382 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the Kingfisher (ULCB extension) board - * - * Copyright (C) 2017 Renesas Electronics Corp. - * Copyright (C) 2017 Cogent Embedded, Inc. - */ - -/* - * SSI-PCM3168A - * aplay -D plughw:0,2 xxx.wav - * arecord -D plughw:0,3 xxx.wav - */ - -/ { - aliases { - serial1 = &hscif0; - serial2 = &scif1; - }; - - clksndsel: clksndsel { - #clock-cells = <0>; - compatible = "gpio-mux-clock"; - clocks = <&cs2000>, <&audio_clk_a>; /* clk8snd, clksnd */ - select-gpios = <&gpio_exp_75 13 GPIO_ACTIVE_HIGH>; - }; - - snd_3p3v: regulator-snd_3p3v { - compatible = "regulator-fixed"; - regulator-name = "snd-3.3v"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - snd_vcc5v: regulator-snd_vcc5v { - compatible = "regulator-fixed"; - regulator-name = "snd-vcc5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - wlan_en: regulator-wlan_en { - compatible = "regulator-fixed"; - regulator-name = "wlan-en-regulator"; - - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&gpio_exp_74 4 GPIO_ACTIVE_HIGH>; - startup-delay-us = <70000>; - enable-active-high; - }; -}; - -&can0 { - pinctrl-0 = <&can0_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&can1 { - pinctrl-0 = <&can1_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&ehci0 { - dr_mode = "otg"; - status = "okay"; -}; - -&hscif0 { - pinctrl-0 = <&hscif0_pins>; - pinctrl-names = "default"; - uart-has-rtscts; - - status = "okay"; -}; - -&hsusb { - dr_mode = "otg"; - status = "okay"; -}; - -&i2c2 { - i2cswitch2: i2c-switch@71 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x71>; - reset-gpios = <&gpio5 3 GPIO_ACTIVE_LOW>; - - /* Audio_SDA, Audio_SCL */ - i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - - pcm3168a: audio-codec@44 { - #sound-dai-cells = <0>; - compatible = "ti,pcm3168a"; - reg = <0x44>; - clocks = <&clksndsel>; - clock-names = "scki"; - - VDD1-supply = <&snd_3p3v>; - VDD2-supply = <&snd_3p3v>; - VCCAD1-supply = <&snd_vcc5v>; - VCCAD2-supply = <&snd_vcc5v>; - VCCDA1-supply = <&snd_vcc5v>; - VCCDA2-supply = <&snd_vcc5v>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - mclk-fs = <512>; - port@0 { - reg = <0>; - pcm3168a_endpoint_p: endpoint { - remote-endpoint = <&rsnd_for_pcm3168a_play>; - clocks = <&clksndsel>; - }; - }; - port@1 { - reg = <1>; - pcm3168a_endpoint_c: endpoint { - remote-endpoint = <&rsnd_for_pcm3168a_capture>; - clocks = <&clksndsel>; - }; - }; - }; - }; - }; - }; - - /* U11 */ - gpio_exp_74: gpio@74 { - compatible = "ti,tca9539"; - reg = <0x74>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - interrupt-parent = <&gpio6>; - interrupts = <8 IRQ_TYPE_EDGE_FALLING>; - - audio_out_off { - gpio-hog; - gpios = <0 GPIO_ACTIVE_HIGH>; /* P00 */ - output-high; - line-name = "Audio_Out_OFF"; - }; - - hub_pwen { - gpio-hog; - gpios = <6 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "HUB pwen"; - }; - - hub_rst { - gpio-hog; - gpios = <7 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "HUB rst"; - }; - - otg_extlpn { - gpio-hog; - gpios = <9 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "OTG EXTLPn"; - }; - - otg_offvbusn { - gpio-hog; - gpios = <8 GPIO_ACTIVE_HIGH>; - output-low; - line-name = "OTG OFFVBUSn"; - }; - - sd-wifi-mux { - gpio-hog; - gpios = <5 GPIO_ACTIVE_HIGH>; - output-low; /* Connect WL1837 */ - line-name = "SD WiFi mux"; - }; - - snd_rst { - gpio-hog; - gpios = <15 GPIO_ACTIVE_HIGH>; /* P17 */ - output-high; - line-name = "SND_RST"; - }; - }; - - /* U5 */ - gpio_exp_75: gpio@75 { - compatible = "ti,tca9539"; - reg = <0x75>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - interrupt-parent = <&gpio6>; - interrupts = <4 IRQ_TYPE_EDGE_FALLING>; - }; -}; - -&i2c4 { - i2cswitch4: i2c-switch@71 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x71>; - reset-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>; - }; - - gpio_exp_76: gpio@76 { - compatible = "ti,tca9539"; - reg = <0x76>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - interrupt-parent = <&gpio7>; - interrupts = <3 IRQ_TYPE_EDGE_FALLING>; - }; - - gpio_exp_77: gpio@77 { - compatible = "ti,tca9539"; - reg = <0x77>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - interrupt-parent = <&gpio5>; - interrupts = <9 IRQ_TYPE_EDGE_FALLING>; - }; -}; - -&ohci0 { - dr_mode = "otg"; - status = "okay"; -}; - -&pcie_bus_clk { - clock-frequency = <100000000>; -}; - -&pciec0 { - status = "okay"; -}; - -&pciec1 { - status = "okay"; -}; - -&pfc { - can0_pins: can0 { - groups = "can0_data_a"; - function = "can0"; - }; - - can1_pins: can1 { - groups = "can1_data"; - function = "can1"; - }; - - hscif0_pins: hscif0 { - groups = "hscif0_data", "hscif0_ctrl"; - function = "hscif0"; - }; - - scif1_pins: scif1 { - groups = "scif1_data_b", "scif1_ctrl"; - function = "scif1"; - }; - - sdhi3_pins: sdhi3 { - groups = "sdhi3_data4", "sdhi3_ctrl"; - function = "sdhi3"; - power-source = <3300>; - }; - - sound_pcm_pins: sound-pcm { - groups = "ssi349_ctrl", "ssi3_data", "ssi4_data"; - function = "ssi"; - }; - - usb0_pins: usb0 { - groups = "usb0"; - function = "usb0"; - }; -}; - -&rcar_sound { - pinctrl-0 = <&sound_pins - &sound_clk_pins - &sound_pcm_pins>; - - ports { - /* rsnd_port0/1 are on salvator-common */ - rsnd_port2: port@2 { - reg = <2>; - rsnd_for_pcm3168a_play: endpoint { - remote-endpoint = <&pcm3168a_endpoint_p>; - - dai-format = "i2s"; - bitclock-master = <&rsnd_for_pcm3168a_play>; - frame-master = <&rsnd_for_pcm3168a_play>; - dai-tdm-slot-num = <8>; - - playback = <&ssi3>; - }; - }; - rsnd_port3: port@3 { - reg = <3>; - rsnd_for_pcm3168a_capture: endpoint { - remote-endpoint = <&pcm3168a_endpoint_c>; - - dai-format = "i2s"; - bitclock-master = <&rsnd_for_pcm3168a_capture>; - frame-master = <&rsnd_for_pcm3168a_capture>; - dai-tdm-slot-num = <6>; - - capture = <&ssi4>; - }; - }; - }; -}; - -&scif1 { - pinctrl-0 = <&scif1_pins>; - pinctrl-names = "default"; - uart-has-rtscts; - - status = "okay"; -}; - -&sdhi3 { - pinctrl-0 = <&sdhi3_pins>; - pinctrl-names = "default"; - - vmmc-supply = <&wlan_en>; - vqmmc-supply = <&wlan_en>; - bus-width = <4>; - no-1-8-v; - non-removable; - cap-power-off-card; - keep-power-in-suspend; - max-frequency = <26000000>; - status = "okay"; - - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@2 { - compatible = "ti,wl1837"; - reg = <2>; - interrupt-parent = <&gpio1>; - interrupts = <25 IRQ_TYPE_EDGE_FALLING>; - }; -}; - -&sound_card { - dais = <&rsnd_port0 /* ak4613 */ - &rsnd_port1 /* HDMI0 */ - &rsnd_port2 /* pcm3168a playback */ - &rsnd_port3 /* pcm3168a capture */ - >; -}; - -&ssi4 { - shared-pin; -}; - -&usb2_phy0 { - pinctrl-0 = <&usb0_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&xhci0 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/renesas/ulcb.dtsi b/sys/gnu/dts/arm64/renesas/ulcb.dtsi deleted file mode 100644 index ff88af8e39d..00000000000 --- a/sys/gnu/dts/arm64/renesas/ulcb.dtsi +++ /dev/null @@ -1,484 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the R-Car Gen3 ULCB board - * - * Copyright (C) 2016 Renesas Electronics Corp. - * Copyright (C) 2016 Cogent Embedded, Inc. - */ - -/* - * SSI-AK4613 - * aplay -D plughw:0,0 xxx.wav - * arecord -D plughw:0,0 xxx.wav - * SSI-HDMI - * aplay -D plughw:0,1 xxx.wav - */ - -#include -#include - -/ { - model = "Renesas R-Car Gen3 ULCB board"; - - aliases { - serial0 = &scif2; - ethernet0 = &avb; - }; - - chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; - stdout-path = "serial0:115200n8"; - }; - - audio_clkout: audio-clkout { - /* - * This is same as <&rcar_sound 0> - * but needed to avoid cs2000/rcar_sound probe dead-lock - */ - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <12288000>; - }; - - hdmi0-out { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi0_con: endpoint { - }; - }; - }; - - keyboard { - compatible = "gpio-keys"; - - key-1 { - linux,code = ; - label = "SW3"; - wakeup-source; - debounce-interval = <20>; - gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; - }; - }; - - leds { - compatible = "gpio-leds"; - - led5 { - gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>; - }; - led6 { - gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>; - }; - }; - - reg_1p8v: regulator0 { - compatible = "regulator-fixed"; - regulator-name = "fixed-1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_3p3v: regulator1 { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - sound_card: sound { - compatible = "audio-graph-card"; - label = "rcar-sound"; - - dais = <&rsnd_port0 /* ak4613 */ - &rsnd_port1 /* HDMI0 */ - >; - }; - - vcc_sdhi0: regulator-vcc-sdhi0 { - compatible = "regulator-fixed"; - - regulator-name = "SDHI0 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vccq_sdhi0: regulator-vccq-sdhi0 { - compatible = "regulator-gpio"; - - regulator-name = "SDHI0 VccQ"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; - gpios-states = <1>; - states = <3300000 1>, <1800000 0>; - }; - - x12_clk: x12 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24576000>; - }; - - x23_clk: x23-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; -}; - -&audio_clk_a { - clock-frequency = <22579200>; -}; - -&avb { - pinctrl-0 = <&avb_pins>; - pinctrl-names = "default"; - phy-handle = <&phy0>; - phy-mode = "rgmii-txid"; - status = "okay"; - - phy0: ethernet-phy@0 { - rxc-skew-ps = <1500>; - reg = <0>; - interrupt-parent = <&gpio2>; - interrupts = <11 IRQ_TYPE_LEVEL_LOW>; - reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; - }; -}; - -&du { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&extal_clk { - clock-frequency = <16666666>; -}; - -&extalr_clk { - clock-frequency = <32768>; -}; - -&hdmi0 { - status = "okay"; - - ports { - port@1 { - reg = <1>; - rcar_dw_hdmi0_out: endpoint { - remote-endpoint = <&hdmi0_con>; - }; - }; - port@2 { - reg = <2>; - dw_hdmi0_snd_in: endpoint { - remote-endpoint = <&rsnd_for_hdmi>; - }; - }; - }; -}; - -&hdmi0_con { - remote-endpoint = <&rcar_dw_hdmi0_out>; -}; - -&i2c2 { - pinctrl-0 = <&i2c2_pins>; - pinctrl-names = "default"; - - status = "okay"; - - clock-frequency = <100000>; - - ak4613: codec@10 { - compatible = "asahi-kasei,ak4613"; - #sound-dai-cells = <0>; - reg = <0x10>; - clocks = <&rcar_sound 3>; - - asahi-kasei,in1-single-end; - asahi-kasei,in2-single-end; - asahi-kasei,out1-single-end; - asahi-kasei,out2-single-end; - asahi-kasei,out3-single-end; - asahi-kasei,out4-single-end; - asahi-kasei,out5-single-end; - asahi-kasei,out6-single-end; - - port { - ak4613_endpoint: endpoint { - remote-endpoint = <&rsnd_for_ak4613>; - }; - }; - }; - - cs2000: clk-multiplier@4f { - #clock-cells = <0>; - compatible = "cirrus,cs2000-cp"; - reg = <0x4f>; - clocks = <&audio_clkout>, <&x12_clk>; - clock-names = "clk_in", "ref_clk"; - - assigned-clocks = <&cs2000>; - assigned-clock-rates = <24576000>; /* 1/1 divide */ - }; -}; - -&i2c4 { - status = "okay"; - - clock-frequency = <400000>; - - versaclock5: clock-generator@6a { - compatible = "idt,5p49v5925"; - reg = <0x6a>; - #clock-cells = <1>; - clocks = <&x23_clk>; - clock-names = "xin"; - }; -}; - -&i2c_dvfs { - status = "okay"; - - clock-frequency = <400000>; - - pmic: pmic@30 { - pinctrl-0 = <&irq0_pins>; - pinctrl-names = "default"; - - compatible = "rohm,bd9571mwv"; - reg = <0x30>; - interrupt-parent = <&intc_ex>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - rohm,ddr-backup-power = <0xf>; - rohm,rstbmode-pulse; - - regulators { - dvfs: dvfs { - regulator-name = "dvfs"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1030000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; -}; - -&ohci1 { - status = "okay"; -}; - -&pfc { - pinctrl-0 = <&scif_clk_pins>; - pinctrl-names = "default"; - - avb_pins: avb { - mux { - groups = "avb_link", "avb_mdio", "avb_mii"; - function = "avb"; - }; - - pins_mdio { - groups = "avb_mdio"; - drive-strength = <24>; - }; - - pins_mii_tx { - pins = "PIN_AVB_TX_CTL", "PIN_AVB_TXC", "PIN_AVB_TD0", - "PIN_AVB_TD1", "PIN_AVB_TD2", "PIN_AVB_TD3"; - drive-strength = <12>; - }; - }; - - i2c2_pins: i2c2 { - groups = "i2c2_a"; - function = "i2c2"; - }; - - irq0_pins: irq0 { - groups = "intc_ex_irq0"; - function = "intc_ex"; - }; - - scif2_pins: scif2 { - groups = "scif2_data_a"; - function = "scif2"; - }; - - scif_clk_pins: scif_clk { - groups = "scif_clk_a"; - function = "scif_clk"; - }; - - sdhi0_pins: sd0 { - groups = "sdhi0_data4", "sdhi0_ctrl"; - function = "sdhi0"; - power-source = <3300>; - }; - - sdhi0_pins_uhs: sd0_uhs { - groups = "sdhi0_data4", "sdhi0_ctrl"; - function = "sdhi0"; - power-source = <1800>; - }; - - sdhi2_pins: sd2 { - groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds"; - function = "sdhi2"; - power-source = <1800>; - }; - - sound_pins: sound { - groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a"; - function = "ssi"; - }; - - sound_clk_pins: sound-clk { - groups = "audio_clk_a_a", "audio_clk_b_a", "audio_clk_c_a", - "audio_clkout_a", "audio_clkout3_a"; - function = "audio_clk"; - }; - - usb1_pins: usb1 { - groups = "usb1"; - function = "usb1"; - }; -}; - -&rcar_sound { - pinctrl-0 = <&sound_pins &sound_clk_pins>; - pinctrl-names = "default"; - - /* Single DAI */ - #sound-dai-cells = <0>; - - /* audio_clkout0/1/2/3 */ - #clock-cells = <1>; - clock-frequency = <12288000 11289600>; - - status = "okay"; - - /* update to */ - clocks = <&cpg CPG_MOD 1005>, - <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, - <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, - <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, - <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, - <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, - <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, - <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, - <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, - <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, - <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, - <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, - <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, - <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, - <&audio_clk_a>, <&cs2000>, - <&audio_clk_c>, - <&cpg CPG_CORE CPG_AUDIO_CLK_I>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - rsnd_port0: port@0 { - reg = <0>; - rsnd_for_ak4613: endpoint { - remote-endpoint = <&ak4613_endpoint>; - - dai-format = "left_j"; - bitclock-master = <&rsnd_for_ak4613>; - frame-master = <&rsnd_for_ak4613>; - - playback = <&ssi0 &src0 &dvc0>; - capture = <&ssi1 &src1 &dvc1>; - }; - }; - rsnd_port1: port@1 { - reg = <1>; - rsnd_for_hdmi: endpoint { - remote-endpoint = <&dw_hdmi0_snd_in>; - - dai-format = "i2s"; - bitclock-master = <&rsnd_for_hdmi>; - frame-master = <&rsnd_for_hdmi>; - - playback = <&ssi2>; - }; - }; - }; -}; - -&rwdt { - timeout-sec = <60>; - status = "okay"; -}; - -&scif2 { - pinctrl-0 = <&scif2_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&scif_clk { - clock-frequency = <14745600>; -}; - -&sdhi0 { - pinctrl-0 = <&sdhi0_pins>; - pinctrl-1 = <&sdhi0_pins_uhs>; - pinctrl-names = "default", "state_uhs"; - - vmmc-supply = <&vcc_sdhi0>; - vqmmc-supply = <&vccq_sdhi0>; - cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; - bus-width = <4>; - sd-uhs-sdr50; - sd-uhs-sdr104; - status = "okay"; -}; - -&sdhi2 { - /* used for on-board 8bit eMMC */ - pinctrl-0 = <&sdhi2_pins>; - pinctrl-1 = <&sdhi2_pins>; - pinctrl-names = "default", "state_uhs"; - - vmmc-supply = <®_3p3v>; - vqmmc-supply = <®_1p8v>; - bus-width = <8>; - mmc-hs200-1_8v; - mmc-hs400-1_8v; - non-removable; - status = "okay"; -}; - -&ssi1 { - shared-pin; -}; - -&usb2_phy1 { - pinctrl-0 = <&usb1_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/rockchip/px30-evb.dts b/sys/gnu/dts/arm64/rockchip/px30-evb.dts deleted file mode 100644 index 0a680257d9c..00000000000 --- a/sys/gnu/dts/arm64/rockchip/px30-evb.dts +++ /dev/null @@ -1,579 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd - */ - -/dts-v1/; -#include -#include -#include -#include "px30.dtsi" - -/ { - model = "Rockchip PX30 EVB"; - compatible = "rockchip,px30-evb", "rockchip,px30"; - - chosen { - stdout-path = "serial5:115200n8"; - }; - - adc-keys { - compatible = "adc-keys"; - io-channels = <&saradc 2>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1800000>; - poll-interval = <100>; - - esc-key { - label = "esc"; - linux,code = ; - press-threshold-microvolt = <1310000>; - }; - - home-key { - label = "home"; - linux,code = ; - press-threshold-microvolt = <624000>; - }; - - menu-key { - label = "menu"; - linux,code = ; - press-threshold-microvolt = <987000>; - }; - - vol-down-key { - label = "volume down"; - linux,code = ; - press-threshold-microvolt = <300000>; - }; - - vol-up-key { - label = "volume up"; - linux,code = ; - press-threshold-microvolt = <17000>; - }; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 25000 0>; - power-supply = <&vcc3v3_lcd>; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - pinctrl-0 = <&emmc_reset>; - pinctrl-names = "default"; - reset-gpios = <&gpio1 RK_PB3 GPIO_ACTIVE_HIGH>; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_enable_h>; - - /* - * On the module itself this is one of these (depending - * on the actual card populated): - * - SDIO_RESET_L_WL_REG_ON - * - PDN (power down when low) - */ - reset-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; /* GPIO3_A4 */ - }; - - vcc5v0_sys: vccsys { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; -}; - -&cpu0 { - cpu-supply = <&vdd_arm>; -}; - -&cpu1 { - cpu-supply = <&vdd_arm>; -}; - -&cpu2 { - cpu-supply = <&vdd_arm>; -}; - -&cpu3 { - cpu-supply = <&vdd_arm>; -}; - -&display_subsystem { - status = "okay"; -}; - -&dsi { - status = "okay"; - - ports { - mipi_out: port@1 { - reg = <1>; - - mipi_out_panel: endpoint { - remote-endpoint = <&mipi_in_panel>; - }; - }; - }; - - panel@0 { - compatible = "xinpeng,xpp055c272"; - reg = <0>; - backlight = <&backlight>; - iovcc-supply = <&vcc_1v8>; - vci-supply = <&vcc3v3_lcd>; - - port { - mipi_in_panel: endpoint { - remote-endpoint = <&mipi_out_panel>; - }; - }; - }; -}; - -&dsi_dphy { - status = "okay"; -}; - -&emmc { - bus-width = <8>; - cap-mmc-highspeed; - mmc-hs200-1_8v; - non-removable; - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vcc_3v0>; - vqmmc-supply = <&vccio_flash>; - status = "okay"; -}; - -&gmac { - clock_in_out = "output"; - phy-supply = <&vcc_rmii>; - snps,reset-gpio = <&gpio2 13 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 50000 50000>; - status = "okay"; -}; - -&gpu { - mali-supply = <&vdd_log>; - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - rk809: pmic@20 { - compatible = "rockchip,rk809"; - reg = <0x20>; - interrupt-parent = <&gpio0>; - interrupts = <7 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int>; - rockchip,system-power-controller; - wakeup-source; - #clock-cells = <0>; - clock-output-names = "xin32k"; - - vcc1-supply = <&vcc5v0_sys>; - vcc2-supply = <&vcc5v0_sys>; - vcc3-supply = <&vcc5v0_sys>; - vcc4-supply = <&vcc5v0_sys>; - vcc5-supply = <&vcc3v3_sys>; - vcc6-supply = <&vcc3v3_sys>; - vcc7-supply = <&vcc3v3_sys>; - vcc8-supply = <&vcc3v3_sys>; - vcc9-supply = <&vcc5v0_sys>; - - regulators { - vdd_log: DCDC_REG1 { - regulator-name = "vdd_log"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <950000>; - }; - }; - - vdd_arm: DCDC_REG2 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <950000>; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_3v0: vcc_rmii: DCDC_REG4 { - regulator-name = "vcc_3v0"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3000000>; - }; - }; - - vcc3v3_sys: DCDC_REG5 { - regulator-name = "vcc3v3_sys"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc_1v0: LDO_REG1 { - regulator-name = "vcc_1v0"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vcc_1v8: vccio_flash: vccio_sdio: LDO_REG2 { - regulator-name = "vcc_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vdd_1v0: LDO_REG3 { - regulator-name = "vdd_1v0"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vcc3v0_pmu: LDO_REG4 { - regulator-name = "vcc3v0_pmu"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3000000>; - }; - }; - - vccio_sd: LDO_REG5 { - regulator-name = "vccio_sd"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc_sd: LDO_REG6 { - regulator-name = "vcc_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc2v8_dvp: LDO_REG7 { - regulator-name = "vcc2v8_dvp"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <2800000>; - }; - }; - - vcc1v8_dvp: LDO_REG8 { - regulator-name = "vcc1v8_dvp"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc1v5_dvp: LDO_REG9 { - regulator-name = "vcc1v5_dvp"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <1500000>; - }; - }; - - vcc3v3_lcd: SWITCH_REG1 { - regulator-name = "vcc3v3_lcd"; - regulator-boot-on; - }; - - vcc5v0_host: SWITCH_REG2 { - regulator-name = "vcc5v0_host"; - regulator-always-on; - regulator-boot-on; - }; - }; - }; -}; - -&i2c1 { - status = "okay"; - - sensor@d { - compatible = "asahi-kasei,ak8963"; - reg = <0x0d>; - gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; - vdd-supply = <&vcc3v0_pmu>; - mount-matrix = "1", /* x0 */ - "0", /* y0 */ - "0", /* z0 */ - "0", /* x1 */ - "1", /* y1 */ - "0", /* z1 */ - "0", /* x2 */ - "0", /* y2 */ - "1"; /* z2 */ - }; - - touchscreen@14 { - compatible = "goodix,gt1151"; - reg = <0x14>; - interrupt-parent = <&gpio0>; - interrupts = ; - irq-gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; - reset-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; - VDDIO-supply = <&vcc3v3_lcd>; - }; - - sensor@4c { - compatible = "fsl,mma7660"; - reg = <0x4c>; - interrupt-parent = <&gpio0>; - interrupts = ; - }; -}; - -&i2s1_2ch { - status = "okay"; -}; - -&io_domains { - status = "okay"; - - vccio1-supply = <&vccio_sdio>; - vccio2-supply = <&vccio_sd>; - vccio3-supply = <&vcc_3v0>; - vccio4-supply = <&vcc3v0_pmu>; - vccio5-supply = <&vcc_3v0>; - vccio6-supply = <&vccio_flash>; -}; - -&pinctrl { - headphone { - hp_det: hp-det { - rockchip,pins = - <2 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; - - emmc { - emmc_reset: emmc-reset { - rockchip,pins = <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - pmic_int: pmic_int { - rockchip,pins = - <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - soc_slppin_gpio: soc_slppin_gpio { - rockchip,pins = - <0 RK_PA4 RK_FUNC_GPIO &pcfg_output_low>; - }; - - soc_slppin_slp: soc_slppin_slp { - rockchip,pins = - <0 RK_PA4 1 &pcfg_pull_none>; - }; - - soc_slppin_rst: soc_slppin_rst { - rockchip,pins = - <0 RK_PA4 2 &pcfg_pull_none>; - }; - }; - - sdio-pwrseq { - wifi_enable_h: wifi-enable-h { - rockchip,pins = - <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&pmu_io_domains { - status = "okay"; - - pmuio1-supply = <&vcc3v0_pmu>; - pmuio2-supply = <&vcc3v0_pmu>; -}; - -&pwm1 { - status = "okay"; -}; - -&saradc { - vref-supply = <&vcc_1v8>; - status = "okay"; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - card-detect-delay = <800>; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-sdr104; - vmmc-supply = <&vcc_sd>; - vqmmc-supply = <&vccio_sd>; - status = "okay"; -}; - -&sdio { - bus-width = <4>; - cap-sd-highspeed; - keep-power-in-suspend; - non-removable; - mmc-pwrseq = <&sdio_pwrseq>; - sd-uhs-sdr104; - status = "okay"; -}; - -&tsadc { - rockchip,hw-tshut-mode = <1>; - rockchip,hw-tshut-polarity = <1>; - status = "okay"; -}; - -&u2phy { - status = "okay"; - - u2phy_host: host-port { - status = "okay"; - }; - - u2phy_otg: otg-port { - status = "okay"; - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_xfer &uart1_cts>; - status = "okay"; -}; - -&uart5 { - status = "okay"; -}; - -&usb20_otg { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&vopl { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/rockchip/px30.dtsi b/sys/gnu/dts/arm64/rockchip/px30.dtsi deleted file mode 100644 index 75908c58751..00000000000 --- a/sys/gnu/dts/arm64/rockchip/px30.dtsi +++ /dev/null @@ -1,2237 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -/ { - compatible = "rockchip,px30"; - - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - ethernet0 = &gmac; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - serial4 = &uart4; - serial5 = &uart5; - spi0 = &spi0; - spi1 = &spi1; - }; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a35"; - reg = <0x0 0x0>; - enable-method = "psci"; - clocks = <&cru ARMCLK>; - #cooling-cells = <2>; - cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; - dynamic-power-coefficient = <90>; - operating-points-v2 = <&cpu0_opp_table>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a35"; - reg = <0x0 0x1>; - enable-method = "psci"; - clocks = <&cru ARMCLK>; - #cooling-cells = <2>; - cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; - dynamic-power-coefficient = <90>; - operating-points-v2 = <&cpu0_opp_table>; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a35"; - reg = <0x0 0x2>; - enable-method = "psci"; - clocks = <&cru ARMCLK>; - #cooling-cells = <2>; - cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; - dynamic-power-coefficient = <90>; - operating-points-v2 = <&cpu0_opp_table>; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a35"; - reg = <0x0 0x3>; - enable-method = "psci"; - clocks = <&cru ARMCLK>; - #cooling-cells = <2>; - cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; - dynamic-power-coefficient = <90>; - operating-points-v2 = <&cpu0_opp_table>; - }; - - idle-states { - entry-method = "psci"; - - CPU_SLEEP: cpu-sleep { - compatible = "arm,idle-state"; - local-timer-stop; - arm,psci-suspend-param = <0x0010000>; - entry-latency-us = <120>; - exit-latency-us = <250>; - min-residency-us = <900>; - }; - - CLUSTER_SLEEP: cluster-sleep { - compatible = "arm,idle-state"; - local-timer-stop; - arm,psci-suspend-param = <0x1010000>; - entry-latency-us = <400>; - exit-latency-us = <500>; - min-residency-us = <2000>; - }; - }; - }; - - cpu0_opp_table: cpu0-opp-table { - compatible = "operating-points-v2"; - opp-shared; - - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <950000 950000 1350000>; - clock-latency-ns = <40000>; - opp-suspend; - }; - opp-816000000 { - opp-hz = /bits/ 64 <816000000>; - opp-microvolt = <1050000 1050000 1350000>; - clock-latency-ns = <40000>; - }; - opp-1008000000 { - opp-hz = /bits/ 64 <1008000000>; - opp-microvolt = <1175000 1175000 1350000>; - clock-latency-ns = <40000>; - }; - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <1300000 1300000 1350000>; - clock-latency-ns = <40000>; - }; - opp-1296000000 { - opp-hz = /bits/ 64 <1296000000>; - opp-microvolt = <1350000 1350000 1350000>; - clock-latency-ns = <40000>; - }; - }; - - arm-pmu { - compatible = "arm,cortex-a53-pmu"; - interrupts = , - , - , - ; - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; - }; - - display_subsystem: display-subsystem { - compatible = "rockchip,display-subsystem"; - ports = <&vopb_out>, <&vopl_out>; - status = "disabled"; - }; - - gmac_clkin: external-gmac-clock { - compatible = "fixed-clock"; - clock-frequency = <50000000>; - clock-output-names = "gmac_clkin"; - #clock-cells = <0>; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - thermal_zones: thermal-zones { - soc_thermal: soc-thermal { - polling-delay-passive = <20>; - polling-delay = <1000>; - sustainable-power = <750>; - thermal-sensors = <&tsadc 0>; - - trips { - threshold: trip-point-0 { - temperature = <70000>; - hysteresis = <2000>; - type = "passive"; - }; - - target: trip-point-1 { - temperature = <85000>; - hysteresis = <2000>; - type = "passive"; - }; - - soc_crit: soc-crit { - temperature = <115000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&target>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - contribution = <4096>; - }; - - map1 { - trip = <&target>; - cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - contribution = <4096>; - }; - }; - }; - - gpu_thermal: gpu-thermal { - polling-delay-passive = <100>; /* milliseconds */ - polling-delay = <1000>; /* milliseconds */ - thermal-sensors = <&tsadc 1>; - }; - }; - - xin24m: xin24m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "xin24m"; - }; - - pmu: power-management@ff000000 { - compatible = "rockchip,px30-pmu", "syscon", "simple-mfd"; - reg = <0x0 0xff000000 0x0 0x1000>; - - power: power-controller { - compatible = "rockchip,px30-power-controller"; - #power-domain-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - - /* These power domains are grouped by VD_LOGIC */ - pd_usb@PX30_PD_USB { - reg = ; - clocks = <&cru HCLK_HOST>, - <&cru HCLK_OTG>, - <&cru SCLK_OTG_ADP>; - pm_qos = <&qos_usb_host>, <&qos_usb_otg>; - }; - pd_sdcard@PX30_PD_SDCARD { - reg = ; - clocks = <&cru HCLK_SDMMC>, - <&cru SCLK_SDMMC>; - pm_qos = <&qos_sdmmc>; - }; - pd_gmac@PX30_PD_GMAC { - reg = ; - clocks = <&cru ACLK_GMAC>, - <&cru PCLK_GMAC>, - <&cru SCLK_MAC_REF>, - <&cru SCLK_GMAC_RX_TX>; - pm_qos = <&qos_gmac>; - }; - pd_mmc_nand@PX30_PD_MMC_NAND { - reg = ; - clocks = <&cru HCLK_NANDC>, - <&cru HCLK_EMMC>, - <&cru HCLK_SDIO>, - <&cru HCLK_SFC>, - <&cru SCLK_EMMC>, - <&cru SCLK_NANDC>, - <&cru SCLK_SDIO>, - <&cru SCLK_SFC>; - pm_qos = <&qos_emmc>, <&qos_nand>, - <&qos_sdio>, <&qos_sfc>; - }; - pd_vpu@PX30_PD_VPU { - reg = ; - clocks = <&cru ACLK_VPU>, - <&cru HCLK_VPU>, - <&cru SCLK_CORE_VPU>; - pm_qos = <&qos_vpu>, <&qos_vpu_r128>; - }; - pd_vo@PX30_PD_VO { - reg = ; - clocks = <&cru ACLK_RGA>, - <&cru ACLK_VOPB>, - <&cru ACLK_VOPL>, - <&cru DCLK_VOPB>, - <&cru DCLK_VOPL>, - <&cru HCLK_RGA>, - <&cru HCLK_VOPB>, - <&cru HCLK_VOPL>, - <&cru PCLK_MIPI_DSI>, - <&cru SCLK_RGA_CORE>, - <&cru SCLK_VOPB_PWM>; - pm_qos = <&qos_rga_rd>, <&qos_rga_wr>, - <&qos_vop_m0>, <&qos_vop_m1>; - }; - pd_vi@PX30_PD_VI { - reg = ; - clocks = <&cru ACLK_CIF>, - <&cru ACLK_ISP>, - <&cru HCLK_CIF>, - <&cru HCLK_ISP>, - <&cru SCLK_ISP>; - pm_qos = <&qos_isp_128>, <&qos_isp_rd>, - <&qos_isp_wr>, <&qos_isp_m1>, - <&qos_vip>; - }; - pd_gpu@PX30_PD_GPU { - reg = ; - clocks = <&cru SCLK_GPU>; - pm_qos = <&qos_gpu>; - }; - }; - }; - - pmugrf: syscon@ff010000 { - compatible = "rockchip,px30-pmugrf", "syscon", "simple-mfd"; - reg = <0x0 0xff010000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - - pmu_io_domains: io-domains { - compatible = "rockchip,px30-pmu-io-voltage-domain"; - status = "disabled"; - }; - - reboot-mode { - compatible = "syscon-reboot-mode"; - offset = <0x200>; - mode-bootloader = ; - mode-fastboot = ; - mode-loader = ; - mode-normal = ; - mode-recovery = ; - }; - }; - - uart0: serial@ff030000 { - compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; - reg = <0x0 0xff030000 0x0 0x100>; - interrupts = ; - clocks = <&pmucru SCLK_UART0_PMU>, <&pmucru PCLK_UART0_PMU>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac 0>, <&dmac 1>; - dma-names = "tx", "rx"; - reg-shift = <2>; - reg-io-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; - status = "disabled"; - }; - - i2s1_2ch: i2s@ff070000 { - compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s"; - reg = <0x0 0xff070000 0x0 0x1000>; - interrupts = ; - clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1>; - clock-names = "i2s_clk", "i2s_hclk"; - dmas = <&dmac 18>, <&dmac 19>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&i2s1_2ch_sclk &i2s1_2ch_lrck - &i2s1_2ch_sdi &i2s1_2ch_sdo>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - i2s2_2ch: i2s@ff080000 { - compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s"; - reg = <0x0 0xff080000 0x0 0x1000>; - interrupts = ; - clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2>; - clock-names = "i2s_clk", "i2s_hclk"; - dmas = <&dmac 20>, <&dmac 21>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&i2s2_2ch_sclk &i2s2_2ch_lrck - &i2s2_2ch_sdi &i2s2_2ch_sdo>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - gic: interrupt-controller@ff131000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x0 0xff131000 0 0x1000>, - <0x0 0xff132000 0 0x2000>, - <0x0 0xff134000 0 0x2000>, - <0x0 0xff136000 0 0x2000>; - interrupts = ; - }; - - grf: syscon@ff140000 { - compatible = "rockchip,px30-grf", "syscon", "simple-mfd"; - reg = <0x0 0xff140000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - - io_domains: io-domains { - compatible = "rockchip,px30-io-voltage-domain"; - status = "disabled"; - }; - - lvds: lvds { - compatible = "rockchip,px30-lvds"; - #address-cells = <1>; - #size-cells = <0>; - phys = <&dsi_dphy>; - phy-names = "dphy"; - rockchip,grf = <&grf>; - rockchip,output = "lvds"; - status = "disabled"; - - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - lvds_vopb_in: endpoint@0 { - reg = <0>; - remote-endpoint = <&vopb_out_lvds>; - }; - - lvds_vopl_in: endpoint@1 { - reg = <1>; - remote-endpoint = <&vopl_out_lvds>; - }; - }; - }; - }; - - uart1: serial@ff158000 { - compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; - reg = <0x0 0xff158000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac 2>, <&dmac 3>; - dma-names = "tx", "rx"; - reg-shift = <2>; - reg-io-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>; - status = "disabled"; - }; - - uart2: serial@ff160000 { - compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; - reg = <0x0 0xff160000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac 4>, <&dmac 5>; - dma-names = "tx", "rx"; - reg-shift = <2>; - reg-io-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&uart2m0_xfer>; - status = "disabled"; - }; - - uart3: serial@ff168000 { - compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; - reg = <0x0 0xff168000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac 6>, <&dmac 7>; - dma-names = "tx", "rx"; - reg-shift = <2>; - reg-io-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&uart3m1_xfer &uart3m1_cts &uart3m1_rts>; - status = "disabled"; - }; - - uart4: serial@ff170000 { - compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; - reg = <0x0 0xff170000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac 8>, <&dmac 9>; - dma-names = "tx", "rx"; - reg-shift = <2>; - reg-io-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>; - status = "disabled"; - }; - - uart5: serial@ff178000 { - compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; - reg = <0x0 0xff178000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac 10>, <&dmac 11>; - dma-names = "tx", "rx"; - reg-shift = <2>; - reg-io-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&uart5_xfer &uart5_cts &uart5_rts>; - status = "disabled"; - }; - - i2c0: i2c@ff180000 { - compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xff180000 0x0 0x1000>; - clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>; - clock-names = "i2c", "pclk"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_xfer>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c1: i2c@ff190000 { - compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xff190000 0x0 0x1000>; - clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; - clock-names = "i2c", "pclk"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_xfer>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@ff1a0000 { - compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xff1a0000 0x0 0x1000>; - clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; - clock-names = "i2c", "pclk"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_xfer>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c3: i2c@ff1b0000 { - compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xff1b0000 0x0 0x1000>; - clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; - clock-names = "i2c", "pclk"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_xfer>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi0: spi@ff1d0000 { - compatible = "rockchip,px30-spi", "rockchip,rk3066-spi"; - reg = <0x0 0xff1d0000 0x0 0x1000>; - interrupts = ; - clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; - clock-names = "spiclk", "apb_pclk"; - dmas = <&dmac 12>, <&dmac 13>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_clk &spi0_csn &spi0_miso &spi0_mosi>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi1: spi@ff1d8000 { - compatible = "rockchip,px30-spi", "rockchip,rk3066-spi"; - reg = <0x0 0xff1d8000 0x0 0x1000>; - interrupts = ; - clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; - clock-names = "spiclk", "apb_pclk"; - dmas = <&dmac 14>, <&dmac 15>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_csn1 &spi1_miso &spi1_mosi>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - wdt: watchdog@ff1e0000 { - compatible = "snps,dw-wdt"; - reg = <0x0 0xff1e0000 0x0 0x100>; - clocks = <&cru PCLK_WDT_NS>; - interrupts = ; - status = "disabled"; - }; - - pwm0: pwm@ff200000 { - compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xff200000 0x0 0x10>; - clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; - clock-names = "pwm", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pin>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm1: pwm@ff200010 { - compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xff200010 0x0 0x10>; - clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; - clock-names = "pwm", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm1_pin>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm2: pwm@ff200020 { - compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xff200020 0x0 0x10>; - clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; - clock-names = "pwm", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm2_pin>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm3: pwm@ff200030 { - compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xff200030 0x0 0x10>; - clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; - clock-names = "pwm", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm3_pin>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm4: pwm@ff208000 { - compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xff208000 0x0 0x10>; - clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; - clock-names = "pwm", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm4_pin>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm5: pwm@ff208010 { - compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xff208010 0x0 0x10>; - clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; - clock-names = "pwm", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm5_pin>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm6: pwm@ff208020 { - compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xff208020 0x0 0x10>; - clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; - clock-names = "pwm", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm6_pin>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm7: pwm@ff208030 { - compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xff208030 0x0 0x10>; - clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; - clock-names = "pwm", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm7_pin>; - #pwm-cells = <3>; - status = "disabled"; - }; - - rktimer: timer@ff210000 { - compatible = "rockchip,px30-timer", "rockchip,rk3288-timer"; - reg = <0x0 0xff210000 0x0 0x1000>; - interrupts = ; - clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>; - clock-names = "pclk", "timer"; - }; - - amba { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - dmac: dmac@ff240000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x0 0xff240000 0x0 0x4000>; - interrupts = , - ; - clocks = <&cru ACLK_DMAC>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - }; - }; - - tsadc: tsadc@ff280000 { - compatible = "rockchip,px30-tsadc"; - reg = <0x0 0xff280000 0x0 0x100>; - interrupts = ; - assigned-clocks = <&cru SCLK_TSADC>; - assigned-clock-rates = <50000>; - clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; - clock-names = "tsadc", "apb_pclk"; - resets = <&cru SRST_TSADC>; - reset-names = "tsadc-apb"; - rockchip,grf = <&grf>; - rockchip,hw-tshut-temp = <120000>; - pinctrl-names = "init", "default", "sleep"; - pinctrl-0 = <&tsadc_otp_gpio>; - pinctrl-1 = <&tsadc_otp_out>; - pinctrl-2 = <&tsadc_otp_gpio>; - #thermal-sensor-cells = <1>; - status = "disabled"; - }; - - saradc: saradc@ff288000 { - compatible = "rockchip,px30-saradc", "rockchip,rk3399-saradc"; - reg = <0x0 0xff288000 0x0 0x100>; - interrupts = ; - #io-channel-cells = <1>; - clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; - clock-names = "saradc", "apb_pclk"; - resets = <&cru SRST_SARADC_P>; - reset-names = "saradc-apb"; - status = "disabled"; - }; - - otp: nvmem@ff290000 { - compatible = "rockchip,px30-otp"; - reg = <0x0 0xff290000 0x0 0x4000>; - clocks = <&cru SCLK_OTP_USR>, <&cru PCLK_OTP_NS>, - <&cru PCLK_OTP_PHY>; - clock-names = "otp", "apb_pclk", "phy"; - resets = <&cru SRST_OTP_PHY>; - reset-names = "phy"; - #address-cells = <1>; - #size-cells = <1>; - - /* Data cells */ - cpu_id: id@7 { - reg = <0x07 0x10>; - }; - cpu_leakage: cpu-leakage@17 { - reg = <0x17 0x1>; - }; - performance: performance@1e { - reg = <0x1e 0x1>; - bits = <4 3>; - }; - }; - - cru: clock-controller@ff2b0000 { - compatible = "rockchip,px30-cru"; - reg = <0x0 0xff2b0000 0x0 0x1000>; - clocks = <&xin24m>, <&pmucru PLL_GPLL>; - clock-names = "xin24m", "gpll"; - rockchip,grf = <&grf>; - #clock-cells = <1>; - #reset-cells = <1>; - - assigned-clocks = <&cru PLL_NPLL>, - <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, - <&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>, - <&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>; - - assigned-clock-rates = <1188000000>, - <200000000>, <200000000>, - <150000000>, <150000000>, - <100000000>, <200000000>; - }; - - pmucru: clock-controller@ff2bc000 { - compatible = "rockchip,px30-pmucru"; - reg = <0x0 0xff2bc000 0x0 0x1000>; - clocks = <&xin24m>; - clock-names = "xin24m"; - rockchip,grf = <&grf>; - #clock-cells = <1>; - #reset-cells = <1>; - - assigned-clocks = - <&pmucru PLL_GPLL>, <&pmucru PCLK_PMU_PRE>, - <&pmucru SCLK_WIFI_PMU>; - assigned-clock-rates = - <1200000000>, <100000000>, - <26000000>; - }; - - usb2phy_grf: syscon@ff2c0000 { - compatible = "rockchip,px30-usb2phy-grf", "syscon", - "simple-mfd"; - reg = <0x0 0xff2c0000 0x0 0x10000>; - #address-cells = <1>; - #size-cells = <1>; - - u2phy: usb2-phy@100 { - compatible = "rockchip,px30-usb2phy"; - reg = <0x100 0x20>; - clocks = <&pmucru SCLK_USBPHY_REF>; - clock-names = "phyclk"; - #clock-cells = <0>; - assigned-clocks = <&cru USB480M>; - assigned-clock-parents = <&u2phy>; - clock-output-names = "usb480m_phy"; - status = "disabled"; - - u2phy_host: host-port { - #phy-cells = <0>; - interrupts = ; - interrupt-names = "linestate"; - status = "disabled"; - }; - - u2phy_otg: otg-port { - #phy-cells = <0>; - interrupts = , - , - ; - interrupt-names = "otg-bvalid", "otg-id", - "linestate"; - status = "disabled"; - }; - }; - }; - - dsi_dphy: phy@ff2e0000 { - compatible = "rockchip,px30-dsi-dphy"; - reg = <0x0 0xff2e0000 0x0 0x10000>; - clocks = <&pmucru SCLK_MIPIDSIPHY_REF>, <&cru PCLK_MIPIDSIPHY>; - clock-names = "ref", "pclk"; - resets = <&cru SRST_MIPIDSIPHY_P>; - reset-names = "apb"; - #phy-cells = <0>; - power-domains = <&power PX30_PD_VO>; - status = "disabled"; - }; - - usb20_otg: usb@ff300000 { - compatible = "rockchip,px30-usb", "rockchip,rk3066-usb", - "snps,dwc2"; - reg = <0x0 0xff300000 0x0 0x40000>; - interrupts = ; - clocks = <&cru HCLK_OTG>; - clock-names = "otg"; - dr_mode = "otg"; - g-np-tx-fifo-size = <16>; - g-rx-fifo-size = <280>; - g-tx-fifo-size = <256 128 128 64 32 16>; - g-use-dma; - phys = <&u2phy_otg>; - phy-names = "usb2-phy"; - power-domains = <&power PX30_PD_USB>; - status = "disabled"; - }; - - usb_host0_ehci: usb@ff340000 { - compatible = "generic-ehci"; - reg = <0x0 0xff340000 0x0 0x10000>; - interrupts = ; - clocks = <&cru HCLK_HOST>; - clock-names = "usbhost"; - phys = <&u2phy_host>; - phy-names = "usb"; - power-domains = <&power PX30_PD_USB>; - status = "disabled"; - }; - - usb_host0_ohci: usb@ff350000 { - compatible = "generic-ohci"; - reg = <0x0 0xff350000 0x0 0x10000>; - interrupts = ; - clocks = <&cru HCLK_HOST>; - clock-names = "usbhost"; - phys = <&u2phy_host>; - phy-names = "usb"; - power-domains = <&power PX30_PD_USB>; - status = "disabled"; - }; - - gmac: ethernet@ff360000 { - compatible = "rockchip,px30-gmac"; - reg = <0x0 0xff360000 0x0 0x10000>; - interrupts = ; - interrupt-names = "macirq"; - clocks = <&cru SCLK_GMAC>, <&cru SCLK_GMAC_RX_TX>, - <&cru SCLK_GMAC_RX_TX>, <&cru SCLK_MAC_REF>, - <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>, - <&cru PCLK_GMAC>, <&cru SCLK_GMAC_RMII>; - clock-names = "stmmaceth", "mac_clk_rx", - "mac_clk_tx", "clk_mac_ref", - "clk_mac_refout", "aclk_mac", - "pclk_mac", "clk_mac_speed"; - rockchip,grf = <&grf>; - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&rmii_pins &mac_refclk_12ma>; - power-domains = <&power PX30_PD_GMAC>; - resets = <&cru SRST_GMAC_A>; - reset-names = "stmmaceth"; - status = "disabled"; - }; - - sdmmc: mmc@ff370000 { - compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x0 0xff370000 0x0 0x4000>; - interrupts = ; - clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, - <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - max-frequency = <150000000>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; - power-domains = <&power PX30_PD_SDCARD>; - status = "disabled"; - }; - - sdio: mmc@ff380000 { - compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x0 0xff380000 0x0 0x4000>; - interrupts = ; - clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, - <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - max-frequency = <150000000>; - pinctrl-names = "default"; - pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>; - power-domains = <&power PX30_PD_MMC_NAND>; - status = "disabled"; - }; - - emmc: mmc@ff390000 { - compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x0 0xff390000 0x0 0x4000>; - interrupts = ; - clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, - <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - max-frequency = <150000000>; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; - power-domains = <&power PX30_PD_MMC_NAND>; - status = "disabled"; - }; - - gpu: gpu@ff400000 { - compatible = "rockchip,px30-mali", "arm,mali-bifrost"; - reg = <0x0 0xff400000 0x0 0x4000>; - interrupts = , - , - ; - interrupt-names = "job", "mmu", "gpu"; - clocks = <&cru SCLK_GPU>; - #cooling-cells = <2>; - power-domains = <&power PX30_PD_GPU>; - status = "disabled"; - }; - - dsi: dsi@ff450000 { - compatible = "rockchip,px30-mipi-dsi"; - reg = <0x0 0xff450000 0x0 0x10000>; - interrupts = ; - clocks = <&cru PCLK_MIPI_DSI>; - clock-names = "pclk"; - phys = <&dsi_dphy>; - phy-names = "dphy"; - power-domains = <&power PX30_PD_VO>; - resets = <&cru SRST_MIPIDSI_HOST_P>; - reset-names = "apb"; - rockchip,grf = <&grf>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - dsi_in_vopb: endpoint@0 { - reg = <0>; - remote-endpoint = <&vopb_out_dsi>; - }; - - dsi_in_vopl: endpoint@1 { - reg = <1>; - remote-endpoint = <&vopl_out_dsi>; - }; - }; - }; - }; - - vopb: vop@ff460000 { - compatible = "rockchip,px30-vop-big"; - reg = <0x0 0xff460000 0x0 0xefc>; - interrupts = ; - clocks = <&cru ACLK_VOPB>, <&cru DCLK_VOPB>, - <&cru HCLK_VOPB>; - clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; - resets = <&cru SRST_VOPB_A>, <&cru SRST_VOPB_H>, <&cru SRST_VOPB>; - reset-names = "axi", "ahb", "dclk"; - iommus = <&vopb_mmu>; - power-domains = <&power PX30_PD_VO>; - rockchip,grf = <&grf>; - status = "disabled"; - - vopb_out: port { - #address-cells = <1>; - #size-cells = <0>; - - vopb_out_dsi: endpoint@0 { - reg = <0>; - remote-endpoint = <&dsi_in_vopb>; - }; - - vopb_out_lvds: endpoint@1 { - reg = <1>; - remote-endpoint = <&lvds_vopb_in>; - }; - }; - }; - - vopb_mmu: iommu@ff460f00 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff460f00 0x0 0x100>; - interrupts = ; - interrupt-names = "vopb_mmu"; - clocks = <&cru ACLK_VOPB>, <&cru HCLK_VOPB>; - clock-names = "aclk", "iface"; - power-domains = <&power PX30_PD_VO>; - #iommu-cells = <0>; - status = "disabled"; - }; - - vopl: vop@ff470000 { - compatible = "rockchip,px30-vop-lit"; - reg = <0x0 0xff470000 0x0 0xefc>; - interrupts = ; - clocks = <&cru ACLK_VOPL>, <&cru DCLK_VOPL>, - <&cru HCLK_VOPL>; - clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; - resets = <&cru SRST_VOPL_A>, <&cru SRST_VOPL_H>, <&cru SRST_VOPL>; - reset-names = "axi", "ahb", "dclk"; - iommus = <&vopl_mmu>; - power-domains = <&power PX30_PD_VO>; - rockchip,grf = <&grf>; - status = "disabled"; - - vopl_out: port { - #address-cells = <1>; - #size-cells = <0>; - - vopl_out_dsi: endpoint@0 { - reg = <0>; - remote-endpoint = <&dsi_in_vopl>; - }; - - vopl_out_lvds: endpoint@1 { - reg = <1>; - remote-endpoint = <&lvds_vopl_in>; - }; - }; - }; - - vopl_mmu: iommu@ff470f00 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff470f00 0x0 0x100>; - interrupts = ; - interrupt-names = "vopl_mmu"; - clocks = <&cru ACLK_VOPL>, <&cru HCLK_VOPL>; - clock-names = "aclk", "iface"; - power-domains = <&power PX30_PD_VO>; - #iommu-cells = <0>; - status = "disabled"; - }; - - qos_gmac: qos@ff518000 { - compatible = "syscon"; - reg = <0x0 0xff518000 0x0 0x20>; - }; - - qos_gpu: qos@ff520000 { - compatible = "syscon"; - reg = <0x0 0xff520000 0x0 0x20>; - }; - - qos_sdmmc: qos@ff52c000 { - compatible = "syscon"; - reg = <0x0 0xff52c000 0x0 0x20>; - }; - - qos_emmc: qos@ff538000 { - compatible = "syscon"; - reg = <0x0 0xff538000 0x0 0x20>; - }; - - qos_nand: qos@ff538080 { - compatible = "syscon"; - reg = <0x0 0xff538080 0x0 0x20>; - }; - - qos_sdio: qos@ff538100 { - compatible = "syscon"; - reg = <0x0 0xff538100 0x0 0x20>; - }; - - qos_sfc: qos@ff538180 { - compatible = "syscon"; - reg = <0x0 0xff538180 0x0 0x20>; - }; - - qos_usb_host: qos@ff540000 { - compatible = "syscon"; - reg = <0x0 0xff540000 0x0 0x20>; - }; - - qos_usb_otg: qos@ff540080 { - compatible = "syscon"; - reg = <0x0 0xff540080 0x0 0x20>; - }; - - qos_isp_128: qos@ff548000 { - compatible = "syscon"; - reg = <0x0 0xff548000 0x0 0x20>; - }; - - qos_isp_rd: qos@ff548080 { - compatible = "syscon"; - reg = <0x0 0xff548080 0x0 0x20>; - }; - - qos_isp_wr: qos@ff548100 { - compatible = "syscon"; - reg = <0x0 0xff548100 0x0 0x20>; - }; - - qos_isp_m1: qos@ff548180 { - compatible = "syscon"; - reg = <0x0 0xff548180 0x0 0x20>; - }; - - qos_vip: qos@ff548200 { - compatible = "syscon"; - reg = <0x0 0xff548200 0x0 0x20>; - }; - - qos_rga_rd: qos@ff550000 { - compatible = "syscon"; - reg = <0x0 0xff550000 0x0 0x20>; - }; - - qos_rga_wr: qos@ff550080 { - compatible = "syscon"; - reg = <0x0 0xff550080 0x0 0x20>; - }; - - qos_vop_m0: qos@ff550100 { - compatible = "syscon"; - reg = <0x0 0xff550100 0x0 0x20>; - }; - - qos_vop_m1: qos@ff550180 { - compatible = "syscon"; - reg = <0x0 0xff550180 0x0 0x20>; - }; - - qos_vpu: qos@ff558000 { - compatible = "syscon"; - reg = <0x0 0xff558000 0x0 0x20>; - }; - - qos_vpu_r128: qos@ff558080 { - compatible = "syscon"; - reg = <0x0 0xff558080 0x0 0x20>; - }; - - pinctrl: pinctrl { - compatible = "rockchip,px30-pinctrl"; - rockchip,grf = <&grf>; - rockchip,pmu = <&pmugrf>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - gpio0: gpio0@ff040000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff040000 0x0 0x100>; - interrupts = ; - clocks = <&pmucru PCLK_GPIO0_PMU>; - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio1@ff250000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff250000 0x0 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO1>; - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio2@ff260000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff260000 0x0 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO2>; - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio3@ff270000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff270000 0x0 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO3>; - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - pcfg_pull_up: pcfg-pull-up { - bias-pull-up; - }; - - pcfg_pull_down: pcfg-pull-down { - bias-pull-down; - }; - - pcfg_pull_none: pcfg-pull-none { - bias-disable; - }; - - pcfg_pull_none_2ma: pcfg-pull-none-2ma { - bias-disable; - drive-strength = <2>; - }; - - pcfg_pull_up_2ma: pcfg-pull-up-2ma { - bias-pull-up; - drive-strength = <2>; - }; - - pcfg_pull_up_4ma: pcfg-pull-up-4ma { - bias-pull-up; - drive-strength = <4>; - }; - - pcfg_pull_none_4ma: pcfg-pull-none-4ma { - bias-disable; - drive-strength = <4>; - }; - - pcfg_pull_down_4ma: pcfg-pull-down-4ma { - bias-pull-down; - drive-strength = <4>; - }; - - pcfg_pull_none_8ma: pcfg-pull-none-8ma { - bias-disable; - drive-strength = <8>; - }; - - pcfg_pull_up_8ma: pcfg-pull-up-8ma { - bias-pull-up; - drive-strength = <8>; - }; - - pcfg_pull_none_12ma: pcfg-pull-none-12ma { - bias-disable; - drive-strength = <12>; - }; - - pcfg_pull_up_12ma: pcfg-pull-up-12ma { - bias-pull-up; - drive-strength = <12>; - }; - - pcfg_pull_none_smt: pcfg-pull-none-smt { - bias-disable; - input-schmitt-enable; - }; - - pcfg_output_high: pcfg-output-high { - output-high; - }; - - pcfg_output_low: pcfg-output-low { - output-low; - }; - - pcfg_input_high: pcfg-input-high { - bias-pull-up; - input-enable; - }; - - pcfg_input: pcfg-input { - input-enable; - }; - - i2c0 { - i2c0_xfer: i2c0-xfer { - rockchip,pins = - <0 RK_PB0 1 &pcfg_pull_none_smt>, - <0 RK_PB1 1 &pcfg_pull_none_smt>; - }; - }; - - i2c1 { - i2c1_xfer: i2c1-xfer { - rockchip,pins = - <0 RK_PC2 1 &pcfg_pull_none_smt>, - <0 RK_PC3 1 &pcfg_pull_none_smt>; - }; - }; - - i2c2 { - i2c2_xfer: i2c2-xfer { - rockchip,pins = - <2 RK_PB7 2 &pcfg_pull_none_smt>, - <2 RK_PC0 2 &pcfg_pull_none_smt>; - }; - }; - - i2c3 { - i2c3_xfer: i2c3-xfer { - rockchip,pins = - <1 RK_PB4 4 &pcfg_pull_none_smt>, - <1 RK_PB5 4 &pcfg_pull_none_smt>; - }; - }; - - tsadc { - tsadc_otp_gpio: tsadc-otp-gpio { - rockchip,pins = - <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - tsadc_otp_out: tsadc-otp-out { - rockchip,pins = - <0 RK_PA6 1 &pcfg_pull_none>; - }; - }; - - uart0 { - uart0_xfer: uart0-xfer { - rockchip,pins = - <0 RK_PB2 1 &pcfg_pull_up>, - <0 RK_PB3 1 &pcfg_pull_up>; - }; - - uart0_cts: uart0-cts { - rockchip,pins = - <0 RK_PB4 1 &pcfg_pull_none>; - }; - - uart0_rts: uart0-rts { - rockchip,pins = - <0 RK_PB5 1 &pcfg_pull_none>; - }; - }; - - uart1 { - uart1_xfer: uart1-xfer { - rockchip,pins = - <1 RK_PC1 1 &pcfg_pull_up>, - <1 RK_PC0 1 &pcfg_pull_up>; - }; - - uart1_cts: uart1-cts { - rockchip,pins = - <1 RK_PC2 1 &pcfg_pull_none>; - }; - - uart1_rts: uart1-rts { - rockchip,pins = - <1 RK_PC3 1 &pcfg_pull_none>; - }; - }; - - uart2-m0 { - uart2m0_xfer: uart2m0-xfer { - rockchip,pins = - <1 RK_PD2 2 &pcfg_pull_up>, - <1 RK_PD3 2 &pcfg_pull_up>; - }; - }; - - uart2-m1 { - uart2m1_xfer: uart2m1-xfer { - rockchip,pins = - <2 RK_PB4 2 &pcfg_pull_up>, - <2 RK_PB6 2 &pcfg_pull_up>; - }; - }; - - uart3-m0 { - uart3m0_xfer: uart3m0-xfer { - rockchip,pins = - <0 RK_PC0 2 &pcfg_pull_up>, - <0 RK_PC1 2 &pcfg_pull_up>; - }; - - uart3m0_cts: uart3m0-cts { - rockchip,pins = - <0 RK_PC2 2 &pcfg_pull_none>; - }; - - uart3m0_rts: uart3m0-rts { - rockchip,pins = - <0 RK_PC3 2 &pcfg_pull_none>; - }; - }; - - uart3-m1 { - uart3m1_xfer: uart3m1-xfer { - rockchip,pins = - <1 RK_PB6 2 &pcfg_pull_up>, - <1 RK_PB7 2 &pcfg_pull_up>; - }; - - uart3m1_cts: uart3m1-cts { - rockchip,pins = - <1 RK_PB4 2 &pcfg_pull_none>; - }; - - uart3m1_rts: uart3m1-rts { - rockchip,pins = - <1 RK_PB5 2 &pcfg_pull_none>; - }; - }; - - uart4 { - uart4_xfer: uart4-xfer { - rockchip,pins = - <1 RK_PD4 2 &pcfg_pull_up>, - <1 RK_PD5 2 &pcfg_pull_up>; - }; - - uart4_cts: uart4-cts { - rockchip,pins = - <1 RK_PD6 2 &pcfg_pull_none>; - }; - - uart4_rts: uart4-rts { - rockchip,pins = - <1 RK_PD7 2 &pcfg_pull_none>; - }; - }; - - uart5 { - uart5_xfer: uart5-xfer { - rockchip,pins = - <3 RK_PA2 4 &pcfg_pull_up>, - <3 RK_PA1 4 &pcfg_pull_up>; - }; - - uart5_cts: uart5-cts { - rockchip,pins = - <3 RK_PA3 4 &pcfg_pull_none>; - }; - - uart5_rts: uart5-rts { - rockchip,pins = - <3 RK_PA5 4 &pcfg_pull_none>; - }; - }; - - spi0 { - spi0_clk: spi0-clk { - rockchip,pins = - <1 RK_PB7 3 &pcfg_pull_up_4ma>; - }; - - spi0_csn: spi0-csn { - rockchip,pins = - <1 RK_PB6 3 &pcfg_pull_up_4ma>; - }; - - spi0_miso: spi0-miso { - rockchip,pins = - <1 RK_PB5 3 &pcfg_pull_up_4ma>; - }; - - spi0_mosi: spi0-mosi { - rockchip,pins = - <1 RK_PB4 3 &pcfg_pull_up_4ma>; - }; - - spi0_clk_hs: spi0-clk-hs { - rockchip,pins = - <1 RK_PB7 3 &pcfg_pull_up_8ma>; - }; - - spi0_miso_hs: spi0-miso-hs { - rockchip,pins = - <1 RK_PB5 3 &pcfg_pull_up_8ma>; - }; - - spi0_mosi_hs: spi0-mosi-hs { - rockchip,pins = - <1 RK_PB4 3 &pcfg_pull_up_8ma>; - }; - }; - - spi1 { - spi1_clk: spi1-clk { - rockchip,pins = - <3 RK_PB7 4 &pcfg_pull_up_4ma>; - }; - - spi1_csn0: spi1-csn0 { - rockchip,pins = - <3 RK_PB1 4 &pcfg_pull_up_4ma>; - }; - - spi1_csn1: spi1-csn1 { - rockchip,pins = - <3 RK_PB2 2 &pcfg_pull_up_4ma>; - }; - - spi1_miso: spi1-miso { - rockchip,pins = - <3 RK_PB6 4 &pcfg_pull_up_4ma>; - }; - - spi1_mosi: spi1-mosi { - rockchip,pins = - <3 RK_PB4 4 &pcfg_pull_up_4ma>; - }; - - spi1_clk_hs: spi1-clk-hs { - rockchip,pins = - <3 RK_PB7 4 &pcfg_pull_up_8ma>; - }; - - spi1_miso_hs: spi1-miso-hs { - rockchip,pins = - <3 RK_PB6 4 &pcfg_pull_up_8ma>; - }; - - spi1_mosi_hs: spi1-mosi-hs { - rockchip,pins = - <3 RK_PB4 4 &pcfg_pull_up_8ma>; - }; - }; - - pdm { - pdm_clk0m0: pdm-clk0m0 { - rockchip,pins = - <3 RK_PC6 2 &pcfg_pull_none>; - }; - - pdm_clk0m1: pdm-clk0m1 { - rockchip,pins = - <2 RK_PC6 1 &pcfg_pull_none>; - }; - - pdm_clk1: pdm-clk1 { - rockchip,pins = - <3 RK_PC7 2 &pcfg_pull_none>; - }; - - pdm_sdi0m0: pdm-sdi0m0 { - rockchip,pins = - <3 RK_PD3 2 &pcfg_pull_none>; - }; - - pdm_sdi0m1: pdm-sdi0m1 { - rockchip,pins = - <2 RK_PC5 2 &pcfg_pull_none>; - }; - - pdm_sdi1: pdm-sdi1 { - rockchip,pins = - <3 RK_PD0 2 &pcfg_pull_none>; - }; - - pdm_sdi2: pdm-sdi2 { - rockchip,pins = - <3 RK_PD1 2 &pcfg_pull_none>; - }; - - pdm_sdi3: pdm-sdi3 { - rockchip,pins = - <3 RK_PD2 2 &pcfg_pull_none>; - }; - - pdm_clk0m0_sleep: pdm-clk0m0-sleep { - rockchip,pins = - <3 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>; - }; - - pdm_clk0m_sleep1: pdm-clk0m1-sleep { - rockchip,pins = - <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>; - }; - - pdm_clk1_sleep: pdm-clk1-sleep { - rockchip,pins = - <3 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>; - }; - - pdm_sdi0m0_sleep: pdm-sdi0m0-sleep { - rockchip,pins = - <3 RK_PD3 RK_FUNC_GPIO &pcfg_input_high>; - }; - - pdm_sdi0m1_sleep: pdm-sdi0m1-sleep { - rockchip,pins = - <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>; - }; - - pdm_sdi1_sleep: pdm-sdi1-sleep { - rockchip,pins = - <3 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>; - }; - - pdm_sdi2_sleep: pdm-sdi2-sleep { - rockchip,pins = - <3 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>; - }; - - pdm_sdi3_sleep: pdm-sdi3-sleep { - rockchip,pins = - <3 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>; - }; - }; - - i2s0 { - i2s0_8ch_mclk: i2s0-8ch-mclk { - rockchip,pins = - <3 RK_PC1 2 &pcfg_pull_none>; - }; - - i2s0_8ch_sclktx: i2s0-8ch-sclktx { - rockchip,pins = - <3 RK_PC3 2 &pcfg_pull_none>; - }; - - i2s0_8ch_sclkrx: i2s0-8ch-sclkrx { - rockchip,pins = - <3 RK_PB4 2 &pcfg_pull_none>; - }; - - i2s0_8ch_lrcktx: i2s0-8ch-lrcktx { - rockchip,pins = - <3 RK_PC2 2 &pcfg_pull_none>; - }; - - i2s0_8ch_lrckrx: i2s0-8ch-lrckrx { - rockchip,pins = - <3 RK_PB5 2 &pcfg_pull_none>; - }; - - i2s0_8ch_sdo0: i2s0-8ch-sdo0 { - rockchip,pins = - <3 RK_PC4 2 &pcfg_pull_none>; - }; - - i2s0_8ch_sdo1: i2s0-8ch-sdo1 { - rockchip,pins = - <3 RK_PC0 2 &pcfg_pull_none>; - }; - - i2s0_8ch_sdo2: i2s0-8ch-sdo2 { - rockchip,pins = - <3 RK_PB7 2 &pcfg_pull_none>; - }; - - i2s0_8ch_sdo3: i2s0-8ch-sdo3 { - rockchip,pins = - <3 RK_PB6 2 &pcfg_pull_none>; - }; - - i2s0_8ch_sdi0: i2s0-8ch-sdi0 { - rockchip,pins = - <3 RK_PC5 2 &pcfg_pull_none>; - }; - - i2s0_8ch_sdi1: i2s0-8ch-sdi1 { - rockchip,pins = - <3 RK_PB3 2 &pcfg_pull_none>; - }; - - i2s0_8ch_sdi2: i2s0-8ch-sdi2 { - rockchip,pins = - <3 RK_PB1 2 &pcfg_pull_none>; - }; - - i2s0_8ch_sdi3: i2s0-8ch-sdi3 { - rockchip,pins = - <3 RK_PB0 2 &pcfg_pull_none>; - }; - }; - - i2s1 { - i2s1_2ch_mclk: i2s1-2ch-mclk { - rockchip,pins = - <2 RK_PC3 1 &pcfg_pull_none>; - }; - - i2s1_2ch_sclk: i2s1-2ch-sclk { - rockchip,pins = - <2 RK_PC2 1 &pcfg_pull_none>; - }; - - i2s1_2ch_lrck: i2s1-2ch-lrck { - rockchip,pins = - <2 RK_PC1 1 &pcfg_pull_none>; - }; - - i2s1_2ch_sdi: i2s1-2ch-sdi { - rockchip,pins = - <2 RK_PC5 1 &pcfg_pull_none>; - }; - - i2s1_2ch_sdo: i2s1-2ch-sdo { - rockchip,pins = - <2 RK_PC4 1 &pcfg_pull_none>; - }; - }; - - i2s2 { - i2s2_2ch_mclk: i2s2-2ch-mclk { - rockchip,pins = - <3 RK_PA1 2 &pcfg_pull_none>; - }; - - i2s2_2ch_sclk: i2s2-2ch-sclk { - rockchip,pins = - <3 RK_PA2 2 &pcfg_pull_none>; - }; - - i2s2_2ch_lrck: i2s2-2ch-lrck { - rockchip,pins = - <3 RK_PA3 2 &pcfg_pull_none>; - }; - - i2s2_2ch_sdi: i2s2-2ch-sdi { - rockchip,pins = - <3 RK_PA5 2 &pcfg_pull_none>; - }; - - i2s2_2ch_sdo: i2s2-2ch-sdo { - rockchip,pins = - <3 RK_PA7 2 &pcfg_pull_none>; - }; - }; - - sdmmc { - sdmmc_clk: sdmmc-clk { - rockchip,pins = - <1 RK_PD6 1 &pcfg_pull_none_8ma>; - }; - - sdmmc_cmd: sdmmc-cmd { - rockchip,pins = - <1 RK_PD7 1 &pcfg_pull_up_8ma>; - }; - - sdmmc_det: sdmmc-det { - rockchip,pins = - <0 RK_PA3 1 &pcfg_pull_up_8ma>; - }; - - sdmmc_bus1: sdmmc-bus1 { - rockchip,pins = - <1 RK_PD2 1 &pcfg_pull_up_8ma>; - }; - - sdmmc_bus4: sdmmc-bus4 { - rockchip,pins = - <1 RK_PD2 1 &pcfg_pull_up_8ma>, - <1 RK_PD3 1 &pcfg_pull_up_8ma>, - <1 RK_PD4 1 &pcfg_pull_up_8ma>, - <1 RK_PD5 1 &pcfg_pull_up_8ma>; - }; - }; - - sdio { - sdio_clk: sdio-clk { - rockchip,pins = - <1 RK_PC5 1 &pcfg_pull_none>; - }; - - sdio_cmd: sdio-cmd { - rockchip,pins = - <1 RK_PC4 1 &pcfg_pull_up>; - }; - - sdio_bus4: sdio-bus4 { - rockchip,pins = - <1 RK_PC6 1 &pcfg_pull_up>, - <1 RK_PC7 1 &pcfg_pull_up>, - <1 RK_PD0 1 &pcfg_pull_up>, - <1 RK_PD1 1 &pcfg_pull_up>; - }; - }; - - emmc { - emmc_clk: emmc-clk { - rockchip,pins = - <1 RK_PB1 2 &pcfg_pull_none_8ma>; - }; - - emmc_cmd: emmc-cmd { - rockchip,pins = - <1 RK_PB2 2 &pcfg_pull_up_8ma>; - }; - - emmc_rstnout: emmc-rstnout { - rockchip,pins = - <1 RK_PB3 2 &pcfg_pull_none>; - }; - - emmc_bus1: emmc-bus1 { - rockchip,pins = - <1 RK_PA0 2 &pcfg_pull_up_8ma>; - }; - - emmc_bus4: emmc-bus4 { - rockchip,pins = - <1 RK_PA0 2 &pcfg_pull_up_8ma>, - <1 RK_PA1 2 &pcfg_pull_up_8ma>, - <1 RK_PA2 2 &pcfg_pull_up_8ma>, - <1 RK_PA3 2 &pcfg_pull_up_8ma>; - }; - - emmc_bus8: emmc-bus8 { - rockchip,pins = - <1 RK_PA0 2 &pcfg_pull_up_8ma>, - <1 RK_PA1 2 &pcfg_pull_up_8ma>, - <1 RK_PA2 2 &pcfg_pull_up_8ma>, - <1 RK_PA3 2 &pcfg_pull_up_8ma>, - <1 RK_PA4 2 &pcfg_pull_up_8ma>, - <1 RK_PA5 2 &pcfg_pull_up_8ma>, - <1 RK_PA6 2 &pcfg_pull_up_8ma>, - <1 RK_PA7 2 &pcfg_pull_up_8ma>; - }; - }; - - flash { - flash_cs0: flash-cs0 { - rockchip,pins = - <1 RK_PB0 1 &pcfg_pull_none>; - }; - - flash_rdy: flash-rdy { - rockchip,pins = - <1 RK_PB1 1 &pcfg_pull_none>; - }; - - flash_dqs: flash-dqs { - rockchip,pins = - <1 RK_PB2 1 &pcfg_pull_none>; - }; - - flash_ale: flash-ale { - rockchip,pins = - <1 RK_PB3 1 &pcfg_pull_none>; - }; - - flash_cle: flash-cle { - rockchip,pins = - <1 RK_PB4 1 &pcfg_pull_none>; - }; - - flash_wrn: flash-wrn { - rockchip,pins = - <1 RK_PB5 1 &pcfg_pull_none>; - }; - - flash_csl: flash-csl { - rockchip,pins = - <1 RK_PB6 1 &pcfg_pull_none>; - }; - - flash_rdn: flash-rdn { - rockchip,pins = - <1 RK_PB7 1 &pcfg_pull_none>; - }; - - flash_bus8: flash-bus8 { - rockchip,pins = - <1 RK_PA0 1 &pcfg_pull_up_12ma>, - <1 RK_PA1 1 &pcfg_pull_up_12ma>, - <1 RK_PA2 1 &pcfg_pull_up_12ma>, - <1 RK_PA3 1 &pcfg_pull_up_12ma>, - <1 RK_PA4 1 &pcfg_pull_up_12ma>, - <1 RK_PA5 1 &pcfg_pull_up_12ma>, - <1 RK_PA6 1 &pcfg_pull_up_12ma>, - <1 RK_PA7 1 &pcfg_pull_up_12ma>; - }; - }; - - lcdc { - lcdc_rgb_dclk_pin: lcdc-rgb-dclk-pin { - rockchip,pins = - <3 RK_PA0 1 &pcfg_pull_none_12ma>; - }; - - lcdc_rgb_m0_hsync_pin: lcdc-rgb-m0-hsync-pin { - rockchip,pins = - <3 RK_PA1 1 &pcfg_pull_none_12ma>; - }; - - lcdc_rgb_m0_vsync_pin: lcdc-rgb-m0-vsync-pin { - rockchip,pins = - <3 RK_PA2 1 &pcfg_pull_none_12ma>; - }; - - lcdc_rgb_m0_den_pin: lcdc-rgb-m0-den-pin { - rockchip,pins = - <3 RK_PA3 1 &pcfg_pull_none_12ma>; - }; - - lcdc_rgb888_m0_data_pins: lcdc-rgb888-m0-data-pins { - rockchip,pins = - <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */ - <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ - <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */ - <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ - <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ - <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ - <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */ - <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */ - <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */ - <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */ - <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ - <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */ - <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ - <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ - <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ - <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */ - <3 RK_PC7 1 &pcfg_pull_none_8ma>, /* lcdc_d19 */ - <3 RK_PC6 1 &pcfg_pull_none_8ma>, /* lcdc_d18 */ - <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */ - <3 RK_PC4 1 &pcfg_pull_none_8ma>, /* lcdc_d16 */ - <3 RK_PD3 1 &pcfg_pull_none_8ma>, /* lcdc_d23 */ - <3 RK_PD2 1 &pcfg_pull_none_8ma>, /* lcdc_d22 */ - <3 RK_PD1 1 &pcfg_pull_none_8ma>, /* lcdc_d21 */ - <3 RK_PD0 1 &pcfg_pull_none_8ma>; /* lcdc_d20 */ - }; - - lcdc_rgb666_m0_data_pins: lcdc-rgb666-m0-data-pins { - rockchip,pins = - <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */ - <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ - <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */ - <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ - <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ - <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ - <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */ - <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */ - <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */ - <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */ - <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ - <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */ - <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ - <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ - <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ - <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */ - <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */ - <3 RK_PC4 1 &pcfg_pull_none_8ma>; /* lcdc_d16 */ - }; - - lcdc_rgb565_m0_data_pins: lcdc-rgb565-m0-data-pins { - rockchip,pins = - <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */ - <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ - <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */ - <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ - <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ - <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ - <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */ - <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */ - <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */ - <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */ - <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ - <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */ - <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ - <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ - <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ - <3 RK_PC0 1 &pcfg_pull_none_8ma>; /* lcdc_d12 */ - }; - - lcdc_rgb888_m1_data_pins: lcdc-rgb888-m1-data-pins { - rockchip,pins = - <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ - <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ - <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ - <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ - <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ - <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ - <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ - <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ - <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */ - <3 RK_PC7 1 &pcfg_pull_none_8ma>, /* lcdc_d19 */ - <3 RK_PC6 1 &pcfg_pull_none_8ma>, /* lcdc_d18 */ - <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */ - <3 RK_PC4 1 &pcfg_pull_none_8ma>, /* lcdc_d16 */ - <3 RK_PD3 1 &pcfg_pull_none_8ma>, /* lcdc_d23 */ - <3 RK_PD2 1 &pcfg_pull_none_8ma>, /* lcdc_d22 */ - <3 RK_PD1 1 &pcfg_pull_none_8ma>, /* lcdc_d21 */ - <3 RK_PD0 1 &pcfg_pull_none_8ma>; /* lcdc_d20 */ - }; - - lcdc_rgb666_m1_data_pins: lcdc-rgb666-m1-data-pins { - rockchip,pins = - <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ - <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ - <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ - <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ - <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ - <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ - <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ - <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ - <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */ - <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */ - <3 RK_PC4 1 &pcfg_pull_none_8ma>; /* lcdc_d16 */ - }; - - lcdc_rgb565_m1_data_pins: lcdc-rgb565-m1-data-pins { - rockchip,pins = - <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ - <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ - <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ - <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ - <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ - <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ - <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ - <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ - <3 RK_PC0 1 &pcfg_pull_none_8ma>; /* lcdc_d12 */ - }; - }; - - pwm0 { - pwm0_pin: pwm0-pin { - rockchip,pins = - <0 RK_PB7 1 &pcfg_pull_none>; - }; - }; - - pwm1 { - pwm1_pin: pwm1-pin { - rockchip,pins = - <0 RK_PC0 1 &pcfg_pull_none>; - }; - }; - - pwm2 { - pwm2_pin: pwm2-pin { - rockchip,pins = - <2 RK_PB5 1 &pcfg_pull_none>; - }; - }; - - pwm3 { - pwm3_pin: pwm3-pin { - rockchip,pins = - <0 RK_PC1 1 &pcfg_pull_none>; - }; - }; - - pwm4 { - pwm4_pin: pwm4-pin { - rockchip,pins = - <3 RK_PC2 3 &pcfg_pull_none>; - }; - }; - - pwm5 { - pwm5_pin: pwm5-pin { - rockchip,pins = - <3 RK_PC3 3 &pcfg_pull_none>; - }; - }; - - pwm6 { - pwm6_pin: pwm6-pin { - rockchip,pins = - <3 RK_PC4 3 &pcfg_pull_none>; - }; - }; - - pwm7 { - pwm7_pin: pwm7-pin { - rockchip,pins = - <3 RK_PC5 3 &pcfg_pull_none>; - }; - }; - - gmac { - rmii_pins: rmii-pins { - rockchip,pins = - <2 RK_PA0 2 &pcfg_pull_none_12ma>, /* mac_txen */ - <2 RK_PA1 2 &pcfg_pull_none_12ma>, /* mac_txd1 */ - <2 RK_PA2 2 &pcfg_pull_none_12ma>, /* mac_txd0 */ - <2 RK_PA3 2 &pcfg_pull_none>, /* mac_rxd0 */ - <2 RK_PA4 2 &pcfg_pull_none>, /* mac_rxd1 */ - <2 RK_PA5 2 &pcfg_pull_none>, /* mac_rxer */ - <2 RK_PA6 2 &pcfg_pull_none>, /* mac_rxdv */ - <2 RK_PA7 2 &pcfg_pull_none>, /* mac_mdio */ - <2 RK_PB1 2 &pcfg_pull_none>; /* mac_mdc */ - }; - - mac_refclk_12ma: mac-refclk-12ma { - rockchip,pins = - <2 RK_PB2 2 &pcfg_pull_none_12ma>; - }; - - mac_refclk: mac-refclk { - rockchip,pins = - <2 RK_PB2 2 &pcfg_pull_none>; - }; - }; - - cif-m0 { - cif_clkout_m0: cif-clkout-m0 { - rockchip,pins = - <2 RK_PB3 1 &pcfg_pull_none>; - }; - - dvp_d2d9_m0: dvp-d2d9-m0 { - rockchip,pins = - <2 RK_PA0 1 &pcfg_pull_none>, /* cif_data2 */ - <2 RK_PA1 1 &pcfg_pull_none>, /* cif_data3 */ - <2 RK_PA2 1 &pcfg_pull_none>, /* cif_data4 */ - <2 RK_PA3 1 &pcfg_pull_none>, /* cif_data5 */ - <2 RK_PA4 1 &pcfg_pull_none>, /* cif_data6 */ - <2 RK_PA5 1 &pcfg_pull_none>, /* cif_data7 */ - <2 RK_PA6 1 &pcfg_pull_none>, /* cif_data8 */ - <2 RK_PA7 1 &pcfg_pull_none>, /* cif_data9 */ - <2 RK_PB0 1 &pcfg_pull_none>, /* cif_sync */ - <2 RK_PB1 1 &pcfg_pull_none>, /* cif_href */ - <2 RK_PB2 1 &pcfg_pull_none>, /* cif_clkin */ - <2 RK_PB3 1 &pcfg_pull_none>; /* cif_clkout */ - }; - - dvp_d0d1_m0: dvp-d0d1-m0 { - rockchip,pins = - <2 RK_PB4 1 &pcfg_pull_none>, /* cif_data0 */ - <2 RK_PB6 1 &pcfg_pull_none>; /* cif_data1 */ - }; - - dvp_d10d11_m0:d10-d11-m0 { - rockchip,pins = - <2 RK_PB7 1 &pcfg_pull_none>, /* cif_data10 */ - <2 RK_PC0 1 &pcfg_pull_none>; /* cif_data11 */ - }; - }; - - cif-m1 { - cif_clkout_m1: cif-clkout-m1 { - rockchip,pins = - <3 RK_PD0 3 &pcfg_pull_none>; - }; - - dvp_d2d9_m1: dvp-d2d9-m1 { - rockchip,pins = - <3 RK_PA3 3 &pcfg_pull_none>, /* cif_data2 */ - <3 RK_PA5 3 &pcfg_pull_none>, /* cif_data3 */ - <3 RK_PA7 3 &pcfg_pull_none>, /* cif_data4 */ - <3 RK_PB0 3 &pcfg_pull_none>, /* cif_data5 */ - <3 RK_PB1 3 &pcfg_pull_none>, /* cif_data6 */ - <3 RK_PB4 3 &pcfg_pull_none>, /* cif_data7 */ - <3 RK_PB6 3 &pcfg_pull_none>, /* cif_data8 */ - <3 RK_PB7 3 &pcfg_pull_none>, /* cif_data9 */ - <3 RK_PD1 3 &pcfg_pull_none>, /* cif_sync */ - <3 RK_PD2 3 &pcfg_pull_none>, /* cif_href */ - <3 RK_PD3 3 &pcfg_pull_none>, /* cif_clkin */ - <3 RK_PD0 3 &pcfg_pull_none>; /* cif_clkout */ - }; - - dvp_d0d1_m1: dvp-d0d1-m1 { - rockchip,pins = - <3 RK_PA1 3 &pcfg_pull_none>, /* cif_data0 */ - <3 RK_PA2 3 &pcfg_pull_none>; /* cif_data1 */ - }; - - dvp_d10d11_m1:d10-d11-m1 { - rockchip,pins = - <3 RK_PC6 3 &pcfg_pull_none>, /* cif_data10 */ - <3 RK_PC7 3 &pcfg_pull_none>; /* cif_data11 */ - }; - }; - - isp { - isp_prelight: isp-prelight { - rockchip,pins = - <3 RK_PD1 4 &pcfg_pull_none>; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/rockchip/rk3308-evb.dts b/sys/gnu/dts/arm64/rockchip/rk3308-evb.dts deleted file mode 100644 index 9b4f855ea5d..00000000000 --- a/sys/gnu/dts/arm64/rockchip/rk3308-evb.dts +++ /dev/null @@ -1,230 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd - * - */ - -/dts-v1/; -#include -#include "rk3308.dtsi" - -/ { - model = "Rockchip RK3308 EVB"; - compatible = "rockchip,rk3308-evb", "rockchip,rk3308"; - - chosen { - stdout-path = "serial4:1500000n8"; - }; - - adc-keys0 { - compatible = "adc-keys"; - io-channels = <&saradc 0>; - io-channel-names = "buttons"; - poll-interval = <100>; - keyup-threshold-microvolt = <1800000>; - - func-key { - linux,code = ; - label = "function"; - press-threshold-microvolt = <18000>; - }; - }; - - adc-keys1 { - compatible = "adc-keys"; - io-channels = <&saradc 1>; - io-channel-names = "buttons"; - poll-interval = <100>; - keyup-threshold-microvolt = <1800000>; - - esc-key { - linux,code = ; - label = "micmute"; - press-threshold-microvolt = <1130000>; - }; - - home-key { - linux,code = ; - label = "mode"; - press-threshold-microvolt = <901000>; - }; - - menu-key { - linux,code = ; - label = "play"; - press-threshold-microvolt = <624000>; - }; - - vol-down-key { - linux,code = ; - label = "volume down"; - press-threshold-microvolt = <300000>; - }; - - vol-up-key { - linux,code = ; - label = "volume up"; - press-threshold-microvolt = <18000>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - - pinctrl-names = "default"; - pinctrl-0 = <&pwr_key>; - - power { - gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "GPIO Key Power"; - debounce-interval = <100>; - wakeup-source; - }; - }; - - vcc12v_dcin: vcc12v-dcin { - compatible = "regulator-fixed"; - regulator-name = "vcc12v_dcin"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-always-on; - regulator-boot-on; - }; - - vcc5v0_sys: vcc5v0-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc12v_dcin>; - }; - - vccio_sdio: vcc_1v8: vcc-1v8 { - compatible = "regulator-fixed"; - regulator-name = "vcc_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_io>; - }; - - vcc_ddr: vcc-ddr { - compatible = "regulator-fixed"; - regulator-name = "vcc_ddr"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc5v0_sys>; - }; - - vcc_io: vcc-io { - compatible = "regulator-fixed"; - regulator-name = "vcc_io"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc5v0_sys>; - }; - - vccio_flash: vccio-flash { - compatible = "regulator-fixed"; - regulator-name = "vccio_flash"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_io>; - }; - - vcc5v0_host: vcc5v0-host { - compatible = "regulator-fixed"; - gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; - enable-active-high; - pinctrl-names = "default"; - pinctrl-0 = <&usb_drv>; - regulator-name = "vbus_host"; - vin-supply = <&vcc5v0_sys>; - }; - - vdd_core: vdd-core { - compatible = "pwm-regulator"; - pwms = <&pwm0 0 5000 1>; - regulator-name = "vdd_core"; - regulator-min-microvolt = <827000>; - regulator-max-microvolt = <1340000>; - regulator-always-on; - regulator-boot-on; - regulator-settling-time-up-us = <250>; - pwm-supply = <&vcc5v0_sys>; - }; - - vdd_log: vdd-log { - compatible = "regulator-fixed"; - regulator-name = "vdd_log"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc5v0_sys>; - }; - - vdd_1v0: vdd-1v0 { - compatible = "regulator-fixed"; - regulator-name = "vdd_1v0"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc5v0_sys>; - }; -}; - -&cpu0 { - cpu-supply = <&vdd_core>; -}; - -&saradc { - status = "okay"; - vref-supply = <&vcc_1v8>; -}; - -&pinctrl { - pinctrl-names = "default"; - pinctrl-0 = <&rtc_32k>; - - buttons { - pwr_key: pwr-key { - rockchip,pins = <0 RK_PA6 0 &pcfg_pull_up>; - }; - }; - - usb { - usb_drv: usb-drv { - rockchip,pins = <0 RK_PC5 0 &pcfg_pull_none>; - }; - }; - - sdio-pwrseq { - wifi_enable_h: wifi-enable-h { - rockchip,pins = <0 RK_PA2 0 &pcfg_pull_none>; - }; - }; -}; - -&pwm0 { - status = "okay"; - pinctrl-0 = <&pwm0_pin_pull_down>; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&uart4_xfer>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/rockchip/rk3308-roc-cc.dts b/sys/gnu/dts/arm64/rockchip/rk3308-roc-cc.dts deleted file mode 100644 index aa256350b18..00000000000 --- a/sys/gnu/dts/arm64/rockchip/rk3308-roc-cc.dts +++ /dev/null @@ -1,188 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd - */ - -/dts-v1/; -#include "rk3308.dtsi" - -/ { - model = "Firefly ROC-RK3308-CC board"; - compatible = "firefly,roc-rk3308-cc", "rockchip,rk3308"; - chosen { - stdout-path = "serial2:1500000n8"; - }; - - ir_rx { - compatible = "gpio-ir-receiver"; - gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&ir_recv_pin>; - }; - - ir_tx { - compatible = "pwm-ir-tx"; - pwms = <&pwm5 0 25000 0>; - }; - - leds { - compatible = "gpio-leds"; - - power { - label = "firefly:red:power"; - linux,default-trigger = "ir-power-click"; - default-state = "on"; - gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; - }; - - user { - label = "firefly:blue:user"; - linux,default-trigger = "ir-user-click"; - default-state = "off"; - gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_HIGH>; - }; - }; - - typec_vcc5v: typec-vcc5v { - compatible = "regulator-fixed"; - regulator-name = "typec_vcc5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - vcc5v0_sys: vcc5v0-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&typec_vcc5v>; - }; - - vcc_io: vcc-io { - compatible = "regulator-fixed"; - regulator-name = "vcc_io"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc5v0_sys>; - }; - - vcc_sdmmc: vcc-sdmmc { - compatible = "regulator-gpio"; - regulator-name = "vcc_sdmmc"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_HIGH>; - states = <1800000 0x0 - 3300000 0x1>; - vin-supply = <&vcc5v0_sys>; - }; - - vcc_sd: vcc-sd { - compatible = "regulator-fixed"; - gpio = <&gpio4 RK_PD6 GPIO_ACTIVE_LOW>; - regulator-name = "vcc_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - vim-supply = <&vcc_io>; - }; - - vdd_core: vdd-core { - compatible = "pwm-regulator"; - pwms = <&pwm0 0 5000 1>; - regulator-name = "vdd_core"; - regulator-min-microvolt = <827000>; - regulator-max-microvolt = <1340000>; - regulator-init-microvolt = <1015000>; - regulator-settling-time-up-us = <250>; - regulator-always-on; - regulator-boot-on; - pwm-supply = <&vcc5v0_sys>; - }; - - vdd_log: vdd-log { - compatible = "regulator-fixed"; - regulator-name = "vdd_log"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc5v0_sys>; - }; -}; - -&cpu0 { - cpu-supply = <&vdd_core>; -}; - -&emmc { - bus-width = <8>; - cap-mmc-highspeed; - disable-wp; - mmc-hs200-1_8v; - non-removable; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <400000>; - status = "okay"; - - rtc: rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - #clock-cells = <0>; - }; -}; - -&pwm5 { - status = "okay"; - pinctrl-names = "active"; - pinctrl-0 = <&pwm5_pin_pull_down>; -}; - -&pinctrl { - pinctrl-names = "default"; - pinctrl-0 = <&rtc_32k>; - - ir-receiver { - ir_recv_pin: ir-recv-pin { - rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - buttons { - pwr_key: pwr-key { - rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; -}; - -&pwm0 { - status = "okay"; - pinctrl-0 = <&pwm0_pin_pull_down>; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - card-detect-delay = <300>; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-sdr104; - vmmc-supply = <&vcc_sd>; - vqmmc-supply = <&vcc_sdmmc>; - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/rockchip/rk3308.dtsi b/sys/gnu/dts/arm64/rockchip/rk3308.dtsi deleted file mode 100644 index 116f1900eff..00000000000 --- a/sys/gnu/dts/arm64/rockchip/rk3308.dtsi +++ /dev/null @@ -1,1739 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd - * - */ - -#include -#include -#include -#include -#include -#include -#include - -/ { - compatible = "rockchip,rk3308"; - - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - serial4 = &uart4; - spi0 = &spi0; - spi1 = &spi1; - spi2 = &spi2; - }; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a35", "arm,armv8"; - reg = <0x0 0x0>; - enable-method = "psci"; - clocks = <&cru ARMCLK>; - #cooling-cells = <2>; - dynamic-power-coefficient = <90>; - operating-points-v2 = <&cpu0_opp_table>; - cpu-idle-states = <&CPU_SLEEP>; - next-level-cache = <&l2>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a35", "arm,armv8"; - reg = <0x0 0x1>; - enable-method = "psci"; - operating-points-v2 = <&cpu0_opp_table>; - cpu-idle-states = <&CPU_SLEEP>; - next-level-cache = <&l2>; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a35", "arm,armv8"; - reg = <0x0 0x2>; - enable-method = "psci"; - operating-points-v2 = <&cpu0_opp_table>; - cpu-idle-states = <&CPU_SLEEP>; - next-level-cache = <&l2>; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a35", "arm,armv8"; - reg = <0x0 0x3>; - enable-method = "psci"; - operating-points-v2 = <&cpu0_opp_table>; - cpu-idle-states = <&CPU_SLEEP>; - next-level-cache = <&l2>; - }; - - idle-states { - entry-method = "psci"; - - CPU_SLEEP: cpu-sleep { - compatible = "arm,idle-state"; - local-timer-stop; - arm,psci-suspend-param = <0x0010000>; - entry-latency-us = <120>; - exit-latency-us = <250>; - min-residency-us = <900>; - }; - }; - - l2: l2-cache { - compatible = "cache"; - }; - }; - - cpu0_opp_table: cpu0-opp-table { - compatible = "operating-points-v2"; - opp-shared; - - opp-408000000 { - opp-hz = /bits/ 64 <408000000>; - opp-microvolt = <950000 950000 1340000>; - clock-latency-ns = <40000>; - opp-suspend; - }; - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <950000 950000 1340000>; - clock-latency-ns = <40000>; - }; - opp-816000000 { - opp-hz = /bits/ 64 <816000000>; - opp-microvolt = <1025000 1025000 1340000>; - clock-latency-ns = <40000>; - }; - opp-1008000000 { - opp-hz = /bits/ 64 <1008000000>; - opp-microvolt = <1125000 1125000 1340000>; - clock-latency-ns = <40000>; - }; - }; - - arm-pmu { - compatible = "arm,cortex-a53-pmu"; - interrupts = , - , - , - ; - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; - }; - - mac_clkin: external-mac-clock { - compatible = "fixed-clock"; - clock-frequency = <50000000>; - clock-output-names = "mac_clkin"; - #clock-cells = <0>; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - xin24m: xin24m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "xin24m"; - }; - - grf: grf@ff000000 { - compatible = "rockchip,rk3308-grf", "syscon", "simple-mfd"; - reg = <0x0 0xff000000 0x0 0x10000>; - - reboot-mode { - compatible = "syscon-reboot-mode"; - offset = <0x500>; - mode-bootloader = ; - mode-loader = ; - mode-normal = ; - mode-recovery = ; - mode-fastboot = ; - }; - }; - - detect_grf: syscon@ff00b000 { - compatible = "rockchip,rk3308-detect-grf", "syscon", "simple-mfd"; - reg = <0x0 0xff00b000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - }; - - core_grf: syscon@ff00c000 { - compatible = "rockchip,rk3308-core-grf", "syscon", "simple-mfd"; - reg = <0x0 0xff00c000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - }; - - i2c0: i2c@ff040000 { - compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xff040000 0x0 0x1000>; - clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>; - clock-names = "i2c", "pclk"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_xfer>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c1: i2c@ff050000 { - compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xff050000 0x0 0x1000>; - clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; - clock-names = "i2c", "pclk"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_xfer>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@ff060000 { - compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xff060000 0x0 0x1000>; - clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; - clock-names = "i2c", "pclk"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_xfer>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c3: i2c@ff070000 { - compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xff070000 0x0 0x1000>; - clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; - clock-names = "i2c", "pclk"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3m0_xfer>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - wdt: watchdog@ff080000 { - compatible = "snps,dw-wdt"; - reg = <0x0 0xff080000 0x0 0x100>; - clocks = <&cru PCLK_WDT>; - interrupts = ; - status = "disabled"; - }; - - uart0: serial@ff0a0000 { - compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; - reg = <0x0 0xff0a0000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; - clock-names = "baudclk", "apb_pclk"; - reg-shift = <2>; - reg-io-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; - status = "disabled"; - }; - - uart1: serial@ff0b0000 { - compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; - reg = <0x0 0xff0b0000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; - clock-names = "baudclk", "apb_pclk"; - reg-shift = <2>; - reg-io-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>; - status = "disabled"; - }; - - uart2: serial@ff0c0000 { - compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; - reg = <0x0 0xff0c0000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; - clock-names = "baudclk", "apb_pclk"; - reg-shift = <2>; - reg-io-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&uart2m0_xfer>; - status = "disabled"; - }; - - uart3: serial@ff0d0000 { - compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; - reg = <0x0 0xff0d0000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; - clock-names = "baudclk", "apb_pclk"; - reg-shift = <2>; - reg-io-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&uart3_xfer>; - status = "disabled"; - }; - - uart4: serial@ff0e0000 { - compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; - reg = <0x0 0xff0e0000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; - clock-names = "baudclk", "apb_pclk"; - reg-shift = <2>; - reg-io-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>; - status = "disabled"; - }; - - spi0: spi@ff120000 { - compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi"; - reg = <0x0 0xff120000 0x0 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; - clock-names = "spiclk", "apb_pclk"; - dmas = <&dmac0 0>, <&dmac0 1>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_clk &spi0_csn0 &spi0_miso &spi0_mosi>; - status = "disabled"; - }; - - spi1: spi@ff130000 { - compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi"; - reg = <0x0 0xff130000 0x0 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; - clock-names = "spiclk", "apb_pclk"; - dmas = <&dmac0 2>, <&dmac0 3>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_miso &spi1_mosi>; - status = "disabled"; - }; - - spi2: spi@ff140000 { - compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi"; - reg = <0x0 0xff140000 0x0 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; - clock-names = "spiclk", "apb_pclk"; - dmas = <&dmac1 16>, <&dmac1 17>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&spi2_clk &spi2_csn0 &spi2_miso &spi2_mosi>; - status = "disabled"; - }; - - pwm8: pwm@ff160000 { - compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xff160000 0x0 0x10>; - clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; - clock-names = "pwm", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm8_pin>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm9: pwm@ff160010 { - compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xff160010 0x0 0x10>; - clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; - clock-names = "pwm", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm9_pin>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm10: pwm@ff160020 { - compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xff160020 0x0 0x10>; - clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; - clock-names = "pwm", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm10_pin>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm11: pwm@ff160030 { - compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xff160030 0x0 0x10>; - clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; - clock-names = "pwm", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm11_pin>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm4: pwm@ff170000 { - compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xff170000 0x0 0x10>; - clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; - clock-names = "pwm", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm4_pin>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm5: pwm@ff170010 { - compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xff170010 0x0 0x10>; - clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; - clock-names = "pwm", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm5_pin>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm6: pwm@ff170020 { - compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xff170020 0x0 0x10>; - clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; - clock-names = "pwm", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm6_pin>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm7: pwm@ff170030 { - compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xff170030 0x0 0x10>; - clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; - clock-names = "pwm", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm7_pin>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm0: pwm@ff180000 { - compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xff180000 0x0 0x10>; - clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; - clock-names = "pwm", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pin>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm1: pwm@ff180010 { - compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xff180010 0x0 0x10>; - clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; - clock-names = "pwm", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm1_pin>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm2: pwm@ff180020 { - compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xff180020 0x0 0x10>; - clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; - clock-names = "pwm", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm2_pin>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm3: pwm@ff180030 { - compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xff180030 0x0 0x10>; - clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; - clock-names = "pwm", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm3_pin>; - #pwm-cells = <3>; - status = "disabled"; - }; - - rktimer: rktimer@ff1a0000 { - compatible = "rockchip,rk3288-timer"; - reg = <0x0 0xff1a0000 0x0 0x20>; - interrupts = ; - clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>; - clock-names = "pclk", "timer"; - }; - - saradc: saradc@ff1e0000 { - compatible = "rockchip,rk3308-saradc", "rockchip,rk3399-saradc"; - reg = <0x0 0xff1e0000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; - clock-names = "saradc", "apb_pclk"; - #io-channel-cells = <1>; - resets = <&cru SRST_SARADC_P>; - reset-names = "saradc-apb"; - status = "disabled"; - }; - - amba { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - dmac0: dma-controller@ff2c0000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x0 0xff2c0000 0x0 0x4000>; - interrupts = , - ; - clocks = <&cru ACLK_DMAC0>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - }; - - dmac1: dma-controller@ff2d0000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x0 0xff2d0000 0x0 0x4000>; - interrupts = , - ; - clocks = <&cru ACLK_DMAC1>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - }; - }; - - i2s_2ch_0: i2s@ff350000 { - compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s"; - reg = <0x0 0xff350000 0x0 0x1000>; - interrupts = ; - clocks = <&cru SCLK_I2S0_2CH>, <&cru HCLK_I2S0_2CH>; - clock-names = "i2s_clk", "i2s_hclk"; - dmas = <&dmac1 8>, <&dmac1 9>; - dma-names = "tx", "rx"; - resets = <&cru SRST_I2S0_2CH_M>, <&cru SRST_I2S0_2CH_H>; - reset-names = "reset-m", "reset-h"; - pinctrl-names = "default"; - pinctrl-0 = <&i2s_2ch_0_sclk - &i2s_2ch_0_lrck - &i2s_2ch_0_sdi - &i2s_2ch_0_sdo>; - status = "disabled"; - }; - - i2s_2ch_1: i2s@ff360000 { - compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s"; - reg = <0x0 0xff360000 0x0 0x1000>; - interrupts = ; - clocks = <&cru SCLK_I2S1_2CH>, <&cru HCLK_I2S1_2CH>; - clock-names = "i2s_clk", "i2s_hclk"; - dmas = <&dmac1 11>; - dma-names = "rx"; - resets = <&cru SRST_I2S1_2CH_M>, <&cru SRST_I2S1_2CH_H>; - reset-names = "reset-m", "reset-h"; - status = "disabled"; - }; - - spdif_tx: spdif-tx@ff3a0000 { - compatible = "rockchip,rk3308-spdif", "rockchip,rk3328-spdif"; - reg = <0x0 0xff3a0000 0x0 0x1000>; - interrupts = ; - clocks = <&cru SCLK_SPDIF_TX>, <&cru HCLK_SPDIFTX>; - clock-names = "mclk", "hclk"; - dmas = <&dmac1 13>; - dma-names = "tx"; - pinctrl-names = "default"; - pinctrl-0 = <&spdif_out>; - status = "disabled"; - }; - - sdmmc: mmc@ff480000 { - compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x0 0xff480000 0x0 0x4000>; - interrupts = ; - bus-width = <4>; - clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, - <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - max-frequency = <150000000>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; - status = "disabled"; - }; - - emmc: mmc@ff490000 { - compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x0 0xff490000 0x0 0x4000>; - interrupts = ; - bus-width = <8>; - clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, - <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - max-frequency = <150000000>; - status = "disabled"; - }; - - sdio: mmc@ff4a0000 { - compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x0 0xff4a0000 0x0 0x4000>; - interrupts = ; - bus-width = <4>; - clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, - <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - max-frequency = <150000000>; - pinctrl-names = "default"; - pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>; - status = "disabled"; - }; - - cru: clock-controller@ff500000 { - compatible = "rockchip,rk3308-cru"; - reg = <0x0 0xff500000 0x0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - rockchip,grf = <&grf>; - - assigned-clocks = <&cru SCLK_RTC32K>; - assigned-clock-rates = <32768>; - }; - - gic: interrupt-controller@ff580000 { - compatible = "arm,gic-400"; - reg = <0x0 0xff581000 0x0 0x1000>, - <0x0 0xff582000 0x0 0x2000>, - <0x0 0xff584000 0x0 0x2000>, - <0x0 0xff586000 0x0 0x2000>; - interrupts = ; - #interrupt-cells = <3>; - interrupt-controller; - #address-cells = <0>; - }; - - sram: sram@fff80000 { - compatible = "mmio-sram"; - reg = <0x0 0xfff80000 0x0 0x40000>; - ranges = <0 0x0 0xfff80000 0x40000>; - #address-cells = <1>; - #size-cells = <1>; - - /* reserved for ddr dvfs and system suspend/resume */ - ddr-sram@0 { - reg = <0x0 0x8000>; - }; - - /* reserved for vad audio buffer */ - vad_sram: vad-sram@8000 { - reg = <0x8000 0x38000>; - }; - }; - - pinctrl: pinctrl { - compatible = "rockchip,rk3308-pinctrl"; - rockchip,grf = <&grf>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - gpio0: gpio0@ff220000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff220000 0x0 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO0>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio1@ff230000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff230000 0x0 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO1>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio2@ff240000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff240000 0x0 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO2>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio3@ff250000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff250000 0x0 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO3>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio4: gpio4@ff260000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff260000 0x0 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO4>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - pcfg_pull_up: pcfg-pull-up { - bias-pull-up; - }; - - pcfg_pull_down: pcfg-pull-down { - bias-pull-down; - }; - - pcfg_pull_none: pcfg-pull-none { - bias-disable; - }; - - pcfg_pull_none_2ma: pcfg-pull-none-2ma { - bias-disable; - drive-strength = <2>; - }; - - pcfg_pull_up_2ma: pcfg-pull-up-2ma { - bias-pull-up; - drive-strength = <2>; - }; - - pcfg_pull_up_4ma: pcfg-pull-up-4ma { - bias-pull-up; - drive-strength = <4>; - }; - - pcfg_pull_none_4ma: pcfg-pull-none-4ma { - bias-disable; - drive-strength = <4>; - }; - - pcfg_pull_down_4ma: pcfg-pull-down-4ma { - bias-pull-down; - drive-strength = <4>; - }; - - pcfg_pull_none_8ma: pcfg-pull-none-8ma { - bias-disable; - drive-strength = <8>; - }; - - pcfg_pull_up_8ma: pcfg-pull-up-8ma { - bias-pull-up; - drive-strength = <8>; - }; - - pcfg_pull_none_12ma: pcfg-pull-none-12ma { - bias-disable; - drive-strength = <12>; - }; - - pcfg_pull_up_12ma: pcfg-pull-up-12ma { - bias-pull-up; - drive-strength = <12>; - }; - - pcfg_pull_none_smt: pcfg-pull-none-smt { - bias-disable; - input-schmitt-enable; - }; - - pcfg_output_high: pcfg-output-high { - output-high; - }; - - pcfg_output_low: pcfg-output-low { - output-low; - }; - - pcfg_input_high: pcfg-input-high { - bias-pull-up; - input-enable; - }; - - pcfg_input: pcfg-input { - input-enable; - }; - - emmc { - emmc_clk: emmc-clk { - rockchip,pins = - <3 RK_PB1 2 &pcfg_pull_none_8ma>; - }; - - emmc_cmd: emmc-cmd { - rockchip,pins = - <3 RK_PB0 2 &pcfg_pull_up_8ma>; - }; - - emmc_pwren: emmc-pwren { - rockchip,pins = - <3 RK_PB3 2 &pcfg_pull_none>; - }; - - emmc_rstn: emmc-rstn { - rockchip,pins = - <3 RK_PB2 2 &pcfg_pull_none>; - }; - - emmc_bus1: emmc-bus1 { - rockchip,pins = - <3 RK_PA0 2 &pcfg_pull_up_8ma>; - }; - - emmc_bus4: emmc-bus4 { - rockchip,pins = - <3 RK_PA0 2 &pcfg_pull_up_8ma>, - <3 RK_PA1 2 &pcfg_pull_up_8ma>, - <3 RK_PA2 2 &pcfg_pull_up_8ma>, - <3 RK_PA3 2 &pcfg_pull_up_8ma>; - }; - - emmc_bus8: emmc-bus8 { - rockchip,pins = - <3 RK_PA0 2 &pcfg_pull_up_8ma>, - <3 RK_PA1 2 &pcfg_pull_up_8ma>, - <3 RK_PA2 2 &pcfg_pull_up_8ma>, - <3 RK_PA3 2 &pcfg_pull_up_8ma>, - <3 RK_PA4 2 &pcfg_pull_up_8ma>, - <3 RK_PA5 2 &pcfg_pull_up_8ma>, - <3 RK_PA6 2 &pcfg_pull_up_8ma>, - <3 RK_PA7 2 &pcfg_pull_up_8ma>; - }; - }; - - flash { - flash_csn0: flash-csn0 { - rockchip,pins = - <3 RK_PB5 1 &pcfg_pull_none>; - }; - - flash_rdy: flash-rdy { - rockchip,pins = - <3 RK_PB4 1 &pcfg_pull_none>; - }; - - flash_ale: flash-ale { - rockchip,pins = - <3 RK_PB3 1 &pcfg_pull_none>; - }; - - flash_cle: flash-cle { - rockchip,pins = - <3 RK_PB1 1 &pcfg_pull_none>; - }; - - flash_wrn: flash-wrn { - rockchip,pins = - <3 RK_PB0 1 &pcfg_pull_none>; - }; - - flash_rdn: flash-rdn { - rockchip,pins = - <3 RK_PB2 1 &pcfg_pull_none>; - }; - - flash_bus8: flash-bus8 { - rockchip,pins = - <3 RK_PA0 1 &pcfg_pull_up_12ma>, - <3 RK_PA1 1 &pcfg_pull_up_12ma>, - <3 RK_PA2 1 &pcfg_pull_up_12ma>, - <3 RK_PA3 1 &pcfg_pull_up_12ma>, - <3 RK_PA4 1 &pcfg_pull_up_12ma>, - <3 RK_PA5 1 &pcfg_pull_up_12ma>, - <3 RK_PA6 1 &pcfg_pull_up_12ma>, - <3 RK_PA7 1 &pcfg_pull_up_12ma>; - }; - }; - - gmac { - rmii_pins: rmii-pins { - rockchip,pins = - /* mac_txen */ - <1 RK_PC1 3 &pcfg_pull_none_12ma>, - /* mac_txd1 */ - <1 RK_PC3 3 &pcfg_pull_none_12ma>, - /* mac_txd0 */ - <1 RK_PC2 3 &pcfg_pull_none_12ma>, - /* mac_rxd0 */ - <1 RK_PC4 3 &pcfg_pull_none>, - /* mac_rxd1 */ - <1 RK_PC5 3 &pcfg_pull_none>, - /* mac_rxer */ - <1 RK_PB7 3 &pcfg_pull_none>, - /* mac_rxdv */ - <1 RK_PC0 3 &pcfg_pull_none>, - /* mac_mdio */ - <1 RK_PB6 3 &pcfg_pull_none>, - /* mac_mdc */ - <1 RK_PB5 3 &pcfg_pull_none>; - }; - - mac_refclk_12ma: mac-refclk-12ma { - rockchip,pins = - <1 RK_PB4 3 &pcfg_pull_none_12ma>; - }; - - mac_refclk: mac-refclk { - rockchip,pins = - <1 RK_PB4 3 &pcfg_pull_none>; - }; - }; - - gmac-m1 { - rmiim1_pins: rmiim1-pins { - rockchip,pins = - /* mac_txen */ - <4 RK_PB7 2 &pcfg_pull_none_12ma>, - /* mac_txd1 */ - <4 RK_PA5 2 &pcfg_pull_none_12ma>, - /* mac_txd0 */ - <4 RK_PA4 2 &pcfg_pull_none_12ma>, - /* mac_rxd0 */ - <4 RK_PA2 2 &pcfg_pull_none>, - /* mac_rxd1 */ - <4 RK_PA3 2 &pcfg_pull_none>, - /* mac_rxer */ - <4 RK_PA0 2 &pcfg_pull_none>, - /* mac_rxdv */ - <4 RK_PA1 2 &pcfg_pull_none>, - /* mac_mdio */ - <4 RK_PB6 2 &pcfg_pull_none>, - /* mac_mdc */ - <4 RK_PB5 2 &pcfg_pull_none>; - }; - - macm1_refclk_12ma: macm1-refclk-12ma { - rockchip,pins = - <4 RK_PB4 2 &pcfg_pull_none_12ma>; - }; - - macm1_refclk: macm1-refclk { - rockchip,pins = - <4 RK_PB4 2 &pcfg_pull_none>; - }; - }; - - i2c0 { - i2c0_xfer: i2c0-xfer { - rockchip,pins = - <1 RK_PD0 2 &pcfg_pull_none_smt>, - <1 RK_PD1 2 &pcfg_pull_none_smt>; - }; - }; - - i2c1 { - i2c1_xfer: i2c1-xfer { - rockchip,pins = - <0 RK_PB3 1 &pcfg_pull_none_smt>, - <0 RK_PB4 1 &pcfg_pull_none_smt>; - }; - }; - - i2c2 { - i2c2_xfer: i2c2-xfer { - rockchip,pins = - <2 RK_PA2 3 &pcfg_pull_none_smt>, - <2 RK_PA3 3 &pcfg_pull_none_smt>; - }; - }; - - i2c3-m0 { - i2c3m0_xfer: i2c3m0-xfer { - rockchip,pins = - <0 RK_PB7 2 &pcfg_pull_none_smt>, - <0 RK_PC0 2 &pcfg_pull_none_smt>; - }; - }; - - i2c3-m1 { - i2c3m1_xfer: i2c3m1-xfer { - rockchip,pins = - <3 RK_PB4 2 &pcfg_pull_none_smt>, - <3 RK_PB5 2 &pcfg_pull_none_smt>; - }; - }; - - i2c3-m2 { - i2c3m2_xfer: i2c3m2-xfer { - rockchip,pins = - <2 RK_PA1 3 &pcfg_pull_none_smt>, - <2 RK_PA0 3 &pcfg_pull_none_smt>; - }; - }; - - i2s_2ch_0 { - i2s_2ch_0_mclk: i2s-2ch-0-mclk { - rockchip,pins = - <4 RK_PB4 1 &pcfg_pull_none>; - }; - - i2s_2ch_0_sclk: i2s-2ch-0-sclk { - rockchip,pins = - <4 RK_PB5 1 &pcfg_pull_none>; - }; - - i2s_2ch_0_lrck: i2s-2ch-0-lrck { - rockchip,pins = - <4 RK_PB6 1 &pcfg_pull_none>; - }; - - i2s_2ch_0_sdo: i2s-2ch-0-sdo { - rockchip,pins = - <4 RK_PB7 1 &pcfg_pull_none>; - }; - - i2s_2ch_0_sdi: i2s-2ch-0-sdi { - rockchip,pins = - <4 RK_PC0 1 &pcfg_pull_none>; - }; - }; - - i2s_8ch_0 { - i2s_8ch_0_mclk: i2s-8ch-0-mclk { - rockchip,pins = - <2 RK_PA4 1 &pcfg_pull_none>; - }; - - i2s_8ch_0_sclktx: i2s-8ch-0-sclktx { - rockchip,pins = - <2 RK_PA5 1 &pcfg_pull_none>; - }; - - i2s_8ch_0_sclkrx: i2s-8ch-0-sclkrx { - rockchip,pins = - <2 RK_PA6 1 &pcfg_pull_none>; - }; - - i2s_8ch_0_lrcktx: i2s-8ch-0-lrcktx { - rockchip,pins = - <2 RK_PA7 1 &pcfg_pull_none>; - }; - - i2s_8ch_0_lrckrx: i2s-8ch-0-lrckrx { - rockchip,pins = - <2 RK_PB0 1 &pcfg_pull_none>; - }; - - i2s_8ch_0_sdo0: i2s-8ch-0-sdo0 { - rockchip,pins = - <2 RK_PB1 1 &pcfg_pull_none>; - }; - - i2s_8ch_0_sdo1: i2s-8ch-0-sdo1 { - rockchip,pins = - <2 RK_PB2 1 &pcfg_pull_none>; - }; - - i2s_8ch_0_sdo2: i2s-8ch-0-sdo2 { - rockchip,pins = - <2 RK_PB3 1 &pcfg_pull_none>; - }; - - i2s_8ch_0_sdo3: i2s-8ch-0-sdo3 { - rockchip,pins = - <2 RK_PB4 1 &pcfg_pull_none>; - }; - - i2s_8ch_0_sdi0: i2s-8ch-0-sdi0 { - rockchip,pins = - <2 RK_PB5 1 &pcfg_pull_none>; - }; - - i2s_8ch_0_sdi1: i2s-8ch-0-sdi1 { - rockchip,pins = - <2 RK_PB6 1 &pcfg_pull_none>; - }; - - i2s_8ch_0_sdi2: i2s-8ch-0-sdi2 { - rockchip,pins = - <2 RK_PB7 1 &pcfg_pull_none>; - }; - - i2s_8ch_0_sdi3: i2s-8ch-0-sdi3 { - rockchip,pins = - <2 RK_PC0 1 &pcfg_pull_none>; - }; - }; - - i2s_8ch_1_m0 { - i2s_8ch_1_m0_mclk: i2s-8ch-1-m0-mclk { - rockchip,pins = - <1 RK_PA2 2 &pcfg_pull_none>; - }; - - i2s_8ch_1_m0_sclktx: i2s-8ch-1-m0-sclktx { - rockchip,pins = - <1 RK_PA3 2 &pcfg_pull_none>; - }; - - i2s_8ch_1_m0_sclkrx: i2s-8ch-1-m0-sclkrx { - rockchip,pins = - <1 RK_PA4 2 &pcfg_pull_none>; - }; - - i2s_8ch_1_m0_lrcktx: i2s-8ch-1-m0-lrcktx { - rockchip,pins = - <1 RK_PA5 2 &pcfg_pull_none>; - }; - - i2s_8ch_1_m0_lrckrx: i2s-8ch-1-m0-lrckrx { - rockchip,pins = - <1 RK_PA6 2 &pcfg_pull_none>; - }; - - i2s_8ch_1_m0_sdo0: i2s-8ch-1-m0-sdo0 { - rockchip,pins = - <1 RK_PA7 2 &pcfg_pull_none>; - }; - - i2s_8ch_1_m0_sdo1_sdi3: i2s-8ch-1-m0-sdo1-sdi3 { - rockchip,pins = - <1 RK_PB0 2 &pcfg_pull_none>; - }; - - i2s_8ch_1_m0_sdo2_sdi2: i2s-8ch-1-m0-sdo2-sdi2 { - rockchip,pins = - <1 RK_PB1 2 &pcfg_pull_none>; - }; - - i2s_8ch_1_m0_sdo3_sdi1: i2s-8ch-1-m0-sdo3_sdi1 { - rockchip,pins = - <1 RK_PB2 2 &pcfg_pull_none>; - }; - - i2s_8ch_1_m0_sdi0: i2s-8ch-1-m0-sdi0 { - rockchip,pins = - <1 RK_PB3 2 &pcfg_pull_none>; - }; - }; - - i2s_8ch_1_m1 { - i2s_8ch_1_m1_mclk: i2s-8ch-1-m1-mclk { - rockchip,pins = - <1 RK_PB4 2 &pcfg_pull_none>; - }; - - i2s_8ch_1_m1_sclktx: i2s-8ch-1-m1-sclktx { - rockchip,pins = - <1 RK_PB5 2 &pcfg_pull_none>; - }; - - i2s_8ch_1_m1_sclkrx: i2s-8ch-1-m1-sclkrx { - rockchip,pins = - <1 RK_PB6 2 &pcfg_pull_none>; - }; - - i2s_8ch_1_m1_lrcktx: i2s-8ch-1-m1-lrcktx { - rockchip,pins = - <1 RK_PB7 2 &pcfg_pull_none>; - }; - - i2s_8ch_1_m1_lrckrx: i2s-8ch-1-m1-lrckrx { - rockchip,pins = - <1 RK_PC0 2 &pcfg_pull_none>; - }; - - i2s_8ch_1_m1_sdo0: i2s-8ch-1-m1-sdo0 { - rockchip,pins = - <1 RK_PC1 2 &pcfg_pull_none>; - }; - - i2s_8ch_1_m1_sdo1_sdi3: i2s-8ch-1-m1-sdo1-sdi3 { - rockchip,pins = - <1 RK_PC2 2 &pcfg_pull_none>; - }; - - i2s_8ch_1_m1_sdo2_sdi2: i2s-8ch-1-m1-sdo2-sdi2 { - rockchip,pins = - <1 RK_PC3 2 &pcfg_pull_none>; - }; - - i2s_8ch_1_m1_sdo3_sdi1: i2s-8ch-1-m1-sdo3_sdi1 { - rockchip,pins = - <1 RK_PC4 2 &pcfg_pull_none>; - }; - - i2s_8ch_1_m1_sdi0: i2s-8ch-1-m1-sdi0 { - rockchip,pins = - <1 RK_PC5 2 &pcfg_pull_none>; - }; - }; - - pdm_m0 { - pdm_m0_clk: pdm-m0-clk { - rockchip,pins = - <1 RK_PA4 3 &pcfg_pull_none>; - }; - - pdm_m0_sdi0: pdm-m0-sdi0 { - rockchip,pins = - <1 RK_PB3 3 &pcfg_pull_none>; - }; - - pdm_m0_sdi1: pdm-m0-sdi1 { - rockchip,pins = - <1 RK_PB2 3 &pcfg_pull_none>; - }; - - pdm_m0_sdi2: pdm-m0-sdi2 { - rockchip,pins = - <1 RK_PB1 3 &pcfg_pull_none>; - }; - - pdm_m0_sdi3: pdm-m0-sdi3 { - rockchip,pins = - <1 RK_PB0 3 &pcfg_pull_none>; - }; - }; - - pdm_m1 { - pdm_m1_clk: pdm-m1-clk { - rockchip,pins = - <1 RK_PB6 4 &pcfg_pull_none>; - }; - - pdm_m1_sdi0: pdm-m1-sdi0 { - rockchip,pins = - <1 RK_PC5 4 &pcfg_pull_none>; - }; - - pdm_m1_sdi1: pdm-m1-sdi1 { - rockchip,pins = - <1 RK_PC4 4 &pcfg_pull_none>; - }; - - pdm_m1_sdi2: pdm-m1-sdi2 { - rockchip,pins = - <1 RK_PC3 4 &pcfg_pull_none>; - }; - - pdm_m1_sdi3: pdm-m1-sdi3 { - rockchip,pins = - <1 RK_PC2 4 &pcfg_pull_none>; - }; - }; - - pdm_m2 { - pdm_m2_clkm: pdm-m2-clkm { - rockchip,pins = - <2 RK_PA4 3 &pcfg_pull_none>; - }; - - pdm_m2_clk: pdm-m2-clk { - rockchip,pins = - <2 RK_PA6 2 &pcfg_pull_none>; - }; - - pdm_m2_sdi0: pdm-m2-sdi0 { - rockchip,pins = - <2 RK_PB5 2 &pcfg_pull_none>; - }; - - pdm_m2_sdi1: pdm-m2-sdi1 { - rockchip,pins = - <2 RK_PB6 2 &pcfg_pull_none>; - }; - - pdm_m2_sdi2: pdm-m2-sdi2 { - rockchip,pins = - <2 RK_PB7 2 &pcfg_pull_none>; - }; - - pdm_m2_sdi3: pdm-m2-sdi3 { - rockchip,pins = - <2 RK_PC0 2 &pcfg_pull_none>; - }; - }; - - pwm0 { - pwm0_pin: pwm0-pin { - rockchip,pins = - <0 RK_PB5 1 &pcfg_pull_none>; - }; - - pwm0_pin_pull_down: pwm0-pin-pull-down { - rockchip,pins = - <0 RK_PB5 1 &pcfg_pull_down>; - }; - }; - - pwm1 { - pwm1_pin: pwm1-pin { - rockchip,pins = - <0 RK_PB6 1 &pcfg_pull_none>; - }; - - pwm1_pin_pull_down: pwm1-pin-pull-down { - rockchip,pins = - <0 RK_PB6 1 &pcfg_pull_down>; - }; - }; - - pwm2 { - pwm2_pin: pwm2-pin { - rockchip,pins = - <0 RK_PB7 1 &pcfg_pull_none>; - }; - - pwm2_pin_pull_down: pwm2-pin-pull-down { - rockchip,pins = - <0 RK_PB7 1 &pcfg_pull_down>; - }; - }; - - pwm3 { - pwm3_pin: pwm3-pin { - rockchip,pins = - <0 RK_PC0 1 &pcfg_pull_none>; - }; - - pwm3_pin_pull_down: pwm3-pin-pull-down { - rockchip,pins = - <0 RK_PC0 1 &pcfg_pull_down>; - }; - }; - - pwm4 { - pwm4_pin: pwm4-pin { - rockchip,pins = - <0 RK_PA1 2 &pcfg_pull_none>; - }; - - pwm4_pin_pull_down: pwm4-pin-pull-down { - rockchip,pins = - <0 RK_PA1 2 &pcfg_pull_down>; - }; - }; - - pwm5 { - pwm5_pin: pwm5-pin { - rockchip,pins = - <0 RK_PC1 2 &pcfg_pull_none>; - }; - - pwm5_pin_pull_down: pwm5-pin-pull-down { - rockchip,pins = - <0 RK_PC1 2 &pcfg_pull_down>; - }; - }; - - pwm6 { - pwm6_pin: pwm6-pin { - rockchip,pins = - <0 RK_PC2 2 &pcfg_pull_none>; - }; - - pwm6_pin_pull_down: pwm6-pin-pull-down { - rockchip,pins = - <0 RK_PC2 2 &pcfg_pull_down>; - }; - }; - - pwm7 { - pwm7_pin: pwm7-pin { - rockchip,pins = - <2 RK_PB0 2 &pcfg_pull_none>; - }; - - pwm7_pin_pull_down: pwm7-pin-pull-down { - rockchip,pins = - <2 RK_PB0 2 &pcfg_pull_down>; - }; - }; - - pwm8 { - pwm8_pin: pwm8-pin { - rockchip,pins = - <2 RK_PB2 2 &pcfg_pull_none>; - }; - - pwm8_pin_pull_down: pwm8-pin-pull-down { - rockchip,pins = - <2 RK_PB2 2 &pcfg_pull_down>; - }; - }; - - pwm9 { - pwm9_pin: pwm9-pin { - rockchip,pins = - <2 RK_PB3 2 &pcfg_pull_none>; - }; - - pwm9_pin_pull_down: pwm9-pin-pull-down { - rockchip,pins = - <2 RK_PB3 2 &pcfg_pull_down>; - }; - }; - - pwm10 { - pwm10_pin: pwm10-pin { - rockchip,pins = - <2 RK_PB4 2 &pcfg_pull_none>; - }; - - pwm10_pin_pull_down: pwm10-pin-pull-down { - rockchip,pins = - <2 RK_PB4 2 &pcfg_pull_down>; - }; - }; - - pwm11 { - pwm11_pin: pwm11-pin { - rockchip,pins = - <2 RK_PC0 4 &pcfg_pull_none>; - }; - - pwm11_pin_pull_down: pwm11-pin-pull-down { - rockchip,pins = - <2 RK_PC0 4 &pcfg_pull_down>; - }; - }; - - rtc { - rtc_32k: rtc-32k { - rockchip,pins = - <0 RK_PC3 1 &pcfg_pull_none>; - }; - }; - - sdmmc { - sdmmc_clk: sdmmc-clk { - rockchip,pins = - <4 RK_PD5 1 &pcfg_pull_none_4ma>; - }; - - sdmmc_cmd: sdmmc-cmd { - rockchip,pins = - <4 RK_PD4 1 &pcfg_pull_up_4ma>; - }; - - sdmmc_det: sdmmc-det { - rockchip,pins = - <0 RK_PA3 1 &pcfg_pull_up_4ma>; - }; - - sdmmc_pwren: sdmmc-pwren { - rockchip,pins = - <4 RK_PD6 1 &pcfg_pull_none_4ma>; - }; - - sdmmc_bus1: sdmmc-bus1 { - rockchip,pins = - <4 RK_PD0 1 &pcfg_pull_up_4ma>; - }; - - sdmmc_bus4: sdmmc-bus4 { - rockchip,pins = - <4 RK_PD0 1 &pcfg_pull_up_4ma>, - <4 RK_PD1 1 &pcfg_pull_up_4ma>, - <4 RK_PD2 1 &pcfg_pull_up_4ma>, - <4 RK_PD3 1 &pcfg_pull_up_4ma>; - }; - }; - - sdio { - sdio_clk: sdio-clk { - rockchip,pins = - <4 RK_PA5 1 &pcfg_pull_none_8ma>; - }; - - sdio_cmd: sdio-cmd { - rockchip,pins = - <4 RK_PA4 1 &pcfg_pull_up_8ma>; - }; - - sdio_pwren: sdio-pwren { - rockchip,pins = - <0 RK_PA2 1 &pcfg_pull_none_8ma>; - }; - - sdio_wrpt: sdio-wrpt { - rockchip,pins = - <0 RK_PA1 1 &pcfg_pull_none_8ma>; - }; - - sdio_intn: sdio-intn { - rockchip,pins = - <0 RK_PA0 1 &pcfg_pull_none_8ma>; - }; - - sdio_bus1: sdio-bus1 { - rockchip,pins = - <4 RK_PA0 1 &pcfg_pull_up_8ma>; - }; - - sdio_bus4: sdio-bus4 { - rockchip,pins = - <4 RK_PA0 1 &pcfg_pull_up_8ma>, - <4 RK_PA1 1 &pcfg_pull_up_8ma>, - <4 RK_PA2 1 &pcfg_pull_up_8ma>, - <4 RK_PA3 1 &pcfg_pull_up_8ma>; - }; - }; - - spdif_in { - spdif_in: spdif-in { - rockchip,pins = - <0 RK_PC2 1 &pcfg_pull_none>; - }; - }; - - spdif_out { - spdif_out: spdif-out { - rockchip,pins = - <0 RK_PC1 1 &pcfg_pull_none>; - }; - }; - - spi0 { - spi0_clk: spi0-clk { - rockchip,pins = - <2 RK_PA2 2 &pcfg_pull_up_4ma>; - }; - - spi0_csn0: spi0-csn0 { - rockchip,pins = - <2 RK_PA3 2 &pcfg_pull_up_4ma>; - }; - - spi0_miso: spi0-miso { - rockchip,pins = - <2 RK_PA0 2 &pcfg_pull_up_4ma>; - }; - - spi0_mosi: spi0-mosi { - rockchip,pins = - <2 RK_PA1 2 &pcfg_pull_up_4ma>; - }; - }; - - spi1 { - spi1_clk: spi1-clk { - rockchip,pins = - <3 RK_PB3 3 &pcfg_pull_up_4ma>; - }; - - spi1_csn0: spi1-csn0 { - rockchip,pins = - <3 RK_PB5 3 &pcfg_pull_up_4ma>; - }; - - spi1_miso: spi1-miso { - rockchip,pins = - <3 RK_PB2 3 &pcfg_pull_up_4ma>; - }; - - spi1_mosi: spi1-mosi { - rockchip,pins = - <3 RK_PB4 3 &pcfg_pull_up_4ma>; - }; - }; - - spi1-m1 { - spi1m1_miso: spi1m1-miso { - rockchip,pins = - <2 RK_PA4 2 &pcfg_pull_up_4ma>; - }; - - spi1m1_mosi: spi1m1-mosi { - rockchip,pins = - <2 RK_PA5 2 &pcfg_pull_up_4ma>; - }; - - spi1m1_clk: spi1m1-clk { - rockchip,pins = - <2 RK_PA7 2 &pcfg_pull_up_4ma>; - }; - - spi1m1_csn0: spi1m1-csn0 { - rockchip,pins = - <2 RK_PB1 2 &pcfg_pull_up_4ma>; - }; - }; - - spi2 { - spi2_clk: spi2-clk { - rockchip,pins = - <1 RK_PD0 3 &pcfg_pull_up_4ma>; - }; - - spi2_csn0: spi2-csn0 { - rockchip,pins = - <1 RK_PD1 3 &pcfg_pull_up_4ma>; - }; - - spi2_miso: spi2-miso { - rockchip,pins = - <1 RK_PC6 3 &pcfg_pull_up_4ma>; - }; - - spi2_mosi: spi2-mosi { - rockchip,pins = - <1 RK_PC7 3 &pcfg_pull_up_4ma>; - }; - }; - - tsadc { - tsadc_otp_gpio: tsadc-otp-gpio { - rockchip,pins = - <0 RK_PB2 0 &pcfg_pull_none>; - }; - - tsadc_otp_out: tsadc-otp-out { - rockchip,pins = - <0 RK_PB2 1 &pcfg_pull_none>; - }; - }; - - uart0 { - uart0_xfer: uart0-xfer { - rockchip,pins = - <2 RK_PA1 1 &pcfg_pull_up>, - <2 RK_PA0 1 &pcfg_pull_up>; - }; - - uart0_cts: uart0-cts { - rockchip,pins = - <2 RK_PA2 1 &pcfg_pull_none>; - }; - - uart0_rts: uart0-rts { - rockchip,pins = - <2 RK_PA3 1 &pcfg_pull_none>; - }; - - uart0_rts_gpio: uart0-rts-gpio { - rockchip,pins = - <2 RK_PA3 0 &pcfg_pull_none>; - }; - }; - - uart1 { - uart1_xfer: uart1-xfer { - rockchip,pins = - <1 RK_PD1 1 &pcfg_pull_up>, - <1 RK_PD0 1 &pcfg_pull_up>; - }; - - uart1_cts: uart1-cts { - rockchip,pins = - <1 RK_PC6 1 &pcfg_pull_none>; - }; - - uart1_rts: uart1-rts { - rockchip,pins = - <1 RK_PC7 1 &pcfg_pull_none>; - }; - }; - - uart2-m0 { - uart2m0_xfer: uart2m0-xfer { - rockchip,pins = - <1 RK_PC7 2 &pcfg_pull_up>, - <1 RK_PC6 2 &pcfg_pull_up>; - }; - }; - - uart2-m1 { - uart2m1_xfer: uart2m1-xfer { - rockchip,pins = - <4 RK_PD3 2 &pcfg_pull_up>, - <4 RK_PD2 2 &pcfg_pull_up>; - }; - }; - - uart3 { - uart3_xfer: uart3-xfer { - rockchip,pins = - <3 RK_PB5 4 &pcfg_pull_up>, - <3 RK_PB4 4 &pcfg_pull_up>; - }; - }; - - uart3-m1 { - uart3m1_xfer: uart3m1-xfer { - rockchip,pins = - <0 RK_PC2 3 &pcfg_pull_up>, - <0 RK_PC1 3 &pcfg_pull_up>; - }; - }; - - uart4 { - uart4_xfer: uart4-xfer { - rockchip,pins = - <4 RK_PB1 1 &pcfg_pull_up>, - <4 RK_PB0 1 &pcfg_pull_up>; - }; - - uart4_cts: uart4-cts { - rockchip,pins = - <4 RK_PA6 1 &pcfg_pull_none>; - }; - - uart4_rts: uart4-rts { - rockchip,pins = - <4 RK_PA7 1 &pcfg_pull_none>; - }; - - uart4_rts_gpio: uart4-rts-gpio { - rockchip,pins = - <4 RK_PA7 0 &pcfg_pull_none>; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/rockchip/rk3328-a1.dts b/sys/gnu/dts/arm64/rockchip/rk3328-a1.dts deleted file mode 100644 index 16f1656d520..00000000000 --- a/sys/gnu/dts/arm64/rockchip/rk3328-a1.dts +++ /dev/null @@ -1,360 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-only OR MIT) -// Copyright (c) 2017-2019 Arm Ltd. - -/dts-v1/; -#include "rk3328.dtsi" - -/ { - model = "Beelink A1"; - compatible = "azw,beelink-a1", "rockchip,rk3328"; - - /* - * UART pins, as viewed with bottom of case removed: - * - * Front - * /------- - * L / o <- Gnd - * e / o <-- Rx - * f / o <--- Tx - * t / o <---- +3.3v - * | - */ - chosen { - stdout-path = "serial2:1500000n8"; - }; - - gmac_clkin: external-gmac-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "gmac_clkin"; - #clock-cells = <0>; - }; - - vcc_host_5v: usb3-current-switch { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&usb30_host_drv>; - regulator-name = "vcc_host_5v"; - vin-supply = <&vcc_sys>; - }; - - vcc_sys: vcc-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - ir-receiver { - compatible = "gpio-ir-receiver"; - gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>; - linux,rc-map-name = "rc-beelink-gs1"; - }; -}; - -&analog_sound { - simple-audio-card,name = "Analog A/V"; - status = "okay"; -}; - -&codec { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <&vdd_arm>; -}; - -&cpu1 { - cpu-supply = <&vdd_arm>; -}; - -&cpu2 { - cpu-supply = <&vdd_arm>; -}; - -&cpu3 { - cpu-supply = <&vdd_arm>; -}; - -&emmc { - bus-width = <8>; - cap-mmc-highspeed; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - no-sd; - no-sdio; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; - vmmc-supply = <&vcc_io>; - vqmmc-supply = <&vcc18_emmc>; - status = "okay"; -}; - -&gmac2io { - assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; - assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>; - clock_in_out = "input"; - phy-handle = <&rtl8211f>; - phy-mode = "rgmii"; - phy-supply = <&vcc_io>; - pinctrl-names = "default"; - pinctrl-0 = <&rgmiim1_pins>; - snps,aal; - snps,pbl = <0x4>; - tx_delay = <0x26>; - rx_delay = <0x11>; - status = "okay"; - - mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - rtl8211f: phy@0 { - reg = <0>; - reset-assert-us = <10000>; - reset-deassert-us = <30000>; - reset-gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&gpu { - mali-supply = <&vdd_logic>; -}; - -&hdmi { - status = "okay"; -}; - -&hdmiphy { - status = "okay"; -}; - -&hdmi_sound { - status = "okay"; -}; - -&i2c1 { - clock-frequency = <1000000>; - i2c-scl-falling-time-ns = <5>; - i2c-scl-rising-time-ns = <83>; - status = "okay"; - - pmic@18 { - compatible = "rockchip,rk805"; - reg = <0x18>; - interrupt-parent = <&gpio2>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l>; - rockchip,system-power-controller; - wakeup-source; - - vcc1-supply = <&vcc_sys>; - vcc2-supply = <&vcc_sys>; - vcc3-supply = <&vcc_sys>; - vcc4-supply = <&vcc_sys>; - vcc5-supply = <&vcc_io>; - vcc6-supply = <&vcc_io>; - - regulators { - vdd_logic: DCDC_REG1 { - regulator-name = "vdd_logic"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vdd_arm: DCDC_REG2 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <950000>; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_io: DCDC_REG4 { - regulator-name = "vcc_io"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vdd_18: LDO_REG1 { - regulator-name = "vdd_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc18_emmc: LDO_REG2 { - regulator-name = "vcc_18emmc"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vdd_11: LDO_REG3 { - regulator-name = "vdd_11"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1100000>; - }; - }; - }; - }; -}; - -&i2s0 { - status = "okay"; -}; - -&i2s1 { - status = "okay"; -}; - -&io_domains { - vccio1-supply = <&vcc_io>; - vccio2-supply = <&vcc18_emmc>; - vccio3-supply = <&vcc_io>; - vccio4-supply = <&vdd_18>; - vccio5-supply = <&vcc_io>; - vccio6-supply = <&vdd_18>; - pmuio-supply = <&vcc_io>; - status = "okay"; -}; - -&pinctrl { - pmic { - pmic_int_l: pmic-int-l { - rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - usb3 { - usb30_host_drv: usb30-host-drv { - rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - wifi { - bt_dis: bt-dis { - rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_output_low>; - }; - - bt_wake_host: bt-wake-host { - rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - chip_en: chip-en { - rockchip,pins = <2 RK_PC3 RK_FUNC_GPIO &pcfg_output_low>; - }; - - host_wake_bt: host-wake-bt { - rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_output_high>; - }; - - wl_dis: wl-dis { - rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_output_low>; - }; - - wl_wake_host: wl-wake-host { - rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - disable-wp; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>; - vmmc-supply = <&vcc_io>; - vqmmc-supply = <&vcc_io>; - status = "okay"; -}; - -&tsadc { - rockchip,hw-tshut-mode = <0>; - rockchip,hw-tshut-polarity = <0>; - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&u2phy { - status = "okay"; -}; - -&u2phy_host { - status = "okay"; -}; - -&u2phy_otg { - status = "okay"; -}; - -&usb20_otg { - dr_mode = "host"; - status = "okay"; -}; - -&usb_host0_ehci { - pinctrl-names = "default"; - pinctrl-0 = <&bt_dis &bt_wake_host &chip_en &host_wake_bt &wl_dis &wl_wake_host>; - status = "okay"; -}; - -&vop { - status = "okay"; -}; - -&vop_mmu { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/rockchip/rk3328-evb.dts b/sys/gnu/dts/arm64/rockchip/rk3328-evb.dts deleted file mode 100644 index 49c4b96da3d..00000000000 --- a/sys/gnu/dts/arm64/rockchip/rk3328-evb.dts +++ /dev/null @@ -1,271 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd - */ - -/dts-v1/; -#include "rk3328.dtsi" - -/ { - model = "Rockchip RK3328 EVB"; - compatible = "rockchip,rk3328-evb", "rockchip,rk3328"; - - chosen { - stdout-path = "serial2:1500000n8"; - }; - - dc_12v: dc-12v { - compatible = "regulator-fixed"; - regulator-name = "dc_12v"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_enable_h>; - - /* - * On the module itself this is one of these (depending - * on the actual card populated): - * - SDIO_RESET_L_WL_REG_ON - * - PDN (power down when low) - */ - reset-gpios = <&gpio1 18 GPIO_ACTIVE_LOW>; - }; - - vcc_sd: sdmmc-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio0 30 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc0m1_gpio>; - regulator-name = "vcc_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_io>; - }; - - vcc_sys: vcc-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&dc_12v>; - }; - - vcc_phy: vcc-phy-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_phy"; - regulator-always-on; - regulator-boot-on; - }; -}; - -&cpu0 { - cpu-supply = <&vdd_arm>; -}; - -&emmc { - bus-width = <8>; - cap-mmc-highspeed; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; - status = "okay"; -}; - -&gmac2phy { - phy-supply = <&vcc_phy>; - clock_in_out = "output"; - assigned-clocks = <&cru SCLK_MAC2PHY_SRC>; - assigned-clock-rate = <50000000>; - assigned-clocks = <&cru SCLK_MAC2PHY>; - assigned-clock-parents = <&cru SCLK_MAC2PHY_SRC>; - -}; - -&i2c1 { - status = "okay"; - - rk805: rk805@18 { - compatible = "rockchip,rk805"; - reg = <0x18>; - interrupt-parent = <&gpio2>; - interrupts = <6 IRQ_TYPE_LEVEL_LOW>; - #clock-cells = <1>; - clock-output-names = "xin32k", "rk805-clkout2"; - gpio-controller; - #gpio-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l>; - rockchip,system-power-controller; - wakeup-source; - - vcc1-supply = <&vcc_sys>; - vcc2-supply = <&vcc_sys>; - vcc3-supply = <&vcc_sys>; - vcc4-supply = <&vcc_sys>; - vcc5-supply = <&vcc_io>; - vcc6-supply = <&vcc_io>; - - regulators { - vdd_logic: DCDC_REG1 { - regulator-name = "vdd_logic"; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1450000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vdd_arm: DCDC_REG2 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1450000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <950000>; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_io: DCDC_REG4 { - regulator-name = "vcc_io"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc_18: LDO_REG1 { - regulator-name = "vcc_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc18_emmc: LDO_REG2 { - regulator-name = "vcc18_emmc"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vdd_10: LDO_REG3 { - regulator-name = "vdd_10"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - }; - }; -}; - -&pinctrl { - pmic { - pmic_int_l: pmic-int-l { - rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - sdio-pwrseq { - wifi_enable_h: wifi-enable-h { - rockchip,pins = - <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&sdio { - bus-width = <4>; - cap-sd-highspeed; - cap-sdio-irq; - keep-power-in-suspend; - max-frequency = <150000000>; - mmc-pwrseq = <&sdio_pwrseq>; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; - status = "okay"; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - disable-wp; - max-frequency = <150000000>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>; - vmmc-supply = <&vcc_sd>; - status = "okay"; -}; - -&tsadc { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&u2phy { - status = "okay"; -}; - -&u2phy_host { - status = "okay"; -}; - -&u2phy_otg { - status = "okay"; -}; - -&usb20_otg { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/rockchip/rk3328-roc-cc.dts b/sys/gnu/dts/arm64/rockchip/rk3328-roc-cc.dts deleted file mode 100644 index 8d553c92182..00000000000 --- a/sys/gnu/dts/arm64/rockchip/rk3328-roc-cc.dts +++ /dev/null @@ -1,354 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 T-Chip Intelligent Technology Co., Ltd - */ - -/dts-v1/; -#include "rk3328.dtsi" - -/ { - model = "Firefly roc-rk3328-cc"; - compatible = "firefly,roc-rk3328-cc", "rockchip,rk3328"; - - chosen { - stdout-path = "serial2:1500000n8"; - }; - - gmac_clkin: external-gmac-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "gmac_clkin"; - #clock-cells = <0>; - }; - - dc_12v: dc-12v { - compatible = "regulator-fixed"; - regulator-name = "dc_12v"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - vcc_sd: sdmmc-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc0m1_gpio>; - regulator-boot-on; - regulator-name = "vcc_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_io>; - }; - - vcc_sdio: sdmmcio-regulator { - compatible = "regulator-gpio"; - gpios = <&grf_gpio 0 GPIO_ACTIVE_HIGH>; - states = <1800000 0x1 - 3300000 0x0>; - regulator-name = "vcc_sdio"; - regulator-type = "voltage"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - vin-supply = <&vcc_sys>; - }; - - vcc_host1_5v: vcc_otg_5v: vcc-host1-5v-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&usb20_host_drv>; - regulator-name = "vcc_host1_5v"; - regulator-always-on; - vin-supply = <&vcc_sys>; - }; - - vcc_sys: vcc-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&dc_12v>; - }; - - vcc_phy: vcc-phy-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_phy"; - regulator-always-on; - regulator-boot-on; - }; - - leds { - compatible = "gpio-leds"; - - power { - label = "firefly:blue:power"; - linux,default-trigger = "heartbeat"; - gpios = <&rk805 1 GPIO_ACTIVE_LOW>; - default-state = "on"; - mode = <0x23>; - }; - - user { - label = "firefly:yellow:user"; - linux,default-trigger = "mmc1"; - gpios = <&rk805 0 GPIO_ACTIVE_LOW>; - default-state = "off"; - mode = <0x05>; - }; - }; -}; - -&cpu0 { - cpu-supply = <&vdd_arm>; -}; - -&cpu1 { - cpu-supply = <&vdd_arm>; -}; - -&cpu2 { - cpu-supply = <&vdd_arm>; -}; - -&cpu3 { - cpu-supply = <&vdd_arm>; -}; - -&emmc { - bus-width = <8>; - cap-mmc-highspeed; - max-frequency = <150000000>; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; - vmmc-supply = <&vcc_io>; - vqmmc-supply = <&vcc18_emmc>; - status = "okay"; -}; - -&gmac2io { - assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; - assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>; - clock_in_out = "input"; - phy-supply = <&vcc_phy>; - phy-mode = "rgmii"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmiim1_pins>; - snps,aal; - snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 50000>; - snps,rxpbl = <0x4>; - snps,txpbl = <0x4>; - tx_delay = <0x24>; - rx_delay = <0x18>; - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmiphy { - status = "okay"; -}; - -&i2c1 { - status = "okay"; - - rk805: pmic@18 { - compatible = "rockchip,rk805"; - reg = <0x18>; - interrupt-parent = <&gpio1>; - interrupts = <24 IRQ_TYPE_LEVEL_LOW>; - #clock-cells = <1>; - clock-output-names = "xin32k", "rk805-clkout2"; - gpio-controller; - #gpio-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l>; - rockchip,system-power-controller; - wakeup-source; - - vcc1-supply = <&vcc_sys>; - vcc2-supply = <&vcc_sys>; - vcc3-supply = <&vcc_sys>; - vcc4-supply = <&vcc_sys>; - vcc5-supply = <&vcc_io>; - vcc6-supply = <&vcc_io>; - - regulators { - vdd_logic: DCDC_REG1 { - regulator-name = "vdd_logic"; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1450000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vdd_arm: DCDC_REG2 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1450000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <950000>; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_io: DCDC_REG4 { - regulator-name = "vcc_io"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc_18: LDO_REG1 { - regulator-name = "vcc_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc18_emmc: LDO_REG2 { - regulator-name = "vcc18_emmc"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vdd_10: LDO_REG3 { - regulator-name = "vdd_10"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - }; - }; -}; - -&io_domains { - status = "okay"; - - vccio1-supply = <&vcc_io>; - vccio2-supply = <&vcc18_emmc>; - vccio3-supply = <&vcc_sdio>; - vccio4-supply = <&vcc_18>; - vccio5-supply = <&vcc_io>; - vccio6-supply = <&vcc_io>; - pmuio-supply = <&vcc_io>; -}; - -&pinctrl { - pmic { - pmic_int_l: pmic-int-l { - rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - usb2 { - usb20_host_drv: usb20-host-drv { - rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - disable-wp; - max-frequency = <150000000>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-sdr104; - vmmc-supply = <&vcc_sd>; - vqmmc-supply = <&vcc_sdio>; - status = "okay"; -}; - -&tsadc { - status = "okay"; -}; - -&u2phy { - status = "okay"; -}; - -&u2phy_host { - status = "okay"; -}; - -&u2phy_otg { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&usb20_otg { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&vop { - status = "okay"; -}; - -&vop_mmu { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/rockchip/rk3328-rock64.dts b/sys/gnu/dts/arm64/rockchip/rk3328-rock64.dts deleted file mode 100644 index 62936b432f9..00000000000 --- a/sys/gnu/dts/arm64/rockchip/rk3328-rock64.dts +++ /dev/null @@ -1,400 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 PINE64 - */ - -/dts-v1/; -#include "rk3328.dtsi" - -/ { - model = "Pine64 Rock64"; - compatible = "pine64,rock64", "rockchip,rk3328"; - - chosen { - stdout-path = "serial2:1500000n8"; - }; - - gmac_clkin: external-gmac-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "gmac_clkin"; - #clock-cells = <0>; - }; - - vcc_sd: sdmmc-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc0m1_gpio>; - regulator-name = "vcc_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_io>; - }; - - vcc_host_5v: vcc-host-5v-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&usb20_host_drv>; - regulator-name = "vcc_host_5v"; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_sys>; - }; - - vcc_host1_5v: vcc_otg_5v: vcc-host1-5v-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&usb20_host_drv>; - regulator-name = "vcc_host1_5v"; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_sys>; - }; - - vcc_sys: vcc-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - ir-receiver { - compatible = "gpio-ir-receiver"; - gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&ir_int>; - pinctrl-names = "default"; - }; - - leds { - compatible = "gpio-leds"; - - power { - gpios = <&rk805 1 GPIO_ACTIVE_LOW>; - linux,default-trigger = "mmc0"; - }; - - standby { - gpios = <&rk805 0 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - }; - }; - - sound { - compatible = "audio-graph-card"; - label = "rockchip,rk3328"; - dais = <&i2s1_p0 - &spdif_p0>; - }; - - spdif-dit { - compatible = "linux,spdif-dit"; - #sound-dai-cells = <0>; - - port { - dit_p0_0: endpoint { - remote-endpoint = <&spdif_p0_0>; - }; - }; - }; -}; - -&codec { - status = "okay"; - - port@0 { - codec_p0_0: endpoint { - remote-endpoint = <&i2s1_p0_0>; - }; - }; -}; - -&cpu0 { - cpu-supply = <&vdd_arm>; -}; - -&cpu1 { - cpu-supply = <&vdd_arm>; -}; - -&cpu2 { - cpu-supply = <&vdd_arm>; -}; - -&cpu3 { - cpu-supply = <&vdd_arm>; -}; - -&emmc { - bus-width = <8>; - cap-mmc-highspeed; - mmc-hs200-1_8v; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; - vmmc-supply = <&vcc_io>; - vqmmc-supply = <&vcc18_emmc>; - status = "okay"; -}; - -&gmac2io { - assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; - assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>; - clock_in_out = "input"; - phy-supply = <&vcc_io>; - phy-mode = "rgmii"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmiim1_pins>; - snps,force_thresh_dma_mode; - snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 50000>; - tx_delay = <0x24>; - rx_delay = <0x18>; - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmiphy { - status = "okay"; -}; - -&i2c1 { - status = "okay"; - - rk805: rk805@18 { - compatible = "rockchip,rk805"; - reg = <0x18>; - interrupt-parent = <&gpio2>; - interrupts = <6 IRQ_TYPE_LEVEL_LOW>; - #clock-cells = <1>; - clock-output-names = "xin32k", "rk805-clkout2"; - gpio-controller; - #gpio-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l>; - rockchip,system-power-controller; - wakeup-source; - - vcc1-supply = <&vcc_sys>; - vcc2-supply = <&vcc_sys>; - vcc3-supply = <&vcc_sys>; - vcc4-supply = <&vcc_sys>; - vcc5-supply = <&vcc_io>; - vcc6-supply = <&vcc_sys>; - - regulators { - vdd_logic: DCDC_REG1 { - regulator-name = "vdd_logic"; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1450000>; - regulator-ramp-delay = <12500>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vdd_arm: DCDC_REG2 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1450000>; - regulator-ramp-delay = <12500>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <950000>; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_io: DCDC_REG4 { - regulator-name = "vcc_io"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc_18: LDO_REG1 { - regulator-name = "vcc_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc18_emmc: LDO_REG2 { - regulator-name = "vcc18_emmc"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vdd_10: LDO_REG3 { - regulator-name = "vdd_10"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - }; - }; -}; - -&i2s1 { - status = "okay"; - - i2s1_p0: port { - i2s1_p0_0: endpoint { - dai-format = "i2s"; - mclk-fs = <256>; - remote-endpoint = <&codec_p0_0>; - }; - }; -}; - -&io_domains { - status = "okay"; - - vccio1-supply = <&vcc_io>; - vccio2-supply = <&vcc18_emmc>; - vccio3-supply = <&vcc_io>; - vccio4-supply = <&vcc_18>; - vccio5-supply = <&vcc_io>; - vccio6-supply = <&vcc_io>; - pmuio-supply = <&vcc_io>; -}; - -&pinctrl { - ir { - ir_int: ir-int { - rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - pmic_int_l: pmic-int-l { - rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - usb2 { - usb20_host_drv: usb20-host-drv { - rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - disable-wp; - max-frequency = <150000000>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>; - vmmc-supply = <&vcc_sd>; - status = "okay"; -}; - -&spdif { - pinctrl-0 = <&spdifm0_tx>; - status = "okay"; - - spdif_p0: port { - spdif_p0_0: endpoint { - remote-endpoint = <&dit_p0_0>; - }; - }; -}; - -&spi0 { - status = "okay"; - - spiflash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - - /* maximum speed for Rockchip SPI */ - spi-max-frequency = <50000000>; - }; -}; - -&tsadc { - rockchip,hw-tshut-mode = <0>; - rockchip,hw-tshut-polarity = <0>; - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&u2phy { - status = "okay"; - - u2phy_host: host-port { - status = "okay"; - }; - - u2phy_otg: otg-port { - status = "okay"; - }; -}; - -&usb20_otg { - dr_mode = "host"; - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&vop { - status = "okay"; -}; - -&vop_mmu { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/rockchip/rk3328.dtsi b/sys/gnu/dts/arm64/rockchip/rk3328.dtsi deleted file mode 100644 index 1f53ead52c7..00000000000 --- a/sys/gnu/dts/arm64/rockchip/rk3328.dtsi +++ /dev/null @@ -1,1914 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -/ { - compatible = "rockchip,rk3328"; - - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - ethernet0 = &gmac2io; - ethernet1 = &gmac2phy; - }; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x0>; - clocks = <&cru ARMCLK>; - #cooling-cells = <2>; - cpu-idle-states = <&CPU_SLEEP>; - dynamic-power-coefficient = <120>; - enable-method = "psci"; - next-level-cache = <&l2>; - operating-points-v2 = <&cpu0_opp_table>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x1>; - clocks = <&cru ARMCLK>; - #cooling-cells = <2>; - cpu-idle-states = <&CPU_SLEEP>; - dynamic-power-coefficient = <120>; - enable-method = "psci"; - next-level-cache = <&l2>; - operating-points-v2 = <&cpu0_opp_table>; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x2>; - clocks = <&cru ARMCLK>; - #cooling-cells = <2>; - cpu-idle-states = <&CPU_SLEEP>; - dynamic-power-coefficient = <120>; - enable-method = "psci"; - next-level-cache = <&l2>; - operating-points-v2 = <&cpu0_opp_table>; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x3>; - clocks = <&cru ARMCLK>; - #cooling-cells = <2>; - cpu-idle-states = <&CPU_SLEEP>; - dynamic-power-coefficient = <120>; - enable-method = "psci"; - next-level-cache = <&l2>; - operating-points-v2 = <&cpu0_opp_table>; - }; - - idle-states { - entry-method = "psci"; - - CPU_SLEEP: cpu-sleep { - compatible = "arm,idle-state"; - local-timer-stop; - arm,psci-suspend-param = <0x0010000>; - entry-latency-us = <120>; - exit-latency-us = <250>; - min-residency-us = <900>; - }; - }; - - l2: l2-cache0 { - compatible = "cache"; - }; - }; - - cpu0_opp_table: opp_table0 { - compatible = "operating-points-v2"; - opp-shared; - - opp-408000000 { - opp-hz = /bits/ 64 <408000000>; - opp-microvolt = <950000>; - clock-latency-ns = <40000>; - opp-suspend; - }; - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <950000>; - clock-latency-ns = <40000>; - }; - opp-816000000 { - opp-hz = /bits/ 64 <816000000>; - opp-microvolt = <1000000>; - clock-latency-ns = <40000>; - }; - opp-1008000000 { - opp-hz = /bits/ 64 <1008000000>; - opp-microvolt = <1100000>; - clock-latency-ns = <40000>; - }; - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <1225000>; - clock-latency-ns = <40000>; - }; - opp-1296000000 { - opp-hz = /bits/ 64 <1296000000>; - opp-microvolt = <1300000>; - clock-latency-ns = <40000>; - }; - }; - - amba { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - dmac: dmac@ff1f0000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x0 0xff1f0000 0x0 0x4000>; - interrupts = , - ; - clocks = <&cru ACLK_DMAC>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - }; - }; - - analog_sound: analog-sound { - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,mclk-fs = <256>; - simple-audio-card,name = "Analog"; - status = "disabled"; - - simple-audio-card,cpu { - sound-dai = <&i2s1>; - }; - - simple-audio-card,codec { - sound-dai = <&codec>; - }; - }; - - arm-pmu { - compatible = "arm,cortex-a53-pmu"; - interrupts = , - , - , - ; - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; - }; - - display_subsystem: display-subsystem { - compatible = "rockchip,display-subsystem"; - ports = <&vop_out>; - }; - - hdmi_sound: hdmi-sound { - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,mclk-fs = <128>; - simple-audio-card,name = "HDMI"; - status = "disabled"; - - simple-audio-card,cpu { - sound-dai = <&i2s0>; - }; - - simple-audio-card,codec { - sound-dai = <&hdmi>; - }; - }; - - psci { - compatible = "arm,psci-1.0", "arm,psci-0.2"; - method = "smc"; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - xin24m: xin24m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "xin24m"; - }; - - i2s0: i2s@ff000000 { - compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; - reg = <0x0 0xff000000 0x0 0x1000>; - interrupts = ; - clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>; - clock-names = "i2s_clk", "i2s_hclk"; - dmas = <&dmac 11>, <&dmac 12>; - dma-names = "tx", "rx"; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - i2s1: i2s@ff010000 { - compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; - reg = <0x0 0xff010000 0x0 0x1000>; - interrupts = ; - clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>; - clock-names = "i2s_clk", "i2s_hclk"; - dmas = <&dmac 14>, <&dmac 15>; - dma-names = "tx", "rx"; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - i2s2: i2s@ff020000 { - compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; - reg = <0x0 0xff020000 0x0 0x1000>; - interrupts = ; - clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>; - clock-names = "i2s_clk", "i2s_hclk"; - dmas = <&dmac 0>, <&dmac 1>; - dma-names = "tx", "rx"; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - spdif: spdif@ff030000 { - compatible = "rockchip,rk3328-spdif"; - reg = <0x0 0xff030000 0x0 0x1000>; - interrupts = ; - clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>; - clock-names = "mclk", "hclk"; - dmas = <&dmac 10>; - dma-names = "tx"; - pinctrl-names = "default"; - pinctrl-0 = <&spdifm2_tx>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - pdm: pdm@ff040000 { - compatible = "rockchip,pdm"; - reg = <0x0 0xff040000 0x0 0x1000>; - clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>; - clock-names = "pdm_clk", "pdm_hclk"; - dmas = <&dmac 16>; - dma-names = "rx"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&pdmm0_clk - &pdmm0_sdi0 - &pdmm0_sdi1 - &pdmm0_sdi2 - &pdmm0_sdi3>; - pinctrl-1 = <&pdmm0_clk_sleep - &pdmm0_sdi0_sleep - &pdmm0_sdi1_sleep - &pdmm0_sdi2_sleep - &pdmm0_sdi3_sleep>; - status = "disabled"; - }; - - grf: syscon@ff100000 { - compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd"; - reg = <0x0 0xff100000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - - io_domains: io-domains { - compatible = "rockchip,rk3328-io-voltage-domain"; - status = "disabled"; - }; - - grf_gpio: grf-gpio { - compatible = "rockchip,rk3328-grf-gpio"; - gpio-controller; - #gpio-cells = <2>; - }; - - power: power-controller { - compatible = "rockchip,rk3328-power-controller"; - #power-domain-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - - pd_hevc@RK3328_PD_HEVC { - reg = ; - }; - pd_video@RK3328_PD_VIDEO { - reg = ; - }; - pd_vpu@RK3328_PD_VPU { - reg = ; - clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; - }; - }; - - reboot-mode { - compatible = "syscon-reboot-mode"; - offset = <0x5c8>; - mode-normal = ; - mode-recovery = ; - mode-bootloader = ; - mode-loader = ; - }; - }; - - uart0: serial@ff110000 { - compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; - reg = <0x0 0xff110000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac 2>, <&dmac 3>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart1: serial@ff120000 { - compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; - reg = <0x0 0xff120000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac 4>, <&dmac 5>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart2: serial@ff130000 { - compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; - reg = <0x0 0xff130000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac 6>, <&dmac 7>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&uart2m1_xfer>; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - i2c0: i2c@ff150000 { - compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xff150000 0x0 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>; - clock-names = "i2c", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_xfer>; - status = "disabled"; - }; - - i2c1: i2c@ff160000 { - compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xff160000 0x0 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; - clock-names = "i2c", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_xfer>; - status = "disabled"; - }; - - i2c2: i2c@ff170000 { - compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xff170000 0x0 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; - clock-names = "i2c", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_xfer>; - status = "disabled"; - }; - - i2c3: i2c@ff180000 { - compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xff180000 0x0 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; - clock-names = "i2c", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_xfer>; - status = "disabled"; - }; - - spi0: spi@ff190000 { - compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi"; - reg = <0x0 0xff190000 0x0 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>; - clock-names = "spiclk", "apb_pclk"; - dmas = <&dmac 8>, <&dmac 9>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>; - status = "disabled"; - }; - - wdt: watchdog@ff1a0000 { - compatible = "snps,dw-wdt"; - reg = <0x0 0xff1a0000 0x0 0x100>; - interrupts = ; - clocks = <&cru PCLK_WDT>; - }; - - pwm0: pwm@ff1b0000 { - compatible = "rockchip,rk3328-pwm"; - reg = <0x0 0xff1b0000 0x0 0x10>; - clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; - clock-names = "pwm", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pin>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm1: pwm@ff1b0010 { - compatible = "rockchip,rk3328-pwm"; - reg = <0x0 0xff1b0010 0x0 0x10>; - clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; - clock-names = "pwm", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm1_pin>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm2: pwm@ff1b0020 { - compatible = "rockchip,rk3328-pwm"; - reg = <0x0 0xff1b0020 0x0 0x10>; - clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; - clock-names = "pwm", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm2_pin>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm3: pwm@ff1b0030 { - compatible = "rockchip,rk3328-pwm"; - reg = <0x0 0xff1b0030 0x0 0x10>; - interrupts = ; - clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; - clock-names = "pwm", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&pwmir_pin>; - #pwm-cells = <3>; - status = "disabled"; - }; - - thermal-zones { - soc_thermal: soc-thermal { - polling-delay-passive = <20>; - polling-delay = <1000>; - sustainable-power = <1000>; - - thermal-sensors = <&tsadc 0>; - - trips { - threshold: trip-point0 { - temperature = <70000>; - hysteresis = <2000>; - type = "passive"; - }; - target: trip-point1 { - temperature = <85000>; - hysteresis = <2000>; - type = "passive"; - }; - soc_crit: soc-crit { - temperature = <95000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&target>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - contribution = <4096>; - }; - }; - }; - - }; - - tsadc: tsadc@ff250000 { - compatible = "rockchip,rk3328-tsadc"; - reg = <0x0 0xff250000 0x0 0x100>; - interrupts = ; - assigned-clocks = <&cru SCLK_TSADC>; - assigned-clock-rates = <50000>; - clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; - clock-names = "tsadc", "apb_pclk"; - pinctrl-names = "init", "default", "sleep"; - pinctrl-0 = <&otp_gpio>; - pinctrl-1 = <&otp_out>; - pinctrl-2 = <&otp_gpio>; - resets = <&cru SRST_TSADC>; - reset-names = "tsadc-apb"; - rockchip,grf = <&grf>; - rockchip,hw-tshut-temp = <100000>; - #thermal-sensor-cells = <1>; - status = "disabled"; - }; - - efuse: efuse@ff260000 { - compatible = "rockchip,rk3328-efuse"; - reg = <0x0 0xff260000 0x0 0x50>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&cru SCLK_EFUSE>; - clock-names = "pclk_efuse"; - rockchip,efuse-size = <0x20>; - - /* Data cells */ - efuse_id: id@7 { - reg = <0x07 0x10>; - }; - cpu_leakage: cpu-leakage@17 { - reg = <0x17 0x1>; - }; - logic_leakage: logic-leakage@19 { - reg = <0x19 0x1>; - }; - efuse_cpu_version: cpu-version@1a { - reg = <0x1a 0x1>; - bits = <3 3>; - }; - }; - - saradc: adc@ff280000 { - compatible = "rockchip,rk3328-saradc", "rockchip,rk3399-saradc"; - reg = <0x0 0xff280000 0x0 0x100>; - interrupts = ; - #io-channel-cells = <1>; - clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; - clock-names = "saradc", "apb_pclk"; - resets = <&cru SRST_SARADC_P>; - reset-names = "saradc-apb"; - status = "disabled"; - }; - - gpu: gpu@ff300000 { - compatible = "rockchip,rk3328-mali", "arm,mali-450"; - reg = <0x0 0xff300000 0x0 0x40000>; - interrupts = , - , - , - , - , - , - ; - interrupt-names = "gp", - "gpmmu", - "pp", - "pp0", - "ppmmu0", - "pp1", - "ppmmu1"; - clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>; - clock-names = "bus", "core"; - resets = <&cru SRST_GPU_A>; - }; - - h265e_mmu: iommu@ff330200 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff330200 0 0x100>; - interrupts = ; - interrupt-names = "h265e_mmu"; - clocks = <&cru ACLK_H265>, <&cru PCLK_H265>; - clock-names = "aclk", "iface"; - #iommu-cells = <0>; - status = "disabled"; - }; - - vepu_mmu: iommu@ff340800 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff340800 0x0 0x40>; - interrupts = ; - interrupt-names = "vepu_mmu"; - clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; - clock-names = "aclk", "iface"; - #iommu-cells = <0>; - status = "disabled"; - }; - - vpu: video-codec@ff350000 { - compatible = "rockchip,rk3328-vpu"; - reg = <0x0 0xff350000 0x0 0x800>; - interrupts = ; - interrupt-names = "vdpu"; - clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; - clock-names = "aclk", "hclk"; - iommus = <&vpu_mmu>; - power-domains = <&power RK3328_PD_VPU>; - }; - - vpu_mmu: iommu@ff350800 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff350800 0x0 0x40>; - interrupts = ; - interrupt-names = "vpu_mmu"; - clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; - clock-names = "aclk", "iface"; - #iommu-cells = <0>; - power-domains = <&power RK3328_PD_VPU>; - }; - - rkvdec_mmu: iommu@ff360480 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff360480 0x0 0x40>, <0x0 0xff3604c0 0x0 0x40>; - interrupts = ; - interrupt-names = "rkvdec_mmu"; - clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>; - clock-names = "aclk", "iface"; - #iommu-cells = <0>; - status = "disabled"; - }; - - vop: vop@ff370000 { - compatible = "rockchip,rk3328-vop"; - reg = <0x0 0xff370000 0x0 0x3efc>; - interrupts = ; - clocks = <&cru ACLK_VOP>, <&cru DCLK_LCDC>, <&cru HCLK_VOP>; - clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; - resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>; - reset-names = "axi", "ahb", "dclk"; - iommus = <&vop_mmu>; - status = "disabled"; - - vop_out: port { - #address-cells = <1>; - #size-cells = <0>; - - vop_out_hdmi: endpoint@0 { - reg = <0>; - remote-endpoint = <&hdmi_in_vop>; - }; - }; - }; - - vop_mmu: iommu@ff373f00 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff373f00 0x0 0x100>; - interrupts = ; - interrupt-names = "vop_mmu"; - clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; - clock-names = "aclk", "iface"; - #iommu-cells = <0>; - status = "disabled"; - }; - - hdmi: hdmi@ff3c0000 { - compatible = "rockchip,rk3328-dw-hdmi"; - reg = <0x0 0xff3c0000 0x0 0x20000>; - reg-io-width = <4>; - interrupts = , - ; - clocks = <&cru PCLK_HDMI>, - <&cru SCLK_HDMI_SFC>, - <&cru SCLK_RTC32K>; - clock-names = "iahb", - "isfr", - "cec"; - phys = <&hdmiphy>; - phy-names = "hdmi"; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_cec &hdmii2c_xfer &hdmi_hpd>; - rockchip,grf = <&grf>; - #sound-dai-cells = <0>; - status = "disabled"; - - ports { - hdmi_in: port { - hdmi_in_vop: endpoint { - remote-endpoint = <&vop_out_hdmi>; - }; - }; - }; - }; - - codec: codec@ff410000 { - compatible = "rockchip,rk3328-codec"; - reg = <0x0 0xff410000 0x0 0x1000>; - clocks = <&cru PCLK_ACODECPHY>, <&cru SCLK_I2S1>; - clock-names = "pclk", "mclk"; - rockchip,grf = <&grf>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - hdmiphy: phy@ff430000 { - compatible = "rockchip,rk3328-hdmi-phy"; - reg = <0x0 0xff430000 0x0 0x10000>; - interrupts = ; - clocks = <&cru PCLK_HDMIPHY>, <&xin24m>, <&cru DCLK_HDMIPHY>; - clock-names = "sysclk", "refoclk", "refpclk"; - clock-output-names = "hdmi_phy"; - #clock-cells = <0>; - nvmem-cells = <&efuse_cpu_version>; - nvmem-cell-names = "cpu-version"; - #phy-cells = <0>; - status = "disabled"; - }; - - cru: clock-controller@ff440000 { - compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon"; - reg = <0x0 0xff440000 0x0 0x1000>; - rockchip,grf = <&grf>; - #clock-cells = <1>; - #reset-cells = <1>; - assigned-clocks = - /* - * CPLL should run at 1200, but that is to high for - * the initial dividers of most of its children. - * We need set cpll child clk div first, - * and then set the cpll frequency. - */ - <&cru DCLK_LCDC>, <&cru SCLK_PDM>, - <&cru SCLK_RTC32K>, <&cru SCLK_UART0>, - <&cru SCLK_UART1>, <&cru SCLK_UART2>, - <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, - <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>, - <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>, - <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>, - <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>, - <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>, - <&cru SCLK_SDIO>, <&cru SCLK_TSP>, - <&cru SCLK_WIFI>, <&cru ARMCLK>, - <&cru PLL_GPLL>, <&cru PLL_CPLL>, - <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>, - <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, - <&cru HCLK_PERI>, <&cru PCLK_PERI>, - <&cru SCLK_RTC32K>; - assigned-clock-parents = - <&cru HDMIPHY>, <&cru PLL_APLL>, - <&cru PLL_GPLL>, <&xin24m>, - <&xin24m>, <&xin24m>; - assigned-clock-rates = - <0>, <61440000>, - <0>, <24000000>, - <24000000>, <24000000>, - <15000000>, <15000000>, - <100000000>, <100000000>, - <100000000>, <100000000>, - <50000000>, <100000000>, - <100000000>, <100000000>, - <50000000>, <50000000>, - <50000000>, <50000000>, - <24000000>, <600000000>, - <491520000>, <1200000000>, - <150000000>, <75000000>, - <75000000>, <150000000>, - <75000000>, <75000000>, - <32768>; - }; - - usb2phy_grf: syscon@ff450000 { - compatible = "rockchip,rk3328-usb2phy-grf", "syscon", - "simple-mfd"; - reg = <0x0 0xff450000 0x0 0x10000>; - #address-cells = <1>; - #size-cells = <1>; - - u2phy: usb2-phy@100 { - compatible = "rockchip,rk3328-usb2phy"; - reg = <0x100 0x10>; - clocks = <&xin24m>; - clock-names = "phyclk"; - clock-output-names = "usb480m_phy"; - #clock-cells = <0>; - assigned-clocks = <&cru USB480M>; - assigned-clock-parents = <&u2phy>; - status = "disabled"; - - u2phy_otg: otg-port { - #phy-cells = <0>; - interrupts = , - , - ; - interrupt-names = "otg-bvalid", "otg-id", - "linestate"; - status = "disabled"; - }; - - u2phy_host: host-port { - #phy-cells = <0>; - interrupts = ; - interrupt-names = "linestate"; - status = "disabled"; - }; - }; - }; - - sdmmc: mmc@ff500000 { - compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x0 0xff500000 0x0 0x4000>; - interrupts = ; - clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, - <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - max-frequency = <150000000>; - status = "disabled"; - }; - - sdio: mmc@ff510000 { - compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x0 0xff510000 0x0 0x4000>; - interrupts = ; - clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, - <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - max-frequency = <150000000>; - status = "disabled"; - }; - - emmc: mmc@ff520000 { - compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x0 0xff520000 0x0 0x4000>; - interrupts = ; - clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, - <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - max-frequency = <150000000>; - status = "disabled"; - }; - - gmac2io: ethernet@ff540000 { - compatible = "rockchip,rk3328-gmac"; - reg = <0x0 0xff540000 0x0 0x10000>; - interrupts = ; - interrupt-names = "macirq"; - clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>, - <&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>, - <&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>, - <&cru PCLK_MAC2IO>; - clock-names = "stmmaceth", "mac_clk_rx", - "mac_clk_tx", "clk_mac_ref", - "clk_mac_refout", "aclk_mac", - "pclk_mac"; - resets = <&cru SRST_GMAC2IO_A>; - reset-names = "stmmaceth"; - rockchip,grf = <&grf>; - status = "disabled"; - }; - - gmac2phy: ethernet@ff550000 { - compatible = "rockchip,rk3328-gmac"; - reg = <0x0 0xff550000 0x0 0x10000>; - rockchip,grf = <&grf>; - interrupts = ; - interrupt-names = "macirq"; - clocks = <&cru SCLK_MAC2PHY_SRC>, <&cru SCLK_MAC2PHY_RXTX>, - <&cru SCLK_MAC2PHY_RXTX>, <&cru SCLK_MAC2PHY_REF>, - <&cru ACLK_MAC2PHY>, <&cru PCLK_MAC2PHY>, - <&cru SCLK_MAC2PHY_OUT>; - clock-names = "stmmaceth", "mac_clk_rx", - "mac_clk_tx", "clk_mac_ref", - "aclk_mac", "pclk_mac", - "clk_macphy"; - resets = <&cru SRST_GMAC2PHY_A>, <&cru SRST_MACPHY>; - reset-names = "stmmaceth", "mac-phy"; - phy-mode = "rmii"; - phy-handle = <&phy>; - status = "disabled"; - - mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - phy: phy@0 { - compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22"; - reg = <0>; - clocks = <&cru SCLK_MAC2PHY_OUT>; - resets = <&cru SRST_MACPHY>; - pinctrl-names = "default"; - pinctrl-0 = <&fephyled_rxm1 &fephyled_linkm1>; - phy-is-integrated; - }; - }; - }; - - usb20_otg: usb@ff580000 { - compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb", - "snps,dwc2"; - reg = <0x0 0xff580000 0x0 0x40000>; - interrupts = ; - clocks = <&cru HCLK_OTG>; - clock-names = "otg"; - dr_mode = "otg"; - g-np-tx-fifo-size = <16>; - g-rx-fifo-size = <280>; - g-tx-fifo-size = <256 128 128 64 32 16>; - g-use-dma; - phys = <&u2phy_otg>; - phy-names = "usb2-phy"; - status = "disabled"; - }; - - usb_host0_ehci: usb@ff5c0000 { - compatible = "generic-ehci"; - reg = <0x0 0xff5c0000 0x0 0x10000>; - interrupts = ; - clocks = <&cru HCLK_HOST0>, <&u2phy>; - clock-names = "usbhost", "utmi"; - phys = <&u2phy_host>; - phy-names = "usb"; - status = "disabled"; - }; - - usb_host0_ohci: usb@ff5d0000 { - compatible = "generic-ohci"; - reg = <0x0 0xff5d0000 0x0 0x10000>; - interrupts = ; - clocks = <&cru HCLK_HOST0>, <&u2phy>; - clock-names = "usbhost", "utmi"; - phys = <&u2phy_host>; - phy-names = "usb"; - status = "disabled"; - }; - - gic: interrupt-controller@ff811000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x0 0xff811000 0 0x1000>, - <0x0 0xff812000 0 0x2000>, - <0x0 0xff814000 0 0x2000>, - <0x0 0xff816000 0 0x2000>; - interrupts = ; - }; - - pinctrl: pinctrl { - compatible = "rockchip,rk3328-pinctrl"; - rockchip,grf = <&grf>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - gpio0: gpio0@ff210000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff210000 0x0 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO0>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio1@ff220000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff220000 0x0 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO1>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio2@ff230000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff230000 0x0 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO2>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio3@ff240000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff240000 0x0 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO3>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - pcfg_pull_up: pcfg-pull-up { - bias-pull-up; - }; - - pcfg_pull_down: pcfg-pull-down { - bias-pull-down; - }; - - pcfg_pull_none: pcfg-pull-none { - bias-disable; - }; - - pcfg_pull_none_2ma: pcfg-pull-none-2ma { - bias-disable; - drive-strength = <2>; - }; - - pcfg_pull_up_2ma: pcfg-pull-up-2ma { - bias-pull-up; - drive-strength = <2>; - }; - - pcfg_pull_up_4ma: pcfg-pull-up-4ma { - bias-pull-up; - drive-strength = <4>; - }; - - pcfg_pull_none_4ma: pcfg-pull-none-4ma { - bias-disable; - drive-strength = <4>; - }; - - pcfg_pull_down_4ma: pcfg-pull-down-4ma { - bias-pull-down; - drive-strength = <4>; - }; - - pcfg_pull_none_8ma: pcfg-pull-none-8ma { - bias-disable; - drive-strength = <8>; - }; - - pcfg_pull_up_8ma: pcfg-pull-up-8ma { - bias-pull-up; - drive-strength = <8>; - }; - - pcfg_pull_none_12ma: pcfg-pull-none-12ma { - bias-disable; - drive-strength = <12>; - }; - - pcfg_pull_up_12ma: pcfg-pull-up-12ma { - bias-pull-up; - drive-strength = <12>; - }; - - pcfg_output_high: pcfg-output-high { - output-high; - }; - - pcfg_output_low: pcfg-output-low { - output-low; - }; - - pcfg_input_high: pcfg-input-high { - bias-pull-up; - input-enable; - }; - - pcfg_input: pcfg-input { - input-enable; - }; - - i2c0 { - i2c0_xfer: i2c0-xfer { - rockchip,pins = <2 RK_PD0 1 &pcfg_pull_none>, - <2 RK_PD1 1 &pcfg_pull_none>; - }; - }; - - i2c1 { - i2c1_xfer: i2c1-xfer { - rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>, - <2 RK_PA5 2 &pcfg_pull_none>; - }; - }; - - i2c2 { - i2c2_xfer: i2c2-xfer { - rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>, - <2 RK_PB6 1 &pcfg_pull_none>; - }; - }; - - i2c3 { - i2c3_xfer: i2c3-xfer { - rockchip,pins = <0 RK_PA5 2 &pcfg_pull_none>, - <0 RK_PA6 2 &pcfg_pull_none>; - }; - i2c3_gpio: i2c3-gpio { - rockchip,pins = - <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>, - <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - hdmi_i2c { - hdmii2c_xfer: hdmii2c-xfer { - rockchip,pins = <0 RK_PA5 1 &pcfg_pull_none>, - <0 RK_PA6 1 &pcfg_pull_none>; - }; - }; - - pdm-0 { - pdmm0_clk: pdmm0-clk { - rockchip,pins = <2 RK_PC2 2 &pcfg_pull_none>; - }; - - pdmm0_fsync: pdmm0-fsync { - rockchip,pins = <2 RK_PC7 2 &pcfg_pull_none>; - }; - - pdmm0_sdi0: pdmm0-sdi0 { - rockchip,pins = <2 RK_PC3 2 &pcfg_pull_none>; - }; - - pdmm0_sdi1: pdmm0-sdi1 { - rockchip,pins = <2 RK_PC4 2 &pcfg_pull_none>; - }; - - pdmm0_sdi2: pdmm0-sdi2 { - rockchip,pins = <2 RK_PC5 2 &pcfg_pull_none>; - }; - - pdmm0_sdi3: pdmm0-sdi3 { - rockchip,pins = <2 RK_PC6 2 &pcfg_pull_none>; - }; - - pdmm0_clk_sleep: pdmm0-clk-sleep { - rockchip,pins = - <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>; - }; - - pdmm0_sdi0_sleep: pdmm0-sdi0-sleep { - rockchip,pins = - <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>; - }; - - pdmm0_sdi1_sleep: pdmm0-sdi1-sleep { - rockchip,pins = - <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>; - }; - - pdmm0_sdi2_sleep: pdmm0-sdi2-sleep { - rockchip,pins = - <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>; - }; - - pdmm0_sdi3_sleep: pdmm0-sdi3-sleep { - rockchip,pins = - <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>; - }; - - pdmm0_fsync_sleep: pdmm0-fsync-sleep { - rockchip,pins = - <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>; - }; - }; - - tsadc { - otp_gpio: otp-gpio { - rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - otp_out: otp-out { - rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>; - }; - }; - - uart0 { - uart0_xfer: uart0-xfer { - rockchip,pins = <1 RK_PB1 1 &pcfg_pull_up>, - <1 RK_PB0 1 &pcfg_pull_none>; - }; - - uart0_cts: uart0-cts { - rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>; - }; - - uart0_rts: uart0-rts { - rockchip,pins = <1 RK_PB2 1 &pcfg_pull_none>; - }; - - uart0_rts_gpio: uart0-rts-gpio { - rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - uart1 { - uart1_xfer: uart1-xfer { - rockchip,pins = <3 RK_PA4 4 &pcfg_pull_up>, - <3 RK_PA6 4 &pcfg_pull_none>; - }; - - uart1_cts: uart1-cts { - rockchip,pins = <3 RK_PA7 4 &pcfg_pull_none>; - }; - - uart1_rts: uart1-rts { - rockchip,pins = <3 RK_PA5 4 &pcfg_pull_none>; - }; - - uart1_rts_gpio: uart1-rts-gpio { - rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - uart2-0 { - uart2m0_xfer: uart2m0-xfer { - rockchip,pins = <1 RK_PA0 2 &pcfg_pull_up>, - <1 RK_PA1 2 &pcfg_pull_none>; - }; - }; - - uart2-1 { - uart2m1_xfer: uart2m1-xfer { - rockchip,pins = <2 RK_PA0 1 &pcfg_pull_up>, - <2 RK_PA1 1 &pcfg_pull_none>; - }; - }; - - spi0-0 { - spi0m0_clk: spi0m0-clk { - rockchip,pins = <2 RK_PB0 1 &pcfg_pull_up>; - }; - - spi0m0_cs0: spi0m0-cs0 { - rockchip,pins = <2 RK_PB3 1 &pcfg_pull_up>; - }; - - spi0m0_tx: spi0m0-tx { - rockchip,pins = <2 RK_PB1 1 &pcfg_pull_up>; - }; - - spi0m0_rx: spi0m0-rx { - rockchip,pins = <2 RK_PB2 1 &pcfg_pull_up>; - }; - - spi0m0_cs1: spi0m0-cs1 { - rockchip,pins = <2 RK_PB4 1 &pcfg_pull_up>; - }; - }; - - spi0-1 { - spi0m1_clk: spi0m1-clk { - rockchip,pins = <3 RK_PC7 2 &pcfg_pull_up>; - }; - - spi0m1_cs0: spi0m1-cs0 { - rockchip,pins = <3 RK_PD2 2 &pcfg_pull_up>; - }; - - spi0m1_tx: spi0m1-tx { - rockchip,pins = <3 RK_PD1 2 &pcfg_pull_up>; - }; - - spi0m1_rx: spi0m1-rx { - rockchip,pins = <3 RK_PD0 2 &pcfg_pull_up>; - }; - - spi0m1_cs1: spi0m1-cs1 { - rockchip,pins = <3 RK_PD3 2 &pcfg_pull_up>; - }; - }; - - spi0-2 { - spi0m2_clk: spi0m2-clk { - rockchip,pins = <3 RK_PA0 4 &pcfg_pull_up>; - }; - - spi0m2_cs0: spi0m2-cs0 { - rockchip,pins = <3 RK_PB0 3 &pcfg_pull_up>; - }; - - spi0m2_tx: spi0m2-tx { - rockchip,pins = <3 RK_PA1 4 &pcfg_pull_up>; - }; - - spi0m2_rx: spi0m2-rx { - rockchip,pins = <3 RK_PA2 4 &pcfg_pull_up>; - }; - }; - - i2s1 { - i2s1_mclk: i2s1-mclk { - rockchip,pins = <2 RK_PB7 1 &pcfg_pull_none>; - }; - - i2s1_sclk: i2s1-sclk { - rockchip,pins = <2 RK_PC2 1 &pcfg_pull_none>; - }; - - i2s1_lrckrx: i2s1-lrckrx { - rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>; - }; - - i2s1_lrcktx: i2s1-lrcktx { - rockchip,pins = <2 RK_PC1 1 &pcfg_pull_none>; - }; - - i2s1_sdi: i2s1-sdi { - rockchip,pins = <2 RK_PC3 1 &pcfg_pull_none>; - }; - - i2s1_sdo: i2s1-sdo { - rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>; - }; - - i2s1_sdio1: i2s1-sdio1 { - rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>; - }; - - i2s1_sdio2: i2s1-sdio2 { - rockchip,pins = <2 RK_PC5 1 &pcfg_pull_none>; - }; - - i2s1_sdio3: i2s1-sdio3 { - rockchip,pins = <2 RK_PC6 1 &pcfg_pull_none>; - }; - - i2s1_sleep: i2s1-sleep { - rockchip,pins = - <2 RK_PB7 RK_FUNC_GPIO &pcfg_input_high>, - <2 RK_PC0 RK_FUNC_GPIO &pcfg_input_high>, - <2 RK_PC1 RK_FUNC_GPIO &pcfg_input_high>, - <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>, - <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>, - <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>, - <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>, - <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>, - <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>; - }; - }; - - i2s2-0 { - i2s2m0_mclk: i2s2m0-mclk { - rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>; - }; - - i2s2m0_sclk: i2s2m0-sclk { - rockchip,pins = <1 RK_PC6 1 &pcfg_pull_none>; - }; - - i2s2m0_lrckrx: i2s2m0-lrckrx { - rockchip,pins = <1 RK_PD2 1 &pcfg_pull_none>; - }; - - i2s2m0_lrcktx: i2s2m0-lrcktx { - rockchip,pins = <1 RK_PC7 1 &pcfg_pull_none>; - }; - - i2s2m0_sdi: i2s2m0-sdi { - rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>; - }; - - i2s2m0_sdo: i2s2m0-sdo { - rockchip,pins = <1 RK_PD1 1 &pcfg_pull_none>; - }; - - i2s2m0_sleep: i2s2m0-sleep { - rockchip,pins = - <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>, - <1 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>, - <1 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>, - <1 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>, - <1 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>, - <1 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>; - }; - }; - - i2s2-1 { - i2s2m1_mclk: i2s2m1-mclk { - rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>; - }; - - i2s2m1_sclk: i2s2m1-sclk { - rockchip,pins = <3 RK_PA0 6 &pcfg_pull_none>; - }; - - i2s2m1_lrckrx: i2sm1-lrckrx { - rockchip,pins = <3 RK_PB0 6 &pcfg_pull_none>; - }; - - i2s2m1_lrcktx: i2s2m1-lrcktx { - rockchip,pins = <3 RK_PB0 4 &pcfg_pull_none>; - }; - - i2s2m1_sdi: i2s2m1-sdi { - rockchip,pins = <3 RK_PA2 6 &pcfg_pull_none>; - }; - - i2s2m1_sdo: i2s2m1-sdo { - rockchip,pins = <3 RK_PA1 6 &pcfg_pull_none>; - }; - - i2s2m1_sleep: i2s2m1-sleep { - rockchip,pins = - <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>, - <3 RK_PA0 RK_FUNC_GPIO &pcfg_input_high>, - <3 RK_PB0 RK_FUNC_GPIO &pcfg_input_high>, - <3 RK_PA2 RK_FUNC_GPIO &pcfg_input_high>, - <3 RK_PA1 RK_FUNC_GPIO &pcfg_input_high>; - }; - }; - - spdif-0 { - spdifm0_tx: spdifm0-tx { - rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>; - }; - }; - - spdif-1 { - spdifm1_tx: spdifm1-tx { - rockchip,pins = <2 RK_PC1 2 &pcfg_pull_none>; - }; - }; - - spdif-2 { - spdifm2_tx: spdifm2-tx { - rockchip,pins = <0 RK_PA2 2 &pcfg_pull_none>; - }; - }; - - sdmmc0-0 { - sdmmc0m0_pwren: sdmmc0m0-pwren { - rockchip,pins = <2 RK_PA7 1 &pcfg_pull_up_4ma>; - }; - - sdmmc0m0_gpio: sdmmc0m0-gpio { - rockchip,pins = <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; - }; - }; - - sdmmc0-1 { - sdmmc0m1_pwren: sdmmc0m1-pwren { - rockchip,pins = <0 RK_PD6 3 &pcfg_pull_up_4ma>; - }; - - sdmmc0m1_gpio: sdmmc0m1-gpio { - rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>; - }; - }; - - sdmmc0 { - sdmmc0_clk: sdmmc0-clk { - rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none_8ma>; - }; - - sdmmc0_cmd: sdmmc0-cmd { - rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up_8ma>; - }; - - sdmmc0_dectn: sdmmc0-dectn { - rockchip,pins = <1 RK_PA5 1 &pcfg_pull_up_4ma>; - }; - - sdmmc0_wrprt: sdmmc0-wrprt { - rockchip,pins = <1 RK_PA7 1 &pcfg_pull_up_4ma>; - }; - - sdmmc0_bus1: sdmmc0-bus1 { - rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>; - }; - - sdmmc0_bus4: sdmmc0-bus4 { - rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>, - <1 RK_PA1 1 &pcfg_pull_up_8ma>, - <1 RK_PA2 1 &pcfg_pull_up_8ma>, - <1 RK_PA3 1 &pcfg_pull_up_8ma>; - }; - - sdmmc0_gpio: sdmmc0-gpio { - rockchip,pins = - <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>; - }; - }; - - sdmmc0ext { - sdmmc0ext_clk: sdmmc0ext-clk { - rockchip,pins = <3 RK_PA2 3 &pcfg_pull_none_4ma>; - }; - - sdmmc0ext_cmd: sdmmc0ext-cmd { - rockchip,pins = <3 RK_PA0 3 &pcfg_pull_up_4ma>; - }; - - sdmmc0ext_wrprt: sdmmc0ext-wrprt { - rockchip,pins = <3 RK_PA3 3 &pcfg_pull_up_4ma>; - }; - - sdmmc0ext_dectn: sdmmc0ext-dectn { - rockchip,pins = <3 RK_PA1 3 &pcfg_pull_up_4ma>; - }; - - sdmmc0ext_bus1: sdmmc0ext-bus1 { - rockchip,pins = <3 RK_PA4 3 &pcfg_pull_up_4ma>; - }; - - sdmmc0ext_bus4: sdmmc0ext-bus4 { - rockchip,pins = - <3 RK_PA4 3 &pcfg_pull_up_4ma>, - <3 RK_PA5 3 &pcfg_pull_up_4ma>, - <3 RK_PA6 3 &pcfg_pull_up_4ma>, - <3 RK_PA7 3 &pcfg_pull_up_4ma>; - }; - - sdmmc0ext_gpio: sdmmc0ext-gpio { - rockchip,pins = - <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; - }; - }; - - sdmmc1 { - sdmmc1_clk: sdmmc1-clk { - rockchip,pins = <1 RK_PB4 1 &pcfg_pull_none_8ma>; - }; - - sdmmc1_cmd: sdmmc1-cmd { - rockchip,pins = <1 RK_PB5 1 &pcfg_pull_up_8ma>; - }; - - sdmmc1_pwren: sdmmc1-pwren { - rockchip,pins = <1 RK_PC2 1 &pcfg_pull_up_8ma>; - }; - - sdmmc1_wrprt: sdmmc1-wrprt { - rockchip,pins = <1 RK_PC4 1 &pcfg_pull_up_8ma>; - }; - - sdmmc1_dectn: sdmmc1-dectn { - rockchip,pins = <1 RK_PC3 1 &pcfg_pull_up_8ma>; - }; - - sdmmc1_bus1: sdmmc1-bus1 { - rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>; - }; - - sdmmc1_bus4: sdmmc1-bus4 { - rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>, - <1 RK_PB7 1 &pcfg_pull_up_8ma>, - <1 RK_PC0 1 &pcfg_pull_up_8ma>, - <1 RK_PC1 1 &pcfg_pull_up_8ma>; - }; - - sdmmc1_gpio: sdmmc1-gpio { - rockchip,pins = - <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up_4ma>; - }; - }; - - emmc { - emmc_clk: emmc-clk { - rockchip,pins = <3 RK_PC5 2 &pcfg_pull_none_12ma>; - }; - - emmc_cmd: emmc-cmd { - rockchip,pins = <3 RK_PC3 2 &pcfg_pull_up_12ma>; - }; - - emmc_pwren: emmc-pwren { - rockchip,pins = <3 RK_PC6 2 &pcfg_pull_none>; - }; - - emmc_rstnout: emmc-rstnout { - rockchip,pins = <3 RK_PC4 2 &pcfg_pull_none>; - }; - - emmc_bus1: emmc-bus1 { - rockchip,pins = <0 RK_PA7 2 &pcfg_pull_up_12ma>; - }; - - emmc_bus4: emmc-bus4 { - rockchip,pins = - <0 RK_PA7 2 &pcfg_pull_up_12ma>, - <2 RK_PD4 2 &pcfg_pull_up_12ma>, - <2 RK_PD5 2 &pcfg_pull_up_12ma>, - <2 RK_PD6 2 &pcfg_pull_up_12ma>; - }; - - emmc_bus8: emmc-bus8 { - rockchip,pins = - <0 RK_PA7 2 &pcfg_pull_up_12ma>, - <2 RK_PD4 2 &pcfg_pull_up_12ma>, - <2 RK_PD5 2 &pcfg_pull_up_12ma>, - <2 RK_PD6 2 &pcfg_pull_up_12ma>, - <2 RK_PD7 2 &pcfg_pull_up_12ma>, - <3 RK_PC0 2 &pcfg_pull_up_12ma>, - <3 RK_PC1 2 &pcfg_pull_up_12ma>, - <3 RK_PC2 2 &pcfg_pull_up_12ma>; - }; - }; - - pwm0 { - pwm0_pin: pwm0-pin { - rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>; - }; - }; - - pwm1 { - pwm1_pin: pwm1-pin { - rockchip,pins = <2 RK_PA5 1 &pcfg_pull_none>; - }; - }; - - pwm2 { - pwm2_pin: pwm2-pin { - rockchip,pins = <2 RK_PA6 1 &pcfg_pull_none>; - }; - }; - - pwmir { - pwmir_pin: pwmir-pin { - rockchip,pins = <2 RK_PA2 1 &pcfg_pull_none>; - }; - }; - - gmac-1 { - rgmiim1_pins: rgmiim1-pins { - rockchip,pins = - /* mac_txclk */ - <1 RK_PB4 2 &pcfg_pull_none_8ma>, - /* mac_rxclk */ - <1 RK_PB5 2 &pcfg_pull_none_4ma>, - /* mac_mdio */ - <1 RK_PC3 2 &pcfg_pull_none_4ma>, - /* mac_txen */ - <1 RK_PD1 2 &pcfg_pull_none_8ma>, - /* mac_clk */ - <1 RK_PC5 2 &pcfg_pull_none_4ma>, - /* mac_rxdv */ - <1 RK_PC6 2 &pcfg_pull_none_4ma>, - /* mac_mdc */ - <1 RK_PC7 2 &pcfg_pull_none_4ma>, - /* mac_rxd1 */ - <1 RK_PB2 2 &pcfg_pull_none_4ma>, - /* mac_rxd0 */ - <1 RK_PB3 2 &pcfg_pull_none_4ma>, - /* mac_txd1 */ - <1 RK_PB0 2 &pcfg_pull_none_8ma>, - /* mac_txd0 */ - <1 RK_PB1 2 &pcfg_pull_none_8ma>, - /* mac_rxd3 */ - <1 RK_PB6 2 &pcfg_pull_none_4ma>, - /* mac_rxd2 */ - <1 RK_PB7 2 &pcfg_pull_none_4ma>, - /* mac_txd3 */ - <1 RK_PC0 2 &pcfg_pull_none_8ma>, - /* mac_txd2 */ - <1 RK_PC1 2 &pcfg_pull_none_8ma>, - - /* mac_txclk */ - <0 RK_PB0 1 &pcfg_pull_none_8ma>, - /* mac_txen */ - <0 RK_PB4 1 &pcfg_pull_none_8ma>, - /* mac_clk */ - <0 RK_PD0 1 &pcfg_pull_none_4ma>, - /* mac_txd1 */ - <0 RK_PC0 1 &pcfg_pull_none_8ma>, - /* mac_txd0 */ - <0 RK_PC1 1 &pcfg_pull_none_8ma>, - /* mac_txd3 */ - <0 RK_PC7 1 &pcfg_pull_none_8ma>, - /* mac_txd2 */ - <0 RK_PC6 1 &pcfg_pull_none_8ma>; - }; - - rmiim1_pins: rmiim1-pins { - rockchip,pins = - /* mac_mdio */ - <1 RK_PC3 2 &pcfg_pull_none_2ma>, - /* mac_txen */ - <1 RK_PD1 2 &pcfg_pull_none_12ma>, - /* mac_clk */ - <1 RK_PC5 2 &pcfg_pull_none_2ma>, - /* mac_rxer */ - <1 RK_PD0 2 &pcfg_pull_none_2ma>, - /* mac_rxdv */ - <1 RK_PC6 2 &pcfg_pull_none_2ma>, - /* mac_mdc */ - <1 RK_PC7 2 &pcfg_pull_none_2ma>, - /* mac_rxd1 */ - <1 RK_PB2 2 &pcfg_pull_none_2ma>, - /* mac_rxd0 */ - <1 RK_PB3 2 &pcfg_pull_none_2ma>, - /* mac_txd1 */ - <1 RK_PB0 2 &pcfg_pull_none_12ma>, - /* mac_txd0 */ - <1 RK_PB1 2 &pcfg_pull_none_12ma>, - - /* mac_mdio */ - <0 RK_PB3 1 &pcfg_pull_none>, - /* mac_txen */ - <0 RK_PB4 1 &pcfg_pull_none>, - /* mac_clk */ - <0 RK_PD0 1 &pcfg_pull_none>, - /* mac_mdc */ - <0 RK_PC3 1 &pcfg_pull_none>, - /* mac_txd1 */ - <0 RK_PC0 1 &pcfg_pull_none>, - /* mac_txd0 */ - <0 RK_PC1 1 &pcfg_pull_none>; - }; - }; - - gmac2phy { - fephyled_speed100: fephyled-speed100 { - rockchip,pins = <0 RK_PD7 1 &pcfg_pull_none>; - }; - - fephyled_speed10: fephyled-speed10 { - rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>; - }; - - fephyled_duplex: fephyled-duplex { - rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>; - }; - - fephyled_rxm0: fephyled-rxm0 { - rockchip,pins = <0 RK_PD5 1 &pcfg_pull_none>; - }; - - fephyled_txm0: fephyled-txm0 { - rockchip,pins = <0 RK_PD5 2 &pcfg_pull_none>; - }; - - fephyled_linkm0: fephyled-linkm0 { - rockchip,pins = <0 RK_PD4 1 &pcfg_pull_none>; - }; - - fephyled_rxm1: fephyled-rxm1 { - rockchip,pins = <2 RK_PD1 2 &pcfg_pull_none>; - }; - - fephyled_txm1: fephyled-txm1 { - rockchip,pins = <2 RK_PD1 3 &pcfg_pull_none>; - }; - - fephyled_linkm1: fephyled-linkm1 { - rockchip,pins = <2 RK_PD0 2 &pcfg_pull_none>; - }; - }; - - tsadc_pin { - tsadc_int: tsadc-int { - rockchip,pins = <2 RK_PB5 2 &pcfg_pull_none>; - }; - tsadc_gpio: tsadc-gpio { - rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - hdmi_pin { - hdmi_cec: hdmi-cec { - rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>; - }; - - hdmi_hpd: hdmi-hpd { - rockchip,pins = <0 RK_PA4 1 &pcfg_pull_down>; - }; - }; - - cif-0 { - dvp_d2d9_m0:dvp-d2d9-m0 { - rockchip,pins = - /* cif_d0 */ - <3 RK_PA4 2 &pcfg_pull_none>, - /* cif_d1 */ - <3 RK_PA5 2 &pcfg_pull_none>, - /* cif_d2 */ - <3 RK_PA6 2 &pcfg_pull_none>, - /* cif_d3 */ - <3 RK_PA7 2 &pcfg_pull_none>, - /* cif_d4 */ - <3 RK_PB0 2 &pcfg_pull_none>, - /* cif_d5m0 */ - <3 RK_PB1 2 &pcfg_pull_none>, - /* cif_d6m0 */ - <3 RK_PB2 2 &pcfg_pull_none>, - /* cif_d7m0 */ - <3 RK_PB3 2 &pcfg_pull_none>, - /* cif_href */ - <3 RK_PA1 2 &pcfg_pull_none>, - /* cif_vsync */ - <3 RK_PA0 2 &pcfg_pull_none>, - /* cif_clkoutm0 */ - <3 RK_PA3 2 &pcfg_pull_none>, - /* cif_clkin */ - <3 RK_PA2 2 &pcfg_pull_none>; - }; - }; - - cif-1 { - dvp_d2d9_m1:dvp-d2d9-m1 { - rockchip,pins = - /* cif_d0 */ - <3 RK_PA4 2 &pcfg_pull_none>, - /* cif_d1 */ - <3 RK_PA5 2 &pcfg_pull_none>, - /* cif_d2 */ - <3 RK_PA6 2 &pcfg_pull_none>, - /* cif_d3 */ - <3 RK_PA7 2 &pcfg_pull_none>, - /* cif_d4 */ - <3 RK_PB0 2 &pcfg_pull_none>, - /* cif_d5m1 */ - <2 RK_PC0 4 &pcfg_pull_none>, - /* cif_d6m1 */ - <2 RK_PC1 4 &pcfg_pull_none>, - /* cif_d7m1 */ - <2 RK_PC2 4 &pcfg_pull_none>, - /* cif_href */ - <3 RK_PA1 2 &pcfg_pull_none>, - /* cif_vsync */ - <3 RK_PA0 2 &pcfg_pull_none>, - /* cif_clkoutm1 */ - <2 RK_PB7 4 &pcfg_pull_none>, - /* cif_clkin */ - <3 RK_PA2 2 &pcfg_pull_none>; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/rockchip/rk3368-evb-act8846.dts b/sys/gnu/dts/arm64/rockchip/rk3368-evb-act8846.dts deleted file mode 100644 index 160f2c7e955..00000000000 --- a/sys/gnu/dts/arm64/rockchip/rk3368-evb-act8846.dts +++ /dev/null @@ -1,139 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2015 Caesar Wang - */ - -/dts-v1/; -#include "rk3368-evb.dtsi" - -/ { - model = "Rockchip RK3368 EVB with ACT8846 pmic"; - compatible = "rockchip,rk3368-evb-act8846", "rockchip,rk3368"; -}; - -&i2c0 { - clock-frequency = <400000>; - - vdd_cpu: syr827@40 { - compatible = "silergy,syr827"; - reg = <0x40>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_cpu"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_sys>; - }; - - vdd_gpu: syr828@41 { - compatible = "silergy,syr828"; - reg = <0x41>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_gpu"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - vin-supply = <&vcc_sys>; - }; - - act8846: act8846@5a { - compatible = "active-semi,act8846"; - reg = <0x5a>; - status = "okay"; - - vp1-supply = <&vcc_sys>; - vp2-supply = <&vcc_sys>; - vp3-supply = <&vcc_sys>; - vp4-supply = <&vcc_sys>; - inl1-supply = <&vcc_io>; - inl2-supply = <&vcc_sys>; - inl3-supply = <&vcc_20>; - - regulators { - vcc_ddr: REG1 { - regulator-name = "VCC_DDR"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - vcc_io: REG2 { - regulator-name = "VCC_IO"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_log: REG3 { - regulator-name = "VDD_LOG"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - }; - - vcc_20: REG4 { - regulator-name = "VCC_20"; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - regulator-always-on; - }; - - vccio_sd: REG5 { - regulator-name = "VCCIO_SD"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd10_lcd: REG6 { - regulator-name = "VDD10_LCD"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - vcca_codec: REG7 { - regulator-name = "VCCA_CODEC"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vcca_tp: REG8 { - regulator-name = "VCCA_TP"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vccio_pmu: REG9 { - regulator-name = "VCCIO_PMU"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_10: REG10 { - regulator-name = "VDD_10"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - vcc_18: REG11 { - regulator-name = "VCC_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vcc18_lcd: REG12 { - regulator-name = "VCC18_LCD"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/rockchip/rk3368-evb.dtsi b/sys/gnu/dts/arm64/rockchip/rk3368-evb.dtsi deleted file mode 100644 index 1c52f47c43a..00000000000 --- a/sys/gnu/dts/arm64/rockchip/rk3368-evb.dtsi +++ /dev/null @@ -1,240 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2015 Caesar Wang - */ - -#include -#include -#include "rk3368.dtsi" - -/ { - chosen { - stdout-path = "serial2:115200n8"; - }; - - memory { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x40000000>; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - brightness-levels = < - 0 1 2 3 4 5 6 7 - 8 9 10 11 12 13 14 15 - 16 17 18 19 20 21 22 23 - 24 25 26 27 28 29 30 31 - 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 - 48 49 50 51 52 53 54 55 - 56 57 58 59 60 61 62 63 - 64 65 66 67 68 69 70 71 - 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 - 88 89 90 91 92 93 94 95 - 96 97 98 99 100 101 102 103 - 104 105 106 107 108 109 110 111 - 112 113 114 115 116 117 118 119 - 120 121 122 123 124 125 126 127 - 128 129 130 131 132 133 134 135 - 136 137 138 139 140 141 142 143 - 144 145 146 147 148 149 150 151 - 152 153 154 155 156 157 158 159 - 160 161 162 163 164 165 166 167 - 168 169 170 171 172 173 174 175 - 176 177 178 179 180 181 182 183 - 184 185 186 187 188 189 190 191 - 192 193 194 195 196 197 198 199 - 200 201 202 203 204 205 206 207 - 208 209 210 211 212 213 214 215 - 216 217 218 219 220 221 222 223 - 224 225 226 227 228 229 230 231 - 232 233 234 235 236 237 238 239 - 240 241 242 243 244 245 246 247 - 248 249 250 251 252 253 254 255>; - default-brightness-level = <128>; - enable-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&bl_en>; - pwms = <&pwm0 0 1000000 PWM_POLARITY_INVERTED>; - pwm-delay-us = <10000>; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - pinctrl-0 = <&emmc_reset>; - pinctrl-names = "default"; - reset-gpios = <&gpio2 RK_PA3 GPIO_ACTIVE_HIGH>; - }; - - keys: gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pwr_key>; - - power { - wakeup-source; - gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; - label = "GPIO Power"; - linux,code = ; - }; - }; - - /* supplies both host and otg */ - vcc_host: vcc-host-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&host_vbus_drv>; - regulator-name = "vcc_host"; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_sys>; - }; - - vcc_lan: vcc-lan-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_lan"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_io>; - }; - - vcc_sys: vcc-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; -}; - -&emmc { - bus-width = <8>; - cap-mmc-highspeed; - mmc-pwrseq = <&emmc_pwrseq>; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; - status = "okay"; -}; - -&gmac { - phy-supply = <&vcc_lan>; - phy-mode = "rmii"; - clock_in_out = "output"; - snps,reset-gpio = <&gpio3 RK_PB4 GPIO_ACTIVE_HIGH>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 1000000>; - pinctrl-names = "default"; - pinctrl-0 = <&rmii_pins>; - tx_delay = <0x30>; - rx_delay = <0x10>; - status = "ok"; -}; - -&i2c0 { - status = "okay"; -}; - -&pinctrl { - pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma { - bias-disable; - drive-strength = <8>; - }; - - pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma { - bias-pull-up; - drive-strength = <8>; - }; - - backlight { - bl_en: bl-en { - rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - emmc { - emmc_bus8: emmc-bus8 { - rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up_drv_8ma>, - <1 RK_PC3 2 &pcfg_pull_up_drv_8ma>, - <1 RK_PC4 2 &pcfg_pull_up_drv_8ma>, - <1 RK_PC5 2 &pcfg_pull_up_drv_8ma>, - <1 RK_PC6 2 &pcfg_pull_up_drv_8ma>, - <1 RK_PC7 2 &pcfg_pull_up_drv_8ma>, - <1 RK_PD0 2 &pcfg_pull_up_drv_8ma>, - <1 RK_PD1 2 &pcfg_pull_up_drv_8ma>; - }; - - emmc-clk { - rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none_drv_8ma>; - }; - - emmc-cmd { - rockchip,pins = <1 RK_PD2 2 &pcfg_pull_up_drv_8ma>; - }; - - emmc_reset: emmc-reset { - rockchip,pins = <2 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - keys { - pwr_key: pwr-key { - rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - pmic { - pmic_int: pmic-int { - rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - sdio { - wifi_reg_on: wifi-reg-on { - rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_rst: bt-rst { - rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb { - host_vbus_drv: host-vbus-drv { - rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&pwm0 { - status = "okay"; -}; - -&tsadc { - rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ - rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_otg { - dr_mode = "host"; - status = "okay"; -}; - -&wdt { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/rockchip/rk3368-geekbox.dts b/sys/gnu/dts/arm64/rockchip/rk3368-geekbox.dts deleted file mode 100644 index 1d0778ff217..00000000000 --- a/sys/gnu/dts/arm64/rockchip/rk3368-geekbox.dts +++ /dev/null @@ -1,277 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Andreas Färber - */ - -/dts-v1/; -#include "rk3368.dtsi" -#include - -/ { - model = "GeekBox"; - compatible = "geekbuying,geekbox", "rockchip,rk3368"; - - chosen { - stdout-path = "serial2:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; - - ext_gmac: gmac-clk { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "ext_gmac"; - #clock-cells = <0>; - }; - - ir: ir-receiver { - compatible = "gpio-ir-receiver"; - gpios = <&gpio3 RK_PD6 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&ir_int>; - }; - - keys: gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pwr_key>; - - power { - gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; - label = "GPIO Power"; - linux,code = ; - wakeup-source; - }; - }; - - leds: gpio-leds { - compatible = "gpio-leds"; - - blue { - gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_HIGH>; - label = "geekbox:blue:led"; - default-state = "on"; - }; - - red { - gpios = <&gpio2 RK_PA3 GPIO_ACTIVE_HIGH>; - label = "geekbox:red:led"; - default-state = "off"; - }; - }; - - vcc_sys: vcc-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; -}; - -&emmc { - status = "okay"; - bus-width = <8>; - cap-mmc-highspeed; - clock-frequency = <150000000>; - non-removable; - vmmc-supply = <&vcc_io>; - vqmmc-supply = <&vcc18_flash>; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_bus8>; -}; - -&gmac { - status = "okay"; - phy-supply = <&vcc_lan>; - phy-mode = "rgmii"; - clock_in_out = "input"; - assigned-clocks = <&cru SCLK_MAC>; - assigned-clock-parents = <&ext_gmac>; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - tx_delay = <0x30>; - rx_delay = <0x10>; -}; - -&i2c0 { - status = "okay"; - - rk808: pmic@1b { - compatible = "rockchip,rk808"; - reg = <0x1b>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int>, <&pmic_sleep>; - interrupt-parent = <&gpio0>; - interrupts = ; - rockchip,system-power-controller; - vcc1-supply = <&vcc_sys>; - vcc2-supply = <&vcc_sys>; - vcc3-supply = <&vcc_sys>; - vcc4-supply = <&vcc_sys>; - vcc6-supply = <&vcc_sys>; - vcc7-supply = <&vcc_sys>; - vcc8-supply = <&vcc_io>; - vcc9-supply = <&vcc_sys>; - vcc10-supply = <&vcc_sys>; - vcc11-supply = <&vcc_sys>; - vcc12-supply = <&vcc_io>; - clock-output-names = "xin32k", "rk808-clkout2"; - #clock-cells = <1>; - - regulators { - vdd_cpu: DCDC_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vdd_cpu"; - }; - - vdd_log: DCDC_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vdd_log"; - }; - - vcc_ddr: DCDC_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc_ddr"; - }; - - vcc_io: DCDC_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc_io"; - }; - - vcc18_flash: LDO_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc18_flash"; - }; - - vcc33_lcd: LDO_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc33_lcd"; - }; - - vdd_10: LDO_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-name = "vdd_10"; - }; - - vcca_18: LDO_REG4 { - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcca_18"; - }; - - vccio_sd: LDO_REG5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vccio_sd"; - }; - - vdd10_lcd: LDO_REG6 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-name = "vdd10_lcd"; - }; - - vcc_18: LDO_REG7 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc_18"; - }; - - vcc18_lcd: LDO_REG8 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc18_lcd"; - }; - - vcc_sd: SWITCH_REG1 { - regulator-name = "vcc_sd"; - }; - - vcc_lan: SWITCH_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc_lan"; - }; - }; - }; -}; - -&pinctrl { - ir { - ir_int: ir-int { - rockchip,pins = <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - keys { - pwr_key: pwr-key { - rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - pmic_sleep: pmic-sleep { - rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>; - }; - - pmic_int: pmic-int { - rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; -}; - -&tsadc { - status = "okay"; - rockchip,hw-tshut-mode = <0>; /* CRU */ - rockchip,hw-tshut-polarity = <1>; /* high */ -}; - -&uart2 { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_otg { - status = "okay"; -}; - -&wdt { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/rockchip/rk3368-lion-haikou.dts b/sys/gnu/dts/arm64/rockchip/rk3368-lion-haikou.dts deleted file mode 100644 index cbde279ae81..00000000000 --- a/sys/gnu/dts/arm64/rockchip/rk3368-lion-haikou.dts +++ /dev/null @@ -1,140 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2018 Theobroma Systems Design und Consulting GmbH - */ - -/dts-v1/; -#include "rk3368-lion.dtsi" - -/ { - model = "Theobroma Systems RK3368-uQ7 Baseboard"; - compatible = "tsd,rk3368-lion-haikou", "rockchip,rk3368"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - i2cmux2 { - i2c@0 { - eeprom: eeprom@50 { - compatible = "atmel,24c01"; - pagesize = <8>; - reg = <0x50>; - }; - }; - }; - - leds { - pinctrl-0 = <&led_pins_module>, <&led_sd_haikou>; - - sd-card-led { - label = "sd_card_led"; - gpios = <&gpio0 RK_PD2 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc0"; - }; - }; - - dc_12v: dc-12v { - compatible = "regulator-fixed"; - regulator-name = "dc_12v"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - vcc3v3_baseboard: vcc3v3-baseboard { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_baseboard"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&dc_12v>; - }; - - vcc5v0_otg: vcc5v0-otg-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&otg_vbus_drv>; - regulator-name = "vcc5v0_otg"; - regulator-always-on; - }; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - cd-gpios = <&gpio2 RK_PB3 GPIO_ACTIVE_LOW>; - disable-wp; - max-frequency = <25000000>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; - rockchip,default-sample-phase = <90>; - vmmc-supply = <&vcc3v3_baseboard>; - status = "okay"; -}; - -&spi2 { - cs-gpios = <0>, <&gpio2 RK_PC3 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; - status = "okay"; -}; - -&uart1 { - /* alternate function of GPIO5/6 */ - status = "disabled"; -}; - -&pinctrl { - pinctrl-names = "default"; - pinctrl-0 = <&haikou_pin_hog>; - - hog { - haikou_pin_hog: haikou-pin-hog { - rockchip,pins = - /* LID_BTN */ - <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>, - /* BATLOW# */ - <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>, - /* SLP_BTN# */ - <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>, - /* BIOS_DISABLE# */ - <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - leds { - led_sd_haikou: led-sd-gpio { - rockchip,pins = - <0 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - sdmmc { - sdmmc_cd_gpio: sdmmc-cd-gpio { - rockchip,pins = - <2 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb_otg { - otg_vbus_drv: otg-vbus-drv { - rockchip,pins = - <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/rockchip/rk3368-lion.dtsi b/sys/gnu/dts/arm64/rockchip/rk3368-lion.dtsi deleted file mode 100644 index e17311e0908..00000000000 --- a/sys/gnu/dts/arm64/rockchip/rk3368-lion.dtsi +++ /dev/null @@ -1,314 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2018 Theobroma Systems Design und Consulting GmbH - */ - -/dts-v1/; -#include "rk3368.dtsi" - -/ { - chosen { - stdout-path = "serial0:115200n8"; - }; - - ext_gmac: gmac-clk { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "ext_gmac"; - #clock-cells = <0>; - }; - - i2cmux1 { - compatible = "i2c-mux-gpio"; - #address-cells = <1>; - #size-cells = <0>; - i2c-parent = <&i2c1>; - mux-gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>; - - /* Q7_GPO_I2C */ - i2c@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - }; - - /* Q7_SMB */ - i2c@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - i2cmux2 { - compatible = "i2c-mux-gpio"; - #address-cells = <1>; - #size-cells = <0>; - i2c-parent = <&i2c2>; - mux-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; - - /* Q7_LVDS_BLC_I2C */ - i2c@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - fan: fan@18 { - compatible = "ti,amc6821"; - reg = <0x18>; - #cooling-cells = <2>; - }; - - rtc_twi: rtc@6f { - compatible = "isil,isl1208"; - reg = <0x6f>; - }; - }; - - /* Q7_GP2_I2C */ - i2c@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_module>; - - module_led1 { - label = "module_led1"; - gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - panic-indicator; - }; - - module_led2 { - label = "module_led2"; - gpios = <&gpio3 RK_PA3 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - - vcc_sys: vcc-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; -}; - -&cpu_l0 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu_l1 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu_l2 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu_l3 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu_b0 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu_b1 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu_b2 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu_b3 { - cpu-supply = <&vdd_cpu>; -}; - -&emmc { - bus-width = <8>; - clock-frequency = <150000000>; - mmc-hs200-1_8v; - non-removable; - vmmc-supply = <&vcc33_io>; - vqmmc-supply = <&vcc18_io>; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_bus8>; - status = "okay"; -}; - -&gmac { - assigned-clocks = <&cru SCLK_MAC>; - assigned-clock-parents = <&ext_gmac>; - clock_in_out = "input"; - phy-supply = <&vcc33_io>; - phy-mode = "rgmii"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 50000>; - snps,reset-gpio = <&gpio3 RK_PB3 GPIO_ACTIVE_HIGH>; - tx_delay = <0x10>; - rx_delay = <0x10>; - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - rk808: pmic@1b { - compatible = "rockchip,rk808"; - reg = <0x1b>; - interrupt-parent = <&gpio0>; - interrupts = ; - clock-output-names = "xin32k", "rk808-clkout2"; - #clock-cells = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l>, <&pmic_sleep>; - rockchip,system-power-controller; - vcc1-supply = <&vcc_sys>; - vcc2-supply = <&vcc_sys>; - vcc3-supply = <&vcc_sys>; - vcc4-supply = <&vcc_sys>; - vcc6-supply = <&vcc_sys>; - vcc7-supply = <&vcc_sys>; - vcc8-supply = <&vcc_sys>; - vcc9-supply = <&vcc_sys>; - vcc10-supply = <&vcc_sys>; - vcc11-supply = <&vcc_sys>; - vcc12-supply = <&vcc_sys>; - - regulators { - vdd_cpu: DCDC_REG1 { - regulator-name = "vdd_cpu"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_log: DCDC_REG2 { - regulator-name = "vdd_log"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - }; - - vcc33_io: DCDC_REG4 { - regulator-name = "vcc33_io"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - vcc33_video: LDO_REG2 { - regulator-name = "vcc33_video"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd10_pll: LDO_REG3 { - regulator-name = "vdd10_pll"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-boot-on; - }; - - vcc18_io: LDO_REG4 { - regulator-name = "vcc18_io"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - }; - - vdd10_video: LDO_REG6 { - regulator-name = "vdd10_video"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-boot-on; - }; - - vcc18_video: LDO_REG8 { - regulator-name = "vcc18_video"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - }; - }; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&pinctrl { - leds { - led_pins_module: led-module-gpio { - rockchip,pins = - <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>, - <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - pmic { - pmic_int_l: pmic-int-l { - rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - pmic_sleep: pmic-sleep { - rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>; - }; - }; -}; - -&spi1 { - status = "okay"; - - norflash: flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <50000000>; - }; -}; - -&uart1 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&wdt { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/rockchip/rk3368-orion-r68-meta.dts b/sys/gnu/dts/arm64/rockchip/rk3368-orion-r68-meta.dts deleted file mode 100644 index 6cc310255da..00000000000 --- a/sys/gnu/dts/arm64/rockchip/rk3368-orion-r68-meta.dts +++ /dev/null @@ -1,338 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Matthias Brugger - */ - -/dts-v1/; -#include -#include "rk3368.dtsi" - -/ { - model = "Rockchip Orion R68"; - compatible = "tronsmart,orion-r68-meta", "rockchip,rk3368"; - - chosen { - stdout-path = "serial2:115200n8"; - }; - - memory { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - pinctrl-0 = <&emmc_reset>; - pinctrl-names = "default"; - reset-gpios = <&gpio2 RK_PA3 GPIO_ACTIVE_HIGH>; - }; - - ext_gmac: external-gmac-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <125000000>; - clock-output-names = "ext_gmac"; - }; - - keys: gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pwr_key>; - - power { - wakeup-source; - gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; - label = "GPIO Power"; - linux,code = ; - }; - }; - - leds: gpio-leds { - compatible = "gpio-leds"; - - red { - gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; - label = "orion:red:led"; - pinctrl-names = "default"; - pinctrl-0 = <&led_ctl>; - default-state = "on"; - }; - - blue { - gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; - label = "orion:blue:led"; - pinctrl-names = "default"; - pinctrl-0 = <&stby_pwren>; - default-state = "off"; - }; - }; - - vcc_18: vcc18-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_sys>; - }; - - /* supplies both host and otg */ - vcc_host: vcc-host-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&host_vbus_drv>; - regulator-name = "vcc_host"; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_sys>; - }; - - vcc_io: vcc-io-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_io"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_sys>; - }; - - vcc_lan: vcc-lan-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_lan"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_io>; - }; - - vcc_sd: vcc-sd-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_sd"; - gpio = <&gpio3 RK_PB3 GPIO_ACTIVE_LOW>; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_io>; - }; - - vcc_sys: vcc-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - vccio_sd: vcc-io-sd-regulator { - compatible = "regulator-fixed"; - regulator-name= "vccio_sd"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_io>; - }; - - vccio_wl: vccio-wl-regulator { - compatible = "regulator-fixed"; - regulator-name = "vccio_wl"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_io>; - }; - - vdd_10: vdd-10-regulator { - compatible = "regulator-fixed"; - regulator-name = "vdd_10"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_sys>; - }; -}; - -&emmc { - bus-width = <8>; - cap-mmc-highspeed; - mmc-pwrseq = <&emmc_pwrseq>; - mmc-hs200-1_2v; - mmc-hs200-1_8v; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; - status = "okay"; -}; - -&gmac { - assigned-clocks = <&cru SCLK_MAC>; - assigned-clock-parents = <&ext_gmac>; - clock_in_out = "input"; - phy-supply = <&vcc_lan>; - phy-mode = "rgmii"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - snps,reset-gpio = <&gpio3 RK_PB4 GPIO_ACTIVE_HIGH>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 1000000>; - tx_delay = <0x30>; - rx_delay = <0x10>; - status = "ok"; -}; - -&i2c0 { - status = "okay"; - - vdd_cpu: syr827@40 { - compatible = "silergy,syr827"; - reg = <0x40>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_cpu"; - regulator-enable-ramp-delay = <300>; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1500000>; - regulator-ramp-delay = <8000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_sys>; - }; - - hym8563: hym8563@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "xin32k"; - /* rtc_int is not connected */ - }; -}; - -&pinctrl { - pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma { - bias-disable; - drive-strength = <8>; - }; - - pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma { - bias-pull-up; - drive-strength = <8>; - }; - - emmc { - emmc_bus8: emmc-bus8 { - rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up_drv_8ma>, - <1 RK_PC3 2 &pcfg_pull_up_drv_8ma>, - <1 RK_PC4 2 &pcfg_pull_up_drv_8ma>, - <1 RK_PC5 2 &pcfg_pull_up_drv_8ma>, - <1 RK_PC6 2 &pcfg_pull_up_drv_8ma>, - <1 RK_PC7 2 &pcfg_pull_up_drv_8ma>, - <1 RK_PD0 2 &pcfg_pull_up_drv_8ma>, - <1 RK_PD1 2 &pcfg_pull_up_drv_8ma>; - }; - - emmc-clk { - rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none_drv_8ma>; - }; - - emmc-cmd { - rockchip,pins = <1 RK_PD2 2 &pcfg_pull_up_drv_8ma>; - }; - - emmc_reset: emmc-reset { - rockchip,pins = <2 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - keys { - pwr_key: pwr-key { - rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; - - leds { - stby_pwren: stby-pwren { - rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - led_ctl: led-ctl { - rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - sdmmc { - sdmmc_clk: sdmmc-clk { - rockchip,pins = <2 RK_PB1 1 &pcfg_pull_none_drv_8ma>; - }; - - sdmmc_cmd: sdmmc-cmd { - rockchip,pins = <2 RK_PB2 1 &pcfg_pull_up_drv_8ma>; - }; - - sdmmc_cd: sdmmc-cd { - rockchip,pins = <2 RK_PB3 1 &pcfg_pull_up_drv_8ma>; - }; - - sdmmc_bus1: sdmmc-bus1 { - rockchip,pins = <2 RK_PA5 1 &pcfg_pull_up_drv_8ma>; - }; - - sdmmc_bus4: sdmmc-bus4 { - rockchip,pins = <2 RK_PA5 1 &pcfg_pull_up_drv_8ma>, - <2 RK_PA6 1 &pcfg_pull_up_drv_8ma>, - <2 RK_PA7 1 &pcfg_pull_up_drv_8ma>, - <2 RK_PB0 1 &pcfg_pull_up_drv_8ma>; - }; - }; - - usb { - host_vbus_drv: host-vbus-drv { - rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&saradc { - vref-supply = <&vcc_18>; - status = "okay"; -}; - -&sdmmc { - bus-width = <4>; - clock-frequency = <50000000>; - max-frequency = <50000000>; - cap-sd-highspeed; - card-detect-delay = <200>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; - vmmc-supply = <&vcc_sd>; - vqmmc-supply = <&vccio_sd>; - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&uart4_xfer>; - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_otg { - status = "okay"; -}; - -&wdt { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/rockchip/rk3368-px5-evb.dts b/sys/gnu/dts/arm64/rockchip/rk3368-px5-evb.dts deleted file mode 100644 index 231db0305a0..00000000000 --- a/sys/gnu/dts/arm64/rockchip/rk3368-px5-evb.dts +++ /dev/null @@ -1,273 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd - */ - -/dts-v1/; -#include "rk3368.dtsi" -#include - -/ { - model = "Rockchip PX5 EVB"; - compatible = "rockchip,px5-evb", "rockchip,px5", "rockchip,rk3368"; - - chosen { - stdout-path = "serial4:115200n8"; - }; - - memory@0 { - reg = <0x0 0x0 0x0 0x40000000>; - device_type = "memory"; - }; - - keys: gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pwr_key>; - - power { - gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; - label = "GPIO Power"; - linux,code = ; - wakeup-source; - }; - }; - - vcc_sys: vcc-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; -}; - -&emmc { - status = "okay"; - bus-width = <8>; - cap-mmc-highspeed; - clock-frequency = <150000000>; - mmc-hs200-1_8v; - no-sdio; - no-sd; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_bus8>; - vmmc-supply = <&vcc_io>; - vqmmc-supply = <&vcc18_flash>; -}; - -&i2c0 { - status = "okay"; - - rk808: pmic@1b { - compatible = "rockchip,rk808"; - reg = <0x1b>; - interrupt-parent = <&gpio0>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int>, <&pmic_sleep>; - rockchip,system-power-controller; - vcc1-supply = <&vcc_sys>; - vcc2-supply = <&vcc_sys>; - vcc3-supply = <&vcc_sys>; - vcc4-supply = <&vcc_sys>; - vcc6-supply = <&vcc_sys>; - vcc7-supply = <&vcc_sys>; - vcc8-supply = <&vcc_io>; - vcc9-supply = <&vcc_sys>; - vcc10-supply = <&vcc_sys>; - vcc11-supply = <&vcc_sys>; - vcc12-supply = <&vcc_io>; - clock-output-names = "xin32k", "rk808-clkout2"; - #clock-cells = <1>; - - regulators { - vdd_cpu: DCDC_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vdd_cpu"; - }; - - vdd_log: DCDC_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vdd_log"; - }; - - vcc_ddr: DCDC_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc_ddr"; - }; - - vcc_io: DCDC_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc_io"; - }; - - vcc18_flash: LDO_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc18_flash"; - }; - - vcca_33: LDO_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcca_33"; - }; - - vdd_10: LDO_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-name = "vdd_10"; - }; - - avdd_33: LDO_REG4 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "avdd_33"; - }; - - vccio_sd: LDO_REG5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vccio_sd"; - }; - - vdd10_lcd: LDO_REG6 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-name = "vdd10_lcd"; - }; - - vcc_18: LDO_REG7 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc_18"; - }; - - vcc18_lcd: LDO_REG8 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc18_lcd"; - }; - - vcc_sd: SWITCH_REG1 { - regulator-name = "vcc_sd"; - }; - - vcc33_lcd: SWITCH_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc33_lcd"; - }; - }; - }; -}; - -&i2c1 { - status = "okay"; - - accelerometer@18 { - compatible = "bosch,bma250"; - reg = <0x18>; - interrupt-parent = <&gpio2>; - interrupts = ; - }; -}; - -&i2c2 { - status = "okay"; - - gsl1680: touchscreen@40 { - compatible = "silead,gsl1680"; - reg = <0x40>; - interrupt-parent = <&gpio3>; - interrupts = ; - power-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>; - touchscreen-size-x = <800>; - touchscreen-size-y = <1280>; - silead,max-fingers = <5>; - }; -}; - -&pinctrl { - keys { - pwr_key: pwr-key { - rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - pmic_sleep: pmic-sleep { - rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>; - }; - - pmic_int: pmic-int { - rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; -}; - -&sdmmc { - status = "okay"; - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - card-detect-delay = <200>; - no-emmc; - no-sdio; - sd-uhs-sdr12; - sd-uhs-sdr25; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_bus4>, <&sdmmc_cd>; - rockchip,default-sample-phase = <90>; - vmmc-supply = <&vcc_sd>; - vqmmc-supply = <&vccio_sd>; -}; - -&tsadc { - status = "okay"; - rockchip,hw-tshut-mode = <0>; /* CRU */ - rockchip,hw-tshut-polarity = <1>; /* high */ -}; - -&uart4 { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_otg { - status = "okay"; -}; - -&wdt { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/rockchip/rk3368-r88.dts b/sys/gnu/dts/arm64/rockchip/rk3368-r88.dts deleted file mode 100644 index 006a1fb6a81..00000000000 --- a/sys/gnu/dts/arm64/rockchip/rk3368-r88.dts +++ /dev/null @@ -1,333 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2015 Heiko Stuebner - */ - -/dts-v1/; -#include "rk3368.dtsi" -#include - -/ { - model = "Rockchip R88"; - compatible = "rockchip,r88", "rockchip,rk3368"; - - chosen { - stdout-path = "serial2:115200n8"; - }; - - memory { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x40000000>; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - pinctrl-0 = <&emmc_reset>; - pinctrl-names = "default"; - reset-gpios = <&gpio2 RK_PA3 GPIO_ACTIVE_HIGH>; - }; - - keys: gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pwr_key>; - - power { - wakeup-source; - gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; - label = "GPIO Power"; - linux,code = ; - }; - }; - - leds: gpio-leds { - compatible = "gpio-leds"; - - work { - gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; - label = "r88:green:led"; - pinctrl-names = "default"; - pinctrl-0 = <&led_ctl>; - }; - }; - - ir: ir-receiver { - compatible = "gpio-ir-receiver"; - gpios = <&gpio3 RK_PD6 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&ir_int>; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&hym8563>; - clock-names = "ext_clock"; - pinctrl-names = "default"; - pinctrl-0 = <&bt_rst>, <&wifi_reg_on>; - - reset-gpios = - /* BT_RST_N */ - <&gpio3 RK_PA5 GPIO_ACTIVE_LOW>, - - /* WL_REG_ON */ - <&gpio3 RK_PA4 GPIO_ACTIVE_LOW>; - }; - - vcc_18: vcc18-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_sys>; - }; - - /* supplies both host and otg */ - vcc_host: vcc-host-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&host_vbus_drv>; - regulator-name = "vcc_host"; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_sys>; - }; - - vcc_io: vcc-io-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_io"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_sys>; - }; - - vcc_lan: vcc-lan-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_lan"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_io>; - }; - - vcc_sys: vcc-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - vccio_wl: vccio-wl-regulator { - compatible = "regulator-fixed"; - regulator-name = "vccio_wl"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_io>; - }; - - vdd_10: vdd-10-regulator { - compatible = "regulator-fixed"; - regulator-name = "vdd_10"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_sys>; - }; -}; - -&emmc { - bus-width = <8>; - cap-mmc-highspeed; - mmc-pwrseq = <&emmc_pwrseq>; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; - status = "okay"; -}; - -&gmac { - phy-supply = <&vcc_lan>; - phy-mode = "rmii"; - clock_in_out = "output"; - snps,reset-gpio = <&gpio3 RK_PB4 GPIO_ACTIVE_HIGH>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 1000000>; - pinctrl-names = "default"; - pinctrl-0 = <&rmii_pins>; - tx_delay = <0x30>; - rx_delay = <0x10>; - status = "ok"; -}; - -&i2c0 { - status = "okay"; - - vdd_cpu: syr827@40 { - compatible = "silergy,syr827"; - reg = <0x40>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_cpu"; - regulator-enable-ramp-delay = <300>; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1500000>; - regulator-ramp-delay = <8000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_sys>; - }; - - hym8563: hym8563@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "xin32k"; - /* rtc_int is not connected */ - }; -}; - -&io_domains { - status = "ok"; - - audio-supply = <&vcc_io>; - gpio30-supply = <&vcc_io>; - gpio1830-supply = <&vcc_io>; - wifi-supply = <&vccio_wl>; -}; - -&sdio0 { - assigned-clocks = <&cru SCLK_SDIO0>; - assigned-clock-parents = <&cru PLL_CPLL>; - bus-width = <4>; - cap-sd-highspeed; - cap-sdio-irq; - keep-power-in-suspend; - mmc-pwrseq = <&sdio_pwrseq>; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_bus4>; - vmmc-supply = <&vcc_io>; - vqmmc-supply = <&vccio_wl>; - status = "okay"; -}; - -&pinctrl { - pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma { - bias-disable; - drive-strength = <8>; - }; - - pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma { - bias-pull-up; - drive-strength = <8>; - }; - - emmc { - emmc_bus8: emmc-bus8 { - rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up_drv_8ma>, - <1 RK_PC3 2 &pcfg_pull_up_drv_8ma>, - <1 RK_PC4 2 &pcfg_pull_up_drv_8ma>, - <1 RK_PC5 2 &pcfg_pull_up_drv_8ma>, - <1 RK_PC6 2 &pcfg_pull_up_drv_8ma>, - <1 RK_PC7 2 &pcfg_pull_up_drv_8ma>, - <1 RK_PD0 2 &pcfg_pull_up_drv_8ma>, - <1 RK_PD1 2 &pcfg_pull_up_drv_8ma>; - }; - - emmc-clk { - rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none_drv_8ma>; - }; - - emmc-cmd { - rockchip,pins = <1 RK_PD2 2 &pcfg_pull_up_drv_8ma>; - }; - - emmc_reset: emmc-reset { - rockchip,pins = <2 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - ir { - ir_int: ir-int { - rockchip,pins = <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - keys { - pwr_key: pwr-key { - rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - leds { - stby_pwren: stby-pwren { - rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - led_ctl: led-ctl { - rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - sdio { - wifi_reg_on: wifi-reg-on { - rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_rst: bt-rst { - rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb { - host_vbus_drv: host-vbus-drv { - rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&pmu_io_domains { - status = "okay"; - - pmu-supply = <&vcc_io>; - vop-supply = <&vcc_io>; -}; - -&saradc { - vref-supply = <&vcc_18>; - status = "okay"; -}; - -&tsadc { - rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ - rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_otg { - dr_mode = "host"; - status = "okay"; -}; - -&wdt { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/rockchip/rk3368.dtsi b/sys/gnu/dts/arm64/rockchip/rk3368.dtsi deleted file mode 100644 index a0df61c6192..00000000000 --- a/sys/gnu/dts/arm64/rockchip/rk3368.dtsi +++ /dev/null @@ -1,1226 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2015 Heiko Stuebner - */ - -#include -#include -#include -#include -#include -#include -#include - -/ { - compatible = "rockchip,rk3368"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - ethernet0 = &gmac; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - serial4 = &uart4; - spi0 = &spi0; - spi1 = &spi1; - spi2 = &spi2; - }; - - cpus { - #address-cells = <0x2>; - #size-cells = <0x0>; - - cpu-map { - cluster0 { - core0 { - cpu = <&cpu_b0>; - }; - core1 { - cpu = <&cpu_b1>; - }; - core2 { - cpu = <&cpu_b2>; - }; - core3 { - cpu = <&cpu_b3>; - }; - }; - - cluster1 { - core0 { - cpu = <&cpu_l0>; - }; - core1 { - cpu = <&cpu_l1>; - }; - core2 { - cpu = <&cpu_l2>; - }; - core3 { - cpu = <&cpu_l3>; - }; - }; - }; - - cpu_l0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x0>; - enable-method = "psci"; - #cooling-cells = <2>; /* min followed by max */ - }; - - cpu_l1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x1>; - enable-method = "psci"; - #cooling-cells = <2>; /* min followed by max */ - }; - - cpu_l2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x2>; - enable-method = "psci"; - #cooling-cells = <2>; /* min followed by max */ - }; - - cpu_l3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x3>; - enable-method = "psci"; - #cooling-cells = <2>; /* min followed by max */ - }; - - cpu_b0: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x100>; - enable-method = "psci"; - #cooling-cells = <2>; /* min followed by max */ - }; - - cpu_b1: cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x101>; - enable-method = "psci"; - #cooling-cells = <2>; /* min followed by max */ - }; - - cpu_b2: cpu@102 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x102>; - enable-method = "psci"; - #cooling-cells = <2>; /* min followed by max */ - }; - - cpu_b3: cpu@103 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x103>; - enable-method = "psci"; - #cooling-cells = <2>; /* min followed by max */ - }; - }; - - amba { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - dmac_peri: dma-controller@ff250000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x0 0xff250000 0x0 0x4000>; - interrupts = , - ; - #dma-cells = <1>; - arm,pl330-broken-no-flushp; - clocks = <&cru ACLK_DMAC_PERI>; - clock-names = "apb_pclk"; - }; - - dmac_bus: dma-controller@ff600000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x0 0xff600000 0x0 0x4000>; - interrupts = , - ; - #dma-cells = <1>; - arm,pl330-broken-no-flushp; - clocks = <&cru ACLK_DMAC_BUS>; - clock-names = "apb_pclk"; - }; - }; - - arm-pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = , - , - , - , - , - , - , - ; - interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>, - <&cpu_l3>, <&cpu_b0>, <&cpu_b1>, - <&cpu_b2>, <&cpu_b3>; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - xin24m: oscillator { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "xin24m"; - #clock-cells = <0>; - }; - - sdmmc: mmc@ff0c0000 { - compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x0 0xff0c0000 0x0 0x4000>; - max-frequency = <150000000>; - clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, - <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - interrupts = ; - resets = <&cru SRST_MMC0>; - reset-names = "reset"; - status = "disabled"; - }; - - sdio0: mmc@ff0d0000 { - compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x0 0xff0d0000 0x0 0x4000>; - max-frequency = <150000000>; - clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>, - <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - interrupts = ; - resets = <&cru SRST_SDIO0>; - reset-names = "reset"; - status = "disabled"; - }; - - emmc: mmc@ff0f0000 { - compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x0 0xff0f0000 0x0 0x4000>; - max-frequency = <150000000>; - clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, - <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - interrupts = ; - resets = <&cru SRST_EMMC>; - reset-names = "reset"; - status = "disabled"; - }; - - saradc: saradc@ff100000 { - compatible = "rockchip,saradc"; - reg = <0x0 0xff100000 0x0 0x100>; - interrupts = ; - #io-channel-cells = <1>; - clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; - clock-names = "saradc", "apb_pclk"; - resets = <&cru SRST_SARADC>; - reset-names = "saradc-apb"; - status = "disabled"; - }; - - spi0: spi@ff110000 { - compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi"; - reg = <0x0 0xff110000 0x0 0x1000>; - clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; - clock-names = "spiclk", "apb_pclk"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi1: spi@ff120000 { - compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi"; - reg = <0x0 0xff120000 0x0 0x1000>; - clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; - clock-names = "spiclk", "apb_pclk"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi2: spi@ff130000 { - compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi"; - reg = <0x0 0xff130000 0x0 0x1000>; - clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; - clock-names = "spiclk", "apb_pclk"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@ff140000 { - compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; - reg = <0x0 0xff140000 0x0 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C2>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_xfer>; - status = "disabled"; - }; - - i2c3: i2c@ff150000 { - compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; - reg = <0x0 0xff150000 0x0 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C3>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_xfer>; - status = "disabled"; - }; - - i2c4: i2c@ff160000 { - compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; - reg = <0x0 0xff160000 0x0 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C4>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_xfer>; - status = "disabled"; - }; - - i2c5: i2c@ff170000 { - compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; - reg = <0x0 0xff170000 0x0 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C5>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c5_xfer>; - status = "disabled"; - }; - - uart0: serial@ff180000 { - compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart"; - reg = <0x0 0xff180000 0x0 0x100>; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; - clock-names = "baudclk", "apb_pclk"; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uart1: serial@ff190000 { - compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart"; - reg = <0x0 0xff190000 0x0 0x100>; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; - clock-names = "baudclk", "apb_pclk"; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uart3: serial@ff1b0000 { - compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart"; - reg = <0x0 0xff1b0000 0x0 0x100>; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; - clock-names = "baudclk", "apb_pclk"; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uart4: serial@ff1c0000 { - compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart"; - reg = <0x0 0xff1c0000 0x0 0x100>; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; - clock-names = "baudclk", "apb_pclk"; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - thermal-zones { - cpu { - polling-delay-passive = <100>; /* milliseconds */ - polling-delay = <5000>; /* milliseconds */ - - thermal-sensors = <&tsadc 0>; - - trips { - cpu_alert0: cpu_alert0 { - temperature = <75000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - cpu_alert1: cpu_alert1 { - temperature = <80000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - cpu_crit: cpu_crit { - temperature = <95000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu_alert0>; - cooling-device = - <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu_alert1>; - cooling-device = - <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - gpu { - polling-delay-passive = <100>; /* milliseconds */ - polling-delay = <5000>; /* milliseconds */ - - thermal-sensors = <&tsadc 1>; - - trips { - gpu_alert0: gpu_alert0 { - temperature = <80000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - gpu_crit: gpu_crit { - temperature = <115000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&gpu_alert0>; - cooling-device = - <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - }; - - tsadc: tsadc@ff280000 { - compatible = "rockchip,rk3368-tsadc"; - reg = <0x0 0xff280000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; - clock-names = "tsadc", "apb_pclk"; - resets = <&cru SRST_TSADC>; - reset-names = "tsadc-apb"; - pinctrl-names = "init", "default", "sleep"; - pinctrl-0 = <&otp_gpio>; - pinctrl-1 = <&otp_out>; - pinctrl-2 = <&otp_gpio>; - #thermal-sensor-cells = <1>; - rockchip,hw-tshut-temp = <95000>; - status = "disabled"; - }; - - gmac: ethernet@ff290000 { - compatible = "rockchip,rk3368-gmac"; - reg = <0x0 0xff290000 0x0 0x10000>; - interrupts = ; - interrupt-names = "macirq"; - rockchip,grf = <&grf>; - clocks = <&cru SCLK_MAC>, - <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>, - <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>, - <&cru ACLK_GMAC>, <&cru PCLK_GMAC>; - clock-names = "stmmaceth", - "mac_clk_rx", "mac_clk_tx", - "clk_mac_ref", "clk_mac_refout", - "aclk_mac", "pclk_mac"; - status = "disabled"; - }; - - usb_host0_ehci: usb@ff500000 { - compatible = "generic-ehci"; - reg = <0x0 0xff500000 0x0 0x100>; - interrupts = ; - clocks = <&cru HCLK_HOST0>; - clock-names = "usbhost"; - status = "disabled"; - }; - - usb_otg: usb@ff580000 { - compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb", - "snps,dwc2"; - reg = <0x0 0xff580000 0x0 0x40000>; - interrupts = ; - clocks = <&cru HCLK_OTG0>; - clock-names = "otg"; - dr_mode = "otg"; - g-np-tx-fifo-size = <16>; - g-rx-fifo-size = <275>; - g-tx-fifo-size = <256 128 128 64 64 32>; - status = "disabled"; - }; - - i2c0: i2c@ff650000 { - compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; - reg = <0x0 0xff650000 0x0 0x1000>; - clocks = <&cru PCLK_I2C0>; - clock-names = "i2c"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_xfer>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c1: i2c@ff660000 { - compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; - reg = <0x0 0xff660000 0x0 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C1>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_xfer>; - status = "disabled"; - }; - - pwm0: pwm@ff680000 { - compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm"; - reg = <0x0 0xff680000 0x0 0x10>; - #pwm-cells = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pin>; - clocks = <&cru PCLK_PWM1>; - clock-names = "pwm"; - status = "disabled"; - }; - - pwm1: pwm@ff680010 { - compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm"; - reg = <0x0 0xff680010 0x0 0x10>; - #pwm-cells = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm1_pin>; - clocks = <&cru PCLK_PWM1>; - clock-names = "pwm"; - status = "disabled"; - }; - - pwm2: pwm@ff680020 { - compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm"; - reg = <0x0 0xff680020 0x0 0x10>; - #pwm-cells = <3>; - clocks = <&cru PCLK_PWM1>; - clock-names = "pwm"; - status = "disabled"; - }; - - pwm3: pwm@ff680030 { - compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm"; - reg = <0x0 0xff680030 0x0 0x10>; - #pwm-cells = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm3_pin>; - clocks = <&cru PCLK_PWM1>; - clock-names = "pwm"; - status = "disabled"; - }; - - uart2: serial@ff690000 { - compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart"; - reg = <0x0 0xff690000 0x0 0x100>; - clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; - clock-names = "baudclk", "apb_pclk"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&uart2_xfer>; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - mbox: mbox@ff6b0000 { - compatible = "rockchip,rk3368-mailbox"; - reg = <0x0 0xff6b0000 0x0 0x1000>; - interrupts = , - , - , - ; - clocks = <&cru PCLK_MAILBOX>; - clock-names = "pclk_mailbox"; - #mbox-cells = <1>; - status = "disabled"; - }; - - pmugrf: syscon@ff738000 { - compatible = "rockchip,rk3368-pmugrf", "syscon", "simple-mfd"; - reg = <0x0 0xff738000 0x0 0x1000>; - - pmu_io_domains: io-domains { - compatible = "rockchip,rk3368-pmu-io-voltage-domain"; - status = "disabled"; - }; - - reboot-mode { - compatible = "syscon-reboot-mode"; - offset = <0x200>; - mode-normal = ; - mode-recovery = ; - mode-bootloader = ; - mode-loader = ; - }; - }; - - cru: clock-controller@ff760000 { - compatible = "rockchip,rk3368-cru"; - reg = <0x0 0xff760000 0x0 0x1000>; - rockchip,grf = <&grf>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - grf: syscon@ff770000 { - compatible = "rockchip,rk3368-grf", "syscon", "simple-mfd"; - reg = <0x0 0xff770000 0x0 0x1000>; - - io_domains: io-domains { - compatible = "rockchip,rk3368-io-voltage-domain"; - status = "disabled"; - }; - }; - - wdt: watchdog@ff800000 { - compatible = "rockchip,rk3368-wdt", "snps,dw-wdt"; - reg = <0x0 0xff800000 0x0 0x100>; - clocks = <&cru PCLK_WDT>; - interrupts = ; - status = "disabled"; - }; - - timer@ff810000 { - compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer"; - reg = <0x0 0xff810000 0x0 0x20>; - interrupts = ; - }; - - spdif: spdif@ff880000 { - compatible = "rockchip,rk3368-spdif"; - reg = <0x0 0xff880000 0x0 0x1000>; - interrupts = ; - clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>; - clock-names = "mclk", "hclk"; - dmas = <&dmac_bus 3>; - dma-names = "tx"; - pinctrl-names = "default"; - pinctrl-0 = <&spdif_tx>; - status = "disabled"; - }; - - i2s_2ch: i2s-2ch@ff890000 { - compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s"; - reg = <0x0 0xff890000 0x0 0x1000>; - interrupts = ; - clock-names = "i2s_clk", "i2s_hclk"; - clocks = <&cru SCLK_I2S_2CH>, <&cru HCLK_I2S_2CH>; - dmas = <&dmac_bus 6>, <&dmac_bus 7>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - i2s_8ch: i2s-8ch@ff898000 { - compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s"; - reg = <0x0 0xff898000 0x0 0x1000>; - interrupts = ; - clock-names = "i2s_clk", "i2s_hclk"; - clocks = <&cru SCLK_I2S_8CH>, <&cru HCLK_I2S_8CH>; - dmas = <&dmac_bus 0>, <&dmac_bus 1>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&i2s_8ch_bus>; - status = "disabled"; - }; - - iep_mmu: iommu@ff900800 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff900800 0x0 0x100>; - interrupts = ; - interrupt-names = "iep_mmu"; - clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; - clock-names = "aclk", "iface"; - #iommu-cells = <0>; - status = "disabled"; - }; - - isp_mmu: iommu@ff914000 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff914000 0x0 0x100>, - <0x0 0xff915000 0x0 0x100>; - interrupts = ; - interrupt-names = "isp_mmu"; - clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>; - clock-names = "aclk", "iface"; - #iommu-cells = <0>; - rockchip,disable-mmu-reset; - status = "disabled"; - }; - - vop_mmu: iommu@ff930300 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff930300 0x0 0x100>; - interrupts = ; - interrupt-names = "vop_mmu"; - clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; - clock-names = "aclk", "iface"; - #iommu-cells = <0>; - status = "disabled"; - }; - - hevc_mmu: iommu@ff9a0440 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff9a0440 0x0 0x40>, - <0x0 0xff9a0480 0x0 0x40>; - interrupts = ; - interrupt-names = "hevc_mmu"; - clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>; - clock-names = "aclk", "iface"; - #iommu-cells = <0>; - status = "disabled"; - }; - - vpu_mmu: iommu@ff9a0800 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff9a0800 0x0 0x100>; - interrupts = , - ; - interrupt-names = "vepu_mmu", "vdpu_mmu"; - clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>; - clock-names = "aclk", "iface"; - #iommu-cells = <0>; - status = "disabled"; - }; - - efuse256: efuse@ffb00000 { - compatible = "rockchip,rk3368-efuse"; - reg = <0x0 0xffb00000 0x0 0x20>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&cru PCLK_EFUSE256>; - clock-names = "pclk_efuse"; - - cpu_leakage: cpu-leakage@17 { - reg = <0x17 0x1>; - }; - temp_adjust: temp-adjust@1f { - reg = <0x1f 0x1>; - }; - }; - - gic: interrupt-controller@ffb71000 { - compatible = "arm,gic-400"; - interrupt-controller; - #interrupt-cells = <3>; - #address-cells = <0>; - - reg = <0x0 0xffb71000 0x0 0x1000>, - <0x0 0xffb72000 0x0 0x2000>, - <0x0 0xffb74000 0x0 0x2000>, - <0x0 0xffb76000 0x0 0x2000>; - interrupts = ; - }; - - pinctrl: pinctrl { - compatible = "rockchip,rk3368-pinctrl"; - rockchip,grf = <&grf>; - rockchip,pmu = <&pmugrf>; - #address-cells = <0x2>; - #size-cells = <0x2>; - ranges; - - gpio0: gpio0@ff750000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff750000 0x0 0x100>; - clocks = <&cru PCLK_GPIO0>; - interrupts = ; - - gpio-controller; - #gpio-cells = <0x2>; - - interrupt-controller; - #interrupt-cells = <0x2>; - }; - - gpio1: gpio1@ff780000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff780000 0x0 0x100>; - clocks = <&cru PCLK_GPIO1>; - interrupts = ; - - gpio-controller; - #gpio-cells = <0x2>; - - interrupt-controller; - #interrupt-cells = <0x2>; - }; - - gpio2: gpio2@ff790000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff790000 0x0 0x100>; - clocks = <&cru PCLK_GPIO2>; - interrupts = ; - - gpio-controller; - #gpio-cells = <0x2>; - - interrupt-controller; - #interrupt-cells = <0x2>; - }; - - gpio3: gpio3@ff7a0000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff7a0000 0x0 0x100>; - clocks = <&cru PCLK_GPIO3>; - interrupts = ; - - gpio-controller; - #gpio-cells = <0x2>; - - interrupt-controller; - #interrupt-cells = <0x2>; - }; - - pcfg_pull_up: pcfg-pull-up { - bias-pull-up; - }; - - pcfg_pull_down: pcfg-pull-down { - bias-pull-down; - }; - - pcfg_pull_none: pcfg-pull-none { - bias-disable; - }; - - pcfg_pull_none_12ma: pcfg-pull-none-12ma { - bias-disable; - drive-strength = <12>; - }; - - emmc { - emmc_clk: emmc-clk { - rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>; - }; - - emmc_cmd: emmc-cmd { - rockchip,pins = <1 RK_PD2 2 &pcfg_pull_up>; - }; - - emmc_pwr: emmc-pwr { - rockchip,pins = <1 RK_PD3 2 &pcfg_pull_up>; - }; - - emmc_bus1: emmc-bus1 { - rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>; - }; - - emmc_bus4: emmc-bus4 { - rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>, - <1 RK_PC3 2 &pcfg_pull_up>, - <1 RK_PC4 2 &pcfg_pull_up>, - <1 RK_PC5 2 &pcfg_pull_up>; - }; - - emmc_bus8: emmc-bus8 { - rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>, - <1 RK_PC3 2 &pcfg_pull_up>, - <1 RK_PC4 2 &pcfg_pull_up>, - <1 RK_PC5 2 &pcfg_pull_up>, - <1 RK_PC6 2 &pcfg_pull_up>, - <1 RK_PC7 2 &pcfg_pull_up>, - <1 RK_PD0 2 &pcfg_pull_up>, - <1 RK_PD1 2 &pcfg_pull_up>; - }; - }; - - gmac { - rgmii_pins: rgmii-pins { - rockchip,pins = <3 RK_PC6 1 &pcfg_pull_none>, - <3 RK_PD0 1 &pcfg_pull_none>, - <3 RK_PC3 1 &pcfg_pull_none>, - <3 RK_PB0 1 &pcfg_pull_none_12ma>, - <3 RK_PB1 1 &pcfg_pull_none_12ma>, - <3 RK_PB2 1 &pcfg_pull_none_12ma>, - <3 RK_PB6 1 &pcfg_pull_none_12ma>, - <3 RK_PD4 1 &pcfg_pull_none_12ma>, - <3 RK_PB5 1 &pcfg_pull_none_12ma>, - <3 RK_PB7 1 &pcfg_pull_none>, - <3 RK_PC0 1 &pcfg_pull_none>, - <3 RK_PC1 1 &pcfg_pull_none>, - <3 RK_PC2 1 &pcfg_pull_none>, - <3 RK_PD1 1 &pcfg_pull_none>, - <3 RK_PC4 1 &pcfg_pull_none>; - }; - - rmii_pins: rmii-pins { - rockchip,pins = <3 RK_PC6 1 &pcfg_pull_none>, - <3 RK_PD0 1 &pcfg_pull_none>, - <3 RK_PC3 1 &pcfg_pull_none>, - <3 RK_PB0 1 &pcfg_pull_none_12ma>, - <3 RK_PB1 1 &pcfg_pull_none_12ma>, - <3 RK_PB5 1 &pcfg_pull_none_12ma>, - <3 RK_PB7 1 &pcfg_pull_none>, - <3 RK_PC0 1 &pcfg_pull_none>, - <3 RK_PC4 1 &pcfg_pull_none>, - <3 RK_PC5 1 &pcfg_pull_none>; - }; - }; - - i2c0 { - i2c0_xfer: i2c0-xfer { - rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>, - <0 RK_PA7 1 &pcfg_pull_none>; - }; - }; - - i2c1 { - i2c1_xfer: i2c1-xfer { - rockchip,pins = <2 RK_PC5 1 &pcfg_pull_none>, - <2 RK_PC6 1 &pcfg_pull_none>; - }; - }; - - i2c2 { - i2c2_xfer: i2c2-xfer { - rockchip,pins = <0 RK_PB1 2 &pcfg_pull_none>, - <3 RK_PD7 2 &pcfg_pull_none>; - }; - }; - - i2c3 { - i2c3_xfer: i2c3-xfer { - rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>, - <1 RK_PC1 1 &pcfg_pull_none>; - }; - }; - - i2c4 { - i2c4_xfer: i2c4-xfer { - rockchip,pins = <3 RK_PD0 2 &pcfg_pull_none>, - <3 RK_PD1 2 &pcfg_pull_none>; - }; - }; - - i2c5 { - i2c5_xfer: i2c5-xfer { - rockchip,pins = <3 RK_PD2 2 &pcfg_pull_none>, - <3 RK_PD3 2 &pcfg_pull_none>; - }; - }; - - i2s { - i2s_8ch_bus: i2s-8ch-bus { - rockchip,pins = <2 RK_PB4 1 &pcfg_pull_none>, - <2 RK_PB5 1 &pcfg_pull_none>, - <2 RK_PB6 1 &pcfg_pull_none>, - <2 RK_PB7 1 &pcfg_pull_none>, - <2 RK_PC0 1 &pcfg_pull_none>, - <2 RK_PC1 1 &pcfg_pull_none>, - <2 RK_PC2 1 &pcfg_pull_none>, - <2 RK_PC3 1 &pcfg_pull_none>, - <2 RK_PC4 1 &pcfg_pull_none>; - }; - }; - - pwm0 { - pwm0_pin: pwm0-pin { - rockchip,pins = <3 RK_PB0 2 &pcfg_pull_none>; - }; - }; - - pwm1 { - pwm1_pin: pwm1-pin { - rockchip,pins = <0 RK_PB0 2 &pcfg_pull_none>; - }; - }; - - pwm3 { - pwm3_pin: pwm3-pin { - rockchip,pins = <3 RK_PD5 3 &pcfg_pull_none>; - }; - }; - - sdio0 { - sdio0_bus1: sdio0-bus1 { - rockchip,pins = <2 RK_PD4 1 &pcfg_pull_up>; - }; - - sdio0_bus4: sdio0-bus4 { - rockchip,pins = <2 RK_PD4 1 &pcfg_pull_up>, - <2 RK_PD5 1 &pcfg_pull_up>, - <2 RK_PD6 1 &pcfg_pull_up>, - <2 RK_PD7 1 &pcfg_pull_up>; - }; - - sdio0_cmd: sdio0-cmd { - rockchip,pins = <3 RK_PA0 1 &pcfg_pull_up>; - }; - - sdio0_clk: sdio0-clk { - rockchip,pins = <3 RK_PA1 1 &pcfg_pull_none>; - }; - - sdio0_cd: sdio0-cd { - rockchip,pins = <3 RK_PA2 1 &pcfg_pull_up>; - }; - - sdio0_wp: sdio0-wp { - rockchip,pins = <3 RK_PA3 1 &pcfg_pull_up>; - }; - - sdio0_pwr: sdio0-pwr { - rockchip,pins = <3 RK_PA4 1 &pcfg_pull_up>; - }; - - sdio0_bkpwr: sdio0-bkpwr { - rockchip,pins = <3 RK_PA5 1 &pcfg_pull_up>; - }; - - sdio0_int: sdio0-int { - rockchip,pins = <3 RK_PA6 1 &pcfg_pull_up>; - }; - }; - - sdmmc { - sdmmc_clk: sdmmc-clk { - rockchip,pins = <2 RK_PB1 1 &pcfg_pull_none>; - }; - - sdmmc_cmd: sdmmc-cmd { - rockchip,pins = <2 RK_PB2 1 &pcfg_pull_up>; - }; - - sdmmc_cd: sdmmc-cd { - rockchip,pins = <2 RK_PB3 1 &pcfg_pull_up>; - }; - - sdmmc_bus1: sdmmc-bus1 { - rockchip,pins = <2 RK_PA5 1 &pcfg_pull_up>; - }; - - sdmmc_bus4: sdmmc-bus4 { - rockchip,pins = <2 RK_PA5 1 &pcfg_pull_up>, - <2 RK_PA6 1 &pcfg_pull_up>, - <2 RK_PA7 1 &pcfg_pull_up>, - <2 RK_PB0 1 &pcfg_pull_up>; - }; - }; - - spdif { - spdif_tx: spdif-tx { - rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>; - }; - }; - - spi0 { - spi0_clk: spi0-clk { - rockchip,pins = <1 RK_PD5 2 &pcfg_pull_up>; - }; - spi0_cs0: spi0-cs0 { - rockchip,pins = <1 RK_PD0 3 &pcfg_pull_up>; - }; - spi0_cs1: spi0-cs1 { - rockchip,pins = <1 RK_PD1 3 &pcfg_pull_up>; - }; - spi0_tx: spi0-tx { - rockchip,pins = <1 RK_PC7 3 &pcfg_pull_up>; - }; - spi0_rx: spi0-rx { - rockchip,pins = <1 RK_PC6 3 &pcfg_pull_up>; - }; - }; - - spi1 { - spi1_clk: spi1-clk { - rockchip,pins = <1 RK_PB6 2 &pcfg_pull_up>; - }; - spi1_cs0: spi1-cs0 { - rockchip,pins = <1 RK_PB7 2 &pcfg_pull_up>; - }; - spi1_cs1: spi1-cs1 { - rockchip,pins = <3 RK_PD4 2 &pcfg_pull_up>; - }; - spi1_rx: spi1-rx { - rockchip,pins = <1 RK_PC0 2 &pcfg_pull_up>; - }; - spi1_tx: spi1-tx { - rockchip,pins = <1 RK_PC1 2 &pcfg_pull_up>; - }; - }; - - spi2 { - spi2_clk: spi2-clk { - rockchip,pins = <0 RK_PB4 2 &pcfg_pull_up>; - }; - spi2_cs0: spi2-cs0 { - rockchip,pins = <0 RK_PB5 2 &pcfg_pull_up>; - }; - spi2_rx: spi2-rx { - rockchip,pins = <0 RK_PB2 2 &pcfg_pull_up>; - }; - spi2_tx: spi2-tx { - rockchip,pins = <0 RK_PB3 2 &pcfg_pull_up>; - }; - }; - - tsadc { - otp_gpio: otp-gpio { - rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - otp_out: otp-out { - rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>; - }; - }; - - uart0 { - uart0_xfer: uart0-xfer { - rockchip,pins = <2 RK_PD0 1 &pcfg_pull_up>, - <2 RK_PD1 1 &pcfg_pull_none>; - }; - - uart0_cts: uart0-cts { - rockchip,pins = <2 RK_PD2 1 &pcfg_pull_none>; - }; - - uart0_rts: uart0-rts { - rockchip,pins = <2 RK_PD3 1 &pcfg_pull_none>; - }; - }; - - uart1 { - uart1_xfer: uart1-xfer { - rockchip,pins = <0 RK_PC4 3 &pcfg_pull_up>, - <0 RK_PC5 3 &pcfg_pull_none>; - }; - - uart1_cts: uart1-cts { - rockchip,pins = <0 RK_PC6 3 &pcfg_pull_none>; - }; - - uart1_rts: uart1-rts { - rockchip,pins = <0 RK_PC7 3 &pcfg_pull_none>; - }; - }; - - uart2 { - uart2_xfer: uart2-xfer { - rockchip,pins = <2 RK_PA6 2 &pcfg_pull_up>, - <2 RK_PA5 2 &pcfg_pull_none>; - }; - /* no rts / cts for uart2 */ - }; - - uart3 { - uart3_xfer: uart3-xfer { - rockchip,pins = <3 RK_PD5 2 &pcfg_pull_up>, - <3 RK_PD6 3 &pcfg_pull_none>; - }; - - uart3_cts: uart3-cts { - rockchip,pins = <3 RK_PC0 2 &pcfg_pull_none>; - }; - - uart3_rts: uart3-rts { - rockchip,pins = <3 RK_PC1 2 &pcfg_pull_none>; - }; - }; - - uart4 { - uart4_xfer: uart4-xfer { - rockchip,pins = <0 RK_PD3 3 &pcfg_pull_up>, - <0 RK_PD2 3 &pcfg_pull_none>; - }; - - uart4_cts: uart4-cts { - rockchip,pins = <0 RK_PD0 3 &pcfg_pull_none>; - }; - - uart4_rts: uart4-rts { - rockchip,pins = <0 RK_PD1 3 &pcfg_pull_none>; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/rockchip/rk3399-evb.dts b/sys/gnu/dts/arm64/rockchip/rk3399-evb.dts deleted file mode 100644 index 77008dca45b..00000000000 --- a/sys/gnu/dts/arm64/rockchip/rk3399-evb.dts +++ /dev/null @@ -1,226 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd - */ - -/dts-v1/; -#include -#include "rk3399.dtsi" - -/ { - model = "Rockchip RK3399 Evaluation Board"; - compatible = "rockchip,rk3399-evb", "rockchip,rk3399", - "google,rk3399evb-rev2"; - - backlight: backlight { - compatible = "pwm-backlight"; - brightness-levels = < - 0 1 2 3 4 5 6 7 - 8 9 10 11 12 13 14 15 - 16 17 18 19 20 21 22 23 - 24 25 26 27 28 29 30 31 - 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 - 48 49 50 51 52 53 54 55 - 56 57 58 59 60 61 62 63 - 64 65 66 67 68 69 70 71 - 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 - 88 89 90 91 92 93 94 95 - 96 97 98 99 100 101 102 103 - 104 105 106 107 108 109 110 111 - 112 113 114 115 116 117 118 119 - 120 121 122 123 124 125 126 127 - 128 129 130 131 132 133 134 135 - 136 137 138 139 140 141 142 143 - 144 145 146 147 148 149 150 151 - 152 153 154 155 156 157 158 159 - 160 161 162 163 164 165 166 167 - 168 169 170 171 172 173 174 175 - 176 177 178 179 180 181 182 183 - 184 185 186 187 188 189 190 191 - 192 193 194 195 196 197 198 199 - 200 201 202 203 204 205 206 207 - 208 209 210 211 212 213 214 215 - 216 217 218 219 220 221 222 223 - 224 225 226 227 228 229 230 231 - 232 233 234 235 236 237 238 239 - 240 241 242 243 244 245 246 247 - 248 249 250 251 252 253 254 255>; - default-brightness-level = <200>; - enable-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>; - pwms = <&pwm0 0 25000 0>; - }; - - clkin_gmac: external-gmac-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "clkin_gmac"; - #clock-cells = <0>; - }; - - vdd_center: vdd-center { - compatible = "pwm-regulator"; - pwms = <&pwm3 0 25000 0>; - regulator-name = "vdd_center"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-boot-on; - status = "okay"; - }; - - vcc3v3_sys: vcc3v3-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vcc5v0_sys: vcc5v0-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - vcc5v0_host: vcc5v0-host-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_host_en>; - regulator-name = "vcc5v0_host"; - vin-supply = <&vcc5v0_sys>; - }; - - vcc_phy: vcc-phy-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_phy"; - regulator-always-on; - regulator-boot-on; - }; - - vcc_phy: vcc-phy-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_phy"; - regulator-always-on; - regulator-boot-on; - }; - -}; - -&emmc_phy { - status = "okay"; -}; - -&gmac { - assigned-clocks = <&cru SCLK_RMII_SRC>; - assigned-clock-parents = <&clkin_gmac>; - clock_in_out = "input"; - phy-supply = <&vcc_phy>; - phy-mode = "rgmii"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 50000>; - tx_delay = <0x28>; - rx_delay = <0x11>; - status = "okay"; -}; - -&pwm0 { - status = "okay"; -}; - -&pwm2 { - status = "okay"; -}; - -&pwm3 { - status = "okay"; -}; - -&sdhci { - bus-width = <8>; - mmc-hs400-1_8v; - mmc-hs400-enhanced-strobe; - non-removable; - status = "okay"; -}; - -&pcie_phy { - status = "disabled"; -}; - -&pcie0 { - ep-gpios = <&gpio3 RK_PB5 GPIO_ACTIVE_HIGH>; - num-lanes = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie_clkreqn_cpm>; - status = "disabled"; -}; - -&u2phy0 { - status = "okay"; -}; - -&u2phy0_host { - phy-supply = <&vcc5v0_host>; - status = "okay"; -}; - -&u2phy1 { - status = "okay"; -}; - -&u2phy1_host { - phy-supply = <&vcc5v0_host>; - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - -&pinctrl { - pmic { - pmic_int_l: pmic-int-l { - rockchip,pins = - <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - pmic_dvs2: pmic-dvs2 { - rockchip,pins = - <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; - - usb2 { - vcc5v0_host_en: vcc5v0-host-en { - rockchip,pins = - <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/rockchip/rk3399-ficus.dts b/sys/gnu/dts/arm64/rockchip/rk3399-ficus.dts deleted file mode 100644 index ebe2ee77ba1..00000000000 --- a/sys/gnu/dts/arm64/rockchip/rk3399-ficus.dts +++ /dev/null @@ -1,169 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2018 Collabora Ltd. - * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd. - * - * Schematics available at https://dl.vamrs.com/products/ficus/docs/hw - */ - -/dts-v1/; -#include "rk3399-rock960.dtsi" - -/ { - model = "96boards RK3399 Ficus"; - compatible = "vamrs,ficus", "rockchip,rk3399"; - - chosen { - stdout-path = "serial2:1500000n8"; - }; - - clkin_gmac: external-gmac-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "clkin_gmac"; - #clock-cells = <0>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&user_led1>, <&user_led2>, <&user_led3>, - <&user_led4>, <&wlan_led>, <&bt_led>; - - user_led1 { - label = "red:user1"; - gpios = <&gpio4 25 0>; - linux,default-trigger = "heartbeat"; - }; - - user_led2 { - label = "red:user2"; - gpios = <&gpio4 26 0>; - linux,default-trigger = "mmc0"; - }; - - user_led3 { - label = "red:user3"; - gpios = <&gpio4 30 0>; - linux,default-trigger = "mmc1"; - }; - - user_led4 { - label = "red:user4"; - gpios = <&gpio1 0 0>; - panic-indicator; - linux,default-trigger = "none"; - }; - - wlan_active_led { - label = "red:wlan"; - gpios = <&gpio1 1 0>; - linux,default-trigger = "phy0tx"; - default-state = "off"; - }; - - bt_active_led { - label = "red:bt"; - gpios = <&gpio1 4 0>; - linux,default-trigger = "hci0-power"; - default-state = "off"; - }; - }; -}; - -&gmac { - assigned-clocks = <&cru SCLK_RMII_SRC>; - assigned-clock-parents = <&clkin_gmac>; - clock_in_out = "input"; - phy-supply = <&vcc3v3_sys>; - phy-mode = "rgmii"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 50000>; - tx_delay = <0x28>; - rx_delay = <0x11>; - status = "okay"; -}; - -&pcie0 { - ep-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_HIGH>; -}; - -&pinctrl { - gmac { - rgmii_sleep_pins: rgmii-sleep-pins { - rockchip,pins = - <3 RK_PB7 RK_FUNC_GPIO &pcfg_output_low>; - }; - }; - - pcie { - pcie_drv: pcie-drv { - rockchip,pins = - <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb2 { - host_vbus_drv: host-vbus-drv { - rockchip,pins = - <4 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - leds { - user_led1: user_led1 { - rockchip,pins = - <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - user_led2: user_led2 { - rockchip,pins = - <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - user_led3: user_led3 { - rockchip,pins = - <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - user_led4: user_led4 { - rockchip,pins = - <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - wlan_led: wlan_led { - rockchip,pins = - <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_led: bt_led { - rockchip,pins = - <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&spi1 { - /* On both Low speed and High speed expansion */ - cs-gpios = <0>, <&gpio4 RK_PA6 0>, <&gpio4 RK_PA7 0>; - status = "okay"; -}; - -&usbdrd_dwc3_0 { - dr_mode = "host"; -}; - -&usbdrd_dwc3_1 { - dr_mode = "host"; -}; - -&vcc3v3_pcie { - gpio = <&gpio1 24 GPIO_ACTIVE_HIGH>; -}; - -&vcc5v0_host { - gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; -}; diff --git a/sys/gnu/dts/arm64/rockchip/rk3399-firefly.dts b/sys/gnu/dts/arm64/rockchip/rk3399-firefly.dts deleted file mode 100644 index d63faf38cc8..00000000000 --- a/sys/gnu/dts/arm64/rockchip/rk3399-firefly.dts +++ /dev/null @@ -1,807 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd. - */ - -/dts-v1/; -#include -#include -#include "rk3399.dtsi" -#include "rk3399-opp.dtsi" - -/ { - model = "Firefly-RK3399 Board"; - compatible = "firefly,firefly-rk3399", "rockchip,rk3399"; - - chosen { - stdout-path = "serial2:1500000n8"; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - enable-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>; - pwms = <&pwm0 0 25000 0>; - brightness-levels = < - 0 1 2 3 4 5 6 7 - 8 9 10 11 12 13 14 15 - 16 17 18 19 20 21 22 23 - 24 25 26 27 28 29 30 31 - 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 - 48 49 50 51 52 53 54 55 - 56 57 58 59 60 61 62 63 - 64 65 66 67 68 69 70 71 - 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 - 88 89 90 91 92 93 94 95 - 96 97 98 99 100 101 102 103 - 104 105 106 107 108 109 110 111 - 112 113 114 115 116 117 118 119 - 120 121 122 123 124 125 126 127 - 128 129 130 131 132 133 134 135 - 136 137 138 139 140 141 142 143 - 144 145 146 147 148 149 150 151 - 152 153 154 155 156 157 158 159 - 160 161 162 163 164 165 166 167 - 168 169 170 171 172 173 174 175 - 176 177 178 179 180 181 182 183 - 184 185 186 187 188 189 190 191 - 192 193 194 195 196 197 198 199 - 200 201 202 203 204 205 206 207 - 208 209 210 211 212 213 214 215 - 216 217 218 219 220 221 222 223 - 224 225 226 227 228 229 230 231 - 232 233 234 235 236 237 238 239 - 240 241 242 243 244 245 246 247 - 248 249 250 251 252 253 254 255>; - default-brightness-level = <200>; - }; - - clkin_gmac: external-gmac-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "clkin_gmac"; - #clock-cells = <0>; - }; - - dc_12v: dc-12v { - compatible = "regulator-fixed"; - regulator-name = "dc_12v"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - pinctrl-names = "default"; - pinctrl-0 = <&pwrbtn>; - - power { - debounce-interval = <100>; - gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; - label = "GPIO Key Power"; - linux,code = ; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&work_led_gpio>, <&diy_led_gpio>; - - work-led { - label = "work"; - default-state = "on"; - gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; - }; - - diy-led { - label = "diy"; - default-state = "off"; - gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; - }; - }; - - rt5640-sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "rockchip,rt5640-codec"; - simple-audio-card,format = "i2s"; - simple-audio-card,mclk-fs = <256>; - simple-audio-card,widgets = - "Microphone", "Mic Jack", - "Headphone", "Headphone Jack"; - simple-audio-card,routing = - "Mic Jack", "MICBIAS1", - "IN1P", "Mic Jack", - "Headphone Jack", "HPOL", - "Headphone Jack", "HPOR"; - - simple-audio-card,cpu { - sound-dai = <&i2s1>; - }; - - simple-audio-card,codec { - sound-dai = <&rt5640>; - }; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&rk808 1>; - clock-names = "ext_clock"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_enable_h>; - - /* - * On the module itself this is one of these (depending - * on the actual card populated): - * - SDIO_RESET_L_WL_REG_ON - * - PDN (power down when low) - */ - reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; - }; - - /* switched by pmic_sleep */ - vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 { - compatible = "regulator-fixed"; - regulator-name = "vcc1v8_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_1v8>; - }; - - vcc3v3_pcie: vcc3v3-pcie-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie_pwr_en>; - regulator-name = "vcc3v3_pcie"; - regulator-always-on; - regulator-boot-on; - vin-supply = <&dc_12v>; - }; - - vcc3v3_sys: vcc3v3-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_sys>; - }; - - /* Actually 3 regulators (host0, 1, 2) controlled by the same gpio */ - vcc5v0_host: vcc5v0-host-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_host_en>; - regulator-name = "vcc5v0_host"; - regulator-always-on; - vin-supply = <&vcc_sys>; - }; - - vcc_sys: vcc-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&dc_12v>; - }; - - vdd_log: vdd-log { - compatible = "pwm-regulator"; - pwms = <&pwm2 0 25000 1>; - regulator-name = "vdd_log"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <430000>; - regulator-max-microvolt = <1400000>; - vin-supply = <&vcc_sys>; - }; -}; - -&cpu_l0 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l1 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l2 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l3 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_b0 { - cpu-supply = <&vdd_cpu_b>; -}; - -&cpu_b1 { - cpu-supply = <&vdd_cpu_b>; -}; - -&emmc_phy { - status = "okay"; -}; - -&gmac { - assigned-clocks = <&cru SCLK_RMII_SRC>; - assigned-clock-parents = <&clkin_gmac>; - clock_in_out = "input"; - phy-supply = <&vcc_lan>; - phy-mode = "rgmii"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 50000>; - tx_delay = <0x28>; - rx_delay = <0x11>; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c3>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_cec>; - status = "okay"; -}; - -&i2c0 { - clock-frequency = <400000>; - i2c-scl-rising-time-ns = <168>; - i2c-scl-falling-time-ns = <4>; - status = "okay"; - - rk808: pmic@1b { - compatible = "rockchip,rk808"; - reg = <0x1b>; - interrupt-parent = <&gpio1>; - interrupts = <21 IRQ_TYPE_LEVEL_LOW>; - #clock-cells = <1>; - clock-output-names = "xin32k", "rk808-clkout2"; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l>; - rockchip,system-power-controller; - wakeup-source; - - vcc1-supply = <&vcc_sys>; - vcc2-supply = <&vcc_sys>; - vcc3-supply = <&vcc_sys>; - vcc4-supply = <&vcc_sys>; - vcc6-supply = <&vcc_sys>; - vcc7-supply = <&vcc_sys>; - vcc8-supply = <&vcc3v3_sys>; - vcc9-supply = <&vcc_sys>; - vcc10-supply = <&vcc_sys>; - vcc11-supply = <&vcc_sys>; - vcc12-supply = <&vcc3v3_sys>; - vddio-supply = <&vcc1v8_pmu>; - - regulators { - vdd_center: DCDC_REG1 { - regulator-name = "vdd_center"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_l: DCDC_REG2 { - regulator-name = "vdd_cpu_l"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_1v8: DCDC_REG4 { - regulator-name = "vcc_1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc1v8_dvp: LDO_REG1 { - regulator-name = "vcc1v8_dvp"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc2v8_dvp: LDO_REG2 { - regulator-name = "vcc2v8_dvp"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc1v8_pmu: LDO_REG3 { - regulator-name = "vcc1v8_pmu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc_sdio: LDO_REG4 { - regulator-name = "vcc_sdio"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3000000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3000000>; - }; - }; - - vcca3v0_codec: LDO_REG5 { - regulator-name = "vcca3v0_codec"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v5: LDO_REG6 { - regulator-name = "vcc_1v5"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1500000>; - }; - }; - - vcca1v8_codec: LDO_REG7 { - regulator-name = "vcca1v8_codec"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_3v0: LDO_REG8 { - regulator-name = "vcc_3v0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3000000>; - }; - }; - - vcc3v3_s3: vcc_lan: SWITCH_REG1 { - regulator-name = "vcc3v3_s3"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v3_s0: SWITCH_REG2 { - regulator-name = "vcc3v3_s0"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; - - vdd_cpu_b: regulator@40 { - compatible = "silergy,syr827"; - reg = <0x40>; - fcs,suspend-voltage-selector = <0>; - regulator-name = "vdd_cpu_b"; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1500000>; - regulator-ramp-delay = <1000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_gpu: regulator@41 { - compatible = "silergy,syr828"; - reg = <0x41>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_gpu"; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1500000>; - regulator-ramp-delay = <1000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&i2c1 { - i2c-scl-rising-time-ns = <300>; - i2c-scl-falling-time-ns = <15>; - status = "okay"; - - rt5640: rt5640@1c { - compatible = "realtek,rt5640"; - reg = <0x1c>; - clocks = <&cru SCLK_I2S_8CH_OUT>; - clock-names = "mclk"; - realtek,in1-differential; - #sound-dai-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&rt5640_hpcon>; - }; -}; - -&i2c3 { - i2c-scl-rising-time-ns = <450>; - i2c-scl-falling-time-ns = <15>; - status = "okay"; -}; - -&i2c4 { - i2c-scl-rising-time-ns = <600>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; - - accelerometer@68 { - compatible = "invensense,mpu6500"; - reg = <0x68>; - interrupt-parent = <&gpio1>; - interrupts = ; - }; -}; - -&i2s0 { - rockchip,playback-channels = <8>; - rockchip,capture-channels = <8>; - status = "okay"; -}; - -&i2s1 { - rockchip,playback-channels = <2>; - rockchip,capture-channels = <2>; - status = "okay"; -}; - -&i2s2 { - status = "okay"; -}; - -&io_domains { - status = "okay"; - - bt656-supply = <&vcc1v8_dvp>; - audio-supply = <&vcca1v8_codec>; - sdmmc-supply = <&vcc_sdio>; - gpio1830-supply = <&vcc_3v0>; -}; - -&pcie_phy { - status = "okay"; -}; - -&pcie0 { - ep-gpios = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>; - num-lanes = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie_clkreqn_cpm>; - status = "okay"; -}; - -&pmu_io_domains { - pmu1830-supply = <&vcc_3v0>; - status = "okay"; -}; - -&pinctrl { - buttons { - pwrbtn: pwrbtn { - rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - lcd-panel { - lcd_panel_reset: lcd-panel-reset { - rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - pcie { - pcie_pwr_en: pcie-pwr-en { - rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - pcie_3g_drv: pcie-3g-drv { - rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - pmic { - vsel1_gpio: vsel1-gpio { - rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - vsel2_gpio: vsel2-gpio { - rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; - - sdio-pwrseq { - wifi_enable_h: wifi-enable-h { - rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - rt5640 { - rt5640_hpcon: rt5640-hpcon { - rockchip,pins = <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - pmic_int_l: pmic-int-l { - rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - usb2 { - vcc5v0_host_en: vcc5v0-host-en { - rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - wifi { - wifi_host_wake_l: wifi-host-wake-l { - rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - leds { - work_led_gpio: work_led-gpio { - rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - diy_led_gpio: diy_led-gpio { - rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&pwm0 { - status = "okay"; -}; - -&pwm2 { - status = "okay"; -}; - -&saradc { - vref-supply = <&vcca1v8_s3>; - status = "okay"; -}; - -&sdio0 { - /* WiFi & BT combo module Ampak AP6356S */ - bus-width = <4>; - cap-sdio-irq; - cap-sd-highspeed; - keep-power-in-suspend; - mmc-pwrseq = <&sdio_pwrseq>; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; - sd-uhs-sdr104; - - /* Power supply */ - vqmmc-supply = &vcc1v8_s3; /* IO line */ - vmmc-supply = &vcc_sdio; /* card's power */ - - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - interrupt-parent = <&gpio0>; - interrupts = ; - interrupt-names = "host-wake"; - brcm,drive-strength = <5>; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_host_wake_l>; - }; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - cd-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>; - disable-wp; - max-frequency = <150000000>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; - status = "okay"; -}; - -&sdhci { - bus-width = <8>; - mmc-hs400-1_8v; - mmc-hs400-enhanced-strobe; - non-removable; - status = "okay"; -}; - -&tcphy0 { - status = "okay"; -}; - -&tcphy1 { - status = "okay"; -}; - -&tsadc { - /* tshut mode 0:CRU 1:GPIO */ - rockchip,hw-tshut-mode = <1>; - /* tshut polarity 0:LOW 1:HIGH */ - rockchip,hw-tshut-polarity = <1>; - status = "okay"; -}; - -&u2phy0 { - status = "okay"; - - u2phy0_otg: otg-port { - status = "okay"; - }; - - u2phy0_host: host-port { - phy-supply = <&vcc5v0_host>; - status = "okay"; - }; -}; - -&u2phy1 { - status = "okay"; - - u2phy1_otg: otg-port { - status = "okay"; - }; - - u2phy1_host: host-port { - phy-supply = <&vcc5v0_host>; - status = "okay"; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_cts>; - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - -&usbdrd3_0 { - status = "okay"; -}; - -&usbdrd_dwc3_0 { - status = "okay"; - dr_mode = "otg"; -}; - -&usbdrd3_1 { - status = "okay"; -}; - -&usbdrd_dwc3_1 { - status = "okay"; - dr_mode = "host"; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&vopl { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/rockchip/rk3399-gru-bob.dts b/sys/gnu/dts/arm64/rockchip/rk3399-gru-bob.dts deleted file mode 100644 index e6c1c94c8d6..00000000000 --- a/sys/gnu/dts/arm64/rockchip/rk3399-gru-bob.dts +++ /dev/null @@ -1,89 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Gru-Bob Rev 4+ board device tree source - * - * Copyright 2018 Google, Inc - */ - -/dts-v1/; -#include "rk3399-gru-chromebook.dtsi" - -/ { - model = "Google Bob"; - compatible = "google,bob-rev13", "google,bob-rev12", - "google,bob-rev11", "google,bob-rev10", - "google,bob-rev9", "google,bob-rev8", - "google,bob-rev7", "google,bob-rev6", - "google,bob-rev5", "google,bob-rev4", - "google,bob", "google,gru", "rockchip,rk3399"; - - edp_panel: edp-panel { - compatible = "boe,nv101wxmn51"; - backlight = <&backlight>; - power-supply = <&pp3300_disp>; - - port { - panel_in_edp: endpoint { - remote-endpoint = <&edp_out_panel>; - }; - }; - }; -}; - -&ap_i2c_ts { - touchscreen: touchscreen@10 { - compatible = "elan,ekth3500"; - reg = <0x10>; - interrupt-parent = <&gpio3>; - interrupts = <13 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&touch_int_l &touch_reset_l>; - reset-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; - }; -}; - -&ap_i2c_tp { - trackpad: trackpad@15 { - compatible = "elan,ekth3000"; - reg = <0x15>; - interrupt-parent = <&gpio1>; - interrupts = <4 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&trackpad_int_l>; - wakeup-source; - }; -}; - -&backlight { - pwms = <&cros_ec_pwm 0>; -}; - -&cpu_alert0 { - temperature = <65000>; -}; - -&cpu_alert1 { - temperature = <70000>; -}; - -&spi0 { - status = "okay"; - - cr50@0 { - compatible = "google,cr50"; - reg = <0>; - interrupt-parent = <&gpio0>; - interrupts = <5 IRQ_TYPE_EDGE_RISING>; - pinctrl-names = "default"; - pinctrl-0 = <&h1_int_od_l>; - spi-max-frequency = <800000>; - }; -}; - -&pinctrl { - tpm { - h1_int_od_l: h1-int-od-l { - rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/rockchip/rk3399-gru-chromebook.dtsi b/sys/gnu/dts/arm64/rockchip/rk3399-gru-chromebook.dtsi deleted file mode 100644 index 7cd6d470c1c..00000000000 --- a/sys/gnu/dts/arm64/rockchip/rk3399-gru-chromebook.dtsi +++ /dev/null @@ -1,402 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Gru-Chromebook shared properties - * - * Copyright 2018 Google, Inc - */ - -#include "rk3399-gru.dtsi" - -/ { - pp900_ap: pp900-ap { - compatible = "regulator-fixed"; - regulator-name = "pp900_ap"; - - /* EC turns on w/ pp900_ap_en; always on for AP */ - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - - vin-supply = <&ppvar_sys>; - }; - - /* EC turns on w/ pp900_usb_en */ - pp900_usb: pp900-ap { - }; - - /* EC turns on w/ pp900_pcie_en */ - pp900_pcie: pp900-ap { - }; - - pp3000: pp3000 { - compatible = "regulator-fixed"; - regulator-name = "pp3000"; - pinctrl-names = "default"; - pinctrl-0 = <&pp3000_en>; - - enable-active-high; - gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>; - - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - - vin-supply = <&ppvar_sys>; - }; - - ppvar_centerlogic_pwm: ppvar-centerlogic-pwm { - compatible = "pwm-regulator"; - regulator-name = "ppvar_centerlogic_pwm"; - - pwms = <&pwm3 0 3337 0>; - pwm-supply = <&ppvar_sys>; - pwm-dutycycle-range = <100 0>; - pwm-dutycycle-unit = <100>; - - /* EC turns on w/ ppvar_centerlogic_en; always on for AP */ - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <799434>; - regulator-max-microvolt = <1049925>; - }; - - ppvar_centerlogic: ppvar-centerlogic { - compatible = "vctrl-regulator"; - regulator-name = "ppvar_centerlogic"; - - regulator-min-microvolt = <799434>; - regulator-max-microvolt = <1049925>; - - ctrl-supply = <&ppvar_centerlogic_pwm>; - ctrl-voltage-range = <799434 1049925>; - - regulator-settling-time-up-us = <378>; - min-slew-down-rate = <225>; - ovp-threshold-percent = <16>; - }; - - /* Schematics call this PPVAR even though it's fixed */ - ppvar_logic: ppvar-logic { - compatible = "regulator-fixed"; - regulator-name = "ppvar_logic"; - - /* EC turns on w/ ppvar_logic_en; always on for AP */ - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - - vin-supply = <&ppvar_sys>; - }; - - pp1800_audio: pp1800-audio { - compatible = "regulator-fixed"; - regulator-name = "pp1800_audio"; - pinctrl-names = "default"; - pinctrl-0 = <&pp1800_audio_en>; - - enable-active-high; - gpio = <&gpio0 2 GPIO_ACTIVE_HIGH>; - - regulator-always-on; - regulator-boot-on; - - vin-supply = <&pp1800>; - }; - - /* gpio is shared with pp3300_wifi_bt */ - pp1800_pcie: pp1800-pcie { - compatible = "regulator-fixed"; - regulator-name = "pp1800_pcie"; - pinctrl-names = "default"; - pinctrl-0 = <&wlan_module_pd_l>; - - enable-active-high; - gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>; - - /* - * Need to wait 1ms + ramp-up time before we can power on WiFi. - * This has been approximated as 8ms total. - */ - regulator-enable-ramp-delay = <8000>; - - vin-supply = <&pp1800>; - }; - - /* Always on; plain and simple */ - pp3000_ap: pp3000_emmc: pp3000 { - }; - - pp1500_ap_io: pp1500-ap-io { - compatible = "regulator-fixed"; - regulator-name = "pp1500_ap_io"; - pinctrl-names = "default"; - pinctrl-0 = <&pp1500_en>; - - enable-active-high; - gpio = <&gpio0 10 GPIO_ACTIVE_HIGH>; - - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - - vin-supply = <&pp1800>; - }; - - pp3300_disp: pp3300-disp { - compatible = "regulator-fixed"; - regulator-name = "pp3300_disp"; - pinctrl-names = "default"; - pinctrl-0 = <&pp3300_disp_en>; - - enable-active-high; - gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; - - startup-delay-us = <2000>; - vin-supply = <&pp3300>; - }; - - /* EC turns on w/ pp3300_usb_en_l */ - pp3300_usb: pp3300 { - }; - - /* gpio is shared with pp1800_pcie and pinctrl is set there */ - pp3300_wifi_bt: pp3300-wifi-bt { - compatible = "regulator-fixed"; - regulator-name = "pp3300_wifi_bt"; - - enable-active-high; - gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>; - - vin-supply = <&pp3300>; - }; - - /* - * This is a bit of a hack. The WiFi module should be reset at least - * 1ms after its regulators have ramped up (max rampup time is ~7ms). - * With some stretching of the imagination, we can call the 1.8V - * regulator a supply. - */ - wlan_pd_n: wlan-pd-n { - compatible = "regulator-fixed"; - regulator-name = "wlan_pd_n"; - pinctrl-names = "default"; - pinctrl-0 = <&wlan_module_reset_l>; - - enable-active-high; - gpio = <&gpio1 11 GPIO_ACTIVE_HIGH>; - - vin-supply = <&pp1800_pcie>; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - enable-gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; - power-supply = <&pp3300_disp>; - pinctrl-names = "default"; - pinctrl-0 = <&bl_en>; - pwm-delay-us = <10000>; - }; - - gpio_keys: gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&bt_host_wake_l>; - - wake_on_bt: wake-on-bt { - label = "Wake-on-Bluetooth"; - gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - }; -}; - -&ppvar_bigcpu { - min-slew-down-rate = <225>; - ovp-threshold-percent = <16>; -}; - -&ppvar_litcpu { - min-slew-down-rate = <225>; - ovp-threshold-percent = <16>; -}; - -&ppvar_gpu { - min-slew-down-rate = <225>; - ovp-threshold-percent = <16>; -}; - -&cdn_dp { - extcon = <&usbc_extcon0>, <&usbc_extcon1>; -}; - -&edp { - status = "okay"; - - ports { - edp_out: port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - edp_out_panel: endpoint@0 { - reg = <0>; - remote-endpoint = <&panel_in_edp>; - }; - }; - }; -}; - -ap_i2c_mic: &i2c1 { - status = "okay"; - - clock-frequency = <400000>; - - /* These are relatively safe rise/fall times */ - i2c-scl-falling-time-ns = <50>; - i2c-scl-rising-time-ns = <300>; - - headsetcodec: rt5514@57 { - compatible = "realtek,rt5514"; - reg = <0x57>; - realtek,dmic-init-delay-ms = <20>; - }; -}; - -ap_i2c_tp: &i2c5 { - status = "okay"; - - clock-frequency = <400000>; - - /* These are relatively safe rise/fall times */ - i2c-scl-falling-time-ns = <50>; - i2c-scl-rising-time-ns = <300>; - - /* - * Note strange pullup enable. Apparently this avoids leakage but - * still allows us to get nice 4.7K pullups for high speed i2c - * transfers. Basically we want the pullup on whenever the ap is - * alive, so the "en" pin just gets set to output high. - */ - pinctrl-0 = <&i2c5_xfer &ap_i2c_tp_pu_en>; -}; - -&cros_ec { - cros_ec_pwm: ec-pwm { - compatible = "google,cros-ec-pwm"; - #pwm-cells = <1>; - }; - - usbc_extcon1: extcon@1 { - compatible = "google,extcon-usbc-cros-ec"; - google,usb-port-id = <1>; - - #extcon-cells = <0>; - }; -}; - -&sound { - rockchip,codec = <&max98357a &headsetcodec - &codec &wacky_spi_audio &cdn_dp>; -}; - -&spi2 { - wacky_spi_audio: spi2@0 { - compatible = "realtek,rt5514"; - reg = <0>; - interrupt-parent = <&gpio1>; - interrupts = <13 IRQ_TYPE_LEVEL_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&mic_int>; - /* May run faster once verified. */ - spi-max-frequency = <10000000>; - wakeup-source; - }; -}; - -&pci_rootport { - mvl_wifi: wifi@0,0 { - compatible = "pci1b4b,2b42"; - reg = <0x83010000 0x0 0x00000000 0x0 0x00100000 - 0x83010000 0x0 0x00100000 0x0 0x00100000>; - interrupt-parent = <&gpio0>; - interrupts = <8 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&wlan_host_wake_l>; - wakeup-source; - }; -}; - -&tcphy1 { - status = "okay"; - extcon = <&usbc_extcon1>; -}; - -&u2phy1 { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - -&usbdrd3_1 { - status = "okay"; - extcon = <&usbc_extcon1>; -}; - -&usbdrd_dwc3_1 { - status = "okay"; - dr_mode = "host"; -}; - -&pinctrl { - discrete-regulators { - pp1500_en: pp1500-en { - rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO - &pcfg_pull_none>; - }; - - pp1800_audio_en: pp1800-audio-en { - rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO - &pcfg_pull_down>; - }; - - pp3000_en: pp3000-en { - rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO - &pcfg_pull_none>; - }; - - pp3300_disp_en: pp3300-disp-en { - rockchip,pins = <4 RK_PD3 RK_FUNC_GPIO - &pcfg_pull_none>; - }; - - wlan_module_pd_l: wlan-module-pd-l { - rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO - &pcfg_pull_down>; - }; - }; -}; - -&wifi { - wifi_perst_l: wifi-perst-l { - rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - wlan_host_wake_l: wlan-host-wake-l { - rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; - }; -}; diff --git a/sys/gnu/dts/arm64/rockchip/rk3399-gru-kevin.dts b/sys/gnu/dts/arm64/rockchip/rk3399-gru-kevin.dts deleted file mode 100644 index 2bbef9fcbe2..00000000000 --- a/sys/gnu/dts/arm64/rockchip/rk3399-gru-kevin.dts +++ /dev/null @@ -1,327 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Gru-Kevin Rev 6+ board device tree source - * - * Copyright 2016-2017 Google, Inc - */ - -/dts-v1/; -#include "rk3399-gru-chromebook.dtsi" -#include - -/* - * Kevin-specific things - * - * Things in this section should use names from Kevin schematic since no - * equivalent exists in Gru schematic. If referring to signals that exist - * in Gru we use the Gru names, though. Confusing enough for you? - */ -/ { - model = "Google Kevin"; - compatible = "google,kevin-rev15", "google,kevin-rev14", - "google,kevin-rev13", "google,kevin-rev12", - "google,kevin-rev11", "google,kevin-rev10", - "google,kevin-rev9", "google,kevin-rev8", - "google,kevin-rev7", "google,kevin-rev6", - "google,kevin", "google,gru", "rockchip,rk3399"; - - /* Power tree */ - - p3_3v_dig: p3-3v-dig { - compatible = "regulator-fixed"; - regulator-name = "p3.3v_dig"; - pinctrl-names = "default"; - pinctrl-0 = <&cpu3_pen_pwr_en>; - - enable-active-high; - gpio = <&gpio4 30 GPIO_ACTIVE_HIGH>; - vin-supply = <&pp3300>; - }; - - edp_panel: edp-panel { - compatible = "sharp,lq123p1jx31"; - backlight = <&backlight>; - power-supply = <&pp3300_disp>; - - panel-timing { - clock-frequency = <266666667>; - hactive = <2400>; - hfront-porch = <48>; - hback-porch = <84>; - hsync-len = <32>; - hsync-active = <0>; - vactive = <1600>; - vfront-porch = <3>; - vback-porch = <120>; - vsync-len = <10>; - vsync-active = <0>; - }; - - port { - panel_in_edp: endpoint { - remote-endpoint = <&edp_out_panel>; - }; - }; - }; - - thermistor_ppvar_bigcpu: thermistor-ppvar-bigcpu { - compatible = "murata,ncp15wb473"; - pullup-uv = <1800000>; - pullup-ohm = <25500>; - pulldown-ohm = <0>; - io-channels = <&saradc 2>; - #thermal-sensor-cells = <0>; - }; - - thermistor_ppvar_litcpu: thermistor-ppvar-litcpu { - compatible = "murata,ncp15wb473"; - pullup-uv = <1800000>; - pullup-ohm = <25500>; - pulldown-ohm = <0>; - io-channels = <&saradc 3>; - #thermal-sensor-cells = <0>; - }; -}; - -&backlight { - pwms = <&cros_ec_pwm 1>; -}; - -&gpio_keys { - pinctrl-names = "default"; - pinctrl-0 = <&bt_host_wake_l>, <&cpu1_pen_eject>; - - pen-insert { - label = "Pen Insert"; - /* Insert = low, eject = high */ - gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; - linux,code = ; - linux,input-type = ; - wakeup-source; - }; -}; - -&thermal_zones { - bigcpu_reg_thermal: bigcpu-reg-thermal { - polling-delay-passive = <100>; /* milliseconds */ - polling-delay = <1000>; /* milliseconds */ - thermal-sensors = <&thermistor_ppvar_bigcpu 0>; - sustainable-power = <4000>; - - ppvar_bigcpu_trips: trips { - ppvar_bigcpu_on: ppvar-bigcpu-on { - temperature = <40000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - - ppvar_bigcpu_alert: ppvar-bigcpu-alert { - temperature = <50000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - - ppvar_bigcpu_crit: ppvar-bigcpu-crit { - temperature = <90000>; /* millicelsius */ - hysteresis = <0>; /* millicelsius */ - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&ppvar_bigcpu_alert>; - cooling-device = - <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - contribution = <4096>; - }; - map1 { - trip = <&ppvar_bigcpu_alert>; - cooling-device = - <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - contribution = <1024>; - }; - }; - }; - - litcpu_reg_thermal: litcpu-reg-thermal { - polling-delay-passive = <100>; /* milliseconds */ - polling-delay = <1000>; /* milliseconds */ - thermal-sensors = <&thermistor_ppvar_litcpu 0>; - sustainable-power = <4000>; - - ppvar_litcpu_trips: trips { - ppvar_litcpu_on: ppvar-litcpu-on { - temperature = <40000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - - ppvar_litcpu_alert: ppvar-litcpu-alert { - temperature = <50000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - - ppvar_litcpu_crit: ppvar-litcpu-crit { - temperature = <90000>; /* millicelsius */ - hysteresis = <0>; /* millicelsius */ - type = "critical"; - }; - }; - }; -}; - -ap_i2c_tpm: &i2c0 { - status = "okay"; - - clock-frequency = <400000>; - - /* These are relatively safe rise/fall times. */ - i2c-scl-falling-time-ns = <50>; - i2c-scl-rising-time-ns = <300>; - - tpm: tpm@20 { - compatible = "infineon,slb9645tt"; - reg = <0x20>; - powered-while-suspended; - }; -}; - -ap_i2c_dig: &i2c2 { - status = "okay"; - - clock-frequency = <400000>; - - /* These are relatively safe rise/fall times. */ - i2c-scl-falling-time-ns = <50>; - i2c-scl-rising-time-ns = <300>; - - digitizer: digitizer@9 { - /* wacom,w9013 */ - compatible = "hid-over-i2c"; - reg = <0x9>; - pinctrl-names = "default"; - pinctrl-0 = <&cpu1_dig_irq_l &cpu1_dig_pdct_l>; - - vdd-supply = <&p3_3v_dig>; - post-power-on-delay-ms = <100>; - - interrupt-parent = <&gpio2>; - interrupts = <4 IRQ_TYPE_LEVEL_LOW>; - - hid-descr-addr = <0x1>; - }; -}; - -/* Adjustments to things in the gru baseboard */ - -&ap_i2c_tp { - trackpad@4a { - compatible = "atmel,maxtouch"; - reg = <0x4a>; - pinctrl-names = "default"; - pinctrl-0 = <&trackpad_int_l>; - interrupt-parent = <&gpio1>; - interrupts = <4 IRQ_TYPE_LEVEL_LOW>; - linux,gpio-keymap = ; - wakeup-source; - }; -}; - -&ap_i2c_ts { - touchscreen@4b { - compatible = "atmel,maxtouch"; - reg = <0x4b>; - pinctrl-names = "default"; - pinctrl-0 = <&touch_int_l>; - interrupt-parent = <&gpio3>; - interrupts = <13 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&ppvar_bigcpu_pwm { - regulator-min-microvolt = <798674>; - regulator-max-microvolt = <1302172>; -}; - -&ppvar_bigcpu { - regulator-min-microvolt = <798674>; - regulator-max-microvolt = <1302172>; - ctrl-voltage-range = <798674 1302172>; -}; - -&ppvar_litcpu_pwm { - regulator-min-microvolt = <799065>; - regulator-max-microvolt = <1303738>; -}; - -&ppvar_litcpu { - regulator-min-microvolt = <799065>; - regulator-max-microvolt = <1303738>; - ctrl-voltage-range = <799065 1303738>; -}; - -&ppvar_gpu_pwm { - regulator-min-microvolt = <785782>; - regulator-max-microvolt = <1217729>; -}; - -&ppvar_gpu { - regulator-min-microvolt = <785782>; - regulator-max-microvolt = <1217729>; - ctrl-voltage-range = <785782 1217729>; -}; - -&ppvar_centerlogic_pwm { - regulator-min-microvolt = <800069>; - regulator-max-microvolt = <1049692>; -}; - -&ppvar_centerlogic { - regulator-min-microvolt = <800069>; - regulator-max-microvolt = <1049692>; - ctrl-voltage-range = <800069 1049692>; -}; - -&saradc { - status = "okay"; - vref-supply = <&pp1800_ap_io>; -}; - -&mvl_wifi { - marvell,wakeup-pin = <14>; /* GPIO_14 on Marvell */ -}; - -&pinctrl { - digitizer { - /* Has external pullup */ - cpu1_dig_irq_l: cpu1-dig-irq-l { - rockchip,pins = <2 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - /* Has external pullup */ - cpu1_dig_pdct_l: cpu1-dig-pdct-l { - rockchip,pins = <2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - discrete-regulators { - cpu3_pen_pwr_en: cpu3-pen-pwr-en { - rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pen { - cpu1_pen_eject: cpu1-pen-eject { - rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/rockchip/rk3399-gru-scarlet-inx.dts b/sys/gnu/dts/arm64/rockchip/rk3399-gru-scarlet-inx.dts deleted file mode 100644 index 2d721a97479..00000000000 --- a/sys/gnu/dts/arm64/rockchip/rk3399-gru-scarlet-inx.dts +++ /dev/null @@ -1,33 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Gru-Scarlet Rev4+ (SKU-6/Innolux) board device tree source - * - * Copyright 2018 Google, Inc - */ - -/dts-v1/; - -#include "rk3399-gru-scarlet.dtsi" - -/ { - model = "Google Scarlet"; - compatible = "google,scarlet-rev15-sku6", "google,scarlet-rev15", - "google,scarlet-rev14-sku6", "google,scarlet-rev14", - "google,scarlet-rev13-sku6", "google,scarlet-rev13", - "google,scarlet-rev12-sku6", "google,scarlet-rev12", - "google,scarlet-rev11-sku6", "google,scarlet-rev11", - "google,scarlet-rev10-sku6", "google,scarlet-rev10", - "google,scarlet-rev9-sku6", "google,scarlet-rev9", - "google,scarlet-rev8-sku6", "google,scarlet-rev8", - "google,scarlet-rev7-sku6", "google,scarlet-rev7", - "google,scarlet-rev6-sku6", "google,scarlet-rev6", - "google,scarlet-rev5-sku6", "google,scarlet-rev5", - "google,scarlet-rev4-sku6", "google,scarlet-rev4", - "google,scarlet", "google,gru", "rockchip,rk3399"; -}; - -&mipi_panel { - compatible = "innolux,p097pfg"; - avdd-supply = <&ppvarp_lcd>; - avee-supply = <&ppvarn_lcd>; -}; diff --git a/sys/gnu/dts/arm64/rockchip/rk3399-gru-scarlet-kd.dts b/sys/gnu/dts/arm64/rockchip/rk3399-gru-scarlet-kd.dts deleted file mode 100644 index bd759221727..00000000000 --- a/sys/gnu/dts/arm64/rockchip/rk3399-gru-scarlet-kd.dts +++ /dev/null @@ -1,33 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Gru-Scarlet Rev3+ (SKU-7/Kingdisplay) board device tree source - * - * Copyright 2018 Google, Inc - */ - -/dts-v1/; - -#include "rk3399-gru-scarlet.dtsi" - -/ { - model = "Google Scarlet"; - compatible = "google,scarlet-rev15-sku7", "google,scarlet-rev15", - "google,scarlet-rev14-sku7", "google,scarlet-rev14", - "google,scarlet-rev13-sku7", "google,scarlet-rev13", - "google,scarlet-rev12-sku7", "google,scarlet-rev12", - "google,scarlet-rev11-sku7", "google,scarlet-rev11", - "google,scarlet-rev10-sku7", "google,scarlet-rev10", - "google,scarlet-rev9-sku7", "google,scarlet-rev9", - "google,scarlet-rev8-sku7", "google,scarlet-rev8", - "google,scarlet-rev7-sku7", "google,scarlet-rev7", - "google,scarlet-rev6-sku7", "google,scarlet-rev6", - "google,scarlet-rev5-sku7", "google,scarlet-rev5", - "google,scarlet-rev4-sku7", "google,scarlet-rev4", - "google,scarlet-rev3-sku7", "google,scarlet-rev3", - "google,scarlet", "google,gru", "rockchip,rk3399"; -}; - -&mipi_panel { - compatible = "kingdisplay,kd097d04"; - power-supply = <&pp3300_s0>; -}; diff --git a/sys/gnu/dts/arm64/rockchip/rk3399-gru-scarlet.dtsi b/sys/gnu/dts/arm64/rockchip/rk3399-gru-scarlet.dtsi deleted file mode 100644 index 4373ed732af..00000000000 --- a/sys/gnu/dts/arm64/rockchip/rk3399-gru-scarlet.dtsi +++ /dev/null @@ -1,616 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Gru-scarlet board device tree source - * - * Copyright 2018 Google, Inc - */ - -#include "rk3399-gru.dtsi" - -/{ - /* Power tree */ - - /* ppvar_sys children, sorted by name */ - pp1250_s3: pp1250-s3 { - compatible = "regulator-fixed"; - regulator-name = "pp1250_s3"; - - /* EC turns on w/ pp1250_s3_en; always on for AP */ - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1250000>; - - vin-supply = <&ppvar_sys>; - }; - - pp1250_cam: pp1250-dvdd { - compatible = "regulator-fixed"; - regulator-name = "pp1250_dvdd"; - pinctrl-names = "default"; - pinctrl-0 = <&pp1250_cam_en>; - - enable-active-high; - gpio = <&gpio2 4 GPIO_ACTIVE_HIGH>; - - /* 740us delay from gpio output high to pp1250 stable, - * rounding up to 1ms for safety. - */ - startup-delay-us = <1000>; - vin-supply = <&pp1250_s3>; - }; - - pp900_s0: pp900-s0 { - compatible = "regulator-fixed"; - regulator-name = "pp900_s0"; - - /* EC turns on w/ pp900_s0_en; always on for AP */ - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - - vin-supply = <&ppvar_sys>; - }; - - ppvarn_lcd: ppvarn-lcd { - compatible = "regulator-fixed"; - regulator-name = "ppvarn_lcd"; - pinctrl-names = "default"; - pinctrl-0 = <&ppvarn_lcd_en>; - - enable-active-high; - gpio = <&gpio4 28 GPIO_ACTIVE_HIGH>; - vin-supply = <&ppvar_sys>; - }; - - ppvarp_lcd: ppvarp-lcd { - compatible = "regulator-fixed"; - regulator-name = "ppvarp_lcd"; - pinctrl-names = "default"; - pinctrl-0 = <&ppvarp_lcd_en>; - - enable-active-high; - gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; - vin-supply = <&ppvar_sys>; - }; - - /* pp1800 children, sorted by name */ - pp900_s3: pp900-s3 { - compatible = "regulator-fixed"; - regulator-name = "pp900_s3"; - - /* EC turns on w/ pp900_s3_en; always on for AP */ - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - - vin-supply = <&pp1800>; - }; - - /* EC turns on pp1800_s3_en */ - pp1800_s3: pp1800 { - }; - - /* pp3300 children, sorted by name */ - pp2800_cam: pp2800-avdd { - compatible = "regulator-fixed"; - regulator-name = "pp2800_avdd"; - pinctrl-names = "default"; - pinctrl-0 = <&pp2800_cam_en>; - - enable-active-high; - gpio = <&gpio2 24 GPIO_ACTIVE_HIGH>; - startup-delay-us = <100>; - vin-supply = <&pp3300>; - }; - - /* EC turns on pp3300_s0_en */ - pp3300_s0: pp3300 { - }; - - /* EC turns on pp3300_s3_en */ - pp3300_s3: pp3300 { - }; - - /* - * See b/66922012 - * - * This is a hack to make sure the Bluetooth part of the QCA6174A - * is reset at boot by toggling BT_EN. At boot BT_EN is first set - * to low when the bt_3v3 regulator is registered (in disabled - * state). The fake regulator is configured as a supply of the - * wlan_3v3 regulator below. When wlan_3v3 is enabled early in - * the boot process it also enables its supply regulator bt_3v3, - * which changes BT_EN to high. - */ - bt_3v3: bt-3v3 { - compatible = "regulator-fixed"; - regulator-name = "bt_3v3"; - pinctrl-names = "default"; - pinctrl-0 = <&bt_en_1v8_l>; - - enable-active-high; - gpio = <&gpio0 8 GPIO_ACTIVE_HIGH>; - vin-supply = <&pp3300_s3>; - }; - - wlan_3v3: wlan-3v3 { - compatible = "regulator-fixed"; - regulator-name = "wlan_3v3"; - pinctrl-names = "default"; - pinctrl-0 = <&wlan_pd_1v8_l>; - - /* - * The WL_EN pin is driven low when the regulator is - * registered, and transitions to high when the PCIe bus - * is powered up. - */ - enable-active-high; - gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>; - - /* - * Require minimum 10ms from power-on (e.g., PD#) to init PCIe. - * TODO (b/64444991): how long to assert PD#? - */ - regulator-enable-ramp-delay = <10000>; - /* See bt_3v3 hack above */ - vin-supply = <&bt_3v3>; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - enable-gpios = <&gpio4 21 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&bl_en>; - pwms = <&pwm1 0 1000000 0>; - pwm-delay-us = <10000>; - }; - - dmic: dmic { - compatible = "dmic-codec"; - dmicen-gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&dmic_en>; - wakeup-delay-ms = <250>; - }; - - gpio_keys: gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pen_eject_odl>; - - pen-insert { - label = "Pen Insert"; - /* Insert = low, eject = high */ - gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; - linux,code = ; - linux,input-type = ; - wakeup-source; - }; - }; -}; - -/* pp900_s0 aliases */ -pp900_ddrpll_ap: &pp900_s0 { -}; -pp900_pcie: &pp900_s0 { -}; -pp900_usb: &pp900_s0 { -}; - -/* pp900_s3 aliases */ -pp900_emmcpll: &pp900_s3 { -}; - -/* EC turns on; alias for pp1800_s0 */ -pp1800_pcie: &pp1800_s0 { -}; - -/* On scarlet PPVAR(big_cpu, lit_cpu, gpu) need to adjust voltage ranges */ -&ppvar_bigcpu { - ctrl-voltage-range = <800074 1299226>; - regulator-min-microvolt = <800074>; - regulator-max-microvolt = <1299226>; -}; - -&ppvar_bigcpu_pwm { - /* On scarlet ppvar big cpu use pwm3 */ - pwms = <&pwm3 0 3337 0>; - regulator-min-microvolt = <800074>; - regulator-max-microvolt = <1299226>; -}; - -&ppvar_litcpu { - ctrl-voltage-range = <802122 1199620>; - regulator-min-microvolt = <802122>; - regulator-max-microvolt = <1199620>; -}; - -&ppvar_litcpu_pwm { - regulator-min-microvolt = <802122>; - regulator-max-microvolt = <1199620>; -}; - -&ppvar_gpu { - ctrl-voltage-range = <799600 1099600>; - regulator-min-microvolt = <799600>; - regulator-max-microvolt = <1099600>; -}; - -&ppvar_gpu_pwm { - regulator-min-microvolt = <799600>; - regulator-max-microvolt = <1099600>; -}; - -&ppvar_sd_card_io { - states = <1800000 0x0 3300000 0x1>; - regulator-max-microvolt = <3300000>; -}; - -&pp3000_sd_slot { - vin-supply = <&pp3300>; -}; - -ap_i2c_dig: &i2c2 { - status = "okay"; - - clock-frequency = <400000>; - - /* These are relatively safe rise/fall times. */ - i2c-scl-falling-time-ns = <50>; - i2c-scl-rising-time-ns = <300>; - - digitizer: digitizer@9 { - compatible = "hid-over-i2c"; - reg = <0x9>; - interrupt-parent = <&gpio1>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - hid-descr-addr = <0x1>; - pinctrl-names = "default"; - pinctrl-0 = <&pen_int_odl &pen_reset_l>; - }; -}; - -&ap_i2c_ts { - touchscreen: touchscreen@10 { - compatible = "elan,ekth3500"; - reg = <0x10>; - interrupt-parent = <&gpio1>; - interrupts = <4 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&touch_int_l &touch_reset_l>; - reset-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; - }; -}; - -camera: &i2c7 { - status = "okay"; - - clock-frequency = <400000>; - - /* These are relatively safe rise/fall times; TODO: measure */ - i2c-scl-falling-time-ns = <50>; - i2c-scl-rising-time-ns = <300>; - - /* 24M mclk is shared between world and user cameras */ - pinctrl-0 = <&i2c7_xfer &test_clkout1>; -}; - -&cdn_dp { - extcon = <&usbc_extcon0>; - phys = <&tcphy0_dp>; -}; - -&cpu_alert0 { - temperature = <66000>; -}; - -&cpu_alert1 { - temperature = <71000>; -}; - -&cros_ec { - interrupt-parent = <&gpio1>; - interrupts = <18 IRQ_TYPE_LEVEL_LOW>; -}; - -&cru { - assigned-clocks = - <&cru PLL_GPLL>, <&cru PLL_CPLL>, - <&cru PLL_NPLL>, - <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>, - <&cru PCLK_PERIHP>, - <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>, - <&cru PCLK_PERILP0>, <&cru ACLK_CCI>, - <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>, - <&cru ACLK_VIO>, - <&cru ACLK_GIC_PRE>, - <&cru PCLK_DDR>, - <&cru ACLK_HDCP>; - assigned-clock-rates = - <600000000>, <1600000000>, - <1000000000>, - <150000000>, <75000000>, - <37500000>, - <100000000>, <100000000>, - <50000000>, <800000000>, - <100000000>, <50000000>, - <400000000>, - <200000000>, - <200000000>, - <400000000>; -}; - -&i2c_tunnel { - google,remote-bus = <0>; -}; - -&io_domains { - bt656-supply = <&pp1800_s0>; /* APIO2_VDD; 2a 2b */ - audio-supply = <&pp1800_s0>; /* APIO5_VDD; 3d 4a */ - gpio1830-supply = <&pp1800_s0>; /* APIO4_VDD; 4c 4d */ -}; - -&max98357a { - sdmode-gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>; -}; - -&mipi_dsi { - status = "okay"; - clock-master; - - ports { - mipi_out: port@1 { - reg = <1>; - - mipi_out_panel: endpoint { - remote-endpoint = <&mipi_in_panel>; - }; - }; - }; - - mipi_panel: panel@0 { - /* 2 different panels are used, compatibles are in dts files */ - reg = <0>; - backlight = <&backlight>; - enable-gpios = <&gpio4 25 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&display_rst_l>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - mipi_in_panel: endpoint { - remote-endpoint = <&mipi_out_panel>; - }; - }; - - port@1 { - reg = <1>; - - mipi1_in_panel: endpoint@1 { - remote-endpoint = <&mipi1_out_panel>; - }; - }; - }; - }; -}; - -&mipi_dsi1 { - status = "okay"; - - ports { - mipi1_out: port@1 { - reg = <1>; - - mipi1_out_panel: endpoint { - remote-endpoint = <&mipi1_in_panel>; - }; - }; - }; -}; - -&pcie0 { - ep-gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>; - - /* PERST# asserted in S3 */ - pcie-reset-suspend = <1>; - - vpcie3v3-supply = <&wlan_3v3>; - vpcie1v8-supply = <&pp1800_pcie>; -}; - -&sdmmc { - cd-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; -}; - -&sound { - rockchip,codec = <&max98357a &dmic &codec &cdn_dp>; -}; - -&spi2 { - status = "okay"; - - cr50@0 { - compatible = "google,cr50"; - reg = <0>; - interrupt-parent = <&gpio1>; - interrupts = <17 IRQ_TYPE_EDGE_RISING>; - pinctrl-names = "default"; - pinctrl-0 = <&h1_int_od_l>; - spi-max-frequency = <800000>; - }; -}; - -&usb_host0_ohci { - #address-cells = <1>; - #size-cells = <0>; - - qca_bt: bluetooth@1 { - compatible = "usbcf3,e300", "usb4ca,301a"; - reg = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&bt_host_wake_l>; - interrupt-parent = <&gpio1>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "wakeup"; - }; -}; - -/* PINCTRL OVERRIDES */ -&ec_ap_int_l { - rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>; -}; - -&ap_fw_wp { - rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; -}; - -&bl_en { - rockchip,pins = <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; -}; - -&bt_host_wake_l { - rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; -}; - -&ec_ap_int_l { - rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>; -}; - -&headset_int_l { - rockchip,pins = <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; -}; - -&i2s0_8ch_bus { - rockchip,pins = - <3 RK_PD0 1 &pcfg_pull_none_6ma>, - <3 RK_PD1 1 &pcfg_pull_none_6ma>, - <3 RK_PD2 1 &pcfg_pull_none_6ma>, - <3 RK_PD3 1 &pcfg_pull_none_6ma>, - <3 RK_PD7 1 &pcfg_pull_none_6ma>, - <4 RK_PA0 1 &pcfg_pull_none_6ma>; -}; - -/* there is no external pull up, so need to set this pin pull up */ -&sdmmc_cd_gpio { - rockchip,pins = <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>; -}; - -&sd_pwr_1800_sel { - rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; -}; - -&sdmode_en { - rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_down>; -}; - -&touch_reset_l { - rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>; -}; - -&touch_int_l { - rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>; -}; - -&pinctrl { - pinctrl-0 = < - &ap_pwroff /* AP will auto-assert this when in S3 */ - &clk_32k /* This pin is always 32k on gru boards */ - &wlan_rf_kill_1v8_l - >; - - pcfg_pull_none_6ma: pcfg-pull-none-6ma { - bias-disable; - drive-strength = <6>; - }; - - camera { - pp1250_cam_en: pp1250-dvdd { - rockchip,pins = <2 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - pp2800_cam_en: pp2800-avdd { - rockchip,pins = <2 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - ucam_rst: ucam_rst { - rockchip,pins = <2 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - wcam_rst: wcam_rst { - rockchip,pins = <2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - digitizer { - pen_int_odl: pen-int-odl { - rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - pen_reset_l: pen-reset-l { - rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - discrete-regulators { - display_rst_l: display-rst-l { - rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - ppvarp_lcd_en: ppvarp-lcd-en { - rockchip,pins = <4 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - ppvarn_lcd_en: ppvarn-lcd-en { - rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - dmic { - dmic_en: dmic-en { - rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pen { - pen_eject_odl: pen-eject-odl { - rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - tpm { - h1_int_od_l: h1-int-od-l { - rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; -}; - -&wifi { - bt_en_1v8_l: bt-en-1v8-l { - rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - wlan_pd_1v8_l: wlan-pd-1v8-l { - rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - /* Default pull-up, but just to be clear */ - wlan_rf_kill_1v8_l: wlan-rf-kill-1v8-l { - rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - wifi_perst_l: wifi-perst-l { - rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - wlan_host_wake_l: wlan-host-wake-l { - rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; - }; -}; diff --git a/sys/gnu/dts/arm64/rockchip/rk3399-gru.dtsi b/sys/gnu/dts/arm64/rockchip/rk3399-gru.dtsi deleted file mode 100644 index dd5624975c9..00000000000 --- a/sys/gnu/dts/arm64/rockchip/rk3399-gru.dtsi +++ /dev/null @@ -1,826 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Gru (and derivatives) board device tree source - * - * Copyright 2016-2017 Google, Inc - */ - -#include -#include "rk3399.dtsi" -#include "rk3399-op1-opp.dtsi" - -/ { - chosen { - stdout-path = "serial2:115200n8"; - }; - - /* - * Power Tree - * - * In general an attempt is made to include all rails called out by - * the schematic as long as those rails interact in some way with - * the AP. AKA: - * - Rails that only connect to the EC (or devices that the EC talks to) - * are not included. - * - Rails _are_ included if the rails go to the AP even if the AP - * doesn't currently care about them / they are always on. The idea - * here is that it makes it easier to map to the schematic or extend - * later. - * - * If two rails are substantially the same from the AP's point of - * view, though, we won't create a full fixed regulator. We'll just - * put the child rail as an alias of the parent rail. Sometimes rails - * look the same to the AP because one of these is true: - * - The EC controls the enable and the EC always enables a rail as - * long as the AP is running. - * - The rails are actually connected to each other by a jumper and - * the distinction is just there to add clarity/flexibility to the - * schematic. - */ - - ppvar_sys: ppvar-sys { - compatible = "regulator-fixed"; - regulator-name = "ppvar_sys"; - regulator-always-on; - regulator-boot-on; - }; - - pp1200_lpddr: pp1200-lpddr { - compatible = "regulator-fixed"; - regulator-name = "pp1200_lpddr"; - - /* EC turns on w/ lpddr_pwr_en; always on for AP */ - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - - vin-supply = <&ppvar_sys>; - }; - - pp1800: pp1800 { - compatible = "regulator-fixed"; - regulator-name = "pp1800"; - - /* Always on when ppvar_sys shows power good */ - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - vin-supply = <&ppvar_sys>; - }; - - pp3300: pp3300 { - compatible = "regulator-fixed"; - regulator-name = "pp3300"; - - /* Always on; plain and simple */ - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - vin-supply = <&ppvar_sys>; - }; - - pp5000: pp5000 { - compatible = "regulator-fixed"; - regulator-name = "pp5000"; - - /* EC turns on w/ pp5000_en; always on for AP */ - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - vin-supply = <&ppvar_sys>; - }; - - ppvar_bigcpu_pwm: ppvar-bigcpu-pwm { - compatible = "pwm-regulator"; - regulator-name = "ppvar_bigcpu_pwm"; - - pwms = <&pwm1 0 3337 0>; - pwm-supply = <&ppvar_sys>; - pwm-dutycycle-range = <100 0>; - pwm-dutycycle-unit = <100>; - - /* EC turns on w/ ap_core_en; always on for AP */ - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <800107>; - regulator-max-microvolt = <1302232>; - }; - - ppvar_bigcpu: ppvar-bigcpu { - compatible = "vctrl-regulator"; - regulator-name = "ppvar_bigcpu"; - - regulator-min-microvolt = <800107>; - regulator-max-microvolt = <1302232>; - - ctrl-supply = <&ppvar_bigcpu_pwm>; - ctrl-voltage-range = <800107 1302232>; - - regulator-settling-time-up-us = <322>; - }; - - ppvar_litcpu_pwm: ppvar-litcpu-pwm { - compatible = "pwm-regulator"; - regulator-name = "ppvar_litcpu_pwm"; - - pwms = <&pwm2 0 3337 0>; - pwm-supply = <&ppvar_sys>; - pwm-dutycycle-range = <100 0>; - pwm-dutycycle-unit = <100>; - - /* EC turns on w/ ap_core_en; always on for AP */ - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <797743>; - regulator-max-microvolt = <1307837>; - }; - - ppvar_litcpu: ppvar-litcpu { - compatible = "vctrl-regulator"; - regulator-name = "ppvar_litcpu"; - - regulator-min-microvolt = <797743>; - regulator-max-microvolt = <1307837>; - - ctrl-supply = <&ppvar_litcpu_pwm>; - ctrl-voltage-range = <797743 1307837>; - - regulator-settling-time-up-us = <384>; - }; - - ppvar_gpu_pwm: ppvar-gpu-pwm { - compatible = "pwm-regulator"; - regulator-name = "ppvar_gpu_pwm"; - - pwms = <&pwm0 0 3337 0>; - pwm-supply = <&ppvar_sys>; - pwm-dutycycle-range = <100 0>; - pwm-dutycycle-unit = <100>; - - /* EC turns on w/ ap_core_en; always on for AP */ - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <786384>; - regulator-max-microvolt = <1217747>; - }; - - ppvar_gpu: ppvar-gpu { - compatible = "vctrl-regulator"; - regulator-name = "ppvar_gpu"; - - regulator-min-microvolt = <786384>; - regulator-max-microvolt = <1217747>; - - ctrl-supply = <&ppvar_gpu_pwm>; - ctrl-voltage-range = <786384 1217747>; - - regulator-settling-time-up-us = <390>; - }; - - /* EC turns on w/ pp900_ddrpll_en */ - pp900_ddrpll: pp900-ap { - }; - - /* EC turns on w/ pp900_pll_en */ - pp900_pll: pp900-ap { - }; - - /* EC turns on w/ pp900_pmu_en */ - pp900_pmu: pp900-ap { - }; - - /* EC turns on w/ pp1800_s0_en_l */ - pp1800_ap_io: pp1800_emmc: pp1800_nfc: pp1800_s0: pp1800 { - }; - - /* EC turns on w/ pp1800_avdd_en_l */ - pp1800_avdd: pp1800 { - }; - - /* EC turns on w/ pp1800_lid_en_l */ - pp1800_lid: pp1800_mic: pp1800 { - }; - - /* EC turns on w/ lpddr_pwr_en */ - pp1800_lpddr: pp1800 { - }; - - /* EC turns on w/ pp1800_pmu_en_l */ - pp1800_pmu: pp1800 { - }; - - /* EC turns on w/ pp1800_usb_en_l */ - pp1800_usb: pp1800 { - }; - - pp3000_sd_slot: pp3000-sd-slot { - compatible = "regulator-fixed"; - regulator-name = "pp3000_sd_slot"; - pinctrl-names = "default"; - pinctrl-0 = <&sd_slot_pwr_en>; - - enable-active-high; - gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>; - - vin-supply = <&pp3000>; - }; - - /* - * Technically, this is a small abuse of 'regulator-gpio'; this - * regulator is a mux between pp1800 and pp3300. pp1800 and pp3300 are - * always on though, so it is sufficient to simply control the mux - * here. - */ - ppvar_sd_card_io: ppvar-sd-card-io { - compatible = "regulator-gpio"; - regulator-name = "ppvar_sd_card_io"; - pinctrl-names = "default"; - pinctrl-0 = <&sd_io_pwr_en &sd_pwr_1800_sel>; - - enable-active-high; - enable-gpio = <&gpio2 2 GPIO_ACTIVE_HIGH>; - gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>; - states = <1800000 0x1 - 3000000 0x0>; - - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3000000>; - }; - - /* EC turns on w/ pp3300_trackpad_en_l */ - pp3300_trackpad: pp3300-trackpad { - }; - - /* EC turns on w/ usb_a_en */ - pp5000_usb_a_vbus: pp5000 { - }; - - ap_rtc_clk: ap-rtc-clk { - compatible = "fixed-clock"; - clock-frequency = <32768>; - clock-output-names = "xin32k"; - #clock-cells = <0>; - }; - - max98357a: max98357a { - compatible = "maxim,max98357a"; - pinctrl-names = "default"; - pinctrl-0 = <&sdmode_en>; - sdmode-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; - sdmode-delay = <2>; - #sound-dai-cells = <0>; - status = "okay"; - }; - - sound: sound { - compatible = "rockchip,rk3399-gru-sound"; - rockchip,cpu = <&i2s0 &i2s2>; - }; -}; - -&cdn_dp { - status = "okay"; -}; - -/* - * Set some suspend operating points to avoid OVP in suspend - * - * When we go into S3 ARM Trusted Firmware will transition our PWM regulators - * from wherever they're at back to the "default" operating point (whatever - * voltage we get when we set the PWM pins to "input"). - * - * This quick transition under light load has the possibility to trigger the - * regulator "over voltage protection" (OVP). - * - * To make extra certain that we don't hit this OVP at suspend time, we'll - * transition to a voltage that's much closer to the default (~1.0 V) so that - * there will not be a big jump. Technically we only need to get within 200 mV - * of the default voltage, but the speed here should be fast enough and we need - * suspend/resume to be rock solid. - */ - -&cluster0_opp { - opp05 { - opp-suspend; - }; -}; - -&cluster1_opp { - opp06 { - opp-suspend; - }; -}; - -&cpu_l0 { - cpu-supply = <&ppvar_litcpu>; -}; - -&cpu_l1 { - cpu-supply = <&ppvar_litcpu>; -}; - -&cpu_l2 { - cpu-supply = <&ppvar_litcpu>; -}; - -&cpu_l3 { - cpu-supply = <&ppvar_litcpu>; -}; - -&cpu_b0 { - cpu-supply = <&ppvar_bigcpu>; -}; - -&cpu_b1 { - cpu-supply = <&ppvar_bigcpu>; -}; - - -&cru { - assigned-clocks = - <&cru PLL_GPLL>, <&cru PLL_CPLL>, - <&cru PLL_NPLL>, - <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>, - <&cru PCLK_PERIHP>, - <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>, - <&cru PCLK_PERILP0>, <&cru ACLK_CCI>, - <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>, - <&cru ACLK_VIO>, <&cru ACLK_HDCP>, - <&cru ACLK_GIC_PRE>, - <&cru PCLK_DDR>; - assigned-clock-rates = - <600000000>, <800000000>, - <1000000000>, - <150000000>, <75000000>, - <37500000>, - <100000000>, <100000000>, - <50000000>, <800000000>, - <100000000>, <50000000>, - <400000000>, <400000000>, - <200000000>, - <200000000>; -}; - -&emmc_phy { - status = "okay"; -}; - -&gpu { - mali-supply = <&ppvar_gpu>; - status = "okay"; -}; - -ap_i2c_ts: &i2c3 { - status = "okay"; - - clock-frequency = <400000>; - - /* These are relatively safe rise/fall times */ - i2c-scl-falling-time-ns = <50>; - i2c-scl-rising-time-ns = <300>; -}; - -ap_i2c_audio: &i2c8 { - status = "okay"; - - clock-frequency = <400000>; - - /* These are relatively safe rise/fall times */ - i2c-scl-falling-time-ns = <50>; - i2c-scl-rising-time-ns = <300>; - - codec: da7219@1a { - compatible = "dlg,da7219"; - reg = <0x1a>; - interrupt-parent = <&gpio1>; - interrupts = <23 IRQ_TYPE_LEVEL_LOW>; - clocks = <&cru SCLK_I2S_8CH_OUT>; - clock-names = "mclk"; - dlg,micbias-lvl = <2600>; - dlg,mic-amp-in-sel = "diff"; - pinctrl-names = "default"; - pinctrl-0 = <&headset_int_l>; - VDD-supply = <&pp1800>; - VDDMIC-supply = <&pp3300>; - VDDIO-supply = <&pp1800>; - - da7219_aad { - dlg,adc-1bit-rpt = <1>; - dlg,btn-avg = <4>; - dlg,btn-cfg = <50>; - dlg,mic-det-thr = <500>; - dlg,jack-ins-deb = <20>; - dlg,jack-det-rate = "32ms_64ms"; - dlg,jack-rem-deb = <1>; - - dlg,a-d-btn-thr = <0xa>; - dlg,d-b-btn-thr = <0x16>; - dlg,b-c-btn-thr = <0x21>; - dlg,c-mic-btn-thr = <0x3E>; - }; - }; -}; - -&i2s0 { - status = "okay"; -}; - -&i2s2 { - status = "okay"; -}; - -&io_domains { - status = "okay"; - - audio-supply = <&pp1800_audio>; /* APIO5_VDD; 3d 4a */ - bt656-supply = <&pp1800_ap_io>; /* APIO2_VDD; 2a 2b */ - gpio1830-supply = <&pp3000_ap>; /* APIO4_VDD; 4c 4d */ - sdmmc-supply = <&ppvar_sd_card_io>; /* SDMMC0_VDD; 4b */ -}; - -&pcie0 { - status = "okay"; - - ep-gpios = <&gpio2 27 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie_clkreqn_cpm>, <&wifi_perst_l>; - vpcie3v3-supply = <&pp3300_wifi_bt>; - vpcie1v8-supply = <&wlan_pd_n>; /* HACK: see &wlan_pd_n */ - vpcie0v9-supply = <&pp900_pcie>; - - pci_rootport: pcie@0,0 { - reg = <0x83000000 0x0 0x00000000 0x0 0x00000000>; - #address-cells = <3>; - #size-cells = <2>; - ranges; - }; -}; - -&pcie_phy { - status = "okay"; -}; - -&pmu_io_domains { - status = "okay"; - - pmu1830-supply = <&pp1800_pmu>; /* PMUIO2_VDD */ -}; - -&pwm0 { - status = "okay"; -}; - -&pwm1 { - status = "okay"; -}; - -&pwm2 { - status = "okay"; -}; - -&pwm3 { - status = "okay"; -}; - -&sdhci { - /* - * Signal integrity isn't great at 200 MHz and 150 MHz (DDR) gives the - * same (or nearly the same) performance for all eMMC that are intended - * to be used. - */ - assigned-clock-rates = <150000000>; - - bus-width = <8>; - mmc-hs400-1_8v; - mmc-hs400-enhanced-strobe; - non-removable; - status = "okay"; -}; - -&sdmmc { - status = "okay"; - - /* - * Note: configure "sdmmc_cd" as card detect even though it's actually - * hooked to ground. Because we specified "cd-gpios" below dw_mmc - * should be ignoring card detect anyway. Specifying the pin as - * sdmmc_cd means that even if you've got GRF_SOC_CON7[12] (force_jtag) - * turned on that the system will still make sure the port is - * configured as SDMMC and not JTAG. - */ - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_cd_gpio - &sdmmc_bus4>; - - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - cd-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; - disable-wp; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-sdr104; - vmmc-supply = <&pp3000_sd_slot>; - vqmmc-supply = <&ppvar_sd_card_io>; -}; - -&spi1 { - status = "okay"; - - pinctrl-names = "default", "sleep"; - pinctrl-1 = <&spi1_sleep>; - - spiflash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - - /* May run faster once verified. */ - spi-max-frequency = <10000000>; - }; -}; - -&spi2 { - status = "okay"; -}; - -&spi5 { - status = "okay"; - - cros_ec: ec@0 { - compatible = "google,cros-ec-spi"; - reg = <0>; - interrupt-parent = <&gpio0>; - interrupts = <1 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&ec_ap_int_l>; - spi-max-frequency = <3000000>; - - i2c_tunnel: i2c-tunnel { - compatible = "google,cros-ec-i2c-tunnel"; - google,remote-bus = <4>; - #address-cells = <1>; - #size-cells = <0>; - }; - - usbc_extcon0: extcon@0 { - compatible = "google,extcon-usbc-cros-ec"; - google,usb-port-id = <0>; - - #extcon-cells = <0>; - }; - }; -}; - -&tsadc { - status = "okay"; - - rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */ - rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */ -}; - -&tcphy0 { - status = "okay"; - extcon = <&usbc_extcon0>; -}; - -&u2phy0 { - status = "okay"; -}; - -&u2phy0_host { - status = "okay"; -}; - -&u2phy1_host { - status = "okay"; -}; - -&u2phy0_otg { - status = "okay"; -}; - -&u2phy1_otg { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usbdrd3_0 { - status = "okay"; - extcon = <&usbc_extcon0>; -}; - -&usbdrd_dwc3_0 { - status = "okay"; - dr_mode = "host"; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&vopl { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; -}; - -#include -#include - -&pinctrl { - /* - * pinctrl settings for pins that have no real owners. - * - * At the moment settings are identical for S0 and S3, but if we later - * need to configure things differently for S3 we'll adjust here. - */ - pinctrl-names = "default"; - pinctrl-0 = < - &ap_pwroff /* AP will auto-assert this when in S3 */ - &clk_32k /* This pin is always 32k on gru boards */ - >; - - pcfg_output_low: pcfg-output-low { - output-low; - }; - - pcfg_output_high: pcfg-output-high { - output-high; - }; - - pcfg_pull_none_8ma: pcfg-pull-none-8ma { - bias-disable; - drive-strength = <8>; - }; - - backlight-enable { - bl_en: bl-en { - rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - cros-ec { - ec_ap_int_l: ec-ap-int-l { - rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - discrete-regulators { - sd_io_pwr_en: sd-io-pwr-en { - rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO - &pcfg_pull_none>; - }; - - sd_pwr_1800_sel: sd-pwr-1800-sel { - rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO - &pcfg_pull_none>; - }; - - sd_slot_pwr_en: sd-slot-pwr-en { - rockchip,pins = <4 RK_PD5 RK_FUNC_GPIO - &pcfg_pull_none>; - }; - }; - - codec { - /* Has external pullup */ - headset_int_l: headset-int-l { - rockchip,pins = <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - mic_int: mic-int { - rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; - - max98357a { - sdmode_en: sdmode-en { - rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; - - pcie { - pcie_clkreqn_cpm: pci-clkreqn-cpm { - /* - * Since our pcie doesn't support ClockPM(CPM), we want - * to hack this as gpio, so the EP could be able to - * de-assert it along and make ClockPM(CPM) work. - */ - rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - sdmmc { - /* - * We run sdmmc at max speed; bump up drive strength. - * We also have external pulls, so disable the internal ones. - */ - sdmmc_bus4: sdmmc-bus4 { - rockchip,pins = - <4 RK_PB0 1 &pcfg_pull_none_8ma>, - <4 RK_PB1 1 &pcfg_pull_none_8ma>, - <4 RK_PB2 1 &pcfg_pull_none_8ma>, - <4 RK_PB3 1 &pcfg_pull_none_8ma>; - }; - - sdmmc_clk: sdmmc-clk { - rockchip,pins = - <4 RK_PB4 1 &pcfg_pull_none_8ma>; - }; - - sdmmc_cmd: sdmmc-cmd { - rockchip,pins = - <4 RK_PB5 1 &pcfg_pull_none_8ma>; - }; - - /* - * In our case the official card detect is hooked to ground - * to avoid getting access to JTAG just by sticking something - * in the SD card slot (see the force_jtag bit in the TRM). - * - * We still configure it as card detect because it doesn't - * hurt and dw_mmc will ignore it. We make sure to disable - * the pull though so we don't burn needless power. - */ - sdmmc_cd: sdmmc-cd { - rockchip,pins = - <0 RK_PA7 1 &pcfg_pull_none>; - }; - - /* This is where we actually hook up CD; has external pull */ - sdmmc_cd_gpio: sdmmc-cd-gpio { - rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - spi1 { - spi1_sleep: spi1-sleep { - /* - * Pull down SPI1 CLK/CS/RX/TX during suspend, to - * prevent leakage. - */ - rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_down>, - <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>, - <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>, - <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; - - touchscreen { - touch_int_l: touch-int-l { - rockchip,pins = <3 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - touch_reset_l: touch-reset-l { - rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - trackpad { - ap_i2c_tp_pu_en: ap-i2c-tp-pu-en { - rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_output_high>; - }; - - trackpad_int_l: trackpad-int-l { - rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - wifi: wifi { - wlan_module_reset_l: wlan-module-reset-l { - rockchip,pins = <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_host_wake_l: bt-host-wake-l { - /* Kevin has an external pull up, but Gru does not */ - rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - write-protect { - ap_fw_wp: ap-fw-wp { - rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/rockchip/rk3399-hugsun-x99.dts b/sys/gnu/dts/arm64/rockchip/rk3399-hugsun-x99.dts deleted file mode 100644 index d69a613fb65..00000000000 --- a/sys/gnu/dts/arm64/rockchip/rk3399-hugsun-x99.dts +++ /dev/null @@ -1,731 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/dts-v1/; -#include -#include -#include "rk3399.dtsi" -#include "rk3399-opp.dtsi" - -/ { - model = "Hugsun X99 TV BOX"; - compatible = "hugsun,x99", "rockchip,rk3399"; - - chosen { - stdout-path = "serial2:1500000n8"; - }; - - clkin_gmac: external-gmac-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "clkin_gmac"; - #clock-cells = <0>; - }; - - dc_5v: dc-5v { - compatible = "regulator-fixed"; - regulator-name = "dc_5v"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - vcc_sys: vcc-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - vin-supply = <&dc_5v>; - }; - - vcc_phy: vcc-phy-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_phy"; - regulator-always-on; - regulator-boot-on; - }; - - vcc1v8_s0: vcc1v8-s0 { - compatible = "regulator-fixed"; - regulator-name = "vcc1v8_s0"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vcc3v3_sys: vcc3v3-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_sys"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - vin-supply = <&vcc_sys>; - }; - - vcc5v0_host: vcc5v0-host-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&host_vbus_drv>; - regulator-name = "vcc5v0_host"; - regulator-always-on; - }; - - vcc5v0_typec: vcc5v0-typec-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_typec_en>; - regulator-name = "vcc5v0_typec"; - regulator-always-on; - vin-supply = <&vcc5v0_usb>; - }; - - vcc5v0_usb: vcc5v0-usb { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_usb"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&dc_5v>; - }; - - vdd_log: vdd-log { - compatible = "pwm-regulator"; - pwms = <&pwm2 0 25000 1>; - pwm-supply = <&vcc_sys>; - regulator-name = "vdd_log"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-boot-on; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&rk808 1>; - clock-names = "ext_clock"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_reg_on_h>; - reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; - }; - -}; - -&cpu_l0 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l1 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l2 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l3 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_b0 { - cpu-supply = <&vdd_cpu_b>; -}; - -&cpu_b1 { - cpu-supply = <&vdd_cpu_b>; -}; - -&emmc_phy { - status = "okay"; -}; - -&gmac { - assigned-clocks = <&cru SCLK_RMII_SRC>; - assigned-clock-parents = <&clkin_gmac>; - clock_in_out = "input"; - phy-supply = <&vcc_phy>; - phy-mode = "rgmii"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 50000>; - tx_delay = <0x28>; - rx_delay = <0x11>; - status = "okay"; -}; - -&gpu { - status = "okay"; - mali-supply = <&vdd_gpu>; -}; - -&hdmi { - ddc-i2c-bus = <&i2c3>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_cec>; - status = "okay"; -}; - -&hdmi_sound { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - i2c-scl-rising-time-ns = <180>; - i2c-scl-falling-time-ns = <30>; - clock-frequency = <400000>; - - vdd_cpu_b: syr827@40 { - compatible = "silergy,syr827"; - reg = <0x40>; - regulator-compatible = "fan53555-reg"; - pinctrl-0 = <&vsel1_gpio>; - regulator-name = "vdd_cpu_b"; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1500000>; - regulator-ramp-delay = <1000>; - fcs,suspend-voltage-selector = <1>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_sys>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_gpu: syr828@41 { - compatible = "silergy,syr828"; - reg = <0x41>; - regulator-compatible = "fan53555-reg"; - pinctrl-0 = <&vsel2_gpio>; - regulator-name = "vdd_gpu"; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1500000>; - regulator-ramp-delay = <1000>; - fcs,suspend-voltage-selector = <1>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_sys>; - regulator-initial-mode = <1>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - rk808: pmic@1b { - compatible = "rockchip,rk808"; - reg = <0x1b>; - interrupt-parent = <&gpio1>; - interrupts = <21 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l>; - rockchip,system-power-controller; - wakeup-source; - #clock-cells = <1>; - clock-output-names = "xin32k", "rtc_clko_wifi"; - - vcc1-supply = <&vcc_sys>; - vcc2-supply = <&vcc_sys>; - vcc3-supply = <&vcc_sys>; - vcc4-supply = <&vcc_sys>; - vcc6-supply = <&vcc_sys>; - vcc7-supply = <&vcc_sys>; - vcc8-supply = <&vcc3v3_sys>; - vcc9-supply = <&vcc_sys>; - vcc10-supply = <&vcc_sys>; - vcc11-supply = <&vcc_sys>; - vcc12-supply = <&vcc3v3_sys>; - vddio-supply = <&vcc_1v8>; - - regulators { - vdd_center: DCDC_REG1 { - regulator-name = "vdd_center"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - regulator-ramp-delay = <6001>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_l: DCDC_REG2 { - regulator-name = "vdd_cpu_l"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_1v8: DCDC_REG4 { - regulator-name = "vcc_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc1v8_dvp: LDO_REG1 { - regulator-name = "vcc1v8_dvp"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcca1v8_hdmi: LDO_REG2 { - regulator-name = "vcca1v8_hdmi"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcca_1v8: LDO_REG3 { - regulator-name = "vcca_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc_sd: LDO_REG4 { - regulator-name = "vcc_sd"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc3v0_sd: LDO_REG5 { - regulator-name = "vcc3v0_sd"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3000000>; - }; - }; - - vcc_1v5: LDO_REG6 { - regulator-name = "vcc_1v5"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1500000>; - }; - }; - - vcca0v9_hdmi: LDO_REG7 { - regulator-name = "vcca0v9_hdmi"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <900000>; - }; - }; - - vcc_3v0: LDO_REG8 { - regulator-name = "vcc_3v0"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3000000>; - }; - }; - - vcc3v3_s3: SWITCH_REG1 { - regulator-name = "vcc3v3_s3"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc3v3_s0: SWITCH_REG2 { - regulator-name = "vcc3v3_s0"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - }; - }; -}; - -&i2c1 { - i2c-scl-rising-time-ns = <300>; - i2c-scl-falling-time-ns = <15>; - status = "okay"; -}; - -&i2c3 { - i2c-scl-rising-time-ns = <450>; - i2c-scl-falling-time-ns = <15>; - status = "okay"; -}; - -&i2c4 { - i2c-scl-rising-time-ns = <600>; - i2c-scl-falling-time-ns = <40>; - status = "okay"; - - fusb0: typec-portc@22 { - compatible = "fcs,fusb302"; - reg = <0x22>; - interrupt-parent = <&gpio1>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&fusb0_int>; - vbus-supply = <&vcc5v0_typec>; - status = "okay"; - }; -}; - -&i2c7 { - status = "okay"; -}; - -&i2s0 { - rockchip,playback-channels = <8>; - rockchip,capture-channels = <8>; - status = "okay"; -}; - -&i2s1 { - rockchip,playback-channels = <2>; - rockchip,capture-channels = <2>; - status = "okay"; -}; - -&i2s2 { - status = "okay"; -}; - -&io_domains { - status = "okay"; - audio-supply = <&vcc1v8_s0>; - bt656-supply = <&vcc1v8_s0>; - gpio1830-supply = <&vcc_3v0>; - sdmmc-supply = <&vcc_sd>; -}; - -&pmu_io_domains { - status = "okay"; - pmu1830-supply = <&vcc_1v8>; -}; - -&pinctrl { - fusb30x { - fusb0_int: fusb0-int { - rockchip,pins = - <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - gmac { - rgmii_sleep_pins: rgmii-sleep-pins { - rockchip,pins = - <3 RK_PB7 RK_FUNC_GPIO &pcfg_output_low>; - }; - }; - - pmic { - pmic_int_l: pmic-int-l { - rockchip,pins = - <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - vsel1_gpio: vsel1-gpio { - rockchip,pins = - <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - vsel2_gpio: vsel2-gpio { - rockchip,pins = - <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; - - sdio { - bt_host_wake_l: bt-host-wake-l { - rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_reg_on_h: bt-reg-on-h { - /* external pullup to VCC1V8_PMUPLL */ - rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_wake_l: bt-wake-l { - rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - wifi_reg_on_h: wifi-reg_on-h { - rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - wifi { - wifi_host_wake_l: wifi-host-wake-l { - rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb-typec { - vcc5v0_typec_en: vcc5v0_typec_en { - rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - usb2 { - host_vbus_drv: host-vbus-drv { - rockchip,pins = - <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&pwm0 { - status = "okay"; -}; - -&pwm2 { - status = "okay"; - pinctrl-0 = <&pwm2_pin_pull_down>; -}; - -&saradc { - vref-supply = <&vcc1v8_s0>; - status = "okay"; -}; - -&sdmmc { - clock-frequency = <150000000>; - clock-freq-min-max = <200000 150000000>; - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - disable-wp; - vqmmc-supply = <&vcc_sd>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; - card-detect-delay = <800>; - status = "okay"; -}; - -&sdhci { - bus-width = <8>; - mmc-hs400-1_8v; - mmc-hs400-enhanced-strobe; - non-removable; - keep-power-in-suspend; - status = "okay"; -}; - -&sdio0 { - bus-width = <4>; - clock-frequency = <50000000>; - cap-sdio-irq; - cap-sd-highspeed; - keep-power-in-suspend; - mmc-pwrseq = <&sdio_pwrseq>; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; - sd-uhs-sdr104; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - brcmf: wifi@1 { - compatible = "brcm,bcm4329-fmac"; - reg = <1>; - interrupt-parent = <&gpio0>; - interrupts = ; - interrupt-names = "host-wake"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_host_wake_l>; - }; -}; - -&spdif { - status = "okay"; - pinctrl-0 = <&spdif_bus_1>; - #sound-dai-cells = <0>; -}; - -&spi1 { - status = "okay"; - max-freq = <10000000>; - - flash@0 { - compatible = "jedec,spi-nor"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0>; - spi-max-frequency = <10000000>; - }; -}; - -&tcphy0 { - status = "okay"; -}; - -&tcphy1 { - status = "okay"; -}; - -&tsadc { - /* tshut mode 0:CRU 1:GPIO */ - rockchip,hw-tshut-mode = <1>; - /* tshut polarity 0:LOW 1:HIGH */ - rockchip,hw-tshut-polarity = <1>; - rockchip,hw-tshut-temp = <110000>; - status = "okay"; -}; - -&u2phy0 { - status = "okay"; - - u2phy0_host: host-port { - phy-supply = <&vcc5v0_typec>; - status = "okay"; - }; - - u2phy0_otg: otg-port { - status = "okay"; - }; -}; - -&u2phy1 { - status = "okay"; - - u2phy1_host: host-port { - phy-supply = <&vcc5v0_host>; - status = "okay"; - }; - - u2phy1_otg: otg-port { - status = "okay"; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_rts &uart0_cts>; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - clocks = <&rk808 1>; - clock-names = "ext_clock"; - device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>; - host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; - shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; - max-speed = <4000000>; - pinctrl-names = "default"; - pinctrl-0 = <&bt_reg_on_h &bt_host_wake_l &bt_wake_l>; - vbat-supply = <&vcc3v3_sys>; - vddio-supply = <&vcc_1v8>; - }; -}; - -&uart2 { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - -&usbdrd3_0 { - status = "okay"; -}; - -&usbdrd_dwc3_0 { - status = "okay"; - dr_mode = "host"; -}; - -&usbdrd3_1 { - status = "okay"; -}; - -&usbdrd_dwc3_1 { - status = "okay"; - dr_mode = "host"; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/rockchip/rk3399-khadas-edge-captain.dts b/sys/gnu/dts/arm64/rockchip/rk3399-khadas-edge-captain.dts deleted file mode 100644 index 8302e51def5..00000000000 --- a/sys/gnu/dts/arm64/rockchip/rk3399-khadas-edge-captain.dts +++ /dev/null @@ -1,27 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 Shenzhen Wesion Technology Co., Ltd. - * (https://www.khadas.com) - */ - -/dts-v1/; -#include "rk3399-khadas-edge.dtsi" - -/ { - model = "Khadas Edge-Captain"; - compatible = "khadas,edge-captain", "rockchip,rk3399"; -}; - -&gmac { - status = "okay"; -}; - -&pcie_phy { - status = "okay"; -}; - -&pcie0 { - ep-gpios = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; - num-lanes = <4>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/rockchip/rk3399-khadas-edge-v.dts b/sys/gnu/dts/arm64/rockchip/rk3399-khadas-edge-v.dts deleted file mode 100644 index f5dcb99dc34..00000000000 --- a/sys/gnu/dts/arm64/rockchip/rk3399-khadas-edge-v.dts +++ /dev/null @@ -1,27 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 Shenzhen Wesion Technology Co., Ltd. - * (https://www.khadas.com) - */ - -/dts-v1/; -#include "rk3399-khadas-edge.dtsi" - -/ { - model = "Khadas Edge-V"; - compatible = "khadas,edge-v", "rockchip,rk3399"; -}; - -&gmac { - status = "okay"; -}; - -&pcie_phy { - status = "okay"; -}; - -&pcie0 { - ep-gpios = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; - num-lanes = <4>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/rockchip/rk3399-khadas-edge.dts b/sys/gnu/dts/arm64/rockchip/rk3399-khadas-edge.dts deleted file mode 100644 index 31616e7ad89..00000000000 --- a/sys/gnu/dts/arm64/rockchip/rk3399-khadas-edge.dts +++ /dev/null @@ -1,13 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 Shenzhen Wesion Technology Co., Ltd. - * (https://www.khadas.com) - */ - -/dts-v1/; -#include "rk3399-khadas-edge.dtsi" - -/ { - model = "Khadas Edge"; - compatible = "khadas,edge", "rockchip,rk3399"; -}; diff --git a/sys/gnu/dts/arm64/rockchip/rk3399-khadas-edge.dtsi b/sys/gnu/dts/arm64/rockchip/rk3399-khadas-edge.dtsi deleted file mode 100644 index e87a0447744..00000000000 --- a/sys/gnu/dts/arm64/rockchip/rk3399-khadas-edge.dtsi +++ /dev/null @@ -1,807 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 Shenzhen Wesion Technology Co., Ltd. - * (https://www.khadas.com) - */ - -/dts-v1/; -#include -#include -#include "rk3399.dtsi" -#include "rk3399-opp.dtsi" - -/ { - chosen { - stdout-path = "serial2:1500000n8"; - }; - - clkin_gmac: external-gmac-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "clkin_gmac"; - #clock-cells = <0>; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&rk808 1>; - clock-names = "ext_clock"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_enable_h>; - - /* - * On the module itself this is one of these (depending - * on the actual card populated): - * - SDIO_RESET_L_WL_REG_ON - * - PDN (power down when low) - */ - reset-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_LOW>; - }; - - /* switched by pmic_sleep */ - vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 { - compatible = "regulator-fixed"; - regulator-name = "vcc1v8_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_1v8>; - }; - - vcc3v3_pcie: vcc3v3-pcie-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_pcie"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vsys_3v3>; - }; - - /* Actually 3 regulators (host0, 1, 2) controlled by the same gpio */ - vcc5v0_host: vcc5v0-host-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_host_en>; - regulator-name = "vcc5v0_host"; - regulator-always-on; - vin-supply = <&vsys_5v0>; - }; - - vdd_log: vdd-log { - compatible = "pwm-regulator"; - pwms = <&pwm2 0 25000 1>; - regulator-name = "vdd_log"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - vin-supply = <&vsys_3v3>; - }; - - vsys: vsys { - compatible = "regulator-fixed"; - regulator-name = "vsys"; - regulator-always-on; - regulator-boot-on; - }; - - vsys_3v3: vsys-3v3 { - compatible = "regulator-fixed"; - regulator-name = "vsys_3v3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vsys>; - }; - - vsys_5v0: vsys-5v0 { - compatible = "regulator-fixed"; - regulator-name = "vsys_5v0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vsys>; - }; - - adc-keys { - compatible = "adc-keys"; - io-channels = <&saradc 1>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1800000>; - poll-interval = <100>; - - recovery { - label = "Recovery"; - linux,code = ; - press-threshold-microvolt = <18000>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - pinctrl-names = "default"; - pinctrl-0 = <&pwrbtn>; - - power { - debounce-interval = <100>; - gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; - label = "GPIO Key Power"; - linux,code = ; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&sys_led_gpio>, <&user_led_gpio>; - - sys-led { - label = "sys_led"; - linux,default-trigger = "heartbeat"; - gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; - }; - - user-led { - label = "user_led"; - default-state = "off"; - gpios = <&gpio4 RK_PD0 GPIO_ACTIVE_HIGH>; - }; - }; - - fan: pwm-fan { - compatible = "pwm-fan"; - cooling-levels = <0 150 200 255>; - #cooling-cells = <2>; - fan-supply = <&vsys_5v0>; - pwms = <&pwm0 0 40000 0>; - }; -}; - -&cpu_l0 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l1 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l2 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l3 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_b0 { - cpu-supply = <&vdd_cpu_b>; -}; - -&cpu_b1 { - cpu-supply = <&vdd_cpu_b>; -}; - -&cpu_thermal { - trips { - cpu_warm: cpu_warm { - temperature = <55000>; - hysteresis = <2000>; - type = "active"; - }; - - cpu_hot: cpu_hot { - temperature = <65000>; - hysteresis = <2000>; - type = "active"; - }; - }; - - cooling-maps { - map2 { - trip = <&cpu_warm>; - cooling-device = <&fan THERMAL_NO_LIMIT 1>; - }; - - map3 { - trip = <&cpu_hot>; - cooling-device = <&fan 2 THERMAL_NO_LIMIT>; - }; - }; -}; - -&emmc_phy { - status = "okay"; -}; - -&gmac { - assigned-clocks = <&cru SCLK_RMII_SRC>; - assigned-clock-parents = <&clkin_gmac>; - clock_in_out = "input"; - phy-supply = <&vcc_lan>; - phy-mode = "rgmii"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 50000>; - tx_delay = <0x28>; - rx_delay = <0x11>; -}; - -&gpu { - mali-supply = <&vdd_gpu>; - status = "okay"; -}; - -&gpu_thermal { - trips { - gpu_warm: gpu_warm { - temperature = <55000>; - hysteresis = <2000>; - type = "active"; - }; - - gpu_hot: gpu_hot { - temperature = <65000>; - hysteresis = <2000>; - type = "active"; - }; - }; - - cooling-maps { - map1 { - trip = <&gpu_warm>; - cooling-device = <&fan THERMAL_NO_LIMIT 1>; - }; - - map2 { - trip = <&gpu_hot>; - cooling-device = <&fan 2 THERMAL_NO_LIMIT>; - }; - }; -}; - -&hdmi { - ddc-i2c-bus = <&i2c3>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_cec>; - status = "okay"; -}; - -&hdmi_sound { - status = "okay"; -}; - -&i2c3 { - i2c-scl-rising-time-ns = <450>; - i2c-scl-falling-time-ns = <15>; - status = "okay"; -}; - -&i2c4 { - clock-frequency = <400000>; - i2c-scl-rising-time-ns = <168>; - i2c-scl-falling-time-ns = <4>; - status = "okay"; - - rk808: pmic@1b { - compatible = "rockchip,rk808"; - reg = <0x1b>; - interrupt-parent = <&gpio1>; - interrupts = ; - #clock-cells = <1>; - clock-output-names = "xin32k", "rk808-clkout2"; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l>; - rockchip,system-power-controller; - wakeup-source; - - vcc1-supply = <&vsys_3v3>; - vcc2-supply = <&vsys_3v3>; - vcc3-supply = <&vsys_3v3>; - vcc4-supply = <&vsys_3v3>; - vcc6-supply = <&vsys_3v3>; - vcc7-supply = <&vsys_3v3>; - vcc8-supply = <&vsys_3v3>; - vcc9-supply = <&vsys_3v3>; - vcc10-supply = <&vsys_3v3>; - vcc11-supply = <&vsys_3v3>; - vcc12-supply = <&vsys_3v3>; - vddio-supply = <&vcc_1v8>; - - regulators { - vdd_center: DCDC_REG1 { - regulator-name = "vdd_center"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_l: DCDC_REG2 { - regulator-name = "vdd_cpu_l"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_1v8: DCDC_REG4 { - regulator-name = "vcc_1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc1v8_apio2: LDO_REG1 { - regulator-name = "vcc1v8_apio2"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_vldo2: LDO_REG2 { - regulator-name = "vcc_vldo2"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc1v8_pmupll: LDO_REG3 { - regulator-name = "vcc1v8_pmupll"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vccio_sd: LDO_REG4 { - regulator-name = "vccio_sd"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3000000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3000000>; - }; - }; - - vcc_vldo5: LDO_REG5 { - regulator-name = "vcc_vldo5"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v5: LDO_REG6 { - regulator-name = "vcc_1v5"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1500000>; - }; - }; - - vcc1v8_codec: LDO_REG7 { - regulator-name = "vcc1v8_codec"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_3v0: LDO_REG8 { - regulator-name = "vcc_3v0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3000000>; - }; - }; - - vcc3v3_s3: vcc_lan: SWITCH_REG1 { - regulator-name = "vcc3v3_s3"; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v3_s0: SWITCH_REG2 { - regulator-name = "vcc3v3_s0"; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; - - vdd_cpu_b: regulator@40 { - compatible = "silergy,syr827"; - reg = <0x40>; - fcs,suspend-voltage-selector = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&cpu_b_sleep>; - regulator-name = "vdd_cpu_b"; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1500000>; - regulator-ramp-delay = <1000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vsys_3v3>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_gpu: regulator@41 { - compatible = "silergy,syr828"; - reg = <0x41>; - fcs,suspend-voltage-selector = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&gpu_sleep>; - regulator-name = "vdd_gpu"; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1500000>; - regulator-ramp-delay = <1000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vsys_3v3>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&i2c8 { - clock-frequency = <400000>; - i2c-scl-rising-time-ns = <160>; - i2c-scl-falling-time-ns = <30>; - status = "okay"; -}; - -&i2s0 { - rockchip,playback-channels = <8>; - rockchip,capture-channels = <8>; - status = "okay"; -}; - -&i2s1 { - rockchip,playback-channels = <2>; - rockchip,capture-channels = <2>; - status = "okay"; -}; - -&i2s2 { - status = "okay"; -}; - -&io_domains { - bt656-supply = <&vcc1v8_apio2>; - audio-supply = <&vcc1v8_codec>; - sdmmc-supply = <&vccio_sd>; - gpio1830-supply = <&vcc_3v0>; - status = "okay"; -}; - -&pmu_io_domains { - pmu1830-supply = <&vcc_1v8>; - status = "okay"; -}; - -&pinctrl { - bt { - bt_host_wake_l: bt-host-wake-l { - rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_reg_on_h: bt-reg-on-h { - rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_wake_l: bt-wake-l { - rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - buttons { - pwrbtn: pwrbtn { - rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - leds { - sys_led_gpio: sys_led-gpio { - rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - user_led_gpio: user_led-gpio { - rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - pmic_int_l: pmic-int-l { - rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - cpu_b_sleep: cpu-b-sleep { - rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - gpu_sleep: gpu-sleep { - rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; - - sdio-pwrseq { - wifi_enable_h: wifi-enable-h { - rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb2 { - vcc5v0_host_en: vcc5v0-host-en { - rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - wifi { - wifi_host_wake_l: wifi-host-wake-l { - rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&pwm0 { - status = "okay"; -}; - -&pwm2 { - status = "okay"; -}; - -&saradc { - vref-supply = <&vcca1v8_s3>; - status = "okay"; -}; - -&sdio0 { - /* WiFi & BT combo module Ampak AP6356S */ - bus-width = <4>; - cap-sdio-irq; - cap-sd-highspeed; - keep-power-in-suspend; - mmc-pwrseq = <&sdio_pwrseq>; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; - sd-uhs-sdr104; - vqmmc-supply = <&vcc1v8_s3>; - vmmc-supply = <&vccio_sd>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - interrupt-parent = <&gpio0>; - interrupts = ; - interrupt-names = "host-wake"; - brcm,drive-strength = <5>; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_host_wake_l>; - }; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; - disable-wp; - max-frequency = <150000000>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; - status = "okay"; -}; - -&sdhci { - bus-width = <8>; - mmc-hs400-1_8v; - mmc-hs400-enhanced-strobe; - non-removable; - status = "okay"; -}; - -&tcphy0 { - status = "okay"; -}; - -&tcphy1 { - status = "okay"; -}; - -&tsadc { - /* tshut mode 0:CRU 1:GPIO */ - rockchip,hw-tshut-mode = <1>; - /* tshut polarity 0:LOW 1:HIGH */ - rockchip,hw-tshut-polarity = <1>; - status = "okay"; -}; - -&u2phy0 { - status = "okay"; - - u2phy0_otg: otg-port { - status = "okay"; - }; - - u2phy0_host: host-port { - phy-supply = <&vcc5v0_host>; - status = "okay"; - }; -}; - -&u2phy1 { - status = "okay"; - - u2phy1_otg: otg-port { - status = "okay"; - }; - - u2phy1_host: host-port { - phy-supply = <&vcc5v0_host>; - status = "okay"; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_rts &uart0_cts>; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - clocks = <&rk808 1>; - clock-names = "lpo"; - device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>; - host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; - shutdown-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; - max-speed = <4000000>; - pinctrl-names = "default"; - pinctrl-0 = <&bt_reg_on_h &bt_host_wake_l &bt_wake_l>; - vbat-supply = <&vsys_3v3>; - vddio-supply = <&vcc_1v8>; - }; -}; - -&uart2 { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - -&usbdrd3_0 { - status = "okay"; -}; - -&usbdrd_dwc3_0 { - status = "okay"; - dr_mode = "otg"; -}; - -&usbdrd3_1 { - status = "okay"; -}; - -&usbdrd_dwc3_1 { - status = "okay"; - dr_mode = "host"; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&vopl { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/rockchip/rk3399-leez-p710.dts b/sys/gnu/dts/arm64/rockchip/rk3399-leez-p710.dts deleted file mode 100644 index 73be38a5379..00000000000 --- a/sys/gnu/dts/arm64/rockchip/rk3399-leez-p710.dts +++ /dev/null @@ -1,645 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 Andy Yan - */ - -/dts-v1/; -#include -#include -#include "rk3399.dtsi" -#include "rk3399-opp.dtsi" - -/ { - model = "Leez RK3399 P710"; - compatible = "leez,p710", "rockchip,rk3399"; - - chosen { - stdout-path = "serial2:1500000n8"; - }; - - clkin_gmac: external-gmac-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "clkin_gmac"; - #clock-cells = <0>; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&rk808 1>; - clock-names = "ext_clock"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_reg_on_h>; - reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; - }; - - dc5v_adp: dc5v-adp { - compatible = "regulator-fixed"; - regulator-name = "dc5v_adapter"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - vcc3v3_lan: vcc3v3-lan { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_lan"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vim-supply = <&vcc3v3_sys>; - }; - - vcc3v3_sys: vcc3v3-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc5v0_sys>; - }; - - vcc5v0_host0: vcc5v0_host1: vcc5v0-host { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_host"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <5500000>; - regulator-max-microvolt = <5500000>; - vin-supply = <&vcc5v0_sys>; - }; - - vcc5v0_host3: vcc5v0-host3 { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_host3"; - enable-active-high; - gpio = <&gpio2 RK_PA2 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_host3_en>; - regulator-always-on; - vin-supply = <&vcc5v0_sys>; - }; - - vcc5v0_sys: vcc5v0-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&dc5v_adp>; - }; - - vdd_log: vdd-log { - compatible = "pwm-regulator"; - pwms = <&pwm2 0 25000 1>; - regulator-name = "vdd_log"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - vin-supply = <&vcc5v0_sys>; - }; -}; - -&cpu_l0 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l1 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l2 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l3 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_b0 { - cpu-supply = <&vdd_cpu_b>; -}; - -&cpu_b1 { - cpu-supply = <&vdd_cpu_b>; -}; - -&emmc_phy { - status = "okay"; -}; - -&gmac { - assigned-clocks = <&cru SCLK_RMII_SRC>; - assigned-clock-parents = <&clkin_gmac>; - clock_in_out = "input"; - phy-supply = <&vcc3v3_lan>; - phy-mode = "rgmii"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 50000>; - tx_delay = <0x28>; - rx_delay = <0x11>; - status = "okay"; -}; - -&gpu { - mali-supply = <&vdd_gpu>; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c7>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_cec>; - status = "okay"; -}; - -&hdmi_sound { - status = "okay"; -}; - -&i2c0 { - clock-frequency = <400000>; - i2c-scl-rising-time-ns = <168>; - i2c-scl-falling-time-ns = <4>; - status = "okay"; - - rk808: pmic@1b { - compatible = "rockchip,rk808"; - reg = <0x1b>; - interrupt-parent = <&gpio1>; - interrupts = <21 IRQ_TYPE_LEVEL_LOW>; - #clock-cells = <1>; - clock-output-names = "xin32k", "rk808-clkout2"; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l>; - rockchip,system-power-controller; - wakeup-source; - - vcc1-supply = <&vcc5v0_sys>; - vcc2-supply = <&vcc5v0_sys>; - vcc3-supply = <&vcc5v0_sys>; - vcc4-supply = <&vcc5v0_sys>; - vcc6-supply = <&vcc5v0_sys>; - vcc7-supply = <&vcc5v0_sys>; - vcc8-supply = <&vcc3v3_sys>; - vcc9-supply = <&vcc5v0_sys>; - vcc10-supply = <&vcc5v0_sys>; - vcc11-supply = <&vcc5v0_sys>; - vcc12-supply = <&vcc3v3_sys>; - vddio-supply = <&vcc_1v8>; - - regulators { - vdd_center: DCDC_REG1 { - regulator-name = "vdd_center"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_l: DCDC_REG2 { - regulator-name = "vdd_cpu_l"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_1v8: DCDC_REG4 { - regulator-name = "vcc_1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc1v8_dvp: LDO_REG1 { - regulator-name = "vcc1v8_dvp"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc1v8_hdmi: LDO_REG2 { - regulator-name = "vcc1v8_hdmi"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcca_1v8: LDO_REG3 { - regulator-name = "vcca_1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vccio_sd: LDO_REG4 { - regulator-name = "vccio_sd"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3000000>; - }; - }; - - vcca3v0_codec: LDO_REG5 { - regulator-name = "vcca3v0_codec"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v5: LDO_REG6 { - regulator-name = "vcc_1v5"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1500000>; - }; - }; - - vcc0v9_hdmi: LDO_REG7 { - regulator-name = "vcc0v9_hdmi"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_3v0: LDO_REG8 { - regulator-name = "vcc_3v0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3000000>; - }; - }; - }; - }; - - vdd_cpu_b: regulator@40 { - compatible = "silergy,syr827"; - reg = <0x40>; - fcs,suspend-voltage-selector = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&vsel1_gpio>; - regulator-name = "vdd_cpu_b"; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1500000>; - regulator-ramp-delay = <1000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_gpu: regulator@41 { - compatible = "silergy,syr828"; - reg = <0x41>; - fcs,suspend-voltage-selector = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&vsel2_gpio>; - regulator-name = "vdd_gpu"; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1500000>; - regulator-ramp-delay = <1000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&i2c1 { - i2c-scl-rising-time-ns = <300>; - i2c-scl-falling-time-ns = <15>; - status = "okay"; -}; - -&i2c3 { - i2c-scl-rising-time-ns = <450>; - i2c-scl-falling-time-ns = <15>; - status = "okay"; -}; - -&i2c4 { - i2c-scl-rising-time-ns = <600>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; -}; - -&i2c7 { - status = "okay"; -}; - -&i2s0 { - rockchip,playback-channels = <8>; - rockchip,capture-channels = <8>; - status = "okay"; -}; - -&i2s1 { - rockchip,playback-channels = <2>; - rockchip,capture-channels = <2>; - status = "okay"; -}; - -&i2s2 { - status = "okay"; -}; - -&io_domains { - status = "okay"; - - bt656-supply = <&vcc1v8_dvp>; - audio-supply = <&vcc_1v8>; - sdmmc-supply = <&vccio_sd>; - gpio1830-supply = <&vcc_3v0>; -}; - -&pmu_io_domains { - status = "okay"; - pmu1830-supply = <&vcc_3v0>; -}; - -&pinctrl { - bt { - bt_reg_on_h: bt-reg-on-h { - rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_host_wake_l: bt-host-wake-l { - rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_wake_l: bt-wake-l { - rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - pmic_int_l: pmic-int-l { - rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - vsel1_gpio: vsel1-gpio { - rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - vsel2_gpio: vsel2-gpio { - rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; - - usb2 { - vcc5v0_host3_en: vcc5v0-host3-en { - rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - wifi { - wifi_reg_on_h: wifi-reg-on-h { - rockchip,pins = - <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - wifi_host_wake_l: wifi-host-wake-l { - rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&pwm2 { - status = "okay"; -}; - -&saradc { - status = "okay"; - - vref-supply = <&vcc_1v8>; -}; - -&sdio0 { - #address-cells = <1>; - #size-cells = <0>; - bus-width = <4>; - clock-frequency = <50000000>; - cap-sdio-irq; - cap-sd-highspeed; - keep-power-in-suspend; - mmc-pwrseq = <&sdio_pwrseq>; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; - sd-uhs-sdr104; - status = "okay"; - - brcmf: wifi@1 { - compatible = "brcm,bcm4329-fmac"; - reg = <1>; - interrupt-parent = <&gpio0>; - interrupts = ; - interrupt-names = "host-wake"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_host_wake_l>; - }; -}; - -&sdhci { - bus-width = <8>; - mmc-hs400-1_8v; - mmc-hs400-enhanced-strobe; - non-removable; - status = "okay"; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; - disable-wp; - max-frequency = <150000000>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cd &sdmmc_cmd &sdmmc_bus4>; - status = "okay"; -}; - -&tcphy0 { - status = "okay"; -}; - -&tcphy1 { - status = "okay"; -}; - -&tsadc { - status = "okay"; - - /* tshut mode 0:CRU 1:GPIO */ - rockchip,hw-tshut-mode = <1>; - /* tshut polarity 0:LOW 1:HIGH */ - rockchip,hw-tshut-polarity = <1>; -}; - -&u2phy0 { - status = "okay"; - - u2phy0_otg: otg-port { - status = "okay"; - }; - - u2phy0_host: host-port { - phy-supply = <&vcc5v0_host0>; - status = "okay"; - }; -}; - -&u2phy1 { - status = "okay"; - - u2phy1_otg: otg-port { - status = "okay"; - }; - - u2phy1_host: host-port { - phy-supply = <&vcc5v0_host1>; - status = "okay"; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - clocks = <&rk808 1>; - clock-names = "ext_clock"; - device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>; - host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; - shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_reg_on_h>; - }; -}; - -&uart2 { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - -&usbdrd3_0 { - status = "okay"; -}; - -&usbdrd_dwc3_0 { - status = "okay"; - dr_mode = "otg"; -}; - -&usbdrd3_1 { - status = "okay"; -}; - -&usbdrd_dwc3_1 { - status = "okay"; - dr_mode = "host"; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&vopl { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/rockchip/rk3399-nanopc-t4.dts b/sys/gnu/dts/arm64/rockchip/rk3399-nanopc-t4.dts deleted file mode 100644 index e0d75617bb7..00000000000 --- a/sys/gnu/dts/arm64/rockchip/rk3399-nanopc-t4.dts +++ /dev/null @@ -1,136 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * FriendlyElec NanoPC-T4 board device tree source - * - * Copyright (c) 2018 FriendlyElec Computer Tech. Co., Ltd. - * (http://www.friendlyarm.com) - * - * Copyright (c) 2018 Collabora Ltd. - */ - -/dts-v1/; -#include "rk3399-nanopi4.dtsi" - -/ { - model = "FriendlyElec NanoPC-T4"; - compatible = "friendlyarm,nanopc-t4", "rockchip,rk3399"; - - vcc12v0_sys: vcc12v0-sys { - compatible = "regulator-fixed"; - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <12000000>; - regulator-min-microvolt = <12000000>; - regulator-name = "vcc12v0_sys"; - }; - - vcc5v0_host0: vcc5v0-host0 { - compatible = "regulator-fixed"; - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc5v0_host0"; - vin-supply = <&vcc5v0_sys>; - }; - - adc-keys { - compatible = "adc-keys"; - io-channels = <&saradc 1>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1800000>; - poll-interval = <100>; - - recovery { - label = "Recovery"; - linux,code = ; - press-threshold-microvolt = <18000>; - }; - }; - - ir-receiver { - compatible = "gpio-ir-receiver"; - gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&ir_rx>; - }; - - fan: pwm-fan { - compatible = "pwm-fan"; - /* - * With 20KHz PWM and an EVERCOOL EC4007H12SA fan, these levels - * work out to 0, ~1200, ~3000, and 5000RPM respectively. - */ - cooling-levels = <0 12 18 255>; - #cooling-cells = <2>; - fan-supply = <&vcc12v0_sys>; - pwms = <&pwm1 0 50000 0>; - }; -}; - -&cpu_thermal { - trips { - cpu_warm: cpu_warm { - temperature = <55000>; - hysteresis = <2000>; - type = "active"; - }; - - cpu_hot: cpu_hot { - temperature = <65000>; - hysteresis = <2000>; - type = "active"; - }; - }; - - cooling-maps { - map2 { - trip = <&cpu_warm>; - cooling-device = <&fan THERMAL_NO_LIMIT 1>; - }; - - map3 { - trip = <&cpu_hot>; - cooling-device = <&fan 2 THERMAL_NO_LIMIT>; - }; - }; -}; - -&pcie0 { - num-lanes = <4>; - vpcie3v3-supply = <&vcc3v3_sys>; -}; - -&pinctrl { - ir { - ir_rx: ir-rx { - /* external pullup to VCC3V3_SYS, despite being 1.8V :/ */ - rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>; - }; - }; -}; - -&sdhci { - mmc-hs400-1_8v; - mmc-hs400-enhanced-strobe; -}; - -&u2phy0_host { - phy-supply = <&vcc5v0_host0>; -}; - -&u2phy1_host { - phy-supply = <&vcc5v0_host0>; -}; - -&vcc5v0_sys { - vin-supply = <&vcc12v0_sys>; -}; - -&vcc3v3_sys { - vin-supply = <&vcc12v0_sys>; -}; - -&vbus_typec { - enable-active-high; - gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; - vin-supply = <&vcc5v0_sys>; -}; diff --git a/sys/gnu/dts/arm64/rockchip/rk3399-nanopi-m4.dts b/sys/gnu/dts/arm64/rockchip/rk3399-nanopi-m4.dts deleted file mode 100644 index 60358ab8c7d..00000000000 --- a/sys/gnu/dts/arm64/rockchip/rk3399-nanopi-m4.dts +++ /dev/null @@ -1,66 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * FriendlyElec NanoPi M4 board device tree source - * - * Copyright (c) 2018 FriendlyElec Computer Tech. Co., Ltd. - * (http://www.friendlyarm.com) - * - * Copyright (c) 2018 Collabora Ltd. - * Copyright (c) 2019 Arm Ltd. - */ - -/dts-v1/; -#include "rk3399-nanopi4.dtsi" - -/ { - model = "FriendlyElec NanoPi M4"; - compatible = "friendlyarm,nanopi-m4", "rockchip,rk3399"; - - vdd_5v: vdd-5v { - compatible = "regulator-fixed"; - regulator-name = "vdd_5v"; - regulator-always-on; - regulator-boot-on; - }; - - vcc5v0_core: vcc5v0-core { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_core"; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vdd_5v>; - }; - - vcc5v0_usb1: vcc5v0-usb1 { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_usb1"; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc5v0_sys>; - }; - - vcc5v0_usb2: vcc5v0-usb2 { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_usb2"; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc5v0_sys>; - }; -}; - -&vcc3v3_sys { - vin-supply = <&vcc5v0_core>; -}; - -&u2phy0_host { - phy-supply = <&vcc5v0_usb1>; -}; - -&u2phy1_host { - phy-supply = <&vcc5v0_usb2>; -}; - -&vbus_typec { - regulator-always-on; - vin-supply = <&vdd_5v>; -}; diff --git a/sys/gnu/dts/arm64/rockchip/rk3399-nanopi-neo4.dts b/sys/gnu/dts/arm64/rockchip/rk3399-nanopi-neo4.dts deleted file mode 100644 index 195410b089b..00000000000 --- a/sys/gnu/dts/arm64/rockchip/rk3399-nanopi-neo4.dts +++ /dev/null @@ -1,50 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2019 Amarula Solutions B.V. - * Author: Jagan Teki - */ - -/dts-v1/; - -#include "rk3399-nanopi4.dtsi" - -/ { - model = "FriendlyARM NanoPi NEO4"; - compatible = "friendlyarm,nanopi-neo4", "rockchip,rk3399"; - - vdd_5v: vdd-5v { - compatible = "regulator-fixed"; - regulator-name = "vdd_5v"; - regulator-always-on; - regulator-boot-on; - }; - - vcc5v0_core: vcc5v0-core { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_core"; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vdd_5v>; - }; - - vcc5v0_usb1: vcc5v0-usb1 { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_usb1"; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc5v0_sys>; - }; -}; - -&vcc3v3_sys { - vin-supply = <&vcc5v0_core>; -}; - -&u2phy0_host { - phy-supply = <&vcc5v0_usb1>; -}; - -&vbus_typec { - regulator-always-on; - vin-supply = <&vdd_5v>; -}; diff --git a/sys/gnu/dts/arm64/rockchip/rk3399-nanopi4.dtsi b/sys/gnu/dts/arm64/rockchip/rk3399-nanopi4.dtsi deleted file mode 100644 index c88018a0ef3..00000000000 --- a/sys/gnu/dts/arm64/rockchip/rk3399-nanopi4.dtsi +++ /dev/null @@ -1,757 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * RK3399-based FriendlyElec boards device tree source - * - * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd - * - * Copyright (c) 2018 FriendlyElec Computer Tech. Co., Ltd. - * (http://www.friendlyarm.com) - * - * Copyright (c) 2018 Collabora Ltd. - * Copyright (c) 2019 Arm Ltd. - */ - -/dts-v1/; -#include -#include "rk3399.dtsi" -#include "rk3399-opp.dtsi" - -/ { - chosen { - stdout-path = "serial2:1500000n8"; - }; - - clkin_gmac: external-gmac-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "clkin_gmac"; - #clock-cells = <0>; - }; - - vcc3v3_sys: vcc3v3-sys { - compatible = "regulator-fixed"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc3v3_sys"; - }; - - vcc5v0_sys: vcc5v0-sys { - compatible = "regulator-fixed"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-name = "vcc5v0_sys"; - vin-supply = <&vdd_5v>; - }; - - /* switched by pmic_sleep */ - vcc1v8_s3: vcc1v8-s3 { - compatible = "regulator-fixed"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc1v8_s3"; - vin-supply = <&vcc_1v8>; - }; - - vcc3v0_sd: vcc3v0-sd { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc0_pwr_h>; - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc3v0_sd"; - vin-supply = <&vcc3v3_sys>; - }; - - /* - * Really, this is supplied by vcc_1v8, and vcc1v8_s3 only - * drives the enable pin, but we can't quite model that. - */ - vcca0v9_s3: vcca0v9-s3 { - compatible = "regulator-fixed"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - regulator-name = "vcca0v9_s3"; - vin-supply = <&vcc1v8_s3>; - }; - - /* As above, actually supplied by vcc3v3_sys */ - vcca1v8_s3: vcca1v8-s3 { - compatible = "regulator-fixed"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcca1v8_s3"; - vin-supply = <&vcc1v8_s3>; - }; - - vbus_typec: vbus-typec { - compatible = "regulator-fixed"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-name = "vbus_typec"; - }; - - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - pinctrl-names = "default"; - pinctrl-0 = <&power_key>; - - power { - debounce-interval = <100>; - gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; - label = "GPIO Key Power"; - linux,code = ; - wakeup-source; - }; - }; - - leds: gpio-leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&leds_gpio>; - - status { - gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; - label = "status_led"; - linux,default-trigger = "heartbeat"; - }; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&rk808 1>; - clock-names = "ext_clock"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_reg_on_h>; - reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; - }; -}; - -&cpu_b0 { - cpu-supply = <&vdd_cpu_b>; -}; - -&cpu_b1 { - cpu-supply = <&vdd_cpu_b>; -}; - -&cpu_l0 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l1 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l2 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l3 { - cpu-supply = <&vdd_cpu_l>; -}; - -&emmc_phy { - status = "okay"; -}; - -&gmac { - assigned-clock-parents = <&clkin_gmac>; - assigned-clocks = <&cru SCLK_RMII_SRC>; - clock_in_out = "input"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>, <&phy_intb>, <&phy_rstb>; - phy-handle = <&rtl8211e>; - phy-mode = "rgmii"; - phy-supply = <&vcc3v3_s3>; - tx_delay = <0x28>; - rx_delay = <0x11>; - status = "okay"; - - mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - rtl8211e: phy@1 { - reg = <1>; - interrupt-parent = <&gpio3>; - interrupts = ; - reset-assert-us = <10000>; - reset-deassert-us = <30000>; - reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&gpu { - mali-supply = <&vdd_gpu>; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c7>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_cec>; - status = "okay"; -}; - -&hdmi_sound { - status = "okay"; -}; - -&i2c0 { - clock-frequency = <400000>; - i2c-scl-rising-time-ns = <160>; - i2c-scl-falling-time-ns = <30>; - status = "okay"; - - vdd_cpu_b: regulator@40 { - compatible = "silergy,syr827"; - reg = <0x40>; - fcs,suspend-voltage-selector = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&cpu_b_sleep>; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1500000>; - regulator-name = "vdd_cpu_b"; - regulator-ramp-delay = <1000>; - vin-supply = <&vcc3v3_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_gpu: regulator@41 { - compatible = "silergy,syr828"; - reg = <0x41>; - fcs,suspend-voltage-selector = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&gpu_sleep>; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1500000>; - regulator-name = "vdd_gpu"; - regulator-ramp-delay = <1000>; - vin-supply = <&vcc3v3_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - rk808: pmic@1b { - compatible = "rockchip,rk808"; - reg = <0x1b>; - clock-output-names = "xin32k", "rtc_clko_wifi"; - #clock-cells = <1>; - interrupt-parent = <&gpio1>; - interrupts = <21 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l>; - rockchip,system-power-controller; - wakeup-source; - - vcc1-supply = <&vcc3v3_sys>; - vcc2-supply = <&vcc3v3_sys>; - vcc3-supply = <&vcc3v3_sys>; - vcc4-supply = <&vcc3v3_sys>; - vcc6-supply = <&vcc3v3_sys>; - vcc7-supply = <&vcc3v3_sys>; - vcc8-supply = <&vcc3v3_sys>; - vcc9-supply = <&vcc3v3_sys>; - vcc10-supply = <&vcc3v3_sys>; - vcc11-supply = <&vcc3v3_sys>; - vcc12-supply = <&vcc3v3_sys>; - vddio-supply = <&vcc_3v0>; - - regulators { - vdd_center: DCDC_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-name = "vdd_center"; - regulator-ramp-delay = <6001>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_l: DCDC_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-name = "vdd_cpu_l"; - regulator-ramp-delay = <6001>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc_ddr"; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_1v8: DCDC_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc_1v8"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc1v8_cam: LDO_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc1v8_cam"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v0_touch: LDO_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc3v0_touch"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc1v8_pmupll: LDO_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc1v8_pmupll"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc_sdio: LDO_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-init-microvolt = <3000000>; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc_sdio"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3000000>; - }; - }; - - vcca3v0_codec: LDO_REG5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcca3v0_codec"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v5: LDO_REG6 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vcc_1v5"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1500000>; - }; - }; - - vcca1v8_codec: LDO_REG7 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcca1v8_codec"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_3v0: LDO_REG8 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc_3v0"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3000000>; - }; - }; - - vcc3v3_s3: SWITCH_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc3v3_s3"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v3_s0: SWITCH_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc3v3_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; -}; - -&i2c1 { - clock-frequency = <200000>; - i2c-scl-rising-time-ns = <150>; - i2c-scl-falling-time-ns = <30>; - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c4 { - clock-frequency = <400000>; - i2c-scl-rising-time-ns = <160>; - i2c-scl-falling-time-ns = <30>; - status = "okay"; - - fusb0: typec-portc@22 { - compatible = "fcs,fusb302"; - reg = <0x22>; - interrupt-parent = <&gpio1>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&fusb0_int>; - vbus-supply = <&vbus_typec>; - }; -}; - -&i2c7 { - status = "okay"; -}; - -&i2s2 { - status = "okay"; -}; - -&io_domains { - bt656-supply = <&vcc_1v8>; - audio-supply = <&vcca1v8_codec>; - sdmmc-supply = <&vcc_sdio>; - gpio1830-supply = <&vcc_3v0>; - status = "okay"; -}; - -&pcie_phy { - assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>; - assigned-clock-rates = <100000000>; - assigned-clocks = <&cru SCLK_PCIEPHY_REF>; - status = "okay"; -}; - -&pcie0 { - ep-gpios = <&gpio2 RK_PA4 GPIO_ACTIVE_HIGH>; - max-link-speed = <2>; - num-lanes = <2>; - vpcie0v9-supply = <&vcca0v9_s3>; - vpcie1v8-supply = <&vcca1v8_s3>; - status = "okay"; -}; - -&pinctrl { - fusb30x { - fusb0_int: fusb0-int { - rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - gpio-leds { - leds_gpio: leds-gpio { - rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - phy { - phy_intb: phy-intb { - rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - phy_rstb: phy-rstb { - rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - cpu_b_sleep: cpu-b-sleep { - rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - gpu_sleep: gpu-sleep { - rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - pmic_int_l: pmic-int-l { - rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - rockchip-key { - power_key: power-key { - rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - sdio { - bt_host_wake_l: bt-host-wake-l { - rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_reg_on_h: bt-reg-on-h { - /* external pullup to VCC1V8_PMUPLL */ - rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_wake_l: bt-wake-l { - rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - wifi_reg_on_h: wifi-reg_on-h { - rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - sdmmc { - sdmmc0_det_l: sdmmc0-det-l { - rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - sdmmc0_pwr_h: sdmmc0-pwr-h { - rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&pmu_io_domains { - pmu1830-supply = <&vcc_3v0>; - status = "okay"; -}; - -&pwm0 { - status = "okay"; -}; - -&pwm1 { - status = "okay"; -}; - -&pwm2 { - pinctrl-names = "active"; - pinctrl-0 = <&pwm2_pin_pull_down>; - status = "okay"; -}; - -&saradc { - vref-supply = <&vcca1v8_s3>; - status = "okay"; -}; - -&sdhci { - bus-width = <8>; - mmc-hs200-1_8v; - non-removable; - status = "okay"; -}; - -&sdio0 { - bus-width = <4>; - cap-sd-highspeed; - cap-sdio-irq; - keep-power-in-suspend; - mmc-pwrseq = <&sdio_pwrseq>; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; - sd-uhs-sdr104; - status = "okay"; -}; - -&sdmmc { - bus-width = <4>; - cap-sd-highspeed; - cap-mmc-highspeed; - cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; - disable-wp; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc0_det_l>; - sd-uhs-sdr104; - vmmc-supply = <&vcc3v0_sd>; - vqmmc-supply = <&vcc_sdio>; - status = "okay"; -}; - -&tcphy0 { - status = "okay"; -}; - -&tcphy1 { - status = "okay"; -}; - -&tsadc { - /* tshut mode 0:CRU 1:GPIO */ - rockchip,hw-tshut-mode = <1>; - /* tshut polarity 0:LOW 1:HIGH */ - rockchip,hw-tshut-polarity = <1>; - status = "okay"; -}; - -&u2phy0 { - status = "okay"; -}; - -&u2phy0_host { - status = "okay"; -}; - -&u2phy0_otg { - status = "okay"; -}; - -&u2phy1 { - status = "okay"; -}; - -&u2phy1_host { - status = "okay"; -}; - -&u2phy1_otg { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_rts &uart0_cts>; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - clocks = <&rk808 1>; - clock-names = "lpo"; - device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>; - host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; - shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; - max-speed = <4000000>; - pinctrl-names = "default"; - pinctrl-0 = <&bt_reg_on_h &bt_host_wake_l &bt_wake_l>; - vbat-supply = <&vcc3v3_sys>; - vddio-supply = <&vcc_1v8>; - }; -}; - -&uart2 { - status = "okay"; -}; - -&usbdrd3_0 { - status = "okay"; -}; - -&usbdrd3_1 { - status = "okay"; -}; - -&usbdrd_dwc3_0 { - status = "okay"; -}; - -&usbdrd_dwc3_1 { - dr_mode = "host"; - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&vopl { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/rockchip/rk3399-op1-opp.dtsi b/sys/gnu/dts/arm64/rockchip/rk3399-op1-opp.dtsi deleted file mode 100644 index 69cc9b05baa..00000000000 --- a/sys/gnu/dts/arm64/rockchip/rk3399-op1-opp.dtsi +++ /dev/null @@ -1,141 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd - */ - -/ { - cluster0_opp: opp-table0 { - compatible = "operating-points-v2"; - opp-shared; - - opp00 { - opp-hz = /bits/ 64 <408000000>; - opp-microvolt = <800000>; - clock-latency-ns = <40000>; - }; - opp01 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <825000>; - }; - opp02 { - opp-hz = /bits/ 64 <816000000>; - opp-microvolt = <850000>; - }; - opp03 { - opp-hz = /bits/ 64 <1008000000>; - opp-microvolt = <900000>; - }; - opp04 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <975000>; - }; - opp05 { - opp-hz = /bits/ 64 <1416000000>; - opp-microvolt = <1100000>; - }; - opp06 { - opp-hz = /bits/ 64 <1512000000>; - opp-microvolt = <1150000>; - }; - }; - - cluster1_opp: opp-table1 { - compatible = "operating-points-v2"; - opp-shared; - - opp00 { - opp-hz = /bits/ 64 <408000000>; - opp-microvolt = <800000>; - clock-latency-ns = <40000>; - }; - opp01 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <800000>; - }; - opp02 { - opp-hz = /bits/ 64 <816000000>; - opp-microvolt = <825000>; - }; - opp03 { - opp-hz = /bits/ 64 <1008000000>; - opp-microvolt = <850000>; - }; - opp04 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <900000>; - }; - opp05 { - opp-hz = /bits/ 64 <1416000000>; - opp-microvolt = <975000>; - }; - opp06 { - opp-hz = /bits/ 64 <1608000000>; - opp-microvolt = <1050000>; - }; - opp07 { - opp-hz = /bits/ 64 <1800000000>; - opp-microvolt = <1150000>; - }; - opp08 { - opp-hz = /bits/ 64 <2016000000>; - opp-microvolt = <1250000>; - }; - }; - - gpu_opp_table: opp-table2 { - compatible = "operating-points-v2"; - - opp00 { - opp-hz = /bits/ 64 <200000000>; - opp-microvolt = <800000>; - }; - opp01 { - opp-hz = /bits/ 64 <297000000>; - opp-microvolt = <800000>; - }; - opp02 { - opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <825000>; - }; - opp03 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <850000>; - }; - opp04 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <925000>; - }; - opp05 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <1075000>; - }; - }; -}; - -&cpu_l0 { - operating-points-v2 = <&cluster0_opp>; -}; - -&cpu_l1 { - operating-points-v2 = <&cluster0_opp>; -}; - -&cpu_l2 { - operating-points-v2 = <&cluster0_opp>; -}; - -&cpu_l3 { - operating-points-v2 = <&cluster0_opp>; -}; - -&cpu_b0 { - operating-points-v2 = <&cluster1_opp>; -}; - -&cpu_b1 { - operating-points-v2 = <&cluster1_opp>; -}; - -&gpu { - operating-points-v2 = <&gpu_opp_table>; -}; diff --git a/sys/gnu/dts/arm64/rockchip/rk3399-opp.dtsi b/sys/gnu/dts/arm64/rockchip/rk3399-opp.dtsi deleted file mode 100644 index d6f1095abb0..00000000000 --- a/sys/gnu/dts/arm64/rockchip/rk3399-opp.dtsi +++ /dev/null @@ -1,133 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd - */ - -/ { - cluster0_opp: opp-table0 { - compatible = "operating-points-v2"; - opp-shared; - - opp00 { - opp-hz = /bits/ 64 <408000000>; - opp-microvolt = <800000>; - clock-latency-ns = <40000>; - }; - opp01 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <800000>; - }; - opp02 { - opp-hz = /bits/ 64 <816000000>; - opp-microvolt = <850000>; - }; - opp03 { - opp-hz = /bits/ 64 <1008000000>; - opp-microvolt = <925000>; - }; - opp04 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <1000000>; - }; - opp05 { - opp-hz = /bits/ 64 <1416000000>; - opp-microvolt = <1125000>; - }; - }; - - cluster1_opp: opp-table1 { - compatible = "operating-points-v2"; - opp-shared; - - opp00 { - opp-hz = /bits/ 64 <408000000>; - opp-microvolt = <800000>; - clock-latency-ns = <40000>; - }; - opp01 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <800000>; - }; - opp02 { - opp-hz = /bits/ 64 <816000000>; - opp-microvolt = <825000>; - }; - opp03 { - opp-hz = /bits/ 64 <1008000000>; - opp-microvolt = <875000>; - }; - opp04 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <950000>; - }; - opp05 { - opp-hz = /bits/ 64 <1416000000>; - opp-microvolt = <1025000>; - }; - opp06 { - opp-hz = /bits/ 64 <1608000000>; - opp-microvolt = <1100000>; - }; - opp07 { - opp-hz = /bits/ 64 <1800000000>; - opp-microvolt = <1200000>; - }; - }; - - gpu_opp_table: opp-table2 { - compatible = "operating-points-v2"; - - opp00 { - opp-hz = /bits/ 64 <200000000>; - opp-microvolt = <800000>; - }; - opp01 { - opp-hz = /bits/ 64 <297000000>; - opp-microvolt = <800000>; - }; - opp02 { - opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <825000>; - }; - opp03 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <875000>; - }; - opp04 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <925000>; - }; - opp05 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <1100000>; - }; - }; -}; - -&cpu_l0 { - operating-points-v2 = <&cluster0_opp>; -}; - -&cpu_l1 { - operating-points-v2 = <&cluster0_opp>; -}; - -&cpu_l2 { - operating-points-v2 = <&cluster0_opp>; -}; - -&cpu_l3 { - operating-points-v2 = <&cluster0_opp>; -}; - -&cpu_b0 { - operating-points-v2 = <&cluster1_opp>; -}; - -&cpu_b1 { - operating-points-v2 = <&cluster1_opp>; -}; - -&gpu { - operating-points-v2 = <&gpu_opp_table>; -}; diff --git a/sys/gnu/dts/arm64/rockchip/rk3399-orangepi.dts b/sys/gnu/dts/arm64/rockchip/rk3399-orangepi.dts deleted file mode 100644 index 9c659f3115c..00000000000 --- a/sys/gnu/dts/arm64/rockchip/rk3399-orangepi.dts +++ /dev/null @@ -1,793 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd. - */ - -/dts-v1/; - -#include "dt-bindings/pwm/pwm.h" -#include "dt-bindings/input/input.h" -#include "rk3399.dtsi" -#include "rk3399-opp.dtsi" - -/ { - model = "Orange Pi RK3399 Board"; - compatible = "rockchip,rk3399-orangepi", "rockchip,rk3399"; - - chosen { - stdout-path = "serial2:1500000n8"; - }; - - clkin_gmac: external-gmac-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "clkin_gmac"; - #clock-cells = <0>; - }; - - adc-keys { - compatible = "adc-keys"; - io-channels = <&saradc 1>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1800000>; - poll-interval = <100>; - - button-up { - label = "Volume Up"; - linux,code = ; - press-threshold-microvolt = <100000>; - }; - - button-down { - label = "Volume Down"; - linux,code = ; - press-threshold-microvolt = <300000>; - }; - - back { - label = "Back"; - linux,code = ; - press-threshold-microvolt = <985000>; - }; - - menu { - label = "Menu"; - linux,code = ; - press-threshold-microvolt = <1314000>; - }; - }; - - dc_12v: dc-12v { - compatible = "regulator-fixed"; - regulator-name = "dc_12v"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - keys: gpio-keys { - compatible = "gpio-keys"; - autorepeat; - - power { - debounce-interval = <100>; - gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; - label = "GPIO Power"; - linux,code = ; - linux,input-type = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&pwr_btn>; - wakeup-source; - }; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&rk808 1>; - clock-names = "ext_clock"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_reg_on_h>; - reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; - }; - - /* switched by pmic_sleep */ - vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 { - compatible = "regulator-fixed"; - regulator-name = "vcc1v8_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_1v8>; - }; - - vcc3v0_sd: vcc3v0-sd { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc0_pwr_h>; - regulator-boot-on; - regulator-max-microvolt = <3000000>; - regulator-min-microvolt = <3000000>; - regulator-name = "vcc3v0_sd"; - vin-supply = <&vcc3v3_sys>; - }; - - vcc3v3_sys: vcc3v3-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_sys>; - }; - - vcc5v0_host: vcc5v0-host-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_host_en>; - regulator-name = "vcc5v0_host"; - regulator-always-on; - vin-supply = <&vcc_sys>; - }; - - vbus_typec: vbus-typec-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_typec_en>; - regulator-name = "vbus_typec"; - vin-supply = <&vcc_sys>; - }; - - vcc_sys: vcc-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&dc_12v>; - }; - - vdd_log: vdd-log { - compatible = "pwm-regulator"; - pwms = <&pwm2 0 25000 1>; - regulator-name = "vdd_log"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - vin-supply = <&vcc_sys>; - }; -}; - -&cpu_l0 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l1 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l2 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l3 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_b0 { - cpu-supply = <&vdd_cpu_b>; -}; - -&cpu_b1 { - cpu-supply = <&vdd_cpu_b>; -}; - -&emmc_phy { - status = "okay"; -}; - -&gmac { - assigned-clocks = <&cru SCLK_RMII_SRC>; - assigned-clock-parents = <&clkin_gmac>; - clock_in_out = "input"; - phy-supply = <&vcc3v3_s3>; - phy-mode = "rgmii"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 50000>; - tx_delay = <0x28>; - rx_delay = <0x11>; - status = "okay"; -}; - -&gpu { - mali-supply = <&vdd_gpu>; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c3>; - status = "okay"; -}; - -&hdmi_sound { - status = "okay"; -}; - -&i2c0 { - clock-frequency = <400000>; - i2c-scl-rising-time-ns = <168>; - i2c-scl-falling-time-ns = <4>; - status = "okay"; - - rk808: pmic@1b { - compatible = "rockchip,rk808"; - reg = <0x1b>; - interrupt-parent = <&gpio1>; - interrupts = <21 IRQ_TYPE_LEVEL_LOW>; - #clock-cells = <1>; - clock-output-names = "rtc_clko_soc", "rtc_clko_wifi"; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l>; - rockchip,system-power-controller; - wakeup-source; - - vcc1-supply = <&vcc3v3_sys>; - vcc2-supply = <&vcc3v3_sys>; - vcc3-supply = <&vcc3v3_sys>; - vcc4-supply = <&vcc3v3_sys>; - vcc6-supply = <&vcc3v3_sys>; - vcc7-supply = <&vcc3v3_sys>; - vcc8-supply = <&vcc3v3_sys>; - vcc9-supply = <&vcc3v3_sys>; - vcc10-supply = <&vcc3v3_sys>; - vcc11-supply = <&vcc3v3_sys>; - vcc12-supply = <&vcc3v3_sys>; - vddio-supply = <&vcc_3v0>; - - regulators { - vdd_center: DCDC_REG1 { - regulator-name = "vdd_center"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1500000>; - regulator-ramp-delay = <6001>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_l: DCDC_REG2 { - regulator-name = "vdd_cpu_l"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1500000>; - regulator-ramp-delay = <6001>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_1v8: DCDC_REG4 { - regulator-name = "vcc_1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc1v8_dvp: LDO_REG1 { - regulator-name = "vcc1v8_dvp"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3400000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v0_tp: LDO_REG2 { - regulator-name = "vcc3v0_tp"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3400000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc1v8_pmupll: LDO_REG3 { - regulator-name = "vcc1v8_pmupll"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <2500000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc_sdio: LDO_REG4 { - regulator-name = "vcc_sdio"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3400000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3000000>; - }; - }; - - vcca3v0_codec: LDO_REG5 { - regulator-name = "vcca3v0_codec"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3400000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v5: LDO_REG6 { - regulator-name = "vcc_1v5"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <2500000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1500000>; - }; - }; - - vcca1v8_codec: LDO_REG7 { - regulator-name = "vcca1v8_codec"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <2500000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_3v0: LDO_REG8 { - regulator-name = "vcc_3v0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3400000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3000000>; - }; - }; - - vcc3v3_s3: SWITCH_REG1 { - regulator-name = "vcc3v3_s3"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v3_s0: SWITCH_REG2 { - regulator-name = "vcc3v3_s0"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; - - vdd_cpu_b: regulator@40 { - compatible = "silergy,syr827"; - reg = <0x40>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_cpu_b"; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1500000>; - regulator-ramp-delay = <1000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc3v3_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_gpu: regulator@41 { - compatible = "silergy,syr828"; - reg = <0x41>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_gpu"; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1500000>; - regulator-ramp-delay = <1000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc3v3_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&i2c1 { - i2c-scl-rising-time-ns = <450>; - i2c-scl-falling-time-ns = <15>; - status = "okay"; -}; - -&i2c3 { - i2c-scl-rising-time-ns = <450>; - i2c-scl-falling-time-ns = <15>; - status = "okay"; -}; - -&i2c4 { - clock-frequency = <400000>; - i2c-scl-rising-time-ns = <450>; - i2c-scl-falling-time-ns = <15>; - status = "okay"; - - ak09911@c { - compatible = "asahi-kasei,ak09911"; - reg = <0x0c>; - vdd-supply = <&vcc3v3_s3>; - vid-supply = <&vcc3v3_s3>; - }; - - mpu6500@68 { - compatible = "invensense,mpu6500"; - reg = <0x68>; - interrupt-parent = <&gpio1>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&gsensor_int_l>; - vddio-supply = <&vcc3v3_s3>; - }; - - lsm6ds3@6a { - compatible = "st,lsm6ds3"; - reg = <0x6a>; - interrupt-parent = <&gpio1>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&gyr_int_l>; - vdd-supply = <&vcc3v3_s3>; - vddio-supply = <&vcc3v3_s3>; - }; - - cm32181@10 { - compatible = "capella,cm32181"; - reg = <0x10>; - interrupt-parent = <&gpio4>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&light_int_l>; - vdd-supply = <&vcc3v3_s3>; - }; - - fusb302@22 { - compatible = "fcs,fusb302"; - reg = <0x22>; - interrupt-parent = <&gpio1>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&chg_cc_int_l>; - vbus-supply = <&vbus_typec>; - }; -}; - -&io_domains { - status = "okay"; - bt656-supply = <&vcc_3v0>; - audio-supply = <&vcca1v8_codec>; - sdmmc-supply = <&vcc_sdio>; - gpio1830-supply = <&vcc_3v0>; -}; - -&pmu_io_domains { - status = "okay"; - pmu1830-supply = <&vcc_3v0>; -}; - -&pinctrl { - buttons { - pwr_btn: pwr-btn { - rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - pmic { - pmic_int_l: pmic-int-l { - rockchip,pins = - <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - sd { - sdmmc0_pwr_h: sdmmc0-pwr-h { - rockchip,pins = - <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb2 { - vcc5v0_host_en: vcc5v0-host-en { - rockchip,pins = - <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - vcc5v0_typec_en: vcc5v0-typec-en { - rockchip,pins = - <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - sdio-pwrseq { - wifi_reg_on_h: wifi-reg-on-h { - rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - wifi { - wifi_host_wake_l: wifi-host-wake-l { - rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - bluetooth { - bt_reg_on_h: bt-enable-h { - rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_host_wake_l: bt-host-wake-l { - rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_wake_l: bt-wake-l { - rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - mpu6500 { - gsensor_int_l: gsensor-int-l { - rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - lsm6ds3 { - gyr_int_l: gyr-int-l { - rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - cm32181 { - light_int_l: light-int-l { - rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - fusb302 { - chg_cc_int_l: chg-cc-int-l { - rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; -}; - -&pwm0 { - status = "okay"; -}; - -&pwm2 { - status = "okay"; -}; - -&saradc { - vref-supply = <&vcca1v8_s3>; - status = "okay"; -}; - -&sdhci { - bus-width = <8>; - mmc-hs400-1_8v; - mmc-hs400-enhanced-strobe; - non-removable; - status = "okay"; -}; - -&sdio0 { - bus-width = <4>; - cap-sd-highspeed; - cap-sdio-irq; - clock-frequency = <50000000>; - disable-wp; - keep-power-in-suspend; - max-frequency = <50000000>; - mmc-pwrseq = <&sdio_pwrseq>; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; - sd-uhs-sdr104; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - interrupt-parent = <&gpio0>; - interrupts = ; - interrupt-names = "host-wake"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_host_wake_l>; - }; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; - clock-frequency = <150000000>; - disable-wp; - max-frequency = <150000000>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; - vmmc-supply = <&vcc3v0_sd>; - vqmmc-supply = <&vcc_sdio>; - status = "okay"; -}; - -&tcphy0 { - status = "okay"; -}; - -&tcphy1 { - status = "okay"; -}; - -&tsadc { - rockchip,hw-tshut-mode = <1>; - rockchip,hw-tshut-polarity = <1>; - status = "okay"; -}; - -&u2phy0 { - status = "okay"; - - u2phy0_otg: otg-port { - phy-supply = <&vbus_typec>; - status = "okay"; - }; - - u2phy0_host: host-port { - phy-supply = <&vcc5v0_host>; - status = "okay"; - }; -}; - -&u2phy1 { - status = "okay"; - - u2phy1_otg: otg-port { - status = "okay"; - }; - - u2phy1_host: host-port { - phy-supply = <&vcc5v0_host>; - status = "okay"; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - clocks = <&rk808 1>; - clock-names = "lpo"; - device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>; - host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; - shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_reg_on_h>; - vbat-supply = <&vcc3v3_sys>; - vddio-supply = <&vcc_1v8>; - }; -}; - -&uart2 { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - -&usbdrd3_0 { - status = "okay"; -}; - -&usbdrd_dwc3_0 { - status = "okay"; - dr_mode = "otg"; -}; - -&usbdrd3_1 { - status = "okay"; -}; - -&usbdrd_dwc3_1 { - status = "okay"; - dr_mode = "host"; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&vopl { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/rockchip/rk3399-puma-haikou.dts b/sys/gnu/dts/arm64/rockchip/rk3399-puma-haikou.dts deleted file mode 100644 index d80d6b72682..00000000000 --- a/sys/gnu/dts/arm64/rockchip/rk3399-puma-haikou.dts +++ /dev/null @@ -1,271 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH - */ - -/dts-v1/; -#include "rk3399-puma.dtsi" - -/ { - model = "Theobroma Systems RK3399-Q7 SoM"; - compatible = "tsd,rk3399-puma-haikou", "rockchip,rk3399"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - pinctrl-0 = <&led_pin_module>, <&led_sd_haikou>; - - sd-card-led { - label = "sd_card_led"; - gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc0"; - }; - }; - - i2s0-sound { - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,name = "Haikou,I2S-codec"; - simple-audio-card,mclk-fs = <512>; - - simple-audio-card,codec { - clocks = <&sgtl5000_clk>; - sound-dai = <&sgtl5000>; - }; - - simple-audio-card,cpu { - bitclock-master; - frame-master; - sound-dai = <&i2s0>; - }; - }; - - sgtl5000_clk: sgtl5000-oscillator { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24576000>; - }; - - dc_12v: dc-12v { - compatible = "regulator-fixed"; - regulator-name = "dc_12v"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - vcc3v3_baseboard: vcc3v3-baseboard { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_baseboard"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&dc_12v>; - }; - - vcc5v0_baseboard: vcc5v0-baseboard { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_baseboard"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&dc_12v>; - }; - - vcc5v0_otg: vcc5v0-otg-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&otg_vbus_drv>; - regulator-name = "vcc5v0_otg"; - regulator-always-on; - }; - - vdda_codec: vdda-codec { - compatible = "regulator-fixed"; - regulator-name = "vdda_codec"; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc5v0_baseboard>; - }; - - vddd_codec: vddd-codec { - compatible = "regulator-fixed"; - regulator-name = "vddd_codec"; - regulator-boot-on; - regulator-min-microvolt = <1600000>; - regulator-max-microvolt = <1600000>; - vin-supply = <&vcc5v0_baseboard>; - }; -}; - -&hdmi { - ddc-i2c-bus = <&i2c3>; - status = "okay"; -}; - -&i2c1 { - status = "okay"; - clock-frequency = <400000>; -}; - -&i2c2 { - status = "okay"; - clock-frequency = <400000>; -}; - -&i2c3 { - i2c-scl-rising-time-ns = <450>; - i2c-scl-falling-time-ns = <15>; - status = "okay"; -}; - -&i2c4 { - status = "okay"; - clock-frequency = <400000>; - - sgtl5000: codec@a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - clocks = <&sgtl5000_clk>; - #sound-dai-cells = <0>; - VDDA-supply = <&vdda_codec>; - VDDIO-supply = <&vdda_codec>; - VDDD-supply = <&vddd_codec>; - status = "okay"; - }; -}; - -&i2c6 { - status = "okay"; - clock-frequency = <400000>; -}; - -&pcie_phy { - status = "okay"; -}; - -&pcie0 { - ep-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>; - num-lanes = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie_clkreqn_cpm>; - status = "okay"; -}; - -&pinctrl { - pinctrl-names = "default"; - pinctrl-0 = <&haikou_pin_hog>; - - hog { - haikou_pin_hog: haikou-pin-hog { - rockchip,pins = - /* LID_BTN */ - <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>, - /* BATLOW# */ - <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>, - /* SLP_BTN# */ - <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>, - /* BIOS_DISABLE# */ - <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - leds { - led_sd_haikou: led-sd-gpio { - rockchip,pins = - <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb2 { - otg_vbus_drv: otg-vbus-drv { - rockchip,pins = - <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&pwm0 { - status = "okay"; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; - disable-wp; - max-frequency = <150000000>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; - vmmc-supply = <&vcc3v3_baseboard>; - status = "okay"; -}; - -&spi5 { - status = "okay"; -}; - -&tcphy0 { - status = "okay"; -}; - -&u2phy0 { - status = "okay"; -}; - -&usbdrd3_0 { - status = "okay"; -}; - -&usbdrd_dwc3_0 { - dr_mode = "otg"; - status = "okay"; -}; - -&u2phy0_host { - phy-supply = <&vcc5v0_otg>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&vopl { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/rockchip/rk3399-puma.dtsi b/sys/gnu/dts/arm64/rockchip/rk3399-puma.dtsi deleted file mode 100644 index c1edca3872c..00000000000 --- a/sys/gnu/dts/arm64/rockchip/rk3399-puma.dtsi +++ /dev/null @@ -1,534 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH - */ - -#include -#include "rk3399.dtsi" -#include "rk3399-opp.dtsi" - -/ { - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pin_module>; - - module-led { - label = "module_led"; - gpios = <&gpio2 RK_PD1 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - panic-indicator; - }; - }; - - /* - * Overwrite the opp-table for CPUB as this board uses a different - * regulator (FAN53555) that only allows 10mV steps and therefore - * can't reach the operation point target voltages from rk3399-opp.dtsi - */ - /delete-node/ opp-table1; - cluster1_opp: opp-table1 { - compatible = "operating-points-v2"; - opp-shared; - - opp00 { - opp-hz = /bits/ 64 <408000000>; - opp-microvolt = <800000>; - clock-latency-ns = <40000>; - }; - opp01 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <800000>; - }; - opp02 { - opp-hz = /bits/ 64 <816000000>; - opp-microvolt = <830000>; - opp-suspend; - }; - opp03 { - opp-hz = /bits/ 64 <1008000000>; - opp-microvolt = <880000>; - }; - opp04 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <950000>; - }; - opp05 { - opp-hz = /bits/ 64 <1416000000>; - opp-microvolt = <1030000>; - }; - opp06 { - opp-hz = /bits/ 64 <1608000000>; - opp-microvolt = <1100000>; - }; - opp07 { - opp-hz = /bits/ 64 <1800000000>; - opp-microvolt = <1200000>; - }; - opp08 { - opp-hz = /bits/ 64 <1992000000>; - opp-microvolt = <1230000>; - turbo-mode; - }; - }; - - clkin_gmac: external-gmac-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "clkin_gmac"; - #clock-cells = <0>; - }; - - vcc1v2_phy: vcc1v2-phy { - compatible = "regulator-fixed"; - regulator-name = "vcc1v2_phy"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - vin-supply = <&vcc5v0_sys>; - }; - - vcc3v3_sys: vcc3v3-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc5v0_sys>; - }; - - vcc5v0_host: vcc5v0-host-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>; - enable-active-low; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_host_en>; - regulator-name = "vcc5v0_host"; - regulator-always-on; - vin-supply = <&vcc5v0_sys>; - }; - - vcc5v0_sys: vcc5v0-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; -}; - -&cpu_b0 { - cpu-supply = <&vdd_cpu_b>; -}; - -&cpu_b1 { - cpu-supply = <&vdd_cpu_b>; -}; - -&cpu_l0 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l1 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l2 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l3 { - cpu-supply = <&vdd_cpu_l>; -}; - -&emmc_phy { - status = "okay"; - drive-impedance-ohm = <33>; -}; - -&gmac { - assigned-clocks = <&cru SCLK_RMII_SRC>; - assigned-clock-parents = <&clkin_gmac>; - clock_in_out = "input"; - phy-supply = <&vcc1v2_phy>; - phy-mode = "rgmii"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - snps,reset-gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 50000>; - tx_delay = <0x10>; - rx_delay = <0x10>; - status = "okay"; -}; - -&gpu { - mali-supply = <&vdd_gpu>; - status = "okay"; -}; - -&i2c0 { - status = "okay"; - i2c-scl-rising-time-ns = <168>; - i2c-scl-falling-time-ns = <4>; - clock-frequency = <400000>; - - rk808: pmic@1b { - compatible = "rockchip,rk808"; - reg = <0x1b>; - interrupt-parent = <&gpio1>; - interrupts = <22 IRQ_TYPE_LEVEL_LOW>; - #clock-cells = <1>; - clock-output-names = "xin32k", "rk808-clkout2"; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l>; - rockchip,system-power-controller; - wakeup-source; - - vcc1-supply = <&vcc5v0_sys>; - vcc2-supply = <&vcc5v0_sys>; - vcc3-supply = <&vcc5v0_sys>; - vcc4-supply = <&vcc5v0_sys>; - vcc6-supply = <&vcc5v0_sys>; - vcc7-supply = <&vcc5v0_sys>; - vcc8-supply = <&vcc3v3_sys>; - vcc9-supply = <&vcc5v0_sys>; - vcc10-supply = <&vcc5v0_sys>; - vcc11-supply = <&vcc5v0_sys>; - vcc12-supply = <&vcc3v3_sys>; - vddio-supply = <&vcc1v8_pmu>; - - regulators { - vdd_center: DCDC_REG1 { - regulator-name = "vdd_center"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_l: DCDC_REG2 { - regulator-name = "vdd_cpu_l"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_1v8: DCDC_REG4 { - regulator-name = "vcc_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc_ldo1: LDO_REG1 { - regulator-name = "vcc_ldo1"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc1v8_hdmi: LDO_REG2 { - regulator-name = "vcc1v8_hdmi"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc1v8_pmu: LDO_REG3 { - regulator-name = "vcc1v8_pmu"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc_sd: LDO_REG4 { - regulator-name = "vcc_sd"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3000000>; - }; - }; - - vcc_ldo5: LDO_REG5 { - regulator-name = "vcc_ldo5"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_ldo6: LDO_REG6 { - regulator-name = "vcc_ldo6"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc0v9_hdmi: LDO_REG7 { - regulator-name = "vcc0v9_hdmi"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_efuse: LDO_REG8 { - regulator-name = "vcc_efuse"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v3_s3: SWITCH_REG1 { - regulator-name = "vcc3v3_s3"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v3_s0: SWITCH_REG2 { - regulator-name = "vcc3v3_s0"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; - - vdd_gpu: regulator@60 { - compatible = "fcs,fan53555"; - reg = <0x60>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_gpu"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1230000>; - regulator-ramp-delay = <1000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc5v0_sys>; - }; -}; - -&i2c7 { - status = "okay"; - clock-frequency = <400000>; - - fan: fan@18 { - compatible = "ti,amc6821"; - reg = <0x18>; - #cooling-cells = <2>; - }; - - rtc_twi: rtc@6f { - compatible = "isil,isl1208"; - reg = <0x6f>; - }; -}; - -&i2c8 { - status = "okay"; - clock-frequency = <400000>; - - vdd_cpu_b: regulator@60 { - compatible = "fcs,fan53555"; - reg = <0x60>; - vin-supply = <&vcc5v0_sys>; - regulator-name = "vdd_cpu_b"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1230000>; - regulator-ramp-delay = <1000>; - fcs,suspend-voltage-selector = <1>; - regulator-always-on; - regulator-boot-on; - }; -}; - -&i2s0 { - pinctrl-0 = <&i2s0_2ch_bus>; - rockchip,playback-channels = <2>; - rockchip,capture-channels = <2>; - status = "okay"; -}; - -/* - * As Q7 does not specify neither a global nor a RX clock for I2S these - * signals are not used. Furthermore I2S0_LRCK_RX is used as GPIO. - * Therefore we have to redefine the i2s0_2ch_bus definition to prevent - * conflicts. - */ -&i2s0_2ch_bus { - rockchip,pins = - <3 RK_PD0 1 &pcfg_pull_none>, - <3 RK_PD2 1 &pcfg_pull_none>, - <3 RK_PD3 1 &pcfg_pull_none>, - <3 RK_PD7 1 &pcfg_pull_none>; -}; - -&io_domains { - status = "okay"; - bt656-supply = <&vcc_1v8>; - audio-supply = <&vcc_1v8>; - sdmmc-supply = <&vcc_sd>; - gpio1830-supply = <&vcc_1v8>; -}; - -&pmu_io_domains { - status = "okay"; - pmu1830-supply = <&vcc_1v8>; -}; - -&pwm2 { - status = "okay"; -}; - -&pinctrl { - i2c8 { - i2c8_xfer_a: i2c8-xfer { - rockchip,pins = - <1 RK_PC4 1 &pcfg_pull_up>, - <1 RK_PC5 1 &pcfg_pull_up>; - }; - }; - - leds { - led_pin_module: led-module-gpio { - rockchip,pins = - <2 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - pmic_int_l: pmic-int-l { - rockchip,pins = - <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - usb2 { - vcc5v0_host_en: vcc5v0-host-en { - rockchip,pins = - <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&sdhci { - bus-width = <8>; - mmc-hs400-1_8v; - mmc-hs400-enhanced-strobe; - non-removable; - status = "okay"; -}; - -&sdmmc { - vqmmc = <&vcc_sd>; -}; - -&spi1 { - status = "okay"; - - norflash: flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <50000000>; - }; -}; - -&tcphy1 { - status = "okay"; -}; - -&tsadc { - rockchip,hw-tshut-mode = <1>; - rockchip,hw-tshut-polarity = <1>; - status = "okay"; -}; - -&u2phy1 { - status = "okay"; - - u2phy1_otg: otg-port { - status = "okay"; - }; - - u2phy1_host: host-port { - phy-supply = <&vcc5v0_host>; - status = "okay"; - }; -}; - -&usbdrd3_1 { - status = "okay"; -}; - -&usbdrd_dwc3_1 { - status = "okay"; - dr_mode = "host"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/rockchip/rk3399-roc-pc-mezzanine.dts b/sys/gnu/dts/arm64/rockchip/rk3399-roc-pc-mezzanine.dts deleted file mode 100644 index 2acb3d500fb..00000000000 --- a/sys/gnu/dts/arm64/rockchip/rk3399-roc-pc-mezzanine.dts +++ /dev/null @@ -1,93 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 T-Chip Intelligent Technology Co., Ltd - * Copyright (c) 2019 Markus Reichl - */ - -/dts-v1/; -#include "rk3399-roc-pc.dtsi" - -/ { - model = "Firefly ROC-RK3399-PC Mezzanine Board"; - compatible = "firefly,roc-rk3399-pc-mezzanine", "rockchip,rk3399"; - - vcc3v3_ngff: vcc3v3-ngff { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_ngff"; - enable-active-high; - gpio = <&gpio4 RK_PD3 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc3v3_ngff_en>; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&dc_12v>; - }; - - vcc3v3_pcie: vcc3v3-pcie { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_pcie"; - enable-active-high; - gpio = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc3v3_pcie_en>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&dc_12v>; - }; -}; - -&pcie_phy { - status = "okay"; -}; - -&pcie0 { - ep-gpios = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>; - num-lanes = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie_perst>; - vpcie3v3-supply = <&vcc3v3_pcie>; - vpcie1v8-supply = <&vcc1v8_pmu>; - vpcie0v9-supply = <&vcca_0v9>; - status = "okay"; -}; - -&pinctrl { - ngff { - vcc3v3_ngff_en: vcc3v3-ngff-en { - rockchip,pins = <4 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pcie { - vcc3v3_pcie_en: vcc3v3-pcie-en { - rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - pcie_perst: pcie-perst { - rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&sdio0 { - bus-width = <4>; - cap-sd-highspeed; - cap-sdio-irq; - keep-power-in-suspend; - mmc-pwrseq = <&sdio_pwrseq>; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; - sd-uhs-sdr104; - vmmc-supply = <&vcc3v3_ngff>; - vqmmc-supply = <&vcc_1v8>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/rockchip/rk3399-roc-pc.dts b/sys/gnu/dts/arm64/rockchip/rk3399-roc-pc.dts deleted file mode 100644 index cd419542530..00000000000 --- a/sys/gnu/dts/arm64/rockchip/rk3399-roc-pc.dts +++ /dev/null @@ -1,12 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 T-Chip Intelligent Technology Co., Ltd - */ - -/dts-v1/; -#include "rk3399-roc-pc.dtsi" - -/ { - model = "Firefly ROC-RK3399-PC Board"; - compatible = "firefly,roc-rk3399-pc", "rockchip,rk3399"; -}; diff --git a/sys/gnu/dts/arm64/rockchip/rk3399-roc-pc.dtsi b/sys/gnu/dts/arm64/rockchip/rk3399-roc-pc.dtsi deleted file mode 100644 index 9f225e9c3d5..00000000000 --- a/sys/gnu/dts/arm64/rockchip/rk3399-roc-pc.dtsi +++ /dev/null @@ -1,814 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 T-Chip Intelligent Technology Co., Ltd - */ - -/dts-v1/; -#include -#include -#include "rk3399.dtsi" -#include "rk3399-opp.dtsi" - -/ { - model = "Firefly ROC-RK3399-PC Board"; - compatible = "firefly,roc-rk3399-pc", "rockchip,rk3399"; - - chosen { - stdout-path = "serial2:1500000n8"; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm0 0 25000 0>; - }; - - clkin_gmac: external-gmac-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "clkin_gmac"; - #clock-cells = <0>; - }; - - adc-keys { - compatible = "adc-keys"; - io-channels = <&saradc 1>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1500000>; - poll-interval = <100>; - - recovery { - label = "Recovery"; - linux,code = ; - press-threshold-microvolt = <18000>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - pinctrl-names = "default"; - pinctrl-0 = <&pwr_key_l>; - - power { - debounce-interval = <100>; - gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; - label = "GPIO Key Power"; - linux,code = ; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&work_led_gpio>, <&diy_led_gpio>, <&yellow_led_gpio>; - - work-led { - label = "green:work"; - gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - - diy-led { - label = "red:diy"; - gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; - default-state = "off"; - linux,default-trigger = "mmc1"; - }; - - yellow-led { - label = "yellow:yellow-led"; - gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; - default-state = "off"; - linux,default-trigger = "mmc0"; - }; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&rk808 1>; - clock-names = "ext_clock"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_enable_h>; - - /* - * On the module itself this is one of these (depending - * on the actual card populated): - * - SDIO_RESET_L_WL_REG_ON - * - PDN (power down when low) - */ - reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; - }; - - vcc_vbus_typec0: vcc-vbus-typec0 { - compatible = "regulator-fixed"; - regulator-name = "vcc_vbus_typec0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - /* switched by pmic_sleep */ - vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 { - compatible = "regulator-fixed"; - regulator-name = "vcc1v8_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_1v8>; - }; - - vcc3v0_sd: vcc3v0-sd { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio4 RK_PD6 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc3v0_sd_en>; - regulator-name = "vcc3v0_sd"; - regulator-boot-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - vin-supply = <&vcc3v3_sys>; - }; - - vcc3v3_sys: vcc3v3-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&dc_12v>; - }; - - vcca_0v9: vcca-0v9 { - compatible = "regulator-fixed"; - regulator-name = "vcca_0v9"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - vin-supply = <&vcc3v3_sys>; - }; - - /* Actually 3 regulators (host0, 1, 2) controlled by the same gpio */ - vcc5v0_host: vcc5v0-host-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_host_en &hub_rst>; - regulator-name = "vcc5v0_host"; - vin-supply = <&vcc_sys>; - }; - - vcc_vbus_typec1: vcc-vbus-typec1 { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc_vbus_typec1_en>; - regulator-name = "vcc_vbus_typec1"; - regulator-always-on; - vin-supply = <&vcc_sys>; - }; - - vcc_sys: vcc-sys { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio2 RK_PA6 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc_sys_en>; - regulator-name = "vcc_sys"; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&dc_12v>; - }; - - vdd_log: vdd-log { - compatible = "pwm-regulator"; - pwms = <&pwm2 0 25000 1>; - regulator-name = "vdd_log"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <450000>; - regulator-max-microvolt = <1400000>; - pwm-supply = <&vcc3v3_sys>; - }; -}; - -&cpu_l0 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l1 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l2 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l3 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_b0 { - cpu-supply = <&vdd_cpu_b>; -}; - -&cpu_b1 { - cpu-supply = <&vdd_cpu_b>; -}; - -&emmc_phy { - status = "okay"; -}; - -&gmac { - assigned-clocks = <&cru SCLK_RMII_SRC>; - assigned-clock-parents = <&clkin_gmac>; - clock_in_out = "input"; - phy-supply = <&vcc_lan>; - phy-mode = "rgmii"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 50000>; - tx_delay = <0x28>; - rx_delay = <0x11>; - status = "okay"; -}; - -&gpu { - mali-supply = <&vdd_gpu>; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c3>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_cec>; - status = "okay"; -}; - -&hdmi_sound { - status = "okay"; -}; - -&i2c0 { - clock-frequency = <400000>; - i2c-scl-rising-time-ns = <168>; - i2c-scl-falling-time-ns = <4>; - status = "okay"; - - rk808: pmic@1b { - compatible = "rockchip,rk808"; - reg = <0x1b>; - interrupt-parent = <&gpio1>; - interrupts = <21 IRQ_TYPE_LEVEL_LOW>; - #clock-cells = <1>; - clock-output-names = "xin32k", "rk808-clkout2"; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l>; - rockchip,system-power-controller; - wakeup-source; - - vcc1-supply = <&vcc3v3_sys>; - vcc2-supply = <&vcc3v3_sys>; - vcc3-supply = <&vcc3v3_sys>; - vcc4-supply = <&vcc3v3_sys>; - vcc6-supply = <&vcc3v3_sys>; - vcc7-supply = <&vcc3v3_sys>; - vcc8-supply = <&vcc3v3_sys>; - vcc9-supply = <&vcc3v3_sys>; - vcc10-supply = <&vcc3v3_sys>; - vcc11-supply = <&vcc3v3_sys>; - vcc12-supply = <&vcc3v3_sys>; - vcc13-supply = <&vcc3v3_sys>; - vcc14-supply = <&vcc3v3_sys>; - vddio-supply = <&vcc_3v0>; - - regulators { - vdd_center: DCDC_REG1 { - regulator-name = "vdd_center"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_l: DCDC_REG2 { - regulator-name = "vdd_cpu_l"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_1v8: DCDC_REG4 { - regulator-name = "vcc_1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcca1v8_codec: LDO_REG1 { - regulator-name = "vcca1v8_codec"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc1v8_hdmi: LDO_REG2 { - regulator-name = "vcc1v8_hdmi"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc1v8_pmu: LDO_REG3 { - regulator-name = "vcc1v8_pmu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc_sdio: LDO_REG4 { - regulator-name = "vcc_sdio"; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3000000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3000000>; - }; - }; - - vcca3v0_codec: LDO_REG5 { - regulator-name = "vcca3v0_codec"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v5: LDO_REG6 { - regulator-name = "vcc_1v5"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1500000>; - }; - }; - - vcca0v9_hdmi: LDO_REG7 { - regulator-name = "vcca0v9_hdmi"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_3v0: LDO_REG8 { - regulator-name = "vcc_3v0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3000000>; - }; - }; - - vcc3v3_s3: vcc_lan: SWITCH_REG1 { - regulator-name = "vcc3v3_s3"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v3_s0: SWITCH_REG2 { - regulator-name = "vcc3v3_s0"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; - - vdd_cpu_b: regulator@40 { - compatible = "silergy,syr827"; - reg = <0x40>; - fcs,suspend-voltage-selector = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&vsel1_gpio>; - regulator-name = "vdd_cpu_b"; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1500000>; - regulator-ramp-delay = <1000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc3v3_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_gpu: regulator@41 { - compatible = "silergy,syr828"; - reg = <0x41>; - fcs,suspend-voltage-selector = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&vsel2_gpio>; - regulator-name = "vdd_gpu"; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1500000>; - regulator-ramp-delay = <1000>; - vin-supply = <&vcc3v3_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&i2c1 { - i2c-scl-rising-time-ns = <300>; - i2c-scl-falling-time-ns = <15>; - status = "okay"; -}; - -&i2c3 { - i2c-scl-rising-time-ns = <450>; - i2c-scl-falling-time-ns = <15>; - status = "okay"; -}; - -&i2c4 { - i2c-scl-rising-time-ns = <600>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; - - fusb1: usb-typec@22 { - compatible = "fcs,fusb302"; - reg = <0x22>; - interrupt-parent = <&gpio1>; - interrupts = <1 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&fusb1_int>; - vbus-supply = <&vcc_vbus_typec1>; - status = "okay"; - }; -}; - -&i2c7 { - i2c-scl-rising-time-ns = <600>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; - - fusb0: usb-typec@22 { - compatible = "fcs,fusb302"; - reg = <0x22>; - interrupt-parent = <&gpio1>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&fusb0_int>; - vbus-supply = <&vcc_vbus_typec0>; - status = "okay"; - }; - - mp8859: regulator@66 { - compatible = "mps,mp8859"; - reg = <0x66>; - dc_12v: mp8859_dcdc { - regulator-name = "dc_12v"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_vbus_typec0>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <12000000>; - }; - }; - }; -}; - -&i2s0 { - rockchip,playback-channels = <8>; - rockchip,capture-channels = <8>; - status = "okay"; -}; - -&i2s1 { - rockchip,playback-channels = <2>; - rockchip,capture-channels = <2>; - status = "okay"; -}; - -&i2s2 { - status = "okay"; -}; - -&io_domains { - audio-supply = <&vcca1v8_codec>; - bt656-supply = <&vcc_3v0>; - gpio1830-supply = <&vcc_3v0>; - sdmmc-supply = <&vcc_sdio>; - status = "okay"; -}; - -&pmu_io_domains { - pmu1830-supply = <&vcc_3v0>; - status = "okay"; -}; - -&pinctrl { - buttons { - pwr_key_l: pwr-key-l { - rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - lcd-panel { - lcd_panel_reset: lcd-panel-reset { - rockchip,pins = <4 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - leds { - diy_led_gpio: diy_led-gpio { - rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - work_led_gpio: work_led-gpio { - rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - yellow_led_gpio: yellow_led-gpio { - rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - vsel1_gpio: vsel1-gpio { - rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - vsel2_gpio: vsel2-gpio { - rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; - - sdio-pwrseq { - wifi_enable_h: wifi-enable-h { - rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - sdmmc { - vcc3v0_sd_en: vcc3v0-sd-en { - rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - pmic_int_l: pmic-int-l { - rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - usb2 { - vcc5v0_host_en: vcc5v0-host-en { - rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - vcc_sys_en: vcc-sys-en { - rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - hub_rst: hub-rst { - rockchip,pins = <2 RK_PA4 RK_FUNC_GPIO &pcfg_output_high>; - }; - }; - - usb-typec { - vcc_vbus_typec1_en: vcc-vbus-typec1-en { - rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - fusb30x { - fusb0_int: fusb0-int { - rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - fusb1_int: fusb1-int { - rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; -}; - -&pwm0 { - status = "okay"; -}; - -&pwm2 { - status = "okay"; -}; - -&saradc { - vref-supply = <&vcca1v8_s3>; - status = "okay"; -}; - -&sdmmc { - bus-width = <4>; - cap-sd-highspeed; - cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; - disable-wp; - max-frequency = <150000000>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; - sd-uhs-sdr104; - vmmc-supply = <&vcc3v0_sd>; - vqmmc-supply = <&vcc_sdio>; - status = "okay"; -}; - -&sdhci { - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&spi1 { - status = "okay"; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <10000000>; - }; -}; - -&tcphy0 { - status = "okay"; -}; - -&tcphy1 { - status = "okay"; -}; - -&tsadc { - /* tshut mode 0:CRU 1:GPIO */ - rockchip,hw-tshut-mode = <1>; - /* tshut polarity 0:LOW 1:HIGH */ - rockchip,hw-tshut-polarity = <1>; - status = "okay"; -}; - -&u2phy0 { - status = "okay"; - - u2phy0_otg: otg-port { - phy-supply = <&vcc_vbus_typec0>; - status = "okay"; - }; - - u2phy0_host: host-port { - phy-supply = <&vcc5v0_host>; - status = "okay"; - }; -}; - -&u2phy1 { - status = "okay"; - - u2phy1_otg: otg-port { - phy-supply = <&vcc_vbus_typec1>; - status = "okay"; - }; - - u2phy1_host: host-port { - phy-supply = <&vcc5v0_host>; - status = "okay"; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_cts>; - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - -&usbdrd3_0 { - status = "okay"; -}; - -&usbdrd_dwc3_0 { - status = "okay"; -}; - -&usbdrd3_1 { - status = "okay"; -}; - -&usbdrd_dwc3_1 { - status = "okay"; - dr_mode = "host"; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&vopl { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/rockchip/rk3399-rock-pi-4.dts b/sys/gnu/dts/arm64/rockchip/rk3399-rock-pi-4.dts deleted file mode 100644 index 3923ec01ef6..00000000000 --- a/sys/gnu/dts/arm64/rockchip/rk3399-rock-pi-4.dts +++ /dev/null @@ -1,735 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 Akash Gajjar - * Copyright (c) 2019 Pragnesh Patel - */ - -/dts-v1/; -#include -#include -#include "rk3399.dtsi" -#include "rk3399-opp.dtsi" - -/ { - model = "Radxa ROCK Pi 4"; - compatible = "radxa,rockpi4", "rockchip,rk3399"; - - chosen { - stdout-path = "serial2:1500000n8"; - }; - - clkin_gmac: external-gmac-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "clkin_gmac"; - #clock-cells = <0>; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&rk808 1>; - clock-names = "ext_clock"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_enable_h>; - reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; - }; - - vcc12v_dcin: dc-12v { - compatible = "regulator-fixed"; - regulator-name = "vcc12v_dcin"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - vcc5v0_sys: vcc-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc12v_dcin>; - }; - - vcc_0v9: vcc-0v9 { - compatible = "regulator-fixed"; - regulator-name = "vcc_0v9"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - vin-supply = <&vcc3v3_sys>; - }; - - vcc3v3_pcie: vcc3v3-pcie-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie_pwr_en>; - regulator-name = "vcc3v3_pcie"; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc5v0_sys>; - }; - - vcc3v3_sys: vcc3v3-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc5v0_sys>; - }; - - vcc5v0_host: vcc5v0-host-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_host_en>; - regulator-name = "vcc5v0_host"; - regulator-always-on; - vin-supply = <&vcc5v0_sys>; - }; - - vcc5v0_typec: vcc5v0-typec-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_typec_en>; - regulator-name = "vcc5v0_typec"; - regulator-always-on; - vin-supply = <&vcc5v0_sys>; - }; - - vcc_lan: vcc3v3-phy-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_lan"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_log: vdd-log { - compatible = "pwm-regulator"; - pwms = <&pwm2 0 25000 1>; - regulator-name = "vdd_log"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - vin-supply = <&vcc5v0_sys>; - }; -}; - -&cpu_l0 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l1 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l2 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l3 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_b0 { - cpu-supply = <&vdd_cpu_b>; -}; - -&cpu_b1 { - cpu-supply = <&vdd_cpu_b>; -}; - -&emmc_phy { - status = "okay"; -}; - -&gmac { - assigned-clocks = <&cru SCLK_RMII_SRC>; - assigned-clock-parents = <&clkin_gmac>; - clock_in_out = "input"; - phy-supply = <&vcc_lan>; - phy-mode = "rgmii"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 50000>; - tx_delay = <0x28>; - rx_delay = <0x11>; - status = "okay"; -}; - -&gpu { - mali-supply = <&vdd_gpu>; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c3>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_cec>; - status = "okay"; -}; - -&hdmi_sound { - status = "okay"; -}; - -&i2c0 { - clock-frequency = <400000>; - i2c-scl-rising-time-ns = <168>; - i2c-scl-falling-time-ns = <4>; - status = "okay"; - - rk808: pmic@1b { - compatible = "rockchip,rk808"; - reg = <0x1b>; - interrupt-parent = <&gpio1>; - interrupts = <21 IRQ_TYPE_LEVEL_LOW>; - #clock-cells = <1>; - clock-output-names = "xin32k", "rk808-clkout2"; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l>; - rockchip,system-power-controller; - wakeup-source; - - vcc1-supply = <&vcc5v0_sys>; - vcc2-supply = <&vcc5v0_sys>; - vcc3-supply = <&vcc5v0_sys>; - vcc4-supply = <&vcc5v0_sys>; - vcc6-supply = <&vcc5v0_sys>; - vcc7-supply = <&vcc5v0_sys>; - vcc8-supply = <&vcc3v3_sys>; - vcc9-supply = <&vcc5v0_sys>; - vcc10-supply = <&vcc5v0_sys>; - vcc11-supply = <&vcc5v0_sys>; - vcc12-supply = <&vcc3v3_sys>; - vddio-supply = <&vcc_1v8>; - - regulators { - vdd_center: DCDC_REG1 { - regulator-name = "vdd_center"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_l: DCDC_REG2 { - regulator-name = "vdd_cpu_l"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_1v8: DCDC_REG4 { - regulator-name = "vcc_1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc1v8_codec: LDO_REG1 { - regulator-name = "vcc1v8_codec"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc1v8_hdmi: LDO_REG2 { - regulator-name = "vcc1v8_hdmi"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcca_1v8: LDO_REG3 { - regulator-name = "vcca_1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc_sdio: LDO_REG4 { - regulator-name = "vcc_sdio"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3000000>; - }; - }; - - vcca3v0_codec: LDO_REG5 { - regulator-name = "vcca3v0_codec"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v5: LDO_REG6 { - regulator-name = "vcc_1v5"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1500000>; - }; - }; - - vcc0v9_hdmi: LDO_REG7 { - regulator-name = "vcc0v9_hdmi"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_3v0: LDO_REG8 { - regulator-name = "vcc_3v0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3000000>; - }; - }; - - vcc_cam: SWITCH_REG1 { - regulator-name = "vcc_cam"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_mipi: SWITCH_REG2 { - regulator-name = "vcc_mipi"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; - - vdd_cpu_b: regulator@40 { - compatible = "silergy,syr827"; - reg = <0x40>; - fcs,suspend-voltage-selector = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&vsel1_gpio>; - regulator-name = "vdd_cpu_b"; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1500000>; - regulator-ramp-delay = <1000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_gpu: regulator@41 { - compatible = "silergy,syr828"; - reg = <0x41>; - fcs,suspend-voltage-selector = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&vsel2_gpio>; - regulator-name = "vdd_gpu"; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1500000>; - regulator-ramp-delay = <1000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&i2c1 { - i2c-scl-rising-time-ns = <300>; - i2c-scl-falling-time-ns = <15>; - status = "okay"; -}; - -&i2c3 { - i2c-scl-rising-time-ns = <450>; - i2c-scl-falling-time-ns = <15>; - status = "okay"; -}; - -&i2c4 { - i2c-scl-rising-time-ns = <600>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; -}; - -&i2s0 { - rockchip,playback-channels = <8>; - rockchip,capture-channels = <8>; - status = "okay"; -}; - -&i2s1 { - rockchip,playback-channels = <2>; - rockchip,capture-channels = <2>; - status = "okay"; -}; - -&i2s2 { - status = "okay"; -}; - -&io_domains { - status = "okay"; - - bt656-supply = <&vcc_3v0>; - audio-supply = <&vcc_3v0>; - sdmmc-supply = <&vcc_sdio>; - gpio1830-supply = <&vcc_3v0>; -}; - -&pmu_io_domains { - status = "okay"; - - pmu1830-supply = <&vcc_3v0>; -}; - -&pcie_phy { - status = "okay"; -}; - -&pcie0 { - ep-gpios = <&gpio4 RK_PD3 GPIO_ACTIVE_HIGH>; - max-link-speed = <2>; - num-lanes = <4>; - pinctrl-0 = <&pcie_clkreqnb_cpm>; - pinctrl-names = "default"; - vpcie0v9-supply = <&vcc_0v9>; - vpcie1v8-supply = <&vcc_1v8>; - vpcie3v3-supply = <&vcc3v3_pcie>; - status = "okay"; -}; - -&pinctrl { - bt { - bt_enable_h: bt-enable-h { - rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_host_wake_l: bt-host-wake-l { - rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_wake_l: bt-wake-l { - rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pcie { - pcie_pwr_en: pcie-pwr-en { - rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - sdio0 { - sdio0_bus4: sdio0-bus4 { - rockchip,pins = <2 RK_PC4 1 &pcfg_pull_up_20ma>, - <2 RK_PC5 1 &pcfg_pull_up_20ma>, - <2 RK_PC6 1 &pcfg_pull_up_20ma>, - <2 RK_PC7 1 &pcfg_pull_up_20ma>; - }; - - sdio0_cmd: sdio0-cmd { - rockchip,pins = <2 RK_PD0 1 &pcfg_pull_up_20ma>; - }; - - sdio0_clk: sdio0-clk { - rockchip,pins = <2 RK_PD1 1 &pcfg_pull_none_20ma>; - }; - }; - - pmic { - pmic_int_l: pmic-int-l { - rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - vsel1_gpio: vsel1-gpio { - rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - vsel2_gpio: vsel2-gpio { - rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; - - usb-typec { - vcc5v0_typec_en: vcc5v0-typec-en { - rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - usb2 { - vcc5v0_host_en: vcc5v0-host-en { - rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - wifi { - wifi_enable_h: wifi-enable-h { - rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - wifi_host_wake_l: wifi-host-wake-l { - rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&pwm2 { - status = "okay"; -}; - -&saradc { - status = "okay"; - - vref-supply = <&vcc_1v8>; -}; - -&sdio0 { - #address-cells = <1>; - #size-cells = <0>; - bus-width = <4>; - clock-frequency = <50000000>; - cap-sdio-irq; - cap-sd-highspeed; - keep-power-in-suspend; - mmc-pwrseq = <&sdio_pwrseq>; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; - sd-uhs-sdr104; - status = "okay"; - - brcmf: wifi@1 { - compatible = "brcm,bcm4329-fmac"; - reg = <1>; - interrupt-parent = <&gpio0>; - interrupts = ; - interrupt-names = "host-wake"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_host_wake_l>; - }; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; - disable-wp; - max-frequency = <150000000>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cd &sdmmc_cmd &sdmmc_bus4>; - status = "okay"; -}; - -&sdhci { - bus-width = <8>; - mmc-hs400-1_8v; - mmc-hs400-enhanced-strobe; - non-removable; - status = "okay"; -}; - -&tcphy0 { - status = "okay"; -}; - -&tcphy1 { - status = "okay"; -}; - -&tsadc { - status = "okay"; - - /* tshut mode 0:CRU 1:GPIO */ - rockchip,hw-tshut-mode = <1>; - /* tshut polarity 0:LOW 1:HIGH */ - rockchip,hw-tshut-polarity = <1>; -}; - -&u2phy0 { - status = "okay"; - - u2phy0_otg: otg-port { - status = "okay"; - }; - - u2phy0_host: host-port { - phy-supply = <&vcc5v0_host>; - status = "okay"; - }; -}; - -&u2phy1 { - status = "okay"; - - u2phy1_otg: otg-port { - status = "okay"; - }; - - u2phy1_host: host-port { - phy-supply = <&vcc5v0_host>; - status = "okay"; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - clocks = <&rk808 1>; - clock-names = "ext_clock"; - device-wakeup-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; - host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; - shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>; - }; -}; - -&uart2 { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - -&usbdrd3_0 { - status = "okay"; -}; - -&usbdrd_dwc3_0 { - status = "okay"; - dr_mode = "otg"; -}; - -&usbdrd3_1 { - status = "okay"; -}; - -&usbdrd_dwc3_1 { - status = "okay"; - dr_mode = "host"; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&vopl { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/rockchip/rk3399-rock960.dts b/sys/gnu/dts/arm64/rockchip/rk3399-rock960.dts deleted file mode 100644 index 437a75f31ad..00000000000 --- a/sys/gnu/dts/arm64/rockchip/rk3399-rock960.dts +++ /dev/null @@ -1,180 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2018 Linaro Ltd. - */ - -/dts-v1/; -#include "rk3399-rock960.dtsi" - -/ { - model = "96boards Rock960"; - compatible = "vamrs,rock960", "rockchip,rk3399"; - - chosen { - stdout-path = "serial2:1500000n8"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&user_led1>, <&user_led2>, <&user_led3>, - <&user_led4>, <&wlan_led>, <&bt_led>; - - user_led1 { - label = "green:user1"; - gpios = <&gpio4 RK_PC2 0>; - linux,default-trigger = "heartbeat"; - }; - - user_led2 { - label = "green:user2"; - gpios = <&gpio4 RK_PC6 0>; - linux,default-trigger = "mmc0"; - }; - - user_led3 { - label = "green:user3"; - gpios = <&gpio4 RK_PD0 0>; - linux,default-trigger = "mmc1"; - }; - - user_led4 { - label = "green:user4"; - gpios = <&gpio4 RK_PD4 0>; - panic-indicator; - linux,default-trigger = "none"; - }; - - wlan_active_led { - label = "yellow:wlan"; - gpios = <&gpio4 RK_PD5 0>; - linux,default-trigger = "phy0tx"; - default-state = "off"; - }; - - bt_active_led { - label = "blue:bt"; - gpios = <&gpio4 RK_PD6 0>; - linux,default-trigger = "hci0-power"; - default-state = "off"; - }; - }; - -}; - -&pcie0 { - ep-gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_HIGH>; -}; - -&pinctrl { - leds { - user_led1: user_led1 { - rockchip,pins = - <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - user_led2: user_led2 { - rockchip,pins = - <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - user_led3: user_led3 { - rockchip,pins = - <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - user_led4: user_led4 { - rockchip,pins = - <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - wlan_led: wlan_led { - rockchip,pins = - <4 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_led: bt_led { - rockchip,pins = - <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pcie { - pcie_drv: pcie-drv { - rockchip,pins = - <2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb2 { - host_vbus_drv: host-vbus-drv { - rockchip,pins = - <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&spi0 { - /* On Low speed expansion (LS-SPI0) */ - status = "okay"; -}; - -&spi4 { - /* On High speed expansion (HS-SPI1) */ - status = "okay"; -}; - -&thermal_zones { - cpu_thermal: cpu { - polling-delay-passive = <100>; - polling-delay = <1000>; - thermal-sensors = <&tsadc 0>; - sustainable-power = <1550>; - - trips { - cpu_alert0: cpu_alert0 { - temperature = <65000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu_alert1: cpu_alert1 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu_crit: cpu_crit { - temperature = <95000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - - trip = <&cpu_alert1>; - cooling-device = - <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; -}; - -&usbdrd_dwc3_0 { - dr_mode = "otg"; -}; - -&usbdrd_dwc3_1 { - dr_mode = "host"; -}; - -&vcc3v3_pcie { - gpio = <&gpio2 5 GPIO_ACTIVE_HIGH>; -}; - -&vcc5v0_host { - gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>; -}; diff --git a/sys/gnu/dts/arm64/rockchip/rk3399-rock960.dtsi b/sys/gnu/dts/arm64/rockchip/rk3399-rock960.dtsi deleted file mode 100644 index b69f0f2cbd6..00000000000 --- a/sys/gnu/dts/arm64/rockchip/rk3399-rock960.dtsi +++ /dev/null @@ -1,664 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2018 Collabora Ltd. - * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd. - * Copyright (c) 2018 Linaro Ltd. - */ - -#include "rk3399.dtsi" -#include "rk3399-opp.dtsi" - -/ { - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&rk808 1>; - clock-names = "ext_clock"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_enable_h>; - reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; - }; - - vcc12v_dcin: vcc12v-dcin { - compatible = "regulator-fixed"; - regulator-name = "vcc12v_dcin"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-always-on; - regulator-boot-on; - }; - - vcc1v8_s0: vcc1v8-s0 { - compatible = "regulator-fixed"; - regulator-name = "vcc1v8_s0"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vcc5v0_sys: vcc5v0-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - vin-supply = <&vcc12v_dcin>; - }; - - vcc3v3_sys: vcc3v3-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_sys"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - vin-supply = <&vcc5v0_sys>; - }; - - vcc3v3_pcie: vcc3v3-pcie-regulator { - compatible = "regulator-fixed"; - enable-active-high; - pinctrl-names = "default"; - pinctrl-0 = <&pcie_drv>; - regulator-boot-on; - regulator-name = "vcc3v3_pcie"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc3v3_sys>; - }; - - vcc5v0_host: vcc5v0-host-regulator { - compatible = "regulator-fixed"; - enable-active-high; - pinctrl-names = "default"; - pinctrl-0 = <&host_vbus_drv>; - regulator-name = "vcc5v0_host"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - vin-supply = <&vcc5v0_sys>; - }; - - vcc_0v9: vcc-0v9 { - compatible = "regulator-fixed"; - regulator-name = "vcc_0v9"; - regulator-always-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - vin-supply = <&vcc3v3_sys>; - }; -}; - -&cpu_l0 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l1 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l2 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l3 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_b0 { - cpu-supply = <&vdd_cpu_b>; -}; - -&cpu_b1 { - cpu-supply = <&vdd_cpu_b>; -}; - -&emmc_phy { - status = "okay"; -}; - -&gpu { - mali-supply = <&vdd_gpu>; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c3>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_cec>; - status = "okay"; -}; - -&hdmi_sound { - status = "okay"; -}; - -&i2c0 { - clock-frequency = <400000>; - i2c-scl-rising-time-ns = <168>; - i2c-scl-falling-time-ns = <4>; - status = "okay"; - - vdd_cpu_b: regulator@40 { - compatible = "silergy,syr827"; - reg = <0x40>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_cpu_b"; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1500000>; - regulator-ramp-delay = <1000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc5v0_sys>; - status = "okay"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_gpu: regulator@41 { - compatible = "silergy,syr828"; - reg = <0x41>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_gpu"; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1500000>; - regulator-ramp-delay = <1000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc5v0_sys>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - rk808: pmic@1b { - compatible = "rockchip,rk808"; - reg = <0x1b>; - interrupt-parent = <&gpio1>; - interrupts = <21 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l>; - rockchip,system-power-controller; - wakeup-source; - #clock-cells = <1>; - clock-output-names = "xin32k", "rk808-clkout2"; - - vcc1-supply = <&vcc5v0_sys>; - vcc2-supply = <&vcc5v0_sys>; - vcc3-supply = <&vcc5v0_sys>; - vcc4-supply = <&vcc5v0_sys>; - vcc6-supply = <&vcc5v0_sys>; - vcc7-supply = <&vcc5v0_sys>; - vcc8-supply = <&vcc3v3_sys>; - vcc9-supply = <&vcc5v0_sys>; - vcc10-supply = <&vcc5v0_sys>; - vcc11-supply = <&vcc5v0_sys>; - vcc12-supply = <&vcc3v3_sys>; - vddio-supply = <&vcc_1v8>; - - regulators { - vdd_center: DCDC_REG1 { - regulator-name = "vdd_center"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_l: DCDC_REG2 { - regulator-name = "vdd_cpu_l"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_1v8: DCDC_REG4 { - regulator-name = "vcc_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc1v8_dvp: LDO_REG1 { - regulator-name = "vcc1v8_dvp"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcca1v8_hdmi: LDO_REG2 { - regulator-name = "vcca1v8_hdmi"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcca_1v8: LDO_REG3 { - regulator-name = "vcca_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc_sd: LDO_REG4 { - regulator-name = "vcc_sd"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc3v0_sd: LDO_REG5 { - regulator-name = "vcc3v0_sd"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3000000>; - }; - }; - - vcc_1v5: LDO_REG6 { - regulator-name = "vcc_1v5"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1500000>; - }; - }; - - vcca0v9_hdmi: LDO_REG7 { - regulator-name = "vcca0v9_hdmi"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <900000>; - }; - }; - - vcc_3v0: LDO_REG8 { - regulator-name = "vcc_3v0"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3000000>; - }; - }; - - vcc3v3_s3: SWITCH_REG1 { - regulator-name = "vcc3v3_s3"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc3v3_s0: SWITCH_REG2 { - regulator-name = "vcc3v3_s0"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - }; - }; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c3 { - status = "okay"; -}; - -&i2c4 { - status = "okay"; -}; - -&i2s2 { - status = "okay"; -}; - -&io_domains { - bt656-supply = <&vcc1v8_s0>; /* bt656_gpio2ab_ms */ - audio-supply = <&vcc1v8_s0>; /* audio_gpio3d4a_ms */ - sdmmc-supply = <&vcc_sd>; /* sdmmc_gpio4b_ms */ - gpio1830-supply = <&vcc_3v0>; /* gpio1833_gpio4cd_ms */ - status = "okay"; -}; - -&pcie_phy { - status = "okay"; -}; - -&pcie0 { - num-lanes = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie_clkreqn_cpm>; - vpcie0v9-supply = <&vcc_0v9>; - vpcie1v8-supply = <&vcca_1v8>; - vpcie3v3-supply = <&vcc3v3_pcie>; - status = "okay"; -}; - -&pmu_io_domains { - pmu1830-supply = <&vcc_1v8>; - status = "okay"; -}; - -&pinctrl { - bt { - bt_enable_h: bt-enable-h { - rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_host_wake_l: bt-host-wake-l { - rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_wake_l: bt-wake-l { - rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - sdmmc { - sdmmc_bus1: sdmmc-bus1 { - rockchip,pins = - <4 RK_PB0 1 &pcfg_pull_up_8ma>; - }; - - sdmmc_bus4: sdmmc-bus4 { - rockchip,pins = - <4 RK_PB0 1 &pcfg_pull_up_8ma>, - <4 RK_PB1 1 &pcfg_pull_up_8ma>, - <4 RK_PB2 1 &pcfg_pull_up_8ma>, - <4 RK_PB3 1 &pcfg_pull_up_8ma>; - }; - - sdmmc_clk: sdmmc-clk { - rockchip,pins = - <4 RK_PB4 1 &pcfg_pull_none_18ma>; - }; - - sdmmc_cmd: sdmmc-cmd { - rockchip,pins = - <4 RK_PB5 1 &pcfg_pull_up_8ma>; - }; - }; - - sdio0 { - sdio0_bus4: sdio0-bus4 { - rockchip,pins = - <2 RK_PC4 1 &pcfg_pull_up_20ma>, - <2 RK_PC5 1 &pcfg_pull_up_20ma>, - <2 RK_PC6 1 &pcfg_pull_up_20ma>, - <2 RK_PC7 1 &pcfg_pull_up_20ma>; - }; - - sdio0_cmd: sdio0-cmd { - rockchip,pins = - <2 RK_PD0 1 &pcfg_pull_up_20ma>; - }; - - sdio0_clk: sdio0-clk { - rockchip,pins = - <2 RK_PD1 1 &pcfg_pull_none_20ma>; - }; - }; - - pmic { - pmic_int_l: pmic-int-l { - rockchip,pins = - <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - vsel1_gpio: vsel1-gpio { - rockchip,pins = - <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - vsel2_gpio: vsel2-gpio { - rockchip,pins = - <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; - - sdio-pwrseq { - wifi_enable_h: wifi-enable-h { - rockchip,pins = - <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - wifi { - wifi_host_wake_l: wifi-host-wake-l { - rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&pwm2 { - status = "okay"; -}; - -&pwm3 { - status = "okay"; -}; - -&sdio0 { - bus-width = <4>; - clock-frequency = <50000000>; - cap-sdio-irq; - cap-sd-highspeed; - keep-power-in-suspend; - mmc-pwrseq = <&sdio_pwrseq>; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; - sd-uhs-sdr104; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - brcmf: wifi@1 { - compatible = "brcm,bcm4329-fmac"; - reg = <1>; - interrupt-parent = <&gpio0>; - interrupts = ; - interrupt-names = "host-wake"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_host_wake_l>; - }; -}; - -&sdhci { - bus-width = <8>; - mmc-hs400-1_8v; - mmc-hs400-enhanced-strobe; - non-removable; - status = "okay"; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - clock-frequency = <100000000>; - clock-freq-min-max = <100000 100000000>; - cd-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>; - disable-wp; - sd-uhs-sdr104; - vqmmc-supply = <&vcc_sd>; - card-detect-delay = <800>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; - status = "okay"; -}; - -&tsadc { - rockchip,hw-tshut-mode = <1>; - rockchip,hw-tshut-polarity = <1>; - rockchip,hw-tshut-temp = <110000>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - clocks = <&rk808 1>; - clock-names = "ext_clock"; - device-wakeup-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; - host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; - shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>; - }; -}; - -&uart2 { - status = "okay"; -}; - -&tcphy0 { - status = "okay"; -}; - -&tcphy1 { - status = "okay"; -}; - -&u2phy0 { - status = "okay"; -}; - -&u2phy1 { - status = "okay"; -}; - -&u2phy0_host { - phy-supply = <&vcc5v0_host>; - status = "okay"; -}; - -&u2phy1_host { - phy-supply = <&vcc5v0_host>; - status = "okay"; -}; - -&u2phy0_otg { - status = "okay"; -}; - -&u2phy1_otg { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - -&usbdrd3_0 { - status = "okay"; -}; - -&usbdrd_dwc3_0 { - status = "okay"; -}; - -&usbdrd3_1 { - status = "okay"; -}; - -&usbdrd_dwc3_1 { - status = "okay"; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&vopl { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/rockchip/rk3399-rockpro64-v2.dts b/sys/gnu/dts/arm64/rockchip/rk3399-rockpro64-v2.dts deleted file mode 100644 index 304e3c51391..00000000000 --- a/sys/gnu/dts/arm64/rockchip/rk3399-rockpro64-v2.dts +++ /dev/null @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd. - * Copyright (c) 2018 Akash Gajjar - * Copyright (c) 2019 Katsuhiro Suzuki - */ - -/dts-v1/; -#include "rk3399-rockpro64.dtsi" - -/ { - model = "Pine64 RockPro64 v2.0"; - compatible = "pine64,rockpro64-v2.0", "pine64,rockpro64", "rockchip,rk3399"; -}; - -&i2c1 { - es8316: codec@10 { - compatible = "everest,es8316"; - reg = <0x10>; - clocks = <&cru SCLK_I2S_8CH_OUT>; - clock-names = "mclk"; - #sound-dai-cells = <0>; - - port { - es8316_p0_0: endpoint { - remote-endpoint = <&i2s1_p0_0>; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/rockchip/rk3399-rockpro64.dts b/sys/gnu/dts/arm64/rockchip/rk3399-rockpro64.dts deleted file mode 100644 index 4b42717800f..00000000000 --- a/sys/gnu/dts/arm64/rockchip/rk3399-rockpro64.dts +++ /dev/null @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd. - * Copyright (c) 2018 Akash Gajjar - * Copyright (c) 2019 Katsuhiro Suzuki - */ - -/dts-v1/; -#include "rk3399-rockpro64.dtsi" - -/ { - model = "Pine64 RockPro64 v2.1"; - compatible = "pine64,rockpro64-v2.1", "pine64,rockpro64", "rockchip,rk3399"; -}; - -&i2c1 { - es8316: codec@11 { - compatible = "everest,es8316"; - reg = <0x11>; - clocks = <&cru SCLK_I2S_8CH_OUT>; - clock-names = "mclk"; - #sound-dai-cells = <0>; - - port { - es8316_p0_0: endpoint { - remote-endpoint = <&i2s1_p0_0>; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/rockchip/rk3399-rockpro64.dtsi b/sys/gnu/dts/arm64/rockchip/rk3399-rockpro64.dtsi deleted file mode 100644 index 9bca2580126..00000000000 --- a/sys/gnu/dts/arm64/rockchip/rk3399-rockpro64.dtsi +++ /dev/null @@ -1,797 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd. - * Copyright (c) 2018 Akash Gajjar - */ - -#include -#include -#include "rk3399.dtsi" -#include "rk3399-opp.dtsi" - -/ { - chosen { - stdout-path = "serial2:1500000n8"; - }; - - clkin_gmac: external-gmac-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "clkin_gmac"; - #clock-cells = <0>; - }; - - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - pinctrl-names = "default"; - pinctrl-0 = <&pwrbtn>; - - power { - debounce-interval = <100>; - gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; - label = "GPIO Key Power"; - linux,code = ; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&work_led_gpio>, <&diy_led_gpio>; - - work-led { - label = "work"; - default-state = "on"; - gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>; - }; - - diy-led { - label = "diy"; - default-state = "off"; - gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; - }; - }; - - fan: pwm-fan { - compatible = "pwm-fan"; - #cooling-cells = <2>; - fan-supply = <&vcc12v_dcin>; - pwms = <&pwm1 0 50000 0>; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&rk808 1>; - clock-names = "ext_clock"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_enable_h>; - reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; - }; - - sound { - compatible = "audio-graph-card"; - label = "rockchip,rk3399"; - dais = <&i2s1_p0>; - }; - - vcc12v_dcin: vcc12v-dcin { - compatible = "regulator-fixed"; - regulator-name = "vcc12v_dcin"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - /* switched by pmic_sleep */ - vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 { - compatible = "regulator-fixed"; - regulator-name = "vcc1v8_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_1v8>; - }; - - vcc3v3_pcie: vcc3v3-pcie-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie_pwr_en>; - regulator-name = "vcc3v3_pcie"; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc12v_dcin>; - }; - - vcc3v3_sys: vcc3v3-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc5v0_sys>; - }; - - /* Actually 3 regulators (host0, 1, 2) controlled by the same gpio */ - vcc5v0_host: vcc5v0-host-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_host_en>; - regulator-name = "vcc5v0_host"; - regulator-always-on; - vin-supply = <&vcc5v0_usb>; - }; - - vcc5v0_typec: vcc5v0-typec-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_typec_en>; - regulator-name = "vcc5v0_typec"; - regulator-always-on; - vin-supply = <&vcc5v0_usb>; - }; - - vcc5v0_sys: vcc5v0-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc12v_dcin>; - }; - - vcc5v0_usb: vcc5v0-usb { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_usb"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc12v_dcin>; - }; - - vdd_log: vdd-log { - compatible = "pwm-regulator"; - pwms = <&pwm2 0 25000 1>; - regulator-name = "vdd_log"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1700000>; - vin-supply = <&vcc5v0_sys>; - }; -}; - -&cpu_l0 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l1 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l2 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l3 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_b0 { - cpu-supply = <&vdd_cpu_b>; -}; - -&cpu_b1 { - cpu-supply = <&vdd_cpu_b>; -}; - -&emmc_phy { - status = "okay"; -}; - -&gmac { - assigned-clocks = <&cru SCLK_RMII_SRC>; - assigned-clock-parents = <&clkin_gmac>; - clock_in_out = "input"; - phy-supply = <&vcc_lan>; - phy-mode = "rgmii"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 50000>; - tx_delay = <0x28>; - rx_delay = <0x11>; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c3>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_cec>; - status = "okay"; -}; - -&hdmi_sound { - status = "okay"; -}; - -&gpu { - mali-supply = <&vdd_gpu>; - status = "okay"; -}; - -&i2c0 { - clock-frequency = <400000>; - i2c-scl-rising-time-ns = <168>; - i2c-scl-falling-time-ns = <4>; - status = "okay"; - - rk808: pmic@1b { - compatible = "rockchip,rk808"; - reg = <0x1b>; - interrupt-parent = <&gpio3>; - interrupts = <10 IRQ_TYPE_LEVEL_LOW>; - #clock-cells = <1>; - clock-output-names = "xin32k", "rk808-clkout2"; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l>; - rockchip,system-power-controller; - wakeup-source; - - vcc1-supply = <&vcc5v0_sys>; - vcc2-supply = <&vcc5v0_sys>; - vcc3-supply = <&vcc5v0_sys>; - vcc4-supply = <&vcc5v0_sys>; - vcc6-supply = <&vcc5v0_sys>; - vcc7-supply = <&vcc5v0_sys>; - vcc8-supply = <&vcc3v3_sys>; - vcc9-supply = <&vcc5v0_sys>; - vcc10-supply = <&vcc5v0_sys>; - vcc11-supply = <&vcc5v0_sys>; - vcc12-supply = <&vcc3v3_sys>; - vddio-supply = <&vcca_1v8>; - - regulators { - vdd_center: DCDC_REG1 { - regulator-name = "vdd_center"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_l: DCDC_REG2 { - regulator-name = "vdd_cpu_l"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_1v8: DCDC_REG4 { - regulator-name = "vcc_1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc1v8_dvp: LDO_REG1 { - regulator-name = "vcc1v8_dvp"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v0_touch: LDO_REG2 { - regulator-name = "vcc3v0_touch"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcca_1v8: LDO_REG3 { - regulator-name = "vcca_1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc_sdio: LDO_REG4 { - regulator-name = "vcc_sdio"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3000000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3000000>; - }; - }; - - vcca3v0_codec: LDO_REG5 { - regulator-name = "vcca3v0_codec"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v5: LDO_REG6 { - regulator-name = "vcc_1v5"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1500000>; - }; - }; - - vcca1v8_codec: LDO_REG7 { - regulator-name = "vcca1v8_codec"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_3v0: LDO_REG8 { - regulator-name = "vcc_3v0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3000000>; - }; - }; - - vcc3v3_s3: vcc_lan: SWITCH_REG1 { - regulator-name = "vcc3v3_s3"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v3_s0: SWITCH_REG2 { - regulator-name = "vcc3v3_s0"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; - - vdd_cpu_b: regulator@40 { - compatible = "silergy,syr827"; - reg = <0x40>; - fcs,suspend-voltage-selector = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&vsel1_gpio>; - regulator-name = "vdd_cpu_b"; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1500000>; - regulator-ramp-delay = <1000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_gpu: regulator@41 { - compatible = "silergy,syr828"; - reg = <0x41>; - fcs,suspend-voltage-selector = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&vsel2_gpio>; - regulator-name = "vdd_gpu"; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1500000>; - regulator-ramp-delay = <1000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&i2c1 { - i2c-scl-rising-time-ns = <300>; - i2c-scl-falling-time-ns = <15>; - status = "okay"; -}; - -&i2c3 { - i2c-scl-rising-time-ns = <450>; - i2c-scl-falling-time-ns = <15>; - status = "okay"; -}; - -&i2c4 { - i2c-scl-rising-time-ns = <600>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; - - fusb0: typec-portc@22 { - compatible = "fcs,fusb302"; - reg = <0x22>; - interrupt-parent = <&gpio1>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&fusb0_int>; - vbus-supply = <&vcc5v0_typec>; - status = "okay"; - }; -}; - -&i2s0 { - rockchip,playback-channels = <8>; - rockchip,capture-channels = <8>; - status = "okay"; -}; - -&i2s1 { - rockchip,playback-channels = <2>; - rockchip,capture-channels = <2>; - status = "okay"; - - i2s1_p0: port { - i2s1_p0_0: endpoint { - dai-format = "i2s"; - mclk-fs = <256>; - remote-endpoint = <&es8316_p0_0>; - }; - }; -}; - -&i2s2 { - status = "okay"; -}; - -&io_domains { - status = "okay"; - - bt656-supply = <&vcc1v8_dvp>; - audio-supply = <&vcc_3v0>; - sdmmc-supply = <&vcc_sdio>; - gpio1830-supply = <&vcc_3v0>; -}; - -&pcie0 { - ep-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>; - num-lanes = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie_perst>; - vpcie12v-supply = <&vcc12v_dcin>; - vpcie3v3-supply = <&vcc3v3_pcie>; - status = "okay"; -}; - -&pcie_phy { - status = "okay"; -}; - -&pmu_io_domains { - pmu1830-supply = <&vcc_3v0>; - status = "okay"; -}; - -&pinctrl { - bt { - bt_enable_h: bt-enable-h { - rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_host_wake_l: bt-host-wake-l { - rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - bt_wake_l: bt-wake-l { - rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - buttons { - pwrbtn: pwrbtn { - rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - fusb302x { - fusb0_int: fusb0-int { - rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - leds { - work_led_gpio: work_led-gpio { - rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - diy_led_gpio: diy_led-gpio { - rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pcie { - pcie_perst: pcie-perst { - rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - pcie_pwr_en: pcie-pwr-en { - rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - pmic_int_l: pmic-int-l { - rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - vsel1_gpio: vsel1-gpio { - rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - vsel2_gpio: vsel2-gpio { - rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; - - sdio-pwrseq { - wifi_enable_h: wifi-enable-h { - rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb-typec { - vcc5v0_typec_en: vcc5v0_typec_en { - rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - usb2 { - vcc5v0_host_en: vcc5v0-host-en { - rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&pwm0 { - status = "okay"; -}; - -&pwm1 { - status = "okay"; -}; - -&pwm2 { - status = "okay"; -}; - -&saradc { - vref-supply = <&vcca1v8_s3>; - status = "okay"; -}; - -&sdio0 { - bus-width = <4>; - cap-sd-highspeed; - cap-sdio-irq; - disable-wp; - keep-power-in-suspend; - mmc-pwrseq = <&sdio_pwrseq>; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; - sd-uhs-sdr104; - status = "okay"; -}; - -&sdmmc { - bus-width = <4>; - cap-sd-highspeed; - cd-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>; - disable-wp; - max-frequency = <150000000>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; - status = "okay"; -}; - -&sdhci { - bus-width = <8>; - mmc-hs200-1_8v; - non-removable; - status = "okay"; -}; - -&spi1 { - status = "okay"; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <10000000>; - }; -}; - -&tcphy0 { - status = "okay"; -}; - -&tcphy1 { - status = "okay"; -}; - -&tsadc { - /* tshut mode 0:CRU 1:GPIO */ - rockchip,hw-tshut-mode = <1>; - /* tshut polarity 0:LOW 1:HIGH */ - rockchip,hw-tshut-polarity = <1>; - status = "okay"; -}; - -&u2phy0 { - status = "okay"; - - u2phy0_otg: otg-port { - status = "okay"; - }; - - u2phy0_host: host-port { - phy-supply = <&vcc5v0_host>; - status = "okay"; - }; -}; - -&u2phy1 { - status = "okay"; - - u2phy1_otg: otg-port { - status = "okay"; - }; - - u2phy1_host: host-port { - phy-supply = <&vcc5v0_host>; - status = "okay"; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - clocks = <&rk808 1>; - clock-names = "lpo"; - device-wakeup-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; - host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; - shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>; - vbat-supply = <&vcc3v3_sys>; - vddio-supply = <&vcc_1v8>; - }; -}; - -&uart2 { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - -&usbdrd3_0 { - status = "okay"; -}; - -&usbdrd_dwc3_0 { - status = "okay"; - dr_mode = "otg"; -}; - -&usbdrd3_1 { - status = "okay"; -}; - -&usbdrd_dwc3_1 { - status = "okay"; - dr_mode = "host"; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&vopl { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/rockchip/rk3399-sapphire-excavator.dts b/sys/gnu/dts/arm64/rockchip/rk3399-sapphire-excavator.dts deleted file mode 100644 index b4d8f60b7e4..00000000000 --- a/sys/gnu/dts/arm64/rockchip/rk3399-sapphire-excavator.dts +++ /dev/null @@ -1,236 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd. - */ - -/dts-v1/; -#include "rk3399-sapphire.dtsi" - -/ { - model = "Excavator-RK3399 Board"; - compatible = "rockchip,rk3399-sapphire-excavator", "rockchip,rk3399"; - - adc-keys { - compatible = "adc-keys"; - io-channels = <&saradc 1>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1800000>; - poll-interval = <100>; - - button-up { - label = "Volume Up"; - linux,code = ; - press-threshold-microvolt = <100000>; - }; - - button-down { - label = "Volume Down"; - linux,code = ; - press-threshold-microvolt = <300000>; - }; - - back { - label = "Back"; - linux,code = ; - press-threshold-microvolt = <985000>; - }; - - menu { - label = "Menu"; - linux,code = ; - press-threshold-microvolt = <1314000>; - }; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - brightness-levels = < - 0 1 2 3 4 5 6 7 - 8 9 10 11 12 13 14 15 - 16 17 18 19 20 21 22 23 - 24 25 26 27 28 29 30 31 - 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 - 48 49 50 51 52 53 54 55 - 56 57 58 59 60 61 62 63 - 64 65 66 67 68 69 70 71 - 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 - 88 89 90 91 92 93 94 95 - 96 97 98 99 100 101 102 103 - 104 105 106 107 108 109 110 111 - 112 113 114 115 116 117 118 119 - 120 121 122 123 124 125 126 127 - 128 129 130 131 132 133 134 135 - 136 137 138 139 140 141 142 143 - 144 145 146 147 148 149 150 151 - 152 153 154 155 156 157 158 159 - 160 161 162 163 164 165 166 167 - 168 169 170 171 172 173 174 175 - 176 177 178 179 180 181 182 183 - 184 185 186 187 188 189 190 191 - 192 193 194 195 196 197 198 199 - 200 201 202 203 204 205 206 207 - 208 209 210 211 212 213 214 215 - 216 217 218 219 220 221 222 223 - 224 225 226 227 228 229 230 231 - 232 233 234 235 236 237 238 239 - 240 241 242 243 244 245 246 247 - 248 249 250 251 252 253 254 255>; - default-brightness-level = <200>; - enable-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>; - pwms = <&pwm0 0 25000 0>; - status = "okay"; - }; - - edp_panel: edp-panel { - compatible ="lg,lp079qx1-sp0v"; - backlight = <&backlight>; - enable-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&lcd_panel_reset>; - power-supply = <&vcc3v3_s0>; - - port { - panel_in_edp: endpoint { - remote-endpoint = <&edp_out_panel>; - }; - }; - }; - - rt5651-sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "realtek,rt5651-codec"; - simple-audio-card,format = "i2s"; - simple-audio-card,mclk-fs = <256>; - simple-audio-card,widgets = - "Microphone", "Mic Jack", - "Headphone", "Headphone Jack"; - simple-audio-card,routing = - "Mic Jack", "MICBIAS1", - "IN1P", "Mic Jack", - "Headphone Jack", "HPOL", - "Headphone Jack", "HPOR"; - simple-audio-card,cpu { - sound-dai = <&i2s0>; - }; - simple-audio-card,codec { - sound-dai = <&rt5651>; - }; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&rk808 1>; - clock-names = "ext_clock"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_enable_h>; - - /* - * On the module itself this is one of these (depending - * on the actual card populated): - * - SDIO_RESET_L_WL_REG_ON - * - PDN (power down when low) - */ - reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; - }; -}; - -&edp { - status = "okay"; - - ports { - edp_out: port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - edp_out_panel: endpoint@0 { - reg = <0>; - remote-endpoint = <&panel_in_edp>; - }; - }; - }; -}; - -&i2c1 { - i2c-scl-rising-time-ns = <300>; - i2c-scl-falling-time-ns = <15>; - status = "okay"; - - rt5651: rt5651@1a { - compatible = "rockchip,rt5651"; - reg = <0x1a>; - clocks = <&cru SCLK_I2S_8CH_OUT>; - clock-names = "mclk"; - hp-det-gpio = <&gpio4 RK_PC4 GPIO_ACTIVE_LOW>; - spk-con-gpio = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>; - #sound-dai-cells = <0>; - }; -}; - -&i2c4 { - i2c-scl-rising-time-ns = <600>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; - - accelerometer@68 { - compatible = "invensense,mpu6500"; - reg = <0x68>; - interrupt-parent = <&gpio1>; - interrupts = ; - }; -}; - -&i2s0 { - rockchip,playback-channels = <8>; - rockchip,capture-channels = <8>; - status = "okay"; -}; - -&pcie_phy { - status = "okay"; -}; - -&pcie0 { - ep-gpios = <&gpio2 RK_PA4 GPIO_ACTIVE_HIGH>; - num-lanes = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie_clkreqn_cpm>; - status = "okay"; -}; - -&pinctrl { - sdio-pwrseq { - wifi_enable_h: wifi-enable-h { - rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - lcd-panel { - lcd_panel_reset: lcd-panel-reset { - rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; -}; - -&sdio0 { - bus-width = <4>; - cap-sd-highspeed; - cap-sdio-irq; - clock-frequency = <50000000>; - keep-power-in-suspend; - max-frequency = <50000000>; - mmc-pwrseq = <&sdio_pwrseq>; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; - sd-uhs-sdr104; - status = "okay"; -}; - -&spdif { - i2c-scl-rising-time-ns = <450>; - i2c-scl-falling-time-ns = <15>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/rockchip/rk3399-sapphire.dts b/sys/gnu/dts/arm64/rockchip/rk3399-sapphire.dts deleted file mode 100644 index 5a58060447c..00000000000 --- a/sys/gnu/dts/arm64/rockchip/rk3399-sapphire.dts +++ /dev/null @@ -1,12 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd. - */ - -/dts-v1/; -#include "rk3399-sapphire.dtsi" - -/ { - model = "Sapphire-RK3399 Board"; - compatible = "rockchip,rk3399-sapphire", "rockchip,rk3399"; -}; diff --git a/sys/gnu/dts/arm64/rockchip/rk3399-sapphire.dtsi b/sys/gnu/dts/arm64/rockchip/rk3399-sapphire.dtsi deleted file mode 100644 index 1bc1579674e..00000000000 --- a/sys/gnu/dts/arm64/rockchip/rk3399-sapphire.dtsi +++ /dev/null @@ -1,648 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd. - */ - -#include "dt-bindings/pwm/pwm.h" -#include "dt-bindings/input/input.h" -#include "rk3399.dtsi" -#include "rk3399-opp.dtsi" - -/ { - compatible = "rockchip,rk3399-sapphire", "rockchip,rk3399"; - - chosen { - stdout-path = "serial2:1500000n8"; - }; - - clkin_gmac: external-gmac-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "clkin_gmac"; - #clock-cells = <0>; - }; - - dc_12v: dc-12v { - compatible = "regulator-fixed"; - regulator-name = "dc_12v"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - /* - * The fan power supply comes from the baseboard. - * For the standalone Sapphire one option is to connect a wire - * from R90030 DNP R0805 pin2 to C90002 10uF C0805 pin1 (vcc_sys). - */ - fan0: gpio-fan { - #cooling-cells = <2>; - compatible = "gpio-fan"; - gpio-fan,speed-map = <0 0 3000 1>; - gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - keys: gpio-keys { - compatible = "gpio-keys"; - autorepeat; - - power { - debounce-interval = <100>; - gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; - label = "GPIO Power"; - linux,code = ; - linux,input-type = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&pwr_btn>; - wakeup-source; - }; - }; - - /* switched by pmic_sleep */ - vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 { - compatible = "regulator-fixed"; - regulator-name = "vcc1v8_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_1v8>; - }; - - vcc3v0_sd: vcc3v0-sd { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc0_pwr_h>; - regulator-always-on; - regulator-max-microvolt = <3000000>; - regulator-min-microvolt = <3000000>; - regulator-name = "vcc3v0_sd"; - vin-supply = <&vcc3v3_sys>; - }; - - vcc3v3_sys: vcc3v3-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_sys>; - }; - - vcc5v0_host: vcc5v0-host-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_host_en>; - regulator-name = "vcc5v0_host"; - regulator-always-on; - vin-supply = <&vcc_sys>; - }; - - vcc5v0_typec0: vcc5v0-typec0-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio2 RK_PA0 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_typec0_en>; - regulator-name = "vcc5v0_typec0"; - vin-supply = <&vcc_sys>; - }; - - vcc_sys: vcc-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&dc_12v>; - }; - - vdd_log: vdd-log { - compatible = "pwm-regulator"; - pwms = <&pwm2 0 25000 1>; - regulator-name = "vdd_log"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - vin-supply = <&vcc_sys>; - }; -}; - -&cpu_l0 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l1 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l2 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l3 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_b0 { - cpu-supply = <&vdd_cpu_b>; -}; - -&cpu_b1 { - cpu-supply = <&vdd_cpu_b>; -}; - -&cpu_thermal { - trips { - cpu_hot: cpu_hot { - hysteresis = <10000>; - temperature = <55000>; - type = "active"; - }; - }; - - cooling-maps { - map2 { - cooling-device = - <&fan0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - trip = <&cpu_hot>; - }; - }; -}; - -&emmc_phy { - status = "okay"; -}; - -&gmac { - assigned-clocks = <&cru SCLK_RMII_SRC>; - assigned-clock-parents = <&clkin_gmac>; - clock_in_out = "input"; - phy-supply = <&vcc_lan>; - phy-mode = "rgmii"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 50000>; - tx_delay = <0x28>; - rx_delay = <0x11>; - status = "okay"; -}; - -&gpu { - mali-supply = <&vdd_gpu>; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c3>; - status = "okay"; -}; - -&hdmi_sound { - status = "okay"; -}; - -&i2c0 { - clock-frequency = <400000>; - i2c-scl-rising-time-ns = <168>; - i2c-scl-falling-time-ns = <4>; - status = "okay"; - - rk808: pmic@1b { - compatible = "rockchip,rk808"; - reg = <0x1b>; - interrupt-parent = <&gpio1>; - interrupts = <21 IRQ_TYPE_LEVEL_LOW>; - #clock-cells = <1>; - clock-output-names = "xin32k", "rk808-clkout2"; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l>; - rockchip,system-power-controller; - wakeup-source; - - vcc1-supply = <&vcc_sys>; - vcc2-supply = <&vcc_sys>; - vcc3-supply = <&vcc_sys>; - vcc4-supply = <&vcc_sys>; - vcc6-supply = <&vcc_sys>; - vcc7-supply = <&vcc_sys>; - vcc8-supply = <&vcc3v3_sys>; - vcc9-supply = <&vcc_sys>; - vcc10-supply = <&vcc_sys>; - vcc11-supply = <&vcc_sys>; - vcc12-supply = <&vcc3v3_sys>; - vddio-supply = <&vcc1v8_pmu>; - - regulators { - vdd_center: DCDC_REG1 { - regulator-name = "vdd_center"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_l: DCDC_REG2 { - regulator-name = "vdd_cpu_l"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_1v8: DCDC_REG4 { - regulator-name = "vcc_1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc1v8_dvp: LDO_REG1 { - regulator-name = "vcc1v8_dvp"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v0_tp: LDO_REG2 { - regulator-name = "vcc3v0_tp"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc1v8_pmu: LDO_REG3 { - regulator-name = "vcc1v8_pmu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc_sdio: LDO_REG4 { - regulator-name = "vcc_sdio"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3000000>; - }; - }; - - vcca3v0_codec: LDO_REG5 { - regulator-name = "vcca3v0_codec"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v5: LDO_REG6 { - regulator-name = "vcc_1v5"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1500000>; - }; - }; - - vcca1v8_codec: LDO_REG7 { - regulator-name = "vcca1v8_codec"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_3v0: LDO_REG8 { - regulator-name = "vcc_3v0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3000000>; - }; - }; - - vcc3v3_s3: vcc_lan: SWITCH_REG1 { - regulator-name = "vcc3v3_s3"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v3_s0: SWITCH_REG2 { - regulator-name = "vcc3v3_s0"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; - - vdd_cpu_b: regulator@40 { - compatible = "silergy,syr827"; - reg = <0x40>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_cpu_b"; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1500000>; - regulator-ramp-delay = <1000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_gpu: regulator@41 { - compatible = "silergy,syr828"; - reg = <0x41>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_gpu"; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1500000>; - regulator-ramp-delay = <1000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&i2c3 { - i2c-scl-rising-time-ns = <450>; - i2c-scl-falling-time-ns = <15>; - status = "okay"; -}; - -&i2s2 { - status = "okay"; -}; - -&io_domains { - status = "okay"; - - bt656-supply = <&vcc_3v0>; - audio-supply = <&vcca1v8_codec>; - sdmmc-supply = <&vcc_sdio>; - gpio1830-supply = <&vcc_3v0>; -}; - -&pmu_io_domains { - pmu1830-supply = <&vcc_3v0>; - status = "okay"; -}; - -&pinctrl { - buttons { - pwr_btn: pwr-btn { - rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - fan { - motor_pwr: motor-pwr { - rockchip,pins = - <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - pmic_int_l: pmic-int-l { - rockchip,pins = - <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - vsel1_gpio: vsel1-gpio { - rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - vsel2_gpio: vsel2-gpio { - rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; - - sd { - sdmmc0_pwr_h: sdmmc0-pwr-h { - rockchip,pins = - <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb2 { - vcc5v0_host_en: vcc5v0-host-en { - rockchip,pins = - <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - vcc5v0_typec0_en: vcc5v0-typec0-en { - rockchip,pins = - <2 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&pwm0 { - status = "okay"; -}; - -&pwm2 { - status = "okay"; -}; - -&saradc { - vref-supply = <&vcca1v8_s3>; - status = "okay"; -}; - -&sdhci { - bus-width = <8>; - mmc-hs400-1_8v; - mmc-hs400-enhanced-strobe; - non-removable; - status = "okay"; -}; - -&sdmmc { - broken-cd; - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - clock-frequency = <150000000>; - disable-wp; - max-frequency = <150000000>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; - vmmc-supply = <&vcc3v0_sd>; - vqmmc-supply = <&vcc_sdio>; - status = "okay"; -}; - -&tcphy0 { - status = "okay"; -}; - -&tcphy1 { - status = "okay"; -}; - -&tsadc { - /* tshut mode 0:CRU 1:GPIO */ - rockchip,hw-tshut-mode = <1>; - /* tshut polarity 0:LOW 1:HIGH */ - rockchip,hw-tshut-polarity = <1>; - status = "okay"; -}; - -&u2phy0 { - status = "okay"; - - u2phy0_otg: otg-port { - status = "okay"; - }; - - u2phy0_host: host-port { - phy-supply = <&vcc5v0_typec0>; - status = "okay"; - }; -}; - -&u2phy1 { - status = "okay"; - - u2phy1_otg: otg-port { - status = "okay"; - }; - - u2phy1_host: host-port { - phy-supply = <&vcc5v0_host>; - status = "okay"; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_cts>; - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - -&usbdrd3_0 { - status = "okay"; -}; - -&usbdrd_dwc3_0 { - status = "okay"; - dr_mode = "host"; -}; - -&usbdrd3_1 { - status = "okay"; -}; - -&usbdrd_dwc3_1 { - status = "okay"; - dr_mode = "host"; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&vopl { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/rockchip/rk3399.dtsi b/sys/gnu/dts/arm64/rockchip/rk3399.dtsi deleted file mode 100644 index 33cc21fcf4c..00000000000 --- a/sys/gnu/dts/arm64/rockchip/rk3399.dtsi +++ /dev/null @@ -1,2664 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd - */ - -#include -#include -#include -#include -#include -#include -#include - -/ { - compatible = "rockchip,rk3399"; - - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - ethernet0 = &gmac; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - i2c6 = &i2c6; - i2c7 = &i2c7; - i2c8 = &i2c8; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - serial4 = &uart4; - }; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu-map { - cluster0 { - core0 { - cpu = <&cpu_l0>; - }; - core1 { - cpu = <&cpu_l1>; - }; - core2 { - cpu = <&cpu_l2>; - }; - core3 { - cpu = <&cpu_l3>; - }; - }; - - cluster1 { - core0 { - cpu = <&cpu_b0>; - }; - core1 { - cpu = <&cpu_b1>; - }; - }; - }; - - cpu_l0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x0>; - enable-method = "psci"; - capacity-dmips-mhz = <485>; - clocks = <&cru ARMCLKL>; - #cooling-cells = <2>; /* min followed by max */ - dynamic-power-coefficient = <100>; - cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; - }; - - cpu_l1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x1>; - enable-method = "psci"; - capacity-dmips-mhz = <485>; - clocks = <&cru ARMCLKL>; - #cooling-cells = <2>; /* min followed by max */ - dynamic-power-coefficient = <100>; - cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; - }; - - cpu_l2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x2>; - enable-method = "psci"; - capacity-dmips-mhz = <485>; - clocks = <&cru ARMCLKL>; - #cooling-cells = <2>; /* min followed by max */ - dynamic-power-coefficient = <100>; - cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; - }; - - cpu_l3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x3>; - enable-method = "psci"; - capacity-dmips-mhz = <485>; - clocks = <&cru ARMCLKL>; - #cooling-cells = <2>; /* min followed by max */ - dynamic-power-coefficient = <100>; - cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; - }; - - cpu_b0: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x0 0x100>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - clocks = <&cru ARMCLKB>; - #cooling-cells = <2>; /* min followed by max */ - dynamic-power-coefficient = <436>; - cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; - }; - - cpu_b1: cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x0 0x101>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - clocks = <&cru ARMCLKB>; - #cooling-cells = <2>; /* min followed by max */ - dynamic-power-coefficient = <436>; - cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; - }; - - idle-states { - entry-method = "psci"; - - CPU_SLEEP: cpu-sleep { - compatible = "arm,idle-state"; - local-timer-stop; - arm,psci-suspend-param = <0x0010000>; - entry-latency-us = <120>; - exit-latency-us = <250>; - min-residency-us = <900>; - }; - - CLUSTER_SLEEP: cluster-sleep { - compatible = "arm,idle-state"; - local-timer-stop; - arm,psci-suspend-param = <0x1010000>; - entry-latency-us = <400>; - exit-latency-us = <500>; - min-residency-us = <2000>; - }; - }; - }; - - display-subsystem { - compatible = "rockchip,display-subsystem"; - ports = <&vopl_out>, <&vopb_out>; - }; - - pmu_a53 { - compatible = "arm,cortex-a53-pmu"; - interrupts = ; - }; - - pmu_a72 { - compatible = "arm,cortex-a72-pmu"; - interrupts = ; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - arm,no-tick-in-suspend; - }; - - xin24m: xin24m { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "xin24m"; - #clock-cells = <0>; - }; - - amba { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - dmac_bus: dma-controller@ff6d0000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x0 0xff6d0000 0x0 0x4000>; - interrupts = , - ; - #dma-cells = <1>; - clocks = <&cru ACLK_DMAC0_PERILP>; - clock-names = "apb_pclk"; - }; - - dmac_peri: dma-controller@ff6e0000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x0 0xff6e0000 0x0 0x4000>; - interrupts = , - ; - #dma-cells = <1>; - clocks = <&cru ACLK_DMAC1_PERILP>; - clock-names = "apb_pclk"; - }; - }; - - pcie0: pcie@f8000000 { - compatible = "rockchip,rk3399-pcie"; - reg = <0x0 0xf8000000 0x0 0x2000000>, - <0x0 0xfd000000 0x0 0x1000000>; - reg-names = "axi-base", "apb-base"; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - aspm-no-l0s; - bus-range = <0x0 0x1f>; - clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>, - <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>; - clock-names = "aclk", "aclk-perf", - "hclk", "pm"; - interrupts = , - , - ; - interrupt-names = "sys", "legacy", "client"; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie0_intc 0>, - <0 0 0 2 &pcie0_intc 1>, - <0 0 0 3 &pcie0_intc 2>, - <0 0 0 4 &pcie0_intc 3>; - linux,pci-domain = <0>; - max-link-speed = <1>; - msi-map = <0x0 &its 0x0 0x1000>; - phys = <&pcie_phy 0>, <&pcie_phy 1>, - <&pcie_phy 2>, <&pcie_phy 3>; - phy-names = "pcie-phy-0", "pcie-phy-1", - "pcie-phy-2", "pcie-phy-3"; - ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x1e00000 - 0x81000000 0x0 0xfbe00000 0x0 0xfbe00000 0x0 0x100000>; - resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>, - <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>, - <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, - <&cru SRST_A_PCIE>; - reset-names = "core", "mgmt", "mgmt-sticky", "pipe", - "pm", "pclk", "aclk"; - status = "disabled"; - - pcie0_intc: interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - }; - }; - - gmac: ethernet@fe300000 { - compatible = "rockchip,rk3399-gmac"; - reg = <0x0 0xfe300000 0x0 0x10000>; - interrupts = ; - interrupt-names = "macirq"; - clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>, - <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>, - <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>, - <&cru PCLK_GMAC>; - clock-names = "stmmaceth", "mac_clk_rx", - "mac_clk_tx", "clk_mac_ref", - "clk_mac_refout", "aclk_mac", - "pclk_mac"; - power-domains = <&power RK3399_PD_GMAC>; - resets = <&cru SRST_A_GMAC>; - reset-names = "stmmaceth"; - rockchip,grf = <&grf>; - status = "disabled"; - }; - - sdio0: mmc@fe310000 { - compatible = "rockchip,rk3399-dw-mshc", - "rockchip,rk3288-dw-mshc"; - reg = <0x0 0xfe310000 0x0 0x4000>; - interrupts = ; - max-frequency = <150000000>; - clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, - <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - power-domains = <&power RK3399_PD_SDIOAUDIO>; - resets = <&cru SRST_SDIO0>; - reset-names = "reset"; - status = "disabled"; - }; - - sdmmc: mmc@fe320000 { - compatible = "rockchip,rk3399-dw-mshc", - "rockchip,rk3288-dw-mshc"; - reg = <0x0 0xfe320000 0x0 0x4000>; - interrupts = ; - max-frequency = <150000000>; - assigned-clocks = <&cru HCLK_SD>; - assigned-clock-rates = <200000000>; - clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, - <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - power-domains = <&power RK3399_PD_SD>; - resets = <&cru SRST_SDMMC>; - reset-names = "reset"; - status = "disabled"; - }; - - sdhci: sdhci@fe330000 { - compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1"; - reg = <0x0 0xfe330000 0x0 0x10000>; - interrupts = ; - arasan,soc-ctl-syscon = <&grf>; - assigned-clocks = <&cru SCLK_EMMC>; - assigned-clock-rates = <200000000>; - clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>; - clock-names = "clk_xin", "clk_ahb"; - clock-output-names = "emmc_cardclock"; - #clock-cells = <0>; - phys = <&emmc_phy>; - phy-names = "phy_arasan"; - power-domains = <&power RK3399_PD_EMMC>; - disable-cqe-dcmd; - status = "disabled"; - }; - - usb_host0_ehci: usb@fe380000 { - compatible = "generic-ehci"; - reg = <0x0 0xfe380000 0x0 0x20000>; - interrupts = ; - clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>, - <&u2phy0>; - clock-names = "usbhost", "arbiter", - "utmi"; - phys = <&u2phy0_host>; - phy-names = "usb"; - status = "disabled"; - }; - - usb_host0_ohci: usb@fe3a0000 { - compatible = "generic-ohci"; - reg = <0x0 0xfe3a0000 0x0 0x20000>; - interrupts = ; - clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>, - <&u2phy0>; - clock-names = "usbhost", "arbiter", - "utmi"; - phys = <&u2phy0_host>; - phy-names = "usb"; - status = "disabled"; - }; - - usb_host1_ehci: usb@fe3c0000 { - compatible = "generic-ehci"; - reg = <0x0 0xfe3c0000 0x0 0x20000>; - interrupts = ; - clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>, - <&u2phy1>; - clock-names = "usbhost", "arbiter", - "utmi"; - phys = <&u2phy1_host>; - phy-names = "usb"; - status = "disabled"; - }; - - usb_host1_ohci: usb@fe3e0000 { - compatible = "generic-ohci"; - reg = <0x0 0xfe3e0000 0x0 0x20000>; - interrupts = ; - clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>, - <&u2phy1>; - clock-names = "usbhost", "arbiter", - "utmi"; - phys = <&u2phy1_host>; - phy-names = "usb"; - status = "disabled"; - }; - - usbdrd3_0: usb@fe800000 { - compatible = "rockchip,rk3399-dwc3"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>, - <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>, - <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>; - clock-names = "ref_clk", "suspend_clk", - "bus_clk", "aclk_usb3_rksoc_axi_perf", - "aclk_usb3", "grf_clk"; - resets = <&cru SRST_A_USB3_OTG0>; - reset-names = "usb3-otg"; - status = "disabled"; - - usbdrd_dwc3_0: dwc3 { - compatible = "snps,dwc3"; - reg = <0x0 0xfe800000 0x0 0x100000>; - interrupts = ; - clocks = <&cru SCLK_USB3OTG0_REF>, <&cru ACLK_USB3OTG0>, - <&cru SCLK_USB3OTG0_SUSPEND>; - clock-names = "ref", "bus_early", "suspend"; - dr_mode = "otg"; - phys = <&u2phy0_otg>, <&tcphy0_usb3>; - phy-names = "usb2-phy", "usb3-phy"; - phy_type = "utmi_wide"; - snps,dis_enblslpm_quirk; - snps,dis-u2-freeclk-exists-quirk; - snps,dis_u2_susphy_quirk; - snps,dis-del-phy-power-chg-quirk; - snps,dis-tx-ipgap-linecheck-quirk; - power-domains = <&power RK3399_PD_USB3>; - status = "disabled"; - }; - }; - - usbdrd3_1: usb@fe900000 { - compatible = "rockchip,rk3399-dwc3"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>, - <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>, - <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>; - clock-names = "ref_clk", "suspend_clk", - "bus_clk", "aclk_usb3_rksoc_axi_perf", - "aclk_usb3", "grf_clk"; - resets = <&cru SRST_A_USB3_OTG1>; - reset-names = "usb3-otg"; - status = "disabled"; - - usbdrd_dwc3_1: dwc3 { - compatible = "snps,dwc3"; - reg = <0x0 0xfe900000 0x0 0x100000>; - interrupts = ; - clocks = <&cru SCLK_USB3OTG1_REF>, <&cru ACLK_USB3OTG1>, - <&cru SCLK_USB3OTG1_SUSPEND>; - clock-names = "ref", "bus_early", "suspend"; - dr_mode = "otg"; - phys = <&u2phy1_otg>, <&tcphy1_usb3>; - phy-names = "usb2-phy", "usb3-phy"; - phy_type = "utmi_wide"; - snps,dis_enblslpm_quirk; - snps,dis-u2-freeclk-exists-quirk; - snps,dis_u2_susphy_quirk; - snps,dis-del-phy-power-chg-quirk; - snps,dis-tx-ipgap-linecheck-quirk; - power-domains = <&power RK3399_PD_USB3>; - status = "disabled"; - }; - }; - - cdn_dp: dp@fec00000 { - compatible = "rockchip,rk3399-cdn-dp"; - reg = <0x0 0xfec00000 0x0 0x100000>; - interrupts = ; - assigned-clocks = <&cru SCLK_DP_CORE>, <&cru SCLK_SPDIF_REC_DPTX>; - assigned-clock-rates = <100000000>, <200000000>; - clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>, - <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>; - clock-names = "core-clk", "pclk", "spdif", "grf"; - phys = <&tcphy0_dp>, <&tcphy1_dp>; - power-domains = <&power RK3399_PD_HDCP>; - resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>, - <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>; - reset-names = "spdif", "dptx", "apb", "core"; - rockchip,grf = <&grf>; - #sound-dai-cells = <1>; - status = "disabled"; - - ports { - dp_in: port { - #address-cells = <1>; - #size-cells = <0>; - - dp_in_vopb: endpoint@0 { - reg = <0>; - remote-endpoint = <&vopb_out_dp>; - }; - - dp_in_vopl: endpoint@1 { - reg = <1>; - remote-endpoint = <&vopl_out_dp>; - }; - }; - }; - }; - - gic: interrupt-controller@fee00000 { - compatible = "arm,gic-v3"; - #interrupt-cells = <4>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - interrupt-controller; - - reg = <0x0 0xfee00000 0 0x10000>, /* GICD */ - <0x0 0xfef00000 0 0xc0000>, /* GICR */ - <0x0 0xfff00000 0 0x10000>, /* GICC */ - <0x0 0xfff10000 0 0x10000>, /* GICH */ - <0x0 0xfff20000 0 0x10000>; /* GICV */ - interrupts = ; - its: interrupt-controller@fee20000 { - compatible = "arm,gic-v3-its"; - msi-controller; - #msi-cells = <1>; - reg = <0x0 0xfee20000 0x0 0x20000>; - }; - - ppi-partitions { - ppi_cluster0: interrupt-partition-0 { - affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>; - }; - - ppi_cluster1: interrupt-partition-1 { - affinity = <&cpu_b0 &cpu_b1>; - }; - }; - }; - - saradc: saradc@ff100000 { - compatible = "rockchip,rk3399-saradc"; - reg = <0x0 0xff100000 0x0 0x100>; - interrupts = ; - #io-channel-cells = <1>; - clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; - clock-names = "saradc", "apb_pclk"; - resets = <&cru SRST_P_SARADC>; - reset-names = "saradc-apb"; - status = "disabled"; - }; - - i2c1: i2c@ff110000 { - compatible = "rockchip,rk3399-i2c"; - reg = <0x0 0xff110000 0x0 0x1000>; - assigned-clocks = <&cru SCLK_I2C1>; - assigned-clock-rates = <200000000>; - clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; - clock-names = "i2c", "pclk"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_xfer>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@ff120000 { - compatible = "rockchip,rk3399-i2c"; - reg = <0x0 0xff120000 0x0 0x1000>; - assigned-clocks = <&cru SCLK_I2C2>; - assigned-clock-rates = <200000000>; - clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; - clock-names = "i2c", "pclk"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_xfer>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c3: i2c@ff130000 { - compatible = "rockchip,rk3399-i2c"; - reg = <0x0 0xff130000 0x0 0x1000>; - assigned-clocks = <&cru SCLK_I2C3>; - assigned-clock-rates = <200000000>; - clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; - clock-names = "i2c", "pclk"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_xfer>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c5: i2c@ff140000 { - compatible = "rockchip,rk3399-i2c"; - reg = <0x0 0xff140000 0x0 0x1000>; - assigned-clocks = <&cru SCLK_I2C5>; - assigned-clock-rates = <200000000>; - clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>; - clock-names = "i2c", "pclk"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&i2c5_xfer>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c6: i2c@ff150000 { - compatible = "rockchip,rk3399-i2c"; - reg = <0x0 0xff150000 0x0 0x1000>; - assigned-clocks = <&cru SCLK_I2C6>; - assigned-clock-rates = <200000000>; - clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>; - clock-names = "i2c", "pclk"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&i2c6_xfer>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c7: i2c@ff160000 { - compatible = "rockchip,rk3399-i2c"; - reg = <0x0 0xff160000 0x0 0x1000>; - assigned-clocks = <&cru SCLK_I2C7>; - assigned-clock-rates = <200000000>; - clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>; - clock-names = "i2c", "pclk"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&i2c7_xfer>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - uart0: serial@ff180000 { - compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; - reg = <0x0 0xff180000 0x0 0x100>; - clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; - clock-names = "baudclk", "apb_pclk"; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer>; - status = "disabled"; - }; - - uart1: serial@ff190000 { - compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; - reg = <0x0 0xff190000 0x0 0x100>; - clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; - clock-names = "baudclk", "apb_pclk"; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&uart1_xfer>; - status = "disabled"; - }; - - uart2: serial@ff1a0000 { - compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; - reg = <0x0 0xff1a0000 0x0 0x100>; - clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; - clock-names = "baudclk", "apb_pclk"; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&uart2c_xfer>; - status = "disabled"; - }; - - uart3: serial@ff1b0000 { - compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; - reg = <0x0 0xff1b0000 0x0 0x100>; - clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; - clock-names = "baudclk", "apb_pclk"; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&uart3_xfer>; - status = "disabled"; - }; - - spi0: spi@ff1c0000 { - compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; - reg = <0x0 0xff1c0000 0x0 0x1000>; - clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; - clock-names = "spiclk", "apb_pclk"; - interrupts = ; - dmas = <&dmac_peri 10>, <&dmac_peri 11>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi1: spi@ff1d0000 { - compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; - reg = <0x0 0xff1d0000 0x0 0x1000>; - clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; - clock-names = "spiclk", "apb_pclk"; - interrupts = ; - dmas = <&dmac_peri 12>, <&dmac_peri 13>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi2: spi@ff1e0000 { - compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; - reg = <0x0 0xff1e0000 0x0 0x1000>; - clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; - clock-names = "spiclk", "apb_pclk"; - interrupts = ; - dmas = <&dmac_peri 14>, <&dmac_peri 15>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi4: spi@ff1f0000 { - compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; - reg = <0x0 0xff1f0000 0x0 0x1000>; - clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>; - clock-names = "spiclk", "apb_pclk"; - interrupts = ; - dmas = <&dmac_peri 18>, <&dmac_peri 19>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi5: spi@ff200000 { - compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; - reg = <0x0 0xff200000 0x0 0x1000>; - clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>; - clock-names = "spiclk", "apb_pclk"; - interrupts = ; - dmas = <&dmac_bus 8>, <&dmac_bus 9>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>; - power-domains = <&power RK3399_PD_SDIOAUDIO>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - thermal_zones: thermal-zones { - cpu_thermal: cpu { - polling-delay-passive = <100>; - polling-delay = <1000>; - - thermal-sensors = <&tsadc 0>; - - trips { - cpu_alert0: cpu_alert0 { - temperature = <70000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu_alert1: cpu_alert1 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu_crit: cpu_crit { - temperature = <95000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu_alert0>; - cooling-device = - <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu_alert1>; - cooling-device = - <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - gpu_thermal: gpu { - polling-delay-passive = <100>; - polling-delay = <1000>; - - thermal-sensors = <&tsadc 1>; - - trips { - gpu_alert0: gpu_alert0 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - gpu_crit: gpu_crit { - temperature = <95000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&gpu_alert0>; - cooling-device = - <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - }; - - tsadc: tsadc@ff260000 { - compatible = "rockchip,rk3399-tsadc"; - reg = <0x0 0xff260000 0x0 0x100>; - interrupts = ; - assigned-clocks = <&cru SCLK_TSADC>; - assigned-clock-rates = <750000>; - clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; - clock-names = "tsadc", "apb_pclk"; - resets = <&cru SRST_TSADC>; - reset-names = "tsadc-apb"; - rockchip,grf = <&grf>; - rockchip,hw-tshut-temp = <95000>; - pinctrl-names = "init", "default", "sleep"; - pinctrl-0 = <&otp_gpio>; - pinctrl-1 = <&otp_out>; - pinctrl-2 = <&otp_gpio>; - #thermal-sensor-cells = <1>; - status = "disabled"; - }; - - qos_emmc: qos@ffa58000 { - compatible = "syscon"; - reg = <0x0 0xffa58000 0x0 0x20>; - }; - - qos_gmac: qos@ffa5c000 { - compatible = "syscon"; - reg = <0x0 0xffa5c000 0x0 0x20>; - }; - - qos_pcie: qos@ffa60080 { - compatible = "syscon"; - reg = <0x0 0xffa60080 0x0 0x20>; - }; - - qos_usb_host0: qos@ffa60100 { - compatible = "syscon"; - reg = <0x0 0xffa60100 0x0 0x20>; - }; - - qos_usb_host1: qos@ffa60180 { - compatible = "syscon"; - reg = <0x0 0xffa60180 0x0 0x20>; - }; - - qos_usb_otg0: qos@ffa70000 { - compatible = "syscon"; - reg = <0x0 0xffa70000 0x0 0x20>; - }; - - qos_usb_otg1: qos@ffa70080 { - compatible = "syscon"; - reg = <0x0 0xffa70080 0x0 0x20>; - }; - - qos_sd: qos@ffa74000 { - compatible = "syscon"; - reg = <0x0 0xffa74000 0x0 0x20>; - }; - - qos_sdioaudio: qos@ffa76000 { - compatible = "syscon"; - reg = <0x0 0xffa76000 0x0 0x20>; - }; - - qos_hdcp: qos@ffa90000 { - compatible = "syscon"; - reg = <0x0 0xffa90000 0x0 0x20>; - }; - - qos_iep: qos@ffa98000 { - compatible = "syscon"; - reg = <0x0 0xffa98000 0x0 0x20>; - }; - - qos_isp0_m0: qos@ffaa0000 { - compatible = "syscon"; - reg = <0x0 0xffaa0000 0x0 0x20>; - }; - - qos_isp0_m1: qos@ffaa0080 { - compatible = "syscon"; - reg = <0x0 0xffaa0080 0x0 0x20>; - }; - - qos_isp1_m0: qos@ffaa8000 { - compatible = "syscon"; - reg = <0x0 0xffaa8000 0x0 0x20>; - }; - - qos_isp1_m1: qos@ffaa8080 { - compatible = "syscon"; - reg = <0x0 0xffaa8080 0x0 0x20>; - }; - - qos_rga_r: qos@ffab0000 { - compatible = "syscon"; - reg = <0x0 0xffab0000 0x0 0x20>; - }; - - qos_rga_w: qos@ffab0080 { - compatible = "syscon"; - reg = <0x0 0xffab0080 0x0 0x20>; - }; - - qos_video_m0: qos@ffab8000 { - compatible = "syscon"; - reg = <0x0 0xffab8000 0x0 0x20>; - }; - - qos_video_m1_r: qos@ffac0000 { - compatible = "syscon"; - reg = <0x0 0xffac0000 0x0 0x20>; - }; - - qos_video_m1_w: qos@ffac0080 { - compatible = "syscon"; - reg = <0x0 0xffac0080 0x0 0x20>; - }; - - qos_vop_big_r: qos@ffac8000 { - compatible = "syscon"; - reg = <0x0 0xffac8000 0x0 0x20>; - }; - - qos_vop_big_w: qos@ffac8080 { - compatible = "syscon"; - reg = <0x0 0xffac8080 0x0 0x20>; - }; - - qos_vop_little: qos@ffad0000 { - compatible = "syscon"; - reg = <0x0 0xffad0000 0x0 0x20>; - }; - - qos_perihp: qos@ffad8080 { - compatible = "syscon"; - reg = <0x0 0xffad8080 0x0 0x20>; - }; - - qos_gpu: qos@ffae0000 { - compatible = "syscon"; - reg = <0x0 0xffae0000 0x0 0x20>; - }; - - pmu: power-management@ff310000 { - compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd"; - reg = <0x0 0xff310000 0x0 0x1000>; - - /* - * Note: RK3399 supports 6 voltage domains including VD_CORE_L, - * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU. - * Some of the power domains are grouped together for every - * voltage domain. - * The detail contents as below. - */ - power: power-controller { - compatible = "rockchip,rk3399-power-controller"; - #power-domain-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - - /* These power domains are grouped by VD_CENTER */ - pd_iep@RK3399_PD_IEP { - reg = ; - clocks = <&cru ACLK_IEP>, - <&cru HCLK_IEP>; - pm_qos = <&qos_iep>; - }; - pd_rga@RK3399_PD_RGA { - reg = ; - clocks = <&cru ACLK_RGA>, - <&cru HCLK_RGA>; - pm_qos = <&qos_rga_r>, - <&qos_rga_w>; - }; - pd_vcodec@RK3399_PD_VCODEC { - reg = ; - clocks = <&cru ACLK_VCODEC>, - <&cru HCLK_VCODEC>; - pm_qos = <&qos_video_m0>; - }; - pd_vdu@RK3399_PD_VDU { - reg = ; - clocks = <&cru ACLK_VDU>, - <&cru HCLK_VDU>; - pm_qos = <&qos_video_m1_r>, - <&qos_video_m1_w>; - }; - - /* These power domains are grouped by VD_GPU */ - pd_gpu@RK3399_PD_GPU { - reg = ; - clocks = <&cru ACLK_GPU>; - pm_qos = <&qos_gpu>; - }; - - /* These power domains are grouped by VD_LOGIC */ - pd_edp@RK3399_PD_EDP { - reg = ; - clocks = <&cru PCLK_EDP_CTRL>; - }; - pd_emmc@RK3399_PD_EMMC { - reg = ; - clocks = <&cru ACLK_EMMC>; - pm_qos = <&qos_emmc>; - }; - pd_gmac@RK3399_PD_GMAC { - reg = ; - clocks = <&cru ACLK_GMAC>, - <&cru PCLK_GMAC>; - pm_qos = <&qos_gmac>; - }; - pd_sd@RK3399_PD_SD { - reg = ; - clocks = <&cru HCLK_SDMMC>, - <&cru SCLK_SDMMC>; - pm_qos = <&qos_sd>; - }; - pd_sdioaudio@RK3399_PD_SDIOAUDIO { - reg = ; - clocks = <&cru HCLK_SDIO>; - pm_qos = <&qos_sdioaudio>; - }; - pd_usb3@RK3399_PD_USB3 { - reg = ; - clocks = <&cru ACLK_USB3>; - pm_qos = <&qos_usb_otg0>, - <&qos_usb_otg1>; - }; - pd_vio@RK3399_PD_VIO { - reg = ; - #address-cells = <1>; - #size-cells = <0>; - - pd_hdcp@RK3399_PD_HDCP { - reg = ; - clocks = <&cru ACLK_HDCP>, - <&cru HCLK_HDCP>, - <&cru PCLK_HDCP>; - pm_qos = <&qos_hdcp>; - }; - pd_isp0@RK3399_PD_ISP0 { - reg = ; - clocks = <&cru ACLK_ISP0>, - <&cru HCLK_ISP0>; - pm_qos = <&qos_isp0_m0>, - <&qos_isp0_m1>; - }; - pd_isp1@RK3399_PD_ISP1 { - reg = ; - clocks = <&cru ACLK_ISP1>, - <&cru HCLK_ISP1>; - pm_qos = <&qos_isp1_m0>, - <&qos_isp1_m1>; - }; - pd_tcpc0@RK3399_PD_TCPC0 { - reg = ; - clocks = <&cru SCLK_UPHY0_TCPDCORE>, - <&cru SCLK_UPHY0_TCPDPHY_REF>; - }; - pd_tcpc1@RK3399_PD_TCPC1 { - reg = ; - clocks = <&cru SCLK_UPHY1_TCPDCORE>, - <&cru SCLK_UPHY1_TCPDPHY_REF>; - }; - pd_vo@RK3399_PD_VO { - reg = ; - #address-cells = <1>; - #size-cells = <0>; - - pd_vopb@RK3399_PD_VOPB { - reg = ; - clocks = <&cru ACLK_VOP0>, - <&cru HCLK_VOP0>; - pm_qos = <&qos_vop_big_r>, - <&qos_vop_big_w>; - }; - pd_vopl@RK3399_PD_VOPL { - reg = ; - clocks = <&cru ACLK_VOP1>, - <&cru HCLK_VOP1>; - pm_qos = <&qos_vop_little>; - }; - }; - }; - }; - }; - - pmugrf: syscon@ff320000 { - compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd"; - reg = <0x0 0xff320000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - - pmu_io_domains: io-domains { - compatible = "rockchip,rk3399-pmu-io-voltage-domain"; - status = "disabled"; - }; - }; - - spi3: spi@ff350000 { - compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; - reg = <0x0 0xff350000 0x0 0x1000>; - clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>; - clock-names = "spiclk", "apb_pclk"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - uart4: serial@ff370000 { - compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; - reg = <0x0 0xff370000 0x0 0x100>; - clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>; - clock-names = "baudclk", "apb_pclk"; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&uart4_xfer>; - status = "disabled"; - }; - - i2c0: i2c@ff3c0000 { - compatible = "rockchip,rk3399-i2c"; - reg = <0x0 0xff3c0000 0x0 0x1000>; - assigned-clocks = <&pmucru SCLK_I2C0_PMU>; - assigned-clock-rates = <200000000>; - clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>; - clock-names = "i2c", "pclk"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_xfer>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c4: i2c@ff3d0000 { - compatible = "rockchip,rk3399-i2c"; - reg = <0x0 0xff3d0000 0x0 0x1000>; - assigned-clocks = <&pmucru SCLK_I2C4_PMU>; - assigned-clock-rates = <200000000>; - clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>; - clock-names = "i2c", "pclk"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_xfer>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c8: i2c@ff3e0000 { - compatible = "rockchip,rk3399-i2c"; - reg = <0x0 0xff3e0000 0x0 0x1000>; - assigned-clocks = <&pmucru SCLK_I2C8_PMU>; - assigned-clock-rates = <200000000>; - clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>; - clock-names = "i2c", "pclk"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&i2c8_xfer>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - pwm0: pwm@ff420000 { - compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; - reg = <0x0 0xff420000 0x0 0x10>; - #pwm-cells = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pin>; - clocks = <&pmucru PCLK_RKPWM_PMU>; - clock-names = "pwm"; - status = "disabled"; - }; - - pwm1: pwm@ff420010 { - compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; - reg = <0x0 0xff420010 0x0 0x10>; - #pwm-cells = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm1_pin>; - clocks = <&pmucru PCLK_RKPWM_PMU>; - clock-names = "pwm"; - status = "disabled"; - }; - - pwm2: pwm@ff420020 { - compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; - reg = <0x0 0xff420020 0x0 0x10>; - #pwm-cells = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm2_pin>; - clocks = <&pmucru PCLK_RKPWM_PMU>; - clock-names = "pwm"; - status = "disabled"; - }; - - pwm3: pwm@ff420030 { - compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; - reg = <0x0 0xff420030 0x0 0x10>; - #pwm-cells = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm3a_pin>; - clocks = <&pmucru PCLK_RKPWM_PMU>; - clock-names = "pwm"; - status = "disabled"; - }; - - vpu: video-codec@ff650000 { - compatible = "rockchip,rk3399-vpu"; - reg = <0x0 0xff650000 0x0 0x800>; - interrupts = , - ; - interrupt-names = "vepu", "vdpu"; - clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; - clock-names = "aclk", "hclk"; - iommus = <&vpu_mmu>; - power-domains = <&power RK3399_PD_VCODEC>; - }; - - vpu_mmu: iommu@ff650800 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff650800 0x0 0x40>; - interrupts = ; - interrupt-names = "vpu_mmu"; - clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; - clock-names = "aclk", "iface"; - #iommu-cells = <0>; - power-domains = <&power RK3399_PD_VCODEC>; - }; - - vdec_mmu: iommu@ff660480 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>; - interrupts = ; - interrupt-names = "vdec_mmu"; - clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>; - clock-names = "aclk", "iface"; - #iommu-cells = <0>; - status = "disabled"; - }; - - iep_mmu: iommu@ff670800 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff670800 0x0 0x40>; - interrupts = ; - interrupt-names = "iep_mmu"; - clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; - clock-names = "aclk", "iface"; - #iommu-cells = <0>; - status = "disabled"; - }; - - rga: rga@ff680000 { - compatible = "rockchip,rk3399-rga"; - reg = <0x0 0xff680000 0x0 0x10000>; - interrupts = ; - clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>; - clock-names = "aclk", "hclk", "sclk"; - resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>; - reset-names = "core", "axi", "ahb"; - power-domains = <&power RK3399_PD_RGA>; - }; - - efuse0: efuse@ff690000 { - compatible = "rockchip,rk3399-efuse"; - reg = <0x0 0xff690000 0x0 0x80>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&cru PCLK_EFUSE1024NS>; - clock-names = "pclk_efuse"; - - /* Data cells */ - cpu_id: cpu-id@7 { - reg = <0x07 0x10>; - }; - cpub_leakage: cpu-leakage@17 { - reg = <0x17 0x1>; - }; - gpu_leakage: gpu-leakage@18 { - reg = <0x18 0x1>; - }; - center_leakage: center-leakage@19 { - reg = <0x19 0x1>; - }; - cpul_leakage: cpu-leakage@1a { - reg = <0x1a 0x1>; - }; - logic_leakage: logic-leakage@1b { - reg = <0x1b 0x1>; - }; - wafer_info: wafer-info@1c { - reg = <0x1c 0x1>; - }; - }; - - pmucru: pmu-clock-controller@ff750000 { - compatible = "rockchip,rk3399-pmucru"; - reg = <0x0 0xff750000 0x0 0x1000>; - rockchip,grf = <&pmugrf>; - #clock-cells = <1>; - #reset-cells = <1>; - assigned-clocks = <&pmucru PLL_PPLL>; - assigned-clock-rates = <676000000>; - }; - - cru: clock-controller@ff760000 { - compatible = "rockchip,rk3399-cru"; - reg = <0x0 0xff760000 0x0 0x1000>; - rockchip,grf = <&grf>; - #clock-cells = <1>; - #reset-cells = <1>; - assigned-clocks = - <&cru PLL_GPLL>, <&cru PLL_CPLL>, - <&cru PLL_NPLL>, - <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>, - <&cru PCLK_PERIHP>, - <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>, - <&cru PCLK_PERILP0>, <&cru ACLK_CCI>, - <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>, - <&cru ACLK_VIO>, <&cru ACLK_HDCP>, - <&cru ACLK_GIC_PRE>, - <&cru PCLK_DDR>; - assigned-clock-rates = - <594000000>, <800000000>, - <1000000000>, - <150000000>, <75000000>, - <37500000>, - <100000000>, <100000000>, - <50000000>, <600000000>, - <100000000>, <50000000>, - <400000000>, <400000000>, - <200000000>, - <200000000>; - }; - - grf: syscon@ff770000 { - compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd"; - reg = <0x0 0xff770000 0x0 0x10000>; - #address-cells = <1>; - #size-cells = <1>; - - io_domains: io-domains { - compatible = "rockchip,rk3399-io-voltage-domain"; - status = "disabled"; - }; - - u2phy0: usb2-phy@e450 { - compatible = "rockchip,rk3399-usb2phy"; - reg = <0xe450 0x10>; - clocks = <&cru SCLK_USB2PHY0_REF>; - clock-names = "phyclk"; - #clock-cells = <0>; - clock-output-names = "clk_usbphy0_480m"; - status = "disabled"; - - u2phy0_host: host-port { - #phy-cells = <0>; - interrupts = ; - interrupt-names = "linestate"; - status = "disabled"; - }; - - u2phy0_otg: otg-port { - #phy-cells = <0>; - interrupts = , - , - ; - interrupt-names = "otg-bvalid", "otg-id", - "linestate"; - status = "disabled"; - }; - }; - - u2phy1: usb2-phy@e460 { - compatible = "rockchip,rk3399-usb2phy"; - reg = <0xe460 0x10>; - clocks = <&cru SCLK_USB2PHY1_REF>; - clock-names = "phyclk"; - #clock-cells = <0>; - clock-output-names = "clk_usbphy1_480m"; - status = "disabled"; - - u2phy1_host: host-port { - #phy-cells = <0>; - interrupts = ; - interrupt-names = "linestate"; - status = "disabled"; - }; - - u2phy1_otg: otg-port { - #phy-cells = <0>; - interrupts = , - , - ; - interrupt-names = "otg-bvalid", "otg-id", - "linestate"; - status = "disabled"; - }; - }; - - emmc_phy: phy@f780 { - compatible = "rockchip,rk3399-emmc-phy"; - reg = <0xf780 0x24>; - clocks = <&sdhci>; - clock-names = "emmcclk"; - #phy-cells = <0>; - status = "disabled"; - }; - - pcie_phy: pcie-phy { - compatible = "rockchip,rk3399-pcie-phy"; - clocks = <&cru SCLK_PCIEPHY_REF>; - clock-names = "refclk"; - #phy-cells = <1>; - resets = <&cru SRST_PCIEPHY>; - drive-impedance-ohm = <50>; - reset-names = "phy"; - status = "disabled"; - }; - }; - - tcphy0: phy@ff7c0000 { - compatible = "rockchip,rk3399-typec-phy"; - reg = <0x0 0xff7c0000 0x0 0x40000>; - clocks = <&cru SCLK_UPHY0_TCPDCORE>, - <&cru SCLK_UPHY0_TCPDPHY_REF>; - clock-names = "tcpdcore", "tcpdphy-ref"; - assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>; - assigned-clock-rates = <50000000>; - power-domains = <&power RK3399_PD_TCPD0>; - resets = <&cru SRST_UPHY0>, - <&cru SRST_UPHY0_PIPE_L00>, - <&cru SRST_P_UPHY0_TCPHY>; - reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; - rockchip,grf = <&grf>; - status = "disabled"; - - tcphy0_dp: dp-port { - #phy-cells = <0>; - }; - - tcphy0_usb3: usb3-port { - #phy-cells = <0>; - }; - }; - - tcphy1: phy@ff800000 { - compatible = "rockchip,rk3399-typec-phy"; - reg = <0x0 0xff800000 0x0 0x40000>; - clocks = <&cru SCLK_UPHY1_TCPDCORE>, - <&cru SCLK_UPHY1_TCPDPHY_REF>; - clock-names = "tcpdcore", "tcpdphy-ref"; - assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>; - assigned-clock-rates = <50000000>; - power-domains = <&power RK3399_PD_TCPD1>; - resets = <&cru SRST_UPHY1>, - <&cru SRST_UPHY1_PIPE_L00>, - <&cru SRST_P_UPHY1_TCPHY>; - reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; - rockchip,grf = <&grf>; - status = "disabled"; - - tcphy1_dp: dp-port { - #phy-cells = <0>; - }; - - tcphy1_usb3: usb3-port { - #phy-cells = <0>; - }; - }; - - watchdog@ff848000 { - compatible = "snps,dw-wdt"; - reg = <0x0 0xff848000 0x0 0x100>; - clocks = <&cru PCLK_WDT>; - interrupts = ; - }; - - rktimer: rktimer@ff850000 { - compatible = "rockchip,rk3399-timer"; - reg = <0x0 0xff850000 0x0 0x1000>; - interrupts = ; - clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>; - clock-names = "pclk", "timer"; - }; - - spdif: spdif@ff870000 { - compatible = "rockchip,rk3399-spdif"; - reg = <0x0 0xff870000 0x0 0x1000>; - interrupts = ; - dmas = <&dmac_bus 7>; - dma-names = "tx"; - clock-names = "mclk", "hclk"; - clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>; - pinctrl-names = "default"; - pinctrl-0 = <&spdif_bus>; - power-domains = <&power RK3399_PD_SDIOAUDIO>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - i2s0: i2s@ff880000 { - compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; - reg = <0x0 0xff880000 0x0 0x1000>; - rockchip,grf = <&grf>; - interrupts = ; - dmas = <&dmac_bus 0>, <&dmac_bus 1>; - dma-names = "tx", "rx"; - clock-names = "i2s_clk", "i2s_hclk"; - clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_8ch_bus>; - power-domains = <&power RK3399_PD_SDIOAUDIO>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - i2s1: i2s@ff890000 { - compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; - reg = <0x0 0xff890000 0x0 0x1000>; - interrupts = ; - dmas = <&dmac_bus 2>, <&dmac_bus 3>; - dma-names = "tx", "rx"; - clock-names = "i2s_clk", "i2s_hclk"; - clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s1_2ch_bus>; - power-domains = <&power RK3399_PD_SDIOAUDIO>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - i2s2: i2s@ff8a0000 { - compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; - reg = <0x0 0xff8a0000 0x0 0x1000>; - interrupts = ; - dmas = <&dmac_bus 4>, <&dmac_bus 5>; - dma-names = "tx", "rx"; - clock-names = "i2s_clk", "i2s_hclk"; - clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>; - power-domains = <&power RK3399_PD_SDIOAUDIO>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - vopl: vop@ff8f0000 { - compatible = "rockchip,rk3399-vop-lit"; - reg = <0x0 0xff8f0000 0x0 0x3efc>; - interrupts = ; - assigned-clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; - assigned-clock-rates = <400000000>, <100000000>; - clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>; - clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; - iommus = <&vopl_mmu>; - power-domains = <&power RK3399_PD_VOPL>; - resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>; - reset-names = "axi", "ahb", "dclk"; - status = "disabled"; - - vopl_out: port { - #address-cells = <1>; - #size-cells = <0>; - - vopl_out_mipi: endpoint@0 { - reg = <0>; - remote-endpoint = <&mipi_in_vopl>; - }; - - vopl_out_edp: endpoint@1 { - reg = <1>; - remote-endpoint = <&edp_in_vopl>; - }; - - vopl_out_hdmi: endpoint@2 { - reg = <2>; - remote-endpoint = <&hdmi_in_vopl>; - }; - - vopl_out_mipi1: endpoint@3 { - reg = <3>; - remote-endpoint = <&mipi1_in_vopl>; - }; - - vopl_out_dp: endpoint@4 { - reg = <4>; - remote-endpoint = <&dp_in_vopl>; - }; - }; - }; - - vopl_mmu: iommu@ff8f3f00 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff8f3f00 0x0 0x100>; - interrupts = ; - interrupt-names = "vopl_mmu"; - clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; - clock-names = "aclk", "iface"; - power-domains = <&power RK3399_PD_VOPL>; - #iommu-cells = <0>; - status = "disabled"; - }; - - vopb: vop@ff900000 { - compatible = "rockchip,rk3399-vop-big"; - reg = <0x0 0xff900000 0x0 0x3efc>; - interrupts = ; - assigned-clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; - assigned-clock-rates = <400000000>, <100000000>; - clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>; - clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; - iommus = <&vopb_mmu>; - power-domains = <&power RK3399_PD_VOPB>; - resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>; - reset-names = "axi", "ahb", "dclk"; - status = "disabled"; - - vopb_out: port { - #address-cells = <1>; - #size-cells = <0>; - - vopb_out_edp: endpoint@0 { - reg = <0>; - remote-endpoint = <&edp_in_vopb>; - }; - - vopb_out_mipi: endpoint@1 { - reg = <1>; - remote-endpoint = <&mipi_in_vopb>; - }; - - vopb_out_hdmi: endpoint@2 { - reg = <2>; - remote-endpoint = <&hdmi_in_vopb>; - }; - - vopb_out_mipi1: endpoint@3 { - reg = <3>; - remote-endpoint = <&mipi1_in_vopb>; - }; - - vopb_out_dp: endpoint@4 { - reg = <4>; - remote-endpoint = <&dp_in_vopb>; - }; - }; - }; - - vopb_mmu: iommu@ff903f00 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff903f00 0x0 0x100>; - interrupts = ; - interrupt-names = "vopb_mmu"; - clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; - clock-names = "aclk", "iface"; - power-domains = <&power RK3399_PD_VOPB>; - #iommu-cells = <0>; - status = "disabled"; - }; - - isp0_mmu: iommu@ff914000 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>; - interrupts = ; - interrupt-names = "isp0_mmu"; - clocks = <&cru ACLK_ISP0_WRAPPER>, <&cru HCLK_ISP0_WRAPPER>; - clock-names = "aclk", "iface"; - #iommu-cells = <0>; - power-domains = <&power RK3399_PD_ISP0>; - rockchip,disable-mmu-reset; - }; - - isp1_mmu: iommu@ff924000 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>; - interrupts = ; - interrupt-names = "isp1_mmu"; - clocks = <&cru ACLK_ISP1_WRAPPER>, <&cru HCLK_ISP1_WRAPPER>; - clock-names = "aclk", "iface"; - #iommu-cells = <0>; - power-domains = <&power RK3399_PD_ISP1>; - rockchip,disable-mmu-reset; - }; - - hdmi_sound: hdmi-sound { - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,mclk-fs = <256>; - simple-audio-card,name = "hdmi-sound"; - status = "disabled"; - - simple-audio-card,cpu { - sound-dai = <&i2s2>; - }; - simple-audio-card,codec { - sound-dai = <&hdmi>; - }; - }; - - hdmi: hdmi@ff940000 { - compatible = "rockchip,rk3399-dw-hdmi"; - reg = <0x0 0xff940000 0x0 0x20000>; - interrupts = ; - clocks = <&cru PCLK_HDMI_CTRL>, - <&cru SCLK_HDMI_SFR>, - <&cru PLL_VPLL>, - <&cru PCLK_VIO_GRF>, - <&cru SCLK_HDMI_CEC>; - clock-names = "iahb", "isfr", "vpll", "grf", "cec"; - power-domains = <&power RK3399_PD_HDCP>; - reg-io-width = <4>; - rockchip,grf = <&grf>; - #sound-dai-cells = <0>; - status = "disabled"; - - ports { - hdmi_in: port { - #address-cells = <1>; - #size-cells = <0>; - - hdmi_in_vopb: endpoint@0 { - reg = <0>; - remote-endpoint = <&vopb_out_hdmi>; - }; - hdmi_in_vopl: endpoint@1 { - reg = <1>; - remote-endpoint = <&vopl_out_hdmi>; - }; - }; - }; - }; - - mipi_dsi: mipi@ff960000 { - compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"; - reg = <0x0 0xff960000 0x0 0x8000>; - interrupts = ; - clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI0>, - <&cru SCLK_DPHY_TX0_CFG>, <&cru PCLK_VIO_GRF>; - clock-names = "ref", "pclk", "phy_cfg", "grf"; - power-domains = <&power RK3399_PD_VIO>; - resets = <&cru SRST_P_MIPI_DSI0>; - reset-names = "apb"; - rockchip,grf = <&grf>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - mipi_in: port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - mipi_in_vopb: endpoint@0 { - reg = <0>; - remote-endpoint = <&vopb_out_mipi>; - }; - mipi_in_vopl: endpoint@1 { - reg = <1>; - remote-endpoint = <&vopl_out_mipi>; - }; - }; - }; - }; - - mipi_dsi1: mipi@ff968000 { - compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"; - reg = <0x0 0xff968000 0x0 0x8000>; - interrupts = ; - clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI1>, - <&cru SCLK_DPHY_TX1RX1_CFG>, <&cru PCLK_VIO_GRF>; - clock-names = "ref", "pclk", "phy_cfg", "grf"; - power-domains = <&power RK3399_PD_VIO>; - resets = <&cru SRST_P_MIPI_DSI1>; - reset-names = "apb"; - rockchip,grf = <&grf>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - mipi1_in: port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - mipi1_in_vopb: endpoint@0 { - reg = <0>; - remote-endpoint = <&vopb_out_mipi1>; - }; - - mipi1_in_vopl: endpoint@1 { - reg = <1>; - remote-endpoint = <&vopl_out_mipi1>; - }; - }; - }; - }; - - edp: edp@ff970000 { - compatible = "rockchip,rk3399-edp"; - reg = <0x0 0xff970000 0x0 0x8000>; - interrupts = ; - clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>, <&cru PCLK_VIO_GRF>; - clock-names = "dp", "pclk", "grf"; - pinctrl-names = "default"; - pinctrl-0 = <&edp_hpd>; - power-domains = <&power RK3399_PD_EDP>; - resets = <&cru SRST_P_EDP_CTRL>; - reset-names = "dp"; - rockchip,grf = <&grf>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - edp_in: port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - edp_in_vopb: endpoint@0 { - reg = <0>; - remote-endpoint = <&vopb_out_edp>; - }; - - edp_in_vopl: endpoint@1 { - reg = <1>; - remote-endpoint = <&vopl_out_edp>; - }; - }; - }; - }; - - gpu: gpu@ff9a0000 { - compatible = "rockchip,rk3399-mali", "arm,mali-t860"; - reg = <0x0 0xff9a0000 0x0 0x10000>; - interrupts = , - , - ; - interrupt-names = "gpu", "job", "mmu"; - clocks = <&cru ACLK_GPU>; - #cooling-cells = <2>; - power-domains = <&power RK3399_PD_GPU>; - status = "disabled"; - }; - - pinctrl: pinctrl { - compatible = "rockchip,rk3399-pinctrl"; - rockchip,grf = <&grf>; - rockchip,pmu = <&pmugrf>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - gpio0: gpio0@ff720000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff720000 0x0 0x100>; - clocks = <&pmucru PCLK_GPIO0_PMU>; - interrupts = ; - - gpio-controller; - #gpio-cells = <0x2>; - - interrupt-controller; - #interrupt-cells = <0x2>; - }; - - gpio1: gpio1@ff730000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff730000 0x0 0x100>; - clocks = <&pmucru PCLK_GPIO1_PMU>; - interrupts = ; - - gpio-controller; - #gpio-cells = <0x2>; - - interrupt-controller; - #interrupt-cells = <0x2>; - }; - - gpio2: gpio2@ff780000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff780000 0x0 0x100>; - clocks = <&cru PCLK_GPIO2>; - interrupts = ; - - gpio-controller; - #gpio-cells = <0x2>; - - interrupt-controller; - #interrupt-cells = <0x2>; - }; - - gpio3: gpio3@ff788000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff788000 0x0 0x100>; - clocks = <&cru PCLK_GPIO3>; - interrupts = ; - - gpio-controller; - #gpio-cells = <0x2>; - - interrupt-controller; - #interrupt-cells = <0x2>; - }; - - gpio4: gpio4@ff790000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff790000 0x0 0x100>; - clocks = <&cru PCLK_GPIO4>; - interrupts = ; - - gpio-controller; - #gpio-cells = <0x2>; - - interrupt-controller; - #interrupt-cells = <0x2>; - }; - - pcfg_pull_up: pcfg-pull-up { - bias-pull-up; - }; - - pcfg_pull_down: pcfg-pull-down { - bias-pull-down; - }; - - pcfg_pull_none: pcfg-pull-none { - bias-disable; - }; - - pcfg_pull_none_12ma: pcfg-pull-none-12ma { - bias-disable; - drive-strength = <12>; - }; - - pcfg_pull_none_13ma: pcfg-pull-none-13ma { - bias-disable; - drive-strength = <13>; - }; - - pcfg_pull_none_18ma: pcfg-pull-none-18ma { - bias-disable; - drive-strength = <18>; - }; - - pcfg_pull_none_20ma: pcfg-pull-none-20ma { - bias-disable; - drive-strength = <20>; - }; - - pcfg_pull_up_2ma: pcfg-pull-up-2ma { - bias-pull-up; - drive-strength = <2>; - }; - - pcfg_pull_up_8ma: pcfg-pull-up-8ma { - bias-pull-up; - drive-strength = <8>; - }; - - pcfg_pull_up_18ma: pcfg-pull-up-18ma { - bias-pull-up; - drive-strength = <18>; - }; - - pcfg_pull_up_20ma: pcfg-pull-up-20ma { - bias-pull-up; - drive-strength = <20>; - }; - - pcfg_pull_down_4ma: pcfg-pull-down-4ma { - bias-pull-down; - drive-strength = <4>; - }; - - pcfg_pull_down_8ma: pcfg-pull-down-8ma { - bias-pull-down; - drive-strength = <8>; - }; - - pcfg_pull_down_12ma: pcfg-pull-down-12ma { - bias-pull-down; - drive-strength = <12>; - }; - - pcfg_pull_down_18ma: pcfg-pull-down-18ma { - bias-pull-down; - drive-strength = <18>; - }; - - pcfg_pull_down_20ma: pcfg-pull-down-20ma { - bias-pull-down; - drive-strength = <20>; - }; - - pcfg_output_high: pcfg-output-high { - output-high; - }; - - pcfg_output_low: pcfg-output-low { - output-low; - }; - - clock { - clk_32k: clk-32k { - rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>; - }; - }; - - edp { - edp_hpd: edp-hpd { - rockchip,pins = - <4 RK_PC7 2 &pcfg_pull_none>; - }; - }; - - gmac { - rgmii_pins: rgmii-pins { - rockchip,pins = - /* mac_txclk */ - <3 RK_PC1 1 &pcfg_pull_none_13ma>, - /* mac_rxclk */ - <3 RK_PB6 1 &pcfg_pull_none>, - /* mac_mdio */ - <3 RK_PB5 1 &pcfg_pull_none>, - /* mac_txen */ - <3 RK_PB4 1 &pcfg_pull_none_13ma>, - /* mac_clk */ - <3 RK_PB3 1 &pcfg_pull_none>, - /* mac_rxdv */ - <3 RK_PB1 1 &pcfg_pull_none>, - /* mac_mdc */ - <3 RK_PB0 1 &pcfg_pull_none>, - /* mac_rxd1 */ - <3 RK_PA7 1 &pcfg_pull_none>, - /* mac_rxd0 */ - <3 RK_PA6 1 &pcfg_pull_none>, - /* mac_txd1 */ - <3 RK_PA5 1 &pcfg_pull_none_13ma>, - /* mac_txd0 */ - <3 RK_PA4 1 &pcfg_pull_none_13ma>, - /* mac_rxd3 */ - <3 RK_PA3 1 &pcfg_pull_none>, - /* mac_rxd2 */ - <3 RK_PA2 1 &pcfg_pull_none>, - /* mac_txd3 */ - <3 RK_PA1 1 &pcfg_pull_none_13ma>, - /* mac_txd2 */ - <3 RK_PA0 1 &pcfg_pull_none_13ma>; - }; - - rmii_pins: rmii-pins { - rockchip,pins = - /* mac_mdio */ - <3 RK_PB5 1 &pcfg_pull_none>, - /* mac_txen */ - <3 RK_PB4 1 &pcfg_pull_none_13ma>, - /* mac_clk */ - <3 RK_PB3 1 &pcfg_pull_none>, - /* mac_rxer */ - <3 RK_PB2 1 &pcfg_pull_none>, - /* mac_rxdv */ - <3 RK_PB1 1 &pcfg_pull_none>, - /* mac_mdc */ - <3 RK_PB0 1 &pcfg_pull_none>, - /* mac_rxd1 */ - <3 RK_PA7 1 &pcfg_pull_none>, - /* mac_rxd0 */ - <3 RK_PA6 1 &pcfg_pull_none>, - /* mac_txd1 */ - <3 RK_PA5 1 &pcfg_pull_none_13ma>, - /* mac_txd0 */ - <3 RK_PA4 1 &pcfg_pull_none_13ma>; - }; - }; - - i2c0 { - i2c0_xfer: i2c0-xfer { - rockchip,pins = - <1 RK_PB7 2 &pcfg_pull_none>, - <1 RK_PC0 2 &pcfg_pull_none>; - }; - }; - - i2c1 { - i2c1_xfer: i2c1-xfer { - rockchip,pins = - <4 RK_PA2 1 &pcfg_pull_none>, - <4 RK_PA1 1 &pcfg_pull_none>; - }; - }; - - i2c2 { - i2c2_xfer: i2c2-xfer { - rockchip,pins = - <2 RK_PA1 2 &pcfg_pull_none_12ma>, - <2 RK_PA0 2 &pcfg_pull_none_12ma>; - }; - }; - - i2c3 { - i2c3_xfer: i2c3-xfer { - rockchip,pins = - <4 RK_PC1 1 &pcfg_pull_none>, - <4 RK_PC0 1 &pcfg_pull_none>; - }; - }; - - i2c4 { - i2c4_xfer: i2c4-xfer { - rockchip,pins = - <1 RK_PB4 1 &pcfg_pull_none>, - <1 RK_PB3 1 &pcfg_pull_none>; - }; - }; - - i2c5 { - i2c5_xfer: i2c5-xfer { - rockchip,pins = - <3 RK_PB3 2 &pcfg_pull_none>, - <3 RK_PB2 2 &pcfg_pull_none>; - }; - }; - - i2c6 { - i2c6_xfer: i2c6-xfer { - rockchip,pins = - <2 RK_PB2 2 &pcfg_pull_none>, - <2 RK_PB1 2 &pcfg_pull_none>; - }; - }; - - i2c7 { - i2c7_xfer: i2c7-xfer { - rockchip,pins = - <2 RK_PB0 2 &pcfg_pull_none>, - <2 RK_PA7 2 &pcfg_pull_none>; - }; - }; - - i2c8 { - i2c8_xfer: i2c8-xfer { - rockchip,pins = - <1 RK_PC5 1 &pcfg_pull_none>, - <1 RK_PC4 1 &pcfg_pull_none>; - }; - }; - - i2s0 { - i2s0_2ch_bus: i2s0-2ch-bus { - rockchip,pins = - <3 RK_PD0 1 &pcfg_pull_none>, - <3 RK_PD1 1 &pcfg_pull_none>, - <3 RK_PD2 1 &pcfg_pull_none>, - <3 RK_PD3 1 &pcfg_pull_none>, - <3 RK_PD7 1 &pcfg_pull_none>, - <4 RK_PA0 1 &pcfg_pull_none>; - }; - - i2s0_8ch_bus: i2s0-8ch-bus { - rockchip,pins = - <3 RK_PD0 1 &pcfg_pull_none>, - <3 RK_PD1 1 &pcfg_pull_none>, - <3 RK_PD2 1 &pcfg_pull_none>, - <3 RK_PD3 1 &pcfg_pull_none>, - <3 RK_PD4 1 &pcfg_pull_none>, - <3 RK_PD5 1 &pcfg_pull_none>, - <3 RK_PD6 1 &pcfg_pull_none>, - <3 RK_PD7 1 &pcfg_pull_none>, - <4 RK_PA0 1 &pcfg_pull_none>; - }; - }; - - i2s1 { - i2s1_2ch_bus: i2s1-2ch-bus { - rockchip,pins = - <4 RK_PA3 1 &pcfg_pull_none>, - <4 RK_PA4 1 &pcfg_pull_none>, - <4 RK_PA5 1 &pcfg_pull_none>, - <4 RK_PA6 1 &pcfg_pull_none>, - <4 RK_PA7 1 &pcfg_pull_none>; - }; - }; - - sdio0 { - sdio0_bus1: sdio0-bus1 { - rockchip,pins = - <2 RK_PC4 1 &pcfg_pull_up>; - }; - - sdio0_bus4: sdio0-bus4 { - rockchip,pins = - <2 RK_PC4 1 &pcfg_pull_up>, - <2 RK_PC5 1 &pcfg_pull_up>, - <2 RK_PC6 1 &pcfg_pull_up>, - <2 RK_PC7 1 &pcfg_pull_up>; - }; - - sdio0_cmd: sdio0-cmd { - rockchip,pins = - <2 RK_PD0 1 &pcfg_pull_up>; - }; - - sdio0_clk: sdio0-clk { - rockchip,pins = - <2 RK_PD1 1 &pcfg_pull_none>; - }; - - sdio0_cd: sdio0-cd { - rockchip,pins = - <2 RK_PD2 1 &pcfg_pull_up>; - }; - - sdio0_pwr: sdio0-pwr { - rockchip,pins = - <2 RK_PD3 1 &pcfg_pull_up>; - }; - - sdio0_bkpwr: sdio0-bkpwr { - rockchip,pins = - <2 RK_PD4 1 &pcfg_pull_up>; - }; - - sdio0_wp: sdio0-wp { - rockchip,pins = - <0 RK_PA3 1 &pcfg_pull_up>; - }; - - sdio0_int: sdio0-int { - rockchip,pins = - <0 RK_PA4 1 &pcfg_pull_up>; - }; - }; - - sdmmc { - sdmmc_bus1: sdmmc-bus1 { - rockchip,pins = - <4 RK_PB0 1 &pcfg_pull_up>; - }; - - sdmmc_bus4: sdmmc-bus4 { - rockchip,pins = - <4 RK_PB0 1 &pcfg_pull_up>, - <4 RK_PB1 1 &pcfg_pull_up>, - <4 RK_PB2 1 &pcfg_pull_up>, - <4 RK_PB3 1 &pcfg_pull_up>; - }; - - sdmmc_clk: sdmmc-clk { - rockchip,pins = - <4 RK_PB4 1 &pcfg_pull_none>; - }; - - sdmmc_cmd: sdmmc-cmd { - rockchip,pins = - <4 RK_PB5 1 &pcfg_pull_up>; - }; - - sdmmc_cd: sdmmc-cd { - rockchip,pins = - <0 RK_PA7 1 &pcfg_pull_up>; - }; - - sdmmc_wp: sdmmc-wp { - rockchip,pins = - <0 RK_PB0 1 &pcfg_pull_up>; - }; - }; - - sleep { - ap_pwroff: ap-pwroff { - rockchip,pins = <1 RK_PA5 1 &pcfg_pull_none>; - }; - - ddrio_pwroff: ddrio-pwroff { - rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>; - }; - }; - - spdif { - spdif_bus: spdif-bus { - rockchip,pins = - <4 RK_PC5 1 &pcfg_pull_none>; - }; - - spdif_bus_1: spdif-bus-1 { - rockchip,pins = - <3 RK_PC0 3 &pcfg_pull_none>; - }; - }; - - spi0 { - spi0_clk: spi0-clk { - rockchip,pins = - <3 RK_PA6 2 &pcfg_pull_up>; - }; - spi0_cs0: spi0-cs0 { - rockchip,pins = - <3 RK_PA7 2 &pcfg_pull_up>; - }; - spi0_cs1: spi0-cs1 { - rockchip,pins = - <3 RK_PB0 2 &pcfg_pull_up>; - }; - spi0_tx: spi0-tx { - rockchip,pins = - <3 RK_PA5 2 &pcfg_pull_up>; - }; - spi0_rx: spi0-rx { - rockchip,pins = - <3 RK_PA4 2 &pcfg_pull_up>; - }; - }; - - spi1 { - spi1_clk: spi1-clk { - rockchip,pins = - <1 RK_PB1 2 &pcfg_pull_up>; - }; - spi1_cs0: spi1-cs0 { - rockchip,pins = - <1 RK_PB2 2 &pcfg_pull_up>; - }; - spi1_rx: spi1-rx { - rockchip,pins = - <1 RK_PA7 2 &pcfg_pull_up>; - }; - spi1_tx: spi1-tx { - rockchip,pins = - <1 RK_PB0 2 &pcfg_pull_up>; - }; - }; - - spi2 { - spi2_clk: spi2-clk { - rockchip,pins = - <2 RK_PB3 1 &pcfg_pull_up>; - }; - spi2_cs0: spi2-cs0 { - rockchip,pins = - <2 RK_PB4 1 &pcfg_pull_up>; - }; - spi2_rx: spi2-rx { - rockchip,pins = - <2 RK_PB1 1 &pcfg_pull_up>; - }; - spi2_tx: spi2-tx { - rockchip,pins = - <2 RK_PB2 1 &pcfg_pull_up>; - }; - }; - - spi3 { - spi3_clk: spi3-clk { - rockchip,pins = - <1 RK_PC1 1 &pcfg_pull_up>; - }; - spi3_cs0: spi3-cs0 { - rockchip,pins = - <1 RK_PC2 1 &pcfg_pull_up>; - }; - spi3_rx: spi3-rx { - rockchip,pins = - <1 RK_PB7 1 &pcfg_pull_up>; - }; - spi3_tx: spi3-tx { - rockchip,pins = - <1 RK_PC0 1 &pcfg_pull_up>; - }; - }; - - spi4 { - spi4_clk: spi4-clk { - rockchip,pins = - <3 RK_PA2 2 &pcfg_pull_up>; - }; - spi4_cs0: spi4-cs0 { - rockchip,pins = - <3 RK_PA3 2 &pcfg_pull_up>; - }; - spi4_rx: spi4-rx { - rockchip,pins = - <3 RK_PA0 2 &pcfg_pull_up>; - }; - spi4_tx: spi4-tx { - rockchip,pins = - <3 RK_PA1 2 &pcfg_pull_up>; - }; - }; - - spi5 { - spi5_clk: spi5-clk { - rockchip,pins = - <2 RK_PC6 2 &pcfg_pull_up>; - }; - spi5_cs0: spi5-cs0 { - rockchip,pins = - <2 RK_PC7 2 &pcfg_pull_up>; - }; - spi5_rx: spi5-rx { - rockchip,pins = - <2 RK_PC4 2 &pcfg_pull_up>; - }; - spi5_tx: spi5-tx { - rockchip,pins = - <2 RK_PC5 2 &pcfg_pull_up>; - }; - }; - - testclk { - test_clkout0: test-clkout0 { - rockchip,pins = - <0 RK_PA0 1 &pcfg_pull_none>; - }; - - test_clkout1: test-clkout1 { - rockchip,pins = - <2 RK_PD1 2 &pcfg_pull_none>; - }; - - test_clkout2: test-clkout2 { - rockchip,pins = - <0 RK_PB0 3 &pcfg_pull_none>; - }; - }; - - tsadc { - otp_gpio: otp-gpio { - rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - otp_out: otp-out { - rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none>; - }; - }; - - uart0 { - uart0_xfer: uart0-xfer { - rockchip,pins = - <2 RK_PC0 1 &pcfg_pull_up>, - <2 RK_PC1 1 &pcfg_pull_none>; - }; - - uart0_cts: uart0-cts { - rockchip,pins = - <2 RK_PC2 1 &pcfg_pull_none>; - }; - - uart0_rts: uart0-rts { - rockchip,pins = - <2 RK_PC3 1 &pcfg_pull_none>; - }; - }; - - uart1 { - uart1_xfer: uart1-xfer { - rockchip,pins = - <3 RK_PB4 2 &pcfg_pull_up>, - <3 RK_PB5 2 &pcfg_pull_none>; - }; - }; - - uart2a { - uart2a_xfer: uart2a-xfer { - rockchip,pins = - <4 RK_PB0 2 &pcfg_pull_up>, - <4 RK_PB1 2 &pcfg_pull_none>; - }; - }; - - uart2b { - uart2b_xfer: uart2b-xfer { - rockchip,pins = - <4 RK_PC0 2 &pcfg_pull_up>, - <4 RK_PC1 2 &pcfg_pull_none>; - }; - }; - - uart2c { - uart2c_xfer: uart2c-xfer { - rockchip,pins = - <4 RK_PC3 1 &pcfg_pull_up>, - <4 RK_PC4 1 &pcfg_pull_none>; - }; - }; - - uart3 { - uart3_xfer: uart3-xfer { - rockchip,pins = - <3 RK_PB6 2 &pcfg_pull_up>, - <3 RK_PB7 2 &pcfg_pull_none>; - }; - - uart3_cts: uart3-cts { - rockchip,pins = - <3 RK_PC0 2 &pcfg_pull_none>; - }; - - uart3_rts: uart3-rts { - rockchip,pins = - <3 RK_PC1 2 &pcfg_pull_none>; - }; - }; - - uart4 { - uart4_xfer: uart4-xfer { - rockchip,pins = - <1 RK_PA7 1 &pcfg_pull_up>, - <1 RK_PB0 1 &pcfg_pull_none>; - }; - }; - - uarthdcp { - uarthdcp_xfer: uarthdcp-xfer { - rockchip,pins = - <4 RK_PC5 2 &pcfg_pull_up>, - <4 RK_PC6 2 &pcfg_pull_none>; - }; - }; - - pwm0 { - pwm0_pin: pwm0-pin { - rockchip,pins = - <4 RK_PC2 1 &pcfg_pull_none>; - }; - - pwm0_pin_pull_down: pwm0-pin-pull-down { - rockchip,pins = - <4 RK_PC2 1 &pcfg_pull_down>; - }; - - vop0_pwm_pin: vop0-pwm-pin { - rockchip,pins = - <4 RK_PC2 2 &pcfg_pull_none>; - }; - - vop1_pwm_pin: vop1-pwm-pin { - rockchip,pins = - <4 RK_PC2 3 &pcfg_pull_none>; - }; - }; - - pwm1 { - pwm1_pin: pwm1-pin { - rockchip,pins = - <4 RK_PC6 1 &pcfg_pull_none>; - }; - - pwm1_pin_pull_down: pwm1-pin-pull-down { - rockchip,pins = - <4 RK_PC6 1 &pcfg_pull_down>; - }; - }; - - pwm2 { - pwm2_pin: pwm2-pin { - rockchip,pins = - <1 RK_PC3 1 &pcfg_pull_none>; - }; - - pwm2_pin_pull_down: pwm2-pin-pull-down { - rockchip,pins = - <1 RK_PC3 1 &pcfg_pull_down>; - }; - }; - - pwm3a { - pwm3a_pin: pwm3a-pin { - rockchip,pins = - <0 RK_PA6 1 &pcfg_pull_none>; - }; - }; - - pwm3b { - pwm3b_pin: pwm3b-pin { - rockchip,pins = - <1 RK_PB6 1 &pcfg_pull_none>; - }; - }; - - hdmi { - hdmi_i2c_xfer: hdmi-i2c-xfer { - rockchip,pins = - <4 RK_PC1 3 &pcfg_pull_none>, - <4 RK_PC0 3 &pcfg_pull_none>; - }; - - hdmi_cec: hdmi-cec { - rockchip,pins = - <4 RK_PC7 1 &pcfg_pull_none>; - }; - }; - - pcie { - pcie_clkreqn_cpm: pci-clkreqn-cpm { - rockchip,pins = - <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - pcie_clkreqnb_cpm: pci-clkreqnb-cpm { - rockchip,pins = - <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - }; -}; diff --git a/sys/gnu/dts/arm64/rockchip/rk3399pro-rock-pi-n10.dts b/sys/gnu/dts/arm64/rockchip/rk3399pro-rock-pi-n10.dts deleted file mode 100644 index b42f9417953..00000000000 --- a/sys/gnu/dts/arm64/rockchip/rk3399pro-rock-pi-n10.dts +++ /dev/null @@ -1,17 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd - * Copyright (c) 2019 Radxa Limited - * Copyright (c) 2019 Amarula Solutions(India) - */ - -/dts-v1/; -#include "rk3399.dtsi" -#include "rk3399-opp.dtsi" -#include "rk3399pro-vmarc-som.dtsi" -#include - -/ { - model = "Radxa ROCK Pi N10"; - compatible = "radxa,rockpi-n10", "rockchip,rk3399pro"; -}; diff --git a/sys/gnu/dts/arm64/rockchip/rk3399pro-vmarc-som.dtsi b/sys/gnu/dts/arm64/rockchip/rk3399pro-vmarc-som.dtsi deleted file mode 100644 index 0a516334f15..00000000000 --- a/sys/gnu/dts/arm64/rockchip/rk3399pro-vmarc-som.dtsi +++ /dev/null @@ -1,333 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd - * Copyright (c) 2019 Vamrs Limited - * Copyright (c) 2019 Amarula Solutions(India) - */ - -#include -#include -#include - -/ { - compatible = "vamrs,rk3399pro-vmarc-som", "rockchip,rk3399pro"; - - clkin_gmac: external-gmac-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "clkin_gmac"; - #clock-cells = <0>; - }; - - vcc12v_dcin: vcc12v-dcin-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc12v_dcin"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - vcc5v0_sys: vcc5v0-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc12v_dcin>; - }; -}; - -&cpu_l0 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l1 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l2 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l3 { - cpu-supply = <&vdd_cpu_l>; -}; - -&emmc_phy { - status = "okay"; -}; - -&gmac { - assigned-clocks = <&cru SCLK_RMII_SRC>; - assigned-clock-parents = <&clkin_gmac>; - clock_in_out = "input"; - phy-supply = <&vcc_lan>; - phy-mode = "rgmii"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 50000>; - tx_delay = <0x28>; - rx_delay = <0x11>; -}; - -&i2c0 { - clock-frequency = <400000>; - i2c-scl-rising-time-ns = <180>; - i2c-scl-falling-time-ns = <30>; - status = "okay"; - - rk809: pmic@20 { - compatible = "rockchip,rk809"; - reg = <0x20>; - interrupt-parent = <&gpio1>; - interrupts = ; - #clock-cells = <1>; - clock-output-names = "rk808-clkout1", "rk808-clkout2"; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l>; - rockchip,system-power-controller; - wakeup-source; - - vcc1-supply = <&vcc5v0_sys>; - vcc2-supply = <&vcc5v0_sys>; - vcc3-supply = <&vcc5v0_sys>; - vcc4-supply = <&vcc5v0_sys>; - vcc5-supply = <&vcc_buck5>; - vcc6-supply = <&vcc_buck5>; - vcc7-supply = <&vcc5v0_sys>; - vcc8-supply = <&vcc3v3_sys>; - vcc9-supply = <&vcc5v0_sys>; - - regulators { - vdd_log: DCDC_REG1 { - regulator-name = "vdd_log"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-initial-mode = <0x2>; - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <900000>; - }; - }; - - vdd_cpu_l: DCDC_REG2 { - regulator-name = "vdd_cpu_l"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - regulator-initial-mode = <0x2>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - regulator-initial-mode = <0x2>; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc3v3_sys: DCDC_REG4 { - regulator-name = "vcc3v3_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-initial-mode = <0x2>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc_buck5: DCDC_REG5 { - regulator-name = "vcc_buck5"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <2200000>; - regulator-max-microvolt = <2200000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <2200000>; - }; - }; - - vcca_0v9: LDO_REG1 { - regulator-name = "vcca_0v9"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v8: LDO_REG2 { - regulator-name = "vcc_1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc_0v9: LDO_REG3 { - regulator-name = "vcc_0v9"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <900000>; - }; - }; - - vcca_1v8: LDO_REG4 { - regulator-name = "vcca_1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1850000>; - regulator-max-microvolt = <1850000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - /* - * As per BSP, but schematic not showing any regulator - * pin for LD05. - */ - vdd1v5_dvp: LDO_REG5 { - regulator-name = "vdd1v5_dvp"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v5: LDO_REG6 { - regulator-name = "vcc_1v5"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vccio_3v0: LDO_REG7 { - regulator-name = "vccio_3v0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vccio_sd: LDO_REG8 { - regulator-name = "vccio_sd"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - /* - * As per BSP, but schematic not showing any regulator - * pin for LD09. - */ - vcc_sd: LDO_REG9 { - regulator-name = "vcc_sd"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc5v0_usb2: SWITCH_REG1 { - regulator-name = "vcc5v0_usb2"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <5000000>; - }; - }; - - vccio_3v3: vcc_lan: SWITCH_REG2 { - regulator-name = "vccio_3v3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; -}; - -&io_domains { - status = "okay"; - bt656-supply = <&vcca_1v8>; - sdmmc-supply = <&vccio_sd>; - gpio1830-supply = <&vccio_3v0>; -}; - -&pmu_io_domains { - status = "okay"; - pmu1830-supply = <&vcc_1v8>; -}; - -&sdhci { - bus-width = <8>; - mmc-hs400-1_8v; - mmc-hs400-enhanced-strobe; - non-removable; - status = "okay"; -}; - -&tsadc { - status = "okay"; - rockchip,hw-tshut-mode = <1>; - rockchip,hw-tshut-polarity = <1>; -}; - -&pinctrl { - pmic { - pmic_int_l: pmic-int-l { - rockchip,pins = - <1 RK_PC2 0 &pcfg_pull_up>; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/rockchip/rk3399pro.dtsi b/sys/gnu/dts/arm64/rockchip/rk3399pro.dtsi deleted file mode 100644 index bb5ebf6608b..00000000000 --- a/sys/gnu/dts/arm64/rockchip/rk3399pro.dtsi +++ /dev/null @@ -1,22 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd. - -#include "rk3399.dtsi" - -/ { - compatible = "rockchip,rk3399pro"; -}; - -/* Default to enabled since AP talk to NPU part over pcie */ -&pcie_phy { - status = "okay"; -}; - -/* Default to enabled since AP talk to NPU part over pcie */ -&pcie0 { - ep-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; - num-lanes = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie_clkreqn_cpm>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/socionext/uniphier-ld11-global.dts b/sys/gnu/dts/arm64/socionext/uniphier-ld11-global.dts deleted file mode 100644 index f72f048a0c9..00000000000 --- a/sys/gnu/dts/arm64/socionext/uniphier-ld11-global.dts +++ /dev/null @@ -1,170 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -// -// Device Tree Source for UniPhier LD11 Global Board -// -// Copyright (C) 2016-2017 Socionext Inc. -// Author: Masahiro Yamada -// Kunihiko Hayashi - -/dts-v1/; -#include -#include "uniphier-ld11.dtsi" - -/ { - model = "UniPhier LD11 Global Board (REF_LD11_GP)"; - compatible = "socionext,uniphier-ld11-global", - "socionext,uniphier-ld11"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - aliases { - serial0 = &serial0; - serial1 = &serial1; - serial2 = &serial2; - serial3 = &serial3; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0 0x80000000 0 0x40000000>; - }; - - dvdd_reg: reg-fixed { - compatible = "regulator-fixed"; - regulator-name = "DVDD"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - amp_vcc_reg: reg-fixed { - compatible = "regulator-fixed"; - regulator-name = "AMP_VCC"; - regulator-min-microvolt = <24000000>; - regulator-max-microvolt = <24000000>; - }; - - sound { - compatible = "audio-graph-card"; - label = "UniPhier LD11"; - widgets = "Headphone", "Headphones"; - dais = <&i2s_port2 - &i2s_port3 - &i2s_port4 - &spdif_port0 - &comp_spdif_port0>; - hp-det-gpio = <&gpio UNIPHIER_GPIO_IRQ(0) GPIO_ACTIVE_LOW>; - }; - - spdif-out { - compatible = "linux,spdif-dit"; - #sound-dai-cells = <0>; - - port@0 { - spdif_tx: endpoint { - remote-endpoint = <&spdif_hiecout1>; - }; - }; - }; - - comp-spdif-out { - compatible = "linux,spdif-dit"; - #sound-dai-cells = <0>; - - port@0 { - comp_spdif_tx: endpoint { - remote-endpoint = <&comp_spdif_hiecout1>; - }; - }; - }; -}; - -&serial0 { - status = "okay"; -}; - -&serial1 { - status = "okay"; -}; - -&i2s_hpcmout1 { - dai-format = "i2s"; - remote-endpoint = <&tas_speaker>; -}; - -&spdif_hiecout1 { - remote-endpoint = <&spdif_tx>; -}; - -&comp_spdif_hiecout1 { - remote-endpoint = <&comp_spdif_tx>; -}; - -&i2c0 { - status = "okay"; - - tas5707a@1d { - compatible = "ti,tas5711"; - reg = <0x1d>; - reset-gpios = <&gpio UNIPHIER_GPIO_PORT(23, 4) GPIO_ACTIVE_LOW>; - pdn-gpios = <&gpio UNIPHIER_GPIO_PORT(23, 5) GPIO_ACTIVE_LOW>; - #sound-dai-cells = <0>; - AVDD-supply = <&dvdd_reg>; - DVDD-supply = <&dvdd_reg>; - PVDD_A-supply = <&_vcc_reg>; - PVDD_B-supply = <&_vcc_reg>; - PVDD_C-supply = <&_vcc_reg>; - PVDD_D-supply = <&_vcc_reg>; - - port@0 { - tas_speaker: endpoint { - dai-format = "i2s"; - remote-endpoint = <&i2s_hpcmout1>; - }; - }; - }; - - eeprom@50 { - compatible = "st,24c64", "atmel,24c64"; - reg = <0x50>; - pagesize = <32>; - }; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; - -&usb2 { - status = "okay"; -}; - -ð { - status = "okay"; - phy-handle = <ðphy>; -}; - -&mdio { - ethphy: ethphy@1 { - reg = <1>; - }; -}; - -&nand { - status = "okay"; - - nand@0 { - reg = <0>; - }; -}; diff --git a/sys/gnu/dts/arm64/socionext/uniphier-ld11-ref.dts b/sys/gnu/dts/arm64/socionext/uniphier-ld11-ref.dts deleted file mode 100644 index b8f62734844..00000000000 --- a/sys/gnu/dts/arm64/socionext/uniphier-ld11-ref.dts +++ /dev/null @@ -1,81 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -// -// Device Tree Source for UniPhier LD11 Reference Board -// -// Copyright (C) 2016 Socionext Inc. -// Author: Masahiro Yamada - -/dts-v1/; -#include "uniphier-ld11.dtsi" -#include "uniphier-ref-daughter.dtsi" -#include "uniphier-support-card.dtsi" - -/ { - model = "UniPhier LD11 Reference Board"; - compatible = "socionext,uniphier-ld11-ref", "socionext,uniphier-ld11"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - aliases { - serial0 = &serial0; - serial1 = &serial1; - serial2 = &serial2; - serial3 = &serial3; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0 0x80000000 0 0x40000000>; - }; -}; - -ðsc { - interrupts = <0 8>; -}; - -&serial0 { - status = "okay"; -}; - -&gpio { - xirq0 { - gpio-hog; - gpios = ; - input; - }; -}; - -&i2c0 { - status = "okay"; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; - -&usb2 { - status = "okay"; -}; - -ð { - status = "okay"; - phy-handle = <ðphy>; -}; - -&mdio { - ethphy: ethphy@1 { - reg = <1>; - }; -}; diff --git a/sys/gnu/dts/arm64/socionext/uniphier-ld11.dtsi b/sys/gnu/dts/arm64/socionext/uniphier-ld11.dtsi deleted file mode 100644 index 5b18bda9c5a..00000000000 --- a/sys/gnu/dts/arm64/socionext/uniphier-ld11.dtsi +++ /dev/null @@ -1,651 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -// -// Device Tree Source for UniPhier LD11 SoC -// -// Copyright (C) 2016 Socionext Inc. -// Author: Masahiro Yamada - -#include -#include - -/ { - compatible = "socionext,uniphier-ld11"; - #address-cells = <2>; - #size-cells = <2>; - interrupt-parent = <&gic>; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu-map { - cluster0 { - core0 { - cpu = <&cpu0>; - }; - core1 { - cpu = <&cpu1>; - }; - }; - }; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0 0x000>; - clocks = <&sys_clk 33>; - enable-method = "psci"; - operating-points-v2 = <&cluster0_opp>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0 0x001>; - clocks = <&sys_clk 33>; - enable-method = "psci"; - operating-points-v2 = <&cluster0_opp>; - }; - }; - - cluster0_opp: opp-table { - compatible = "operating-points-v2"; - opp-shared; - - opp-245000000 { - opp-hz = /bits/ 64 <245000000>; - clock-latency-ns = <300>; - }; - opp-250000000 { - opp-hz = /bits/ 64 <250000000>; - clock-latency-ns = <300>; - }; - opp-490000000 { - opp-hz = /bits/ 64 <490000000>; - clock-latency-ns = <300>; - }; - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - clock-latency-ns = <300>; - }; - opp-653334000 { - opp-hz = /bits/ 64 <653334000>; - clock-latency-ns = <300>; - }; - opp-666667000 { - opp-hz = /bits/ 64 <666667000>; - clock-latency-ns = <300>; - }; - opp-980000000 { - opp-hz = /bits/ 64 <980000000>; - clock-latency-ns = <300>; - }; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - clocks { - refclk: ref { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio UNIPHIER_GPIO_PORT(3, 2) GPIO_ACTIVE_LOW>; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = <1 13 4>, - <1 14 4>, - <1 11 4>, - <1 10 4>; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - secure-memory@81000000 { - reg = <0x0 0x81000000 0x0 0x01000000>; - no-map; - }; - }; - - soc@0 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0 0xffffffff>; - - spi0: spi@54006000 { - compatible = "socionext,uniphier-scssi"; - status = "disabled"; - reg = <0x54006000 0x100>; - interrupts = <0 39 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi0>; - clocks = <&peri_clk 11>; - resets = <&peri_rst 11>; - }; - - spi1: spi@54006100 { - compatible = "socionext,uniphier-scssi"; - status = "disabled"; - reg = <0x54006100 0x100>; - interrupts = <0 216 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1>; - clocks = <&peri_clk 11>; - resets = <&peri_rst 11>; - }; - - serial0: serial@54006800 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006800 0x40>; - interrupts = <0 33 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0>; - clocks = <&peri_clk 0>; - resets = <&peri_rst 0>; - }; - - serial1: serial@54006900 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006900 0x40>; - interrupts = <0 35 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - clocks = <&peri_clk 1>; - resets = <&peri_rst 1>; - }; - - serial2: serial@54006a00 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006a00 0x40>; - interrupts = <0 37 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - clocks = <&peri_clk 2>; - resets = <&peri_rst 2>; - }; - - serial3: serial@54006b00 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006b00 0x40>; - interrupts = <0 177 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - clocks = <&peri_clk 3>; - resets = <&peri_rst 3>; - }; - - gpio: gpio@55000000 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000000 0x200>; - interrupt-parent = <&aidet>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl 0 0 0>, - <&pinctrl 43 0 0>, - <&pinctrl 51 0 0>, - <&pinctrl 96 0 0>, - <&pinctrl 160 0 0>, - <&pinctrl 184 0 0>; - gpio-ranges-group-names = "gpio_range0", - "gpio_range1", - "gpio_range2", - "gpio_range3", - "gpio_range4", - "gpio_range5"; - ngpios = <200>; - socionext,interrupt-ranges = <0 48 16>, <16 154 5>, - <21 217 3>; - }; - - audio@56000000 { - compatible = "socionext,uniphier-ld11-aio"; - reg = <0x56000000 0x80000>; - interrupts = <0 144 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_aout1>, - <&pinctrl_aoutiec1>; - clock-names = "aio"; - clocks = <&sys_clk 40>; - reset-names = "aio"; - resets = <&sys_rst 40>; - #sound-dai-cells = <1>; - socionext,syscon = <&soc_glue>; - - i2s_port0: port@0 { - i2s_hdmi: endpoint { - }; - }; - - i2s_port1: port@1 { - i2s_pcmin2: endpoint { - }; - }; - - i2s_port2: port@2 { - i2s_line: endpoint { - dai-format = "i2s"; - remote-endpoint = <&evea_line>; - }; - }; - - i2s_port3: port@3 { - i2s_hpcmout1: endpoint { - }; - }; - - i2s_port4: port@4 { - i2s_hp: endpoint { - dai-format = "i2s"; - remote-endpoint = <&evea_hp>; - }; - }; - - spdif_port0: port@5 { - spdif_hiecout1: endpoint { - }; - }; - - src_port0: port@6 { - i2s_epcmout2: endpoint { - }; - }; - - src_port1: port@7 { - i2s_epcmout3: endpoint { - }; - }; - - comp_spdif_port0: port@8 { - comp_spdif_hiecout1: endpoint { - }; - }; - }; - - codec@57900000 { - compatible = "socionext,uniphier-evea"; - reg = <0x57900000 0x1000>; - clock-names = "evea", "exiv"; - clocks = <&sys_clk 41>, <&sys_clk 42>; - reset-names = "evea", "exiv", "adamv"; - resets = <&sys_rst 41>, <&sys_rst 42>, <&adamv_rst 0>; - #sound-dai-cells = <1>; - - port@0 { - evea_line: endpoint { - remote-endpoint = <&i2s_line>; - }; - }; - - port@1 { - evea_hp: endpoint { - remote-endpoint = <&i2s_hp>; - }; - }; - }; - - adamv@57920000 { - compatible = "socionext,uniphier-ld11-adamv", - "simple-mfd", "syscon"; - reg = <0x57920000 0x1000>; - - adamv_rst: reset { - compatible = "socionext,uniphier-ld11-adamv-reset"; - #reset-cells = <1>; - }; - }; - - i2c0: i2c@58780000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58780000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 41 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - clocks = <&peri_clk 4>; - resets = <&peri_rst 4>; - clock-frequency = <100000>; - }; - - i2c1: i2c@58781000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58781000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 42 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - clocks = <&peri_clk 5>; - resets = <&peri_rst 5>; - clock-frequency = <100000>; - }; - - i2c2: i2c@58782000 { - compatible = "socionext,uniphier-fi2c"; - reg = <0x58782000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 43 4>; - clocks = <&peri_clk 6>; - resets = <&peri_rst 6>; - clock-frequency = <400000>; - }; - - i2c3: i2c@58783000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58783000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 44 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - clocks = <&peri_clk 7>; - resets = <&peri_rst 7>; - clock-frequency = <100000>; - }; - - i2c4: i2c@58784000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58784000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 45 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4>; - clocks = <&peri_clk 8>; - resets = <&peri_rst 8>; - clock-frequency = <100000>; - }; - - i2c5: i2c@58785000 { - compatible = "socionext,uniphier-fi2c"; - reg = <0x58785000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 25 4>; - clocks = <&peri_clk 9>; - resets = <&peri_rst 9>; - clock-frequency = <400000>; - }; - - system_bus: system-bus@58c00000 { - compatible = "socionext,uniphier-system-bus"; - status = "disabled"; - reg = <0x58c00000 0x400>; - #address-cells = <2>; - #size-cells = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_system_bus>; - }; - - smpctrl@59801000 { - compatible = "socionext,uniphier-smpctrl"; - reg = <0x59801000 0x400>; - }; - - sdctrl@59810000 { - compatible = "socionext,uniphier-ld11-sdctrl", - "simple-mfd", "syscon"; - reg = <0x59810000 0x400>; - - sd_rst: reset { - compatible = "socionext,uniphier-ld11-sd-reset"; - #reset-cells = <1>; - }; - }; - - perictrl@59820000 { - compatible = "socionext,uniphier-ld11-perictrl", - "simple-mfd", "syscon"; - reg = <0x59820000 0x200>; - - peri_clk: clock { - compatible = "socionext,uniphier-ld11-peri-clock"; - #clock-cells = <1>; - }; - - peri_rst: reset { - compatible = "socionext,uniphier-ld11-peri-reset"; - #reset-cells = <1>; - }; - }; - - emmc: sdhc@5a000000 { - compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc"; - reg = <0x5a000000 0x400>; - interrupts = <0 78 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_emmc>; - clocks = <&sys_clk 4>; - resets = <&sys_rst 4>; - bus-width = <8>; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - mmc-pwrseq = <&emmc_pwrseq>; - cdns,phy-input-delay-legacy = <9>; - cdns,phy-input-delay-mmc-highspeed = <2>; - cdns,phy-input-delay-mmc-ddr = <3>; - cdns,phy-dll-delay-sdclk = <21>; - cdns,phy-dll-delay-sdclk-hsmmc = <21>; - }; - - usb0: usb@5a800100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a800100 0x100>; - interrupts = <0 243 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb0>; - clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>, - <&mio_clk 12>; - resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>, - <&mio_rst 12>; - phy-names = "usb"; - phys = <&usb_phy0>; - has-transaction-translator; - }; - - usb1: usb@5a810100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a810100 0x100>; - interrupts = <0 244 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb1>; - clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>, - <&mio_clk 13>; - resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>, - <&mio_rst 13>; - phy-names = "usb"; - phys = <&usb_phy1>; - has-transaction-translator; - }; - - usb2: usb@5a820100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a820100 0x100>; - interrupts = <0 245 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb2>; - clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 10>, - <&mio_clk 14>; - resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>, - <&mio_rst 14>; - phy-names = "usb"; - phys = <&usb_phy2>; - has-transaction-translator; - }; - - mioctrl@5b3e0000 { - compatible = "socionext,uniphier-ld11-mioctrl", - "simple-mfd", "syscon"; - reg = <0x5b3e0000 0x800>; - - mio_clk: clock { - compatible = "socionext,uniphier-ld11-mio-clock"; - #clock-cells = <1>; - }; - - mio_rst: reset { - compatible = "socionext,uniphier-ld11-mio-reset"; - #reset-cells = <1>; - resets = <&sys_rst 7>; - }; - }; - - soc_glue: soc-glue@5f800000 { - compatible = "socionext,uniphier-ld11-soc-glue", - "simple-mfd", "syscon"; - reg = <0x5f800000 0x2000>; - - pinctrl: pinctrl { - compatible = "socionext,uniphier-ld11-pinctrl"; - }; - - usb-phy { - compatible = "socionext,uniphier-ld11-usb2-phy"; - #address-cells = <1>; - #size-cells = <0>; - - usb_phy0: phy@0 { - reg = <0>; - #phy-cells = <0>; - }; - - usb_phy1: phy@1 { - reg = <1>; - #phy-cells = <0>; - }; - - usb_phy2: phy@2 { - reg = <2>; - #phy-cells = <0>; - }; - }; - }; - - soc-glue@5f900000 { - compatible = "socionext,uniphier-ld11-soc-glue-debug", - "simple-mfd"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x5f900000 0x2000>; - - efuse@100 { - compatible = "socionext,uniphier-efuse"; - reg = <0x100 0x28>; - }; - - efuse@200 { - compatible = "socionext,uniphier-efuse"; - reg = <0x200 0x68>; - }; - }; - - aidet: aidet@5fc20000 { - compatible = "socionext,uniphier-ld11-aidet"; - reg = <0x5fc20000 0x200>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gic: interrupt-controller@5fe00000 { - compatible = "arm,gic-v3"; - reg = <0x5fe00000 0x10000>, /* GICD */ - <0x5fe40000 0x80000>; /* GICR */ - interrupt-controller; - #interrupt-cells = <3>; - interrupts = <1 9 4>; - }; - - sysctrl@61840000 { - compatible = "socionext,uniphier-ld11-sysctrl", - "simple-mfd", "syscon"; - reg = <0x61840000 0x10000>; - - sys_clk: clock { - compatible = "socionext,uniphier-ld11-clock"; - #clock-cells = <1>; - }; - - sys_rst: reset { - compatible = "socionext,uniphier-ld11-reset"; - #reset-cells = <1>; - }; - - watchdog { - compatible = "socionext,uniphier-wdt"; - }; - }; - - eth: ethernet@65000000 { - compatible = "socionext,uniphier-ld11-ave4"; - status = "disabled"; - reg = <0x65000000 0x8500>; - interrupts = <0 66 4>; - clock-names = "ether"; - clocks = <&sys_clk 6>; - reset-names = "ether"; - resets = <&sys_rst 6>; - phy-mode = "internal"; - local-mac-address = [00 00 00 00 00 00]; - socionext,syscon-phy-mode = <&soc_glue 0>; - - mdio: mdio { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - nand: nand@68000000 { - compatible = "socionext,uniphier-denali-nand-v5b"; - status = "disabled"; - reg-names = "nand_data", "denali_reg"; - reg = <0x68000000 0x20>, <0x68100000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 65 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nand>; - clock-names = "nand", "nand_x", "ecc"; - clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>; - reset-names = "nand", "reg"; - resets = <&sys_rst 2>, <&sys_rst 2>; - }; - }; -}; - -#include "uniphier-pinctrl.dtsi" - -&pinctrl_aoutiec1 { - drive-strength = <4>; /* default: 4mA */ - - ao1arc { - pins = "AO1ARC"; - drive-strength = <8>; /* 8mA */ - }; -}; diff --git a/sys/gnu/dts/arm64/socionext/uniphier-ld20-global.dts b/sys/gnu/dts/arm64/socionext/uniphier-ld20-global.dts deleted file mode 100644 index 9ca692ed1b2..00000000000 --- a/sys/gnu/dts/arm64/socionext/uniphier-ld20-global.dts +++ /dev/null @@ -1,154 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -// -// Device Tree Source for UniPhier LD20 Global Board -// -// Copyright (C) 2015-2017 Socionext Inc. -// Author: Masahiro Yamada -// Kunihiko Hayashi - -/dts-v1/; -#include -#include "uniphier-ld20.dtsi" - -/ { - model = "UniPhier LD20 Global Board (REF_LD20_GP)"; - compatible = "socionext,uniphier-ld20-global", - "socionext,uniphier-ld20"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - aliases { - serial0 = &serial0; - serial1 = &serial1; - serial2 = &serial2; - serial3 = &serial3; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0 0x80000000 0 0xc0000000>; - }; - - dvdd_reg: reg-fixed { - compatible = "regulator-fixed"; - regulator-name = "DVDD"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - amp_vcc_reg: reg-fixed { - compatible = "regulator-fixed"; - regulator-name = "AMP_VCC"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - sound { - compatible = "audio-graph-card"; - label = "UniPhier LD20"; - widgets = "Headphone", "Headphones"; - dais = <&i2s_port2 - &i2s_port3 - &i2s_port4 - &spdif_port0 - &comp_spdif_port0>; - hp-det-gpio = <&gpio UNIPHIER_GPIO_IRQ(0) GPIO_ACTIVE_LOW>; - }; - - spdif-out { - compatible = "linux,spdif-dit"; - #sound-dai-cells = <0>; - - port@0 { - spdif_tx: endpoint { - remote-endpoint = <&spdif_hiecout1>; - }; - }; - }; - - comp-spdif-out { - compatible = "linux,spdif-dit"; - #sound-dai-cells = <0>; - - port@0 { - comp_spdif_tx: endpoint { - remote-endpoint = <&comp_spdif_hiecout1>; - }; - }; - }; -}; - -&serial0 { - status = "okay"; -}; - -&serial1 { - status = "okay"; -}; - -&i2s_hpcmout1 { - dai-format = "i2s"; - remote-endpoint = <&tas_speaker>; -}; - -&spdif_hiecout1 { - remote-endpoint = <&spdif_tx>; -}; - -&comp_spdif_hiecout1 { - remote-endpoint = <&comp_spdif_tx>; -}; - -&i2c0 { - status = "okay"; - - tas5707@1b { - compatible = "ti,tas5711"; - reg = <0x1b>; - reset-gpios = <&gpio UNIPHIER_GPIO_PORT(0, 0) GPIO_ACTIVE_LOW>; - pdn-gpios = <&gpio UNIPHIER_GPIO_PORT(0, 1) GPIO_ACTIVE_LOW>; - #sound-dai-cells = <0>; - AVDD-supply = <&dvdd_reg>; - DVDD-supply = <&dvdd_reg>; - PVDD_A-supply = <&_vcc_reg>; - PVDD_B-supply = <&_vcc_reg>; - PVDD_C-supply = <&_vcc_reg>; - PVDD_D-supply = <&_vcc_reg>; - - port@0 { - tas_speaker: endpoint { - dai-format = "i2s"; - remote-endpoint = <&i2s_hpcmout1>; - }; - }; - }; -}; - -ð { - status = "okay"; - phy-mode = "rmii"; - pinctrl-0 = <&pinctrl_ether_rmii>; - phy-handle = <ðphy>; -}; - -&mdio { - ethphy: ethphy@1 { - reg = <1>; - }; -}; - -&usb { - status = "okay"; -}; - -&nand { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/socionext/uniphier-ld20-ref.dts b/sys/gnu/dts/arm64/socionext/uniphier-ld20-ref.dts deleted file mode 100644 index 406244a5c8e..00000000000 --- a/sys/gnu/dts/arm64/socionext/uniphier-ld20-ref.dts +++ /dev/null @@ -1,81 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -// -// Device Tree Source for UniPhier LD20 Reference Board -// -// Copyright (C) 2015-2016 Socionext Inc. -// Author: Masahiro Yamada - -/dts-v1/; -#include "uniphier-ld20.dtsi" -#include "uniphier-ref-daughter.dtsi" -#include "uniphier-support-card.dtsi" - -/ { - model = "UniPhier LD20 Reference Board"; - compatible = "socionext,uniphier-ld20-ref", "socionext,uniphier-ld20"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - aliases { - serial0 = &serial0; - serial1 = &serial1; - serial2 = &serial2; - serial3 = &serial3; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0 0x80000000 0 0xc0000000>; - }; -}; - -ðsc { - interrupts = <0 8>; -}; - -&serial0 { - status = "okay"; -}; - -&gpio { - xirq0 { - gpio-hog; - gpios = ; - input; - }; -}; - -&i2c0 { - status = "okay"; -}; - -ð { - status = "okay"; - phy-handle = <ðphy>; -}; - -&mdio { - ethphy: ethphy@0 { - reg = <0>; - }; -}; - -&pinctrl_ether_rgmii { - tx { - pins = "RGMII_TXCLK", "RGMII_TXD0", "RGMII_TXD1", - "RGMII_TXD2", "RGMII_TXD3", "RGMII_TXCTL"; - drive-strength = <9>; - }; -}; - -&usb { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/socionext/uniphier-ld20.dtsi b/sys/gnu/dts/arm64/socionext/uniphier-ld20.dtsi deleted file mode 100644 index f2dc5f69502..00000000000 --- a/sys/gnu/dts/arm64/socionext/uniphier-ld20.dtsi +++ /dev/null @@ -1,964 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -// -// Device Tree Source for UniPhier LD20 SoC -// -// Copyright (C) 2015-2016 Socionext Inc. -// Author: Masahiro Yamada - -#include -#include -#include - -/ { - compatible = "socionext,uniphier-ld20"; - #address-cells = <2>; - #size-cells = <2>; - interrupt-parent = <&gic>; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu-map { - cluster0 { - core0 { - cpu = <&cpu0>; - }; - core1 { - cpu = <&cpu1>; - }; - }; - - cluster1 { - core0 { - cpu = <&cpu2>; - }; - core1 { - cpu = <&cpu3>; - }; - }; - }; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0 0x000>; - clocks = <&sys_clk 32>; - enable-method = "psci"; - operating-points-v2 = <&cluster0_opp>; - #cooling-cells = <2>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0 0x001>; - clocks = <&sys_clk 32>; - enable-method = "psci"; - operating-points-v2 = <&cluster0_opp>; - #cooling-cells = <2>; - }; - - cpu2: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0 0x100>; - clocks = <&sys_clk 33>; - enable-method = "psci"; - operating-points-v2 = <&cluster1_opp>; - #cooling-cells = <2>; - }; - - cpu3: cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0 0x101>; - clocks = <&sys_clk 33>; - enable-method = "psci"; - operating-points-v2 = <&cluster1_opp>; - #cooling-cells = <2>; - }; - }; - - cluster0_opp: opp-table0 { - compatible = "operating-points-v2"; - opp-shared; - - opp-250000000 { - opp-hz = /bits/ 64 <250000000>; - clock-latency-ns = <300>; - }; - opp-275000000 { - opp-hz = /bits/ 64 <275000000>; - clock-latency-ns = <300>; - }; - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - clock-latency-ns = <300>; - }; - opp-550000000 { - opp-hz = /bits/ 64 <550000000>; - clock-latency-ns = <300>; - }; - opp-666667000 { - opp-hz = /bits/ 64 <666667000>; - clock-latency-ns = <300>; - }; - opp-733334000 { - opp-hz = /bits/ 64 <733334000>; - clock-latency-ns = <300>; - }; - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - clock-latency-ns = <300>; - }; - opp-1100000000 { - opp-hz = /bits/ 64 <1100000000>; - clock-latency-ns = <300>; - }; - }; - - cluster1_opp: opp-table1 { - compatible = "operating-points-v2"; - opp-shared; - - opp-250000000 { - opp-hz = /bits/ 64 <250000000>; - clock-latency-ns = <300>; - }; - opp-275000000 { - opp-hz = /bits/ 64 <275000000>; - clock-latency-ns = <300>; - }; - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - clock-latency-ns = <300>; - }; - opp-550000000 { - opp-hz = /bits/ 64 <550000000>; - clock-latency-ns = <300>; - }; - opp-666667000 { - opp-hz = /bits/ 64 <666667000>; - clock-latency-ns = <300>; - }; - opp-733334000 { - opp-hz = /bits/ 64 <733334000>; - clock-latency-ns = <300>; - }; - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - clock-latency-ns = <300>; - }; - opp-1100000000 { - opp-hz = /bits/ 64 <1100000000>; - clock-latency-ns = <300>; - }; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - clocks { - refclk: ref { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio UNIPHIER_GPIO_PORT(3, 2) GPIO_ACTIVE_LOW>; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = <1 13 4>, - <1 14 4>, - <1 11 4>, - <1 10 4>; - }; - - thermal-zones { - cpu-thermal { - polling-delay-passive = <250>; /* 250ms */ - polling-delay = <1000>; /* 1000ms */ - thermal-sensors = <&pvtctl>; - - trips { - cpu_crit: cpu-crit { - temperature = <110000>; /* 110C */ - hysteresis = <2000>; - type = "critical"; - }; - cpu_alert: cpu-alert { - temperature = <100000>; /* 100C */ - hysteresis = <2000>; - type = "passive"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu_alert>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - secure-memory@81000000 { - reg = <0x0 0x81000000 0x0 0x01000000>; - no-map; - }; - }; - - soc@0 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0 0xffffffff>; - - spi0: spi@54006000 { - compatible = "socionext,uniphier-scssi"; - status = "disabled"; - reg = <0x54006000 0x100>; - interrupts = <0 39 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi0>; - clocks = <&peri_clk 11>; - resets = <&peri_rst 11>; - }; - - spi1: spi@54006100 { - compatible = "socionext,uniphier-scssi"; - status = "disabled"; - reg = <0x54006100 0x100>; - interrupts = <0 216 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1>; - clocks = <&peri_clk 11>; - resets = <&peri_rst 11>; - }; - - spi2: spi@54006200 { - compatible = "socionext,uniphier-scssi"; - status = "disabled"; - reg = <0x54006200 0x100>; - interrupts = <0 229 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi2>; - clocks = <&peri_clk 11>; - resets = <&peri_rst 11>; - }; - - spi3: spi@54006300 { - compatible = "socionext,uniphier-scssi"; - status = "disabled"; - reg = <0x54006300 0x100>; - interrupts = <0 230 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi3>; - clocks = <&peri_clk 11>; - resets = <&peri_rst 11>; - }; - - serial0: serial@54006800 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006800 0x40>; - interrupts = <0 33 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0>; - clocks = <&peri_clk 0>; - resets = <&peri_rst 0>; - }; - - serial1: serial@54006900 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006900 0x40>; - interrupts = <0 35 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - clocks = <&peri_clk 1>; - resets = <&peri_rst 1>; - }; - - serial2: serial@54006a00 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006a00 0x40>; - interrupts = <0 37 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - clocks = <&peri_clk 2>; - resets = <&peri_rst 2>; - }; - - serial3: serial@54006b00 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006b00 0x40>; - interrupts = <0 177 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - clocks = <&peri_clk 3>; - resets = <&peri_rst 3>; - }; - - gpio: gpio@55000000 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000000 0x200>; - interrupt-parent = <&aidet>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl 0 0 0>, - <&pinctrl 96 0 0>, - <&pinctrl 160 0 0>; - gpio-ranges-group-names = "gpio_range0", - "gpio_range1", - "gpio_range2"; - ngpios = <205>; - socionext,interrupt-ranges = <0 48 16>, <16 154 5>, - <21 217 3>; - }; - - audio@56000000 { - compatible = "socionext,uniphier-ld20-aio"; - reg = <0x56000000 0x80000>; - interrupts = <0 144 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_aout1>, - <&pinctrl_aoutiec1>; - clock-names = "aio"; - clocks = <&sys_clk 40>; - reset-names = "aio"; - resets = <&sys_rst 40>; - #sound-dai-cells = <1>; - socionext,syscon = <&soc_glue>; - - i2s_port0: port@0 { - i2s_hdmi: endpoint { - }; - }; - - i2s_port1: port@1 { - i2s_pcmin2: endpoint { - }; - }; - - i2s_port2: port@2 { - i2s_line: endpoint { - dai-format = "i2s"; - remote-endpoint = <&evea_line>; - }; - }; - - i2s_port3: port@3 { - i2s_hpcmout1: endpoint { - }; - }; - - i2s_port4: port@4 { - i2s_hp: endpoint { - dai-format = "i2s"; - remote-endpoint = <&evea_hp>; - }; - }; - - spdif_port0: port@5 { - spdif_hiecout1: endpoint { - }; - }; - - src_port0: port@6 { - i2s_epcmout2: endpoint { - }; - }; - - src_port1: port@7 { - i2s_epcmout3: endpoint { - }; - }; - - comp_spdif_port0: port@8 { - comp_spdif_hiecout1: endpoint { - }; - }; - }; - - codec@57900000 { - compatible = "socionext,uniphier-evea"; - reg = <0x57900000 0x1000>; - clock-names = "evea", "exiv"; - clocks = <&sys_clk 41>, <&sys_clk 42>; - reset-names = "evea", "exiv", "adamv"; - resets = <&sys_rst 41>, <&sys_rst 42>, <&adamv_rst 0>; - #sound-dai-cells = <1>; - - port@0 { - evea_line: endpoint { - remote-endpoint = <&i2s_line>; - }; - }; - - port@1 { - evea_hp: endpoint { - remote-endpoint = <&i2s_hp>; - }; - }; - }; - - adamv@57920000 { - compatible = "socionext,uniphier-ld20-adamv", - "simple-mfd", "syscon"; - reg = <0x57920000 0x1000>; - - adamv_rst: reset { - compatible = "socionext,uniphier-ld20-adamv-reset"; - #reset-cells = <1>; - }; - }; - - i2c0: i2c@58780000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58780000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 41 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - clocks = <&peri_clk 4>; - resets = <&peri_rst 4>; - clock-frequency = <100000>; - }; - - i2c1: i2c@58781000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58781000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 42 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - clocks = <&peri_clk 5>; - resets = <&peri_rst 5>; - clock-frequency = <100000>; - }; - - i2c2: i2c@58782000 { - compatible = "socionext,uniphier-fi2c"; - reg = <0x58782000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 43 4>; - clocks = <&peri_clk 6>; - resets = <&peri_rst 6>; - clock-frequency = <400000>; - }; - - i2c3: i2c@58783000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58783000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 44 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - clocks = <&peri_clk 7>; - resets = <&peri_rst 7>; - clock-frequency = <100000>; - }; - - i2c4: i2c@58784000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58784000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 45 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4>; - clocks = <&peri_clk 8>; - resets = <&peri_rst 8>; - clock-frequency = <100000>; - }; - - i2c5: i2c@58785000 { - compatible = "socionext,uniphier-fi2c"; - reg = <0x58785000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 25 4>; - clocks = <&peri_clk 9>; - resets = <&peri_rst 9>; - clock-frequency = <400000>; - }; - - system_bus: system-bus@58c00000 { - compatible = "socionext,uniphier-system-bus"; - status = "disabled"; - reg = <0x58c00000 0x400>; - #address-cells = <2>; - #size-cells = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_system_bus>; - }; - - smpctrl@59801000 { - compatible = "socionext,uniphier-smpctrl"; - reg = <0x59801000 0x400>; - }; - - sdctrl@59810000 { - compatible = "socionext,uniphier-ld20-sdctrl", - "simple-mfd", "syscon"; - reg = <0x59810000 0x400>; - - sd_clk: clock { - compatible = "socionext,uniphier-ld20-sd-clock"; - #clock-cells = <1>; - }; - - sd_rst: reset { - compatible = "socionext,uniphier-ld20-sd-reset"; - #reset-cells = <1>; - }; - }; - - perictrl@59820000 { - compatible = "socionext,uniphier-ld20-perictrl", - "simple-mfd", "syscon"; - reg = <0x59820000 0x200>; - - peri_clk: clock { - compatible = "socionext,uniphier-ld20-peri-clock"; - #clock-cells = <1>; - }; - - peri_rst: reset { - compatible = "socionext,uniphier-ld20-peri-reset"; - #reset-cells = <1>; - }; - }; - - emmc: sdhc@5a000000 { - compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc"; - reg = <0x5a000000 0x400>; - interrupts = <0 78 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_emmc>; - clocks = <&sys_clk 4>; - resets = <&sys_rst 4>; - bus-width = <8>; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - mmc-pwrseq = <&emmc_pwrseq>; - cdns,phy-input-delay-legacy = <9>; - cdns,phy-input-delay-mmc-highspeed = <2>; - cdns,phy-input-delay-mmc-ddr = <3>; - cdns,phy-dll-delay-sdclk = <21>; - cdns,phy-dll-delay-sdclk-hsmmc = <21>; - }; - - sd: sdhc@5a400000 { - compatible = "socionext,uniphier-sd-v3.1.1"; - status = "disabled"; - reg = <0x5a400000 0x800>; - interrupts = <0 76 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sd>; - clocks = <&sd_clk 0>; - reset-names = "host"; - resets = <&sd_rst 0>; - bus-width = <4>; - cap-sd-highspeed; - }; - - soc_glue: soc-glue@5f800000 { - compatible = "socionext,uniphier-ld20-soc-glue", - "simple-mfd", "syscon"; - reg = <0x5f800000 0x2000>; - - pinctrl: pinctrl { - compatible = "socionext,uniphier-ld20-pinctrl"; - }; - }; - - soc-glue@5f900000 { - compatible = "socionext,uniphier-ld20-soc-glue-debug", - "simple-mfd"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x5f900000 0x2000>; - - efuse@100 { - compatible = "socionext,uniphier-efuse"; - reg = <0x100 0x28>; - }; - - efuse@200 { - compatible = "socionext,uniphier-efuse"; - reg = <0x200 0x68>; - #address-cells = <1>; - #size-cells = <1>; - - /* USB cells */ - usb_rterm0: trim@54,4 { - reg = <0x54 1>; - bits = <4 2>; - }; - usb_rterm1: trim@55,4 { - reg = <0x55 1>; - bits = <4 2>; - }; - usb_rterm2: trim@58,4 { - reg = <0x58 1>; - bits = <4 2>; - }; - usb_rterm3: trim@59,4 { - reg = <0x59 1>; - bits = <4 2>; - }; - usb_sel_t0: trim@54,0 { - reg = <0x54 1>; - bits = <0 4>; - }; - usb_sel_t1: trim@55,0 { - reg = <0x55 1>; - bits = <0 4>; - }; - usb_sel_t2: trim@58,0 { - reg = <0x58 1>; - bits = <0 4>; - }; - usb_sel_t3: trim@59,0 { - reg = <0x59 1>; - bits = <0 4>; - }; - usb_hs_i0: trim@56,0 { - reg = <0x56 1>; - bits = <0 4>; - }; - usb_hs_i2: trim@5a,0 { - reg = <0x5a 1>; - bits = <0 4>; - }; - }; - }; - - aidet: aidet@5fc20000 { - compatible = "socionext,uniphier-ld20-aidet"; - reg = <0x5fc20000 0x200>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gic: interrupt-controller@5fe00000 { - compatible = "arm,gic-v3"; - reg = <0x5fe00000 0x10000>, /* GICD */ - <0x5fe80000 0x80000>; /* GICR */ - interrupt-controller; - #interrupt-cells = <3>; - interrupts = <1 9 4>; - }; - - sysctrl@61840000 { - compatible = "socionext,uniphier-ld20-sysctrl", - "simple-mfd", "syscon"; - reg = <0x61840000 0x10000>; - - sys_clk: clock { - compatible = "socionext,uniphier-ld20-clock"; - #clock-cells = <1>; - }; - - sys_rst: reset { - compatible = "socionext,uniphier-ld20-reset"; - #reset-cells = <1>; - }; - - watchdog { - compatible = "socionext,uniphier-wdt"; - }; - - pvtctl: pvtctl { - compatible = "socionext,uniphier-ld20-thermal"; - interrupts = <0 3 4>; - #thermal-sensor-cells = <0>; - socionext,tmod-calibration = <0x0f22 0x68ee>; - }; - }; - - eth: ethernet@65000000 { - compatible = "socionext,uniphier-ld20-ave4"; - status = "disabled"; - reg = <0x65000000 0x8500>; - interrupts = <0 66 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ether_rgmii>; - clock-names = "ether"; - clocks = <&sys_clk 6>; - reset-names = "ether"; - resets = <&sys_rst 6>; - phy-mode = "rgmii"; - local-mac-address = [00 00 00 00 00 00]; - socionext,syscon-phy-mode = <&soc_glue 0>; - - mdio: mdio { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - usb: usb@65a00000 { - compatible = "socionext,uniphier-dwc3", "snps,dwc3"; - status = "disabled"; - reg = <0x65a00000 0xcd00>; - interrupt-names = "host"; - interrupts = <0 134 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb1>, - <&pinctrl_usb2>, <&pinctrl_usb3>; - clock-names = "ref", "bus_early", "suspend"; - clocks = <&sys_clk 14>, <&sys_clk 14>, <&sys_clk 14>; - resets = <&usb_rst 15>; - phys = <&usb_hsphy0>, <&usb_hsphy1>, - <&usb_hsphy2>, <&usb_hsphy3>, - <&usb_ssphy0>, <&usb_ssphy1>; - dr_mode = "host"; - }; - - usb-glue@65b00000 { - compatible = "socionext,uniphier-ld20-dwc3-glue", - "simple-mfd"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x65b00000 0x400>; - - usb_rst: reset@0 { - compatible = "socionext,uniphier-ld20-usb3-reset"; - reg = <0x0 0x4>; - #reset-cells = <1>; - clock-names = "link"; - clocks = <&sys_clk 14>; - reset-names = "link"; - resets = <&sys_rst 14>; - }; - - usb_vbus0: regulator@100 { - compatible = "socionext,uniphier-ld20-usb3-regulator"; - reg = <0x100 0x10>; - clock-names = "link"; - clocks = <&sys_clk 14>; - reset-names = "link"; - resets = <&sys_rst 14>; - }; - - usb_vbus1: regulator@110 { - compatible = "socionext,uniphier-ld20-usb3-regulator"; - reg = <0x110 0x10>; - clock-names = "link"; - clocks = <&sys_clk 14>; - reset-names = "link"; - resets = <&sys_rst 14>; - }; - - usb_vbus2: regulator@120 { - compatible = "socionext,uniphier-ld20-usb3-regulator"; - reg = <0x120 0x10>; - clock-names = "link"; - clocks = <&sys_clk 14>; - reset-names = "link"; - resets = <&sys_rst 14>; - }; - - usb_vbus3: regulator@130 { - compatible = "socionext,uniphier-ld20-usb3-regulator"; - reg = <0x130 0x10>; - clock-names = "link"; - clocks = <&sys_clk 14>; - reset-names = "link"; - resets = <&sys_rst 14>; - }; - - usb_hsphy0: hs-phy@200 { - compatible = "socionext,uniphier-ld20-usb3-hsphy"; - reg = <0x200 0x10>; - #phy-cells = <0>; - clock-names = "link", "phy"; - clocks = <&sys_clk 14>, <&sys_clk 16>; - reset-names = "link", "phy"; - resets = <&sys_rst 14>, <&sys_rst 16>; - vbus-supply = <&usb_vbus0>; - nvmem-cell-names = "rterm", "sel_t", "hs_i"; - nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>, - <&usb_hs_i0>; - }; - - usb_hsphy1: hs-phy@210 { - compatible = "socionext,uniphier-ld20-usb3-hsphy"; - reg = <0x210 0x10>; - #phy-cells = <0>; - clock-names = "link", "phy"; - clocks = <&sys_clk 14>, <&sys_clk 16>; - reset-names = "link", "phy"; - resets = <&sys_rst 14>, <&sys_rst 16>; - vbus-supply = <&usb_vbus1>; - nvmem-cell-names = "rterm", "sel_t", "hs_i"; - nvmem-cells = <&usb_rterm1>, <&usb_sel_t1>, - <&usb_hs_i0>; - }; - - usb_hsphy2: hs-phy@220 { - compatible = "socionext,uniphier-ld20-usb3-hsphy"; - reg = <0x220 0x10>; - #phy-cells = <0>; - clock-names = "link", "phy"; - clocks = <&sys_clk 14>, <&sys_clk 17>; - reset-names = "link", "phy"; - resets = <&sys_rst 14>, <&sys_rst 17>; - vbus-supply = <&usb_vbus2>; - nvmem-cell-names = "rterm", "sel_t", "hs_i"; - nvmem-cells = <&usb_rterm2>, <&usb_sel_t2>, - <&usb_hs_i2>; - }; - - usb_hsphy3: hs-phy@230 { - compatible = "socionext,uniphier-ld20-usb3-hsphy"; - reg = <0x230 0x10>; - #phy-cells = <0>; - clock-names = "link", "phy"; - clocks = <&sys_clk 14>, <&sys_clk 17>; - reset-names = "link", "phy"; - resets = <&sys_rst 14>, <&sys_rst 17>; - vbus-supply = <&usb_vbus3>; - nvmem-cell-names = "rterm", "sel_t", "hs_i"; - nvmem-cells = <&usb_rterm3>, <&usb_sel_t3>, - <&usb_hs_i2>; - }; - - usb_ssphy0: ss-phy@300 { - compatible = "socionext,uniphier-ld20-usb3-ssphy"; - reg = <0x300 0x10>; - #phy-cells = <0>; - clock-names = "link", "phy"; - clocks = <&sys_clk 14>, <&sys_clk 18>; - reset-names = "link", "phy"; - resets = <&sys_rst 14>, <&sys_rst 18>; - vbus-supply = <&usb_vbus0>; - }; - - usb_ssphy1: ss-phy@310 { - compatible = "socionext,uniphier-ld20-usb3-ssphy"; - reg = <0x310 0x10>; - #phy-cells = <0>; - clock-names = "link", "phy"; - clocks = <&sys_clk 14>, <&sys_clk 19>; - reset-names = "link", "phy"; - resets = <&sys_rst 14>, <&sys_rst 19>; - vbus-supply = <&usb_vbus1>; - }; - }; - - pcie: pcie@66000000 { - compatible = "socionext,uniphier-pcie", "snps,dw-pcie"; - status = "disabled"; - reg-names = "dbi", "link", "config"; - reg = <0x66000000 0x1000>, <0x66010000 0x10000>, - <0x2fff0000 0x10000>; - #address-cells = <3>; - #size-cells = <2>; - clocks = <&sys_clk 24>; - resets = <&sys_rst 24>; - num-lanes = <1>; - num-viewport = <1>; - bus-range = <0x0 0xff>; - device_type = "pci"; - ranges = - /* downstream I/O */ - <0x81000000 0 0x00000000 0x2ffe0000 0 0x00010000>, - /* non-prefetchable memory */ - <0x82000000 0 0x20000000 0x20000000 0 0x0ffe0000>; - #interrupt-cells = <1>; - interrupt-names = "dma", "msi"; - interrupts = <0 224 4>, <0 225 4>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie_intc 0>, /* INTA */ - <0 0 0 2 &pcie_intc 1>, /* INTB */ - <0 0 0 3 &pcie_intc 2>, /* INTC */ - <0 0 0 4 &pcie_intc 3>; /* INTD */ - phy-names = "pcie-phy"; - phys = <&pcie_phy>; - - pcie_intc: legacy-interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - interrupt-parent = <&gic>; - interrupts = <0 226 4>; - }; - }; - - pcie_phy: phy@66038000 { - compatible = "socionext,uniphier-ld20-pcie-phy"; - reg = <0x66038000 0x4000>; - #phy-cells = <0>; - clocks = <&sys_clk 24>; - resets = <&sys_rst 24>; - socionext,syscon = <&soc_glue>; - }; - - nand: nand@68000000 { - compatible = "socionext,uniphier-denali-nand-v5b"; - status = "disabled"; - reg-names = "nand_data", "denali_reg"; - reg = <0x68000000 0x20>, <0x68100000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 65 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nand>; - clock-names = "nand", "nand_x", "ecc"; - clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>; - reset-names = "nand", "reg"; - resets = <&sys_rst 2>, <&sys_rst 2>; - }; - }; -}; - -#include "uniphier-pinctrl.dtsi" - -&pinctrl_aout1 { - drive-strength = <4>; /* default: 3.5mA */ - - ao1dacck { - pins = "AO1DACCK"; - drive-strength = <5>; /* 5mA */ - }; -}; - -&pinctrl_aoutiec1 { - drive-strength = <4>; /* default: 3.5mA */ - - ao1arc { - pins = "AO1ARC"; - drive-strength = <11>; /* 11mA */ - }; -}; diff --git a/sys/gnu/dts/arm64/socionext/uniphier-pinctrl.dtsi b/sys/gnu/dts/arm64/socionext/uniphier-pinctrl.dtsi deleted file mode 100644 index 9caabbb8bae..00000000000 --- a/sys/gnu/dts/arm64/socionext/uniphier-pinctrl.dtsi +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/sys/gnu/dts/arm64/socionext/uniphier-pxs3-ref.dts b/sys/gnu/dts/arm64/socionext/uniphier-pxs3-ref.dts deleted file mode 100644 index 754315bbd1c..00000000000 --- a/sys/gnu/dts/arm64/socionext/uniphier-pxs3-ref.dts +++ /dev/null @@ -1,122 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -// -// Device Tree Source for UniPhier PXs3 Reference Board -// -// Copyright (C) 2017 Socionext Inc. -// Author: Masahiro Yamada - -/dts-v1/; -#include "uniphier-pxs3.dtsi" -#include "uniphier-support-card.dtsi" - -/ { - model = "UniPhier PXs3 Reference Board"; - compatible = "socionext,uniphier-pxs3-ref", "socionext,uniphier-pxs3"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - aliases { - serial0 = &serial0; - serial1 = &serial1; - serial2 = &serial2; - serial3 = &serial3; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c6 = &i2c6; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0 0x80000000 0 0xa0000000>; - }; -}; - -ðsc { - interrupts = <4 8>; -}; - -&serial0 { - status = "okay"; -}; - -&serial2 { - status = "okay"; -}; - -&serial3 { - status = "okay"; -}; - -&gpio { - xirq4 { - gpio-hog; - gpios = ; - input; - }; -}; - -&i2c0 { - status = "okay"; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c3 { - status = "okay"; -}; - -&sd { - status = "okay"; -}; - -ð0 { - status = "okay"; - phy-handle = <ðphy0>; -}; - -&mdio0 { - ethphy0: ethphy@0 { - reg = <0>; - }; -}; - -ð1 { - status = "okay"; - phy-handle = <ðphy1>; -}; - -&mdio1 { - ethphy1: ethphy@0 { - reg = <0>; - }; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; - -&pcie { - status = "okay"; -}; - -&nand { - status = "okay"; - - nand@0 { - reg = <0>; - }; -}; diff --git a/sys/gnu/dts/arm64/socionext/uniphier-pxs3.dtsi b/sys/gnu/dts/arm64/socionext/uniphier-pxs3.dtsi deleted file mode 100644 index 73e7e1203b0..00000000000 --- a/sys/gnu/dts/arm64/socionext/uniphier-pxs3.dtsi +++ /dev/null @@ -1,804 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -// -// Device Tree Source for UniPhier PXs3 SoC -// -// Copyright (C) 2017 Socionext Inc. -// Author: Masahiro Yamada - -#include -#include - -/ { - compatible = "socionext,uniphier-pxs3"; - #address-cells = <2>; - #size-cells = <2>; - interrupt-parent = <&gic>; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu-map { - cluster0 { - core0 { - cpu = <&cpu0>; - }; - core1 { - cpu = <&cpu1>; - }; - core2 { - cpu = <&cpu2>; - }; - core3 { - cpu = <&cpu3>; - }; - }; - }; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0 0x000>; - clocks = <&sys_clk 33>; - enable-method = "psci"; - operating-points-v2 = <&cluster0_opp>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0 0x001>; - clocks = <&sys_clk 33>; - enable-method = "psci"; - operating-points-v2 = <&cluster0_opp>; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0 0x002>; - clocks = <&sys_clk 33>; - enable-method = "psci"; - operating-points-v2 = <&cluster0_opp>; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0 0x003>; - clocks = <&sys_clk 33>; - enable-method = "psci"; - operating-points-v2 = <&cluster0_opp>; - }; - }; - - cluster0_opp: opp-table { - compatible = "operating-points-v2"; - opp-shared; - - opp-250000000 { - opp-hz = /bits/ 64 <250000000>; - clock-latency-ns = <300>; - }; - opp-325000000 { - opp-hz = /bits/ 64 <325000000>; - clock-latency-ns = <300>; - }; - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - clock-latency-ns = <300>; - }; - opp-650000000 { - opp-hz = /bits/ 64 <650000000>; - clock-latency-ns = <300>; - }; - opp-666667000 { - opp-hz = /bits/ 64 <666667000>; - clock-latency-ns = <300>; - }; - opp-866667000 { - opp-hz = /bits/ 64 <866667000>; - clock-latency-ns = <300>; - }; - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - clock-latency-ns = <300>; - }; - opp-1300000000 { - opp-hz = /bits/ 64 <1300000000>; - clock-latency-ns = <300>; - }; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - clocks { - refclk: ref { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio UNIPHIER_GPIO_PORT(5, 7) GPIO_ACTIVE_LOW>; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = <1 13 4>, - <1 14 4>, - <1 11 4>, - <1 10 4>; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - secure-memory@81000000 { - reg = <0x0 0x81000000 0x0 0x01000000>; - no-map; - }; - }; - - soc@0 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0 0xffffffff>; - - spi0: spi@54006000 { - compatible = "socionext,uniphier-scssi"; - status = "disabled"; - reg = <0x54006000 0x100>; - interrupts = <0 39 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi0>; - clocks = <&peri_clk 11>; - resets = <&peri_rst 11>; - }; - - spi1: spi@54006100 { - compatible = "socionext,uniphier-scssi"; - status = "disabled"; - reg = <0x54006100 0x100>; - interrupts = <0 216 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1>; - clocks = <&peri_clk 11>; - resets = <&peri_rst 11>; - }; - - serial0: serial@54006800 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006800 0x40>; - interrupts = <0 33 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0>; - clocks = <&peri_clk 0>; - resets = <&peri_rst 0>; - }; - - serial1: serial@54006900 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006900 0x40>; - interrupts = <0 35 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - clocks = <&peri_clk 1>; - resets = <&peri_rst 1>; - }; - - serial2: serial@54006a00 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006a00 0x40>; - interrupts = <0 37 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - clocks = <&peri_clk 2>; - resets = <&peri_rst 2>; - }; - - serial3: serial@54006b00 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006b00 0x40>; - interrupts = <0 177 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - clocks = <&peri_clk 3>; - resets = <&peri_rst 3>; - }; - - gpio: gpio@55000000 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000000 0x200>; - interrupt-parent = <&aidet>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl 0 0 0>, - <&pinctrl 104 0 0>, - <&pinctrl 168 0 0>; - gpio-ranges-group-names = "gpio_range0", - "gpio_range1", - "gpio_range2"; - ngpios = <286>; - socionext,interrupt-ranges = <0 48 16>, <16 154 5>, - <21 217 3>; - }; - - i2c0: i2c@58780000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58780000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 41 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - clocks = <&peri_clk 4>; - resets = <&peri_rst 4>; - clock-frequency = <100000>; - }; - - i2c1: i2c@58781000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58781000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 42 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - clocks = <&peri_clk 5>; - resets = <&peri_rst 5>; - clock-frequency = <100000>; - }; - - i2c2: i2c@58782000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58782000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 43 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - clocks = <&peri_clk 6>; - resets = <&peri_rst 6>; - clock-frequency = <100000>; - }; - - i2c3: i2c@58783000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58783000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 44 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - clocks = <&peri_clk 7>; - resets = <&peri_rst 7>; - clock-frequency = <100000>; - }; - - /* chip-internal connection for HDMI */ - i2c6: i2c@58786000 { - compatible = "socionext,uniphier-fi2c"; - reg = <0x58786000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 26 4>; - clocks = <&peri_clk 10>; - resets = <&peri_rst 10>; - clock-frequency = <400000>; - }; - - system_bus: system-bus@58c00000 { - compatible = "socionext,uniphier-system-bus"; - status = "disabled"; - reg = <0x58c00000 0x400>; - #address-cells = <2>; - #size-cells = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_system_bus>; - }; - - smpctrl@59801000 { - compatible = "socionext,uniphier-smpctrl"; - reg = <0x59801000 0x400>; - }; - - sdctrl@59810000 { - compatible = "socionext,uniphier-pxs3-sdctrl", - "simple-mfd", "syscon"; - reg = <0x59810000 0x400>; - - sd_clk: clock { - compatible = "socionext,uniphier-pxs3-sd-clock"; - #clock-cells = <1>; - }; - - sd_rst: reset { - compatible = "socionext,uniphier-pxs3-sd-reset"; - #reset-cells = <1>; - }; - }; - - perictrl@59820000 { - compatible = "socionext,uniphier-pxs3-perictrl", - "simple-mfd", "syscon"; - reg = <0x59820000 0x200>; - - peri_clk: clock { - compatible = "socionext,uniphier-pxs3-peri-clock"; - #clock-cells = <1>; - }; - - peri_rst: reset { - compatible = "socionext,uniphier-pxs3-peri-reset"; - #reset-cells = <1>; - }; - }; - - emmc: sdhc@5a000000 { - compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc"; - reg = <0x5a000000 0x400>; - interrupts = <0 78 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_emmc>; - clocks = <&sys_clk 4>; - resets = <&sys_rst 4>; - bus-width = <8>; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - mmc-pwrseq = <&emmc_pwrseq>; - cdns,phy-input-delay-legacy = <9>; - cdns,phy-input-delay-mmc-highspeed = <2>; - cdns,phy-input-delay-mmc-ddr = <3>; - cdns,phy-dll-delay-sdclk = <21>; - cdns,phy-dll-delay-sdclk-hsmmc = <21>; - }; - - sd: sdhc@5a400000 { - compatible = "socionext,uniphier-sd-v3.1.1"; - status = "disabled"; - reg = <0x5a400000 0x800>; - interrupts = <0 76 4>; - pinctrl-names = "default", "uhs"; - pinctrl-0 = <&pinctrl_sd>; - pinctrl-1 = <&pinctrl_sd_uhs>; - clocks = <&sd_clk 0>; - reset-names = "host"; - resets = <&sd_rst 0>; - bus-width = <4>; - cap-sd-highspeed; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - }; - - soc_glue: soc-glue@5f800000 { - compatible = "socionext,uniphier-pxs3-soc-glue", - "simple-mfd", "syscon"; - reg = <0x5f800000 0x2000>; - - pinctrl: pinctrl { - compatible = "socionext,uniphier-pxs3-pinctrl"; - }; - }; - - soc-glue@5f900000 { - compatible = "socionext,uniphier-pxs3-soc-glue-debug", - "simple-mfd"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x5f900000 0x2000>; - - efuse@100 { - compatible = "socionext,uniphier-efuse"; - reg = <0x100 0x28>; - }; - - efuse@200 { - compatible = "socionext,uniphier-efuse"; - reg = <0x200 0x68>; - #address-cells = <1>; - #size-cells = <1>; - - /* USB cells */ - usb_rterm0: trim@54,4 { - reg = <0x54 1>; - bits = <4 2>; - }; - usb_rterm1: trim@55,4 { - reg = <0x55 1>; - bits = <4 2>; - }; - usb_rterm2: trim@58,4 { - reg = <0x58 1>; - bits = <4 2>; - }; - usb_rterm3: trim@59,4 { - reg = <0x59 1>; - bits = <4 2>; - }; - usb_sel_t0: trim@54,0 { - reg = <0x54 1>; - bits = <0 4>; - }; - usb_sel_t1: trim@55,0 { - reg = <0x55 1>; - bits = <0 4>; - }; - usb_sel_t2: trim@58,0 { - reg = <0x58 1>; - bits = <0 4>; - }; - usb_sel_t3: trim@59,0 { - reg = <0x59 1>; - bits = <0 4>; - }; - usb_hs_i0: trim@56,0 { - reg = <0x56 1>; - bits = <0 4>; - }; - usb_hs_i2: trim@5a,0 { - reg = <0x5a 1>; - bits = <0 4>; - }; - }; - }; - - aidet: aidet@5fc20000 { - compatible = "socionext,uniphier-pxs3-aidet"; - reg = <0x5fc20000 0x200>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gic: interrupt-controller@5fe00000 { - compatible = "arm,gic-v3"; - reg = <0x5fe00000 0x10000>, /* GICD */ - <0x5fe80000 0x80000>; /* GICR */ - interrupt-controller; - #interrupt-cells = <3>; - interrupts = <1 9 4>; - }; - - sysctrl@61840000 { - compatible = "socionext,uniphier-pxs3-sysctrl", - "simple-mfd", "syscon"; - reg = <0x61840000 0x10000>; - - sys_clk: clock { - compatible = "socionext,uniphier-pxs3-clock"; - #clock-cells = <1>; - }; - - sys_rst: reset { - compatible = "socionext,uniphier-pxs3-reset"; - #reset-cells = <1>; - }; - - watchdog { - compatible = "socionext,uniphier-wdt"; - }; - }; - - eth0: ethernet@65000000 { - compatible = "socionext,uniphier-pxs3-ave4"; - status = "disabled"; - reg = <0x65000000 0x8500>; - interrupts = <0 66 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ether_rgmii>; - clock-names = "ether"; - clocks = <&sys_clk 6>; - reset-names = "ether"; - resets = <&sys_rst 6>; - phy-mode = "rgmii"; - local-mac-address = [00 00 00 00 00 00]; - socionext,syscon-phy-mode = <&soc_glue 0>; - - mdio0: mdio { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - eth1: ethernet@65200000 { - compatible = "socionext,uniphier-pxs3-ave4"; - status = "disabled"; - reg = <0x65200000 0x8500>; - interrupts = <0 67 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ether1_rgmii>; - clock-names = "ether"; - clocks = <&sys_clk 7>; - reset-names = "ether"; - resets = <&sys_rst 7>; - phy-mode = "rgmii"; - local-mac-address = [00 00 00 00 00 00]; - socionext,syscon-phy-mode = <&soc_glue 1>; - - mdio1: mdio { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - usb0: usb@65a00000 { - compatible = "socionext,uniphier-dwc3", "snps,dwc3"; - status = "disabled"; - reg = <0x65a00000 0xcd00>; - interrupt-names = "host", "peripheral"; - interrupts = <0 134 4>, <0 135 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>; - clock-names = "ref", "bus_early", "suspend"; - clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>; - resets = <&usb0_rst 15>; - phys = <&usb0_hsphy0>, <&usb0_hsphy1>, - <&usb0_ssphy0>, <&usb0_ssphy1>; - dr_mode = "host"; - }; - - usb-glue@65b00000 { - compatible = "socionext,uniphier-pxs3-dwc3-glue", - "simple-mfd"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x65b00000 0x400>; - - usb0_rst: reset@0 { - compatible = "socionext,uniphier-pxs3-usb3-reset"; - reg = <0x0 0x4>; - #reset-cells = <1>; - clock-names = "link"; - clocks = <&sys_clk 12>; - reset-names = "link"; - resets = <&sys_rst 12>; - }; - - usb0_vbus0: regulator@100 { - compatible = "socionext,uniphier-pxs3-usb3-regulator"; - reg = <0x100 0x10>; - clock-names = "link"; - clocks = <&sys_clk 12>; - reset-names = "link"; - resets = <&sys_rst 12>; - }; - - usb0_vbus1: regulator@110 { - compatible = "socionext,uniphier-pxs3-usb3-regulator"; - reg = <0x110 0x10>; - clock-names = "link"; - clocks = <&sys_clk 12>; - reset-names = "link"; - resets = <&sys_rst 12>; - }; - - usb0_hsphy0: hs-phy@200 { - compatible = "socionext,uniphier-pxs3-usb3-hsphy"; - reg = <0x200 0x10>; - #phy-cells = <0>; - clock-names = "link", "phy"; - clocks = <&sys_clk 12>, <&sys_clk 16>; - reset-names = "link", "phy"; - resets = <&sys_rst 12>, <&sys_rst 16>; - vbus-supply = <&usb0_vbus0>; - nvmem-cell-names = "rterm", "sel_t", "hs_i"; - nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>, - <&usb_hs_i0>; - }; - - usb0_hsphy1: hs-phy@210 { - compatible = "socionext,uniphier-pxs3-usb3-hsphy"; - reg = <0x210 0x10>; - #phy-cells = <0>; - clock-names = "link", "phy"; - clocks = <&sys_clk 12>, <&sys_clk 16>; - reset-names = "link", "phy"; - resets = <&sys_rst 12>, <&sys_rst 16>; - vbus-supply = <&usb0_vbus1>; - nvmem-cell-names = "rterm", "sel_t", "hs_i"; - nvmem-cells = <&usb_rterm1>, <&usb_sel_t1>, - <&usb_hs_i0>; - }; - - usb0_ssphy0: ss-phy@300 { - compatible = "socionext,uniphier-pxs3-usb3-ssphy"; - reg = <0x300 0x10>; - #phy-cells = <0>; - clock-names = "link", "phy"; - clocks = <&sys_clk 12>, <&sys_clk 17>; - reset-names = "link", "phy"; - resets = <&sys_rst 12>, <&sys_rst 17>; - vbus-supply = <&usb0_vbus0>; - }; - - usb0_ssphy1: ss-phy@310 { - compatible = "socionext,uniphier-pxs3-usb3-ssphy"; - reg = <0x310 0x10>; - #phy-cells = <0>; - clock-names = "link", "phy"; - clocks = <&sys_clk 12>, <&sys_clk 18>; - reset-names = "link", "phy"; - resets = <&sys_rst 12>, <&sys_rst 18>; - vbus-supply = <&usb0_vbus1>; - }; - }; - - usb1: usb@65c00000 { - compatible = "socionext,uniphier-dwc3", "snps,dwc3"; - status = "disabled"; - reg = <0x65c00000 0xcd00>; - interrupt-names = "host", "peripheral"; - interrupts = <0 137 4>, <0 138 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>; - clock-names = "ref", "bus_early", "suspend"; - clocks = <&sys_clk 13>, <&sys_clk 13>, <&sys_clk 13>; - resets = <&usb1_rst 15>; - phys = <&usb1_hsphy0>, <&usb1_hsphy1>, - <&usb1_ssphy0>; - dr_mode = "host"; - }; - - usb-glue@65d00000 { - compatible = "socionext,uniphier-pxs3-dwc3-glue", - "simple-mfd"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x65d00000 0x400>; - - usb1_rst: reset@0 { - compatible = "socionext,uniphier-pxs3-usb3-reset"; - reg = <0x0 0x4>; - #reset-cells = <1>; - clock-names = "link"; - clocks = <&sys_clk 13>; - reset-names = "link"; - resets = <&sys_rst 13>; - }; - - usb1_vbus0: regulator@100 { - compatible = "socionext,uniphier-pxs3-usb3-regulator"; - reg = <0x100 0x10>; - clock-names = "link"; - clocks = <&sys_clk 13>; - reset-names = "link"; - resets = <&sys_rst 13>; - }; - - usb1_vbus1: regulator@110 { - compatible = "socionext,uniphier-pxs3-usb3-regulator"; - reg = <0x110 0x10>; - clock-names = "link"; - clocks = <&sys_clk 13>; - reset-names = "link"; - resets = <&sys_rst 13>; - }; - - usb1_hsphy0: hs-phy@200 { - compatible = "socionext,uniphier-pxs3-usb3-hsphy"; - reg = <0x200 0x10>; - #phy-cells = <0>; - clock-names = "link", "phy", "phy-ext"; - clocks = <&sys_clk 13>, <&sys_clk 20>, - <&sys_clk 14>; - reset-names = "link", "phy"; - resets = <&sys_rst 13>, <&sys_rst 20>; - vbus-supply = <&usb1_vbus0>; - nvmem-cell-names = "rterm", "sel_t", "hs_i"; - nvmem-cells = <&usb_rterm2>, <&usb_sel_t2>, - <&usb_hs_i2>; - }; - - usb1_hsphy1: hs-phy@210 { - compatible = "socionext,uniphier-pxs3-usb3-hsphy"; - reg = <0x210 0x10>; - #phy-cells = <0>; - clock-names = "link", "phy", "phy-ext"; - clocks = <&sys_clk 13>, <&sys_clk 20>, - <&sys_clk 14>; - reset-names = "link", "phy"; - resets = <&sys_rst 13>, <&sys_rst 20>; - vbus-supply = <&usb1_vbus1>; - nvmem-cell-names = "rterm", "sel_t", "hs_i"; - nvmem-cells = <&usb_rterm3>, <&usb_sel_t3>, - <&usb_hs_i2>; - }; - - usb1_ssphy0: ss-phy@300 { - compatible = "socionext,uniphier-pxs3-usb3-ssphy"; - reg = <0x300 0x10>; - #phy-cells = <0>; - clock-names = "link", "phy", "phy-ext"; - clocks = <&sys_clk 13>, <&sys_clk 21>, - <&sys_clk 14>; - reset-names = "link", "phy"; - resets = <&sys_rst 13>, <&sys_rst 21>; - vbus-supply = <&usb1_vbus0>; - }; - }; - - pcie: pcie@66000000 { - compatible = "socionext,uniphier-pcie", "snps,dw-pcie"; - status = "disabled"; - reg-names = "dbi", "link", "config"; - reg = <0x66000000 0x1000>, <0x66010000 0x10000>, - <0x2fff0000 0x10000>; - #address-cells = <3>; - #size-cells = <2>; - clocks = <&sys_clk 24>; - resets = <&sys_rst 24>; - num-lanes = <1>; - num-viewport = <1>; - bus-range = <0x0 0xff>; - device_type = "pci"; - ranges = - /* downstream I/O */ - <0x81000000 0 0x00000000 0x2ffe0000 0 0x00010000>, - /* non-prefetchable memory */ - <0x82000000 0 0x20000000 0x20000000 0 0x0ffe0000>; - #interrupt-cells = <1>; - interrupt-names = "dma", "msi"; - interrupts = <0 224 4>, <0 225 4>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie_intc 0>, /* INTA */ - <0 0 0 2 &pcie_intc 1>, /* INTB */ - <0 0 0 3 &pcie_intc 2>, /* INTC */ - <0 0 0 4 &pcie_intc 3>; /* INTD */ - phy-names = "pcie-phy"; - phys = <&pcie_phy>; - - pcie_intc: legacy-interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - interrupt-parent = <&gic>; - interrupts = <0 226 4>; - }; - }; - - pcie_phy: phy@66038000 { - compatible = "socionext,uniphier-pxs3-pcie-phy"; - reg = <0x66038000 0x4000>; - #phy-cells = <0>; - clocks = <&sys_clk 24>; - resets = <&sys_rst 24>; - socionext,syscon = <&soc_glue>; - }; - - nand: nand@68000000 { - compatible = "socionext,uniphier-denali-nand-v5b"; - status = "disabled"; - reg-names = "nand_data", "denali_reg"; - reg = <0x68000000 0x20>, <0x68100000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 65 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nand>; - clock-names = "nand", "nand_x", "ecc"; - clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>; - reset-names = "nand", "reg"; - resets = <&sys_rst 2>, <&sys_rst 2>; - }; - }; -}; - -#include "uniphier-pinctrl.dtsi" diff --git a/sys/gnu/dts/arm64/socionext/uniphier-ref-daughter.dtsi b/sys/gnu/dts/arm64/socionext/uniphier-ref-daughter.dtsi deleted file mode 100644 index e66d999d9f5..00000000000 --- a/sys/gnu/dts/arm64/socionext/uniphier-ref-daughter.dtsi +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/sys/gnu/dts/arm64/socionext/uniphier-support-card.dtsi b/sys/gnu/dts/arm64/socionext/uniphier-support-card.dtsi deleted file mode 100644 index 28c5b4ed1d9..00000000000 --- a/sys/gnu/dts/arm64/socionext/uniphier-support-card.dtsi +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/sys/gnu/dts/arm64/sprd/sc2731.dtsi b/sys/gnu/dts/arm64/sprd/sc2731.dtsi deleted file mode 100644 index e15409f55f4..00000000000 --- a/sys/gnu/dts/arm64/sprd/sc2731.dtsi +++ /dev/null @@ -1,258 +0,0 @@ -/* - * Spreadtrum SC2731 PMIC dts file - * - * Copyright (C) 2018, Spreadtrum Communications Inc. - * - * SPDX-License-Identifier: (GPL-2.0+ OR MIT) - */ - -&adi_bus { - sc2731_pmic: pmic@0 { - compatible = "sprd,sc2731"; - reg = <0>; - spi-max-frequency = <26000000>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - - charger@0 { - compatible = "sprd,sc2731-charger"; - reg = <0x0>; - monitored-battery = <&bat>; - }; - - led-controller@200 { - compatible = "sprd,sc2731-bltc"; - reg = <0x200>; - #address-cells = <1>; - #size-cells = <0>; - - led@0 { - label = "red"; - reg = <0x0>; - }; - - led@1 { - label = "green"; - reg = <0x1>; - }; - - led@2 { - label = "blue"; - reg = <0x2>; - }; - }; - - rtc@280 { - compatible = "sprd,sc2731-rtc"; - reg = <0x280>; - interrupt-parent = <&sc2731_pmic>; - interrupts = <2>; - }; - - pmic_eic: gpio@300 { - compatible = "sprd,sc2731-eic"; - reg = <0x300>; - interrupt-parent = <&sc2731_pmic>; - interrupts = <5>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - efuse@380 { - compatible = "sprd,sc2731-efuse"; - reg = <0x380>; - #address-cells = <1>; - #size-cells = <1>; - hwlocks = <&hwlock 12>; - - fgu_calib: calib@6 { - reg = <0x6 0x2>; - bits = <0 9>; - }; - - adc_big_scale: calib@24 { - reg = <0x24 0x2>; - }; - - adc_small_scale: calib@26 { - reg = <0x26 0x2>; - }; - }; - - pmic_adc: adc@480 { - compatible = "sprd,sc2731-adc"; - reg = <0x480>; - interrupt-parent = <&sc2731_pmic>; - interrupts = <0>; - #io-channel-cells = <1>; - hwlocks = <&hwlock 4>; - nvmem-cell-names = "big_scale_calib", "small_scale_calib"; - nvmem-cells = <&adc_big_scale>, <&adc_small_scale>; - }; - - fgu@a00 { - compatible = "sprd,sc2731-fgu"; - reg = <0xa00>; - bat-detect-gpio = <&pmic_eic 9 GPIO_ACTIVE_HIGH>; - io-channels = <&pmic_adc 3>, <&pmic_adc 6>; - io-channel-names = "bat-temp", "charge-vol"; - monitored-battery = <&bat>; - nvmem-cell-names = "fgu_calib"; - nvmem-cells = <&fgu_calib>; - interrupt-parent = <&sc2731_pmic>; - interrupts = <4>; - }; - - vibrator@ec8 { - compatible = "sprd,sc2731-vibrator"; - reg = <0xec8>; - }; - - regulators { - compatible = "sprd,sc2731-regulator"; - - vddarm0: BUCK_CPU0 { - regulator-name = "vddarm0"; - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1996875>; - regulator-ramp-delay = <25000>; - regulator-always-on; - }; - - vddarm1: BUCK_CPU1 { - regulator-name = "vddarm1"; - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1996875>; - regulator-ramp-delay = <25000>; - regulator-always-on; - }; - - dcdcrf: BUCK_RF { - regulator-name = "dcdcrf"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <2196875>; - regulator-ramp-delay = <25000>; - regulator-enable-ramp-delay = <100>; - regulator-always-on; - }; - - vddcama0: LDO_CAMA0 { - regulator-name = "vddcama0"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3750000>; - regulator-enable-ramp-delay = <100>; - }; - - vddcama1: LDO_CAMA1 { - regulator-name = "vddcama1"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3750000>; - regulator-enable-ramp-delay = <100>; - regulator-ramp-delay = <25000>; - }; - - vddcammot: LDO_CAMMOT { - regulator-name = "vddcammot"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3750000>; - regulator-enable-ramp-delay = <100>; - regulator-ramp-delay = <25000>; - }; - - vddvldo: LDO_VLDO { - regulator-name = "vddvldo"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3750000>; - regulator-enable-ramp-delay = <100>; - regulator-ramp-delay = <25000>; - }; - - vddemmccore: LDO_EMMCCORE { - regulator-name = "vddemmccore"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3750000>; - regulator-enable-ramp-delay = <100>; - regulator-ramp-delay = <25000>; - regulator-boot-on; - }; - - vddsdcore: LDO_SDCORE { - regulator-name = "vddsdcore"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3750000>; - regulator-enable-ramp-delay = <100>; - regulator-ramp-delay = <25000>; - }; - - vddsdio: LDO_SDIO { - regulator-name = "vddsdio"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3750000>; - regulator-enable-ramp-delay = <100>; - regulator-ramp-delay = <25000>; - }; - - vddwifipa: LDO_WIFIPA { - regulator-name = "vddwifipa"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3750000>; - regulator-enable-ramp-delay = <100>; - regulator-ramp-delay = <25000>; - }; - - vddusb33: LDO_USB33 { - regulator-name = "vddusb33"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3750000>; - regulator-enable-ramp-delay = <100>; - regulator-ramp-delay = <25000>; - }; - - vddcamd0: LDO_CAMD0 { - regulator-name = "vddcamd0"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1793750>; - regulator-enable-ramp-delay = <100>; - regulator-ramp-delay = <25000>; - }; - - vddcamd1: LDO_CAMD1 { - regulator-name = "vddcamd1"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1793750>; - regulator-enable-ramp-delay = <100>; - regulator-ramp-delay = <25000>; - }; - - vddcon: LDO_CON { - regulator-name = "vddcon"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1793750>; - regulator-enable-ramp-delay = <100>; - regulator-ramp-delay = <25000>; - }; - - vddcamio: LDO_CAMIO { - regulator-name = "vddcamio"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1793750>; - regulator-enable-ramp-delay = <100>; - regulator-ramp-delay = <25000>; - }; - - vddsram: LDO_SRAM { - regulator-name = "vddsram"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1793750>; - regulator-enable-ramp-delay = <100>; - regulator-ramp-delay = <25000>; - regulator-always-on; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/sprd/sc9836-openphone.dts b/sys/gnu/dts/arm64/sprd/sc9836-openphone.dts deleted file mode 100644 index e5657c35cd1..00000000000 --- a/sys/gnu/dts/arm64/sprd/sc9836-openphone.dts +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Spreadtrum SC9836 openphone board DTS file - * - * Copyright (C) 2014, Spreadtrum Communications Inc. - * - * This file is licensed under a dual GPLv2 or X11 license. - */ - -/dts-v1/; - -#include "sc9836.dtsi" - -/ { - model = "Spreadtrum SC9836 Openphone Board"; - - compatible = "sprd,sc9836-openphone", "sprd,sc9836"; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0 0x80000000 0 0x20000000>; - }; - - chosen { - stdout-path = "serial1:115200n8"; - }; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/sprd/sc9836.dtsi b/sys/gnu/dts/arm64/sprd/sc9836.dtsi deleted file mode 100644 index 231436be0e3..00000000000 --- a/sys/gnu/dts/arm64/sprd/sc9836.dtsi +++ /dev/null @@ -1,224 +0,0 @@ -/* - * Spreadtrum SC9836 SoC DTS file - * - * Copyright (C) 2014, Spreadtrum Communications Inc. - * - * This file is licensed under a dual GPLv2 or X11 license. - */ - -#include "sharkl64.dtsi" -#include - -/ { - compatible = "sprd,sc9836"; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x0>; - enable-method = "psci"; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x1>; - enable-method = "psci"; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x2>; - enable-method = "psci"; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x3>; - enable-method = "psci"; - }; - }; - - etf@10003000 { - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0 0x10003000 0 0x1000>; - clocks = <&clk26mhz>; - clock-names = "apb_pclk"; - in-ports { - port { - etf_in: endpoint { - remote-endpoint = <&funnel_out_port0>; - }; - }; - }; - }; - - funnel@10001000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0x10001000 0 0x1000>; - clocks = <&clk26mhz>; - clock-names = "apb_pclk"; - - out-ports { - port { - funnel_out_port0: endpoint { - remote-endpoint = <&etf_in>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - funnel_in_port0: endpoint { - remote-endpoint = <&etm0_out>; - }; - }; - - port@1 { - reg = <1>; - funnel_in_port1: endpoint { - remote-endpoint = <&etm1_out>; - }; - }; - - port@2 { - reg = <2>; - funnel_in_port2: endpoint { - remote-endpoint = <&etm2_out>; - }; - }; - - port@3 { - reg = <3>; - funnel_in_port3: endpoint { - remote-endpoint = <&etm3_out>; - }; - }; - - port@4 { - reg = <4>; - funnel_in_port4: endpoint { - remote-endpoint = <&stm_out>; - }; - }; - /* Other input ports aren't connected to anyone */ - }; - }; - - etm@10440000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x10440000 0 0x1000>; - - cpu = <&cpu0>; - clocks = <&clk26mhz>; - clock-names = "apb_pclk"; - out-ports { - port { - etm0_out: endpoint { - remote-endpoint = <&funnel_in_port0>; - }; - }; - }; - }; - - etm@10540000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x10540000 0 0x1000>; - - cpu = <&cpu1>; - clocks = <&clk26mhz>; - clock-names = "apb_pclk"; - out-ports { - port { - etm1_out: endpoint { - remote-endpoint = <&funnel_in_port1>; - }; - }; - }; - }; - - etm@10640000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x10640000 0 0x1000>; - - cpu = <&cpu2>; - clocks = <&clk26mhz>; - clock-names = "apb_pclk"; - out-ports { - port { - etm2_out: endpoint { - remote-endpoint = <&funnel_in_port2>; - }; - }; - }; - }; - - etm@10740000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x10740000 0 0x1000>; - - cpu = <&cpu3>; - clocks = <&clk26mhz>; - clock-names = "apb_pclk"; - out-ports { - port { - etm3_out: endpoint { - remote-endpoint = <&funnel_in_port3>; - }; - }; - }; - }; - - stm@10006000 { - compatible = "arm,coresight-stm", "arm,primecell"; - reg = <0 0x10006000 0 0x1000>, - <0 0x01000000 0 0x180000>; - reg-names = "stm-base", "stm-stimulus-base"; - clocks = <&clk26mhz>; - clock-names = "apb_pclk"; - out-ports { - port { - stm_out: endpoint { - remote-endpoint = <&funnel_in_port4>; - }; - }; - }; - }; - - gic: interrupt-controller@12001000 { - compatible = "arm,gic-400"; - reg = <0 0x12001000 0 0x1000>, - <0 0x12002000 0 0x2000>, - <0 0x12004000 0 0x2000>, - <0 0x12006000 0 0x2000>; - #interrupt-cells = <3>; - interrupt-controller; - interrupts = ; - }; - - psci { - compatible = "arm,psci"; - method = "smc"; - cpu_on = <0xc4000003>; - cpu_off = <0x84000002>; - cpu_suspend = <0xc4000001>; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; -}; diff --git a/sys/gnu/dts/arm64/sprd/sc9860.dtsi b/sys/gnu/dts/arm64/sprd/sc9860.dtsi deleted file mode 100644 index e27eb3ed1d4..00000000000 --- a/sys/gnu/dts/arm64/sprd/sc9860.dtsi +++ /dev/null @@ -1,716 +0,0 @@ -/* - * Spreadtrum SC9860 SoC - * - * Copyright (C) 2016, Spreadtrum Communications Inc. - * - * SPDX-License-Identifier: (GPL-2.0+ OR MIT) - */ - -#include -#include -#include -#include "whale2.dtsi" - -/ { - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu-map { - cluster0 { - core0 { - cpu = <&CPU0>; - }; - core1 { - cpu = <&CPU1>; - }; - core2 { - cpu = <&CPU2>; - }; - core3 { - cpu = <&CPU3>; - }; - }; - - cluster1 { - core0 { - cpu = <&CPU4>; - }; - core1 { - cpu = <&CPU5>; - }; - core2 { - cpu = <&CPU6>; - }; - core3 { - cpu = <&CPU7>; - }; - }; - }; - - CPU0: cpu@530000 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x530000>; - enable-method = "psci"; - cpu-idle-states = <&CORE_PD &CLUSTER_PD>; - }; - - CPU1: cpu@530001 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x530001>; - enable-method = "psci"; - cpu-idle-states = <&CORE_PD &CLUSTER_PD>; - }; - - CPU2: cpu@530002 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x530002>; - enable-method = "psci"; - cpu-idle-states = <&CORE_PD &CLUSTER_PD>; - }; - - CPU3: cpu@530003 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x530003>; - enable-method = "psci"; - cpu-idle-states = <&CORE_PD &CLUSTER_PD>; - }; - - CPU4: cpu@530100 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x530100>; - enable-method = "psci"; - cpu-idle-states = <&CORE_PD &CLUSTER_PD>; - }; - - CPU5: cpu@530101 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x530101>; - enable-method = "psci"; - cpu-idle-states = <&CORE_PD &CLUSTER_PD>; - }; - - CPU6: cpu@530102 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x530102>; - enable-method = "psci"; - cpu-idle-states = <&CORE_PD &CLUSTER_PD>; - }; - - CPU7: cpu@530103 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x530103>; - enable-method = "psci"; - cpu-idle-states = <&CORE_PD &CLUSTER_PD>; - }; - }; - - idle-states{ - entry-method = "psci"; - - CORE_PD: core_pd { - compatible = "arm,idle-state"; - entry-latency-us = <1000>; - exit-latency-us = <700>; - min-residency-us = <2500>; - local-timer-stop; - arm,psci-suspend-param = <0x00010002>; - }; - - CLUSTER_PD: cluster_pd { - compatible = "arm,idle-state"; - entry-latency-us = <1000>; - exit-latency-us = <1000>; - min-residency-us = <3000>; - local-timer-stop; - arm,psci-suspend-param = <0x01010003>; - }; - }; - - gic: interrupt-controller@12001000 { - compatible = "arm,gic-400"; - reg = <0 0x12001000 0 0x1000>, - <0 0x12002000 0 0x2000>, - <0 0x12004000 0 0x2000>, - <0 0x12006000 0 0x2000>; - #interrupt-cells = <3>; - interrupt-controller; - interrupts = ; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - pmu { - compatible = "arm,cortex-a53-pmu", "arm,armv8-pmuv3"; - interrupts = , - , - , - , - , - , - , - ; - interrupt-affinity = <&CPU0>, - <&CPU1>, - <&CPU2>, - <&CPU3>, - <&CPU4>, - <&CPU5>, - <&CPU6>, - <&CPU7>; - }; - - soc { - pmu_gate: pmu-gate { - compatible = "sprd,sc9860-pmu-gate"; - sprd,syscon = <&pmu_regs>; /* 0x402b0000 */ - clocks = <&ext_26m>; - #clock-cells = <1>; - }; - - pll: pll { - compatible = "sprd,sc9860-pll"; - sprd,syscon = <&ana_regs>; /* 0x40400000 */ - clocks = <&pmu_gate 0>; - #clock-cells = <1>; - }; - - ap_clk: clock-controller@20000000 { - compatible = "sprd,sc9860-ap-clk"; - reg = <0 0x20000000 0 0x400>; - clocks = <&ext_26m>, <&pll 0>, - <&pmu_gate 0>; - #clock-cells = <1>; - }; - - aon_prediv: aon-prediv { - compatible = "sprd,sc9860-aon-prediv"; - reg = <0 0x402d0000 0 0x400>; - clocks = <&ext_26m>, <&pll 0>, - <&pmu_gate 0>; - #clock-cells = <1>; - }; - - apahb_gate: apahb-gate { - compatible = "sprd,sc9860-apahb-gate"; - sprd,syscon = <&ap_ahb_regs>; /* 0x20210000 */ - clocks = <&aon_prediv 0>; - #clock-cells = <1>; - }; - - aon_gate: aon-gate { - compatible = "sprd,sc9860-aon-gate"; - sprd,syscon = <&aon_regs>; /* 0x402e0000 */ - clocks = <&aon_prediv 0>; - #clock-cells = <1>; - }; - - aonsecure_clk: clock-controller@40880000 { - compatible = "sprd,sc9860-aonsecure-clk"; - reg = <0 0x40880000 0 0x400>; - clocks = <&ext_26m>, <&pll 0>; - #clock-cells = <1>; - }; - - agcp_gate: agcp-gate { - compatible = "sprd,sc9860-agcp-gate"; - sprd,syscon = <&agcp_regs>; /* 0x415e0000 */ - clocks = <&aon_prediv 0>; - #clock-cells = <1>; - }; - - gpu_clk: clock-controller@60200000 { - compatible = "sprd,sc9860-gpu-clk"; - reg = <0 0x60200000 0 0x400>; - clocks = <&pll 0>; - #clock-cells = <1>; - }; - - vsp_clk: clock-controller@61000000 { - compatible = "sprd,sc9860-vsp-clk"; - reg = <0 0x61000000 0 0x400>; - clocks = <&ext_26m>, <&pll 0>; - #clock-cells = <1>; - }; - - vsp_gate: vsp-gate { - compatible = "sprd,sc9860-vsp-gate"; - sprd,syscon = <&vsp_regs>; /* 0x61100000 */ - clocks = <&vsp_clk 0>; - #clock-cells = <1>; - }; - - cam_clk: clock-controller@62000000 { - compatible = "sprd,sc9860-cam-clk"; - reg = <0 0x62000000 0 0x4000>; - clocks = <&ext_26m>, <&pll 0>; - #clock-cells = <1>; - }; - - cam_gate: cam-gate { - compatible = "sprd,sc9860-cam-gate"; - sprd,syscon = <&cam_regs>; /* 0x62100000 */ - clocks = <&cam_clk 0>; - #clock-cells = <1>; - }; - - disp_clk: clock-controller@63000000 { - compatible = "sprd,sc9860-disp-clk"; - reg = <0 0x63000000 0 0x400>; - clocks = <&ext_26m>, <&pll 0>; - #clock-cells = <1>; - }; - - disp_gate: disp-gate { - compatible = "sprd,sc9860-disp-gate"; - sprd,syscon = <&disp_regs>; /* 0x63100000 */ - clocks = <&disp_clk 0>; - #clock-cells = <1>; - }; - - apapb_gate: apapb-gate { - compatible = "sprd,sc9860-apapb-gate"; - sprd,syscon = <&ap_apb_regs>; /* 0x70b00000 */ - clocks = <&ap_clk 0>; - #clock-cells = <1>; - }; - - funnel@10001000 { /* SoC Funnel */ - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0x10001000 0 0x1000>; - clocks = <&ext_26m>; - clock-names = "apb_pclk"; - out-ports { - port { - soc_funnel_out_port: endpoint { - remote-endpoint = <&etb_in>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - soc_funnel_in_port0: endpoint { - remote-endpoint = - <&main_funnel_out_port>; - }; - }; - - port@4 { - reg = <4>; - soc_funnel_in_port1: endpoint { - remote-endpoint = - <&stm_out_port>; - }; - }; - }; - }; - - etb@10003000 { - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0 0x10003000 0 0x1000>; - clocks = <&ext_26m>; - clock-names = "apb_pclk"; - out-ports { - port { - etb_in: endpoint { - remote-endpoint = - <&soc_funnel_out_port>; - }; - }; - }; - }; - - stm@10006000 { - compatible = "arm,coresight-stm", "arm,primecell"; - reg = <0 0x10006000 0 0x1000>, - <0 0x01000000 0 0x180000>; - reg-names = "stm-base", "stm-stimulus-base"; - clocks = <&ext_26m>; - clock-names = "apb_pclk"; - out-ports { - port { - stm_out_port: endpoint { - remote-endpoint = - <&soc_funnel_in_port1>; - }; - }; - }; - }; - - funnel@11001000 { /* Cluster0 Funnel */ - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0x11001000 0 0x1000>; - clocks = <&ext_26m>; - clock-names = "apb_pclk"; - out-ports { - port { - cluster0_funnel_out_port: endpoint { - remote-endpoint = - <&cluster0_etf_in>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - cluster0_funnel_in_port0: endpoint { - remote-endpoint = <&etm0_out>; - }; - }; - - port@1 { - reg = <1>; - cluster0_funnel_in_port1: endpoint { - remote-endpoint = <&etm1_out>; - }; - }; - - port@2 { - reg = <2>; - cluster0_funnel_in_port2: endpoint { - remote-endpoint = <&etm2_out>; - }; - }; - - port@4 { - reg = <4>; - cluster0_funnel_in_port3: endpoint { - remote-endpoint = <&etm3_out>; - }; - }; - }; - }; - - funnel@11002000 { /* Cluster1 Funnel */ - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0x11002000 0 0x1000>; - clocks = <&ext_26m>; - clock-names = "apb_pclk"; - out-ports { - port { - cluster1_funnel_out_port: endpoint { - remote-endpoint = - <&cluster1_etf_in>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - cluster1_funnel_in_port0: endpoint { - remote-endpoint = <&etm4_out>; - }; - }; - - port@1 { - reg = <1>; - cluster1_funnel_in_port1: endpoint { - remote-endpoint = <&etm5_out>; - }; - }; - - port@2 { - reg = <2>; - cluster1_funnel_in_port2: endpoint { - remote-endpoint = <&etm6_out>; - }; - }; - - port@3 { - reg = <3>; - cluster1_funnel_in_port3: endpoint { - remote-endpoint = <&etm7_out>; - }; - }; - }; - }; - - etf@11003000 { /* ETF on Cluster0 */ - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0 0x11003000 0 0x1000>; - clocks = <&ext_26m>; - clock-names = "apb_pclk"; - - out-ports { - port { - cluster0_etf_out: endpoint { - remote-endpoint = - <&main_funnel_in_port0>; - }; - }; - }; - - in-ports { - port { - cluster0_etf_in: endpoint { - remote-endpoint = - <&cluster0_funnel_out_port>; - }; - }; - }; - }; - - etf@11004000 { /* ETF on Cluster1 */ - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0 0x11004000 0 0x1000>; - clocks = <&ext_26m>; - clock-names = "apb_pclk"; - - out-ports { - port { - cluster1_etf_out: endpoint { - remote-endpoint = - <&main_funnel_in_port1>; - }; - }; - }; - - in-ports { - port { - cluster1_etf_in: endpoint { - remote-endpoint = - <&cluster1_funnel_out_port>; - }; - }; - }; - }; - - funnel@11005000 { /* Main Funnel */ - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0x11005000 0 0x1000>; - clocks = <&ext_26m>; - clock-names = "apb_pclk"; - - out-ports { - port { - main_funnel_out_port: endpoint { - remote-endpoint = - <&soc_funnel_in_port0>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - main_funnel_in_port0: endpoint { - remote-endpoint = - <&cluster0_etf_out>; - }; - }; - - port@1 { - reg = <1>; - main_funnel_in_port1: endpoint { - remote-endpoint = - <&cluster1_etf_out>; - }; - }; - }; - }; - - etm@11440000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x11440000 0 0x1000>; - cpu = <&CPU0>; - clocks = <&ext_26m>; - clock-names = "apb_pclk"; - - out-ports { - port { - etm0_out: endpoint { - remote-endpoint = - <&cluster0_funnel_in_port0>; - }; - }; - }; - }; - - etm@11540000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x11540000 0 0x1000>; - cpu = <&CPU1>; - clocks = <&ext_26m>; - clock-names = "apb_pclk"; - - out-ports { - port { - etm1_out: endpoint { - remote-endpoint = - <&cluster0_funnel_in_port1>; - }; - }; - }; - }; - - etm@11640000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x11640000 0 0x1000>; - cpu = <&CPU2>; - clocks = <&ext_26m>; - clock-names = "apb_pclk"; - - out-ports { - port { - etm2_out: endpoint { - remote-endpoint = - <&cluster0_funnel_in_port2>; - }; - }; - }; - }; - - etm@11740000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x11740000 0 0x1000>; - cpu = <&CPU3>; - clocks = <&ext_26m>; - clock-names = "apb_pclk"; - - out-ports { - port { - etm3_out: endpoint { - remote-endpoint = - <&cluster0_funnel_in_port3>; - }; - }; - }; - }; - - etm@11840000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x11840000 0 0x1000>; - cpu = <&CPU4>; - clocks = <&ext_26m>; - clock-names = "apb_pclk"; - - out-ports { - port { - etm4_out: endpoint { - remote-endpoint = - <&cluster1_funnel_in_port0>; - }; - }; - }; - }; - - etm@11940000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x11940000 0 0x1000>; - cpu = <&CPU5>; - clocks = <&ext_26m>; - clock-names = "apb_pclk"; - - out-ports { - port { - etm5_out: endpoint { - remote-endpoint = - <&cluster1_funnel_in_port1>; - }; - }; - }; - }; - - etm@11a40000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x11a40000 0 0x1000>; - cpu = <&CPU6>; - clocks = <&ext_26m>; - clock-names = "apb_pclk"; - - out-ports { - port { - etm6_out: endpoint { - remote-endpoint = - <&cluster1_funnel_in_port2>; - }; - }; - }; - }; - - etm@11b40000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x11b40000 0 0x1000>; - cpu = <&CPU7>; - clocks = <&ext_26m>; - clock-names = "apb_pclk"; - - out-ports { - port { - etm7_out: endpoint { - remote-endpoint = - <&cluster1_funnel_in_port3>; - }; - }; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - key-volumedown { - label = "Volume Down Key"; - linux,code = ; - gpios = <&eic_debounce 2 GPIO_ACTIVE_LOW>; - debounce-interval = <2>; - wakeup-source; - }; - - key-volumeup { - label = "Volume Up Key"; - linux,code = ; - gpios = <&pmic_eic 10 GPIO_ACTIVE_HIGH>; - debounce-interval = <2>; - wakeup-source; - }; - - key-power { - label = "Power Key"; - linux,code = ; - gpios = <&pmic_eic 1 GPIO_ACTIVE_HIGH>; - debounce-interval = <2>; - wakeup-source; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/sprd/sc9863a.dtsi b/sys/gnu/dts/arm64/sprd/sc9863a.dtsi deleted file mode 100644 index 2c590ca1d07..00000000000 --- a/sys/gnu/dts/arm64/sprd/sc9863a.dtsi +++ /dev/null @@ -1,523 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Unisoc SC9863A SoC DTS file - * - * Copyright (C) 2019, Unisoc Inc. - */ - -#include -#include "sharkl3.dtsi" - -/ { - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu-map { - cluster0 { - core0 { - cpu = <&CPU0>; - }; - core1 { - cpu = <&CPU1>; - }; - core2 { - cpu = <&CPU2>; - }; - core3 { - cpu = <&CPU3>; - }; - core4 { - cpu = <&CPU4>; - }; - core5 { - cpu = <&CPU5>; - }; - core6 { - cpu = <&CPU6>; - }; - core7 { - cpu = <&CPU7>; - }; - }; - }; - - CPU0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x0 0x0>; - enable-method = "psci"; - cpu-idle-states = <&CORE_PD>; - }; - - CPU1: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x0 0x100>; - enable-method = "psci"; - cpu-idle-states = <&CORE_PD>; - }; - - CPU2: cpu@200 { - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x0 0x200>; - enable-method = "psci"; - cpu-idle-states = <&CORE_PD>; - }; - - CPU3: cpu@300 { - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x0 0x300>; - enable-method = "psci"; - cpu-idle-states = <&CORE_PD>; - }; - - CPU4: cpu@400 { - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x0 0x400>; - enable-method = "psci"; - cpu-idle-states = <&CORE_PD>; - }; - - CPU5: cpu@500 { - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x0 0x500>; - enable-method = "psci"; - cpu-idle-states = <&CORE_PD>; - }; - - CPU6: cpu@600 { - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x0 0x600>; - enable-method = "psci"; - cpu-idle-states = <&CORE_PD>; - }; - - CPU7: cpu@700 { - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x0 0x700>; - enable-method = "psci"; - cpu-idle-states = <&CORE_PD>; - }; - }; - - idle-states { - entry-method = "psci"; - CORE_PD: core-pd { - compatible = "arm,idle-state"; - entry-latency-us = <4000>; - exit-latency-us = <4000>; - min-residency-us = <10000>; - local-timer-stop; - arm,psci-suspend-param = <0x00010000>; - }; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , /* Physical Secure PPI */ - , /* Physical Non-Secure PPI */ - , /* Virtual PPI */ - ; /* Hipervisor PPI */ - }; - - pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = , - , - , - , - , - , - , - ; - }; - - soc { - gic: interrupt-controller@14000000 { - compatible = "arm,gic-v3"; - #interrupt-cells = <3>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - redistributor-stride = <0x0 0x20000>; /* 128KB stride */ - #redistributor-regions = <1>; - interrupt-controller; - reg = <0x0 0x14000000 0 0x20000>, /* GICD */ - <0x0 0x14040000 0 0x100000>; /* GICR */ - interrupts = ; - }; - - funnel@10001000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0x10001000 0 0x1000>; - clocks = <&ext_26m>; - clock-names = "apb_pclk"; - - out-ports { - port { - funnel_soc_out_port: endpoint { - remote-endpoint = <&etb_in>; - }; - }; - }; - - in-ports { - port { - funnel_soc_in_port: endpoint { - remote-endpoint = - <&funnel_ca55_out_port>; - }; - }; - }; - }; - - etb@10003000 { - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0 0x10003000 0 0x1000>; - clocks = <&ext_26m>; - clock-names = "apb_pclk"; - - in-ports { - port { - etb_in: endpoint { - remote-endpoint = - <&funnel_soc_out_port>; - }; - }; - }; - }; - - funnel@12001000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0x12001000 0 0x1000>; - clocks = <&ext_26m>; - clock-names = "apb_pclk"; - - out-ports { - port { - funnel_little_out_port: endpoint { - remote-endpoint = - <&etf_little_in>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - funnel_little_in_port0: endpoint { - remote-endpoint = <&etm0_out>; - }; - }; - - port@1 { - reg = <1>; - funnel_little_in_port1: endpoint { - remote-endpoint = <&etm1_out>; - }; - }; - - port@2 { - reg = <2>; - funnel_little_in_port2: endpoint { - remote-endpoint = <&etm2_out>; - }; - }; - - port@3 { - reg = <3>; - funnel_little_in_port3: endpoint { - remote-endpoint = <&etm3_out>; - }; - }; - }; - }; - - etf@12002000 { - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0 0x12002000 0 0x1000>; - clocks = <&ext_26m>; - clock-names = "apb_pclk"; - - out-ports { - port { - etf_little_out: endpoint { - remote-endpoint = - <&funnel_ca55_in_port0>; - }; - }; - }; - - in-port { - port { - etf_little_in: endpoint { - remote-endpoint = - <&funnel_little_out_port>; - }; - }; - }; - }; - - etf@12003000 { - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0 0x12003000 0 0x1000>; - clocks = <&ext_26m>; - clock-names = "apb_pclk"; - - out-ports { - port { - etf_big_out: endpoint { - remote-endpoint = - <&funnel_ca55_in_port1>; - }; - }; - }; - - in-ports { - port { - etf_big_in: endpoint { - remote-endpoint = - <&funnel_big_out_port>; - }; - }; - }; - }; - - funnel@12004000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0x12004000 0 0x1000>; - clocks = <&ext_26m>; - clock-names = "apb_pclk"; - - out-ports { - port { - funnel_ca55_out_port: endpoint { - remote-endpoint = - <&funnel_soc_in_port>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - funnel_ca55_in_port0: endpoint { - remote-endpoint = - <&etf_little_out>; - }; - }; - - port@1 { - reg = <1>; - funnel_ca55_in_port1: endpoint { - remote-endpoint = - <&etf_big_out>; - }; - }; - }; - }; - - funnel@12005000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0x12005000 0 0x1000>; - clocks = <&ext_26m>; - clock-names = "apb_pclk"; - - out-ports { - port { - funnel_big_out_port: endpoint { - remote-endpoint = - <&etf_big_in>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - funnel_big_in_port0: endpoint { - remote-endpoint = <&etm4_out>; - }; - }; - - port@1 { - reg = <1>; - funnel_big_in_port1: endpoint { - remote-endpoint = <&etm5_out>; - }; - }; - - port@2 { - reg = <2>; - funnel_big_in_port2: endpoint { - remote-endpoint = <&etm6_out>; - }; - }; - - port@3 { - reg = <3>; - funnel_big_in_port3: endpoint { - remote-endpoint = <&etm7_out>; - }; - }; - }; - }; - - etm@13040000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x13040000 0 0x1000>; - cpu = <&CPU0>; - clocks = <&ext_26m>; - clock-names = "apb_pclk"; - - out-ports { - port { - etm0_out: endpoint { - remote-endpoint = - <&funnel_little_in_port0>; - }; - }; - }; - }; - - etm@13140000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x13140000 0 0x1000>; - cpu = <&CPU1>; - clocks = <&ext_26m>; - clock-names = "apb_pclk"; - - out-ports { - port { - etm1_out: endpoint { - remote-endpoint = - <&funnel_little_in_port1>; - }; - }; - }; - }; - - etm@13240000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x13240000 0 0x1000>; - cpu = <&CPU2>; - clocks = <&ext_26m>; - clock-names = "apb_pclk"; - - out-ports { - port { - etm2_out: endpoint { - remote-endpoint = - <&funnel_little_in_port2>; - }; - }; - }; - }; - - etm@13340000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x13340000 0 0x1000>; - cpu = <&CPU3>; - clocks = <&ext_26m>; - clock-names = "apb_pclk"; - - out-ports { - port { - etm3_out: endpoint { - remote-endpoint = - <&funnel_little_in_port3>; - }; - }; - }; - }; - - etm@13440000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x13440000 0 0x1000>; - cpu = <&CPU4>; - clocks = <&ext_26m>; - clock-names = "apb_pclk"; - - out-ports { - port { - etm4_out: endpoint { - remote-endpoint = - <&funnel_big_in_port0>; - }; - }; - }; - }; - - etm@13540000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x13540000 0 0x1000>; - cpu = <&CPU5>; - clocks = <&ext_26m>; - clock-names = "apb_pclk"; - - out-ports { - port { - etm5_out: endpoint { - remote-endpoint = - <&funnel_big_in_port1>; - }; - }; - }; - }; - - etm@13640000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x13640000 0 0x1000>; - cpu = <&CPU6>; - clocks = <&ext_26m>; - clock-names = "apb_pclk"; - - out-ports { - port { - etm6_out: endpoint { - remote-endpoint = - <&funnel_big_in_port2>; - }; - }; - }; - }; - - etm@13740000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x13740000 0 0x1000>; - cpu = <&CPU7>; - clocks = <&ext_26m>; - clock-names = "apb_pclk"; - - out-ports { - port { - etm7_out: endpoint { - remote-endpoint = - <&funnel_big_in_port3>; - }; - }; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/sprd/sharkl3.dtsi b/sys/gnu/dts/arm64/sprd/sharkl3.dtsi deleted file mode 100644 index 0222128b10f..00000000000 --- a/sys/gnu/dts/arm64/sprd/sharkl3.dtsi +++ /dev/null @@ -1,78 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Unisoc Sharkl3 platform DTS file - * - * Copyright (C) 2019, Unisoc Inc. - */ - -/ { - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - soc: soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - apb@70000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x0 0x70000000 0x10000000>; - - uart0: serial@0 { - compatible = "sprd,sc9863a-uart", - "sprd,sc9836-uart"; - reg = <0x0 0x100>; - interrupts = ; - clocks = <&ext_26m>; - status = "disabled"; - }; - - uart1: serial@100000 { - compatible = "sprd,sc9863a-uart", - "sprd,sc9836-uart"; - reg = <0x100000 0x100>; - interrupts = ; - clocks = <&ext_26m>; - status = "disabled"; - }; - - uart2: serial@200000 { - compatible = "sprd,sc9863a-uart", - "sprd,sc9836-uart"; - reg = <0x200000 0x100>; - interrupts = ; - clocks = <&ext_26m>; - status = "disabled"; - }; - - uart3: serial@300000 { - compatible = "sprd,sc9863a-uart", - "sprd,sc9836-uart"; - reg = <0x300000 0x100>; - interrupts = ; - clocks = <&ext_26m>; - status = "disabled"; - }; - - uart4: serial@400000 { - compatible = "sprd,sc9863a-uart", - "sprd,sc9836-uart"; - reg = <0x400000 0x100>; - interrupts = ; - clocks = <&ext_26m>; - status = "disabled"; - }; - }; - }; - - ext_26m: ext-26m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <26000000>; - clock-output-names = "ext-26m"; - }; -}; diff --git a/sys/gnu/dts/arm64/sprd/sharkl64.dtsi b/sys/gnu/dts/arm64/sprd/sharkl64.dtsi deleted file mode 100644 index 69f64e7fce7..00000000000 --- a/sys/gnu/dts/arm64/sprd/sharkl64.dtsi +++ /dev/null @@ -1,65 +0,0 @@ -/* - * Spreadtrum Sharkl64 platform DTS file - * - * Copyright (C) 2014, Spreadtrum Communications Inc. - * - * This file is licensed under a dual GPLv2 or X11 license. - */ - -/ { - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - ap-apb { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - uart0: serial@70000000 { - compatible = "sprd,sc9836-uart"; - reg = <0 0x70000000 0 0x100>; - interrupts = <0 2 0xf04>; - clocks = <&clk26mhz>; - status = "disabled"; - }; - - uart1: serial@70100000 { - compatible = "sprd,sc9836-uart"; - reg = <0 0x70100000 0 0x100>; - interrupts = <0 3 0xf04>; - clocks = <&clk26mhz>; - status = "disabled"; - }; - - uart2: serial@70200000 { - compatible = "sprd,sc9836-uart"; - reg = <0 0x70200000 0 0x100>; - interrupts = <0 4 0xf04>; - clocks = <&clk26mhz>; - status = "disabled"; - }; - - uart3: serial@70300000 { - compatible = "sprd,sc9836-uart"; - reg = <0 0x70300000 0 0x100>; - interrupts = <0 5 0xf04>; - clocks = <&clk26mhz>; - status = "disabled"; - }; - }; - }; - - clk26mhz: clk26mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <26000000>; - }; -}; diff --git a/sys/gnu/dts/arm64/sprd/sp9860g-1h10.dts b/sys/gnu/dts/arm64/sprd/sp9860g-1h10.dts deleted file mode 100644 index 6b95fd94cee..00000000000 --- a/sys/gnu/dts/arm64/sprd/sp9860g-1h10.dts +++ /dev/null @@ -1,74 +0,0 @@ -/* - * Spreadtrum SP9860g board - * - * Copyright (C) 2017, Spreadtrum Communications Inc. - * - * SPDX-License-Identifier: (GPL-2.0+ OR MIT) - */ - -/dts-v1/; - -#include "sc9860.dtsi" -#include "sc2731.dtsi" - -/ { - model = "Spreadtrum SP9860G 3GFHD Board"; - - compatible = "sprd,sp9860g-1h10", "sprd,sc9860"; - - aliases { - serial0 = &uart0; /* for Bluetooth */ - serial1 = &uart1; /* UART console */ - serial2 = &uart2; /* Reserved */ - serial3 = &uart3; /* for GPS */ - spi0 = &adi_bus; - }; - - memory{ - device_type = "memory"; - reg = <0x0 0x80000000 0 0x60000000>, - <0x1 0x80000000 0 0x60000000>; - }; - - chosen { - stdout-path = "serial1:115200n8"; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - }; - - bat: battery { - compatible = "simple-battery"; - charge-full-design-microamp-hours = <1900000>; - charge-term-current-microamp = <120000>; - constant_charge_voltage_max_microvolt = <4350000>; - internal-resistance-micro-ohms = <250000>; - ocv-capacity-celsius = <20>; - ocv-capacity-table-0 = <4185000 100>, <4113000 95>, <4066000 90>, - <4022000 85>, <3983000 80>, <3949000 75>, - <3917000 70>, <3889000 65>, <3864000 60>, - <3835000 55>, <3805000 50>, <3787000 45>, - <3777000 40>, <3773000 35>, <3770000 30>, - <3765000 25>, <3752000 20>, <3724000 15>, - <3680000 10>, <3605000 5>, <3400000 0>; - }; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/sprd/sp9863a-1h10.dts b/sys/gnu/dts/arm64/sprd/sp9863a-1h10.dts deleted file mode 100644 index 5c32c159633..00000000000 --- a/sys/gnu/dts/arm64/sprd/sp9863a-1h10.dts +++ /dev/null @@ -1,39 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Unisoc SP9863A-1h10 boards DTS file - * - * Copyright (C) 2019, Unisoc Inc. - */ - -/dts-v1/; - -#include "sc9863a.dtsi" - -/ { - model = "Spreadtrum SP9863A-1H10 Board"; - - compatible = "sprd,sp9863a-1h10", "sprd,sc9863a"; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x0 0x80000000 0x0 0x80000000>; - }; - - chosen { - stdout-path = "serial1:115200n8"; - bootargs = "earlycon"; - }; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/sprd/whale2.dtsi b/sys/gnu/dts/arm64/sprd/whale2.dtsi deleted file mode 100644 index 79b9591c37a..00000000000 --- a/sys/gnu/dts/arm64/sprd/whale2.dtsi +++ /dev/null @@ -1,310 +0,0 @@ -/* - * Spreadtrum Whale2 platform peripherals - * - * Copyright (C) 2016, Spreadtrum Communications Inc. - * - * SPDX-License-Identifier: (GPL-2.0+ OR MIT) - */ - -#include - -/ { - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - soc: soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - ap_ahb_regs: syscon@20210000 { - compatible = "syscon"; - reg = <0 0x20210000 0 0x10000>; - }; - - pmu_regs: syscon@402b0000 { - compatible = "syscon"; - reg = <0 0x402b0000 0 0x10000>; - }; - - aon_regs: syscon@402e0000 { - compatible = "syscon"; - reg = <0 0x402e0000 0 0x10000>; - }; - - ana_regs: syscon@40400000 { - compatible = "syscon"; - reg = <0 0x40400000 0 0x10000>; - }; - - agcp_regs: syscon@415e0000 { - compatible = "syscon"; - reg = <0 0x415e0000 0 0x1000000>; - }; - - vsp_regs: syscon@61100000 { - compatible = "syscon"; - reg = <0 0x61100000 0 0x10000>; - }; - - cam_regs: syscon@62100000 { - compatible = "syscon"; - reg = <0 0x62100000 0 0x10000>; - }; - - disp_regs: syscon@63100000 { - compatible = "syscon"; - reg = <0 0x63100000 0 0x10000>; - }; - - ap_apb_regs: syscon@70b00000 { - compatible = "syscon"; - reg = <0 0x70b00000 0 0x40000>; - }; - - ap-apb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x0 0x70000000 0x10000000>; - - uart0: serial@0 { - compatible = "sprd,sc9860-uart", - "sprd,sc9836-uart"; - reg = <0x0 0x100>; - interrupts = ; - clock-names = "enable", "uart", "source"; - clocks = <&apapb_gate CLK_UART0_EB>, - <&ap_clk CLK_UART0>, <&ext_26m>; - status = "disabled"; - }; - - uart1: serial@100000 { - compatible = "sprd,sc9860-uart", - "sprd,sc9836-uart"; - reg = <0x100000 0x100>; - interrupts = ; - clock-names = "enable", "uart", "source"; - clocks = <&apapb_gate CLK_UART1_EB>, - <&ap_clk CLK_UART1>, <&ext_26m>; - status = "disabled"; - }; - - uart2: serial@200000 { - compatible = "sprd,sc9860-uart", - "sprd,sc9836-uart"; - reg = <0x200000 0x100>; - interrupts = ; - clock-names = "enable", "uart", "source"; - clocks = <&apapb_gate CLK_UART2_EB>, - <&ap_clk CLK_UART2>, <&ext_26m>; - status = "disabled"; - }; - - uart3: serial@300000 { - compatible = "sprd,sc9860-uart", - "sprd,sc9836-uart"; - reg = <0x300000 0x100>; - interrupts = ; - clock-names = "enable", "uart", "source"; - clocks = <&apapb_gate CLK_UART3_EB>, - <&ap_clk CLK_UART3>, <&ext_26m>; - status = "disabled"; - }; - }; - - ap-ahb { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - ap_dma: dma-controller@20100000 { - compatible = "sprd,sc9860-dma"; - reg = <0 0x20100000 0 0x4000>; - interrupts = ; - #dma-cells = <1>; - #dma-channels = <32>; - clock-names = "enable"; - clocks = <&apahb_gate CLK_DMA_EB>; - }; - - sdio3: sdio@50430000 { - compatible = "sprd,sdhci-r11"; - reg = <0 0x50430000 0 0x1000>; - interrupts = ; - - clock-names = "sdio", "enable", "2x_enable"; - clocks = <&aon_prediv CLK_EMMC_2X>, - <&apahb_gate CLK_EMMC_EB>, - <&aon_gate CLK_EMMC_2X_EN>; - assigned-clocks = <&aon_prediv CLK_EMMC_2X>; - assigned-clock-parents = <&clk_l0_409m6>; - - sprd,phy-delay-mmc-hs400 = <0x44 0x7f 0x2e 0x2e>; - sprd,phy-delay-mmc-hs200 = <0x0 0x8c 0x8c 0x8c>; - sprd,phy-delay-mmc-ddr52 = <0x3f 0x75 0x14 0x14>; - sprd,phy-delay-mmc-hs400es = <0x3f 0x3f 0x2e 0x2e>; - vmmc-supply = <&vddemmccore>; - bus-width = <8>; - non-removable; - no-sdio; - no-sd; - cap-mmc-hw-reset; - mmc-hs400-enhanced-strobe; - mmc-hs400-1_8v; - mmc-hs200-1_8v; - mmc-ddr-1_8v; - }; - }; - - aon { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - adi_bus: spi@40030000 { - compatible = "sprd,sc9860-adi"; - reg = <0 0x40030000 0 0x10000>; - hwlocks = <&hwlock 0>; - hwlock-names = "adi"; - #address-cells = <1>; - #size-cells = <0>; - }; - - timer@40050000 { - compatible = "sprd,sc9860-timer"; - reg = <0 0x40050000 0 0x20>; - interrupts = ; - clocks = <&ext_32k>; - }; - - timer@40050020 { - compatible = "sprd,sc9860-suspend-timer"; - reg = <0 0x40050020 0 0x20>; - clocks = <&ext_32k>; - }; - - hwlock: hwspinlock@40500000 { - compatible = "sprd,hwspinlock-r3p0"; - reg = <0 0x40500000 0 0x1000>; - #hwlock-cells = <1>; - clock-names = "enable"; - clocks = <&aon_gate CLK_SPLK_EB>; - }; - - eic_debounce: gpio@40210000 { - compatible = "sprd,sc9860-eic-debounce"; - reg = <0 0x40210000 0 0x80>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = ; - }; - - eic_latch: gpio@40210080 { - compatible = "sprd,sc9860-eic-latch"; - reg = <0 0x40210080 0 0x20>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = ; - }; - - eic_async: gpio@402100a0 { - compatible = "sprd,sc9860-eic-async"; - reg = <0 0x402100a0 0 0x20>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = ; - }; - - eic_sync: gpio@402100c0 { - compatible = "sprd,sc9860-eic-sync"; - reg = <0 0x402100c0 0 0x20>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = ; - }; - - ap_gpio: gpio@40280000 { - compatible = "sprd,sc9860-gpio"; - reg = <0 0x40280000 0 0x1000>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = ; - }; - - pin_controller: pinctrl@402a0000 { - compatible = "sprd,sc9860-pinctrl"; - reg = <0 0x402a0000 0 0x10000>; - }; - - watchdog@40310000 { - compatible = "sprd,sp9860-wdt"; - reg = <0 0x40310000 0 0x1000>; - interrupts = ; - timeout-sec = <12>; - clock-names = "enable", "rtc_enable"; - clocks = <&aon_gate CLK_APCPU_WDG_EB>, - <&aon_gate CLK_AP_WDG_RTC_EB>; - }; - }; - - agcp { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - agcp_dma: dma-controller@41580000 { - compatible = "sprd,sc9860-dma"; - reg = <0 0x41580000 0 0x4000>; - #dma-cells = <1>; - #dma-channels = <32>; - clock-names = "enable", "ashb_eb"; - clocks = <&agcp_gate CLK_AGCP_DMAAP_EB>, - <&agcp_gate CLK_AGCP_AP_ASHB_EB>; - }; - }; - }; - - ext_32k: ext_32k { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "ext-32k"; - }; - - ext_26m: ext_26m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <26000000>; - clock-output-names = "ext-26m"; - }; - - ext_rco_100m: ext_rco_100m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - clock-output-names = "ext-rco-100m"; - }; - - clk_l0_409m6: clk_l0_409m6 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <409600000>; - clock-output-names = "ext-409m6"; - }; -}; diff --git a/sys/gnu/dts/arm64/synaptics/as370.dtsi b/sys/gnu/dts/arm64/synaptics/as370.dtsi deleted file mode 100644 index addeb0efc61..00000000000 --- a/sys/gnu/dts/arm64/synaptics/as370.dtsi +++ /dev/null @@ -1,173 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2018 Synaptics Incorporated - * - * Author: Jisheng Zhang - */ - -#include - -/ { - compatible = "syna,as370"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <0x0>; - enable-method = "psci"; - next-level-cache = <&l2>; - cpu-idle-states = <&CPU_SLEEP_0>; - }; - - cpu1: cpu@1 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <0x1>; - enable-method = "psci"; - next-level-cache = <&l2>; - cpu-idle-states = <&CPU_SLEEP_0>; - }; - - cpu2: cpu@2 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <0x2>; - enable-method = "psci"; - next-level-cache = <&l2>; - cpu-idle-states = <&CPU_SLEEP_0>; - }; - - cpu3: cpu@3 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <0x3>; - enable-method = "psci"; - next-level-cache = <&l2>; - cpu-idle-states = <&CPU_SLEEP_0>; - }; - - l2: cache { - compatible = "cache"; - }; - - idle-states { - entry-method = "psci"; - CPU_SLEEP_0: cpu-sleep-0 { - compatible = "arm,idle-state"; - local-timer-stop; - arm,psci-suspend-param = <0x0010000>; - entry-latency-us = <75>; - exit-latency-us = <155>; - min-residency-us = <1000>; - }; - }; - }; - - osc: osc { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - - pmu { - compatible = "arm,cortex-a53-pmu"; - interrupts = , - , - , - ; - interrupt-affinity = <&cpu0>, - <&cpu1>, - <&cpu2>, - <&cpu3>; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - soc@f7000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0xf7000000 0x1000000>; - - gic: interrupt-controller@901000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x901000 0x1000>, - <0x902000 0x2000>, - <0x904000 0x2000>, - <0x906000 0x2000>; - interrupts = ; - }; - - apb@e80000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0xe80000 0x10000>; - - uart0: serial@c00 { - compatible = "snps,dw-apb-uart"; - reg = <0xc00 0x100>; - interrupts = ; - clocks = <&osc>; - reg-shift = <2>; - status = "disabled"; - }; - - gpio0: gpio@1800 { - compatible = "snps,dw-apb-gpio"; - reg = <0x1800 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - porta: gpio-port@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <32>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = ; - }; - }; - - gpio1: gpio@2000 { - compatible = "snps,dw-apb-gpio"; - reg = <0x2000 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - portb: gpio-port@1 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <32>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = ; - }; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/synaptics/berlin4ct-dmp.dts b/sys/gnu/dts/arm64/synaptics/berlin4ct-dmp.dts deleted file mode 100644 index c64a179ebbb..00000000000 --- a/sys/gnu/dts/arm64/synaptics/berlin4ct-dmp.dts +++ /dev/null @@ -1,29 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2015 Marvell Technology Group Ltd. - * - * Author: Jisheng Zhang - */ - -/dts-v1/; - -#include "berlin4ct.dtsi" - -/ { - model = "Marvell BG4CT DMP board"; - compatible = "marvell,berlin4ct-dmp", "marvell,berlin4ct", "marvell,berlin"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@1000000 { - device_type = "memory"; - /* the first 16MB is for firmwares' usage */ - reg = <0 0x01000000 0 0x7f000000>; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/synaptics/berlin4ct-stb.dts b/sys/gnu/dts/arm64/synaptics/berlin4ct-stb.dts deleted file mode 100644 index 277dccfa05c..00000000000 --- a/sys/gnu/dts/arm64/synaptics/berlin4ct-stb.dts +++ /dev/null @@ -1,29 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2015 Marvell Technology Group Ltd. - * - * Author: Jisheng Zhang - */ - -/dts-v1/; - -#include "berlin4ct.dtsi" - -/ { - model = "Marvell BG4CT STB board"; - compatible = "marvell,berlin4ct-stb", "marvell,berlin4ct", "marvell,berlin"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@1000000 { - device_type = "memory"; - /* the first 16MB is for firmwares' usage */ - reg = <0 0x01000000 0 0x7f000000>; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/synaptics/berlin4ct.dtsi b/sys/gnu/dts/arm64/synaptics/berlin4ct.dtsi deleted file mode 100644 index 15625b99e33..00000000000 --- a/sys/gnu/dts/arm64/synaptics/berlin4ct.dtsi +++ /dev/null @@ -1,314 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2015 Marvell Technology Group Ltd. - * - * Author: Jisheng Zhang - */ - -#include - -/ { - compatible = "marvell,berlin4ct", "marvell,berlin"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - serial0 = &uart0; - }; - - psci { - compatible = "arm,psci-1.0", "arm,psci-0.2"; - method = "smc"; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <0x0>; - enable-method = "psci"; - next-level-cache = <&l2>; - cpu-idle-states = <&CPU_SLEEP_0>; - }; - - cpu1: cpu@1 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <0x1>; - enable-method = "psci"; - next-level-cache = <&l2>; - cpu-idle-states = <&CPU_SLEEP_0>; - }; - - cpu2: cpu@2 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <0x2>; - enable-method = "psci"; - next-level-cache = <&l2>; - cpu-idle-states = <&CPU_SLEEP_0>; - }; - - cpu3: cpu@3 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <0x3>; - enable-method = "psci"; - next-level-cache = <&l2>; - cpu-idle-states = <&CPU_SLEEP_0>; - }; - - l2: cache { - compatible = "cache"; - }; - - idle-states { - entry-method = "psci"; - CPU_SLEEP_0: cpu-sleep-0 { - compatible = "arm,idle-state"; - local-timer-stop; - arm,psci-suspend-param = <0x0010000>; - entry-latency-us = <75>; - exit-latency-us = <155>; - min-residency-us = <1000>; - }; - }; - }; - - osc: osc { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - - pmu { - compatible = "arm,cortex-a53-pmu", "arm,armv8-pmuv3"; - interrupts = , - , - , - ; - interrupt-affinity = <&cpu0>, - <&cpu1>, - <&cpu2>, - <&cpu3>; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - soc@f7000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0xf7000000 0x1000000>; - - gic: interrupt-controller@901000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x901000 0x1000>, - <0x902000 0x2000>, - <0x904000 0x2000>, - <0x906000 0x2000>; - interrupts = ; - }; - - apb@e80000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - - ranges = <0 0xe80000 0x10000>; - interrupt-parent = <&aic>; - - gpio0: gpio@400 { - compatible = "snps,dw-apb-gpio"; - reg = <0x0400 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - porta: gpio-port@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <32>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <0>; - }; - }; - - gpio1: gpio@800 { - compatible = "snps,dw-apb-gpio"; - reg = <0x0800 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - portb: gpio-port@1 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <32>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <1>; - }; - }; - - gpio2: gpio@c00 { - compatible = "snps,dw-apb-gpio"; - reg = <0x0c00 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - portc: gpio-port@2 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <32>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <2>; - }; - }; - - gpio3: gpio@1000 { - compatible = "snps,dw-apb-gpio"; - reg = <0x1000 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - portd: gpio-port@3 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <32>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <3>; - }; - }; - - aic: interrupt-controller@3800 { - compatible = "snps,dw-apb-ictl"; - reg = <0x3800 0x30>; - interrupt-controller; - #interrupt-cells = <1>; - interrupt-parent = <&gic>; - interrupts = ; - }; - }; - - soc_pinctrl: pin-controller@ea8000 { - compatible = "marvell,berlin4ct-soc-pinctrl"; - reg = <0xea8000 0x14>; - }; - - avio_pinctrl: pin-controller@ea8400 { - compatible = "marvell,berlin4ct-avio-pinctrl"; - reg = <0xea8400 0x8>; - }; - - apb@fc0000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0xfc0000 0x10000>; - interrupt-parent = <&sic>; - - sic: interrupt-controller@1000 { - compatible = "snps,dw-apb-ictl"; - reg = <0x1000 0x30>; - interrupt-controller; - #interrupt-cells = <1>; - interrupt-parent = <&gic>; - interrupts = ; - }; - - wdt0: watchdog@3000 { - compatible = "snps,dw-wdt"; - reg = <0x3000 0x100>; - clocks = <&osc>; - interrupts = <0>; - }; - - wdt1: watchdog@4000 { - compatible = "snps,dw-wdt"; - reg = <0x4000 0x100>; - clocks = <&osc>; - interrupts = <1>; - }; - - wdt2: watchdog@5000 { - compatible = "snps,dw-wdt"; - reg = <0x5000 0x100>; - clocks = <&osc>; - interrupts = <2>; - }; - - sm_gpio0: gpio@8000 { - compatible = "snps,dw-apb-gpio"; - reg = <0x8000 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - porte: gpio-port@4 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <32>; - reg = <0>; - }; - }; - - sm_gpio1: gpio@9000 { - compatible = "snps,dw-apb-gpio"; - reg = <0x9000 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - portf: gpio-port@5 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <32>; - reg = <0>; - }; - }; - - uart0: uart@d000 { - compatible = "snps,dw-apb-uart"; - reg = <0xd000 0x100>; - interrupts = <8>; - clocks = <&osc>; - reg-shift = <2>; - status = "disabled"; - pinctrl-0 = <&uart0_pmux>; - pinctrl-names = "default"; - }; - }; - - system_pinctrl: pin-controller@fe2200 { - compatible = "marvell,berlin4ct-system-pinctrl"; - reg = <0xfe2200 0xc>; - - uart0_pmux: uart0-pmux { - groups = "SM_URT0_TXD", "SM_URT0_RXD"; - function = "uart0"; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/ti/k3-am65-main.dtsi b/sys/gnu/dts/arm64/ti/k3-am65-main.dtsi deleted file mode 100644 index e5df20a2d2f..00000000000 --- a/sys/gnu/dts/arm64/ti/k3-am65-main.dtsi +++ /dev/null @@ -1,745 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for AM6 SoC Family Main Domain peripherals - * - * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/ - */ -#include - -&cbass_main { - msmc_ram: sram@70000000 { - compatible = "mmio-sram"; - reg = <0x0 0x70000000 0x0 0x200000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x70000000 0x200000>; - - atf-sram@0 { - reg = <0x0 0x20000>; - }; - - sysfw-sram@f0000 { - reg = <0xf0000 0x10000>; - }; - - l3cache-sram@100000 { - reg = <0x100000 0x100000>; - }; - }; - - gic500: interrupt-controller@1800000 { - compatible = "arm,gic-v3"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ - <0x00 0x01880000 0x00 0x90000>; /* GICR */ - /* - * vcpumntirq: - * virtual CPU interface maintenance interrupt - */ - interrupts = ; - - gic_its: gic-its@1820000 { - compatible = "arm,gic-v3-its"; - reg = <0x00 0x01820000 0x00 0x10000>; - socionext,synquacer-pre-its = <0x1000000 0x400000>; - msi-controller; - #msi-cells = <1>; - }; - }; - - serdes0: serdes@900000 { - compatible = "ti,phy-am654-serdes"; - reg = <0x0 0x900000 0x0 0x2000>; - reg-names = "serdes"; - #phy-cells = <2>; - power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 153 4>, <&k3_clks 153 1>, <&serdes1 AM654_SERDES_LO_REFCLK>; - clock-output-names = "serdes0_cmu_refclk", "serdes0_lo_refclk", "serdes0_ro_refclk"; - assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>; - assigned-clock-parents = <&k3_clks 153 8>, <&k3_clks 153 4>; - ti,serdes-clk = <&serdes0_clk>; - #clock-cells = <1>; - mux-controls = <&serdes_mux 0>; - }; - - serdes1: serdes@910000 { - compatible = "ti,phy-am654-serdes"; - reg = <0x0 0x910000 0x0 0x2000>; - reg-names = "serdes"; - #phy-cells = <2>; - power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; - clocks = <&serdes0 AM654_SERDES_RO_REFCLK>, <&k3_clks 154 1>, <&k3_clks 154 5>; - clock-output-names = "serdes1_cmu_refclk", "serdes1_lo_refclk", "serdes1_ro_refclk"; - assigned-clocks = <&k3_clks 154 5>, <&serdes1 AM654_SERDES_CMU_REFCLK>; - assigned-clock-parents = <&k3_clks 154 9>, <&k3_clks 154 5>; - ti,serdes-clk = <&serdes1_clk>; - #clock-cells = <1>; - mux-controls = <&serdes_mux 1>; - }; - - main_uart0: serial@2800000 { - compatible = "ti,am654-uart"; - reg = <0x00 0x02800000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; - interrupts = ; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; - }; - - main_uart1: serial@2810000 { - compatible = "ti,am654-uart"; - reg = <0x00 0x02810000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; - interrupts = ; - clock-frequency = <48000000>; - power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>; - }; - - main_uart2: serial@2820000 { - compatible = "ti,am654-uart"; - reg = <0x00 0x02820000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; - interrupts = ; - clock-frequency = <48000000>; - power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>; - }; - - main_pmx0: pinmux@11c000 { - compatible = "pinctrl-single"; - reg = <0x0 0x11c000 0x0 0x2e4>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0xffffffff>; - }; - - main_pmx1: pinmux@11c2e8 { - compatible = "pinctrl-single"; - reg = <0x0 0x11c2e8 0x0 0x24>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0xffffffff>; - }; - - main_i2c0: i2c@2000000 { - compatible = "ti,am654-i2c", "ti,omap4-i2c"; - reg = <0x0 0x2000000 0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 110 1>; - power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; - }; - - main_i2c1: i2c@2010000 { - compatible = "ti,am654-i2c", "ti,omap4-i2c"; - reg = <0x0 0x2010000 0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 111 1>; - power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; - }; - - main_i2c2: i2c@2020000 { - compatible = "ti,am654-i2c", "ti,omap4-i2c"; - reg = <0x0 0x2020000 0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 112 1>; - power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>; - }; - - main_i2c3: i2c@2030000 { - compatible = "ti,am654-i2c", "ti,omap4-i2c"; - reg = <0x0 0x2030000 0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 113 1>; - power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; - }; - - ecap0: pwm@3100000 { - compatible = "ti,am654-ecap", "ti,am3352-ecap"; - #pwm-cells = <3>; - reg = <0x0 0x03100000 0x0 0x60>; - power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 39 0>; - clock-names = "fck"; - }; - - main_spi0: spi@2100000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x0 0x2100000 0x0 0x400>; - interrupts = ; - clocks = <&k3_clks 137 1>; - power-domains = <&k3_pds 137 TI_SCI_PD_EXCLUSIVE>; - #address-cells = <1>; - #size-cells = <0>; - }; - - main_spi1: spi@2110000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x0 0x2110000 0x0 0x400>; - interrupts = ; - clocks = <&k3_clks 138 1>; - power-domains = <&k3_pds 138 TI_SCI_PD_EXCLUSIVE>; - #address-cells = <1>; - #size-cells = <0>; - assigned-clocks = <&k3_clks 137 1>; - assigned-clock-rates = <48000000>; - }; - - main_spi2: spi@2120000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x0 0x2120000 0x0 0x400>; - interrupts = ; - clocks = <&k3_clks 139 1>; - power-domains = <&k3_pds 139 TI_SCI_PD_EXCLUSIVE>; - #address-cells = <1>; - #size-cells = <0>; - }; - - main_spi3: spi@2130000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x0 0x2130000 0x0 0x400>; - interrupts = ; - clocks = <&k3_clks 140 1>; - power-domains = <&k3_pds 140 TI_SCI_PD_EXCLUSIVE>; - #address-cells = <1>; - #size-cells = <0>; - }; - - main_spi4: spi@2140000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x0 0x2140000 0x0 0x400>; - interrupts = ; - clocks = <&k3_clks 141 1>; - power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>; - #address-cells = <1>; - #size-cells = <0>; - }; - - sdhci0: sdhci@4f80000 { - compatible = "ti,am654-sdhci-5.1"; - reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>; - power-domains = <&k3_pds 47 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 47 0>, <&k3_clks 47 1>; - clock-names = "clk_ahb", "clk_xin"; - interrupts = ; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - ti,otap-del-sel = <0x2>; - ti,trm-icp = <0x8>; - dma-coherent; - }; - - scm_conf: scm_conf@100000 { - compatible = "syscon", "simple-mfd"; - reg = <0 0x00100000 0 0x1c000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x00100000 0x1c000>; - - pcie0_mode: pcie-mode@4060 { - compatible = "syscon"; - reg = <0x00004060 0x4>; - }; - - pcie1_mode: pcie-mode@4070 { - compatible = "syscon"; - reg = <0x00004070 0x4>; - }; - - pcie_devid: pcie-devid@210 { - compatible = "syscon"; - reg = <0x00000210 0x4>; - }; - - serdes0_clk: serdes_clk@4080 { - compatible = "syscon"; - reg = <0x00004080 0x4>; - }; - - serdes1_clk: serdes_clk@4090 { - compatible = "syscon"; - reg = <0x00004090 0x4>; - }; - - serdes_mux: mux-controller { - compatible = "mmio-mux"; - #mux-control-cells = <1>; - mux-reg-masks = <0x4080 0x3>, /* SERDES0 lane select */ - <0x4090 0x3>; /* SERDES1 lane select */ - }; - }; - - dwc3_0: dwc3@4000000 { - compatible = "ti,am654-dwc3"; - reg = <0x0 0x4000000 0x0 0x4000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x4000000 0x20000>; - interrupts = ; - dma-coherent; - power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>; - assigned-clocks = <&k3_clks 151 2>, <&k3_clks 151 7>; - assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */ - <&k3_clks 151 9>; /* set PIPE3_TXB_CLK to CLK_12M_RC/256 (for HS only) */ - - usb0: usb@10000 { - compatible = "snps,dwc3"; - reg = <0x10000 0x10000>; - interrupts = , - , - ; - interrupt-names = "peripheral", - "host", - "otg"; - maximum-speed = "high-speed"; - dr_mode = "otg"; - phys = <&usb0_phy>; - phy-names = "usb2-phy"; - snps,dis_u3_susphy_quirk; - }; - }; - - usb0_phy: phy@4100000 { - compatible = "ti,am654-usb2", "ti,omap-usb2"; - reg = <0x0 0x4100000 0x0 0x54>; - syscon-phy-power = <&scm_conf 0x4000>; - clocks = <&k3_clks 151 0>, <&k3_clks 151 1>; - clock-names = "wkupclk", "refclk"; - #phy-cells = <0>; - }; - - dwc3_1: dwc3@4020000 { - compatible = "ti,am654-dwc3"; - reg = <0x0 0x4020000 0x0 0x4000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x4020000 0x20000>; - interrupts = ; - dma-coherent; - power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; - assigned-clocks = <&k3_clks 152 2>; - assigned-clock-parents = <&k3_clks 152 4>; /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */ - - usb1: usb@10000 { - compatible = "snps,dwc3"; - reg = <0x10000 0x10000>; - interrupts = , - , - ; - interrupt-names = "peripheral", - "host", - "otg"; - maximum-speed = "high-speed"; - dr_mode = "otg"; - phys = <&usb1_phy>; - phy-names = "usb2-phy"; - }; - }; - - usb1_phy: phy@4110000 { - compatible = "ti,am654-usb2", "ti,omap-usb2"; - reg = <0x0 0x4110000 0x0 0x54>; - syscon-phy-power = <&scm_conf 0x4020>; - clocks = <&k3_clks 152 0>, <&k3_clks 152 1>; - clock-names = "wkupclk", "refclk"; - #phy-cells = <0>; - }; - - intr_main_gpio: interrupt-controller0 { - compatible = "ti,sci-intr"; - ti,intr-trigger-type = <1>; - interrupt-controller; - interrupt-parent = <&gic500>; - #interrupt-cells = <2>; - ti,sci = <&dmsc>; - ti,sci-dst-id = <56>; - ti,sci-rm-range-girq = <0x1>; - }; - - main_navss { - compatible = "simple-mfd"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - dma-coherent; - dma-ranges; - - ti,sci-dev-id = <118>; - - intr_main_navss: interrupt-controller1 { - compatible = "ti,sci-intr"; - ti,intr-trigger-type = <4>; - interrupt-controller; - interrupt-parent = <&gic500>; - #interrupt-cells = <2>; - ti,sci = <&dmsc>; - ti,sci-dst-id = <56>; - ti,sci-rm-range-girq = <0x0>, <0x2>; - }; - - inta_main_udmass: interrupt-controller@33d00000 { - compatible = "ti,sci-inta"; - reg = <0x0 0x33d00000 0x0 0x100000>; - interrupt-controller; - interrupt-parent = <&intr_main_navss>; - msi-controller; - ti,sci = <&dmsc>; - ti,sci-dev-id = <179>; - ti,sci-rm-range-vint = <0x0>; - ti,sci-rm-range-global-event = <0x1>; - }; - - secure_proxy_main: mailbox@32c00000 { - compatible = "ti,am654-secure-proxy"; - #mbox-cells = <1>; - reg-names = "target_data", "rt", "scfg"; - reg = <0x00 0x32c00000 0x00 0x100000>, - <0x00 0x32400000 0x00 0x100000>, - <0x00 0x32800000 0x00 0x100000>; - interrupt-names = "rx_011"; - interrupts = ; - }; - - hwspinlock: spinlock@30e00000 { - compatible = "ti,am654-hwspinlock"; - reg = <0x00 0x30e00000 0x00 0x1000>; - #hwlock-cells = <1>; - }; - - mailbox0_cluster0: mailbox@31f80000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f80000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&intr_main_navss>; - }; - - mailbox0_cluster1: mailbox@31f81000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f81000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&intr_main_navss>; - }; - - mailbox0_cluster2: mailbox@31f82000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f82000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&intr_main_navss>; - }; - - mailbox0_cluster3: mailbox@31f83000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f83000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&intr_main_navss>; - }; - - mailbox0_cluster4: mailbox@31f84000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f84000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&intr_main_navss>; - }; - - mailbox0_cluster5: mailbox@31f85000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f85000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&intr_main_navss>; - }; - - mailbox0_cluster6: mailbox@31f86000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f86000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&intr_main_navss>; - }; - - mailbox0_cluster7: mailbox@31f87000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f87000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&intr_main_navss>; - }; - - mailbox0_cluster8: mailbox@31f88000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f88000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&intr_main_navss>; - }; - - mailbox0_cluster9: mailbox@31f89000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f89000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&intr_main_navss>; - }; - - mailbox0_cluster10: mailbox@31f8a000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f8a000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&intr_main_navss>; - }; - - mailbox0_cluster11: mailbox@31f8b000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f8b000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&intr_main_navss>; - }; - - ringacc: ringacc@3c000000 { - compatible = "ti,am654-navss-ringacc"; - reg = <0x0 0x3c000000 0x0 0x400000>, - <0x0 0x38000000 0x0 0x400000>, - <0x0 0x31120000 0x0 0x100>, - <0x0 0x33000000 0x0 0x40000>; - reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; - ti,num-rings = <818>; - ti,sci-rm-range-gp-rings = <0x2>; /* GP ring range */ - ti,dma-ring-reset-quirk; - ti,sci = <&dmsc>; - ti,sci-dev-id = <187>; - msi-parent = <&inta_main_udmass>; - }; - - main_udmap: dma-controller@31150000 { - compatible = "ti,am654-navss-main-udmap"; - reg = <0x0 0x31150000 0x0 0x100>, - <0x0 0x34000000 0x0 0x100000>, - <0x0 0x35000000 0x0 0x100000>; - reg-names = "gcfg", "rchanrt", "tchanrt"; - msi-parent = <&inta_main_udmass>; - #dma-cells = <1>; - - ti,sci = <&dmsc>; - ti,sci-dev-id = <188>; - ti,ringacc = <&ringacc>; - - ti,sci-rm-range-tchan = <0x1>, /* TX_HCHAN */ - <0x2>; /* TX_CHAN */ - ti,sci-rm-range-rchan = <0x4>, /* RX_HCHAN */ - <0x5>; /* RX_CHAN */ - ti,sci-rm-range-rflow = <0x6>; /* GP RFLOW */ - }; - }; - - main_gpio0: main_gpio0@600000 { - compatible = "ti,am654-gpio", "ti,keystone-gpio"; - reg = <0x0 0x600000 0x0 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&intr_main_gpio>; - interrupts = <57 256>, <57 257>, <57 258>, <57 259>, <57 260>, - <57 261>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <96>; - ti,davinci-gpio-unbanked = <0>; - clocks = <&k3_clks 57 0>; - clock-names = "gpio"; - }; - - main_gpio1: main_gpio1@601000 { - compatible = "ti,am654-gpio", "ti,keystone-gpio"; - reg = <0x0 0x601000 0x0 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&intr_main_gpio>; - interrupts = <58 256>, <58 257>, <58 258>, <58 259>, <58 260>, - <58 261>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <90>; - ti,davinci-gpio-unbanked = <0>; - clocks = <&k3_clks 58 0>; - clock-names = "gpio"; - }; - - pcie0_rc: pcie@5500000 { - compatible = "ti,am654-pcie-rc"; - reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x2000>, <0x0 0x5506000 0x0 0x1000>; - reg-names = "app", "dbics", "config", "atu"; - power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; - #address-cells = <3>; - #size-cells = <2>; - ranges = <0x81000000 0 0 0x0 0x10020000 0 0x00010000 - 0x82000000 0 0x10030000 0x0 0x10030000 0 0x07FD0000>; - ti,syscon-pcie-id = <&pcie_devid>; - ti,syscon-pcie-mode = <&pcie0_mode>; - bus-range = <0x0 0xff>; - num-viewport = <16>; - max-link-speed = <3>; - dma-coherent; - interrupts = ; - msi-map = <0x0 &gic_its 0x0 0x10000>; - }; - - pcie0_ep: pcie-ep@5500000 { - compatible = "ti,am654-pcie-ep"; - reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x8000000>, <0x0 0x5506000 0x0 0x1000>; - reg-names = "app", "dbics", "addr_space", "atu"; - power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; - ti,syscon-pcie-mode = <&pcie0_mode>; - num-ib-windows = <16>; - num-ob-windows = <16>; - max-link-speed = <3>; - dma-coherent; - interrupts = ; - }; - - pcie1_rc: pcie@5600000 { - compatible = "ti,am654-pcie-rc"; - reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x2000>, <0x0 0x5606000 0x0 0x1000>; - reg-names = "app", "dbics", "config", "atu"; - power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>; - #address-cells = <3>; - #size-cells = <2>; - ranges = <0x81000000 0 0 0x0 0x18020000 0 0x00010000 - 0x82000000 0 0x18030000 0x0 0x18030000 0 0x07FD0000>; - ti,syscon-pcie-id = <&pcie_devid>; - ti,syscon-pcie-mode = <&pcie1_mode>; - bus-range = <0x0 0xff>; - num-viewport = <16>; - max-link-speed = <3>; - dma-coherent; - interrupts = ; - msi-map = <0x0 &gic_its 0x10000 0x10000>; - }; - - pcie1_ep: pcie-ep@5600000 { - compatible = "ti,am654-pcie-ep"; - reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x4000000>, <0x0 0x5606000 0x0 0x1000>; - reg-names = "app", "dbics", "addr_space", "atu"; - power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>; - ti,syscon-pcie-mode = <&pcie1_mode>; - num-ib-windows = <16>; - num-ob-windows = <16>; - max-link-speed = <3>; - dma-coherent; - interrupts = ; - }; - - mcasp0: mcasp@2b00000 { - compatible = "ti,am33xx-mcasp-audio"; - reg = <0x0 0x02b00000 0x0 0x2000>, - <0x0 0x02b08000 0x0 0x1000>; - reg-names = "mpu","dat"; - interrupts = , - ; - interrupt-names = "tx", "rx"; - - dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>; - dma-names = "tx", "rx"; - - clocks = <&k3_clks 104 0>; - clock-names = "fck"; - power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; - - status = "disabled"; - }; - - mcasp1: mcasp@2b10000 { - compatible = "ti,am33xx-mcasp-audio"; - reg = <0x0 0x02b10000 0x0 0x2000>, - <0x0 0x02b18000 0x0 0x1000>; - reg-names = "mpu","dat"; - interrupts = , - ; - interrupt-names = "tx", "rx"; - - dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>; - dma-names = "tx", "rx"; - - clocks = <&k3_clks 105 0>; - clock-names = "fck"; - power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; - - status = "disabled"; - }; - - mcasp2: mcasp@2b20000 { - compatible = "ti,am33xx-mcasp-audio"; - reg = <0x0 0x02b20000 0x0 0x2000>, - <0x0 0x02b28000 0x0 0x1000>; - reg-names = "mpu","dat"; - interrupts = , - ; - interrupt-names = "tx", "rx"; - - dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>; - dma-names = "tx", "rx"; - - clocks = <&k3_clks 106 0>; - clock-names = "fck"; - power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; - - status = "disabled"; - }; - - cal: cal@6f03000 { - compatible = "ti,am654-cal"; - reg = <0x0 0x06f03000 0x0 0x400>, - <0x0 0x06f03800 0x0 0x40>; - reg-names = "cal_top", - "cal_rx_core0"; - interrupts = ; - ti,camerrx-control = <&scm_conf 0x40c0>; - clock-names = "fck"; - clocks = <&k3_clks 2 0>; - power-domains = <&k3_pds 2 TI_SCI_PD_EXCLUSIVE>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - csi2_0: port@0 { - reg = <0>; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/ti/k3-am65-mcu.dtsi b/sys/gnu/dts/arm64/ti/k3-am65-mcu.dtsi deleted file mode 100644 index 92629cbdc18..00000000000 --- a/sys/gnu/dts/arm64/ti/k3-am65-mcu.dtsi +++ /dev/null @@ -1,190 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for AM6 SoC Family MCU Domain peripherals - * - * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/ - */ - -&cbass_mcu { - mcu_conf: scm_conf@40f00000 { - compatible = "syscon", "simple-mfd"; - reg = <0x0 0x40f00000 0x0 0x20000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x40f00000 0x20000>; - }; - - mcu_uart0: serial@40a00000 { - compatible = "ti,am654-uart"; - reg = <0x00 0x40a00000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; - interrupts = ; - clock-frequency = <96000000>; - current-speed = <115200>; - power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; - }; - - mcu_ram: sram@41c00000 { - compatible = "mmio-sram"; - reg = <0x00 0x41c00000 0x00 0x80000>; - ranges = <0x0 0x00 0x41c00000 0x80000>; - #address-cells = <1>; - #size-cells = <1>; - }; - - mcu_i2c0: i2c@40b00000 { - compatible = "ti,am654-i2c", "ti,omap4-i2c"; - reg = <0x0 0x40b00000 0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 114 1>; - power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; - }; - - mcu_spi0: spi@40300000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x0 0x40300000 0x0 0x400>; - interrupts = ; - clocks = <&k3_clks 142 1>; - power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>; - #address-cells = <1>; - #size-cells = <0>; - }; - - mcu_spi1: spi@40310000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x0 0x40310000 0x0 0x400>; - interrupts = ; - clocks = <&k3_clks 143 1>; - power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>; - #address-cells = <1>; - #size-cells = <0>; - }; - - mcu_spi2: spi@40320000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x0 0x40320000 0x0 0x400>; - interrupts = ; - clocks = <&k3_clks 144 1>; - power-domains = <&k3_pds 144 TI_SCI_PD_EXCLUSIVE>; - #address-cells = <1>; - #size-cells = <0>; - }; - - tscadc0: tscadc@40200000 { - compatible = "ti,am654-tscadc", "ti,am3359-tscadc"; - reg = <0x0 0x40200000 0x0 0x1000>; - interrupts = ; - clocks = <&k3_clks 0 2>; - assigned-clocks = <&k3_clks 0 2>; - assigned-clock-rates = <60000000>; - clock-names = "adc_tsc_fck"; - - adc { - #io-channel-cells = <1>; - compatible = "ti,am654-adc", "ti,am3359-adc"; - }; - }; - - tscadc1: tscadc@40210000 { - compatible = "ti,am654-tscadc", "ti,am3359-tscadc"; - reg = <0x0 0x40210000 0x0 0x1000>; - interrupts = ; - clocks = <&k3_clks 1 2>; - assigned-clocks = <&k3_clks 1 2>; - assigned-clock-rates = <60000000>; - clock-names = "adc_tsc_fck"; - - adc { - #io-channel-cells = <1>; - compatible = "ti,am654-adc", "ti,am3359-adc"; - }; - }; - - mcu_navss { - compatible = "simple-mfd"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - dma-coherent; - dma-ranges; - - ti,sci-dev-id = <119>; - - mcu_ringacc: ringacc@2b800000 { - compatible = "ti,am654-navss-ringacc"; - reg = <0x0 0x2b800000 0x0 0x400000>, - <0x0 0x2b000000 0x0 0x400000>, - <0x0 0x28590000 0x0 0x100>, - <0x0 0x2a500000 0x0 0x40000>; - reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; - ti,num-rings = <286>; - ti,sci-rm-range-gp-rings = <0x2>; /* GP ring range */ - ti,dma-ring-reset-quirk; - ti,sci = <&dmsc>; - ti,sci-dev-id = <195>; - msi-parent = <&inta_main_udmass>; - }; - - mcu_udmap: dma-controller@285c0000 { - compatible = "ti,am654-navss-mcu-udmap"; - reg = <0x0 0x285c0000 0x0 0x100>, - <0x0 0x2a800000 0x0 0x40000>, - <0x0 0x2aa00000 0x0 0x40000>; - reg-names = "gcfg", "rchanrt", "tchanrt"; - msi-parent = <&inta_main_udmass>; - #dma-cells = <1>; - - ti,sci = <&dmsc>; - ti,sci-dev-id = <194>; - ti,ringacc = <&mcu_ringacc>; - - ti,sci-rm-range-tchan = <0x1>, /* TX_HCHAN */ - <0x2>; /* TX_CHAN */ - ti,sci-rm-range-rchan = <0x3>, /* RX_HCHAN */ - <0x4>; /* RX_CHAN */ - ti,sci-rm-range-rflow = <0x5>; /* GP RFLOW */ - }; - }; - - fss: fss@47000000 { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - ospi0: spi@47040000 { - compatible = "ti,am654-ospi", "cdns,qspi-nor"; - reg = <0x0 0x47040000 0x0 0x100>, - <0x5 0x00000000 0x1 0x0000000>; - interrupts = ; - cdns,fifo-depth = <256>; - cdns,fifo-width = <4>; - cdns,trigger-address = <0x0>; - clocks = <&k3_clks 248 0>; - assigned-clocks = <&k3_clks 248 0>; - assigned-clock-parents = <&k3_clks 248 2>; - assigned-clock-rates = <166666666>; - power-domains = <&k3_pds 248 TI_SCI_PD_EXCLUSIVE>; - #address-cells = <1>; - #size-cells = <0>; - }; - - ospi1: spi@47050000 { - compatible = "ti,am654-ospi", "cdns,qspi-nor"; - reg = <0x0 0x47050000 0x0 0x100>, - <0x7 0x00000000 0x1 0x00000000>; - interrupts = ; - cdns,fifo-depth = <256>; - cdns,fifo-width = <4>; - cdns,trigger-address = <0x0>; - clocks = <&k3_clks 249 6>; - power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/ti/k3-am65-wakeup.dtsi b/sys/gnu/dts/arm64/ti/k3-am65-wakeup.dtsi deleted file mode 100644 index f4227e2743f..00000000000 --- a/sys/gnu/dts/arm64/ti/k3-am65-wakeup.dtsi +++ /dev/null @@ -1,92 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for AM6 SoC Family Wakeup Domain peripherals - * - * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/ - */ - -&cbass_wakeup { - dmsc: dmsc { - compatible = "ti,am654-sci"; - ti,host-id = <12>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - mbox-names = "rx", "tx"; - - mboxes= <&secure_proxy_main 11>, - <&secure_proxy_main 13>; - - k3_pds: power-controller { - compatible = "ti,sci-pm-domain"; - #power-domain-cells = <2>; - }; - - k3_clks: clocks { - compatible = "ti,k2g-sci-clk"; - #clock-cells = <2>; - }; - - k3_reset: reset-controller { - compatible = "ti,sci-reset"; - #reset-cells = <2>; - }; - }; - - wkup_pmx0: pinmux@4301c000 { - compatible = "pinctrl-single"; - reg = <0x4301c000 0x118>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0xffffffff>; - }; - - wkup_uart0: serial@42300000 { - compatible = "ti,am654-uart"; - reg = <0x42300000 0x100>; - reg-shift = <2>; - reg-io-width = <4>; - interrupts = ; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 150 TI_SCI_PD_EXCLUSIVE>; - }; - - wkup_i2c0: i2c@42120000 { - compatible = "ti,am654-i2c", "ti,omap4-i2c"; - reg = <0x42120000 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 115 1>; - power-domains = <&k3_pds 115 TI_SCI_PD_EXCLUSIVE>; - }; - - intr_wkup_gpio: interrupt-controller2 { - compatible = "ti,sci-intr"; - ti,intr-trigger-type = <1>; - interrupt-controller; - interrupt-parent = <&gic500>; - #interrupt-cells = <2>; - ti,sci = <&dmsc>; - ti,sci-dst-id = <56>; - ti,sci-rm-range-girq = <0x4>; - }; - - wkup_gpio0: wkup_gpio0@42110000 { - compatible = "ti,am654-gpio", "ti,keystone-gpio"; - reg = <0x42110000 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&intr_wkup_gpio>; - interrupts = <59 128>, <59 129>, <59 130>, <59 131>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <56>; - ti,davinci-gpio-unbanked = <0>; - clocks = <&k3_clks 59 0>; - clock-names = "gpio"; - }; -}; diff --git a/sys/gnu/dts/arm64/ti/k3-am65.dtsi b/sys/gnu/dts/arm64/ti/k3-am65.dtsi deleted file mode 100644 index aea36e29dd3..00000000000 --- a/sys/gnu/dts/arm64/ti/k3-am65.dtsi +++ /dev/null @@ -1,122 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for AM6 SoC Family - * - * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/ - */ - -#include -#include -#include -#include -#include - -/ { - model = "Texas Instruments K3 AM654 SoC"; - compatible = "ti,am654"; - interrupt-parent = <&gic500>; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - serial0 = &wkup_uart0; - serial1 = &mcu_uart0; - serial2 = &main_uart0; - serial3 = &main_uart1; - serial4 = &main_uart2; - i2c0 = &wkup_i2c0; - i2c1 = &mcu_i2c0; - i2c2 = &main_i2c0; - i2c3 = &main_i2c1; - i2c4 = &main_i2c2; - i2c5 = &main_i2c3; - }; - - chosen { }; - - firmware { - optee { - compatible = "linaro,optee-tz"; - method = "smc"; - }; - - psci: psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - }; - - a53_timer0: timer-cl0-cpu0 { - compatible = "arm,armv8-timer"; - interrupts = , /* cntpsirq */ - , /* cntpnsirq */ - , /* cntvirq */ - ; /* cnthpirq */ - }; - - pmu: pmu { - compatible = "arm,armv8-pmuv3"; - /* Recommendation from GIC500 TRM Table A.3 */ - interrupts = ; - }; - - cbass_main: interconnect@100000 { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */ - <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */ - <0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */ - <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */ - <0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>, /* MAIN NAVSS */ - <0x00 0x70000000 0x00 0x70000000 0x00 0x00200000>, /* MSMC SRAM */ - <0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */ - /* MCUSS Range */ - <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, - <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>, - <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */ - <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, - <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, - <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>, - <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, - <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, - <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, - <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, - <0x00 0x50000000 0x00 0x50000000 0x00 0x8000000>, - <0x00 0x70000000 0x00 0x70000000 0x00 0x200000>, - <0x05 0x00000000 0x05 0x00000000 0x01 0x0000000>, - <0x07 0x00000000 0x07 0x00000000 0x01 0x0000000>; - - cbass_mcu: interconnect@28380000 { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/ - <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>, /* First peripheral window */ - <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */ - <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */ - <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */ - <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>, /* MCU SRAM */ - <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP */ - <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */ - <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */ - <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI space 1 */ - <0x00 0x50000000 0x00 0x50000000 0x00 0x8000000>, /* FSS OSPI0 data region 1 */ - <0x05 0x00000000 0x05 0x00000000 0x01 0x0000000>, /* FSS OSPI0 data region 3*/ - <0x07 0x00000000 0x07 0x00000000 0x01 0x0000000>; /* FSS OSPI1 data region 3*/ - - cbass_wakeup: interconnect@42040000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - /* WKUP Basic peripherals */ - ranges = <0x42040000 0x00 0x42040000 0x03ac2400>; - }; - }; - }; -}; - -/* Now include the peripherals for each bus segments */ -#include "k3-am65-main.dtsi" -#include "k3-am65-mcu.dtsi" -#include "k3-am65-wakeup.dtsi" diff --git a/sys/gnu/dts/arm64/ti/k3-am654-base-board.dts b/sys/gnu/dts/arm64/ti/k3-am654-base-board.dts deleted file mode 100644 index 1700996800e..00000000000 --- a/sys/gnu/dts/arm64/ti/k3-am654-base-board.dts +++ /dev/null @@ -1,421 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/ - */ - -/dts-v1/; - -#include "k3-am654.dtsi" -#include - -/ { - compatible = "ti,am654-evm", "ti,am654"; - model = "Texas Instruments AM654 Base Board"; - - chosen { - stdout-path = "serial2:115200n8"; - bootargs = "earlycon=ns16550a,mmio32,0x02800000"; - }; - - memory@80000000 { - device_type = "memory"; - /* 4G RAM */ - reg = <0x00000000 0x80000000 0x00000000 0x80000000>, - <0x00000008 0x80000000 0x00000000 0x80000000>; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - secure_ddr: secure_ddr@9e800000 { - reg = <0 0x9e800000 0 0x01800000>; /* for OP-TEE */ - alignment = <0x1000>; - no-map; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - pinctrl-names = "default"; - pinctrl-0 = <&push_button_pins_default>; - - sw5 { - label = "GPIO Key USER1"; - linux,code = ; - gpios = <&wkup_gpio0 24 GPIO_ACTIVE_LOW>; - }; - - sw6 { - label = "GPIO Key USER2"; - linux,code = ; - gpios = <&wkup_gpio0 27 GPIO_ACTIVE_LOW>; - }; - }; - - clk_ov5640_fixed: clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - }; -}; - -&wkup_pmx0 { - wkup_i2c0_pins_default: wkup-i2c0-pins-default { - pinctrl-single,pins = < - AM65X_WKUP_IOPAD(0x00e0, PIN_INPUT, 0) /* (AC7) WKUP_I2C0_SCL */ - AM65X_WKUP_IOPAD(0x00e4, PIN_INPUT, 0) /* (AD6) WKUP_I2C0_SDA */ - >; - }; - - push_button_pins_default: push_button__pins_default { - pinctrl-single,pins = < - AM65X_WKUP_IOPAD(0x0030, PIN_INPUT, 7) /* (R5) WKUP_GPIO0_24 */ - AM65X_WKUP_IOPAD(0x003c, PIN_INPUT, 7) /* (P2) WKUP_GPIO0_27 */ - >; - }; - - mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins_default { - pinctrl-single,pins = < - AM65X_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* (V1) MCU_OSPI0_CLK */ - AM65X_WKUP_IOPAD(0x0008, PIN_INPUT, 0) /* (U2) MCU_OSPI0_DQS */ - AM65X_WKUP_IOPAD(0x000c, PIN_INPUT, 0) /* (U4) MCU_OSPI0_D0 */ - AM65X_WKUP_IOPAD(0x0010, PIN_INPUT, 0) /* (U5) MCU_OSPI0_D1 */ - AM65X_WKUP_IOPAD(0x0014, PIN_INPUT, 0) /* (T2) MCU_OSPI0_D2 */ - AM65X_WKUP_IOPAD(0x0018, PIN_INPUT, 0) /* (T3) MCU_OSPI0_D3 */ - AM65X_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /* (T4) MCU_OSPI0_D4 */ - AM65X_WKUP_IOPAD(0x0020, PIN_INPUT, 0) /* (T5) MCU_OSPI0_D5 */ - AM65X_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* (R2) MCU_OSPI0_D6 */ - AM65X_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* (R3) MCU_OSPI0_D7 */ - AM65X_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* (R4) MCU_OSPI0_CSn0 */ - >; - }; - - wkup_pca554_default: wkup_pca554_default { - pinctrl-single,pins = < - AM65X_WKUP_IOPAD(0x0034, PIN_INPUT, 7) /* (T1) MCU_OSPI1_CLK.WKUP_GPIO0_25 */ - - >; - }; -}; - -&main_pmx0 { - main_uart0_pins_default: main-uart0-pins-default { - pinctrl-single,pins = < - AM65X_IOPAD(0x01e4, PIN_INPUT, 0) /* (AF11) UART0_RXD */ - AM65X_IOPAD(0x01e8, PIN_OUTPUT, 0) /* (AE11) UART0_TXD */ - AM65X_IOPAD(0x01ec, PIN_INPUT, 0) /* (AG11) UART0_CTSn */ - AM65X_IOPAD(0x01f0, PIN_OUTPUT, 0) /* (AD11) UART0_RTSn */ - >; - }; - - main_i2c2_pins_default: main-i2c2-pins-default { - pinctrl-single,pins = < - AM65X_IOPAD(0x0074, PIN_INPUT, 5) /* (T27) GPMC0_CSn3.I2C2_SCL */ - AM65X_IOPAD(0x0070, PIN_INPUT, 5) /* (R25) GPMC0_CSn2.I2C2_SDA */ - >; - }; - - main_spi0_pins_default: main-spi0-pins-default { - pinctrl-single,pins = < - AM65X_IOPAD(0x01c4, PIN_INPUT, 0) /* (AH13) SPI0_CLK */ - AM65X_IOPAD(0x01c8, PIN_INPUT, 0) /* (AE13) SPI0_D0 */ - AM65X_IOPAD(0x01cc, PIN_INPUT, 0) /* (AD13) SPI0_D1 */ - AM65X_IOPAD(0x01bc, PIN_OUTPUT, 0) /* (AG13) SPI0_CS0 */ - >; - }; - - main_mmc0_pins_default: main-mmc0-pins-default { - pinctrl-single,pins = < - AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /* (B25) MMC0_CLK */ - AM65X_IOPAD(0x01ac, PIN_INPUT_PULLUP, 0) /* (B27) MMC0_CMD */ - AM65X_IOPAD(0x01a4, PIN_INPUT_PULLUP, 0) /* (A26) MMC0_DAT0 */ - AM65X_IOPAD(0x01a0, PIN_INPUT_PULLUP, 0) /* (E25) MMC0_DAT1 */ - AM65X_IOPAD(0x019c, PIN_INPUT_PULLUP, 0) /* (C26) MMC0_DAT2 */ - AM65X_IOPAD(0x0198, PIN_INPUT_PULLUP, 0) /* (A25) MMC0_DAT3 */ - AM65X_IOPAD(0x0194, PIN_INPUT_PULLUP, 0) /* (E24) MMC0_DAT4 */ - AM65X_IOPAD(0x0190, PIN_INPUT_PULLUP, 0) /* (A24) MMC0_DAT5 */ - AM65X_IOPAD(0x018c, PIN_INPUT_PULLUP, 0) /* (B26) MMC0_DAT6 */ - AM65X_IOPAD(0x0188, PIN_INPUT_PULLUP, 0) /* (D25) MMC0_DAT7 */ - AM65X_IOPAD(0x01b4, PIN_INPUT_PULLUP, 0) /* (A23) MMC0_SDCD */ - AM65X_IOPAD(0x01b0, PIN_INPUT, 0) /* (C25) MMC0_DS */ - >; - }; - - usb1_pins_default: usb1_pins_default { - pinctrl-single,pins = < - AM65X_IOPAD(0x02c0, PIN_OUTPUT, 0) /* (AC8) USB1_DRVVBUS */ - >; - }; -}; - -&main_pmx1 { - main_i2c0_pins_default: main-i2c0-pins-default { - pinctrl-single,pins = < - AM65X_IOPAD(0x0000, PIN_INPUT, 0) /* (D20) I2C0_SCL */ - AM65X_IOPAD(0x0004, PIN_INPUT, 0) /* (C21) I2C0_SDA */ - >; - }; - - main_i2c1_pins_default: main-i2c1-pins-default { - pinctrl-single,pins = < - AM65X_IOPAD(0x0008, PIN_INPUT, 0) /* (B21) I2C1_SCL */ - AM65X_IOPAD(0x000c, PIN_INPUT, 0) /* (E21) I2C1_SDA */ - >; - }; - - ecap0_pins_default: ecap0-pins-default { - pinctrl-single,pins = < - AM65X_IOPAD(0x0010, PIN_INPUT, 0) /* (D21) ECAP0_IN_APWM_OUT */ - >; - }; -}; - -&wkup_uart0 { - /* Wakeup UART is used by System firmware */ - status = "disabled"; -}; - -&main_uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&main_uart0_pins_default>; - power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>; -}; - -&wkup_i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&wkup_i2c0_pins_default>; - clock-frequency = <400000>; - - pca9554: gpio@39 { - compatible = "nxp,pca9554"; - reg = <0x39>; - gpio-controller; - #gpio-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&wkup_pca554_default>; - interrupt-parent = <&wkup_gpio0>; - interrupts = <25 IRQ_TYPE_EDGE_FALLING>; - interrupt-controller; - #interrupt-cells = <2>; - }; -}; - -&main_i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c0_pins_default>; - clock-frequency = <400000>; - - pca9555: gpio@21 { - compatible = "nxp,pca9555"; - reg = <0x21>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -&main_i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c1_pins_default>; - clock-frequency = <400000>; - - ov5640@3c { - compatible = "ovti,ov5640"; - reg = <0x3c>; - - clocks = <&clk_ov5640_fixed>; - clock-names = "xclk"; - - port { - csi2_cam0: endpoint { - remote-endpoint = <&csi2_phy0>; - clock-lanes = <0>; - data-lanes = <1 2>; - }; - }; - }; - -}; - -&main_i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c2_pins_default>; - clock-frequency = <400000>; -}; - -&ecap0 { - pinctrl-names = "default"; - pinctrl-0 = <&ecap0_pins_default>; -}; - -&main_spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&main_spi0_pins_default>; - #address-cells = <1>; - #size-cells= <0>; - ti,pindir-d0-out-d1-in = <1>; - - flash@0{ - compatible = "jedec,spi-nor"; - reg = <0x0>; - spi-tx-bus-width = <1>; - spi-rx-bus-width = <1>; - spi-max-frequency = <48000000>; - #address-cells = <1>; - #size-cells= <1>; - }; -}; - -&sdhci0 { - pinctrl-names = "default"; - pinctrl-0 = <&main_mmc0_pins_default>; - bus-width = <8>; - non-removable; - ti,driver-strength-ohm = <50>; - disable-wp; -}; - -&dwc3_1 { - status = "okay"; -}; - -&usb1_phy { - status = "okay"; -}; - -&usb1 { - pinctrl-names = "default"; - pinctrl-0 = <&usb1_pins_default>; - dr_mode = "otg"; -}; - -&dwc3_0 { - status = "disabled"; -}; - -&usb0_phy { - status = "disabled"; -}; - -&tscadc0 { - adc { - ti,adc-channels = <0 1 2 3 4 5 6 7>; - }; -}; - -&tscadc1 { - adc { - ti,adc-channels = <0 1 2 3 4 5 6 7>; - }; -}; - -&serdes0 { - status = "disabled"; -}; - -&serdes1 { - status = "disabled"; -}; - -&pcie0_rc { - status = "disabled"; -}; - -&pcie0_ep { - status = "disabled"; -}; - -&pcie1_rc { - status = "disabled"; -}; - -&pcie1_ep { - status = "disabled"; -}; - -&mailbox0_cluster0 { - interrupts = <164 0>; - - mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { - ti,mbox-tx = <1 0 0>; - ti,mbox-rx = <0 0 0>; - }; -}; - -&mailbox0_cluster1 { - interrupts = <165 0>; - - mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { - ti,mbox-tx = <1 0 0>; - ti,mbox-rx = <0 0 0>; - }; -}; - -&mailbox0_cluster2 { - status = "disabled"; -}; - -&mailbox0_cluster3 { - status = "disabled"; -}; - -&mailbox0_cluster4 { - status = "disabled"; -}; - -&mailbox0_cluster5 { - status = "disabled"; -}; - -&mailbox0_cluster6 { - status = "disabled"; -}; - -&mailbox0_cluster7 { - status = "disabled"; -}; - -&mailbox0_cluster8 { - status = "disabled"; -}; - -&mailbox0_cluster9 { - status = "disabled"; -}; - -&mailbox0_cluster10 { - status = "disabled"; -}; - -&mailbox0_cluster11 { - status = "disabled"; -}; - -&ospi0 { - pinctrl-names = "default"; - pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; - - flash@0{ - compatible = "jedec,spi-nor"; - reg = <0x0>; - spi-tx-bus-width = <1>; - spi-rx-bus-width = <8>; - spi-max-frequency = <40000000>; - cdns,tshsl-ns = <60>; - cdns,tsd2d-ns = <60>; - cdns,tchsh-ns = <60>; - cdns,tslch-ns = <60>; - cdns,read-delay = <0>; - #address-cells = <1>; - #size-cells = <1>; - }; -}; - -&csi2_0 { - csi2_phy0: endpoint { - remote-endpoint = <&csi2_cam0>; - clock-lanes = <0>; - data-lanes = <1 2>; - }; -}; diff --git a/sys/gnu/dts/arm64/ti/k3-am654.dtsi b/sys/gnu/dts/arm64/ti/k3-am654.dtsi deleted file mode 100644 index b221abf43ac..00000000000 --- a/sys/gnu/dts/arm64/ti/k3-am654.dtsi +++ /dev/null @@ -1,115 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for AM6 SoC family in Quad core configuration - * - * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/ - */ - -#include "k3-am65.dtsi" - -/ { - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu-map { - cluster0: cluster0 { - core0 { - cpu = <&cpu0>; - }; - - core1 { - cpu = <&cpu1>; - }; - }; - - cluster1: cluster1 { - core0 { - cpu = <&cpu2>; - }; - - core1 { - cpu = <&cpu3>; - }; - }; - }; - - cpu0: cpu@0 { - compatible = "arm,cortex-a53"; - reg = <0x000>; - device_type = "cpu"; - enable-method = "psci"; - i-cache-size = <0x8000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - next-level-cache = <&L2_0>; - }; - - cpu1: cpu@1 { - compatible = "arm,cortex-a53"; - reg = <0x001>; - device_type = "cpu"; - enable-method = "psci"; - i-cache-size = <0x8000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - next-level-cache = <&L2_0>; - }; - - cpu2: cpu@100 { - compatible = "arm,cortex-a53"; - reg = <0x100>; - device_type = "cpu"; - enable-method = "psci"; - i-cache-size = <0x8000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - next-level-cache = <&L2_1>; - }; - - cpu3: cpu@101 { - compatible = "arm,cortex-a53"; - reg = <0x101>; - device_type = "cpu"; - enable-method = "psci"; - i-cache-size = <0x8000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - next-level-cache = <&L2_1>; - }; - }; - - L2_0: l2-cache0 { - compatible = "cache"; - cache-level = <2>; - cache-size = <0x80000>; - cache-line-size = <64>; - cache-sets = <512>; - next-level-cache = <&msmc_l3>; - }; - - L2_1: l2-cache1 { - compatible = "cache"; - cache-level = <2>; - cache-size = <0x80000>; - cache-line-size = <64>; - cache-sets = <512>; - next-level-cache = <&msmc_l3>; - }; - - msmc_l3: l3-cache0 { - compatible = "cache"; - cache-level = <3>; - }; -}; diff --git a/sys/gnu/dts/arm64/ti/k3-j721e-common-proc-board.dts b/sys/gnu/dts/arm64/ti/k3-j721e-common-proc-board.dts deleted file mode 100644 index 7a5c3d4adad..00000000000 --- a/sys/gnu/dts/arm64/ti/k3-j721e-common-proc-board.dts +++ /dev/null @@ -1,431 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ - */ - -/dts-v1/; - -#include "k3-j721e-som-p0.dtsi" -#include -#include - -/ { - chosen { - stdout-path = "serial2:115200n8"; - bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000"; - }; - - gpio_keys: gpio-keys { - compatible = "gpio-keys"; - autorepeat; - pinctrl-names = "default"; - pinctrl-0 = <&sw10_button_pins_default &sw11_button_pins_default>; - - sw10: sw10 { - label = "GPIO Key USER1"; - linux,code = ; - gpios = <&main_gpio0 0 GPIO_ACTIVE_LOW>; - }; - - sw11: sw11 { - label = "GPIO Key USER2"; - linux,code = ; - gpios = <&wkup_gpio0 7 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&main_pmx0 { - sw10_button_pins_default: sw10_button_pins_default { - pinctrl-single,pins = < - J721E_IOPAD(0x0, PIN_INPUT, 7) /* (AC18) EXTINTn.GPIO0_0 */ - >; - }; - - main_mmc1_pins_default: main_mmc1_pins_default { - pinctrl-single,pins = < - J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */ - J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */ - J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */ - J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */ - J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */ - J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */ - J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */ - J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */ - J721E_IOPAD(0x25c, PIN_INPUT, 0) /* (R28) MMC1_SDWP */ - >; - }; - - main_usbss0_pins_default: main_usbss0_pins_default { - pinctrl-single,pins = < - J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */ - >; - }; - - main_usbss1_pins_default: main_usbss1_pins_default { - pinctrl-single,pins = < - J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */ - >; - }; - - main_i2c1_exp4_pins_default: main-i2c1-exp4-pins-default { - pinctrl-single,pins = < - J721E_IOPAD(0x230, PIN_INPUT, 7) /* (U2) ECAP0_IN_APWM_OUT.GPIO1_11 */ - >; - }; - - main_i2c0_pins_default: main-i2c0-pins-default { - pinctrl-single,pins = < - J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */ - J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */ - >; - }; - - main_i2c1_pins_default: main-i2c1-pins-default { - pinctrl-single,pins = < - J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */ - J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */ - >; - }; - - main_i2c3_pins_default: main-i2c3-pins-default { - pinctrl-single,pins = < - J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */ - J721E_IOPAD(0x274, PIN_INPUT_PULLUP, 4) /* (T25) MMC2_CMD.I2C3_SDA */ - >; - }; - - main_i2c6_pins_default: main-i2c6-pins-default { - pinctrl-single,pins = < - J721E_IOPAD(0x1d0, PIN_INPUT_PULLUP, 2) /* (AA3) SPI0_D1.I2C6_SCL */ - J721E_IOPAD(0x1e4, PIN_INPUT_PULLUP, 2) /* (Y2) SPI1_D1.I2C6_SDA */ - >; - }; - - main_i2c1_exp4_pins_default: main-i2c1-exp4-pins-default { - pinctrl-single,pins = < - J721E_IOPAD(0x230, PIN_INPUT, 7) /* (U2) ECAP0_IN_APWM_OUT.GPIO1_11 */ - >; - }; -}; - -&wkup_pmx0 { - sw11_button_pins_default: sw11_button_pins_default { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0xcc, PIN_INPUT, 7) /* (G28) WKUP_GPIO0_7 */ - >; - }; - - mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-pins-default { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0x34, PIN_OUTPUT, 0) /* (F22) MCU_OSPI1_CLK */ - J721E_WKUP_IOPAD(0x50, PIN_OUTPUT, 0) /* (C22) MCU_OSPI1_CSn0 */ - J721E_WKUP_IOPAD(0x40, PIN_INPUT, 0) /* (D22) MCU_OSPI1_D0 */ - J721E_WKUP_IOPAD(0x44, PIN_INPUT, 0) /* (G22) MCU_OSPI1_D1 */ - J721E_WKUP_IOPAD(0x48, PIN_INPUT, 0) /* (D23) MCU_OSPI1_D2 */ - J721E_WKUP_IOPAD(0x4c, PIN_INPUT, 0) /* (C23) MCU_OSPI1_D3 */ - J721E_WKUP_IOPAD(0x3c, PIN_INPUT, 0) /* (B23) MCU_OSPI1_DQS */ - J721E_WKUP_IOPAD(0x38, PIN_INPUT, 0) /* (A23) MCU_OSPI1_LBCLKO */ - >; - }; -}; - -&wkup_uart0 { - /* Wakeup UART is used by System firmware */ - status = "disabled"; -}; - -&main_uart0 { - power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>; -}; - -&main_uart3 { - /* UART not brought out */ - status = "disabled"; -}; - -&main_uart5 { - /* UART not brought out */ - status = "disabled"; -}; - -&main_uart6 { - /* UART not brought out */ - status = "disabled"; -}; - -&main_uart7 { - /* UART not brought out */ - status = "disabled"; -}; - -&main_uart8 { - /* UART not brought out */ - status = "disabled"; -}; - -&main_uart9 { - /* UART not brought out */ - status = "disabled"; -}; - -&main_gpio2 { - status = "disabled"; -}; - -&main_gpio3 { - status = "disabled"; -}; - -&main_gpio4 { - status = "disabled"; -}; - -&main_gpio5 { - status = "disabled"; -}; - -&main_gpio6 { - status = "disabled"; -}; - -&main_gpio7 { - status = "disabled"; -}; - -&wkup_gpio1 { - status = "disabled"; -}; - -&mailbox0_cluster0 { - interrupts = <214 0>; - - mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster1 { - interrupts = <215 0>; - - mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster2 { - interrupts = <216 0>; - - mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster3 { - interrupts = <217 0>; - - mbox_c66_0: mbox-c66-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_c66_1: mbox-c66-1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster4 { - interrupts = <218 0>; - - mbox_c71_0: mbox-c71-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; -}; - -&mailbox0_cluster5 { - status = "disabled"; -}; - -&mailbox0_cluster6 { - status = "disabled"; -}; - -&mailbox0_cluster7 { - status = "disabled"; -}; - -&mailbox0_cluster8 { - status = "disabled"; -}; - -&mailbox0_cluster9 { - status = "disabled"; -}; - -&mailbox0_cluster10 { - status = "disabled"; -}; - -&mailbox0_cluster11 { - status = "disabled"; -}; - -&main_sdhci0 { - /* eMMC */ - non-removable; - ti,driver-strength-ohm = <50>; - disable-wp; -}; - -&main_sdhci1 { - /* SD/MMC */ - pinctrl-names = "default"; - pinctrl-0 = <&main_mmc1_pins_default>; - ti,driver-strength-ohm = <50>; - disable-wp; -}; - -&main_sdhci2 { - /* Unused */ - status = "disabled"; -}; - -&usbss0 { - pinctrl-names = "default"; - pinctrl-0 = <&main_usbss0_pins_default>; - ti,usb2-only; - ti,vbus-divider; -}; - -&usb0 { - dr_mode = "otg"; - maximum-speed = "high-speed"; -}; - -&usbss1 { - pinctrl-names = "default"; - pinctrl-0 = <&main_usbss1_pins_default>; - ti,usb2-only; -}; - -&usb1 { - dr_mode = "host"; - maximum-speed = "high-speed"; -}; - -&ospi1 { - pinctrl-names = "default"; - pinctrl-0 = <&mcu_fss0_ospi1_pins_default>; - - flash@0{ - compatible = "jedec,spi-nor"; - reg = <0x0>; - spi-tx-bus-width = <1>; - spi-rx-bus-width = <4>; - spi-max-frequency = <40000000>; - cdns,tshsl-ns = <60>; - cdns,tsd2d-ns = <60>; - cdns,tchsh-ns = <60>; - cdns,tslch-ns = <60>; - cdns,read-delay = <2>; - #address-cells = <1>; - #size-cells = <1>; - }; -}; - -&tscadc0 { - adc { - ti,adc-channels = <0 1 2 3 4 5 6 7>; - }; -}; - -&tscadc1 { - adc { - ti,adc-channels = <0 1 2 3 4 5 6 7>; - }; -}; - -&main_i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c0_pins_default>; - clock-frequency = <400000>; - - exp1: gpio@20 { - compatible = "ti,tca6416"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - }; - - exp2: gpio@22 { - compatible = "ti,tca6424"; - reg = <0x22>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -&main_i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c1_pins_default>; - clock-frequency = <400000>; - - exp4: gpio@20 { - compatible = "ti,tca6408"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c1_exp4_pins_default>; - interrupt-parent = <&main_gpio1>; - interrupts = <11 IRQ_TYPE_EDGE_FALLING>; - interrupt-controller; - #interrupt-cells = <2>; - }; -}; - -&main_i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c3_pins_default>; - clock-frequency = <400000>; - - exp3: gpio@20 { - compatible = "ti,tca6408"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -&main_i2c6 { - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c6_pins_default>; - clock-frequency = <400000>; - - exp5: gpio@20 { - compatible = "ti,tca6408"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - }; -}; diff --git a/sys/gnu/dts/arm64/ti/k3-j721e-main.dtsi b/sys/gnu/dts/arm64/ti/k3-j721e-main.dtsi deleted file mode 100644 index 0b9d14b838a..00000000000 --- a/sys/gnu/dts/arm64/ti/k3-j721e-main.dtsi +++ /dev/null @@ -1,966 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for J721E SoC Family Main Domain peripherals - * - * Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/ - */ - -&cbass_main { - msmc_ram: sram@70000000 { - compatible = "mmio-sram"; - reg = <0x0 0x70000000 0x0 0x800000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x70000000 0x800000>; - - atf-sram@0 { - reg = <0x0 0x20000>; - }; - }; - - gic500: interrupt-controller@1800000 { - compatible = "arm,gic-v3"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ - <0x00 0x01900000 0x00 0x100000>; /* GICR */ - - /* vcpumntirq: virtual CPU interface maintenance interrupt */ - interrupts = ; - - gic_its: gic-its@1820000 { - compatible = "arm,gic-v3-its"; - reg = <0x00 0x01820000 0x00 0x10000>; - socionext,synquacer-pre-its = <0x1000000 0x400000>; - msi-controller; - #msi-cells = <1>; - }; - }; - - main_gpio_intr: interrupt-controller0 { - compatible = "ti,sci-intr"; - ti,intr-trigger-type = <1>; - interrupt-controller; - interrupt-parent = <&gic500>; - #interrupt-cells = <2>; - ti,sci = <&dmsc>; - ti,sci-dst-id = <14>; - ti,sci-rm-range-girq = <0x1>; - }; - - main_navss { - compatible = "simple-mfd"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - dma-coherent; - dma-ranges; - - ti,sci-dev-id = <199>; - - main_navss_intr: interrupt-controller1 { - compatible = "ti,sci-intr"; - ti,intr-trigger-type = <4>; - interrupt-controller; - interrupt-parent = <&gic500>; - #interrupt-cells = <2>; - ti,sci = <&dmsc>; - ti,sci-dst-id = <14>; - ti,sci-rm-range-girq = <0>, <2>; - }; - - main_udmass_inta: interrupt-controller@33d00000 { - compatible = "ti,sci-inta"; - reg = <0x0 0x33d00000 0x0 0x100000>; - interrupt-controller; - interrupt-parent = <&main_navss_intr>; - msi-controller; - ti,sci = <&dmsc>; - ti,sci-dev-id = <209>; - ti,sci-rm-range-vint = <0xa>; - ti,sci-rm-range-global-event = <0xd>; - }; - - secure_proxy_main: mailbox@32c00000 { - compatible = "ti,am654-secure-proxy"; - #mbox-cells = <1>; - reg-names = "target_data", "rt", "scfg"; - reg = <0x00 0x32c00000 0x00 0x100000>, - <0x00 0x32400000 0x00 0x100000>, - <0x00 0x32800000 0x00 0x100000>; - interrupt-names = "rx_011"; - interrupts = ; - }; - - smmu0: smmu@36600000 { - compatible = "arm,smmu-v3"; - reg = <0x0 0x36600000 0x0 0x100000>; - interrupt-parent = <&gic500>; - interrupts = , - ; - interrupt-names = "eventq", "gerror"; - #iommu-cells = <1>; - }; - - hwspinlock: spinlock@30e00000 { - compatible = "ti,am654-hwspinlock"; - reg = <0x00 0x30e00000 0x00 0x1000>; - #hwlock-cells = <1>; - }; - - mailbox0_cluster0: mailbox@31f80000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f80000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - }; - - mailbox0_cluster1: mailbox@31f81000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f81000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - }; - - mailbox0_cluster2: mailbox@31f82000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f82000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - }; - - mailbox0_cluster3: mailbox@31f83000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f83000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - }; - - mailbox0_cluster4: mailbox@31f84000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f84000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - }; - - mailbox0_cluster5: mailbox@31f85000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f85000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - }; - - mailbox0_cluster6: mailbox@31f86000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f86000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - }; - - mailbox0_cluster7: mailbox@31f87000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f87000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - }; - - mailbox0_cluster8: mailbox@31f88000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f88000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - }; - - mailbox0_cluster9: mailbox@31f89000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f89000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - }; - - mailbox0_cluster10: mailbox@31f8a000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f8a000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - }; - - mailbox0_cluster11: mailbox@31f8b000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f8b000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - }; - - main_ringacc: ringacc@3c000000 { - compatible = "ti,am654-navss-ringacc"; - reg = <0x0 0x3c000000 0x0 0x400000>, - <0x0 0x38000000 0x0 0x400000>, - <0x0 0x31120000 0x0 0x100>, - <0x0 0x33000000 0x0 0x40000>; - reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; - ti,num-rings = <1024>; - ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ - ti,sci = <&dmsc>; - ti,sci-dev-id = <211>; - msi-parent = <&main_udmass_inta>; - }; - - main_udmap: dma-controller@31150000 { - compatible = "ti,j721e-navss-main-udmap"; - reg = <0x0 0x31150000 0x0 0x100>, - <0x0 0x34000000 0x0 0x100000>, - <0x0 0x35000000 0x0 0x100000>; - reg-names = "gcfg", "rchanrt", "tchanrt"; - msi-parent = <&main_udmass_inta>; - #dma-cells = <1>; - - ti,sci = <&dmsc>; - ti,sci-dev-id = <212>; - ti,ringacc = <&main_ringacc>; - - ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ - <0x0f>, /* TX_HCHAN */ - <0x10>; /* TX_UHCHAN */ - ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ - <0x0b>, /* RX_HCHAN */ - <0x0c>; /* RX_UHCHAN */ - ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ - }; - }; - - main_pmx0: pinmux@11c000 { - compatible = "pinctrl-single"; - /* Proxy 0 addressing */ - reg = <0x0 0x11c000 0x0 0x2b4>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0xffffffff>; - }; - - main_uart0: serial@2800000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02800000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; - interrupts = ; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 146 0>; - clock-names = "fclk"; - }; - - main_uart1: serial@2810000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02810000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; - interrupts = ; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 278 0>; - clock-names = "fclk"; - }; - - main_uart2: serial@2820000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02820000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; - interrupts = ; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 279 0>; - clock-names = "fclk"; - }; - - main_uart3: serial@2830000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02830000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; - interrupts = ; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 280 0>; - clock-names = "fclk"; - }; - - main_uart4: serial@2840000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02840000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; - interrupts = ; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 281 0>; - clock-names = "fclk"; - }; - - main_uart5: serial@2850000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02850000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; - interrupts = ; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 282 0>; - clock-names = "fclk"; - }; - - main_uart6: serial@2860000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02860000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; - interrupts = ; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 283 0>; - clock-names = "fclk"; - }; - - main_uart7: serial@2870000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02870000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; - interrupts = ; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 284 0>; - clock-names = "fclk"; - }; - - main_uart8: serial@2880000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02880000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; - interrupts = ; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 285 0>; - clock-names = "fclk"; - }; - - main_uart9: serial@2890000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02890000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; - interrupts = ; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 286 0>; - clock-names = "fclk"; - }; - - main_gpio0: gpio@600000 { - compatible = "ti,j721e-gpio", "ti,keystone-gpio"; - reg = <0x0 0x00600000 0x0 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&main_gpio_intr>; - interrupts = <105 0>, <105 1>, <105 2>, <105 3>, - <105 4>, <105 5>, <105 6>, <105 7>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <128>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 105 0>; - clock-names = "gpio"; - }; - - main_gpio1: gpio@601000 { - compatible = "ti,j721e-gpio", "ti,keystone-gpio"; - reg = <0x0 0x00601000 0x0 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&main_gpio_intr>; - interrupts = <106 0>, <106 1>, <106 2>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <36>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 106 0>; - clock-names = "gpio"; - }; - - main_gpio2: gpio@610000 { - compatible = "ti,j721e-gpio", "ti,keystone-gpio"; - reg = <0x0 0x00610000 0x0 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&main_gpio_intr>; - interrupts = <107 0>, <107 1>, <107 2>, <107 3>, - <107 4>, <107 5>, <107 6>, <107 7>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <128>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 107 0>; - clock-names = "gpio"; - }; - - main_gpio3: gpio@611000 { - compatible = "ti,j721e-gpio", "ti,keystone-gpio"; - reg = <0x0 0x00611000 0x0 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&main_gpio_intr>; - interrupts = <108 0>, <108 1>, <108 2>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <36>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 108 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 108 0>; - clock-names = "gpio"; - }; - - main_gpio4: gpio@620000 { - compatible = "ti,j721e-gpio", "ti,keystone-gpio"; - reg = <0x0 0x00620000 0x0 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&main_gpio_intr>; - interrupts = <109 0>, <109 1>, <109 2>, <109 3>, - <109 4>, <109 5>, <109 6>, <109 7>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <128>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 109 0>; - clock-names = "gpio"; - }; - - main_gpio5: gpio@621000 { - compatible = "ti,j721e-gpio", "ti,keystone-gpio"; - reg = <0x0 0x00621000 0x0 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&main_gpio_intr>; - interrupts = <110 0>, <110 1>, <110 2>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <36>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 110 0>; - clock-names = "gpio"; - }; - - main_gpio6: gpio@630000 { - compatible = "ti,j721e-gpio", "ti,keystone-gpio"; - reg = <0x0 0x00630000 0x0 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&main_gpio_intr>; - interrupts = <111 0>, <111 1>, <111 2>, <111 3>, - <111 4>, <111 5>, <111 6>, <111 7>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <128>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 111 0>; - clock-names = "gpio"; - }; - - main_gpio7: gpio@631000 { - compatible = "ti,j721e-gpio", "ti,keystone-gpio"; - reg = <0x0 0x00631000 0x0 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&main_gpio_intr>; - interrupts = <112 0>, <112 1>, <112 2>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <36>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 112 0>; - clock-names = "gpio"; - }; - - main_sdhci0: sdhci@4f80000 { - compatible = "ti,j721e-sdhci-8bit"; - reg = <0x0 0x4f80000 0x0 0x1000>, <0x0 0x4f88000 0x0 0x400>; - interrupts = ; - power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; - clock-names = "clk_xin", "clk_ahb"; - clocks = <&k3_clks 91 1>, <&k3_clks 91 0>; - assigned-clocks = <&k3_clks 91 1>; - assigned-clock-parents = <&k3_clks 91 2>; - bus-width = <8>; - mmc-hs400-1_8v; - mmc-ddr-1_8v; - ti,otap-del-sel = <0x2>; - ti,trm-icp = <0x8>; - ti,strobe-sel = <0x77>; - dma-coherent; - }; - - main_sdhci1: sdhci@4fb0000 { - compatible = "ti,j721e-sdhci-4bit"; - reg = <0x0 0x04fb0000 0x0 0x1000>, <0x0 0x4fb8000 0x0 0x400>; - interrupts = ; - power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>; - clock-names = "clk_xin", "clk_ahb"; - clocks = <&k3_clks 92 0>, <&k3_clks 92 5>; - assigned-clocks = <&k3_clks 92 0>; - assigned-clock-parents = <&k3_clks 92 1>; - ti,otap-del-sel = <0x2>; - ti,trm-icp = <0x8>; - ti,clkbuf-sel = <0x7>; - dma-coherent; - no-1-8-v; - }; - - main_sdhci2: sdhci@4f98000 { - compatible = "ti,j721e-sdhci-4bit"; - reg = <0x0 0x4f98000 0x0 0x1000>, <0x0 0x4f90000 0x0 0x400>; - interrupts = ; - power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>; - clock-names = "clk_xin", "clk_ahb"; - clocks = <&k3_clks 93 0>, <&k3_clks 93 5>; - assigned-clocks = <&k3_clks 93 0>; - assigned-clock-parents = <&k3_clks 93 1>; - ti,otap-del-sel = <0x2>; - ti,trm-icp = <0x8>; - ti,clkbuf-sel = <0x7>; - dma-coherent; - no-1-8-v; - }; - - usbss0: cdns_usb@4104000 { - compatible = "ti,j721e-usb"; - reg = <0x00 0x4104000 0x00 0x100>; - dma-coherent; - power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 288 15>, <&k3_clks 288 3>; - clock-names = "ref", "lpm"; - assigned-clocks = <&k3_clks 288 15>; /* USB2_REFCLK */ - assigned-clock-parents = <&k3_clks 288 16>; /* HFOSC0 */ - #address-cells = <2>; - #size-cells = <2>; - ranges; - - usb0: usb@6000000 { - compatible = "cdns,usb3"; - reg = <0x00 0x6000000 0x00 0x10000>, - <0x00 0x6010000 0x00 0x10000>, - <0x00 0x6020000 0x00 0x10000>; - reg-names = "otg", "xhci", "dev"; - interrupts = , /* irq.0 */ - , /* irq.6 */ - ; /* otgirq.0 */ - interrupt-names = "host", - "peripheral", - "otg"; - maximum-speed = "super-speed"; - dr_mode = "otg"; - }; - }; - - usbss1: cdns_usb@4114000 { - compatible = "ti,j721e-usb"; - reg = <0x00 0x4114000 0x00 0x100>; - dma-coherent; - power-domains = <&k3_pds 289 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 289 15>, <&k3_clks 289 3>; - clock-names = "ref", "lpm"; - assigned-clocks = <&k3_clks 289 15>; /* USB2_REFCLK */ - assigned-clock-parents = <&k3_clks 289 16>; /* HFOSC0 */ - #address-cells = <2>; - #size-cells = <2>; - ranges; - - usb1: usb@6400000 { - compatible = "cdns,usb3"; - reg = <0x00 0x6400000 0x00 0x10000>, - <0x00 0x6410000 0x00 0x10000>, - <0x00 0x6420000 0x00 0x10000>; - reg-names = "otg", "xhci", "dev"; - interrupts = , /* irq.0 */ - , /* irq.6 */ - ; /* otgirq.0 */ - interrupt-names = "host", - "peripheral", - "otg"; - maximum-speed = "super-speed"; - dr_mode = "otg"; - }; - }; - - main_i2c0: i2c@2000000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x0 0x2000000 0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 187 0>; - power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>; - }; - - main_i2c1: i2c@2010000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x0 0x2010000 0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 188 0>; - power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>; - }; - - main_i2c2: i2c@2020000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x0 0x2020000 0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 189 0>; - power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>; - }; - - main_i2c3: i2c@2030000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x0 0x2030000 0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 190 0>; - power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; - }; - - main_i2c4: i2c@2040000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x0 0x2040000 0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 191 0>; - power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; - }; - - main_i2c5: i2c@2050000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x0 0x2050000 0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 192 0>; - power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; - }; - - main_i2c6: i2c@2060000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x0 0x2060000 0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 193 0>; - power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>; - }; - - ufs_wrapper: ufs-wrapper@4e80000 { - compatible = "ti,j721e-ufs"; - reg = <0x0 0x4e80000 0x0 0x100>; - power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 277 1>; - assigned-clocks = <&k3_clks 277 1>; - assigned-clock-parents = <&k3_clks 277 4>; - ranges; - #address-cells = <2>; - #size-cells = <2>; - - ufs@4e84000 { - compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0"; - reg = <0x0 0x4e84000 0x0 0x10000>; - interrupts = ; - freq-table-hz = <250000000 250000000>, <19200000 19200000>, <19200000 19200000>; - clocks = <&k3_clks 277 0>, <&k3_clks 277 1>, <&k3_clks 277 1>; - clock-names = "core_clk", "phy_clk", "ref_clk"; - dma-coherent; - }; - }; - - mcasp0: mcasp@2b00000 { - compatible = "ti,am33xx-mcasp-audio"; - reg = <0x0 0x02b00000 0x0 0x2000>, - <0x0 0x02b08000 0x0 0x1000>; - reg-names = "mpu","dat"; - interrupts = , - ; - interrupt-names = "tx", "rx"; - - dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>; - dma-names = "tx", "rx"; - - clocks = <&k3_clks 174 1>; - clock-names = "fck"; - power-domains = <&k3_pds 174 TI_SCI_PD_EXCLUSIVE>; - - status = "disabled"; - }; - - mcasp1: mcasp@2b10000 { - compatible = "ti,am33xx-mcasp-audio"; - reg = <0x0 0x02b10000 0x0 0x2000>, - <0x0 0x02b18000 0x0 0x1000>; - reg-names = "mpu","dat"; - interrupts = , - ; - interrupt-names = "tx", "rx"; - - dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>; - dma-names = "tx", "rx"; - - clocks = <&k3_clks 175 1>; - clock-names = "fck"; - power-domains = <&k3_pds 175 TI_SCI_PD_EXCLUSIVE>; - - status = "disabled"; - }; - - mcasp2: mcasp@2b20000 { - compatible = "ti,am33xx-mcasp-audio"; - reg = <0x0 0x02b20000 0x0 0x2000>, - <0x0 0x02b28000 0x0 0x1000>; - reg-names = "mpu","dat"; - interrupts = , - ; - interrupt-names = "tx", "rx"; - - dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>; - dma-names = "tx", "rx"; - - clocks = <&k3_clks 176 1>; - clock-names = "fck"; - power-domains = <&k3_pds 176 TI_SCI_PD_EXCLUSIVE>; - - status = "disabled"; - }; - - mcasp3: mcasp@2b30000 { - compatible = "ti,am33xx-mcasp-audio"; - reg = <0x0 0x02b30000 0x0 0x2000>, - <0x0 0x02b38000 0x0 0x1000>; - reg-names = "mpu","dat"; - interrupts = , - ; - interrupt-names = "tx", "rx"; - - dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>; - dma-names = "tx", "rx"; - - clocks = <&k3_clks 177 1>; - clock-names = "fck"; - power-domains = <&k3_pds 177 TI_SCI_PD_EXCLUSIVE>; - - status = "disabled"; - }; - - mcasp4: mcasp@2b40000 { - compatible = "ti,am33xx-mcasp-audio"; - reg = <0x0 0x02b40000 0x0 0x2000>, - <0x0 0x02b48000 0x0 0x1000>; - reg-names = "mpu","dat"; - interrupts = , - ; - interrupt-names = "tx", "rx"; - - dmas = <&main_udmap 0xc501>, <&main_udmap 0x4501>; - dma-names = "tx", "rx"; - - clocks = <&k3_clks 178 1>; - clock-names = "fck"; - power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>; - - status = "disabled"; - }; - - mcasp5: mcasp@2b50000 { - compatible = "ti,am33xx-mcasp-audio"; - reg = <0x0 0x02b50000 0x0 0x2000>, - <0x0 0x02b58000 0x0 0x1000>; - reg-names = "mpu","dat"; - interrupts = , - ; - interrupt-names = "tx", "rx"; - - dmas = <&main_udmap 0xc502>, <&main_udmap 0x4502>; - dma-names = "tx", "rx"; - - clocks = <&k3_clks 179 1>; - clock-names = "fck"; - power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>; - - status = "disabled"; - }; - - mcasp6: mcasp@2b60000 { - compatible = "ti,am33xx-mcasp-audio"; - reg = <0x0 0x02b60000 0x0 0x2000>, - <0x0 0x02b68000 0x0 0x1000>; - reg-names = "mpu","dat"; - interrupts = , - ; - interrupt-names = "tx", "rx"; - - dmas = <&main_udmap 0xc503>, <&main_udmap 0x4503>; - dma-names = "tx", "rx"; - - clocks = <&k3_clks 180 1>; - clock-names = "fck"; - power-domains = <&k3_pds 180 TI_SCI_PD_EXCLUSIVE>; - - status = "disabled"; - }; - - mcasp7: mcasp@2b70000 { - compatible = "ti,am33xx-mcasp-audio"; - reg = <0x0 0x02b70000 0x0 0x2000>, - <0x0 0x02b78000 0x0 0x1000>; - reg-names = "mpu","dat"; - interrupts = , - ; - interrupt-names = "tx", "rx"; - - dmas = <&main_udmap 0xc504>, <&main_udmap 0x4504>; - dma-names = "tx", "rx"; - - clocks = <&k3_clks 181 1>; - clock-names = "fck"; - power-domains = <&k3_pds 181 TI_SCI_PD_EXCLUSIVE>; - - status = "disabled"; - }; - - mcasp8: mcasp@2b80000 { - compatible = "ti,am33xx-mcasp-audio"; - reg = <0x0 0x02b80000 0x0 0x2000>, - <0x0 0x02b88000 0x0 0x1000>; - reg-names = "mpu","dat"; - interrupts = , - ; - interrupt-names = "tx", "rx"; - - dmas = <&main_udmap 0xc505>, <&main_udmap 0x4505>; - dma-names = "tx", "rx"; - - clocks = <&k3_clks 182 1>; - clock-names = "fck"; - power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; - - status = "disabled"; - }; - - mcasp9: mcasp@2b90000 { - compatible = "ti,am33xx-mcasp-audio"; - reg = <0x0 0x02b90000 0x0 0x2000>, - <0x0 0x02b98000 0x0 0x1000>; - reg-names = "mpu","dat"; - interrupts = , - ; - interrupt-names = "tx", "rx"; - - dmas = <&main_udmap 0xc506>, <&main_udmap 0x4506>; - dma-names = "tx", "rx"; - - clocks = <&k3_clks 183 1>; - clock-names = "fck"; - power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>; - - status = "disabled"; - }; - - mcasp10: mcasp@2ba0000 { - compatible = "ti,am33xx-mcasp-audio"; - reg = <0x0 0x02ba0000 0x0 0x2000>, - <0x0 0x02ba8000 0x0 0x1000>; - reg-names = "mpu","dat"; - interrupts = , - ; - interrupt-names = "tx", "rx"; - - dmas = <&main_udmap 0xc507>, <&main_udmap 0x4507>; - dma-names = "tx", "rx"; - - clocks = <&k3_clks 184 1>; - clock-names = "fck"; - power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>; - - status = "disabled"; - }; - - mcasp11: mcasp@2bb0000 { - compatible = "ti,am33xx-mcasp-audio"; - reg = <0x0 0x02bb0000 0x0 0x2000>, - <0x0 0x02bb8000 0x0 0x1000>; - reg-names = "mpu","dat"; - interrupts = , - ; - interrupt-names = "tx", "rx"; - - dmas = <&main_udmap 0xc508>, <&main_udmap 0x4508>; - dma-names = "tx", "rx"; - - clocks = <&k3_clks 185 1>; - clock-names = "fck"; - power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>; - - status = "disabled"; - }; -}; diff --git a/sys/gnu/dts/arm64/ti/k3-j721e-mcu-wakeup.dtsi b/sys/gnu/dts/arm64/ti/k3-j721e-mcu-wakeup.dtsi deleted file mode 100644 index 16c874bfd49..00000000000 --- a/sys/gnu/dts/arm64/ti/k3-j721e-mcu-wakeup.dtsi +++ /dev/null @@ -1,273 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for J721E SoC Family MCU/WAKEUP Domain peripherals - * - * Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/ - */ - -&cbass_mcu_wakeup { - dmsc: dmsc@44083000 { - compatible = "ti,k2g-sci"; - ti,host-id = <12>; - - mbox-names = "rx", "tx"; - - mboxes= <&secure_proxy_main 11>, - <&secure_proxy_main 13>; - - reg-names = "debug_messages"; - reg = <0x00 0x44083000 0x0 0x1000>; - - k3_pds: power-controller { - compatible = "ti,sci-pm-domain"; - #power-domain-cells = <2>; - }; - - k3_clks: clocks { - compatible = "ti,k2g-sci-clk"; - #clock-cells = <2>; - }; - - k3_reset: reset-controller { - compatible = "ti,sci-reset"; - #reset-cells = <2>; - }; - }; - - wkup_pmx0: pinmux@4301c000 { - compatible = "pinctrl-single"; - /* Proxy 0 addressing */ - reg = <0x00 0x4301c000 0x00 0x178>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0xffffffff>; - }; - - mcu_ram: sram@41c00000 { - compatible = "mmio-sram"; - reg = <0x00 0x41c00000 0x00 0x100000>; - ranges = <0x0 0x00 0x41c00000 0x100000>; - #address-cells = <1>; - #size-cells = <1>; - }; - - wkup_uart0: serial@42300000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x42300000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; - interrupts = ; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 287 0>; - clock-names = "fclk"; - }; - - mcu_uart0: serial@40a00000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x40a00000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; - interrupts = ; - clock-frequency = <96000000>; - current-speed = <115200>; - power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 149 0>; - clock-names = "fclk"; - }; - - wkup_gpio_intr: interrupt-controller2 { - compatible = "ti,sci-intr"; - ti,intr-trigger-type = <1>; - interrupt-controller; - interrupt-parent = <&gic500>; - #interrupt-cells = <2>; - ti,sci = <&dmsc>; - ti,sci-dst-id = <14>; - ti,sci-rm-range-girq = <0x5>; - }; - - wkup_gpio0: gpio@42110000 { - compatible = "ti,j721e-gpio", "ti,keystone-gpio"; - reg = <0x0 0x42110000 0x0 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&wkup_gpio_intr>; - interrupts = <113 0>, <113 1>, <113 2>, - <113 3>, <113 4>, <113 5>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <84>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 113 0>; - clock-names = "gpio"; - }; - - wkup_gpio1: gpio@42100000 { - compatible = "ti,j721e-gpio", "ti,keystone-gpio"; - reg = <0x0 0x42100000 0x0 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&wkup_gpio_intr>; - interrupts = <114 0>, <114 1>, <114 2>, - <114 3>, <114 4>, <114 5>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <84>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 114 0>; - clock-names = "gpio"; - }; - - mcu_i2c0: i2c@40b00000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x0 0x40b00000 0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 194 0>; - power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>; - }; - - mcu_i2c1: i2c@40b10000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x0 0x40b10000 0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 195 0>; - power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>; - }; - - wkup_i2c0: i2c@42120000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x0 0x42120000 0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 197 0>; - power-domains = <&k3_pds 197 TI_SCI_PD_SHARED>; - }; - - fss: fss@47000000 { - compatible = "simple-bus"; - reg = <0x0 0x47000000 0x0 0x100>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - ospi0: spi@47040000 { - compatible = "ti,am654-ospi"; - reg = <0x0 0x47040000 0x0 0x100>, - <0x5 0x00000000 0x1 0x0000000>; - interrupts = ; - cdns,fifo-depth = <256>; - cdns,fifo-width = <4>; - cdns,trigger-address = <0x0>; - clocks = <&k3_clks 103 0>; - assigned-clocks = <&k3_clks 103 0>; - assigned-clock-parents = <&k3_clks 103 2>; - assigned-clock-rates = <166666666>; - power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; - #address-cells = <1>; - #size-cells = <0>; - }; - - ospi1: spi@47050000 { - compatible = "ti,am654-ospi"; - reg = <0x0 0x47050000 0x0 0x100>, - <0x7 0x00000000 0x1 0x00000000>; - interrupts = ; - cdns,fifo-depth = <256>; - cdns,fifo-width = <4>; - cdns,trigger-address = <0x0>; - clocks = <&k3_clks 104 0>; - power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - tscadc0: tscadc@40200000 { - compatible = "ti,am3359-tscadc"; - reg = <0x0 0x40200000 0x0 0x1000>; - interrupts = ; - power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 0 1>; - assigned-clocks = <&k3_clks 0 3>; - assigned-clock-rates = <60000000>; - clock-names = "adc_tsc_fck"; - - adc { - #io-channel-cells = <1>; - compatible = "ti,am3359-adc"; - }; - }; - - tscadc1: tscadc@40210000 { - compatible = "ti,am3359-tscadc"; - reg = <0x0 0x40210000 0x0 0x1000>; - interrupts = ; - power-domains = <&k3_pds 1 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 1 1>; - assigned-clocks = <&k3_clks 1 3>; - assigned-clock-rates = <60000000>; - clock-names = "adc_tsc_fck"; - - adc { - #io-channel-cells = <1>; - compatible = "ti,am3359-adc"; - }; - }; - - mcu_navss { - compatible = "simple-mfd"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - dma-coherent; - dma-ranges; - - ti,sci-dev-id = <232>; - - mcu_ringacc: ringacc@2b800000 { - compatible = "ti,am654-navss-ringacc"; - reg = <0x0 0x2b800000 0x0 0x400000>, - <0x0 0x2b000000 0x0 0x400000>, - <0x0 0x28590000 0x0 0x100>, - <0x0 0x2a500000 0x0 0x40000>; - reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; - ti,num-rings = <286>; - ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ - ti,sci = <&dmsc>; - ti,sci-dev-id = <235>; - msi-parent = <&main_udmass_inta>; - }; - - mcu_udmap: dma-controller@285c0000 { - compatible = "ti,j721e-navss-mcu-udmap"; - reg = <0x0 0x285c0000 0x0 0x100>, - <0x0 0x2a800000 0x0 0x40000>, - <0x0 0x2aa00000 0x0 0x40000>; - reg-names = "gcfg", "rchanrt", "tchanrt"; - msi-parent = <&main_udmass_inta>; - #dma-cells = <1>; - - ti,sci = <&dmsc>; - ti,sci-dev-id = <236>; - ti,ringacc = <&mcu_ringacc>; - - ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ - <0x0f>; /* TX_HCHAN */ - ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ - <0x0b>; /* RX_HCHAN */ - ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ - }; - }; -}; diff --git a/sys/gnu/dts/arm64/ti/k3-j721e-som-p0.dtsi b/sys/gnu/dts/arm64/ti/k3-j721e-som-p0.dtsi deleted file mode 100644 index 7680109ca60..00000000000 --- a/sys/gnu/dts/arm64/ti/k3-j721e-som-p0.dtsi +++ /dev/null @@ -1,74 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ - */ - -/dts-v1/; - -#include "k3-j721e.dtsi" - -/ { - memory@80000000 { - device_type = "memory"; - /* 4G RAM */ - reg = <0x00000000 0x80000000 0x00000000 0x80000000>, - <0x00000008 0x80000000 0x00000000 0x80000000>; - }; - - reserved_memory: reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - secure_ddr: optee@9e800000 { - reg = <0x00 0x9e800000 0x00 0x01800000>; - alignment = <0x1000>; - no-map; - }; - }; -}; - -&wkup_pmx0 { - wkup_i2c0_pins_default: wkup_i2c0_pins_default { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */ - J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */ - >; - }; - - mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */ - J721E_WKUP_IOPAD(0x0008, PIN_INPUT, 0) /* MCU_OSPI0_DQS */ - J721E_WKUP_IOPAD(0x000c, PIN_INPUT, 0) /* MCU_OSPI0_D0 */ - J721E_WKUP_IOPAD(0x0010, PIN_INPUT, 0) /* MCU_OSPI0_D1 */ - J721E_WKUP_IOPAD(0x0014, PIN_INPUT, 0) /* MCU_OSPI0_D2 */ - J721E_WKUP_IOPAD(0x0018, PIN_INPUT, 0) /* MCU_OSPI0_D3 */ - J721E_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /* MCU_OSPI0_D4 */ - J721E_WKUP_IOPAD(0x0020, PIN_INPUT, 0) /* MCU_OSPI0_D5 */ - J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* MCU_OSPI0_D6 */ - J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* MCU_OSPI0_D7 */ - J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */ - >; - }; -}; - -&ospi0 { - pinctrl-names = "default"; - pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; - - flash@0{ - compatible = "jedec,spi-nor"; - reg = <0x0>; - spi-tx-bus-width = <1>; - spi-rx-bus-width = <8>; - spi-max-frequency = <40000000>; - cdns,tshsl-ns = <60>; - cdns,tsd2d-ns = <60>; - cdns,tchsh-ns = <60>; - cdns,tslch-ns = <60>; - cdns,read-delay = <0>; - #address-cells = <1>; - #size-cells = <1>; - }; -}; diff --git a/sys/gnu/dts/arm64/ti/k3-j721e.dtsi b/sys/gnu/dts/arm64/ti/k3-j721e.dtsi deleted file mode 100644 index 027bd1febaf..00000000000 --- a/sys/gnu/dts/arm64/ti/k3-j721e.dtsi +++ /dev/null @@ -1,180 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for J721E SoC Family - * - * Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/ - */ - -#include -#include -#include -#include - -/ { - model = "Texas Instruments K3 J721E SoC"; - compatible = "ti,j721e"; - interrupt-parent = <&gic500>; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - serial0 = &wkup_uart0; - serial1 = &mcu_uart0; - serial2 = &main_uart0; - serial3 = &main_uart1; - serial4 = &main_uart2; - serial5 = &main_uart3; - serial6 = &main_uart4; - serial7 = &main_uart5; - serial8 = &main_uart6; - serial9 = &main_uart7; - serial10 = &main_uart8; - serial11 = &main_uart9; - }; - - chosen { }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu-map { - cluster0: cluster0 { - core0 { - cpu = <&cpu0>; - }; - - core1 { - cpu = <&cpu1>; - }; - }; - - }; - - cpu0: cpu@0 { - compatible = "arm,cortex-a72"; - reg = <0x000>; - device_type = "cpu"; - enable-method = "psci"; - i-cache-size = <0xC000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - next-level-cache = <&L2_0>; - }; - - cpu1: cpu@1 { - compatible = "arm,cortex-a72"; - reg = <0x001>; - device_type = "cpu"; - enable-method = "psci"; - i-cache-size = <0xC000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - next-level-cache = <&L2_0>; - }; - }; - - L2_0: l2-cache0 { - compatible = "cache"; - cache-level = <2>; - cache-size = <0x100000>; - cache-line-size = <64>; - cache-sets = <2048>; - next-level-cache = <&msmc_l3>; - }; - - msmc_l3: l3-cache0 { - compatible = "cache"; - cache-level = <3>; - }; - - firmware { - optee { - compatible = "linaro,optee-tz"; - method = "smc"; - }; - - psci: psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - }; - - a72_timer0: timer-cl0-cpu0 { - compatible = "arm,armv8-timer"; - interrupts = , /* cntpsirq */ - , /* cntpnsirq */ - , /* cntvirq */ - ; /* cnthpirq */ - }; - - pmu: pmu { - compatible = "arm,armv8-pmuv3"; - /* Recommendation from GIC500 TRM Table A.3 */ - interrupts = ; - }; - - cbass_main: interconnect@100000 { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */ - <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */ - <0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */ - <0x00 0x00A40000 0x00 0x00A40000 0x00 0x00000800>, /* timesync router */ - <0x00 0x06000000 0x00 0x06000000 0x00 0x00400000>, /* USBSS0 */ - <0x00 0x06400000 0x00 0x06400000 0x00 0x00400000>, /* USBSS1 */ - <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */ - <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */ - <0x00 0x0d000000 0x00 0x0d000000 0x00 0x01000000>, /* PCIe Core*/ - <0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */ - <0x00 0x64800000 0x00 0x64800000 0x00 0x00800000>, /* C71 */ - <0x4d 0x80800000 0x4d 0x80800000 0x00 0x00800000>, /* C66_0 */ - <0x4d 0x81800000 0x4d 0x81800000 0x00 0x00800000>, /* C66_1 */ - <0x4e 0x20000000 0x4e 0x20000000 0x00 0x00080000>, /* GPU */ - <0x00 0x70000000 0x00 0x70000000 0x00 0x00800000>, /* MSMC RAM */ - - /* MCUSS_WKUP Range */ - <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, - <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, - <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, - <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, - <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, - <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, - <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, - <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, - <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, - <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, - <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, - <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, - <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; - - cbass_mcu_wakeup: interconnect@28380000 { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/ - <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, /* First peripheral window */ - <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */ - <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */ - <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */ - <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, /* MCU SRAM */ - <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP peripheral window */ - <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */ - <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */ - <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI register space */ - <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS OSPI0/1 data region 0 */ - <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS OSPI0 data region 3 */ - <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3*/ - }; - }; -}; - -/* Now include the peripherals for each bus segments */ -#include "k3-j721e-main.dtsi" -#include "k3-j721e-mcu-wakeup.dtsi" diff --git a/sys/gnu/dts/arm64/xilinx/avnet-ultra96-rev1.dts b/sys/gnu/dts/arm64/xilinx/avnet-ultra96-rev1.dts deleted file mode 100644 index 88aa06fa78a..00000000000 --- a/sys/gnu/dts/arm64/xilinx/avnet-ultra96-rev1.dts +++ /dev/null @@ -1,19 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * dts file for Avnet Ultra96 rev1 - * - * (C) Copyright 2018, Xilinx, Inc. - * - * Michal Simek - */ - -/dts-v1/; - -#include "zynqmp-zcu100-revC.dts" - -/ { - model = "Avnet Ultra96 Rev1"; - compatible = "avnet,ultra96-rev1", "avnet,ultra96", - "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100", - "xlnx,zynqmp"; -}; diff --git a/sys/gnu/dts/arm64/xilinx/zynqmp-clk-ccf.dtsi b/sys/gnu/dts/arm64/xilinx/zynqmp-clk-ccf.dtsi deleted file mode 100644 index 9868ca15dfc..00000000000 --- a/sys/gnu/dts/arm64/xilinx/zynqmp-clk-ccf.dtsi +++ /dev/null @@ -1,222 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Clock specification for Xilinx ZynqMP - * - * (C) Copyright 2017 - 2019, Xilinx, Inc. - * - * Michal Simek - */ - -#include -/ { - pss_ref_clk: pss_ref_clk { - u-boot,dm-pre-reloc; - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <33333333>; - }; - - video_clk: video_clk { - u-boot,dm-pre-reloc; - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <27000000>; - }; - - pss_alt_ref_clk: pss_alt_ref_clk { - u-boot,dm-pre-reloc; - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - gt_crx_ref_clk: gt_crx_ref_clk { - u-boot,dm-pre-reloc; - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <108000000>; - }; - - aux_ref_clk: aux_ref_clk { - u-boot,dm-pre-reloc; - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <27000000>; - }; -}; - -&can0 { - clocks = <&zynqmp_clk CAN0_REF>, <&zynqmp_clk LPD_LSBUS>; -}; - -&can1 { - clocks = <&zynqmp_clk CAN1_REF>, <&zynqmp_clk LPD_LSBUS>; -}; - -&cpu0 { - clocks = <&zynqmp_clk ACPU>; -}; - -&fpd_dma_chan1 { - clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; -}; - -&fpd_dma_chan2 { - clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; -}; - -&fpd_dma_chan3 { - clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; -}; - -&fpd_dma_chan4 { - clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; -}; - -&fpd_dma_chan5 { - clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; -}; - -&fpd_dma_chan6 { - clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; -}; - -&fpd_dma_chan7 { - clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; -}; - -&fpd_dma_chan8 { - clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; -}; - -&lpd_dma_chan1 { - clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; -}; - -&lpd_dma_chan2 { - clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; -}; - -&lpd_dma_chan3 { - clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; -}; - -&lpd_dma_chan4 { - clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; -}; - -&lpd_dma_chan5 { - clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; -}; - -&lpd_dma_chan6 { - clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; -}; - -&lpd_dma_chan7 { - clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; -}; - -&lpd_dma_chan8 { - clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; -}; - -&gem0 { - clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>, - <&zynqmp_clk GEM0_TX>, <&zynqmp_clk GEM0_RX>, - <&zynqmp_clk GEM_TSU>; - clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; -}; - -&gem1 { - clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>, - <&zynqmp_clk GEM1_TX>, <&zynqmp_clk GEM1_RX>, - <&zynqmp_clk GEM_TSU>; - clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; -}; - -&gem2 { - clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM2_REF>, - <&zynqmp_clk GEM2_TX>, <&zynqmp_clk GEM2_RX>, - <&zynqmp_clk GEM_TSU>; - clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; -}; - -&gem3 { - clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM3_REF>, - <&zynqmp_clk GEM3_TX>, <&zynqmp_clk GEM3_RX>, - <&zynqmp_clk GEM_TSU>; - clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; -}; - -&gpio { - clocks = <&zynqmp_clk LPD_LSBUS>; -}; - -&i2c0 { - clocks = <&zynqmp_clk I2C0_REF>; -}; - -&i2c1 { - clocks = <&zynqmp_clk I2C1_REF>; -}; - -&pcie { - clocks = <&zynqmp_clk PCIE_REF>; -}; - -&sata { - clocks = <&zynqmp_clk SATA_REF>; -}; - -&sdhci0 { - clocks = <&zynqmp_clk SDIO0_REF>, <&zynqmp_clk LPD_LSBUS>; -}; - -&sdhci1 { - clocks = <&zynqmp_clk SDIO1_REF>, <&zynqmp_clk LPD_LSBUS>; -}; - -&spi0 { - clocks = <&zynqmp_clk SPI0_REF>, <&zynqmp_clk LPD_LSBUS>; -}; - -&spi1 { - clocks = <&zynqmp_clk SPI1_REF>, <&zynqmp_clk LPD_LSBUS>; -}; - -&ttc0 { - clocks = <&zynqmp_clk LPD_LSBUS>; -}; - -&ttc1 { - clocks = <&zynqmp_clk LPD_LSBUS>; -}; - -&ttc2 { - clocks = <&zynqmp_clk LPD_LSBUS>; -}; - -&ttc3 { - clocks = <&zynqmp_clk LPD_LSBUS>; -}; - -&uart0 { - clocks = <&zynqmp_clk UART0_REF>, <&zynqmp_clk LPD_LSBUS>; -}; - -&uart1 { - clocks = <&zynqmp_clk UART1_REF>, <&zynqmp_clk LPD_LSBUS>; -}; - -&usb0 { - clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>; -}; - -&usb1 { - clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>; -}; - -&watchdog0 { - clocks = <&zynqmp_clk WDT>; -}; diff --git a/sys/gnu/dts/arm64/xilinx/zynqmp-zc1232-revA.dts b/sys/gnu/dts/arm64/xilinx/zynqmp-zc1232-revA.dts deleted file mode 100644 index 2e05fa41695..00000000000 --- a/sys/gnu/dts/arm64/xilinx/zynqmp-zc1232-revA.dts +++ /dev/null @@ -1,54 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * dts file for Xilinx ZynqMP ZC1232 - * - * (C) Copyright 2017 - 2019, Xilinx, Inc. - * - * Michal Simek - */ - -/dts-v1/; - -#include "zynqmp.dtsi" -#include "zynqmp-clk-ccf.dtsi" - -/ { - model = "ZynqMP ZC1232 RevA"; - compatible = "xlnx,zynqmp-zc1232-revA", "xlnx,zynqmp-zc1232", "xlnx,zynqmp"; - - aliases { - serial0 = &uart0; - serial1 = &dcc; - }; - - chosen { - bootargs = "earlycon"; - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; -}; - -&dcc { - status = "okay"; -}; - -&sata { - status = "okay"; - /* SATA OOB timing settings */ - ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; - ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; - ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; - ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; - ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; - ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; - ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; - ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; -}; - -&uart0 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/xilinx/zynqmp-zc1254-revA.dts b/sys/gnu/dts/arm64/xilinx/zynqmp-zc1254-revA.dts deleted file mode 100644 index 3d0aaa02f18..00000000000 --- a/sys/gnu/dts/arm64/xilinx/zynqmp-zc1254-revA.dts +++ /dev/null @@ -1,42 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * dts file for Xilinx ZynqMP ZC1254 - * - * (C) Copyright 2015 - 2019, Xilinx, Inc. - * - * Michal Simek - * Siva Durga Prasad Paladugu - */ - -/dts-v1/; - -#include "zynqmp.dtsi" -#include "zynqmp-clk-ccf.dtsi" - -/ { - model = "ZynqMP ZC1254 RevA"; - compatible = "xlnx,zynqmp-zc1254-revA", "xlnx,zynqmp-zc1254", "xlnx,zynqmp"; - - aliases { - serial0 = &uart0; - serial1 = &dcc; - }; - - chosen { - bootargs = "earlycon"; - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; -}; - -&dcc { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/xilinx/zynqmp-zc1275-revA.dts b/sys/gnu/dts/arm64/xilinx/zynqmp-zc1275-revA.dts deleted file mode 100644 index 66a90483b00..00000000000 --- a/sys/gnu/dts/arm64/xilinx/zynqmp-zc1275-revA.dts +++ /dev/null @@ -1,42 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * dts file for Xilinx ZynqMP ZC1275 - * - * (C) Copyright 2017 - 2019, Xilinx, Inc. - * - * Michal Simek - * Siva Durga Prasad Paladugu - */ - -/dts-v1/; - -#include "zynqmp.dtsi" -#include "zynqmp-clk-ccf.dtsi" - -/ { - model = "ZynqMP ZC1275 RevA"; - compatible = "xlnx,zynqmp-zc1275-revA", "xlnx,zynqmp-zc1275", "xlnx,zynqmp"; - - aliases { - serial0 = &uart0; - serial1 = &dcc; - }; - - chosen { - bootargs = "earlycon"; - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; -}; - -&dcc { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/xilinx/zynqmp-zc1751-xm015-dc1.dts b/sys/gnu/dts/arm64/xilinx/zynqmp-zc1751-xm015-dc1.dts deleted file mode 100644 index 69f6e461073..00000000000 --- a/sys/gnu/dts/arm64/xilinx/zynqmp-zc1751-xm015-dc1.dts +++ /dev/null @@ -1,132 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * dts file for Xilinx ZynqMP zc1751-xm015-dc1 - * - * (C) Copyright 2015 - 2019, Xilinx, Inc. - * - * Michal Simek - */ - -/dts-v1/; - -#include "zynqmp.dtsi" -#include "zynqmp-clk-ccf.dtsi" -#include - -/ { - model = "ZynqMP zc1751-xm015-dc1 RevA"; - compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; - - aliases { - ethernet0 = &gem3; - i2c0 = &i2c1; - mmc0 = &sdhci0; - mmc1 = &sdhci1; - rtc0 = &rtc; - serial0 = &uart0; - }; - - chosen { - bootargs = "earlycon"; - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; - }; -}; - -&fpd_dma_chan1 { - status = "okay"; -}; - -&fpd_dma_chan2 { - status = "okay"; -}; - -&fpd_dma_chan3 { - status = "okay"; -}; - -&fpd_dma_chan4 { - status = "okay"; -}; - -&fpd_dma_chan5 { - status = "okay"; -}; - -&fpd_dma_chan6 { - status = "okay"; -}; - -&fpd_dma_chan7 { - status = "okay"; -}; - -&fpd_dma_chan8 { - status = "okay"; -}; - -&gem3 { - status = "okay"; - phy-handle = <&phy0>; - phy-mode = "rgmii-id"; - phy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -&gpio { - status = "okay"; -}; - - -&i2c1 { - status = "okay"; - clock-frequency = <400000>; - - eeprom: eeprom@55 { - compatible = "atmel,24c64"; /* 24AA64 */ - reg = <0x55>; - }; -}; - -&rtc { - status = "okay"; -}; - -&sata { - status = "okay"; - /* SATA phy OOB timing settings */ - ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; - ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; - ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; - ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; - ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; - ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; - ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; - ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; -}; - -/* eMMC */ -&sdhci0 { - status = "okay"; - bus-width = <8>; -}; - -/* SD1 with level shifter */ -&sdhci1 { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -/* ULPI SMSC USB3320 */ -&usb0 { - status = "okay"; - dr_mode = "host"; -}; diff --git a/sys/gnu/dts/arm64/xilinx/zynqmp-zc1751-xm016-dc2.dts b/sys/gnu/dts/arm64/xilinx/zynqmp-zc1751-xm016-dc2.dts deleted file mode 100644 index 4a86efa32d6..00000000000 --- a/sys/gnu/dts/arm64/xilinx/zynqmp-zc1751-xm016-dc2.dts +++ /dev/null @@ -1,170 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * dts file for Xilinx ZynqMP zc1751-xm016-dc2 - * - * (C) Copyright 2015 - 2019, Xilinx, Inc. - * - * Michal Simek - */ - -/dts-v1/; - -#include "zynqmp.dtsi" -#include "zynqmp-clk-ccf.dtsi" -#include - -/ { - model = "ZynqMP zc1751-xm016-dc2 RevA"; - compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; - - aliases { - can0 = &can0; - can1 = &can1; - ethernet0 = &gem2; - i2c0 = &i2c0; - rtc0 = &rtc; - serial0 = &uart0; - serial1 = &uart1; - spi0 = &spi0; - spi1 = &spi1; - }; - - chosen { - bootargs = "earlycon"; - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; - }; -}; - -&can0 { - status = "okay"; -}; - -&can1 { - status = "okay"; -}; - -&fpd_dma_chan1 { - status = "okay"; -}; - -&fpd_dma_chan2 { - status = "okay"; -}; - -&fpd_dma_chan3 { - status = "okay"; -}; - -&fpd_dma_chan4 { - status = "okay"; -}; - -&fpd_dma_chan5 { - status = "okay"; -}; - -&fpd_dma_chan6 { - status = "okay"; -}; - -&fpd_dma_chan7 { - status = "okay"; -}; - -&fpd_dma_chan8 { - status = "okay"; -}; - -&gem2 { - status = "okay"; - phy-handle = <&phy0>; - phy-mode = "rgmii-id"; - phy0: ethernet-phy@5 { - reg = <5>; - ti,rx-internal-delay = <0x8>; - ti,tx-internal-delay = <0xa>; - ti,fifo-depth = <0x1>; - ti,dp83867-rxctrl-strap-quirk; - }; -}; - -&gpio { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - clock-frequency = <400000>; - - tca6416_u26: gpio@20 { - compatible = "ti,tca6416"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - /* IRQ not connected */ - }; - - rtc@68 { - compatible = "dallas,ds1339"; - reg = <0x68>; - }; -}; - -&rtc { - status = "okay"; -}; - -&spi0 { - status = "okay"; - num-cs = <1>; - - spi0_flash0: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "sst,sst25wf080", "jedec,spi-nor"; - spi-max-frequency = <50000000>; - reg = <0>; - - partition@0 { - label = "data"; - reg = <0x0 0x100000>; - }; - }; -}; - -&spi1 { - status = "okay"; - num-cs = <1>; - - spi1_flash0: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "atmel,at45db041e", "atmel,at45", "atmel,dataflash"; - spi-max-frequency = <20000000>; - reg = <0>; - - partition@0 { - label = "data"; - reg = <0x0 0x84000>; - }; - }; -}; - -/* ULPI SMSC USB3320 */ -&usb1 { - status = "okay"; - dr_mode = "host"; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/xilinx/zynqmp-zc1751-xm017-dc3.dts b/sys/gnu/dts/arm64/xilinx/zynqmp-zc1751-xm017-dc3.dts deleted file mode 100644 index 4ea6ef5a7f2..00000000000 --- a/sys/gnu/dts/arm64/xilinx/zynqmp-zc1751-xm017-dc3.dts +++ /dev/null @@ -1,150 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * dts file for Xilinx ZynqMP zc1751-xm017-dc3 - * - * (C) Copyright 2016 - 2019, Xilinx, Inc. - * - * Michal Simek - */ - -/dts-v1/; - -#include "zynqmp.dtsi" -#include "zynqmp-clk-ccf.dtsi" - -/ { - model = "ZynqMP zc1751-xm017-dc3 RevA"; - compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; - - aliases { - ethernet0 = &gem0; - i2c0 = &i2c0; - i2c1 = &i2c1; - mmc0 = &sdhci1; - rtc0 = &rtc; - serial0 = &uart0; - serial1 = &uart1; - }; - - chosen { - bootargs = "earlycon"; - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; - }; -}; - -&fpd_dma_chan1 { - status = "okay"; -}; - -&fpd_dma_chan2 { - status = "okay"; -}; - -&fpd_dma_chan3 { - status = "okay"; -}; - -&fpd_dma_chan4 { - status = "okay"; -}; - -&fpd_dma_chan5 { - status = "okay"; -}; - -&fpd_dma_chan6 { - status = "okay"; -}; - -&fpd_dma_chan7 { - status = "okay"; -}; - -&fpd_dma_chan8 { - status = "okay"; -}; - -&gem0 { - status = "okay"; - phy-handle = <&phy0>; - phy-mode = "rgmii-id"; - phy0: ethernet-phy@0 { /* VSC8211 */ - reg = <0>; - }; -}; - -&gpio { - status = "okay"; -}; - -/* just eeprom here */ -&i2c0 { - status = "okay"; - clock-frequency = <400000>; - - tca6416_u26: gpio@20 { - compatible = "ti,tca6416"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - /* IRQ not connected */ - }; - - rtc@68 { - compatible = "dallas,ds1339"; - reg = <0x68>; - }; -}; - -/* eeprom24c02 and SE98A temp chip pca9306 */ -&i2c1 { - status = "okay"; - clock-frequency = <400000>; -}; - -&rtc { - status = "okay"; -}; - -&sata { - status = "okay"; - /* SATA phy OOB timing settings */ - ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; - ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; - ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; - ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; - ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; - ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; - ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; - ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; -}; - -&sdhci1 { /* emmc with some settings */ - status = "okay"; -}; - -/* main */ -&uart0 { - status = "okay"; -}; - -/* DB9 */ -&uart1 { - status = "okay"; -}; - -&usb0 { - status = "okay"; - dr_mode = "host"; -}; - -/* ULPI SMSC USB3320 */ -&usb1 { - status = "okay"; - dr_mode = "host"; -}; diff --git a/sys/gnu/dts/arm64/xilinx/zynqmp-zc1751-xm018-dc4.dts b/sys/gnu/dts/arm64/xilinx/zynqmp-zc1751-xm018-dc4.dts deleted file mode 100644 index 2366cd9f091..00000000000 --- a/sys/gnu/dts/arm64/xilinx/zynqmp-zc1751-xm018-dc4.dts +++ /dev/null @@ -1,178 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * dts file for Xilinx ZynqMP zc1751-xm018-dc4 - * - * (C) Copyright 2015 - 2019, Xilinx, Inc. - * - * Michal Simek - */ - -/dts-v1/; - -#include "zynqmp.dtsi" -#include "zynqmp-clk-ccf.dtsi" - -/ { - model = "ZynqMP zc1751-xm018-dc4"; - compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; - - aliases { - ethernet0 = &gem0; - ethernet1 = &gem1; - ethernet2 = &gem2; - ethernet3 = &gem3; - i2c0 = &i2c0; - i2c1 = &i2c1; - rtc0 = &rtc; - serial0 = &uart0; - serial1 = &uart1; - }; - - chosen { - bootargs = "earlycon"; - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; - }; -}; - -&can0 { - status = "okay"; -}; - -&can1 { - status = "okay"; -}; - -&fpd_dma_chan1 { - status = "okay"; -}; - -&fpd_dma_chan2 { - status = "okay"; -}; - -&fpd_dma_chan3 { - status = "okay"; -}; - -&fpd_dma_chan4 { - status = "okay"; -}; - -&fpd_dma_chan5 { - status = "okay"; -}; - -&fpd_dma_chan6 { - status = "okay"; -}; - -&fpd_dma_chan7 { - status = "okay"; -}; - -&fpd_dma_chan8 { - status = "okay"; -}; - -&lpd_dma_chan1 { - status = "okay"; -}; - -&lpd_dma_chan2 { - status = "okay"; -}; - -&lpd_dma_chan3 { - status = "okay"; -}; - -&lpd_dma_chan4 { - status = "okay"; -}; - -&lpd_dma_chan5 { - status = "okay"; -}; - -&lpd_dma_chan6 { - status = "okay"; -}; - -&lpd_dma_chan7 { - status = "okay"; -}; - -&lpd_dma_chan8 { - status = "okay"; -}; - -&gem0 { - status = "okay"; - phy-mode = "rgmii-id"; - phy-handle = <ðernet_phy0>; - ethernet_phy0: ethernet-phy@0 { /* Marvell 88e1512 */ - reg = <0>; - }; - ethernet_phy7: ethernet-phy@7 { /* Vitesse VSC8211 */ - reg = <7>; - }; - ethernet_phy3: ethernet-phy@3 { /* Realtek RTL8211DN */ - reg = <3>; - }; - ethernet_phy8: ethernet-phy@8 { /* Vitesse VSC8211 */ - reg = <8>; - }; -}; - -&gem1 { - status = "okay"; - phy-mode = "rgmii-id"; - phy-handle = <ðernet_phy7>; -}; - -&gem2 { - status = "okay"; - phy-mode = "rgmii-id"; - phy-handle = <ðernet_phy3>; -}; - -&gem3 { - status = "okay"; - phy-mode = "rgmii-id"; - phy-handle = <ðernet_phy8>; -}; - -&gpio { - status = "okay"; -}; - -&i2c0 { - clock-frequency = <400000>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <400000>; - status = "okay"; -}; - -&rtc { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&watchdog0 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/xilinx/zynqmp-zc1751-xm019-dc5.dts b/sys/gnu/dts/arm64/xilinx/zynqmp-zc1751-xm019-dc5.dts deleted file mode 100644 index 41934e3525c..00000000000 --- a/sys/gnu/dts/arm64/xilinx/zynqmp-zc1751-xm019-dc5.dts +++ /dev/null @@ -1,125 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * dts file for Xilinx ZynqMP zc1751-xm019-dc5 - * - * (C) Copyright 2015 - 2019, Xilinx, Inc. - * - * Siva Durga Prasad - * Michal Simek - */ - -/dts-v1/; - -#include "zynqmp.dtsi" -#include "zynqmp-clk-ccf.dtsi" -#include - -/ { - model = "ZynqMP zc1751-xm019-dc5 RevA"; - compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; - - aliases { - ethernet0 = &gem1; - i2c0 = &i2c0; - i2c1 = &i2c1; - mmc0 = &sdhci0; - serial0 = &uart0; - serial1 = &uart1; - }; - - chosen { - bootargs = "earlycon"; - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; - }; -}; - -&fpd_dma_chan1 { - status = "okay"; -}; - -&fpd_dma_chan2 { - status = "okay"; -}; - -&fpd_dma_chan3 { - status = "okay"; -}; - -&fpd_dma_chan4 { - status = "okay"; -}; - -&fpd_dma_chan5 { - status = "okay"; -}; - -&fpd_dma_chan6 { - status = "okay"; -}; - -&fpd_dma_chan7 { - status = "okay"; -}; - -&fpd_dma_chan8 { - status = "okay"; -}; - -&gem1 { - status = "okay"; - phy-handle = <&phy0>; - phy-mode = "rgmii-id"; - phy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -&gpio { - status = "okay"; -}; - -&i2c0 { - status = "okay"; -}; - -&i2c1 { - status = "okay"; -}; - -&sdhci0 { - status = "okay"; - no-1-8-v; -}; - -&ttc0 { - status = "okay"; -}; - -&ttc1 { - status = "okay"; -}; - -&ttc2 { - status = "okay"; -}; - -&ttc3 { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&watchdog0 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/xilinx/zynqmp-zcu100-revC.dts b/sys/gnu/dts/arm64/xilinx/zynqmp-zcu100-revC.dts deleted file mode 100644 index d60110ad836..00000000000 --- a/sys/gnu/dts/arm64/xilinx/zynqmp-zcu100-revC.dts +++ /dev/null @@ -1,295 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * dts file for Xilinx ZynqMP ZCU100 revC - * - * (C) Copyright 2016 - 2019, Xilinx, Inc. - * - * Michal Simek - * Nathalie Chan King Choy - */ - -/dts-v1/; - -#include "zynqmp.dtsi" -#include "zynqmp-clk-ccf.dtsi" -#include -#include -#include - -/ { - model = "ZynqMP ZCU100 RevC"; - compatible = "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100", "xlnx,zynqmp"; - - aliases { - i2c0 = &i2c1; - rtc0 = &rtc; - serial0 = &uart1; - serial1 = &uart0; - serial2 = &dcc; - spi0 = &spi0; - spi1 = &spi1; - mmc0 = &sdhci0; - mmc1 = &sdhci1; - }; - - chosen { - bootargs = "earlycon"; - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; - - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - sw4 { - label = "sw4"; - gpios = <&gpio 23 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - autorepeat; - }; - }; - - leds { - compatible = "gpio-leds"; - ds2 { - label = "ds2"; - gpios = <&gpio 20 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - - ds3 { - label = "ds3"; - gpios = <&gpio 19 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "phy0tx"; /* WLAN tx */ - default-state = "off"; - }; - - ds4 { - label = "ds4"; - gpios = <&gpio 18 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "phy0rx"; /* WLAN rx */ - default-state = "off"; - }; - - ds5 { - label = "ds5"; - gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "bluetooth-power"; - }; - - vbus-det { /* U5 USB5744 VBUS detection via MIO25 */ - label = "vbus_det"; - gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; - - wmmcsdio_fixed: fixedregulator-mmcsdio { - compatible = "regulator-fixed"; - regulator-name = "wmmcsdio_fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */ - post-power-on-delay-ms = <10>; - }; - - ina226 { - compatible = "iio-hwmon"; - io-channels = <&u35 0>, <&u35 1>, <&u35 2>, <&u35 3>; - }; -}; - -&dcc { - status = "okay"; -}; - -&gpio { - status = "okay"; - gpio-line-names = "UART1_TX", "UART1_RX", "UART0_RX", "UART0_TX", "I2C1_SCL", - "I2C1_SDA", "SPI1_SCLK", "WLAN_EN", "BT_EN", "SPI1_CS", - "SPI1_MISO", "SPI1_MOSI", "I2C_MUX_RESET", "SD0_DAT0", "SD0_DAT1", - "SD0_DAT2", "SD0_DAT3", "PS_LED3", "PS_LED2", "PS_LED1", - "PS_LED0", "SD0_CMD", "SD0_CLK", "GPIO_PB", "SD0_DETECT", - "VBUS_DET", "POWER_INT", "DP_AUX", "DP_HPD", "DP_OE", - "DP_AUX_IN", "INA226_ALERT", "PS_FP_PWR_EN", "PL_PWR_EN", "POWER_KILL", - "", "GPIO-A", "GPIO-B", "SPI0_SCLK", "GPIO-C", - "GPIO-D", "SPI0_CS", "SPI0_MISO", "SPI_MOSI", "GPIO-E", - "GPIO-F", "SD1_D0", "SD1_D1", "SD1_D2", "SD1_D3", - "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", - "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", - "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", - "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", - "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", - "USB_DATA7", "WLAN_IRQ", "PMIC_IRQ", /* MIO end and EMIO start */ - "", "", - "", "", "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", "", "", - "", "", "", ""; -}; - -&i2c1 { - status = "okay"; - clock-frequency = <100000>; - i2c-mux@75 { /* u11 */ - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x75>; - i2csw_0: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - label = "LS-I2C0"; - }; - i2csw_1: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - label = "LS-I2C1"; - }; - i2csw_2: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - label = "HS-I2C2"; - }; - i2csw_3: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - label = "HS-I2C3"; - }; - i2csw_4: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x4>; - - pmic: pmic@5e { /* Custom TI PMIC u33 */ - compatible = "ti,tps65086"; - reg = <0x5e>; - interrupt-parent = <&gpio>; - interrupts = <77 GPIO_ACTIVE_LOW>; - #gpio-cells = <2>; - gpio-controller; - }; - }; - i2csw_5: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - /* PS_PMBUS */ - u35: ina226@40 { /* u35 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - reg = <0x40>; - shunt-resistor = <10000>; - /* MIO31 is alert which should be routed to PMUFW */ - }; - }; - i2csw_6: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - /* - * Not Connected - */ - }; - i2csw_7: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - /* - * usb5744 (DNP) - U5 - * 100kHz - this is default freq for us - */ - }; - }; -}; - -&rtc { - status = "okay"; -}; - -/* SD0 only supports 3.3V, no level shifter */ -&sdhci0 { - status = "okay"; - no-1-8-v; - disable-wp; -}; - -&sdhci1 { - status = "okay"; - bus-width = <0x4>; - non-removable; - disable-wp; - cap-power-off-card; - mmc-pwrseq = <&sdio_pwrseq>; - vqmmc-supply = <&wmmcsdio_fixed>; - #address-cells = <1>; - #size-cells = <0>; - wlcore: wifi@2 { - compatible = "ti,wl1831"; - reg = <2>; - interrupt-parent = <&gpio>; - interrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */ - }; -}; - -&spi0 { /* Low Speed connector */ - status = "okay"; - label = "LS-SPI0"; - num-cs = <1>; -}; - -&spi1 { /* High Speed connector */ - status = "okay"; - label = "HS-SPI1"; - num-cs = <1>; -}; - -&uart0 { - status = "okay"; - bluetooth { - compatible = "ti,wl1831-st"; - enable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>; - }; -}; - -&uart1 { - status = "okay"; - -}; - -/* ULPI SMSC USB3320 */ -&usb0 { - status = "okay"; - dr_mode = "peripheral"; -}; - -/* ULPI SMSC USB3320 */ -&usb1 { - status = "okay"; - dr_mode = "host"; -}; - -&watchdog0 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/xilinx/zynqmp-zcu102-rev1.0.dts b/sys/gnu/dts/arm64/xilinx/zynqmp-zcu102-rev1.0.dts deleted file mode 100644 index 6647e97edba..00000000000 --- a/sys/gnu/dts/arm64/xilinx/zynqmp-zcu102-rev1.0.dts +++ /dev/null @@ -1,36 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * dts file for Xilinx ZynqMP ZCU102 Rev1.0 - * - * (C) Copyright 2016 - 2018, Xilinx, Inc. - * - * Michal Simek - */ - -#include "zynqmp-zcu102-revB.dts" - -/ { - model = "ZynqMP ZCU102 Rev1.0"; - compatible = "xlnx,zynqmp-zcu102-rev1.0", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; -}; - -&eeprom { - #address-cells = <1>; - #size-cells = <1>; - - board_sn: board-sn@0 { - reg = <0x0 0x14>; - }; - - eth_mac: eth-mac@20 { - reg = <0x20 0x6>; - }; - - board_name: board-name@d0 { - reg = <0xd0 0x6>; - }; - - board_revision: board-revision@e0 { - reg = <0xe0 0x3>; - }; -}; diff --git a/sys/gnu/dts/arm64/xilinx/zynqmp-zcu102-revA.dts b/sys/gnu/dts/arm64/xilinx/zynqmp-zcu102-revA.dts deleted file mode 100644 index 4f801721564..00000000000 --- a/sys/gnu/dts/arm64/xilinx/zynqmp-zcu102-revA.dts +++ /dev/null @@ -1,634 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * dts file for Xilinx ZynqMP ZCU102 RevA - * - * (C) Copyright 2015 - 2019, Xilinx, Inc. - * - * Michal Simek - */ - -/dts-v1/; - -#include "zynqmp.dtsi" -#include "zynqmp-clk-ccf.dtsi" -#include -#include - -/ { - model = "ZynqMP ZCU102 RevA"; - compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; - - aliases { - ethernet0 = &gem3; - i2c0 = &i2c0; - i2c1 = &i2c1; - mmc0 = &sdhci1; - rtc0 = &rtc; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &dcc; - }; - - chosen { - bootargs = "earlycon"; - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; - }; - - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - sw19 { - label = "sw19"; - gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; - linux,code = ; - wakeup-source; - autorepeat; - }; - }; - - leds { - compatible = "gpio-leds"; - heartbeat-led { - label = "heartbeat"; - gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - ina226-u76 { - compatible = "iio-hwmon"; - io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>; - }; - ina226-u77 { - compatible = "iio-hwmon"; - io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>; - }; - ina226-u78 { - compatible = "iio-hwmon"; - io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>; - }; - ina226-u87 { - compatible = "iio-hwmon"; - io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>; - }; - ina226-u85 { - compatible = "iio-hwmon"; - io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>; - }; - ina226-u86 { - compatible = "iio-hwmon"; - io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>; - }; - ina226-u93 { - compatible = "iio-hwmon"; - io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>; - }; - ina226-u88 { - compatible = "iio-hwmon"; - io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>; - }; - ina226-u15 { - compatible = "iio-hwmon"; - io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>; - }; - ina226-u92 { - compatible = "iio-hwmon"; - io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>; - }; - ina226-u79 { - compatible = "iio-hwmon"; - io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; - }; - ina226-u81 { - compatible = "iio-hwmon"; - io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>; - }; - ina226-u80 { - compatible = "iio-hwmon"; - io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>; - }; - ina226-u84 { - compatible = "iio-hwmon"; - io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>; - }; - ina226-u16 { - compatible = "iio-hwmon"; - io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>; - }; - ina226-u65 { - compatible = "iio-hwmon"; - io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>; - }; - ina226-u74 { - compatible = "iio-hwmon"; - io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>; - }; - ina226-u75 { - compatible = "iio-hwmon"; - io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>; - }; -}; - -&can1 { - status = "okay"; -}; - -&dcc { - status = "okay"; -}; - -&fpd_dma_chan1 { - status = "okay"; -}; - -&fpd_dma_chan2 { - status = "okay"; -}; - -&fpd_dma_chan3 { - status = "okay"; -}; - -&fpd_dma_chan4 { - status = "okay"; -}; - -&fpd_dma_chan5 { - status = "okay"; -}; - -&fpd_dma_chan6 { - status = "okay"; -}; - -&fpd_dma_chan7 { - status = "okay"; -}; - -&fpd_dma_chan8 { - status = "okay"; -}; - -&gem3 { - status = "okay"; - phy-handle = <&phy0>; - phy-mode = "rgmii-id"; - phy0: ethernet-phy@21 { - reg = <21>; - ti,rx-internal-delay = <0x8>; - ti,tx-internal-delay = <0xa>; - ti,fifo-depth = <0x1>; - ti,dp83867-rxctrl-strap-quirk; - }; -}; - -&gpio { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - clock-frequency = <400000>; - - tca6416_u97: gpio@20 { - compatible = "ti,tca6416"; - reg = <0x20>; - gpio-controller; /* IRQ not connected */ - #gpio-cells = <2>; - gpio-line-names = "PS_GTR_LAN_SEL0", "PS_GTR_LAN_SEL1", "PS_GTR_LAN_SEL2", "PS_GTR_LAN_SEL3", - "PCI_CLK_DIR_SEL", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", - "", "", "", "", "", "", "", "", ""; - gtr-sel0 { - gpio-hog; - gpios = <0 0>; - output-low; /* PCIE = 0, DP = 1 */ - line-name = "sel0"; - }; - gtr-sel1 { - gpio-hog; - gpios = <1 0>; - output-high; /* PCIE = 0, DP = 1 */ - line-name = "sel1"; - }; - gtr-sel2 { - gpio-hog; - gpios = <2 0>; - output-high; /* PCIE = 0, USB0 = 1 */ - line-name = "sel2"; - }; - gtr-sel3 { - gpio-hog; - gpios = <3 0>; - output-high; /* PCIE = 0, SATA = 1 */ - line-name = "sel3"; - }; - }; - - tca6416_u61: gpio@21 { - compatible = "ti,tca6416"; - reg = <0x21>; - gpio-controller; /* IRQ not connected */ - #gpio-cells = <2>; - gpio-line-names = "VCCPSPLL_EN", "MGTRAVCC_EN", "MGTRAVTT_EN", "VCCPSDDRPLL_EN", "MIO26_PMU_INPUT_LS", - "PL_PMBUS_ALERT", "PS_PMBUS_ALERT", "MAXIM_PMBUS_ALERT", "PL_DDR4_VTERM_EN", - "PL_DDR4_VPP_2V5_EN", "PS_DIMM_VDDQ_TO_PSVCCO_ON", "PS_DIMM_SUSPEND_EN", - "PS_DDR4_VTERM_EN", "PS_DDR4_VPP_2V5_EN", "", ""; - }; - - i2c-mux@75 { /* u60 */ - compatible = "nxp,pca9544"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x75>; - i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - /* PS_PMBUS */ - u76: ina226@40 { /* u76 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u76"; - reg = <0x40>; - shunt-resistor = <5000>; - }; - u77: ina226@41 { /* u77 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u77"; - reg = <0x41>; - shunt-resistor = <5000>; - }; - u78: ina226@42 { /* u78 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u78"; - reg = <0x42>; - shunt-resistor = <5000>; - }; - u87: ina226@43 { /* u87 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u87"; - reg = <0x43>; - shunt-resistor = <5000>; - }; - u85: ina226@44 { /* u85 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u85"; - reg = <0x44>; - shunt-resistor = <5000>; - }; - u86: ina226@45 { /* u86 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u86"; - reg = <0x45>; - shunt-resistor = <5000>; - }; - u93: ina226@46 { /* u93 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u93"; - reg = <0x46>; - shunt-resistor = <5000>; - }; - u88: ina226@47 { /* u88 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u88"; - reg = <0x47>; - shunt-resistor = <5000>; - }; - u15: ina226@4a { /* u15 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u15"; - reg = <0x4a>; - shunt-resistor = <5000>; - }; - u92: ina226@4b { /* u92 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u92"; - reg = <0x4b>; - shunt-resistor = <5000>; - }; - }; - i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - /* PL_PMBUS */ - u79: ina226@40 { /* u79 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u79"; - reg = <0x40>; - shunt-resistor = <2000>; - }; - u81: ina226@41 { /* u81 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u81"; - reg = <0x41>; - shunt-resistor = <5000>; - }; - u80: ina226@42 { /* u80 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u80"; - reg = <0x42>; - shunt-resistor = <5000>; - }; - u84: ina226@43 { /* u84 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u84"; - reg = <0x43>; - shunt-resistor = <5000>; - }; - u16: ina226@44 { /* u16 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u16"; - reg = <0x44>; - shunt-resistor = <5000>; - }; - u65: ina226@45 { /* u65 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u65"; - reg = <0x45>; - shunt-resistor = <5000>; - }; - u74: ina226@46 { /* u74 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u74"; - reg = <0x46>; - shunt-resistor = <5000>; - }; - u75: ina226@47 { /* u75 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u75"; - reg = <0x47>; - shunt-resistor = <5000>; - }; - }; - i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - /* MAXIM_PMBUS - 00 */ - max15301@a { /* u46 */ - compatible = "maxim,max15301"; - reg = <0xa>; - }; - max15303@b { /* u4 */ - compatible = "maxim,max15303"; - reg = <0xb>; - }; - max15303@10 { /* u13 */ - compatible = "maxim,max15303"; - reg = <0x10>; - }; - max15301@13 { /* u47 */ - compatible = "maxim,max15301"; - reg = <0x13>; - }; - max15303@14 { /* u7 */ - compatible = "maxim,max15303"; - reg = <0x14>; - }; - max15303@15 { /* u6 */ - compatible = "maxim,max15303"; - reg = <0x15>; - }; - max15303@16 { /* u10 */ - compatible = "maxim,max15303"; - reg = <0x16>; - }; - max15303@17 { /* u9 */ - compatible = "maxim,max15303"; - reg = <0x17>; - }; - max15301@18 { /* u63 */ - compatible = "maxim,max15301"; - reg = <0x18>; - }; - max15303@1a { /* u49 */ - compatible = "maxim,max15303"; - reg = <0x1a>; - }; - max15303@1d { /* u18 */ - compatible = "maxim,max15303"; - reg = <0x1d>; - }; - max15303@20 { /* u8 */ - compatible = "maxim,max15303"; - status = "disabled"; /* unreachable */ - reg = <0x20>; - }; - - max20751@72 { /* u95 */ - compatible = "maxim,max20751"; - reg = <0x72>; - }; - max20751@73 { /* u96 */ - compatible = "maxim,max20751"; - reg = <0x73>; - }; - }; - /* Bus 3 is not connected */ - }; -}; - -&i2c1 { - status = "okay"; - clock-frequency = <400000>; - - /* PL i2c via PCA9306 - u45 */ - i2c-mux@74 { /* u34 */ - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x74>; - i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - /* - * IIC_EEPROM 1kB memory which uses 256B blocks - * where every block has different address. - * 0 - 256B address 0x54 - * 256B - 512B address 0x55 - * 512B - 768B address 0x56 - * 768B - 1024B address 0x57 - */ - eeprom: eeprom@54 { /* u23 */ - compatible = "atmel,24c08"; - reg = <0x54>; - }; - }; - i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - si5341: clock-generator@36 { /* SI5341 - u69 */ - reg = <0x36>; - }; - - }; - i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - si570_1: clock-generator@5d { /* USER SI570 - u42 */ - #clock-cells = <0>; - compatible = "silabs,si570"; - reg = <0x5d>; - temperature-stability = <50>; - factory-fout = <300000000>; - clock-frequency = <300000000>; - clock-output-names = "si570_user"; - }; - }; - i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ - #clock-cells = <0>; - compatible = "silabs,si570"; - reg = <0x5d>; - temperature-stability = <50>; /* copy from zc702 */ - factory-fout = <156250000>; - clock-frequency = <148500000>; - clock-output-names = "si570_mgt"; - }; - }; - i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - si5328: clock-generator@69 {/* SI5328 - u20 */ - reg = <0x69>; - /* - * Chip has interrupt present connected to PL - * interrupt-parent = <&>; - * interrupts = <>; - */ - }; - }; - /* 5 - 7 unconnected */ - }; - - i2c-mux@75 { - compatible = "nxp,pca9548"; /* u135 */ - #address-cells = <1>; - #size-cells = <0>; - reg = <0x75>; - - i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - /* HPC0_IIC */ - }; - i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - /* HPC1_IIC */ - }; - i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - /* SYSMON */ - }; - i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - /* DDR4 SODIMM */ - }; - i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - /* SEP 3 */ - }; - i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - /* SEP 2 */ - }; - i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - /* SEP 1 */ - }; - i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - /* SEP 0 */ - }; - }; -}; - -&pcie { - status = "okay"; -}; - -&rtc { - status = "okay"; -}; - -&sata { - status = "okay"; - /* SATA OOB timing settings */ - ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; - ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; - ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; - ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; - ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; - ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; - ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; - ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; -}; - -/* SD1 with level shifter */ -&sdhci1 { - status = "okay"; - no-1-8-v; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -/* ULPI SMSC USB3320 */ -&usb0 { - status = "okay"; - dr_mode = "host"; -}; - -&watchdog0 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/xilinx/zynqmp-zcu102-revB.dts b/sys/gnu/dts/arm64/xilinx/zynqmp-zcu102-revB.dts deleted file mode 100644 index d9ad8a4b20d..00000000000 --- a/sys/gnu/dts/arm64/xilinx/zynqmp-zcu102-revB.dts +++ /dev/null @@ -1,41 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * dts file for Xilinx ZynqMP ZCU102 RevB - * - * (C) Copyright 2016 - 2018, Xilinx, Inc. - * - * Michal Simek - */ - -#include "zynqmp-zcu102-revA.dts" - -/ { - model = "ZynqMP ZCU102 RevB"; - compatible = "xlnx,zynqmp-zcu102-revB", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; -}; - -&gem3 { - phy-handle = <&phyc>; - phyc: ethernet-phy@c { - reg = <0xc>; - ti,rx-internal-delay = <0x8>; - ti,tx-internal-delay = <0xa>; - ti,fifo-depth = <0x1>; - ti,dp83867-rxctrl-strap-quirk; - }; - /* Cleanup from RevA */ - /delete-node/ ethernet-phy@21; -}; - -/* Fix collision with u61 */ -&i2c0 { - i2c-mux@75 { - i2c@2 { - max15303@1b { /* u8 */ - compatible = "maxim,max15303"; - reg = <0x1b>; - }; - /delete-node/ max15303@20; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/xilinx/zynqmp-zcu104-revA.dts b/sys/gnu/dts/arm64/xilinx/zynqmp-zcu104-revA.dts deleted file mode 100644 index 7a4614e3f5f..00000000000 --- a/sys/gnu/dts/arm64/xilinx/zynqmp-zcu104-revA.dts +++ /dev/null @@ -1,197 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * dts file for Xilinx ZynqMP ZCU104 - * - * (C) Copyright 2017 - 2019, Xilinx, Inc. - * - * Michal Simek - */ - -/dts-v1/; - -#include "zynqmp.dtsi" -#include "zynqmp-clk-ccf.dtsi" -#include - -/ { - model = "ZynqMP ZCU104 RevA"; - compatible = "xlnx,zynqmp-zcu104-revA", "xlnx,zynqmp-zcu104", "xlnx,zynqmp"; - - aliases { - ethernet0 = &gem3; - i2c0 = &i2c1; - mmc0 = &sdhci1; - rtc0 = &rtc; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &dcc; - }; - - chosen { - bootargs = "earlycon"; - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; -}; - -&can1 { - status = "okay"; -}; - -&dcc { - status = "okay"; -}; - -&gem3 { - status = "okay"; - phy-handle = <&phy0>; - phy-mode = "rgmii-id"; - phy0: ethernet-phy@c { - reg = <0xc>; - ti,rx-internal-delay = <0x8>; - ti,tx-internal-delay = <0xa>; - ti,fifo-depth = <0x1>; - ti,dp83867-rxctrl-strap-quirk; - }; -}; - -&gpio { - status = "okay"; -}; - -&i2c1 { - status = "okay"; - clock-frequency = <400000>; - - /* Another connection to this bus via PL i2c via PCA9306 - u45 */ - i2c-mux@74 { /* u34 */ - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x74>; - i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - /* - * IIC_EEPROM 1kB memory which uses 256B blocks - * where every block has different address. - * 0 - 256B address 0x54 - * 256B - 512B address 0x55 - * 512B - 768B address 0x56 - * 768B - 1024B address 0x57 - */ - eeprom@54 { /* u23 */ - compatible = "atmel,24c08"; - reg = <0x54>; - #address-cells = <1>; - #size-cells = <1>; - }; - }; - - i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - clock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */ - reg = <0x6c>; - }; - }; - - i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - irps5401_43: irps54012@43 { /* IRPS5401 - u175 */ - reg = <0x43>; - }; - irps5401_4d: irps54012@4d { /* IRPS5401 - u180 */ - reg = <0x4d>; - }; - }; - - i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - tca6416_u97: gpio@20 { - compatible = "ti,tca6416"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - /* - * IRQ not connected - * Lines: - * 0 - IRPS5401_ALERT_B - * 1 - HDMI_8T49N241_INT_ALM - * 2 - MAX6643_OT_B - * 3 - MAX6643_FANFAIL_B - * 5 - IIC_MUX_RESET_B - * 6 - GEM3_EXP_RESET_B - * 7 - FMC_LPC_PRSNT_M2C_B - * 4, 10 - 17 - not connected - */ - }; - }; - - i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - - i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - - /* 3, 6 not connected */ - }; -}; - -&rtc { - status = "okay"; -}; - -&sata { - status = "okay"; - /* SATA OOB timing settings */ - ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; - ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; - ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; - ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; - ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; - ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; - ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; - ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; -}; - -/* SD1 with level shifter */ -&sdhci1 { - status = "okay"; - no-1-8-v; - disable-wp; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -/* ULPI SMSC USB3320 */ -&usb0 { - status = "okay"; - dr_mode = "host"; -}; - -&watchdog0 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/xilinx/zynqmp-zcu106-revA.dts b/sys/gnu/dts/arm64/xilinx/zynqmp-zcu106-revA.dts deleted file mode 100644 index 6e9efe23383..00000000000 --- a/sys/gnu/dts/arm64/xilinx/zynqmp-zcu106-revA.dts +++ /dev/null @@ -1,633 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * dts file for Xilinx ZynqMP ZCU106 - * - * (C) Copyright 2016 - 2019, Xilinx, Inc. - * - * Michal Simek - */ - -/dts-v1/; - -#include "zynqmp.dtsi" -#include "zynqmp-clk-ccf.dtsi" -#include -#include - -/ { - model = "ZynqMP ZCU106 RevA"; - compatible = "xlnx,zynqmp-zcu106-revA", "xlnx,zynqmp-zcu106", "xlnx,zynqmp"; - - aliases { - ethernet0 = &gem3; - i2c0 = &i2c0; - i2c1 = &i2c1; - mmc0 = &sdhci1; - rtc0 = &rtc; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &dcc; - }; - - chosen { - bootargs = "earlycon"; - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; - }; - - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - sw19 { - label = "sw19"; - gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; - linux,code = ; - wakeup-source; - autorepeat; - }; - }; - - leds { - compatible = "gpio-leds"; - heartbeat-led { - label = "heartbeat"; - gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - ina226-u76 { - compatible = "iio-hwmon"; - io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>; - }; - ina226-u77 { - compatible = "iio-hwmon"; - io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>; - }; - ina226-u78 { - compatible = "iio-hwmon"; - io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>; - }; - ina226-u87 { - compatible = "iio-hwmon"; - io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>; - }; - ina226-u85 { - compatible = "iio-hwmon"; - io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>; - }; - ina226-u86 { - compatible = "iio-hwmon"; - io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>; - }; - ina226-u93 { - compatible = "iio-hwmon"; - io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>; - }; - ina226-u88 { - compatible = "iio-hwmon"; - io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>; - }; - ina226-u15 { - compatible = "iio-hwmon"; - io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>; - }; - ina226-u92 { - compatible = "iio-hwmon"; - io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>; - }; - ina226-u79 { - compatible = "iio-hwmon"; - io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; - }; - ina226-u81 { - compatible = "iio-hwmon"; - io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>; - }; - ina226-u80 { - compatible = "iio-hwmon"; - io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>; - }; - ina226-u84 { - compatible = "iio-hwmon"; - io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>; - }; - ina226-u16 { - compatible = "iio-hwmon"; - io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>; - }; - ina226-u65 { - compatible = "iio-hwmon"; - io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>; - }; - ina226-u74 { - compatible = "iio-hwmon"; - io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>; - }; - ina226-u75 { - compatible = "iio-hwmon"; - io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>; - }; -}; - -&can1 { - status = "okay"; -}; - -&dcc { - status = "okay"; -}; - -/* fpd_dma clk 667MHz, lpd_dma 500MHz */ -&fpd_dma_chan1 { - status = "okay"; -}; - -&fpd_dma_chan2 { - status = "okay"; -}; - -&fpd_dma_chan3 { - status = "okay"; -}; - -&fpd_dma_chan4 { - status = "okay"; -}; - -&fpd_dma_chan5 { - status = "okay"; -}; - -&fpd_dma_chan6 { - status = "okay"; -}; - -&fpd_dma_chan7 { - status = "okay"; -}; - -&fpd_dma_chan8 { - status = "okay"; -}; - -&gem3 { - status = "okay"; - phy-handle = <&phy0>; - phy-mode = "rgmii-id"; - phy0: ethernet-phy@c { - reg = <0xc>; - ti,rx-internal-delay = <0x8>; - ti,tx-internal-delay = <0xa>; - ti,fifo-depth = <0x1>; - ti,dp83867-rxctrl-strap-quirk; - }; -}; - -&gpio { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - clock-frequency = <400000>; - - tca6416_u97: gpio@20 { - compatible = "ti,tca6416"; - reg = <0x20>; - gpio-controller; /* interrupt not connected */ - #gpio-cells = <2>; - /* - * IRQ not connected - * Lines: - * 0 - SFP_SI5328_INT_ALM - * 1 - HDMI_SI5328_INT_ALM - * 5 - IIC_MUX_RESET_B - * 6 - GEM3_EXP_RESET_B - * 10 - FMC_HPC0_PRSNT_M2C_B - * 11 - FMC_HPC1_PRSNT_M2C_B - * 2-4, 7, 12-17 - not connected - */ - }; - - tca6416_u61: gpio@21 { - compatible = "ti,tca6416"; - reg = <0x21>; - gpio-controller; - #gpio-cells = <2>; - /* - * IRQ not connected - * Lines: - * 0 - VCCPSPLL_EN - * 1 - MGTRAVCC_EN - * 2 - MGTRAVTT_EN - * 3 - VCCPSDDRPLL_EN - * 4 - MIO26_PMU_INPUT_LS - * 5 - PL_PMBUS_ALERT - * 6 - PS_PMBUS_ALERT - * 7 - MAXIM_PMBUS_ALERT - * 10 - PL_DDR4_VTERM_EN - * 11 - PL_DDR4_VPP_2V5_EN - * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON - * 13 - PS_DIMM_SUSPEND_EN - * 14 - PS_DDR4_VTERM_EN - * 15 - PS_DDR4_VPP_2V5_EN - * 16 - 17 - not connected - */ - }; - - i2c-mux@75 { /* u60 */ - compatible = "nxp,pca9544"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x75>; - i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - /* PS_PMBUS */ - u76: ina226@40 { /* u76 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u76"; - reg = <0x40>; - shunt-resistor = <5000>; - }; - u77: ina226@41 { /* u77 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u77"; - reg = <0x41>; - shunt-resistor = <5000>; - }; - u78: ina226@42 { /* u78 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u78"; - reg = <0x42>; - shunt-resistor = <5000>; - }; - u87: ina226@43 { /* u87 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u87"; - reg = <0x43>; - shunt-resistor = <5000>; - }; - u85: ina226@44 { /* u85 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u85"; - reg = <0x44>; - shunt-resistor = <5000>; - }; - u86: ina226@45 { /* u86 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u86"; - reg = <0x45>; - shunt-resistor = <5000>; - }; - u93: ina226@46 { /* u93 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u93"; - reg = <0x46>; - shunt-resistor = <5000>; - }; - u88: ina226@47 { /* u88 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u88"; - reg = <0x47>; - shunt-resistor = <5000>; - }; - u15: ina226@4a { /* u15 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u15"; - reg = <0x4a>; - shunt-resistor = <5000>; - }; - u92: ina226@4b { /* u92 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u92"; - reg = <0x4b>; - shunt-resistor = <5000>; - }; - }; - i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - /* PL_PMBUS */ - u79: ina226@40 { /* u79 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u79"; - reg = <0x40>; - shunt-resistor = <2000>; - }; - u81: ina226@41 { /* u81 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u81"; - reg = <0x41>; - shunt-resistor = <5000>; - }; - u80: ina226@42 { /* u80 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u80"; - reg = <0x42>; - shunt-resistor = <5000>; - }; - u84: ina226@43 { /* u84 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u84"; - reg = <0x43>; - shunt-resistor = <5000>; - }; - u16: ina226@44 { /* u16 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u16"; - reg = <0x44>; - shunt-resistor = <5000>; - }; - u65: ina226@45 { /* u65 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u65"; - reg = <0x45>; - shunt-resistor = <5000>; - }; - u74: ina226@46 { /* u74 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u74"; - reg = <0x46>; - shunt-resistor = <5000>; - }; - u75: ina226@47 { /* u75 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u75"; - reg = <0x47>; - shunt-resistor = <5000>; - }; - }; - i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - /* MAXIM_PMBUS - 00 */ - max15301@a { /* u46 */ - compatible = "maxim,max15301"; - reg = <0xa>; - }; - max15303@b { /* u4 */ - compatible = "maxim,max15303"; - reg = <0xb>; - }; - max15303@10 { /* u13 */ - compatible = "maxim,max15303"; - reg = <0x10>; - }; - max15301@13 { /* u47 */ - compatible = "maxim,max15301"; - reg = <0x13>; - }; - max15303@14 { /* u7 */ - compatible = "maxim,max15303"; - reg = <0x14>; - }; - max15303@15 { /* u6 */ - compatible = "maxim,max15303"; - reg = <0x15>; - }; - max15303@16 { /* u10 */ - compatible = "maxim,max15303"; - reg = <0x16>; - }; - max15303@17 { /* u9 */ - compatible = "maxim,max15303"; - reg = <0x17>; - }; - max15301@18 { /* u63 */ - compatible = "maxim,max15301"; - reg = <0x18>; - }; - max15303@1a { /* u49 */ - compatible = "maxim,max15303"; - reg = <0x1a>; - }; - max15303@1b { /* u8 */ - compatible = "maxim,max15303"; - reg = <0x1b>; - }; - max15303@1d { /* u18 */ - compatible = "maxim,max15303"; - reg = <0x1d>; - }; - - max20751@72 { /* u95 */ - compatible = "maxim,max20751"; - reg = <0x72>; - }; - max20751@73 { /* u96 */ - compatible = "maxim,max20751"; - reg = <0x73>; - }; - }; - /* Bus 3 is not connected */ - }; -}; - -&i2c1 { - status = "okay"; - clock-frequency = <400000>; - - /* PL i2c via PCA9306 - u45 */ - i2c-mux@74 { /* u34 */ - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x74>; - i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - /* - * IIC_EEPROM 1kB memory which uses 256B blocks - * where every block has different address. - * 0 - 256B address 0x54 - * 256B - 512B address 0x55 - * 512B - 768B address 0x56 - * 768B - 1024B address 0x57 - */ - eeprom: eeprom@54 { /* u23 */ - compatible = "atmel,24c08"; - reg = <0x54>; - }; - }; - i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - si5341: clock-generator@36 { /* SI5341 - u69 */ - reg = <0x36>; - }; - - }; - i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - si570_1: clock-generator@5d { /* USER SI570 - u42 */ - #clock-cells = <0>; - compatible = "silabs,si570"; - reg = <0x5d>; - temperature-stability = <50>; - factory-fout = <300000000>; - clock-frequency = <300000000>; - clock-output-names = "si570_user"; - }; - }; - i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ - #clock-cells = <0>; - compatible = "silabs,si570"; - reg = <0x5d>; - temperature-stability = <50>; /* copy from zc702 */ - factory-fout = <156250000>; - clock-frequency = <148500000>; - clock-output-names = "si570_mgt"; - }; - }; - i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - si5328: clock-generator@69 {/* SI5328 - u20 */ - reg = <0x69>; - }; - }; - i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; /* FAN controller */ - temp@4c {/* lm96163 - u128 */ - compatible = "national,lm96163"; - reg = <0x4c>; - }; - }; - /* 6 - 7 unconnected */ - }; - - i2c-mux@75 { - compatible = "nxp,pca9548"; /* u135 */ - #address-cells = <1>; - #size-cells = <0>; - reg = <0x75>; - - i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - /* HPC0_IIC */ - }; - i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - /* HPC1_IIC */ - }; - i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - /* SYSMON */ - }; - i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - /* DDR4 SODIMM */ - }; - i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - /* SEP 3 */ - }; - i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - /* SEP 2 */ - }; - i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - /* SEP 1 */ - }; - i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - /* SEP 0 */ - }; - }; -}; - -&rtc { - status = "okay"; -}; - -&sata { - status = "okay"; - /* SATA OOB timing settings */ - ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; - ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; - ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; - ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; - ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; - ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; - ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; - ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; -}; - -/* SD1 with level shifter */ -&sdhci1 { - status = "okay"; - no-1-8-v; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -/* ULPI SMSC USB3320 */ -&usb0 { - status = "okay"; - dr_mode = "host"; -}; - -&watchdog0 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/xilinx/zynqmp-zcu111-revA.dts b/sys/gnu/dts/arm64/xilinx/zynqmp-zcu111-revA.dts deleted file mode 100644 index 2e92634c77f..00000000000 --- a/sys/gnu/dts/arm64/xilinx/zynqmp-zcu111-revA.dts +++ /dev/null @@ -1,531 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * dts file for Xilinx ZynqMP ZCU111 - * - * (C) Copyright 2017 - 2019, Xilinx, Inc. - * - * Michal Simek - */ - -/dts-v1/; - -#include "zynqmp.dtsi" -#include "zynqmp-clk-ccf.dtsi" -#include -#include - -/ { - model = "ZynqMP ZCU111 RevA"; - compatible = "xlnx,zynqmp-zcu111-revA", "xlnx,zynqmp-zcu111", "xlnx,zynqmp"; - - aliases { - ethernet0 = &gem3; - i2c0 = &i2c0; - i2c1 = &i2c1; - mmc0 = &sdhci1; - rtc0 = &rtc; - serial0 = &uart0; - serial1 = &dcc; - }; - - chosen { - bootargs = "earlycon"; - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; - /* Another 4GB connected to PL */ - }; - - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - sw19 { - label = "sw19"; - gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; - linux,code = ; - wakeup-source; - autorepeat; - }; - }; - - leds { - compatible = "gpio-leds"; - heartbeat-led { - label = "heartbeat"; - gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - ina226-u67 { - compatible = "iio-hwmon"; - io-channels = <&u67 0>, <&u67 1>, <&u67 2>, <&u67 3>; - }; - ina226-u59 { - compatible = "iio-hwmon"; - io-channels = <&u59 0>, <&u59 1>, <&u59 2>, <&u59 3>; - }; - ina226-u61 { - compatible = "iio-hwmon"; - io-channels = <&u61 0>, <&u61 1>, <&u61 2>, <&u61 3>; - }; - ina226-u60 { - compatible = "iio-hwmon"; - io-channels = <&u60 0>, <&u60 1>, <&u60 2>, <&u60 3>; - }; - ina226-u64 { - compatible = "iio-hwmon"; - io-channels = <&u64 0>, <&u64 1>, <&u64 2>, <&u64 3>; - }; - ina226-u69 { - compatible = "iio-hwmon"; - io-channels = <&u69 0>, <&u69 1>, <&u69 2>, <&u69 3>; - }; - ina226-u66 { - compatible = "iio-hwmon"; - io-channels = <&u66 0>, <&u66 1>, <&u66 2>, <&u66 3>; - }; - ina226-u65 { - compatible = "iio-hwmon"; - io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>; - }; - ina226-u63 { - compatible = "iio-hwmon"; - io-channels = <&u63 0>, <&u63 1>, <&u63 2>, <&u63 3>; - }; - ina226-u3 { - compatible = "iio-hwmon"; - io-channels = <&u3 0>, <&u3 1>, <&u3 2>, <&u3 3>; - }; - ina226-u71 { - compatible = "iio-hwmon"; - io-channels = <&u71 0>, <&u71 1>, <&u71 2>, <&u71 3>; - }; - ina226-u77 { - compatible = "iio-hwmon"; - io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>; - }; - ina226-u73 { - compatible = "iio-hwmon"; - io-channels = <&u73 0>, <&u73 1>, <&u73 2>, <&u73 3>; - }; - ina226-u79 { - compatible = "iio-hwmon"; - io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; - }; -}; - -&dcc { - status = "okay"; -}; - -&fpd_dma_chan1 { - status = "okay"; -}; - -&fpd_dma_chan2 { - status = "okay"; -}; - -&fpd_dma_chan3 { - status = "okay"; -}; - -&fpd_dma_chan4 { - status = "okay"; -}; - -&fpd_dma_chan5 { - status = "okay"; -}; - -&fpd_dma_chan6 { - status = "okay"; -}; - -&fpd_dma_chan7 { - status = "okay"; -}; - -&fpd_dma_chan8 { - status = "okay"; -}; - -&gem3 { - status = "okay"; - phy-handle = <&phy0>; - phy-mode = "rgmii-id"; - phy0: ethernet-phy@c { - reg = <0xc>; - ti,rx-internal-delay = <0x8>; - ti,tx-internal-delay = <0xa>; - ti,fifo-depth = <0x1>; - ti,dp83867-rxctrl-strap-quirk; - }; -}; - -&gpio { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - clock-frequency = <400000>; - - tca6416_u22: gpio@20 { - compatible = "ti,tca6416"; - reg = <0x20>; - gpio-controller; /* interrupt not connected */ - #gpio-cells = <2>; - /* - * IRQ not connected - * Lines: - * 0 - MAX6643_OT_B - * 1 - MAX6643_FANFAIL_B - * 2 - MIO26_PMU_INPUT_LS - * 4 - SFP_SI5382_INT_ALM - * 5 - IIC_MUX_RESET_B - * 6 - GEM3_EXP_RESET_B - * 10 - FMCP_HSPC_PRSNT_M2C_B - * 11 - CLK_SPI_MUX_SEL0 - * 12 - CLK_SPI_MUX_SEL1 - * 16 - IRPS5401_ALERT_B - * 17 - INA226_PMBUS_ALERT - * 3, 7, 13-15 - not connected - */ - }; - - i2c-mux@75 { /* u23 */ - compatible = "nxp,pca9544"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x75>; - i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - /* PS_PMBUS */ - /* PMBUS_ALERT done via pca9544 */ - u67: ina226@40 { /* u67 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u67"; - reg = <0x40>; - shunt-resistor = <2000>; - }; - u59: ina226@41 { /* u59 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u59"; - reg = <0x41>; - shunt-resistor = <5000>; - }; - u61: ina226@42 { /* u61 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u61"; - reg = <0x42>; - shunt-resistor = <5000>; - }; - u60: ina226@43 { /* u60 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u60"; - reg = <0x43>; - shunt-resistor = <5000>; - }; - u64: ina226@45 { /* u64 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u64"; - reg = <0x45>; - shunt-resistor = <5000>; - }; - u69: ina226@46 { /* u69 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u69"; - reg = <0x46>; - shunt-resistor = <2000>; - }; - u66: ina226@47 { /* u66 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u66"; - reg = <0x47>; - shunt-resistor = <5000>; - }; - u65: ina226@48 { /* u65 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u65"; - reg = <0x48>; - shunt-resistor = <5000>; - }; - u63: ina226@49 { /* u63 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u63"; - reg = <0x49>; - shunt-resistor = <5000>; - }; - u3: ina226@4a { /* u3 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u3"; - reg = <0x4a>; - shunt-resistor = <5000>; - }; - u71: ina226@4b { /* u71 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u71"; - reg = <0x4b>; - shunt-resistor = <5000>; - }; - u77: ina226@4c { /* u77 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u77"; - reg = <0x4c>; - shunt-resistor = <5000>; - }; - u73: ina226@4d { /* u73 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u73"; - reg = <0x4d>; - shunt-resistor = <5000>; - }; - u79: ina226@4e { /* u79 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u79"; - reg = <0x4e>; - shunt-resistor = <5000>; - }; - }; - i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - /* NC */ - }; - i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - irps5401_43: irps54012@43 { /* IRPS5401 - u53 check these */ - reg = <0x43>; - }; - irps5401_44: irps54012@44 { /* IRPS5401 - u55 */ - reg = <0x44>; - }; - irps5401_45: irps54012@45 { /* IRPS5401 - u57 */ - reg = <0x45>; - }; - /* u68 IR38064 +0 */ - /* u70 IR38060 +1 */ - /* u74 IR38060 +2 */ - /* u75 IR38060 +6 */ - /* J19 header too */ - - }; - i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - /* SYSMON */ - }; - }; -}; - -&i2c1 { - status = "okay"; - clock-frequency = <400000>; - - i2c-mux@74 { /* u26 */ - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x74>; - i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - /* - * IIC_EEPROM 1kB memory which uses 256B blocks - * where every block has different address. - * 0 - 256B address 0x54 - * 256B - 512B address 0x55 - * 512B - 768B address 0x56 - * 768B - 1024B address 0x57 - */ - eeprom: eeprom@54 { /* u88 */ - compatible = "atmel,24c08"; - reg = <0x54>; - }; - }; - i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - si5341: clock-generator@36 { /* SI5341 - u46 */ - reg = <0x36>; - }; - - }; - i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - si570_1: clock-generator@5d { /* USER SI570 - u47 */ - #clock-cells = <0>; - compatible = "silabs,si570"; - reg = <0x5d>; - temperature-stability = <50>; - factory-fout = <300000000>; - clock-frequency = <300000000>; - clock-output-names = "si570_user"; - }; - }; - i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - si570_2: clock-generator@5d { /* USER MGT SI570 - u49 */ - #clock-cells = <0>; - compatible = "silabs,si570"; - reg = <0x5d>; - temperature-stability = <50>; - factory-fout = <156250000>; - clock-frequency = <156250000>; - clock-output-names = "si570_mgt"; - }; - }; - i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - si5328: clock-generator@69 { /* SI5328 - u48 */ - reg = <0x69>; - }; - }; - i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - sc18is603@2f { /* sc18is602 - u93 */ - compatible = "nxp,sc18is603"; - reg = <0x2f>; - /* 4 gpios for CS not handled by driver */ - /* - * USB2ANY cable or - * LMK04208 - u90 or - * LMX2594 - u102 or - * LMX2594 - u103 or - * LMX2594 - u104 - */ - }; - }; - i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - /* FMC connector */ - }; - /* 7 NC */ - }; - - i2c-mux@75 { - compatible = "nxp,pca9548"; /* u27 */ - #address-cells = <1>; - #size-cells = <0>; - reg = <0x75>; - - i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - /* FMCP_HSPC_IIC */ - }; - i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - /* NC */ - }; - i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - /* SYSMON */ - }; - i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - /* DDR4 SODIMM */ - }; - i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - /* SFP3 */ - }; - i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - /* SFP2 */ - }; - i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - /* SFP1 */ - }; - i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - /* SFP0 */ - }; - }; -}; - -&rtc { - status = "okay"; -}; - -&sata { - status = "okay"; - /* SATA OOB timing settings */ - ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; - ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; - ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; - ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; - ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; - ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; - ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; - ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; -}; - -/* SD1 with level shifter */ -&sdhci1 { - status = "okay"; - no-1-8-v; -}; - -&uart0 { - status = "okay"; -}; - -/* ULPI SMSC USB3320 */ -&usb0 { - status = "okay"; - dr_mode = "host"; -}; diff --git a/sys/gnu/dts/arm64/xilinx/zynqmp.dtsi b/sys/gnu/dts/arm64/xilinx/zynqmp.dtsi deleted file mode 100644 index 26d926eb143..00000000000 --- a/sys/gnu/dts/arm64/xilinx/zynqmp.dtsi +++ /dev/null @@ -1,726 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * dts file for Xilinx ZynqMP - * - * (C) Copyright 2014 - 2019, Xilinx, Inc. - * - * Michal Simek - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - */ - -#include - -/ { - compatible = "xlnx,zynqmp"; - #address-cells = <2>; - #size-cells = <2>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - enable-method = "psci"; - operating-points-v2 = <&cpu_opp_table>; - reg = <0x0>; - cpu-idle-states = <&CPU_SLEEP_0>; - }; - - cpu1: cpu@1 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - enable-method = "psci"; - reg = <0x1>; - operating-points-v2 = <&cpu_opp_table>; - cpu-idle-states = <&CPU_SLEEP_0>; - }; - - cpu2: cpu@2 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - enable-method = "psci"; - reg = <0x2>; - operating-points-v2 = <&cpu_opp_table>; - cpu-idle-states = <&CPU_SLEEP_0>; - }; - - cpu3: cpu@3 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - enable-method = "psci"; - reg = <0x3>; - operating-points-v2 = <&cpu_opp_table>; - cpu-idle-states = <&CPU_SLEEP_0>; - }; - - idle-states { - entry-method = "psci"; - - CPU_SLEEP_0: cpu-sleep-0 { - compatible = "arm,idle-state"; - arm,psci-suspend-param = <0x40000000>; - local-timer-stop; - entry-latency-us = <300>; - exit-latency-us = <600>; - min-residency-us = <10000>; - }; - }; - }; - - cpu_opp_table: cpu-opp-table { - compatible = "operating-points-v2"; - opp-shared; - opp00 { - opp-hz = /bits/ 64 <1199999988>; - opp-microvolt = <1000000>; - clock-latency-ns = <500000>; - }; - opp01 { - opp-hz = /bits/ 64 <599999994>; - opp-microvolt = <1000000>; - clock-latency-ns = <500000>; - }; - opp02 { - opp-hz = /bits/ 64 <399999996>; - opp-microvolt = <1000000>; - clock-latency-ns = <500000>; - }; - opp03 { - opp-hz = /bits/ 64 <299999997>; - opp-microvolt = <1000000>; - clock-latency-ns = <500000>; - }; - }; - - dcc: dcc { - compatible = "arm,dcc"; - status = "disabled"; - }; - - pmu { - compatible = "arm,armv8-pmuv3"; - interrupt-parent = <&gic>; - interrupts = <0 143 4>, - <0 144 4>, - <0 145 4>, - <0 146 4>; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - firmware { - zynqmp_firmware: zynqmp-firmware { - compatible = "xlnx,zynqmp-firmware"; - #power-domain-cells = <1>; - method = "smc"; - - zynqmp_power: zynqmp-power { - compatible = "xlnx,zynqmp-power"; - interrupt-parent = <&gic>; - interrupts = <0 35 4>; - }; - - zynqmp_clk: clock-controller { - u-boot,dm-pre-reloc; - #clock-cells = <1>; - compatible = "xlnx,zynqmp-clk"; - clocks = <&pss_ref_clk>, - <&video_clk>, - <&pss_alt_ref_clk>, - <&aux_ref_clk>, - <>_crx_ref_clk>; - clock-names = "pss_ref_clk", - "video_clk", - "pss_alt_ref_clk", - "aux_ref_clk", - "gt_crx_ref_clk"; - }; - - nvmem_firmware { - compatible = "xlnx,zynqmp-nvmem-fw"; - #address-cells = <1>; - #size-cells = <1>; - - soc_revision: soc_revision@0 { - reg = <0x0 0x4>; - }; - }; - - zynqmp_pcap: pcap { - compatible = "xlnx,zynqmp-pcap-fpga"; - }; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupt-parent = <&gic>; - interrupts = <1 13 0xf08>, - <1 14 0xf08>, - <1 11 0xf08>, - <1 10 0xf08>; - }; - - fpga_full: fpga-full { - compatible = "fpga-region"; - fpga-mgr = <&zynqmp_pcap>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - }; - - amba_apu: amba-apu@0 { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0 0 0xffffffff>; - - gic: interrupt-controller@f9010000 { - compatible = "arm,gic-400", "arm,cortex-a15-gic"; - #interrupt-cells = <3>; - reg = <0x0 0xf9010000 0x10000>, - <0x0 0xf9020000 0x20000>, - <0x0 0xf9040000 0x20000>, - <0x0 0xf9060000 0x20000>; - interrupt-controller; - interrupt-parent = <&gic>; - interrupts = <1 9 0xf04>; - }; - }; - - amba: amba { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - can0: can@ff060000 { - compatible = "xlnx,zynq-can-1.0"; - status = "disabled"; - clock-names = "can_clk", "pclk"; - reg = <0x0 0xff060000 0x0 0x1000>; - interrupts = <0 23 4>; - interrupt-parent = <&gic>; - tx-fifo-depth = <0x40>; - rx-fifo-depth = <0x40>; - power-domains = <&zynqmp_firmware PD_CAN_0>; - }; - - can1: can@ff070000 { - compatible = "xlnx,zynq-can-1.0"; - status = "disabled"; - clock-names = "can_clk", "pclk"; - reg = <0x0 0xff070000 0x0 0x1000>; - interrupts = <0 24 4>; - interrupt-parent = <&gic>; - tx-fifo-depth = <0x40>; - rx-fifo-depth = <0x40>; - power-domains = <&zynqmp_firmware PD_CAN_1>; - }; - - cci: cci@fd6e0000 { - compatible = "arm,cci-400"; - reg = <0x0 0xfd6e0000 0x0 0x9000>; - ranges = <0x0 0x0 0xfd6e0000 0x10000>; - #address-cells = <1>; - #size-cells = <1>; - - pmu@9000 { - compatible = "arm,cci-400-pmu,r1"; - reg = <0x9000 0x5000>; - interrupt-parent = <&gic>; - interrupts = <0 123 4>, - <0 123 4>, - <0 123 4>, - <0 123 4>, - <0 123 4>; - }; - }; - - /* GDMA */ - fpd_dma_chan1: dma@fd500000 { - status = "disabled"; - compatible = "xlnx,zynqmp-dma-1.0"; - reg = <0x0 0xfd500000 0x0 0x1000>; - interrupt-parent = <&gic>; - interrupts = <0 124 4>; - clock-names = "clk_main", "clk_apb"; - xlnx,bus-width = <128>; - power-domains = <&zynqmp_firmware PD_GDMA>; - }; - - fpd_dma_chan2: dma@fd510000 { - status = "disabled"; - compatible = "xlnx,zynqmp-dma-1.0"; - reg = <0x0 0xfd510000 0x0 0x1000>; - interrupt-parent = <&gic>; - interrupts = <0 125 4>; - clock-names = "clk_main", "clk_apb"; - xlnx,bus-width = <128>; - power-domains = <&zynqmp_firmware PD_GDMA>; - }; - - fpd_dma_chan3: dma@fd520000 { - status = "disabled"; - compatible = "xlnx,zynqmp-dma-1.0"; - reg = <0x0 0xfd520000 0x0 0x1000>; - interrupt-parent = <&gic>; - interrupts = <0 126 4>; - clock-names = "clk_main", "clk_apb"; - xlnx,bus-width = <128>; - power-domains = <&zynqmp_firmware PD_GDMA>; - }; - - fpd_dma_chan4: dma@fd530000 { - status = "disabled"; - compatible = "xlnx,zynqmp-dma-1.0"; - reg = <0x0 0xfd530000 0x0 0x1000>; - interrupt-parent = <&gic>; - interrupts = <0 127 4>; - clock-names = "clk_main", "clk_apb"; - xlnx,bus-width = <128>; - power-domains = <&zynqmp_firmware PD_GDMA>; - }; - - fpd_dma_chan5: dma@fd540000 { - status = "disabled"; - compatible = "xlnx,zynqmp-dma-1.0"; - reg = <0x0 0xfd540000 0x0 0x1000>; - interrupt-parent = <&gic>; - interrupts = <0 128 4>; - clock-names = "clk_main", "clk_apb"; - xlnx,bus-width = <128>; - power-domains = <&zynqmp_firmware PD_GDMA>; - }; - - fpd_dma_chan6: dma@fd550000 { - status = "disabled"; - compatible = "xlnx,zynqmp-dma-1.0"; - reg = <0x0 0xfd550000 0x0 0x1000>; - interrupt-parent = <&gic>; - interrupts = <0 129 4>; - clock-names = "clk_main", "clk_apb"; - xlnx,bus-width = <128>; - power-domains = <&zynqmp_firmware PD_GDMA>; - }; - - fpd_dma_chan7: dma@fd560000 { - status = "disabled"; - compatible = "xlnx,zynqmp-dma-1.0"; - reg = <0x0 0xfd560000 0x0 0x1000>; - interrupt-parent = <&gic>; - interrupts = <0 130 4>; - clock-names = "clk_main", "clk_apb"; - xlnx,bus-width = <128>; - power-domains = <&zynqmp_firmware PD_GDMA>; - }; - - fpd_dma_chan8: dma@fd570000 { - status = "disabled"; - compatible = "xlnx,zynqmp-dma-1.0"; - reg = <0x0 0xfd570000 0x0 0x1000>; - interrupt-parent = <&gic>; - interrupts = <0 131 4>; - clock-names = "clk_main", "clk_apb"; - xlnx,bus-width = <128>; - power-domains = <&zynqmp_firmware PD_GDMA>; - }; - - /* LPDDMA default allows only secured access. inorder to enable - * These dma channels, Users should ensure that these dma - * Channels are allowed for non secure access. - */ - lpd_dma_chan1: dma@ffa80000 { - status = "disabled"; - compatible = "xlnx,zynqmp-dma-1.0"; - reg = <0x0 0xffa80000 0x0 0x1000>; - interrupt-parent = <&gic>; - interrupts = <0 77 4>; - clock-names = "clk_main", "clk_apb"; - xlnx,bus-width = <64>; - power-domains = <&zynqmp_firmware PD_ADMA>; - }; - - lpd_dma_chan2: dma@ffa90000 { - status = "disabled"; - compatible = "xlnx,zynqmp-dma-1.0"; - reg = <0x0 0xffa90000 0x0 0x1000>; - interrupt-parent = <&gic>; - interrupts = <0 78 4>; - clock-names = "clk_main", "clk_apb"; - xlnx,bus-width = <64>; - power-domains = <&zynqmp_firmware PD_ADMA>; - }; - - lpd_dma_chan3: dma@ffaa0000 { - status = "disabled"; - compatible = "xlnx,zynqmp-dma-1.0"; - reg = <0x0 0xffaa0000 0x0 0x1000>; - interrupt-parent = <&gic>; - interrupts = <0 79 4>; - clock-names = "clk_main", "clk_apb"; - xlnx,bus-width = <64>; - power-domains = <&zynqmp_firmware PD_ADMA>; - }; - - lpd_dma_chan4: dma@ffab0000 { - status = "disabled"; - compatible = "xlnx,zynqmp-dma-1.0"; - reg = <0x0 0xffab0000 0x0 0x1000>; - interrupt-parent = <&gic>; - interrupts = <0 80 4>; - clock-names = "clk_main", "clk_apb"; - xlnx,bus-width = <64>; - power-domains = <&zynqmp_firmware PD_ADMA>; - }; - - lpd_dma_chan5: dma@ffac0000 { - status = "disabled"; - compatible = "xlnx,zynqmp-dma-1.0"; - reg = <0x0 0xffac0000 0x0 0x1000>; - interrupt-parent = <&gic>; - interrupts = <0 81 4>; - clock-names = "clk_main", "clk_apb"; - xlnx,bus-width = <64>; - power-domains = <&zynqmp_firmware PD_ADMA>; - }; - - lpd_dma_chan6: dma@ffad0000 { - status = "disabled"; - compatible = "xlnx,zynqmp-dma-1.0"; - reg = <0x0 0xffad0000 0x0 0x1000>; - interrupt-parent = <&gic>; - interrupts = <0 82 4>; - clock-names = "clk_main", "clk_apb"; - xlnx,bus-width = <64>; - power-domains = <&zynqmp_firmware PD_ADMA>; - }; - - lpd_dma_chan7: dma@ffae0000 { - status = "disabled"; - compatible = "xlnx,zynqmp-dma-1.0"; - reg = <0x0 0xffae0000 0x0 0x1000>; - interrupt-parent = <&gic>; - interrupts = <0 83 4>; - clock-names = "clk_main", "clk_apb"; - xlnx,bus-width = <64>; - power-domains = <&zynqmp_firmware PD_ADMA>; - }; - - lpd_dma_chan8: dma@ffaf0000 { - status = "disabled"; - compatible = "xlnx,zynqmp-dma-1.0"; - reg = <0x0 0xffaf0000 0x0 0x1000>; - interrupt-parent = <&gic>; - interrupts = <0 84 4>; - clock-names = "clk_main", "clk_apb"; - xlnx,bus-width = <64>; - power-domains = <&zynqmp_firmware PD_ADMA>; - }; - - mc: memory-controller@fd070000 { - compatible = "xlnx,zynqmp-ddrc-2.40a"; - reg = <0x0 0xfd070000 0x0 0x30000>; - interrupt-parent = <&gic>; - interrupts = <0 112 4>; - }; - - gem0: ethernet@ff0b0000 { - compatible = "cdns,zynqmp-gem", "cdns,gem"; - status = "disabled"; - interrupt-parent = <&gic>; - interrupts = <0 57 4>, <0 57 4>; - reg = <0x0 0xff0b0000 0x0 0x1000>; - clock-names = "pclk", "hclk", "tx_clk"; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&zynqmp_firmware PD_ETH_0>; - }; - - gem1: ethernet@ff0c0000 { - compatible = "cdns,zynqmp-gem", "cdns,gem"; - status = "disabled"; - interrupt-parent = <&gic>; - interrupts = <0 59 4>, <0 59 4>; - reg = <0x0 0xff0c0000 0x0 0x1000>; - clock-names = "pclk", "hclk", "tx_clk"; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&zynqmp_firmware PD_ETH_1>; - }; - - gem2: ethernet@ff0d0000 { - compatible = "cdns,zynqmp-gem", "cdns,gem"; - status = "disabled"; - interrupt-parent = <&gic>; - interrupts = <0 61 4>, <0 61 4>; - reg = <0x0 0xff0d0000 0x0 0x1000>; - clock-names = "pclk", "hclk", "tx_clk"; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&zynqmp_firmware PD_ETH_2>; - }; - - gem3: ethernet@ff0e0000 { - compatible = "cdns,zynqmp-gem", "cdns,gem"; - status = "disabled"; - interrupt-parent = <&gic>; - interrupts = <0 63 4>, <0 63 4>; - reg = <0x0 0xff0e0000 0x0 0x1000>; - clock-names = "pclk", "hclk", "tx_clk"; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&zynqmp_firmware PD_ETH_3>; - }; - - gpio: gpio@ff0a0000 { - compatible = "xlnx,zynqmp-gpio-1.0"; - status = "disabled"; - #gpio-cells = <0x2>; - gpio-controller; - interrupt-parent = <&gic>; - interrupts = <0 16 4>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x0 0xff0a0000 0x0 0x1000>; - power-domains = <&zynqmp_firmware PD_GPIO>; - }; - - i2c0: i2c@ff020000 { - compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; - status = "disabled"; - interrupt-parent = <&gic>; - interrupts = <0 17 4>; - reg = <0x0 0xff020000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&zynqmp_firmware PD_I2C_0>; - }; - - i2c1: i2c@ff030000 { - compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; - status = "disabled"; - interrupt-parent = <&gic>; - interrupts = <0 18 4>; - reg = <0x0 0xff030000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&zynqmp_firmware PD_I2C_1>; - }; - - pcie: pcie@fd0e0000 { - compatible = "xlnx,nwl-pcie-2.11"; - status = "disabled"; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - msi-controller; - device_type = "pci"; - interrupt-parent = <&gic>; - interrupts = <0 118 4>, - <0 117 4>, - <0 116 4>, - <0 115 4>, /* MSI_1 [63...32] */ - <0 114 4>; /* MSI_0 [31...0] */ - interrupt-names = "misc", "dummy", "intx", - "msi1", "msi0"; - msi-parent = <&pcie>; - reg = <0x0 0xfd0e0000 0x0 0x1000>, - <0x0 0xfd480000 0x0 0x1000>, - <0x80 0x00000000 0x0 0x1000000>; - reg-names = "breg", "pcireg", "cfg"; - ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */ - 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */ - bus-range = <0x00 0xff>; - interrupt-map-mask = <0x0 0x0 0x0 0x7>; - interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>, - <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, - <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, - <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; - power-domains = <&zynqmp_firmware PD_PCIE>; - pcie_intc: legacy-interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - }; - }; - - rtc: rtc@ffa60000 { - compatible = "xlnx,zynqmp-rtc"; - status = "disabled"; - reg = <0x0 0xffa60000 0x0 0x100>; - interrupt-parent = <&gic>; - interrupts = <0 26 4>, <0 27 4>; - interrupt-names = "alarm", "sec"; - calibration = <0x8000>; - }; - - sata: ahci@fd0c0000 { - compatible = "ceva,ahci-1v84"; - status = "disabled"; - reg = <0x0 0xfd0c0000 0x0 0x2000>; - interrupt-parent = <&gic>; - interrupts = <0 133 4>; - power-domains = <&zynqmp_firmware PD_SATA>; - }; - - sdhci0: mmc@ff160000 { - compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; - status = "disabled"; - interrupt-parent = <&gic>; - interrupts = <0 48 4>; - reg = <0x0 0xff160000 0x0 0x1000>; - clock-names = "clk_xin", "clk_ahb"; - #clock-cells = <1>; - clock-output-names = "clk_out_sd0", "clk_in_sd0"; - power-domains = <&zynqmp_firmware PD_SD_0>; - }; - - sdhci1: mmc@ff170000 { - compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; - status = "disabled"; - interrupt-parent = <&gic>; - interrupts = <0 49 4>; - reg = <0x0 0xff170000 0x0 0x1000>; - clock-names = "clk_xin", "clk_ahb"; - #clock-cells = <1>; - clock-output-names = "clk_out_sd1", "clk_in_sd1"; - power-domains = <&zynqmp_firmware PD_SD_1>; - }; - - smmu: smmu@fd800000 { - compatible = "arm,mmu-500"; - reg = <0x0 0xfd800000 0x0 0x20000>; - status = "disabled"; - #global-interrupts = <1>; - interrupt-parent = <&gic>; - interrupts = <0 155 4>, - <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, - <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, - <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, - <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>; - }; - - spi0: spi@ff040000 { - compatible = "cdns,spi-r1p6"; - status = "disabled"; - interrupt-parent = <&gic>; - interrupts = <0 19 4>; - reg = <0x0 0xff040000 0x0 0x1000>; - clock-names = "ref_clk", "pclk"; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&zynqmp_firmware PD_SPI_0>; - }; - - spi1: spi@ff050000 { - compatible = "cdns,spi-r1p6"; - status = "disabled"; - interrupt-parent = <&gic>; - interrupts = <0 20 4>; - reg = <0x0 0xff050000 0x0 0x1000>; - clock-names = "ref_clk", "pclk"; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&zynqmp_firmware PD_SPI_1>; - }; - - ttc0: timer@ff110000 { - compatible = "cdns,ttc"; - status = "disabled"; - interrupt-parent = <&gic>; - interrupts = <0 36 4>, <0 37 4>, <0 38 4>; - reg = <0x0 0xff110000 0x0 0x1000>; - timer-width = <32>; - power-domains = <&zynqmp_firmware PD_TTC_0>; - }; - - ttc1: timer@ff120000 { - compatible = "cdns,ttc"; - status = "disabled"; - interrupt-parent = <&gic>; - interrupts = <0 39 4>, <0 40 4>, <0 41 4>; - reg = <0x0 0xff120000 0x0 0x1000>; - timer-width = <32>; - power-domains = <&zynqmp_firmware PD_TTC_1>; - }; - - ttc2: timer@ff130000 { - compatible = "cdns,ttc"; - status = "disabled"; - interrupt-parent = <&gic>; - interrupts = <0 42 4>, <0 43 4>, <0 44 4>; - reg = <0x0 0xff130000 0x0 0x1000>; - timer-width = <32>; - power-domains = <&zynqmp_firmware PD_TTC_2>; - }; - - ttc3: timer@ff140000 { - compatible = "cdns,ttc"; - status = "disabled"; - interrupt-parent = <&gic>; - interrupts = <0 45 4>, <0 46 4>, <0 47 4>; - reg = <0x0 0xff140000 0x0 0x1000>; - timer-width = <32>; - power-domains = <&zynqmp_firmware PD_TTC_3>; - }; - - uart0: serial@ff000000 { - compatible = "cdns,uart-r1p12", "xlnx,xuartps"; - status = "disabled"; - interrupt-parent = <&gic>; - interrupts = <0 21 4>; - reg = <0x0 0xff000000 0x0 0x1000>; - clock-names = "uart_clk", "pclk"; - power-domains = <&zynqmp_firmware PD_UART_0>; - }; - - uart1: serial@ff010000 { - compatible = "cdns,uart-r1p12", "xlnx,xuartps"; - status = "disabled"; - interrupt-parent = <&gic>; - interrupts = <0 22 4>; - reg = <0x0 0xff010000 0x0 0x1000>; - clock-names = "uart_clk", "pclk"; - power-domains = <&zynqmp_firmware PD_UART_1>; - }; - - usb0: usb@fe200000 { - compatible = "snps,dwc3"; - status = "disabled"; - interrupt-parent = <&gic>; - interrupts = <0 65 4>; - reg = <0x0 0xfe200000 0x0 0x40000>; - clock-names = "clk_xin", "clk_ahb"; - power-domains = <&zynqmp_firmware PD_USB_0>; - }; - - usb1: usb@fe300000 { - compatible = "snps,dwc3"; - status = "disabled"; - interrupt-parent = <&gic>; - interrupts = <0 70 4>; - reg = <0x0 0xfe300000 0x0 0x40000>; - clock-names = "clk_xin", "clk_ahb"; - power-domains = <&zynqmp_firmware PD_USB_1>; - }; - - watchdog0: watchdog@fd4d0000 { - compatible = "cdns,wdt-r1p2"; - status = "disabled"; - interrupt-parent = <&gic>; - interrupts = <0 113 1>; - reg = <0x0 0xfd4d0000 0x0 0x1000>; - timeout-sec = <10>; - }; - }; -}; diff --git a/sys/gnu/dts/arm64/zte/zx296718-evb.dts b/sys/gnu/dts/arm64/zte/zx296718-evb.dts deleted file mode 100644 index cb2519ecd72..00000000000 --- a/sys/gnu/dts/arm64/zte/zx296718-evb.dts +++ /dev/null @@ -1,144 +0,0 @@ -/* - * Copyright 2016 ZTE Corporation. - * Copyright 2016 Linaro Ltd. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "zx296718.dtsi" - -/ { - model = "ZTE zx296718 evaluation board"; - compatible = "zte,zx296718-evb", "zte,zx296718"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x40000000>; - }; - - sound-spdif0 { - compatible = "audio-graph-card"; - dais = <&spdif0_port>; - }; - - sound-i2s0 { - compatible = "audio-graph-card"; - dais = <&i2s0_port>; - pinctrl-names = "default"; - pinctrl-0 = <&lifier_pins>; - pa-gpios = <&bgpio4 0 GPIO_ACTIVE_HIGH>; - widgets = "Line", "Line Out Jack"; - routing = "Amplifier", "LINEOUTL", - "Amplifier", "LINEOUTR", - "Line Out Jack", "Amplifier"; - }; -}; - -&aud96p22 { - port { - aud96p22_endpoint: endpoint { - remote-endpoint = <&i2s0_endpoint>; - }; - }; -}; - -&emmc { - status = "okay"; -}; - -&hdmi { - status = "okay"; - - port { - hdmi_endpoint: endpoint { - remote-endpoint = <&spdif0_endpoint>; - }; - }; -}; - -&i2c0 { - status = "okay"; -}; - -&i2s0 { - status = "okay"; - - i2s0_port: port { - i2s0_endpoint: endpoint { - remote-endpoint = <&aud96p22_endpoint>; - dai-format = "i2s"; - frame-master; - bitclock-master; - }; - }; -}; - -&pmm { - amplifier_pins: amplifier { - pins = "TSI3_DATA"; - function = "BGPIO"; - }; -}; - -&sd1 { - status = "okay"; -}; - -&spdif0 { - status = "okay"; - - spdif0_port: port { - spdif0_endpoint: endpoint { - remote-endpoint = <&hdmi_endpoint>; - }; - }; -}; - -&tvenc { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/zte/zx296718-pcbox.dts b/sys/gnu/dts/arm64/zte/zx296718-pcbox.dts deleted file mode 100644 index e02509f7082..00000000000 --- a/sys/gnu/dts/arm64/zte/zx296718-pcbox.dts +++ /dev/null @@ -1,143 +0,0 @@ -/* - * Copyright (C) 2017 Sanechips Technology Co., Ltd. - * Copyright 2017 Linaro Ltd. - * - * SPDX-License-Identifier: (GPL-2.0+ OR MIT) - */ - -/dts-v1/; -#include "zx296718.dtsi" -#include - -/ { - model = "ZTE ZX296718 PCBOX Board"; - compatible = "zte,zx296718-pcbox", "zte,zx296718"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x80000000>; - }; - - a53_vdd0v9: regulator-a53 { - compatible = "pwm-regulator"; - pwms = <&pwm 3 1250 PWM_POLARITY_INVERTED>; - regulator-name = "A53_VDD0V9"; - regulator-min-microvolt = <855000>; - regulator-max-microvolt = <1183000>; - pwm-dutycycle-unit = <100>; - pwm-dutycycle-range = <0 100>; - regulator-always-on; - regulator-boot-on; - }; - - sound-spdif0 { - compatible = "audio-graph-card"; - dais = <&spdif0_port>; - }; - - sound-i2s0 { - compatible = "audio-graph-card"; - dais = <&i2s0_port>; - }; -}; - -&aud96p22 { - port { - aud96p22_endpoint: endpoint { - remote-endpoint = <&i2s0_endpoint>; - }; - }; -}; - -&cpu0 { - cpu-supply = <&a53_vdd0v9>; -}; - -&emmc { - status = "okay"; -}; - -&hdmi { - status = "disabled"; - - port { - hdmi_endpoint: endpoint { - remote-endpoint = <&spdif0_endpoint>; - }; - }; -}; - -&i2c0 { - status = "okay"; -}; - -&i2s0 { - status = "okay"; - - i2s0_port: port { - i2s0_endpoint: endpoint { - remote-endpoint = <&aud96p22_endpoint>; - dai-format = "i2s"; - frame-master; - bitclock-master; - }; - }; -}; - -&irdec { - status = "okay"; -}; - -&pmm { - pwm3_pins: pwm3 { - pins = "KEY_ROW2"; - function = "PWM"; - }; - - vga_pins: vga { - pins = "KEY_COL1", "KEY_COL2", "VGA_HS", "VGA_VS"; - function = "VGA"; - }; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm3_pins>; - status = "okay"; -}; - -&sd0 { - status = "okay"; -}; - -&sd1 { - status = "okay"; -}; - -&spdif0 { - status = "okay"; - - spdif0_port: port { - spdif0_endpoint: endpoint { - remote-endpoint = <&hdmi_endpoint>; - }; - }; -}; - -&tvenc { - status = "disabled"; -}; - -&uart0 { - status = "okay"; -}; - -&vga { - pinctrl-names = "default"; - pinctrl-0 = <&vga_pins>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm64/zte/zx296718.dtsi b/sys/gnu/dts/arm64/zte/zx296718.dtsi deleted file mode 100644 index cc54837ff4b..00000000000 --- a/sys/gnu/dts/arm64/zte/zx296718.dtsi +++ /dev/null @@ -1,627 +0,0 @@ -/* - * Copyright 2016 ZTE Corporation. - * Copyright 2016 Linaro Ltd. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include -#include -#include -#include - -/ { - compatible = "zte,zx296718"; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&gic>; - - aliases { - gpio0 = &bgpio0; - gpio1 = &bgpio1; - gpio2 = &bgpio2; - gpio3 = &bgpio3; - gpio4 = &bgpio4; - gpio5 = &bgpio5; - gpio6 = &bgpio6; - serial0 = &uart0; - }; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu-map { - cluster0 { - core0 { - cpu = <&cpu0>; - }; - core1 { - cpu = <&cpu1>; - }; - core2 { - cpu = <&cpu2>; - }; - core3 { - cpu = <&cpu3>; - }; - }; - }; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x0>; - enable-method = "psci"; - clocks = <&topcrm A53_GATE>; - operating-points-v2 = <&cluster0_opp>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x1>; - enable-method = "psci"; - clocks = <&topcrm A53_GATE>; - operating-points-v2 = <&cluster0_opp>; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x2>; - enable-method = "psci"; - clocks = <&topcrm A53_GATE>; - operating-points-v2 = <&cluster0_opp>; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x3>; - enable-method = "psci"; - clocks = <&topcrm A53_GATE>; - operating-points-v2 = <&cluster0_opp>; - }; - }; - - cluster0_opp: opp-table0 { - compatible = "operating-points-v2"; - opp-shared; - - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <866000>; - clock-latency-ns = <500000>; - }; - - opp-648000000 { - opp-hz = /bits/ 64 <648000000>; - opp-microvolt = <866000>; - clock-latency-ns = <500000>; - }; - - opp-800000000 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <888000>; - clock-latency-ns = <500000>; - }; - - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <898000>; - clock-latency-ns = <500000>; - }; - - opp-1188000000 { - opp-hz = /bits/ 64 <1188000000>; - opp-microvolt = <1015000>; - clock-latency-ns = <500000>; - }; - }; - - clk24k: clk-24k { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000>; - clock-output-names = "rtcclk"; - }; - - osc32k: clk-osc32k { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32000>; - clock-output-names = "osc32k"; - }; - - osc12m: clk-osc12m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <12000000>; - clock-output-names = "osc12m"; - }; - - osc24m: clk-osc24m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "osc24m"; - }; - - osc25m: clk-osc25m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - clock-output-names = "osc25m"; - }; - - osc60m: clk-osc60m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <60000000>; - clock-output-names = "osc60m"; - }; - - osc99m: clk-osc99m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <99000000>; - clock-output-names = "osc99m"; - }; - - osc125m: clk-osc125m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <125000000>; - clock-output-names = "osc125m"; - }; - - osc198m: clk-osc198m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <198000000>; - clock-output-names = "osc198m"; - }; - - pll_audio: clk-pll-884m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <884000000>; - clock-output-names = "pll_audio"; - }; - - pll_ddr: clk-pll-932m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <932000000>; - clock-output-names = "pll_ddr"; - }; - - pll_hsic: clk-pll-960m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <960000000>; - clock-output-names = "pll_hsic"; - }; - - pll_mac: clk-pll-1000m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <1000000000>; - clock-output-names = "pll_mac"; - }; - - pll_mm0: clk-pll-1188m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <1188000000>; - clock-output-names = "pll_mm0"; - }; - - pll_mm1: clk-pll-1296m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <1296000000>; - clock-output-names = "pll_mm1"; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - pmu { - compatible = "arm,cortex-a53-pmu"; - interrupts = ; - }; - - gic: interrupt-controller@2a00000 { - compatible = "arm,gic-v3"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x02a00000 0x10000>, - <0x02b00000 0xc0000>; - interrupts = ; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges; - - irdec: ir-decoder@111000 { - compatible = "zte,zx296718-irdec"; - reg = <0x111000 0x1000>; - interrupts = ; - status = "disabled"; - }; - - aon_sysctrl: aon-sysctrl@116000 { - compatible = "zte,zx296718-aon-sysctrl", "syscon"; - reg = <0x116000 0x1000>; - }; - - iocfg: pin-controller@119000 { - compatible = "zte,zx296718-iocfg"; - reg = <0x119000 0x1000>; - }; - - uart0: uart@11f000 { - compatible = "arm,pl011", "arm,primecell"; - arm,primecell-periphid = <0x001feffe>; - reg = <0x11f000 0x1000>; - interrupts = ; - clocks = <&osc24m>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - sd0: mmc@1110000 { - compatible = "zte,zx296718-dw-mshc"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x01110000 0x1000>; - interrupts = ; - fifo-depth = <32>; - data-addr = <0x200>; - fifo-watermark-aligned; - bus-width = <4>; - clock-frequency = <50000000>; - clocks = <&topcrm SD0_AHB>, <&topcrm SD0_WCLK>; - clock-names = "biu", "ciu"; - max-frequency = <50000000>; - cap-sdio-irq; - cap-sd-highspeed; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-sdr104; - sd-uhs-ddr50; - status = "disabled"; - }; - - sd1: mmc@1111000 { - compatible = "zte,zx296718-dw-mshc"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x01111000 0x1000>; - interrupts = ; - fifo-depth = <32>; - data-addr = <0x200>; - fifo-watermark-aligned; - bus-width = <4>; - clock-frequency = <167000000>; - clocks = <&topcrm SD1_AHB>, <&topcrm SD1_WCLK>; - clock-names = "biu", "ciu"; - max-frequency = <167000000>; - cap-sdio-irq; - cap-sd-highspeed; - status = "disabled"; - }; - - dma: dma-controller@1460000 { - compatible = "zte,zx296702-dma"; - reg = <0x01460000 0x1000>; - interrupts = ; - clocks = <&osc24m>; - clock-names = "dmaclk"; - #dma-cells = <1>; - dma-channels = <32>; - dma-requests = <32>; - }; - - lsp0crm: clock-controller@1420000 { - compatible = "zte,zx296718-lsp0crm"; - reg = <0x01420000 0x1000>; - #clock-cells = <1>; - }; - - bgpio0: gpio@142d000 { - compatible = "zte,zx296718-gpio", "zte,zx296702-gpio"; - reg = <0x142d000 0x40>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmm 0 48 16>; - interrupts = ; - interrupt-parent = <&gic>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - bgpio1: gpio@142d040 { - compatible = "zte,zx296718-gpio", "zte,zx296702-gpio"; - reg = <0x142d040 0x40>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmm 0 80 16>; - interrupts = ; - interrupt-parent = <&gic>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - bgpio2: gpio@142d080 { - compatible = "zte,zx296718-gpio", "zte,zx296702-gpio"; - reg = <0x142d080 0x40>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmm 0 80 3 - &pmm 3 32 4 - &pmm 7 83 9>; - interrupts = ; - interrupt-parent = <&gic>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - bgpio3: gpio@142d0c0 { - compatible = "zte,zx296718-gpio", "zte,zx296702-gpio"; - reg = <0x142d0c0 0x40>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmm 0 92 16>; - interrupts = ; - interrupt-parent = <&gic>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - bgpio4: gpio@142d100 { - compatible = "zte,zx296718-gpio", "zte,zx296702-gpio"; - reg = <0x142d100 0x40>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmm 0 108 12 - &pmm 12 121 4>; - interrupts = ; - interrupt-parent = <&gic>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - bgpio5: gpio@142d140 { - compatible = "zte,zx296718-gpio", "zte,zx296702-gpio"; - reg = <0x142d140 0x40>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmm 0 125 16>; - interrupts = ; - interrupt-parent = <&gic>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - bgpio6: gpio@142d180 { - compatible = "zte,zx296718-gpio", "zte,zx296702-gpio"; - reg = <0x142d180 0x40>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmm 0 141 2>; - interrupts = ; - interrupt-parent = <&gic>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - lsp1crm: clock-controller@1430000 { - compatible = "zte,zx296718-lsp1crm"; - reg = <0x01430000 0x1000>; - #clock-cells = <1>; - }; - - pwm: pwm@1439000 { - compatible = "zte,zx296718-pwm"; - reg = <0x1439000 0x1000>; - clocks = <&lsp1crm LSP1_PWM_PCLK>, - <&lsp1crm LSP1_PWM_WCLK>; - clock-names = "pclk", "wclk"; - #pwm-cells = <3>; - status = "disabled"; - }; - - vou: vou@1440000 { - compatible = "zte,zx296718-vou"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1440000 0x10000>; - - dpc: dpc@0 { - compatible = "zte,zx296718-dpc"; - reg = <0x0000 0x1000>, <0x1000 0x1000>, - <0x5000 0x1000>, <0x6000 0x1000>, - <0xa000 0x1000>; - reg-names = "osd", "timing_ctrl", - "dtrc", "vou_ctrl", - "otfppu"; - interrupts = ; - clocks = <&topcrm VOU_ACLK>, <&topcrm VOU_PPU_WCLK>, - <&topcrm VOU_MAIN_WCLK>, <&topcrm VOU_AUX_WCLK>; - clock-names = "aclk", "ppu_wclk", - "main_wclk", "aux_wclk"; - }; - - vga: vga@8000 { - compatible = "zte,zx296718-vga"; - reg = <0x8000 0x1000>; - interrupts = ; - clocks = <&topcrm VGA_I2C_WCLK>; - clock-names = "i2c_wclk"; - zte,vga-power-control = <&sysctrl 0x170 0xe0>; - status = "disabled"; - }; - - hdmi: hdmi@c000 { - compatible = "zte,zx296718-hdmi"; - reg = <0xc000 0x4000>; - interrupts = ; - clocks = <&topcrm HDMI_OSC_CEC>, - <&topcrm HDMI_OSC_CLK>, - <&topcrm HDMI_XCLK>; - clock-names = "osc_cec", "osc_clk", "xclk"; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - tvenc: tvenc@2000 { - compatible = "zte,zx296718-tvenc"; - reg = <0x2000 0x1000>; - zte,tvenc-power-control = <&sysctrl 0x170 0x10>; - status = "disabled"; - }; - }; - - topcrm: clock-controller@1461000 { - compatible = "zte,zx296718-topcrm"; - reg = <0x01461000 0x1000>; - #clock-cells = <1>; - }; - - pmm: pin-controller@1462000 { - compatible = "zte,zx296718-pmm"; - reg = <0x1462000 0x1000>; - zte,auxiliary-controller = <&iocfg>; - }; - - sysctrl: sysctrl@1463000 { - compatible = "zte,zx296718-sysctrl", "syscon"; - reg = <0x1463000 0x1000>; - }; - - emmc: mmc@1470000{ - compatible = "zte,zx296718-dw-mshc"; - reg = <0x01470000 0x1000>; - interrupts = ; - zte,aon-syscon = <&aon_sysctrl>; - bus-width = <8>; - fifo-depth = <128>; - data-addr = <0x200>; - fifo-watermark-aligned; - clock-frequency = <167000000>; - clocks = <&topcrm EMMC_NAND_AHB>, <&topcrm EMMC_WCLK>; - clock-names = "biu", "ciu"; - max-frequency = <167000000>; - cap-mmc-highspeed; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - non-removable; - disable-wp; - status = "disabled"; - }; - - audiocrm: clock-controller@1480000 { - compatible = "zte,zx296718-audiocrm"; - reg = <0x01480000 0x1000>; - #clock-cells = <1>; - }; - - i2s0: i2s@1482000 { - compatible = "zte,zx296718-i2s", "zte,zx296702-i2s"; - reg = <0x01482000 0x1000>; - clocks = <&audiocrm AUDIO_I2S0_WCLK>, - <&audiocrm AUDIO_I2S0_PCLK>; - clock-names = "wclk", "pclk"; - assigned-clocks = <&audiocrm I2S0_WCLK_MUX>; - assigned-clock-parents = <&topcrm AUDIO_99M>; - interrupts = ; - dmas = <&dma 22>, <&dma 23>; - dma-names = "tx", "rx"; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - i2c0: i2c@1486000 { - compatible = "zte,zx296718-i2c"; - reg = <0x01486000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&audiocrm AUDIO_I2C0_WCLK>; - clock-frequency = <1600000>; - status = "disabled"; - - aud96p22: codec@22 { - compatible = "zte,zx-aud96p22"; - #sound-dai-cells = <0>; - reg = <0x22>; - }; - }; - - spdif0: spdif@1488000 { - compatible = "zte,zx296702-spdif"; - reg = <0x1488000 0x1000>; - clocks = <&audiocrm AUDIO_SPDIF0_WCLK>; - clock-names = "tx"; - interrupts = ; - #sound-dai-cells = <0>; - dmas = <&dma 30>; - dma-names = "tx"; - status = "disabled"; - }; - }; -}; diff --git a/sys/gnu/dts/include/dt-bindings/arm/ux500_pm_domains.h b/sys/gnu/dts/include/dt-bindings/arm/ux500_pm_domains.h deleted file mode 100644 index 9bd764f0c9e..00000000000 --- a/sys/gnu/dts/include/dt-bindings/arm/ux500_pm_domains.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) 2014 Linaro Ltd. - * - * Author: Ulf Hansson - */ -#ifndef _DT_BINDINGS_ARM_UX500_PM_DOMAINS_H -#define _DT_BINDINGS_ARM_UX500_PM_DOMAINS_H - -#define DOMAIN_VAPE 0 - -/* Number of PM domains. */ -#define NR_DOMAINS (DOMAIN_VAPE + 1) - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/bus/moxtet.h b/sys/gnu/dts/include/dt-bindings/bus/moxtet.h deleted file mode 100644 index dc9345440eb..00000000000 --- a/sys/gnu/dts/include/dt-bindings/bus/moxtet.h +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Constant for device tree bindings for Turris Mox module configuration bus - * - * Copyright (C) 2019 Marek Behun - */ - -#ifndef _DT_BINDINGS_BUS_MOXTET_H -#define _DT_BINDINGS_BUS_MOXTET_H - -#define MOXTET_IRQ_PCI 0 -#define MOXTET_IRQ_USB3 4 -#define MOXTET_IRQ_PERIDOT(n) (8 + (n)) -#define MOXTET_IRQ_TOPAZ 12 - -#endif /* _DT_BINDINGS_BUS_MOXTET_H */ diff --git a/sys/gnu/dts/include/dt-bindings/bus/ti-sysc.h b/sys/gnu/dts/include/dt-bindings/bus/ti-sysc.h deleted file mode 100644 index babd08a1d22..00000000000 --- a/sys/gnu/dts/include/dt-bindings/bus/ti-sysc.h +++ /dev/null @@ -1,25 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* TI sysc interconnect target module defines */ - -/* Generic sysc found on omap2 and later, also known as type1 */ -#define SYSC_OMAP2_CLOCKACTIVITY (3 << 8) -#define SYSC_OMAP2_EMUFREE (1 << 5) -#define SYSC_OMAP2_ENAWAKEUP (1 << 2) -#define SYSC_OMAP2_SOFTRESET (1 << 1) -#define SYSC_OMAP2_AUTOIDLE (1 << 0) - -/* Generic sysc found on omap4 and later, also known as type2 */ -#define SYSC_OMAP4_DMADISABLE (1 << 16) -#define SYSC_OMAP4_FREEEMU (1 << 1) /* Also known as EMUFREE */ -#define SYSC_OMAP4_SOFTRESET (1 << 0) - -/* SmartReflex sysc found on 36xx and later */ -#define SYSC_OMAP3_SR_ENAWAKEUP (1 << 26) - -#define SYSC_DRA7_MCAN_ENAWAKEUP (1 << 4) - -/* SYSCONFIG STANDBYMODE/MIDLEMODE/SIDLEMODE supported by hardware */ -#define SYSC_IDLE_FORCE 0 -#define SYSC_IDLE_NO 1 -#define SYSC_IDLE_SMART 2 -#define SYSC_IDLE_SMART_WKUP 3 diff --git a/sys/gnu/dts/include/dt-bindings/clk/at91.h b/sys/gnu/dts/include/dt-bindings/clk/at91.h deleted file mode 100644 index 0b4cb999a3f..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clk/at91.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * This header provides constants for AT91 pmc status. - * - * The constants defined in this header are being used in dts. - * - * Licensed under GPLv2 or later. - */ - -#ifndef _DT_BINDINGS_CLK_AT91_H -#define _DT_BINDINGS_CLK_AT91_H - -#define AT91_PMC_MOSCS 0 /* MOSCS Flag */ -#define AT91_PMC_LOCKA 1 /* PLLA Lock */ -#define AT91_PMC_LOCKB 2 /* PLLB Lock */ -#define AT91_PMC_MCKRDY 3 /* Master Clock */ -#define AT91_PMC_LOCKU 6 /* UPLL Lock */ -#define AT91_PMC_PCKRDY(id) (8 + (id)) /* Programmable Clock */ -#define AT91_PMC_MOSCSELS 16 /* Main Oscillator Selection */ -#define AT91_PMC_MOSCRCS 17 /* Main On-Chip RC */ -#define AT91_PMC_CFDEV 18 /* Clock Failure Detector Event */ - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clk/exynos-audss-clk.h b/sys/gnu/dts/include/dt-bindings/clk/exynos-audss-clk.h deleted file mode 100644 index 0ae6f5a75d2..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clk/exynos-audss-clk.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * This header provides constants for Samsung audio subsystem - * clock controller. - * - * The constants defined in this header are being used in dts - * and exynos audss driver. - */ - -#ifndef _DT_BINDINGS_CLK_EXYNOS_AUDSS_H -#define _DT_BINDINGS_CLK_EXYNOS_AUDSS_H - -#define EXYNOS_MOUT_AUDSS 0 -#define EXYNOS_MOUT_I2S 1 -#define EXYNOS_DOUT_SRP 2 -#define EXYNOS_DOUT_AUD_BUS 3 -#define EXYNOS_DOUT_I2S 4 -#define EXYNOS_SRP_CLK 5 -#define EXYNOS_I2S_BUS 6 -#define EXYNOS_SCLK_I2S 7 -#define EXYNOS_PCM_BUS 8 -#define EXYNOS_SCLK_PCM 9 -#define EXYNOS_ADMA 10 - -#define EXYNOS_AUDSS_MAX_CLKS 11 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clk/lochnagar.h b/sys/gnu/dts/include/dt-bindings/clk/lochnagar.h deleted file mode 100644 index 8fa20551ff1..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clk/lochnagar.h +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Device Tree defines for Lochnagar clocking - * - * Copyright (c) 2017-2018 Cirrus Logic, Inc. and - * Cirrus Logic International Semiconductor Ltd. - * - * Author: Charles Keepax - */ - -#ifndef DT_BINDINGS_CLK_LOCHNAGAR_H -#define DT_BINDINGS_CLK_LOCHNAGAR_H - -#define LOCHNAGAR_CDC_MCLK1 0 -#define LOCHNAGAR_CDC_MCLK2 1 -#define LOCHNAGAR_DSP_CLKIN 2 -#define LOCHNAGAR_GF_CLKOUT1 3 -#define LOCHNAGAR_GF_CLKOUT2 4 -#define LOCHNAGAR_PSIA1_MCLK 5 -#define LOCHNAGAR_PSIA2_MCLK 6 -#define LOCHNAGAR_SPDIF_MCLK 7 -#define LOCHNAGAR_ADAT_MCLK 8 -#define LOCHNAGAR_SOUNDCARD_MCLK 9 -#define LOCHNAGAR_SPDIF_CLKOUT 10 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clk/ti-dra7-atl.h b/sys/gnu/dts/include/dt-bindings/clk/ti-dra7-atl.h deleted file mode 100644 index 42dd4164f6f..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clk/ti-dra7-atl.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * This header provides constants for DRA7 ATL (Audio Tracking Logic) - * - * The constants defined in this header are used in dts files - * - * Copyright (C) 2013 Texas Instruments, Inc. - * - * Peter Ujfalusi - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _DT_BINDINGS_CLK_DRA7_ATL_H -#define _DT_BINDINGS_CLK_DRA7_ATL_H - -#define DRA7_ATL_WS_MCASP1_FSR 0 -#define DRA7_ATL_WS_MCASP1_FSX 1 -#define DRA7_ATL_WS_MCASP2_FSR 2 -#define DRA7_ATL_WS_MCASP2_FSX 3 -#define DRA7_ATL_WS_MCASP3_FSX 4 -#define DRA7_ATL_WS_MCASP4_FSX 5 -#define DRA7_ATL_WS_MCASP5_FSX 6 -#define DRA7_ATL_WS_MCASP6_FSX 7 -#define DRA7_ATL_WS_MCASP7_FSX 8 -#define DRA7_ATL_WS_MCASP8_FSX 9 -#define DRA7_ATL_WS_MCASP8_AHCLKX 10 -#define DRA7_ATL_WS_XREF_CLK3 11 -#define DRA7_ATL_WS_XREF_CLK0 12 -#define DRA7_ATL_WS_XREF_CLK1 13 -#define DRA7_ATL_WS_XREF_CLK2 14 -#define DRA7_ATL_WS_OSC1_X1 15 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/actions,s500-cmu.h b/sys/gnu/dts/include/dt-bindings/clock/actions,s500-cmu.h deleted file mode 100644 index 030981cd2d5..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/actions,s500-cmu.h +++ /dev/null @@ -1,78 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Device Tree binding constants for Actions Semi S500 Clock Management Unit - * - * Copyright (c) 2014 Actions Semi Inc. - * Copyright (c) 2018 LSI-TEC - Caninos Loucos - */ - -#ifndef __DT_BINDINGS_CLOCK_S500_CMU_H -#define __DT_BINDINGS_CLOCK_S500_CMU_H - -#define CLK_NONE 0 - -/* fixed rate clocks */ -#define CLK_LOSC 1 -#define CLK_HOSC 2 - -/* pll clocks */ -#define CLK_CORE_PLL 3 -#define CLK_DEV_PLL 4 -#define CLK_DDR_PLL 5 -#define CLK_NAND_PLL 6 -#define CLK_DISPLAY_PLL 7 -#define CLK_ETHERNET_PLL 8 -#define CLK_AUDIO_PLL 9 - -/* system clock */ -#define CLK_DEV 10 -#define CLK_H 11 -#define CLK_AHBPREDIV 12 -#define CLK_AHB 13 -#define CLK_DE 14 -#define CLK_BISP 15 -#define CLK_VCE 16 -#define CLK_VDE 17 - -/* peripheral device clock */ -#define CLK_TIMER 18 -#define CLK_I2C0 19 -#define CLK_I2C1 20 -#define CLK_I2C2 21 -#define CLK_I2C3 22 -#define CLK_PWM0 23 -#define CLK_PWM1 24 -#define CLK_PWM2 25 -#define CLK_PWM3 26 -#define CLK_PWM4 27 -#define CLK_PWM5 28 -#define CLK_SD0 29 -#define CLK_SD1 30 -#define CLK_SD2 31 -#define CLK_SENSOR0 32 -#define CLK_SENSOR1 33 -#define CLK_SPI0 34 -#define CLK_SPI1 35 -#define CLK_SPI2 36 -#define CLK_SPI3 37 -#define CLK_UART0 38 -#define CLK_UART1 39 -#define CLK_UART2 40 -#define CLK_UART3 41 -#define CLK_UART4 42 -#define CLK_UART5 43 -#define CLK_UART6 44 -#define CLK_DE1 45 -#define CLK_DE2 46 -#define CLK_I2SRX 47 -#define CLK_I2STX 48 -#define CLK_HDMI_AUDIO 49 -#define CLK_HDMI 50 -#define CLK_SPDIF 51 -#define CLK_NAND 52 -#define CLK_ECC 53 -#define CLK_RMII_REF 54 - -#define CLK_NR_CLKS (CLK_RMII_REF + 1) - -#endif /* __DT_BINDINGS_CLOCK_S500_CMU_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/actions,s700-cmu.h b/sys/gnu/dts/include/dt-bindings/clock/actions,s700-cmu.h deleted file mode 100644 index 3e194299672..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/actions,s700-cmu.h +++ /dev/null @@ -1,118 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 - * - * Device Tree binding constants for Actions Semi S700 Clock Management Unit - * - * Copyright (c) 2014 Actions Semi Inc. - * Author: David Liu - * - * Author: Pathiban Nallathambi - * Author: Saravanan Sekar - */ - -#ifndef __DT_BINDINGS_CLOCK_S700_H -#define __DT_BINDINGS_CLOCK_S700_H - -#define CLK_NONE 0 - -/* pll clocks */ -#define CLK_CORE_PLL 1 -#define CLK_DEV_PLL 2 -#define CLK_DDR_PLL 3 -#define CLK_NAND_PLL 4 -#define CLK_DISPLAY_PLL 5 -#define CLK_TVOUT_PLL 6 -#define CLK_CVBS_PLL 7 -#define CLK_AUDIO_PLL 8 -#define CLK_ETHERNET_PLL 9 - -/* system clock */ -#define CLK_CPU 10 -#define CLK_DEV 11 -#define CLK_AHB 12 -#define CLK_APB 13 -#define CLK_DMAC 14 -#define CLK_NOC0_CLK_MUX 15 -#define CLK_NOC1_CLK_MUX 16 -#define CLK_HP_CLK_MUX 17 -#define CLK_HP_CLK_DIV 18 -#define CLK_NOC1_CLK_DIV 19 -#define CLK_NOC0 20 -#define CLK_NOC1 21 -#define CLK_SENOR_SRC 22 - -/* peripheral device clock */ -#define CLK_GPIO 23 -#define CLK_TIMER 24 -#define CLK_DSI 25 -#define CLK_CSI 26 -#define CLK_SI 27 -#define CLK_DE 28 -#define CLK_HDE 29 -#define CLK_VDE 30 -#define CLK_VCE 31 -#define CLK_NAND 32 -#define CLK_SD0 33 -#define CLK_SD1 34 -#define CLK_SD2 35 - -#define CLK_UART0 36 -#define CLK_UART1 37 -#define CLK_UART2 38 -#define CLK_UART3 39 -#define CLK_UART4 40 -#define CLK_UART5 41 -#define CLK_UART6 42 - -#define CLK_PWM0 43 -#define CLK_PWM1 44 -#define CLK_PWM2 45 -#define CLK_PWM3 46 -#define CLK_PWM4 47 -#define CLK_PWM5 48 -#define CLK_GPU3D 49 - -#define CLK_I2C0 50 -#define CLK_I2C1 51 -#define CLK_I2C2 52 -#define CLK_I2C3 53 - -#define CLK_SPI0 54 -#define CLK_SPI1 55 -#define CLK_SPI2 56 -#define CLK_SPI3 57 - -#define CLK_USB3_480MPLL0 58 -#define CLK_USB3_480MPHY0 59 -#define CLK_USB3_5GPHY 60 -#define CLK_USB3_CCE 61 -#define CLK_USB3_MAC 62 - -#define CLK_LCD 63 -#define CLK_HDMI_AUDIO 64 -#define CLK_I2SRX 65 -#define CLK_I2STX 66 - -#define CLK_SENSOR0 67 -#define CLK_SENSOR1 68 - -#define CLK_HDMI_DEV 69 - -#define CLK_ETHERNET 70 -#define CLK_RMII_REF 71 - -#define CLK_USB2H0_PLLEN 72 -#define CLK_USB2H0_PHY 73 -#define CLK_USB2H0_CCE 74 -#define CLK_USB2H1_PLLEN 75 -#define CLK_USB2H1_PHY 76 -#define CLK_USB2H1_CCE 77 - -#define CLK_TVOUT 78 - -#define CLK_THERMAL_SENSOR 79 - -#define CLK_IRC_SWITCH 80 -#define CLK_PCM1 81 -#define CLK_NR_CLKS (CLK_PCM1 + 1) - -#endif /* __DT_BINDINGS_CLOCK_S700_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/actions,s900-cmu.h b/sys/gnu/dts/include/dt-bindings/clock/actions,s900-cmu.h deleted file mode 100644 index 7c1251565f4..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/actions,s900-cmu.h +++ /dev/null @@ -1,129 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// -// Device Tree binding constants for Actions Semi S900 Clock Management Unit -// -// Copyright (c) 2014 Actions Semi Inc. -// Copyright (c) 2018 Linaro Ltd. - -#ifndef __DT_BINDINGS_CLOCK_S900_CMU_H -#define __DT_BINDINGS_CLOCK_S900_CMU_H - -#define CLK_NONE 0 - -/* fixed rate clocks */ -#define CLK_LOSC 1 -#define CLK_HOSC 2 - -/* pll clocks */ -#define CLK_CORE_PLL 3 -#define CLK_DEV_PLL 4 -#define CLK_DDR_PLL 5 -#define CLK_NAND_PLL 6 -#define CLK_DISPLAY_PLL 7 -#define CLK_DSI_PLL 8 -#define CLK_ASSIST_PLL 9 -#define CLK_AUDIO_PLL 10 - -/* system clock */ -#define CLK_CPU 15 -#define CLK_DEV 16 -#define CLK_NOC 17 -#define CLK_NOC_MUX 18 -#define CLK_NOC_DIV 19 -#define CLK_AHB 20 -#define CLK_APB 21 -#define CLK_DMAC 22 - -/* peripheral device clock */ -#define CLK_GPIO 23 - -#define CLK_BISP 24 -#define CLK_CSI0 25 -#define CLK_CSI1 26 - -#define CLK_DE0 27 -#define CLK_DE1 28 -#define CLK_DE2 29 -#define CLK_DE3 30 -#define CLK_DSI 32 - -#define CLK_GPU 33 -#define CLK_GPU_CORE 34 -#define CLK_GPU_MEM 35 -#define CLK_GPU_SYS 36 - -#define CLK_HDE 37 -#define CLK_I2C0 38 -#define CLK_I2C1 39 -#define CLK_I2C2 40 -#define CLK_I2C3 41 -#define CLK_I2C4 42 -#define CLK_I2C5 43 -#define CLK_I2SRX 44 -#define CLK_I2STX 45 -#define CLK_IMX 46 -#define CLK_LCD 47 -#define CLK_NAND0 48 -#define CLK_NAND1 49 -#define CLK_PWM0 50 -#define CLK_PWM1 51 -#define CLK_PWM2 52 -#define CLK_PWM3 53 -#define CLK_PWM4 54 -#define CLK_PWM5 55 -#define CLK_SD0 56 -#define CLK_SD1 57 -#define CLK_SD2 58 -#define CLK_SD3 59 -#define CLK_SENSOR 60 -#define CLK_SPEED_SENSOR 61 -#define CLK_SPI0 62 -#define CLK_SPI1 63 -#define CLK_SPI2 64 -#define CLK_SPI3 65 -#define CLK_THERMAL_SENSOR 66 -#define CLK_UART0 67 -#define CLK_UART1 68 -#define CLK_UART2 69 -#define CLK_UART3 70 -#define CLK_UART4 71 -#define CLK_UART5 72 -#define CLK_UART6 73 -#define CLK_VCE 74 -#define CLK_VDE 75 - -#define CLK_USB3_480MPLL0 76 -#define CLK_USB3_480MPHY0 77 -#define CLK_USB3_5GPHY 78 -#define CLK_USB3_CCE 79 -#define CLK_USB3_MAC 80 - -#define CLK_TIMER 83 - -#define CLK_HDMI_AUDIO 84 - -#define CLK_24M 85 - -#define CLK_EDP 86 - -#define CLK_24M_EDP 87 -#define CLK_EDP_PLL 88 -#define CLK_EDP_LINK 89 - -#define CLK_USB2H0_PLLEN 90 -#define CLK_USB2H0_PHY 91 -#define CLK_USB2H0_CCE 92 -#define CLK_USB2H1_PLLEN 93 -#define CLK_USB2H1_PHY 94 -#define CLK_USB2H1_CCE 95 - -#define CLK_DDR0 96 -#define CLK_DDR1 97 -#define CLK_DMM 98 - -#define CLK_ETH_MAC 99 -#define CLK_RMII_REF 100 - -#define CLK_NR_CLKS (CLK_RMII_REF + 1) - -#endif /* __DT_BINDINGS_CLOCK_S900_CMU_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/alphascale,asm9260.h b/sys/gnu/dts/include/dt-bindings/clock/alphascale,asm9260.h deleted file mode 100644 index d3871c63308..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/alphascale,asm9260.h +++ /dev/null @@ -1,89 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2014 Oleksij Rempel - */ - -#ifndef _DT_BINDINGS_CLK_ASM9260_H -#define _DT_BINDINGS_CLK_ASM9260_H - -/* ahb gate */ -#define CLKID_AHB_ROM 0 -#define CLKID_AHB_RAM 1 -#define CLKID_AHB_GPIO 2 -#define CLKID_AHB_MAC 3 -#define CLKID_AHB_EMI 4 -#define CLKID_AHB_USB0 5 -#define CLKID_AHB_USB1 6 -#define CLKID_AHB_DMA0 7 -#define CLKID_AHB_DMA1 8 -#define CLKID_AHB_UART0 9 -#define CLKID_AHB_UART1 10 -#define CLKID_AHB_UART2 11 -#define CLKID_AHB_UART3 12 -#define CLKID_AHB_UART4 13 -#define CLKID_AHB_UART5 14 -#define CLKID_AHB_UART6 15 -#define CLKID_AHB_UART7 16 -#define CLKID_AHB_UART8 17 -#define CLKID_AHB_UART9 18 -#define CLKID_AHB_I2S0 19 -#define CLKID_AHB_I2C0 20 -#define CLKID_AHB_I2C1 21 -#define CLKID_AHB_SSP0 22 -#define CLKID_AHB_IOCONFIG 23 -#define CLKID_AHB_WDT 24 -#define CLKID_AHB_CAN0 25 -#define CLKID_AHB_CAN1 26 -#define CLKID_AHB_MPWM 27 -#define CLKID_AHB_SPI0 28 -#define CLKID_AHB_SPI1 29 -#define CLKID_AHB_QEI 30 -#define CLKID_AHB_QUADSPI0 31 -#define CLKID_AHB_CAMIF 32 -#define CLKID_AHB_LCDIF 33 -#define CLKID_AHB_TIMER0 34 -#define CLKID_AHB_TIMER1 35 -#define CLKID_AHB_TIMER2 36 -#define CLKID_AHB_TIMER3 37 -#define CLKID_AHB_IRQ 38 -#define CLKID_AHB_RTC 39 -#define CLKID_AHB_NAND 40 -#define CLKID_AHB_ADC0 41 -#define CLKID_AHB_LED 42 -#define CLKID_AHB_DAC0 43 -#define CLKID_AHB_LCD 44 -#define CLKID_AHB_I2S1 45 -#define CLKID_AHB_MAC1 46 - -/* devider */ -#define CLKID_SYS_CPU 47 -#define CLKID_SYS_AHB 48 -#define CLKID_SYS_I2S0M 49 -#define CLKID_SYS_I2S0S 50 -#define CLKID_SYS_I2S1M 51 -#define CLKID_SYS_I2S1S 52 -#define CLKID_SYS_UART0 53 -#define CLKID_SYS_UART1 54 -#define CLKID_SYS_UART2 55 -#define CLKID_SYS_UART3 56 -#define CLKID_SYS_UART4 56 -#define CLKID_SYS_UART5 57 -#define CLKID_SYS_UART6 58 -#define CLKID_SYS_UART7 59 -#define CLKID_SYS_UART8 60 -#define CLKID_SYS_UART9 61 -#define CLKID_SYS_SPI0 62 -#define CLKID_SYS_SPI1 63 -#define CLKID_SYS_QUADSPI 64 -#define CLKID_SYS_SSP0 65 -#define CLKID_SYS_NAND 66 -#define CLKID_SYS_TRACE 67 -#define CLKID_SYS_CAMM 68 -#define CLKID_SYS_WDT 69 -#define CLKID_SYS_CLKOUT 70 -#define CLKID_SYS_MAC 71 -#define CLKID_SYS_LCD 72 -#define CLKID_SYS_ADCANA 73 - -#define MAX_CLKS 74 -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/am3.h b/sys/gnu/dts/include/dt-bindings/clock/am3.h deleted file mode 100644 index 89495154127..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/am3.h +++ /dev/null @@ -1,219 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2017 Texas Instruments, Inc. - */ -#ifndef __DT_BINDINGS_CLK_AM3_H -#define __DT_BINDINGS_CLK_AM3_H - -#define AM3_CLKCTRL_OFFSET 0x0 -#define AM3_CLKCTRL_INDEX(offset) ((offset) - AM3_CLKCTRL_OFFSET) - -/* XXX: Compatibility part begin, remove this once compatibility support is no longer needed */ - -/* l4_per clocks */ -#define AM3_L4_PER_CLKCTRL_OFFSET 0x14 -#define AM3_L4_PER_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_PER_CLKCTRL_OFFSET) -#define AM3_CPGMAC0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x14) -#define AM3_LCDC_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x18) -#define AM3_USB_OTG_HS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x1c) -#define AM3_TPTC0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x24) -#define AM3_EMIF_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x28) -#define AM3_OCMCRAM_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x2c) -#define AM3_GPMC_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x30) -#define AM3_MCASP0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x34) -#define AM3_UART6_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x38) -#define AM3_MMC1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x3c) -#define AM3_ELM_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x40) -#define AM3_I2C3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x44) -#define AM3_I2C2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x48) -#define AM3_SPI0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x4c) -#define AM3_SPI1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x50) -#define AM3_L4_LS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x60) -#define AM3_MCASP1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x68) -#define AM3_UART2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x6c) -#define AM3_UART3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x70) -#define AM3_UART4_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x74) -#define AM3_UART5_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x78) -#define AM3_TIMER7_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x7c) -#define AM3_TIMER2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x80) -#define AM3_TIMER3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x84) -#define AM3_TIMER4_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x88) -#define AM3_RNG_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x90) -#define AM3_AES_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x94) -#define AM3_SHAM_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xa0) -#define AM3_GPIO2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xac) -#define AM3_GPIO3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xb0) -#define AM3_GPIO4_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xb4) -#define AM3_TPCC_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xbc) -#define AM3_D_CAN0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xc0) -#define AM3_D_CAN1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xc4) -#define AM3_EPWMSS1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xcc) -#define AM3_EPWMSS0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xd4) -#define AM3_EPWMSS2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xd8) -#define AM3_L3_INSTR_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xdc) -#define AM3_L3_MAIN_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xe0) -#define AM3_PRUSS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xe8) -#define AM3_TIMER5_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xec) -#define AM3_TIMER6_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xf0) -#define AM3_MMC2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xf4) -#define AM3_MMC3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xf8) -#define AM3_TPTC1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xfc) -#define AM3_TPTC2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x100) -#define AM3_SPINLOCK_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x10c) -#define AM3_MAILBOX_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x110) -#define AM3_L4_HS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x120) -#define AM3_OCPWP_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x130) -#define AM3_CLKDIV32K_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x14c) - -/* l4_wkup clocks */ -#define AM3_L4_WKUP_CLKCTRL_OFFSET 0x4 -#define AM3_L4_WKUP_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_WKUP_CLKCTRL_OFFSET) -#define AM3_CONTROL_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0x4) -#define AM3_GPIO1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0x8) -#define AM3_L4_WKUP_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc) -#define AM3_DEBUGSS_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0x14) -#define AM3_WKUP_M3_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xb0) -#define AM3_UART1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xb4) -#define AM3_I2C1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xb8) -#define AM3_ADC_TSC_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xbc) -#define AM3_SMARTREFLEX0_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc0) -#define AM3_TIMER1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc4) -#define AM3_SMARTREFLEX1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc8) -#define AM3_WD_TIMER2_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xd4) - -/* mpu clocks */ -#define AM3_MPU_CLKCTRL_OFFSET 0x4 -#define AM3_MPU_CLKCTRL_INDEX(offset) ((offset) - AM3_MPU_CLKCTRL_OFFSET) -#define AM3_MPU_CLKCTRL AM3_MPU_CLKCTRL_INDEX(0x4) - -/* l4_rtc clocks */ -#define AM3_RTC_CLKCTRL AM3_CLKCTRL_INDEX(0x0) - -/* gfx_l3 clocks */ -#define AM3_GFX_L3_CLKCTRL_OFFSET 0x4 -#define AM3_GFX_L3_CLKCTRL_INDEX(offset) ((offset) - AM3_GFX_L3_CLKCTRL_OFFSET) -#define AM3_GFX_CLKCTRL AM3_GFX_L3_CLKCTRL_INDEX(0x4) - -/* l4_cefuse clocks */ -#define AM3_L4_CEFUSE_CLKCTRL_OFFSET 0x20 -#define AM3_L4_CEFUSE_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_CEFUSE_CLKCTRL_OFFSET) -#define AM3_CEFUSE_CLKCTRL AM3_L4_CEFUSE_CLKCTRL_INDEX(0x20) - -/* XXX: Compatibility part end */ - -/* l4ls clocks */ -#define AM3_L4LS_CLKCTRL_OFFSET 0x38 -#define AM3_L4LS_CLKCTRL_INDEX(offset) ((offset) - AM3_L4LS_CLKCTRL_OFFSET) -#define AM3_L4LS_UART6_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x38) -#define AM3_L4LS_MMC1_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x3c) -#define AM3_L4LS_ELM_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x40) -#define AM3_L4LS_I2C3_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x44) -#define AM3_L4LS_I2C2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x48) -#define AM3_L4LS_SPI0_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x4c) -#define AM3_L4LS_SPI1_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x50) -#define AM3_L4LS_L4_LS_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x60) -#define AM3_L4LS_UART2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x6c) -#define AM3_L4LS_UART3_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x70) -#define AM3_L4LS_UART4_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x74) -#define AM3_L4LS_UART5_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x78) -#define AM3_L4LS_TIMER7_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x7c) -#define AM3_L4LS_TIMER2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x80) -#define AM3_L4LS_TIMER3_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x84) -#define AM3_L4LS_TIMER4_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x88) -#define AM3_L4LS_RNG_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x90) -#define AM3_L4LS_GPIO2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xac) -#define AM3_L4LS_GPIO3_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xb0) -#define AM3_L4LS_GPIO4_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xb4) -#define AM3_L4LS_D_CAN0_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xc0) -#define AM3_L4LS_D_CAN1_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xc4) -#define AM3_L4LS_EPWMSS1_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xcc) -#define AM3_L4LS_EPWMSS0_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xd4) -#define AM3_L4LS_EPWMSS2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xd8) -#define AM3_L4LS_TIMER5_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xec) -#define AM3_L4LS_TIMER6_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xf0) -#define AM3_L4LS_MMC2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xf4) -#define AM3_L4LS_SPINLOCK_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x10c) -#define AM3_L4LS_MAILBOX_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x110) -#define AM3_L4LS_OCPWP_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x130) - -/* l3s clocks */ -#define AM3_L3S_CLKCTRL_OFFSET 0x1c -#define AM3_L3S_CLKCTRL_INDEX(offset) ((offset) - AM3_L3S_CLKCTRL_OFFSET) -#define AM3_L3S_USB_OTG_HS_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0x1c) -#define AM3_L3S_GPMC_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0x30) -#define AM3_L3S_MCASP0_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0x34) -#define AM3_L3S_MCASP1_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0x68) -#define AM3_L3S_MMC3_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0xf8) - -/* l3 clocks */ -#define AM3_L3_CLKCTRL_OFFSET 0x24 -#define AM3_L3_CLKCTRL_INDEX(offset) ((offset) - AM3_L3_CLKCTRL_OFFSET) -#define AM3_L3_TPTC0_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x24) -#define AM3_L3_EMIF_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x28) -#define AM3_L3_OCMCRAM_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x2c) -#define AM3_L3_AES_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x94) -#define AM3_L3_SHAM_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xa0) -#define AM3_L3_TPCC_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xbc) -#define AM3_L3_L3_INSTR_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xdc) -#define AM3_L3_L3_MAIN_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xe0) -#define AM3_L3_TPTC1_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xfc) -#define AM3_L3_TPTC2_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x100) - -/* l4hs clocks */ -#define AM3_L4HS_CLKCTRL_OFFSET 0x120 -#define AM3_L4HS_CLKCTRL_INDEX(offset) ((offset) - AM3_L4HS_CLKCTRL_OFFSET) -#define AM3_L4HS_L4_HS_CLKCTRL AM3_L4HS_CLKCTRL_INDEX(0x120) - -/* pruss_ocp clocks */ -#define AM3_PRUSS_OCP_CLKCTRL_OFFSET 0xe8 -#define AM3_PRUSS_OCP_CLKCTRL_INDEX(offset) ((offset) - AM3_PRUSS_OCP_CLKCTRL_OFFSET) -#define AM3_PRUSS_OCP_PRUSS_CLKCTRL AM3_PRUSS_OCP_CLKCTRL_INDEX(0xe8) - -/* cpsw_125mhz clocks */ -#define AM3_CPSW_125MHZ_CPGMAC0_CLKCTRL AM3_CLKCTRL_INDEX(0x14) - -/* lcdc clocks */ -#define AM3_LCDC_CLKCTRL_OFFSET 0x18 -#define AM3_LCDC_CLKCTRL_INDEX(offset) ((offset) - AM3_LCDC_CLKCTRL_OFFSET) -#define AM3_LCDC_LCDC_CLKCTRL AM3_LCDC_CLKCTRL_INDEX(0x18) - -/* clk_24mhz clocks */ -#define AM3_CLK_24MHZ_CLKCTRL_OFFSET 0x14c -#define AM3_CLK_24MHZ_CLKCTRL_INDEX(offset) ((offset) - AM3_CLK_24MHZ_CLKCTRL_OFFSET) -#define AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL AM3_CLK_24MHZ_CLKCTRL_INDEX(0x14c) - -/* l4_wkup clocks */ -#define AM3_L4_WKUP_CONTROL_CLKCTRL AM3_CLKCTRL_INDEX(0x4) -#define AM3_L4_WKUP_GPIO1_CLKCTRL AM3_CLKCTRL_INDEX(0x8) -#define AM3_L4_WKUP_L4_WKUP_CLKCTRL AM3_CLKCTRL_INDEX(0xc) -#define AM3_L4_WKUP_UART1_CLKCTRL AM3_CLKCTRL_INDEX(0xb4) -#define AM3_L4_WKUP_I2C1_CLKCTRL AM3_CLKCTRL_INDEX(0xb8) -#define AM3_L4_WKUP_ADC_TSC_CLKCTRL AM3_CLKCTRL_INDEX(0xbc) -#define AM3_L4_WKUP_SMARTREFLEX0_CLKCTRL AM3_CLKCTRL_INDEX(0xc0) -#define AM3_L4_WKUP_TIMER1_CLKCTRL AM3_CLKCTRL_INDEX(0xc4) -#define AM3_L4_WKUP_SMARTREFLEX1_CLKCTRL AM3_CLKCTRL_INDEX(0xc8) -#define AM3_L4_WKUP_WD_TIMER2_CLKCTRL AM3_CLKCTRL_INDEX(0xd4) - -/* l3_aon clocks */ -#define AM3_L3_AON_CLKCTRL_OFFSET 0x14 -#define AM3_L3_AON_CLKCTRL_INDEX(offset) ((offset) - AM3_L3_AON_CLKCTRL_OFFSET) -#define AM3_L3_AON_DEBUGSS_CLKCTRL AM3_L3_AON_CLKCTRL_INDEX(0x14) - -/* l4_wkup_aon clocks */ -#define AM3_L4_WKUP_AON_CLKCTRL_OFFSET 0xb0 -#define AM3_L4_WKUP_AON_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_WKUP_AON_CLKCTRL_OFFSET) -#define AM3_L4_WKUP_AON_WKUP_M3_CLKCTRL AM3_L4_WKUP_AON_CLKCTRL_INDEX(0xb0) - -/* mpu clocks */ -#define AM3_MPU_MPU_CLKCTRL AM3_CLKCTRL_INDEX(0x4) - -/* l4_rtc clocks */ -#define AM3_L4_RTC_RTC_CLKCTRL AM3_CLKCTRL_INDEX(0x0) - -/* gfx_l3 clocks */ -#define AM3_GFX_L3_GFX_CLKCTRL AM3_CLKCTRL_INDEX(0x4) - -/* l4_cefuse clocks */ -#define AM3_L4_CEFUSE_CEFUSE_CLKCTRL AM3_CLKCTRL_INDEX(0x20) - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/am4.h b/sys/gnu/dts/include/dt-bindings/clock/am4.h deleted file mode 100644 index d961e7cb368..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/am4.h +++ /dev/null @@ -1,237 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2017 Texas Instruments, Inc. - */ -#ifndef __DT_BINDINGS_CLK_AM4_H -#define __DT_BINDINGS_CLK_AM4_H - -#define AM4_CLKCTRL_OFFSET 0x20 -#define AM4_CLKCTRL_INDEX(offset) ((offset) - AM4_CLKCTRL_OFFSET) - -/* XXX: Compatibility part begin, remove this once compatibility support is no longer needed */ - -/* l4_wkup clocks */ -#define AM4_ADC_TSC_CLKCTRL AM4_CLKCTRL_INDEX(0x120) -#define AM4_L4_WKUP_CLKCTRL AM4_CLKCTRL_INDEX(0x220) -#define AM4_WKUP_M3_CLKCTRL AM4_CLKCTRL_INDEX(0x228) -#define AM4_COUNTER_32K_CLKCTRL AM4_CLKCTRL_INDEX(0x230) -#define AM4_TIMER1_CLKCTRL AM4_CLKCTRL_INDEX(0x328) -#define AM4_WD_TIMER2_CLKCTRL AM4_CLKCTRL_INDEX(0x338) -#define AM4_I2C1_CLKCTRL AM4_CLKCTRL_INDEX(0x340) -#define AM4_UART1_CLKCTRL AM4_CLKCTRL_INDEX(0x348) -#define AM4_SMARTREFLEX0_CLKCTRL AM4_CLKCTRL_INDEX(0x350) -#define AM4_SMARTREFLEX1_CLKCTRL AM4_CLKCTRL_INDEX(0x358) -#define AM4_CONTROL_CLKCTRL AM4_CLKCTRL_INDEX(0x360) -#define AM4_GPIO1_CLKCTRL AM4_CLKCTRL_INDEX(0x368) - -/* mpu clocks */ -#define AM4_MPU_CLKCTRL AM4_CLKCTRL_INDEX(0x20) - -/* gfx_l3 clocks */ -#define AM4_GFX_CLKCTRL AM4_CLKCTRL_INDEX(0x20) - -/* l4_rtc clocks */ -#define AM4_RTC_CLKCTRL AM4_CLKCTRL_INDEX(0x20) - -/* l4_per clocks */ -#define AM4_L3_MAIN_CLKCTRL AM4_CLKCTRL_INDEX(0x20) -#define AM4_AES_CLKCTRL AM4_CLKCTRL_INDEX(0x28) -#define AM4_DES_CLKCTRL AM4_CLKCTRL_INDEX(0x30) -#define AM4_L3_INSTR_CLKCTRL AM4_CLKCTRL_INDEX(0x40) -#define AM4_OCMCRAM_CLKCTRL AM4_CLKCTRL_INDEX(0x50) -#define AM4_SHAM_CLKCTRL AM4_CLKCTRL_INDEX(0x58) -#define AM4_VPFE0_CLKCTRL AM4_CLKCTRL_INDEX(0x68) -#define AM4_VPFE1_CLKCTRL AM4_CLKCTRL_INDEX(0x70) -#define AM4_TPCC_CLKCTRL AM4_CLKCTRL_INDEX(0x78) -#define AM4_TPTC0_CLKCTRL AM4_CLKCTRL_INDEX(0x80) -#define AM4_TPTC1_CLKCTRL AM4_CLKCTRL_INDEX(0x88) -#define AM4_TPTC2_CLKCTRL AM4_CLKCTRL_INDEX(0x90) -#define AM4_L4_HS_CLKCTRL AM4_CLKCTRL_INDEX(0xa0) -#define AM4_GPMC_CLKCTRL AM4_CLKCTRL_INDEX(0x220) -#define AM4_MCASP0_CLKCTRL AM4_CLKCTRL_INDEX(0x238) -#define AM4_MCASP1_CLKCTRL AM4_CLKCTRL_INDEX(0x240) -#define AM4_MMC3_CLKCTRL AM4_CLKCTRL_INDEX(0x248) -#define AM4_QSPI_CLKCTRL AM4_CLKCTRL_INDEX(0x258) -#define AM4_USB_OTG_SS0_CLKCTRL AM4_CLKCTRL_INDEX(0x260) -#define AM4_USB_OTG_SS1_CLKCTRL AM4_CLKCTRL_INDEX(0x268) -#define AM4_PRUSS_CLKCTRL AM4_CLKCTRL_INDEX(0x320) -#define AM4_L4_LS_CLKCTRL AM4_CLKCTRL_INDEX(0x420) -#define AM4_D_CAN0_CLKCTRL AM4_CLKCTRL_INDEX(0x428) -#define AM4_D_CAN1_CLKCTRL AM4_CLKCTRL_INDEX(0x430) -#define AM4_EPWMSS0_CLKCTRL AM4_CLKCTRL_INDEX(0x438) -#define AM4_EPWMSS1_CLKCTRL AM4_CLKCTRL_INDEX(0x440) -#define AM4_EPWMSS2_CLKCTRL AM4_CLKCTRL_INDEX(0x448) -#define AM4_EPWMSS3_CLKCTRL AM4_CLKCTRL_INDEX(0x450) -#define AM4_EPWMSS4_CLKCTRL AM4_CLKCTRL_INDEX(0x458) -#define AM4_EPWMSS5_CLKCTRL AM4_CLKCTRL_INDEX(0x460) -#define AM4_ELM_CLKCTRL AM4_CLKCTRL_INDEX(0x468) -#define AM4_GPIO2_CLKCTRL AM4_CLKCTRL_INDEX(0x478) -#define AM4_GPIO3_CLKCTRL AM4_CLKCTRL_INDEX(0x480) -#define AM4_GPIO4_CLKCTRL AM4_CLKCTRL_INDEX(0x488) -#define AM4_GPIO5_CLKCTRL AM4_CLKCTRL_INDEX(0x490) -#define AM4_GPIO6_CLKCTRL AM4_CLKCTRL_INDEX(0x498) -#define AM4_HDQ1W_CLKCTRL AM4_CLKCTRL_INDEX(0x4a0) -#define AM4_I2C2_CLKCTRL AM4_CLKCTRL_INDEX(0x4a8) -#define AM4_I2C3_CLKCTRL AM4_CLKCTRL_INDEX(0x4b0) -#define AM4_MAILBOX_CLKCTRL AM4_CLKCTRL_INDEX(0x4b8) -#define AM4_MMC1_CLKCTRL AM4_CLKCTRL_INDEX(0x4c0) -#define AM4_MMC2_CLKCTRL AM4_CLKCTRL_INDEX(0x4c8) -#define AM4_RNG_CLKCTRL AM4_CLKCTRL_INDEX(0x4e0) -#define AM4_SPI0_CLKCTRL AM4_CLKCTRL_INDEX(0x500) -#define AM4_SPI1_CLKCTRL AM4_CLKCTRL_INDEX(0x508) -#define AM4_SPI2_CLKCTRL AM4_CLKCTRL_INDEX(0x510) -#define AM4_SPI3_CLKCTRL AM4_CLKCTRL_INDEX(0x518) -#define AM4_SPI4_CLKCTRL AM4_CLKCTRL_INDEX(0x520) -#define AM4_SPINLOCK_CLKCTRL AM4_CLKCTRL_INDEX(0x528) -#define AM4_TIMER2_CLKCTRL AM4_CLKCTRL_INDEX(0x530) -#define AM4_TIMER3_CLKCTRL AM4_CLKCTRL_INDEX(0x538) -#define AM4_TIMER4_CLKCTRL AM4_CLKCTRL_INDEX(0x540) -#define AM4_TIMER5_CLKCTRL AM4_CLKCTRL_INDEX(0x548) -#define AM4_TIMER6_CLKCTRL AM4_CLKCTRL_INDEX(0x550) -#define AM4_TIMER7_CLKCTRL AM4_CLKCTRL_INDEX(0x558) -#define AM4_TIMER8_CLKCTRL AM4_CLKCTRL_INDEX(0x560) -#define AM4_TIMER9_CLKCTRL AM4_CLKCTRL_INDEX(0x568) -#define AM4_TIMER10_CLKCTRL AM4_CLKCTRL_INDEX(0x570) -#define AM4_TIMER11_CLKCTRL AM4_CLKCTRL_INDEX(0x578) -#define AM4_UART2_CLKCTRL AM4_CLKCTRL_INDEX(0x580) -#define AM4_UART3_CLKCTRL AM4_CLKCTRL_INDEX(0x588) -#define AM4_UART4_CLKCTRL AM4_CLKCTRL_INDEX(0x590) -#define AM4_UART5_CLKCTRL AM4_CLKCTRL_INDEX(0x598) -#define AM4_UART6_CLKCTRL AM4_CLKCTRL_INDEX(0x5a0) -#define AM4_OCP2SCP0_CLKCTRL AM4_CLKCTRL_INDEX(0x5b8) -#define AM4_OCP2SCP1_CLKCTRL AM4_CLKCTRL_INDEX(0x5c0) -#define AM4_EMIF_CLKCTRL AM4_CLKCTRL_INDEX(0x720) -#define AM4_DSS_CORE_CLKCTRL AM4_CLKCTRL_INDEX(0xa20) -#define AM4_CPGMAC0_CLKCTRL AM4_CLKCTRL_INDEX(0xb20) - -/* XXX: Compatibility part end. */ - -/* l3s_tsc clocks */ -#define AM4_L3S_TSC_CLKCTRL_OFFSET 0x120 -#define AM4_L3S_TSC_CLKCTRL_INDEX(offset) ((offset) - AM4_L3S_TSC_CLKCTRL_OFFSET) -#define AM4_L3S_TSC_ADC_TSC_CLKCTRL AM4_L3S_TSC_CLKCTRL_INDEX(0x120) - -/* l4_wkup_aon clocks */ -#define AM4_L4_WKUP_AON_CLKCTRL_OFFSET 0x228 -#define AM4_L4_WKUP_AON_CLKCTRL_INDEX(offset) ((offset) - AM4_L4_WKUP_AON_CLKCTRL_OFFSET) -#define AM4_L4_WKUP_AON_WKUP_M3_CLKCTRL AM4_L4_WKUP_AON_CLKCTRL_INDEX(0x228) -#define AM4_L4_WKUP_AON_COUNTER_32K_CLKCTRL AM4_L4_WKUP_AON_CLKCTRL_INDEX(0x230) - -/* l4_wkup clocks */ -#define AM4_L4_WKUP_CLKCTRL_OFFSET 0x220 -#define AM4_L4_WKUP_CLKCTRL_INDEX(offset) ((offset) - AM4_L4_WKUP_CLKCTRL_OFFSET) -#define AM4_L4_WKUP_L4_WKUP_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x220) -#define AM4_L4_WKUP_TIMER1_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x328) -#define AM4_L4_WKUP_WD_TIMER2_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x338) -#define AM4_L4_WKUP_I2C1_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x340) -#define AM4_L4_WKUP_UART1_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x348) -#define AM4_L4_WKUP_SMARTREFLEX0_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x350) -#define AM4_L4_WKUP_SMARTREFLEX1_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x358) -#define AM4_L4_WKUP_CONTROL_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x360) -#define AM4_L4_WKUP_GPIO1_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x368) - -/* mpu clocks */ -#define AM4_MPU_MPU_CLKCTRL AM4_CLKCTRL_INDEX(0x20) - -/* gfx_l3 clocks */ -#define AM4_GFX_L3_GFX_CLKCTRL AM4_CLKCTRL_INDEX(0x20) - -/* l4_rtc clocks */ -#define AM4_L4_RTC_RTC_CLKCTRL AM4_CLKCTRL_INDEX(0x20) - -/* l3 clocks */ -#define AM4_L3_L3_MAIN_CLKCTRL AM4_CLKCTRL_INDEX(0x20) -#define AM4_L3_AES_CLKCTRL AM4_CLKCTRL_INDEX(0x28) -#define AM4_L3_DES_CLKCTRL AM4_CLKCTRL_INDEX(0x30) -#define AM4_L3_L3_INSTR_CLKCTRL AM4_CLKCTRL_INDEX(0x40) -#define AM4_L3_OCMCRAM_CLKCTRL AM4_CLKCTRL_INDEX(0x50) -#define AM4_L3_SHAM_CLKCTRL AM4_CLKCTRL_INDEX(0x58) -#define AM4_L3_TPCC_CLKCTRL AM4_CLKCTRL_INDEX(0x78) -#define AM4_L3_TPTC0_CLKCTRL AM4_CLKCTRL_INDEX(0x80) -#define AM4_L3_TPTC1_CLKCTRL AM4_CLKCTRL_INDEX(0x88) -#define AM4_L3_TPTC2_CLKCTRL AM4_CLKCTRL_INDEX(0x90) -#define AM4_L3_L4_HS_CLKCTRL AM4_CLKCTRL_INDEX(0xa0) - -/* l3s clocks */ -#define AM4_L3S_CLKCTRL_OFFSET 0x68 -#define AM4_L3S_CLKCTRL_INDEX(offset) ((offset) - AM4_L3S_CLKCTRL_OFFSET) -#define AM4_L3S_VPFE0_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x68) -#define AM4_L3S_VPFE1_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x70) -#define AM4_L3S_GPMC_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x220) -#define AM4_L3S_MCASP0_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x238) -#define AM4_L3S_MCASP1_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x240) -#define AM4_L3S_MMC3_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x248) -#define AM4_L3S_QSPI_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x258) -#define AM4_L3S_USB_OTG_SS0_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x260) -#define AM4_L3S_USB_OTG_SS1_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x268) - -/* pruss_ocp clocks */ -#define AM4_PRUSS_OCP_CLKCTRL_OFFSET 0x320 -#define AM4_PRUSS_OCP_CLKCTRL_INDEX(offset) ((offset) - AM4_PRUSS_OCP_CLKCTRL_OFFSET) -#define AM4_PRUSS_OCP_PRUSS_CLKCTRL AM4_PRUSS_OCP_CLKCTRL_INDEX(0x320) - -/* l4ls clocks */ -#define AM4_L4LS_CLKCTRL_OFFSET 0x420 -#define AM4_L4LS_CLKCTRL_INDEX(offset) ((offset) - AM4_L4LS_CLKCTRL_OFFSET) -#define AM4_L4LS_L4_LS_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x420) -#define AM4_L4LS_D_CAN0_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x428) -#define AM4_L4LS_D_CAN1_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x430) -#define AM4_L4LS_EPWMSS0_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x438) -#define AM4_L4LS_EPWMSS1_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x440) -#define AM4_L4LS_EPWMSS2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x448) -#define AM4_L4LS_EPWMSS3_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x450) -#define AM4_L4LS_EPWMSS4_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x458) -#define AM4_L4LS_EPWMSS5_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x460) -#define AM4_L4LS_ELM_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x468) -#define AM4_L4LS_GPIO2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x478) -#define AM4_L4LS_GPIO3_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x480) -#define AM4_L4LS_GPIO4_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x488) -#define AM4_L4LS_GPIO5_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x490) -#define AM4_L4LS_GPIO6_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x498) -#define AM4_L4LS_HDQ1W_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4a0) -#define AM4_L4LS_I2C2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4a8) -#define AM4_L4LS_I2C3_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4b0) -#define AM4_L4LS_MAILBOX_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4b8) -#define AM4_L4LS_MMC1_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4c0) -#define AM4_L4LS_MMC2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4c8) -#define AM4_L4LS_RNG_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4e0) -#define AM4_L4LS_SPI0_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x500) -#define AM4_L4LS_SPI1_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x508) -#define AM4_L4LS_SPI2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x510) -#define AM4_L4LS_SPI3_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x518) -#define AM4_L4LS_SPI4_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x520) -#define AM4_L4LS_SPINLOCK_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x528) -#define AM4_L4LS_TIMER2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x530) -#define AM4_L4LS_TIMER3_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x538) -#define AM4_L4LS_TIMER4_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x540) -#define AM4_L4LS_TIMER5_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x548) -#define AM4_L4LS_TIMER6_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x550) -#define AM4_L4LS_TIMER7_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x558) -#define AM4_L4LS_TIMER8_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x560) -#define AM4_L4LS_TIMER9_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x568) -#define AM4_L4LS_TIMER10_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x570) -#define AM4_L4LS_TIMER11_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x578) -#define AM4_L4LS_UART2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x580) -#define AM4_L4LS_UART3_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x588) -#define AM4_L4LS_UART4_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x590) -#define AM4_L4LS_UART5_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x598) -#define AM4_L4LS_UART6_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x5a0) -#define AM4_L4LS_OCP2SCP0_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x5b8) -#define AM4_L4LS_OCP2SCP1_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x5c0) - -/* emif clocks */ -#define AM4_EMIF_CLKCTRL_OFFSET 0x720 -#define AM4_EMIF_CLKCTRL_INDEX(offset) ((offset) - AM4_EMIF_CLKCTRL_OFFSET) -#define AM4_EMIF_EMIF_CLKCTRL AM4_EMIF_CLKCTRL_INDEX(0x720) - -/* dss clocks */ -#define AM4_DSS_CLKCTRL_OFFSET 0xa20 -#define AM4_DSS_CLKCTRL_INDEX(offset) ((offset) - AM4_DSS_CLKCTRL_OFFSET) -#define AM4_DSS_DSS_CORE_CLKCTRL AM4_DSS_CLKCTRL_INDEX(0xa20) - -/* cpsw_125mhz clocks */ -#define AM4_CPSW_125MHZ_CLKCTRL_OFFSET 0xb20 -#define AM4_CPSW_125MHZ_CLKCTRL_INDEX(offset) ((offset) - AM4_CPSW_125MHZ_CLKCTRL_OFFSET) -#define AM4_CPSW_125MHZ_CPGMAC0_CLKCTRL AM4_CPSW_125MHZ_CLKCTRL_INDEX(0xb20) - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/aspeed-clock.h b/sys/gnu/dts/include/dt-bindings/clock/aspeed-clock.h deleted file mode 100644 index 9ff4f6e4558..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/aspeed-clock.h +++ /dev/null @@ -1,56 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ - -#ifndef DT_BINDINGS_ASPEED_CLOCK_H -#define DT_BINDINGS_ASPEED_CLOCK_H - -#define ASPEED_CLK_GATE_ECLK 0 -#define ASPEED_CLK_GATE_GCLK 1 -#define ASPEED_CLK_GATE_MCLK 2 -#define ASPEED_CLK_GATE_VCLK 3 -#define ASPEED_CLK_GATE_BCLK 4 -#define ASPEED_CLK_GATE_DCLK 5 -#define ASPEED_CLK_GATE_REFCLK 6 -#define ASPEED_CLK_GATE_USBPORT2CLK 7 -#define ASPEED_CLK_GATE_LCLK 8 -#define ASPEED_CLK_GATE_USBUHCICLK 9 -#define ASPEED_CLK_GATE_D1CLK 10 -#define ASPEED_CLK_GATE_YCLK 11 -#define ASPEED_CLK_GATE_USBPORT1CLK 12 -#define ASPEED_CLK_GATE_UART1CLK 13 -#define ASPEED_CLK_GATE_UART2CLK 14 -#define ASPEED_CLK_GATE_UART5CLK 15 -#define ASPEED_CLK_GATE_ESPICLK 16 -#define ASPEED_CLK_GATE_MAC1CLK 17 -#define ASPEED_CLK_GATE_MAC2CLK 18 -#define ASPEED_CLK_GATE_RSACLK 19 -#define ASPEED_CLK_GATE_UART3CLK 20 -#define ASPEED_CLK_GATE_UART4CLK 21 -#define ASPEED_CLK_GATE_SDCLK 22 -#define ASPEED_CLK_GATE_LHCCLK 23 -#define ASPEED_CLK_HPLL 24 -#define ASPEED_CLK_AHB 25 -#define ASPEED_CLK_APB 26 -#define ASPEED_CLK_UART 27 -#define ASPEED_CLK_SDIO 28 -#define ASPEED_CLK_ECLK 29 -#define ASPEED_CLK_ECLK_MUX 30 -#define ASPEED_CLK_LHCLK 31 -#define ASPEED_CLK_MAC 32 -#define ASPEED_CLK_BCLK 33 -#define ASPEED_CLK_MPLL 34 -#define ASPEED_CLK_24M 35 -#define ASPEED_CLK_MAC1RCLK 36 -#define ASPEED_CLK_MAC2RCLK 37 - -#define ASPEED_RESET_XDMA 0 -#define ASPEED_RESET_MCTP 1 -#define ASPEED_RESET_ADC 2 -#define ASPEED_RESET_JTAG_MASTER 3 -#define ASPEED_RESET_MIC 4 -#define ASPEED_RESET_PWM 5 -#define ASPEED_RESET_PECI 6 -#define ASPEED_RESET_I2C 7 -#define ASPEED_RESET_AHB 8 -#define ASPEED_RESET_CRT1 9 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/ast2600-clock.h b/sys/gnu/dts/include/dt-bindings/clock/ast2600-clock.h deleted file mode 100644 index 62b9520a00f..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/ast2600-clock.h +++ /dev/null @@ -1,117 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later OR MIT */ -#ifndef DT_BINDINGS_AST2600_CLOCK_H -#define DT_BINDINGS_AST2600_CLOCK_H - -#define ASPEED_CLK_GATE_ECLK 0 -#define ASPEED_CLK_GATE_GCLK 1 - -#define ASPEED_CLK_GATE_MCLK 2 - -#define ASPEED_CLK_GATE_VCLK 3 -#define ASPEED_CLK_GATE_BCLK 4 -#define ASPEED_CLK_GATE_DCLK 5 - -#define ASPEED_CLK_GATE_LCLK 6 -#define ASPEED_CLK_GATE_LHCCLK 7 - -#define ASPEED_CLK_GATE_D1CLK 8 -#define ASPEED_CLK_GATE_YCLK 9 - -#define ASPEED_CLK_GATE_REF0CLK 10 -#define ASPEED_CLK_GATE_REF1CLK 11 - -#define ASPEED_CLK_GATE_ESPICLK 12 - -#define ASPEED_CLK_GATE_USBUHCICLK 13 -#define ASPEED_CLK_GATE_USBPORT1CLK 14 -#define ASPEED_CLK_GATE_USBPORT2CLK 15 - -#define ASPEED_CLK_GATE_RSACLK 16 -#define ASPEED_CLK_GATE_RVASCLK 17 - -#define ASPEED_CLK_GATE_MAC1CLK 18 -#define ASPEED_CLK_GATE_MAC2CLK 19 -#define ASPEED_CLK_GATE_MAC3CLK 20 -#define ASPEED_CLK_GATE_MAC4CLK 21 - -#define ASPEED_CLK_GATE_UART1CLK 22 -#define ASPEED_CLK_GATE_UART2CLK 23 -#define ASPEED_CLK_GATE_UART3CLK 24 -#define ASPEED_CLK_GATE_UART4CLK 25 -#define ASPEED_CLK_GATE_UART5CLK 26 -#define ASPEED_CLK_GATE_UART6CLK 27 -#define ASPEED_CLK_GATE_UART7CLK 28 -#define ASPEED_CLK_GATE_UART8CLK 29 -#define ASPEED_CLK_GATE_UART9CLK 30 -#define ASPEED_CLK_GATE_UART10CLK 31 -#define ASPEED_CLK_GATE_UART11CLK 32 -#define ASPEED_CLK_GATE_UART12CLK 33 -#define ASPEED_CLK_GATE_UART13CLK 34 - -#define ASPEED_CLK_GATE_SDCLK 35 -#define ASPEED_CLK_GATE_EMMCCLK 36 - -#define ASPEED_CLK_GATE_I3C0CLK 37 -#define ASPEED_CLK_GATE_I3C1CLK 38 -#define ASPEED_CLK_GATE_I3C2CLK 39 -#define ASPEED_CLK_GATE_I3C3CLK 40 -#define ASPEED_CLK_GATE_I3C4CLK 41 -#define ASPEED_CLK_GATE_I3C5CLK 42 -#define ASPEED_CLK_GATE_I3C6CLK 43 -#define ASPEED_CLK_GATE_I3C7CLK 44 - -#define ASPEED_CLK_GATE_FSICLK 45 - -#define ASPEED_CLK_HPLL 46 -#define ASPEED_CLK_MPLL 47 -#define ASPEED_CLK_DPLL 48 -#define ASPEED_CLK_EPLL 49 -#define ASPEED_CLK_APLL 50 -#define ASPEED_CLK_AHB 51 -#define ASPEED_CLK_APB1 52 -#define ASPEED_CLK_APB2 53 -#define ASPEED_CLK_BCLK 54 -#define ASPEED_CLK_D1CLK 55 -#define ASPEED_CLK_VCLK 56 -#define ASPEED_CLK_LHCLK 57 -#define ASPEED_CLK_UART 58 -#define ASPEED_CLK_UARTX 59 -#define ASPEED_CLK_SDIO 60 -#define ASPEED_CLK_EMMC 61 -#define ASPEED_CLK_ECLK 62 -#define ASPEED_CLK_ECLK_MUX 63 -#define ASPEED_CLK_MAC12 64 -#define ASPEED_CLK_MAC34 65 -#define ASPEED_CLK_USBPHY_40M 66 -#define ASPEED_CLK_MAC1RCLK 67 -#define ASPEED_CLK_MAC2RCLK 68 -#define ASPEED_CLK_MAC3RCLK 69 -#define ASPEED_CLK_MAC4RCLK 70 - -/* Only list resets here that are not part of a gate */ -#define ASPEED_RESET_ADC 55 -#define ASPEED_RESET_JTAG_MASTER2 54 -#define ASPEED_RESET_I3C_DMA 39 -#define ASPEED_RESET_PWM 37 -#define ASPEED_RESET_PECI 36 -#define ASPEED_RESET_MII 35 -#define ASPEED_RESET_I2C 34 -#define ASPEED_RESET_H2X 31 -#define ASPEED_RESET_GP_MCU 30 -#define ASPEED_RESET_DP_MCU 29 -#define ASPEED_RESET_DP 28 -#define ASPEED_RESET_RC_XDMA 27 -#define ASPEED_RESET_GRAPHICS 26 -#define ASPEED_RESET_DEV_XDMA 25 -#define ASPEED_RESET_DEV_MCTP 24 -#define ASPEED_RESET_RC_MCTP 23 -#define ASPEED_RESET_JTAG_MASTER 22 -#define ASPEED_RESET_PCIE_DEV_O 21 -#define ASPEED_RESET_PCIE_DEV_OEN 20 -#define ASPEED_RESET_PCIE_RC_O 19 -#define ASPEED_RESET_PCIE_RC_OEN 18 -#define ASPEED_RESET_PCI_DP 5 -#define ASPEED_RESET_AHB 1 -#define ASPEED_RESET_SDRAM 0 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/at91.h b/sys/gnu/dts/include/dt-bindings/clock/at91.h deleted file mode 100644 index 38b5554153c..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/at91.h +++ /dev/null @@ -1,37 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * This header provides constants for AT91 pmc status. - * - * The constants defined in this header are being used in dts. - */ - -#ifndef _DT_BINDINGS_CLK_AT91_H -#define _DT_BINDINGS_CLK_AT91_H - -#define PMC_TYPE_CORE 0 -#define PMC_TYPE_SYSTEM 1 -#define PMC_TYPE_PERIPHERAL 2 -#define PMC_TYPE_GCK 3 - -#define PMC_SLOW 0 -#define PMC_MCK 1 -#define PMC_UTMI 2 -#define PMC_MAIN 3 -#define PMC_MCK2 4 -#define PMC_I2S0_MUX 5 -#define PMC_I2S1_MUX 6 - -#ifndef AT91_PMC_MOSCS -#define AT91_PMC_MOSCS 0 /* MOSCS Flag */ -#define AT91_PMC_LOCKA 1 /* PLLA Lock */ -#define AT91_PMC_LOCKB 2 /* PLLB Lock */ -#define AT91_PMC_MCKRDY 3 /* Master Clock */ -#define AT91_PMC_LOCKU 6 /* UPLL Lock */ -#define AT91_PMC_PCKRDY(id) (8 + (id)) /* Programmable Clock */ -#define AT91_PMC_MOSCSELS 16 /* Main Oscillator Selection */ -#define AT91_PMC_MOSCRCS 17 /* Main On-Chip RC */ -#define AT91_PMC_CFDEV 18 /* Clock Failure Detector Event */ -#define AT91_PMC_GCKRDY 24 /* Generated Clocks */ -#endif - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/ath79-clk.h b/sys/gnu/dts/include/dt-bindings/clock/ath79-clk.h deleted file mode 100644 index eec8f399b9e..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/ath79-clk.h +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) 2014, 2016 Antony Pavlov - */ - -#ifndef __DT_BINDINGS_ATH79_CLK_H -#define __DT_BINDINGS_ATH79_CLK_H - -#define ATH79_CLK_CPU 0 -#define ATH79_CLK_DDR 1 -#define ATH79_CLK_AHB 2 -#define ATH79_CLK_REF 3 -#define ATH79_CLK_MDIO 4 - -#define ATH79_CLK_END 5 - -#endif /* __DT_BINDINGS_ATH79_CLK_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/axg-aoclkc.h b/sys/gnu/dts/include/dt-bindings/clock/axg-aoclkc.h deleted file mode 100644 index 8ec4a269c7a..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/axg-aoclkc.h +++ /dev/null @@ -1,31 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ -/* - * Copyright (c) 2016 BayLibre, SAS - * Author: Neil Armstrong - * - * Copyright (c) 2018 Amlogic, inc. - * Author: Qiufang Dai - */ - -#ifndef DT_BINDINGS_CLOCK_AMLOGIC_MESON_AXG_AOCLK -#define DT_BINDINGS_CLOCK_AMLOGIC_MESON_AXG_AOCLK - -#define CLKID_AO_REMOTE 0 -#define CLKID_AO_I2C_MASTER 1 -#define CLKID_AO_I2C_SLAVE 2 -#define CLKID_AO_UART1 3 -#define CLKID_AO_UART2 4 -#define CLKID_AO_IR_BLASTER 5 -#define CLKID_AO_SAR_ADC 6 -#define CLKID_AO_CLK81 7 -#define CLKID_AO_SAR_ADC_SEL 8 -#define CLKID_AO_SAR_ADC_DIV 9 -#define CLKID_AO_SAR_ADC_CLK 10 -#define CLKID_AO_CTS_OSCIN 11 -#define CLKID_AO_32K_PRE 12 -#define CLKID_AO_32K_DIV 13 -#define CLKID_AO_32K_SEL 14 -#define CLKID_AO_32K 15 -#define CLKID_AO_CTS_RTC_OSCIN 16 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/axg-audio-clkc.h b/sys/gnu/dts/include/dt-bindings/clock/axg-audio-clkc.h deleted file mode 100644 index f561f5c5ef8..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/axg-audio-clkc.h +++ /dev/null @@ -1,94 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ -/* - * Copyright (c) 2018 Baylibre SAS. - * Author: Jerome Brunet - */ - -#ifndef __AXG_AUDIO_CLKC_BINDINGS_H -#define __AXG_AUDIO_CLKC_BINDINGS_H - -#define AUD_CLKID_DDR_ARB 29 -#define AUD_CLKID_PDM 30 -#define AUD_CLKID_TDMIN_A 31 -#define AUD_CLKID_TDMIN_B 32 -#define AUD_CLKID_TDMIN_C 33 -#define AUD_CLKID_TDMIN_LB 34 -#define AUD_CLKID_TDMOUT_A 35 -#define AUD_CLKID_TDMOUT_B 36 -#define AUD_CLKID_TDMOUT_C 37 -#define AUD_CLKID_FRDDR_A 38 -#define AUD_CLKID_FRDDR_B 39 -#define AUD_CLKID_FRDDR_C 40 -#define AUD_CLKID_TODDR_A 41 -#define AUD_CLKID_TODDR_B 42 -#define AUD_CLKID_TODDR_C 43 -#define AUD_CLKID_LOOPBACK 44 -#define AUD_CLKID_SPDIFIN 45 -#define AUD_CLKID_SPDIFOUT 46 -#define AUD_CLKID_RESAMPLE 47 -#define AUD_CLKID_POWER_DETECT 48 -#define AUD_CLKID_MST_A_MCLK 49 -#define AUD_CLKID_MST_B_MCLK 50 -#define AUD_CLKID_MST_C_MCLK 51 -#define AUD_CLKID_MST_D_MCLK 52 -#define AUD_CLKID_MST_E_MCLK 53 -#define AUD_CLKID_MST_F_MCLK 54 -#define AUD_CLKID_SPDIFOUT_CLK 55 -#define AUD_CLKID_SPDIFIN_CLK 56 -#define AUD_CLKID_PDM_DCLK 57 -#define AUD_CLKID_PDM_SYSCLK 58 -#define AUD_CLKID_MST_A_SCLK 79 -#define AUD_CLKID_MST_B_SCLK 80 -#define AUD_CLKID_MST_C_SCLK 81 -#define AUD_CLKID_MST_D_SCLK 82 -#define AUD_CLKID_MST_E_SCLK 83 -#define AUD_CLKID_MST_F_SCLK 84 -#define AUD_CLKID_MST_A_LRCLK 86 -#define AUD_CLKID_MST_B_LRCLK 87 -#define AUD_CLKID_MST_C_LRCLK 88 -#define AUD_CLKID_MST_D_LRCLK 89 -#define AUD_CLKID_MST_E_LRCLK 90 -#define AUD_CLKID_MST_F_LRCLK 91 -#define AUD_CLKID_TDMIN_A_SCLK_SEL 116 -#define AUD_CLKID_TDMIN_B_SCLK_SEL 117 -#define AUD_CLKID_TDMIN_C_SCLK_SEL 118 -#define AUD_CLKID_TDMIN_LB_SCLK_SEL 119 -#define AUD_CLKID_TDMOUT_A_SCLK_SEL 120 -#define AUD_CLKID_TDMOUT_B_SCLK_SEL 121 -#define AUD_CLKID_TDMOUT_C_SCLK_SEL 122 -#define AUD_CLKID_TDMIN_A_SCLK 123 -#define AUD_CLKID_TDMIN_B_SCLK 124 -#define AUD_CLKID_TDMIN_C_SCLK 125 -#define AUD_CLKID_TDMIN_LB_SCLK 126 -#define AUD_CLKID_TDMOUT_A_SCLK 127 -#define AUD_CLKID_TDMOUT_B_SCLK 128 -#define AUD_CLKID_TDMOUT_C_SCLK 129 -#define AUD_CLKID_TDMIN_A_LRCLK 130 -#define AUD_CLKID_TDMIN_B_LRCLK 131 -#define AUD_CLKID_TDMIN_C_LRCLK 132 -#define AUD_CLKID_TDMIN_LB_LRCLK 133 -#define AUD_CLKID_TDMOUT_A_LRCLK 134 -#define AUD_CLKID_TDMOUT_B_LRCLK 135 -#define AUD_CLKID_TDMOUT_C_LRCLK 136 -#define AUD_CLKID_SPDIFOUT_B 151 -#define AUD_CLKID_SPDIFOUT_B_CLK 152 -#define AUD_CLKID_TDM_MCLK_PAD0 155 -#define AUD_CLKID_TDM_MCLK_PAD1 156 -#define AUD_CLKID_TDM_LRCLK_PAD0 157 -#define AUD_CLKID_TDM_LRCLK_PAD1 158 -#define AUD_CLKID_TDM_LRCLK_PAD2 159 -#define AUD_CLKID_TDM_SCLK_PAD0 160 -#define AUD_CLKID_TDM_SCLK_PAD1 161 -#define AUD_CLKID_TDM_SCLK_PAD2 162 -#define AUD_CLKID_TOP 163 -#define AUD_CLKID_TORAM 164 -#define AUD_CLKID_EQDRC 165 -#define AUD_CLKID_RESAMPLE_B 166 -#define AUD_CLKID_TOVAD 167 -#define AUD_CLKID_LOCKER 168 -#define AUD_CLKID_SPDIFIN_LB 169 -#define AUD_CLKID_FRDDR_D 170 -#define AUD_CLKID_TODDR_D 171 -#define AUD_CLKID_LOOPBACK_B 172 - -#endif /* __AXG_AUDIO_CLKC_BINDINGS_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/axg-clkc.h b/sys/gnu/dts/include/dt-bindings/clock/axg-clkc.h deleted file mode 100644 index fd1f938c38d..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/axg-clkc.h +++ /dev/null @@ -1,76 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ -/* - * Meson-AXG clock tree IDs - * - * Copyright (c) 2017 Amlogic, Inc. All rights reserved. - */ - -#ifndef __AXG_CLKC_H -#define __AXG_CLKC_H - -#define CLKID_SYS_PLL 0 -#define CLKID_FIXED_PLL 1 -#define CLKID_FCLK_DIV2 2 -#define CLKID_FCLK_DIV3 3 -#define CLKID_FCLK_DIV4 4 -#define CLKID_FCLK_DIV5 5 -#define CLKID_FCLK_DIV7 6 -#define CLKID_GP0_PLL 7 -#define CLKID_CLK81 10 -#define CLKID_MPLL0 11 -#define CLKID_MPLL1 12 -#define CLKID_MPLL2 13 -#define CLKID_MPLL3 14 -#define CLKID_DDR 15 -#define CLKID_AUDIO_LOCKER 16 -#define CLKID_MIPI_DSI_HOST 17 -#define CLKID_ISA 18 -#define CLKID_PL301 19 -#define CLKID_PERIPHS 20 -#define CLKID_SPICC0 21 -#define CLKID_I2C 22 -#define CLKID_RNG0 23 -#define CLKID_UART0 24 -#define CLKID_MIPI_DSI_PHY 25 -#define CLKID_SPICC1 26 -#define CLKID_PCIE_A 27 -#define CLKID_PCIE_B 28 -#define CLKID_HIU_IFACE 29 -#define CLKID_ASSIST_MISC 30 -#define CLKID_SD_EMMC_B 31 -#define CLKID_SD_EMMC_C 32 -#define CLKID_DMA 33 -#define CLKID_SPI 34 -#define CLKID_AUDIO 35 -#define CLKID_ETH 36 -#define CLKID_UART1 37 -#define CLKID_G2D 38 -#define CLKID_USB0 39 -#define CLKID_USB1 40 -#define CLKID_RESET 41 -#define CLKID_USB 42 -#define CLKID_AHB_ARB0 43 -#define CLKID_EFUSE 44 -#define CLKID_BOOT_ROM 45 -#define CLKID_AHB_DATA_BUS 46 -#define CLKID_AHB_CTRL_BUS 47 -#define CLKID_USB1_DDR_BRIDGE 48 -#define CLKID_USB0_DDR_BRIDGE 49 -#define CLKID_MMC_PCLK 50 -#define CLKID_VPU_INTR 51 -#define CLKID_SEC_AHB_AHB3_BRIDGE 52 -#define CLKID_GIC 53 -#define CLKID_AO_MEDIA_CPU 54 -#define CLKID_AO_AHB_SRAM 55 -#define CLKID_AO_AHB_BUS 56 -#define CLKID_AO_IFACE 57 -#define CLKID_AO_I2C 58 -#define CLKID_SD_EMMC_B_CLK0 59 -#define CLKID_SD_EMMC_C_CLK0 60 -#define CLKID_HIFI_PLL 69 -#define CLKID_PCIE_CML_EN0 79 -#define CLKID_PCIE_CML_EN1 80 -#define CLKID_MIPI_ENABLE 81 -#define CLKID_GEN_CLK 84 - -#endif /* __AXG_CLKC_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/axis,artpec6-clkctrl.h b/sys/gnu/dts/include/dt-bindings/clock/axis,artpec6-clkctrl.h deleted file mode 100644 index b1f4971642e..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/axis,artpec6-clkctrl.h +++ /dev/null @@ -1,35 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * ARTPEC-6 clock controller indexes - * - * Copyright 2016 Axis Comunications AB. - */ - -#ifndef DT_BINDINGS_CLK_ARTPEC6_CLKCTRL_H -#define DT_BINDINGS_CLK_ARTPEC6_CLKCTRL_H - -#define ARTPEC6_CLK_CPU 0 -#define ARTPEC6_CLK_CPU_PERIPH 1 -#define ARTPEC6_CLK_NAND_CLKA 2 -#define ARTPEC6_CLK_NAND_CLKB 3 -#define ARTPEC6_CLK_ETH_ACLK 4 -#define ARTPEC6_CLK_DMA_ACLK 5 -#define ARTPEC6_CLK_PTP_REF 6 -#define ARTPEC6_CLK_SD_PCLK 7 -#define ARTPEC6_CLK_SD_IMCLK 8 -#define ARTPEC6_CLK_I2S_HST 9 -#define ARTPEC6_CLK_I2S0_CLK 10 -#define ARTPEC6_CLK_I2S1_CLK 11 -#define ARTPEC6_CLK_UART_PCLK 12 -#define ARTPEC6_CLK_UART_REFCLK 13 -#define ARTPEC6_CLK_I2C 14 -#define ARTPEC6_CLK_SPI_PCLK 15 -#define ARTPEC6_CLK_SPI_SSPCLK 16 -#define ARTPEC6_CLK_SYS_TIMER 17 -#define ARTPEC6_CLK_FRACDIV_IN 18 -#define ARTPEC6_CLK_DBG_PCLK 19 - -/* This must be the highest clock index plus one. */ -#define ARTPEC6_CLK_NUMCLOCKS 20 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/bcm-cygnus.h b/sys/gnu/dts/include/dt-bindings/clock/bcm-cygnus.h deleted file mode 100644 index 62ac5d782a0..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/bcm-cygnus.h +++ /dev/null @@ -1,74 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright(c) 2014 Broadcom Corporation. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _CLOCK_BCM_CYGNUS_H -#define _CLOCK_BCM_CYGNUS_H - -/* GENPLL clock ID */ -#define BCM_CYGNUS_GENPLL 0 -#define BCM_CYGNUS_GENPLL_AXI21_CLK 1 -#define BCM_CYGNUS_GENPLL_250MHZ_CLK 2 -#define BCM_CYGNUS_GENPLL_IHOST_SYS_CLK 3 -#define BCM_CYGNUS_GENPLL_ENET_SW_CLK 4 -#define BCM_CYGNUS_GENPLL_AUDIO_125_CLK 5 -#define BCM_CYGNUS_GENPLL_CAN_CLK 6 - -/* LCPLL0 clock ID */ -#define BCM_CYGNUS_LCPLL0 0 -#define BCM_CYGNUS_LCPLL0_PCIE_PHY_REF_CLK 1 -#define BCM_CYGNUS_LCPLL0_DDR_PHY_CLK 2 -#define BCM_CYGNUS_LCPLL0_SDIO_CLK 3 -#define BCM_CYGNUS_LCPLL0_USB_PHY_REF_CLK 4 -#define BCM_CYGNUS_LCPLL0_SMART_CARD_CLK 5 -#define BCM_CYGNUS_LCPLL0_CH5_UNUSED 6 - -/* MIPI PLL clock ID */ -#define BCM_CYGNUS_MIPIPLL 0 -#define BCM_CYGNUS_MIPIPLL_CH0_UNUSED 1 -#define BCM_CYGNUS_MIPIPLL_CH1_LCD 2 -#define BCM_CYGNUS_MIPIPLL_CH2_V3D 3 -#define BCM_CYGNUS_MIPIPLL_CH3_UNUSED 4 -#define BCM_CYGNUS_MIPIPLL_CH4_UNUSED 5 -#define BCM_CYGNUS_MIPIPLL_CH5_UNUSED 6 - -/* ASIU clock ID */ -#define BCM_CYGNUS_ASIU_KEYPAD_CLK 0 -#define BCM_CYGNUS_ASIU_ADC_CLK 1 -#define BCM_CYGNUS_ASIU_PWM_CLK 2 - -/* AUDIO clock ID */ -#define BCM_CYGNUS_AUDIOPLL 0 -#define BCM_CYGNUS_AUDIOPLL_CH0 1 -#define BCM_CYGNUS_AUDIOPLL_CH1 2 -#define BCM_CYGNUS_AUDIOPLL_CH2 3 - -#endif /* _CLOCK_BCM_CYGNUS_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/bcm-ns2.h b/sys/gnu/dts/include/dt-bindings/clock/bcm-ns2.h deleted file mode 100644 index d99c7a2e70c..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/bcm-ns2.h +++ /dev/null @@ -1,72 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright(c) 2015 Broadcom Corporation. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _CLOCK_BCM_NS2_H -#define _CLOCK_BCM_NS2_H - -/* GENPLL SCR clock channel ID */ -#define BCM_NS2_GENPLL_SCR 0 -#define BCM_NS2_GENPLL_SCR_SCR_CLK 1 -#define BCM_NS2_GENPLL_SCR_FS_CLK 2 -#define BCM_NS2_GENPLL_SCR_AUDIO_CLK 3 -#define BCM_NS2_GENPLL_SCR_CH3_UNUSED 4 -#define BCM_NS2_GENPLL_SCR_CH4_UNUSED 5 -#define BCM_NS2_GENPLL_SCR_CH5_UNUSED 6 - -/* GENPLL SW clock channel ID */ -#define BCM_NS2_GENPLL_SW 0 -#define BCM_NS2_GENPLL_SW_RPE_CLK 1 -#define BCM_NS2_GENPLL_SW_250_CLK 2 -#define BCM_NS2_GENPLL_SW_NIC_CLK 3 -#define BCM_NS2_GENPLL_SW_CHIMP_CLK 4 -#define BCM_NS2_GENPLL_SW_PORT_CLK 5 -#define BCM_NS2_GENPLL_SW_SDIO_CLK 6 - -/* LCPLL DDR clock channel ID */ -#define BCM_NS2_LCPLL_DDR 0 -#define BCM_NS2_LCPLL_DDR_PCIE_SATA_USB_CLK 1 -#define BCM_NS2_LCPLL_DDR_DDR_CLK 2 -#define BCM_NS2_LCPLL_DDR_CH2_UNUSED 3 -#define BCM_NS2_LCPLL_DDR_CH3_UNUSED 4 -#define BCM_NS2_LCPLL_DDR_CH4_UNUSED 5 -#define BCM_NS2_LCPLL_DDR_CH5_UNUSED 6 - -/* LCPLL PORTS clock channel ID */ -#define BCM_NS2_LCPLL_PORTS 0 -#define BCM_NS2_LCPLL_PORTS_WAN_CLK 1 -#define BCM_NS2_LCPLL_PORTS_RGMII_CLK 2 -#define BCM_NS2_LCPLL_PORTS_CH2_UNUSED 3 -#define BCM_NS2_LCPLL_PORTS_CH3_UNUSED 4 -#define BCM_NS2_LCPLL_PORTS_CH4_UNUSED 5 -#define BCM_NS2_LCPLL_PORTS_CH5_UNUSED 6 - -#endif /* _CLOCK_BCM_NS2_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/bcm-nsp.h b/sys/gnu/dts/include/dt-bindings/clock/bcm-nsp.h deleted file mode 100644 index ad5827cde78..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/bcm-nsp.h +++ /dev/null @@ -1,51 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright(c) 2015 Broadcom Corporation. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _CLOCK_BCM_NSP_H -#define _CLOCK_BCM_NSP_H - -/* GENPLL clock channel ID */ -#define BCM_NSP_GENPLL 0 -#define BCM_NSP_GENPLL_PHY_CLK 1 -#define BCM_NSP_GENPLL_ENET_SW_CLK 2 -#define BCM_NSP_GENPLL_USB_PHY_REF_CLK 3 -#define BCM_NSP_GENPLL_IPROCFAST_CLK 4 -#define BCM_NSP_GENPLL_SATA1_CLK 5 -#define BCM_NSP_GENPLL_SATA2_CLK 6 - -/* LCPLL0 clock channel ID */ -#define BCM_NSP_LCPLL0 0 -#define BCM_NSP_LCPLL0_PCIE_PHY_REF_CLK 1 -#define BCM_NSP_LCPLL0_SDIO_CLK 2 -#define BCM_NSP_LCPLL0_DDR_PHY_CLK 3 - -#endif /* _CLOCK_BCM_NSP_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/bcm-sr.h b/sys/gnu/dts/include/dt-bindings/clock/bcm-sr.h deleted file mode 100644 index 419011ba1a9..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/bcm-sr.h +++ /dev/null @@ -1,111 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright(c) 2017 Broadcom. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _CLOCK_BCM_SR_H -#define _CLOCK_BCM_SR_H - -/* GENPLL 0 clock channel ID SCR HSLS FS PCIE */ -#define BCM_SR_GENPLL0 0 -#define BCM_SR_GENPLL0_125M_CLK 1 -#define BCM_SR_GENPLL0_SCR_CLK 2 -#define BCM_SR_GENPLL0_250M_CLK 3 -#define BCM_SR_GENPLL0_PCIE_AXI_CLK 4 -#define BCM_SR_GENPLL0_PAXC_AXI_X2_CLK 5 -#define BCM_SR_GENPLL0_PAXC_AXI_CLK 6 - -/* GENPLL 1 clock channel ID MHB PCIE NITRO */ -#define BCM_SR_GENPLL1 0 -#define BCM_SR_GENPLL1_PCIE_TL_CLK 1 -#define BCM_SR_GENPLL1_MHB_APB_CLK 2 - -/* GENPLL 2 clock channel ID NITRO MHB*/ -#define BCM_SR_GENPLL2 0 -#define BCM_SR_GENPLL2_NIC_CLK 1 -#define BCM_SR_GENPLL2_TS_500_CLK 2 -#define BCM_SR_GENPLL2_125_NITRO_CLK 3 -#define BCM_SR_GENPLL2_CHIMP_CLK 4 -#define BCM_SR_GENPLL2_NIC_FLASH_CLK 5 -#define BCM_SR_GENPLL2_FS4_CLK 6 - -/* GENPLL 3 HSLS clock channel ID */ -#define BCM_SR_GENPLL3 0 -#define BCM_SR_GENPLL3_HSLS_CLK 1 -#define BCM_SR_GENPLL3_SDIO_CLK 2 - -/* GENPLL 4 SCR clock channel ID */ -#define BCM_SR_GENPLL4 0 -#define BCM_SR_GENPLL4_CCN_CLK 1 -#define BCM_SR_GENPLL4_TPIU_PLL_CLK 2 -#define BCM_SR_GENPLL4_NOC_CLK 3 -#define BCM_SR_GENPLL4_CHCLK_FS4_CLK 4 -#define BCM_SR_GENPLL4_BRIDGE_FSCPU_CLK 5 - -/* GENPLL 5 FS4 clock channel ID */ -#define BCM_SR_GENPLL5 0 -#define BCM_SR_GENPLL5_FS4_HF_CLK 1 -#define BCM_SR_GENPLL5_CRYPTO_AE_CLK 2 -#define BCM_SR_GENPLL5_RAID_AE_CLK 3 - -/* GENPLL 6 NITRO clock channel ID */ -#define BCM_SR_GENPLL6 0 -#define BCM_SR_GENPLL6_48_USB_CLK 1 - -/* LCPLL0 clock channel ID */ -#define BCM_SR_LCPLL0 0 -#define BCM_SR_LCPLL0_SATA_REFP_CLK 1 -#define BCM_SR_LCPLL0_SATA_REFN_CLK 2 -#define BCM_SR_LCPLL0_SATA_350_CLK 3 -#define BCM_SR_LCPLL0_SATA_500_CLK 4 - -/* LCPLL1 clock channel ID */ -#define BCM_SR_LCPLL1 0 -#define BCM_SR_LCPLL1_WAN_CLK 1 -#define BCM_SR_LCPLL1_USB_REF_CLK 2 -#define BCM_SR_LCPLL1_CRMU_TS_CLK 3 - -/* LCPLL PCIE clock channel ID */ -#define BCM_SR_LCPLL_PCIE 0 -#define BCM_SR_LCPLL_PCIE_PHY_REF_CLK 1 - -/* GENPLL EMEM0 clock channel ID */ -#define BCM_SR_EMEMPLL0 0 -#define BCM_SR_EMEMPLL0_EMEM_CLK 1 - -/* GENPLL EMEM0 clock channel ID */ -#define BCM_SR_EMEMPLL1 0 -#define BCM_SR_EMEMPLL1_EMEM_CLK 1 - -/* GENPLL EMEM0 clock channel ID */ -#define BCM_SR_EMEMPLL2 0 -#define BCM_SR_EMEMPLL2_EMEM_CLK 1 - -#endif /* _CLOCK_BCM_SR_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/bcm21664.h b/sys/gnu/dts/include/dt-bindings/clock/bcm21664.h deleted file mode 100644 index 5a7f0e4750a..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/bcm21664.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - * Copyright (C) 2013 Broadcom Corporation - * Copyright 2013 Linaro Limited - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _CLOCK_BCM21664_H -#define _CLOCK_BCM21664_H - -/* - * This file defines the values used to specify clocks provided by - * the clock control units (CCUs) on Broadcom BCM21664 family SoCs. - */ - -/* bcm21664 CCU device tree "compatible" strings */ -#define BCM21664_DT_ROOT_CCU_COMPAT "brcm,bcm21664-root-ccu" -#define BCM21664_DT_AON_CCU_COMPAT "brcm,bcm21664-aon-ccu" -#define BCM21664_DT_MASTER_CCU_COMPAT "brcm,bcm21664-master-ccu" -#define BCM21664_DT_SLAVE_CCU_COMPAT "brcm,bcm21664-slave-ccu" - -/* root CCU clock ids */ - -#define BCM21664_ROOT_CCU_FRAC_1M 0 -#define BCM21664_ROOT_CCU_CLOCK_COUNT 1 - -/* aon CCU clock ids */ - -#define BCM21664_AON_CCU_HUB_TIMER 0 -#define BCM21664_AON_CCU_CLOCK_COUNT 1 - -/* master CCU clock ids */ - -#define BCM21664_MASTER_CCU_SDIO1 0 -#define BCM21664_MASTER_CCU_SDIO2 1 -#define BCM21664_MASTER_CCU_SDIO3 2 -#define BCM21664_MASTER_CCU_SDIO4 3 -#define BCM21664_MASTER_CCU_SDIO1_SLEEP 4 -#define BCM21664_MASTER_CCU_SDIO2_SLEEP 5 -#define BCM21664_MASTER_CCU_SDIO3_SLEEP 6 -#define BCM21664_MASTER_CCU_SDIO4_SLEEP 7 -#define BCM21664_MASTER_CCU_CLOCK_COUNT 8 - -/* slave CCU clock ids */ - -#define BCM21664_SLAVE_CCU_UARTB 0 -#define BCM21664_SLAVE_CCU_UARTB2 1 -#define BCM21664_SLAVE_CCU_UARTB3 2 -#define BCM21664_SLAVE_CCU_BSC1 3 -#define BCM21664_SLAVE_CCU_BSC2 4 -#define BCM21664_SLAVE_CCU_BSC3 5 -#define BCM21664_SLAVE_CCU_BSC4 6 -#define BCM21664_SLAVE_CCU_CLOCK_COUNT 7 - -#endif /* _CLOCK_BCM21664_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/bcm281xx.h b/sys/gnu/dts/include/dt-bindings/clock/bcm281xx.h deleted file mode 100644 index a763460cf1a..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/bcm281xx.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Copyright (C) 2013 Broadcom Corporation - * Copyright 2013 Linaro Limited - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _CLOCK_BCM281XX_H -#define _CLOCK_BCM281XX_H - -/* - * This file defines the values used to specify clocks provided by - * the clock control units (CCUs) on Broadcom BCM281XX family SoCs. - */ - -/* - * These are the bcm281xx CCU device tree "compatible" strings. - * We're stuck with using "bcm11351" in the string because wild - * cards aren't allowed, and that name was the first one defined - * in this family of devices. - */ -#define BCM281XX_DT_ROOT_CCU_COMPAT "brcm,bcm11351-root-ccu" -#define BCM281XX_DT_AON_CCU_COMPAT "brcm,bcm11351-aon-ccu" -#define BCM281XX_DT_HUB_CCU_COMPAT "brcm,bcm11351-hub-ccu" -#define BCM281XX_DT_MASTER_CCU_COMPAT "brcm,bcm11351-master-ccu" -#define BCM281XX_DT_SLAVE_CCU_COMPAT "brcm,bcm11351-slave-ccu" - -/* root CCU clock ids */ - -#define BCM281XX_ROOT_CCU_FRAC_1M 0 -#define BCM281XX_ROOT_CCU_CLOCK_COUNT 1 - -/* aon CCU clock ids */ - -#define BCM281XX_AON_CCU_HUB_TIMER 0 -#define BCM281XX_AON_CCU_PMU_BSC 1 -#define BCM281XX_AON_CCU_PMU_BSC_VAR 2 -#define BCM281XX_AON_CCU_CLOCK_COUNT 3 - -/* hub CCU clock ids */ - -#define BCM281XX_HUB_CCU_TMON_1M 0 -#define BCM281XX_HUB_CCU_CLOCK_COUNT 1 - -/* master CCU clock ids */ - -#define BCM281XX_MASTER_CCU_SDIO1 0 -#define BCM281XX_MASTER_CCU_SDIO2 1 -#define BCM281XX_MASTER_CCU_SDIO3 2 -#define BCM281XX_MASTER_CCU_SDIO4 3 -#define BCM281XX_MASTER_CCU_USB_IC 4 -#define BCM281XX_MASTER_CCU_HSIC2_48M 5 -#define BCM281XX_MASTER_CCU_HSIC2_12M 6 -#define BCM281XX_MASTER_CCU_CLOCK_COUNT 7 - -/* slave CCU clock ids */ - -#define BCM281XX_SLAVE_CCU_UARTB 0 -#define BCM281XX_SLAVE_CCU_UARTB2 1 -#define BCM281XX_SLAVE_CCU_UARTB3 2 -#define BCM281XX_SLAVE_CCU_UARTB4 3 -#define BCM281XX_SLAVE_CCU_SSP0 4 -#define BCM281XX_SLAVE_CCU_SSP2 5 -#define BCM281XX_SLAVE_CCU_BSC1 6 -#define BCM281XX_SLAVE_CCU_BSC2 7 -#define BCM281XX_SLAVE_CCU_BSC3 8 -#define BCM281XX_SLAVE_CCU_PWM 9 -#define BCM281XX_SLAVE_CCU_CLOCK_COUNT 10 - -#endif /* _CLOCK_BCM281XX_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/bcm2835-aux.h b/sys/gnu/dts/include/dt-bindings/clock/bcm2835-aux.h deleted file mode 100644 index bb79de383a3..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/bcm2835-aux.h +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2015 Broadcom Corporation - */ - -#define BCM2835_AUX_CLOCK_UART 0 -#define BCM2835_AUX_CLOCK_SPI1 1 -#define BCM2835_AUX_CLOCK_SPI2 2 -#define BCM2835_AUX_CLOCK_COUNT 3 diff --git a/sys/gnu/dts/include/dt-bindings/clock/bcm2835.h b/sys/gnu/dts/include/dt-bindings/clock/bcm2835.h deleted file mode 100644 index b60c03430cf..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/bcm2835.h +++ /dev/null @@ -1,62 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2015 Broadcom Corporation - */ - -#define BCM2835_PLLA 0 -#define BCM2835_PLLB 1 -#define BCM2835_PLLC 2 -#define BCM2835_PLLD 3 -#define BCM2835_PLLH 4 - -#define BCM2835_PLLA_CORE 5 -#define BCM2835_PLLA_PER 6 -#define BCM2835_PLLB_ARM 7 -#define BCM2835_PLLC_CORE0 8 -#define BCM2835_PLLC_CORE1 9 -#define BCM2835_PLLC_CORE2 10 -#define BCM2835_PLLC_PER 11 -#define BCM2835_PLLD_CORE 12 -#define BCM2835_PLLD_PER 13 -#define BCM2835_PLLH_RCAL 14 -#define BCM2835_PLLH_AUX 15 -#define BCM2835_PLLH_PIX 16 - -#define BCM2835_CLOCK_TIMER 17 -#define BCM2835_CLOCK_OTP 18 -#define BCM2835_CLOCK_UART 19 -#define BCM2835_CLOCK_VPU 20 -#define BCM2835_CLOCK_V3D 21 -#define BCM2835_CLOCK_ISP 22 -#define BCM2835_CLOCK_H264 23 -#define BCM2835_CLOCK_VEC 24 -#define BCM2835_CLOCK_HSM 25 -#define BCM2835_CLOCK_SDRAM 26 -#define BCM2835_CLOCK_TSENS 27 -#define BCM2835_CLOCK_EMMC 28 -#define BCM2835_CLOCK_PERI_IMAGE 29 -#define BCM2835_CLOCK_PWM 30 -#define BCM2835_CLOCK_PCM 31 - -#define BCM2835_PLLA_DSI0 32 -#define BCM2835_PLLA_CCP2 33 -#define BCM2835_PLLD_DSI0 34 -#define BCM2835_PLLD_DSI1 35 - -#define BCM2835_CLOCK_AVEO 36 -#define BCM2835_CLOCK_DFT 37 -#define BCM2835_CLOCK_GP0 38 -#define BCM2835_CLOCK_GP1 39 -#define BCM2835_CLOCK_GP2 40 -#define BCM2835_CLOCK_SLIM 41 -#define BCM2835_CLOCK_SMI 42 -#define BCM2835_CLOCK_TEC 43 -#define BCM2835_CLOCK_DPI 44 -#define BCM2835_CLOCK_CAM0 45 -#define BCM2835_CLOCK_CAM1 46 -#define BCM2835_CLOCK_DSI0E 47 -#define BCM2835_CLOCK_DSI1E 48 -#define BCM2835_CLOCK_DSI0P 49 -#define BCM2835_CLOCK_DSI1P 50 - -#define BCM2711_CLOCK_EMMC2 51 diff --git a/sys/gnu/dts/include/dt-bindings/clock/berlin2.h b/sys/gnu/dts/include/dt-bindings/clock/berlin2.h deleted file mode 100644 index b07b8efab07..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/berlin2.h +++ /dev/null @@ -1,46 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Berlin2 BG2/BG2CD clock tree IDs - */ - -#define CLKID_SYS 0 -#define CLKID_CPU 1 -#define CLKID_DRMFIGO 2 -#define CLKID_CFG 3 -#define CLKID_GFX 4 -#define CLKID_ZSP 5 -#define CLKID_PERIF 6 -#define CLKID_PCUBE 7 -#define CLKID_VSCOPE 8 -#define CLKID_NFC_ECC 9 -#define CLKID_VPP 10 -#define CLKID_APP 11 -#define CLKID_AUDIO0 12 -#define CLKID_AUDIO2 13 -#define CLKID_AUDIO3 14 -#define CLKID_AUDIO1 15 -#define CLKID_GFX3D_CORE 16 -#define CLKID_GFX3D_SYS 17 -#define CLKID_ARC 18 -#define CLKID_VIP 19 -#define CLKID_SDIO0XIN 20 -#define CLKID_SDIO1XIN 21 -#define CLKID_GFX3D_EXTRA 22 -#define CLKID_GC360 23 -#define CLKID_SDIO_DLLMST 24 -#define CLKID_GETH0 25 -#define CLKID_GETH1 26 -#define CLKID_SATA 27 -#define CLKID_AHBAPB 28 -#define CLKID_USB0 29 -#define CLKID_USB1 30 -#define CLKID_PBRIDGE 31 -#define CLKID_SDIO0 32 -#define CLKID_SDIO1 33 -#define CLKID_NFC 34 -#define CLKID_SMEMC 35 -#define CLKID_AUDIOHD 36 -#define CLKID_VIDEO0 37 -#define CLKID_VIDEO1 38 -#define CLKID_VIDEO2 39 -#define CLKID_TWD 40 diff --git a/sys/gnu/dts/include/dt-bindings/clock/berlin2q.h b/sys/gnu/dts/include/dt-bindings/clock/berlin2q.h deleted file mode 100644 index 44b4ac38285..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/berlin2q.h +++ /dev/null @@ -1,33 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Berlin2 BG2Q clock tree IDs - */ - -#define CLKID_SYS 0 -#define CLKID_DRMFIGO 1 -#define CLKID_CFG 2 -#define CLKID_GFX2D 3 -#define CLKID_ZSP 4 -#define CLKID_PERIF 5 -#define CLKID_PCUBE 6 -#define CLKID_VSCOPE 7 -#define CLKID_NFC_ECC 8 -#define CLKID_VPP 9 -#define CLKID_APP 10 -#define CLKID_SDIO0XIN 11 -#define CLKID_SDIO1XIN 12 -#define CLKID_GFX2DAXI 13 -#define CLKID_GETH0 14 -#define CLKID_SATA 15 -#define CLKID_AHBAPB 16 -#define CLKID_USB0 17 -#define CLKID_USB1 18 -#define CLKID_USB2 19 -#define CLKID_USB3 20 -#define CLKID_PBRIDGE 21 -#define CLKID_SDIO 22 -#define CLKID_NFC 23 -#define CLKID_SMEMC 24 -#define CLKID_PCIE 25 -#define CLKID_TWD 26 -#define CLKID_CPU 27 diff --git a/sys/gnu/dts/include/dt-bindings/clock/bm1880-clock.h b/sys/gnu/dts/include/dt-bindings/clock/bm1880-clock.h deleted file mode 100644 index b46732361b2..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/bm1880-clock.h +++ /dev/null @@ -1,82 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Device Tree binding constants for Bitmain BM1880 SoC - * - * Copyright (c) 2019 Linaro Ltd. - */ - -#ifndef __DT_BINDINGS_CLOCK_BM1880_H -#define __DT_BINDINGS_CLOCK_BM1880_H - -#define BM1880_CLK_OSC 0 -#define BM1880_CLK_MPLL 1 -#define BM1880_CLK_SPLL 2 -#define BM1880_CLK_FPLL 3 -#define BM1880_CLK_DDRPLL 4 -#define BM1880_CLK_A53 5 -#define BM1880_CLK_50M_A53 6 -#define BM1880_CLK_AHB_ROM 7 -#define BM1880_CLK_AXI_SRAM 8 -#define BM1880_CLK_DDR_AXI 9 -#define BM1880_CLK_EFUSE 10 -#define BM1880_CLK_APB_EFUSE 11 -#define BM1880_CLK_AXI5_EMMC 12 -#define BM1880_CLK_EMMC 13 -#define BM1880_CLK_100K_EMMC 14 -#define BM1880_CLK_AXI5_SD 15 -#define BM1880_CLK_SD 16 -#define BM1880_CLK_100K_SD 17 -#define BM1880_CLK_500M_ETH0 18 -#define BM1880_CLK_AXI4_ETH0 19 -#define BM1880_CLK_500M_ETH1 20 -#define BM1880_CLK_AXI4_ETH1 21 -#define BM1880_CLK_AXI1_GDMA 22 -#define BM1880_CLK_APB_GPIO 23 -#define BM1880_CLK_APB_GPIO_INTR 24 -#define BM1880_CLK_GPIO_DB 25 -#define BM1880_CLK_AXI1_MINER 26 -#define BM1880_CLK_AHB_SF 27 -#define BM1880_CLK_SDMA_AXI 28 -#define BM1880_CLK_SDMA_AUD 29 -#define BM1880_CLK_APB_I2C 30 -#define BM1880_CLK_APB_WDT 31 -#define BM1880_CLK_APB_JPEG 32 -#define BM1880_CLK_JPEG_AXI 33 -#define BM1880_CLK_AXI5_NF 34 -#define BM1880_CLK_APB_NF 35 -#define BM1880_CLK_NF 36 -#define BM1880_CLK_APB_PWM 37 -#define BM1880_CLK_DIV_0_RV 38 -#define BM1880_CLK_DIV_1_RV 39 -#define BM1880_CLK_MUX_RV 40 -#define BM1880_CLK_RV 41 -#define BM1880_CLK_APB_SPI 42 -#define BM1880_CLK_TPU_AXI 43 -#define BM1880_CLK_DIV_UART_500M 44 -#define BM1880_CLK_UART_500M 45 -#define BM1880_CLK_APB_UART 46 -#define BM1880_CLK_APB_I2S 47 -#define BM1880_CLK_AXI4_USB 48 -#define BM1880_CLK_APB_USB 49 -#define BM1880_CLK_125M_USB 50 -#define BM1880_CLK_33K_USB 51 -#define BM1880_CLK_DIV_12M_USB 52 -#define BM1880_CLK_12M_USB 53 -#define BM1880_CLK_APB_VIDEO 54 -#define BM1880_CLK_VIDEO_AXI 55 -#define BM1880_CLK_VPP_AXI 56 -#define BM1880_CLK_APB_VPP 57 -#define BM1880_CLK_DIV_0_AXI1 58 -#define BM1880_CLK_DIV_1_AXI1 59 -#define BM1880_CLK_AXI1 60 -#define BM1880_CLK_AXI2 61 -#define BM1880_CLK_AXI3 62 -#define BM1880_CLK_AXI4 63 -#define BM1880_CLK_AXI5 64 -#define BM1880_CLK_DIV_0_AXI6 65 -#define BM1880_CLK_DIV_1_AXI6 66 -#define BM1880_CLK_MUX_AXI6 67 -#define BM1880_CLK_AXI6 68 -#define BM1880_NR_CLKS 69 - -#endif /* __DT_BINDINGS_CLOCK_BM1880_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/boston-clock.h b/sys/gnu/dts/include/dt-bindings/clock/boston-clock.h deleted file mode 100644 index a6f00982113..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/boston-clock.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * Copyright (C) 2016 Imagination Technologies - * - * SPDX-License-Identifier: GPL-2.0 - */ - -#ifndef __DT_BINDINGS_CLOCK_BOSTON_CLOCK_H__ -#define __DT_BINDINGS_CLOCK_BOSTON_CLOCK_H__ - -#define BOSTON_CLK_INPUT 0 -#define BOSTON_CLK_SYS 1 -#define BOSTON_CLK_CPU 2 - -#endif /* __DT_BINDINGS_CLOCK_BOSTON_CLOCK_H__ */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/clps711x-clock.h b/sys/gnu/dts/include/dt-bindings/clock/clps711x-clock.h deleted file mode 100644 index 55b403d8b4c..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/clps711x-clock.h +++ /dev/null @@ -1,23 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) 2014 Alexander Shiyan - */ - -#ifndef __DT_BINDINGS_CLOCK_CLPS711X_H -#define __DT_BINDINGS_CLOCK_CLPS711X_H - -#define CLPS711X_CLK_DUMMY 0 -#define CLPS711X_CLK_CPU 1 -#define CLPS711X_CLK_BUS 2 -#define CLPS711X_CLK_PLL 3 -#define CLPS711X_CLK_TIMERREF 4 -#define CLPS711X_CLK_TIMER1 5 -#define CLPS711X_CLK_TIMER2 6 -#define CLPS711X_CLK_PWM 7 -#define CLPS711X_CLK_SPIREF 8 -#define CLPS711X_CLK_SPI 9 -#define CLPS711X_CLK_UART 10 -#define CLPS711X_CLK_TICK 11 -#define CLPS711X_CLK_MAX 12 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/cortina,gemini-clock.h b/sys/gnu/dts/include/dt-bindings/clock/cortina,gemini-clock.h deleted file mode 100644 index 04c3404b2d3..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/cortina,gemini-clock.h +++ /dev/null @@ -1,30 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef DT_BINDINGS_CORTINA_GEMINI_CLOCK_H -#define DT_BINDINGS_CORTINA_GEMINI_CLOCK_H - -/* RTC, AHB, APB, CPU, PCI, TVC, UART clocks and 13 gates */ -#define GEMINI_NUM_CLKS 20 - -#define GEMINI_CLK_RTC 0 -#define GEMINI_CLK_AHB 1 -#define GEMINI_CLK_APB 2 -#define GEMINI_CLK_CPU 3 -#define GEMINI_CLK_PCI 4 -#define GEMINI_CLK_TVC 5 -#define GEMINI_CLK_UART 6 -#define GEMINI_CLK_GATES 7 -#define GEMINI_CLK_GATE_SECURITY 7 -#define GEMINI_CLK_GATE_GMAC0 8 -#define GEMINI_CLK_GATE_GMAC1 9 -#define GEMINI_CLK_GATE_SATA0 10 -#define GEMINI_CLK_GATE_SATA1 11 -#define GEMINI_CLK_GATE_USB0 12 -#define GEMINI_CLK_GATE_USB1 13 -#define GEMINI_CLK_GATE_IDE 14 -#define GEMINI_CLK_GATE_PCI 15 -#define GEMINI_CLK_GATE_DDR 16 -#define GEMINI_CLK_GATE_FLASH 17 -#define GEMINI_CLK_GATE_TVC 18 -#define GEMINI_CLK_GATE_BOOT 19 - -#endif /* DT_BINDINGS_CORTINA_GEMINI_CLOCK_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/dm814.h b/sys/gnu/dts/include/dt-bindings/clock/dm814.h deleted file mode 100644 index f0f04e0a249..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/dm814.h +++ /dev/null @@ -1,37 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2017 Texas Instruments, Inc. - */ -#ifndef __DT_BINDINGS_CLK_DM814_H -#define __DT_BINDINGS_CLK_DM814_H - -#define DM814_CLKCTRL_OFFSET 0x0 -#define DM814_CLKCTRL_INDEX(offset) ((offset) - DM814_CLKCTRL_OFFSET) - -/* default clocks */ -#define DM814_USB_OTG_HS_CLKCTRL DM814_CLKCTRL_INDEX(0x58) - -/* alwon clocks */ -#define DM814_UART1_CLKCTRL DM814_CLKCTRL_INDEX(0x150) -#define DM814_UART2_CLKCTRL DM814_CLKCTRL_INDEX(0x154) -#define DM814_UART3_CLKCTRL DM814_CLKCTRL_INDEX(0x158) -#define DM814_GPIO1_CLKCTRL DM814_CLKCTRL_INDEX(0x15c) -#define DM814_GPIO2_CLKCTRL DM814_CLKCTRL_INDEX(0x160) -#define DM814_I2C1_CLKCTRL DM814_CLKCTRL_INDEX(0x164) -#define DM814_I2C2_CLKCTRL DM814_CLKCTRL_INDEX(0x168) -#define DM814_WD_TIMER_CLKCTRL DM814_CLKCTRL_INDEX(0x18c) -#define DM814_MCSPI1_CLKCTRL DM814_CLKCTRL_INDEX(0x190) -#define DM814_GPMC_CLKCTRL DM814_CLKCTRL_INDEX(0x1d0) -#define DM814_CPGMAC0_CLKCTRL DM814_CLKCTRL_INDEX(0x1d4) -#define DM814_MPU_CLKCTRL DM814_CLKCTRL_INDEX(0x1dc) -#define DM814_RTC_CLKCTRL DM814_CLKCTRL_INDEX(0x1f0) -#define DM814_TPCC_CLKCTRL DM814_CLKCTRL_INDEX(0x1f4) -#define DM814_TPTC0_CLKCTRL DM814_CLKCTRL_INDEX(0x1f8) -#define DM814_TPTC1_CLKCTRL DM814_CLKCTRL_INDEX(0x1fc) -#define DM814_TPTC2_CLKCTRL DM814_CLKCTRL_INDEX(0x200) -#define DM814_TPTC3_CLKCTRL DM814_CLKCTRL_INDEX(0x204) -#define DM814_MMC1_CLKCTRL DM814_CLKCTRL_INDEX(0x21c) -#define DM814_MMC2_CLKCTRL DM814_CLKCTRL_INDEX(0x220) -#define DM814_MMC3_CLKCTRL DM814_CLKCTRL_INDEX(0x224) - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/dm816.h b/sys/gnu/dts/include/dt-bindings/clock/dm816.h deleted file mode 100644 index fb0d94174d2..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/dm816.h +++ /dev/null @@ -1,45 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2017 Texas Instruments, Inc. - */ -#ifndef __DT_BINDINGS_CLK_DM816_H -#define __DT_BINDINGS_CLK_DM816_H - -#define DM816_CLKCTRL_OFFSET 0x0 -#define DM816_CLKCTRL_INDEX(offset) ((offset) - DM816_CLKCTRL_OFFSET) - -/* default clocks */ -#define DM816_USB_OTG_HS_CLKCTRL DM816_CLKCTRL_INDEX(0x58) - -/* alwon clocks */ -#define DM816_UART1_CLKCTRL DM816_CLKCTRL_INDEX(0x150) -#define DM816_UART2_CLKCTRL DM816_CLKCTRL_INDEX(0x154) -#define DM816_UART3_CLKCTRL DM816_CLKCTRL_INDEX(0x158) -#define DM816_GPIO1_CLKCTRL DM816_CLKCTRL_INDEX(0x15c) -#define DM816_GPIO2_CLKCTRL DM816_CLKCTRL_INDEX(0x160) -#define DM816_I2C1_CLKCTRL DM816_CLKCTRL_INDEX(0x164) -#define DM816_I2C2_CLKCTRL DM816_CLKCTRL_INDEX(0x168) -#define DM816_TIMER1_CLKCTRL DM816_CLKCTRL_INDEX(0x170) -#define DM816_TIMER2_CLKCTRL DM816_CLKCTRL_INDEX(0x174) -#define DM816_TIMER3_CLKCTRL DM816_CLKCTRL_INDEX(0x178) -#define DM816_TIMER4_CLKCTRL DM816_CLKCTRL_INDEX(0x17c) -#define DM816_TIMER5_CLKCTRL DM816_CLKCTRL_INDEX(0x180) -#define DM816_TIMER6_CLKCTRL DM816_CLKCTRL_INDEX(0x184) -#define DM816_TIMER7_CLKCTRL DM816_CLKCTRL_INDEX(0x188) -#define DM816_WD_TIMER_CLKCTRL DM816_CLKCTRL_INDEX(0x18c) -#define DM816_MCSPI1_CLKCTRL DM816_CLKCTRL_INDEX(0x190) -#define DM816_MAILBOX_CLKCTRL DM816_CLKCTRL_INDEX(0x194) -#define DM816_SPINBOX_CLKCTRL DM816_CLKCTRL_INDEX(0x198) -#define DM816_MMC1_CLKCTRL DM816_CLKCTRL_INDEX(0x1b0) -#define DM816_GPMC_CLKCTRL DM816_CLKCTRL_INDEX(0x1d0) -#define DM816_DAVINCI_MDIO_CLKCTRL DM816_CLKCTRL_INDEX(0x1d4) -#define DM816_EMAC1_CLKCTRL DM816_CLKCTRL_INDEX(0x1d8) -#define DM816_MPU_CLKCTRL DM816_CLKCTRL_INDEX(0x1dc) -#define DM816_RTC_CLKCTRL DM816_CLKCTRL_INDEX(0x1f0) -#define DM816_TPCC_CLKCTRL DM816_CLKCTRL_INDEX(0x1f4) -#define DM816_TPTC0_CLKCTRL DM816_CLKCTRL_INDEX(0x1f8) -#define DM816_TPTC1_CLKCTRL DM816_CLKCTRL_INDEX(0x1fc) -#define DM816_TPTC2_CLKCTRL DM816_CLKCTRL_INDEX(0x200) -#define DM816_TPTC3_CLKCTRL DM816_CLKCTRL_INDEX(0x204) - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/dra7.h b/sys/gnu/dts/include/dt-bindings/clock/dra7.h deleted file mode 100644 index 72f2e841152..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/dra7.h +++ /dev/null @@ -1,355 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2017 Texas Instruments, Inc. - */ -#ifndef __DT_BINDINGS_CLK_DRA7_H -#define __DT_BINDINGS_CLK_DRA7_H - -#define DRA7_CLKCTRL_OFFSET 0x20 -#define DRA7_CLKCTRL_INDEX(offset) ((offset) - DRA7_CLKCTRL_OFFSET) - -/* XXX: Compatibility part begin, remove this once compatibility support is no longer needed */ - -/* mpu clocks */ -#define DRA7_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) - -/* ipu clocks */ -#define _DRA7_IPU_CLKCTRL_OFFSET 0x40 -#define _DRA7_IPU_CLKCTRL_INDEX(offset) ((offset) - _DRA7_IPU_CLKCTRL_OFFSET) -#define DRA7_MCASP1_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x50) -#define DRA7_TIMER5_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x58) -#define DRA7_TIMER6_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x60) -#define DRA7_TIMER7_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x68) -#define DRA7_TIMER8_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x70) -#define DRA7_I2C5_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x78) -#define DRA7_UART6_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x80) - -/* rtc clocks */ -#define DRA7_RTC_CLKCTRL_OFFSET 0x40 -#define DRA7_RTC_CLKCTRL_INDEX(offset) ((offset) - DRA7_RTC_CLKCTRL_OFFSET) -#define DRA7_RTCSS_CLKCTRL DRA7_RTC_CLKCTRL_INDEX(0x44) - -/* coreaon clocks */ -#define DRA7_SMARTREFLEX_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) -#define DRA7_SMARTREFLEX_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x38) - -/* l3main1 clocks */ -#define DRA7_L3_MAIN_1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) -#define DRA7_GPMC_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) -#define DRA7_TPCC_CLKCTRL DRA7_CLKCTRL_INDEX(0x70) -#define DRA7_TPTC0_CLKCTRL DRA7_CLKCTRL_INDEX(0x78) -#define DRA7_TPTC1_CLKCTRL DRA7_CLKCTRL_INDEX(0x80) -#define DRA7_VCP1_CLKCTRL DRA7_CLKCTRL_INDEX(0x88) -#define DRA7_VCP2_CLKCTRL DRA7_CLKCTRL_INDEX(0x90) - -/* dma clocks */ -#define DRA7_DMA_SYSTEM_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) - -/* emif clocks */ -#define DRA7_DMM_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) - -/* atl clocks */ -#define DRA7_ATL_CLKCTRL_OFFSET 0x0 -#define DRA7_ATL_CLKCTRL_INDEX(offset) ((offset) - DRA7_ATL_CLKCTRL_OFFSET) -#define DRA7_ATL_CLKCTRL DRA7_ATL_CLKCTRL_INDEX(0x0) - -/* l4cfg clocks */ -#define DRA7_L4_CFG_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) -#define DRA7_SPINLOCK_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) -#define DRA7_MAILBOX1_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) -#define DRA7_MAILBOX2_CLKCTRL DRA7_CLKCTRL_INDEX(0x48) -#define DRA7_MAILBOX3_CLKCTRL DRA7_CLKCTRL_INDEX(0x50) -#define DRA7_MAILBOX4_CLKCTRL DRA7_CLKCTRL_INDEX(0x58) -#define DRA7_MAILBOX5_CLKCTRL DRA7_CLKCTRL_INDEX(0x60) -#define DRA7_MAILBOX6_CLKCTRL DRA7_CLKCTRL_INDEX(0x68) -#define DRA7_MAILBOX7_CLKCTRL DRA7_CLKCTRL_INDEX(0x70) -#define DRA7_MAILBOX8_CLKCTRL DRA7_CLKCTRL_INDEX(0x78) -#define DRA7_MAILBOX9_CLKCTRL DRA7_CLKCTRL_INDEX(0x80) -#define DRA7_MAILBOX10_CLKCTRL DRA7_CLKCTRL_INDEX(0x88) -#define DRA7_MAILBOX11_CLKCTRL DRA7_CLKCTRL_INDEX(0x90) -#define DRA7_MAILBOX12_CLKCTRL DRA7_CLKCTRL_INDEX(0x98) -#define DRA7_MAILBOX13_CLKCTRL DRA7_CLKCTRL_INDEX(0xa0) - -/* l3instr clocks */ -#define DRA7_L3_MAIN_2_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) -#define DRA7_L3_INSTR_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) - -/* dss clocks */ -#define DRA7_DSS_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) -#define DRA7_BB2D_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) - -/* l3init clocks */ -#define DRA7_MMC1_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) -#define DRA7_MMC2_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) -#define DRA7_USB_OTG_SS2_CLKCTRL DRA7_CLKCTRL_INDEX(0x40) -#define DRA7_USB_OTG_SS3_CLKCTRL DRA7_CLKCTRL_INDEX(0x48) -#define DRA7_USB_OTG_SS4_CLKCTRL DRA7_CLKCTRL_INDEX(0x50) -#define DRA7_SATA_CLKCTRL DRA7_CLKCTRL_INDEX(0x88) -#define DRA7_PCIE1_CLKCTRL DRA7_CLKCTRL_INDEX(0xb0) -#define DRA7_PCIE2_CLKCTRL DRA7_CLKCTRL_INDEX(0xb8) -#define DRA7_GMAC_CLKCTRL DRA7_CLKCTRL_INDEX(0xd0) -#define DRA7_OCP2SCP1_CLKCTRL DRA7_CLKCTRL_INDEX(0xe0) -#define DRA7_OCP2SCP3_CLKCTRL DRA7_CLKCTRL_INDEX(0xe8) -#define DRA7_USB_OTG_SS1_CLKCTRL DRA7_CLKCTRL_INDEX(0xf0) - -/* l4per clocks */ -#define _DRA7_L4PER_CLKCTRL_OFFSET 0x0 -#define _DRA7_L4PER_CLKCTRL_INDEX(offset) ((offset) - _DRA7_L4PER_CLKCTRL_OFFSET) -#define DRA7_L4_PER2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xc) -#define DRA7_L4_PER3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x14) -#define DRA7_TIMER10_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x28) -#define DRA7_TIMER11_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x30) -#define DRA7_TIMER2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x38) -#define DRA7_TIMER3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x40) -#define DRA7_TIMER4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x48) -#define DRA7_TIMER9_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x50) -#define DRA7_ELM_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x58) -#define DRA7_GPIO2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x60) -#define DRA7_GPIO3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x68) -#define DRA7_GPIO4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x70) -#define DRA7_GPIO5_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x78) -#define DRA7_GPIO6_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x80) -#define DRA7_HDQ1W_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x88) -#define DRA7_EPWMSS1_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x90) -#define DRA7_EPWMSS2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x98) -#define DRA7_I2C1_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xa0) -#define DRA7_I2C2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xa8) -#define DRA7_I2C3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xb0) -#define DRA7_I2C4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xb8) -#define DRA7_L4_PER1_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xc0) -#define DRA7_EPWMSS0_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xc4) -#define DRA7_TIMER13_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xc8) -#define DRA7_TIMER14_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xd0) -#define DRA7_TIMER15_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xd8) -#define DRA7_MCSPI1_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xf0) -#define DRA7_MCSPI2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xf8) -#define DRA7_MCSPI3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x100) -#define DRA7_MCSPI4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x108) -#define DRA7_GPIO7_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x110) -#define DRA7_GPIO8_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x118) -#define DRA7_MMC3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x120) -#define DRA7_MMC4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x128) -#define DRA7_TIMER16_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x130) -#define DRA7_QSPI_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x138) -#define DRA7_UART1_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x140) -#define DRA7_UART2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x148) -#define DRA7_UART3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x150) -#define DRA7_UART4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x158) -#define DRA7_MCASP2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x160) -#define DRA7_MCASP3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x168) -#define DRA7_UART5_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x170) -#define DRA7_MCASP5_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x178) -#define DRA7_MCASP8_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x190) -#define DRA7_MCASP4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x198) -#define DRA7_AES1_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1a0) -#define DRA7_AES2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1a8) -#define DRA7_DES_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1b0) -#define DRA7_RNG_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1c0) -#define DRA7_SHAM_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1c8) -#define DRA7_UART7_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1d0) -#define DRA7_UART8_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1e0) -#define DRA7_UART9_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1e8) -#define DRA7_DCAN2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1f0) -#define DRA7_MCASP6_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x204) -#define DRA7_MCASP7_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x208) - -/* wkupaon clocks */ -#define DRA7_L4_WKUP_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) -#define DRA7_WD_TIMER2_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) -#define DRA7_GPIO1_CLKCTRL DRA7_CLKCTRL_INDEX(0x38) -#define DRA7_TIMER1_CLKCTRL DRA7_CLKCTRL_INDEX(0x40) -#define DRA7_TIMER12_CLKCTRL DRA7_CLKCTRL_INDEX(0x48) -#define DRA7_COUNTER_32K_CLKCTRL DRA7_CLKCTRL_INDEX(0x50) -#define DRA7_UART10_CLKCTRL DRA7_CLKCTRL_INDEX(0x80) -#define DRA7_DCAN1_CLKCTRL DRA7_CLKCTRL_INDEX(0x88) -#define DRA7_ADC_CLKCTRL DRA7_CLKCTRL_INDEX(0xa0) - -/* XXX: Compatibility part end. */ - -/* mpu clocks */ -#define DRA7_MPU_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) - -/* dsp1 clocks */ -#define DRA7_DSP1_MMU0_DSP1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) - -/* ipu1 clocks */ -#define DRA7_IPU1_MMU_IPU1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) - -/* ipu clocks */ -#define DRA7_IPU_CLKCTRL_OFFSET 0x50 -#define DRA7_IPU_CLKCTRL_INDEX(offset) ((offset) - DRA7_IPU_CLKCTRL_OFFSET) -#define DRA7_IPU_MCASP1_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x50) -#define DRA7_IPU_TIMER5_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x58) -#define DRA7_IPU_TIMER6_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x60) -#define DRA7_IPU_TIMER7_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x68) -#define DRA7_IPU_TIMER8_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x70) -#define DRA7_IPU_I2C5_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x78) -#define DRA7_IPU_UART6_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x80) - -/* dsp2 clocks */ -#define DRA7_DSP2_MMU0_DSP2_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) - -/* rtc clocks */ -#define DRA7_RTC_RTCSS_CLKCTRL DRA7_CLKCTRL_INDEX(0x44) - -/* coreaon clocks */ -#define DRA7_COREAON_SMARTREFLEX_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) -#define DRA7_COREAON_SMARTREFLEX_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x38) - -/* l3main1 clocks */ -#define DRA7_L3MAIN1_L3_MAIN_1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) -#define DRA7_L3MAIN1_GPMC_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) -#define DRA7_L3MAIN1_TPCC_CLKCTRL DRA7_CLKCTRL_INDEX(0x70) -#define DRA7_L3MAIN1_TPTC0_CLKCTRL DRA7_CLKCTRL_INDEX(0x78) -#define DRA7_L3MAIN1_TPTC1_CLKCTRL DRA7_CLKCTRL_INDEX(0x80) -#define DRA7_L3MAIN1_VCP1_CLKCTRL DRA7_CLKCTRL_INDEX(0x88) -#define DRA7_L3MAIN1_VCP2_CLKCTRL DRA7_CLKCTRL_INDEX(0x90) - -/* ipu2 clocks */ -#define DRA7_IPU2_MMU_IPU2_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) - -/* dma clocks */ -#define DRA7_DMA_DMA_SYSTEM_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) - -/* emif clocks */ -#define DRA7_EMIF_DMM_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) - -/* atl clocks */ -#define DRA7_ATL_CLKCTRL_OFFSET 0x0 -#define DRA7_ATL_CLKCTRL_INDEX(offset) ((offset) - DRA7_ATL_CLKCTRL_OFFSET) -#define DRA7_ATL_ATL_CLKCTRL DRA7_ATL_CLKCTRL_INDEX(0x0) - -/* l4cfg clocks */ -#define DRA7_L4CFG_L4_CFG_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) -#define DRA7_L4CFG_SPINLOCK_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) -#define DRA7_L4CFG_MAILBOX1_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) -#define DRA7_L4CFG_MAILBOX2_CLKCTRL DRA7_CLKCTRL_INDEX(0x48) -#define DRA7_L4CFG_MAILBOX3_CLKCTRL DRA7_CLKCTRL_INDEX(0x50) -#define DRA7_L4CFG_MAILBOX4_CLKCTRL DRA7_CLKCTRL_INDEX(0x58) -#define DRA7_L4CFG_MAILBOX5_CLKCTRL DRA7_CLKCTRL_INDEX(0x60) -#define DRA7_L4CFG_MAILBOX6_CLKCTRL DRA7_CLKCTRL_INDEX(0x68) -#define DRA7_L4CFG_MAILBOX7_CLKCTRL DRA7_CLKCTRL_INDEX(0x70) -#define DRA7_L4CFG_MAILBOX8_CLKCTRL DRA7_CLKCTRL_INDEX(0x78) -#define DRA7_L4CFG_MAILBOX9_CLKCTRL DRA7_CLKCTRL_INDEX(0x80) -#define DRA7_L4CFG_MAILBOX10_CLKCTRL DRA7_CLKCTRL_INDEX(0x88) -#define DRA7_L4CFG_MAILBOX11_CLKCTRL DRA7_CLKCTRL_INDEX(0x90) -#define DRA7_L4CFG_MAILBOX12_CLKCTRL DRA7_CLKCTRL_INDEX(0x98) -#define DRA7_L4CFG_MAILBOX13_CLKCTRL DRA7_CLKCTRL_INDEX(0xa0) - -/* l3instr clocks */ -#define DRA7_L3INSTR_L3_MAIN_2_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) -#define DRA7_L3INSTR_L3_INSTR_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) - -/* dss clocks */ -#define DRA7_DSS_DSS_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) -#define DRA7_DSS_BB2D_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) - -/* l3init clocks */ -#define DRA7_L3INIT_MMC1_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) -#define DRA7_L3INIT_MMC2_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) -#define DRA7_L3INIT_USB_OTG_SS2_CLKCTRL DRA7_CLKCTRL_INDEX(0x40) -#define DRA7_L3INIT_USB_OTG_SS3_CLKCTRL DRA7_CLKCTRL_INDEX(0x48) -#define DRA7_L3INIT_USB_OTG_SS4_CLKCTRL DRA7_CLKCTRL_INDEX(0x50) -#define DRA7_L3INIT_SATA_CLKCTRL DRA7_CLKCTRL_INDEX(0x88) -#define DRA7_L3INIT_OCP2SCP1_CLKCTRL DRA7_CLKCTRL_INDEX(0xe0) -#define DRA7_L3INIT_OCP2SCP3_CLKCTRL DRA7_CLKCTRL_INDEX(0xe8) -#define DRA7_L3INIT_USB_OTG_SS1_CLKCTRL DRA7_CLKCTRL_INDEX(0xf0) - -/* pcie clocks */ -#define DRA7_PCIE_CLKCTRL_OFFSET 0xb0 -#define DRA7_PCIE_CLKCTRL_INDEX(offset) ((offset) - DRA7_PCIE_CLKCTRL_OFFSET) -#define DRA7_PCIE_PCIE1_CLKCTRL DRA7_PCIE_CLKCTRL_INDEX(0xb0) -#define DRA7_PCIE_PCIE2_CLKCTRL DRA7_PCIE_CLKCTRL_INDEX(0xb8) - -/* gmac clocks */ -#define DRA7_GMAC_CLKCTRL_OFFSET 0xd0 -#define DRA7_GMAC_CLKCTRL_INDEX(offset) ((offset) - DRA7_GMAC_CLKCTRL_OFFSET) -#define DRA7_GMAC_GMAC_CLKCTRL DRA7_GMAC_CLKCTRL_INDEX(0xd0) - -/* l4per clocks */ -#define DRA7_L4PER_CLKCTRL_OFFSET 0x28 -#define DRA7_L4PER_CLKCTRL_INDEX(offset) ((offset) - DRA7_L4PER_CLKCTRL_OFFSET) -#define DRA7_L4PER_TIMER10_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x28) -#define DRA7_L4PER_TIMER11_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x30) -#define DRA7_L4PER_TIMER2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x38) -#define DRA7_L4PER_TIMER3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x40) -#define DRA7_L4PER_TIMER4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x48) -#define DRA7_L4PER_TIMER9_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x50) -#define DRA7_L4PER_ELM_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x58) -#define DRA7_L4PER_GPIO2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x60) -#define DRA7_L4PER_GPIO3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x68) -#define DRA7_L4PER_GPIO4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x70) -#define DRA7_L4PER_GPIO5_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x78) -#define DRA7_L4PER_GPIO6_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x80) -#define DRA7_L4PER_HDQ1W_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x88) -#define DRA7_L4PER_I2C1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xa0) -#define DRA7_L4PER_I2C2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xa8) -#define DRA7_L4PER_I2C3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xb0) -#define DRA7_L4PER_I2C4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xb8) -#define DRA7_L4PER_L4_PER1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xc0) -#define DRA7_L4PER_MCSPI1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xf0) -#define DRA7_L4PER_MCSPI2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xf8) -#define DRA7_L4PER_MCSPI3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x100) -#define DRA7_L4PER_MCSPI4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x108) -#define DRA7_L4PER_GPIO7_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x110) -#define DRA7_L4PER_GPIO8_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x118) -#define DRA7_L4PER_MMC3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x120) -#define DRA7_L4PER_MMC4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x128) -#define DRA7_L4PER_UART1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x140) -#define DRA7_L4PER_UART2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x148) -#define DRA7_L4PER_UART3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x150) -#define DRA7_L4PER_UART4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x158) -#define DRA7_L4PER_UART5_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x170) - -/* l4sec clocks */ -#define DRA7_L4SEC_CLKCTRL_OFFSET 0x1a0 -#define DRA7_L4SEC_CLKCTRL_INDEX(offset) ((offset) - DRA7_L4SEC_CLKCTRL_OFFSET) -#define DRA7_L4SEC_AES1_CLKCTRL DRA7_L4SEC_CLKCTRL_INDEX(0x1a0) -#define DRA7_L4SEC_AES2_CLKCTRL DRA7_L4SEC_CLKCTRL_INDEX(0x1a8) -#define DRA7_L4SEC_DES_CLKCTRL DRA7_L4SEC_CLKCTRL_INDEX(0x1b0) -#define DRA7_L4SEC_RNG_CLKCTRL DRA7_L4SEC_CLKCTRL_INDEX(0x1c0) -#define DRA7_L4SEC_SHAM_CLKCTRL DRA7_L4SEC_CLKCTRL_INDEX(0x1c8) - -/* l4per2 clocks */ -#define DRA7_L4PER2_CLKCTRL_OFFSET 0xc -#define DRA7_L4PER2_CLKCTRL_INDEX(offset) ((offset) - DRA7_L4PER2_CLKCTRL_OFFSET) -#define DRA7_L4PER2_L4_PER2_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0xc) -#define DRA7_L4PER2_PRUSS1_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x18) -#define DRA7_L4PER2_PRUSS2_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x20) -#define DRA7_L4PER2_EPWMSS1_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x90) -#define DRA7_L4PER2_EPWMSS2_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x98) -#define DRA7_L4PER2_EPWMSS0_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0xc4) -#define DRA7_L4PER2_QSPI_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x138) -#define DRA7_L4PER2_MCASP2_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x160) -#define DRA7_L4PER2_MCASP3_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x168) -#define DRA7_L4PER2_MCASP5_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x178) -#define DRA7_L4PER2_MCASP8_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x190) -#define DRA7_L4PER2_MCASP4_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x198) -#define DRA7_L4PER2_UART7_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x1d0) -#define DRA7_L4PER2_UART8_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x1e0) -#define DRA7_L4PER2_UART9_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x1e8) -#define DRA7_L4PER2_DCAN2_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x1f0) -#define DRA7_L4PER2_MCASP6_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x204) -#define DRA7_L4PER2_MCASP7_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x208) - -/* l4per3 clocks */ -#define DRA7_L4PER3_CLKCTRL_OFFSET 0x14 -#define DRA7_L4PER3_CLKCTRL_INDEX(offset) ((offset) - DRA7_L4PER3_CLKCTRL_OFFSET) -#define DRA7_L4PER3_L4_PER3_CLKCTRL DRA7_L4PER3_CLKCTRL_INDEX(0x14) -#define DRA7_L4PER3_TIMER13_CLKCTRL DRA7_L4PER3_CLKCTRL_INDEX(0xc8) -#define DRA7_L4PER3_TIMER14_CLKCTRL DRA7_L4PER3_CLKCTRL_INDEX(0xd0) -#define DRA7_L4PER3_TIMER15_CLKCTRL DRA7_L4PER3_CLKCTRL_INDEX(0xd8) -#define DRA7_L4PER3_TIMER16_CLKCTRL DRA7_L4PER3_CLKCTRL_INDEX(0x130) - -/* wkupaon clocks */ -#define DRA7_WKUPAON_L4_WKUP_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) -#define DRA7_WKUPAON_WD_TIMER2_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) -#define DRA7_WKUPAON_GPIO1_CLKCTRL DRA7_CLKCTRL_INDEX(0x38) -#define DRA7_WKUPAON_TIMER1_CLKCTRL DRA7_CLKCTRL_INDEX(0x40) -#define DRA7_WKUPAON_TIMER12_CLKCTRL DRA7_CLKCTRL_INDEX(0x48) -#define DRA7_WKUPAON_COUNTER_32K_CLKCTRL DRA7_CLKCTRL_INDEX(0x50) -#define DRA7_WKUPAON_UART10_CLKCTRL DRA7_CLKCTRL_INDEX(0x80) -#define DRA7_WKUPAON_DCAN1_CLKCTRL DRA7_CLKCTRL_INDEX(0x88) -#define DRA7_WKUPAON_ADC_CLKCTRL DRA7_CLKCTRL_INDEX(0xa0) - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/efm32-cmu.h b/sys/gnu/dts/include/dt-bindings/clock/efm32-cmu.h deleted file mode 100644 index 4b48d15fe19..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/efm32-cmu.h +++ /dev/null @@ -1,43 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __DT_BINDINGS_CLOCK_EFM32_CMU_H -#define __DT_BINDINGS_CLOCK_EFM32_CMU_H - -#define clk_HFXO 0 -#define clk_HFRCO 1 -#define clk_LFXO 2 -#define clk_LFRCO 3 -#define clk_ULFRCO 4 -#define clk_AUXHFRCO 5 -#define clk_HFCLKNODIV 6 -#define clk_HFCLK 7 -#define clk_HFPERCLK 8 -#define clk_HFCORECLK 9 -#define clk_LFACLK 10 -#define clk_LFBCLK 11 -#define clk_WDOGCLK 12 -#define clk_HFCORECLKDMA 13 -#define clk_HFCORECLKAES 14 -#define clk_HFCORECLKUSBC 15 -#define clk_HFCORECLKUSB 16 -#define clk_HFCORECLKLE 17 -#define clk_HFCORECLKEBI 18 -#define clk_HFPERCLKUSART0 19 -#define clk_HFPERCLKUSART1 20 -#define clk_HFPERCLKUSART2 21 -#define clk_HFPERCLKUART0 22 -#define clk_HFPERCLKUART1 23 -#define clk_HFPERCLKTIMER0 24 -#define clk_HFPERCLKTIMER1 25 -#define clk_HFPERCLKTIMER2 26 -#define clk_HFPERCLKTIMER3 27 -#define clk_HFPERCLKACMP0 28 -#define clk_HFPERCLKACMP1 29 -#define clk_HFPERCLKI2C0 30 -#define clk_HFPERCLKI2C1 31 -#define clk_HFPERCLKGPIO 32 -#define clk_HFPERCLKVCMP 33 -#define clk_HFPERCLKPRS 34 -#define clk_HFPERCLKADC0 35 -#define clk_HFPERCLKDAC0 36 - -#endif /* __DT_BINDINGS_CLOCK_EFM32_CMU_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/exynos-audss-clk.h b/sys/gnu/dts/include/dt-bindings/clock/exynos-audss-clk.h deleted file mode 100644 index eee9fcc6e6a..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/exynos-audss-clk.h +++ /dev/null @@ -1,27 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides constants for Samsung audio subsystem - * clock controller. - * - * The constants defined in this header are being used in dts - * and exynos audss driver. - */ - -#ifndef _DT_BINDINGS_CLK_EXYNOS_AUDSS_H -#define _DT_BINDINGS_CLK_EXYNOS_AUDSS_H - -#define EXYNOS_MOUT_AUDSS 0 -#define EXYNOS_MOUT_I2S 1 -#define EXYNOS_DOUT_SRP 2 -#define EXYNOS_DOUT_AUD_BUS 3 -#define EXYNOS_DOUT_I2S 4 -#define EXYNOS_SRP_CLK 5 -#define EXYNOS_I2S_BUS 6 -#define EXYNOS_SCLK_I2S 7 -#define EXYNOS_PCM_BUS 8 -#define EXYNOS_SCLK_PCM 9 -#define EXYNOS_ADMA 10 - -#define EXYNOS_AUDSS_MAX_CLKS 11 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/exynos3250.h b/sys/gnu/dts/include/dt-bindings/clock/exynos3250.h deleted file mode 100644 index fe8214017b4..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/exynos3250.h +++ /dev/null @@ -1,353 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2014 Samsung Electronics Co., Ltd. - * Author: Tomasz Figa - * - * Device Tree binding constants for Samsung Exynos3250 clock controllers. - */ - -#ifndef _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H -#define _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H - -/* - * Let each exported clock get a unique index, which is used on DT-enabled - * platforms to lookup the clock from a clock specifier. These indices are - * therefore considered an ABI and so must not be changed. This implies - * that new clocks should be added either in free spaces between clock groups - * or at the end. - */ - - -/* - * Main CMU - */ - -#define CLK_OSCSEL 1 -#define CLK_FIN_PLL 2 -#define CLK_FOUT_APLL 3 -#define CLK_FOUT_VPLL 4 -#define CLK_FOUT_UPLL 5 -#define CLK_FOUT_MPLL 6 -#define CLK_ARM_CLK 7 - -/* Muxes */ -#define CLK_MOUT_MPLL_USER_L 16 -#define CLK_MOUT_GDL 17 -#define CLK_MOUT_MPLL_USER_R 18 -#define CLK_MOUT_GDR 19 -#define CLK_MOUT_EBI 20 -#define CLK_MOUT_ACLK_200 21 -#define CLK_MOUT_ACLK_160 22 -#define CLK_MOUT_ACLK_100 23 -#define CLK_MOUT_ACLK_266_1 24 -#define CLK_MOUT_ACLK_266_0 25 -#define CLK_MOUT_ACLK_266 26 -#define CLK_MOUT_VPLL 27 -#define CLK_MOUT_EPLL_USER 28 -#define CLK_MOUT_EBI_1 29 -#define CLK_MOUT_UPLL 30 -#define CLK_MOUT_ACLK_400_MCUISP_SUB 31 -#define CLK_MOUT_MPLL 32 -#define CLK_MOUT_ACLK_400_MCUISP 33 -#define CLK_MOUT_VPLLSRC 34 -#define CLK_MOUT_CAM1 35 -#define CLK_MOUT_CAM_BLK 36 -#define CLK_MOUT_MFC 37 -#define CLK_MOUT_MFC_1 38 -#define CLK_MOUT_MFC_0 39 -#define CLK_MOUT_G3D 40 -#define CLK_MOUT_G3D_1 41 -#define CLK_MOUT_G3D_0 42 -#define CLK_MOUT_MIPI0 43 -#define CLK_MOUT_FIMD0 44 -#define CLK_MOUT_UART_ISP 45 -#define CLK_MOUT_SPI1_ISP 46 -#define CLK_MOUT_SPI0_ISP 47 -#define CLK_MOUT_TSADC 48 -#define CLK_MOUT_MMC1 49 -#define CLK_MOUT_MMC0 50 -#define CLK_MOUT_UART1 51 -#define CLK_MOUT_UART0 52 -#define CLK_MOUT_SPI1 53 -#define CLK_MOUT_SPI0 54 -#define CLK_MOUT_AUDIO 55 -#define CLK_MOUT_MPLL_USER_C 56 -#define CLK_MOUT_HPM 57 -#define CLK_MOUT_CORE 58 -#define CLK_MOUT_APLL 59 -#define CLK_MOUT_ACLK_266_SUB 60 -#define CLK_MOUT_UART2 61 -#define CLK_MOUT_MMC2 62 - -/* Dividers */ -#define CLK_DIV_GPL 64 -#define CLK_DIV_GDL 65 -#define CLK_DIV_GPR 66 -#define CLK_DIV_GDR 67 -#define CLK_DIV_MPLL_PRE 68 -#define CLK_DIV_ACLK_400_MCUISP 69 -#define CLK_DIV_EBI 70 -#define CLK_DIV_ACLK_200 71 -#define CLK_DIV_ACLK_160 72 -#define CLK_DIV_ACLK_100 73 -#define CLK_DIV_ACLK_266 74 -#define CLK_DIV_CAM1 75 -#define CLK_DIV_CAM_BLK 76 -#define CLK_DIV_MFC 77 -#define CLK_DIV_G3D 78 -#define CLK_DIV_MIPI0_PRE 79 -#define CLK_DIV_MIPI0 80 -#define CLK_DIV_FIMD0 81 -#define CLK_DIV_UART_ISP 82 -#define CLK_DIV_SPI1_ISP_PRE 83 -#define CLK_DIV_SPI1_ISP 84 -#define CLK_DIV_SPI0_ISP_PRE 85 -#define CLK_DIV_SPI0_ISP 86 -#define CLK_DIV_TSADC_PRE 87 -#define CLK_DIV_TSADC 88 -#define CLK_DIV_MMC1_PRE 89 -#define CLK_DIV_MMC1 90 -#define CLK_DIV_MMC0_PRE 91 -#define CLK_DIV_MMC0 92 -#define CLK_DIV_UART1 93 -#define CLK_DIV_UART0 94 -#define CLK_DIV_SPI1_PRE 95 -#define CLK_DIV_SPI1 96 -#define CLK_DIV_SPI0_PRE 97 -#define CLK_DIV_SPI0 98 -#define CLK_DIV_PCM 99 -#define CLK_DIV_AUDIO 100 -#define CLK_DIV_I2S 101 -#define CLK_DIV_CORE2 102 -#define CLK_DIV_APLL 103 -#define CLK_DIV_PCLK_DBG 104 -#define CLK_DIV_ATB 105 -#define CLK_DIV_COREM 106 -#define CLK_DIV_CORE 107 -#define CLK_DIV_HPM 108 -#define CLK_DIV_COPY 109 -#define CLK_DIV_UART2 110 -#define CLK_DIV_MMC2_PRE 111 -#define CLK_DIV_MMC2 112 - -/* Gates */ -#define CLK_ASYNC_G3D 128 -#define CLK_ASYNC_MFCL 129 -#define CLK_PPMULEFT 130 -#define CLK_GPIO_LEFT 131 -#define CLK_ASYNC_ISPMX 132 -#define CLK_ASYNC_FSYSD 133 -#define CLK_ASYNC_LCD0X 134 -#define CLK_ASYNC_CAMX 135 -#define CLK_PPMURIGHT 136 -#define CLK_GPIO_RIGHT 137 -#define CLK_MONOCNT 138 -#define CLK_TZPC6 139 -#define CLK_PROVISIONKEY1 140 -#define CLK_PROVISIONKEY0 141 -#define CLK_CMU_ISPPART 142 -#define CLK_TMU_APBIF 143 -#define CLK_KEYIF 144 -#define CLK_RTC 145 -#define CLK_WDT 146 -#define CLK_MCT 147 -#define CLK_SECKEY 148 -#define CLK_TZPC5 149 -#define CLK_TZPC4 150 -#define CLK_TZPC3 151 -#define CLK_TZPC2 152 -#define CLK_TZPC1 153 -#define CLK_TZPC0 154 -#define CLK_CMU_COREPART 155 -#define CLK_CMU_TOPPART 156 -#define CLK_PMU_APBIF 157 -#define CLK_SYSREG 158 -#define CLK_CHIP_ID 159 -#define CLK_QEJPEG 160 -#define CLK_PIXELASYNCM1 161 -#define CLK_PIXELASYNCM0 162 -#define CLK_PPMUCAMIF 163 -#define CLK_QEM2MSCALER 164 -#define CLK_QEGSCALER1 165 -#define CLK_QEGSCALER0 166 -#define CLK_SMMUJPEG 167 -#define CLK_SMMUM2M2SCALER 168 -#define CLK_SMMUGSCALER1 169 -#define CLK_SMMUGSCALER0 170 -#define CLK_JPEG 171 -#define CLK_M2MSCALER 172 -#define CLK_GSCALER1 173 -#define CLK_GSCALER0 174 -#define CLK_QEMFC 175 -#define CLK_PPMUMFC_L 176 -#define CLK_SMMUMFC_L 177 -#define CLK_MFC 178 -#define CLK_SMMUG3D 179 -#define CLK_QEG3D 180 -#define CLK_PPMUG3D 181 -#define CLK_G3D 182 -#define CLK_QE_CH1_LCD 183 -#define CLK_QE_CH0_LCD 184 -#define CLK_PPMULCD0 185 -#define CLK_SMMUFIMD0 186 -#define CLK_DSIM0 187 -#define CLK_FIMD0 188 -#define CLK_CAM1 189 -#define CLK_UART_ISP_TOP 190 -#define CLK_SPI1_ISP_TOP 191 -#define CLK_SPI0_ISP_TOP 192 -#define CLK_TSADC 193 -#define CLK_PPMUFILE 194 -#define CLK_USBOTG 195 -#define CLK_USBHOST 196 -#define CLK_SROMC 197 -#define CLK_SDMMC1 198 -#define CLK_SDMMC0 199 -#define CLK_PDMA1 200 -#define CLK_PDMA0 201 -#define CLK_PWM 202 -#define CLK_PCM 203 -#define CLK_I2S 204 -#define CLK_SPI1 205 -#define CLK_SPI0 206 -#define CLK_I2C7 207 -#define CLK_I2C6 208 -#define CLK_I2C5 209 -#define CLK_I2C4 210 -#define CLK_I2C3 211 -#define CLK_I2C2 212 -#define CLK_I2C1 213 -#define CLK_I2C0 214 -#define CLK_UART1 215 -#define CLK_UART0 216 -#define CLK_BLOCK_LCD 217 -#define CLK_BLOCK_G3D 218 -#define CLK_BLOCK_MFC 219 -#define CLK_BLOCK_CAM 220 -#define CLK_SMIES 221 -#define CLK_UART2 222 -#define CLK_SDMMC2 223 - -/* Special clocks */ -#define CLK_SCLK_JPEG 224 -#define CLK_SCLK_M2MSCALER 225 -#define CLK_SCLK_GSCALER1 226 -#define CLK_SCLK_GSCALER0 227 -#define CLK_SCLK_MFC 228 -#define CLK_SCLK_G3D 229 -#define CLK_SCLK_MIPIDPHY2L 230 -#define CLK_SCLK_MIPI0 231 -#define CLK_SCLK_FIMD0 232 -#define CLK_SCLK_CAM1 233 -#define CLK_SCLK_UART_ISP 234 -#define CLK_SCLK_SPI1_ISP 235 -#define CLK_SCLK_SPI0_ISP 236 -#define CLK_SCLK_UPLL 237 -#define CLK_SCLK_TSADC 238 -#define CLK_SCLK_EBI 239 -#define CLK_SCLK_MMC1 240 -#define CLK_SCLK_MMC0 241 -#define CLK_SCLK_I2S 242 -#define CLK_SCLK_PCM 243 -#define CLK_SCLK_SPI1 244 -#define CLK_SCLK_SPI0 245 -#define CLK_SCLK_UART1 246 -#define CLK_SCLK_UART0 247 -#define CLK_SCLK_UART2 248 -#define CLK_SCLK_MMC2 249 - -/* - * Total number of clocks of main CMU. - * NOTE: Must be equal to last clock ID increased by one. - */ -#define CLK_NR_CLKS 250 - -/* - * CMU DMC - */ - -#define CLK_FOUT_BPLL 1 -#define CLK_FOUT_EPLL 2 - -/* Muxes */ -#define CLK_MOUT_MPLL_MIF 8 -#define CLK_MOUT_BPLL 9 -#define CLK_MOUT_DPHY 10 -#define CLK_MOUT_DMC_BUS 11 -#define CLK_MOUT_EPLL 12 - -/* Dividers */ -#define CLK_DIV_DMC 16 -#define CLK_DIV_DPHY 17 -#define CLK_DIV_DMC_PRE 18 -#define CLK_DIV_DMCP 19 -#define CLK_DIV_DMCD 20 - -/* - * Total number of clocks of main CMU. - * NOTE: Must be equal to last clock ID increased by one. - */ -#define NR_CLKS_DMC 21 - -/* - * CMU ISP - */ - -/* Dividers */ - -#define CLK_DIV_ISP1 1 -#define CLK_DIV_ISP0 2 -#define CLK_DIV_MCUISP1 3 -#define CLK_DIV_MCUISP0 4 -#define CLK_DIV_MPWM 5 - -/* Gates */ - -#define CLK_UART_ISP 8 -#define CLK_WDT_ISP 9 -#define CLK_PWM_ISP 10 -#define CLK_I2C1_ISP 11 -#define CLK_I2C0_ISP 12 -#define CLK_MPWM_ISP 13 -#define CLK_MCUCTL_ISP 14 -#define CLK_PPMUISPX 15 -#define CLK_PPMUISPMX 16 -#define CLK_QE_LITE1 17 -#define CLK_QE_LITE0 18 -#define CLK_QE_FD 19 -#define CLK_QE_DRC 20 -#define CLK_QE_ISP 21 -#define CLK_CSIS1 22 -#define CLK_SMMU_LITE1 23 -#define CLK_SMMU_LITE0 24 -#define CLK_SMMU_FD 25 -#define CLK_SMMU_DRC 26 -#define CLK_SMMU_ISP 27 -#define CLK_GICISP 28 -#define CLK_CSIS0 29 -#define CLK_MCUISP 30 -#define CLK_LITE1 31 -#define CLK_LITE0 32 -#define CLK_FD 33 -#define CLK_DRC 34 -#define CLK_ISP 35 -#define CLK_QE_ISPCX 36 -#define CLK_QE_SCALERP 37 -#define CLK_QE_SCALERC 38 -#define CLK_SMMU_SCALERP 39 -#define CLK_SMMU_SCALERC 40 -#define CLK_SCALERP 41 -#define CLK_SCALERC 42 -#define CLK_SPI1_ISP 43 -#define CLK_SPI0_ISP 44 -#define CLK_SMMU_ISPCX 45 -#define CLK_ASYNCAXIM 46 -#define CLK_SCLK_MPWM_ISP 47 - -/* - * Total number of clocks of CMU_ISP. - * NOTE: Must be equal to last clock ID increased by one. - */ -#define NR_CLKS_ISP 48 - -#endif /* _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/exynos4.h b/sys/gnu/dts/include/dt-bindings/clock/exynos4.h deleted file mode 100644 index 88ec3968b90..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/exynos4.h +++ /dev/null @@ -1,278 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2013 Samsung Electronics Co., Ltd. - * Author: Andrzej Hajda - * - * Device Tree binding constants for Exynos4 clock controller. - */ - -#ifndef _DT_BINDINGS_CLOCK_EXYNOS_4_H -#define _DT_BINDINGS_CLOCK_EXYNOS_4_H - -/* core clocks */ -#define CLK_XXTI 1 -#define CLK_XUSBXTI 2 -#define CLK_FIN_PLL 3 -#define CLK_FOUT_APLL 4 -#define CLK_FOUT_MPLL 5 -#define CLK_FOUT_EPLL 6 -#define CLK_FOUT_VPLL 7 -#define CLK_SCLK_APLL 8 -#define CLK_SCLK_MPLL 9 -#define CLK_SCLK_EPLL 10 -#define CLK_SCLK_VPLL 11 -#define CLK_ARM_CLK 12 -#define CLK_ACLK200 13 -#define CLK_ACLK100 14 -#define CLK_ACLK160 15 -#define CLK_ACLK133 16 -#define CLK_MOUT_MPLL_USER_T 17 /* Exynos4x12 only */ -#define CLK_MOUT_MPLL_USER_C 18 /* Exynos4x12 only */ -#define CLK_MOUT_CORE 19 -#define CLK_MOUT_APLL 20 -#define CLK_SCLK_HDMIPHY 22 -#define CLK_OUT_DMC 23 -#define CLK_OUT_TOP 24 -#define CLK_OUT_LEFTBUS 25 -#define CLK_OUT_RIGHTBUS 26 -#define CLK_OUT_CPU 27 - -/* gate for special clocks (sclk) */ -#define CLK_SCLK_FIMC0 128 -#define CLK_SCLK_FIMC1 129 -#define CLK_SCLK_FIMC2 130 -#define CLK_SCLK_FIMC3 131 -#define CLK_SCLK_CAM0 132 -#define CLK_SCLK_CAM1 133 -#define CLK_SCLK_CSIS0 134 -#define CLK_SCLK_CSIS1 135 -#define CLK_SCLK_HDMI 136 -#define CLK_SCLK_MIXER 137 -#define CLK_SCLK_DAC 138 -#define CLK_SCLK_PIXEL 139 -#define CLK_SCLK_FIMD0 140 -#define CLK_SCLK_MDNIE0 141 /* Exynos4412 only */ -#define CLK_SCLK_MDNIE_PWM0 142 -#define CLK_SCLK_MIPI0 143 -#define CLK_SCLK_AUDIO0 144 -#define CLK_SCLK_MMC0 145 -#define CLK_SCLK_MMC1 146 -#define CLK_SCLK_MMC2 147 -#define CLK_SCLK_MMC3 148 -#define CLK_SCLK_MMC4 149 -#define CLK_SCLK_SATA 150 /* Exynos4210 only */ -#define CLK_SCLK_UART0 151 -#define CLK_SCLK_UART1 152 -#define CLK_SCLK_UART2 153 -#define CLK_SCLK_UART3 154 -#define CLK_SCLK_UART4 155 -#define CLK_SCLK_AUDIO1 156 -#define CLK_SCLK_AUDIO2 157 -#define CLK_SCLK_SPDIF 158 -#define CLK_SCLK_SPI0 159 -#define CLK_SCLK_SPI1 160 -#define CLK_SCLK_SPI2 161 -#define CLK_SCLK_SLIMBUS 162 -#define CLK_SCLK_FIMD1 163 /* Exynos4210 only */ -#define CLK_SCLK_MIPI1 164 /* Exynos4210 only */ -#define CLK_SCLK_PCM1 165 -#define CLK_SCLK_PCM2 166 -#define CLK_SCLK_I2S1 167 -#define CLK_SCLK_I2S2 168 -#define CLK_SCLK_MIPIHSI 169 /* Exynos4412 only */ -#define CLK_SCLK_MFC 170 -#define CLK_SCLK_PCM0 171 -#define CLK_SCLK_G3D 172 -#define CLK_SCLK_PWM_ISP 173 /* Exynos4x12 only */ -#define CLK_SCLK_SPI0_ISP 174 /* Exynos4x12 only */ -#define CLK_SCLK_SPI1_ISP 175 /* Exynos4x12 only */ -#define CLK_SCLK_UART_ISP 176 /* Exynos4x12 only */ -#define CLK_SCLK_FIMG2D 177 - -/* gate clocks */ -#define CLK_SSS 255 -#define CLK_FIMC0 256 -#define CLK_FIMC1 257 -#define CLK_FIMC2 258 -#define CLK_FIMC3 259 -#define CLK_CSIS0 260 -#define CLK_CSIS1 261 -#define CLK_JPEG 262 -#define CLK_SMMU_FIMC0 263 -#define CLK_SMMU_FIMC1 264 -#define CLK_SMMU_FIMC2 265 -#define CLK_SMMU_FIMC3 266 -#define CLK_SMMU_JPEG 267 -#define CLK_VP 268 -#define CLK_MIXER 269 -#define CLK_TVENC 270 /* Exynos4210 only */ -#define CLK_HDMI 271 -#define CLK_SMMU_TV 272 -#define CLK_MFC 273 -#define CLK_SMMU_MFCL 274 -#define CLK_SMMU_MFCR 275 -#define CLK_G3D 276 -#define CLK_G2D 277 -#define CLK_ROTATOR 278 -#define CLK_MDMA 279 -#define CLK_SMMU_G2D 280 -#define CLK_SMMU_ROTATOR 281 -#define CLK_SMMU_MDMA 282 -#define CLK_FIMD0 283 -#define CLK_MIE0 284 -#define CLK_MDNIE0 285 /* Exynos4412 only */ -#define CLK_DSIM0 286 -#define CLK_SMMU_FIMD0 287 -#define CLK_FIMD1 288 /* Exynos4210 only */ -#define CLK_MIE1 289 /* Exynos4210 only */ -#define CLK_DSIM1 290 /* Exynos4210 only */ -#define CLK_SMMU_FIMD1 291 /* Exynos4210 only */ -#define CLK_PDMA0 292 -#define CLK_PDMA1 293 -#define CLK_PCIE_PHY 294 -#define CLK_SATA_PHY 295 /* Exynos4210 only */ -#define CLK_TSI 296 -#define CLK_SDMMC0 297 -#define CLK_SDMMC1 298 -#define CLK_SDMMC2 299 -#define CLK_SDMMC3 300 -#define CLK_SDMMC4 301 -#define CLK_SATA 302 /* Exynos4210 only */ -#define CLK_SROMC 303 -#define CLK_USB_HOST 304 -#define CLK_USB_DEVICE 305 -#define CLK_PCIE 306 -#define CLK_ONENAND 307 -#define CLK_NFCON 308 -#define CLK_SMMU_PCIE 309 -#define CLK_GPS 310 -#define CLK_SMMU_GPS 311 -#define CLK_UART0 312 -#define CLK_UART1 313 -#define CLK_UART2 314 -#define CLK_UART3 315 -#define CLK_UART4 316 -#define CLK_I2C0 317 -#define CLK_I2C1 318 -#define CLK_I2C2 319 -#define CLK_I2C3 320 -#define CLK_I2C4 321 -#define CLK_I2C5 322 -#define CLK_I2C6 323 -#define CLK_I2C7 324 -#define CLK_I2C_HDMI 325 -#define CLK_TSADC 326 -#define CLK_SPI0 327 -#define CLK_SPI1 328 -#define CLK_SPI2 329 -#define CLK_I2S1 330 -#define CLK_I2S2 331 -#define CLK_PCM0 332 -#define CLK_I2S0 333 -#define CLK_PCM1 334 -#define CLK_PCM2 335 -#define CLK_PWM 336 -#define CLK_SLIMBUS 337 -#define CLK_SPDIF 338 -#define CLK_AC97 339 -#define CLK_MODEMIF 340 -#define CLK_CHIPID 341 -#define CLK_SYSREG 342 -#define CLK_HDMI_CEC 343 -#define CLK_MCT 344 -#define CLK_WDT 345 -#define CLK_RTC 346 -#define CLK_KEYIF 347 -#define CLK_AUDSS 348 -#define CLK_MIPI_HSI 349 /* Exynos4210 only */ -#define CLK_PIXELASYNCM0 351 -#define CLK_PIXELASYNCM1 352 -#define CLK_ASYNC_G3D 353 /* Exynos4x12 only */ -#define CLK_PWM_ISP_SCLK 379 /* Exynos4x12 only */ -#define CLK_SPI0_ISP_SCLK 380 /* Exynos4x12 only */ -#define CLK_SPI1_ISP_SCLK 381 /* Exynos4x12 only */ -#define CLK_UART_ISP_SCLK 382 /* Exynos4x12 only */ -#define CLK_TMU_APBIF 383 - -/* mux clocks */ -#define CLK_MOUT_FIMC0 384 -#define CLK_MOUT_FIMC1 385 -#define CLK_MOUT_FIMC2 386 -#define CLK_MOUT_FIMC3 387 -#define CLK_MOUT_CAM0 388 -#define CLK_MOUT_CAM1 389 -#define CLK_MOUT_CSIS0 390 -#define CLK_MOUT_CSIS1 391 -#define CLK_MOUT_G3D0 392 -#define CLK_MOUT_G3D1 393 -#define CLK_MOUT_G3D 394 -#define CLK_ACLK400_MCUISP 395 /* Exynos4x12 only */ -#define CLK_MOUT_HDMI 396 -#define CLK_MOUT_MIXER 397 - -/* gate clocks - ppmu */ -#define CLK_PPMULEFT 400 -#define CLK_PPMURIGHT 401 -#define CLK_PPMUCAMIF 402 -#define CLK_PPMUTV 403 -#define CLK_PPMUMFC_L 404 -#define CLK_PPMUMFC_R 405 -#define CLK_PPMUG3D 406 -#define CLK_PPMUIMAGE 407 -#define CLK_PPMULCD0 408 -#define CLK_PPMULCD1 409 /* Exynos4210 only */ -#define CLK_PPMUFILE 410 -#define CLK_PPMUGPS 411 -#define CLK_PPMUDMC0 412 -#define CLK_PPMUDMC1 413 -#define CLK_PPMUCPU 414 -#define CLK_PPMUACP 415 - -/* div clocks */ -#define CLK_DIV_ACLK200 454 /* Exynos4x12 only */ -#define CLK_DIV_ACLK400_MCUISP 455 /* Exynos4x12 only */ -#define CLK_DIV_ACP 456 -#define CLK_DIV_DMC 457 -#define CLK_DIV_C2C 458 /* Exynos4x12 only */ -#define CLK_DIV_GDL 459 -#define CLK_DIV_GDR 460 - -/* must be greater than maximal clock id */ -#define CLK_NR_CLKS 461 - -/* Exynos4x12 ISP clocks */ -#define CLK_ISP_FIMC_ISP 1 -#define CLK_ISP_FIMC_DRC 2 -#define CLK_ISP_FIMC_FD 3 -#define CLK_ISP_FIMC_LITE0 4 -#define CLK_ISP_FIMC_LITE1 5 -#define CLK_ISP_MCUISP 6 -#define CLK_ISP_GICISP 7 -#define CLK_ISP_SMMU_ISP 8 -#define CLK_ISP_SMMU_DRC 9 -#define CLK_ISP_SMMU_FD 10 -#define CLK_ISP_SMMU_LITE0 11 -#define CLK_ISP_SMMU_LITE1 12 -#define CLK_ISP_PPMUISPMX 13 -#define CLK_ISP_PPMUISPX 14 -#define CLK_ISP_MCUCTL_ISP 15 -#define CLK_ISP_MPWM_ISP 16 -#define CLK_ISP_I2C0_ISP 17 -#define CLK_ISP_I2C1_ISP 18 -#define CLK_ISP_MTCADC_ISP 19 -#define CLK_ISP_PWM_ISP 20 -#define CLK_ISP_WDT_ISP 21 -#define CLK_ISP_UART_ISP 22 -#define CLK_ISP_ASYNCAXIM 23 -#define CLK_ISP_SMMU_ISPCX 24 -#define CLK_ISP_SPI0_ISP 25 -#define CLK_ISP_SPI1_ISP 26 - -#define CLK_ISP_DIV_ISP0 27 -#define CLK_ISP_DIV_ISP1 28 -#define CLK_ISP_DIV_MCUISP0 29 -#define CLK_ISP_DIV_MCUISP1 30 - -#define CLK_NR_ISP_CLKS 31 - -#endif /* _DT_BINDINGS_CLOCK_EXYNOS_4_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/exynos4415.h b/sys/gnu/dts/include/dt-bindings/clock/exynos4415.h deleted file mode 100644 index 7eed5510072..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/exynos4415.h +++ /dev/null @@ -1,360 +0,0 @@ -/* - * Copyright (c) 2014 Samsung Electronics Co., Ltd. - * Author: Chanwoo Choi - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Device Tree binding constants for Samsung Exynos4415 clock controllers. - */ - -#ifndef _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS4415_CLOCK_H -#define _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS4415_CLOCK_H - -/* - * Let each exported clock get a unique index, which is used on DT-enabled - * platforms to lookup the clock from a clock specifier. These indices are - * therefore considered an ABI and so must not be changed. This implies - * that new clocks should be added either in free spaces between clock groups - * or at the end. - */ - -/* - * Main CMU - */ - -#define CLK_OSCSEL 1 -#define CLK_FIN_PLL 2 -#define CLK_FOUT_APLL 3 -#define CLK_FOUT_MPLL 4 -#define CLK_FOUT_EPLL 5 -#define CLK_FOUT_G3D_PLL 6 -#define CLK_FOUT_ISP_PLL 7 -#define CLK_FOUT_DISP_PLL 8 - -/* Muxes */ -#define CLK_MOUT_MPLL_USER_L 16 -#define CLK_MOUT_GDL 17 -#define CLK_MOUT_MPLL_USER_R 18 -#define CLK_MOUT_GDR 19 -#define CLK_MOUT_EBI 20 -#define CLK_MOUT_ACLK_200 21 -#define CLK_MOUT_ACLK_160 22 -#define CLK_MOUT_ACLK_100 23 -#define CLK_MOUT_ACLK_266 24 -#define CLK_MOUT_G3D_PLL 25 -#define CLK_MOUT_EPLL 26 -#define CLK_MOUT_EBI_1 27 -#define CLK_MOUT_ISP_PLL 28 -#define CLK_MOUT_DISP_PLL 29 -#define CLK_MOUT_MPLL_USER_T 30 -#define CLK_MOUT_ACLK_400_MCUISP 31 -#define CLK_MOUT_G3D_PLLSRC 32 -#define CLK_MOUT_CSIS1 33 -#define CLK_MOUT_CSIS0 34 -#define CLK_MOUT_CAM1 35 -#define CLK_MOUT_FIMC3_LCLK 36 -#define CLK_MOUT_FIMC2_LCLK 37 -#define CLK_MOUT_FIMC1_LCLK 38 -#define CLK_MOUT_FIMC0_LCLK 39 -#define CLK_MOUT_MFC 40 -#define CLK_MOUT_MFC_1 41 -#define CLK_MOUT_MFC_0 42 -#define CLK_MOUT_G3D 43 -#define CLK_MOUT_G3D_1 44 -#define CLK_MOUT_G3D_0 45 -#define CLK_MOUT_MIPI0 46 -#define CLK_MOUT_FIMD0 47 -#define CLK_MOUT_TSADC_ISP 48 -#define CLK_MOUT_UART_ISP 49 -#define CLK_MOUT_SPI1_ISP 50 -#define CLK_MOUT_SPI0_ISP 51 -#define CLK_MOUT_PWM_ISP 52 -#define CLK_MOUT_AUDIO0 53 -#define CLK_MOUT_TSADC 54 -#define CLK_MOUT_MMC2 55 -#define CLK_MOUT_MMC1 56 -#define CLK_MOUT_MMC0 57 -#define CLK_MOUT_UART3 58 -#define CLK_MOUT_UART2 59 -#define CLK_MOUT_UART1 60 -#define CLK_MOUT_UART0 61 -#define CLK_MOUT_SPI2 62 -#define CLK_MOUT_SPI1 63 -#define CLK_MOUT_SPI0 64 -#define CLK_MOUT_SPDIF 65 -#define CLK_MOUT_AUDIO2 66 -#define CLK_MOUT_AUDIO1 67 -#define CLK_MOUT_MPLL_USER_C 68 -#define CLK_MOUT_HPM 69 -#define CLK_MOUT_CORE 70 -#define CLK_MOUT_APLL 71 -#define CLK_MOUT_PXLASYNC_CSIS1_FIMC 72 -#define CLK_MOUT_PXLASYNC_CSIS0_FIMC 73 -#define CLK_MOUT_JPEG 74 -#define CLK_MOUT_JPEG1 75 -#define CLK_MOUT_JPEG0 76 -#define CLK_MOUT_ACLK_ISP0_300 77 -#define CLK_MOUT_ACLK_ISP0_400 78 -#define CLK_MOUT_ACLK_ISP0_300_USER 79 -#define CLK_MOUT_ACLK_ISP1_300 80 -#define CLK_MOUT_ACLK_ISP1_300_USER 81 -#define CLK_MOUT_HDMI 82 - -/* Dividers */ -#define CLK_DIV_GPL 90 -#define CLK_DIV_GDL 91 -#define CLK_DIV_GPR 92 -#define CLK_DIV_GDR 93 -#define CLK_DIV_ACLK_400_MCUISP 94 -#define CLK_DIV_EBI 95 -#define CLK_DIV_ACLK_200 96 -#define CLK_DIV_ACLK_160 97 -#define CLK_DIV_ACLK_100 98 -#define CLK_DIV_ACLK_266 99 -#define CLK_DIV_CSIS1 100 -#define CLK_DIV_CSIS0 101 -#define CLK_DIV_CAM1 102 -#define CLK_DIV_FIMC3_LCLK 103 -#define CLK_DIV_FIMC2_LCLK 104 -#define CLK_DIV_FIMC1_LCLK 105 -#define CLK_DIV_FIMC0_LCLK 106 -#define CLK_DIV_TV_BLK 107 -#define CLK_DIV_MFC 108 -#define CLK_DIV_G3D 109 -#define CLK_DIV_MIPI0_PRE 110 -#define CLK_DIV_MIPI0 111 -#define CLK_DIV_FIMD0 112 -#define CLK_DIV_UART_ISP 113 -#define CLK_DIV_SPI1_ISP_PRE 114 -#define CLK_DIV_SPI1_ISP 115 -#define CLK_DIV_SPI0_ISP_PRE 116 -#define CLK_DIV_SPI0_ISP 117 -#define CLK_DIV_PWM_ISP 118 -#define CLK_DIV_PCM0 119 -#define CLK_DIV_AUDIO0 120 -#define CLK_DIV_TSADC_PRE 121 -#define CLK_DIV_TSADC 122 -#define CLK_DIV_MMC1_PRE 123 -#define CLK_DIV_MMC1 124 -#define CLK_DIV_MMC0_PRE 125 -#define CLK_DIV_MMC0 126 -#define CLK_DIV_MMC2_PRE 127 -#define CLK_DIV_MMC2 128 -#define CLK_DIV_UART3 129 -#define CLK_DIV_UART2 130 -#define CLK_DIV_UART1 131 -#define CLK_DIV_UART0 132 -#define CLK_DIV_SPI1_PRE 133 -#define CLK_DIV_SPI1 134 -#define CLK_DIV_SPI0_PRE 135 -#define CLK_DIV_SPI0 136 -#define CLK_DIV_SPI2_PRE 137 -#define CLK_DIV_SPI2 138 -#define CLK_DIV_PCM2 139 -#define CLK_DIV_AUDIO2 140 -#define CLK_DIV_PCM1 141 -#define CLK_DIV_AUDIO1 142 -#define CLK_DIV_I2S1 143 -#define CLK_DIV_PXLASYNC_CSIS1_FIMC 144 -#define CLK_DIV_PXLASYNC_CSIS0_FIMC 145 -#define CLK_DIV_JPEG 146 -#define CLK_DIV_CORE2 147 -#define CLK_DIV_APLL 148 -#define CLK_DIV_PCLK_DBG 149 -#define CLK_DIV_ATB 150 -#define CLK_DIV_PERIPH 151 -#define CLK_DIV_COREM1 152 -#define CLK_DIV_COREM0 153 -#define CLK_DIV_CORE 154 -#define CLK_DIV_HPM 155 -#define CLK_DIV_COPY 156 - -/* Gates */ -#define CLK_ASYNC_G3D 180 -#define CLK_ASYNC_MFCL 181 -#define CLK_ASYNC_TVX 182 -#define CLK_PPMULEFT 183 -#define CLK_GPIO_LEFT 184 -#define CLK_PPMUIMAGE 185 -#define CLK_QEMDMA2 186 -#define CLK_QEROTATOR 187 -#define CLK_SMMUMDMA2 188 -#define CLK_SMMUROTATOR 189 -#define CLK_MDMA2 190 -#define CLK_ROTATOR 191 -#define CLK_ASYNC_ISPMX 192 -#define CLK_ASYNC_MAUDIOX 193 -#define CLK_ASYNC_MFCR 194 -#define CLK_ASYNC_FSYSD 195 -#define CLK_ASYNC_LCD0X 196 -#define CLK_ASYNC_CAMX 197 -#define CLK_PPMURIGHT 198 -#define CLK_GPIO_RIGHT 199 -#define CLK_ANTIRBK_APBIF 200 -#define CLK_EFUSE_WRITER_APBIF 201 -#define CLK_MONOCNT 202 -#define CLK_TZPC6 203 -#define CLK_PROVISIONKEY1 204 -#define CLK_PROVISIONKEY0 205 -#define CLK_CMU_ISPPART 206 -#define CLK_TMU_APBIF 207 -#define CLK_KEYIF 208 -#define CLK_RTC 209 -#define CLK_WDT 210 -#define CLK_MCT 211 -#define CLK_SECKEY 212 -#define CLK_HDMI_CEC 213 -#define CLK_TZPC5 214 -#define CLK_TZPC4 215 -#define CLK_TZPC3 216 -#define CLK_TZPC2 217 -#define CLK_TZPC1 218 -#define CLK_TZPC0 219 -#define CLK_CMU_COREPART 220 -#define CLK_CMU_TOPPART 221 -#define CLK_PMU_APBIF 222 -#define CLK_SYSREG 223 -#define CLK_CHIP_ID 224 -#define CLK_SMMUFIMC_LITE2 225 -#define CLK_FIMC_LITE2 226 -#define CLK_PIXELASYNCM1 227 -#define CLK_PIXELASYNCM0 228 -#define CLK_PPMUCAMIF 229 -#define CLK_SMMUJPEG 230 -#define CLK_SMMUFIMC3 231 -#define CLK_SMMUFIMC2 232 -#define CLK_SMMUFIMC1 233 -#define CLK_SMMUFIMC0 234 -#define CLK_JPEG 235 -#define CLK_CSIS1 236 -#define CLK_CSIS0 237 -#define CLK_FIMC3 238 -#define CLK_FIMC2 239 -#define CLK_FIMC1 240 -#define CLK_FIMC0 241 -#define CLK_PPMUTV 242 -#define CLK_SMMUTV 243 -#define CLK_HDMI 244 -#define CLK_MIXER 245 -#define CLK_VP 246 -#define CLK_PPMUMFC_R 247 -#define CLK_PPMUMFC_L 248 -#define CLK_SMMUMFC_R 249 -#define CLK_SMMUMFC_L 250 -#define CLK_MFC 251 -#define CLK_PPMUG3D 252 -#define CLK_G3D 253 -#define CLK_PPMULCD0 254 -#define CLK_SMMUFIMD0 255 -#define CLK_DSIM0 256 -#define CLK_SMIES 257 -#define CLK_MIE0 258 -#define CLK_FIMD0 259 -#define CLK_TSADC 260 -#define CLK_PPMUFILE 261 -#define CLK_NFCON 262 -#define CLK_USBDEVICE 263 -#define CLK_USBHOST 264 -#define CLK_SROMC 265 -#define CLK_SDMMC2 266 -#define CLK_SDMMC1 267 -#define CLK_SDMMC0 268 -#define CLK_PDMA1 269 -#define CLK_PDMA0 270 -#define CLK_SPDIF 271 -#define CLK_PWM 272 -#define CLK_PCM2 273 -#define CLK_PCM1 274 -#define CLK_I2S1 275 -#define CLK_SPI2 276 -#define CLK_SPI1 277 -#define CLK_SPI0 278 -#define CLK_I2CHDMI 279 -#define CLK_I2C7 280 -#define CLK_I2C6 281 -#define CLK_I2C5 282 -#define CLK_I2C4 283 -#define CLK_I2C3 284 -#define CLK_I2C2 285 -#define CLK_I2C1 286 -#define CLK_I2C0 287 -#define CLK_UART3 288 -#define CLK_UART2 289 -#define CLK_UART1 290 -#define CLK_UART0 291 - -/* Special clocks */ -#define CLK_SCLK_PXLAYSNC_CSIS1_FIMC 330 -#define CLK_SCLK_PXLAYSNC_CSIS0_FIMC 331 -#define CLK_SCLK_JPEG 332 -#define CLK_SCLK_CSIS1 333 -#define CLK_SCLK_CSIS0 334 -#define CLK_SCLK_CAM1 335 -#define CLK_SCLK_FIMC3_LCLK 336 -#define CLK_SCLK_FIMC2_LCLK 337 -#define CLK_SCLK_FIMC1_LCLK 338 -#define CLK_SCLK_FIMC0_LCLK 339 -#define CLK_SCLK_PIXEL 340 -#define CLK_SCLK_HDMI 341 -#define CLK_SCLK_MIXER 342 -#define CLK_SCLK_MFC 343 -#define CLK_SCLK_G3D 344 -#define CLK_SCLK_MIPIDPHY4L 345 -#define CLK_SCLK_MIPI0 346 -#define CLK_SCLK_MDNIE0 347 -#define CLK_SCLK_FIMD0 348 -#define CLK_SCLK_PCM0 349 -#define CLK_SCLK_AUDIO0 350 -#define CLK_SCLK_TSADC 351 -#define CLK_SCLK_EBI 352 -#define CLK_SCLK_MMC2 353 -#define CLK_SCLK_MMC1 354 -#define CLK_SCLK_MMC0 355 -#define CLK_SCLK_I2S 356 -#define CLK_SCLK_PCM2 357 -#define CLK_SCLK_PCM1 358 -#define CLK_SCLK_AUDIO2 359 -#define CLK_SCLK_AUDIO1 360 -#define CLK_SCLK_SPDIF 361 -#define CLK_SCLK_SPI2 362 -#define CLK_SCLK_SPI1 363 -#define CLK_SCLK_SPI0 364 -#define CLK_SCLK_UART3 365 -#define CLK_SCLK_UART2 366 -#define CLK_SCLK_UART1 367 -#define CLK_SCLK_UART0 368 -#define CLK_SCLK_HDMIPHY 369 - -/* - * Total number of clocks of main CMU. - * NOTE: Must be equal to last clock ID increased by one. - */ -#define CLK_NR_CLKS 370 - -/* - * CMU DMC - */ -#define CLK_DMC_FOUT_MPLL 1 -#define CLK_DMC_FOUT_BPLL 2 - -#define CLK_DMC_MOUT_MPLL 3 -#define CLK_DMC_MOUT_BPLL 4 -#define CLK_DMC_MOUT_DPHY 5 -#define CLK_DMC_MOUT_DMC_BUS 6 - -#define CLK_DMC_DIV_DMC 7 -#define CLK_DMC_DIV_DPHY 8 -#define CLK_DMC_DIV_DMC_PRE 9 -#define CLK_DMC_DIV_DMCP 10 -#define CLK_DMC_DIV_DMCD 11 -#define CLK_DMC_DIV_MPLL_PRE 12 - -/* - * Total number of clocks of CMU_DMC. - * NOTE: Must be equal to highest clock ID increased by one. - */ -#define NR_CLKS_DMC 13 - -#endif /* _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS4415_CLOCK_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/exynos5250.h b/sys/gnu/dts/include/dt-bindings/clock/exynos5250.h deleted file mode 100644 index bc8a3c53a54..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/exynos5250.h +++ /dev/null @@ -1,179 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2013 Samsung Electronics Co., Ltd. - * Author: Andrzej Hajda - * - * Device Tree binding constants for Exynos5250 clock controller. - */ - -#ifndef _DT_BINDINGS_CLOCK_EXYNOS_5250_H -#define _DT_BINDINGS_CLOCK_EXYNOS_5250_H - -/* core clocks */ -#define CLK_FIN_PLL 1 -#define CLK_FOUT_APLL 2 -#define CLK_FOUT_MPLL 3 -#define CLK_FOUT_BPLL 4 -#define CLK_FOUT_GPLL 5 -#define CLK_FOUT_CPLL 6 -#define CLK_FOUT_EPLL 7 -#define CLK_FOUT_VPLL 8 -#define CLK_ARM_CLK 9 - -/* gate for special clocks (sclk) */ -#define CLK_SCLK_CAM_BAYER 128 -#define CLK_SCLK_CAM0 129 -#define CLK_SCLK_CAM1 130 -#define CLK_SCLK_GSCL_WA 131 -#define CLK_SCLK_GSCL_WB 132 -#define CLK_SCLK_FIMD1 133 -#define CLK_SCLK_MIPI1 134 -#define CLK_SCLK_DP 135 -#define CLK_SCLK_HDMI 136 -#define CLK_SCLK_PIXEL 137 -#define CLK_SCLK_AUDIO0 138 -#define CLK_SCLK_MMC0 139 -#define CLK_SCLK_MMC1 140 -#define CLK_SCLK_MMC2 141 -#define CLK_SCLK_MMC3 142 -#define CLK_SCLK_SATA 143 -#define CLK_SCLK_USB3 144 -#define CLK_SCLK_JPEG 145 -#define CLK_SCLK_UART0 146 -#define CLK_SCLK_UART1 147 -#define CLK_SCLK_UART2 148 -#define CLK_SCLK_UART3 149 -#define CLK_SCLK_PWM 150 -#define CLK_SCLK_AUDIO1 151 -#define CLK_SCLK_AUDIO2 152 -#define CLK_SCLK_SPDIF 153 -#define CLK_SCLK_SPI0 154 -#define CLK_SCLK_SPI1 155 -#define CLK_SCLK_SPI2 156 -#define CLK_DIV_I2S1 157 -#define CLK_DIV_I2S2 158 -#define CLK_SCLK_HDMIPHY 159 -#define CLK_DIV_PCM0 160 - -/* gate clocks */ -#define CLK_GSCL0 256 -#define CLK_GSCL1 257 -#define CLK_GSCL2 258 -#define CLK_GSCL3 259 -#define CLK_GSCL_WA 260 -#define CLK_GSCL_WB 261 -#define CLK_SMMU_GSCL0 262 -#define CLK_SMMU_GSCL1 263 -#define CLK_SMMU_GSCL2 264 -#define CLK_SMMU_GSCL3 265 -#define CLK_MFC 266 -#define CLK_SMMU_MFCL 267 -#define CLK_SMMU_MFCR 268 -#define CLK_ROTATOR 269 -#define CLK_JPEG 270 -#define CLK_MDMA1 271 -#define CLK_SMMU_ROTATOR 272 -#define CLK_SMMU_JPEG 273 -#define CLK_SMMU_MDMA1 274 -#define CLK_PDMA0 275 -#define CLK_PDMA1 276 -#define CLK_SATA 277 -#define CLK_USBOTG 278 -#define CLK_MIPI_HSI 279 -#define CLK_SDMMC0 280 -#define CLK_SDMMC1 281 -#define CLK_SDMMC2 282 -#define CLK_SDMMC3 283 -#define CLK_SROMC 284 -#define CLK_USB2 285 -#define CLK_USB3 286 -#define CLK_SATA_PHYCTRL 287 -#define CLK_SATA_PHYI2C 288 -#define CLK_UART0 289 -#define CLK_UART1 290 -#define CLK_UART2 291 -#define CLK_UART3 292 -#define CLK_UART4 293 -#define CLK_I2C0 294 -#define CLK_I2C1 295 -#define CLK_I2C2 296 -#define CLK_I2C3 297 -#define CLK_I2C4 298 -#define CLK_I2C5 299 -#define CLK_I2C6 300 -#define CLK_I2C7 301 -#define CLK_I2C_HDMI 302 -#define CLK_ADC 303 -#define CLK_SPI0 304 -#define CLK_SPI1 305 -#define CLK_SPI2 306 -#define CLK_I2S1 307 -#define CLK_I2S2 308 -#define CLK_PCM1 309 -#define CLK_PCM2 310 -#define CLK_PWM 311 -#define CLK_SPDIF 312 -#define CLK_AC97 313 -#define CLK_HSI2C0 314 -#define CLK_HSI2C1 315 -#define CLK_HSI2C2 316 -#define CLK_HSI2C3 317 -#define CLK_CHIPID 318 -#define CLK_SYSREG 319 -#define CLK_PMU 320 -#define CLK_CMU_TOP 321 -#define CLK_CMU_CORE 322 -#define CLK_CMU_MEM 323 -#define CLK_TZPC0 324 -#define CLK_TZPC1 325 -#define CLK_TZPC2 326 -#define CLK_TZPC3 327 -#define CLK_TZPC4 328 -#define CLK_TZPC5 329 -#define CLK_TZPC6 330 -#define CLK_TZPC7 331 -#define CLK_TZPC8 332 -#define CLK_TZPC9 333 -#define CLK_HDMI_CEC 334 -#define CLK_MCT 335 -#define CLK_WDT 336 -#define CLK_RTC 337 -#define CLK_TMU 338 -#define CLK_FIMD1 339 -#define CLK_MIE1 340 -#define CLK_DSIM0 341 -#define CLK_DP 342 -#define CLK_MIXER 343 -#define CLK_HDMI 344 -#define CLK_G2D 345 -#define CLK_MDMA0 346 -#define CLK_SMMU_MDMA0 347 -#define CLK_SSS 348 -#define CLK_G3D 349 -#define CLK_SMMU_TV 350 -#define CLK_SMMU_FIMD1 351 -#define CLK_SMMU_2D 352 -#define CLK_SMMU_FIMC_ISP 353 -#define CLK_SMMU_FIMC_DRC 354 -#define CLK_SMMU_FIMC_SCC 355 -#define CLK_SMMU_FIMC_SCP 356 -#define CLK_SMMU_FIMC_FD 357 -#define CLK_SMMU_FIMC_MCU 358 -#define CLK_SMMU_FIMC_ODC 359 -#define CLK_SMMU_FIMC_DIS0 360 -#define CLK_SMMU_FIMC_DIS1 361 -#define CLK_SMMU_FIMC_3DNR 362 -#define CLK_SMMU_FIMC_LITE0 363 -#define CLK_SMMU_FIMC_LITE1 364 -#define CLK_CAMIF_TOP 365 - -/* mux clocks */ -#define CLK_MOUT_HDMI 1024 -#define CLK_MOUT_GPLL 1025 -#define CLK_MOUT_ACLK200_DISP1_SUB 1026 -#define CLK_MOUT_ACLK300_DISP1_SUB 1027 - -/* must be greater than maximal clock id */ -#define CLK_NR_CLKS 1028 - -#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5250_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/exynos5260-clk.h b/sys/gnu/dts/include/dt-bindings/clock/exynos5260-clk.h deleted file mode 100644 index 98a58cbd81b..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/exynos5260-clk.h +++ /dev/null @@ -1,466 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2014 Samsung Electronics Co., Ltd. - * Author: Rahul Sharma - * - * Provides Constants for Exynos5260 clocks. - */ - -#ifndef _DT_BINDINGS_CLK_EXYNOS5260_H -#define _DT_BINDINGS_CLK_EXYNOS5260_H - -/* Clock names: */ - -/* List Of Clocks For CMU_TOP */ - -#define TOP_FOUT_DISP_PLL 1 -#define TOP_FOUT_AUD_PLL 2 -#define TOP_MOUT_AUDTOP_PLL_USER 3 -#define TOP_MOUT_AUD_PLL 4 -#define TOP_MOUT_DISP_PLL 5 -#define TOP_MOUT_BUSTOP_PLL_USER 6 -#define TOP_MOUT_MEMTOP_PLL_USER 7 -#define TOP_MOUT_MEDIATOP_PLL_USER 8 -#define TOP_MOUT_DISP_DISP_333 9 -#define TOP_MOUT_ACLK_DISP_333 10 -#define TOP_MOUT_DISP_DISP_222 11 -#define TOP_MOUT_ACLK_DISP_222 12 -#define TOP_MOUT_DISP_MEDIA_PIXEL 13 -#define TOP_MOUT_FIMD1 14 -#define TOP_MOUT_SCLK_PERI_SPI0_CLK 15 -#define TOP_MOUT_SCLK_PERI_SPI1_CLK 16 -#define TOP_MOUT_SCLK_PERI_SPI2_CLK 17 -#define TOP_MOUT_SCLK_PERI_UART0_UCLK 18 -#define TOP_MOUT_SCLK_PERI_UART2_UCLK 19 -#define TOP_MOUT_SCLK_PERI_UART1_UCLK 20 -#define TOP_MOUT_BUS4_BUSTOP_100 21 -#define TOP_MOUT_BUS4_BUSTOP_400 22 -#define TOP_MOUT_BUS3_BUSTOP_100 23 -#define TOP_MOUT_BUS3_BUSTOP_400 24 -#define TOP_MOUT_BUS2_BUSTOP_400 25 -#define TOP_MOUT_BUS2_BUSTOP_100 26 -#define TOP_MOUT_BUS1_BUSTOP_100 27 -#define TOP_MOUT_BUS1_BUSTOP_400 28 -#define TOP_MOUT_SCLK_FSYS_USB 29 -#define TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_A 30 -#define TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_A 31 -#define TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_A 32 -#define TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_B 33 -#define TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_B 34 -#define TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_B 35 -#define TOP_MOUT_ACLK_ISP1_266 36 -#define TOP_MOUT_ISP1_MEDIA_266 37 -#define TOP_MOUT_ACLK_ISP1_400 38 -#define TOP_MOUT_ISP1_MEDIA_400 39 -#define TOP_MOUT_SCLK_ISP1_SPI0 40 -#define TOP_MOUT_SCLK_ISP1_SPI1 41 -#define TOP_MOUT_SCLK_ISP1_UART 42 -#define TOP_MOUT_SCLK_ISP1_SENSOR2 43 -#define TOP_MOUT_SCLK_ISP1_SENSOR1 44 -#define TOP_MOUT_SCLK_ISP1_SENSOR0 45 -#define TOP_MOUT_ACLK_MFC_333 46 -#define TOP_MOUT_MFC_BUSTOP_333 47 -#define TOP_MOUT_ACLK_G2D_333 48 -#define TOP_MOUT_G2D_BUSTOP_333 49 -#define TOP_MOUT_ACLK_GSCL_FIMC 50 -#define TOP_MOUT_GSCL_BUSTOP_FIMC 51 -#define TOP_MOUT_ACLK_GSCL_333 52 -#define TOP_MOUT_GSCL_BUSTOP_333 53 -#define TOP_MOUT_ACLK_GSCL_400 54 -#define TOP_MOUT_M2M_MEDIATOP_400 55 -#define TOP_DOUT_ACLK_MFC_333 56 -#define TOP_DOUT_ACLK_G2D_333 57 -#define TOP_DOUT_SCLK_ISP1_SENSOR2_A 58 -#define TOP_DOUT_SCLK_ISP1_SENSOR1_A 59 -#define TOP_DOUT_SCLK_ISP1_SENSOR0_A 60 -#define TOP_DOUT_ACLK_GSCL_FIMC 61 -#define TOP_DOUT_ACLK_GSCL_400 62 -#define TOP_DOUT_ACLK_GSCL_333 63 -#define TOP_DOUT_SCLK_ISP1_SPI0_B 64 -#define TOP_DOUT_SCLK_ISP1_SPI0_A 65 -#define TOP_DOUT_ACLK_ISP1_400 66 -#define TOP_DOUT_ACLK_ISP1_266 67 -#define TOP_DOUT_SCLK_ISP1_UART 68 -#define TOP_DOUT_SCLK_ISP1_SPI1_B 69 -#define TOP_DOUT_SCLK_ISP1_SPI1_A 70 -#define TOP_DOUT_SCLK_ISP1_SENSOR2_B 71 -#define TOP_DOUT_SCLK_ISP1_SENSOR1_B 72 -#define TOP_DOUT_SCLK_ISP1_SENSOR0_B 73 -#define TOP_DOUTTOP__SCLK_HPM_TARGETCLK 74 -#define TOP_DOUT_SCLK_DISP_PIXEL 75 -#define TOP_DOUT_ACLK_DISP_222 76 -#define TOP_DOUT_ACLK_DISP_333 77 -#define TOP_DOUT_ACLK_BUS4_100 78 -#define TOP_DOUT_ACLK_BUS4_400 79 -#define TOP_DOUT_ACLK_BUS3_100 80 -#define TOP_DOUT_ACLK_BUS3_400 81 -#define TOP_DOUT_ACLK_BUS2_100 82 -#define TOP_DOUT_ACLK_BUS2_400 83 -#define TOP_DOUT_ACLK_BUS1_100 84 -#define TOP_DOUT_ACLK_BUS1_400 85 -#define TOP_DOUT_SCLK_PERI_SPI1_B 86 -#define TOP_DOUT_SCLK_PERI_SPI1_A 87 -#define TOP_DOUT_SCLK_PERI_SPI0_B 88 -#define TOP_DOUT_SCLK_PERI_SPI0_A 89 -#define TOP_DOUT_SCLK_PERI_UART0 90 -#define TOP_DOUT_SCLK_PERI_UART2 91 -#define TOP_DOUT_SCLK_PERI_UART1 92 -#define TOP_DOUT_SCLK_PERI_SPI2_B 93 -#define TOP_DOUT_SCLK_PERI_SPI2_A 94 -#define TOP_DOUT_ACLK_PERI_AUD 95 -#define TOP_DOUT_ACLK_PERI_66 96 -#define TOP_DOUT_SCLK_FSYS_MMC0_SDCLKIN_B 97 -#define TOP_DOUT_SCLK_FSYS_MMC0_SDCLKIN_A 98 -#define TOP_DOUT_SCLK_FSYS_USBDRD30_SUSPEND_CLK 99 -#define TOP_DOUT_ACLK_FSYS_200 100 -#define TOP_DOUT_SCLK_FSYS_MMC2_SDCLKIN_B 101 -#define TOP_DOUT_SCLK_FSYS_MMC2_SDCLKIN_A 102 -#define TOP_DOUT_SCLK_FSYS_MMC1_SDCLKIN_B 103 -#define TOP_DOUT_SCLK_FSYS_MMC1_SDCLKIN_A 104 -#define TOP_SCLK_FIMD1 105 -#define TOP_SCLK_MMC2 106 -#define TOP_SCLK_MMC1 107 -#define TOP_SCLK_MMC0 108 -#define PHYCLK_DPTX_PHY_CH3_TXD_CLK 109 -#define PHYCLK_DPTX_PHY_CH2_TXD_CLK 110 -#define PHYCLK_DPTX_PHY_CH1_TXD_CLK 111 -#define PHYCLK_DPTX_PHY_CH0_TXD_CLK 112 -#define phyclk_hdmi_phy_tmds_clko 113 -#define PHYCLK_HDMI_PHY_PIXEL_CLKO 114 -#define PHYCLK_HDMI_LINK_O_TMDS_CLKHI 115 -#define PHYCLK_MIPI_DPHY_4L_M_TXBYTECLKHS 116 -#define PHYCLK_DPTX_PHY_O_REF_CLK_24M 117 -#define PHYCLK_DPTX_PHY_CLK_DIV2 118 -#define PHYCLK_MIPI_DPHY_4L_M_RXCLKESC0 119 -#define PHYCLK_USBHOST20_PHY_PHYCLOCK 120 -#define PHYCLK_USBHOST20_PHY_FREECLK 121 -#define PHYCLK_USBHOST20_PHY_CLK48MOHCI 122 -#define PHYCLK_USBDRD30_UDRD30_PIPE_PCLK 123 -#define PHYCLK_USBDRD30_UDRD30_PHYCLOCK 124 -#define TOP_NR_CLK 125 - - -/* List Of Clocks For CMU_EGL */ - -#define EGL_FOUT_EGL_PLL 1 -#define EGL_FOUT_EGL_DPLL 2 -#define EGL_MOUT_EGL_B 3 -#define EGL_MOUT_EGL_PLL 4 -#define EGL_DOUT_EGL_PLL 5 -#define EGL_DOUT_EGL_PCLK_DBG 6 -#define EGL_DOUT_EGL_ATCLK 7 -#define EGL_DOUT_PCLK_EGL 8 -#define EGL_DOUT_ACLK_EGL 9 -#define EGL_DOUT_EGL2 10 -#define EGL_DOUT_EGL1 11 -#define EGL_NR_CLK 12 - - -/* List Of Clocks For CMU_KFC */ - -#define KFC_FOUT_KFC_PLL 1 -#define KFC_MOUT_KFC_PLL 2 -#define KFC_MOUT_KFC 3 -#define KFC_DOUT_KFC_PLL 4 -#define KFC_DOUT_PCLK_KFC 5 -#define KFC_DOUT_ACLK_KFC 6 -#define KFC_DOUT_KFC_PCLK_DBG 7 -#define KFC_DOUT_KFC_ATCLK 8 -#define KFC_DOUT_KFC2 9 -#define KFC_DOUT_KFC1 10 -#define KFC_NR_CLK 11 - - -/* List Of Clocks For CMU_MIF */ - -#define MIF_FOUT_MEM_PLL 1 -#define MIF_FOUT_MEDIA_PLL 2 -#define MIF_FOUT_BUS_PLL 3 -#define MIF_MOUT_CLK2X_PHY 4 -#define MIF_MOUT_MIF_DREX2X 5 -#define MIF_MOUT_CLKM_PHY 6 -#define MIF_MOUT_MIF_DREX 7 -#define MIF_MOUT_MEDIA_PLL 8 -#define MIF_MOUT_BUS_PLL 9 -#define MIF_MOUT_MEM_PLL 10 -#define MIF_DOUT_ACLK_BUS_100 11 -#define MIF_DOUT_ACLK_BUS_200 12 -#define MIF_DOUT_ACLK_MIF_466 13 -#define MIF_DOUT_CLK2X_PHY 14 -#define MIF_DOUT_CLKM_PHY 15 -#define MIF_DOUT_BUS_PLL 16 -#define MIF_DOUT_MEM_PLL 17 -#define MIF_DOUT_MEDIA_PLL 18 -#define MIF_CLK_LPDDR3PHY_WRAP1 19 -#define MIF_CLK_LPDDR3PHY_WRAP0 20 -#define MIF_CLK_MONOCNT 21 -#define MIF_CLK_MIF_RTC 22 -#define MIF_CLK_DREX1 23 -#define MIF_CLK_DREX0 24 -#define MIF_CLK_INTMEM 25 -#define MIF_SCLK_LPDDR3PHY_WRAP_U1 26 -#define MIF_SCLK_LPDDR3PHY_WRAP_U0 27 -#define MIF_NR_CLK 28 - - -/* List Of Clocks For CMU_G3D */ - -#define G3D_FOUT_G3D_PLL 1 -#define G3D_MOUT_G3D_PLL 2 -#define G3D_DOUT_PCLK_G3D 3 -#define G3D_DOUT_ACLK_G3D 4 -#define G3D_CLK_G3D_HPM 5 -#define G3D_CLK_G3D 6 -#define G3D_NR_CLK 7 - - -/* List Of Clocks For CMU_AUD */ - -#define AUD_MOUT_SCLK_AUD_PCM 1 -#define AUD_MOUT_SCLK_AUD_I2S 2 -#define AUD_MOUT_AUD_PLL_USER 3 -#define AUD_DOUT_ACLK_AUD_131 4 -#define AUD_DOUT_SCLK_AUD_UART 5 -#define AUD_DOUT_SCLK_AUD_PCM 6 -#define AUD_DOUT_SCLK_AUD_I2S 7 -#define AUD_CLK_AUD_UART 8 -#define AUD_CLK_PCM 9 -#define AUD_CLK_I2S 10 -#define AUD_CLK_DMAC 11 -#define AUD_CLK_SRAMC 12 -#define AUD_SCLK_AUD_UART 13 -#define AUD_SCLK_PCM 14 -#define AUD_SCLK_I2S 15 -#define AUD_NR_CLK 16 - - -/* List Of Clocks For CMU_MFC */ - -#define MFC_MOUT_ACLK_MFC_333_USER 1 -#define MFC_DOUT_PCLK_MFC_83 2 -#define MFC_CLK_MFC 3 -#define MFC_CLK_SMMU2_MFCM1 4 -#define MFC_CLK_SMMU2_MFCM0 5 -#define MFC_NR_CLK 6 - - -/* List Of Clocks For CMU_GSCL */ - -#define GSCL_MOUT_ACLK_CSIS 1 -#define GSCL_MOUT_ACLK_GSCL_FIMC_USER 2 -#define GSCL_MOUT_ACLK_M2M_400_USER 3 -#define GSCL_MOUT_ACLK_GSCL_333_USER 4 -#define GSCL_DOUT_ACLK_CSIS_200 5 -#define GSCL_DOUT_PCLK_M2M_100 6 -#define GSCL_CLK_PIXEL_GSCL1 7 -#define GSCL_CLK_PIXEL_GSCL0 8 -#define GSCL_CLK_MSCL1 9 -#define GSCL_CLK_MSCL0 10 -#define GSCL_CLK_GSCL1 11 -#define GSCL_CLK_GSCL0 12 -#define GSCL_CLK_FIMC_LITE_D 13 -#define GSCL_CLK_FIMC_LITE_B 14 -#define GSCL_CLK_FIMC_LITE_A 15 -#define GSCL_CLK_CSIS1 16 -#define GSCL_CLK_CSIS0 17 -#define GSCL_CLK_SMMU3_LITE_D 18 -#define GSCL_CLK_SMMU3_LITE_B 19 -#define GSCL_CLK_SMMU3_LITE_A 20 -#define GSCL_CLK_SMMU3_GSCL0 21 -#define GSCL_CLK_SMMU3_GSCL1 22 -#define GSCL_CLK_SMMU3_MSCL0 23 -#define GSCL_CLK_SMMU3_MSCL1 24 -#define GSCL_SCLK_CSIS1_WRAP 25 -#define GSCL_SCLK_CSIS0_WRAP 26 -#define GSCL_NR_CLK 27 - - -/* List Of Clocks For CMU_FSYS */ - -#define FSYS_MOUT_PHYCLK_USBHOST20_PHYCLK_USER 1 -#define FSYS_MOUT_PHYCLK_USBHOST20_FREECLK_USER 2 -#define FSYS_MOUT_PHYCLK_USBHOST20_CLK48MOHCI_USER 3 -#define FSYS_MOUT_PHYCLK_USBDRD30_PIPE_PCLK_USER 4 -#define FSYS_MOUT_PHYCLK_USBDRD30_PHYCLOCK_USER 5 -#define FSYS_CLK_TSI 6 -#define FSYS_CLK_USBLINK 7 -#define FSYS_CLK_USBHOST20 8 -#define FSYS_CLK_USBDRD30 9 -#define FSYS_CLK_SROMC 10 -#define FSYS_CLK_PDMA 11 -#define FSYS_CLK_MMC2 12 -#define FSYS_CLK_MMC1 13 -#define FSYS_CLK_MMC0 14 -#define FSYS_CLK_RTIC 15 -#define FSYS_CLK_SMMU_RTIC 16 -#define FSYS_PHYCLK_USBDRD30 17 -#define FSYS_PHYCLK_USBHOST20 18 -#define FSYS_NR_CLK 19 - - -/* List Of Clocks For CMU_PERI */ - -#define PERI_MOUT_SCLK_SPDIF 1 -#define PERI_MOUT_SCLK_I2SCOD 2 -#define PERI_MOUT_SCLK_PCM 3 -#define PERI_DOUT_I2S 4 -#define PERI_DOUT_PCM 5 -#define PERI_CLK_WDT_KFC 6 -#define PERI_CLK_WDT_EGL 7 -#define PERI_CLK_HSIC3 8 -#define PERI_CLK_HSIC2 9 -#define PERI_CLK_HSIC1 10 -#define PERI_CLK_HSIC0 11 -#define PERI_CLK_PCM 12 -#define PERI_CLK_MCT 13 -#define PERI_CLK_I2S 14 -#define PERI_CLK_I2CHDMI 15 -#define PERI_CLK_I2C7 16 -#define PERI_CLK_I2C6 17 -#define PERI_CLK_I2C5 18 -#define PERI_CLK_I2C4 19 -#define PERI_CLK_I2C9 20 -#define PERI_CLK_I2C8 21 -#define PERI_CLK_I2C11 22 -#define PERI_CLK_I2C10 23 -#define PERI_CLK_HDMICEC 24 -#define PERI_CLK_EFUSE_WRITER 25 -#define PERI_CLK_ABB 26 -#define PERI_CLK_UART2 27 -#define PERI_CLK_UART1 28 -#define PERI_CLK_UART0 29 -#define PERI_CLK_ADC 30 -#define PERI_CLK_TMU4 31 -#define PERI_CLK_TMU3 32 -#define PERI_CLK_TMU2 33 -#define PERI_CLK_TMU1 34 -#define PERI_CLK_TMU0 35 -#define PERI_CLK_SPI2 36 -#define PERI_CLK_SPI1 37 -#define PERI_CLK_SPI0 38 -#define PERI_CLK_SPDIF 39 -#define PERI_CLK_PWM 40 -#define PERI_CLK_UART4 41 -#define PERI_CLK_CHIPID 42 -#define PERI_CLK_PROVKEY0 43 -#define PERI_CLK_PROVKEY1 44 -#define PERI_CLK_SECKEY 45 -#define PERI_CLK_TOP_RTC 46 -#define PERI_CLK_TZPC10 47 -#define PERI_CLK_TZPC9 48 -#define PERI_CLK_TZPC8 49 -#define PERI_CLK_TZPC7 50 -#define PERI_CLK_TZPC6 51 -#define PERI_CLK_TZPC5 52 -#define PERI_CLK_TZPC4 53 -#define PERI_CLK_TZPC3 54 -#define PERI_CLK_TZPC2 55 -#define PERI_CLK_TZPC1 56 -#define PERI_CLK_TZPC0 57 -#define PERI_SCLK_UART2 58 -#define PERI_SCLK_UART1 59 -#define PERI_SCLK_UART0 60 -#define PERI_SCLK_SPI2 61 -#define PERI_SCLK_SPI1 62 -#define PERI_SCLK_SPI0 63 -#define PERI_SCLK_SPDIF 64 -#define PERI_SCLK_I2S 65 -#define PERI_SCLK_PCM1 66 -#define PERI_NR_CLK 67 - - -/* List Of Clocks For CMU_DISP */ - -#define DISP_MOUT_SCLK_HDMI_SPDIF 1 -#define DISP_MOUT_SCLK_HDMI_PIXEL 2 -#define DISP_MOUT_PHYCLK_MIPI_DPHY_4LMRXCLK_ESC0_USER 3 -#define DISP_MOUT_PHYCLK_HDMI_PHY_TMDS_CLKO_USER 4 -#define DISP_MOUT_PHYCLK_HDMI_PHY_REF_CLKO_USER 5 -#define DISP_MOUT_HDMI_PHY_PIXEL 6 -#define DISP_MOUT_PHYCLK_HDMI_LINK_O_TMDS_CLKHI_USER 7 -#define DISP_MOUT_PHYCLK_MIPI_DPHY_4L_M_TXBYTE_CLKHS 8 -#define DISP_MOUT_PHYCLK_DPTX_PHY_O_REF_CLK_24M_USER 9 -#define DISP_MOUT_PHYCLK_DPTX_PHY_CLK_DIV2_USER 10 -#define DISP_MOUT_PHYCLK_DPTX_PHY_CH3_TXD_CLK_USER 11 -#define DISP_MOUT_PHYCLK_DPTX_PHY_CH2_TXD_CLK_USER 12 -#define DISP_MOUT_PHYCLK_DPTX_PHY_CH1_TXD_CLK_USER 13 -#define DISP_MOUT_PHYCLK_DPTX_PHY_CH0_TXD_CLK_USER 14 -#define DISP_MOUT_ACLK_DISP_222_USER 15 -#define DISP_MOUT_SCLK_DISP_PIXEL_USER 16 -#define DISP_MOUT_ACLK_DISP_333_USER 17 -#define DISP_DOUT_SCLK_HDMI_PHY_PIXEL_CLKI 18 -#define DISP_DOUT_SCLK_FIMD1_EXTCLKPLL 19 -#define DISP_DOUT_PCLK_DISP_111 20 -#define DISP_CLK_SMMU_TV 21 -#define DISP_CLK_SMMU_FIMD1M1 22 -#define DISP_CLK_SMMU_FIMD1M0 23 -#define DISP_CLK_PIXEL_MIXER 24 -#define DISP_CLK_PIXEL_DISP 25 -#define DISP_CLK_MIXER 26 -#define DISP_CLK_MIPIPHY 27 -#define DISP_CLK_HDMIPHY 28 -#define DISP_CLK_HDMI 29 -#define DISP_CLK_FIMD1 30 -#define DISP_CLK_DSIM1 31 -#define DISP_CLK_DPPHY 32 -#define DISP_CLK_DP 33 -#define DISP_SCLK_PIXEL 34 -#define DISP_MOUT_HDMI_PHY_PIXEL_USER 35 -#define DISP_NR_CLK 36 - - -/* List Of Clocks For CMU_G2D */ - -#define G2D_MOUT_ACLK_G2D_333_USER 1 -#define G2D_DOUT_PCLK_G2D_83 2 -#define G2D_CLK_SMMU3_JPEG 3 -#define G2D_CLK_MDMA 4 -#define G2D_CLK_JPEG 5 -#define G2D_CLK_G2D 6 -#define G2D_CLK_SSS 7 -#define G2D_CLK_SLIM_SSS 8 -#define G2D_CLK_SMMU_SLIM_SSS 9 -#define G2D_CLK_SMMU_SSS 10 -#define G2D_CLK_SMMU_MDMA 11 -#define G2D_CLK_SMMU3_G2D 12 -#define G2D_NR_CLK 13 - - -/* List Of Clocks For CMU_ISP */ - -#define ISP_MOUT_ISP_400_USER 1 -#define ISP_MOUT_ISP_266_USER 2 -#define ISP_DOUT_SCLK_MPWM 3 -#define ISP_DOUT_CA5_PCLKDBG 4 -#define ISP_DOUT_CA5_ATCLKIN 5 -#define ISP_DOUT_PCLK_ISP_133 6 -#define ISP_DOUT_PCLK_ISP_66 7 -#define ISP_CLK_GIC 8 -#define ISP_CLK_WDT 9 -#define ISP_CLK_UART 10 -#define ISP_CLK_SPI1 11 -#define ISP_CLK_SPI0 12 -#define ISP_CLK_SMMU_SCALERP 13 -#define ISP_CLK_SMMU_SCALERC 14 -#define ISP_CLK_SMMU_ISPCX 15 -#define ISP_CLK_SMMU_ISP 16 -#define ISP_CLK_SMMU_FD 17 -#define ISP_CLK_SMMU_DRC 18 -#define ISP_CLK_PWM 19 -#define ISP_CLK_MTCADC 20 -#define ISP_CLK_MPWM 21 -#define ISP_CLK_MCUCTL 22 -#define ISP_CLK_I2C1 23 -#define ISP_CLK_I2C0 24 -#define ISP_CLK_FIMC_SCALERP 25 -#define ISP_CLK_FIMC_SCALERC 26 -#define ISP_CLK_FIMC 27 -#define ISP_CLK_FIMC_FD 28 -#define ISP_CLK_FIMC_DRC 29 -#define ISP_CLK_CA5 30 -#define ISP_SCLK_SPI0_EXT 31 -#define ISP_SCLK_SPI1_EXT 32 -#define ISP_SCLK_UART_EXT 33 -#define ISP_NR_CLK 34 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/exynos5410.h b/sys/gnu/dts/include/dt-bindings/clock/exynos5410.h deleted file mode 100644 index 86c2ad56c5e..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/exynos5410.h +++ /dev/null @@ -1,66 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2014 Samsung Electronics Co., Ltd. - * Copyright (c) 2016 Krzysztof Kozlowski - * - * Device Tree binding constants for Exynos5421 clock controller. - */ - -#ifndef _DT_BINDINGS_CLOCK_EXYNOS_5410_H -#define _DT_BINDINGS_CLOCK_EXYNOS_5410_H - -/* core clocks */ -#define CLK_FIN_PLL 1 -#define CLK_FOUT_APLL 2 -#define CLK_FOUT_CPLL 3 -#define CLK_FOUT_MPLL 4 -#define CLK_FOUT_BPLL 5 -#define CLK_FOUT_KPLL 6 -#define CLK_FOUT_EPLL 7 - -/* gate for special clocks (sclk) */ -#define CLK_SCLK_UART0 128 -#define CLK_SCLK_UART1 129 -#define CLK_SCLK_UART2 130 -#define CLK_SCLK_UART3 131 -#define CLK_SCLK_MMC0 132 -#define CLK_SCLK_MMC1 133 -#define CLK_SCLK_MMC2 134 -#define CLK_SCLK_USBD300 150 -#define CLK_SCLK_USBD301 151 -#define CLK_SCLK_USBPHY300 152 -#define CLK_SCLK_USBPHY301 153 -#define CLK_SCLK_PWM 155 - -/* gate clocks */ -#define CLK_UART0 257 -#define CLK_UART1 258 -#define CLK_UART2 259 -#define CLK_UART3 260 -#define CLK_I2C0 261 -#define CLK_I2C1 262 -#define CLK_I2C2 263 -#define CLK_I2C3 264 -#define CLK_USI0 265 -#define CLK_USI1 266 -#define CLK_USI2 267 -#define CLK_USI3 268 -#define CLK_TSADC 270 -#define CLK_PWM 279 -#define CLK_MCT 315 -#define CLK_WDT 316 -#define CLK_RTC 317 -#define CLK_TMU 318 -#define CLK_MMC0 351 -#define CLK_MMC1 352 -#define CLK_MMC2 353 -#define CLK_PDMA0 362 -#define CLK_PDMA1 363 -#define CLK_USBH20 365 -#define CLK_USBD300 366 -#define CLK_USBD301 367 -#define CLK_SSS 471 - -#define CLK_NR_CLKS 512 - -#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5410_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/exynos5420.h b/sys/gnu/dts/include/dt-bindings/clock/exynos5420.h deleted file mode 100644 index 02d5ac469a3..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/exynos5420.h +++ /dev/null @@ -1,271 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2013 Samsung Electronics Co., Ltd. - * Author: Andrzej Hajda - * - * Device Tree binding constants for Exynos5420 clock controller. - */ - -#ifndef _DT_BINDINGS_CLOCK_EXYNOS_5420_H -#define _DT_BINDINGS_CLOCK_EXYNOS_5420_H - -/* core clocks */ -#define CLK_FIN_PLL 1 -#define CLK_FOUT_APLL 2 -#define CLK_FOUT_CPLL 3 -#define CLK_FOUT_DPLL 4 -#define CLK_FOUT_EPLL 5 -#define CLK_FOUT_RPLL 6 -#define CLK_FOUT_IPLL 7 -#define CLK_FOUT_SPLL 8 -#define CLK_FOUT_VPLL 9 -#define CLK_FOUT_MPLL 10 -#define CLK_FOUT_BPLL 11 -#define CLK_FOUT_KPLL 12 -#define CLK_ARM_CLK 13 -#define CLK_KFC_CLK 14 - -/* gate for special clocks (sclk) */ -#define CLK_SCLK_UART0 128 -#define CLK_SCLK_UART1 129 -#define CLK_SCLK_UART2 130 -#define CLK_SCLK_UART3 131 -#define CLK_SCLK_MMC0 132 -#define CLK_SCLK_MMC1 133 -#define CLK_SCLK_MMC2 134 -#define CLK_SCLK_SPI0 135 -#define CLK_SCLK_SPI1 136 -#define CLK_SCLK_SPI2 137 -#define CLK_SCLK_I2S1 138 -#define CLK_SCLK_I2S2 139 -#define CLK_SCLK_PCM1 140 -#define CLK_SCLK_PCM2 141 -#define CLK_SCLK_SPDIF 142 -#define CLK_SCLK_HDMI 143 -#define CLK_SCLK_PIXEL 144 -#define CLK_SCLK_DP1 145 -#define CLK_SCLK_MIPI1 146 -#define CLK_SCLK_FIMD1 147 -#define CLK_SCLK_MAUDIO0 148 -#define CLK_SCLK_MAUPCM0 149 -#define CLK_SCLK_USBD300 150 -#define CLK_SCLK_USBD301 151 -#define CLK_SCLK_USBPHY300 152 -#define CLK_SCLK_USBPHY301 153 -#define CLK_SCLK_UNIPRO 154 -#define CLK_SCLK_PWM 155 -#define CLK_SCLK_GSCL_WA 156 -#define CLK_SCLK_GSCL_WB 157 -#define CLK_SCLK_HDMIPHY 158 -#define CLK_MAU_EPLL 159 -#define CLK_SCLK_HSIC_12M 160 -#define CLK_SCLK_MPHY_IXTAL24 161 -#define CLK_SCLK_BPLL 162 - -/* gate clocks */ -#define CLK_UART0 257 -#define CLK_UART1 258 -#define CLK_UART2 259 -#define CLK_UART3 260 -#define CLK_I2C0 261 -#define CLK_I2C1 262 -#define CLK_I2C2 263 -#define CLK_I2C3 264 -#define CLK_USI0 265 -#define CLK_USI1 266 -#define CLK_USI2 267 -#define CLK_USI3 268 -#define CLK_I2C_HDMI 269 -#define CLK_TSADC 270 -#define CLK_SPI0 271 -#define CLK_SPI1 272 -#define CLK_SPI2 273 -#define CLK_KEYIF 274 -#define CLK_I2S1 275 -#define CLK_I2S2 276 -#define CLK_PCM1 277 -#define CLK_PCM2 278 -#define CLK_PWM 279 -#define CLK_SPDIF 280 -#define CLK_USI4 281 -#define CLK_USI5 282 -#define CLK_USI6 283 -#define CLK_ACLK66_PSGEN 300 -#define CLK_CHIPID 301 -#define CLK_SYSREG 302 -#define CLK_TZPC0 303 -#define CLK_TZPC1 304 -#define CLK_TZPC2 305 -#define CLK_TZPC3 306 -#define CLK_TZPC4 307 -#define CLK_TZPC5 308 -#define CLK_TZPC6 309 -#define CLK_TZPC7 310 -#define CLK_TZPC8 311 -#define CLK_TZPC9 312 -#define CLK_HDMI_CEC 313 -#define CLK_SECKEY 314 -#define CLK_MCT 315 -#define CLK_WDT 316 -#define CLK_RTC 317 -#define CLK_TMU 318 -#define CLK_TMU_GPU 319 -#define CLK_PCLK66_GPIO 330 -#define CLK_ACLK200_FSYS2 350 -#define CLK_MMC0 351 -#define CLK_MMC1 352 -#define CLK_MMC2 353 -#define CLK_SROMC 354 -#define CLK_UFS 355 -#define CLK_ACLK200_FSYS 360 -#define CLK_TSI 361 -#define CLK_PDMA0 362 -#define CLK_PDMA1 363 -#define CLK_RTIC 364 -#define CLK_USBH20 365 -#define CLK_USBD300 366 -#define CLK_USBD301 367 -#define CLK_ACLK400_MSCL 380 -#define CLK_MSCL0 381 -#define CLK_MSCL1 382 -#define CLK_MSCL2 383 -#define CLK_SMMU_MSCL0 384 -#define CLK_SMMU_MSCL1 385 -#define CLK_SMMU_MSCL2 386 -#define CLK_ACLK333 400 -#define CLK_MFC 401 -#define CLK_SMMU_MFCL 402 -#define CLK_SMMU_MFCR 403 -#define CLK_ACLK200_DISP1 410 -#define CLK_DSIM1 411 -#define CLK_DP1 412 -#define CLK_HDMI 413 -#define CLK_ACLK300_DISP1 420 -#define CLK_FIMD1 421 -#define CLK_SMMU_FIMD1M0 422 -#define CLK_SMMU_FIMD1M1 423 -#define CLK_ACLK166 430 -#define CLK_MIXER 431 -#define CLK_ACLK266 440 -#define CLK_ROTATOR 441 -#define CLK_MDMA1 442 -#define CLK_SMMU_ROTATOR 443 -#define CLK_SMMU_MDMA1 444 -#define CLK_ACLK300_JPEG 450 -#define CLK_JPEG 451 -#define CLK_JPEG2 452 -#define CLK_SMMU_JPEG 453 -#define CLK_SMMU_JPEG2 454 -#define CLK_ACLK300_GSCL 460 -#define CLK_SMMU_GSCL0 461 -#define CLK_SMMU_GSCL1 462 -#define CLK_GSCL_WA 463 -#define CLK_GSCL_WB 464 -#define CLK_GSCL0 465 -#define CLK_GSCL1 466 -#define CLK_FIMC_3AA 467 -#define CLK_ACLK266_G2D 470 -#define CLK_SSS 471 -#define CLK_SLIM_SSS 472 -#define CLK_MDMA0 473 -#define CLK_ACLK333_G2D 480 -#define CLK_G2D 481 -#define CLK_ACLK333_432_GSCL 490 -#define CLK_SMMU_3AA 491 -#define CLK_SMMU_FIMCL0 492 -#define CLK_SMMU_FIMCL1 493 -#define CLK_SMMU_FIMCL3 494 -#define CLK_FIMC_LITE3 495 -#define CLK_FIMC_LITE0 496 -#define CLK_FIMC_LITE1 497 -#define CLK_ACLK_G3D 500 -#define CLK_G3D 501 -#define CLK_SMMU_MIXER 502 -#define CLK_SMMU_G2D 503 -#define CLK_SMMU_MDMA0 504 -#define CLK_MC 505 -#define CLK_TOP_RTC 506 -#define CLK_SCLK_UART_ISP 510 -#define CLK_SCLK_SPI0_ISP 511 -#define CLK_SCLK_SPI1_ISP 512 -#define CLK_SCLK_PWM_ISP 513 -#define CLK_SCLK_ISP_SENSOR0 514 -#define CLK_SCLK_ISP_SENSOR1 515 -#define CLK_SCLK_ISP_SENSOR2 516 -#define CLK_ACLK432_SCALER 517 -#define CLK_ACLK432_CAM 518 -#define CLK_ACLK_FL1550_CAM 519 -#define CLK_ACLK550_CAM 520 -#define CLK_CLKM_PHY0 521 -#define CLK_CLKM_PHY1 522 -#define CLK_ACLK_PPMU_DREX0_0 523 -#define CLK_ACLK_PPMU_DREX0_1 524 -#define CLK_ACLK_PPMU_DREX1_0 525 -#define CLK_ACLK_PPMU_DREX1_1 526 -#define CLK_PCLK_PPMU_DREX0_0 527 -#define CLK_PCLK_PPMU_DREX0_1 528 -#define CLK_PCLK_PPMU_DREX1_0 529 -#define CLK_PCLK_PPMU_DREX1_1 530 - -/* mux clocks */ -#define CLK_MOUT_HDMI 640 -#define CLK_MOUT_G3D 641 -#define CLK_MOUT_VPLL 642 -#define CLK_MOUT_MAUDIO0 643 -#define CLK_MOUT_USER_ACLK333 644 -#define CLK_MOUT_SW_ACLK333 645 -#define CLK_MOUT_USER_ACLK200_DISP1 646 -#define CLK_MOUT_SW_ACLK200 647 -#define CLK_MOUT_USER_ACLK300_DISP1 648 -#define CLK_MOUT_SW_ACLK300 649 -#define CLK_MOUT_USER_ACLK400_DISP1 650 -#define CLK_MOUT_SW_ACLK400 651 -#define CLK_MOUT_USER_ACLK300_GSCL 652 -#define CLK_MOUT_SW_ACLK300_GSCL 653 -#define CLK_MOUT_MCLK_CDREX 654 -#define CLK_MOUT_BPLL 655 -#define CLK_MOUT_MX_MSPLL_CCORE 656 -#define CLK_MOUT_EPLL 657 -#define CLK_MOUT_MAU_EPLL 658 -#define CLK_MOUT_USER_MAU_EPLL 659 -#define CLK_MOUT_SCLK_SPLL 660 -#define CLK_MOUT_MX_MSPLL_CCORE_PHY 661 - -/* divider clocks */ -#define CLK_DOUT_PIXEL 768 -#define CLK_DOUT_ACLK400_WCORE 769 -#define CLK_DOUT_ACLK400_ISP 770 -#define CLK_DOUT_ACLK400_MSCL 771 -#define CLK_DOUT_ACLK200 772 -#define CLK_DOUT_ACLK200_FSYS2 773 -#define CLK_DOUT_ACLK100_NOC 774 -#define CLK_DOUT_PCLK200_FSYS 775 -#define CLK_DOUT_ACLK200_FSYS 776 -#define CLK_DOUT_ACLK333_432_GSCL 777 -#define CLK_DOUT_ACLK333_432_ISP 778 -#define CLK_DOUT_ACLK66 779 -#define CLK_DOUT_ACLK333_432_ISP0 780 -#define CLK_DOUT_ACLK266 781 -#define CLK_DOUT_ACLK166 782 -#define CLK_DOUT_ACLK333 783 -#define CLK_DOUT_ACLK333_G2D 784 -#define CLK_DOUT_ACLK266_G2D 785 -#define CLK_DOUT_ACLK_G3D 786 -#define CLK_DOUT_ACLK300_JPEG 787 -#define CLK_DOUT_ACLK300_DISP1 788 -#define CLK_DOUT_ACLK300_GSCL 789 -#define CLK_DOUT_ACLK400_DISP1 790 -#define CLK_DOUT_PCLK_CDREX 791 -#define CLK_DOUT_SCLK_CDREX 792 -#define CLK_DOUT_ACLK_CDREX1 793 -#define CLK_DOUT_CCLK_DREX0 794 -#define CLK_DOUT_CLK2X_PHY0 795 -#define CLK_DOUT_PCLK_CORE_MEM 796 -#define CLK_FF_DOUT_SPLL2 797 -#define CLK_DOUT_PCLK_DREX0 798 -#define CLK_DOUT_PCLK_DREX1 799 - -/* must be greater than maximal clock id */ -#define CLK_NR_CLKS 800 - -#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5420_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/exynos5433.h b/sys/gnu/dts/include/dt-bindings/clock/exynos5433.h deleted file mode 100644 index 25ffa53573a..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/exynos5433.h +++ /dev/null @@ -1,1415 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2014 Samsung Electronics Co., Ltd. - * Author: Chanwoo Choi - */ - -#ifndef _DT_BINDINGS_CLOCK_EXYNOS5433_H -#define _DT_BINDINGS_CLOCK_EXYNOS5433_H - -/* CMU_TOP */ -#define CLK_FOUT_ISP_PLL 1 -#define CLK_FOUT_AUD_PLL 2 - -#define CLK_MOUT_AUD_PLL 10 -#define CLK_MOUT_ISP_PLL 11 -#define CLK_MOUT_AUD_PLL_USER_T 12 -#define CLK_MOUT_MPHY_PLL_USER 13 -#define CLK_MOUT_MFC_PLL_USER 14 -#define CLK_MOUT_BUS_PLL_USER 15 -#define CLK_MOUT_ACLK_HEVC_400 16 -#define CLK_MOUT_ACLK_CAM1_333 17 -#define CLK_MOUT_ACLK_CAM1_552_B 18 -#define CLK_MOUT_ACLK_CAM1_552_A 19 -#define CLK_MOUT_ACLK_ISP_DIS_400 20 -#define CLK_MOUT_ACLK_ISP_400 21 -#define CLK_MOUT_ACLK_BUS0_400 22 -#define CLK_MOUT_ACLK_MSCL_400_B 23 -#define CLK_MOUT_ACLK_MSCL_400_A 24 -#define CLK_MOUT_ACLK_GSCL_333 25 -#define CLK_MOUT_ACLK_G2D_400_B 26 -#define CLK_MOUT_ACLK_G2D_400_A 27 -#define CLK_MOUT_SCLK_JPEG_C 28 -#define CLK_MOUT_SCLK_JPEG_B 29 -#define CLK_MOUT_SCLK_JPEG_A 30 -#define CLK_MOUT_SCLK_MMC2_B 31 -#define CLK_MOUT_SCLK_MMC2_A 32 -#define CLK_MOUT_SCLK_MMC1_B 33 -#define CLK_MOUT_SCLK_MMC1_A 34 -#define CLK_MOUT_SCLK_MMC0_D 35 -#define CLK_MOUT_SCLK_MMC0_C 36 -#define CLK_MOUT_SCLK_MMC0_B 37 -#define CLK_MOUT_SCLK_MMC0_A 38 -#define CLK_MOUT_SCLK_SPI4 39 -#define CLK_MOUT_SCLK_SPI3 40 -#define CLK_MOUT_SCLK_UART2 41 -#define CLK_MOUT_SCLK_UART1 42 -#define CLK_MOUT_SCLK_UART0 43 -#define CLK_MOUT_SCLK_SPI2 44 -#define CLK_MOUT_SCLK_SPI1 45 -#define CLK_MOUT_SCLK_SPI0 46 -#define CLK_MOUT_ACLK_MFC_400_C 47 -#define CLK_MOUT_ACLK_MFC_400_B 48 -#define CLK_MOUT_ACLK_MFC_400_A 49 -#define CLK_MOUT_SCLK_ISP_SENSOR2 50 -#define CLK_MOUT_SCLK_ISP_SENSOR1 51 -#define CLK_MOUT_SCLK_ISP_SENSOR0 52 -#define CLK_MOUT_SCLK_ISP_UART 53 -#define CLK_MOUT_SCLK_ISP_SPI1 54 -#define CLK_MOUT_SCLK_ISP_SPI0 55 -#define CLK_MOUT_SCLK_PCIE_100 56 -#define CLK_MOUT_SCLK_UFSUNIPRO 57 -#define CLK_MOUT_SCLK_USBHOST30 58 -#define CLK_MOUT_SCLK_USBDRD30 59 -#define CLK_MOUT_SCLK_SLIMBUS 60 -#define CLK_MOUT_SCLK_SPDIF 61 -#define CLK_MOUT_SCLK_AUDIO1 62 -#define CLK_MOUT_SCLK_AUDIO0 63 -#define CLK_MOUT_SCLK_HDMI_SPDIF 64 - -#define CLK_DIV_ACLK_FSYS_200 100 -#define CLK_DIV_ACLK_IMEM_SSSX_266 101 -#define CLK_DIV_ACLK_IMEM_200 102 -#define CLK_DIV_ACLK_IMEM_266 103 -#define CLK_DIV_ACLK_PERIC_66_B 104 -#define CLK_DIV_ACLK_PERIC_66_A 105 -#define CLK_DIV_ACLK_PERIS_66_B 106 -#define CLK_DIV_ACLK_PERIS_66_A 107 -#define CLK_DIV_SCLK_MMC1_B 108 -#define CLK_DIV_SCLK_MMC1_A 109 -#define CLK_DIV_SCLK_MMC0_B 110 -#define CLK_DIV_SCLK_MMC0_A 111 -#define CLK_DIV_SCLK_MMC2_B 112 -#define CLK_DIV_SCLK_MMC2_A 113 -#define CLK_DIV_SCLK_SPI1_B 114 -#define CLK_DIV_SCLK_SPI1_A 115 -#define CLK_DIV_SCLK_SPI0_B 116 -#define CLK_DIV_SCLK_SPI0_A 117 -#define CLK_DIV_SCLK_SPI2_B 118 -#define CLK_DIV_SCLK_SPI2_A 119 -#define CLK_DIV_SCLK_UART2 120 -#define CLK_DIV_SCLK_UART1 121 -#define CLK_DIV_SCLK_UART0 122 -#define CLK_DIV_SCLK_SPI4_B 123 -#define CLK_DIV_SCLK_SPI4_A 124 -#define CLK_DIV_SCLK_SPI3_B 125 -#define CLK_DIV_SCLK_SPI3_A 126 -#define CLK_DIV_SCLK_I2S1 127 -#define CLK_DIV_SCLK_PCM1 128 -#define CLK_DIV_SCLK_AUDIO1 129 -#define CLK_DIV_SCLK_AUDIO0 130 -#define CLK_DIV_ACLK_GSCL_111 131 -#define CLK_DIV_ACLK_GSCL_333 132 -#define CLK_DIV_ACLK_HEVC_400 133 -#define CLK_DIV_ACLK_MFC_400 134 -#define CLK_DIV_ACLK_G2D_266 135 -#define CLK_DIV_ACLK_G2D_400 136 -#define CLK_DIV_ACLK_G3D_400 137 -#define CLK_DIV_ACLK_BUS0_400 138 -#define CLK_DIV_ACLK_BUS1_400 139 -#define CLK_DIV_SCLK_PCIE_100 140 -#define CLK_DIV_SCLK_USBHOST30 141 -#define CLK_DIV_SCLK_UFSUNIPRO 142 -#define CLK_DIV_SCLK_USBDRD30 143 -#define CLK_DIV_SCLK_JPEG 144 -#define CLK_DIV_ACLK_MSCL_400 145 -#define CLK_DIV_ACLK_ISP_DIS_400 146 -#define CLK_DIV_ACLK_ISP_400 147 -#define CLK_DIV_ACLK_CAM0_333 148 -#define CLK_DIV_ACLK_CAM0_400 149 -#define CLK_DIV_ACLK_CAM0_552 150 -#define CLK_DIV_ACLK_CAM1_333 151 -#define CLK_DIV_ACLK_CAM1_400 152 -#define CLK_DIV_ACLK_CAM1_552 153 -#define CLK_DIV_SCLK_ISP_UART 154 -#define CLK_DIV_SCLK_ISP_SPI1_B 155 -#define CLK_DIV_SCLK_ISP_SPI1_A 156 -#define CLK_DIV_SCLK_ISP_SPI0_B 157 -#define CLK_DIV_SCLK_ISP_SPI0_A 158 -#define CLK_DIV_SCLK_ISP_SENSOR2_B 159 -#define CLK_DIV_SCLK_ISP_SENSOR2_A 160 -#define CLK_DIV_SCLK_ISP_SENSOR1_B 161 -#define CLK_DIV_SCLK_ISP_SENSOR1_A 162 -#define CLK_DIV_SCLK_ISP_SENSOR0_B 163 -#define CLK_DIV_SCLK_ISP_SENSOR0_A 164 - -#define CLK_ACLK_PERIC_66 200 -#define CLK_ACLK_PERIS_66 201 -#define CLK_ACLK_FSYS_200 202 -#define CLK_SCLK_MMC2_FSYS 203 -#define CLK_SCLK_MMC1_FSYS 204 -#define CLK_SCLK_MMC0_FSYS 205 -#define CLK_SCLK_SPI4_PERIC 206 -#define CLK_SCLK_SPI3_PERIC 207 -#define CLK_SCLK_UART2_PERIC 208 -#define CLK_SCLK_UART1_PERIC 209 -#define CLK_SCLK_UART0_PERIC 210 -#define CLK_SCLK_SPI2_PERIC 211 -#define CLK_SCLK_SPI1_PERIC 212 -#define CLK_SCLK_SPI0_PERIC 213 -#define CLK_SCLK_SPDIF_PERIC 214 -#define CLK_SCLK_I2S1_PERIC 215 -#define CLK_SCLK_PCM1_PERIC 216 -#define CLK_SCLK_SLIMBUS 217 -#define CLK_SCLK_AUDIO1 218 -#define CLK_SCLK_AUDIO0 219 -#define CLK_ACLK_G2D_266 220 -#define CLK_ACLK_G2D_400 221 -#define CLK_ACLK_G3D_400 222 -#define CLK_ACLK_IMEM_SSSX_266 223 -#define CLK_ACLK_BUS0_400 224 -#define CLK_ACLK_BUS1_400 225 -#define CLK_ACLK_IMEM_200 226 -#define CLK_ACLK_IMEM_266 227 -#define CLK_SCLK_PCIE_100_FSYS 228 -#define CLK_SCLK_UFSUNIPRO_FSYS 229 -#define CLK_SCLK_USBHOST30_FSYS 230 -#define CLK_SCLK_USBDRD30_FSYS 231 -#define CLK_ACLK_GSCL_111 232 -#define CLK_ACLK_GSCL_333 233 -#define CLK_SCLK_JPEG_MSCL 234 -#define CLK_ACLK_MSCL_400 235 -#define CLK_ACLK_MFC_400 236 -#define CLK_ACLK_HEVC_400 237 -#define CLK_ACLK_ISP_DIS_400 238 -#define CLK_ACLK_ISP_400 239 -#define CLK_ACLK_CAM0_333 240 -#define CLK_ACLK_CAM0_400 241 -#define CLK_ACLK_CAM0_552 242 -#define CLK_ACLK_CAM1_333 243 -#define CLK_ACLK_CAM1_400 244 -#define CLK_ACLK_CAM1_552 245 -#define CLK_SCLK_ISP_SENSOR2 246 -#define CLK_SCLK_ISP_SENSOR1 247 -#define CLK_SCLK_ISP_SENSOR0 248 -#define CLK_SCLK_ISP_MCTADC_CAM1 249 -#define CLK_SCLK_ISP_UART_CAM1 250 -#define CLK_SCLK_ISP_SPI1_CAM1 251 -#define CLK_SCLK_ISP_SPI0_CAM1 252 -#define CLK_SCLK_HDMI_SPDIF_DISP 253 - -#define TOP_NR_CLK 254 - -/* CMU_CPIF */ -#define CLK_FOUT_MPHY_PLL 1 - -#define CLK_MOUT_MPHY_PLL 2 - -#define CLK_DIV_SCLK_MPHY 10 - -#define CLK_SCLK_MPHY_PLL 11 -#define CLK_SCLK_UFS_MPHY 11 - -#define CPIF_NR_CLK 12 - -/* CMU_MIF */ -#define CLK_FOUT_MEM0_PLL 1 -#define CLK_FOUT_MEM1_PLL 2 -#define CLK_FOUT_BUS_PLL 3 -#define CLK_FOUT_MFC_PLL 4 -#define CLK_DOUT_MFC_PLL 5 -#define CLK_DOUT_BUS_PLL 6 -#define CLK_DOUT_MEM1_PLL 7 -#define CLK_DOUT_MEM0_PLL 8 - -#define CLK_MOUT_MFC_PLL_DIV2 10 -#define CLK_MOUT_BUS_PLL_DIV2 11 -#define CLK_MOUT_MEM1_PLL_DIV2 12 -#define CLK_MOUT_MEM0_PLL_DIV2 13 -#define CLK_MOUT_MFC_PLL 14 -#define CLK_MOUT_BUS_PLL 15 -#define CLK_MOUT_MEM1_PLL 16 -#define CLK_MOUT_MEM0_PLL 17 -#define CLK_MOUT_CLK2X_PHY_C 18 -#define CLK_MOUT_CLK2X_PHY_B 19 -#define CLK_MOUT_CLK2X_PHY_A 20 -#define CLK_MOUT_CLKM_PHY_C 21 -#define CLK_MOUT_CLKM_PHY_B 22 -#define CLK_MOUT_CLKM_PHY_A 23 -#define CLK_MOUT_ACLK_MIFNM_200 24 -#define CLK_MOUT_ACLK_MIFNM_400 25 -#define CLK_MOUT_ACLK_DISP_333_B 26 -#define CLK_MOUT_ACLK_DISP_333_A 27 -#define CLK_MOUT_SCLK_DECON_VCLK_C 28 -#define CLK_MOUT_SCLK_DECON_VCLK_B 29 -#define CLK_MOUT_SCLK_DECON_VCLK_A 30 -#define CLK_MOUT_SCLK_DECON_ECLK_C 31 -#define CLK_MOUT_SCLK_DECON_ECLK_B 32 -#define CLK_MOUT_SCLK_DECON_ECLK_A 33 -#define CLK_MOUT_SCLK_DECON_TV_ECLK_C 34 -#define CLK_MOUT_SCLK_DECON_TV_ECLK_B 35 -#define CLK_MOUT_SCLK_DECON_TV_ECLK_A 36 -#define CLK_MOUT_SCLK_DSD_C 37 -#define CLK_MOUT_SCLK_DSD_B 38 -#define CLK_MOUT_SCLK_DSD_A 39 -#define CLK_MOUT_SCLK_DSIM0_C 40 -#define CLK_MOUT_SCLK_DSIM0_B 41 -#define CLK_MOUT_SCLK_DSIM0_A 42 -#define CLK_MOUT_SCLK_DECON_TV_VCLK_C 46 -#define CLK_MOUT_SCLK_DECON_TV_VCLK_B 47 -#define CLK_MOUT_SCLK_DECON_TV_VCLK_A 48 -#define CLK_MOUT_SCLK_DSIM1_C 49 -#define CLK_MOUT_SCLK_DSIM1_B 50 -#define CLK_MOUT_SCLK_DSIM1_A 51 - -#define CLK_DIV_SCLK_HPM_MIF 55 -#define CLK_DIV_ACLK_DREX1 56 -#define CLK_DIV_ACLK_DREX0 57 -#define CLK_DIV_CLK2XPHY 58 -#define CLK_DIV_ACLK_MIF_266 59 -#define CLK_DIV_ACLK_MIFND_133 60 -#define CLK_DIV_ACLK_MIF_133 61 -#define CLK_DIV_ACLK_MIFNM_200 62 -#define CLK_DIV_ACLK_MIF_200 63 -#define CLK_DIV_ACLK_MIF_400 64 -#define CLK_DIV_ACLK_BUS2_400 65 -#define CLK_DIV_ACLK_DISP_333 66 -#define CLK_DIV_ACLK_CPIF_200 67 -#define CLK_DIV_SCLK_DSIM1 68 -#define CLK_DIV_SCLK_DECON_TV_VCLK 69 -#define CLK_DIV_SCLK_DSIM0 70 -#define CLK_DIV_SCLK_DSD 71 -#define CLK_DIV_SCLK_DECON_TV_ECLK 72 -#define CLK_DIV_SCLK_DECON_VCLK 73 -#define CLK_DIV_SCLK_DECON_ECLK 74 -#define CLK_DIV_MIF_PRE 75 - -#define CLK_CLK2X_PHY1 80 -#define CLK_CLK2X_PHY0 81 -#define CLK_CLKM_PHY1 82 -#define CLK_CLKM_PHY0 83 -#define CLK_RCLK_DREX1 84 -#define CLK_RCLK_DREX0 85 -#define CLK_ACLK_DREX1_TZ 86 -#define CLK_ACLK_DREX0_TZ 87 -#define CLK_ACLK_DREX1_PEREV 88 -#define CLK_ACLK_DREX0_PEREV 89 -#define CLK_ACLK_DREX1_MEMIF 90 -#define CLK_ACLK_DREX0_MEMIF 91 -#define CLK_ACLK_DREX1_SCH 92 -#define CLK_ACLK_DREX0_SCH 93 -#define CLK_ACLK_DREX1_BUSIF 94 -#define CLK_ACLK_DREX0_BUSIF 95 -#define CLK_ACLK_DREX1_BUSIF_RD 96 -#define CLK_ACLK_DREX0_BUSIF_RD 97 -#define CLK_ACLK_DREX1 98 -#define CLK_ACLK_DREX0 99 -#define CLK_ACLK_ASYNCAXIM_ATLAS_CCIX 100 -#define CLK_ACLK_ASYNCAXIS_ATLAS_MIF 101 -#define CLK_ACLK_ASYNCAXIM_ATLAS_MIF 102 -#define CLK_ACLK_ASYNCAXIS_MIF_IMEM 103 -#define CLK_ACLK_ASYNCAXIS_NOC_P_CCI 104 -#define CLK_ACLK_ASYNCAXIM_NOC_P_CCI 105 -#define CLK_ACLK_ASYNCAXIS_CP1 106 -#define CLK_ACLK_ASYNCAXIM_CP1 107 -#define CLK_ACLK_ASYNCAXIS_CP0 108 -#define CLK_ACLK_ASYNCAXIM_CP0 109 -#define CLK_ACLK_ASYNCAXIS_DREX1_3 110 -#define CLK_ACLK_ASYNCAXIM_DREX1_3 111 -#define CLK_ACLK_ASYNCAXIS_DREX1_1 112 -#define CLK_ACLK_ASYNCAXIM_DREX1_1 113 -#define CLK_ACLK_ASYNCAXIS_DREX1_0 114 -#define CLK_ACLK_ASYNCAXIM_DREX1_0 115 -#define CLK_ACLK_ASYNCAXIS_DREX0_3 116 -#define CLK_ACLK_ASYNCAXIM_DREX0_3 117 -#define CLK_ACLK_ASYNCAXIS_DREX0_1 118 -#define CLK_ACLK_ASYNCAXIM_DREX0_1 119 -#define CLK_ACLK_ASYNCAXIS_DREX0_0 120 -#define CLK_ACLK_ASYNCAXIM_DREX0_0 121 -#define CLK_ACLK_AHB2APB_MIF2P 122 -#define CLK_ACLK_AHB2APB_MIF1P 123 -#define CLK_ACLK_AHB2APB_MIF0P 124 -#define CLK_ACLK_IXIU_CCI 125 -#define CLK_ACLK_XIU_MIFSFRX 126 -#define CLK_ACLK_MIFNP_133 127 -#define CLK_ACLK_MIFNM_200 128 -#define CLK_ACLK_MIFND_133 129 -#define CLK_ACLK_MIFND_400 130 -#define CLK_ACLK_CCI 131 -#define CLK_ACLK_MIFND_266 132 -#define CLK_ACLK_PPMU_DREX1S3 133 -#define CLK_ACLK_PPMU_DREX1S1 134 -#define CLK_ACLK_PPMU_DREX1S0 135 -#define CLK_ACLK_PPMU_DREX0S3 136 -#define CLK_ACLK_PPMU_DREX0S1 137 -#define CLK_ACLK_PPMU_DREX0S0 138 -#define CLK_ACLK_BTS_APOLLO 139 -#define CLK_ACLK_BTS_ATLAS 140 -#define CLK_ACLK_ACE_SEL_APOLL 141 -#define CLK_ACLK_ACE_SEL_ATLAS 142 -#define CLK_ACLK_AXIDS_CCI_MIFSFRX 143 -#define CLK_ACLK_AXIUS_ATLAS_CCI 144 -#define CLK_ACLK_AXISYNCDNS_CCI 145 -#define CLK_ACLK_AXISYNCDN_CCI 146 -#define CLK_ACLK_AXISYNCDN_NOC_D 147 -#define CLK_ACLK_ASYNCACEM_APOLLO_CCI 148 -#define CLK_ACLK_ASYNCACEM_ATLAS_CCI 149 -#define CLK_ACLK_ASYNCAPBS_MIF_CSSYS 150 -#define CLK_ACLK_BUS2_400 151 -#define CLK_ACLK_DISP_333 152 -#define CLK_ACLK_CPIF_200 153 -#define CLK_PCLK_PPMU_DREX1S3 154 -#define CLK_PCLK_PPMU_DREX1S1 155 -#define CLK_PCLK_PPMU_DREX1S0 156 -#define CLK_PCLK_PPMU_DREX0S3 157 -#define CLK_PCLK_PPMU_DREX0S1 158 -#define CLK_PCLK_PPMU_DREX0S0 159 -#define CLK_PCLK_BTS_APOLLO 160 -#define CLK_PCLK_BTS_ATLAS 161 -#define CLK_PCLK_ASYNCAXI_NOC_P_CCI 162 -#define CLK_PCLK_ASYNCAXI_CP1 163 -#define CLK_PCLK_ASYNCAXI_CP0 164 -#define CLK_PCLK_ASYNCAXI_DREX1_3 165 -#define CLK_PCLK_ASYNCAXI_DREX1_1 166 -#define CLK_PCLK_ASYNCAXI_DREX1_0 167 -#define CLK_PCLK_ASYNCAXI_DREX0_3 168 -#define CLK_PCLK_ASYNCAXI_DREX0_1 169 -#define CLK_PCLK_ASYNCAXI_DREX0_0 170 -#define CLK_PCLK_MIFSRVND_133 171 -#define CLK_PCLK_PMU_MIF 172 -#define CLK_PCLK_SYSREG_MIF 173 -#define CLK_PCLK_GPIO_ALIVE 174 -#define CLK_PCLK_ABB 175 -#define CLK_PCLK_PMU_APBIF 176 -#define CLK_PCLK_DDR_PHY1 177 -#define CLK_PCLK_DREX1 178 -#define CLK_PCLK_DDR_PHY0 179 -#define CLK_PCLK_DREX0 180 -#define CLK_PCLK_DREX0_TZ 181 -#define CLK_PCLK_DREX1_TZ 182 -#define CLK_PCLK_MONOTONIC_CNT 183 -#define CLK_PCLK_RTC 184 -#define CLK_SCLK_DSIM1_DISP 185 -#define CLK_SCLK_DECON_TV_VCLK_DISP 186 -#define CLK_SCLK_FREQ_DET_BUS_PLL 187 -#define CLK_SCLK_FREQ_DET_MFC_PLL 188 -#define CLK_SCLK_FREQ_DET_MEM0_PLL 189 -#define CLK_SCLK_FREQ_DET_MEM1_PLL 190 -#define CLK_SCLK_DSIM0_DISP 191 -#define CLK_SCLK_DSD_DISP 192 -#define CLK_SCLK_DECON_TV_ECLK_DISP 193 -#define CLK_SCLK_DECON_VCLK_DISP 194 -#define CLK_SCLK_DECON_ECLK_DISP 195 -#define CLK_SCLK_HPM_MIF 196 -#define CLK_SCLK_MFC_PLL 197 -#define CLK_SCLK_BUS_PLL 198 -#define CLK_SCLK_BUS_PLL_APOLLO 199 -#define CLK_SCLK_BUS_PLL_ATLAS 200 - -#define MIF_NR_CLK 201 - -/* CMU_PERIC */ -#define CLK_PCLK_SPI2 1 -#define CLK_PCLK_SPI1 2 -#define CLK_PCLK_SPI0 3 -#define CLK_PCLK_UART2 4 -#define CLK_PCLK_UART1 5 -#define CLK_PCLK_UART0 6 -#define CLK_PCLK_HSI2C3 7 -#define CLK_PCLK_HSI2C2 8 -#define CLK_PCLK_HSI2C1 9 -#define CLK_PCLK_HSI2C0 10 -#define CLK_PCLK_I2C7 11 -#define CLK_PCLK_I2C6 12 -#define CLK_PCLK_I2C5 13 -#define CLK_PCLK_I2C4 14 -#define CLK_PCLK_I2C3 15 -#define CLK_PCLK_I2C2 16 -#define CLK_PCLK_I2C1 17 -#define CLK_PCLK_I2C0 18 -#define CLK_PCLK_SPI4 19 -#define CLK_PCLK_SPI3 20 -#define CLK_PCLK_HSI2C11 21 -#define CLK_PCLK_HSI2C10 22 -#define CLK_PCLK_HSI2C9 23 -#define CLK_PCLK_HSI2C8 24 -#define CLK_PCLK_HSI2C7 25 -#define CLK_PCLK_HSI2C6 26 -#define CLK_PCLK_HSI2C5 27 -#define CLK_PCLK_HSI2C4 28 -#define CLK_SCLK_SPI4 29 -#define CLK_SCLK_SPI3 30 -#define CLK_SCLK_SPI2 31 -#define CLK_SCLK_SPI1 32 -#define CLK_SCLK_SPI0 33 -#define CLK_SCLK_UART2 34 -#define CLK_SCLK_UART1 35 -#define CLK_SCLK_UART0 36 -#define CLK_ACLK_AHB2APB_PERIC2P 37 -#define CLK_ACLK_AHB2APB_PERIC1P 38 -#define CLK_ACLK_AHB2APB_PERIC0P 39 -#define CLK_ACLK_PERICNP_66 40 -#define CLK_PCLK_SCI 41 -#define CLK_PCLK_GPIO_FINGER 42 -#define CLK_PCLK_GPIO_ESE 43 -#define CLK_PCLK_PWM 44 -#define CLK_PCLK_SPDIF 45 -#define CLK_PCLK_PCM1 46 -#define CLK_PCLK_I2S1 47 -#define CLK_PCLK_ADCIF 48 -#define CLK_PCLK_GPIO_TOUCH 49 -#define CLK_PCLK_GPIO_NFC 50 -#define CLK_PCLK_GPIO_PERIC 51 -#define CLK_PCLK_PMU_PERIC 52 -#define CLK_PCLK_SYSREG_PERIC 53 -#define CLK_SCLK_IOCLK_SPI4 54 -#define CLK_SCLK_IOCLK_SPI3 55 -#define CLK_SCLK_SCI 56 -#define CLK_SCLK_SC_IN 57 -#define CLK_SCLK_PWM 58 -#define CLK_SCLK_IOCLK_SPI2 59 -#define CLK_SCLK_IOCLK_SPI1 60 -#define CLK_SCLK_IOCLK_SPI0 61 -#define CLK_SCLK_IOCLK_I2S1_BCLK 62 -#define CLK_SCLK_SPDIF 63 -#define CLK_SCLK_PCM1 64 -#define CLK_SCLK_I2S1 65 - -#define CLK_DIV_SCLK_SCI 70 -#define CLK_DIV_SCLK_SC_IN 71 - -#define PERIC_NR_CLK 72 - -/* CMU_PERIS */ -#define CLK_PCLK_HPM_APBIF 1 -#define CLK_PCLK_TMU1_APBIF 2 -#define CLK_PCLK_TMU0_APBIF 3 -#define CLK_PCLK_PMU_PERIS 4 -#define CLK_PCLK_SYSREG_PERIS 5 -#define CLK_PCLK_CMU_TOP_APBIF 6 -#define CLK_PCLK_WDT_APOLLO 7 -#define CLK_PCLK_WDT_ATLAS 8 -#define CLK_PCLK_MCT 9 -#define CLK_PCLK_HDMI_CEC 10 -#define CLK_ACLK_AHB2APB_PERIS1P 11 -#define CLK_ACLK_AHB2APB_PERIS0P 12 -#define CLK_ACLK_PERISNP_66 13 -#define CLK_PCLK_TZPC12 14 -#define CLK_PCLK_TZPC11 15 -#define CLK_PCLK_TZPC10 16 -#define CLK_PCLK_TZPC9 17 -#define CLK_PCLK_TZPC8 18 -#define CLK_PCLK_TZPC7 19 -#define CLK_PCLK_TZPC6 20 -#define CLK_PCLK_TZPC5 21 -#define CLK_PCLK_TZPC4 22 -#define CLK_PCLK_TZPC3 23 -#define CLK_PCLK_TZPC2 24 -#define CLK_PCLK_TZPC1 25 -#define CLK_PCLK_TZPC0 26 -#define CLK_PCLK_SECKEY_APBIF 27 -#define CLK_PCLK_CHIPID_APBIF 28 -#define CLK_PCLK_TOPRTC 29 -#define CLK_PCLK_CUSTOM_EFUSE_APBIF 30 -#define CLK_PCLK_ANTIRBK_CNT_APBIF 31 -#define CLK_PCLK_OTP_CON_APBIF 32 -#define CLK_SCLK_ASV_TB 33 -#define CLK_SCLK_TMU1 34 -#define CLK_SCLK_TMU0 35 -#define CLK_SCLK_SECKEY 36 -#define CLK_SCLK_CHIPID 37 -#define CLK_SCLK_TOPRTC 38 -#define CLK_SCLK_CUSTOM_EFUSE 39 -#define CLK_SCLK_ANTIRBK_CNT 40 -#define CLK_SCLK_OTP_CON 41 - -#define PERIS_NR_CLK 42 - -/* CMU_FSYS */ -#define CLK_MOUT_ACLK_FSYS_200_USER 1 -#define CLK_MOUT_SCLK_MMC2_USER 2 -#define CLK_MOUT_SCLK_MMC1_USER 3 -#define CLK_MOUT_SCLK_MMC0_USER 4 -#define CLK_MOUT_SCLK_UFS_MPHY_USER 5 -#define CLK_MOUT_SCLK_PCIE_100_USER 6 -#define CLK_MOUT_SCLK_UFSUNIPRO_USER 7 -#define CLK_MOUT_SCLK_USBHOST30_USER 8 -#define CLK_MOUT_SCLK_USBDRD30_USER 9 -#define CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER 10 -#define CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER 11 -#define CLK_MOUT_PHYCLK_USBHOST20_PHY_HSIC1_USER 12 -#define CLK_MOUT_PHYCLK_USBHOST20_PHY_CLK48MOHCI_USER 13 -#define CLK_MOUT_PHYCLK_USBHOST20_PHY_PHYCLOCK_USER 14 -#define CLK_MOUT_PHYCLK_USBHOST20_PHY_PHY_FREECLK_USER 15 -#define CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER 16 -#define CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER 17 -#define CLK_MOUT_PHYCLK_UFS_RX1_SYMBOL_USER 18 -#define CLK_MOUT_PHYCLK_UFS_RX0_SYMBOL_USER 19 -#define CLK_MOUT_PHYCLK_UFS_TX1_SYMBOL_USER 20 -#define CLK_MOUT_PHYCLK_UFS_TX0_SYMBOL_USER 21 -#define CLK_MOUT_PHYCLK_LLI_MPHY_TO_UFS_USER 22 -#define CLK_MOUT_SCLK_MPHY 23 - -#define CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY 25 -#define CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY 26 -#define CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY 27 -#define CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY 28 -#define CLK_PHYCLK_USBHOST20_PHY_FREECLK_PHY 29 -#define CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK_PHY 30 -#define CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI_PHY 31 -#define CLK_PHYCLK_USBHOST20_PHY_HSIC1_PHY 32 -#define CLK_PHYCLK_UFS_TX0_SYMBOL_PHY 33 -#define CLK_PHYCLK_UFS_RX0_SYMBOL_PHY 34 -#define CLK_PHYCLK_UFS_TX1_SYMBOL_PHY 35 -#define CLK_PHYCLK_UFS_RX1_SYMBOL_PHY 36 -#define CLK_PHYCLK_LLI_MPHY_TO_UFS_PHY 37 - -#define CLK_ACLK_PCIE 50 -#define CLK_ACLK_PDMA1 51 -#define CLK_ACLK_TSI 52 -#define CLK_ACLK_MMC2 53 -#define CLK_ACLK_MMC1 54 -#define CLK_ACLK_MMC0 55 -#define CLK_ACLK_UFS 56 -#define CLK_ACLK_USBHOST20 57 -#define CLK_ACLK_USBHOST30 58 -#define CLK_ACLK_USBDRD30 59 -#define CLK_ACLK_PDMA0 60 -#define CLK_SCLK_MMC2 61 -#define CLK_SCLK_MMC1 62 -#define CLK_SCLK_MMC0 63 -#define CLK_PDMA1 64 -#define CLK_PDMA0 65 -#define CLK_ACLK_XIU_FSYSPX 66 -#define CLK_ACLK_AHB_USBLINKH1 67 -#define CLK_ACLK_SMMU_PDMA1 68 -#define CLK_ACLK_BTS_PCIE 69 -#define CLK_ACLK_AXIUS_PDMA1 70 -#define CLK_ACLK_SMMU_PDMA0 71 -#define CLK_ACLK_BTS_UFS 72 -#define CLK_ACLK_BTS_USBHOST30 73 -#define CLK_ACLK_BTS_USBDRD30 74 -#define CLK_ACLK_AXIUS_PDMA0 75 -#define CLK_ACLK_AXIUS_USBHS 76 -#define CLK_ACLK_AXIUS_FSYSSX 77 -#define CLK_ACLK_AHB2APB_FSYSP 78 -#define CLK_ACLK_AHB2AXI_USBHS 79 -#define CLK_ACLK_AHB_USBLINKH0 80 -#define CLK_ACLK_AHB_USBHS 81 -#define CLK_ACLK_AHB_FSYSH 82 -#define CLK_ACLK_XIU_FSYSX 83 -#define CLK_ACLK_XIU_FSYSSX 84 -#define CLK_ACLK_FSYSNP_200 85 -#define CLK_ACLK_FSYSND_200 86 -#define CLK_PCLK_PCIE_CTRL 87 -#define CLK_PCLK_SMMU_PDMA1 88 -#define CLK_PCLK_PCIE_PHY 89 -#define CLK_PCLK_BTS_PCIE 90 -#define CLK_PCLK_SMMU_PDMA0 91 -#define CLK_PCLK_BTS_UFS 92 -#define CLK_PCLK_BTS_USBHOST30 93 -#define CLK_PCLK_BTS_USBDRD30 94 -#define CLK_PCLK_GPIO_FSYS 95 -#define CLK_PCLK_PMU_FSYS 96 -#define CLK_PCLK_SYSREG_FSYS 97 -#define CLK_SCLK_PCIE_100 98 -#define CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK 99 -#define CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK 100 -#define CLK_PHYCLK_UFS_RX1_SYMBOL 101 -#define CLK_PHYCLK_UFS_RX0_SYMBOL 102 -#define CLK_PHYCLK_UFS_TX1_SYMBOL 103 -#define CLK_PHYCLK_UFS_TX0_SYMBOL 104 -#define CLK_PHYCLK_USBHOST20_PHY_HSIC1 105 -#define CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI 106 -#define CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK 107 -#define CLK_PHYCLK_USBHOST20_PHY_FREECLK 108 -#define CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK 109 -#define CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK 110 -#define CLK_SCLK_MPHY 111 -#define CLK_SCLK_UFSUNIPRO 112 -#define CLK_SCLK_USBHOST30 113 -#define CLK_SCLK_USBDRD30 114 -#define CLK_PCIE 115 - -#define FSYS_NR_CLK 116 - -/* CMU_G2D */ -#define CLK_MUX_ACLK_G2D_266_USER 1 -#define CLK_MUX_ACLK_G2D_400_USER 2 - -#define CLK_DIV_PCLK_G2D 3 - -#define CLK_ACLK_SMMU_MDMA1 4 -#define CLK_ACLK_BTS_MDMA1 5 -#define CLK_ACLK_BTS_G2D 6 -#define CLK_ACLK_ALB_G2D 7 -#define CLK_ACLK_AXIUS_G2DX 8 -#define CLK_ACLK_ASYNCAXI_SYSX 9 -#define CLK_ACLK_AHB2APB_G2D1P 10 -#define CLK_ACLK_AHB2APB_G2D0P 11 -#define CLK_ACLK_XIU_G2DX 12 -#define CLK_ACLK_G2DNP_133 13 -#define CLK_ACLK_G2DND_400 14 -#define CLK_ACLK_MDMA1 15 -#define CLK_ACLK_G2D 16 -#define CLK_ACLK_SMMU_G2D 17 -#define CLK_PCLK_SMMU_MDMA1 18 -#define CLK_PCLK_BTS_MDMA1 19 -#define CLK_PCLK_BTS_G2D 20 -#define CLK_PCLK_ALB_G2D 21 -#define CLK_PCLK_ASYNCAXI_SYSX 22 -#define CLK_PCLK_PMU_G2D 23 -#define CLK_PCLK_SYSREG_G2D 24 -#define CLK_PCLK_G2D 25 -#define CLK_PCLK_SMMU_G2D 26 - -#define G2D_NR_CLK 27 - -/* CMU_DISP */ -#define CLK_FOUT_DISP_PLL 1 - -#define CLK_MOUT_DISP_PLL 2 -#define CLK_MOUT_SCLK_DSIM1_USER 3 -#define CLK_MOUT_SCLK_DSIM0_USER 4 -#define CLK_MOUT_SCLK_DSD_USER 5 -#define CLK_MOUT_SCLK_DECON_TV_ECLK_USER 6 -#define CLK_MOUT_SCLK_DECON_VCLK_USER 7 -#define CLK_MOUT_SCLK_DECON_ECLK_USER 8 -#define CLK_MOUT_SCLK_DECON_TV_VCLK_USER 9 -#define CLK_MOUT_ACLK_DISP_333_USER 10 -#define CLK_MOUT_PHYCLK_MIPIDPHY1_BITCLKDIV8_USER 11 -#define CLK_MOUT_PHYCLK_MIPIDPHY1_RXCLKESC0_USER 12 -#define CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER 13 -#define CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER 14 -#define CLK_MOUT_PHYCLK_HDMIPHY_TMDS_CLKO_USER 15 -#define CLK_MOUT_PHYCLK_HDMIPHY_PIXEL_CLKO_USER 16 -#define CLK_MOUT_SCLK_DSIM0 17 -#define CLK_MOUT_SCLK_DECON_TV_ECLK 18 -#define CLK_MOUT_SCLK_DECON_VCLK 19 -#define CLK_MOUT_SCLK_DECON_ECLK 20 -#define CLK_MOUT_SCLK_DSIM1_B_DISP 21 -#define CLK_MOUT_SCLK_DSIM1_A_DISP 22 -#define CLK_MOUT_SCLK_DECON_TV_VCLK_C_DISP 23 -#define CLK_MOUT_SCLK_DECON_TV_VCLK_B_DISP 24 -#define CLK_MOUT_SCLK_DECON_TV_VCLK_A_DISP 25 - -#define CLK_DIV_SCLK_DSIM1_DISP 30 -#define CLK_DIV_SCLK_DECON_TV_VCLK_DISP 31 -#define CLK_DIV_SCLK_DSIM0_DISP 32 -#define CLK_DIV_SCLK_DECON_TV_ECLK_DISP 33 -#define CLK_DIV_SCLK_DECON_VCLK_DISP 34 -#define CLK_DIV_SCLK_DECON_ECLK_DISP 35 -#define CLK_DIV_PCLK_DISP 36 - -#define CLK_ACLK_DECON_TV 40 -#define CLK_ACLK_DECON 41 -#define CLK_ACLK_SMMU_TV1X 42 -#define CLK_ACLK_SMMU_TV0X 43 -#define CLK_ACLK_SMMU_DECON1X 44 -#define CLK_ACLK_SMMU_DECON0X 45 -#define CLK_ACLK_BTS_DECON_TV_M3 46 -#define CLK_ACLK_BTS_DECON_TV_M2 47 -#define CLK_ACLK_BTS_DECON_TV_M1 48 -#define CLK_ACLK_BTS_DECON_TV_M0 49 -#define CLK_ACLK_BTS_DECON_NM4 50 -#define CLK_ACLK_BTS_DECON_NM3 51 -#define CLK_ACLK_BTS_DECON_NM2 52 -#define CLK_ACLK_BTS_DECON_NM1 53 -#define CLK_ACLK_BTS_DECON_NM0 54 -#define CLK_ACLK_AHB2APB_DISPSFR2P 55 -#define CLK_ACLK_AHB2APB_DISPSFR1P 56 -#define CLK_ACLK_AHB2APB_DISPSFR0P 57 -#define CLK_ACLK_AHB_DISPH 58 -#define CLK_ACLK_XIU_TV1X 59 -#define CLK_ACLK_XIU_TV0X 60 -#define CLK_ACLK_XIU_DECON1X 61 -#define CLK_ACLK_XIU_DECON0X 62 -#define CLK_ACLK_XIU_DISP1X 63 -#define CLK_ACLK_XIU_DISPNP_100 64 -#define CLK_ACLK_DISP1ND_333 65 -#define CLK_ACLK_DISP0ND_333 66 -#define CLK_PCLK_SMMU_TV1X 67 -#define CLK_PCLK_SMMU_TV0X 68 -#define CLK_PCLK_SMMU_DECON1X 69 -#define CLK_PCLK_SMMU_DECON0X 70 -#define CLK_PCLK_BTS_DECON_TV_M3 71 -#define CLK_PCLK_BTS_DECON_TV_M2 72 -#define CLK_PCLK_BTS_DECON_TV_M1 73 -#define CLK_PCLK_BTS_DECON_TV_M0 74 -#define CLK_PCLK_BTS_DECONM4 75 -#define CLK_PCLK_BTS_DECONM3 76 -#define CLK_PCLK_BTS_DECONM2 77 -#define CLK_PCLK_BTS_DECONM1 78 -#define CLK_PCLK_BTS_DECONM0 79 -#define CLK_PCLK_MIC1 80 -#define CLK_PCLK_PMU_DISP 81 -#define CLK_PCLK_SYSREG_DISP 82 -#define CLK_PCLK_HDMIPHY 83 -#define CLK_PCLK_HDMI 84 -#define CLK_PCLK_MIC0 85 -#define CLK_PCLK_DSIM1 86 -#define CLK_PCLK_DSIM0 87 -#define CLK_PCLK_DECON_TV 88 -#define CLK_PHYCLK_MIPIDPHY1_BITCLKDIV8 89 -#define CLK_PHYCLK_MIPIDPHY1_RXCLKESC0 90 -#define CLK_SCLK_RGB_TV_VCLK_TO_DSIM1 91 -#define CLK_SCLK_RGB_TV_VCLK_TO_MIC1 92 -#define CLK_SCLK_DSIM1 93 -#define CLK_SCLK_DECON_TV_VCLK 94 -#define CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8 95 -#define CLK_PHYCLK_MIPIDPHY0_RXCLKESC0 96 -#define CLK_PHYCLK_HDMIPHY_TMDS_CLKO 97 -#define CLK_PHYCLK_HDMI_PIXEL 98 -#define CLK_SCLK_RGB_VCLK_TO_SMIES 99 -#define CLK_SCLK_FREQ_DET_DISP_PLL 100 -#define CLK_SCLK_RGB_VCLK_TO_DSIM0 101 -#define CLK_SCLK_RGB_VCLK_TO_MIC0 102 -#define CLK_SCLK_DSD 103 -#define CLK_SCLK_HDMI_SPDIF 104 -#define CLK_SCLK_DSIM0 105 -#define CLK_SCLK_DECON_TV_ECLK 106 -#define CLK_SCLK_DECON_VCLK 107 -#define CLK_SCLK_DECON_ECLK 108 -#define CLK_SCLK_RGB_VCLK 109 -#define CLK_SCLK_RGB_TV_VCLK 110 - -#define CLK_PHYCLK_HDMIPHY_PIXEL_CLKO_PHY 111 -#define CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY 112 - -#define CLK_PCLK_DECON 113 - -#define CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY 114 -#define CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY 115 - -#define DISP_NR_CLK 116 - -/* CMU_AUD */ -#define CLK_MOUT_AUD_PLL_USER 1 -#define CLK_MOUT_SCLK_AUD_PCM 2 -#define CLK_MOUT_SCLK_AUD_I2S 3 - -#define CLK_DIV_ATCLK_AUD 4 -#define CLK_DIV_PCLK_DBG_AUD 5 -#define CLK_DIV_ACLK_AUD 6 -#define CLK_DIV_AUD_CA5 7 -#define CLK_DIV_SCLK_AUD_SLIMBUS 8 -#define CLK_DIV_SCLK_AUD_UART 9 -#define CLK_DIV_SCLK_AUD_PCM 10 -#define CLK_DIV_SCLK_AUD_I2S 11 - -#define CLK_ACLK_INTR_CTRL 12 -#define CLK_ACLK_AXIDS2_LPASSP 13 -#define CLK_ACLK_AXIDS1_LPASSP 14 -#define CLK_ACLK_AXI2APB1_LPASSP 15 -#define CLK_ACLK_AXI2APH_LPASSP 16 -#define CLK_ACLK_SMMU_LPASSX 17 -#define CLK_ACLK_AXIDS0_LPASSP 18 -#define CLK_ACLK_AXI2APB0_LPASSP 19 -#define CLK_ACLK_XIU_LPASSX 20 -#define CLK_ACLK_AUDNP_133 21 -#define CLK_ACLK_AUDND_133 22 -#define CLK_ACLK_SRAMC 23 -#define CLK_ACLK_DMAC 24 -#define CLK_PCLK_WDT1 25 -#define CLK_PCLK_WDT0 26 -#define CLK_PCLK_SFR1 27 -#define CLK_PCLK_SMMU_LPASSX 28 -#define CLK_PCLK_GPIO_AUD 29 -#define CLK_PCLK_PMU_AUD 30 -#define CLK_PCLK_SYSREG_AUD 31 -#define CLK_PCLK_AUD_SLIMBUS 32 -#define CLK_PCLK_AUD_UART 33 -#define CLK_PCLK_AUD_PCM 34 -#define CLK_PCLK_AUD_I2S 35 -#define CLK_PCLK_TIMER 36 -#define CLK_PCLK_SFR0_CTRL 37 -#define CLK_ATCLK_AUD 38 -#define CLK_PCLK_DBG_AUD 39 -#define CLK_SCLK_AUD_CA5 40 -#define CLK_SCLK_JTAG_TCK 41 -#define CLK_SCLK_SLIMBUS_CLKIN 42 -#define CLK_SCLK_AUD_SLIMBUS 43 -#define CLK_SCLK_AUD_UART 44 -#define CLK_SCLK_AUD_PCM 45 -#define CLK_SCLK_I2S_BCLK 46 -#define CLK_SCLK_AUD_I2S 47 - -#define AUD_NR_CLK 48 - -/* CMU_BUS{0|1|2} */ -#define CLK_DIV_PCLK_BUS_133 1 - -#define CLK_ACLK_AHB2APB_BUSP 2 -#define CLK_ACLK_BUSNP_133 3 -#define CLK_ACLK_BUSND_400 4 -#define CLK_PCLK_BUSSRVND_133 5 -#define CLK_PCLK_PMU_BUS 6 -#define CLK_PCLK_SYSREG_BUS 7 - -#define CLK_MOUT_ACLK_BUS2_400_USER 8 /* Only CMU_BUS2 */ -#define CLK_ACLK_BUS2BEND_400 9 /* Only CMU_BUS2 */ -#define CLK_ACLK_BUS2RTND_400 10 /* Only CMU_BUS2 */ - -#define BUSx_NR_CLK 11 - -/* CMU_G3D */ -#define CLK_FOUT_G3D_PLL 1 - -#define CLK_MOUT_ACLK_G3D_400 2 -#define CLK_MOUT_G3D_PLL 3 - -#define CLK_DIV_SCLK_HPM_G3D 4 -#define CLK_DIV_PCLK_G3D 5 -#define CLK_DIV_ACLK_G3D 6 -#define CLK_ACLK_BTS_G3D1 7 -#define CLK_ACLK_BTS_G3D0 8 -#define CLK_ACLK_ASYNCAPBS_G3D 9 -#define CLK_ACLK_ASYNCAPBM_G3D 10 -#define CLK_ACLK_AHB2APB_G3DP 11 -#define CLK_ACLK_G3DNP_150 12 -#define CLK_ACLK_G3DND_600 13 -#define CLK_ACLK_G3D 14 -#define CLK_PCLK_BTS_G3D1 15 -#define CLK_PCLK_BTS_G3D0 16 -#define CLK_PCLK_PMU_G3D 17 -#define CLK_PCLK_SYSREG_G3D 18 -#define CLK_SCLK_HPM_G3D 19 - -#define G3D_NR_CLK 20 - -/* CMU_GSCL */ -#define CLK_MOUT_ACLK_GSCL_111_USER 1 -#define CLK_MOUT_ACLK_GSCL_333_USER 2 - -#define CLK_ACLK_BTS_GSCL2 3 -#define CLK_ACLK_BTS_GSCL1 4 -#define CLK_ACLK_BTS_GSCL0 5 -#define CLK_ACLK_AHB2APB_GSCLP 6 -#define CLK_ACLK_XIU_GSCLX 7 -#define CLK_ACLK_GSCLNP_111 8 -#define CLK_ACLK_GSCLRTND_333 9 -#define CLK_ACLK_GSCLBEND_333 10 -#define CLK_ACLK_GSD 11 -#define CLK_ACLK_GSCL2 12 -#define CLK_ACLK_GSCL1 13 -#define CLK_ACLK_GSCL0 14 -#define CLK_ACLK_SMMU_GSCL0 15 -#define CLK_ACLK_SMMU_GSCL1 16 -#define CLK_ACLK_SMMU_GSCL2 17 -#define CLK_PCLK_BTS_GSCL2 18 -#define CLK_PCLK_BTS_GSCL1 19 -#define CLK_PCLK_BTS_GSCL0 20 -#define CLK_PCLK_PMU_GSCL 21 -#define CLK_PCLK_SYSREG_GSCL 22 -#define CLK_PCLK_GSCL2 23 -#define CLK_PCLK_GSCL1 24 -#define CLK_PCLK_GSCL0 25 -#define CLK_PCLK_SMMU_GSCL0 26 -#define CLK_PCLK_SMMU_GSCL1 27 -#define CLK_PCLK_SMMU_GSCL2 28 - -#define GSCL_NR_CLK 29 - -/* CMU_APOLLO */ -#define CLK_FOUT_APOLLO_PLL 1 - -#define CLK_MOUT_APOLLO_PLL 2 -#define CLK_MOUT_BUS_PLL_APOLLO_USER 3 -#define CLK_MOUT_APOLLO 4 - -#define CLK_DIV_CNTCLK_APOLLO 5 -#define CLK_DIV_PCLK_DBG_APOLLO 6 -#define CLK_DIV_ATCLK_APOLLO 7 -#define CLK_DIV_PCLK_APOLLO 8 -#define CLK_DIV_ACLK_APOLLO 9 -#define CLK_DIV_APOLLO2 10 -#define CLK_DIV_APOLLO1 11 -#define CLK_DIV_SCLK_HPM_APOLLO 12 -#define CLK_DIV_APOLLO_PLL 13 - -#define CLK_ACLK_ATBDS_APOLLO_3 14 -#define CLK_ACLK_ATBDS_APOLLO_2 15 -#define CLK_ACLK_ATBDS_APOLLO_1 16 -#define CLK_ACLK_ATBDS_APOLLO_0 17 -#define CLK_ACLK_ASATBSLV_APOLLO_3_CSSYS 18 -#define CLK_ACLK_ASATBSLV_APOLLO_2_CSSYS 19 -#define CLK_ACLK_ASATBSLV_APOLLO_1_CSSYS 20 -#define CLK_ACLK_ASATBSLV_APOLLO_0_CSSYS 21 -#define CLK_ACLK_ASYNCACES_APOLLO_CCI 22 -#define CLK_ACLK_AHB2APB_APOLLOP 23 -#define CLK_ACLK_APOLLONP_200 24 -#define CLK_PCLK_ASAPBMST_CSSYS_APOLLO 25 -#define CLK_PCLK_PMU_APOLLO 26 -#define CLK_PCLK_SYSREG_APOLLO 27 -#define CLK_CNTCLK_APOLLO 28 -#define CLK_SCLK_HPM_APOLLO 29 -#define CLK_SCLK_APOLLO 30 - -#define APOLLO_NR_CLK 31 - -/* CMU_ATLAS */ -#define CLK_FOUT_ATLAS_PLL 1 - -#define CLK_MOUT_ATLAS_PLL 2 -#define CLK_MOUT_BUS_PLL_ATLAS_USER 3 -#define CLK_MOUT_ATLAS 4 - -#define CLK_DIV_CNTCLK_ATLAS 5 -#define CLK_DIV_PCLK_DBG_ATLAS 6 -#define CLK_DIV_ATCLK_ATLASO 7 -#define CLK_DIV_PCLK_ATLAS 8 -#define CLK_DIV_ACLK_ATLAS 9 -#define CLK_DIV_ATLAS2 10 -#define CLK_DIV_ATLAS1 11 -#define CLK_DIV_SCLK_HPM_ATLAS 12 -#define CLK_DIV_ATLAS_PLL 13 - -#define CLK_ACLK_ATB_AUD_CSSYS 14 -#define CLK_ACLK_ATB_APOLLO3_CSSYS 15 -#define CLK_ACLK_ATB_APOLLO2_CSSYS 16 -#define CLK_ACLK_ATB_APOLLO1_CSSYS 17 -#define CLK_ACLK_ATB_APOLLO0_CSSYS 18 -#define CLK_ACLK_ASYNCAHBS_CSSYS_SSS 19 -#define CLK_ACLK_ASYNCAXIS_CSSYS_CCIX 20 -#define CLK_ACLK_ASYNCACES_ATLAS_CCI 21 -#define CLK_ACLK_AHB2APB_ATLASP 22 -#define CLK_ACLK_ATLASNP_200 23 -#define CLK_PCLK_ASYNCAPB_AUD_CSSYS 24 -#define CLK_PCLK_ASYNCAPB_ISP_CSSYS 25 -#define CLK_PCLK_ASYNCAPB_APOLLO_CSSYS 26 -#define CLK_PCLK_PMU_ATLAS 27 -#define CLK_PCLK_SYSREG_ATLAS 28 -#define CLK_PCLK_SECJTAG 29 -#define CLK_CNTCLK_ATLAS 30 -#define CLK_SCLK_FREQ_DET_ATLAS_PLL 31 -#define CLK_SCLK_HPM_ATLAS 32 -#define CLK_TRACECLK 33 -#define CLK_CTMCLK 34 -#define CLK_HCLK_CSSYS 35 -#define CLK_PCLK_DBG_CSSYS 36 -#define CLK_PCLK_DBG 37 -#define CLK_ATCLK 38 -#define CLK_SCLK_ATLAS 39 - -#define ATLAS_NR_CLK 40 - -/* CMU_MSCL */ -#define CLK_MOUT_SCLK_JPEG_USER 1 -#define CLK_MOUT_ACLK_MSCL_400_USER 2 -#define CLK_MOUT_SCLK_JPEG 3 - -#define CLK_DIV_PCLK_MSCL 4 - -#define CLK_ACLK_BTS_JPEG 5 -#define CLK_ACLK_BTS_M2MSCALER1 6 -#define CLK_ACLK_BTS_M2MSCALER0 7 -#define CLK_ACLK_AHB2APB_MSCL0P 8 -#define CLK_ACLK_XIU_MSCLX 9 -#define CLK_ACLK_MSCLNP_100 10 -#define CLK_ACLK_MSCLND_400 11 -#define CLK_ACLK_JPEG 12 -#define CLK_ACLK_M2MSCALER1 13 -#define CLK_ACLK_M2MSCALER0 14 -#define CLK_ACLK_SMMU_M2MSCALER0 15 -#define CLK_ACLK_SMMU_M2MSCALER1 16 -#define CLK_ACLK_SMMU_JPEG 17 -#define CLK_PCLK_BTS_JPEG 18 -#define CLK_PCLK_BTS_M2MSCALER1 19 -#define CLK_PCLK_BTS_M2MSCALER0 20 -#define CLK_PCLK_PMU_MSCL 21 -#define CLK_PCLK_SYSREG_MSCL 22 -#define CLK_PCLK_JPEG 23 -#define CLK_PCLK_M2MSCALER1 24 -#define CLK_PCLK_M2MSCALER0 25 -#define CLK_PCLK_SMMU_M2MSCALER0 26 -#define CLK_PCLK_SMMU_M2MSCALER1 27 -#define CLK_PCLK_SMMU_JPEG 28 -#define CLK_SCLK_JPEG 29 - -#define MSCL_NR_CLK 30 - -/* CMU_MFC */ -#define CLK_MOUT_ACLK_MFC_400_USER 1 - -#define CLK_DIV_PCLK_MFC 2 - -#define CLK_ACLK_BTS_MFC_1 3 -#define CLK_ACLK_BTS_MFC_0 4 -#define CLK_ACLK_AHB2APB_MFCP 5 -#define CLK_ACLK_XIU_MFCX 6 -#define CLK_ACLK_MFCNP_100 7 -#define CLK_ACLK_MFCND_400 8 -#define CLK_ACLK_MFC 9 -#define CLK_ACLK_SMMU_MFC_1 10 -#define CLK_ACLK_SMMU_MFC_0 11 -#define CLK_PCLK_BTS_MFC_1 12 -#define CLK_PCLK_BTS_MFC_0 13 -#define CLK_PCLK_PMU_MFC 14 -#define CLK_PCLK_SYSREG_MFC 15 -#define CLK_PCLK_MFC 16 -#define CLK_PCLK_SMMU_MFC_1 17 -#define CLK_PCLK_SMMU_MFC_0 18 - -#define MFC_NR_CLK 19 - -/* CMU_HEVC */ -#define CLK_MOUT_ACLK_HEVC_400_USER 1 - -#define CLK_DIV_PCLK_HEVC 2 - -#define CLK_ACLK_BTS_HEVC_1 3 -#define CLK_ACLK_BTS_HEVC_0 4 -#define CLK_ACLK_AHB2APB_HEVCP 5 -#define CLK_ACLK_XIU_HEVCX 6 -#define CLK_ACLK_HEVCNP_100 7 -#define CLK_ACLK_HEVCND_400 8 -#define CLK_ACLK_HEVC 9 -#define CLK_ACLK_SMMU_HEVC_1 10 -#define CLK_ACLK_SMMU_HEVC_0 11 -#define CLK_PCLK_BTS_HEVC_1 12 -#define CLK_PCLK_BTS_HEVC_0 13 -#define CLK_PCLK_PMU_HEVC 14 -#define CLK_PCLK_SYSREG_HEVC 15 -#define CLK_PCLK_HEVC 16 -#define CLK_PCLK_SMMU_HEVC_1 17 -#define CLK_PCLK_SMMU_HEVC_0 18 - -#define HEVC_NR_CLK 19 - -/* CMU_ISP */ -#define CLK_MOUT_ACLK_ISP_DIS_400_USER 1 -#define CLK_MOUT_ACLK_ISP_400_USER 2 - -#define CLK_DIV_PCLK_ISP_DIS 3 -#define CLK_DIV_PCLK_ISP 4 -#define CLK_DIV_ACLK_ISP_D_200 5 -#define CLK_DIV_ACLK_ISP_C_200 6 - -#define CLK_ACLK_ISP_D_GLUE 7 -#define CLK_ACLK_SCALERP 8 -#define CLK_ACLK_3DNR 9 -#define CLK_ACLK_DIS 10 -#define CLK_ACLK_SCALERC 11 -#define CLK_ACLK_DRC 12 -#define CLK_ACLK_ISP 13 -#define CLK_ACLK_AXIUS_SCALERP 14 -#define CLK_ACLK_AXIUS_SCALERC 15 -#define CLK_ACLK_AXIUS_DRC 16 -#define CLK_ACLK_ASYNCAHBM_ISP2P 17 -#define CLK_ACLK_ASYNCAHBM_ISP1P 18 -#define CLK_ACLK_ASYNCAXIS_DIS1 19 -#define CLK_ACLK_ASYNCAXIS_DIS0 20 -#define CLK_ACLK_ASYNCAXIM_DIS1 21 -#define CLK_ACLK_ASYNCAXIM_DIS0 22 -#define CLK_ACLK_ASYNCAXIM_ISP2P 23 -#define CLK_ACLK_ASYNCAXIM_ISP1P 24 -#define CLK_ACLK_AHB2APB_ISP2P 25 -#define CLK_ACLK_AHB2APB_ISP1P 26 -#define CLK_ACLK_AXI2APB_ISP2P 27 -#define CLK_ACLK_AXI2APB_ISP1P 28 -#define CLK_ACLK_XIU_ISPEX1 29 -#define CLK_ACLK_XIU_ISPEX0 30 -#define CLK_ACLK_ISPND_400 31 -#define CLK_ACLK_SMMU_SCALERP 32 -#define CLK_ACLK_SMMU_3DNR 33 -#define CLK_ACLK_SMMU_DIS1 34 -#define CLK_ACLK_SMMU_DIS0 35 -#define CLK_ACLK_SMMU_SCALERC 36 -#define CLK_ACLK_SMMU_DRC 37 -#define CLK_ACLK_SMMU_ISP 38 -#define CLK_ACLK_BTS_SCALERP 39 -#define CLK_ACLK_BTS_3DR 40 -#define CLK_ACLK_BTS_DIS1 41 -#define CLK_ACLK_BTS_DIS0 42 -#define CLK_ACLK_BTS_SCALERC 43 -#define CLK_ACLK_BTS_DRC 44 -#define CLK_ACLK_BTS_ISP 45 -#define CLK_PCLK_SMMU_SCALERP 46 -#define CLK_PCLK_SMMU_3DNR 47 -#define CLK_PCLK_SMMU_DIS1 48 -#define CLK_PCLK_SMMU_DIS0 49 -#define CLK_PCLK_SMMU_SCALERC 50 -#define CLK_PCLK_SMMU_DRC 51 -#define CLK_PCLK_SMMU_ISP 52 -#define CLK_PCLK_BTS_SCALERP 53 -#define CLK_PCLK_BTS_3DNR 54 -#define CLK_PCLK_BTS_DIS1 55 -#define CLK_PCLK_BTS_DIS0 56 -#define CLK_PCLK_BTS_SCALERC 57 -#define CLK_PCLK_BTS_DRC 58 -#define CLK_PCLK_BTS_ISP 59 -#define CLK_PCLK_ASYNCAXI_DIS1 60 -#define CLK_PCLK_ASYNCAXI_DIS0 61 -#define CLK_PCLK_PMU_ISP 62 -#define CLK_PCLK_SYSREG_ISP 63 -#define CLK_PCLK_CMU_ISP_LOCAL 64 -#define CLK_PCLK_SCALERP 65 -#define CLK_PCLK_3DNR 66 -#define CLK_PCLK_DIS_CORE 67 -#define CLK_PCLK_DIS 68 -#define CLK_PCLK_SCALERC 69 -#define CLK_PCLK_DRC 70 -#define CLK_PCLK_ISP 71 -#define CLK_SCLK_PIXELASYNCS_DIS 72 -#define CLK_SCLK_PIXELASYNCM_DIS 73 -#define CLK_SCLK_PIXELASYNCS_SCALERP 74 -#define CLK_SCLK_PIXELASYNCM_ISPD 75 -#define CLK_SCLK_PIXELASYNCS_ISPC 76 -#define CLK_SCLK_PIXELASYNCM_ISPC 77 - -#define ISP_NR_CLK 78 - -/* CMU_CAM0 */ -#define CLK_PHYCLK_RXBYTEECLKHS0_S4_PHY 1 -#define CLK_PHYCLK_RXBYTEECLKHS0_S2A_PHY 2 - -#define CLK_MOUT_ACLK_CAM0_333_USER 3 -#define CLK_MOUT_ACLK_CAM0_400_USER 4 -#define CLK_MOUT_ACLK_CAM0_552_USER 5 -#define CLK_MOUT_PHYCLK_RXBYTECLKHS0_S4_USER 6 -#define CLK_MOUT_PHYCLK_RXBYTECLKHS0_S2A_USER 7 -#define CLK_MOUT_ACLK_LITE_D_B 8 -#define CLK_MOUT_ACLK_LITE_D_A 9 -#define CLK_MOUT_ACLK_LITE_B_B 10 -#define CLK_MOUT_ACLK_LITE_B_A 11 -#define CLK_MOUT_ACLK_LITE_A_B 12 -#define CLK_MOUT_ACLK_LITE_A_A 13 -#define CLK_MOUT_ACLK_CAM0_400 14 -#define CLK_MOUT_ACLK_CSIS1_B 15 -#define CLK_MOUT_ACLK_CSIS1_A 16 -#define CLK_MOUT_ACLK_CSIS0_B 17 -#define CLK_MOUT_ACLK_CSIS0_A 18 -#define CLK_MOUT_ACLK_3AA1_B 19 -#define CLK_MOUT_ACLK_3AA1_A 20 -#define CLK_MOUT_ACLK_3AA0_B 21 -#define CLK_MOUT_ACLK_3AA0_A 22 -#define CLK_MOUT_SCLK_LITE_FREECNT_C 23 -#define CLK_MOUT_SCLK_LITE_FREECNT_B 24 -#define CLK_MOUT_SCLK_LITE_FREECNT_A 25 -#define CLK_MOUT_SCLK_PIXELASYNC_LITE_C_B 26 -#define CLK_MOUT_SCLK_PIXELASYNC_LITE_C_A 27 -#define CLK_MOUT_SCLK_PIXELASYNC_LITE_C_INIT_B 28 -#define CLK_MOUT_SCLK_PIXELASYNC_LITE_C_INIT_A 29 - -#define CLK_DIV_PCLK_CAM0_50 30 -#define CLK_DIV_ACLK_CAM0_200 31 -#define CLK_DIV_ACLK_CAM0_BUS_400 32 -#define CLK_DIV_PCLK_LITE_D 33 -#define CLK_DIV_ACLK_LITE_D 34 -#define CLK_DIV_PCLK_LITE_B 35 -#define CLK_DIV_ACLK_LITE_B 36 -#define CLK_DIV_PCLK_LITE_A 37 -#define CLK_DIV_ACLK_LITE_A 38 -#define CLK_DIV_ACLK_CSIS1 39 -#define CLK_DIV_ACLK_CSIS0 40 -#define CLK_DIV_PCLK_3AA1 41 -#define CLK_DIV_ACLK_3AA1 42 -#define CLK_DIV_PCLK_3AA0 43 -#define CLK_DIV_ACLK_3AA0 44 -#define CLK_DIV_SCLK_PIXELASYNC_LITE_C 45 -#define CLK_DIV_PCLK_PIXELASYNC_LITE_C 46 -#define CLK_DIV_SCLK_PIXELASYNC_LITE_C_INIT 47 - -#define CLK_ACLK_CSIS1 50 -#define CLK_ACLK_CSIS0 51 -#define CLK_ACLK_3AA1 52 -#define CLK_ACLK_3AA0 53 -#define CLK_ACLK_LITE_D 54 -#define CLK_ACLK_LITE_B 55 -#define CLK_ACLK_LITE_A 56 -#define CLK_ACLK_AHBSYNCDN 57 -#define CLK_ACLK_AXIUS_LITE_D 58 -#define CLK_ACLK_AXIUS_LITE_B 59 -#define CLK_ACLK_AXIUS_LITE_A 60 -#define CLK_ACLK_ASYNCAPBM_3AA1 61 -#define CLK_ACLK_ASYNCAPBS_3AA1 62 -#define CLK_ACLK_ASYNCAPBM_3AA0 63 -#define CLK_ACLK_ASYNCAPBS_3AA0 64 -#define CLK_ACLK_ASYNCAPBM_LITE_D 65 -#define CLK_ACLK_ASYNCAPBS_LITE_D 66 -#define CLK_ACLK_ASYNCAPBM_LITE_B 67 -#define CLK_ACLK_ASYNCAPBS_LITE_B 68 -#define CLK_ACLK_ASYNCAPBM_LITE_A 69 -#define CLK_ACLK_ASYNCAPBS_LITE_A 70 -#define CLK_ACLK_ASYNCAXIM_ISP0P 71 -#define CLK_ACLK_ASYNCAXIM_3AA1 72 -#define CLK_ACLK_ASYNCAXIS_3AA1 73 -#define CLK_ACLK_ASYNCAXIM_3AA0 74 -#define CLK_ACLK_ASYNCAXIS_3AA0 75 -#define CLK_ACLK_ASYNCAXIM_LITE_D 76 -#define CLK_ACLK_ASYNCAXIS_LITE_D 77 -#define CLK_ACLK_ASYNCAXIM_LITE_B 78 -#define CLK_ACLK_ASYNCAXIS_LITE_B 79 -#define CLK_ACLK_ASYNCAXIM_LITE_A 80 -#define CLK_ACLK_ASYNCAXIS_LITE_A 81 -#define CLK_ACLK_AHB2APB_ISPSFRP 82 -#define CLK_ACLK_AXI2APB_ISP0P 83 -#define CLK_ACLK_AXI2AHB_ISP0P 84 -#define CLK_ACLK_XIU_IS0X 85 -#define CLK_ACLK_XIU_ISP0EX 86 -#define CLK_ACLK_CAM0NP_276 87 -#define CLK_ACLK_CAM0ND_400 88 -#define CLK_ACLK_SMMU_3AA1 89 -#define CLK_ACLK_SMMU_3AA0 90 -#define CLK_ACLK_SMMU_LITE_D 91 -#define CLK_ACLK_SMMU_LITE_B 92 -#define CLK_ACLK_SMMU_LITE_A 93 -#define CLK_ACLK_BTS_3AA1 94 -#define CLK_ACLK_BTS_3AA0 95 -#define CLK_ACLK_BTS_LITE_D 96 -#define CLK_ACLK_BTS_LITE_B 97 -#define CLK_ACLK_BTS_LITE_A 98 -#define CLK_PCLK_SMMU_3AA1 99 -#define CLK_PCLK_SMMU_3AA0 100 -#define CLK_PCLK_SMMU_LITE_D 101 -#define CLK_PCLK_SMMU_LITE_B 102 -#define CLK_PCLK_SMMU_LITE_A 103 -#define CLK_PCLK_BTS_3AA1 104 -#define CLK_PCLK_BTS_3AA0 105 -#define CLK_PCLK_BTS_LITE_D 106 -#define CLK_PCLK_BTS_LITE_B 107 -#define CLK_PCLK_BTS_LITE_A 108 -#define CLK_PCLK_ASYNCAXI_CAM1 109 -#define CLK_PCLK_ASYNCAXI_3AA1 110 -#define CLK_PCLK_ASYNCAXI_3AA0 111 -#define CLK_PCLK_ASYNCAXI_LITE_D 112 -#define CLK_PCLK_ASYNCAXI_LITE_B 113 -#define CLK_PCLK_ASYNCAXI_LITE_A 114 -#define CLK_PCLK_PMU_CAM0 115 -#define CLK_PCLK_SYSREG_CAM0 116 -#define CLK_PCLK_CMU_CAM0_LOCAL 117 -#define CLK_PCLK_CSIS1 118 -#define CLK_PCLK_CSIS0 119 -#define CLK_PCLK_3AA1 120 -#define CLK_PCLK_3AA0 121 -#define CLK_PCLK_LITE_D 122 -#define CLK_PCLK_LITE_B 123 -#define CLK_PCLK_LITE_A 124 -#define CLK_PHYCLK_RXBYTECLKHS0_S4 125 -#define CLK_PHYCLK_RXBYTECLKHS0_S2A 126 -#define CLK_SCLK_LITE_FREECNT 127 -#define CLK_SCLK_PIXELASYNCM_3AA1 128 -#define CLK_SCLK_PIXELASYNCM_3AA0 129 -#define CLK_SCLK_PIXELASYNCS_3AA0 130 -#define CLK_SCLK_PIXELASYNCM_LITE_C 131 -#define CLK_SCLK_PIXELASYNCM_LITE_C_INIT 132 -#define CLK_SCLK_PIXELASYNCS_LITE_C_INIT 133 - -#define CAM0_NR_CLK 134 - -/* CMU_CAM1 */ -#define CLK_PHYCLK_RXBYTEECLKHS0_S2B 1 - -#define CLK_MOUT_SCLK_ISP_UART_USER 2 -#define CLK_MOUT_SCLK_ISP_SPI1_USER 3 -#define CLK_MOUT_SCLK_ISP_SPI0_USER 4 -#define CLK_MOUT_ACLK_CAM1_333_USER 5 -#define CLK_MOUT_ACLK_CAM1_400_USER 6 -#define CLK_MOUT_ACLK_CAM1_552_USER 7 -#define CLK_MOUT_PHYCLK_RXBYTECLKHS0_S2B_USER 8 -#define CLK_MOUT_ACLK_CSIS2_B 9 -#define CLK_MOUT_ACLK_CSIS2_A 10 -#define CLK_MOUT_ACLK_FD_B 11 -#define CLK_MOUT_ACLK_FD_A 12 -#define CLK_MOUT_ACLK_LITE_C_B 13 -#define CLK_MOUT_ACLK_LITE_C_A 14 - -#define CLK_DIV_SCLK_ISP_MPWM 15 -#define CLK_DIV_PCLK_CAM1_83 16 -#define CLK_DIV_PCLK_CAM1_166 17 -#define CLK_DIV_PCLK_DBG_CAM1 18 -#define CLK_DIV_ATCLK_CAM1 19 -#define CLK_DIV_ACLK_CSIS2 20 -#define CLK_DIV_PCLK_FD 21 -#define CLK_DIV_ACLK_FD 22 -#define CLK_DIV_PCLK_LITE_C 23 -#define CLK_DIV_ACLK_LITE_C 24 - -#define CLK_ACLK_ISP_GIC 25 -#define CLK_ACLK_FD 26 -#define CLK_ACLK_LITE_C 27 -#define CLK_ACLK_CSIS2 28 -#define CLK_ACLK_ASYNCAPBM_FD 29 -#define CLK_ACLK_ASYNCAPBS_FD 30 -#define CLK_ACLK_ASYNCAPBM_LITE_C 31 -#define CLK_ACLK_ASYNCAPBS_LITE_C 32 -#define CLK_ACLK_ASYNCAHBS_SFRISP2H2 33 -#define CLK_ACLK_ASYNCAHBS_SFRISP2H1 34 -#define CLK_ACLK_ASYNCAXIM_CA5 35 -#define CLK_ACLK_ASYNCAXIS_CA5 36 -#define CLK_ACLK_ASYNCAXIS_ISPX2 37 -#define CLK_ACLK_ASYNCAXIS_ISPX1 38 -#define CLK_ACLK_ASYNCAXIS_ISPX0 39 -#define CLK_ACLK_ASYNCAXIM_ISPEX 40 -#define CLK_ACLK_ASYNCAXIM_ISP3P 41 -#define CLK_ACLK_ASYNCAXIS_ISP3P 42 -#define CLK_ACLK_ASYNCAXIM_FD 43 -#define CLK_ACLK_ASYNCAXIS_FD 44 -#define CLK_ACLK_ASYNCAXIM_LITE_C 45 -#define CLK_ACLK_ASYNCAXIS_LITE_C 46 -#define CLK_ACLK_AHB2APB_ISP5P 47 -#define CLK_ACLK_AHB2APB_ISP3P 48 -#define CLK_ACLK_AXI2APB_ISP3P 49 -#define CLK_ACLK_AHB_SFRISP2H 50 -#define CLK_ACLK_AXI_ISP_HX_R 51 -#define CLK_ACLK_AXI_ISP_CX_R 52 -#define CLK_ACLK_AXI_ISP_HX 53 -#define CLK_ACLK_AXI_ISP_CX 54 -#define CLK_ACLK_XIU_ISPX 55 -#define CLK_ACLK_XIU_ISPEX 56 -#define CLK_ACLK_CAM1NP_333 57 -#define CLK_ACLK_CAM1ND_400 58 -#define CLK_ACLK_SMMU_ISPCPU 59 -#define CLK_ACLK_SMMU_FD 60 -#define CLK_ACLK_SMMU_LITE_C 61 -#define CLK_ACLK_BTS_ISP3P 62 -#define CLK_ACLK_BTS_FD 63 -#define CLK_ACLK_BTS_LITE_C 64 -#define CLK_ACLK_AHBDN_SFRISP2H 65 -#define CLK_ACLK_AHBDN_ISP5P 66 -#define CLK_ACLK_AXIUS_ISP3P 67 -#define CLK_ACLK_AXIUS_FD 68 -#define CLK_ACLK_AXIUS_LITE_C 69 -#define CLK_PCLK_SMMU_ISPCPU 70 -#define CLK_PCLK_SMMU_FD 71 -#define CLK_PCLK_SMMU_LITE_C 72 -#define CLK_PCLK_BTS_ISP3P 73 -#define CLK_PCLK_BTS_FD 74 -#define CLK_PCLK_BTS_LITE_C 75 -#define CLK_PCLK_ASYNCAXIM_CA5 76 -#define CLK_PCLK_ASYNCAXIM_ISPEX 77 -#define CLK_PCLK_ASYNCAXIM_ISP3P 78 -#define CLK_PCLK_ASYNCAXIM_FD 79 -#define CLK_PCLK_ASYNCAXIM_LITE_C 80 -#define CLK_PCLK_PMU_CAM1 81 -#define CLK_PCLK_SYSREG_CAM1 82 -#define CLK_PCLK_CMU_CAM1_LOCAL 83 -#define CLK_PCLK_ISP_MCTADC 84 -#define CLK_PCLK_ISP_WDT 85 -#define CLK_PCLK_ISP_PWM 86 -#define CLK_PCLK_ISP_UART 87 -#define CLK_PCLK_ISP_MCUCTL 88 -#define CLK_PCLK_ISP_SPI1 89 -#define CLK_PCLK_ISP_SPI0 90 -#define CLK_PCLK_ISP_I2C2 91 -#define CLK_PCLK_ISP_I2C1 92 -#define CLK_PCLK_ISP_I2C0 93 -#define CLK_PCLK_ISP_MPWM 94 -#define CLK_PCLK_FD 95 -#define CLK_PCLK_LITE_C 96 -#define CLK_PCLK_CSIS2 97 -#define CLK_SCLK_ISP_I2C2 98 -#define CLK_SCLK_ISP_I2C1 99 -#define CLK_SCLK_ISP_I2C0 100 -#define CLK_SCLK_ISP_PWM 101 -#define CLK_PHYCLK_RXBYTECLKHS0_S2B 102 -#define CLK_SCLK_LITE_C_FREECNT 103 -#define CLK_SCLK_PIXELASYNCM_FD 104 -#define CLK_SCLK_ISP_MCTADC 105 -#define CLK_SCLK_ISP_UART 106 -#define CLK_SCLK_ISP_SPI1 107 -#define CLK_SCLK_ISP_SPI0 108 -#define CLK_SCLK_ISP_MPWM 109 -#define CLK_PCLK_DBG_ISP 110 -#define CLK_ATCLK_ISP 111 -#define CLK_SCLK_ISP_CA5 112 - -#define CAM1_NR_CLK 113 - -/* CMU_IMEM */ -#define CLK_ACLK_SLIMSSS 2 -#define CLK_PCLK_SLIMSSS 35 - -#define IMEM_NR_CLK 36 - -#endif /* _DT_BINDINGS_CLOCK_EXYNOS5433_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/exynos5440.h b/sys/gnu/dts/include/dt-bindings/clock/exynos5440.h deleted file mode 100644 index c66fc405a79..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/exynos5440.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Copyright (c) 2013 Samsung Electronics Co., Ltd. - * Author: Andrzej Hajda - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Device Tree binding constants for Exynos5440 clock controller. -*/ - -#ifndef _DT_BINDINGS_CLOCK_EXYNOS_5440_H -#define _DT_BINDINGS_CLOCK_EXYNOS_5440_H - -#define CLK_XTAL 1 -#define CLK_ARM_CLK 2 -#define CLK_SPI_BAUD 16 -#define CLK_PB0_250 17 -#define CLK_PR0_250 18 -#define CLK_PR1_250 19 -#define CLK_B_250 20 -#define CLK_B_125 21 -#define CLK_B_200 22 -#define CLK_SATA 23 -#define CLK_USB 24 -#define CLK_GMAC0 25 -#define CLK_CS250 26 -#define CLK_PB0_250_O 27 -#define CLK_PR0_250_O 28 -#define CLK_PR1_250_O 29 -#define CLK_B_250_O 30 -#define CLK_B_125_O 31 -#define CLK_B_200_O 32 -#define CLK_SATA_O 33 -#define CLK_USB_O 34 -#define CLK_GMAC0_O 35 -#define CLK_CS250_O 36 - -/* must be greater than maximal clock id */ -#define CLK_NR_CLKS 37 - -#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5440_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/exynos7-clk.h b/sys/gnu/dts/include/dt-bindings/clock/exynos7-clk.h deleted file mode 100644 index fce33c7050c..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/exynos7-clk.h +++ /dev/null @@ -1,204 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2014 Samsung Electronics Co., Ltd. - * Author: Naveen Krishna Ch - */ - -#ifndef _DT_BINDINGS_CLOCK_EXYNOS7_H -#define _DT_BINDINGS_CLOCK_EXYNOS7_H - -/* TOPC */ -#define DOUT_ACLK_PERIS 1 -#define DOUT_SCLK_BUS0_PLL 2 -#define DOUT_SCLK_BUS1_PLL 3 -#define DOUT_SCLK_CC_PLL 4 -#define DOUT_SCLK_MFC_PLL 5 -#define DOUT_ACLK_CCORE_133 6 -#define DOUT_ACLK_MSCL_532 7 -#define ACLK_MSCL_532 8 -#define DOUT_SCLK_AUD_PLL 9 -#define FOUT_AUD_PLL 10 -#define SCLK_AUD_PLL 11 -#define SCLK_MFC_PLL_B 12 -#define SCLK_MFC_PLL_A 13 -#define SCLK_BUS1_PLL_B 14 -#define SCLK_BUS1_PLL_A 15 -#define SCLK_BUS0_PLL_B 16 -#define SCLK_BUS0_PLL_A 17 -#define SCLK_CC_PLL_B 18 -#define SCLK_CC_PLL_A 19 -#define ACLK_CCORE_133 20 -#define ACLK_PERIS_66 21 -#define TOPC_NR_CLK 22 - -/* TOP0 */ -#define DOUT_ACLK_PERIC1 1 -#define DOUT_ACLK_PERIC0 2 -#define CLK_SCLK_UART0 3 -#define CLK_SCLK_UART1 4 -#define CLK_SCLK_UART2 5 -#define CLK_SCLK_UART3 6 -#define CLK_SCLK_SPI0 7 -#define CLK_SCLK_SPI1 8 -#define CLK_SCLK_SPI2 9 -#define CLK_SCLK_SPI3 10 -#define CLK_SCLK_SPI4 11 -#define CLK_SCLK_SPDIF 12 -#define CLK_SCLK_PCM1 13 -#define CLK_SCLK_I2S1 14 -#define CLK_ACLK_PERIC0_66 15 -#define CLK_ACLK_PERIC1_66 16 -#define TOP0_NR_CLK 17 - -/* TOP1 */ -#define DOUT_ACLK_FSYS1_200 1 -#define DOUT_ACLK_FSYS0_200 2 -#define DOUT_SCLK_MMC2 3 -#define DOUT_SCLK_MMC1 4 -#define DOUT_SCLK_MMC0 5 -#define CLK_SCLK_MMC2 6 -#define CLK_SCLK_MMC1 7 -#define CLK_SCLK_MMC0 8 -#define CLK_ACLK_FSYS0_200 9 -#define CLK_ACLK_FSYS1_200 10 -#define CLK_SCLK_PHY_FSYS1 11 -#define CLK_SCLK_PHY_FSYS1_26M 12 -#define MOUT_SCLK_UFSUNIPRO20 13 -#define DOUT_SCLK_UFSUNIPRO20 14 -#define CLK_SCLK_UFSUNIPRO20 15 -#define DOUT_SCLK_PHY_FSYS1 16 -#define DOUT_SCLK_PHY_FSYS1_26M 17 -#define TOP1_NR_CLK 18 - -/* CCORE */ -#define PCLK_RTC 1 -#define CCORE_NR_CLK 2 - -/* PERIC0 */ -#define PCLK_UART0 1 -#define SCLK_UART0 2 -#define PCLK_HSI2C0 3 -#define PCLK_HSI2C1 4 -#define PCLK_HSI2C4 5 -#define PCLK_HSI2C5 6 -#define PCLK_HSI2C9 7 -#define PCLK_HSI2C10 8 -#define PCLK_HSI2C11 9 -#define PCLK_PWM 10 -#define SCLK_PWM 11 -#define PCLK_ADCIF 12 -#define PERIC0_NR_CLK 13 - -/* PERIC1 */ -#define PCLK_UART1 1 -#define PCLK_UART2 2 -#define PCLK_UART3 3 -#define SCLK_UART1 4 -#define SCLK_UART2 5 -#define SCLK_UART3 6 -#define PCLK_HSI2C2 7 -#define PCLK_HSI2C3 8 -#define PCLK_HSI2C6 9 -#define PCLK_HSI2C7 10 -#define PCLK_HSI2C8 11 -#define PCLK_SPI0 12 -#define PCLK_SPI1 13 -#define PCLK_SPI2 14 -#define PCLK_SPI3 15 -#define PCLK_SPI4 16 -#define SCLK_SPI0 17 -#define SCLK_SPI1 18 -#define SCLK_SPI2 19 -#define SCLK_SPI3 20 -#define SCLK_SPI4 21 -#define PCLK_I2S1 22 -#define PCLK_PCM1 23 -#define PCLK_SPDIF 24 -#define SCLK_I2S1 25 -#define SCLK_PCM1 26 -#define SCLK_SPDIF 27 -#define PERIC1_NR_CLK 28 - -/* PERIS */ -#define PCLK_CHIPID 1 -#define SCLK_CHIPID 2 -#define PCLK_WDT 3 -#define PCLK_TMU 4 -#define SCLK_TMU 5 -#define PERIS_NR_CLK 6 - -/* FSYS0 */ -#define ACLK_MMC2 1 -#define ACLK_AXIUS_USBDRD30X_FSYS0X 2 -#define ACLK_USBDRD300 3 -#define SCLK_USBDRD300_SUSPENDCLK 4 -#define SCLK_USBDRD300_REFCLK 5 -#define PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER 6 -#define PHYCLK_USBDRD300_UDRD30_PHYCLK_USER 7 -#define OSCCLK_PHY_CLKOUT_USB30_PHY 8 -#define ACLK_PDMA0 9 -#define ACLK_PDMA1 10 -#define FSYS0_NR_CLK 11 - -/* FSYS1 */ -#define ACLK_MMC1 1 -#define ACLK_MMC0 2 -#define PHYCLK_UFS20_TX0_SYMBOL 3 -#define PHYCLK_UFS20_RX0_SYMBOL 4 -#define PHYCLK_UFS20_RX1_SYMBOL 5 -#define ACLK_UFS20_LINK 6 -#define SCLK_UFSUNIPRO20_USER 7 -#define PHYCLK_UFS20_RX1_SYMBOL_USER 8 -#define PHYCLK_UFS20_RX0_SYMBOL_USER 9 -#define PHYCLK_UFS20_TX0_SYMBOL_USER 10 -#define OSCCLK_PHY_CLKOUT_EMBEDDED_COMBO_PHY 11 -#define SCLK_COMBO_PHY_EMBEDDED_26M 12 -#define DOUT_PCLK_FSYS1 13 -#define PCLK_GPIO_FSYS1 14 -#define MOUT_FSYS1_PHYCLK_SEL1 15 -#define FSYS1_NR_CLK 16 - -/* MSCL */ -#define USERMUX_ACLK_MSCL_532 1 -#define DOUT_PCLK_MSCL 2 -#define ACLK_MSCL_0 3 -#define ACLK_MSCL_1 4 -#define ACLK_JPEG 5 -#define ACLK_G2D 6 -#define ACLK_LH_ASYNC_SI_MSCL_0 7 -#define ACLK_LH_ASYNC_SI_MSCL_1 8 -#define ACLK_AXI2ACEL_BRIDGE 9 -#define ACLK_XIU_MSCLX_0 10 -#define ACLK_XIU_MSCLX_1 11 -#define ACLK_QE_MSCL_0 12 -#define ACLK_QE_MSCL_1 13 -#define ACLK_QE_JPEG 14 -#define ACLK_QE_G2D 15 -#define ACLK_PPMU_MSCL_0 16 -#define ACLK_PPMU_MSCL_1 17 -#define ACLK_MSCLNP_133 18 -#define ACLK_AHB2APB_MSCL0P 19 -#define ACLK_AHB2APB_MSCL1P 20 - -#define PCLK_MSCL_0 21 -#define PCLK_MSCL_1 22 -#define PCLK_JPEG 23 -#define PCLK_G2D 24 -#define PCLK_QE_MSCL_0 25 -#define PCLK_QE_MSCL_1 26 -#define PCLK_QE_JPEG 27 -#define PCLK_QE_G2D 28 -#define PCLK_PPMU_MSCL_0 29 -#define PCLK_PPMU_MSCL_1 30 -#define PCLK_AXI2ACEL_BRIDGE 31 -#define PCLK_PMU_MSCL 32 -#define MSCL_NR_CLK 33 - -/* AUD */ -#define SCLK_I2S 1 -#define SCLK_PCM 2 -#define PCLK_I2S 3 -#define PCLK_PCM 4 -#define ACLK_ADMA 5 -#define AUD_NR_CLK 6 -#endif /* _DT_BINDINGS_CLOCK_EXYNOS7_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/g12a-aoclkc.h b/sys/gnu/dts/include/dt-bindings/clock/g12a-aoclkc.h deleted file mode 100644 index e916e49ff28..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/g12a-aoclkc.h +++ /dev/null @@ -1,36 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ -/* - * Copyright (c) 2016 BayLibre, SAS - * Author: Neil Armstrong - * - * Copyright (c) 2018 Amlogic, inc. - * Author: Qiufang Dai - */ - -#ifndef DT_BINDINGS_CLOCK_AMLOGIC_MESON_G12A_AOCLK -#define DT_BINDINGS_CLOCK_AMLOGIC_MESON_G12A_AOCLK - -#define CLKID_AO_AHB 0 -#define CLKID_AO_IR_IN 1 -#define CLKID_AO_I2C_M0 2 -#define CLKID_AO_I2C_S0 3 -#define CLKID_AO_UART 4 -#define CLKID_AO_PROD_I2C 5 -#define CLKID_AO_UART2 6 -#define CLKID_AO_IR_OUT 7 -#define CLKID_AO_SAR_ADC 8 -#define CLKID_AO_MAILBOX 9 -#define CLKID_AO_M3 10 -#define CLKID_AO_AHB_SRAM 11 -#define CLKID_AO_RTI 12 -#define CLKID_AO_M4_FCLK 13 -#define CLKID_AO_M4_HCLK 14 -#define CLKID_AO_CLK81 15 -#define CLKID_AO_SAR_ADC_SEL 16 -#define CLKID_AO_SAR_ADC_CLK 18 -#define CLKID_AO_CTS_OSCIN 19 -#define CLKID_AO_32K 23 -#define CLKID_AO_CEC 27 -#define CLKID_AO_CTS_RTC_OSCIN 28 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/g12a-clkc.h b/sys/gnu/dts/include/dt-bindings/clock/g12a-clkc.h deleted file mode 100644 index 0837c1a7ae4..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/g12a-clkc.h +++ /dev/null @@ -1,147 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ OR MIT */ -/* - * Meson-G12A clock tree IDs - * - * Copyright (c) 2018 Amlogic, Inc. All rights reserved. - */ - -#ifndef __G12A_CLKC_H -#define __G12A_CLKC_H - -#define CLKID_SYS_PLL 0 -#define CLKID_FIXED_PLL 1 -#define CLKID_FCLK_DIV2 2 -#define CLKID_FCLK_DIV3 3 -#define CLKID_FCLK_DIV4 4 -#define CLKID_FCLK_DIV5 5 -#define CLKID_FCLK_DIV7 6 -#define CLKID_GP0_PLL 7 -#define CLKID_CLK81 10 -#define CLKID_MPLL0 11 -#define CLKID_MPLL1 12 -#define CLKID_MPLL2 13 -#define CLKID_MPLL3 14 -#define CLKID_DDR 15 -#define CLKID_DOS 16 -#define CLKID_AUDIO_LOCKER 17 -#define CLKID_MIPI_DSI_HOST 18 -#define CLKID_ETH_PHY 19 -#define CLKID_ISA 20 -#define CLKID_PL301 21 -#define CLKID_PERIPHS 22 -#define CLKID_SPICC0 23 -#define CLKID_I2C 24 -#define CLKID_SANA 25 -#define CLKID_SD 26 -#define CLKID_RNG0 27 -#define CLKID_UART0 28 -#define CLKID_SPICC1 29 -#define CLKID_HIU_IFACE 30 -#define CLKID_MIPI_DSI_PHY 31 -#define CLKID_ASSIST_MISC 32 -#define CLKID_SD_EMMC_A 33 -#define CLKID_SD_EMMC_B 34 -#define CLKID_SD_EMMC_C 35 -#define CLKID_AUDIO_CODEC 36 -#define CLKID_AUDIO 37 -#define CLKID_ETH 38 -#define CLKID_DEMUX 39 -#define CLKID_AUDIO_IFIFO 40 -#define CLKID_ADC 41 -#define CLKID_UART1 42 -#define CLKID_G2D 43 -#define CLKID_RESET 44 -#define CLKID_PCIE_COMB 45 -#define CLKID_PARSER 46 -#define CLKID_USB 47 -#define CLKID_PCIE_PHY 48 -#define CLKID_AHB_ARB0 49 -#define CLKID_AHB_DATA_BUS 50 -#define CLKID_AHB_CTRL_BUS 51 -#define CLKID_HTX_HDCP22 52 -#define CLKID_HTX_PCLK 53 -#define CLKID_BT656 54 -#define CLKID_USB1_DDR_BRIDGE 55 -#define CLKID_MMC_PCLK 56 -#define CLKID_UART2 57 -#define CLKID_VPU_INTR 58 -#define CLKID_GIC 59 -#define CLKID_SD_EMMC_A_CLK0 60 -#define CLKID_SD_EMMC_B_CLK0 61 -#define CLKID_SD_EMMC_C_CLK0 62 -#define CLKID_HIFI_PLL 74 -#define CLKID_VCLK2_VENCI0 80 -#define CLKID_VCLK2_VENCI1 81 -#define CLKID_VCLK2_VENCP0 82 -#define CLKID_VCLK2_VENCP1 83 -#define CLKID_VCLK2_VENCT0 84 -#define CLKID_VCLK2_VENCT1 85 -#define CLKID_VCLK2_OTHER 86 -#define CLKID_VCLK2_ENCI 87 -#define CLKID_VCLK2_ENCP 88 -#define CLKID_DAC_CLK 89 -#define CLKID_AOCLK 90 -#define CLKID_IEC958 91 -#define CLKID_ENC480P 92 -#define CLKID_RNG1 93 -#define CLKID_VCLK2_ENCT 94 -#define CLKID_VCLK2_ENCL 95 -#define CLKID_VCLK2_VENCLMMC 96 -#define CLKID_VCLK2_VENCL 97 -#define CLKID_VCLK2_OTHER1 98 -#define CLKID_FCLK_DIV2P5 99 -#define CLKID_DMA 105 -#define CLKID_EFUSE 106 -#define CLKID_ROM_BOOT 107 -#define CLKID_RESET_SEC 108 -#define CLKID_SEC_AHB_APB3 109 -#define CLKID_VPU_0_SEL 110 -#define CLKID_VPU_0 112 -#define CLKID_VPU_1_SEL 113 -#define CLKID_VPU_1 115 -#define CLKID_VPU 116 -#define CLKID_VAPB_0_SEL 117 -#define CLKID_VAPB_0 119 -#define CLKID_VAPB_1_SEL 120 -#define CLKID_VAPB_1 122 -#define CLKID_VAPB_SEL 123 -#define CLKID_VAPB 124 -#define CLKID_HDMI_PLL 128 -#define CLKID_VID_PLL 129 -#define CLKID_VCLK 138 -#define CLKID_VCLK2 139 -#define CLKID_VCLK_DIV1 148 -#define CLKID_VCLK_DIV2 149 -#define CLKID_VCLK_DIV4 150 -#define CLKID_VCLK_DIV6 151 -#define CLKID_VCLK_DIV12 152 -#define CLKID_VCLK2_DIV1 153 -#define CLKID_VCLK2_DIV2 154 -#define CLKID_VCLK2_DIV4 155 -#define CLKID_VCLK2_DIV6 156 -#define CLKID_VCLK2_DIV12 157 -#define CLKID_CTS_ENCI 162 -#define CLKID_CTS_ENCP 163 -#define CLKID_CTS_VDAC 164 -#define CLKID_HDMI_TX 165 -#define CLKID_HDMI 168 -#define CLKID_MALI_0_SEL 169 -#define CLKID_MALI_0 171 -#define CLKID_MALI_1_SEL 172 -#define CLKID_MALI_1 174 -#define CLKID_MALI 175 -#define CLKID_MPLL_50M 177 -#define CLKID_CPU_CLK 187 -#define CLKID_PCIE_PLL 201 -#define CLKID_VDEC_1 204 -#define CLKID_VDEC_HEVC 207 -#define CLKID_VDEC_HEVCF 210 -#define CLKID_TS 212 -#define CLKID_CPUB_CLK 224 -#define CLKID_GP1_PLL 243 -#define CLKID_DSU_CLK 252 -#define CLKID_CPU1_CLK 253 -#define CLKID_CPU2_CLK 254 -#define CLKID_CPU3_CLK 255 - -#endif /* __G12A_CLKC_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/gxbb-aoclkc.h b/sys/gnu/dts/include/dt-bindings/clock/gxbb-aoclkc.h deleted file mode 100644 index ec3b26319fc..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/gxbb-aoclkc.h +++ /dev/null @@ -1,74 +0,0 @@ -/* - * This file is provided under a dual BSD/GPLv2 license. When using or - * redistributing this file, you may do so under either license. - * - * GPL LICENSE SUMMARY - * - * Copyright (c) 2016 BayLibre, SAS. - * Author: Neil Armstrong - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, see . - * The full GNU General Public License is included in this distribution - * in the file called COPYING. - * - * BSD LICENSE - * - * Copyright (c) 2016 BayLibre, SAS. - * Author: Neil Armstrong - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Intel Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef DT_BINDINGS_CLOCK_AMLOGIC_MESON_GXBB_AOCLK -#define DT_BINDINGS_CLOCK_AMLOGIC_MESON_GXBB_AOCLK - -#define CLKID_AO_REMOTE 0 -#define CLKID_AO_I2C_MASTER 1 -#define CLKID_AO_I2C_SLAVE 2 -#define CLKID_AO_UART1 3 -#define CLKID_AO_UART2 4 -#define CLKID_AO_IR_BLASTER 5 -#define CLKID_AO_CEC_32K 6 -#define CLKID_AO_CTS_OSCIN 7 -#define CLKID_AO_32K_PRE 8 -#define CLKID_AO_32K_DIV 9 -#define CLKID_AO_32K_SEL 10 -#define CLKID_AO_32K 11 -#define CLKID_AO_CTS_RTC_OSCIN 12 -#define CLKID_AO_CLK81 13 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/gxbb-clkc.h b/sys/gnu/dts/include/dt-bindings/clock/gxbb-clkc.h deleted file mode 100644 index db0763e9617..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/gxbb-clkc.h +++ /dev/null @@ -1,150 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * GXBB clock tree IDs - */ - -#ifndef __GXBB_CLKC_H -#define __GXBB_CLKC_H - -#define CLKID_SYS_PLL 0 -#define CLKID_HDMI_PLL 2 -#define CLKID_FIXED_PLL 3 -#define CLKID_FCLK_DIV2 4 -#define CLKID_FCLK_DIV3 5 -#define CLKID_FCLK_DIV4 6 -#define CLKID_FCLK_DIV5 7 -#define CLKID_FCLK_DIV7 8 -#define CLKID_GP0_PLL 9 -#define CLKID_CLK81 12 -#define CLKID_MPLL0 13 -#define CLKID_MPLL1 14 -#define CLKID_MPLL2 15 -#define CLKID_DDR 16 -#define CLKID_DOS 17 -#define CLKID_ISA 18 -#define CLKID_PL301 19 -#define CLKID_PERIPHS 20 -#define CLKID_SPICC 21 -#define CLKID_I2C 22 -#define CLKID_SAR_ADC 23 -#define CLKID_SMART_CARD 24 -#define CLKID_RNG0 25 -#define CLKID_UART0 26 -#define CLKID_SDHC 27 -#define CLKID_STREAM 28 -#define CLKID_ASYNC_FIFO 29 -#define CLKID_SDIO 30 -#define CLKID_ABUF 31 -#define CLKID_HIU_IFACE 32 -#define CLKID_ASSIST_MISC 33 -#define CLKID_SPI 34 -#define CLKID_ETH 36 -#define CLKID_I2S_SPDIF 35 -#define CLKID_DEMUX 37 -#define CLKID_AIU_GLUE 38 -#define CLKID_IEC958 39 -#define CLKID_I2S_OUT 40 -#define CLKID_AMCLK 41 -#define CLKID_AIFIFO2 42 -#define CLKID_MIXER 43 -#define CLKID_MIXER_IFACE 44 -#define CLKID_ADC 45 -#define CLKID_BLKMV 46 -#define CLKID_AIU 47 -#define CLKID_UART1 48 -#define CLKID_G2D 49 -#define CLKID_USB0 50 -#define CLKID_USB1 51 -#define CLKID_RESET 52 -#define CLKID_NAND 53 -#define CLKID_DOS_PARSER 54 -#define CLKID_USB 55 -#define CLKID_VDIN1 56 -#define CLKID_AHB_ARB0 57 -#define CLKID_EFUSE 58 -#define CLKID_BOOT_ROM 59 -#define CLKID_AHB_DATA_BUS 60 -#define CLKID_AHB_CTRL_BUS 61 -#define CLKID_HDMI_INTR_SYNC 62 -#define CLKID_HDMI_PCLK 63 -#define CLKID_USB1_DDR_BRIDGE 64 -#define CLKID_USB0_DDR_BRIDGE 65 -#define CLKID_MMC_PCLK 66 -#define CLKID_DVIN 67 -#define CLKID_UART2 68 -#define CLKID_SANA 69 -#define CLKID_VPU_INTR 70 -#define CLKID_SEC_AHB_AHB3_BRIDGE 71 -#define CLKID_CLK81_A53 72 -#define CLKID_VCLK2_VENCI0 73 -#define CLKID_VCLK2_VENCI1 74 -#define CLKID_VCLK2_VENCP0 75 -#define CLKID_VCLK2_VENCP1 76 -#define CLKID_GCLK_VENCI_INT0 77 -#define CLKID_GCLK_VENCI_INT 78 -#define CLKID_DAC_CLK 79 -#define CLKID_AOCLK_GATE 80 -#define CLKID_IEC958_GATE 81 -#define CLKID_ENC480P 82 -#define CLKID_RNG1 83 -#define CLKID_GCLK_VENCI_INT1 84 -#define CLKID_VCLK2_VENCLMCC 85 -#define CLKID_VCLK2_VENCL 86 -#define CLKID_VCLK_OTHER 87 -#define CLKID_EDP 88 -#define CLKID_AO_MEDIA_CPU 89 -#define CLKID_AO_AHB_SRAM 90 -#define CLKID_AO_AHB_BUS 91 -#define CLKID_AO_IFACE 92 -#define CLKID_AO_I2C 93 -#define CLKID_SD_EMMC_A 94 -#define CLKID_SD_EMMC_B 95 -#define CLKID_SD_EMMC_C 96 -#define CLKID_SAR_ADC_CLK 97 -#define CLKID_SAR_ADC_SEL 98 -#define CLKID_MALI_0_SEL 100 -#define CLKID_MALI_0 102 -#define CLKID_MALI_1_SEL 103 -#define CLKID_MALI_1 105 -#define CLKID_MALI 106 -#define CLKID_CTS_AMCLK 107 -#define CLKID_CTS_MCLK_I958 110 -#define CLKID_CTS_I958 113 -#define CLKID_32K_CLK 114 -#define CLKID_SD_EMMC_A_CLK0 119 -#define CLKID_SD_EMMC_B_CLK0 122 -#define CLKID_SD_EMMC_C_CLK0 125 -#define CLKID_VPU_0_SEL 126 -#define CLKID_VPU_0 128 -#define CLKID_VPU_1_SEL 129 -#define CLKID_VPU_1 131 -#define CLKID_VPU 132 -#define CLKID_VAPB_0_SEL 133 -#define CLKID_VAPB_0 135 -#define CLKID_VAPB_1_SEL 136 -#define CLKID_VAPB_1 138 -#define CLKID_VAPB_SEL 139 -#define CLKID_VAPB 140 -#define CLKID_VDEC_1 153 -#define CLKID_VDEC_HEVC 156 -#define CLKID_GEN_CLK 159 -#define CLKID_VID_PLL 166 -#define CLKID_VCLK 175 -#define CLKID_VCLK2 176 -#define CLKID_VCLK_DIV1 185 -#define CLKID_VCLK_DIV2 186 -#define CLKID_VCLK_DIV4 187 -#define CLKID_VCLK_DIV6 188 -#define CLKID_VCLK_DIV12 189 -#define CLKID_VCLK2_DIV1 190 -#define CLKID_VCLK2_DIV2 191 -#define CLKID_VCLK2_DIV4 192 -#define CLKID_VCLK2_DIV6 193 -#define CLKID_VCLK2_DIV12 194 -#define CLKID_CTS_ENCI 199 -#define CLKID_CTS_ENCP 200 -#define CLKID_CTS_VDAC 201 -#define CLKID_HDMI_TX 202 -#define CLKID_HDMI 205 - -#endif /* __GXBB_CLKC_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/hi3516cv300-clock.h b/sys/gnu/dts/include/dt-bindings/clock/hi3516cv300-clock.h deleted file mode 100644 index ccea1bab7a6..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/hi3516cv300-clock.h +++ /dev/null @@ -1,36 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright (c) 2016 HiSilicon Technologies Co., Ltd. - */ - -#ifndef __DTS_HI3516CV300_CLOCK_H -#define __DTS_HI3516CV300_CLOCK_H - -/* hi3516CV300 core CRG */ -#define HI3516CV300_APB_CLK 0 -#define HI3516CV300_UART0_CLK 1 -#define HI3516CV300_UART1_CLK 2 -#define HI3516CV300_UART2_CLK 3 -#define HI3516CV300_SPI0_CLK 4 -#define HI3516CV300_SPI1_CLK 5 -#define HI3516CV300_FMC_CLK 6 -#define HI3516CV300_MMC0_CLK 7 -#define HI3516CV300_MMC1_CLK 8 -#define HI3516CV300_MMC2_CLK 9 -#define HI3516CV300_MMC3_CLK 10 -#define HI3516CV300_ETH_CLK 11 -#define HI3516CV300_ETH_MACIF_CLK 12 -#define HI3516CV300_DMAC_CLK 13 -#define HI3516CV300_PWM_CLK 14 -#define HI3516CV300_USB2_BUS_CLK 15 -#define HI3516CV300_USB2_OHCI48M_CLK 16 -#define HI3516CV300_USB2_OHCI12M_CLK 17 -#define HI3516CV300_USB2_OTG_UTMI_CLK 18 -#define HI3516CV300_USB2_HST_PHY_CLK 19 -#define HI3516CV300_USB2_UTMI0_CLK 20 -#define HI3516CV300_USB2_PHY_CLK 21 - -/* hi3516CV300 sysctrl CRG */ -#define HI3516CV300_WDT_CLK 1 - -#endif /* __DTS_HI3516CV300_CLOCK_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/hi3519-clock.h b/sys/gnu/dts/include/dt-bindings/clock/hi3519-clock.h deleted file mode 100644 index 43354105f62..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/hi3519-clock.h +++ /dev/null @@ -1,28 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright (c) 2015 HiSilicon Technologies Co., Ltd. - */ - -#ifndef __DTS_HI3519_CLOCK_H -#define __DTS_HI3519_CLOCK_H - -#define HI3519_FMC_CLK 1 -#define HI3519_SPI0_CLK 2 -#define HI3519_SPI1_CLK 3 -#define HI3519_SPI2_CLK 4 -#define HI3519_UART0_CLK 5 -#define HI3519_UART1_CLK 6 -#define HI3519_UART2_CLK 7 -#define HI3519_UART3_CLK 8 -#define HI3519_UART4_CLK 9 -#define HI3519_PWM_CLK 10 -#define HI3519_DMA_CLK 11 -#define HI3519_IR_CLK 12 -#define HI3519_ETH_PHY_CLK 13 -#define HI3519_ETH_MAC_CLK 14 -#define HI3519_ETH_MACIF_CLK 15 -#define HI3519_USB2_BUS_CLK 16 -#define HI3519_USB2_PORT_CLK 17 -#define HI3519_USB3_CLK 18 - -#endif /* __DTS_HI3519_CLOCK_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/hi3620-clock.h b/sys/gnu/dts/include/dt-bindings/clock/hi3620-clock.h deleted file mode 100644 index f9dc6f6d302..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/hi3620-clock.h +++ /dev/null @@ -1,143 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright (c) 2012-2013 Hisilicon Limited. - * Copyright (c) 2012-2013 Linaro Limited. - * - * Author: Haojian Zhuang - * Xin Li - */ - -#ifndef __DTS_HI3620_CLOCK_H -#define __DTS_HI3620_CLOCK_H - -#define HI3620_NONE_CLOCK 0 - -/* fixed rate & fixed factor clocks */ -#define HI3620_OSC32K 1 -#define HI3620_OSC26M 2 -#define HI3620_PCLK 3 -#define HI3620_PLL_ARM0 4 -#define HI3620_PLL_ARM1 5 -#define HI3620_PLL_PERI 6 -#define HI3620_PLL_USB 7 -#define HI3620_PLL_HDMI 8 -#define HI3620_PLL_GPU 9 -#define HI3620_RCLK_TCXO 10 -#define HI3620_RCLK_CFGAXI 11 -#define HI3620_RCLK_PICO 12 - -/* mux clocks */ -#define HI3620_TIMER0_MUX 32 -#define HI3620_TIMER1_MUX 33 -#define HI3620_TIMER2_MUX 34 -#define HI3620_TIMER3_MUX 35 -#define HI3620_TIMER4_MUX 36 -#define HI3620_TIMER5_MUX 37 -#define HI3620_TIMER6_MUX 38 -#define HI3620_TIMER7_MUX 39 -#define HI3620_TIMER8_MUX 40 -#define HI3620_TIMER9_MUX 41 -#define HI3620_UART0_MUX 42 -#define HI3620_UART1_MUX 43 -#define HI3620_UART2_MUX 44 -#define HI3620_UART3_MUX 45 -#define HI3620_UART4_MUX 46 -#define HI3620_SPI0_MUX 47 -#define HI3620_SPI1_MUX 48 -#define HI3620_SPI2_MUX 49 -#define HI3620_SAXI_MUX 50 -#define HI3620_PWM0_MUX 51 -#define HI3620_PWM1_MUX 52 -#define HI3620_SD_MUX 53 -#define HI3620_MMC1_MUX 54 -#define HI3620_MMC1_MUX2 55 -#define HI3620_G2D_MUX 56 -#define HI3620_VENC_MUX 57 -#define HI3620_VDEC_MUX 58 -#define HI3620_VPP_MUX 59 -#define HI3620_EDC0_MUX 60 -#define HI3620_LDI0_MUX 61 -#define HI3620_EDC1_MUX 62 -#define HI3620_LDI1_MUX 63 -#define HI3620_RCLK_HSIC 64 -#define HI3620_MMC2_MUX 65 -#define HI3620_MMC3_MUX 66 - -/* divider clocks */ -#define HI3620_SHAREAXI_DIV 128 -#define HI3620_CFGAXI_DIV 129 -#define HI3620_SD_DIV 130 -#define HI3620_MMC1_DIV 131 -#define HI3620_HSIC_DIV 132 -#define HI3620_MMC2_DIV 133 -#define HI3620_MMC3_DIV 134 - -/* gate clocks */ -#define HI3620_TIMERCLK01 160 -#define HI3620_TIMER_RCLK01 161 -#define HI3620_TIMERCLK23 162 -#define HI3620_TIMER_RCLK23 163 -#define HI3620_TIMERCLK45 164 -#define HI3620_TIMERCLK67 165 -#define HI3620_TIMERCLK89 166 -#define HI3620_RTCCLK 167 -#define HI3620_KPC_CLK 168 -#define HI3620_GPIOCLK0 169 -#define HI3620_GPIOCLK1 170 -#define HI3620_GPIOCLK2 171 -#define HI3620_GPIOCLK3 172 -#define HI3620_GPIOCLK4 173 -#define HI3620_GPIOCLK5 174 -#define HI3620_GPIOCLK6 175 -#define HI3620_GPIOCLK7 176 -#define HI3620_GPIOCLK8 177 -#define HI3620_GPIOCLK9 178 -#define HI3620_GPIOCLK10 179 -#define HI3620_GPIOCLK11 180 -#define HI3620_GPIOCLK12 181 -#define HI3620_GPIOCLK13 182 -#define HI3620_GPIOCLK14 183 -#define HI3620_GPIOCLK15 184 -#define HI3620_GPIOCLK16 185 -#define HI3620_GPIOCLK17 186 -#define HI3620_GPIOCLK18 187 -#define HI3620_GPIOCLK19 188 -#define HI3620_GPIOCLK20 189 -#define HI3620_GPIOCLK21 190 -#define HI3620_DPHY0_CLK 191 -#define HI3620_DPHY1_CLK 192 -#define HI3620_DPHY2_CLK 193 -#define HI3620_USBPHY_CLK 194 -#define HI3620_ACP_CLK 195 -#define HI3620_PWMCLK0 196 -#define HI3620_PWMCLK1 197 -#define HI3620_UARTCLK0 198 -#define HI3620_UARTCLK1 199 -#define HI3620_UARTCLK2 200 -#define HI3620_UARTCLK3 201 -#define HI3620_UARTCLK4 202 -#define HI3620_SPICLK0 203 -#define HI3620_SPICLK1 204 -#define HI3620_SPICLK2 205 -#define HI3620_I2CCLK0 206 -#define HI3620_I2CCLK1 207 -#define HI3620_I2CCLK2 208 -#define HI3620_I2CCLK3 209 -#define HI3620_SCI_CLK 210 -#define HI3620_DDRC_PER_CLK 211 -#define HI3620_DMAC_CLK 212 -#define HI3620_USB2DVC_CLK 213 -#define HI3620_SD_CLK 214 -#define HI3620_MMC_CLK1 215 -#define HI3620_MMC_CLK2 216 -#define HI3620_MMC_CLK3 217 -#define HI3620_MCU_CLK 218 - -#define HI3620_SD_CIUCLK 0 -#define HI3620_MMC_CIUCLK1 1 -#define HI3620_MMC_CIUCLK2 2 -#define HI3620_MMC_CIUCLK3 3 - -#define HI3620_NR_CLKS 219 - -#endif /* __DTS_HI3620_CLOCK_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/hi3660-clock.h b/sys/gnu/dts/include/dt-bindings/clock/hi3660-clock.h deleted file mode 100644 index e1374e18094..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/hi3660-clock.h +++ /dev/null @@ -1,214 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright (c) 2016-2017 Linaro Ltd. - * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd. - */ - -#ifndef __DTS_HI3660_CLOCK_H -#define __DTS_HI3660_CLOCK_H - -/* fixed rate clocks */ -#define HI3660_CLKIN_SYS 0 -#define HI3660_CLKIN_REF 1 -#define HI3660_CLK_FLL_SRC 2 -#define HI3660_CLK_PPLL0 3 -#define HI3660_CLK_PPLL1 4 -#define HI3660_CLK_PPLL2 5 -#define HI3660_CLK_PPLL3 6 -#define HI3660_CLK_SCPLL 7 -#define HI3660_PCLK 8 -#define HI3660_CLK_UART0_DBG 9 -#define HI3660_CLK_UART6 10 -#define HI3660_OSC32K 11 -#define HI3660_OSC19M 12 -#define HI3660_CLK_480M 13 -#define HI3660_CLK_INV 14 - -/* clk in crgctrl */ -#define HI3660_FACTOR_UART3 15 -#define HI3660_CLK_FACTOR_MMC 16 -#define HI3660_CLK_GATE_I2C0 17 -#define HI3660_CLK_GATE_I2C1 18 -#define HI3660_CLK_GATE_I2C2 19 -#define HI3660_CLK_GATE_I2C6 20 -#define HI3660_CLK_DIV_SYSBUS 21 -#define HI3660_CLK_DIV_320M 22 -#define HI3660_CLK_DIV_A53 23 -#define HI3660_CLK_GATE_SPI0 24 -#define HI3660_CLK_GATE_SPI2 25 -#define HI3660_PCIEPHY_REF 26 -#define HI3660_CLK_ABB_USB 27 -#define HI3660_HCLK_GATE_SDIO0 28 -#define HI3660_HCLK_GATE_SD 29 -#define HI3660_CLK_GATE_AOMM 30 -#define HI3660_PCLK_GPIO0 31 -#define HI3660_PCLK_GPIO1 32 -#define HI3660_PCLK_GPIO2 33 -#define HI3660_PCLK_GPIO3 34 -#define HI3660_PCLK_GPIO4 35 -#define HI3660_PCLK_GPIO5 36 -#define HI3660_PCLK_GPIO6 37 -#define HI3660_PCLK_GPIO7 38 -#define HI3660_PCLK_GPIO8 39 -#define HI3660_PCLK_GPIO9 40 -#define HI3660_PCLK_GPIO10 41 -#define HI3660_PCLK_GPIO11 42 -#define HI3660_PCLK_GPIO12 43 -#define HI3660_PCLK_GPIO13 44 -#define HI3660_PCLK_GPIO14 45 -#define HI3660_PCLK_GPIO15 46 -#define HI3660_PCLK_GPIO16 47 -#define HI3660_PCLK_GPIO17 48 -#define HI3660_PCLK_GPIO18 49 -#define HI3660_PCLK_GPIO19 50 -#define HI3660_PCLK_GPIO20 51 -#define HI3660_PCLK_GPIO21 52 -#define HI3660_CLK_GATE_SPI3 53 -#define HI3660_CLK_GATE_I2C7 54 -#define HI3660_CLK_GATE_I2C3 55 -#define HI3660_CLK_GATE_SPI1 56 -#define HI3660_CLK_GATE_UART1 57 -#define HI3660_CLK_GATE_UART2 58 -#define HI3660_CLK_GATE_UART4 59 -#define HI3660_CLK_GATE_UART5 60 -#define HI3660_CLK_GATE_I2C4 61 -#define HI3660_CLK_GATE_DMAC 62 -#define HI3660_PCLK_GATE_DSS 63 -#define HI3660_ACLK_GATE_DSS 64 -#define HI3660_CLK_GATE_LDI1 65 -#define HI3660_CLK_GATE_LDI0 66 -#define HI3660_CLK_GATE_VIVOBUS 67 -#define HI3660_CLK_GATE_EDC0 68 -#define HI3660_CLK_GATE_TXDPHY0_CFG 69 -#define HI3660_CLK_GATE_TXDPHY0_REF 70 -#define HI3660_CLK_GATE_TXDPHY1_CFG 71 -#define HI3660_CLK_GATE_TXDPHY1_REF 72 -#define HI3660_ACLK_GATE_USB3OTG 73 -#define HI3660_CLK_GATE_SPI4 74 -#define HI3660_CLK_GATE_SD 75 -#define HI3660_CLK_GATE_SDIO0 76 -#define HI3660_CLK_GATE_UFS_SUBSYS 77 -#define HI3660_PCLK_GATE_DSI0 78 -#define HI3660_PCLK_GATE_DSI1 79 -#define HI3660_ACLK_GATE_PCIE 80 -#define HI3660_PCLK_GATE_PCIE_SYS 81 -#define HI3660_CLK_GATE_PCIEAUX 82 -#define HI3660_PCLK_GATE_PCIE_PHY 83 -#define HI3660_CLK_ANDGT_LDI0 84 -#define HI3660_CLK_ANDGT_LDI1 85 -#define HI3660_CLK_ANDGT_EDC0 86 -#define HI3660_CLK_GATE_UFSPHY_GT 87 -#define HI3660_CLK_ANDGT_MMC 88 -#define HI3660_CLK_ANDGT_SD 89 -#define HI3660_CLK_A53HPM_ANDGT 90 -#define HI3660_CLK_ANDGT_SDIO 91 -#define HI3660_CLK_ANDGT_UART0 92 -#define HI3660_CLK_ANDGT_UART1 93 -#define HI3660_CLK_ANDGT_UARTH 94 -#define HI3660_CLK_ANDGT_SPI 95 -#define HI3660_CLK_VIVOBUS_ANDGT 96 -#define HI3660_CLK_AOMM_ANDGT 97 -#define HI3660_CLK_320M_PLL_GT 98 -#define HI3660_AUTODIV_EMMC0BUS 99 -#define HI3660_AUTODIV_SYSBUS 100 -#define HI3660_CLK_GATE_UFSPHY_CFG 101 -#define HI3660_CLK_GATE_UFSIO_REF 102 -#define HI3660_CLK_MUX_SYSBUS 103 -#define HI3660_CLK_MUX_UART0 104 -#define HI3660_CLK_MUX_UART1 105 -#define HI3660_CLK_MUX_UARTH 106 -#define HI3660_CLK_MUX_SPI 107 -#define HI3660_CLK_MUX_I2C 108 -#define HI3660_CLK_MUX_MMC_PLL 109 -#define HI3660_CLK_MUX_LDI1 110 -#define HI3660_CLK_MUX_LDI0 111 -#define HI3660_CLK_MUX_SD_PLL 112 -#define HI3660_CLK_MUX_SD_SYS 113 -#define HI3660_CLK_MUX_EDC0 114 -#define HI3660_CLK_MUX_SDIO_SYS 115 -#define HI3660_CLK_MUX_SDIO_PLL 116 -#define HI3660_CLK_MUX_VIVOBUS 117 -#define HI3660_CLK_MUX_A53HPM 118 -#define HI3660_CLK_MUX_320M 119 -#define HI3660_CLK_MUX_IOPERI 120 -#define HI3660_CLK_DIV_UART0 121 -#define HI3660_CLK_DIV_UART1 122 -#define HI3660_CLK_DIV_UARTH 123 -#define HI3660_CLK_DIV_MMC 124 -#define HI3660_CLK_DIV_SD 125 -#define HI3660_CLK_DIV_EDC0 126 -#define HI3660_CLK_DIV_LDI0 127 -#define HI3660_CLK_DIV_SDIO 128 -#define HI3660_CLK_DIV_LDI1 129 -#define HI3660_CLK_DIV_SPI 130 -#define HI3660_CLK_DIV_VIVOBUS 131 -#define HI3660_CLK_DIV_I2C 132 -#define HI3660_CLK_DIV_UFSPHY 133 -#define HI3660_CLK_DIV_CFGBUS 134 -#define HI3660_CLK_DIV_MMC0BUS 135 -#define HI3660_CLK_DIV_MMC1BUS 136 -#define HI3660_CLK_DIV_UFSPERI 137 -#define HI3660_CLK_DIV_AOMM 138 -#define HI3660_CLK_DIV_IOPERI 139 -#define HI3660_VENC_VOLT_HOLD 140 -#define HI3660_PERI_VOLT_HOLD 141 -#define HI3660_CLK_GATE_VENC 142 -#define HI3660_CLK_GATE_VDEC 143 -#define HI3660_CLK_ANDGT_VENC 144 -#define HI3660_CLK_ANDGT_VDEC 145 -#define HI3660_CLK_MUX_VENC 146 -#define HI3660_CLK_MUX_VDEC 147 -#define HI3660_CLK_DIV_VENC 148 -#define HI3660_CLK_DIV_VDEC 149 -#define HI3660_CLK_FAC_ISP_SNCLK 150 -#define HI3660_CLK_GATE_ISP_SNCLK0 151 -#define HI3660_CLK_GATE_ISP_SNCLK1 152 -#define HI3660_CLK_GATE_ISP_SNCLK2 153 -#define HI3660_CLK_ANGT_ISP_SNCLK 154 -#define HI3660_CLK_MUX_ISP_SNCLK 155 -#define HI3660_CLK_DIV_ISP_SNCLK 156 - -/* clk in pmuctrl */ -#define HI3660_GATE_ABB_192 0 - -/* clk in pctrl */ -#define HI3660_GATE_UFS_TCXO_EN 0 -#define HI3660_GATE_USB_TCXO_EN 1 - -/* clk in sctrl */ -#define HI3660_PCLK_AO_GPIO0 0 -#define HI3660_PCLK_AO_GPIO1 1 -#define HI3660_PCLK_AO_GPIO2 2 -#define HI3660_PCLK_AO_GPIO3 3 -#define HI3660_PCLK_AO_GPIO4 4 -#define HI3660_PCLK_AO_GPIO5 5 -#define HI3660_PCLK_AO_GPIO6 6 -#define HI3660_PCLK_GATE_MMBUF 7 -#define HI3660_CLK_GATE_DSS_AXI_MM 8 -#define HI3660_PCLK_MMBUF_ANDGT 9 -#define HI3660_CLK_MMBUF_PLL_ANDGT 10 -#define HI3660_CLK_FLL_MMBUF_ANDGT 11 -#define HI3660_CLK_SYS_MMBUF_ANDGT 12 -#define HI3660_CLK_GATE_PCIEPHY_GT 13 -#define HI3660_ACLK_MUX_MMBUF 14 -#define HI3660_CLK_SW_MMBUF 15 -#define HI3660_CLK_DIV_AOBUS 16 -#define HI3660_PCLK_DIV_MMBUF 17 -#define HI3660_ACLK_DIV_MMBUF 18 -#define HI3660_CLK_DIV_PCIEPHY 19 - -/* clk in iomcu */ -#define HI3660_CLK_I2C0_IOMCU 0 -#define HI3660_CLK_I2C1_IOMCU 1 -#define HI3660_CLK_I2C2_IOMCU 2 -#define HI3660_CLK_I2C6_IOMCU 3 -#define HI3660_CLK_IOMCU_PERI0 4 - -/* clk in stub clock */ -#define HI3660_CLK_STUB_CLUSTER0 0 -#define HI3660_CLK_STUB_CLUSTER1 1 -#define HI3660_CLK_STUB_GPU 2 -#define HI3660_CLK_STUB_DDR 3 -#define HI3660_CLK_STUB_NUM 4 - -#endif /* __DTS_HI3660_CLOCK_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/hi3670-clock.h b/sys/gnu/dts/include/dt-bindings/clock/hi3670-clock.h deleted file mode 100644 index fa48583f87d..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/hi3670-clock.h +++ /dev/null @@ -1,348 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Device Tree binding constants for HiSilicon Hi3670 SoC - * - * Copyright (c) 2001-2021, Huawei Tech. Co., Ltd. - * Copyright (c) 2018 Linaro Ltd. - */ - -#ifndef __DT_BINDINGS_CLOCK_HI3670_H -#define __DT_BINDINGS_CLOCK_HI3670_H - -/* clk in stub clock */ -#define HI3670_CLK_STUB_CLUSTER0 0 -#define HI3670_CLK_STUB_CLUSTER1 1 -#define HI3670_CLK_STUB_GPU 2 -#define HI3670_CLK_STUB_DDR 3 -#define HI3670_CLK_STUB_DDR_VOTE 4 -#define HI3670_CLK_STUB_DDR_LIMIT 5 -#define HI3670_CLK_STUB_NUM 6 - -/* clk in crg clock */ -#define HI3670_CLKIN_SYS 0 -#define HI3670_CLKIN_REF 1 -#define HI3670_CLK_FLL_SRC 2 -#define HI3670_CLK_PPLL0 3 -#define HI3670_CLK_PPLL1 4 -#define HI3670_CLK_PPLL2 5 -#define HI3670_CLK_PPLL3 6 -#define HI3670_CLK_PPLL4 7 -#define HI3670_CLK_PPLL6 8 -#define HI3670_CLK_PPLL7 9 -#define HI3670_CLK_PPLL_PCIE 10 -#define HI3670_CLK_PCIEPLL_REV 11 -#define HI3670_CLK_SCPLL 12 -#define HI3670_PCLK 13 -#define HI3670_CLK_UART0_DBG 14 -#define HI3670_CLK_UART6 15 -#define HI3670_OSC32K 16 -#define HI3670_OSC19M 17 -#define HI3670_CLK_480M 18 -#define HI3670_CLK_INVALID 19 -#define HI3670_CLK_DIV_SYSBUS 20 -#define HI3670_CLK_FACTOR_MMC 21 -#define HI3670_CLK_SD_SYS 22 -#define HI3670_CLK_SDIO_SYS 23 -#define HI3670_CLK_DIV_A53HPM 24 -#define HI3670_CLK_DIV_320M 25 -#define HI3670_PCLK_GATE_UART0 26 -#define HI3670_CLK_FACTOR_UART0 27 -#define HI3670_CLK_FACTOR_USB3PHY_PLL 28 -#define HI3670_CLK_GATE_ABB_USB 29 -#define HI3670_CLK_GATE_UFSPHY_REF 30 -#define HI3670_ICS_VOLT_HIGH 31 -#define HI3670_ICS_VOLT_MIDDLE 32 -#define HI3670_VENC_VOLT_HOLD 33 -#define HI3670_VDEC_VOLT_HOLD 34 -#define HI3670_EDC_VOLT_HOLD 35 -#define HI3670_CLK_ISP_SNCLK_FAC 36 -#define HI3670_CLK_FACTOR_RXDPHY 37 -#define HI3670_AUTODIV_SYSBUS 38 -#define HI3670_AUTODIV_EMMC0BUS 39 -#define HI3670_PCLK_ANDGT_MMC1_PCIE 40 -#define HI3670_CLK_GATE_VCODECBUS_GT 41 -#define HI3670_CLK_ANDGT_SD 42 -#define HI3670_CLK_SD_SYS_GT 43 -#define HI3670_CLK_ANDGT_SDIO 44 -#define HI3670_CLK_SDIO_SYS_GT 45 -#define HI3670_CLK_A53HPM_ANDGT 46 -#define HI3670_CLK_320M_PLL_GT 47 -#define HI3670_CLK_ANDGT_UARTH 48 -#define HI3670_CLK_ANDGT_UARTL 49 -#define HI3670_CLK_ANDGT_UART0 50 -#define HI3670_CLK_ANDGT_SPI 51 -#define HI3670_CLK_ANDGT_PCIEAXI 52 -#define HI3670_CLK_DIV_AO_ASP_GT 53 -#define HI3670_CLK_GATE_CSI_TRANS 54 -#define HI3670_CLK_GATE_DSI_TRANS 55 -#define HI3670_CLK_ANDGT_PTP 56 -#define HI3670_CLK_ANDGT_OUT0 57 -#define HI3670_CLK_ANDGT_OUT1 58 -#define HI3670_CLKGT_DP_AUDIO_PLL_AO 59 -#define HI3670_CLK_ANDGT_VDEC 60 -#define HI3670_CLK_ANDGT_VENC 61 -#define HI3670_CLK_ISP_SNCLK_ANGT 62 -#define HI3670_CLK_ANDGT_RXDPHY 63 -#define HI3670_CLK_ANDGT_ICS 64 -#define HI3670_AUTODIV_DMABUS 65 -#define HI3670_CLK_MUX_SYSBUS 66 -#define HI3670_CLK_MUX_VCODECBUS 67 -#define HI3670_CLK_MUX_SD_SYS 68 -#define HI3670_CLK_MUX_SD_PLL 69 -#define HI3670_CLK_MUX_SDIO_SYS 70 -#define HI3670_CLK_MUX_SDIO_PLL 71 -#define HI3670_CLK_MUX_A53HPM 72 -#define HI3670_CLK_MUX_320M 73 -#define HI3670_CLK_MUX_UARTH 74 -#define HI3670_CLK_MUX_UARTL 75 -#define HI3670_CLK_MUX_UART0 76 -#define HI3670_CLK_MUX_I2C 77 -#define HI3670_CLK_MUX_SPI 78 -#define HI3670_CLK_MUX_PCIEAXI 79 -#define HI3670_CLK_MUX_AO_ASP 80 -#define HI3670_CLK_MUX_VDEC 81 -#define HI3670_CLK_MUX_VENC 82 -#define HI3670_CLK_ISP_SNCLK_MUX0 83 -#define HI3670_CLK_ISP_SNCLK_MUX1 84 -#define HI3670_CLK_ISP_SNCLK_MUX2 85 -#define HI3670_CLK_MUX_RXDPHY_CFG 86 -#define HI3670_CLK_MUX_ICS 87 -#define HI3670_CLK_DIV_CFGBUS 88 -#define HI3670_CLK_DIV_MMC0BUS 89 -#define HI3670_CLK_DIV_MMC1BUS 90 -#define HI3670_PCLK_DIV_MMC1_PCIE 91 -#define HI3670_CLK_DIV_VCODECBUS 92 -#define HI3670_CLK_DIV_SD 93 -#define HI3670_CLK_DIV_SDIO 94 -#define HI3670_CLK_DIV_UARTH 95 -#define HI3670_CLK_DIV_UARTL 96 -#define HI3670_CLK_DIV_UART0 97 -#define HI3670_CLK_DIV_I2C 98 -#define HI3670_CLK_DIV_SPI 99 -#define HI3670_CLK_DIV_PCIEAXI 100 -#define HI3670_CLK_DIV_AO_ASP 101 -#define HI3670_CLK_DIV_CSI_TRANS 102 -#define HI3670_CLK_DIV_DSI_TRANS 103 -#define HI3670_CLK_DIV_PTP 104 -#define HI3670_CLK_DIV_CLKOUT0_PLL 105 -#define HI3670_CLK_DIV_CLKOUT1_PLL 106 -#define HI3670_CLKDIV_DP_AUDIO_PLL_AO 107 -#define HI3670_CLK_DIV_VDEC 108 -#define HI3670_CLK_DIV_VENC 109 -#define HI3670_CLK_ISP_SNCLK_DIV0 110 -#define HI3670_CLK_ISP_SNCLK_DIV1 111 -#define HI3670_CLK_ISP_SNCLK_DIV2 112 -#define HI3670_CLK_DIV_ICS 113 -#define HI3670_PPLL1_EN_ACPU 114 -#define HI3670_PPLL2_EN_ACPU 115 -#define HI3670_PPLL3_EN_ACPU 116 -#define HI3670_PPLL1_GT_CPU 117 -#define HI3670_PPLL2_GT_CPU 118 -#define HI3670_PPLL3_GT_CPU 119 -#define HI3670_CLK_GATE_PPLL2_MEDIA 120 -#define HI3670_CLK_GATE_PPLL3_MEDIA 121 -#define HI3670_CLK_GATE_PPLL4_MEDIA 122 -#define HI3670_CLK_GATE_PPLL6_MEDIA 123 -#define HI3670_CLK_GATE_PPLL7_MEDIA 124 -#define HI3670_PCLK_GPIO0 125 -#define HI3670_PCLK_GPIO1 126 -#define HI3670_PCLK_GPIO2 127 -#define HI3670_PCLK_GPIO3 128 -#define HI3670_PCLK_GPIO4 129 -#define HI3670_PCLK_GPIO5 130 -#define HI3670_PCLK_GPIO6 131 -#define HI3670_PCLK_GPIO7 132 -#define HI3670_PCLK_GPIO8 133 -#define HI3670_PCLK_GPIO9 134 -#define HI3670_PCLK_GPIO10 135 -#define HI3670_PCLK_GPIO11 136 -#define HI3670_PCLK_GPIO12 137 -#define HI3670_PCLK_GPIO13 138 -#define HI3670_PCLK_GPIO14 139 -#define HI3670_PCLK_GPIO15 140 -#define HI3670_PCLK_GPIO16 141 -#define HI3670_PCLK_GPIO17 142 -#define HI3670_PCLK_GPIO20 143 -#define HI3670_PCLK_GPIO21 144 -#define HI3670_PCLK_GATE_DSI0 145 -#define HI3670_PCLK_GATE_DSI1 146 -#define HI3670_HCLK_GATE_USB3OTG 147 -#define HI3670_ACLK_GATE_USB3DVFS 148 -#define HI3670_HCLK_GATE_SDIO 149 -#define HI3670_PCLK_GATE_PCIE_SYS 150 -#define HI3670_PCLK_GATE_PCIE_PHY 151 -#define HI3670_PCLK_GATE_MMC1_PCIE 152 -#define HI3670_PCLK_GATE_MMC0_IOC 153 -#define HI3670_PCLK_GATE_MMC1_IOC 154 -#define HI3670_CLK_GATE_DMAC 155 -#define HI3670_CLK_GATE_VCODECBUS2DDR 156 -#define HI3670_CLK_CCI400_BYPASS 157 -#define HI3670_CLK_GATE_CCI400 158 -#define HI3670_CLK_GATE_SD 159 -#define HI3670_HCLK_GATE_SD 160 -#define HI3670_CLK_GATE_SDIO 161 -#define HI3670_CLK_GATE_A57HPM 162 -#define HI3670_CLK_GATE_A53HPM 163 -#define HI3670_CLK_GATE_PA_A53 164 -#define HI3670_CLK_GATE_PA_A57 165 -#define HI3670_CLK_GATE_PA_G3D 166 -#define HI3670_CLK_GATE_GPUHPM 167 -#define HI3670_CLK_GATE_PERIHPM 168 -#define HI3670_CLK_GATE_AOHPM 169 -#define HI3670_CLK_GATE_UART1 170 -#define HI3670_CLK_GATE_UART4 171 -#define HI3670_PCLK_GATE_UART1 172 -#define HI3670_PCLK_GATE_UART4 173 -#define HI3670_CLK_GATE_UART2 174 -#define HI3670_CLK_GATE_UART5 175 -#define HI3670_PCLK_GATE_UART2 176 -#define HI3670_PCLK_GATE_UART5 177 -#define HI3670_CLK_GATE_UART0 178 -#define HI3670_CLK_GATE_I2C3 179 -#define HI3670_CLK_GATE_I2C4 180 -#define HI3670_CLK_GATE_I2C7 181 -#define HI3670_PCLK_GATE_I2C3 182 -#define HI3670_PCLK_GATE_I2C4 183 -#define HI3670_PCLK_GATE_I2C7 184 -#define HI3670_CLK_GATE_SPI1 185 -#define HI3670_CLK_GATE_SPI4 186 -#define HI3670_PCLK_GATE_SPI1 187 -#define HI3670_PCLK_GATE_SPI4 188 -#define HI3670_CLK_GATE_USB3OTG_REF 189 -#define HI3670_CLK_GATE_USB2PHY_REF 190 -#define HI3670_CLK_GATE_PCIEAUX 191 -#define HI3670_ACLK_GATE_PCIE 192 -#define HI3670_CLK_GATE_MMC1_PCIEAXI 193 -#define HI3670_CLK_GATE_PCIEPHY_REF 194 -#define HI3670_CLK_GATE_PCIE_DEBOUNCE 195 -#define HI3670_CLK_GATE_PCIEIO 196 -#define HI3670_CLK_GATE_PCIE_HP 197 -#define HI3670_CLK_GATE_AO_ASP 198 -#define HI3670_PCLK_GATE_PCTRL 199 -#define HI3670_CLK_CSI_TRANS_GT 200 -#define HI3670_CLK_DSI_TRANS_GT 201 -#define HI3670_CLK_GATE_PWM 202 -#define HI3670_ABB_AUDIO_EN0 203 -#define HI3670_ABB_AUDIO_EN1 204 -#define HI3670_ABB_AUDIO_GT_EN0 205 -#define HI3670_ABB_AUDIO_GT_EN1 206 -#define HI3670_CLK_GATE_DP_AUDIO_PLL_AO 207 -#define HI3670_PERI_VOLT_HOLD 208 -#define HI3670_PERI_VOLT_MIDDLE 209 -#define HI3670_CLK_GATE_ISP_SNCLK0 210 -#define HI3670_CLK_GATE_ISP_SNCLK1 211 -#define HI3670_CLK_GATE_ISP_SNCLK2 212 -#define HI3670_CLK_GATE_RXDPHY0_CFG 213 -#define HI3670_CLK_GATE_RXDPHY1_CFG 214 -#define HI3670_CLK_GATE_RXDPHY2_CFG 215 -#define HI3670_CLK_GATE_TXDPHY0_CFG 216 -#define HI3670_CLK_GATE_TXDPHY0_REF 217 -#define HI3670_CLK_GATE_TXDPHY1_CFG 218 -#define HI3670_CLK_GATE_TXDPHY1_REF 219 -#define HI3670_CLK_GATE_MEDIA_TCXO 220 - -/* clk in sctrl */ -#define HI3670_CLK_ANDGT_IOPERI 0 -#define HI3670_CLKANDGT_ASP_SUBSYS_PERI 1 -#define HI3670_CLK_ANGT_ASP_SUBSYS 2 -#define HI3670_CLK_MUX_UFS_SUBSYS 3 -#define HI3670_CLK_MUX_CLKOUT0 4 -#define HI3670_CLK_MUX_CLKOUT1 5 -#define HI3670_CLK_MUX_ASP_SUBSYS_PERI 6 -#define HI3670_CLK_MUX_ASP_PLL 7 -#define HI3670_CLK_DIV_AOBUS 8 -#define HI3670_CLK_DIV_UFS_SUBSYS 9 -#define HI3670_CLK_DIV_IOPERI 10 -#define HI3670_CLK_DIV_CLKOUT0_TCXO 11 -#define HI3670_CLK_DIV_CLKOUT1_TCXO 12 -#define HI3670_CLK_ASP_SUBSYS_PERI_DIV 13 -#define HI3670_CLK_DIV_ASP_SUBSYS 14 -#define HI3670_PPLL0_EN_ACPU 15 -#define HI3670_PPLL0_GT_CPU 16 -#define HI3670_CLK_GATE_PPLL0_MEDIA 17 -#define HI3670_PCLK_GPIO18 18 -#define HI3670_PCLK_GPIO19 19 -#define HI3670_CLK_GATE_SPI 20 -#define HI3670_PCLK_GATE_SPI 21 -#define HI3670_CLK_GATE_UFS_SUBSYS 22 -#define HI3670_CLK_GATE_UFSIO_REF 23 -#define HI3670_PCLK_AO_GPIO0 24 -#define HI3670_PCLK_AO_GPIO1 25 -#define HI3670_PCLK_AO_GPIO2 26 -#define HI3670_PCLK_AO_GPIO3 27 -#define HI3670_PCLK_AO_GPIO4 28 -#define HI3670_PCLK_AO_GPIO5 29 -#define HI3670_PCLK_AO_GPIO6 30 -#define HI3670_CLK_GATE_OUT0 31 -#define HI3670_CLK_GATE_OUT1 32 -#define HI3670_PCLK_GATE_SYSCNT 33 -#define HI3670_CLK_GATE_SYSCNT 34 -#define HI3670_CLK_GATE_ASP_SUBSYS_PERI 35 -#define HI3670_CLK_GATE_ASP_SUBSYS 36 -#define HI3670_CLK_GATE_ASP_TCXO 37 -#define HI3670_CLK_GATE_DP_AUDIO_PLL 38 - -/* clk in pmuctrl */ -#define HI3670_GATE_ABB_192 0 - -/* clk in pctrl */ -#define HI3670_GATE_UFS_TCXO_EN 0 -#define HI3670_GATE_USB_TCXO_EN 1 - -/* clk in iomcu */ -#define HI3670_CLK_GATE_I2C0 0 -#define HI3670_CLK_GATE_I2C1 1 -#define HI3670_CLK_GATE_I2C2 2 -#define HI3670_CLK_GATE_SPI0 3 -#define HI3670_CLK_GATE_SPI2 4 -#define HI3670_CLK_GATE_UART3 5 -#define HI3670_CLK_I2C0_GATE_IOMCU 6 -#define HI3670_CLK_I2C1_GATE_IOMCU 7 -#define HI3670_CLK_I2C2_GATE_IOMCU 8 -#define HI3670_CLK_SPI0_GATE_IOMCU 9 -#define HI3670_CLK_SPI2_GATE_IOMCU 10 -#define HI3670_CLK_UART3_GATE_IOMCU 11 -#define HI3670_CLK_GATE_PERI0_IOMCU 12 - -/* clk in media1 */ -#define HI3670_CLK_GATE_VIVOBUS_ANDGT 0 -#define HI3670_CLK_ANDGT_EDC0 1 -#define HI3670_CLK_ANDGT_LDI0 2 -#define HI3670_CLK_ANDGT_LDI1 3 -#define HI3670_CLK_MMBUF_PLL_ANDGT 4 -#define HI3670_PCLK_MMBUF_ANDGT 5 -#define HI3670_CLK_MUX_VIVOBUS 6 -#define HI3670_CLK_MUX_EDC0 7 -#define HI3670_CLK_MUX_LDI0 8 -#define HI3670_CLK_MUX_LDI1 9 -#define HI3670_CLK_SW_MMBUF 10 -#define HI3670_CLK_DIV_VIVOBUS 11 -#define HI3670_CLK_DIV_EDC0 12 -#define HI3670_CLK_DIV_LDI0 13 -#define HI3670_CLK_DIV_LDI1 14 -#define HI3670_ACLK_DIV_MMBUF 15 -#define HI3670_PCLK_DIV_MMBUF 16 -#define HI3670_ACLK_GATE_NOC_DSS 17 -#define HI3670_PCLK_GATE_NOC_DSS_CFG 18 -#define HI3670_PCLK_GATE_MMBUF_CFG 19 -#define HI3670_PCLK_GATE_DISP_NOC_SUBSYS 20 -#define HI3670_ACLK_GATE_DISP_NOC_SUBSYS 21 -#define HI3670_PCLK_GATE_DSS 22 -#define HI3670_ACLK_GATE_DSS 23 -#define HI3670_CLK_GATE_VIVOBUSFREQ 24 -#define HI3670_CLK_GATE_EDC0 25 -#define HI3670_CLK_GATE_LDI0 26 -#define HI3670_CLK_GATE_LDI1FREQ 27 -#define HI3670_CLK_GATE_BRG 28 -#define HI3670_ACLK_GATE_ASC 29 -#define HI3670_CLK_GATE_DSS_AXI_MM 30 -#define HI3670_CLK_GATE_MMBUF 31 -#define HI3670_PCLK_GATE_MMBUF 32 -#define HI3670_CLK_GATE_ATDIV_VIVO 33 - -/* clk in media2 */ -#define HI3670_CLK_GATE_VDECFREQ 0 -#define HI3670_CLK_GATE_VENCFREQ 1 -#define HI3670_CLK_GATE_ICSFREQ 2 - -#endif /* __DT_BINDINGS_CLOCK_HI3670_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/hi6220-clock.h b/sys/gnu/dts/include/dt-bindings/clock/hi6220-clock.h deleted file mode 100644 index 9e40605e614..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/hi6220-clock.h +++ /dev/null @@ -1,178 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2015 Hisilicon Limited. - * - * Author: Bintian Wang - */ - -#ifndef __DT_BINDINGS_CLOCK_HI6220_H -#define __DT_BINDINGS_CLOCK_HI6220_H - -/* clk in Hi6220 AO (always on) controller */ -#define HI6220_NONE_CLOCK 0 - -/* fixed rate clocks */ -#define HI6220_REF32K 1 -#define HI6220_CLK_TCXO 2 -#define HI6220_MMC1_PAD 3 -#define HI6220_MMC2_PAD 4 -#define HI6220_MMC0_PAD 5 -#define HI6220_PLL_BBP 6 -#define HI6220_PLL_GPU 7 -#define HI6220_PLL1_DDR 8 -#define HI6220_PLL_SYS 9 -#define HI6220_PLL_SYS_MEDIA 10 -#define HI6220_DDR_SRC 11 -#define HI6220_PLL_MEDIA 12 -#define HI6220_PLL_DDR 13 - -/* fixed factor clocks */ -#define HI6220_300M 14 -#define HI6220_150M 15 -#define HI6220_PICOPHY_SRC 16 -#define HI6220_MMC0_SRC_SEL 17 -#define HI6220_MMC1_SRC_SEL 18 -#define HI6220_MMC2_SRC_SEL 19 -#define HI6220_VPU_CODEC 20 -#define HI6220_MMC0_SMP 21 -#define HI6220_MMC1_SMP 22 -#define HI6220_MMC2_SMP 23 - -/* gate clocks */ -#define HI6220_WDT0_PCLK 24 -#define HI6220_WDT1_PCLK 25 -#define HI6220_WDT2_PCLK 26 -#define HI6220_TIMER0_PCLK 27 -#define HI6220_TIMER1_PCLK 28 -#define HI6220_TIMER2_PCLK 29 -#define HI6220_TIMER3_PCLK 30 -#define HI6220_TIMER4_PCLK 31 -#define HI6220_TIMER5_PCLK 32 -#define HI6220_TIMER6_PCLK 33 -#define HI6220_TIMER7_PCLK 34 -#define HI6220_TIMER8_PCLK 35 -#define HI6220_UART0_PCLK 36 -#define HI6220_RTC0_PCLK 37 -#define HI6220_RTC1_PCLK 38 -#define HI6220_AO_NR_CLKS 39 - -/* clk in Hi6220 systrl */ -/* gate clock */ -#define HI6220_MMC0_CLK 1 -#define HI6220_MMC0_CIUCLK 2 -#define HI6220_MMC1_CLK 3 -#define HI6220_MMC1_CIUCLK 4 -#define HI6220_MMC2_CLK 5 -#define HI6220_MMC2_CIUCLK 6 -#define HI6220_USBOTG_HCLK 7 -#define HI6220_CLK_PICOPHY 8 -#define HI6220_HIFI 9 -#define HI6220_DACODEC_PCLK 10 -#define HI6220_EDMAC_ACLK 11 -#define HI6220_CS_ATB 12 -#define HI6220_I2C0_CLK 13 -#define HI6220_I2C1_CLK 14 -#define HI6220_I2C2_CLK 15 -#define HI6220_I2C3_CLK 16 -#define HI6220_UART1_PCLK 17 -#define HI6220_UART2_PCLK 18 -#define HI6220_UART3_PCLK 19 -#define HI6220_UART4_PCLK 20 -#define HI6220_SPI_CLK 21 -#define HI6220_TSENSOR_CLK 22 -#define HI6220_MMU_CLK 23 -#define HI6220_HIFI_SEL 24 -#define HI6220_MMC0_SYSPLL 25 -#define HI6220_MMC1_SYSPLL 26 -#define HI6220_MMC2_SYSPLL 27 -#define HI6220_MMC0_SEL 28 -#define HI6220_MMC1_SEL 29 -#define HI6220_BBPPLL_SEL 30 -#define HI6220_MEDIA_PLL_SRC 31 -#define HI6220_MMC2_SEL 32 -#define HI6220_CS_ATB_SYSPLL 33 - -/* mux clocks */ -#define HI6220_MMC0_SRC 34 -#define HI6220_MMC0_SMP_IN 35 -#define HI6220_MMC1_SRC 36 -#define HI6220_MMC1_SMP_IN 37 -#define HI6220_MMC2_SRC 38 -#define HI6220_MMC2_SMP_IN 39 -#define HI6220_HIFI_SRC 40 -#define HI6220_UART1_SRC 41 -#define HI6220_UART2_SRC 42 -#define HI6220_UART3_SRC 43 -#define HI6220_UART4_SRC 44 -#define HI6220_MMC0_MUX0 45 -#define HI6220_MMC1_MUX0 46 -#define HI6220_MMC2_MUX0 47 -#define HI6220_MMC0_MUX1 48 -#define HI6220_MMC1_MUX1 49 -#define HI6220_MMC2_MUX1 50 - -/* divider clocks */ -#define HI6220_CLK_BUS 51 -#define HI6220_MMC0_DIV 52 -#define HI6220_MMC1_DIV 53 -#define HI6220_MMC2_DIV 54 -#define HI6220_HIFI_DIV 55 -#define HI6220_BBPPLL0_DIV 56 -#define HI6220_CS_DAPB 57 -#define HI6220_CS_ATB_DIV 58 - -/* gate clock */ -#define HI6220_DAPB_CLK 59 - -#define HI6220_SYS_NR_CLKS 60 - -/* clk in Hi6220 media controller */ -/* gate clocks */ -#define HI6220_DSI_PCLK 1 -#define HI6220_G3D_PCLK 2 -#define HI6220_ACLK_CODEC_VPU 3 -#define HI6220_ISP_SCLK 4 -#define HI6220_ADE_CORE 5 -#define HI6220_MED_MMU 6 -#define HI6220_CFG_CSI4PHY 7 -#define HI6220_CFG_CSI2PHY 8 -#define HI6220_ISP_SCLK_GATE 9 -#define HI6220_ISP_SCLK_GATE1 10 -#define HI6220_ADE_CORE_GATE 11 -#define HI6220_CODEC_VPU_GATE 12 -#define HI6220_MED_SYSPLL 13 - -/* mux clocks */ -#define HI6220_1440_1200 14 -#define HI6220_1000_1200 15 -#define HI6220_1000_1440 16 - -/* divider clocks */ -#define HI6220_CODEC_JPEG 17 -#define HI6220_ISP_SCLK_SRC 18 -#define HI6220_ISP_SCLK1 19 -#define HI6220_ADE_CORE_SRC 20 -#define HI6220_ADE_PIX_SRC 21 -#define HI6220_G3D_CLK 22 -#define HI6220_CODEC_VPU_SRC 23 - -#define HI6220_MEDIA_NR_CLKS 24 - -/* clk in Hi6220 power controller */ -/* gate clocks */ -#define HI6220_PLL_GPU_GATE 1 -#define HI6220_PLL1_DDR_GATE 2 -#define HI6220_PLL_DDR_GATE 3 -#define HI6220_PLL_MEDIA_GATE 4 -#define HI6220_PLL0_BBP_GATE 5 - -/* divider clocks */ -#define HI6220_DDRC_SRC 6 -#define HI6220_DDRC_AXI1 7 - -#define HI6220_POWER_NR_CLKS 8 - -/* clk in Hi6220 acpu sctrl */ -#define HI6220_ACPU_SFT_AT_S 0 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/hip04-clock.h b/sys/gnu/dts/include/dt-bindings/clock/hip04-clock.h deleted file mode 100644 index 088d70cd794..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/hip04-clock.h +++ /dev/null @@ -1,21 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright (c) 2013-2014 Hisilicon Limited. - * Copyright (c) 2013-2014 Linaro Limited. - * - * Author: Haojian Zhuang - */ - -#ifndef __DTS_HIP04_CLOCK_H -#define __DTS_HIP04_CLOCK_H - -#define HIP04_NONE_CLOCK 0 - -/* fixed rate & fixed factor clocks */ -#define HIP04_OSC50M 1 -#define HIP04_CLK_50M 2 -#define HIP04_CLK_168M 3 - -#define HIP04_NR_CLKS 64 - -#endif /* __DTS_HIP04_CLOCK_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/histb-clock.h b/sys/gnu/dts/include/dt-bindings/clock/histb-clock.h deleted file mode 100644 index e64e5770ada..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/histb-clock.h +++ /dev/null @@ -1,70 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright (c) 2016 HiSilicon Technologies Co., Ltd. - */ - -#ifndef __DTS_HISTB_CLOCK_H -#define __DTS_HISTB_CLOCK_H - -/* clocks provided by core CRG */ -#define HISTB_OSC_CLK 0 -#define HISTB_APB_CLK 1 -#define HISTB_AHB_CLK 2 -#define HISTB_UART1_CLK 3 -#define HISTB_UART2_CLK 4 -#define HISTB_UART3_CLK 5 -#define HISTB_I2C0_CLK 6 -#define HISTB_I2C1_CLK 7 -#define HISTB_I2C2_CLK 8 -#define HISTB_I2C3_CLK 9 -#define HISTB_I2C4_CLK 10 -#define HISTB_I2C5_CLK 11 -#define HISTB_SPI0_CLK 12 -#define HISTB_SPI1_CLK 13 -#define HISTB_SPI2_CLK 14 -#define HISTB_SCI_CLK 15 -#define HISTB_FMC_CLK 16 -#define HISTB_MMC_BIU_CLK 17 -#define HISTB_MMC_CIU_CLK 18 -#define HISTB_MMC_DRV_CLK 19 -#define HISTB_MMC_SAMPLE_CLK 20 -#define HISTB_SDIO0_BIU_CLK 21 -#define HISTB_SDIO0_CIU_CLK 22 -#define HISTB_SDIO0_DRV_CLK 23 -#define HISTB_SDIO0_SAMPLE_CLK 24 -#define HISTB_PCIE_AUX_CLK 25 -#define HISTB_PCIE_PIPE_CLK 26 -#define HISTB_PCIE_SYS_CLK 27 -#define HISTB_PCIE_BUS_CLK 28 -#define HISTB_ETH0_MAC_CLK 29 -#define HISTB_ETH0_MACIF_CLK 30 -#define HISTB_ETH1_MAC_CLK 31 -#define HISTB_ETH1_MACIF_CLK 32 -#define HISTB_COMBPHY1_CLK 33 -#define HISTB_USB2_BUS_CLK 34 -#define HISTB_USB2_PHY_CLK 35 -#define HISTB_USB2_UTMI_CLK 36 -#define HISTB_USB2_12M_CLK 37 -#define HISTB_USB2_48M_CLK 38 -#define HISTB_USB2_OTG_UTMI_CLK 39 -#define HISTB_USB2_PHY1_REF_CLK 40 -#define HISTB_USB2_PHY2_REF_CLK 41 -#define HISTB_COMBPHY0_CLK 42 -#define HISTB_USB3_BUS_CLK 43 -#define HISTB_USB3_UTMI_CLK 44 -#define HISTB_USB3_PIPE_CLK 45 -#define HISTB_USB3_SUSPEND_CLK 46 -#define HISTB_USB3_BUS_CLK1 47 -#define HISTB_USB3_UTMI_CLK1 48 -#define HISTB_USB3_PIPE_CLK1 49 -#define HISTB_USB3_SUSPEND_CLK1 50 - -/* clocks provided by mcu CRG */ -#define HISTB_MCE_CLK 1 -#define HISTB_IR_CLK 2 -#define HISTB_TIMER01_CLK 3 -#define HISTB_LEDC_CLK 4 -#define HISTB_UART0_CLK 5 -#define HISTB_LSADC_CLK 6 - -#endif /* __DTS_HISTB_CLOCK_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/hix5hd2-clock.h b/sys/gnu/dts/include/dt-bindings/clock/hix5hd2-clock.h deleted file mode 100644 index 2b8779f1ac9..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/hix5hd2-clock.h +++ /dev/null @@ -1,82 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2014 Linaro Ltd. - * Copyright (c) 2014 Hisilicon Limited. - */ - -#ifndef __DTS_HIX5HD2_CLOCK_H -#define __DTS_HIX5HD2_CLOCK_H - -/* fixed rate */ -#define HIX5HD2_FIXED_1200M 1 -#define HIX5HD2_FIXED_400M 2 -#define HIX5HD2_FIXED_48M 3 -#define HIX5HD2_FIXED_24M 4 -#define HIX5HD2_FIXED_600M 5 -#define HIX5HD2_FIXED_300M 6 -#define HIX5HD2_FIXED_75M 7 -#define HIX5HD2_FIXED_200M 8 -#define HIX5HD2_FIXED_100M 9 -#define HIX5HD2_FIXED_40M 10 -#define HIX5HD2_FIXED_150M 11 -#define HIX5HD2_FIXED_1728M 12 -#define HIX5HD2_FIXED_28P8M 13 -#define HIX5HD2_FIXED_432M 14 -#define HIX5HD2_FIXED_345P6M 15 -#define HIX5HD2_FIXED_288M 16 -#define HIX5HD2_FIXED_60M 17 -#define HIX5HD2_FIXED_750M 18 -#define HIX5HD2_FIXED_500M 19 -#define HIX5HD2_FIXED_54M 20 -#define HIX5HD2_FIXED_27M 21 -#define HIX5HD2_FIXED_1500M 22 -#define HIX5HD2_FIXED_375M 23 -#define HIX5HD2_FIXED_187M 24 -#define HIX5HD2_FIXED_250M 25 -#define HIX5HD2_FIXED_125M 26 -#define HIX5HD2_FIXED_2P02M 27 -#define HIX5HD2_FIXED_50M 28 -#define HIX5HD2_FIXED_25M 29 -#define HIX5HD2_FIXED_83M 30 - -/* mux clocks */ -#define HIX5HD2_SFC_MUX 64 -#define HIX5HD2_MMC_MUX 65 -#define HIX5HD2_FEPHY_MUX 66 -#define HIX5HD2_SD_MUX 67 - -/* gate clocks */ -#define HIX5HD2_SFC_RST 128 -#define HIX5HD2_SFC_CLK 129 -#define HIX5HD2_MMC_CIU_CLK 130 -#define HIX5HD2_MMC_BIU_CLK 131 -#define HIX5HD2_MMC_CIU_RST 132 -#define HIX5HD2_FWD_BUS_CLK 133 -#define HIX5HD2_FWD_SYS_CLK 134 -#define HIX5HD2_MAC0_PHY_CLK 135 -#define HIX5HD2_SD_CIU_CLK 136 -#define HIX5HD2_SD_BIU_CLK 137 -#define HIX5HD2_SD_CIU_RST 138 -#define HIX5HD2_WDG0_CLK 139 -#define HIX5HD2_WDG0_RST 140 -#define HIX5HD2_I2C0_CLK 141 -#define HIX5HD2_I2C0_RST 142 -#define HIX5HD2_I2C1_CLK 143 -#define HIX5HD2_I2C1_RST 144 -#define HIX5HD2_I2C2_CLK 145 -#define HIX5HD2_I2C2_RST 146 -#define HIX5HD2_I2C3_CLK 147 -#define HIX5HD2_I2C3_RST 148 -#define HIX5HD2_I2C4_CLK 149 -#define HIX5HD2_I2C4_RST 150 -#define HIX5HD2_I2C5_CLK 151 -#define HIX5HD2_I2C5_RST 152 - -/* complex */ -#define HIX5HD2_MAC0_CLK 192 -#define HIX5HD2_MAC1_CLK 193 -#define HIX5HD2_SATA_CLK 194 -#define HIX5HD2_USB_CLK 195 - -#define HIX5HD2_NR_CLKS 256 -#endif /* __DTS_HIX5HD2_CLOCK_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/imx1-clock.h b/sys/gnu/dts/include/dt-bindings/clock/imx1-clock.h deleted file mode 100644 index 3730a46e7c8..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/imx1-clock.h +++ /dev/null @@ -1,36 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) 2014 Alexander Shiyan - */ - -#ifndef __DT_BINDINGS_CLOCK_IMX1_H -#define __DT_BINDINGS_CLOCK_IMX1_H - -#define IMX1_CLK_DUMMY 0 -#define IMX1_CLK_CLK32 1 -#define IMX1_CLK_CLK16M_EXT 2 -#define IMX1_CLK_CLK16M 3 -#define IMX1_CLK_CLK32_PREMULT 4 -#define IMX1_CLK_PREM 5 -#define IMX1_CLK_MPLL 6 -#define IMX1_CLK_MPLL_GATE 7 -#define IMX1_CLK_SPLL 8 -#define IMX1_CLK_SPLL_GATE 9 -#define IMX1_CLK_MCU 10 -#define IMX1_CLK_FCLK 11 -#define IMX1_CLK_HCLK 12 -#define IMX1_CLK_CLK48M 13 -#define IMX1_CLK_PER1 14 -#define IMX1_CLK_PER2 15 -#define IMX1_CLK_PER3 16 -#define IMX1_CLK_CLKO 17 -#define IMX1_CLK_UART3_GATE 18 -#define IMX1_CLK_SSI2_GATE 19 -#define IMX1_CLK_BROM_GATE 20 -#define IMX1_CLK_DMA_GATE 21 -#define IMX1_CLK_CSI_GATE 22 -#define IMX1_CLK_MMA_GATE 23 -#define IMX1_CLK_USBD_GATE 24 -#define IMX1_CLK_MAX 25 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/imx21-clock.h b/sys/gnu/dts/include/dt-bindings/clock/imx21-clock.h deleted file mode 100644 index 66d0ec5e4c9..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/imx21-clock.h +++ /dev/null @@ -1,76 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) 2014 Alexander Shiyan - */ - -#ifndef __DT_BINDINGS_CLOCK_IMX21_H -#define __DT_BINDINGS_CLOCK_IMX21_H - -#define IMX21_CLK_DUMMY 0 -#define IMX21_CLK_CKIL 1 -#define IMX21_CLK_CKIH 2 -#define IMX21_CLK_FPM 3 -#define IMX21_CLK_CKIH_DIV1P5 4 -#define IMX21_CLK_MPLL_GATE 5 -#define IMX21_CLK_SPLL_GATE 6 -#define IMX21_CLK_FPM_GATE 7 -#define IMX21_CLK_CKIH_GATE 8 -#define IMX21_CLK_MPLL_OSC_SEL 9 -#define IMX21_CLK_IPG 10 -#define IMX21_CLK_HCLK 11 -#define IMX21_CLK_MPLL_SEL 12 -#define IMX21_CLK_SPLL_SEL 13 -#define IMX21_CLK_SSI1_SEL 14 -#define IMX21_CLK_SSI2_SEL 15 -#define IMX21_CLK_USB_DIV 16 -#define IMX21_CLK_FCLK 17 -#define IMX21_CLK_MPLL 18 -#define IMX21_CLK_SPLL 19 -#define IMX21_CLK_NFC_DIV 20 -#define IMX21_CLK_SSI1_DIV 21 -#define IMX21_CLK_SSI2_DIV 22 -#define IMX21_CLK_PER1 23 -#define IMX21_CLK_PER2 24 -#define IMX21_CLK_PER3 25 -#define IMX21_CLK_PER4 26 -#define IMX21_CLK_UART1_IPG_GATE 27 -#define IMX21_CLK_UART2_IPG_GATE 28 -#define IMX21_CLK_UART3_IPG_GATE 29 -#define IMX21_CLK_UART4_IPG_GATE 30 -#define IMX21_CLK_CSPI1_IPG_GATE 31 -#define IMX21_CLK_CSPI2_IPG_GATE 32 -#define IMX21_CLK_SSI1_GATE 33 -#define IMX21_CLK_SSI2_GATE 34 -#define IMX21_CLK_SDHC1_IPG_GATE 35 -#define IMX21_CLK_SDHC2_IPG_GATE 36 -#define IMX21_CLK_GPIO_GATE 37 -#define IMX21_CLK_I2C_GATE 38 -#define IMX21_CLK_DMA_GATE 39 -#define IMX21_CLK_USB_GATE 40 -#define IMX21_CLK_EMMA_GATE 41 -#define IMX21_CLK_SSI2_BAUD_GATE 42 -#define IMX21_CLK_SSI1_BAUD_GATE 43 -#define IMX21_CLK_LCDC_IPG_GATE 44 -#define IMX21_CLK_NFC_GATE 45 -#define IMX21_CLK_LCDC_HCLK_GATE 46 -#define IMX21_CLK_PER4_GATE 47 -#define IMX21_CLK_BMI_GATE 48 -#define IMX21_CLK_USB_HCLK_GATE 49 -#define IMX21_CLK_SLCDC_GATE 50 -#define IMX21_CLK_SLCDC_HCLK_GATE 51 -#define IMX21_CLK_EMMA_HCLK_GATE 52 -#define IMX21_CLK_BROM_GATE 53 -#define IMX21_CLK_DMA_HCLK_GATE 54 -#define IMX21_CLK_CSI_HCLK_GATE 55 -#define IMX21_CLK_CSPI3_IPG_GATE 56 -#define IMX21_CLK_WDOG_GATE 57 -#define IMX21_CLK_GPT1_IPG_GATE 58 -#define IMX21_CLK_GPT2_IPG_GATE 59 -#define IMX21_CLK_GPT3_IPG_GATE 60 -#define IMX21_CLK_PWM_IPG_GATE 61 -#define IMX21_CLK_RTC_GATE 62 -#define IMX21_CLK_KPP_GATE 63 -#define IMX21_CLK_OWIRE_GATE 64 -#define IMX21_CLK_MAX 65 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/imx27-clock.h b/sys/gnu/dts/include/dt-bindings/clock/imx27-clock.h deleted file mode 100644 index 1ff448b8036..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/imx27-clock.h +++ /dev/null @@ -1,104 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) 2014 Alexander Shiyan - */ - -#ifndef __DT_BINDINGS_CLOCK_IMX27_H -#define __DT_BINDINGS_CLOCK_IMX27_H - -#define IMX27_CLK_DUMMY 0 -#define IMX27_CLK_CKIH 1 -#define IMX27_CLK_CKIL 2 -#define IMX27_CLK_MPLL 3 -#define IMX27_CLK_SPLL 4 -#define IMX27_CLK_MPLL_MAIN2 5 -#define IMX27_CLK_AHB 6 -#define IMX27_CLK_IPG 7 -#define IMX27_CLK_NFC_DIV 8 -#define IMX27_CLK_PER1_DIV 9 -#define IMX27_CLK_PER2_DIV 10 -#define IMX27_CLK_PER3_DIV 11 -#define IMX27_CLK_PER4_DIV 12 -#define IMX27_CLK_VPU_SEL 13 -#define IMX27_CLK_VPU_DIV 14 -#define IMX27_CLK_USB_DIV 15 -#define IMX27_CLK_CPU_SEL 16 -#define IMX27_CLK_CLKO_SEL 17 -#define IMX27_CLK_CPU_DIV 18 -#define IMX27_CLK_CLKO_DIV 19 -#define IMX27_CLK_SSI1_SEL 20 -#define IMX27_CLK_SSI2_SEL 21 -#define IMX27_CLK_SSI1_DIV 22 -#define IMX27_CLK_SSI2_DIV 23 -#define IMX27_CLK_CLKO_EN 24 -#define IMX27_CLK_SSI2_IPG_GATE 25 -#define IMX27_CLK_SSI1_IPG_GATE 26 -#define IMX27_CLK_SLCDC_IPG_GATE 27 -#define IMX27_CLK_SDHC3_IPG_GATE 28 -#define IMX27_CLK_SDHC2_IPG_GATE 29 -#define IMX27_CLK_SDHC1_IPG_GATE 30 -#define IMX27_CLK_SCC_IPG_GATE 31 -#define IMX27_CLK_SAHARA_IPG_GATE 32 -#define IMX27_CLK_RTC_IPG_GATE 33 -#define IMX27_CLK_PWM_IPG_GATE 34 -#define IMX27_CLK_OWIRE_IPG_GATE 35 -#define IMX27_CLK_LCDC_IPG_GATE 36 -#define IMX27_CLK_KPP_IPG_GATE 37 -#define IMX27_CLK_IIM_IPG_GATE 38 -#define IMX27_CLK_I2C2_IPG_GATE 39 -#define IMX27_CLK_I2C1_IPG_GATE 40 -#define IMX27_CLK_GPT6_IPG_GATE 41 -#define IMX27_CLK_GPT5_IPG_GATE 42 -#define IMX27_CLK_GPT4_IPG_GATE 43 -#define IMX27_CLK_GPT3_IPG_GATE 44 -#define IMX27_CLK_GPT2_IPG_GATE 45 -#define IMX27_CLK_GPT1_IPG_GATE 46 -#define IMX27_CLK_GPIO_IPG_GATE 47 -#define IMX27_CLK_FEC_IPG_GATE 48 -#define IMX27_CLK_EMMA_IPG_GATE 49 -#define IMX27_CLK_DMA_IPG_GATE 50 -#define IMX27_CLK_CSPI3_IPG_GATE 51 -#define IMX27_CLK_CSPI2_IPG_GATE 52 -#define IMX27_CLK_CSPI1_IPG_GATE 53 -#define IMX27_CLK_NFC_BAUD_GATE 54 -#define IMX27_CLK_SSI2_BAUD_GATE 55 -#define IMX27_CLK_SSI1_BAUD_GATE 56 -#define IMX27_CLK_VPU_BAUD_GATE 57 -#define IMX27_CLK_PER4_GATE 58 -#define IMX27_CLK_PER3_GATE 59 -#define IMX27_CLK_PER2_GATE 60 -#define IMX27_CLK_PER1_GATE 61 -#define IMX27_CLK_USB_AHB_GATE 62 -#define IMX27_CLK_SLCDC_AHB_GATE 63 -#define IMX27_CLK_SAHARA_AHB_GATE 64 -#define IMX27_CLK_LCDC_AHB_GATE 65 -#define IMX27_CLK_VPU_AHB_GATE 66 -#define IMX27_CLK_FEC_AHB_GATE 67 -#define IMX27_CLK_EMMA_AHB_GATE 68 -#define IMX27_CLK_EMI_AHB_GATE 69 -#define IMX27_CLK_DMA_AHB_GATE 70 -#define IMX27_CLK_CSI_AHB_GATE 71 -#define IMX27_CLK_BROM_AHB_GATE 72 -#define IMX27_CLK_ATA_AHB_GATE 73 -#define IMX27_CLK_WDOG_IPG_GATE 74 -#define IMX27_CLK_USB_IPG_GATE 75 -#define IMX27_CLK_UART6_IPG_GATE 76 -#define IMX27_CLK_UART5_IPG_GATE 77 -#define IMX27_CLK_UART4_IPG_GATE 78 -#define IMX27_CLK_UART3_IPG_GATE 79 -#define IMX27_CLK_UART2_IPG_GATE 80 -#define IMX27_CLK_UART1_IPG_GATE 81 -#define IMX27_CLK_CKIH_DIV1P5 82 -#define IMX27_CLK_FPM 83 -#define IMX27_CLK_MPLL_OSC_SEL 84 -#define IMX27_CLK_MPLL_SEL 85 -#define IMX27_CLK_SPLL_GATE 86 -#define IMX27_CLK_MSHC_DIV 87 -#define IMX27_CLK_RTIC_IPG_GATE 88 -#define IMX27_CLK_MSHC_IPG_GATE 89 -#define IMX27_CLK_RTIC_AHB_GATE 90 -#define IMX27_CLK_MSHC_BAUD_GATE 91 -#define IMX27_CLK_CKIH_GATE 92 -#define IMX27_CLK_MAX 93 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/imx5-clock.h b/sys/gnu/dts/include/dt-bindings/clock/imx5-clock.h deleted file mode 100644 index bc65e30695b..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/imx5-clock.h +++ /dev/null @@ -1,216 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2013 Lucas Stach, Pengutronix - */ - -#ifndef __DT_BINDINGS_CLOCK_IMX5_H -#define __DT_BINDINGS_CLOCK_IMX5_H - -#define IMX5_CLK_DUMMY 0 -#define IMX5_CLK_CKIL 1 -#define IMX5_CLK_OSC 2 -#define IMX5_CLK_CKIH1 3 -#define IMX5_CLK_CKIH2 4 -#define IMX5_CLK_AHB 5 -#define IMX5_CLK_IPG 6 -#define IMX5_CLK_AXI_A 7 -#define IMX5_CLK_AXI_B 8 -#define IMX5_CLK_UART_PRED 9 -#define IMX5_CLK_UART_ROOT 10 -#define IMX5_CLK_ESDHC_A_PRED 11 -#define IMX5_CLK_ESDHC_B_PRED 12 -#define IMX5_CLK_ESDHC_C_SEL 13 -#define IMX5_CLK_ESDHC_D_SEL 14 -#define IMX5_CLK_EMI_SEL 15 -#define IMX5_CLK_EMI_SLOW_PODF 16 -#define IMX5_CLK_NFC_PODF 17 -#define IMX5_CLK_ECSPI_PRED 18 -#define IMX5_CLK_ECSPI_PODF 19 -#define IMX5_CLK_USBOH3_PRED 20 -#define IMX5_CLK_USBOH3_PODF 21 -#define IMX5_CLK_USB_PHY_PRED 22 -#define IMX5_CLK_USB_PHY_PODF 23 -#define IMX5_CLK_CPU_PODF 24 -#define IMX5_CLK_DI_PRED 25 -#define IMX5_CLK_TVE_SEL 27 -#define IMX5_CLK_UART1_IPG_GATE 28 -#define IMX5_CLK_UART1_PER_GATE 29 -#define IMX5_CLK_UART2_IPG_GATE 30 -#define IMX5_CLK_UART2_PER_GATE 31 -#define IMX5_CLK_UART3_IPG_GATE 32 -#define IMX5_CLK_UART3_PER_GATE 33 -#define IMX5_CLK_I2C1_GATE 34 -#define IMX5_CLK_I2C2_GATE 35 -#define IMX5_CLK_GPT_IPG_GATE 36 -#define IMX5_CLK_PWM1_IPG_GATE 37 -#define IMX5_CLK_PWM1_HF_GATE 38 -#define IMX5_CLK_PWM2_IPG_GATE 39 -#define IMX5_CLK_PWM2_HF_GATE 40 -#define IMX5_CLK_GPT_HF_GATE 41 -#define IMX5_CLK_FEC_GATE 42 -#define IMX5_CLK_USBOH3_PER_GATE 43 -#define IMX5_CLK_ESDHC1_IPG_GATE 44 -#define IMX5_CLK_ESDHC2_IPG_GATE 45 -#define IMX5_CLK_ESDHC3_IPG_GATE 46 -#define IMX5_CLK_ESDHC4_IPG_GATE 47 -#define IMX5_CLK_SSI1_IPG_GATE 48 -#define IMX5_CLK_SSI2_IPG_GATE 49 -#define IMX5_CLK_SSI3_IPG_GATE 50 -#define IMX5_CLK_ECSPI1_IPG_GATE 51 -#define IMX5_CLK_ECSPI1_PER_GATE 52 -#define IMX5_CLK_ECSPI2_IPG_GATE 53 -#define IMX5_CLK_ECSPI2_PER_GATE 54 -#define IMX5_CLK_CSPI_IPG_GATE 55 -#define IMX5_CLK_SDMA_GATE 56 -#define IMX5_CLK_EMI_SLOW_GATE 57 -#define IMX5_CLK_IPU_SEL 58 -#define IMX5_CLK_IPU_GATE 59 -#define IMX5_CLK_NFC_GATE 60 -#define IMX5_CLK_IPU_DI1_GATE 61 -#define IMX5_CLK_VPU_SEL 62 -#define IMX5_CLK_VPU_GATE 63 -#define IMX5_CLK_VPU_REFERENCE_GATE 64 -#define IMX5_CLK_UART4_IPG_GATE 65 -#define IMX5_CLK_UART4_PER_GATE 66 -#define IMX5_CLK_UART5_IPG_GATE 67 -#define IMX5_CLK_UART5_PER_GATE 68 -#define IMX5_CLK_TVE_GATE 69 -#define IMX5_CLK_TVE_PRED 70 -#define IMX5_CLK_ESDHC1_PER_GATE 71 -#define IMX5_CLK_ESDHC2_PER_GATE 72 -#define IMX5_CLK_ESDHC3_PER_GATE 73 -#define IMX5_CLK_ESDHC4_PER_GATE 74 -#define IMX5_CLK_USB_PHY_GATE 75 -#define IMX5_CLK_HSI2C_GATE 76 -#define IMX5_CLK_MIPI_HSC1_GATE 77 -#define IMX5_CLK_MIPI_HSC2_GATE 78 -#define IMX5_CLK_MIPI_ESC_GATE 79 -#define IMX5_CLK_MIPI_HSP_GATE 80 -#define IMX5_CLK_LDB_DI1_DIV_3_5 81 -#define IMX5_CLK_LDB_DI1_DIV 82 -#define IMX5_CLK_LDB_DI0_DIV_3_5 83 -#define IMX5_CLK_LDB_DI0_DIV 84 -#define IMX5_CLK_LDB_DI1_GATE 85 -#define IMX5_CLK_CAN2_SERIAL_GATE 86 -#define IMX5_CLK_CAN2_IPG_GATE 87 -#define IMX5_CLK_I2C3_GATE 88 -#define IMX5_CLK_LP_APM 89 -#define IMX5_CLK_PERIPH_APM 90 -#define IMX5_CLK_MAIN_BUS 91 -#define IMX5_CLK_AHB_MAX 92 -#define IMX5_CLK_AIPS_TZ1 93 -#define IMX5_CLK_AIPS_TZ2 94 -#define IMX5_CLK_TMAX1 95 -#define IMX5_CLK_TMAX2 96 -#define IMX5_CLK_TMAX3 97 -#define IMX5_CLK_SPBA 98 -#define IMX5_CLK_UART_SEL 99 -#define IMX5_CLK_ESDHC_A_SEL 100 -#define IMX5_CLK_ESDHC_B_SEL 101 -#define IMX5_CLK_ESDHC_A_PODF 102 -#define IMX5_CLK_ESDHC_B_PODF 103 -#define IMX5_CLK_ECSPI_SEL 104 -#define IMX5_CLK_USBOH3_SEL 105 -#define IMX5_CLK_USB_PHY_SEL 106 -#define IMX5_CLK_IIM_GATE 107 -#define IMX5_CLK_USBOH3_GATE 108 -#define IMX5_CLK_EMI_FAST_GATE 109 -#define IMX5_CLK_IPU_DI0_GATE 110 -#define IMX5_CLK_GPC_DVFS 111 -#define IMX5_CLK_PLL1_SW 112 -#define IMX5_CLK_PLL2_SW 113 -#define IMX5_CLK_PLL3_SW 114 -#define IMX5_CLK_IPU_DI0_SEL 115 -#define IMX5_CLK_IPU_DI1_SEL 116 -#define IMX5_CLK_TVE_EXT_SEL 117 -#define IMX5_CLK_MX51_MIPI 118 -#define IMX5_CLK_PLL4_SW 119 -#define IMX5_CLK_LDB_DI1_SEL 120 -#define IMX5_CLK_DI_PLL4_PODF 121 -#define IMX5_CLK_LDB_DI0_SEL 122 -#define IMX5_CLK_LDB_DI0_GATE 123 -#define IMX5_CLK_USB_PHY1_GATE 124 -#define IMX5_CLK_USB_PHY2_GATE 125 -#define IMX5_CLK_PER_LP_APM 126 -#define IMX5_CLK_PER_PRED1 127 -#define IMX5_CLK_PER_PRED2 128 -#define IMX5_CLK_PER_PODF 129 -#define IMX5_CLK_PER_ROOT 130 -#define IMX5_CLK_SSI_APM 131 -#define IMX5_CLK_SSI1_ROOT_SEL 132 -#define IMX5_CLK_SSI2_ROOT_SEL 133 -#define IMX5_CLK_SSI3_ROOT_SEL 134 -#define IMX5_CLK_SSI_EXT1_SEL 135 -#define IMX5_CLK_SSI_EXT2_SEL 136 -#define IMX5_CLK_SSI_EXT1_COM_SEL 137 -#define IMX5_CLK_SSI_EXT2_COM_SEL 138 -#define IMX5_CLK_SSI1_ROOT_PRED 139 -#define IMX5_CLK_SSI1_ROOT_PODF 140 -#define IMX5_CLK_SSI2_ROOT_PRED 141 -#define IMX5_CLK_SSI2_ROOT_PODF 142 -#define IMX5_CLK_SSI_EXT1_PRED 143 -#define IMX5_CLK_SSI_EXT1_PODF 144 -#define IMX5_CLK_SSI_EXT2_PRED 145 -#define IMX5_CLK_SSI_EXT2_PODF 146 -#define IMX5_CLK_SSI1_ROOT_GATE 147 -#define IMX5_CLK_SSI2_ROOT_GATE 148 -#define IMX5_CLK_SSI3_ROOT_GATE 149 -#define IMX5_CLK_SSI_EXT1_GATE 150 -#define IMX5_CLK_SSI_EXT2_GATE 151 -#define IMX5_CLK_EPIT1_IPG_GATE 152 -#define IMX5_CLK_EPIT1_HF_GATE 153 -#define IMX5_CLK_EPIT2_IPG_GATE 154 -#define IMX5_CLK_EPIT2_HF_GATE 155 -#define IMX5_CLK_CAN_SEL 156 -#define IMX5_CLK_CAN1_SERIAL_GATE 157 -#define IMX5_CLK_CAN1_IPG_GATE 158 -#define IMX5_CLK_OWIRE_GATE 159 -#define IMX5_CLK_GPU3D_SEL 160 -#define IMX5_CLK_GPU2D_SEL 161 -#define IMX5_CLK_GPU3D_GATE 162 -#define IMX5_CLK_GPU2D_GATE 163 -#define IMX5_CLK_GARB_GATE 164 -#define IMX5_CLK_CKO1_SEL 165 -#define IMX5_CLK_CKO1_PODF 166 -#define IMX5_CLK_CKO1 167 -#define IMX5_CLK_CKO2_SEL 168 -#define IMX5_CLK_CKO2_PODF 169 -#define IMX5_CLK_CKO2 170 -#define IMX5_CLK_SRTC_GATE 171 -#define IMX5_CLK_PATA_GATE 172 -#define IMX5_CLK_SATA_GATE 173 -#define IMX5_CLK_SPDIF_XTAL_SEL 174 -#define IMX5_CLK_SPDIF0_SEL 175 -#define IMX5_CLK_SPDIF1_SEL 176 -#define IMX5_CLK_SPDIF0_PRED 177 -#define IMX5_CLK_SPDIF0_PODF 178 -#define IMX5_CLK_SPDIF1_PRED 179 -#define IMX5_CLK_SPDIF1_PODF 180 -#define IMX5_CLK_SPDIF0_COM_SEL 181 -#define IMX5_CLK_SPDIF1_COM_SEL 182 -#define IMX5_CLK_SPDIF0_GATE 183 -#define IMX5_CLK_SPDIF1_GATE 184 -#define IMX5_CLK_SPDIF_IPG_GATE 185 -#define IMX5_CLK_OCRAM 186 -#define IMX5_CLK_SAHARA_IPG_GATE 187 -#define IMX5_CLK_SATA_REF 188 -#define IMX5_CLK_STEP_SEL 189 -#define IMX5_CLK_CPU_PODF_SEL 190 -#define IMX5_CLK_ARM 191 -#define IMX5_CLK_FIRI_PRED 192 -#define IMX5_CLK_FIRI_SEL 193 -#define IMX5_CLK_FIRI_PODF 194 -#define IMX5_CLK_FIRI_SERIAL_GATE 195 -#define IMX5_CLK_FIRI_IPG_GATE 196 -#define IMX5_CLK_CSI0_MCLK1_PRED 197 -#define IMX5_CLK_CSI0_MCLK1_SEL 198 -#define IMX5_CLK_CSI0_MCLK1_PODF 199 -#define IMX5_CLK_CSI0_MCLK1_GATE 200 -#define IMX5_CLK_IEEE1588_PRED 201 -#define IMX5_CLK_IEEE1588_SEL 202 -#define IMX5_CLK_IEEE1588_PODF 203 -#define IMX5_CLK_IEEE1588_GATE 204 -#define IMX5_CLK_SCC2_IPG_GATE 205 -#define IMX5_CLK_END 206 - -#endif /* __DT_BINDINGS_CLOCK_IMX5_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/imx6qdl-clock.h b/sys/gnu/dts/include/dt-bindings/clock/imx6qdl-clock.h deleted file mode 100644 index e20c43cc36f..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/imx6qdl-clock.h +++ /dev/null @@ -1,278 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - */ - -#ifndef __DT_BINDINGS_CLOCK_IMX6QDL_H -#define __DT_BINDINGS_CLOCK_IMX6QDL_H - -#define IMX6QDL_CLK_DUMMY 0 -#define IMX6QDL_CLK_CKIL 1 -#define IMX6QDL_CLK_CKIH 2 -#define IMX6QDL_CLK_OSC 3 -#define IMX6QDL_CLK_PLL2_PFD0_352M 4 -#define IMX6QDL_CLK_PLL2_PFD1_594M 5 -#define IMX6QDL_CLK_PLL2_PFD2_396M 6 -#define IMX6QDL_CLK_PLL3_PFD0_720M 7 -#define IMX6QDL_CLK_PLL3_PFD1_540M 8 -#define IMX6QDL_CLK_PLL3_PFD2_508M 9 -#define IMX6QDL_CLK_PLL3_PFD3_454M 10 -#define IMX6QDL_CLK_PLL2_198M 11 -#define IMX6QDL_CLK_PLL3_120M 12 -#define IMX6QDL_CLK_PLL3_80M 13 -#define IMX6QDL_CLK_PLL3_60M 14 -#define IMX6QDL_CLK_TWD 15 -#define IMX6QDL_CLK_STEP 16 -#define IMX6QDL_CLK_PLL1_SW 17 -#define IMX6QDL_CLK_PERIPH_PRE 18 -#define IMX6QDL_CLK_PERIPH2_PRE 19 -#define IMX6QDL_CLK_PERIPH_CLK2_SEL 20 -#define IMX6QDL_CLK_PERIPH2_CLK2_SEL 21 -#define IMX6QDL_CLK_AXI_SEL 22 -#define IMX6QDL_CLK_ESAI_SEL 23 -#define IMX6QDL_CLK_ASRC_SEL 24 -#define IMX6QDL_CLK_SPDIF_SEL 25 -#define IMX6QDL_CLK_GPU2D_AXI 26 -#define IMX6QDL_CLK_GPU3D_AXI 27 -#define IMX6QDL_CLK_GPU2D_CORE_SEL 28 -#define IMX6QDL_CLK_GPU3D_CORE_SEL 29 -#define IMX6QDL_CLK_GPU3D_SHADER_SEL 30 -#define IMX6QDL_CLK_IPU1_SEL 31 -#define IMX6QDL_CLK_IPU2_SEL 32 -#define IMX6QDL_CLK_LDB_DI0_SEL 33 -#define IMX6QDL_CLK_LDB_DI1_SEL 34 -#define IMX6QDL_CLK_IPU1_DI0_PRE_SEL 35 -#define IMX6QDL_CLK_IPU1_DI1_PRE_SEL 36 -#define IMX6QDL_CLK_IPU2_DI0_PRE_SEL 37 -#define IMX6QDL_CLK_IPU2_DI1_PRE_SEL 38 -#define IMX6QDL_CLK_IPU1_DI0_SEL 39 -#define IMX6QDL_CLK_IPU1_DI1_SEL 40 -#define IMX6QDL_CLK_IPU2_DI0_SEL 41 -#define IMX6QDL_CLK_IPU2_DI1_SEL 42 -#define IMX6QDL_CLK_HSI_TX_SEL 43 -#define IMX6QDL_CLK_PCIE_AXI_SEL 44 -#define IMX6QDL_CLK_SSI1_SEL 45 -#define IMX6QDL_CLK_SSI2_SEL 46 -#define IMX6QDL_CLK_SSI3_SEL 47 -#define IMX6QDL_CLK_USDHC1_SEL 48 -#define IMX6QDL_CLK_USDHC2_SEL 49 -#define IMX6QDL_CLK_USDHC3_SEL 50 -#define IMX6QDL_CLK_USDHC4_SEL 51 -#define IMX6QDL_CLK_ENFC_SEL 52 -#define IMX6QDL_CLK_EIM_SEL 53 -#define IMX6QDL_CLK_EIM_SLOW_SEL 54 -#define IMX6QDL_CLK_VDO_AXI_SEL 55 -#define IMX6QDL_CLK_VPU_AXI_SEL 56 -#define IMX6QDL_CLK_CKO1_SEL 57 -#define IMX6QDL_CLK_PERIPH 58 -#define IMX6QDL_CLK_PERIPH2 59 -#define IMX6QDL_CLK_PERIPH_CLK2 60 -#define IMX6QDL_CLK_PERIPH2_CLK2 61 -#define IMX6QDL_CLK_IPG 62 -#define IMX6QDL_CLK_IPG_PER 63 -#define IMX6QDL_CLK_ESAI_PRED 64 -#define IMX6QDL_CLK_ESAI_PODF 65 -#define IMX6QDL_CLK_ASRC_PRED 66 -#define IMX6QDL_CLK_ASRC_PODF 67 -#define IMX6QDL_CLK_SPDIF_PRED 68 -#define IMX6QDL_CLK_SPDIF_PODF 69 -#define IMX6QDL_CLK_CAN_ROOT 70 -#define IMX6QDL_CLK_ECSPI_ROOT 71 -#define IMX6QDL_CLK_GPU2D_CORE_PODF 72 -#define IMX6QDL_CLK_GPU3D_CORE_PODF 73 -#define IMX6QDL_CLK_GPU3D_SHADER 74 -#define IMX6QDL_CLK_IPU1_PODF 75 -#define IMX6QDL_CLK_IPU2_PODF 76 -#define IMX6QDL_CLK_LDB_DI0_PODF 77 -#define IMX6QDL_CLK_LDB_DI1_PODF 78 -#define IMX6QDL_CLK_IPU1_DI0_PRE 79 -#define IMX6QDL_CLK_IPU1_DI1_PRE 80 -#define IMX6QDL_CLK_IPU2_DI0_PRE 81 -#define IMX6QDL_CLK_IPU2_DI1_PRE 82 -#define IMX6QDL_CLK_HSI_TX_PODF 83 -#define IMX6QDL_CLK_SSI1_PRED 84 -#define IMX6QDL_CLK_SSI1_PODF 85 -#define IMX6QDL_CLK_SSI2_PRED 86 -#define IMX6QDL_CLK_SSI2_PODF 87 -#define IMX6QDL_CLK_SSI3_PRED 88 -#define IMX6QDL_CLK_SSI3_PODF 89 -#define IMX6QDL_CLK_UART_SERIAL_PODF 90 -#define IMX6QDL_CLK_USDHC1_PODF 91 -#define IMX6QDL_CLK_USDHC2_PODF 92 -#define IMX6QDL_CLK_USDHC3_PODF 93 -#define IMX6QDL_CLK_USDHC4_PODF 94 -#define IMX6QDL_CLK_ENFC_PRED 95 -#define IMX6QDL_CLK_ENFC_PODF 96 -#define IMX6QDL_CLK_EIM_PODF 97 -#define IMX6QDL_CLK_EIM_SLOW_PODF 98 -#define IMX6QDL_CLK_VPU_AXI_PODF 99 -#define IMX6QDL_CLK_CKO1_PODF 100 -#define IMX6QDL_CLK_AXI 101 -#define IMX6QDL_CLK_MMDC_CH0_AXI_PODF 102 -#define IMX6QDL_CLK_MMDC_CH1_AXI_PODF 103 -#define IMX6QDL_CLK_ARM 104 -#define IMX6QDL_CLK_AHB 105 -#define IMX6QDL_CLK_APBH_DMA 106 -#define IMX6QDL_CLK_ASRC 107 -#define IMX6QDL_CLK_CAN1_IPG 108 -#define IMX6QDL_CLK_CAN1_SERIAL 109 -#define IMX6QDL_CLK_CAN2_IPG 110 -#define IMX6QDL_CLK_CAN2_SERIAL 111 -#define IMX6QDL_CLK_ECSPI1 112 -#define IMX6QDL_CLK_ECSPI2 113 -#define IMX6QDL_CLK_ECSPI3 114 -#define IMX6QDL_CLK_ECSPI4 115 -#define IMX6Q_CLK_ECSPI5 116 -#define IMX6DL_CLK_I2C4 116 -#define IMX6QDL_CLK_ENET 117 -#define IMX6QDL_CLK_ESAI_EXTAL 118 -#define IMX6QDL_CLK_GPT_IPG 119 -#define IMX6QDL_CLK_GPT_IPG_PER 120 -#define IMX6QDL_CLK_GPU2D_CORE 121 -#define IMX6QDL_CLK_GPU3D_CORE 122 -#define IMX6QDL_CLK_HDMI_IAHB 123 -#define IMX6QDL_CLK_HDMI_ISFR 124 -#define IMX6QDL_CLK_I2C1 125 -#define IMX6QDL_CLK_I2C2 126 -#define IMX6QDL_CLK_I2C3 127 -#define IMX6QDL_CLK_IIM 128 -#define IMX6QDL_CLK_ENFC 129 -#define IMX6QDL_CLK_IPU1 130 -#define IMX6QDL_CLK_IPU1_DI0 131 -#define IMX6QDL_CLK_IPU1_DI1 132 -#define IMX6QDL_CLK_IPU2 133 -#define IMX6QDL_CLK_IPU2_DI0 134 -#define IMX6QDL_CLK_LDB_DI0 135 -#define IMX6QDL_CLK_LDB_DI1 136 -#define IMX6QDL_CLK_IPU2_DI1 137 -#define IMX6QDL_CLK_HSI_TX 138 -#define IMX6QDL_CLK_MLB 139 -#define IMX6QDL_CLK_MMDC_CH0_AXI 140 -#define IMX6QDL_CLK_MMDC_CH1_AXI 141 -#define IMX6QDL_CLK_OCRAM 142 -#define IMX6QDL_CLK_OPENVG_AXI 143 -#define IMX6QDL_CLK_PCIE_AXI 144 -#define IMX6QDL_CLK_PWM1 145 -#define IMX6QDL_CLK_PWM2 146 -#define IMX6QDL_CLK_PWM3 147 -#define IMX6QDL_CLK_PWM4 148 -#define IMX6QDL_CLK_PER1_BCH 149 -#define IMX6QDL_CLK_GPMI_BCH_APB 150 -#define IMX6QDL_CLK_GPMI_BCH 151 -#define IMX6QDL_CLK_GPMI_IO 152 -#define IMX6QDL_CLK_GPMI_APB 153 -#define IMX6QDL_CLK_SATA 154 -#define IMX6QDL_CLK_SDMA 155 -#define IMX6QDL_CLK_SPBA 156 -#define IMX6QDL_CLK_SSI1 157 -#define IMX6QDL_CLK_SSI2 158 -#define IMX6QDL_CLK_SSI3 159 -#define IMX6QDL_CLK_UART_IPG 160 -#define IMX6QDL_CLK_UART_SERIAL 161 -#define IMX6QDL_CLK_USBOH3 162 -#define IMX6QDL_CLK_USDHC1 163 -#define IMX6QDL_CLK_USDHC2 164 -#define IMX6QDL_CLK_USDHC3 165 -#define IMX6QDL_CLK_USDHC4 166 -#define IMX6QDL_CLK_VDO_AXI 167 -#define IMX6QDL_CLK_VPU_AXI 168 -#define IMX6QDL_CLK_CKO1 169 -#define IMX6QDL_CLK_PLL1_SYS 170 -#define IMX6QDL_CLK_PLL2_BUS 171 -#define IMX6QDL_CLK_PLL3_USB_OTG 172 -#define IMX6QDL_CLK_PLL4_AUDIO 173 -#define IMX6QDL_CLK_PLL5_VIDEO 174 -#define IMX6QDL_CLK_PLL8_MLB 175 -#define IMX6QDL_CLK_PLL7_USB_HOST 176 -#define IMX6QDL_CLK_PLL6_ENET 177 -#define IMX6QDL_CLK_SSI1_IPG 178 -#define IMX6QDL_CLK_SSI2_IPG 179 -#define IMX6QDL_CLK_SSI3_IPG 180 -#define IMX6QDL_CLK_ROM 181 -#define IMX6QDL_CLK_USBPHY1 182 -#define IMX6QDL_CLK_USBPHY2 183 -#define IMX6QDL_CLK_LDB_DI0_DIV_3_5 184 -#define IMX6QDL_CLK_LDB_DI1_DIV_3_5 185 -#define IMX6QDL_CLK_SATA_REF 186 -#define IMX6QDL_CLK_SATA_REF_100M 187 -#define IMX6QDL_CLK_PCIE_REF 188 -#define IMX6QDL_CLK_PCIE_REF_125M 189 -#define IMX6QDL_CLK_ENET_REF 190 -#define IMX6QDL_CLK_USBPHY1_GATE 191 -#define IMX6QDL_CLK_USBPHY2_GATE 192 -#define IMX6QDL_CLK_PLL4_POST_DIV 193 -#define IMX6QDL_CLK_PLL5_POST_DIV 194 -#define IMX6QDL_CLK_PLL5_VIDEO_DIV 195 -#define IMX6QDL_CLK_EIM_SLOW 196 -#define IMX6QDL_CLK_SPDIF 197 -#define IMX6QDL_CLK_CKO2_SEL 198 -#define IMX6QDL_CLK_CKO2_PODF 199 -#define IMX6QDL_CLK_CKO2 200 -#define IMX6QDL_CLK_CKO 201 -#define IMX6QDL_CLK_VDOA 202 -#define IMX6QDL_CLK_PLL4_AUDIO_DIV 203 -#define IMX6QDL_CLK_LVDS1_SEL 204 -#define IMX6QDL_CLK_LVDS2_SEL 205 -#define IMX6QDL_CLK_LVDS1_GATE 206 -#define IMX6QDL_CLK_LVDS2_GATE 207 -#define IMX6QDL_CLK_ESAI_IPG 208 -#define IMX6QDL_CLK_ESAI_MEM 209 -#define IMX6QDL_CLK_ASRC_IPG 210 -#define IMX6QDL_CLK_ASRC_MEM 211 -#define IMX6QDL_CLK_LVDS1_IN 212 -#define IMX6QDL_CLK_LVDS2_IN 213 -#define IMX6QDL_CLK_ANACLK1 214 -#define IMX6QDL_CLK_ANACLK2 215 -#define IMX6QDL_PLL1_BYPASS_SRC 216 -#define IMX6QDL_PLL2_BYPASS_SRC 217 -#define IMX6QDL_PLL3_BYPASS_SRC 218 -#define IMX6QDL_PLL4_BYPASS_SRC 219 -#define IMX6QDL_PLL5_BYPASS_SRC 220 -#define IMX6QDL_PLL6_BYPASS_SRC 221 -#define IMX6QDL_PLL7_BYPASS_SRC 222 -#define IMX6QDL_CLK_PLL1 223 -#define IMX6QDL_CLK_PLL2 224 -#define IMX6QDL_CLK_PLL3 225 -#define IMX6QDL_CLK_PLL4 226 -#define IMX6QDL_CLK_PLL5 227 -#define IMX6QDL_CLK_PLL6 228 -#define IMX6QDL_CLK_PLL7 229 -#define IMX6QDL_PLL1_BYPASS 230 -#define IMX6QDL_PLL2_BYPASS 231 -#define IMX6QDL_PLL3_BYPASS 232 -#define IMX6QDL_PLL4_BYPASS 233 -#define IMX6QDL_PLL5_BYPASS 234 -#define IMX6QDL_PLL6_BYPASS 235 -#define IMX6QDL_PLL7_BYPASS 236 -#define IMX6QDL_CLK_GPT_3M 237 -#define IMX6QDL_CLK_VIDEO_27M 238 -#define IMX6QDL_CLK_MIPI_CORE_CFG 239 -#define IMX6QDL_CLK_MIPI_IPG 240 -#define IMX6QDL_CLK_CAAM_MEM 241 -#define IMX6QDL_CLK_CAAM_ACLK 242 -#define IMX6QDL_CLK_CAAM_IPG 243 -#define IMX6QDL_CLK_SPDIF_GCLK 244 -#define IMX6QDL_CLK_UART_SEL 245 -#define IMX6QDL_CLK_IPG_PER_SEL 246 -#define IMX6QDL_CLK_ECSPI_SEL 247 -#define IMX6QDL_CLK_CAN_SEL 248 -#define IMX6QDL_CLK_MMDC_CH1_AXI_CG 249 -#define IMX6QDL_CLK_PRE0 250 -#define IMX6QDL_CLK_PRE1 251 -#define IMX6QDL_CLK_PRE2 252 -#define IMX6QDL_CLK_PRE3 253 -#define IMX6QDL_CLK_PRG0_AXI 254 -#define IMX6QDL_CLK_PRG1_AXI 255 -#define IMX6QDL_CLK_PRG0_APB 256 -#define IMX6QDL_CLK_PRG1_APB 257 -#define IMX6QDL_CLK_PRE_AXI 258 -#define IMX6QDL_CLK_MLB_SEL 259 -#define IMX6QDL_CLK_MLB_PODF 260 -#define IMX6QDL_CLK_EPIT1 261 -#define IMX6QDL_CLK_EPIT2 262 -#define IMX6QDL_CLK_MMDC_P0_IPG 263 -#define IMX6QDL_CLK_DCIC1 264 -#define IMX6QDL_CLK_DCIC2 265 -#define IMX6QDL_CLK_END 266 - -#endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/imx6sl-clock.h b/sys/gnu/dts/include/dt-bindings/clock/imx6sl-clock.h deleted file mode 100644 index 31364d2caae..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/imx6sl-clock.h +++ /dev/null @@ -1,178 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - */ - -#ifndef __DT_BINDINGS_CLOCK_IMX6SL_H -#define __DT_BINDINGS_CLOCK_IMX6SL_H - -#define IMX6SL_CLK_DUMMY 0 -#define IMX6SL_CLK_CKIL 1 -#define IMX6SL_CLK_OSC 2 -#define IMX6SL_CLK_PLL1_SYS 3 -#define IMX6SL_CLK_PLL2_BUS 4 -#define IMX6SL_CLK_PLL3_USB_OTG 5 -#define IMX6SL_CLK_PLL4_AUDIO 6 -#define IMX6SL_CLK_PLL5_VIDEO 7 -#define IMX6SL_CLK_PLL6_ENET 8 -#define IMX6SL_CLK_PLL7_USB_HOST 9 -#define IMX6SL_CLK_USBPHY1 10 -#define IMX6SL_CLK_USBPHY2 11 -#define IMX6SL_CLK_USBPHY1_GATE 12 -#define IMX6SL_CLK_USBPHY2_GATE 13 -#define IMX6SL_CLK_PLL4_POST_DIV 14 -#define IMX6SL_CLK_PLL5_POST_DIV 15 -#define IMX6SL_CLK_PLL5_VIDEO_DIV 16 -#define IMX6SL_CLK_ENET_REF 17 -#define IMX6SL_CLK_PLL2_PFD0 18 -#define IMX6SL_CLK_PLL2_PFD1 19 -#define IMX6SL_CLK_PLL2_PFD2 20 -#define IMX6SL_CLK_PLL3_PFD0 21 -#define IMX6SL_CLK_PLL3_PFD1 22 -#define IMX6SL_CLK_PLL3_PFD2 23 -#define IMX6SL_CLK_PLL3_PFD3 24 -#define IMX6SL_CLK_PLL2_198M 25 -#define IMX6SL_CLK_PLL3_120M 26 -#define IMX6SL_CLK_PLL3_80M 27 -#define IMX6SL_CLK_PLL3_60M 28 -#define IMX6SL_CLK_STEP 29 -#define IMX6SL_CLK_PLL1_SW 30 -#define IMX6SL_CLK_OCRAM_ALT_SEL 31 -#define IMX6SL_CLK_OCRAM_SEL 32 -#define IMX6SL_CLK_PRE_PERIPH2_SEL 33 -#define IMX6SL_CLK_PRE_PERIPH_SEL 34 -#define IMX6SL_CLK_PERIPH2_CLK2_SEL 35 -#define IMX6SL_CLK_PERIPH_CLK2_SEL 36 -#define IMX6SL_CLK_CSI_SEL 37 -#define IMX6SL_CLK_LCDIF_AXI_SEL 38 -#define IMX6SL_CLK_USDHC1_SEL 39 -#define IMX6SL_CLK_USDHC2_SEL 40 -#define IMX6SL_CLK_USDHC3_SEL 41 -#define IMX6SL_CLK_USDHC4_SEL 42 -#define IMX6SL_CLK_SSI1_SEL 43 -#define IMX6SL_CLK_SSI2_SEL 44 -#define IMX6SL_CLK_SSI3_SEL 45 -#define IMX6SL_CLK_PERCLK_SEL 46 -#define IMX6SL_CLK_PXP_AXI_SEL 47 -#define IMX6SL_CLK_EPDC_AXI_SEL 48 -#define IMX6SL_CLK_GPU2D_OVG_SEL 49 -#define IMX6SL_CLK_GPU2D_SEL 50 -#define IMX6SL_CLK_LCDIF_PIX_SEL 51 -#define IMX6SL_CLK_EPDC_PIX_SEL 52 -#define IMX6SL_CLK_SPDIF0_SEL 53 -#define IMX6SL_CLK_SPDIF1_SEL 54 -#define IMX6SL_CLK_EXTERN_AUDIO_SEL 55 -#define IMX6SL_CLK_ECSPI_SEL 56 -#define IMX6SL_CLK_UART_SEL 57 -#define IMX6SL_CLK_PERIPH 58 -#define IMX6SL_CLK_PERIPH2 59 -#define IMX6SL_CLK_OCRAM_PODF 60 -#define IMX6SL_CLK_PERIPH_CLK2_PODF 61 -#define IMX6SL_CLK_PERIPH2_CLK2_PODF 62 -#define IMX6SL_CLK_IPG 63 -#define IMX6SL_CLK_CSI_PODF 64 -#define IMX6SL_CLK_LCDIF_AXI_PODF 65 -#define IMX6SL_CLK_USDHC1_PODF 66 -#define IMX6SL_CLK_USDHC2_PODF 67 -#define IMX6SL_CLK_USDHC3_PODF 68 -#define IMX6SL_CLK_USDHC4_PODF 69 -#define IMX6SL_CLK_SSI1_PRED 70 -#define IMX6SL_CLK_SSI1_PODF 71 -#define IMX6SL_CLK_SSI2_PRED 72 -#define IMX6SL_CLK_SSI2_PODF 73 -#define IMX6SL_CLK_SSI3_PRED 74 -#define IMX6SL_CLK_SSI3_PODF 75 -#define IMX6SL_CLK_PERCLK 76 -#define IMX6SL_CLK_PXP_AXI_PODF 77 -#define IMX6SL_CLK_EPDC_AXI_PODF 78 -#define IMX6SL_CLK_GPU2D_OVG_PODF 79 -#define IMX6SL_CLK_GPU2D_PODF 80 -#define IMX6SL_CLK_LCDIF_PIX_PRED 81 -#define IMX6SL_CLK_EPDC_PIX_PRED 82 -#define IMX6SL_CLK_LCDIF_PIX_PODF 83 -#define IMX6SL_CLK_EPDC_PIX_PODF 84 -#define IMX6SL_CLK_SPDIF0_PRED 85 -#define IMX6SL_CLK_SPDIF0_PODF 86 -#define IMX6SL_CLK_SPDIF1_PRED 87 -#define IMX6SL_CLK_SPDIF1_PODF 88 -#define IMX6SL_CLK_EXTERN_AUDIO_PRED 89 -#define IMX6SL_CLK_EXTERN_AUDIO_PODF 90 -#define IMX6SL_CLK_ECSPI_ROOT 91 -#define IMX6SL_CLK_UART_ROOT 92 -#define IMX6SL_CLK_AHB 93 -#define IMX6SL_CLK_MMDC_ROOT 94 -#define IMX6SL_CLK_ARM 95 -#define IMX6SL_CLK_ECSPI1 96 -#define IMX6SL_CLK_ECSPI2 97 -#define IMX6SL_CLK_ECSPI3 98 -#define IMX6SL_CLK_ECSPI4 99 -#define IMX6SL_CLK_EPIT1 100 -#define IMX6SL_CLK_EPIT2 101 -#define IMX6SL_CLK_EXTERN_AUDIO 102 -#define IMX6SL_CLK_GPT 103 -#define IMX6SL_CLK_GPT_SERIAL 104 -#define IMX6SL_CLK_GPU2D_OVG 105 -#define IMX6SL_CLK_I2C1 106 -#define IMX6SL_CLK_I2C2 107 -#define IMX6SL_CLK_I2C3 108 -#define IMX6SL_CLK_OCOTP 109 -#define IMX6SL_CLK_CSI 110 -#define IMX6SL_CLK_PXP_AXI 111 -#define IMX6SL_CLK_EPDC_AXI 112 -#define IMX6SL_CLK_LCDIF_AXI 113 -#define IMX6SL_CLK_LCDIF_PIX 114 -#define IMX6SL_CLK_EPDC_PIX 115 -#define IMX6SL_CLK_OCRAM 116 -#define IMX6SL_CLK_PWM1 117 -#define IMX6SL_CLK_PWM2 118 -#define IMX6SL_CLK_PWM3 119 -#define IMX6SL_CLK_PWM4 120 -#define IMX6SL_CLK_SDMA 121 -#define IMX6SL_CLK_SPDIF 122 -#define IMX6SL_CLK_SSI1 123 -#define IMX6SL_CLK_SSI2 124 -#define IMX6SL_CLK_SSI3 125 -#define IMX6SL_CLK_UART 126 -#define IMX6SL_CLK_UART_SERIAL 127 -#define IMX6SL_CLK_USBOH3 128 -#define IMX6SL_CLK_USDHC1 129 -#define IMX6SL_CLK_USDHC2 130 -#define IMX6SL_CLK_USDHC3 131 -#define IMX6SL_CLK_USDHC4 132 -#define IMX6SL_CLK_PLL4_AUDIO_DIV 133 -#define IMX6SL_CLK_SPBA 134 -#define IMX6SL_CLK_ENET 135 -#define IMX6SL_CLK_LVDS1_SEL 136 -#define IMX6SL_CLK_LVDS1_OUT 137 -#define IMX6SL_CLK_LVDS1_IN 138 -#define IMX6SL_CLK_ANACLK1 139 -#define IMX6SL_PLL1_BYPASS_SRC 140 -#define IMX6SL_PLL2_BYPASS_SRC 141 -#define IMX6SL_PLL3_BYPASS_SRC 142 -#define IMX6SL_PLL4_BYPASS_SRC 143 -#define IMX6SL_PLL5_BYPASS_SRC 144 -#define IMX6SL_PLL6_BYPASS_SRC 145 -#define IMX6SL_PLL7_BYPASS_SRC 146 -#define IMX6SL_CLK_PLL1 147 -#define IMX6SL_CLK_PLL2 148 -#define IMX6SL_CLK_PLL3 149 -#define IMX6SL_CLK_PLL4 150 -#define IMX6SL_CLK_PLL5 151 -#define IMX6SL_CLK_PLL6 152 -#define IMX6SL_CLK_PLL7 153 -#define IMX6SL_PLL1_BYPASS 154 -#define IMX6SL_PLL2_BYPASS 155 -#define IMX6SL_PLL3_BYPASS 156 -#define IMX6SL_PLL4_BYPASS 157 -#define IMX6SL_PLL5_BYPASS 158 -#define IMX6SL_PLL6_BYPASS 159 -#define IMX6SL_PLL7_BYPASS 160 -#define IMX6SL_CLK_SSI1_IPG 161 -#define IMX6SL_CLK_SSI2_IPG 162 -#define IMX6SL_CLK_SSI3_IPG 163 -#define IMX6SL_CLK_SPDIF_GCLK 164 -#define IMX6SL_CLK_MMDC_P0_IPG 165 -#define IMX6SL_CLK_MMDC_P1_IPG 166 -#define IMX6SL_CLK_END 167 - -#endif /* __DT_BINDINGS_CLOCK_IMX6SL_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/imx6sll-clock.h b/sys/gnu/dts/include/dt-bindings/clock/imx6sll-clock.h deleted file mode 100644 index f446710fe63..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/imx6sll-clock.h +++ /dev/null @@ -1,210 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2016 Freescale Semiconductor, Inc. - * Copyright 2017-2018 NXP. - * - */ - -#ifndef __DT_BINDINGS_CLOCK_IMX6SLL_H -#define __DT_BINDINGS_CLOCK_IMX6SLL_H - -#define IMX6SLL_CLK_DUMMY 0 -#define IMX6SLL_CLK_CKIL 1 -#define IMX6SLL_CLK_OSC 2 -#define IMX6SLL_PLL1_BYPASS_SRC 3 -#define IMX6SLL_PLL2_BYPASS_SRC 4 -#define IMX6SLL_PLL3_BYPASS_SRC 5 -#define IMX6SLL_PLL4_BYPASS_SRC 6 -#define IMX6SLL_PLL5_BYPASS_SRC 7 -#define IMX6SLL_PLL6_BYPASS_SRC 8 -#define IMX6SLL_PLL7_BYPASS_SRC 9 -#define IMX6SLL_CLK_PLL1 10 -#define IMX6SLL_CLK_PLL2 11 -#define IMX6SLL_CLK_PLL3 12 -#define IMX6SLL_CLK_PLL4 13 -#define IMX6SLL_CLK_PLL5 14 -#define IMX6SLL_CLK_PLL6 15 -#define IMX6SLL_CLK_PLL7 16 -#define IMX6SLL_PLL1_BYPASS 17 -#define IMX6SLL_PLL2_BYPASS 18 -#define IMX6SLL_PLL3_BYPASS 19 -#define IMX6SLL_PLL4_BYPASS 20 -#define IMX6SLL_PLL5_BYPASS 21 -#define IMX6SLL_PLL6_BYPASS 22 -#define IMX6SLL_PLL7_BYPASS 23 -#define IMX6SLL_CLK_PLL1_SYS 24 -#define IMX6SLL_CLK_PLL2_BUS 25 -#define IMX6SLL_CLK_PLL3_USB_OTG 26 -#define IMX6SLL_CLK_PLL4_AUDIO 27 -#define IMX6SLL_CLK_PLL5_VIDEO 28 -#define IMX6SLL_CLK_PLL6_ENET 29 -#define IMX6SLL_CLK_PLL7_USB_HOST 30 -#define IMX6SLL_CLK_USBPHY1 31 -#define IMX6SLL_CLK_USBPHY2 32 -#define IMX6SLL_CLK_USBPHY1_GATE 33 -#define IMX6SLL_CLK_USBPHY2_GATE 34 -#define IMX6SLL_CLK_PLL2_PFD0 35 -#define IMX6SLL_CLK_PLL2_PFD1 36 -#define IMX6SLL_CLK_PLL2_PFD2 37 -#define IMX6SLL_CLK_PLL2_PFD3 38 -#define IMX6SLL_CLK_PLL3_PFD0 39 -#define IMX6SLL_CLK_PLL3_PFD1 40 -#define IMX6SLL_CLK_PLL3_PFD2 41 -#define IMX6SLL_CLK_PLL3_PFD3 42 -#define IMX6SLL_CLK_PLL4_POST_DIV 43 -#define IMX6SLL_CLK_PLL4_AUDIO_DIV 44 -#define IMX6SLL_CLK_PLL5_POST_DIV 45 -#define IMX6SLL_CLK_PLL5_VIDEO_DIV 46 -#define IMX6SLL_CLK_PLL2_198M 47 -#define IMX6SLL_CLK_PLL3_120M 48 -#define IMX6SLL_CLK_PLL3_80M 49 -#define IMX6SLL_CLK_PLL3_60M 50 -#define IMX6SLL_CLK_STEP 51 -#define IMX6SLL_CLK_PLL1_SW 52 -#define IMX6SLL_CLK_AXI_ALT_SEL 53 -#define IMX6SLL_CLK_AXI_SEL 54 -#define IMX6SLL_CLK_PERIPH_PRE 55 -#define IMX6SLL_CLK_PERIPH2_PRE 56 -#define IMX6SLL_CLK_PERIPH_CLK2_SEL 57 -#define IMX6SLL_CLK_PERIPH2_CLK2_SEL 58 -#define IMX6SLL_CLK_PERCLK_SEL 59 -#define IMX6SLL_CLK_USDHC1_SEL 60 -#define IMX6SLL_CLK_USDHC2_SEL 61 -#define IMX6SLL_CLK_USDHC3_SEL 62 -#define IMX6SLL_CLK_SSI1_SEL 63 -#define IMX6SLL_CLK_SSI2_SEL 64 -#define IMX6SLL_CLK_SSI3_SEL 65 -#define IMX6SLL_CLK_PXP_SEL 66 -#define IMX6SLL_CLK_LCDIF_PRE_SEL 67 -#define IMX6SLL_CLK_LCDIF_SEL 68 -#define IMX6SLL_CLK_EPDC_PRE_SEL 69 -#define IMX6SLL_CLK_SPDIF_SEL 70 -#define IMX6SLL_CLK_ECSPI_SEL 71 -#define IMX6SLL_CLK_UART_SEL 72 -#define IMX6SLL_CLK_ARM 73 -#define IMX6SLL_CLK_PERIPH 74 -#define IMX6SLL_CLK_PERIPH2 75 -#define IMX6SLL_CLK_PERIPH2_CLK2 76 -#define IMX6SLL_CLK_PERIPH_CLK2 77 -#define IMX6SLL_CLK_MMDC_PODF 78 -#define IMX6SLL_CLK_AXI_PODF 79 -#define IMX6SLL_CLK_AHB 80 -#define IMX6SLL_CLK_IPG 81 -#define IMX6SLL_CLK_PERCLK 82 -#define IMX6SLL_CLK_USDHC1_PODF 83 -#define IMX6SLL_CLK_USDHC2_PODF 84 -#define IMX6SLL_CLK_USDHC3_PODF 85 -#define IMX6SLL_CLK_SSI1_PRED 86 -#define IMX6SLL_CLK_SSI2_PRED 87 -#define IMX6SLL_CLK_SSI3_PRED 88 -#define IMX6SLL_CLK_SSI1_PODF 89 -#define IMX6SLL_CLK_SSI2_PODF 90 -#define IMX6SLL_CLK_SSI3_PODF 91 -#define IMX6SLL_CLK_PXP_PODF 92 -#define IMX6SLL_CLK_LCDIF_PRED 93 -#define IMX6SLL_CLK_LCDIF_PODF 94 -#define IMX6SLL_CLK_EPDC_SEL 95 -#define IMX6SLL_CLK_EPDC_PODF 96 -#define IMX6SLL_CLK_SPDIF_PRED 97 -#define IMX6SLL_CLK_SPDIF_PODF 98 -#define IMX6SLL_CLK_ECSPI_PODF 99 -#define IMX6SLL_CLK_UART_PODF 100 - -/* CCGR 0 */ -#define IMX6SLL_CLK_AIPSTZ1 101 -#define IMX6SLL_CLK_AIPSTZ2 102 -#define IMX6SLL_CLK_DCP 103 -#define IMX6SLL_CLK_UART2_IPG 104 -#define IMX6SLL_CLK_UART2_SERIAL 105 - -/* CCGR 1 */ -#define IMX6SLL_CLK_ECSPI1 106 -#define IMX6SLL_CLK_ECSPI2 107 -#define IMX6SLL_CLK_ECSPI3 108 -#define IMX6SLL_CLK_ECSPI4 109 -#define IMX6SLL_CLK_UART3_IPG 110 -#define IMX6SLL_CLK_UART3_SERIAL 111 -#define IMX6SLL_CLK_UART4_IPG 112 -#define IMX6SLL_CLK_UART4_SERIAL 113 -#define IMX6SLL_CLK_EPIT1 114 -#define IMX6SLL_CLK_EPIT2 115 -#define IMX6SLL_CLK_GPT_BUS 116 -#define IMX6SLL_CLK_GPT_SERIAL 117 - -/* CCGR2 */ -#define IMX6SLL_CLK_CSI 118 -#define IMX6SLL_CLK_I2C1 119 -#define IMX6SLL_CLK_I2C2 120 -#define IMX6SLL_CLK_I2C3 121 -#define IMX6SLL_CLK_OCOTP 122 -#define IMX6SLL_CLK_LCDIF_APB 123 -#define IMX6SLL_CLK_PXP 124 - -/* CCGR3 */ -#define IMX6SLL_CLK_UART5_IPG 125 -#define IMX6SLL_CLK_UART5_SERIAL 126 -#define IMX6SLL_CLK_EPDC_AXI 127 -#define IMX6SLL_CLK_EPDC_PIX 128 -#define IMX6SLL_CLK_LCDIF_PIX 129 -#define IMX6SLL_CLK_WDOG1 130 -#define IMX6SLL_CLK_MMDC_P0_FAST 131 -#define IMX6SLL_CLK_MMDC_P0_IPG 132 -#define IMX6SLL_CLK_OCRAM 133 - -/* CCGR4 */ -#define IMX6SLL_CLK_PWM1 134 -#define IMX6SLL_CLK_PWM2 135 -#define IMX6SLL_CLK_PWM3 136 -#define IMX6SLL_CLK_PWM4 137 - -/* CCGR 5 */ -#define IMX6SLL_CLK_ROM 138 -#define IMX6SLL_CLK_SDMA 139 -#define IMX6SLL_CLK_KPP 140 -#define IMX6SLL_CLK_WDOG2 141 -#define IMX6SLL_CLK_SPBA 142 -#define IMX6SLL_CLK_SPDIF 143 -#define IMX6SLL_CLK_SPDIF_GCLK 144 -#define IMX6SLL_CLK_SSI1 145 -#define IMX6SLL_CLK_SSI1_IPG 146 -#define IMX6SLL_CLK_SSI2 147 -#define IMX6SLL_CLK_SSI2_IPG 148 -#define IMX6SLL_CLK_SSI3 149 -#define IMX6SLL_CLK_SSI3_IPG 150 -#define IMX6SLL_CLK_UART1_IPG 151 -#define IMX6SLL_CLK_UART1_SERIAL 152 - -/* CCGR 6 */ -#define IMX6SLL_CLK_USBOH3 153 -#define IMX6SLL_CLK_USDHC1 154 -#define IMX6SLL_CLK_USDHC2 155 -#define IMX6SLL_CLK_USDHC3 156 - -#define IMX6SLL_CLK_IPP_DI0 157 -#define IMX6SLL_CLK_IPP_DI1 158 -#define IMX6SLL_CLK_LDB_DI0_SEL 159 -#define IMX6SLL_CLK_LDB_DI0_DIV_3_5 160 -#define IMX6SLL_CLK_LDB_DI0_DIV_7 161 -#define IMX6SLL_CLK_LDB_DI0_DIV_SEL 162 -#define IMX6SLL_CLK_LDB_DI0 163 -#define IMX6SLL_CLK_LDB_DI1_SEL 164 -#define IMX6SLL_CLK_LDB_DI1_DIV_3_5 165 -#define IMX6SLL_CLK_LDB_DI1_DIV_7 166 -#define IMX6SLL_CLK_LDB_DI1_DIV_SEL 167 -#define IMX6SLL_CLK_LDB_DI1 168 -#define IMX6SLL_CLK_EXTERN_AUDIO_SEL 169 -#define IMX6SLL_CLK_EXTERN_AUDIO_PRED 170 -#define IMX6SLL_CLK_EXTERN_AUDIO_PODF 171 -#define IMX6SLL_CLK_EXTERN_AUDIO 172 - -#define IMX6SLL_CLK_GPIO1 173 -#define IMX6SLL_CLK_GPIO2 174 -#define IMX6SLL_CLK_GPIO3 175 -#define IMX6SLL_CLK_GPIO4 176 -#define IMX6SLL_CLK_GPIO5 177 -#define IMX6SLL_CLK_GPIO6 178 -#define IMX6SLL_CLK_MMDC_P1_IPG 179 - -#define IMX6SLL_CLK_END 180 - -#endif /* __DT_BINDINGS_CLOCK_IMX6SLL_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/imx6sx-clock.h b/sys/gnu/dts/include/dt-bindings/clock/imx6sx-clock.h deleted file mode 100644 index 1c64997d619..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/imx6sx-clock.h +++ /dev/null @@ -1,281 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) 2014 Freescale Semiconductor, Inc. - */ - -#ifndef __DT_BINDINGS_CLOCK_IMX6SX_H -#define __DT_BINDINGS_CLOCK_IMX6SX_H - -#define IMX6SX_CLK_DUMMY 0 -#define IMX6SX_CLK_CKIL 1 -#define IMX6SX_CLK_CKIH 2 -#define IMX6SX_CLK_OSC 3 -#define IMX6SX_CLK_PLL1_SYS 4 -#define IMX6SX_CLK_PLL2_BUS 5 -#define IMX6SX_CLK_PLL3_USB_OTG 6 -#define IMX6SX_CLK_PLL4_AUDIO 7 -#define IMX6SX_CLK_PLL5_VIDEO 8 -#define IMX6SX_CLK_PLL6_ENET 9 -#define IMX6SX_CLK_PLL7_USB_HOST 10 -#define IMX6SX_CLK_USBPHY1 11 -#define IMX6SX_CLK_USBPHY2 12 -#define IMX6SX_CLK_USBPHY1_GATE 13 -#define IMX6SX_CLK_USBPHY2_GATE 14 -#define IMX6SX_CLK_PCIE_REF 15 -#define IMX6SX_CLK_PCIE_REF_125M 16 -#define IMX6SX_CLK_ENET_REF 17 -#define IMX6SX_CLK_PLL2_PFD0 18 -#define IMX6SX_CLK_PLL2_PFD1 19 -#define IMX6SX_CLK_PLL2_PFD2 20 -#define IMX6SX_CLK_PLL2_PFD3 21 -#define IMX6SX_CLK_PLL3_PFD0 22 -#define IMX6SX_CLK_PLL3_PFD1 23 -#define IMX6SX_CLK_PLL3_PFD2 24 -#define IMX6SX_CLK_PLL3_PFD3 25 -#define IMX6SX_CLK_PLL2_198M 26 -#define IMX6SX_CLK_PLL3_120M 27 -#define IMX6SX_CLK_PLL3_80M 28 -#define IMX6SX_CLK_PLL3_60M 29 -#define IMX6SX_CLK_TWD 30 -#define IMX6SX_CLK_PLL4_POST_DIV 31 -#define IMX6SX_CLK_PLL4_AUDIO_DIV 32 -#define IMX6SX_CLK_PLL5_POST_DIV 33 -#define IMX6SX_CLK_PLL5_VIDEO_DIV 34 -#define IMX6SX_CLK_STEP 35 -#define IMX6SX_CLK_PLL1_SW 36 -#define IMX6SX_CLK_OCRAM_SEL 37 -#define IMX6SX_CLK_PERIPH_PRE 38 -#define IMX6SX_CLK_PERIPH2_PRE 39 -#define IMX6SX_CLK_PERIPH_CLK2_SEL 40 -#define IMX6SX_CLK_PERIPH2_CLK2_SEL 41 -#define IMX6SX_CLK_PCIE_AXI_SEL 42 -#define IMX6SX_CLK_GPU_AXI_SEL 43 -#define IMX6SX_CLK_GPU_CORE_SEL 44 -#define IMX6SX_CLK_EIM_SLOW_SEL 45 -#define IMX6SX_CLK_USDHC1_SEL 46 -#define IMX6SX_CLK_USDHC2_SEL 47 -#define IMX6SX_CLK_USDHC3_SEL 48 -#define IMX6SX_CLK_USDHC4_SEL 49 -#define IMX6SX_CLK_SSI1_SEL 50 -#define IMX6SX_CLK_SSI2_SEL 51 -#define IMX6SX_CLK_SSI3_SEL 52 -#define IMX6SX_CLK_QSPI1_SEL 53 -#define IMX6SX_CLK_PERCLK_SEL 54 -#define IMX6SX_CLK_VID_SEL 55 -#define IMX6SX_CLK_ESAI_SEL 56 -#define IMX6SX_CLK_LDB_DI0_DIV_SEL 57 -#define IMX6SX_CLK_LDB_DI1_DIV_SEL 58 -#define IMX6SX_CLK_CAN_SEL 59 -#define IMX6SX_CLK_UART_SEL 60 -#define IMX6SX_CLK_QSPI2_SEL 61 -#define IMX6SX_CLK_LDB_DI1_SEL 62 -#define IMX6SX_CLK_LDB_DI0_SEL 63 -#define IMX6SX_CLK_SPDIF_SEL 64 -#define IMX6SX_CLK_AUDIO_SEL 65 -#define IMX6SX_CLK_ENET_PRE_SEL 66 -#define IMX6SX_CLK_ENET_SEL 67 -#define IMX6SX_CLK_M4_PRE_SEL 68 -#define IMX6SX_CLK_M4_SEL 69 -#define IMX6SX_CLK_ECSPI_SEL 70 -#define IMX6SX_CLK_LCDIF1_PRE_SEL 71 -#define IMX6SX_CLK_LCDIF2_PRE_SEL 72 -#define IMX6SX_CLK_LCDIF1_SEL 73 -#define IMX6SX_CLK_LCDIF2_SEL 74 -#define IMX6SX_CLK_DISPLAY_SEL 75 -#define IMX6SX_CLK_CSI_SEL 76 -#define IMX6SX_CLK_CKO1_SEL 77 -#define IMX6SX_CLK_CKO2_SEL 78 -#define IMX6SX_CLK_CKO 79 -#define IMX6SX_CLK_PERIPH_CLK2 80 -#define IMX6SX_CLK_PERIPH2_CLK2 81 -#define IMX6SX_CLK_IPG 82 -#define IMX6SX_CLK_GPU_CORE_PODF 83 -#define IMX6SX_CLK_GPU_AXI_PODF 84 -#define IMX6SX_CLK_LCDIF1_PODF 85 -#define IMX6SX_CLK_QSPI1_PODF 86 -#define IMX6SX_CLK_EIM_SLOW_PODF 87 -#define IMX6SX_CLK_LCDIF2_PODF 88 -#define IMX6SX_CLK_PERCLK 89 -#define IMX6SX_CLK_VID_PODF 90 -#define IMX6SX_CLK_CAN_PODF 91 -#define IMX6SX_CLK_USDHC1_PODF 92 -#define IMX6SX_CLK_USDHC2_PODF 93 -#define IMX6SX_CLK_USDHC3_PODF 94 -#define IMX6SX_CLK_USDHC4_PODF 95 -#define IMX6SX_CLK_UART_PODF 96 -#define IMX6SX_CLK_ESAI_PRED 97 -#define IMX6SX_CLK_ESAI_PODF 98 -#define IMX6SX_CLK_SSI3_PRED 99 -#define IMX6SX_CLK_SSI3_PODF 100 -#define IMX6SX_CLK_SSI1_PRED 101 -#define IMX6SX_CLK_SSI1_PODF 102 -#define IMX6SX_CLK_QSPI2_PRED 103 -#define IMX6SX_CLK_QSPI2_PODF 104 -#define IMX6SX_CLK_SSI2_PRED 105 -#define IMX6SX_CLK_SSI2_PODF 106 -#define IMX6SX_CLK_SPDIF_PRED 107 -#define IMX6SX_CLK_SPDIF_PODF 108 -#define IMX6SX_CLK_AUDIO_PRED 109 -#define IMX6SX_CLK_AUDIO_PODF 110 -#define IMX6SX_CLK_ENET_PODF 111 -#define IMX6SX_CLK_M4_PODF 112 -#define IMX6SX_CLK_ECSPI_PODF 113 -#define IMX6SX_CLK_LCDIF1_PRED 114 -#define IMX6SX_CLK_LCDIF2_PRED 115 -#define IMX6SX_CLK_DISPLAY_PODF 116 -#define IMX6SX_CLK_CSI_PODF 117 -#define IMX6SX_CLK_LDB_DI0_DIV_3_5 118 -#define IMX6SX_CLK_LDB_DI0_DIV_7 119 -#define IMX6SX_CLK_LDB_DI1_DIV_3_5 120 -#define IMX6SX_CLK_LDB_DI1_DIV_7 121 -#define IMX6SX_CLK_CKO1_PODF 122 -#define IMX6SX_CLK_CKO2_PODF 123 -#define IMX6SX_CLK_PERIPH 124 -#define IMX6SX_CLK_PERIPH2 125 -#define IMX6SX_CLK_OCRAM 126 -#define IMX6SX_CLK_AHB 127 -#define IMX6SX_CLK_MMDC_PODF 128 -#define IMX6SX_CLK_ARM 129 -#define IMX6SX_CLK_AIPS_TZ1 130 -#define IMX6SX_CLK_AIPS_TZ2 131 -#define IMX6SX_CLK_APBH_DMA 132 -#define IMX6SX_CLK_ASRC_GATE 133 -#define IMX6SX_CLK_CAAM_MEM 134 -#define IMX6SX_CLK_CAAM_ACLK 135 -#define IMX6SX_CLK_CAAM_IPG 136 -#define IMX6SX_CLK_CAN1_IPG 137 -#define IMX6SX_CLK_CAN1_SERIAL 138 -#define IMX6SX_CLK_CAN2_IPG 139 -#define IMX6SX_CLK_CAN2_SERIAL 140 -#define IMX6SX_CLK_CPU_DEBUG 141 -#define IMX6SX_CLK_DCIC1 142 -#define IMX6SX_CLK_DCIC2 143 -#define IMX6SX_CLK_AIPS_TZ3 144 -#define IMX6SX_CLK_ECSPI1 145 -#define IMX6SX_CLK_ECSPI2 146 -#define IMX6SX_CLK_ECSPI3 147 -#define IMX6SX_CLK_ECSPI4 148 -#define IMX6SX_CLK_ECSPI5 149 -#define IMX6SX_CLK_EPIT1 150 -#define IMX6SX_CLK_EPIT2 151 -#define IMX6SX_CLK_ESAI_EXTAL 152 -#define IMX6SX_CLK_WAKEUP 153 -#define IMX6SX_CLK_GPT_BUS 154 -#define IMX6SX_CLK_GPT_SERIAL 155 -#define IMX6SX_CLK_GPU 156 -#define IMX6SX_CLK_OCRAM_S 157 -#define IMX6SX_CLK_CANFD 158 -#define IMX6SX_CLK_CSI 159 -#define IMX6SX_CLK_I2C1 160 -#define IMX6SX_CLK_I2C2 161 -#define IMX6SX_CLK_I2C3 162 -#define IMX6SX_CLK_OCOTP 163 -#define IMX6SX_CLK_IOMUXC 164 -#define IMX6SX_CLK_IPMUX1 165 -#define IMX6SX_CLK_IPMUX2 166 -#define IMX6SX_CLK_IPMUX3 167 -#define IMX6SX_CLK_TZASC1 168 -#define IMX6SX_CLK_LCDIF_APB 169 -#define IMX6SX_CLK_PXP_AXI 170 -#define IMX6SX_CLK_M4 171 -#define IMX6SX_CLK_ENET 172 -#define IMX6SX_CLK_DISPLAY_AXI 173 -#define IMX6SX_CLK_LCDIF2_PIX 174 -#define IMX6SX_CLK_LCDIF1_PIX 175 -#define IMX6SX_CLK_LDB_DI0 176 -#define IMX6SX_CLK_QSPI1 177 -#define IMX6SX_CLK_MLB 178 -#define IMX6SX_CLK_MMDC_P0_FAST 179 -#define IMX6SX_CLK_MMDC_P0_IPG 180 -#define IMX6SX_CLK_AXI 181 -#define IMX6SX_CLK_PCIE_AXI 182 -#define IMX6SX_CLK_QSPI2 183 -#define IMX6SX_CLK_PER1_BCH 184 -#define IMX6SX_CLK_PER2_MAIN 185 -#define IMX6SX_CLK_PWM1 186 -#define IMX6SX_CLK_PWM2 187 -#define IMX6SX_CLK_PWM3 188 -#define IMX6SX_CLK_PWM4 189 -#define IMX6SX_CLK_GPMI_BCH_APB 190 -#define IMX6SX_CLK_GPMI_BCH 191 -#define IMX6SX_CLK_GPMI_IO 192 -#define IMX6SX_CLK_GPMI_APB 193 -#define IMX6SX_CLK_ROM 194 -#define IMX6SX_CLK_SDMA 195 -#define IMX6SX_CLK_SPBA 196 -#define IMX6SX_CLK_SPDIF 197 -#define IMX6SX_CLK_SSI1_IPG 198 -#define IMX6SX_CLK_SSI2_IPG 199 -#define IMX6SX_CLK_SSI3_IPG 200 -#define IMX6SX_CLK_SSI1 201 -#define IMX6SX_CLK_SSI2 202 -#define IMX6SX_CLK_SSI3 203 -#define IMX6SX_CLK_UART_IPG 204 -#define IMX6SX_CLK_UART_SERIAL 205 -#define IMX6SX_CLK_SAI1 206 -#define IMX6SX_CLK_SAI2 207 -#define IMX6SX_CLK_USBOH3 208 -#define IMX6SX_CLK_USDHC1 209 -#define IMX6SX_CLK_USDHC2 210 -#define IMX6SX_CLK_USDHC3 211 -#define IMX6SX_CLK_USDHC4 212 -#define IMX6SX_CLK_EIM_SLOW 213 -#define IMX6SX_CLK_PWM8 214 -#define IMX6SX_CLK_VADC 215 -#define IMX6SX_CLK_GIS 216 -#define IMX6SX_CLK_I2C4 217 -#define IMX6SX_CLK_PWM5 218 -#define IMX6SX_CLK_PWM6 219 -#define IMX6SX_CLK_PWM7 220 -#define IMX6SX_CLK_CKO1 221 -#define IMX6SX_CLK_CKO2 222 -#define IMX6SX_CLK_IPP_DI0 223 -#define IMX6SX_CLK_IPP_DI1 224 -#define IMX6SX_CLK_ENET_AHB 225 -#define IMX6SX_CLK_OCRAM_PODF 226 -#define IMX6SX_CLK_GPT_3M 227 -#define IMX6SX_CLK_ENET_PTP 228 -#define IMX6SX_CLK_ENET_PTP_REF 229 -#define IMX6SX_CLK_ENET2_REF 230 -#define IMX6SX_CLK_ENET2_REF_125M 231 -#define IMX6SX_CLK_AUDIO 232 -#define IMX6SX_CLK_LVDS1_SEL 233 -#define IMX6SX_CLK_LVDS1_OUT 234 -#define IMX6SX_CLK_ASRC_IPG 235 -#define IMX6SX_CLK_ASRC_MEM 236 -#define IMX6SX_CLK_SAI1_IPG 237 -#define IMX6SX_CLK_SAI2_IPG 238 -#define IMX6SX_CLK_ESAI_IPG 239 -#define IMX6SX_CLK_ESAI_MEM 240 -#define IMX6SX_CLK_LVDS1_IN 241 -#define IMX6SX_CLK_ANACLK1 242 -#define IMX6SX_PLL1_BYPASS_SRC 243 -#define IMX6SX_PLL2_BYPASS_SRC 244 -#define IMX6SX_PLL3_BYPASS_SRC 245 -#define IMX6SX_PLL4_BYPASS_SRC 246 -#define IMX6SX_PLL5_BYPASS_SRC 247 -#define IMX6SX_PLL6_BYPASS_SRC 248 -#define IMX6SX_PLL7_BYPASS_SRC 249 -#define IMX6SX_CLK_PLL1 250 -#define IMX6SX_CLK_PLL2 251 -#define IMX6SX_CLK_PLL3 252 -#define IMX6SX_CLK_PLL4 253 -#define IMX6SX_CLK_PLL5 254 -#define IMX6SX_CLK_PLL6 255 -#define IMX6SX_CLK_PLL7 256 -#define IMX6SX_PLL1_BYPASS 257 -#define IMX6SX_PLL2_BYPASS 258 -#define IMX6SX_PLL3_BYPASS 259 -#define IMX6SX_PLL4_BYPASS 260 -#define IMX6SX_PLL5_BYPASS 261 -#define IMX6SX_PLL6_BYPASS 262 -#define IMX6SX_PLL7_BYPASS 263 -#define IMX6SX_CLK_SPDIF_GCLK 264 -#define IMX6SX_CLK_LVDS2_SEL 265 -#define IMX6SX_CLK_LVDS2_OUT 266 -#define IMX6SX_CLK_LVDS2_IN 267 -#define IMX6SX_CLK_ANACLK2 268 -#define IMX6SX_CLK_MMDC_P1_IPG 269 -#define IMX6SX_CLK_CLK_END 270 - -#endif /* __DT_BINDINGS_CLOCK_IMX6SX_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/imx6ul-clock.h b/sys/gnu/dts/include/dt-bindings/clock/imx6ul-clock.h deleted file mode 100644 index 79094338e6f..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/imx6ul-clock.h +++ /dev/null @@ -1,262 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) 2015 Freescale Semiconductor, Inc. - */ - -#ifndef __DT_BINDINGS_CLOCK_IMX6UL_H -#define __DT_BINDINGS_CLOCK_IMX6UL_H - -#define IMX6UL_CLK_DUMMY 0 -#define IMX6UL_CLK_CKIL 1 -#define IMX6UL_CLK_CKIH 2 -#define IMX6UL_CLK_OSC 3 -#define IMX6UL_PLL1_BYPASS_SRC 4 -#define IMX6UL_PLL2_BYPASS_SRC 5 -#define IMX6UL_PLL3_BYPASS_SRC 6 -#define IMX6UL_PLL4_BYPASS_SRC 7 -#define IMX6UL_PLL5_BYPASS_SRC 8 -#define IMX6UL_PLL6_BYPASS_SRC 9 -#define IMX6UL_PLL7_BYPASS_SRC 10 -#define IMX6UL_CLK_PLL1 11 -#define IMX6UL_CLK_PLL2 12 -#define IMX6UL_CLK_PLL3 13 -#define IMX6UL_CLK_PLL4 14 -#define IMX6UL_CLK_PLL5 15 -#define IMX6UL_CLK_PLL6 16 -#define IMX6UL_CLK_PLL7 17 -#define IMX6UL_PLL1_BYPASS 18 -#define IMX6UL_PLL2_BYPASS 19 -#define IMX6UL_PLL3_BYPASS 20 -#define IMX6UL_PLL4_BYPASS 21 -#define IMX6UL_PLL5_BYPASS 22 -#define IMX6UL_PLL6_BYPASS 23 -#define IMX6UL_PLL7_BYPASS 24 -#define IMX6UL_CLK_PLL1_SYS 25 -#define IMX6UL_CLK_PLL2_BUS 26 -#define IMX6UL_CLK_PLL3_USB_OTG 27 -#define IMX6UL_CLK_PLL4_AUDIO 28 -#define IMX6UL_CLK_PLL5_VIDEO 29 -#define IMX6UL_CLK_PLL6_ENET 30 -#define IMX6UL_CLK_PLL7_USB_HOST 31 -#define IMX6UL_CLK_USBPHY1 32 -#define IMX6UL_CLK_USBPHY2 33 -#define IMX6UL_CLK_USBPHY1_GATE 34 -#define IMX6UL_CLK_USBPHY2_GATE 35 -#define IMX6UL_CLK_PLL2_PFD0 36 -#define IMX6UL_CLK_PLL2_PFD1 37 -#define IMX6UL_CLK_PLL2_PFD2 38 -#define IMX6UL_CLK_PLL2_PFD3 39 -#define IMX6UL_CLK_PLL3_PFD0 40 -#define IMX6UL_CLK_PLL3_PFD1 41 -#define IMX6UL_CLK_PLL3_PFD2 42 -#define IMX6UL_CLK_PLL3_PFD3 43 -#define IMX6UL_CLK_ENET_REF 44 -#define IMX6UL_CLK_ENET2_REF 45 -#define IMX6UL_CLK_ENET2_REF_125M 46 -#define IMX6UL_CLK_ENET_PTP_REF 47 -#define IMX6UL_CLK_ENET_PTP 48 -#define IMX6UL_CLK_PLL4_POST_DIV 49 -#define IMX6UL_CLK_PLL4_AUDIO_DIV 50 -#define IMX6UL_CLK_PLL5_POST_DIV 51 -#define IMX6UL_CLK_PLL5_VIDEO_DIV 52 -#define IMX6UL_CLK_PLL2_198M 53 -#define IMX6UL_CLK_PLL3_80M 54 -#define IMX6UL_CLK_PLL3_60M 55 -#define IMX6UL_CLK_STEP 56 -#define IMX6UL_CLK_PLL1_SW 57 -#define IMX6UL_CLK_AXI_ALT_SEL 58 -#define IMX6UL_CLK_AXI_SEL 59 -#define IMX6UL_CLK_PERIPH_PRE 60 -#define IMX6UL_CLK_PERIPH2_PRE 61 -#define IMX6UL_CLK_PERIPH_CLK2_SEL 62 -#define IMX6UL_CLK_PERIPH2_CLK2_SEL 63 -#define IMX6UL_CLK_USDHC1_SEL 64 -#define IMX6UL_CLK_USDHC2_SEL 65 -#define IMX6UL_CLK_BCH_SEL 66 -#define IMX6UL_CLK_GPMI_SEL 67 -#define IMX6UL_CLK_EIM_SLOW_SEL 68 -#define IMX6UL_CLK_SPDIF_SEL 69 -#define IMX6UL_CLK_SAI1_SEL 70 -#define IMX6UL_CLK_SAI2_SEL 71 -#define IMX6UL_CLK_SAI3_SEL 72 -#define IMX6UL_CLK_LCDIF_PRE_SEL 73 -#define IMX6UL_CLK_SIM_PRE_SEL 74 -#define IMX6UL_CLK_LDB_DI0_SEL 75 -#define IMX6UL_CLK_LDB_DI1_SEL 76 -#define IMX6UL_CLK_ENFC_SEL 77 -#define IMX6UL_CLK_CAN_SEL 78 -#define IMX6UL_CLK_ECSPI_SEL 79 -#define IMX6UL_CLK_UART_SEL 80 -#define IMX6UL_CLK_QSPI1_SEL 81 -#define IMX6UL_CLK_PERCLK_SEL 82 -#define IMX6UL_CLK_LCDIF_SEL 83 -#define IMX6UL_CLK_SIM_SEL 84 -#define IMX6UL_CLK_PERIPH 85 -#define IMX6UL_CLK_PERIPH2 86 -#define IMX6UL_CLK_LDB_DI0_DIV_3_5 87 -#define IMX6UL_CLK_LDB_DI0_DIV_7 88 -#define IMX6UL_CLK_LDB_DI1_DIV_3_5 89 -#define IMX6UL_CLK_LDB_DI1_DIV_7 90 -#define IMX6UL_CLK_LDB_DI0_DIV_SEL 91 -#define IMX6UL_CLK_LDB_DI1_DIV_SEL 92 -#define IMX6UL_CLK_ARM 93 -#define IMX6UL_CLK_PERIPH_CLK2 94 -#define IMX6UL_CLK_PERIPH2_CLK2 95 -#define IMX6UL_CLK_AHB 96 -#define IMX6UL_CLK_MMDC_PODF 97 -#define IMX6UL_CLK_AXI_PODF 98 -#define IMX6UL_CLK_PERCLK 99 -#define IMX6UL_CLK_IPG 100 -#define IMX6UL_CLK_USDHC1_PODF 101 -#define IMX6UL_CLK_USDHC2_PODF 102 -#define IMX6UL_CLK_BCH_PODF 103 -#define IMX6UL_CLK_GPMI_PODF 104 -#define IMX6UL_CLK_EIM_SLOW_PODF 105 -#define IMX6UL_CLK_SPDIF_PRED 106 -#define IMX6UL_CLK_SPDIF_PODF 107 -#define IMX6UL_CLK_SAI1_PRED 108 -#define IMX6UL_CLK_SAI1_PODF 109 -#define IMX6UL_CLK_SAI2_PRED 110 -#define IMX6UL_CLK_SAI2_PODF 111 -#define IMX6UL_CLK_SAI3_PRED 112 -#define IMX6UL_CLK_SAI3_PODF 113 -#define IMX6UL_CLK_LCDIF_PRED 114 -#define IMX6UL_CLK_LCDIF_PODF 115 -#define IMX6UL_CLK_SIM_PODF 116 -#define IMX6UL_CLK_QSPI1_PDOF 117 -#define IMX6UL_CLK_ENFC_PRED 118 -#define IMX6UL_CLK_ENFC_PODF 119 -#define IMX6UL_CLK_CAN_PODF 120 -#define IMX6UL_CLK_ECSPI_PODF 121 -#define IMX6UL_CLK_UART_PODF 122 -#define IMX6UL_CLK_ADC1 123 -#define IMX6UL_CLK_ADC2 124 -#define IMX6UL_CLK_AIPSTZ1 125 -#define IMX6UL_CLK_AIPSTZ2 126 -#define IMX6UL_CLK_AIPSTZ3 127 -#define IMX6UL_CLK_APBHDMA 128 -#define IMX6UL_CLK_ASRC_IPG 129 -#define IMX6UL_CLK_ASRC_MEM 130 -#define IMX6UL_CLK_GPMI_BCH_APB 131 -#define IMX6UL_CLK_GPMI_BCH 132 -#define IMX6UL_CLK_GPMI_IO 133 -#define IMX6UL_CLK_GPMI_APB 134 -#define IMX6UL_CLK_CAAM_MEM 135 -#define IMX6UL_CLK_CAAM_ACLK 136 -#define IMX6UL_CLK_CAAM_IPG 137 -#define IMX6UL_CLK_CSI 138 -#define IMX6UL_CLK_ECSPI1 139 -#define IMX6UL_CLK_ECSPI2 140 -#define IMX6UL_CLK_ECSPI3 141 -#define IMX6UL_CLK_ECSPI4 142 -#define IMX6UL_CLK_EIM 143 -#define IMX6UL_CLK_ENET 144 -#define IMX6UL_CLK_ENET_AHB 145 -#define IMX6UL_CLK_EPIT1 146 -#define IMX6UL_CLK_EPIT2 147 -#define IMX6UL_CLK_CAN1_IPG 148 -#define IMX6UL_CLK_CAN1_SERIAL 149 -#define IMX6UL_CLK_CAN2_IPG 150 -#define IMX6UL_CLK_CAN2_SERIAL 151 -#define IMX6UL_CLK_GPT1_BUS 152 -#define IMX6UL_CLK_GPT1_SERIAL 153 -#define IMX6UL_CLK_GPT2_BUS 154 -#define IMX6UL_CLK_GPT2_SERIAL 155 -#define IMX6UL_CLK_I2C1 156 -#define IMX6UL_CLK_I2C2 157 -#define IMX6UL_CLK_I2C3 158 -#define IMX6UL_CLK_I2C4 159 -#define IMX6UL_CLK_IOMUXC 160 -#define IMX6UL_CLK_LCDIF_APB 161 -#define IMX6UL_CLK_LCDIF_PIX 162 -#define IMX6UL_CLK_MMDC_P0_FAST 163 -#define IMX6UL_CLK_MMDC_P0_IPG 164 -#define IMX6UL_CLK_OCOTP 165 -#define IMX6UL_CLK_OCRAM 166 -#define IMX6UL_CLK_PWM1 167 -#define IMX6UL_CLK_PWM2 168 -#define IMX6UL_CLK_PWM3 169 -#define IMX6UL_CLK_PWM4 170 -#define IMX6UL_CLK_PWM5 171 -#define IMX6UL_CLK_PWM6 172 -#define IMX6UL_CLK_PWM7 173 -#define IMX6UL_CLK_PWM8 174 -#define IMX6UL_CLK_PXP 175 -#define IMX6UL_CLK_QSPI 176 -#define IMX6UL_CLK_ROM 177 -#define IMX6UL_CLK_SAI1 178 -#define IMX6UL_CLK_SAI1_IPG 179 -#define IMX6UL_CLK_SAI2 180 -#define IMX6UL_CLK_SAI2_IPG 181 -#define IMX6UL_CLK_SAI3 182 -#define IMX6UL_CLK_SAI3_IPG 183 -#define IMX6UL_CLK_SDMA 184 -#define IMX6UL_CLK_SIM 185 -#define IMX6UL_CLK_SIM_S 186 -#define IMX6UL_CLK_SPBA 187 -#define IMX6UL_CLK_SPDIF 188 -#define IMX6UL_CLK_UART1_IPG 189 -#define IMX6UL_CLK_UART1_SERIAL 190 -#define IMX6UL_CLK_UART2_IPG 191 -#define IMX6UL_CLK_UART2_SERIAL 192 -#define IMX6UL_CLK_UART3_IPG 193 -#define IMX6UL_CLK_UART3_SERIAL 194 -#define IMX6UL_CLK_UART4_IPG 195 -#define IMX6UL_CLK_UART4_SERIAL 196 -#define IMX6UL_CLK_UART5_IPG 197 -#define IMX6UL_CLK_UART5_SERIAL 198 -#define IMX6UL_CLK_UART6_IPG 199 -#define IMX6UL_CLK_UART6_SERIAL 200 -#define IMX6UL_CLK_UART7_IPG 201 -#define IMX6UL_CLK_UART7_SERIAL 202 -#define IMX6UL_CLK_UART8_IPG 203 -#define IMX6UL_CLK_UART8_SERIAL 204 -#define IMX6UL_CLK_USBOH3 205 -#define IMX6UL_CLK_USDHC1 206 -#define IMX6UL_CLK_USDHC2 207 -#define IMX6UL_CLK_WDOG1 208 -#define IMX6UL_CLK_WDOG2 209 -#define IMX6UL_CLK_WDOG3 210 -#define IMX6UL_CLK_LDB_DI0 211 -#define IMX6UL_CLK_AXI 212 -#define IMX6UL_CLK_SPDIF_GCLK 213 -#define IMX6UL_CLK_GPT_3M 214 -#define IMX6UL_CLK_SIM2 215 -#define IMX6UL_CLK_SIM1 216 -#define IMX6UL_CLK_IPP_DI0 217 -#define IMX6UL_CLK_IPP_DI1 218 -#define IMX6UL_CA7_SECONDARY_SEL 219 -#define IMX6UL_CLK_PER_BCH 220 -#define IMX6UL_CLK_CSI_SEL 221 -#define IMX6UL_CLK_CSI_PODF 222 -#define IMX6UL_CLK_PLL3_120M 223 -#define IMX6UL_CLK_KPP 224 -#define IMX6ULL_CLK_ESAI_PRED 225 -#define IMX6ULL_CLK_ESAI_PODF 226 -#define IMX6ULL_CLK_ESAI_EXTAL 227 -#define IMX6ULL_CLK_ESAI_MEM 228 -#define IMX6ULL_CLK_ESAI_IPG 229 -#define IMX6ULL_CLK_DCP_CLK 230 -#define IMX6ULL_CLK_EPDC_PRE_SEL 231 -#define IMX6ULL_CLK_EPDC_SEL 232 -#define IMX6ULL_CLK_EPDC_PODF 233 -#define IMX6ULL_CLK_EPDC_ACLK 234 -#define IMX6ULL_CLK_EPDC_PIX 235 -#define IMX6ULL_CLK_ESAI_SEL 236 -#define IMX6UL_CLK_CKO1_SEL 237 -#define IMX6UL_CLK_CKO1_PODF 238 -#define IMX6UL_CLK_CKO1 239 -#define IMX6UL_CLK_CKO2_SEL 240 -#define IMX6UL_CLK_CKO2_PODF 241 -#define IMX6UL_CLK_CKO2 242 -#define IMX6UL_CLK_CKO 243 -#define IMX6UL_CLK_GPIO1 244 -#define IMX6UL_CLK_GPIO2 245 -#define IMX6UL_CLK_GPIO3 246 -#define IMX6UL_CLK_GPIO4 247 -#define IMX6UL_CLK_GPIO5 248 -#define IMX6UL_CLK_MMDC_P1_IPG 249 - -#define IMX6UL_CLK_END 250 - -#endif /* __DT_BINDINGS_CLOCK_IMX6UL_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/imx7d-clock.h b/sys/gnu/dts/include/dt-bindings/clock/imx7d-clock.h deleted file mode 100644 index e6a670e1a3f..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/imx7d-clock.h +++ /dev/null @@ -1,455 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. - */ - -#ifndef __DT_BINDINGS_CLOCK_IMX7D_H -#define __DT_BINDINGS_CLOCK_IMX7D_H - -#define IMX7D_OSC_24M_CLK 0 -#define IMX7D_PLL_ARM_MAIN 1 -#define IMX7D_PLL_ARM_MAIN_CLK 2 -#define IMX7D_PLL_ARM_MAIN_SRC 3 -#define IMX7D_PLL_ARM_MAIN_BYPASS 4 -#define IMX7D_PLL_SYS_MAIN 5 -#define IMX7D_PLL_SYS_MAIN_CLK 6 -#define IMX7D_PLL_SYS_MAIN_SRC 7 -#define IMX7D_PLL_SYS_MAIN_BYPASS 8 -#define IMX7D_PLL_SYS_MAIN_480M 9 -#define IMX7D_PLL_SYS_MAIN_240M 10 -#define IMX7D_PLL_SYS_MAIN_120M 11 -#define IMX7D_PLL_SYS_MAIN_480M_CLK 12 -#define IMX7D_PLL_SYS_MAIN_240M_CLK 13 -#define IMX7D_PLL_SYS_MAIN_120M_CLK 14 -#define IMX7D_PLL_SYS_PFD0_392M_CLK 15 -#define IMX7D_PLL_SYS_PFD0_196M 16 -#define IMX7D_PLL_SYS_PFD0_196M_CLK 17 -#define IMX7D_PLL_SYS_PFD1_332M_CLK 18 -#define IMX7D_PLL_SYS_PFD1_166M 19 -#define IMX7D_PLL_SYS_PFD1_166M_CLK 20 -#define IMX7D_PLL_SYS_PFD2_270M_CLK 21 -#define IMX7D_PLL_SYS_PFD2_135M 22 -#define IMX7D_PLL_SYS_PFD2_135M_CLK 23 -#define IMX7D_PLL_SYS_PFD3_CLK 24 -#define IMX7D_PLL_SYS_PFD4_CLK 25 -#define IMX7D_PLL_SYS_PFD5_CLK 26 -#define IMX7D_PLL_SYS_PFD6_CLK 27 -#define IMX7D_PLL_SYS_PFD7_CLK 28 -#define IMX7D_PLL_ENET_MAIN 29 -#define IMX7D_PLL_ENET_MAIN_CLK 30 -#define IMX7D_PLL_ENET_MAIN_SRC 31 -#define IMX7D_PLL_ENET_MAIN_BYPASS 32 -#define IMX7D_PLL_ENET_MAIN_500M 33 -#define IMX7D_PLL_ENET_MAIN_250M 34 -#define IMX7D_PLL_ENET_MAIN_125M 35 -#define IMX7D_PLL_ENET_MAIN_100M 36 -#define IMX7D_PLL_ENET_MAIN_50M 37 -#define IMX7D_PLL_ENET_MAIN_40M 38 -#define IMX7D_PLL_ENET_MAIN_25M 39 -#define IMX7D_PLL_ENET_MAIN_500M_CLK 40 -#define IMX7D_PLL_ENET_MAIN_250M_CLK 41 -#define IMX7D_PLL_ENET_MAIN_125M_CLK 42 -#define IMX7D_PLL_ENET_MAIN_100M_CLK 43 -#define IMX7D_PLL_ENET_MAIN_50M_CLK 44 -#define IMX7D_PLL_ENET_MAIN_40M_CLK 45 -#define IMX7D_PLL_ENET_MAIN_25M_CLK 46 -#define IMX7D_PLL_DRAM_MAIN 47 -#define IMX7D_PLL_DRAM_MAIN_CLK 48 -#define IMX7D_PLL_DRAM_MAIN_SRC 49 -#define IMX7D_PLL_DRAM_MAIN_BYPASS 50 -#define IMX7D_PLL_DRAM_MAIN_533M 51 -#define IMX7D_PLL_DRAM_MAIN_533M_CLK 52 -#define IMX7D_PLL_AUDIO_MAIN 53 -#define IMX7D_PLL_AUDIO_MAIN_CLK 54 -#define IMX7D_PLL_AUDIO_MAIN_SRC 55 -#define IMX7D_PLL_AUDIO_MAIN_BYPASS 56 -#define IMX7D_PLL_VIDEO_MAIN_CLK 57 -#define IMX7D_PLL_VIDEO_MAIN 58 -#define IMX7D_PLL_VIDEO_MAIN_SRC 59 -#define IMX7D_PLL_VIDEO_MAIN_BYPASS 60 -#define IMX7D_USB_MAIN_480M_CLK 61 -#define IMX7D_ARM_A7_ROOT_CLK 62 -#define IMX7D_ARM_A7_ROOT_SRC 63 -#define IMX7D_ARM_A7_ROOT_CG 64 -#define IMX7D_ARM_A7_ROOT_DIV 65 -#define IMX7D_ARM_M4_ROOT_CLK 66 -#define IMX7D_ARM_M4_ROOT_SRC 67 -#define IMX7D_ARM_M4_ROOT_CG 68 -#define IMX7D_ARM_M4_ROOT_DIV 69 -#define IMX7D_ARM_M0_ROOT_CLK 70 /* unused */ -#define IMX7D_ARM_M0_ROOT_SRC 71 /* unused */ -#define IMX7D_ARM_M0_ROOT_CG 72 /* unused */ -#define IMX7D_ARM_M0_ROOT_DIV 73 /* unused */ -#define IMX7D_MAIN_AXI_ROOT_CLK 74 -#define IMX7D_MAIN_AXI_ROOT_SRC 75 -#define IMX7D_MAIN_AXI_ROOT_CG 76 -#define IMX7D_MAIN_AXI_ROOT_DIV 77 -#define IMX7D_DISP_AXI_ROOT_CLK 78 -#define IMX7D_DISP_AXI_ROOT_SRC 79 -#define IMX7D_DISP_AXI_ROOT_CG 80 -#define IMX7D_DISP_AXI_ROOT_DIV 81 -#define IMX7D_ENET_AXI_ROOT_CLK 82 -#define IMX7D_ENET_AXI_ROOT_SRC 83 -#define IMX7D_ENET_AXI_ROOT_CG 84 -#define IMX7D_ENET_AXI_ROOT_DIV 85 -#define IMX7D_NAND_USDHC_BUS_ROOT_CLK 86 -#define IMX7D_NAND_USDHC_BUS_ROOT_SRC 87 -#define IMX7D_NAND_USDHC_BUS_ROOT_CG 88 -#define IMX7D_NAND_USDHC_BUS_ROOT_DIV 89 -#define IMX7D_AHB_CHANNEL_ROOT_CLK 90 -#define IMX7D_AHB_CHANNEL_ROOT_SRC 91 -#define IMX7D_AHB_CHANNEL_ROOT_CG 92 -#define IMX7D_AHB_CHANNEL_ROOT_DIV 93 -#define IMX7D_DRAM_PHYM_ROOT_CLK 94 -#define IMX7D_DRAM_PHYM_ROOT_SRC 95 -#define IMX7D_DRAM_PHYM_ROOT_CG 96 -#define IMX7D_DRAM_PHYM_ROOT_DIV 97 -#define IMX7D_DRAM_ROOT_CLK 98 -#define IMX7D_DRAM_ROOT_SRC 99 -#define IMX7D_DRAM_ROOT_CG 100 -#define IMX7D_DRAM_ROOT_DIV 101 -#define IMX7D_DRAM_PHYM_ALT_ROOT_CLK 102 -#define IMX7D_DRAM_PHYM_ALT_ROOT_SRC 103 -#define IMX7D_DRAM_PHYM_ALT_ROOT_CG 104 -#define IMX7D_DRAM_PHYM_ALT_ROOT_DIV 105 -#define IMX7D_DRAM_ALT_ROOT_CLK 106 -#define IMX7D_DRAM_ALT_ROOT_SRC 107 -#define IMX7D_DRAM_ALT_ROOT_CG 108 -#define IMX7D_DRAM_ALT_ROOT_DIV 109 -#define IMX7D_USB_HSIC_ROOT_CLK 110 -#define IMX7D_USB_HSIC_ROOT_SRC 111 -#define IMX7D_USB_HSIC_ROOT_CG 112 -#define IMX7D_USB_HSIC_ROOT_DIV 113 -#define IMX7D_PCIE_CTRL_ROOT_CLK 114 -#define IMX7D_PCIE_CTRL_ROOT_SRC 115 -#define IMX7D_PCIE_CTRL_ROOT_CG 116 -#define IMX7D_PCIE_CTRL_ROOT_DIV 117 -#define IMX7D_PCIE_PHY_ROOT_CLK 118 -#define IMX7D_PCIE_PHY_ROOT_SRC 119 -#define IMX7D_PCIE_PHY_ROOT_CG 120 -#define IMX7D_PCIE_PHY_ROOT_DIV 121 -#define IMX7D_EPDC_PIXEL_ROOT_CLK 122 -#define IMX7D_EPDC_PIXEL_ROOT_SRC 123 -#define IMX7D_EPDC_PIXEL_ROOT_CG 124 -#define IMX7D_EPDC_PIXEL_ROOT_DIV 125 -#define IMX7D_LCDIF_PIXEL_ROOT_CLK 126 -#define IMX7D_LCDIF_PIXEL_ROOT_SRC 127 -#define IMX7D_LCDIF_PIXEL_ROOT_CG 128 -#define IMX7D_LCDIF_PIXEL_ROOT_DIV 129 -#define IMX7D_MIPI_DSI_ROOT_CLK 130 -#define IMX7D_MIPI_DSI_ROOT_SRC 131 -#define IMX7D_MIPI_DSI_ROOT_CG 132 -#define IMX7D_MIPI_DSI_ROOT_DIV 133 -#define IMX7D_MIPI_CSI_ROOT_CLK 134 -#define IMX7D_MIPI_CSI_ROOT_SRC 135 -#define IMX7D_MIPI_CSI_ROOT_CG 136 -#define IMX7D_MIPI_CSI_ROOT_DIV 137 -#define IMX7D_MIPI_DPHY_ROOT_CLK 138 -#define IMX7D_MIPI_DPHY_ROOT_SRC 139 -#define IMX7D_MIPI_DPHY_ROOT_CG 140 -#define IMX7D_MIPI_DPHY_ROOT_DIV 141 -#define IMX7D_SAI1_ROOT_CLK 142 -#define IMX7D_SAI1_ROOT_SRC 143 -#define IMX7D_SAI1_ROOT_CG 144 -#define IMX7D_SAI1_ROOT_DIV 145 -#define IMX7D_SAI2_ROOT_CLK 146 -#define IMX7D_SAI2_ROOT_SRC 147 -#define IMX7D_SAI2_ROOT_CG 148 -#define IMX7D_SAI2_ROOT_DIV 149 -#define IMX7D_SAI3_ROOT_CLK 150 -#define IMX7D_SAI3_ROOT_SRC 151 -#define IMX7D_SAI3_ROOT_CG 152 -#define IMX7D_SAI3_ROOT_DIV 153 -#define IMX7D_SPDIF_ROOT_CLK 154 -#define IMX7D_SPDIF_ROOT_SRC 155 -#define IMX7D_SPDIF_ROOT_CG 156 -#define IMX7D_SPDIF_ROOT_DIV 157 -#define IMX7D_ENET1_IPG_ROOT_CLK 158 -#define IMX7D_ENET1_REF_ROOT_SRC 159 -#define IMX7D_ENET1_REF_ROOT_CG 160 -#define IMX7D_ENET1_REF_ROOT_DIV 161 -#define IMX7D_ENET1_TIME_ROOT_CLK 162 -#define IMX7D_ENET1_TIME_ROOT_SRC 163 -#define IMX7D_ENET1_TIME_ROOT_CG 164 -#define IMX7D_ENET1_TIME_ROOT_DIV 165 -#define IMX7D_ENET2_IPG_ROOT_CLK 166 -#define IMX7D_ENET2_REF_ROOT_SRC 167 -#define IMX7D_ENET2_REF_ROOT_CG 168 -#define IMX7D_ENET2_REF_ROOT_DIV 169 -#define IMX7D_ENET2_TIME_ROOT_CLK 170 -#define IMX7D_ENET2_TIME_ROOT_SRC 171 -#define IMX7D_ENET2_TIME_ROOT_CG 172 -#define IMX7D_ENET2_TIME_ROOT_DIV 173 -#define IMX7D_ENET_PHY_REF_ROOT_CLK 174 -#define IMX7D_ENET_PHY_REF_ROOT_SRC 175 -#define IMX7D_ENET_PHY_REF_ROOT_CG 176 -#define IMX7D_ENET_PHY_REF_ROOT_DIV 177 -#define IMX7D_EIM_ROOT_CLK 178 -#define IMX7D_EIM_ROOT_SRC 179 -#define IMX7D_EIM_ROOT_CG 180 -#define IMX7D_EIM_ROOT_DIV 181 -#define IMX7D_NAND_ROOT_CLK 182 -#define IMX7D_NAND_ROOT_SRC 183 -#define IMX7D_NAND_ROOT_CG 184 -#define IMX7D_NAND_ROOT_DIV 185 -#define IMX7D_QSPI_ROOT_CLK 186 -#define IMX7D_QSPI_ROOT_SRC 187 -#define IMX7D_QSPI_ROOT_CG 188 -#define IMX7D_QSPI_ROOT_DIV 189 -#define IMX7D_USDHC1_ROOT_CLK 190 -#define IMX7D_USDHC1_ROOT_SRC 191 -#define IMX7D_USDHC1_ROOT_CG 192 -#define IMX7D_USDHC1_ROOT_DIV 193 -#define IMX7D_USDHC2_ROOT_CLK 194 -#define IMX7D_USDHC2_ROOT_SRC 195 -#define IMX7D_USDHC2_ROOT_CG 196 -#define IMX7D_USDHC2_ROOT_DIV 197 -#define IMX7D_USDHC3_ROOT_CLK 198 -#define IMX7D_USDHC3_ROOT_SRC 199 -#define IMX7D_USDHC3_ROOT_CG 200 -#define IMX7D_USDHC3_ROOT_DIV 201 -#define IMX7D_CAN1_ROOT_CLK 202 -#define IMX7D_CAN1_ROOT_SRC 203 -#define IMX7D_CAN1_ROOT_CG 204 -#define IMX7D_CAN1_ROOT_DIV 205 -#define IMX7D_CAN2_ROOT_CLK 206 -#define IMX7D_CAN2_ROOT_SRC 207 -#define IMX7D_CAN2_ROOT_CG 208 -#define IMX7D_CAN2_ROOT_DIV 209 -#define IMX7D_I2C1_ROOT_CLK 210 -#define IMX7D_I2C1_ROOT_SRC 211 -#define IMX7D_I2C1_ROOT_CG 212 -#define IMX7D_I2C1_ROOT_DIV 213 -#define IMX7D_I2C2_ROOT_CLK 214 -#define IMX7D_I2C2_ROOT_SRC 215 -#define IMX7D_I2C2_ROOT_CG 216 -#define IMX7D_I2C2_ROOT_DIV 217 -#define IMX7D_I2C3_ROOT_CLK 218 -#define IMX7D_I2C3_ROOT_SRC 219 -#define IMX7D_I2C3_ROOT_CG 220 -#define IMX7D_I2C3_ROOT_DIV 221 -#define IMX7D_I2C4_ROOT_CLK 222 -#define IMX7D_I2C4_ROOT_SRC 223 -#define IMX7D_I2C4_ROOT_CG 224 -#define IMX7D_I2C4_ROOT_DIV 225 -#define IMX7D_UART1_ROOT_CLK 226 -#define IMX7D_UART1_ROOT_SRC 227 -#define IMX7D_UART1_ROOT_CG 228 -#define IMX7D_UART1_ROOT_DIV 229 -#define IMX7D_UART2_ROOT_CLK 230 -#define IMX7D_UART2_ROOT_SRC 231 -#define IMX7D_UART2_ROOT_CG 232 -#define IMX7D_UART2_ROOT_DIV 233 -#define IMX7D_UART3_ROOT_CLK 234 -#define IMX7D_UART3_ROOT_SRC 235 -#define IMX7D_UART3_ROOT_CG 236 -#define IMX7D_UART3_ROOT_DIV 237 -#define IMX7D_UART4_ROOT_CLK 238 -#define IMX7D_UART4_ROOT_SRC 239 -#define IMX7D_UART4_ROOT_CG 240 -#define IMX7D_UART4_ROOT_DIV 241 -#define IMX7D_UART5_ROOT_CLK 242 -#define IMX7D_UART5_ROOT_SRC 243 -#define IMX7D_UART5_ROOT_CG 244 -#define IMX7D_UART5_ROOT_DIV 245 -#define IMX7D_UART6_ROOT_CLK 246 -#define IMX7D_UART6_ROOT_SRC 247 -#define IMX7D_UART6_ROOT_CG 248 -#define IMX7D_UART6_ROOT_DIV 249 -#define IMX7D_UART7_ROOT_CLK 250 -#define IMX7D_UART7_ROOT_SRC 251 -#define IMX7D_UART7_ROOT_CG 252 -#define IMX7D_UART7_ROOT_DIV 253 -#define IMX7D_ECSPI1_ROOT_CLK 254 -#define IMX7D_ECSPI1_ROOT_SRC 255 -#define IMX7D_ECSPI1_ROOT_CG 256 -#define IMX7D_ECSPI1_ROOT_DIV 257 -#define IMX7D_ECSPI2_ROOT_CLK 258 -#define IMX7D_ECSPI2_ROOT_SRC 259 -#define IMX7D_ECSPI2_ROOT_CG 260 -#define IMX7D_ECSPI2_ROOT_DIV 261 -#define IMX7D_ECSPI3_ROOT_CLK 262 -#define IMX7D_ECSPI3_ROOT_SRC 263 -#define IMX7D_ECSPI3_ROOT_CG 264 -#define IMX7D_ECSPI3_ROOT_DIV 265 -#define IMX7D_ECSPI4_ROOT_CLK 266 -#define IMX7D_ECSPI4_ROOT_SRC 267 -#define IMX7D_ECSPI4_ROOT_CG 268 -#define IMX7D_ECSPI4_ROOT_DIV 269 -#define IMX7D_PWM1_ROOT_CLK 270 -#define IMX7D_PWM1_ROOT_SRC 271 -#define IMX7D_PWM1_ROOT_CG 272 -#define IMX7D_PWM1_ROOT_DIV 273 -#define IMX7D_PWM2_ROOT_CLK 274 -#define IMX7D_PWM2_ROOT_SRC 275 -#define IMX7D_PWM2_ROOT_CG 276 -#define IMX7D_PWM2_ROOT_DIV 277 -#define IMX7D_PWM3_ROOT_CLK 278 -#define IMX7D_PWM3_ROOT_SRC 279 -#define IMX7D_PWM3_ROOT_CG 280 -#define IMX7D_PWM3_ROOT_DIV 281 -#define IMX7D_PWM4_ROOT_CLK 282 -#define IMX7D_PWM4_ROOT_SRC 283 -#define IMX7D_PWM4_ROOT_CG 284 -#define IMX7D_PWM4_ROOT_DIV 285 -#define IMX7D_FLEXTIMER1_ROOT_CLK 286 -#define IMX7D_FLEXTIMER1_ROOT_SRC 287 -#define IMX7D_FLEXTIMER1_ROOT_CG 288 -#define IMX7D_FLEXTIMER1_ROOT_DIV 289 -#define IMX7D_FLEXTIMER2_ROOT_CLK 290 -#define IMX7D_FLEXTIMER2_ROOT_SRC 291 -#define IMX7D_FLEXTIMER2_ROOT_CG 292 -#define IMX7D_FLEXTIMER2_ROOT_DIV 293 -#define IMX7D_SIM1_ROOT_CLK 294 -#define IMX7D_SIM1_ROOT_SRC 295 -#define IMX7D_SIM1_ROOT_CG 296 -#define IMX7D_SIM1_ROOT_DIV 297 -#define IMX7D_SIM2_ROOT_CLK 298 -#define IMX7D_SIM2_ROOT_SRC 299 -#define IMX7D_SIM2_ROOT_CG 300 -#define IMX7D_SIM2_ROOT_DIV 301 -#define IMX7D_GPT1_ROOT_CLK 302 -#define IMX7D_GPT1_ROOT_SRC 303 -#define IMX7D_GPT1_ROOT_CG 304 -#define IMX7D_GPT1_ROOT_DIV 305 -#define IMX7D_GPT2_ROOT_CLK 306 -#define IMX7D_GPT2_ROOT_SRC 307 -#define IMX7D_GPT2_ROOT_CG 308 -#define IMX7D_GPT2_ROOT_DIV 309 -#define IMX7D_GPT3_ROOT_CLK 310 -#define IMX7D_GPT3_ROOT_SRC 311 -#define IMX7D_GPT3_ROOT_CG 312 -#define IMX7D_GPT3_ROOT_DIV 313 -#define IMX7D_GPT4_ROOT_CLK 314 -#define IMX7D_GPT4_ROOT_SRC 315 -#define IMX7D_GPT4_ROOT_CG 316 -#define IMX7D_GPT4_ROOT_DIV 317 -#define IMX7D_TRACE_ROOT_CLK 318 -#define IMX7D_TRACE_ROOT_SRC 319 -#define IMX7D_TRACE_ROOT_CG 320 -#define IMX7D_TRACE_ROOT_DIV 321 -#define IMX7D_WDOG1_ROOT_CLK 322 -#define IMX7D_WDOG_ROOT_SRC 323 -#define IMX7D_WDOG_ROOT_CG 324 -#define IMX7D_WDOG_ROOT_DIV 325 -#define IMX7D_CSI_MCLK_ROOT_CLK 326 -#define IMX7D_CSI_MCLK_ROOT_SRC 327 -#define IMX7D_CSI_MCLK_ROOT_CG 328 -#define IMX7D_CSI_MCLK_ROOT_DIV 329 -#define IMX7D_AUDIO_MCLK_ROOT_CLK 330 -#define IMX7D_AUDIO_MCLK_ROOT_SRC 331 -#define IMX7D_AUDIO_MCLK_ROOT_CG 332 -#define IMX7D_AUDIO_MCLK_ROOT_DIV 333 -#define IMX7D_WRCLK_ROOT_CLK 334 -#define IMX7D_WRCLK_ROOT_SRC 335 -#define IMX7D_WRCLK_ROOT_CG 336 -#define IMX7D_WRCLK_ROOT_DIV 337 -#define IMX7D_CLKO1_ROOT_SRC 338 -#define IMX7D_CLKO1_ROOT_CG 339 -#define IMX7D_CLKO1_ROOT_DIV 340 -#define IMX7D_CLKO2_ROOT_SRC 341 -#define IMX7D_CLKO2_ROOT_CG 342 -#define IMX7D_CLKO2_ROOT_DIV 343 -#define IMX7D_MAIN_AXI_ROOT_PRE_DIV 344 -#define IMX7D_DISP_AXI_ROOT_PRE_DIV 345 -#define IMX7D_ENET_AXI_ROOT_PRE_DIV 346 -#define IMX7D_NAND_USDHC_BUS_ROOT_PRE_DIV 347 -#define IMX7D_AHB_CHANNEL_ROOT_PRE_DIV 348 -#define IMX7D_USB_HSIC_ROOT_PRE_DIV 349 -#define IMX7D_PCIE_CTRL_ROOT_PRE_DIV 350 -#define IMX7D_PCIE_PHY_ROOT_PRE_DIV 351 -#define IMX7D_EPDC_PIXEL_ROOT_PRE_DIV 352 -#define IMX7D_LCDIF_PIXEL_ROOT_PRE_DIV 353 -#define IMX7D_MIPI_DSI_ROOT_PRE_DIV 354 -#define IMX7D_MIPI_CSI_ROOT_PRE_DIV 355 -#define IMX7D_MIPI_DPHY_ROOT_PRE_DIV 356 -#define IMX7D_SAI1_ROOT_PRE_DIV 357 -#define IMX7D_SAI2_ROOT_PRE_DIV 358 -#define IMX7D_SAI3_ROOT_PRE_DIV 359 -#define IMX7D_SPDIF_ROOT_PRE_DIV 360 -#define IMX7D_ENET1_REF_ROOT_PRE_DIV 361 -#define IMX7D_ENET1_TIME_ROOT_PRE_DIV 362 -#define IMX7D_ENET2_REF_ROOT_PRE_DIV 363 -#define IMX7D_ENET2_TIME_ROOT_PRE_DIV 364 -#define IMX7D_ENET_PHY_REF_ROOT_PRE_DIV 365 -#define IMX7D_EIM_ROOT_PRE_DIV 366 -#define IMX7D_NAND_ROOT_PRE_DIV 367 -#define IMX7D_QSPI_ROOT_PRE_DIV 368 -#define IMX7D_USDHC1_ROOT_PRE_DIV 369 -#define IMX7D_USDHC2_ROOT_PRE_DIV 370 -#define IMX7D_USDHC3_ROOT_PRE_DIV 371 -#define IMX7D_CAN1_ROOT_PRE_DIV 372 -#define IMX7D_CAN2_ROOT_PRE_DIV 373 -#define IMX7D_I2C1_ROOT_PRE_DIV 374 -#define IMX7D_I2C2_ROOT_PRE_DIV 375 -#define IMX7D_I2C3_ROOT_PRE_DIV 376 -#define IMX7D_I2C4_ROOT_PRE_DIV 377 -#define IMX7D_UART1_ROOT_PRE_DIV 378 -#define IMX7D_UART2_ROOT_PRE_DIV 379 -#define IMX7D_UART3_ROOT_PRE_DIV 380 -#define IMX7D_UART4_ROOT_PRE_DIV 381 -#define IMX7D_UART5_ROOT_PRE_DIV 382 -#define IMX7D_UART6_ROOT_PRE_DIV 383 -#define IMX7D_UART7_ROOT_PRE_DIV 384 -#define IMX7D_ECSPI1_ROOT_PRE_DIV 385 -#define IMX7D_ECSPI2_ROOT_PRE_DIV 386 -#define IMX7D_ECSPI3_ROOT_PRE_DIV 387 -#define IMX7D_ECSPI4_ROOT_PRE_DIV 388 -#define IMX7D_PWM1_ROOT_PRE_DIV 389 -#define IMX7D_PWM2_ROOT_PRE_DIV 390 -#define IMX7D_PWM3_ROOT_PRE_DIV 391 -#define IMX7D_PWM4_ROOT_PRE_DIV 392 -#define IMX7D_FLEXTIMER1_ROOT_PRE_DIV 393 -#define IMX7D_FLEXTIMER2_ROOT_PRE_DIV 394 -#define IMX7D_SIM1_ROOT_PRE_DIV 395 -#define IMX7D_SIM2_ROOT_PRE_DIV 396 -#define IMX7D_GPT1_ROOT_PRE_DIV 397 -#define IMX7D_GPT2_ROOT_PRE_DIV 398 -#define IMX7D_GPT3_ROOT_PRE_DIV 399 -#define IMX7D_GPT4_ROOT_PRE_DIV 400 -#define IMX7D_TRACE_ROOT_PRE_DIV 401 -#define IMX7D_WDOG_ROOT_PRE_DIV 402 -#define IMX7D_CSI_MCLK_ROOT_PRE_DIV 403 -#define IMX7D_AUDIO_MCLK_ROOT_PRE_DIV 404 -#define IMX7D_WRCLK_ROOT_PRE_DIV 405 -#define IMX7D_CLKO1_ROOT_PRE_DIV 406 -#define IMX7D_CLKO2_ROOT_PRE_DIV 407 -#define IMX7D_DRAM_PHYM_ALT_ROOT_PRE_DIV 408 -#define IMX7D_DRAM_ALT_ROOT_PRE_DIV 409 -#define IMX7D_LVDS1_IN_CLK 410 -#define IMX7D_LVDS1_OUT_SEL 411 -#define IMX7D_LVDS1_OUT_CLK 412 -#define IMX7D_CLK_DUMMY 413 -#define IMX7D_GPT_3M_CLK 414 -#define IMX7D_OCRAM_CLK 415 -#define IMX7D_OCRAM_S_CLK 416 -#define IMX7D_WDOG2_ROOT_CLK 417 -#define IMX7D_WDOG3_ROOT_CLK 418 -#define IMX7D_WDOG4_ROOT_CLK 419 -#define IMX7D_SDMA_CORE_CLK 420 -#define IMX7D_USB1_MAIN_480M_CLK 421 -#define IMX7D_USB_CTRL_CLK 422 -#define IMX7D_USB_PHY1_CLK 423 -#define IMX7D_USB_PHY2_CLK 424 -#define IMX7D_IPG_ROOT_CLK 425 -#define IMX7D_SAI1_IPG_CLK 426 -#define IMX7D_SAI2_IPG_CLK 427 -#define IMX7D_SAI3_IPG_CLK 428 -#define IMX7D_PLL_AUDIO_TEST_DIV 429 -#define IMX7D_PLL_AUDIO_POST_DIV 430 -#define IMX7D_PLL_VIDEO_TEST_DIV 431 -#define IMX7D_PLL_VIDEO_POST_DIV 432 -#define IMX7D_MU_ROOT_CLK 433 -#define IMX7D_SEMA4_HS_ROOT_CLK 434 -#define IMX7D_PLL_DRAM_TEST_DIV 435 -#define IMX7D_ADC_ROOT_CLK 436 -#define IMX7D_CLK_ARM 437 -#define IMX7D_CKIL 438 -#define IMX7D_OCOTP_CLK 439 -#define IMX7D_NAND_RAWNAND_CLK 440 -#define IMX7D_NAND_USDHC_BUS_RAWNAND_CLK 441 -#define IMX7D_SNVS_CLK 442 -#define IMX7D_CAAM_CLK 443 -#define IMX7D_KPP_ROOT_CLK 444 -#define IMX7D_CLK_END 445 -#endif /* __DT_BINDINGS_CLOCK_IMX7D_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/imx7ulp-clock.h b/sys/gnu/dts/include/dt-bindings/clock/imx7ulp-clock.h deleted file mode 100644 index 38145bdcd97..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/imx7ulp-clock.h +++ /dev/null @@ -1,116 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2016 Freescale Semiconductor, Inc. - * Copyright 2017~2018 NXP - * - */ - -#ifndef __DT_BINDINGS_CLOCK_IMX7ULP_H -#define __DT_BINDINGS_CLOCK_IMX7ULP_H - -/* SCG1 */ - -#define IMX7ULP_CLK_DUMMY 0 -#define IMX7ULP_CLK_ROSC 1 -#define IMX7ULP_CLK_SOSC 2 -#define IMX7ULP_CLK_FIRC 3 -#define IMX7ULP_CLK_SPLL_PRE_SEL 4 -#define IMX7ULP_CLK_SPLL_PRE_DIV 5 -#define IMX7ULP_CLK_SPLL 6 -#define IMX7ULP_CLK_SPLL_POST_DIV1 7 -#define IMX7ULP_CLK_SPLL_POST_DIV2 8 -#define IMX7ULP_CLK_SPLL_PFD0 9 -#define IMX7ULP_CLK_SPLL_PFD1 10 -#define IMX7ULP_CLK_SPLL_PFD2 11 -#define IMX7ULP_CLK_SPLL_PFD3 12 -#define IMX7ULP_CLK_SPLL_PFD_SEL 13 -#define IMX7ULP_CLK_SPLL_SEL 14 -#define IMX7ULP_CLK_APLL_PRE_SEL 15 -#define IMX7ULP_CLK_APLL_PRE_DIV 16 -#define IMX7ULP_CLK_APLL 17 -#define IMX7ULP_CLK_APLL_POST_DIV1 18 -#define IMX7ULP_CLK_APLL_POST_DIV2 19 -#define IMX7ULP_CLK_APLL_PFD0 20 -#define IMX7ULP_CLK_APLL_PFD1 21 -#define IMX7ULP_CLK_APLL_PFD2 22 -#define IMX7ULP_CLK_APLL_PFD3 23 -#define IMX7ULP_CLK_APLL_PFD_SEL 24 -#define IMX7ULP_CLK_APLL_SEL 25 -#define IMX7ULP_CLK_UPLL 26 -#define IMX7ULP_CLK_SYS_SEL 27 -#define IMX7ULP_CLK_CORE_DIV 28 -#define IMX7ULP_CLK_BUS_DIV 29 -#define IMX7ULP_CLK_PLAT_DIV 30 -#define IMX7ULP_CLK_DDR_SEL 31 -#define IMX7ULP_CLK_DDR_DIV 32 -#define IMX7ULP_CLK_NIC_SEL 33 -#define IMX7ULP_CLK_NIC0_DIV 34 -#define IMX7ULP_CLK_GPU_DIV 35 -#define IMX7ULP_CLK_NIC1_DIV 36 -#define IMX7ULP_CLK_NIC1_BUS_DIV 37 -#define IMX7ULP_CLK_NIC1_EXT_DIV 38 -/* IMX7ULP_CLK_MIPI_PLL is unsupported and shouldn't be used in DT */ -#define IMX7ULP_CLK_MIPI_PLL 39 -#define IMX7ULP_CLK_SIRC 40 -#define IMX7ULP_CLK_SOSC_BUS_CLK 41 -#define IMX7ULP_CLK_FIRC_BUS_CLK 42 -#define IMX7ULP_CLK_SPLL_BUS_CLK 43 -#define IMX7ULP_CLK_HSRUN_SYS_SEL 44 -#define IMX7ULP_CLK_HSRUN_CORE_DIV 45 - -#define IMX7ULP_CLK_SCG1_END 46 - -/* PCC2 */ -#define IMX7ULP_CLK_DMA1 0 -#define IMX7ULP_CLK_RGPIO2P1 1 -#define IMX7ULP_CLK_FLEXBUS 2 -#define IMX7ULP_CLK_SEMA42_1 3 -#define IMX7ULP_CLK_DMA_MUX1 4 -#define IMX7ULP_CLK_CAAM 6 -#define IMX7ULP_CLK_LPTPM4 7 -#define IMX7ULP_CLK_LPTPM5 8 -#define IMX7ULP_CLK_LPIT1 9 -#define IMX7ULP_CLK_LPSPI2 10 -#define IMX7ULP_CLK_LPSPI3 11 -#define IMX7ULP_CLK_LPI2C4 12 -#define IMX7ULP_CLK_LPI2C5 13 -#define IMX7ULP_CLK_LPUART4 14 -#define IMX7ULP_CLK_LPUART5 15 -#define IMX7ULP_CLK_FLEXIO1 16 -#define IMX7ULP_CLK_USB0 17 -#define IMX7ULP_CLK_USB1 18 -#define IMX7ULP_CLK_USB_PHY 19 -#define IMX7ULP_CLK_USB_PL301 20 -#define IMX7ULP_CLK_USDHC0 21 -#define IMX7ULP_CLK_USDHC1 22 -#define IMX7ULP_CLK_WDG1 23 -#define IMX7ULP_CLK_WDG2 24 - -#define IMX7ULP_CLK_PCC2_END 25 - -/* PCC3 */ -#define IMX7ULP_CLK_LPTPM6 0 -#define IMX7ULP_CLK_LPTPM7 1 -#define IMX7ULP_CLK_LPI2C6 2 -#define IMX7ULP_CLK_LPI2C7 3 -#define IMX7ULP_CLK_LPUART6 4 -#define IMX7ULP_CLK_LPUART7 5 -#define IMX7ULP_CLK_VIU 6 -#define IMX7ULP_CLK_DSI 7 -#define IMX7ULP_CLK_LCDIF 8 -#define IMX7ULP_CLK_MMDC 9 -#define IMX7ULP_CLK_PCTLC 10 -#define IMX7ULP_CLK_PCTLD 11 -#define IMX7ULP_CLK_PCTLE 12 -#define IMX7ULP_CLK_PCTLF 13 -#define IMX7ULP_CLK_GPU3D 14 -#define IMX7ULP_CLK_GPU2D 15 - -#define IMX7ULP_CLK_PCC3_END 16 - -/* SMC1 */ -#define IMX7ULP_CLK_ARM 0 - -#define IMX7ULP_CLK_SMC1_END 1 - -#endif /* __DT_BINDINGS_CLOCK_IMX7ULP_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/imx8-clock.h b/sys/gnu/dts/include/dt-bindings/clock/imx8-clock.h deleted file mode 100644 index 673a8c66234..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/imx8-clock.h +++ /dev/null @@ -1,293 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2018 NXP - * Dong Aisheng - */ - -#ifndef __DT_BINDINGS_CLOCK_IMX_H -#define __DT_BINDINGS_CLOCK_IMX_H - -/* SCU Clocks */ - -#define IMX_CLK_DUMMY 0 - -/* CPU */ -#define IMX_A35_CLK 1 - -/* LSIO SS */ -#define IMX_LSIO_MEM_CLK 2 -#define IMX_LSIO_BUS_CLK 3 -#define IMX_LSIO_PWM0_CLK 10 -#define IMX_LSIO_PWM1_CLK 11 -#define IMX_LSIO_PWM2_CLK 12 -#define IMX_LSIO_PWM3_CLK 13 -#define IMX_LSIO_PWM4_CLK 14 -#define IMX_LSIO_PWM5_CLK 15 -#define IMX_LSIO_PWM6_CLK 16 -#define IMX_LSIO_PWM7_CLK 17 -#define IMX_LSIO_GPT0_CLK 18 -#define IMX_LSIO_GPT1_CLK 19 -#define IMX_LSIO_GPT2_CLK 20 -#define IMX_LSIO_GPT3_CLK 21 -#define IMX_LSIO_GPT4_CLK 22 -#define IMX_LSIO_FSPI0_CLK 23 -#define IMX_LSIO_FSPI1_CLK 24 - -/* Connectivity SS */ -#define IMX_CONN_AXI_CLK_ROOT 30 -#define IMX_CONN_AHB_CLK_ROOT 31 -#define IMX_CONN_IPG_CLK_ROOT 32 -#define IMX_CONN_SDHC0_CLK 40 -#define IMX_CONN_SDHC1_CLK 41 -#define IMX_CONN_SDHC2_CLK 42 -#define IMX_CONN_ENET0_ROOT_CLK 43 -#define IMX_CONN_ENET0_BYPASS_CLK 44 -#define IMX_CONN_ENET0_RGMII_CLK 45 -#define IMX_CONN_ENET1_ROOT_CLK 46 -#define IMX_CONN_ENET1_BYPASS_CLK 47 -#define IMX_CONN_ENET1_RGMII_CLK 48 -#define IMX_CONN_GPMI_BCH_IO_CLK 49 -#define IMX_CONN_GPMI_BCH_CLK 50 -#define IMX_CONN_USB2_ACLK 51 -#define IMX_CONN_USB2_BUS_CLK 52 -#define IMX_CONN_USB2_LPM_CLK 53 - -/* HSIO SS */ -#define IMX_HSIO_AXI_CLK 60 -#define IMX_HSIO_PER_CLK 61 - -/* Display controller SS */ -#define IMX_DC_AXI_EXT_CLK 70 -#define IMX_DC_AXI_INT_CLK 71 -#define IMX_DC_CFG_CLK 72 -#define IMX_DC0_PLL0_CLK 80 -#define IMX_DC0_PLL1_CLK 81 -#define IMX_DC0_DISP0_CLK 82 -#define IMX_DC0_DISP1_CLK 83 - -/* MIPI-LVDS SS */ -#define IMX_MIPI_IPG_CLK 90 -#define IMX_MIPI0_PIXEL_CLK 100 -#define IMX_MIPI0_BYPASS_CLK 101 -#define IMX_MIPI0_LVDS_PIXEL_CLK 102 -#define IMX_MIPI0_LVDS_BYPASS_CLK 103 -#define IMX_MIPI0_LVDS_PHY_CLK 104 -#define IMX_MIPI0_I2C0_CLK 105 -#define IMX_MIPI0_I2C1_CLK 106 -#define IMX_MIPI0_PWM0_CLK 107 -#define IMX_MIPI1_PIXEL_CLK 108 -#define IMX_MIPI1_BYPASS_CLK 109 -#define IMX_MIPI1_LVDS_PIXEL_CLK 110 -#define IMX_MIPI1_LVDS_BYPASS_CLK 111 -#define IMX_MIPI1_LVDS_PHY_CLK 112 -#define IMX_MIPI1_I2C0_CLK 113 -#define IMX_MIPI1_I2C1_CLK 114 -#define IMX_MIPI1_PWM0_CLK 115 - -/* IMG SS */ -#define IMX_IMG_AXI_CLK 120 -#define IMX_IMG_IPG_CLK 121 -#define IMX_IMG_PXL_CLK 122 - -/* MIPI-CSI SS */ -#define IMX_CSI0_CORE_CLK 130 -#define IMX_CSI0_ESC_CLK 131 -#define IMX_CSI0_PWM0_CLK 132 -#define IMX_CSI0_I2C0_CLK 133 - -/* PARALLER CSI SS */ -#define IMX_PARALLEL_CSI_DPLL_CLK 140 -#define IMX_PARALLEL_CSI_PIXEL_CLK 141 -#define IMX_PARALLEL_CSI_MCLK_CLK 142 - -/* VPU SS */ -#define IMX_VPU_ENC_CLK 150 -#define IMX_VPU_DEC_CLK 151 - -/* GPU SS */ -#define IMX_GPU0_CORE_CLK 160 -#define IMX_GPU0_SHADER_CLK 161 - -/* ADMA SS */ -#define IMX_ADMA_IPG_CLK_ROOT 165 -#define IMX_ADMA_UART0_CLK 170 -#define IMX_ADMA_UART1_CLK 171 -#define IMX_ADMA_UART2_CLK 172 -#define IMX_ADMA_UART3_CLK 173 -#define IMX_ADMA_SPI0_CLK 174 -#define IMX_ADMA_SPI1_CLK 175 -#define IMX_ADMA_SPI2_CLK 176 -#define IMX_ADMA_SPI3_CLK 177 -#define IMX_ADMA_CAN0_CLK 178 -#define IMX_ADMA_CAN1_CLK 179 -#define IMX_ADMA_CAN2_CLK 180 -#define IMX_ADMA_I2C0_CLK 181 -#define IMX_ADMA_I2C1_CLK 182 -#define IMX_ADMA_I2C2_CLK 183 -#define IMX_ADMA_I2C3_CLK 184 -#define IMX_ADMA_FTM0_CLK 185 -#define IMX_ADMA_FTM1_CLK 186 -#define IMX_ADMA_ADC0_CLK 187 -#define IMX_ADMA_PWM_CLK 188 -#define IMX_ADMA_LCD_CLK 189 - -#define IMX_SCU_CLK_END 190 - -/* LPCG clocks */ - -/* LSIO SS LPCG */ -#define IMX_LSIO_LPCG_PWM0_IPG_CLK 0 -#define IMX_LSIO_LPCG_PWM0_IPG_S_CLK 1 -#define IMX_LSIO_LPCG_PWM0_IPG_HF_CLK 2 -#define IMX_LSIO_LPCG_PWM0_IPG_SLV_CLK 3 -#define IMX_LSIO_LPCG_PWM0_IPG_MSTR_CLK 4 -#define IMX_LSIO_LPCG_PWM1_IPG_CLK 5 -#define IMX_LSIO_LPCG_PWM1_IPG_S_CLK 6 -#define IMX_LSIO_LPCG_PWM1_IPG_HF_CLK 7 -#define IMX_LSIO_LPCG_PWM1_IPG_SLV_CLK 8 -#define IMX_LSIO_LPCG_PWM1_IPG_MSTR_CLK 9 -#define IMX_LSIO_LPCG_PWM2_IPG_CLK 10 -#define IMX_LSIO_LPCG_PWM2_IPG_S_CLK 11 -#define IMX_LSIO_LPCG_PWM2_IPG_HF_CLK 12 -#define IMX_LSIO_LPCG_PWM2_IPG_SLV_CLK 13 -#define IMX_LSIO_LPCG_PWM2_IPG_MSTR_CLK 14 -#define IMX_LSIO_LPCG_PWM3_IPG_CLK 15 -#define IMX_LSIO_LPCG_PWM3_IPG_S_CLK 16 -#define IMX_LSIO_LPCG_PWM3_IPG_HF_CLK 17 -#define IMX_LSIO_LPCG_PWM3_IPG_SLV_CLK 18 -#define IMX_LSIO_LPCG_PWM3_IPG_MSTR_CLK 19 -#define IMX_LSIO_LPCG_PWM4_IPG_CLK 20 -#define IMX_LSIO_LPCG_PWM4_IPG_S_CLK 21 -#define IMX_LSIO_LPCG_PWM4_IPG_HF_CLK 22 -#define IMX_LSIO_LPCG_PWM4_IPG_SLV_CLK 23 -#define IMX_LSIO_LPCG_PWM4_IPG_MSTR_CLK 24 -#define IMX_LSIO_LPCG_PWM5_IPG_CLK 25 -#define IMX_LSIO_LPCG_PWM5_IPG_S_CLK 26 -#define IMX_LSIO_LPCG_PWM5_IPG_HF_CLK 27 -#define IMX_LSIO_LPCG_PWM5_IPG_SLV_CLK 28 -#define IMX_LSIO_LPCG_PWM5_IPG_MSTR_CLK 29 -#define IMX_LSIO_LPCG_PWM6_IPG_CLK 30 -#define IMX_LSIO_LPCG_PWM6_IPG_S_CLK 31 -#define IMX_LSIO_LPCG_PWM6_IPG_HF_CLK 32 -#define IMX_LSIO_LPCG_PWM6_IPG_SLV_CLK 33 -#define IMX_LSIO_LPCG_PWM6_IPG_MSTR_CLK 34 -#define IMX_LSIO_LPCG_PWM7_IPG_CLK 35 -#define IMX_LSIO_LPCG_PWM7_IPG_S_CLK 36 -#define IMX_LSIO_LPCG_PWM7_IPG_HF_CLK 37 -#define IMX_LSIO_LPCG_PWM7_IPG_SLV_CLK 38 -#define IMX_LSIO_LPCG_PWM7_IPG_MSTR_CLK 39 -#define IMX_LSIO_LPCG_GPT0_IPG_CLK 40 -#define IMX_LSIO_LPCG_GPT0_IPG_S_CLK 41 -#define IMX_LSIO_LPCG_GPT0_IPG_HF_CLK 42 -#define IMX_LSIO_LPCG_GPT0_IPG_SLV_CLK 43 -#define IMX_LSIO_LPCG_GPT0_IPG_MSTR_CLK 44 -#define IMX_LSIO_LPCG_GPT1_IPG_CLK 45 -#define IMX_LSIO_LPCG_GPT1_IPG_S_CLK 46 -#define IMX_LSIO_LPCG_GPT1_IPG_HF_CLK 47 -#define IMX_LSIO_LPCG_GPT1_IPG_SLV_CLK 48 -#define IMX_LSIO_LPCG_GPT1_IPG_MSTR_CLK 49 -#define IMX_LSIO_LPCG_GPT2_IPG_CLK 50 -#define IMX_LSIO_LPCG_GPT2_IPG_S_CLK 51 -#define IMX_LSIO_LPCG_GPT2_IPG_HF_CLK 52 -#define IMX_LSIO_LPCG_GPT2_IPG_SLV_CLK 53 -#define IMX_LSIO_LPCG_GPT2_IPG_MSTR_CLK 54 -#define IMX_LSIO_LPCG_GPT3_IPG_CLK 55 -#define IMX_LSIO_LPCG_GPT3_IPG_S_CLK 56 -#define IMX_LSIO_LPCG_GPT3_IPG_HF_CLK 57 -#define IMX_LSIO_LPCG_GPT3_IPG_SLV_CLK 58 -#define IMX_LSIO_LPCG_GPT3_IPG_MSTR_CLK 59 -#define IMX_LSIO_LPCG_GPT4_IPG_CLK 60 -#define IMX_LSIO_LPCG_GPT4_IPG_S_CLK 61 -#define IMX_LSIO_LPCG_GPT4_IPG_HF_CLK 62 -#define IMX_LSIO_LPCG_GPT4_IPG_SLV_CLK 63 -#define IMX_LSIO_LPCG_GPT4_IPG_MSTR_CLK 64 -#define IMX_LSIO_LPCG_FSPI0_HCLK 65 -#define IMX_LSIO_LPCG_FSPI0_IPG_CLK 66 -#define IMX_LSIO_LPCG_FSPI0_IPG_S_CLK 67 -#define IMX_LSIO_LPCG_FSPI0_IPG_SFCK 68 -#define IMX_LSIO_LPCG_FSPI1_HCLK 69 -#define IMX_LSIO_LPCG_FSPI1_IPG_CLK 70 -#define IMX_LSIO_LPCG_FSPI1_IPG_S_CLK 71 -#define IMX_LSIO_LPCG_FSPI1_IPG_SFCK 72 - -#define IMX_LSIO_LPCG_CLK_END 73 - -/* Connectivity SS LPCG */ -#define IMX_CONN_LPCG_SDHC0_IPG_CLK 0 -#define IMX_CONN_LPCG_SDHC0_PER_CLK 1 -#define IMX_CONN_LPCG_SDHC0_HCLK 2 -#define IMX_CONN_LPCG_SDHC1_IPG_CLK 3 -#define IMX_CONN_LPCG_SDHC1_PER_CLK 4 -#define IMX_CONN_LPCG_SDHC1_HCLK 5 -#define IMX_CONN_LPCG_SDHC2_IPG_CLK 6 -#define IMX_CONN_LPCG_SDHC2_PER_CLK 7 -#define IMX_CONN_LPCG_SDHC2_HCLK 8 -#define IMX_CONN_LPCG_GPMI_APB_CLK 9 -#define IMX_CONN_LPCG_GPMI_BCH_APB_CLK 10 -#define IMX_CONN_LPCG_GPMI_BCH_IO_CLK 11 -#define IMX_CONN_LPCG_GPMI_BCH_CLK 12 -#define IMX_CONN_LPCG_APBHDMA_CLK 13 -#define IMX_CONN_LPCG_ENET0_ROOT_CLK 14 -#define IMX_CONN_LPCG_ENET0_TX_CLK 15 -#define IMX_CONN_LPCG_ENET0_AHB_CLK 16 -#define IMX_CONN_LPCG_ENET0_IPG_S_CLK 17 -#define IMX_CONN_LPCG_ENET0_IPG_CLK 18 - -#define IMX_CONN_LPCG_ENET1_ROOT_CLK 19 -#define IMX_CONN_LPCG_ENET1_TX_CLK 20 -#define IMX_CONN_LPCG_ENET1_AHB_CLK 21 -#define IMX_CONN_LPCG_ENET1_IPG_S_CLK 22 -#define IMX_CONN_LPCG_ENET1_IPG_CLK 23 - -#define IMX_CONN_LPCG_CLK_END 24 - -/* ADMA SS LPCG */ -#define IMX_ADMA_LPCG_UART0_IPG_CLK 0 -#define IMX_ADMA_LPCG_UART0_BAUD_CLK 1 -#define IMX_ADMA_LPCG_UART1_IPG_CLK 2 -#define IMX_ADMA_LPCG_UART1_BAUD_CLK 3 -#define IMX_ADMA_LPCG_UART2_IPG_CLK 4 -#define IMX_ADMA_LPCG_UART2_BAUD_CLK 5 -#define IMX_ADMA_LPCG_UART3_IPG_CLK 6 -#define IMX_ADMA_LPCG_UART3_BAUD_CLK 7 -#define IMX_ADMA_LPCG_SPI0_IPG_CLK 8 -#define IMX_ADMA_LPCG_SPI1_IPG_CLK 9 -#define IMX_ADMA_LPCG_SPI2_IPG_CLK 10 -#define IMX_ADMA_LPCG_SPI3_IPG_CLK 11 -#define IMX_ADMA_LPCG_SPI0_CLK 12 -#define IMX_ADMA_LPCG_SPI1_CLK 13 -#define IMX_ADMA_LPCG_SPI2_CLK 14 -#define IMX_ADMA_LPCG_SPI3_CLK 15 -#define IMX_ADMA_LPCG_CAN0_IPG_CLK 16 -#define IMX_ADMA_LPCG_CAN0_IPG_PE_CLK 17 -#define IMX_ADMA_LPCG_CAN0_IPG_CHI_CLK 18 -#define IMX_ADMA_LPCG_CAN1_IPG_CLK 19 -#define IMX_ADMA_LPCG_CAN1_IPG_PE_CLK 20 -#define IMX_ADMA_LPCG_CAN1_IPG_CHI_CLK 21 -#define IMX_ADMA_LPCG_CAN2_IPG_CLK 22 -#define IMX_ADMA_LPCG_CAN2_IPG_PE_CLK 23 -#define IMX_ADMA_LPCG_CAN2_IPG_CHI_CLK 24 -#define IMX_ADMA_LPCG_I2C0_CLK 25 -#define IMX_ADMA_LPCG_I2C1_CLK 26 -#define IMX_ADMA_LPCG_I2C2_CLK 27 -#define IMX_ADMA_LPCG_I2C3_CLK 28 -#define IMX_ADMA_LPCG_I2C0_IPG_CLK 29 -#define IMX_ADMA_LPCG_I2C1_IPG_CLK 30 -#define IMX_ADMA_LPCG_I2C2_IPG_CLK 31 -#define IMX_ADMA_LPCG_I2C3_IPG_CLK 32 -#define IMX_ADMA_LPCG_FTM0_CLK 33 -#define IMX_ADMA_LPCG_FTM1_CLK 34 -#define IMX_ADMA_LPCG_FTM0_IPG_CLK 35 -#define IMX_ADMA_LPCG_FTM1_IPG_CLK 36 -#define IMX_ADMA_LPCG_PWM_HI_CLK 37 -#define IMX_ADMA_LPCG_PWM_IPG_CLK 38 -#define IMX_ADMA_LPCG_LCD_PIX_CLK 39 -#define IMX_ADMA_LPCG_LCD_APB_CLK 40 -#define IMX_ADMA_LPCG_DSP_ADB_CLK 41 -#define IMX_ADMA_LPCG_DSP_IPG_CLK 42 -#define IMX_ADMA_LPCG_DSP_CORE_CLK 43 -#define IMX_ADMA_LPCG_OCRAM_IPG_CLK 44 - -#define IMX_ADMA_LPCG_CLK_END 45 - -#endif /* __DT_BINDINGS_CLOCK_IMX_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/imx8mm-clock.h b/sys/gnu/dts/include/dt-bindings/clock/imx8mm-clock.h deleted file mode 100644 index edeece2289f..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/imx8mm-clock.h +++ /dev/null @@ -1,270 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright 2017-2018 NXP - */ - -#ifndef __DT_BINDINGS_CLOCK_IMX8MM_H -#define __DT_BINDINGS_CLOCK_IMX8MM_H - -#define IMX8MM_CLK_DUMMY 0 -#define IMX8MM_CLK_32K 1 -#define IMX8MM_CLK_24M 2 -#define IMX8MM_OSC_HDMI_CLK 3 -#define IMX8MM_CLK_EXT1 4 -#define IMX8MM_CLK_EXT2 5 -#define IMX8MM_CLK_EXT3 6 -#define IMX8MM_CLK_EXT4 7 -#define IMX8MM_AUDIO_PLL1_REF_SEL 8 -#define IMX8MM_AUDIO_PLL2_REF_SEL 9 -#define IMX8MM_VIDEO_PLL1_REF_SEL 10 -#define IMX8MM_DRAM_PLL_REF_SEL 11 -#define IMX8MM_GPU_PLL_REF_SEL 12 -#define IMX8MM_VPU_PLL_REF_SEL 13 -#define IMX8MM_ARM_PLL_REF_SEL 14 -#define IMX8MM_SYS_PLL1_REF_SEL 15 -#define IMX8MM_SYS_PLL2_REF_SEL 16 -#define IMX8MM_SYS_PLL3_REF_SEL 17 -#define IMX8MM_AUDIO_PLL1 18 -#define IMX8MM_AUDIO_PLL2 19 -#define IMX8MM_VIDEO_PLL1 20 -#define IMX8MM_DRAM_PLL 21 -#define IMX8MM_GPU_PLL 22 -#define IMX8MM_VPU_PLL 23 -#define IMX8MM_ARM_PLL 24 -#define IMX8MM_SYS_PLL1 25 -#define IMX8MM_SYS_PLL2 26 -#define IMX8MM_SYS_PLL3 27 -#define IMX8MM_AUDIO_PLL1_BYPASS 28 -#define IMX8MM_AUDIO_PLL2_BYPASS 29 -#define IMX8MM_VIDEO_PLL1_BYPASS 30 -#define IMX8MM_DRAM_PLL_BYPASS 31 -#define IMX8MM_GPU_PLL_BYPASS 32 -#define IMX8MM_VPU_PLL_BYPASS 33 -#define IMX8MM_ARM_PLL_BYPASS 34 -#define IMX8MM_SYS_PLL1_BYPASS 35 -#define IMX8MM_SYS_PLL2_BYPASS 36 -#define IMX8MM_SYS_PLL3_BYPASS 37 -#define IMX8MM_AUDIO_PLL1_OUT 38 -#define IMX8MM_AUDIO_PLL2_OUT 39 -#define IMX8MM_VIDEO_PLL1_OUT 40 -#define IMX8MM_DRAM_PLL_OUT 41 -#define IMX8MM_GPU_PLL_OUT 42 -#define IMX8MM_VPU_PLL_OUT 43 -#define IMX8MM_ARM_PLL_OUT 44 -#define IMX8MM_SYS_PLL1_OUT 45 -#define IMX8MM_SYS_PLL2_OUT 46 -#define IMX8MM_SYS_PLL3_OUT 47 -#define IMX8MM_SYS_PLL1_40M 48 -#define IMX8MM_SYS_PLL1_80M 49 -#define IMX8MM_SYS_PLL1_100M 50 -#define IMX8MM_SYS_PLL1_133M 51 -#define IMX8MM_SYS_PLL1_160M 52 -#define IMX8MM_SYS_PLL1_200M 53 -#define IMX8MM_SYS_PLL1_266M 54 -#define IMX8MM_SYS_PLL1_400M 55 -#define IMX8MM_SYS_PLL1_800M 56 -#define IMX8MM_SYS_PLL2_50M 57 -#define IMX8MM_SYS_PLL2_100M 58 -#define IMX8MM_SYS_PLL2_125M 59 -#define IMX8MM_SYS_PLL2_166M 60 -#define IMX8MM_SYS_PLL2_200M 61 -#define IMX8MM_SYS_PLL2_250M 62 -#define IMX8MM_SYS_PLL2_333M 63 -#define IMX8MM_SYS_PLL2_500M 64 -#define IMX8MM_SYS_PLL2_1000M 65 - -/* core */ -#define IMX8MM_CLK_A53_SRC 66 -#define IMX8MM_CLK_M4_SRC 67 -#define IMX8MM_CLK_VPU_SRC 68 -#define IMX8MM_CLK_GPU3D_SRC 69 -#define IMX8MM_CLK_GPU2D_SRC 70 -#define IMX8MM_CLK_A53_CG 71 -#define IMX8MM_CLK_M4_CG 72 -#define IMX8MM_CLK_VPU_CG 73 -#define IMX8MM_CLK_GPU3D_CG 74 -#define IMX8MM_CLK_GPU2D_CG 75 -#define IMX8MM_CLK_A53_DIV 76 -#define IMX8MM_CLK_M4_DIV 77 -#define IMX8MM_CLK_VPU_DIV 78 -#define IMX8MM_CLK_GPU3D_DIV 79 -#define IMX8MM_CLK_GPU2D_DIV 80 - -/* bus */ -#define IMX8MM_CLK_MAIN_AXI 81 -#define IMX8MM_CLK_ENET_AXI 82 -#define IMX8MM_CLK_NAND_USDHC_BUS 83 -#define IMX8MM_CLK_VPU_BUS 84 -#define IMX8MM_CLK_DISP_AXI 85 -#define IMX8MM_CLK_DISP_APB 86 -#define IMX8MM_CLK_DISP_RTRM 87 -#define IMX8MM_CLK_USB_BUS 88 -#define IMX8MM_CLK_GPU_AXI 89 -#define IMX8MM_CLK_GPU_AHB 90 -#define IMX8MM_CLK_NOC 91 -#define IMX8MM_CLK_NOC_APB 92 - -#define IMX8MM_CLK_AHB 93 -#define IMX8MM_CLK_AUDIO_AHB 94 -#define IMX8MM_CLK_IPG_ROOT 95 -#define IMX8MM_CLK_IPG_AUDIO_ROOT 96 - -#define IMX8MM_CLK_DRAM_ALT 97 -#define IMX8MM_CLK_DRAM_APB 98 -#define IMX8MM_CLK_VPU_G1 99 -#define IMX8MM_CLK_VPU_G2 100 -#define IMX8MM_CLK_DISP_DTRC 101 -#define IMX8MM_CLK_DISP_DC8000 102 -#define IMX8MM_CLK_PCIE1_CTRL 103 -#define IMX8MM_CLK_PCIE1_PHY 104 -#define IMX8MM_CLK_PCIE1_AUX 105 -#define IMX8MM_CLK_DC_PIXEL 106 -#define IMX8MM_CLK_LCDIF_PIXEL 107 -#define IMX8MM_CLK_SAI1 108 -#define IMX8MM_CLK_SAI2 109 -#define IMX8MM_CLK_SAI3 110 -#define IMX8MM_CLK_SAI4 111 -#define IMX8MM_CLK_SAI5 112 -#define IMX8MM_CLK_SAI6 113 -#define IMX8MM_CLK_SPDIF1 114 -#define IMX8MM_CLK_SPDIF2 115 -#define IMX8MM_CLK_ENET_REF 116 -#define IMX8MM_CLK_ENET_TIMER 117 -#define IMX8MM_CLK_ENET_PHY_REF 118 -#define IMX8MM_CLK_NAND 119 -#define IMX8MM_CLK_QSPI 120 -#define IMX8MM_CLK_USDHC1 121 -#define IMX8MM_CLK_USDHC2 122 -#define IMX8MM_CLK_I2C1 123 -#define IMX8MM_CLK_I2C2 124 -#define IMX8MM_CLK_I2C3 125 -#define IMX8MM_CLK_I2C4 126 -#define IMX8MM_CLK_UART1 127 -#define IMX8MM_CLK_UART2 128 -#define IMX8MM_CLK_UART3 129 -#define IMX8MM_CLK_UART4 130 -#define IMX8MM_CLK_USB_CORE_REF 131 -#define IMX8MM_CLK_USB_PHY_REF 132 -#define IMX8MM_CLK_ECSPI1 133 -#define IMX8MM_CLK_ECSPI2 134 -#define IMX8MM_CLK_PWM1 135 -#define IMX8MM_CLK_PWM2 136 -#define IMX8MM_CLK_PWM3 137 -#define IMX8MM_CLK_PWM4 138 -#define IMX8MM_CLK_GPT1 139 -#define IMX8MM_CLK_WDOG 140 -#define IMX8MM_CLK_WRCLK 141 -#define IMX8MM_CLK_DSI_CORE 142 -#define IMX8MM_CLK_DSI_PHY_REF 143 -#define IMX8MM_CLK_DSI_DBI 144 -#define IMX8MM_CLK_USDHC3 145 -#define IMX8MM_CLK_CSI1_CORE 146 -#define IMX8MM_CLK_CSI1_PHY_REF 147 -#define IMX8MM_CLK_CSI1_ESC 148 -#define IMX8MM_CLK_CSI2_CORE 149 -#define IMX8MM_CLK_CSI2_PHY_REF 150 -#define IMX8MM_CLK_CSI2_ESC 151 -#define IMX8MM_CLK_PCIE2_CTRL 152 -#define IMX8MM_CLK_PCIE2_PHY 153 -#define IMX8MM_CLK_PCIE2_AUX 154 -#define IMX8MM_CLK_ECSPI3 155 -#define IMX8MM_CLK_PDM 156 -#define IMX8MM_CLK_VPU_H1 157 -#define IMX8MM_CLK_CLKO1 158 - -#define IMX8MM_CLK_ECSPI1_ROOT 159 -#define IMX8MM_CLK_ECSPI2_ROOT 160 -#define IMX8MM_CLK_ECSPI3_ROOT 161 -#define IMX8MM_CLK_ENET1_ROOT 162 -#define IMX8MM_CLK_GPT1_ROOT 163 -#define IMX8MM_CLK_I2C1_ROOT 164 -#define IMX8MM_CLK_I2C2_ROOT 165 -#define IMX8MM_CLK_I2C3_ROOT 166 -#define IMX8MM_CLK_I2C4_ROOT 167 -#define IMX8MM_CLK_OCOTP_ROOT 168 -#define IMX8MM_CLK_PCIE1_ROOT 169 -#define IMX8MM_CLK_PWM1_ROOT 170 -#define IMX8MM_CLK_PWM2_ROOT 171 -#define IMX8MM_CLK_PWM3_ROOT 172 -#define IMX8MM_CLK_PWM4_ROOT 173 -#define IMX8MM_CLK_QSPI_ROOT 174 -#define IMX8MM_CLK_NAND_ROOT 175 -#define IMX8MM_CLK_SAI1_ROOT 176 -#define IMX8MM_CLK_SAI1_IPG 177 -#define IMX8MM_CLK_SAI2_ROOT 178 -#define IMX8MM_CLK_SAI2_IPG 179 -#define IMX8MM_CLK_SAI3_ROOT 180 -#define IMX8MM_CLK_SAI3_IPG 181 -#define IMX8MM_CLK_SAI4_ROOT 182 -#define IMX8MM_CLK_SAI4_IPG 183 -#define IMX8MM_CLK_SAI5_ROOT 184 -#define IMX8MM_CLK_SAI5_IPG 185 -#define IMX8MM_CLK_SAI6_ROOT 186 -#define IMX8MM_CLK_SAI6_IPG 187 -#define IMX8MM_CLK_UART1_ROOT 188 -#define IMX8MM_CLK_UART2_ROOT 189 -#define IMX8MM_CLK_UART3_ROOT 190 -#define IMX8MM_CLK_UART4_ROOT 191 -#define IMX8MM_CLK_USB1_CTRL_ROOT 192 -#define IMX8MM_CLK_GPU3D_ROOT 193 -#define IMX8MM_CLK_USDHC1_ROOT 194 -#define IMX8MM_CLK_USDHC2_ROOT 195 -#define IMX8MM_CLK_WDOG1_ROOT 196 -#define IMX8MM_CLK_WDOG2_ROOT 197 -#define IMX8MM_CLK_WDOG3_ROOT 198 -#define IMX8MM_CLK_VPU_G1_ROOT 199 -#define IMX8MM_CLK_GPU_BUS_ROOT 200 -#define IMX8MM_CLK_VPU_H1_ROOT 201 -#define IMX8MM_CLK_VPU_G2_ROOT 202 -#define IMX8MM_CLK_PDM_ROOT 203 -#define IMX8MM_CLK_DISP_ROOT 204 -#define IMX8MM_CLK_DISP_AXI_ROOT 205 -#define IMX8MM_CLK_DISP_APB_ROOT 206 -#define IMX8MM_CLK_DISP_RTRM_ROOT 207 -#define IMX8MM_CLK_USDHC3_ROOT 208 -#define IMX8MM_CLK_TMU_ROOT 209 -#define IMX8MM_CLK_VPU_DEC_ROOT 210 -#define IMX8MM_CLK_SDMA1_ROOT 211 -#define IMX8MM_CLK_SDMA2_ROOT 212 -#define IMX8MM_CLK_SDMA3_ROOT 213 -#define IMX8MM_CLK_GPT_3M 214 -#define IMX8MM_CLK_ARM 215 -#define IMX8MM_CLK_PDM_IPG 216 -#define IMX8MM_CLK_GPU2D_ROOT 217 -#define IMX8MM_CLK_MU_ROOT 218 -#define IMX8MM_CLK_CSI1_ROOT 219 - -#define IMX8MM_CLK_DRAM_CORE 220 -#define IMX8MM_CLK_DRAM_ALT_ROOT 221 - -#define IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK 222 - -#define IMX8MM_CLK_GPIO1_ROOT 223 -#define IMX8MM_CLK_GPIO2_ROOT 224 -#define IMX8MM_CLK_GPIO3_ROOT 225 -#define IMX8MM_CLK_GPIO4_ROOT 226 -#define IMX8MM_CLK_GPIO5_ROOT 227 - -#define IMX8MM_CLK_SNVS_ROOT 228 -#define IMX8MM_CLK_GIC 229 - -#define IMX8MM_SYS_PLL1_40M_CG 230 -#define IMX8MM_SYS_PLL1_80M_CG 231 -#define IMX8MM_SYS_PLL1_100M_CG 232 -#define IMX8MM_SYS_PLL1_133M_CG 233 -#define IMX8MM_SYS_PLL1_160M_CG 234 -#define IMX8MM_SYS_PLL1_200M_CG 235 -#define IMX8MM_SYS_PLL1_266M_CG 236 -#define IMX8MM_SYS_PLL1_400M_CG 237 -#define IMX8MM_SYS_PLL2_50M_CG 238 -#define IMX8MM_SYS_PLL2_100M_CG 239 -#define IMX8MM_SYS_PLL2_125M_CG 240 -#define IMX8MM_SYS_PLL2_166M_CG 241 -#define IMX8MM_SYS_PLL2_200M_CG 242 -#define IMX8MM_SYS_PLL2_250M_CG 243 -#define IMX8MM_SYS_PLL2_333M_CG 244 -#define IMX8MM_SYS_PLL2_500M_CG 245 - -#define IMX8MM_CLK_END 246 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/imx8mn-clock.h b/sys/gnu/dts/include/dt-bindings/clock/imx8mn-clock.h deleted file mode 100644 index 65ac6eb6c73..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/imx8mn-clock.h +++ /dev/null @@ -1,233 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright 2018-2019 NXP - */ - -#ifndef __DT_BINDINGS_CLOCK_IMX8MN_H -#define __DT_BINDINGS_CLOCK_IMX8MN_H - -#define IMX8MN_CLK_DUMMY 0 -#define IMX8MN_CLK_32K 1 -#define IMX8MN_CLK_24M 2 -#define IMX8MN_OSC_HDMI_CLK 3 -#define IMX8MN_CLK_EXT1 4 -#define IMX8MN_CLK_EXT2 5 -#define IMX8MN_CLK_EXT3 6 -#define IMX8MN_CLK_EXT4 7 -#define IMX8MN_AUDIO_PLL1_REF_SEL 8 -#define IMX8MN_AUDIO_PLL2_REF_SEL 9 -#define IMX8MN_VIDEO_PLL1_REF_SEL 10 -#define IMX8MN_DRAM_PLL_REF_SEL 11 -#define IMX8MN_GPU_PLL_REF_SEL 12 -#define IMX8MN_VPU_PLL_REF_SEL 13 -#define IMX8MN_ARM_PLL_REF_SEL 14 -#define IMX8MN_SYS_PLL1_REF_SEL 15 -#define IMX8MN_SYS_PLL2_REF_SEL 16 -#define IMX8MN_SYS_PLL3_REF_SEL 17 -#define IMX8MN_AUDIO_PLL1 18 -#define IMX8MN_AUDIO_PLL2 19 -#define IMX8MN_VIDEO_PLL1 20 -#define IMX8MN_DRAM_PLL 21 -#define IMX8MN_GPU_PLL 22 -#define IMX8MN_VPU_PLL 23 -#define IMX8MN_ARM_PLL 24 -#define IMX8MN_SYS_PLL1 25 -#define IMX8MN_SYS_PLL2 26 -#define IMX8MN_SYS_PLL3 27 -#define IMX8MN_AUDIO_PLL1_BYPASS 28 -#define IMX8MN_AUDIO_PLL2_BYPASS 29 -#define IMX8MN_VIDEO_PLL1_BYPASS 30 -#define IMX8MN_DRAM_PLL_BYPASS 31 -#define IMX8MN_GPU_PLL_BYPASS 32 -#define IMX8MN_VPU_PLL_BYPASS 33 -#define IMX8MN_ARM_PLL_BYPASS 34 -#define IMX8MN_SYS_PLL1_BYPASS 35 -#define IMX8MN_SYS_PLL2_BYPASS 36 -#define IMX8MN_SYS_PLL3_BYPASS 37 -#define IMX8MN_AUDIO_PLL1_OUT 38 -#define IMX8MN_AUDIO_PLL2_OUT 39 -#define IMX8MN_VIDEO_PLL1_OUT 40 -#define IMX8MN_DRAM_PLL_OUT 41 -#define IMX8MN_GPU_PLL_OUT 42 -#define IMX8MN_VPU_PLL_OUT 43 -#define IMX8MN_ARM_PLL_OUT 44 -#define IMX8MN_SYS_PLL1_OUT 45 -#define IMX8MN_SYS_PLL2_OUT 46 -#define IMX8MN_SYS_PLL3_OUT 47 -#define IMX8MN_SYS_PLL1_40M 48 -#define IMX8MN_SYS_PLL1_80M 49 -#define IMX8MN_SYS_PLL1_100M 50 -#define IMX8MN_SYS_PLL1_133M 51 -#define IMX8MN_SYS_PLL1_160M 52 -#define IMX8MN_SYS_PLL1_200M 53 -#define IMX8MN_SYS_PLL1_266M 54 -#define IMX8MN_SYS_PLL1_400M 55 -#define IMX8MN_SYS_PLL1_800M 56 -#define IMX8MN_SYS_PLL2_50M 57 -#define IMX8MN_SYS_PLL2_100M 58 -#define IMX8MN_SYS_PLL2_125M 59 -#define IMX8MN_SYS_PLL2_166M 60 -#define IMX8MN_SYS_PLL2_200M 61 -#define IMX8MN_SYS_PLL2_250M 62 -#define IMX8MN_SYS_PLL2_333M 63 -#define IMX8MN_SYS_PLL2_500M 64 -#define IMX8MN_SYS_PLL2_1000M 65 - -/* CORE CLOCK ROOT */ -#define IMX8MN_CLK_A53_SRC 66 -#define IMX8MN_CLK_GPU_CORE_SRC 67 -#define IMX8MN_CLK_GPU_SHADER_SRC 68 -#define IMX8MN_CLK_A53_CG 69 -#define IMX8MN_CLK_GPU_CORE_CG 70 -#define IMX8MN_CLK_GPU_SHADER_CG 71 -#define IMX8MN_CLK_A53_DIV 72 -#define IMX8MN_CLK_GPU_CORE_DIV 73 -#define IMX8MN_CLK_GPU_SHADER_DIV 74 - -/* BUS CLOCK ROOT */ -#define IMX8MN_CLK_MAIN_AXI 75 -#define IMX8MN_CLK_ENET_AXI 76 -#define IMX8MN_CLK_NAND_USDHC_BUS 77 -#define IMX8MN_CLK_DISP_AXI 78 -#define IMX8MN_CLK_DISP_APB 79 -#define IMX8MN_CLK_USB_BUS 80 -#define IMX8MN_CLK_GPU_AXI 81 -#define IMX8MN_CLK_GPU_AHB 82 -#define IMX8MN_CLK_NOC 83 -#define IMX8MN_CLK_AHB 84 -#define IMX8MN_CLK_AUDIO_AHB 85 - -/* IPG CLOCK ROOT */ -#define IMX8MN_CLK_IPG_ROOT 86 -#define IMX8MN_CLK_IPG_AUDIO_ROOT 87 - -/* IP */ -#define IMX8MN_CLK_DRAM_CORE 88 -#define IMX8MN_CLK_DRAM_ALT 89 -#define IMX8MN_CLK_DRAM_APB 90 -#define IMX8MN_CLK_DRAM_ALT_ROOT 91 -#define IMX8MN_CLK_DISP_PIXEL 92 -#define IMX8MN_CLK_SAI2 93 -#define IMX8MN_CLK_SAI3 94 -#define IMX8MN_CLK_SAI5 95 -#define IMX8MN_CLK_SAI6 96 -#define IMX8MN_CLK_SPDIF1 97 -#define IMX8MN_CLK_ENET_REF 98 -#define IMX8MN_CLK_ENET_TIMER 99 -#define IMX8MN_CLK_ENET_PHY_REF 100 -#define IMX8MN_CLK_NAND 101 -#define IMX8MN_CLK_QSPI 102 -#define IMX8MN_CLK_USDHC1 103 -#define IMX8MN_CLK_USDHC2 104 -#define IMX8MN_CLK_I2C1 105 -#define IMX8MN_CLK_I2C2 106 -#define IMX8MN_CLK_I2C3 107 -#define IMX8MN_CLK_I2C4 108 -#define IMX8MN_CLK_UART1 109 -#define IMX8MN_CLK_UART2 110 -#define IMX8MN_CLK_UART3 111 -#define IMX8MN_CLK_UART4 112 -#define IMX8MN_CLK_USB_CORE_REF 113 -#define IMX8MN_CLK_USB_PHY_REF 114 -#define IMX8MN_CLK_ECSPI1 115 -#define IMX8MN_CLK_ECSPI2 116 -#define IMX8MN_CLK_PWM1 117 -#define IMX8MN_CLK_PWM2 118 -#define IMX8MN_CLK_PWM3 119 -#define IMX8MN_CLK_PWM4 120 -#define IMX8MN_CLK_WDOG 121 -#define IMX8MN_CLK_WRCLK 122 -#define IMX8MN_CLK_CLKO1 123 -#define IMX8MN_CLK_CLKO2 124 -#define IMX8MN_CLK_DSI_CORE 125 -#define IMX8MN_CLK_DSI_PHY_REF 126 -#define IMX8MN_CLK_DSI_DBI 127 -#define IMX8MN_CLK_USDHC3 128 -#define IMX8MN_CLK_CAMERA_PIXEL 129 -#define IMX8MN_CLK_CSI1_PHY_REF 130 -#define IMX8MN_CLK_CSI2_PHY_REF 131 -#define IMX8MN_CLK_CSI2_ESC 132 -#define IMX8MN_CLK_ECSPI3 133 -#define IMX8MN_CLK_PDM 134 -#define IMX8MN_CLK_SAI7 135 - -#define IMX8MN_CLK_ECSPI1_ROOT 136 -#define IMX8MN_CLK_ECSPI2_ROOT 137 -#define IMX8MN_CLK_ECSPI3_ROOT 138 -#define IMX8MN_CLK_ENET1_ROOT 139 -#define IMX8MN_CLK_GPIO1_ROOT 140 -#define IMX8MN_CLK_GPIO2_ROOT 141 -#define IMX8MN_CLK_GPIO3_ROOT 142 -#define IMX8MN_CLK_GPIO4_ROOT 143 -#define IMX8MN_CLK_GPIO5_ROOT 144 -#define IMX8MN_CLK_I2C1_ROOT 145 -#define IMX8MN_CLK_I2C2_ROOT 146 -#define IMX8MN_CLK_I2C3_ROOT 147 -#define IMX8MN_CLK_I2C4_ROOT 148 -#define IMX8MN_CLK_MU_ROOT 149 -#define IMX8MN_CLK_OCOTP_ROOT 150 -#define IMX8MN_CLK_PWM1_ROOT 151 -#define IMX8MN_CLK_PWM2_ROOT 152 -#define IMX8MN_CLK_PWM3_ROOT 153 -#define IMX8MN_CLK_PWM4_ROOT 154 -#define IMX8MN_CLK_QSPI_ROOT 155 -#define IMX8MN_CLK_NAND_ROOT 156 -#define IMX8MN_CLK_SAI2_ROOT 157 -#define IMX8MN_CLK_SAI2_IPG 158 -#define IMX8MN_CLK_SAI3_ROOT 159 -#define IMX8MN_CLK_SAI3_IPG 160 -#define IMX8MN_CLK_SAI5_ROOT 161 -#define IMX8MN_CLK_SAI5_IPG 162 -#define IMX8MN_CLK_SAI6_ROOT 163 -#define IMX8MN_CLK_SAI6_IPG 164 -#define IMX8MN_CLK_SAI7_ROOT 165 -#define IMX8MN_CLK_SAI7_IPG 166 -#define IMX8MN_CLK_SDMA1_ROOT 167 -#define IMX8MN_CLK_SDMA2_ROOT 168 -#define IMX8MN_CLK_UART1_ROOT 169 -#define IMX8MN_CLK_UART2_ROOT 170 -#define IMX8MN_CLK_UART3_ROOT 171 -#define IMX8MN_CLK_UART4_ROOT 172 -#define IMX8MN_CLK_USB1_CTRL_ROOT 173 -#define IMX8MN_CLK_USDHC1_ROOT 174 -#define IMX8MN_CLK_USDHC2_ROOT 175 -#define IMX8MN_CLK_WDOG1_ROOT 176 -#define IMX8MN_CLK_WDOG2_ROOT 177 -#define IMX8MN_CLK_WDOG3_ROOT 178 -#define IMX8MN_CLK_GPU_BUS_ROOT 179 -#define IMX8MN_CLK_ASRC_ROOT 180 -#define IMX8MN_CLK_GPU3D_ROOT 181 -#define IMX8MN_CLK_PDM_ROOT 182 -#define IMX8MN_CLK_PDM_IPG 183 -#define IMX8MN_CLK_DISP_AXI_ROOT 184 -#define IMX8MN_CLK_DISP_APB_ROOT 185 -#define IMX8MN_CLK_DISP_PIXEL_ROOT 186 -#define IMX8MN_CLK_CAMERA_PIXEL_ROOT 187 -#define IMX8MN_CLK_USDHC3_ROOT 188 -#define IMX8MN_CLK_SDMA3_ROOT 189 -#define IMX8MN_CLK_TMU_ROOT 190 -#define IMX8MN_CLK_ARM 191 -#define IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK 192 -#define IMX8MN_CLK_GPU_CORE_ROOT 193 -#define IMX8MN_CLK_GIC 194 - -#define IMX8MN_SYS_PLL1_40M_CG 195 -#define IMX8MN_SYS_PLL1_80M_CG 196 -#define IMX8MN_SYS_PLL1_100M_CG 197 -#define IMX8MN_SYS_PLL1_133M_CG 198 -#define IMX8MN_SYS_PLL1_160M_CG 199 -#define IMX8MN_SYS_PLL1_200M_CG 200 -#define IMX8MN_SYS_PLL1_266M_CG 201 -#define IMX8MN_SYS_PLL1_400M_CG 202 -#define IMX8MN_SYS_PLL2_50M_CG 203 -#define IMX8MN_SYS_PLL2_100M_CG 204 -#define IMX8MN_SYS_PLL2_125M_CG 205 -#define IMX8MN_SYS_PLL2_166M_CG 206 -#define IMX8MN_SYS_PLL2_200M_CG 207 -#define IMX8MN_SYS_PLL2_250M_CG 208 -#define IMX8MN_SYS_PLL2_333M_CG 209 -#define IMX8MN_SYS_PLL2_500M_CG 210 - -#define IMX8MN_CLK_END 211 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/imx8mp-clock.h b/sys/gnu/dts/include/dt-bindings/clock/imx8mp-clock.h deleted file mode 100644 index 2fab63186bc..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/imx8mp-clock.h +++ /dev/null @@ -1,300 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright 2019 NXP - */ - -#ifndef __DT_BINDINGS_CLOCK_IMX8MP_H -#define __DT_BINDINGS_CLOCK_IMX8MP_H - -#define IMX8MP_CLK_DUMMY 0 -#define IMX8MP_CLK_32K 1 -#define IMX8MP_CLK_24M 2 -#define IMX8MP_OSC_HDMI_CLK 3 -#define IMX8MP_CLK_EXT1 4 -#define IMX8MP_CLK_EXT2 5 -#define IMX8MP_CLK_EXT3 6 -#define IMX8MP_CLK_EXT4 7 -#define IMX8MP_AUDIO_PLL1_REF_SEL 8 -#define IMX8MP_AUDIO_PLL2_REF_SEL 9 -#define IMX8MP_VIDEO_PLL1_REF_SEL 10 -#define IMX8MP_DRAM_PLL_REF_SEL 11 -#define IMX8MP_GPU_PLL_REF_SEL 12 -#define IMX8MP_VPU_PLL_REF_SEL 13 -#define IMX8MP_ARM_PLL_REF_SEL 14 -#define IMX8MP_SYS_PLL1_REF_SEL 15 -#define IMX8MP_SYS_PLL2_REF_SEL 16 -#define IMX8MP_SYS_PLL3_REF_SEL 17 -#define IMX8MP_AUDIO_PLL1 18 -#define IMX8MP_AUDIO_PLL2 19 -#define IMX8MP_VIDEO_PLL1 20 -#define IMX8MP_DRAM_PLL 21 -#define IMX8MP_GPU_PLL 22 -#define IMX8MP_VPU_PLL 23 -#define IMX8MP_ARM_PLL 24 -#define IMX8MP_SYS_PLL1 25 -#define IMX8MP_SYS_PLL2 26 -#define IMX8MP_SYS_PLL3 27 -#define IMX8MP_AUDIO_PLL1_BYPASS 28 -#define IMX8MP_AUDIO_PLL2_BYPASS 29 -#define IMX8MP_VIDEO_PLL1_BYPASS 30 -#define IMX8MP_DRAM_PLL_BYPASS 31 -#define IMX8MP_GPU_PLL_BYPASS 32 -#define IMX8MP_VPU_PLL_BYPASS 33 -#define IMX8MP_ARM_PLL_BYPASS 34 -#define IMX8MP_SYS_PLL1_BYPASS 35 -#define IMX8MP_SYS_PLL2_BYPASS 36 -#define IMX8MP_SYS_PLL3_BYPASS 37 -#define IMX8MP_AUDIO_PLL1_OUT 38 -#define IMX8MP_AUDIO_PLL2_OUT 39 -#define IMX8MP_VIDEO_PLL1_OUT 40 -#define IMX8MP_DRAM_PLL_OUT 41 -#define IMX8MP_GPU_PLL_OUT 42 -#define IMX8MP_VPU_PLL_OUT 43 -#define IMX8MP_ARM_PLL_OUT 44 -#define IMX8MP_SYS_PLL1_OUT 45 -#define IMX8MP_SYS_PLL2_OUT 46 -#define IMX8MP_SYS_PLL3_OUT 47 -#define IMX8MP_SYS_PLL1_40M 48 -#define IMX8MP_SYS_PLL1_80M 49 -#define IMX8MP_SYS_PLL1_100M 50 -#define IMX8MP_SYS_PLL1_133M 51 -#define IMX8MP_SYS_PLL1_160M 52 -#define IMX8MP_SYS_PLL1_200M 53 -#define IMX8MP_SYS_PLL1_266M 54 -#define IMX8MP_SYS_PLL1_400M 55 -#define IMX8MP_SYS_PLL1_800M 56 -#define IMX8MP_SYS_PLL2_50M 57 -#define IMX8MP_SYS_PLL2_100M 58 -#define IMX8MP_SYS_PLL2_125M 59 -#define IMX8MP_SYS_PLL2_166M 60 -#define IMX8MP_SYS_PLL2_200M 61 -#define IMX8MP_SYS_PLL2_250M 62 -#define IMX8MP_SYS_PLL2_333M 63 -#define IMX8MP_SYS_PLL2_500M 64 -#define IMX8MP_SYS_PLL2_1000M 65 -#define IMX8MP_CLK_A53_SRC 66 -#define IMX8MP_CLK_M7_SRC 67 -#define IMX8MP_CLK_ML_SRC 68 -#define IMX8MP_CLK_GPU3D_CORE_SRC 69 -#define IMX8MP_CLK_GPU3D_SHADER_SRC 70 -#define IMX8MP_CLK_GPU2D_SRC 71 -#define IMX8MP_CLK_AUDIO_AXI_SRC 72 -#define IMX8MP_CLK_HSIO_AXI_SRC 73 -#define IMX8MP_CLK_MEDIA_ISP_SRC 74 -#define IMX8MP_CLK_A53_CG 75 -#define IMX8MP_CLK_M4_CG 76 -#define IMX8MP_CLK_ML_CG 77 -#define IMX8MP_CLK_GPU3D_CORE_CG 78 -#define IMX8MP_CLK_GPU3D_SHADER_CG 79 -#define IMX8MP_CLK_GPU2D_CG 80 -#define IMX8MP_CLK_AUDIO_AXI_CG 81 -#define IMX8MP_CLK_HSIO_AXI_CG 82 -#define IMX8MP_CLK_MEDIA_ISP_CG 83 -#define IMX8MP_CLK_A53_DIV 84 -#define IMX8MP_CLK_M7_DIV 85 -#define IMX8MP_CLK_ML_DIV 86 -#define IMX8MP_CLK_GPU3D_CORE_DIV 87 -#define IMX8MP_CLK_GPU3D_SHADER_DIV 88 -#define IMX8MP_CLK_GPU2D_DIV 89 -#define IMX8MP_CLK_AUDIO_AXI_DIV 90 -#define IMX8MP_CLK_HSIO_AXI_DIV 91 -#define IMX8MP_CLK_MEDIA_ISP_DIV 92 -#define IMX8MP_CLK_MAIN_AXI 93 -#define IMX8MP_CLK_ENET_AXI 94 -#define IMX8MP_CLK_NAND_USDHC_BUS 95 -#define IMX8MP_CLK_VPU_BUS 96 -#define IMX8MP_CLK_MEDIA_AXI 97 -#define IMX8MP_CLK_MEDIA_APB 98 -#define IMX8MP_CLK_HDMI_APB 99 -#define IMX8MP_CLK_HDMI_AXI 100 -#define IMX8MP_CLK_GPU_AXI 101 -#define IMX8MP_CLK_GPU_AHB 102 -#define IMX8MP_CLK_NOC 103 -#define IMX8MP_CLK_NOC_IO 104 -#define IMX8MP_CLK_ML_AXI 105 -#define IMX8MP_CLK_ML_AHB 106 -#define IMX8MP_CLK_AHB 107 -#define IMX8MP_CLK_AUDIO_AHB 108 -#define IMX8MP_CLK_MIPI_DSI_ESC_RX 109 -#define IMX8MP_CLK_IPG_ROOT 110 -#define IMX8MP_CLK_IPG_AUDIO_ROOT 111 -#define IMX8MP_CLK_DRAM_ALT 112 -#define IMX8MP_CLK_DRAM_APB 113 -#define IMX8MP_CLK_VPU_G1 114 -#define IMX8MP_CLK_VPU_G2 115 -#define IMX8MP_CLK_CAN1 116 -#define IMX8MP_CLK_CAN2 117 -#define IMX8MP_CLK_MEMREPAIR 118 -#define IMX8MP_CLK_PCIE_PHY 119 -#define IMX8MP_CLK_PCIE_AUX 120 -#define IMX8MP_CLK_I2C5 121 -#define IMX8MP_CLK_I2C6 122 -#define IMX8MP_CLK_SAI1 123 -#define IMX8MP_CLK_SAI2 124 -#define IMX8MP_CLK_SAI3 125 -#define IMX8MP_CLK_SAI4 126 -#define IMX8MP_CLK_SAI5 127 -#define IMX8MP_CLK_SAI6 128 -#define IMX8MP_CLK_ENET_QOS 129 -#define IMX8MP_CLK_ENET_QOS_TIMER 130 -#define IMX8MP_CLK_ENET_REF 131 -#define IMX8MP_CLK_ENET_TIMER 132 -#define IMX8MP_CLK_ENET_PHY_REF 133 -#define IMX8MP_CLK_NAND 134 -#define IMX8MP_CLK_QSPI 135 -#define IMX8MP_CLK_USDHC1 136 -#define IMX8MP_CLK_USDHC2 137 -#define IMX8MP_CLK_I2C1 138 -#define IMX8MP_CLK_I2C2 139 -#define IMX8MP_CLK_I2C3 140 -#define IMX8MP_CLK_I2C4 141 -#define IMX8MP_CLK_UART1 142 -#define IMX8MP_CLK_UART2 143 -#define IMX8MP_CLK_UART3 144 -#define IMX8MP_CLK_UART4 145 -#define IMX8MP_CLK_USB_CORE_REF 146 -#define IMX8MP_CLK_USB_PHY_REF 147 -#define IMX8MP_CLK_GIC 148 -#define IMX8MP_CLK_ECSPI1 149 -#define IMX8MP_CLK_ECSPI2 150 -#define IMX8MP_CLK_PWM1 151 -#define IMX8MP_CLK_PWM2 152 -#define IMX8MP_CLK_PWM3 153 -#define IMX8MP_CLK_PWM4 154 -#define IMX8MP_CLK_GPT1 155 -#define IMX8MP_CLK_GPT2 156 -#define IMX8MP_CLK_GPT3 157 -#define IMX8MP_CLK_GPT4 158 -#define IMX8MP_CLK_GPT5 159 -#define IMX8MP_CLK_GPT6 160 -#define IMX8MP_CLK_TRACE 161 -#define IMX8MP_CLK_WDOG 162 -#define IMX8MP_CLK_WRCLK 163 -#define IMX8MP_CLK_IPP_DO_CLKO1 164 -#define IMX8MP_CLK_IPP_DO_CLKO2 165 -#define IMX8MP_CLK_HDMI_FDCC_TST 166 -#define IMX8MP_CLK_HDMI_27M 167 -#define IMX8MP_CLK_HDMI_REF_266M 168 -#define IMX8MP_CLK_USDHC3 169 -#define IMX8MP_CLK_MEDIA_CAM1_PIX 170 -#define IMX8MP_CLK_MEDIA_MIPI_PHY1_REF 171 -#define IMX8MP_CLK_MEDIA_DISP1_PIX 172 -#define IMX8MP_CLK_MEDIA_CAM2_PIX 173 -#define IMX8MP_CLK_MEDIA_MIPI_PHY2_REF 174 -#define IMX8MP_CLK_MEDIA_MIPI_CSI2_ESC 175 -#define IMX8MP_CLK_PCIE2_CTRL 176 -#define IMX8MP_CLK_PCIE2_PHY 177 -#define IMX8MP_CLK_MEDIA_MIPI_TEST_BYTE 178 -#define IMX8MP_CLK_ECSPI3 179 -#define IMX8MP_CLK_PDM 180 -#define IMX8MP_CLK_VPU_VC8000E 181 -#define IMX8MP_CLK_SAI7 182 -#define IMX8MP_CLK_GPC_ROOT 183 -#define IMX8MP_CLK_ANAMIX_ROOT 184 -#define IMX8MP_CLK_CPU_ROOT 185 -#define IMX8MP_CLK_CSU_ROOT 186 -#define IMX8MP_CLK_DEBUG_ROOT 187 -#define IMX8MP_CLK_DRAM1_ROOT 188 -#define IMX8MP_CLK_ECSPI1_ROOT 189 -#define IMX8MP_CLK_ECSPI2_ROOT 190 -#define IMX8MP_CLK_ECSPI3_ROOT 191 -#define IMX8MP_CLK_ENET1_ROOT 192 -#define IMX8MP_CLK_GPIO1_ROOT 193 -#define IMX8MP_CLK_GPIO2_ROOT 194 -#define IMX8MP_CLK_GPIO3_ROOT 195 -#define IMX8MP_CLK_GPIO4_ROOT 196 -#define IMX8MP_CLK_GPIO5_ROOT 197 -#define IMX8MP_CLK_GPT1_ROOT 198 -#define IMX8MP_CLK_GPT2_ROOT 199 -#define IMX8MP_CLK_GPT3_ROOT 200 -#define IMX8MP_CLK_GPT4_ROOT 201 -#define IMX8MP_CLK_GPT5_ROOT 202 -#define IMX8MP_CLK_GPT6_ROOT 203 -#define IMX8MP_CLK_HS_ROOT 204 -#define IMX8MP_CLK_I2C1_ROOT 205 -#define IMX8MP_CLK_I2C2_ROOT 206 -#define IMX8MP_CLK_I2C3_ROOT 207 -#define IMX8MP_CLK_I2C4_ROOT 208 -#define IMX8MP_CLK_IOMUX_ROOT 209 -#define IMX8MP_CLK_IPMUX1_ROOT 210 -#define IMX8MP_CLK_IPMUX2_ROOT 211 -#define IMX8MP_CLK_IPMUX3_ROOT 212 -#define IMX8MP_CLK_MU_ROOT 213 -#define IMX8MP_CLK_OCOTP_ROOT 214 -#define IMX8MP_CLK_OCRAM_ROOT 215 -#define IMX8MP_CLK_OCRAM_S_ROOT 216 -#define IMX8MP_CLK_PCIE_ROOT 217 -#define IMX8MP_CLK_PERFMON1_ROOT 218 -#define IMX8MP_CLK_PERFMON2_ROOT 219 -#define IMX8MP_CLK_PWM1_ROOT 220 -#define IMX8MP_CLK_PWM2_ROOT 221 -#define IMX8MP_CLK_PWM3_ROOT 222 -#define IMX8MP_CLK_PWM4_ROOT 223 -#define IMX8MP_CLK_QOS_ROOT 224 -#define IMX8MP_CLK_QOS_ENET_ROOT 225 -#define IMX8MP_CLK_QSPI_ROOT 226 -#define IMX8MP_CLK_NAND_ROOT 227 -#define IMX8MP_CLK_NAND_USDHC_BUS_RAWNAND_CLK 228 -#define IMX8MP_CLK_RDC_ROOT 229 -#define IMX8MP_CLK_ROM_ROOT 230 -#define IMX8MP_CLK_I2C5_ROOT 231 -#define IMX8MP_CLK_I2C6_ROOT 232 -#define IMX8MP_CLK_CAN1_ROOT 233 -#define IMX8MP_CLK_CAN2_ROOT 234 -#define IMX8MP_CLK_SCTR_ROOT 235 -#define IMX8MP_CLK_SDMA1_ROOT 236 -#define IMX8MP_CLK_ENET_QOS_ROOT 237 -#define IMX8MP_CLK_SEC_DEBUG_ROOT 238 -#define IMX8MP_CLK_SEMA1_ROOT 239 -#define IMX8MP_CLK_SEMA2_ROOT 240 -#define IMX8MP_CLK_IRQ_STEER_ROOT 241 -#define IMX8MP_CLK_SIM_ENET_ROOT 242 -#define IMX8MP_CLK_SIM_M_ROOT 243 -#define IMX8MP_CLK_SIM_MAIN_ROOT 244 -#define IMX8MP_CLK_SIM_S_ROOT 245 -#define IMX8MP_CLK_SIM_WAKEUP_ROOT 246 -#define IMX8MP_CLK_GPU2D_ROOT 247 -#define IMX8MP_CLK_GPU3D_ROOT 248 -#define IMX8MP_CLK_SNVS_ROOT 249 -#define IMX8MP_CLK_TRACE_ROOT 250 -#define IMX8MP_CLK_UART1_ROOT 251 -#define IMX8MP_CLK_UART2_ROOT 252 -#define IMX8MP_CLK_UART3_ROOT 253 -#define IMX8MP_CLK_UART4_ROOT 254 -#define IMX8MP_CLK_USB_ROOT 255 -#define IMX8MP_CLK_USB_PHY_ROOT 256 -#define IMX8MP_CLK_USDHC1_ROOT 257 -#define IMX8MP_CLK_USDHC2_ROOT 258 -#define IMX8MP_CLK_WDOG1_ROOT 259 -#define IMX8MP_CLK_WDOG2_ROOT 260 -#define IMX8MP_CLK_WDOG3_ROOT 261 -#define IMX8MP_CLK_VPU_G1_ROOT 262 -#define IMX8MP_CLK_GPU_ROOT 263 -#define IMX8MP_CLK_NOC_WRAPPER_ROOT 264 -#define IMX8MP_CLK_VPU_VC8KE_ROOT 265 -#define IMX8MP_CLK_VPU_G2_ROOT 266 -#define IMX8MP_CLK_NPU_ROOT 267 -#define IMX8MP_CLK_HSIO_ROOT 268 -#define IMX8MP_CLK_MEDIA_APB_ROOT 269 -#define IMX8MP_CLK_MEDIA_AXI_ROOT 270 -#define IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT 271 -#define IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT 272 -#define IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT 273 -#define IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT 274 -#define IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT 275 -#define IMX8MP_CLK_MEDIA_ISP_ROOT 276 -#define IMX8MP_CLK_USDHC3_ROOT 277 -#define IMX8MP_CLK_HDMI_ROOT 278 -#define IMX8MP_CLK_XTAL_ROOT 279 -#define IMX8MP_CLK_PLL_ROOT 280 -#define IMX8MP_CLK_TSENSOR_ROOT 281 -#define IMX8MP_CLK_VPU_ROOT 282 -#define IMX8MP_CLK_MRPR_ROOT 283 -#define IMX8MP_CLK_AUDIO_ROOT 284 -#define IMX8MP_CLK_DRAM_ALT_ROOT 285 -#define IMX8MP_CLK_DRAM_CORE 286 -#define IMX8MP_CLK_ARM 287 - -#define IMX8MP_CLK_END 288 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/imx8mq-clock.h b/sys/gnu/dts/include/dt-bindings/clock/imx8mq-clock.h deleted file mode 100644 index 3bab9b21c8d..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/imx8mq-clock.h +++ /dev/null @@ -1,429 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright 2016 Freescale Semiconductor, Inc. - * Copyright 2017 NXP - */ - -#ifndef __DT_BINDINGS_CLOCK_IMX8MQ_H -#define __DT_BINDINGS_CLOCK_IMX8MQ_H - -#define IMX8MQ_CLK_DUMMY 0 -#define IMX8MQ_CLK_32K 1 -#define IMX8MQ_CLK_25M 2 -#define IMX8MQ_CLK_27M 3 -#define IMX8MQ_CLK_EXT1 4 -#define IMX8MQ_CLK_EXT2 5 -#define IMX8MQ_CLK_EXT3 6 -#define IMX8MQ_CLK_EXT4 7 - -/* ANAMIX PLL clocks */ -/* FRAC PLLs */ -/* ARM PLL */ -#define IMX8MQ_ARM_PLL_REF_SEL 8 -#define IMX8MQ_ARM_PLL_REF_DIV 9 -#define IMX8MQ_ARM_PLL 10 -#define IMX8MQ_ARM_PLL_BYPASS 11 -#define IMX8MQ_ARM_PLL_OUT 12 - -/* GPU PLL */ -#define IMX8MQ_GPU_PLL_REF_SEL 13 -#define IMX8MQ_GPU_PLL_REF_DIV 14 -#define IMX8MQ_GPU_PLL 15 -#define IMX8MQ_GPU_PLL_BYPASS 16 -#define IMX8MQ_GPU_PLL_OUT 17 - -/* VPU PLL */ -#define IMX8MQ_VPU_PLL_REF_SEL 18 -#define IMX8MQ_VPU_PLL_REF_DIV 19 -#define IMX8MQ_VPU_PLL 20 -#define IMX8MQ_VPU_PLL_BYPASS 21 -#define IMX8MQ_VPU_PLL_OUT 22 - -/* AUDIO PLL1 */ -#define IMX8MQ_AUDIO_PLL1_REF_SEL 23 -#define IMX8MQ_AUDIO_PLL1_REF_DIV 24 -#define IMX8MQ_AUDIO_PLL1 25 -#define IMX8MQ_AUDIO_PLL1_BYPASS 26 -#define IMX8MQ_AUDIO_PLL1_OUT 27 - -/* AUDIO PLL2 */ -#define IMX8MQ_AUDIO_PLL2_REF_SEL 28 -#define IMX8MQ_AUDIO_PLL2_REF_DIV 29 -#define IMX8MQ_AUDIO_PLL2 30 -#define IMX8MQ_AUDIO_PLL2_BYPASS 31 -#define IMX8MQ_AUDIO_PLL2_OUT 32 - -/* VIDEO PLL1 */ -#define IMX8MQ_VIDEO_PLL1_REF_SEL 33 -#define IMX8MQ_VIDEO_PLL1_REF_DIV 34 -#define IMX8MQ_VIDEO_PLL1 35 -#define IMX8MQ_VIDEO_PLL1_BYPASS 36 -#define IMX8MQ_VIDEO_PLL1_OUT 37 - -/* SYS1 PLL */ -#define IMX8MQ_SYS1_PLL1_REF_SEL 38 -#define IMX8MQ_SYS1_PLL1_REF_DIV 39 -#define IMX8MQ_SYS1_PLL1 40 -#define IMX8MQ_SYS1_PLL1_OUT 41 -#define IMX8MQ_SYS1_PLL1_OUT_DIV 42 -#define IMX8MQ_SYS1_PLL2 43 -#define IMX8MQ_SYS1_PLL2_DIV 44 -#define IMX8MQ_SYS1_PLL2_OUT 45 - -/* SYS2 PLL */ -#define IMX8MQ_SYS2_PLL1_REF_SEL 46 -#define IMX8MQ_SYS2_PLL1_REF_DIV 47 -#define IMX8MQ_SYS2_PLL1 48 -#define IMX8MQ_SYS2_PLL1_OUT 49 -#define IMX8MQ_SYS2_PLL1_OUT_DIV 50 -#define IMX8MQ_SYS2_PLL2 51 -#define IMX8MQ_SYS2_PLL2_DIV 52 -#define IMX8MQ_SYS2_PLL2_OUT 53 - -/* SYS3 PLL */ -#define IMX8MQ_SYS3_PLL1_REF_SEL 54 -#define IMX8MQ_SYS3_PLL1_REF_DIV 55 -#define IMX8MQ_SYS3_PLL1 56 -#define IMX8MQ_SYS3_PLL1_OUT 57 -#define IMX8MQ_SYS3_PLL1_OUT_DIV 58 -#define IMX8MQ_SYS3_PLL2 59 -#define IMX8MQ_SYS3_PLL2_DIV 60 -#define IMX8MQ_SYS3_PLL2_OUT 61 - -/* DRAM PLL */ -#define IMX8MQ_DRAM_PLL1_REF_SEL 62 -#define IMX8MQ_DRAM_PLL1_REF_DIV 63 -#define IMX8MQ_DRAM_PLL1 64 -#define IMX8MQ_DRAM_PLL1_OUT 65 -#define IMX8MQ_DRAM_PLL1_OUT_DIV 66 -#define IMX8MQ_DRAM_PLL2 67 -#define IMX8MQ_DRAM_PLL2_DIV 68 -#define IMX8MQ_DRAM_PLL2_OUT 69 - -/* SYS PLL DIV */ -#define IMX8MQ_SYS1_PLL_40M 70 -#define IMX8MQ_SYS1_PLL_80M 71 -#define IMX8MQ_SYS1_PLL_100M 72 -#define IMX8MQ_SYS1_PLL_133M 73 -#define IMX8MQ_SYS1_PLL_160M 74 -#define IMX8MQ_SYS1_PLL_200M 75 -#define IMX8MQ_SYS1_PLL_266M 76 -#define IMX8MQ_SYS1_PLL_400M 77 -#define IMX8MQ_SYS1_PLL_800M 78 - -#define IMX8MQ_SYS2_PLL_50M 79 -#define IMX8MQ_SYS2_PLL_100M 80 -#define IMX8MQ_SYS2_PLL_125M 81 -#define IMX8MQ_SYS2_PLL_166M 82 -#define IMX8MQ_SYS2_PLL_200M 83 -#define IMX8MQ_SYS2_PLL_250M 84 -#define IMX8MQ_SYS2_PLL_333M 85 -#define IMX8MQ_SYS2_PLL_500M 86 -#define IMX8MQ_SYS2_PLL_1000M 87 - -/* CCM ROOT clocks */ -/* A53 */ -#define IMX8MQ_CLK_A53_SRC 88 -#define IMX8MQ_CLK_A53_CG 89 -#define IMX8MQ_CLK_A53_DIV 90 -/* M4 */ -#define IMX8MQ_CLK_M4_SRC 91 -#define IMX8MQ_CLK_M4_CG 92 -#define IMX8MQ_CLK_M4_DIV 93 -/* VPU */ -#define IMX8MQ_CLK_VPU_SRC 94 -#define IMX8MQ_CLK_VPU_CG 95 -#define IMX8MQ_CLK_VPU_DIV 96 -/* GPU CORE */ -#define IMX8MQ_CLK_GPU_CORE_SRC 97 -#define IMX8MQ_CLK_GPU_CORE_CG 98 -#define IMX8MQ_CLK_GPU_CORE_DIV 99 -/* GPU SHADER */ -#define IMX8MQ_CLK_GPU_SHADER_SRC 100 -#define IMX8MQ_CLK_GPU_SHADER_CG 101 -#define IMX8MQ_CLK_GPU_SHADER_DIV 102 - -/* BUS TYPE */ -/* MAIN AXI */ -#define IMX8MQ_CLK_MAIN_AXI 103 -/* ENET AXI */ -#define IMX8MQ_CLK_ENET_AXI 104 -/* NAND_USDHC_BUS */ -#define IMX8MQ_CLK_NAND_USDHC_BUS 105 -/* VPU BUS */ -#define IMX8MQ_CLK_VPU_BUS 106 -/* DISP_AXI */ -#define IMX8MQ_CLK_DISP_AXI 107 -/* DISP APB */ -#define IMX8MQ_CLK_DISP_APB 108 -/* DISP RTRM */ -#define IMX8MQ_CLK_DISP_RTRM 109 -/* USB_BUS */ -#define IMX8MQ_CLK_USB_BUS 110 -/* GPU_AXI */ -#define IMX8MQ_CLK_GPU_AXI 111 -/* GPU_AHB */ -#define IMX8MQ_CLK_GPU_AHB 112 -/* NOC */ -#define IMX8MQ_CLK_NOC 113 -/* NOC_APB */ -#define IMX8MQ_CLK_NOC_APB 115 - -/* AHB */ -#define IMX8MQ_CLK_AHB 116 -/* AUDIO AHB */ -#define IMX8MQ_CLK_AUDIO_AHB 117 - -/* DRAM_ALT */ -#define IMX8MQ_CLK_DRAM_ALT 118 -/* DRAM APB */ -#define IMX8MQ_CLK_DRAM_APB 119 -/* VPU_G1 */ -#define IMX8MQ_CLK_VPU_G1 120 -/* VPU_G2 */ -#define IMX8MQ_CLK_VPU_G2 121 -/* DISP_DTRC */ -#define IMX8MQ_CLK_DISP_DTRC 122 -/* DISP_DC8000 */ -#define IMX8MQ_CLK_DISP_DC8000 123 -/* PCIE_CTRL */ -#define IMX8MQ_CLK_PCIE1_CTRL 124 -/* PCIE_PHY */ -#define IMX8MQ_CLK_PCIE1_PHY 125 -/* PCIE_AUX */ -#define IMX8MQ_CLK_PCIE1_AUX 126 -/* DC_PIXEL */ -#define IMX8MQ_CLK_DC_PIXEL 127 -/* LCDIF_PIXEL */ -#define IMX8MQ_CLK_LCDIF_PIXEL 128 -/* SAI1~6 */ -#define IMX8MQ_CLK_SAI1 129 - -#define IMX8MQ_CLK_SAI2 130 - -#define IMX8MQ_CLK_SAI3 131 - -#define IMX8MQ_CLK_SAI4 132 - -#define IMX8MQ_CLK_SAI5 133 - -#define IMX8MQ_CLK_SAI6 134 -/* SPDIF1 */ -#define IMX8MQ_CLK_SPDIF1 135 -/* SPDIF2 */ -#define IMX8MQ_CLK_SPDIF2 136 -/* ENET_REF */ -#define IMX8MQ_CLK_ENET_REF 137 -/* ENET_TIMER */ -#define IMX8MQ_CLK_ENET_TIMER 138 -/* ENET_PHY */ -#define IMX8MQ_CLK_ENET_PHY_REF 139 -/* NAND */ -#define IMX8MQ_CLK_NAND 140 -/* QSPI */ -#define IMX8MQ_CLK_QSPI 141 -/* USDHC1 */ -#define IMX8MQ_CLK_USDHC1 142 -/* USDHC2 */ -#define IMX8MQ_CLK_USDHC2 143 -/* I2C1 */ -#define IMX8MQ_CLK_I2C1 144 -/* I2C2 */ -#define IMX8MQ_CLK_I2C2 145 -/* I2C3 */ -#define IMX8MQ_CLK_I2C3 146 -/* I2C4 */ -#define IMX8MQ_CLK_I2C4 147 -/* UART1 */ -#define IMX8MQ_CLK_UART1 148 -/* UART2 */ -#define IMX8MQ_CLK_UART2 149 -/* UART3 */ -#define IMX8MQ_CLK_UART3 150 -/* UART4 */ -#define IMX8MQ_CLK_UART4 151 -/* USB_CORE_REF */ -#define IMX8MQ_CLK_USB_CORE_REF 152 -/* USB_PHY_REF */ -#define IMX8MQ_CLK_USB_PHY_REF 153 -/* ECSPI1 */ -#define IMX8MQ_CLK_ECSPI1 154 -/* ECSPI2 */ -#define IMX8MQ_CLK_ECSPI2 155 -/* PWM1 */ -#define IMX8MQ_CLK_PWM1 156 -/* PWM2 */ -#define IMX8MQ_CLK_PWM2 157 -/* PWM3 */ -#define IMX8MQ_CLK_PWM3 158 -/* PWM4 */ -#define IMX8MQ_CLK_PWM4 159 -/* GPT1 */ -#define IMX8MQ_CLK_GPT1 160 -/* WDOG */ -#define IMX8MQ_CLK_WDOG 161 -/* WRCLK */ -#define IMX8MQ_CLK_WRCLK 162 -/* DSI_CORE */ -#define IMX8MQ_CLK_DSI_CORE 163 -/* DSI_PHY */ -#define IMX8MQ_CLK_DSI_PHY_REF 164 -/* DSI_DBI */ -#define IMX8MQ_CLK_DSI_DBI 165 -/*DSI_ESC */ -#define IMX8MQ_CLK_DSI_ESC 166 -/* CSI1_CORE */ -#define IMX8MQ_CLK_CSI1_CORE 167 -/* CSI1_PHY */ -#define IMX8MQ_CLK_CSI1_PHY_REF 168 -/* CSI_ESC */ -#define IMX8MQ_CLK_CSI1_ESC 169 -/* CSI2_CORE */ -#define IMX8MQ_CLK_CSI2_CORE 170 -/* CSI2_PHY */ -#define IMX8MQ_CLK_CSI2_PHY_REF 171 -/* CSI2_ESC */ -#define IMX8MQ_CLK_CSI2_ESC 172 -/* PCIE2_CTRL */ -#define IMX8MQ_CLK_PCIE2_CTRL 173 -/* PCIE2_PHY */ -#define IMX8MQ_CLK_PCIE2_PHY 174 -/* PCIE2_AUX */ -#define IMX8MQ_CLK_PCIE2_AUX 175 -/* ECSPI3 */ -#define IMX8MQ_CLK_ECSPI3 176 - -/* CCGR clocks */ -#define IMX8MQ_CLK_A53_ROOT 177 -#define IMX8MQ_CLK_DRAM_ROOT 178 -#define IMX8MQ_CLK_ECSPI1_ROOT 179 -#define IMX8MQ_CLK_ECSPI2_ROOT 180 -#define IMX8MQ_CLK_ECSPI3_ROOT 181 -#define IMX8MQ_CLK_ENET1_ROOT 182 -#define IMX8MQ_CLK_GPT1_ROOT 183 -#define IMX8MQ_CLK_I2C1_ROOT 184 -#define IMX8MQ_CLK_I2C2_ROOT 185 -#define IMX8MQ_CLK_I2C3_ROOT 186 -#define IMX8MQ_CLK_I2C4_ROOT 187 -#define IMX8MQ_CLK_M4_ROOT 188 -#define IMX8MQ_CLK_PCIE1_ROOT 189 -#define IMX8MQ_CLK_PCIE2_ROOT 190 -#define IMX8MQ_CLK_PWM1_ROOT 191 -#define IMX8MQ_CLK_PWM2_ROOT 192 -#define IMX8MQ_CLK_PWM3_ROOT 193 -#define IMX8MQ_CLK_PWM4_ROOT 194 -#define IMX8MQ_CLK_QSPI_ROOT 195 -#define IMX8MQ_CLK_SAI1_ROOT 196 -#define IMX8MQ_CLK_SAI2_ROOT 197 -#define IMX8MQ_CLK_SAI3_ROOT 198 -#define IMX8MQ_CLK_SAI4_ROOT 199 -#define IMX8MQ_CLK_SAI5_ROOT 200 -#define IMX8MQ_CLK_SAI6_ROOT 201 -#define IMX8MQ_CLK_UART1_ROOT 202 -#define IMX8MQ_CLK_UART2_ROOT 203 -#define IMX8MQ_CLK_UART3_ROOT 204 -#define IMX8MQ_CLK_UART4_ROOT 205 -#define IMX8MQ_CLK_USB1_CTRL_ROOT 206 -#define IMX8MQ_CLK_USB2_CTRL_ROOT 207 -#define IMX8MQ_CLK_USB1_PHY_ROOT 208 -#define IMX8MQ_CLK_USB2_PHY_ROOT 209 -#define IMX8MQ_CLK_USDHC1_ROOT 210 -#define IMX8MQ_CLK_USDHC2_ROOT 211 -#define IMX8MQ_CLK_WDOG1_ROOT 212 -#define IMX8MQ_CLK_WDOG2_ROOT 213 -#define IMX8MQ_CLK_WDOG3_ROOT 214 -#define IMX8MQ_CLK_GPU_ROOT 215 -#define IMX8MQ_CLK_HEVC_ROOT 216 -#define IMX8MQ_CLK_AVC_ROOT 217 -#define IMX8MQ_CLK_VP9_ROOT 218 -#define IMX8MQ_CLK_HEVC_INTER_ROOT 219 -#define IMX8MQ_CLK_DISP_ROOT 220 -#define IMX8MQ_CLK_HDMI_ROOT 221 -#define IMX8MQ_CLK_HDMI_PHY_ROOT 222 -#define IMX8MQ_CLK_VPU_DEC_ROOT 223 -#define IMX8MQ_CLK_CSI1_ROOT 224 -#define IMX8MQ_CLK_CSI2_ROOT 225 -#define IMX8MQ_CLK_RAWNAND_ROOT 226 -#define IMX8MQ_CLK_SDMA1_ROOT 227 -#define IMX8MQ_CLK_SDMA2_ROOT 228 -#define IMX8MQ_CLK_VPU_G1_ROOT 229 -#define IMX8MQ_CLK_VPU_G2_ROOT 230 - -/* SCCG PLL GATE */ -#define IMX8MQ_SYS1_PLL_OUT 231 -#define IMX8MQ_SYS2_PLL_OUT 232 -#define IMX8MQ_SYS3_PLL_OUT 233 -#define IMX8MQ_DRAM_PLL_OUT 234 - -#define IMX8MQ_GPT_3M_CLK 235 - -#define IMX8MQ_CLK_IPG_ROOT 236 -#define IMX8MQ_CLK_IPG_AUDIO_ROOT 237 -#define IMX8MQ_CLK_SAI1_IPG 238 -#define IMX8MQ_CLK_SAI2_IPG 239 -#define IMX8MQ_CLK_SAI3_IPG 240 -#define IMX8MQ_CLK_SAI4_IPG 241 -#define IMX8MQ_CLK_SAI5_IPG 242 -#define IMX8MQ_CLK_SAI6_IPG 243 - -/* DSI AHB/IPG clocks */ -/* rxesc clock */ -#define IMX8MQ_CLK_DSI_AHB 244 -/* txesc clock */ -#define IMX8MQ_CLK_DSI_IPG_DIV 245 - -#define IMX8MQ_CLK_TMU_ROOT 246 - -/* Display root clocks */ -#define IMX8MQ_CLK_DISP_AXI_ROOT 247 -#define IMX8MQ_CLK_DISP_APB_ROOT 248 -#define IMX8MQ_CLK_DISP_RTRM_ROOT 249 - -#define IMX8MQ_CLK_OCOTP_ROOT 250 - -#define IMX8MQ_CLK_DRAM_ALT_ROOT 251 -#define IMX8MQ_CLK_DRAM_CORE 252 - -#define IMX8MQ_CLK_MU_ROOT 253 -#define IMX8MQ_VIDEO2_PLL_OUT 254 - -#define IMX8MQ_CLK_CLKO2 255 - -#define IMX8MQ_CLK_NAND_USDHC_BUS_RAWNAND_CLK 256 - -#define IMX8MQ_CLK_CLKO1 257 -#define IMX8MQ_CLK_ARM 258 - -#define IMX8MQ_CLK_GPIO1_ROOT 259 -#define IMX8MQ_CLK_GPIO2_ROOT 260 -#define IMX8MQ_CLK_GPIO3_ROOT 261 -#define IMX8MQ_CLK_GPIO4_ROOT 262 -#define IMX8MQ_CLK_GPIO5_ROOT 263 - -#define IMX8MQ_CLK_SNVS_ROOT 264 -#define IMX8MQ_CLK_GIC 265 - -#define IMX8MQ_VIDEO2_PLL1_REF_SEL 266 - -#define IMX8MQ_SYS1_PLL_40M_CG 267 -#define IMX8MQ_SYS1_PLL_80M_CG 268 -#define IMX8MQ_SYS1_PLL_100M_CG 269 -#define IMX8MQ_SYS1_PLL_133M_CG 270 -#define IMX8MQ_SYS1_PLL_160M_CG 271 -#define IMX8MQ_SYS1_PLL_200M_CG 272 -#define IMX8MQ_SYS1_PLL_266M_CG 273 -#define IMX8MQ_SYS1_PLL_400M_CG 274 -#define IMX8MQ_SYS1_PLL_800M_CG 275 -#define IMX8MQ_SYS2_PLL_50M_CG 276 -#define IMX8MQ_SYS2_PLL_100M_CG 277 -#define IMX8MQ_SYS2_PLL_125M_CG 278 -#define IMX8MQ_SYS2_PLL_166M_CG 279 -#define IMX8MQ_SYS2_PLL_200M_CG 280 -#define IMX8MQ_SYS2_PLL_250M_CG 281 -#define IMX8MQ_SYS2_PLL_333M_CG 282 -#define IMX8MQ_SYS2_PLL_500M_CG 283 -#define IMX8MQ_SYS2_PLL_1000M_CG 284 - -#define IMX8MQ_CLK_END 285 - -#endif /* __DT_BINDINGS_CLOCK_IMX8MQ_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/ingenic,tcu.h b/sys/gnu/dts/include/dt-bindings/clock/ingenic,tcu.h deleted file mode 100644 index d569650a794..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/ingenic,tcu.h +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides clock numbers for the ingenic,tcu DT binding. - */ - -#ifndef __DT_BINDINGS_CLOCK_INGENIC_TCU_H__ -#define __DT_BINDINGS_CLOCK_INGENIC_TCU_H__ - -#define TCU_CLK_TIMER0 0 -#define TCU_CLK_TIMER1 1 -#define TCU_CLK_TIMER2 2 -#define TCU_CLK_TIMER3 3 -#define TCU_CLK_TIMER4 4 -#define TCU_CLK_TIMER5 5 -#define TCU_CLK_TIMER6 6 -#define TCU_CLK_TIMER7 7 -#define TCU_CLK_WDT 8 -#define TCU_CLK_OST 9 - -#endif /* __DT_BINDINGS_CLOCK_INGENIC_TCU_H__ */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/jz4725b-cgu.h b/sys/gnu/dts/include/dt-bindings/clock/jz4725b-cgu.h deleted file mode 100644 index 31f1ab0fe42..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/jz4725b-cgu.h +++ /dev/null @@ -1,36 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides clock numbers for the ingenic,jz4725b-cgu DT binding. - */ - -#ifndef __DT_BINDINGS_CLOCK_JZ4725B_CGU_H__ -#define __DT_BINDINGS_CLOCK_JZ4725B_CGU_H__ - -#define JZ4725B_CLK_EXT 0 -#define JZ4725B_CLK_OSC32K 1 -#define JZ4725B_CLK_PLL 2 -#define JZ4725B_CLK_PLL_HALF 3 -#define JZ4725B_CLK_CCLK 4 -#define JZ4725B_CLK_HCLK 5 -#define JZ4725B_CLK_PCLK 6 -#define JZ4725B_CLK_MCLK 7 -#define JZ4725B_CLK_IPU 8 -#define JZ4725B_CLK_LCD 9 -#define JZ4725B_CLK_I2S 10 -#define JZ4725B_CLK_SPI 11 -#define JZ4725B_CLK_MMC_MUX 12 -#define JZ4725B_CLK_UDC 13 -#define JZ4725B_CLK_UART 14 -#define JZ4725B_CLK_DMA 15 -#define JZ4725B_CLK_ADC 16 -#define JZ4725B_CLK_I2C 17 -#define JZ4725B_CLK_AIC 18 -#define JZ4725B_CLK_MMC0 19 -#define JZ4725B_CLK_MMC1 20 -#define JZ4725B_CLK_BCH 21 -#define JZ4725B_CLK_TCU 22 -#define JZ4725B_CLK_EXT512 23 -#define JZ4725B_CLK_RTC 24 -#define JZ4725B_CLK_UDC_PHY 25 - -#endif /* __DT_BINDINGS_CLOCK_JZ4725B_CGU_H__ */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/jz4740-cgu.h b/sys/gnu/dts/include/dt-bindings/clock/jz4740-cgu.h deleted file mode 100644 index e82d7702858..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/jz4740-cgu.h +++ /dev/null @@ -1,39 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides clock numbers for the ingenic,jz4740-cgu DT binding. - * - * They are roughly ordered as: - * - external clocks - * - PLLs - * - muxes/dividers in the order they appear in the jz4740 programmers manual - * - gates in order of their bit in the CLKGR* registers - */ - -#ifndef __DT_BINDINGS_CLOCK_JZ4740_CGU_H__ -#define __DT_BINDINGS_CLOCK_JZ4740_CGU_H__ - -#define JZ4740_CLK_EXT 0 -#define JZ4740_CLK_RTC 1 -#define JZ4740_CLK_PLL 2 -#define JZ4740_CLK_PLL_HALF 3 -#define JZ4740_CLK_CCLK 4 -#define JZ4740_CLK_HCLK 5 -#define JZ4740_CLK_PCLK 6 -#define JZ4740_CLK_MCLK 7 -#define JZ4740_CLK_LCD 8 -#define JZ4740_CLK_LCD_PCLK 9 -#define JZ4740_CLK_I2S 10 -#define JZ4740_CLK_SPI 11 -#define JZ4740_CLK_MMC 12 -#define JZ4740_CLK_UHC 13 -#define JZ4740_CLK_UDC 14 -#define JZ4740_CLK_UART0 15 -#define JZ4740_CLK_UART1 16 -#define JZ4740_CLK_DMA 17 -#define JZ4740_CLK_IPU 18 -#define JZ4740_CLK_ADC 19 -#define JZ4740_CLK_I2C 20 -#define JZ4740_CLK_AIC 21 -#define JZ4740_CLK_TCU 22 - -#endif /* __DT_BINDINGS_CLOCK_JZ4740_CGU_H__ */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/jz4770-cgu.h b/sys/gnu/dts/include/dt-bindings/clock/jz4770-cgu.h deleted file mode 100644 index d68a7695a1f..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/jz4770-cgu.h +++ /dev/null @@ -1,58 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides clock numbers for the ingenic,jz4770-cgu DT binding. - */ - -#ifndef __DT_BINDINGS_CLOCK_JZ4770_CGU_H__ -#define __DT_BINDINGS_CLOCK_JZ4770_CGU_H__ - -#define JZ4770_CLK_EXT 0 -#define JZ4770_CLK_OSC32K 1 -#define JZ4770_CLK_PLL0 2 -#define JZ4770_CLK_PLL1 3 -#define JZ4770_CLK_CCLK 4 -#define JZ4770_CLK_H0CLK 5 -#define JZ4770_CLK_H1CLK 6 -#define JZ4770_CLK_H2CLK 7 -#define JZ4770_CLK_C1CLK 8 -#define JZ4770_CLK_PCLK 9 -#define JZ4770_CLK_MMC0_MUX 10 -#define JZ4770_CLK_MMC0 11 -#define JZ4770_CLK_MMC1_MUX 12 -#define JZ4770_CLK_MMC1 13 -#define JZ4770_CLK_MMC2_MUX 14 -#define JZ4770_CLK_MMC2 15 -#define JZ4770_CLK_CIM 16 -#define JZ4770_CLK_UHC 17 -#define JZ4770_CLK_GPU 18 -#define JZ4770_CLK_BCH 19 -#define JZ4770_CLK_LPCLK_MUX 20 -#define JZ4770_CLK_GPS 21 -#define JZ4770_CLK_SSI_MUX 22 -#define JZ4770_CLK_PCM_MUX 23 -#define JZ4770_CLK_I2S 24 -#define JZ4770_CLK_OTG 25 -#define JZ4770_CLK_SSI0 26 -#define JZ4770_CLK_SSI1 27 -#define JZ4770_CLK_SSI2 28 -#define JZ4770_CLK_PCM0 29 -#define JZ4770_CLK_PCM1 30 -#define JZ4770_CLK_DMA 31 -#define JZ4770_CLK_I2C0 32 -#define JZ4770_CLK_I2C1 33 -#define JZ4770_CLK_I2C2 34 -#define JZ4770_CLK_UART0 35 -#define JZ4770_CLK_UART1 36 -#define JZ4770_CLK_UART2 37 -#define JZ4770_CLK_UART3 38 -#define JZ4770_CLK_IPU 39 -#define JZ4770_CLK_ADC 40 -#define JZ4770_CLK_AIC 41 -#define JZ4770_CLK_AUX 42 -#define JZ4770_CLK_VPU 43 -#define JZ4770_CLK_UHC_PHY 44 -#define JZ4770_CLK_OTG_PHY 45 -#define JZ4770_CLK_EXT512 46 -#define JZ4770_CLK_RTC 47 - -#endif /* __DT_BINDINGS_CLOCK_JZ4770_CGU_H__ */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/jz4780-cgu.h b/sys/gnu/dts/include/dt-bindings/clock/jz4780-cgu.h deleted file mode 100644 index 1859ce53ee3..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/jz4780-cgu.h +++ /dev/null @@ -1,89 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides clock numbers for the ingenic,jz4780-cgu DT binding. - * - * They are roughly ordered as: - * - external clocks - * - PLLs - * - muxes/dividers in the order they appear in the jz4780 programmers manual - * - gates in order of their bit in the CLKGR* registers - */ - -#ifndef __DT_BINDINGS_CLOCK_JZ4780_CGU_H__ -#define __DT_BINDINGS_CLOCK_JZ4780_CGU_H__ - -#define JZ4780_CLK_EXCLK 0 -#define JZ4780_CLK_RTCLK 1 -#define JZ4780_CLK_APLL 2 -#define JZ4780_CLK_MPLL 3 -#define JZ4780_CLK_EPLL 4 -#define JZ4780_CLK_VPLL 5 -#define JZ4780_CLK_OTGPHY 6 -#define JZ4780_CLK_SCLKA 7 -#define JZ4780_CLK_CPUMUX 8 -#define JZ4780_CLK_CPU 9 -#define JZ4780_CLK_L2CACHE 10 -#define JZ4780_CLK_AHB0 11 -#define JZ4780_CLK_AHB2PMUX 12 -#define JZ4780_CLK_AHB2 13 -#define JZ4780_CLK_PCLK 14 -#define JZ4780_CLK_DDR 15 -#define JZ4780_CLK_VPU 16 -#define JZ4780_CLK_I2SPLL 17 -#define JZ4780_CLK_I2S 18 -#define JZ4780_CLK_LCD0PIXCLK 19 -#define JZ4780_CLK_LCD1PIXCLK 20 -#define JZ4780_CLK_MSCMUX 21 -#define JZ4780_CLK_MSC0 22 -#define JZ4780_CLK_MSC1 23 -#define JZ4780_CLK_MSC2 24 -#define JZ4780_CLK_UHC 25 -#define JZ4780_CLK_SSIPLL 26 -#define JZ4780_CLK_SSI 27 -#define JZ4780_CLK_CIMMCLK 28 -#define JZ4780_CLK_PCMPLL 29 -#define JZ4780_CLK_PCM 30 -#define JZ4780_CLK_GPU 31 -#define JZ4780_CLK_HDMI 32 -#define JZ4780_CLK_BCH 33 -#define JZ4780_CLK_NEMC 34 -#define JZ4780_CLK_OTG0 35 -#define JZ4780_CLK_SSI0 36 -#define JZ4780_CLK_SMB0 37 -#define JZ4780_CLK_SMB1 38 -#define JZ4780_CLK_SCC 39 -#define JZ4780_CLK_AIC 40 -#define JZ4780_CLK_TSSI0 41 -#define JZ4780_CLK_OWI 42 -#define JZ4780_CLK_KBC 43 -#define JZ4780_CLK_SADC 44 -#define JZ4780_CLK_UART0 45 -#define JZ4780_CLK_UART1 46 -#define JZ4780_CLK_UART2 47 -#define JZ4780_CLK_UART3 48 -#define JZ4780_CLK_SSI1 49 -#define JZ4780_CLK_SSI2 50 -#define JZ4780_CLK_PDMA 51 -#define JZ4780_CLK_GPS 52 -#define JZ4780_CLK_MAC 53 -#define JZ4780_CLK_SMB2 54 -#define JZ4780_CLK_CIM 55 -#define JZ4780_CLK_LCD 56 -#define JZ4780_CLK_TVE 57 -#define JZ4780_CLK_IPU 58 -#define JZ4780_CLK_DDR0 59 -#define JZ4780_CLK_DDR1 60 -#define JZ4780_CLK_SMB3 61 -#define JZ4780_CLK_TSSI1 62 -#define JZ4780_CLK_COMPRESS 63 -#define JZ4780_CLK_AIC1 64 -#define JZ4780_CLK_GPVLC 65 -#define JZ4780_CLK_OTG1 66 -#define JZ4780_CLK_UART4 67 -#define JZ4780_CLK_AHBMON 68 -#define JZ4780_CLK_SMB4 69 -#define JZ4780_CLK_DES 70 -#define JZ4780_CLK_X2D 71 -#define JZ4780_CLK_CORE1 72 - -#endif /* __DT_BINDINGS_CLOCK_JZ4780_CGU_H__ */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/lpc18xx-ccu.h b/sys/gnu/dts/include/dt-bindings/clock/lpc18xx-ccu.h deleted file mode 100644 index bbfe00b6ab7..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/lpc18xx-ccu.h +++ /dev/null @@ -1,74 +0,0 @@ -/* - * Copyright (c) 2015 Joachim Eastwood - * - * This code is released using a dual license strategy: BSD/GPL - * You can choose the licence that better fits your requirements. - * - * Released under the terms of 3-clause BSD License - * Released under the terms of GNU General Public License Version 2.0 - * - */ - -/* Clock Control Unit 1 (CCU1) clock offsets */ -#define CLK_APB3_BUS 0x100 -#define CLK_APB3_I2C1 0x108 -#define CLK_APB3_DAC 0x110 -#define CLK_APB3_ADC0 0x118 -#define CLK_APB3_ADC1 0x120 -#define CLK_APB3_CAN0 0x128 -#define CLK_APB1_BUS 0x200 -#define CLK_APB1_MOTOCON_PWM 0x208 -#define CLK_APB1_I2C0 0x210 -#define CLK_APB1_I2S 0x218 -#define CLK_APB1_CAN1 0x220 -#define CLK_SPIFI 0x300 -#define CLK_CPU_BUS 0x400 -#define CLK_CPU_SPIFI 0x408 -#define CLK_CPU_GPIO 0x410 -#define CLK_CPU_LCD 0x418 -#define CLK_CPU_ETHERNET 0x420 -#define CLK_CPU_USB0 0x428 -#define CLK_CPU_EMC 0x430 -#define CLK_CPU_SDIO 0x438 -#define CLK_CPU_DMA 0x440 -#define CLK_CPU_CORE 0x448 -#define CLK_CPU_SCT 0x468 -#define CLK_CPU_USB1 0x470 -#define CLK_CPU_EMCDIV 0x478 -#define CLK_CPU_FLASHA 0x480 -#define CLK_CPU_FLASHB 0x488 -#define CLK_CPU_M0APP 0x490 -#define CLK_CPU_ADCHS 0x498 -#define CLK_CPU_EEPROM 0x4a0 -#define CLK_CPU_WWDT 0x500 -#define CLK_CPU_UART0 0x508 -#define CLK_CPU_UART1 0x510 -#define CLK_CPU_SSP0 0x518 -#define CLK_CPU_TIMER0 0x520 -#define CLK_CPU_TIMER1 0x528 -#define CLK_CPU_SCU 0x530 -#define CLK_CPU_CREG 0x538 -#define CLK_CPU_RITIMER 0x600 -#define CLK_CPU_UART2 0x608 -#define CLK_CPU_UART3 0x610 -#define CLK_CPU_TIMER2 0x618 -#define CLK_CPU_TIMER3 0x620 -#define CLK_CPU_SSP1 0x628 -#define CLK_CPU_QEI 0x630 -#define CLK_PERIPH_BUS 0x700 -#define CLK_PERIPH_CORE 0x710 -#define CLK_PERIPH_SGPIO 0x718 -#define CLK_USB0 0x800 -#define CLK_USB1 0x900 -#define CLK_SPI 0xA00 -#define CLK_ADCHS 0xB00 - -/* Clock Control Unit 2 (CCU2) clock offsets */ -#define CLK_AUDIO 0x100 -#define CLK_APB2_UART3 0x200 -#define CLK_APB2_UART2 0x300 -#define CLK_APB0_UART1 0x400 -#define CLK_APB0_UART0 0x500 -#define CLK_APB2_SSP1 0x600 -#define CLK_APB0_SSP0 0x700 -#define CLK_SDIO 0x800 diff --git a/sys/gnu/dts/include/dt-bindings/clock/lpc18xx-cgu.h b/sys/gnu/dts/include/dt-bindings/clock/lpc18xx-cgu.h deleted file mode 100644 index 6e57c6d2ca6..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/lpc18xx-cgu.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * Copyright (c) 2015 Joachim Eastwood - * - * This code is released using a dual license strategy: BSD/GPL - * You can choose the licence that better fits your requirements. - * - * Released under the terms of 3-clause BSD License - * Released under the terms of GNU General Public License Version 2.0 - * - */ - -/* LPC18xx/43xx base clock ids */ -#define BASE_SAFE_CLK 0 -#define BASE_USB0_CLK 1 -#define BASE_PERIPH_CLK 2 -#define BASE_USB1_CLK 3 -#define BASE_CPU_CLK 4 -#define BASE_SPIFI_CLK 5 -#define BASE_SPI_CLK 6 -#define BASE_PHY_RX_CLK 7 -#define BASE_PHY_TX_CLK 8 -#define BASE_APB1_CLK 9 -#define BASE_APB3_CLK 10 -#define BASE_LCD_CLK 11 -#define BASE_ADCHS_CLK 12 -#define BASE_SDIO_CLK 13 -#define BASE_SSP0_CLK 14 -#define BASE_SSP1_CLK 15 -#define BASE_UART0_CLK 16 -#define BASE_UART1_CLK 17 -#define BASE_UART2_CLK 18 -#define BASE_UART3_CLK 19 -#define BASE_OUT_CLK 20 -#define BASE_RES1_CLK 21 -#define BASE_RES2_CLK 22 -#define BASE_RES3_CLK 23 -#define BASE_RES4_CLK 24 -#define BASE_AUDIO_CLK 25 -#define BASE_CGU_OUT0_CLK 26 -#define BASE_CGU_OUT1_CLK 27 -#define BASE_CLK_MAX (BASE_CGU_OUT1_CLK + 1) diff --git a/sys/gnu/dts/include/dt-bindings/clock/lpc32xx-clock.h b/sys/gnu/dts/include/dt-bindings/clock/lpc32xx-clock.h deleted file mode 100644 index e624d3a5279..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/lpc32xx-clock.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * Copyright (c) 2015 Vladimir Zapolskiy - * - * This code is released using a dual license strategy: BSD/GPL - * You can choose the licence that better fits your requirements. - * - * Released under the terms of 3-clause BSD License - * Released under the terms of GNU General Public License Version 2.0 - * - */ - -#ifndef __DT_BINDINGS_LPC32XX_CLOCK_H -#define __DT_BINDINGS_LPC32XX_CLOCK_H - -/* LPC32XX System Control Block clocks */ -#define LPC32XX_CLK_RTC 1 -#define LPC32XX_CLK_DMA 2 -#define LPC32XX_CLK_MLC 3 -#define LPC32XX_CLK_SLC 4 -#define LPC32XX_CLK_LCD 5 -#define LPC32XX_CLK_MAC 6 -#define LPC32XX_CLK_SD 7 -#define LPC32XX_CLK_DDRAM 8 -#define LPC32XX_CLK_SSP0 9 -#define LPC32XX_CLK_SSP1 10 -#define LPC32XX_CLK_UART3 11 -#define LPC32XX_CLK_UART4 12 -#define LPC32XX_CLK_UART5 13 -#define LPC32XX_CLK_UART6 14 -#define LPC32XX_CLK_IRDA 15 -#define LPC32XX_CLK_I2C1 16 -#define LPC32XX_CLK_I2C2 17 -#define LPC32XX_CLK_TIMER0 18 -#define LPC32XX_CLK_TIMER1 19 -#define LPC32XX_CLK_TIMER2 20 -#define LPC32XX_CLK_TIMER3 21 -#define LPC32XX_CLK_TIMER4 22 -#define LPC32XX_CLK_TIMER5 23 -#define LPC32XX_CLK_WDOG 24 -#define LPC32XX_CLK_I2S0 25 -#define LPC32XX_CLK_I2S1 26 -#define LPC32XX_CLK_SPI1 27 -#define LPC32XX_CLK_SPI2 28 -#define LPC32XX_CLK_MCPWM 29 -#define LPC32XX_CLK_HSTIMER 30 -#define LPC32XX_CLK_KEY 31 -#define LPC32XX_CLK_PWM1 32 -#define LPC32XX_CLK_PWM2 33 -#define LPC32XX_CLK_ADC 34 -#define LPC32XX_CLK_HCLK_PLL 35 -#define LPC32XX_CLK_PERIPH 36 - -/* LPC32XX USB clocks */ -#define LPC32XX_USB_CLK_I2C 1 -#define LPC32XX_USB_CLK_DEVICE 2 -#define LPC32XX_USB_CLK_HOST 3 - -#endif /* __DT_BINDINGS_LPC32XX_CLOCK_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/lsi,axm5516-clks.h b/sys/gnu/dts/include/dt-bindings/clock/lsi,axm5516-clks.h deleted file mode 100644 index 050bbdab4f2..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/lsi,axm5516-clks.h +++ /dev/null @@ -1,33 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2014 LSI Corporation - */ - -#ifndef _DT_BINDINGS_CLK_AXM5516_H -#define _DT_BINDINGS_CLK_AXM5516_H - -#define AXXIA_CLK_FAB_PLL 0 -#define AXXIA_CLK_CPU_PLL 1 -#define AXXIA_CLK_SYS_PLL 2 -#define AXXIA_CLK_SM0_PLL 3 -#define AXXIA_CLK_SM1_PLL 4 -#define AXXIA_CLK_FAB_DIV 5 -#define AXXIA_CLK_SYS_DIV 6 -#define AXXIA_CLK_NRCP_DIV 7 -#define AXXIA_CLK_CPU0_DIV 8 -#define AXXIA_CLK_CPU1_DIV 9 -#define AXXIA_CLK_CPU2_DIV 10 -#define AXXIA_CLK_CPU3_DIV 11 -#define AXXIA_CLK_PER_DIV 12 -#define AXXIA_CLK_MMC_DIV 13 -#define AXXIA_CLK_FAB 14 -#define AXXIA_CLK_SYS 15 -#define AXXIA_CLK_NRCP 16 -#define AXXIA_CLK_CPU0 17 -#define AXXIA_CLK_CPU1 18 -#define AXXIA_CLK_CPU2 19 -#define AXXIA_CLK_CPU3 20 -#define AXXIA_CLK_PER 21 -#define AXXIA_CLK_MMC 22 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/marvell,mmp2.h b/sys/gnu/dts/include/dt-bindings/clock/marvell,mmp2.h deleted file mode 100644 index 4b1a7724f20..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/marvell,mmp2.h +++ /dev/null @@ -1,79 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __DTS_MARVELL_MMP2_CLOCK_H -#define __DTS_MARVELL_MMP2_CLOCK_H - -/* fixed clocks and plls */ -#define MMP2_CLK_CLK32 1 -#define MMP2_CLK_VCTCXO 2 -#define MMP2_CLK_PLL1 3 -#define MMP2_CLK_PLL1_2 8 -#define MMP2_CLK_PLL1_4 9 -#define MMP2_CLK_PLL1_8 10 -#define MMP2_CLK_PLL1_16 11 -#define MMP2_CLK_PLL1_3 12 -#define MMP2_CLK_PLL1_6 13 -#define MMP2_CLK_PLL1_12 14 -#define MMP2_CLK_PLL1_20 15 -#define MMP2_CLK_PLL2 16 -#define MMP2_CLK_PLL2_2 17 -#define MMP2_CLK_PLL2_4 18 -#define MMP2_CLK_PLL2_8 19 -#define MMP2_CLK_PLL2_16 20 -#define MMP2_CLK_PLL2_3 21 -#define MMP2_CLK_PLL2_6 22 -#define MMP2_CLK_PLL2_12 23 -#define MMP2_CLK_VCTCXO_2 24 -#define MMP2_CLK_VCTCXO_4 25 -#define MMP2_CLK_UART_PLL 26 -#define MMP2_CLK_USB_PLL 27 - -/* apb periphrals */ -#define MMP2_CLK_TWSI0 60 -#define MMP2_CLK_TWSI1 61 -#define MMP2_CLK_TWSI2 62 -#define MMP2_CLK_TWSI3 63 -#define MMP2_CLK_TWSI4 64 -#define MMP2_CLK_TWSI5 65 -#define MMP2_CLK_GPIO 66 -#define MMP2_CLK_KPC 67 -#define MMP2_CLK_RTC 68 -#define MMP2_CLK_PWM0 69 -#define MMP2_CLK_PWM1 70 -#define MMP2_CLK_PWM2 71 -#define MMP2_CLK_PWM3 72 -#define MMP2_CLK_UART0 73 -#define MMP2_CLK_UART1 74 -#define MMP2_CLK_UART2 75 -#define MMP2_CLK_UART3 76 -#define MMP2_CLK_SSP0 77 -#define MMP2_CLK_SSP1 78 -#define MMP2_CLK_SSP2 79 -#define MMP2_CLK_SSP3 80 -#define MMP2_CLK_TIMER 81 - -/* axi periphrals */ -#define MMP2_CLK_SDH0 101 -#define MMP2_CLK_SDH1 102 -#define MMP2_CLK_SDH2 103 -#define MMP2_CLK_SDH3 104 -#define MMP2_CLK_USB 105 -#define MMP2_CLK_DISP0 106 -#define MMP2_CLK_DISP0_MUX 107 -#define MMP2_CLK_DISP0_SPHY 108 -#define MMP2_CLK_DISP1 109 -#define MMP2_CLK_DISP1_MUX 110 -#define MMP2_CLK_CCIC_ARBITER 111 -#define MMP2_CLK_CCIC0 112 -#define MMP2_CLK_CCIC0_MIX 113 -#define MMP2_CLK_CCIC0_PHY 114 -#define MMP2_CLK_CCIC0_SPHY 115 -#define MMP2_CLK_CCIC1 116 -#define MMP2_CLK_CCIC1_MIX 117 -#define MMP2_CLK_CCIC1_PHY 118 -#define MMP2_CLK_CCIC1_SPHY 119 -#define MMP2_CLK_DISP0_LCDC 120 -#define MMP2_CLK_USBHSIC0 121 -#define MMP2_CLK_USBHSIC1 122 - -#define MMP2_NR_CLKS 200 -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/marvell,pxa168.h b/sys/gnu/dts/include/dt-bindings/clock/marvell,pxa168.h deleted file mode 100644 index caf90436b84..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/marvell,pxa168.h +++ /dev/null @@ -1,61 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __DTS_MARVELL_PXA168_CLOCK_H -#define __DTS_MARVELL_PXA168_CLOCK_H - -/* fixed clocks and plls */ -#define PXA168_CLK_CLK32 1 -#define PXA168_CLK_VCTCXO 2 -#define PXA168_CLK_PLL1 3 -#define PXA168_CLK_PLL1_2 8 -#define PXA168_CLK_PLL1_4 9 -#define PXA168_CLK_PLL1_8 10 -#define PXA168_CLK_PLL1_16 11 -#define PXA168_CLK_PLL1_6 12 -#define PXA168_CLK_PLL1_12 13 -#define PXA168_CLK_PLL1_24 14 -#define PXA168_CLK_PLL1_48 15 -#define PXA168_CLK_PLL1_96 16 -#define PXA168_CLK_PLL1_13 17 -#define PXA168_CLK_PLL1_13_1_5 18 -#define PXA168_CLK_PLL1_2_1_5 19 -#define PXA168_CLK_PLL1_3_16 20 -#define PXA168_CLK_PLL1_192 21 -#define PXA168_CLK_UART_PLL 27 -#define PXA168_CLK_USB_PLL 28 - -/* apb periphrals */ -#define PXA168_CLK_TWSI0 60 -#define PXA168_CLK_TWSI1 61 -#define PXA168_CLK_TWSI2 62 -#define PXA168_CLK_TWSI3 63 -#define PXA168_CLK_GPIO 64 -#define PXA168_CLK_KPC 65 -#define PXA168_CLK_RTC 66 -#define PXA168_CLK_PWM0 67 -#define PXA168_CLK_PWM1 68 -#define PXA168_CLK_PWM2 69 -#define PXA168_CLK_PWM3 70 -#define PXA168_CLK_UART0 71 -#define PXA168_CLK_UART1 72 -#define PXA168_CLK_UART2 73 -#define PXA168_CLK_SSP0 74 -#define PXA168_CLK_SSP1 75 -#define PXA168_CLK_SSP2 76 -#define PXA168_CLK_SSP3 77 -#define PXA168_CLK_SSP4 78 -#define PXA168_CLK_TIMER 79 - -/* axi periphrals */ -#define PXA168_CLK_DFC 100 -#define PXA168_CLK_SDH0 101 -#define PXA168_CLK_SDH1 102 -#define PXA168_CLK_SDH2 103 -#define PXA168_CLK_USB 104 -#define PXA168_CLK_SPH 105 -#define PXA168_CLK_DISP0 106 -#define PXA168_CLK_CCIC0 107 -#define PXA168_CLK_CCIC0_PHY 108 -#define PXA168_CLK_CCIC0_SPHY 109 - -#define PXA168_NR_CLKS 200 -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/marvell,pxa1928.h b/sys/gnu/dts/include/dt-bindings/clock/marvell,pxa1928.h deleted file mode 100644 index 5dca4820297..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/marvell,pxa1928.h +++ /dev/null @@ -1,58 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __DTS_MARVELL_PXA1928_CLOCK_H -#define __DTS_MARVELL_PXA1928_CLOCK_H - -/* - * Clock ID values here correspond to the control register offset/4. - */ - -/* apb peripherals */ -#define PXA1928_CLK_RTC 0x00 -#define PXA1928_CLK_TWSI0 0x01 -#define PXA1928_CLK_TWSI1 0x02 -#define PXA1928_CLK_TWSI2 0x03 -#define PXA1928_CLK_TWSI3 0x04 -#define PXA1928_CLK_OWIRE 0x05 -#define PXA1928_CLK_KPC 0x06 -#define PXA1928_CLK_TB_ROTARY 0x07 -#define PXA1928_CLK_SW_JTAG 0x08 -#define PXA1928_CLK_TIMER1 0x09 -#define PXA1928_CLK_UART0 0x0b -#define PXA1928_CLK_UART1 0x0c -#define PXA1928_CLK_UART2 0x0d -#define PXA1928_CLK_GPIO 0x0e -#define PXA1928_CLK_PWM0 0x0f -#define PXA1928_CLK_PWM1 0x10 -#define PXA1928_CLK_PWM2 0x11 -#define PXA1928_CLK_PWM3 0x12 -#define PXA1928_CLK_SSP0 0x13 -#define PXA1928_CLK_SSP1 0x14 -#define PXA1928_CLK_SSP2 0x15 - -#define PXA1928_CLK_TWSI4 0x1f -#define PXA1928_CLK_TWSI5 0x20 -#define PXA1928_CLK_UART3 0x22 -#define PXA1928_CLK_THSENS_GLOB 0x24 -#define PXA1928_CLK_THSENS_CPU 0x26 -#define PXA1928_CLK_THSENS_VPU 0x27 -#define PXA1928_CLK_THSENS_GC 0x28 -#define PXA1928_APBC_NR_CLKS 0x30 - - -/* axi peripherals */ -#define PXA1928_CLK_SDH0 0x15 -#define PXA1928_CLK_SDH1 0x16 -#define PXA1928_CLK_USB 0x17 -#define PXA1928_CLK_NAND 0x18 -#define PXA1928_CLK_DMA 0x19 - -#define PXA1928_CLK_SDH2 0x3a -#define PXA1928_CLK_SDH3 0x3b -#define PXA1928_CLK_HSIC 0x3e -#define PXA1928_CLK_SDH4 0x57 -#define PXA1928_CLK_GC3D 0x5d -#define PXA1928_CLK_GC2D 0x5f - -#define PXA1928_APMU_NR_CLKS 0x60 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/marvell,pxa910.h b/sys/gnu/dts/include/dt-bindings/clock/marvell,pxa910.h deleted file mode 100644 index 7bf46238946..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/marvell,pxa910.h +++ /dev/null @@ -1,59 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __DTS_MARVELL_PXA910_CLOCK_H -#define __DTS_MARVELL_PXA910_CLOCK_H - -/* fixed clocks and plls */ -#define PXA910_CLK_CLK32 1 -#define PXA910_CLK_VCTCXO 2 -#define PXA910_CLK_PLL1 3 -#define PXA910_CLK_PLL1_2 8 -#define PXA910_CLK_PLL1_4 9 -#define PXA910_CLK_PLL1_8 10 -#define PXA910_CLK_PLL1_16 11 -#define PXA910_CLK_PLL1_6 12 -#define PXA910_CLK_PLL1_12 13 -#define PXA910_CLK_PLL1_24 14 -#define PXA910_CLK_PLL1_48 15 -#define PXA910_CLK_PLL1_96 16 -#define PXA910_CLK_PLL1_13 17 -#define PXA910_CLK_PLL1_13_1_5 18 -#define PXA910_CLK_PLL1_2_1_5 19 -#define PXA910_CLK_PLL1_3_16 20 -#define PXA910_CLK_PLL1_192 21 -#define PXA910_CLK_UART_PLL 27 -#define PXA910_CLK_USB_PLL 28 - -/* apb periphrals */ -#define PXA910_CLK_TWSI0 60 -#define PXA910_CLK_TWSI1 61 -#define PXA910_CLK_TWSI2 62 -#define PXA910_CLK_TWSI3 63 -#define PXA910_CLK_GPIO 64 -#define PXA910_CLK_KPC 65 -#define PXA910_CLK_RTC 66 -#define PXA910_CLK_PWM0 67 -#define PXA910_CLK_PWM1 68 -#define PXA910_CLK_PWM2 69 -#define PXA910_CLK_PWM3 70 -#define PXA910_CLK_UART0 71 -#define PXA910_CLK_UART1 72 -#define PXA910_CLK_UART2 73 -#define PXA910_CLK_SSP0 74 -#define PXA910_CLK_SSP1 75 -#define PXA910_CLK_TIMER0 76 -#define PXA910_CLK_TIMER1 77 - -/* axi periphrals */ -#define PXA910_CLK_DFC 100 -#define PXA910_CLK_SDH0 101 -#define PXA910_CLK_SDH1 102 -#define PXA910_CLK_SDH2 103 -#define PXA910_CLK_USB 104 -#define PXA910_CLK_SPH 105 -#define PXA910_CLK_DISP0 106 -#define PXA910_CLK_CCIC0 107 -#define PXA910_CLK_CCIC0_PHY 108 -#define PXA910_CLK_CCIC0_SPHY 109 - -#define PXA910_NR_CLKS 200 -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/maxim,max77620.h b/sys/gnu/dts/include/dt-bindings/clock/maxim,max77620.h deleted file mode 100644 index 9d6609aaa10..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/maxim,max77620.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) 2016 NVIDIA CORPORATION. All rights reserved. - * - * Device Tree binding constants clocks for the Maxim 77620 PMIC. - */ - -#ifndef _DT_BINDINGS_CLOCK_MAXIM_MAX77620_CLOCK_H -#define _DT_BINDINGS_CLOCK_MAXIM_MAX77620_CLOCK_H - -/* Fixed rate clocks. */ - -#define MAX77620_CLK_32K_OUT0 0 - -/* Total number of clocks. */ -#define MAX77620_CLKS_NUM (MAX77620_CLK_32K_OUT0 + 1) - -#endif /* _DT_BINDINGS_CLOCK_MAXIM_MAX77620_CLOCK_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/maxim,max77686.h b/sys/gnu/dts/include/dt-bindings/clock/maxim,max77686.h deleted file mode 100644 index af8261dcace..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/maxim,max77686.h +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2014 Google, Inc - * - * Device Tree binding constants clocks for the Maxim 77686 PMIC. - */ - -#ifndef _DT_BINDINGS_CLOCK_MAXIM_MAX77686_CLOCK_H -#define _DT_BINDINGS_CLOCK_MAXIM_MAX77686_CLOCK_H - -/* Fixed rate clocks. */ - -#define MAX77686_CLK_AP 0 -#define MAX77686_CLK_CP 1 -#define MAX77686_CLK_PMIC 2 - -/* Total number of clocks. */ -#define MAX77686_CLKS_NUM (MAX77686_CLK_PMIC + 1) - -#endif /* _DT_BINDINGS_CLOCK_MAXIM_MAX77686_CLOCK_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/maxim,max77802.h b/sys/gnu/dts/include/dt-bindings/clock/maxim,max77802.h deleted file mode 100644 index 51adcbaed69..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/maxim,max77802.h +++ /dev/null @@ -1,19 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2014 Google, Inc - * - * Device Tree binding constants clocks for the Maxim 77802 PMIC. - */ - -#ifndef _DT_BINDINGS_CLOCK_MAXIM_MAX77802_CLOCK_H -#define _DT_BINDINGS_CLOCK_MAXIM_MAX77802_CLOCK_H - -/* Fixed rate clocks. */ - -#define MAX77802_CLK_32K_AP 0 -#define MAX77802_CLK_32K_CP 1 - -/* Total number of clocks. */ -#define MAX77802_CLKS_NUM (MAX77802_CLK_32K_CP + 1) - -#endif /* _DT_BINDINGS_CLOCK_MAXIM_MAX77802_CLOCK_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/maxim,max9485.h b/sys/gnu/dts/include/dt-bindings/clock/maxim,max9485.h deleted file mode 100644 index 368719a1b8d..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/maxim,max9485.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) 2018 Daniel Mack - */ - -#ifndef __DT_BINDINGS_MAX9485_CLK_H -#define __DT_BINDINGS_MAX9485_CLK_H - -#define MAX9485_MCLKOUT 0 -#define MAX9485_CLKOUT 1 -#define MAX9485_CLKOUT1 2 -#define MAX9485_CLKOUT2 3 - -#endif /* __DT_BINDINGS_MAX9485_CLK_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/meson8-ddr-clkc.h b/sys/gnu/dts/include/dt-bindings/clock/meson8-ddr-clkc.h deleted file mode 100644 index a8e0fa2987a..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/meson8-ddr-clkc.h +++ /dev/null @@ -1,4 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ - -#define DDR_CLKID_DDR_PLL_DCO 0 -#define DDR_CLKID_DDR_PLL 1 diff --git a/sys/gnu/dts/include/dt-bindings/clock/meson8b-clkc.h b/sys/gnu/dts/include/dt-bindings/clock/meson8b-clkc.h deleted file mode 100644 index 68862aaf977..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/meson8b-clkc.h +++ /dev/null @@ -1,119 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Meson8b clock tree IDs - */ - -#ifndef __MESON8B_CLKC_H -#define __MESON8B_CLKC_H - -#define CLKID_UNUSED 0 -#define CLKID_XTAL 1 -#define CLKID_PLL_FIXED 2 -#define CLKID_PLL_VID 3 -#define CLKID_PLL_SYS 4 -#define CLKID_FCLK_DIV2 5 -#define CLKID_FCLK_DIV3 6 -#define CLKID_FCLK_DIV4 7 -#define CLKID_FCLK_DIV5 8 -#define CLKID_FCLK_DIV7 9 -#define CLKID_CLK81 10 -#define CLKID_MALI 11 -#define CLKID_CPUCLK 12 -#define CLKID_ZERO 13 -#define CLKID_MPEG_SEL 14 -#define CLKID_MPEG_DIV 15 -#define CLKID_DDR 16 -#define CLKID_DOS 17 -#define CLKID_ISA 18 -#define CLKID_PL301 19 -#define CLKID_PERIPHS 20 -#define CLKID_SPICC 21 -#define CLKID_I2C 22 -#define CLKID_SAR_ADC 23 -#define CLKID_SMART_CARD 24 -#define CLKID_RNG0 25 -#define CLKID_UART0 26 -#define CLKID_SDHC 27 -#define CLKID_STREAM 28 -#define CLKID_ASYNC_FIFO 29 -#define CLKID_SDIO 30 -#define CLKID_ABUF 31 -#define CLKID_HIU_IFACE 32 -#define CLKID_ASSIST_MISC 33 -#define CLKID_SPI 34 -#define CLKID_I2S_SPDIF 35 -#define CLKID_ETH 36 -#define CLKID_DEMUX 37 -#define CLKID_AIU_GLUE 38 -#define CLKID_IEC958 39 -#define CLKID_I2S_OUT 40 -#define CLKID_AMCLK 41 -#define CLKID_AIFIFO2 42 -#define CLKID_MIXER 43 -#define CLKID_MIXER_IFACE 44 -#define CLKID_ADC 45 -#define CLKID_BLKMV 46 -#define CLKID_AIU 47 -#define CLKID_UART1 48 -#define CLKID_G2D 49 -#define CLKID_USB0 50 -#define CLKID_USB1 51 -#define CLKID_RESET 52 -#define CLKID_NAND 53 -#define CLKID_DOS_PARSER 54 -#define CLKID_USB 55 -#define CLKID_VDIN1 56 -#define CLKID_AHB_ARB0 57 -#define CLKID_EFUSE 58 -#define CLKID_BOOT_ROM 59 -#define CLKID_AHB_DATA_BUS 60 -#define CLKID_AHB_CTRL_BUS 61 -#define CLKID_HDMI_INTR_SYNC 62 -#define CLKID_HDMI_PCLK 63 -#define CLKID_USB1_DDR_BRIDGE 64 -#define CLKID_USB0_DDR_BRIDGE 65 -#define CLKID_MMC_PCLK 66 -#define CLKID_DVIN 67 -#define CLKID_UART2 68 -#define CLKID_SANA 69 -#define CLKID_VPU_INTR 70 -#define CLKID_SEC_AHB_AHB3_BRIDGE 71 -#define CLKID_CLK81_A9 72 -#define CLKID_VCLK2_VENCI0 73 -#define CLKID_VCLK2_VENCI1 74 -#define CLKID_VCLK2_VENCP0 75 -#define CLKID_VCLK2_VENCP1 76 -#define CLKID_GCLK_VENCI_INT 77 -#define CLKID_GCLK_VENCP_INT 78 -#define CLKID_DAC_CLK 79 -#define CLKID_AOCLK_GATE 80 -#define CLKID_IEC958_GATE 81 -#define CLKID_ENC480P 82 -#define CLKID_RNG1 83 -#define CLKID_GCLK_VENCL_INT 84 -#define CLKID_VCLK2_VENCLMCC 85 -#define CLKID_VCLK2_VENCL 86 -#define CLKID_VCLK2_OTHER 87 -#define CLKID_EDP 88 -#define CLKID_AO_MEDIA_CPU 89 -#define CLKID_AO_AHB_SRAM 90 -#define CLKID_AO_AHB_BUS 91 -#define CLKID_AO_IFACE 92 -#define CLKID_MPLL0 93 -#define CLKID_MPLL1 94 -#define CLKID_MPLL2 95 -#define CLKID_NAND_CLK 112 -#define CLKID_APB 124 -#define CLKID_PERIPH 126 -#define CLKID_AXI 128 -#define CLKID_L2_DRAM 130 -#define CLKID_VPU 190 -#define CLKID_VDEC_1 196 -#define CLKID_VDEC_HCODEC 199 -#define CLKID_VDEC_2 202 -#define CLKID_VDEC_HEVC 206 -#define CLKID_CTS_AMCLK 209 -#define CLKID_CTS_MCLK_I958 212 -#define CLKID_CTS_I958 213 - -#endif /* __MESON8B_CLKC_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/microchip,pic32-clock.h b/sys/gnu/dts/include/dt-bindings/clock/microchip,pic32-clock.h deleted file mode 100644 index 371668d9899..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/microchip,pic32-clock.h +++ /dev/null @@ -1,34 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Purna Chandra Mandal, - * Copyright (C) 2015 Microchip Technology Inc. All rights reserved. - */ - -#ifndef _DT_BINDINGS_CLK_MICROCHIP_PIC32_H_ -#define _DT_BINDINGS_CLK_MICROCHIP_PIC32_H_ - -/* clock output indices */ -#define POSCCLK 0 -#define FRCCLK 1 -#define BFRCCLK 2 -#define LPRCCLK 3 -#define SOSCCLK 4 -#define FRCDIVCLK 5 -#define PLLCLK 6 -#define SCLK 7 -#define PB1CLK 8 -#define PB2CLK 9 -#define PB3CLK 10 -#define PB4CLK 11 -#define PB5CLK 12 -#define PB6CLK 13 -#define PB7CLK 14 -#define REF1CLK 15 -#define REF2CLK 16 -#define REF3CLK 17 -#define REF4CLK 18 -#define REF5CLK 19 -#define UPLLCLK 20 -#define MAXCLKS 21 - -#endif /* _DT_BINDINGS_CLK_MICROCHIP_PIC32_H_ */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/mpc512x-clock.h b/sys/gnu/dts/include/dt-bindings/clock/mpc512x-clock.h deleted file mode 100644 index 13c316bf279..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/mpc512x-clock.h +++ /dev/null @@ -1,77 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides constants for MPC512x clock specs in DT bindings. - */ - -#ifndef _DT_BINDINGS_CLOCK_MPC512x_CLOCK_H -#define _DT_BINDINGS_CLOCK_MPC512x_CLOCK_H - -#define MPC512x_CLK_DUMMY 0 -#define MPC512x_CLK_REF 1 -#define MPC512x_CLK_SYS 2 -#define MPC512x_CLK_DIU 3 -#define MPC512x_CLK_VIU 4 -#define MPC512x_CLK_CSB 5 -#define MPC512x_CLK_E300 6 -#define MPC512x_CLK_IPS 7 -#define MPC512x_CLK_FEC 8 -#define MPC512x_CLK_SATA 9 -#define MPC512x_CLK_PATA 10 -#define MPC512x_CLK_NFC 11 -#define MPC512x_CLK_LPC 12 -#define MPC512x_CLK_MBX_BUS 13 -#define MPC512x_CLK_MBX 14 -#define MPC512x_CLK_MBX_3D 15 -#define MPC512x_CLK_AXE 16 -#define MPC512x_CLK_USB1 17 -#define MPC512x_CLK_USB2 18 -#define MPC512x_CLK_I2C 19 -#define MPC512x_CLK_MSCAN0_MCLK 20 -#define MPC512x_CLK_MSCAN1_MCLK 21 -#define MPC512x_CLK_MSCAN2_MCLK 22 -#define MPC512x_CLK_MSCAN3_MCLK 23 -#define MPC512x_CLK_BDLC 24 -#define MPC512x_CLK_SDHC 25 -#define MPC512x_CLK_PCI 26 -#define MPC512x_CLK_PSC_MCLK_IN 27 -#define MPC512x_CLK_SPDIF_TX 28 -#define MPC512x_CLK_SPDIF_RX 29 -#define MPC512x_CLK_SPDIF_MCLK 30 -#define MPC512x_CLK_SPDIF 31 -#define MPC512x_CLK_AC97 32 -#define MPC512x_CLK_PSC0_MCLK 33 -#define MPC512x_CLK_PSC1_MCLK 34 -#define MPC512x_CLK_PSC2_MCLK 35 -#define MPC512x_CLK_PSC3_MCLK 36 -#define MPC512x_CLK_PSC4_MCLK 37 -#define MPC512x_CLK_PSC5_MCLK 38 -#define MPC512x_CLK_PSC6_MCLK 39 -#define MPC512x_CLK_PSC7_MCLK 40 -#define MPC512x_CLK_PSC8_MCLK 41 -#define MPC512x_CLK_PSC9_MCLK 42 -#define MPC512x_CLK_PSC10_MCLK 43 -#define MPC512x_CLK_PSC11_MCLK 44 -#define MPC512x_CLK_PSC_FIFO 45 -#define MPC512x_CLK_PSC0 46 -#define MPC512x_CLK_PSC1 47 -#define MPC512x_CLK_PSC2 48 -#define MPC512x_CLK_PSC3 49 -#define MPC512x_CLK_PSC4 50 -#define MPC512x_CLK_PSC5 51 -#define MPC512x_CLK_PSC6 52 -#define MPC512x_CLK_PSC7 53 -#define MPC512x_CLK_PSC8 54 -#define MPC512x_CLK_PSC9 55 -#define MPC512x_CLK_PSC10 56 -#define MPC512x_CLK_PSC11 57 -#define MPC512x_CLK_SDHC2 58 -#define MPC512x_CLK_FEC2 59 -#define MPC512x_CLK_OUT0_CLK 60 -#define MPC512x_CLK_OUT1_CLK 61 -#define MPC512x_CLK_OUT2_CLK 62 -#define MPC512x_CLK_OUT3_CLK 63 -#define MPC512x_CLK_CAN_CLK_IN 64 - -#define MPC512x_CLK_LAST_PUBLIC 64 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/mt2701-clk.h b/sys/gnu/dts/include/dt-bindings/clock/mt2701-clk.h deleted file mode 100644 index 6d531d5ae06..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/mt2701-clk.h +++ /dev/null @@ -1,484 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2014 MediaTek Inc. - * Author: Shunli Wang - */ - -#ifndef _DT_BINDINGS_CLK_MT2701_H -#define _DT_BINDINGS_CLK_MT2701_H - -/* TOPCKGEN */ -#define CLK_TOP_SYSPLL 1 -#define CLK_TOP_SYSPLL_D2 2 -#define CLK_TOP_SYSPLL_D3 3 -#define CLK_TOP_SYSPLL_D5 4 -#define CLK_TOP_SYSPLL_D7 5 -#define CLK_TOP_SYSPLL1_D2 6 -#define CLK_TOP_SYSPLL1_D4 7 -#define CLK_TOP_SYSPLL1_D8 8 -#define CLK_TOP_SYSPLL1_D16 9 -#define CLK_TOP_SYSPLL2_D2 10 -#define CLK_TOP_SYSPLL2_D4 11 -#define CLK_TOP_SYSPLL2_D8 12 -#define CLK_TOP_SYSPLL3_D2 13 -#define CLK_TOP_SYSPLL3_D4 14 -#define CLK_TOP_SYSPLL4_D2 15 -#define CLK_TOP_SYSPLL4_D4 16 -#define CLK_TOP_UNIVPLL 17 -#define CLK_TOP_UNIVPLL_D2 18 -#define CLK_TOP_UNIVPLL_D3 19 -#define CLK_TOP_UNIVPLL_D5 20 -#define CLK_TOP_UNIVPLL_D7 21 -#define CLK_TOP_UNIVPLL_D26 22 -#define CLK_TOP_UNIVPLL_D52 23 -#define CLK_TOP_UNIVPLL_D108 24 -#define CLK_TOP_USB_PHY48M 25 -#define CLK_TOP_UNIVPLL1_D2 26 -#define CLK_TOP_UNIVPLL1_D4 27 -#define CLK_TOP_UNIVPLL1_D8 28 -#define CLK_TOP_UNIVPLL2_D2 29 -#define CLK_TOP_UNIVPLL2_D4 30 -#define CLK_TOP_UNIVPLL2_D8 31 -#define CLK_TOP_UNIVPLL2_D16 32 -#define CLK_TOP_UNIVPLL2_D32 33 -#define CLK_TOP_UNIVPLL3_D2 34 -#define CLK_TOP_UNIVPLL3_D4 35 -#define CLK_TOP_UNIVPLL3_D8 36 -#define CLK_TOP_MSDCPLL 37 -#define CLK_TOP_MSDCPLL_D2 38 -#define CLK_TOP_MSDCPLL_D4 39 -#define CLK_TOP_MSDCPLL_D8 40 -#define CLK_TOP_MMPLL 41 -#define CLK_TOP_MMPLL_D2 42 -#define CLK_TOP_DMPLL 43 -#define CLK_TOP_DMPLL_D2 44 -#define CLK_TOP_DMPLL_D4 45 -#define CLK_TOP_DMPLL_X2 46 -#define CLK_TOP_TVDPLL 47 -#define CLK_TOP_TVDPLL_D2 48 -#define CLK_TOP_TVDPLL_D4 49 -#define CLK_TOP_TVD2PLL 50 -#define CLK_TOP_TVD2PLL_D2 51 -#define CLK_TOP_HADDS2PLL_98M 52 -#define CLK_TOP_HADDS2PLL_294M 53 -#define CLK_TOP_HADDS2_FB 54 -#define CLK_TOP_MIPIPLL_D2 55 -#define CLK_TOP_MIPIPLL_D4 56 -#define CLK_TOP_HDMIPLL 57 -#define CLK_TOP_HDMIPLL_D2 58 -#define CLK_TOP_HDMIPLL_D3 59 -#define CLK_TOP_HDMI_SCL_RX 60 -#define CLK_TOP_HDMI_0_PIX340M 61 -#define CLK_TOP_HDMI_0_DEEP340M 62 -#define CLK_TOP_HDMI_0_PLL340M 63 -#define CLK_TOP_AUD1PLL_98M 64 -#define CLK_TOP_AUD2PLL_90M 65 -#define CLK_TOP_AUDPLL 66 -#define CLK_TOP_AUDPLL_D4 67 -#define CLK_TOP_AUDPLL_D8 68 -#define CLK_TOP_AUDPLL_D16 69 -#define CLK_TOP_AUDPLL_D24 70 -#define CLK_TOP_ETHPLL_500M 71 -#define CLK_TOP_VDECPLL 72 -#define CLK_TOP_VENCPLL 73 -#define CLK_TOP_MIPIPLL 74 -#define CLK_TOP_ARMPLL_1P3G 75 - -#define CLK_TOP_MM_SEL 76 -#define CLK_TOP_DDRPHYCFG_SEL 77 -#define CLK_TOP_MEM_SEL 78 -#define CLK_TOP_AXI_SEL 79 -#define CLK_TOP_CAMTG_SEL 80 -#define CLK_TOP_MFG_SEL 81 -#define CLK_TOP_VDEC_SEL 82 -#define CLK_TOP_PWM_SEL 83 -#define CLK_TOP_MSDC30_0_SEL 84 -#define CLK_TOP_USB20_SEL 85 -#define CLK_TOP_SPI0_SEL 86 -#define CLK_TOP_UART_SEL 87 -#define CLK_TOP_AUDINTBUS_SEL 88 -#define CLK_TOP_AUDIO_SEL 89 -#define CLK_TOP_MSDC30_2_SEL 90 -#define CLK_TOP_MSDC30_1_SEL 91 -#define CLK_TOP_DPI1_SEL 92 -#define CLK_TOP_DPI0_SEL 93 -#define CLK_TOP_SCP_SEL 94 -#define CLK_TOP_PMICSPI_SEL 95 -#define CLK_TOP_APLL_SEL 96 -#define CLK_TOP_HDMI_SEL 97 -#define CLK_TOP_TVE_SEL 98 -#define CLK_TOP_EMMC_HCLK_SEL 99 -#define CLK_TOP_NFI2X_SEL 100 -#define CLK_TOP_RTC_SEL 101 -#define CLK_TOP_OSD_SEL 102 -#define CLK_TOP_NR_SEL 103 -#define CLK_TOP_DI_SEL 104 -#define CLK_TOP_FLASH_SEL 105 -#define CLK_TOP_ASM_M_SEL 106 -#define CLK_TOP_ASM_I_SEL 107 -#define CLK_TOP_INTDIR_SEL 108 -#define CLK_TOP_HDMIRX_BIST_SEL 109 -#define CLK_TOP_ETHIF_SEL 110 -#define CLK_TOP_MS_CARD_SEL 111 -#define CLK_TOP_ASM_H_SEL 112 -#define CLK_TOP_SPI1_SEL 113 -#define CLK_TOP_CMSYS_SEL 114 -#define CLK_TOP_MSDC30_3_SEL 115 -#define CLK_TOP_HDMIRX26_24_SEL 116 -#define CLK_TOP_AUD2DVD_SEL 117 -#define CLK_TOP_8BDAC_SEL 118 -#define CLK_TOP_SPI2_SEL 119 -#define CLK_TOP_AUD_MUX1_SEL 120 -#define CLK_TOP_AUD_MUX2_SEL 121 -#define CLK_TOP_AUDPLL_MUX_SEL 122 -#define CLK_TOP_AUD_K1_SRC_SEL 123 -#define CLK_TOP_AUD_K2_SRC_SEL 124 -#define CLK_TOP_AUD_K3_SRC_SEL 125 -#define CLK_TOP_AUD_K4_SRC_SEL 126 -#define CLK_TOP_AUD_K5_SRC_SEL 127 -#define CLK_TOP_AUD_K6_SRC_SEL 128 -#define CLK_TOP_PADMCLK_SEL 129 -#define CLK_TOP_AUD_EXTCK1_DIV 130 -#define CLK_TOP_AUD_EXTCK2_DIV 131 -#define CLK_TOP_AUD_MUX1_DIV 132 -#define CLK_TOP_AUD_MUX2_DIV 133 -#define CLK_TOP_AUD_K1_SRC_DIV 134 -#define CLK_TOP_AUD_K2_SRC_DIV 135 -#define CLK_TOP_AUD_K3_SRC_DIV 136 -#define CLK_TOP_AUD_K4_SRC_DIV 137 -#define CLK_TOP_AUD_K5_SRC_DIV 138 -#define CLK_TOP_AUD_K6_SRC_DIV 139 -#define CLK_TOP_AUD_I2S1_MCLK 140 -#define CLK_TOP_AUD_I2S2_MCLK 141 -#define CLK_TOP_AUD_I2S3_MCLK 142 -#define CLK_TOP_AUD_I2S4_MCLK 143 -#define CLK_TOP_AUD_I2S5_MCLK 144 -#define CLK_TOP_AUD_I2S6_MCLK 145 -#define CLK_TOP_AUD_48K_TIMING 146 -#define CLK_TOP_AUD_44K_TIMING 147 - -#define CLK_TOP_32K_INTERNAL 148 -#define CLK_TOP_32K_EXTERNAL 149 -#define CLK_TOP_CLK26M_D8 150 -#define CLK_TOP_8BDAC 151 -#define CLK_TOP_WBG_DIG_416M 152 -#define CLK_TOP_DPI 153 -#define CLK_TOP_DSI0_LNTC_DSI 154 -#define CLK_TOP_AUD_EXT1 155 -#define CLK_TOP_AUD_EXT2 156 -#define CLK_TOP_NFI1X_PAD 157 -#define CLK_TOP_AXISEL_D4 158 -#define CLK_TOP_NR 159 - -/* APMIXEDSYS */ - -#define CLK_APMIXED_ARMPLL 1 -#define CLK_APMIXED_MAINPLL 2 -#define CLK_APMIXED_UNIVPLL 3 -#define CLK_APMIXED_MMPLL 4 -#define CLK_APMIXED_MSDCPLL 5 -#define CLK_APMIXED_TVDPLL 6 -#define CLK_APMIXED_AUD1PLL 7 -#define CLK_APMIXED_TRGPLL 8 -#define CLK_APMIXED_ETHPLL 9 -#define CLK_APMIXED_VDECPLL 10 -#define CLK_APMIXED_HADDS2PLL 11 -#define CLK_APMIXED_AUD2PLL 12 -#define CLK_APMIXED_TVD2PLL 13 -#define CLK_APMIXED_HDMI_REF 14 -#define CLK_APMIXED_NR 15 - -/* DDRPHY */ - -#define CLK_DDRPHY_VENCPLL 1 -#define CLK_DDRPHY_NR 2 - -/* INFRACFG */ - -#define CLK_INFRA_DBG 1 -#define CLK_INFRA_SMI 2 -#define CLK_INFRA_QAXI_CM4 3 -#define CLK_INFRA_AUD_SPLIN_B 4 -#define CLK_INFRA_AUDIO 5 -#define CLK_INFRA_EFUSE 6 -#define CLK_INFRA_L2C_SRAM 7 -#define CLK_INFRA_M4U 8 -#define CLK_INFRA_CONNMCU 9 -#define CLK_INFRA_TRNG 10 -#define CLK_INFRA_RAMBUFIF 11 -#define CLK_INFRA_CPUM 12 -#define CLK_INFRA_KP 13 -#define CLK_INFRA_CEC 14 -#define CLK_INFRA_IRRX 15 -#define CLK_INFRA_PMICSPI 16 -#define CLK_INFRA_PMICWRAP 17 -#define CLK_INFRA_DDCCI 18 -#define CLK_INFRA_CLK_13M 19 -#define CLK_INFRA_CPUSEL 20 -#define CLK_INFRA_NR 21 - -/* PERICFG */ - -#define CLK_PERI_NFI 1 -#define CLK_PERI_THERM 2 -#define CLK_PERI_PWM1 3 -#define CLK_PERI_PWM2 4 -#define CLK_PERI_PWM3 5 -#define CLK_PERI_PWM4 6 -#define CLK_PERI_PWM5 7 -#define CLK_PERI_PWM6 8 -#define CLK_PERI_PWM7 9 -#define CLK_PERI_PWM 10 -#define CLK_PERI_USB0 11 -#define CLK_PERI_USB1 12 -#define CLK_PERI_AP_DMA 13 -#define CLK_PERI_MSDC30_0 14 -#define CLK_PERI_MSDC30_1 15 -#define CLK_PERI_MSDC30_2 16 -#define CLK_PERI_MSDC30_3 17 -#define CLK_PERI_MSDC50_3 18 -#define CLK_PERI_NLI 19 -#define CLK_PERI_UART0 20 -#define CLK_PERI_UART1 21 -#define CLK_PERI_UART2 22 -#define CLK_PERI_UART3 23 -#define CLK_PERI_BTIF 24 -#define CLK_PERI_I2C0 25 -#define CLK_PERI_I2C1 26 -#define CLK_PERI_I2C2 27 -#define CLK_PERI_I2C3 28 -#define CLK_PERI_AUXADC 29 -#define CLK_PERI_SPI0 30 -#define CLK_PERI_ETH 31 -#define CLK_PERI_USB0_MCU 32 - -#define CLK_PERI_USB1_MCU 33 -#define CLK_PERI_USB_SLV 34 -#define CLK_PERI_GCPU 35 -#define CLK_PERI_NFI_ECC 36 -#define CLK_PERI_NFI_PAD 37 -#define CLK_PERI_FLASH 38 -#define CLK_PERI_HOST89_INT 39 -#define CLK_PERI_HOST89_SPI 40 -#define CLK_PERI_HOST89_DVD 41 -#define CLK_PERI_SPI1 42 -#define CLK_PERI_SPI2 43 -#define CLK_PERI_FCI 44 - -#define CLK_PERI_UART0_SEL 45 -#define CLK_PERI_UART1_SEL 46 -#define CLK_PERI_UART2_SEL 47 -#define CLK_PERI_UART3_SEL 48 -#define CLK_PERI_NR 49 - -/* AUDIO */ - -#define CLK_AUD_AFE 1 -#define CLK_AUD_LRCK_DETECT 2 -#define CLK_AUD_I2S 3 -#define CLK_AUD_APLL_TUNER 4 -#define CLK_AUD_HDMI 5 -#define CLK_AUD_SPDF 6 -#define CLK_AUD_SPDF2 7 -#define CLK_AUD_APLL 8 -#define CLK_AUD_TML 9 -#define CLK_AUD_AHB_IDLE_EXT 10 -#define CLK_AUD_AHB_IDLE_INT 11 - -#define CLK_AUD_I2SIN1 12 -#define CLK_AUD_I2SIN2 13 -#define CLK_AUD_I2SIN3 14 -#define CLK_AUD_I2SIN4 15 -#define CLK_AUD_I2SIN5 16 -#define CLK_AUD_I2SIN6 17 -#define CLK_AUD_I2SO1 18 -#define CLK_AUD_I2SO2 19 -#define CLK_AUD_I2SO3 20 -#define CLK_AUD_I2SO4 21 -#define CLK_AUD_I2SO5 22 -#define CLK_AUD_I2SO6 23 -#define CLK_AUD_ASRCI1 24 -#define CLK_AUD_ASRCI2 25 -#define CLK_AUD_ASRCO1 26 -#define CLK_AUD_ASRCO2 27 -#define CLK_AUD_ASRC11 28 -#define CLK_AUD_ASRC12 29 -#define CLK_AUD_HDMIRX 30 -#define CLK_AUD_INTDIR 31 -#define CLK_AUD_A1SYS 32 -#define CLK_AUD_A2SYS 33 -#define CLK_AUD_AFE_CONN 34 -#define CLK_AUD_AFE_PCMIF 35 -#define CLK_AUD_AFE_MRGIF 36 - -#define CLK_AUD_MMIF_UL1 37 -#define CLK_AUD_MMIF_UL2 38 -#define CLK_AUD_MMIF_UL3 39 -#define CLK_AUD_MMIF_UL4 40 -#define CLK_AUD_MMIF_UL5 41 -#define CLK_AUD_MMIF_UL6 42 -#define CLK_AUD_MMIF_DL1 43 -#define CLK_AUD_MMIF_DL2 44 -#define CLK_AUD_MMIF_DL3 45 -#define CLK_AUD_MMIF_DL4 46 -#define CLK_AUD_MMIF_DL5 47 -#define CLK_AUD_MMIF_DL6 48 -#define CLK_AUD_MMIF_DLMCH 49 -#define CLK_AUD_MMIF_ARB1 50 -#define CLK_AUD_MMIF_AWB1 51 -#define CLK_AUD_MMIF_AWB2 52 -#define CLK_AUD_MMIF_DAI 53 - -#define CLK_AUD_DMIC1 54 -#define CLK_AUD_DMIC2 55 -#define CLK_AUD_ASRCI3 56 -#define CLK_AUD_ASRCI4 57 -#define CLK_AUD_ASRCI5 58 -#define CLK_AUD_ASRCI6 59 -#define CLK_AUD_ASRCO3 60 -#define CLK_AUD_ASRCO4 61 -#define CLK_AUD_ASRCO5 62 -#define CLK_AUD_ASRCO6 63 -#define CLK_AUD_MEM_ASRC1 64 -#define CLK_AUD_MEM_ASRC2 65 -#define CLK_AUD_MEM_ASRC3 66 -#define CLK_AUD_MEM_ASRC4 67 -#define CLK_AUD_MEM_ASRC5 68 -#define CLK_AUD_DSD_ENC 69 -#define CLK_AUD_ASRC_BRG 70 -#define CLK_AUD_NR 71 - -/* MMSYS */ - -#define CLK_MM_SMI_COMMON 1 -#define CLK_MM_SMI_LARB0 2 -#define CLK_MM_CMDQ 3 -#define CLK_MM_MUTEX 4 -#define CLK_MM_DISP_COLOR 5 -#define CLK_MM_DISP_BLS 6 -#define CLK_MM_DISP_WDMA 7 -#define CLK_MM_DISP_RDMA 8 -#define CLK_MM_DISP_OVL 9 -#define CLK_MM_MDP_TDSHP 10 -#define CLK_MM_MDP_WROT 11 -#define CLK_MM_MDP_WDMA 12 -#define CLK_MM_MDP_RSZ1 13 -#define CLK_MM_MDP_RSZ0 14 -#define CLK_MM_MDP_RDMA 15 -#define CLK_MM_MDP_BLS_26M 16 -#define CLK_MM_CAM_MDP 17 -#define CLK_MM_FAKE_ENG 18 -#define CLK_MM_MUTEX_32K 19 -#define CLK_MM_DISP_RDMA1 20 -#define CLK_MM_DISP_UFOE 21 - -#define CLK_MM_DSI_ENGINE 22 -#define CLK_MM_DSI_DIG 23 -#define CLK_MM_DPI_DIGL 24 -#define CLK_MM_DPI_ENGINE 25 -#define CLK_MM_DPI1_DIGL 26 -#define CLK_MM_DPI1_ENGINE 27 -#define CLK_MM_TVE_OUTPUT 28 -#define CLK_MM_TVE_INPUT 29 -#define CLK_MM_HDMI_PIXEL 30 -#define CLK_MM_HDMI_PLL 31 -#define CLK_MM_HDMI_AUDIO 32 -#define CLK_MM_HDMI_SPDIF 33 -#define CLK_MM_TVE_FMM 34 -#define CLK_MM_NR 35 - -/* IMGSYS */ - -#define CLK_IMG_SMI_COMM 1 -#define CLK_IMG_RESZ 2 -#define CLK_IMG_JPGDEC_SMI 3 -#define CLK_IMG_JPGDEC 4 -#define CLK_IMG_VENC_LT 5 -#define CLK_IMG_VENC 6 -#define CLK_IMG_NR 7 - -/* VDEC */ - -#define CLK_VDEC_CKGEN 1 -#define CLK_VDEC_LARB 2 -#define CLK_VDEC_NR 3 - -/* HIFSYS */ - -#define CLK_HIFSYS_USB0PHY 1 -#define CLK_HIFSYS_USB1PHY 2 -#define CLK_HIFSYS_PCIE0 3 -#define CLK_HIFSYS_PCIE1 4 -#define CLK_HIFSYS_PCIE2 5 -#define CLK_HIFSYS_NR 6 - -/* ETHSYS */ -#define CLK_ETHSYS_HSDMA 1 -#define CLK_ETHSYS_ESW 2 -#define CLK_ETHSYS_GP2 3 -#define CLK_ETHSYS_GP1 4 -#define CLK_ETHSYS_PCM 5 -#define CLK_ETHSYS_GDMA 6 -#define CLK_ETHSYS_I2S 7 -#define CLK_ETHSYS_CRYPTO 8 -#define CLK_ETHSYS_NR 9 - -/* G3DSYS */ -#define CLK_G3DSYS_CORE 1 -#define CLK_G3DSYS_NR 2 - -/* BDP */ - -#define CLK_BDP_BRG_BA 1 -#define CLK_BDP_BRG_DRAM 2 -#define CLK_BDP_LARB_DRAM 3 -#define CLK_BDP_WR_VDI_PXL 4 -#define CLK_BDP_WR_VDI_DRAM 5 -#define CLK_BDP_WR_B 6 -#define CLK_BDP_DGI_IN 7 -#define CLK_BDP_DGI_OUT 8 -#define CLK_BDP_FMT_MAST_27 9 -#define CLK_BDP_FMT_B 10 -#define CLK_BDP_OSD_B 11 -#define CLK_BDP_OSD_DRAM 12 -#define CLK_BDP_OSD_AGENT 13 -#define CLK_BDP_OSD_PXL 14 -#define CLK_BDP_RLE_B 15 -#define CLK_BDP_RLE_AGENT 16 -#define CLK_BDP_RLE_DRAM 17 -#define CLK_BDP_F27M 18 -#define CLK_BDP_F27M_VDOUT 19 -#define CLK_BDP_F27_74_74 20 -#define CLK_BDP_F2FS 21 -#define CLK_BDP_F2FS74_148 22 -#define CLK_BDP_FB 23 -#define CLK_BDP_VDO_DRAM 24 -#define CLK_BDP_VDO_2FS 25 -#define CLK_BDP_VDO_B 26 -#define CLK_BDP_WR_DI_PXL 27 -#define CLK_BDP_WR_DI_DRAM 28 -#define CLK_BDP_WR_DI_B 29 -#define CLK_BDP_NR_PXL 30 -#define CLK_BDP_NR_DRAM 31 -#define CLK_BDP_NR_B 32 - -#define CLK_BDP_RX_F 33 -#define CLK_BDP_RX_X 34 -#define CLK_BDP_RXPDT 35 -#define CLK_BDP_RX_CSCL_N 36 -#define CLK_BDP_RX_CSCL 37 -#define CLK_BDP_RX_DDCSCL_N 38 -#define CLK_BDP_RX_DDCSCL 39 -#define CLK_BDP_RX_VCO 40 -#define CLK_BDP_RX_DP 41 -#define CLK_BDP_RX_P 42 -#define CLK_BDP_RX_M 43 -#define CLK_BDP_RX_PLL 44 -#define CLK_BDP_BRG_RT_B 45 -#define CLK_BDP_BRG_RT_DRAM 46 -#define CLK_BDP_LARBRT_DRAM 47 -#define CLK_BDP_TMDS_SYN 48 -#define CLK_BDP_HDMI_MON 49 -#define CLK_BDP_NR 50 - -#endif /* _DT_BINDINGS_CLK_MT2701_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/mt2712-clk.h b/sys/gnu/dts/include/dt-bindings/clock/mt2712-clk.h deleted file mode 100644 index 0800d9ce7c6..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/mt2712-clk.h +++ /dev/null @@ -1,428 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2017 MediaTek Inc. - * Author: Weiyi Lu - */ - -#ifndef _DT_BINDINGS_CLK_MT2712_H -#define _DT_BINDINGS_CLK_MT2712_H - -/* APMIXEDSYS */ - -#define CLK_APMIXED_MAINPLL 0 -#define CLK_APMIXED_UNIVPLL 1 -#define CLK_APMIXED_VCODECPLL 2 -#define CLK_APMIXED_VENCPLL 3 -#define CLK_APMIXED_APLL1 4 -#define CLK_APMIXED_APLL2 5 -#define CLK_APMIXED_LVDSPLL 6 -#define CLK_APMIXED_LVDSPLL2 7 -#define CLK_APMIXED_MSDCPLL 8 -#define CLK_APMIXED_MSDCPLL2 9 -#define CLK_APMIXED_TVDPLL 10 -#define CLK_APMIXED_MMPLL 11 -#define CLK_APMIXED_ARMCA35PLL 12 -#define CLK_APMIXED_ARMCA72PLL 13 -#define CLK_APMIXED_ETHERPLL 14 -#define CLK_APMIXED_NR_CLK 15 - -/* TOPCKGEN */ - -#define CLK_TOP_ARMCA35PLL 0 -#define CLK_TOP_ARMCA35PLL_600M 1 -#define CLK_TOP_ARMCA35PLL_400M 2 -#define CLK_TOP_ARMCA72PLL 3 -#define CLK_TOP_SYSPLL 4 -#define CLK_TOP_SYSPLL_D2 5 -#define CLK_TOP_SYSPLL1_D2 6 -#define CLK_TOP_SYSPLL1_D4 7 -#define CLK_TOP_SYSPLL1_D8 8 -#define CLK_TOP_SYSPLL1_D16 9 -#define CLK_TOP_SYSPLL_D3 10 -#define CLK_TOP_SYSPLL2_D2 11 -#define CLK_TOP_SYSPLL2_D4 12 -#define CLK_TOP_SYSPLL_D5 13 -#define CLK_TOP_SYSPLL3_D2 14 -#define CLK_TOP_SYSPLL3_D4 15 -#define CLK_TOP_SYSPLL_D7 16 -#define CLK_TOP_SYSPLL4_D2 17 -#define CLK_TOP_SYSPLL4_D4 18 -#define CLK_TOP_UNIVPLL 19 -#define CLK_TOP_UNIVPLL_D7 20 -#define CLK_TOP_UNIVPLL_D26 21 -#define CLK_TOP_UNIVPLL_D52 22 -#define CLK_TOP_UNIVPLL_D104 23 -#define CLK_TOP_UNIVPLL_D208 24 -#define CLK_TOP_UNIVPLL_D2 25 -#define CLK_TOP_UNIVPLL1_D2 26 -#define CLK_TOP_UNIVPLL1_D4 27 -#define CLK_TOP_UNIVPLL1_D8 28 -#define CLK_TOP_UNIVPLL_D3 29 -#define CLK_TOP_UNIVPLL2_D2 30 -#define CLK_TOP_UNIVPLL2_D4 31 -#define CLK_TOP_UNIVPLL2_D8 32 -#define CLK_TOP_UNIVPLL_D5 33 -#define CLK_TOP_UNIVPLL3_D2 34 -#define CLK_TOP_UNIVPLL3_D4 35 -#define CLK_TOP_UNIVPLL3_D8 36 -#define CLK_TOP_F_MP0_PLL1 37 -#define CLK_TOP_F_MP0_PLL2 38 -#define CLK_TOP_F_BIG_PLL1 39 -#define CLK_TOP_F_BIG_PLL2 40 -#define CLK_TOP_F_BUS_PLL1 41 -#define CLK_TOP_F_BUS_PLL2 42 -#define CLK_TOP_APLL1 43 -#define CLK_TOP_APLL1_D2 44 -#define CLK_TOP_APLL1_D4 45 -#define CLK_TOP_APLL1_D8 46 -#define CLK_TOP_APLL1_D16 47 -#define CLK_TOP_APLL2 48 -#define CLK_TOP_APLL2_D2 49 -#define CLK_TOP_APLL2_D4 50 -#define CLK_TOP_APLL2_D8 51 -#define CLK_TOP_APLL2_D16 52 -#define CLK_TOP_LVDSPLL 53 -#define CLK_TOP_LVDSPLL_D2 54 -#define CLK_TOP_LVDSPLL_D4 55 -#define CLK_TOP_LVDSPLL_D8 56 -#define CLK_TOP_LVDSPLL2 57 -#define CLK_TOP_LVDSPLL2_D2 58 -#define CLK_TOP_LVDSPLL2_D4 59 -#define CLK_TOP_LVDSPLL2_D8 60 -#define CLK_TOP_ETHERPLL_125M 61 -#define CLK_TOP_ETHERPLL_50M 62 -#define CLK_TOP_CVBS 63 -#define CLK_TOP_CVBS_D2 64 -#define CLK_TOP_SYS_26M 65 -#define CLK_TOP_MMPLL 66 -#define CLK_TOP_MMPLL_D2 67 -#define CLK_TOP_VENCPLL 68 -#define CLK_TOP_VENCPLL_D2 69 -#define CLK_TOP_VCODECPLL 70 -#define CLK_TOP_VCODECPLL_D2 71 -#define CLK_TOP_TVDPLL 72 -#define CLK_TOP_TVDPLL_D2 73 -#define CLK_TOP_TVDPLL_D4 74 -#define CLK_TOP_TVDPLL_D8 75 -#define CLK_TOP_TVDPLL_429M 76 -#define CLK_TOP_TVDPLL_429M_D2 77 -#define CLK_TOP_TVDPLL_429M_D4 78 -#define CLK_TOP_MSDCPLL 79 -#define CLK_TOP_MSDCPLL_D2 80 -#define CLK_TOP_MSDCPLL_D4 81 -#define CLK_TOP_MSDCPLL2 82 -#define CLK_TOP_MSDCPLL2_D2 83 -#define CLK_TOP_MSDCPLL2_D4 84 -#define CLK_TOP_CLK26M_D2 85 -#define CLK_TOP_D2A_ULCLK_6P5M 86 -#define CLK_TOP_VPLL3_DPIX 87 -#define CLK_TOP_VPLL_DPIX 88 -#define CLK_TOP_LTEPLL_FS26M 89 -#define CLK_TOP_DMPLL 90 -#define CLK_TOP_DSI0_LNTC 91 -#define CLK_TOP_DSI1_LNTC 92 -#define CLK_TOP_LVDSTX3_CLKDIG_CTS 93 -#define CLK_TOP_LVDSTX_CLKDIG_CTS 94 -#define CLK_TOP_CLKRTC_EXT 95 -#define CLK_TOP_CLKRTC_INT 96 -#define CLK_TOP_CSI0 97 -#define CLK_TOP_CVBSPLL 98 -#define CLK_TOP_AXI_SEL 99 -#define CLK_TOP_MEM_SEL 100 -#define CLK_TOP_MM_SEL 101 -#define CLK_TOP_PWM_SEL 102 -#define CLK_TOP_VDEC_SEL 103 -#define CLK_TOP_VENC_SEL 104 -#define CLK_TOP_MFG_SEL 105 -#define CLK_TOP_CAMTG_SEL 106 -#define CLK_TOP_UART_SEL 107 -#define CLK_TOP_SPI_SEL 108 -#define CLK_TOP_USB20_SEL 109 -#define CLK_TOP_USB30_SEL 110 -#define CLK_TOP_MSDC50_0_HCLK_SEL 111 -#define CLK_TOP_MSDC50_0_SEL 112 -#define CLK_TOP_MSDC30_1_SEL 113 -#define CLK_TOP_MSDC30_2_SEL 114 -#define CLK_TOP_MSDC30_3_SEL 115 -#define CLK_TOP_AUDIO_SEL 116 -#define CLK_TOP_AUD_INTBUS_SEL 117 -#define CLK_TOP_PMICSPI_SEL 118 -#define CLK_TOP_DPILVDS1_SEL 119 -#define CLK_TOP_ATB_SEL 120 -#define CLK_TOP_NR_SEL 121 -#define CLK_TOP_NFI2X_SEL 122 -#define CLK_TOP_IRDA_SEL 123 -#define CLK_TOP_CCI400_SEL 124 -#define CLK_TOP_AUD_1_SEL 125 -#define CLK_TOP_AUD_2_SEL 126 -#define CLK_TOP_MEM_MFG_IN_AS_SEL 127 -#define CLK_TOP_AXI_MFG_IN_AS_SEL 128 -#define CLK_TOP_SCAM_SEL 129 -#define CLK_TOP_NFIECC_SEL 130 -#define CLK_TOP_PE2_MAC_P0_SEL 131 -#define CLK_TOP_PE2_MAC_P1_SEL 132 -#define CLK_TOP_DPILVDS_SEL 133 -#define CLK_TOP_MSDC50_3_HCLK_SEL 134 -#define CLK_TOP_HDCP_SEL 135 -#define CLK_TOP_HDCP_24M_SEL 136 -#define CLK_TOP_RTC_SEL 137 -#define CLK_TOP_SPINOR_SEL 138 -#define CLK_TOP_APLL_SEL 139 -#define CLK_TOP_APLL2_SEL 140 -#define CLK_TOP_A1SYS_HP_SEL 141 -#define CLK_TOP_A2SYS_HP_SEL 142 -#define CLK_TOP_ASM_L_SEL 143 -#define CLK_TOP_ASM_M_SEL 144 -#define CLK_TOP_ASM_H_SEL 145 -#define CLK_TOP_I2SO1_SEL 146 -#define CLK_TOP_I2SO2_SEL 147 -#define CLK_TOP_I2SO3_SEL 148 -#define CLK_TOP_TDMO0_SEL 149 -#define CLK_TOP_TDMO1_SEL 150 -#define CLK_TOP_I2SI1_SEL 151 -#define CLK_TOP_I2SI2_SEL 152 -#define CLK_TOP_I2SI3_SEL 153 -#define CLK_TOP_ETHER_125M_SEL 154 -#define CLK_TOP_ETHER_50M_SEL 155 -#define CLK_TOP_JPGDEC_SEL 156 -#define CLK_TOP_SPISLV_SEL 157 -#define CLK_TOP_ETHER_50M_RMII_SEL 158 -#define CLK_TOP_CAM2TG_SEL 159 -#define CLK_TOP_DI_SEL 160 -#define CLK_TOP_TVD_SEL 161 -#define CLK_TOP_I2C_SEL 162 -#define CLK_TOP_PWM_INFRA_SEL 163 -#define CLK_TOP_MSDC0P_AES_SEL 164 -#define CLK_TOP_CMSYS_SEL 165 -#define CLK_TOP_GCPU_SEL 166 -#define CLK_TOP_AUD_APLL1_SEL 167 -#define CLK_TOP_AUD_APLL2_SEL 168 -#define CLK_TOP_DA_AUDULL_VTX_6P5M_SEL 169 -#define CLK_TOP_APLL_DIV0 170 -#define CLK_TOP_APLL_DIV1 171 -#define CLK_TOP_APLL_DIV2 172 -#define CLK_TOP_APLL_DIV3 173 -#define CLK_TOP_APLL_DIV4 174 -#define CLK_TOP_APLL_DIV5 175 -#define CLK_TOP_APLL_DIV6 176 -#define CLK_TOP_APLL_DIV7 177 -#define CLK_TOP_APLL_DIV_PDN0 178 -#define CLK_TOP_APLL_DIV_PDN1 179 -#define CLK_TOP_APLL_DIV_PDN2 180 -#define CLK_TOP_APLL_DIV_PDN3 181 -#define CLK_TOP_APLL_DIV_PDN4 182 -#define CLK_TOP_APLL_DIV_PDN5 183 -#define CLK_TOP_APLL_DIV_PDN6 184 -#define CLK_TOP_APLL_DIV_PDN7 185 -#define CLK_TOP_APLL1_D3 186 -#define CLK_TOP_APLL1_REF_SEL 187 -#define CLK_TOP_APLL2_REF_SEL 188 -#define CLK_TOP_NFI2X_EN 189 -#define CLK_TOP_NFIECC_EN 190 -#define CLK_TOP_NFI1X_CK_EN 191 -#define CLK_TOP_APLL2_D3 192 -#define CLK_TOP_NR_CLK 193 - -/* INFRACFG */ - -#define CLK_INFRA_DBGCLK 0 -#define CLK_INFRA_GCE 1 -#define CLK_INFRA_M4U 2 -#define CLK_INFRA_KP 3 -#define CLK_INFRA_AO_SPI0 4 -#define CLK_INFRA_AO_SPI1 5 -#define CLK_INFRA_AO_UART5 6 -#define CLK_INFRA_NR_CLK 7 - -/* PERICFG */ - -#define CLK_PERI_NFI 0 -#define CLK_PERI_THERM 1 -#define CLK_PERI_PWM0 2 -#define CLK_PERI_PWM1 3 -#define CLK_PERI_PWM2 4 -#define CLK_PERI_PWM3 5 -#define CLK_PERI_PWM4 6 -#define CLK_PERI_PWM5 7 -#define CLK_PERI_PWM6 8 -#define CLK_PERI_PWM7 9 -#define CLK_PERI_PWM 10 -#define CLK_PERI_AP_DMA 11 -#define CLK_PERI_MSDC30_0 12 -#define CLK_PERI_MSDC30_1 13 -#define CLK_PERI_MSDC30_2 14 -#define CLK_PERI_MSDC30_3 15 -#define CLK_PERI_UART0 16 -#define CLK_PERI_UART1 17 -#define CLK_PERI_UART2 18 -#define CLK_PERI_UART3 19 -#define CLK_PERI_I2C0 20 -#define CLK_PERI_I2C1 21 -#define CLK_PERI_I2C2 22 -#define CLK_PERI_I2C3 23 -#define CLK_PERI_I2C4 24 -#define CLK_PERI_AUXADC 25 -#define CLK_PERI_SPI0 26 -#define CLK_PERI_SPI 27 -#define CLK_PERI_I2C5 28 -#define CLK_PERI_SPI2 29 -#define CLK_PERI_SPI3 30 -#define CLK_PERI_SPI5 31 -#define CLK_PERI_UART4 32 -#define CLK_PERI_SFLASH 33 -#define CLK_PERI_GMAC 34 -#define CLK_PERI_PCIE0 35 -#define CLK_PERI_PCIE1 36 -#define CLK_PERI_GMAC_PCLK 37 -#define CLK_PERI_MSDC50_0_EN 38 -#define CLK_PERI_MSDC30_1_EN 39 -#define CLK_PERI_MSDC30_2_EN 40 -#define CLK_PERI_MSDC30_3_EN 41 -#define CLK_PERI_MSDC50_0_HCLK_EN 42 -#define CLK_PERI_MSDC50_3_HCLK_EN 43 -#define CLK_PERI_MSDC30_0_QTR_EN 44 -#define CLK_PERI_MSDC30_3_QTR_EN 45 -#define CLK_PERI_NR_CLK 46 - -/* MCUCFG */ - -#define CLK_MCU_MP0_SEL 0 -#define CLK_MCU_MP2_SEL 1 -#define CLK_MCU_BUS_SEL 2 -#define CLK_MCU_NR_CLK 3 - -/* MFGCFG */ - -#define CLK_MFG_BG3D 0 -#define CLK_MFG_NR_CLK 1 - -/* MMSYS */ - -#define CLK_MM_SMI_COMMON 0 -#define CLK_MM_SMI_LARB0 1 -#define CLK_MM_CAM_MDP 2 -#define CLK_MM_MDP_RDMA0 3 -#define CLK_MM_MDP_RDMA1 4 -#define CLK_MM_MDP_RSZ0 5 -#define CLK_MM_MDP_RSZ1 6 -#define CLK_MM_MDP_RSZ2 7 -#define CLK_MM_MDP_TDSHP0 8 -#define CLK_MM_MDP_TDSHP1 9 -#define CLK_MM_MDP_CROP 10 -#define CLK_MM_MDP_WDMA 11 -#define CLK_MM_MDP_WROT0 12 -#define CLK_MM_MDP_WROT1 13 -#define CLK_MM_FAKE_ENG 14 -#define CLK_MM_MUTEX_32K 15 -#define CLK_MM_DISP_OVL0 16 -#define CLK_MM_DISP_OVL1 17 -#define CLK_MM_DISP_RDMA0 18 -#define CLK_MM_DISP_RDMA1 19 -#define CLK_MM_DISP_RDMA2 20 -#define CLK_MM_DISP_WDMA0 21 -#define CLK_MM_DISP_WDMA1 22 -#define CLK_MM_DISP_COLOR0 23 -#define CLK_MM_DISP_COLOR1 24 -#define CLK_MM_DISP_AAL 25 -#define CLK_MM_DISP_GAMMA 26 -#define CLK_MM_DISP_UFOE 27 -#define CLK_MM_DISP_SPLIT0 28 -#define CLK_MM_DISP_OD 29 -#define CLK_MM_DISP_PWM0_MM 30 -#define CLK_MM_DISP_PWM0_26M 31 -#define CLK_MM_DISP_PWM1_MM 32 -#define CLK_MM_DISP_PWM1_26M 33 -#define CLK_MM_DSI0_ENGINE 34 -#define CLK_MM_DSI0_DIGITAL 35 -#define CLK_MM_DSI1_ENGINE 36 -#define CLK_MM_DSI1_DIGITAL 37 -#define CLK_MM_DPI_PIXEL 38 -#define CLK_MM_DPI_ENGINE 39 -#define CLK_MM_DPI1_PIXEL 40 -#define CLK_MM_DPI1_ENGINE 41 -#define CLK_MM_LVDS_PIXEL 42 -#define CLK_MM_LVDS_CTS 43 -#define CLK_MM_SMI_LARB4 44 -#define CLK_MM_SMI_COMMON1 45 -#define CLK_MM_SMI_LARB5 46 -#define CLK_MM_MDP_RDMA2 47 -#define CLK_MM_MDP_TDSHP2 48 -#define CLK_MM_DISP_OVL2 49 -#define CLK_MM_DISP_WDMA2 50 -#define CLK_MM_DISP_COLOR2 51 -#define CLK_MM_DISP_AAL1 52 -#define CLK_MM_DISP_OD1 53 -#define CLK_MM_LVDS1_PIXEL 54 -#define CLK_MM_LVDS1_CTS 55 -#define CLK_MM_SMI_LARB7 56 -#define CLK_MM_MDP_RDMA3 57 -#define CLK_MM_MDP_WROT2 58 -#define CLK_MM_DSI2 59 -#define CLK_MM_DSI2_DIGITAL 60 -#define CLK_MM_DSI3 61 -#define CLK_MM_DSI3_DIGITAL 62 -#define CLK_MM_NR_CLK 63 - -/* IMGSYS */ - -#define CLK_IMG_SMI_LARB2 0 -#define CLK_IMG_SENINF_SCAM_EN 1 -#define CLK_IMG_SENINF_CAM_EN 2 -#define CLK_IMG_CAM_SV_EN 3 -#define CLK_IMG_CAM_SV1_EN 4 -#define CLK_IMG_CAM_SV2_EN 5 -#define CLK_IMG_NR_CLK 6 - -/* BDPSYS */ - -#define CLK_BDP_BRIDGE_B 0 -#define CLK_BDP_BRIDGE_DRAM 1 -#define CLK_BDP_LARB_DRAM 2 -#define CLK_BDP_WR_CHANNEL_VDI_PXL 3 -#define CLK_BDP_WR_CHANNEL_VDI_DRAM 4 -#define CLK_BDP_WR_CHANNEL_VDI_B 5 -#define CLK_BDP_MT_B 6 -#define CLK_BDP_DISPFMT_27M 7 -#define CLK_BDP_DISPFMT_27M_VDOUT 8 -#define CLK_BDP_DISPFMT_27_74_74 9 -#define CLK_BDP_DISPFMT_2FS 10 -#define CLK_BDP_DISPFMT_2FS_2FS74_148 11 -#define CLK_BDP_DISPFMT_B 12 -#define CLK_BDP_VDO_DRAM 13 -#define CLK_BDP_VDO_2FS 14 -#define CLK_BDP_VDO_B 15 -#define CLK_BDP_WR_CHANNEL_DI_PXL 16 -#define CLK_BDP_WR_CHANNEL_DI_DRAM 17 -#define CLK_BDP_WR_CHANNEL_DI_B 18 -#define CLK_BDP_NR_AGENT 19 -#define CLK_BDP_NR_DRAM 20 -#define CLK_BDP_NR_B 21 -#define CLK_BDP_BRIDGE_RT_B 22 -#define CLK_BDP_BRIDGE_RT_DRAM 23 -#define CLK_BDP_LARB_RT_DRAM 24 -#define CLK_BDP_TVD_TDC 25 -#define CLK_BDP_TVD_54 26 -#define CLK_BDP_TVD_CBUS 27 -#define CLK_BDP_NR_CLK 28 - -/* VDECSYS */ - -#define CLK_VDEC_CKEN 0 -#define CLK_VDEC_LARB1_CKEN 1 -#define CLK_VDEC_IMGRZ_CKEN 2 -#define CLK_VDEC_NR_CLK 3 - -/* VENCSYS */ - -#define CLK_VENC_SMI_COMMON_CON 0 -#define CLK_VENC_VENC 1 -#define CLK_VENC_SMI_LARB6 2 -#define CLK_VENC_NR_CLK 3 - -/* JPGDECSYS */ - -#define CLK_JPGDEC_JPGDEC1 0 -#define CLK_JPGDEC_JPGDEC 1 -#define CLK_JPGDEC_NR_CLK 2 - -#endif /* _DT_BINDINGS_CLK_MT2712_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/mt6779-clk.h b/sys/gnu/dts/include/dt-bindings/clock/mt6779-clk.h deleted file mode 100644 index b083139afbd..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/mt6779-clk.h +++ /dev/null @@ -1,436 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2019 MediaTek Inc. - * Author: Wendell Lin - */ - -#ifndef _DT_BINDINGS_CLK_MT6779_H -#define _DT_BINDINGS_CLK_MT6779_H - -/* TOPCKGEN */ -#define CLK_TOP_AXI 1 -#define CLK_TOP_MM 2 -#define CLK_TOP_CAM 3 -#define CLK_TOP_MFG 4 -#define CLK_TOP_CAMTG 5 -#define CLK_TOP_UART 6 -#define CLK_TOP_SPI 7 -#define CLK_TOP_MSDC50_0_HCLK 8 -#define CLK_TOP_MSDC50_0 9 -#define CLK_TOP_MSDC30_1 10 -#define CLK_TOP_MSDC30_2 11 -#define CLK_TOP_AUD 12 -#define CLK_TOP_AUD_INTBUS 13 -#define CLK_TOP_FPWRAP_ULPOSC 14 -#define CLK_TOP_SCP 15 -#define CLK_TOP_ATB 16 -#define CLK_TOP_SSPM 17 -#define CLK_TOP_DPI0 18 -#define CLK_TOP_SCAM 19 -#define CLK_TOP_AUD_1 20 -#define CLK_TOP_AUD_2 21 -#define CLK_TOP_DISP_PWM 22 -#define CLK_TOP_SSUSB_TOP_XHCI 23 -#define CLK_TOP_USB_TOP 24 -#define CLK_TOP_SPM 25 -#define CLK_TOP_I2C 26 -#define CLK_TOP_F52M_MFG 27 -#define CLK_TOP_SENINF 28 -#define CLK_TOP_DXCC 29 -#define CLK_TOP_CAMTG2 30 -#define CLK_TOP_AUD_ENG1 31 -#define CLK_TOP_AUD_ENG2 32 -#define CLK_TOP_FAES_UFSFDE 33 -#define CLK_TOP_FUFS 34 -#define CLK_TOP_IMG 35 -#define CLK_TOP_DSP 36 -#define CLK_TOP_DSP1 37 -#define CLK_TOP_DSP2 38 -#define CLK_TOP_IPU_IF 39 -#define CLK_TOP_CAMTG3 40 -#define CLK_TOP_CAMTG4 41 -#define CLK_TOP_PMICSPI 42 -#define CLK_TOP_MAINPLL_CK 43 -#define CLK_TOP_MAINPLL_D2 44 -#define CLK_TOP_MAINPLL_D3 45 -#define CLK_TOP_MAINPLL_D5 46 -#define CLK_TOP_MAINPLL_D7 47 -#define CLK_TOP_MAINPLL_D2_D2 48 -#define CLK_TOP_MAINPLL_D2_D4 49 -#define CLK_TOP_MAINPLL_D2_D8 50 -#define CLK_TOP_MAINPLL_D2_D16 51 -#define CLK_TOP_MAINPLL_D3_D2 52 -#define CLK_TOP_MAINPLL_D3_D4 53 -#define CLK_TOP_MAINPLL_D3_D8 54 -#define CLK_TOP_MAINPLL_D5_D2 55 -#define CLK_TOP_MAINPLL_D5_D4 56 -#define CLK_TOP_MAINPLL_D7_D2 57 -#define CLK_TOP_MAINPLL_D7_D4 58 -#define CLK_TOP_UNIVPLL_CK 59 -#define CLK_TOP_UNIVPLL_D2 60 -#define CLK_TOP_UNIVPLL_D3 61 -#define CLK_TOP_UNIVPLL_D5 62 -#define CLK_TOP_UNIVPLL_D7 63 -#define CLK_TOP_UNIVPLL_D2_D2 64 -#define CLK_TOP_UNIVPLL_D2_D4 65 -#define CLK_TOP_UNIVPLL_D2_D8 66 -#define CLK_TOP_UNIVPLL_D3_D2 67 -#define CLK_TOP_UNIVPLL_D3_D4 68 -#define CLK_TOP_UNIVPLL_D3_D8 69 -#define CLK_TOP_UNIVPLL_D5_D2 70 -#define CLK_TOP_UNIVPLL_D5_D4 71 -#define CLK_TOP_UNIVPLL_D5_D8 72 -#define CLK_TOP_APLL1_CK 73 -#define CLK_TOP_APLL1_D2 74 -#define CLK_TOP_APLL1_D4 75 -#define CLK_TOP_APLL1_D8 76 -#define CLK_TOP_APLL2_CK 77 -#define CLK_TOP_APLL2_D2 78 -#define CLK_TOP_APLL2_D4 79 -#define CLK_TOP_APLL2_D8 80 -#define CLK_TOP_TVDPLL_CK 81 -#define CLK_TOP_TVDPLL_D2 82 -#define CLK_TOP_TVDPLL_D4 83 -#define CLK_TOP_TVDPLL_D8 84 -#define CLK_TOP_TVDPLL_D16 85 -#define CLK_TOP_MSDCPLL_CK 86 -#define CLK_TOP_MSDCPLL_D2 87 -#define CLK_TOP_MSDCPLL_D4 88 -#define CLK_TOP_MSDCPLL_D8 89 -#define CLK_TOP_MSDCPLL_D16 90 -#define CLK_TOP_AD_OSC_CK 91 -#define CLK_TOP_OSC_D2 92 -#define CLK_TOP_OSC_D4 93 -#define CLK_TOP_OSC_D8 94 -#define CLK_TOP_OSC_D16 95 -#define CLK_TOP_F26M_CK_D2 96 -#define CLK_TOP_MFGPLL_CK 97 -#define CLK_TOP_UNIVP_192M_CK 98 -#define CLK_TOP_UNIVP_192M_D2 99 -#define CLK_TOP_UNIVP_192M_D4 100 -#define CLK_TOP_UNIVP_192M_D8 101 -#define CLK_TOP_UNIVP_192M_D16 102 -#define CLK_TOP_UNIVP_192M_D32 103 -#define CLK_TOP_MMPLL_CK 104 -#define CLK_TOP_MMPLL_D4 105 -#define CLK_TOP_MMPLL_D4_D2 106 -#define CLK_TOP_MMPLL_D4_D4 107 -#define CLK_TOP_MMPLL_D5 108 -#define CLK_TOP_MMPLL_D5_D2 109 -#define CLK_TOP_MMPLL_D5_D4 110 -#define CLK_TOP_MMPLL_D6 111 -#define CLK_TOP_MMPLL_D7 112 -#define CLK_TOP_CLK26M 113 -#define CLK_TOP_CLK13M 114 -#define CLK_TOP_ADSP 115 -#define CLK_TOP_DPMAIF 116 -#define CLK_TOP_VENC 117 -#define CLK_TOP_VDEC 118 -#define CLK_TOP_CAMTM 119 -#define CLK_TOP_PWM 120 -#define CLK_TOP_ADSPPLL_CK 121 -#define CLK_TOP_I2S0_M_SEL 122 -#define CLK_TOP_I2S1_M_SEL 123 -#define CLK_TOP_I2S2_M_SEL 124 -#define CLK_TOP_I2S3_M_SEL 125 -#define CLK_TOP_I2S4_M_SEL 126 -#define CLK_TOP_I2S5_M_SEL 127 -#define CLK_TOP_APLL12_DIV0 128 -#define CLK_TOP_APLL12_DIV1 129 -#define CLK_TOP_APLL12_DIV2 130 -#define CLK_TOP_APLL12_DIV3 131 -#define CLK_TOP_APLL12_DIV4 132 -#define CLK_TOP_APLL12_DIVB 133 -#define CLK_TOP_APLL12_DIV5 134 -#define CLK_TOP_IPE 135 -#define CLK_TOP_DPE 136 -#define CLK_TOP_CCU 137 -#define CLK_TOP_DSP3 138 -#define CLK_TOP_SENINF1 139 -#define CLK_TOP_SENINF2 140 -#define CLK_TOP_AUD_H 141 -#define CLK_TOP_CAMTG5 142 -#define CLK_TOP_TVDPLL_MAINPLL_D2_CK 143 -#define CLK_TOP_AD_OSC2_CK 144 -#define CLK_TOP_OSC2_D2 145 -#define CLK_TOP_OSC2_D3 146 -#define CLK_TOP_FMEM_466M_CK 147 -#define CLK_TOP_ADSPPLL_D4 148 -#define CLK_TOP_ADSPPLL_D5 149 -#define CLK_TOP_ADSPPLL_D6 150 -#define CLK_TOP_OSC_D10 151 -#define CLK_TOP_UNIVPLL_D3_D16 152 -#define CLK_TOP_NR_CLK 153 - -/* APMIXED */ -#define CLK_APMIXED_ARMPLL_LL 1 -#define CLK_APMIXED_ARMPLL_BL 2 -#define CLK_APMIXED_ARMPLL_BB 3 -#define CLK_APMIXED_CCIPLL 4 -#define CLK_APMIXED_MAINPLL 5 -#define CLK_APMIXED_UNIV2PLL 6 -#define CLK_APMIXED_MSDCPLL 7 -#define CLK_APMIXED_ADSPPLL 8 -#define CLK_APMIXED_MMPLL 9 -#define CLK_APMIXED_MFGPLL 10 -#define CLK_APMIXED_TVDPLL 11 -#define CLK_APMIXED_APLL1 12 -#define CLK_APMIXED_APLL2 13 -#define CLK_APMIXED_SSUSB26M 14 -#define CLK_APMIXED_APPLL26M 15 -#define CLK_APMIXED_MIPIC0_26M 16 -#define CLK_APMIXED_MDPLLGP26M 17 -#define CLK_APMIXED_MM_F26M 18 -#define CLK_APMIXED_UFS26M 19 -#define CLK_APMIXED_MIPIC1_26M 20 -#define CLK_APMIXED_MEMPLL26M 21 -#define CLK_APMIXED_CLKSQ_LVPLL_26M 22 -#define CLK_APMIXED_MIPID0_26M 23 -#define CLK_APMIXED_MIPID1_26M 24 -#define CLK_APMIXED_NR_CLK 25 - -/* CAMSYS */ -#define CLK_CAM_LARB10 1 -#define CLK_CAM_DFP_VAD 2 -#define CLK_CAM_LARB11 3 -#define CLK_CAM_LARB9 4 -#define CLK_CAM_CAM 5 -#define CLK_CAM_CAMTG 6 -#define CLK_CAM_SENINF 7 -#define CLK_CAM_CAMSV0 8 -#define CLK_CAM_CAMSV1 9 -#define CLK_CAM_CAMSV2 10 -#define CLK_CAM_CAMSV3 11 -#define CLK_CAM_CCU 12 -#define CLK_CAM_FAKE_ENG 13 -#define CLK_CAM_NR_CLK 14 - -/* INFRA */ -#define CLK_INFRA_PMIC_TMR 1 -#define CLK_INFRA_PMIC_AP 2 -#define CLK_INFRA_PMIC_MD 3 -#define CLK_INFRA_PMIC_CONN 4 -#define CLK_INFRA_SCPSYS 5 -#define CLK_INFRA_SEJ 6 -#define CLK_INFRA_APXGPT 7 -#define CLK_INFRA_ICUSB 8 -#define CLK_INFRA_GCE 9 -#define CLK_INFRA_THERM 10 -#define CLK_INFRA_I2C0 11 -#define CLK_INFRA_I2C1 12 -#define CLK_INFRA_I2C2 13 -#define CLK_INFRA_I2C3 14 -#define CLK_INFRA_PWM_HCLK 15 -#define CLK_INFRA_PWM1 16 -#define CLK_INFRA_PWM2 17 -#define CLK_INFRA_PWM3 18 -#define CLK_INFRA_PWM4 19 -#define CLK_INFRA_PWM 20 -#define CLK_INFRA_UART0 21 -#define CLK_INFRA_UART1 22 -#define CLK_INFRA_UART2 23 -#define CLK_INFRA_UART3 24 -#define CLK_INFRA_GCE_26M 25 -#define CLK_INFRA_CQ_DMA_FPC 26 -#define CLK_INFRA_BTIF 27 -#define CLK_INFRA_SPI0 28 -#define CLK_INFRA_MSDC0 29 -#define CLK_INFRA_MSDC1 30 -#define CLK_INFRA_MSDC2 31 -#define CLK_INFRA_MSDC0_SCK 32 -#define CLK_INFRA_DVFSRC 33 -#define CLK_INFRA_GCPU 34 -#define CLK_INFRA_TRNG 35 -#define CLK_INFRA_AUXADC 36 -#define CLK_INFRA_CPUM 37 -#define CLK_INFRA_CCIF1_AP 38 -#define CLK_INFRA_CCIF1_MD 39 -#define CLK_INFRA_AUXADC_MD 40 -#define CLK_INFRA_MSDC1_SCK 41 -#define CLK_INFRA_MSDC2_SCK 42 -#define CLK_INFRA_AP_DMA 43 -#define CLK_INFRA_XIU 44 -#define CLK_INFRA_DEVICE_APC 45 -#define CLK_INFRA_CCIF_AP 46 -#define CLK_INFRA_DEBUGSYS 47 -#define CLK_INFRA_AUD 48 -#define CLK_INFRA_CCIF_MD 49 -#define CLK_INFRA_DXCC_SEC_CORE 50 -#define CLK_INFRA_DXCC_AO 51 -#define CLK_INFRA_DRAMC_F26M 52 -#define CLK_INFRA_IRTX 53 -#define CLK_INFRA_DISP_PWM 54 -#define CLK_INFRA_DPMAIF_CK 55 -#define CLK_INFRA_AUD_26M_BCLK 56 -#define CLK_INFRA_SPI1 57 -#define CLK_INFRA_I2C4 58 -#define CLK_INFRA_MODEM_TEMP_SHARE 59 -#define CLK_INFRA_SPI2 60 -#define CLK_INFRA_SPI3 61 -#define CLK_INFRA_UNIPRO_SCK 62 -#define CLK_INFRA_UNIPRO_TICK 63 -#define CLK_INFRA_UFS_MP_SAP_BCLK 64 -#define CLK_INFRA_MD32_BCLK 65 -#define CLK_INFRA_SSPM 66 -#define CLK_INFRA_UNIPRO_MBIST 67 -#define CLK_INFRA_SSPM_BUS_HCLK 68 -#define CLK_INFRA_I2C5 69 -#define CLK_INFRA_I2C5_ARBITER 70 -#define CLK_INFRA_I2C5_IMM 71 -#define CLK_INFRA_I2C1_ARBITER 72 -#define CLK_INFRA_I2C1_IMM 73 -#define CLK_INFRA_I2C2_ARBITER 74 -#define CLK_INFRA_I2C2_IMM 75 -#define CLK_INFRA_SPI4 76 -#define CLK_INFRA_SPI5 77 -#define CLK_INFRA_CQ_DMA 78 -#define CLK_INFRA_UFS 79 -#define CLK_INFRA_AES_UFSFDE 80 -#define CLK_INFRA_UFS_TICK 81 -#define CLK_INFRA_MSDC0_SELF 82 -#define CLK_INFRA_MSDC1_SELF 83 -#define CLK_INFRA_MSDC2_SELF 84 -#define CLK_INFRA_SSPM_26M_SELF 85 -#define CLK_INFRA_SSPM_32K_SELF 86 -#define CLK_INFRA_UFS_AXI 87 -#define CLK_INFRA_I2C6 88 -#define CLK_INFRA_AP_MSDC0 89 -#define CLK_INFRA_MD_MSDC0 90 -#define CLK_INFRA_USB 91 -#define CLK_INFRA_DEVMPU_BCLK 92 -#define CLK_INFRA_CCIF2_AP 93 -#define CLK_INFRA_CCIF2_MD 94 -#define CLK_INFRA_CCIF3_AP 95 -#define CLK_INFRA_CCIF3_MD 96 -#define CLK_INFRA_SEJ_F13M 97 -#define CLK_INFRA_AES_BCLK 98 -#define CLK_INFRA_I2C7 99 -#define CLK_INFRA_I2C8 100 -#define CLK_INFRA_FBIST2FPC 101 -#define CLK_INFRA_CCIF4_AP 102 -#define CLK_INFRA_CCIF4_MD 103 -#define CLK_INFRA_FADSP 104 -#define CLK_INFRA_SSUSB_XHCI 105 -#define CLK_INFRA_SPI6 106 -#define CLK_INFRA_SPI7 107 -#define CLK_INFRA_NR_CLK 108 - -/* MFGCFG */ -#define CLK_MFGCFG_BG3D 1 -#define CLK_MFGCFG_NR_CLK 2 - -/* IMG */ -#define CLK_IMG_WPE_A 1 -#define CLK_IMG_MFB 2 -#define CLK_IMG_DIP 3 -#define CLK_IMG_LARB6 4 -#define CLK_IMG_LARB5 5 -#define CLK_IMG_NR_CLK 6 - -/* IPE */ -#define CLK_IPE_LARB7 1 -#define CLK_IPE_LARB8 2 -#define CLK_IPE_SMI_SUBCOM 3 -#define CLK_IPE_FD 4 -#define CLK_IPE_FE 5 -#define CLK_IPE_RSC 6 -#define CLK_IPE_DPE 7 -#define CLK_IPE_NR_CLK 8 - -/* MM_CONFIG */ -#define CLK_MM_SMI_COMMON 1 -#define CLK_MM_SMI_LARB0 2 -#define CLK_MM_SMI_LARB1 3 -#define CLK_MM_GALS_COMM0 4 -#define CLK_MM_GALS_COMM1 5 -#define CLK_MM_GALS_CCU2MM 6 -#define CLK_MM_GALS_IPU12MM 7 -#define CLK_MM_GALS_IMG2MM 8 -#define CLK_MM_GALS_CAM2MM 9 -#define CLK_MM_GALS_IPU2MM 10 -#define CLK_MM_MDP_DL_TXCK 11 -#define CLK_MM_IPU_DL_TXCK 12 -#define CLK_MM_MDP_RDMA0 13 -#define CLK_MM_MDP_RDMA1 14 -#define CLK_MM_MDP_RSZ0 15 -#define CLK_MM_MDP_RSZ1 16 -#define CLK_MM_MDP_TDSHP 17 -#define CLK_MM_MDP_WROT0 18 -#define CLK_MM_FAKE_ENG 19 -#define CLK_MM_DISP_OVL0 20 -#define CLK_MM_DISP_OVL0_2L 21 -#define CLK_MM_DISP_OVL1_2L 22 -#define CLK_MM_DISP_RDMA0 23 -#define CLK_MM_DISP_RDMA1 24 -#define CLK_MM_DISP_WDMA0 25 -#define CLK_MM_DISP_COLOR0 26 -#define CLK_MM_DISP_CCORR0 27 -#define CLK_MM_DISP_AAL0 28 -#define CLK_MM_DISP_GAMMA0 29 -#define CLK_MM_DISP_DITHER0 30 -#define CLK_MM_DISP_SPLIT 31 -#define CLK_MM_DSI0_MM_CK 32 -#define CLK_MM_DSI0_IF_CK 33 -#define CLK_MM_DPI_MM_CK 34 -#define CLK_MM_DPI_IF_CK 35 -#define CLK_MM_FAKE_ENG2 36 -#define CLK_MM_MDP_DL_RX_CK 37 -#define CLK_MM_IPU_DL_RX_CK 38 -#define CLK_MM_26M 39 -#define CLK_MM_MM_R2Y 40 -#define CLK_MM_DISP_RSZ 41 -#define CLK_MM_MDP_WDMA0 42 -#define CLK_MM_MDP_AAL 43 -#define CLK_MM_MDP_HDR 44 -#define CLK_MM_DBI_MM_CK 45 -#define CLK_MM_DBI_IF_CK 46 -#define CLK_MM_MDP_WROT1 47 -#define CLK_MM_DISP_POSTMASK0 48 -#define CLK_MM_DISP_HRT_BW 49 -#define CLK_MM_DISP_OVL_FBDC 50 -#define CLK_MM_NR_CLK 51 - -/* VDEC_GCON */ -#define CLK_VDEC_VDEC 1 -#define CLK_VDEC_LARB1 2 -#define CLK_VDEC_GCON_NR_CLK 3 - -/* VENC_GCON */ -#define CLK_VENC_GCON_LARB 1 -#define CLK_VENC_GCON_VENC 2 -#define CLK_VENC_GCON_JPGENC 3 -#define CLK_VENC_GCON_GALS 4 -#define CLK_VENC_GCON_NR_CLK 5 - -/* AUD */ -#define CLK_AUD_AFE 1 -#define CLK_AUD_22M 2 -#define CLK_AUD_24M 3 -#define CLK_AUD_APLL2_TUNER 4 -#define CLK_AUD_APLL_TUNER 5 -#define CLK_AUD_TDM 6 -#define CLK_AUD_ADC 7 -#define CLK_AUD_DAC 8 -#define CLK_AUD_DAC_PREDIS 9 -#define CLK_AUD_TML 10 -#define CLK_AUD_NLE 11 -#define CLK_AUD_I2S1_BCLK_SW 12 -#define CLK_AUD_I2S2_BCLK_SW 13 -#define CLK_AUD_I2S3_BCLK_SW 14 -#define CLK_AUD_I2S4_BCLK_SW 15 -#define CLK_AUD_I2S5_BCLK_SW 16 -#define CLK_AUD_CONN_I2S_ASRC 17 -#define CLK_AUD_GENERAL1_ASRC 18 -#define CLK_AUD_GENERAL2_ASRC 19 -#define CLK_AUD_DAC_HIRES 20 -#define CLK_AUD_PDN_ADDA6_ADC 21 -#define CLK_AUD_ADC_HIRES 22 -#define CLK_AUD_ADC_HIRES_TML 23 -#define CLK_AUD_ADDA6_ADC_HIRES 24 -#define CLK_AUD_3RD_DAC 25 -#define CLK_AUD_3RD_DAC_PREDIS 26 -#define CLK_AUD_3RD_DAC_TML 27 -#define CLK_AUD_3RD_DAC_HIRES 28 -#define CLK_AUD_NR_CLK 29 - -#endif /* _DT_BINDINGS_CLK_MT6779_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/mt6797-clk.h b/sys/gnu/dts/include/dt-bindings/clock/mt6797-clk.h deleted file mode 100644 index dc23ddb754b..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/mt6797-clk.h +++ /dev/null @@ -1,273 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2017 MediaTek Inc. - * Author: Kevin Chen - */ - -#ifndef _DT_BINDINGS_CLK_MT6797_H -#define _DT_BINDINGS_CLK_MT6797_H - -/* TOPCKGEN */ -#define CLK_TOP_MUX_ULPOSC_AXI_CK_MUX_PRE 1 -#define CLK_TOP_MUX_ULPOSC_AXI_CK_MUX 2 -#define CLK_TOP_MUX_AXI 3 -#define CLK_TOP_MUX_MEM 4 -#define CLK_TOP_MUX_DDRPHYCFG 5 -#define CLK_TOP_MUX_MM 6 -#define CLK_TOP_MUX_PWM 7 -#define CLK_TOP_MUX_VDEC 8 -#define CLK_TOP_MUX_VENC 9 -#define CLK_TOP_MUX_MFG 10 -#define CLK_TOP_MUX_CAMTG 11 -#define CLK_TOP_MUX_UART 12 -#define CLK_TOP_MUX_SPI 13 -#define CLK_TOP_MUX_ULPOSC_SPI_CK_MUX 14 -#define CLK_TOP_MUX_USB20 15 -#define CLK_TOP_MUX_MSDC50_0_HCLK 16 -#define CLK_TOP_MUX_MSDC50_0 17 -#define CLK_TOP_MUX_MSDC30_1 18 -#define CLK_TOP_MUX_MSDC30_2 19 -#define CLK_TOP_MUX_AUDIO 20 -#define CLK_TOP_MUX_AUD_INTBUS 21 -#define CLK_TOP_MUX_PMICSPI 22 -#define CLK_TOP_MUX_SCP 23 -#define CLK_TOP_MUX_ATB 24 -#define CLK_TOP_MUX_MJC 25 -#define CLK_TOP_MUX_DPI0 26 -#define CLK_TOP_MUX_AUD_1 27 -#define CLK_TOP_MUX_AUD_2 28 -#define CLK_TOP_MUX_SSUSB_TOP_SYS 29 -#define CLK_TOP_MUX_SPM 30 -#define CLK_TOP_MUX_BSI_SPI 31 -#define CLK_TOP_MUX_AUDIO_H 32 -#define CLK_TOP_MUX_ANC_MD32 33 -#define CLK_TOP_MUX_MFG_52M 34 -#define CLK_TOP_SYSPLL_CK 35 -#define CLK_TOP_SYSPLL_D2 36 -#define CLK_TOP_SYSPLL1_D2 37 -#define CLK_TOP_SYSPLL1_D4 38 -#define CLK_TOP_SYSPLL1_D8 39 -#define CLK_TOP_SYSPLL1_D16 40 -#define CLK_TOP_SYSPLL_D3 41 -#define CLK_TOP_SYSPLL_D3_D3 42 -#define CLK_TOP_SYSPLL2_D2 43 -#define CLK_TOP_SYSPLL2_D4 44 -#define CLK_TOP_SYSPLL2_D8 45 -#define CLK_TOP_SYSPLL_D5 46 -#define CLK_TOP_SYSPLL3_D2 47 -#define CLK_TOP_SYSPLL3_D4 48 -#define CLK_TOP_SYSPLL_D7 49 -#define CLK_TOP_SYSPLL4_D2 50 -#define CLK_TOP_SYSPLL4_D4 51 -#define CLK_TOP_UNIVPLL_CK 52 -#define CLK_TOP_UNIVPLL_D7 53 -#define CLK_TOP_UNIVPLL_D26 54 -#define CLK_TOP_SSUSB_PHY_48M_CK 55 -#define CLK_TOP_USB_PHY48M_CK 56 -#define CLK_TOP_UNIVPLL_D2 57 -#define CLK_TOP_UNIVPLL1_D2 58 -#define CLK_TOP_UNIVPLL1_D4 59 -#define CLK_TOP_UNIVPLL1_D8 60 -#define CLK_TOP_UNIVPLL_D3 61 -#define CLK_TOP_UNIVPLL2_D2 62 -#define CLK_TOP_UNIVPLL2_D4 63 -#define CLK_TOP_UNIVPLL2_D8 64 -#define CLK_TOP_UNIVPLL_D5 65 -#define CLK_TOP_UNIVPLL3_D2 66 -#define CLK_TOP_UNIVPLL3_D4 67 -#define CLK_TOP_UNIVPLL3_D8 68 -#define CLK_TOP_ULPOSC_CK_ORG 69 -#define CLK_TOP_ULPOSC_CK 70 -#define CLK_TOP_ULPOSC_D2 71 -#define CLK_TOP_ULPOSC_D3 72 -#define CLK_TOP_ULPOSC_D4 73 -#define CLK_TOP_ULPOSC_D8 74 -#define CLK_TOP_ULPOSC_D10 75 -#define CLK_TOP_APLL1_CK 76 -#define CLK_TOP_APLL2_CK 77 -#define CLK_TOP_MFGPLL_CK 78 -#define CLK_TOP_MFGPLL_D2 79 -#define CLK_TOP_IMGPLL_CK 80 -#define CLK_TOP_IMGPLL_D2 81 -#define CLK_TOP_IMGPLL_D4 82 -#define CLK_TOP_CODECPLL_CK 83 -#define CLK_TOP_CODECPLL_D2 84 -#define CLK_TOP_VDECPLL_CK 85 -#define CLK_TOP_TVDPLL_CK 86 -#define CLK_TOP_TVDPLL_D2 87 -#define CLK_TOP_TVDPLL_D4 88 -#define CLK_TOP_TVDPLL_D8 89 -#define CLK_TOP_TVDPLL_D16 90 -#define CLK_TOP_MSDCPLL_CK 91 -#define CLK_TOP_MSDCPLL_D2 92 -#define CLK_TOP_MSDCPLL_D4 93 -#define CLK_TOP_MSDCPLL_D8 94 -#define CLK_TOP_NR 95 - -/* APMIXED_SYS */ -#define CLK_APMIXED_MAINPLL 1 -#define CLK_APMIXED_UNIVPLL 2 -#define CLK_APMIXED_MFGPLL 3 -#define CLK_APMIXED_MSDCPLL 4 -#define CLK_APMIXED_IMGPLL 5 -#define CLK_APMIXED_TVDPLL 6 -#define CLK_APMIXED_CODECPLL 7 -#define CLK_APMIXED_VDECPLL 8 -#define CLK_APMIXED_APLL1 9 -#define CLK_APMIXED_APLL2 10 -#define CLK_APMIXED_NR 11 - -/* INFRA_SYS */ -#define CLK_INFRA_PMIC_TMR 1 -#define CLK_INFRA_PMIC_AP 2 -#define CLK_INFRA_PMIC_MD 3 -#define CLK_INFRA_PMIC_CONN 4 -#define CLK_INFRA_SCP 5 -#define CLK_INFRA_SEJ 6 -#define CLK_INFRA_APXGPT 7 -#define CLK_INFRA_SEJ_13M 8 -#define CLK_INFRA_ICUSB 9 -#define CLK_INFRA_GCE 10 -#define CLK_INFRA_THERM 11 -#define CLK_INFRA_I2C0 12 -#define CLK_INFRA_I2C1 13 -#define CLK_INFRA_I2C2 14 -#define CLK_INFRA_I2C3 15 -#define CLK_INFRA_PWM_HCLK 16 -#define CLK_INFRA_PWM1 17 -#define CLK_INFRA_PWM2 18 -#define CLK_INFRA_PWM3 19 -#define CLK_INFRA_PWM4 20 -#define CLK_INFRA_PWM 21 -#define CLK_INFRA_UART0 22 -#define CLK_INFRA_UART1 23 -#define CLK_INFRA_UART2 24 -#define CLK_INFRA_UART3 25 -#define CLK_INFRA_MD2MD_CCIF_0 26 -#define CLK_INFRA_MD2MD_CCIF_1 27 -#define CLK_INFRA_MD2MD_CCIF_2 28 -#define CLK_INFRA_FHCTL 29 -#define CLK_INFRA_BTIF 30 -#define CLK_INFRA_MD2MD_CCIF_3 31 -#define CLK_INFRA_SPI 32 -#define CLK_INFRA_MSDC0 33 -#define CLK_INFRA_MD2MD_CCIF_4 34 -#define CLK_INFRA_MSDC1 35 -#define CLK_INFRA_MSDC2 36 -#define CLK_INFRA_MD2MD_CCIF_5 37 -#define CLK_INFRA_GCPU 38 -#define CLK_INFRA_TRNG 39 -#define CLK_INFRA_AUXADC 40 -#define CLK_INFRA_CPUM 41 -#define CLK_INFRA_AP_C2K_CCIF_0 42 -#define CLK_INFRA_AP_C2K_CCIF_1 43 -#define CLK_INFRA_CLDMA 44 -#define CLK_INFRA_DISP_PWM 45 -#define CLK_INFRA_AP_DMA 46 -#define CLK_INFRA_DEVICE_APC 47 -#define CLK_INFRA_L2C_SRAM 48 -#define CLK_INFRA_CCIF_AP 49 -#define CLK_INFRA_AUDIO 50 -#define CLK_INFRA_CCIF_MD 51 -#define CLK_INFRA_DRAMC_F26M 52 -#define CLK_INFRA_I2C4 53 -#define CLK_INFRA_I2C_APPM 54 -#define CLK_INFRA_I2C_GPUPM 55 -#define CLK_INFRA_I2C2_IMM 56 -#define CLK_INFRA_I2C2_ARB 57 -#define CLK_INFRA_I2C3_IMM 58 -#define CLK_INFRA_I2C3_ARB 59 -#define CLK_INFRA_I2C5 60 -#define CLK_INFRA_SYS_CIRQ 61 -#define CLK_INFRA_SPI1 62 -#define CLK_INFRA_DRAMC_B_F26M 63 -#define CLK_INFRA_ANC_MD32 64 -#define CLK_INFRA_ANC_MD32_32K 65 -#define CLK_INFRA_DVFS_SPM1 66 -#define CLK_INFRA_AES_TOP0 67 -#define CLK_INFRA_AES_TOP1 68 -#define CLK_INFRA_SSUSB_BUS 69 -#define CLK_INFRA_SPI2 70 -#define CLK_INFRA_SPI3 71 -#define CLK_INFRA_SPI4 72 -#define CLK_INFRA_SPI5 73 -#define CLK_INFRA_IRTX 74 -#define CLK_INFRA_SSUSB_SYS 75 -#define CLK_INFRA_SSUSB_REF 76 -#define CLK_INFRA_AUDIO_26M 77 -#define CLK_INFRA_AUDIO_26M_PAD_TOP 78 -#define CLK_INFRA_MODEM_TEMP_SHARE 79 -#define CLK_INFRA_VAD_WRAP_SOC 80 -#define CLK_INFRA_DRAMC_CONF 81 -#define CLK_INFRA_DRAMC_B_CONF 82 -#define CLK_INFRA_MFG_VCG 83 -#define CLK_INFRA_13M 84 -#define CLK_INFRA_NR 85 - -/* IMG_SYS */ -#define CLK_IMG_FDVT 1 -#define CLK_IMG_DPE 2 -#define CLK_IMG_DIP 3 -#define CLK_IMG_LARB6 4 -#define CLK_IMG_NR 5 - -/* MM_SYS */ -#define CLK_MM_SMI_COMMON 1 -#define CLK_MM_SMI_LARB0 2 -#define CLK_MM_SMI_LARB5 3 -#define CLK_MM_CAM_MDP 4 -#define CLK_MM_MDP_RDMA0 5 -#define CLK_MM_MDP_RDMA1 6 -#define CLK_MM_MDP_RSZ0 7 -#define CLK_MM_MDP_RSZ1 8 -#define CLK_MM_MDP_RSZ2 9 -#define CLK_MM_MDP_TDSHP 10 -#define CLK_MM_MDP_COLOR 11 -#define CLK_MM_MDP_WDMA 12 -#define CLK_MM_MDP_WROT0 13 -#define CLK_MM_MDP_WROT1 14 -#define CLK_MM_FAKE_ENG 15 -#define CLK_MM_DISP_OVL0 16 -#define CLK_MM_DISP_OVL1 17 -#define CLK_MM_DISP_OVL0_2L 18 -#define CLK_MM_DISP_OVL1_2L 19 -#define CLK_MM_DISP_RDMA0 20 -#define CLK_MM_DISP_RDMA1 21 -#define CLK_MM_DISP_WDMA0 22 -#define CLK_MM_DISP_WDMA1 23 -#define CLK_MM_DISP_COLOR 24 -#define CLK_MM_DISP_CCORR 25 -#define CLK_MM_DISP_AAL 26 -#define CLK_MM_DISP_GAMMA 27 -#define CLK_MM_DISP_OD 28 -#define CLK_MM_DISP_DITHER 29 -#define CLK_MM_DISP_UFOE 30 -#define CLK_MM_DISP_DSC 31 -#define CLK_MM_DISP_SPLIT 32 -#define CLK_MM_DSI0_MM_CLOCK 33 -#define CLK_MM_DSI1_MM_CLOCK 34 -#define CLK_MM_DPI_MM_CLOCK 35 -#define CLK_MM_DPI_INTERFACE_CLOCK 36 -#define CLK_MM_LARB4_AXI_ASIF_MM_CLOCK 37 -#define CLK_MM_LARB4_AXI_ASIF_MJC_CLOCK 38 -#define CLK_MM_DISP_OVL0_MOUT_CLOCK 39 -#define CLK_MM_FAKE_ENG2 40 -#define CLK_MM_DSI0_INTERFACE_CLOCK 41 -#define CLK_MM_DSI1_INTERFACE_CLOCK 42 -#define CLK_MM_NR 43 - -/* VDEC_SYS */ -#define CLK_VDEC_CKEN_ENG 1 -#define CLK_VDEC_ACTIVE 2 -#define CLK_VDEC_CKEN 3 -#define CLK_VDEC_LARB1_CKEN 4 -#define CLK_VDEC_NR 5 - -/* VENC_SYS */ -#define CLK_VENC_0 1 -#define CLK_VENC_1 2 -#define CLK_VENC_2 3 -#define CLK_VENC_3 4 -#define CLK_VENC_NR 5 - -#endif /* _DT_BINDINGS_CLK_MT6797_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/mt7622-clk.h b/sys/gnu/dts/include/dt-bindings/clock/mt7622-clk.h deleted file mode 100644 index c12e7eab078..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/mt7622-clk.h +++ /dev/null @@ -1,282 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2017 MediaTek Inc. - * Author: Chen Zhong - */ - -#ifndef _DT_BINDINGS_CLK_MT7622_H -#define _DT_BINDINGS_CLK_MT7622_H - -/* TOPCKGEN */ - -#define CLK_TOP_TO_U2_PHY 0 -#define CLK_TOP_TO_U2_PHY_1P 1 -#define CLK_TOP_PCIE0_PIPE_EN 2 -#define CLK_TOP_PCIE1_PIPE_EN 3 -#define CLK_TOP_SSUSB_TX250M 4 -#define CLK_TOP_SSUSB_EQ_RX250M 5 -#define CLK_TOP_SSUSB_CDR_REF 6 -#define CLK_TOP_SSUSB_CDR_FB 7 -#define CLK_TOP_SATA_ASIC 8 -#define CLK_TOP_SATA_RBC 9 -#define CLK_TOP_TO_USB3_SYS 10 -#define CLK_TOP_P1_1MHZ 11 -#define CLK_TOP_4MHZ 12 -#define CLK_TOP_P0_1MHZ 13 -#define CLK_TOP_TXCLK_SRC_PRE 14 -#define CLK_TOP_RTC 15 -#define CLK_TOP_MEMPLL 16 -#define CLK_TOP_DMPLL 17 -#define CLK_TOP_SYSPLL_D2 18 -#define CLK_TOP_SYSPLL1_D2 19 -#define CLK_TOP_SYSPLL1_D4 20 -#define CLK_TOP_SYSPLL1_D8 21 -#define CLK_TOP_SYSPLL2_D4 22 -#define CLK_TOP_SYSPLL2_D8 23 -#define CLK_TOP_SYSPLL_D5 24 -#define CLK_TOP_SYSPLL3_D2 25 -#define CLK_TOP_SYSPLL3_D4 26 -#define CLK_TOP_SYSPLL4_D2 27 -#define CLK_TOP_SYSPLL4_D4 28 -#define CLK_TOP_SYSPLL4_D16 29 -#define CLK_TOP_UNIVPLL 30 -#define CLK_TOP_UNIVPLL_D2 31 -#define CLK_TOP_UNIVPLL1_D2 32 -#define CLK_TOP_UNIVPLL1_D4 33 -#define CLK_TOP_UNIVPLL1_D8 34 -#define CLK_TOP_UNIVPLL1_D16 35 -#define CLK_TOP_UNIVPLL2_D2 36 -#define CLK_TOP_UNIVPLL2_D4 37 -#define CLK_TOP_UNIVPLL2_D8 38 -#define CLK_TOP_UNIVPLL2_D16 39 -#define CLK_TOP_UNIVPLL_D5 40 -#define CLK_TOP_UNIVPLL3_D2 41 -#define CLK_TOP_UNIVPLL3_D4 42 -#define CLK_TOP_UNIVPLL3_D16 43 -#define CLK_TOP_UNIVPLL_D7 44 -#define CLK_TOP_UNIVPLL_D80_D4 45 -#define CLK_TOP_UNIV48M 46 -#define CLK_TOP_SGMIIPLL 47 -#define CLK_TOP_SGMIIPLL_D2 48 -#define CLK_TOP_AUD1PLL 49 -#define CLK_TOP_AUD2PLL 50 -#define CLK_TOP_AUD_I2S2_MCK 51 -#define CLK_TOP_TO_USB3_REF 52 -#define CLK_TOP_PCIE1_MAC_EN 53 -#define CLK_TOP_PCIE0_MAC_EN 54 -#define CLK_TOP_ETH_500M 55 -#define CLK_TOP_AXI_SEL 56 -#define CLK_TOP_MEM_SEL 57 -#define CLK_TOP_DDRPHYCFG_SEL 58 -#define CLK_TOP_ETH_SEL 59 -#define CLK_TOP_PWM_SEL 60 -#define CLK_TOP_F10M_REF_SEL 61 -#define CLK_TOP_NFI_INFRA_SEL 62 -#define CLK_TOP_FLASH_SEL 63 -#define CLK_TOP_UART_SEL 64 -#define CLK_TOP_SPI0_SEL 65 -#define CLK_TOP_SPI1_SEL 66 -#define CLK_TOP_MSDC50_0_SEL 67 -#define CLK_TOP_MSDC30_0_SEL 68 -#define CLK_TOP_MSDC30_1_SEL 69 -#define CLK_TOP_A1SYS_HP_SEL 70 -#define CLK_TOP_A2SYS_HP_SEL 71 -#define CLK_TOP_INTDIR_SEL 72 -#define CLK_TOP_AUD_INTBUS_SEL 73 -#define CLK_TOP_PMICSPI_SEL 74 -#define CLK_TOP_SCP_SEL 75 -#define CLK_TOP_ATB_SEL 76 -#define CLK_TOP_HIF_SEL 77 -#define CLK_TOP_AUDIO_SEL 78 -#define CLK_TOP_U2_SEL 79 -#define CLK_TOP_AUD1_SEL 80 -#define CLK_TOP_AUD2_SEL 81 -#define CLK_TOP_IRRX_SEL 82 -#define CLK_TOP_IRTX_SEL 83 -#define CLK_TOP_ASM_L_SEL 84 -#define CLK_TOP_ASM_M_SEL 85 -#define CLK_TOP_ASM_H_SEL 86 -#define CLK_TOP_APLL1_SEL 87 -#define CLK_TOP_APLL2_SEL 88 -#define CLK_TOP_I2S0_MCK_SEL 89 -#define CLK_TOP_I2S1_MCK_SEL 90 -#define CLK_TOP_I2S2_MCK_SEL 91 -#define CLK_TOP_I2S3_MCK_SEL 92 -#define CLK_TOP_APLL1_DIV 93 -#define CLK_TOP_APLL2_DIV 94 -#define CLK_TOP_I2S0_MCK_DIV 95 -#define CLK_TOP_I2S1_MCK_DIV 96 -#define CLK_TOP_I2S2_MCK_DIV 97 -#define CLK_TOP_I2S3_MCK_DIV 98 -#define CLK_TOP_A1SYS_HP_DIV 99 -#define CLK_TOP_A2SYS_HP_DIV 100 -#define CLK_TOP_APLL1_DIV_PD 101 -#define CLK_TOP_APLL2_DIV_PD 102 -#define CLK_TOP_I2S0_MCK_DIV_PD 103 -#define CLK_TOP_I2S1_MCK_DIV_PD 104 -#define CLK_TOP_I2S2_MCK_DIV_PD 105 -#define CLK_TOP_I2S3_MCK_DIV_PD 106 -#define CLK_TOP_A1SYS_HP_DIV_PD 107 -#define CLK_TOP_A2SYS_HP_DIV_PD 108 -#define CLK_TOP_NR_CLK 109 - -/* INFRACFG */ - -#define CLK_INFRA_MUX1_SEL 0 -#define CLK_INFRA_DBGCLK_PD 1 -#define CLK_INFRA_AUDIO_PD 2 -#define CLK_INFRA_IRRX_PD 3 -#define CLK_INFRA_APXGPT_PD 4 -#define CLK_INFRA_PMIC_PD 5 -#define CLK_INFRA_TRNG 6 -#define CLK_INFRA_NR_CLK 7 - -/* PERICFG */ - -#define CLK_PERIBUS_SEL 0 -#define CLK_PERI_THERM_PD 1 -#define CLK_PERI_PWM1_PD 2 -#define CLK_PERI_PWM2_PD 3 -#define CLK_PERI_PWM3_PD 4 -#define CLK_PERI_PWM4_PD 5 -#define CLK_PERI_PWM5_PD 6 -#define CLK_PERI_PWM6_PD 7 -#define CLK_PERI_PWM7_PD 8 -#define CLK_PERI_PWM_PD 9 -#define CLK_PERI_AP_DMA_PD 10 -#define CLK_PERI_MSDC30_0_PD 11 -#define CLK_PERI_MSDC30_1_PD 12 -#define CLK_PERI_UART0_PD 13 -#define CLK_PERI_UART1_PD 14 -#define CLK_PERI_UART2_PD 15 -#define CLK_PERI_UART3_PD 16 -#define CLK_PERI_UART4_PD 17 -#define CLK_PERI_BTIF_PD 18 -#define CLK_PERI_I2C0_PD 19 -#define CLK_PERI_I2C1_PD 20 -#define CLK_PERI_I2C2_PD 21 -#define CLK_PERI_SPI1_PD 22 -#define CLK_PERI_AUXADC_PD 23 -#define CLK_PERI_SPI0_PD 24 -#define CLK_PERI_SNFI_PD 25 -#define CLK_PERI_NFI_PD 26 -#define CLK_PERI_NFIECC_PD 27 -#define CLK_PERI_FLASH_PD 28 -#define CLK_PERI_IRTX_PD 29 -#define CLK_PERI_NR_CLK 30 - -/* APMIXEDSYS */ - -#define CLK_APMIXED_ARMPLL 0 -#define CLK_APMIXED_MAINPLL 1 -#define CLK_APMIXED_UNIV2PLL 2 -#define CLK_APMIXED_ETH1PLL 3 -#define CLK_APMIXED_ETH2PLL 4 -#define CLK_APMIXED_AUD1PLL 5 -#define CLK_APMIXED_AUD2PLL 6 -#define CLK_APMIXED_TRGPLL 7 -#define CLK_APMIXED_SGMIPLL 8 -#define CLK_APMIXED_MAIN_CORE_EN 9 -#define CLK_APMIXED_NR_CLK 10 - -/* AUDIOSYS */ - -#define CLK_AUDIO_AFE 0 -#define CLK_AUDIO_HDMI 1 -#define CLK_AUDIO_SPDF 2 -#define CLK_AUDIO_APLL 3 -#define CLK_AUDIO_I2SIN1 4 -#define CLK_AUDIO_I2SIN2 5 -#define CLK_AUDIO_I2SIN3 6 -#define CLK_AUDIO_I2SIN4 7 -#define CLK_AUDIO_I2SO1 8 -#define CLK_AUDIO_I2SO2 9 -#define CLK_AUDIO_I2SO3 10 -#define CLK_AUDIO_I2SO4 11 -#define CLK_AUDIO_ASRCI1 12 -#define CLK_AUDIO_ASRCI2 13 -#define CLK_AUDIO_ASRCO1 14 -#define CLK_AUDIO_ASRCO2 15 -#define CLK_AUDIO_INTDIR 16 -#define CLK_AUDIO_A1SYS 17 -#define CLK_AUDIO_A2SYS 18 -#define CLK_AUDIO_UL1 19 -#define CLK_AUDIO_UL2 20 -#define CLK_AUDIO_UL3 21 -#define CLK_AUDIO_UL4 22 -#define CLK_AUDIO_UL5 23 -#define CLK_AUDIO_UL6 24 -#define CLK_AUDIO_DL1 25 -#define CLK_AUDIO_DL2 26 -#define CLK_AUDIO_DL3 27 -#define CLK_AUDIO_DL4 28 -#define CLK_AUDIO_DL5 29 -#define CLK_AUDIO_DL6 30 -#define CLK_AUDIO_DLMCH 31 -#define CLK_AUDIO_ARB1 32 -#define CLK_AUDIO_AWB 33 -#define CLK_AUDIO_AWB2 34 -#define CLK_AUDIO_DAI 35 -#define CLK_AUDIO_MOD 36 -#define CLK_AUDIO_ASRCI3 37 -#define CLK_AUDIO_ASRCI4 38 -#define CLK_AUDIO_ASRCO3 39 -#define CLK_AUDIO_ASRCO4 40 -#define CLK_AUDIO_MEM_ASRC1 41 -#define CLK_AUDIO_MEM_ASRC2 42 -#define CLK_AUDIO_MEM_ASRC3 43 -#define CLK_AUDIO_MEM_ASRC4 44 -#define CLK_AUDIO_MEM_ASRC5 45 -#define CLK_AUDIO_AFE_CONN 46 -#define CLK_AUDIO_NR_CLK 47 - -/* SSUSBSYS */ - -#define CLK_SSUSB_U2_PHY_1P_EN 0 -#define CLK_SSUSB_U2_PHY_EN 1 -#define CLK_SSUSB_REF_EN 2 -#define CLK_SSUSB_SYS_EN 3 -#define CLK_SSUSB_MCU_EN 4 -#define CLK_SSUSB_DMA_EN 5 -#define CLK_SSUSB_NR_CLK 6 - -/* PCIESYS */ - -#define CLK_PCIE_P1_AUX_EN 0 -#define CLK_PCIE_P1_OBFF_EN 1 -#define CLK_PCIE_P1_AHB_EN 2 -#define CLK_PCIE_P1_AXI_EN 3 -#define CLK_PCIE_P1_MAC_EN 4 -#define CLK_PCIE_P1_PIPE_EN 5 -#define CLK_PCIE_P0_AUX_EN 6 -#define CLK_PCIE_P0_OBFF_EN 7 -#define CLK_PCIE_P0_AHB_EN 8 -#define CLK_PCIE_P0_AXI_EN 9 -#define CLK_PCIE_P0_MAC_EN 10 -#define CLK_PCIE_P0_PIPE_EN 11 -#define CLK_SATA_AHB_EN 12 -#define CLK_SATA_AXI_EN 13 -#define CLK_SATA_ASIC_EN 14 -#define CLK_SATA_RBC_EN 15 -#define CLK_SATA_PM_EN 16 -#define CLK_PCIE_NR_CLK 17 - -/* ETHSYS */ - -#define CLK_ETH_HSDMA_EN 0 -#define CLK_ETH_ESW_EN 1 -#define CLK_ETH_GP2_EN 2 -#define CLK_ETH_GP1_EN 3 -#define CLK_ETH_GP0_EN 4 -#define CLK_ETH_NR_CLK 5 - -/* SGMIISYS */ - -#define CLK_SGMII_TX250M_EN 0 -#define CLK_SGMII_RX250M_EN 1 -#define CLK_SGMII_CDR_REF 2 -#define CLK_SGMII_CDR_FB 3 -#define CLK_SGMII_NR_CLK 4 - -#endif /* _DT_BINDINGS_CLK_MT7622_H */ - diff --git a/sys/gnu/dts/include/dt-bindings/clock/mt7629-clk.h b/sys/gnu/dts/include/dt-bindings/clock/mt7629-clk.h deleted file mode 100644 index ad8e6d7f015..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/mt7629-clk.h +++ /dev/null @@ -1,203 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2018 MediaTek Inc. - */ - -#ifndef _DT_BINDINGS_CLK_MT7629_H -#define _DT_BINDINGS_CLK_MT7629_H - -/* TOPCKGEN */ -#define CLK_TOP_TO_U2_PHY 0 -#define CLK_TOP_TO_U2_PHY_1P 1 -#define CLK_TOP_PCIE0_PIPE_EN 2 -#define CLK_TOP_PCIE1_PIPE_EN 3 -#define CLK_TOP_SSUSB_TX250M 4 -#define CLK_TOP_SSUSB_EQ_RX250M 5 -#define CLK_TOP_SSUSB_CDR_REF 6 -#define CLK_TOP_SSUSB_CDR_FB 7 -#define CLK_TOP_SATA_ASIC 8 -#define CLK_TOP_SATA_RBC 9 -#define CLK_TOP_TO_USB3_SYS 10 -#define CLK_TOP_P1_1MHZ 11 -#define CLK_TOP_4MHZ 12 -#define CLK_TOP_P0_1MHZ 13 -#define CLK_TOP_ETH_500M 14 -#define CLK_TOP_TXCLK_SRC_PRE 15 -#define CLK_TOP_RTC 16 -#define CLK_TOP_PWM_QTR_26M 17 -#define CLK_TOP_CPUM_TCK_IN 18 -#define CLK_TOP_TO_USB3_DA_TOP 19 -#define CLK_TOP_MEMPLL 20 -#define CLK_TOP_DMPLL 21 -#define CLK_TOP_DMPLL_D4 22 -#define CLK_TOP_DMPLL_D8 23 -#define CLK_TOP_SYSPLL_D2 24 -#define CLK_TOP_SYSPLL1_D2 25 -#define CLK_TOP_SYSPLL1_D4 26 -#define CLK_TOP_SYSPLL1_D8 27 -#define CLK_TOP_SYSPLL1_D16 28 -#define CLK_TOP_SYSPLL2_D2 29 -#define CLK_TOP_SYSPLL2_D4 30 -#define CLK_TOP_SYSPLL2_D8 31 -#define CLK_TOP_SYSPLL_D5 32 -#define CLK_TOP_SYSPLL3_D2 33 -#define CLK_TOP_SYSPLL3_D4 34 -#define CLK_TOP_SYSPLL_D7 35 -#define CLK_TOP_SYSPLL4_D2 36 -#define CLK_TOP_SYSPLL4_D4 37 -#define CLK_TOP_SYSPLL4_D16 38 -#define CLK_TOP_UNIVPLL 39 -#define CLK_TOP_UNIVPLL1_D2 40 -#define CLK_TOP_UNIVPLL1_D4 41 -#define CLK_TOP_UNIVPLL1_D8 42 -#define CLK_TOP_UNIVPLL_D3 43 -#define CLK_TOP_UNIVPLL2_D2 44 -#define CLK_TOP_UNIVPLL2_D4 45 -#define CLK_TOP_UNIVPLL2_D8 46 -#define CLK_TOP_UNIVPLL2_D16 47 -#define CLK_TOP_UNIVPLL_D5 48 -#define CLK_TOP_UNIVPLL3_D2 49 -#define CLK_TOP_UNIVPLL3_D4 50 -#define CLK_TOP_UNIVPLL3_D16 51 -#define CLK_TOP_UNIVPLL_D7 52 -#define CLK_TOP_UNIVPLL_D80_D4 53 -#define CLK_TOP_UNIV48M 54 -#define CLK_TOP_SGMIIPLL_D2 55 -#define CLK_TOP_CLKXTAL_D4 56 -#define CLK_TOP_HD_FAXI 57 -#define CLK_TOP_FAXI 58 -#define CLK_TOP_F_FAUD_INTBUS 59 -#define CLK_TOP_AP2WBHIF_HCLK 60 -#define CLK_TOP_10M_INFRAO 61 -#define CLK_TOP_MSDC30_1 62 -#define CLK_TOP_SPI 63 -#define CLK_TOP_SF 64 -#define CLK_TOP_FLASH 65 -#define CLK_TOP_TO_USB3_REF 66 -#define CLK_TOP_TO_USB3_MCU 67 -#define CLK_TOP_TO_USB3_DMA 68 -#define CLK_TOP_FROM_TOP_AHB 69 -#define CLK_TOP_FROM_TOP_AXI 70 -#define CLK_TOP_PCIE1_MAC_EN 71 -#define CLK_TOP_PCIE0_MAC_EN 72 -#define CLK_TOP_AXI_SEL 73 -#define CLK_TOP_MEM_SEL 74 -#define CLK_TOP_DDRPHYCFG_SEL 75 -#define CLK_TOP_ETH_SEL 76 -#define CLK_TOP_PWM_SEL 77 -#define CLK_TOP_F10M_REF_SEL 78 -#define CLK_TOP_NFI_INFRA_SEL 79 -#define CLK_TOP_FLASH_SEL 80 -#define CLK_TOP_UART_SEL 81 -#define CLK_TOP_SPI0_SEL 82 -#define CLK_TOP_SPI1_SEL 83 -#define CLK_TOP_MSDC50_0_SEL 84 -#define CLK_TOP_MSDC30_0_SEL 85 -#define CLK_TOP_MSDC30_1_SEL 86 -#define CLK_TOP_AP2WBMCU_SEL 87 -#define CLK_TOP_AP2WBHIF_SEL 88 -#define CLK_TOP_AUDIO_SEL 89 -#define CLK_TOP_AUD_INTBUS_SEL 90 -#define CLK_TOP_PMICSPI_SEL 91 -#define CLK_TOP_SCP_SEL 92 -#define CLK_TOP_ATB_SEL 93 -#define CLK_TOP_HIF_SEL 94 -#define CLK_TOP_SATA_SEL 95 -#define CLK_TOP_U2_SEL 96 -#define CLK_TOP_AUD1_SEL 97 -#define CLK_TOP_AUD2_SEL 98 -#define CLK_TOP_IRRX_SEL 99 -#define CLK_TOP_IRTX_SEL 100 -#define CLK_TOP_SATA_MCU_SEL 101 -#define CLK_TOP_PCIE0_MCU_SEL 102 -#define CLK_TOP_PCIE1_MCU_SEL 103 -#define CLK_TOP_SSUSB_MCU_SEL 104 -#define CLK_TOP_CRYPTO_SEL 105 -#define CLK_TOP_SGMII_REF_1_SEL 106 -#define CLK_TOP_10M_SEL 107 -#define CLK_TOP_NR_CLK 108 - -/* INFRACFG */ -#define CLK_INFRA_MUX1_SEL 0 -#define CLK_INFRA_DBGCLK_PD 1 -#define CLK_INFRA_TRNG_PD 2 -#define CLK_INFRA_DEVAPC_PD 3 -#define CLK_INFRA_APXGPT_PD 4 -#define CLK_INFRA_SEJ_PD 5 -#define CLK_INFRA_NR_CLK 6 - -/* PERICFG */ -#define CLK_PERIBUS_SEL 0 -#define CLK_PERI_PWM1_PD 1 -#define CLK_PERI_PWM2_PD 2 -#define CLK_PERI_PWM3_PD 3 -#define CLK_PERI_PWM4_PD 4 -#define CLK_PERI_PWM5_PD 5 -#define CLK_PERI_PWM6_PD 6 -#define CLK_PERI_PWM7_PD 7 -#define CLK_PERI_PWM_PD 8 -#define CLK_PERI_AP_DMA_PD 9 -#define CLK_PERI_MSDC30_1_PD 10 -#define CLK_PERI_UART0_PD 11 -#define CLK_PERI_UART1_PD 12 -#define CLK_PERI_UART2_PD 13 -#define CLK_PERI_UART3_PD 14 -#define CLK_PERI_BTIF_PD 15 -#define CLK_PERI_I2C0_PD 16 -#define CLK_PERI_SPI0_PD 17 -#define CLK_PERI_SNFI_PD 18 -#define CLK_PERI_NFI_PD 19 -#define CLK_PERI_NFIECC_PD 20 -#define CLK_PERI_FLASH_PD 21 -#define CLK_PERI_NR_CLK 22 - -/* APMIXEDSYS */ -#define CLK_APMIXED_ARMPLL 0 -#define CLK_APMIXED_MAINPLL 1 -#define CLK_APMIXED_UNIV2PLL 2 -#define CLK_APMIXED_ETH1PLL 3 -#define CLK_APMIXED_ETH2PLL 4 -#define CLK_APMIXED_SGMIPLL 5 -#define CLK_APMIXED_MAIN_CORE_EN 6 -#define CLK_APMIXED_NR_CLK 7 - -/* SSUSBSYS */ -#define CLK_SSUSB_U2_PHY_1P_EN 0 -#define CLK_SSUSB_U2_PHY_EN 1 -#define CLK_SSUSB_REF_EN 2 -#define CLK_SSUSB_SYS_EN 3 -#define CLK_SSUSB_MCU_EN 4 -#define CLK_SSUSB_DMA_EN 5 -#define CLK_SSUSB_NR_CLK 6 - -/* PCIESYS */ -#define CLK_PCIE_P1_AUX_EN 0 -#define CLK_PCIE_P1_OBFF_EN 1 -#define CLK_PCIE_P1_AHB_EN 2 -#define CLK_PCIE_P1_AXI_EN 3 -#define CLK_PCIE_P1_MAC_EN 4 -#define CLK_PCIE_P1_PIPE_EN 5 -#define CLK_PCIE_P0_AUX_EN 6 -#define CLK_PCIE_P0_OBFF_EN 7 -#define CLK_PCIE_P0_AHB_EN 8 -#define CLK_PCIE_P0_AXI_EN 9 -#define CLK_PCIE_P0_MAC_EN 10 -#define CLK_PCIE_P0_PIPE_EN 11 -#define CLK_PCIE_NR_CLK 12 - -/* ETHSYS */ -#define CLK_ETH_FE_EN 0 -#define CLK_ETH_GP2_EN 1 -#define CLK_ETH_GP1_EN 2 -#define CLK_ETH_GP0_EN 3 -#define CLK_ETH_ESW_EN 4 -#define CLK_ETH_NR_CLK 5 - -/* SGMIISYS */ -#define CLK_SGMII_TX_EN 0 -#define CLK_SGMII_RX_EN 1 -#define CLK_SGMII_CDR_REF 2 -#define CLK_SGMII_CDR_FB 3 -#define CLK_SGMII_NR_CLK 4 - -#endif /* _DT_BINDINGS_CLK_MT7629_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/mt8135-clk.h b/sys/gnu/dts/include/dt-bindings/clock/mt8135-clk.h deleted file mode 100644 index dad8365a4da..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/mt8135-clk.h +++ /dev/null @@ -1,186 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2014 MediaTek Inc. - * Author: James Liao - */ - -#ifndef _DT_BINDINGS_CLK_MT8135_H -#define _DT_BINDINGS_CLK_MT8135_H - -/* TOPCKGEN */ - -#define CLK_TOP_DSI0_LNTC_DSICLK 1 -#define CLK_TOP_HDMITX_CLKDIG_CTS 2 -#define CLK_TOP_CLKPH_MCK 3 -#define CLK_TOP_CPUM_TCK_IN 4 -#define CLK_TOP_MAINPLL_806M 5 -#define CLK_TOP_MAINPLL_537P3M 6 -#define CLK_TOP_MAINPLL_322P4M 7 -#define CLK_TOP_MAINPLL_230P3M 8 -#define CLK_TOP_UNIVPLL_624M 9 -#define CLK_TOP_UNIVPLL_416M 10 -#define CLK_TOP_UNIVPLL_249P6M 11 -#define CLK_TOP_UNIVPLL_178P3M 12 -#define CLK_TOP_UNIVPLL_48M 13 -#define CLK_TOP_MMPLL_D2 14 -#define CLK_TOP_MMPLL_D3 15 -#define CLK_TOP_MMPLL_D5 16 -#define CLK_TOP_MMPLL_D7 17 -#define CLK_TOP_MMPLL_D4 18 -#define CLK_TOP_MMPLL_D6 19 -#define CLK_TOP_SYSPLL_D2 20 -#define CLK_TOP_SYSPLL_D4 21 -#define CLK_TOP_SYSPLL_D6 22 -#define CLK_TOP_SYSPLL_D8 23 -#define CLK_TOP_SYSPLL_D10 24 -#define CLK_TOP_SYSPLL_D12 25 -#define CLK_TOP_SYSPLL_D16 26 -#define CLK_TOP_SYSPLL_D24 27 -#define CLK_TOP_SYSPLL_D3 28 -#define CLK_TOP_SYSPLL_D2P5 29 -#define CLK_TOP_SYSPLL_D5 30 -#define CLK_TOP_SYSPLL_D3P5 31 -#define CLK_TOP_UNIVPLL1_D2 32 -#define CLK_TOP_UNIVPLL1_D4 33 -#define CLK_TOP_UNIVPLL1_D6 34 -#define CLK_TOP_UNIVPLL1_D8 35 -#define CLK_TOP_UNIVPLL1_D10 36 -#define CLK_TOP_UNIVPLL2_D2 37 -#define CLK_TOP_UNIVPLL2_D4 38 -#define CLK_TOP_UNIVPLL2_D6 39 -#define CLK_TOP_UNIVPLL2_D8 40 -#define CLK_TOP_UNIVPLL_D3 41 -#define CLK_TOP_UNIVPLL_D5 42 -#define CLK_TOP_UNIVPLL_D7 43 -#define CLK_TOP_UNIVPLL_D10 44 -#define CLK_TOP_UNIVPLL_D26 45 -#define CLK_TOP_APLL 46 -#define CLK_TOP_APLL_D4 47 -#define CLK_TOP_APLL_D8 48 -#define CLK_TOP_APLL_D16 49 -#define CLK_TOP_APLL_D24 50 -#define CLK_TOP_LVDSPLL_D2 51 -#define CLK_TOP_LVDSPLL_D4 52 -#define CLK_TOP_LVDSPLL_D8 53 -#define CLK_TOP_LVDSTX_CLKDIG_CT 54 -#define CLK_TOP_VPLL_DPIX 55 -#define CLK_TOP_TVHDMI_H 56 -#define CLK_TOP_HDMITX_CLKDIG_D2 57 -#define CLK_TOP_HDMITX_CLKDIG_D3 58 -#define CLK_TOP_TVHDMI_D2 59 -#define CLK_TOP_TVHDMI_D4 60 -#define CLK_TOP_MEMPLL_MCK_D4 61 -#define CLK_TOP_AXI_SEL 62 -#define CLK_TOP_SMI_SEL 63 -#define CLK_TOP_MFG_SEL 64 -#define CLK_TOP_IRDA_SEL 65 -#define CLK_TOP_CAM_SEL 66 -#define CLK_TOP_AUD_INTBUS_SEL 67 -#define CLK_TOP_JPG_SEL 68 -#define CLK_TOP_DISP_SEL 69 -#define CLK_TOP_MSDC30_1_SEL 70 -#define CLK_TOP_MSDC30_2_SEL 71 -#define CLK_TOP_MSDC30_3_SEL 72 -#define CLK_TOP_MSDC30_4_SEL 73 -#define CLK_TOP_USB20_SEL 74 -#define CLK_TOP_VENC_SEL 75 -#define CLK_TOP_SPI_SEL 76 -#define CLK_TOP_UART_SEL 77 -#define CLK_TOP_MEM_SEL 78 -#define CLK_TOP_CAMTG_SEL 79 -#define CLK_TOP_AUDIO_SEL 80 -#define CLK_TOP_FIX_SEL 81 -#define CLK_TOP_VDEC_SEL 82 -#define CLK_TOP_DDRPHYCFG_SEL 83 -#define CLK_TOP_DPILVDS_SEL 84 -#define CLK_TOP_PMICSPI_SEL 85 -#define CLK_TOP_MSDC30_0_SEL 86 -#define CLK_TOP_SMI_MFG_AS_SEL 87 -#define CLK_TOP_GCPU_SEL 88 -#define CLK_TOP_DPI1_SEL 89 -#define CLK_TOP_CCI_SEL 90 -#define CLK_TOP_APLL_SEL 91 -#define CLK_TOP_HDMIPLL_SEL 92 -#define CLK_TOP_NR_CLK 93 - -/* APMIXED_SYS */ - -#define CLK_APMIXED_ARMPLL1 1 -#define CLK_APMIXED_ARMPLL2 2 -#define CLK_APMIXED_MAINPLL 3 -#define CLK_APMIXED_UNIVPLL 4 -#define CLK_APMIXED_MMPLL 5 -#define CLK_APMIXED_MSDCPLL 6 -#define CLK_APMIXED_TVDPLL 7 -#define CLK_APMIXED_LVDSPLL 8 -#define CLK_APMIXED_AUDPLL 9 -#define CLK_APMIXED_VDECPLL 10 -#define CLK_APMIXED_NR_CLK 11 - -/* INFRA_SYS */ - -#define CLK_INFRA_PMIC_WRAP 1 -#define CLK_INFRA_PMICSPI 2 -#define CLK_INFRA_CCIF1_AP_CTRL 3 -#define CLK_INFRA_CCIF0_AP_CTRL 4 -#define CLK_INFRA_KP 5 -#define CLK_INFRA_CPUM 6 -#define CLK_INFRA_M4U 7 -#define CLK_INFRA_MFGAXI 8 -#define CLK_INFRA_DEVAPC 9 -#define CLK_INFRA_AUDIO 10 -#define CLK_INFRA_MFG_BUS 11 -#define CLK_INFRA_SMI 12 -#define CLK_INFRA_DBGCLK 13 -#define CLK_INFRA_NR_CLK 14 - -/* PERI_SYS */ - -#define CLK_PERI_I2C5 1 -#define CLK_PERI_I2C4 2 -#define CLK_PERI_I2C3 3 -#define CLK_PERI_I2C2 4 -#define CLK_PERI_I2C1 5 -#define CLK_PERI_I2C0 6 -#define CLK_PERI_UART3 7 -#define CLK_PERI_UART2 8 -#define CLK_PERI_UART1 9 -#define CLK_PERI_UART0 10 -#define CLK_PERI_IRDA 11 -#define CLK_PERI_NLI 12 -#define CLK_PERI_MD_HIF 13 -#define CLK_PERI_AP_HIF 14 -#define CLK_PERI_MSDC30_3 15 -#define CLK_PERI_MSDC30_2 16 -#define CLK_PERI_MSDC30_1 17 -#define CLK_PERI_MSDC20_2 18 -#define CLK_PERI_MSDC20_1 19 -#define CLK_PERI_AP_DMA 20 -#define CLK_PERI_USB1 21 -#define CLK_PERI_USB0 22 -#define CLK_PERI_PWM 23 -#define CLK_PERI_PWM7 24 -#define CLK_PERI_PWM6 25 -#define CLK_PERI_PWM5 26 -#define CLK_PERI_PWM4 27 -#define CLK_PERI_PWM3 28 -#define CLK_PERI_PWM2 29 -#define CLK_PERI_PWM1 30 -#define CLK_PERI_THERM 31 -#define CLK_PERI_NFI 32 -#define CLK_PERI_USBSLV 33 -#define CLK_PERI_USB1_MCU 34 -#define CLK_PERI_USB0_MCU 35 -#define CLK_PERI_GCPU 36 -#define CLK_PERI_FHCTL 37 -#define CLK_PERI_SPI1 38 -#define CLK_PERI_AUXADC 39 -#define CLK_PERI_PERI_PWRAP 40 -#define CLK_PERI_I2C6 41 -#define CLK_PERI_UART0_SEL 42 -#define CLK_PERI_UART1_SEL 43 -#define CLK_PERI_UART2_SEL 44 -#define CLK_PERI_UART3_SEL 45 -#define CLK_PERI_NR_CLK 46 - -#endif /* _DT_BINDINGS_CLK_MT8135_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/mt8173-clk.h b/sys/gnu/dts/include/dt-bindings/clock/mt8173-clk.h deleted file mode 100644 index 3acebe937bf..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/mt8173-clk.h +++ /dev/null @@ -1,323 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2014 MediaTek Inc. - * Author: James Liao - */ - -#ifndef _DT_BINDINGS_CLK_MT8173_H -#define _DT_BINDINGS_CLK_MT8173_H - -/* TOPCKGEN */ - -#define CLK_TOP_CLKPH_MCK_O 1 -#define CLK_TOP_USB_SYSPLL_125M 3 -#define CLK_TOP_HDMITX_DIG_CTS 4 -#define CLK_TOP_ARMCA7PLL_754M 5 -#define CLK_TOP_ARMCA7PLL_502M 6 -#define CLK_TOP_MAIN_H546M 7 -#define CLK_TOP_MAIN_H364M 8 -#define CLK_TOP_MAIN_H218P4M 9 -#define CLK_TOP_MAIN_H156M 10 -#define CLK_TOP_TVDPLL_445P5M 11 -#define CLK_TOP_TVDPLL_594M 12 -#define CLK_TOP_UNIV_624M 13 -#define CLK_TOP_UNIV_416M 14 -#define CLK_TOP_UNIV_249P6M 15 -#define CLK_TOP_UNIV_178P3M 16 -#define CLK_TOP_UNIV_48M 17 -#define CLK_TOP_CLKRTC_EXT 18 -#define CLK_TOP_CLKRTC_INT 19 -#define CLK_TOP_FPC 20 -#define CLK_TOP_HDMITXPLL_D2 21 -#define CLK_TOP_HDMITXPLL_D3 22 -#define CLK_TOP_ARMCA7PLL_D2 23 -#define CLK_TOP_ARMCA7PLL_D3 24 -#define CLK_TOP_APLL1 25 -#define CLK_TOP_APLL2 26 -#define CLK_TOP_DMPLL 27 -#define CLK_TOP_DMPLL_D2 28 -#define CLK_TOP_DMPLL_D4 29 -#define CLK_TOP_DMPLL_D8 30 -#define CLK_TOP_DMPLL_D16 31 -#define CLK_TOP_LVDSPLL_D2 32 -#define CLK_TOP_LVDSPLL_D4 33 -#define CLK_TOP_LVDSPLL_D8 34 -#define CLK_TOP_MMPLL 35 -#define CLK_TOP_MMPLL_D2 36 -#define CLK_TOP_MSDCPLL 37 -#define CLK_TOP_MSDCPLL_D2 38 -#define CLK_TOP_MSDCPLL_D4 39 -#define CLK_TOP_MSDCPLL2 40 -#define CLK_TOP_MSDCPLL2_D2 41 -#define CLK_TOP_MSDCPLL2_D4 42 -#define CLK_TOP_SYSPLL_D2 43 -#define CLK_TOP_SYSPLL1_D2 44 -#define CLK_TOP_SYSPLL1_D4 45 -#define CLK_TOP_SYSPLL1_D8 46 -#define CLK_TOP_SYSPLL1_D16 47 -#define CLK_TOP_SYSPLL_D3 48 -#define CLK_TOP_SYSPLL2_D2 49 -#define CLK_TOP_SYSPLL2_D4 50 -#define CLK_TOP_SYSPLL_D5 51 -#define CLK_TOP_SYSPLL3_D2 52 -#define CLK_TOP_SYSPLL3_D4 53 -#define CLK_TOP_SYSPLL_D7 54 -#define CLK_TOP_SYSPLL4_D2 55 -#define CLK_TOP_SYSPLL4_D4 56 -#define CLK_TOP_TVDPLL 57 -#define CLK_TOP_TVDPLL_D2 58 -#define CLK_TOP_TVDPLL_D4 59 -#define CLK_TOP_TVDPLL_D8 60 -#define CLK_TOP_TVDPLL_D16 61 -#define CLK_TOP_UNIVPLL_D2 62 -#define CLK_TOP_UNIVPLL1_D2 63 -#define CLK_TOP_UNIVPLL1_D4 64 -#define CLK_TOP_UNIVPLL1_D8 65 -#define CLK_TOP_UNIVPLL_D3 66 -#define CLK_TOP_UNIVPLL2_D2 67 -#define CLK_TOP_UNIVPLL2_D4 68 -#define CLK_TOP_UNIVPLL2_D8 69 -#define CLK_TOP_UNIVPLL_D5 70 -#define CLK_TOP_UNIVPLL3_D2 71 -#define CLK_TOP_UNIVPLL3_D4 72 -#define CLK_TOP_UNIVPLL3_D8 73 -#define CLK_TOP_UNIVPLL_D7 74 -#define CLK_TOP_UNIVPLL_D26 75 -#define CLK_TOP_UNIVPLL_D52 76 -#define CLK_TOP_VCODECPLL 77 -#define CLK_TOP_VCODECPLL_370P5 78 -#define CLK_TOP_VENCPLL 79 -#define CLK_TOP_VENCPLL_D2 80 -#define CLK_TOP_VENCPLL_D4 81 -#define CLK_TOP_AXI_SEL 82 -#define CLK_TOP_MEM_SEL 83 -#define CLK_TOP_DDRPHYCFG_SEL 84 -#define CLK_TOP_MM_SEL 85 -#define CLK_TOP_PWM_SEL 86 -#define CLK_TOP_VDEC_SEL 87 -#define CLK_TOP_VENC_SEL 88 -#define CLK_TOP_MFG_SEL 89 -#define CLK_TOP_CAMTG_SEL 90 -#define CLK_TOP_UART_SEL 91 -#define CLK_TOP_SPI_SEL 92 -#define CLK_TOP_USB20_SEL 93 -#define CLK_TOP_USB30_SEL 94 -#define CLK_TOP_MSDC50_0_H_SEL 95 -#define CLK_TOP_MSDC50_0_SEL 96 -#define CLK_TOP_MSDC30_1_SEL 97 -#define CLK_TOP_MSDC30_2_SEL 98 -#define CLK_TOP_MSDC30_3_SEL 99 -#define CLK_TOP_AUDIO_SEL 100 -#define CLK_TOP_AUD_INTBUS_SEL 101 -#define CLK_TOP_PMICSPI_SEL 102 -#define CLK_TOP_SCP_SEL 103 -#define CLK_TOP_ATB_SEL 104 -#define CLK_TOP_VENC_LT_SEL 105 -#define CLK_TOP_DPI0_SEL 106 -#define CLK_TOP_IRDA_SEL 107 -#define CLK_TOP_CCI400_SEL 108 -#define CLK_TOP_AUD_1_SEL 109 -#define CLK_TOP_AUD_2_SEL 110 -#define CLK_TOP_MEM_MFG_IN_SEL 111 -#define CLK_TOP_AXI_MFG_IN_SEL 112 -#define CLK_TOP_SCAM_SEL 113 -#define CLK_TOP_SPINFI_IFR_SEL 114 -#define CLK_TOP_HDMI_SEL 115 -#define CLK_TOP_DPILVDS_SEL 116 -#define CLK_TOP_MSDC50_2_H_SEL 117 -#define CLK_TOP_HDCP_SEL 118 -#define CLK_TOP_HDCP_24M_SEL 119 -#define CLK_TOP_RTC_SEL 120 -#define CLK_TOP_APLL1_DIV0 121 -#define CLK_TOP_APLL1_DIV1 122 -#define CLK_TOP_APLL1_DIV2 123 -#define CLK_TOP_APLL1_DIV3 124 -#define CLK_TOP_APLL1_DIV4 125 -#define CLK_TOP_APLL1_DIV5 126 -#define CLK_TOP_APLL2_DIV0 127 -#define CLK_TOP_APLL2_DIV1 128 -#define CLK_TOP_APLL2_DIV2 129 -#define CLK_TOP_APLL2_DIV3 130 -#define CLK_TOP_APLL2_DIV4 131 -#define CLK_TOP_APLL2_DIV5 132 -#define CLK_TOP_I2S0_M_SEL 133 -#define CLK_TOP_I2S1_M_SEL 134 -#define CLK_TOP_I2S2_M_SEL 135 -#define CLK_TOP_I2S3_M_SEL 136 -#define CLK_TOP_I2S3_B_SEL 137 -#define CLK_TOP_DSI0_DIG 138 -#define CLK_TOP_DSI1_DIG 139 -#define CLK_TOP_LVDS_PXL 140 -#define CLK_TOP_LVDS_CTS 141 -#define CLK_TOP_NR_CLK 142 - -/* APMIXED_SYS */ - -#define CLK_APMIXED_ARMCA15PLL 1 -#define CLK_APMIXED_ARMCA7PLL 2 -#define CLK_APMIXED_MAINPLL 3 -#define CLK_APMIXED_UNIVPLL 4 -#define CLK_APMIXED_MMPLL 5 -#define CLK_APMIXED_MSDCPLL 6 -#define CLK_APMIXED_VENCPLL 7 -#define CLK_APMIXED_TVDPLL 8 -#define CLK_APMIXED_MPLL 9 -#define CLK_APMIXED_VCODECPLL 10 -#define CLK_APMIXED_APLL1 11 -#define CLK_APMIXED_APLL2 12 -#define CLK_APMIXED_LVDSPLL 13 -#define CLK_APMIXED_MSDCPLL2 14 -#define CLK_APMIXED_REF2USB_TX 15 -#define CLK_APMIXED_HDMI_REF 16 -#define CLK_APMIXED_NR_CLK 17 - -/* INFRA_SYS */ - -#define CLK_INFRA_DBGCLK 1 -#define CLK_INFRA_SMI 2 -#define CLK_INFRA_AUDIO 3 -#define CLK_INFRA_GCE 4 -#define CLK_INFRA_L2C_SRAM 5 -#define CLK_INFRA_M4U 6 -#define CLK_INFRA_CPUM 7 -#define CLK_INFRA_KP 8 -#define CLK_INFRA_CEC 9 -#define CLK_INFRA_PMICSPI 10 -#define CLK_INFRA_PMICWRAP 11 -#define CLK_INFRA_CLK_13M 12 -#define CLK_INFRA_CA53SEL 13 -#define CLK_INFRA_CA57SEL 14 /* Deprecated. Don't use it. */ -#define CLK_INFRA_CA72SEL 14 -#define CLK_INFRA_NR_CLK 15 - -/* PERI_SYS */ - -#define CLK_PERI_NFI 1 -#define CLK_PERI_THERM 2 -#define CLK_PERI_PWM1 3 -#define CLK_PERI_PWM2 4 -#define CLK_PERI_PWM3 5 -#define CLK_PERI_PWM4 6 -#define CLK_PERI_PWM5 7 -#define CLK_PERI_PWM6 8 -#define CLK_PERI_PWM7 9 -#define CLK_PERI_PWM 10 -#define CLK_PERI_USB0 11 -#define CLK_PERI_USB1 12 -#define CLK_PERI_AP_DMA 13 -#define CLK_PERI_MSDC30_0 14 -#define CLK_PERI_MSDC30_1 15 -#define CLK_PERI_MSDC30_2 16 -#define CLK_PERI_MSDC30_3 17 -#define CLK_PERI_NLI_ARB 18 -#define CLK_PERI_IRDA 19 -#define CLK_PERI_UART0 20 -#define CLK_PERI_UART1 21 -#define CLK_PERI_UART2 22 -#define CLK_PERI_UART3 23 -#define CLK_PERI_I2C0 24 -#define CLK_PERI_I2C1 25 -#define CLK_PERI_I2C2 26 -#define CLK_PERI_I2C3 27 -#define CLK_PERI_I2C4 28 -#define CLK_PERI_AUXADC 29 -#define CLK_PERI_SPI0 30 -#define CLK_PERI_I2C5 31 -#define CLK_PERI_NFIECC 32 -#define CLK_PERI_SPI 33 -#define CLK_PERI_IRRX 34 -#define CLK_PERI_I2C6 35 -#define CLK_PERI_UART0_SEL 36 -#define CLK_PERI_UART1_SEL 37 -#define CLK_PERI_UART2_SEL 38 -#define CLK_PERI_UART3_SEL 39 -#define CLK_PERI_NR_CLK 40 - -/* IMG_SYS */ - -#define CLK_IMG_LARB2_SMI 1 -#define CLK_IMG_CAM_SMI 2 -#define CLK_IMG_CAM_CAM 3 -#define CLK_IMG_SEN_TG 4 -#define CLK_IMG_SEN_CAM 5 -#define CLK_IMG_CAM_SV 6 -#define CLK_IMG_FD 7 -#define CLK_IMG_NR_CLK 8 - -/* MM_SYS */ - -#define CLK_MM_SMI_COMMON 1 -#define CLK_MM_SMI_LARB0 2 -#define CLK_MM_CAM_MDP 3 -#define CLK_MM_MDP_RDMA0 4 -#define CLK_MM_MDP_RDMA1 5 -#define CLK_MM_MDP_RSZ0 6 -#define CLK_MM_MDP_RSZ1 7 -#define CLK_MM_MDP_RSZ2 8 -#define CLK_MM_MDP_TDSHP0 9 -#define CLK_MM_MDP_TDSHP1 10 -#define CLK_MM_MDP_WDMA 11 -#define CLK_MM_MDP_WROT0 12 -#define CLK_MM_MDP_WROT1 13 -#define CLK_MM_FAKE_ENG 14 -#define CLK_MM_MUTEX_32K 15 -#define CLK_MM_DISP_OVL0 16 -#define CLK_MM_DISP_OVL1 17 -#define CLK_MM_DISP_RDMA0 18 -#define CLK_MM_DISP_RDMA1 19 -#define CLK_MM_DISP_RDMA2 20 -#define CLK_MM_DISP_WDMA0 21 -#define CLK_MM_DISP_WDMA1 22 -#define CLK_MM_DISP_COLOR0 23 -#define CLK_MM_DISP_COLOR1 24 -#define CLK_MM_DISP_AAL 25 -#define CLK_MM_DISP_GAMMA 26 -#define CLK_MM_DISP_UFOE 27 -#define CLK_MM_DISP_SPLIT0 28 -#define CLK_MM_DISP_SPLIT1 29 -#define CLK_MM_DISP_MERGE 30 -#define CLK_MM_DISP_OD 31 -#define CLK_MM_DISP_PWM0MM 32 -#define CLK_MM_DISP_PWM026M 33 -#define CLK_MM_DISP_PWM1MM 34 -#define CLK_MM_DISP_PWM126M 35 -#define CLK_MM_DSI0_ENGINE 36 -#define CLK_MM_DSI0_DIGITAL 37 -#define CLK_MM_DSI1_ENGINE 38 -#define CLK_MM_DSI1_DIGITAL 39 -#define CLK_MM_DPI_PIXEL 40 -#define CLK_MM_DPI_ENGINE 41 -#define CLK_MM_DPI1_PIXEL 42 -#define CLK_MM_DPI1_ENGINE 43 -#define CLK_MM_HDMI_PIXEL 44 -#define CLK_MM_HDMI_PLLCK 45 -#define CLK_MM_HDMI_AUDIO 46 -#define CLK_MM_HDMI_SPDIF 47 -#define CLK_MM_LVDS_PIXEL 48 -#define CLK_MM_LVDS_CTS 49 -#define CLK_MM_SMI_LARB4 50 -#define CLK_MM_HDMI_HDCP 51 -#define CLK_MM_HDMI_HDCP24M 52 -#define CLK_MM_NR_CLK 53 - -/* VDEC_SYS */ - -#define CLK_VDEC_CKEN 1 -#define CLK_VDEC_LARB_CKEN 2 -#define CLK_VDEC_NR_CLK 3 - -/* VENC_SYS */ - -#define CLK_VENC_CKE0 1 -#define CLK_VENC_CKE1 2 -#define CLK_VENC_CKE2 3 -#define CLK_VENC_CKE3 4 -#define CLK_VENC_NR_CLK 5 - -/* VENCLT_SYS */ - -#define CLK_VENCLT_CKE0 1 -#define CLK_VENCLT_CKE1 2 -#define CLK_VENCLT_NR_CLK 3 - -#endif /* _DT_BINDINGS_CLK_MT8173_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/mt8183-clk.h b/sys/gnu/dts/include/dt-bindings/clock/mt8183-clk.h deleted file mode 100644 index a7b470b0ec8..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/mt8183-clk.h +++ /dev/null @@ -1,426 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2018 MediaTek Inc. - * Author: Weiyi Lu - */ - -#ifndef _DT_BINDINGS_CLK_MT8183_H -#define _DT_BINDINGS_CLK_MT8183_H - -/* APMIXED */ -#define CLK_APMIXED_ARMPLL_LL 0 -#define CLK_APMIXED_ARMPLL_L 1 -#define CLK_APMIXED_CCIPLL 2 -#define CLK_APMIXED_MAINPLL 3 -#define CLK_APMIXED_UNIV2PLL 4 -#define CLK_APMIXED_MSDCPLL 5 -#define CLK_APMIXED_MMPLL 6 -#define CLK_APMIXED_MFGPLL 7 -#define CLK_APMIXED_TVDPLL 8 -#define CLK_APMIXED_APLL1 9 -#define CLK_APMIXED_APLL2 10 -#define CLK_APMIXED_SSUSB_26M 11 -#define CLK_APMIXED_APPLL_26M 12 -#define CLK_APMIXED_MIPIC0_26M 13 -#define CLK_APMIXED_MDPLLGP_26M 14 -#define CLK_APMIXED_MMSYS_26M 15 -#define CLK_APMIXED_UFS_26M 16 -#define CLK_APMIXED_MIPIC1_26M 17 -#define CLK_APMIXED_MEMPLL_26M 18 -#define CLK_APMIXED_CLKSQ_LVPLL_26M 19 -#define CLK_APMIXED_MIPID0_26M 20 -#define CLK_APMIXED_MIPID1_26M 21 -#define CLK_APMIXED_NR_CLK 22 - -/* TOPCKGEN */ -#define CLK_TOP_MUX_AXI 0 -#define CLK_TOP_MUX_MM 1 -#define CLK_TOP_MUX_CAM 2 -#define CLK_TOP_MUX_MFG 3 -#define CLK_TOP_MUX_CAMTG 4 -#define CLK_TOP_MUX_UART 5 -#define CLK_TOP_MUX_SPI 6 -#define CLK_TOP_MUX_MSDC50_0_HCLK 7 -#define CLK_TOP_MUX_MSDC50_0 8 -#define CLK_TOP_MUX_MSDC30_1 9 -#define CLK_TOP_MUX_MSDC30_2 10 -#define CLK_TOP_MUX_AUDIO 11 -#define CLK_TOP_MUX_AUD_INTBUS 12 -#define CLK_TOP_MUX_FPWRAP_ULPOSC 13 -#define CLK_TOP_MUX_SCP 14 -#define CLK_TOP_MUX_ATB 15 -#define CLK_TOP_MUX_SSPM 16 -#define CLK_TOP_MUX_DPI0 17 -#define CLK_TOP_MUX_SCAM 18 -#define CLK_TOP_MUX_AUD_1 19 -#define CLK_TOP_MUX_AUD_2 20 -#define CLK_TOP_MUX_DISP_PWM 21 -#define CLK_TOP_MUX_SSUSB_TOP_XHCI 22 -#define CLK_TOP_MUX_USB_TOP 23 -#define CLK_TOP_MUX_SPM 24 -#define CLK_TOP_MUX_I2C 25 -#define CLK_TOP_MUX_F52M_MFG 26 -#define CLK_TOP_MUX_SENINF 27 -#define CLK_TOP_MUX_DXCC 28 -#define CLK_TOP_MUX_CAMTG2 29 -#define CLK_TOP_MUX_AUD_ENG1 30 -#define CLK_TOP_MUX_AUD_ENG2 31 -#define CLK_TOP_MUX_FAES_UFSFDE 32 -#define CLK_TOP_MUX_FUFS 33 -#define CLK_TOP_MUX_IMG 34 -#define CLK_TOP_MUX_DSP 35 -#define CLK_TOP_MUX_DSP1 36 -#define CLK_TOP_MUX_DSP2 37 -#define CLK_TOP_MUX_IPU_IF 38 -#define CLK_TOP_MUX_CAMTG3 39 -#define CLK_TOP_MUX_CAMTG4 40 -#define CLK_TOP_MUX_PMICSPI 41 -#define CLK_TOP_SYSPLL_CK 42 -#define CLK_TOP_SYSPLL_D2 43 -#define CLK_TOP_SYSPLL_D3 44 -#define CLK_TOP_SYSPLL_D5 45 -#define CLK_TOP_SYSPLL_D7 46 -#define CLK_TOP_SYSPLL_D2_D2 47 -#define CLK_TOP_SYSPLL_D2_D4 48 -#define CLK_TOP_SYSPLL_D2_D8 49 -#define CLK_TOP_SYSPLL_D2_D16 50 -#define CLK_TOP_SYSPLL_D3_D2 51 -#define CLK_TOP_SYSPLL_D3_D4 52 -#define CLK_TOP_SYSPLL_D3_D8 53 -#define CLK_TOP_SYSPLL_D5_D2 54 -#define CLK_TOP_SYSPLL_D5_D4 55 -#define CLK_TOP_SYSPLL_D7_D2 56 -#define CLK_TOP_SYSPLL_D7_D4 57 -#define CLK_TOP_UNIVPLL_CK 58 -#define CLK_TOP_UNIVPLL_D2 59 -#define CLK_TOP_UNIVPLL_D3 60 -#define CLK_TOP_UNIVPLL_D5 61 -#define CLK_TOP_UNIVPLL_D7 62 -#define CLK_TOP_UNIVPLL_D2_D2 63 -#define CLK_TOP_UNIVPLL_D2_D4 64 -#define CLK_TOP_UNIVPLL_D2_D8 65 -#define CLK_TOP_UNIVPLL_D3_D2 66 -#define CLK_TOP_UNIVPLL_D3_D4 67 -#define CLK_TOP_UNIVPLL_D3_D8 68 -#define CLK_TOP_UNIVPLL_D5_D2 69 -#define CLK_TOP_UNIVPLL_D5_D4 70 -#define CLK_TOP_UNIVPLL_D5_D8 71 -#define CLK_TOP_APLL1_CK 72 -#define CLK_TOP_APLL1_D2 73 -#define CLK_TOP_APLL1_D4 74 -#define CLK_TOP_APLL1_D8 75 -#define CLK_TOP_APLL2_CK 76 -#define CLK_TOP_APLL2_D2 77 -#define CLK_TOP_APLL2_D4 78 -#define CLK_TOP_APLL2_D8 79 -#define CLK_TOP_TVDPLL_CK 80 -#define CLK_TOP_TVDPLL_D2 81 -#define CLK_TOP_TVDPLL_D4 82 -#define CLK_TOP_TVDPLL_D8 83 -#define CLK_TOP_TVDPLL_D16 84 -#define CLK_TOP_MSDCPLL_CK 85 -#define CLK_TOP_MSDCPLL_D2 86 -#define CLK_TOP_MSDCPLL_D4 87 -#define CLK_TOP_MSDCPLL_D8 88 -#define CLK_TOP_MSDCPLL_D16 89 -#define CLK_TOP_AD_OSC_CK 90 -#define CLK_TOP_OSC_D2 91 -#define CLK_TOP_OSC_D4 92 -#define CLK_TOP_OSC_D8 93 -#define CLK_TOP_OSC_D16 94 -#define CLK_TOP_F26M_CK_D2 95 -#define CLK_TOP_MFGPLL_CK 96 -#define CLK_TOP_UNIVP_192M_CK 97 -#define CLK_TOP_UNIVP_192M_D2 98 -#define CLK_TOP_UNIVP_192M_D4 99 -#define CLK_TOP_UNIVP_192M_D8 100 -#define CLK_TOP_UNIVP_192M_D16 101 -#define CLK_TOP_UNIVP_192M_D32 102 -#define CLK_TOP_MMPLL_CK 103 -#define CLK_TOP_MMPLL_D4 104 -#define CLK_TOP_MMPLL_D4_D2 105 -#define CLK_TOP_MMPLL_D4_D4 106 -#define CLK_TOP_MMPLL_D5 107 -#define CLK_TOP_MMPLL_D5_D2 108 -#define CLK_TOP_MMPLL_D5_D4 109 -#define CLK_TOP_MMPLL_D6 110 -#define CLK_TOP_MMPLL_D7 111 -#define CLK_TOP_CLK26M 112 -#define CLK_TOP_CLK13M 113 -#define CLK_TOP_ULPOSC 114 -#define CLK_TOP_UNIVP_192M 115 -#define CLK_TOP_MUX_APLL_I2S0 116 -#define CLK_TOP_MUX_APLL_I2S1 117 -#define CLK_TOP_MUX_APLL_I2S2 118 -#define CLK_TOP_MUX_APLL_I2S3 119 -#define CLK_TOP_MUX_APLL_I2S4 120 -#define CLK_TOP_MUX_APLL_I2S5 121 -#define CLK_TOP_APLL12_DIV0 122 -#define CLK_TOP_APLL12_DIV1 123 -#define CLK_TOP_APLL12_DIV2 124 -#define CLK_TOP_APLL12_DIV3 125 -#define CLK_TOP_APLL12_DIV4 126 -#define CLK_TOP_APLL12_DIVB 127 -#define CLK_TOP_UNIVPLL 128 -#define CLK_TOP_ARMPLL_DIV_PLL1 129 -#define CLK_TOP_ARMPLL_DIV_PLL2 130 -#define CLK_TOP_UNIVPLL_D3_D16 131 -#define CLK_TOP_NR_CLK 132 - -/* CAMSYS */ -#define CLK_CAM_LARB6 0 -#define CLK_CAM_DFP_VAD 1 -#define CLK_CAM_CAM 2 -#define CLK_CAM_CAMTG 3 -#define CLK_CAM_SENINF 4 -#define CLK_CAM_CAMSV0 5 -#define CLK_CAM_CAMSV1 6 -#define CLK_CAM_CAMSV2 7 -#define CLK_CAM_CCU 8 -#define CLK_CAM_LARB3 9 -#define CLK_CAM_NR_CLK 10 - -/* INFRACFG_AO */ -#define CLK_INFRA_PMIC_TMR 0 -#define CLK_INFRA_PMIC_AP 1 -#define CLK_INFRA_PMIC_MD 2 -#define CLK_INFRA_PMIC_CONN 3 -#define CLK_INFRA_SCPSYS 4 -#define CLK_INFRA_SEJ 5 -#define CLK_INFRA_APXGPT 6 -#define CLK_INFRA_ICUSB 7 -#define CLK_INFRA_GCE 8 -#define CLK_INFRA_THERM 9 -#define CLK_INFRA_I2C0 10 -#define CLK_INFRA_I2C1 11 -#define CLK_INFRA_I2C2 12 -#define CLK_INFRA_I2C3 13 -#define CLK_INFRA_PWM_HCLK 14 -#define CLK_INFRA_PWM1 15 -#define CLK_INFRA_PWM2 16 -#define CLK_INFRA_PWM3 17 -#define CLK_INFRA_PWM4 18 -#define CLK_INFRA_PWM 19 -#define CLK_INFRA_UART0 20 -#define CLK_INFRA_UART1 21 -#define CLK_INFRA_UART2 22 -#define CLK_INFRA_UART3 23 -#define CLK_INFRA_GCE_26M 24 -#define CLK_INFRA_CQ_DMA_FPC 25 -#define CLK_INFRA_BTIF 26 -#define CLK_INFRA_SPI0 27 -#define CLK_INFRA_MSDC0 28 -#define CLK_INFRA_MSDC1 29 -#define CLK_INFRA_MSDC2 30 -#define CLK_INFRA_MSDC0_SCK 31 -#define CLK_INFRA_DVFSRC 32 -#define CLK_INFRA_GCPU 33 -#define CLK_INFRA_TRNG 34 -#define CLK_INFRA_AUXADC 35 -#define CLK_INFRA_CPUM 36 -#define CLK_INFRA_CCIF1_AP 37 -#define CLK_INFRA_CCIF1_MD 38 -#define CLK_INFRA_AUXADC_MD 39 -#define CLK_INFRA_MSDC1_SCK 40 -#define CLK_INFRA_MSDC2_SCK 41 -#define CLK_INFRA_AP_DMA 42 -#define CLK_INFRA_XIU 43 -#define CLK_INFRA_DEVICE_APC 44 -#define CLK_INFRA_CCIF_AP 45 -#define CLK_INFRA_DEBUGSYS 46 -#define CLK_INFRA_AUDIO 47 -#define CLK_INFRA_CCIF_MD 48 -#define CLK_INFRA_DXCC_SEC_CORE 49 -#define CLK_INFRA_DXCC_AO 50 -#define CLK_INFRA_DRAMC_F26M 51 -#define CLK_INFRA_IRTX 52 -#define CLK_INFRA_DISP_PWM 53 -#define CLK_INFRA_CLDMA_BCLK 54 -#define CLK_INFRA_AUDIO_26M_BCLK 55 -#define CLK_INFRA_SPI1 56 -#define CLK_INFRA_I2C4 57 -#define CLK_INFRA_MODEM_TEMP_SHARE 58 -#define CLK_INFRA_SPI2 59 -#define CLK_INFRA_SPI3 60 -#define CLK_INFRA_UNIPRO_SCK 61 -#define CLK_INFRA_UNIPRO_TICK 62 -#define CLK_INFRA_UFS_MP_SAP_BCLK 63 -#define CLK_INFRA_MD32_BCLK 64 -#define CLK_INFRA_SSPM 65 -#define CLK_INFRA_UNIPRO_MBIST 66 -#define CLK_INFRA_SSPM_BUS_HCLK 67 -#define CLK_INFRA_I2C5 68 -#define CLK_INFRA_I2C5_ARBITER 69 -#define CLK_INFRA_I2C5_IMM 70 -#define CLK_INFRA_I2C1_ARBITER 71 -#define CLK_INFRA_I2C1_IMM 72 -#define CLK_INFRA_I2C2_ARBITER 73 -#define CLK_INFRA_I2C2_IMM 74 -#define CLK_INFRA_SPI4 75 -#define CLK_INFRA_SPI5 76 -#define CLK_INFRA_CQ_DMA 77 -#define CLK_INFRA_UFS 78 -#define CLK_INFRA_AES_UFSFDE 79 -#define CLK_INFRA_UFS_TICK 80 -#define CLK_INFRA_MSDC0_SELF 81 -#define CLK_INFRA_MSDC1_SELF 82 -#define CLK_INFRA_MSDC2_SELF 83 -#define CLK_INFRA_SSPM_26M_SELF 84 -#define CLK_INFRA_SSPM_32K_SELF 85 -#define CLK_INFRA_UFS_AXI 86 -#define CLK_INFRA_I2C6 87 -#define CLK_INFRA_AP_MSDC0 88 -#define CLK_INFRA_MD_MSDC0 89 -#define CLK_INFRA_USB 90 -#define CLK_INFRA_DEVMPU_BCLK 91 -#define CLK_INFRA_CCIF2_AP 92 -#define CLK_INFRA_CCIF2_MD 93 -#define CLK_INFRA_CCIF3_AP 94 -#define CLK_INFRA_CCIF3_MD 95 -#define CLK_INFRA_SEJ_F13M 96 -#define CLK_INFRA_AES_BCLK 97 -#define CLK_INFRA_I2C7 98 -#define CLK_INFRA_I2C8 99 -#define CLK_INFRA_FBIST2FPC 100 -#define CLK_INFRA_NR_CLK 101 - -/* PERICFG */ -#define CLK_PERI_AXI 0 -#define CLK_PERI_NR_CLK 1 - -/* MFGCFG */ -#define CLK_MFG_BG3D 0 -#define CLK_MFG_NR_CLK 1 - -/* IMG */ -#define CLK_IMG_OWE 0 -#define CLK_IMG_WPE_B 1 -#define CLK_IMG_WPE_A 2 -#define CLK_IMG_MFB 3 -#define CLK_IMG_RSC 4 -#define CLK_IMG_DPE 5 -#define CLK_IMG_FDVT 6 -#define CLK_IMG_DIP 7 -#define CLK_IMG_LARB2 8 -#define CLK_IMG_LARB5 9 -#define CLK_IMG_NR_CLK 10 - -/* MMSYS_CONFIG */ -#define CLK_MM_SMI_COMMON 0 -#define CLK_MM_SMI_LARB0 1 -#define CLK_MM_SMI_LARB1 2 -#define CLK_MM_GALS_COMM0 3 -#define CLK_MM_GALS_COMM1 4 -#define CLK_MM_GALS_CCU2MM 5 -#define CLK_MM_GALS_IPU12MM 6 -#define CLK_MM_GALS_IMG2MM 7 -#define CLK_MM_GALS_CAM2MM 8 -#define CLK_MM_GALS_IPU2MM 9 -#define CLK_MM_MDP_DL_TXCK 10 -#define CLK_MM_IPU_DL_TXCK 11 -#define CLK_MM_MDP_RDMA0 12 -#define CLK_MM_MDP_RDMA1 13 -#define CLK_MM_MDP_RSZ0 14 -#define CLK_MM_MDP_RSZ1 15 -#define CLK_MM_MDP_TDSHP 16 -#define CLK_MM_MDP_WROT0 17 -#define CLK_MM_FAKE_ENG 18 -#define CLK_MM_DISP_OVL0 19 -#define CLK_MM_DISP_OVL0_2L 20 -#define CLK_MM_DISP_OVL1_2L 21 -#define CLK_MM_DISP_RDMA0 22 -#define CLK_MM_DISP_RDMA1 23 -#define CLK_MM_DISP_WDMA0 24 -#define CLK_MM_DISP_COLOR0 25 -#define CLK_MM_DISP_CCORR0 26 -#define CLK_MM_DISP_AAL0 27 -#define CLK_MM_DISP_GAMMA0 28 -#define CLK_MM_DISP_DITHER0 29 -#define CLK_MM_DISP_SPLIT 30 -#define CLK_MM_DSI0_MM 31 -#define CLK_MM_DSI0_IF 32 -#define CLK_MM_DPI_MM 33 -#define CLK_MM_DPI_IF 34 -#define CLK_MM_FAKE_ENG2 35 -#define CLK_MM_MDP_DL_RX 36 -#define CLK_MM_IPU_DL_RX 37 -#define CLK_MM_26M 38 -#define CLK_MM_MMSYS_R2Y 39 -#define CLK_MM_DISP_RSZ 40 -#define CLK_MM_MDP_WDMA0 41 -#define CLK_MM_MDP_AAL 42 -#define CLK_MM_MDP_CCORR 43 -#define CLK_MM_DBI_MM 44 -#define CLK_MM_DBI_IF 45 -#define CLK_MM_NR_CLK 46 - -/* VDEC_GCON */ -#define CLK_VDEC_VDEC 0 -#define CLK_VDEC_LARB1 1 -#define CLK_VDEC_NR_CLK 2 - -/* VENC_GCON */ -#define CLK_VENC_LARB 0 -#define CLK_VENC_VENC 1 -#define CLK_VENC_JPGENC 2 -#define CLK_VENC_NR_CLK 3 - -/* AUDIO */ -#define CLK_AUDIO_TML 0 -#define CLK_AUDIO_DAC_PREDIS 1 -#define CLK_AUDIO_DAC 2 -#define CLK_AUDIO_ADC 3 -#define CLK_AUDIO_APLL_TUNER 4 -#define CLK_AUDIO_APLL2_TUNER 5 -#define CLK_AUDIO_24M 6 -#define CLK_AUDIO_22M 7 -#define CLK_AUDIO_AFE 8 -#define CLK_AUDIO_I2S4 9 -#define CLK_AUDIO_I2S3 10 -#define CLK_AUDIO_I2S2 11 -#define CLK_AUDIO_I2S1 12 -#define CLK_AUDIO_PDN_ADDA6_ADC 13 -#define CLK_AUDIO_TDM 14 -#define CLK_AUDIO_NR_CLK 15 - -/* IPU_CONN */ -#define CLK_IPU_CONN_IPU 0 -#define CLK_IPU_CONN_AHB 1 -#define CLK_IPU_CONN_AXI 2 -#define CLK_IPU_CONN_ISP 3 -#define CLK_IPU_CONN_CAM_ADL 4 -#define CLK_IPU_CONN_IMG_ADL 5 -#define CLK_IPU_CONN_DAP_RX 6 -#define CLK_IPU_CONN_APB2AXI 7 -#define CLK_IPU_CONN_APB2AHB 8 -#define CLK_IPU_CONN_IPU_CAB1TO2 9 -#define CLK_IPU_CONN_IPU1_CAB1TO2 10 -#define CLK_IPU_CONN_IPU2_CAB1TO2 11 -#define CLK_IPU_CONN_CAB3TO3 12 -#define CLK_IPU_CONN_CAB2TO1 13 -#define CLK_IPU_CONN_CAB3TO1_SLICE 14 -#define CLK_IPU_CONN_NR_CLK 15 - -/* IPU_ADL */ -#define CLK_IPU_ADL_CABGEN 0 -#define CLK_IPU_ADL_NR_CLK 1 - -/* IPU_CORE0 */ -#define CLK_IPU_CORE0_JTAG 0 -#define CLK_IPU_CORE0_AXI 1 -#define CLK_IPU_CORE0_IPU 2 -#define CLK_IPU_CORE0_NR_CLK 3 - -/* IPU_CORE1 */ -#define CLK_IPU_CORE1_JTAG 0 -#define CLK_IPU_CORE1_AXI 1 -#define CLK_IPU_CORE1_IPU 2 -#define CLK_IPU_CORE1_NR_CLK 3 - -/* MCUCFG */ -#define CLK_MCU_MP0_SEL 0 -#define CLK_MCU_MP2_SEL 1 -#define CLK_MCU_BUS_SEL 2 -#define CLK_MCU_NR_CLK 3 - -#endif /* _DT_BINDINGS_CLK_MT8183_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/mt8516-clk.h b/sys/gnu/dts/include/dt-bindings/clock/mt8516-clk.h deleted file mode 100644 index 816447b98ed..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/mt8516-clk.h +++ /dev/null @@ -1,228 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2019 MediaTek Inc. - * Copyright (c) 2019 BayLibre, SAS. - * Author: James Liao - */ - -#ifndef _DT_BINDINGS_CLK_MT8516_H -#define _DT_BINDINGS_CLK_MT8516_H - -/* APMIXEDSYS */ - -#define CLK_APMIXED_ARMPLL 0 -#define CLK_APMIXED_MAINPLL 1 -#define CLK_APMIXED_UNIVPLL 2 -#define CLK_APMIXED_MMPLL 3 -#define CLK_APMIXED_APLL1 4 -#define CLK_APMIXED_APLL2 5 -#define CLK_APMIXED_NR_CLK 6 - -/* INFRACFG */ - -#define CLK_IFR_MUX1_SEL 0 -#define CLK_IFR_ETH_25M_SEL 1 -#define CLK_IFR_I2C0_SEL 2 -#define CLK_IFR_I2C1_SEL 3 -#define CLK_IFR_I2C2_SEL 4 -#define CLK_IFR_NR_CLK 5 - -/* TOPCKGEN */ - -#define CLK_TOP_CLK_NULL 0 -#define CLK_TOP_I2S_INFRA_BCK 1 -#define CLK_TOP_MEMPLL 2 -#define CLK_TOP_DMPLL 3 -#define CLK_TOP_MAINPLL_D2 4 -#define CLK_TOP_MAINPLL_D4 5 -#define CLK_TOP_MAINPLL_D8 6 -#define CLK_TOP_MAINPLL_D16 7 -#define CLK_TOP_MAINPLL_D11 8 -#define CLK_TOP_MAINPLL_D22 9 -#define CLK_TOP_MAINPLL_D3 10 -#define CLK_TOP_MAINPLL_D6 11 -#define CLK_TOP_MAINPLL_D12 12 -#define CLK_TOP_MAINPLL_D5 13 -#define CLK_TOP_MAINPLL_D10 14 -#define CLK_TOP_MAINPLL_D20 15 -#define CLK_TOP_MAINPLL_D40 16 -#define CLK_TOP_MAINPLL_D7 17 -#define CLK_TOP_MAINPLL_D14 18 -#define CLK_TOP_UNIVPLL_D2 19 -#define CLK_TOP_UNIVPLL_D4 20 -#define CLK_TOP_UNIVPLL_D8 21 -#define CLK_TOP_UNIVPLL_D16 22 -#define CLK_TOP_UNIVPLL_D3 23 -#define CLK_TOP_UNIVPLL_D6 24 -#define CLK_TOP_UNIVPLL_D12 25 -#define CLK_TOP_UNIVPLL_D24 26 -#define CLK_TOP_UNIVPLL_D5 27 -#define CLK_TOP_UNIVPLL_D20 28 -#define CLK_TOP_MMPLL380M 29 -#define CLK_TOP_MMPLL_D2 30 -#define CLK_TOP_MMPLL_200M 31 -#define CLK_TOP_USB_PHY48M 32 -#define CLK_TOP_APLL1 33 -#define CLK_TOP_APLL1_D2 34 -#define CLK_TOP_APLL1_D4 35 -#define CLK_TOP_APLL1_D8 36 -#define CLK_TOP_APLL2 37 -#define CLK_TOP_APLL2_D2 38 -#define CLK_TOP_APLL2_D4 39 -#define CLK_TOP_APLL2_D8 40 -#define CLK_TOP_CLK26M 41 -#define CLK_TOP_CLK26M_D2 42 -#define CLK_TOP_AHB_INFRA_D2 43 -#define CLK_TOP_NFI1X 44 -#define CLK_TOP_ETH_D2 45 -#define CLK_TOP_THEM 46 -#define CLK_TOP_APDMA 47 -#define CLK_TOP_I2C0 48 -#define CLK_TOP_I2C1 49 -#define CLK_TOP_AUXADC1 50 -#define CLK_TOP_NFI 51 -#define CLK_TOP_NFIECC 52 -#define CLK_TOP_DEBUGSYS 53 -#define CLK_TOP_PWM 54 -#define CLK_TOP_UART0 55 -#define CLK_TOP_UART1 56 -#define CLK_TOP_BTIF 57 -#define CLK_TOP_USB 58 -#define CLK_TOP_FLASHIF_26M 59 -#define CLK_TOP_AUXADC2 60 -#define CLK_TOP_I2C2 61 -#define CLK_TOP_MSDC0 62 -#define CLK_TOP_MSDC1 63 -#define CLK_TOP_NFI2X 64 -#define CLK_TOP_PMICWRAP_AP 65 -#define CLK_TOP_SEJ 66 -#define CLK_TOP_MEMSLP_DLYER 67 -#define CLK_TOP_SPI 68 -#define CLK_TOP_APXGPT 69 -#define CLK_TOP_AUDIO 70 -#define CLK_TOP_PMICWRAP_MD 71 -#define CLK_TOP_PMICWRAP_CONN 72 -#define CLK_TOP_PMICWRAP_26M 73 -#define CLK_TOP_AUX_ADC 74 -#define CLK_TOP_AUX_TP 75 -#define CLK_TOP_MSDC2 76 -#define CLK_TOP_RBIST 77 -#define CLK_TOP_NFI_BUS 78 -#define CLK_TOP_GCE 79 -#define CLK_TOP_TRNG 80 -#define CLK_TOP_SEJ_13M 81 -#define CLK_TOP_AES 82 -#define CLK_TOP_PWM_B 83 -#define CLK_TOP_PWM1_FB 84 -#define CLK_TOP_PWM2_FB 85 -#define CLK_TOP_PWM3_FB 86 -#define CLK_TOP_PWM4_FB 87 -#define CLK_TOP_PWM5_FB 88 -#define CLK_TOP_USB_1P 89 -#define CLK_TOP_FLASHIF_FREERUN 90 -#define CLK_TOP_66M_ETH 91 -#define CLK_TOP_133M_ETH 92 -#define CLK_TOP_FETH_25M 93 -#define CLK_TOP_FETH_50M 94 -#define CLK_TOP_FLASHIF_AXI 95 -#define CLK_TOP_USBIF 96 -#define CLK_TOP_UART2 97 -#define CLK_TOP_BSI 98 -#define CLK_TOP_RG_SPINOR 99 -#define CLK_TOP_RG_MSDC2 100 -#define CLK_TOP_RG_ETH 101 -#define CLK_TOP_RG_AUD1 102 -#define CLK_TOP_RG_AUD2 103 -#define CLK_TOP_RG_AUD_ENGEN1 104 -#define CLK_TOP_RG_AUD_ENGEN2 105 -#define CLK_TOP_RG_I2C 106 -#define CLK_TOP_RG_PWM_INFRA 107 -#define CLK_TOP_RG_AUD_SPDIF_IN 108 -#define CLK_TOP_RG_UART2 109 -#define CLK_TOP_RG_BSI 110 -#define CLK_TOP_RG_DBG_ATCLK 111 -#define CLK_TOP_RG_NFIECC 112 -#define CLK_TOP_RG_APLL1_D2_EN 113 -#define CLK_TOP_RG_APLL1_D4_EN 114 -#define CLK_TOP_RG_APLL1_D8_EN 115 -#define CLK_TOP_RG_APLL2_D2_EN 116 -#define CLK_TOP_RG_APLL2_D4_EN 117 -#define CLK_TOP_RG_APLL2_D8_EN 118 -#define CLK_TOP_APLL12_DIV0 119 -#define CLK_TOP_APLL12_DIV1 120 -#define CLK_TOP_APLL12_DIV2 121 -#define CLK_TOP_APLL12_DIV3 122 -#define CLK_TOP_APLL12_DIV4 123 -#define CLK_TOP_APLL12_DIV4B 124 -#define CLK_TOP_APLL12_DIV5 125 -#define CLK_TOP_APLL12_DIV5B 126 -#define CLK_TOP_APLL12_DIV6 127 -#define CLK_TOP_UART0_SEL 128 -#define CLK_TOP_EMI_DDRPHY_SEL 129 -#define CLK_TOP_AHB_INFRA_SEL 130 -#define CLK_TOP_MSDC0_SEL 131 -#define CLK_TOP_UART1_SEL 132 -#define CLK_TOP_MSDC1_SEL 133 -#define CLK_TOP_PMICSPI_SEL 134 -#define CLK_TOP_QAXI_AUD26M_SEL 135 -#define CLK_TOP_AUD_INTBUS_SEL 136 -#define CLK_TOP_NFI2X_PAD_SEL 137 -#define CLK_TOP_NFI1X_PAD_SEL 138 -#define CLK_TOP_DDRPHYCFG_SEL 139 -#define CLK_TOP_USB_78M_SEL 140 -#define CLK_TOP_SPINOR_SEL 141 -#define CLK_TOP_MSDC2_SEL 142 -#define CLK_TOP_ETH_SEL 143 -#define CLK_TOP_AUD1_SEL 144 -#define CLK_TOP_AUD2_SEL 145 -#define CLK_TOP_AUD_ENGEN1_SEL 146 -#define CLK_TOP_AUD_ENGEN2_SEL 147 -#define CLK_TOP_I2C_SEL 148 -#define CLK_TOP_AUD_I2S0_M_SEL 149 -#define CLK_TOP_AUD_I2S1_M_SEL 150 -#define CLK_TOP_AUD_I2S2_M_SEL 151 -#define CLK_TOP_AUD_I2S3_M_SEL 152 -#define CLK_TOP_AUD_I2S4_M_SEL 153 -#define CLK_TOP_AUD_I2S5_M_SEL 154 -#define CLK_TOP_AUD_SPDIF_B_SEL 155 -#define CLK_TOP_PWM_SEL 156 -#define CLK_TOP_SPI_SEL 157 -#define CLK_TOP_AUD_SPDIFIN_SEL 158 -#define CLK_TOP_UART2_SEL 159 -#define CLK_TOP_BSI_SEL 160 -#define CLK_TOP_DBG_ATCLK_SEL 161 -#define CLK_TOP_CSW_NFIECC_SEL 162 -#define CLK_TOP_NFIECC_SEL 163 -#define CLK_TOP_APLL12_CK_DIV0 164 -#define CLK_TOP_APLL12_CK_DIV1 165 -#define CLK_TOP_APLL12_CK_DIV2 166 -#define CLK_TOP_APLL12_CK_DIV3 167 -#define CLK_TOP_APLL12_CK_DIV4 168 -#define CLK_TOP_APLL12_CK_DIV4B 169 -#define CLK_TOP_APLL12_CK_DIV5 170 -#define CLK_TOP_APLL12_CK_DIV5B 171 -#define CLK_TOP_APLL12_CK_DIV6 172 -#define CLK_TOP_USB_78M 173 -#define CLK_TOP_MSDC0_INFRA 174 -#define CLK_TOP_MSDC1_INFRA 175 -#define CLK_TOP_MSDC2_INFRA 176 -#define CLK_TOP_NR_CLK 177 - -/* AUDSYS */ - -#define CLK_AUD_AFE 0 -#define CLK_AUD_I2S 1 -#define CLK_AUD_22M 2 -#define CLK_AUD_24M 3 -#define CLK_AUD_INTDIR 4 -#define CLK_AUD_APLL2_TUNER 5 -#define CLK_AUD_APLL_TUNER 6 -#define CLK_AUD_HDMI 7 -#define CLK_AUD_SPDF 8 -#define CLK_AUD_ADC 9 -#define CLK_AUD_DAC 10 -#define CLK_AUD_DAC_PREDIS 11 -#define CLK_AUD_TML 12 -#define CLK_AUD_NR_CLK 13 - -#endif /* _DT_BINDINGS_CLK_MT8516_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/nuvoton,npcm7xx-clock.h b/sys/gnu/dts/include/dt-bindings/clock/nuvoton,npcm7xx-clock.h deleted file mode 100644 index f21522605b9..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/nuvoton,npcm7xx-clock.h +++ /dev/null @@ -1,44 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Nuvoton NPCM7xx Clock Generator binding - * clock binding number for all clocks supportted by nuvoton,npcm7xx-clk - * - * Copyright (C) 2018 Nuvoton Technologies tali.perry@nuvoton.com - * - */ - -#ifndef __DT_BINDINGS_CLOCK_NPCM7XX_H -#define __DT_BINDINGS_CLOCK_NPCM7XX_H - - -#define NPCM7XX_CLK_CPU 0 -#define NPCM7XX_CLK_GFX_PIXEL 1 -#define NPCM7XX_CLK_MC 2 -#define NPCM7XX_CLK_ADC 3 -#define NPCM7XX_CLK_AHB 4 -#define NPCM7XX_CLK_TIMER 5 -#define NPCM7XX_CLK_UART 6 -#define NPCM7XX_CLK_MMC 7 -#define NPCM7XX_CLK_SPI3 8 -#define NPCM7XX_CLK_PCI 9 -#define NPCM7XX_CLK_AXI 10 -#define NPCM7XX_CLK_APB4 11 -#define NPCM7XX_CLK_APB3 12 -#define NPCM7XX_CLK_APB2 13 -#define NPCM7XX_CLK_APB1 14 -#define NPCM7XX_CLK_APB5 15 -#define NPCM7XX_CLK_CLKOUT 16 -#define NPCM7XX_CLK_GFX 17 -#define NPCM7XX_CLK_SU 18 -#define NPCM7XX_CLK_SU48 19 -#define NPCM7XX_CLK_SDHC 20 -#define NPCM7XX_CLK_SPI0 21 -#define NPCM7XX_CLK_SPIX 22 - -#define NPCM7XX_CLK_REFCLK 23 -#define NPCM7XX_CLK_SYSBYPCK 24 -#define NPCM7XX_CLK_MCBYPCK 25 - -#define NPCM7XX_NUM_CLOCKS (NPCM7XX_CLK_MCBYPCK+1) - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/omap4.h b/sys/gnu/dts/include/dt-bindings/clock/omap4.h deleted file mode 100644 index 5167b2d93ac..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/omap4.h +++ /dev/null @@ -1,138 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2017 Texas Instruments, Inc. - */ -#ifndef __DT_BINDINGS_CLK_OMAP4_H -#define __DT_BINDINGS_CLK_OMAP4_H - -#define OMAP4_CLKCTRL_OFFSET 0x20 -#define OMAP4_CLKCTRL_INDEX(offset) ((offset) - OMAP4_CLKCTRL_OFFSET) - -/* mpuss clocks */ -#define OMAP4_MPU_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) - -/* tesla clocks */ -#define OMAP4_DSP_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) - -/* abe clocks */ -#define OMAP4_L4_ABE_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) -#define OMAP4_AESS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) -#define OMAP4_MCPDM_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) -#define OMAP4_DMIC_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38) -#define OMAP4_MCASP_CLKCTRL OMAP4_CLKCTRL_INDEX(0x40) -#define OMAP4_MCBSP1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x48) -#define OMAP4_MCBSP2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x50) -#define OMAP4_MCBSP3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x58) -#define OMAP4_SLIMBUS1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x60) -#define OMAP4_TIMER5_CLKCTRL OMAP4_CLKCTRL_INDEX(0x68) -#define OMAP4_TIMER6_CLKCTRL OMAP4_CLKCTRL_INDEX(0x70) -#define OMAP4_TIMER7_CLKCTRL OMAP4_CLKCTRL_INDEX(0x78) -#define OMAP4_TIMER8_CLKCTRL OMAP4_CLKCTRL_INDEX(0x80) -#define OMAP4_WD_TIMER3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x88) - -/* l4_ao clocks */ -#define OMAP4_SMARTREFLEX_MPU_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) -#define OMAP4_SMARTREFLEX_IVA_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) -#define OMAP4_SMARTREFLEX_CORE_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38) - -/* l3_1 clocks */ -#define OMAP4_L3_MAIN_1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) - -/* l3_2 clocks */ -#define OMAP4_L3_MAIN_2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) -#define OMAP4_GPMC_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) -#define OMAP4_OCMC_RAM_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) - -/* ducati clocks */ -#define OMAP4_IPU_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) - -/* l3_dma clocks */ -#define OMAP4_DMA_SYSTEM_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) - -/* l3_emif clocks */ -#define OMAP4_DMM_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) -#define OMAP4_EMIF1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) -#define OMAP4_EMIF2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38) - -/* d2d clocks */ -#define OMAP4_C2C_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) - -/* l4_cfg clocks */ -#define OMAP4_L4_CFG_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) -#define OMAP4_SPINLOCK_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) -#define OMAP4_MAILBOX_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) - -/* l3_instr clocks */ -#define OMAP4_L3_MAIN_3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) -#define OMAP4_L3_INSTR_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) -#define OMAP4_OCP_WP_NOC_CLKCTRL OMAP4_CLKCTRL_INDEX(0x40) - -/* ivahd clocks */ -#define OMAP4_IVA_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) -#define OMAP4_SL2IF_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) - -/* iss clocks */ -#define OMAP4_ISS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) -#define OMAP4_FDIF_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) - -/* l3_dss clocks */ -#define OMAP4_DSS_CORE_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) - -/* l3_gfx clocks */ -#define OMAP4_GPU_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) - -/* l3_init clocks */ -#define OMAP4_MMC1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) -#define OMAP4_MMC2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) -#define OMAP4_HSI_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38) -#define OMAP4_USB_HOST_HS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x58) -#define OMAP4_USB_OTG_HS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x60) -#define OMAP4_USB_TLL_HS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x68) -#define OMAP4_USB_HOST_FS_CLKCTRL OMAP4_CLKCTRL_INDEX(0xd0) -#define OMAP4_OCP2SCP_USB_PHY_CLKCTRL OMAP4_CLKCTRL_INDEX(0xe0) - -/* l4_per clocks */ -#define OMAP4_TIMER10_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) -#define OMAP4_TIMER11_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) -#define OMAP4_TIMER2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38) -#define OMAP4_TIMER3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x40) -#define OMAP4_TIMER4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x48) -#define OMAP4_TIMER9_CLKCTRL OMAP4_CLKCTRL_INDEX(0x50) -#define OMAP4_ELM_CLKCTRL OMAP4_CLKCTRL_INDEX(0x58) -#define OMAP4_GPIO2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x60) -#define OMAP4_GPIO3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x68) -#define OMAP4_GPIO4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x70) -#define OMAP4_GPIO5_CLKCTRL OMAP4_CLKCTRL_INDEX(0x78) -#define OMAP4_GPIO6_CLKCTRL OMAP4_CLKCTRL_INDEX(0x80) -#define OMAP4_HDQ1W_CLKCTRL OMAP4_CLKCTRL_INDEX(0x88) -#define OMAP4_I2C1_CLKCTRL OMAP4_CLKCTRL_INDEX(0xa0) -#define OMAP4_I2C2_CLKCTRL OMAP4_CLKCTRL_INDEX(0xa8) -#define OMAP4_I2C3_CLKCTRL OMAP4_CLKCTRL_INDEX(0xb0) -#define OMAP4_I2C4_CLKCTRL OMAP4_CLKCTRL_INDEX(0xb8) -#define OMAP4_L4_PER_CLKCTRL OMAP4_CLKCTRL_INDEX(0xc0) -#define OMAP4_MCBSP4_CLKCTRL OMAP4_CLKCTRL_INDEX(0xe0) -#define OMAP4_MCSPI1_CLKCTRL OMAP4_CLKCTRL_INDEX(0xf0) -#define OMAP4_MCSPI2_CLKCTRL OMAP4_CLKCTRL_INDEX(0xf8) -#define OMAP4_MCSPI3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x100) -#define OMAP4_MCSPI4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x108) -#define OMAP4_MMC3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x120) -#define OMAP4_MMC4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x128) -#define OMAP4_SLIMBUS2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x138) -#define OMAP4_UART1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x140) -#define OMAP4_UART2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x148) -#define OMAP4_UART3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x150) -#define OMAP4_UART4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x158) -#define OMAP4_MMC5_CLKCTRL OMAP4_CLKCTRL_INDEX(0x160) - -/* l4_wkup clocks */ -#define OMAP4_L4_WKUP_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) -#define OMAP4_WD_TIMER2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) -#define OMAP4_GPIO1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38) -#define OMAP4_TIMER1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x40) -#define OMAP4_COUNTER_32K_CLKCTRL OMAP4_CLKCTRL_INDEX(0x50) -#define OMAP4_KBD_CLKCTRL OMAP4_CLKCTRL_INDEX(0x78) - -/* emu_sys clocks */ -#define OMAP4_DEBUGSS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/omap5.h b/sys/gnu/dts/include/dt-bindings/clock/omap5.h deleted file mode 100644 index e5411938983..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/omap5.h +++ /dev/null @@ -1,113 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2017 Texas Instruments, Inc. - */ -#ifndef __DT_BINDINGS_CLK_OMAP5_H -#define __DT_BINDINGS_CLK_OMAP5_H - -#define OMAP5_CLKCTRL_OFFSET 0x20 -#define OMAP5_CLKCTRL_INDEX(offset) ((offset) - OMAP5_CLKCTRL_OFFSET) - -/* mpu clocks */ -#define OMAP5_MPU_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) - -/* dsp clocks */ -#define OMAP5_MMU_DSP_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) - -/* abe clocks */ -#define OMAP5_L4_ABE_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) -#define OMAP5_MCPDM_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30) -#define OMAP5_DMIC_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38) -#define OMAP5_MCBSP1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x48) -#define OMAP5_MCBSP2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x50) -#define OMAP5_MCBSP3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x58) -#define OMAP5_TIMER5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x68) -#define OMAP5_TIMER6_CLKCTRL OMAP5_CLKCTRL_INDEX(0x70) -#define OMAP5_TIMER7_CLKCTRL OMAP5_CLKCTRL_INDEX(0x78) -#define OMAP5_TIMER8_CLKCTRL OMAP5_CLKCTRL_INDEX(0x80) - -/* l3main1 clocks */ -#define OMAP5_L3_MAIN_1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) - -/* l3main2 clocks */ -#define OMAP5_L3_MAIN_2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) - -/* ipu clocks */ -#define OMAP5_MMU_IPU_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) - -/* dma clocks */ -#define OMAP5_DMA_SYSTEM_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) - -/* emif clocks */ -#define OMAP5_DMM_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) -#define OMAP5_EMIF1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30) -#define OMAP5_EMIF2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38) - -/* l4cfg clocks */ -#define OMAP5_L4_CFG_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) -#define OMAP5_SPINLOCK_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28) -#define OMAP5_MAILBOX_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30) - -/* l3instr clocks */ -#define OMAP5_L3_MAIN_3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) -#define OMAP5_L3_INSTR_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28) - -/* l4per clocks */ -#define OMAP5_TIMER10_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28) -#define OMAP5_TIMER11_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30) -#define OMAP5_TIMER2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38) -#define OMAP5_TIMER3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x40) -#define OMAP5_TIMER4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x48) -#define OMAP5_TIMER9_CLKCTRL OMAP5_CLKCTRL_INDEX(0x50) -#define OMAP5_GPIO2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x60) -#define OMAP5_GPIO3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x68) -#define OMAP5_GPIO4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x70) -#define OMAP5_GPIO5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x78) -#define OMAP5_GPIO6_CLKCTRL OMAP5_CLKCTRL_INDEX(0x80) -#define OMAP5_I2C1_CLKCTRL OMAP5_CLKCTRL_INDEX(0xa0) -#define OMAP5_I2C2_CLKCTRL OMAP5_CLKCTRL_INDEX(0xa8) -#define OMAP5_I2C3_CLKCTRL OMAP5_CLKCTRL_INDEX(0xb0) -#define OMAP5_I2C4_CLKCTRL OMAP5_CLKCTRL_INDEX(0xb8) -#define OMAP5_L4_PER_CLKCTRL OMAP5_CLKCTRL_INDEX(0xc0) -#define OMAP5_MCSPI1_CLKCTRL OMAP5_CLKCTRL_INDEX(0xf0) -#define OMAP5_MCSPI2_CLKCTRL OMAP5_CLKCTRL_INDEX(0xf8) -#define OMAP5_MCSPI3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x100) -#define OMAP5_MCSPI4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x108) -#define OMAP5_GPIO7_CLKCTRL OMAP5_CLKCTRL_INDEX(0x110) -#define OMAP5_GPIO8_CLKCTRL OMAP5_CLKCTRL_INDEX(0x118) -#define OMAP5_MMC3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x120) -#define OMAP5_MMC4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x128) -#define OMAP5_UART1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x140) -#define OMAP5_UART2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x148) -#define OMAP5_UART3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x150) -#define OMAP5_UART4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x158) -#define OMAP5_MMC5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x160) -#define OMAP5_I2C5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x168) -#define OMAP5_UART5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x170) -#define OMAP5_UART6_CLKCTRL OMAP5_CLKCTRL_INDEX(0x178) - -/* dss clocks */ -#define OMAP5_DSS_CORE_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) - -/* gpu clocks */ -#define OMAP5_GPU_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) - -/* l3init clocks */ -#define OMAP5_MMC1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28) -#define OMAP5_MMC2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30) -#define OMAP5_USB_HOST_HS_CLKCTRL OMAP5_CLKCTRL_INDEX(0x58) -#define OMAP5_USB_TLL_HS_CLKCTRL OMAP5_CLKCTRL_INDEX(0x68) -#define OMAP5_SATA_CLKCTRL OMAP5_CLKCTRL_INDEX(0x88) -#define OMAP5_OCP2SCP1_CLKCTRL OMAP5_CLKCTRL_INDEX(0xe0) -#define OMAP5_OCP2SCP3_CLKCTRL OMAP5_CLKCTRL_INDEX(0xe8) -#define OMAP5_USB_OTG_SS_CLKCTRL OMAP5_CLKCTRL_INDEX(0xf0) - -/* wkupaon clocks */ -#define OMAP5_L4_WKUP_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) -#define OMAP5_WD_TIMER2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30) -#define OMAP5_GPIO1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38) -#define OMAP5_TIMER1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x40) -#define OMAP5_COUNTER_32K_CLKCTRL OMAP5_CLKCTRL_INDEX(0x50) -#define OMAP5_KBD_CLKCTRL OMAP5_CLKCTRL_INDEX(0x78) - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/oxsemi,ox810se.h b/sys/gnu/dts/include/dt-bindings/clock/oxsemi,ox810se.h deleted file mode 100644 index 7256365160f..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/oxsemi,ox810se.h +++ /dev/null @@ -1,19 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) 2016 Neil Armstrong - */ - -#ifndef DT_CLOCK_OXSEMI_OX810SE_H -#define DT_CLOCK_OXSEMI_OX810SE_H - -#define CLK_810_LEON 0 -#define CLK_810_DMA_SGDMA 1 -#define CLK_810_CIPHER 2 -#define CLK_810_SATA 3 -#define CLK_810_AUDIO 4 -#define CLK_810_USBMPH 5 -#define CLK_810_ETHA 6 -#define CLK_810_PCIEA 7 -#define CLK_810_NAND 8 - -#endif /* DT_CLOCK_OXSEMI_OX810SE_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/oxsemi,ox820.h b/sys/gnu/dts/include/dt-bindings/clock/oxsemi,ox820.h deleted file mode 100644 index 55f4226e2f3..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/oxsemi,ox820.h +++ /dev/null @@ -1,29 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) 2016 Neil Armstrong - */ - -#ifndef DT_CLOCK_OXSEMI_OX820_H -#define DT_CLOCK_OXSEMI_OX820_H - -/* PLLs */ -#define CLK_820_PLLA 0 -#define CLK_820_PLLB 1 - -/* Gate Clocks */ -#define CLK_820_LEON 2 -#define CLK_820_DMA_SGDMA 3 -#define CLK_820_CIPHER 4 -#define CLK_820_SD 5 -#define CLK_820_SATA 6 -#define CLK_820_AUDIO 7 -#define CLK_820_USBMPH 8 -#define CLK_820_ETHA 9 -#define CLK_820_PCIEA 10 -#define CLK_820_NAND 11 -#define CLK_820_PCIEB 12 -#define CLK_820_ETHB 13 -#define CLK_820_REF600 14 -#define CLK_820_USBDEV 15 - -#endif /* DT_CLOCK_OXSEMI_OX820_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/pistachio-clk.h b/sys/gnu/dts/include/dt-bindings/clock/pistachio-clk.h deleted file mode 100644 index ec7a8683f3e..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/pistachio-clk.h +++ /dev/null @@ -1,180 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) 2014 Google, Inc. - */ - -#ifndef _DT_BINDINGS_CLOCK_PISTACHIO_H -#define _DT_BINDINGS_CLOCK_PISTACHIO_H - -/* PLLs */ -#define CLK_MIPS_PLL 0 -#define CLK_AUDIO_PLL 1 -#define CLK_RPU_V_PLL 2 -#define CLK_RPU_L_PLL 3 -#define CLK_SYS_PLL 4 -#define CLK_WIFI_PLL 5 -#define CLK_BT_PLL 6 - -/* Fixed-factor clocks */ -#define CLK_WIFI_DIV4 16 -#define CLK_WIFI_DIV8 17 - -/* Gate clocks */ -#define CLK_MIPS 32 -#define CLK_AUDIO_IN 33 -#define CLK_AUDIO 34 -#define CLK_I2S 35 -#define CLK_SPDIF 36 -#define CLK_AUDIO_DAC 37 -#define CLK_RPU_V 38 -#define CLK_RPU_L 39 -#define CLK_RPU_SLEEP 40 -#define CLK_WIFI_PLL_GATE 41 -#define CLK_RPU_CORE 42 -#define CLK_WIFI_ADC 43 -#define CLK_WIFI_DAC 44 -#define CLK_USB_PHY 45 -#define CLK_ENET_IN 46 -#define CLK_ENET 47 -#define CLK_UART0 48 -#define CLK_UART1 49 -#define CLK_PERIPH_SYS 50 -#define CLK_SPI0 51 -#define CLK_SPI1 52 -#define CLK_EVENT_TIMER 53 -#define CLK_AUX_ADC_INTERNAL 54 -#define CLK_AUX_ADC 55 -#define CLK_SD_HOST 56 -#define CLK_BT 57 -#define CLK_BT_DIV4 58 -#define CLK_BT_DIV8 59 -#define CLK_BT_1MHZ 60 - -/* Divider clocks */ -#define CLK_MIPS_INTERNAL_DIV 64 -#define CLK_MIPS_DIV 65 -#define CLK_AUDIO_DIV 66 -#define CLK_I2S_DIV 67 -#define CLK_SPDIF_DIV 68 -#define CLK_AUDIO_DAC_DIV 69 -#define CLK_RPU_V_DIV 70 -#define CLK_RPU_L_DIV 71 -#define CLK_RPU_SLEEP_DIV 72 -#define CLK_RPU_CORE_DIV 73 -#define CLK_USB_PHY_DIV 74 -#define CLK_ENET_DIV 75 -#define CLK_UART0_INTERNAL_DIV 76 -#define CLK_UART0_DIV 77 -#define CLK_UART1_INTERNAL_DIV 78 -#define CLK_UART1_DIV 79 -#define CLK_SYS_INTERNAL_DIV 80 -#define CLK_SPI0_INTERNAL_DIV 81 -#define CLK_SPI0_DIV 82 -#define CLK_SPI1_INTERNAL_DIV 83 -#define CLK_SPI1_DIV 84 -#define CLK_EVENT_TIMER_INTERNAL_DIV 85 -#define CLK_EVENT_TIMER_DIV 86 -#define CLK_AUX_ADC_INTERNAL_DIV 87 -#define CLK_AUX_ADC_DIV 88 -#define CLK_SD_HOST_DIV 89 -#define CLK_BT_DIV 90 -#define CLK_BT_DIV4_DIV 91 -#define CLK_BT_DIV8_DIV 92 -#define CLK_BT_1MHZ_INTERNAL_DIV 93 -#define CLK_BT_1MHZ_DIV 94 - -/* Mux clocks */ -#define CLK_AUDIO_REF_MUX 96 -#define CLK_MIPS_PLL_MUX 97 -#define CLK_AUDIO_PLL_MUX 98 -#define CLK_AUDIO_MUX 99 -#define CLK_RPU_V_PLL_MUX 100 -#define CLK_RPU_L_PLL_MUX 101 -#define CLK_RPU_L_MUX 102 -#define CLK_WIFI_PLL_MUX 103 -#define CLK_WIFI_DIV4_MUX 104 -#define CLK_WIFI_DIV8_MUX 105 -#define CLK_RPU_CORE_MUX 106 -#define CLK_SYS_PLL_MUX 107 -#define CLK_ENET_MUX 108 -#define CLK_EVENT_TIMER_MUX 109 -#define CLK_SD_HOST_MUX 110 -#define CLK_BT_PLL_MUX 111 -#define CLK_DEBUG_MUX 112 - -#define CLK_NR_CLKS 113 - -/* Peripheral gate clocks */ -#define PERIPH_CLK_SYS 0 -#define PERIPH_CLK_SYS_BUS 1 -#define PERIPH_CLK_DDR 2 -#define PERIPH_CLK_ROM 3 -#define PERIPH_CLK_COUNTER_FAST 4 -#define PERIPH_CLK_COUNTER_SLOW 5 -#define PERIPH_CLK_IR 6 -#define PERIPH_CLK_WD 7 -#define PERIPH_CLK_PDM 8 -#define PERIPH_CLK_PWM 9 -#define PERIPH_CLK_I2C0 10 -#define PERIPH_CLK_I2C1 11 -#define PERIPH_CLK_I2C2 12 -#define PERIPH_CLK_I2C3 13 - -/* Peripheral divider clocks */ -#define PERIPH_CLK_ROM_DIV 32 -#define PERIPH_CLK_COUNTER_FAST_DIV 33 -#define PERIPH_CLK_COUNTER_SLOW_PRE_DIV 34 -#define PERIPH_CLK_COUNTER_SLOW_DIV 35 -#define PERIPH_CLK_IR_PRE_DIV 36 -#define PERIPH_CLK_IR_DIV 37 -#define PERIPH_CLK_WD_PRE_DIV 38 -#define PERIPH_CLK_WD_DIV 39 -#define PERIPH_CLK_PDM_PRE_DIV 40 -#define PERIPH_CLK_PDM_DIV 41 -#define PERIPH_CLK_PWM_PRE_DIV 42 -#define PERIPH_CLK_PWM_DIV 43 -#define PERIPH_CLK_I2C0_PRE_DIV 44 -#define PERIPH_CLK_I2C0_DIV 45 -#define PERIPH_CLK_I2C1_PRE_DIV 46 -#define PERIPH_CLK_I2C1_DIV 47 -#define PERIPH_CLK_I2C2_PRE_DIV 48 -#define PERIPH_CLK_I2C2_DIV 49 -#define PERIPH_CLK_I2C3_PRE_DIV 50 -#define PERIPH_CLK_I2C3_DIV 51 - -#define PERIPH_CLK_NR_CLKS 52 - -/* System gate clocks */ -#define SYS_CLK_I2C0 0 -#define SYS_CLK_I2C1 1 -#define SYS_CLK_I2C2 2 -#define SYS_CLK_I2C3 3 -#define SYS_CLK_I2S_IN 4 -#define SYS_CLK_PAUD_OUT 5 -#define SYS_CLK_SPDIF_OUT 6 -#define SYS_CLK_SPI0_MASTER 7 -#define SYS_CLK_SPI0_SLAVE 8 -#define SYS_CLK_PWM 9 -#define SYS_CLK_UART0 10 -#define SYS_CLK_UART1 11 -#define SYS_CLK_SPI1 12 -#define SYS_CLK_MDC 13 -#define SYS_CLK_SD_HOST 14 -#define SYS_CLK_ENET 15 -#define SYS_CLK_IR 16 -#define SYS_CLK_WD 17 -#define SYS_CLK_TIMER 18 -#define SYS_CLK_I2S_OUT 24 -#define SYS_CLK_SPDIF_IN 25 -#define SYS_CLK_EVENT_TIMER 26 -#define SYS_CLK_HASH 27 - -#define SYS_CLK_NR_CLKS 28 - -/* Gates for external input clocks */ -#define EXT_CLK_AUDIO_IN 0 -#define EXT_CLK_ENET_IN 1 - -#define EXT_CLK_NR_CLKS 2 - -#endif /* _DT_BINDINGS_CLOCK_PISTACHIO_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/px30-cru.h b/sys/gnu/dts/include/dt-bindings/clock/px30-cru.h deleted file mode 100644 index 5b1416fcde6..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/px30-cru.h +++ /dev/null @@ -1,391 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ - -#ifndef _DT_BINDINGS_CLK_ROCKCHIP_PX30_H -#define _DT_BINDINGS_CLK_ROCKCHIP_PX30_H - -/* core clocks */ -#define PLL_APLL 1 -#define PLL_DPLL 2 -#define PLL_CPLL 3 -#define PLL_NPLL 4 -#define APLL_BOOST_H 5 -#define APLL_BOOST_L 6 -#define ARMCLK 7 - -/* sclk gates (special clocks) */ -#define USB480M 14 -#define SCLK_PDM 15 -#define SCLK_I2S0_TX 16 -#define SCLK_I2S0_TX_OUT 17 -#define SCLK_I2S0_RX 18 -#define SCLK_I2S0_RX_OUT 19 -#define SCLK_I2S1 20 -#define SCLK_I2S1_OUT 21 -#define SCLK_I2S2 22 -#define SCLK_I2S2_OUT 23 -#define SCLK_UART1 24 -#define SCLK_UART2 25 -#define SCLK_UART3 26 -#define SCLK_UART4 27 -#define SCLK_UART5 28 -#define SCLK_I2C0 29 -#define SCLK_I2C1 30 -#define SCLK_I2C2 31 -#define SCLK_I2C3 32 -#define SCLK_I2C4 33 -#define SCLK_PWM0 34 -#define SCLK_PWM1 35 -#define SCLK_SPI0 36 -#define SCLK_SPI1 37 -#define SCLK_TIMER0 38 -#define SCLK_TIMER1 39 -#define SCLK_TIMER2 40 -#define SCLK_TIMER3 41 -#define SCLK_TIMER4 42 -#define SCLK_TIMER5 43 -#define SCLK_TSADC 44 -#define SCLK_SARADC 45 -#define SCLK_OTP 46 -#define SCLK_OTP_USR 47 -#define SCLK_CRYPTO 48 -#define SCLK_CRYPTO_APK 49 -#define SCLK_DDRC 50 -#define SCLK_ISP 51 -#define SCLK_CIF_OUT 52 -#define SCLK_RGA_CORE 53 -#define SCLK_VOPB_PWM 54 -#define SCLK_NANDC 55 -#define SCLK_SDIO 56 -#define SCLK_EMMC 57 -#define SCLK_SFC 58 -#define SCLK_SDMMC 59 -#define SCLK_OTG_ADP 60 -#define SCLK_GMAC_SRC 61 -#define SCLK_GMAC 62 -#define SCLK_GMAC_RX_TX 63 -#define SCLK_MAC_REF 64 -#define SCLK_MAC_REFOUT 65 -#define SCLK_MAC_OUT 66 -#define SCLK_SDMMC_DRV 67 -#define SCLK_SDMMC_SAMPLE 68 -#define SCLK_SDIO_DRV 69 -#define SCLK_SDIO_SAMPLE 70 -#define SCLK_EMMC_DRV 71 -#define SCLK_EMMC_SAMPLE 72 -#define SCLK_GPU 73 -#define SCLK_PVTM 74 -#define SCLK_CORE_VPU 75 -#define SCLK_GMAC_RMII 76 -#define SCLK_UART2_SRC 77 -#define SCLK_NANDC_DIV 78 -#define SCLK_NANDC_DIV50 79 -#define SCLK_SDIO_DIV 80 -#define SCLK_SDIO_DIV50 81 -#define SCLK_EMMC_DIV 82 -#define SCLK_EMMC_DIV50 83 -#define SCLK_DDRCLK 84 -#define SCLK_UART1_SRC 85 -#define SCLK_SDMMC_DIV 86 -#define SCLK_SDMMC_DIV50 87 - -/* dclk gates */ -#define DCLK_VOPB 150 -#define DCLK_VOPL 151 - -/* aclk gates */ -#define ACLK_GPU 170 -#define ACLK_BUS_PRE 171 -#define ACLK_CRYPTO 172 -#define ACLK_VI_PRE 173 -#define ACLK_VO_PRE 174 -#define ACLK_VPU 175 -#define ACLK_PERI_PRE 176 -#define ACLK_GMAC 178 -#define ACLK_CIF 179 -#define ACLK_ISP 180 -#define ACLK_VOPB 181 -#define ACLK_VOPL 182 -#define ACLK_RGA 183 -#define ACLK_GIC 184 -#define ACLK_DCF 186 -#define ACLK_DMAC 187 -#define ACLK_BUS_SRC 188 -#define ACLK_PERI_SRC 189 - -/* hclk gates */ -#define HCLK_BUS_PRE 240 -#define HCLK_CRYPTO 241 -#define HCLK_VI_PRE 242 -#define HCLK_VO_PRE 243 -#define HCLK_VPU 244 -#define HCLK_PERI_PRE 245 -#define HCLK_MMC_NAND 246 -#define HCLK_SDMMC 247 -#define HCLK_USB 248 -#define HCLK_CIF 249 -#define HCLK_ISP 250 -#define HCLK_VOPB 251 -#define HCLK_VOPL 252 -#define HCLK_RGA 253 -#define HCLK_NANDC 254 -#define HCLK_SDIO 255 -#define HCLK_EMMC 256 -#define HCLK_SFC 257 -#define HCLK_OTG 258 -#define HCLK_HOST 259 -#define HCLK_HOST_ARB 260 -#define HCLK_PDM 261 -#define HCLK_I2S0 262 -#define HCLK_I2S1 263 -#define HCLK_I2S2 264 - -/* pclk gates */ -#define PCLK_BUS_PRE 320 -#define PCLK_DDR 321 -#define PCLK_VO_PRE 322 -#define PCLK_GMAC 323 -#define PCLK_MIPI_DSI 324 -#define PCLK_MIPIDSIPHY 325 -#define PCLK_MIPICSIPHY 326 -#define PCLK_USB_GRF 327 -#define PCLK_DCF 328 -#define PCLK_UART1 329 -#define PCLK_UART2 330 -#define PCLK_UART3 331 -#define PCLK_UART4 332 -#define PCLK_UART5 333 -#define PCLK_I2C0 334 -#define PCLK_I2C1 335 -#define PCLK_I2C2 336 -#define PCLK_I2C3 337 -#define PCLK_I2C4 338 -#define PCLK_PWM0 339 -#define PCLK_PWM1 340 -#define PCLK_SPI0 341 -#define PCLK_SPI1 342 -#define PCLK_SARADC 343 -#define PCLK_TSADC 344 -#define PCLK_TIMER 345 -#define PCLK_OTP_NS 346 -#define PCLK_WDT_NS 347 -#define PCLK_GPIO1 348 -#define PCLK_GPIO2 349 -#define PCLK_GPIO3 350 -#define PCLK_ISP 351 -#define PCLK_CIF 352 -#define PCLK_OTP_PHY 353 - -#define CLK_NR_CLKS (PCLK_OTP_PHY + 1) - -/* pmu-clocks indices */ - -#define PLL_GPLL 1 - -#define SCLK_RTC32K_PMU 4 -#define SCLK_WIFI_PMU 5 -#define SCLK_UART0_PMU 6 -#define SCLK_PVTM_PMU 7 -#define PCLK_PMU_PRE 8 -#define SCLK_REF24M_PMU 9 -#define SCLK_USBPHY_REF 10 -#define SCLK_MIPIDSIPHY_REF 11 - -#define XIN24M_DIV 12 - -#define PCLK_GPIO0_PMU 20 -#define PCLK_UART0_PMU 21 - -#define CLKPMU_NR_CLKS (PCLK_UART0_PMU + 1) - -/* soft-reset indices */ -#define SRST_CORE0_PO 0 -#define SRST_CORE1_PO 1 -#define SRST_CORE2_PO 2 -#define SRST_CORE3_PO 3 -#define SRST_CORE0 4 -#define SRST_CORE1 5 -#define SRST_CORE2 6 -#define SRST_CORE3 7 -#define SRST_CORE0_DBG 8 -#define SRST_CORE1_DBG 9 -#define SRST_CORE2_DBG 10 -#define SRST_CORE3_DBG 11 -#define SRST_TOPDBG 12 -#define SRST_CORE_NOC 13 -#define SRST_STRC_A 14 -#define SRST_L2C 15 - -#define SRST_DAP 16 -#define SRST_CORE_PVTM 17 -#define SRST_GPU 18 -#define SRST_GPU_NIU 19 -#define SRST_UPCTL2 20 -#define SRST_UPCTL2_A 21 -#define SRST_UPCTL2_P 22 -#define SRST_MSCH 23 -#define SRST_MSCH_P 24 -#define SRST_DDRMON_P 25 -#define SRST_DDRSTDBY_P 26 -#define SRST_DDRSTDBY 27 -#define SRST_DDRGRF_p 28 -#define SRST_AXI_SPLIT_A 29 -#define SRST_AXI_CMD_A 30 -#define SRST_AXI_CMD_P 31 - -#define SRST_DDRPHY 32 -#define SRST_DDRPHYDIV 33 -#define SRST_DDRPHY_P 34 -#define SRST_VPU_A 36 -#define SRST_VPU_NIU_A 37 -#define SRST_VPU_H 38 -#define SRST_VPU_NIU_H 39 -#define SRST_VI_NIU_A 40 -#define SRST_VI_NIU_H 41 -#define SRST_ISP_H 42 -#define SRST_ISP 43 -#define SRST_CIF_A 44 -#define SRST_CIF_H 45 -#define SRST_CIF_PCLKIN 46 -#define SRST_MIPICSIPHY_P 47 - -#define SRST_VO_NIU_A 48 -#define SRST_VO_NIU_H 49 -#define SRST_VO_NIU_P 50 -#define SRST_VOPB_A 51 -#define SRST_VOPB_H 52 -#define SRST_VOPB 53 -#define SRST_PWM_VOPB 54 -#define SRST_VOPL_A 55 -#define SRST_VOPL_H 56 -#define SRST_VOPL 57 -#define SRST_RGA_A 58 -#define SRST_RGA_H 59 -#define SRST_RGA 60 -#define SRST_MIPIDSI_HOST_P 61 -#define SRST_MIPIDSIPHY_P 62 -#define SRST_VPU_CORE 63 - -#define SRST_PERI_NIU_A 64 -#define SRST_USB_NIU_H 65 -#define SRST_USB2OTG_H 66 -#define SRST_USB2OTG 67 -#define SRST_USB2OTG_ADP 68 -#define SRST_USB2HOST_H 69 -#define SRST_USB2HOST_ARB_H 70 -#define SRST_USB2HOST_AUX_H 71 -#define SRST_USB2HOST_EHCI 72 -#define SRST_USB2HOST 73 -#define SRST_USBPHYPOR 74 -#define SRST_USBPHY_OTG_PORT 75 -#define SRST_USBPHY_HOST_PORT 76 -#define SRST_USBPHY_GRF 77 -#define SRST_CPU_BOOST_P 78 -#define SRST_CPU_BOOST 79 - -#define SRST_MMC_NAND_NIU_H 80 -#define SRST_SDIO_H 81 -#define SRST_EMMC_H 82 -#define SRST_SFC_H 83 -#define SRST_SFC 84 -#define SRST_SDCARD_NIU_H 85 -#define SRST_SDMMC_H 86 -#define SRST_NANDC_H 89 -#define SRST_NANDC 90 -#define SRST_GMAC_NIU_A 92 -#define SRST_GMAC_NIU_P 93 -#define SRST_GMAC_A 94 - -#define SRST_PMU_NIU_P 96 -#define SRST_PMU_SGRF_P 97 -#define SRST_PMU_GRF_P 98 -#define SRST_PMU 99 -#define SRST_PMU_MEM_P 100 -#define SRST_PMU_GPIO0_P 101 -#define SRST_PMU_UART0_P 102 -#define SRST_PMU_CRU_P 103 -#define SRST_PMU_PVTM 104 -#define SRST_PMU_UART 105 -#define SRST_PMU_NIU_H 106 -#define SRST_PMU_DDR_FAIL_SAVE 107 -#define SRST_PMU_CORE_PERF_A 108 -#define SRST_PMU_CORE_GRF_P 109 -#define SRST_PMU_GPU_PERF_A 110 -#define SRST_PMU_GPU_GRF_P 111 - -#define SRST_CRYPTO_NIU_A 112 -#define SRST_CRYPTO_NIU_H 113 -#define SRST_CRYPTO_A 114 -#define SRST_CRYPTO_H 115 -#define SRST_CRYPTO 116 -#define SRST_CRYPTO_APK 117 -#define SRST_BUS_NIU_H 120 -#define SRST_USB_NIU_P 121 -#define SRST_BUS_TOP_NIU_P 122 -#define SRST_INTMEM_A 123 -#define SRST_GIC_A 124 -#define SRST_ROM_H 126 -#define SRST_DCF_A 127 - -#define SRST_DCF_P 128 -#define SRST_PDM_H 129 -#define SRST_PDM 130 -#define SRST_I2S0_H 131 -#define SRST_I2S0_TX 132 -#define SRST_I2S1_H 133 -#define SRST_I2S1 134 -#define SRST_I2S2_H 135 -#define SRST_I2S2 136 -#define SRST_UART1_P 137 -#define SRST_UART1 138 -#define SRST_UART2_P 139 -#define SRST_UART2 140 -#define SRST_UART3_P 141 -#define SRST_UART3 142 -#define SRST_UART4_P 143 - -#define SRST_UART4 144 -#define SRST_UART5_P 145 -#define SRST_UART5 146 -#define SRST_I2C0_P 147 -#define SRST_I2C0 148 -#define SRST_I2C1_P 149 -#define SRST_I2C1 150 -#define SRST_I2C2_P 151 -#define SRST_I2C2 152 -#define SRST_I2C3_P 153 -#define SRST_I2C3 154 -#define SRST_PWM0_P 157 -#define SRST_PWM0 158 -#define SRST_PWM1_P 159 - -#define SRST_PWM1 160 -#define SRST_SPI0_P 161 -#define SRST_SPI0 162 -#define SRST_SPI1_P 163 -#define SRST_SPI1 164 -#define SRST_SARADC_P 165 -#define SRST_SARADC 166 -#define SRST_TSADC_P 167 -#define SRST_TSADC 168 -#define SRST_TIMER_P 169 -#define SRST_TIMER0 170 -#define SRST_TIMER1 171 -#define SRST_TIMER2 172 -#define SRST_TIMER3 173 -#define SRST_TIMER4 174 -#define SRST_TIMER5 175 - -#define SRST_OTP_NS_P 176 -#define SRST_OTP_NS_SBPI 177 -#define SRST_OTP_NS_USR 178 -#define SRST_OTP_PHY_P 179 -#define SRST_OTP_PHY 180 -#define SRST_WDT_NS_P 181 -#define SRST_GPIO1_P 182 -#define SRST_GPIO2_P 183 -#define SRST_GPIO3_P 184 -#define SRST_SGRF_P 185 -#define SRST_GRF_P 186 -#define SRST_I2S0_RX 191 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/pxa-clock.h b/sys/gnu/dts/include/dt-bindings/clock/pxa-clock.h deleted file mode 100644 index ce3d6b6a2e4..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/pxa-clock.h +++ /dev/null @@ -1,74 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Inspired by original work from pxa2xx-regs.h by Nicolas Pitre - * Copyright (C) 2014 Robert Jarzmik - */ - -#ifndef __DT_BINDINGS_CLOCK_PXA2XX_H__ -#define __DT_BINDINGS_CLOCK_PXA2XX_H__ - -#define CLK_NONE 0 -#define CLK_1WIRE 1 -#define CLK_AC97 2 -#define CLK_AC97CONF 3 -#define CLK_ASSP 4 -#define CLK_BOOT 5 -#define CLK_BTUART 6 -#define CLK_CAMERA 7 -#define CLK_CIR 8 -#define CLK_CORE 9 -#define CLK_DMC 10 -#define CLK_FFUART 11 -#define CLK_FICP 12 -#define CLK_GPIO 13 -#define CLK_HSIO2 14 -#define CLK_HWUART 15 -#define CLK_I2C 16 -#define CLK_I2S 17 -#define CLK_IM 18 -#define CLK_INC 19 -#define CLK_ISC 20 -#define CLK_KEYPAD 21 -#define CLK_LCD 22 -#define CLK_MEMC 23 -#define CLK_MEMSTK 24 -#define CLK_MINI_IM 25 -#define CLK_MINI_LCD 26 -#define CLK_MMC 27 -#define CLK_MMC1 28 -#define CLK_MMC2 29 -#define CLK_MMC3 30 -#define CLK_MSL 31 -#define CLK_MSL0 32 -#define CLK_MVED 33 -#define CLK_NAND 34 -#define CLK_NSSP 35 -#define CLK_OSTIMER 36 -#define CLK_PWM0 37 -#define CLK_PWM1 38 -#define CLK_PWM2 39 -#define CLK_PWM3 40 -#define CLK_PWRI2C 41 -#define CLK_PXA300_GCU 42 -#define CLK_PXA320_GCU 43 -#define CLK_SMC 44 -#define CLK_SSP 45 -#define CLK_SSP1 46 -#define CLK_SSP2 47 -#define CLK_SSP3 48 -#define CLK_SSP4 49 -#define CLK_STUART 50 -#define CLK_TOUCH 51 -#define CLK_TPM 52 -#define CLK_UDC 53 -#define CLK_USB 54 -#define CLK_USB2 55 -#define CLK_USBH 56 -#define CLK_USBHOST 57 -#define CLK_USIM 58 -#define CLK_USIM1 59 -#define CLK_USMI0 60 -#define CLK_OSC32k768 61 -#define CLK_MAX 62 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/qcom,camcc-sdm845.h b/sys/gnu/dts/include/dt-bindings/clock/qcom,camcc-sdm845.h deleted file mode 100644 index 4f7a2d2320b..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/qcom,camcc-sdm845.h +++ /dev/null @@ -1,116 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_CLK_SDM_CAM_CC_SDM845_H -#define _DT_BINDINGS_CLK_SDM_CAM_CC_SDM845_H - -/* CAM_CC clock registers */ -#define CAM_CC_BPS_AHB_CLK 0 -#define CAM_CC_BPS_AREG_CLK 1 -#define CAM_CC_BPS_AXI_CLK 2 -#define CAM_CC_BPS_CLK 3 -#define CAM_CC_BPS_CLK_SRC 4 -#define CAM_CC_CAMNOC_ATB_CLK 5 -#define CAM_CC_CAMNOC_AXI_CLK 6 -#define CAM_CC_CCI_CLK 7 -#define CAM_CC_CCI_CLK_SRC 8 -#define CAM_CC_CPAS_AHB_CLK 9 -#define CAM_CC_CPHY_RX_CLK_SRC 10 -#define CAM_CC_CSI0PHYTIMER_CLK 11 -#define CAM_CC_CSI0PHYTIMER_CLK_SRC 12 -#define CAM_CC_CSI1PHYTIMER_CLK 13 -#define CAM_CC_CSI1PHYTIMER_CLK_SRC 14 -#define CAM_CC_CSI2PHYTIMER_CLK 15 -#define CAM_CC_CSI2PHYTIMER_CLK_SRC 16 -#define CAM_CC_CSI3PHYTIMER_CLK 17 -#define CAM_CC_CSI3PHYTIMER_CLK_SRC 18 -#define CAM_CC_CSIPHY0_CLK 19 -#define CAM_CC_CSIPHY1_CLK 20 -#define CAM_CC_CSIPHY2_CLK 21 -#define CAM_CC_CSIPHY3_CLK 22 -#define CAM_CC_FAST_AHB_CLK_SRC 23 -#define CAM_CC_FD_CORE_CLK 24 -#define CAM_CC_FD_CORE_CLK_SRC 25 -#define CAM_CC_FD_CORE_UAR_CLK 26 -#define CAM_CC_ICP_APB_CLK 27 -#define CAM_CC_ICP_ATB_CLK 28 -#define CAM_CC_ICP_CLK 29 -#define CAM_CC_ICP_CLK_SRC 30 -#define CAM_CC_ICP_CTI_CLK 31 -#define CAM_CC_ICP_TS_CLK 32 -#define CAM_CC_IFE_0_AXI_CLK 33 -#define CAM_CC_IFE_0_CLK 34 -#define CAM_CC_IFE_0_CLK_SRC 35 -#define CAM_CC_IFE_0_CPHY_RX_CLK 36 -#define CAM_CC_IFE_0_CSID_CLK 37 -#define CAM_CC_IFE_0_CSID_CLK_SRC 38 -#define CAM_CC_IFE_0_DSP_CLK 39 -#define CAM_CC_IFE_1_AXI_CLK 40 -#define CAM_CC_IFE_1_CLK 41 -#define CAM_CC_IFE_1_CLK_SRC 42 -#define CAM_CC_IFE_1_CPHY_RX_CLK 43 -#define CAM_CC_IFE_1_CSID_CLK 44 -#define CAM_CC_IFE_1_CSID_CLK_SRC 45 -#define CAM_CC_IFE_1_DSP_CLK 46 -#define CAM_CC_IFE_LITE_CLK 47 -#define CAM_CC_IFE_LITE_CLK_SRC 48 -#define CAM_CC_IFE_LITE_CPHY_RX_CLK 49 -#define CAM_CC_IFE_LITE_CSID_CLK 50 -#define CAM_CC_IFE_LITE_CSID_CLK_SRC 51 -#define CAM_CC_IPE_0_AHB_CLK 52 -#define CAM_CC_IPE_0_AREG_CLK 53 -#define CAM_CC_IPE_0_AXI_CLK 54 -#define CAM_CC_IPE_0_CLK 55 -#define CAM_CC_IPE_0_CLK_SRC 56 -#define CAM_CC_IPE_1_AHB_CLK 57 -#define CAM_CC_IPE_1_AREG_CLK 58 -#define CAM_CC_IPE_1_AXI_CLK 59 -#define CAM_CC_IPE_1_CLK 60 -#define CAM_CC_IPE_1_CLK_SRC 61 -#define CAM_CC_JPEG_CLK 62 -#define CAM_CC_JPEG_CLK_SRC 63 -#define CAM_CC_LRME_CLK 64 -#define CAM_CC_LRME_CLK_SRC 65 -#define CAM_CC_MCLK0_CLK 66 -#define CAM_CC_MCLK0_CLK_SRC 67 -#define CAM_CC_MCLK1_CLK 68 -#define CAM_CC_MCLK1_CLK_SRC 69 -#define CAM_CC_MCLK2_CLK 70 -#define CAM_CC_MCLK2_CLK_SRC 71 -#define CAM_CC_MCLK3_CLK 72 -#define CAM_CC_MCLK3_CLK_SRC 73 -#define CAM_CC_PLL0 74 -#define CAM_CC_PLL0_OUT_EVEN 75 -#define CAM_CC_PLL1 76 -#define CAM_CC_PLL1_OUT_EVEN 77 -#define CAM_CC_PLL2 78 -#define CAM_CC_PLL2_OUT_EVEN 79 -#define CAM_CC_PLL3 80 -#define CAM_CC_PLL3_OUT_EVEN 81 -#define CAM_CC_SLOW_AHB_CLK_SRC 82 -#define CAM_CC_SOC_AHB_CLK 83 -#define CAM_CC_SYS_TMR_CLK 84 - -/* CAM_CC Resets */ -#define TITAN_CAM_CC_CCI_BCR 0 -#define TITAN_CAM_CC_CPAS_BCR 1 -#define TITAN_CAM_CC_CSI0PHY_BCR 2 -#define TITAN_CAM_CC_CSI1PHY_BCR 3 -#define TITAN_CAM_CC_CSI2PHY_BCR 4 -#define TITAN_CAM_CC_MCLK0_BCR 5 -#define TITAN_CAM_CC_MCLK1_BCR 6 -#define TITAN_CAM_CC_MCLK2_BCR 7 -#define TITAN_CAM_CC_MCLK3_BCR 8 -#define TITAN_CAM_CC_TITAN_TOP_BCR 9 - -/* CAM_CC GDSCRs */ -#define BPS_GDSC 0 -#define IPE_0_GDSC 1 -#define IPE_1_GDSC 2 -#define IFE_0_GDSC 3 -#define IFE_1_GDSC 4 -#define TITAN_TOP_GDSC 5 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/qcom,dispcc-sc7180.h b/sys/gnu/dts/include/dt-bindings/clock/qcom,dispcc-sc7180.h deleted file mode 100644 index b9b51617a33..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/qcom,dispcc-sc7180.h +++ /dev/null @@ -1,46 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SC7180_H -#define _DT_BINDINGS_CLK_QCOM_DISP_CC_SC7180_H - -#define DISP_CC_PLL0 0 -#define DISP_CC_PLL0_OUT_EVEN 1 -#define DISP_CC_MDSS_AHB_CLK 2 -#define DISP_CC_MDSS_AHB_CLK_SRC 3 -#define DISP_CC_MDSS_BYTE0_CLK 4 -#define DISP_CC_MDSS_BYTE0_CLK_SRC 5 -#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 6 -#define DISP_CC_MDSS_BYTE0_INTF_CLK 7 -#define DISP_CC_MDSS_DP_AUX_CLK 8 -#define DISP_CC_MDSS_DP_AUX_CLK_SRC 9 -#define DISP_CC_MDSS_DP_CRYPTO_CLK 10 -#define DISP_CC_MDSS_DP_CRYPTO_CLK_SRC 11 -#define DISP_CC_MDSS_DP_LINK_CLK 12 -#define DISP_CC_MDSS_DP_LINK_CLK_SRC 13 -#define DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC 14 -#define DISP_CC_MDSS_DP_LINK_INTF_CLK 15 -#define DISP_CC_MDSS_DP_PIXEL_CLK 16 -#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC 17 -#define DISP_CC_MDSS_ESC0_CLK 18 -#define DISP_CC_MDSS_ESC0_CLK_SRC 19 -#define DISP_CC_MDSS_MDP_CLK 20 -#define DISP_CC_MDSS_MDP_CLK_SRC 21 -#define DISP_CC_MDSS_MDP_LUT_CLK 22 -#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 23 -#define DISP_CC_MDSS_PCLK0_CLK 24 -#define DISP_CC_MDSS_PCLK0_CLK_SRC 25 -#define DISP_CC_MDSS_ROT_CLK 26 -#define DISP_CC_MDSS_ROT_CLK_SRC 27 -#define DISP_CC_MDSS_RSCC_AHB_CLK 28 -#define DISP_CC_MDSS_RSCC_VSYNC_CLK 29 -#define DISP_CC_MDSS_VSYNC_CLK 30 -#define DISP_CC_MDSS_VSYNC_CLK_SRC 31 -#define DISP_CC_XO_CLK 32 - -/* DISP_CC GDSCR */ -#define MDSS_GDSC 0 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/qcom,dispcc-sdm845.h b/sys/gnu/dts/include/dt-bindings/clock/qcom,dispcc-sdm845.h deleted file mode 100644 index 4016fd1d5b4..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/qcom,dispcc-sdm845.h +++ /dev/null @@ -1,56 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_CLK_SDM_DISP_CC_SDM845_H -#define _DT_BINDINGS_CLK_SDM_DISP_CC_SDM845_H - -/* DISP_CC clock registers */ -#define DISP_CC_MDSS_AHB_CLK 0 -#define DISP_CC_MDSS_AXI_CLK 1 -#define DISP_CC_MDSS_BYTE0_CLK 2 -#define DISP_CC_MDSS_BYTE0_CLK_SRC 3 -#define DISP_CC_MDSS_BYTE0_INTF_CLK 4 -#define DISP_CC_MDSS_BYTE1_CLK 5 -#define DISP_CC_MDSS_BYTE1_CLK_SRC 6 -#define DISP_CC_MDSS_BYTE1_INTF_CLK 7 -#define DISP_CC_MDSS_ESC0_CLK 8 -#define DISP_CC_MDSS_ESC0_CLK_SRC 9 -#define DISP_CC_MDSS_ESC1_CLK 10 -#define DISP_CC_MDSS_ESC1_CLK_SRC 11 -#define DISP_CC_MDSS_MDP_CLK 12 -#define DISP_CC_MDSS_MDP_CLK_SRC 13 -#define DISP_CC_MDSS_MDP_LUT_CLK 14 -#define DISP_CC_MDSS_PCLK0_CLK 15 -#define DISP_CC_MDSS_PCLK0_CLK_SRC 16 -#define DISP_CC_MDSS_PCLK1_CLK 17 -#define DISP_CC_MDSS_PCLK1_CLK_SRC 18 -#define DISP_CC_MDSS_ROT_CLK 19 -#define DISP_CC_MDSS_ROT_CLK_SRC 20 -#define DISP_CC_MDSS_RSCC_AHB_CLK 21 -#define DISP_CC_MDSS_RSCC_VSYNC_CLK 22 -#define DISP_CC_MDSS_VSYNC_CLK 23 -#define DISP_CC_MDSS_VSYNC_CLK_SRC 24 -#define DISP_CC_PLL0 25 -#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 26 -#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 27 -#define DISP_CC_MDSS_DP_AUX_CLK 28 -#define DISP_CC_MDSS_DP_AUX_CLK_SRC 29 -#define DISP_CC_MDSS_DP_CRYPTO_CLK 30 -#define DISP_CC_MDSS_DP_CRYPTO_CLK_SRC 31 -#define DISP_CC_MDSS_DP_LINK_CLK 32 -#define DISP_CC_MDSS_DP_LINK_CLK_SRC 33 -#define DISP_CC_MDSS_DP_LINK_INTF_CLK 34 -#define DISP_CC_MDSS_DP_PIXEL1_CLK 35 -#define DISP_CC_MDSS_DP_PIXEL1_CLK_SRC 36 -#define DISP_CC_MDSS_DP_PIXEL_CLK 37 -#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC 38 - -/* DISP_CC Reset */ -#define DISP_CC_MDSS_RSCC_BCR 0 - -/* DISP_CC GDSCR */ -#define MDSS_GDSC 0 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-apq8084.h b/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-apq8084.h deleted file mode 100644 index 7f657cf8cc8..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-apq8084.h +++ /dev/null @@ -1,349 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2014, The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_CLK_APQ_GCC_8084_H -#define _DT_BINDINGS_CLK_APQ_GCC_8084_H - -#define GPLL0 0 -#define GPLL0_VOTE 1 -#define GPLL1 2 -#define GPLL1_VOTE 3 -#define GPLL2 4 -#define GPLL2_VOTE 5 -#define GPLL3 6 -#define GPLL3_VOTE 7 -#define GPLL4 8 -#define GPLL4_VOTE 9 -#define CONFIG_NOC_CLK_SRC 10 -#define PERIPH_NOC_CLK_SRC 11 -#define SYSTEM_NOC_CLK_SRC 12 -#define BLSP_UART_SIM_CLK_SRC 13 -#define QDSS_TSCTR_CLK_SRC 14 -#define UFS_AXI_CLK_SRC 15 -#define RPM_CLK_SRC 16 -#define KPSS_AHB_CLK_SRC 17 -#define QDSS_AT_CLK_SRC 18 -#define BIMC_DDR_CLK_SRC 19 -#define USB30_MASTER_CLK_SRC 20 -#define USB30_SEC_MASTER_CLK_SRC 21 -#define USB_HSIC_AHB_CLK_SRC 22 -#define MMSS_BIMC_GFX_CLK_SRC 23 -#define QDSS_STM_CLK_SRC 24 -#define ACC_CLK_SRC 25 -#define SEC_CTRL_CLK_SRC 26 -#define BLSP1_QUP1_I2C_APPS_CLK_SRC 27 -#define BLSP1_QUP1_SPI_APPS_CLK_SRC 28 -#define BLSP1_QUP2_I2C_APPS_CLK_SRC 29 -#define BLSP1_QUP2_SPI_APPS_CLK_SRC 30 -#define BLSP1_QUP3_I2C_APPS_CLK_SRC 31 -#define BLSP1_QUP3_SPI_APPS_CLK_SRC 32 -#define BLSP1_QUP4_I2C_APPS_CLK_SRC 33 -#define BLSP1_QUP4_SPI_APPS_CLK_SRC 34 -#define BLSP1_QUP5_I2C_APPS_CLK_SRC 35 -#define BLSP1_QUP5_SPI_APPS_CLK_SRC 36 -#define BLSP1_QUP6_I2C_APPS_CLK_SRC 37 -#define BLSP1_QUP6_SPI_APPS_CLK_SRC 38 -#define BLSP1_UART1_APPS_CLK_SRC 39 -#define BLSP1_UART2_APPS_CLK_SRC 40 -#define BLSP1_UART3_APPS_CLK_SRC 41 -#define BLSP1_UART4_APPS_CLK_SRC 42 -#define BLSP1_UART5_APPS_CLK_SRC 43 -#define BLSP1_UART6_APPS_CLK_SRC 44 -#define BLSP2_QUP1_I2C_APPS_CLK_SRC 45 -#define BLSP2_QUP1_SPI_APPS_CLK_SRC 46 -#define BLSP2_QUP2_I2C_APPS_CLK_SRC 47 -#define BLSP2_QUP2_SPI_APPS_CLK_SRC 48 -#define BLSP2_QUP3_I2C_APPS_CLK_SRC 49 -#define BLSP2_QUP3_SPI_APPS_CLK_SRC 50 -#define BLSP2_QUP4_I2C_APPS_CLK_SRC 51 -#define BLSP2_QUP4_SPI_APPS_CLK_SRC 52 -#define BLSP2_QUP5_I2C_APPS_CLK_SRC 53 -#define BLSP2_QUP5_SPI_APPS_CLK_SRC 54 -#define BLSP2_QUP6_I2C_APPS_CLK_SRC 55 -#define BLSP2_QUP6_SPI_APPS_CLK_SRC 56 -#define BLSP2_UART1_APPS_CLK_SRC 57 -#define BLSP2_UART2_APPS_CLK_SRC 58 -#define BLSP2_UART3_APPS_CLK_SRC 59 -#define BLSP2_UART4_APPS_CLK_SRC 60 -#define BLSP2_UART5_APPS_CLK_SRC 61 -#define BLSP2_UART6_APPS_CLK_SRC 62 -#define CE1_CLK_SRC 63 -#define CE2_CLK_SRC 64 -#define CE3_CLK_SRC 65 -#define GP1_CLK_SRC 66 -#define GP2_CLK_SRC 67 -#define GP3_CLK_SRC 68 -#define PDM2_CLK_SRC 69 -#define QDSS_TRACECLKIN_CLK_SRC 70 -#define RBCPR_CLK_SRC 71 -#define SATA_ASIC0_CLK_SRC 72 -#define SATA_PMALIVE_CLK_SRC 73 -#define SATA_RX_CLK_SRC 74 -#define SATA_RX_OOB_CLK_SRC 75 -#define SDCC1_APPS_CLK_SRC 76 -#define SDCC2_APPS_CLK_SRC 77 -#define SDCC3_APPS_CLK_SRC 78 -#define SDCC4_APPS_CLK_SRC 79 -#define GCC_SNOC_BUS_TIMEOUT0_AHB_CLK 80 -#define SPMI_AHB_CLK_SRC 81 -#define SPMI_SER_CLK_SRC 82 -#define TSIF_REF_CLK_SRC 83 -#define USB30_MOCK_UTMI_CLK_SRC 84 -#define USB30_SEC_MOCK_UTMI_CLK_SRC 85 -#define USB_HS_SYSTEM_CLK_SRC 86 -#define USB_HSIC_CLK_SRC 87 -#define USB_HSIC_IO_CAL_CLK_SRC 88 -#define USB_HSIC_MOCK_UTMI_CLK_SRC 89 -#define USB_HSIC_SYSTEM_CLK_SRC 90 -#define GCC_BAM_DMA_AHB_CLK 91 -#define GCC_BAM_DMA_INACTIVITY_TIMERS_CLK 92 -#define DDR_CLK_SRC 93 -#define GCC_BIMC_CFG_AHB_CLK 94 -#define GCC_BIMC_CLK 95 -#define GCC_BIMC_KPSS_AXI_CLK 96 -#define GCC_BIMC_SLEEP_CLK 97 -#define GCC_BIMC_SYSNOC_AXI_CLK 98 -#define GCC_BIMC_XO_CLK 99 -#define GCC_BLSP1_AHB_CLK 100 -#define GCC_BLSP1_SLEEP_CLK 101 -#define GCC_BLSP1_QUP1_I2C_APPS_CLK 102 -#define GCC_BLSP1_QUP1_SPI_APPS_CLK 103 -#define GCC_BLSP1_QUP2_I2C_APPS_CLK 104 -#define GCC_BLSP1_QUP2_SPI_APPS_CLK 105 -#define GCC_BLSP1_QUP3_I2C_APPS_CLK 106 -#define GCC_BLSP1_QUP3_SPI_APPS_CLK 107 -#define GCC_BLSP1_QUP4_I2C_APPS_CLK 108 -#define GCC_BLSP1_QUP4_SPI_APPS_CLK 109 -#define GCC_BLSP1_QUP5_I2C_APPS_CLK 110 -#define GCC_BLSP1_QUP5_SPI_APPS_CLK 111 -#define GCC_BLSP1_QUP6_I2C_APPS_CLK 112 -#define GCC_BLSP1_QUP6_SPI_APPS_CLK 113 -#define GCC_BLSP1_UART1_APPS_CLK 114 -#define GCC_BLSP1_UART1_SIM_CLK 115 -#define GCC_BLSP1_UART2_APPS_CLK 116 -#define GCC_BLSP1_UART2_SIM_CLK 117 -#define GCC_BLSP1_UART3_APPS_CLK 118 -#define GCC_BLSP1_UART3_SIM_CLK 119 -#define GCC_BLSP1_UART4_APPS_CLK 120 -#define GCC_BLSP1_UART4_SIM_CLK 121 -#define GCC_BLSP1_UART5_APPS_CLK 122 -#define GCC_BLSP1_UART5_SIM_CLK 123 -#define GCC_BLSP1_UART6_APPS_CLK 124 -#define GCC_BLSP1_UART6_SIM_CLK 125 -#define GCC_BLSP2_AHB_CLK 126 -#define GCC_BLSP2_SLEEP_CLK 127 -#define GCC_BLSP2_QUP1_I2C_APPS_CLK 128 -#define GCC_BLSP2_QUP1_SPI_APPS_CLK 129 -#define GCC_BLSP2_QUP2_I2C_APPS_CLK 130 -#define GCC_BLSP2_QUP2_SPI_APPS_CLK 131 -#define GCC_BLSP2_QUP3_I2C_APPS_CLK 132 -#define GCC_BLSP2_QUP3_SPI_APPS_CLK 133 -#define GCC_BLSP2_QUP4_I2C_APPS_CLK 134 -#define GCC_BLSP2_QUP4_SPI_APPS_CLK 135 -#define GCC_BLSP2_QUP5_I2C_APPS_CLK 136 -#define GCC_BLSP2_QUP5_SPI_APPS_CLK 137 -#define GCC_BLSP2_QUP6_I2C_APPS_CLK 138 -#define GCC_BLSP2_QUP6_SPI_APPS_CLK 139 -#define GCC_BLSP2_UART1_APPS_CLK 140 -#define GCC_BLSP2_UART1_SIM_CLK 141 -#define GCC_BLSP2_UART2_APPS_CLK 142 -#define GCC_BLSP2_UART2_SIM_CLK 143 -#define GCC_BLSP2_UART3_APPS_CLK 144 -#define GCC_BLSP2_UART3_SIM_CLK 145 -#define GCC_BLSP2_UART4_APPS_CLK 146 -#define GCC_BLSP2_UART4_SIM_CLK 147 -#define GCC_BLSP2_UART5_APPS_CLK 148 -#define GCC_BLSP2_UART5_SIM_CLK 149 -#define GCC_BLSP2_UART6_APPS_CLK 150 -#define GCC_BLSP2_UART6_SIM_CLK 151 -#define GCC_BOOT_ROM_AHB_CLK 152 -#define GCC_CE1_AHB_CLK 153 -#define GCC_CE1_AXI_CLK 154 -#define GCC_CE1_CLK 155 -#define GCC_CE2_AHB_CLK 156 -#define GCC_CE2_AXI_CLK 157 -#define GCC_CE2_CLK 158 -#define GCC_CE3_AHB_CLK 159 -#define GCC_CE3_AXI_CLK 160 -#define GCC_CE3_CLK 161 -#define GCC_CNOC_BUS_TIMEOUT0_AHB_CLK 162 -#define GCC_CNOC_BUS_TIMEOUT1_AHB_CLK 163 -#define GCC_CNOC_BUS_TIMEOUT2_AHB_CLK 164 -#define GCC_CNOC_BUS_TIMEOUT3_AHB_CLK 165 -#define GCC_CNOC_BUS_TIMEOUT4_AHB_CLK 166 -#define GCC_CNOC_BUS_TIMEOUT5_AHB_CLK 167 -#define GCC_CNOC_BUS_TIMEOUT6_AHB_CLK 168 -#define GCC_CNOC_BUS_TIMEOUT7_AHB_CLK 169 -#define GCC_CFG_NOC_AHB_CLK 170 -#define GCC_CFG_NOC_DDR_CFG_CLK 171 -#define GCC_CFG_NOC_RPM_AHB_CLK 172 -#define GCC_COPSS_SMMU_AHB_CLK 173 -#define GCC_COPSS_SMMU_AXI_CLK 174 -#define GCC_DCD_XO_CLK 175 -#define GCC_BIMC_DDR_CH0_CLK 176 -#define GCC_BIMC_DDR_CH1_CLK 177 -#define GCC_BIMC_DDR_CPLL0_CLK 178 -#define GCC_BIMC_DDR_CPLL1_CLK 179 -#define GCC_BIMC_GFX_CLK 180 -#define GCC_DDR_DIM_CFG_CLK 181 -#define GCC_DDR_DIM_SLEEP_CLK 182 -#define GCC_DEHR_CLK 183 -#define GCC_AHB_CLK 184 -#define GCC_IM_SLEEP_CLK 185 -#define GCC_XO_CLK 186 -#define GCC_XO_DIV4_CLK 187 -#define GCC_GP1_CLK 188 -#define GCC_GP2_CLK 189 -#define GCC_GP3_CLK 190 -#define GCC_IMEM_AXI_CLK 191 -#define GCC_IMEM_CFG_AHB_CLK 192 -#define GCC_KPSS_AHB_CLK 193 -#define GCC_KPSS_AXI_CLK 194 -#define GCC_LPASS_MPORT_AXI_CLK 195 -#define GCC_LPASS_Q6_AXI_CLK 196 -#define GCC_LPASS_SWAY_CLK 197 -#define GCC_MMSS_BIMC_GFX_CLK 198 -#define GCC_MMSS_NOC_AT_CLK 199 -#define GCC_MMSS_NOC_CFG_AHB_CLK 200 -#define GCC_MMSS_VPU_MAPLE_SYS_NOC_AXI_CLK 201 -#define GCC_OCMEM_NOC_CFG_AHB_CLK 202 -#define GCC_OCMEM_SYS_NOC_AXI_CLK 203 -#define GCC_MPM_AHB_CLK 204 -#define GCC_MSG_RAM_AHB_CLK 205 -#define GCC_NOC_CONF_XPU_AHB_CLK 206 -#define GCC_PDM2_CLK 207 -#define GCC_PDM_AHB_CLK 208 -#define GCC_PDM_XO4_CLK 209 -#define GCC_PERIPH_NOC_AHB_CLK 210 -#define GCC_PERIPH_NOC_AT_CLK 211 -#define GCC_PERIPH_NOC_CFG_AHB_CLK 212 -#define GCC_PERIPH_NOC_USB_HSIC_AHB_CLK 213 -#define GCC_PERIPH_NOC_MPU_CFG_AHB_CLK 214 -#define GCC_PERIPH_XPU_AHB_CLK 215 -#define GCC_PNOC_BUS_TIMEOUT0_AHB_CLK 216 -#define GCC_PNOC_BUS_TIMEOUT1_AHB_CLK 217 -#define GCC_PNOC_BUS_TIMEOUT2_AHB_CLK 218 -#define GCC_PNOC_BUS_TIMEOUT3_AHB_CLK 219 -#define GCC_PNOC_BUS_TIMEOUT4_AHB_CLK 220 -#define GCC_PRNG_AHB_CLK 221 -#define GCC_QDSS_AT_CLK 222 -#define GCC_QDSS_CFG_AHB_CLK 223 -#define GCC_QDSS_DAP_AHB_CLK 224 -#define GCC_QDSS_DAP_CLK 225 -#define GCC_QDSS_ETR_USB_CLK 226 -#define GCC_QDSS_STM_CLK 227 -#define GCC_QDSS_TRACECLKIN_CLK 228 -#define GCC_QDSS_TSCTR_DIV16_CLK 229 -#define GCC_QDSS_TSCTR_DIV2_CLK 230 -#define GCC_QDSS_TSCTR_DIV3_CLK 231 -#define GCC_QDSS_TSCTR_DIV4_CLK 232 -#define GCC_QDSS_TSCTR_DIV8_CLK 233 -#define GCC_QDSS_RBCPR_XPU_AHB_CLK 234 -#define GCC_RBCPR_AHB_CLK 235 -#define GCC_RBCPR_CLK 236 -#define GCC_RPM_BUS_AHB_CLK 237 -#define GCC_RPM_PROC_HCLK 238 -#define GCC_RPM_SLEEP_CLK 239 -#define GCC_RPM_TIMER_CLK 240 -#define GCC_SATA_ASIC0_CLK 241 -#define GCC_SATA_AXI_CLK 242 -#define GCC_SATA_CFG_AHB_CLK 243 -#define GCC_SATA_PMALIVE_CLK 244 -#define GCC_SATA_RX_CLK 245 -#define GCC_SATA_RX_OOB_CLK 246 -#define GCC_SDCC1_AHB_CLK 247 -#define GCC_SDCC1_APPS_CLK 248 -#define GCC_SDCC1_CDCCAL_FF_CLK 249 -#define GCC_SDCC1_CDCCAL_SLEEP_CLK 250 -#define GCC_SDCC2_AHB_CLK 251 -#define GCC_SDCC2_APPS_CLK 252 -#define GCC_SDCC2_INACTIVITY_TIMERS_CLK 253 -#define GCC_SDCC3_AHB_CLK 254 -#define GCC_SDCC3_APPS_CLK 255 -#define GCC_SDCC3_INACTIVITY_TIMERS_CLK 256 -#define GCC_SDCC4_AHB_CLK 257 -#define GCC_SDCC4_APPS_CLK 258 -#define GCC_SDCC4_INACTIVITY_TIMERS_CLK 259 -#define GCC_SEC_CTRL_ACC_CLK 260 -#define GCC_SEC_CTRL_AHB_CLK 261 -#define GCC_SEC_CTRL_BOOT_ROM_PATCH_CLK 262 -#define GCC_SEC_CTRL_CLK 263 -#define GCC_SEC_CTRL_SENSE_CLK 264 -#define GCC_SNOC_BUS_TIMEOUT2_AHB_CLK 265 -#define GCC_SNOC_BUS_TIMEOUT3_AHB_CLK 266 -#define GCC_SPDM_BIMC_CY_CLK 267 -#define GCC_SPDM_CFG_AHB_CLK 268 -#define GCC_SPDM_DEBUG_CY_CLK 269 -#define GCC_SPDM_FF_CLK 270 -#define GCC_SPDM_MSTR_AHB_CLK 271 -#define GCC_SPDM_PNOC_CY_CLK 272 -#define GCC_SPDM_RPM_CY_CLK 273 -#define GCC_SPDM_SNOC_CY_CLK 274 -#define GCC_SPMI_AHB_CLK 275 -#define GCC_SPMI_CNOC_AHB_CLK 276 -#define GCC_SPMI_SER_CLK 277 -#define GCC_SPSS_AHB_CLK 278 -#define GCC_SNOC_CNOC_AHB_CLK 279 -#define GCC_SNOC_PNOC_AHB_CLK 280 -#define GCC_SYS_NOC_AT_CLK 281 -#define GCC_SYS_NOC_AXI_CLK 282 -#define GCC_SYS_NOC_KPSS_AHB_CLK 283 -#define GCC_SYS_NOC_QDSS_STM_AXI_CLK 284 -#define GCC_SYS_NOC_UFS_AXI_CLK 285 -#define GCC_SYS_NOC_USB3_AXI_CLK 286 -#define GCC_SYS_NOC_USB3_SEC_AXI_CLK 287 -#define GCC_TCSR_AHB_CLK 288 -#define GCC_TLMM_AHB_CLK 289 -#define GCC_TLMM_CLK 290 -#define GCC_TSIF_AHB_CLK 291 -#define GCC_TSIF_INACTIVITY_TIMERS_CLK 292 -#define GCC_TSIF_REF_CLK 293 -#define GCC_UFS_AHB_CLK 294 -#define GCC_UFS_AXI_CLK 295 -#define GCC_UFS_RX_CFG_CLK 296 -#define GCC_UFS_RX_SYMBOL_0_CLK 297 -#define GCC_UFS_RX_SYMBOL_1_CLK 298 -#define GCC_UFS_TX_CFG_CLK 299 -#define GCC_UFS_TX_SYMBOL_0_CLK 300 -#define GCC_UFS_TX_SYMBOL_1_CLK 301 -#define GCC_USB2A_PHY_SLEEP_CLK 302 -#define GCC_USB2B_PHY_SLEEP_CLK 303 -#define GCC_USB30_MASTER_CLK 304 -#define GCC_USB30_MOCK_UTMI_CLK 305 -#define GCC_USB30_SLEEP_CLK 306 -#define GCC_USB30_SEC_MASTER_CLK 307 -#define GCC_USB30_SEC_MOCK_UTMI_CLK 308 -#define GCC_USB30_SEC_SLEEP_CLK 309 -#define GCC_USB_HS_AHB_CLK 310 -#define GCC_USB_HS_INACTIVITY_TIMERS_CLK 311 -#define GCC_USB_HS_SYSTEM_CLK 312 -#define GCC_USB_HSIC_AHB_CLK 313 -#define GCC_USB_HSIC_CLK 314 -#define GCC_USB_HSIC_IO_CAL_CLK 315 -#define GCC_USB_HSIC_IO_CAL_SLEEP_CLK 316 -#define GCC_USB_HSIC_MOCK_UTMI_CLK 317 -#define GCC_USB_HSIC_SYSTEM_CLK 318 -#define PCIE_0_AUX_CLK_SRC 319 -#define PCIE_0_PIPE_CLK_SRC 320 -#define PCIE_1_AUX_CLK_SRC 321 -#define PCIE_1_PIPE_CLK_SRC 322 -#define GCC_PCIE_0_AUX_CLK 323 -#define GCC_PCIE_0_CFG_AHB_CLK 324 -#define GCC_PCIE_0_MSTR_AXI_CLK 325 -#define GCC_PCIE_0_PIPE_CLK 326 -#define GCC_PCIE_0_SLV_AXI_CLK 327 -#define GCC_PCIE_1_AUX_CLK 328 -#define GCC_PCIE_1_CFG_AHB_CLK 329 -#define GCC_PCIE_1_MSTR_AXI_CLK 330 -#define GCC_PCIE_1_PIPE_CLK 331 -#define GCC_PCIE_1_SLV_AXI_CLK 332 - -/* gdscs */ -#define USB_HS_HSIC_GDSC 0 -#define PCIE0_GDSC 1 -#define PCIE1_GDSC 2 -#define USB30_GDSC 3 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-ipq4019.h b/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-ipq4019.h deleted file mode 100644 index 7e8a7be6dcd..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-ipq4019.h +++ /dev/null @@ -1,169 +0,0 @@ -/* Copyright (c) 2015 The Linux Foundation. All rights reserved. - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - */ -#ifndef __QCOM_CLK_IPQ4019_H__ -#define __QCOM_CLK_IPQ4019_H__ - -#define GCC_DUMMY_CLK 0 -#define AUDIO_CLK_SRC 1 -#define BLSP1_QUP1_I2C_APPS_CLK_SRC 2 -#define BLSP1_QUP1_SPI_APPS_CLK_SRC 3 -#define BLSP1_QUP2_I2C_APPS_CLK_SRC 4 -#define BLSP1_QUP2_SPI_APPS_CLK_SRC 5 -#define BLSP1_UART1_APPS_CLK_SRC 6 -#define BLSP1_UART2_APPS_CLK_SRC 7 -#define GCC_USB3_MOCK_UTMI_CLK_SRC 8 -#define GCC_APPS_CLK_SRC 9 -#define GCC_APPS_AHB_CLK_SRC 10 -#define GP1_CLK_SRC 11 -#define GP2_CLK_SRC 12 -#define GP3_CLK_SRC 13 -#define SDCC1_APPS_CLK_SRC 14 -#define FEPHY_125M_DLY_CLK_SRC 15 -#define WCSS2G_CLK_SRC 16 -#define WCSS5G_CLK_SRC 17 -#define GCC_APSS_AHB_CLK 18 -#define GCC_AUDIO_AHB_CLK 19 -#define GCC_AUDIO_PWM_CLK 20 -#define GCC_BLSP1_AHB_CLK 21 -#define GCC_BLSP1_QUP1_I2C_APPS_CLK 22 -#define GCC_BLSP1_QUP1_SPI_APPS_CLK 23 -#define GCC_BLSP1_QUP2_I2C_APPS_CLK 24 -#define GCC_BLSP1_QUP2_SPI_APPS_CLK 25 -#define GCC_BLSP1_UART1_APPS_CLK 26 -#define GCC_BLSP1_UART2_APPS_CLK 27 -#define GCC_DCD_XO_CLK 28 -#define GCC_GP1_CLK 29 -#define GCC_GP2_CLK 30 -#define GCC_GP3_CLK 31 -#define GCC_BOOT_ROM_AHB_CLK 32 -#define GCC_CRYPTO_AHB_CLK 33 -#define GCC_CRYPTO_AXI_CLK 34 -#define GCC_CRYPTO_CLK 35 -#define GCC_ESS_CLK 36 -#define GCC_IMEM_AXI_CLK 37 -#define GCC_IMEM_CFG_AHB_CLK 38 -#define GCC_PCIE_AHB_CLK 39 -#define GCC_PCIE_AXI_M_CLK 40 -#define GCC_PCIE_AXI_S_CLK 41 -#define GCC_PCNOC_AHB_CLK 42 -#define GCC_PRNG_AHB_CLK 43 -#define GCC_QPIC_AHB_CLK 44 -#define GCC_QPIC_CLK 45 -#define GCC_SDCC1_AHB_CLK 46 -#define GCC_SDCC1_APPS_CLK 47 -#define GCC_SNOC_PCNOC_AHB_CLK 48 -#define GCC_SYS_NOC_125M_CLK 49 -#define GCC_SYS_NOC_AXI_CLK 50 -#define GCC_TCSR_AHB_CLK 51 -#define GCC_TLMM_AHB_CLK 52 -#define GCC_USB2_MASTER_CLK 53 -#define GCC_USB2_SLEEP_CLK 54 -#define GCC_USB2_MOCK_UTMI_CLK 55 -#define GCC_USB3_MASTER_CLK 56 -#define GCC_USB3_SLEEP_CLK 57 -#define GCC_USB3_MOCK_UTMI_CLK 58 -#define GCC_WCSS2G_CLK 59 -#define GCC_WCSS2G_REF_CLK 60 -#define GCC_WCSS2G_RTC_CLK 61 -#define GCC_WCSS5G_CLK 62 -#define GCC_WCSS5G_REF_CLK 63 -#define GCC_WCSS5G_RTC_CLK 64 -#define GCC_APSS_DDRPLL_VCO 65 -#define GCC_SDCC_PLLDIV_CLK 66 -#define GCC_FEPLL_VCO 67 -#define GCC_FEPLL125_CLK 68 -#define GCC_FEPLL125DLY_CLK 69 -#define GCC_FEPLL200_CLK 70 -#define GCC_FEPLL500_CLK 71 -#define GCC_FEPLL_WCSS2G_CLK 72 -#define GCC_FEPLL_WCSS5G_CLK 73 -#define GCC_APSS_CPU_PLLDIV_CLK 74 -#define GCC_PCNOC_AHB_CLK_SRC 75 - -#define WIFI0_CPU_INIT_RESET 0 -#define WIFI0_RADIO_SRIF_RESET 1 -#define WIFI0_RADIO_WARM_RESET 2 -#define WIFI0_RADIO_COLD_RESET 3 -#define WIFI0_CORE_WARM_RESET 4 -#define WIFI0_CORE_COLD_RESET 5 -#define WIFI1_CPU_INIT_RESET 6 -#define WIFI1_RADIO_SRIF_RESET 7 -#define WIFI1_RADIO_WARM_RESET 8 -#define WIFI1_RADIO_COLD_RESET 9 -#define WIFI1_CORE_WARM_RESET 10 -#define WIFI1_CORE_COLD_RESET 11 -#define USB3_UNIPHY_PHY_ARES 12 -#define USB3_HSPHY_POR_ARES 13 -#define USB3_HSPHY_S_ARES 14 -#define USB2_HSPHY_POR_ARES 15 -#define USB2_HSPHY_S_ARES 16 -#define PCIE_PHY_AHB_ARES 17 -#define PCIE_AHB_ARES 18 -#define PCIE_PWR_ARES 19 -#define PCIE_PIPE_STICKY_ARES 20 -#define PCIE_AXI_M_STICKY_ARES 21 -#define PCIE_PHY_ARES 22 -#define PCIE_PARF_XPU_ARES 23 -#define PCIE_AXI_S_XPU_ARES 24 -#define PCIE_AXI_M_VMIDMT_ARES 25 -#define PCIE_PIPE_ARES 26 -#define PCIE_AXI_S_ARES 27 -#define PCIE_AXI_M_ARES 28 -#define ESS_RESET 29 -#define GCC_BLSP1_BCR 30 -#define GCC_BLSP1_QUP1_BCR 31 -#define GCC_BLSP1_UART1_BCR 32 -#define GCC_BLSP1_QUP2_BCR 33 -#define GCC_BLSP1_UART2_BCR 34 -#define GCC_BIMC_BCR 35 -#define GCC_TLMM_BCR 36 -#define GCC_IMEM_BCR 37 -#define GCC_ESS_BCR 38 -#define GCC_PRNG_BCR 39 -#define GCC_BOOT_ROM_BCR 40 -#define GCC_CRYPTO_BCR 41 -#define GCC_SDCC1_BCR 42 -#define GCC_SEC_CTRL_BCR 43 -#define GCC_AUDIO_BCR 44 -#define GCC_QPIC_BCR 45 -#define GCC_PCIE_BCR 46 -#define GCC_USB2_BCR 47 -#define GCC_USB2_PHY_BCR 48 -#define GCC_USB3_BCR 49 -#define GCC_USB3_PHY_BCR 50 -#define GCC_SYSTEM_NOC_BCR 51 -#define GCC_PCNOC_BCR 52 -#define GCC_DCD_BCR 53 -#define GCC_SNOC_BUS_TIMEOUT0_BCR 54 -#define GCC_SNOC_BUS_TIMEOUT1_BCR 55 -#define GCC_SNOC_BUS_TIMEOUT2_BCR 56 -#define GCC_SNOC_BUS_TIMEOUT3_BCR 57 -#define GCC_PCNOC_BUS_TIMEOUT0_BCR 58 -#define GCC_PCNOC_BUS_TIMEOUT1_BCR 59 -#define GCC_PCNOC_BUS_TIMEOUT2_BCR 60 -#define GCC_PCNOC_BUS_TIMEOUT3_BCR 61 -#define GCC_PCNOC_BUS_TIMEOUT4_BCR 62 -#define GCC_PCNOC_BUS_TIMEOUT5_BCR 63 -#define GCC_PCNOC_BUS_TIMEOUT6_BCR 64 -#define GCC_PCNOC_BUS_TIMEOUT7_BCR 65 -#define GCC_PCNOC_BUS_TIMEOUT8_BCR 66 -#define GCC_PCNOC_BUS_TIMEOUT9_BCR 67 -#define GCC_TCSR_BCR 68 -#define GCC_QDSS_BCR 69 -#define GCC_MPM_BCR 70 -#define GCC_SPDM_BCR 71 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-ipq6018.h b/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-ipq6018.h deleted file mode 100644 index 6f4be3aa0ac..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-ipq6018.h +++ /dev/null @@ -1,262 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_CLOCK_IPQ_GCC_6018_H -#define _DT_BINDINGS_CLOCK_IPQ_GCC_6018_H - -#define GPLL0 0 -#define UBI32_PLL 1 -#define GPLL6 2 -#define GPLL4 3 -#define PCNOC_BFDCD_CLK_SRC 4 -#define GPLL2 5 -#define NSS_CRYPTO_PLL 6 -#define NSS_PPE_CLK_SRC 7 -#define GCC_XO_CLK_SRC 8 -#define NSS_CE_CLK_SRC 9 -#define GCC_SLEEP_CLK_SRC 10 -#define APSS_AHB_CLK_SRC 11 -#define NSS_PORT5_RX_CLK_SRC 12 -#define NSS_PORT5_TX_CLK_SRC 13 -#define PCIE0_AXI_CLK_SRC 14 -#define USB0_MASTER_CLK_SRC 15 -#define APSS_AHB_POSTDIV_CLK_SRC 16 -#define NSS_PORT1_RX_CLK_SRC 17 -#define NSS_PORT1_TX_CLK_SRC 18 -#define NSS_PORT2_RX_CLK_SRC 19 -#define NSS_PORT2_TX_CLK_SRC 20 -#define NSS_PORT3_RX_CLK_SRC 21 -#define NSS_PORT3_TX_CLK_SRC 22 -#define NSS_PORT4_RX_CLK_SRC 23 -#define NSS_PORT4_TX_CLK_SRC 24 -#define NSS_PORT5_RX_DIV_CLK_SRC 25 -#define NSS_PORT5_TX_DIV_CLK_SRC 26 -#define APSS_AXI_CLK_SRC 27 -#define NSS_CRYPTO_CLK_SRC 28 -#define NSS_PORT1_RX_DIV_CLK_SRC 29 -#define NSS_PORT1_TX_DIV_CLK_SRC 30 -#define NSS_PORT2_RX_DIV_CLK_SRC 31 -#define NSS_PORT2_TX_DIV_CLK_SRC 32 -#define NSS_PORT3_RX_DIV_CLK_SRC 33 -#define NSS_PORT3_TX_DIV_CLK_SRC 34 -#define NSS_PORT4_RX_DIV_CLK_SRC 35 -#define NSS_PORT4_TX_DIV_CLK_SRC 36 -#define NSS_UBI0_CLK_SRC 37 -#define BLSP1_QUP1_I2C_APPS_CLK_SRC 38 -#define BLSP1_QUP1_SPI_APPS_CLK_SRC 39 -#define BLSP1_QUP2_I2C_APPS_CLK_SRC 40 -#define BLSP1_QUP2_SPI_APPS_CLK_SRC 41 -#define BLSP1_QUP3_I2C_APPS_CLK_SRC 42 -#define BLSP1_QUP3_SPI_APPS_CLK_SRC 43 -#define BLSP1_QUP4_I2C_APPS_CLK_SRC 44 -#define BLSP1_QUP4_SPI_APPS_CLK_SRC 45 -#define BLSP1_QUP5_I2C_APPS_CLK_SRC 46 -#define BLSP1_QUP5_SPI_APPS_CLK_SRC 47 -#define BLSP1_QUP6_I2C_APPS_CLK_SRC 48 -#define BLSP1_QUP6_SPI_APPS_CLK_SRC 49 -#define BLSP1_UART1_APPS_CLK_SRC 50 -#define BLSP1_UART2_APPS_CLK_SRC 51 -#define BLSP1_UART3_APPS_CLK_SRC 52 -#define BLSP1_UART4_APPS_CLK_SRC 53 -#define BLSP1_UART5_APPS_CLK_SRC 54 -#define BLSP1_UART6_APPS_CLK_SRC 55 -#define CRYPTO_CLK_SRC 56 -#define NSS_UBI0_DIV_CLK_SRC 57 -#define PCIE0_AUX_CLK_SRC 58 -#define PCIE0_PIPE_CLK_SRC 59 -#define SDCC1_APPS_CLK_SRC 60 -#define USB0_AUX_CLK_SRC 61 -#define USB0_MOCK_UTMI_CLK_SRC 62 -#define USB0_PIPE_CLK_SRC 63 -#define USB1_MOCK_UTMI_CLK_SRC 64 -#define GCC_APSS_AHB_CLK 65 -#define GCC_APSS_AXI_CLK 66 -#define GCC_BLSP1_AHB_CLK 67 -#define GCC_BLSP1_QUP1_I2C_APPS_CLK 68 -#define GCC_BLSP1_QUP1_SPI_APPS_CLK 69 -#define GCC_BLSP1_QUP2_I2C_APPS_CLK 70 -#define GCC_BLSP1_QUP2_SPI_APPS_CLK 71 -#define GCC_BLSP1_QUP3_I2C_APPS_CLK 72 -#define GCC_BLSP1_QUP3_SPI_APPS_CLK 73 -#define GCC_BLSP1_QUP4_I2C_APPS_CLK 74 -#define GCC_BLSP1_QUP4_SPI_APPS_CLK 75 -#define GCC_BLSP1_QUP5_I2C_APPS_CLK 76 -#define GCC_BLSP1_QUP5_SPI_APPS_CLK 77 -#define GCC_BLSP1_QUP6_I2C_APPS_CLK 78 -#define GCC_BLSP1_QUP6_SPI_APPS_CLK 79 -#define GCC_BLSP1_UART1_APPS_CLK 80 -#define GCC_BLSP1_UART2_APPS_CLK 81 -#define GCC_BLSP1_UART3_APPS_CLK 82 -#define GCC_BLSP1_UART4_APPS_CLK 83 -#define GCC_BLSP1_UART5_APPS_CLK 84 -#define GCC_BLSP1_UART6_APPS_CLK 85 -#define GCC_CRYPTO_AHB_CLK 86 -#define GCC_CRYPTO_AXI_CLK 87 -#define GCC_CRYPTO_CLK 88 -#define GCC_XO_CLK 89 -#define GCC_XO_DIV4_CLK 90 -#define GCC_MDIO_AHB_CLK 91 -#define GCC_CRYPTO_PPE_CLK 92 -#define GCC_NSS_CE_APB_CLK 93 -#define GCC_NSS_CE_AXI_CLK 94 -#define GCC_NSS_CFG_CLK 95 -#define GCC_NSS_CRYPTO_CLK 96 -#define GCC_NSS_CSR_CLK 97 -#define GCC_NSS_EDMA_CFG_CLK 98 -#define GCC_NSS_EDMA_CLK 99 -#define GCC_NSS_NOC_CLK 100 -#define GCC_NSS_PORT1_RX_CLK 101 -#define GCC_NSS_PORT1_TX_CLK 102 -#define GCC_NSS_PORT2_RX_CLK 103 -#define GCC_NSS_PORT2_TX_CLK 104 -#define GCC_NSS_PORT3_RX_CLK 105 -#define GCC_NSS_PORT3_TX_CLK 106 -#define GCC_NSS_PORT4_RX_CLK 107 -#define GCC_NSS_PORT4_TX_CLK 108 -#define GCC_NSS_PORT5_RX_CLK 109 -#define GCC_NSS_PORT5_TX_CLK 110 -#define GCC_NSS_PPE_CFG_CLK 111 -#define GCC_NSS_PPE_CLK 112 -#define GCC_NSS_PPE_IPE_CLK 113 -#define GCC_NSS_PTP_REF_CLK 114 -#define GCC_NSSNOC_CE_APB_CLK 115 -#define GCC_NSSNOC_CE_AXI_CLK 116 -#define GCC_NSSNOC_CRYPTO_CLK 117 -#define GCC_NSSNOC_PPE_CFG_CLK 118 -#define GCC_NSSNOC_PPE_CLK 119 -#define GCC_NSSNOC_QOSGEN_REF_CLK 120 -#define GCC_NSSNOC_TIMEOUT_REF_CLK 121 -#define GCC_NSSNOC_UBI0_AHB_CLK 122 -#define GCC_PORT1_MAC_CLK 123 -#define GCC_PORT2_MAC_CLK 124 -#define GCC_PORT3_MAC_CLK 125 -#define GCC_PORT4_MAC_CLK 126 -#define GCC_PORT5_MAC_CLK 127 -#define GCC_UBI0_AHB_CLK 128 -#define GCC_UBI0_AXI_CLK 129 -#define GCC_UBI0_CORE_CLK 130 -#define GCC_PCIE0_AHB_CLK 131 -#define GCC_PCIE0_AUX_CLK 132 -#define GCC_PCIE0_AXI_M_CLK 133 -#define GCC_PCIE0_AXI_S_CLK 134 -#define GCC_PCIE0_PIPE_CLK 135 -#define GCC_PRNG_AHB_CLK 136 -#define GCC_QPIC_AHB_CLK 137 -#define GCC_QPIC_CLK 138 -#define GCC_SDCC1_AHB_CLK 139 -#define GCC_SDCC1_APPS_CLK 140 -#define GCC_UNIPHY0_AHB_CLK 141 -#define GCC_UNIPHY0_PORT1_RX_CLK 142 -#define GCC_UNIPHY0_PORT1_TX_CLK 143 -#define GCC_UNIPHY0_PORT2_RX_CLK 144 -#define GCC_UNIPHY0_PORT2_TX_CLK 145 -#define GCC_UNIPHY0_PORT3_RX_CLK 146 -#define GCC_UNIPHY0_PORT3_TX_CLK 147 -#define GCC_UNIPHY0_PORT4_RX_CLK 148 -#define GCC_UNIPHY0_PORT4_TX_CLK 149 -#define GCC_UNIPHY0_PORT5_RX_CLK 150 -#define GCC_UNIPHY0_PORT5_TX_CLK 151 -#define GCC_UNIPHY0_SYS_CLK 152 -#define GCC_UNIPHY1_AHB_CLK 153 -#define GCC_UNIPHY1_PORT5_RX_CLK 154 -#define GCC_UNIPHY1_PORT5_TX_CLK 155 -#define GCC_UNIPHY1_SYS_CLK 156 -#define GCC_USB0_AUX_CLK 157 -#define GCC_USB0_MASTER_CLK 158 -#define GCC_USB0_MOCK_UTMI_CLK 159 -#define GCC_USB0_PHY_CFG_AHB_CLK 160 -#define GCC_USB0_PIPE_CLK 161 -#define GCC_USB0_SLEEP_CLK 162 -#define GCC_USB1_MASTER_CLK 163 -#define GCC_USB1_MOCK_UTMI_CLK 164 -#define GCC_USB1_PHY_CFG_AHB_CLK 165 -#define GCC_USB1_SLEEP_CLK 166 -#define GP1_CLK_SRC 167 -#define GP2_CLK_SRC 168 -#define GP3_CLK_SRC 169 -#define GCC_GP1_CLK 170 -#define GCC_GP2_CLK 171 -#define GCC_GP3_CLK 172 -#define SYSTEM_NOC_BFDCD_CLK_SRC 173 -#define GCC_NSSNOC_SNOC_CLK 174 -#define GCC_UBI0_NC_AXI_CLK 175 -#define GCC_UBI1_NC_AXI_CLK 176 -#define GPLL0_MAIN 177 -#define UBI32_PLL_MAIN 178 -#define GPLL6_MAIN 179 -#define GPLL4_MAIN 180 -#define GPLL2_MAIN 181 -#define NSS_CRYPTO_PLL_MAIN 182 -#define GCC_CMN_12GPLL_AHB_CLK 183 -#define GCC_CMN_12GPLL_SYS_CLK 184 -#define GCC_SNOC_BUS_TIMEOUT2_AHB_CLK 185 -#define GCC_SYS_NOC_USB0_AXI_CLK 186 -#define GCC_SYS_NOC_PCIE0_AXI_CLK 187 -#define QDSS_TSCTR_CLK_SRC 188 -#define QDSS_AT_CLK_SRC 189 -#define GCC_QDSS_AT_CLK 190 -#define GCC_QDSS_DAP_CLK 191 -#define ADSS_PWM_CLK_SRC 192 -#define GCC_ADSS_PWM_CLK 193 -#define SDCC1_ICE_CORE_CLK_SRC 194 -#define GCC_SDCC1_ICE_CORE_CLK 195 -#define GCC_DCC_CLK 196 -#define PCIE0_RCHNG_CLK_SRC 197 -#define GCC_PCIE0_AXI_S_BRIDGE_CLK 198 -#define PCIE0_RCHNG_CLK 199 -#define UBI32_MEM_NOC_BFDCD_CLK_SRC 200 -#define WCSS_AHB_CLK_SRC 201 -#define Q6_AXI_CLK_SRC 202 -#define GCC_Q6SS_PCLKDBG_CLK 203 -#define GCC_Q6_TSCTR_1TO2_CLK 204 -#define GCC_WCSS_CORE_TBU_CLK 205 -#define GCC_WCSS_AXI_M_CLK 206 -#define GCC_SYS_NOC_WCSS_AHB_CLK 207 -#define GCC_Q6_AXIM_CLK 208 -#define GCC_Q6SS_ATBM_CLK 209 -#define GCC_WCSS_Q6_TBU_CLK 210 -#define GCC_Q6_AXIM2_CLK 211 -#define GCC_Q6_AHB_CLK 212 -#define GCC_Q6_AHB_S_CLK 213 -#define GCC_WCSS_DBG_IFC_APB_CLK 214 -#define GCC_WCSS_DBG_IFC_ATB_CLK 215 -#define GCC_WCSS_DBG_IFC_NTS_CLK 216 -#define GCC_WCSS_DBG_IFC_DAPBUS_CLK 217 -#define GCC_WCSS_DBG_IFC_APB_BDG_CLK 218 -#define GCC_WCSS_DBG_IFC_ATB_BDG_CLK 219 -#define GCC_WCSS_DBG_IFC_NTS_BDG_CLK 220 -#define GCC_WCSS_DBG_IFC_DAPBUS_BDG_CLK 221 -#define GCC_WCSS_ECAHB_CLK 222 -#define GCC_WCSS_ACMT_CLK 223 -#define GCC_WCSS_AHB_S_CLK 224 -#define GCC_RBCPR_WCSS_CLK 225 -#define RBCPR_WCSS_CLK_SRC 226 -#define GCC_RBCPR_WCSS_AHB_CLK 227 -#define GCC_LPASS_CORE_AXIM_CLK 228 -#define GCC_LPASS_SNOC_CFG_CLK 229 -#define GCC_LPASS_Q6_AXIM_CLK 230 -#define GCC_LPASS_Q6_ATBM_AT_CLK 231 -#define GCC_LPASS_Q6_PCLKDBG_CLK 232 -#define GCC_LPASS_Q6SS_TSCTR_1TO2_CLK 233 -#define GCC_LPASS_Q6SS_TRIG_CLK 234 -#define GCC_LPASS_TBU_CLK 235 -#define LPASS_CORE_AXIM_CLK_SRC 236 -#define LPASS_SNOC_CFG_CLK_SRC 237 -#define LPASS_Q6_AXIM_CLK_SRC 238 -#define GCC_PCNOC_LPASS_CLK 239 -#define GCC_UBI0_UTCM_CLK 240 -#define SNOC_NSSNOC_BFDCD_CLK_SRC 241 -#define GCC_SNOC_NSSNOC_CLK 242 -#define GCC_MEM_NOC_Q6_AXI_CLK 243 -#define GCC_MEM_NOC_UBI32_CLK 244 -#define GCC_MEM_NOC_LPASS_CLK 245 -#define GCC_SNOC_LPASS_CFG_CLK 246 -#define GCC_SYS_NOC_QDSS_STM_AXI_CLK 247 -#define GCC_QDSS_STM_CLK 248 -#define GCC_QDSS_TRACECLKIN_CLK 249 -#define QDSS_STM_CLK_SRC 250 -#define QDSS_TRACECLKIN_CLK_SRC 251 -#define GCC_NSSNOC_ATB_CLK 252 -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-ipq806x.h b/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-ipq806x.h deleted file mode 100644 index 7deec14a6de..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-ipq806x.h +++ /dev/null @@ -1,287 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2014, The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_CLK_GCC_IPQ806X_H -#define _DT_BINDINGS_CLK_GCC_IPQ806X_H - -#define AFAB_CLK_SRC 0 -#define QDSS_STM_CLK 1 -#define SCSS_A_CLK 2 -#define SCSS_H_CLK 3 -#define AFAB_CORE_CLK 4 -#define SCSS_XO_SRC_CLK 5 -#define AFAB_EBI1_CH0_A_CLK 6 -#define AFAB_EBI1_CH1_A_CLK 7 -#define AFAB_AXI_S0_FCLK 8 -#define AFAB_AXI_S1_FCLK 9 -#define AFAB_AXI_S2_FCLK 10 -#define AFAB_AXI_S3_FCLK 11 -#define AFAB_AXI_S4_FCLK 12 -#define SFAB_CORE_CLK 13 -#define SFAB_AXI_S0_FCLK 14 -#define SFAB_AXI_S1_FCLK 15 -#define SFAB_AXI_S2_FCLK 16 -#define SFAB_AXI_S3_FCLK 17 -#define SFAB_AXI_S4_FCLK 18 -#define SFAB_AXI_S5_FCLK 19 -#define SFAB_AHB_S0_FCLK 20 -#define SFAB_AHB_S1_FCLK 21 -#define SFAB_AHB_S2_FCLK 22 -#define SFAB_AHB_S3_FCLK 23 -#define SFAB_AHB_S4_FCLK 24 -#define SFAB_AHB_S5_FCLK 25 -#define SFAB_AHB_S6_FCLK 26 -#define SFAB_AHB_S7_FCLK 27 -#define QDSS_AT_CLK_SRC 28 -#define QDSS_AT_CLK 29 -#define QDSS_TRACECLKIN_CLK_SRC 30 -#define QDSS_TRACECLKIN_CLK 31 -#define QDSS_TSCTR_CLK_SRC 32 -#define QDSS_TSCTR_CLK 33 -#define SFAB_ADM0_M0_A_CLK 34 -#define SFAB_ADM0_M1_A_CLK 35 -#define SFAB_ADM0_M2_H_CLK 36 -#define ADM0_CLK 37 -#define ADM0_PBUS_CLK 38 -#define IMEM0_A_CLK 39 -#define QDSS_H_CLK 40 -#define PCIE_A_CLK 41 -#define PCIE_AUX_CLK 42 -#define PCIE_H_CLK 43 -#define PCIE_PHY_CLK 44 -#define SFAB_CLK_SRC 45 -#define SFAB_LPASS_Q6_A_CLK 46 -#define SFAB_AFAB_M_A_CLK 47 -#define AFAB_SFAB_M0_A_CLK 48 -#define AFAB_SFAB_M1_A_CLK 49 -#define SFAB_SATA_S_H_CLK 50 -#define DFAB_CLK_SRC 51 -#define DFAB_CLK 52 -#define SFAB_DFAB_M_A_CLK 53 -#define DFAB_SFAB_M_A_CLK 54 -#define DFAB_SWAY0_H_CLK 55 -#define DFAB_SWAY1_H_CLK 56 -#define DFAB_ARB0_H_CLK 57 -#define DFAB_ARB1_H_CLK 58 -#define PPSS_H_CLK 59 -#define PPSS_PROC_CLK 60 -#define PPSS_TIMER0_CLK 61 -#define PPSS_TIMER1_CLK 62 -#define PMEM_A_CLK 63 -#define DMA_BAM_H_CLK 64 -#define SIC_H_CLK 65 -#define SPS_TIC_H_CLK 66 -#define CFPB_2X_CLK_SRC 67 -#define CFPB_CLK 68 -#define CFPB0_H_CLK 69 -#define CFPB1_H_CLK 70 -#define CFPB2_H_CLK 71 -#define SFAB_CFPB_M_H_CLK 72 -#define CFPB_MASTER_H_CLK 73 -#define SFAB_CFPB_S_H_CLK 74 -#define CFPB_SPLITTER_H_CLK 75 -#define TSIF_H_CLK 76 -#define TSIF_INACTIVITY_TIMERS_CLK 77 -#define TSIF_REF_SRC 78 -#define TSIF_REF_CLK 79 -#define CE1_H_CLK 80 -#define CE1_CORE_CLK 81 -#define CE1_SLEEP_CLK 82 -#define CE2_H_CLK 83 -#define CE2_CORE_CLK 84 -#define SFPB_H_CLK_SRC 85 -#define SFPB_H_CLK 86 -#define SFAB_SFPB_M_H_CLK 87 -#define SFAB_SFPB_S_H_CLK 88 -#define RPM_PROC_CLK 89 -#define RPM_BUS_H_CLK 90 -#define RPM_SLEEP_CLK 91 -#define RPM_TIMER_CLK 92 -#define RPM_MSG_RAM_H_CLK 93 -#define PMIC_ARB0_H_CLK 94 -#define PMIC_ARB1_H_CLK 95 -#define PMIC_SSBI2_SRC 96 -#define PMIC_SSBI2_CLK 97 -#define SDC1_H_CLK 98 -#define SDC2_H_CLK 99 -#define SDC3_H_CLK 100 -#define SDC4_H_CLK 101 -#define SDC1_SRC 102 -#define SDC1_CLK 103 -#define SDC2_SRC 104 -#define SDC2_CLK 105 -#define SDC3_SRC 106 -#define SDC3_CLK 107 -#define SDC4_SRC 108 -#define SDC4_CLK 109 -#define USB_HS1_H_CLK 110 -#define USB_HS1_XCVR_SRC 111 -#define USB_HS1_XCVR_CLK 112 -#define USB_HSIC_H_CLK 113 -#define USB_HSIC_XCVR_SRC 114 -#define USB_HSIC_XCVR_CLK 115 -#define USB_HSIC_SYSTEM_CLK_SRC 116 -#define USB_HSIC_SYSTEM_CLK 117 -#define CFPB0_C0_H_CLK 118 -#define CFPB0_D0_H_CLK 119 -#define CFPB0_C1_H_CLK 120 -#define CFPB0_D1_H_CLK 121 -#define USB_FS1_H_CLK 122 -#define USB_FS1_XCVR_SRC 123 -#define USB_FS1_XCVR_CLK 124 -#define USB_FS1_SYSTEM_CLK 125 -#define GSBI_COMMON_SIM_SRC 126 -#define GSBI1_H_CLK 127 -#define GSBI2_H_CLK 128 -#define GSBI3_H_CLK 129 -#define GSBI4_H_CLK 130 -#define GSBI5_H_CLK 131 -#define GSBI6_H_CLK 132 -#define GSBI7_H_CLK 133 -#define GSBI1_QUP_SRC 134 -#define GSBI1_QUP_CLK 135 -#define GSBI2_QUP_SRC 136 -#define GSBI2_QUP_CLK 137 -#define GSBI3_QUP_SRC 138 -#define GSBI3_QUP_CLK 139 -#define GSBI4_QUP_SRC 140 -#define GSBI4_QUP_CLK 141 -#define GSBI5_QUP_SRC 142 -#define GSBI5_QUP_CLK 143 -#define GSBI6_QUP_SRC 144 -#define GSBI6_QUP_CLK 145 -#define GSBI7_QUP_SRC 146 -#define GSBI7_QUP_CLK 147 -#define GSBI1_UART_SRC 148 -#define GSBI1_UART_CLK 149 -#define GSBI2_UART_SRC 150 -#define GSBI2_UART_CLK 151 -#define GSBI3_UART_SRC 152 -#define GSBI3_UART_CLK 153 -#define GSBI4_UART_SRC 154 -#define GSBI4_UART_CLK 155 -#define GSBI5_UART_SRC 156 -#define GSBI5_UART_CLK 157 -#define GSBI6_UART_SRC 158 -#define GSBI6_UART_CLK 159 -#define GSBI7_UART_SRC 160 -#define GSBI7_UART_CLK 161 -#define GSBI1_SIM_CLK 162 -#define GSBI2_SIM_CLK 163 -#define GSBI3_SIM_CLK 164 -#define GSBI4_SIM_CLK 165 -#define GSBI5_SIM_CLK 166 -#define GSBI6_SIM_CLK 167 -#define GSBI7_SIM_CLK 168 -#define USB_HSIC_HSIC_CLK_SRC 169 -#define USB_HSIC_HSIC_CLK 170 -#define USB_HSIC_HSIO_CAL_CLK 171 -#define SPDM_CFG_H_CLK 172 -#define SPDM_MSTR_H_CLK 173 -#define SPDM_FF_CLK_SRC 174 -#define SPDM_FF_CLK 175 -#define SEC_CTRL_CLK 176 -#define SEC_CTRL_ACC_CLK_SRC 177 -#define SEC_CTRL_ACC_CLK 178 -#define TLMM_H_CLK 179 -#define TLMM_CLK 180 -#define SATA_H_CLK 181 -#define SATA_CLK_SRC 182 -#define SATA_RXOOB_CLK 183 -#define SATA_PMALIVE_CLK 184 -#define SATA_PHY_REF_CLK 185 -#define SATA_A_CLK 186 -#define SATA_PHY_CFG_CLK 187 -#define TSSC_CLK_SRC 188 -#define TSSC_CLK 189 -#define PDM_SRC 190 -#define PDM_CLK 191 -#define GP0_SRC 192 -#define GP0_CLK 193 -#define GP1_SRC 194 -#define GP1_CLK 195 -#define GP2_SRC 196 -#define GP2_CLK 197 -#define MPM_CLK 198 -#define EBI1_CLK_SRC 199 -#define EBI1_CH0_CLK 200 -#define EBI1_CH1_CLK 201 -#define EBI1_2X_CLK 202 -#define EBI1_CH0_DQ_CLK 203 -#define EBI1_CH1_DQ_CLK 204 -#define EBI1_CH0_CA_CLK 205 -#define EBI1_CH1_CA_CLK 206 -#define EBI1_XO_CLK 207 -#define SFAB_SMPSS_S_H_CLK 208 -#define PRNG_SRC 209 -#define PRNG_CLK 210 -#define PXO_SRC 211 -#define SPDM_CY_PORT0_CLK 212 -#define SPDM_CY_PORT1_CLK 213 -#define SPDM_CY_PORT2_CLK 214 -#define SPDM_CY_PORT3_CLK 215 -#define SPDM_CY_PORT4_CLK 216 -#define SPDM_CY_PORT5_CLK 217 -#define SPDM_CY_PORT6_CLK 218 -#define SPDM_CY_PORT7_CLK 219 -#define PLL0 220 -#define PLL0_VOTE 221 -#define PLL3 222 -#define PLL3_VOTE 223 -#define PLL4_VOTE 225 -#define PLL8 226 -#define PLL8_VOTE 227 -#define PLL9 228 -#define PLL10 229 -#define PLL11 230 -#define PLL12 231 -#define PLL14 232 -#define PLL14_VOTE 233 -#define PLL18 234 -#define CE5_SRC 235 -#define CE5_H_CLK 236 -#define CE5_CORE_CLK 237 -#define CE3_SLEEP_CLK 238 -#define SFAB_AHB_S8_FCLK 239 -#define SPDM_CY_PORT8_CLK 246 -#define PCIE_ALT_REF_SRC 247 -#define PCIE_ALT_REF_CLK 248 -#define PCIE_1_A_CLK 249 -#define PCIE_1_AUX_CLK 250 -#define PCIE_1_H_CLK 251 -#define PCIE_1_PHY_CLK 252 -#define PCIE_1_ALT_REF_SRC 253 -#define PCIE_1_ALT_REF_CLK 254 -#define PCIE_2_A_CLK 255 -#define PCIE_2_AUX_CLK 256 -#define PCIE_2_H_CLK 257 -#define PCIE_2_PHY_CLK 258 -#define PCIE_2_ALT_REF_SRC 259 -#define PCIE_2_ALT_REF_CLK 260 -#define EBI2_CLK 261 -#define USB30_SLEEP_CLK 262 -#define USB30_UTMI_SRC 263 -#define USB30_0_UTMI_CLK 264 -#define USB30_1_UTMI_CLK 265 -#define USB30_MASTER_SRC 266 -#define USB30_0_MASTER_CLK 267 -#define USB30_1_MASTER_CLK 268 -#define GMAC_CORE1_CLK_SRC 269 -#define GMAC_CORE2_CLK_SRC 270 -#define GMAC_CORE3_CLK_SRC 271 -#define GMAC_CORE4_CLK_SRC 272 -#define GMAC_CORE1_CLK 273 -#define GMAC_CORE2_CLK 274 -#define GMAC_CORE3_CLK 275 -#define GMAC_CORE4_CLK 276 -#define UBI32_CORE1_CLK_SRC 277 -#define UBI32_CORE2_CLK_SRC 278 -#define UBI32_CORE1_CLK 279 -#define UBI32_CORE2_CLK 280 -#define EBI2_AON_CLK 281 -#define NSSTCM_CLK_SRC 282 -#define NSSTCM_CLK 283 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-ipq8074.h b/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-ipq8074.h deleted file mode 100644 index 4de4811a354..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-ipq8074.h +++ /dev/null @@ -1,366 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_CLOCK_IPQ_GCC_8074_H -#define _DT_BINDINGS_CLOCK_IPQ_GCC_8074_H - -#define GPLL0 0 -#define GPLL0_MAIN 1 -#define GCC_SLEEP_CLK_SRC 2 -#define BLSP1_QUP1_I2C_APPS_CLK_SRC 3 -#define BLSP1_QUP1_SPI_APPS_CLK_SRC 4 -#define BLSP1_QUP2_I2C_APPS_CLK_SRC 5 -#define BLSP1_QUP2_SPI_APPS_CLK_SRC 6 -#define BLSP1_QUP3_I2C_APPS_CLK_SRC 7 -#define BLSP1_QUP3_SPI_APPS_CLK_SRC 8 -#define BLSP1_QUP4_I2C_APPS_CLK_SRC 9 -#define BLSP1_QUP4_SPI_APPS_CLK_SRC 10 -#define BLSP1_QUP5_I2C_APPS_CLK_SRC 11 -#define BLSP1_QUP5_SPI_APPS_CLK_SRC 12 -#define BLSP1_QUP6_I2C_APPS_CLK_SRC 13 -#define BLSP1_QUP6_SPI_APPS_CLK_SRC 14 -#define BLSP1_UART1_APPS_CLK_SRC 15 -#define BLSP1_UART2_APPS_CLK_SRC 16 -#define BLSP1_UART3_APPS_CLK_SRC 17 -#define BLSP1_UART4_APPS_CLK_SRC 18 -#define BLSP1_UART5_APPS_CLK_SRC 19 -#define BLSP1_UART6_APPS_CLK_SRC 20 -#define GCC_BLSP1_AHB_CLK 21 -#define GCC_BLSP1_QUP1_I2C_APPS_CLK 22 -#define GCC_BLSP1_QUP1_SPI_APPS_CLK 23 -#define GCC_BLSP1_QUP2_I2C_APPS_CLK 24 -#define GCC_BLSP1_QUP2_SPI_APPS_CLK 25 -#define GCC_BLSP1_QUP3_I2C_APPS_CLK 26 -#define GCC_BLSP1_QUP3_SPI_APPS_CLK 27 -#define GCC_BLSP1_QUP4_I2C_APPS_CLK 28 -#define GCC_BLSP1_QUP4_SPI_APPS_CLK 29 -#define GCC_BLSP1_QUP5_I2C_APPS_CLK 30 -#define GCC_BLSP1_QUP5_SPI_APPS_CLK 31 -#define GCC_BLSP1_QUP6_I2C_APPS_CLK 32 -#define GCC_BLSP1_QUP6_SPI_APPS_CLK 33 -#define GCC_BLSP1_UART1_APPS_CLK 34 -#define GCC_BLSP1_UART2_APPS_CLK 35 -#define GCC_BLSP1_UART3_APPS_CLK 36 -#define GCC_BLSP1_UART4_APPS_CLK 37 -#define GCC_BLSP1_UART5_APPS_CLK 38 -#define GCC_BLSP1_UART6_APPS_CLK 39 -#define GCC_PRNG_AHB_CLK 40 -#define GCC_QPIC_AHB_CLK 41 -#define GCC_QPIC_CLK 42 -#define PCNOC_BFDCD_CLK_SRC 43 -#define GPLL2_MAIN 44 -#define GPLL2 45 -#define GPLL4_MAIN 46 -#define GPLL4 47 -#define GPLL6_MAIN 48 -#define GPLL6 49 -#define UBI32_PLL_MAIN 50 -#define UBI32_PLL 51 -#define NSS_CRYPTO_PLL_MAIN 52 -#define NSS_CRYPTO_PLL 53 -#define PCIE0_AXI_CLK_SRC 54 -#define PCIE0_AUX_CLK_SRC 55 -#define PCIE0_PIPE_CLK_SRC 56 -#define PCIE1_AXI_CLK_SRC 57 -#define PCIE1_AUX_CLK_SRC 58 -#define PCIE1_PIPE_CLK_SRC 59 -#define SDCC1_APPS_CLK_SRC 60 -#define SDCC1_ICE_CORE_CLK_SRC 61 -#define SDCC2_APPS_CLK_SRC 62 -#define USB0_MASTER_CLK_SRC 63 -#define USB0_AUX_CLK_SRC 64 -#define USB0_MOCK_UTMI_CLK_SRC 65 -#define USB0_PIPE_CLK_SRC 66 -#define USB1_MASTER_CLK_SRC 67 -#define USB1_AUX_CLK_SRC 68 -#define USB1_MOCK_UTMI_CLK_SRC 69 -#define USB1_PIPE_CLK_SRC 70 -#define GCC_XO_CLK_SRC 71 -#define SYSTEM_NOC_BFDCD_CLK_SRC 72 -#define NSS_CE_CLK_SRC 73 -#define NSS_NOC_BFDCD_CLK_SRC 74 -#define NSS_CRYPTO_CLK_SRC 75 -#define NSS_UBI0_CLK_SRC 76 -#define NSS_UBI0_DIV_CLK_SRC 77 -#define NSS_UBI1_CLK_SRC 78 -#define NSS_UBI1_DIV_CLK_SRC 79 -#define UBI_MPT_CLK_SRC 80 -#define NSS_IMEM_CLK_SRC 81 -#define NSS_PPE_CLK_SRC 82 -#define NSS_PORT1_RX_CLK_SRC 83 -#define NSS_PORT1_RX_DIV_CLK_SRC 84 -#define NSS_PORT1_TX_CLK_SRC 85 -#define NSS_PORT1_TX_DIV_CLK_SRC 86 -#define NSS_PORT2_RX_CLK_SRC 87 -#define NSS_PORT2_RX_DIV_CLK_SRC 88 -#define NSS_PORT2_TX_CLK_SRC 89 -#define NSS_PORT2_TX_DIV_CLK_SRC 90 -#define NSS_PORT3_RX_CLK_SRC 91 -#define NSS_PORT3_RX_DIV_CLK_SRC 92 -#define NSS_PORT3_TX_CLK_SRC 93 -#define NSS_PORT3_TX_DIV_CLK_SRC 94 -#define NSS_PORT4_RX_CLK_SRC 95 -#define NSS_PORT4_RX_DIV_CLK_SRC 96 -#define NSS_PORT4_TX_CLK_SRC 97 -#define NSS_PORT4_TX_DIV_CLK_SRC 98 -#define NSS_PORT5_RX_CLK_SRC 99 -#define NSS_PORT5_RX_DIV_CLK_SRC 100 -#define NSS_PORT5_TX_CLK_SRC 101 -#define NSS_PORT5_TX_DIV_CLK_SRC 102 -#define NSS_PORT6_RX_CLK_SRC 103 -#define NSS_PORT6_RX_DIV_CLK_SRC 104 -#define NSS_PORT6_TX_CLK_SRC 105 -#define NSS_PORT6_TX_DIV_CLK_SRC 106 -#define CRYPTO_CLK_SRC 107 -#define GP1_CLK_SRC 108 -#define GP2_CLK_SRC 109 -#define GP3_CLK_SRC 110 -#define GCC_PCIE0_AHB_CLK 111 -#define GCC_PCIE0_AUX_CLK 112 -#define GCC_PCIE0_AXI_M_CLK 113 -#define GCC_PCIE0_AXI_S_CLK 114 -#define GCC_PCIE0_PIPE_CLK 115 -#define GCC_SYS_NOC_PCIE0_AXI_CLK 116 -#define GCC_PCIE1_AHB_CLK 117 -#define GCC_PCIE1_AUX_CLK 118 -#define GCC_PCIE1_AXI_M_CLK 119 -#define GCC_PCIE1_AXI_S_CLK 120 -#define GCC_PCIE1_PIPE_CLK 121 -#define GCC_SYS_NOC_PCIE1_AXI_CLK 122 -#define GCC_USB0_AUX_CLK 123 -#define GCC_SYS_NOC_USB0_AXI_CLK 124 -#define GCC_USB0_MASTER_CLK 125 -#define GCC_USB0_MOCK_UTMI_CLK 126 -#define GCC_USB0_PHY_CFG_AHB_CLK 127 -#define GCC_USB0_PIPE_CLK 128 -#define GCC_USB0_SLEEP_CLK 129 -#define GCC_USB1_AUX_CLK 130 -#define GCC_SYS_NOC_USB1_AXI_CLK 131 -#define GCC_USB1_MASTER_CLK 132 -#define GCC_USB1_MOCK_UTMI_CLK 133 -#define GCC_USB1_PHY_CFG_AHB_CLK 134 -#define GCC_USB1_PIPE_CLK 135 -#define GCC_USB1_SLEEP_CLK 136 -#define GCC_SDCC1_AHB_CLK 137 -#define GCC_SDCC1_APPS_CLK 138 -#define GCC_SDCC1_ICE_CORE_CLK 139 -#define GCC_SDCC2_AHB_CLK 140 -#define GCC_SDCC2_APPS_CLK 141 -#define GCC_MEM_NOC_NSS_AXI_CLK 142 -#define GCC_NSS_CE_APB_CLK 143 -#define GCC_NSS_CE_AXI_CLK 144 -#define GCC_NSS_CFG_CLK 145 -#define GCC_NSS_CRYPTO_CLK 146 -#define GCC_NSS_CSR_CLK 147 -#define GCC_NSS_EDMA_CFG_CLK 148 -#define GCC_NSS_EDMA_CLK 149 -#define GCC_NSS_IMEM_CLK 150 -#define GCC_NSS_NOC_CLK 151 -#define GCC_NSS_PPE_BTQ_CLK 152 -#define GCC_NSS_PPE_CFG_CLK 153 -#define GCC_NSS_PPE_CLK 154 -#define GCC_NSS_PPE_IPE_CLK 155 -#define GCC_NSS_PTP_REF_CLK 156 -#define GCC_NSSNOC_CE_APB_CLK 157 -#define GCC_NSSNOC_CE_AXI_CLK 158 -#define GCC_NSSNOC_CRYPTO_CLK 159 -#define GCC_NSSNOC_PPE_CFG_CLK 160 -#define GCC_NSSNOC_PPE_CLK 161 -#define GCC_NSSNOC_QOSGEN_REF_CLK 162 -#define GCC_NSSNOC_SNOC_CLK 163 -#define GCC_NSSNOC_TIMEOUT_REF_CLK 164 -#define GCC_NSSNOC_UBI0_AHB_CLK 165 -#define GCC_NSSNOC_UBI1_AHB_CLK 166 -#define GCC_UBI0_AHB_CLK 167 -#define GCC_UBI0_AXI_CLK 168 -#define GCC_UBI0_NC_AXI_CLK 169 -#define GCC_UBI0_CORE_CLK 170 -#define GCC_UBI0_MPT_CLK 171 -#define GCC_UBI1_AHB_CLK 172 -#define GCC_UBI1_AXI_CLK 173 -#define GCC_UBI1_NC_AXI_CLK 174 -#define GCC_UBI1_CORE_CLK 175 -#define GCC_UBI1_MPT_CLK 176 -#define GCC_CMN_12GPLL_AHB_CLK 177 -#define GCC_CMN_12GPLL_SYS_CLK 178 -#define GCC_MDIO_AHB_CLK 179 -#define GCC_UNIPHY0_AHB_CLK 180 -#define GCC_UNIPHY0_SYS_CLK 181 -#define GCC_UNIPHY1_AHB_CLK 182 -#define GCC_UNIPHY1_SYS_CLK 183 -#define GCC_UNIPHY2_AHB_CLK 184 -#define GCC_UNIPHY2_SYS_CLK 185 -#define GCC_NSS_PORT1_RX_CLK 186 -#define GCC_NSS_PORT1_TX_CLK 187 -#define GCC_NSS_PORT2_RX_CLK 188 -#define GCC_NSS_PORT2_TX_CLK 189 -#define GCC_NSS_PORT3_RX_CLK 190 -#define GCC_NSS_PORT3_TX_CLK 191 -#define GCC_NSS_PORT4_RX_CLK 192 -#define GCC_NSS_PORT4_TX_CLK 193 -#define GCC_NSS_PORT5_RX_CLK 194 -#define GCC_NSS_PORT5_TX_CLK 195 -#define GCC_NSS_PORT6_RX_CLK 196 -#define GCC_NSS_PORT6_TX_CLK 197 -#define GCC_PORT1_MAC_CLK 198 -#define GCC_PORT2_MAC_CLK 199 -#define GCC_PORT3_MAC_CLK 200 -#define GCC_PORT4_MAC_CLK 201 -#define GCC_PORT5_MAC_CLK 202 -#define GCC_PORT6_MAC_CLK 203 -#define GCC_UNIPHY0_PORT1_RX_CLK 204 -#define GCC_UNIPHY0_PORT1_TX_CLK 205 -#define GCC_UNIPHY0_PORT2_RX_CLK 206 -#define GCC_UNIPHY0_PORT2_TX_CLK 207 -#define GCC_UNIPHY0_PORT3_RX_CLK 208 -#define GCC_UNIPHY0_PORT3_TX_CLK 209 -#define GCC_UNIPHY0_PORT4_RX_CLK 210 -#define GCC_UNIPHY0_PORT4_TX_CLK 211 -#define GCC_UNIPHY0_PORT5_RX_CLK 212 -#define GCC_UNIPHY0_PORT5_TX_CLK 213 -#define GCC_UNIPHY1_PORT5_RX_CLK 214 -#define GCC_UNIPHY1_PORT5_TX_CLK 215 -#define GCC_UNIPHY2_PORT6_RX_CLK 216 -#define GCC_UNIPHY2_PORT6_TX_CLK 217 -#define GCC_CRYPTO_AHB_CLK 218 -#define GCC_CRYPTO_AXI_CLK 219 -#define GCC_CRYPTO_CLK 220 -#define GCC_GP1_CLK 221 -#define GCC_GP2_CLK 222 -#define GCC_GP3_CLK 223 - -#define GCC_BLSP1_BCR 0 -#define GCC_BLSP1_QUP1_BCR 1 -#define GCC_BLSP1_UART1_BCR 2 -#define GCC_BLSP1_QUP2_BCR 3 -#define GCC_BLSP1_UART2_BCR 4 -#define GCC_BLSP1_QUP3_BCR 5 -#define GCC_BLSP1_UART3_BCR 6 -#define GCC_BLSP1_QUP4_BCR 7 -#define GCC_BLSP1_UART4_BCR 8 -#define GCC_BLSP1_QUP5_BCR 9 -#define GCC_BLSP1_UART5_BCR 10 -#define GCC_BLSP1_QUP6_BCR 11 -#define GCC_BLSP1_UART6_BCR 12 -#define GCC_IMEM_BCR 13 -#define GCC_SMMU_BCR 14 -#define GCC_APSS_TCU_BCR 15 -#define GCC_SMMU_XPU_BCR 16 -#define GCC_PCNOC_TBU_BCR 17 -#define GCC_SMMU_CFG_BCR 18 -#define GCC_PRNG_BCR 19 -#define GCC_BOOT_ROM_BCR 20 -#define GCC_CRYPTO_BCR 21 -#define GCC_WCSS_BCR 22 -#define GCC_WCSS_Q6_BCR 23 -#define GCC_NSS_BCR 24 -#define GCC_SEC_CTRL_BCR 25 -#define GCC_ADSS_BCR 26 -#define GCC_DDRSS_BCR 27 -#define GCC_SYSTEM_NOC_BCR 28 -#define GCC_PCNOC_BCR 29 -#define GCC_TCSR_BCR 30 -#define GCC_QDSS_BCR 31 -#define GCC_DCD_BCR 32 -#define GCC_MSG_RAM_BCR 33 -#define GCC_MPM_BCR 34 -#define GCC_SPMI_BCR 35 -#define GCC_SPDM_BCR 36 -#define GCC_RBCPR_BCR 37 -#define GCC_RBCPR_MX_BCR 38 -#define GCC_TLMM_BCR 39 -#define GCC_RBCPR_WCSS_BCR 40 -#define GCC_USB0_PHY_BCR 41 -#define GCC_USB3PHY_0_PHY_BCR 42 -#define GCC_USB0_BCR 43 -#define GCC_USB1_PHY_BCR 44 -#define GCC_USB3PHY_1_PHY_BCR 45 -#define GCC_USB1_BCR 46 -#define GCC_QUSB2_0_PHY_BCR 47 -#define GCC_QUSB2_1_PHY_BCR 48 -#define GCC_SDCC1_BCR 49 -#define GCC_SDCC2_BCR 50 -#define GCC_SNOC_BUS_TIMEOUT0_BCR 51 -#define GCC_SNOC_BUS_TIMEOUT2_BCR 52 -#define GCC_SNOC_BUS_TIMEOUT3_BCR 53 -#define GCC_PCNOC_BUS_TIMEOUT0_BCR 54 -#define GCC_PCNOC_BUS_TIMEOUT1_BCR 55 -#define GCC_PCNOC_BUS_TIMEOUT2_BCR 56 -#define GCC_PCNOC_BUS_TIMEOUT3_BCR 57 -#define GCC_PCNOC_BUS_TIMEOUT4_BCR 58 -#define GCC_PCNOC_BUS_TIMEOUT5_BCR 59 -#define GCC_PCNOC_BUS_TIMEOUT6_BCR 60 -#define GCC_PCNOC_BUS_TIMEOUT7_BCR 61 -#define GCC_PCNOC_BUS_TIMEOUT8_BCR 62 -#define GCC_PCNOC_BUS_TIMEOUT9_BCR 63 -#define GCC_UNIPHY0_BCR 64 -#define GCC_UNIPHY1_BCR 65 -#define GCC_UNIPHY2_BCR 66 -#define GCC_CMN_12GPLL_BCR 67 -#define GCC_QPIC_BCR 68 -#define GCC_MDIO_BCR 69 -#define GCC_PCIE1_TBU_BCR 70 -#define GCC_WCSS_CORE_TBU_BCR 71 -#define GCC_WCSS_Q6_TBU_BCR 72 -#define GCC_USB0_TBU_BCR 73 -#define GCC_USB1_TBU_BCR 74 -#define GCC_PCIE0_TBU_BCR 75 -#define GCC_NSS_NOC_TBU_BCR 76 -#define GCC_PCIE0_BCR 77 -#define GCC_PCIE0_PHY_BCR 78 -#define GCC_PCIE0PHY_PHY_BCR 79 -#define GCC_PCIE0_LINK_DOWN_BCR 80 -#define GCC_PCIE1_BCR 81 -#define GCC_PCIE1_PHY_BCR 82 -#define GCC_PCIE1PHY_PHY_BCR 83 -#define GCC_PCIE1_LINK_DOWN_BCR 84 -#define GCC_DCC_BCR 85 -#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR 86 -#define GCC_APC1_VOLTAGE_DROOP_DETECTOR_BCR 87 -#define GCC_SMMU_CATS_BCR 88 -#define GCC_UBI0_AXI_ARES 89 -#define GCC_UBI0_AHB_ARES 90 -#define GCC_UBI0_NC_AXI_ARES 91 -#define GCC_UBI0_DBG_ARES 92 -#define GCC_UBI0_CORE_CLAMP_ENABLE 93 -#define GCC_UBI0_CLKRST_CLAMP_ENABLE 94 -#define GCC_UBI1_AXI_ARES 95 -#define GCC_UBI1_AHB_ARES 96 -#define GCC_UBI1_NC_AXI_ARES 97 -#define GCC_UBI1_DBG_ARES 98 -#define GCC_UBI1_CORE_CLAMP_ENABLE 99 -#define GCC_UBI1_CLKRST_CLAMP_ENABLE 100 -#define GCC_NSS_CFG_ARES 101 -#define GCC_NSS_IMEM_ARES 102 -#define GCC_NSS_NOC_ARES 103 -#define GCC_NSS_CRYPTO_ARES 104 -#define GCC_NSS_CSR_ARES 105 -#define GCC_NSS_CE_APB_ARES 106 -#define GCC_NSS_CE_AXI_ARES 107 -#define GCC_NSSNOC_CE_APB_ARES 108 -#define GCC_NSSNOC_CE_AXI_ARES 109 -#define GCC_NSSNOC_UBI0_AHB_ARES 110 -#define GCC_NSSNOC_UBI1_AHB_ARES 111 -#define GCC_NSSNOC_SNOC_ARES 112 -#define GCC_NSSNOC_CRYPTO_ARES 113 -#define GCC_NSSNOC_ATB_ARES 114 -#define GCC_NSSNOC_QOSGEN_REF_ARES 115 -#define GCC_NSSNOC_TIMEOUT_REF_ARES 116 -#define GCC_PCIE0_PIPE_ARES 117 -#define GCC_PCIE0_SLEEP_ARES 118 -#define GCC_PCIE0_CORE_STICKY_ARES 119 -#define GCC_PCIE0_AXI_MASTER_ARES 120 -#define GCC_PCIE0_AXI_SLAVE_ARES 121 -#define GCC_PCIE0_AHB_ARES 122 -#define GCC_PCIE0_AXI_MASTER_STICKY_ARES 123 -#define GCC_PCIE1_PIPE_ARES 124 -#define GCC_PCIE1_SLEEP_ARES 125 -#define GCC_PCIE1_CORE_STICKY_ARES 126 -#define GCC_PCIE1_AXI_MASTER_ARES 127 -#define GCC_PCIE1_AXI_SLAVE_ARES 128 -#define GCC_PCIE1_AHB_ARES 129 -#define GCC_PCIE1_AXI_MASTER_STICKY_ARES 130 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-mdm9615.h b/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-mdm9615.h deleted file mode 100644 index 9e4c34823da..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-mdm9615.h +++ /dev/null @@ -1,321 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2013, The Linux Foundation. All rights reserved. - * Copyright (c) BayLibre, SAS. - * Author : Neil Armstrong - */ - -#ifndef _DT_BINDINGS_CLK_MDM_GCC_9615_H -#define _DT_BINDINGS_CLK_MDM_GCC_9615_H - -#define AFAB_CLK_SRC 0 -#define AFAB_CORE_CLK 1 -#define SFAB_MSS_Q6_SW_A_CLK 2 -#define SFAB_MSS_Q6_FW_A_CLK 3 -#define QDSS_STM_CLK 4 -#define SCSS_A_CLK 5 -#define SCSS_H_CLK 6 -#define SCSS_XO_SRC_CLK 7 -#define AFAB_EBI1_CH0_A_CLK 8 -#define AFAB_EBI1_CH1_A_CLK 9 -#define AFAB_AXI_S0_FCLK 10 -#define AFAB_AXI_S1_FCLK 11 -#define AFAB_AXI_S2_FCLK 12 -#define AFAB_AXI_S3_FCLK 13 -#define AFAB_AXI_S4_FCLK 14 -#define SFAB_CORE_CLK 15 -#define SFAB_AXI_S0_FCLK 16 -#define SFAB_AXI_S1_FCLK 17 -#define SFAB_AXI_S2_FCLK 18 -#define SFAB_AXI_S3_FCLK 19 -#define SFAB_AXI_S4_FCLK 20 -#define SFAB_AHB_S0_FCLK 21 -#define SFAB_AHB_S1_FCLK 22 -#define SFAB_AHB_S2_FCLK 23 -#define SFAB_AHB_S3_FCLK 24 -#define SFAB_AHB_S4_FCLK 25 -#define SFAB_AHB_S5_FCLK 26 -#define SFAB_AHB_S6_FCLK 27 -#define SFAB_AHB_S7_FCLK 28 -#define QDSS_AT_CLK_SRC 29 -#define QDSS_AT_CLK 30 -#define QDSS_TRACECLKIN_CLK_SRC 31 -#define QDSS_TRACECLKIN_CLK 32 -#define QDSS_TSCTR_CLK_SRC 33 -#define QDSS_TSCTR_CLK 34 -#define SFAB_ADM0_M0_A_CLK 35 -#define SFAB_ADM0_M1_A_CLK 36 -#define SFAB_ADM0_M2_H_CLK 37 -#define ADM0_CLK 38 -#define ADM0_PBUS_CLK 39 -#define MSS_XPU_CLK 40 -#define IMEM0_A_CLK 41 -#define QDSS_H_CLK 42 -#define PCIE_A_CLK 43 -#define PCIE_AUX_CLK 44 -#define PCIE_PHY_REF_CLK 45 -#define PCIE_H_CLK 46 -#define SFAB_CLK_SRC 47 -#define MAHB0_CLK 48 -#define Q6SW_CLK_SRC 49 -#define Q6SW_CLK 50 -#define Q6FW_CLK_SRC 51 -#define Q6FW_CLK 52 -#define SFAB_MSS_M_A_CLK 53 -#define SFAB_USB3_M_A_CLK 54 -#define SFAB_LPASS_Q6_A_CLK 55 -#define SFAB_AFAB_M_A_CLK 56 -#define AFAB_SFAB_M0_A_CLK 57 -#define AFAB_SFAB_M1_A_CLK 58 -#define SFAB_SATA_S_H_CLK 59 -#define DFAB_CLK_SRC 60 -#define DFAB_CLK 61 -#define SFAB_DFAB_M_A_CLK 62 -#define DFAB_SFAB_M_A_CLK 63 -#define DFAB_SWAY0_H_CLK 64 -#define DFAB_SWAY1_H_CLK 65 -#define DFAB_ARB0_H_CLK 66 -#define DFAB_ARB1_H_CLK 67 -#define PPSS_H_CLK 68 -#define PPSS_PROC_CLK 69 -#define PPSS_TIMER0_CLK 70 -#define PPSS_TIMER1_CLK 71 -#define PMEM_A_CLK 72 -#define DMA_BAM_H_CLK 73 -#define SIC_H_CLK 74 -#define SPS_TIC_H_CLK 75 -#define SLIMBUS_H_CLK 76 -#define SLIMBUS_XO_SRC_CLK 77 -#define CFPB_2X_CLK_SRC 78 -#define CFPB_CLK 79 -#define CFPB0_H_CLK 80 -#define CFPB1_H_CLK 81 -#define CFPB2_H_CLK 82 -#define SFAB_CFPB_M_H_CLK 83 -#define CFPB_MASTER_H_CLK 84 -#define SFAB_CFPB_S_H_CLK 85 -#define CFPB_SPLITTER_H_CLK 86 -#define TSIF_H_CLK 87 -#define TSIF_INACTIVITY_TIMERS_CLK 88 -#define TSIF_REF_SRC 89 -#define TSIF_REF_CLK 90 -#define CE1_H_CLK 91 -#define CE1_CORE_CLK 92 -#define CE1_SLEEP_CLK 93 -#define CE2_H_CLK 94 -#define CE2_CORE_CLK 95 -#define SFPB_H_CLK_SRC 97 -#define SFPB_H_CLK 98 -#define SFAB_SFPB_M_H_CLK 99 -#define SFAB_SFPB_S_H_CLK 100 -#define RPM_PROC_CLK 101 -#define RPM_BUS_H_CLK 102 -#define RPM_SLEEP_CLK 103 -#define RPM_TIMER_CLK 104 -#define RPM_MSG_RAM_H_CLK 105 -#define PMIC_ARB0_H_CLK 106 -#define PMIC_ARB1_H_CLK 107 -#define PMIC_SSBI2_SRC 108 -#define PMIC_SSBI2_CLK 109 -#define SDC1_H_CLK 110 -#define SDC2_H_CLK 111 -#define SDC3_H_CLK 112 -#define SDC4_H_CLK 113 -#define SDC5_H_CLK 114 -#define SDC1_SRC 115 -#define SDC2_SRC 116 -#define SDC3_SRC 117 -#define SDC4_SRC 118 -#define SDC5_SRC 119 -#define SDC1_CLK 120 -#define SDC2_CLK 121 -#define SDC3_CLK 122 -#define SDC4_CLK 123 -#define SDC5_CLK 124 -#define DFAB_A2_H_CLK 125 -#define USB_HS1_H_CLK 126 -#define USB_HS1_XCVR_SRC 127 -#define USB_HS1_XCVR_CLK 128 -#define USB_HSIC_H_CLK 129 -#define USB_HSIC_XCVR_FS_SRC 130 -#define USB_HSIC_XCVR_FS_CLK 131 -#define USB_HSIC_SYSTEM_CLK_SRC 132 -#define USB_HSIC_SYSTEM_CLK 133 -#define CFPB0_C0_H_CLK 134 -#define CFPB0_C1_H_CLK 135 -#define CFPB0_D0_H_CLK 136 -#define CFPB0_D1_H_CLK 137 -#define USB_FS1_H_CLK 138 -#define USB_FS1_XCVR_FS_SRC 139 -#define USB_FS1_XCVR_FS_CLK 140 -#define USB_FS1_SYSTEM_CLK 141 -#define USB_FS2_H_CLK 142 -#define USB_FS2_XCVR_FS_SRC 143 -#define USB_FS2_XCVR_FS_CLK 144 -#define USB_FS2_SYSTEM_CLK 145 -#define GSBI_COMMON_SIM_SRC 146 -#define GSBI1_H_CLK 147 -#define GSBI2_H_CLK 148 -#define GSBI3_H_CLK 149 -#define GSBI4_H_CLK 150 -#define GSBI5_H_CLK 151 -#define GSBI6_H_CLK 152 -#define GSBI7_H_CLK 153 -#define GSBI8_H_CLK 154 -#define GSBI9_H_CLK 155 -#define GSBI10_H_CLK 156 -#define GSBI11_H_CLK 157 -#define GSBI12_H_CLK 158 -#define GSBI1_UART_SRC 159 -#define GSBI1_UART_CLK 160 -#define GSBI2_UART_SRC 161 -#define GSBI2_UART_CLK 162 -#define GSBI3_UART_SRC 163 -#define GSBI3_UART_CLK 164 -#define GSBI4_UART_SRC 165 -#define GSBI4_UART_CLK 166 -#define GSBI5_UART_SRC 167 -#define GSBI5_UART_CLK 168 -#define GSBI6_UART_SRC 169 -#define GSBI6_UART_CLK 170 -#define GSBI7_UART_SRC 171 -#define GSBI7_UART_CLK 172 -#define GSBI8_UART_SRC 173 -#define GSBI8_UART_CLK 174 -#define GSBI9_UART_SRC 175 -#define GSBI9_UART_CLK 176 -#define GSBI10_UART_SRC 177 -#define GSBI10_UART_CLK 178 -#define GSBI11_UART_SRC 179 -#define GSBI11_UART_CLK 180 -#define GSBI12_UART_SRC 181 -#define GSBI12_UART_CLK 182 -#define GSBI1_QUP_SRC 183 -#define GSBI1_QUP_CLK 184 -#define GSBI2_QUP_SRC 185 -#define GSBI2_QUP_CLK 186 -#define GSBI3_QUP_SRC 187 -#define GSBI3_QUP_CLK 188 -#define GSBI4_QUP_SRC 189 -#define GSBI4_QUP_CLK 190 -#define GSBI5_QUP_SRC 191 -#define GSBI5_QUP_CLK 192 -#define GSBI6_QUP_SRC 193 -#define GSBI6_QUP_CLK 194 -#define GSBI7_QUP_SRC 195 -#define GSBI7_QUP_CLK 196 -#define GSBI8_QUP_SRC 197 -#define GSBI8_QUP_CLK 198 -#define GSBI9_QUP_SRC 199 -#define GSBI9_QUP_CLK 200 -#define GSBI10_QUP_SRC 201 -#define GSBI10_QUP_CLK 202 -#define GSBI11_QUP_SRC 203 -#define GSBI11_QUP_CLK 204 -#define GSBI12_QUP_SRC 205 -#define GSBI12_QUP_CLK 206 -#define GSBI1_SIM_CLK 207 -#define GSBI2_SIM_CLK 208 -#define GSBI3_SIM_CLK 209 -#define GSBI4_SIM_CLK 210 -#define GSBI5_SIM_CLK 211 -#define GSBI6_SIM_CLK 212 -#define GSBI7_SIM_CLK 213 -#define GSBI8_SIM_CLK 214 -#define GSBI9_SIM_CLK 215 -#define GSBI10_SIM_CLK 216 -#define GSBI11_SIM_CLK 217 -#define GSBI12_SIM_CLK 218 -#define USB_HSIC_HSIC_CLK_SRC 219 -#define USB_HSIC_HSIC_CLK 220 -#define USB_HSIC_HSIO_CAL_CLK 221 -#define SPDM_CFG_H_CLK 222 -#define SPDM_MSTR_H_CLK 223 -#define SPDM_FF_CLK_SRC 224 -#define SPDM_FF_CLK 225 -#define SEC_CTRL_CLK 226 -#define SEC_CTRL_ACC_CLK_SRC 227 -#define SEC_CTRL_ACC_CLK 228 -#define TLMM_H_CLK 229 -#define TLMM_CLK 230 -#define SFAB_MSS_S_H_CLK 231 -#define MSS_SLP_CLK 232 -#define MSS_Q6SW_JTAG_CLK 233 -#define MSS_Q6FW_JTAG_CLK 234 -#define MSS_S_H_CLK 235 -#define MSS_CXO_SRC_CLK 236 -#define SATA_H_CLK 237 -#define SATA_CLK_SRC 238 -#define SATA_RXOOB_CLK 239 -#define SATA_PMALIVE_CLK 240 -#define SATA_PHY_REF_CLK 241 -#define TSSC_CLK_SRC 242 -#define TSSC_CLK 243 -#define PDM_SRC 244 -#define PDM_CLK 245 -#define GP0_SRC 246 -#define GP0_CLK 247 -#define GP1_SRC 248 -#define GP1_CLK 249 -#define GP2_SRC 250 -#define GP2_CLK 251 -#define MPM_CLK 252 -#define EBI1_CLK_SRC 253 -#define EBI1_CH0_CLK 254 -#define EBI1_CH1_CLK 255 -#define EBI1_2X_CLK 256 -#define EBI1_CH0_DQ_CLK 257 -#define EBI1_CH1_DQ_CLK 258 -#define EBI1_CH0_CA_CLK 259 -#define EBI1_CH1_CA_CLK 260 -#define EBI1_XO_CLK 261 -#define SFAB_SMPSS_S_H_CLK 262 -#define PRNG_SRC 263 -#define PRNG_CLK 264 -#define PXO_SRC 265 -#define LPASS_CXO_CLK 266 -#define LPASS_PXO_CLK 267 -#define SPDM_CY_PORT0_CLK 268 -#define SPDM_CY_PORT1_CLK 269 -#define SPDM_CY_PORT2_CLK 270 -#define SPDM_CY_PORT3_CLK 271 -#define SPDM_CY_PORT4_CLK 272 -#define SPDM_CY_PORT5_CLK 273 -#define SPDM_CY_PORT6_CLK 274 -#define SPDM_CY_PORT7_CLK 275 -#define PLL0 276 -#define PLL0_VOTE 277 -#define PLL3 278 -#define PLL3_VOTE 279 -#define PLL4_VOTE 280 -#define PLL5 281 -#define PLL5_VOTE 282 -#define PLL6 283 -#define PLL6_VOTE 284 -#define PLL7_VOTE 285 -#define PLL8 286 -#define PLL8_VOTE 287 -#define PLL9 288 -#define PLL10 289 -#define PLL11 290 -#define PLL12 291 -#define PLL13 292 -#define PLL14 293 -#define PLL14_VOTE 294 -#define USB_HS3_H_CLK 295 -#define USB_HS3_XCVR_SRC 296 -#define USB_HS3_XCVR_CLK 297 -#define USB_HS4_H_CLK 298 -#define USB_HS4_XCVR_SRC 299 -#define USB_HS4_XCVR_CLK 300 -#define SATA_PHY_CFG_CLK 301 -#define SATA_A_CLK 302 -#define CE3_SRC 303 -#define CE3_CORE_CLK 304 -#define CE3_H_CLK 305 -#define USB_HS1_SYSTEM_CLK_SRC 306 -#define USB_HS1_SYSTEM_CLK 307 -#define EBI2_CLK 308 -#define EBI2_AON_CLK 309 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-msm8660.h b/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-msm8660.h deleted file mode 100644 index 4777c002711..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-msm8660.h +++ /dev/null @@ -1,268 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2013, The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_CLK_MSM_GCC_8660_H -#define _DT_BINDINGS_CLK_MSM_GCC_8660_H - -#define AFAB_CLK_SRC 0 -#define AFAB_CORE_CLK 1 -#define SCSS_A_CLK 2 -#define SCSS_H_CLK 3 -#define SCSS_XO_SRC_CLK 4 -#define AFAB_EBI1_CH0_A_CLK 5 -#define AFAB_EBI1_CH1_A_CLK 6 -#define AFAB_AXI_S0_FCLK 7 -#define AFAB_AXI_S1_FCLK 8 -#define AFAB_AXI_S2_FCLK 9 -#define AFAB_AXI_S3_FCLK 10 -#define AFAB_AXI_S4_FCLK 11 -#define SFAB_CORE_CLK 12 -#define SFAB_AXI_S0_FCLK 13 -#define SFAB_AXI_S1_FCLK 14 -#define SFAB_AXI_S2_FCLK 15 -#define SFAB_AXI_S3_FCLK 16 -#define SFAB_AXI_S4_FCLK 17 -#define SFAB_AHB_S0_FCLK 18 -#define SFAB_AHB_S1_FCLK 19 -#define SFAB_AHB_S2_FCLK 20 -#define SFAB_AHB_S3_FCLK 21 -#define SFAB_AHB_S4_FCLK 22 -#define SFAB_AHB_S5_FCLK 23 -#define SFAB_AHB_S6_FCLK 24 -#define SFAB_ADM0_M0_A_CLK 25 -#define SFAB_ADM0_M1_A_CLK 26 -#define SFAB_ADM0_M2_A_CLK 27 -#define ADM0_CLK 28 -#define ADM0_PBUS_CLK 29 -#define SFAB_ADM1_M0_A_CLK 30 -#define SFAB_ADM1_M1_A_CLK 31 -#define SFAB_ADM1_M2_A_CLK 32 -#define MMFAB_ADM1_M3_A_CLK 33 -#define ADM1_CLK 34 -#define ADM1_PBUS_CLK 35 -#define IMEM0_A_CLK 36 -#define MAHB0_CLK 37 -#define SFAB_LPASS_Q6_A_CLK 38 -#define SFAB_AFAB_M_A_CLK 39 -#define AFAB_SFAB_M0_A_CLK 40 -#define AFAB_SFAB_M1_A_CLK 41 -#define DFAB_CLK_SRC 42 -#define DFAB_CLK 43 -#define DFAB_CORE_CLK 44 -#define SFAB_DFAB_M_A_CLK 45 -#define DFAB_SFAB_M_A_CLK 46 -#define DFAB_SWAY0_H_CLK 47 -#define DFAB_SWAY1_H_CLK 48 -#define DFAB_ARB0_H_CLK 49 -#define DFAB_ARB1_H_CLK 50 -#define PPSS_H_CLK 51 -#define PPSS_PROC_CLK 52 -#define PPSS_TIMER0_CLK 53 -#define PPSS_TIMER1_CLK 54 -#define PMEM_A_CLK 55 -#define DMA_BAM_H_CLK 56 -#define SIC_H_CLK 57 -#define SPS_TIC_H_CLK 58 -#define SLIMBUS_H_CLK 59 -#define SLIMBUS_XO_SRC_CLK 60 -#define CFPB_2X_CLK_SRC 61 -#define CFPB_CLK 62 -#define CFPB0_H_CLK 63 -#define CFPB1_H_CLK 64 -#define CFPB2_H_CLK 65 -#define EBI2_2X_CLK 66 -#define EBI2_CLK 67 -#define SFAB_CFPB_M_H_CLK 68 -#define CFPB_MASTER_H_CLK 69 -#define SFAB_CFPB_S_HCLK 70 -#define CFPB_SPLITTER_H_CLK 71 -#define TSIF_H_CLK 72 -#define TSIF_INACTIVITY_TIMERS_CLK 73 -#define TSIF_REF_SRC 74 -#define TSIF_REF_CLK 75 -#define CE1_H_CLK 76 -#define CE2_H_CLK 77 -#define SFPB_H_CLK_SRC 78 -#define SFPB_H_CLK 79 -#define SFAB_SFPB_M_H_CLK 80 -#define SFAB_SFPB_S_H_CLK 81 -#define RPM_PROC_CLK 82 -#define RPM_BUS_H_CLK 83 -#define RPM_SLEEP_CLK 84 -#define RPM_TIMER_CLK 85 -#define MODEM_AHB1_H_CLK 86 -#define MODEM_AHB2_H_CLK 87 -#define RPM_MSG_RAM_H_CLK 88 -#define SC_H_CLK 89 -#define SC_A_CLK 90 -#define PMIC_ARB0_H_CLK 91 -#define PMIC_ARB1_H_CLK 92 -#define PMIC_SSBI2_SRC 93 -#define PMIC_SSBI2_CLK 94 -#define SDC1_H_CLK 95 -#define SDC2_H_CLK 96 -#define SDC3_H_CLK 97 -#define SDC4_H_CLK 98 -#define SDC5_H_CLK 99 -#define SDC1_SRC 100 -#define SDC2_SRC 101 -#define SDC3_SRC 102 -#define SDC4_SRC 103 -#define SDC5_SRC 104 -#define SDC1_CLK 105 -#define SDC2_CLK 106 -#define SDC3_CLK 107 -#define SDC4_CLK 108 -#define SDC5_CLK 109 -#define USB_HS1_H_CLK 110 -#define USB_HS1_XCVR_SRC 111 -#define USB_HS1_XCVR_CLK 112 -#define USB_HS2_H_CLK 113 -#define USB_HS2_XCVR_SRC 114 -#define USB_HS2_XCVR_CLK 115 -#define USB_FS1_H_CLK 116 -#define USB_FS1_XCVR_FS_SRC 117 -#define USB_FS1_XCVR_FS_CLK 118 -#define USB_FS1_SYSTEM_CLK 119 -#define USB_FS2_H_CLK 120 -#define USB_FS2_XCVR_FS_SRC 121 -#define USB_FS2_XCVR_FS_CLK 122 -#define USB_FS2_SYSTEM_CLK 123 -#define GSBI_COMMON_SIM_SRC 124 -#define GSBI1_H_CLK 125 -#define GSBI2_H_CLK 126 -#define GSBI3_H_CLK 127 -#define GSBI4_H_CLK 128 -#define GSBI5_H_CLK 129 -#define GSBI6_H_CLK 130 -#define GSBI7_H_CLK 131 -#define GSBI8_H_CLK 132 -#define GSBI9_H_CLK 133 -#define GSBI10_H_CLK 134 -#define GSBI11_H_CLK 135 -#define GSBI12_H_CLK 136 -#define GSBI1_UART_SRC 137 -#define GSBI1_UART_CLK 138 -#define GSBI2_UART_SRC 139 -#define GSBI2_UART_CLK 140 -#define GSBI3_UART_SRC 141 -#define GSBI3_UART_CLK 142 -#define GSBI4_UART_SRC 143 -#define GSBI4_UART_CLK 144 -#define GSBI5_UART_SRC 145 -#define GSBI5_UART_CLK 146 -#define GSBI6_UART_SRC 147 -#define GSBI6_UART_CLK 148 -#define GSBI7_UART_SRC 149 -#define GSBI7_UART_CLK 150 -#define GSBI8_UART_SRC 151 -#define GSBI8_UART_CLK 152 -#define GSBI9_UART_SRC 153 -#define GSBI9_UART_CLK 154 -#define GSBI10_UART_SRC 155 -#define GSBI10_UART_CLK 156 -#define GSBI11_UART_SRC 157 -#define GSBI11_UART_CLK 158 -#define GSBI12_UART_SRC 159 -#define GSBI12_UART_CLK 160 -#define GSBI1_QUP_SRC 161 -#define GSBI1_QUP_CLK 162 -#define GSBI2_QUP_SRC 163 -#define GSBI2_QUP_CLK 164 -#define GSBI3_QUP_SRC 165 -#define GSBI3_QUP_CLK 166 -#define GSBI4_QUP_SRC 167 -#define GSBI4_QUP_CLK 168 -#define GSBI5_QUP_SRC 169 -#define GSBI5_QUP_CLK 170 -#define GSBI6_QUP_SRC 171 -#define GSBI6_QUP_CLK 172 -#define GSBI7_QUP_SRC 173 -#define GSBI7_QUP_CLK 174 -#define GSBI8_QUP_SRC 175 -#define GSBI8_QUP_CLK 176 -#define GSBI9_QUP_SRC 177 -#define GSBI9_QUP_CLK 178 -#define GSBI10_QUP_SRC 179 -#define GSBI10_QUP_CLK 180 -#define GSBI11_QUP_SRC 181 -#define GSBI11_QUP_CLK 182 -#define GSBI12_QUP_SRC 183 -#define GSBI12_QUP_CLK 184 -#define GSBI1_SIM_CLK 185 -#define GSBI2_SIM_CLK 186 -#define GSBI3_SIM_CLK 187 -#define GSBI4_SIM_CLK 188 -#define GSBI5_SIM_CLK 189 -#define GSBI6_SIM_CLK 190 -#define GSBI7_SIM_CLK 191 -#define GSBI8_SIM_CLK 192 -#define GSBI9_SIM_CLK 193 -#define GSBI10_SIM_CLK 194 -#define GSBI11_SIM_CLK 195 -#define GSBI12_SIM_CLK 196 -#define SPDM_CFG_H_CLK 197 -#define SPDM_MSTR_H_CLK 198 -#define SPDM_FF_CLK_SRC 199 -#define SPDM_FF_CLK 200 -#define SEC_CTRL_CLK 201 -#define SEC_CTRL_ACC_CLK_SRC 202 -#define SEC_CTRL_ACC_CLK 203 -#define TLMM_H_CLK 204 -#define TLMM_CLK 205 -#define MARM_CLK_SRC 206 -#define MARM_CLK 207 -#define MAHB1_SRC 208 -#define MAHB1_CLK 209 -#define SFAB_MSS_S_H_CLK 210 -#define MAHB2_SRC 211 -#define MAHB2_CLK 212 -#define MSS_MODEM_CLK_SRC 213 -#define MSS_MODEM_CXO_CLK 214 -#define MSS_SLP_CLK 215 -#define MSS_SYS_REF_CLK 216 -#define TSSC_CLK_SRC 217 -#define TSSC_CLK 218 -#define PDM_SRC 219 -#define PDM_CLK 220 -#define GP0_SRC 221 -#define GP0_CLK 222 -#define GP1_SRC 223 -#define GP1_CLK 224 -#define GP2_SRC 225 -#define GP2_CLK 226 -#define PMEM_CLK 227 -#define MPM_CLK 228 -#define EBI1_ASFAB_SRC 229 -#define EBI1_CLK_SRC 230 -#define EBI1_CH0_CLK 231 -#define EBI1_CH1_CLK 232 -#define SFAB_SMPSS_S_H_CLK 233 -#define PRNG_SRC 234 -#define PRNG_CLK 235 -#define PXO_SRC 236 -#define LPASS_CXO_CLK 237 -#define LPASS_PXO_CLK 238 -#define SPDM_CY_PORT0_CLK 239 -#define SPDM_CY_PORT1_CLK 240 -#define SPDM_CY_PORT2_CLK 241 -#define SPDM_CY_PORT3_CLK 242 -#define SPDM_CY_PORT4_CLK 243 -#define SPDM_CY_PORT5_CLK 244 -#define SPDM_CY_PORT6_CLK 245 -#define SPDM_CY_PORT7_CLK 246 -#define PLL0 247 -#define PLL0_VOTE 248 -#define PLL5 249 -#define PLL6 250 -#define PLL6_VOTE 251 -#define PLL8 252 -#define PLL8_VOTE 253 -#define PLL9 254 -#define PLL10 255 -#define PLL11 256 -#define PLL12 257 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-msm8916.h b/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-msm8916.h deleted file mode 100644 index 56303440618..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-msm8916.h +++ /dev/null @@ -1,179 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2015 Linaro Limited - */ - -#ifndef _DT_BINDINGS_CLK_MSM_GCC_8916_H -#define _DT_BINDINGS_CLK_MSM_GCC_8916_H - -#define GPLL0 0 -#define GPLL0_VOTE 1 -#define BIMC_PLL 2 -#define BIMC_PLL_VOTE 3 -#define GPLL1 4 -#define GPLL1_VOTE 5 -#define GPLL2 6 -#define GPLL2_VOTE 7 -#define PCNOC_BFDCD_CLK_SRC 8 -#define SYSTEM_NOC_BFDCD_CLK_SRC 9 -#define CAMSS_AHB_CLK_SRC 10 -#define APSS_AHB_CLK_SRC 11 -#define CSI0_CLK_SRC 12 -#define CSI1_CLK_SRC 13 -#define GFX3D_CLK_SRC 14 -#define VFE0_CLK_SRC 15 -#define BLSP1_QUP1_I2C_APPS_CLK_SRC 16 -#define BLSP1_QUP1_SPI_APPS_CLK_SRC 17 -#define BLSP1_QUP2_I2C_APPS_CLK_SRC 18 -#define BLSP1_QUP2_SPI_APPS_CLK_SRC 19 -#define BLSP1_QUP3_I2C_APPS_CLK_SRC 20 -#define BLSP1_QUP3_SPI_APPS_CLK_SRC 21 -#define BLSP1_QUP4_I2C_APPS_CLK_SRC 22 -#define BLSP1_QUP4_SPI_APPS_CLK_SRC 23 -#define BLSP1_QUP5_I2C_APPS_CLK_SRC 24 -#define BLSP1_QUP5_SPI_APPS_CLK_SRC 25 -#define BLSP1_QUP6_I2C_APPS_CLK_SRC 26 -#define BLSP1_QUP6_SPI_APPS_CLK_SRC 27 -#define BLSP1_UART1_APPS_CLK_SRC 28 -#define BLSP1_UART2_APPS_CLK_SRC 29 -#define CCI_CLK_SRC 30 -#define CAMSS_GP0_CLK_SRC 31 -#define CAMSS_GP1_CLK_SRC 32 -#define JPEG0_CLK_SRC 33 -#define MCLK0_CLK_SRC 34 -#define MCLK1_CLK_SRC 35 -#define CSI0PHYTIMER_CLK_SRC 36 -#define CSI1PHYTIMER_CLK_SRC 37 -#define CPP_CLK_SRC 38 -#define CRYPTO_CLK_SRC 39 -#define GP1_CLK_SRC 40 -#define GP2_CLK_SRC 41 -#define GP3_CLK_SRC 42 -#define BYTE0_CLK_SRC 43 -#define ESC0_CLK_SRC 44 -#define MDP_CLK_SRC 45 -#define PCLK0_CLK_SRC 46 -#define VSYNC_CLK_SRC 47 -#define PDM2_CLK_SRC 48 -#define SDCC1_APPS_CLK_SRC 49 -#define SDCC2_APPS_CLK_SRC 50 -#define APSS_TCU_CLK_SRC 51 -#define USB_HS_SYSTEM_CLK_SRC 52 -#define VCODEC0_CLK_SRC 53 -#define GCC_BLSP1_AHB_CLK 54 -#define GCC_BLSP1_SLEEP_CLK 55 -#define GCC_BLSP1_QUP1_I2C_APPS_CLK 56 -#define GCC_BLSP1_QUP1_SPI_APPS_CLK 57 -#define GCC_BLSP1_QUP2_I2C_APPS_CLK 58 -#define GCC_BLSP1_QUP2_SPI_APPS_CLK 59 -#define GCC_BLSP1_QUP3_I2C_APPS_CLK 60 -#define GCC_BLSP1_QUP3_SPI_APPS_CLK 61 -#define GCC_BLSP1_QUP4_I2C_APPS_CLK 62 -#define GCC_BLSP1_QUP4_SPI_APPS_CLK 63 -#define GCC_BLSP1_QUP5_I2C_APPS_CLK 64 -#define GCC_BLSP1_QUP5_SPI_APPS_CLK 65 -#define GCC_BLSP1_QUP6_I2C_APPS_CLK 66 -#define GCC_BLSP1_QUP6_SPI_APPS_CLK 67 -#define GCC_BLSP1_UART1_APPS_CLK 68 -#define GCC_BLSP1_UART2_APPS_CLK 69 -#define GCC_BOOT_ROM_AHB_CLK 70 -#define GCC_CAMSS_CCI_AHB_CLK 71 -#define GCC_CAMSS_CCI_CLK 72 -#define GCC_CAMSS_CSI0_AHB_CLK 73 -#define GCC_CAMSS_CSI0_CLK 74 -#define GCC_CAMSS_CSI0PHY_CLK 75 -#define GCC_CAMSS_CSI0PIX_CLK 76 -#define GCC_CAMSS_CSI0RDI_CLK 77 -#define GCC_CAMSS_CSI1_AHB_CLK 78 -#define GCC_CAMSS_CSI1_CLK 79 -#define GCC_CAMSS_CSI1PHY_CLK 80 -#define GCC_CAMSS_CSI1PIX_CLK 81 -#define GCC_CAMSS_CSI1RDI_CLK 82 -#define GCC_CAMSS_CSI_VFE0_CLK 83 -#define GCC_CAMSS_GP0_CLK 84 -#define GCC_CAMSS_GP1_CLK 85 -#define GCC_CAMSS_ISPIF_AHB_CLK 86 -#define GCC_CAMSS_JPEG0_CLK 87 -#define GCC_CAMSS_JPEG_AHB_CLK 88 -#define GCC_CAMSS_JPEG_AXI_CLK 89 -#define GCC_CAMSS_MCLK0_CLK 90 -#define GCC_CAMSS_MCLK1_CLK 91 -#define GCC_CAMSS_MICRO_AHB_CLK 92 -#define GCC_CAMSS_CSI0PHYTIMER_CLK 93 -#define GCC_CAMSS_CSI1PHYTIMER_CLK 94 -#define GCC_CAMSS_AHB_CLK 95 -#define GCC_CAMSS_TOP_AHB_CLK 96 -#define GCC_CAMSS_CPP_AHB_CLK 97 -#define GCC_CAMSS_CPP_CLK 98 -#define GCC_CAMSS_VFE0_CLK 99 -#define GCC_CAMSS_VFE_AHB_CLK 100 -#define GCC_CAMSS_VFE_AXI_CLK 101 -#define GCC_CRYPTO_AHB_CLK 102 -#define GCC_CRYPTO_AXI_CLK 103 -#define GCC_CRYPTO_CLK 104 -#define GCC_OXILI_GMEM_CLK 105 -#define GCC_GP1_CLK 106 -#define GCC_GP2_CLK 107 -#define GCC_GP3_CLK 108 -#define GCC_MDSS_AHB_CLK 109 -#define GCC_MDSS_AXI_CLK 110 -#define GCC_MDSS_BYTE0_CLK 111 -#define GCC_MDSS_ESC0_CLK 112 -#define GCC_MDSS_MDP_CLK 113 -#define GCC_MDSS_PCLK0_CLK 114 -#define GCC_MDSS_VSYNC_CLK 115 -#define GCC_MSS_CFG_AHB_CLK 116 -#define GCC_OXILI_AHB_CLK 117 -#define GCC_OXILI_GFX3D_CLK 118 -#define GCC_PDM2_CLK 119 -#define GCC_PDM_AHB_CLK 120 -#define GCC_PRNG_AHB_CLK 121 -#define GCC_SDCC1_AHB_CLK 122 -#define GCC_SDCC1_APPS_CLK 123 -#define GCC_SDCC2_AHB_CLK 124 -#define GCC_SDCC2_APPS_CLK 125 -#define GCC_GTCU_AHB_CLK 126 -#define GCC_JPEG_TBU_CLK 127 -#define GCC_MDP_TBU_CLK 128 -#define GCC_SMMU_CFG_CLK 129 -#define GCC_VENUS_TBU_CLK 130 -#define GCC_VFE_TBU_CLK 131 -#define GCC_USB2A_PHY_SLEEP_CLK 132 -#define GCC_USB_HS_AHB_CLK 133 -#define GCC_USB_HS_SYSTEM_CLK 134 -#define GCC_VENUS0_AHB_CLK 135 -#define GCC_VENUS0_AXI_CLK 136 -#define GCC_VENUS0_VCODEC0_CLK 137 -#define BIMC_DDR_CLK_SRC 138 -#define GCC_APSS_TCU_CLK 139 -#define GCC_GFX_TCU_CLK 140 -#define BIMC_GPU_CLK_SRC 141 -#define GCC_BIMC_GFX_CLK 142 -#define GCC_BIMC_GPU_CLK 143 -#define ULTAUDIO_LPAIF_PRI_I2S_CLK_SRC 144 -#define ULTAUDIO_LPAIF_SEC_I2S_CLK_SRC 145 -#define ULTAUDIO_LPAIF_AUX_I2S_CLK_SRC 146 -#define ULTAUDIO_XO_CLK_SRC 147 -#define ULTAUDIO_AHBFABRIC_CLK_SRC 148 -#define CODEC_DIGCODEC_CLK_SRC 149 -#define GCC_ULTAUDIO_PCNOC_MPORT_CLK 150 -#define GCC_ULTAUDIO_PCNOC_SWAY_CLK 151 -#define GCC_ULTAUDIO_AVSYNC_XO_CLK 152 -#define GCC_ULTAUDIO_STC_XO_CLK 153 -#define GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK 154 -#define GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CLK 155 -#define GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK 156 -#define GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK 157 -#define GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK 158 -#define GCC_CODEC_DIGCODEC_CLK 159 -#define GCC_MSS_Q6_BIMC_AXI_CLK 160 - -/* Indexes for GDSCs */ -#define BIMC_GDSC 0 -#define VENUS_GDSC 1 -#define MDSS_GDSC 2 -#define JPEG_GDSC 3 -#define VFE_GDSC 4 -#define OXILI_GDSC 5 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-msm8960.h b/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-msm8960.h deleted file mode 100644 index 950b8286262..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-msm8960.h +++ /dev/null @@ -1,317 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2013, The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_CLK_MSM_GCC_8960_H -#define _DT_BINDINGS_CLK_MSM_GCC_8960_H - -#define AFAB_CLK_SRC 0 -#define AFAB_CORE_CLK 1 -#define SFAB_MSS_Q6_SW_A_CLK 2 -#define SFAB_MSS_Q6_FW_A_CLK 3 -#define QDSS_STM_CLK 4 -#define SCSS_A_CLK 5 -#define SCSS_H_CLK 6 -#define SCSS_XO_SRC_CLK 7 -#define AFAB_EBI1_CH0_A_CLK 8 -#define AFAB_EBI1_CH1_A_CLK 9 -#define AFAB_AXI_S0_FCLK 10 -#define AFAB_AXI_S1_FCLK 11 -#define AFAB_AXI_S2_FCLK 12 -#define AFAB_AXI_S3_FCLK 13 -#define AFAB_AXI_S4_FCLK 14 -#define SFAB_CORE_CLK 15 -#define SFAB_AXI_S0_FCLK 16 -#define SFAB_AXI_S1_FCLK 17 -#define SFAB_AXI_S2_FCLK 18 -#define SFAB_AXI_S3_FCLK 19 -#define SFAB_AXI_S4_FCLK 20 -#define SFAB_AHB_S0_FCLK 21 -#define SFAB_AHB_S1_FCLK 22 -#define SFAB_AHB_S2_FCLK 23 -#define SFAB_AHB_S3_FCLK 24 -#define SFAB_AHB_S4_FCLK 25 -#define SFAB_AHB_S5_FCLK 26 -#define SFAB_AHB_S6_FCLK 27 -#define SFAB_AHB_S7_FCLK 28 -#define QDSS_AT_CLK_SRC 29 -#define QDSS_AT_CLK 30 -#define QDSS_TRACECLKIN_CLK_SRC 31 -#define QDSS_TRACECLKIN_CLK 32 -#define QDSS_TSCTR_CLK_SRC 33 -#define QDSS_TSCTR_CLK 34 -#define SFAB_ADM0_M0_A_CLK 35 -#define SFAB_ADM0_M1_A_CLK 36 -#define SFAB_ADM0_M2_H_CLK 37 -#define ADM0_CLK 38 -#define ADM0_PBUS_CLK 39 -#define MSS_XPU_CLK 40 -#define IMEM0_A_CLK 41 -#define QDSS_H_CLK 42 -#define PCIE_A_CLK 43 -#define PCIE_AUX_CLK 44 -#define PCIE_PHY_REF_CLK 45 -#define PCIE_H_CLK 46 -#define SFAB_CLK_SRC 47 -#define MAHB0_CLK 48 -#define Q6SW_CLK_SRC 49 -#define Q6SW_CLK 50 -#define Q6FW_CLK_SRC 51 -#define Q6FW_CLK 52 -#define SFAB_MSS_M_A_CLK 53 -#define SFAB_USB3_M_A_CLK 54 -#define SFAB_LPASS_Q6_A_CLK 55 -#define SFAB_AFAB_M_A_CLK 56 -#define AFAB_SFAB_M0_A_CLK 57 -#define AFAB_SFAB_M1_A_CLK 58 -#define SFAB_SATA_S_H_CLK 59 -#define DFAB_CLK_SRC 60 -#define DFAB_CLK 61 -#define SFAB_DFAB_M_A_CLK 62 -#define DFAB_SFAB_M_A_CLK 63 -#define DFAB_SWAY0_H_CLK 64 -#define DFAB_SWAY1_H_CLK 65 -#define DFAB_ARB0_H_CLK 66 -#define DFAB_ARB1_H_CLK 67 -#define PPSS_H_CLK 68 -#define PPSS_PROC_CLK 69 -#define PPSS_TIMER0_CLK 70 -#define PPSS_TIMER1_CLK 71 -#define PMEM_A_CLK 72 -#define DMA_BAM_H_CLK 73 -#define SIC_H_CLK 74 -#define SPS_TIC_H_CLK 75 -#define SLIMBUS_H_CLK 76 -#define SLIMBUS_XO_SRC_CLK 77 -#define CFPB_2X_CLK_SRC 78 -#define CFPB_CLK 79 -#define CFPB0_H_CLK 80 -#define CFPB1_H_CLK 81 -#define CFPB2_H_CLK 82 -#define SFAB_CFPB_M_H_CLK 83 -#define CFPB_MASTER_H_CLK 84 -#define SFAB_CFPB_S_H_CLK 85 -#define CFPB_SPLITTER_H_CLK 86 -#define TSIF_H_CLK 87 -#define TSIF_INACTIVITY_TIMERS_CLK 88 -#define TSIF_REF_SRC 89 -#define TSIF_REF_CLK 90 -#define CE1_H_CLK 91 -#define CE1_CORE_CLK 92 -#define CE1_SLEEP_CLK 93 -#define CE2_H_CLK 94 -#define CE2_CORE_CLK 95 -#define SFPB_H_CLK_SRC 97 -#define SFPB_H_CLK 98 -#define SFAB_SFPB_M_H_CLK 99 -#define SFAB_SFPB_S_H_CLK 100 -#define RPM_PROC_CLK 101 -#define RPM_BUS_H_CLK 102 -#define RPM_SLEEP_CLK 103 -#define RPM_TIMER_CLK 104 -#define RPM_MSG_RAM_H_CLK 105 -#define PMIC_ARB0_H_CLK 106 -#define PMIC_ARB1_H_CLK 107 -#define PMIC_SSBI2_SRC 108 -#define PMIC_SSBI2_CLK 109 -#define SDC1_H_CLK 110 -#define SDC2_H_CLK 111 -#define SDC3_H_CLK 112 -#define SDC4_H_CLK 113 -#define SDC5_H_CLK 114 -#define SDC1_SRC 115 -#define SDC2_SRC 116 -#define SDC3_SRC 117 -#define SDC4_SRC 118 -#define SDC5_SRC 119 -#define SDC1_CLK 120 -#define SDC2_CLK 121 -#define SDC3_CLK 122 -#define SDC4_CLK 123 -#define SDC5_CLK 124 -#define DFAB_A2_H_CLK 125 -#define USB_HS1_H_CLK 126 -#define USB_HS1_XCVR_SRC 127 -#define USB_HS1_XCVR_CLK 128 -#define USB_HSIC_H_CLK 129 -#define USB_HSIC_XCVR_FS_SRC 130 -#define USB_HSIC_XCVR_FS_CLK 131 -#define USB_HSIC_SYSTEM_CLK_SRC 132 -#define USB_HSIC_SYSTEM_CLK 133 -#define CFPB0_C0_H_CLK 134 -#define CFPB0_C1_H_CLK 135 -#define CFPB0_D0_H_CLK 136 -#define CFPB0_D1_H_CLK 137 -#define USB_FS1_H_CLK 138 -#define USB_FS1_XCVR_FS_SRC 139 -#define USB_FS1_XCVR_FS_CLK 140 -#define USB_FS1_SYSTEM_CLK 141 -#define USB_FS2_H_CLK 142 -#define USB_FS2_XCVR_FS_SRC 143 -#define USB_FS2_XCVR_FS_CLK 144 -#define USB_FS2_SYSTEM_CLK 145 -#define GSBI_COMMON_SIM_SRC 146 -#define GSBI1_H_CLK 147 -#define GSBI2_H_CLK 148 -#define GSBI3_H_CLK 149 -#define GSBI4_H_CLK 150 -#define GSBI5_H_CLK 151 -#define GSBI6_H_CLK 152 -#define GSBI7_H_CLK 153 -#define GSBI8_H_CLK 154 -#define GSBI9_H_CLK 155 -#define GSBI10_H_CLK 156 -#define GSBI11_H_CLK 157 -#define GSBI12_H_CLK 158 -#define GSBI1_UART_SRC 159 -#define GSBI1_UART_CLK 160 -#define GSBI2_UART_SRC 161 -#define GSBI2_UART_CLK 162 -#define GSBI3_UART_SRC 163 -#define GSBI3_UART_CLK 164 -#define GSBI4_UART_SRC 165 -#define GSBI4_UART_CLK 166 -#define GSBI5_UART_SRC 167 -#define GSBI5_UART_CLK 168 -#define GSBI6_UART_SRC 169 -#define GSBI6_UART_CLK 170 -#define GSBI7_UART_SRC 171 -#define GSBI7_UART_CLK 172 -#define GSBI8_UART_SRC 173 -#define GSBI8_UART_CLK 174 -#define GSBI9_UART_SRC 175 -#define GSBI9_UART_CLK 176 -#define GSBI10_UART_SRC 177 -#define GSBI10_UART_CLK 178 -#define GSBI11_UART_SRC 179 -#define GSBI11_UART_CLK 180 -#define GSBI12_UART_SRC 181 -#define GSBI12_UART_CLK 182 -#define GSBI1_QUP_SRC 183 -#define GSBI1_QUP_CLK 184 -#define GSBI2_QUP_SRC 185 -#define GSBI2_QUP_CLK 186 -#define GSBI3_QUP_SRC 187 -#define GSBI3_QUP_CLK 188 -#define GSBI4_QUP_SRC 189 -#define GSBI4_QUP_CLK 190 -#define GSBI5_QUP_SRC 191 -#define GSBI5_QUP_CLK 192 -#define GSBI6_QUP_SRC 193 -#define GSBI6_QUP_CLK 194 -#define GSBI7_QUP_SRC 195 -#define GSBI7_QUP_CLK 196 -#define GSBI8_QUP_SRC 197 -#define GSBI8_QUP_CLK 198 -#define GSBI9_QUP_SRC 199 -#define GSBI9_QUP_CLK 200 -#define GSBI10_QUP_SRC 201 -#define GSBI10_QUP_CLK 202 -#define GSBI11_QUP_SRC 203 -#define GSBI11_QUP_CLK 204 -#define GSBI12_QUP_SRC 205 -#define GSBI12_QUP_CLK 206 -#define GSBI1_SIM_CLK 207 -#define GSBI2_SIM_CLK 208 -#define GSBI3_SIM_CLK 209 -#define GSBI4_SIM_CLK 210 -#define GSBI5_SIM_CLK 211 -#define GSBI6_SIM_CLK 212 -#define GSBI7_SIM_CLK 213 -#define GSBI8_SIM_CLK 214 -#define GSBI9_SIM_CLK 215 -#define GSBI10_SIM_CLK 216 -#define GSBI11_SIM_CLK 217 -#define GSBI12_SIM_CLK 218 -#define USB_HSIC_HSIC_CLK_SRC 219 -#define USB_HSIC_HSIC_CLK 220 -#define USB_HSIC_HSIO_CAL_CLK 221 -#define SPDM_CFG_H_CLK 222 -#define SPDM_MSTR_H_CLK 223 -#define SPDM_FF_CLK_SRC 224 -#define SPDM_FF_CLK 225 -#define SEC_CTRL_CLK 226 -#define SEC_CTRL_ACC_CLK_SRC 227 -#define SEC_CTRL_ACC_CLK 228 -#define TLMM_H_CLK 229 -#define TLMM_CLK 230 -#define SFAB_MSS_S_H_CLK 231 -#define MSS_SLP_CLK 232 -#define MSS_Q6SW_JTAG_CLK 233 -#define MSS_Q6FW_JTAG_CLK 234 -#define MSS_S_H_CLK 235 -#define MSS_CXO_SRC_CLK 236 -#define SATA_H_CLK 237 -#define SATA_CLK_SRC 238 -#define SATA_RXOOB_CLK 239 -#define SATA_PMALIVE_CLK 240 -#define SATA_PHY_REF_CLK 241 -#define TSSC_CLK_SRC 242 -#define TSSC_CLK 243 -#define PDM_SRC 244 -#define PDM_CLK 245 -#define GP0_SRC 246 -#define GP0_CLK 247 -#define GP1_SRC 248 -#define GP1_CLK 249 -#define GP2_SRC 250 -#define GP2_CLK 251 -#define MPM_CLK 252 -#define EBI1_CLK_SRC 253 -#define EBI1_CH0_CLK 254 -#define EBI1_CH1_CLK 255 -#define EBI1_2X_CLK 256 -#define EBI1_CH0_DQ_CLK 257 -#define EBI1_CH1_DQ_CLK 258 -#define EBI1_CH0_CA_CLK 259 -#define EBI1_CH1_CA_CLK 260 -#define EBI1_XO_CLK 261 -#define SFAB_SMPSS_S_H_CLK 262 -#define PRNG_SRC 263 -#define PRNG_CLK 264 -#define PXO_SRC 265 -#define LPASS_CXO_CLK 266 -#define LPASS_PXO_CLK 267 -#define SPDM_CY_PORT0_CLK 268 -#define SPDM_CY_PORT1_CLK 269 -#define SPDM_CY_PORT2_CLK 270 -#define SPDM_CY_PORT3_CLK 271 -#define SPDM_CY_PORT4_CLK 272 -#define SPDM_CY_PORT5_CLK 273 -#define SPDM_CY_PORT6_CLK 274 -#define SPDM_CY_PORT7_CLK 275 -#define PLL0 276 -#define PLL0_VOTE 277 -#define PLL3 278 -#define PLL3_VOTE 279 -#define PLL4_VOTE 280 -#define PLL5 281 -#define PLL5_VOTE 282 -#define PLL6 283 -#define PLL6_VOTE 284 -#define PLL7_VOTE 285 -#define PLL8 286 -#define PLL8_VOTE 287 -#define PLL9 288 -#define PLL10 289 -#define PLL11 290 -#define PLL12 291 -#define PLL13 292 -#define PLL14 293 -#define PLL14_VOTE 294 -#define USB_HS3_H_CLK 295 -#define USB_HS3_XCVR_SRC 296 -#define USB_HS3_XCVR_CLK 297 -#define USB_HS4_H_CLK 298 -#define USB_HS4_XCVR_SRC 299 -#define USB_HS4_XCVR_CLK 300 -#define SATA_PHY_CFG_CLK 301 -#define SATA_A_CLK 302 -#define CE3_SRC 303 -#define CE3_CORE_CLK 304 -#define CE3_H_CLK 305 -#define PLL16 306 -#define PLL17 307 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-msm8974.h b/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-msm8974.h deleted file mode 100644 index 5c10570988e..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-msm8974.h +++ /dev/null @@ -1,319 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2013, The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_CLK_MSM_GCC_8974_H -#define _DT_BINDINGS_CLK_MSM_GCC_8974_H - -#define GPLL0 0 -#define GPLL0_VOTE 1 -#define CONFIG_NOC_CLK_SRC 2 -#define GPLL2 3 -#define GPLL2_VOTE 4 -#define GPLL3 5 -#define GPLL3_VOTE 6 -#define PERIPH_NOC_CLK_SRC 7 -#define BLSP_UART_SIM_CLK_SRC 8 -#define QDSS_TSCTR_CLK_SRC 9 -#define BIMC_DDR_CLK_SRC 10 -#define SYSTEM_NOC_CLK_SRC 11 -#define GPLL1 12 -#define GPLL1_VOTE 13 -#define RPM_CLK_SRC 14 -#define GCC_BIMC_CLK 15 -#define BIMC_DDR_CPLL0_ROOT_CLK_SRC 16 -#define KPSS_AHB_CLK_SRC 17 -#define QDSS_AT_CLK_SRC 18 -#define USB30_MASTER_CLK_SRC 19 -#define BIMC_DDR_CPLL1_ROOT_CLK_SRC 20 -#define QDSS_STM_CLK_SRC 21 -#define ACC_CLK_SRC 22 -#define SEC_CTRL_CLK_SRC 23 -#define BLSP1_QUP1_I2C_APPS_CLK_SRC 24 -#define BLSP1_QUP1_SPI_APPS_CLK_SRC 25 -#define BLSP1_QUP2_I2C_APPS_CLK_SRC 26 -#define BLSP1_QUP2_SPI_APPS_CLK_SRC 27 -#define BLSP1_QUP3_I2C_APPS_CLK_SRC 28 -#define BLSP1_QUP3_SPI_APPS_CLK_SRC 29 -#define BLSP1_QUP4_I2C_APPS_CLK_SRC 30 -#define BLSP1_QUP4_SPI_APPS_CLK_SRC 31 -#define BLSP1_QUP5_I2C_APPS_CLK_SRC 32 -#define BLSP1_QUP5_SPI_APPS_CLK_SRC 33 -#define BLSP1_QUP6_I2C_APPS_CLK_SRC 34 -#define BLSP1_QUP6_SPI_APPS_CLK_SRC 35 -#define BLSP1_UART1_APPS_CLK_SRC 36 -#define BLSP1_UART2_APPS_CLK_SRC 37 -#define BLSP1_UART3_APPS_CLK_SRC 38 -#define BLSP1_UART4_APPS_CLK_SRC 39 -#define BLSP1_UART5_APPS_CLK_SRC 40 -#define BLSP1_UART6_APPS_CLK_SRC 41 -#define BLSP2_QUP1_I2C_APPS_CLK_SRC 42 -#define BLSP2_QUP1_SPI_APPS_CLK_SRC 43 -#define BLSP2_QUP2_I2C_APPS_CLK_SRC 44 -#define BLSP2_QUP2_SPI_APPS_CLK_SRC 45 -#define BLSP2_QUP3_I2C_APPS_CLK_SRC 46 -#define BLSP2_QUP3_SPI_APPS_CLK_SRC 47 -#define BLSP2_QUP4_I2C_APPS_CLK_SRC 48 -#define BLSP2_QUP4_SPI_APPS_CLK_SRC 49 -#define BLSP2_QUP5_I2C_APPS_CLK_SRC 50 -#define BLSP2_QUP5_SPI_APPS_CLK_SRC 51 -#define BLSP2_QUP6_I2C_APPS_CLK_SRC 52 -#define BLSP2_QUP6_SPI_APPS_CLK_SRC 53 -#define BLSP2_UART1_APPS_CLK_SRC 54 -#define BLSP2_UART2_APPS_CLK_SRC 55 -#define BLSP2_UART3_APPS_CLK_SRC 56 -#define BLSP2_UART4_APPS_CLK_SRC 57 -#define BLSP2_UART5_APPS_CLK_SRC 58 -#define BLSP2_UART6_APPS_CLK_SRC 59 -#define CE1_CLK_SRC 60 -#define CE2_CLK_SRC 61 -#define GP1_CLK_SRC 62 -#define GP2_CLK_SRC 63 -#define GP3_CLK_SRC 64 -#define PDM2_CLK_SRC 65 -#define QDSS_TRACECLKIN_CLK_SRC 66 -#define RBCPR_CLK_SRC 67 -#define SDCC1_APPS_CLK_SRC 68 -#define SDCC2_APPS_CLK_SRC 69 -#define SDCC3_APPS_CLK_SRC 70 -#define SDCC4_APPS_CLK_SRC 71 -#define SPMI_AHB_CLK_SRC 72 -#define SPMI_SER_CLK_SRC 73 -#define TSIF_REF_CLK_SRC 74 -#define USB30_MOCK_UTMI_CLK_SRC 75 -#define USB_HS_SYSTEM_CLK_SRC 76 -#define USB_HSIC_CLK_SRC 77 -#define USB_HSIC_IO_CAL_CLK_SRC 78 -#define USB_HSIC_SYSTEM_CLK_SRC 79 -#define GCC_BAM_DMA_AHB_CLK 80 -#define GCC_BAM_DMA_INACTIVITY_TIMERS_CLK 81 -#define GCC_BIMC_CFG_AHB_CLK 82 -#define GCC_BIMC_KPSS_AXI_CLK 83 -#define GCC_BIMC_SLEEP_CLK 84 -#define GCC_BIMC_SYSNOC_AXI_CLK 85 -#define GCC_BIMC_XO_CLK 86 -#define GCC_BLSP1_AHB_CLK 87 -#define GCC_BLSP1_SLEEP_CLK 88 -#define GCC_BLSP1_QUP1_I2C_APPS_CLK 89 -#define GCC_BLSP1_QUP1_SPI_APPS_CLK 90 -#define GCC_BLSP1_QUP2_I2C_APPS_CLK 91 -#define GCC_BLSP1_QUP2_SPI_APPS_CLK 92 -#define GCC_BLSP1_QUP3_I2C_APPS_CLK 93 -#define GCC_BLSP1_QUP3_SPI_APPS_CLK 94 -#define GCC_BLSP1_QUP4_I2C_APPS_CLK 95 -#define GCC_BLSP1_QUP4_SPI_APPS_CLK 96 -#define GCC_BLSP1_QUP5_I2C_APPS_CLK 97 -#define GCC_BLSP1_QUP5_SPI_APPS_CLK 98 -#define GCC_BLSP1_QUP6_I2C_APPS_CLK 99 -#define GCC_BLSP1_QUP6_SPI_APPS_CLK 100 -#define GCC_BLSP1_UART1_APPS_CLK 101 -#define GCC_BLSP1_UART1_SIM_CLK 102 -#define GCC_BLSP1_UART2_APPS_CLK 103 -#define GCC_BLSP1_UART2_SIM_CLK 104 -#define GCC_BLSP1_UART3_APPS_CLK 105 -#define GCC_BLSP1_UART3_SIM_CLK 106 -#define GCC_BLSP1_UART4_APPS_CLK 107 -#define GCC_BLSP1_UART4_SIM_CLK 108 -#define GCC_BLSP1_UART5_APPS_CLK 109 -#define GCC_BLSP1_UART5_SIM_CLK 110 -#define GCC_BLSP1_UART6_APPS_CLK 111 -#define GCC_BLSP1_UART6_SIM_CLK 112 -#define GCC_BLSP2_AHB_CLK 113 -#define GCC_BLSP2_SLEEP_CLK 114 -#define GCC_BLSP2_QUP1_I2C_APPS_CLK 115 -#define GCC_BLSP2_QUP1_SPI_APPS_CLK 116 -#define GCC_BLSP2_QUP2_I2C_APPS_CLK 117 -#define GCC_BLSP2_QUP2_SPI_APPS_CLK 118 -#define GCC_BLSP2_QUP3_I2C_APPS_CLK 119 -#define GCC_BLSP2_QUP3_SPI_APPS_CLK 120 -#define GCC_BLSP2_QUP4_I2C_APPS_CLK 121 -#define GCC_BLSP2_QUP4_SPI_APPS_CLK 122 -#define GCC_BLSP2_QUP5_I2C_APPS_CLK 123 -#define GCC_BLSP2_QUP5_SPI_APPS_CLK 124 -#define GCC_BLSP2_QUP6_I2C_APPS_CLK 125 -#define GCC_BLSP2_QUP6_SPI_APPS_CLK 126 -#define GCC_BLSP2_UART1_APPS_CLK 127 -#define GCC_BLSP2_UART1_SIM_CLK 128 -#define GCC_BLSP2_UART2_APPS_CLK 129 -#define GCC_BLSP2_UART2_SIM_CLK 130 -#define GCC_BLSP2_UART3_APPS_CLK 131 -#define GCC_BLSP2_UART3_SIM_CLK 132 -#define GCC_BLSP2_UART4_APPS_CLK 133 -#define GCC_BLSP2_UART4_SIM_CLK 134 -#define GCC_BLSP2_UART5_APPS_CLK 135 -#define GCC_BLSP2_UART5_SIM_CLK 136 -#define GCC_BLSP2_UART6_APPS_CLK 137 -#define GCC_BLSP2_UART6_SIM_CLK 138 -#define GCC_BOOT_ROM_AHB_CLK 139 -#define GCC_CE1_AHB_CLK 140 -#define GCC_CE1_AXI_CLK 141 -#define GCC_CE1_CLK 142 -#define GCC_CE2_AHB_CLK 143 -#define GCC_CE2_AXI_CLK 144 -#define GCC_CE2_CLK 145 -#define GCC_CNOC_BUS_TIMEOUT0_AHB_CLK 146 -#define GCC_CNOC_BUS_TIMEOUT1_AHB_CLK 147 -#define GCC_CNOC_BUS_TIMEOUT2_AHB_CLK 148 -#define GCC_CNOC_BUS_TIMEOUT3_AHB_CLK 149 -#define GCC_CNOC_BUS_TIMEOUT4_AHB_CLK 150 -#define GCC_CNOC_BUS_TIMEOUT5_AHB_CLK 151 -#define GCC_CNOC_BUS_TIMEOUT6_AHB_CLK 152 -#define GCC_CFG_NOC_AHB_CLK 153 -#define GCC_CFG_NOC_DDR_CFG_CLK 154 -#define GCC_CFG_NOC_RPM_AHB_CLK 155 -#define GCC_BIMC_DDR_CPLL0_CLK 156 -#define GCC_BIMC_DDR_CPLL1_CLK 157 -#define GCC_DDR_DIM_CFG_CLK 158 -#define GCC_DDR_DIM_SLEEP_CLK 159 -#define GCC_DEHR_CLK 160 -#define GCC_AHB_CLK 161 -#define GCC_IM_SLEEP_CLK 162 -#define GCC_XO_CLK 163 -#define GCC_XO_DIV4_CLK 164 -#define GCC_GP1_CLK 165 -#define GCC_GP2_CLK 166 -#define GCC_GP3_CLK 167 -#define GCC_IMEM_AXI_CLK 168 -#define GCC_IMEM_CFG_AHB_CLK 169 -#define GCC_KPSS_AHB_CLK 170 -#define GCC_KPSS_AXI_CLK 171 -#define GCC_LPASS_Q6_AXI_CLK 172 -#define GCC_MMSS_NOC_AT_CLK 173 -#define GCC_MMSS_NOC_CFG_AHB_CLK 174 -#define GCC_OCMEM_NOC_CFG_AHB_CLK 175 -#define GCC_OCMEM_SYS_NOC_AXI_CLK 176 -#define GCC_MPM_AHB_CLK 177 -#define GCC_MSG_RAM_AHB_CLK 178 -#define GCC_MSS_CFG_AHB_CLK 179 -#define GCC_MSS_Q6_BIMC_AXI_CLK 180 -#define GCC_NOC_CONF_XPU_AHB_CLK 181 -#define GCC_PDM2_CLK 182 -#define GCC_PDM_AHB_CLK 183 -#define GCC_PDM_XO4_CLK 184 -#define GCC_PERIPH_NOC_AHB_CLK 185 -#define GCC_PERIPH_NOC_AT_CLK 186 -#define GCC_PERIPH_NOC_CFG_AHB_CLK 187 -#define GCC_PERIPH_NOC_MPU_CFG_AHB_CLK 188 -#define GCC_PERIPH_XPU_AHB_CLK 189 -#define GCC_PNOC_BUS_TIMEOUT0_AHB_CLK 190 -#define GCC_PNOC_BUS_TIMEOUT1_AHB_CLK 191 -#define GCC_PNOC_BUS_TIMEOUT2_AHB_CLK 192 -#define GCC_PNOC_BUS_TIMEOUT3_AHB_CLK 193 -#define GCC_PNOC_BUS_TIMEOUT4_AHB_CLK 194 -#define GCC_PRNG_AHB_CLK 195 -#define GCC_QDSS_AT_CLK 196 -#define GCC_QDSS_CFG_AHB_CLK 197 -#define GCC_QDSS_DAP_AHB_CLK 198 -#define GCC_QDSS_DAP_CLK 199 -#define GCC_QDSS_ETR_USB_CLK 200 -#define GCC_QDSS_STM_CLK 201 -#define GCC_QDSS_TRACECLKIN_CLK 202 -#define GCC_QDSS_TSCTR_DIV16_CLK 203 -#define GCC_QDSS_TSCTR_DIV2_CLK 204 -#define GCC_QDSS_TSCTR_DIV3_CLK 205 -#define GCC_QDSS_TSCTR_DIV4_CLK 206 -#define GCC_QDSS_TSCTR_DIV8_CLK 207 -#define GCC_QDSS_RBCPR_XPU_AHB_CLK 208 -#define GCC_RBCPR_AHB_CLK 209 -#define GCC_RBCPR_CLK 210 -#define GCC_RPM_BUS_AHB_CLK 211 -#define GCC_RPM_PROC_HCLK 212 -#define GCC_RPM_SLEEP_CLK 213 -#define GCC_RPM_TIMER_CLK 214 -#define GCC_SDCC1_AHB_CLK 215 -#define GCC_SDCC1_APPS_CLK 216 -#define GCC_SDCC1_INACTIVITY_TIMERS_CLK 217 -#define GCC_SDCC2_AHB_CLK 218 -#define GCC_SDCC2_APPS_CLK 219 -#define GCC_SDCC2_INACTIVITY_TIMERS_CLK 220 -#define GCC_SDCC3_AHB_CLK 221 -#define GCC_SDCC3_APPS_CLK 222 -#define GCC_SDCC3_INACTIVITY_TIMERS_CLK 223 -#define GCC_SDCC4_AHB_CLK 224 -#define GCC_SDCC4_APPS_CLK 225 -#define GCC_SDCC4_INACTIVITY_TIMERS_CLK 226 -#define GCC_SEC_CTRL_ACC_CLK 227 -#define GCC_SEC_CTRL_AHB_CLK 228 -#define GCC_SEC_CTRL_BOOT_ROM_PATCH_CLK 229 -#define GCC_SEC_CTRL_CLK 230 -#define GCC_SEC_CTRL_SENSE_CLK 231 -#define GCC_SNOC_BUS_TIMEOUT0_AHB_CLK 232 -#define GCC_SNOC_BUS_TIMEOUT2_AHB_CLK 233 -#define GCC_SPDM_BIMC_CY_CLK 234 -#define GCC_SPDM_CFG_AHB_CLK 235 -#define GCC_SPDM_DEBUG_CY_CLK 236 -#define GCC_SPDM_FF_CLK 237 -#define GCC_SPDM_MSTR_AHB_CLK 238 -#define GCC_SPDM_PNOC_CY_CLK 239 -#define GCC_SPDM_RPM_CY_CLK 240 -#define GCC_SPDM_SNOC_CY_CLK 241 -#define GCC_SPMI_AHB_CLK 242 -#define GCC_SPMI_CNOC_AHB_CLK 243 -#define GCC_SPMI_SER_CLK 244 -#define GCC_SNOC_CNOC_AHB_CLK 245 -#define GCC_SNOC_PNOC_AHB_CLK 246 -#define GCC_SYS_NOC_AT_CLK 247 -#define GCC_SYS_NOC_AXI_CLK 248 -#define GCC_SYS_NOC_KPSS_AHB_CLK 249 -#define GCC_SYS_NOC_QDSS_STM_AXI_CLK 250 -#define GCC_SYS_NOC_USB3_AXI_CLK 251 -#define GCC_TCSR_AHB_CLK 252 -#define GCC_TLMM_AHB_CLK 253 -#define GCC_TLMM_CLK 254 -#define GCC_TSIF_AHB_CLK 255 -#define GCC_TSIF_INACTIVITY_TIMERS_CLK 256 -#define GCC_TSIF_REF_CLK 257 -#define GCC_USB2A_PHY_SLEEP_CLK 258 -#define GCC_USB2B_PHY_SLEEP_CLK 259 -#define GCC_USB30_MASTER_CLK 260 -#define GCC_USB30_MOCK_UTMI_CLK 261 -#define GCC_USB30_SLEEP_CLK 262 -#define GCC_USB_HS_AHB_CLK 263 -#define GCC_USB_HS_INACTIVITY_TIMERS_CLK 264 -#define GCC_USB_HS_SYSTEM_CLK 265 -#define GCC_USB_HSIC_AHB_CLK 266 -#define GCC_USB_HSIC_CLK 267 -#define GCC_USB_HSIC_IO_CAL_CLK 268 -#define GCC_USB_HSIC_IO_CAL_SLEEP_CLK 269 -#define GCC_USB_HSIC_SYSTEM_CLK 270 -#define GCC_WCSS_GPLL1_CLK_SRC 271 -#define GCC_MMSS_GPLL0_CLK_SRC 272 -#define GCC_LPASS_GPLL0_CLK_SRC 273 -#define GCC_WCSS_GPLL1_CLK_SRC_SLEEP_ENA 274 -#define GCC_MMSS_GPLL0_CLK_SRC_SLEEP_ENA 275 -#define GCC_LPASS_GPLL0_CLK_SRC_SLEEP_ENA 276 -#define GCC_IMEM_AXI_CLK_SLEEP_ENA 277 -#define GCC_SYS_NOC_KPSS_AHB_CLK_SLEEP_ENA 278 -#define GCC_BIMC_KPSS_AXI_CLK_SLEEP_ENA 279 -#define GCC_KPSS_AHB_CLK_SLEEP_ENA 280 -#define GCC_KPSS_AXI_CLK_SLEEP_ENA 281 -#define GCC_MPM_AHB_CLK_SLEEP_ENA 282 -#define GCC_OCMEM_SYS_NOC_AXI_CLK_SLEEP_ENA 283 -#define GCC_BLSP1_AHB_CLK_SLEEP_ENA 284 -#define GCC_BLSP1_SLEEP_CLK_SLEEP_ENA 285 -#define GCC_BLSP2_AHB_CLK_SLEEP_ENA 286 -#define GCC_BLSP2_SLEEP_CLK_SLEEP_ENA 287 -#define GCC_PRNG_AHB_CLK_SLEEP_ENA 288 -#define GCC_BAM_DMA_AHB_CLK_SLEEP_ENA 289 -#define GCC_BAM_DMA_INACTIVITY_TIMERS_CLK_SLEEP_ENA 290 -#define GCC_BOOT_ROM_AHB_CLK_SLEEP_ENA 291 -#define GCC_MSG_RAM_AHB_CLK_SLEEP_ENA 292 -#define GCC_TLMM_AHB_CLK_SLEEP_ENA 293 -#define GCC_TLMM_CLK_SLEEP_ENA 294 -#define GCC_SPMI_CNOC_AHB_CLK_SLEEP_ENA 295 -#define GCC_CE1_CLK_SLEEP_ENA 296 -#define GCC_CE1_AXI_CLK_SLEEP_ENA 297 -#define GCC_CE1_AHB_CLK_SLEEP_ENA 298 -#define GCC_CE2_CLK_SLEEP_ENA 299 -#define GCC_CE2_AXI_CLK_SLEEP_ENA 300 -#define GCC_CE2_AHB_CLK_SLEEP_ENA 301 -#define GPLL4 302 -#define GPLL4_VOTE 303 -#define GCC_SDCC1_CDCCAL_SLEEP_CLK 304 -#define GCC_SDCC1_CDCCAL_FF_CLK 305 - -/* gdscs */ -#define USB_HS_HSIC_GDSC 0 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-msm8994.h b/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-msm8994.h deleted file mode 100644 index 938969309e0..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-msm8994.h +++ /dev/null @@ -1,130 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2016, The Linux Foundation. All rights reserved. - */ - - -#ifndef _DT_BINDINGS_CLK_MSM_GCC_8994_H -#define _DT_BINDINGS_CLK_MSM_GCC_8994_H - -#define GPLL0_EARLY 0 -#define GPLL0 1 -#define GPLL4_EARLY 2 -#define GPLL4 3 -#define UFS_AXI_CLK_SRC 4 -#define USB30_MASTER_CLK_SRC 5 -#define BLSP1_QUP1_I2C_APPS_CLK_SRC 6 -#define BLSP1_QUP1_SPI_APPS_CLK_SRC 7 -#define BLSP1_QUP2_I2C_APPS_CLK_SRC 8 -#define BLSP1_QUP2_SPI_APPS_CLK_SRC 9 -#define BLSP1_QUP3_I2C_APPS_CLK_SRC 10 -#define BLSP1_QUP3_SPI_APPS_CLK_SRC 11 -#define BLSP1_QUP4_I2C_APPS_CLK_SRC 12 -#define BLSP1_QUP4_SPI_APPS_CLK_SRC 13 -#define BLSP1_QUP5_I2C_APPS_CLK_SRC 14 -#define BLSP1_QUP5_SPI_APPS_CLK_SRC 15 -#define BLSP1_QUP6_I2C_APPS_CLK_SRC 16 -#define BLSP1_QUP6_SPI_APPS_CLK_SRC 17 -#define BLSP1_UART1_APPS_CLK_SRC 18 -#define BLSP1_UART2_APPS_CLK_SRC 19 -#define BLSP1_UART3_APPS_CLK_SRC 20 -#define BLSP1_UART4_APPS_CLK_SRC 21 -#define BLSP1_UART5_APPS_CLK_SRC 22 -#define BLSP1_UART6_APPS_CLK_SRC 23 -#define BLSP2_QUP1_I2C_APPS_CLK_SRC 24 -#define BLSP2_QUP1_SPI_APPS_CLK_SRC 25 -#define BLSP2_QUP2_I2C_APPS_CLK_SRC 26 -#define BLSP2_QUP2_SPI_APPS_CLK_SRC 27 -#define BLSP2_QUP3_I2C_APPS_CLK_SRC 28 -#define BLSP2_QUP3_SPI_APPS_CLK_SRC 29 -#define BLSP2_QUP4_I2C_APPS_CLK_SRC 30 -#define BLSP2_QUP4_SPI_APPS_CLK_SRC 31 -#define BLSP2_QUP5_I2C_APPS_CLK_SRC 32 -#define BLSP2_QUP5_SPI_APPS_CLK_SRC 33 -#define BLSP2_QUP6_I2C_APPS_CLK_SRC 34 -#define BLSP2_QUP6_SPI_APPS_CLK_SRC 35 -#define BLSP2_UART1_APPS_CLK_SRC 36 -#define BLSP2_UART2_APPS_CLK_SRC 37 -#define BLSP2_UART3_APPS_CLK_SRC 38 -#define BLSP2_UART4_APPS_CLK_SRC 39 -#define BLSP2_UART5_APPS_CLK_SRC 40 -#define BLSP2_UART6_APPS_CLK_SRC 41 -#define GP1_CLK_SRC 42 -#define GP2_CLK_SRC 43 -#define GP3_CLK_SRC 44 -#define PCIE_0_AUX_CLK_SRC 45 -#define PCIE_0_PIPE_CLK_SRC 46 -#define PCIE_1_AUX_CLK_SRC 47 -#define PCIE_1_PIPE_CLK_SRC 48 -#define PDM2_CLK_SRC 49 -#define SDCC1_APPS_CLK_SRC 50 -#define SDCC2_APPS_CLK_SRC 51 -#define SDCC3_APPS_CLK_SRC 52 -#define SDCC4_APPS_CLK_SRC 53 -#define TSIF_REF_CLK_SRC 54 -#define USB30_MOCK_UTMI_CLK_SRC 55 -#define USB3_PHY_AUX_CLK_SRC 56 -#define USB_HS_SYSTEM_CLK_SRC 57 -#define GCC_BLSP1_AHB_CLK 58 -#define GCC_BLSP1_QUP1_I2C_APPS_CLK 59 -#define GCC_BLSP1_QUP1_SPI_APPS_CLK 60 -#define GCC_BLSP1_QUP2_I2C_APPS_CLK 61 -#define GCC_BLSP1_QUP2_SPI_APPS_CLK 62 -#define GCC_BLSP1_QUP3_I2C_APPS_CLK 63 -#define GCC_BLSP1_QUP3_SPI_APPS_CLK 64 -#define GCC_BLSP1_QUP4_I2C_APPS_CLK 65 -#define GCC_BLSP1_QUP4_SPI_APPS_CLK 66 -#define GCC_BLSP1_QUP5_I2C_APPS_CLK 67 -#define GCC_BLSP1_QUP5_SPI_APPS_CLK 68 -#define GCC_BLSP1_QUP6_I2C_APPS_CLK 69 -#define GCC_BLSP1_QUP6_SPI_APPS_CLK 70 -#define GCC_BLSP1_UART1_APPS_CLK 71 -#define GCC_BLSP1_UART2_APPS_CLK 72 -#define GCC_BLSP1_UART3_APPS_CLK 73 -#define GCC_BLSP1_UART4_APPS_CLK 74 -#define GCC_BLSP1_UART5_APPS_CLK 75 -#define GCC_BLSP1_UART6_APPS_CLK 76 -#define GCC_BLSP2_AHB_CLK 77 -#define GCC_BLSP2_QUP1_I2C_APPS_CLK 78 -#define GCC_BLSP2_QUP1_SPI_APPS_CLK 79 -#define GCC_BLSP2_QUP2_I2C_APPS_CLK 80 -#define GCC_BLSP2_QUP2_SPI_APPS_CLK 81 -#define GCC_BLSP2_QUP3_I2C_APPS_CLK 82 -#define GCC_BLSP2_QUP3_SPI_APPS_CLK 83 -#define GCC_BLSP2_QUP4_I2C_APPS_CLK 84 -#define GCC_BLSP2_QUP4_SPI_APPS_CLK 85 -#define GCC_BLSP2_QUP5_I2C_APPS_CLK 86 -#define GCC_BLSP2_QUP5_SPI_APPS_CLK 87 -#define GCC_BLSP2_QUP6_I2C_APPS_CLK 88 -#define GCC_BLSP2_QUP6_SPI_APPS_CLK 89 -#define GCC_BLSP2_UART1_APPS_CLK 90 -#define GCC_BLSP2_UART2_APPS_CLK 91 -#define GCC_BLSP2_UART3_APPS_CLK 92 -#define GCC_BLSP2_UART4_APPS_CLK 93 -#define GCC_BLSP2_UART5_APPS_CLK 94 -#define GCC_BLSP2_UART6_APPS_CLK 95 -#define GCC_GP1_CLK 96 -#define GCC_GP2_CLK 97 -#define GCC_GP3_CLK 98 -#define GCC_PCIE_0_AUX_CLK 99 -#define GCC_PCIE_0_PIPE_CLK 100 -#define GCC_PCIE_1_AUX_CLK 101 -#define GCC_PCIE_1_PIPE_CLK 102 -#define GCC_PDM2_CLK 103 -#define GCC_SDCC1_APPS_CLK 104 -#define GCC_SDCC2_APPS_CLK 105 -#define GCC_SDCC3_APPS_CLK 106 -#define GCC_SDCC4_APPS_CLK 107 -#define GCC_SYS_NOC_UFS_AXI_CLK 108 -#define GCC_SYS_NOC_USB3_AXI_CLK 109 -#define GCC_TSIF_REF_CLK 110 -#define GCC_UFS_AXI_CLK 111 -#define GCC_UFS_RX_CFG_CLK 112 -#define GCC_UFS_TX_CFG_CLK 113 -#define GCC_USB30_MASTER_CLK 114 -#define GCC_USB30_MOCK_UTMI_CLK 115 -#define GCC_USB3_PHY_AUX_CLK 116 -#define GCC_USB_HS_SYSTEM_CLK 117 -#define GCC_SDCC1_AHB_CLK 118 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-msm8996.h b/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-msm8996.h deleted file mode 100644 index 03bf49d43d2..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-msm8996.h +++ /dev/null @@ -1,359 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2015, The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_CLK_MSM_GCC_8996_H -#define _DT_BINDINGS_CLK_MSM_GCC_8996_H - -#define GPLL0_EARLY 0 -#define GPLL0 1 -#define GPLL1_EARLY 2 -#define GPLL1 3 -#define GPLL2_EARLY 4 -#define GPLL2 5 -#define GPLL3_EARLY 6 -#define GPLL3 7 -#define GPLL4_EARLY 8 -#define GPLL4 9 -#define SYSTEM_NOC_CLK_SRC 10 -#define CONFIG_NOC_CLK_SRC 11 -#define PERIPH_NOC_CLK_SRC 12 -#define MMSS_BIMC_GFX_CLK_SRC 13 -#define USB30_MASTER_CLK_SRC 14 -#define USB30_MOCK_UTMI_CLK_SRC 15 -#define USB3_PHY_AUX_CLK_SRC 16 -#define USB20_MASTER_CLK_SRC 17 -#define USB20_MOCK_UTMI_CLK_SRC 18 -#define SDCC1_APPS_CLK_SRC 19 -#define SDCC1_ICE_CORE_CLK_SRC 20 -#define SDCC2_APPS_CLK_SRC 21 -#define SDCC3_APPS_CLK_SRC 22 -#define SDCC4_APPS_CLK_SRC 23 -#define BLSP1_QUP1_SPI_APPS_CLK_SRC 24 -#define BLSP1_QUP1_I2C_APPS_CLK_SRC 25 -#define BLSP1_UART1_APPS_CLK_SRC 26 -#define BLSP1_QUP2_SPI_APPS_CLK_SRC 27 -#define BLSP1_QUP2_I2C_APPS_CLK_SRC 28 -#define BLSP1_UART2_APPS_CLK_SRC 29 -#define BLSP1_QUP3_SPI_APPS_CLK_SRC 30 -#define BLSP1_QUP3_I2C_APPS_CLK_SRC 31 -#define BLSP1_UART3_APPS_CLK_SRC 32 -#define BLSP1_QUP4_SPI_APPS_CLK_SRC 33 -#define BLSP1_QUP4_I2C_APPS_CLK_SRC 34 -#define BLSP1_UART4_APPS_CLK_SRC 35 -#define BLSP1_QUP5_SPI_APPS_CLK_SRC 36 -#define BLSP1_QUP5_I2C_APPS_CLK_SRC 37 -#define BLSP1_UART5_APPS_CLK_SRC 38 -#define BLSP1_QUP6_SPI_APPS_CLK_SRC 39 -#define BLSP1_QUP6_I2C_APPS_CLK_SRC 40 -#define BLSP1_UART6_APPS_CLK_SRC 41 -#define BLSP2_QUP1_SPI_APPS_CLK_SRC 42 -#define BLSP2_QUP1_I2C_APPS_CLK_SRC 43 -#define BLSP2_UART1_APPS_CLK_SRC 44 -#define BLSP2_QUP2_SPI_APPS_CLK_SRC 45 -#define BLSP2_QUP2_I2C_APPS_CLK_SRC 46 -#define BLSP2_UART2_APPS_CLK_SRC 47 -#define BLSP2_QUP3_SPI_APPS_CLK_SRC 48 -#define BLSP2_QUP3_I2C_APPS_CLK_SRC 49 -#define BLSP2_UART3_APPS_CLK_SRC 50 -#define BLSP2_QUP4_SPI_APPS_CLK_SRC 51 -#define BLSP2_QUP4_I2C_APPS_CLK_SRC 52 -#define BLSP2_UART4_APPS_CLK_SRC 53 -#define BLSP2_QUP5_SPI_APPS_CLK_SRC 54 -#define BLSP2_QUP5_I2C_APPS_CLK_SRC 55 -#define BLSP2_UART5_APPS_CLK_SRC 56 -#define BLSP2_QUP6_SPI_APPS_CLK_SRC 57 -#define BLSP2_QUP6_I2C_APPS_CLK_SRC 58 -#define BLSP2_UART6_APPS_CLK_SRC 59 -#define PDM2_CLK_SRC 60 -#define TSIF_REF_CLK_SRC 61 -#define CE1_CLK_SRC 62 -#define GCC_SLEEP_CLK_SRC 63 -#define BIMC_CLK_SRC 64 -#define HMSS_AHB_CLK_SRC 65 -#define BIMC_HMSS_AXI_CLK_SRC 66 -#define HMSS_RBCPR_CLK_SRC 67 -#define HMSS_GPLL0_CLK_SRC 68 -#define GP1_CLK_SRC 69 -#define GP2_CLK_SRC 70 -#define GP3_CLK_SRC 71 -#define PCIE_AUX_CLK_SRC 72 -#define UFS_AXI_CLK_SRC 73 -#define UFS_ICE_CORE_CLK_SRC 74 -#define QSPI_SER_CLK_SRC 75 -#define GCC_SYS_NOC_AXI_CLK 76 -#define GCC_SYS_NOC_HMSS_AHB_CLK 77 -#define GCC_SNOC_CNOC_AHB_CLK 78 -#define GCC_SNOC_PNOC_AHB_CLK 79 -#define GCC_SYS_NOC_AT_CLK 80 -#define GCC_SYS_NOC_USB3_AXI_CLK 81 -#define GCC_SYS_NOC_UFS_AXI_CLK 82 -#define GCC_CFG_NOC_AHB_CLK 83 -#define GCC_PERIPH_NOC_AHB_CLK 84 -#define GCC_PERIPH_NOC_USB20_AHB_CLK 85 -#define GCC_TIC_CLK 86 -#define GCC_IMEM_AXI_CLK 87 -#define GCC_MMSS_SYS_NOC_AXI_CLK 88 -#define GCC_MMSS_NOC_CFG_AHB_CLK 89 -#define GCC_MMSS_BIMC_GFX_CLK 90 -#define GCC_USB30_MASTER_CLK 91 -#define GCC_USB30_SLEEP_CLK 92 -#define GCC_USB30_MOCK_UTMI_CLK 93 -#define GCC_USB3_PHY_AUX_CLK 94 -#define GCC_USB3_PHY_PIPE_CLK 95 -#define GCC_USB20_MASTER_CLK 96 -#define GCC_USB20_SLEEP_CLK 97 -#define GCC_USB20_MOCK_UTMI_CLK 98 -#define GCC_USB_PHY_CFG_AHB2PHY_CLK 99 -#define GCC_SDCC1_APPS_CLK 100 -#define GCC_SDCC1_AHB_CLK 101 -#define GCC_SDCC1_ICE_CORE_CLK 102 -#define GCC_SDCC2_APPS_CLK 103 -#define GCC_SDCC2_AHB_CLK 104 -#define GCC_SDCC3_APPS_CLK 105 -#define GCC_SDCC3_AHB_CLK 106 -#define GCC_SDCC4_APPS_CLK 107 -#define GCC_SDCC4_AHB_CLK 108 -#define GCC_BLSP1_AHB_CLK 109 -#define GCC_BLSP1_SLEEP_CLK 110 -#define GCC_BLSP1_QUP1_SPI_APPS_CLK 111 -#define GCC_BLSP1_QUP1_I2C_APPS_CLK 112 -#define GCC_BLSP1_UART1_APPS_CLK 113 -#define GCC_BLSP1_QUP2_SPI_APPS_CLK 114 -#define GCC_BLSP1_QUP2_I2C_APPS_CLK 115 -#define GCC_BLSP1_UART2_APPS_CLK 116 -#define GCC_BLSP1_QUP3_SPI_APPS_CLK 117 -#define GCC_BLSP1_QUP3_I2C_APPS_CLK 118 -#define GCC_BLSP1_UART3_APPS_CLK 119 -#define GCC_BLSP1_QUP4_SPI_APPS_CLK 120 -#define GCC_BLSP1_QUP4_I2C_APPS_CLK 121 -#define GCC_BLSP1_UART4_APPS_CLK 122 -#define GCC_BLSP1_QUP5_SPI_APPS_CLK 123 -#define GCC_BLSP1_QUP5_I2C_APPS_CLK 124 -#define GCC_BLSP1_UART5_APPS_CLK 125 -#define GCC_BLSP1_QUP6_SPI_APPS_CLK 126 -#define GCC_BLSP1_QUP6_I2C_APPS_CLK 127 -#define GCC_BLSP1_UART6_APPS_CLK 128 -#define GCC_BLSP2_AHB_CLK 129 -#define GCC_BLSP2_SLEEP_CLK 130 -#define GCC_BLSP2_QUP1_SPI_APPS_CLK 131 -#define GCC_BLSP2_QUP1_I2C_APPS_CLK 132 -#define GCC_BLSP2_UART1_APPS_CLK 133 -#define GCC_BLSP2_QUP2_SPI_APPS_CLK 134 -#define GCC_BLSP2_QUP2_I2C_APPS_CLK 135 -#define GCC_BLSP2_UART2_APPS_CLK 136 -#define GCC_BLSP2_QUP3_SPI_APPS_CLK 137 -#define GCC_BLSP2_QUP3_I2C_APPS_CLK 138 -#define GCC_BLSP2_UART3_APPS_CLK 139 -#define GCC_BLSP2_QUP4_SPI_APPS_CLK 140 -#define GCC_BLSP2_QUP4_I2C_APPS_CLK 141 -#define GCC_BLSP2_UART4_APPS_CLK 142 -#define GCC_BLSP2_QUP5_SPI_APPS_CLK 143 -#define GCC_BLSP2_QUP5_I2C_APPS_CLK 144 -#define GCC_BLSP2_UART5_APPS_CLK 145 -#define GCC_BLSP2_QUP6_SPI_APPS_CLK 146 -#define GCC_BLSP2_QUP6_I2C_APPS_CLK 147 -#define GCC_BLSP2_UART6_APPS_CLK 148 -#define GCC_PDM_AHB_CLK 149 -#define GCC_PDM_XO4_CLK 150 -#define GCC_PDM2_CLK 151 -#define GCC_PRNG_AHB_CLK 152 -#define GCC_TSIF_AHB_CLK 153 -#define GCC_TSIF_REF_CLK 154 -#define GCC_TSIF_INACTIVITY_TIMERS_CLK 155 -#define GCC_TCSR_AHB_CLK 156 -#define GCC_BOOT_ROM_AHB_CLK 157 -#define GCC_MSG_RAM_AHB_CLK 158 -#define GCC_TLMM_AHB_CLK 159 -#define GCC_TLMM_CLK 160 -#define GCC_MPM_AHB_CLK 161 -#define GCC_SPMI_SER_CLK 162 -#define GCC_SPMI_CNOC_AHB_CLK 163 -#define GCC_CE1_CLK 164 -#define GCC_CE1_AXI_CLK 165 -#define GCC_CE1_AHB_CLK 166 -#define GCC_BIMC_HMSS_AXI_CLK 167 -#define GCC_BIMC_GFX_CLK 168 -#define GCC_HMSS_AHB_CLK 169 -#define GCC_HMSS_SLV_AXI_CLK 170 -#define GCC_HMSS_MSTR_AXI_CLK 171 -#define GCC_HMSS_RBCPR_CLK 172 -#define GCC_GP1_CLK 173 -#define GCC_GP2_CLK 174 -#define GCC_GP3_CLK 175 -#define GCC_PCIE_0_SLV_AXI_CLK 176 -#define GCC_PCIE_0_MSTR_AXI_CLK 177 -#define GCC_PCIE_0_CFG_AHB_CLK 178 -#define GCC_PCIE_0_AUX_CLK 179 -#define GCC_PCIE_0_PIPE_CLK 180 -#define GCC_PCIE_1_SLV_AXI_CLK 181 -#define GCC_PCIE_1_MSTR_AXI_CLK 182 -#define GCC_PCIE_1_CFG_AHB_CLK 183 -#define GCC_PCIE_1_AUX_CLK 184 -#define GCC_PCIE_1_PIPE_CLK 185 -#define GCC_PCIE_2_SLV_AXI_CLK 186 -#define GCC_PCIE_2_MSTR_AXI_CLK 187 -#define GCC_PCIE_2_CFG_AHB_CLK 188 -#define GCC_PCIE_2_AUX_CLK 189 -#define GCC_PCIE_2_PIPE_CLK 190 -#define GCC_PCIE_PHY_CFG_AHB_CLK 191 -#define GCC_PCIE_PHY_AUX_CLK 192 -#define GCC_UFS_AXI_CLK 193 -#define GCC_UFS_AHB_CLK 194 -#define GCC_UFS_TX_CFG_CLK 195 -#define GCC_UFS_RX_CFG_CLK 196 -#define GCC_UFS_TX_SYMBOL_0_CLK 197 -#define GCC_UFS_RX_SYMBOL_0_CLK 198 -#define GCC_UFS_RX_SYMBOL_1_CLK 199 -#define GCC_UFS_UNIPRO_CORE_CLK 200 -#define GCC_UFS_ICE_CORE_CLK 201 -#define GCC_UFS_SYS_CLK_CORE_CLK 202 -#define GCC_UFS_TX_SYMBOL_CLK_CORE_CLK 203 -#define GCC_AGGRE0_SNOC_AXI_CLK 204 -#define GCC_AGGRE0_CNOC_AHB_CLK 205 -#define GCC_SMMU_AGGRE0_AXI_CLK 206 -#define GCC_SMMU_AGGRE0_AHB_CLK 207 -#define GCC_AGGRE1_PNOC_AHB_CLK 208 -#define GCC_AGGRE2_UFS_AXI_CLK 209 -#define GCC_AGGRE2_USB3_AXI_CLK 210 -#define GCC_QSPI_AHB_CLK 211 -#define GCC_QSPI_SER_CLK 212 -#define GCC_USB3_CLKREF_CLK 213 -#define GCC_HDMI_CLKREF_CLK 214 -#define GCC_UFS_CLKREF_CLK 215 -#define GCC_PCIE_CLKREF_CLK 216 -#define GCC_RX2_USB2_CLKREF_CLK 217 -#define GCC_RX1_USB2_CLKREF_CLK 218 -#define GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK 219 -#define GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK 220 -#define GCC_EDP_CLKREF_CLK 221 -#define GCC_MSS_CFG_AHB_CLK 222 -#define GCC_MSS_Q6_BIMC_AXI_CLK 223 -#define GCC_MSS_SNOC_AXI_CLK 224 -#define GCC_MSS_MNOC_BIMC_AXI_CLK 225 -#define GCC_DCC_AHB_CLK 226 -#define GCC_AGGRE0_NOC_MPU_CFG_AHB_CLK 227 -#define GCC_MMSS_GPLL0_DIV_CLK 228 -#define GCC_MSS_GPLL0_DIV_CLK 229 - -#define GCC_SYSTEM_NOC_BCR 0 -#define GCC_CONFIG_NOC_BCR 1 -#define GCC_PERIPH_NOC_BCR 2 -#define GCC_IMEM_BCR 3 -#define GCC_MMSS_BCR 4 -#define GCC_PIMEM_BCR 5 -#define GCC_QDSS_BCR 6 -#define GCC_USB_30_BCR 7 -#define GCC_USB_20_BCR 8 -#define GCC_QUSB2PHY_PRIM_BCR 9 -#define GCC_QUSB2PHY_SEC_BCR 10 -#define GCC_USB_PHY_CFG_AHB2PHY_BCR 11 -#define GCC_SDCC1_BCR 12 -#define GCC_SDCC2_BCR 13 -#define GCC_SDCC3_BCR 14 -#define GCC_SDCC4_BCR 15 -#define GCC_BLSP1_BCR 16 -#define GCC_BLSP1_QUP1_BCR 17 -#define GCC_BLSP1_UART1_BCR 18 -#define GCC_BLSP1_QUP2_BCR 19 -#define GCC_BLSP1_UART2_BCR 20 -#define GCC_BLSP1_QUP3_BCR 21 -#define GCC_BLSP1_UART3_BCR 22 -#define GCC_BLSP1_QUP4_BCR 23 -#define GCC_BLSP1_UART4_BCR 24 -#define GCC_BLSP1_QUP5_BCR 25 -#define GCC_BLSP1_UART5_BCR 26 -#define GCC_BLSP1_QUP6_BCR 27 -#define GCC_BLSP1_UART6_BCR 28 -#define GCC_BLSP2_BCR 29 -#define GCC_BLSP2_QUP1_BCR 30 -#define GCC_BLSP2_UART1_BCR 31 -#define GCC_BLSP2_QUP2_BCR 32 -#define GCC_BLSP2_UART2_BCR 33 -#define GCC_BLSP2_QUP3_BCR 34 -#define GCC_BLSP2_UART3_BCR 35 -#define GCC_BLSP2_QUP4_BCR 36 -#define GCC_BLSP2_UART4_BCR 37 -#define GCC_BLSP2_QUP5_BCR 38 -#define GCC_BLSP2_UART5_BCR 39 -#define GCC_BLSP2_QUP6_BCR 40 -#define GCC_BLSP2_UART6_BCR 41 -#define GCC_PDM_BCR 42 -#define GCC_PRNG_BCR 43 -#define GCC_TSIF_BCR 44 -#define GCC_TCSR_BCR 45 -#define GCC_BOOT_ROM_BCR 46 -#define GCC_MSG_RAM_BCR 47 -#define GCC_TLMM_BCR 48 -#define GCC_MPM_BCR 49 -#define GCC_SEC_CTRL_BCR 50 -#define GCC_SPMI_BCR 51 -#define GCC_SPDM_BCR 52 -#define GCC_CE1_BCR 53 -#define GCC_BIMC_BCR 54 -#define GCC_SNOC_BUS_TIMEOUT0_BCR 55 -#define GCC_SNOC_BUS_TIMEOUT2_BCR 56 -#define GCC_SNOC_BUS_TIMEOUT1_BCR 57 -#define GCC_SNOC_BUS_TIMEOUT3_BCR 58 -#define GCC_SNOC_BUS_TIMEOUT_EXTREF_BCR 59 -#define GCC_PNOC_BUS_TIMEOUT0_BCR 60 -#define GCC_PNOC_BUS_TIMEOUT1_BCR 61 -#define GCC_PNOC_BUS_TIMEOUT2_BCR 62 -#define GCC_PNOC_BUS_TIMEOUT3_BCR 63 -#define GCC_PNOC_BUS_TIMEOUT4_BCR 64 -#define GCC_CNOC_BUS_TIMEOUT0_BCR 65 -#define GCC_CNOC_BUS_TIMEOUT1_BCR 66 -#define GCC_CNOC_BUS_TIMEOUT2_BCR 67 -#define GCC_CNOC_BUS_TIMEOUT3_BCR 68 -#define GCC_CNOC_BUS_TIMEOUT4_BCR 69 -#define GCC_CNOC_BUS_TIMEOUT5_BCR 70 -#define GCC_CNOC_BUS_TIMEOUT6_BCR 71 -#define GCC_CNOC_BUS_TIMEOUT7_BCR 72 -#define GCC_CNOC_BUS_TIMEOUT8_BCR 73 -#define GCC_CNOC_BUS_TIMEOUT9_BCR 74 -#define GCC_CNOC_BUS_TIMEOUT_EXTREF_BCR 75 -#define GCC_APB2JTAG_BCR 76 -#define GCC_RBCPR_CX_BCR 77 -#define GCC_RBCPR_MX_BCR 78 -#define GCC_PCIE_0_BCR 79 -#define GCC_PCIE_0_PHY_BCR 80 -#define GCC_PCIE_1_BCR 81 -#define GCC_PCIE_1_PHY_BCR 82 -#define GCC_PCIE_2_BCR 83 -#define GCC_PCIE_2_PHY_BCR 84 -#define GCC_PCIE_PHY_BCR 85 -#define GCC_DCD_BCR 86 -#define GCC_OBT_ODT_BCR 87 -#define GCC_UFS_BCR 88 -#define GCC_SSC_BCR 89 -#define GCC_VS_BCR 90 -#define GCC_AGGRE0_NOC_BCR 91 -#define GCC_AGGRE1_NOC_BCR 92 -#define GCC_AGGRE2_NOC_BCR 93 -#define GCC_DCC_BCR 94 -#define GCC_IPA_BCR 95 -#define GCC_QSPI_BCR 96 -#define GCC_SKL_BCR 97 -#define GCC_MSMPU_BCR 98 -#define GCC_MSS_Q6_BCR 99 -#define GCC_QREFS_VBG_CAL_BCR 100 -#define GCC_PCIE_PHY_COM_BCR 101 -#define GCC_PCIE_PHY_COM_NOCSR_BCR 102 -#define GCC_USB3_PHY_BCR 103 -#define GCC_USB3PHY_PHY_BCR 104 -#define GCC_MSS_RESTART 105 - - -/* Indexes for GDSCs */ -#define AGGRE0_NOC_GDSC 0 -#define HLOS1_VOTE_AGGRE0_NOC_GDSC 1 -#define HLOS1_VOTE_LPASS_ADSP_GDSC 2 -#define HLOS1_VOTE_LPASS_CORE_GDSC 3 -#define USB30_GDSC 4 -#define PCIE0_GDSC 5 -#define PCIE1_GDSC 6 -#define PCIE2_GDSC 7 -#define UFS_GDSC 8 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-msm8998.h b/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-msm8998.h deleted file mode 100644 index 63e02dc32a0..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-msm8998.h +++ /dev/null @@ -1,301 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2016, The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_CLK_MSM_GCC_COBALT_H -#define _DT_BINDINGS_CLK_MSM_GCC_COBALT_H - -#define BLSP1_QUP1_I2C_APPS_CLK_SRC 0 -#define BLSP1_QUP1_SPI_APPS_CLK_SRC 1 -#define BLSP1_QUP2_I2C_APPS_CLK_SRC 2 -#define BLSP1_QUP2_SPI_APPS_CLK_SRC 3 -#define BLSP1_QUP3_I2C_APPS_CLK_SRC 4 -#define BLSP1_QUP3_SPI_APPS_CLK_SRC 5 -#define BLSP1_QUP4_I2C_APPS_CLK_SRC 6 -#define BLSP1_QUP4_SPI_APPS_CLK_SRC 7 -#define BLSP1_QUP5_I2C_APPS_CLK_SRC 8 -#define BLSP1_QUP5_SPI_APPS_CLK_SRC 9 -#define BLSP1_QUP6_I2C_APPS_CLK_SRC 10 -#define BLSP1_QUP6_SPI_APPS_CLK_SRC 11 -#define BLSP1_UART1_APPS_CLK_SRC 12 -#define BLSP1_UART2_APPS_CLK_SRC 13 -#define BLSP1_UART3_APPS_CLK_SRC 14 -#define BLSP2_QUP1_I2C_APPS_CLK_SRC 15 -#define BLSP2_QUP1_SPI_APPS_CLK_SRC 16 -#define BLSP2_QUP2_I2C_APPS_CLK_SRC 17 -#define BLSP2_QUP2_SPI_APPS_CLK_SRC 18 -#define BLSP2_QUP3_I2C_APPS_CLK_SRC 19 -#define BLSP2_QUP3_SPI_APPS_CLK_SRC 20 -#define BLSP2_QUP4_I2C_APPS_CLK_SRC 21 -#define BLSP2_QUP4_SPI_APPS_CLK_SRC 22 -#define BLSP2_QUP5_I2C_APPS_CLK_SRC 23 -#define BLSP2_QUP5_SPI_APPS_CLK_SRC 24 -#define BLSP2_QUP6_I2C_APPS_CLK_SRC 25 -#define BLSP2_QUP6_SPI_APPS_CLK_SRC 26 -#define BLSP2_UART1_APPS_CLK_SRC 27 -#define BLSP2_UART2_APPS_CLK_SRC 28 -#define BLSP2_UART3_APPS_CLK_SRC 29 -#define GCC_AGGRE1_NOC_XO_CLK 30 -#define GCC_AGGRE1_UFS_AXI_CLK 31 -#define GCC_AGGRE1_USB3_AXI_CLK 32 -#define GCC_APSS_QDSS_TSCTR_DIV2_CLK 33 -#define GCC_APSS_QDSS_TSCTR_DIV8_CLK 34 -#define GCC_BIMC_HMSS_AXI_CLK 35 -#define GCC_BIMC_MSS_Q6_AXI_CLK 36 -#define GCC_BLSP1_AHB_CLK 37 -#define GCC_BLSP1_QUP1_I2C_APPS_CLK 38 -#define GCC_BLSP1_QUP1_SPI_APPS_CLK 39 -#define GCC_BLSP1_QUP2_I2C_APPS_CLK 40 -#define GCC_BLSP1_QUP2_SPI_APPS_CLK 41 -#define GCC_BLSP1_QUP3_I2C_APPS_CLK 42 -#define GCC_BLSP1_QUP3_SPI_APPS_CLK 43 -#define GCC_BLSP1_QUP4_I2C_APPS_CLK 44 -#define GCC_BLSP1_QUP4_SPI_APPS_CLK 45 -#define GCC_BLSP1_QUP5_I2C_APPS_CLK 46 -#define GCC_BLSP1_QUP5_SPI_APPS_CLK 47 -#define GCC_BLSP1_QUP6_I2C_APPS_CLK 48 -#define GCC_BLSP1_QUP6_SPI_APPS_CLK 49 -#define GCC_BLSP1_SLEEP_CLK 50 -#define GCC_BLSP1_UART1_APPS_CLK 51 -#define GCC_BLSP1_UART2_APPS_CLK 52 -#define GCC_BLSP1_UART3_APPS_CLK 53 -#define GCC_BLSP2_AHB_CLK 54 -#define GCC_BLSP2_QUP1_I2C_APPS_CLK 55 -#define GCC_BLSP2_QUP1_SPI_APPS_CLK 56 -#define GCC_BLSP2_QUP2_I2C_APPS_CLK 57 -#define GCC_BLSP2_QUP2_SPI_APPS_CLK 58 -#define GCC_BLSP2_QUP3_I2C_APPS_CLK 59 -#define GCC_BLSP2_QUP3_SPI_APPS_CLK 60 -#define GCC_BLSP2_QUP4_I2C_APPS_CLK 61 -#define GCC_BLSP2_QUP4_SPI_APPS_CLK 62 -#define GCC_BLSP2_QUP5_I2C_APPS_CLK 63 -#define GCC_BLSP2_QUP5_SPI_APPS_CLK 64 -#define GCC_BLSP2_QUP6_I2C_APPS_CLK 65 -#define GCC_BLSP2_QUP6_SPI_APPS_CLK 66 -#define GCC_BLSP2_SLEEP_CLK 67 -#define GCC_BLSP2_UART1_APPS_CLK 68 -#define GCC_BLSP2_UART2_APPS_CLK 69 -#define GCC_BLSP2_UART3_APPS_CLK 70 -#define GCC_CFG_NOC_USB3_AXI_CLK 71 -#define GCC_GP1_CLK 72 -#define GCC_GP2_CLK 73 -#define GCC_GP3_CLK 74 -#define GCC_GPU_BIMC_GFX_CLK 75 -#define GCC_GPU_BIMC_GFX_SRC_CLK 76 -#define GCC_GPU_CFG_AHB_CLK 77 -#define GCC_GPU_SNOC_DVM_GFX_CLK 78 -#define GCC_HMSS_AHB_CLK 79 -#define GCC_HMSS_AT_CLK 80 -#define GCC_HMSS_DVM_BUS_CLK 81 -#define GCC_HMSS_RBCPR_CLK 82 -#define GCC_HMSS_TRIG_CLK 83 -#define GCC_LPASS_AT_CLK 84 -#define GCC_LPASS_TRIG_CLK 85 -#define GCC_MMSS_NOC_CFG_AHB_CLK 86 -#define GCC_MMSS_QM_AHB_CLK 87 -#define GCC_MMSS_QM_CORE_CLK 88 -#define GCC_MMSS_SYS_NOC_AXI_CLK 89 -#define GCC_MSS_AT_CLK 90 -#define GCC_PCIE_0_AUX_CLK 91 -#define GCC_PCIE_0_CFG_AHB_CLK 92 -#define GCC_PCIE_0_MSTR_AXI_CLK 93 -#define GCC_PCIE_0_PIPE_CLK 94 -#define GCC_PCIE_0_SLV_AXI_CLK 95 -#define GCC_PCIE_PHY_AUX_CLK 96 -#define GCC_PDM2_CLK 97 -#define GCC_PDM_AHB_CLK 98 -#define GCC_PDM_XO4_CLK 99 -#define GCC_PRNG_AHB_CLK 100 -#define GCC_SDCC2_AHB_CLK 101 -#define GCC_SDCC2_APPS_CLK 102 -#define GCC_SDCC4_AHB_CLK 103 -#define GCC_SDCC4_APPS_CLK 104 -#define GCC_TSIF_AHB_CLK 105 -#define GCC_TSIF_INACTIVITY_TIMERS_CLK 106 -#define GCC_TSIF_REF_CLK 107 -#define GCC_UFS_AHB_CLK 108 -#define GCC_UFS_AXI_CLK 109 -#define GCC_UFS_ICE_CORE_CLK 110 -#define GCC_UFS_PHY_AUX_CLK 111 -#define GCC_UFS_RX_SYMBOL_0_CLK 112 -#define GCC_UFS_RX_SYMBOL_1_CLK 113 -#define GCC_UFS_TX_SYMBOL_0_CLK 114 -#define GCC_UFS_UNIPRO_CORE_CLK 115 -#define GCC_USB30_MASTER_CLK 116 -#define GCC_USB30_MOCK_UTMI_CLK 117 -#define GCC_USB30_SLEEP_CLK 118 -#define GCC_USB3_PHY_AUX_CLK 119 -#define GCC_USB3_PHY_PIPE_CLK 120 -#define GCC_USB_PHY_CFG_AHB2PHY_CLK 121 -#define GP1_CLK_SRC 122 -#define GP2_CLK_SRC 123 -#define GP3_CLK_SRC 124 -#define GPLL0 125 -#define GPLL0_OUT_EVEN 126 -#define GPLL0_OUT_MAIN 127 -#define GPLL0_OUT_ODD 128 -#define GPLL0_OUT_TEST 129 -#define GPLL1 130 -#define GPLL1_OUT_EVEN 131 -#define GPLL1_OUT_MAIN 132 -#define GPLL1_OUT_ODD 133 -#define GPLL1_OUT_TEST 134 -#define GPLL2 135 -#define GPLL2_OUT_EVEN 136 -#define GPLL2_OUT_MAIN 137 -#define GPLL2_OUT_ODD 138 -#define GPLL2_OUT_TEST 139 -#define GPLL3 140 -#define GPLL3_OUT_EVEN 141 -#define GPLL3_OUT_MAIN 142 -#define GPLL3_OUT_ODD 143 -#define GPLL3_OUT_TEST 144 -#define GPLL4 145 -#define GPLL4_OUT_EVEN 146 -#define GPLL4_OUT_MAIN 147 -#define GPLL4_OUT_ODD 148 -#define GPLL4_OUT_TEST 149 -#define GPLL6 150 -#define GPLL6_OUT_EVEN 151 -#define GPLL6_OUT_MAIN 152 -#define GPLL6_OUT_ODD 153 -#define GPLL6_OUT_TEST 154 -#define HMSS_AHB_CLK_SRC 155 -#define HMSS_RBCPR_CLK_SRC 156 -#define PCIE_AUX_CLK_SRC 157 -#define PDM2_CLK_SRC 158 -#define SDCC2_APPS_CLK_SRC 159 -#define SDCC4_APPS_CLK_SRC 160 -#define TSIF_REF_CLK_SRC 161 -#define UFS_AXI_CLK_SRC 162 -#define USB30_MASTER_CLK_SRC 163 -#define USB30_MOCK_UTMI_CLK_SRC 164 -#define USB3_PHY_AUX_CLK_SRC 165 -#define GCC_USB3_CLKREF_CLK 166 -#define GCC_HDMI_CLKREF_CLK 167 -#define GCC_UFS_CLKREF_CLK 168 -#define GCC_PCIE_CLKREF_CLK 169 -#define GCC_RX1_USB2_CLKREF_CLK 170 -#define GCC_MSS_CFG_AHB_CLK 171 -#define GCC_BOOT_ROM_AHB_CLK 172 -#define GCC_MSS_GPLL0_DIV_CLK_SRC 173 -#define GCC_MSS_SNOC_AXI_CLK 174 -#define GCC_MSS_MNOC_BIMC_AXI_CLK 175 -#define GCC_BIMC_GFX_CLK 176 - -#define PCIE_0_GDSC 0 -#define UFS_GDSC 1 -#define USB_30_GDSC 2 - -#define GCC_BLSP1_QUP1_BCR 0 -#define GCC_BLSP1_QUP2_BCR 1 -#define GCC_BLSP1_QUP3_BCR 2 -#define GCC_BLSP1_QUP4_BCR 3 -#define GCC_BLSP1_QUP5_BCR 4 -#define GCC_BLSP1_QUP6_BCR 5 -#define GCC_BLSP2_QUP1_BCR 6 -#define GCC_BLSP2_QUP2_BCR 7 -#define GCC_BLSP2_QUP3_BCR 8 -#define GCC_BLSP2_QUP4_BCR 9 -#define GCC_BLSP2_QUP5_BCR 10 -#define GCC_BLSP2_QUP6_BCR 11 -#define GCC_PCIE_0_BCR 12 -#define GCC_PDM_BCR 13 -#define GCC_SDCC2_BCR 14 -#define GCC_SDCC4_BCR 15 -#define GCC_TSIF_BCR 16 -#define GCC_UFS_BCR 17 -#define GCC_USB_30_BCR 18 -#define GCC_SYSTEM_NOC_BCR 19 -#define GCC_CONFIG_NOC_BCR 20 -#define GCC_AHB2PHY_EAST_BCR 21 -#define GCC_IMEM_BCR 22 -#define GCC_PIMEM_BCR 23 -#define GCC_MMSS_BCR 24 -#define GCC_QDSS_BCR 25 -#define GCC_WCSS_BCR 26 -#define GCC_BLSP1_BCR 27 -#define GCC_BLSP1_UART1_BCR 28 -#define GCC_BLSP1_UART2_BCR 29 -#define GCC_BLSP1_UART3_BCR 30 -#define GCC_CM_PHY_REFGEN1_BCR 31 -#define GCC_CM_PHY_REFGEN2_BCR 32 -#define GCC_BLSP2_BCR 33 -#define GCC_BLSP2_UART1_BCR 34 -#define GCC_BLSP2_UART2_BCR 35 -#define GCC_BLSP2_UART3_BCR 36 -#define GCC_SRAM_SENSOR_BCR 37 -#define GCC_PRNG_BCR 38 -#define GCC_TSIF_0_RESET 39 -#define GCC_TSIF_1_RESET 40 -#define GCC_TCSR_BCR 41 -#define GCC_BOOT_ROM_BCR 42 -#define GCC_MSG_RAM_BCR 43 -#define GCC_TLMM_BCR 44 -#define GCC_MPM_BCR 45 -#define GCC_SEC_CTRL_BCR 46 -#define GCC_SPMI_BCR 47 -#define GCC_SPDM_BCR 48 -#define GCC_CE1_BCR 49 -#define GCC_BIMC_BCR 50 -#define GCC_SNOC_BUS_TIMEOUT0_BCR 51 -#define GCC_SNOC_BUS_TIMEOUT1_BCR 52 -#define GCC_SNOC_BUS_TIMEOUT3_BCR 53 -#define GCC_SNOC_BUS_TIMEOUT_EXTREF_BCR 54 -#define GCC_PNOC_BUS_TIMEOUT0_BCR 55 -#define GCC_CNOC_PERIPH_BUS_TIMEOUT1_BCR 56 -#define GCC_CNOC_PERIPH_BUS_TIMEOUT2_BCR 57 -#define GCC_CNOC_BUS_TIMEOUT0_BCR 58 -#define GCC_CNOC_BUS_TIMEOUT1_BCR 59 -#define GCC_CNOC_BUS_TIMEOUT2_BCR 60 -#define GCC_CNOC_BUS_TIMEOUT3_BCR 61 -#define GCC_CNOC_BUS_TIMEOUT4_BCR 62 -#define GCC_CNOC_BUS_TIMEOUT5_BCR 63 -#define GCC_CNOC_BUS_TIMEOUT6_BCR 64 -#define GCC_CNOC_BUS_TIMEOUT7_BCR 65 -#define GCC_APB2JTAG_BCR 66 -#define GCC_RBCPR_CX_BCR 67 -#define GCC_RBCPR_MX_BCR 68 -#define GCC_USB3_PHY_BCR 69 -#define GCC_USB3PHY_PHY_BCR 70 -#define GCC_USB3_DP_PHY_BCR 71 -#define GCC_SSC_BCR 72 -#define GCC_SSC_RESET 73 -#define GCC_USB_PHY_CFG_AHB2PHY_BCR 74 -#define GCC_PCIE_0_LINK_DOWN_BCR 75 -#define GCC_PCIE_0_PHY_BCR 76 -#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 77 -#define GCC_PCIE_PHY_BCR 78 -#define GCC_PCIE_PHY_NOCSR_COM_PHY_BCR 79 -#define GCC_PCIE_PHY_CFG_AHB_BCR 80 -#define GCC_PCIE_PHY_COM_BCR 81 -#define GCC_GPU_BCR 82 -#define GCC_SPSS_BCR 83 -#define GCC_OBT_ODT_BCR 84 -#define GCC_VS_BCR 85 -#define GCC_MSS_VS_RESET 86 -#define GCC_GPU_VS_RESET 87 -#define GCC_APC0_VS_RESET 88 -#define GCC_APC1_VS_RESET 89 -#define GCC_CNOC_BUS_TIMEOUT8_BCR 90 -#define GCC_CNOC_BUS_TIMEOUT9_BCR 91 -#define GCC_CNOC_BUS_TIMEOUT10_BCR 92 -#define GCC_CNOC_BUS_TIMEOUT11_BCR 93 -#define GCC_CNOC_BUS_TIMEOUT12_BCR 94 -#define GCC_CNOC_BUS_TIMEOUT13_BCR 95 -#define GCC_CNOC_BUS_TIMEOUT14_BCR 96 -#define GCC_CNOC_BUS_TIMEOUT_EXTREF_BCR 97 -#define GCC_AGGRE1_NOC_BCR 98 -#define GCC_AGGRE2_NOC_BCR 99 -#define GCC_DCC_BCR 100 -#define GCC_QREFS_VBG_CAL_BCR 101 -#define GCC_IPA_BCR 102 -#define GCC_GLM_BCR 103 -#define GCC_SKL_BCR 104 -#define GCC_MSMPU_BCR 105 -#define GCC_QUSB2PHY_PRIM_BCR 106 -#define GCC_QUSB2PHY_SEC_BCR 107 -#define GCC_MSS_RESTART 108 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-qcs404.h b/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-qcs404.h deleted file mode 100644 index bc305154334..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-qcs404.h +++ /dev/null @@ -1,180 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_CLK_QCOM_GCC_QCS404_H -#define _DT_BINDINGS_CLK_QCOM_GCC_QCS404_H - -#define GCC_APSS_AHB_CLK_SRC 0 -#define GCC_BLSP1_QUP0_I2C_APPS_CLK_SRC 1 -#define GCC_BLSP1_QUP0_SPI_APPS_CLK_SRC 2 -#define GCC_BLSP1_QUP1_I2C_APPS_CLK_SRC 3 -#define GCC_BLSP1_QUP1_SPI_APPS_CLK_SRC 4 -#define GCC_BLSP1_QUP2_I2C_APPS_CLK_SRC 5 -#define GCC_BLSP1_QUP2_SPI_APPS_CLK_SRC 6 -#define GCC_BLSP1_QUP3_I2C_APPS_CLK_SRC 7 -#define GCC_BLSP1_QUP3_SPI_APPS_CLK_SRC 8 -#define GCC_BLSP1_QUP4_I2C_APPS_CLK_SRC 9 -#define GCC_BLSP1_QUP4_SPI_APPS_CLK_SRC 10 -#define GCC_BLSP1_UART0_APPS_CLK_SRC 11 -#define GCC_BLSP1_UART1_APPS_CLK_SRC 12 -#define GCC_BLSP1_UART2_APPS_CLK_SRC 13 -#define GCC_BLSP1_UART3_APPS_CLK_SRC 14 -#define GCC_BLSP2_QUP0_I2C_APPS_CLK_SRC 15 -#define GCC_BLSP2_QUP0_SPI_APPS_CLK_SRC 16 -#define GCC_BLSP2_UART0_APPS_CLK_SRC 17 -#define GCC_BYTE0_CLK_SRC 18 -#define GCC_EMAC_CLK_SRC 19 -#define GCC_EMAC_PTP_CLK_SRC 20 -#define GCC_ESC0_CLK_SRC 21 -#define GCC_APSS_AHB_CLK 22 -#define GCC_APSS_AXI_CLK 23 -#define GCC_BIMC_APSS_AXI_CLK 24 -#define GCC_BIMC_GFX_CLK 25 -#define GCC_BIMC_MDSS_CLK 26 -#define GCC_BLSP1_AHB_CLK 27 -#define GCC_BLSP1_QUP0_I2C_APPS_CLK 28 -#define GCC_BLSP1_QUP0_SPI_APPS_CLK 29 -#define GCC_BLSP1_QUP1_I2C_APPS_CLK 30 -#define GCC_BLSP1_QUP1_SPI_APPS_CLK 31 -#define GCC_BLSP1_QUP2_I2C_APPS_CLK 32 -#define GCC_BLSP1_QUP2_SPI_APPS_CLK 33 -#define GCC_BLSP1_QUP3_I2C_APPS_CLK 34 -#define GCC_BLSP1_QUP3_SPI_APPS_CLK 35 -#define GCC_BLSP1_QUP4_I2C_APPS_CLK 36 -#define GCC_BLSP1_QUP4_SPI_APPS_CLK 37 -#define GCC_BLSP1_UART0_APPS_CLK 38 -#define GCC_BLSP1_UART1_APPS_CLK 39 -#define GCC_BLSP1_UART2_APPS_CLK 40 -#define GCC_BLSP1_UART3_APPS_CLK 41 -#define GCC_BLSP2_AHB_CLK 42 -#define GCC_BLSP2_QUP0_I2C_APPS_CLK 43 -#define GCC_BLSP2_QUP0_SPI_APPS_CLK 44 -#define GCC_BLSP2_UART0_APPS_CLK 45 -#define GCC_BOOT_ROM_AHB_CLK 46 -#define GCC_DCC_CLK 47 -#define GCC_GENI_IR_H_CLK 48 -#define GCC_ETH_AXI_CLK 49 -#define GCC_ETH_PTP_CLK 50 -#define GCC_ETH_RGMII_CLK 51 -#define GCC_ETH_SLAVE_AHB_CLK 52 -#define GCC_GENI_IR_S_CLK 53 -#define GCC_GP1_CLK 54 -#define GCC_GP2_CLK 55 -#define GCC_GP3_CLK 56 -#define GCC_MDSS_AHB_CLK 57 -#define GCC_MDSS_AXI_CLK 58 -#define GCC_MDSS_BYTE0_CLK 59 -#define GCC_MDSS_ESC0_CLK 60 -#define GCC_MDSS_HDMI_APP_CLK 61 -#define GCC_MDSS_HDMI_PCLK_CLK 62 -#define GCC_MDSS_MDP_CLK 63 -#define GCC_MDSS_PCLK0_CLK 64 -#define GCC_MDSS_VSYNC_CLK 65 -#define GCC_OXILI_AHB_CLK 66 -#define GCC_OXILI_GFX3D_CLK 67 -#define GCC_PCIE_0_AUX_CLK 68 -#define GCC_PCIE_0_CFG_AHB_CLK 69 -#define GCC_PCIE_0_MSTR_AXI_CLK 70 -#define GCC_PCIE_0_PIPE_CLK 71 -#define GCC_PCIE_0_SLV_AXI_CLK 72 -#define GCC_PCNOC_USB2_CLK 73 -#define GCC_PCNOC_USB3_CLK 74 -#define GCC_PDM2_CLK 75 -#define GCC_PDM_AHB_CLK 76 -#define GCC_VSYNC_CLK_SRC 77 -#define GCC_PRNG_AHB_CLK 78 -#define GCC_PWM0_XO512_CLK 79 -#define GCC_PWM1_XO512_CLK 80 -#define GCC_PWM2_XO512_CLK 81 -#define GCC_SDCC1_AHB_CLK 82 -#define GCC_SDCC1_APPS_CLK 83 -#define GCC_SDCC1_ICE_CORE_CLK 84 -#define GCC_SDCC2_AHB_CLK 85 -#define GCC_SDCC2_APPS_CLK 86 -#define GCC_SYS_NOC_USB3_CLK 87 -#define GCC_USB20_MOCK_UTMI_CLK 88 -#define GCC_USB2A_PHY_SLEEP_CLK 89 -#define GCC_USB30_MASTER_CLK 90 -#define GCC_USB30_MOCK_UTMI_CLK 91 -#define GCC_USB30_SLEEP_CLK 92 -#define GCC_USB3_PHY_AUX_CLK 93 -#define GCC_USB3_PHY_PIPE_CLK 94 -#define GCC_USB_HS_PHY_CFG_AHB_CLK 95 -#define GCC_USB_HS_SYSTEM_CLK 96 -#define GCC_GFX3D_CLK_SRC 97 -#define GCC_GP1_CLK_SRC 98 -#define GCC_GP2_CLK_SRC 99 -#define GCC_GP3_CLK_SRC 100 -#define GCC_GPLL0_OUT_MAIN 101 -#define GCC_GPLL1_OUT_MAIN 102 -#define GCC_GPLL3_OUT_MAIN 103 -#define GCC_GPLL4_OUT_MAIN 104 -#define GCC_HDMI_APP_CLK_SRC 105 -#define GCC_HDMI_PCLK_CLK_SRC 106 -#define GCC_MDP_CLK_SRC 107 -#define GCC_PCIE_0_AUX_CLK_SRC 108 -#define GCC_PCIE_0_PIPE_CLK_SRC 109 -#define GCC_PCLK0_CLK_SRC 110 -#define GCC_PDM2_CLK_SRC 111 -#define GCC_SDCC1_APPS_CLK_SRC 112 -#define GCC_SDCC1_ICE_CORE_CLK_SRC 113 -#define GCC_SDCC2_APPS_CLK_SRC 114 -#define GCC_USB20_MOCK_UTMI_CLK_SRC 115 -#define GCC_USB30_MASTER_CLK_SRC 116 -#define GCC_USB30_MOCK_UTMI_CLK_SRC 117 -#define GCC_USB3_PHY_AUX_CLK_SRC 118 -#define GCC_USB_HS_SYSTEM_CLK_SRC 119 -#define GCC_GPLL0_AO_CLK_SRC 120 -#define GCC_USB_HS_INACTIVITY_TIMERS_CLK 122 -#define GCC_GPLL0_AO_OUT_MAIN 123 -#define GCC_GPLL0_SLEEP_CLK_SRC 124 -#define GCC_GPLL6 125 -#define GCC_GPLL6_OUT_AUX 126 -#define GCC_MDSS_MDP_VOTE_CLK 127 -#define GCC_MDSS_ROTATOR_VOTE_CLK 128 -#define GCC_BIMC_GPU_CLK 129 -#define GCC_GTCU_AHB_CLK 130 -#define GCC_GFX_TCU_CLK 131 -#define GCC_GFX_TBU_CLK 132 -#define GCC_SMMU_CFG_CLK 133 -#define GCC_APSS_TCU_CLK 134 -#define GCC_CRYPTO_AHB_CLK 135 -#define GCC_CRYPTO_AXI_CLK 136 -#define GCC_CRYPTO_CLK 137 -#define GCC_MDP_TBU_CLK 138 -#define GCC_QDSS_DAP_CLK 139 -#define GCC_DCC_XO_CLK 140 -#define GCC_WCSS_Q6_AHB_CLK 141 -#define GCC_WCSS_Q6_AXIM_CLK 142 -#define GCC_CDSP_CFG_AHB_CLK 143 -#define GCC_BIMC_CDSP_CLK 144 -#define GCC_CDSP_TBU_CLK 145 -#define GCC_CDSP_BIMC_CLK_SRC 146 - -#define GCC_GENI_IR_BCR 0 -#define GCC_USB_HS_BCR 1 -#define GCC_USB2_HS_PHY_ONLY_BCR 2 -#define GCC_QUSB2_PHY_BCR 3 -#define GCC_USB_HS_PHY_CFG_AHB_BCR 4 -#define GCC_USB2A_PHY_BCR 5 -#define GCC_USB3_PHY_BCR 6 -#define GCC_USB_30_BCR 7 -#define GCC_USB3PHY_PHY_BCR 8 -#define GCC_PCIE_0_BCR 9 -#define GCC_PCIE_0_PHY_BCR 10 -#define GCC_PCIE_0_LINK_DOWN_BCR 11 -#define GCC_PCIEPHY_0_PHY_BCR 12 -#define GCC_EMAC_BCR 13 -#define GCC_CDSP_RESTART 14 -#define GCC_PCIE_0_AXI_MASTER_STICKY_ARES 15 -#define GCC_PCIE_0_AHB_ARES 16 -#define GCC_PCIE_0_AXI_SLAVE_ARES 17 -#define GCC_PCIE_0_AXI_MASTER_ARES 18 -#define GCC_PCIE_0_CORE_STICKY_ARES 19 -#define GCC_PCIE_0_SLEEP_ARES 20 -#define GCC_PCIE_0_PIPE_ARES 21 -#define GCC_WDSP_RESTART 22 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-sc7180.h b/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-sc7180.h deleted file mode 100644 index e8029b2e92d..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-sc7180.h +++ /dev/null @@ -1,155 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SC7180_H -#define _DT_BINDINGS_CLK_QCOM_GCC_SC7180_H - -/* GCC clocks */ -#define GCC_GPLL0_MAIN_DIV_CDIV 0 -#define GPLL0 1 -#define GPLL0_OUT_EVEN 2 -#define GPLL1 3 -#define GPLL4 4 -#define GPLL6 5 -#define GPLL7 6 -#define GCC_AGGRE_UFS_PHY_AXI_CLK 7 -#define GCC_AGGRE_USB3_PRIM_AXI_CLK 8 -#define GCC_BOOT_ROM_AHB_CLK 9 -#define GCC_CAMERA_AHB_CLK 10 -#define GCC_CAMERA_HF_AXI_CLK 11 -#define GCC_CAMERA_THROTTLE_HF_AXI_CLK 12 -#define GCC_CAMERA_XO_CLK 13 -#define GCC_CE1_AHB_CLK 14 -#define GCC_CE1_AXI_CLK 15 -#define GCC_CE1_CLK 16 -#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 17 -#define GCC_CPUSS_AHB_CLK 18 -#define GCC_CPUSS_AHB_CLK_SRC 19 -#define GCC_CPUSS_GNOC_CLK 20 -#define GCC_CPUSS_RBCPR_CLK 21 -#define GCC_DDRSS_GPU_AXI_CLK 22 -#define GCC_DISP_AHB_CLK 23 -#define GCC_DISP_GPLL0_CLK_SRC 24 -#define GCC_DISP_GPLL0_DIV_CLK_SRC 25 -#define GCC_DISP_HF_AXI_CLK 26 -#define GCC_DISP_THROTTLE_HF_AXI_CLK 27 -#define GCC_DISP_XO_CLK 28 -#define GCC_GP1_CLK 29 -#define GCC_GP1_CLK_SRC 30 -#define GCC_GP2_CLK 31 -#define GCC_GP2_CLK_SRC 32 -#define GCC_GP3_CLK 33 -#define GCC_GP3_CLK_SRC 34 -#define GCC_GPU_CFG_AHB_CLK 35 -#define GCC_GPU_GPLL0_CLK_SRC 36 -#define GCC_GPU_GPLL0_DIV_CLK_SRC 37 -#define GCC_GPU_MEMNOC_GFX_CLK 38 -#define GCC_GPU_SNOC_DVM_GFX_CLK 39 -#define GCC_NPU_AXI_CLK 40 -#define GCC_NPU_BWMON_AXI_CLK 41 -#define GCC_NPU_BWMON_DMA_CFG_AHB_CLK 42 -#define GCC_NPU_BWMON_DSP_CFG_AHB_CLK 43 -#define GCC_NPU_CFG_AHB_CLK 44 -#define GCC_NPU_DMA_CLK 45 -#define GCC_NPU_GPLL0_CLK_SRC 46 -#define GCC_NPU_GPLL0_DIV_CLK_SRC 47 -#define GCC_PDM2_CLK 48 -#define GCC_PDM2_CLK_SRC 49 -#define GCC_PDM_AHB_CLK 50 -#define GCC_PDM_XO4_CLK 51 -#define GCC_PRNG_AHB_CLK 52 -#define GCC_QSPI_CNOC_PERIPH_AHB_CLK 53 -#define GCC_QSPI_CORE_CLK 54 -#define GCC_QSPI_CORE_CLK_SRC 55 -#define GCC_QUPV3_WRAP0_CORE_2X_CLK 56 -#define GCC_QUPV3_WRAP0_CORE_CLK 57 -#define GCC_QUPV3_WRAP0_S0_CLK 58 -#define GCC_QUPV3_WRAP0_S0_CLK_SRC 59 -#define GCC_QUPV3_WRAP0_S1_CLK 60 -#define GCC_QUPV3_WRAP0_S1_CLK_SRC 61 -#define GCC_QUPV3_WRAP0_S2_CLK 62 -#define GCC_QUPV3_WRAP0_S2_CLK_SRC 63 -#define GCC_QUPV3_WRAP0_S3_CLK 64 -#define GCC_QUPV3_WRAP0_S3_CLK_SRC 65 -#define GCC_QUPV3_WRAP0_S4_CLK 66 -#define GCC_QUPV3_WRAP0_S4_CLK_SRC 67 -#define GCC_QUPV3_WRAP0_S5_CLK 68 -#define GCC_QUPV3_WRAP0_S5_CLK_SRC 69 -#define GCC_QUPV3_WRAP1_CORE_2X_CLK 70 -#define GCC_QUPV3_WRAP1_CORE_CLK 71 -#define GCC_QUPV3_WRAP1_S0_CLK 72 -#define GCC_QUPV3_WRAP1_S0_CLK_SRC 73 -#define GCC_QUPV3_WRAP1_S1_CLK 74 -#define GCC_QUPV3_WRAP1_S1_CLK_SRC 75 -#define GCC_QUPV3_WRAP1_S2_CLK 76 -#define GCC_QUPV3_WRAP1_S2_CLK_SRC 77 -#define GCC_QUPV3_WRAP1_S3_CLK 78 -#define GCC_QUPV3_WRAP1_S3_CLK_SRC 79 -#define GCC_QUPV3_WRAP1_S4_CLK 80 -#define GCC_QUPV3_WRAP1_S4_CLK_SRC 81 -#define GCC_QUPV3_WRAP1_S5_CLK 82 -#define GCC_QUPV3_WRAP1_S5_CLK_SRC 83 -#define GCC_QUPV3_WRAP_0_M_AHB_CLK 84 -#define GCC_QUPV3_WRAP_0_S_AHB_CLK 85 -#define GCC_QUPV3_WRAP_1_M_AHB_CLK 86 -#define GCC_QUPV3_WRAP_1_S_AHB_CLK 87 -#define GCC_SDCC1_AHB_CLK 88 -#define GCC_SDCC1_APPS_CLK 89 -#define GCC_SDCC1_APPS_CLK_SRC 90 -#define GCC_SDCC1_ICE_CORE_CLK 91 -#define GCC_SDCC1_ICE_CORE_CLK_SRC 92 -#define GCC_SDCC2_AHB_CLK 93 -#define GCC_SDCC2_APPS_CLK 94 -#define GCC_SDCC2_APPS_CLK_SRC 95 -#define GCC_SYS_NOC_CPUSS_AHB_CLK 96 -#define GCC_UFS_MEM_CLKREF_CLK 97 -#define GCC_UFS_PHY_AHB_CLK 98 -#define GCC_UFS_PHY_AXI_CLK 99 -#define GCC_UFS_PHY_AXI_CLK_SRC 100 -#define GCC_UFS_PHY_ICE_CORE_CLK 101 -#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 102 -#define GCC_UFS_PHY_PHY_AUX_CLK 103 -#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 104 -#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 105 -#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 106 -#define GCC_UFS_PHY_UNIPRO_CORE_CLK 107 -#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 108 -#define GCC_USB30_PRIM_MASTER_CLK 109 -#define GCC_USB30_PRIM_MASTER_CLK_SRC 110 -#define GCC_USB30_PRIM_MOCK_UTMI_CLK 111 -#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 112 -#define GCC_USB30_PRIM_SLEEP_CLK 113 -#define GCC_USB3_PRIM_CLKREF_CLK 114 -#define GCC_USB3_PRIM_PHY_AUX_CLK 115 -#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 116 -#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 117 -#define GCC_USB3_PRIM_PHY_PIPE_CLK 118 -#define GCC_USB_PHY_CFG_AHB2PHY_CLK 119 -#define GCC_VIDEO_AHB_CLK 120 -#define GCC_VIDEO_AXI_CLK 121 -#define GCC_VIDEO_GPLL0_DIV_CLK_SRC 122 -#define GCC_VIDEO_THROTTLE_AXI_CLK 123 -#define GCC_VIDEO_XO_CLK 124 - -/* GCC resets */ -#define GCC_QUSB2PHY_PRIM_BCR 0 -#define GCC_QUSB2PHY_SEC_BCR 1 -#define GCC_UFS_PHY_BCR 2 -#define GCC_USB30_PRIM_BCR 3 -#define GCC_USB3_DP_PHY_PRIM_BCR 4 -#define GCC_USB3_DP_PHY_SEC_BCR 5 -#define GCC_USB3_PHY_PRIM_BCR 6 -#define GCC_USB3_PHY_SEC_BCR 7 -#define GCC_USB3PHY_PHY_PRIM_BCR 8 -#define GCC_USB3PHY_PHY_SEC_BCR 9 -#define GCC_USB_PHY_CFG_AHB2PHY_BCR 10 - -/* GCC GDSCRs */ -#define UFS_PHY_GDSC 0 -#define USB30_PRIM_GDSC 1 -#define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC 2 -#define HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC 3 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-sdm660.h b/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-sdm660.h deleted file mode 100644 index 46830228291..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-sdm660.h +++ /dev/null @@ -1,156 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. - * Copyright (c) 2018, Craig Tatlor. - */ - -#ifndef _DT_BINDINGS_CLK_MSM_GCC_660_H -#define _DT_BINDINGS_CLK_MSM_GCC_660_H - -#define BLSP1_QUP1_I2C_APPS_CLK_SRC 0 -#define BLSP1_QUP1_SPI_APPS_CLK_SRC 1 -#define BLSP1_QUP2_I2C_APPS_CLK_SRC 2 -#define BLSP1_QUP2_SPI_APPS_CLK_SRC 3 -#define BLSP1_QUP3_I2C_APPS_CLK_SRC 4 -#define BLSP1_QUP3_SPI_APPS_CLK_SRC 5 -#define BLSP1_QUP4_I2C_APPS_CLK_SRC 6 -#define BLSP1_QUP4_SPI_APPS_CLK_SRC 7 -#define BLSP1_UART1_APPS_CLK_SRC 8 -#define BLSP1_UART2_APPS_CLK_SRC 9 -#define BLSP2_QUP1_I2C_APPS_CLK_SRC 10 -#define BLSP2_QUP1_SPI_APPS_CLK_SRC 11 -#define BLSP2_QUP2_I2C_APPS_CLK_SRC 12 -#define BLSP2_QUP2_SPI_APPS_CLK_SRC 13 -#define BLSP2_QUP3_I2C_APPS_CLK_SRC 14 -#define BLSP2_QUP3_SPI_APPS_CLK_SRC 15 -#define BLSP2_QUP4_I2C_APPS_CLK_SRC 16 -#define BLSP2_QUP4_SPI_APPS_CLK_SRC 17 -#define BLSP2_UART1_APPS_CLK_SRC 18 -#define BLSP2_UART2_APPS_CLK_SRC 19 -#define GCC_AGGRE2_UFS_AXI_CLK 20 -#define GCC_AGGRE2_USB3_AXI_CLK 21 -#define GCC_BIMC_GFX_CLK 22 -#define GCC_BIMC_HMSS_AXI_CLK 23 -#define GCC_BIMC_MSS_Q6_AXI_CLK 24 -#define GCC_BLSP1_AHB_CLK 25 -#define GCC_BLSP1_QUP1_I2C_APPS_CLK 26 -#define GCC_BLSP1_QUP1_SPI_APPS_CLK 27 -#define GCC_BLSP1_QUP2_I2C_APPS_CLK 28 -#define GCC_BLSP1_QUP2_SPI_APPS_CLK 29 -#define GCC_BLSP1_QUP3_I2C_APPS_CLK 30 -#define GCC_BLSP1_QUP3_SPI_APPS_CLK 31 -#define GCC_BLSP1_QUP4_I2C_APPS_CLK 32 -#define GCC_BLSP1_QUP4_SPI_APPS_CLK 33 -#define GCC_BLSP1_UART1_APPS_CLK 34 -#define GCC_BLSP1_UART2_APPS_CLK 35 -#define GCC_BLSP2_AHB_CLK 36 -#define GCC_BLSP2_QUP1_I2C_APPS_CLK 37 -#define GCC_BLSP2_QUP1_SPI_APPS_CLK 38 -#define GCC_BLSP2_QUP2_I2C_APPS_CLK 39 -#define GCC_BLSP2_QUP2_SPI_APPS_CLK 40 -#define GCC_BLSP2_QUP3_I2C_APPS_CLK 41 -#define GCC_BLSP2_QUP3_SPI_APPS_CLK 42 -#define GCC_BLSP2_QUP4_I2C_APPS_CLK 43 -#define GCC_BLSP2_QUP4_SPI_APPS_CLK 44 -#define GCC_BLSP2_UART1_APPS_CLK 45 -#define GCC_BLSP2_UART2_APPS_CLK 46 -#define GCC_BOOT_ROM_AHB_CLK 47 -#define GCC_CFG_NOC_USB2_AXI_CLK 48 -#define GCC_CFG_NOC_USB3_AXI_CLK 49 -#define GCC_DCC_AHB_CLK 50 -#define GCC_GP1_CLK 51 -#define GCC_GP2_CLK 52 -#define GCC_GP3_CLK 53 -#define GCC_GPU_BIMC_GFX_CLK 54 -#define GCC_GPU_CFG_AHB_CLK 55 -#define GCC_GPU_GPLL0_CLK 56 -#define GCC_GPU_GPLL0_DIV_CLK 57 -#define GCC_HMSS_DVM_BUS_CLK 58 -#define GCC_HMSS_RBCPR_CLK 59 -#define GCC_MMSS_GPLL0_CLK 60 -#define GCC_MMSS_GPLL0_DIV_CLK 61 -#define GCC_MMSS_NOC_CFG_AHB_CLK 62 -#define GCC_MMSS_SYS_NOC_AXI_CLK 63 -#define GCC_MSS_CFG_AHB_CLK 64 -#define GCC_MSS_GPLL0_DIV_CLK 65 -#define GCC_MSS_MNOC_BIMC_AXI_CLK 66 -#define GCC_MSS_Q6_BIMC_AXI_CLK 67 -#define GCC_MSS_SNOC_AXI_CLK 68 -#define GCC_PDM2_CLK 69 -#define GCC_PDM_AHB_CLK 70 -#define GCC_PRNG_AHB_CLK 71 -#define GCC_QSPI_AHB_CLK 72 -#define GCC_QSPI_SER_CLK 73 -#define GCC_SDCC1_AHB_CLK 74 -#define GCC_SDCC1_APPS_CLK 75 -#define GCC_SDCC1_ICE_CORE_CLK 76 -#define GCC_SDCC2_AHB_CLK 77 -#define GCC_SDCC2_APPS_CLK 78 -#define GCC_UFS_AHB_CLK 79 -#define GCC_UFS_AXI_CLK 80 -#define GCC_UFS_CLKREF_CLK 81 -#define GCC_UFS_ICE_CORE_CLK 82 -#define GCC_UFS_PHY_AUX_CLK 83 -#define GCC_UFS_RX_SYMBOL_0_CLK 84 -#define GCC_UFS_RX_SYMBOL_1_CLK 85 -#define GCC_UFS_TX_SYMBOL_0_CLK 86 -#define GCC_UFS_UNIPRO_CORE_CLK 87 -#define GCC_USB20_MASTER_CLK 88 -#define GCC_USB20_MOCK_UTMI_CLK 89 -#define GCC_USB20_SLEEP_CLK 90 -#define GCC_USB30_MASTER_CLK 91 -#define GCC_USB30_MOCK_UTMI_CLK 92 -#define GCC_USB30_SLEEP_CLK 93 -#define GCC_USB3_CLKREF_CLK 94 -#define GCC_USB3_PHY_AUX_CLK 95 -#define GCC_USB3_PHY_PIPE_CLK 96 -#define GCC_USB_PHY_CFG_AHB2PHY_CLK 97 -#define GP1_CLK_SRC 98 -#define GP2_CLK_SRC 99 -#define GP3_CLK_SRC 100 -#define GPLL0 101 -#define GPLL0_EARLY 102 -#define GPLL1 103 -#define GPLL1_EARLY 104 -#define GPLL4 105 -#define GPLL4_EARLY 106 -#define HMSS_GPLL0_CLK_SRC 107 -#define HMSS_GPLL4_CLK_SRC 108 -#define HMSS_RBCPR_CLK_SRC 109 -#define PDM2_CLK_SRC 110 -#define QSPI_SER_CLK_SRC 111 -#define SDCC1_APPS_CLK_SRC 112 -#define SDCC1_ICE_CORE_CLK_SRC 113 -#define SDCC2_APPS_CLK_SRC 114 -#define UFS_AXI_CLK_SRC 115 -#define UFS_ICE_CORE_CLK_SRC 116 -#define UFS_PHY_AUX_CLK_SRC 117 -#define UFS_UNIPRO_CORE_CLK_SRC 118 -#define USB20_MASTER_CLK_SRC 119 -#define USB20_MOCK_UTMI_CLK_SRC 120 -#define USB30_MASTER_CLK_SRC 121 -#define USB30_MOCK_UTMI_CLK_SRC 122 -#define USB3_PHY_AUX_CLK_SRC 123 -#define GPLL0_OUT_MSSCC 124 -#define GCC_UFS_AXI_HW_CTL_CLK 125 -#define GCC_UFS_ICE_CORE_HW_CTL_CLK 126 -#define GCC_UFS_PHY_AUX_HW_CTL_CLK 127 -#define GCC_UFS_UNIPRO_CORE_HW_CTL_CLK 128 -#define GCC_RX0_USB2_CLKREF_CLK 129 -#define GCC_RX1_USB2_CLKREF_CLK 130 - -#define PCIE_0_GDSC 0 -#define UFS_GDSC 1 -#define USB_30_GDSC 2 - -#define GCC_QUSB2PHY_PRIM_BCR 0 -#define GCC_QUSB2PHY_SEC_BCR 1 -#define GCC_UFS_BCR 2 -#define GCC_USB3_DP_PHY_BCR 3 -#define GCC_USB3_PHY_BCR 4 -#define GCC_USB3PHY_PHY_BCR 5 -#define GCC_USB_20_BCR 6 -#define GCC_USB_30_BCR 7 -#define GCC_USB_PHY_CFG_AHB2PHY_BCR 8 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-sdm845.h b/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-sdm845.h deleted file mode 100644 index 968fa65b9c4..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-sdm845.h +++ /dev/null @@ -1,246 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_CLK_SDM_GCC_SDM845_H -#define _DT_BINDINGS_CLK_SDM_GCC_SDM845_H - -/* GCC clock registers */ -#define GCC_AGGRE_NOC_PCIE_TBU_CLK 0 -#define GCC_AGGRE_UFS_CARD_AXI_CLK 1 -#define GCC_AGGRE_UFS_PHY_AXI_CLK 2 -#define GCC_AGGRE_USB3_PRIM_AXI_CLK 3 -#define GCC_AGGRE_USB3_SEC_AXI_CLK 4 -#define GCC_BOOT_ROM_AHB_CLK 5 -#define GCC_CAMERA_AHB_CLK 6 -#define GCC_CAMERA_AXI_CLK 7 -#define GCC_CAMERA_XO_CLK 8 -#define GCC_CE1_AHB_CLK 9 -#define GCC_CE1_AXI_CLK 10 -#define GCC_CE1_CLK 11 -#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 12 -#define GCC_CFG_NOC_USB3_SEC_AXI_CLK 13 -#define GCC_CPUSS_AHB_CLK 14 -#define GCC_CPUSS_AHB_CLK_SRC 15 -#define GCC_CPUSS_RBCPR_CLK 16 -#define GCC_CPUSS_RBCPR_CLK_SRC 17 -#define GCC_DDRSS_GPU_AXI_CLK 18 -#define GCC_DISP_AHB_CLK 19 -#define GCC_DISP_AXI_CLK 20 -#define GCC_DISP_GPLL0_CLK_SRC 21 -#define GCC_DISP_GPLL0_DIV_CLK_SRC 22 -#define GCC_DISP_XO_CLK 23 -#define GCC_GP1_CLK 24 -#define GCC_GP1_CLK_SRC 25 -#define GCC_GP2_CLK 26 -#define GCC_GP2_CLK_SRC 27 -#define GCC_GP3_CLK 28 -#define GCC_GP3_CLK_SRC 29 -#define GCC_GPU_CFG_AHB_CLK 30 -#define GCC_GPU_GPLL0_CLK_SRC 31 -#define GCC_GPU_GPLL0_DIV_CLK_SRC 32 -#define GCC_GPU_MEMNOC_GFX_CLK 33 -#define GCC_GPU_SNOC_DVM_GFX_CLK 34 -#define GCC_MSS_AXIS2_CLK 35 -#define GCC_MSS_CFG_AHB_CLK 36 -#define GCC_MSS_GPLL0_DIV_CLK_SRC 37 -#define GCC_MSS_MFAB_AXIS_CLK 38 -#define GCC_MSS_Q6_MEMNOC_AXI_CLK 39 -#define GCC_MSS_SNOC_AXI_CLK 40 -#define GCC_PCIE_0_AUX_CLK 41 -#define GCC_PCIE_0_AUX_CLK_SRC 42 -#define GCC_PCIE_0_CFG_AHB_CLK 43 -#define GCC_PCIE_0_CLKREF_CLK 44 -#define GCC_PCIE_0_MSTR_AXI_CLK 45 -#define GCC_PCIE_0_PIPE_CLK 46 -#define GCC_PCIE_0_SLV_AXI_CLK 47 -#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 48 -#define GCC_PCIE_1_AUX_CLK 49 -#define GCC_PCIE_1_AUX_CLK_SRC 50 -#define GCC_PCIE_1_CFG_AHB_CLK 51 -#define GCC_PCIE_1_CLKREF_CLK 52 -#define GCC_PCIE_1_MSTR_AXI_CLK 53 -#define GCC_PCIE_1_PIPE_CLK 54 -#define GCC_PCIE_1_SLV_AXI_CLK 55 -#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 56 -#define GCC_PCIE_PHY_AUX_CLK 57 -#define GCC_PCIE_PHY_REFGEN_CLK 58 -#define GCC_PCIE_PHY_REFGEN_CLK_SRC 59 -#define GCC_PDM2_CLK 60 -#define GCC_PDM2_CLK_SRC 61 -#define GCC_PDM_AHB_CLK 62 -#define GCC_PDM_XO4_CLK 63 -#define GCC_PRNG_AHB_CLK 64 -#define GCC_QMIP_CAMERA_AHB_CLK 65 -#define GCC_QMIP_DISP_AHB_CLK 66 -#define GCC_QMIP_VIDEO_AHB_CLK 67 -#define GCC_QUPV3_WRAP0_S0_CLK 68 -#define GCC_QUPV3_WRAP0_S0_CLK_SRC 69 -#define GCC_QUPV3_WRAP0_S1_CLK 70 -#define GCC_QUPV3_WRAP0_S1_CLK_SRC 71 -#define GCC_QUPV3_WRAP0_S2_CLK 72 -#define GCC_QUPV3_WRAP0_S2_CLK_SRC 73 -#define GCC_QUPV3_WRAP0_S3_CLK 74 -#define GCC_QUPV3_WRAP0_S3_CLK_SRC 75 -#define GCC_QUPV3_WRAP0_S4_CLK 76 -#define GCC_QUPV3_WRAP0_S4_CLK_SRC 77 -#define GCC_QUPV3_WRAP0_S5_CLK 78 -#define GCC_QUPV3_WRAP0_S5_CLK_SRC 79 -#define GCC_QUPV3_WRAP0_S6_CLK 80 -#define GCC_QUPV3_WRAP0_S6_CLK_SRC 81 -#define GCC_QUPV3_WRAP0_S7_CLK 82 -#define GCC_QUPV3_WRAP0_S7_CLK_SRC 83 -#define GCC_QUPV3_WRAP1_S0_CLK 84 -#define GCC_QUPV3_WRAP1_S0_CLK_SRC 85 -#define GCC_QUPV3_WRAP1_S1_CLK 86 -#define GCC_QUPV3_WRAP1_S1_CLK_SRC 87 -#define GCC_QUPV3_WRAP1_S2_CLK 88 -#define GCC_QUPV3_WRAP1_S2_CLK_SRC 89 -#define GCC_QUPV3_WRAP1_S3_CLK 90 -#define GCC_QUPV3_WRAP1_S3_CLK_SRC 91 -#define GCC_QUPV3_WRAP1_S4_CLK 92 -#define GCC_QUPV3_WRAP1_S4_CLK_SRC 93 -#define GCC_QUPV3_WRAP1_S5_CLK 94 -#define GCC_QUPV3_WRAP1_S5_CLK_SRC 95 -#define GCC_QUPV3_WRAP1_S6_CLK 96 -#define GCC_QUPV3_WRAP1_S6_CLK_SRC 97 -#define GCC_QUPV3_WRAP1_S7_CLK 98 -#define GCC_QUPV3_WRAP1_S7_CLK_SRC 99 -#define GCC_QUPV3_WRAP_0_M_AHB_CLK 100 -#define GCC_QUPV3_WRAP_0_S_AHB_CLK 101 -#define GCC_QUPV3_WRAP_1_M_AHB_CLK 102 -#define GCC_QUPV3_WRAP_1_S_AHB_CLK 103 -#define GCC_SDCC2_AHB_CLK 104 -#define GCC_SDCC2_APPS_CLK 105 -#define GCC_SDCC2_APPS_CLK_SRC 106 -#define GCC_SDCC4_AHB_CLK 107 -#define GCC_SDCC4_APPS_CLK 108 -#define GCC_SDCC4_APPS_CLK_SRC 109 -#define GCC_SYS_NOC_CPUSS_AHB_CLK 110 -#define GCC_TSIF_AHB_CLK 111 -#define GCC_TSIF_INACTIVITY_TIMERS_CLK 112 -#define GCC_TSIF_REF_CLK 113 -#define GCC_TSIF_REF_CLK_SRC 114 -#define GCC_UFS_CARD_AHB_CLK 115 -#define GCC_UFS_CARD_AXI_CLK 116 -#define GCC_UFS_CARD_AXI_CLK_SRC 117 -#define GCC_UFS_CARD_CLKREF_CLK 118 -#define GCC_UFS_CARD_ICE_CORE_CLK 119 -#define GCC_UFS_CARD_ICE_CORE_CLK_SRC 120 -#define GCC_UFS_CARD_PHY_AUX_CLK 121 -#define GCC_UFS_CARD_PHY_AUX_CLK_SRC 122 -#define GCC_UFS_CARD_RX_SYMBOL_0_CLK 123 -#define GCC_UFS_CARD_RX_SYMBOL_1_CLK 124 -#define GCC_UFS_CARD_TX_SYMBOL_0_CLK 125 -#define GCC_UFS_CARD_UNIPRO_CORE_CLK 126 -#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC 127 -#define GCC_UFS_MEM_CLKREF_CLK 128 -#define GCC_UFS_PHY_AHB_CLK 129 -#define GCC_UFS_PHY_AXI_CLK 130 -#define GCC_UFS_PHY_AXI_CLK_SRC 131 -#define GCC_UFS_PHY_ICE_CORE_CLK 132 -#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 133 -#define GCC_UFS_PHY_PHY_AUX_CLK 134 -#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 135 -#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 136 -#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 137 -#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 138 -#define GCC_UFS_PHY_UNIPRO_CORE_CLK 139 -#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 140 -#define GCC_USB30_PRIM_MASTER_CLK 141 -#define GCC_USB30_PRIM_MASTER_CLK_SRC 142 -#define GCC_USB30_PRIM_MOCK_UTMI_CLK 143 -#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 144 -#define GCC_USB30_PRIM_SLEEP_CLK 145 -#define GCC_USB30_SEC_MASTER_CLK 146 -#define GCC_USB30_SEC_MASTER_CLK_SRC 147 -#define GCC_USB30_SEC_MOCK_UTMI_CLK 148 -#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 149 -#define GCC_USB30_SEC_SLEEP_CLK 150 -#define GCC_USB3_PRIM_CLKREF_CLK 151 -#define GCC_USB3_PRIM_PHY_AUX_CLK 152 -#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 153 -#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 154 -#define GCC_USB3_PRIM_PHY_PIPE_CLK 155 -#define GCC_USB3_SEC_CLKREF_CLK 156 -#define GCC_USB3_SEC_PHY_AUX_CLK 157 -#define GCC_USB3_SEC_PHY_AUX_CLK_SRC 158 -#define GCC_USB3_SEC_PHY_PIPE_CLK 159 -#define GCC_USB3_SEC_PHY_COM_AUX_CLK 160 -#define GCC_USB_PHY_CFG_AHB2PHY_CLK 161 -#define GCC_VIDEO_AHB_CLK 162 -#define GCC_VIDEO_AXI_CLK 163 -#define GCC_VIDEO_XO_CLK 164 -#define GPLL0 165 -#define GPLL0_OUT_EVEN 166 -#define GPLL0_OUT_MAIN 167 -#define GCC_GPU_IREF_CLK 168 -#define GCC_SDCC1_AHB_CLK 169 -#define GCC_SDCC1_APPS_CLK 170 -#define GCC_SDCC1_ICE_CORE_CLK 171 -#define GCC_SDCC1_APPS_CLK_SRC 172 -#define GCC_SDCC1_ICE_CORE_CLK_SRC 173 -#define GCC_APC_VS_CLK 174 -#define GCC_GPU_VS_CLK 175 -#define GCC_MSS_VS_CLK 176 -#define GCC_VDDA_VS_CLK 177 -#define GCC_VDDCX_VS_CLK 178 -#define GCC_VDDMX_VS_CLK 179 -#define GCC_VS_CTRL_AHB_CLK 180 -#define GCC_VS_CTRL_CLK 181 -#define GCC_VS_CTRL_CLK_SRC 182 -#define GCC_VSENSOR_CLK_SRC 183 -#define GPLL4 184 -#define GCC_CPUSS_DVM_BUS_CLK 185 -#define GCC_CPUSS_GNOC_CLK 186 -#define GCC_QSPI_CORE_CLK_SRC 187 -#define GCC_QSPI_CORE_CLK 188 -#define GCC_QSPI_CNOC_PERIPH_AHB_CLK 189 -#define GCC_LPASS_Q6_AXI_CLK 190 -#define GCC_LPASS_SWAY_CLK 191 - -/* GCC Resets */ -#define GCC_MMSS_BCR 0 -#define GCC_PCIE_0_BCR 1 -#define GCC_PCIE_1_BCR 2 -#define GCC_PCIE_PHY_BCR 3 -#define GCC_PDM_BCR 4 -#define GCC_PRNG_BCR 5 -#define GCC_QUPV3_WRAPPER_0_BCR 6 -#define GCC_QUPV3_WRAPPER_1_BCR 7 -#define GCC_QUSB2PHY_PRIM_BCR 8 -#define GCC_QUSB2PHY_SEC_BCR 9 -#define GCC_SDCC2_BCR 10 -#define GCC_SDCC4_BCR 11 -#define GCC_TSIF_BCR 12 -#define GCC_UFS_CARD_BCR 13 -#define GCC_UFS_PHY_BCR 14 -#define GCC_USB30_PRIM_BCR 15 -#define GCC_USB30_SEC_BCR 16 -#define GCC_USB3_PHY_PRIM_BCR 17 -#define GCC_USB3PHY_PHY_PRIM_BCR 18 -#define GCC_USB3_DP_PHY_PRIM_BCR 19 -#define GCC_USB3_PHY_SEC_BCR 20 -#define GCC_USB3PHY_PHY_SEC_BCR 21 -#define GCC_USB3_DP_PHY_SEC_BCR 22 -#define GCC_USB_PHY_CFG_AHB2PHY_BCR 23 -#define GCC_PCIE_0_PHY_BCR 24 -#define GCC_PCIE_1_PHY_BCR 25 - -/* GCC GDSCRs */ -#define PCIE_0_GDSC 0 -#define PCIE_1_GDSC 1 -#define UFS_CARD_GDSC 2 -#define UFS_PHY_GDSC 3 -#define USB30_PRIM_GDSC 4 -#define USB30_SEC_GDSC 5 -#define HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC 6 -#define HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC 7 -#define HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC 8 -#define HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC 9 -#define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC 10 -#define HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC 11 -#define HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC 12 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-sm8150.h b/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-sm8150.h deleted file mode 100644 index 90d60ef94c6..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-sm8150.h +++ /dev/null @@ -1,243 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SM8150_H -#define _DT_BINDINGS_CLK_QCOM_GCC_SM8150_H - -/* GCC clocks */ -#define GCC_AGGRE_NOC_PCIE_TBU_CLK 0 -#define GCC_AGGRE_UFS_CARD_AXI_CLK 1 -#define GCC_AGGRE_UFS_CARD_AXI_HW_CTL_CLK 2 -#define GCC_AGGRE_UFS_PHY_AXI_CLK 3 -#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 4 -#define GCC_AGGRE_USB3_PRIM_AXI_CLK 5 -#define GCC_AGGRE_USB3_SEC_AXI_CLK 6 -#define GCC_BOOT_ROM_AHB_CLK 7 -#define GCC_CAMERA_AHB_CLK 8 -#define GCC_CAMERA_HF_AXI_CLK 9 -#define GCC_CAMERA_SF_AXI_CLK 10 -#define GCC_CAMERA_XO_CLK 11 -#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 12 -#define GCC_CFG_NOC_USB3_SEC_AXI_CLK 13 -#define GCC_CPUSS_AHB_CLK 14 -#define GCC_CPUSS_AHB_CLK_SRC 15 -#define GCC_CPUSS_DVM_BUS_CLK 16 -#define GCC_CPUSS_GNOC_CLK 17 -#define GCC_CPUSS_RBCPR_CLK 18 -#define GCC_DDRSS_GPU_AXI_CLK 19 -#define GCC_DISP_AHB_CLK 20 -#define GCC_DISP_HF_AXI_CLK 21 -#define GCC_DISP_SF_AXI_CLK 22 -#define GCC_DISP_XO_CLK 23 -#define GCC_EMAC_AXI_CLK 24 -#define GCC_EMAC_PTP_CLK 25 -#define GCC_EMAC_PTP_CLK_SRC 26 -#define GCC_EMAC_RGMII_CLK 27 -#define GCC_EMAC_RGMII_CLK_SRC 28 -#define GCC_EMAC_SLV_AHB_CLK 29 -#define GCC_GP1_CLK 30 -#define GCC_GP1_CLK_SRC 31 -#define GCC_GP2_CLK 32 -#define GCC_GP2_CLK_SRC 33 -#define GCC_GP3_CLK 34 -#define GCC_GP3_CLK_SRC 35 -#define GCC_GPU_CFG_AHB_CLK 36 -#define GCC_GPU_GPLL0_CLK_SRC 37 -#define GCC_GPU_GPLL0_DIV_CLK_SRC 38 -#define GCC_GPU_IREF_CLK 39 -#define GCC_GPU_MEMNOC_GFX_CLK 40 -#define GCC_GPU_SNOC_DVM_GFX_CLK 41 -#define GCC_NPU_AT_CLK 42 -#define GCC_NPU_AXI_CLK 43 -#define GCC_NPU_CFG_AHB_CLK 44 -#define GCC_NPU_GPLL0_CLK_SRC 45 -#define GCC_NPU_GPLL0_DIV_CLK_SRC 46 -#define GCC_NPU_TRIG_CLK 47 -#define GCC_PCIE0_PHY_REFGEN_CLK 48 -#define GCC_PCIE1_PHY_REFGEN_CLK 49 -#define GCC_PCIE_0_AUX_CLK 50 -#define GCC_PCIE_0_AUX_CLK_SRC 51 -#define GCC_PCIE_0_CFG_AHB_CLK 52 -#define GCC_PCIE_0_CLKREF_CLK 53 -#define GCC_PCIE_0_MSTR_AXI_CLK 54 -#define GCC_PCIE_0_PIPE_CLK 55 -#define GCC_PCIE_0_SLV_AXI_CLK 56 -#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 57 -#define GCC_PCIE_1_AUX_CLK 58 -#define GCC_PCIE_1_AUX_CLK_SRC 59 -#define GCC_PCIE_1_CFG_AHB_CLK 60 -#define GCC_PCIE_1_CLKREF_CLK 61 -#define GCC_PCIE_1_MSTR_AXI_CLK 62 -#define GCC_PCIE_1_PIPE_CLK 63 -#define GCC_PCIE_1_SLV_AXI_CLK 64 -#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 65 -#define GCC_PCIE_PHY_AUX_CLK 66 -#define GCC_PCIE_PHY_REFGEN_CLK_SRC 67 -#define GCC_PDM2_CLK 68 -#define GCC_PDM2_CLK_SRC 69 -#define GCC_PDM_AHB_CLK 70 -#define GCC_PDM_XO4_CLK 71 -#define GCC_PRNG_AHB_CLK 72 -#define GCC_QMIP_CAMERA_NRT_AHB_CLK 73 -#define GCC_QMIP_CAMERA_RT_AHB_CLK 74 -#define GCC_QMIP_DISP_AHB_CLK 75 -#define GCC_QMIP_VIDEO_CVP_AHB_CLK 76 -#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 77 -#define GCC_QSPI_CNOC_PERIPH_AHB_CLK 78 -#define GCC_QSPI_CORE_CLK 79 -#define GCC_QSPI_CORE_CLK_SRC 80 -#define GCC_QUPV3_WRAP0_S0_CLK 81 -#define GCC_QUPV3_WRAP0_S0_CLK_SRC 82 -#define GCC_QUPV3_WRAP0_S1_CLK 83 -#define GCC_QUPV3_WRAP0_S1_CLK_SRC 84 -#define GCC_QUPV3_WRAP0_S2_CLK 85 -#define GCC_QUPV3_WRAP0_S2_CLK_SRC 86 -#define GCC_QUPV3_WRAP0_S3_CLK 87 -#define GCC_QUPV3_WRAP0_S3_CLK_SRC 88 -#define GCC_QUPV3_WRAP0_S4_CLK 89 -#define GCC_QUPV3_WRAP0_S4_CLK_SRC 90 -#define GCC_QUPV3_WRAP0_S5_CLK 91 -#define GCC_QUPV3_WRAP0_S5_CLK_SRC 92 -#define GCC_QUPV3_WRAP0_S6_CLK 93 -#define GCC_QUPV3_WRAP0_S6_CLK_SRC 94 -#define GCC_QUPV3_WRAP0_S7_CLK 95 -#define GCC_QUPV3_WRAP0_S7_CLK_SRC 96 -#define GCC_QUPV3_WRAP1_S0_CLK 97 -#define GCC_QUPV3_WRAP1_S0_CLK_SRC 98 -#define GCC_QUPV3_WRAP1_S1_CLK 99 -#define GCC_QUPV3_WRAP1_S1_CLK_SRC 100 -#define GCC_QUPV3_WRAP1_S2_CLK 101 -#define GCC_QUPV3_WRAP1_S2_CLK_SRC 102 -#define GCC_QUPV3_WRAP1_S3_CLK 103 -#define GCC_QUPV3_WRAP1_S3_CLK_SRC 104 -#define GCC_QUPV3_WRAP1_S4_CLK 105 -#define GCC_QUPV3_WRAP1_S4_CLK_SRC 106 -#define GCC_QUPV3_WRAP1_S5_CLK 107 -#define GCC_QUPV3_WRAP1_S5_CLK_SRC 108 -#define GCC_QUPV3_WRAP2_S0_CLK 109 -#define GCC_QUPV3_WRAP2_S0_CLK_SRC 110 -#define GCC_QUPV3_WRAP2_S1_CLK 111 -#define GCC_QUPV3_WRAP2_S1_CLK_SRC 112 -#define GCC_QUPV3_WRAP2_S2_CLK 113 -#define GCC_QUPV3_WRAP2_S2_CLK_SRC 114 -#define GCC_QUPV3_WRAP2_S3_CLK 115 -#define GCC_QUPV3_WRAP2_S3_CLK_SRC 116 -#define GCC_QUPV3_WRAP2_S4_CLK 117 -#define GCC_QUPV3_WRAP2_S4_CLK_SRC 118 -#define GCC_QUPV3_WRAP2_S5_CLK 119 -#define GCC_QUPV3_WRAP2_S5_CLK_SRC 120 -#define GCC_QUPV3_WRAP_0_M_AHB_CLK 121 -#define GCC_QUPV3_WRAP_0_S_AHB_CLK 122 -#define GCC_QUPV3_WRAP_1_M_AHB_CLK 123 -#define GCC_QUPV3_WRAP_1_S_AHB_CLK 124 -#define GCC_QUPV3_WRAP_2_M_AHB_CLK 125 -#define GCC_QUPV3_WRAP_2_S_AHB_CLK 126 -#define GCC_SDCC2_AHB_CLK 127 -#define GCC_SDCC2_APPS_CLK 128 -#define GCC_SDCC2_APPS_CLK_SRC 129 -#define GCC_SDCC4_AHB_CLK 130 -#define GCC_SDCC4_APPS_CLK 131 -#define GCC_SDCC4_APPS_CLK_SRC 132 -#define GCC_SYS_NOC_CPUSS_AHB_CLK 133 -#define GCC_TSIF_AHB_CLK 134 -#define GCC_TSIF_INACTIVITY_TIMERS_CLK 135 -#define GCC_TSIF_REF_CLK 136 -#define GCC_TSIF_REF_CLK_SRC 137 -#define GCC_UFS_CARD_AHB_CLK 138 -#define GCC_UFS_CARD_AXI_CLK 139 -#define GCC_UFS_CARD_AXI_CLK_SRC 140 -#define GCC_UFS_CARD_AXI_HW_CTL_CLK 141 -#define GCC_UFS_CARD_CLKREF_CLK 142 -#define GCC_UFS_CARD_ICE_CORE_CLK 143 -#define GCC_UFS_CARD_ICE_CORE_CLK_SRC 144 -#define GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK 145 -#define GCC_UFS_CARD_PHY_AUX_CLK 146 -#define GCC_UFS_CARD_PHY_AUX_CLK_SRC 147 -#define GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK 148 -#define GCC_UFS_CARD_RX_SYMBOL_0_CLK 149 -#define GCC_UFS_CARD_RX_SYMBOL_1_CLK 150 -#define GCC_UFS_CARD_TX_SYMBOL_0_CLK 151 -#define GCC_UFS_CARD_UNIPRO_CORE_CLK 152 -#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC 153 -#define GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK 154 -#define GCC_UFS_MEM_CLKREF_CLK 155 -#define GCC_UFS_PHY_AHB_CLK 156 -#define GCC_UFS_PHY_AXI_CLK 157 -#define GCC_UFS_PHY_AXI_CLK_SRC 158 -#define GCC_UFS_PHY_AXI_HW_CTL_CLK 159 -#define GCC_UFS_PHY_ICE_CORE_CLK 160 -#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 161 -#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 162 -#define GCC_UFS_PHY_PHY_AUX_CLK 163 -#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 164 -#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 165 -#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 166 -#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 167 -#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 168 -#define GCC_UFS_PHY_UNIPRO_CORE_CLK 169 -#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 170 -#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 171 -#define GCC_USB30_PRIM_MASTER_CLK 172 -#define GCC_USB30_PRIM_MASTER_CLK_SRC 173 -#define GCC_USB30_PRIM_MOCK_UTMI_CLK 174 -#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 175 -#define GCC_USB30_PRIM_SLEEP_CLK 176 -#define GCC_USB30_SEC_MASTER_CLK 177 -#define GCC_USB30_SEC_MASTER_CLK_SRC 178 -#define GCC_USB30_SEC_MOCK_UTMI_CLK 179 -#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 180 -#define GCC_USB30_SEC_SLEEP_CLK 181 -#define GCC_USB3_PRIM_CLKREF_CLK 182 -#define GCC_USB3_PRIM_PHY_AUX_CLK 183 -#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 184 -#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 185 -#define GCC_USB3_PRIM_PHY_PIPE_CLK 186 -#define GCC_USB3_SEC_CLKREF_CLK 187 -#define GCC_USB3_SEC_PHY_AUX_CLK 188 -#define GCC_USB3_SEC_PHY_AUX_CLK_SRC 189 -#define GCC_USB3_SEC_PHY_COM_AUX_CLK 190 -#define GCC_USB3_SEC_PHY_PIPE_CLK 191 -#define GCC_VIDEO_AHB_CLK 192 -#define GCC_VIDEO_AXI0_CLK 193 -#define GCC_VIDEO_AXI1_CLK 194 -#define GCC_VIDEO_AXIC_CLK 195 -#define GCC_VIDEO_XO_CLK 196 -#define GPLL0 197 -#define GPLL0_OUT_EVEN 198 -#define GPLL7 199 -#define GPLL9 200 - -/* Reset clocks */ -#define GCC_EMAC_BCR 0 -#define GCC_GPU_BCR 1 -#define GCC_MMSS_BCR 2 -#define GCC_NPU_BCR 3 -#define GCC_PCIE_0_BCR 4 -#define GCC_PCIE_0_PHY_BCR 5 -#define GCC_PCIE_1_BCR 6 -#define GCC_PCIE_1_PHY_BCR 7 -#define GCC_PCIE_PHY_BCR 8 -#define GCC_PDM_BCR 9 -#define GCC_PRNG_BCR 10 -#define GCC_QSPI_BCR 11 -#define GCC_QUPV3_WRAPPER_0_BCR 12 -#define GCC_QUPV3_WRAPPER_1_BCR 13 -#define GCC_QUPV3_WRAPPER_2_BCR 14 -#define GCC_QUSB2PHY_PRIM_BCR 15 -#define GCC_QUSB2PHY_SEC_BCR 16 -#define GCC_USB3_PHY_PRIM_BCR 17 -#define GCC_USB3_DP_PHY_PRIM_BCR 18 -#define GCC_USB3_PHY_SEC_BCR 19 -#define GCC_USB3PHY_PHY_SEC_BCR 20 -#define GCC_SDCC2_BCR 21 -#define GCC_SDCC4_BCR 22 -#define GCC_TSIF_BCR 23 -#define GCC_UFS_CARD_BCR 24 -#define GCC_UFS_PHY_BCR 25 -#define GCC_USB30_PRIM_BCR 26 -#define GCC_USB30_SEC_BCR 27 -#define GCC_USB_PHY_CFG_AHB2PHY_BCR 28 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/qcom,gpucc-msm8998.h b/sys/gnu/dts/include/dt-bindings/clock/qcom,gpucc-msm8998.h deleted file mode 100644 index 2623570ee97..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/qcom,gpucc-msm8998.h +++ /dev/null @@ -1,29 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2019, Jeffrey Hugo - */ - -#ifndef _DT_BINDINGS_CLK_MSM_GPUCC_8998_H -#define _DT_BINDINGS_CLK_MSM_GPUCC_8998_H - -#define GPUPLL0 0 -#define GPUPLL0_OUT_EVEN 1 -#define RBCPR_CLK_SRC 2 -#define GFX3D_CLK_SRC 3 -#define RBBMTIMER_CLK_SRC 4 -#define GFX3D_ISENSE_CLK_SRC 5 -#define RBCPR_CLK 6 -#define GFX3D_CLK 7 -#define RBBMTIMER_CLK 8 -#define GFX3D_ISENSE_CLK 9 -#define GPUCC_CXO_CLK 10 - -#define GPU_CX_BCR 0 -#define RBCPR_BCR 1 -#define GPU_GX_BCR 2 -#define GPU_ISENSE_BCR 3 - -#define GPU_CX_GDSC 1 -#define GPU_GX_GDSC 2 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/qcom,gpucc-sc7180.h b/sys/gnu/dts/include/dt-bindings/clock/qcom,gpucc-sc7180.h deleted file mode 100644 index 0e4643b08b4..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/qcom,gpucc-sc7180.h +++ /dev/null @@ -1,21 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SC7180_H -#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SC7180_H - -#define GPU_CC_PLL1 0 -#define GPU_CC_AHB_CLK 1 -#define GPU_CC_CRC_AHB_CLK 2 -#define GPU_CC_CX_GMU_CLK 3 -#define GPU_CC_CX_SNOC_DVM_CLK 4 -#define GPU_CC_CXO_AON_CLK 5 -#define GPU_CC_CXO_CLK 6 -#define GPU_CC_GMU_CLK_SRC 7 - -/* CAM_CC GDSCRs */ -#define CX_GDSC 0 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/qcom,gpucc-sdm845.h b/sys/gnu/dts/include/dt-bindings/clock/qcom,gpucc-sdm845.h deleted file mode 100644 index 9690d901b50..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/qcom,gpucc-sdm845.h +++ /dev/null @@ -1,24 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_CLK_SDM_GPU_CC_SDM845_H -#define _DT_BINDINGS_CLK_SDM_GPU_CC_SDM845_H - -/* GPU_CC clock registers */ -#define GPU_CC_CX_GMU_CLK 0 -#define GPU_CC_CXO_CLK 1 -#define GPU_CC_GMU_CLK_SRC 2 -#define GPU_CC_PLL1 3 - -/* GPU_CC Resets */ -#define GPUCC_GPU_CC_CX_BCR 0 -#define GPUCC_GPU_CC_GMU_BCR 1 -#define GPUCC_GPU_CC_XO_BCR 2 - -/* GPU_CC GDSCRs */ -#define GPU_CX_GDSC 0 -#define GPU_GX_GDSC 1 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/qcom,lcc-ipq806x.h b/sys/gnu/dts/include/dt-bindings/clock/qcom,lcc-ipq806x.h deleted file mode 100644 index 25b92bbf0ab..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/qcom,lcc-ipq806x.h +++ /dev/null @@ -1,22 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2014, The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_CLK_LCC_IPQ806X_H -#define _DT_BINDINGS_CLK_LCC_IPQ806X_H - -#define PLL4 0 -#define MI2S_OSR_SRC 1 -#define MI2S_OSR_CLK 2 -#define MI2S_DIV_CLK 3 -#define MI2S_BIT_DIV_CLK 4 -#define MI2S_BIT_CLK 5 -#define PCM_SRC 6 -#define PCM_CLK_OUT 7 -#define PCM_CLK 8 -#define SPDIF_SRC 9 -#define SPDIF_CLK 10 -#define AHBIX_CLK 11 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/qcom,lcc-mdm9615.h b/sys/gnu/dts/include/dt-bindings/clock/qcom,lcc-mdm9615.h deleted file mode 100644 index 299338ee1d8..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/qcom,lcc-mdm9615.h +++ /dev/null @@ -1,44 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2014, The Linux Foundation. All rights reserved. - * Copyright (c) BayLibre, SAS. - * Author : Neil Armstrong - */ - -#ifndef _DT_BINDINGS_CLK_LCC_MDM9615_H -#define _DT_BINDINGS_CLK_LCC_MDM9615_H - -#define PLL4 0 -#define MI2S_OSR_SRC 1 -#define MI2S_OSR_CLK 2 -#define MI2S_DIV_CLK 3 -#define MI2S_BIT_DIV_CLK 4 -#define MI2S_BIT_CLK 5 -#define PCM_SRC 6 -#define PCM_CLK_OUT 7 -#define PCM_CLK 8 -#define SLIMBUS_SRC 9 -#define AUDIO_SLIMBUS_CLK 10 -#define SPS_SLIMBUS_CLK 11 -#define CODEC_I2S_MIC_OSR_SRC 12 -#define CODEC_I2S_MIC_OSR_CLK 13 -#define CODEC_I2S_MIC_DIV_CLK 14 -#define CODEC_I2S_MIC_BIT_DIV_CLK 15 -#define CODEC_I2S_MIC_BIT_CLK 16 -#define SPARE_I2S_MIC_OSR_SRC 17 -#define SPARE_I2S_MIC_OSR_CLK 18 -#define SPARE_I2S_MIC_DIV_CLK 19 -#define SPARE_I2S_MIC_BIT_DIV_CLK 20 -#define SPARE_I2S_MIC_BIT_CLK 21 -#define CODEC_I2S_SPKR_OSR_SRC 22 -#define CODEC_I2S_SPKR_OSR_CLK 23 -#define CODEC_I2S_SPKR_DIV_CLK 24 -#define CODEC_I2S_SPKR_BIT_DIV_CLK 25 -#define CODEC_I2S_SPKR_BIT_CLK 26 -#define SPARE_I2S_SPKR_OSR_SRC 27 -#define SPARE_I2S_SPKR_OSR_CLK 28 -#define SPARE_I2S_SPKR_DIV_CLK 29 -#define SPARE_I2S_SPKR_BIT_DIV_CLK 30 -#define SPARE_I2S_SPKR_BIT_CLK 31 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/qcom,lcc-msm8960.h b/sys/gnu/dts/include/dt-bindings/clock/qcom,lcc-msm8960.h deleted file mode 100644 index d115a49f4cb..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/qcom,lcc-msm8960.h +++ /dev/null @@ -1,42 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2014, The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_CLK_LCC_MSM8960_H -#define _DT_BINDINGS_CLK_LCC_MSM8960_H - -#define PLL4 0 -#define MI2S_OSR_SRC 1 -#define MI2S_OSR_CLK 2 -#define MI2S_DIV_CLK 3 -#define MI2S_BIT_DIV_CLK 4 -#define MI2S_BIT_CLK 5 -#define PCM_SRC 6 -#define PCM_CLK_OUT 7 -#define PCM_CLK 8 -#define SLIMBUS_SRC 9 -#define AUDIO_SLIMBUS_CLK 10 -#define SPS_SLIMBUS_CLK 11 -#define CODEC_I2S_MIC_OSR_SRC 12 -#define CODEC_I2S_MIC_OSR_CLK 13 -#define CODEC_I2S_MIC_DIV_CLK 14 -#define CODEC_I2S_MIC_BIT_DIV_CLK 15 -#define CODEC_I2S_MIC_BIT_CLK 16 -#define SPARE_I2S_MIC_OSR_SRC 17 -#define SPARE_I2S_MIC_OSR_CLK 18 -#define SPARE_I2S_MIC_DIV_CLK 19 -#define SPARE_I2S_MIC_BIT_DIV_CLK 20 -#define SPARE_I2S_MIC_BIT_CLK 21 -#define CODEC_I2S_SPKR_OSR_SRC 22 -#define CODEC_I2S_SPKR_OSR_CLK 23 -#define CODEC_I2S_SPKR_DIV_CLK 24 -#define CODEC_I2S_SPKR_BIT_DIV_CLK 25 -#define CODEC_I2S_SPKR_BIT_CLK 26 -#define SPARE_I2S_SPKR_OSR_SRC 27 -#define SPARE_I2S_SPKR_OSR_CLK 28 -#define SPARE_I2S_SPKR_DIV_CLK 29 -#define SPARE_I2S_SPKR_BIT_DIV_CLK 30 -#define SPARE_I2S_SPKR_BIT_CLK 31 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/qcom,lpass-sdm845.h b/sys/gnu/dts/include/dt-bindings/clock/qcom,lpass-sdm845.h deleted file mode 100644 index 659050846f6..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/qcom,lpass-sdm845.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_CLK_SDM_LPASS_SDM845_H -#define _DT_BINDINGS_CLK_SDM_LPASS_SDM845_H - -#define LPASS_Q6SS_AHBM_AON_CLK 0 -#define LPASS_Q6SS_AHBS_AON_CLK 1 -#define LPASS_QDSP6SS_XO_CLK 2 -#define LPASS_QDSP6SS_SLEEP_CLK 3 -#define LPASS_QDSP6SS_CORE_CLK 4 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/qcom,mmcc-apq8084.h b/sys/gnu/dts/include/dt-bindings/clock/qcom,mmcc-apq8084.h deleted file mode 100644 index 9d42b1b25a9..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/qcom,mmcc-apq8084.h +++ /dev/null @@ -1,185 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2014, The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_CLK_APQ_MMCC_8084_H -#define _DT_BINDINGS_CLK_APQ_MMCC_8084_H - -#define MMSS_AHB_CLK_SRC 0 -#define MMSS_AXI_CLK_SRC 1 -#define MMPLL0 2 -#define MMPLL0_VOTE 3 -#define MMPLL1 4 -#define MMPLL1_VOTE 5 -#define MMPLL2 6 -#define MMPLL3 7 -#define MMPLL4 8 -#define CSI0_CLK_SRC 9 -#define CSI1_CLK_SRC 10 -#define CSI2_CLK_SRC 11 -#define CSI3_CLK_SRC 12 -#define VCODEC0_CLK_SRC 13 -#define VFE0_CLK_SRC 14 -#define VFE1_CLK_SRC 15 -#define MDP_CLK_SRC 16 -#define PCLK0_CLK_SRC 17 -#define PCLK1_CLK_SRC 18 -#define OCMEMNOC_CLK_SRC 19 -#define GFX3D_CLK_SRC 20 -#define JPEG0_CLK_SRC 21 -#define JPEG1_CLK_SRC 22 -#define JPEG2_CLK_SRC 23 -#define EDPPIXEL_CLK_SRC 24 -#define EXTPCLK_CLK_SRC 25 -#define VP_CLK_SRC 26 -#define CCI_CLK_SRC 27 -#define CAMSS_GP0_CLK_SRC 28 -#define CAMSS_GP1_CLK_SRC 29 -#define MCLK0_CLK_SRC 30 -#define MCLK1_CLK_SRC 31 -#define MCLK2_CLK_SRC 32 -#define MCLK3_CLK_SRC 33 -#define CSI0PHYTIMER_CLK_SRC 34 -#define CSI1PHYTIMER_CLK_SRC 35 -#define CSI2PHYTIMER_CLK_SRC 36 -#define CPP_CLK_SRC 37 -#define BYTE0_CLK_SRC 38 -#define BYTE1_CLK_SRC 39 -#define EDPAUX_CLK_SRC 40 -#define EDPLINK_CLK_SRC 41 -#define ESC0_CLK_SRC 42 -#define ESC1_CLK_SRC 43 -#define HDMI_CLK_SRC 44 -#define VSYNC_CLK_SRC 45 -#define MMSS_RBCPR_CLK_SRC 46 -#define RBBMTIMER_CLK_SRC 47 -#define MAPLE_CLK_SRC 48 -#define VDP_CLK_SRC 49 -#define VPU_BUS_CLK_SRC 50 -#define MMSS_CXO_CLK 51 -#define MMSS_SLEEPCLK_CLK 52 -#define AVSYNC_AHB_CLK 53 -#define AVSYNC_EDPPIXEL_CLK 54 -#define AVSYNC_EXTPCLK_CLK 55 -#define AVSYNC_PCLK0_CLK 56 -#define AVSYNC_PCLK1_CLK 57 -#define AVSYNC_VP_CLK 58 -#define CAMSS_AHB_CLK 59 -#define CAMSS_CCI_CCI_AHB_CLK 60 -#define CAMSS_CCI_CCI_CLK 61 -#define CAMSS_CSI0_AHB_CLK 62 -#define CAMSS_CSI0_CLK 63 -#define CAMSS_CSI0PHY_CLK 64 -#define CAMSS_CSI0PIX_CLK 65 -#define CAMSS_CSI0RDI_CLK 66 -#define CAMSS_CSI1_AHB_CLK 67 -#define CAMSS_CSI1_CLK 68 -#define CAMSS_CSI1PHY_CLK 69 -#define CAMSS_CSI1PIX_CLK 70 -#define CAMSS_CSI1RDI_CLK 71 -#define CAMSS_CSI2_AHB_CLK 72 -#define CAMSS_CSI2_CLK 73 -#define CAMSS_CSI2PHY_CLK 74 -#define CAMSS_CSI2PIX_CLK 75 -#define CAMSS_CSI2RDI_CLK 76 -#define CAMSS_CSI3_AHB_CLK 77 -#define CAMSS_CSI3_CLK 78 -#define CAMSS_CSI3PHY_CLK 79 -#define CAMSS_CSI3PIX_CLK 80 -#define CAMSS_CSI3RDI_CLK 81 -#define CAMSS_CSI_VFE0_CLK 82 -#define CAMSS_CSI_VFE1_CLK 83 -#define CAMSS_GP0_CLK 84 -#define CAMSS_GP1_CLK 85 -#define CAMSS_ISPIF_AHB_CLK 86 -#define CAMSS_JPEG_JPEG0_CLK 87 -#define CAMSS_JPEG_JPEG1_CLK 88 -#define CAMSS_JPEG_JPEG2_CLK 89 -#define CAMSS_JPEG_JPEG_AHB_CLK 90 -#define CAMSS_JPEG_JPEG_AXI_CLK 91 -#define CAMSS_MCLK0_CLK 92 -#define CAMSS_MCLK1_CLK 93 -#define CAMSS_MCLK2_CLK 94 -#define CAMSS_MCLK3_CLK 95 -#define CAMSS_MICRO_AHB_CLK 96 -#define CAMSS_PHY0_CSI0PHYTIMER_CLK 97 -#define CAMSS_PHY1_CSI1PHYTIMER_CLK 98 -#define CAMSS_PHY2_CSI2PHYTIMER_CLK 99 -#define CAMSS_TOP_AHB_CLK 100 -#define CAMSS_VFE_CPP_AHB_CLK 101 -#define CAMSS_VFE_CPP_CLK 102 -#define CAMSS_VFE_VFE0_CLK 103 -#define CAMSS_VFE_VFE1_CLK 104 -#define CAMSS_VFE_VFE_AHB_CLK 105 -#define CAMSS_VFE_VFE_AXI_CLK 106 -#define MDSS_AHB_CLK 107 -#define MDSS_AXI_CLK 108 -#define MDSS_BYTE0_CLK 109 -#define MDSS_BYTE1_CLK 110 -#define MDSS_EDPAUX_CLK 111 -#define MDSS_EDPLINK_CLK 112 -#define MDSS_EDPPIXEL_CLK 113 -#define MDSS_ESC0_CLK 114 -#define MDSS_ESC1_CLK 115 -#define MDSS_EXTPCLK_CLK 116 -#define MDSS_HDMI_AHB_CLK 117 -#define MDSS_HDMI_CLK 118 -#define MDSS_MDP_CLK 119 -#define MDSS_MDP_LUT_CLK 120 -#define MDSS_PCLK0_CLK 121 -#define MDSS_PCLK1_CLK 122 -#define MDSS_VSYNC_CLK 123 -#define MMSS_RBCPR_AHB_CLK 124 -#define MMSS_RBCPR_CLK 125 -#define MMSS_SPDM_AHB_CLK 126 -#define MMSS_SPDM_AXI_CLK 127 -#define MMSS_SPDM_CSI0_CLK 128 -#define MMSS_SPDM_GFX3D_CLK 129 -#define MMSS_SPDM_JPEG0_CLK 130 -#define MMSS_SPDM_JPEG1_CLK 131 -#define MMSS_SPDM_JPEG2_CLK 132 -#define MMSS_SPDM_MDP_CLK 133 -#define MMSS_SPDM_PCLK0_CLK 134 -#define MMSS_SPDM_PCLK1_CLK 135 -#define MMSS_SPDM_VCODEC0_CLK 136 -#define MMSS_SPDM_VFE0_CLK 137 -#define MMSS_SPDM_VFE1_CLK 138 -#define MMSS_SPDM_RM_AXI_CLK 139 -#define MMSS_SPDM_RM_OCMEMNOC_CLK 140 -#define MMSS_MISC_AHB_CLK 141 -#define MMSS_MMSSNOC_AHB_CLK 142 -#define MMSS_MMSSNOC_BTO_AHB_CLK 143 -#define MMSS_MMSSNOC_AXI_CLK 144 -#define MMSS_S0_AXI_CLK 145 -#define OCMEMCX_AHB_CLK 146 -#define OCMEMCX_OCMEMNOC_CLK 147 -#define OXILI_OCMEMGX_CLK 148 -#define OXILI_GFX3D_CLK 149 -#define OXILI_RBBMTIMER_CLK 150 -#define OXILICX_AHB_CLK 151 -#define VENUS0_AHB_CLK 152 -#define VENUS0_AXI_CLK 153 -#define VENUS0_CORE0_VCODEC_CLK 154 -#define VENUS0_CORE1_VCODEC_CLK 155 -#define VENUS0_OCMEMNOC_CLK 156 -#define VENUS0_VCODEC0_CLK 157 -#define VPU_AHB_CLK 158 -#define VPU_AXI_CLK 159 -#define VPU_BUS_CLK 160 -#define VPU_CXO_CLK 161 -#define VPU_MAPLE_CLK 162 -#define VPU_SLEEP_CLK 163 -#define VPU_VDP_CLK 164 - -/* GDSCs */ -#define VENUS0_GDSC 0 -#define VENUS0_CORE0_GDSC 1 -#define VENUS0_CORE1_GDSC 2 -#define MDSS_GDSC 3 -#define CAMSS_JPEG_GDSC 4 -#define CAMSS_VFE_GDSC 5 -#define OXILI_GDSC 6 -#define OXILICX_GDSC 7 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/qcom,mmcc-msm8960.h b/sys/gnu/dts/include/dt-bindings/clock/qcom,mmcc-msm8960.h deleted file mode 100644 index 81714fc859c..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/qcom,mmcc-msm8960.h +++ /dev/null @@ -1,137 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2013, The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_CLK_MSM_MMCC_8960_H -#define _DT_BINDINGS_CLK_MSM_MMCC_8960_H - -#define MMSS_AHB_SRC 0 -#define FAB_AHB_CLK 1 -#define APU_AHB_CLK 2 -#define TV_ENC_AHB_CLK 3 -#define AMP_AHB_CLK 4 -#define DSI2_S_AHB_CLK 5 -#define JPEGD_AHB_CLK 6 -#define GFX2D0_AHB_CLK 7 -#define DSI_S_AHB_CLK 8 -#define DSI2_M_AHB_CLK 9 -#define VPE_AHB_CLK 10 -#define SMMU_AHB_CLK 11 -#define HDMI_M_AHB_CLK 12 -#define VFE_AHB_CLK 13 -#define ROT_AHB_CLK 14 -#define VCODEC_AHB_CLK 15 -#define MDP_AHB_CLK 16 -#define DSI_M_AHB_CLK 17 -#define CSI_AHB_CLK 18 -#define MMSS_IMEM_AHB_CLK 19 -#define IJPEG_AHB_CLK 20 -#define HDMI_S_AHB_CLK 21 -#define GFX3D_AHB_CLK 22 -#define GFX2D1_AHB_CLK 23 -#define MMSS_FPB_CLK 24 -#define MMSS_AXI_SRC 25 -#define MMSS_FAB_CORE 26 -#define FAB_MSP_AXI_CLK 27 -#define JPEGD_AXI_CLK 28 -#define GMEM_AXI_CLK 29 -#define MDP_AXI_CLK 30 -#define MMSS_IMEM_AXI_CLK 31 -#define IJPEG_AXI_CLK 32 -#define GFX3D_AXI_CLK 33 -#define VCODEC_AXI_CLK 34 -#define VFE_AXI_CLK 35 -#define VPE_AXI_CLK 36 -#define ROT_AXI_CLK 37 -#define VCODEC_AXI_A_CLK 38 -#define VCODEC_AXI_B_CLK 39 -#define MM_AXI_S3_FCLK 40 -#define MM_AXI_S2_FCLK 41 -#define MM_AXI_S1_FCLK 42 -#define MM_AXI_S0_FCLK 43 -#define MM_AXI_S2_CLK 44 -#define MM_AXI_S1_CLK 45 -#define MM_AXI_S0_CLK 46 -#define CSI0_SRC 47 -#define CSI0_CLK 48 -#define CSI0_PHY_CLK 49 -#define CSI1_SRC 50 -#define CSI1_CLK 51 -#define CSI1_PHY_CLK 52 -#define CSI2_SRC 53 -#define CSI2_CLK 54 -#define CSI2_PHY_CLK 55 -#define DSI_SRC 56 -#define DSI_CLK 57 -#define CSI_PIX_CLK 58 -#define CSI_RDI_CLK 59 -#define MDP_VSYNC_CLK 60 -#define HDMI_DIV_CLK 61 -#define HDMI_APP_CLK 62 -#define CSI_PIX1_CLK 63 -#define CSI_RDI2_CLK 64 -#define CSI_RDI1_CLK 65 -#define GFX2D0_SRC 66 -#define GFX2D0_CLK 67 -#define GFX2D1_SRC 68 -#define GFX2D1_CLK 69 -#define GFX3D_SRC 70 -#define GFX3D_CLK 71 -#define IJPEG_SRC 72 -#define IJPEG_CLK 73 -#define JPEGD_SRC 74 -#define JPEGD_CLK 75 -#define MDP_SRC 76 -#define MDP_CLK 77 -#define MDP_LUT_CLK 78 -#define DSI2_PIXEL_SRC 79 -#define DSI2_PIXEL_CLK 80 -#define DSI2_SRC 81 -#define DSI2_CLK 82 -#define DSI1_BYTE_SRC 83 -#define DSI1_BYTE_CLK 84 -#define DSI2_BYTE_SRC 85 -#define DSI2_BYTE_CLK 86 -#define DSI1_ESC_SRC 87 -#define DSI1_ESC_CLK 88 -#define DSI2_ESC_SRC 89 -#define DSI2_ESC_CLK 90 -#define ROT_SRC 91 -#define ROT_CLK 92 -#define TV_ENC_CLK 93 -#define TV_DAC_CLK 94 -#define HDMI_TV_CLK 95 -#define MDP_TV_CLK 96 -#define TV_SRC 97 -#define VCODEC_SRC 98 -#define VCODEC_CLK 99 -#define VFE_SRC 100 -#define VFE_CLK 101 -#define VFE_CSI_CLK 102 -#define VPE_SRC 103 -#define VPE_CLK 104 -#define DSI_PIXEL_SRC 105 -#define DSI_PIXEL_CLK 106 -#define CAMCLK0_SRC 107 -#define CAMCLK0_CLK 108 -#define CAMCLK1_SRC 109 -#define CAMCLK1_CLK 110 -#define CAMCLK2_SRC 111 -#define CAMCLK2_CLK 112 -#define CSIPHYTIMER_SRC 113 -#define CSIPHY2_TIMER_CLK 114 -#define CSIPHY1_TIMER_CLK 115 -#define CSIPHY0_TIMER_CLK 116 -#define PLL1 117 -#define PLL2 118 -#define RGB_TV_CLK 119 -#define NPL_TV_CLK 120 -#define VCAP_AHB_CLK 121 -#define VCAP_AXI_CLK 122 -#define VCAP_SRC 123 -#define VCAP_CLK 124 -#define VCAP_NPL_CLK 125 -#define PLL15 126 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/qcom,mmcc-msm8974.h b/sys/gnu/dts/include/dt-bindings/clock/qcom,mmcc-msm8974.h deleted file mode 100644 index a62cb0629a7..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/qcom,mmcc-msm8974.h +++ /dev/null @@ -1,161 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2013, The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_CLK_MSM_MMCC_8974_H -#define _DT_BINDINGS_CLK_MSM_MMCC_8974_H - -#define MMSS_AHB_CLK_SRC 0 -#define MMSS_AXI_CLK_SRC 1 -#define MMPLL0 2 -#define MMPLL0_VOTE 3 -#define MMPLL1 4 -#define MMPLL1_VOTE 5 -#define MMPLL2 6 -#define MMPLL3 7 -#define CSI0_CLK_SRC 8 -#define CSI1_CLK_SRC 9 -#define CSI2_CLK_SRC 10 -#define CSI3_CLK_SRC 11 -#define VFE0_CLK_SRC 12 -#define VFE1_CLK_SRC 13 -#define MDP_CLK_SRC 14 -#define GFX3D_CLK_SRC 15 -#define JPEG0_CLK_SRC 16 -#define JPEG1_CLK_SRC 17 -#define JPEG2_CLK_SRC 18 -#define PCLK0_CLK_SRC 19 -#define PCLK1_CLK_SRC 20 -#define VCODEC0_CLK_SRC 21 -#define CCI_CLK_SRC 22 -#define CAMSS_GP0_CLK_SRC 23 -#define CAMSS_GP1_CLK_SRC 24 -#define MCLK0_CLK_SRC 25 -#define MCLK1_CLK_SRC 26 -#define MCLK2_CLK_SRC 27 -#define MCLK3_CLK_SRC 28 -#define CSI0PHYTIMER_CLK_SRC 29 -#define CSI1PHYTIMER_CLK_SRC 30 -#define CSI2PHYTIMER_CLK_SRC 31 -#define CPP_CLK_SRC 32 -#define BYTE0_CLK_SRC 33 -#define BYTE1_CLK_SRC 34 -#define EDPAUX_CLK_SRC 35 -#define EDPLINK_CLK_SRC 36 -#define EDPPIXEL_CLK_SRC 37 -#define ESC0_CLK_SRC 38 -#define ESC1_CLK_SRC 39 -#define EXTPCLK_CLK_SRC 40 -#define HDMI_CLK_SRC 41 -#define VSYNC_CLK_SRC 42 -#define MMSS_RBCPR_CLK_SRC 43 -#define CAMSS_CCI_CCI_AHB_CLK 44 -#define CAMSS_CCI_CCI_CLK 45 -#define CAMSS_CSI0_AHB_CLK 46 -#define CAMSS_CSI0_CLK 47 -#define CAMSS_CSI0PHY_CLK 48 -#define CAMSS_CSI0PIX_CLK 49 -#define CAMSS_CSI0RDI_CLK 50 -#define CAMSS_CSI1_AHB_CLK 51 -#define CAMSS_CSI1_CLK 52 -#define CAMSS_CSI1PHY_CLK 53 -#define CAMSS_CSI1PIX_CLK 54 -#define CAMSS_CSI1RDI_CLK 55 -#define CAMSS_CSI2_AHB_CLK 56 -#define CAMSS_CSI2_CLK 57 -#define CAMSS_CSI2PHY_CLK 58 -#define CAMSS_CSI2PIX_CLK 59 -#define CAMSS_CSI2RDI_CLK 60 -#define CAMSS_CSI3_AHB_CLK 61 -#define CAMSS_CSI3_CLK 62 -#define CAMSS_CSI3PHY_CLK 63 -#define CAMSS_CSI3PIX_CLK 64 -#define CAMSS_CSI3RDI_CLK 65 -#define CAMSS_CSI_VFE0_CLK 66 -#define CAMSS_CSI_VFE1_CLK 67 -#define CAMSS_GP0_CLK 68 -#define CAMSS_GP1_CLK 69 -#define CAMSS_ISPIF_AHB_CLK 70 -#define CAMSS_JPEG_JPEG0_CLK 71 -#define CAMSS_JPEG_JPEG1_CLK 72 -#define CAMSS_JPEG_JPEG2_CLK 73 -#define CAMSS_JPEG_JPEG_AHB_CLK 74 -#define CAMSS_JPEG_JPEG_AXI_CLK 75 -#define CAMSS_JPEG_JPEG_OCMEMNOC_CLK 76 -#define CAMSS_MCLK0_CLK 77 -#define CAMSS_MCLK1_CLK 78 -#define CAMSS_MCLK2_CLK 79 -#define CAMSS_MCLK3_CLK 80 -#define CAMSS_MICRO_AHB_CLK 81 -#define CAMSS_PHY0_CSI0PHYTIMER_CLK 82 -#define CAMSS_PHY1_CSI1PHYTIMER_CLK 83 -#define CAMSS_PHY2_CSI2PHYTIMER_CLK 84 -#define CAMSS_TOP_AHB_CLK 85 -#define CAMSS_VFE_CPP_AHB_CLK 86 -#define CAMSS_VFE_CPP_CLK 87 -#define CAMSS_VFE_VFE0_CLK 88 -#define CAMSS_VFE_VFE1_CLK 89 -#define CAMSS_VFE_VFE_AHB_CLK 90 -#define CAMSS_VFE_VFE_AXI_CLK 91 -#define CAMSS_VFE_VFE_OCMEMNOC_CLK 92 -#define MDSS_AHB_CLK 93 -#define MDSS_AXI_CLK 94 -#define MDSS_BYTE0_CLK 95 -#define MDSS_BYTE1_CLK 96 -#define MDSS_EDPAUX_CLK 97 -#define MDSS_EDPLINK_CLK 98 -#define MDSS_EDPPIXEL_CLK 99 -#define MDSS_ESC0_CLK 100 -#define MDSS_ESC1_CLK 101 -#define MDSS_EXTPCLK_CLK 102 -#define MDSS_HDMI_AHB_CLK 103 -#define MDSS_HDMI_CLK 104 -#define MDSS_MDP_CLK 105 -#define MDSS_MDP_LUT_CLK 106 -#define MDSS_PCLK0_CLK 107 -#define MDSS_PCLK1_CLK 108 -#define MDSS_VSYNC_CLK 109 -#define MMSS_MISC_AHB_CLK 110 -#define MMSS_MMSSNOC_AHB_CLK 111 -#define MMSS_MMSSNOC_BTO_AHB_CLK 112 -#define MMSS_MMSSNOC_AXI_CLK 113 -#define MMSS_S0_AXI_CLK 114 -#define OCMEMCX_AHB_CLK 115 -#define OCMEMCX_OCMEMNOC_CLK 116 -#define OXILI_OCMEMGX_CLK 117 -#define OCMEMNOC_CLK 118 -#define OXILI_GFX3D_CLK 119 -#define OXILICX_AHB_CLK 120 -#define OXILICX_AXI_CLK 121 -#define VENUS0_AHB_CLK 122 -#define VENUS0_AXI_CLK 123 -#define VENUS0_OCMEMNOC_CLK 124 -#define VENUS0_VCODEC0_CLK 125 -#define OCMEMNOC_CLK_SRC 126 -#define SPDM_JPEG0 127 -#define SPDM_JPEG1 128 -#define SPDM_MDP 129 -#define SPDM_AXI 130 -#define SPDM_VCODEC0 131 -#define SPDM_VFE0 132 -#define SPDM_VFE1 133 -#define SPDM_JPEG2 134 -#define SPDM_PCLK1 135 -#define SPDM_GFX3D 136 -#define SPDM_AHB 137 -#define SPDM_PCLK0 138 -#define SPDM_OCMEMNOC 139 -#define SPDM_CSI0 140 -#define SPDM_RM_AXI 141 -#define SPDM_RM_OCMEMNOC 142 - -/* gdscs */ -#define VENUS0_GDSC 0 -#define MDSS_GDSC 1 -#define CAMSS_JPEG_GDSC 2 -#define CAMSS_VFE_GDSC 3 -#define OXILI_GDSC 4 -#define OXILICX_GDSC 5 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/qcom,mmcc-msm8996.h b/sys/gnu/dts/include/dt-bindings/clock/qcom,mmcc-msm8996.h deleted file mode 100644 index d51f9ac7056..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/qcom,mmcc-msm8996.h +++ /dev/null @@ -1,295 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2015, The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_CLK_MSM_MMCC_8996_H -#define _DT_BINDINGS_CLK_MSM_MMCC_8996_H - -#define MMPLL0_EARLY 0 -#define MMPLL0_PLL 1 -#define MMPLL1_EARLY 2 -#define MMPLL1_PLL 3 -#define MMPLL2_EARLY 4 -#define MMPLL2_PLL 5 -#define MMPLL3_EARLY 6 -#define MMPLL3_PLL 7 -#define MMPLL4_EARLY 8 -#define MMPLL4_PLL 9 -#define MMPLL5_EARLY 10 -#define MMPLL5_PLL 11 -#define MMPLL8_EARLY 12 -#define MMPLL8_PLL 13 -#define MMPLL9_EARLY 14 -#define MMPLL9_PLL 15 -#define AHB_CLK_SRC 16 -#define AXI_CLK_SRC 17 -#define MAXI_CLK_SRC 18 -#define DSA_CORE_CLK_SRC 19 -#define GFX3D_CLK_SRC 20 -#define RBBMTIMER_CLK_SRC 21 -#define ISENSE_CLK_SRC 22 -#define RBCPR_CLK_SRC 23 -#define VIDEO_CORE_CLK_SRC 24 -#define VIDEO_SUBCORE0_CLK_SRC 25 -#define VIDEO_SUBCORE1_CLK_SRC 26 -#define PCLK0_CLK_SRC 27 -#define PCLK1_CLK_SRC 28 -#define MDP_CLK_SRC 29 -#define EXTPCLK_CLK_SRC 30 -#define VSYNC_CLK_SRC 31 -#define HDMI_CLK_SRC 32 -#define BYTE0_CLK_SRC 33 -#define BYTE1_CLK_SRC 34 -#define ESC0_CLK_SRC 35 -#define ESC1_CLK_SRC 36 -#define CAMSS_GP0_CLK_SRC 37 -#define CAMSS_GP1_CLK_SRC 38 -#define MCLK0_CLK_SRC 39 -#define MCLK1_CLK_SRC 40 -#define MCLK2_CLK_SRC 41 -#define MCLK3_CLK_SRC 42 -#define CCI_CLK_SRC 43 -#define CSI0PHYTIMER_CLK_SRC 44 -#define CSI1PHYTIMER_CLK_SRC 45 -#define CSI2PHYTIMER_CLK_SRC 46 -#define CSIPHY0_3P_CLK_SRC 47 -#define CSIPHY1_3P_CLK_SRC 48 -#define CSIPHY2_3P_CLK_SRC 49 -#define JPEG0_CLK_SRC 50 -#define JPEG2_CLK_SRC 51 -#define JPEG_DMA_CLK_SRC 52 -#define VFE0_CLK_SRC 53 -#define VFE1_CLK_SRC 54 -#define CPP_CLK_SRC 55 -#define CSI0_CLK_SRC 56 -#define CSI1_CLK_SRC 57 -#define CSI2_CLK_SRC 58 -#define CSI3_CLK_SRC 59 -#define FD_CORE_CLK_SRC 60 -#define MMSS_CXO_CLK 61 -#define MMSS_SLEEPCLK_CLK 62 -#define MMSS_MMAGIC_AHB_CLK 63 -#define MMSS_MMAGIC_CFG_AHB_CLK 64 -#define MMSS_MISC_AHB_CLK 65 -#define MMSS_MISC_CXO_CLK 66 -#define MMSS_BTO_AHB_CLK 67 -#define MMSS_MMAGIC_AXI_CLK 68 -#define MMSS_S0_AXI_CLK 69 -#define MMSS_MMAGIC_MAXI_CLK 70 -#define DSA_CORE_CLK 71 -#define DSA_NOC_CFG_AHB_CLK 72 -#define MMAGIC_CAMSS_AXI_CLK 73 -#define MMAGIC_CAMSS_NOC_CFG_AHB_CLK 74 -#define THROTTLE_CAMSS_CXO_CLK 75 -#define THROTTLE_CAMSS_AHB_CLK 76 -#define THROTTLE_CAMSS_AXI_CLK 77 -#define SMMU_VFE_AHB_CLK 78 -#define SMMU_VFE_AXI_CLK 79 -#define SMMU_CPP_AHB_CLK 80 -#define SMMU_CPP_AXI_CLK 81 -#define SMMU_JPEG_AHB_CLK 82 -#define SMMU_JPEG_AXI_CLK 83 -#define MMAGIC_MDSS_AXI_CLK 84 -#define MMAGIC_MDSS_NOC_CFG_AHB_CLK 85 -#define THROTTLE_MDSS_CXO_CLK 86 -#define THROTTLE_MDSS_AHB_CLK 87 -#define THROTTLE_MDSS_AXI_CLK 88 -#define SMMU_ROT_AHB_CLK 89 -#define SMMU_ROT_AXI_CLK 90 -#define SMMU_MDP_AHB_CLK 91 -#define SMMU_MDP_AXI_CLK 92 -#define MMAGIC_VIDEO_AXI_CLK 93 -#define MMAGIC_VIDEO_NOC_CFG_AHB_CLK 94 -#define THROTTLE_VIDEO_CXO_CLK 95 -#define THROTTLE_VIDEO_AHB_CLK 96 -#define THROTTLE_VIDEO_AXI_CLK 97 -#define SMMU_VIDEO_AHB_CLK 98 -#define SMMU_VIDEO_AXI_CLK 99 -#define MMAGIC_BIMC_AXI_CLK 100 -#define MMAGIC_BIMC_NOC_CFG_AHB_CLK 101 -#define GPU_GX_GFX3D_CLK 102 -#define GPU_GX_RBBMTIMER_CLK 103 -#define GPU_AHB_CLK 104 -#define GPU_AON_ISENSE_CLK 105 -#define VMEM_MAXI_CLK 106 -#define VMEM_AHB_CLK 107 -#define MMSS_RBCPR_CLK 108 -#define MMSS_RBCPR_AHB_CLK 109 -#define VIDEO_CORE_CLK 110 -#define VIDEO_AXI_CLK 111 -#define VIDEO_MAXI_CLK 112 -#define VIDEO_AHB_CLK 113 -#define VIDEO_SUBCORE0_CLK 114 -#define VIDEO_SUBCORE1_CLK 115 -#define MDSS_AHB_CLK 116 -#define MDSS_HDMI_AHB_CLK 117 -#define MDSS_AXI_CLK 118 -#define MDSS_PCLK0_CLK 119 -#define MDSS_PCLK1_CLK 120 -#define MDSS_MDP_CLK 121 -#define MDSS_EXTPCLK_CLK 122 -#define MDSS_VSYNC_CLK 123 -#define MDSS_HDMI_CLK 124 -#define MDSS_BYTE0_CLK 125 -#define MDSS_BYTE1_CLK 126 -#define MDSS_ESC0_CLK 127 -#define MDSS_ESC1_CLK 128 -#define CAMSS_TOP_AHB_CLK 129 -#define CAMSS_AHB_CLK 130 -#define CAMSS_MICRO_AHB_CLK 131 -#define CAMSS_GP0_CLK 132 -#define CAMSS_GP1_CLK 133 -#define CAMSS_MCLK0_CLK 134 -#define CAMSS_MCLK1_CLK 135 -#define CAMSS_MCLK2_CLK 136 -#define CAMSS_MCLK3_CLK 137 -#define CAMSS_CCI_CLK 138 -#define CAMSS_CCI_AHB_CLK 139 -#define CAMSS_CSI0PHYTIMER_CLK 140 -#define CAMSS_CSI1PHYTIMER_CLK 141 -#define CAMSS_CSI2PHYTIMER_CLK 142 -#define CAMSS_CSIPHY0_3P_CLK 143 -#define CAMSS_CSIPHY1_3P_CLK 144 -#define CAMSS_CSIPHY2_3P_CLK 145 -#define CAMSS_JPEG0_CLK 146 -#define CAMSS_JPEG2_CLK 147 -#define CAMSS_JPEG_DMA_CLK 148 -#define CAMSS_JPEG_AHB_CLK 149 -#define CAMSS_JPEG_AXI_CLK 150 -#define CAMSS_VFE_AHB_CLK 151 -#define CAMSS_VFE_AXI_CLK 152 -#define CAMSS_VFE0_CLK 153 -#define CAMSS_VFE0_STREAM_CLK 154 -#define CAMSS_VFE0_AHB_CLK 155 -#define CAMSS_VFE1_CLK 156 -#define CAMSS_VFE1_STREAM_CLK 157 -#define CAMSS_VFE1_AHB_CLK 158 -#define CAMSS_CSI_VFE0_CLK 159 -#define CAMSS_CSI_VFE1_CLK 160 -#define CAMSS_CPP_VBIF_AHB_CLK 161 -#define CAMSS_CPP_AXI_CLK 162 -#define CAMSS_CPP_CLK 163 -#define CAMSS_CPP_AHB_CLK 164 -#define CAMSS_CSI0_CLK 165 -#define CAMSS_CSI0_AHB_CLK 166 -#define CAMSS_CSI0PHY_CLK 167 -#define CAMSS_CSI0RDI_CLK 168 -#define CAMSS_CSI0PIX_CLK 169 -#define CAMSS_CSI1_CLK 170 -#define CAMSS_CSI1_AHB_CLK 171 -#define CAMSS_CSI1PHY_CLK 172 -#define CAMSS_CSI1RDI_CLK 173 -#define CAMSS_CSI1PIX_CLK 174 -#define CAMSS_CSI2_CLK 175 -#define CAMSS_CSI2_AHB_CLK 176 -#define CAMSS_CSI2PHY_CLK 177 -#define CAMSS_CSI2RDI_CLK 178 -#define CAMSS_CSI2PIX_CLK 179 -#define CAMSS_CSI3_CLK 180 -#define CAMSS_CSI3_AHB_CLK 181 -#define CAMSS_CSI3PHY_CLK 182 -#define CAMSS_CSI3RDI_CLK 183 -#define CAMSS_CSI3PIX_CLK 184 -#define CAMSS_ISPIF_AHB_CLK 185 -#define FD_CORE_CLK 186 -#define FD_CORE_UAR_CLK 187 -#define FD_AHB_CLK 188 -#define MMSS_SPDM_CSI0_CLK 189 -#define MMSS_SPDM_JPEG_DMA_CLK 190 -#define MMSS_SPDM_CPP_CLK 191 -#define MMSS_SPDM_PCLK0_CLK 192 -#define MMSS_SPDM_AHB_CLK 193 -#define MMSS_SPDM_GFX3D_CLK 194 -#define MMSS_SPDM_PCLK1_CLK 195 -#define MMSS_SPDM_JPEG2_CLK 196 -#define MMSS_SPDM_DEBUG_CLK 197 -#define MMSS_SPDM_VFE1_CLK 198 -#define MMSS_SPDM_VFE0_CLK 199 -#define MMSS_SPDM_VIDEO_CORE_CLK 200 -#define MMSS_SPDM_AXI_CLK 201 -#define MMSS_SPDM_MDP_CLK 202 -#define MMSS_SPDM_JPEG0_CLK 203 -#define MMSS_SPDM_RM_AXI_CLK 204 -#define MMSS_SPDM_RM_MAXI_CLK 205 - -#define MMAGICAHB_BCR 0 -#define MMAGIC_CFG_BCR 1 -#define MISC_BCR 2 -#define BTO_BCR 3 -#define MMAGICAXI_BCR 4 -#define MMAGICMAXI_BCR 5 -#define DSA_BCR 6 -#define MMAGIC_CAMSS_BCR 7 -#define THROTTLE_CAMSS_BCR 8 -#define SMMU_VFE_BCR 9 -#define SMMU_CPP_BCR 10 -#define SMMU_JPEG_BCR 11 -#define MMAGIC_MDSS_BCR 12 -#define THROTTLE_MDSS_BCR 13 -#define SMMU_ROT_BCR 14 -#define SMMU_MDP_BCR 15 -#define MMAGIC_VIDEO_BCR 16 -#define THROTTLE_VIDEO_BCR 17 -#define SMMU_VIDEO_BCR 18 -#define MMAGIC_BIMC_BCR 19 -#define GPU_GX_BCR 20 -#define GPU_BCR 21 -#define GPU_AON_BCR 22 -#define VMEM_BCR 23 -#define MMSS_RBCPR_BCR 24 -#define VIDEO_BCR 25 -#define MDSS_BCR 26 -#define CAMSS_TOP_BCR 27 -#define CAMSS_AHB_BCR 28 -#define CAMSS_MICRO_BCR 29 -#define CAMSS_CCI_BCR 30 -#define CAMSS_PHY0_BCR 31 -#define CAMSS_PHY1_BCR 32 -#define CAMSS_PHY2_BCR 33 -#define CAMSS_CSIPHY0_3P_BCR 34 -#define CAMSS_CSIPHY1_3P_BCR 35 -#define CAMSS_CSIPHY2_3P_BCR 36 -#define CAMSS_JPEG_BCR 37 -#define CAMSS_VFE_BCR 38 -#define CAMSS_VFE0_BCR 39 -#define CAMSS_VFE1_BCR 40 -#define CAMSS_CSI_VFE0_BCR 41 -#define CAMSS_CSI_VFE1_BCR 42 -#define CAMSS_CPP_TOP_BCR 43 -#define CAMSS_CPP_BCR 44 -#define CAMSS_CSI0_BCR 45 -#define CAMSS_CSI0RDI_BCR 46 -#define CAMSS_CSI0PIX_BCR 47 -#define CAMSS_CSI1_BCR 48 -#define CAMSS_CSI1RDI_BCR 49 -#define CAMSS_CSI1PIX_BCR 50 -#define CAMSS_CSI2_BCR 51 -#define CAMSS_CSI2RDI_BCR 52 -#define CAMSS_CSI2PIX_BCR 53 -#define CAMSS_CSI3_BCR 54 -#define CAMSS_CSI3RDI_BCR 55 -#define CAMSS_CSI3PIX_BCR 56 -#define CAMSS_ISPIF_BCR 57 -#define FD_BCR 58 -#define MMSS_SPDM_RM_BCR 59 - -/* Indexes for GDSCs */ -#define MMAGIC_VIDEO_GDSC 0 -#define MMAGIC_MDSS_GDSC 1 -#define MMAGIC_CAMSS_GDSC 2 -#define GPU_GDSC 3 -#define VENUS_GDSC 4 -#define VENUS_CORE0_GDSC 5 -#define VENUS_CORE1_GDSC 6 -#define CAMSS_GDSC 7 -#define VFE0_GDSC 8 -#define VFE1_GDSC 9 -#define JPEG_GDSC 10 -#define CPP_GDSC 11 -#define FD_GDSC 12 -#define MDSS_GDSC 13 -#define GPU_GX_GDSC 14 -#define MMAGIC_BIMC_GDSC 15 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/qcom,mmcc-msm8998.h b/sys/gnu/dts/include/dt-bindings/clock/qcom,mmcc-msm8998.h deleted file mode 100644 index ecbafdb930a..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/qcom,mmcc-msm8998.h +++ /dev/null @@ -1,210 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_CLK_MSM_MMCC_8998_H -#define _DT_BINDINGS_CLK_MSM_MMCC_8998_H - -#define MMPLL0 0 -#define MMPLL0_OUT_EVEN 1 -#define MMPLL1 2 -#define MMPLL1_OUT_EVEN 3 -#define MMPLL3 4 -#define MMPLL3_OUT_EVEN 5 -#define MMPLL4 6 -#define MMPLL4_OUT_EVEN 7 -#define MMPLL5 8 -#define MMPLL5_OUT_EVEN 9 -#define MMPLL6 10 -#define MMPLL6_OUT_EVEN 11 -#define MMPLL7 12 -#define MMPLL7_OUT_EVEN 13 -#define MMPLL10 14 -#define MMPLL10_OUT_EVEN 15 -#define BYTE0_CLK_SRC 16 -#define BYTE1_CLK_SRC 17 -#define CCI_CLK_SRC 18 -#define CPP_CLK_SRC 19 -#define CSI0_CLK_SRC 20 -#define CSI1_CLK_SRC 21 -#define CSI2_CLK_SRC 22 -#define CSI3_CLK_SRC 23 -#define CSIPHY_CLK_SRC 24 -#define CSI0PHYTIMER_CLK_SRC 25 -#define CSI1PHYTIMER_CLK_SRC 26 -#define CSI2PHYTIMER_CLK_SRC 27 -#define DP_AUX_CLK_SRC 28 -#define DP_CRYPTO_CLK_SRC 29 -#define DP_LINK_CLK_SRC 30 -#define DP_PIXEL_CLK_SRC 31 -#define ESC0_CLK_SRC 32 -#define ESC1_CLK_SRC 33 -#define EXTPCLK_CLK_SRC 34 -#define FD_CORE_CLK_SRC 35 -#define HDMI_CLK_SRC 36 -#define JPEG0_CLK_SRC 37 -#define MAXI_CLK_SRC 38 -#define MCLK0_CLK_SRC 39 -#define MCLK1_CLK_SRC 40 -#define MCLK2_CLK_SRC 41 -#define MCLK3_CLK_SRC 42 -#define MDP_CLK_SRC 43 -#define VSYNC_CLK_SRC 44 -#define AHB_CLK_SRC 45 -#define AXI_CLK_SRC 46 -#define PCLK0_CLK_SRC 47 -#define PCLK1_CLK_SRC 48 -#define ROT_CLK_SRC 49 -#define VIDEO_CORE_CLK_SRC 50 -#define VIDEO_SUBCORE0_CLK_SRC 51 -#define VIDEO_SUBCORE1_CLK_SRC 52 -#define VFE0_CLK_SRC 53 -#define VFE1_CLK_SRC 54 -#define MISC_AHB_CLK 55 -#define VIDEO_CORE_CLK 56 -#define VIDEO_AHB_CLK 57 -#define VIDEO_AXI_CLK 58 -#define VIDEO_MAXI_CLK 59 -#define VIDEO_SUBCORE0_CLK 60 -#define VIDEO_SUBCORE1_CLK 61 -#define MDSS_AHB_CLK 62 -#define MDSS_HDMI_DP_AHB_CLK 63 -#define MDSS_AXI_CLK 64 -#define MDSS_PCLK0_CLK 65 -#define MDSS_PCLK1_CLK 66 -#define MDSS_MDP_CLK 67 -#define MDSS_MDP_LUT_CLK 68 -#define MDSS_EXTPCLK_CLK 69 -#define MDSS_VSYNC_CLK 70 -#define MDSS_HDMI_CLK 71 -#define MDSS_BYTE0_CLK 72 -#define MDSS_BYTE1_CLK 73 -#define MDSS_ESC0_CLK 74 -#define MDSS_ESC1_CLK 75 -#define MDSS_ROT_CLK 76 -#define MDSS_DP_LINK_CLK 77 -#define MDSS_DP_LINK_INTF_CLK 78 -#define MDSS_DP_CRYPTO_CLK 79 -#define MDSS_DP_PIXEL_CLK 80 -#define MDSS_DP_AUX_CLK 81 -#define MDSS_BYTE0_INTF_CLK 82 -#define MDSS_BYTE1_INTF_CLK 83 -#define CAMSS_CSI0PHYTIMER_CLK 84 -#define CAMSS_CSI1PHYTIMER_CLK 85 -#define CAMSS_CSI2PHYTIMER_CLK 86 -#define CAMSS_CSI0_CLK 87 -#define CAMSS_CSI0_AHB_CLK 88 -#define CAMSS_CSI0RDI_CLK 89 -#define CAMSS_CSI0PIX_CLK 90 -#define CAMSS_CSI1_CLK 91 -#define CAMSS_CSI1_AHB_CLK 92 -#define CAMSS_CSI1RDI_CLK 93 -#define CAMSS_CSI1PIX_CLK 94 -#define CAMSS_CSI2_CLK 95 -#define CAMSS_CSI2_AHB_CLK 96 -#define CAMSS_CSI2RDI_CLK 97 -#define CAMSS_CSI2PIX_CLK 98 -#define CAMSS_CSI3_CLK 99 -#define CAMSS_CSI3_AHB_CLK 100 -#define CAMSS_CSI3RDI_CLK 101 -#define CAMSS_CSI3PIX_CLK 102 -#define CAMSS_ISPIF_AHB_CLK 103 -#define CAMSS_CCI_CLK 104 -#define CAMSS_CCI_AHB_CLK 105 -#define CAMSS_MCLK0_CLK 106 -#define CAMSS_MCLK1_CLK 107 -#define CAMSS_MCLK2_CLK 108 -#define CAMSS_MCLK3_CLK 109 -#define CAMSS_TOP_AHB_CLK 110 -#define CAMSS_AHB_CLK 111 -#define CAMSS_MICRO_AHB_CLK 112 -#define CAMSS_JPEG0_CLK 113 -#define CAMSS_JPEG_AHB_CLK 114 -#define CAMSS_JPEG_AXI_CLK 115 -#define CAMSS_VFE0_AHB_CLK 116 -#define CAMSS_VFE1_AHB_CLK 117 -#define CAMSS_VFE0_CLK 118 -#define CAMSS_VFE1_CLK 119 -#define CAMSS_CPP_CLK 120 -#define CAMSS_CPP_AHB_CLK 121 -#define CAMSS_VFE_VBIF_AHB_CLK 122 -#define CAMSS_VFE_VBIF_AXI_CLK 123 -#define CAMSS_CPP_AXI_CLK 124 -#define CAMSS_CPP_VBIF_AHB_CLK 125 -#define CAMSS_CSI_VFE0_CLK 126 -#define CAMSS_CSI_VFE1_CLK 127 -#define CAMSS_VFE0_STREAM_CLK 128 -#define CAMSS_VFE1_STREAM_CLK 129 -#define CAMSS_CPHY_CSID0_CLK 130 -#define CAMSS_CPHY_CSID1_CLK 131 -#define CAMSS_CPHY_CSID2_CLK 132 -#define CAMSS_CPHY_CSID3_CLK 133 -#define CAMSS_CSIPHY0_CLK 134 -#define CAMSS_CSIPHY1_CLK 135 -#define CAMSS_CSIPHY2_CLK 136 -#define FD_CORE_CLK 137 -#define FD_CORE_UAR_CLK 138 -#define FD_AHB_CLK 139 -#define MNOC_AHB_CLK 140 -#define BIMC_SMMU_AHB_CLK 141 -#define BIMC_SMMU_AXI_CLK 142 -#define MNOC_MAXI_CLK 143 -#define VMEM_MAXI_CLK 144 -#define VMEM_AHB_CLK 145 - -#define SPDM_BCR 0 -#define SPDM_RM_BCR 1 -#define MISC_BCR 2 -#define VIDEO_TOP_BCR 3 -#define THROTTLE_VIDEO_BCR 4 -#define MDSS_BCR 5 -#define THROTTLE_MDSS_BCR 6 -#define CAMSS_PHY0_BCR 7 -#define CAMSS_PHY1_BCR 8 -#define CAMSS_PHY2_BCR 9 -#define CAMSS_CSI0_BCR 10 -#define CAMSS_CSI0RDI_BCR 11 -#define CAMSS_CSI0PIX_BCR 12 -#define CAMSS_CSI1_BCR 13 -#define CAMSS_CSI1RDI_BCR 14 -#define CAMSS_CSI1PIX_BCR 15 -#define CAMSS_CSI2_BCR 16 -#define CAMSS_CSI2RDI_BCR 17 -#define CAMSS_CSI2PIX_BCR 18 -#define CAMSS_CSI3_BCR 19 -#define CAMSS_CSI3RDI_BCR 20 -#define CAMSS_CSI3PIX_BCR 21 -#define CAMSS_ISPIF_BCR 22 -#define CAMSS_CCI_BCR 23 -#define CAMSS_TOP_BCR 24 -#define CAMSS_AHB_BCR 25 -#define CAMSS_MICRO_BCR 26 -#define CAMSS_JPEG_BCR 27 -#define CAMSS_VFE0_BCR 28 -#define CAMSS_VFE1_BCR 29 -#define CAMSS_VFE_VBIF_BCR 30 -#define CAMSS_CPP_TOP_BCR 31 -#define CAMSS_CPP_BCR 32 -#define CAMSS_CSI_VFE0_BCR 33 -#define CAMSS_CSI_VFE1_BCR 34 -#define CAMSS_FD_BCR 35 -#define THROTTLE_CAMSS_BCR 36 -#define MNOCAHB_BCR 37 -#define MNOCAXI_BCR 38 -#define BMIC_SMMU_BCR 39 -#define MNOC_MAXI_BCR 40 -#define VMEM_BCR 41 -#define BTO_BCR 42 - -#define VIDEO_TOP_GDSC 1 -#define VIDEO_SUBCORE0_GDSC 2 -#define VIDEO_SUBCORE1_GDSC 3 -#define MDSS_GDSC 4 -#define CAMSS_TOP_GDSC 5 -#define CAMSS_VFE0_GDSC 6 -#define CAMSS_VFE1_GDSC 7 -#define CAMSS_CPP_GDSC 8 -#define BIMC_SMMU_GDSC 9 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/qcom,q6sstopcc-qcs404.h b/sys/gnu/dts/include/dt-bindings/clock/qcom,q6sstopcc-qcs404.h deleted file mode 100644 index c6f5290f091..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/qcom,q6sstopcc-qcs404.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_CLK_Q6SSTOP_QCS404_H -#define _DT_BINDINGS_CLK_Q6SSTOP_QCS404_H - -#define LCC_AHBFABRIC_CBC_CLK 0 -#define LCC_Q6SS_AHBS_CBC_CLK 1 -#define LCC_Q6SS_TCM_SLAVE_CBC_CLK 2 -#define LCC_Q6SS_AHBM_CBC_CLK 3 -#define LCC_Q6SS_AXIM_CBC_CLK 4 -#define LCC_Q6SS_BCR_SLEEP_CLK 5 -#define TCSR_Q6SS_LCC_CBCR_CLK 6 - -#define Q6SSTOP_BCR_RESET 1 -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/qcom,rpmcc.h b/sys/gnu/dts/include/dt-bindings/clock/qcom,rpmcc.h deleted file mode 100644 index 8e309572055..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/qcom,rpmcc.h +++ /dev/null @@ -1,133 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2015 Linaro Limited - */ - -#ifndef _DT_BINDINGS_CLK_MSM_RPMCC_H -#define _DT_BINDINGS_CLK_MSM_RPMCC_H - -/* RPM clocks */ -#define RPM_PXO_CLK 0 -#define RPM_PXO_A_CLK 1 -#define RPM_CXO_CLK 2 -#define RPM_CXO_A_CLK 3 -#define RPM_APPS_FABRIC_CLK 4 -#define RPM_APPS_FABRIC_A_CLK 5 -#define RPM_CFPB_CLK 6 -#define RPM_CFPB_A_CLK 7 -#define RPM_QDSS_CLK 8 -#define RPM_QDSS_A_CLK 9 -#define RPM_DAYTONA_FABRIC_CLK 10 -#define RPM_DAYTONA_FABRIC_A_CLK 11 -#define RPM_EBI1_CLK 12 -#define RPM_EBI1_A_CLK 13 -#define RPM_MM_FABRIC_CLK 14 -#define RPM_MM_FABRIC_A_CLK 15 -#define RPM_MMFPB_CLK 16 -#define RPM_MMFPB_A_CLK 17 -#define RPM_SYS_FABRIC_CLK 18 -#define RPM_SYS_FABRIC_A_CLK 19 -#define RPM_SFPB_CLK 20 -#define RPM_SFPB_A_CLK 21 -#define RPM_SMI_CLK 22 -#define RPM_SMI_A_CLK 23 -#define RPM_PLL4_CLK 24 -#define RPM_XO_D0 25 -#define RPM_XO_D1 26 -#define RPM_XO_A0 27 -#define RPM_XO_A1 28 -#define RPM_XO_A2 29 - -/* SMD RPM clocks */ -#define RPM_SMD_XO_CLK_SRC 0 -#define RPM_SMD_XO_A_CLK_SRC 1 -#define RPM_SMD_PCNOC_CLK 2 -#define RPM_SMD_PCNOC_A_CLK 3 -#define RPM_SMD_SNOC_CLK 4 -#define RPM_SMD_SNOC_A_CLK 5 -#define RPM_SMD_BIMC_CLK 6 -#define RPM_SMD_BIMC_A_CLK 7 -#define RPM_SMD_QDSS_CLK 8 -#define RPM_SMD_QDSS_A_CLK 9 -#define RPM_SMD_BB_CLK1 10 -#define RPM_SMD_BB_CLK1_A 11 -#define RPM_SMD_BB_CLK2 12 -#define RPM_SMD_BB_CLK2_A 13 -#define RPM_SMD_RF_CLK1 14 -#define RPM_SMD_RF_CLK1_A 15 -#define RPM_SMD_RF_CLK2 16 -#define RPM_SMD_RF_CLK2_A 17 -#define RPM_SMD_BB_CLK1_PIN 18 -#define RPM_SMD_BB_CLK1_A_PIN 19 -#define RPM_SMD_BB_CLK2_PIN 20 -#define RPM_SMD_BB_CLK2_A_PIN 21 -#define RPM_SMD_RF_CLK1_PIN 22 -#define RPM_SMD_RF_CLK1_A_PIN 23 -#define RPM_SMD_RF_CLK2_PIN 24 -#define RPM_SMD_RF_CLK2_A_PIN 25 -#define RPM_SMD_PNOC_CLK 26 -#define RPM_SMD_PNOC_A_CLK 27 -#define RPM_SMD_CNOC_CLK 28 -#define RPM_SMD_CNOC_A_CLK 29 -#define RPM_SMD_MMSSNOC_AHB_CLK 30 -#define RPM_SMD_MMSSNOC_AHB_A_CLK 31 -#define RPM_SMD_GFX3D_CLK_SRC 32 -#define RPM_SMD_GFX3D_A_CLK_SRC 33 -#define RPM_SMD_OCMEMGX_CLK 34 -#define RPM_SMD_OCMEMGX_A_CLK 35 -#define RPM_SMD_CXO_D0 36 -#define RPM_SMD_CXO_D0_A 37 -#define RPM_SMD_CXO_D1 38 -#define RPM_SMD_CXO_D1_A 39 -#define RPM_SMD_CXO_A0 40 -#define RPM_SMD_CXO_A0_A 41 -#define RPM_SMD_CXO_A1 42 -#define RPM_SMD_CXO_A1_A 43 -#define RPM_SMD_CXO_A2 44 -#define RPM_SMD_CXO_A2_A 45 -#define RPM_SMD_DIV_CLK1 46 -#define RPM_SMD_DIV_A_CLK1 47 -#define RPM_SMD_DIV_CLK2 48 -#define RPM_SMD_DIV_A_CLK2 49 -#define RPM_SMD_DIFF_CLK 50 -#define RPM_SMD_DIFF_A_CLK 51 -#define RPM_SMD_CXO_D0_PIN 52 -#define RPM_SMD_CXO_D0_A_PIN 53 -#define RPM_SMD_CXO_D1_PIN 54 -#define RPM_SMD_CXO_D1_A_PIN 55 -#define RPM_SMD_CXO_A0_PIN 56 -#define RPM_SMD_CXO_A0_A_PIN 57 -#define RPM_SMD_CXO_A1_PIN 58 -#define RPM_SMD_CXO_A1_A_PIN 59 -#define RPM_SMD_CXO_A2_PIN 60 -#define RPM_SMD_CXO_A2_A_PIN 61 -#define RPM_SMD_AGGR1_NOC_CLK 62 -#define RPM_SMD_AGGR1_NOC_A_CLK 63 -#define RPM_SMD_AGGR2_NOC_CLK 64 -#define RPM_SMD_AGGR2_NOC_A_CLK 65 -#define RPM_SMD_MMAXI_CLK 66 -#define RPM_SMD_MMAXI_A_CLK 67 -#define RPM_SMD_IPA_CLK 68 -#define RPM_SMD_IPA_A_CLK 69 -#define RPM_SMD_CE1_CLK 70 -#define RPM_SMD_CE1_A_CLK 71 -#define RPM_SMD_DIV_CLK3 72 -#define RPM_SMD_DIV_A_CLK3 73 -#define RPM_SMD_LN_BB_CLK 74 -#define RPM_SMD_LN_BB_A_CLK 75 -#define RPM_SMD_BIMC_GPU_CLK 76 -#define RPM_SMD_BIMC_GPU_A_CLK 77 -#define RPM_SMD_QPIC_CLK 78 -#define RPM_SMD_QPIC_CLK_A 79 -#define RPM_SMD_LN_BB_CLK1 80 -#define RPM_SMD_LN_BB_CLK1_A 81 -#define RPM_SMD_LN_BB_CLK2 82 -#define RPM_SMD_LN_BB_CLK2_A 83 -#define RPM_SMD_LN_BB_CLK3_PIN 84 -#define RPM_SMD_LN_BB_CLK3_A_PIN 85 -#define RPM_SMD_RF_CLK3 86 -#define RPM_SMD_RF_CLK3_A 87 -#define RPM_SMD_RF_CLK3_PIN 88 -#define RPM_SMD_RF_CLK3_A_PIN 89 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/qcom,rpmh.h b/sys/gnu/dts/include/dt-bindings/clock/qcom,rpmh.h deleted file mode 100644 index edcab3f7b7d..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/qcom,rpmh.h +++ /dev/null @@ -1,23 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* Copyright (c) 2018, The Linux Foundation. All rights reserved. */ - - -#ifndef _DT_BINDINGS_CLK_MSM_RPMH_H -#define _DT_BINDINGS_CLK_MSM_RPMH_H - -/* RPMh controlled clocks */ -#define RPMH_CXO_CLK 0 -#define RPMH_CXO_CLK_A 1 -#define RPMH_LN_BB_CLK2 2 -#define RPMH_LN_BB_CLK2_A 3 -#define RPMH_LN_BB_CLK3 4 -#define RPMH_LN_BB_CLK3_A 5 -#define RPMH_RF_CLK1 6 -#define RPMH_RF_CLK1_A 7 -#define RPMH_RF_CLK2 8 -#define RPMH_RF_CLK2_A 9 -#define RPMH_RF_CLK3 10 -#define RPMH_RF_CLK3_A 11 -#define RPMH_IPA_CLK 12 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/qcom,turingcc-qcs404.h b/sys/gnu/dts/include/dt-bindings/clock/qcom,turingcc-qcs404.h deleted file mode 100644 index 838faef57c6..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/qcom,turingcc-qcs404.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2019, Linaro Ltd - */ - -#ifndef _DT_BINDINGS_CLK_TURING_QCS404_H -#define _DT_BINDINGS_CLK_TURING_QCS404_H - -#define TURING_Q6SS_Q6_AXIM_CLK 0 -#define TURING_Q6SS_AHBM_AON_CLK 1 -#define TURING_WRAPPER_AON_CLK 2 -#define TURING_Q6SS_AHBS_AON_CLK 3 -#define TURING_WRAPPER_QOS_AHBS_AON_CLK 4 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/qcom,videocc-sc7180.h b/sys/gnu/dts/include/dt-bindings/clock/qcom,videocc-sc7180.h deleted file mode 100644 index 7acaf1366b1..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/qcom,videocc-sc7180.h +++ /dev/null @@ -1,23 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SC7180_H -#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SC7180_H - -/* VIDEO_CC clocks */ -#define VIDEO_PLL0 0 -#define VIDEO_CC_VCODEC0_AXI_CLK 1 -#define VIDEO_CC_VCODEC0_CORE_CLK 2 -#define VIDEO_CC_VENUS_AHB_CLK 3 -#define VIDEO_CC_VENUS_CLK_SRC 4 -#define VIDEO_CC_VENUS_CTL_AXI_CLK 5 -#define VIDEO_CC_VENUS_CTL_CORE_CLK 6 -#define VIDEO_CC_XO_CLK 7 - -/* VIDEO_CC GDSCRs */ -#define VENUS_GDSC 0 -#define VCODEC0_GDSC 1 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/qcom,videocc-sdm845.h b/sys/gnu/dts/include/dt-bindings/clock/qcom,videocc-sdm845.h deleted file mode 100644 index 1b868165e8c..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/qcom,videocc-sdm845.h +++ /dev/null @@ -1,35 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_CLK_SDM_VIDEO_CC_SDM845_H -#define _DT_BINDINGS_CLK_SDM_VIDEO_CC_SDM845_H - -/* VIDEO_CC clock registers */ -#define VIDEO_CC_APB_CLK 0 -#define VIDEO_CC_AT_CLK 1 -#define VIDEO_CC_QDSS_TRIG_CLK 2 -#define VIDEO_CC_QDSS_TSCTR_DIV8_CLK 3 -#define VIDEO_CC_VCODEC0_AXI_CLK 4 -#define VIDEO_CC_VCODEC0_CORE_CLK 5 -#define VIDEO_CC_VCODEC1_AXI_CLK 6 -#define VIDEO_CC_VCODEC1_CORE_CLK 7 -#define VIDEO_CC_VENUS_AHB_CLK 8 -#define VIDEO_CC_VENUS_CLK_SRC 9 -#define VIDEO_CC_VENUS_CTL_AXI_CLK 10 -#define VIDEO_CC_VENUS_CTL_CORE_CLK 11 -#define VIDEO_PLL0 12 - -/* VIDEO_CC Resets */ -#define VIDEO_CC_VENUS_BCR 0 -#define VIDEO_CC_VCODEC0_BCR 1 -#define VIDEO_CC_VCODEC1_BCR 2 -#define VIDEO_CC_INTERFACE_BCR 3 - -/* VIDEO_CC GDSCRs */ -#define VENUS_GDSC 0 -#define VCODEC0_GDSC 1 -#define VCODEC1_GDSC 2 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/r7s72100-clock.h b/sys/gnu/dts/include/dt-bindings/clock/r7s72100-clock.h deleted file mode 100644 index a267ac25014..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/r7s72100-clock.h +++ /dev/null @@ -1,112 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 - * - * Copyright (C) 2014 Renesas Solutions Corp. - * Copyright (C) 2014 Wolfram Sang, Sang Engineering - */ - -#ifndef __DT_BINDINGS_CLOCK_R7S72100_H__ -#define __DT_BINDINGS_CLOCK_R7S72100_H__ - -#define R7S72100_CLK_PLL 0 -#define R7S72100_CLK_I 1 -#define R7S72100_CLK_G 2 - -/* MSTP2 */ -#define R7S72100_CLK_CORESIGHT 0 - -/* MSTP3 */ -#define R7S72100_CLK_IEBUS 7 -#define R7S72100_CLK_IRDA 6 -#define R7S72100_CLK_LIN0 5 -#define R7S72100_CLK_LIN1 4 -#define R7S72100_CLK_MTU2 3 -#define R7S72100_CLK_CAN 2 -#define R7S72100_CLK_ADCPWR 1 -#define R7S72100_CLK_PWM 0 - -/* MSTP4 */ -#define R7S72100_CLK_SCIF0 7 -#define R7S72100_CLK_SCIF1 6 -#define R7S72100_CLK_SCIF2 5 -#define R7S72100_CLK_SCIF3 4 -#define R7S72100_CLK_SCIF4 3 -#define R7S72100_CLK_SCIF5 2 -#define R7S72100_CLK_SCIF6 1 -#define R7S72100_CLK_SCIF7 0 - -/* MSTP5 */ -#define R7S72100_CLK_SCI0 7 -#define R7S72100_CLK_SCI1 6 -#define R7S72100_CLK_SG0 5 -#define R7S72100_CLK_SG1 4 -#define R7S72100_CLK_SG2 3 -#define R7S72100_CLK_SG3 2 -#define R7S72100_CLK_OSTM0 1 -#define R7S72100_CLK_OSTM1 0 - -/* MSTP6 */ -#define R7S72100_CLK_ADC 7 -#define R7S72100_CLK_CEU 6 -#define R7S72100_CLK_DOC0 5 -#define R7S72100_CLK_DOC1 4 -#define R7S72100_CLK_DRC0 3 -#define R7S72100_CLK_DRC1 2 -#define R7S72100_CLK_JCU 1 -#define R7S72100_CLK_RTC 0 - -/* MSTP7 */ -#define R7S72100_CLK_VDEC0 7 -#define R7S72100_CLK_VDEC1 6 -#define R7S72100_CLK_ETHER 4 -#define R7S72100_CLK_NAND 3 -#define R7S72100_CLK_USB0 1 -#define R7S72100_CLK_USB1 0 - -/* MSTP8 */ -#define R7S72100_CLK_IMR0 7 -#define R7S72100_CLK_IMR1 6 -#define R7S72100_CLK_IMRDISP 5 -#define R7S72100_CLK_MMCIF 4 -#define R7S72100_CLK_MLB 3 -#define R7S72100_CLK_ETHAVB 2 -#define R7S72100_CLK_SCUX 1 - -/* MSTP9 */ -#define R7S72100_CLK_I2C0 7 -#define R7S72100_CLK_I2C1 6 -#define R7S72100_CLK_I2C2 5 -#define R7S72100_CLK_I2C3 4 -#define R7S72100_CLK_SPIBSC0 3 -#define R7S72100_CLK_SPIBSC1 2 -#define R7S72100_CLK_VDC50 1 /* and LVDS */ -#define R7S72100_CLK_VDC51 0 - -/* MSTP10 */ -#define R7S72100_CLK_SPI0 7 -#define R7S72100_CLK_SPI1 6 -#define R7S72100_CLK_SPI2 5 -#define R7S72100_CLK_SPI3 4 -#define R7S72100_CLK_SPI4 3 -#define R7S72100_CLK_CDROM 2 -#define R7S72100_CLK_SPDIF 1 -#define R7S72100_CLK_RGPVG2 0 - -/* MSTP11 */ -#define R7S72100_CLK_SSI0 5 -#define R7S72100_CLK_SSI1 4 -#define R7S72100_CLK_SSI2 3 -#define R7S72100_CLK_SSI3 2 -#define R7S72100_CLK_SSI4 1 -#define R7S72100_CLK_SSI5 0 - -/* MSTP12 */ -#define R7S72100_CLK_SDHI00 3 -#define R7S72100_CLK_SDHI01 2 -#define R7S72100_CLK_SDHI10 1 -#define R7S72100_CLK_SDHI11 0 - -/* MSTP13 */ -#define R7S72100_CLK_PIX1 2 -#define R7S72100_CLK_PIX0 1 - -#endif /* __DT_BINDINGS_CLOCK_R7S72100_H__ */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/r7s9210-cpg-mssr.h b/sys/gnu/dts/include/dt-bindings/clock/r7s9210-cpg-mssr.h deleted file mode 100644 index b6f85ca149a..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/r7s9210-cpg-mssr.h +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 - * - * Copyright (C) 2018 Renesas Electronics Corp. - * - */ - -#ifndef __DT_BINDINGS_CLOCK_R7S9210_CPG_MSSR_H__ -#define __DT_BINDINGS_CLOCK_R7S9210_CPG_MSSR_H__ - -#include - -/* R7S9210 CPG Core Clocks */ -#define R7S9210_CLK_I 0 -#define R7S9210_CLK_G 1 -#define R7S9210_CLK_B 2 -#define R7S9210_CLK_P1 3 -#define R7S9210_CLK_P1C 4 -#define R7S9210_CLK_P0 5 - -#endif /* __DT_BINDINGS_CLOCK_R7S9210_CPG_MSSR_H__ */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/r8a73a4-clock.h b/sys/gnu/dts/include/dt-bindings/clock/r8a73a4-clock.h deleted file mode 100644 index 1ec4827b809..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/r8a73a4-clock.h +++ /dev/null @@ -1,60 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright 2014 Ulrich Hecht - */ - -#ifndef __DT_BINDINGS_CLOCK_R8A73A4_H__ -#define __DT_BINDINGS_CLOCK_R8A73A4_H__ - -/* CPG */ -#define R8A73A4_CLK_MAIN 0 -#define R8A73A4_CLK_PLL0 1 -#define R8A73A4_CLK_PLL1 2 -#define R8A73A4_CLK_PLL2 3 -#define R8A73A4_CLK_PLL2S 4 -#define R8A73A4_CLK_PLL2H 5 -#define R8A73A4_CLK_Z 6 -#define R8A73A4_CLK_Z2 7 -#define R8A73A4_CLK_I 8 -#define R8A73A4_CLK_M3 9 -#define R8A73A4_CLK_B 10 -#define R8A73A4_CLK_M1 11 -#define R8A73A4_CLK_M2 12 -#define R8A73A4_CLK_ZX 13 -#define R8A73A4_CLK_ZS 14 -#define R8A73A4_CLK_HP 15 - -/* MSTP2 */ -#define R8A73A4_CLK_DMAC 18 -#define R8A73A4_CLK_SCIFB3 17 -#define R8A73A4_CLK_SCIFB2 16 -#define R8A73A4_CLK_SCIFB1 7 -#define R8A73A4_CLK_SCIFB0 6 -#define R8A73A4_CLK_SCIFA0 4 -#define R8A73A4_CLK_SCIFA1 3 - -/* MSTP3 */ -#define R8A73A4_CLK_CMT1 29 -#define R8A73A4_CLK_IIC1 23 -#define R8A73A4_CLK_IIC0 18 -#define R8A73A4_CLK_IIC7 17 -#define R8A73A4_CLK_IIC6 16 -#define R8A73A4_CLK_MMCIF0 15 -#define R8A73A4_CLK_SDHI0 14 -#define R8A73A4_CLK_SDHI1 13 -#define R8A73A4_CLK_SDHI2 12 -#define R8A73A4_CLK_MMCIF1 5 -#define R8A73A4_CLK_IIC2 0 - -/* MSTP4 */ -#define R8A73A4_CLK_IIC3 11 -#define R8A73A4_CLK_IIC4 10 -#define R8A73A4_CLK_IIC5 9 -#define R8A73A4_CLK_INTC_SYS 8 -#define R8A73A4_CLK_IRQC 7 - -/* MSTP5 */ -#define R8A73A4_CLK_THERMAL 22 -#define R8A73A4_CLK_IIC8 15 - -#endif /* __DT_BINDINGS_CLOCK_R8A73A4_H__ */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/r8a7740-clock.h b/sys/gnu/dts/include/dt-bindings/clock/r8a7740-clock.h deleted file mode 100644 index 1b3fdb39cc4..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/r8a7740-clock.h +++ /dev/null @@ -1,74 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright 2014 Ulrich Hecht - */ - -#ifndef __DT_BINDINGS_CLOCK_R8A7740_H__ -#define __DT_BINDINGS_CLOCK_R8A7740_H__ - -/* CPG */ -#define R8A7740_CLK_SYSTEM 0 -#define R8A7740_CLK_PLLC0 1 -#define R8A7740_CLK_PLLC1 2 -#define R8A7740_CLK_PLLC2 3 -#define R8A7740_CLK_R 4 -#define R8A7740_CLK_USB24S 5 -#define R8A7740_CLK_I 6 -#define R8A7740_CLK_ZG 7 -#define R8A7740_CLK_B 8 -#define R8A7740_CLK_M1 9 -#define R8A7740_CLK_HP 10 -#define R8A7740_CLK_HPP 11 -#define R8A7740_CLK_USBP 12 -#define R8A7740_CLK_S 13 -#define R8A7740_CLK_ZB 14 -#define R8A7740_CLK_M3 15 -#define R8A7740_CLK_CP 16 - -/* MSTP1 */ -#define R8A7740_CLK_CEU21 28 -#define R8A7740_CLK_CEU20 27 -#define R8A7740_CLK_TMU0 25 -#define R8A7740_CLK_LCDC1 17 -#define R8A7740_CLK_IIC0 16 -#define R8A7740_CLK_TMU1 11 -#define R8A7740_CLK_LCDC0 0 - -/* MSTP2 */ -#define R8A7740_CLK_SCIFA6 30 -#define R8A7740_CLK_INTCA 29 -#define R8A7740_CLK_SCIFA7 22 -#define R8A7740_CLK_DMAC1 18 -#define R8A7740_CLK_DMAC2 17 -#define R8A7740_CLK_DMAC3 16 -#define R8A7740_CLK_USBDMAC 14 -#define R8A7740_CLK_SCIFA5 7 -#define R8A7740_CLK_SCIFB 6 -#define R8A7740_CLK_SCIFA0 4 -#define R8A7740_CLK_SCIFA1 3 -#define R8A7740_CLK_SCIFA2 2 -#define R8A7740_CLK_SCIFA3 1 -#define R8A7740_CLK_SCIFA4 0 - -/* MSTP3 */ -#define R8A7740_CLK_CMT1 29 -#define R8A7740_CLK_FSI 28 -#define R8A7740_CLK_IIC1 23 -#define R8A7740_CLK_USBF 20 -#define R8A7740_CLK_SDHI0 14 -#define R8A7740_CLK_SDHI1 13 -#define R8A7740_CLK_MMC 12 -#define R8A7740_CLK_GETHER 9 -#define R8A7740_CLK_TPU0 4 - -/* MSTP4 */ -#define R8A7740_CLK_USBH 16 -#define R8A7740_CLK_SDHI2 15 -#define R8A7740_CLK_USBFUNC 7 -#define R8A7740_CLK_USBPHY 6 - -/* SUBCK* */ -#define R8A7740_CLK_SUBCK 9 -#define R8A7740_CLK_SUBCK2 10 - -#endif /* __DT_BINDINGS_CLOCK_R8A7740_H__ */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/r8a7743-cpg-mssr.h b/sys/gnu/dts/include/dt-bindings/clock/r8a7743-cpg-mssr.h deleted file mode 100644 index 3ba936029d9..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/r8a7743-cpg-mssr.h +++ /dev/null @@ -1,39 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ - * - * Copyright (C) 2016 Cogent Embedded Inc. - */ -#ifndef __DT_BINDINGS_CLOCK_R8A7743_CPG_MSSR_H__ -#define __DT_BINDINGS_CLOCK_R8A7743_CPG_MSSR_H__ - -#include - -/* r8a7743 CPG Core Clocks */ -#define R8A7743_CLK_Z 0 -#define R8A7743_CLK_ZG 1 -#define R8A7743_CLK_ZTR 2 -#define R8A7743_CLK_ZTRD2 3 -#define R8A7743_CLK_ZT 4 -#define R8A7743_CLK_ZX 5 -#define R8A7743_CLK_ZS 6 -#define R8A7743_CLK_HP 7 -#define R8A7743_CLK_B 9 -#define R8A7743_CLK_LB 10 -#define R8A7743_CLK_P 11 -#define R8A7743_CLK_CL 12 -#define R8A7743_CLK_M2 13 -#define R8A7743_CLK_ZB3 15 -#define R8A7743_CLK_ZB3D2 16 -#define R8A7743_CLK_DDR 17 -#define R8A7743_CLK_SDH 18 -#define R8A7743_CLK_SD0 19 -#define R8A7743_CLK_SD2 20 -#define R8A7743_CLK_SD3 21 -#define R8A7743_CLK_MMC0 22 -#define R8A7743_CLK_MP 23 -#define R8A7743_CLK_QSPI 26 -#define R8A7743_CLK_CP 27 -#define R8A7743_CLK_RCAN 28 -#define R8A7743_CLK_R 29 -#define R8A7743_CLK_OSC 30 - -#endif /* __DT_BINDINGS_CLOCK_R8A7743_CPG_MSSR_H__ */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/r8a7744-cpg-mssr.h b/sys/gnu/dts/include/dt-bindings/clock/r8a7744-cpg-mssr.h deleted file mode 100644 index 2690be0c3e2..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/r8a7744-cpg-mssr.h +++ /dev/null @@ -1,39 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 - * - * Copyright (C) 2018 Renesas Electronics Corp. - */ -#ifndef __DT_BINDINGS_CLOCK_R8A7744_CPG_MSSR_H__ -#define __DT_BINDINGS_CLOCK_R8A7744_CPG_MSSR_H__ - -#include - -/* r8a7744 CPG Core Clocks */ -#define R8A7744_CLK_Z 0 -#define R8A7744_CLK_ZG 1 -#define R8A7744_CLK_ZTR 2 -#define R8A7744_CLK_ZTRD2 3 -#define R8A7744_CLK_ZT 4 -#define R8A7744_CLK_ZX 5 -#define R8A7744_CLK_ZS 6 -#define R8A7744_CLK_HP 7 -#define R8A7744_CLK_B 9 -#define R8A7744_CLK_LB 10 -#define R8A7744_CLK_P 11 -#define R8A7744_CLK_CL 12 -#define R8A7744_CLK_M2 13 -#define R8A7744_CLK_ZB3 15 -#define R8A7744_CLK_ZB3D2 16 -#define R8A7744_CLK_DDR 17 -#define R8A7744_CLK_SDH 18 -#define R8A7744_CLK_SD0 19 -#define R8A7744_CLK_SD2 20 -#define R8A7744_CLK_SD3 21 -#define R8A7744_CLK_MMC0 22 -#define R8A7744_CLK_MP 23 -#define R8A7744_CLK_QSPI 26 -#define R8A7744_CLK_CP 27 -#define R8A7744_CLK_RCAN 28 -#define R8A7744_CLK_R 29 -#define R8A7744_CLK_OSC 30 - -#endif /* __DT_BINDINGS_CLOCK_R8A7744_CPG_MSSR_H__ */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/r8a7745-cpg-mssr.h b/sys/gnu/dts/include/dt-bindings/clock/r8a7745-cpg-mssr.h deleted file mode 100644 index f81066c9d19..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/r8a7745-cpg-mssr.h +++ /dev/null @@ -1,40 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ - * - * Copyright (C) 2016 Cogent Embedded Inc. - */ -#ifndef __DT_BINDINGS_CLOCK_R8A7745_CPG_MSSR_H__ -#define __DT_BINDINGS_CLOCK_R8A7745_CPG_MSSR_H__ - -#include - -/* r8a7745 CPG Core Clocks */ -#define R8A7745_CLK_Z2 0 -#define R8A7745_CLK_ZG 1 -#define R8A7745_CLK_ZTR 2 -#define R8A7745_CLK_ZTRD2 3 -#define R8A7745_CLK_ZT 4 -#define R8A7745_CLK_ZX 5 -#define R8A7745_CLK_ZS 6 -#define R8A7745_CLK_HP 7 -#define R8A7745_CLK_B 9 -#define R8A7745_CLK_LB 10 -#define R8A7745_CLK_P 11 -#define R8A7745_CLK_CL 12 -#define R8A7745_CLK_CP 13 -#define R8A7745_CLK_M2 14 -#define R8A7745_CLK_ZB3 16 -#define R8A7745_CLK_ZB3D2 17 -#define R8A7745_CLK_DDR 18 -#define R8A7745_CLK_SDH 19 -#define R8A7745_CLK_SD0 20 -#define R8A7745_CLK_SD2 21 -#define R8A7745_CLK_SD3 22 -#define R8A7745_CLK_MMC0 23 -#define R8A7745_CLK_MP 24 -#define R8A7745_CLK_QSPI 25 -#define R8A7745_CLK_CPEX 26 -#define R8A7745_CLK_RCAN 27 -#define R8A7745_CLK_R 28 -#define R8A7745_CLK_OSC 29 - -#endif /* __DT_BINDINGS_CLOCK_R8A7745_CPG_MSSR_H__ */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/r8a77470-cpg-mssr.h b/sys/gnu/dts/include/dt-bindings/clock/r8a77470-cpg-mssr.h deleted file mode 100644 index 34cba49d0f8..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/r8a77470-cpg-mssr.h +++ /dev/null @@ -1,36 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 - * - * Copyright (C) 2018 Renesas Electronics Corp. - */ -#ifndef __DT_BINDINGS_CLOCK_R8A77470_CPG_MSSR_H__ -#define __DT_BINDINGS_CLOCK_R8A77470_CPG_MSSR_H__ - -#include - -/* r8a77470 CPG Core Clocks */ -#define R8A77470_CLK_Z2 0 -#define R8A77470_CLK_ZTR 1 -#define R8A77470_CLK_ZTRD2 2 -#define R8A77470_CLK_ZT 3 -#define R8A77470_CLK_ZX 4 -#define R8A77470_CLK_ZS 5 -#define R8A77470_CLK_HP 6 -#define R8A77470_CLK_B 7 -#define R8A77470_CLK_LB 8 -#define R8A77470_CLK_P 9 -#define R8A77470_CLK_CL 10 -#define R8A77470_CLK_CP 11 -#define R8A77470_CLK_M2 12 -#define R8A77470_CLK_ZB3 13 -#define R8A77470_CLK_SDH 14 -#define R8A77470_CLK_SD0 15 -#define R8A77470_CLK_SD1 16 -#define R8A77470_CLK_SD2 17 -#define R8A77470_CLK_MP 18 -#define R8A77470_CLK_QSPI 19 -#define R8A77470_CLK_CPEX 20 -#define R8A77470_CLK_RCAN 21 -#define R8A77470_CLK_R 22 -#define R8A77470_CLK_OSC 23 - -#endif /* __DT_BINDINGS_CLOCK_R8A77470_CPG_MSSR_H__ */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/r8a774a1-cpg-mssr.h b/sys/gnu/dts/include/dt-bindings/clock/r8a774a1-cpg-mssr.h deleted file mode 100644 index e355363f40c..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/r8a774a1-cpg-mssr.h +++ /dev/null @@ -1,59 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 - * - * Copyright (C) 2018 Renesas Electronics Corp. - */ -#ifndef __DT_BINDINGS_CLOCK_R8A774A1_CPG_MSSR_H__ -#define __DT_BINDINGS_CLOCK_R8A774A1_CPG_MSSR_H__ - -#include - -/* r8a774a1 CPG Core Clocks */ -#define R8A774A1_CLK_Z 0 -#define R8A774A1_CLK_Z2 1 -#define R8A774A1_CLK_ZG 2 -#define R8A774A1_CLK_ZTR 3 -#define R8A774A1_CLK_ZTRD2 4 -#define R8A774A1_CLK_ZT 5 -#define R8A774A1_CLK_ZX 6 -#define R8A774A1_CLK_S0D1 7 -#define R8A774A1_CLK_S0D2 8 -#define R8A774A1_CLK_S0D3 9 -#define R8A774A1_CLK_S0D4 10 -#define R8A774A1_CLK_S0D6 11 -#define R8A774A1_CLK_S0D8 12 -#define R8A774A1_CLK_S0D12 13 -#define R8A774A1_CLK_S1D2 14 -#define R8A774A1_CLK_S1D4 15 -#define R8A774A1_CLK_S2D1 16 -#define R8A774A1_CLK_S2D2 17 -#define R8A774A1_CLK_S2D4 18 -#define R8A774A1_CLK_S3D1 19 -#define R8A774A1_CLK_S3D2 20 -#define R8A774A1_CLK_S3D4 21 -#define R8A774A1_CLK_LB 22 -#define R8A774A1_CLK_CL 23 -#define R8A774A1_CLK_ZB3 24 -#define R8A774A1_CLK_ZB3D2 25 -#define R8A774A1_CLK_ZB3D4 26 -#define R8A774A1_CLK_CR 27 -#define R8A774A1_CLK_CRD2 28 -#define R8A774A1_CLK_SD0H 29 -#define R8A774A1_CLK_SD0 30 -#define R8A774A1_CLK_SD1H 31 -#define R8A774A1_CLK_SD1 32 -#define R8A774A1_CLK_SD2H 33 -#define R8A774A1_CLK_SD2 34 -#define R8A774A1_CLK_SD3H 35 -#define R8A774A1_CLK_SD3 36 -#define R8A774A1_CLK_RPC 37 -#define R8A774A1_CLK_RPCD2 38 -#define R8A774A1_CLK_MSO 39 -#define R8A774A1_CLK_HDMI 40 -#define R8A774A1_CLK_CSI0 41 -#define R8A774A1_CLK_CP 42 -#define R8A774A1_CLK_CPEX 43 -#define R8A774A1_CLK_R 44 -#define R8A774A1_CLK_OSC 45 -#define R8A774A1_CLK_CANFD 46 - -#endif /* __DT_BINDINGS_CLOCK_R8A774A1_CPG_MSSR_H__ */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/r8a774b1-cpg-mssr.h b/sys/gnu/dts/include/dt-bindings/clock/r8a774b1-cpg-mssr.h deleted file mode 100644 index 1355451b74b..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/r8a774b1-cpg-mssr.h +++ /dev/null @@ -1,57 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 - * - * Copyright (C) 2019 Renesas Electronics Corp. - */ -#ifndef __DT_BINDINGS_CLOCK_R8A774B1_CPG_MSSR_H__ -#define __DT_BINDINGS_CLOCK_R8A774B1_CPG_MSSR_H__ - -#include - -/* r8a774b1 CPG Core Clocks */ -#define R8A774B1_CLK_Z 0 -#define R8A774B1_CLK_ZG 1 -#define R8A774B1_CLK_ZTR 2 -#define R8A774B1_CLK_ZTRD2 3 -#define R8A774B1_CLK_ZT 4 -#define R8A774B1_CLK_ZX 5 -#define R8A774B1_CLK_S0D1 6 -#define R8A774B1_CLK_S0D2 7 -#define R8A774B1_CLK_S0D3 8 -#define R8A774B1_CLK_S0D4 9 -#define R8A774B1_CLK_S0D6 10 -#define R8A774B1_CLK_S0D8 11 -#define R8A774B1_CLK_S0D12 12 -#define R8A774B1_CLK_S1D2 13 -#define R8A774B1_CLK_S1D4 14 -#define R8A774B1_CLK_S2D1 15 -#define R8A774B1_CLK_S2D2 16 -#define R8A774B1_CLK_S2D4 17 -#define R8A774B1_CLK_S3D1 18 -#define R8A774B1_CLK_S3D2 19 -#define R8A774B1_CLK_S3D4 20 -#define R8A774B1_CLK_LB 21 -#define R8A774B1_CLK_CL 22 -#define R8A774B1_CLK_ZB3 23 -#define R8A774B1_CLK_ZB3D2 24 -#define R8A774B1_CLK_CR 25 -#define R8A774B1_CLK_DDR 26 -#define R8A774B1_CLK_SD0H 27 -#define R8A774B1_CLK_SD0 28 -#define R8A774B1_CLK_SD1H 29 -#define R8A774B1_CLK_SD1 30 -#define R8A774B1_CLK_SD2H 31 -#define R8A774B1_CLK_SD2 32 -#define R8A774B1_CLK_SD3H 33 -#define R8A774B1_CLK_SD3 34 -#define R8A774B1_CLK_RPC 35 -#define R8A774B1_CLK_RPCD2 36 -#define R8A774B1_CLK_MSO 37 -#define R8A774B1_CLK_HDMI 38 -#define R8A774B1_CLK_CSI0 39 -#define R8A774B1_CLK_CP 40 -#define R8A774B1_CLK_CPEX 41 -#define R8A774B1_CLK_R 42 -#define R8A774B1_CLK_OSC 43 -#define R8A774B1_CLK_CANFD 44 - -#endif /* __DT_BINDINGS_CLOCK_R8A774B1_CPG_MSSR_H__ */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/r8a774c0-cpg-mssr.h b/sys/gnu/dts/include/dt-bindings/clock/r8a774c0-cpg-mssr.h deleted file mode 100644 index 8ad9cd6be8e..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/r8a774c0-cpg-mssr.h +++ /dev/null @@ -1,61 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2018 Renesas Electronics Corp. - */ -#ifndef __DT_BINDINGS_CLOCK_R8A774C0_CPG_MSSR_H__ -#define __DT_BINDINGS_CLOCK_R8A774C0_CPG_MSSR_H__ - -#include - -/* r8a774c0 CPG Core Clocks */ -#define R8A774C0_CLK_Z2 0 -#define R8A774C0_CLK_ZG 1 -#define R8A774C0_CLK_ZTR 2 -#define R8A774C0_CLK_ZT 3 -#define R8A774C0_CLK_ZX 4 -#define R8A774C0_CLK_S0D1 5 -#define R8A774C0_CLK_S0D3 6 -#define R8A774C0_CLK_S0D6 7 -#define R8A774C0_CLK_S0D12 8 -#define R8A774C0_CLK_S0D24 9 -#define R8A774C0_CLK_S1D1 10 -#define R8A774C0_CLK_S1D2 11 -#define R8A774C0_CLK_S1D4 12 -#define R8A774C0_CLK_S2D1 13 -#define R8A774C0_CLK_S2D2 14 -#define R8A774C0_CLK_S2D4 15 -#define R8A774C0_CLK_S3D1 16 -#define R8A774C0_CLK_S3D2 17 -#define R8A774C0_CLK_S3D4 18 -#define R8A774C0_CLK_S0D6C 19 -#define R8A774C0_CLK_S3D1C 20 -#define R8A774C0_CLK_S3D2C 21 -#define R8A774C0_CLK_S3D4C 22 -#define R8A774C0_CLK_LB 23 -#define R8A774C0_CLK_CL 24 -#define R8A774C0_CLK_ZB3 25 -#define R8A774C0_CLK_ZB3D2 26 -#define R8A774C0_CLK_CR 27 -#define R8A774C0_CLK_CRD2 28 -#define R8A774C0_CLK_SD0H 29 -#define R8A774C0_CLK_SD0 30 -#define R8A774C0_CLK_SD1H 31 -#define R8A774C0_CLK_SD1 32 -#define R8A774C0_CLK_SD3H 33 -#define R8A774C0_CLK_SD3 34 -#define R8A774C0_CLK_RPC 35 -#define R8A774C0_CLK_RPCD2 36 -#define R8A774C0_CLK_ZA2 37 -#define R8A774C0_CLK_ZA8 38 -#define R8A774C0_CLK_Z2D 39 -#define R8A774C0_CLK_MSO 40 -#define R8A774C0_CLK_R 41 -#define R8A774C0_CLK_OSC 42 -#define R8A774C0_CLK_LV0 43 -#define R8A774C0_CLK_LV1 44 -#define R8A774C0_CLK_CSI0 45 -#define R8A774C0_CLK_CP 46 -#define R8A774C0_CLK_CPEX 47 -#define R8A774C0_CLK_CANFD 48 - -#endif /* __DT_BINDINGS_CLOCK_R8A774C0_CPG_MSSR_H__ */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/r8a7778-clock.h b/sys/gnu/dts/include/dt-bindings/clock/r8a7778-clock.h deleted file mode 100644 index 4a32b364fd2..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/r8a7778-clock.h +++ /dev/null @@ -1,69 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright (C) 2014 Ulrich Hecht - */ - -#ifndef __DT_BINDINGS_CLOCK_R8A7778_H__ -#define __DT_BINDINGS_CLOCK_R8A7778_H__ - -/* CPG */ -#define R8A7778_CLK_PLLA 0 -#define R8A7778_CLK_PLLB 1 -#define R8A7778_CLK_B 2 -#define R8A7778_CLK_OUT 3 -#define R8A7778_CLK_P 4 -#define R8A7778_CLK_S 5 -#define R8A7778_CLK_S1 6 - -/* MSTP0 */ -#define R8A7778_CLK_I2C0 30 -#define R8A7778_CLK_I2C1 29 -#define R8A7778_CLK_I2C2 28 -#define R8A7778_CLK_I2C3 27 -#define R8A7778_CLK_SCIF0 26 -#define R8A7778_CLK_SCIF1 25 -#define R8A7778_CLK_SCIF2 24 -#define R8A7778_CLK_SCIF3 23 -#define R8A7778_CLK_SCIF4 22 -#define R8A7778_CLK_SCIF5 21 -#define R8A7778_CLK_HSCIF0 19 -#define R8A7778_CLK_HSCIF1 18 -#define R8A7778_CLK_TMU0 16 -#define R8A7778_CLK_TMU1 15 -#define R8A7778_CLK_TMU2 14 -#define R8A7778_CLK_SSI0 12 -#define R8A7778_CLK_SSI1 11 -#define R8A7778_CLK_SSI2 10 -#define R8A7778_CLK_SSI3 9 -#define R8A7778_CLK_SRU 8 -#define R8A7778_CLK_HSPI 7 - -/* MSTP1 */ -#define R8A7778_CLK_ETHER 14 -#define R8A7778_CLK_VIN0 10 -#define R8A7778_CLK_VIN1 9 -#define R8A7778_CLK_USB 0 - -/* MSTP3 */ -#define R8A7778_CLK_MMC 31 -#define R8A7778_CLK_SDHI0 23 -#define R8A7778_CLK_SDHI1 22 -#define R8A7778_CLK_SDHI2 21 -#define R8A7778_CLK_SSI4 11 -#define R8A7778_CLK_SSI5 10 -#define R8A7778_CLK_SSI6 9 -#define R8A7778_CLK_SSI7 8 -#define R8A7778_CLK_SSI8 7 - -/* MSTP5 */ -#define R8A7778_CLK_SRU_SRC0 31 -#define R8A7778_CLK_SRU_SRC1 30 -#define R8A7778_CLK_SRU_SRC2 29 -#define R8A7778_CLK_SRU_SRC3 28 -#define R8A7778_CLK_SRU_SRC4 27 -#define R8A7778_CLK_SRU_SRC5 26 -#define R8A7778_CLK_SRU_SRC6 25 -#define R8A7778_CLK_SRU_SRC7 24 -#define R8A7778_CLK_SRU_SRC8 23 - -#endif /* __DT_BINDINGS_CLOCK_R8A7778_H__ */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/r8a7779-clock.h b/sys/gnu/dts/include/dt-bindings/clock/r8a7779-clock.h deleted file mode 100644 index f0549234b7d..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/r8a7779-clock.h +++ /dev/null @@ -1,60 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright (C) 2013 Horms Solutions Ltd. - * - * Contact: Simon Horman - */ - -#ifndef __DT_BINDINGS_CLOCK_R8A7779_H__ -#define __DT_BINDINGS_CLOCK_R8A7779_H__ - -/* CPG */ -#define R8A7779_CLK_PLLA 0 -#define R8A7779_CLK_Z 1 -#define R8A7779_CLK_ZS 2 -#define R8A7779_CLK_S 3 -#define R8A7779_CLK_S1 4 -#define R8A7779_CLK_P 5 -#define R8A7779_CLK_B 6 -#define R8A7779_CLK_OUT 7 - -/* MSTP 0 */ -#define R8A7779_CLK_HSPI 7 -#define R8A7779_CLK_TMU2 14 -#define R8A7779_CLK_TMU1 15 -#define R8A7779_CLK_TMU0 16 -#define R8A7779_CLK_HSCIF1 18 -#define R8A7779_CLK_HSCIF0 19 -#define R8A7779_CLK_SCIF5 21 -#define R8A7779_CLK_SCIF4 22 -#define R8A7779_CLK_SCIF3 23 -#define R8A7779_CLK_SCIF2 24 -#define R8A7779_CLK_SCIF1 25 -#define R8A7779_CLK_SCIF0 26 -#define R8A7779_CLK_I2C3 27 -#define R8A7779_CLK_I2C2 28 -#define R8A7779_CLK_I2C1 29 -#define R8A7779_CLK_I2C0 30 - -/* MSTP 1 */ -#define R8A7779_CLK_USB01 0 -#define R8A7779_CLK_USB2 1 -#define R8A7779_CLK_DU 3 -#define R8A7779_CLK_VIN2 8 -#define R8A7779_CLK_VIN1 9 -#define R8A7779_CLK_VIN0 10 -#define R8A7779_CLK_ETHER 14 -#define R8A7779_CLK_SATA 15 -#define R8A7779_CLK_PCIE 16 -#define R8A7779_CLK_VIN3 20 - -/* MSTP 3 */ -#define R8A7779_CLK_SDHI3 20 -#define R8A7779_CLK_SDHI2 21 -#define R8A7779_CLK_SDHI1 22 -#define R8A7779_CLK_SDHI0 23 -#define R8A7779_CLK_MMC1 30 -#define R8A7779_CLK_MMC0 31 - - -#endif /* __DT_BINDINGS_CLOCK_R8A7779_H__ */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/r8a7790-clock.h b/sys/gnu/dts/include/dt-bindings/clock/r8a7790-clock.h deleted file mode 100644 index c92ff1e6022..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/r8a7790-clock.h +++ /dev/null @@ -1,158 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright 2013 Ideas On Board SPRL - */ - -#ifndef __DT_BINDINGS_CLOCK_R8A7790_H__ -#define __DT_BINDINGS_CLOCK_R8A7790_H__ - -/* CPG */ -#define R8A7790_CLK_MAIN 0 -#define R8A7790_CLK_PLL0 1 -#define R8A7790_CLK_PLL1 2 -#define R8A7790_CLK_PLL3 3 -#define R8A7790_CLK_LB 4 -#define R8A7790_CLK_QSPI 5 -#define R8A7790_CLK_SDH 6 -#define R8A7790_CLK_SD0 7 -#define R8A7790_CLK_SD1 8 -#define R8A7790_CLK_Z 9 -#define R8A7790_CLK_RCAN 10 -#define R8A7790_CLK_ADSP 11 - -/* MSTP0 */ -#define R8A7790_CLK_MSIOF0 0 - -/* MSTP1 */ -#define R8A7790_CLK_VCP1 0 -#define R8A7790_CLK_VCP0 1 -#define R8A7790_CLK_VPC1 2 -#define R8A7790_CLK_VPC0 3 -#define R8A7790_CLK_JPU 6 -#define R8A7790_CLK_SSP1 9 -#define R8A7790_CLK_TMU1 11 -#define R8A7790_CLK_3DG 12 -#define R8A7790_CLK_2DDMAC 15 -#define R8A7790_CLK_FDP1_2 17 -#define R8A7790_CLK_FDP1_1 18 -#define R8A7790_CLK_FDP1_0 19 -#define R8A7790_CLK_TMU3 21 -#define R8A7790_CLK_TMU2 22 -#define R8A7790_CLK_CMT0 24 -#define R8A7790_CLK_TMU0 25 -#define R8A7790_CLK_VSP1_DU1 27 -#define R8A7790_CLK_VSP1_DU0 28 -#define R8A7790_CLK_VSP1_R 30 -#define R8A7790_CLK_VSP1_S 31 - -/* MSTP2 */ -#define R8A7790_CLK_SCIFA2 2 -#define R8A7790_CLK_SCIFA1 3 -#define R8A7790_CLK_SCIFA0 4 -#define R8A7790_CLK_MSIOF2 5 -#define R8A7790_CLK_SCIFB0 6 -#define R8A7790_CLK_SCIFB1 7 -#define R8A7790_CLK_MSIOF1 8 -#define R8A7790_CLK_MSIOF3 15 -#define R8A7790_CLK_SCIFB2 16 -#define R8A7790_CLK_SYS_DMAC1 18 -#define R8A7790_CLK_SYS_DMAC0 19 - -/* MSTP3 */ -#define R8A7790_CLK_IIC2 0 -#define R8A7790_CLK_TPU0 4 -#define R8A7790_CLK_MMCIF1 5 -#define R8A7790_CLK_SCIF2 10 -#define R8A7790_CLK_SDHI3 11 -#define R8A7790_CLK_SDHI2 12 -#define R8A7790_CLK_SDHI1 13 -#define R8A7790_CLK_SDHI0 14 -#define R8A7790_CLK_MMCIF0 15 -#define R8A7790_CLK_IIC0 18 -#define R8A7790_CLK_PCIEC 19 -#define R8A7790_CLK_IIC1 23 -#define R8A7790_CLK_SSUSB 28 -#define R8A7790_CLK_CMT1 29 -#define R8A7790_CLK_USBDMAC0 30 -#define R8A7790_CLK_USBDMAC1 31 - -/* MSTP4 */ -#define R8A7790_CLK_IRQC 7 -#define R8A7790_CLK_INTC_SYS 8 - -/* MSTP5 */ -#define R8A7790_CLK_AUDIO_DMAC1 1 -#define R8A7790_CLK_AUDIO_DMAC0 2 -#define R8A7790_CLK_ADSP_MOD 6 -#define R8A7790_CLK_THERMAL 22 -#define R8A7790_CLK_PWM 23 - -/* MSTP7 */ -#define R8A7790_CLK_EHCI 3 -#define R8A7790_CLK_HSUSB 4 -#define R8A7790_CLK_HSCIF1 16 -#define R8A7790_CLK_HSCIF0 17 -#define R8A7790_CLK_SCIF1 20 -#define R8A7790_CLK_SCIF0 21 -#define R8A7790_CLK_DU2 22 -#define R8A7790_CLK_DU1 23 -#define R8A7790_CLK_DU0 24 -#define R8A7790_CLK_LVDS1 25 -#define R8A7790_CLK_LVDS0 26 - -/* MSTP8 */ -#define R8A7790_CLK_MLB 2 -#define R8A7790_CLK_VIN3 8 -#define R8A7790_CLK_VIN2 9 -#define R8A7790_CLK_VIN1 10 -#define R8A7790_CLK_VIN0 11 -#define R8A7790_CLK_ETHERAVB 12 -#define R8A7790_CLK_ETHER 13 -#define R8A7790_CLK_SATA1 14 -#define R8A7790_CLK_SATA0 15 - -/* MSTP9 */ -#define R8A7790_CLK_GPIO5 7 -#define R8A7790_CLK_GPIO4 8 -#define R8A7790_CLK_GPIO3 9 -#define R8A7790_CLK_GPIO2 10 -#define R8A7790_CLK_GPIO1 11 -#define R8A7790_CLK_GPIO0 12 -#define R8A7790_CLK_RCAN1 15 -#define R8A7790_CLK_RCAN0 16 -#define R8A7790_CLK_QSPI_MOD 17 -#define R8A7790_CLK_IICDVFS 26 -#define R8A7790_CLK_I2C3 28 -#define R8A7790_CLK_I2C2 29 -#define R8A7790_CLK_I2C1 30 -#define R8A7790_CLK_I2C0 31 - -/* MSTP10 */ -#define R8A7790_CLK_SSI_ALL 5 -#define R8A7790_CLK_SSI9 6 -#define R8A7790_CLK_SSI8 7 -#define R8A7790_CLK_SSI7 8 -#define R8A7790_CLK_SSI6 9 -#define R8A7790_CLK_SSI5 10 -#define R8A7790_CLK_SSI4 11 -#define R8A7790_CLK_SSI3 12 -#define R8A7790_CLK_SSI2 13 -#define R8A7790_CLK_SSI1 14 -#define R8A7790_CLK_SSI0 15 -#define R8A7790_CLK_SCU_ALL 17 -#define R8A7790_CLK_SCU_DVC1 18 -#define R8A7790_CLK_SCU_DVC0 19 -#define R8A7790_CLK_SCU_CTU1_MIX1 20 -#define R8A7790_CLK_SCU_CTU0_MIX0 21 -#define R8A7790_CLK_SCU_SRC9 22 -#define R8A7790_CLK_SCU_SRC8 23 -#define R8A7790_CLK_SCU_SRC7 24 -#define R8A7790_CLK_SCU_SRC6 25 -#define R8A7790_CLK_SCU_SRC5 26 -#define R8A7790_CLK_SCU_SRC4 27 -#define R8A7790_CLK_SCU_SRC3 28 -#define R8A7790_CLK_SCU_SRC2 29 -#define R8A7790_CLK_SCU_SRC1 30 -#define R8A7790_CLK_SCU_SRC0 31 - -#endif /* __DT_BINDINGS_CLOCK_R8A7790_H__ */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/r8a7790-cpg-mssr.h b/sys/gnu/dts/include/dt-bindings/clock/r8a7790-cpg-mssr.h deleted file mode 100644 index c5955b56b36..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/r8a7790-cpg-mssr.h +++ /dev/null @@ -1,48 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ - * - * Copyright (C) 2015 Renesas Electronics Corp. - */ - -#ifndef __DT_BINDINGS_CLOCK_R8A7790_CPG_MSSR_H__ -#define __DT_BINDINGS_CLOCK_R8A7790_CPG_MSSR_H__ - -#include - -/* r8a7790 CPG Core Clocks */ -#define R8A7790_CLK_Z 0 -#define R8A7790_CLK_Z2 1 -#define R8A7790_CLK_ZG 2 -#define R8A7790_CLK_ZTR 3 -#define R8A7790_CLK_ZTRD2 4 -#define R8A7790_CLK_ZT 5 -#define R8A7790_CLK_ZX 6 -#define R8A7790_CLK_ZS 7 -#define R8A7790_CLK_HP 8 -#define R8A7790_CLK_I 9 -#define R8A7790_CLK_B 10 -#define R8A7790_CLK_LB 11 -#define R8A7790_CLK_P 12 -#define R8A7790_CLK_CL 13 -#define R8A7790_CLK_M2 14 -#define R8A7790_CLK_ADSP 15 -#define R8A7790_CLK_IMP 16 -#define R8A7790_CLK_ZB3 17 -#define R8A7790_CLK_ZB3D2 18 -#define R8A7790_CLK_DDR 19 -#define R8A7790_CLK_SDH 20 -#define R8A7790_CLK_SD0 21 -#define R8A7790_CLK_SD1 22 -#define R8A7790_CLK_SD2 23 -#define R8A7790_CLK_SD3 24 -#define R8A7790_CLK_MMC0 25 -#define R8A7790_CLK_MMC1 26 -#define R8A7790_CLK_MP 27 -#define R8A7790_CLK_SSP 28 -#define R8A7790_CLK_SSPRS 29 -#define R8A7790_CLK_QSPI 30 -#define R8A7790_CLK_CP 31 -#define R8A7790_CLK_RCAN 32 -#define R8A7790_CLK_R 33 -#define R8A7790_CLK_OSC 34 - -#endif /* __DT_BINDINGS_CLOCK_R8A7790_CPG_MSSR_H__ */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/r8a7791-clock.h b/sys/gnu/dts/include/dt-bindings/clock/r8a7791-clock.h deleted file mode 100644 index bb4f18b1b3d..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/r8a7791-clock.h +++ /dev/null @@ -1,161 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright 2013 Ideas On Board SPRL - */ - -#ifndef __DT_BINDINGS_CLOCK_R8A7791_H__ -#define __DT_BINDINGS_CLOCK_R8A7791_H__ - -/* CPG */ -#define R8A7791_CLK_MAIN 0 -#define R8A7791_CLK_PLL0 1 -#define R8A7791_CLK_PLL1 2 -#define R8A7791_CLK_PLL3 3 -#define R8A7791_CLK_LB 4 -#define R8A7791_CLK_QSPI 5 -#define R8A7791_CLK_SDH 6 -#define R8A7791_CLK_SD0 7 -#define R8A7791_CLK_Z 8 -#define R8A7791_CLK_RCAN 9 -#define R8A7791_CLK_ADSP 10 - -/* MSTP0 */ -#define R8A7791_CLK_MSIOF0 0 - -/* MSTP1 */ -#define R8A7791_CLK_VCP0 1 -#define R8A7791_CLK_VPC0 3 -#define R8A7791_CLK_JPU 6 -#define R8A7791_CLK_SSP1 9 -#define R8A7791_CLK_TMU1 11 -#define R8A7791_CLK_3DG 12 -#define R8A7791_CLK_2DDMAC 15 -#define R8A7791_CLK_FDP1_1 18 -#define R8A7791_CLK_FDP1_0 19 -#define R8A7791_CLK_TMU3 21 -#define R8A7791_CLK_TMU2 22 -#define R8A7791_CLK_CMT0 24 -#define R8A7791_CLK_TMU0 25 -#define R8A7791_CLK_VSP1_DU1 27 -#define R8A7791_CLK_VSP1_DU0 28 -#define R8A7791_CLK_VSP1_S 31 - -/* MSTP2 */ -#define R8A7791_CLK_SCIFA2 2 -#define R8A7791_CLK_SCIFA1 3 -#define R8A7791_CLK_SCIFA0 4 -#define R8A7791_CLK_MSIOF2 5 -#define R8A7791_CLK_SCIFB0 6 -#define R8A7791_CLK_SCIFB1 7 -#define R8A7791_CLK_MSIOF1 8 -#define R8A7791_CLK_SCIFB2 16 -#define R8A7791_CLK_SYS_DMAC1 18 -#define R8A7791_CLK_SYS_DMAC0 19 - -/* MSTP3 */ -#define R8A7791_CLK_TPU0 4 -#define R8A7791_CLK_SDHI2 11 -#define R8A7791_CLK_SDHI1 12 -#define R8A7791_CLK_SDHI0 14 -#define R8A7791_CLK_MMCIF0 15 -#define R8A7791_CLK_IIC0 18 -#define R8A7791_CLK_PCIEC 19 -#define R8A7791_CLK_IIC1 23 -#define R8A7791_CLK_SSUSB 28 -#define R8A7791_CLK_CMT1 29 -#define R8A7791_CLK_USBDMAC0 30 -#define R8A7791_CLK_USBDMAC1 31 - -/* MSTP4 */ -#define R8A7791_CLK_IRQC 7 -#define R8A7791_CLK_INTC_SYS 8 - -/* MSTP5 */ -#define R8A7791_CLK_AUDIO_DMAC1 1 -#define R8A7791_CLK_AUDIO_DMAC0 2 -#define R8A7791_CLK_ADSP_MOD 6 -#define R8A7791_CLK_THERMAL 22 -#define R8A7791_CLK_PWM 23 - -/* MSTP7 */ -#define R8A7791_CLK_EHCI 3 -#define R8A7791_CLK_HSUSB 4 -#define R8A7791_CLK_HSCIF2 13 -#define R8A7791_CLK_SCIF5 14 -#define R8A7791_CLK_SCIF4 15 -#define R8A7791_CLK_HSCIF1 16 -#define R8A7791_CLK_HSCIF0 17 -#define R8A7791_CLK_SCIF3 18 -#define R8A7791_CLK_SCIF2 19 -#define R8A7791_CLK_SCIF1 20 -#define R8A7791_CLK_SCIF0 21 -#define R8A7791_CLK_DU1 23 -#define R8A7791_CLK_DU0 24 -#define R8A7791_CLK_LVDS0 26 - -/* MSTP8 */ -#define R8A7791_CLK_IPMMU_SGX 0 -#define R8A7791_CLK_MLB 2 -#define R8A7791_CLK_VIN2 9 -#define R8A7791_CLK_VIN1 10 -#define R8A7791_CLK_VIN0 11 -#define R8A7791_CLK_ETHERAVB 12 -#define R8A7791_CLK_ETHER 13 -#define R8A7791_CLK_SATA1 14 -#define R8A7791_CLK_SATA0 15 - -/* MSTP9 */ -#define R8A7791_CLK_GYROADC 1 -#define R8A7791_CLK_GPIO7 4 -#define R8A7791_CLK_GPIO6 5 -#define R8A7791_CLK_GPIO5 7 -#define R8A7791_CLK_GPIO4 8 -#define R8A7791_CLK_GPIO3 9 -#define R8A7791_CLK_GPIO2 10 -#define R8A7791_CLK_GPIO1 11 -#define R8A7791_CLK_GPIO0 12 -#define R8A7791_CLK_RCAN1 15 -#define R8A7791_CLK_RCAN0 16 -#define R8A7791_CLK_QSPI_MOD 17 -#define R8A7791_CLK_I2C5 25 -#define R8A7791_CLK_IICDVFS 26 -#define R8A7791_CLK_I2C4 27 -#define R8A7791_CLK_I2C3 28 -#define R8A7791_CLK_I2C2 29 -#define R8A7791_CLK_I2C1 30 -#define R8A7791_CLK_I2C0 31 - -/* MSTP10 */ -#define R8A7791_CLK_SSI_ALL 5 -#define R8A7791_CLK_SSI9 6 -#define R8A7791_CLK_SSI8 7 -#define R8A7791_CLK_SSI7 8 -#define R8A7791_CLK_SSI6 9 -#define R8A7791_CLK_SSI5 10 -#define R8A7791_CLK_SSI4 11 -#define R8A7791_CLK_SSI3 12 -#define R8A7791_CLK_SSI2 13 -#define R8A7791_CLK_SSI1 14 -#define R8A7791_CLK_SSI0 15 -#define R8A7791_CLK_SCU_ALL 17 -#define R8A7791_CLK_SCU_DVC1 18 -#define R8A7791_CLK_SCU_DVC0 19 -#define R8A7791_CLK_SCU_CTU1_MIX1 20 -#define R8A7791_CLK_SCU_CTU0_MIX0 21 -#define R8A7791_CLK_SCU_SRC9 22 -#define R8A7791_CLK_SCU_SRC8 23 -#define R8A7791_CLK_SCU_SRC7 24 -#define R8A7791_CLK_SCU_SRC6 25 -#define R8A7791_CLK_SCU_SRC5 26 -#define R8A7791_CLK_SCU_SRC4 27 -#define R8A7791_CLK_SCU_SRC3 28 -#define R8A7791_CLK_SCU_SRC2 29 -#define R8A7791_CLK_SCU_SRC1 30 -#define R8A7791_CLK_SCU_SRC0 31 - -/* MSTP11 */ -#define R8A7791_CLK_SCIFA3 6 -#define R8A7791_CLK_SCIFA4 7 -#define R8A7791_CLK_SCIFA5 8 - -#endif /* __DT_BINDINGS_CLOCK_R8A7791_H__ */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/r8a7791-cpg-mssr.h b/sys/gnu/dts/include/dt-bindings/clock/r8a7791-cpg-mssr.h deleted file mode 100644 index aadd06c566c..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/r8a7791-cpg-mssr.h +++ /dev/null @@ -1,44 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ - * - * Copyright (C) 2015 Renesas Electronics Corp. - */ - -#ifndef __DT_BINDINGS_CLOCK_R8A7791_CPG_MSSR_H__ -#define __DT_BINDINGS_CLOCK_R8A7791_CPG_MSSR_H__ - -#include - -/* r8a7791 CPG Core Clocks */ -#define R8A7791_CLK_Z 0 -#define R8A7791_CLK_ZG 1 -#define R8A7791_CLK_ZTR 2 -#define R8A7791_CLK_ZTRD2 3 -#define R8A7791_CLK_ZT 4 -#define R8A7791_CLK_ZX 5 -#define R8A7791_CLK_ZS 6 -#define R8A7791_CLK_HP 7 -#define R8A7791_CLK_I 8 -#define R8A7791_CLK_B 9 -#define R8A7791_CLK_LB 10 -#define R8A7791_CLK_P 11 -#define R8A7791_CLK_CL 12 -#define R8A7791_CLK_M2 13 -#define R8A7791_CLK_ADSP 14 -#define R8A7791_CLK_ZB3 15 -#define R8A7791_CLK_ZB3D2 16 -#define R8A7791_CLK_DDR 17 -#define R8A7791_CLK_SDH 18 -#define R8A7791_CLK_SD0 19 -#define R8A7791_CLK_SD2 20 -#define R8A7791_CLK_SD3 21 -#define R8A7791_CLK_MMC0 22 -#define R8A7791_CLK_MP 23 -#define R8A7791_CLK_SSP 24 -#define R8A7791_CLK_SSPRS 25 -#define R8A7791_CLK_QSPI 26 -#define R8A7791_CLK_CP 27 -#define R8A7791_CLK_RCAN 28 -#define R8A7791_CLK_R 29 -#define R8A7791_CLK_OSC 30 - -#endif /* __DT_BINDINGS_CLOCK_R8A7791_CPG_MSSR_H__ */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/r8a7792-clock.h b/sys/gnu/dts/include/dt-bindings/clock/r8a7792-clock.h deleted file mode 100644 index 2948d9ce3a1..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/r8a7792-clock.h +++ /dev/null @@ -1,98 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright (C) 2016 Cogent Embedded, Inc. - */ - -#ifndef __DT_BINDINGS_CLOCK_R8A7792_H__ -#define __DT_BINDINGS_CLOCK_R8A7792_H__ - -/* CPG */ -#define R8A7792_CLK_MAIN 0 -#define R8A7792_CLK_PLL0 1 -#define R8A7792_CLK_PLL1 2 -#define R8A7792_CLK_PLL3 3 -#define R8A7792_CLK_LB 4 -#define R8A7792_CLK_QSPI 5 - -/* MSTP0 */ -#define R8A7792_CLK_MSIOF0 0 - -/* MSTP1 */ -#define R8A7792_CLK_JPU 6 -#define R8A7792_CLK_TMU1 11 -#define R8A7792_CLK_TMU3 21 -#define R8A7792_CLK_TMU2 22 -#define R8A7792_CLK_CMT0 24 -#define R8A7792_CLK_TMU0 25 -#define R8A7792_CLK_VSP1DU1 27 -#define R8A7792_CLK_VSP1DU0 28 -#define R8A7792_CLK_VSP1_SY 31 - -/* MSTP2 */ -#define R8A7792_CLK_MSIOF1 8 -#define R8A7792_CLK_SYS_DMAC1 18 -#define R8A7792_CLK_SYS_DMAC0 19 - -/* MSTP3 */ -#define R8A7792_CLK_TPU0 4 -#define R8A7792_CLK_SDHI0 14 -#define R8A7792_CLK_CMT1 29 - -/* MSTP4 */ -#define R8A7792_CLK_IRQC 7 -#define R8A7792_CLK_INTC_SYS 8 - -/* MSTP5 */ -#define R8A7792_CLK_AUDIO_DMAC0 2 -#define R8A7792_CLK_THERMAL 22 -#define R8A7792_CLK_PWM 23 - -/* MSTP7 */ -#define R8A7792_CLK_HSCIF1 16 -#define R8A7792_CLK_HSCIF0 17 -#define R8A7792_CLK_SCIF3 18 -#define R8A7792_CLK_SCIF2 19 -#define R8A7792_CLK_SCIF1 20 -#define R8A7792_CLK_SCIF0 21 -#define R8A7792_CLK_DU1 23 -#define R8A7792_CLK_DU0 24 - -/* MSTP8 */ -#define R8A7792_CLK_VIN5 4 -#define R8A7792_CLK_VIN4 5 -#define R8A7792_CLK_VIN3 8 -#define R8A7792_CLK_VIN2 9 -#define R8A7792_CLK_VIN1 10 -#define R8A7792_CLK_VIN0 11 -#define R8A7792_CLK_ETHERAVB 12 - -/* MSTP9 */ -#define R8A7792_CLK_GPIO7 4 -#define R8A7792_CLK_GPIO6 5 -#define R8A7792_CLK_GPIO5 7 -#define R8A7792_CLK_GPIO4 8 -#define R8A7792_CLK_GPIO3 9 -#define R8A7792_CLK_GPIO2 10 -#define R8A7792_CLK_GPIO1 11 -#define R8A7792_CLK_GPIO0 12 -#define R8A7792_CLK_GPIO11 13 -#define R8A7792_CLK_GPIO10 14 -#define R8A7792_CLK_CAN1 15 -#define R8A7792_CLK_CAN0 16 -#define R8A7792_CLK_QSPI_MOD 17 -#define R8A7792_CLK_GPIO9 19 -#define R8A7792_CLK_GPIO8 21 -#define R8A7792_CLK_I2C5 25 -#define R8A7792_CLK_IICDVFS 26 -#define R8A7792_CLK_I2C4 27 -#define R8A7792_CLK_I2C3 28 -#define R8A7792_CLK_I2C2 29 -#define R8A7792_CLK_I2C1 30 -#define R8A7792_CLK_I2C0 31 - -/* MSTP10 */ -#define R8A7792_CLK_SSI_ALL 5 -#define R8A7792_CLK_SSI4 11 -#define R8A7792_CLK_SSI3 12 - -#endif /* __DT_BINDINGS_CLOCK_R8A7792_H__ */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/r8a7792-cpg-mssr.h b/sys/gnu/dts/include/dt-bindings/clock/r8a7792-cpg-mssr.h deleted file mode 100644 index 829c44db027..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/r8a7792-cpg-mssr.h +++ /dev/null @@ -1,39 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ - * - * Copyright (C) 2015 Renesas Electronics Corp. - */ - -#ifndef __DT_BINDINGS_CLOCK_R8A7792_CPG_MSSR_H__ -#define __DT_BINDINGS_CLOCK_R8A7792_CPG_MSSR_H__ - -#include - -/* r8a7792 CPG Core Clocks */ -#define R8A7792_CLK_Z 0 -#define R8A7792_CLK_ZG 1 -#define R8A7792_CLK_ZTR 2 -#define R8A7792_CLK_ZTRD2 3 -#define R8A7792_CLK_ZT 4 -#define R8A7792_CLK_ZX 5 -#define R8A7792_CLK_ZS 6 -#define R8A7792_CLK_HP 7 -#define R8A7792_CLK_I 8 -#define R8A7792_CLK_B 9 -#define R8A7792_CLK_LB 10 -#define R8A7792_CLK_P 11 -#define R8A7792_CLK_CL 12 -#define R8A7792_CLK_M2 13 -#define R8A7792_CLK_IMP 14 -#define R8A7792_CLK_ZB3 15 -#define R8A7792_CLK_ZB3D2 16 -#define R8A7792_CLK_DDR 17 -#define R8A7792_CLK_SD 18 -#define R8A7792_CLK_MP 19 -#define R8A7792_CLK_QSPI 20 -#define R8A7792_CLK_CP 21 -#define R8A7792_CLK_CPEX 22 -#define R8A7792_CLK_RCAN 23 -#define R8A7792_CLK_R 24 -#define R8A7792_CLK_OSC 25 - -#endif /* __DT_BINDINGS_CLOCK_R8A7792_CPG_MSSR_H__ */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/r8a7793-clock.h b/sys/gnu/dts/include/dt-bindings/clock/r8a7793-clock.h deleted file mode 100644 index 49c66d8ed17..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/r8a7793-clock.h +++ /dev/null @@ -1,159 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 - * - * r8a7793 clock definition - * - * Copyright (C) 2014 Renesas Electronics Corporation - */ - -#ifndef __DT_BINDINGS_CLOCK_R8A7793_H__ -#define __DT_BINDINGS_CLOCK_R8A7793_H__ - -/* CPG */ -#define R8A7793_CLK_MAIN 0 -#define R8A7793_CLK_PLL0 1 -#define R8A7793_CLK_PLL1 2 -#define R8A7793_CLK_PLL3 3 -#define R8A7793_CLK_LB 4 -#define R8A7793_CLK_QSPI 5 -#define R8A7793_CLK_SDH 6 -#define R8A7793_CLK_SD0 7 -#define R8A7793_CLK_Z 8 -#define R8A7793_CLK_RCAN 9 -#define R8A7793_CLK_ADSP 10 - -/* MSTP0 */ -#define R8A7793_CLK_MSIOF0 0 - -/* MSTP1 */ -#define R8A7793_CLK_VCP0 1 -#define R8A7793_CLK_VPC0 3 -#define R8A7793_CLK_SSP1 9 -#define R8A7793_CLK_TMU1 11 -#define R8A7793_CLK_3DG 12 -#define R8A7793_CLK_2DDMAC 15 -#define R8A7793_CLK_FDP1_1 18 -#define R8A7793_CLK_FDP1_0 19 -#define R8A7793_CLK_TMU3 21 -#define R8A7793_CLK_TMU2 22 -#define R8A7793_CLK_CMT0 24 -#define R8A7793_CLK_TMU0 25 -#define R8A7793_CLK_VSP1_DU1 27 -#define R8A7793_CLK_VSP1_DU0 28 -#define R8A7793_CLK_VSP1_S 31 - -/* MSTP2 */ -#define R8A7793_CLK_SCIFA2 2 -#define R8A7793_CLK_SCIFA1 3 -#define R8A7793_CLK_SCIFA0 4 -#define R8A7793_CLK_MSIOF2 5 -#define R8A7793_CLK_SCIFB0 6 -#define R8A7793_CLK_SCIFB1 7 -#define R8A7793_CLK_MSIOF1 8 -#define R8A7793_CLK_SCIFB2 16 -#define R8A7793_CLK_SYS_DMAC1 18 -#define R8A7793_CLK_SYS_DMAC0 19 - -/* MSTP3 */ -#define R8A7793_CLK_TPU0 4 -#define R8A7793_CLK_SDHI2 11 -#define R8A7793_CLK_SDHI1 12 -#define R8A7793_CLK_SDHI0 14 -#define R8A7793_CLK_MMCIF0 15 -#define R8A7793_CLK_IIC0 18 -#define R8A7793_CLK_PCIEC 19 -#define R8A7793_CLK_IIC1 23 -#define R8A7793_CLK_SSUSB 28 -#define R8A7793_CLK_CMT1 29 -#define R8A7793_CLK_USBDMAC0 30 -#define R8A7793_CLK_USBDMAC1 31 - -/* MSTP4 */ -#define R8A7793_CLK_IRQC 7 -#define R8A7793_CLK_INTC_SYS 8 - -/* MSTP5 */ -#define R8A7793_CLK_AUDIO_DMAC1 1 -#define R8A7793_CLK_AUDIO_DMAC0 2 -#define R8A7793_CLK_ADSP_MOD 6 -#define R8A7793_CLK_THERMAL 22 -#define R8A7793_CLK_PWM 23 - -/* MSTP7 */ -#define R8A7793_CLK_EHCI 3 -#define R8A7793_CLK_HSUSB 4 -#define R8A7793_CLK_HSCIF2 13 -#define R8A7793_CLK_SCIF5 14 -#define R8A7793_CLK_SCIF4 15 -#define R8A7793_CLK_HSCIF1 16 -#define R8A7793_CLK_HSCIF0 17 -#define R8A7793_CLK_SCIF3 18 -#define R8A7793_CLK_SCIF2 19 -#define R8A7793_CLK_SCIF1 20 -#define R8A7793_CLK_SCIF0 21 -#define R8A7793_CLK_DU1 23 -#define R8A7793_CLK_DU0 24 -#define R8A7793_CLK_LVDS0 26 - -/* MSTP8 */ -#define R8A7793_CLK_IPMMU_SGX 0 -#define R8A7793_CLK_VIN2 9 -#define R8A7793_CLK_VIN1 10 -#define R8A7793_CLK_VIN0 11 -#define R8A7793_CLK_ETHER 13 -#define R8A7793_CLK_SATA1 14 -#define R8A7793_CLK_SATA0 15 - -/* MSTP9 */ -#define R8A7793_CLK_GPIO7 4 -#define R8A7793_CLK_GPIO6 5 -#define R8A7793_CLK_GPIO5 7 -#define R8A7793_CLK_GPIO4 8 -#define R8A7793_CLK_GPIO3 9 -#define R8A7793_CLK_GPIO2 10 -#define R8A7793_CLK_GPIO1 11 -#define R8A7793_CLK_GPIO0 12 -#define R8A7793_CLK_RCAN1 15 -#define R8A7793_CLK_RCAN0 16 -#define R8A7793_CLK_QSPI_MOD 17 -#define R8A7793_CLK_I2C5 25 -#define R8A7793_CLK_IICDVFS 26 -#define R8A7793_CLK_I2C4 27 -#define R8A7793_CLK_I2C3 28 -#define R8A7793_CLK_I2C2 29 -#define R8A7793_CLK_I2C1 30 -#define R8A7793_CLK_I2C0 31 - -/* MSTP10 */ -#define R8A7793_CLK_SSI_ALL 5 -#define R8A7793_CLK_SSI9 6 -#define R8A7793_CLK_SSI8 7 -#define R8A7793_CLK_SSI7 8 -#define R8A7793_CLK_SSI6 9 -#define R8A7793_CLK_SSI5 10 -#define R8A7793_CLK_SSI4 11 -#define R8A7793_CLK_SSI3 12 -#define R8A7793_CLK_SSI2 13 -#define R8A7793_CLK_SSI1 14 -#define R8A7793_CLK_SSI0 15 -#define R8A7793_CLK_SCU_ALL 17 -#define R8A7793_CLK_SCU_DVC1 18 -#define R8A7793_CLK_SCU_DVC0 19 -#define R8A7793_CLK_SCU_CTU1_MIX1 20 -#define R8A7793_CLK_SCU_CTU0_MIX0 21 -#define R8A7793_CLK_SCU_SRC9 22 -#define R8A7793_CLK_SCU_SRC8 23 -#define R8A7793_CLK_SCU_SRC7 24 -#define R8A7793_CLK_SCU_SRC6 25 -#define R8A7793_CLK_SCU_SRC5 26 -#define R8A7793_CLK_SCU_SRC4 27 -#define R8A7793_CLK_SCU_SRC3 28 -#define R8A7793_CLK_SCU_SRC2 29 -#define R8A7793_CLK_SCU_SRC1 30 -#define R8A7793_CLK_SCU_SRC0 31 - -/* MSTP11 */ -#define R8A7793_CLK_SCIFA3 6 -#define R8A7793_CLK_SCIFA4 7 -#define R8A7793_CLK_SCIFA5 8 - -#endif /* __DT_BINDINGS_CLOCK_R8A7793_H__ */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/r8a7793-cpg-mssr.h b/sys/gnu/dts/include/dt-bindings/clock/r8a7793-cpg-mssr.h deleted file mode 100644 index d1ff646c31f..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/r8a7793-cpg-mssr.h +++ /dev/null @@ -1,44 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ - * - * Copyright (C) 2015 Renesas Electronics Corp. - */ - -#ifndef __DT_BINDINGS_CLOCK_R8A7793_CPG_MSSR_H__ -#define __DT_BINDINGS_CLOCK_R8A7793_CPG_MSSR_H__ - -#include - -/* r8a7793 CPG Core Clocks */ -#define R8A7793_CLK_Z 0 -#define R8A7793_CLK_ZG 1 -#define R8A7793_CLK_ZTR 2 -#define R8A7793_CLK_ZTRD2 3 -#define R8A7793_CLK_ZT 4 -#define R8A7793_CLK_ZX 5 -#define R8A7793_CLK_ZS 6 -#define R8A7793_CLK_HP 7 -#define R8A7793_CLK_I 8 -#define R8A7793_CLK_B 9 -#define R8A7793_CLK_LB 10 -#define R8A7793_CLK_P 11 -#define R8A7793_CLK_CL 12 -#define R8A7793_CLK_M2 13 -#define R8A7793_CLK_ADSP 14 -#define R8A7793_CLK_ZB3 15 -#define R8A7793_CLK_ZB3D2 16 -#define R8A7793_CLK_DDR 17 -#define R8A7793_CLK_SDH 18 -#define R8A7793_CLK_SD0 19 -#define R8A7793_CLK_SD2 20 -#define R8A7793_CLK_SD3 21 -#define R8A7793_CLK_MMC0 22 -#define R8A7793_CLK_MP 23 -#define R8A7793_CLK_SSP 24 -#define R8A7793_CLK_SSPRS 25 -#define R8A7793_CLK_QSPI 26 -#define R8A7793_CLK_CP 27 -#define R8A7793_CLK_RCAN 28 -#define R8A7793_CLK_R 29 -#define R8A7793_CLK_OSC 30 - -#endif /* __DT_BINDINGS_CLOCK_R8A7793_CPG_MSSR_H__ */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/r8a7794-clock.h b/sys/gnu/dts/include/dt-bindings/clock/r8a7794-clock.h deleted file mode 100644 index 649f005782d..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/r8a7794-clock.h +++ /dev/null @@ -1,137 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ - * - * Copyright (C) 2014 Renesas Electronics Corporation - * Copyright 2013 Ideas On Board SPRL - */ - -#ifndef __DT_BINDINGS_CLOCK_R8A7794_H__ -#define __DT_BINDINGS_CLOCK_R8A7794_H__ - -/* CPG */ -#define R8A7794_CLK_MAIN 0 -#define R8A7794_CLK_PLL0 1 -#define R8A7794_CLK_PLL1 2 -#define R8A7794_CLK_PLL3 3 -#define R8A7794_CLK_LB 4 -#define R8A7794_CLK_QSPI 5 -#define R8A7794_CLK_SDH 6 -#define R8A7794_CLK_SD0 7 -#define R8A7794_CLK_RCAN 8 - -/* MSTP0 */ -#define R8A7794_CLK_MSIOF0 0 - -/* MSTP1 */ -#define R8A7794_CLK_VCP0 1 -#define R8A7794_CLK_VPC0 3 -#define R8A7794_CLK_TMU1 11 -#define R8A7794_CLK_3DG 12 -#define R8A7794_CLK_2DDMAC 15 -#define R8A7794_CLK_FDP1_0 19 -#define R8A7794_CLK_TMU3 21 -#define R8A7794_CLK_TMU2 22 -#define R8A7794_CLK_CMT0 24 -#define R8A7794_CLK_TMU0 25 -#define R8A7794_CLK_VSP1_DU0 28 -#define R8A7794_CLK_VSP1_S 31 - -/* MSTP2 */ -#define R8A7794_CLK_SCIFA2 2 -#define R8A7794_CLK_SCIFA1 3 -#define R8A7794_CLK_SCIFA0 4 -#define R8A7794_CLK_MSIOF2 5 -#define R8A7794_CLK_SCIFB0 6 -#define R8A7794_CLK_SCIFB1 7 -#define R8A7794_CLK_MSIOF1 8 -#define R8A7794_CLK_SCIFB2 16 -#define R8A7794_CLK_SYS_DMAC1 18 -#define R8A7794_CLK_SYS_DMAC0 19 - -/* MSTP3 */ -#define R8A7794_CLK_SDHI2 11 -#define R8A7794_CLK_SDHI1 12 -#define R8A7794_CLK_SDHI0 14 -#define R8A7794_CLK_MMCIF0 15 -#define R8A7794_CLK_IIC0 18 -#define R8A7794_CLK_IIC1 23 -#define R8A7794_CLK_CMT1 29 -#define R8A7794_CLK_USBDMAC0 30 -#define R8A7794_CLK_USBDMAC1 31 - -/* MSTP4 */ -#define R8A7794_CLK_IRQC 7 -#define R8A7794_CLK_INTC_SYS 8 - -/* MSTP5 */ -#define R8A7794_CLK_AUDIO_DMAC0 2 -#define R8A7794_CLK_PWM 23 - -/* MSTP7 */ -#define R8A7794_CLK_EHCI 3 -#define R8A7794_CLK_HSUSB 4 -#define R8A7794_CLK_HSCIF2 13 -#define R8A7794_CLK_SCIF5 14 -#define R8A7794_CLK_SCIF4 15 -#define R8A7794_CLK_HSCIF1 16 -#define R8A7794_CLK_HSCIF0 17 -#define R8A7794_CLK_SCIF3 18 -#define R8A7794_CLK_SCIF2 19 -#define R8A7794_CLK_SCIF1 20 -#define R8A7794_CLK_SCIF0 21 -#define R8A7794_CLK_DU1 23 -#define R8A7794_CLK_DU0 24 - -/* MSTP8 */ -#define R8A7794_CLK_VIN1 10 -#define R8A7794_CLK_VIN0 11 -#define R8A7794_CLK_ETHERAVB 12 -#define R8A7794_CLK_ETHER 13 - -/* MSTP9 */ -#define R8A7794_CLK_GPIO6 5 -#define R8A7794_CLK_GPIO5 7 -#define R8A7794_CLK_GPIO4 8 -#define R8A7794_CLK_GPIO3 9 -#define R8A7794_CLK_GPIO2 10 -#define R8A7794_CLK_GPIO1 11 -#define R8A7794_CLK_GPIO0 12 -#define R8A7794_CLK_RCAN1 15 -#define R8A7794_CLK_RCAN0 16 -#define R8A7794_CLK_QSPI_MOD 17 -#define R8A7794_CLK_I2C5 25 -#define R8A7794_CLK_I2C4 27 -#define R8A7794_CLK_I2C3 28 -#define R8A7794_CLK_I2C2 29 -#define R8A7794_CLK_I2C1 30 -#define R8A7794_CLK_I2C0 31 - -/* MSTP10 */ -#define R8A7794_CLK_SSI_ALL 5 -#define R8A7794_CLK_SSI9 6 -#define R8A7794_CLK_SSI8 7 -#define R8A7794_CLK_SSI7 8 -#define R8A7794_CLK_SSI6 9 -#define R8A7794_CLK_SSI5 10 -#define R8A7794_CLK_SSI4 11 -#define R8A7794_CLK_SSI3 12 -#define R8A7794_CLK_SSI2 13 -#define R8A7794_CLK_SSI1 14 -#define R8A7794_CLK_SSI0 15 -#define R8A7794_CLK_SCU_ALL 17 -#define R8A7794_CLK_SCU_DVC1 18 -#define R8A7794_CLK_SCU_DVC0 19 -#define R8A7794_CLK_SCU_CTU1_MIX1 20 -#define R8A7794_CLK_SCU_CTU0_MIX0 21 -#define R8A7794_CLK_SCU_SRC6 25 -#define R8A7794_CLK_SCU_SRC5 26 -#define R8A7794_CLK_SCU_SRC4 27 -#define R8A7794_CLK_SCU_SRC3 28 -#define R8A7794_CLK_SCU_SRC2 29 -#define R8A7794_CLK_SCU_SRC1 30 - -/* MSTP11 */ -#define R8A7794_CLK_SCIFA3 6 -#define R8A7794_CLK_SCIFA4 7 -#define R8A7794_CLK_SCIFA5 8 - -#endif /* __DT_BINDINGS_CLOCK_R8A7794_H__ */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/r8a7794-cpg-mssr.h b/sys/gnu/dts/include/dt-bindings/clock/r8a7794-cpg-mssr.h deleted file mode 100644 index 6314e23b51a..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/r8a7794-cpg-mssr.h +++ /dev/null @@ -1,43 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ - * - * Copyright (C) 2015 Renesas Electronics Corp. - */ - -#ifndef __DT_BINDINGS_CLOCK_R8A7794_CPG_MSSR_H__ -#define __DT_BINDINGS_CLOCK_R8A7794_CPG_MSSR_H__ - -#include - -/* r8a7794 CPG Core Clocks */ -#define R8A7794_CLK_Z2 0 -#define R8A7794_CLK_ZG 1 -#define R8A7794_CLK_ZTR 2 -#define R8A7794_CLK_ZTRD2 3 -#define R8A7794_CLK_ZT 4 -#define R8A7794_CLK_ZX 5 -#define R8A7794_CLK_ZS 6 -#define R8A7794_CLK_HP 7 -#define R8A7794_CLK_I 8 -#define R8A7794_CLK_B 9 -#define R8A7794_CLK_LB 10 -#define R8A7794_CLK_P 11 -#define R8A7794_CLK_CL 12 -#define R8A7794_CLK_CP 13 -#define R8A7794_CLK_M2 14 -#define R8A7794_CLK_ADSP 15 -#define R8A7794_CLK_ZB3 16 -#define R8A7794_CLK_ZB3D2 17 -#define R8A7794_CLK_DDR 18 -#define R8A7794_CLK_SDH 19 -#define R8A7794_CLK_SD0 20 -#define R8A7794_CLK_SD2 21 -#define R8A7794_CLK_SD3 22 -#define R8A7794_CLK_MMC0 23 -#define R8A7794_CLK_MP 24 -#define R8A7794_CLK_QSPI 25 -#define R8A7794_CLK_CPEX 26 -#define R8A7794_CLK_RCAN 27 -#define R8A7794_CLK_R 28 -#define R8A7794_CLK_OSC 29 - -#endif /* __DT_BINDINGS_CLOCK_R8A7794_CPG_MSSR_H__ */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/r8a7795-cpg-mssr.h b/sys/gnu/dts/include/dt-bindings/clock/r8a7795-cpg-mssr.h deleted file mode 100644 index 92b3e2a9517..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/r8a7795-cpg-mssr.h +++ /dev/null @@ -1,66 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ - * - * Copyright (C) 2015 Renesas Electronics Corp. - */ -#ifndef __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__ -#define __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__ - -#include - -/* r8a7795 CPG Core Clocks */ -#define R8A7795_CLK_Z 0 -#define R8A7795_CLK_Z2 1 -#define R8A7795_CLK_ZR 2 -#define R8A7795_CLK_ZG 3 -#define R8A7795_CLK_ZTR 4 -#define R8A7795_CLK_ZTRD2 5 -#define R8A7795_CLK_ZT 6 -#define R8A7795_CLK_ZX 7 -#define R8A7795_CLK_S0D1 8 -#define R8A7795_CLK_S0D4 9 -#define R8A7795_CLK_S1D1 10 -#define R8A7795_CLK_S1D2 11 -#define R8A7795_CLK_S1D4 12 -#define R8A7795_CLK_S2D1 13 -#define R8A7795_CLK_S2D2 14 -#define R8A7795_CLK_S2D4 15 -#define R8A7795_CLK_S3D1 16 -#define R8A7795_CLK_S3D2 17 -#define R8A7795_CLK_S3D4 18 -#define R8A7795_CLK_LB 19 -#define R8A7795_CLK_CL 20 -#define R8A7795_CLK_ZB3 21 -#define R8A7795_CLK_ZB3D2 22 -#define R8A7795_CLK_CR 23 -#define R8A7795_CLK_CRD2 24 -#define R8A7795_CLK_SD0H 25 -#define R8A7795_CLK_SD0 26 -#define R8A7795_CLK_SD1H 27 -#define R8A7795_CLK_SD1 28 -#define R8A7795_CLK_SD2H 29 -#define R8A7795_CLK_SD2 30 -#define R8A7795_CLK_SD3H 31 -#define R8A7795_CLK_SD3 32 -#define R8A7795_CLK_SSP2 33 -#define R8A7795_CLK_SSP1 34 -#define R8A7795_CLK_SSPRS 35 -#define R8A7795_CLK_RPC 36 -#define R8A7795_CLK_RPCD2 37 -#define R8A7795_CLK_MSO 38 -#define R8A7795_CLK_CANFD 39 -#define R8A7795_CLK_HDMI 40 -#define R8A7795_CLK_CSI0 41 -/* CLK_CSIREF was removed */ -#define R8A7795_CLK_CP 43 -#define R8A7795_CLK_CPEX 44 -#define R8A7795_CLK_R 45 -#define R8A7795_CLK_OSC 46 - -/* r8a7795 ES2.0 CPG Core Clocks */ -#define R8A7795_CLK_S0D2 47 -#define R8A7795_CLK_S0D3 48 -#define R8A7795_CLK_S0D6 49 -#define R8A7795_CLK_S0D8 50 -#define R8A7795_CLK_S0D12 51 - -#endif /* __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__ */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/r8a7796-cpg-mssr.h b/sys/gnu/dts/include/dt-bindings/clock/r8a7796-cpg-mssr.h deleted file mode 100644 index c0957cf4584..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/r8a7796-cpg-mssr.h +++ /dev/null @@ -1,65 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ - * - * Copyright (C) 2016 Renesas Electronics Corp. - */ -#ifndef __DT_BINDINGS_CLOCK_R8A7796_CPG_MSSR_H__ -#define __DT_BINDINGS_CLOCK_R8A7796_CPG_MSSR_H__ - -#include - -/* r8a7796 CPG Core Clocks */ -#define R8A7796_CLK_Z 0 -#define R8A7796_CLK_Z2 1 -#define R8A7796_CLK_ZR 2 -#define R8A7796_CLK_ZG 3 -#define R8A7796_CLK_ZTR 4 -#define R8A7796_CLK_ZTRD2 5 -#define R8A7796_CLK_ZT 6 -#define R8A7796_CLK_ZX 7 -#define R8A7796_CLK_S0D1 8 -#define R8A7796_CLK_S0D2 9 -#define R8A7796_CLK_S0D3 10 -#define R8A7796_CLK_S0D4 11 -#define R8A7796_CLK_S0D6 12 -#define R8A7796_CLK_S0D8 13 -#define R8A7796_CLK_S0D12 14 -#define R8A7796_CLK_S1D1 15 -#define R8A7796_CLK_S1D2 16 -#define R8A7796_CLK_S1D4 17 -#define R8A7796_CLK_S2D1 18 -#define R8A7796_CLK_S2D2 19 -#define R8A7796_CLK_S2D4 20 -#define R8A7796_CLK_S3D1 21 -#define R8A7796_CLK_S3D2 22 -#define R8A7796_CLK_S3D4 23 -#define R8A7796_CLK_LB 24 -#define R8A7796_CLK_CL 25 -#define R8A7796_CLK_ZB3 26 -#define R8A7796_CLK_ZB3D2 27 -#define R8A7796_CLK_ZB3D4 28 -#define R8A7796_CLK_CR 29 -#define R8A7796_CLK_CRD2 30 -#define R8A7796_CLK_SD0H 31 -#define R8A7796_CLK_SD0 32 -#define R8A7796_CLK_SD1H 33 -#define R8A7796_CLK_SD1 34 -#define R8A7796_CLK_SD2H 35 -#define R8A7796_CLK_SD2 36 -#define R8A7796_CLK_SD3H 37 -#define R8A7796_CLK_SD3 38 -#define R8A7796_CLK_SSP2 39 -#define R8A7796_CLK_SSP1 40 -#define R8A7796_CLK_SSPRS 41 -#define R8A7796_CLK_RPC 42 -#define R8A7796_CLK_RPCD2 43 -#define R8A7796_CLK_MSO 44 -#define R8A7796_CLK_CANFD 45 -#define R8A7796_CLK_HDMI 46 -#define R8A7796_CLK_CSI0 47 -/* CLK_CSIREF was removed */ -#define R8A7796_CLK_CP 49 -#define R8A7796_CLK_CPEX 50 -#define R8A7796_CLK_R 51 -#define R8A7796_CLK_OSC 52 - -#endif /* __DT_BINDINGS_CLOCK_R8A7796_CPG_MSSR_H__ */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/r8a77961-cpg-mssr.h b/sys/gnu/dts/include/dt-bindings/clock/r8a77961-cpg-mssr.h deleted file mode 100644 index 7921d785546..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/r8a77961-cpg-mssr.h +++ /dev/null @@ -1,65 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ - * - * Copyright (C) 2019 Renesas Electronics Corp. - */ -#ifndef __DT_BINDINGS_CLOCK_R8A77961_CPG_MSSR_H__ -#define __DT_BINDINGS_CLOCK_R8A77961_CPG_MSSR_H__ - -#include - -/* r8a77961 CPG Core Clocks */ -#define R8A77961_CLK_Z 0 -#define R8A77961_CLK_Z2 1 -#define R8A77961_CLK_ZR 2 -#define R8A77961_CLK_ZG 3 -#define R8A77961_CLK_ZTR 4 -#define R8A77961_CLK_ZTRD2 5 -#define R8A77961_CLK_ZT 6 -#define R8A77961_CLK_ZX 7 -#define R8A77961_CLK_S0D1 8 -#define R8A77961_CLK_S0D2 9 -#define R8A77961_CLK_S0D3 10 -#define R8A77961_CLK_S0D4 11 -#define R8A77961_CLK_S0D6 12 -#define R8A77961_CLK_S0D8 13 -#define R8A77961_CLK_S0D12 14 -#define R8A77961_CLK_S1D1 15 -#define R8A77961_CLK_S1D2 16 -#define R8A77961_CLK_S1D4 17 -#define R8A77961_CLK_S2D1 18 -#define R8A77961_CLK_S2D2 19 -#define R8A77961_CLK_S2D4 20 -#define R8A77961_CLK_S3D1 21 -#define R8A77961_CLK_S3D2 22 -#define R8A77961_CLK_S3D4 23 -#define R8A77961_CLK_LB 24 -#define R8A77961_CLK_CL 25 -#define R8A77961_CLK_ZB3 26 -#define R8A77961_CLK_ZB3D2 27 -#define R8A77961_CLK_ZB3D4 28 -#define R8A77961_CLK_CR 29 -#define R8A77961_CLK_CRD2 30 -#define R8A77961_CLK_SD0H 31 -#define R8A77961_CLK_SD0 32 -#define R8A77961_CLK_SD1H 33 -#define R8A77961_CLK_SD1 34 -#define R8A77961_CLK_SD2H 35 -#define R8A77961_CLK_SD2 36 -#define R8A77961_CLK_SD3H 37 -#define R8A77961_CLK_SD3 38 -#define R8A77961_CLK_SSP2 39 -#define R8A77961_CLK_SSP1 40 -#define R8A77961_CLK_SSPRS 41 -#define R8A77961_CLK_RPC 42 -#define R8A77961_CLK_RPCD2 43 -#define R8A77961_CLK_MSO 44 -#define R8A77961_CLK_CANFD 45 -#define R8A77961_CLK_HDMI 46 -#define R8A77961_CLK_CSI0 47 -/* CLK_CSIREF was removed */ -#define R8A77961_CLK_CP 49 -#define R8A77961_CLK_CPEX 50 -#define R8A77961_CLK_R 51 -#define R8A77961_CLK_OSC 52 - -#endif /* __DT_BINDINGS_CLOCK_R8A77961_CPG_MSSR_H__ */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/r8a77965-cpg-mssr.h b/sys/gnu/dts/include/dt-bindings/clock/r8a77965-cpg-mssr.h deleted file mode 100644 index 6d3b5a9a608..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/r8a77965-cpg-mssr.h +++ /dev/null @@ -1,62 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2018 Jacopo Mondi - */ -#ifndef __DT_BINDINGS_CLOCK_R8A77965_CPG_MSSR_H__ -#define __DT_BINDINGS_CLOCK_R8A77965_CPG_MSSR_H__ - -#include - -/* r8a77965 CPG Core Clocks */ -#define R8A77965_CLK_Z 0 -#define R8A77965_CLK_ZR 1 -#define R8A77965_CLK_ZG 2 -#define R8A77965_CLK_ZTR 3 -#define R8A77965_CLK_ZTRD2 4 -#define R8A77965_CLK_ZT 5 -#define R8A77965_CLK_ZX 6 -#define R8A77965_CLK_S0D1 7 -#define R8A77965_CLK_S0D2 8 -#define R8A77965_CLK_S0D3 9 -#define R8A77965_CLK_S0D4 10 -#define R8A77965_CLK_S0D6 11 -#define R8A77965_CLK_S0D8 12 -#define R8A77965_CLK_S0D12 13 -#define R8A77965_CLK_S1D1 14 -#define R8A77965_CLK_S1D2 15 -#define R8A77965_CLK_S1D4 16 -#define R8A77965_CLK_S2D1 17 -#define R8A77965_CLK_S2D2 18 -#define R8A77965_CLK_S2D4 19 -#define R8A77965_CLK_S3D1 20 -#define R8A77965_CLK_S3D2 21 -#define R8A77965_CLK_S3D4 22 -#define R8A77965_CLK_LB 23 -#define R8A77965_CLK_CL 24 -#define R8A77965_CLK_ZB3 25 -#define R8A77965_CLK_ZB3D2 26 -#define R8A77965_CLK_CR 27 -#define R8A77965_CLK_CRD2 28 -#define R8A77965_CLK_SD0H 29 -#define R8A77965_CLK_SD0 30 -#define R8A77965_CLK_SD1H 31 -#define R8A77965_CLK_SD1 32 -#define R8A77965_CLK_SD2H 33 -#define R8A77965_CLK_SD2 34 -#define R8A77965_CLK_SD3H 35 -#define R8A77965_CLK_SD3 36 -#define R8A77965_CLK_SSP2 37 -#define R8A77965_CLK_SSP1 38 -#define R8A77965_CLK_SSPRS 39 -#define R8A77965_CLK_RPC 40 -#define R8A77965_CLK_RPCD2 41 -#define R8A77965_CLK_MSO 42 -#define R8A77965_CLK_CANFD 43 -#define R8A77965_CLK_HDMI 44 -#define R8A77965_CLK_CSI0 45 -#define R8A77965_CLK_CP 46 -#define R8A77965_CLK_CPEX 47 -#define R8A77965_CLK_R 48 -#define R8A77965_CLK_OSC 49 - -#endif /* __DT_BINDINGS_CLOCK_R8A77965_CPG_MSSR_H__ */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/r8a77970-cpg-mssr.h b/sys/gnu/dts/include/dt-bindings/clock/r8a77970-cpg-mssr.h deleted file mode 100644 index 6145ebe6636..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/r8a77970-cpg-mssr.h +++ /dev/null @@ -1,44 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ - * - * Copyright (C) 2016 Renesas Electronics Corp. - * Copyright (C) 2017 Cogent Embedded, Inc. - */ -#ifndef __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__ -#define __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__ - -#include - -/* r8a77970 CPG Core Clocks */ -#define R8A77970_CLK_Z2 0 -#define R8A77970_CLK_ZR 1 -#define R8A77970_CLK_ZTR 2 -#define R8A77970_CLK_ZTRD2 3 -#define R8A77970_CLK_ZT 4 -#define R8A77970_CLK_ZX 5 -#define R8A77970_CLK_S1D1 6 -#define R8A77970_CLK_S1D2 7 -#define R8A77970_CLK_S1D4 8 -#define R8A77970_CLK_S2D1 9 -#define R8A77970_CLK_S2D2 10 -#define R8A77970_CLK_S2D4 11 -#define R8A77970_CLK_LB 12 -#define R8A77970_CLK_CL 13 -#define R8A77970_CLK_ZB3 14 -#define R8A77970_CLK_ZB3D2 15 -#define R8A77970_CLK_DDR 16 -#define R8A77970_CLK_CR 17 -#define R8A77970_CLK_CRD2 18 -#define R8A77970_CLK_SD0H 19 -#define R8A77970_CLK_SD0 20 -#define R8A77970_CLK_RPC 21 -#define R8A77970_CLK_RPCD2 22 -#define R8A77970_CLK_MSO 23 -#define R8A77970_CLK_CANFD 24 -#define R8A77970_CLK_CSI0 25 -#define R8A77970_CLK_FRAY 26 -#define R8A77970_CLK_CP 27 -#define R8A77970_CLK_CPEX 28 -#define R8A77970_CLK_R 29 -#define R8A77970_CLK_OSC 30 - -#endif /* __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__ */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/r8a77980-cpg-mssr.h b/sys/gnu/dts/include/dt-bindings/clock/r8a77980-cpg-mssr.h deleted file mode 100644 index a4c0d76c392..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/r8a77980-cpg-mssr.h +++ /dev/null @@ -1,51 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2018 Renesas Electronics Corp. - * Copyright (C) 2018 Cogent Embedded, Inc. - */ -#ifndef __DT_BINDINGS_CLOCK_R8A77980_CPG_MSSR_H__ -#define __DT_BINDINGS_CLOCK_R8A77980_CPG_MSSR_H__ - -#include - -/* r8a77980 CPG Core Clocks */ -#define R8A77980_CLK_Z2 0 -#define R8A77980_CLK_ZR 1 -#define R8A77980_CLK_ZTR 2 -#define R8A77980_CLK_ZTRD2 3 -#define R8A77980_CLK_ZT 4 -#define R8A77980_CLK_ZX 5 -#define R8A77980_CLK_S0D1 6 -#define R8A77980_CLK_S0D2 7 -#define R8A77980_CLK_S0D3 8 -#define R8A77980_CLK_S0D4 9 -#define R8A77980_CLK_S0D6 10 -#define R8A77980_CLK_S0D12 11 -#define R8A77980_CLK_S0D24 12 -#define R8A77980_CLK_S1D1 13 -#define R8A77980_CLK_S1D2 14 -#define R8A77980_CLK_S1D4 15 -#define R8A77980_CLK_S2D1 16 -#define R8A77980_CLK_S2D2 17 -#define R8A77980_CLK_S2D4 18 -#define R8A77980_CLK_S3D1 19 -#define R8A77980_CLK_S3D2 20 -#define R8A77980_CLK_S3D4 21 -#define R8A77980_CLK_LB 22 -#define R8A77980_CLK_CL 23 -#define R8A77980_CLK_ZB3 24 -#define R8A77980_CLK_ZB3D2 25 -#define R8A77980_CLK_ZB3D4 26 -#define R8A77980_CLK_SD0H 27 -#define R8A77980_CLK_SD0 28 -#define R8A77980_CLK_RPC 29 -#define R8A77980_CLK_RPCD2 30 -#define R8A77980_CLK_MSO 31 -#define R8A77980_CLK_CANFD 32 -#define R8A77980_CLK_CSI0 33 -#define R8A77980_CLK_CP 34 -#define R8A77980_CLK_CPEX 35 -#define R8A77980_CLK_R 36 -#define R8A77980_CLK_OSC 37 - -#endif /* __DT_BINDINGS_CLOCK_R8A77980_CPG_MSSR_H__ */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/r8a77990-cpg-mssr.h b/sys/gnu/dts/include/dt-bindings/clock/r8a77990-cpg-mssr.h deleted file mode 100644 index a596a482f3a..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/r8a77990-cpg-mssr.h +++ /dev/null @@ -1,62 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2018 Renesas Electronics Corp. - */ -#ifndef __DT_BINDINGS_CLOCK_R8A77990_CPG_MSSR_H__ -#define __DT_BINDINGS_CLOCK_R8A77990_CPG_MSSR_H__ - -#include - -/* r8a77990 CPG Core Clocks */ -#define R8A77990_CLK_Z2 0 -#define R8A77990_CLK_ZR 1 -#define R8A77990_CLK_ZG 2 -#define R8A77990_CLK_ZTR 3 -#define R8A77990_CLK_ZT 4 -#define R8A77990_CLK_ZX 5 -#define R8A77990_CLK_S0D1 6 -#define R8A77990_CLK_S0D3 7 -#define R8A77990_CLK_S0D6 8 -#define R8A77990_CLK_S0D12 9 -#define R8A77990_CLK_S0D24 10 -#define R8A77990_CLK_S1D1 11 -#define R8A77990_CLK_S1D2 12 -#define R8A77990_CLK_S1D4 13 -#define R8A77990_CLK_S2D1 14 -#define R8A77990_CLK_S2D2 15 -#define R8A77990_CLK_S2D4 16 -#define R8A77990_CLK_S3D1 17 -#define R8A77990_CLK_S3D2 18 -#define R8A77990_CLK_S3D4 19 -#define R8A77990_CLK_S0D6C 20 -#define R8A77990_CLK_S3D1C 21 -#define R8A77990_CLK_S3D2C 22 -#define R8A77990_CLK_S3D4C 23 -#define R8A77990_CLK_LB 24 -#define R8A77990_CLK_CL 25 -#define R8A77990_CLK_ZB3 26 -#define R8A77990_CLK_ZB3D2 27 -#define R8A77990_CLK_CR 28 -#define R8A77990_CLK_CRD2 29 -#define R8A77990_CLK_SD0H 30 -#define R8A77990_CLK_SD0 31 -#define R8A77990_CLK_SD1H 32 -#define R8A77990_CLK_SD1 33 -#define R8A77990_CLK_SD3H 34 -#define R8A77990_CLK_SD3 35 -#define R8A77990_CLK_RPC 36 -#define R8A77990_CLK_RPCD2 37 -#define R8A77990_CLK_ZA2 38 -#define R8A77990_CLK_ZA8 39 -#define R8A77990_CLK_Z2D 40 -#define R8A77990_CLK_CANFD 41 -#define R8A77990_CLK_MSO 42 -#define R8A77990_CLK_R 43 -#define R8A77990_CLK_OSC 44 -#define R8A77990_CLK_LV0 45 -#define R8A77990_CLK_LV1 46 -#define R8A77990_CLK_CSI0 47 -#define R8A77990_CLK_CP 48 -#define R8A77990_CLK_CPEX 49 - -#endif /* __DT_BINDINGS_CLOCK_R8A77990_CPG_MSSR_H__ */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/r8a77995-cpg-mssr.h b/sys/gnu/dts/include/dt-bindings/clock/r8a77995-cpg-mssr.h deleted file mode 100644 index fd701c4e87c..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/r8a77995-cpg-mssr.h +++ /dev/null @@ -1,54 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ - * - * Copyright (C) 2017 Glider bvba - */ -#ifndef __DT_BINDINGS_CLOCK_R8A77995_CPG_MSSR_H__ -#define __DT_BINDINGS_CLOCK_R8A77995_CPG_MSSR_H__ - -#include - -/* r8a77995 CPG Core Clocks */ -#define R8A77995_CLK_Z2 0 -#define R8A77995_CLK_ZG 1 -#define R8A77995_CLK_ZTR 2 -#define R8A77995_CLK_ZT 3 -#define R8A77995_CLK_ZX 4 -#define R8A77995_CLK_S0D1 5 -#define R8A77995_CLK_S1D1 6 -#define R8A77995_CLK_S1D2 7 -#define R8A77995_CLK_S1D4 8 -#define R8A77995_CLK_S2D1 9 -#define R8A77995_CLK_S2D2 10 -#define R8A77995_CLK_S2D4 11 -#define R8A77995_CLK_S3D1 12 -#define R8A77995_CLK_S3D2 13 -#define R8A77995_CLK_S3D4 14 -#define R8A77995_CLK_S1D4C 15 -#define R8A77995_CLK_S3D1C 16 -#define R8A77995_CLK_S3D2C 17 -#define R8A77995_CLK_S3D4C 18 -#define R8A77995_CLK_LB 19 -#define R8A77995_CLK_CL 20 -#define R8A77995_CLK_ZB3 21 -#define R8A77995_CLK_ZB3D2 22 -#define R8A77995_CLK_CR 23 -#define R8A77995_CLK_CRD2 24 -#define R8A77995_CLK_SD0H 25 -#define R8A77995_CLK_SD0 26 -/* CLK_SSP2 was removed */ -/* CLK_SSP1 was removed */ -#define R8A77995_CLK_RPC 29 -#define R8A77995_CLK_RPCD2 30 -#define R8A77995_CLK_ZA2 31 -#define R8A77995_CLK_ZA8 32 -#define R8A77995_CLK_Z2D 33 -#define R8A77995_CLK_CANFD 34 -#define R8A77995_CLK_MSO 35 -#define R8A77995_CLK_R 36 -#define R8A77995_CLK_OSC 37 -#define R8A77995_CLK_LV0 38 -#define R8A77995_CLK_LV1 39 -#define R8A77995_CLK_CP 40 -#define R8A77995_CLK_CPEX 41 - -#endif /* __DT_BINDINGS_CLOCK_R8A77995_CPG_MSSR_H__ */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/r9a06g032-sysctrl.h b/sys/gnu/dts/include/dt-bindings/clock/r9a06g032-sysctrl.h deleted file mode 100644 index 90c0f3dc1ba..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/r9a06g032-sysctrl.h +++ /dev/null @@ -1,148 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * R9A06G032 sysctrl IDs - * - * Copyright (C) 2018 Renesas Electronics Europe Limited - * - * Michel Pollet , - */ - -#ifndef __DT_BINDINGS_R9A06G032_SYSCTRL_H__ -#define __DT_BINDINGS_R9A06G032_SYSCTRL_H__ - -#define R9A06G032_CLK_PLL_USB 1 -#define R9A06G032_CLK_48 1 /* AKA CLK_PLL_USB */ -#define R9A06G032_MSEBIS_CLK 3 /* AKA CLKOUT_D16 */ -#define R9A06G032_MSEBIM_CLK 3 /* AKA CLKOUT_D16 */ -#define R9A06G032_CLK_DDRPHY_PLLCLK 5 /* AKA CLKOUT_D1OR2 */ -#define R9A06G032_CLK50 6 /* AKA CLKOUT_D20 */ -#define R9A06G032_CLK25 7 /* AKA CLKOUT_D40 */ -#define R9A06G032_CLK125 9 /* AKA CLKOUT_D8 */ -#define R9A06G032_CLK_P5_PG1 17 /* AKA DIV_P5_PG */ -#define R9A06G032_CLK_REF_SYNC 21 /* AKA DIV_REF_SYNC */ -#define R9A06G032_CLK_25_PG4 26 -#define R9A06G032_CLK_25_PG5 27 -#define R9A06G032_CLK_25_PG6 28 -#define R9A06G032_CLK_25_PG7 29 -#define R9A06G032_CLK_25_PG8 30 -#define R9A06G032_CLK_ADC 31 -#define R9A06G032_CLK_ECAT100 32 -#define R9A06G032_CLK_HSR100 33 -#define R9A06G032_CLK_I2C0 34 -#define R9A06G032_CLK_I2C1 35 -#define R9A06G032_CLK_MII_REF 36 -#define R9A06G032_CLK_NAND 37 -#define R9A06G032_CLK_NOUSBP2_PG6 38 -#define R9A06G032_CLK_P1_PG2 39 -#define R9A06G032_CLK_P1_PG3 40 -#define R9A06G032_CLK_P1_PG4 41 -#define R9A06G032_CLK_P4_PG3 42 -#define R9A06G032_CLK_P4_PG4 43 -#define R9A06G032_CLK_P6_PG1 44 -#define R9A06G032_CLK_P6_PG2 45 -#define R9A06G032_CLK_P6_PG3 46 -#define R9A06G032_CLK_P6_PG4 47 -#define R9A06G032_CLK_PCI_USB 48 -#define R9A06G032_CLK_QSPI0 49 -#define R9A06G032_CLK_QSPI1 50 -#define R9A06G032_CLK_RGMII_REF 51 -#define R9A06G032_CLK_RMII_REF 52 -#define R9A06G032_CLK_SDIO0 53 -#define R9A06G032_CLK_SDIO1 54 -#define R9A06G032_CLK_SERCOS100 55 -#define R9A06G032_CLK_SLCD 56 -#define R9A06G032_CLK_SPI0 57 -#define R9A06G032_CLK_SPI1 58 -#define R9A06G032_CLK_SPI2 59 -#define R9A06G032_CLK_SPI3 60 -#define R9A06G032_CLK_SPI4 61 -#define R9A06G032_CLK_SPI5 62 -#define R9A06G032_CLK_SWITCH 63 -#define R9A06G032_HCLK_ECAT125 65 -#define R9A06G032_HCLK_PINCONFIG 66 -#define R9A06G032_HCLK_SERCOS 67 -#define R9A06G032_HCLK_SGPIO2 68 -#define R9A06G032_HCLK_SGPIO3 69 -#define R9A06G032_HCLK_SGPIO4 70 -#define R9A06G032_HCLK_TIMER0 71 -#define R9A06G032_HCLK_TIMER1 72 -#define R9A06G032_HCLK_USBF 73 -#define R9A06G032_HCLK_USBH 74 -#define R9A06G032_HCLK_USBPM 75 -#define R9A06G032_CLK_48_PG_F 76 -#define R9A06G032_CLK_48_PG4 77 -#define R9A06G032_CLK_DDRPHY_PCLK 81 /* AKA CLK_REF_SYNC_D4 */ -#define R9A06G032_CLK_FW 81 /* AKA CLK_REF_SYNC_D4 */ -#define R9A06G032_CLK_CRYPTO 81 /* AKA CLK_REF_SYNC_D4 */ -#define R9A06G032_CLK_A7MP 84 /* AKA DIV_CA7 */ -#define R9A06G032_HCLK_CAN0 85 -#define R9A06G032_HCLK_CAN1 86 -#define R9A06G032_HCLK_DELTASIGMA 87 -#define R9A06G032_HCLK_PWMPTO 88 -#define R9A06G032_HCLK_RSV 89 -#define R9A06G032_HCLK_SGPIO0 90 -#define R9A06G032_HCLK_SGPIO1 91 -#define R9A06G032_RTOS_MDC 92 -#define R9A06G032_CLK_CM3 93 -#define R9A06G032_CLK_DDRC 94 -#define R9A06G032_CLK_ECAT25 95 -#define R9A06G032_CLK_HSR50 96 -#define R9A06G032_CLK_HW_RTOS 97 -#define R9A06G032_CLK_SERCOS50 98 -#define R9A06G032_HCLK_ADC 99 -#define R9A06G032_HCLK_CM3 100 -#define R9A06G032_HCLK_CRYPTO_EIP150 101 -#define R9A06G032_HCLK_CRYPTO_EIP93 102 -#define R9A06G032_HCLK_DDRC 103 -#define R9A06G032_HCLK_DMA0 104 -#define R9A06G032_HCLK_DMA1 105 -#define R9A06G032_HCLK_GMAC0 106 -#define R9A06G032_HCLK_GMAC1 107 -#define R9A06G032_HCLK_GPIO0 108 -#define R9A06G032_HCLK_GPIO1 109 -#define R9A06G032_HCLK_GPIO2 110 -#define R9A06G032_HCLK_HSR 111 -#define R9A06G032_HCLK_I2C0 112 -#define R9A06G032_HCLK_I2C1 113 -#define R9A06G032_HCLK_LCD 114 -#define R9A06G032_HCLK_MSEBI_M 115 -#define R9A06G032_HCLK_MSEBI_S 116 -#define R9A06G032_HCLK_NAND 117 -#define R9A06G032_HCLK_PG_I 118 -#define R9A06G032_HCLK_PG19 119 -#define R9A06G032_HCLK_PG20 120 -#define R9A06G032_HCLK_PG3 121 -#define R9A06G032_HCLK_PG4 122 -#define R9A06G032_HCLK_QSPI0 123 -#define R9A06G032_HCLK_QSPI1 124 -#define R9A06G032_HCLK_ROM 125 -#define R9A06G032_HCLK_RTC 126 -#define R9A06G032_HCLK_SDIO0 127 -#define R9A06G032_HCLK_SDIO1 128 -#define R9A06G032_HCLK_SEMAP 129 -#define R9A06G032_HCLK_SPI0 130 -#define R9A06G032_HCLK_SPI1 131 -#define R9A06G032_HCLK_SPI2 132 -#define R9A06G032_HCLK_SPI3 133 -#define R9A06G032_HCLK_SPI4 134 -#define R9A06G032_HCLK_SPI5 135 -#define R9A06G032_HCLK_SWITCH 136 -#define R9A06G032_HCLK_SWITCH_RG 137 -#define R9A06G032_HCLK_UART0 138 -#define R9A06G032_HCLK_UART1 139 -#define R9A06G032_HCLK_UART2 140 -#define R9A06G032_HCLK_UART3 141 -#define R9A06G032_HCLK_UART4 142 -#define R9A06G032_HCLK_UART5 143 -#define R9A06G032_HCLK_UART6 144 -#define R9A06G032_HCLK_UART7 145 -#define R9A06G032_CLK_UART0 146 -#define R9A06G032_CLK_UART1 147 -#define R9A06G032_CLK_UART2 148 -#define R9A06G032_CLK_UART3 149 -#define R9A06G032_CLK_UART4 150 -#define R9A06G032_CLK_UART5 151 -#define R9A06G032_CLK_UART6 152 -#define R9A06G032_CLK_UART7 153 - -#endif /* __DT_BINDINGS_R9A06G032_SYSCTRL_H__ */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/renesas-cpg-mssr.h b/sys/gnu/dts/include/dt-bindings/clock/renesas-cpg-mssr.h deleted file mode 100644 index 8169ad063f0..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/renesas-cpg-mssr.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ - * - * Copyright (C) 2015 Renesas Electronics Corp. - */ -#ifndef __DT_BINDINGS_CLOCK_RENESAS_CPG_MSSR_H__ -#define __DT_BINDINGS_CLOCK_RENESAS_CPG_MSSR_H__ - -#define CPG_CORE 0 /* Core Clock */ -#define CPG_MOD 1 /* Module Clock */ - -#endif /* __DT_BINDINGS_CLOCK_RENESAS_CPG_MSSR_H__ */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/rk3036-cru.h b/sys/gnu/dts/include/dt-bindings/clock/rk3036-cru.h deleted file mode 100644 index 35a5a01f969..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/rk3036-cru.h +++ /dev/null @@ -1,186 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright (c) 2015 Rockchip Electronics Co. Ltd. - * Author: Xing Zheng - */ - -#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H -#define _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H - -/* core clocks */ -#define PLL_APLL 1 -#define PLL_DPLL 2 -#define PLL_GPLL 3 -#define ARMCLK 4 - -/* sclk gates (special clocks) */ -#define SCLK_GPU 64 -#define SCLK_SPI 65 -#define SCLK_SDMMC 68 -#define SCLK_SDIO 69 -#define SCLK_EMMC 71 -#define SCLK_NANDC 76 -#define SCLK_UART0 77 -#define SCLK_UART1 78 -#define SCLK_UART2 79 -#define SCLK_I2S 82 -#define SCLK_SPDIF 83 -#define SCLK_TIMER0 85 -#define SCLK_TIMER1 86 -#define SCLK_TIMER2 87 -#define SCLK_TIMER3 88 -#define SCLK_OTGPHY0 93 -#define SCLK_LCDC 100 -#define SCLK_HDMI 109 -#define SCLK_HEVC 111 -#define SCLK_I2S_OUT 113 -#define SCLK_SDMMC_DRV 114 -#define SCLK_SDIO_DRV 115 -#define SCLK_EMMC_DRV 117 -#define SCLK_SDMMC_SAMPLE 118 -#define SCLK_SDIO_SAMPLE 119 -#define SCLK_EMMC_SAMPLE 121 -#define SCLK_PVTM_CORE 123 -#define SCLK_PVTM_GPU 124 -#define SCLK_PVTM_VIDEO 125 -#define SCLK_MAC 151 -#define SCLK_MACREF 152 -#define SCLK_MACPLL 153 -#define SCLK_SFC 160 - -/* aclk gates */ -#define ACLK_DMAC2 194 -#define ACLK_LCDC 197 -#define ACLK_VIO 203 -#define ACLK_VCODEC 208 -#define ACLK_CPU 209 -#define ACLK_PERI 210 - -/* pclk gates */ -#define PCLK_GPIO0 320 -#define PCLK_GPIO1 321 -#define PCLK_GPIO2 322 -#define PCLK_GRF 329 -#define PCLK_I2C0 332 -#define PCLK_I2C1 333 -#define PCLK_I2C2 334 -#define PCLK_SPI 338 -#define PCLK_UART0 341 -#define PCLK_UART1 342 -#define PCLK_UART2 343 -#define PCLK_PWM 350 -#define PCLK_TIMER 353 -#define PCLK_HDMI 360 -#define PCLK_CPU 362 -#define PCLK_PERI 363 -#define PCLK_DDRUPCTL 364 -#define PCLK_WDT 368 -#define PCLK_ACODEC 369 - -/* hclk gates */ -#define HCLK_OTG0 449 -#define HCLK_OTG1 450 -#define HCLK_NANDC 453 -#define HCLK_SDMMC 456 -#define HCLK_SDIO 457 -#define HCLK_EMMC 459 -#define HCLK_MAC 460 -#define HCLK_I2S 462 -#define HCLK_LCDC 465 -#define HCLK_ROM 467 -#define HCLK_VIO_BUS 472 -#define HCLK_VCODEC 476 -#define HCLK_CPU 477 -#define HCLK_PERI 478 - -#define CLK_NR_CLKS (HCLK_PERI + 1) - -/* soft-reset indices */ -#define SRST_CORE0 0 -#define SRST_CORE1 1 -#define SRST_CORE0_DBG 4 -#define SRST_CORE1_DBG 5 -#define SRST_CORE0_POR 8 -#define SRST_CORE1_POR 9 -#define SRST_L2C 12 -#define SRST_TOPDBG 13 -#define SRST_STRC_SYS_A 14 -#define SRST_PD_CORE_NIU 15 - -#define SRST_TIMER2 16 -#define SRST_CPUSYS_H 17 -#define SRST_AHB2APB_H 19 -#define SRST_TIMER3 20 -#define SRST_INTMEM 21 -#define SRST_ROM 22 -#define SRST_PERI_NIU 23 -#define SRST_I2S 24 -#define SRST_DDR_PLL 25 -#define SRST_GPU_DLL 26 -#define SRST_TIMER0 27 -#define SRST_TIMER1 28 -#define SRST_CORE_DLL 29 -#define SRST_EFUSE_P 30 -#define SRST_ACODEC_P 31 - -#define SRST_GPIO0 32 -#define SRST_GPIO1 33 -#define SRST_GPIO2 34 -#define SRST_UART0 39 -#define SRST_UART1 40 -#define SRST_UART2 41 -#define SRST_I2C0 43 -#define SRST_I2C1 44 -#define SRST_I2C2 45 -#define SRST_SFC 47 - -#define SRST_PWM0 48 -#define SRST_DAP 51 -#define SRST_DAP_SYS 52 -#define SRST_GRF 55 -#define SRST_PERIPHSYS_A 57 -#define SRST_PERIPHSYS_H 58 -#define SRST_PERIPHSYS_P 59 -#define SRST_CPU_PERI 61 -#define SRST_EMEM_PERI 62 -#define SRST_USB_PERI 63 - -#define SRST_DMA2 64 -#define SRST_MAC 66 -#define SRST_NANDC 68 -#define SRST_USBOTG0 69 -#define SRST_OTGC0 71 -#define SRST_USBOTG1 72 -#define SRST_OTGC1 74 -#define SRST_DDRMSCH 79 - -#define SRST_MMC0 81 -#define SRST_SDIO 82 -#define SRST_EMMC 83 -#define SRST_SPI0 84 -#define SRST_WDT 86 -#define SRST_DDRPHY 88 -#define SRST_DDRPHY_P 89 -#define SRST_DDRCTRL 90 -#define SRST_DDRCTRL_P 91 - -#define SRST_HDMI_P 96 -#define SRST_VIO_BUS_H 99 -#define SRST_UTMI0 103 -#define SRST_UTMI1 104 -#define SRST_USBPOR 105 - -#define SRST_VCODEC_A 112 -#define SRST_VCODEC_H 113 -#define SRST_VIO1_A 114 -#define SRST_HEVC 115 -#define SRST_VCODEC_NIU_A 116 -#define SRST_LCDC1_A 117 -#define SRST_LCDC1_H 118 -#define SRST_LCDC1_D 119 -#define SRST_GPU 120 -#define SRST_GPU_NIU_A 122 - -#define SRST_DBG_P 131 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/rk3066a-cru.h b/sys/gnu/dts/include/dt-bindings/clock/rk3066a-cru.h deleted file mode 100644 index 553f9728350..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/rk3066a-cru.h +++ /dev/null @@ -1,31 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright (c) 2014 MundoReader S.L. - * Author: Heiko Stuebner - */ - -#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3066A_H -#define _DT_BINDINGS_CLK_ROCKCHIP_RK3066A_H - -#include - -/* soft-reset indices */ -#define SRST_SRST1 0 -#define SRST_SRST2 1 - -#define SRST_L2MEM 18 -#define SRST_I2S0 23 -#define SRST_I2S1 24 -#define SRST_I2S2 25 -#define SRST_TIMER2 29 - -#define SRST_GPIO4 36 -#define SRST_GPIO6 38 - -#define SRST_TSADC 92 - -#define SRST_HDMI 96 -#define SRST_HDMI_APB 97 -#define SRST_CIF1 111 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/rk3128-cru.h b/sys/gnu/dts/include/dt-bindings/clock/rk3128-cru.h deleted file mode 100644 index 6a47825dac5..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/rk3128-cru.h +++ /dev/null @@ -1,273 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright (c) 2017 Rockchip Electronics Co. Ltd. - * Author: Elaine - */ - -#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3128_H -#define _DT_BINDINGS_CLK_ROCKCHIP_RK3128_H - -/* core clocks */ -#define PLL_APLL 1 -#define PLL_DPLL 2 -#define PLL_CPLL 3 -#define PLL_GPLL 4 -#define ARMCLK 5 -#define PLL_GPLL_DIV2 6 -#define PLL_GPLL_DIV3 7 - -/* sclk gates (special clocks) */ -#define SCLK_SPI0 65 -#define SCLK_NANDC 67 -#define SCLK_SDMMC 68 -#define SCLK_SDIO 69 -#define SCLK_EMMC 71 -#define SCLK_UART0 77 -#define SCLK_UART1 78 -#define SCLK_UART2 79 -#define SCLK_I2S0 80 -#define SCLK_I2S1 81 -#define SCLK_SPDIF 83 -#define SCLK_TIMER0 85 -#define SCLK_TIMER1 86 -#define SCLK_TIMER2 87 -#define SCLK_TIMER3 88 -#define SCLK_TIMER4 89 -#define SCLK_TIMER5 90 -#define SCLK_SARADC 91 -#define SCLK_I2S_OUT 113 -#define SCLK_SDMMC_DRV 114 -#define SCLK_SDIO_DRV 115 -#define SCLK_EMMC_DRV 117 -#define SCLK_SDMMC_SAMPLE 118 -#define SCLK_SDIO_SAMPLE 119 -#define SCLK_EMMC_SAMPLE 121 -#define SCLK_VOP 122 -#define SCLK_MAC_SRC 124 -#define SCLK_MAC 126 -#define SCLK_MAC_REFOUT 127 -#define SCLK_MAC_REF 128 -#define SCLK_MAC_RX 129 -#define SCLK_MAC_TX 130 -#define SCLK_HEVC_CORE 134 -#define SCLK_RGA 135 -#define SCLK_CRYPTO 138 -#define SCLK_TSP 139 -#define SCLK_OTGPHY0 142 -#define SCLK_OTGPHY1 143 -#define SCLK_DDRC 144 -#define SCLK_PVTM_FUNC 145 -#define SCLK_PVTM_CORE 146 -#define SCLK_PVTM_GPU 147 -#define SCLK_MIPI_24M 148 -#define SCLK_PVTM 149 -#define SCLK_CIF_SRC 150 -#define SCLK_CIF_OUT_SRC 151 -#define SCLK_CIF_OUT 152 -#define SCLK_SFC 153 -#define SCLK_USB480M 154 - -/* dclk gates */ -#define DCLK_VOP 190 -#define DCLK_EBC 191 - -/* aclk gates */ -#define ACLK_VIO0 192 -#define ACLK_VIO1 193 -#define ACLK_DMAC 194 -#define ACLK_CPU 195 -#define ACLK_VEPU 196 -#define ACLK_VDPU 197 -#define ACLK_CIF 198 -#define ACLK_IEP 199 -#define ACLK_LCDC0 204 -#define ACLK_RGA 205 -#define ACLK_PERI 210 -#define ACLK_VOP 211 -#define ACLK_GMAC 212 -#define ACLK_GPU 213 - -/* pclk gates */ -#define PCLK_SARADC 318 -#define PCLK_WDT 319 -#define PCLK_GPIO0 320 -#define PCLK_GPIO1 321 -#define PCLK_GPIO2 322 -#define PCLK_GPIO3 323 -#define PCLK_VIO_H2P 324 -#define PCLK_MIPI 325 -#define PCLK_EFUSE 326 -#define PCLK_HDMI 327 -#define PCLK_ACODEC 328 -#define PCLK_GRF 329 -#define PCLK_I2C0 332 -#define PCLK_I2C1 333 -#define PCLK_I2C2 334 -#define PCLK_I2C3 335 -#define PCLK_SPI0 338 -#define PCLK_UART0 341 -#define PCLK_UART1 342 -#define PCLK_UART2 343 -#define PCLK_TSADC 344 -#define PCLK_PWM 350 -#define PCLK_TIMER 353 -#define PCLK_CPU 354 -#define PCLK_PERI 363 -#define PCLK_GMAC 367 -#define PCLK_PMU_PRE 368 -#define PCLK_SIM_CARD 369 - -/* hclk gates */ -#define HCLK_SPDIF 440 -#define HCLK_GPS 441 -#define HCLK_USBHOST 442 -#define HCLK_I2S_8CH 443 -#define HCLK_I2S_2CH 444 -#define HCLK_VOP 452 -#define HCLK_NANDC 453 -#define HCLK_SDMMC 456 -#define HCLK_SDIO 457 -#define HCLK_EMMC 459 -#define HCLK_CPU 460 -#define HCLK_VEPU 461 -#define HCLK_VDPU 462 -#define HCLK_LCDC0 463 -#define HCLK_EBC 465 -#define HCLK_VIO 466 -#define HCLK_RGA 467 -#define HCLK_IEP 468 -#define HCLK_VIO_H2P 469 -#define HCLK_CIF 470 -#define HCLK_HOST2 473 -#define HCLK_OTG 474 -#define HCLK_TSP 475 -#define HCLK_CRYPTO 476 -#define HCLK_PERI 478 - -#define CLK_NR_CLKS (HCLK_PERI + 1) - -/* soft-reset indices */ -#define SRST_CORE0_PO 0 -#define SRST_CORE1_PO 1 -#define SRST_CORE2_PO 2 -#define SRST_CORE3_PO 3 -#define SRST_CORE0 4 -#define SRST_CORE1 5 -#define SRST_CORE2 6 -#define SRST_CORE3 7 -#define SRST_CORE0_DBG 8 -#define SRST_CORE1_DBG 9 -#define SRST_CORE2_DBG 10 -#define SRST_CORE3_DBG 11 -#define SRST_TOPDBG 12 -#define SRST_ACLK_CORE 13 -#define SRST_STRC_SYS_A 14 -#define SRST_L2C 15 - -#define SRST_CPUSYS_H 18 -#define SRST_AHB2APBSYS_H 19 -#define SRST_SPDIF 20 -#define SRST_INTMEM 21 -#define SRST_ROM 22 -#define SRST_PERI_NIU 23 -#define SRST_I2S_2CH 24 -#define SRST_I2S_8CH 25 -#define SRST_GPU_PVTM 26 -#define SRST_FUNC_PVTM 27 -#define SRST_CORE_PVTM 29 -#define SRST_EFUSE_P 30 -#define SRST_ACODEC_P 31 - -#define SRST_GPIO0 32 -#define SRST_GPIO1 33 -#define SRST_GPIO2 34 -#define SRST_GPIO3 35 -#define SRST_MIPIPHY_P 36 -#define SRST_UART0 39 -#define SRST_UART1 40 -#define SRST_UART2 41 -#define SRST_I2C0 43 -#define SRST_I2C1 44 -#define SRST_I2C2 45 -#define SRST_I2C3 46 -#define SRST_SFC 47 - -#define SRST_PWM 48 -#define SRST_DAP_PO 50 -#define SRST_DAP 51 -#define SRST_DAP_SYS 52 -#define SRST_CRYPTO 53 -#define SRST_GRF 55 -#define SRST_GMAC 56 -#define SRST_PERIPH_SYS_A 57 -#define SRST_PERIPH_SYS_H 58 -#define SRST_PERIPH_SYS_P 59 -#define SRST_SMART_CARD 60 -#define SRST_CPU_PERI 61 -#define SRST_EMEM_PERI 62 -#define SRST_USB_PERI 63 - -#define SRST_DMA 64 -#define SRST_GPS 67 -#define SRST_NANDC 68 -#define SRST_USBOTG0 69 -#define SRST_OTGC0 71 -#define SRST_USBOTG1 72 -#define SRST_OTGC1 74 -#define SRST_DDRMSCH 79 - -#define SRST_SDMMC 81 -#define SRST_SDIO 82 -#define SRST_EMMC 83 -#define SRST_SPI 84 -#define SRST_WDT 86 -#define SRST_SARADC 87 -#define SRST_DDRPHY 88 -#define SRST_DDRPHY_P 89 -#define SRST_DDRCTRL 90 -#define SRST_DDRCTRL_P 91 -#define SRST_TSP 92 -#define SRST_TSP_CLKIN 93 -#define SRST_HOST0_ECHI 94 - -#define SRST_HDMI_P 96 -#define SRST_VIO_ARBI_H 97 -#define SRST_VIO0_A 98 -#define SRST_VIO_BUS_H 99 -#define SRST_VOP_A 100 -#define SRST_VOP_H 101 -#define SRST_VOP_D 102 -#define SRST_UTMI0 103 -#define SRST_UTMI1 104 -#define SRST_USBPOR 105 -#define SRST_IEP_A 106 -#define SRST_IEP_H 107 -#define SRST_RGA_A 108 -#define SRST_RGA_H 109 -#define SRST_CIF0 110 -#define SRST_PMU 111 - -#define SRST_VCODEC_A 112 -#define SRST_VCODEC_H 113 -#define SRST_VIO1_A 114 -#define SRST_HEVC_CORE 115 -#define SRST_VCODEC_NIU_A 116 -#define SRST_PMU_NIU_P 117 -#define SRST_LCDC0_S 119 -#define SRST_GPU 120 -#define SRST_GPU_NIU_A 122 -#define SRST_EBC_A 123 -#define SRST_EBC_H 124 - -#define SRST_CORE_DBG 128 -#define SRST_DBG_P 129 -#define SRST_TIMER0 130 -#define SRST_TIMER1 131 -#define SRST_TIMER2 132 -#define SRST_TIMER3 133 -#define SRST_TIMER4 134 -#define SRST_TIMER5 135 -#define SRST_VIO_H2P 136 -#define SRST_VIO_MIPI_DSI 137 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/rk3188-cru-common.h b/sys/gnu/dts/include/dt-bindings/clock/rk3188-cru-common.h deleted file mode 100644 index afad90680fc..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/rk3188-cru-common.h +++ /dev/null @@ -1,261 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright (c) 2014 MundoReader S.L. - * Author: Heiko Stuebner - */ - -#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3188_COMMON_H -#define _DT_BINDINGS_CLK_ROCKCHIP_RK3188_COMMON_H - -/* core clocks from */ -#define PLL_APLL 1 -#define PLL_DPLL 2 -#define PLL_CPLL 3 -#define PLL_GPLL 4 -#define CORE_PERI 5 -#define CORE_L2C 6 -#define ARMCLK 7 - -/* sclk gates (special clocks) */ -#define SCLK_UART0 64 -#define SCLK_UART1 65 -#define SCLK_UART2 66 -#define SCLK_UART3 67 -#define SCLK_MAC 68 -#define SCLK_SPI0 69 -#define SCLK_SPI1 70 -#define SCLK_SARADC 71 -#define SCLK_SDMMC 72 -#define SCLK_SDIO 73 -#define SCLK_EMMC 74 -#define SCLK_I2S0 75 -#define SCLK_I2S1 76 -#define SCLK_I2S2 77 -#define SCLK_SPDIF 78 -#define SCLK_CIF0 79 -#define SCLK_CIF1 80 -#define SCLK_OTGPHY0 81 -#define SCLK_OTGPHY1 82 -#define SCLK_HSADC 83 -#define SCLK_TIMER0 84 -#define SCLK_TIMER1 85 -#define SCLK_TIMER2 86 -#define SCLK_TIMER3 87 -#define SCLK_TIMER4 88 -#define SCLK_TIMER5 89 -#define SCLK_TIMER6 90 -#define SCLK_JTAG 91 -#define SCLK_SMC 92 -#define SCLK_TSADC 93 - -#define DCLK_LCDC0 190 -#define DCLK_LCDC1 191 - -/* aclk gates */ -#define ACLK_DMA1 192 -#define ACLK_DMA2 193 -#define ACLK_GPS 194 -#define ACLK_LCDC0 195 -#define ACLK_LCDC1 196 -#define ACLK_GPU 197 -#define ACLK_SMC 198 -#define ACLK_CIF1 199 -#define ACLK_IPP 200 -#define ACLK_RGA 201 -#define ACLK_CIF0 202 -#define ACLK_CPU 203 -#define ACLK_PERI 204 -#define ACLK_VEPU 205 -#define ACLK_VDPU 206 - -/* pclk gates */ -#define PCLK_GRF 320 -#define PCLK_PMU 321 -#define PCLK_TIMER0 322 -#define PCLK_TIMER1 323 -#define PCLK_TIMER2 324 -#define PCLK_TIMER3 325 -#define PCLK_PWM01 326 -#define PCLK_PWM23 327 -#define PCLK_SPI0 328 -#define PCLK_SPI1 329 -#define PCLK_SARADC 330 -#define PCLK_WDT 331 -#define PCLK_UART0 332 -#define PCLK_UART1 333 -#define PCLK_UART2 334 -#define PCLK_UART3 335 -#define PCLK_I2C0 336 -#define PCLK_I2C1 337 -#define PCLK_I2C2 338 -#define PCLK_I2C3 339 -#define PCLK_I2C4 340 -#define PCLK_GPIO0 341 -#define PCLK_GPIO1 342 -#define PCLK_GPIO2 343 -#define PCLK_GPIO3 344 -#define PCLK_GPIO4 345 -#define PCLK_GPIO6 346 -#define PCLK_EFUSE 347 -#define PCLK_TZPC 348 -#define PCLK_TSADC 349 -#define PCLK_CPU 350 -#define PCLK_PERI 351 -#define PCLK_DDRUPCTL 352 -#define PCLK_PUBL 353 - -/* hclk gates */ -#define HCLK_SDMMC 448 -#define HCLK_SDIO 449 -#define HCLK_EMMC 450 -#define HCLK_OTG0 451 -#define HCLK_EMAC 452 -#define HCLK_SPDIF 453 -#define HCLK_I2S0 454 -#define HCLK_I2S1 455 -#define HCLK_I2S2 456 -#define HCLK_OTG1 457 -#define HCLK_HSIC 458 -#define HCLK_HSADC 459 -#define HCLK_PIDF 460 -#define HCLK_LCDC0 461 -#define HCLK_LCDC1 462 -#define HCLK_ROM 463 -#define HCLK_CIF0 464 -#define HCLK_IPP 465 -#define HCLK_RGA 466 -#define HCLK_NANDC0 467 -#define HCLK_CPU 468 -#define HCLK_PERI 469 -#define HCLK_CIF1 470 -#define HCLK_VEPU 471 -#define HCLK_VDPU 472 -#define HCLK_HDMI 473 - -#define CLK_NR_CLKS (HCLK_HDMI + 1) - -/* soft-reset indices */ -#define SRST_MCORE 2 -#define SRST_CORE0 3 -#define SRST_CORE1 4 -#define SRST_MCORE_DBG 7 -#define SRST_CORE0_DBG 8 -#define SRST_CORE1_DBG 9 -#define SRST_CORE0_WDT 12 -#define SRST_CORE1_WDT 13 -#define SRST_STRC_SYS 14 -#define SRST_L2C 15 - -#define SRST_CPU_AHB 17 -#define SRST_AHB2APB 19 -#define SRST_DMA1 20 -#define SRST_INTMEM 21 -#define SRST_ROM 22 -#define SRST_SPDIF 26 -#define SRST_TIMER0 27 -#define SRST_TIMER1 28 -#define SRST_EFUSE 30 - -#define SRST_GPIO0 32 -#define SRST_GPIO1 33 -#define SRST_GPIO2 34 -#define SRST_GPIO3 35 - -#define SRST_UART0 39 -#define SRST_UART1 40 -#define SRST_UART2 41 -#define SRST_UART3 42 -#define SRST_I2C0 43 -#define SRST_I2C1 44 -#define SRST_I2C2 45 -#define SRST_I2C3 46 -#define SRST_I2C4 47 - -#define SRST_PWM0 48 -#define SRST_PWM1 49 -#define SRST_DAP_PO 50 -#define SRST_DAP 51 -#define SRST_DAP_SYS 52 -#define SRST_TPIU_ATB 53 -#define SRST_PMU_APB 54 -#define SRST_GRF 55 -#define SRST_PMU 56 -#define SRST_PERI_AXI 57 -#define SRST_PERI_AHB 58 -#define SRST_PERI_APB 59 -#define SRST_PERI_NIU 60 -#define SRST_CPU_PERI 61 -#define SRST_EMEM_PERI 62 -#define SRST_USB_PERI 63 - -#define SRST_DMA2 64 -#define SRST_SMC 65 -#define SRST_MAC 66 -#define SRST_NANC0 68 -#define SRST_USBOTG0 69 -#define SRST_USBPHY0 70 -#define SRST_OTGC0 71 -#define SRST_USBOTG1 72 -#define SRST_USBPHY1 73 -#define SRST_OTGC1 74 -#define SRST_HSADC 76 -#define SRST_PIDFILTER 77 -#define SRST_DDR_MSCH 79 - -#define SRST_TZPC 80 -#define SRST_SDMMC 81 -#define SRST_SDIO 82 -#define SRST_EMMC 83 -#define SRST_SPI0 84 -#define SRST_SPI1 85 -#define SRST_WDT 86 -#define SRST_SARADC 87 -#define SRST_DDRPHY 88 -#define SRST_DDRPHY_APB 89 -#define SRST_DDRCTL 90 -#define SRST_DDRCTL_APB 91 -#define SRST_DDRPUB 93 - -#define SRST_VIO0_AXI 98 -#define SRST_VIO0_AHB 99 -#define SRST_LCDC0_AXI 100 -#define SRST_LCDC0_AHB 101 -#define SRST_LCDC0_DCLK 102 -#define SRST_LCDC1_AXI 103 -#define SRST_LCDC1_AHB 104 -#define SRST_LCDC1_DCLK 105 -#define SRST_IPP_AXI 106 -#define SRST_IPP_AHB 107 -#define SRST_RGA_AXI 108 -#define SRST_RGA_AHB 109 -#define SRST_CIF0 110 - -#define SRST_VCODEC_AXI 112 -#define SRST_VCODEC_AHB 113 -#define SRST_VIO1_AXI 114 -#define SRST_VCODEC_CPU 115 -#define SRST_VCODEC_NIU 116 -#define SRST_GPU 120 -#define SRST_GPU_NIU 122 -#define SRST_TFUN_ATB 125 -#define SRST_TFUN_APB 126 -#define SRST_CTI4_APB 127 - -#define SRST_TPIU_APB 128 -#define SRST_TRACE 129 -#define SRST_CORE_DBG 130 -#define SRST_DBG_APB 131 -#define SRST_CTI0 132 -#define SRST_CTI0_APB 133 -#define SRST_CTI1 134 -#define SRST_CTI1_APB 135 -#define SRST_PTM_CORE0 136 -#define SRST_PTM_CORE1 137 -#define SRST_PTM0 138 -#define SRST_PTM0_ATB 139 -#define SRST_PTM1 140 -#define SRST_PTM1_ATB 141 -#define SRST_CTM 142 -#define SRST_TS 143 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/rk3188-cru.h b/sys/gnu/dts/include/dt-bindings/clock/rk3188-cru.h deleted file mode 100644 index c45916ae687..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/rk3188-cru.h +++ /dev/null @@ -1,47 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright (c) 2014 MundoReader S.L. - * Author: Heiko Stuebner - */ - -#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3188_H -#define _DT_BINDINGS_CLK_ROCKCHIP_RK3188_H - -#include - -/* soft-reset indices */ -#define SRST_PTM_CORE2 0 -#define SRST_PTM_CORE3 1 -#define SRST_CORE2 5 -#define SRST_CORE3 6 -#define SRST_CORE2_DBG 10 -#define SRST_CORE3_DBG 11 - -#define SRST_TIMER2 16 -#define SRST_TIMER4 23 -#define SRST_I2S0 24 -#define SRST_TIMER5 25 -#define SRST_TIMER3 29 -#define SRST_TIMER6 31 - -#define SRST_PTM3 36 -#define SRST_PTM3_ATB 37 - -#define SRST_GPS 67 -#define SRST_HSICPHY 75 -#define SRST_TIMER 78 - -#define SRST_PTM2 92 -#define SRST_CORE2_WDT 94 -#define SRST_CORE3_WDT 95 - -#define SRST_PTM2_ATB 111 - -#define SRST_HSIC 117 -#define SRST_CTI2 118 -#define SRST_CTI2_APB 119 -#define SRST_GPU_BRIDGE 121 -#define SRST_CTI3 123 -#define SRST_CTI3_APB 124 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/rk3228-cru.h b/sys/gnu/dts/include/dt-bindings/clock/rk3228-cru.h deleted file mode 100644 index de550ea56ee..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/rk3228-cru.h +++ /dev/null @@ -1,287 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright (c) 2015 Rockchip Electronics Co. Ltd. - * Author: Jeffy Chen - */ - -#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H -#define _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H - -/* core clocks */ -#define PLL_APLL 1 -#define PLL_DPLL 2 -#define PLL_CPLL 3 -#define PLL_GPLL 4 -#define ARMCLK 5 - -/* sclk gates (special clocks) */ -#define SCLK_SPI0 65 -#define SCLK_NANDC 67 -#define SCLK_SDMMC 68 -#define SCLK_SDIO 69 -#define SCLK_EMMC 71 -#define SCLK_TSADC 72 -#define SCLK_UART0 77 -#define SCLK_UART1 78 -#define SCLK_UART2 79 -#define SCLK_I2S0 80 -#define SCLK_I2S1 81 -#define SCLK_I2S2 82 -#define SCLK_SPDIF 83 -#define SCLK_TIMER0 85 -#define SCLK_TIMER1 86 -#define SCLK_TIMER2 87 -#define SCLK_TIMER3 88 -#define SCLK_TIMER4 89 -#define SCLK_TIMER5 90 -#define SCLK_I2S_OUT 113 -#define SCLK_SDMMC_DRV 114 -#define SCLK_SDIO_DRV 115 -#define SCLK_EMMC_DRV 117 -#define SCLK_SDMMC_SAMPLE 118 -#define SCLK_SDIO_SAMPLE 119 -#define SCLK_SDIO_SRC 120 -#define SCLK_EMMC_SAMPLE 121 -#define SCLK_VOP 122 -#define SCLK_HDMI_HDCP 123 -#define SCLK_MAC_SRC 124 -#define SCLK_MAC_EXTCLK 125 -#define SCLK_MAC 126 -#define SCLK_MAC_REFOUT 127 -#define SCLK_MAC_REF 128 -#define SCLK_MAC_RX 129 -#define SCLK_MAC_TX 130 -#define SCLK_MAC_PHY 131 -#define SCLK_MAC_OUT 132 -#define SCLK_VDEC_CABAC 133 -#define SCLK_VDEC_CORE 134 -#define SCLK_RGA 135 -#define SCLK_HDCP 136 -#define SCLK_HDMI_CEC 137 -#define SCLK_CRYPTO 138 -#define SCLK_TSP 139 -#define SCLK_HSADC 140 -#define SCLK_WIFI 141 -#define SCLK_OTGPHY0 142 -#define SCLK_OTGPHY1 143 -#define SCLK_HDMI_PHY 144 - -/* dclk gates */ -#define DCLK_VOP 190 -#define DCLK_HDMI_PHY 191 - -/* aclk gates */ -#define ACLK_DMAC 194 -#define ACLK_CPU 195 -#define ACLK_VPU_PRE 196 -#define ACLK_RKVDEC_PRE 197 -#define ACLK_RGA_PRE 198 -#define ACLK_IEP_PRE 199 -#define ACLK_HDCP_PRE 200 -#define ACLK_VOP_PRE 201 -#define ACLK_VPU 202 -#define ACLK_RKVDEC 203 -#define ACLK_IEP 204 -#define ACLK_RGA 205 -#define ACLK_HDCP 206 -#define ACLK_PERI 210 -#define ACLK_VOP 211 -#define ACLK_GMAC 212 -#define ACLK_GPU 213 - -/* pclk gates */ -#define PCLK_GPIO0 320 -#define PCLK_GPIO1 321 -#define PCLK_GPIO2 322 -#define PCLK_GPIO3 323 -#define PCLK_VIO_H2P 324 -#define PCLK_HDCP 325 -#define PCLK_EFUSE_1024 326 -#define PCLK_EFUSE_256 327 -#define PCLK_GRF 329 -#define PCLK_I2C0 332 -#define PCLK_I2C1 333 -#define PCLK_I2C2 334 -#define PCLK_I2C3 335 -#define PCLK_SPI0 338 -#define PCLK_UART0 341 -#define PCLK_UART1 342 -#define PCLK_UART2 343 -#define PCLK_TSADC 344 -#define PCLK_PWM 350 -#define PCLK_TIMER 353 -#define PCLK_CPU 354 -#define PCLK_PERI 363 -#define PCLK_HDMI_CTRL 364 -#define PCLK_HDMI_PHY 365 -#define PCLK_GMAC 367 - -/* hclk gates */ -#define HCLK_I2S0_8CH 442 -#define HCLK_I2S1_8CH 443 -#define HCLK_I2S2_2CH 444 -#define HCLK_SPDIF_8CH 445 -#define HCLK_VOP 452 -#define HCLK_NANDC 453 -#define HCLK_SDMMC 456 -#define HCLK_SDIO 457 -#define HCLK_EMMC 459 -#define HCLK_CPU 460 -#define HCLK_VPU_PRE 461 -#define HCLK_RKVDEC_PRE 462 -#define HCLK_VIO_PRE 463 -#define HCLK_VPU 464 -#define HCLK_RKVDEC 465 -#define HCLK_VIO 466 -#define HCLK_RGA 467 -#define HCLK_IEP 468 -#define HCLK_VIO_H2P 469 -#define HCLK_HDCP_MMU 470 -#define HCLK_HOST0 471 -#define HCLK_HOST1 472 -#define HCLK_HOST2 473 -#define HCLK_OTG 474 -#define HCLK_TSP 475 -#define HCLK_M_CRYPTO 476 -#define HCLK_S_CRYPTO 477 -#define HCLK_PERI 478 - -#define CLK_NR_CLKS (HCLK_PERI + 1) - -/* soft-reset indices */ -#define SRST_CORE0_PO 0 -#define SRST_CORE1_PO 1 -#define SRST_CORE2_PO 2 -#define SRST_CORE3_PO 3 -#define SRST_CORE0 4 -#define SRST_CORE1 5 -#define SRST_CORE2 6 -#define SRST_CORE3 7 -#define SRST_CORE0_DBG 8 -#define SRST_CORE1_DBG 9 -#define SRST_CORE2_DBG 10 -#define SRST_CORE3_DBG 11 -#define SRST_TOPDBG 12 -#define SRST_ACLK_CORE 13 -#define SRST_NOC 14 -#define SRST_L2C 15 - -#define SRST_CPUSYS_H 18 -#define SRST_BUSSYS_H 19 -#define SRST_SPDIF 20 -#define SRST_INTMEM 21 -#define SRST_ROM 22 -#define SRST_OTG_ADP 23 -#define SRST_I2S0 24 -#define SRST_I2S1 25 -#define SRST_I2S2 26 -#define SRST_ACODEC_P 27 -#define SRST_DFIMON 28 -#define SRST_MSCH 29 -#define SRST_EFUSE1024 30 -#define SRST_EFUSE256 31 - -#define SRST_GPIO0 32 -#define SRST_GPIO1 33 -#define SRST_GPIO2 34 -#define SRST_GPIO3 35 -#define SRST_PERIPH_NOC_A 36 -#define SRST_PERIPH_NOC_BUS_H 37 -#define SRST_PERIPH_NOC_P 38 -#define SRST_UART0 39 -#define SRST_UART1 40 -#define SRST_UART2 41 -#define SRST_PHYNOC 42 -#define SRST_I2C0 43 -#define SRST_I2C1 44 -#define SRST_I2C2 45 -#define SRST_I2C3 46 - -#define SRST_PWM 48 -#define SRST_A53_GIC 49 -#define SRST_DAP 51 -#define SRST_DAP_NOC 52 -#define SRST_CRYPTO 53 -#define SRST_SGRF 54 -#define SRST_GRF 55 -#define SRST_GMAC 56 -#define SRST_PERIPH_NOC_H 58 -#define SRST_MACPHY 63 - -#define SRST_DMA 64 -#define SRST_NANDC 68 -#define SRST_USBOTG 69 -#define SRST_OTGC 70 -#define SRST_USBHOST0 71 -#define SRST_HOST_CTRL0 72 -#define SRST_USBHOST1 73 -#define SRST_HOST_CTRL1 74 -#define SRST_USBHOST2 75 -#define SRST_HOST_CTRL2 76 -#define SRST_USBPOR0 77 -#define SRST_USBPOR1 78 -#define SRST_DDRMSCH 79 - -#define SRST_SMART_CARD 80 -#define SRST_SDMMC 81 -#define SRST_SDIO 82 -#define SRST_EMMC 83 -#define SRST_SPI 84 -#define SRST_TSP_H 85 -#define SRST_TSP 86 -#define SRST_TSADC 87 -#define SRST_DDRPHY 88 -#define SRST_DDRPHY_P 89 -#define SRST_DDRCTRL 90 -#define SRST_DDRCTRL_P 91 -#define SRST_HOST0_ECHI 92 -#define SRST_HOST1_ECHI 93 -#define SRST_HOST2_ECHI 94 -#define SRST_VOP_NOC_A 95 - -#define SRST_HDMI_P 96 -#define SRST_VIO_ARBI_H 97 -#define SRST_IEP_NOC_A 98 -#define SRST_VIO_NOC_H 99 -#define SRST_VOP_A 100 -#define SRST_VOP_H 101 -#define SRST_VOP_D 102 -#define SRST_UTMI0 103 -#define SRST_UTMI1 104 -#define SRST_UTMI2 105 -#define SRST_UTMI3 106 -#define SRST_RGA 107 -#define SRST_RGA_NOC_A 108 -#define SRST_RGA_A 109 -#define SRST_RGA_H 110 -#define SRST_HDCP_A 111 - -#define SRST_VPU_A 112 -#define SRST_VPU_H 113 -#define SRST_VPU_NOC_A 116 -#define SRST_VPU_NOC_H 117 -#define SRST_RKVDEC_A 118 -#define SRST_RKVDEC_NOC_A 119 -#define SRST_RKVDEC_H 120 -#define SRST_RKVDEC_NOC_H 121 -#define SRST_RKVDEC_CORE 122 -#define SRST_RKVDEC_CABAC 123 -#define SRST_IEP_A 124 -#define SRST_IEP_H 125 -#define SRST_GPU_A 126 -#define SRST_GPU_NOC_A 127 - -#define SRST_CORE_DBG 128 -#define SRST_DBG_P 129 -#define SRST_TIMER0 130 -#define SRST_TIMER1 131 -#define SRST_TIMER2 132 -#define SRST_TIMER3 133 -#define SRST_TIMER4 134 -#define SRST_TIMER5 135 -#define SRST_VIO_H2P 136 -#define SRST_HDMIPHY 139 -#define SRST_VDAC 140 -#define SRST_TIMER_6CH_P 141 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/rk3288-cru.h b/sys/gnu/dts/include/dt-bindings/clock/rk3288-cru.h deleted file mode 100644 index 33819acbfc5..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/rk3288-cru.h +++ /dev/null @@ -1,380 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright (c) 2014 MundoReader S.L. - * Author: Heiko Stuebner - */ - -#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3288_H -#define _DT_BINDINGS_CLK_ROCKCHIP_RK3288_H - -/* core clocks */ -#define PLL_APLL 1 -#define PLL_DPLL 2 -#define PLL_CPLL 3 -#define PLL_GPLL 4 -#define PLL_NPLL 5 -#define ARMCLK 6 - -/* sclk gates (special clocks) */ -#define SCLK_GPU 64 -#define SCLK_SPI0 65 -#define SCLK_SPI1 66 -#define SCLK_SPI2 67 -#define SCLK_SDMMC 68 -#define SCLK_SDIO0 69 -#define SCLK_SDIO1 70 -#define SCLK_EMMC 71 -#define SCLK_TSADC 72 -#define SCLK_SARADC 73 -#define SCLK_PS2C 74 -#define SCLK_NANDC0 75 -#define SCLK_NANDC1 76 -#define SCLK_UART0 77 -#define SCLK_UART1 78 -#define SCLK_UART2 79 -#define SCLK_UART3 80 -#define SCLK_UART4 81 -#define SCLK_I2S0 82 -#define SCLK_SPDIF 83 -#define SCLK_SPDIF8CH 84 -#define SCLK_TIMER0 85 -#define SCLK_TIMER1 86 -#define SCLK_TIMER2 87 -#define SCLK_TIMER3 88 -#define SCLK_TIMER4 89 -#define SCLK_TIMER5 90 -#define SCLK_TIMER6 91 -#define SCLK_HSADC 92 -#define SCLK_OTGPHY0 93 -#define SCLK_OTGPHY1 94 -#define SCLK_OTGPHY2 95 -#define SCLK_OTG_ADP 96 -#define SCLK_HSICPHY480M 97 -#define SCLK_HSICPHY12M 98 -#define SCLK_MACREF 99 -#define SCLK_LCDC_PWM0 100 -#define SCLK_LCDC_PWM1 101 -#define SCLK_MAC_RX 102 -#define SCLK_MAC_TX 103 -#define SCLK_EDP_24M 104 -#define SCLK_EDP 105 -#define SCLK_RGA 106 -#define SCLK_ISP 107 -#define SCLK_ISP_JPE 108 -#define SCLK_HDMI_HDCP 109 -#define SCLK_HDMI_CEC 110 -#define SCLK_HEVC_CABAC 111 -#define SCLK_HEVC_CORE 112 -#define SCLK_I2S0_OUT 113 -#define SCLK_SDMMC_DRV 114 -#define SCLK_SDIO0_DRV 115 -#define SCLK_SDIO1_DRV 116 -#define SCLK_EMMC_DRV 117 -#define SCLK_SDMMC_SAMPLE 118 -#define SCLK_SDIO0_SAMPLE 119 -#define SCLK_SDIO1_SAMPLE 120 -#define SCLK_EMMC_SAMPLE 121 -#define SCLK_USBPHY480M_SRC 122 -#define SCLK_PVTM_CORE 123 -#define SCLK_PVTM_GPU 124 -#define SCLK_CRYPTO 125 -#define SCLK_MIPIDSI_24M 126 -#define SCLK_VIP_OUT 127 - -#define SCLK_MAC 151 -#define SCLK_MACREF_OUT 152 - -#define DCLK_VOP0 190 -#define DCLK_VOP1 191 - -/* aclk gates */ -#define ACLK_GPU 192 -#define ACLK_DMAC1 193 -#define ACLK_DMAC2 194 -#define ACLK_MMU 195 -#define ACLK_GMAC 196 -#define ACLK_VOP0 197 -#define ACLK_VOP1 198 -#define ACLK_CRYPTO 199 -#define ACLK_RGA 200 -#define ACLK_RGA_NIU 201 -#define ACLK_IEP 202 -#define ACLK_VIO0_NIU 203 -#define ACLK_VIP 204 -#define ACLK_ISP 205 -#define ACLK_VIO1_NIU 206 -#define ACLK_HEVC 207 -#define ACLK_VCODEC 208 -#define ACLK_CPU 209 -#define ACLK_PERI 210 - -/* pclk gates */ -#define PCLK_GPIO0 320 -#define PCLK_GPIO1 321 -#define PCLK_GPIO2 322 -#define PCLK_GPIO3 323 -#define PCLK_GPIO4 324 -#define PCLK_GPIO5 325 -#define PCLK_GPIO6 326 -#define PCLK_GPIO7 327 -#define PCLK_GPIO8 328 -#define PCLK_GRF 329 -#define PCLK_SGRF 330 -#define PCLK_PMU 331 -#define PCLK_I2C0 332 -#define PCLK_I2C1 333 -#define PCLK_I2C2 334 -#define PCLK_I2C3 335 -#define PCLK_I2C4 336 -#define PCLK_I2C5 337 -#define PCLK_SPI0 338 -#define PCLK_SPI1 339 -#define PCLK_SPI2 340 -#define PCLK_UART0 341 -#define PCLK_UART1 342 -#define PCLK_UART2 343 -#define PCLK_UART3 344 -#define PCLK_UART4 345 -#define PCLK_TSADC 346 -#define PCLK_SARADC 347 -#define PCLK_SIM 348 -#define PCLK_GMAC 349 -#define PCLK_PWM 350 -#define PCLK_RKPWM 351 -#define PCLK_PS2C 352 -#define PCLK_TIMER 353 -#define PCLK_TZPC 354 -#define PCLK_EDP_CTRL 355 -#define PCLK_MIPI_DSI0 356 -#define PCLK_MIPI_DSI1 357 -#define PCLK_MIPI_CSI 358 -#define PCLK_LVDS_PHY 359 -#define PCLK_HDMI_CTRL 360 -#define PCLK_VIO2_H2P 361 -#define PCLK_CPU 362 -#define PCLK_PERI 363 -#define PCLK_DDRUPCTL0 364 -#define PCLK_PUBL0 365 -#define PCLK_DDRUPCTL1 366 -#define PCLK_PUBL1 367 -#define PCLK_WDT 368 -#define PCLK_EFUSE256 369 -#define PCLK_EFUSE1024 370 -#define PCLK_ISP_IN 371 - -/* hclk gates */ -#define HCLK_GPS 448 -#define HCLK_OTG0 449 -#define HCLK_USBHOST0 450 -#define HCLK_USBHOST1 451 -#define HCLK_HSIC 452 -#define HCLK_NANDC0 453 -#define HCLK_NANDC1 454 -#define HCLK_TSP 455 -#define HCLK_SDMMC 456 -#define HCLK_SDIO0 457 -#define HCLK_SDIO1 458 -#define HCLK_EMMC 459 -#define HCLK_HSADC 460 -#define HCLK_CRYPTO 461 -#define HCLK_I2S0 462 -#define HCLK_SPDIF 463 -#define HCLK_SPDIF8CH 464 -#define HCLK_VOP0 465 -#define HCLK_VOP1 466 -#define HCLK_ROM 467 -#define HCLK_IEP 468 -#define HCLK_ISP 469 -#define HCLK_RGA 470 -#define HCLK_VIO_AHB_ARBI 471 -#define HCLK_VIO_NIU 472 -#define HCLK_VIP 473 -#define HCLK_VIO2_H2P 474 -#define HCLK_HEVC 475 -#define HCLK_VCODEC 476 -#define HCLK_CPU 477 -#define HCLK_PERI 478 - -#define CLK_NR_CLKS (HCLK_PERI + 1) - -/* soft-reset indices */ -#define SRST_CORE0 0 -#define SRST_CORE1 1 -#define SRST_CORE2 2 -#define SRST_CORE3 3 -#define SRST_CORE0_PO 4 -#define SRST_CORE1_PO 5 -#define SRST_CORE2_PO 6 -#define SRST_CORE3_PO 7 -#define SRST_PDCORE_STRSYS 8 -#define SRST_PDBUS_STRSYS 9 -#define SRST_L2C 10 -#define SRST_TOPDBG 11 -#define SRST_CORE0_DBG 12 -#define SRST_CORE1_DBG 13 -#define SRST_CORE2_DBG 14 -#define SRST_CORE3_DBG 15 - -#define SRST_PDBUG_AHB_ARBITOR 16 -#define SRST_EFUSE256 17 -#define SRST_DMAC1 18 -#define SRST_INTMEM 19 -#define SRST_ROM 20 -#define SRST_SPDIF8CH 21 -#define SRST_TIMER 22 -#define SRST_I2S0 23 -#define SRST_SPDIF 24 -#define SRST_TIMER0 25 -#define SRST_TIMER1 26 -#define SRST_TIMER2 27 -#define SRST_TIMER3 28 -#define SRST_TIMER4 29 -#define SRST_TIMER5 30 -#define SRST_EFUSE 31 - -#define SRST_GPIO0 32 -#define SRST_GPIO1 33 -#define SRST_GPIO2 34 -#define SRST_GPIO3 35 -#define SRST_GPIO4 36 -#define SRST_GPIO5 37 -#define SRST_GPIO6 38 -#define SRST_GPIO7 39 -#define SRST_GPIO8 40 -#define SRST_I2C0 42 -#define SRST_I2C1 43 -#define SRST_I2C2 44 -#define SRST_I2C3 45 -#define SRST_I2C4 46 -#define SRST_I2C5 47 - -#define SRST_DWPWM 48 -#define SRST_MMC_PERI 49 -#define SRST_PERIPH_MMU 50 -#define SRST_DAP 51 -#define SRST_DAP_SYS 52 -#define SRST_TPIU 53 -#define SRST_PMU_APB 54 -#define SRST_GRF 55 -#define SRST_PMU 56 -#define SRST_PERIPH_AXI 57 -#define SRST_PERIPH_AHB 58 -#define SRST_PERIPH_APB 59 -#define SRST_PERIPH_NIU 60 -#define SRST_PDPERI_AHB_ARBI 61 -#define SRST_EMEM 62 -#define SRST_USB_PERI 63 - -#define SRST_DMAC2 64 -#define SRST_MAC 66 -#define SRST_GPS 67 -#define SRST_RKPWM 69 -#define SRST_CCP 71 -#define SRST_USBHOST0 72 -#define SRST_HSIC 73 -#define SRST_HSIC_AUX 74 -#define SRST_HSIC_PHY 75 -#define SRST_HSADC 76 -#define SRST_NANDC0 77 -#define SRST_NANDC1 78 - -#define SRST_TZPC 80 -#define SRST_SPI0 83 -#define SRST_SPI1 84 -#define SRST_SPI2 85 -#define SRST_SARADC 87 -#define SRST_PDALIVE_NIU 88 -#define SRST_PDPMU_INTMEM 89 -#define SRST_PDPMU_NIU 90 -#define SRST_SGRF 91 - -#define SRST_VIO_ARBI 96 -#define SRST_RGA_NIU 97 -#define SRST_VIO0_NIU_AXI 98 -#define SRST_VIO_NIU_AHB 99 -#define SRST_LCDC0_AXI 100 -#define SRST_LCDC0_AHB 101 -#define SRST_LCDC0_DCLK 102 -#define SRST_VIO1_NIU_AXI 103 -#define SRST_VIP 104 -#define SRST_RGA_CORE 105 -#define SRST_IEP_AXI 106 -#define SRST_IEP_AHB 107 -#define SRST_RGA_AXI 108 -#define SRST_RGA_AHB 109 -#define SRST_ISP 110 -#define SRST_EDP 111 - -#define SRST_VCODEC_AXI 112 -#define SRST_VCODEC_AHB 113 -#define SRST_VIO_H2P 114 -#define SRST_MIPIDSI0 115 -#define SRST_MIPIDSI1 116 -#define SRST_MIPICSI 117 -#define SRST_LVDS_PHY 118 -#define SRST_LVDS_CON 119 -#define SRST_GPU 120 -#define SRST_HDMI 121 -#define SRST_CORE_PVTM 124 -#define SRST_GPU_PVTM 125 - -#define SRST_MMC0 128 -#define SRST_SDIO0 129 -#define SRST_SDIO1 130 -#define SRST_EMMC 131 -#define SRST_USBOTG_AHB 132 -#define SRST_USBOTG_PHY 133 -#define SRST_USBOTG_CON 134 -#define SRST_USBHOST0_AHB 135 -#define SRST_USBHOST0_PHY 136 -#define SRST_USBHOST0_CON 137 -#define SRST_USBHOST1_AHB 138 -#define SRST_USBHOST1_PHY 139 -#define SRST_USBHOST1_CON 140 -#define SRST_USB_ADP 141 -#define SRST_ACC_EFUSE 142 - -#define SRST_CORESIGHT 144 -#define SRST_PD_CORE_AHB_NOC 145 -#define SRST_PD_CORE_APB_NOC 146 -#define SRST_PD_CORE_MP_AXI 147 -#define SRST_GIC 148 -#define SRST_LCDC_PWM0 149 -#define SRST_LCDC_PWM1 150 -#define SRST_VIO0_H2P_BRG 151 -#define SRST_VIO1_H2P_BRG 152 -#define SRST_RGA_H2P_BRG 153 -#define SRST_HEVC 154 -#define SRST_TSADC 159 - -#define SRST_DDRPHY0 160 -#define SRST_DDRPHY0_APB 161 -#define SRST_DDRCTRL0 162 -#define SRST_DDRCTRL0_APB 163 -#define SRST_DDRPHY0_CTRL 164 -#define SRST_DDRPHY1 165 -#define SRST_DDRPHY1_APB 166 -#define SRST_DDRCTRL1 167 -#define SRST_DDRCTRL1_APB 168 -#define SRST_DDRPHY1_CTRL 169 -#define SRST_DDRMSCH0 170 -#define SRST_DDRMSCH1 171 -#define SRST_CRYPTO 174 -#define SRST_C2C_HOST 175 - -#define SRST_LCDC1_AXI 176 -#define SRST_LCDC1_AHB 177 -#define SRST_LCDC1_DCLK 178 -#define SRST_UART0 179 -#define SRST_UART1 180 -#define SRST_UART2 181 -#define SRST_UART3 182 -#define SRST_UART4 183 -#define SRST_SIMC 186 -#define SRST_PS2C 187 -#define SRST_TSP 188 -#define SRST_TSP_CLKIN0 189 -#define SRST_TSP_CLKIN1 190 -#define SRST_TSP_27M 191 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/rk3308-cru.h b/sys/gnu/dts/include/dt-bindings/clock/rk3308-cru.h deleted file mode 100644 index d97840f9ee2..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/rk3308-cru.h +++ /dev/null @@ -1,387 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2019 Rockchip Electronics Co. Ltd. - * Author: Finley Xiao - */ - -#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3308_H -#define _DT_BINDINGS_CLK_ROCKCHIP_RK3308_H - -/* core clocks */ -#define PLL_APLL 1 -#define PLL_DPLL 2 -#define PLL_VPLL0 3 -#define PLL_VPLL1 4 -#define ARMCLK 5 - -/* sclk (special clocks) */ -#define USB480M 14 -#define SCLK_RTC32K 15 -#define SCLK_PVTM_CORE 16 -#define SCLK_UART0 17 -#define SCLK_UART1 18 -#define SCLK_UART2 19 -#define SCLK_UART3 20 -#define SCLK_UART4 21 -#define SCLK_I2C0 22 -#define SCLK_I2C1 23 -#define SCLK_I2C2 24 -#define SCLK_I2C3 25 -#define SCLK_PWM0 26 -#define SCLK_SPI0 27 -#define SCLK_SPI1 28 -#define SCLK_SPI2 29 -#define SCLK_TIMER0 30 -#define SCLK_TIMER1 31 -#define SCLK_TIMER2 32 -#define SCLK_TIMER3 33 -#define SCLK_TIMER4 34 -#define SCLK_TIMER5 35 -#define SCLK_TSADC 36 -#define SCLK_SARADC 37 -#define SCLK_OTP 38 -#define SCLK_OTP_USR 39 -#define SCLK_CPU_BOOST 40 -#define SCLK_CRYPTO 41 -#define SCLK_CRYPTO_APK 42 -#define SCLK_NANDC_DIV 43 -#define SCLK_NANDC_DIV50 44 -#define SCLK_NANDC 45 -#define SCLK_SDMMC_DIV 46 -#define SCLK_SDMMC_DIV50 47 -#define SCLK_SDMMC 48 -#define SCLK_SDMMC_DRV 49 -#define SCLK_SDMMC_SAMPLE 50 -#define SCLK_SDIO_DIV 51 -#define SCLK_SDIO_DIV50 52 -#define SCLK_SDIO 53 -#define SCLK_SDIO_DRV 54 -#define SCLK_SDIO_SAMPLE 55 -#define SCLK_EMMC_DIV 56 -#define SCLK_EMMC_DIV50 57 -#define SCLK_EMMC 58 -#define SCLK_EMMC_DRV 59 -#define SCLK_EMMC_SAMPLE 60 -#define SCLK_SFC 61 -#define SCLK_OTG_ADP 62 -#define SCLK_MAC_SRC 63 -#define SCLK_MAC 64 -#define SCLK_MAC_REF 65 -#define SCLK_MAC_RX_TX 66 -#define SCLK_MAC_RMII 67 -#define SCLK_DDR_MON_TIMER 68 -#define SCLK_DDR_MON 69 -#define SCLK_DDRCLK 70 -#define SCLK_PMU 71 -#define SCLK_USBPHY_REF 72 -#define SCLK_WIFI 73 -#define SCLK_PVTM_PMU 74 -#define SCLK_PDM 75 -#define SCLK_I2S0_8CH_TX 76 -#define SCLK_I2S0_8CH_TX_OUT 77 -#define SCLK_I2S0_8CH_RX 78 -#define SCLK_I2S0_8CH_RX_OUT 79 -#define SCLK_I2S1_8CH_TX 80 -#define SCLK_I2S1_8CH_TX_OUT 81 -#define SCLK_I2S1_8CH_RX 82 -#define SCLK_I2S1_8CH_RX_OUT 83 -#define SCLK_I2S2_8CH_TX 84 -#define SCLK_I2S2_8CH_TX_OUT 85 -#define SCLK_I2S2_8CH_RX 86 -#define SCLK_I2S2_8CH_RX_OUT 87 -#define SCLK_I2S3_8CH_TX 88 -#define SCLK_I2S3_8CH_TX_OUT 89 -#define SCLK_I2S3_8CH_RX 90 -#define SCLK_I2S3_8CH_RX_OUT 91 -#define SCLK_I2S0_2CH 92 -#define SCLK_I2S0_2CH_OUT 93 -#define SCLK_I2S1_2CH 94 -#define SCLK_I2S1_2CH_OUT 95 -#define SCLK_SPDIF_TX_DIV 96 -#define SCLK_SPDIF_TX_DIV50 97 -#define SCLK_SPDIF_TX 98 -#define SCLK_SPDIF_RX_DIV 99 -#define SCLK_SPDIF_RX_DIV50 100 -#define SCLK_SPDIF_RX 101 -#define SCLK_I2S0_8CH_TX_MUX 102 -#define SCLK_I2S0_8CH_RX_MUX 103 -#define SCLK_I2S1_8CH_TX_MUX 104 -#define SCLK_I2S1_8CH_RX_MUX 105 -#define SCLK_I2S2_8CH_TX_MUX 106 -#define SCLK_I2S2_8CH_RX_MUX 107 -#define SCLK_I2S3_8CH_TX_MUX 108 -#define SCLK_I2S3_8CH_RX_MUX 109 -#define SCLK_I2S0_8CH_TX_SRC 110 -#define SCLK_I2S0_8CH_RX_SRC 111 -#define SCLK_I2S1_8CH_TX_SRC 112 -#define SCLK_I2S1_8CH_RX_SRC 113 -#define SCLK_I2S2_8CH_TX_SRC 114 -#define SCLK_I2S2_8CH_RX_SRC 115 -#define SCLK_I2S3_8CH_TX_SRC 116 -#define SCLK_I2S3_8CH_RX_SRC 117 -#define SCLK_I2S0_2CH_SRC 118 -#define SCLK_I2S1_2CH_SRC 119 -#define SCLK_PWM1 120 -#define SCLK_PWM2 121 -#define SCLK_OWIRE 122 - -/* dclk */ -#define DCLK_VOP 125 - -/* aclk */ -#define ACLK_BUS_SRC 130 -#define ACLK_BUS 131 -#define ACLK_PERI_SRC 132 -#define ACLK_PERI 133 -#define ACLK_MAC 134 -#define ACLK_CRYPTO 135 -#define ACLK_VOP 136 -#define ACLK_GIC 137 -#define ACLK_DMAC0 138 -#define ACLK_DMAC1 139 - -/* hclk */ -#define HCLK_BUS 150 -#define HCLK_PERI 151 -#define HCLK_AUDIO 152 -#define HCLK_NANDC 153 -#define HCLK_SDMMC 154 -#define HCLK_SDIO 155 -#define HCLK_EMMC 156 -#define HCLK_SFC 157 -#define HCLK_OTG 158 -#define HCLK_HOST 159 -#define HCLK_HOST_ARB 160 -#define HCLK_PDM 161 -#define HCLK_SPDIFTX 162 -#define HCLK_SPDIFRX 163 -#define HCLK_I2S0_8CH 164 -#define HCLK_I2S1_8CH 165 -#define HCLK_I2S2_8CH 166 -#define HCLK_I2S3_8CH 167 -#define HCLK_I2S0_2CH 168 -#define HCLK_I2S1_2CH 169 -#define HCLK_VAD 170 -#define HCLK_CRYPTO 171 -#define HCLK_VOP 172 - -/* pclk */ -#define PCLK_BUS 190 -#define PCLK_DDR 191 -#define PCLK_PERI 192 -#define PCLK_PMU 193 -#define PCLK_AUDIO 194 -#define PCLK_MAC 195 -#define PCLK_ACODEC 196 -#define PCLK_UART0 197 -#define PCLK_UART1 198 -#define PCLK_UART2 199 -#define PCLK_UART3 200 -#define PCLK_UART4 201 -#define PCLK_I2C0 202 -#define PCLK_I2C1 203 -#define PCLK_I2C2 204 -#define PCLK_I2C3 205 -#define PCLK_PWM0 206 -#define PCLK_SPI0 207 -#define PCLK_SPI1 208 -#define PCLK_SPI2 209 -#define PCLK_SARADC 210 -#define PCLK_TSADC 211 -#define PCLK_TIMER 212 -#define PCLK_OTP_NS 213 -#define PCLK_WDT 214 -#define PCLK_GPIO0 215 -#define PCLK_GPIO1 216 -#define PCLK_GPIO2 217 -#define PCLK_GPIO3 218 -#define PCLK_GPIO4 219 -#define PCLK_SGRF 220 -#define PCLK_GRF 221 -#define PCLK_USBSD_DET 222 -#define PCLK_DDR_UPCTL 223 -#define PCLK_DDR_MON 224 -#define PCLK_DDRPHY 225 -#define PCLK_DDR_STDBY 226 -#define PCLK_USB_GRF 227 -#define PCLK_CRU 228 -#define PCLK_OTP_PHY 229 -#define PCLK_CPU_BOOST 230 -#define PCLK_PWM1 231 -#define PCLK_PWM2 232 -#define PCLK_CAN 233 -#define PCLK_OWIRE 234 - -#define CLK_NR_CLKS (PCLK_OWIRE + 1) - -/* soft-reset indices */ - -/* cru_softrst_con0 */ -#define SRST_CORE0_PO 0 -#define SRST_CORE1_PO 1 -#define SRST_CORE2_PO 2 -#define SRST_CORE3_PO 3 -#define SRST_CORE0 4 -#define SRST_CORE1 5 -#define SRST_CORE2 6 -#define SRST_CORE3 7 -#define SRST_CORE0_DBG 8 -#define SRST_CORE1_DBG 9 -#define SRST_CORE2_DBG 10 -#define SRST_CORE3_DBG 11 -#define SRST_TOPDBG 12 -#define SRST_CORE_NOC 13 -#define SRST_STRC_A 14 -#define SRST_L2C 15 - -/* cru_softrst_con1 */ -#define SRST_DAP 16 -#define SRST_CORE_PVTM 17 -#define SRST_CORE_PRF 18 -#define SRST_CORE_GRF 19 -#define SRST_DDRUPCTL 20 -#define SRST_DDRUPCTL_P 22 -#define SRST_MSCH 23 -#define SRST_DDRMON_P 25 -#define SRST_DDRSTDBY_P 26 -#define SRST_DDRSTDBY 27 -#define SRST_DDRPHY 28 -#define SRST_DDRPHY_DIV 29 -#define SRST_DDRPHY_P 30 - -/* cru_softrst_con2 */ -#define SRST_BUS_NIU_H 32 -#define SRST_USB_NIU_P 33 -#define SRST_CRYPTO_A 34 -#define SRST_CRYPTO_H 35 -#define SRST_CRYPTO 36 -#define SRST_CRYPTO_APK 37 -#define SRST_VOP_A 38 -#define SRST_VOP_H 39 -#define SRST_VOP_D 40 -#define SRST_INTMEM_A 41 -#define SRST_ROM_H 42 -#define SRST_GIC_A 43 -#define SRST_UART0_P 44 -#define SRST_UART0 45 -#define SRST_UART1_P 46 -#define SRST_UART1 47 - -/* cru_softrst_con3 */ -#define SRST_UART2_P 48 -#define SRST_UART2 49 -#define SRST_UART3_P 50 -#define SRST_UART3 51 -#define SRST_UART4_P 52 -#define SRST_UART4 53 -#define SRST_I2C0_P 54 -#define SRST_I2C0 55 -#define SRST_I2C1_P 56 -#define SRST_I2C1 57 -#define SRST_I2C2_P 58 -#define SRST_I2C2 59 -#define SRST_I2C3_P 60 -#define SRST_I2C3 61 -#define SRST_PWM0_P 62 -#define SRST_PWM0 63 - -/* cru_softrst_con4 */ -#define SRST_SPI0_P 64 -#define SRST_SPI0 65 -#define SRST_SPI1_P 66 -#define SRST_SPI1 67 -#define SRST_SPI2_P 68 -#define SRST_SPI2 69 -#define SRST_SARADC_P 70 -#define SRST_TSADC_P 71 -#define SRST_TSADC 72 -#define SRST_TIMER0_P 73 -#define SRST_TIMER0 74 -#define SRST_TIMER1 75 -#define SRST_TIMER2 76 -#define SRST_TIMER3 77 -#define SRST_TIMER4 78 -#define SRST_TIMER5 79 - -/* cru_softrst_con5 */ -#define SRST_OTP_NS_P 80 -#define SRST_OTP_NS_SBPI 81 -#define SRST_OTP_NS_USR 82 -#define SRST_OTP_PHY_P 83 -#define SRST_OTP_PHY 84 -#define SRST_GPIO0_P 86 -#define SRST_GPIO1_P 87 -#define SRST_GPIO2_P 88 -#define SRST_GPIO3_P 89 -#define SRST_GPIO4_P 90 -#define SRST_GRF_P 91 -#define SRST_USBSD_DET_P 92 -#define SRST_PMU 93 -#define SRST_PMU_PVTM 94 -#define SRST_USB_GRF_P 95 - -/* cru_softrst_con6 */ -#define SRST_CPU_BOOST 96 -#define SRST_CPU_BOOST_P 97 -#define SRST_PWM1_P 98 -#define SRST_PWM1 99 -#define SRST_PWM2_P 100 -#define SRST_PWM2 101 -#define SRST_PERI_NIU_A 104 -#define SRST_PERI_NIU_H 105 -#define SRST_PERI_NIU_p 106 -#define SRST_USB2OTG_H 107 -#define SRST_USB2OTG 108 -#define SRST_USB2OTG_ADP 109 -#define SRST_USB2HOST_H 110 -#define SRST_USB2HOST_ARB_H 111 - -/* cru_softrst_con7 */ -#define SRST_USB2HOST_AUX_H 112 -#define SRST_USB2HOST_EHCI 113 -#define SRST_USB2HOST 114 -#define SRST_USBPHYPOR 115 -#define SRST_UTMI0 116 -#define SRST_UTMI1 117 -#define SRST_SDIO_H 118 -#define SRST_EMMC_H 119 -#define SRST_SFC_H 120 -#define SRST_SFC 121 -#define SRST_SD_H 122 -#define SRST_NANDC_H 123 -#define SRST_NANDC_N 124 -#define SRST_MAC_A 125 -#define SRST_CAN_P 126 -#define SRST_OWIRE_P 127 - -/* cru_softrst_con8 */ -#define SRST_AUDIO_NIU_H 128 -#define SRST_AUDIO_NIU_P 129 -#define SRST_PDM_H 130 -#define SRST_PDM_M 131 -#define SRST_SPDIFTX_H 132 -#define SRST_SPDIFTX_M 133 -#define SRST_SPDIFRX_H 134 -#define SRST_SPDIFRX_M 135 -#define SRST_I2S0_8CH_H 136 -#define SRST_I2S0_8CH_TX_M 137 -#define SRST_I2S0_8CH_RX_M 138 -#define SRST_I2S1_8CH_H 139 -#define SRST_I2S1_8CH_TX_M 140 -#define SRST_I2S1_8CH_RX_M 141 -#define SRST_I2S2_8CH_H 142 -#define SRST_I2S2_8CH_TX_M 143 - -/* cru_softrst_con9 */ -#define SRST_I2S2_8CH_RX_M 144 -#define SRST_I2S3_8CH_H 145 -#define SRST_I2S3_8CH_TX_M 146 -#define SRST_I2S3_8CH_RX_M 147 -#define SRST_I2S0_2CH_H 148 -#define SRST_I2S0_2CH_M 149 -#define SRST_I2S1_2CH_H 150 -#define SRST_I2S1_2CH_M 151 -#define SRST_VAD_H 152 -#define SRST_ACODEC_P 153 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/rk3328-cru.h b/sys/gnu/dts/include/dt-bindings/clock/rk3328-cru.h deleted file mode 100644 index 555b4ff660a..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/rk3328-cru.h +++ /dev/null @@ -1,393 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright (c) 2016 Rockchip Electronics Co. Ltd. - * Author: Elaine - */ - -#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3328_H -#define _DT_BINDINGS_CLK_ROCKCHIP_RK3328_H - -/* core clocks */ -#define PLL_APLL 1 -#define PLL_DPLL 2 -#define PLL_CPLL 3 -#define PLL_GPLL 4 -#define PLL_NPLL 5 -#define ARMCLK 6 - -/* sclk gates (special clocks) */ -#define SCLK_RTC32K 30 -#define SCLK_SDMMC_EXT 31 -#define SCLK_SPI 32 -#define SCLK_SDMMC 33 -#define SCLK_SDIO 34 -#define SCLK_EMMC 35 -#define SCLK_TSADC 36 -#define SCLK_SARADC 37 -#define SCLK_UART0 38 -#define SCLK_UART1 39 -#define SCLK_UART2 40 -#define SCLK_I2S0 41 -#define SCLK_I2S1 42 -#define SCLK_I2S2 43 -#define SCLK_I2S1_OUT 44 -#define SCLK_I2S2_OUT 45 -#define SCLK_SPDIF 46 -#define SCLK_TIMER0 47 -#define SCLK_TIMER1 48 -#define SCLK_TIMER2 49 -#define SCLK_TIMER3 50 -#define SCLK_TIMER4 51 -#define SCLK_TIMER5 52 -#define SCLK_WIFI 53 -#define SCLK_CIF_OUT 54 -#define SCLK_I2C0 55 -#define SCLK_I2C1 56 -#define SCLK_I2C2 57 -#define SCLK_I2C3 58 -#define SCLK_CRYPTO 59 -#define SCLK_PWM 60 -#define SCLK_PDM 61 -#define SCLK_EFUSE 62 -#define SCLK_OTP 63 -#define SCLK_DDRCLK 64 -#define SCLK_VDEC_CABAC 65 -#define SCLK_VDEC_CORE 66 -#define SCLK_VENC_DSP 67 -#define SCLK_VENC_CORE 68 -#define SCLK_RGA 69 -#define SCLK_HDMI_SFC 70 -#define SCLK_HDMI_CEC 71 -#define SCLK_USB3_REF 72 -#define SCLK_USB3_SUSPEND 73 -#define SCLK_SDMMC_DRV 74 -#define SCLK_SDIO_DRV 75 -#define SCLK_EMMC_DRV 76 -#define SCLK_SDMMC_EXT_DRV 77 -#define SCLK_SDMMC_SAMPLE 78 -#define SCLK_SDIO_SAMPLE 79 -#define SCLK_EMMC_SAMPLE 80 -#define SCLK_SDMMC_EXT_SAMPLE 81 -#define SCLK_VOP 82 -#define SCLK_MAC2PHY_RXTX 83 -#define SCLK_MAC2PHY_SRC 84 -#define SCLK_MAC2PHY_REF 85 -#define SCLK_MAC2PHY_OUT 86 -#define SCLK_MAC2IO_RX 87 -#define SCLK_MAC2IO_TX 88 -#define SCLK_MAC2IO_REFOUT 89 -#define SCLK_MAC2IO_REF 90 -#define SCLK_MAC2IO_OUT 91 -#define SCLK_TSP 92 -#define SCLK_HSADC_TSP 93 -#define SCLK_USB3PHY_REF 94 -#define SCLK_REF_USB3OTG 95 -#define SCLK_USB3OTG_REF 96 -#define SCLK_USB3OTG_SUSPEND 97 -#define SCLK_REF_USB3OTG_SRC 98 -#define SCLK_MAC2IO_SRC 99 -#define SCLK_MAC2IO 100 -#define SCLK_MAC2PHY 101 -#define SCLK_MAC2IO_EXT 102 - -/* dclk gates */ -#define DCLK_LCDC 120 -#define DCLK_HDMIPHY 121 -#define HDMIPHY 122 -#define USB480M 123 -#define DCLK_LCDC_SRC 124 - -/* aclk gates */ -#define ACLK_AXISRAM 130 -#define ACLK_VOP_PRE 131 -#define ACLK_USB3OTG 132 -#define ACLK_RGA_PRE 133 -#define ACLK_DMAC 134 -#define ACLK_GPU 135 -#define ACLK_BUS_PRE 136 -#define ACLK_PERI_PRE 137 -#define ACLK_RKVDEC_PRE 138 -#define ACLK_RKVDEC 139 -#define ACLK_RKVENC 140 -#define ACLK_VPU_PRE 141 -#define ACLK_VIO_PRE 142 -#define ACLK_VPU 143 -#define ACLK_VIO 144 -#define ACLK_VOP 145 -#define ACLK_GMAC 146 -#define ACLK_H265 147 -#define ACLK_H264 148 -#define ACLK_MAC2PHY 149 -#define ACLK_MAC2IO 150 -#define ACLK_DCF 151 -#define ACLK_TSP 152 -#define ACLK_PERI 153 -#define ACLK_RGA 154 -#define ACLK_IEP 155 -#define ACLK_CIF 156 -#define ACLK_HDCP 157 - -/* pclk gates */ -#define PCLK_GPIO0 200 -#define PCLK_GPIO1 201 -#define PCLK_GPIO2 202 -#define PCLK_GPIO3 203 -#define PCLK_GRF 204 -#define PCLK_I2C0 205 -#define PCLK_I2C1 206 -#define PCLK_I2C2 207 -#define PCLK_I2C3 208 -#define PCLK_SPI 209 -#define PCLK_UART0 210 -#define PCLK_UART1 211 -#define PCLK_UART2 212 -#define PCLK_TSADC 213 -#define PCLK_PWM 214 -#define PCLK_TIMER 215 -#define PCLK_BUS_PRE 216 -#define PCLK_PERI_PRE 217 -#define PCLK_HDMI_CTRL 218 -#define PCLK_HDMI_PHY 219 -#define PCLK_GMAC 220 -#define PCLK_H265 221 -#define PCLK_MAC2PHY 222 -#define PCLK_MAC2IO 223 -#define PCLK_USB3PHY_OTG 224 -#define PCLK_USB3PHY_PIPE 225 -#define PCLK_USB3_GRF 226 -#define PCLK_USB2_GRF 227 -#define PCLK_HDMIPHY 228 -#define PCLK_DDR 229 -#define PCLK_PERI 230 -#define PCLK_HDMI 231 -#define PCLK_HDCP 232 -#define PCLK_DCF 233 -#define PCLK_SARADC 234 -#define PCLK_ACODECPHY 235 -#define PCLK_WDT 236 - -/* hclk gates */ -#define HCLK_PERI 308 -#define HCLK_TSP 309 -#define HCLK_GMAC 310 -#define HCLK_I2S0_8CH 311 -#define HCLK_I2S1_8CH 312 -#define HCLK_I2S2_2CH 313 -#define HCLK_SPDIF_8CH 314 -#define HCLK_VOP 315 -#define HCLK_NANDC 316 -#define HCLK_SDMMC 317 -#define HCLK_SDIO 318 -#define HCLK_EMMC 319 -#define HCLK_SDMMC_EXT 320 -#define HCLK_RKVDEC_PRE 321 -#define HCLK_RKVDEC 322 -#define HCLK_RKVENC 323 -#define HCLK_VPU_PRE 324 -#define HCLK_VIO_PRE 325 -#define HCLK_VPU 326 -#define HCLK_BUS_PRE 328 -#define HCLK_PERI_PRE 329 -#define HCLK_H264 330 -#define HCLK_CIF 331 -#define HCLK_OTG_PMU 332 -#define HCLK_OTG 333 -#define HCLK_HOST0 334 -#define HCLK_HOST0_ARB 335 -#define HCLK_CRYPTO_MST 336 -#define HCLK_CRYPTO_SLV 337 -#define HCLK_PDM 338 -#define HCLK_IEP 339 -#define HCLK_RGA 340 -#define HCLK_HDCP 341 - -#define CLK_NR_CLKS (HCLK_HDCP + 1) - -/* soft-reset indices */ -#define SRST_CORE0_PO 0 -#define SRST_CORE1_PO 1 -#define SRST_CORE2_PO 2 -#define SRST_CORE3_PO 3 -#define SRST_CORE0 4 -#define SRST_CORE1 5 -#define SRST_CORE2 6 -#define SRST_CORE3 7 -#define SRST_CORE0_DBG 8 -#define SRST_CORE1_DBG 9 -#define SRST_CORE2_DBG 10 -#define SRST_CORE3_DBG 11 -#define SRST_TOPDBG 12 -#define SRST_CORE_NIU 13 -#define SRST_STRC_A 14 -#define SRST_L2C 15 - -#define SRST_A53_GIC 18 -#define SRST_DAP 19 -#define SRST_PMU_P 21 -#define SRST_EFUSE 22 -#define SRST_BUSSYS_H 23 -#define SRST_BUSSYS_P 24 -#define SRST_SPDIF 25 -#define SRST_INTMEM 26 -#define SRST_ROM 27 -#define SRST_GPIO0 28 -#define SRST_GPIO1 29 -#define SRST_GPIO2 30 -#define SRST_GPIO3 31 - -#define SRST_I2S0 32 -#define SRST_I2S1 33 -#define SRST_I2S2 34 -#define SRST_I2S0_H 35 -#define SRST_I2S1_H 36 -#define SRST_I2S2_H 37 -#define SRST_UART0 38 -#define SRST_UART1 39 -#define SRST_UART2 40 -#define SRST_UART0_P 41 -#define SRST_UART1_P 42 -#define SRST_UART2_P 43 -#define SRST_I2C0 44 -#define SRST_I2C1 45 -#define SRST_I2C2 46 -#define SRST_I2C3 47 - -#define SRST_I2C0_P 48 -#define SRST_I2C1_P 49 -#define SRST_I2C2_P 50 -#define SRST_I2C3_P 51 -#define SRST_EFUSE_SE_P 52 -#define SRST_EFUSE_NS_P 53 -#define SRST_PWM0 54 -#define SRST_PWM0_P 55 -#define SRST_DMA 56 -#define SRST_TSP_A 57 -#define SRST_TSP_H 58 -#define SRST_TSP 59 -#define SRST_TSP_HSADC 60 -#define SRST_DCF_A 61 -#define SRST_DCF_P 62 - -#define SRST_SCR 64 -#define SRST_SPI 65 -#define SRST_TSADC 66 -#define SRST_TSADC_P 67 -#define SRST_CRYPTO 68 -#define SRST_SGRF 69 -#define SRST_GRF 70 -#define SRST_USB_GRF 71 -#define SRST_TIMER_6CH_P 72 -#define SRST_TIMER0 73 -#define SRST_TIMER1 74 -#define SRST_TIMER2 75 -#define SRST_TIMER3 76 -#define SRST_TIMER4 77 -#define SRST_TIMER5 78 -#define SRST_USB3GRF 79 - -#define SRST_PHYNIU 80 -#define SRST_HDMIPHY 81 -#define SRST_VDAC 82 -#define SRST_ACODEC_p 83 -#define SRST_SARADC 85 -#define SRST_SARADC_P 86 -#define SRST_GRF_DDR 87 -#define SRST_DFIMON 88 -#define SRST_MSCH 89 -#define SRST_DDRMSCH 91 -#define SRST_DDRCTRL 92 -#define SRST_DDRCTRL_P 93 -#define SRST_DDRPHY 94 -#define SRST_DDRPHY_P 95 - -#define SRST_GMAC_NIU_A 96 -#define SRST_GMAC_NIU_P 97 -#define SRST_GMAC2PHY_A 98 -#define SRST_GMAC2IO_A 99 -#define SRST_MACPHY 100 -#define SRST_OTP_PHY 101 -#define SRST_GPU_A 102 -#define SRST_GPU_NIU_A 103 -#define SRST_SDMMCEXT 104 -#define SRST_PERIPH_NIU_A 105 -#define SRST_PERIHP_NIU_H 106 -#define SRST_PERIHP_P 107 -#define SRST_PERIPHSYS_H 108 -#define SRST_MMC0 109 -#define SRST_SDIO 110 -#define SRST_EMMC 111 - -#define SRST_USB2OTG_H 112 -#define SRST_USB2OTG 113 -#define SRST_USB2OTG_ADP 114 -#define SRST_USB2HOST_H 115 -#define SRST_USB2HOST_ARB 116 -#define SRST_USB2HOST_AUX 117 -#define SRST_USB2HOST_EHCIPHY 118 -#define SRST_USB2HOST_UTMI 119 -#define SRST_USB3OTG 120 -#define SRST_USBPOR 121 -#define SRST_USB2OTG_UTMI 122 -#define SRST_USB2HOST_PHY_UTMI 123 -#define SRST_USB3OTG_UTMI 124 -#define SRST_USB3PHY_U2 125 -#define SRST_USB3PHY_U3 126 -#define SRST_USB3PHY_PIPE 127 - -#define SRST_VIO_A 128 -#define SRST_VIO_BUS_H 129 -#define SRST_VIO_H2P_H 130 -#define SRST_VIO_ARBI_H 131 -#define SRST_VOP_NIU_A 132 -#define SRST_VOP_A 133 -#define SRST_VOP_H 134 -#define SRST_VOP_D 135 -#define SRST_RGA 136 -#define SRST_RGA_NIU_A 137 -#define SRST_RGA_A 138 -#define SRST_RGA_H 139 -#define SRST_IEP_A 140 -#define SRST_IEP_H 141 -#define SRST_HDMI 142 -#define SRST_HDMI_P 143 - -#define SRST_HDCP_A 144 -#define SRST_HDCP 145 -#define SRST_HDCP_H 146 -#define SRST_CIF_A 147 -#define SRST_CIF_H 148 -#define SRST_CIF_P 149 -#define SRST_OTP_P 150 -#define SRST_OTP_SBPI 151 -#define SRST_OTP_USER 152 -#define SRST_DDRCTRL_A 153 -#define SRST_DDRSTDY_P 154 -#define SRST_DDRSTDY 155 -#define SRST_PDM_H 156 -#define SRST_PDM 157 -#define SRST_USB3PHY_OTG_P 158 -#define SRST_USB3PHY_PIPE_P 159 - -#define SRST_VCODEC_A 160 -#define SRST_VCODEC_NIU_A 161 -#define SRST_VCODEC_H 162 -#define SRST_VCODEC_NIU_H 163 -#define SRST_VDEC_A 164 -#define SRST_VDEC_NIU_A 165 -#define SRST_VDEC_H 166 -#define SRST_VDEC_NIU_H 167 -#define SRST_VDEC_CORE 168 -#define SRST_VDEC_CABAC 169 -#define SRST_DDRPHYDIV 175 - -#define SRST_RKVENC_NIU_A 176 -#define SRST_RKVENC_NIU_H 177 -#define SRST_RKVENC_H265_A 178 -#define SRST_RKVENC_H265_P 179 -#define SRST_RKVENC_H265_CORE 180 -#define SRST_RKVENC_H265_DSP 181 -#define SRST_RKVENC_H264_A 182 -#define SRST_RKVENC_H264_H 183 -#define SRST_RKVENC_INTMEM 184 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/rk3368-cru.h b/sys/gnu/dts/include/dt-bindings/clock/rk3368-cru.h deleted file mode 100644 index 0a06c5f514d..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/rk3368-cru.h +++ /dev/null @@ -1,381 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright (c) 2015 Heiko Stuebner - */ - -#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3368_H -#define _DT_BINDINGS_CLK_ROCKCHIP_RK3368_H - -/* core clocks */ -#define PLL_APLLB 1 -#define PLL_APLLL 2 -#define PLL_DPLL 3 -#define PLL_CPLL 4 -#define PLL_GPLL 5 -#define PLL_NPLL 6 -#define ARMCLKB 7 -#define ARMCLKL 8 - -/* sclk gates (special clocks) */ -#define SCLK_GPU_CORE 64 -#define SCLK_SPI0 65 -#define SCLK_SPI1 66 -#define SCLK_SPI2 67 -#define SCLK_SDMMC 68 -#define SCLK_SDIO0 69 -#define SCLK_EMMC 71 -#define SCLK_TSADC 72 -#define SCLK_SARADC 73 -#define SCLK_NANDC0 75 -#define SCLK_UART0 77 -#define SCLK_UART1 78 -#define SCLK_UART2 79 -#define SCLK_UART3 80 -#define SCLK_UART4 81 -#define SCLK_I2S_8CH 82 -#define SCLK_SPDIF_8CH 83 -#define SCLK_I2S_2CH 84 -#define SCLK_TIMER00 85 -#define SCLK_TIMER01 86 -#define SCLK_TIMER02 87 -#define SCLK_TIMER03 88 -#define SCLK_TIMER04 89 -#define SCLK_TIMER05 90 -#define SCLK_OTGPHY0 93 -#define SCLK_OTG_ADP 96 -#define SCLK_HSICPHY480M 97 -#define SCLK_HSICPHY12M 98 -#define SCLK_MACREF 99 -#define SCLK_VOP0_PWM 100 -#define SCLK_MAC_RX 102 -#define SCLK_MAC_TX 103 -#define SCLK_EDP_24M 104 -#define SCLK_EDP 105 -#define SCLK_RGA 106 -#define SCLK_ISP 107 -#define SCLK_HDCP 108 -#define SCLK_HDMI_HDCP 109 -#define SCLK_HDMI_CEC 110 -#define SCLK_HEVC_CABAC 111 -#define SCLK_HEVC_CORE 112 -#define SCLK_I2S_8CH_OUT 113 -#define SCLK_SDMMC_DRV 114 -#define SCLK_SDIO0_DRV 115 -#define SCLK_EMMC_DRV 117 -#define SCLK_SDMMC_SAMPLE 118 -#define SCLK_SDIO0_SAMPLE 119 -#define SCLK_EMMC_SAMPLE 121 -#define SCLK_USBPHY480M 122 -#define SCLK_PVTM_CORE 123 -#define SCLK_PVTM_GPU 124 -#define SCLK_PVTM_PMU 125 -#define SCLK_SFC 126 -#define SCLK_MAC 127 -#define SCLK_MACREF_OUT 128 -#define SCLK_TIMER10 133 -#define SCLK_TIMER11 134 -#define SCLK_TIMER12 135 -#define SCLK_TIMER13 136 -#define SCLK_TIMER14 137 -#define SCLK_TIMER15 138 - -#define DCLK_VOP 190 -#define MCLK_CRYPTO 191 - -/* aclk gates */ -#define ACLK_GPU_MEM 192 -#define ACLK_GPU_CFG 193 -#define ACLK_DMAC_BUS 194 -#define ACLK_DMAC_PERI 195 -#define ACLK_PERI_MMU 196 -#define ACLK_GMAC 197 -#define ACLK_VOP 198 -#define ACLK_VOP_IEP 199 -#define ACLK_RGA 200 -#define ACLK_HDCP 201 -#define ACLK_IEP 202 -#define ACLK_VIO0_NOC 203 -#define ACLK_VIP 204 -#define ACLK_ISP 205 -#define ACLK_VIO1_NOC 206 -#define ACLK_VIDEO 208 -#define ACLK_BUS 209 -#define ACLK_PERI 210 - -/* pclk gates */ -#define PCLK_GPIO0 320 -#define PCLK_GPIO1 321 -#define PCLK_GPIO2 322 -#define PCLK_GPIO3 323 -#define PCLK_PMUGRF 324 -#define PCLK_MAILBOX 325 -#define PCLK_GRF 329 -#define PCLK_SGRF 330 -#define PCLK_PMU 331 -#define PCLK_I2C0 332 -#define PCLK_I2C1 333 -#define PCLK_I2C2 334 -#define PCLK_I2C3 335 -#define PCLK_I2C4 336 -#define PCLK_I2C5 337 -#define PCLK_SPI0 338 -#define PCLK_SPI1 339 -#define PCLK_SPI2 340 -#define PCLK_UART0 341 -#define PCLK_UART1 342 -#define PCLK_UART2 343 -#define PCLK_UART3 344 -#define PCLK_UART4 345 -#define PCLK_TSADC 346 -#define PCLK_SARADC 347 -#define PCLK_SIM 348 -#define PCLK_GMAC 349 -#define PCLK_PWM0 350 -#define PCLK_PWM1 351 -#define PCLK_TIMER0 353 -#define PCLK_TIMER1 354 -#define PCLK_EDP_CTRL 355 -#define PCLK_MIPI_DSI0 356 -#define PCLK_MIPI_CSI 358 -#define PCLK_HDCP 359 -#define PCLK_HDMI_CTRL 360 -#define PCLK_VIO_H2P 361 -#define PCLK_BUS 362 -#define PCLK_PERI 363 -#define PCLK_DDRUPCTL 364 -#define PCLK_DDRPHY 365 -#define PCLK_ISP 366 -#define PCLK_VIP 367 -#define PCLK_WDT 368 -#define PCLK_EFUSE256 369 - -/* hclk gates */ -#define HCLK_SFC 448 -#define HCLK_OTG0 449 -#define HCLK_HOST0 450 -#define HCLK_HOST1 451 -#define HCLK_HSIC 452 -#define HCLK_NANDC0 453 -#define HCLK_TSP 455 -#define HCLK_SDMMC 456 -#define HCLK_SDIO0 457 -#define HCLK_EMMC 459 -#define HCLK_HSADC 460 -#define HCLK_CRYPTO 461 -#define HCLK_I2S_2CH 462 -#define HCLK_I2S_8CH 463 -#define HCLK_SPDIF 464 -#define HCLK_VOP 465 -#define HCLK_ROM 467 -#define HCLK_IEP 468 -#define HCLK_ISP 469 -#define HCLK_RGA 470 -#define HCLK_VIO_AHB_ARBI 471 -#define HCLK_VIO_NOC 472 -#define HCLK_VIP 473 -#define HCLK_VIO_H2P 474 -#define HCLK_VIO_HDCPMMU 475 -#define HCLK_VIDEO 476 -#define HCLK_BUS 477 -#define HCLK_PERI 478 - -#define CLK_NR_CLKS (HCLK_PERI + 1) - -/* soft-reset indices */ -#define SRST_CORE_B0 0 -#define SRST_CORE_B1 1 -#define SRST_CORE_B2 2 -#define SRST_CORE_B3 3 -#define SRST_CORE_B0_PO 4 -#define SRST_CORE_B1_PO 5 -#define SRST_CORE_B2_PO 6 -#define SRST_CORE_B3_PO 7 -#define SRST_L2_B 8 -#define SRST_ADB_B 9 -#define SRST_PD_CORE_B_NIU 10 -#define SRST_PDBUS_STRSYS 11 -#define SRST_SOCDBG_B 14 -#define SRST_CORE_B_DBG 15 - -#define SRST_DMAC1 18 -#define SRST_INTMEM 19 -#define SRST_ROM 20 -#define SRST_SPDIF8CH 21 -#define SRST_I2S8CH 23 -#define SRST_MAILBOX 24 -#define SRST_I2S2CH 25 -#define SRST_EFUSE_256 26 -#define SRST_MCU_SYS 28 -#define SRST_MCU_PO 29 -#define SRST_MCU_NOC 30 -#define SRST_EFUSE 31 - -#define SRST_GPIO0 32 -#define SRST_GPIO1 33 -#define SRST_GPIO2 34 -#define SRST_GPIO3 35 -#define SRST_GPIO4 36 -#define SRST_PMUGRF 41 -#define SRST_I2C0 42 -#define SRST_I2C1 43 -#define SRST_I2C2 44 -#define SRST_I2C3 45 -#define SRST_I2C4 46 -#define SRST_I2C5 47 - -#define SRST_DWPWM 48 -#define SRST_MMC_PERI 49 -#define SRST_PERIPH_MMU 50 -#define SRST_GRF 55 -#define SRST_PMU 56 -#define SRST_PERIPH_AXI 57 -#define SRST_PERIPH_AHB 58 -#define SRST_PERIPH_APB 59 -#define SRST_PERIPH_NIU 60 -#define SRST_PDPERI_AHB_ARBI 61 -#define SRST_EMEM 62 -#define SRST_USB_PERI 63 - -#define SRST_DMAC2 64 -#define SRST_MAC 66 -#define SRST_GPS 67 -#define SRST_RKPWM 69 -#define SRST_USBHOST0 72 -#define SRST_HSIC 73 -#define SRST_HSIC_AUX 74 -#define SRST_HSIC_PHY 75 -#define SRST_HSADC 76 -#define SRST_NANDC0 77 -#define SRST_SFC 79 - -#define SRST_SPI0 83 -#define SRST_SPI1 84 -#define SRST_SPI2 85 -#define SRST_SARADC 87 -#define SRST_PDALIVE_NIU 88 -#define SRST_PDPMU_INTMEM 89 -#define SRST_PDPMU_NIU 90 -#define SRST_SGRF 91 - -#define SRST_VIO_ARBI 96 -#define SRST_RGA_NIU 97 -#define SRST_VIO0_NIU_AXI 98 -#define SRST_VIO_NIU_AHB 99 -#define SRST_LCDC0_AXI 100 -#define SRST_LCDC0_AHB 101 -#define SRST_LCDC0_DCLK 102 -#define SRST_VIP 104 -#define SRST_RGA_CORE 105 -#define SRST_IEP_AXI 106 -#define SRST_IEP_AHB 107 -#define SRST_RGA_AXI 108 -#define SRST_RGA_AHB 109 -#define SRST_ISP 110 -#define SRST_EDP_24M 111 - -#define SRST_VIDEO_AXI 112 -#define SRST_VIDEO_AHB 113 -#define SRST_MIPIDPHYTX 114 -#define SRST_MIPIDSI0 115 -#define SRST_MIPIDPHYRX 116 -#define SRST_MIPICSI 117 -#define SRST_GPU 120 -#define SRST_HDMI 121 -#define SRST_EDP 122 -#define SRST_PMU_PVTM 123 -#define SRST_CORE_PVTM 124 -#define SRST_GPU_PVTM 125 -#define SRST_GPU_SYS 126 -#define SRST_GPU_MEM_NIU 127 - -#define SRST_MMC0 128 -#define SRST_SDIO0 129 -#define SRST_EMMC 131 -#define SRST_USBOTG_AHB 132 -#define SRST_USBOTG_PHY 133 -#define SRST_USBOTG_CON 134 -#define SRST_USBHOST0_AHB 135 -#define SRST_USBHOST0_PHY 136 -#define SRST_USBHOST0_CON 137 -#define SRST_USBOTG_UTMI 138 -#define SRST_USBHOST1_UTMI 139 -#define SRST_USB_ADP 141 - -#define SRST_CORESIGHT 144 -#define SRST_PD_CORE_AHB_NOC 145 -#define SRST_PD_CORE_APB_NOC 146 -#define SRST_GIC 148 -#define SRST_LCDC_PWM0 149 -#define SRST_RGA_H2P_BRG 153 -#define SRST_VIDEO 154 -#define SRST_GPU_CFG_NIU 157 -#define SRST_TSADC 159 - -#define SRST_DDRPHY0 160 -#define SRST_DDRPHY0_APB 161 -#define SRST_DDRCTRL0 162 -#define SRST_DDRCTRL0_APB 163 -#define SRST_VIDEO_NIU 165 -#define SRST_VIDEO_NIU_AHB 167 -#define SRST_DDRMSCH0 170 -#define SRST_PDBUS_AHB 173 -#define SRST_CRYPTO 174 - -#define SRST_UART0 179 -#define SRST_UART1 180 -#define SRST_UART2 181 -#define SRST_UART3 182 -#define SRST_UART4 183 -#define SRST_SIMC 186 -#define SRST_TSP 188 -#define SRST_TSP_CLKIN0 189 - -#define SRST_CORE_L0 192 -#define SRST_CORE_L1 193 -#define SRST_CORE_L2 194 -#define SRST_CORE_L3 195 -#define SRST_CORE_L0_PO 195 -#define SRST_CORE_L1_PO 197 -#define SRST_CORE_L2_PO 198 -#define SRST_CORE_L3_PO 199 -#define SRST_L2_L 200 -#define SRST_ADB_L 201 -#define SRST_PD_CORE_L_NIU 202 -#define SRST_CCI_SYS 203 -#define SRST_CCI_DDR 204 -#define SRST_CCI 205 -#define SRST_SOCDBG_L 206 -#define SRST_CORE_L_DBG 207 - -#define SRST_CORE_B0_NC 208 -#define SRST_CORE_B0_PO_NC 209 -#define SRST_L2_B_NC 210 -#define SRST_ADB_B_NC 211 -#define SRST_PD_CORE_B_NIU_NC 212 -#define SRST_PDBUS_STRSYS_NC 213 -#define SRST_CORE_L0_NC 214 -#define SRST_CORE_L0_PO_NC 215 -#define SRST_L2_L_NC 216 -#define SRST_ADB_L_NC 217 -#define SRST_PD_CORE_L_NIU_NC 218 -#define SRST_CCI_SYS_NC 219 -#define SRST_CCI_DDR_NC 220 -#define SRST_CCI_NC 221 -#define SRST_TRACE_NC 222 - -#define SRST_TIMER00 224 -#define SRST_TIMER01 225 -#define SRST_TIMER02 226 -#define SRST_TIMER03 227 -#define SRST_TIMER04 228 -#define SRST_TIMER05 229 -#define SRST_TIMER10 230 -#define SRST_TIMER11 231 -#define SRST_TIMER12 232 -#define SRST_TIMER13 233 -#define SRST_TIMER14 234 -#define SRST_TIMER15 235 -#define SRST_TIMER0_APB 236 -#define SRST_TIMER1_APB 237 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/rk3399-cru.h b/sys/gnu/dts/include/dt-bindings/clock/rk3399-cru.h deleted file mode 100644 index 44e0a319f07..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/rk3399-cru.h +++ /dev/null @@ -1,751 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright (c) 2016 Rockchip Electronics Co. Ltd. - * Author: Xing Zheng - */ - -#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H -#define _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H - -/* core clocks */ -#define PLL_APLLL 1 -#define PLL_APLLB 2 -#define PLL_DPLL 3 -#define PLL_CPLL 4 -#define PLL_GPLL 5 -#define PLL_NPLL 6 -#define PLL_VPLL 7 -#define ARMCLKL 8 -#define ARMCLKB 9 - -/* sclk gates (special clocks) */ -#define SCLK_I2C1 65 -#define SCLK_I2C2 66 -#define SCLK_I2C3 67 -#define SCLK_I2C5 68 -#define SCLK_I2C6 69 -#define SCLK_I2C7 70 -#define SCLK_SPI0 71 -#define SCLK_SPI1 72 -#define SCLK_SPI2 73 -#define SCLK_SPI4 74 -#define SCLK_SPI5 75 -#define SCLK_SDMMC 76 -#define SCLK_SDIO 77 -#define SCLK_EMMC 78 -#define SCLK_TSADC 79 -#define SCLK_SARADC 80 -#define SCLK_UART0 81 -#define SCLK_UART1 82 -#define SCLK_UART2 83 -#define SCLK_UART3 84 -#define SCLK_SPDIF_8CH 85 -#define SCLK_I2S0_8CH 86 -#define SCLK_I2S1_8CH 87 -#define SCLK_I2S2_8CH 88 -#define SCLK_I2S_8CH_OUT 89 -#define SCLK_TIMER00 90 -#define SCLK_TIMER01 91 -#define SCLK_TIMER02 92 -#define SCLK_TIMER03 93 -#define SCLK_TIMER04 94 -#define SCLK_TIMER05 95 -#define SCLK_TIMER06 96 -#define SCLK_TIMER07 97 -#define SCLK_TIMER08 98 -#define SCLK_TIMER09 99 -#define SCLK_TIMER10 100 -#define SCLK_TIMER11 101 -#define SCLK_MACREF 102 -#define SCLK_MAC_RX 103 -#define SCLK_MAC_TX 104 -#define SCLK_MAC 105 -#define SCLK_MACREF_OUT 106 -#define SCLK_VOP0_PWM 107 -#define SCLK_VOP1_PWM 108 -#define SCLK_RGA_CORE 109 -#define SCLK_ISP0 110 -#define SCLK_ISP1 111 -#define SCLK_HDMI_CEC 112 -#define SCLK_HDMI_SFR 113 -#define SCLK_DP_CORE 114 -#define SCLK_PVTM_CORE_L 115 -#define SCLK_PVTM_CORE_B 116 -#define SCLK_PVTM_GPU 117 -#define SCLK_PVTM_DDR 118 -#define SCLK_MIPIDPHY_REF 119 -#define SCLK_MIPIDPHY_CFG 120 -#define SCLK_HSICPHY 121 -#define SCLK_USBPHY480M 122 -#define SCLK_USB2PHY0_REF 123 -#define SCLK_USB2PHY1_REF 124 -#define SCLK_UPHY0_TCPDPHY_REF 125 -#define SCLK_UPHY0_TCPDCORE 126 -#define SCLK_UPHY1_TCPDPHY_REF 127 -#define SCLK_UPHY1_TCPDCORE 128 -#define SCLK_USB3OTG0_REF 129 -#define SCLK_USB3OTG1_REF 130 -#define SCLK_USB3OTG0_SUSPEND 131 -#define SCLK_USB3OTG1_SUSPEND 132 -#define SCLK_CRYPTO0 133 -#define SCLK_CRYPTO1 134 -#define SCLK_CCI_TRACE 135 -#define SCLK_CS 136 -#define SCLK_CIF_OUT 137 -#define SCLK_PCIEPHY_REF 138 -#define SCLK_PCIE_CORE 139 -#define SCLK_M0_PERILP 140 -#define SCLK_M0_PERILP_DEC 141 -#define SCLK_CM0S 142 -#define SCLK_DBG_NOC 143 -#define SCLK_DBG_PD_CORE_B 144 -#define SCLK_DBG_PD_CORE_L 145 -#define SCLK_DFIMON0_TIMER 146 -#define SCLK_DFIMON1_TIMER 147 -#define SCLK_INTMEM0 148 -#define SCLK_INTMEM1 149 -#define SCLK_INTMEM2 150 -#define SCLK_INTMEM3 151 -#define SCLK_INTMEM4 152 -#define SCLK_INTMEM5 153 -#define SCLK_SDMMC_DRV 154 -#define SCLK_SDMMC_SAMPLE 155 -#define SCLK_SDIO_DRV 156 -#define SCLK_SDIO_SAMPLE 157 -#define SCLK_VDU_CORE 158 -#define SCLK_VDU_CA 159 -#define SCLK_PCIE_PM 160 -#define SCLK_SPDIF_REC_DPTX 161 -#define SCLK_DPHY_PLL 162 -#define SCLK_DPHY_TX0_CFG 163 -#define SCLK_DPHY_TX1RX1_CFG 164 -#define SCLK_DPHY_RX0_CFG 165 -#define SCLK_RMII_SRC 166 -#define SCLK_PCIEPHY_REF100M 167 -#define SCLK_DDRC 168 -#define SCLK_TESTCLKOUT1 169 -#define SCLK_TESTCLKOUT2 170 - -#define DCLK_VOP0 180 -#define DCLK_VOP1 181 -#define DCLK_VOP0_DIV 182 -#define DCLK_VOP1_DIV 183 -#define DCLK_M0_PERILP 184 -#define DCLK_VOP0_FRAC 185 -#define DCLK_VOP1_FRAC 186 - -#define FCLK_CM0S 190 - -/* aclk gates */ -#define ACLK_PERIHP 192 -#define ACLK_PERIHP_NOC 193 -#define ACLK_PERILP0 194 -#define ACLK_PERILP0_NOC 195 -#define ACLK_PERF_PCIE 196 -#define ACLK_PCIE 197 -#define ACLK_INTMEM 198 -#define ACLK_TZMA 199 -#define ACLK_DCF 200 -#define ACLK_CCI 201 -#define ACLK_CCI_NOC0 202 -#define ACLK_CCI_NOC1 203 -#define ACLK_CCI_GRF 204 -#define ACLK_CENTER 205 -#define ACLK_CENTER_MAIN_NOC 206 -#define ACLK_CENTER_PERI_NOC 207 -#define ACLK_GPU 208 -#define ACLK_PERF_GPU 209 -#define ACLK_GPU_GRF 210 -#define ACLK_DMAC0_PERILP 211 -#define ACLK_DMAC1_PERILP 212 -#define ACLK_GMAC 213 -#define ACLK_GMAC_NOC 214 -#define ACLK_PERF_GMAC 215 -#define ACLK_VOP0_NOC 216 -#define ACLK_VOP0 217 -#define ACLK_VOP1_NOC 218 -#define ACLK_VOP1 219 -#define ACLK_RGA 220 -#define ACLK_RGA_NOC 221 -#define ACLK_HDCP 222 -#define ACLK_HDCP_NOC 223 -#define ACLK_HDCP22 224 -#define ACLK_IEP 225 -#define ACLK_IEP_NOC 226 -#define ACLK_VIO 227 -#define ACLK_VIO_NOC 228 -#define ACLK_ISP0 229 -#define ACLK_ISP1 230 -#define ACLK_ISP0_NOC 231 -#define ACLK_ISP1_NOC 232 -#define ACLK_ISP0_WRAPPER 233 -#define ACLK_ISP1_WRAPPER 234 -#define ACLK_VCODEC 235 -#define ACLK_VCODEC_NOC 236 -#define ACLK_VDU 237 -#define ACLK_VDU_NOC 238 -#define ACLK_PERI 239 -#define ACLK_EMMC 240 -#define ACLK_EMMC_CORE 241 -#define ACLK_EMMC_NOC 242 -#define ACLK_EMMC_GRF 243 -#define ACLK_USB3 244 -#define ACLK_USB3_NOC 245 -#define ACLK_USB3OTG0 246 -#define ACLK_USB3OTG1 247 -#define ACLK_USB3_RKSOC_AXI_PERF 248 -#define ACLK_USB3_GRF 249 -#define ACLK_GIC 250 -#define ACLK_GIC_NOC 251 -#define ACLK_GIC_ADB400_CORE_L_2_GIC 252 -#define ACLK_GIC_ADB400_CORE_B_2_GIC 253 -#define ACLK_GIC_ADB400_GIC_2_CORE_L 254 -#define ACLK_GIC_ADB400_GIC_2_CORE_B 255 -#define ACLK_CORE_ADB400_CORE_L_2_CCI500 256 -#define ACLK_CORE_ADB400_CORE_B_2_CCI500 257 -#define ACLK_ADB400M_PD_CORE_L 258 -#define ACLK_ADB400M_PD_CORE_B 259 -#define ACLK_PERF_CORE_L 260 -#define ACLK_PERF_CORE_B 261 -#define ACLK_GIC_PRE 262 -#define ACLK_VOP0_PRE 263 -#define ACLK_VOP1_PRE 264 - -/* pclk gates */ -#define PCLK_PERIHP 320 -#define PCLK_PERIHP_NOC 321 -#define PCLK_PERILP0 322 -#define PCLK_PERILP1 323 -#define PCLK_PERILP1_NOC 324 -#define PCLK_PERILP_SGRF 325 -#define PCLK_PERIHP_GRF 326 -#define PCLK_PCIE 327 -#define PCLK_SGRF 328 -#define PCLK_INTR_ARB 329 -#define PCLK_CENTER_MAIN_NOC 330 -#define PCLK_CIC 331 -#define PCLK_COREDBG_B 332 -#define PCLK_COREDBG_L 333 -#define PCLK_DBG_CXCS_PD_CORE_B 334 -#define PCLK_DCF 335 -#define PCLK_GPIO2 336 -#define PCLK_GPIO3 337 -#define PCLK_GPIO4 338 -#define PCLK_GRF 339 -#define PCLK_HSICPHY 340 -#define PCLK_I2C1 341 -#define PCLK_I2C2 342 -#define PCLK_I2C3 343 -#define PCLK_I2C5 344 -#define PCLK_I2C6 345 -#define PCLK_I2C7 346 -#define PCLK_SPI0 347 -#define PCLK_SPI1 348 -#define PCLK_SPI2 349 -#define PCLK_SPI4 350 -#define PCLK_SPI5 351 -#define PCLK_UART0 352 -#define PCLK_UART1 353 -#define PCLK_UART2 354 -#define PCLK_UART3 355 -#define PCLK_TSADC 356 -#define PCLK_SARADC 357 -#define PCLK_GMAC 358 -#define PCLK_GMAC_NOC 359 -#define PCLK_TIMER0 360 -#define PCLK_TIMER1 361 -#define PCLK_EDP 362 -#define PCLK_EDP_NOC 363 -#define PCLK_EDP_CTRL 364 -#define PCLK_VIO 365 -#define PCLK_VIO_NOC 366 -#define PCLK_VIO_GRF 367 -#define PCLK_MIPI_DSI0 368 -#define PCLK_MIPI_DSI1 369 -#define PCLK_HDCP 370 -#define PCLK_HDCP_NOC 371 -#define PCLK_HDMI_CTRL 372 -#define PCLK_DP_CTRL 373 -#define PCLK_HDCP22 374 -#define PCLK_GASKET 375 -#define PCLK_DDR 376 -#define PCLK_DDR_MON 377 -#define PCLK_DDR_SGRF 378 -#define PCLK_ISP1_WRAPPER 379 -#define PCLK_WDT 380 -#define PCLK_EFUSE1024NS 381 -#define PCLK_EFUSE1024S 382 -#define PCLK_PMU_INTR_ARB 383 -#define PCLK_MAILBOX0 384 -#define PCLK_USBPHY_MUX_G 385 -#define PCLK_UPHY0_TCPHY_G 386 -#define PCLK_UPHY0_TCPD_G 387 -#define PCLK_UPHY1_TCPHY_G 388 -#define PCLK_UPHY1_TCPD_G 389 -#define PCLK_ALIVE 390 - -/* hclk gates */ -#define HCLK_PERIHP 448 -#define HCLK_PERILP0 449 -#define HCLK_PERILP1 450 -#define HCLK_PERILP0_NOC 451 -#define HCLK_PERILP1_NOC 452 -#define HCLK_M0_PERILP 453 -#define HCLK_M0_PERILP_NOC 454 -#define HCLK_AHB1TOM 455 -#define HCLK_HOST0 456 -#define HCLK_HOST0_ARB 457 -#define HCLK_HOST1 458 -#define HCLK_HOST1_ARB 459 -#define HCLK_HSIC 460 -#define HCLK_SD 461 -#define HCLK_SDMMC 462 -#define HCLK_SDMMC_NOC 463 -#define HCLK_M_CRYPTO0 464 -#define HCLK_M_CRYPTO1 465 -#define HCLK_S_CRYPTO0 466 -#define HCLK_S_CRYPTO1 467 -#define HCLK_I2S0_8CH 468 -#define HCLK_I2S1_8CH 469 -#define HCLK_I2S2_8CH 470 -#define HCLK_SPDIF 471 -#define HCLK_VOP0_NOC 472 -#define HCLK_VOP0 473 -#define HCLK_VOP1_NOC 474 -#define HCLK_VOP1 475 -#define HCLK_ROM 476 -#define HCLK_IEP 477 -#define HCLK_IEP_NOC 478 -#define HCLK_ISP0 479 -#define HCLK_ISP1 480 -#define HCLK_ISP0_NOC 481 -#define HCLK_ISP1_NOC 482 -#define HCLK_ISP0_WRAPPER 483 -#define HCLK_ISP1_WRAPPER 484 -#define HCLK_RGA 485 -#define HCLK_RGA_NOC 486 -#define HCLK_HDCP 487 -#define HCLK_HDCP_NOC 488 -#define HCLK_HDCP22 489 -#define HCLK_VCODEC 490 -#define HCLK_VCODEC_NOC 491 -#define HCLK_VDU 492 -#define HCLK_VDU_NOC 493 -#define HCLK_SDIO 494 -#define HCLK_SDIO_NOC 495 -#define HCLK_SDIOAUDIO_NOC 496 - -#define CLK_NR_CLKS (HCLK_SDIOAUDIO_NOC + 1) - -/* pmu-clocks indices */ - -#define PLL_PPLL 1 - -#define SCLK_32K_SUSPEND_PMU 2 -#define SCLK_SPI3_PMU 3 -#define SCLK_TIMER12_PMU 4 -#define SCLK_TIMER13_PMU 5 -#define SCLK_UART4_PMU 6 -#define SCLK_PVTM_PMU 7 -#define SCLK_WIFI_PMU 8 -#define SCLK_I2C0_PMU 9 -#define SCLK_I2C4_PMU 10 -#define SCLK_I2C8_PMU 11 - -#define PCLK_SRC_PMU 19 -#define PCLK_PMU 20 -#define PCLK_PMUGRF_PMU 21 -#define PCLK_INTMEM1_PMU 22 -#define PCLK_GPIO0_PMU 23 -#define PCLK_GPIO1_PMU 24 -#define PCLK_SGRF_PMU 25 -#define PCLK_NOC_PMU 26 -#define PCLK_I2C0_PMU 27 -#define PCLK_I2C4_PMU 28 -#define PCLK_I2C8_PMU 29 -#define PCLK_RKPWM_PMU 30 -#define PCLK_SPI3_PMU 31 -#define PCLK_TIMER_PMU 32 -#define PCLK_MAILBOX_PMU 33 -#define PCLK_UART4_PMU 34 -#define PCLK_WDT_M0_PMU 35 - -#define FCLK_CM0S_SRC_PMU 44 -#define FCLK_CM0S_PMU 45 -#define SCLK_CM0S_PMU 46 -#define HCLK_CM0S_PMU 47 -#define DCLK_CM0S_PMU 48 -#define PCLK_INTR_ARB_PMU 49 -#define HCLK_NOC_PMU 50 - -#define CLKPMU_NR_CLKS (HCLK_NOC_PMU + 1) - -/* soft-reset indices */ - -/* cru_softrst_con0 */ -#define SRST_CORE_L0 0 -#define SRST_CORE_B0 1 -#define SRST_CORE_PO_L0 2 -#define SRST_CORE_PO_B0 3 -#define SRST_L2_L 4 -#define SRST_L2_B 5 -#define SRST_ADB_L 6 -#define SRST_ADB_B 7 -#define SRST_A_CCI 8 -#define SRST_A_CCIM0_NOC 9 -#define SRST_A_CCIM1_NOC 10 -#define SRST_DBG_NOC 11 - -/* cru_softrst_con1 */ -#define SRST_CORE_L0_T 16 -#define SRST_CORE_L1 17 -#define SRST_CORE_L2 18 -#define SRST_CORE_L3 19 -#define SRST_CORE_PO_L0_T 20 -#define SRST_CORE_PO_L1 21 -#define SRST_CORE_PO_L2 22 -#define SRST_CORE_PO_L3 23 -#define SRST_A_ADB400_GIC2COREL 24 -#define SRST_A_ADB400_COREL2GIC 25 -#define SRST_P_DBG_L 26 -#define SRST_L2_L_T 28 -#define SRST_ADB_L_T 29 -#define SRST_A_RKPERF_L 30 -#define SRST_PVTM_CORE_L 31 - -/* cru_softrst_con2 */ -#define SRST_CORE_B0_T 32 -#define SRST_CORE_B1 33 -#define SRST_CORE_PO_B0_T 36 -#define SRST_CORE_PO_B1 37 -#define SRST_A_ADB400_GIC2COREB 40 -#define SRST_A_ADB400_COREB2GIC 41 -#define SRST_P_DBG_B 42 -#define SRST_L2_B_T 43 -#define SRST_ADB_B_T 45 -#define SRST_A_RKPERF_B 46 -#define SRST_PVTM_CORE_B 47 - -/* cru_softrst_con3 */ -#define SRST_A_CCI_T 50 -#define SRST_A_CCIM0_NOC_T 51 -#define SRST_A_CCIM1_NOC_T 52 -#define SRST_A_ADB400M_PD_CORE_B_T 53 -#define SRST_A_ADB400M_PD_CORE_L_T 54 -#define SRST_DBG_NOC_T 55 -#define SRST_DBG_CXCS 56 -#define SRST_CCI_TRACE 57 -#define SRST_P_CCI_GRF 58 - -/* cru_softrst_con4 */ -#define SRST_A_CENTER_MAIN_NOC 64 -#define SRST_A_CENTER_PERI_NOC 65 -#define SRST_P_CENTER_MAIN 66 -#define SRST_P_DDRMON 67 -#define SRST_P_CIC 68 -#define SRST_P_CENTER_SGRF 69 -#define SRST_DDR0_MSCH 70 -#define SRST_DDRCFG0_MSCH 71 -#define SRST_DDR0 72 -#define SRST_DDRPHY0 73 -#define SRST_DDR1_MSCH 74 -#define SRST_DDRCFG1_MSCH 75 -#define SRST_DDR1 76 -#define SRST_DDRPHY1 77 -#define SRST_DDR_CIC 78 -#define SRST_PVTM_DDR 79 - -/* cru_softrst_con5 */ -#define SRST_A_VCODEC_NOC 80 -#define SRST_A_VCODEC 81 -#define SRST_H_VCODEC_NOC 82 -#define SRST_H_VCODEC 83 -#define SRST_A_VDU_NOC 88 -#define SRST_A_VDU 89 -#define SRST_H_VDU_NOC 90 -#define SRST_H_VDU 91 -#define SRST_VDU_CORE 92 -#define SRST_VDU_CA 93 - -/* cru_softrst_con6 */ -#define SRST_A_IEP_NOC 96 -#define SRST_A_VOP_IEP 97 -#define SRST_A_IEP 98 -#define SRST_H_IEP_NOC 99 -#define SRST_H_IEP 100 -#define SRST_A_RGA_NOC 102 -#define SRST_A_RGA 103 -#define SRST_H_RGA_NOC 104 -#define SRST_H_RGA 105 -#define SRST_RGA_CORE 106 -#define SRST_EMMC_NOC 108 -#define SRST_EMMC 109 -#define SRST_EMMC_GRF 110 - -/* cru_softrst_con7 */ -#define SRST_A_PERIHP_NOC 112 -#define SRST_P_PERIHP_GRF 113 -#define SRST_H_PERIHP_NOC 114 -#define SRST_USBHOST0 115 -#define SRST_HOSTC0_AUX 116 -#define SRST_HOST0_ARB 117 -#define SRST_USBHOST1 118 -#define SRST_HOSTC1_AUX 119 -#define SRST_HOST1_ARB 120 -#define SRST_SDIO0 121 -#define SRST_SDMMC 122 -#define SRST_HSIC 123 -#define SRST_HSIC_AUX 124 -#define SRST_AHB1TOM 125 -#define SRST_P_PERIHP_NOC 126 -#define SRST_HSICPHY 127 - -/* cru_softrst_con8 */ -#define SRST_A_PCIE 128 -#define SRST_P_PCIE 129 -#define SRST_PCIE_CORE 130 -#define SRST_PCIE_MGMT 131 -#define SRST_PCIE_MGMT_STICKY 132 -#define SRST_PCIE_PIPE 133 -#define SRST_PCIE_PM 134 -#define SRST_PCIEPHY 135 -#define SRST_A_GMAC_NOC 136 -#define SRST_A_GMAC 137 -#define SRST_P_GMAC_NOC 138 -#define SRST_P_GMAC_GRF 140 -#define SRST_HSICPHY_POR 142 -#define SRST_HSICPHY_UTMI 143 - -/* cru_softrst_con9 */ -#define SRST_USB2PHY0_POR 144 -#define SRST_USB2PHY0_UTMI_PORT0 145 -#define SRST_USB2PHY0_UTMI_PORT1 146 -#define SRST_USB2PHY0_EHCIPHY 147 -#define SRST_UPHY0_PIPE_L00 148 -#define SRST_UPHY0 149 -#define SRST_UPHY0_TCPDPWRUP 150 -#define SRST_USB2PHY1_POR 152 -#define SRST_USB2PHY1_UTMI_PORT0 153 -#define SRST_USB2PHY1_UTMI_PORT1 154 -#define SRST_USB2PHY1_EHCIPHY 155 -#define SRST_UPHY1_PIPE_L00 156 -#define SRST_UPHY1 157 -#define SRST_UPHY1_TCPDPWRUP 158 - -/* cru_softrst_con10 */ -#define SRST_A_PERILP0_NOC 160 -#define SRST_A_DCF 161 -#define SRST_GIC500 162 -#define SRST_DMAC0_PERILP0 163 -#define SRST_DMAC1_PERILP0 164 -#define SRST_TZMA 165 -#define SRST_INTMEM 166 -#define SRST_ADB400_MST0 167 -#define SRST_ADB400_MST1 168 -#define SRST_ADB400_SLV0 169 -#define SRST_ADB400_SLV1 170 -#define SRST_H_PERILP0 171 -#define SRST_H_PERILP0_NOC 172 -#define SRST_ROM 173 -#define SRST_CRYPTO_S 174 -#define SRST_CRYPTO_M 175 - -/* cru_softrst_con11 */ -#define SRST_P_DCF 176 -#define SRST_CM0S_NOC 177 -#define SRST_CM0S 178 -#define SRST_CM0S_DBG 179 -#define SRST_CM0S_PO 180 -#define SRST_CRYPTO 181 -#define SRST_P_PERILP1_SGRF 182 -#define SRST_P_PERILP1_GRF 183 -#define SRST_CRYPTO1_S 184 -#define SRST_CRYPTO1_M 185 -#define SRST_CRYPTO1 186 -#define SRST_GIC_NOC 188 -#define SRST_SD_NOC 189 -#define SRST_SDIOAUDIO_BRG 190 - -/* cru_softrst_con12 */ -#define SRST_H_PERILP1 192 -#define SRST_H_PERILP1_NOC 193 -#define SRST_H_I2S0_8CH 194 -#define SRST_H_I2S1_8CH 195 -#define SRST_H_I2S2_8CH 196 -#define SRST_H_SPDIF_8CH 197 -#define SRST_P_PERILP1_NOC 198 -#define SRST_P_EFUSE_1024 199 -#define SRST_P_EFUSE_1024S 200 -#define SRST_P_I2C0 201 -#define SRST_P_I2C1 202 -#define SRST_P_I2C2 203 -#define SRST_P_I2C3 204 -#define SRST_P_I2C4 205 -#define SRST_P_I2C5 206 -#define SRST_P_MAILBOX0 207 - -/* cru_softrst_con13 */ -#define SRST_P_UART0 208 -#define SRST_P_UART1 209 -#define SRST_P_UART2 210 -#define SRST_P_UART3 211 -#define SRST_P_SARADC 212 -#define SRST_P_TSADC 213 -#define SRST_P_SPI0 214 -#define SRST_P_SPI1 215 -#define SRST_P_SPI2 216 -#define SRST_P_SPI3 217 -#define SRST_P_SPI4 218 -#define SRST_SPI0 219 -#define SRST_SPI1 220 -#define SRST_SPI2 221 -#define SRST_SPI3 222 -#define SRST_SPI4 223 - -/* cru_softrst_con14 */ -#define SRST_I2S0_8CH 224 -#define SRST_I2S1_8CH 225 -#define SRST_I2S2_8CH 226 -#define SRST_SPDIF_8CH 227 -#define SRST_UART0 228 -#define SRST_UART1 229 -#define SRST_UART2 230 -#define SRST_UART3 231 -#define SRST_TSADC 232 -#define SRST_I2C0 233 -#define SRST_I2C1 234 -#define SRST_I2C2 235 -#define SRST_I2C3 236 -#define SRST_I2C4 237 -#define SRST_I2C5 238 -#define SRST_SDIOAUDIO_NOC 239 - -/* cru_softrst_con15 */ -#define SRST_A_VIO_NOC 240 -#define SRST_A_HDCP_NOC 241 -#define SRST_A_HDCP 242 -#define SRST_H_HDCP_NOC 243 -#define SRST_H_HDCP 244 -#define SRST_P_HDCP_NOC 245 -#define SRST_P_HDCP 246 -#define SRST_P_HDMI_CTRL 247 -#define SRST_P_DP_CTRL 248 -#define SRST_S_DP_CTRL 249 -#define SRST_C_DP_CTRL 250 -#define SRST_P_MIPI_DSI0 251 -#define SRST_P_MIPI_DSI1 252 -#define SRST_DP_CORE 253 -#define SRST_DP_I2S 254 - -/* cru_softrst_con16 */ -#define SRST_GASKET 256 -#define SRST_VIO_GRF 258 -#define SRST_DPTX_SPDIF_REC 259 -#define SRST_HDMI_CTRL 260 -#define SRST_HDCP_CTRL 261 -#define SRST_A_ISP0_NOC 262 -#define SRST_A_ISP1_NOC 263 -#define SRST_H_ISP0_NOC 266 -#define SRST_H_ISP1_NOC 267 -#define SRST_H_ISP0 268 -#define SRST_H_ISP1 269 -#define SRST_ISP0 270 -#define SRST_ISP1 271 - -/* cru_softrst_con17 */ -#define SRST_A_VOP0_NOC 272 -#define SRST_A_VOP1_NOC 273 -#define SRST_A_VOP0 274 -#define SRST_A_VOP1 275 -#define SRST_H_VOP0_NOC 276 -#define SRST_H_VOP1_NOC 277 -#define SRST_H_VOP0 278 -#define SRST_H_VOP1 279 -#define SRST_D_VOP0 280 -#define SRST_D_VOP1 281 -#define SRST_VOP0_PWM 282 -#define SRST_VOP1_PWM 283 -#define SRST_P_EDP_NOC 284 -#define SRST_P_EDP_CTRL 285 - -/* cru_softrst_con18 */ -#define SRST_A_GPU 288 -#define SRST_A_GPU_NOC 289 -#define SRST_A_GPU_GRF 290 -#define SRST_PVTM_GPU 291 -#define SRST_A_USB3_NOC 292 -#define SRST_A_USB3_OTG0 293 -#define SRST_A_USB3_OTG1 294 -#define SRST_A_USB3_GRF 295 -#define SRST_PMU 296 - -/* cru_softrst_con19 */ -#define SRST_P_TIMER0_5 304 -#define SRST_TIMER0 305 -#define SRST_TIMER1 306 -#define SRST_TIMER2 307 -#define SRST_TIMER3 308 -#define SRST_TIMER4 309 -#define SRST_TIMER5 310 -#define SRST_P_TIMER6_11 311 -#define SRST_TIMER6 312 -#define SRST_TIMER7 313 -#define SRST_TIMER8 314 -#define SRST_TIMER9 315 -#define SRST_TIMER10 316 -#define SRST_TIMER11 317 -#define SRST_P_INTR_ARB_PMU 318 -#define SRST_P_ALIVE_SGRF 319 - -/* cru_softrst_con20 */ -#define SRST_P_GPIO2 320 -#define SRST_P_GPIO3 321 -#define SRST_P_GPIO4 322 -#define SRST_P_GRF 323 -#define SRST_P_ALIVE_NOC 324 -#define SRST_P_WDT0 325 -#define SRST_P_WDT1 326 -#define SRST_P_INTR_ARB 327 -#define SRST_P_UPHY0_DPTX 328 -#define SRST_P_UPHY0_APB 330 -#define SRST_P_UPHY0_TCPHY 332 -#define SRST_P_UPHY1_TCPHY 333 -#define SRST_P_UPHY0_TCPDCTRL 334 -#define SRST_P_UPHY1_TCPDCTRL 335 - -/* pmu soft-reset indices */ - -/* pmu_cru_softrst_con0 */ -#define SRST_P_NOC 0 -#define SRST_P_INTMEM 1 -#define SRST_H_CM0S 2 -#define SRST_H_CM0S_NOC 3 -#define SRST_DBG_CM0S 4 -#define SRST_PO_CM0S 5 -#define SRST_P_SPI6 6 -#define SRST_SPI6 7 -#define SRST_P_TIMER_0_1 8 -#define SRST_P_TIMER_0 9 -#define SRST_P_TIMER_1 10 -#define SRST_P_UART4 11 -#define SRST_UART4 12 -#define SRST_P_WDT 13 - -/* pmu_cru_softrst_con1 */ -#define SRST_P_I2C6 16 -#define SRST_P_I2C7 17 -#define SRST_P_I2C8 18 -#define SRST_P_MAILBOX 19 -#define SRST_P_RKPWM 20 -#define SRST_P_PMUGRF 21 -#define SRST_P_SGRF 22 -#define SRST_P_GPIO0 23 -#define SRST_P_GPIO1 24 -#define SRST_P_CRU 25 -#define SRST_P_INTR 26 -#define SRST_PVTM 27 -#define SRST_I2C6 28 -#define SRST_I2C7 29 -#define SRST_I2C8 30 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/rk3399-ddr.h b/sys/gnu/dts/include/dt-bindings/clock/rk3399-ddr.h deleted file mode 100644 index ed228084496..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/rk3399-ddr.h +++ /dev/null @@ -1,56 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ - -#ifndef DT_BINDINGS_DDR_H -#define DT_BINDINGS_DDR_H - -/* - * DDR3 SDRAM Standard Speed Bins include tCK, tRCD, tRP, tRAS and tRC for - * each corresponding bin. - */ - -/* DDR3-800 (5-5-5) */ -#define DDR3_800D 0 -/* DDR3-800 (6-6-6) */ -#define DDR3_800E 1 -/* DDR3-1066 (6-6-6) */ -#define DDR3_1066E 2 -/* DDR3-1066 (7-7-7) */ -#define DDR3_1066F 3 -/* DDR3-1066 (8-8-8) */ -#define DDR3_1066G 4 -/* DDR3-1333 (7-7-7) */ -#define DDR3_1333F 5 -/* DDR3-1333 (8-8-8) */ -#define DDR3_1333G 6 -/* DDR3-1333 (9-9-9) */ -#define DDR3_1333H 7 -/* DDR3-1333 (10-10-10) */ -#define DDR3_1333J 8 -/* DDR3-1600 (8-8-8) */ -#define DDR3_1600G 9 -/* DDR3-1600 (9-9-9) */ -#define DDR3_1600H 10 -/* DDR3-1600 (10-10-10) */ -#define DDR3_1600J 11 -/* DDR3-1600 (11-11-11) */ -#define DDR3_1600K 12 -/* DDR3-1600 (10-10-10) */ -#define DDR3_1866J 13 -/* DDR3-1866 (11-11-11) */ -#define DDR3_1866K 14 -/* DDR3-1866 (12-12-12) */ -#define DDR3_1866L 15 -/* DDR3-1866 (13-13-13) */ -#define DDR3_1866M 16 -/* DDR3-2133 (11-11-11) */ -#define DDR3_2133K 17 -/* DDR3-2133 (12-12-12) */ -#define DDR3_2133L 18 -/* DDR3-2133 (13-13-13) */ -#define DDR3_2133M 19 -/* DDR3-2133 (14-14-14) */ -#define DDR3_2133N 20 -/* DDR3 ATF default */ -#define DDR3_DEFAULT 21 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/rockchip,rk808.h b/sys/gnu/dts/include/dt-bindings/clock/rockchip,rk808.h deleted file mode 100644 index 75dabfc6adc..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/rockchip,rk808.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides constants clk index RK808 pmic clkout - */ -#ifndef _CLK_ROCKCHIP_RK808 -#define _CLK_ROCKCHIP_RK808 - -/* CLOCKOUT index */ -#define RK808_CLKOUT0 0 -#define RK808_CLKOUT1 1 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/rv1108-cru.h b/sys/gnu/dts/include/dt-bindings/clock/rv1108-cru.h deleted file mode 100644 index 41d7d6080ea..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/rv1108-cru.h +++ /dev/null @@ -1,353 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright (c) 2016 Rockchip Electronics Co. Ltd. - * Author: Shawn Lin - */ - -#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H -#define _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H - -/* pll id */ -#define PLL_APLL 0 -#define PLL_DPLL 1 -#define PLL_GPLL 2 -#define ARMCLK 3 - -/* sclk gates (special clocks) */ -#define SCLK_SPI0 65 -#define SCLK_NANDC 67 -#define SCLK_SDMMC 68 -#define SCLK_SDIO 69 -#define SCLK_EMMC 71 -#define SCLK_UART0 72 -#define SCLK_UART1 73 -#define SCLK_UART2 74 -#define SCLK_I2S0 75 -#define SCLK_I2S1 76 -#define SCLK_I2S2 77 -#define SCLK_TIMER0 78 -#define SCLK_TIMER1 79 -#define SCLK_SFC 80 -#define SCLK_SDMMC_DRV 81 -#define SCLK_SDIO_DRV 82 -#define SCLK_EMMC_DRV 83 -#define SCLK_SDMMC_SAMPLE 84 -#define SCLK_SDIO_SAMPLE 85 -#define SCLK_EMMC_SAMPLE 86 -#define SCLK_VENC_CORE 87 -#define SCLK_HEVC_CORE 88 -#define SCLK_HEVC_CABAC 89 -#define SCLK_PWM0_PMU 90 -#define SCLK_I2C0_PMU 91 -#define SCLK_WIFI 92 -#define SCLK_CIFOUT 93 -#define SCLK_MIPI_CSI_OUT 94 -#define SCLK_CIF0 95 -#define SCLK_CIF1 96 -#define SCLK_CIF2 97 -#define SCLK_CIF3 98 -#define SCLK_DSP 99 -#define SCLK_DSP_IOP 100 -#define SCLK_DSP_EPP 101 -#define SCLK_DSP_EDP 102 -#define SCLK_DSP_EDAP 103 -#define SCLK_CVBS_HOST 104 -#define SCLK_HDMI_SFR 105 -#define SCLK_HDMI_CEC 106 -#define SCLK_CRYPTO 107 -#define SCLK_SPI 108 -#define SCLK_SARADC 109 -#define SCLK_TSADC 110 -#define SCLK_MAC_PRE 111 -#define SCLK_MAC 112 -#define SCLK_MAC_RX 113 -#define SCLK_MAC_REF 114 -#define SCLK_MAC_REFOUT 115 -#define SCLK_DSP_PFM 116 -#define SCLK_RGA 117 -#define SCLK_I2C1 118 -#define SCLK_I2C2 119 -#define SCLK_I2C3 120 -#define SCLK_PWM 121 -#define SCLK_ISP 122 -#define SCLK_USBPHY 123 -#define SCLK_I2S0_SRC 124 -#define SCLK_I2S1_SRC 125 -#define SCLK_I2S2_SRC 126 -#define SCLK_UART0_SRC 127 -#define SCLK_UART1_SRC 128 -#define SCLK_UART2_SRC 129 - -#define DCLK_VOP_SRC 185 -#define DCLK_HDMIPHY 186 -#define DCLK_VOP 187 - -/* aclk gates */ -#define ACLK_DMAC 192 -#define ACLK_PRE 193 -#define ACLK_CORE 194 -#define ACLK_ENMCORE 195 -#define ACLK_RKVENC 196 -#define ACLK_RKVDEC 197 -#define ACLK_VPU 198 -#define ACLK_CIF0 199 -#define ACLK_VIO0 200 -#define ACLK_VIO1 201 -#define ACLK_VOP 202 -#define ACLK_IEP 203 -#define ACLK_RGA 204 -#define ACLK_ISP 205 -#define ACLK_CIF1 206 -#define ACLK_CIF2 207 -#define ACLK_CIF3 208 -#define ACLK_PERI 209 -#define ACLK_GMAC 210 - -/* pclk gates */ -#define PCLK_GPIO1 256 -#define PCLK_GPIO2 257 -#define PCLK_GPIO3 258 -#define PCLK_GRF 259 -#define PCLK_I2C1 260 -#define PCLK_I2C2 261 -#define PCLK_I2C3 262 -#define PCLK_SPI 263 -#define PCLK_SFC 264 -#define PCLK_UART0 265 -#define PCLK_UART1 266 -#define PCLK_UART2 267 -#define PCLK_TSADC 268 -#define PCLK_PWM 269 -#define PCLK_TIMER 270 -#define PCLK_PERI 271 -#define PCLK_GPIO0_PMU 272 -#define PCLK_I2C0_PMU 273 -#define PCLK_PWM0_PMU 274 -#define PCLK_ISP 275 -#define PCLK_VIO 276 -#define PCLK_MIPI_DSI 277 -#define PCLK_HDMI_CTRL 278 -#define PCLK_SARADC 279 -#define PCLK_DSP_CFG 280 -#define PCLK_BUS 281 -#define PCLK_EFUSE0 282 -#define PCLK_EFUSE1 283 -#define PCLK_WDT 284 -#define PCLK_GMAC 285 - -/* hclk gates */ -#define HCLK_I2S0_8CH 320 -#define HCLK_I2S1_2CH 321 -#define HCLK_I2S2_2CH 322 -#define HCLK_NANDC 323 -#define HCLK_SDMMC 324 -#define HCLK_SDIO 325 -#define HCLK_EMMC 326 -#define HCLK_PERI 327 -#define HCLK_SFC 328 -#define HCLK_RKVENC 329 -#define HCLK_RKVDEC 330 -#define HCLK_CIF0 331 -#define HCLK_VIO 332 -#define HCLK_VOP 333 -#define HCLK_IEP 334 -#define HCLK_RGA 335 -#define HCLK_ISP 336 -#define HCLK_CRYPTO_MST 337 -#define HCLK_CRYPTO_SLV 338 -#define HCLK_HOST0 339 -#define HCLK_OTG 340 -#define HCLK_CIF1 341 -#define HCLK_CIF2 342 -#define HCLK_CIF3 343 -#define HCLK_BUS 344 -#define HCLK_VPU 345 - -#define CLK_NR_CLKS (HCLK_VPU + 1) - -/* reset id */ -#define SRST_CORE_PO_AD 0 -#define SRST_CORE_AD 1 -#define SRST_L2_AD 2 -#define SRST_CPU_NIU_AD 3 -#define SRST_CORE_PO 4 -#define SRST_CORE 5 -#define SRST_L2 6 -#define SRST_CORE_DBG 8 -#define PRST_DBG 9 -#define RST_DAP 10 -#define PRST_DBG_NIU 11 -#define ARST_STRC_SYS_AD 15 - -#define SRST_DDRPHY_CLKDIV 16 -#define SRST_DDRPHY 17 -#define PRST_DDRPHY 18 -#define PRST_HDMIPHY 19 -#define PRST_VDACPHY 20 -#define PRST_VADCPHY 21 -#define PRST_MIPI_CSI_PHY 22 -#define PRST_MIPI_DSI_PHY 23 -#define PRST_ACODEC 24 -#define ARST_BUS_NIU 25 -#define PRST_TOP_NIU 26 -#define ARST_INTMEM 27 -#define HRST_ROM 28 -#define ARST_DMAC 29 -#define SRST_MSCH_NIU 30 -#define PRST_MSCH_NIU 31 - -#define PRST_DDRUPCTL 32 -#define NRST_DDRUPCTL 33 -#define PRST_DDRMON 34 -#define HRST_I2S0_8CH 35 -#define MRST_I2S0_8CH 36 -#define HRST_I2S1_2CH 37 -#define MRST_IS21_2CH 38 -#define HRST_I2S2_2CH 39 -#define MRST_I2S2_2CH 40 -#define HRST_CRYPTO 41 -#define SRST_CRYPTO 42 -#define PRST_SPI 43 -#define SRST_SPI 44 -#define PRST_UART0 45 -#define PRST_UART1 46 -#define PRST_UART2 47 - -#define SRST_UART0 48 -#define SRST_UART1 49 -#define SRST_UART2 50 -#define PRST_I2C1 51 -#define PRST_I2C2 52 -#define PRST_I2C3 53 -#define SRST_I2C1 54 -#define SRST_I2C2 55 -#define SRST_I2C3 56 -#define PRST_PWM1 58 -#define SRST_PWM1 60 -#define PRST_WDT 61 -#define PRST_GPIO1 62 -#define PRST_GPIO2 63 - -#define PRST_GPIO3 64 -#define PRST_GRF 65 -#define PRST_EFUSE 66 -#define PRST_EFUSE512 67 -#define PRST_TIMER0 68 -#define SRST_TIMER0 69 -#define SRST_TIMER1 70 -#define PRST_TSADC 71 -#define SRST_TSADC 72 -#define PRST_SARADC 73 -#define SRST_SARADC 74 -#define HRST_SYSBUS 75 -#define PRST_USBGRF 76 - -#define ARST_PERIPH_NIU 80 -#define HRST_PERIPH_NIU 81 -#define PRST_PERIPH_NIU 82 -#define HRST_PERIPH 83 -#define HRST_SDMMC 84 -#define HRST_SDIO 85 -#define HRST_EMMC 86 -#define HRST_NANDC 87 -#define NRST_NANDC 88 -#define HRST_SFC 89 -#define SRST_SFC 90 -#define ARST_GMAC 91 -#define HRST_OTG 92 -#define SRST_OTG 93 -#define SRST_OTG_ADP 94 -#define HRST_HOST0 95 - -#define HRST_HOST0_AUX 96 -#define HRST_HOST0_ARB 97 -#define SRST_HOST0_EHCIPHY 98 -#define SRST_HOST0_UTMI 99 -#define SRST_USBPOR 100 -#define SRST_UTMI0 101 -#define SRST_UTMI1 102 - -#define ARST_VIO0_NIU 102 -#define ARST_VIO1_NIU 103 -#define HRST_VIO_NIU 104 -#define PRST_VIO_NIU 105 -#define ARST_VOP 106 -#define HRST_VOP 107 -#define DRST_VOP 108 -#define ARST_IEP 109 -#define HRST_IEP 110 -#define ARST_RGA 111 -#define HRST_RGA 112 -#define SRST_RGA 113 -#define PRST_CVBS 114 -#define PRST_HDMI 115 -#define SRST_HDMI 116 -#define PRST_MIPI_DSI 117 - -#define ARST_ISP_NIU 118 -#define HRST_ISP_NIU 119 -#define HRST_ISP 120 -#define SRST_ISP 121 -#define ARST_VIP0 122 -#define HRST_VIP0 123 -#define PRST_VIP0 124 -#define ARST_VIP1 125 -#define HRST_VIP1 126 -#define PRST_VIP1 127 -#define ARST_VIP2 128 -#define HRST_VIP2 129 -#define PRST_VIP2 120 -#define ARST_VIP3 121 -#define HRST_VIP3 122 -#define PRST_VIP4 123 - -#define PRST_CIF1TO4 124 -#define SRST_CVBS_CLK 125 -#define HRST_CVBS 126 - -#define ARST_VPU_NIU 140 -#define HRST_VPU_NIU 141 -#define ARST_VPU 142 -#define HRST_VPU 143 -#define ARST_RKVDEC_NIU 144 -#define HRST_RKVDEC_NIU 145 -#define ARST_RKVDEC 146 -#define HRST_RKVDEC 147 -#define SRST_RKVDEC_CABAC 148 -#define SRST_RKVDEC_CORE 149 -#define ARST_RKVENC_NIU 150 -#define HRST_RKVENC_NIU 151 -#define ARST_RKVENC 152 -#define HRST_RKVENC 153 -#define SRST_RKVENC_CORE 154 - -#define SRST_DSP_CORE 156 -#define SRST_DSP_SYS 157 -#define SRST_DSP_GLOBAL 158 -#define SRST_DSP_OECM 159 -#define PRST_DSP_IOP_NIU 160 -#define ARST_DSP_EPP_NIU 161 -#define ARST_DSP_EDP_NIU 162 -#define PRST_DSP_DBG_NIU 163 -#define PRST_DSP_CFG_NIU 164 -#define PRST_DSP_GRF 165 -#define PRST_DSP_MAILBOX 166 -#define PRST_DSP_INTC 167 -#define PRST_DSP_PFM_MON 169 -#define SRST_DSP_PFM_MON 170 -#define ARST_DSP_EDAP_NIU 171 - -#define SRST_PMU 172 -#define SRST_PMU_I2C0 173 -#define PRST_PMU_I2C0 174 -#define PRST_PMU_GPIO0 175 -#define PRST_PMU_INTMEM 176 -#define PRST_PMU_PWM0 177 -#define SRST_PMU_PWM0 178 -#define PRST_PMU_GRF 179 -#define SRST_PMU_NIU 180 -#define SRST_PMU_PVTM 181 -#define ARST_DSP_EDP_PERF 184 -#define ARST_DSP_EPP_PERF 185 - -#endif /* _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/s3c2410.h b/sys/gnu/dts/include/dt-bindings/clock/s3c2410.h deleted file mode 100644 index 0fb65c3f2f5..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/s3c2410.h +++ /dev/null @@ -1,59 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2013 Heiko Stuebner - * - * Device Tree binding constants clock controllers of Samsung S3C2410 and later. - */ - -#ifndef _DT_BINDINGS_CLOCK_SAMSUNG_S3C2410_CLOCK_H -#define _DT_BINDINGS_CLOCK_SAMSUNG_S3C2410_CLOCK_H - -/* - * Let each exported clock get a unique index, which is used on DT-enabled - * platforms to lookup the clock from a clock specifier. These indices are - * therefore considered an ABI and so must not be changed. This implies - * that new clocks should be added either in free spaces between clock groups - * or at the end. - */ - -/* Core clocks. */ - -/* id 1 is reserved */ -#define MPLL 2 -#define UPLL 3 -#define FCLK 4 -#define HCLK 5 -#define PCLK 6 -#define UCLK 7 -#define ARMCLK 8 - -/* pclk-gates */ -#define PCLK_UART0 16 -#define PCLK_UART1 17 -#define PCLK_UART2 18 -#define PCLK_I2C 19 -#define PCLK_SDI 20 -#define PCLK_SPI 21 -#define PCLK_ADC 22 -#define PCLK_AC97 23 -#define PCLK_I2S 24 -#define PCLK_PWM 25 -#define PCLK_RTC 26 -#define PCLK_GPIO 27 - - -/* hclk-gates */ -#define HCLK_LCD 32 -#define HCLK_USBH 33 -#define HCLK_USBD 34 -#define HCLK_NAND 35 -#define HCLK_CAM 36 - - -#define CAMIF 40 - - -/* Total number of clocks. */ -#define NR_CLKS (CAMIF + 1) - -#endif /* _DT_BINDINGS_CLOCK_SAMSUNG_S3C2443_CLOCK_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/s3c2412.h b/sys/gnu/dts/include/dt-bindings/clock/s3c2412.h deleted file mode 100644 index b4656156cc0..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/s3c2412.h +++ /dev/null @@ -1,70 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2013 Heiko Stuebner - * - * Device Tree binding constants clock controllers of Samsung S3C2412. - */ - -#ifndef _DT_BINDINGS_CLOCK_SAMSUNG_S3C2412_CLOCK_H -#define _DT_BINDINGS_CLOCK_SAMSUNG_S3C2412_CLOCK_H - -/* - * Let each exported clock get a unique index, which is used on DT-enabled - * platforms to lookup the clock from a clock specifier. These indices are - * therefore considered an ABI and so must not be changed. This implies - * that new clocks should be added either in free spaces between clock groups - * or at the end. - */ - -/* Core clocks. */ - -/* id 1 is reserved */ -#define MPLL 2 -#define UPLL 3 -#define MDIVCLK 4 -#define MSYSCLK 5 -#define USYSCLK 6 -#define HCLK 7 -#define PCLK 8 -#define ARMDIV 9 -#define ARMCLK 10 - - -/* Special clocks */ -#define SCLK_CAM 16 -#define SCLK_UART 17 -#define SCLK_I2S 18 -#define SCLK_USBD 19 -#define SCLK_USBH 20 - -/* pclk-gates */ -#define PCLK_WDT 32 -#define PCLK_SPI 33 -#define PCLK_I2S 34 -#define PCLK_I2C 35 -#define PCLK_ADC 36 -#define PCLK_RTC 37 -#define PCLK_GPIO 38 -#define PCLK_UART2 39 -#define PCLK_UART1 40 -#define PCLK_UART0 41 -#define PCLK_SDI 42 -#define PCLK_PWM 43 -#define PCLK_USBD 44 - -/* hclk-gates */ -#define HCLK_HALF 48 -#define HCLK_X2 49 -#define HCLK_SDRAM 50 -#define HCLK_USBH 51 -#define HCLK_LCD 52 -#define HCLK_NAND 53 -#define HCLK_DMA3 54 -#define HCLK_DMA2 55 -#define HCLK_DMA1 56 -#define HCLK_DMA0 57 - -/* Total number of clocks. */ -#define NR_CLKS (HCLK_DMA0 + 1) - -#endif /* _DT_BINDINGS_CLOCK_SAMSUNG_S3C2412_CLOCK_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/s3c2443.h b/sys/gnu/dts/include/dt-bindings/clock/s3c2443.h deleted file mode 100644 index a9d2f105d53..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/s3c2443.h +++ /dev/null @@ -1,91 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2013 Heiko Stuebner - * - * Device Tree binding constants clock controllers of Samsung S3C2443 and later. - */ - -#ifndef _DT_BINDINGS_CLOCK_SAMSUNG_S3C2443_CLOCK_H -#define _DT_BINDINGS_CLOCK_SAMSUNG_S3C2443_CLOCK_H - -/* - * Let each exported clock get a unique index, which is used on DT-enabled - * platforms to lookup the clock from a clock specifier. These indices are - * therefore considered an ABI and so must not be changed. This implies - * that new clocks should be added either in free spaces between clock groups - * or at the end. - */ - -/* Core clocks. */ -#define MSYSCLK 1 -#define ESYSCLK 2 -#define ARMDIV 3 -#define ARMCLK 4 -#define HCLK 5 -#define PCLK 6 -#define MPLL 7 -#define EPLL 8 - -/* Special clocks */ -#define SCLK_HSSPI0 16 -#define SCLK_FIMD 17 -#define SCLK_I2S0 18 -#define SCLK_I2S1 19 -#define SCLK_HSMMC1 20 -#define SCLK_HSMMC_EXT 21 -#define SCLK_CAM 22 -#define SCLK_UART 23 -#define SCLK_USBH 24 - -/* Muxes */ -#define MUX_HSSPI0 32 -#define MUX_HSSPI1 33 -#define MUX_HSMMC0 34 -#define MUX_HSMMC1 35 - -/* hclk-gates */ -#define HCLK_DMA0 48 -#define HCLK_DMA1 49 -#define HCLK_DMA2 50 -#define HCLK_DMA3 51 -#define HCLK_DMA4 52 -#define HCLK_DMA5 53 -#define HCLK_DMA6 54 -#define HCLK_DMA7 55 -#define HCLK_CAM 56 -#define HCLK_LCD 57 -#define HCLK_USBH 58 -#define HCLK_USBD 59 -#define HCLK_IROM 60 -#define HCLK_HSMMC0 61 -#define HCLK_HSMMC1 62 -#define HCLK_CFC 63 -#define HCLK_SSMC 64 -#define HCLK_DRAM 65 -#define HCLK_2D 66 - -/* pclk-gates */ -#define PCLK_UART0 72 -#define PCLK_UART1 73 -#define PCLK_UART2 74 -#define PCLK_UART3 75 -#define PCLK_I2C0 76 -#define PCLK_SDI 77 -#define PCLK_SPI0 78 -#define PCLK_ADC 79 -#define PCLK_AC97 80 -#define PCLK_I2S0 81 -#define PCLK_PWM 82 -#define PCLK_WDT 83 -#define PCLK_RTC 84 -#define PCLK_GPIO 85 -#define PCLK_SPI1 86 -#define PCLK_CHIPID 87 -#define PCLK_I2C1 88 -#define PCLK_I2S1 89 -#define PCLK_PCM 90 - -/* Total number of clocks. */ -#define NR_CLKS (PCLK_PCM + 1) - -#endif /* _DT_BINDINGS_CLOCK_SAMSUNG_S3C2443_CLOCK_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/s5pv210-audss.h b/sys/gnu/dts/include/dt-bindings/clock/s5pv210-audss.h deleted file mode 100644 index 84d62fe7a73..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/s5pv210-audss.h +++ /dev/null @@ -1,31 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2014 Tomasz Figa - * - * This header provides constants for Samsung audio subsystem - * clock controller. - * - * The constants defined in this header are being used in dts - * and s5pv210 audss driver. - */ - -#ifndef _DT_BINDINGS_CLOCK_S5PV210_AUDSS_H -#define _DT_BINDINGS_CLOCK_S5PV210_AUDSS_H - -#define CLK_MOUT_AUDSS 0 -#define CLK_MOUT_I2S_A 1 - -#define CLK_DOUT_AUD_BUS 2 -#define CLK_DOUT_I2S_A 3 - -#define CLK_I2S 4 -#define CLK_HCLK_I2S 5 -#define CLK_HCLK_UART 6 -#define CLK_HCLK_HWA 7 -#define CLK_HCLK_DMA 8 -#define CLK_HCLK_BUF 9 -#define CLK_HCLK_RP 10 - -#define AUDSS_MAX_CLKS 11 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/s5pv210.h b/sys/gnu/dts/include/dt-bindings/clock/s5pv210.h deleted file mode 100644 index c36699c2fa3..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/s5pv210.h +++ /dev/null @@ -1,236 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2013 Samsung Electronics Co., Ltd. - * Author: Mateusz Krawczuk - * - * Device Tree binding constants for Samsung S5PV210 clock controller. - */ - -#ifndef _DT_BINDINGS_CLOCK_S5PV210_H -#define _DT_BINDINGS_CLOCK_S5PV210_H - -/* Core clocks. */ -#define FIN_PLL 1 -#define FOUT_APLL 2 -#define FOUT_MPLL 3 -#define FOUT_EPLL 4 -#define FOUT_VPLL 5 - -/* Muxes. */ -#define MOUT_FLASH 6 -#define MOUT_PSYS 7 -#define MOUT_DSYS 8 -#define MOUT_MSYS 9 -#define MOUT_VPLL 10 -#define MOUT_EPLL 11 -#define MOUT_MPLL 12 -#define MOUT_APLL 13 -#define MOUT_VPLLSRC 14 -#define MOUT_CSIS 15 -#define MOUT_FIMD 16 -#define MOUT_CAM1 17 -#define MOUT_CAM0 18 -#define MOUT_DAC 19 -#define MOUT_MIXER 20 -#define MOUT_HDMI 21 -#define MOUT_G2D 22 -#define MOUT_MFC 23 -#define MOUT_G3D 24 -#define MOUT_FIMC2 25 -#define MOUT_FIMC1 26 -#define MOUT_FIMC0 27 -#define MOUT_UART3 28 -#define MOUT_UART2 29 -#define MOUT_UART1 30 -#define MOUT_UART0 31 -#define MOUT_MMC3 32 -#define MOUT_MMC2 33 -#define MOUT_MMC1 34 -#define MOUT_MMC0 35 -#define MOUT_PWM 36 -#define MOUT_SPI0 37 -#define MOUT_SPI1 38 -#define MOUT_DMC0 39 -#define MOUT_PWI 40 -#define MOUT_HPM 41 -#define MOUT_SPDIF 42 -#define MOUT_AUDIO2 43 -#define MOUT_AUDIO1 44 -#define MOUT_AUDIO0 45 - -/* Dividers. */ -#define DOUT_PCLKP 46 -#define DOUT_HCLKP 47 -#define DOUT_PCLKD 48 -#define DOUT_HCLKD 49 -#define DOUT_PCLKM 50 -#define DOUT_HCLKM 51 -#define DOUT_A2M 52 -#define DOUT_APLL 53 -#define DOUT_CSIS 54 -#define DOUT_FIMD 55 -#define DOUT_CAM1 56 -#define DOUT_CAM0 57 -#define DOUT_TBLK 58 -#define DOUT_G2D 59 -#define DOUT_MFC 60 -#define DOUT_G3D 61 -#define DOUT_FIMC2 62 -#define DOUT_FIMC1 63 -#define DOUT_FIMC0 64 -#define DOUT_UART3 65 -#define DOUT_UART2 66 -#define DOUT_UART1 67 -#define DOUT_UART0 68 -#define DOUT_MMC3 69 -#define DOUT_MMC2 70 -#define DOUT_MMC1 71 -#define DOUT_MMC0 72 -#define DOUT_PWM 73 -#define DOUT_SPI1 74 -#define DOUT_SPI0 75 -#define DOUT_DMC0 76 -#define DOUT_PWI 77 -#define DOUT_HPM 78 -#define DOUT_COPY 79 -#define DOUT_FLASH 80 -#define DOUT_AUDIO2 81 -#define DOUT_AUDIO1 82 -#define DOUT_AUDIO0 83 -#define DOUT_DPM 84 -#define DOUT_DVSEM 85 - -/* Gates */ -#define SCLK_FIMC 86 -#define CLK_CSIS 87 -#define CLK_ROTATOR 88 -#define CLK_FIMC2 89 -#define CLK_FIMC1 90 -#define CLK_FIMC0 91 -#define CLK_MFC 92 -#define CLK_G2D 93 -#define CLK_G3D 94 -#define CLK_IMEM 95 -#define CLK_PDMA1 96 -#define CLK_PDMA0 97 -#define CLK_MDMA 98 -#define CLK_DMC1 99 -#define CLK_DMC0 100 -#define CLK_NFCON 101 -#define CLK_SROMC 102 -#define CLK_CFCON 103 -#define CLK_NANDXL 104 -#define CLK_USB_HOST 105 -#define CLK_USB_OTG 106 -#define CLK_HDMI 107 -#define CLK_TVENC 108 -#define CLK_MIXER 109 -#define CLK_VP 110 -#define CLK_DSIM 111 -#define CLK_FIMD 112 -#define CLK_TZIC3 113 -#define CLK_TZIC2 114 -#define CLK_TZIC1 115 -#define CLK_TZIC0 116 -#define CLK_VIC3 117 -#define CLK_VIC2 118 -#define CLK_VIC1 119 -#define CLK_VIC0 120 -#define CLK_TSI 121 -#define CLK_HSMMC3 122 -#define CLK_HSMMC2 123 -#define CLK_HSMMC1 124 -#define CLK_HSMMC0 125 -#define CLK_JTAG 126 -#define CLK_MODEMIF 127 -#define CLK_CORESIGHT 128 -#define CLK_SDM 129 -#define CLK_SECSS 130 -#define CLK_PCM2 131 -#define CLK_PCM1 132 -#define CLK_PCM0 133 -#define CLK_SYSCON 134 -#define CLK_GPIO 135 -#define CLK_TSADC 136 -#define CLK_PWM 137 -#define CLK_WDT 138 -#define CLK_KEYIF 139 -#define CLK_UART3 140 -#define CLK_UART2 141 -#define CLK_UART1 142 -#define CLK_UART0 143 -#define CLK_SYSTIMER 144 -#define CLK_RTC 145 -#define CLK_SPI1 146 -#define CLK_SPI0 147 -#define CLK_I2C_HDMI_PHY 148 -#define CLK_I2C1 149 -#define CLK_I2C2 150 -#define CLK_I2C0 151 -#define CLK_I2S1 152 -#define CLK_I2S2 153 -#define CLK_I2S0 154 -#define CLK_AC97 155 -#define CLK_SPDIF 156 -#define CLK_TZPC3 157 -#define CLK_TZPC2 158 -#define CLK_TZPC1 159 -#define CLK_TZPC0 160 -#define CLK_SECKEY 161 -#define CLK_IEM_APC 162 -#define CLK_IEM_IEC 163 -#define CLK_CHIPID 164 -#define CLK_JPEG 163 - -/* Special clocks*/ -#define SCLK_PWI 164 -#define SCLK_SPDIF 165 -#define SCLK_AUDIO2 166 -#define SCLK_AUDIO1 167 -#define SCLK_AUDIO0 168 -#define SCLK_PWM 169 -#define SCLK_SPI1 170 -#define SCLK_SPI0 171 -#define SCLK_UART3 172 -#define SCLK_UART2 173 -#define SCLK_UART1 174 -#define SCLK_UART0 175 -#define SCLK_MMC3 176 -#define SCLK_MMC2 177 -#define SCLK_MMC1 178 -#define SCLK_MMC0 179 -#define SCLK_FINVPLL 180 -#define SCLK_CSIS 181 -#define SCLK_FIMD 182 -#define SCLK_CAM1 183 -#define SCLK_CAM0 184 -#define SCLK_DAC 185 -#define SCLK_MIXER 186 -#define SCLK_HDMI 187 -#define SCLK_FIMC2 188 -#define SCLK_FIMC1 189 -#define SCLK_FIMC0 190 -#define SCLK_HDMI27M 191 -#define SCLK_HDMIPHY 192 -#define SCLK_USBPHY0 193 -#define SCLK_USBPHY1 194 - -/* S5P6442-specific clocks */ -#define MOUT_D0SYNC 195 -#define MOUT_D1SYNC 196 -#define DOUT_MIXER 197 -#define CLK_ETB 198 -#define CLK_ETM 199 - -/* CLKOUT */ -#define FOUT_APLL_CLKOUT 200 -#define FOUT_MPLL_CLKOUT 201 -#define DOUT_APLL_CLKOUT 202 -#define MOUT_CLKSEL 203 -#define DOUT_CLKOUT 204 -#define MOUT_CLKOUT 205 - -/* Total number of clocks. */ -#define NR_CLKS 206 - -#endif /* _DT_BINDINGS_CLOCK_S5PV210_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/samsung,s2mps11.h b/sys/gnu/dts/include/dt-bindings/clock/samsung,s2mps11.h deleted file mode 100644 index 5ece35d429f..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/samsung,s2mps11.h +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2015 Markus Reichl - * - * Device Tree binding constants clocks for the Samsung S2MPS11 PMIC. - */ - -#ifndef _DT_BINDINGS_CLOCK_SAMSUNG_S2MPS11_CLOCK_H -#define _DT_BINDINGS_CLOCK_SAMSUNG_S2MPS11_CLOCK_H - -/* Fixed rate clocks. */ - -#define S2MPS11_CLK_AP 0 -#define S2MPS11_CLK_CP 1 -#define S2MPS11_CLK_BT 2 - -/* Total number of clocks. */ -#define S2MPS11_CLKS_NUM (S2MPS11_CLK_BT + 1) - -#endif /* _DT_BINDINGS_CLOCK_SAMSUNG_S2MPS11_CLOCK_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/samsung,s3c64xx-clock.h b/sys/gnu/dts/include/dt-bindings/clock/samsung,s3c64xx-clock.h deleted file mode 100644 index 19d233f37e2..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/samsung,s3c64xx-clock.h +++ /dev/null @@ -1,175 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2013 Tomasz Figa - * - * Device Tree binding constants for Samsung S3C64xx clock controller. - */ - -#ifndef _DT_BINDINGS_CLOCK_SAMSUNG_S3C64XX_CLOCK_H -#define _DT_BINDINGS_CLOCK_SAMSUNG_S3C64XX_CLOCK_H - -/* - * Let each exported clock get a unique index, which is used on DT-enabled - * platforms to lookup the clock from a clock specifier. These indices are - * therefore considered an ABI and so must not be changed. This implies - * that new clocks should be added either in free spaces between clock groups - * or at the end. - */ - -/* Core clocks. */ -#define CLK27M 1 -#define CLK48M 2 -#define FOUT_APLL 3 -#define FOUT_MPLL 4 -#define FOUT_EPLL 5 -#define ARMCLK 6 -#define HCLKX2 7 -#define HCLK 8 -#define PCLK 9 - -/* HCLK bus clocks. */ -#define HCLK_3DSE 16 -#define HCLK_UHOST 17 -#define HCLK_SECUR 18 -#define HCLK_SDMA1 19 -#define HCLK_SDMA0 20 -#define HCLK_IROM 21 -#define HCLK_DDR1 22 -#define HCLK_MEM1 23 -#define HCLK_MEM0 24 -#define HCLK_USB 25 -#define HCLK_HSMMC2 26 -#define HCLK_HSMMC1 27 -#define HCLK_HSMMC0 28 -#define HCLK_MDP 29 -#define HCLK_DHOST 30 -#define HCLK_IHOST 31 -#define HCLK_DMA1 32 -#define HCLK_DMA0 33 -#define HCLK_JPEG 34 -#define HCLK_CAMIF 35 -#define HCLK_SCALER 36 -#define HCLK_2D 37 -#define HCLK_TV 38 -#define HCLK_POST0 39 -#define HCLK_ROT 40 -#define HCLK_LCD 41 -#define HCLK_TZIC 42 -#define HCLK_INTC 43 -#define HCLK_MFC 44 -#define HCLK_DDR0 45 - -/* PCLK bus clocks. */ -#define PCLK_IIC1 48 -#define PCLK_IIS2 49 -#define PCLK_SKEY 50 -#define PCLK_CHIPID 51 -#define PCLK_SPI1 52 -#define PCLK_SPI0 53 -#define PCLK_HSIRX 54 -#define PCLK_HSITX 55 -#define PCLK_GPIO 56 -#define PCLK_IIC0 57 -#define PCLK_IIS1 58 -#define PCLK_IIS0 59 -#define PCLK_AC97 60 -#define PCLK_TZPC 61 -#define PCLK_TSADC 62 -#define PCLK_KEYPAD 63 -#define PCLK_IRDA 64 -#define PCLK_PCM1 65 -#define PCLK_PCM0 66 -#define PCLK_PWM 67 -#define PCLK_RTC 68 -#define PCLK_WDT 69 -#define PCLK_UART3 70 -#define PCLK_UART2 71 -#define PCLK_UART1 72 -#define PCLK_UART0 73 -#define PCLK_MFC 74 - -/* Special clocks. */ -#define SCLK_UHOST 80 -#define SCLK_MMC2_48 81 -#define SCLK_MMC1_48 82 -#define SCLK_MMC0_48 83 -#define SCLK_MMC2 84 -#define SCLK_MMC1 85 -#define SCLK_MMC0 86 -#define SCLK_SPI1_48 87 -#define SCLK_SPI0_48 88 -#define SCLK_SPI1 89 -#define SCLK_SPI0 90 -#define SCLK_DAC27 91 -#define SCLK_TV27 92 -#define SCLK_SCALER27 93 -#define SCLK_SCALER 94 -#define SCLK_LCD27 95 -#define SCLK_LCD 96 -#define SCLK_FIMC 97 -#define SCLK_POST0_27 98 -#define SCLK_AUDIO2 99 -#define SCLK_POST0 100 -#define SCLK_AUDIO1 101 -#define SCLK_AUDIO0 102 -#define SCLK_SECUR 103 -#define SCLK_IRDA 104 -#define SCLK_UART 105 -#define SCLK_MFC 106 -#define SCLK_CAM 107 -#define SCLK_JPEG 108 -#define SCLK_ONENAND 109 - -/* MEM0 bus clocks - S3C6410-specific. */ -#define MEM0_CFCON 112 -#define MEM0_ONENAND1 113 -#define MEM0_ONENAND0 114 -#define MEM0_NFCON 115 -#define MEM0_SROM 116 - -/* Muxes. */ -#define MOUT_APLL 128 -#define MOUT_MPLL 129 -#define MOUT_EPLL 130 -#define MOUT_MFC 131 -#define MOUT_AUDIO0 132 -#define MOUT_AUDIO1 133 -#define MOUT_UART 134 -#define MOUT_SPI0 135 -#define MOUT_SPI1 136 -#define MOUT_MMC0 137 -#define MOUT_MMC1 138 -#define MOUT_MMC2 139 -#define MOUT_UHOST 140 -#define MOUT_IRDA 141 -#define MOUT_LCD 142 -#define MOUT_SCALER 143 -#define MOUT_DAC27 144 -#define MOUT_TV27 145 -#define MOUT_AUDIO2 146 - -/* Dividers. */ -#define DOUT_MPLL 160 -#define DOUT_SECUR 161 -#define DOUT_CAM 162 -#define DOUT_JPEG 163 -#define DOUT_MFC 164 -#define DOUT_MMC0 165 -#define DOUT_MMC1 166 -#define DOUT_MMC2 167 -#define DOUT_LCD 168 -#define DOUT_SCALER 169 -#define DOUT_UHOST 170 -#define DOUT_SPI0 171 -#define DOUT_SPI1 172 -#define DOUT_AUDIO0 173 -#define DOUT_AUDIO1 174 -#define DOUT_UART 175 -#define DOUT_IRDA 176 -#define DOUT_FIMC 177 -#define DOUT_AUDIO2 178 - -/* Total number of clocks. */ -#define NR_CLKS (DOUT_AUDIO2 + 1) - -#endif /* _DT_BINDINGS_CLOCK_SAMSUNG_S3C64XX_CLOCK_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/sh73a0-clock.h b/sys/gnu/dts/include/dt-bindings/clock/sh73a0-clock.h deleted file mode 100644 index 5b544ad7f9b..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/sh73a0-clock.h +++ /dev/null @@ -1,82 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright 2014 Ulrich Hecht - */ - -#ifndef __DT_BINDINGS_CLOCK_SH73A0_H__ -#define __DT_BINDINGS_CLOCK_SH73A0_H__ - -/* CPG */ -#define SH73A0_CLK_MAIN 0 -#define SH73A0_CLK_PLL0 1 -#define SH73A0_CLK_PLL1 2 -#define SH73A0_CLK_PLL2 3 -#define SH73A0_CLK_PLL3 4 -#define SH73A0_CLK_DSI0PHY 5 -#define SH73A0_CLK_DSI1PHY 6 -#define SH73A0_CLK_ZG 7 -#define SH73A0_CLK_M3 8 -#define SH73A0_CLK_B 9 -#define SH73A0_CLK_M1 10 -#define SH73A0_CLK_M2 11 -#define SH73A0_CLK_Z 12 -#define SH73A0_CLK_ZX 13 -#define SH73A0_CLK_HP 14 - -/* MSTP0 */ -#define SH73A0_CLK_IIC2 1 -#define SH73A0_CLK_MSIOF0 0 - -/* MSTP1 */ -#define SH73A0_CLK_CEU1 29 -#define SH73A0_CLK_CSI2_RX1 28 -#define SH73A0_CLK_CEU0 27 -#define SH73A0_CLK_CSI2_RX0 26 -#define SH73A0_CLK_TMU0 25 -#define SH73A0_CLK_DSITX0 18 -#define SH73A0_CLK_IIC0 16 -#define SH73A0_CLK_SGX 12 -#define SH73A0_CLK_LCDC0 0 - -/* MSTP2 */ -#define SH73A0_CLK_SCIFA7 19 -#define SH73A0_CLK_SY_DMAC 18 -#define SH73A0_CLK_MP_DMAC 17 -#define SH73A0_CLK_MSIOF3 15 -#define SH73A0_CLK_MSIOF1 8 -#define SH73A0_CLK_SCIFA5 7 -#define SH73A0_CLK_SCIFB 6 -#define SH73A0_CLK_MSIOF2 5 -#define SH73A0_CLK_SCIFA0 4 -#define SH73A0_CLK_SCIFA1 3 -#define SH73A0_CLK_SCIFA2 2 -#define SH73A0_CLK_SCIFA3 1 -#define SH73A0_CLK_SCIFA4 0 - -/* MSTP3 */ -#define SH73A0_CLK_SCIFA6 31 -#define SH73A0_CLK_CMT1 29 -#define SH73A0_CLK_FSI 28 -#define SH73A0_CLK_IRDA 25 -#define SH73A0_CLK_IIC1 23 -#define SH73A0_CLK_USB 22 -#define SH73A0_CLK_FLCTL 15 -#define SH73A0_CLK_SDHI0 14 -#define SH73A0_CLK_SDHI1 13 -#define SH73A0_CLK_MMCIF0 12 -#define SH73A0_CLK_SDHI2 11 -#define SH73A0_CLK_TPU0 4 -#define SH73A0_CLK_TPU1 3 -#define SH73A0_CLK_TPU2 2 -#define SH73A0_CLK_TPU3 1 -#define SH73A0_CLK_TPU4 0 - -/* MSTP4 */ -#define SH73A0_CLK_IIC3 11 -#define SH73A0_CLK_IIC4 10 -#define SH73A0_CLK_KEYSC 3 - -/* MSTP5 */ -#define SH73A0_CLK_INTCA0 8 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/sifive-fu540-prci.h b/sys/gnu/dts/include/dt-bindings/clock/sifive-fu540-prci.h deleted file mode 100644 index 3b21d0522c9..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/sifive-fu540-prci.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ -/* - * Copyright (C) 2018-2019 SiFive, Inc. - * Wesley Terpstra - * Paul Walmsley - */ - -#ifndef __DT_BINDINGS_CLOCK_SIFIVE_FU540_PRCI_H -#define __DT_BINDINGS_CLOCK_SIFIVE_FU540_PRCI_H - -/* Clock indexes for use by Device Tree data and the PRCI driver */ - -#define PRCI_CLK_COREPLL 0 -#define PRCI_CLK_DDRPLL 1 -#define PRCI_CLK_GEMGXLPLL 2 -#define PRCI_CLK_TLCLK 3 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/sprd,sc9860-clk.h b/sys/gnu/dts/include/dt-bindings/clock/sprd,sc9860-clk.h deleted file mode 100644 index f2ab4631df0..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/sprd,sc9860-clk.h +++ /dev/null @@ -1,423 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// -// Spreadtrum SC9860 platform clocks -// -// Copyright (C) 2017, Spreadtrum Communications Inc. - -#ifndef _DT_BINDINGS_CLK_SC9860_H_ -#define _DT_BINDINGS_CLK_SC9860_H_ - -#define CLK_FAC_4M 0 -#define CLK_FAC_2M 1 -#define CLK_FAC_1M 2 -#define CLK_FAC_250K 3 -#define CLK_FAC_RPLL0_26M 4 -#define CLK_FAC_RPLL1_26M 5 -#define CLK_FAC_RCO25M 6 -#define CLK_FAC_RCO4M 7 -#define CLK_FAC_RCO2M 8 -#define CLK_FAC_3K2 9 -#define CLK_FAC_1K 10 -#define CLK_MPLL0_GATE 11 -#define CLK_MPLL1_GATE 12 -#define CLK_DPLL0_GATE 13 -#define CLK_DPLL1_GATE 14 -#define CLK_LTEPLL0_GATE 15 -#define CLK_TWPLL_GATE 16 -#define CLK_LTEPLL1_GATE 17 -#define CLK_RPLL0_GATE 18 -#define CLK_RPLL1_GATE 19 -#define CLK_CPPLL_GATE 20 -#define CLK_GPLL_GATE 21 -#define CLK_PMU_GATE_NUM (CLK_GPLL_GATE + 1) - -#define CLK_MPLL0 0 -#define CLK_MPLL1 1 -#define CLK_DPLL0 2 -#define CLK_DPLL1 3 -#define CLK_RPLL0 4 -#define CLK_RPLL1 5 -#define CLK_TWPLL 6 -#define CLK_LTEPLL0 7 -#define CLK_LTEPLL1 8 -#define CLK_GPLL 9 -#define CLK_CPPLL 10 -#define CLK_GPLL_42M5 11 -#define CLK_TWPLL_768M 12 -#define CLK_TWPLL_384M 13 -#define CLK_TWPLL_192M 14 -#define CLK_TWPLL_96M 15 -#define CLK_TWPLL_48M 16 -#define CLK_TWPLL_24M 17 -#define CLK_TWPLL_12M 18 -#define CLK_TWPLL_512M 19 -#define CLK_TWPLL_256M 20 -#define CLK_TWPLL_128M 21 -#define CLK_TWPLL_64M 22 -#define CLK_TWPLL_307M2 23 -#define CLK_TWPLL_153M6 24 -#define CLK_TWPLL_76M8 25 -#define CLK_TWPLL_51M2 26 -#define CLK_TWPLL_38M4 27 -#define CLK_TWPLL_19M2 28 -#define CLK_L0_614M4 29 -#define CLK_L0_409M6 30 -#define CLK_L0_38M 31 -#define CLK_L1_38M 32 -#define CLK_RPLL0_192M 33 -#define CLK_RPLL0_96M 34 -#define CLK_RPLL0_48M 35 -#define CLK_RPLL1_468M 36 -#define CLK_RPLL1_192M 37 -#define CLK_RPLL1_96M 38 -#define CLK_RPLL1_64M 39 -#define CLK_RPLL1_48M 40 -#define CLK_DPLL0_50M 41 -#define CLK_DPLL1_50M 42 -#define CLK_CPPLL_50M 43 -#define CLK_M0_39M 44 -#define CLK_M1_63M 45 -#define CLK_PLL_NUM (CLK_M1_63M + 1) - - -#define CLK_AP_APB 0 -#define CLK_AP_USB3 1 -#define CLK_UART0 2 -#define CLK_UART1 3 -#define CLK_UART2 4 -#define CLK_UART3 5 -#define CLK_UART4 6 -#define CLK_I2C0 7 -#define CLK_I2C1 8 -#define CLK_I2C2 9 -#define CLK_I2C3 10 -#define CLK_I2C4 11 -#define CLK_I2C5 12 -#define CLK_SPI0 13 -#define CLK_SPI1 14 -#define CLK_SPI2 15 -#define CLK_SPI3 16 -#define CLK_IIS0 17 -#define CLK_IIS1 18 -#define CLK_IIS2 19 -#define CLK_IIS3 20 -#define CLK_AP_CLK_NUM (CLK_IIS3 + 1) - -#define CLK_AON_APB 0 -#define CLK_AUX0 1 -#define CLK_AUX1 2 -#define CLK_AUX2 3 -#define CLK_PROBE 4 -#define CLK_SP_AHB 5 -#define CLK_CCI 6 -#define CLK_GIC 7 -#define CLK_CSSYS 8 -#define CLK_SDIO0_2X 9 -#define CLK_SDIO1_2X 10 -#define CLK_SDIO2_2X 11 -#define CLK_EMMC_2X 12 -#define CLK_SDIO0_1X 13 -#define CLK_SDIO1_1X 14 -#define CLK_SDIO2_1X 15 -#define CLK_EMMC_1X 16 -#define CLK_ADI 17 -#define CLK_PWM0 18 -#define CLK_PWM1 19 -#define CLK_PWM2 20 -#define CLK_PWM3 21 -#define CLK_EFUSE 22 -#define CLK_CM3_UART0 23 -#define CLK_CM3_UART1 24 -#define CLK_THM 25 -#define CLK_CM3_I2C0 26 -#define CLK_CM3_I2C1 27 -#define CLK_CM4_SPI 28 -#define CLK_AON_I2C 29 -#define CLK_AVS 30 -#define CLK_CA53_DAP 31 -#define CLK_CA53_TS 32 -#define CLK_DJTAG_TCK 33 -#define CLK_PMU 34 -#define CLK_PMU_26M 35 -#define CLK_DEBOUNCE 36 -#define CLK_OTG2_REF 37 -#define CLK_USB3_REF 38 -#define CLK_AP_AXI 39 -#define CLK_AON_PREDIV_NUM (CLK_AP_AXI + 1) - -#define CLK_USB3_EB 0 -#define CLK_USB3_SUSPEND_EB 1 -#define CLK_USB3_REF_EB 2 -#define CLK_DMA_EB 3 -#define CLK_SDIO0_EB 4 -#define CLK_SDIO1_EB 5 -#define CLK_SDIO2_EB 6 -#define CLK_EMMC_EB 7 -#define CLK_ROM_EB 8 -#define CLK_BUSMON_EB 9 -#define CLK_CC63S_EB 10 -#define CLK_CC63P_EB 11 -#define CLK_CE0_EB 12 -#define CLK_CE1_EB 13 -#define CLK_APAHB_GATE_NUM (CLK_CE1_EB + 1) - -#define CLK_AVS_LIT_EB 0 -#define CLK_AVS_BIG_EB 1 -#define CLK_AP_INTC5_EB 2 -#define CLK_GPIO_EB 3 -#define CLK_PWM0_EB 4 -#define CLK_PWM1_EB 5 -#define CLK_PWM2_EB 6 -#define CLK_PWM3_EB 7 -#define CLK_KPD_EB 8 -#define CLK_AON_SYS_EB 9 -#define CLK_AP_SYS_EB 10 -#define CLK_AON_TMR_EB 11 -#define CLK_AP_TMR0_EB 12 -#define CLK_EFUSE_EB 13 -#define CLK_EIC_EB 14 -#define CLK_PUB1_REG_EB 15 -#define CLK_ADI_EB 16 -#define CLK_AP_INTC0_EB 17 -#define CLK_AP_INTC1_EB 18 -#define CLK_AP_INTC2_EB 19 -#define CLK_AP_INTC3_EB 20 -#define CLK_AP_INTC4_EB 21 -#define CLK_SPLK_EB 22 -#define CLK_MSPI_EB 23 -#define CLK_PUB0_REG_EB 24 -#define CLK_PIN_EB 25 -#define CLK_AON_CKG_EB 26 -#define CLK_GPU_EB 27 -#define CLK_APCPU_TS0_EB 28 -#define CLK_APCPU_TS1_EB 29 -#define CLK_DAP_EB 30 -#define CLK_I2C_EB 31 -#define CLK_PMU_EB 32 -#define CLK_THM_EB 33 -#define CLK_AUX0_EB 34 -#define CLK_AUX1_EB 35 -#define CLK_AUX2_EB 36 -#define CLK_PROBE_EB 37 -#define CLK_GPU0_AVS_EB 38 -#define CLK_GPU1_AVS_EB 39 -#define CLK_APCPU_WDG_EB 40 -#define CLK_AP_TMR1_EB 41 -#define CLK_AP_TMR2_EB 42 -#define CLK_DISP_EMC_EB 43 -#define CLK_ZIP_EMC_EB 44 -#define CLK_GSP_EMC_EB 45 -#define CLK_OSC_AON_EB 46 -#define CLK_LVDS_TRX_EB 47 -#define CLK_LVDS_TCXO_EB 48 -#define CLK_MDAR_EB 49 -#define CLK_RTC4M0_CAL_EB 50 -#define CLK_RCT100M_CAL_EB 51 -#define CLK_DJTAG_EB 52 -#define CLK_MBOX_EB 53 -#define CLK_AON_DMA_EB 54 -#define CLK_DBG_EMC_EB 55 -#define CLK_LVDS_PLL_DIV_EN 56 -#define CLK_DEF_EB 57 -#define CLK_AON_APB_RSV0 58 -#define CLK_ORP_JTAG_EB 59 -#define CLK_VSP_EB 60 -#define CLK_CAM_EB 61 -#define CLK_DISP_EB 62 -#define CLK_DBG_AXI_IF_EB 63 -#define CLK_SDIO0_2X_EN 64 -#define CLK_SDIO1_2X_EN 65 -#define CLK_SDIO2_2X_EN 66 -#define CLK_EMMC_2X_EN 67 -#define CLK_ARCH_RTC_EB 68 -#define CLK_KPB_RTC_EB 69 -#define CLK_AON_SYST_RTC_EB 70 -#define CLK_AP_SYST_RTC_EB 71 -#define CLK_AON_TMR_RTC_EB 72 -#define CLK_AP_TMR0_RTC_EB 73 -#define CLK_EIC_RTC_EB 74 -#define CLK_EIC_RTCDV5_EB 75 -#define CLK_AP_WDG_RTC_EB 76 -#define CLK_AP_TMR1_RTC_EB 77 -#define CLK_AP_TMR2_RTC_EB 78 -#define CLK_DCXO_TMR_RTC_EB 79 -#define CLK_BB_CAL_RTC_EB 80 -#define CLK_AVS_BIG_RTC_EB 81 -#define CLK_AVS_LIT_RTC_EB 82 -#define CLK_AVS_GPU0_RTC_EB 83 -#define CLK_AVS_GPU1_RTC_EB 84 -#define CLK_GPU_TS_EB 85 -#define CLK_RTCDV10_EB 86 -#define CLK_AON_GATE_NUM (CLK_RTCDV10_EB + 1) - -#define CLK_LIT_MCU 0 -#define CLK_BIG_MCU 1 -#define CLK_AONSECURE_NUM (CLK_BIG_MCU + 1) - -#define CLK_AGCP_IIS0_EB 0 -#define CLK_AGCP_IIS1_EB 1 -#define CLK_AGCP_IIS2_EB 2 -#define CLK_AGCP_IIS3_EB 3 -#define CLK_AGCP_UART_EB 4 -#define CLK_AGCP_DMACP_EB 5 -#define CLK_AGCP_DMAAP_EB 6 -#define CLK_AGCP_ARC48K_EB 7 -#define CLK_AGCP_SRC44P1K_EB 8 -#define CLK_AGCP_MCDT_EB 9 -#define CLK_AGCP_VBCIFD_EB 10 -#define CLK_AGCP_VBC_EB 11 -#define CLK_AGCP_SPINLOCK_EB 12 -#define CLK_AGCP_ICU_EB 13 -#define CLK_AGCP_AP_ASHB_EB 14 -#define CLK_AGCP_CP_ASHB_EB 15 -#define CLK_AGCP_AUD_EB 16 -#define CLK_AGCP_AUDIF_EB 17 -#define CLK_AGCP_GATE_NUM (CLK_AGCP_AUDIF_EB + 1) - -#define CLK_GPU 0 -#define CLK_GPU_NUM (CLK_GPU + 1) - -#define CLK_AHB_VSP 0 -#define CLK_VSP 1 -#define CLK_VSP_ENC 2 -#define CLK_VPP 3 -#define CLK_VSP_26M 4 -#define CLK_VSP_NUM (CLK_VSP_26M + 1) - -#define CLK_VSP_DEC_EB 0 -#define CLK_VSP_CKG_EB 1 -#define CLK_VSP_MMU_EB 2 -#define CLK_VSP_ENC_EB 3 -#define CLK_VPP_EB 4 -#define CLK_VSP_26M_EB 5 -#define CLK_VSP_AXI_GATE 6 -#define CLK_VSP_ENC_GATE 7 -#define CLK_VPP_AXI_GATE 8 -#define CLK_VSP_BM_GATE 9 -#define CLK_VSP_ENC_BM_GATE 10 -#define CLK_VPP_BM_GATE 11 -#define CLK_VSP_GATE_NUM (CLK_VPP_BM_GATE + 1) - -#define CLK_AHB_CAM 0 -#define CLK_SENSOR0 1 -#define CLK_SENSOR1 2 -#define CLK_SENSOR2 3 -#define CLK_MIPI_CSI0_EB 4 -#define CLK_MIPI_CSI1_EB 5 -#define CLK_CAM_NUM (CLK_MIPI_CSI1_EB + 1) - -#define CLK_DCAM0_EB 0 -#define CLK_DCAM1_EB 1 -#define CLK_ISP0_EB 2 -#define CLK_CSI0_EB 3 -#define CLK_CSI1_EB 4 -#define CLK_JPG0_EB 5 -#define CLK_JPG1_EB 6 -#define CLK_CAM_CKG_EB 7 -#define CLK_CAM_MMU_EB 8 -#define CLK_ISP1_EB 9 -#define CLK_CPP_EB 10 -#define CLK_MMU_PF_EB 11 -#define CLK_ISP2_EB 12 -#define CLK_DCAM2ISP_IF_EB 13 -#define CLK_ISP2DCAM_IF_EB 14 -#define CLK_ISP_LCLK_EB 15 -#define CLK_ISP_ICLK_EB 16 -#define CLK_ISP_MCLK_EB 17 -#define CLK_ISP_PCLK_EB 18 -#define CLK_ISP_ISP2DCAM_EB 19 -#define CLK_DCAM0_IF_EB 20 -#define CLK_CLK26M_IF_EB 21 -#define CLK_CPHY0_GATE 22 -#define CLK_MIPI_CSI0_GATE 23 -#define CLK_CPHY1_GATE 24 -#define CLK_MIPI_CSI1 25 -#define CLK_DCAM0_AXI_GATE 26 -#define CLK_DCAM1_AXI_GATE 27 -#define CLK_SENSOR0_GATE 28 -#define CLK_SENSOR1_GATE 29 -#define CLK_JPG0_AXI_GATE 30 -#define CLK_GPG1_AXI_GATE 31 -#define CLK_ISP0_AXI_GATE 32 -#define CLK_ISP1_AXI_GATE 33 -#define CLK_ISP2_AXI_GATE 34 -#define CLK_CPP_AXI_GATE 35 -#define CLK_D0_IF_AXI_GATE 36 -#define CLK_D2I_IF_AXI_GATE 37 -#define CLK_I2D_IF_AXI_GATE 38 -#define CLK_SPARE_AXI_GATE 39 -#define CLK_SENSOR2_GATE 40 -#define CLK_D0IF_IN_D_EN 41 -#define CLK_D1IF_IN_D_EN 42 -#define CLK_D0IF_IN_D2I_EN 43 -#define CLK_D1IF_IN_D2I_EN 44 -#define CLK_IA_IN_D2I_EN 45 -#define CLK_IB_IN_D2I_EN 46 -#define CLK_IC_IN_D2I_EN 47 -#define CLK_IA_IN_I_EN 48 -#define CLK_IB_IN_I_EN 49 -#define CLK_IC_IN_I_EN 50 -#define CLK_CAM_GATE_NUM (CLK_IC_IN_I_EN + 1) - -#define CLK_AHB_DISP 0 -#define CLK_DISPC0_DPI 1 -#define CLK_DISPC1_DPI 2 -#define CLK_DISP_NUM (CLK_DISPC1_DPI + 1) - -#define CLK_DISPC0_EB 0 -#define CLK_DISPC1_EB 1 -#define CLK_DISPC_MMU_EB 2 -#define CLK_GSP0_EB 3 -#define CLK_GSP1_EB 4 -#define CLK_GSP0_MMU_EB 5 -#define CLK_GSP1_MMU_EB 6 -#define CLK_DSI0_EB 7 -#define CLK_DSI1_EB 8 -#define CLK_DISP_CKG_EB 9 -#define CLK_DISP_GPU_EB 10 -#define CLK_GPU_MTX_EB 11 -#define CLK_GSP_MTX_EB 12 -#define CLK_TMC_MTX_EB 13 -#define CLK_DISPC_MTX_EB 14 -#define CLK_DPHY0_GATE 15 -#define CLK_DPHY1_GATE 16 -#define CLK_GSP0_A_GATE 17 -#define CLK_GSP1_A_GATE 18 -#define CLK_GSP0_F_GATE 19 -#define CLK_GSP1_F_GATE 20 -#define CLK_D_MTX_F_GATE 21 -#define CLK_D_MTX_A_GATE 22 -#define CLK_D_NOC_F_GATE 23 -#define CLK_D_NOC_A_GATE 24 -#define CLK_GSP_MTX_F_GATE 25 -#define CLK_GSP_MTX_A_GATE 26 -#define CLK_GSP_NOC_F_GATE 27 -#define CLK_GSP_NOC_A_GATE 28 -#define CLK_DISPM0IDLE_GATE 29 -#define CLK_GSPM0IDLE_GATE 30 -#define CLK_DISP_GATE_NUM (CLK_GSPM0IDLE_GATE + 1) - -#define CLK_SIM0_EB 0 -#define CLK_IIS0_EB 1 -#define CLK_IIS1_EB 2 -#define CLK_IIS2_EB 3 -#define CLK_IIS3_EB 4 -#define CLK_SPI0_EB 5 -#define CLK_SPI1_EB 6 -#define CLK_SPI2_EB 7 -#define CLK_I2C0_EB 8 -#define CLK_I2C1_EB 9 -#define CLK_I2C2_EB 10 -#define CLK_I2C3_EB 11 -#define CLK_I2C4_EB 12 -#define CLK_I2C5_EB 13 -#define CLK_UART0_EB 14 -#define CLK_UART1_EB 15 -#define CLK_UART2_EB 16 -#define CLK_UART3_EB 17 -#define CLK_UART4_EB 18 -#define CLK_AP_CKG_EB 19 -#define CLK_SPI3_EB 20 -#define CLK_APAPB_GATE_NUM (CLK_SPI3_EB + 1) - -#endif /* _DT_BINDINGS_CLK_SC9860_H_ */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/ste-ab8500.h b/sys/gnu/dts/include/dt-bindings/clock/ste-ab8500.h deleted file mode 100644 index fb42dd0cab5..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/ste-ab8500.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __STE_CLK_AB8500_H__ -#define __STE_CLK_AB8500_H__ - -#define AB8500_SYSCLK_BUF2 0 -#define AB8500_SYSCLK_BUF3 1 -#define AB8500_SYSCLK_BUF4 2 -#define AB8500_SYSCLK_ULP 3 -#define AB8500_SYSCLK_INT 4 -#define AB8500_SYSCLK_AUDIO 5 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/stih407-clks.h b/sys/gnu/dts/include/dt-bindings/clock/stih407-clks.h deleted file mode 100644 index f0936c13377..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/stih407-clks.h +++ /dev/null @@ -1,91 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides constants clk index STMicroelectronics - * STiH407 SoC. - */ -#ifndef _DT_BINDINGS_CLK_STIH407 -#define _DT_BINDINGS_CLK_STIH407 - -/* CLOCKGEN A0 */ -#define CLK_IC_LMI0 0 -#define CLK_IC_LMI1 1 - -/* CLOCKGEN C0 */ -#define CLK_ICN_GPU 0 -#define CLK_FDMA 1 -#define CLK_NAND 2 -#define CLK_HVA 3 -#define CLK_PROC_STFE 4 -#define CLK_PROC_TP 5 -#define CLK_RX_ICN_DMU 6 -#define CLK_RX_ICN_DISP_0 6 -#define CLK_RX_ICN_DISP_1 6 -#define CLK_RX_ICN_HVA 7 -#define CLK_RX_ICN_TS 7 -#define CLK_ICN_CPU 8 -#define CLK_TX_ICN_DMU 9 -#define CLK_TX_ICN_HVA 9 -#define CLK_TX_ICN_TS 9 -#define CLK_ICN_COMPO 9 -#define CLK_MMC_0 10 -#define CLK_MMC_1 11 -#define CLK_JPEGDEC 12 -#define CLK_ICN_REG 13 -#define CLK_TRACE_A9 13 -#define CLK_PTI_STM 13 -#define CLK_EXT2F_A9 13 -#define CLK_IC_BDISP_0 14 -#define CLK_IC_BDISP_1 15 -#define CLK_PP_DMU 16 -#define CLK_VID_DMU 17 -#define CLK_DSS_LPC 18 -#define CLK_ST231_AUD_0 19 -#define CLK_ST231_GP_0 19 -#define CLK_ST231_GP_1 20 -#define CLK_ST231_DMU 21 -#define CLK_ICN_LMI 22 -#define CLK_TX_ICN_DISP_0 23 -#define CLK_TX_ICN_DISP_1 23 -#define CLK_ICN_SBC 24 -#define CLK_STFE_FRC2 25 -#define CLK_ETH_PHY 26 -#define CLK_ETH_REF_PHYCLK 27 -#define CLK_FLASH_PROMIP 28 -#define CLK_MAIN_DISP 29 -#define CLK_AUX_DISP 30 -#define CLK_COMPO_DVP 31 - -/* CLOCKGEN D0 */ -#define CLK_PCM_0 0 -#define CLK_PCM_1 1 -#define CLK_PCM_2 2 -#define CLK_SPDIFF 3 - -/* CLOCKGEN D2 */ -#define CLK_PIX_MAIN_DISP 0 -#define CLK_PIX_PIP 1 -#define CLK_PIX_GDP1 2 -#define CLK_PIX_GDP2 3 -#define CLK_PIX_GDP3 4 -#define CLK_PIX_GDP4 5 -#define CLK_PIX_AUX_DISP 6 -#define CLK_DENC 7 -#define CLK_PIX_HDDAC 8 -#define CLK_HDDAC 9 -#define CLK_SDDAC 10 -#define CLK_PIX_DVO 11 -#define CLK_DVO 12 -#define CLK_PIX_HDMI 13 -#define CLK_TMDS_HDMI 14 -#define CLK_REF_HDMIPHY 15 - -/* CLOCKGEN D3 */ -#define CLK_STFE_FRC1 0 -#define CLK_TSOUT_0 1 -#define CLK_TSOUT_1 2 -#define CLK_MCHI 3 -#define CLK_VSENS_COMPO 4 -#define CLK_FRC1_REMOTE 5 -#define CLK_LPC_0 6 -#define CLK_LPC_1 7 -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/stih410-clks.h b/sys/gnu/dts/include/dt-bindings/clock/stih410-clks.h deleted file mode 100644 index 90cbe6154c3..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/stih410-clks.h +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides constants clk index STMicroelectronics - * STiH410 SoC. - */ -#ifndef _DT_BINDINGS_CLK_STIH410 -#define _DT_BINDINGS_CLK_STIH410 - -#include "stih407-clks.h" - -/* STiH410 introduces new clock outputs compared to STiH407 */ - -/* CLOCKGEN C0 */ -#define CLK_TX_ICN_HADES 32 -#define CLK_RX_ICN_HADES 33 -#define CLK_ICN_REG_16 34 -#define CLK_PP_HADES 35 -#define CLK_CLUST_HADES 36 -#define CLK_HWPE_HADES 37 -#define CLK_FC_HADES 38 - -/* CLOCKGEN D0 */ -#define CLK_PCMR10_MASTER 4 -#define CLK_USB2_PHY 5 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/stih415-clks.h b/sys/gnu/dts/include/dt-bindings/clock/stih415-clks.h deleted file mode 100644 index d80caa68aeb..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/stih415-clks.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * This header provides constants clk index STMicroelectronics - * STiH415 SoC. - */ -#ifndef _CLK_STIH415 -#define _CLK_STIH415 - -/* CLOCKGEN A0 */ -#define CLK_ICN_REG 0 -#define CLK_ETH1_PHY 4 - -/* CLOCKGEN A1 */ -#define CLK_ICN_IF_2 0 -#define CLK_GMAC0_PHY 3 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/stih416-clks.h b/sys/gnu/dts/include/dt-bindings/clock/stih416-clks.h deleted file mode 100644 index 74302278024..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/stih416-clks.h +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides constants clk index STMicroelectronics - * STiH416 SoC. - */ -#ifndef _CLK_STIH416 -#define _CLK_STIH416 - -/* CLOCKGEN A0 */ -#define CLK_ICN_REG 0 -#define CLK_ETH1_PHY 4 - -/* CLOCKGEN A1 */ -#define CLK_ICN_IF_2 0 -#define CLK_GMAC0_PHY 3 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/stih418-clks.h b/sys/gnu/dts/include/dt-bindings/clock/stih418-clks.h deleted file mode 100644 index 0e7fba0c52b..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/stih418-clks.h +++ /dev/null @@ -1,35 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides constants clk index STMicroelectronics - * STiH418 SoC. - */ -#ifndef _DT_BINDINGS_CLK_STIH418 -#define _DT_BINDINGS_CLK_STIH418 - -#include "stih410-clks.h" - -/* STiH418 introduces new clock outputs compared to STiH410 */ - -/* CLOCKGEN C0 */ -#define CLK_PROC_BDISP_0 14 -#define CLK_PROC_BDISP_1 15 -#define CLK_TX_ICN_1 23 -#define CLK_ETH_PHYREF 27 -#define CLK_PP_HEVC 35 -#define CLK_CLUST_HEVC 36 -#define CLK_HWPE_HEVC 37 -#define CLK_FC_HEVC 38 -#define CLK_PROC_MIXER 39 -#define CLK_PROC_SC 40 -#define CLK_AVSP_HEVC 41 - -/* CLOCKGEN D2 */ -#undef CLK_PIX_PIP -#undef CLK_PIX_GDP1 -#undef CLK_PIX_GDP2 -#undef CLK_PIX_GDP3 -#undef CLK_PIX_GDP4 - -#define CLK_TMDS_HDMI_DIV2 5 -#define CLK_VP9 47 -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/stm32fx-clock.h b/sys/gnu/dts/include/dt-bindings/clock/stm32fx-clock.h deleted file mode 100644 index 1cc89c54857..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/stm32fx-clock.h +++ /dev/null @@ -1,63 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * stm32fx-clock.h - * - * Copyright (C) 2016 STMicroelectronics - * Author: Gabriel Fernandez for STMicroelectronics. - */ - -/* - * List of clocks wich are not derived from system clock (SYSCLOCK) - * - * The index of these clocks is the secondary index of DT bindings - * (see Documentatoin/devicetree/bindings/clock/st,stm32-rcc.txt) - * - * e.g: - ; -*/ - -#ifndef _DT_BINDINGS_CLK_STMFX_H -#define _DT_BINDINGS_CLK_STMFX_H - -#define SYSTICK 0 -#define FCLK 1 -#define CLK_LSI 2 -#define CLK_LSE 3 -#define CLK_HSE_RTC 4 -#define CLK_RTC 5 -#define PLL_VCO_I2S 6 -#define PLL_VCO_SAI 7 -#define CLK_LCD 8 -#define CLK_I2S 9 -#define CLK_SAI1 10 -#define CLK_SAI2 11 -#define CLK_I2SQ_PDIV 12 -#define CLK_SAIQ_PDIV 13 -#define CLK_HSI 14 -#define CLK_SYSCLK 15 -#define CLK_F469_DSI 16 - -#define END_PRIMARY_CLK 17 - -#define CLK_HDMI_CEC 16 -#define CLK_SPDIF 17 -#define CLK_USART1 18 -#define CLK_USART2 19 -#define CLK_USART3 20 -#define CLK_UART4 21 -#define CLK_UART5 22 -#define CLK_USART6 23 -#define CLK_UART7 24 -#define CLK_UART8 25 -#define CLK_I2C1 26 -#define CLK_I2C2 27 -#define CLK_I2C3 28 -#define CLK_I2C4 29 -#define CLK_LPTIMER 30 -#define CLK_PLL_SRC 31 -#define CLK_DFSDM1 32 -#define CLK_ADFSDM1 33 -#define CLK_F769_DSI 34 -#define END_PRIMARY_CLK_F7 35 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/stm32h7-clks.h b/sys/gnu/dts/include/dt-bindings/clock/stm32h7-clks.h deleted file mode 100644 index 6637272b324..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/stm32h7-clks.h +++ /dev/null @@ -1,165 +0,0 @@ -/* SYS, CORE AND BUS CLOCKS */ -#define SYS_D1CPRE 0 -#define HCLK 1 -#define PCLK1 2 -#define PCLK2 3 -#define PCLK3 4 -#define PCLK4 5 -#define HSI_DIV 6 -#define HSE_1M 7 -#define I2S_CKIN 8 -#define CK_DSI_PHY 9 -#define HSE_CK 10 -#define LSE_CK 11 -#define CSI_KER_DIV122 12 -#define RTC_CK 13 -#define CPU_SYSTICK 14 - -/* OSCILLATOR BANK */ -#define OSC_BANK 18 -#define HSI_CK 18 -#define HSI_KER_CK 19 -#define CSI_CK 20 -#define CSI_KER_CK 21 -#define RC48_CK 22 -#define LSI_CK 23 - -/* MCLOCK BANK */ -#define MCLK_BANK 28 -#define PER_CK 28 -#define PLLSRC 29 -#define SYS_CK 30 -#define TRACEIN_CK 31 - -/* ODF BANK */ -#define ODF_BANK 32 -#define PLL1_P 32 -#define PLL1_Q 33 -#define PLL1_R 34 -#define PLL2_P 35 -#define PLL2_Q 36 -#define PLL2_R 37 -#define PLL3_P 38 -#define PLL3_Q 39 -#define PLL3_R 40 - -/* MCO BANK */ -#define MCO_BANK 41 -#define MCO1 41 -#define MCO2 42 - -/* PERIF BANK */ -#define PERIF_BANK 50 -#define D1SRAM1_CK 50 -#define ITCM_CK 51 -#define DTCM2_CK 52 -#define DTCM1_CK 53 -#define FLITF_CK 54 -#define JPGDEC_CK 55 -#define DMA2D_CK 56 -#define MDMA_CK 57 -#define USB2ULPI_CK 58 -#define USB1ULPI_CK 59 -#define ETH1RX_CK 60 -#define ETH1TX_CK 61 -#define ETH1MAC_CK 62 -#define ART_CK 63 -#define DMA2_CK 64 -#define DMA1_CK 65 -#define D2SRAM3_CK 66 -#define D2SRAM2_CK 67 -#define D2SRAM1_CK 68 -#define HASH_CK 69 -#define CRYPT_CK 70 -#define CAMITF_CK 71 -#define BKPRAM_CK 72 -#define HSEM_CK 73 -#define BDMA_CK 74 -#define CRC_CK 75 -#define GPIOK_CK 76 -#define GPIOJ_CK 77 -#define GPIOI_CK 78 -#define GPIOH_CK 79 -#define GPIOG_CK 80 -#define GPIOF_CK 81 -#define GPIOE_CK 82 -#define GPIOD_CK 83 -#define GPIOC_CK 84 -#define GPIOB_CK 85 -#define GPIOA_CK 86 -#define WWDG1_CK 87 -#define DAC12_CK 88 -#define WWDG2_CK 89 -#define TIM14_CK 90 -#define TIM13_CK 91 -#define TIM12_CK 92 -#define TIM7_CK 93 -#define TIM6_CK 94 -#define TIM5_CK 95 -#define TIM4_CK 96 -#define TIM3_CK 97 -#define TIM2_CK 98 -#define MDIOS_CK 99 -#define OPAMP_CK 100 -#define CRS_CK 101 -#define TIM17_CK 102 -#define TIM16_CK 103 -#define TIM15_CK 104 -#define TIM8_CK 105 -#define TIM1_CK 106 -#define TMPSENS_CK 107 -#define RTCAPB_CK 108 -#define VREF_CK 109 -#define COMP12_CK 110 -#define SYSCFG_CK 111 - -/* KERNEL BANK */ -#define KERN_BANK 120 -#define SDMMC1_CK 120 -#define QUADSPI_CK 121 -#define FMC_CK 122 -#define USB2OTG_CK 123 -#define USB1OTG_CK 124 -#define ADC12_CK 125 -#define SDMMC2_CK 126 -#define RNG_CK 127 -#define ADC3_CK 128 -#define DSI_CK 129 -#define LTDC_CK 130 -#define USART8_CK 131 -#define USART7_CK 132 -#define HDMICEC_CK 133 -#define I2C3_CK 134 -#define I2C2_CK 135 -#define I2C1_CK 136 -#define UART5_CK 137 -#define UART4_CK 138 -#define USART3_CK 139 -#define USART2_CK 140 -#define SPDIFRX_CK 141 -#define SPI3_CK 142 -#define SPI2_CK 143 -#define LPTIM1_CK 144 -#define FDCAN_CK 145 -#define SWP_CK 146 -#define HRTIM_CK 147 -#define DFSDM1_CK 148 -#define SAI3_CK 149 -#define SAI2_CK 150 -#define SAI1_CK 151 -#define SPI5_CK 152 -#define SPI4_CK 153 -#define SPI1_CK 154 -#define USART6_CK 155 -#define USART1_CK 156 -#define SAI4B_CK 157 -#define SAI4A_CK 158 -#define LPTIM5_CK 159 -#define LPTIM4_CK 160 -#define LPTIM3_CK 161 -#define LPTIM2_CK 162 -#define I2C4_CK 163 -#define SPI6_CK 164 -#define LPUART1_CK 165 - -#define STM32H7_MAX_CLKS 166 diff --git a/sys/gnu/dts/include/dt-bindings/clock/stm32mp1-clks.h b/sys/gnu/dts/include/dt-bindings/clock/stm32mp1-clks.h deleted file mode 100644 index 4cdaf135829..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/stm32mp1-clks.h +++ /dev/null @@ -1,251 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ -/* - * Copyright (C) STMicroelectronics 2018 - All Rights Reserved - * Author: Gabriel Fernandez for STMicroelectronics. - */ - -#ifndef _DT_BINDINGS_STM32MP1_CLKS_H_ -#define _DT_BINDINGS_STM32MP1_CLKS_H_ - -/* OSCILLATOR clocks */ -#define CK_HSE 0 -#define CK_CSI 1 -#define CK_LSI 2 -#define CK_LSE 3 -#define CK_HSI 4 -#define CK_HSE_DIV2 5 - -/* Bus clocks */ -#define TIM2 6 -#define TIM3 7 -#define TIM4 8 -#define TIM5 9 -#define TIM6 10 -#define TIM7 11 -#define TIM12 12 -#define TIM13 13 -#define TIM14 14 -#define LPTIM1 15 -#define SPI2 16 -#define SPI3 17 -#define USART2 18 -#define USART3 19 -#define UART4 20 -#define UART5 21 -#define UART7 22 -#define UART8 23 -#define I2C1 24 -#define I2C2 25 -#define I2C3 26 -#define I2C5 27 -#define SPDIF 28 -#define CEC 29 -#define DAC12 30 -#define MDIO 31 -#define TIM1 32 -#define TIM8 33 -#define TIM15 34 -#define TIM16 35 -#define TIM17 36 -#define SPI1 37 -#define SPI4 38 -#define SPI5 39 -#define USART6 40 -#define SAI1 41 -#define SAI2 42 -#define SAI3 43 -#define DFSDM 44 -#define FDCAN 45 -#define LPTIM2 46 -#define LPTIM3 47 -#define LPTIM4 48 -#define LPTIM5 49 -#define SAI4 50 -#define SYSCFG 51 -#define VREF 52 -#define TMPSENS 53 -#define PMBCTRL 54 -#define HDP 55 -#define LTDC 56 -#define DSI 57 -#define IWDG2 58 -#define USBPHY 59 -#define STGENRO 60 -#define SPI6 61 -#define I2C4 62 -#define I2C6 63 -#define USART1 64 -#define RTCAPB 65 -#define TZC1 66 -#define TZPC 67 -#define IWDG1 68 -#define BSEC 69 -#define STGEN 70 -#define DMA1 71 -#define DMA2 72 -#define DMAMUX 73 -#define ADC12 74 -#define USBO 75 -#define SDMMC3 76 -#define DCMI 77 -#define CRYP2 78 -#define HASH2 79 -#define RNG2 80 -#define CRC2 81 -#define HSEM 82 -#define IPCC 83 -#define GPIOA 84 -#define GPIOB 85 -#define GPIOC 86 -#define GPIOD 87 -#define GPIOE 88 -#define GPIOF 89 -#define GPIOG 90 -#define GPIOH 91 -#define GPIOI 92 -#define GPIOJ 93 -#define GPIOK 94 -#define GPIOZ 95 -#define CRYP1 96 -#define HASH1 97 -#define RNG1 98 -#define BKPSRAM 99 -#define MDMA 100 -#define GPU 101 -#define ETHCK 102 -#define ETHTX 103 -#define ETHRX 104 -#define ETHMAC 105 -#define FMC 106 -#define QSPI 107 -#define SDMMC1 108 -#define SDMMC2 109 -#define CRC1 110 -#define USBH 111 -#define ETHSTP 112 -#define TZC2 113 - -/* Kernel clocks */ -#define SDMMC1_K 118 -#define SDMMC2_K 119 -#define SDMMC3_K 120 -#define FMC_K 121 -#define QSPI_K 122 -#define ETHCK_K 123 -#define RNG1_K 124 -#define RNG2_K 125 -#define GPU_K 126 -#define USBPHY_K 127 -#define STGEN_K 128 -#define SPDIF_K 129 -#define SPI1_K 130 -#define SPI2_K 131 -#define SPI3_K 132 -#define SPI4_K 133 -#define SPI5_K 134 -#define SPI6_K 135 -#define CEC_K 136 -#define I2C1_K 137 -#define I2C2_K 138 -#define I2C3_K 139 -#define I2C4_K 140 -#define I2C5_K 141 -#define I2C6_K 142 -#define LPTIM1_K 143 -#define LPTIM2_K 144 -#define LPTIM3_K 145 -#define LPTIM4_K 146 -#define LPTIM5_K 147 -#define USART1_K 148 -#define USART2_K 149 -#define USART3_K 150 -#define UART4_K 151 -#define UART5_K 152 -#define USART6_K 153 -#define UART7_K 154 -#define UART8_K 155 -#define DFSDM_K 156 -#define FDCAN_K 157 -#define SAI1_K 158 -#define SAI2_K 159 -#define SAI3_K 160 -#define SAI4_K 161 -#define ADC12_K 162 -#define DSI_K 163 -#define DSI_PX 164 -#define ADFSDM_K 165 -#define USBO_K 166 -#define LTDC_PX 167 -#define DAC12_K 168 -#define ETHPTP_K 169 - -/* PLL */ -#define PLL1 176 -#define PLL2 177 -#define PLL3 178 -#define PLL4 179 - -/* ODF */ -#define PLL1_P 180 -#define PLL1_Q 181 -#define PLL1_R 182 -#define PLL2_P 183 -#define PLL2_Q 184 -#define PLL2_R 185 -#define PLL3_P 186 -#define PLL3_Q 187 -#define PLL3_R 188 -#define PLL4_P 189 -#define PLL4_Q 190 -#define PLL4_R 191 - -/* AUX */ -#define RTC 192 - -/* MCLK */ -#define CK_PER 193 -#define CK_MPU 194 -#define CK_AXI 195 -#define CK_MCU 196 - -/* Time base */ -#define TIM2_K 197 -#define TIM3_K 198 -#define TIM4_K 199 -#define TIM5_K 200 -#define TIM6_K 201 -#define TIM7_K 202 -#define TIM12_K 203 -#define TIM13_K 204 -#define TIM14_K 205 -#define TIM1_K 206 -#define TIM8_K 207 -#define TIM15_K 208 -#define TIM16_K 209 -#define TIM17_K 210 - -/* MCO clocks */ -#define CK_MCO1 211 -#define CK_MCO2 212 - -/* TRACE & DEBUG clocks */ -#define CK_DBG 214 -#define CK_TRACE 215 - -/* DDR */ -#define DDRC1 220 -#define DDRC1LP 221 -#define DDRC2 222 -#define DDRC2LP 223 -#define DDRPHYC 224 -#define DDRPHYCLP 225 -#define DDRCAPB 226 -#define DDRCAPBLP 227 -#define AXIDCG 228 -#define DDRPHYCAPB 229 -#define DDRPHYCAPBLP 230 -#define DDRPERFM 231 - -#define STM32MP1_LAST_CLK 232 - -#endif /* _DT_BINDINGS_STM32MP1_CLKS_H_ */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/stratix10-clock.h b/sys/gnu/dts/include/dt-bindings/clock/stratix10-clock.h deleted file mode 100644 index 08b98e20b7c..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/stratix10-clock.h +++ /dev/null @@ -1,86 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2017, Intel Corporation - */ - -#ifndef __STRATIX10_CLOCK_H -#define __STRATIX10_CLOCK_H - -/* fixed rate clocks */ -#define STRATIX10_OSC1 0 -#define STRATIX10_CB_INTOSC_HS_DIV2_CLK 1 -#define STRATIX10_CB_INTOSC_LS_CLK 2 -#define STRATIX10_F2S_FREE_CLK 3 - -/* fixed factor clocks */ -#define STRATIX10_L4_SYS_FREE_CLK 4 -#define STRATIX10_MPU_PERIPH_CLK 5 -#define STRATIX10_MPU_L2RAM_CLK 6 -#define STRATIX10_SDMMC_CIU_CLK 7 - -/* PLL clocks */ -#define STRATIX10_MAIN_PLL_CLK 8 -#define STRATIX10_PERIPH_PLL_CLK 9 -#define STRATIX10_BOOT_CLK 10 - -/* Periph clocks */ -#define STRATIX10_MAIN_MPU_BASE_CLK 11 -#define STRATIX10_MAIN_NOC_BASE_CLK 12 -#define STRATIX10_MAIN_EMACA_CLK 13 -#define STRATIX10_MAIN_EMACB_CLK 14 -#define STRATIX10_MAIN_EMAC_PTP_CLK 15 -#define STRATIX10_MAIN_GPIO_DB_CLK 16 -#define STRATIX10_MAIN_SDMMC_CLK 17 -#define STRATIX10_MAIN_S2F_USR0_CLK 18 -#define STRATIX10_MAIN_S2F_USR1_CLK 19 -#define STRATIX10_MAIN_PSI_REF_CLK 20 - -#define STRATIX10_PERI_MPU_BASE_CLK 21 -#define STRATIX10_PERI_NOC_BASE_CLK 22 -#define STRATIX10_PERI_EMACA_CLK 23 -#define STRATIX10_PERI_EMACB_CLK 24 -#define STRATIX10_PERI_EMAC_PTP_CLK 25 -#define STRATIX10_PERI_GPIO_DB_CLK 26 -#define STRATIX10_PERI_SDMMC_CLK 27 -#define STRATIX10_PERI_S2F_USR0_CLK 28 -#define STRATIX10_PERI_S2F_USR1_CLK 29 -#define STRATIX10_PERI_PSI_REF_CLK 30 - -#define STRATIX10_MPU_FREE_CLK 31 -#define STRATIX10_NOC_FREE_CLK 32 -#define STRATIX10_S2F_USR0_CLK 33 -#define STRATIX10_NOC_CLK 34 -#define STRATIX10_EMAC_A_FREE_CLK 35 -#define STRATIX10_EMAC_B_FREE_CLK 36 -#define STRATIX10_EMAC_PTP_FREE_CLK 37 -#define STRATIX10_GPIO_DB_FREE_CLK 38 -#define STRATIX10_SDMMC_FREE_CLK 39 -#define STRATIX10_S2F_USER1_FREE_CLK 40 -#define STRATIX10_PSI_REF_FREE_CLK 41 - -/* Gate clocks */ -#define STRATIX10_MPU_CLK 42 -#define STRATIX10_L4_MAIN_CLK 43 -#define STRATIX10_L4_MP_CLK 44 -#define STRATIX10_L4_SP_CLK 45 -#define STRATIX10_CS_AT_CLK 46 -#define STRATIX10_CS_TRACE_CLK 47 -#define STRATIX10_CS_PDBG_CLK 48 -#define STRATIX10_CS_TIMER_CLK 49 -#define STRATIX10_S2F_USER0_CLK 50 -#define STRATIX10_S2F_USER1_CLK 51 -#define STRATIX10_EMAC0_CLK 52 -#define STRATIX10_EMAC1_CLK 53 -#define STRATIX10_EMAC2_CLK 54 -#define STRATIX10_EMAC_PTP_CLK 55 -#define STRATIX10_GPIO_DB_CLK 56 -#define STRATIX10_SDMMC_CLK 57 -#define STRATIX10_PSI_REF_CLK 58 -#define STRATIX10_USB_CLK 59 -#define STRATIX10_SPI_M_CLK 60 -#define STRATIX10_NAND_CLK 61 -#define STRATIX10_NAND_X_CLK 62 -#define STRATIX10_NAND_ECC_CLK 63 -#define STRATIX10_NUM_CLKS 64 - -#endif /* __STRATIX10_CLOCK_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/sun4i-a10-ccu.h b/sys/gnu/dts/include/dt-bindings/clock/sun4i-a10-ccu.h deleted file mode 100644 index e4fa61be5c7..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/sun4i-a10-ccu.h +++ /dev/null @@ -1,202 +0,0 @@ -/* - * Copyright (C) 2017 Priit Laes - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_CLK_SUN4I_A10_H_ -#define _DT_BINDINGS_CLK_SUN4I_A10_H_ - -#define CLK_HOSC 1 -#define CLK_PLL_VIDEO0_2X 9 -#define CLK_PLL_VIDEO1_2X 18 -#define CLK_CPU 20 - -/* AHB Gates */ -#define CLK_AHB_OTG 26 -#define CLK_AHB_EHCI0 27 -#define CLK_AHB_OHCI0 28 -#define CLK_AHB_EHCI1 29 -#define CLK_AHB_OHCI1 30 -#define CLK_AHB_SS 31 -#define CLK_AHB_DMA 32 -#define CLK_AHB_BIST 33 -#define CLK_AHB_MMC0 34 -#define CLK_AHB_MMC1 35 -#define CLK_AHB_MMC2 36 -#define CLK_AHB_MMC3 37 -#define CLK_AHB_MS 38 -#define CLK_AHB_NAND 39 -#define CLK_AHB_SDRAM 40 -#define CLK_AHB_ACE 41 -#define CLK_AHB_EMAC 42 -#define CLK_AHB_TS 43 -#define CLK_AHB_SPI0 44 -#define CLK_AHB_SPI1 45 -#define CLK_AHB_SPI2 46 -#define CLK_AHB_SPI3 47 -#define CLK_AHB_PATA 48 -#define CLK_AHB_SATA 49 -#define CLK_AHB_GPS 50 -#define CLK_AHB_HSTIMER 51 -#define CLK_AHB_VE 52 -#define CLK_AHB_TVD 53 -#define CLK_AHB_TVE0 54 -#define CLK_AHB_TVE1 55 -#define CLK_AHB_LCD0 56 -#define CLK_AHB_LCD1 57 -#define CLK_AHB_CSI0 58 -#define CLK_AHB_CSI1 59 -#define CLK_AHB_HDMI0 60 -#define CLK_AHB_HDMI1 61 -#define CLK_AHB_DE_BE0 62 -#define CLK_AHB_DE_BE1 63 -#define CLK_AHB_DE_FE0 64 -#define CLK_AHB_DE_FE1 65 -#define CLK_AHB_GMAC 66 -#define CLK_AHB_MP 67 -#define CLK_AHB_GPU 68 - -/* APB0 Gates */ -#define CLK_APB0_CODEC 69 -#define CLK_APB0_SPDIF 70 -#define CLK_APB0_I2S0 71 -#define CLK_APB0_AC97 72 -#define CLK_APB0_I2S1 73 -#define CLK_APB0_PIO 74 -#define CLK_APB0_IR0 75 -#define CLK_APB0_IR1 76 -#define CLK_APB0_I2S2 77 -#define CLK_APB0_KEYPAD 78 - -/* APB1 Gates */ -#define CLK_APB1_I2C0 79 -#define CLK_APB1_I2C1 80 -#define CLK_APB1_I2C2 81 -#define CLK_APB1_I2C3 82 -#define CLK_APB1_CAN 83 -#define CLK_APB1_SCR 84 -#define CLK_APB1_PS20 85 -#define CLK_APB1_PS21 86 -#define CLK_APB1_I2C4 87 -#define CLK_APB1_UART0 88 -#define CLK_APB1_UART1 89 -#define CLK_APB1_UART2 90 -#define CLK_APB1_UART3 91 -#define CLK_APB1_UART4 92 -#define CLK_APB1_UART5 93 -#define CLK_APB1_UART6 94 -#define CLK_APB1_UART7 95 - -/* IP clocks */ -#define CLK_NAND 96 -#define CLK_MS 97 -#define CLK_MMC0 98 -#define CLK_MMC0_OUTPUT 99 -#define CLK_MMC0_SAMPLE 100 -#define CLK_MMC1 101 -#define CLK_MMC1_OUTPUT 102 -#define CLK_MMC1_SAMPLE 103 -#define CLK_MMC2 104 -#define CLK_MMC2_OUTPUT 105 -#define CLK_MMC2_SAMPLE 106 -#define CLK_MMC3 107 -#define CLK_MMC3_OUTPUT 108 -#define CLK_MMC3_SAMPLE 109 -#define CLK_TS 110 -#define CLK_SS 111 -#define CLK_SPI0 112 -#define CLK_SPI1 113 -#define CLK_SPI2 114 -#define CLK_PATA 115 -#define CLK_IR0 116 -#define CLK_IR1 117 -#define CLK_I2S0 118 -#define CLK_AC97 119 -#define CLK_SPDIF 120 -#define CLK_KEYPAD 121 -#define CLK_SATA 122 -#define CLK_USB_OHCI0 123 -#define CLK_USB_OHCI1 124 -#define CLK_USB_PHY 125 -#define CLK_GPS 126 -#define CLK_SPI3 127 -#define CLK_I2S1 128 -#define CLK_I2S2 129 - -/* DRAM Gates */ -#define CLK_DRAM_VE 130 -#define CLK_DRAM_CSI0 131 -#define CLK_DRAM_CSI1 132 -#define CLK_DRAM_TS 133 -#define CLK_DRAM_TVD 134 -#define CLK_DRAM_TVE0 135 -#define CLK_DRAM_TVE1 136 -#define CLK_DRAM_OUT 137 -#define CLK_DRAM_DE_FE1 138 -#define CLK_DRAM_DE_FE0 139 -#define CLK_DRAM_DE_BE0 140 -#define CLK_DRAM_DE_BE1 141 -#define CLK_DRAM_MP 142 -#define CLK_DRAM_ACE 143 - -/* Display Engine Clocks */ -#define CLK_DE_BE0 144 -#define CLK_DE_BE1 145 -#define CLK_DE_FE0 146 -#define CLK_DE_FE1 147 -#define CLK_DE_MP 148 -#define CLK_TCON0_CH0 149 -#define CLK_TCON1_CH0 150 -#define CLK_CSI_SCLK 151 -#define CLK_TVD_SCLK2 152 -#define CLK_TVD 153 -#define CLK_TCON0_CH1_SCLK2 154 -#define CLK_TCON0_CH1 155 -#define CLK_TCON1_CH1_SCLK2 156 -#define CLK_TCON1_CH1 157 -#define CLK_CSI0 158 -#define CLK_CSI1 159 -#define CLK_CODEC 160 -#define CLK_VE 161 -#define CLK_AVS 162 -#define CLK_ACE 163 -#define CLK_HDMI 164 -#define CLK_GPU 165 - -#endif /* _DT_BINDINGS_CLK_SUN4I_A10_H_ */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/sun4i-a10-pll2.h b/sys/gnu/dts/include/dt-bindings/clock/sun4i-a10-pll2.h deleted file mode 100644 index 071c8112d53..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/sun4i-a10-pll2.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright 2015 Maxime Ripard - * - * Maxime Ripard - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef __DT_BINDINGS_CLOCK_SUN4I_A10_PLL2_H_ -#define __DT_BINDINGS_CLOCK_SUN4I_A10_PLL2_H_ - -#define SUN4I_A10_PLL2_1X 0 -#define SUN4I_A10_PLL2_2X 1 -#define SUN4I_A10_PLL2_4X 2 -#define SUN4I_A10_PLL2_8X 3 - -#endif /* __DT_BINDINGS_CLOCK_SUN4I_A10_PLL2_H_ */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/sun50i-a64-ccu.h b/sys/gnu/dts/include/dt-bindings/clock/sun50i-a64-ccu.h deleted file mode 100644 index e512a1c9b0f..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/sun50i-a64-ccu.h +++ /dev/null @@ -1,138 +0,0 @@ -/* - * Copyright (C) 2016 Maxime Ripard - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_CLK_SUN50I_A64_H_ -#define _DT_BINDINGS_CLK_SUN50I_A64_H_ - -#define CLK_PLL_VIDEO0 7 -#define CLK_PLL_PERIPH0 11 - -#define CLK_CPUX 21 -#define CLK_BUS_MIPI_DSI 28 -#define CLK_BUS_CE 29 -#define CLK_BUS_DMA 30 -#define CLK_BUS_MMC0 31 -#define CLK_BUS_MMC1 32 -#define CLK_BUS_MMC2 33 -#define CLK_BUS_NAND 34 -#define CLK_BUS_DRAM 35 -#define CLK_BUS_EMAC 36 -#define CLK_BUS_TS 37 -#define CLK_BUS_HSTIMER 38 -#define CLK_BUS_SPI0 39 -#define CLK_BUS_SPI1 40 -#define CLK_BUS_OTG 41 -#define CLK_BUS_EHCI0 42 -#define CLK_BUS_EHCI1 43 -#define CLK_BUS_OHCI0 44 -#define CLK_BUS_OHCI1 45 -#define CLK_BUS_VE 46 -#define CLK_BUS_TCON0 47 -#define CLK_BUS_TCON1 48 -#define CLK_BUS_DEINTERLACE 49 -#define CLK_BUS_CSI 50 -#define CLK_BUS_HDMI 51 -#define CLK_BUS_DE 52 -#define CLK_BUS_GPU 53 -#define CLK_BUS_MSGBOX 54 -#define CLK_BUS_SPINLOCK 55 -#define CLK_BUS_CODEC 56 -#define CLK_BUS_SPDIF 57 -#define CLK_BUS_PIO 58 -#define CLK_BUS_THS 59 -#define CLK_BUS_I2S0 60 -#define CLK_BUS_I2S1 61 -#define CLK_BUS_I2S2 62 -#define CLK_BUS_I2C0 63 -#define CLK_BUS_I2C1 64 -#define CLK_BUS_I2C2 65 -#define CLK_BUS_SCR 66 -#define CLK_BUS_UART0 67 -#define CLK_BUS_UART1 68 -#define CLK_BUS_UART2 69 -#define CLK_BUS_UART3 70 -#define CLK_BUS_UART4 71 -#define CLK_BUS_DBG 72 -#define CLK_THS 73 -#define CLK_NAND 74 -#define CLK_MMC0 75 -#define CLK_MMC1 76 -#define CLK_MMC2 77 -#define CLK_TS 78 -#define CLK_CE 79 -#define CLK_SPI0 80 -#define CLK_SPI1 81 -#define CLK_I2S0 82 -#define CLK_I2S1 83 -#define CLK_I2S2 84 -#define CLK_SPDIF 85 -#define CLK_USB_PHY0 86 -#define CLK_USB_PHY1 87 -#define CLK_USB_HSIC 88 -#define CLK_USB_HSIC_12M 89 - -#define CLK_USB_OHCI0 91 - -#define CLK_USB_OHCI1 93 - -#define CLK_DRAM_VE 95 -#define CLK_DRAM_CSI 96 -#define CLK_DRAM_DEINTERLACE 97 -#define CLK_DRAM_TS 98 -#define CLK_DE 99 -#define CLK_TCON0 100 -#define CLK_TCON1 101 -#define CLK_DEINTERLACE 102 -#define CLK_CSI_MISC 103 -#define CLK_CSI_SCLK 104 -#define CLK_CSI_MCLK 105 -#define CLK_VE 106 -#define CLK_AC_DIG 107 -#define CLK_AC_DIG_4X 108 -#define CLK_AVS 109 -#define CLK_HDMI 110 -#define CLK_HDMI_DDC 111 - -#define CLK_DSI_DPHY 113 -#define CLK_GPU 114 - -#endif /* _DT_BINDINGS_CLK_SUN50I_H_ */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/sun50i-h6-ccu.h b/sys/gnu/dts/include/dt-bindings/clock/sun50i-h6-ccu.h deleted file mode 100644 index a1545cd60e7..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/sun50i-h6-ccu.h +++ /dev/null @@ -1,125 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ or MIT) -/* - * Copyright (C) 2017 Icenowy Zheng - */ - -#ifndef _DT_BINDINGS_CLK_SUN50I_H6_H_ -#define _DT_BINDINGS_CLK_SUN50I_H6_H_ - -#define CLK_PLL_PERIPH0 3 - -#define CLK_CPUX 21 - -#define CLK_APB1 26 - -#define CLK_DE 29 -#define CLK_BUS_DE 30 -#define CLK_DEINTERLACE 31 -#define CLK_BUS_DEINTERLACE 32 -#define CLK_GPU 33 -#define CLK_BUS_GPU 34 -#define CLK_CE 35 -#define CLK_BUS_CE 36 -#define CLK_VE 37 -#define CLK_BUS_VE 38 -#define CLK_EMCE 39 -#define CLK_BUS_EMCE 40 -#define CLK_VP9 41 -#define CLK_BUS_VP9 42 -#define CLK_BUS_DMA 43 -#define CLK_BUS_MSGBOX 44 -#define CLK_BUS_SPINLOCK 45 -#define CLK_BUS_HSTIMER 46 -#define CLK_AVS 47 -#define CLK_BUS_DBG 48 -#define CLK_BUS_PSI 49 -#define CLK_BUS_PWM 50 -#define CLK_BUS_IOMMU 51 - -#define CLK_MBUS_DMA 53 -#define CLK_MBUS_VE 54 -#define CLK_MBUS_CE 55 -#define CLK_MBUS_TS 56 -#define CLK_MBUS_NAND 57 -#define CLK_MBUS_CSI 58 -#define CLK_MBUS_DEINTERLACE 59 - -#define CLK_NAND0 61 -#define CLK_NAND1 62 -#define CLK_BUS_NAND 63 -#define CLK_MMC0 64 -#define CLK_MMC1 65 -#define CLK_MMC2 66 -#define CLK_BUS_MMC0 67 -#define CLK_BUS_MMC1 68 -#define CLK_BUS_MMC2 69 -#define CLK_BUS_UART0 70 -#define CLK_BUS_UART1 71 -#define CLK_BUS_UART2 72 -#define CLK_BUS_UART3 73 -#define CLK_BUS_I2C0 74 -#define CLK_BUS_I2C1 75 -#define CLK_BUS_I2C2 76 -#define CLK_BUS_I2C3 77 -#define CLK_BUS_SCR0 78 -#define CLK_BUS_SCR1 79 -#define CLK_SPI0 80 -#define CLK_SPI1 81 -#define CLK_BUS_SPI0 82 -#define CLK_BUS_SPI1 83 -#define CLK_BUS_EMAC 84 -#define CLK_TS 85 -#define CLK_BUS_TS 86 -#define CLK_IR_TX 87 -#define CLK_BUS_IR_TX 88 -#define CLK_BUS_THS 89 -#define CLK_I2S3 90 -#define CLK_I2S0 91 -#define CLK_I2S1 92 -#define CLK_I2S2 93 -#define CLK_BUS_I2S0 94 -#define CLK_BUS_I2S1 95 -#define CLK_BUS_I2S2 96 -#define CLK_BUS_I2S3 97 -#define CLK_SPDIF 98 -#define CLK_BUS_SPDIF 99 -#define CLK_DMIC 100 -#define CLK_BUS_DMIC 101 -#define CLK_AUDIO_HUB 102 -#define CLK_BUS_AUDIO_HUB 103 -#define CLK_USB_OHCI0 104 -#define CLK_USB_PHY0 105 -#define CLK_USB_PHY1 106 -#define CLK_USB_OHCI3 107 -#define CLK_USB_PHY3 108 -#define CLK_USB_HSIC_12M 109 -#define CLK_USB_HSIC 110 -#define CLK_BUS_OHCI0 111 -#define CLK_BUS_OHCI3 112 -#define CLK_BUS_EHCI0 113 -#define CLK_BUS_XHCI 114 -#define CLK_BUS_EHCI3 115 -#define CLK_BUS_OTG 116 -#define CLK_PCIE_REF_100M 117 -#define CLK_PCIE_REF 118 -#define CLK_PCIE_REF_OUT 119 -#define CLK_PCIE_MAXI 120 -#define CLK_PCIE_AUX 121 -#define CLK_BUS_PCIE 122 -#define CLK_HDMI 123 -#define CLK_HDMI_SLOW 124 -#define CLK_HDMI_CEC 125 -#define CLK_BUS_HDMI 126 -#define CLK_BUS_TCON_TOP 127 -#define CLK_TCON_LCD0 128 -#define CLK_BUS_TCON_LCD0 129 -#define CLK_TCON_TV0 130 -#define CLK_BUS_TCON_TV0 131 -#define CLK_CSI_CCI 132 -#define CLK_CSI_TOP 133 -#define CLK_CSI_MCLK 134 -#define CLK_BUS_CSI 135 -#define CLK_HDCP 136 -#define CLK_BUS_HDCP 137 - -#endif /* _DT_BINDINGS_CLK_SUN50I_H6_H_ */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/sun50i-h6-r-ccu.h b/sys/gnu/dts/include/dt-bindings/clock/sun50i-h6-r-ccu.h deleted file mode 100644 index 76136132a13..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/sun50i-h6-r-ccu.h +++ /dev/null @@ -1,24 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2017 Icenowy Zheng - */ - -#ifndef _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_ -#define _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_ - -#define CLK_AR100 0 - -#define CLK_R_APB1 2 - -#define CLK_R_APB1_TIMER 4 -#define CLK_R_APB1_TWD 5 -#define CLK_R_APB1_PWM 6 -#define CLK_R_APB2_UART 7 -#define CLK_R_APB2_I2C 8 -#define CLK_R_APB1_IR 9 -#define CLK_R_APB1_W1 10 - -#define CLK_IR 11 -#define CLK_W1 12 - -#endif /* _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_ */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/sun5i-ccu.h b/sys/gnu/dts/include/dt-bindings/clock/sun5i-ccu.h deleted file mode 100644 index 75fe5619c3d..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/sun5i-ccu.h +++ /dev/null @@ -1,97 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright 2016 Maxime Ripard - * - * Maxime Ripard - */ - -#ifndef _DT_BINDINGS_CLK_SUN5I_H_ -#define _DT_BINDINGS_CLK_SUN5I_H_ - -#define CLK_HOSC 1 - -#define CLK_PLL_VIDEO0_2X 9 - -#define CLK_PLL_VIDEO1_2X 16 -#define CLK_CPU 17 - -#define CLK_AHB_OTG 23 -#define CLK_AHB_EHCI 24 -#define CLK_AHB_OHCI 25 -#define CLK_AHB_SS 26 -#define CLK_AHB_DMA 27 -#define CLK_AHB_BIST 28 -#define CLK_AHB_MMC0 29 -#define CLK_AHB_MMC1 30 -#define CLK_AHB_MMC2 31 -#define CLK_AHB_NAND 32 -#define CLK_AHB_SDRAM 33 -#define CLK_AHB_EMAC 34 -#define CLK_AHB_TS 35 -#define CLK_AHB_SPI0 36 -#define CLK_AHB_SPI1 37 -#define CLK_AHB_SPI2 38 -#define CLK_AHB_GPS 39 -#define CLK_AHB_HSTIMER 40 -#define CLK_AHB_VE 41 -#define CLK_AHB_TVE 42 -#define CLK_AHB_LCD 43 -#define CLK_AHB_CSI 44 -#define CLK_AHB_HDMI 45 -#define CLK_AHB_DE_BE 46 -#define CLK_AHB_DE_FE 47 -#define CLK_AHB_IEP 48 -#define CLK_AHB_GPU 49 -#define CLK_APB0_CODEC 50 -#define CLK_APB0_SPDIF 51 -#define CLK_APB0_I2S 52 -#define CLK_APB0_PIO 53 -#define CLK_APB0_IR 54 -#define CLK_APB0_KEYPAD 55 -#define CLK_APB1_I2C0 56 -#define CLK_APB1_I2C1 57 -#define CLK_APB1_I2C2 58 -#define CLK_APB1_UART0 59 -#define CLK_APB1_UART1 60 -#define CLK_APB1_UART2 61 -#define CLK_APB1_UART3 62 -#define CLK_NAND 63 -#define CLK_MMC0 64 -#define CLK_MMC1 65 -#define CLK_MMC2 66 -#define CLK_TS 67 -#define CLK_SS 68 -#define CLK_SPI0 69 -#define CLK_SPI1 70 -#define CLK_SPI2 71 -#define CLK_IR 72 -#define CLK_I2S 73 -#define CLK_SPDIF 74 -#define CLK_KEYPAD 75 -#define CLK_USB_OHCI 76 -#define CLK_USB_PHY0 77 -#define CLK_USB_PHY1 78 -#define CLK_GPS 79 -#define CLK_DRAM_VE 80 -#define CLK_DRAM_CSI 81 -#define CLK_DRAM_TS 82 -#define CLK_DRAM_TVE 83 -#define CLK_DRAM_DE_FE 84 -#define CLK_DRAM_DE_BE 85 -#define CLK_DRAM_ACE 86 -#define CLK_DRAM_IEP 87 -#define CLK_DE_BE 88 -#define CLK_DE_FE 89 -#define CLK_TCON_CH0 90 - -#define CLK_TCON_CH1 92 -#define CLK_CSI 93 -#define CLK_VE 94 -#define CLK_CODEC 95 -#define CLK_AVS 96 -#define CLK_HDMI 97 -#define CLK_GPU 98 -#define CLK_MBUS 99 -#define CLK_IEP 100 - -#endif /* _DT_BINDINGS_CLK_SUN5I_H_ */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/sun6i-a31-ccu.h b/sys/gnu/dts/include/dt-bindings/clock/sun6i-a31-ccu.h deleted file mode 100644 index 39878d9dce9..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/sun6i-a31-ccu.h +++ /dev/null @@ -1,193 +0,0 @@ -/* - * Copyright (C) 2016 Chen-Yu Tsai - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_CLK_SUN6I_A31_H_ -#define _DT_BINDINGS_CLK_SUN6I_A31_H_ - -#define CLK_PLL_VIDEO0_2X 7 - -#define CLK_PLL_PERIPH 10 - -#define CLK_PLL_VIDEO1_2X 13 - -#define CLK_PLL_MIPI 15 - -#define CLK_CPU 18 - -#define CLK_AHB1_MIPIDSI 23 -#define CLK_AHB1_SS 24 -#define CLK_AHB1_DMA 25 -#define CLK_AHB1_MMC0 26 -#define CLK_AHB1_MMC1 27 -#define CLK_AHB1_MMC2 28 -#define CLK_AHB1_MMC3 29 -#define CLK_AHB1_NAND1 30 -#define CLK_AHB1_NAND0 31 -#define CLK_AHB1_SDRAM 32 -#define CLK_AHB1_EMAC 33 -#define CLK_AHB1_TS 34 -#define CLK_AHB1_HSTIMER 35 -#define CLK_AHB1_SPI0 36 -#define CLK_AHB1_SPI1 37 -#define CLK_AHB1_SPI2 38 -#define CLK_AHB1_SPI3 39 -#define CLK_AHB1_OTG 40 -#define CLK_AHB1_EHCI0 41 -#define CLK_AHB1_EHCI1 42 -#define CLK_AHB1_OHCI0 43 -#define CLK_AHB1_OHCI1 44 -#define CLK_AHB1_OHCI2 45 -#define CLK_AHB1_VE 46 -#define CLK_AHB1_LCD0 47 -#define CLK_AHB1_LCD1 48 -#define CLK_AHB1_CSI 49 -#define CLK_AHB1_HDMI 50 -#define CLK_AHB1_BE0 51 -#define CLK_AHB1_BE1 52 -#define CLK_AHB1_FE0 53 -#define CLK_AHB1_FE1 54 -#define CLK_AHB1_MP 55 -#define CLK_AHB1_GPU 56 -#define CLK_AHB1_DEU0 57 -#define CLK_AHB1_DEU1 58 -#define CLK_AHB1_DRC0 59 -#define CLK_AHB1_DRC1 60 - -#define CLK_APB1_CODEC 61 -#define CLK_APB1_SPDIF 62 -#define CLK_APB1_DIGITAL_MIC 63 -#define CLK_APB1_PIO 64 -#define CLK_APB1_DAUDIO0 65 -#define CLK_APB1_DAUDIO1 66 - -#define CLK_APB2_I2C0 67 -#define CLK_APB2_I2C1 68 -#define CLK_APB2_I2C2 69 -#define CLK_APB2_I2C3 70 -#define CLK_APB2_UART0 71 -#define CLK_APB2_UART1 72 -#define CLK_APB2_UART2 73 -#define CLK_APB2_UART3 74 -#define CLK_APB2_UART4 75 -#define CLK_APB2_UART5 76 - -#define CLK_NAND0 77 -#define CLK_NAND1 78 -#define CLK_MMC0 79 -#define CLK_MMC0_SAMPLE 80 -#define CLK_MMC0_OUTPUT 81 -#define CLK_MMC1 82 -#define CLK_MMC1_SAMPLE 83 -#define CLK_MMC1_OUTPUT 84 -#define CLK_MMC2 85 -#define CLK_MMC2_SAMPLE 86 -#define CLK_MMC2_OUTPUT 87 -#define CLK_MMC3 88 -#define CLK_MMC3_SAMPLE 89 -#define CLK_MMC3_OUTPUT 90 -#define CLK_TS 91 -#define CLK_SS 92 -#define CLK_SPI0 93 -#define CLK_SPI1 94 -#define CLK_SPI2 95 -#define CLK_SPI3 96 -#define CLK_DAUDIO0 97 -#define CLK_DAUDIO1 98 -#define CLK_SPDIF 99 -#define CLK_USB_PHY0 100 -#define CLK_USB_PHY1 101 -#define CLK_USB_PHY2 102 -#define CLK_USB_OHCI0 103 -#define CLK_USB_OHCI1 104 -#define CLK_USB_OHCI2 105 - -#define CLK_DRAM_VE 110 -#define CLK_DRAM_CSI_ISP 111 -#define CLK_DRAM_TS 112 -#define CLK_DRAM_DRC0 113 -#define CLK_DRAM_DRC1 114 -#define CLK_DRAM_DEU0 115 -#define CLK_DRAM_DEU1 116 -#define CLK_DRAM_FE0 117 -#define CLK_DRAM_FE1 118 -#define CLK_DRAM_BE0 119 -#define CLK_DRAM_BE1 120 -#define CLK_DRAM_MP 121 - -#define CLK_BE0 122 -#define CLK_BE1 123 -#define CLK_FE0 124 -#define CLK_FE1 125 -#define CLK_MP 126 -#define CLK_LCD0_CH0 127 -#define CLK_LCD1_CH0 128 -#define CLK_LCD0_CH1 129 -#define CLK_LCD1_CH1 130 -#define CLK_CSI0_SCLK 131 -#define CLK_CSI0_MCLK 132 -#define CLK_CSI1_MCLK 133 -#define CLK_VE 134 -#define CLK_CODEC 135 -#define CLK_AVS 136 -#define CLK_DIGITAL_MIC 137 -#define CLK_HDMI 138 -#define CLK_HDMI_DDC 139 -#define CLK_PS 140 - -#define CLK_MIPI_DSI 143 -#define CLK_MIPI_DSI_DPHY 144 -#define CLK_MIPI_CSI_DPHY 145 -#define CLK_IEP_DRC0 146 -#define CLK_IEP_DRC1 147 -#define CLK_IEP_DEU0 148 -#define CLK_IEP_DEU1 149 -#define CLK_GPU_CORE 150 -#define CLK_GPU_MEMORY 151 -#define CLK_GPU_HYD 152 -#define CLK_ATS 153 -#define CLK_TRACE 154 - -#define CLK_OUT_A 155 -#define CLK_OUT_B 156 -#define CLK_OUT_C 157 - -#endif /* _DT_BINDINGS_CLK_SUN6I_A31_H_ */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/sun7i-a20-ccu.h b/sys/gnu/dts/include/dt-bindings/clock/sun7i-a20-ccu.h deleted file mode 100644 index 045a5178da0..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/sun7i-a20-ccu.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright (C) 2017 Priit Laes - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_CLK_SUN7I_A20_H_ -#define _DT_BINDINGS_CLK_SUN7I_A20_H_ - -#include - -#define CLK_MBUS 166 -#define CLK_HDMI1_SLOW 167 -#define CLK_HDMI1 168 -#define CLK_OUT_A 169 -#define CLK_OUT_B 170 - -#endif /* _DT_BINDINGS_CLK_SUN7I_A20_H_ */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/sun8i-a23-a33-ccu.h b/sys/gnu/dts/include/dt-bindings/clock/sun8i-a23-a33-ccu.h deleted file mode 100644 index eb524d0bbd0..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/sun8i-a23-a33-ccu.h +++ /dev/null @@ -1,129 +0,0 @@ -/* - * Copyright (C) 2016 Maxime Ripard - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_CLK_SUN8I_A23_A33_H_ -#define _DT_BINDINGS_CLK_SUN8I_A23_A33_H_ - -#define CLK_PLL_MIPI 13 - -#define CLK_CPUX 18 - -#define CLK_BUS_MIPI_DSI 23 -#define CLK_BUS_SS 24 -#define CLK_BUS_DMA 25 -#define CLK_BUS_MMC0 26 -#define CLK_BUS_MMC1 27 -#define CLK_BUS_MMC2 28 -#define CLK_BUS_NAND 29 -#define CLK_BUS_DRAM 30 -#define CLK_BUS_HSTIMER 31 -#define CLK_BUS_SPI0 32 -#define CLK_BUS_SPI1 33 -#define CLK_BUS_OTG 34 -#define CLK_BUS_EHCI 35 -#define CLK_BUS_OHCI 36 -#define CLK_BUS_VE 37 -#define CLK_BUS_LCD 38 -#define CLK_BUS_CSI 39 -#define CLK_BUS_DE_BE 40 -#define CLK_BUS_DE_FE 41 -#define CLK_BUS_GPU 42 -#define CLK_BUS_MSGBOX 43 -#define CLK_BUS_SPINLOCK 44 -#define CLK_BUS_DRC 45 -#define CLK_BUS_SAT 46 -#define CLK_BUS_CODEC 47 -#define CLK_BUS_PIO 48 -#define CLK_BUS_I2S0 49 -#define CLK_BUS_I2S1 50 -#define CLK_BUS_I2C0 51 -#define CLK_BUS_I2C1 52 -#define CLK_BUS_I2C2 53 -#define CLK_BUS_UART0 54 -#define CLK_BUS_UART1 55 -#define CLK_BUS_UART2 56 -#define CLK_BUS_UART3 57 -#define CLK_BUS_UART4 58 -#define CLK_NAND 59 -#define CLK_MMC0 60 -#define CLK_MMC0_SAMPLE 61 -#define CLK_MMC0_OUTPUT 62 -#define CLK_MMC1 63 -#define CLK_MMC1_SAMPLE 64 -#define CLK_MMC1_OUTPUT 65 -#define CLK_MMC2 66 -#define CLK_MMC2_SAMPLE 67 -#define CLK_MMC2_OUTPUT 68 -#define CLK_SS 69 -#define CLK_SPI0 70 -#define CLK_SPI1 71 -#define CLK_I2S0 72 -#define CLK_I2S1 73 -#define CLK_USB_PHY0 74 -#define CLK_USB_PHY1 75 -#define CLK_USB_HSIC 76 -#define CLK_USB_HSIC_12M 77 -#define CLK_USB_OHCI 78 - -#define CLK_DRAM_VE 80 -#define CLK_DRAM_CSI 81 -#define CLK_DRAM_DRC 82 -#define CLK_DRAM_DE_FE 83 -#define CLK_DRAM_DE_BE 84 -#define CLK_DE_BE 85 -#define CLK_DE_FE 86 -#define CLK_LCD_CH0 87 -#define CLK_LCD_CH1 88 -#define CLK_CSI_SCLK 89 -#define CLK_CSI_MCLK 90 -#define CLK_VE 91 -#define CLK_AC_DIG 92 -#define CLK_AC_DIG_4X 93 -#define CLK_AVS 94 - -#define CLK_DSI_SCLK 96 -#define CLK_DSI_DPHY 97 -#define CLK_DRC 98 -#define CLK_GPU 99 -#define CLK_ATS 100 - -#endif /* _DT_BINDINGS_CLK_SUN8I_A23_A33_H_ */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/sun8i-a83t-ccu.h b/sys/gnu/dts/include/dt-bindings/clock/sun8i-a83t-ccu.h deleted file mode 100644 index 78af5085f63..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/sun8i-a83t-ccu.h +++ /dev/null @@ -1,140 +0,0 @@ -/* - * Copyright (C) 2017 Chen-Yu Tsai - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_CLOCK_SUN8I_A83T_CCU_H_ -#define _DT_BINDINGS_CLOCK_SUN8I_A83T_CCU_H_ - -#define CLK_PLL_PERIPH 6 - -#define CLK_PLL_DE 9 - -#define CLK_C0CPUX 11 -#define CLK_C1CPUX 12 - -#define CLK_BUS_MIPI_DSI 19 -#define CLK_BUS_SS 20 -#define CLK_BUS_DMA 21 -#define CLK_BUS_MMC0 22 -#define CLK_BUS_MMC1 23 -#define CLK_BUS_MMC2 24 -#define CLK_BUS_NAND 25 -#define CLK_BUS_DRAM 26 -#define CLK_BUS_EMAC 27 -#define CLK_BUS_HSTIMER 28 -#define CLK_BUS_SPI0 29 -#define CLK_BUS_SPI1 30 -#define CLK_BUS_OTG 31 -#define CLK_BUS_EHCI0 32 -#define CLK_BUS_EHCI1 33 -#define CLK_BUS_OHCI0 34 - -#define CLK_BUS_VE 35 -#define CLK_BUS_TCON0 36 -#define CLK_BUS_TCON1 37 -#define CLK_BUS_CSI 38 -#define CLK_BUS_HDMI 39 -#define CLK_BUS_DE 40 -#define CLK_BUS_GPU 41 -#define CLK_BUS_MSGBOX 42 -#define CLK_BUS_SPINLOCK 43 - -#define CLK_BUS_SPDIF 44 -#define CLK_BUS_PIO 45 -#define CLK_BUS_I2S0 46 -#define CLK_BUS_I2S1 47 -#define CLK_BUS_I2S2 48 -#define CLK_BUS_TDM 49 - -#define CLK_BUS_I2C0 50 -#define CLK_BUS_I2C1 51 -#define CLK_BUS_I2C2 52 -#define CLK_BUS_UART0 53 -#define CLK_BUS_UART1 54 -#define CLK_BUS_UART2 55 -#define CLK_BUS_UART3 56 -#define CLK_BUS_UART4 57 - -#define CLK_NAND 59 -#define CLK_MMC0 60 -#define CLK_MMC0_SAMPLE 61 -#define CLK_MMC0_OUTPUT 62 -#define CLK_MMC1 63 -#define CLK_MMC1_SAMPLE 64 -#define CLK_MMC1_OUTPUT 65 -#define CLK_MMC2 66 -#define CLK_MMC2_SAMPLE 67 -#define CLK_MMC2_OUTPUT 68 -#define CLK_SS 69 -#define CLK_SPI0 70 -#define CLK_SPI1 71 -#define CLK_I2S0 72 -#define CLK_I2S1 73 -#define CLK_I2S2 74 -#define CLK_TDM 75 -#define CLK_SPDIF 76 -#define CLK_USB_PHY0 77 -#define CLK_USB_PHY1 78 -#define CLK_USB_HSIC 79 -#define CLK_USB_HSIC_12M 80 -#define CLK_USB_OHCI0 81 - -#define CLK_DRAM_VE 83 -#define CLK_DRAM_CSI 84 - -#define CLK_TCON0 85 -#define CLK_TCON1 86 -#define CLK_CSI_MISC 87 -#define CLK_MIPI_CSI 88 -#define CLK_CSI_MCLK 89 -#define CLK_CSI_SCLK 90 -#define CLK_VE 91 -#define CLK_AVS 92 -#define CLK_HDMI 93 -#define CLK_HDMI_SLOW 94 - -#define CLK_MIPI_DSI0 96 -#define CLK_MIPI_DSI1 97 -#define CLK_GPU_CORE 98 -#define CLK_GPU_MEMORY 99 -#define CLK_GPU_HYD 100 - -#endif /* _DT_BINDINGS_CLOCK_SUN8I_A83T_CCU_H_ */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/sun8i-de2.h b/sys/gnu/dts/include/dt-bindings/clock/sun8i-de2.h deleted file mode 100644 index 7768f73b051..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/sun8i-de2.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * Copyright (C) 2016 Icenowy Zheng - * - * SPDX-License-Identifier: (GPL-2.0+ OR MIT) - */ - -#ifndef _DT_BINDINGS_CLOCK_SUN8I_DE2_H_ -#define _DT_BINDINGS_CLOCK_SUN8I_DE2_H_ - -#define CLK_BUS_MIXER0 0 -#define CLK_BUS_MIXER1 1 -#define CLK_BUS_WB 2 - -#define CLK_MIXER0 6 -#define CLK_MIXER1 7 -#define CLK_WB 8 - -#define CLK_BUS_ROT 9 -#define CLK_ROT 10 - -#endif /* _DT_BINDINGS_CLOCK_SUN8I_DE2_H_ */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/sun8i-h3-ccu.h b/sys/gnu/dts/include/dt-bindings/clock/sun8i-h3-ccu.h deleted file mode 100644 index 30d2d15373a..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/sun8i-h3-ccu.h +++ /dev/null @@ -1,152 +0,0 @@ -/* - * Copyright (C) 2016 Maxime Ripard - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_CLK_SUN8I_H3_H_ -#define _DT_BINDINGS_CLK_SUN8I_H3_H_ - -#define CLK_PLL_VIDEO 6 - -#define CLK_PLL_PERIPH0 9 - -#define CLK_CPUX 14 - -#define CLK_BUS_CE 20 -#define CLK_BUS_DMA 21 -#define CLK_BUS_MMC0 22 -#define CLK_BUS_MMC1 23 -#define CLK_BUS_MMC2 24 -#define CLK_BUS_NAND 25 -#define CLK_BUS_DRAM 26 -#define CLK_BUS_EMAC 27 -#define CLK_BUS_TS 28 -#define CLK_BUS_HSTIMER 29 -#define CLK_BUS_SPI0 30 -#define CLK_BUS_SPI1 31 -#define CLK_BUS_OTG 32 -#define CLK_BUS_EHCI0 33 -#define CLK_BUS_EHCI1 34 -#define CLK_BUS_EHCI2 35 -#define CLK_BUS_EHCI3 36 -#define CLK_BUS_OHCI0 37 -#define CLK_BUS_OHCI1 38 -#define CLK_BUS_OHCI2 39 -#define CLK_BUS_OHCI3 40 -#define CLK_BUS_VE 41 -#define CLK_BUS_TCON0 42 -#define CLK_BUS_TCON1 43 -#define CLK_BUS_DEINTERLACE 44 -#define CLK_BUS_CSI 45 -#define CLK_BUS_TVE 46 -#define CLK_BUS_HDMI 47 -#define CLK_BUS_DE 48 -#define CLK_BUS_GPU 49 -#define CLK_BUS_MSGBOX 50 -#define CLK_BUS_SPINLOCK 51 -#define CLK_BUS_CODEC 52 -#define CLK_BUS_SPDIF 53 -#define CLK_BUS_PIO 54 -#define CLK_BUS_THS 55 -#define CLK_BUS_I2S0 56 -#define CLK_BUS_I2S1 57 -#define CLK_BUS_I2S2 58 -#define CLK_BUS_I2C0 59 -#define CLK_BUS_I2C1 60 -#define CLK_BUS_I2C2 61 -#define CLK_BUS_UART0 62 -#define CLK_BUS_UART1 63 -#define CLK_BUS_UART2 64 -#define CLK_BUS_UART3 65 -#define CLK_BUS_SCR0 66 -#define CLK_BUS_EPHY 67 -#define CLK_BUS_DBG 68 - -#define CLK_THS 69 -#define CLK_NAND 70 -#define CLK_MMC0 71 -#define CLK_MMC0_SAMPLE 72 -#define CLK_MMC0_OUTPUT 73 -#define CLK_MMC1 74 -#define CLK_MMC1_SAMPLE 75 -#define CLK_MMC1_OUTPUT 76 -#define CLK_MMC2 77 -#define CLK_MMC2_SAMPLE 78 -#define CLK_MMC2_OUTPUT 79 -#define CLK_TS 80 -#define CLK_CE 81 -#define CLK_SPI0 82 -#define CLK_SPI1 83 -#define CLK_I2S0 84 -#define CLK_I2S1 85 -#define CLK_I2S2 86 -#define CLK_SPDIF 87 -#define CLK_USB_PHY0 88 -#define CLK_USB_PHY1 89 -#define CLK_USB_PHY2 90 -#define CLK_USB_PHY3 91 -#define CLK_USB_OHCI0 92 -#define CLK_USB_OHCI1 93 -#define CLK_USB_OHCI2 94 -#define CLK_USB_OHCI3 95 - -#define CLK_DRAM_VE 97 -#define CLK_DRAM_CSI 98 -#define CLK_DRAM_DEINTERLACE 99 -#define CLK_DRAM_TS 100 -#define CLK_DE 101 -#define CLK_TCON0 102 -#define CLK_TVE 103 -#define CLK_DEINTERLACE 104 -#define CLK_CSI_MISC 105 -#define CLK_CSI_SCLK 106 -#define CLK_CSI_MCLK 107 -#define CLK_VE 108 -#define CLK_AC_DIG 109 -#define CLK_AVS 110 -#define CLK_HDMI 111 -#define CLK_HDMI_DDC 112 -#define CLK_MBUS 113 -#define CLK_GPU 114 - -/* New clocks imported in H5 */ -#define CLK_BUS_SCR1 115 - -#endif /* _DT_BINDINGS_CLK_SUN8I_H3_H_ */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/sun8i-r-ccu.h b/sys/gnu/dts/include/dt-bindings/clock/sun8i-r-ccu.h deleted file mode 100644 index 779d20aa0d0..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/sun8i-r-ccu.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Copyright (c) 2016 Icenowy Zheng - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_CLK_SUN8I_R_CCU_H_ -#define _DT_BINDINGS_CLK_SUN8I_R_CCU_H_ - -#define CLK_AR100 0 - -#define CLK_APB0_PIO 3 -#define CLK_APB0_IR 4 -#define CLK_APB0_TIMER 5 -#define CLK_APB0_RSB 6 -#define CLK_APB0_UART 7 -/* 8 is reserved for CLK_APB0_W1 on A31 */ -#define CLK_APB0_I2C 9 -#define CLK_APB0_TWD 10 - -#define CLK_IR 11 - -#endif /* _DT_BINDINGS_CLK_SUN8I_R_CCU_H_ */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/sun8i-r40-ccu.h b/sys/gnu/dts/include/dt-bindings/clock/sun8i-r40-ccu.h deleted file mode 100644 index d7337b55a4e..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/sun8i-r40-ccu.h +++ /dev/null @@ -1,191 +0,0 @@ -/* - * Copyright (C) 2017 Icenowy Zheng - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_CLK_SUN8I_R40_H_ -#define _DT_BINDINGS_CLK_SUN8I_R40_H_ - -#define CLK_PLL_VIDEO0 7 - -#define CLK_PLL_VIDEO1 16 - -#define CLK_CPU 24 - -#define CLK_BUS_MIPI_DSI 29 -#define CLK_BUS_CE 30 -#define CLK_BUS_DMA 31 -#define CLK_BUS_MMC0 32 -#define CLK_BUS_MMC1 33 -#define CLK_BUS_MMC2 34 -#define CLK_BUS_MMC3 35 -#define CLK_BUS_NAND 36 -#define CLK_BUS_DRAM 37 -#define CLK_BUS_EMAC 38 -#define CLK_BUS_TS 39 -#define CLK_BUS_HSTIMER 40 -#define CLK_BUS_SPI0 41 -#define CLK_BUS_SPI1 42 -#define CLK_BUS_SPI2 43 -#define CLK_BUS_SPI3 44 -#define CLK_BUS_SATA 45 -#define CLK_BUS_OTG 46 -#define CLK_BUS_EHCI0 47 -#define CLK_BUS_EHCI1 48 -#define CLK_BUS_EHCI2 49 -#define CLK_BUS_OHCI0 50 -#define CLK_BUS_OHCI1 51 -#define CLK_BUS_OHCI2 52 -#define CLK_BUS_VE 53 -#define CLK_BUS_MP 54 -#define CLK_BUS_DEINTERLACE 55 -#define CLK_BUS_CSI0 56 -#define CLK_BUS_CSI1 57 -#define CLK_BUS_HDMI1 58 -#define CLK_BUS_HDMI0 59 -#define CLK_BUS_DE 60 -#define CLK_BUS_TVE0 61 -#define CLK_BUS_TVE1 62 -#define CLK_BUS_TVE_TOP 63 -#define CLK_BUS_GMAC 64 -#define CLK_BUS_GPU 65 -#define CLK_BUS_TVD0 66 -#define CLK_BUS_TVD1 67 -#define CLK_BUS_TVD2 68 -#define CLK_BUS_TVD3 69 -#define CLK_BUS_TVD_TOP 70 -#define CLK_BUS_TCON_LCD0 71 -#define CLK_BUS_TCON_LCD1 72 -#define CLK_BUS_TCON_TV0 73 -#define CLK_BUS_TCON_TV1 74 -#define CLK_BUS_TCON_TOP 75 -#define CLK_BUS_CODEC 76 -#define CLK_BUS_SPDIF 77 -#define CLK_BUS_AC97 78 -#define CLK_BUS_PIO 79 -#define CLK_BUS_IR0 80 -#define CLK_BUS_IR1 81 -#define CLK_BUS_THS 82 -#define CLK_BUS_KEYPAD 83 -#define CLK_BUS_I2S0 84 -#define CLK_BUS_I2S1 85 -#define CLK_BUS_I2S2 86 -#define CLK_BUS_I2C0 87 -#define CLK_BUS_I2C1 88 -#define CLK_BUS_I2C2 89 -#define CLK_BUS_I2C3 90 -#define CLK_BUS_CAN 91 -#define CLK_BUS_SCR 92 -#define CLK_BUS_PS20 93 -#define CLK_BUS_PS21 94 -#define CLK_BUS_I2C4 95 -#define CLK_BUS_UART0 96 -#define CLK_BUS_UART1 97 -#define CLK_BUS_UART2 98 -#define CLK_BUS_UART3 99 -#define CLK_BUS_UART4 100 -#define CLK_BUS_UART5 101 -#define CLK_BUS_UART6 102 -#define CLK_BUS_UART7 103 -#define CLK_BUS_DBG 104 - -#define CLK_THS 105 -#define CLK_NAND 106 -#define CLK_MMC0 107 -#define CLK_MMC1 108 -#define CLK_MMC2 109 -#define CLK_MMC3 110 -#define CLK_TS 111 -#define CLK_CE 112 -#define CLK_SPI0 113 -#define CLK_SPI1 114 -#define CLK_SPI2 115 -#define CLK_SPI3 116 -#define CLK_I2S0 117 -#define CLK_I2S1 118 -#define CLK_I2S2 119 -#define CLK_AC97 120 -#define CLK_SPDIF 121 -#define CLK_KEYPAD 122 -#define CLK_SATA 123 -#define CLK_USB_PHY0 124 -#define CLK_USB_PHY1 125 -#define CLK_USB_PHY2 126 -#define CLK_USB_OHCI0 127 -#define CLK_USB_OHCI1 128 -#define CLK_USB_OHCI2 129 -#define CLK_IR0 130 -#define CLK_IR1 131 - -#define CLK_DRAM_VE 133 -#define CLK_DRAM_CSI0 134 -#define CLK_DRAM_CSI1 135 -#define CLK_DRAM_TS 136 -#define CLK_DRAM_TVD 137 -#define CLK_DRAM_MP 138 -#define CLK_DRAM_DEINTERLACE 139 -#define CLK_DE 140 -#define CLK_MP 141 -#define CLK_TCON_LCD0 142 -#define CLK_TCON_LCD1 143 -#define CLK_TCON_TV0 144 -#define CLK_TCON_TV1 145 -#define CLK_DEINTERLACE 146 -#define CLK_CSI1_MCLK 147 -#define CLK_CSI_SCLK 148 -#define CLK_CSI0_MCLK 149 -#define CLK_VE 150 -#define CLK_CODEC 151 -#define CLK_AVS 152 -#define CLK_HDMI 153 -#define CLK_HDMI_SLOW 154 -#define CLK_MBUS 155 -#define CLK_DSI_DPHY 156 -#define CLK_TVE0 157 -#define CLK_TVE1 158 -#define CLK_TVD0 159 -#define CLK_TVD1 160 -#define CLK_TVD2 161 -#define CLK_TVD3 162 -#define CLK_GPU 163 -#define CLK_OUTA 164 -#define CLK_OUTB 165 - -#endif /* _DT_BINDINGS_CLK_SUN8I_R40_H_ */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/sun8i-tcon-top.h b/sys/gnu/dts/include/dt-bindings/clock/sun8i-tcon-top.h deleted file mode 100644 index 25164d76783..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/sun8i-tcon-top.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ -/* Copyright (C) 2018 Jernej Skrabec */ - -#ifndef _DT_BINDINGS_CLOCK_SUN8I_TCON_TOP_H_ -#define _DT_BINDINGS_CLOCK_SUN8I_TCON_TOP_H_ - -#define CLK_TCON_TOP_TV0 0 -#define CLK_TCON_TOP_TV1 1 -#define CLK_TCON_TOP_DSI 2 - -#endif /* _DT_BINDINGS_CLOCK_SUN8I_TCON_TOP_H_ */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/sun8i-v3s-ccu.h b/sys/gnu/dts/include/dt-bindings/clock/sun8i-v3s-ccu.h deleted file mode 100644 index 014ac6123d1..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/sun8i-v3s-ccu.h +++ /dev/null @@ -1,111 +0,0 @@ -/* - * Copyright (c) 2016 Icenowy Zheng - * - * Based on sun8i-h3-ccu.h, which is: - * Copyright (C) 2016 Maxime Ripard - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_CLK_SUN8I_V3S_H_ -#define _DT_BINDINGS_CLK_SUN8I_V3S_H_ - -#define CLK_CPU 14 - -#define CLK_BUS_CE 20 -#define CLK_BUS_DMA 21 -#define CLK_BUS_MMC0 22 -#define CLK_BUS_MMC1 23 -#define CLK_BUS_MMC2 24 -#define CLK_BUS_DRAM 25 -#define CLK_BUS_EMAC 26 -#define CLK_BUS_HSTIMER 27 -#define CLK_BUS_SPI0 28 -#define CLK_BUS_OTG 29 -#define CLK_BUS_EHCI0 30 -#define CLK_BUS_OHCI0 31 -#define CLK_BUS_VE 32 -#define CLK_BUS_TCON0 33 -#define CLK_BUS_CSI 34 -#define CLK_BUS_DE 35 -#define CLK_BUS_CODEC 36 -#define CLK_BUS_PIO 37 -#define CLK_BUS_I2C0 38 -#define CLK_BUS_I2C1 39 -#define CLK_BUS_UART0 40 -#define CLK_BUS_UART1 41 -#define CLK_BUS_UART2 42 -#define CLK_BUS_EPHY 43 -#define CLK_BUS_DBG 44 - -#define CLK_MMC0 45 -#define CLK_MMC0_SAMPLE 46 -#define CLK_MMC0_OUTPUT 47 -#define CLK_MMC1 48 -#define CLK_MMC1_SAMPLE 49 -#define CLK_MMC1_OUTPUT 50 -#define CLK_MMC2 51 -#define CLK_MMC2_SAMPLE 52 -#define CLK_MMC2_OUTPUT 53 -#define CLK_CE 54 -#define CLK_SPI0 55 -#define CLK_USB_PHY0 56 -#define CLK_USB_OHCI0 57 - -#define CLK_DRAM_VE 59 -#define CLK_DRAM_CSI 60 -#define CLK_DRAM_EHCI 61 -#define CLK_DRAM_OHCI 62 -#define CLK_DE 63 -#define CLK_TCON0 64 -#define CLK_CSI_MISC 65 -#define CLK_CSI0_MCLK 66 -#define CLK_CSI1_SCLK 67 -#define CLK_CSI1_MCLK 68 -#define CLK_VE 69 -#define CLK_AC_DIG 70 -#define CLK_AVS 71 - -#define CLK_MIPI_CSI 73 - -/* Clocks not available on V3s */ -#define CLK_BUS_I2S0 75 -#define CLK_I2S0 76 - -#endif /* _DT_BINDINGS_CLK_SUN8I_V3S_H_ */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/sun9i-a80-ccu.h b/sys/gnu/dts/include/dt-bindings/clock/sun9i-a80-ccu.h deleted file mode 100644 index 6ea1492a73a..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/sun9i-a80-ccu.h +++ /dev/null @@ -1,162 +0,0 @@ -/* - * Copyright (C) 2016 Chen-Yu Tsai - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_CLOCK_SUN9I_A80_CCU_H_ -#define _DT_BINDINGS_CLOCK_SUN9I_A80_CCU_H_ - -#define CLK_PLL_AUDIO 2 -#define CLK_PLL_PERIPH0 3 - -#define CLK_C0CPUX 12 -#define CLK_C1CPUX 13 - -#define CLK_OUT_A 27 -#define CLK_OUT_B 28 - -#define CLK_NAND0_0 29 -#define CLK_NAND0_1 30 -#define CLK_NAND1_0 31 -#define CLK_NAND1_1 32 -#define CLK_MMC0 33 -#define CLK_MMC0_SAMPLE 34 -#define CLK_MMC0_OUTPUT 35 -#define CLK_MMC1 36 -#define CLK_MMC1_SAMPLE 37 -#define CLK_MMC1_OUTPUT 38 -#define CLK_MMC2 39 -#define CLK_MMC2_SAMPLE 40 -#define CLK_MMC2_OUTPUT 41 -#define CLK_MMC3 42 -#define CLK_MMC3_SAMPLE 43 -#define CLK_MMC3_OUTPUT 44 -#define CLK_TS 45 -#define CLK_SS 46 -#define CLK_SPI0 47 -#define CLK_SPI1 48 -#define CLK_SPI2 49 -#define CLK_SPI3 50 -#define CLK_I2S0 51 -#define CLK_I2S1 52 -#define CLK_SPDIF 53 -#define CLK_SDRAM 54 -#define CLK_DE 55 -#define CLK_EDP 56 -#define CLK_MP 57 -#define CLK_LCD0 58 -#define CLK_LCD1 59 -#define CLK_MIPI_DSI0 60 -#define CLK_MIPI_DSI1 61 -#define CLK_HDMI 62 -#define CLK_HDMI_SLOW 63 -#define CLK_MIPI_CSI 64 -#define CLK_CSI_ISP 65 -#define CLK_CSI_MISC 66 -#define CLK_CSI0_MCLK 67 -#define CLK_CSI1_MCLK 68 -#define CLK_FD 69 -#define CLK_VE 70 -#define CLK_AVS 71 -#define CLK_GPU_CORE 72 -#define CLK_GPU_MEMORY 73 -#define CLK_GPU_AXI 74 -#define CLK_SATA 75 -#define CLK_AC97 76 -#define CLK_MIPI_HSI 77 -#define CLK_GPADC 78 -#define CLK_CIR_TX 79 - -#define CLK_BUS_FD 80 -#define CLK_BUS_VE 81 -#define CLK_BUS_GPU_CTRL 82 -#define CLK_BUS_SS 83 -#define CLK_BUS_MMC 84 -#define CLK_BUS_NAND0 85 -#define CLK_BUS_NAND1 86 -#define CLK_BUS_SDRAM 87 -#define CLK_BUS_MIPI_HSI 88 -#define CLK_BUS_SATA 89 -#define CLK_BUS_TS 90 -#define CLK_BUS_SPI0 91 -#define CLK_BUS_SPI1 92 -#define CLK_BUS_SPI2 93 -#define CLK_BUS_SPI3 94 - -#define CLK_BUS_OTG 95 -#define CLK_BUS_USB 96 -#define CLK_BUS_GMAC 97 -#define CLK_BUS_MSGBOX 98 -#define CLK_BUS_SPINLOCK 99 -#define CLK_BUS_HSTIMER 100 -#define CLK_BUS_DMA 101 - -#define CLK_BUS_LCD0 102 -#define CLK_BUS_LCD1 103 -#define CLK_BUS_EDP 104 -#define CLK_BUS_CSI 105 -#define CLK_BUS_HDMI 106 -#define CLK_BUS_DE 107 -#define CLK_BUS_MP 108 -#define CLK_BUS_MIPI_DSI 109 - -#define CLK_BUS_SPDIF 110 -#define CLK_BUS_PIO 111 -#define CLK_BUS_AC97 112 -#define CLK_BUS_I2S0 113 -#define CLK_BUS_I2S1 114 -#define CLK_BUS_LRADC 115 -#define CLK_BUS_GPADC 116 -#define CLK_BUS_TWD 117 -#define CLK_BUS_CIR_TX 118 - -#define CLK_BUS_I2C0 119 -#define CLK_BUS_I2C1 120 -#define CLK_BUS_I2C2 121 -#define CLK_BUS_I2C3 122 -#define CLK_BUS_I2C4 123 -#define CLK_BUS_UART0 124 -#define CLK_BUS_UART1 125 -#define CLK_BUS_UART2 126 -#define CLK_BUS_UART3 127 -#define CLK_BUS_UART4 128 -#define CLK_BUS_UART5 129 - -#endif /* _DT_BINDINGS_CLOCK_SUN9I_A80_CCU_H_ */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/sun9i-a80-de.h b/sys/gnu/dts/include/dt-bindings/clock/sun9i-a80-de.h deleted file mode 100644 index 3dad6c3cd13..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/sun9i-a80-de.h +++ /dev/null @@ -1,80 +0,0 @@ -/* - * Copyright (C) 2016 Chen-Yu Tsai - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_CLOCK_SUN9I_A80_DE_H_ -#define _DT_BINDINGS_CLOCK_SUN9I_A80_DE_H_ - -#define CLK_FE0 0 -#define CLK_FE1 1 -#define CLK_FE2 2 -#define CLK_IEP_DEU0 3 -#define CLK_IEP_DEU1 4 -#define CLK_BE0 5 -#define CLK_BE1 6 -#define CLK_BE2 7 -#define CLK_IEP_DRC0 8 -#define CLK_IEP_DRC1 9 -#define CLK_MERGE 10 - -#define CLK_DRAM_FE0 11 -#define CLK_DRAM_FE1 12 -#define CLK_DRAM_FE2 13 -#define CLK_DRAM_DEU0 14 -#define CLK_DRAM_DEU1 15 -#define CLK_DRAM_BE0 16 -#define CLK_DRAM_BE1 17 -#define CLK_DRAM_BE2 18 -#define CLK_DRAM_DRC0 19 -#define CLK_DRAM_DRC1 20 - -#define CLK_BUS_FE0 21 -#define CLK_BUS_FE1 22 -#define CLK_BUS_FE2 23 -#define CLK_BUS_DEU0 24 -#define CLK_BUS_DEU1 25 -#define CLK_BUS_BE0 26 -#define CLK_BUS_BE1 27 -#define CLK_BUS_BE2 28 -#define CLK_BUS_DRC0 29 -#define CLK_BUS_DRC1 30 - -#endif /* _DT_BINDINGS_CLOCK_SUN9I_A80_DE_H_ */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/sun9i-a80-usb.h b/sys/gnu/dts/include/dt-bindings/clock/sun9i-a80-usb.h deleted file mode 100644 index 783a60d2cce..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/sun9i-a80-usb.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Copyright (C) 2016 Chen-Yu Tsai - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_CLOCK_SUN9I_A80_USB_H_ -#define _DT_BINDINGS_CLOCK_SUN9I_A80_USB_H_ - -#define CLK_BUS_HCI0 0 -#define CLK_USB_OHCI0 1 -#define CLK_BUS_HCI1 2 -#define CLK_BUS_HCI2 3 -#define CLK_USB_OHCI2 4 - -#define CLK_USB0_PHY 5 -#define CLK_USB1_HSIC 6 -#define CLK_USB1_PHY 7 -#define CLK_USB2_HSIC 8 -#define CLK_USB2_PHY 9 -#define CLK_USB_HSIC 10 - -#endif /* _DT_BINDINGS_CLOCK_SUN9I_A80_USB_H_ */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/suniv-ccu-f1c100s.h b/sys/gnu/dts/include/dt-bindings/clock/suniv-ccu-f1c100s.h deleted file mode 100644 index f5ac155c9c7..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/suniv-ccu-f1c100s.h +++ /dev/null @@ -1,70 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) - * - * Copyright (c) 2018 Icenowy Zheng - * - */ - -#ifndef _DT_BINDINGS_CLK_SUNIV_F1C100S_H_ -#define _DT_BINDINGS_CLK_SUNIV_F1C100S_H_ - -#define CLK_CPU 11 - -#define CLK_BUS_DMA 14 -#define CLK_BUS_MMC0 15 -#define CLK_BUS_MMC1 16 -#define CLK_BUS_DRAM 17 -#define CLK_BUS_SPI0 18 -#define CLK_BUS_SPI1 19 -#define CLK_BUS_OTG 20 -#define CLK_BUS_VE 21 -#define CLK_BUS_LCD 22 -#define CLK_BUS_DEINTERLACE 23 -#define CLK_BUS_CSI 24 -#define CLK_BUS_TVD 25 -#define CLK_BUS_TVE 26 -#define CLK_BUS_DE_BE 27 -#define CLK_BUS_DE_FE 28 -#define CLK_BUS_CODEC 29 -#define CLK_BUS_SPDIF 30 -#define CLK_BUS_IR 31 -#define CLK_BUS_RSB 32 -#define CLK_BUS_I2S0 33 -#define CLK_BUS_I2C0 34 -#define CLK_BUS_I2C1 35 -#define CLK_BUS_I2C2 36 -#define CLK_BUS_PIO 37 -#define CLK_BUS_UART0 38 -#define CLK_BUS_UART1 39 -#define CLK_BUS_UART2 40 - -#define CLK_MMC0 41 -#define CLK_MMC0_SAMPLE 42 -#define CLK_MMC0_OUTPUT 43 -#define CLK_MMC1 44 -#define CLK_MMC1_SAMPLE 45 -#define CLK_MMC1_OUTPUT 46 -#define CLK_I2S 47 -#define CLK_SPDIF 48 - -#define CLK_USB_PHY0 49 - -#define CLK_DRAM_VE 50 -#define CLK_DRAM_CSI 51 -#define CLK_DRAM_DEINTERLACE 52 -#define CLK_DRAM_TVD 53 -#define CLK_DRAM_DE_FE 54 -#define CLK_DRAM_DE_BE 55 - -#define CLK_DE_BE 56 -#define CLK_DE_FE 57 -#define CLK_TCON 58 -#define CLK_DEINTERLACE 59 -#define CLK_TVE2_CLK 60 -#define CLK_TVE1_CLK 61 -#define CLK_TVD 62 -#define CLK_CSI 63 -#define CLK_VE 64 -#define CLK_CODEC 65 -#define CLK_AVS 66 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/tegra114-car.h b/sys/gnu/dts/include/dt-bindings/clock/tegra114-car.h deleted file mode 100644 index bb5c2c999c0..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/tegra114-car.h +++ /dev/null @@ -1,344 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides constants for binding nvidia,tegra114-car. - * - * The first 160 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB - * registers. These IDs often match those in the CAR's RST_DEVICES registers, - * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In - * this case, those clocks are assigned IDs above 160 in order to highlight - * this issue. Implementations that interpret these clock IDs as bit values - * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to - * explicitly handle these special cases. - * - * The balance of the clocks controlled by the CAR are assigned IDs of 160 and - * above. - */ - -#ifndef _DT_BINDINGS_CLOCK_TEGRA114_CAR_H -#define _DT_BINDINGS_CLOCK_TEGRA114_CAR_H - -/* 0 */ -/* 1 */ -/* 2 */ -/* 3 */ -#define TEGRA114_CLK_RTC 4 -#define TEGRA114_CLK_TIMER 5 -#define TEGRA114_CLK_UARTA 6 -/* 7 (register bit affects uartb and vfir) */ -/* 8 */ -#define TEGRA114_CLK_SDMMC2 9 -/* 10 (register bit affects spdif_in and spdif_out) */ -#define TEGRA114_CLK_I2S1 11 -#define TEGRA114_CLK_I2C1 12 -#define TEGRA114_CLK_NDFLASH 13 -#define TEGRA114_CLK_SDMMC1 14 -#define TEGRA114_CLK_SDMMC4 15 -/* 16 */ -#define TEGRA114_CLK_PWM 17 -#define TEGRA114_CLK_I2S2 18 -#define TEGRA114_CLK_EPP 19 -/* 20 (register bit affects vi and vi_sensor) */ -#define TEGRA114_CLK_GR2D 21 -#define TEGRA114_CLK_USBD 22 -#define TEGRA114_CLK_ISP 23 -#define TEGRA114_CLK_GR3D 24 -/* 25 */ -#define TEGRA114_CLK_DISP2 26 -#define TEGRA114_CLK_DISP1 27 -#define TEGRA114_CLK_HOST1X 28 -#define TEGRA114_CLK_VCP 29 -#define TEGRA114_CLK_I2S0 30 -/* 31 */ - -#define TEGRA114_CLK_MC 32 -/* 33 */ -#define TEGRA114_CLK_APBDMA 34 -/* 35 */ -#define TEGRA114_CLK_KBC 36 -/* 37 */ -/* 38 */ -/* 39 (register bit affects fuse and fuse_burn) */ -#define TEGRA114_CLK_KFUSE 40 -#define TEGRA114_CLK_SBC1 41 -#define TEGRA114_CLK_NOR 42 -/* 43 */ -#define TEGRA114_CLK_SBC2 44 -/* 45 */ -#define TEGRA114_CLK_SBC3 46 -#define TEGRA114_CLK_I2C5 47 -#define TEGRA114_CLK_DSIA 48 -/* 49 */ -#define TEGRA114_CLK_MIPI 50 -#define TEGRA114_CLK_HDMI 51 -#define TEGRA114_CLK_CSI 52 -/* 53 */ -#define TEGRA114_CLK_I2C2 54 -#define TEGRA114_CLK_UARTC 55 -#define TEGRA114_CLK_MIPI_CAL 56 -#define TEGRA114_CLK_EMC 57 -#define TEGRA114_CLK_USB2 58 -#define TEGRA114_CLK_USB3 59 -/* 60 */ -#define TEGRA114_CLK_VDE 61 -#define TEGRA114_CLK_BSEA 62 -#define TEGRA114_CLK_BSEV 63 - -/* 64 */ -#define TEGRA114_CLK_UARTD 65 -/* 66 */ -#define TEGRA114_CLK_I2C3 67 -#define TEGRA114_CLK_SBC4 68 -#define TEGRA114_CLK_SDMMC3 69 -/* 70 */ -#define TEGRA114_CLK_OWR 71 -/* 72 */ -#define TEGRA114_CLK_CSITE 73 -/* 74 */ -/* 75 */ -#define TEGRA114_CLK_LA 76 -#define TEGRA114_CLK_TRACE 77 -#define TEGRA114_CLK_SOC_THERM 78 -#define TEGRA114_CLK_DTV 79 -#define TEGRA114_CLK_NDSPEED 80 -#define TEGRA114_CLK_I2CSLOW 81 -#define TEGRA114_CLK_DSIB 82 -#define TEGRA114_CLK_TSEC 83 -/* 84 */ -/* 85 */ -/* 86 */ -/* 87 */ -/* 88 */ -#define TEGRA114_CLK_XUSB_HOST 89 -/* 90 */ -#define TEGRA114_CLK_MSENC 91 -#define TEGRA114_CLK_CSUS 92 -/* 93 */ -/* 94 */ -/* 95 (bit affects xusb_dev and xusb_dev_src) */ - -/* 96 */ -/* 97 */ -/* 98 */ -#define TEGRA114_CLK_MSELECT 99 -#define TEGRA114_CLK_TSENSOR 100 -#define TEGRA114_CLK_I2S3 101 -#define TEGRA114_CLK_I2S4 102 -#define TEGRA114_CLK_I2C4 103 -#define TEGRA114_CLK_SBC5 104 -#define TEGRA114_CLK_SBC6 105 -#define TEGRA114_CLK_D_AUDIO 106 -#define TEGRA114_CLK_APBIF 107 -#define TEGRA114_CLK_DAM0 108 -#define TEGRA114_CLK_DAM1 109 -#define TEGRA114_CLK_DAM2 110 -#define TEGRA114_CLK_HDA2CODEC_2X 111 -/* 112 */ -#define TEGRA114_CLK_AUDIO0_2X 113 -#define TEGRA114_CLK_AUDIO1_2X 114 -#define TEGRA114_CLK_AUDIO2_2X 115 -#define TEGRA114_CLK_AUDIO3_2X 116 -#define TEGRA114_CLK_AUDIO4_2X 117 -#define TEGRA114_CLK_SPDIF_2X 118 -#define TEGRA114_CLK_ACTMON 119 -#define TEGRA114_CLK_EXTERN1 120 -#define TEGRA114_CLK_EXTERN2 121 -#define TEGRA114_CLK_EXTERN3 122 -/* 123 */ -/* 124 */ -#define TEGRA114_CLK_HDA 125 -/* 126 */ -#define TEGRA114_CLK_SE 127 - -#define TEGRA114_CLK_HDA2HDMI 128 -/* 129 */ -/* 130 */ -/* 131 */ -/* 132 */ -/* 133 */ -/* 134 */ -/* 135 */ -#define TEGRA114_CLK_CEC 136 -/* 137 */ -/* 138 */ -/* 139 */ -/* 140 */ -/* 141 */ -/* 142 */ -/* 143 (bit affects xusb_falcon_src, xusb_fs_src, */ -/* xusb_host_src and xusb_ss_src) */ -#define TEGRA114_CLK_CILAB 144 -#define TEGRA114_CLK_CILCD 145 -#define TEGRA114_CLK_CILE 146 -#define TEGRA114_CLK_DSIALP 147 -#define TEGRA114_CLK_DSIBLP 148 -/* 149 */ -#define TEGRA114_CLK_DDS 150 -/* 151 */ -#define TEGRA114_CLK_DP2 152 -#define TEGRA114_CLK_AMX 153 -#define TEGRA114_CLK_ADX 154 -/* 155 (bit affects dfll_ref and dfll_soc) */ -#define TEGRA114_CLK_XUSB_SS 156 -/* 157 */ -/* 158 */ -/* 159 */ - -/* 160 */ -/* 161 */ -/* 162 */ -/* 163 */ -/* 164 */ -/* 165 */ -/* 166 */ -/* 167 */ -/* 168 */ -/* 169 */ -/* 170 */ -/* 171 */ -/* 172 */ -/* 173 */ -/* 174 */ -/* 175 */ -/* 176 */ -/* 177 */ -/* 178 */ -/* 179 */ -/* 180 */ -/* 181 */ -/* 182 */ -/* 183 */ -/* 184 */ -/* 185 */ -/* 186 */ -/* 187 */ -/* 188 */ -/* 189 */ -/* 190 */ -/* 191 */ - -#define TEGRA114_CLK_UARTB 192 -#define TEGRA114_CLK_VFIR 193 -#define TEGRA114_CLK_SPDIF_IN 194 -#define TEGRA114_CLK_SPDIF_OUT 195 -#define TEGRA114_CLK_VI 196 -#define TEGRA114_CLK_VI_SENSOR 197 -#define TEGRA114_CLK_FUSE 198 -#define TEGRA114_CLK_FUSE_BURN 199 -#define TEGRA114_CLK_CLK_32K 200 -#define TEGRA114_CLK_CLK_M 201 -#define TEGRA114_CLK_CLK_M_DIV2 202 -#define TEGRA114_CLK_CLK_M_DIV4 203 -#define TEGRA114_CLK_PLL_REF 204 -#define TEGRA114_CLK_PLL_C 205 -#define TEGRA114_CLK_PLL_C_OUT1 206 -#define TEGRA114_CLK_PLL_C2 207 -#define TEGRA114_CLK_PLL_C3 208 -#define TEGRA114_CLK_PLL_M 209 -#define TEGRA114_CLK_PLL_M_OUT1 210 -#define TEGRA114_CLK_PLL_P 211 -#define TEGRA114_CLK_PLL_P_OUT1 212 -#define TEGRA114_CLK_PLL_P_OUT2 213 -#define TEGRA114_CLK_PLL_P_OUT3 214 -#define TEGRA114_CLK_PLL_P_OUT4 215 -#define TEGRA114_CLK_PLL_A 216 -#define TEGRA114_CLK_PLL_A_OUT0 217 -#define TEGRA114_CLK_PLL_D 218 -#define TEGRA114_CLK_PLL_D_OUT0 219 -#define TEGRA114_CLK_PLL_D2 220 -#define TEGRA114_CLK_PLL_D2_OUT0 221 -#define TEGRA114_CLK_PLL_U 222 -#define TEGRA114_CLK_PLL_U_480M 223 - -#define TEGRA114_CLK_PLL_U_60M 224 -#define TEGRA114_CLK_PLL_U_48M 225 -#define TEGRA114_CLK_PLL_U_12M 226 -#define TEGRA114_CLK_PLL_X 227 -#define TEGRA114_CLK_PLL_X_OUT0 228 -#define TEGRA114_CLK_PLL_RE_VCO 229 -#define TEGRA114_CLK_PLL_RE_OUT 230 -#define TEGRA114_CLK_PLL_E_OUT0 231 -#define TEGRA114_CLK_SPDIF_IN_SYNC 232 -#define TEGRA114_CLK_I2S0_SYNC 233 -#define TEGRA114_CLK_I2S1_SYNC 234 -#define TEGRA114_CLK_I2S2_SYNC 235 -#define TEGRA114_CLK_I2S3_SYNC 236 -#define TEGRA114_CLK_I2S4_SYNC 237 -#define TEGRA114_CLK_VIMCLK_SYNC 238 -#define TEGRA114_CLK_AUDIO0 239 -#define TEGRA114_CLK_AUDIO1 240 -#define TEGRA114_CLK_AUDIO2 241 -#define TEGRA114_CLK_AUDIO3 242 -#define TEGRA114_CLK_AUDIO4 243 -#define TEGRA114_CLK_SPDIF 244 -#define TEGRA114_CLK_CLK_OUT_1 245 -#define TEGRA114_CLK_CLK_OUT_2 246 -#define TEGRA114_CLK_CLK_OUT_3 247 -#define TEGRA114_CLK_BLINK 248 -/* 249 */ -/* 250 */ -/* 251 */ -#define TEGRA114_CLK_XUSB_HOST_SRC 252 -#define TEGRA114_CLK_XUSB_FALCON_SRC 253 -#define TEGRA114_CLK_XUSB_FS_SRC 254 -#define TEGRA114_CLK_XUSB_SS_SRC 255 - -#define TEGRA114_CLK_XUSB_DEV_SRC 256 -#define TEGRA114_CLK_XUSB_DEV 257 -#define TEGRA114_CLK_XUSB_HS_SRC 258 -#define TEGRA114_CLK_SCLK 259 -#define TEGRA114_CLK_HCLK 260 -#define TEGRA114_CLK_PCLK 261 -#define TEGRA114_CLK_CCLK_G 262 -#define TEGRA114_CLK_CCLK_LP 263 -#define TEGRA114_CLK_DFLL_REF 264 -#define TEGRA114_CLK_DFLL_SOC 265 -/* 266 */ -/* 267 */ -/* 268 */ -/* 269 */ -/* 270 */ -/* 271 */ -/* 272 */ -/* 273 */ -/* 274 */ -/* 275 */ -/* 276 */ -/* 277 */ -/* 278 */ -/* 279 */ -/* 280 */ -/* 281 */ -/* 282 */ -/* 283 */ -/* 284 */ -/* 285 */ -/* 286 */ -/* 287 */ - -/* 288 */ -/* 289 */ -/* 290 */ -/* 291 */ -/* 292 */ -/* 293 */ -/* 294 */ -/* 295 */ -/* 296 */ -/* 297 */ -/* 298 */ -/* 299 */ -#define TEGRA114_CLK_AUDIO0_MUX 300 -#define TEGRA114_CLK_AUDIO1_MUX 301 -#define TEGRA114_CLK_AUDIO2_MUX 302 -#define TEGRA114_CLK_AUDIO3_MUX 303 -#define TEGRA114_CLK_AUDIO4_MUX 304 -#define TEGRA114_CLK_SPDIF_MUX 305 -#define TEGRA114_CLK_CLK_OUT_1_MUX 306 -#define TEGRA114_CLK_CLK_OUT_2_MUX 307 -#define TEGRA114_CLK_CLK_OUT_3_MUX 308 -#define TEGRA114_CLK_DSIA_MUX 309 -#define TEGRA114_CLK_DSIB_MUX 310 -#define TEGRA114_CLK_XUSB_SS_DIV2 311 -#define TEGRA114_CLK_CLK_MAX 312 - -#endif /* _DT_BINDINGS_CLOCK_TEGRA114_CAR_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/tegra124-car-common.h b/sys/gnu/dts/include/dt-bindings/clock/tegra124-car-common.h deleted file mode 100644 index 0c4f5be0a74..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/tegra124-car-common.h +++ /dev/null @@ -1,347 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides constants for binding nvidia,tegra124-car or - * nvidia,tegra132-car. - * - * The first 192 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB - * registers. These IDs often match those in the CAR's RST_DEVICES registers, - * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In - * this case, those clocks are assigned IDs above 185 in order to highlight - * this issue. Implementations that interpret these clock IDs as bit values - * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to - * explicitly handle these special cases. - * - * The balance of the clocks controlled by the CAR are assigned IDs of 185 and - * above. - */ - -#ifndef _DT_BINDINGS_CLOCK_TEGRA124_CAR_COMMON_H -#define _DT_BINDINGS_CLOCK_TEGRA124_CAR_COMMON_H - -/* 0 */ -/* 1 */ -/* 2 */ -#define TEGRA124_CLK_ISPB 3 -#define TEGRA124_CLK_RTC 4 -#define TEGRA124_CLK_TIMER 5 -#define TEGRA124_CLK_UARTA 6 -/* 7 (register bit affects uartb and vfir) */ -/* 8 */ -#define TEGRA124_CLK_SDMMC2 9 -/* 10 (register bit affects spdif_in and spdif_out) */ -#define TEGRA124_CLK_I2S1 11 -#define TEGRA124_CLK_I2C1 12 -/* 13 */ -#define TEGRA124_CLK_SDMMC1 14 -#define TEGRA124_CLK_SDMMC4 15 -/* 16 */ -#define TEGRA124_CLK_PWM 17 -#define TEGRA124_CLK_I2S2 18 -/* 20 (register bit affects vi and vi_sensor) */ -/* 21 */ -#define TEGRA124_CLK_USBD 22 -#define TEGRA124_CLK_ISP 23 -/* 26 */ -/* 25 */ -#define TEGRA124_CLK_DISP2 26 -#define TEGRA124_CLK_DISP1 27 -#define TEGRA124_CLK_HOST1X 28 -#define TEGRA124_CLK_VCP 29 -#define TEGRA124_CLK_I2S0 30 -/* 31 */ - -#define TEGRA124_CLK_MC 32 -/* 33 */ -#define TEGRA124_CLK_APBDMA 34 -/* 35 */ -#define TEGRA124_CLK_KBC 36 -/* 37 */ -/* 38 */ -/* 39 (register bit affects fuse and fuse_burn) */ -#define TEGRA124_CLK_KFUSE 40 -#define TEGRA124_CLK_SBC1 41 -#define TEGRA124_CLK_NOR 42 -/* 43 */ -#define TEGRA124_CLK_SBC2 44 -/* 45 */ -#define TEGRA124_CLK_SBC3 46 -#define TEGRA124_CLK_I2C5 47 -#define TEGRA124_CLK_DSIA 48 -/* 49 */ -#define TEGRA124_CLK_MIPI 50 -#define TEGRA124_CLK_HDMI 51 -#define TEGRA124_CLK_CSI 52 -/* 53 */ -#define TEGRA124_CLK_I2C2 54 -#define TEGRA124_CLK_UARTC 55 -#define TEGRA124_CLK_MIPI_CAL 56 -#define TEGRA124_CLK_EMC 57 -#define TEGRA124_CLK_USB2 58 -#define TEGRA124_CLK_USB3 59 -/* 60 */ -#define TEGRA124_CLK_VDE 61 -#define TEGRA124_CLK_BSEA 62 -#define TEGRA124_CLK_BSEV 63 - -/* 64 */ -#define TEGRA124_CLK_UARTD 65 -/* 66 */ -#define TEGRA124_CLK_I2C3 67 -#define TEGRA124_CLK_SBC4 68 -#define TEGRA124_CLK_SDMMC3 69 -#define TEGRA124_CLK_PCIE 70 -#define TEGRA124_CLK_OWR 71 -#define TEGRA124_CLK_AFI 72 -#define TEGRA124_CLK_CSITE 73 -/* 74 */ -/* 75 */ -#define TEGRA124_CLK_LA 76 -#define TEGRA124_CLK_TRACE 77 -#define TEGRA124_CLK_SOC_THERM 78 -#define TEGRA124_CLK_DTV 79 -/* 80 */ -#define TEGRA124_CLK_I2CSLOW 81 -#define TEGRA124_CLK_DSIB 82 -#define TEGRA124_CLK_TSEC 83 -/* 84 */ -/* 85 */ -/* 86 */ -/* 87 */ -/* 88 */ -#define TEGRA124_CLK_XUSB_HOST 89 -/* 90 */ -#define TEGRA124_CLK_MSENC 91 -#define TEGRA124_CLK_CSUS 92 -/* 93 */ -/* 94 */ -/* 95 (bit affects xusb_dev and xusb_dev_src) */ - -/* 96 */ -/* 97 */ -/* 98 */ -#define TEGRA124_CLK_MSELECT 99 -#define TEGRA124_CLK_TSENSOR 100 -#define TEGRA124_CLK_I2S3 101 -#define TEGRA124_CLK_I2S4 102 -#define TEGRA124_CLK_I2C4 103 -#define TEGRA124_CLK_SBC5 104 -#define TEGRA124_CLK_SBC6 105 -#define TEGRA124_CLK_D_AUDIO 106 -#define TEGRA124_CLK_APBIF 107 -#define TEGRA124_CLK_DAM0 108 -#define TEGRA124_CLK_DAM1 109 -#define TEGRA124_CLK_DAM2 110 -#define TEGRA124_CLK_HDA2CODEC_2X 111 -/* 112 */ -#define TEGRA124_CLK_AUDIO0_2X 113 -#define TEGRA124_CLK_AUDIO1_2X 114 -#define TEGRA124_CLK_AUDIO2_2X 115 -#define TEGRA124_CLK_AUDIO3_2X 116 -#define TEGRA124_CLK_AUDIO4_2X 117 -#define TEGRA124_CLK_SPDIF_2X 118 -#define TEGRA124_CLK_ACTMON 119 -#define TEGRA124_CLK_EXTERN1 120 -#define TEGRA124_CLK_EXTERN2 121 -#define TEGRA124_CLK_EXTERN3 122 -#define TEGRA124_CLK_SATA_OOB 123 -#define TEGRA124_CLK_SATA 124 -#define TEGRA124_CLK_HDA 125 -/* 126 */ -#define TEGRA124_CLK_SE 127 - -#define TEGRA124_CLK_HDA2HDMI 128 -#define TEGRA124_CLK_SATA_COLD 129 -/* 130 */ -/* 131 */ -/* 132 */ -/* 133 */ -/* 134 */ -/* 135 */ -#define TEGRA124_CLK_CEC 136 -/* 137 */ -/* 138 */ -/* 139 */ -/* 140 */ -/* 141 */ -/* 142 */ -/* 143 (bit affects xusb_falcon_src, xusb_fs_src, */ -/* xusb_host_src and xusb_ss_src) */ -#define TEGRA124_CLK_CILAB 144 -#define TEGRA124_CLK_CILCD 145 -#define TEGRA124_CLK_CILE 146 -#define TEGRA124_CLK_DSIALP 147 -#define TEGRA124_CLK_DSIBLP 148 -#define TEGRA124_CLK_ENTROPY 149 -#define TEGRA124_CLK_DDS 150 -/* 151 */ -#define TEGRA124_CLK_DP2 152 -#define TEGRA124_CLK_AMX 153 -#define TEGRA124_CLK_ADX 154 -/* 155 (bit affects dfll_ref and dfll_soc) */ -#define TEGRA124_CLK_XUSB_SS 156 -/* 157 */ -/* 158 */ -/* 159 */ - -/* 160 */ -/* 161 */ -/* 162 */ -/* 163 */ -/* 164 */ -/* 165 */ -#define TEGRA124_CLK_I2C6 166 -/* 167 */ -/* 168 */ -/* 169 */ -/* 170 */ -#define TEGRA124_CLK_VIM2_CLK 171 -/* 172 */ -/* 173 */ -/* 174 */ -/* 175 */ -#define TEGRA124_CLK_HDMI_AUDIO 176 -#define TEGRA124_CLK_CLK72MHZ 177 -#define TEGRA124_CLK_VIC03 178 -/* 179 */ -#define TEGRA124_CLK_ADX1 180 -#define TEGRA124_CLK_DPAUX 181 -#define TEGRA124_CLK_SOR0 182 -/* 183 */ -#define TEGRA124_CLK_GPU 184 -#define TEGRA124_CLK_AMX1 185 -/* 186 */ -/* 187 */ -/* 188 */ -/* 189 */ -/* 190 */ -/* 191 */ -#define TEGRA124_CLK_UARTB 192 -#define TEGRA124_CLK_VFIR 193 -#define TEGRA124_CLK_SPDIF_IN 194 -#define TEGRA124_CLK_SPDIF_OUT 195 -#define TEGRA124_CLK_VI 196 -#define TEGRA124_CLK_VI_SENSOR 197 -#define TEGRA124_CLK_FUSE 198 -#define TEGRA124_CLK_FUSE_BURN 199 -#define TEGRA124_CLK_CLK_32K 200 -#define TEGRA124_CLK_CLK_M 201 -#define TEGRA124_CLK_CLK_M_DIV2 202 -#define TEGRA124_CLK_CLK_M_DIV4 203 -#define TEGRA124_CLK_PLL_REF 204 -#define TEGRA124_CLK_PLL_C 205 -#define TEGRA124_CLK_PLL_C_OUT1 206 -#define TEGRA124_CLK_PLL_C2 207 -#define TEGRA124_CLK_PLL_C3 208 -#define TEGRA124_CLK_PLL_M 209 -#define TEGRA124_CLK_PLL_M_OUT1 210 -#define TEGRA124_CLK_PLL_P 211 -#define TEGRA124_CLK_PLL_P_OUT1 212 -#define TEGRA124_CLK_PLL_P_OUT2 213 -#define TEGRA124_CLK_PLL_P_OUT3 214 -#define TEGRA124_CLK_PLL_P_OUT4 215 -#define TEGRA124_CLK_PLL_A 216 -#define TEGRA124_CLK_PLL_A_OUT0 217 -#define TEGRA124_CLK_PLL_D 218 -#define TEGRA124_CLK_PLL_D_OUT0 219 -#define TEGRA124_CLK_PLL_D2 220 -#define TEGRA124_CLK_PLL_D2_OUT0 221 -#define TEGRA124_CLK_PLL_U 222 -#define TEGRA124_CLK_PLL_U_480M 223 - -#define TEGRA124_CLK_PLL_U_60M 224 -#define TEGRA124_CLK_PLL_U_48M 225 -#define TEGRA124_CLK_PLL_U_12M 226 -/* 227 */ -/* 228 */ -#define TEGRA124_CLK_PLL_RE_VCO 229 -#define TEGRA124_CLK_PLL_RE_OUT 230 -#define TEGRA124_CLK_PLL_E 231 -#define TEGRA124_CLK_SPDIF_IN_SYNC 232 -#define TEGRA124_CLK_I2S0_SYNC 233 -#define TEGRA124_CLK_I2S1_SYNC 234 -#define TEGRA124_CLK_I2S2_SYNC 235 -#define TEGRA124_CLK_I2S3_SYNC 236 -#define TEGRA124_CLK_I2S4_SYNC 237 -#define TEGRA124_CLK_VIMCLK_SYNC 238 -#define TEGRA124_CLK_AUDIO0 239 -#define TEGRA124_CLK_AUDIO1 240 -#define TEGRA124_CLK_AUDIO2 241 -#define TEGRA124_CLK_AUDIO3 242 -#define TEGRA124_CLK_AUDIO4 243 -#define TEGRA124_CLK_SPDIF 244 -#define TEGRA124_CLK_CLK_OUT_1 245 -#define TEGRA124_CLK_CLK_OUT_2 246 -#define TEGRA124_CLK_CLK_OUT_3 247 -#define TEGRA124_CLK_BLINK 248 -/* 249 */ -/* 250 */ -/* 251 */ -#define TEGRA124_CLK_XUSB_HOST_SRC 252 -#define TEGRA124_CLK_XUSB_FALCON_SRC 253 -#define TEGRA124_CLK_XUSB_FS_SRC 254 -#define TEGRA124_CLK_XUSB_SS_SRC 255 - -#define TEGRA124_CLK_XUSB_DEV_SRC 256 -#define TEGRA124_CLK_XUSB_DEV 257 -#define TEGRA124_CLK_XUSB_HS_SRC 258 -#define TEGRA124_CLK_SCLK 259 -#define TEGRA124_CLK_HCLK 260 -#define TEGRA124_CLK_PCLK 261 -/* 262 */ -/* 263 */ -#define TEGRA124_CLK_DFLL_REF 264 -#define TEGRA124_CLK_DFLL_SOC 265 -#define TEGRA124_CLK_VI_SENSOR2 266 -#define TEGRA124_CLK_PLL_P_OUT5 267 -#define TEGRA124_CLK_CML0 268 -#define TEGRA124_CLK_CML1 269 -#define TEGRA124_CLK_PLL_C4 270 -#define TEGRA124_CLK_PLL_DP 271 -#define TEGRA124_CLK_PLL_E_MUX 272 -#define TEGRA124_CLK_PLL_D_DSI_OUT 273 -/* 274 */ -/* 275 */ -/* 276 */ -/* 277 */ -/* 278 */ -/* 279 */ -/* 280 */ -/* 281 */ -/* 282 */ -/* 283 */ -/* 284 */ -/* 285 */ -/* 286 */ -/* 287 */ - -/* 288 */ -/* 289 */ -/* 290 */ -/* 291 */ -/* 292 */ -/* 293 */ -/* 294 */ -/* 295 */ -/* 296 */ -/* 297 */ -/* 298 */ -/* 299 */ -#define TEGRA124_CLK_AUDIO0_MUX 300 -#define TEGRA124_CLK_AUDIO1_MUX 301 -#define TEGRA124_CLK_AUDIO2_MUX 302 -#define TEGRA124_CLK_AUDIO3_MUX 303 -#define TEGRA124_CLK_AUDIO4_MUX 304 -#define TEGRA124_CLK_SPDIF_MUX 305 -#define TEGRA124_CLK_CLK_OUT_1_MUX 306 -#define TEGRA124_CLK_CLK_OUT_2_MUX 307 -#define TEGRA124_CLK_CLK_OUT_3_MUX 308 -/* 309 */ -/* 310 */ -#define TEGRA124_CLK_SOR0_LVDS 311 /* deprecated */ -#define TEGRA124_CLK_SOR0_OUT 311 -#define TEGRA124_CLK_XUSB_SS_DIV2 312 - -#define TEGRA124_CLK_PLL_M_UD 313 -#define TEGRA124_CLK_PLL_C_UD 314 - -#endif /* _DT_BINDINGS_CLOCK_TEGRA124_CAR_COMMON_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/tegra124-car.h b/sys/gnu/dts/include/dt-bindings/clock/tegra124-car.h deleted file mode 100644 index c520ee23195..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/tegra124-car.h +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides Tegra124-specific constants for binding - * nvidia,tegra124-car. - */ - -#include - -#ifndef _DT_BINDINGS_CLOCK_TEGRA124_CAR_H -#define _DT_BINDINGS_CLOCK_TEGRA124_CAR_H - -#define TEGRA124_CLK_PLL_X 227 -#define TEGRA124_CLK_PLL_X_OUT0 228 - -#define TEGRA124_CLK_CCLK_G 262 -#define TEGRA124_CLK_CCLK_LP 263 - -#define TEGRA124_CLK_CLK_MAX 315 - -#endif /* _DT_BINDINGS_CLOCK_TEGRA124_CAR_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/tegra186-clock.h b/sys/gnu/dts/include/dt-bindings/clock/tegra186-clock.h deleted file mode 100644 index d6b525f4566..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/tegra186-clock.h +++ /dev/null @@ -1,941 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/** @file */ - -#ifndef _MACH_T186_CLK_T186_H -#define _MACH_T186_CLK_T186_H - -/** - * @defgroup clock_ids Clock Identifiers - * @{ - * @defgroup extern_input external input clocks - * @{ - * @def TEGRA186_CLK_OSC - * @def TEGRA186_CLK_CLK_32K - * @def TEGRA186_CLK_DTV_INPUT - * @def TEGRA186_CLK_SOR0_PAD_CLKOUT - * @def TEGRA186_CLK_SOR1_PAD_CLKOUT - * @def TEGRA186_CLK_I2S1_SYNC_INPUT - * @def TEGRA186_CLK_I2S2_SYNC_INPUT - * @def TEGRA186_CLK_I2S3_SYNC_INPUT - * @def TEGRA186_CLK_I2S4_SYNC_INPUT - * @def TEGRA186_CLK_I2S5_SYNC_INPUT - * @def TEGRA186_CLK_I2S6_SYNC_INPUT - * @def TEGRA186_CLK_SPDIFIN_SYNC_INPUT - * @} - * - * @defgroup extern_output external output clocks - * @{ - * @def TEGRA186_CLK_EXTPERIPH1 - * @def TEGRA186_CLK_EXTPERIPH2 - * @def TEGRA186_CLK_EXTPERIPH3 - * @def TEGRA186_CLK_EXTPERIPH4 - * @} - * - * @defgroup display_clks display related clocks - * @{ - * @def TEGRA186_CLK_CEC - * @def TEGRA186_CLK_DSIC - * @def TEGRA186_CLK_DSIC_LP - * @def TEGRA186_CLK_DSID - * @def TEGRA186_CLK_DSID_LP - * @def TEGRA186_CLK_DPAUX1 - * @def TEGRA186_CLK_DPAUX - * @def TEGRA186_CLK_HDA2HDMICODEC - * @def TEGRA186_CLK_NVDISPLAY_DISP - * @def TEGRA186_CLK_NVDISPLAY_DSC - * @def TEGRA186_CLK_NVDISPLAY_P0 - * @def TEGRA186_CLK_NVDISPLAY_P1 - * @def TEGRA186_CLK_NVDISPLAY_P2 - * @def TEGRA186_CLK_NVDISPLAYHUB - * @def TEGRA186_CLK_SOR_SAFE - * @def TEGRA186_CLK_SOR0 - * @def TEGRA186_CLK_SOR0_OUT - * @def TEGRA186_CLK_SOR1 - * @def TEGRA186_CLK_SOR1_OUT - * @def TEGRA186_CLK_DSI - * @def TEGRA186_CLK_MIPI_CAL - * @def TEGRA186_CLK_DSIA_LP - * @def TEGRA186_CLK_DSIB - * @def TEGRA186_CLK_DSIB_LP - * @} - * - * @defgroup camera_clks camera related clocks - * @{ - * @def TEGRA186_CLK_NVCSI - * @def TEGRA186_CLK_NVCSILP - * @def TEGRA186_CLK_VI - * @} - * - * @defgroup audio_clks audio related clocks - * @{ - * @def TEGRA186_CLK_ACLK - * @def TEGRA186_CLK_ADSP - * @def TEGRA186_CLK_ADSPNEON - * @def TEGRA186_CLK_AHUB - * @def TEGRA186_CLK_APE - * @def TEGRA186_CLK_APB2APE - * @def TEGRA186_CLK_AUD_MCLK - * @def TEGRA186_CLK_DMIC1 - * @def TEGRA186_CLK_DMIC2 - * @def TEGRA186_CLK_DMIC3 - * @def TEGRA186_CLK_DMIC4 - * @def TEGRA186_CLK_DSPK1 - * @def TEGRA186_CLK_DSPK2 - * @def TEGRA186_CLK_HDA - * @def TEGRA186_CLK_HDA2CODEC_2X - * @def TEGRA186_CLK_I2S1 - * @def TEGRA186_CLK_I2S2 - * @def TEGRA186_CLK_I2S3 - * @def TEGRA186_CLK_I2S4 - * @def TEGRA186_CLK_I2S5 - * @def TEGRA186_CLK_I2S6 - * @def TEGRA186_CLK_MAUD - * @def TEGRA186_CLK_PLL_A_OUT0 - * @def TEGRA186_CLK_SPDIF_DOUBLER - * @def TEGRA186_CLK_SPDIF_IN - * @def TEGRA186_CLK_SPDIF_OUT - * @def TEGRA186_CLK_SYNC_DMIC1 - * @def TEGRA186_CLK_SYNC_DMIC2 - * @def TEGRA186_CLK_SYNC_DMIC3 - * @def TEGRA186_CLK_SYNC_DMIC4 - * @def TEGRA186_CLK_SYNC_DMIC5 - * @def TEGRA186_CLK_SYNC_DSPK1 - * @def TEGRA186_CLK_SYNC_DSPK2 - * @def TEGRA186_CLK_SYNC_I2S1 - * @def TEGRA186_CLK_SYNC_I2S2 - * @def TEGRA186_CLK_SYNC_I2S3 - * @def TEGRA186_CLK_SYNC_I2S4 - * @def TEGRA186_CLK_SYNC_I2S5 - * @def TEGRA186_CLK_SYNC_I2S6 - * @def TEGRA186_CLK_SYNC_SPDIF - * @} - * - * @defgroup uart_clks UART clocks - * @{ - * @def TEGRA186_CLK_AON_UART_FST_MIPI_CAL - * @def TEGRA186_CLK_UARTA - * @def TEGRA186_CLK_UARTB - * @def TEGRA186_CLK_UARTC - * @def TEGRA186_CLK_UARTD - * @def TEGRA186_CLK_UARTE - * @def TEGRA186_CLK_UARTF - * @def TEGRA186_CLK_UARTG - * @def TEGRA186_CLK_UART_FST_MIPI_CAL - * @} - * - * @defgroup i2c_clks I2C clocks - * @{ - * @def TEGRA186_CLK_AON_I2C_SLOW - * @def TEGRA186_CLK_I2C1 - * @def TEGRA186_CLK_I2C2 - * @def TEGRA186_CLK_I2C3 - * @def TEGRA186_CLK_I2C4 - * @def TEGRA186_CLK_I2C5 - * @def TEGRA186_CLK_I2C6 - * @def TEGRA186_CLK_I2C8 - * @def TEGRA186_CLK_I2C9 - * @def TEGRA186_CLK_I2C1 - * @def TEGRA186_CLK_I2C12 - * @def TEGRA186_CLK_I2C13 - * @def TEGRA186_CLK_I2C14 - * @def TEGRA186_CLK_I2C_SLOW - * @def TEGRA186_CLK_VI_I2C - * @} - * - * @defgroup spi_clks SPI clocks - * @{ - * @def TEGRA186_CLK_SPI1 - * @def TEGRA186_CLK_SPI2 - * @def TEGRA186_CLK_SPI3 - * @def TEGRA186_CLK_SPI4 - * @} - * - * @defgroup storage storage related clocks - * @{ - * @def TEGRA186_CLK_SATA - * @def TEGRA186_CLK_SATA_OOB - * @def TEGRA186_CLK_SATA_IOBIST - * @def TEGRA186_CLK_SDMMC_LEGACY_TM - * @def TEGRA186_CLK_SDMMC1 - * @def TEGRA186_CLK_SDMMC2 - * @def TEGRA186_CLK_SDMMC3 - * @def TEGRA186_CLK_SDMMC4 - * @def TEGRA186_CLK_QSPI - * @def TEGRA186_CLK_QSPI_OUT - * @def TEGRA186_CLK_UFSDEV_REF - * @def TEGRA186_CLK_UFSHC - * @} - * - * @defgroup pwm_clks PWM clocks - * @{ - * @def TEGRA186_CLK_PWM1 - * @def TEGRA186_CLK_PWM2 - * @def TEGRA186_CLK_PWM3 - * @def TEGRA186_CLK_PWM4 - * @def TEGRA186_CLK_PWM5 - * @def TEGRA186_CLK_PWM6 - * @def TEGRA186_CLK_PWM7 - * @def TEGRA186_CLK_PWM8 - * @} - * - * @defgroup plls PLLs and related clocks - * @{ - * @def TEGRA186_CLK_PLLREFE_OUT_GATED - * @def TEGRA186_CLK_PLLREFE_OUT1 - * @def TEGRA186_CLK_PLLD_OUT1 - * @def TEGRA186_CLK_PLLP_OUT0 - * @def TEGRA186_CLK_PLLP_OUT5 - * @def TEGRA186_CLK_PLLA - * @def TEGRA186_CLK_PLLE_PWRSEQ - * @def TEGRA186_CLK_PLLA_OUT1 - * @def TEGRA186_CLK_PLLREFE_REF - * @def TEGRA186_CLK_UPHY_PLL0_PWRSEQ - * @def TEGRA186_CLK_UPHY_PLL1_PWRSEQ - * @def TEGRA186_CLK_PLLREFE_PLLE_PASSTHROUGH - * @def TEGRA186_CLK_PLLREFE_PEX - * @def TEGRA186_CLK_PLLREFE_IDDQ - * @def TEGRA186_CLK_PLLC_OUT_AON - * @def TEGRA186_CLK_PLLC_OUT_ISP - * @def TEGRA186_CLK_PLLC_OUT_VE - * @def TEGRA186_CLK_PLLC4_OUT - * @def TEGRA186_CLK_PLLREFE_OUT - * @def TEGRA186_CLK_PLLREFE_PLL_REF - * @def TEGRA186_CLK_PLLE - * @def TEGRA186_CLK_PLLC - * @def TEGRA186_CLK_PLLP - * @def TEGRA186_CLK_PLLD - * @def TEGRA186_CLK_PLLD2 - * @def TEGRA186_CLK_PLLREFE_VCO - * @def TEGRA186_CLK_PLLC2 - * @def TEGRA186_CLK_PLLC3 - * @def TEGRA186_CLK_PLLDP - * @def TEGRA186_CLK_PLLC4_VCO - * @def TEGRA186_CLK_PLLA1 - * @def TEGRA186_CLK_PLLNVCSI - * @def TEGRA186_CLK_PLLDISPHUB - * @def TEGRA186_CLK_PLLD3 - * @def TEGRA186_CLK_PLLBPMPCAM - * @def TEGRA186_CLK_PLLAON - * @def TEGRA186_CLK_PLLU - * @def TEGRA186_CLK_PLLC4_VCO_DIV2 - * @def TEGRA186_CLK_PLL_REF - * @def TEGRA186_CLK_PLLREFE_OUT1_DIV5 - * @def TEGRA186_CLK_UTMIP_PLL_PWRSEQ - * @def TEGRA186_CLK_PLL_U_48M - * @def TEGRA186_CLK_PLL_U_480M - * @def TEGRA186_CLK_PLLC4_OUT0 - * @def TEGRA186_CLK_PLLC4_OUT1 - * @def TEGRA186_CLK_PLLC4_OUT2 - * @def TEGRA186_CLK_PLLC4_OUT_MUX - * @def TEGRA186_CLK_DFLLDISP_DIV - * @def TEGRA186_CLK_PLLDISPHUB_DIV - * @def TEGRA186_CLK_PLLP_DIV8 - * @} - * - * @defgroup nafll_clks NAFLL clock sources - * @{ - * @def TEGRA186_CLK_NAFLL_AXI_CBB - * @def TEGRA186_CLK_NAFLL_BCPU - * @def TEGRA186_CLK_NAFLL_BPMP - * @def TEGRA186_CLK_NAFLL_DISP - * @def TEGRA186_CLK_NAFLL_GPU - * @def TEGRA186_CLK_NAFLL_ISP - * @def TEGRA186_CLK_NAFLL_MCPU - * @def TEGRA186_CLK_NAFLL_NVDEC - * @def TEGRA186_CLK_NAFLL_NVENC - * @def TEGRA186_CLK_NAFLL_NVJPG - * @def TEGRA186_CLK_NAFLL_SCE - * @def TEGRA186_CLK_NAFLL_SE - * @def TEGRA186_CLK_NAFLL_TSEC - * @def TEGRA186_CLK_NAFLL_TSECB - * @def TEGRA186_CLK_NAFLL_VI - * @def TEGRA186_CLK_NAFLL_VIC - * @} - * - * @defgroup mphy MPHY related clocks - * @{ - * @def TEGRA186_CLK_MPHY_L0_RX_SYMB - * @def TEGRA186_CLK_MPHY_L0_RX_LS_BIT - * @def TEGRA186_CLK_MPHY_L0_TX_SYMB - * @def TEGRA186_CLK_MPHY_L0_TX_LS_3XBIT - * @def TEGRA186_CLK_MPHY_L0_RX_ANA - * @def TEGRA186_CLK_MPHY_L1_RX_ANA - * @def TEGRA186_CLK_MPHY_IOBIST - * @def TEGRA186_CLK_MPHY_TX_1MHZ_REF - * @def TEGRA186_CLK_MPHY_CORE_PLL_FIXED - * @} - * - * @defgroup eavb EAVB related clocks - * @{ - * @def TEGRA186_CLK_EQOS_AXI - * @def TEGRA186_CLK_EQOS_PTP_REF - * @def TEGRA186_CLK_EQOS_RX - * @def TEGRA186_CLK_EQOS_RX_INPUT - * @def TEGRA186_CLK_EQOS_TX - * @} - * - * @defgroup usb USB related clocks - * @{ - * @def TEGRA186_CLK_PEX_USB_PAD0_MGMT - * @def TEGRA186_CLK_PEX_USB_PAD1_MGMT - * @def TEGRA186_CLK_HSIC_TRK - * @def TEGRA186_CLK_USB2_TRK - * @def TEGRA186_CLK_USB2_HSIC_TRK - * @def TEGRA186_CLK_XUSB_CORE_SS - * @def TEGRA186_CLK_XUSB_CORE_DEV - * @def TEGRA186_CLK_XUSB_FALCON - * @def TEGRA186_CLK_XUSB_FS - * @def TEGRA186_CLK_XUSB - * @def TEGRA186_CLK_XUSB_DEV - * @def TEGRA186_CLK_XUSB_HOST - * @def TEGRA186_CLK_XUSB_SS - * @} - * - * @defgroup bigblock compute block related clocks - * @{ - * @def TEGRA186_CLK_GPCCLK - * @def TEGRA186_CLK_GPC2CLK - * @def TEGRA186_CLK_GPU - * @def TEGRA186_CLK_HOST1X - * @def TEGRA186_CLK_ISP - * @def TEGRA186_CLK_NVDEC - * @def TEGRA186_CLK_NVENC - * @def TEGRA186_CLK_NVJPG - * @def TEGRA186_CLK_SE - * @def TEGRA186_CLK_TSEC - * @def TEGRA186_CLK_TSECB - * @def TEGRA186_CLK_VIC - * @} - * - * @defgroup can CAN bus related clocks - * @{ - * @def TEGRA186_CLK_CAN1 - * @def TEGRA186_CLK_CAN1_HOST - * @def TEGRA186_CLK_CAN2 - * @def TEGRA186_CLK_CAN2_HOST - * @} - * - * @defgroup system basic system clocks - * @{ - * @def TEGRA186_CLK_ACTMON - * @def TEGRA186_CLK_AON_APB - * @def TEGRA186_CLK_AON_CPU_NIC - * @def TEGRA186_CLK_AON_NIC - * @def TEGRA186_CLK_AXI_CBB - * @def TEGRA186_CLK_BPMP_APB - * @def TEGRA186_CLK_BPMP_CPU_NIC - * @def TEGRA186_CLK_BPMP_NIC_RATE - * @def TEGRA186_CLK_CLK_M - * @def TEGRA186_CLK_EMC - * @def TEGRA186_CLK_MSS_ENCRYPT - * @def TEGRA186_CLK_SCE_APB - * @def TEGRA186_CLK_SCE_CPU_NIC - * @def TEGRA186_CLK_SCE_NIC - * @def TEGRA186_CLK_TSC - * @} - * - * @defgroup pcie_clks PCIe related clocks - * @{ - * @def TEGRA186_CLK_AFI - * @def TEGRA186_CLK_PCIE - * @def TEGRA186_CLK_PCIE2_IOBIST - * @def TEGRA186_CLK_PCIERX0 - * @def TEGRA186_CLK_PCIERX1 - * @def TEGRA186_CLK_PCIERX2 - * @def TEGRA186_CLK_PCIERX3 - * @def TEGRA186_CLK_PCIERX4 - * @} - */ - -/** @brief output of gate CLK_ENB_FUSE */ -#define TEGRA186_CLK_FUSE 0 -/** - * @brief It's not what you think - * @details output of gate CLK_ENB_GPU. This output connects to the GPU - * pwrclk. @warning: This is almost certainly not the clock you think - * it is. If you're looking for the clock of the graphics engine, see - * TEGRA186_GPCCLK - */ -#define TEGRA186_CLK_GPU 1 -/** @brief output of gate CLK_ENB_PCIE */ -#define TEGRA186_CLK_PCIE 3 -/** @brief output of the divider IPFS_CLK_DIVISOR */ -#define TEGRA186_CLK_AFI 4 -/** @brief output of gate CLK_ENB_PCIE2_IOBIST */ -#define TEGRA186_CLK_PCIE2_IOBIST 5 -/** @brief output of gate CLK_ENB_PCIERX0*/ -#define TEGRA186_CLK_PCIERX0 6 -/** @brief output of gate CLK_ENB_PCIERX1*/ -#define TEGRA186_CLK_PCIERX1 7 -/** @brief output of gate CLK_ENB_PCIERX2*/ -#define TEGRA186_CLK_PCIERX2 8 -/** @brief output of gate CLK_ENB_PCIERX3*/ -#define TEGRA186_CLK_PCIERX3 9 -/** @brief output of gate CLK_ENB_PCIERX4*/ -#define TEGRA186_CLK_PCIERX4 10 -/** @brief output branch of PLL_C for ISP, controlled by gate CLK_ENB_PLLC_OUT_ISP */ -#define TEGRA186_CLK_PLLC_OUT_ISP 11 -/** @brief output branch of PLL_C for VI, controlled by gate CLK_ENB_PLLC_OUT_VE */ -#define TEGRA186_CLK_PLLC_OUT_VE 12 -/** @brief output branch of PLL_C for AON domain, controlled by gate CLK_ENB_PLLC_OUT_AON */ -#define TEGRA186_CLK_PLLC_OUT_AON 13 -/** @brief output of gate CLK_ENB_SOR_SAFE */ -#define TEGRA186_CLK_SOR_SAFE 39 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S2 */ -#define TEGRA186_CLK_I2S2 42 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S3 */ -#define TEGRA186_CLK_I2S3 43 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPDF_IN */ -#define TEGRA186_CLK_SPDIF_IN 44 -/** @brief output of gate CLK_ENB_SPDIF_DOUBLER */ -#define TEGRA186_CLK_SPDIF_DOUBLER 45 -/** @clkdesc{spi_clks, out, mux, CLK_RST_CONTROLLER_CLK_SOURCE_SPI3} */ -#define TEGRA186_CLK_SPI3 46 -/** @clkdesc{i2c_clks, out, mux, CLK_RST_CONTROLLER_CLK_SOURCE_I2C1} */ -#define TEGRA186_CLK_I2C1 47 -/** @clkdesc{i2c_clks, out, mux, CLK_RST_CONTROLLER_CLK_SOURCE_I2C5} */ -#define TEGRA186_CLK_I2C5 48 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI1 */ -#define TEGRA186_CLK_SPI1 49 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_ISP */ -#define TEGRA186_CLK_ISP 50 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VI */ -#define TEGRA186_CLK_VI 51 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1 */ -#define TEGRA186_CLK_SDMMC1 52 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2 */ -#define TEGRA186_CLK_SDMMC2 53 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */ -#define TEGRA186_CLK_SDMMC4 54 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */ -#define TEGRA186_CLK_UARTA 55 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTB */ -#define TEGRA186_CLK_UARTB 56 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X */ -#define TEGRA186_CLK_HOST1X 57 -/** - * @brief controls the EMC clock frequency. - * @details Doing a clk_set_rate on this clock will select the - * appropriate clock source, program the source rate and execute a - * specific sequence to switch to the new clock source for both memory - * controllers. This can be used to control the balance between memory - * throughput and memory controller power. - */ -#define TEGRA186_CLK_EMC 58 -/* @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4 */ -#define TEGRA186_CLK_EXTPERIPH4 73 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI4 */ -#define TEGRA186_CLK_SPI4 74 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C3 */ -#define TEGRA186_CLK_I2C3 75 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3 */ -#define TEGRA186_CLK_SDMMC3 76 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTD */ -#define TEGRA186_CLK_UARTD 77 -/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S1 */ -#define TEGRA186_CLK_I2S1 79 -/** output of gate CLK_ENB_DTV */ -#define TEGRA186_CLK_DTV 80 -/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TSEC */ -#define TEGRA186_CLK_TSEC 81 -/** @brief output of gate CLK_ENB_DP2 */ -#define TEGRA186_CLK_DP2 82 -/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S4 */ -#define TEGRA186_CLK_I2S4 84 -/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S5 */ -#define TEGRA186_CLK_I2S5 85 -/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C4 */ -#define TEGRA186_CLK_I2C4 86 -/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AHUB */ -#define TEGRA186_CLK_AHUB 87 -/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X */ -#define TEGRA186_CLK_HDA2CODEC_2X 88 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1 */ -#define TEGRA186_CLK_EXTPERIPH1 89 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2 */ -#define TEGRA186_CLK_EXTPERIPH2 90 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3 */ -#define TEGRA186_CLK_EXTPERIPH3 91 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW */ -#define TEGRA186_CLK_I2C_SLOW 92 -/** @brief output of the SOR1_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR1 */ -#define TEGRA186_CLK_SOR1 93 -/** @brief output of gate CLK_ENB_CEC */ -#define TEGRA186_CLK_CEC 94 -/** @brief output of gate CLK_ENB_DPAUX1 */ -#define TEGRA186_CLK_DPAUX1 95 -/** @brief output of gate CLK_ENB_DPAUX */ -#define TEGRA186_CLK_DPAUX 96 -/** @brief output of the SOR0_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR0 */ -#define TEGRA186_CLK_SOR0 97 -/** @brief output of gate CLK_ENB_HDA2HDMICODEC */ -#define TEGRA186_CLK_HDA2HDMICODEC 98 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SATA */ -#define TEGRA186_CLK_SATA 99 -/** @brief output of gate CLK_ENB_SATA_OOB */ -#define TEGRA186_CLK_SATA_OOB 100 -/** @brief output of gate CLK_ENB_SATA_IOBIST */ -#define TEGRA186_CLK_SATA_IOBIST 101 -/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HDA */ -#define TEGRA186_CLK_HDA 102 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SE */ -#define TEGRA186_CLK_SE 103 -/** @brief output of gate CLK_ENB_APB2APE */ -#define TEGRA186_CLK_APB2APE 104 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_APE */ -#define TEGRA186_CLK_APE 105 -/** @brief output of gate CLK_ENB_IQC1 */ -#define TEGRA186_CLK_IQC1 106 -/** @brief output of gate CLK_ENB_IQC2 */ -#define TEGRA186_CLK_IQC2 107 -/** divide by 2 version of TEGRA186_CLK_PLLREFE_VCO */ -#define TEGRA186_CLK_PLLREFE_OUT 108 -/** @brief output of gate CLK_ENB_PLLREFE_PLL_REF */ -#define TEGRA186_CLK_PLLREFE_PLL_REF 109 -/** @brief output of gate CLK_ENB_PLLC4_OUT */ -#define TEGRA186_CLK_PLLC4_OUT 110 -/** @brief output of mux xusb_core_clk_switch on page 67 of T186_Clocks_IAS.doc */ -#define TEGRA186_CLK_XUSB 111 -/** controls xusb_dev_ce signal on page 66 and 67 of T186_Clocks_IAS.doc */ -#define TEGRA186_CLK_XUSB_DEV 112 -/** controls xusb_host_ce signal on page 67 of T186_Clocks_IAS.doc */ -#define TEGRA186_CLK_XUSB_HOST 113 -/** controls xusb_ss_ce signal on page 67 of T186_Clocks_IAS.doc */ -#define TEGRA186_CLK_XUSB_SS 114 -/** @brief output of gate CLK_ENB_DSI */ -#define TEGRA186_CLK_DSI 115 -/** @brief output of gate CLK_ENB_MIPI_CAL */ -#define TEGRA186_CLK_MIPI_CAL 116 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP */ -#define TEGRA186_CLK_DSIA_LP 117 -/** @brief output of gate CLK_ENB_DSIB */ -#define TEGRA186_CLK_DSIB 118 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSIB_LP */ -#define TEGRA186_CLK_DSIB_LP 119 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1 */ -#define TEGRA186_CLK_DMIC1 122 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2 */ -#define TEGRA186_CLK_DMIC2 123 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK */ -#define TEGRA186_CLK_AUD_MCLK 124 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 */ -#define TEGRA186_CLK_I2C6 125 -/**output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL */ -#define TEGRA186_CLK_UART_FST_MIPI_CAL 126 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VIC */ -#define TEGRA186_CLK_VIC 127 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM */ -#define TEGRA186_CLK_SDMMC_LEGACY_TM 128 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC */ -#define TEGRA186_CLK_NVDEC 129 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG */ -#define TEGRA186_CLK_NVJPG 130 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVENC */ -#define TEGRA186_CLK_NVENC 131 -/** @brief output of the QSPI_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI */ -#define TEGRA186_CLK_QSPI 132 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VI_I2C */ -#define TEGRA186_CLK_VI_I2C 133 -/** @brief output of gate CLK_ENB_HSIC_TRK */ -#define TEGRA186_CLK_HSIC_TRK 134 -/** @brief output of gate CLK_ENB_USB2_TRK */ -#define TEGRA186_CLK_USB2_TRK 135 -/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_MAUD */ -#define TEGRA186_CLK_MAUD 136 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TSECB */ -#define TEGRA186_CLK_TSECB 137 -/** @brief output of gate CLK_ENB_ADSP */ -#define TEGRA186_CLK_ADSP 138 -/** @brief output of gate CLK_ENB_ADSPNEON */ -#define TEGRA186_CLK_ADSPNEON 139 -/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_RX_LS_SYMB */ -#define TEGRA186_CLK_MPHY_L0_RX_SYMB 140 -/** @brief output of gate CLK_ENB_MPHY_L0_RX_LS_BIT */ -#define TEGRA186_CLK_MPHY_L0_RX_LS_BIT 141 -/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_TX_LS_SYMB */ -#define TEGRA186_CLK_MPHY_L0_TX_SYMB 142 -/** @brief output of gate CLK_ENB_MPHY_L0_TX_LS_3XBIT */ -#define TEGRA186_CLK_MPHY_L0_TX_LS_3XBIT 143 -/** @brief output of gate CLK_ENB_MPHY_L0_RX_ANA */ -#define TEGRA186_CLK_MPHY_L0_RX_ANA 144 -/** @brief output of gate CLK_ENB_MPHY_L1_RX_ANA */ -#define TEGRA186_CLK_MPHY_L1_RX_ANA 145 -/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_IOBIST */ -#define TEGRA186_CLK_MPHY_IOBIST 146 -/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_TX_1MHZ_REF */ -#define TEGRA186_CLK_MPHY_TX_1MHZ_REF 147 -/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_CORE_PLL_FIXED */ -#define TEGRA186_CLK_MPHY_CORE_PLL_FIXED 148 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB */ -#define TEGRA186_CLK_AXI_CBB 149 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3 */ -#define TEGRA186_CLK_DMIC3 150 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4 */ -#define TEGRA186_CLK_DMIC4 151 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1 */ -#define TEGRA186_CLK_DSPK1 152 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2 */ -#define TEGRA186_CLK_DSPK2 153 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 */ -#define TEGRA186_CLK_I2S6 154 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0 */ -#define TEGRA186_CLK_NVDISPLAY_P0 155 -/** @brief output of the NVDISPLAY_DISP_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP */ -#define TEGRA186_CLK_NVDISPLAY_DISP 156 -/** @brief output of gate CLK_ENB_NVDISPLAY_DSC */ -#define TEGRA186_CLK_NVDISPLAY_DSC 157 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB */ -#define TEGRA186_CLK_NVDISPLAYHUB 158 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1 */ -#define TEGRA186_CLK_NVDISPLAY_P1 159 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2 */ -#define TEGRA186_CLK_NVDISPLAY_P2 160 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TACH */ -#define TEGRA186_CLK_TACH 166 -/** @brief output of gate CLK_ENB_EQOS */ -#define TEGRA186_CLK_EQOS_AXI 167 -/** @brief output of gate CLK_ENB_EQOS_RX */ -#define TEGRA186_CLK_EQOS_RX 168 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS */ -#define TEGRA186_CLK_UFSHC 178 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF */ -#define TEGRA186_CLK_UFSDEV_REF 179 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI */ -#define TEGRA186_CLK_NVCSI 180 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP */ -#define TEGRA186_CLK_NVCSILP 181 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C7 */ -#define TEGRA186_CLK_I2C7 182 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C9 */ -#define TEGRA186_CLK_I2C9 183 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C12 */ -#define TEGRA186_CLK_I2C12 184 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C13 */ -#define TEGRA186_CLK_I2C13 185 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C14 */ -#define TEGRA186_CLK_I2C14 186 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM1 */ -#define TEGRA186_CLK_PWM1 187 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM2 */ -#define TEGRA186_CLK_PWM2 188 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM3 */ -#define TEGRA186_CLK_PWM3 189 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM5 */ -#define TEGRA186_CLK_PWM5 190 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM6 */ -#define TEGRA186_CLK_PWM6 191 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM7 */ -#define TEGRA186_CLK_PWM7 192 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM8 */ -#define TEGRA186_CLK_PWM8 193 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTE */ -#define TEGRA186_CLK_UARTE 194 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTF */ -#define TEGRA186_CLK_UARTF 195 -/** @deprecated */ -#define TEGRA186_CLK_DBGAPB 196 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC */ -#define TEGRA186_CLK_BPMP_CPU_NIC 197 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB */ -#define TEGRA186_CLK_BPMP_APB 199 -/** @brief output of mux controlled by TEGRA186_CLK_SOC_ACTMON */ -#define TEGRA186_CLK_ACTMON 201 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC */ -#define TEGRA186_CLK_AON_CPU_NIC 208 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_CAN1 */ -#define TEGRA186_CLK_CAN1 210 -/** @brief output of gate CLK_ENB_CAN1_HOST */ -#define TEGRA186_CLK_CAN1_HOST 211 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_CAN2 */ -#define TEGRA186_CLK_CAN2 212 -/** @brief output of gate CLK_ENB_CAN2_HOST */ -#define TEGRA186_CLK_CAN2_HOST 213 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB */ -#define TEGRA186_CLK_AON_APB 214 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTC */ -#define TEGRA186_CLK_UARTC 215 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTG */ -#define TEGRA186_CLK_UARTG 216 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL */ -#define TEGRA186_CLK_AON_UART_FST_MIPI_CAL 217 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C2 */ -#define TEGRA186_CLK_I2C2 218 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C8 */ -#define TEGRA186_CLK_I2C8 219 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C10 */ -#define TEGRA186_CLK_I2C10 220 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW */ -#define TEGRA186_CLK_AON_I2C_SLOW 221 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI2 */ -#define TEGRA186_CLK_SPI2 222 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5 */ -#define TEGRA186_CLK_DMIC5 223 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH */ -#define TEGRA186_CLK_AON_TOUCH 224 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM4 */ -#define TEGRA186_CLK_PWM4 225 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TSC. This clock object is read only and is used for all timers in the system. */ -#define TEGRA186_CLK_TSC 226 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT */ -#define TEGRA186_CLK_MSS_ENCRYPT 227 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC */ -#define TEGRA186_CLK_SCE_CPU_NIC 228 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB */ -#define TEGRA186_CLK_SCE_APB 230 -/** @brief output of gate CLK_ENB_DSIC */ -#define TEGRA186_CLK_DSIC 231 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSIC_LP */ -#define TEGRA186_CLK_DSIC_LP 232 -/** @brief output of gate CLK_ENB_DSID */ -#define TEGRA186_CLK_DSID 233 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSID_LP */ -#define TEGRA186_CLK_DSID_LP 234 -/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP */ -#define TEGRA186_CLK_PEX_SATA_USB_RX_BYP 236 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT */ -#define TEGRA186_CLK_SPDIF_OUT 238 -/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_PTP_REF_CLK_0 */ -#define TEGRA186_CLK_EQOS_PTP_REF 239 -/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK */ -#define TEGRA186_CLK_EQOS_TX 240 -/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK */ -#define TEGRA186_CLK_USB2_HSIC_TRK 241 -/** @brief output of mux xusb_ss_clk_switch on page 66 of T186_Clocks_IAS.doc */ -#define TEGRA186_CLK_XUSB_CORE_SS 242 -/** @brief output of mux xusb_core_dev_clk_switch on page 67 of T186_Clocks_IAS.doc */ -#define TEGRA186_CLK_XUSB_CORE_DEV 243 -/** @brief output of mux xusb_core_falcon_clk_switch on page 67 of T186_Clocks_IAS.doc */ -#define TEGRA186_CLK_XUSB_FALCON 244 -/** @brief output of mux xusb_fs_clk_switch on page 66 of T186_Clocks_IAS.doc */ -#define TEGRA186_CLK_XUSB_FS 245 -/** @brief output of the divider CLK_RST_CONTROLLER_PLLA_OUT */ -#define TEGRA186_CLK_PLL_A_OUT0 246 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1 */ -#define TEGRA186_CLK_SYNC_I2S1 247 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2 */ -#define TEGRA186_CLK_SYNC_I2S2 248 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3 */ -#define TEGRA186_CLK_SYNC_I2S3 249 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4 */ -#define TEGRA186_CLK_SYNC_I2S4 250 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5 */ -#define TEGRA186_CLK_SYNC_I2S5 251 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6 */ -#define TEGRA186_CLK_SYNC_I2S6 252 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1 */ -#define TEGRA186_CLK_SYNC_DSPK1 253 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2 */ -#define TEGRA186_CLK_SYNC_DSPK2 254 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1 */ -#define TEGRA186_CLK_SYNC_DMIC1 255 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2 */ -#define TEGRA186_CLK_SYNC_DMIC2 256 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3 */ -#define TEGRA186_CLK_SYNC_DMIC3 257 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4 */ -#define TEGRA186_CLK_SYNC_DMIC4 259 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF */ -#define TEGRA186_CLK_SYNC_SPDIF 260 -/** @brief output of gate CLK_ENB_PLLREFE_OUT */ -#define TEGRA186_CLK_PLLREFE_OUT_GATED 261 -/** @brief output of the divider PLLREFE_DIVP in CLK_RST_CONTROLLER_PLLREFE_BASE. PLLREFE has 2 outputs: - * * VCO/pdiv defined by this clock object - * * VCO/2 defined by TEGRA186_CLK_PLLREFE_OUT - */ -#define TEGRA186_CLK_PLLREFE_OUT1 262 -#define TEGRA186_CLK_PLLD_OUT1 267 -/** @brief output of the divider PLLP_DIVP in CLK_RST_CONTROLLER_PLLP_BASE */ -#define TEGRA186_CLK_PLLP_OUT0 269 -/** @brief output of the divider CLK_RST_CONTROLLER_PLLP_OUTC */ -#define TEGRA186_CLK_PLLP_OUT5 270 -/** PLL controlled by CLK_RST_CONTROLLER_PLLA_BASE for use by audio clocks */ -#define TEGRA186_CLK_PLLA 271 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_ACLK_BURST_POLICY divided by the divider controlled by ACLK_CLK_DIVISOR in CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER */ -#define TEGRA186_CLK_ACLK 273 -/** fixed 48MHz clock divided down from TEGRA186_CLK_PLL_U */ -#define TEGRA186_CLK_PLL_U_48M 274 -/** fixed 480MHz clock divided down from TEGRA186_CLK_PLL_U */ -#define TEGRA186_CLK_PLL_U_480M 275 -/** @brief output of the divider PLLC4_DIVP in CLK_RST_CONTROLLER_PLLC4_BASE. Output frequency is TEGRA186_CLK_PLLC4_VCO/PLLC4_DIVP */ -#define TEGRA186_CLK_PLLC4_OUT0 276 -/** fixed /3 divider. Output frequency of this clock is TEGRA186_CLK_PLLC4_VCO/3 */ -#define TEGRA186_CLK_PLLC4_OUT1 277 -/** fixed /5 divider. Output frequency of this clock is TEGRA186_CLK_PLLC4_VCO/5 */ -#define TEGRA186_CLK_PLLC4_OUT2 278 -/** @brief output of mux controlled by PLLC4_CLK_SEL in CLK_RST_CONTROLLER_PLLC4_MISC1 */ -#define TEGRA186_CLK_PLLC4_OUT_MUX 279 -/** @brief output of divider NVDISPLAY_DISP_CLK_DIVISOR in CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP when DFLLDISP_DIV is selected in NVDISPLAY_DISP_CLK_SRC */ -#define TEGRA186_CLK_DFLLDISP_DIV 284 -/** @brief output of divider NVDISPLAY_DISP_CLK_DIVISOR in CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP when PLLDISPHUB_DIV is selected in NVDISPLAY_DISP_CLK_SRC */ -#define TEGRA186_CLK_PLLDISPHUB_DIV 285 -/** fixed /8 divider which is used as the input for TEGRA186_CLK_SOR_SAFE */ -#define TEGRA186_CLK_PLLP_DIV8 286 -/** @brief output of divider CLK_RST_CONTROLLER_BPMP_NIC_RATE */ -#define TEGRA186_CLK_BPMP_NIC 287 -/** @brief output of the divider CLK_RST_CONTROLLER_PLLA1_OUT1 */ -#define TEGRA186_CLK_PLL_A_OUT1 288 -/** @deprecated */ -#define TEGRA186_CLK_GPC2CLK 289 -/** A fake clock which must be enabled during KFUSE read operations to ensure adequate VDD_CORE voltage. */ -#define TEGRA186_CLK_KFUSE 293 -/** - * @brief controls the PLLE hardware sequencer. - * @details This clock only has enable and disable methods. When the - * PLLE hw sequencer is enabled, PLLE, will be enabled or disabled by - * hw based on the control signals from the PCIe, SATA and XUSB - * clocks. When the PLLE hw sequencer is disabled, the state of PLLE - * is controlled by sw using clk_enable/clk_disable on - * TEGRA186_CLK_PLLE. - */ -#define TEGRA186_CLK_PLLE_PWRSEQ 294 -/** fixed 60MHz clock divided down from, TEGRA186_CLK_PLL_U */ -#define TEGRA186_CLK_PLLREFE_REF 295 -/** @brief output of mux controlled by SOR0_CLK_SEL0 and SOR0_CLK_SEL1 in CLK_RST_CONTROLLER_CLK_SOURCE_SOR0 */ -#define TEGRA186_CLK_SOR0_OUT 296 -/** @brief output of mux controlled by SOR1_CLK_SEL0 and SOR1_CLK_SEL1 in CLK_RST_CONTROLLER_CLK_SOURCE_SOR1 */ -#define TEGRA186_CLK_SOR1_OUT 297 -/** @brief fixed /5 divider. Output frequency of this clock is TEGRA186_CLK_PLLREFE_OUT1/5. Used as input for TEGRA186_CLK_EQOS_AXI */ -#define TEGRA186_CLK_PLLREFE_OUT1_DIV5 298 -/** @brief controls the UTMIP_PLL (aka PLLU) hardware sqeuencer */ -#define TEGRA186_CLK_UTMIP_PLL_PWRSEQ 301 -/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT */ -#define TEGRA186_CLK_PEX_USB_PAD0_MGMT 302 -/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT */ -#define TEGRA186_CLK_PEX_USB_PAD1_MGMT 303 -/** @brief controls the UPHY_PLL0 hardware sqeuencer */ -#define TEGRA186_CLK_UPHY_PLL0_PWRSEQ 304 -/** @brief controls the UPHY_PLL1 hardware sqeuencer */ -#define TEGRA186_CLK_UPHY_PLL1_PWRSEQ 305 -/** @brief control for PLLREFE_IDDQ in CLK_RST_CONTROLLER_PLLREFE_MISC so the bypass output even be used when the PLL is disabled */ -#define TEGRA186_CLK_PLLREFE_PLLE_PASSTHROUGH 306 -/** @brief output of the mux controlled by PLLREFE_SEL_CLKIN_PEX in CLK_RST_CONTROLLER_PLLREFE_MISC */ -#define TEGRA186_CLK_PLLREFE_PEX 307 -/** @brief control for PLLREFE_IDDQ in CLK_RST_CONTROLLER_PLLREFE_MISC to turn on the PLL when enabled */ -#define TEGRA186_CLK_PLLREFE_IDDQ 308 -/** @brief output of the divider QSPI_CLK_DIV2_SEL in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI */ -#define TEGRA186_CLK_QSPI_OUT 309 -/** - * @brief GPC2CLK-div-2 - * @details fixed /2 divider. Output frequency is - * TEGRA186_CLK_GPC2CLK/2. The frequency of this clock is the - * frequency at which the GPU graphics engine runs. */ -#define TEGRA186_CLK_GPCCLK 310 -/** @brief output of divider CLK_RST_CONTROLLER_AON_NIC_RATE */ -#define TEGRA186_CLK_AON_NIC 450 -/** @brief output of divider CLK_RST_CONTROLLER_SCE_NIC_RATE */ -#define TEGRA186_CLK_SCE_NIC 451 -/** Fixed 100MHz PLL for PCIe, SATA and superspeed USB */ -#define TEGRA186_CLK_PLLE 512 -/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC_BASE */ -#define TEGRA186_CLK_PLLC 513 -/** Fixed 408MHz PLL for use by peripheral clocks */ -#define TEGRA186_CLK_PLLP 516 -/** @deprecated */ -#define TEGRA186_CLK_PLL_P TEGRA186_CLK_PLLP -/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLD_BASE for use by DSI */ -#define TEGRA186_CLK_PLLD 518 -/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLD2_BASE for use by HDMI or DP */ -#define TEGRA186_CLK_PLLD2 519 -/** - * @brief PLL controlled by CLK_RST_CONTROLLER_PLLREFE_BASE. - * @details Note that this clock only controls the VCO output, before - * the post-divider. See TEGRA186_CLK_PLLREFE_OUT1 for more - * information. - */ -#define TEGRA186_CLK_PLLREFE_VCO 520 -/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC2_BASE */ -#define TEGRA186_CLK_PLLC2 521 -/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC3_BASE */ -#define TEGRA186_CLK_PLLC3 522 -/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLDP_BASE for use as the DP link clock */ -#define TEGRA186_CLK_PLLDP 523 -/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC4_BASE */ -#define TEGRA186_CLK_PLLC4_VCO 524 -/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLA1_BASE for use by audio clocks */ -#define TEGRA186_CLK_PLLA1 525 -/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLNVCSI_BASE */ -#define TEGRA186_CLK_PLLNVCSI 526 -/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLDISPHUB_BASE */ -#define TEGRA186_CLK_PLLDISPHUB 527 -/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLD3_BASE for use by HDMI or DP */ -#define TEGRA186_CLK_PLLD3 528 -/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLBPMPCAM_BASE */ -#define TEGRA186_CLK_PLLBPMPCAM 531 -/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLAON_BASE for use by IP blocks in the AON domain */ -#define TEGRA186_CLK_PLLAON 532 -/** Fixed frequency 960MHz PLL for USB and EAVB */ -#define TEGRA186_CLK_PLLU 533 -/** fixed /2 divider. Output frequency is TEGRA186_CLK_PLLC4_VCO/2 */ -#define TEGRA186_CLK_PLLC4_VCO_DIV2 535 -/** @brief NAFLL clock source for AXI_CBB */ -#define TEGRA186_CLK_NAFLL_AXI_CBB 564 -/** @brief NAFLL clock source for BPMP */ -#define TEGRA186_CLK_NAFLL_BPMP 565 -/** @brief NAFLL clock source for ISP */ -#define TEGRA186_CLK_NAFLL_ISP 566 -/** @brief NAFLL clock source for NVDEC */ -#define TEGRA186_CLK_NAFLL_NVDEC 567 -/** @brief NAFLL clock source for NVENC */ -#define TEGRA186_CLK_NAFLL_NVENC 568 -/** @brief NAFLL clock source for NVJPG */ -#define TEGRA186_CLK_NAFLL_NVJPG 569 -/** @brief NAFLL clock source for SCE */ -#define TEGRA186_CLK_NAFLL_SCE 570 -/** @brief NAFLL clock source for SE */ -#define TEGRA186_CLK_NAFLL_SE 571 -/** @brief NAFLL clock source for TSEC */ -#define TEGRA186_CLK_NAFLL_TSEC 572 -/** @brief NAFLL clock source for TSECB */ -#define TEGRA186_CLK_NAFLL_TSECB 573 -/** @brief NAFLL clock source for VI */ -#define TEGRA186_CLK_NAFLL_VI 574 -/** @brief NAFLL clock source for VIC */ -#define TEGRA186_CLK_NAFLL_VIC 575 -/** @brief NAFLL clock source for DISP */ -#define TEGRA186_CLK_NAFLL_DISP 576 -/** @brief NAFLL clock source for GPU */ -#define TEGRA186_CLK_NAFLL_GPU 577 -/** @brief NAFLL clock source for M-CPU cluster */ -#define TEGRA186_CLK_NAFLL_MCPU 578 -/** @brief NAFLL clock source for B-CPU cluster */ -#define TEGRA186_CLK_NAFLL_BCPU 579 -/** @brief input from Tegra's CLK_32K_IN pad */ -#define TEGRA186_CLK_CLK_32K 608 -/** @brief output of divider CLK_RST_CONTROLLER_CLK_M_DIVIDE */ -#define TEGRA186_CLK_CLK_M 609 -/** @brief output of divider PLL_REF_DIV in CLK_RST_CONTROLLER_OSC_CTRL */ -#define TEGRA186_CLK_PLL_REF 610 -/** @brief input from Tegra's XTAL_IN */ -#define TEGRA186_CLK_OSC 612 -/** @brief clock recovered from EAVB input */ -#define TEGRA186_CLK_EQOS_RX_INPUT 613 -/** @brief clock recovered from DTV input */ -#define TEGRA186_CLK_DTV_INPUT 614 -/** @brief SOR0 brick output which feeds into SOR0_CLK_SEL mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR0*/ -#define TEGRA186_CLK_SOR0_PAD_CLKOUT 615 -/** @brief SOR1 brick output which feeds into SOR1_CLK_SEL mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR1*/ -#define TEGRA186_CLK_SOR1_PAD_CLKOUT 616 -/** @brief clock recovered from I2S1 input */ -#define TEGRA186_CLK_I2S1_SYNC_INPUT 617 -/** @brief clock recovered from I2S2 input */ -#define TEGRA186_CLK_I2S2_SYNC_INPUT 618 -/** @brief clock recovered from I2S3 input */ -#define TEGRA186_CLK_I2S3_SYNC_INPUT 619 -/** @brief clock recovered from I2S4 input */ -#define TEGRA186_CLK_I2S4_SYNC_INPUT 620 -/** @brief clock recovered from I2S5 input */ -#define TEGRA186_CLK_I2S5_SYNC_INPUT 621 -/** @brief clock recovered from I2S6 input */ -#define TEGRA186_CLK_I2S6_SYNC_INPUT 622 -/** @brief clock recovered from SPDIFIN input */ -#define TEGRA186_CLK_SPDIFIN_SYNC_INPUT 623 - -/** - * @brief subject to change - * @details maximum clock identifier value plus one. - */ -#define TEGRA186_CLK_CLK_MAX 624 - -/** @} */ - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/tegra194-clock.h b/sys/gnu/dts/include/dt-bindings/clock/tegra194-clock.h deleted file mode 100644 index a2ff66342d6..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/tegra194-clock.h +++ /dev/null @@ -1,321 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. */ - -#ifndef __ABI_MACH_T194_CLOCK_H -#define __ABI_MACH_T194_CLOCK_H - -#define TEGRA194_CLK_ACTMON 1 -#define TEGRA194_CLK_ADSP 2 -#define TEGRA194_CLK_ADSPNEON 3 -#define TEGRA194_CLK_AHUB 4 -#define TEGRA194_CLK_APB2APE 5 -#define TEGRA194_CLK_APE 6 -#define TEGRA194_CLK_AUD_MCLK 7 -#define TEGRA194_CLK_AXI_CBB 8 -#define TEGRA194_CLK_CAN1 9 -#define TEGRA194_CLK_CAN1_HOST 10 -#define TEGRA194_CLK_CAN2 11 -#define TEGRA194_CLK_CAN2_HOST 12 -#define TEGRA194_CLK_CEC 13 -#define TEGRA194_CLK_CLK_M 14 -#define TEGRA194_CLK_DMIC1 15 -#define TEGRA194_CLK_DMIC2 16 -#define TEGRA194_CLK_DMIC3 17 -#define TEGRA194_CLK_DMIC4 18 -#define TEGRA194_CLK_DPAUX 19 -#define TEGRA194_CLK_DPAUX1 20 -#define TEGRA194_CLK_ACLK 21 -#define TEGRA194_CLK_MSS_ENCRYPT 22 -#define TEGRA194_CLK_EQOS_RX_INPUT 23 -#define TEGRA194_CLK_IQC2 24 -#define TEGRA194_CLK_AON_APB 25 -#define TEGRA194_CLK_AON_NIC 26 -#define TEGRA194_CLK_AON_CPU_NIC 27 -#define TEGRA194_CLK_PLLA1 28 -#define TEGRA194_CLK_DSPK1 29 -#define TEGRA194_CLK_DSPK2 30 -#define TEGRA194_CLK_EMC 31 -#define TEGRA194_CLK_EQOS_AXI 32 -#define TEGRA194_CLK_EQOS_PTP_REF 33 -#define TEGRA194_CLK_EQOS_RX 34 -#define TEGRA194_CLK_EQOS_TX 35 -#define TEGRA194_CLK_EXTPERIPH1 36 -#define TEGRA194_CLK_EXTPERIPH2 37 -#define TEGRA194_CLK_EXTPERIPH3 38 -#define TEGRA194_CLK_EXTPERIPH4 39 -#define TEGRA194_CLK_FUSE 40 -#define TEGRA194_CLK_GPCCLK 41 -#define TEGRA194_CLK_GPU_PWR 42 -#define TEGRA194_CLK_HDA 43 -#define TEGRA194_CLK_HDA2CODEC_2X 44 -#define TEGRA194_CLK_HDA2HDMICODEC 45 -#define TEGRA194_CLK_HOST1X 46 -#define TEGRA194_CLK_HSIC_TRK 47 -#define TEGRA194_CLK_I2C1 48 -#define TEGRA194_CLK_I2C2 49 -#define TEGRA194_CLK_I2C3 50 -#define TEGRA194_CLK_I2C4 51 -#define TEGRA194_CLK_I2C6 52 -#define TEGRA194_CLK_I2C7 53 -#define TEGRA194_CLK_I2C8 54 -#define TEGRA194_CLK_I2C9 55 -#define TEGRA194_CLK_I2S1 56 -#define TEGRA194_CLK_I2S1_SYNC_INPUT 57 -#define TEGRA194_CLK_I2S2 58 -#define TEGRA194_CLK_I2S2_SYNC_INPUT 59 -#define TEGRA194_CLK_I2S3 60 -#define TEGRA194_CLK_I2S3_SYNC_INPUT 61 -#define TEGRA194_CLK_I2S4 62 -#define TEGRA194_CLK_I2S4_SYNC_INPUT 63 -#define TEGRA194_CLK_I2S5 64 -#define TEGRA194_CLK_I2S5_SYNC_INPUT 65 -#define TEGRA194_CLK_I2S6 66 -#define TEGRA194_CLK_I2S6_SYNC_INPUT 67 -#define TEGRA194_CLK_IQC1 68 -#define TEGRA194_CLK_ISP 69 -#define TEGRA194_CLK_KFUSE 70 -#define TEGRA194_CLK_MAUD 71 -#define TEGRA194_CLK_MIPI_CAL 72 -#define TEGRA194_CLK_MPHY_CORE_PLL_FIXED 73 -#define TEGRA194_CLK_MPHY_L0_RX_ANA 74 -#define TEGRA194_CLK_MPHY_L0_RX_LS_BIT 75 -#define TEGRA194_CLK_MPHY_L0_RX_SYMB 76 -#define TEGRA194_CLK_MPHY_L0_TX_LS_3XBIT 77 -#define TEGRA194_CLK_MPHY_L0_TX_SYMB 78 -#define TEGRA194_CLK_MPHY_L1_RX_ANA 79 -#define TEGRA194_CLK_MPHY_TX_1MHZ_REF 80 -#define TEGRA194_CLK_NVCSI 81 -#define TEGRA194_CLK_NVCSILP 82 -#define TEGRA194_CLK_NVDEC 83 -#define TEGRA194_CLK_NVDISPLAYHUB 84 -#define TEGRA194_CLK_NVDISPLAY_DISP 85 -#define TEGRA194_CLK_NVDISPLAY_P0 86 -#define TEGRA194_CLK_NVDISPLAY_P1 87 -#define TEGRA194_CLK_NVDISPLAY_P2 88 -#define TEGRA194_CLK_NVENC 89 -#define TEGRA194_CLK_NVJPG 90 -#define TEGRA194_CLK_OSC 91 -#define TEGRA194_CLK_AON_TOUCH 92 -#define TEGRA194_CLK_PLLA 93 -#define TEGRA194_CLK_PLLAON 94 -#define TEGRA194_CLK_PLLD 95 -#define TEGRA194_CLK_PLLD2 96 -#define TEGRA194_CLK_PLLD3 97 -#define TEGRA194_CLK_PLLDP 98 -#define TEGRA194_CLK_PLLD4 99 -#define TEGRA194_CLK_PLLE 100 -#define TEGRA194_CLK_PLLP 101 -#define TEGRA194_CLK_PLLP_OUT0 102 -#define TEGRA194_CLK_UTMIPLL 103 -#define TEGRA194_CLK_PLLA_OUT0 104 -#define TEGRA194_CLK_PWM1 105 -#define TEGRA194_CLK_PWM2 106 -#define TEGRA194_CLK_PWM3 107 -#define TEGRA194_CLK_PWM4 108 -#define TEGRA194_CLK_PWM5 109 -#define TEGRA194_CLK_PWM6 110 -#define TEGRA194_CLK_PWM7 111 -#define TEGRA194_CLK_PWM8 112 -#define TEGRA194_CLK_RCE_CPU_NIC 113 -#define TEGRA194_CLK_RCE_NIC 114 -#define TEGRA194_CLK_SATA 115 -#define TEGRA194_CLK_SATA_OOB 116 -#define TEGRA194_CLK_AON_I2C_SLOW 117 -#define TEGRA194_CLK_SCE_CPU_NIC 118 -#define TEGRA194_CLK_SCE_NIC 119 -#define TEGRA194_CLK_SDMMC1 120 -#define TEGRA194_CLK_UPHY_PLL3 121 -#define TEGRA194_CLK_SDMMC3 122 -#define TEGRA194_CLK_SDMMC4 123 -#define TEGRA194_CLK_SE 124 -#define TEGRA194_CLK_SOR0_OUT 125 -#define TEGRA194_CLK_SOR0_REF 126 -#define TEGRA194_CLK_SOR0_PAD_CLKOUT 127 -#define TEGRA194_CLK_SOR1_OUT 128 -#define TEGRA194_CLK_SOR1_REF 129 -#define TEGRA194_CLK_SOR1_PAD_CLKOUT 130 -#define TEGRA194_CLK_SOR_SAFE 131 -#define TEGRA194_CLK_IQC1_IN 132 -#define TEGRA194_CLK_IQC2_IN 133 -#define TEGRA194_CLK_DMIC5 134 -#define TEGRA194_CLK_SPI1 135 -#define TEGRA194_CLK_SPI2 136 -#define TEGRA194_CLK_SPI3 137 -#define TEGRA194_CLK_I2C_SLOW 138 -#define TEGRA194_CLK_SYNC_DMIC1 139 -#define TEGRA194_CLK_SYNC_DMIC2 140 -#define TEGRA194_CLK_SYNC_DMIC3 141 -#define TEGRA194_CLK_SYNC_DMIC4 142 -#define TEGRA194_CLK_SYNC_DSPK1 143 -#define TEGRA194_CLK_SYNC_DSPK2 144 -#define TEGRA194_CLK_SYNC_I2S1 145 -#define TEGRA194_CLK_SYNC_I2S2 146 -#define TEGRA194_CLK_SYNC_I2S3 147 -#define TEGRA194_CLK_SYNC_I2S4 148 -#define TEGRA194_CLK_SYNC_I2S5 149 -#define TEGRA194_CLK_SYNC_I2S6 150 -#define TEGRA194_CLK_MPHY_FORCE_LS_MODE 151 -#define TEGRA194_CLK_TACH 152 -#define TEGRA194_CLK_TSEC 153 -#define TEGRA194_CLK_TSECB 154 -#define TEGRA194_CLK_UARTA 155 -#define TEGRA194_CLK_UARTB 156 -#define TEGRA194_CLK_UARTC 157 -#define TEGRA194_CLK_UARTD 158 -#define TEGRA194_CLK_UARTE 159 -#define TEGRA194_CLK_UARTF 160 -#define TEGRA194_CLK_UARTG 161 -#define TEGRA194_CLK_UART_FST_MIPI_CAL 162 -#define TEGRA194_CLK_UFSDEV_REF 163 -#define TEGRA194_CLK_UFSHC 164 -#define TEGRA194_CLK_USB2_TRK 165 -#define TEGRA194_CLK_VI 166 -#define TEGRA194_CLK_VIC 167 -#define TEGRA194_CLK_PVA0_AXI 168 -#define TEGRA194_CLK_PVA0_VPS0 169 -#define TEGRA194_CLK_PVA0_VPS1 170 -#define TEGRA194_CLK_PVA1_AXI 171 -#define TEGRA194_CLK_PVA1_VPS0 172 -#define TEGRA194_CLK_PVA1_VPS1 173 -#define TEGRA194_CLK_DLA0_FALCON 174 -#define TEGRA194_CLK_DLA0_CORE 175 -#define TEGRA194_CLK_DLA1_FALCON 176 -#define TEGRA194_CLK_DLA1_CORE 177 -#define TEGRA194_CLK_SOR2_OUT 178 -#define TEGRA194_CLK_SOR2_REF 179 -#define TEGRA194_CLK_SOR2_PAD_CLKOUT 180 -#define TEGRA194_CLK_SOR3_OUT 181 -#define TEGRA194_CLK_SOR3_REF 182 -#define TEGRA194_CLK_SOR3_PAD_CLKOUT 183 -#define TEGRA194_CLK_NVDISPLAY_P3 184 -#define TEGRA194_CLK_DPAUX2 185 -#define TEGRA194_CLK_DPAUX3 186 -#define TEGRA194_CLK_NVDEC1 187 -#define TEGRA194_CLK_NVENC1 188 -#define TEGRA194_CLK_SE_FREE 189 -#define TEGRA194_CLK_UARTH 190 -#define TEGRA194_CLK_FUSE_SERIAL 191 -#define TEGRA194_CLK_QSPI0 192 -#define TEGRA194_CLK_QSPI1 193 -#define TEGRA194_CLK_QSPI0_PM 194 -#define TEGRA194_CLK_QSPI1_PM 195 -#define TEGRA194_CLK_VI_CONST 196 -#define TEGRA194_CLK_NAFLL_BPMP 197 -#define TEGRA194_CLK_NAFLL_SCE 198 -#define TEGRA194_CLK_NAFLL_NVDEC 199 -#define TEGRA194_CLK_NAFLL_NVJPG 200 -#define TEGRA194_CLK_NAFLL_TSEC 201 -#define TEGRA194_CLK_NAFLL_TSECB 202 -#define TEGRA194_CLK_NAFLL_VI 203 -#define TEGRA194_CLK_NAFLL_SE 204 -#define TEGRA194_CLK_NAFLL_NVENC 205 -#define TEGRA194_CLK_NAFLL_ISP 206 -#define TEGRA194_CLK_NAFLL_VIC 207 -#define TEGRA194_CLK_NAFLL_NVDISPLAYHUB 208 -#define TEGRA194_CLK_NAFLL_AXICBB 209 -#define TEGRA194_CLK_NAFLL_DLA 210 -#define TEGRA194_CLK_NAFLL_PVA_CORE 211 -#define TEGRA194_CLK_NAFLL_PVA_VPS 212 -#define TEGRA194_CLK_NAFLL_CVNAS 213 -#define TEGRA194_CLK_NAFLL_RCE 214 -#define TEGRA194_CLK_NAFLL_NVENC1 215 -#define TEGRA194_CLK_NAFLL_DLA_FALCON 216 -#define TEGRA194_CLK_NAFLL_NVDEC1 217 -#define TEGRA194_CLK_NAFLL_GPU 218 -#define TEGRA194_CLK_SDMMC_LEGACY_TM 219 -#define TEGRA194_CLK_PEX0_CORE_0 220 -#define TEGRA194_CLK_PEX0_CORE_1 221 -#define TEGRA194_CLK_PEX0_CORE_2 222 -#define TEGRA194_CLK_PEX0_CORE_3 223 -#define TEGRA194_CLK_PEX0_CORE_4 224 -#define TEGRA194_CLK_PEX1_CORE_5 225 -#define TEGRA194_CLK_PEX_REF1 226 -#define TEGRA194_CLK_PEX_REF2 227 -#define TEGRA194_CLK_CSI_A 229 -#define TEGRA194_CLK_CSI_B 230 -#define TEGRA194_CLK_CSI_C 231 -#define TEGRA194_CLK_CSI_D 232 -#define TEGRA194_CLK_CSI_E 233 -#define TEGRA194_CLK_CSI_F 234 -#define TEGRA194_CLK_CSI_G 235 -#define TEGRA194_CLK_CSI_H 236 -#define TEGRA194_CLK_PLLC4 237 -#define TEGRA194_CLK_PLLC4_OUT 238 -#define TEGRA194_CLK_PLLC4_OUT1 239 -#define TEGRA194_CLK_PLLC4_OUT2 240 -#define TEGRA194_CLK_PLLC4_MUXED 241 -#define TEGRA194_CLK_PLLC4_VCO_DIV2 242 -#define TEGRA194_CLK_CSI_A_PAD 244 -#define TEGRA194_CLK_CSI_B_PAD 245 -#define TEGRA194_CLK_CSI_C_PAD 246 -#define TEGRA194_CLK_CSI_D_PAD 247 -#define TEGRA194_CLK_CSI_E_PAD 248 -#define TEGRA194_CLK_CSI_F_PAD 249 -#define TEGRA194_CLK_CSI_G_PAD 250 -#define TEGRA194_CLK_CSI_H_PAD 251 -#define TEGRA194_CLK_PEX_SATA_USB_RX_BYP 254 -#define TEGRA194_CLK_PEX_USB_PAD_PLL0_MGMT 255 -#define TEGRA194_CLK_PEX_USB_PAD_PLL1_MGMT 256 -#define TEGRA194_CLK_PEX_USB_PAD_PLL2_MGMT 257 -#define TEGRA194_CLK_PEX_USB_PAD_PLL3_MGMT 258 -#define TEGRA194_CLK_XUSB_CORE_DEV 265 -#define TEGRA194_CLK_XUSB_CORE_MUX 266 -#define TEGRA194_CLK_XUSB_CORE_HOST 267 -#define TEGRA194_CLK_XUSB_CORE_SS 268 -#define TEGRA194_CLK_XUSB_FALCON 269 -#define TEGRA194_CLK_XUSB_FALCON_HOST 270 -#define TEGRA194_CLK_XUSB_FALCON_SS 271 -#define TEGRA194_CLK_XUSB_FS 272 -#define TEGRA194_CLK_XUSB_FS_HOST 273 -#define TEGRA194_CLK_XUSB_FS_DEV 274 -#define TEGRA194_CLK_XUSB_SS 275 -#define TEGRA194_CLK_XUSB_SS_DEV 276 -#define TEGRA194_CLK_XUSB_SS_SUPERSPEED 277 -#define TEGRA194_CLK_PLLDISPHUB 278 -#define TEGRA194_CLK_PLLDISPHUB_DIV 279 -#define TEGRA194_CLK_NAFLL_CLUSTER0 280 -#define TEGRA194_CLK_NAFLL_CLUSTER1 281 -#define TEGRA194_CLK_NAFLL_CLUSTER2 282 -#define TEGRA194_CLK_NAFLL_CLUSTER3 283 -#define TEGRA194_CLK_CAN1_CORE 284 -#define TEGRA194_CLK_CAN2_CORE 285 -#define TEGRA194_CLK_PLLA1_OUT1 286 -#define TEGRA194_CLK_PLLREFE_VCOOUT 288 -#define TEGRA194_CLK_CLK_32K 289 -#define TEGRA194_CLK_SPDIFIN_SYNC_INPUT 290 -#define TEGRA194_CLK_UTMIPLL_CLKOUT48 291 -#define TEGRA194_CLK_UTMIPLL_CLKOUT480 292 -#define TEGRA194_CLK_CVNAS 293 -#define TEGRA194_CLK_PLLNVCSI 294 -#define TEGRA194_CLK_PVA0_CPU_AXI 295 -#define TEGRA194_CLK_PVA1_CPU_AXI 296 -#define TEGRA194_CLK_PVA0_VPS 297 -#define TEGRA194_CLK_PVA1_VPS 298 -#define TEGRA194_CLK_DLA0_FALCON_MUX 299 -#define TEGRA194_CLK_DLA1_FALCON_MUX 300 -#define TEGRA194_CLK_DLA0_CORE_MUX 301 -#define TEGRA194_CLK_DLA1_CORE_MUX 302 -#define TEGRA194_CLK_UTMIPLL_HPS 304 -#define TEGRA194_CLK_I2C5 305 -#define TEGRA194_CLK_I2C10 306 -#define TEGRA194_CLK_BPMP_CPU_NIC 307 -#define TEGRA194_CLK_BPMP_APB 308 -#define TEGRA194_CLK_TSC 309 -#define TEGRA194_CLK_EMCSA 310 -#define TEGRA194_CLK_EMCSB 311 -#define TEGRA194_CLK_EMCSC 312 -#define TEGRA194_CLK_EMCSD 313 -#define TEGRA194_CLK_PLLC 314 -#define TEGRA194_CLK_PLLC2 315 -#define TEGRA194_CLK_PLLC3 316 -#define TEGRA194_CLK_TSC_REF 317 -#define TEGRA194_CLK_FUSE_BURN 318 -#define TEGRA194_CLK_PEX0_CORE_0M 319 -#define TEGRA194_CLK_PEX0_CORE_1M 320 -#define TEGRA194_CLK_PEX0_CORE_2M 321 -#define TEGRA194_CLK_PEX0_CORE_3M 322 -#define TEGRA194_CLK_PEX0_CORE_4M 323 -#define TEGRA194_CLK_PEX1_CORE_5M 324 -#define TEGRA194_CLK_PLLE_HPS 326 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/tegra20-car.h b/sys/gnu/dts/include/dt-bindings/clock/tegra20-car.h deleted file mode 100644 index b21a0eb3292..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/tegra20-car.h +++ /dev/null @@ -1,159 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides constants for binding nvidia,tegra20-car. - * - * The first 96 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB - * registers. These IDs often match those in the CAR's RST_DEVICES registers, - * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In - * this case, those clocks are assigned IDs above 95 in order to highlight - * this issue. Implementations that interpret these clock IDs as bit values - * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to - * explicitly handle these special cases. - * - * The balance of the clocks controlled by the CAR are assigned IDs of 96 and - * above. - */ - -#ifndef _DT_BINDINGS_CLOCK_TEGRA20_CAR_H -#define _DT_BINDINGS_CLOCK_TEGRA20_CAR_H - -#define TEGRA20_CLK_CPU 0 -/* 1 */ -/* 2 */ -#define TEGRA20_CLK_AC97 3 -#define TEGRA20_CLK_RTC 4 -#define TEGRA20_CLK_TIMER 5 -#define TEGRA20_CLK_UARTA 6 -/* 7 (register bit affects uart2 and vfir) */ -#define TEGRA20_CLK_GPIO 8 -#define TEGRA20_CLK_SDMMC2 9 -/* 10 (register bit affects spdif_in and spdif_out) */ -#define TEGRA20_CLK_I2S1 11 -#define TEGRA20_CLK_I2C1 12 -#define TEGRA20_CLK_NDFLASH 13 -#define TEGRA20_CLK_SDMMC1 14 -#define TEGRA20_CLK_SDMMC4 15 -#define TEGRA20_CLK_TWC 16 -#define TEGRA20_CLK_PWM 17 -#define TEGRA20_CLK_I2S2 18 -#define TEGRA20_CLK_EPP 19 -/* 20 (register bit affects vi and vi_sensor) */ -#define TEGRA20_CLK_GR2D 21 -#define TEGRA20_CLK_USBD 22 -#define TEGRA20_CLK_ISP 23 -#define TEGRA20_CLK_GR3D 24 -#define TEGRA20_CLK_IDE 25 -#define TEGRA20_CLK_DISP2 26 -#define TEGRA20_CLK_DISP1 27 -#define TEGRA20_CLK_HOST1X 28 -#define TEGRA20_CLK_VCP 29 -/* 30 */ -#define TEGRA20_CLK_CACHE2 31 - -#define TEGRA20_CLK_MC 32 -#define TEGRA20_CLK_AHBDMA 33 -#define TEGRA20_CLK_APBDMA 34 -/* 35 */ -#define TEGRA20_CLK_KBC 36 -#define TEGRA20_CLK_STAT_MON 37 -#define TEGRA20_CLK_PMC 38 -#define TEGRA20_CLK_FUSE 39 -#define TEGRA20_CLK_KFUSE 40 -#define TEGRA20_CLK_SBC1 41 -#define TEGRA20_CLK_NOR 42 -#define TEGRA20_CLK_SPI 43 -#define TEGRA20_CLK_SBC2 44 -#define TEGRA20_CLK_XIO 45 -#define TEGRA20_CLK_SBC3 46 -#define TEGRA20_CLK_DVC 47 -#define TEGRA20_CLK_DSI 48 -/* 49 (register bit affects tvo and cve) */ -#define TEGRA20_CLK_MIPI 50 -#define TEGRA20_CLK_HDMI 51 -#define TEGRA20_CLK_CSI 52 -#define TEGRA20_CLK_TVDAC 53 -#define TEGRA20_CLK_I2C2 54 -#define TEGRA20_CLK_UARTC 55 -/* 56 */ -#define TEGRA20_CLK_EMC 57 -#define TEGRA20_CLK_USB2 58 -#define TEGRA20_CLK_USB3 59 -#define TEGRA20_CLK_MPE 60 -#define TEGRA20_CLK_VDE 61 -#define TEGRA20_CLK_BSEA 62 -#define TEGRA20_CLK_BSEV 63 - -#define TEGRA20_CLK_SPEEDO 64 -#define TEGRA20_CLK_UARTD 65 -#define TEGRA20_CLK_UARTE 66 -#define TEGRA20_CLK_I2C3 67 -#define TEGRA20_CLK_SBC4 68 -#define TEGRA20_CLK_SDMMC3 69 -#define TEGRA20_CLK_PEX 70 -#define TEGRA20_CLK_OWR 71 -#define TEGRA20_CLK_AFI 72 -#define TEGRA20_CLK_CSITE 73 -/* 74 */ -#define TEGRA20_CLK_AVPUCQ 75 -#define TEGRA20_CLK_LA 76 -/* 77 */ -/* 78 */ -/* 79 */ -/* 80 */ -/* 81 */ -/* 82 */ -/* 83 */ -#define TEGRA20_CLK_IRAMA 84 -#define TEGRA20_CLK_IRAMB 85 -#define TEGRA20_CLK_IRAMC 86 -#define TEGRA20_CLK_IRAMD 87 -#define TEGRA20_CLK_CRAM2 88 -#define TEGRA20_CLK_AUDIO_2X 89 /* a/k/a audio_2x_sync_clk */ -#define TEGRA20_CLK_CLK_D 90 -/* 91 */ -#define TEGRA20_CLK_CSUS 92 -#define TEGRA20_CLK_CDEV2 93 -#define TEGRA20_CLK_CDEV1 94 -/* 95 */ - -#define TEGRA20_CLK_UARTB 96 -#define TEGRA20_CLK_VFIR 97 -#define TEGRA20_CLK_SPDIF_IN 98 -#define TEGRA20_CLK_SPDIF_OUT 99 -#define TEGRA20_CLK_VI 100 -#define TEGRA20_CLK_VI_SENSOR 101 -#define TEGRA20_CLK_TVO 102 -#define TEGRA20_CLK_CVE 103 -#define TEGRA20_CLK_OSC 104 -#define TEGRA20_CLK_CLK_32K 105 /* a/k/a clk_s */ -#define TEGRA20_CLK_CLK_M 106 -#define TEGRA20_CLK_SCLK 107 -#define TEGRA20_CLK_CCLK 108 -#define TEGRA20_CLK_HCLK 109 -#define TEGRA20_CLK_PCLK 110 -#define TEGRA20_CLK_BLINK 111 -#define TEGRA20_CLK_PLL_A 112 -#define TEGRA20_CLK_PLL_A_OUT0 113 -#define TEGRA20_CLK_PLL_C 114 -#define TEGRA20_CLK_PLL_C_OUT1 115 -#define TEGRA20_CLK_PLL_D 116 -#define TEGRA20_CLK_PLL_D_OUT0 117 -#define TEGRA20_CLK_PLL_E 118 -#define TEGRA20_CLK_PLL_M 119 -#define TEGRA20_CLK_PLL_M_OUT1 120 -#define TEGRA20_CLK_PLL_P 121 -#define TEGRA20_CLK_PLL_P_OUT1 122 -#define TEGRA20_CLK_PLL_P_OUT2 123 -#define TEGRA20_CLK_PLL_P_OUT3 124 -#define TEGRA20_CLK_PLL_P_OUT4 125 -#define TEGRA20_CLK_PLL_S 126 -#define TEGRA20_CLK_PLL_U 127 - -#define TEGRA20_CLK_PLL_X 128 -#define TEGRA20_CLK_COP 129 /* a/k/a avp */ -#define TEGRA20_CLK_AUDIO 130 /* a/k/a audio_sync_clk */ -#define TEGRA20_CLK_PLL_REF 131 -#define TEGRA20_CLK_TWD 132 -#define TEGRA20_CLK_CLK_MAX 133 - -#endif /* _DT_BINDINGS_CLOCK_TEGRA20_CAR_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/tegra210-car.h b/sys/gnu/dts/include/dt-bindings/clock/tegra210-car.h deleted file mode 100644 index 44f60623f99..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/tegra210-car.h +++ /dev/null @@ -1,412 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides constants for binding nvidia,tegra210-car. - * - * The first 224 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB - * registers. These IDs often match those in the CAR's RST_DEVICES registers, - * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In - * this case, those clocks are assigned IDs above 224 in order to highlight - * this issue. Implementations that interpret these clock IDs as bit values - * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to - * explicitly handle these special cases. - * - * The balance of the clocks controlled by the CAR are assigned IDs of 224 and - * above. - */ - -#ifndef _DT_BINDINGS_CLOCK_TEGRA210_CAR_H -#define _DT_BINDINGS_CLOCK_TEGRA210_CAR_H - -/* 0 */ -/* 1 */ -/* 2 */ -#define TEGRA210_CLK_ISPB 3 -#define TEGRA210_CLK_RTC 4 -#define TEGRA210_CLK_TIMER 5 -#define TEGRA210_CLK_UARTA 6 -/* 7 (register bit affects uartb and vfir) */ -#define TEGRA210_CLK_GPIO 8 -#define TEGRA210_CLK_SDMMC2 9 -/* 10 (register bit affects spdif_in and spdif_out) */ -#define TEGRA210_CLK_I2S1 11 -#define TEGRA210_CLK_I2C1 12 -/* 13 */ -#define TEGRA210_CLK_SDMMC1 14 -#define TEGRA210_CLK_SDMMC4 15 -/* 16 */ -#define TEGRA210_CLK_PWM 17 -#define TEGRA210_CLK_I2S2 18 -/* 19 */ -/* 20 (register bit affects vi and vi_sensor) */ -/* 21 */ -#define TEGRA210_CLK_USBD 22 -#define TEGRA210_CLK_ISPA 23 -/* 24 */ -/* 25 */ -#define TEGRA210_CLK_DISP2 26 -#define TEGRA210_CLK_DISP1 27 -#define TEGRA210_CLK_HOST1X 28 -/* 29 */ -#define TEGRA210_CLK_I2S0 30 -/* 31 */ - -#define TEGRA210_CLK_MC 32 -#define TEGRA210_CLK_AHBDMA 33 -#define TEGRA210_CLK_APBDMA 34 -/* 35 */ -/* 36 */ -/* 37 */ -#define TEGRA210_CLK_PMC 38 -/* 39 (register bit affects fuse and fuse_burn) */ -#define TEGRA210_CLK_KFUSE 40 -#define TEGRA210_CLK_SBC1 41 -/* 42 */ -/* 43 */ -#define TEGRA210_CLK_SBC2 44 -/* 45 */ -#define TEGRA210_CLK_SBC3 46 -#define TEGRA210_CLK_I2C5 47 -#define TEGRA210_CLK_DSIA 48 -/* 49 */ -/* 50 */ -/* 51 */ -#define TEGRA210_CLK_CSI 52 -/* 53 */ -#define TEGRA210_CLK_I2C2 54 -#define TEGRA210_CLK_UARTC 55 -#define TEGRA210_CLK_MIPI_CAL 56 -#define TEGRA210_CLK_EMC 57 -#define TEGRA210_CLK_USB2 58 -/* 59 */ -/* 60 */ -/* 61 */ -/* 62 */ -#define TEGRA210_CLK_BSEV 63 - -/* 64 */ -#define TEGRA210_CLK_UARTD 65 -/* 66 */ -#define TEGRA210_CLK_I2C3 67 -#define TEGRA210_CLK_SBC4 68 -#define TEGRA210_CLK_SDMMC3 69 -#define TEGRA210_CLK_PCIE 70 -#define TEGRA210_CLK_OWR 71 -#define TEGRA210_CLK_AFI 72 -#define TEGRA210_CLK_CSITE 73 -/* 74 */ -/* 75 */ -#define TEGRA210_CLK_LA 76 -/* 77 */ -#define TEGRA210_CLK_SOC_THERM 78 -#define TEGRA210_CLK_DTV 79 -/* 80 */ -#define TEGRA210_CLK_I2CSLOW 81 -#define TEGRA210_CLK_DSIB 82 -#define TEGRA210_CLK_TSEC 83 -/* 84 */ -/* 85 */ -/* 86 */ -/* 87 */ -/* 88 */ -#define TEGRA210_CLK_XUSB_HOST 89 -/* 90 */ -/* 91 */ -#define TEGRA210_CLK_CSUS 92 -/* 93 */ -/* 94 */ -/* 95 (bit affects xusb_dev and xusb_dev_src) */ - -/* 96 */ -/* 97 */ -/* 98 */ -#define TEGRA210_CLK_MSELECT 99 -#define TEGRA210_CLK_TSENSOR 100 -#define TEGRA210_CLK_I2S3 101 -#define TEGRA210_CLK_I2S4 102 -#define TEGRA210_CLK_I2C4 103 -/* 104 */ -/* 105 */ -#define TEGRA210_CLK_D_AUDIO 106 -#define TEGRA210_CLK_APB2APE 107 -/* 108 */ -/* 109 */ -/* 110 */ -#define TEGRA210_CLK_HDA2CODEC_2X 111 -/* 112 */ -/* 113 */ -/* 114 */ -/* 115 */ -/* 116 */ -/* 117 */ -#define TEGRA210_CLK_SPDIF_2X 118 -#define TEGRA210_CLK_ACTMON 119 -#define TEGRA210_CLK_EXTERN1 120 -#define TEGRA210_CLK_EXTERN2 121 -#define TEGRA210_CLK_EXTERN3 122 -#define TEGRA210_CLK_SATA_OOB 123 -#define TEGRA210_CLK_SATA 124 -#define TEGRA210_CLK_HDA 125 -/* 126 */ -/* 127 */ - -#define TEGRA210_CLK_HDA2HDMI 128 -/* 129 */ -/* 130 */ -/* 131 */ -/* 132 */ -/* 133 */ -/* 134 */ -/* 135 */ -#define TEGRA210_CLK_CEC 136 -/* 137 */ -/* 138 */ -/* 139 */ -/* 140 */ -/* 141 */ -/* 142 */ -/* (bit affects xusb_falcon_src, xusb_fs_src, xusb_host_src and xusb_ss_src) */ -#define TEGRA210_CLK_XUSB_GATE 143 -#define TEGRA210_CLK_CILAB 144 -#define TEGRA210_CLK_CILCD 145 -#define TEGRA210_CLK_CILE 146 -#define TEGRA210_CLK_DSIALP 147 -#define TEGRA210_CLK_DSIBLP 148 -#define TEGRA210_CLK_ENTROPY 149 -/* 150 */ -/* 151 */ -#define TEGRA210_CLK_DP2 152 -/* 153 */ -/* 154 */ -/* 155 (bit affects dfll_ref and dfll_soc) */ -#define TEGRA210_CLK_XUSB_SS 156 -/* 157 */ -/* 158 */ -/* 159 */ - -/* 160 */ -#define TEGRA210_CLK_DMIC1 161 -#define TEGRA210_CLK_DMIC2 162 -/* 163 */ -/* 164 */ -/* 165 */ -#define TEGRA210_CLK_I2C6 166 -/* 167 */ -/* 168 */ -/* 169 */ -/* 170 */ -#define TEGRA210_CLK_VIM2_CLK 171 -/* 172 */ -#define TEGRA210_CLK_MIPIBIF 173 -/* 174 */ -/* 175 */ -/* 176 */ -#define TEGRA210_CLK_CLK72MHZ 177 -#define TEGRA210_CLK_VIC03 178 -/* 179 */ -/* 180 */ -#define TEGRA210_CLK_DPAUX 181 -#define TEGRA210_CLK_SOR0 182 -#define TEGRA210_CLK_SOR1 183 -#define TEGRA210_CLK_GPU 184 -#define TEGRA210_CLK_DBGAPB 185 -/* 186 */ -#define TEGRA210_CLK_PLL_P_OUT_ADSP 187 -/* 188 ((bit affects pll_a_out_adsp and pll_a_out0_out_adsp)*/ -#define TEGRA210_CLK_PLL_G_REF 189 -/* 190 */ -/* 191 */ - -/* 192 */ -#define TEGRA210_CLK_SDMMC_LEGACY 193 -#define TEGRA210_CLK_NVDEC 194 -#define TEGRA210_CLK_NVJPG 195 -/* 196 */ -#define TEGRA210_CLK_DMIC3 197 -#define TEGRA210_CLK_APE 198 -#define TEGRA210_CLK_ADSP 199 -/* 200 */ -/* 201 */ -#define TEGRA210_CLK_MAUD 202 -/* 203 */ -/* 204 */ -/* 205 */ -#define TEGRA210_CLK_TSECB 206 -#define TEGRA210_CLK_DPAUX1 207 -#define TEGRA210_CLK_VI_I2C 208 -#define TEGRA210_CLK_HSIC_TRK 209 -#define TEGRA210_CLK_USB2_TRK 210 -#define TEGRA210_CLK_QSPI 211 -#define TEGRA210_CLK_UARTAPE 212 -/* 213 */ -/* 214 */ -/* 215 */ -/* 216 */ -/* 217 */ -#define TEGRA210_CLK_ADSP_NEON 218 -#define TEGRA210_CLK_NVENC 219 -#define TEGRA210_CLK_IQC2 220 -#define TEGRA210_CLK_IQC1 221 -#define TEGRA210_CLK_SOR_SAFE 222 -#define TEGRA210_CLK_PLL_P_OUT_CPU 223 - - -#define TEGRA210_CLK_UARTB 224 -#define TEGRA210_CLK_VFIR 225 -#define TEGRA210_CLK_SPDIF_IN 226 -#define TEGRA210_CLK_SPDIF_OUT 227 -#define TEGRA210_CLK_VI 228 -#define TEGRA210_CLK_VI_SENSOR 229 -#define TEGRA210_CLK_FUSE 230 -#define TEGRA210_CLK_FUSE_BURN 231 -#define TEGRA210_CLK_CLK_32K 232 -#define TEGRA210_CLK_CLK_M 233 -#define TEGRA210_CLK_CLK_M_DIV2 234 -#define TEGRA210_CLK_CLK_M_DIV4 235 -#define TEGRA210_CLK_PLL_REF 236 -#define TEGRA210_CLK_PLL_C 237 -#define TEGRA210_CLK_PLL_C_OUT1 238 -#define TEGRA210_CLK_PLL_C2 239 -#define TEGRA210_CLK_PLL_C3 240 -#define TEGRA210_CLK_PLL_M 241 -#define TEGRA210_CLK_PLL_M_OUT1 242 -#define TEGRA210_CLK_PLL_P 243 -#define TEGRA210_CLK_PLL_P_OUT1 244 -#define TEGRA210_CLK_PLL_P_OUT2 245 -#define TEGRA210_CLK_PLL_P_OUT3 246 -#define TEGRA210_CLK_PLL_P_OUT4 247 -#define TEGRA210_CLK_PLL_A 248 -#define TEGRA210_CLK_PLL_A_OUT0 249 -#define TEGRA210_CLK_PLL_D 250 -#define TEGRA210_CLK_PLL_D_OUT0 251 -#define TEGRA210_CLK_PLL_D2 252 -#define TEGRA210_CLK_PLL_D2_OUT0 253 -#define TEGRA210_CLK_PLL_U 254 -#define TEGRA210_CLK_PLL_U_480M 255 - -#define TEGRA210_CLK_PLL_U_60M 256 -#define TEGRA210_CLK_PLL_U_48M 257 -/* 258 */ -#define TEGRA210_CLK_PLL_X 259 -#define TEGRA210_CLK_PLL_X_OUT0 260 -#define TEGRA210_CLK_PLL_RE_VCO 261 -#define TEGRA210_CLK_PLL_RE_OUT 262 -#define TEGRA210_CLK_PLL_E 263 -#define TEGRA210_CLK_SPDIF_IN_SYNC 264 -#define TEGRA210_CLK_I2S0_SYNC 265 -#define TEGRA210_CLK_I2S1_SYNC 266 -#define TEGRA210_CLK_I2S2_SYNC 267 -#define TEGRA210_CLK_I2S3_SYNC 268 -#define TEGRA210_CLK_I2S4_SYNC 269 -#define TEGRA210_CLK_VIMCLK_SYNC 270 -#define TEGRA210_CLK_AUDIO0 271 -#define TEGRA210_CLK_AUDIO1 272 -#define TEGRA210_CLK_AUDIO2 273 -#define TEGRA210_CLK_AUDIO3 274 -#define TEGRA210_CLK_AUDIO4 275 -#define TEGRA210_CLK_SPDIF 276 -#define TEGRA210_CLK_CLK_OUT_1 277 -#define TEGRA210_CLK_CLK_OUT_2 278 -#define TEGRA210_CLK_CLK_OUT_3 279 -#define TEGRA210_CLK_BLINK 280 -#define TEGRA210_CLK_SOR0_LVDS 281 /* deprecated */ -#define TEGRA210_CLK_SOR0_OUT 281 -#define TEGRA210_CLK_SOR1_OUT 282 -/* 283 */ -#define TEGRA210_CLK_XUSB_HOST_SRC 284 -#define TEGRA210_CLK_XUSB_FALCON_SRC 285 -#define TEGRA210_CLK_XUSB_FS_SRC 286 -#define TEGRA210_CLK_XUSB_SS_SRC 287 - -#define TEGRA210_CLK_XUSB_DEV_SRC 288 -#define TEGRA210_CLK_XUSB_DEV 289 -#define TEGRA210_CLK_XUSB_HS_SRC 290 -#define TEGRA210_CLK_SCLK 291 -#define TEGRA210_CLK_HCLK 292 -#define TEGRA210_CLK_PCLK 293 -#define TEGRA210_CLK_CCLK_G 294 -#define TEGRA210_CLK_CCLK_LP 295 -#define TEGRA210_CLK_DFLL_REF 296 -#define TEGRA210_CLK_DFLL_SOC 297 -#define TEGRA210_CLK_VI_SENSOR2 298 -#define TEGRA210_CLK_PLL_P_OUT5 299 -#define TEGRA210_CLK_CML0 300 -#define TEGRA210_CLK_CML1 301 -#define TEGRA210_CLK_PLL_C4 302 -#define TEGRA210_CLK_PLL_DP 303 -#define TEGRA210_CLK_PLL_E_MUX 304 -#define TEGRA210_CLK_PLL_MB 305 -#define TEGRA210_CLK_PLL_A1 306 -#define TEGRA210_CLK_PLL_D_DSI_OUT 307 -#define TEGRA210_CLK_PLL_C4_OUT0 308 -#define TEGRA210_CLK_PLL_C4_OUT1 309 -#define TEGRA210_CLK_PLL_C4_OUT2 310 -#define TEGRA210_CLK_PLL_C4_OUT3 311 -#define TEGRA210_CLK_PLL_U_OUT 312 -#define TEGRA210_CLK_PLL_U_OUT1 313 -#define TEGRA210_CLK_PLL_U_OUT2 314 -#define TEGRA210_CLK_USB2_HSIC_TRK 315 -#define TEGRA210_CLK_PLL_P_OUT_HSIO 316 -#define TEGRA210_CLK_PLL_P_OUT_XUSB 317 -#define TEGRA210_CLK_XUSB_SSP_SRC 318 -#define TEGRA210_CLK_PLL_RE_OUT1 319 -/* 320 */ -/* 321 */ -#define TEGRA210_CLK_ISP 322 -#define TEGRA210_CLK_PLL_A_OUT_ADSP 323 -#define TEGRA210_CLK_PLL_A_OUT0_OUT_ADSP 324 -/* 325 */ -/* 326 */ -/* 327 */ -/* 328 */ -/* 329 */ -/* 330 */ -/* 331 */ -/* 332 */ -/* 333 */ -/* 334 */ -/* 335 */ -/* 336 */ -/* 337 */ -/* 338 */ -/* 339 */ -/* 340 */ -/* 341 */ -/* 342 */ -/* 343 */ -/* 344 */ -/* 345 */ -/* 346 */ -/* 347 */ -/* 348 */ -/* 349 */ - -#define TEGRA210_CLK_AUDIO0_MUX 350 -#define TEGRA210_CLK_AUDIO1_MUX 351 -#define TEGRA210_CLK_AUDIO2_MUX 352 -#define TEGRA210_CLK_AUDIO3_MUX 353 -#define TEGRA210_CLK_AUDIO4_MUX 354 -#define TEGRA210_CLK_SPDIF_MUX 355 -#define TEGRA210_CLK_CLK_OUT_1_MUX 356 -#define TEGRA210_CLK_CLK_OUT_2_MUX 357 -#define TEGRA210_CLK_CLK_OUT_3_MUX 358 -#define TEGRA210_CLK_DSIA_MUX 359 -#define TEGRA210_CLK_DSIB_MUX 360 -/* 361 */ -#define TEGRA210_CLK_XUSB_SS_DIV2 362 - -#define TEGRA210_CLK_PLL_M_UD 363 -#define TEGRA210_CLK_PLL_C_UD 364 -#define TEGRA210_CLK_SCLK_MUX 365 - -#define TEGRA210_CLK_ACLK 370 - -#define TEGRA210_CLK_DMIC1_SYNC_CLK 388 -#define TEGRA210_CLK_DMIC1_SYNC_CLK_MUX 389 -#define TEGRA210_CLK_DMIC2_SYNC_CLK 390 -#define TEGRA210_CLK_DMIC2_SYNC_CLK_MUX 391 -#define TEGRA210_CLK_DMIC3_SYNC_CLK 392 -#define TEGRA210_CLK_DMIC3_SYNC_CLK_MUX 393 - -#define TEGRA210_CLK_CLK_MAX 394 - -#endif /* _DT_BINDINGS_CLOCK_TEGRA210_CAR_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/tegra30-car.h b/sys/gnu/dts/include/dt-bindings/clock/tegra30-car.h deleted file mode 100644 index 3c90f153555..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/tegra30-car.h +++ /dev/null @@ -1,274 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides constants for binding nvidia,tegra30-car. - * - * The first 130 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB - * registers. These IDs often match those in the CAR's RST_DEVICES registers, - * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In - * this case, those clocks are assigned IDs above 160 in order to highlight - * this issue. Implementations that interpret these clock IDs as bit values - * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to - * explicitly handle these special cases. - * - * The balance of the clocks controlled by the CAR are assigned IDs of 160 and - * above. - */ - -#ifndef _DT_BINDINGS_CLOCK_TEGRA30_CAR_H -#define _DT_BINDINGS_CLOCK_TEGRA30_CAR_H - -#define TEGRA30_CLK_CPU 0 -/* 1 */ -/* 2 */ -/* 3 */ -#define TEGRA30_CLK_RTC 4 -#define TEGRA30_CLK_TIMER 5 -#define TEGRA30_CLK_UARTA 6 -/* 7 (register bit affects uartb and vfir) */ -#define TEGRA30_CLK_GPIO 8 -#define TEGRA30_CLK_SDMMC2 9 -/* 10 (register bit affects spdif_in and spdif_out) */ -#define TEGRA30_CLK_I2S1 11 -#define TEGRA30_CLK_I2C1 12 -#define TEGRA30_CLK_NDFLASH 13 -#define TEGRA30_CLK_SDMMC1 14 -#define TEGRA30_CLK_SDMMC4 15 -/* 16 */ -#define TEGRA30_CLK_PWM 17 -#define TEGRA30_CLK_I2S2 18 -#define TEGRA30_CLK_EPP 19 -/* 20 (register bit affects vi and vi_sensor) */ -#define TEGRA30_CLK_GR2D 21 -#define TEGRA30_CLK_USBD 22 -#define TEGRA30_CLK_ISP 23 -#define TEGRA30_CLK_GR3D 24 -/* 25 */ -#define TEGRA30_CLK_DISP2 26 -#define TEGRA30_CLK_DISP1 27 -#define TEGRA30_CLK_HOST1X 28 -#define TEGRA30_CLK_VCP 29 -#define TEGRA30_CLK_I2S0 30 -#define TEGRA30_CLK_COP_CACHE 31 - -#define TEGRA30_CLK_MC 32 -#define TEGRA30_CLK_AHBDMA 33 -#define TEGRA30_CLK_APBDMA 34 -/* 35 */ -#define TEGRA30_CLK_KBC 36 -#define TEGRA30_CLK_STATMON 37 -#define TEGRA30_CLK_PMC 38 -/* 39 (register bit affects fuse and fuse_burn) */ -#define TEGRA30_CLK_KFUSE 40 -#define TEGRA30_CLK_SBC1 41 -#define TEGRA30_CLK_NOR 42 -/* 43 */ -#define TEGRA30_CLK_SBC2 44 -/* 45 */ -#define TEGRA30_CLK_SBC3 46 -#define TEGRA30_CLK_I2C5 47 -#define TEGRA30_CLK_DSIA 48 -/* 49 (register bit affects cve and tvo) */ -#define TEGRA30_CLK_MIPI 50 -#define TEGRA30_CLK_HDMI 51 -#define TEGRA30_CLK_CSI 52 -#define TEGRA30_CLK_TVDAC 53 -#define TEGRA30_CLK_I2C2 54 -#define TEGRA30_CLK_UARTC 55 -/* 56 */ -#define TEGRA30_CLK_EMC 57 -#define TEGRA30_CLK_USB2 58 -#define TEGRA30_CLK_USB3 59 -#define TEGRA30_CLK_MPE 60 -#define TEGRA30_CLK_VDE 61 -#define TEGRA30_CLK_BSEA 62 -#define TEGRA30_CLK_BSEV 63 - -#define TEGRA30_CLK_SPEEDO 64 -#define TEGRA30_CLK_UARTD 65 -#define TEGRA30_CLK_UARTE 66 -#define TEGRA30_CLK_I2C3 67 -#define TEGRA30_CLK_SBC4 68 -#define TEGRA30_CLK_SDMMC3 69 -#define TEGRA30_CLK_PCIE 70 -#define TEGRA30_CLK_OWR 71 -#define TEGRA30_CLK_AFI 72 -#define TEGRA30_CLK_CSITE 73 -/* 74 */ -#define TEGRA30_CLK_AVPUCQ 75 -#define TEGRA30_CLK_LA 76 -/* 77 */ -/* 78 */ -#define TEGRA30_CLK_DTV 79 -#define TEGRA30_CLK_NDSPEED 80 -#define TEGRA30_CLK_I2CSLOW 81 -#define TEGRA30_CLK_DSIB 82 -/* 83 */ -#define TEGRA30_CLK_IRAMA 84 -#define TEGRA30_CLK_IRAMB 85 -#define TEGRA30_CLK_IRAMC 86 -#define TEGRA30_CLK_IRAMD 87 -#define TEGRA30_CLK_CRAM2 88 -/* 89 */ -#define TEGRA30_CLK_AUDIO_2X 90 /* a/k/a audio_2x_sync_clk */ -/* 91 */ -#define TEGRA30_CLK_CSUS 92 -#define TEGRA30_CLK_CDEV2 93 -#define TEGRA30_CLK_CDEV1 94 -/* 95 */ - -#define TEGRA30_CLK_CPU_G 96 -#define TEGRA30_CLK_CPU_LP 97 -#define TEGRA30_CLK_GR3D2 98 -#define TEGRA30_CLK_MSELECT 99 -#define TEGRA30_CLK_TSENSOR 100 -#define TEGRA30_CLK_I2S3 101 -#define TEGRA30_CLK_I2S4 102 -#define TEGRA30_CLK_I2C4 103 -#define TEGRA30_CLK_SBC5 104 -#define TEGRA30_CLK_SBC6 105 -#define TEGRA30_CLK_D_AUDIO 106 -#define TEGRA30_CLK_APBIF 107 -#define TEGRA30_CLK_DAM0 108 -#define TEGRA30_CLK_DAM1 109 -#define TEGRA30_CLK_DAM2 110 -#define TEGRA30_CLK_HDA2CODEC_2X 111 -#define TEGRA30_CLK_ATOMICS 112 -#define TEGRA30_CLK_AUDIO0_2X 113 -#define TEGRA30_CLK_AUDIO1_2X 114 -#define TEGRA30_CLK_AUDIO2_2X 115 -#define TEGRA30_CLK_AUDIO3_2X 116 -#define TEGRA30_CLK_AUDIO4_2X 117 -#define TEGRA30_CLK_SPDIF_2X 118 -#define TEGRA30_CLK_ACTMON 119 -#define TEGRA30_CLK_EXTERN1 120 -#define TEGRA30_CLK_EXTERN2 121 -#define TEGRA30_CLK_EXTERN3 122 -#define TEGRA30_CLK_SATA_OOB 123 -#define TEGRA30_CLK_SATA 124 -#define TEGRA30_CLK_HDA 125 -/* 126 */ -#define TEGRA30_CLK_SE 127 - -#define TEGRA30_CLK_HDA2HDMI 128 -#define TEGRA30_CLK_SATA_COLD 129 -/* 130 */ -/* 131 */ -/* 132 */ -/* 133 */ -/* 134 */ -/* 135 */ -#define TEGRA30_CLK_CEC 136 -/* 137 */ -/* 138 */ -/* 139 */ -/* 140 */ -/* 141 */ -/* 142 */ -/* 143 */ -/* 144 */ -/* 145 */ -/* 146 */ -/* 147 */ -/* 148 */ -/* 149 */ -/* 150 */ -/* 151 */ -/* 152 */ -/* 153 */ -/* 154 */ -/* 155 */ -/* 156 */ -/* 157 */ -/* 158 */ -/* 159 */ - -#define TEGRA30_CLK_UARTB 160 -#define TEGRA30_CLK_VFIR 161 -#define TEGRA30_CLK_SPDIF_IN 162 -#define TEGRA30_CLK_SPDIF_OUT 163 -#define TEGRA30_CLK_VI 164 -#define TEGRA30_CLK_VI_SENSOR 165 -#define TEGRA30_CLK_FUSE 166 -#define TEGRA30_CLK_FUSE_BURN 167 -#define TEGRA30_CLK_CVE 168 -#define TEGRA30_CLK_TVO 169 -#define TEGRA30_CLK_CLK_32K 170 -#define TEGRA30_CLK_CLK_M 171 -#define TEGRA30_CLK_CLK_M_DIV2 172 -#define TEGRA30_CLK_CLK_M_DIV4 173 -#define TEGRA30_CLK_PLL_REF 174 -#define TEGRA30_CLK_PLL_C 175 -#define TEGRA30_CLK_PLL_C_OUT1 176 -#define TEGRA30_CLK_PLL_M 177 -#define TEGRA30_CLK_PLL_M_OUT1 178 -#define TEGRA30_CLK_PLL_P 179 -#define TEGRA30_CLK_PLL_P_OUT1 180 -#define TEGRA30_CLK_PLL_P_OUT2 181 -#define TEGRA30_CLK_PLL_P_OUT3 182 -#define TEGRA30_CLK_PLL_P_OUT4 183 -#define TEGRA30_CLK_PLL_A 184 -#define TEGRA30_CLK_PLL_A_OUT0 185 -#define TEGRA30_CLK_PLL_D 186 -#define TEGRA30_CLK_PLL_D_OUT0 187 -#define TEGRA30_CLK_PLL_D2 188 -#define TEGRA30_CLK_PLL_D2_OUT0 189 -#define TEGRA30_CLK_PLL_U 190 -#define TEGRA30_CLK_PLL_X 191 - -#define TEGRA30_CLK_PLL_X_OUT0 192 -#define TEGRA30_CLK_PLL_E 193 -#define TEGRA30_CLK_SPDIF_IN_SYNC 194 -#define TEGRA30_CLK_I2S0_SYNC 195 -#define TEGRA30_CLK_I2S1_SYNC 196 -#define TEGRA30_CLK_I2S2_SYNC 197 -#define TEGRA30_CLK_I2S3_SYNC 198 -#define TEGRA30_CLK_I2S4_SYNC 199 -#define TEGRA30_CLK_VIMCLK_SYNC 200 -#define TEGRA30_CLK_AUDIO0 201 -#define TEGRA30_CLK_AUDIO1 202 -#define TEGRA30_CLK_AUDIO2 203 -#define TEGRA30_CLK_AUDIO3 204 -#define TEGRA30_CLK_AUDIO4 205 -#define TEGRA30_CLK_SPDIF 206 -#define TEGRA30_CLK_CLK_OUT_1 207 /* (extern1) */ -#define TEGRA30_CLK_CLK_OUT_2 208 /* (extern2) */ -#define TEGRA30_CLK_CLK_OUT_3 209 /* (extern3) */ -#define TEGRA30_CLK_SCLK 210 -#define TEGRA30_CLK_BLINK 211 -#define TEGRA30_CLK_CCLK_G 212 -#define TEGRA30_CLK_CCLK_LP 213 -#define TEGRA30_CLK_TWD 214 -#define TEGRA30_CLK_CML0 215 -#define TEGRA30_CLK_CML1 216 -#define TEGRA30_CLK_HCLK 217 -#define TEGRA30_CLK_PCLK 218 -/* 219 */ -/* 220 */ -/* 221 */ -/* 222 */ -/* 223 */ - -/* 288 */ -/* 289 */ -/* 290 */ -/* 291 */ -/* 292 */ -/* 293 */ -/* 294 */ -/* 295 */ -/* 296 */ -/* 297 */ -/* 298 */ -/* 299 */ -#define TEGRA30_CLK_CLK_OUT_1_MUX 300 -#define TEGRA30_CLK_CLK_OUT_2_MUX 301 -#define TEGRA30_CLK_CLK_OUT_3_MUX 302 -#define TEGRA30_CLK_AUDIO0_MUX 303 -#define TEGRA30_CLK_AUDIO1_MUX 304 -#define TEGRA30_CLK_AUDIO2_MUX 305 -#define TEGRA30_CLK_AUDIO3_MUX 306 -#define TEGRA30_CLK_AUDIO4_MUX 307 -#define TEGRA30_CLK_SPDIF_MUX 308 -#define TEGRA30_CLK_CLK_MAX 309 - -#endif /* _DT_BINDINGS_CLOCK_TEGRA30_CAR_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/ti-dra7-atl.h b/sys/gnu/dts/include/dt-bindings/clock/ti-dra7-atl.h deleted file mode 100644 index e69de29bb2d..00000000000 diff --git a/sys/gnu/dts/include/dt-bindings/clock/vf610-clock.h b/sys/gnu/dts/include/dt-bindings/clock/vf610-clock.h deleted file mode 100644 index 95394f35a74..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/vf610-clock.h +++ /dev/null @@ -1,200 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - */ - -#ifndef __DT_BINDINGS_CLOCK_VF610_H -#define __DT_BINDINGS_CLOCK_VF610_H - -#define VF610_CLK_DUMMY 0 -#define VF610_CLK_SIRC_128K 1 -#define VF610_CLK_SIRC_32K 2 -#define VF610_CLK_FIRC 3 -#define VF610_CLK_SXOSC 4 -#define VF610_CLK_FXOSC 5 -#define VF610_CLK_FXOSC_HALF 6 -#define VF610_CLK_SLOW_CLK_SEL 7 -#define VF610_CLK_FASK_CLK_SEL 8 -#define VF610_CLK_AUDIO_EXT 9 -#define VF610_CLK_ENET_EXT 10 -#define VF610_CLK_PLL1_SYS 11 -#define VF610_CLK_PLL1_PFD1 12 -#define VF610_CLK_PLL1_PFD2 13 -#define VF610_CLK_PLL1_PFD3 14 -#define VF610_CLK_PLL1_PFD4 15 -#define VF610_CLK_PLL2_BUS 16 -#define VF610_CLK_PLL2_PFD1 17 -#define VF610_CLK_PLL2_PFD2 18 -#define VF610_CLK_PLL2_PFD3 19 -#define VF610_CLK_PLL2_PFD4 20 -#define VF610_CLK_PLL3_USB_OTG 21 -#define VF610_CLK_PLL3_PFD1 22 -#define VF610_CLK_PLL3_PFD2 23 -#define VF610_CLK_PLL3_PFD3 24 -#define VF610_CLK_PLL3_PFD4 25 -#define VF610_CLK_PLL4_AUDIO 26 -#define VF610_CLK_PLL5_ENET 27 -#define VF610_CLK_PLL6_VIDEO 28 -#define VF610_CLK_PLL3_MAIN_DIV 29 -#define VF610_CLK_PLL4_MAIN_DIV 30 -#define VF610_CLK_PLL6_MAIN_DIV 31 -#define VF610_CLK_PLL1_PFD_SEL 32 -#define VF610_CLK_PLL2_PFD_SEL 33 -#define VF610_CLK_SYS_SEL 34 -#define VF610_CLK_DDR_SEL 35 -#define VF610_CLK_SYS_BUS 36 -#define VF610_CLK_PLATFORM_BUS 37 -#define VF610_CLK_IPG_BUS 38 -#define VF610_CLK_UART0 39 -#define VF610_CLK_UART1 40 -#define VF610_CLK_UART2 41 -#define VF610_CLK_UART3 42 -#define VF610_CLK_UART4 43 -#define VF610_CLK_UART5 44 -#define VF610_CLK_PIT 45 -#define VF610_CLK_I2C0 46 -#define VF610_CLK_I2C1 47 -#define VF610_CLK_I2C2 48 -#define VF610_CLK_I2C3 49 -#define VF610_CLK_FTM0_EXT_SEL 50 -#define VF610_CLK_FTM0_FIX_SEL 51 -#define VF610_CLK_FTM0_EXT_FIX_EN 52 -#define VF610_CLK_FTM1_EXT_SEL 53 -#define VF610_CLK_FTM1_FIX_SEL 54 -#define VF610_CLK_FTM1_EXT_FIX_EN 55 -#define VF610_CLK_FTM2_EXT_SEL 56 -#define VF610_CLK_FTM2_FIX_SEL 57 -#define VF610_CLK_FTM2_EXT_FIX_EN 58 -#define VF610_CLK_FTM3_EXT_SEL 59 -#define VF610_CLK_FTM3_FIX_SEL 60 -#define VF610_CLK_FTM3_EXT_FIX_EN 61 -#define VF610_CLK_FTM0 62 -#define VF610_CLK_FTM1 63 -#define VF610_CLK_FTM2 64 -#define VF610_CLK_FTM3 65 -#define VF610_CLK_ENET_50M 66 -#define VF610_CLK_ENET_25M 67 -#define VF610_CLK_ENET_SEL 68 -#define VF610_CLK_ENET 69 -#define VF610_CLK_ENET_TS_SEL 70 -#define VF610_CLK_ENET_TS 71 -#define VF610_CLK_DSPI0 72 -#define VF610_CLK_DSPI1 73 -#define VF610_CLK_DSPI2 74 -#define VF610_CLK_DSPI3 75 -#define VF610_CLK_WDT 76 -#define VF610_CLK_ESDHC0_SEL 77 -#define VF610_CLK_ESDHC0_EN 78 -#define VF610_CLK_ESDHC0_DIV 79 -#define VF610_CLK_ESDHC0 80 -#define VF610_CLK_ESDHC1_SEL 81 -#define VF610_CLK_ESDHC1_EN 82 -#define VF610_CLK_ESDHC1_DIV 83 -#define VF610_CLK_ESDHC1 84 -#define VF610_CLK_DCU0_SEL 85 -#define VF610_CLK_DCU0_EN 86 -#define VF610_CLK_DCU0_DIV 87 -#define VF610_CLK_DCU0 88 -#define VF610_CLK_DCU1_SEL 89 -#define VF610_CLK_DCU1_EN 90 -#define VF610_CLK_DCU1_DIV 91 -#define VF610_CLK_DCU1 92 -#define VF610_CLK_ESAI_SEL 93 -#define VF610_CLK_ESAI_EN 94 -#define VF610_CLK_ESAI_DIV 95 -#define VF610_CLK_ESAI 96 -#define VF610_CLK_SAI0_SEL 97 -#define VF610_CLK_SAI0_EN 98 -#define VF610_CLK_SAI0_DIV 99 -#define VF610_CLK_SAI0 100 -#define VF610_CLK_SAI1_SEL 101 -#define VF610_CLK_SAI1_EN 102 -#define VF610_CLK_SAI1_DIV 103 -#define VF610_CLK_SAI1 104 -#define VF610_CLK_SAI2_SEL 105 -#define VF610_CLK_SAI2_EN 106 -#define VF610_CLK_SAI2_DIV 107 -#define VF610_CLK_SAI2 108 -#define VF610_CLK_SAI3_SEL 109 -#define VF610_CLK_SAI3_EN 110 -#define VF610_CLK_SAI3_DIV 111 -#define VF610_CLK_SAI3 112 -#define VF610_CLK_USBC0 113 -#define VF610_CLK_USBC1 114 -#define VF610_CLK_QSPI0_SEL 115 -#define VF610_CLK_QSPI0_EN 116 -#define VF610_CLK_QSPI0_X4_DIV 117 -#define VF610_CLK_QSPI0_X2_DIV 118 -#define VF610_CLK_QSPI0_X1_DIV 119 -#define VF610_CLK_QSPI1_SEL 120 -#define VF610_CLK_QSPI1_EN 121 -#define VF610_CLK_QSPI1_X4_DIV 122 -#define VF610_CLK_QSPI1_X2_DIV 123 -#define VF610_CLK_QSPI1_X1_DIV 124 -#define VF610_CLK_QSPI0 125 -#define VF610_CLK_QSPI1 126 -#define VF610_CLK_NFC_SEL 127 -#define VF610_CLK_NFC_EN 128 -#define VF610_CLK_NFC_PRE_DIV 129 -#define VF610_CLK_NFC_FRAC_DIV 130 -#define VF610_CLK_NFC_INV 131 -#define VF610_CLK_NFC 132 -#define VF610_CLK_VADC_SEL 133 -#define VF610_CLK_VADC_EN 134 -#define VF610_CLK_VADC_DIV 135 -#define VF610_CLK_VADC_DIV_HALF 136 -#define VF610_CLK_VADC 137 -#define VF610_CLK_ADC0 138 -#define VF610_CLK_ADC1 139 -#define VF610_CLK_DAC0 140 -#define VF610_CLK_DAC1 141 -#define VF610_CLK_FLEXCAN0 142 -#define VF610_CLK_FLEXCAN1 143 -#define VF610_CLK_ASRC 144 -#define VF610_CLK_GPU_SEL 145 -#define VF610_CLK_GPU_EN 146 -#define VF610_CLK_GPU2D 147 -#define VF610_CLK_ENET0 148 -#define VF610_CLK_ENET1 149 -#define VF610_CLK_DMAMUX0 150 -#define VF610_CLK_DMAMUX1 151 -#define VF610_CLK_DMAMUX2 152 -#define VF610_CLK_DMAMUX3 153 -#define VF610_CLK_FLEXCAN0_EN 154 -#define VF610_CLK_FLEXCAN1_EN 155 -#define VF610_CLK_PLL7_USB_HOST 156 -#define VF610_CLK_USBPHY0 157 -#define VF610_CLK_USBPHY1 158 -#define VF610_CLK_LVDS1_IN 159 -#define VF610_CLK_ANACLK1 160 -#define VF610_CLK_PLL1_BYPASS_SRC 161 -#define VF610_CLK_PLL2_BYPASS_SRC 162 -#define VF610_CLK_PLL3_BYPASS_SRC 163 -#define VF610_CLK_PLL4_BYPASS_SRC 164 -#define VF610_CLK_PLL5_BYPASS_SRC 165 -#define VF610_CLK_PLL6_BYPASS_SRC 166 -#define VF610_CLK_PLL7_BYPASS_SRC 167 -#define VF610_CLK_PLL1 168 -#define VF610_CLK_PLL2 169 -#define VF610_CLK_PLL3 170 -#define VF610_CLK_PLL4 171 -#define VF610_CLK_PLL5 172 -#define VF610_CLK_PLL6 173 -#define VF610_CLK_PLL7 174 -#define VF610_PLL1_BYPASS 175 -#define VF610_PLL2_BYPASS 176 -#define VF610_PLL3_BYPASS 177 -#define VF610_PLL4_BYPASS 178 -#define VF610_PLL5_BYPASS 179 -#define VF610_PLL6_BYPASS 180 -#define VF610_PLL7_BYPASS 181 -#define VF610_CLK_SNVS 182 -#define VF610_CLK_DAP 183 -#define VF610_CLK_OCOTP 184 -#define VF610_CLK_DDRMC 185 -#define VF610_CLK_WKPU 186 -#define VF610_CLK_TCON0 187 -#define VF610_CLK_TCON1 188 -#define VF610_CLK_END 189 - -#endif /* __DT_BINDINGS_CLOCK_VF610_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/x1000-cgu.h b/sys/gnu/dts/include/dt-bindings/clock/x1000-cgu.h deleted file mode 100644 index bbaebaf7adb..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/x1000-cgu.h +++ /dev/null @@ -1,44 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides clock numbers for the ingenic,x1000-cgu DT binding. - * - * They are roughly ordered as: - * - external clocks - * - PLLs - * - muxes/dividers in the order they appear in the x1000 programmers manual - * - gates in order of their bit in the CLKGR* registers - */ - -#ifndef __DT_BINDINGS_CLOCK_X1000_CGU_H__ -#define __DT_BINDINGS_CLOCK_X1000_CGU_H__ - -#define X1000_CLK_EXCLK 0 -#define X1000_CLK_RTCLK 1 -#define X1000_CLK_APLL 2 -#define X1000_CLK_MPLL 3 -#define X1000_CLK_SCLKA 4 -#define X1000_CLK_CPUMUX 5 -#define X1000_CLK_CPU 6 -#define X1000_CLK_L2CACHE 7 -#define X1000_CLK_AHB0 8 -#define X1000_CLK_AHB2PMUX 9 -#define X1000_CLK_AHB2 10 -#define X1000_CLK_PCLK 11 -#define X1000_CLK_DDR 12 -#define X1000_CLK_MAC 13 -#define X1000_CLK_MSCMUX 14 -#define X1000_CLK_MSC0 15 -#define X1000_CLK_MSC1 16 -#define X1000_CLK_SSIPLL 17 -#define X1000_CLK_SSIMUX 18 -#define X1000_CLK_SFC 19 -#define X1000_CLK_I2C0 20 -#define X1000_CLK_I2C1 21 -#define X1000_CLK_I2C2 22 -#define X1000_CLK_UART0 23 -#define X1000_CLK_UART1 24 -#define X1000_CLK_UART2 25 -#define X1000_CLK_SSI 26 -#define X1000_CLK_PDMA 27 - -#endif /* __DT_BINDINGS_CLOCK_X1000_CGU_H__ */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/xlnx-versal-clk.h b/sys/gnu/dts/include/dt-bindings/clock/xlnx-versal-clk.h deleted file mode 100644 index 264d634d226..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/xlnx-versal-clk.h +++ /dev/null @@ -1,123 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2019 Xilinx Inc. - * - */ - -#ifndef _DT_BINDINGS_CLK_VERSAL_H -#define _DT_BINDINGS_CLK_VERSAL_H - -#define PMC_PLL 1 -#define APU_PLL 2 -#define RPU_PLL 3 -#define CPM_PLL 4 -#define NOC_PLL 5 -#define PLL_MAX 6 -#define PMC_PRESRC 7 -#define PMC_POSTCLK 8 -#define PMC_PLL_OUT 9 -#define PPLL 10 -#define NOC_PRESRC 11 -#define NOC_POSTCLK 12 -#define NOC_PLL_OUT 13 -#define NPLL 14 -#define APU_PRESRC 15 -#define APU_POSTCLK 16 -#define APU_PLL_OUT 17 -#define APLL 18 -#define RPU_PRESRC 19 -#define RPU_POSTCLK 20 -#define RPU_PLL_OUT 21 -#define RPLL 22 -#define CPM_PRESRC 23 -#define CPM_POSTCLK 24 -#define CPM_PLL_OUT 25 -#define CPLL 26 -#define PPLL_TO_XPD 27 -#define NPLL_TO_XPD 28 -#define APLL_TO_XPD 29 -#define RPLL_TO_XPD 30 -#define EFUSE_REF 31 -#define SYSMON_REF 32 -#define IRO_SUSPEND_REF 33 -#define USB_SUSPEND 34 -#define SWITCH_TIMEOUT 35 -#define RCLK_PMC 36 -#define RCLK_LPD 37 -#define WDT 38 -#define TTC0 39 -#define TTC1 40 -#define TTC2 41 -#define TTC3 42 -#define GEM_TSU 43 -#define GEM_TSU_LB 44 -#define MUXED_IRO_DIV2 45 -#define MUXED_IRO_DIV4 46 -#define PSM_REF 47 -#define GEM0_RX 48 -#define GEM0_TX 49 -#define GEM1_RX 50 -#define GEM1_TX 51 -#define CPM_CORE_REF 52 -#define CPM_LSBUS_REF 53 -#define CPM_DBG_REF 54 -#define CPM_AUX0_REF 55 -#define CPM_AUX1_REF 56 -#define QSPI_REF 57 -#define OSPI_REF 58 -#define SDIO0_REF 59 -#define SDIO1_REF 60 -#define PMC_LSBUS_REF 61 -#define I2C_REF 62 -#define TEST_PATTERN_REF 63 -#define DFT_OSC_REF 64 -#define PMC_PL0_REF 65 -#define PMC_PL1_REF 66 -#define PMC_PL2_REF 67 -#define PMC_PL3_REF 68 -#define CFU_REF 69 -#define SPARE_REF 70 -#define NPI_REF 71 -#define HSM0_REF 72 -#define HSM1_REF 73 -#define SD_DLL_REF 74 -#define FPD_TOP_SWITCH 75 -#define FPD_LSBUS 76 -#define ACPU 77 -#define DBG_TRACE 78 -#define DBG_FPD 79 -#define LPD_TOP_SWITCH 80 -#define ADMA 81 -#define LPD_LSBUS 82 -#define CPU_R5 83 -#define CPU_R5_CORE 84 -#define CPU_R5_OCM 85 -#define CPU_R5_OCM2 86 -#define IOU_SWITCH 87 -#define GEM0_REF 88 -#define GEM1_REF 89 -#define GEM_TSU_REF 90 -#define USB0_BUS_REF 91 -#define UART0_REF 92 -#define UART1_REF 93 -#define SPI0_REF 94 -#define SPI1_REF 95 -#define CAN0_REF 96 -#define CAN1_REF 97 -#define I2C0_REF 98 -#define I2C1_REF 99 -#define DBG_LPD 100 -#define TIMESTAMP_REF 101 -#define DBG_TSTMP 102 -#define CPM_TOPSW_REF 103 -#define USB3_DUAL_REF 104 -#define OUTCLK_MAX 105 -#define REF_CLK 106 -#define PL_ALT_REF_CLK 107 -#define MUXED_IRO 108 -#define PL_EXT 109 -#define PL_LB 110 -#define MIO_50_OR_51 111 -#define MIO_24_OR_25 112 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/xlnx-zynqmp-clk.h b/sys/gnu/dts/include/dt-bindings/clock/xlnx-zynqmp-clk.h deleted file mode 100644 index cdc4c0b9a37..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/xlnx-zynqmp-clk.h +++ /dev/null @@ -1,126 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Xilinx Zynq MPSoC Firmware layer - * - * Copyright (C) 2014-2018 Xilinx, Inc. - * - */ - -#ifndef _DT_BINDINGS_CLK_ZYNQMP_H -#define _DT_BINDINGS_CLK_ZYNQMP_H - -#define IOPLL 0 -#define RPLL 1 -#define APLL 2 -#define DPLL 3 -#define VPLL 4 -#define IOPLL_TO_FPD 5 -#define RPLL_TO_FPD 6 -#define APLL_TO_LPD 7 -#define DPLL_TO_LPD 8 -#define VPLL_TO_LPD 9 -#define ACPU 10 -#define ACPU_HALF 11 -#define DBF_FPD 12 -#define DBF_LPD 13 -#define DBG_TRACE 14 -#define DBG_TSTMP 15 -#define DP_VIDEO_REF 16 -#define DP_AUDIO_REF 17 -#define DP_STC_REF 18 -#define GDMA_REF 19 -#define DPDMA_REF 20 -#define DDR_REF 21 -#define SATA_REF 22 -#define PCIE_REF 23 -#define GPU_REF 24 -#define GPU_PP0_REF 25 -#define GPU_PP1_REF 26 -#define TOPSW_MAIN 27 -#define TOPSW_LSBUS 28 -#define GTGREF0_REF 29 -#define LPD_SWITCH 30 -#define LPD_LSBUS 31 -#define USB0_BUS_REF 32 -#define USB1_BUS_REF 33 -#define USB3_DUAL_REF 34 -#define USB0 35 -#define USB1 36 -#define CPU_R5 37 -#define CPU_R5_CORE 38 -#define CSU_SPB 39 -#define CSU_PLL 40 -#define PCAP 41 -#define IOU_SWITCH 42 -#define GEM_TSU_REF 43 -#define GEM_TSU 44 -#define GEM0_TX 45 -#define GEM1_TX 46 -#define GEM2_TX 47 -#define GEM3_TX 48 -#define GEM0_RX 49 -#define GEM1_RX 50 -#define GEM2_RX 51 -#define GEM3_RX 52 -#define QSPI_REF 53 -#define SDIO0_REF 54 -#define SDIO1_REF 55 -#define UART0_REF 56 -#define UART1_REF 57 -#define SPI0_REF 58 -#define SPI1_REF 59 -#define NAND_REF 60 -#define I2C0_REF 61 -#define I2C1_REF 62 -#define CAN0_REF 63 -#define CAN1_REF 64 -#define CAN0 65 -#define CAN1 66 -#define DLL_REF 67 -#define ADMA_REF 68 -#define TIMESTAMP_REF 69 -#define AMS_REF 70 -#define PL0_REF 71 -#define PL1_REF 72 -#define PL2_REF 73 -#define PL3_REF 74 -#define WDT 75 -#define IOPLL_INT 76 -#define IOPLL_PRE_SRC 77 -#define IOPLL_HALF 78 -#define IOPLL_INT_MUX 79 -#define IOPLL_POST_SRC 80 -#define RPLL_INT 81 -#define RPLL_PRE_SRC 82 -#define RPLL_HALF 83 -#define RPLL_INT_MUX 84 -#define RPLL_POST_SRC 85 -#define APLL_INT 86 -#define APLL_PRE_SRC 87 -#define APLL_HALF 88 -#define APLL_INT_MUX 89 -#define APLL_POST_SRC 90 -#define DPLL_INT 91 -#define DPLL_PRE_SRC 92 -#define DPLL_HALF 93 -#define DPLL_INT_MUX 94 -#define DPLL_POST_SRC 95 -#define VPLL_INT 96 -#define VPLL_PRE_SRC 97 -#define VPLL_HALF 98 -#define VPLL_INT_MUX 99 -#define VPLL_POST_SRC 100 -#define CAN0_MIO 101 -#define CAN1_MIO 102 -#define ACPU_FULL 103 -#define GEM0_REF 104 -#define GEM1_REF 105 -#define GEM2_REF 106 -#define GEM3_REF 107 -#define GEM0_REF_UNG 108 -#define GEM1_REF_UNG 109 -#define GEM2_REF_UNG 110 -#define GEM3_REF_UNG 111 -#define LPD_WDT 112 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/zx296702-clock.h b/sys/gnu/dts/include/dt-bindings/clock/zx296702-clock.h deleted file mode 100644 index e04126111aa..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/zx296702-clock.h +++ /dev/null @@ -1,180 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2014 Linaro Ltd. - * Copyright (C) 2014 ZTE Corporation. - */ - -#ifndef __DT_BINDINGS_CLOCK_ZX296702_H -#define __DT_BINDINGS_CLOCK_ZX296702_H - -#define ZX296702_OSC 0 -#define ZX296702_PLL_A9 1 -#define ZX296702_PLL_A9_350M 2 -#define ZX296702_PLL_MAC_1000M 3 -#define ZX296702_PLL_MAC_333M 4 -#define ZX296702_PLL_MM0_1188M 5 -#define ZX296702_PLL_MM0_396M 6 -#define ZX296702_PLL_MM0_198M 7 -#define ZX296702_PLL_MM1_108M 8 -#define ZX296702_PLL_MM1_72M 9 -#define ZX296702_PLL_MM1_54M 10 -#define ZX296702_PLL_LSP_104M 11 -#define ZX296702_PLL_LSP_26M 12 -#define ZX296702_PLL_AUDIO_294M912 13 -#define ZX296702_PLL_DDR_266M 14 -#define ZX296702_CLK_148M5 15 -#define ZX296702_MATRIX_ACLK 16 -#define ZX296702_MAIN_HCLK 17 -#define ZX296702_MAIN_PCLK 18 -#define ZX296702_CLK_500 19 -#define ZX296702_CLK_250 20 -#define ZX296702_CLK_125 21 -#define ZX296702_CLK_74M25 22 -#define ZX296702_A9_WCLK 23 -#define ZX296702_A9_AS1_ACLK_MUX 24 -#define ZX296702_A9_TRACE_CLKIN_MUX 25 -#define ZX296702_A9_AS1_ACLK_DIV 26 -#define ZX296702_CLK_2 27 -#define ZX296702_CLK_27 28 -#define ZX296702_DECPPU_ACLK_MUX 29 -#define ZX296702_PPU_ACLK_MUX 30 -#define ZX296702_MALI400_ACLK_MUX 31 -#define ZX296702_VOU_ACLK_MUX 32 -#define ZX296702_VOU_MAIN_WCLK_MUX 33 -#define ZX296702_VOU_AUX_WCLK_MUX 34 -#define ZX296702_VOU_SCALER_WCLK_MUX 35 -#define ZX296702_R2D_ACLK_MUX 36 -#define ZX296702_R2D_WCLK_MUX 37 -#define ZX296702_CLK_50 38 -#define ZX296702_CLK_25 39 -#define ZX296702_CLK_12 40 -#define ZX296702_CLK_16M384 41 -#define ZX296702_CLK_32K768 42 -#define ZX296702_SEC_WCLK_DIV 43 -#define ZX296702_DDR_WCLK_MUX 44 -#define ZX296702_NAND_WCLK_MUX 45 -#define ZX296702_LSP_26_WCLK_MUX 46 -#define ZX296702_A9_AS0_ACLK 47 -#define ZX296702_A9_AS1_ACLK 48 -#define ZX296702_A9_TRACE_CLKIN 49 -#define ZX296702_DECPPU_AXI_M_ACLK 50 -#define ZX296702_DECPPU_AHB_S_HCLK 51 -#define ZX296702_PPU_AXI_M_ACLK 52 -#define ZX296702_PPU_AHB_S_HCLK 53 -#define ZX296702_VOU_AXI_M_ACLK 54 -#define ZX296702_VOU_APB_PCLK 55 -#define ZX296702_VOU_MAIN_CHANNEL_WCLK 56 -#define ZX296702_VOU_AUX_CHANNEL_WCLK 57 -#define ZX296702_VOU_HDMI_OSCLK_CEC 58 -#define ZX296702_VOU_SCALER_WCLK 59 -#define ZX296702_MALI400_AXI_M_ACLK 60 -#define ZX296702_MALI400_APB_PCLK 61 -#define ZX296702_R2D_WCLK 62 -#define ZX296702_R2D_AXI_M_ACLK 63 -#define ZX296702_R2D_AHB_HCLK 64 -#define ZX296702_DDR3_AXI_S0_ACLK 65 -#define ZX296702_DDR3_APB_PCLK 66 -#define ZX296702_DDR3_WCLK 67 -#define ZX296702_USB20_0_AHB_HCLK 68 -#define ZX296702_USB20_0_EXTREFCLK 69 -#define ZX296702_USB20_1_AHB_HCLK 70 -#define ZX296702_USB20_1_EXTREFCLK 71 -#define ZX296702_USB20_2_AHB_HCLK 72 -#define ZX296702_USB20_2_EXTREFCLK 73 -#define ZX296702_GMAC_AXI_M_ACLK 74 -#define ZX296702_GMAC_APB_PCLK 75 -#define ZX296702_GMAC_125_CLKIN 76 -#define ZX296702_GMAC_RMII_CLKIN 77 -#define ZX296702_GMAC_25M_CLK 78 -#define ZX296702_NANDFLASH_AHB_HCLK 79 -#define ZX296702_NANDFLASH_WCLK 80 -#define ZX296702_LSP0_APB_PCLK 81 -#define ZX296702_LSP0_AHB_HCLK 82 -#define ZX296702_LSP0_26M_WCLK 83 -#define ZX296702_LSP0_104M_WCLK 84 -#define ZX296702_LSP0_16M384_WCLK 85 -#define ZX296702_LSP1_APB_PCLK 86 -#define ZX296702_LSP1_26M_WCLK 87 -#define ZX296702_LSP1_104M_WCLK 88 -#define ZX296702_LSP1_32K_CLK 89 -#define ZX296702_AON_HCLK 90 -#define ZX296702_SYS_CTRL_PCLK 91 -#define ZX296702_DMA_PCLK 92 -#define ZX296702_DMA_ACLK 93 -#define ZX296702_SEC_HCLK 94 -#define ZX296702_AES_WCLK 95 -#define ZX296702_DES_WCLK 96 -#define ZX296702_IRAM_ACLK 97 -#define ZX296702_IROM_ACLK 98 -#define ZX296702_BOOT_CTRL_HCLK 99 -#define ZX296702_EFUSE_CLK_30 100 -#define ZX296702_VOU_MAIN_CHANNEL_DIV 101 -#define ZX296702_VOU_AUX_CHANNEL_DIV 102 -#define ZX296702_VOU_TV_ENC_HD_DIV 103 -#define ZX296702_VOU_TV_ENC_SD_DIV 104 -#define ZX296702_VL0_MUX 105 -#define ZX296702_VL1_MUX 106 -#define ZX296702_VL2_MUX 107 -#define ZX296702_GL0_MUX 108 -#define ZX296702_GL1_MUX 109 -#define ZX296702_GL2_MUX 110 -#define ZX296702_WB_MUX 111 -#define ZX296702_HDMI_MUX 112 -#define ZX296702_VOU_TV_ENC_HD_MUX 113 -#define ZX296702_VOU_TV_ENC_SD_MUX 114 -#define ZX296702_VL0_CLK 115 -#define ZX296702_VL1_CLK 116 -#define ZX296702_VL2_CLK 117 -#define ZX296702_GL0_CLK 118 -#define ZX296702_GL1_CLK 119 -#define ZX296702_GL2_CLK 120 -#define ZX296702_WB_CLK 121 -#define ZX296702_CL_CLK 122 -#define ZX296702_MAIN_MIX_CLK 123 -#define ZX296702_AUX_MIX_CLK 124 -#define ZX296702_HDMI_CLK 125 -#define ZX296702_VOU_TV_ENC_HD_DAC_CLK 126 -#define ZX296702_VOU_TV_ENC_SD_DAC_CLK 127 -#define ZX296702_A9_PERIPHCLK 128 -#define ZX296702_TOPCLK_END 129 - -#define ZX296702_SDMMC1_WCLK_MUX 0 -#define ZX296702_SDMMC1_WCLK_DIV 1 -#define ZX296702_SDMMC1_WCLK 2 -#define ZX296702_SDMMC1_PCLK 3 -#define ZX296702_SPDIF0_WCLK_MUX 4 -#define ZX296702_SPDIF0_WCLK 5 -#define ZX296702_SPDIF0_PCLK 6 -#define ZX296702_SPDIF0_DIV 7 -#define ZX296702_I2S0_WCLK_MUX 8 -#define ZX296702_I2S0_WCLK 9 -#define ZX296702_I2S0_PCLK 10 -#define ZX296702_I2S0_DIV 11 -#define ZX296702_I2S1_WCLK_MUX 12 -#define ZX296702_I2S1_WCLK 13 -#define ZX296702_I2S1_PCLK 14 -#define ZX296702_I2S1_DIV 15 -#define ZX296702_I2S2_WCLK_MUX 16 -#define ZX296702_I2S2_WCLK 17 -#define ZX296702_I2S2_PCLK 18 -#define ZX296702_I2S2_DIV 19 -#define ZX296702_GPIO_CLK 20 -#define ZX296702_LSP0CLK_END 21 - -#define ZX296702_UART0_WCLK_MUX 0 -#define ZX296702_UART0_WCLK 1 -#define ZX296702_UART0_PCLK 2 -#define ZX296702_UART1_WCLK_MUX 3 -#define ZX296702_UART1_WCLK 4 -#define ZX296702_UART1_PCLK 5 -#define ZX296702_SDMMC0_WCLK_MUX 6 -#define ZX296702_SDMMC0_WCLK_DIV 7 -#define ZX296702_SDMMC0_WCLK 8 -#define ZX296702_SDMMC0_PCLK 9 -#define ZX296702_SPDIF1_WCLK_MUX 10 -#define ZX296702_SPDIF1_WCLK 11 -#define ZX296702_SPDIF1_PCLK 12 -#define ZX296702_SPDIF1_DIV 13 -#define ZX296702_LSP1CLK_END 14 - -#endif /* __DT_BINDINGS_CLOCK_ZX296702_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/zx296718-clock.h b/sys/gnu/dts/include/dt-bindings/clock/zx296718-clock.h deleted file mode 100644 index bf2ff6d2ee2..00000000000 --- a/sys/gnu/dts/include/dt-bindings/clock/zx296718-clock.h +++ /dev/null @@ -1,164 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) 2015 - 2016 ZTE Corporation. - */ -#ifndef __DT_BINDINGS_CLOCK_ZX296718_H -#define __DT_BINDINGS_CLOCK_ZX296718_H - -/* PLL */ -#define ZX296718_PLL_CPU 1 -#define ZX296718_PLL_MAC 2 -#define ZX296718_PLL_MM0 3 -#define ZX296718_PLL_MM1 4 -#define ZX296718_PLL_VGA 5 -#define ZX296718_PLL_DDR 6 -#define ZX296718_PLL_AUDIO 7 -#define ZX296718_PLL_HSIC 8 -#define CPU_DBG_GATE 9 -#define A72_GATE 10 -#define CPU_PERI_GATE 11 -#define A53_GATE 12 -#define DDR1_GATE 13 -#define DDR0_GATE 14 -#define SD1_WCLK 15 -#define SD1_AHB 16 -#define SD0_WCLK 17 -#define SD0_AHB 18 -#define EMMC_WCLK 19 -#define EMMC_NAND_AXI 20 -#define NAND_WCLK 21 -#define EMMC_NAND_AHB 22 -#define LSP1_148M5 23 -#define LSP1_99M 24 -#define LSP1_24M 25 -#define LSP0_74M25 26 -#define LSP0_32K 27 -#define LSP0_148M5 28 -#define LSP0_99M 29 -#define LSP0_24M 30 -#define DEMUX_AXI 31 -#define DEMUX_APB 32 -#define DEMUX_148M5 33 -#define DEMUX_108M 34 -#define AUDIO_APB 35 -#define AUDIO_99M 36 -#define AUDIO_24M 37 -#define AUDIO_16M384 38 -#define AUDIO_32K 39 -#define WDT_WCLK 40 -#define TIMER_WCLK 41 -#define VDE_ACLK 42 -#define VCE_ACLK 43 -#define HDE_ACLK 44 -#define GPU_ACLK 45 -#define SAPPU_ACLK 46 -#define SAPPU_WCLK 47 -#define VOU_ACLK 48 -#define VOU_MAIN_WCLK 49 -#define VOU_AUX_WCLK 50 -#define VOU_PPU_WCLK 51 -#define MIPI_CFG_CLK 52 -#define VGA_I2C_WCLK 53 -#define MIPI_REF_CLK 54 -#define HDMI_OSC_CEC 55 -#define HDMI_OSC_CLK 56 -#define HDMI_XCLK 57 -#define VIU_M0_ACLK 58 -#define VIU_M1_ACLK 59 -#define VIU_WCLK 60 -#define VIU_JPEG_WCLK 61 -#define VIU_CFG_CLK 62 -#define TS_SYS_WCLK 63 -#define TS_SYS_108M 64 -#define USB20_HCLK 65 -#define USB20_PHY_CLK 66 -#define USB21_HCLK 67 -#define USB21_PHY_CLK 68 -#define GMAC_RMIICLK 69 -#define GMAC_PCLK 70 -#define GMAC_ACLK 71 -#define GMAC_RFCLK 72 -#define TEMPSENSOR_GATE 73 - -#define TOP_NR_CLKS 74 - - -#define LSP0_TIMER3_PCLK 1 -#define LSP0_TIMER3_WCLK 2 -#define LSP0_TIMER4_PCLK 3 -#define LSP0_TIMER4_WCLK 4 -#define LSP0_TIMER5_PCLK 5 -#define LSP0_TIMER5_WCLK 6 -#define LSP0_UART3_PCLK 7 -#define LSP0_UART3_WCLK 8 -#define LSP0_UART1_PCLK 9 -#define LSP0_UART1_WCLK 10 -#define LSP0_UART2_PCLK 11 -#define LSP0_UART2_WCLK 12 -#define LSP0_SPIFC0_PCLK 13 -#define LSP0_SPIFC0_WCLK 14 -#define LSP0_I2C4_PCLK 15 -#define LSP0_I2C4_WCLK 16 -#define LSP0_I2C5_PCLK 17 -#define LSP0_I2C5_WCLK 18 -#define LSP0_SSP0_PCLK 19 -#define LSP0_SSP0_WCLK 20 -#define LSP0_SSP1_PCLK 21 -#define LSP0_SSP1_WCLK 22 -#define LSP0_USIM_PCLK 23 -#define LSP0_USIM_WCLK 24 -#define LSP0_GPIO_PCLK 25 -#define LSP0_GPIO_WCLK 26 -#define LSP0_I2C3_PCLK 27 -#define LSP0_I2C3_WCLK 28 - -#define LSP0_NR_CLKS 29 - - -#define LSP1_UART4_PCLK 1 -#define LSP1_UART4_WCLK 2 -#define LSP1_UART5_PCLK 3 -#define LSP1_UART5_WCLK 4 -#define LSP1_PWM_PCLK 5 -#define LSP1_PWM_WCLK 6 -#define LSP1_I2C2_PCLK 7 -#define LSP1_I2C2_WCLK 8 -#define LSP1_SSP2_PCLK 9 -#define LSP1_SSP2_WCLK 10 -#define LSP1_SSP3_PCLK 11 -#define LSP1_SSP3_WCLK 12 -#define LSP1_SSP4_PCLK 13 -#define LSP1_SSP4_WCLK 14 -#define LSP1_USIM1_PCLK 15 -#define LSP1_USIM1_WCLK 16 - -#define LSP1_NR_CLKS 17 - - -#define AUDIO_I2S0_WCLK 1 -#define AUDIO_I2S0_PCLK 2 -#define AUDIO_I2S1_WCLK 3 -#define AUDIO_I2S1_PCLK 4 -#define AUDIO_I2S2_WCLK 5 -#define AUDIO_I2S2_PCLK 6 -#define AUDIO_I2S3_WCLK 7 -#define AUDIO_I2S3_PCLK 8 -#define AUDIO_I2C0_WCLK 9 -#define AUDIO_I2C0_PCLK 10 -#define AUDIO_SPDIF0_WCLK 11 -#define AUDIO_SPDIF0_PCLK 12 -#define AUDIO_SPDIF1_WCLK 13 -#define AUDIO_SPDIF1_PCLK 14 -#define AUDIO_TIMER_WCLK 15 -#define AUDIO_TIMER_PCLK 16 -#define AUDIO_TDM_WCLK 17 -#define AUDIO_TDM_PCLK 18 -#define AUDIO_TS_PCLK 19 -#define I2S0_WCLK_MUX 20 -#define I2S1_WCLK_MUX 21 -#define I2S2_WCLK_MUX 22 -#define I2S3_WCLK_MUX 23 - -#define AUDIO_NR_CLKS 24 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/display/tda998x.h b/sys/gnu/dts/include/dt-bindings/display/tda998x.h deleted file mode 100644 index 746831ff396..00000000000 --- a/sys/gnu/dts/include/dt-bindings/display/tda998x.h +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _DT_BINDINGS_TDA998X_H -#define _DT_BINDINGS_TDA998X_H - -#define TDA998x_SPDIF 1 -#define TDA998x_I2S 2 - -#endif /*_DT_BINDINGS_TDA998X_H */ diff --git a/sys/gnu/dts/include/dt-bindings/dma/at91.h b/sys/gnu/dts/include/dt-bindings/dma/at91.h deleted file mode 100644 index e7b3e06554c..00000000000 --- a/sys/gnu/dts/include/dt-bindings/dma/at91.h +++ /dev/null @@ -1,51 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * This header provides macros for at91 dma bindings. - * - * Copyright (C) 2013 Ludovic Desroches - */ - -#ifndef __DT_BINDINGS_AT91_DMA_H__ -#define __DT_BINDINGS_AT91_DMA_H__ - -/* ---------- HDMAC ---------- */ - -/* - * Source and/or destination peripheral ID - */ -#define AT91_DMA_CFG_PER_ID_MASK (0xff) -#define AT91_DMA_CFG_PER_ID(id) (id & AT91_DMA_CFG_PER_ID_MASK) - -/* - * FIFO configuration: it defines when a request is serviced. - */ -#define AT91_DMA_CFG_FIFOCFG_OFFSET (8) -#define AT91_DMA_CFG_FIFOCFG_MASK (0xf << AT91_DMA_CFG_FIFOCFG_OFFSET) -#define AT91_DMA_CFG_FIFOCFG_HALF (0x0 << AT91_DMA_CFG_FIFOCFG_OFFSET) /* half FIFO (default behavior) */ -#define AT91_DMA_CFG_FIFOCFG_ALAP (0x1 << AT91_DMA_CFG_FIFOCFG_OFFSET) /* largest defined AHB burst */ -#define AT91_DMA_CFG_FIFOCFG_ASAP (0x2 << AT91_DMA_CFG_FIFOCFG_OFFSET) /* single AHB access */ - - -/* ---------- XDMAC ---------- */ -#define AT91_XDMAC_DT_MEM_IF_MASK (0x1) -#define AT91_XDMAC_DT_MEM_IF_OFFSET (13) -#define AT91_XDMAC_DT_MEM_IF(mem_if) (((mem_if) & AT91_XDMAC_DT_MEM_IF_MASK) \ - << AT91_XDMAC_DT_MEM_IF_OFFSET) -#define AT91_XDMAC_DT_GET_MEM_IF(cfg) (((cfg) >> AT91_XDMAC_DT_MEM_IF_OFFSET) \ - & AT91_XDMAC_DT_MEM_IF_MASK) - -#define AT91_XDMAC_DT_PER_IF_MASK (0x1) -#define AT91_XDMAC_DT_PER_IF_OFFSET (14) -#define AT91_XDMAC_DT_PER_IF(per_if) (((per_if) & AT91_XDMAC_DT_PER_IF_MASK) \ - << AT91_XDMAC_DT_PER_IF_OFFSET) -#define AT91_XDMAC_DT_GET_PER_IF(cfg) (((cfg) >> AT91_XDMAC_DT_PER_IF_OFFSET) \ - & AT91_XDMAC_DT_PER_IF_MASK) - -#define AT91_XDMAC_DT_PERID_MASK (0x7f) -#define AT91_XDMAC_DT_PERID_OFFSET (24) -#define AT91_XDMAC_DT_PERID(perid) (((perid) & AT91_XDMAC_DT_PERID_MASK) \ - << AT91_XDMAC_DT_PERID_OFFSET) -#define AT91_XDMAC_DT_GET_PERID(cfg) (((cfg) >> AT91_XDMAC_DT_PERID_OFFSET) \ - & AT91_XDMAC_DT_PERID_MASK) - -#endif /* __DT_BINDINGS_AT91_DMA_H__ */ diff --git a/sys/gnu/dts/include/dt-bindings/dma/axi-dmac.h b/sys/gnu/dts/include/dt-bindings/dma/axi-dmac.h deleted file mode 100644 index ad9e6ecb9c2..00000000000 --- a/sys/gnu/dts/include/dt-bindings/dma/axi-dmac.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef __DT_BINDINGS_DMA_AXI_DMAC_H__ -#define __DT_BINDINGS_DMA_AXI_DMAC_H__ - -#define AXI_DMAC_BUS_TYPE_AXI_MM 0 -#define AXI_DMAC_BUS_TYPE_AXI_STREAM 1 -#define AXI_DMAC_BUS_TYPE_FIFO 2 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/dma/dw-dmac.h b/sys/gnu/dts/include/dt-bindings/dma/dw-dmac.h deleted file mode 100644 index d1ca705c95b..00000000000 --- a/sys/gnu/dts/include/dt-bindings/dma/dw-dmac.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ - -#ifndef __DT_BINDINGS_DMA_DW_DMAC_H__ -#define __DT_BINDINGS_DMA_DW_DMAC_H__ - -/* - * Protection Control bits provide protection against illegal transactions. - * The protection bits[0:2] are one-to-one mapped to AHB HPROT[3:1] signals. - */ -#define DW_DMAC_HPROT1_PRIVILEGED_MODE (1 << 0) /* Privileged Mode */ -#define DW_DMAC_HPROT2_BUFFERABLE (1 << 1) /* DMA is bufferable */ -#define DW_DMAC_HPROT3_CACHEABLE (1 << 2) /* DMA is cacheable */ - -#endif /* __DT_BINDINGS_DMA_DW_DMAC_H__ */ diff --git a/sys/gnu/dts/include/dt-bindings/dma/jz4780-dma.h b/sys/gnu/dts/include/dt-bindings/dma/jz4780-dma.h deleted file mode 100644 index df017fdfb44..00000000000 --- a/sys/gnu/dts/include/dt-bindings/dma/jz4780-dma.h +++ /dev/null @@ -1,49 +0,0 @@ -#ifndef __DT_BINDINGS_DMA_JZ4780_DMA_H__ -#define __DT_BINDINGS_DMA_JZ4780_DMA_H__ - -/* - * Request type numbers for the JZ4780 DMA controller (written to the DRTn - * register for the channel). - */ -#define JZ4780_DMA_I2S1_TX 0x4 -#define JZ4780_DMA_I2S1_RX 0x5 -#define JZ4780_DMA_I2S0_TX 0x6 -#define JZ4780_DMA_I2S0_RX 0x7 -#define JZ4780_DMA_AUTO 0x8 -#define JZ4780_DMA_SADC_RX 0x9 -#define JZ4780_DMA_UART4_TX 0xc -#define JZ4780_DMA_UART4_RX 0xd -#define JZ4780_DMA_UART3_TX 0xe -#define JZ4780_DMA_UART3_RX 0xf -#define JZ4780_DMA_UART2_TX 0x10 -#define JZ4780_DMA_UART2_RX 0x11 -#define JZ4780_DMA_UART1_TX 0x12 -#define JZ4780_DMA_UART1_RX 0x13 -#define JZ4780_DMA_UART0_TX 0x14 -#define JZ4780_DMA_UART0_RX 0x15 -#define JZ4780_DMA_SSI0_TX 0x16 -#define JZ4780_DMA_SSI0_RX 0x17 -#define JZ4780_DMA_SSI1_TX 0x18 -#define JZ4780_DMA_SSI1_RX 0x19 -#define JZ4780_DMA_MSC0_TX 0x1a -#define JZ4780_DMA_MSC0_RX 0x1b -#define JZ4780_DMA_MSC1_TX 0x1c -#define JZ4780_DMA_MSC1_RX 0x1d -#define JZ4780_DMA_MSC2_TX 0x1e -#define JZ4780_DMA_MSC2_RX 0x1f -#define JZ4780_DMA_PCM0_TX 0x20 -#define JZ4780_DMA_PCM0_RX 0x21 -#define JZ4780_DMA_SMB0_TX 0x24 -#define JZ4780_DMA_SMB0_RX 0x25 -#define JZ4780_DMA_SMB1_TX 0x26 -#define JZ4780_DMA_SMB1_RX 0x27 -#define JZ4780_DMA_SMB2_TX 0x28 -#define JZ4780_DMA_SMB2_RX 0x29 -#define JZ4780_DMA_SMB3_TX 0x2a -#define JZ4780_DMA_SMB3_RX 0x2b -#define JZ4780_DMA_SMB4_TX 0x2c -#define JZ4780_DMA_SMB4_RX 0x2d -#define JZ4780_DMA_DES_TX 0x2e -#define JZ4780_DMA_DES_RX 0x2f - -#endif /* __DT_BINDINGS_DMA_JZ4780_DMA_H__ */ diff --git a/sys/gnu/dts/include/dt-bindings/dma/nbpfaxi.h b/sys/gnu/dts/include/dt-bindings/dma/nbpfaxi.h deleted file mode 100644 index 88e59acc067..00000000000 --- a/sys/gnu/dts/include/dt-bindings/dma/nbpfaxi.h +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) 2013-2014 Renesas Electronics Europe Ltd. - * Author: Guennadi Liakhovetski - */ - -#ifndef DT_BINDINGS_NBPFAXI_H -#define DT_BINDINGS_NBPFAXI_H - -/** - * Use "#dma-cells = <2>;" with the second integer defining slave DMA flags: - */ -#define NBPF_SLAVE_RQ_HIGH 1 -#define NBPF_SLAVE_RQ_LOW 2 -#define NBPF_SLAVE_RQ_LEVEL 4 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/dma/sun4i-a10.h b/sys/gnu/dts/include/dt-bindings/dma/sun4i-a10.h deleted file mode 100644 index 8caba9ef7e9..00000000000 --- a/sys/gnu/dts/include/dt-bindings/dma/sun4i-a10.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - * Copyright 2014 Maxime Ripard - * - * Maxime Ripard - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef __DT_BINDINGS_DMA_SUN4I_A10_H_ -#define __DT_BINDINGS_DMA_SUN4I_A10_H_ - -#define SUN4I_DMA_NORMAL 0 -#define SUN4I_DMA_DEDICATED 1 - -#endif /* __DT_BINDINGS_DMA_SUN4I_A10_H_ */ diff --git a/sys/gnu/dts/include/dt-bindings/dma/x1000-dma.h b/sys/gnu/dts/include/dt-bindings/dma/x1000-dma.h deleted file mode 100644 index 401e1656e69..00000000000 --- a/sys/gnu/dts/include/dt-bindings/dma/x1000-dma.h +++ /dev/null @@ -1,40 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * This header provides macros for X1000 DMA bindings. - * - * Copyright (c) 2019 Zhou Yanjie - */ - -#ifndef __DT_BINDINGS_DMA_X1000_DMA_H__ -#define __DT_BINDINGS_DMA_X1000_DMA_H__ - -/* - * Request type numbers for the X1000 DMA controller (written to the DRTn - * register for the channel). - */ -#define X1000_DMA_DMIC_RX 0x5 -#define X1000_DMA_I2S0_TX 0x6 -#define X1000_DMA_I2S0_RX 0x7 -#define X1000_DMA_AUTO 0x8 -#define X1000_DMA_UART2_TX 0x10 -#define X1000_DMA_UART2_RX 0x11 -#define X1000_DMA_UART1_TX 0x12 -#define X1000_DMA_UART1_RX 0x13 -#define X1000_DMA_UART0_TX 0x14 -#define X1000_DMA_UART0_RX 0x15 -#define X1000_DMA_SSI0_TX 0x16 -#define X1000_DMA_SSI0_RX 0x17 -#define X1000_DMA_MSC0_TX 0x1a -#define X1000_DMA_MSC0_RX 0x1b -#define X1000_DMA_MSC1_TX 0x1c -#define X1000_DMA_MSC1_RX 0x1d -#define X1000_DMA_PCM0_TX 0x20 -#define X1000_DMA_PCM0_RX 0x21 -#define X1000_DMA_SMB0_TX 0x24 -#define X1000_DMA_SMB0_RX 0x25 -#define X1000_DMA_SMB1_TX 0x26 -#define X1000_DMA_SMB1_RX 0x27 -#define X1000_DMA_SMB2_TX 0x28 -#define X1000_DMA_SMB2_RX 0x29 - -#endif /* __DT_BINDINGS_DMA_X1000_DMA_H__ */ diff --git a/sys/gnu/dts/include/dt-bindings/dma/x1830-dma.h b/sys/gnu/dts/include/dt-bindings/dma/x1830-dma.h deleted file mode 100644 index 35bcb8966ea..00000000000 --- a/sys/gnu/dts/include/dt-bindings/dma/x1830-dma.h +++ /dev/null @@ -1,39 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * This header provides macros for X1830 DMA bindings. - * - * Copyright (c) 2019 周琰杰 (Zhou Yanjie) - */ - -#ifndef __DT_BINDINGS_DMA_X1830_DMA_H__ -#define __DT_BINDINGS_DMA_X1830_DMA_H__ - -/* - * Request type numbers for the X1830 DMA controller (written to the DRTn - * register for the channel). - */ -#define X1830_DMA_I2S0_TX 0x6 -#define X1830_DMA_I2S0_RX 0x7 -#define X1830_DMA_AUTO 0x8 -#define X1830_DMA_SADC_RX 0x9 -#define X1830_DMA_UART1_TX 0x12 -#define X1830_DMA_UART1_RX 0x13 -#define X1830_DMA_UART0_TX 0x14 -#define X1830_DMA_UART0_RX 0x15 -#define X1830_DMA_SSI0_TX 0x16 -#define X1830_DMA_SSI0_RX 0x17 -#define X1830_DMA_SSI1_TX 0x18 -#define X1830_DMA_SSI1_RX 0x19 -#define X1830_DMA_MSC0_TX 0x1a -#define X1830_DMA_MSC0_RX 0x1b -#define X1830_DMA_MSC1_TX 0x1c -#define X1830_DMA_MSC1_RX 0x1d -#define X1830_DMA_DMIC_RX 0x21 -#define X1830_DMA_SMB0_TX 0x24 -#define X1830_DMA_SMB0_RX 0x25 -#define X1830_DMA_SMB1_TX 0x26 -#define X1830_DMA_SMB1_RX 0x27 -#define X1830_DMA_DES_TX 0x2e -#define X1830_DMA_DES_RX 0x2f - -#endif /* __DT_BINDINGS_DMA_X1830_DMA_H__ */ diff --git a/sys/gnu/dts/include/dt-bindings/firmware/imx/rsrc.h b/sys/gnu/dts/include/dt-bindings/firmware/imx/rsrc.h deleted file mode 100644 index 4e61f648509..00000000000 --- a/sys/gnu/dts/include/dt-bindings/firmware/imx/rsrc.h +++ /dev/null @@ -1,550 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2016 Freescale Semiconductor, Inc. - * Copyright 2017-2018 NXP - */ - -#ifndef __DT_BINDINGS_RSCRC_IMX_H -#define __DT_BINDINGS_RSCRC_IMX_H - -/* - * These defines are used to indicate a resource. Resources include peripherals - * and bus masters (but not memory regions). Note items from list should - * never be changed or removed (only added to at the end of the list). - */ - -#define IMX_SC_R_A53 0 -#define IMX_SC_R_A53_0 1 -#define IMX_SC_R_A53_1 2 -#define IMX_SC_R_A53_2 3 -#define IMX_SC_R_A53_3 4 -#define IMX_SC_R_A72 5 -#define IMX_SC_R_A72_0 6 -#define IMX_SC_R_A72_1 7 -#define IMX_SC_R_A72_2 8 -#define IMX_SC_R_A72_3 9 -#define IMX_SC_R_CCI 10 -#define IMX_SC_R_DB 11 -#define IMX_SC_R_DRC_0 12 -#define IMX_SC_R_DRC_1 13 -#define IMX_SC_R_GIC_SMMU 14 -#define IMX_SC_R_IRQSTR_M4_0 15 -#define IMX_SC_R_IRQSTR_M4_1 16 -#define IMX_SC_R_SMMU 17 -#define IMX_SC_R_GIC 18 -#define IMX_SC_R_DC_0_BLIT0 19 -#define IMX_SC_R_DC_0_BLIT1 20 -#define IMX_SC_R_DC_0_BLIT2 21 -#define IMX_SC_R_DC_0_BLIT_OUT 22 -#define IMX_SC_R_PERF 23 -#define IMX_SC_R_DC_0_WARP 25 -#define IMX_SC_R_DC_0_VIDEO0 28 -#define IMX_SC_R_DC_0_VIDEO1 29 -#define IMX_SC_R_DC_0_FRAC0 30 -#define IMX_SC_R_DC_0 32 -#define IMX_SC_R_GPU_2_PID0 33 -#define IMX_SC_R_DC_0_PLL_0 34 -#define IMX_SC_R_DC_0_PLL_1 35 -#define IMX_SC_R_DC_1_BLIT0 36 -#define IMX_SC_R_DC_1_BLIT1 37 -#define IMX_SC_R_DC_1_BLIT2 38 -#define IMX_SC_R_DC_1_BLIT_OUT 39 -#define IMX_SC_R_DC_1_WARP 42 -#define IMX_SC_R_DC_1_VIDEO0 45 -#define IMX_SC_R_DC_1_VIDEO1 46 -#define IMX_SC_R_DC_1_FRAC0 47 -#define IMX_SC_R_DC_1 49 -#define IMX_SC_R_DC_1_PLL_0 51 -#define IMX_SC_R_DC_1_PLL_1 52 -#define IMX_SC_R_SPI_0 53 -#define IMX_SC_R_SPI_1 54 -#define IMX_SC_R_SPI_2 55 -#define IMX_SC_R_SPI_3 56 -#define IMX_SC_R_UART_0 57 -#define IMX_SC_R_UART_1 58 -#define IMX_SC_R_UART_2 59 -#define IMX_SC_R_UART_3 60 -#define IMX_SC_R_UART_4 61 -#define IMX_SC_R_EMVSIM_0 62 -#define IMX_SC_R_EMVSIM_1 63 -#define IMX_SC_R_DMA_0_CH0 64 -#define IMX_SC_R_DMA_0_CH1 65 -#define IMX_SC_R_DMA_0_CH2 66 -#define IMX_SC_R_DMA_0_CH3 67 -#define IMX_SC_R_DMA_0_CH4 68 -#define IMX_SC_R_DMA_0_CH5 69 -#define IMX_SC_R_DMA_0_CH6 70 -#define IMX_SC_R_DMA_0_CH7 71 -#define IMX_SC_R_DMA_0_CH8 72 -#define IMX_SC_R_DMA_0_CH9 73 -#define IMX_SC_R_DMA_0_CH10 74 -#define IMX_SC_R_DMA_0_CH11 75 -#define IMX_SC_R_DMA_0_CH12 76 -#define IMX_SC_R_DMA_0_CH13 77 -#define IMX_SC_R_DMA_0_CH14 78 -#define IMX_SC_R_DMA_0_CH15 79 -#define IMX_SC_R_DMA_0_CH16 80 -#define IMX_SC_R_DMA_0_CH17 81 -#define IMX_SC_R_DMA_0_CH18 82 -#define IMX_SC_R_DMA_0_CH19 83 -#define IMX_SC_R_DMA_0_CH20 84 -#define IMX_SC_R_DMA_0_CH21 85 -#define IMX_SC_R_DMA_0_CH22 86 -#define IMX_SC_R_DMA_0_CH23 87 -#define IMX_SC_R_DMA_0_CH24 88 -#define IMX_SC_R_DMA_0_CH25 89 -#define IMX_SC_R_DMA_0_CH26 90 -#define IMX_SC_R_DMA_0_CH27 91 -#define IMX_SC_R_DMA_0_CH28 92 -#define IMX_SC_R_DMA_0_CH29 93 -#define IMX_SC_R_DMA_0_CH30 94 -#define IMX_SC_R_DMA_0_CH31 95 -#define IMX_SC_R_I2C_0 96 -#define IMX_SC_R_I2C_1 97 -#define IMX_SC_R_I2C_2 98 -#define IMX_SC_R_I2C_3 99 -#define IMX_SC_R_I2C_4 100 -#define IMX_SC_R_ADC_0 101 -#define IMX_SC_R_ADC_1 102 -#define IMX_SC_R_FTM_0 103 -#define IMX_SC_R_FTM_1 104 -#define IMX_SC_R_CAN_0 105 -#define IMX_SC_R_CAN_1 106 -#define IMX_SC_R_CAN_2 107 -#define IMX_SC_R_DMA_1_CH0 108 -#define IMX_SC_R_DMA_1_CH1 109 -#define IMX_SC_R_DMA_1_CH2 110 -#define IMX_SC_R_DMA_1_CH3 111 -#define IMX_SC_R_DMA_1_CH4 112 -#define IMX_SC_R_DMA_1_CH5 113 -#define IMX_SC_R_DMA_1_CH6 114 -#define IMX_SC_R_DMA_1_CH7 115 -#define IMX_SC_R_DMA_1_CH8 116 -#define IMX_SC_R_DMA_1_CH9 117 -#define IMX_SC_R_DMA_1_CH10 118 -#define IMX_SC_R_DMA_1_CH11 119 -#define IMX_SC_R_DMA_1_CH12 120 -#define IMX_SC_R_DMA_1_CH13 121 -#define IMX_SC_R_DMA_1_CH14 122 -#define IMX_SC_R_DMA_1_CH15 123 -#define IMX_SC_R_DMA_1_CH16 124 -#define IMX_SC_R_DMA_1_CH17 125 -#define IMX_SC_R_DMA_1_CH18 126 -#define IMX_SC_R_DMA_1_CH19 127 -#define IMX_SC_R_DMA_1_CH20 128 -#define IMX_SC_R_DMA_1_CH21 129 -#define IMX_SC_R_DMA_1_CH22 130 -#define IMX_SC_R_DMA_1_CH23 131 -#define IMX_SC_R_DMA_1_CH24 132 -#define IMX_SC_R_DMA_1_CH25 133 -#define IMX_SC_R_DMA_1_CH26 134 -#define IMX_SC_R_DMA_1_CH27 135 -#define IMX_SC_R_DMA_1_CH28 136 -#define IMX_SC_R_DMA_1_CH29 137 -#define IMX_SC_R_DMA_1_CH30 138 -#define IMX_SC_R_DMA_1_CH31 139 -#define IMX_SC_R_UNUSED1 140 -#define IMX_SC_R_UNUSED2 141 -#define IMX_SC_R_UNUSED3 142 -#define IMX_SC_R_UNUSED4 143 -#define IMX_SC_R_GPU_0_PID0 144 -#define IMX_SC_R_GPU_0_PID1 145 -#define IMX_SC_R_GPU_0_PID2 146 -#define IMX_SC_R_GPU_0_PID3 147 -#define IMX_SC_R_GPU_1_PID0 148 -#define IMX_SC_R_GPU_1_PID1 149 -#define IMX_SC_R_GPU_1_PID2 150 -#define IMX_SC_R_GPU_1_PID3 151 -#define IMX_SC_R_PCIE_A 152 -#define IMX_SC_R_SERDES_0 153 -#define IMX_SC_R_MATCH_0 154 -#define IMX_SC_R_MATCH_1 155 -#define IMX_SC_R_MATCH_2 156 -#define IMX_SC_R_MATCH_3 157 -#define IMX_SC_R_MATCH_4 158 -#define IMX_SC_R_MATCH_5 159 -#define IMX_SC_R_MATCH_6 160 -#define IMX_SC_R_MATCH_7 161 -#define IMX_SC_R_MATCH_8 162 -#define IMX_SC_R_MATCH_9 163 -#define IMX_SC_R_MATCH_10 164 -#define IMX_SC_R_MATCH_11 165 -#define IMX_SC_R_MATCH_12 166 -#define IMX_SC_R_MATCH_13 167 -#define IMX_SC_R_MATCH_14 168 -#define IMX_SC_R_PCIE_B 169 -#define IMX_SC_R_SATA_0 170 -#define IMX_SC_R_SERDES_1 171 -#define IMX_SC_R_HSIO_GPIO 172 -#define IMX_SC_R_MATCH_15 173 -#define IMX_SC_R_MATCH_16 174 -#define IMX_SC_R_MATCH_17 175 -#define IMX_SC_R_MATCH_18 176 -#define IMX_SC_R_MATCH_19 177 -#define IMX_SC_R_MATCH_20 178 -#define IMX_SC_R_MATCH_21 179 -#define IMX_SC_R_MATCH_22 180 -#define IMX_SC_R_MATCH_23 181 -#define IMX_SC_R_MATCH_24 182 -#define IMX_SC_R_MATCH_25 183 -#define IMX_SC_R_MATCH_26 184 -#define IMX_SC_R_MATCH_27 185 -#define IMX_SC_R_MATCH_28 186 -#define IMX_SC_R_LCD_0 187 -#define IMX_SC_R_LCD_0_PWM_0 188 -#define IMX_SC_R_LCD_0_I2C_0 189 -#define IMX_SC_R_LCD_0_I2C_1 190 -#define IMX_SC_R_PWM_0 191 -#define IMX_SC_R_PWM_1 192 -#define IMX_SC_R_PWM_2 193 -#define IMX_SC_R_PWM_3 194 -#define IMX_SC_R_PWM_4 195 -#define IMX_SC_R_PWM_5 196 -#define IMX_SC_R_PWM_6 197 -#define IMX_SC_R_PWM_7 198 -#define IMX_SC_R_GPIO_0 199 -#define IMX_SC_R_GPIO_1 200 -#define IMX_SC_R_GPIO_2 201 -#define IMX_SC_R_GPIO_3 202 -#define IMX_SC_R_GPIO_4 203 -#define IMX_SC_R_GPIO_5 204 -#define IMX_SC_R_GPIO_6 205 -#define IMX_SC_R_GPIO_7 206 -#define IMX_SC_R_GPT_0 207 -#define IMX_SC_R_GPT_1 208 -#define IMX_SC_R_GPT_2 209 -#define IMX_SC_R_GPT_3 210 -#define IMX_SC_R_GPT_4 211 -#define IMX_SC_R_KPP 212 -#define IMX_SC_R_MU_0A 213 -#define IMX_SC_R_MU_1A 214 -#define IMX_SC_R_MU_2A 215 -#define IMX_SC_R_MU_3A 216 -#define IMX_SC_R_MU_4A 217 -#define IMX_SC_R_MU_5A 218 -#define IMX_SC_R_MU_6A 219 -#define IMX_SC_R_MU_7A 220 -#define IMX_SC_R_MU_8A 221 -#define IMX_SC_R_MU_9A 222 -#define IMX_SC_R_MU_10A 223 -#define IMX_SC_R_MU_11A 224 -#define IMX_SC_R_MU_12A 225 -#define IMX_SC_R_MU_13A 226 -#define IMX_SC_R_MU_5B 227 -#define IMX_SC_R_MU_6B 228 -#define IMX_SC_R_MU_7B 229 -#define IMX_SC_R_MU_8B 230 -#define IMX_SC_R_MU_9B 231 -#define IMX_SC_R_MU_10B 232 -#define IMX_SC_R_MU_11B 233 -#define IMX_SC_R_MU_12B 234 -#define IMX_SC_R_MU_13B 235 -#define IMX_SC_R_ROM_0 236 -#define IMX_SC_R_FSPI_0 237 -#define IMX_SC_R_FSPI_1 238 -#define IMX_SC_R_IEE 239 -#define IMX_SC_R_IEE_R0 240 -#define IMX_SC_R_IEE_R1 241 -#define IMX_SC_R_IEE_R2 242 -#define IMX_SC_R_IEE_R3 243 -#define IMX_SC_R_IEE_R4 244 -#define IMX_SC_R_IEE_R5 245 -#define IMX_SC_R_IEE_R6 246 -#define IMX_SC_R_IEE_R7 247 -#define IMX_SC_R_SDHC_0 248 -#define IMX_SC_R_SDHC_1 249 -#define IMX_SC_R_SDHC_2 250 -#define IMX_SC_R_ENET_0 251 -#define IMX_SC_R_ENET_1 252 -#define IMX_SC_R_MLB_0 253 -#define IMX_SC_R_DMA_2_CH0 254 -#define IMX_SC_R_DMA_2_CH1 255 -#define IMX_SC_R_DMA_2_CH2 256 -#define IMX_SC_R_DMA_2_CH3 257 -#define IMX_SC_R_DMA_2_CH4 258 -#define IMX_SC_R_USB_0 259 -#define IMX_SC_R_USB_1 260 -#define IMX_SC_R_USB_0_PHY 261 -#define IMX_SC_R_USB_2 262 -#define IMX_SC_R_USB_2_PHY 263 -#define IMX_SC_R_DTCP 264 -#define IMX_SC_R_NAND 265 -#define IMX_SC_R_LVDS_0 266 -#define IMX_SC_R_LVDS_0_PWM_0 267 -#define IMX_SC_R_LVDS_0_I2C_0 268 -#define IMX_SC_R_LVDS_0_I2C_1 269 -#define IMX_SC_R_LVDS_1 270 -#define IMX_SC_R_LVDS_1_PWM_0 271 -#define IMX_SC_R_LVDS_1_I2C_0 272 -#define IMX_SC_R_LVDS_1_I2C_1 273 -#define IMX_SC_R_LVDS_2 274 -#define IMX_SC_R_LVDS_2_PWM_0 275 -#define IMX_SC_R_LVDS_2_I2C_0 276 -#define IMX_SC_R_LVDS_2_I2C_1 277 -#define IMX_SC_R_M4_0_PID0 278 -#define IMX_SC_R_M4_0_PID1 279 -#define IMX_SC_R_M4_0_PID2 280 -#define IMX_SC_R_M4_0_PID3 281 -#define IMX_SC_R_M4_0_PID4 282 -#define IMX_SC_R_M4_0_RGPIO 283 -#define IMX_SC_R_M4_0_SEMA42 284 -#define IMX_SC_R_M4_0_TPM 285 -#define IMX_SC_R_M4_0_PIT 286 -#define IMX_SC_R_M4_0_UART 287 -#define IMX_SC_R_M4_0_I2C 288 -#define IMX_SC_R_M4_0_INTMUX 289 -#define IMX_SC_R_M4_0_MU_0B 292 -#define IMX_SC_R_M4_0_MU_0A0 293 -#define IMX_SC_R_M4_0_MU_0A1 294 -#define IMX_SC_R_M4_0_MU_0A2 295 -#define IMX_SC_R_M4_0_MU_0A3 296 -#define IMX_SC_R_M4_0_MU_1A 297 -#define IMX_SC_R_M4_1_PID0 298 -#define IMX_SC_R_M4_1_PID1 299 -#define IMX_SC_R_M4_1_PID2 300 -#define IMX_SC_R_M4_1_PID3 301 -#define IMX_SC_R_M4_1_PID4 302 -#define IMX_SC_R_M4_1_RGPIO 303 -#define IMX_SC_R_M4_1_SEMA42 304 -#define IMX_SC_R_M4_1_TPM 305 -#define IMX_SC_R_M4_1_PIT 306 -#define IMX_SC_R_M4_1_UART 307 -#define IMX_SC_R_M4_1_I2C 308 -#define IMX_SC_R_M4_1_INTMUX 309 -#define IMX_SC_R_M4_1_MU_0B 312 -#define IMX_SC_R_M4_1_MU_0A0 313 -#define IMX_SC_R_M4_1_MU_0A1 314 -#define IMX_SC_R_M4_1_MU_0A2 315 -#define IMX_SC_R_M4_1_MU_0A3 316 -#define IMX_SC_R_M4_1_MU_1A 317 -#define IMX_SC_R_SAI_0 318 -#define IMX_SC_R_SAI_1 319 -#define IMX_SC_R_SAI_2 320 -#define IMX_SC_R_IRQSTR_SCU2 321 -#define IMX_SC_R_IRQSTR_DSP 322 -#define IMX_SC_R_ELCDIF_PLL 323 -#define IMX_SC_R_OCRAM 324 -#define IMX_SC_R_AUDIO_PLL_0 325 -#define IMX_SC_R_PI_0 326 -#define IMX_SC_R_PI_0_PWM_0 327 -#define IMX_SC_R_PI_0_PWM_1 328 -#define IMX_SC_R_PI_0_I2C_0 329 -#define IMX_SC_R_PI_0_PLL 330 -#define IMX_SC_R_PI_1 331 -#define IMX_SC_R_PI_1_PWM_0 332 -#define IMX_SC_R_PI_1_PWM_1 333 -#define IMX_SC_R_PI_1_I2C_0 334 -#define IMX_SC_R_PI_1_PLL 335 -#define IMX_SC_R_SC_PID0 336 -#define IMX_SC_R_SC_PID1 337 -#define IMX_SC_R_SC_PID2 338 -#define IMX_SC_R_SC_PID3 339 -#define IMX_SC_R_SC_PID4 340 -#define IMX_SC_R_SC_SEMA42 341 -#define IMX_SC_R_SC_TPM 342 -#define IMX_SC_R_SC_PIT 343 -#define IMX_SC_R_SC_UART 344 -#define IMX_SC_R_SC_I2C 345 -#define IMX_SC_R_SC_MU_0B 346 -#define IMX_SC_R_SC_MU_0A0 347 -#define IMX_SC_R_SC_MU_0A1 348 -#define IMX_SC_R_SC_MU_0A2 349 -#define IMX_SC_R_SC_MU_0A3 350 -#define IMX_SC_R_SC_MU_1A 351 -#define IMX_SC_R_SYSCNT_RD 352 -#define IMX_SC_R_SYSCNT_CMP 353 -#define IMX_SC_R_DEBUG 354 -#define IMX_SC_R_SYSTEM 355 -#define IMX_SC_R_SNVS 356 -#define IMX_SC_R_OTP 357 -#define IMX_SC_R_VPU_PID0 358 -#define IMX_SC_R_VPU_PID1 359 -#define IMX_SC_R_VPU_PID2 360 -#define IMX_SC_R_VPU_PID3 361 -#define IMX_SC_R_VPU_PID4 362 -#define IMX_SC_R_VPU_PID5 363 -#define IMX_SC_R_VPU_PID6 364 -#define IMX_SC_R_VPU_PID7 365 -#define IMX_SC_R_VPU_UART 366 -#define IMX_SC_R_VPUCORE 367 -#define IMX_SC_R_VPUCORE_0 368 -#define IMX_SC_R_VPUCORE_1 369 -#define IMX_SC_R_VPUCORE_2 370 -#define IMX_SC_R_VPUCORE_3 371 -#define IMX_SC_R_DMA_4_CH0 372 -#define IMX_SC_R_DMA_4_CH1 373 -#define IMX_SC_R_DMA_4_CH2 374 -#define IMX_SC_R_DMA_4_CH3 375 -#define IMX_SC_R_DMA_4_CH4 376 -#define IMX_SC_R_ISI_CH0 377 -#define IMX_SC_R_ISI_CH1 378 -#define IMX_SC_R_ISI_CH2 379 -#define IMX_SC_R_ISI_CH3 380 -#define IMX_SC_R_ISI_CH4 381 -#define IMX_SC_R_ISI_CH5 382 -#define IMX_SC_R_ISI_CH6 383 -#define IMX_SC_R_ISI_CH7 384 -#define IMX_SC_R_MJPEG_DEC_S0 385 -#define IMX_SC_R_MJPEG_DEC_S1 386 -#define IMX_SC_R_MJPEG_DEC_S2 387 -#define IMX_SC_R_MJPEG_DEC_S3 388 -#define IMX_SC_R_MJPEG_ENC_S0 389 -#define IMX_SC_R_MJPEG_ENC_S1 390 -#define IMX_SC_R_MJPEG_ENC_S2 391 -#define IMX_SC_R_MJPEG_ENC_S3 392 -#define IMX_SC_R_MIPI_0 393 -#define IMX_SC_R_MIPI_0_PWM_0 394 -#define IMX_SC_R_MIPI_0_I2C_0 395 -#define IMX_SC_R_MIPI_0_I2C_1 396 -#define IMX_SC_R_MIPI_1 397 -#define IMX_SC_R_MIPI_1_PWM_0 398 -#define IMX_SC_R_MIPI_1_I2C_0 399 -#define IMX_SC_R_MIPI_1_I2C_1 400 -#define IMX_SC_R_CSI_0 401 -#define IMX_SC_R_CSI_0_PWM_0 402 -#define IMX_SC_R_CSI_0_I2C_0 403 -#define IMX_SC_R_CSI_1 404 -#define IMX_SC_R_CSI_1_PWM_0 405 -#define IMX_SC_R_CSI_1_I2C_0 406 -#define IMX_SC_R_HDMI 407 -#define IMX_SC_R_HDMI_I2S 408 -#define IMX_SC_R_HDMI_I2C_0 409 -#define IMX_SC_R_HDMI_PLL_0 410 -#define IMX_SC_R_HDMI_RX 411 -#define IMX_SC_R_HDMI_RX_BYPASS 412 -#define IMX_SC_R_HDMI_RX_I2C_0 413 -#define IMX_SC_R_ASRC_0 414 -#define IMX_SC_R_ESAI_0 415 -#define IMX_SC_R_SPDIF_0 416 -#define IMX_SC_R_SPDIF_1 417 -#define IMX_SC_R_SAI_3 418 -#define IMX_SC_R_SAI_4 419 -#define IMX_SC_R_SAI_5 420 -#define IMX_SC_R_GPT_5 421 -#define IMX_SC_R_GPT_6 422 -#define IMX_SC_R_GPT_7 423 -#define IMX_SC_R_GPT_8 424 -#define IMX_SC_R_GPT_9 425 -#define IMX_SC_R_GPT_10 426 -#define IMX_SC_R_DMA_2_CH5 427 -#define IMX_SC_R_DMA_2_CH6 428 -#define IMX_SC_R_DMA_2_CH7 429 -#define IMX_SC_R_DMA_2_CH8 430 -#define IMX_SC_R_DMA_2_CH9 431 -#define IMX_SC_R_DMA_2_CH10 432 -#define IMX_SC_R_DMA_2_CH11 433 -#define IMX_SC_R_DMA_2_CH12 434 -#define IMX_SC_R_DMA_2_CH13 435 -#define IMX_SC_R_DMA_2_CH14 436 -#define IMX_SC_R_DMA_2_CH15 437 -#define IMX_SC_R_DMA_2_CH16 438 -#define IMX_SC_R_DMA_2_CH17 439 -#define IMX_SC_R_DMA_2_CH18 440 -#define IMX_SC_R_DMA_2_CH19 441 -#define IMX_SC_R_DMA_2_CH20 442 -#define IMX_SC_R_DMA_2_CH21 443 -#define IMX_SC_R_DMA_2_CH22 444 -#define IMX_SC_R_DMA_2_CH23 445 -#define IMX_SC_R_DMA_2_CH24 446 -#define IMX_SC_R_DMA_2_CH25 447 -#define IMX_SC_R_DMA_2_CH26 448 -#define IMX_SC_R_DMA_2_CH27 449 -#define IMX_SC_R_DMA_2_CH28 450 -#define IMX_SC_R_DMA_2_CH29 451 -#define IMX_SC_R_DMA_2_CH30 452 -#define IMX_SC_R_DMA_2_CH31 453 -#define IMX_SC_R_ASRC_1 454 -#define IMX_SC_R_ESAI_1 455 -#define IMX_SC_R_SAI_6 456 -#define IMX_SC_R_SAI_7 457 -#define IMX_SC_R_AMIX 458 -#define IMX_SC_R_MQS_0 459 -#define IMX_SC_R_DMA_3_CH0 460 -#define IMX_SC_R_DMA_3_CH1 461 -#define IMX_SC_R_DMA_3_CH2 462 -#define IMX_SC_R_DMA_3_CH3 463 -#define IMX_SC_R_DMA_3_CH4 464 -#define IMX_SC_R_DMA_3_CH5 465 -#define IMX_SC_R_DMA_3_CH6 466 -#define IMX_SC_R_DMA_3_CH7 467 -#define IMX_SC_R_DMA_3_CH8 468 -#define IMX_SC_R_DMA_3_CH9 469 -#define IMX_SC_R_DMA_3_CH10 470 -#define IMX_SC_R_DMA_3_CH11 471 -#define IMX_SC_R_DMA_3_CH12 472 -#define IMX_SC_R_DMA_3_CH13 473 -#define IMX_SC_R_DMA_3_CH14 474 -#define IMX_SC_R_DMA_3_CH15 475 -#define IMX_SC_R_DMA_3_CH16 476 -#define IMX_SC_R_DMA_3_CH17 477 -#define IMX_SC_R_DMA_3_CH18 478 -#define IMX_SC_R_DMA_3_CH19 479 -#define IMX_SC_R_DMA_3_CH20 480 -#define IMX_SC_R_DMA_3_CH21 481 -#define IMX_SC_R_DMA_3_CH22 482 -#define IMX_SC_R_DMA_3_CH23 483 -#define IMX_SC_R_DMA_3_CH24 484 -#define IMX_SC_R_DMA_3_CH25 485 -#define IMX_SC_R_DMA_3_CH26 486 -#define IMX_SC_R_DMA_3_CH27 487 -#define IMX_SC_R_DMA_3_CH28 488 -#define IMX_SC_R_DMA_3_CH29 489 -#define IMX_SC_R_DMA_3_CH30 490 -#define IMX_SC_R_DMA_3_CH31 491 -#define IMX_SC_R_AUDIO_PLL_1 492 -#define IMX_SC_R_AUDIO_CLK_0 493 -#define IMX_SC_R_AUDIO_CLK_1 494 -#define IMX_SC_R_MCLK_OUT_0 495 -#define IMX_SC_R_MCLK_OUT_1 496 -#define IMX_SC_R_PMIC_0 497 -#define IMX_SC_R_PMIC_1 498 -#define IMX_SC_R_SECO 499 -#define IMX_SC_R_CAAM_JR1 500 -#define IMX_SC_R_CAAM_JR2 501 -#define IMX_SC_R_CAAM_JR3 502 -#define IMX_SC_R_SECO_MU_2 503 -#define IMX_SC_R_SECO_MU_3 504 -#define IMX_SC_R_SECO_MU_4 505 -#define IMX_SC_R_HDMI_RX_PWM_0 506 -#define IMX_SC_R_A35 507 -#define IMX_SC_R_A35_0 508 -#define IMX_SC_R_A35_1 509 -#define IMX_SC_R_A35_2 510 -#define IMX_SC_R_A35_3 511 -#define IMX_SC_R_DSP 512 -#define IMX_SC_R_DSP_RAM 513 -#define IMX_SC_R_CAAM_JR1_OUT 514 -#define IMX_SC_R_CAAM_JR2_OUT 515 -#define IMX_SC_R_CAAM_JR3_OUT 516 -#define IMX_SC_R_VPU_DEC_0 517 -#define IMX_SC_R_VPU_ENC_0 518 -#define IMX_SC_R_CAAM_JR0 519 -#define IMX_SC_R_CAAM_JR0_OUT 520 -#define IMX_SC_R_PMIC_2 521 -#define IMX_SC_R_DBLOGIC 522 -#define IMX_SC_R_HDMI_PLL_1 523 -#define IMX_SC_R_BOARD_R0 524 -#define IMX_SC_R_BOARD_R1 525 -#define IMX_SC_R_BOARD_R2 526 -#define IMX_SC_R_BOARD_R3 527 -#define IMX_SC_R_BOARD_R4 528 -#define IMX_SC_R_BOARD_R5 529 -#define IMX_SC_R_BOARD_R6 530 -#define IMX_SC_R_BOARD_R7 531 -#define IMX_SC_R_MJPEG_DEC_MP 532 -#define IMX_SC_R_MJPEG_ENC_MP 533 -#define IMX_SC_R_VPU_TS_0 534 -#define IMX_SC_R_VPU_MU_0 535 -#define IMX_SC_R_VPU_MU_1 536 -#define IMX_SC_R_VPU_MU_2 537 -#define IMX_SC_R_VPU_MU_3 538 -#define IMX_SC_R_VPU_ENC_1 539 -#define IMX_SC_R_VPU 540 -#define IMX_SC_R_DMA_5_CH0 541 -#define IMX_SC_R_DMA_5_CH1 542 -#define IMX_SC_R_DMA_5_CH2 543 -#define IMX_SC_R_DMA_5_CH3 544 -#define IMX_SC_R_ATTESTATION 545 -#define IMX_SC_R_LAST 546 - -#endif /* __DT_BINDINGS_RSCRC_IMX_H */ diff --git a/sys/gnu/dts/include/dt-bindings/gce/mt8173-gce.h b/sys/gnu/dts/include/dt-bindings/gce/mt8173-gce.h deleted file mode 100644 index ffcf94ba96c..00000000000 --- a/sys/gnu/dts/include/dt-bindings/gce/mt8173-gce.h +++ /dev/null @@ -1,44 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2018 MediaTek Inc. - * Author: Houlong Wei - * - */ - -#ifndef _DT_BINDINGS_GCE_MT8173_H -#define _DT_BINDINGS_GCE_MT8173_H - -/* GCE HW thread priority */ -#define CMDQ_THR_PRIO_LOWEST 0 -#define CMDQ_THR_PRIO_HIGHEST 1 - -/* GCE SUBSYS */ -#define SUBSYS_1400XXXX 1 -#define SUBSYS_1401XXXX 2 -#define SUBSYS_1402XXXX 3 - -/* GCE HW EVENT */ -#define CMDQ_EVENT_DISP_OVL0_SOF 11 -#define CMDQ_EVENT_DISP_OVL1_SOF 12 -#define CMDQ_EVENT_DISP_RDMA0_SOF 13 -#define CMDQ_EVENT_DISP_RDMA1_SOF 14 -#define CMDQ_EVENT_DISP_RDMA2_SOF 15 -#define CMDQ_EVENT_DISP_WDMA0_SOF 16 -#define CMDQ_EVENT_DISP_WDMA1_SOF 17 -#define CMDQ_EVENT_DISP_OVL0_EOF 39 -#define CMDQ_EVENT_DISP_OVL1_EOF 40 -#define CMDQ_EVENT_DISP_RDMA0_EOF 41 -#define CMDQ_EVENT_DISP_RDMA1_EOF 42 -#define CMDQ_EVENT_DISP_RDMA2_EOF 43 -#define CMDQ_EVENT_DISP_WDMA0_EOF 44 -#define CMDQ_EVENT_DISP_WDMA1_EOF 45 -#define CMDQ_EVENT_MUTEX0_STREAM_EOF 53 -#define CMDQ_EVENT_MUTEX1_STREAM_EOF 54 -#define CMDQ_EVENT_MUTEX2_STREAM_EOF 55 -#define CMDQ_EVENT_MUTEX3_STREAM_EOF 56 -#define CMDQ_EVENT_MUTEX4_STREAM_EOF 57 -#define CMDQ_EVENT_DISP_RDMA0_UNDERRUN 63 -#define CMDQ_EVENT_DISP_RDMA1_UNDERRUN 64 -#define CMDQ_EVENT_DISP_RDMA2_UNDERRUN 65 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/gce/mt8183-gce.h b/sys/gnu/dts/include/dt-bindings/gce/mt8183-gce.h deleted file mode 100644 index 29c967476f7..00000000000 --- a/sys/gnu/dts/include/dt-bindings/gce/mt8183-gce.h +++ /dev/null @@ -1,175 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2019 MediaTek Inc. - * Author: Bibby Hsieh - * - */ - -#ifndef _DT_BINDINGS_GCE_MT8183_H -#define _DT_BINDINGS_GCE_MT8183_H - -#define CMDQ_NO_TIMEOUT 0xffffffff - -/* GCE HW thread priority */ -#define CMDQ_THR_PRIO_LOWEST 0 -#define CMDQ_THR_PRIO_HIGHEST 1 - -/* GCE SUBSYS */ -#define SUBSYS_1300XXXX 0 -#define SUBSYS_1400XXXX 1 -#define SUBSYS_1401XXXX 2 -#define SUBSYS_1402XXXX 3 -#define SUBSYS_1502XXXX 4 -#define SUBSYS_1880XXXX 5 -#define SUBSYS_1881XXXX 6 -#define SUBSYS_1882XXXX 7 -#define SUBSYS_1883XXXX 8 -#define SUBSYS_1884XXXX 9 -#define SUBSYS_1000XXXX 10 -#define SUBSYS_1001XXXX 11 -#define SUBSYS_1002XXXX 12 -#define SUBSYS_1003XXXX 13 -#define SUBSYS_1004XXXX 14 -#define SUBSYS_1005XXXX 15 -#define SUBSYS_1020XXXX 16 -#define SUBSYS_1028XXXX 17 -#define SUBSYS_1700XXXX 18 -#define SUBSYS_1701XXXX 19 -#define SUBSYS_1702XXXX 20 -#define SUBSYS_1703XXXX 21 -#define SUBSYS_1800XXXX 22 -#define SUBSYS_1801XXXX 23 -#define SUBSYS_1802XXXX 24 -#define SUBSYS_1804XXXX 25 -#define SUBSYS_1805XXXX 26 -#define SUBSYS_1808XXXX 27 -#define SUBSYS_180aXXXX 28 -#define SUBSYS_180bXXXX 29 - -#define CMDQ_EVENT_DISP_RDMA0_SOF 0 -#define CMDQ_EVENT_DISP_RDMA1_SOF 1 -#define CMDQ_EVENT_MDP_RDMA0_SOF 2 -#define CMDQ_EVENT_MDP_RSZ0_SOF 4 -#define CMDQ_EVENT_MDP_RSZ1_SOF 5 -#define CMDQ_EVENT_MDP_TDSHP_SOF 6 -#define CMDQ_EVENT_MDP_WROT0_SOF 7 -#define CMDQ_EVENT_MDP_WDMA0_SOF 8 -#define CMDQ_EVENT_DISP_OVL0_SOF 9 -#define CMDQ_EVENT_DISP_OVL0_2L_SOF 10 -#define CMDQ_EVENT_DISP_OVL1_2L_SOF 11 -#define CMDQ_EVENT_DISP_WDMA0_SOF 12 -#define CMDQ_EVENT_DISP_COLOR0_SOF 13 -#define CMDQ_EVENT_DISP_CCORR0_SOF 14 -#define CMDQ_EVENT_DISP_AAL0_SOF 15 -#define CMDQ_EVENT_DISP_GAMMA0_SOF 16 -#define CMDQ_EVENT_DISP_DITHER0_SOF 17 -#define CMDQ_EVENT_DISP_PWM0_SOF 18 -#define CMDQ_EVENT_DISP_DSI0_SOF 19 -#define CMDQ_EVENT_DISP_DPI0_SOF 20 -#define CMDQ_EVENT_DISP_RSZ_SOF 22 -#define CMDQ_EVENT_MDP_AAL_SOF 23 -#define CMDQ_EVENT_MDP_CCORR_SOF 24 -#define CMDQ_EVENT_DISP_DBI_SOF 25 -#define CMDQ_EVENT_DISP_RDMA0_EOF 26 -#define CMDQ_EVENT_DISP_RDMA1_EOF 27 -#define CMDQ_EVENT_MDP_RDMA0_EOF 28 -#define CMDQ_EVENT_MDP_RSZ0_EOF 30 -#define CMDQ_EVENT_MDP_RSZ1_EOF 31 -#define CMDQ_EVENT_MDP_TDSHP_EOF 32 -#define CMDQ_EVENT_MDP_WROT0_EOF 33 -#define CMDQ_EVENT_MDP_WDMA0_EOF 34 -#define CMDQ_EVENT_DISP_OVL0_EOF 35 -#define CMDQ_EVENT_DISP_OVL0_2L_EOF 36 -#define CMDQ_EVENT_DISP_OVL1_2L_EOF 37 -#define CMDQ_EVENT_DISP_WDMA0_EOF 38 -#define CMDQ_EVENT_DISP_COLOR0_EOF 39 -#define CMDQ_EVENT_DISP_CCORR0_EOF 40 -#define CMDQ_EVENT_DISP_AAL0_EOF 41 -#define CMDQ_EVENT_DISP_GAMMA0_EOF 42 -#define CMDQ_EVENT_DISP_DITHER0_EOF 43 -#define CMDQ_EVENT_DSI0_EOF 44 -#define CMDQ_EVENT_DPI0_EOF 45 -#define CMDQ_EVENT_DISP_RSZ_EOF 47 -#define CMDQ_EVENT_MDP_AAL_EOF 48 -#define CMDQ_EVENT_MDP_CCORR_EOF 49 -#define CMDQ_EVENT_DBI_EOF 50 -#define CMDQ_EVENT_MUTEX_STREAM_DONE0 130 -#define CMDQ_EVENT_MUTEX_STREAM_DONE1 131 -#define CMDQ_EVENT_MUTEX_STREAM_DONE2 132 -#define CMDQ_EVENT_MUTEX_STREAM_DONE3 133 -#define CMDQ_EVENT_MUTEX_STREAM_DONE4 134 -#define CMDQ_EVENT_MUTEX_STREAM_DONE5 135 -#define CMDQ_EVENT_MUTEX_STREAM_DONE6 136 -#define CMDQ_EVENT_MUTEX_STREAM_DONE7 137 -#define CMDQ_EVENT_MUTEX_STREAM_DONE8 138 -#define CMDQ_EVENT_MUTEX_STREAM_DONE9 139 -#define CMDQ_EVENT_MUTEX_STREAM_DONE10 140 -#define CMDQ_EVENT_MUTEX_STREAM_DONE11 141 -#define CMDQ_EVENT_DISP_RDMA0_BUF_UNDERRUN_EVEN 142 -#define CMDQ_EVENT_DISP_RDMA1_BUF_UNDERRUN_EVEN 143 -#define CMDQ_EVENT_DSI0_TE_EVENT 144 -#define CMDQ_EVENT_DSI0_IRQ_EVENT 145 -#define CMDQ_EVENT_DSI0_DONE_EVENT 146 -#define CMDQ_EVENT_DISP_WDMA0_SW_RST_DONE 150 -#define CMDQ_EVENT_MDP_WDMA_SW_RST_DONE 151 -#define CMDQ_EVENT_MDP_WROT0_SW_RST_DONE 152 -#define CMDQ_EVENT_MDP_RDMA0_SW_RST_DONE 154 -#define CMDQ_EVENT_DISP_OVL0_FRAME_RST_DONE_PULE 155 -#define CMDQ_EVENT_DISP_OVL0_2L_FRAME_RST_DONE_ULSE 156 -#define CMDQ_EVENT_DISP_OVL1_2L_FRAME_RST_DONE_ULSE 157 -#define CMDQ_EVENT_ISP_FRAME_DONE_P2_0 257 -#define CMDQ_EVENT_ISP_FRAME_DONE_P2_1 258 -#define CMDQ_EVENT_ISP_FRAME_DONE_P2_2 259 -#define CMDQ_EVENT_ISP_FRAME_DONE_P2_3 260 -#define CMDQ_EVENT_ISP_FRAME_DONE_P2_4 261 -#define CMDQ_EVENT_ISP_FRAME_DONE_P2_5 262 -#define CMDQ_EVENT_ISP_FRAME_DONE_P2_6 263 -#define CMDQ_EVENT_ISP_FRAME_DONE_P2_7 264 -#define CMDQ_EVENT_ISP_FRAME_DONE_P2_8 265 -#define CMDQ_EVENT_ISP_FRAME_DONE_P2_9 266 -#define CMDQ_EVENT_ISP_FRAME_DONE_P2_10 267 -#define CMDQ_EVENT_ISP_FRAME_DONE_P2_11 268 -#define CMDQ_EVENT_ISP_FRAME_DONE_P2_12 269 -#define CMDQ_EVENT_ISP_FRAME_DONE_P2_13 270 -#define CMDQ_EVENT_ISP_FRAME_DONE_P2_14 271 -#define CMDQ_EVENT_ISP_FRAME_DONE_P2_15 272 -#define CMDQ_EVENT_ISP_FRAME_DONE_P2_16 273 -#define CMDQ_EVENT_ISP_FRAME_DONE_P2_17 274 -#define CMDQ_EVENT_ISP_FRAME_DONE_P2_18 275 -#define CMDQ_EVENT_AMD_FRAME_DONE 276 -#define CMDQ_EVENT_DVE_DONE 277 -#define CMDQ_EVENT_WMFE_DONE 278 -#define CMDQ_EVENT_RSC_DONE 279 -#define CMDQ_EVENT_MFB_DONE 280 -#define CMDQ_EVENT_WPE_A_DONE 281 -#define CMDQ_EVENT_SPE_B_DONE 282 -#define CMDQ_EVENT_OCC_DONE 283 -#define CMDQ_EVENT_VENC_CMDQ_FRAME_DONE 289 -#define CMDQ_EVENT_JPG_ENC_CMDQ_DONE 290 -#define CMDQ_EVENT_JPG_DEC_CMDQ_DONE 291 -#define CMDQ_EVENT_VENC_CMDQ_MB_DONE 292 -#define CMDQ_EVENT_VENC_CMDQ_128BYTE_DONE 293 -#define CMDQ_EVENT_ISP_FRAME_DONE_A 321 -#define CMDQ_EVENT_ISP_FRAME_DONE_B 322 -#define CMDQ_EVENT_CAMSV0_PASS1_DONE 323 -#define CMDQ_EVENT_CAMSV1_PASS1_DONE 324 -#define CMDQ_EVENT_CAMSV2_PASS1_DONE 325 -#define CMDQ_EVENT_TSF_DONE 326 -#define CMDQ_EVENT_SENINF_CAM0_FIFO_FULL 327 -#define CMDQ_EVENT_SENINF_CAM1_FIFO_FULL 328 -#define CMDQ_EVENT_SENINF_CAM2_FIFO_FULL 329 -#define CMDQ_EVENT_SENINF_CAM3_FIFO_FULL 330 -#define CMDQ_EVENT_SENINF_CAM4_FIFO_FULL 331 -#define CMDQ_EVENT_SENINF_CAM5_FIFO_FULL 332 -#define CMDQ_EVENT_SENINF_CAM6_FIFO_FULL 333 -#define CMDQ_EVENT_SENINF_CAM7_FIFO_FULL 334 -#define CMDQ_EVENT_IPU_CORE0_DONE0 353 -#define CMDQ_EVENT_IPU_CORE0_DONE1 354 -#define CMDQ_EVENT_IPU_CORE0_DONE2 355 -#define CMDQ_EVENT_IPU_CORE0_DONE3 356 -#define CMDQ_EVENT_IPU_CORE1_DONE0 385 -#define CMDQ_EVENT_IPU_CORE1_DONE1 386 -#define CMDQ_EVENT_IPU_CORE1_DONE2 387 -#define CMDQ_EVENT_IPU_CORE1_DONE3 388 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/gpio/aspeed-gpio.h b/sys/gnu/dts/include/dt-bindings/gpio/aspeed-gpio.h deleted file mode 100644 index 56fc4889b2c..00000000000 --- a/sys/gnu/dts/include/dt-bindings/gpio/aspeed-gpio.h +++ /dev/null @@ -1,49 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * This header provides constants for binding aspeed,*-gpio. - * - * The first cell in Aspeed's GPIO specifier is the GPIO ID. The macros below - * provide names for this. - * - * The second cell contains standard flag values specified in gpio.h. - */ - -#ifndef _DT_BINDINGS_GPIO_ASPEED_GPIO_H -#define _DT_BINDINGS_GPIO_ASPEED_GPIO_H - -#include - -#define ASPEED_GPIO_PORT_A 0 -#define ASPEED_GPIO_PORT_B 1 -#define ASPEED_GPIO_PORT_C 2 -#define ASPEED_GPIO_PORT_D 3 -#define ASPEED_GPIO_PORT_E 4 -#define ASPEED_GPIO_PORT_F 5 -#define ASPEED_GPIO_PORT_G 6 -#define ASPEED_GPIO_PORT_H 7 -#define ASPEED_GPIO_PORT_I 8 -#define ASPEED_GPIO_PORT_J 9 -#define ASPEED_GPIO_PORT_K 10 -#define ASPEED_GPIO_PORT_L 11 -#define ASPEED_GPIO_PORT_M 12 -#define ASPEED_GPIO_PORT_N 13 -#define ASPEED_GPIO_PORT_O 14 -#define ASPEED_GPIO_PORT_P 15 -#define ASPEED_GPIO_PORT_Q 16 -#define ASPEED_GPIO_PORT_R 17 -#define ASPEED_GPIO_PORT_S 18 -#define ASPEED_GPIO_PORT_T 19 -#define ASPEED_GPIO_PORT_U 20 -#define ASPEED_GPIO_PORT_V 21 -#define ASPEED_GPIO_PORT_W 22 -#define ASPEED_GPIO_PORT_X 23 -#define ASPEED_GPIO_PORT_Y 24 -#define ASPEED_GPIO_PORT_Z 25 -#define ASPEED_GPIO_PORT_AA 26 -#define ASPEED_GPIO_PORT_AB 27 -#define ASPEED_GPIO_PORT_AC 28 - -#define ASPEED_GPIO(port, offset) \ - ((ASPEED_GPIO_PORT_##port * 8) + offset) - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/gpio/gpio.h b/sys/gnu/dts/include/dt-bindings/gpio/gpio.h deleted file mode 100644 index c029467e828..00000000000 --- a/sys/gnu/dts/include/dt-bindings/gpio/gpio.h +++ /dev/null @@ -1,42 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides constants for most GPIO bindings. - * - * Most GPIO bindings include a flags cell as part of the GPIO specifier. - * In most cases, the format of the flags cell uses the standard values - * defined in this header. - */ - -#ifndef _DT_BINDINGS_GPIO_GPIO_H -#define _DT_BINDINGS_GPIO_GPIO_H - -/* Bit 0 express polarity */ -#define GPIO_ACTIVE_HIGH 0 -#define GPIO_ACTIVE_LOW 1 - -/* Bit 1 express single-endedness */ -#define GPIO_PUSH_PULL 0 -#define GPIO_SINGLE_ENDED 2 - -/* Bit 2 express Open drain or open source */ -#define GPIO_LINE_OPEN_SOURCE 0 -#define GPIO_LINE_OPEN_DRAIN 4 - -/* - * Open Drain/Collector is the combination of single-ended open drain interface. - * Open Source/Emitter is the combination of single-ended open source interface. - */ -#define GPIO_OPEN_DRAIN (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_DRAIN) -#define GPIO_OPEN_SOURCE (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_SOURCE) - -/* Bit 3 express GPIO suspend/resume and reset persistence */ -#define GPIO_PERSISTENT 0 -#define GPIO_TRANSITORY 8 - -/* Bit 4 express pull up */ -#define GPIO_PULL_UP 16 - -/* Bit 5 express pull down */ -#define GPIO_PULL_DOWN 32 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/gpio/meson-a1-gpio.h b/sys/gnu/dts/include/dt-bindings/gpio/meson-a1-gpio.h deleted file mode 100644 index 40e57a5ff1d..00000000000 --- a/sys/gnu/dts/include/dt-bindings/gpio/meson-a1-gpio.h +++ /dev/null @@ -1,73 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ -/* - * Copyright (c) 2019 Amlogic, Inc. All rights reserved. - * Author: Qianggui Song - */ - -#ifndef _DT_BINDINGS_MESON_A1_GPIO_H -#define _DT_BINDINGS_MESON_A1_GPIO_H - -#define GPIOP_0 0 -#define GPIOP_1 1 -#define GPIOP_2 2 -#define GPIOP_3 3 -#define GPIOP_4 4 -#define GPIOP_5 5 -#define GPIOP_6 6 -#define GPIOP_7 7 -#define GPIOP_8 8 -#define GPIOP_9 9 -#define GPIOP_10 10 -#define GPIOP_11 11 -#define GPIOP_12 12 -#define GPIOB_0 13 -#define GPIOB_1 14 -#define GPIOB_2 15 -#define GPIOB_3 16 -#define GPIOB_4 17 -#define GPIOB_5 18 -#define GPIOB_6 19 -#define GPIOX_0 20 -#define GPIOX_1 21 -#define GPIOX_2 22 -#define GPIOX_3 23 -#define GPIOX_4 24 -#define GPIOX_5 25 -#define GPIOX_6 26 -#define GPIOX_7 27 -#define GPIOX_8 28 -#define GPIOX_9 29 -#define GPIOX_10 30 -#define GPIOX_11 31 -#define GPIOX_12 32 -#define GPIOX_13 33 -#define GPIOX_14 34 -#define GPIOX_15 35 -#define GPIOX_16 36 -#define GPIOF_0 37 -#define GPIOF_1 38 -#define GPIOF_2 39 -#define GPIOF_3 40 -#define GPIOF_4 41 -#define GPIOF_5 42 -#define GPIOF_6 43 -#define GPIOF_7 44 -#define GPIOF_8 45 -#define GPIOF_9 46 -#define GPIOF_10 47 -#define GPIOF_11 48 -#define GPIOF_12 49 -#define GPIOA_0 50 -#define GPIOA_1 51 -#define GPIOA_2 52 -#define GPIOA_3 53 -#define GPIOA_4 54 -#define GPIOA_5 55 -#define GPIOA_6 56 -#define GPIOA_7 57 -#define GPIOA_8 58 -#define GPIOA_9 59 -#define GPIOA_10 60 -#define GPIOA_11 61 - -#endif /* _DT_BINDINGS_MESON_A1_GPIO_H */ diff --git a/sys/gnu/dts/include/dt-bindings/gpio/meson-axg-gpio.h b/sys/gnu/dts/include/dt-bindings/gpio/meson-axg-gpio.h deleted file mode 100644 index 25bb1fffa97..00000000000 --- a/sys/gnu/dts/include/dt-bindings/gpio/meson-axg-gpio.h +++ /dev/null @@ -1,116 +0,0 @@ -/* - * Copyright (c) 2017 Amlogic, Inc. All rights reserved. - * Author: Xingyu Chen - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _DT_BINDINGS_MESON_AXG_GPIO_H -#define _DT_BINDINGS_MESON_AXG_GPIO_H - -/* First GPIO chip */ -#define GPIOAO_0 0 -#define GPIOAO_1 1 -#define GPIOAO_2 2 -#define GPIOAO_3 3 -#define GPIOAO_4 4 -#define GPIOAO_5 5 -#define GPIOAO_6 6 -#define GPIOAO_7 7 -#define GPIOAO_8 8 -#define GPIOAO_9 9 -#define GPIOAO_10 10 -#define GPIOAO_11 11 -#define GPIOAO_12 12 -#define GPIOAO_13 13 -#define GPIO_TEST_N 14 - -/* Second GPIO chip */ -#define GPIOZ_0 0 -#define GPIOZ_1 1 -#define GPIOZ_2 2 -#define GPIOZ_3 3 -#define GPIOZ_4 4 -#define GPIOZ_5 5 -#define GPIOZ_6 6 -#define GPIOZ_7 7 -#define GPIOZ_8 8 -#define GPIOZ_9 9 -#define GPIOZ_10 10 -#define BOOT_0 11 -#define BOOT_1 12 -#define BOOT_2 13 -#define BOOT_3 14 -#define BOOT_4 15 -#define BOOT_5 16 -#define BOOT_6 17 -#define BOOT_7 18 -#define BOOT_8 19 -#define BOOT_9 20 -#define BOOT_10 21 -#define BOOT_11 22 -#define BOOT_12 23 -#define BOOT_13 24 -#define BOOT_14 25 -#define GPIOA_0 26 -#define GPIOA_1 27 -#define GPIOA_2 28 -#define GPIOA_3 29 -#define GPIOA_4 30 -#define GPIOA_5 31 -#define GPIOA_6 32 -#define GPIOA_7 33 -#define GPIOA_8 34 -#define GPIOA_9 35 -#define GPIOA_10 36 -#define GPIOA_11 37 -#define GPIOA_12 38 -#define GPIOA_13 39 -#define GPIOA_14 40 -#define GPIOA_15 41 -#define GPIOA_16 42 -#define GPIOA_17 43 -#define GPIOA_18 44 -#define GPIOA_19 45 -#define GPIOA_20 46 -#define GPIOX_0 47 -#define GPIOX_1 48 -#define GPIOX_2 49 -#define GPIOX_3 50 -#define GPIOX_4 51 -#define GPIOX_5 52 -#define GPIOX_6 53 -#define GPIOX_7 54 -#define GPIOX_8 55 -#define GPIOX_9 56 -#define GPIOX_10 57 -#define GPIOX_11 58 -#define GPIOX_12 59 -#define GPIOX_13 60 -#define GPIOX_14 61 -#define GPIOX_15 62 -#define GPIOX_16 63 -#define GPIOX_17 64 -#define GPIOX_18 65 -#define GPIOX_19 66 -#define GPIOX_20 67 -#define GPIOX_21 68 -#define GPIOX_22 69 -#define GPIOY_0 70 -#define GPIOY_1 71 -#define GPIOY_2 72 -#define GPIOY_3 73 -#define GPIOY_4 74 -#define GPIOY_5 75 -#define GPIOY_6 76 -#define GPIOY_7 77 -#define GPIOY_8 78 -#define GPIOY_9 79 -#define GPIOY_10 80 -#define GPIOY_11 81 -#define GPIOY_12 82 -#define GPIOY_13 83 -#define GPIOY_14 84 -#define GPIOY_15 85 - -#endif /* _DT_BINDINGS_MESON_AXG_GPIO_H */ diff --git a/sys/gnu/dts/include/dt-bindings/gpio/meson-g12a-gpio.h b/sys/gnu/dts/include/dt-bindings/gpio/meson-g12a-gpio.h deleted file mode 100644 index f7bd69350d1..00000000000 --- a/sys/gnu/dts/include/dt-bindings/gpio/meson-g12a-gpio.h +++ /dev/null @@ -1,114 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ -/* - * Copyright (c) 2018 Amlogic, Inc. All rights reserved. - * Author: Xingyu Chen - */ - -#ifndef _DT_BINDINGS_MESON_G12A_GPIO_H -#define _DT_BINDINGS_MESON_G12A_GPIO_H - -/* First GPIO chip */ -#define GPIOAO_0 0 -#define GPIOAO_1 1 -#define GPIOAO_2 2 -#define GPIOAO_3 3 -#define GPIOAO_4 4 -#define GPIOAO_5 5 -#define GPIOAO_6 6 -#define GPIOAO_7 7 -#define GPIOAO_8 8 -#define GPIOAO_9 9 -#define GPIOAO_10 10 -#define GPIOAO_11 11 -#define GPIOE_0 12 -#define GPIOE_1 13 -#define GPIOE_2 14 - -/* Second GPIO chip */ -#define GPIOZ_0 0 -#define GPIOZ_1 1 -#define GPIOZ_2 2 -#define GPIOZ_3 3 -#define GPIOZ_4 4 -#define GPIOZ_5 5 -#define GPIOZ_6 6 -#define GPIOZ_7 7 -#define GPIOZ_8 8 -#define GPIOZ_9 9 -#define GPIOZ_10 10 -#define GPIOZ_11 11 -#define GPIOZ_12 12 -#define GPIOZ_13 13 -#define GPIOZ_14 14 -#define GPIOZ_15 15 -#define GPIOH_0 16 -#define GPIOH_1 17 -#define GPIOH_2 18 -#define GPIOH_3 19 -#define GPIOH_4 20 -#define GPIOH_5 21 -#define GPIOH_6 22 -#define GPIOH_7 23 -#define GPIOH_8 24 -#define BOOT_0 25 -#define BOOT_1 26 -#define BOOT_2 27 -#define BOOT_3 28 -#define BOOT_4 29 -#define BOOT_5 30 -#define BOOT_6 31 -#define BOOT_7 32 -#define BOOT_8 33 -#define BOOT_9 34 -#define BOOT_10 35 -#define BOOT_11 36 -#define BOOT_12 37 -#define BOOT_13 38 -#define BOOT_14 39 -#define BOOT_15 40 -#define GPIOC_0 41 -#define GPIOC_1 42 -#define GPIOC_2 43 -#define GPIOC_3 44 -#define GPIOC_4 45 -#define GPIOC_5 46 -#define GPIOC_6 47 -#define GPIOC_7 48 -#define GPIOA_0 49 -#define GPIOA_1 50 -#define GPIOA_2 51 -#define GPIOA_3 52 -#define GPIOA_4 53 -#define GPIOA_5 54 -#define GPIOA_6 55 -#define GPIOA_7 56 -#define GPIOA_8 57 -#define GPIOA_9 58 -#define GPIOA_10 59 -#define GPIOA_11 60 -#define GPIOA_12 61 -#define GPIOA_13 62 -#define GPIOA_14 63 -#define GPIOA_15 64 -#define GPIOX_0 65 -#define GPIOX_1 66 -#define GPIOX_2 67 -#define GPIOX_3 68 -#define GPIOX_4 69 -#define GPIOX_5 70 -#define GPIOX_6 71 -#define GPIOX_7 72 -#define GPIOX_8 73 -#define GPIOX_9 74 -#define GPIOX_10 75 -#define GPIOX_11 76 -#define GPIOX_12 77 -#define GPIOX_13 78 -#define GPIOX_14 79 -#define GPIOX_15 80 -#define GPIOX_16 81 -#define GPIOX_17 82 -#define GPIOX_18 83 -#define GPIOX_19 84 - -#endif /* _DT_BINDINGS_MESON_G12A_GPIO_H */ diff --git a/sys/gnu/dts/include/dt-bindings/gpio/meson-gxbb-gpio.h b/sys/gnu/dts/include/dt-bindings/gpio/meson-gxbb-gpio.h deleted file mode 100644 index 489c75b2764..00000000000 --- a/sys/gnu/dts/include/dt-bindings/gpio/meson-gxbb-gpio.h +++ /dev/null @@ -1,148 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * GPIO definitions for Amlogic Meson GXBB SoCs - * - * Copyright (C) 2016 Endless Mobile, Inc. - * Author: Carlo Caione - */ - -#ifndef _DT_BINDINGS_MESON_GXBB_GPIO_H -#define _DT_BINDINGS_MESON_GXBB_GPIO_H - -#define GPIOAO_0 0 -#define GPIOAO_1 1 -#define GPIOAO_2 2 -#define GPIOAO_3 3 -#define GPIOAO_4 4 -#define GPIOAO_5 5 -#define GPIOAO_6 6 -#define GPIOAO_7 7 -#define GPIOAO_8 8 -#define GPIOAO_9 9 -#define GPIOAO_10 10 -#define GPIOAO_11 11 -#define GPIOAO_12 12 -#define GPIOAO_13 13 -#define GPIO_TEST_N 14 - -#define GPIOZ_0 0 -#define GPIOZ_1 1 -#define GPIOZ_2 2 -#define GPIOZ_3 3 -#define GPIOZ_4 4 -#define GPIOZ_5 5 -#define GPIOZ_6 6 -#define GPIOZ_7 7 -#define GPIOZ_8 8 -#define GPIOZ_9 9 -#define GPIOZ_10 10 -#define GPIOZ_11 11 -#define GPIOZ_12 12 -#define GPIOZ_13 13 -#define GPIOZ_14 14 -#define GPIOZ_15 15 -#define GPIOH_0 16 -#define GPIOH_1 17 -#define GPIOH_2 18 -#define GPIOH_3 19 -#define BOOT_0 20 -#define BOOT_1 21 -#define BOOT_2 22 -#define BOOT_3 23 -#define BOOT_4 24 -#define BOOT_5 25 -#define BOOT_6 26 -#define BOOT_7 27 -#define BOOT_8 28 -#define BOOT_9 29 -#define BOOT_10 30 -#define BOOT_11 31 -#define BOOT_12 32 -#define BOOT_13 33 -#define BOOT_14 34 -#define BOOT_15 35 -#define BOOT_16 36 -#define BOOT_17 37 -#define CARD_0 38 -#define CARD_1 39 -#define CARD_2 40 -#define CARD_3 41 -#define CARD_4 42 -#define CARD_5 43 -#define CARD_6 44 -#define GPIODV_0 45 -#define GPIODV_1 46 -#define GPIODV_2 47 -#define GPIODV_3 48 -#define GPIODV_4 49 -#define GPIODV_5 50 -#define GPIODV_6 51 -#define GPIODV_7 52 -#define GPIODV_8 53 -#define GPIODV_9 54 -#define GPIODV_10 55 -#define GPIODV_11 56 -#define GPIODV_12 57 -#define GPIODV_13 58 -#define GPIODV_14 59 -#define GPIODV_15 60 -#define GPIODV_16 61 -#define GPIODV_17 62 -#define GPIODV_18 63 -#define GPIODV_19 64 -#define GPIODV_20 65 -#define GPIODV_21 66 -#define GPIODV_22 67 -#define GPIODV_23 68 -#define GPIODV_24 69 -#define GPIODV_25 70 -#define GPIODV_26 71 -#define GPIODV_27 72 -#define GPIODV_28 73 -#define GPIODV_29 74 -#define GPIOY_0 75 -#define GPIOY_1 76 -#define GPIOY_2 77 -#define GPIOY_3 78 -#define GPIOY_4 79 -#define GPIOY_5 80 -#define GPIOY_6 81 -#define GPIOY_7 82 -#define GPIOY_8 83 -#define GPIOY_9 84 -#define GPIOY_10 85 -#define GPIOY_11 86 -#define GPIOY_12 87 -#define GPIOY_13 88 -#define GPIOY_14 89 -#define GPIOY_15 90 -#define GPIOY_16 91 -#define GPIOX_0 92 -#define GPIOX_1 93 -#define GPIOX_2 94 -#define GPIOX_3 95 -#define GPIOX_4 96 -#define GPIOX_5 97 -#define GPIOX_6 98 -#define GPIOX_7 99 -#define GPIOX_8 100 -#define GPIOX_9 101 -#define GPIOX_10 102 -#define GPIOX_11 103 -#define GPIOX_12 104 -#define GPIOX_13 105 -#define GPIOX_14 106 -#define GPIOX_15 107 -#define GPIOX_16 108 -#define GPIOX_17 109 -#define GPIOX_18 110 -#define GPIOX_19 111 -#define GPIOX_20 112 -#define GPIOX_21 113 -#define GPIOX_22 114 -#define GPIOCLK_0 115 -#define GPIOCLK_1 116 -#define GPIOCLK_2 117 -#define GPIOCLK_3 118 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/gpio/meson-gxl-gpio.h b/sys/gnu/dts/include/dt-bindings/gpio/meson-gxl-gpio.h deleted file mode 100644 index 0a001ae4827..00000000000 --- a/sys/gnu/dts/include/dt-bindings/gpio/meson-gxl-gpio.h +++ /dev/null @@ -1,125 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * GPIO definitions for Amlogic Meson GXL SoCs - * - * Copyright (C) 2016 Endless Mobile, Inc. - * Author: Carlo Caione - */ - -#ifndef _DT_BINDINGS_MESON_GXL_GPIO_H -#define _DT_BINDINGS_MESON_GXL_GPIO_H - -#define GPIOAO_0 0 -#define GPIOAO_1 1 -#define GPIOAO_2 2 -#define GPIOAO_3 3 -#define GPIOAO_4 4 -#define GPIOAO_5 5 -#define GPIOAO_6 6 -#define GPIOAO_7 7 -#define GPIOAO_8 8 -#define GPIOAO_9 9 -#define GPIO_TEST_N 10 - -#define GPIOZ_0 0 -#define GPIOZ_1 1 -#define GPIOZ_2 2 -#define GPIOZ_3 3 -#define GPIOZ_4 4 -#define GPIOZ_5 5 -#define GPIOZ_6 6 -#define GPIOZ_7 7 -#define GPIOZ_8 8 -#define GPIOZ_9 9 -#define GPIOZ_10 10 -#define GPIOZ_11 11 -#define GPIOZ_12 12 -#define GPIOZ_13 13 -#define GPIOZ_14 14 -#define GPIOZ_15 15 -#define GPIOH_0 16 -#define GPIOH_1 17 -#define GPIOH_2 18 -#define GPIOH_3 19 -#define GPIOH_4 20 -#define GPIOH_5 21 -#define GPIOH_6 22 -#define GPIOH_7 23 -#define GPIOH_8 24 -#define GPIOH_9 25 -#define BOOT_0 26 -#define BOOT_1 27 -#define BOOT_2 28 -#define BOOT_3 29 -#define BOOT_4 30 -#define BOOT_5 31 -#define BOOT_6 32 -#define BOOT_7 33 -#define BOOT_8 34 -#define BOOT_9 35 -#define BOOT_10 36 -#define BOOT_11 37 -#define BOOT_12 38 -#define BOOT_13 39 -#define BOOT_14 40 -#define BOOT_15 41 -#define CARD_0 42 -#define CARD_1 43 -#define CARD_2 44 -#define CARD_3 45 -#define CARD_4 46 -#define CARD_5 47 -#define CARD_6 48 -#define GPIODV_0 49 -#define GPIODV_1 50 -#define GPIODV_2 51 -#define GPIODV_3 52 -#define GPIODV_4 53 -#define GPIODV_5 54 -#define GPIODV_6 55 -#define GPIODV_7 56 -#define GPIODV_8 57 -#define GPIODV_9 58 -#define GPIODV_10 59 -#define GPIODV_11 60 -#define GPIODV_12 61 -#define GPIODV_13 62 -#define GPIODV_14 63 -#define GPIODV_15 64 -#define GPIODV_16 65 -#define GPIODV_17 66 -#define GPIODV_18 67 -#define GPIODV_19 68 -#define GPIODV_20 69 -#define GPIODV_21 70 -#define GPIODV_22 71 -#define GPIODV_23 72 -#define GPIODV_24 73 -#define GPIODV_25 74 -#define GPIODV_26 75 -#define GPIODV_27 76 -#define GPIODV_28 77 -#define GPIODV_29 78 -#define GPIOX_0 79 -#define GPIOX_1 80 -#define GPIOX_2 81 -#define GPIOX_3 82 -#define GPIOX_4 83 -#define GPIOX_5 84 -#define GPIOX_6 85 -#define GPIOX_7 86 -#define GPIOX_8 87 -#define GPIOX_9 88 -#define GPIOX_10 89 -#define GPIOX_11 90 -#define GPIOX_12 91 -#define GPIOX_13 92 -#define GPIOX_14 93 -#define GPIOX_15 94 -#define GPIOX_16 95 -#define GPIOX_17 96 -#define GPIOX_18 97 -#define GPIOCLK_0 98 -#define GPIOCLK_1 99 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/gpio/meson8-gpio.h b/sys/gnu/dts/include/dt-bindings/gpio/meson8-gpio.h deleted file mode 100644 index e2d083104df..00000000000 --- a/sys/gnu/dts/include/dt-bindings/gpio/meson8-gpio.h +++ /dev/null @@ -1,151 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * GPIO definitions for Amlogic Meson8 SoCs - * - * Copyright (C) 2014 Beniamino Galvani - */ - -#ifndef _DT_BINDINGS_MESON8_GPIO_H -#define _DT_BINDINGS_MESON8_GPIO_H - -/* First GPIO chip */ -#define GPIOX_0 0 -#define GPIOX_1 1 -#define GPIOX_2 2 -#define GPIOX_3 3 -#define GPIOX_4 4 -#define GPIOX_5 5 -#define GPIOX_6 6 -#define GPIOX_7 7 -#define GPIOX_8 8 -#define GPIOX_9 9 -#define GPIOX_10 10 -#define GPIOX_11 11 -#define GPIOX_12 12 -#define GPIOX_13 13 -#define GPIOX_14 14 -#define GPIOX_15 15 -#define GPIOX_16 16 -#define GPIOX_17 17 -#define GPIOX_18 18 -#define GPIOX_19 19 -#define GPIOX_20 20 -#define GPIOX_21 21 -#define GPIOY_0 22 -#define GPIOY_1 23 -#define GPIOY_2 24 -#define GPIOY_3 25 -#define GPIOY_4 26 -#define GPIOY_5 27 -#define GPIOY_6 28 -#define GPIOY_7 29 -#define GPIOY_8 30 -#define GPIOY_9 31 -#define GPIOY_10 32 -#define GPIOY_11 33 -#define GPIOY_12 34 -#define GPIOY_13 35 -#define GPIOY_14 36 -#define GPIOY_15 37 -#define GPIOY_16 38 -#define GPIODV_0 39 -#define GPIODV_1 40 -#define GPIODV_2 41 -#define GPIODV_3 42 -#define GPIODV_4 43 -#define GPIODV_5 44 -#define GPIODV_6 45 -#define GPIODV_7 46 -#define GPIODV_8 47 -#define GPIODV_9 48 -#define GPIODV_10 49 -#define GPIODV_11 50 -#define GPIODV_12 51 -#define GPIODV_13 52 -#define GPIODV_14 53 -#define GPIODV_15 54 -#define GPIODV_16 55 -#define GPIODV_17 56 -#define GPIODV_18 57 -#define GPIODV_19 58 -#define GPIODV_20 59 -#define GPIODV_21 60 -#define GPIODV_22 61 -#define GPIODV_23 62 -#define GPIODV_24 63 -#define GPIODV_25 64 -#define GPIODV_26 65 -#define GPIODV_27 66 -#define GPIODV_28 67 -#define GPIODV_29 68 -#define GPIOH_0 69 -#define GPIOH_1 70 -#define GPIOH_2 71 -#define GPIOH_3 72 -#define GPIOH_4 73 -#define GPIOH_5 74 -#define GPIOH_6 75 -#define GPIOH_7 76 -#define GPIOH_8 77 -#define GPIOH_9 78 -#define GPIOZ_0 79 -#define GPIOZ_1 80 -#define GPIOZ_2 81 -#define GPIOZ_3 82 -#define GPIOZ_4 83 -#define GPIOZ_5 84 -#define GPIOZ_6 85 -#define GPIOZ_7 86 -#define GPIOZ_8 87 -#define GPIOZ_9 88 -#define GPIOZ_10 89 -#define GPIOZ_11 90 -#define GPIOZ_12 91 -#define GPIOZ_13 92 -#define GPIOZ_14 93 -#define CARD_0 94 -#define CARD_1 95 -#define CARD_2 96 -#define CARD_3 97 -#define CARD_4 98 -#define CARD_5 99 -#define CARD_6 100 -#define BOOT_0 101 -#define BOOT_1 102 -#define BOOT_2 103 -#define BOOT_3 104 -#define BOOT_4 105 -#define BOOT_5 106 -#define BOOT_6 107 -#define BOOT_7 108 -#define BOOT_8 109 -#define BOOT_9 110 -#define BOOT_10 111 -#define BOOT_11 112 -#define BOOT_12 113 -#define BOOT_13 114 -#define BOOT_14 115 -#define BOOT_15 116 -#define BOOT_16 117 -#define BOOT_17 118 -#define BOOT_18 119 - -/* Second GPIO chip */ -#define GPIOAO_0 0 -#define GPIOAO_1 1 -#define GPIOAO_2 2 -#define GPIOAO_3 3 -#define GPIOAO_4 4 -#define GPIOAO_5 5 -#define GPIOAO_6 6 -#define GPIOAO_7 7 -#define GPIOAO_8 8 -#define GPIOAO_9 9 -#define GPIOAO_10 10 -#define GPIOAO_11 11 -#define GPIOAO_12 12 -#define GPIOAO_13 13 -#define GPIO_BSD_EN 14 -#define GPIO_TEST_N 15 - -#endif /* _DT_BINDINGS_MESON8_GPIO_H */ diff --git a/sys/gnu/dts/include/dt-bindings/gpio/meson8b-gpio.h b/sys/gnu/dts/include/dt-bindings/gpio/meson8b-gpio.h deleted file mode 100644 index 7c3bc0782ec..00000000000 --- a/sys/gnu/dts/include/dt-bindings/gpio/meson8b-gpio.h +++ /dev/null @@ -1,121 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * GPIO definitions for Amlogic Meson8b SoCs - * - * Copyright (C) 2015 Endless Mobile, Inc. - * Author: Carlo Caione - */ - -#ifndef _DT_BINDINGS_MESON8B_GPIO_H -#define _DT_BINDINGS_MESON8B_GPIO_H - -/* EE (CBUS) GPIO chip */ -#define GPIOX_0 0 -#define GPIOX_1 1 -#define GPIOX_2 2 -#define GPIOX_3 3 -#define GPIOX_4 4 -#define GPIOX_5 5 -#define GPIOX_6 6 -#define GPIOX_7 7 -#define GPIOX_8 8 -#define GPIOX_9 9 -#define GPIOX_10 10 -#define GPIOX_11 11 -#define GPIOX_16 12 -#define GPIOX_17 13 -#define GPIOX_18 14 -#define GPIOX_19 15 -#define GPIOX_20 16 -#define GPIOX_21 17 - -#define GPIOY_0 18 -#define GPIOY_1 19 -#define GPIOY_3 20 -#define GPIOY_6 21 -#define GPIOY_7 22 -#define GPIOY_8 23 -#define GPIOY_9 24 -#define GPIOY_10 25 -#define GPIOY_11 26 -#define GPIOY_12 27 -#define GPIOY_13 28 -#define GPIOY_14 29 - -#define GPIODV_9 30 -#define GPIODV_24 31 -#define GPIODV_25 32 -#define GPIODV_26 33 -#define GPIODV_27 34 -#define GPIODV_28 35 -#define GPIODV_29 36 - -#define GPIOH_0 37 -#define GPIOH_1 38 -#define GPIOH_2 39 -#define GPIOH_3 40 -#define GPIOH_4 41 -#define GPIOH_5 42 -#define GPIOH_6 43 -#define GPIOH_7 44 -#define GPIOH_8 45 -#define GPIOH_9 46 - -#define CARD_0 47 -#define CARD_1 48 -#define CARD_2 49 -#define CARD_3 50 -#define CARD_4 51 -#define CARD_5 52 -#define CARD_6 53 - -#define BOOT_0 54 -#define BOOT_1 55 -#define BOOT_2 56 -#define BOOT_3 57 -#define BOOT_4 58 -#define BOOT_5 59 -#define BOOT_6 60 -#define BOOT_7 61 -#define BOOT_8 62 -#define BOOT_9 63 -#define BOOT_10 64 -#define BOOT_11 65 -#define BOOT_12 66 -#define BOOT_13 67 -#define BOOT_14 68 -#define BOOT_15 69 -#define BOOT_16 70 -#define BOOT_17 71 -#define BOOT_18 72 - -#define DIF_0_P 73 -#define DIF_0_N 74 -#define DIF_1_P 75 -#define DIF_1_N 76 -#define DIF_2_P 77 -#define DIF_2_N 78 -#define DIF_3_P 79 -#define DIF_3_N 80 -#define DIF_4_P 81 -#define DIF_4_N 82 - -/* AO GPIO chip */ -#define GPIOAO_0 0 -#define GPIOAO_1 1 -#define GPIOAO_2 2 -#define GPIOAO_3 3 -#define GPIOAO_4 4 -#define GPIOAO_5 5 -#define GPIOAO_6 6 -#define GPIOAO_7 7 -#define GPIOAO_8 8 -#define GPIOAO_9 9 -#define GPIOAO_10 10 -#define GPIOAO_11 11 -#define GPIOAO_12 12 -#define GPIOAO_13 13 -#define GPIO_BSD_EN 14 -#define GPIO_TEST_N 15 - -#endif /* _DT_BINDINGS_MESON8B_GPIO_H */ diff --git a/sys/gnu/dts/include/dt-bindings/gpio/tegra-gpio.h b/sys/gnu/dts/include/dt-bindings/gpio/tegra-gpio.h deleted file mode 100644 index 7625dbc577c..00000000000 --- a/sys/gnu/dts/include/dt-bindings/gpio/tegra-gpio.h +++ /dev/null @@ -1,52 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides constants for binding nvidia,tegra*-gpio. - * - * The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below - * provide names for this. - * - * The second cell contains standard flag values specified in gpio.h. - */ - -#ifndef _DT_BINDINGS_GPIO_TEGRA_GPIO_H -#define _DT_BINDINGS_GPIO_TEGRA_GPIO_H - -#include - -#define TEGRA_GPIO_PORT_A 0 -#define TEGRA_GPIO_PORT_B 1 -#define TEGRA_GPIO_PORT_C 2 -#define TEGRA_GPIO_PORT_D 3 -#define TEGRA_GPIO_PORT_E 4 -#define TEGRA_GPIO_PORT_F 5 -#define TEGRA_GPIO_PORT_G 6 -#define TEGRA_GPIO_PORT_H 7 -#define TEGRA_GPIO_PORT_I 8 -#define TEGRA_GPIO_PORT_J 9 -#define TEGRA_GPIO_PORT_K 10 -#define TEGRA_GPIO_PORT_L 11 -#define TEGRA_GPIO_PORT_M 12 -#define TEGRA_GPIO_PORT_N 13 -#define TEGRA_GPIO_PORT_O 14 -#define TEGRA_GPIO_PORT_P 15 -#define TEGRA_GPIO_PORT_Q 16 -#define TEGRA_GPIO_PORT_R 17 -#define TEGRA_GPIO_PORT_S 18 -#define TEGRA_GPIO_PORT_T 19 -#define TEGRA_GPIO_PORT_U 20 -#define TEGRA_GPIO_PORT_V 21 -#define TEGRA_GPIO_PORT_W 22 -#define TEGRA_GPIO_PORT_X 23 -#define TEGRA_GPIO_PORT_Y 24 -#define TEGRA_GPIO_PORT_Z 25 -#define TEGRA_GPIO_PORT_AA 26 -#define TEGRA_GPIO_PORT_BB 27 -#define TEGRA_GPIO_PORT_CC 28 -#define TEGRA_GPIO_PORT_DD 29 -#define TEGRA_GPIO_PORT_EE 30 -#define TEGRA_GPIO_PORT_FF 31 - -#define TEGRA_GPIO(port, offset) \ - ((TEGRA_GPIO_PORT_##port * 8) + offset) - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/gpio/tegra186-gpio.h b/sys/gnu/dts/include/dt-bindings/gpio/tegra186-gpio.h deleted file mode 100644 index 0782b05e277..00000000000 --- a/sys/gnu/dts/include/dt-bindings/gpio/tegra186-gpio.h +++ /dev/null @@ -1,57 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides constants for binding nvidia,tegra186-gpio*. - * - * The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below - * provide names for this. - * - * The second cell contains standard flag values specified in gpio.h. - */ - -#ifndef _DT_BINDINGS_GPIO_TEGRA_GPIO_H -#define _DT_BINDINGS_GPIO_TEGRA_GPIO_H - -#include - -/* GPIOs implemented by main GPIO controller */ -#define TEGRA186_MAIN_GPIO_PORT_A 0 -#define TEGRA186_MAIN_GPIO_PORT_B 1 -#define TEGRA186_MAIN_GPIO_PORT_C 2 -#define TEGRA186_MAIN_GPIO_PORT_D 3 -#define TEGRA186_MAIN_GPIO_PORT_E 4 -#define TEGRA186_MAIN_GPIO_PORT_F 5 -#define TEGRA186_MAIN_GPIO_PORT_G 6 -#define TEGRA186_MAIN_GPIO_PORT_H 7 -#define TEGRA186_MAIN_GPIO_PORT_I 8 -#define TEGRA186_MAIN_GPIO_PORT_J 9 -#define TEGRA186_MAIN_GPIO_PORT_K 10 -#define TEGRA186_MAIN_GPIO_PORT_L 11 -#define TEGRA186_MAIN_GPIO_PORT_M 12 -#define TEGRA186_MAIN_GPIO_PORT_N 13 -#define TEGRA186_MAIN_GPIO_PORT_O 14 -#define TEGRA186_MAIN_GPIO_PORT_P 15 -#define TEGRA186_MAIN_GPIO_PORT_Q 16 -#define TEGRA186_MAIN_GPIO_PORT_R 17 -#define TEGRA186_MAIN_GPIO_PORT_T 18 -#define TEGRA186_MAIN_GPIO_PORT_X 19 -#define TEGRA186_MAIN_GPIO_PORT_Y 20 -#define TEGRA186_MAIN_GPIO_PORT_BB 21 -#define TEGRA186_MAIN_GPIO_PORT_CC 22 - -#define TEGRA186_MAIN_GPIO(port, offset) \ - ((TEGRA186_MAIN_GPIO_PORT_##port * 8) + offset) - -/* GPIOs implemented by AON GPIO controller */ -#define TEGRA186_AON_GPIO_PORT_S 0 -#define TEGRA186_AON_GPIO_PORT_U 1 -#define TEGRA186_AON_GPIO_PORT_V 2 -#define TEGRA186_AON_GPIO_PORT_W 3 -#define TEGRA186_AON_GPIO_PORT_Z 4 -#define TEGRA186_AON_GPIO_PORT_AA 5 -#define TEGRA186_AON_GPIO_PORT_EE 6 -#define TEGRA186_AON_GPIO_PORT_FF 7 - -#define TEGRA186_AON_GPIO(port, offset) \ - ((TEGRA186_AON_GPIO_PORT_##port * 8) + offset) - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/gpio/tegra194-gpio.h b/sys/gnu/dts/include/dt-bindings/gpio/tegra194-gpio.h deleted file mode 100644 index ede860225f6..00000000000 --- a/sys/gnu/dts/include/dt-bindings/gpio/tegra194-gpio.h +++ /dev/null @@ -1,61 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. */ - -/* - * This header provides constants for binding nvidia,tegra194-gpio*. - * - * The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below - * provide names for this. - * - * The second cell contains standard flag values specified in gpio.h. - */ - -#ifndef _DT_BINDINGS_GPIO_TEGRA194_GPIO_H -#define _DT_BINDINGS_GPIO_TEGRA194_GPIO_H - -#include - -/* GPIOs implemented by main GPIO controller */ -#define TEGRA194_MAIN_GPIO_PORT_A 0 -#define TEGRA194_MAIN_GPIO_PORT_B 1 -#define TEGRA194_MAIN_GPIO_PORT_C 2 -#define TEGRA194_MAIN_GPIO_PORT_D 3 -#define TEGRA194_MAIN_GPIO_PORT_E 4 -#define TEGRA194_MAIN_GPIO_PORT_F 5 -#define TEGRA194_MAIN_GPIO_PORT_G 6 -#define TEGRA194_MAIN_GPIO_PORT_H 7 -#define TEGRA194_MAIN_GPIO_PORT_I 8 -#define TEGRA194_MAIN_GPIO_PORT_J 9 -#define TEGRA194_MAIN_GPIO_PORT_K 10 -#define TEGRA194_MAIN_GPIO_PORT_L 11 -#define TEGRA194_MAIN_GPIO_PORT_M 12 -#define TEGRA194_MAIN_GPIO_PORT_N 13 -#define TEGRA194_MAIN_GPIO_PORT_O 14 -#define TEGRA194_MAIN_GPIO_PORT_P 15 -#define TEGRA194_MAIN_GPIO_PORT_Q 16 -#define TEGRA194_MAIN_GPIO_PORT_R 17 -#define TEGRA194_MAIN_GPIO_PORT_S 18 -#define TEGRA194_MAIN_GPIO_PORT_T 19 -#define TEGRA194_MAIN_GPIO_PORT_U 20 -#define TEGRA194_MAIN_GPIO_PORT_V 21 -#define TEGRA194_MAIN_GPIO_PORT_W 22 -#define TEGRA194_MAIN_GPIO_PORT_X 23 -#define TEGRA194_MAIN_GPIO_PORT_Y 24 -#define TEGRA194_MAIN_GPIO_PORT_Z 25 -#define TEGRA194_MAIN_GPIO_PORT_FF 26 -#define TEGRA194_MAIN_GPIO_PORT_GG 27 - -#define TEGRA194_MAIN_GPIO(port, offset) \ - ((TEGRA194_MAIN_GPIO_PORT_##port * 8) + offset) - -/* GPIOs implemented by AON GPIO controller */ -#define TEGRA194_AON_GPIO_PORT_AA 0 -#define TEGRA194_AON_GPIO_PORT_BB 1 -#define TEGRA194_AON_GPIO_PORT_CC 2 -#define TEGRA194_AON_GPIO_PORT_DD 3 -#define TEGRA194_AON_GPIO_PORT_EE 4 - -#define TEGRA194_AON_GPIO(port, offset) \ - ((TEGRA194_AON_GPIO_PORT_##port * 8) + offset) - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/gpio/uniphier-gpio.h b/sys/gnu/dts/include/dt-bindings/gpio/uniphier-gpio.h deleted file mode 100644 index 9f0ad174f61..00000000000 --- a/sys/gnu/dts/include/dt-bindings/gpio/uniphier-gpio.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * Copyright (C) 2017 Socionext Inc. - * Author: Masahiro Yamada - */ - -#ifndef _DT_BINDINGS_GPIO_UNIPHIER_H -#define _DT_BINDINGS_GPIO_UNIPHIER_H - -#define UNIPHIER_GPIO_LINES_PER_BANK 8 - -#define UNIPHIER_GPIO_IRQ_OFFSET ((UNIPHIER_GPIO_LINES_PER_BANK) * 15) - -#define UNIPHIER_GPIO_PORT(bank, line) \ - ((UNIPHIER_GPIO_LINES_PER_BANK) * (bank) + (line)) - -#define UNIPHIER_GPIO_IRQ(n) ((UNIPHIER_GPIO_IRQ_OFFSET) + (n)) - -#endif /* _DT_BINDINGS_GPIO_UNIPHIER_H */ diff --git a/sys/gnu/dts/include/dt-bindings/i2c/i2c.h b/sys/gnu/dts/include/dt-bindings/i2c/i2c.h deleted file mode 100644 index 0c12c38dfa2..00000000000 --- a/sys/gnu/dts/include/dt-bindings/i2c/i2c.h +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * This header provides constants for I2C bindings - * - * Copyright (C) 2015 by Sang Engineering - * Copyright (C) 2015 by Renesas Electronics Corporation - * - * Wolfram Sang - */ - -#ifndef _DT_BINDINGS_I2C_I2C_H -#define _DT_BINDINGS_I2C_I2C_H - -#define I2C_TEN_BIT_ADDRESS (1 << 31) -#define I2C_OWN_SLAVE_ADDRESS (1 << 30) - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/iio/adc/at91-sama5d2_adc.h b/sys/gnu/dts/include/dt-bindings/iio/adc/at91-sama5d2_adc.h deleted file mode 100644 index 70f99dbdbb4..00000000000 --- a/sys/gnu/dts/include/dt-bindings/iio/adc/at91-sama5d2_adc.h +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides constants for configuring the AT91 SAMA5D2 ADC - */ - -#ifndef _DT_BINDINGS_IIO_ADC_AT91_SAMA5D2_ADC_H -#define _DT_BINDINGS_IIO_ADC_AT91_SAMA5D2_ADC_H - -/* X relative position channel index */ -#define AT91_SAMA5D2_ADC_X_CHANNEL 24 -/* Y relative position channel index */ -#define AT91_SAMA5D2_ADC_Y_CHANNEL 25 -/* pressure channel index */ -#define AT91_SAMA5D2_ADC_P_CHANNEL 26 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/iio/adc/fsl-imx25-gcq.h b/sys/gnu/dts/include/dt-bindings/iio/adc/fsl-imx25-gcq.h deleted file mode 100644 index 08ef4d298b9..00000000000 --- a/sys/gnu/dts/include/dt-bindings/iio/adc/fsl-imx25-gcq.h +++ /dev/null @@ -1,19 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides constants for configuring the I.MX25 ADC - */ - -#ifndef _DT_BINDINGS_IIO_ADC_FS_IMX25_GCQ_H -#define _DT_BINDINGS_IIO_ADC_FS_IMX25_GCQ_H - -#define MX25_ADC_REFP_YP 0 /* YP voltage reference */ -#define MX25_ADC_REFP_XP 1 /* XP voltage reference */ -#define MX25_ADC_REFP_EXT 2 /* External voltage reference */ -#define MX25_ADC_REFP_INT 3 /* Internal voltage reference */ - -#define MX25_ADC_REFN_XN 0 /* XN ground reference */ -#define MX25_ADC_REFN_YN 1 /* YN ground reference */ -#define MX25_ADC_REFN_NGND 2 /* Internal ground reference */ -#define MX25_ADC_REFN_NGND2 3 /* External ground reference */ - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/iio/adc/ingenic,adc.h b/sys/gnu/dts/include/dt-bindings/iio/adc/ingenic,adc.h deleted file mode 100644 index 42f871ab327..00000000000 --- a/sys/gnu/dts/include/dt-bindings/iio/adc/ingenic,adc.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ - -#ifndef _DT_BINDINGS_IIO_ADC_INGENIC_ADC_H -#define _DT_BINDINGS_IIO_ADC_INGENIC_ADC_H - -/* ADC channel idx. */ -#define INGENIC_ADC_AUX 0 -#define INGENIC_ADC_BATTERY 1 -#define INGENIC_ADC_AUX2 2 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/iio/adi,ad5592r.h b/sys/gnu/dts/include/dt-bindings/iio/adi,ad5592r.h deleted file mode 100644 index 9f8c7b808cd..00000000000 --- a/sys/gnu/dts/include/dt-bindings/iio/adi,ad5592r.h +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ - -#ifndef _DT_BINDINGS_ADI_AD5592R_H -#define _DT_BINDINGS_ADI_AD5592R_H - -#define CH_MODE_UNUSED 0 -#define CH_MODE_ADC 1 -#define CH_MODE_DAC 2 -#define CH_MODE_DAC_AND_ADC 3 -#define CH_MODE_GPIO 8 - -#define CH_OFFSTATE_PULLDOWN 0 -#define CH_OFFSTATE_OUT_LOW 1 -#define CH_OFFSTATE_OUT_HIGH 2 -#define CH_OFFSTATE_OUT_TRISTATE 3 - -#endif /* _DT_BINDINGS_ADI_AD5592R_H */ diff --git a/sys/gnu/dts/include/dt-bindings/iio/qcom,spmi-vadc.h b/sys/gnu/dts/include/dt-bindings/iio/qcom,spmi-vadc.h deleted file mode 100644 index 61d556db154..00000000000 --- a/sys/gnu/dts/include/dt-bindings/iio/qcom,spmi-vadc.h +++ /dev/null @@ -1,224 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2012-2014,2018 The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_H -#define _DT_BINDINGS_QCOM_SPMI_VADC_H - -/* Voltage ADC channels */ -#define VADC_USBIN 0x00 -#define VADC_DCIN 0x01 -#define VADC_VCHG_SNS 0x02 -#define VADC_SPARE1_03 0x03 -#define VADC_USB_ID_MV 0x04 -#define VADC_VCOIN 0x05 -#define VADC_VBAT_SNS 0x06 -#define VADC_VSYS 0x07 -#define VADC_DIE_TEMP 0x08 -#define VADC_REF_625MV 0x09 -#define VADC_REF_1250MV 0x0a -#define VADC_CHG_TEMP 0x0b -#define VADC_SPARE1 0x0c -#define VADC_SPARE2 0x0d -#define VADC_GND_REF 0x0e -#define VADC_VDD_VADC 0x0f - -#define VADC_P_MUX1_1_1 0x10 -#define VADC_P_MUX2_1_1 0x11 -#define VADC_P_MUX3_1_1 0x12 -#define VADC_P_MUX4_1_1 0x13 -#define VADC_P_MUX5_1_1 0x14 -#define VADC_P_MUX6_1_1 0x15 -#define VADC_P_MUX7_1_1 0x16 -#define VADC_P_MUX8_1_1 0x17 -#define VADC_P_MUX9_1_1 0x18 -#define VADC_P_MUX10_1_1 0x19 -#define VADC_P_MUX11_1_1 0x1a -#define VADC_P_MUX12_1_1 0x1b -#define VADC_P_MUX13_1_1 0x1c -#define VADC_P_MUX14_1_1 0x1d -#define VADC_P_MUX15_1_1 0x1e -#define VADC_P_MUX16_1_1 0x1f - -#define VADC_P_MUX1_1_3 0x20 -#define VADC_P_MUX2_1_3 0x21 -#define VADC_P_MUX3_1_3 0x22 -#define VADC_P_MUX4_1_3 0x23 -#define VADC_P_MUX5_1_3 0x24 -#define VADC_P_MUX6_1_3 0x25 -#define VADC_P_MUX7_1_3 0x26 -#define VADC_P_MUX8_1_3 0x27 -#define VADC_P_MUX9_1_3 0x28 -#define VADC_P_MUX10_1_3 0x29 -#define VADC_P_MUX11_1_3 0x2a -#define VADC_P_MUX12_1_3 0x2b -#define VADC_P_MUX13_1_3 0x2c -#define VADC_P_MUX14_1_3 0x2d -#define VADC_P_MUX15_1_3 0x2e -#define VADC_P_MUX16_1_3 0x2f - -#define VADC_LR_MUX1_BAT_THERM 0x30 -#define VADC_LR_MUX2_BAT_ID 0x31 -#define VADC_LR_MUX3_XO_THERM 0x32 -#define VADC_LR_MUX4_AMUX_THM1 0x33 -#define VADC_LR_MUX5_AMUX_THM2 0x34 -#define VADC_LR_MUX6_AMUX_THM3 0x35 -#define VADC_LR_MUX7_HW_ID 0x36 -#define VADC_LR_MUX8_AMUX_THM4 0x37 -#define VADC_LR_MUX9_AMUX_THM5 0x38 -#define VADC_LR_MUX10_USB_ID 0x39 -#define VADC_AMUX_PU1 0x3a -#define VADC_AMUX_PU2 0x3b -#define VADC_LR_MUX3_BUF_XO_THERM 0x3c - -#define VADC_LR_MUX1_PU1_BAT_THERM 0x70 -#define VADC_LR_MUX2_PU1_BAT_ID 0x71 -#define VADC_LR_MUX3_PU1_XO_THERM 0x72 -#define VADC_LR_MUX4_PU1_AMUX_THM1 0x73 -#define VADC_LR_MUX5_PU1_AMUX_THM2 0x74 -#define VADC_LR_MUX6_PU1_AMUX_THM3 0x75 -#define VADC_LR_MUX7_PU1_AMUX_HW_ID 0x76 -#define VADC_LR_MUX8_PU1_AMUX_THM4 0x77 -#define VADC_LR_MUX9_PU1_AMUX_THM5 0x78 -#define VADC_LR_MUX10_PU1_AMUX_USB_ID 0x79 -#define VADC_LR_MUX3_BUF_PU1_XO_THERM 0x7c - -#define VADC_LR_MUX1_PU2_BAT_THERM 0xb0 -#define VADC_LR_MUX2_PU2_BAT_ID 0xb1 -#define VADC_LR_MUX3_PU2_XO_THERM 0xb2 -#define VADC_LR_MUX4_PU2_AMUX_THM1 0xb3 -#define VADC_LR_MUX5_PU2_AMUX_THM2 0xb4 -#define VADC_LR_MUX6_PU2_AMUX_THM3 0xb5 -#define VADC_LR_MUX7_PU2_AMUX_HW_ID 0xb6 -#define VADC_LR_MUX8_PU2_AMUX_THM4 0xb7 -#define VADC_LR_MUX9_PU2_AMUX_THM5 0xb8 -#define VADC_LR_MUX10_PU2_AMUX_USB_ID 0xb9 -#define VADC_LR_MUX3_BUF_PU2_XO_THERM 0xbc - -#define VADC_LR_MUX1_PU1_PU2_BAT_THERM 0xf0 -#define VADC_LR_MUX2_PU1_PU2_BAT_ID 0xf1 -#define VADC_LR_MUX3_PU1_PU2_XO_THERM 0xf2 -#define VADC_LR_MUX4_PU1_PU2_AMUX_THM1 0xf3 -#define VADC_LR_MUX5_PU1_PU2_AMUX_THM2 0xf4 -#define VADC_LR_MUX6_PU1_PU2_AMUX_THM3 0xf5 -#define VADC_LR_MUX7_PU1_PU2_AMUX_HW_ID 0xf6 -#define VADC_LR_MUX8_PU1_PU2_AMUX_THM4 0xf7 -#define VADC_LR_MUX9_PU1_PU2_AMUX_THM5 0xf8 -#define VADC_LR_MUX10_PU1_PU2_AMUX_USB_ID 0xf9 -#define VADC_LR_MUX3_BUF_PU1_PU2_XO_THERM 0xfc - -/* ADC channels for SPMI PMIC5 */ - -#define ADC5_REF_GND 0x00 -#define ADC5_1P25VREF 0x01 -#define ADC5_VREF_VADC 0x02 -#define ADC5_VREF_VADC5_DIV_3 0x82 -#define ADC5_VPH_PWR 0x83 -#define ADC5_VBAT_SNS 0x84 -#define ADC5_VCOIN 0x85 -#define ADC5_DIE_TEMP 0x06 -#define ADC5_USB_IN_I 0x07 -#define ADC5_USB_IN_V_16 0x08 -#define ADC5_CHG_TEMP 0x09 -#define ADC5_BAT_THERM 0x0a -#define ADC5_BAT_ID 0x0b -#define ADC5_XO_THERM 0x0c -#define ADC5_AMUX_THM1 0x0d -#define ADC5_AMUX_THM2 0x0e -#define ADC5_AMUX_THM3 0x0f -#define ADC5_AMUX_THM4 0x10 -#define ADC5_AMUX_THM5 0x11 -#define ADC5_GPIO1 0x12 -#define ADC5_GPIO2 0x13 -#define ADC5_GPIO3 0x14 -#define ADC5_GPIO4 0x15 -#define ADC5_GPIO5 0x16 -#define ADC5_GPIO6 0x17 -#define ADC5_GPIO7 0x18 -#define ADC5_SBUx 0x99 -#define ADC5_MID_CHG_DIV6 0x1e -#define ADC5_OFF 0xff - -/* 30k pull-up1 */ -#define ADC5_BAT_THERM_30K_PU 0x2a -#define ADC5_BAT_ID_30K_PU 0x2b -#define ADC5_XO_THERM_30K_PU 0x2c -#define ADC5_AMUX_THM1_30K_PU 0x2d -#define ADC5_AMUX_THM2_30K_PU 0x2e -#define ADC5_AMUX_THM3_30K_PU 0x2f -#define ADC5_AMUX_THM4_30K_PU 0x30 -#define ADC5_AMUX_THM5_30K_PU 0x31 -#define ADC5_GPIO1_30K_PU 0x32 -#define ADC5_GPIO2_30K_PU 0x33 -#define ADC5_GPIO3_30K_PU 0x34 -#define ADC5_GPIO4_30K_PU 0x35 -#define ADC5_GPIO5_30K_PU 0x36 -#define ADC5_GPIO6_30K_PU 0x37 -#define ADC5_GPIO7_30K_PU 0x38 -#define ADC5_SBUx_30K_PU 0x39 - -/* 100k pull-up2 */ -#define ADC5_BAT_THERM_100K_PU 0x4a -#define ADC5_BAT_ID_100K_PU 0x4b -#define ADC5_XO_THERM_100K_PU 0x4c -#define ADC5_AMUX_THM1_100K_PU 0x4d -#define ADC5_AMUX_THM2_100K_PU 0x4e -#define ADC5_AMUX_THM3_100K_PU 0x4f -#define ADC5_AMUX_THM4_100K_PU 0x50 -#define ADC5_AMUX_THM5_100K_PU 0x51 -#define ADC5_GPIO1_100K_PU 0x52 -#define ADC5_GPIO2_100K_PU 0x53 -#define ADC5_GPIO3_100K_PU 0x54 -#define ADC5_GPIO4_100K_PU 0x55 -#define ADC5_GPIO5_100K_PU 0x56 -#define ADC5_GPIO6_100K_PU 0x57 -#define ADC5_GPIO7_100K_PU 0x58 -#define ADC5_SBUx_100K_PU 0x59 - -/* 400k pull-up3 */ -#define ADC5_BAT_THERM_400K_PU 0x6a -#define ADC5_BAT_ID_400K_PU 0x6b -#define ADC5_XO_THERM_400K_PU 0x6c -#define ADC5_AMUX_THM1_400K_PU 0x6d -#define ADC5_AMUX_THM2_400K_PU 0x6e -#define ADC5_AMUX_THM3_400K_PU 0x6f -#define ADC5_AMUX_THM4_400K_PU 0x70 -#define ADC5_AMUX_THM5_400K_PU 0x71 -#define ADC5_GPIO1_400K_PU 0x72 -#define ADC5_GPIO2_400K_PU 0x73 -#define ADC5_GPIO3_400K_PU 0x74 -#define ADC5_GPIO4_400K_PU 0x75 -#define ADC5_GPIO5_400K_PU 0x76 -#define ADC5_GPIO6_400K_PU 0x77 -#define ADC5_GPIO7_400K_PU 0x78 -#define ADC5_SBUx_400K_PU 0x79 - -/* 1/3 Divider */ -#define ADC5_GPIO1_DIV3 0x92 -#define ADC5_GPIO2_DIV3 0x93 -#define ADC5_GPIO3_DIV3 0x94 -#define ADC5_GPIO4_DIV3 0x95 -#define ADC5_GPIO5_DIV3 0x96 -#define ADC5_GPIO6_DIV3 0x97 -#define ADC5_GPIO7_DIV3 0x98 -#define ADC5_SBUx_DIV3 0x99 - -/* Current and combined current/voltage channels */ -#define ADC5_INT_EXT_ISENSE 0xa1 -#define ADC5_PARALLEL_ISENSE 0xa5 -#define ADC5_CUR_REPLICA_VDS 0xa7 -#define ADC5_CUR_SENS_BATFET_VDS_OFFSET 0xa9 -#define ADC5_CUR_SENS_REPLICA_VDS_OFFSET 0xab -#define ADC5_EXT_SENS_OFFSET 0xad - -#define ADC5_INT_EXT_ISENSE_VBAT_VDATA 0xb0 -#define ADC5_INT_EXT_ISENSE_VBAT_IDATA 0xb1 -#define ADC5_EXT_ISENSE_VBAT_VDATA 0xb2 -#define ADC5_EXT_ISENSE_VBAT_IDATA 0xb3 -#define ADC5_PARALLEL_ISENSE_VBAT_VDATA 0xb4 -#define ADC5_PARALLEL_ISENSE_VBAT_IDATA 0xb5 - -#define ADC5_MAX_CHANNEL 0xc0 - -#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_H */ diff --git a/sys/gnu/dts/include/dt-bindings/iio/temperature/thermocouple.h b/sys/gnu/dts/include/dt-bindings/iio/temperature/thermocouple.h deleted file mode 100644 index ce037f5238a..00000000000 --- a/sys/gnu/dts/include/dt-bindings/iio/temperature/thermocouple.h +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ - -#ifndef _DT_BINDINGS_TEMPERATURE_THERMOCOUPLE_H -#define _DT_BINDINGS_TEMPERATURE_THERMOCOUPLE_H - - -#define THERMOCOUPLE_TYPE_B 0x00 -#define THERMOCOUPLE_TYPE_E 0x01 -#define THERMOCOUPLE_TYPE_J 0x02 -#define THERMOCOUPLE_TYPE_K 0x03 -#define THERMOCOUPLE_TYPE_N 0x04 -#define THERMOCOUPLE_TYPE_R 0x05 -#define THERMOCOUPLE_TYPE_S 0x06 -#define THERMOCOUPLE_TYPE_T 0x07 - -#endif /* _DT_BINDINGS_TEMPERATURE_THERMOCOUPLE_H */ diff --git a/sys/gnu/dts/include/dt-bindings/input/gpio-keys.h b/sys/gnu/dts/include/dt-bindings/input/gpio-keys.h deleted file mode 100644 index 8962df79e75..00000000000 --- a/sys/gnu/dts/include/dt-bindings/input/gpio-keys.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides constants for gpio keys bindings. - */ - -#ifndef _DT_BINDINGS_GPIO_KEYS_H -#define _DT_BINDINGS_GPIO_KEYS_H - -#define EV_ACT_ANY 0x00 /* asserted or deasserted */ -#define EV_ACT_ASSERTED 0x01 /* asserted */ -#define EV_ACT_DEASSERTED 0x02 /* deasserted */ - -#endif /* _DT_BINDINGS_GPIO_KEYS_H */ diff --git a/sys/gnu/dts/include/dt-bindings/input/input.h b/sys/gnu/dts/include/dt-bindings/input/input.h deleted file mode 100644 index bcf0ae100f2..00000000000 --- a/sys/gnu/dts/include/dt-bindings/input/input.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides constants for most input bindings. - * - * Most input bindings include key code, matrix key code format. - * In most cases, key code and matrix key code format uses - * the standard values/macro defined in this header. - */ - -#ifndef _DT_BINDINGS_INPUT_INPUT_H -#define _DT_BINDINGS_INPUT_INPUT_H - -#include "linux-event-codes.h" - -#define MATRIX_KEY(row, col, code) \ - ((((row) & 0xFF) << 24) | (((col) & 0xFF) << 16) | ((code) & 0xFFFF)) - -#endif /* _DT_BINDINGS_INPUT_INPUT_H */ diff --git a/sys/gnu/dts/include/dt-bindings/input/linux-event-codes.h b/sys/gnu/dts/include/dt-bindings/input/linux-event-codes.h deleted file mode 100644 index 6923dc7e029..00000000000 --- a/sys/gnu/dts/include/dt-bindings/input/linux-event-codes.h +++ /dev/null @@ -1,944 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -/* - * Input event codes - * - * *** IMPORTANT *** - * This file is not only included from C-code but also from devicetree source - * files. As such this file MUST only contain comments and defines. - * - * Copyright (c) 1999-2002 Vojtech Pavlik - * Copyright (c) 2015 Hans de Goede - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#ifndef _UAPI_INPUT_EVENT_CODES_H -#define _UAPI_INPUT_EVENT_CODES_H - -/* - * Device properties and quirks - */ - -#define INPUT_PROP_POINTER 0x00 /* needs a pointer */ -#define INPUT_PROP_DIRECT 0x01 /* direct input devices */ -#define INPUT_PROP_BUTTONPAD 0x02 /* has button(s) under pad */ -#define INPUT_PROP_SEMI_MT 0x03 /* touch rectangle only */ -#define INPUT_PROP_TOPBUTTONPAD 0x04 /* softbuttons at top of pad */ -#define INPUT_PROP_POINTING_STICK 0x05 /* is a pointing stick */ -#define INPUT_PROP_ACCELEROMETER 0x06 /* has accelerometer */ - -#define INPUT_PROP_MAX 0x1f -#define INPUT_PROP_CNT (INPUT_PROP_MAX + 1) - -/* - * Event types - */ - -#define EV_SYN 0x00 -#define EV_KEY 0x01 -#define EV_REL 0x02 -#define EV_ABS 0x03 -#define EV_MSC 0x04 -#define EV_SW 0x05 -#define EV_LED 0x11 -#define EV_SND 0x12 -#define EV_REP 0x14 -#define EV_FF 0x15 -#define EV_PWR 0x16 -#define EV_FF_STATUS 0x17 -#define EV_MAX 0x1f -#define EV_CNT (EV_MAX+1) - -/* - * Synchronization events. - */ - -#define SYN_REPORT 0 -#define SYN_CONFIG 1 -#define SYN_MT_REPORT 2 -#define SYN_DROPPED 3 -#define SYN_MAX 0xf -#define SYN_CNT (SYN_MAX+1) - -/* - * Keys and buttons - * - * Most of the keys/buttons are modeled after USB HUT 1.12 - * (see http://www.usb.org/developers/hidpage). - * Abbreviations in the comments: - * AC - Application Control - * AL - Application Launch Button - * SC - System Control - */ - -#define KEY_RESERVED 0 -#define KEY_ESC 1 -#define KEY_1 2 -#define KEY_2 3 -#define KEY_3 4 -#define KEY_4 5 -#define KEY_5 6 -#define KEY_6 7 -#define KEY_7 8 -#define KEY_8 9 -#define KEY_9 10 -#define KEY_0 11 -#define KEY_MINUS 12 -#define KEY_EQUAL 13 -#define KEY_BACKSPACE 14 -#define KEY_TAB 15 -#define KEY_Q 16 -#define KEY_W 17 -#define KEY_E 18 -#define KEY_R 19 -#define KEY_T 20 -#define KEY_Y 21 -#define KEY_U 22 -#define KEY_I 23 -#define KEY_O 24 -#define KEY_P 25 -#define KEY_LEFTBRACE 26 -#define KEY_RIGHTBRACE 27 -#define KEY_ENTER 28 -#define KEY_LEFTCTRL 29 -#define KEY_A 30 -#define KEY_S 31 -#define KEY_D 32 -#define KEY_F 33 -#define KEY_G 34 -#define KEY_H 35 -#define KEY_J 36 -#define KEY_K 37 -#define KEY_L 38 -#define KEY_SEMICOLON 39 -#define KEY_APOSTROPHE 40 -#define KEY_GRAVE 41 -#define KEY_LEFTSHIFT 42 -#define KEY_BACKSLASH 43 -#define KEY_Z 44 -#define KEY_X 45 -#define KEY_C 46 -#define KEY_V 47 -#define KEY_B 48 -#define KEY_N 49 -#define KEY_M 50 -#define KEY_COMMA 51 -#define KEY_DOT 52 -#define KEY_SLASH 53 -#define KEY_RIGHTSHIFT 54 -#define KEY_KPASTERISK 55 -#define KEY_LEFTALT 56 -#define KEY_SPACE 57 -#define KEY_CAPSLOCK 58 -#define KEY_F1 59 -#define KEY_F2 60 -#define KEY_F3 61 -#define KEY_F4 62 -#define KEY_F5 63 -#define KEY_F6 64 -#define KEY_F7 65 -#define KEY_F8 66 -#define KEY_F9 67 -#define KEY_F10 68 -#define KEY_NUMLOCK 69 -#define KEY_SCROLLLOCK 70 -#define KEY_KP7 71 -#define KEY_KP8 72 -#define KEY_KP9 73 -#define KEY_KPMINUS 74 -#define KEY_KP4 75 -#define KEY_KP5 76 -#define KEY_KP6 77 -#define KEY_KPPLUS 78 -#define KEY_KP1 79 -#define KEY_KP2 80 -#define KEY_KP3 81 -#define KEY_KP0 82 -#define KEY_KPDOT 83 - -#define KEY_ZENKAKUHANKAKU 85 -#define KEY_102ND 86 -#define KEY_F11 87 -#define KEY_F12 88 -#define KEY_RO 89 -#define KEY_KATAKANA 90 -#define KEY_HIRAGANA 91 -#define KEY_HENKAN 92 -#define KEY_KATAKANAHIRAGANA 93 -#define KEY_MUHENKAN 94 -#define KEY_KPJPCOMMA 95 -#define KEY_KPENTER 96 -#define KEY_RIGHTCTRL 97 -#define KEY_KPSLASH 98 -#define KEY_SYSRQ 99 -#define KEY_RIGHTALT 100 -#define KEY_LINEFEED 101 -#define KEY_HOME 102 -#define KEY_UP 103 -#define KEY_PAGEUP 104 -#define KEY_LEFT 105 -#define KEY_RIGHT 106 -#define KEY_END 107 -#define KEY_DOWN 108 -#define KEY_PAGEDOWN 109 -#define KEY_INSERT 110 -#define KEY_DELETE 111 -#define KEY_MACRO 112 -#define KEY_MUTE 113 -#define KEY_VOLUMEDOWN 114 -#define KEY_VOLUMEUP 115 -#define KEY_POWER 116 /* SC System Power Down */ -#define KEY_KPEQUAL 117 -#define KEY_KPPLUSMINUS 118 -#define KEY_PAUSE 119 -#define KEY_SCALE 120 /* AL Compiz Scale (Expose) */ - -#define KEY_KPCOMMA 121 -#define KEY_HANGEUL 122 -#define KEY_HANGUEL KEY_HANGEUL -#define KEY_HANJA 123 -#define KEY_YEN 124 -#define KEY_LEFTMETA 125 -#define KEY_RIGHTMETA 126 -#define KEY_COMPOSE 127 - -#define KEY_STOP 128 /* AC Stop */ -#define KEY_AGAIN 129 -#define KEY_PROPS 130 /* AC Properties */ -#define KEY_UNDO 131 /* AC Undo */ -#define KEY_FRONT 132 -#define KEY_COPY 133 /* AC Copy */ -#define KEY_OPEN 134 /* AC Open */ -#define KEY_PASTE 135 /* AC Paste */ -#define KEY_FIND 136 /* AC Search */ -#define KEY_CUT 137 /* AC Cut */ -#define KEY_HELP 138 /* AL Integrated Help Center */ -#define KEY_MENU 139 /* Menu (show menu) */ -#define KEY_CALC 140 /* AL Calculator */ -#define KEY_SETUP 141 -#define KEY_SLEEP 142 /* SC System Sleep */ -#define KEY_WAKEUP 143 /* System Wake Up */ -#define KEY_FILE 144 /* AL Local Machine Browser */ -#define KEY_SENDFILE 145 -#define KEY_DELETEFILE 146 -#define KEY_XFER 147 -#define KEY_PROG1 148 -#define KEY_PROG2 149 -#define KEY_WWW 150 /* AL Internet Browser */ -#define KEY_MSDOS 151 -#define KEY_COFFEE 152 /* AL Terminal Lock/Screensaver */ -#define KEY_SCREENLOCK KEY_COFFEE -#define KEY_ROTATE_DISPLAY 153 /* Display orientation for e.g. tablets */ -#define KEY_DIRECTION KEY_ROTATE_DISPLAY -#define KEY_CYCLEWINDOWS 154 -#define KEY_MAIL 155 -#define KEY_BOOKMARKS 156 /* AC Bookmarks */ -#define KEY_COMPUTER 157 -#define KEY_BACK 158 /* AC Back */ -#define KEY_FORWARD 159 /* AC Forward */ -#define KEY_CLOSECD 160 -#define KEY_EJECTCD 161 -#define KEY_EJECTCLOSECD 162 -#define KEY_NEXTSONG 163 -#define KEY_PLAYPAUSE 164 -#define KEY_PREVIOUSSONG 165 -#define KEY_STOPCD 166 -#define KEY_RECORD 167 -#define KEY_REWIND 168 -#define KEY_PHONE 169 /* Media Select Telephone */ -#define KEY_ISO 170 -#define KEY_CONFIG 171 /* AL Consumer Control Configuration */ -#define KEY_HOMEPAGE 172 /* AC Home */ -#define KEY_REFRESH 173 /* AC Refresh */ -#define KEY_EXIT 174 /* AC Exit */ -#define KEY_MOVE 175 -#define KEY_EDIT 176 -#define KEY_SCROLLUP 177 -#define KEY_SCROLLDOWN 178 -#define KEY_KPLEFTPAREN 179 -#define KEY_KPRIGHTPAREN 180 -#define KEY_NEW 181 /* AC New */ -#define KEY_REDO 182 /* AC Redo/Repeat */ - -#define KEY_F13 183 -#define KEY_F14 184 -#define KEY_F15 185 -#define KEY_F16 186 -#define KEY_F17 187 -#define KEY_F18 188 -#define KEY_F19 189 -#define KEY_F20 190 -#define KEY_F21 191 -#define KEY_F22 192 -#define KEY_F23 193 -#define KEY_F24 194 - -#define KEY_PLAYCD 200 -#define KEY_PAUSECD 201 -#define KEY_PROG3 202 -#define KEY_PROG4 203 -#define KEY_DASHBOARD 204 /* AL Dashboard */ -#define KEY_SUSPEND 205 -#define KEY_CLOSE 206 /* AC Close */ -#define KEY_PLAY 207 -#define KEY_FASTFORWARD 208 -#define KEY_BASSBOOST 209 -#define KEY_PRINT 210 /* AC Print */ -#define KEY_HP 211 -#define KEY_CAMERA 212 -#define KEY_SOUND 213 -#define KEY_QUESTION 214 -#define KEY_EMAIL 215 -#define KEY_CHAT 216 -#define KEY_SEARCH 217 -#define KEY_CONNECT 218 -#define KEY_FINANCE 219 /* AL Checkbook/Finance */ -#define KEY_SPORT 220 -#define KEY_SHOP 221 -#define KEY_ALTERASE 222 -#define KEY_CANCEL 223 /* AC Cancel */ -#define KEY_BRIGHTNESSDOWN 224 -#define KEY_BRIGHTNESSUP 225 -#define KEY_MEDIA 226 - -#define KEY_SWITCHVIDEOMODE 227 /* Cycle between available video - outputs (Monitor/LCD/TV-out/etc) */ -#define KEY_KBDILLUMTOGGLE 228 -#define KEY_KBDILLUMDOWN 229 -#define KEY_KBDILLUMUP 230 - -#define KEY_SEND 231 /* AC Send */ -#define KEY_REPLY 232 /* AC Reply */ -#define KEY_FORWARDMAIL 233 /* AC Forward Msg */ -#define KEY_SAVE 234 /* AC Save */ -#define KEY_DOCUMENTS 235 - -#define KEY_BATTERY 236 - -#define KEY_BLUETOOTH 237 -#define KEY_WLAN 238 -#define KEY_UWB 239 - -#define KEY_UNKNOWN 240 - -#define KEY_VIDEO_NEXT 241 /* drive next video source */ -#define KEY_VIDEO_PREV 242 /* drive previous video source */ -#define KEY_BRIGHTNESS_CYCLE 243 /* brightness up, after max is min */ -#define KEY_BRIGHTNESS_AUTO 244 /* Set Auto Brightness: manual - brightness control is off, - rely on ambient */ -#define KEY_BRIGHTNESS_ZERO KEY_BRIGHTNESS_AUTO -#define KEY_DISPLAY_OFF 245 /* display device to off state */ - -#define KEY_WWAN 246 /* Wireless WAN (LTE, UMTS, GSM, etc.) */ -#define KEY_WIMAX KEY_WWAN -#define KEY_RFKILL 247 /* Key that controls all radios */ - -#define KEY_MICMUTE 248 /* Mute / unmute the microphone */ - -/* Code 255 is reserved for special needs of AT keyboard driver */ - -#define BTN_MISC 0x100 -#define BTN_0 0x100 -#define BTN_1 0x101 -#define BTN_2 0x102 -#define BTN_3 0x103 -#define BTN_4 0x104 -#define BTN_5 0x105 -#define BTN_6 0x106 -#define BTN_7 0x107 -#define BTN_8 0x108 -#define BTN_9 0x109 - -#define BTN_MOUSE 0x110 -#define BTN_LEFT 0x110 -#define BTN_RIGHT 0x111 -#define BTN_MIDDLE 0x112 -#define BTN_SIDE 0x113 -#define BTN_EXTRA 0x114 -#define BTN_FORWARD 0x115 -#define BTN_BACK 0x116 -#define BTN_TASK 0x117 - -#define BTN_JOYSTICK 0x120 -#define BTN_TRIGGER 0x120 -#define BTN_THUMB 0x121 -#define BTN_THUMB2 0x122 -#define BTN_TOP 0x123 -#define BTN_TOP2 0x124 -#define BTN_PINKIE 0x125 -#define BTN_BASE 0x126 -#define BTN_BASE2 0x127 -#define BTN_BASE3 0x128 -#define BTN_BASE4 0x129 -#define BTN_BASE5 0x12a -#define BTN_BASE6 0x12b -#define BTN_DEAD 0x12f - -#define BTN_GAMEPAD 0x130 -#define BTN_SOUTH 0x130 -#define BTN_A BTN_SOUTH -#define BTN_EAST 0x131 -#define BTN_B BTN_EAST -#define BTN_C 0x132 -#define BTN_NORTH 0x133 -#define BTN_X BTN_NORTH -#define BTN_WEST 0x134 -#define BTN_Y BTN_WEST -#define BTN_Z 0x135 -#define BTN_TL 0x136 -#define BTN_TR 0x137 -#define BTN_TL2 0x138 -#define BTN_TR2 0x139 -#define BTN_SELECT 0x13a -#define BTN_START 0x13b -#define BTN_MODE 0x13c -#define BTN_THUMBL 0x13d -#define BTN_THUMBR 0x13e - -#define BTN_DIGI 0x140 -#define BTN_TOOL_PEN 0x140 -#define BTN_TOOL_RUBBER 0x141 -#define BTN_TOOL_BRUSH 0x142 -#define BTN_TOOL_PENCIL 0x143 -#define BTN_TOOL_AIRBRUSH 0x144 -#define BTN_TOOL_FINGER 0x145 -#define BTN_TOOL_MOUSE 0x146 -#define BTN_TOOL_LENS 0x147 -#define BTN_TOOL_QUINTTAP 0x148 /* Five fingers on trackpad */ -#define BTN_STYLUS3 0x149 -#define BTN_TOUCH 0x14a -#define BTN_STYLUS 0x14b -#define BTN_STYLUS2 0x14c -#define BTN_TOOL_DOUBLETAP 0x14d -#define BTN_TOOL_TRIPLETAP 0x14e -#define BTN_TOOL_QUADTAP 0x14f /* Four fingers on trackpad */ - -#define BTN_WHEEL 0x150 -#define BTN_GEAR_DOWN 0x150 -#define BTN_GEAR_UP 0x151 - -#define KEY_OK 0x160 -#define KEY_SELECT 0x161 -#define KEY_GOTO 0x162 -#define KEY_CLEAR 0x163 -#define KEY_POWER2 0x164 -#define KEY_OPTION 0x165 -#define KEY_INFO 0x166 /* AL OEM Features/Tips/Tutorial */ -#define KEY_TIME 0x167 -#define KEY_VENDOR 0x168 -#define KEY_ARCHIVE 0x169 -#define KEY_PROGRAM 0x16a /* Media Select Program Guide */ -#define KEY_CHANNEL 0x16b -#define KEY_FAVORITES 0x16c -#define KEY_EPG 0x16d -#define KEY_PVR 0x16e /* Media Select Home */ -#define KEY_MHP 0x16f -#define KEY_LANGUAGE 0x170 -#define KEY_TITLE 0x171 -#define KEY_SUBTITLE 0x172 -#define KEY_ANGLE 0x173 -#define KEY_FULL_SCREEN 0x174 /* AC View Toggle */ -#define KEY_ZOOM KEY_FULL_SCREEN -#define KEY_MODE 0x175 -#define KEY_KEYBOARD 0x176 -#define KEY_ASPECT_RATIO 0x177 /* HUTRR37: Aspect */ -#define KEY_SCREEN KEY_ASPECT_RATIO -#define KEY_PC 0x178 /* Media Select Computer */ -#define KEY_TV 0x179 /* Media Select TV */ -#define KEY_TV2 0x17a /* Media Select Cable */ -#define KEY_VCR 0x17b /* Media Select VCR */ -#define KEY_VCR2 0x17c /* VCR Plus */ -#define KEY_SAT 0x17d /* Media Select Satellite */ -#define KEY_SAT2 0x17e -#define KEY_CD 0x17f /* Media Select CD */ -#define KEY_TAPE 0x180 /* Media Select Tape */ -#define KEY_RADIO 0x181 -#define KEY_TUNER 0x182 /* Media Select Tuner */ -#define KEY_PLAYER 0x183 -#define KEY_TEXT 0x184 -#define KEY_DVD 0x185 /* Media Select DVD */ -#define KEY_AUX 0x186 -#define KEY_MP3 0x187 -#define KEY_AUDIO 0x188 /* AL Audio Browser */ -#define KEY_VIDEO 0x189 /* AL Movie Browser */ -#define KEY_DIRECTORY 0x18a -#define KEY_LIST 0x18b -#define KEY_MEMO 0x18c /* Media Select Messages */ -#define KEY_CALENDAR 0x18d -#define KEY_RED 0x18e -#define KEY_GREEN 0x18f -#define KEY_YELLOW 0x190 -#define KEY_BLUE 0x191 -#define KEY_CHANNELUP 0x192 /* Channel Increment */ -#define KEY_CHANNELDOWN 0x193 /* Channel Decrement */ -#define KEY_FIRST 0x194 -#define KEY_LAST 0x195 /* Recall Last */ -#define KEY_AB 0x196 -#define KEY_NEXT 0x197 -#define KEY_RESTART 0x198 -#define KEY_SLOW 0x199 -#define KEY_SHUFFLE 0x19a -#define KEY_BREAK 0x19b -#define KEY_PREVIOUS 0x19c -#define KEY_DIGITS 0x19d -#define KEY_TEEN 0x19e -#define KEY_TWEN 0x19f -#define KEY_VIDEOPHONE 0x1a0 /* Media Select Video Phone */ -#define KEY_GAMES 0x1a1 /* Media Select Games */ -#define KEY_ZOOMIN 0x1a2 /* AC Zoom In */ -#define KEY_ZOOMOUT 0x1a3 /* AC Zoom Out */ -#define KEY_ZOOMRESET 0x1a4 /* AC Zoom */ -#define KEY_WORDPROCESSOR 0x1a5 /* AL Word Processor */ -#define KEY_EDITOR 0x1a6 /* AL Text Editor */ -#define KEY_SPREADSHEET 0x1a7 /* AL Spreadsheet */ -#define KEY_GRAPHICSEDITOR 0x1a8 /* AL Graphics Editor */ -#define KEY_PRESENTATION 0x1a9 /* AL Presentation App */ -#define KEY_DATABASE 0x1aa /* AL Database App */ -#define KEY_NEWS 0x1ab /* AL Newsreader */ -#define KEY_VOICEMAIL 0x1ac /* AL Voicemail */ -#define KEY_ADDRESSBOOK 0x1ad /* AL Contacts/Address Book */ -#define KEY_MESSENGER 0x1ae /* AL Instant Messaging */ -#define KEY_DISPLAYTOGGLE 0x1af /* Turn display (LCD) on and off */ -#define KEY_BRIGHTNESS_TOGGLE KEY_DISPLAYTOGGLE -#define KEY_SPELLCHECK 0x1b0 /* AL Spell Check */ -#define KEY_LOGOFF 0x1b1 /* AL Logoff */ - -#define KEY_DOLLAR 0x1b2 -#define KEY_EURO 0x1b3 - -#define KEY_FRAMEBACK 0x1b4 /* Consumer - transport controls */ -#define KEY_FRAMEFORWARD 0x1b5 -#define KEY_CONTEXT_MENU 0x1b6 /* GenDesc - system context menu */ -#define KEY_MEDIA_REPEAT 0x1b7 /* Consumer - transport control */ -#define KEY_10CHANNELSUP 0x1b8 /* 10 channels up (10+) */ -#define KEY_10CHANNELSDOWN 0x1b9 /* 10 channels down (10-) */ -#define KEY_IMAGES 0x1ba /* AL Image Browser */ - -#define KEY_DEL_EOL 0x1c0 -#define KEY_DEL_EOS 0x1c1 -#define KEY_INS_LINE 0x1c2 -#define KEY_DEL_LINE 0x1c3 - -#define KEY_FN 0x1d0 -#define KEY_FN_ESC 0x1d1 -#define KEY_FN_F1 0x1d2 -#define KEY_FN_F2 0x1d3 -#define KEY_FN_F3 0x1d4 -#define KEY_FN_F4 0x1d5 -#define KEY_FN_F5 0x1d6 -#define KEY_FN_F6 0x1d7 -#define KEY_FN_F7 0x1d8 -#define KEY_FN_F8 0x1d9 -#define KEY_FN_F9 0x1da -#define KEY_FN_F10 0x1db -#define KEY_FN_F11 0x1dc -#define KEY_FN_F12 0x1dd -#define KEY_FN_1 0x1de -#define KEY_FN_2 0x1df -#define KEY_FN_D 0x1e0 -#define KEY_FN_E 0x1e1 -#define KEY_FN_F 0x1e2 -#define KEY_FN_S 0x1e3 -#define KEY_FN_B 0x1e4 - -#define KEY_BRL_DOT1 0x1f1 -#define KEY_BRL_DOT2 0x1f2 -#define KEY_BRL_DOT3 0x1f3 -#define KEY_BRL_DOT4 0x1f4 -#define KEY_BRL_DOT5 0x1f5 -#define KEY_BRL_DOT6 0x1f6 -#define KEY_BRL_DOT7 0x1f7 -#define KEY_BRL_DOT8 0x1f8 -#define KEY_BRL_DOT9 0x1f9 -#define KEY_BRL_DOT10 0x1fa - -#define KEY_NUMERIC_0 0x200 /* used by phones, remote controls, */ -#define KEY_NUMERIC_1 0x201 /* and other keypads */ -#define KEY_NUMERIC_2 0x202 -#define KEY_NUMERIC_3 0x203 -#define KEY_NUMERIC_4 0x204 -#define KEY_NUMERIC_5 0x205 -#define KEY_NUMERIC_6 0x206 -#define KEY_NUMERIC_7 0x207 -#define KEY_NUMERIC_8 0x208 -#define KEY_NUMERIC_9 0x209 -#define KEY_NUMERIC_STAR 0x20a -#define KEY_NUMERIC_POUND 0x20b -#define KEY_NUMERIC_A 0x20c /* Phone key A - HUT Telephony 0xb9 */ -#define KEY_NUMERIC_B 0x20d -#define KEY_NUMERIC_C 0x20e -#define KEY_NUMERIC_D 0x20f - -#define KEY_CAMERA_FOCUS 0x210 -#define KEY_WPS_BUTTON 0x211 /* WiFi Protected Setup key */ - -#define KEY_TOUCHPAD_TOGGLE 0x212 /* Request switch touchpad on or off */ -#define KEY_TOUCHPAD_ON 0x213 -#define KEY_TOUCHPAD_OFF 0x214 - -#define KEY_CAMERA_ZOOMIN 0x215 -#define KEY_CAMERA_ZOOMOUT 0x216 -#define KEY_CAMERA_UP 0x217 -#define KEY_CAMERA_DOWN 0x218 -#define KEY_CAMERA_LEFT 0x219 -#define KEY_CAMERA_RIGHT 0x21a - -#define KEY_ATTENDANT_ON 0x21b -#define KEY_ATTENDANT_OFF 0x21c -#define KEY_ATTENDANT_TOGGLE 0x21d /* Attendant call on or off */ -#define KEY_LIGHTS_TOGGLE 0x21e /* Reading light on or off */ - -#define BTN_DPAD_UP 0x220 -#define BTN_DPAD_DOWN 0x221 -#define BTN_DPAD_LEFT 0x222 -#define BTN_DPAD_RIGHT 0x223 - -#define KEY_ALS_TOGGLE 0x230 /* Ambient light sensor */ -#define KEY_ROTATE_LOCK_TOGGLE 0x231 /* Display rotation lock */ - -#define KEY_BUTTONCONFIG 0x240 /* AL Button Configuration */ -#define KEY_TASKMANAGER 0x241 /* AL Task/Project Manager */ -#define KEY_JOURNAL 0x242 /* AL Log/Journal/Timecard */ -#define KEY_CONTROLPANEL 0x243 /* AL Control Panel */ -#define KEY_APPSELECT 0x244 /* AL Select Task/Application */ -#define KEY_SCREENSAVER 0x245 /* AL Screen Saver */ -#define KEY_VOICECOMMAND 0x246 /* Listening Voice Command */ -#define KEY_ASSISTANT 0x247 /* AL Context-aware desktop assistant */ -#define KEY_KBD_LAYOUT_NEXT 0x248 /* AC Next Keyboard Layout Select */ - -#define KEY_BRIGHTNESS_MIN 0x250 /* Set Brightness to Minimum */ -#define KEY_BRIGHTNESS_MAX 0x251 /* Set Brightness to Maximum */ - -#define KEY_KBDINPUTASSIST_PREV 0x260 -#define KEY_KBDINPUTASSIST_NEXT 0x261 -#define KEY_KBDINPUTASSIST_PREVGROUP 0x262 -#define KEY_KBDINPUTASSIST_NEXTGROUP 0x263 -#define KEY_KBDINPUTASSIST_ACCEPT 0x264 -#define KEY_KBDINPUTASSIST_CANCEL 0x265 - -/* Diagonal movement keys */ -#define KEY_RIGHT_UP 0x266 -#define KEY_RIGHT_DOWN 0x267 -#define KEY_LEFT_UP 0x268 -#define KEY_LEFT_DOWN 0x269 - -#define KEY_ROOT_MENU 0x26a /* Show Device's Root Menu */ -/* Show Top Menu of the Media (e.g. DVD) */ -#define KEY_MEDIA_TOP_MENU 0x26b -#define KEY_NUMERIC_11 0x26c -#define KEY_NUMERIC_12 0x26d -/* - * Toggle Audio Description: refers to an audio service that helps blind and - * visually impaired consumers understand the action in a program. Note: in - * some countries this is referred to as "Video Description". - */ -#define KEY_AUDIO_DESC 0x26e -#define KEY_3D_MODE 0x26f -#define KEY_NEXT_FAVORITE 0x270 -#define KEY_STOP_RECORD 0x271 -#define KEY_PAUSE_RECORD 0x272 -#define KEY_VOD 0x273 /* Video on Demand */ -#define KEY_UNMUTE 0x274 -#define KEY_FASTREVERSE 0x275 -#define KEY_SLOWREVERSE 0x276 -/* - * Control a data application associated with the currently viewed channel, - * e.g. teletext or data broadcast application (MHEG, MHP, HbbTV, etc.) - */ -#define KEY_DATA 0x277 -#define KEY_ONSCREEN_KEYBOARD 0x278 -/* Electronic privacy screen control */ -#define KEY_PRIVACY_SCREEN_TOGGLE 0x279 - -/* Select an area of screen to be copied */ -#define KEY_SELECTIVE_SCREENSHOT 0x27a - -/* - * Some keyboards have keys which do not have a defined meaning, these keys - * are intended to be programmed / bound to macros by the user. For most - * keyboards with these macro-keys the key-sequence to inject, or action to - * take, is all handled by software on the host side. So from the kernel's - * point of view these are just normal keys. - * - * The KEY_MACRO# codes below are intended for such keys, which may be labeled - * e.g. G1-G18, or S1 - S30. The KEY_MACRO# codes MUST NOT be used for keys - * where the marking on the key does indicate a defined meaning / purpose. - * - * The KEY_MACRO# codes MUST also NOT be used as fallback for when no existing - * KEY_FOO define matches the marking / purpose. In this case a new KEY_FOO - * define MUST be added. - */ -#define KEY_MACRO1 0x290 -#define KEY_MACRO2 0x291 -#define KEY_MACRO3 0x292 -#define KEY_MACRO4 0x293 -#define KEY_MACRO5 0x294 -#define KEY_MACRO6 0x295 -#define KEY_MACRO7 0x296 -#define KEY_MACRO8 0x297 -#define KEY_MACRO9 0x298 -#define KEY_MACRO10 0x299 -#define KEY_MACRO11 0x29a -#define KEY_MACRO12 0x29b -#define KEY_MACRO13 0x29c -#define KEY_MACRO14 0x29d -#define KEY_MACRO15 0x29e -#define KEY_MACRO16 0x29f -#define KEY_MACRO17 0x2a0 -#define KEY_MACRO18 0x2a1 -#define KEY_MACRO19 0x2a2 -#define KEY_MACRO20 0x2a3 -#define KEY_MACRO21 0x2a4 -#define KEY_MACRO22 0x2a5 -#define KEY_MACRO23 0x2a6 -#define KEY_MACRO24 0x2a7 -#define KEY_MACRO25 0x2a8 -#define KEY_MACRO26 0x2a9 -#define KEY_MACRO27 0x2aa -#define KEY_MACRO28 0x2ab -#define KEY_MACRO29 0x2ac -#define KEY_MACRO30 0x2ad - -/* - * Some keyboards with the macro-keys described above have some extra keys - * for controlling the host-side software responsible for the macro handling: - * -A macro recording start/stop key. Note that not all keyboards which emit - * KEY_MACRO_RECORD_START will also emit KEY_MACRO_RECORD_STOP if - * KEY_MACRO_RECORD_STOP is not advertised, then KEY_MACRO_RECORD_START - * should be interpreted as a recording start/stop toggle; - * -Keys for switching between different macro (pre)sets, either a key for - * cycling through the configured presets or keys to directly select a preset. - */ -#define KEY_MACRO_RECORD_START 0x2b0 -#define KEY_MACRO_RECORD_STOP 0x2b1 -#define KEY_MACRO_PRESET_CYCLE 0x2b2 -#define KEY_MACRO_PRESET1 0x2b3 -#define KEY_MACRO_PRESET2 0x2b4 -#define KEY_MACRO_PRESET3 0x2b5 - -/* - * Some keyboards have a buildin LCD panel where the contents are controlled - * by the host. Often these have a number of keys directly below the LCD - * intended for controlling a menu shown on the LCD. These keys often don't - * have any labeling so we just name them KEY_KBD_LCD_MENU# - */ -#define KEY_KBD_LCD_MENU1 0x2b8 -#define KEY_KBD_LCD_MENU2 0x2b9 -#define KEY_KBD_LCD_MENU3 0x2ba -#define KEY_KBD_LCD_MENU4 0x2bb -#define KEY_KBD_LCD_MENU5 0x2bc - -#define BTN_TRIGGER_HAPPY 0x2c0 -#define BTN_TRIGGER_HAPPY1 0x2c0 -#define BTN_TRIGGER_HAPPY2 0x2c1 -#define BTN_TRIGGER_HAPPY3 0x2c2 -#define BTN_TRIGGER_HAPPY4 0x2c3 -#define BTN_TRIGGER_HAPPY5 0x2c4 -#define BTN_TRIGGER_HAPPY6 0x2c5 -#define BTN_TRIGGER_HAPPY7 0x2c6 -#define BTN_TRIGGER_HAPPY8 0x2c7 -#define BTN_TRIGGER_HAPPY9 0x2c8 -#define BTN_TRIGGER_HAPPY10 0x2c9 -#define BTN_TRIGGER_HAPPY11 0x2ca -#define BTN_TRIGGER_HAPPY12 0x2cb -#define BTN_TRIGGER_HAPPY13 0x2cc -#define BTN_TRIGGER_HAPPY14 0x2cd -#define BTN_TRIGGER_HAPPY15 0x2ce -#define BTN_TRIGGER_HAPPY16 0x2cf -#define BTN_TRIGGER_HAPPY17 0x2d0 -#define BTN_TRIGGER_HAPPY18 0x2d1 -#define BTN_TRIGGER_HAPPY19 0x2d2 -#define BTN_TRIGGER_HAPPY20 0x2d3 -#define BTN_TRIGGER_HAPPY21 0x2d4 -#define BTN_TRIGGER_HAPPY22 0x2d5 -#define BTN_TRIGGER_HAPPY23 0x2d6 -#define BTN_TRIGGER_HAPPY24 0x2d7 -#define BTN_TRIGGER_HAPPY25 0x2d8 -#define BTN_TRIGGER_HAPPY26 0x2d9 -#define BTN_TRIGGER_HAPPY27 0x2da -#define BTN_TRIGGER_HAPPY28 0x2db -#define BTN_TRIGGER_HAPPY29 0x2dc -#define BTN_TRIGGER_HAPPY30 0x2dd -#define BTN_TRIGGER_HAPPY31 0x2de -#define BTN_TRIGGER_HAPPY32 0x2df -#define BTN_TRIGGER_HAPPY33 0x2e0 -#define BTN_TRIGGER_HAPPY34 0x2e1 -#define BTN_TRIGGER_HAPPY35 0x2e2 -#define BTN_TRIGGER_HAPPY36 0x2e3 -#define BTN_TRIGGER_HAPPY37 0x2e4 -#define BTN_TRIGGER_HAPPY38 0x2e5 -#define BTN_TRIGGER_HAPPY39 0x2e6 -#define BTN_TRIGGER_HAPPY40 0x2e7 - -/* We avoid low common keys in module aliases so they don't get huge. */ -#define KEY_MIN_INTERESTING KEY_MUTE -#define KEY_MAX 0x2ff -#define KEY_CNT (KEY_MAX+1) - -/* - * Relative axes - */ - -#define REL_X 0x00 -#define REL_Y 0x01 -#define REL_Z 0x02 -#define REL_RX 0x03 -#define REL_RY 0x04 -#define REL_RZ 0x05 -#define REL_HWHEEL 0x06 -#define REL_DIAL 0x07 -#define REL_WHEEL 0x08 -#define REL_MISC 0x09 -/* - * 0x0a is reserved and should not be used in input drivers. - * It was used by HID as REL_MISC+1 and userspace needs to detect if - * the next REL_* event is correct or is just REL_MISC + n. - * We define here REL_RESERVED so userspace can rely on it and detect - * the situation described above. - */ -#define REL_RESERVED 0x0a -#define REL_WHEEL_HI_RES 0x0b -#define REL_HWHEEL_HI_RES 0x0c -#define REL_MAX 0x0f -#define REL_CNT (REL_MAX+1) - -/* - * Absolute axes - */ - -#define ABS_X 0x00 -#define ABS_Y 0x01 -#define ABS_Z 0x02 -#define ABS_RX 0x03 -#define ABS_RY 0x04 -#define ABS_RZ 0x05 -#define ABS_THROTTLE 0x06 -#define ABS_RUDDER 0x07 -#define ABS_WHEEL 0x08 -#define ABS_GAS 0x09 -#define ABS_BRAKE 0x0a -#define ABS_HAT0X 0x10 -#define ABS_HAT0Y 0x11 -#define ABS_HAT1X 0x12 -#define ABS_HAT1Y 0x13 -#define ABS_HAT2X 0x14 -#define ABS_HAT2Y 0x15 -#define ABS_HAT3X 0x16 -#define ABS_HAT3Y 0x17 -#define ABS_PRESSURE 0x18 -#define ABS_DISTANCE 0x19 -#define ABS_TILT_X 0x1a -#define ABS_TILT_Y 0x1b -#define ABS_TOOL_WIDTH 0x1c - -#define ABS_VOLUME 0x20 - -#define ABS_MISC 0x28 - -/* - * 0x2e is reserved and should not be used in input drivers. - * It was used by HID as ABS_MISC+6 and userspace needs to detect if - * the next ABS_* event is correct or is just ABS_MISC + n. - * We define here ABS_RESERVED so userspace can rely on it and detect - * the situation described above. - */ -#define ABS_RESERVED 0x2e - -#define ABS_MT_SLOT 0x2f /* MT slot being modified */ -#define ABS_MT_TOUCH_MAJOR 0x30 /* Major axis of touching ellipse */ -#define ABS_MT_TOUCH_MINOR 0x31 /* Minor axis (omit if circular) */ -#define ABS_MT_WIDTH_MAJOR 0x32 /* Major axis of approaching ellipse */ -#define ABS_MT_WIDTH_MINOR 0x33 /* Minor axis (omit if circular) */ -#define ABS_MT_ORIENTATION 0x34 /* Ellipse orientation */ -#define ABS_MT_POSITION_X 0x35 /* Center X touch position */ -#define ABS_MT_POSITION_Y 0x36 /* Center Y touch position */ -#define ABS_MT_TOOL_TYPE 0x37 /* Type of touching device */ -#define ABS_MT_BLOB_ID 0x38 /* Group a set of packets as a blob */ -#define ABS_MT_TRACKING_ID 0x39 /* Unique ID of initiated contact */ -#define ABS_MT_PRESSURE 0x3a /* Pressure on contact area */ -#define ABS_MT_DISTANCE 0x3b /* Contact hover distance */ -#define ABS_MT_TOOL_X 0x3c /* Center X tool position */ -#define ABS_MT_TOOL_Y 0x3d /* Center Y tool position */ - - -#define ABS_MAX 0x3f -#define ABS_CNT (ABS_MAX+1) - -/* - * Switch events - */ - -#define SW_LID 0x00 /* set = lid shut */ -#define SW_TABLET_MODE 0x01 /* set = tablet mode */ -#define SW_HEADPHONE_INSERT 0x02 /* set = inserted */ -#define SW_RFKILL_ALL 0x03 /* rfkill master switch, type "any" - set = radio enabled */ -#define SW_RADIO SW_RFKILL_ALL /* deprecated */ -#define SW_MICROPHONE_INSERT 0x04 /* set = inserted */ -#define SW_DOCK 0x05 /* set = plugged into dock */ -#define SW_LINEOUT_INSERT 0x06 /* set = inserted */ -#define SW_JACK_PHYSICAL_INSERT 0x07 /* set = mechanical switch set */ -#define SW_VIDEOOUT_INSERT 0x08 /* set = inserted */ -#define SW_CAMERA_LENS_COVER 0x09 /* set = lens covered */ -#define SW_KEYPAD_SLIDE 0x0a /* set = keypad slide out */ -#define SW_FRONT_PROXIMITY 0x0b /* set = front proximity sensor active */ -#define SW_ROTATE_LOCK 0x0c /* set = rotate locked/disabled */ -#define SW_LINEIN_INSERT 0x0d /* set = inserted */ -#define SW_MUTE_DEVICE 0x0e /* set = device disabled */ -#define SW_PEN_INSERTED 0x0f /* set = pen inserted */ -#define SW_MAX 0x0f -#define SW_CNT (SW_MAX+1) - -/* - * Misc events - */ - -#define MSC_SERIAL 0x00 -#define MSC_PULSELED 0x01 -#define MSC_GESTURE 0x02 -#define MSC_RAW 0x03 -#define MSC_SCAN 0x04 -#define MSC_TIMESTAMP 0x05 -#define MSC_MAX 0x07 -#define MSC_CNT (MSC_MAX+1) - -/* - * LEDs - */ - -#define LED_NUML 0x00 -#define LED_CAPSL 0x01 -#define LED_SCROLLL 0x02 -#define LED_COMPOSE 0x03 -#define LED_KANA 0x04 -#define LED_SLEEP 0x05 -#define LED_SUSPEND 0x06 -#define LED_MUTE 0x07 -#define LED_MISC 0x08 -#define LED_MAIL 0x09 -#define LED_CHARGING 0x0a -#define LED_MAX 0x0f -#define LED_CNT (LED_MAX+1) - -/* - * Autorepeat values - */ - -#define REP_DELAY 0x00 -#define REP_PERIOD 0x01 -#define REP_MAX 0x01 -#define REP_CNT (REP_MAX+1) - -/* - * Sounds - */ - -#define SND_CLICK 0x00 -#define SND_BELL 0x01 -#define SND_TONE 0x02 -#define SND_MAX 0x07 -#define SND_CNT (SND_MAX+1) - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/input/ti-drv260x.h b/sys/gnu/dts/include/dt-bindings/input/ti-drv260x.h deleted file mode 100644 index af71082dd18..00000000000 --- a/sys/gnu/dts/include/dt-bindings/input/ti-drv260x.h +++ /dev/null @@ -1,28 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * DRV260X haptics driver family - * - * Author: Dan Murphy - * - * Copyright: (C) 2014 Texas Instruments, Inc. - */ - -#ifndef _DT_BINDINGS_TI_DRV260X_H -#define _DT_BINDINGS_TI_DRV260X_H - -/* Calibration Types */ -#define DRV260X_LRA_MODE 0x00 -#define DRV260X_LRA_NO_CAL_MODE 0x01 -#define DRV260X_ERM_MODE 0x02 - -/* Library Selection */ -#define DRV260X_LIB_EMPTY 0x00 -#define DRV260X_ERM_LIB_A 0x01 -#define DRV260X_ERM_LIB_B 0x02 -#define DRV260X_ERM_LIB_C 0x03 -#define DRV260X_ERM_LIB_D 0x04 -#define DRV260X_ERM_LIB_E 0x05 -#define DRV260X_LIB_LRA 0x06 -#define DRV260X_ERM_LIB_F 0x07 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/interconnect/qcom,msm8916.h b/sys/gnu/dts/include/dt-bindings/interconnect/qcom,msm8916.h deleted file mode 100644 index 359a75feb19..00000000000 --- a/sys/gnu/dts/include/dt-bindings/interconnect/qcom,msm8916.h +++ /dev/null @@ -1,100 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Qualcomm interconnect IDs - * - * Copyright (c) 2019, Linaro Ltd. - * Author: Georgi Djakov - */ - -#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_MSM8916_H -#define __DT_BINDINGS_INTERCONNECT_QCOM_MSM8916_H - -#define BIMC_SNOC_SLV 0 -#define MASTER_JPEG 1 -#define MASTER_MDP_PORT0 2 -#define MASTER_QDSS_BAM 3 -#define MASTER_QDSS_ETR 4 -#define MASTER_SNOC_CFG 5 -#define MASTER_VFE 6 -#define MASTER_VIDEO_P0 7 -#define SNOC_MM_INT_0 8 -#define SNOC_MM_INT_1 9 -#define SNOC_MM_INT_2 10 -#define SNOC_MM_INT_BIMC 11 -#define PCNOC_SNOC_SLV 12 -#define SLAVE_APSS 13 -#define SLAVE_CATS_128 14 -#define SLAVE_OCMEM_64 15 -#define SLAVE_IMEM 16 -#define SLAVE_QDSS_STM 17 -#define SLAVE_SRVC_SNOC 18 -#define SNOC_BIMC_0_MAS 19 -#define SNOC_BIMC_1_MAS 20 -#define SNOC_INT_0 21 -#define SNOC_INT_1 22 -#define SNOC_INT_BIMC 23 -#define SNOC_PCNOC_MAS 24 -#define SNOC_QDSS_INT 25 - -#define BIMC_SNOC_MAS 0 -#define MASTER_AMPSS_M0 1 -#define MASTER_GRAPHICS_3D 2 -#define MASTER_TCU0 3 -#define MASTER_TCU1 4 -#define SLAVE_AMPSS_L2 5 -#define SLAVE_EBI_CH0 6 -#define SNOC_BIMC_0_SLV 7 -#define SNOC_BIMC_1_SLV 8 - -#define MASTER_BLSP_1 0 -#define MASTER_DEHR 1 -#define MASTER_LPASS 2 -#define MASTER_CRYPTO_CORE0 3 -#define MASTER_SDCC_1 4 -#define MASTER_SDCC_2 5 -#define MASTER_SPDM 6 -#define MASTER_USB_HS 7 -#define PCNOC_INT_0 8 -#define PCNOC_INT_1 9 -#define PCNOC_MAS_0 10 -#define PCNOC_MAS_1 11 -#define PCNOC_SLV_0 12 -#define PCNOC_SLV_1 13 -#define PCNOC_SLV_2 14 -#define PCNOC_SLV_3 15 -#define PCNOC_SLV_4 16 -#define PCNOC_SLV_8 17 -#define PCNOC_SLV_9 18 -#define PCNOC_SNOC_MAS 19 -#define SLAVE_BIMC_CFG 20 -#define SLAVE_BLSP_1 21 -#define SLAVE_BOOT_ROM 22 -#define SLAVE_CAMERA_CFG 23 -#define SLAVE_CLK_CTL 24 -#define SLAVE_CRYPTO_0_CFG 25 -#define SLAVE_DEHR_CFG 26 -#define SLAVE_DISPLAY_CFG 27 -#define SLAVE_GRAPHICS_3D_CFG 28 -#define SLAVE_IMEM_CFG 29 -#define SLAVE_LPASS 30 -#define SLAVE_MPM 31 -#define SLAVE_MSG_RAM 32 -#define SLAVE_MSS 33 -#define SLAVE_PDM 34 -#define SLAVE_PMIC_ARB 35 -#define SLAVE_PCNOC_CFG 36 -#define SLAVE_PRNG 37 -#define SLAVE_QDSS_CFG 38 -#define SLAVE_RBCPR_CFG 39 -#define SLAVE_SDCC_1 40 -#define SLAVE_SDCC_2 41 -#define SLAVE_SECURITY 42 -#define SLAVE_SNOC_CFG 43 -#define SLAVE_SPDM 44 -#define SLAVE_TCSR 45 -#define SLAVE_TLMM 46 -#define SLAVE_USB_HS 47 -#define SLAVE_VENUS_CFG 48 -#define SNOC_PCNOC_SLV 49 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/interconnect/qcom,msm8974.h b/sys/gnu/dts/include/dt-bindings/interconnect/qcom,msm8974.h deleted file mode 100644 index e65ae27ffff..00000000000 --- a/sys/gnu/dts/include/dt-bindings/interconnect/qcom,msm8974.h +++ /dev/null @@ -1,146 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) */ -/* - * Qualcomm msm8974 interconnect IDs - * - * Copyright (c) 2019 Brian Masney - */ - -#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_MSM8974_H -#define __DT_BINDINGS_INTERCONNECT_QCOM_MSM8974_H - -#define BIMC_MAS_AMPSS_M0 0 -#define BIMC_MAS_AMPSS_M1 1 -#define BIMC_MAS_MSS_PROC 2 -#define BIMC_TO_MNOC 3 -#define BIMC_TO_SNOC 4 -#define BIMC_SLV_EBI_CH0 5 -#define BIMC_SLV_AMPSS_L2 6 - -#define CNOC_MAS_RPM_INST 0 -#define CNOC_MAS_RPM_DATA 1 -#define CNOC_MAS_RPM_SYS 2 -#define CNOC_MAS_DEHR 3 -#define CNOC_MAS_QDSS_DAP 4 -#define CNOC_MAS_SPDM 5 -#define CNOC_MAS_TIC 6 -#define CNOC_SLV_CLK_CTL 7 -#define CNOC_SLV_CNOC_MSS 8 -#define CNOC_SLV_SECURITY 9 -#define CNOC_SLV_TCSR 10 -#define CNOC_SLV_TLMM 11 -#define CNOC_SLV_CRYPTO_0_CFG 12 -#define CNOC_SLV_CRYPTO_1_CFG 13 -#define CNOC_SLV_IMEM_CFG 14 -#define CNOC_SLV_MESSAGE_RAM 15 -#define CNOC_SLV_BIMC_CFG 16 -#define CNOC_SLV_BOOT_ROM 17 -#define CNOC_SLV_PMIC_ARB 18 -#define CNOC_SLV_SPDM_WRAPPER 19 -#define CNOC_SLV_DEHR_CFG 20 -#define CNOC_SLV_MPM 21 -#define CNOC_SLV_QDSS_CFG 22 -#define CNOC_SLV_RBCPR_CFG 23 -#define CNOC_SLV_RBCPR_QDSS_APU_CFG 24 -#define CNOC_TO_SNOC 25 -#define CNOC_SLV_CNOC_ONOC_CFG 26 -#define CNOC_SLV_CNOC_MNOC_MMSS_CFG 27 -#define CNOC_SLV_CNOC_MNOC_CFG 28 -#define CNOC_SLV_PNOC_CFG 29 -#define CNOC_SLV_SNOC_MPU_CFG 30 -#define CNOC_SLV_SNOC_CFG 31 -#define CNOC_SLV_EBI1_DLL_CFG 32 -#define CNOC_SLV_PHY_APU_CFG 33 -#define CNOC_SLV_EBI1_PHY_CFG 34 -#define CNOC_SLV_RPM 35 -#define CNOC_SLV_SERVICE_CNOC 36 - -#define MNOC_MAS_GRAPHICS_3D 0 -#define MNOC_MAS_JPEG 1 -#define MNOC_MAS_MDP_PORT0 2 -#define MNOC_MAS_VIDEO_P0 3 -#define MNOC_MAS_VIDEO_P1 4 -#define MNOC_MAS_VFE 5 -#define MNOC_TO_CNOC 6 -#define MNOC_TO_BIMC 7 -#define MNOC_SLV_CAMERA_CFG 8 -#define MNOC_SLV_DISPLAY_CFG 9 -#define MNOC_SLV_OCMEM_CFG 10 -#define MNOC_SLV_CPR_CFG 11 -#define MNOC_SLV_CPR_XPU_CFG 12 -#define MNOC_SLV_MISC_CFG 13 -#define MNOC_SLV_MISC_XPU_CFG 14 -#define MNOC_SLV_VENUS_CFG 15 -#define MNOC_SLV_GRAPHICS_3D_CFG 16 -#define MNOC_SLV_MMSS_CLK_CFG 17 -#define MNOC_SLV_MMSS_CLK_XPU_CFG 18 -#define MNOC_SLV_MNOC_MPU_CFG 19 -#define MNOC_SLV_ONOC_MPU_CFG 20 -#define MNOC_SLV_SERVICE_MNOC 21 - -#define OCMEM_NOC_TO_OCMEM_VNOC 0 -#define OCMEM_MAS_JPEG_OCMEM 1 -#define OCMEM_MAS_MDP_OCMEM 2 -#define OCMEM_MAS_VIDEO_P0_OCMEM 3 -#define OCMEM_MAS_VIDEO_P1_OCMEM 4 -#define OCMEM_MAS_VFE_OCMEM 5 -#define OCMEM_MAS_CNOC_ONOC_CFG 6 -#define OCMEM_SLV_SERVICE_ONOC 7 -#define OCMEM_VNOC_TO_SNOC 8 -#define OCMEM_VNOC_TO_OCMEM_NOC 9 -#define OCMEM_VNOC_MAS_GFX3D 10 -#define OCMEM_SLV_OCMEM 11 - -#define PNOC_MAS_PNOC_CFG 0 -#define PNOC_MAS_SDCC_1 1 -#define PNOC_MAS_SDCC_3 2 -#define PNOC_MAS_SDCC_4 3 -#define PNOC_MAS_SDCC_2 4 -#define PNOC_MAS_TSIF 5 -#define PNOC_MAS_BAM_DMA 6 -#define PNOC_MAS_BLSP_2 7 -#define PNOC_MAS_USB_HSIC 8 -#define PNOC_MAS_BLSP_1 9 -#define PNOC_MAS_USB_HS 10 -#define PNOC_TO_SNOC 11 -#define PNOC_SLV_SDCC_1 12 -#define PNOC_SLV_SDCC_3 13 -#define PNOC_SLV_SDCC_2 14 -#define PNOC_SLV_SDCC_4 15 -#define PNOC_SLV_TSIF 16 -#define PNOC_SLV_BAM_DMA 17 -#define PNOC_SLV_BLSP_2 18 -#define PNOC_SLV_USB_HSIC 19 -#define PNOC_SLV_BLSP_1 20 -#define PNOC_SLV_USB_HS 21 -#define PNOC_SLV_PDM 22 -#define PNOC_SLV_PERIPH_APU_CFG 23 -#define PNOC_SLV_PNOC_MPU_CFG 24 -#define PNOC_SLV_PRNG 25 -#define PNOC_SLV_SERVICE_PNOC 26 - -#define SNOC_MAS_LPASS_AHB 0 -#define SNOC_MAS_QDSS_BAM 1 -#define SNOC_MAS_SNOC_CFG 2 -#define SNOC_TO_BIMC 3 -#define SNOC_TO_CNOC 4 -#define SNOC_TO_PNOC 5 -#define SNOC_TO_OCMEM_VNOC 6 -#define SNOC_MAS_CRYPTO_CORE0 7 -#define SNOC_MAS_CRYPTO_CORE1 8 -#define SNOC_MAS_LPASS_PROC 9 -#define SNOC_MAS_MSS 10 -#define SNOC_MAS_MSS_NAV 11 -#define SNOC_MAS_OCMEM_DMA 12 -#define SNOC_MAS_WCSS 13 -#define SNOC_MAS_QDSS_ETR 14 -#define SNOC_MAS_USB3 15 -#define SNOC_SLV_AMPSS 16 -#define SNOC_SLV_LPASS 17 -#define SNOC_SLV_USB3 18 -#define SNOC_SLV_WCSS 19 -#define SNOC_SLV_OCIMEM 20 -#define SNOC_SLV_SNOC_OCMEM 21 -#define SNOC_SLV_SERVICE_SNOC 22 -#define SNOC_SLV_QDSS_STM 23 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/interconnect/qcom,qcs404.h b/sys/gnu/dts/include/dt-bindings/interconnect/qcom,qcs404.h deleted file mode 100644 index 960f6e39c5f..00000000000 --- a/sys/gnu/dts/include/dt-bindings/interconnect/qcom,qcs404.h +++ /dev/null @@ -1,88 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Qualcomm interconnect IDs - * - * Copyright (c) 2019, Linaro Ltd. - * Author: Georgi Djakov - */ - -#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_QCS404_H -#define __DT_BINDINGS_INTERCONNECT_QCOM_QCS404_H - -#define MASTER_AMPSS_M0 0 -#define MASTER_OXILI 1 -#define MASTER_MDP_PORT0 2 -#define MASTER_SNOC_BIMC_1 3 -#define MASTER_TCU_0 4 -#define SLAVE_EBI_CH0 5 -#define SLAVE_BIMC_SNOC 6 - -#define MASTER_SPDM 0 -#define MASTER_BLSP_1 1 -#define MASTER_BLSP_2 2 -#define MASTER_XI_USB_HS1 3 -#define MASTER_CRYPT0 4 -#define MASTER_SDCC_1 5 -#define MASTER_SDCC_2 6 -#define MASTER_SNOC_PCNOC 7 -#define MASTER_QPIC 8 -#define PCNOC_INT_0 9 -#define PCNOC_INT_2 10 -#define PCNOC_INT_3 11 -#define PCNOC_S_0 12 -#define PCNOC_S_1 13 -#define PCNOC_S_2 14 -#define PCNOC_S_3 15 -#define PCNOC_S_4 16 -#define PCNOC_S_6 17 -#define PCNOC_S_7 18 -#define PCNOC_S_8 19 -#define PCNOC_S_9 20 -#define PCNOC_S_10 21 -#define PCNOC_S_11 22 -#define SLAVE_SPDM 23 -#define SLAVE_PDM 24 -#define SLAVE_PRNG 25 -#define SLAVE_TCSR 26 -#define SLAVE_SNOC_CFG 27 -#define SLAVE_MESSAGE_RAM 28 -#define SLAVE_DISP_SS_CFG 29 -#define SLAVE_GPU_CFG 30 -#define SLAVE_BLSP_1 31 -#define SLAVE_BLSP_2 32 -#define SLAVE_TLMM_NORTH 33 -#define SLAVE_PCIE 34 -#define SLAVE_ETHERNET 35 -#define SLAVE_TLMM_EAST 36 -#define SLAVE_TCU 37 -#define SLAVE_PMIC_ARB 38 -#define SLAVE_SDCC_1 39 -#define SLAVE_SDCC_2 40 -#define SLAVE_TLMM_SOUTH 41 -#define SLAVE_USB_HS 42 -#define SLAVE_USB3 43 -#define SLAVE_CRYPTO_0_CFG 44 -#define SLAVE_PCNOC_SNOC 45 - -#define MASTER_QDSS_BAM 0 -#define MASTER_BIMC_SNOC 1 -#define MASTER_PCNOC_SNOC 2 -#define MASTER_QDSS_ETR 3 -#define MASTER_EMAC 4 -#define MASTER_PCIE 5 -#define MASTER_USB3 6 -#define QDSS_INT 7 -#define SNOC_INT_0 8 -#define SNOC_INT_1 9 -#define SNOC_INT_2 10 -#define SLAVE_KPSS_AHB 11 -#define SLAVE_WCSS 12 -#define SLAVE_SNOC_BIMC_1 13 -#define SLAVE_IMEM 14 -#define SLAVE_SNOC_PCNOC 15 -#define SLAVE_QDSS_STM 16 -#define SLAVE_CATS_0 17 -#define SLAVE_CATS_1 18 -#define SLAVE_LPASS 19 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/interconnect/qcom,sdm845.h b/sys/gnu/dts/include/dt-bindings/interconnect/qcom,sdm845.h deleted file mode 100644 index 7b2393be736..00000000000 --- a/sys/gnu/dts/include/dt-bindings/interconnect/qcom,sdm845.h +++ /dev/null @@ -1,143 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Qualcomm SDM845 interconnect IDs - * - * Copyright (c) 2018, Linaro Ltd. - * Author: Georgi Djakov - */ - -#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SDM845_H -#define __DT_BINDINGS_INTERCONNECT_QCOM_SDM845_H - -#define MASTER_A1NOC_CFG 0 -#define MASTER_BLSP_1 1 -#define MASTER_TSIF 2 -#define MASTER_SDCC_2 3 -#define MASTER_SDCC_4 4 -#define MASTER_UFS_CARD 5 -#define MASTER_UFS_MEM 6 -#define MASTER_PCIE_0 7 -#define MASTER_A2NOC_CFG 8 -#define MASTER_QDSS_BAM 9 -#define MASTER_BLSP_2 10 -#define MASTER_CNOC_A2NOC 11 -#define MASTER_CRYPTO 12 -#define MASTER_IPA 13 -#define MASTER_PCIE_1 14 -#define MASTER_QDSS_ETR 15 -#define MASTER_USB3_0 16 -#define MASTER_USB3_1 17 -#define MASTER_CAMNOC_HF0_UNCOMP 18 -#define MASTER_CAMNOC_HF1_UNCOMP 19 -#define MASTER_CAMNOC_SF_UNCOMP 20 -#define MASTER_SPDM 21 -#define MASTER_TIC 22 -#define MASTER_SNOC_CNOC 23 -#define MASTER_QDSS_DAP 24 -#define MASTER_CNOC_DC_NOC 25 -#define MASTER_APPSS_PROC 26 -#define MASTER_GNOC_CFG 27 -#define MASTER_LLCC 28 -#define MASTER_TCU_0 29 -#define MASTER_MEM_NOC_CFG 30 -#define MASTER_GNOC_MEM_NOC 31 -#define MASTER_MNOC_HF_MEM_NOC 32 -#define MASTER_MNOC_SF_MEM_NOC 33 -#define MASTER_SNOC_GC_MEM_NOC 34 -#define MASTER_SNOC_SF_MEM_NOC 35 -#define MASTER_GFX3D 36 -#define MASTER_CNOC_MNOC_CFG 37 -#define MASTER_CAMNOC_HF0 38 -#define MASTER_CAMNOC_HF1 39 -#define MASTER_CAMNOC_SF 40 -#define MASTER_MDP0 41 -#define MASTER_MDP1 42 -#define MASTER_ROTATOR 43 -#define MASTER_VIDEO_P0 44 -#define MASTER_VIDEO_P1 45 -#define MASTER_VIDEO_PROC 46 -#define MASTER_SNOC_CFG 47 -#define MASTER_A1NOC_SNOC 48 -#define MASTER_A2NOC_SNOC 49 -#define MASTER_GNOC_SNOC 50 -#define MASTER_MEM_NOC_SNOC 51 -#define MASTER_ANOC_PCIE_SNOC 52 -#define MASTER_PIMEM 53 -#define MASTER_GIC 54 -#define SLAVE_A1NOC_SNOC 55 -#define SLAVE_SERVICE_A1NOC 56 -#define SLAVE_ANOC_PCIE_A1NOC_SNOC 57 -#define SLAVE_A2NOC_SNOC 58 -#define SLAVE_ANOC_PCIE_SNOC 59 -#define SLAVE_SERVICE_A2NOC 60 -#define SLAVE_CAMNOC_UNCOMP 61 -#define SLAVE_A1NOC_CFG 62 -#define SLAVE_A2NOC_CFG 63 -#define SLAVE_AOP 64 -#define SLAVE_AOSS 65 -#define SLAVE_CAMERA_CFG 66 -#define SLAVE_CLK_CTL 67 -#define SLAVE_CDSP_CFG 68 -#define SLAVE_RBCPR_CX_CFG 69 -#define SLAVE_CRYPTO_0_CFG 70 -#define SLAVE_DCC_CFG 71 -#define SLAVE_CNOC_DDRSS 72 -#define SLAVE_DISPLAY_CFG 73 -#define SLAVE_GLM 74 -#define SLAVE_GFX3D_CFG 75 -#define SLAVE_IMEM_CFG 76 -#define SLAVE_IPA_CFG 77 -#define SLAVE_CNOC_MNOC_CFG 78 -#define SLAVE_PCIE_0_CFG 79 -#define SLAVE_PCIE_1_CFG 80 -#define SLAVE_PDM 81 -#define SLAVE_SOUTH_PHY_CFG 82 -#define SLAVE_PIMEM_CFG 83 -#define SLAVE_PRNG 84 -#define SLAVE_QDSS_CFG 85 -#define SLAVE_BLSP_2 86 -#define SLAVE_BLSP_1 87 -#define SLAVE_SDCC_2 88 -#define SLAVE_SDCC_4 89 -#define SLAVE_SNOC_CFG 90 -#define SLAVE_SPDM_WRAPPER 91 -#define SLAVE_SPSS_CFG 92 -#define SLAVE_TCSR 93 -#define SLAVE_TLMM_NORTH 94 -#define SLAVE_TLMM_SOUTH 95 -#define SLAVE_TSIF 96 -#define SLAVE_UFS_CARD_CFG 97 -#define SLAVE_UFS_MEM_CFG 98 -#define SLAVE_USB3_0 99 -#define SLAVE_USB3_1 100 -#define SLAVE_VENUS_CFG 101 -#define SLAVE_VSENSE_CTRL_CFG 102 -#define SLAVE_CNOC_A2NOC 103 -#define SLAVE_SERVICE_CNOC 104 -#define SLAVE_LLCC_CFG 105 -#define SLAVE_MEM_NOC_CFG 106 -#define SLAVE_GNOC_SNOC 107 -#define SLAVE_GNOC_MEM_NOC 108 -#define SLAVE_SERVICE_GNOC 109 -#define SLAVE_EBI1 110 -#define SLAVE_MSS_PROC_MS_MPU_CFG 111 -#define SLAVE_MEM_NOC_GNOC 112 -#define SLAVE_LLCC 113 -#define SLAVE_MEM_NOC_SNOC 114 -#define SLAVE_SERVICE_MEM_NOC 115 -#define SLAVE_MNOC_SF_MEM_NOC 116 -#define SLAVE_MNOC_HF_MEM_NOC 117 -#define SLAVE_SERVICE_MNOC 118 -#define SLAVE_APPSS 119 -#define SLAVE_SNOC_CNOC 120 -#define SLAVE_SNOC_MEM_NOC_GC 121 -#define SLAVE_SNOC_MEM_NOC_SF 122 -#define SLAVE_IMEM 123 -#define SLAVE_PCIE_0 124 -#define SLAVE_PCIE_1 125 -#define SLAVE_PIMEM 126 -#define SLAVE_SERVICE_SNOC 127 -#define SLAVE_QDSS_STM 128 -#define SLAVE_TCU 129 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/interrupt-controller/arm-gic.h b/sys/gnu/dts/include/dt-bindings/interrupt-controller/arm-gic.h deleted file mode 100644 index 35b6f69b7db..00000000000 --- a/sys/gnu/dts/include/dt-bindings/interrupt-controller/arm-gic.h +++ /dev/null @@ -1,23 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 OR MIT */ -/* - * This header provides constants for the ARM GIC. - */ - -#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_ARM_GIC_H -#define _DT_BINDINGS_INTERRUPT_CONTROLLER_ARM_GIC_H - -#include - -/* interrupt specifier cell 0 */ - -#define GIC_SPI 0 -#define GIC_PPI 1 - -/* - * Interrupt specifier cell 2. - * The flags in irq.h are valid, plus those below. - */ -#define GIC_CPU_MASK_RAW(x) ((x) << 8) -#define GIC_CPU_MASK_SIMPLE(num) GIC_CPU_MASK_RAW((1 << (num)) - 1) - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/interrupt-controller/aspeed-scu-ic.h b/sys/gnu/dts/include/dt-bindings/interrupt-controller/aspeed-scu-ic.h deleted file mode 100644 index f315d5a7f5e..00000000000 --- a/sys/gnu/dts/include/dt-bindings/interrupt-controller/aspeed-scu-ic.h +++ /dev/null @@ -1,23 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ - -#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_ASPEED_SCU_IC_H_ -#define _DT_BINDINGS_INTERRUPT_CONTROLLER_ASPEED_SCU_IC_H_ - -#define ASPEED_SCU_IC_VGA_CURSOR_CHANGE 0 -#define ASPEED_SCU_IC_VGA_SCRATCH_REG_CHANGE 1 - -#define ASPEED_AST2500_SCU_IC_PCIE_RESET_LO_TO_HI 2 -#define ASPEED_AST2500_SCU_IC_PCIE_RESET_HI_TO_LO 3 -#define ASPEED_AST2500_SCU_IC_LPC_RESET_LO_TO_HI 4 -#define ASPEED_AST2500_SCU_IC_LPC_RESET_HI_TO_LO 5 -#define ASPEED_AST2500_SCU_IC_ISSUE_MSI 6 - -#define ASPEED_AST2600_SCU_IC0_PCIE_PERST_LO_TO_HI 2 -#define ASPEED_AST2600_SCU_IC0_PCIE_PERST_HI_TO_LO 3 -#define ASPEED_AST2600_SCU_IC0_PCIE_RCRST_LO_TO_HI 4 -#define ASPEED_AST2600_SCU_IC0_PCIE_RCRST_HI_TO_LO 5 - -#define ASPEED_AST2600_SCU_IC1_LPC_RESET_LO_TO_HI 0 -#define ASPEED_AST2600_SCU_IC1_LPC_RESET_HI_TO_LO 1 - -#endif /* _DT_BINDINGS_INTERRUPT_CONTROLLER_ASPEED_SCU_IC_H_ */ diff --git a/sys/gnu/dts/include/dt-bindings/interrupt-controller/irq-st.h b/sys/gnu/dts/include/dt-bindings/interrupt-controller/irq-st.h deleted file mode 100644 index 9c9c8e2b808..00000000000 --- a/sys/gnu/dts/include/dt-bindings/interrupt-controller/irq-st.h +++ /dev/null @@ -1,27 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * include/linux/irqchip/irq-st.h - * - * Copyright (C) 2014 STMicroelectronics – All Rights Reserved - * - * Author: Lee Jones - */ - -#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_ST_H -#define _DT_BINDINGS_INTERRUPT_CONTROLLER_ST_H - -#define ST_IRQ_SYSCFG_EXT_0 0 -#define ST_IRQ_SYSCFG_EXT_1 1 -#define ST_IRQ_SYSCFG_EXT_2 2 -#define ST_IRQ_SYSCFG_CTI_0 3 -#define ST_IRQ_SYSCFG_CTI_1 4 -#define ST_IRQ_SYSCFG_PMU_0 5 -#define ST_IRQ_SYSCFG_PMU_1 6 -#define ST_IRQ_SYSCFG_pl310_L2 7 -#define ST_IRQ_SYSCFG_DISABLED 0xFFFFFFFF - -#define ST_IRQ_SYSCFG_EXT_1_INV 0x1 -#define ST_IRQ_SYSCFG_EXT_2_INV 0x2 -#define ST_IRQ_SYSCFG_EXT_3_INV 0x4 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/interrupt-controller/irq.h b/sys/gnu/dts/include/dt-bindings/interrupt-controller/irq.h deleted file mode 100644 index 9e3d183e138..00000000000 --- a/sys/gnu/dts/include/dt-bindings/interrupt-controller/irq.h +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 OR MIT */ -/* - * This header provides constants for most IRQ bindings. - * - * Most IRQ bindings include a flags cell as part of the IRQ specifier. - * In most cases, the format of the flags cell uses the standard values - * defined in this header. - */ - -#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H -#define _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H - -#define IRQ_TYPE_NONE 0 -#define IRQ_TYPE_EDGE_RISING 1 -#define IRQ_TYPE_EDGE_FALLING 2 -#define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING) -#define IRQ_TYPE_LEVEL_HIGH 4 -#define IRQ_TYPE_LEVEL_LOW 8 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/interrupt-controller/mips-gic.h b/sys/gnu/dts/include/dt-bindings/interrupt-controller/mips-gic.h deleted file mode 100644 index bd45cee0c3f..00000000000 --- a/sys/gnu/dts/include/dt-bindings/interrupt-controller/mips-gic.h +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_MIPS_GIC_H -#define _DT_BINDINGS_INTERRUPT_CONTROLLER_MIPS_GIC_H - -#include - -#define GIC_SHARED 0 -#define GIC_LOCAL 1 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/interrupt-controller/mvebu-icu.h b/sys/gnu/dts/include/dt-bindings/interrupt-controller/mvebu-icu.h deleted file mode 100644 index bb5217c6420..00000000000 --- a/sys/gnu/dts/include/dt-bindings/interrupt-controller/mvebu-icu.h +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides constants for the MVEBU ICU driver. - */ - -#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_MVEBU_ICU_H -#define _DT_BINDINGS_INTERRUPT_CONTROLLER_MVEBU_ICU_H - -/* interrupt specifier cell 0 */ - -#define ICU_GRP_NSR 0x0 -#define ICU_GRP_SR 0x1 -#define ICU_GRP_SEI 0x4 -#define ICU_GRP_REI 0x5 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/leds/common.h b/sys/gnu/dts/include/dt-bindings/leds/common.h deleted file mode 100644 index 9e1256a7c1b..00000000000 --- a/sys/gnu/dts/include/dt-bindings/leds/common.h +++ /dev/null @@ -1,75 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides macros for the common LEDs device tree bindings. - * - * Copyright (C) 2015, Samsung Electronics Co., Ltd. - * Author: Jacek Anaszewski - * - * Copyright (C) 2019 Jacek Anaszewski - */ - -#ifndef __DT_BINDINGS_LEDS_H -#define __DT_BINDINGS_LEDS_H - -/* External trigger type */ -#define LEDS_TRIG_TYPE_EDGE 0 -#define LEDS_TRIG_TYPE_LEVEL 1 - -/* Boost modes */ -#define LEDS_BOOST_OFF 0 -#define LEDS_BOOST_ADAPTIVE 1 -#define LEDS_BOOST_FIXED 2 - -/* Standard LED colors */ -#define LED_COLOR_ID_WHITE 0 -#define LED_COLOR_ID_RED 1 -#define LED_COLOR_ID_GREEN 2 -#define LED_COLOR_ID_BLUE 3 -#define LED_COLOR_ID_AMBER 4 -#define LED_COLOR_ID_VIOLET 5 -#define LED_COLOR_ID_YELLOW 6 -#define LED_COLOR_ID_IR 7 -#define LED_COLOR_ID_MAX 8 - -/* Standard LED functions */ -#define LED_FUNCTION_ACTIVITY "activity" -#define LED_FUNCTION_ALARM "alarm" -#define LED_FUNCTION_BACKLIGHT "backlight" -#define LED_FUNCTION_BLUETOOTH "bluetooth" -#define LED_FUNCTION_BOOT "boot" -#define LED_FUNCTION_CPU "cpu" -#define LED_FUNCTION_CAPSLOCK "capslock" -#define LED_FUNCTION_CHARGING "charging" -#define LED_FUNCTION_DEBUG "debug" -#define LED_FUNCTION_DISK "disk" -#define LED_FUNCTION_DISK_ACTIVITY "disk-activity" -#define LED_FUNCTION_DISK_ERR "disk-err" -#define LED_FUNCTION_DISK_READ "disk-read" -#define LED_FUNCTION_DISK_WRITE "disk-write" -#define LED_FUNCTION_FAULT "fault" -#define LED_FUNCTION_FLASH "flash" -#define LED_FUNCTION_HEARTBEAT "heartbeat" -#define LED_FUNCTION_INDICATOR "indicator" -#define LED_FUNCTION_KBD_BACKLIGHT "kbd_backlight" -#define LED_FUNCTION_LAN "lan" -#define LED_FUNCTION_MAIL "mail" -#define LED_FUNCTION_MTD "mtd" -#define LED_FUNCTION_MICMUTE "micmute" -#define LED_FUNCTION_MUTE "mute" -#define LED_FUNCTION_NUMLOCK "numlock" -#define LED_FUNCTION_PANIC "panic" -#define LED_FUNCTION_PROGRAMMING "programming" -#define LED_FUNCTION_POWER "power" -#define LED_FUNCTION_RX "rx" -#define LED_FUNCTION_SD "sd" -#define LED_FUNCTION_SCROLLLOCK "scrolllock" -#define LED_FUNCTION_STANDBY "standby" -#define LED_FUNCTION_STATUS "status" -#define LED_FUNCTION_TORCH "torch" -#define LED_FUNCTION_TX "tx" -#define LED_FUNCTION_USB "usb" -#define LED_FUNCTION_WAN "wan" -#define LED_FUNCTION_WLAN "wlan" -#define LED_FUNCTION_WPS "wps" - -#endif /* __DT_BINDINGS_LEDS_H */ diff --git a/sys/gnu/dts/include/dt-bindings/leds/leds-netxbig.h b/sys/gnu/dts/include/dt-bindings/leds/leds-netxbig.h deleted file mode 100644 index 92658b0310b..00000000000 --- a/sys/gnu/dts/include/dt-bindings/leds/leds-netxbig.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * This header provides constants for netxbig LED bindings. - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef _DT_BINDINGS_LEDS_NETXBIG_H -#define _DT_BINDINGS_LEDS_NETXBIG_H - -#define NETXBIG_LED_OFF 0 -#define NETXBIG_LED_ON 1 -#define NETXBIG_LED_SATA 2 -#define NETXBIG_LED_TIMER1 3 -#define NETXBIG_LED_TIMER2 4 - -#endif /* _DT_BINDINGS_LEDS_NETXBIG_H */ diff --git a/sys/gnu/dts/include/dt-bindings/leds/leds-ns2.h b/sys/gnu/dts/include/dt-bindings/leds/leds-ns2.h deleted file mode 100644 index fd615749e70..00000000000 --- a/sys/gnu/dts/include/dt-bindings/leds/leds-ns2.h +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _DT_BINDINGS_LEDS_NS2_H -#define _DT_BINDINGS_LEDS_NS2_H - -#define NS_V2_LED_OFF 0 -#define NS_V2_LED_ON 1 -#define NS_V2_LED_SATA 2 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/leds/leds-pca9532.h b/sys/gnu/dts/include/dt-bindings/leds/leds-pca9532.h deleted file mode 100644 index 4d917aab7e1..00000000000 --- a/sys/gnu/dts/include/dt-bindings/leds/leds-pca9532.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * This header provides constants for pca9532 LED bindings. - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef _DT_BINDINGS_LEDS_PCA9532_H -#define _DT_BINDINGS_LEDS_PCA9532_H - -#define PCA9532_TYPE_NONE 0 -#define PCA9532_TYPE_LED 1 -#define PCA9532_TYPE_N2100_BEEP 2 -#define PCA9532_TYPE_GPIO 3 -#define PCA9532_LED_TIMER2 4 - -#endif /* _DT_BINDINGS_LEDS_PCA9532_H */ diff --git a/sys/gnu/dts/include/dt-bindings/leds/leds-pca955x.h b/sys/gnu/dts/include/dt-bindings/leds/leds-pca955x.h deleted file mode 100644 index 78cb7e979de..00000000000 --- a/sys/gnu/dts/include/dt-bindings/leds/leds-pca955x.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * This header provides constants for pca955x LED bindings. - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef _DT_BINDINGS_LEDS_PCA955X_H -#define _DT_BINDINGS_LEDS_PCA955X_H - -#define PCA955X_TYPE_NONE 0 -#define PCA955X_TYPE_LED 1 -#define PCA955X_TYPE_GPIO 2 - -#endif /* _DT_BINDINGS_LEDS_PCA955X_H */ diff --git a/sys/gnu/dts/include/dt-bindings/mailbox/tegra186-hsp.h b/sys/gnu/dts/include/dt-bindings/mailbox/tegra186-hsp.h deleted file mode 100644 index 3bdec7a84d3..00000000000 --- a/sys/gnu/dts/include/dt-bindings/mailbox/tegra186-hsp.h +++ /dev/null @@ -1,36 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides constants for binding nvidia,tegra186-hsp. - */ - -#ifndef _DT_BINDINGS_MAILBOX_TEGRA186_HSP_H -#define _DT_BINDINGS_MAILBOX_TEGRA186_HSP_H - -/* - * These define the type of mailbox that is to be used (doorbell, shared - * mailbox, shared semaphore or arbitrated semaphore). - */ -#define TEGRA_HSP_MBOX_TYPE_DB 0x0 -#define TEGRA_HSP_MBOX_TYPE_SM 0x1 -#define TEGRA_HSP_MBOX_TYPE_SS 0x2 -#define TEGRA_HSP_MBOX_TYPE_AS 0x3 - -/* - * These defines represent the bit associated with the given master ID in the - * doorbell registers. - */ -#define TEGRA_HSP_DB_MASTER_CCPLEX 17 -#define TEGRA_HSP_DB_MASTER_BPMP 19 - -/* - * Shared mailboxes are unidirectional, so the direction needs to be specified - * in the device tree. - */ -#define TEGRA_HSP_SM_MASK 0x00ffffff -#define TEGRA_HSP_SM_FLAG_RX (0 << 31) -#define TEGRA_HSP_SM_FLAG_TX (1 << 31) - -#define TEGRA_HSP_SM_RX(x) (TEGRA_HSP_SM_FLAG_RX | ((x) & TEGRA_HSP_SM_MASK)) -#define TEGRA_HSP_SM_TX(x) (TEGRA_HSP_SM_FLAG_TX | ((x) & TEGRA_HSP_SM_MASK)) - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/media/c8sectpfe.h b/sys/gnu/dts/include/dt-bindings/media/c8sectpfe.h deleted file mode 100644 index 6b1fb6f5413..00000000000 --- a/sys/gnu/dts/include/dt-bindings/media/c8sectpfe.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __DT_C8SECTPFE_H -#define __DT_C8SECTPFE_H - -#define STV0367_TDA18212_NIMA_1 0 -#define STV0367_TDA18212_NIMA_2 1 -#define STV0367_TDA18212_NIMB_1 2 -#define STV0367_TDA18212_NIMB_2 3 - -#define STV0903_6110_LNB24_NIMA 4 -#define STV0903_6110_LNB24_NIMB 5 - -#endif /* __DT_C8SECTPFE_H */ diff --git a/sys/gnu/dts/include/dt-bindings/media/omap3-isp.h b/sys/gnu/dts/include/dt-bindings/media/omap3-isp.h deleted file mode 100644 index 436c71210e6..00000000000 --- a/sys/gnu/dts/include/dt-bindings/media/omap3-isp.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * include/dt-bindings/media/omap3-isp.h - * - * Copyright (C) 2015 Sakari Ailus - */ - -#ifndef __DT_BINDINGS_OMAP3_ISP_H__ -#define __DT_BINDINGS_OMAP3_ISP_H__ - -#define OMAP3ISP_PHY_TYPE_COMPLEX_IO 0 -#define OMAP3ISP_PHY_TYPE_CSIPHY 1 - -#endif /* __DT_BINDINGS_OMAP3_ISP_H__ */ diff --git a/sys/gnu/dts/include/dt-bindings/media/tda1997x.h b/sys/gnu/dts/include/dt-bindings/media/tda1997x.h deleted file mode 100644 index bd9fbd718ec..00000000000 --- a/sys/gnu/dts/include/dt-bindings/media/tda1997x.h +++ /dev/null @@ -1,74 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2017 Gateworks Corporation - */ -#ifndef _DT_BINDINGS_MEDIA_TDA1997X_H -#define _DT_BINDINGS_MEDIA_TDA1997X_H - -/* TDA19973 36bit Video Port control registers */ -#define TDA1997X_VP36_35_32 0 -#define TDA1997X_VP36_31_28 1 -#define TDA1997X_VP36_27_24 2 -#define TDA1997X_VP36_23_20 3 -#define TDA1997X_VP36_19_16 4 -#define TDA1997X_VP36_15_12 5 -#define TDA1997X_VP36_11_08 6 -#define TDA1997X_VP36_07_04 7 -#define TDA1997X_VP36_03_00 8 - -/* TDA19971 24bit Video Port control registers */ -#define TDA1997X_VP24_V23_20 0 -#define TDA1997X_VP24_V19_16 1 -#define TDA1997X_VP24_V15_12 3 -#define TDA1997X_VP24_V11_08 4 -#define TDA1997X_VP24_V07_04 6 -#define TDA1997X_VP24_V03_00 7 - -/* Pin groups */ -#define TDA1997X_VP_OUT_EN 0x80 /* enable output group */ -#define TDA1997X_VP_HIZ 0x40 /* hi-Z output group when not used */ -#define TDA1997X_VP_SWP 0x10 /* pin-swap output group */ -#define TDA1997X_R_CR_CBCR_3_0 (0 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ) -#define TDA1997X_R_CR_CBCR_7_4 (1 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ) -#define TDA1997X_R_CR_CBCR_11_8 (2 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ) -#define TDA1997X_B_CB_3_0 (3 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ) -#define TDA1997X_B_CB_7_4 (4 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ) -#define TDA1997X_B_CB_11_8 (5 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ) -#define TDA1997X_G_Y_3_0 (6 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ) -#define TDA1997X_G_Y_7_4 (7 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ) -#define TDA1997X_G_Y_11_8 (8 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ) -/* pinswapped groups */ -#define TDA1997X_R_CR_CBCR_3_0_S (TDA1997X_R_CR_CBCR_3_0 | TDA1997X_VP_SWAP) -#define TDA1997X_R_CR_CBCR_7_4_S (TDA1997X_R_CR_CBCR_7_4 | TDA1997X_VP_SWAP) -#define TDA1997X_R_CR_CBCR_11_8_S (TDA1997X_R_CR_CBCR_11_8 | TDA1997X_VP_SWAP) -#define TDA1997X_B_CB_3_0_S (TDA1997X_B_CB_3_0 | TDA1997X_VP_SWAP) -#define TDA1997X_B_CB_7_4_S (TDA1997X_B_CB_7_4 | TDA1997X_VP_SWAP) -#define TDA1997X_B_CB_11_8_S (TDA1997X_B_CB_11_8 | TDA1997X_VP_SWAP) -#define TDA1997X_G_Y_3_0_S (TDA1997X_G_Y_3_0 | TDA1997X_VP_SWAP) -#define TDA1997X_G_Y_7_4_S (TDA1997X_G_Y_7_4 | TDA1997X_VP_SWAP) -#define TDA1997X_G_Y_11_8_S (TDA1997X_G_Y_11_8 | TDA1997X_VP_SWAP) - -/* Audio bus DAI format */ -#define TDA1997X_I2S16 1 /* I2S 16bit */ -#define TDA1997X_I2S32 2 /* I2S 32bit */ -#define TDA1997X_SPDIF 3 /* SPDIF */ -#define TDA1997X_OBA 4 /* One Bit Audio */ -#define TDA1997X_DST 5 /* Direct Stream Transfer */ -#define TDA1997X_I2S16_HBR 6 /* HBR straight in I2S 16bit mode */ -#define TDA1997X_I2S16_HBR_DEMUX 7 /* HBR demux in I2S 16bit mode */ -#define TDA1997X_I2S32_HBR_DEMUX 8 /* HBR demux in I2S 32bit mode */ -#define TDA1997X_SPDIF_HBR_DEMUX 9 /* HBR demux in SPDIF mode */ - -/* Audio bus channel layout */ -#define TDA1997X_LAYOUT0 0 /* 2-channel */ -#define TDA1997X_LAYOUT1 1 /* 8-channel */ - -/* Audio bus clock */ -#define TDA1997X_ACLK_16FS 0 -#define TDA1997X_ACLK_32FS 1 -#define TDA1997X_ACLK_64FS 2 -#define TDA1997X_ACLK_128FS 3 -#define TDA1997X_ACLK_256FS 4 -#define TDA1997X_ACLK_512FS 5 - -#endif /* _DT_BINDINGS_MEDIA_TDA1997X_H */ diff --git a/sys/gnu/dts/include/dt-bindings/media/tvp5150.h b/sys/gnu/dts/include/dt-bindings/media/tvp5150.h deleted file mode 100644 index 01eedf4985b..00000000000 --- a/sys/gnu/dts/include/dt-bindings/media/tvp5150.h +++ /dev/null @@ -1,23 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - tvp5150.h - definition for tvp5150 inputs - - Copyright (C) 2006 Hans Verkuil (hverkuil@xs4all.nl) - -*/ - -#ifndef _DT_BINDINGS_MEDIA_TVP5150_H -#define _DT_BINDINGS_MEDIA_TVP5150_H - -/* TVP5150 HW inputs */ -#define TVP5150_COMPOSITE0 0 -#define TVP5150_COMPOSITE1 1 -#define TVP5150_SVIDEO 2 - -#define TVP5150_INPUT_NUM 3 - -/* TVP5150 HW outputs */ -#define TVP5150_NORMAL 0 -#define TVP5150_BLACK_SCREEN 1 - -#endif /* _DT_BINDINGS_MEDIA_TVP5150_H */ diff --git a/sys/gnu/dts/include/dt-bindings/media/xilinx-vip.h b/sys/gnu/dts/include/dt-bindings/media/xilinx-vip.h deleted file mode 100644 index 94ed3edfcc7..00000000000 --- a/sys/gnu/dts/include/dt-bindings/media/xilinx-vip.h +++ /dev/null @@ -1,36 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Xilinx Video IP Core - * - * Copyright (C) 2013-2015 Ideas on Board - * Copyright (C) 2013-2015 Xilinx, Inc. - * - * Contacts: Hyun Kwon - * Laurent Pinchart - */ - -#ifndef __DT_BINDINGS_MEDIA_XILINX_VIP_H__ -#define __DT_BINDINGS_MEDIA_XILINX_VIP_H__ - -/* - * Video format codes as defined in "AXI4-Stream Video IP and System Design - * Guide". - */ -#define XVIP_VF_YUV_422 0 -#define XVIP_VF_YUV_444 1 -#define XVIP_VF_RBG 2 -#define XVIP_VF_YUV_420 3 -#define XVIP_VF_YUVA_422 4 -#define XVIP_VF_YUVA_444 5 -#define XVIP_VF_RGBA 6 -#define XVIP_VF_YUVA_420 7 -#define XVIP_VF_YUVD_422 8 -#define XVIP_VF_YUVD_444 9 -#define XVIP_VF_RGBD 10 -#define XVIP_VF_YUVD_420 11 -#define XVIP_VF_MONO_SENSOR 12 -#define XVIP_VF_CUSTOM2 13 -#define XVIP_VF_CUSTOM3 14 -#define XVIP_VF_CUSTOM4 15 - -#endif /* __DT_BINDINGS_MEDIA_XILINX_VIP_H__ */ diff --git a/sys/gnu/dts/include/dt-bindings/memory/mt2701-larb-port.h b/sys/gnu/dts/include/dt-bindings/memory/mt2701-larb-port.h deleted file mode 100644 index 2d85c2ec6cf..00000000000 --- a/sys/gnu/dts/include/dt-bindings/memory/mt2701-larb-port.h +++ /dev/null @@ -1,77 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2015 MediaTek Inc. - * Author: Honghui Zhang - */ - -#ifndef _MT2701_LARB_PORT_H_ -#define _MT2701_LARB_PORT_H_ - -/* - * Mediatek m4u generation 1 such as mt2701 has flat m4u port numbers, - * the first port's id for larb[N] would be the last port's id of larb[N - 1] - * plus one while larb[0]'s first port number is 0. The definition of - * MT2701_M4U_ID_LARBx is following HW register spec. - * But m4u generation 2 like mt8173 have different port number, it use fixed - * offset for each larb, the first port's id for larb[N] would be (N * 32). - */ -#define LARB0_PORT_OFFSET 0 -#define LARB1_PORT_OFFSET 11 -#define LARB2_PORT_OFFSET 21 -#define LARB3_PORT_OFFSET 44 - -#define MT2701_M4U_ID_LARB0(port) ((port) + LARB0_PORT_OFFSET) -#define MT2701_M4U_ID_LARB1(port) ((port) + LARB1_PORT_OFFSET) -#define MT2701_M4U_ID_LARB2(port) ((port) + LARB2_PORT_OFFSET) - -/* Port define for larb0 */ -#define MT2701_M4U_PORT_DISP_OVL_0 MT2701_M4U_ID_LARB0(0) -#define MT2701_M4U_PORT_DISP_RDMA1 MT2701_M4U_ID_LARB0(1) -#define MT2701_M4U_PORT_DISP_RDMA MT2701_M4U_ID_LARB0(2) -#define MT2701_M4U_PORT_DISP_WDMA MT2701_M4U_ID_LARB0(3) -#define MT2701_M4U_PORT_MM_CMDQ MT2701_M4U_ID_LARB0(4) -#define MT2701_M4U_PORT_MDP_RDMA MT2701_M4U_ID_LARB0(5) -#define MT2701_M4U_PORT_MDP_WDMA MT2701_M4U_ID_LARB0(6) -#define MT2701_M4U_PORT_MDP_ROTO MT2701_M4U_ID_LARB0(7) -#define MT2701_M4U_PORT_MDP_ROTCO MT2701_M4U_ID_LARB0(8) -#define MT2701_M4U_PORT_MDP_ROTVO MT2701_M4U_ID_LARB0(9) -#define MT2701_M4U_PORT_MDP_RDMA1 MT2701_M4U_ID_LARB0(10) - -/* Port define for larb1 */ -#define MT2701_M4U_PORT_VDEC_MC_EXT MT2701_M4U_ID_LARB1(0) -#define MT2701_M4U_PORT_VDEC_PP_EXT MT2701_M4U_ID_LARB1(1) -#define MT2701_M4U_PORT_VDEC_PPWRAP_EXT MT2701_M4U_ID_LARB1(2) -#define MT2701_M4U_PORT_VDEC_AVC_MV_EXT MT2701_M4U_ID_LARB1(3) -#define MT2701_M4U_PORT_VDEC_PRED_RD_EXT MT2701_M4U_ID_LARB1(4) -#define MT2701_M4U_PORT_VDEC_PRED_WR_EXT MT2701_M4U_ID_LARB1(5) -#define MT2701_M4U_PORT_VDEC_VLD_EXT MT2701_M4U_ID_LARB1(6) -#define MT2701_M4U_PORT_VDEC_VLD2_EXT MT2701_M4U_ID_LARB1(7) -#define MT2701_M4U_PORT_VDEC_TILE_EXT MT2701_M4U_ID_LARB1(8) -#define MT2701_M4U_PORT_VDEC_IMG_RESZ_EXT MT2701_M4U_ID_LARB1(9) - -/* Port define for larb2 */ -#define MT2701_M4U_PORT_VENC_RCPU MT2701_M4U_ID_LARB2(0) -#define MT2701_M4U_PORT_VENC_REC_FRM MT2701_M4U_ID_LARB2(1) -#define MT2701_M4U_PORT_VENC_BSDMA MT2701_M4U_ID_LARB2(2) -#define MT2701_M4U_PORT_JPGENC_RDMA MT2701_M4U_ID_LARB2(3) -#define MT2701_M4U_PORT_VENC_LT_RCPU MT2701_M4U_ID_LARB2(4) -#define MT2701_M4U_PORT_VENC_LT_REC_FRM MT2701_M4U_ID_LARB2(5) -#define MT2701_M4U_PORT_VENC_LT_BSDMA MT2701_M4U_ID_LARB2(6) -#define MT2701_M4U_PORT_JPGDEC_BSDMA MT2701_M4U_ID_LARB2(7) -#define MT2701_M4U_PORT_VENC_SV_COMV MT2701_M4U_ID_LARB2(8) -#define MT2701_M4U_PORT_VENC_RD_COMV MT2701_M4U_ID_LARB2(9) -#define MT2701_M4U_PORT_JPGENC_BSDMA MT2701_M4U_ID_LARB2(10) -#define MT2701_M4U_PORT_VENC_CUR_LUMA MT2701_M4U_ID_LARB2(11) -#define MT2701_M4U_PORT_VENC_CUR_CHROMA MT2701_M4U_ID_LARB2(12) -#define MT2701_M4U_PORT_VENC_REF_LUMA MT2701_M4U_ID_LARB2(13) -#define MT2701_M4U_PORT_VENC_REF_CHROMA MT2701_M4U_ID_LARB2(14) -#define MT2701_M4U_PORT_IMG_RESZ MT2701_M4U_ID_LARB2(15) -#define MT2701_M4U_PORT_VENC_LT_SV_COMV MT2701_M4U_ID_LARB2(16) -#define MT2701_M4U_PORT_VENC_LT_RD_COMV MT2701_M4U_ID_LARB2(17) -#define MT2701_M4U_PORT_VENC_LT_CUR_LUMA MT2701_M4U_ID_LARB2(18) -#define MT2701_M4U_PORT_VENC_LT_CUR_CHROMA MT2701_M4U_ID_LARB2(19) -#define MT2701_M4U_PORT_VENC_LT_REF_LUMA MT2701_M4U_ID_LARB2(20) -#define MT2701_M4U_PORT_VENC_LT_REF_CHROMA MT2701_M4U_ID_LARB2(21) -#define MT2701_M4U_PORT_JPGDEC_WDMA MT2701_M4U_ID_LARB2(22) - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/memory/mt2712-larb-port.h b/sys/gnu/dts/include/dt-bindings/memory/mt2712-larb-port.h deleted file mode 100644 index 6f9aa7349ce..00000000000 --- a/sys/gnu/dts/include/dt-bindings/memory/mt2712-larb-port.h +++ /dev/null @@ -1,95 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2017 MediaTek Inc. - * Author: Yong Wu - */ -#ifndef __DTS_IOMMU_PORT_MT2712_H -#define __DTS_IOMMU_PORT_MT2712_H - -#define MTK_M4U_ID(larb, port) (((larb) << 5) | (port)) - -#define M4U_LARB0_ID 0 -#define M4U_LARB1_ID 1 -#define M4U_LARB2_ID 2 -#define M4U_LARB3_ID 3 -#define M4U_LARB4_ID 4 -#define M4U_LARB5_ID 5 -#define M4U_LARB6_ID 6 -#define M4U_LARB7_ID 7 -#define M4U_LARB8_ID 8 -#define M4U_LARB9_ID 9 - -/* larb0 */ -#define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID, 0) -#define M4U_PORT_DISP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 1) -#define M4U_PORT_DISP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 2) -#define M4U_PORT_DISP_OD_R MTK_M4U_ID(M4U_LARB0_ID, 3) -#define M4U_PORT_DISP_OD_W MTK_M4U_ID(M4U_LARB0_ID, 4) -#define M4U_PORT_MDP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 5) -#define M4U_PORT_MDP_WDMA MTK_M4U_ID(M4U_LARB0_ID, 6) -#define M4U_PORT_DISP_RDMA2 MTK_M4U_ID(M4U_LARB0_ID, 7) - -/* larb1 */ -#define M4U_PORT_HW_VDEC_MC_EXT MTK_M4U_ID(M4U_LARB1_ID, 0) -#define M4U_PORT_HW_VDEC_PP_EXT MTK_M4U_ID(M4U_LARB1_ID, 1) -#define M4U_PORT_HW_VDEC_UFO_EXT MTK_M4U_ID(M4U_LARB1_ID, 2) -#define M4U_PORT_HW_VDEC_VLD_EXT MTK_M4U_ID(M4U_LARB1_ID, 3) -#define M4U_PORT_HW_VDEC_VLD2_EXT MTK_M4U_ID(M4U_LARB1_ID, 4) -#define M4U_PORT_HW_VDEC_AVC_MV_EXT MTK_M4U_ID(M4U_LARB1_ID, 5) -#define M4U_PORT_HW_VDEC_PRED_RD_EXT MTK_M4U_ID(M4U_LARB1_ID, 6) -#define M4U_PORT_HW_VDEC_PRED_WR_EXT MTK_M4U_ID(M4U_LARB1_ID, 7) -#define M4U_PORT_HW_VDEC_PPWRAP_EXT MTK_M4U_ID(M4U_LARB1_ID, 8) -#define M4U_PORT_HW_VDEC_TILE MTK_M4U_ID(M4U_LARB1_ID, 9) -#define M4U_PORT_HW_IMG_RESZ_EXT MTK_M4U_ID(M4U_LARB1_ID, 10) - -/* larb2 */ -#define M4U_PORT_CAM_DMA0 MTK_M4U_ID(M4U_LARB2_ID, 0) -#define M4U_PORT_CAM_DMA1 MTK_M4U_ID(M4U_LARB2_ID, 1) -#define M4U_PORT_CAM_DMA2 MTK_M4U_ID(M4U_LARB2_ID, 2) - -/* larb3 */ -#define M4U_PORT_VENC_RCPU MTK_M4U_ID(M4U_LARB3_ID, 0) -#define M4U_PORT_VENC_REC MTK_M4U_ID(M4U_LARB3_ID, 1) -#define M4U_PORT_VENC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 2) -#define M4U_PORT_VENC_SV_COMV MTK_M4U_ID(M4U_LARB3_ID, 3) -#define M4U_PORT_VENC_RD_COMV MTK_M4U_ID(M4U_LARB3_ID, 4) -#define M4U_PORT_VENC_CUR_CHROMA MTK_M4U_ID(M4U_LARB3_ID, 5) -#define M4U_PORT_VENC_REF_CHROMA MTK_M4U_ID(M4U_LARB3_ID, 6) -#define M4U_PORT_VENC_CUR_LUMA MTK_M4U_ID(M4U_LARB3_ID, 7) -#define M4U_PORT_VENC_REF_LUMA MTK_M4U_ID(M4U_LARB3_ID, 8) - -/* larb4 */ -#define M4U_PORT_DISP_OVL1 MTK_M4U_ID(M4U_LARB4_ID, 0) -#define M4U_PORT_DISP_RDMA1 MTK_M4U_ID(M4U_LARB4_ID, 1) -#define M4U_PORT_DISP_WDMA1 MTK_M4U_ID(M4U_LARB4_ID, 2) -#define M4U_PORT_DISP_OD1_R MTK_M4U_ID(M4U_LARB4_ID, 3) -#define M4U_PORT_DISP_OD1_W MTK_M4U_ID(M4U_LARB4_ID, 4) -#define M4U_PORT_MDP_RDMA1 MTK_M4U_ID(M4U_LARB4_ID, 5) -#define M4U_PORT_MDP_WROT1 MTK_M4U_ID(M4U_LARB4_ID, 6) - -/* larb5 */ -#define M4U_PORT_DISP_OVL2 MTK_M4U_ID(M4U_LARB5_ID, 0) -#define M4U_PORT_DISP_WDMA2 MTK_M4U_ID(M4U_LARB5_ID, 1) -#define M4U_PORT_MDP_RDMA2 MTK_M4U_ID(M4U_LARB5_ID, 2) -#define M4U_PORT_MDP_WROT0 MTK_M4U_ID(M4U_LARB5_ID, 3) - -/* larb6 */ -#define M4U_PORT_JPGDEC_WDMA_0 MTK_M4U_ID(M4U_LARB6_ID, 0) -#define M4U_PORT_JPGDEC_WDMA_1 MTK_M4U_ID(M4U_LARB6_ID, 1) -#define M4U_PORT_JPGDEC_BSDMA_0 MTK_M4U_ID(M4U_LARB6_ID, 2) -#define M4U_PORT_JPGDEC_BSDMA_1 MTK_M4U_ID(M4U_LARB6_ID, 3) - -/* larb7 */ -#define M4U_PORT_MDP_RDMA3 MTK_M4U_ID(M4U_LARB7_ID, 0) -#define M4U_PORT_MDP_WROT2 MTK_M4U_ID(M4U_LARB7_ID, 1) - -/* larb8 */ -#define M4U_PORT_VDO MTK_M4U_ID(M4U_LARB8_ID, 0) -#define M4U_PORT_NR MTK_M4U_ID(M4U_LARB8_ID, 1) -#define M4U_PORT_WR_CHANNEL0 MTK_M4U_ID(M4U_LARB8_ID, 2) - -/* larb9 */ -#define M4U_PORT_TVD MTK_M4U_ID(M4U_LARB9_ID, 0) -#define M4U_PORT_WR_CHANNEL1 MTK_M4U_ID(M4U_LARB9_ID, 1) - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/memory/mt8173-larb-port.h b/sys/gnu/dts/include/dt-bindings/memory/mt8173-larb-port.h deleted file mode 100644 index 9f31ccfeca2..00000000000 --- a/sys/gnu/dts/include/dt-bindings/memory/mt8173-larb-port.h +++ /dev/null @@ -1,99 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2015-2016 MediaTek Inc. - * Author: Yong Wu - */ -#ifndef __DTS_IOMMU_PORT_MT8173_H -#define __DTS_IOMMU_PORT_MT8173_H - -#define MTK_M4U_ID(larb, port) (((larb) << 5) | (port)) - -#define M4U_LARB0_ID 0 -#define M4U_LARB1_ID 1 -#define M4U_LARB2_ID 2 -#define M4U_LARB3_ID 3 -#define M4U_LARB4_ID 4 -#define M4U_LARB5_ID 5 - -/* larb0 */ -#define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID, 0) -#define M4U_PORT_DISP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 1) -#define M4U_PORT_DISP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 2) -#define M4U_PORT_DISP_OD_R MTK_M4U_ID(M4U_LARB0_ID, 3) -#define M4U_PORT_DISP_OD_W MTK_M4U_ID(M4U_LARB0_ID, 4) -#define M4U_PORT_MDP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 5) -#define M4U_PORT_MDP_WDMA MTK_M4U_ID(M4U_LARB0_ID, 6) -#define M4U_PORT_MDP_WROT0 MTK_M4U_ID(M4U_LARB0_ID, 7) - -/* larb1 */ -#define M4U_PORT_HW_VDEC_MC_EXT MTK_M4U_ID(M4U_LARB1_ID, 0) -#define M4U_PORT_HW_VDEC_PP_EXT MTK_M4U_ID(M4U_LARB1_ID, 1) -#define M4U_PORT_HW_VDEC_UFO_EXT MTK_M4U_ID(M4U_LARB1_ID, 2) -#define M4U_PORT_HW_VDEC_VLD_EXT MTK_M4U_ID(M4U_LARB1_ID, 3) -#define M4U_PORT_HW_VDEC_VLD2_EXT MTK_M4U_ID(M4U_LARB1_ID, 4) -#define M4U_PORT_HW_VDEC_AVC_MV_EXT MTK_M4U_ID(M4U_LARB1_ID, 5) -#define M4U_PORT_HW_VDEC_PRED_RD_EXT MTK_M4U_ID(M4U_LARB1_ID, 6) -#define M4U_PORT_HW_VDEC_PRED_WR_EXT MTK_M4U_ID(M4U_LARB1_ID, 7) -#define M4U_PORT_HW_VDEC_PPWRAP_EXT MTK_M4U_ID(M4U_LARB1_ID, 8) -#define M4U_PORT_HW_VDEC_TILE MTK_M4U_ID(M4U_LARB1_ID, 9) - -/* larb2 */ -#define M4U_PORT_IMGO MTK_M4U_ID(M4U_LARB2_ID, 0) -#define M4U_PORT_RRZO MTK_M4U_ID(M4U_LARB2_ID, 1) -#define M4U_PORT_AAO MTK_M4U_ID(M4U_LARB2_ID, 2) -#define M4U_PORT_LCSO MTK_M4U_ID(M4U_LARB2_ID, 3) -#define M4U_PORT_ESFKO MTK_M4U_ID(M4U_LARB2_ID, 4) -#define M4U_PORT_IMGO_D MTK_M4U_ID(M4U_LARB2_ID, 5) -#define M4U_PORT_LSCI MTK_M4U_ID(M4U_LARB2_ID, 6) -#define M4U_PORT_LSCI_D MTK_M4U_ID(M4U_LARB2_ID, 7) -#define M4U_PORT_BPCI MTK_M4U_ID(M4U_LARB2_ID, 8) -#define M4U_PORT_BPCI_D MTK_M4U_ID(M4U_LARB2_ID, 9) -#define M4U_PORT_UFDI MTK_M4U_ID(M4U_LARB2_ID, 10) -#define M4U_PORT_IMGI MTK_M4U_ID(M4U_LARB2_ID, 11) -#define M4U_PORT_IMG2O MTK_M4U_ID(M4U_LARB2_ID, 12) -#define M4U_PORT_IMG3O MTK_M4U_ID(M4U_LARB2_ID, 13) -#define M4U_PORT_VIPI MTK_M4U_ID(M4U_LARB2_ID, 14) -#define M4U_PORT_VIP2I MTK_M4U_ID(M4U_LARB2_ID, 15) -#define M4U_PORT_VIP3I MTK_M4U_ID(M4U_LARB2_ID, 16) -#define M4U_PORT_LCEI MTK_M4U_ID(M4U_LARB2_ID, 17) -#define M4U_PORT_RB MTK_M4U_ID(M4U_LARB2_ID, 18) -#define M4U_PORT_RP MTK_M4U_ID(M4U_LARB2_ID, 19) -#define M4U_PORT_WR MTK_M4U_ID(M4U_LARB2_ID, 20) - -/* larb3 */ -#define M4U_PORT_VENC_RCPU MTK_M4U_ID(M4U_LARB3_ID, 0) -#define M4U_PORT_VENC_REC MTK_M4U_ID(M4U_LARB3_ID, 1) -#define M4U_PORT_VENC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 2) -#define M4U_PORT_VENC_SV_COMV MTK_M4U_ID(M4U_LARB3_ID, 3) -#define M4U_PORT_VENC_RD_COMV MTK_M4U_ID(M4U_LARB3_ID, 4) -#define M4U_PORT_JPGENC_RDMA MTK_M4U_ID(M4U_LARB3_ID, 5) -#define M4U_PORT_JPGENC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 6) -#define M4U_PORT_JPGDEC_WDMA MTK_M4U_ID(M4U_LARB3_ID, 7) -#define M4U_PORT_JPGDEC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 8) -#define M4U_PORT_VENC_CUR_LUMA MTK_M4U_ID(M4U_LARB3_ID, 9) -#define M4U_PORT_VENC_CUR_CHROMA MTK_M4U_ID(M4U_LARB3_ID, 10) -#define M4U_PORT_VENC_REF_LUMA MTK_M4U_ID(M4U_LARB3_ID, 11) -#define M4U_PORT_VENC_REF_CHROMA MTK_M4U_ID(M4U_LARB3_ID, 12) -#define M4U_PORT_VENC_NBM_RDMA MTK_M4U_ID(M4U_LARB3_ID, 13) -#define M4U_PORT_VENC_NBM_WDMA MTK_M4U_ID(M4U_LARB3_ID, 14) - -/* larb4 */ -#define M4U_PORT_DISP_OVL1 MTK_M4U_ID(M4U_LARB4_ID, 0) -#define M4U_PORT_DISP_RDMA1 MTK_M4U_ID(M4U_LARB4_ID, 1) -#define M4U_PORT_DISP_RDMA2 MTK_M4U_ID(M4U_LARB4_ID, 2) -#define M4U_PORT_DISP_WDMA1 MTK_M4U_ID(M4U_LARB4_ID, 3) -#define M4U_PORT_MDP_RDMA1 MTK_M4U_ID(M4U_LARB4_ID, 4) -#define M4U_PORT_MDP_WROT1 MTK_M4U_ID(M4U_LARB4_ID, 5) - -/* larb5 */ -#define M4U_PORT_VENC_RCPU_SET2 MTK_M4U_ID(M4U_LARB5_ID, 0) -#define M4U_PORT_VENC_REC_FRM_SET2 MTK_M4U_ID(M4U_LARB5_ID, 1) -#define M4U_PORT_VENC_REF_LUMA_SET2 MTK_M4U_ID(M4U_LARB5_ID, 2) -#define M4U_PORT_VENC_REC_CHROMA_SET2 MTK_M4U_ID(M4U_LARB5_ID, 3) -#define M4U_PORT_VENC_BSDMA_SET2 MTK_M4U_ID(M4U_LARB5_ID, 4) -#define M4U_PORT_VENC_CUR_LUMA_SET2 MTK_M4U_ID(M4U_LARB5_ID, 5) -#define M4U_PORT_VENC_CUR_CHROMA_SET2 MTK_M4U_ID(M4U_LARB5_ID, 6) -#define M4U_PORT_VENC_RD_COMA_SET2 MTK_M4U_ID(M4U_LARB5_ID, 7) -#define M4U_PORT_VENC_SV_COMA_SET2 MTK_M4U_ID(M4U_LARB5_ID, 8) - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/memory/mt8183-larb-port.h b/sys/gnu/dts/include/dt-bindings/memory/mt8183-larb-port.h deleted file mode 100644 index 2c579f30516..00000000000 --- a/sys/gnu/dts/include/dt-bindings/memory/mt8183-larb-port.h +++ /dev/null @@ -1,130 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2018 MediaTek Inc. - * Author: Yong Wu - */ -#ifndef __DTS_IOMMU_PORT_MT8183_H -#define __DTS_IOMMU_PORT_MT8183_H - -#define MTK_M4U_ID(larb, port) (((larb) << 5) | (port)) - -#define M4U_LARB0_ID 0 -#define M4U_LARB1_ID 1 -#define M4U_LARB2_ID 2 -#define M4U_LARB3_ID 3 -#define M4U_LARB4_ID 4 -#define M4U_LARB5_ID 5 -#define M4U_LARB6_ID 6 -#define M4U_LARB7_ID 7 - -/* larb0 */ -#define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID, 0) -#define M4U_PORT_DISP_2L_OVL0_LARB0 MTK_M4U_ID(M4U_LARB0_ID, 1) -#define M4U_PORT_DISP_2L_OVL1_LARB0 MTK_M4U_ID(M4U_LARB0_ID, 2) -#define M4U_PORT_DISP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 3) -#define M4U_PORT_DISP_RDMA1 MTK_M4U_ID(M4U_LARB0_ID, 4) -#define M4U_PORT_DISP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 5) -#define M4U_PORT_MDP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 6) -#define M4U_PORT_MDP_WROT0 MTK_M4U_ID(M4U_LARB0_ID, 7) -#define M4U_PORT_MDP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 8) -#define M4U_PORT_DISP_FAKE0 MTK_M4U_ID(M4U_LARB0_ID, 9) - -/* larb1 */ -#define M4U_PORT_HW_VDEC_MC_EXT MTK_M4U_ID(M4U_LARB1_ID, 0) -#define M4U_PORT_HW_VDEC_PP_EXT MTK_M4U_ID(M4U_LARB1_ID, 1) -#define M4U_PORT_HW_VDEC_VLD_EXT MTK_M4U_ID(M4U_LARB1_ID, 2) -#define M4U_PORT_HW_VDEC_AVC_MV_EXT MTK_M4U_ID(M4U_LARB1_ID, 3) -#define M4U_PORT_HW_VDEC_PRED_RD_EXT MTK_M4U_ID(M4U_LARB1_ID, 4) -#define M4U_PORT_HW_VDEC_PRED_WR_EXT MTK_M4U_ID(M4U_LARB1_ID, 5) -#define M4U_PORT_HW_VDEC_PPWRAP_EXT MTK_M4U_ID(M4U_LARB1_ID, 6) - -/* larb2 VPU0 */ -#define M4U_PORT_IMG_IPUO MTK_M4U_ID(M4U_LARB2_ID, 0) -#define M4U_PORT_IMG_IPU3O MTK_M4U_ID(M4U_LARB2_ID, 1) -#define M4U_PORT_IMG_IPUI MTK_M4U_ID(M4U_LARB2_ID, 2) - -/* larb3 VPU1 */ -#define M4U_PORT_CAM_IPUO MTK_M4U_ID(M4U_LARB3_ID, 0) -#define M4U_PORT_CAM_IPU2O MTK_M4U_ID(M4U_LARB3_ID, 1) -#define M4U_PORT_CAM_IPU3O MTK_M4U_ID(M4U_LARB3_ID, 2) -#define M4U_PORT_CAM_IPUI MTK_M4U_ID(M4U_LARB3_ID, 3) -#define M4U_PORT_CAM_IPU2I MTK_M4U_ID(M4U_LARB3_ID, 4) - -/* larb4 */ -#define M4U_PORT_VENC_RCPU MTK_M4U_ID(M4U_LARB4_ID, 0) -#define M4U_PORT_VENC_REC MTK_M4U_ID(M4U_LARB4_ID, 1) -#define M4U_PORT_VENC_BSDMA MTK_M4U_ID(M4U_LARB4_ID, 2) -#define M4U_PORT_VENC_SV_COMV MTK_M4U_ID(M4U_LARB4_ID, 3) -#define M4U_PORT_VENC_RD_COMV MTK_M4U_ID(M4U_LARB4_ID, 4) -#define M4U_PORT_JPGENC_RDMA MTK_M4U_ID(M4U_LARB4_ID, 5) -#define M4U_PORT_JPGENC_BSDMA MTK_M4U_ID(M4U_LARB4_ID, 6) -#define M4U_PORT_VENC_CUR_LUMA MTK_M4U_ID(M4U_LARB4_ID, 7) -#define M4U_PORT_VENC_CUR_CHROMA MTK_M4U_ID(M4U_LARB4_ID, 8) -#define M4U_PORT_VENC_REF_LUMA MTK_M4U_ID(M4U_LARB4_ID, 9) -#define M4U_PORT_VENC_REF_CHROMA MTK_M4U_ID(M4U_LARB4_ID, 10) - -/* larb5 */ -#define M4U_PORT_CAM_IMGI MTK_M4U_ID(M4U_LARB5_ID, 0) -#define M4U_PORT_CAM_IMG2O MTK_M4U_ID(M4U_LARB5_ID, 1) -#define M4U_PORT_CAM_IMG3O MTK_M4U_ID(M4U_LARB5_ID, 2) -#define M4U_PORT_CAM_VIPI MTK_M4U_ID(M4U_LARB5_ID, 3) -#define M4U_PORT_CAM_LCEI MTK_M4U_ID(M4U_LARB5_ID, 4) -#define M4U_PORT_CAM_SMXI MTK_M4U_ID(M4U_LARB5_ID, 5) -#define M4U_PORT_CAM_SMXO MTK_M4U_ID(M4U_LARB5_ID, 6) -#define M4U_PORT_CAM_WPE0_RDMA1 MTK_M4U_ID(M4U_LARB5_ID, 7) -#define M4U_PORT_CAM_WPE0_RDMA0 MTK_M4U_ID(M4U_LARB5_ID, 8) -#define M4U_PORT_CAM_WPE0_WDMA MTK_M4U_ID(M4U_LARB5_ID, 9) -#define M4U_PORT_CAM_FDVT_RP MTK_M4U_ID(M4U_LARB5_ID, 10) -#define M4U_PORT_CAM_FDVT_WR MTK_M4U_ID(M4U_LARB5_ID, 11) -#define M4U_PORT_CAM_FDVT_RB MTK_M4U_ID(M4U_LARB5_ID, 12) -#define M4U_PORT_CAM_WPE1_RDMA0 MTK_M4U_ID(M4U_LARB5_ID, 13) -#define M4U_PORT_CAM_WPE1_RDMA1 MTK_M4U_ID(M4U_LARB5_ID, 14) -#define M4U_PORT_CAM_WPE1_WDMA MTK_M4U_ID(M4U_LARB5_ID, 15) -#define M4U_PORT_CAM_DPE_RDMA MTK_M4U_ID(M4U_LARB5_ID, 16) -#define M4U_PORT_CAM_DPE_WDMA MTK_M4U_ID(M4U_LARB5_ID, 17) -#define M4U_PORT_CAM_MFB_RDMA0 MTK_M4U_ID(M4U_LARB5_ID, 18) -#define M4U_PORT_CAM_MFB_RDMA1 MTK_M4U_ID(M4U_LARB5_ID, 19) -#define M4U_PORT_CAM_MFB_WDMA MTK_M4U_ID(M4U_LARB5_ID, 20) -#define M4U_PORT_CAM_RSC_RDMA0 MTK_M4U_ID(M4U_LARB5_ID, 21) -#define M4U_PORT_CAM_RSC_WDMA MTK_M4U_ID(M4U_LARB5_ID, 22) -#define M4U_PORT_CAM_OWE_RDMA MTK_M4U_ID(M4U_LARB5_ID, 23) -#define M4U_PORT_CAM_OWE_WDMA MTK_M4U_ID(M4U_LARB5_ID, 24) - -/* larb6 */ -#define M4U_PORT_CAM_IMGO MTK_M4U_ID(M4U_LARB6_ID, 0) -#define M4U_PORT_CAM_RRZO MTK_M4U_ID(M4U_LARB6_ID, 1) -#define M4U_PORT_CAM_AAO MTK_M4U_ID(M4U_LARB6_ID, 2) -#define M4U_PORT_CAM_AFO MTK_M4U_ID(M4U_LARB6_ID, 3) -#define M4U_PORT_CAM_LSCI0 MTK_M4U_ID(M4U_LARB6_ID, 4) -#define M4U_PORT_CAM_LSCI1 MTK_M4U_ID(M4U_LARB6_ID, 5) -#define M4U_PORT_CAM_PDO MTK_M4U_ID(M4U_LARB6_ID, 6) -#define M4U_PORT_CAM_BPCI MTK_M4U_ID(M4U_LARB6_ID, 7) -#define M4U_PORT_CAM_LCSO MTK_M4U_ID(M4U_LARB6_ID, 8) -#define M4U_PORT_CAM_CAM_RSSO_A MTK_M4U_ID(M4U_LARB6_ID, 9) -#define M4U_PORT_CAM_UFEO MTK_M4U_ID(M4U_LARB6_ID, 10) -#define M4U_PORT_CAM_SOCO MTK_M4U_ID(M4U_LARB6_ID, 11) -#define M4U_PORT_CAM_SOC1 MTK_M4U_ID(M4U_LARB6_ID, 12) -#define M4U_PORT_CAM_SOC2 MTK_M4U_ID(M4U_LARB6_ID, 13) -#define M4U_PORT_CAM_CCUI MTK_M4U_ID(M4U_LARB6_ID, 14) -#define M4U_PORT_CAM_CCUO MTK_M4U_ID(M4U_LARB6_ID, 15) -#define M4U_PORT_CAM_RAWI_A MTK_M4U_ID(M4U_LARB6_ID, 16) -#define M4U_PORT_CAM_CCUG MTK_M4U_ID(M4U_LARB6_ID, 17) -#define M4U_PORT_CAM_PSO MTK_M4U_ID(M4U_LARB6_ID, 18) -#define M4U_PORT_CAM_AFO_1 MTK_M4U_ID(M4U_LARB6_ID, 19) -#define M4U_PORT_CAM_LSCI_2 MTK_M4U_ID(M4U_LARB6_ID, 20) -#define M4U_PORT_CAM_PDI MTK_M4U_ID(M4U_LARB6_ID, 21) -#define M4U_PORT_CAM_FLKO MTK_M4U_ID(M4U_LARB6_ID, 22) -#define M4U_PORT_CAM_LMVO MTK_M4U_ID(M4U_LARB6_ID, 23) -#define M4U_PORT_CAM_UFGO MTK_M4U_ID(M4U_LARB6_ID, 24) -#define M4U_PORT_CAM_SPARE MTK_M4U_ID(M4U_LARB6_ID, 25) -#define M4U_PORT_CAM_SPARE_2 MTK_M4U_ID(M4U_LARB6_ID, 26) -#define M4U_PORT_CAM_SPARE_3 MTK_M4U_ID(M4U_LARB6_ID, 27) -#define M4U_PORT_CAM_SPARE_4 MTK_M4U_ID(M4U_LARB6_ID, 28) -#define M4U_PORT_CAM_SPARE_5 MTK_M4U_ID(M4U_LARB6_ID, 29) -#define M4U_PORT_CAM_SPARE_6 MTK_M4U_ID(M4U_LARB6_ID, 30) - -/* CCU */ -#define M4U_PORT_CCU0 MTK_M4U_ID(M4U_LARB7_ID, 0) -#define M4U_PORT_CCU1 MTK_M4U_ID(M4U_LARB7_ID, 1) - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/memory/tegra114-mc.h b/sys/gnu/dts/include/dt-bindings/memory/tegra114-mc.h deleted file mode 100644 index dfe99c8a5ba..00000000000 --- a/sys/gnu/dts/include/dt-bindings/memory/tegra114-mc.h +++ /dev/null @@ -1,43 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef DT_BINDINGS_MEMORY_TEGRA114_MC_H -#define DT_BINDINGS_MEMORY_TEGRA114_MC_H - -#define TEGRA_SWGROUP_PTC 0 -#define TEGRA_SWGROUP_DC 1 -#define TEGRA_SWGROUP_DCB 2 -#define TEGRA_SWGROUP_EPP 3 -#define TEGRA_SWGROUP_G2 4 -#define TEGRA_SWGROUP_AVPC 5 -#define TEGRA_SWGROUP_NV 6 -#define TEGRA_SWGROUP_HDA 7 -#define TEGRA_SWGROUP_HC 8 -#define TEGRA_SWGROUP_MSENC 9 -#define TEGRA_SWGROUP_PPCS 10 -#define TEGRA_SWGROUP_VDE 11 -#define TEGRA_SWGROUP_MPCORELP 12 -#define TEGRA_SWGROUP_MPCORE 13 -#define TEGRA_SWGROUP_VI 14 -#define TEGRA_SWGROUP_ISP 15 -#define TEGRA_SWGROUP_XUSB_HOST 16 -#define TEGRA_SWGROUP_XUSB_DEV 17 -#define TEGRA_SWGROUP_EMUCIF 18 -#define TEGRA_SWGROUP_TSEC 19 - -#define TEGRA114_MC_RESET_AVPC 0 -#define TEGRA114_MC_RESET_DC 1 -#define TEGRA114_MC_RESET_DCB 2 -#define TEGRA114_MC_RESET_EPP 3 -#define TEGRA114_MC_RESET_2D 4 -#define TEGRA114_MC_RESET_HC 5 -#define TEGRA114_MC_RESET_HDA 6 -#define TEGRA114_MC_RESET_ISP 7 -#define TEGRA114_MC_RESET_MPCORE 8 -#define TEGRA114_MC_RESET_MPCORELP 9 -#define TEGRA114_MC_RESET_MPE 10 -#define TEGRA114_MC_RESET_3D 11 -#define TEGRA114_MC_RESET_3D2 12 -#define TEGRA114_MC_RESET_PPCS 13 -#define TEGRA114_MC_RESET_VDE 14 -#define TEGRA114_MC_RESET_VI 15 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/memory/tegra124-mc.h b/sys/gnu/dts/include/dt-bindings/memory/tegra124-mc.h deleted file mode 100644 index 186e6b7e9b3..00000000000 --- a/sys/gnu/dts/include/dt-bindings/memory/tegra124-mc.h +++ /dev/null @@ -1,57 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef DT_BINDINGS_MEMORY_TEGRA124_MC_H -#define DT_BINDINGS_MEMORY_TEGRA124_MC_H - -#define TEGRA_SWGROUP_PTC 0 -#define TEGRA_SWGROUP_DC 1 -#define TEGRA_SWGROUP_DCB 2 -#define TEGRA_SWGROUP_AFI 3 -#define TEGRA_SWGROUP_AVPC 4 -#define TEGRA_SWGROUP_HDA 5 -#define TEGRA_SWGROUP_HC 6 -#define TEGRA_SWGROUP_MSENC 7 -#define TEGRA_SWGROUP_PPCS 8 -#define TEGRA_SWGROUP_SATA 9 -#define TEGRA_SWGROUP_VDE 10 -#define TEGRA_SWGROUP_MPCORELP 11 -#define TEGRA_SWGROUP_MPCORE 12 -#define TEGRA_SWGROUP_ISP2 13 -#define TEGRA_SWGROUP_XUSB_HOST 14 -#define TEGRA_SWGROUP_XUSB_DEV 15 -#define TEGRA_SWGROUP_ISP2B 16 -#define TEGRA_SWGROUP_TSEC 17 -#define TEGRA_SWGROUP_A9AVP 18 -#define TEGRA_SWGROUP_GPU 19 -#define TEGRA_SWGROUP_SDMMC1A 20 -#define TEGRA_SWGROUP_SDMMC2A 21 -#define TEGRA_SWGROUP_SDMMC3A 22 -#define TEGRA_SWGROUP_SDMMC4A 23 -#define TEGRA_SWGROUP_VIC 24 -#define TEGRA_SWGROUP_VI 25 - -#define TEGRA124_MC_RESET_AFI 0 -#define TEGRA124_MC_RESET_AVPC 1 -#define TEGRA124_MC_RESET_DC 2 -#define TEGRA124_MC_RESET_DCB 3 -#define TEGRA124_MC_RESET_HC 4 -#define TEGRA124_MC_RESET_HDA 5 -#define TEGRA124_MC_RESET_ISP2 6 -#define TEGRA124_MC_RESET_MPCORE 7 -#define TEGRA124_MC_RESET_MPCORELP 8 -#define TEGRA124_MC_RESET_MSENC 9 -#define TEGRA124_MC_RESET_PPCS 10 -#define TEGRA124_MC_RESET_SATA 11 -#define TEGRA124_MC_RESET_VDE 12 -#define TEGRA124_MC_RESET_VI 13 -#define TEGRA124_MC_RESET_VIC 14 -#define TEGRA124_MC_RESET_XUSB_HOST 15 -#define TEGRA124_MC_RESET_XUSB_DEV 16 -#define TEGRA124_MC_RESET_TSEC 17 -#define TEGRA124_MC_RESET_SDMMC1 18 -#define TEGRA124_MC_RESET_SDMMC2 19 -#define TEGRA124_MC_RESET_SDMMC3 20 -#define TEGRA124_MC_RESET_SDMMC4 21 -#define TEGRA124_MC_RESET_ISP2B 22 -#define TEGRA124_MC_RESET_GPU 23 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/memory/tegra186-mc.h b/sys/gnu/dts/include/dt-bindings/memory/tegra186-mc.h deleted file mode 100644 index 82a1e27f735..00000000000 --- a/sys/gnu/dts/include/dt-bindings/memory/tegra186-mc.h +++ /dev/null @@ -1,250 +0,0 @@ -#ifndef DT_BINDINGS_MEMORY_TEGRA186_MC_H -#define DT_BINDINGS_MEMORY_TEGRA186_MC_H - -/* special clients */ -#define TEGRA186_SID_INVALID 0x00 -#define TEGRA186_SID_PASSTHROUGH 0x7f - -/* host1x clients */ -#define TEGRA186_SID_HOST1X 0x01 -#define TEGRA186_SID_CSI 0x02 -#define TEGRA186_SID_VIC 0x03 -#define TEGRA186_SID_VI 0x04 -#define TEGRA186_SID_ISP 0x05 -#define TEGRA186_SID_NVDEC 0x06 -#define TEGRA186_SID_NVENC 0x07 -#define TEGRA186_SID_NVJPG 0x08 -#define TEGRA186_SID_NVDISPLAY 0x09 -#define TEGRA186_SID_TSEC 0x0a -#define TEGRA186_SID_TSECB 0x0b -#define TEGRA186_SID_SE 0x0c -#define TEGRA186_SID_SE1 0x0d -#define TEGRA186_SID_SE2 0x0e -#define TEGRA186_SID_SE3 0x0f - -/* GPU clients */ -#define TEGRA186_SID_GPU 0x10 - -/* other SoC clients */ -#define TEGRA186_SID_AFI 0x11 -#define TEGRA186_SID_HDA 0x12 -#define TEGRA186_SID_ETR 0x13 -#define TEGRA186_SID_EQOS 0x14 -#define TEGRA186_SID_UFSHC 0x15 -#define TEGRA186_SID_AON 0x16 -#define TEGRA186_SID_SDMMC4 0x17 -#define TEGRA186_SID_SDMMC3 0x18 -#define TEGRA186_SID_SDMMC2 0x19 -#define TEGRA186_SID_SDMMC1 0x1a -#define TEGRA186_SID_XUSB_HOST 0x1b -#define TEGRA186_SID_XUSB_DEV 0x1c -#define TEGRA186_SID_SATA 0x1d -#define TEGRA186_SID_APE 0x1e -#define TEGRA186_SID_SCE 0x1f - -/* GPC DMA clients */ -#define TEGRA186_SID_GPCDMA_0 0x20 -#define TEGRA186_SID_GPCDMA_1 0x21 -#define TEGRA186_SID_GPCDMA_2 0x22 -#define TEGRA186_SID_GPCDMA_3 0x23 -#define TEGRA186_SID_GPCDMA_4 0x24 -#define TEGRA186_SID_GPCDMA_5 0x25 -#define TEGRA186_SID_GPCDMA_6 0x26 -#define TEGRA186_SID_GPCDMA_7 0x27 - -/* APE DMA clients */ -#define TEGRA186_SID_APE_1 0x28 -#define TEGRA186_SID_APE_2 0x29 - -/* camera RTCPU */ -#define TEGRA186_SID_RCE 0x2a - -/* camera RTCPU on host1x address space */ -#define TEGRA186_SID_RCE_1X 0x2b - -/* APE DMA clients */ -#define TEGRA186_SID_APE_3 0x2c - -/* camera RTCPU running on APE */ -#define TEGRA186_SID_APE_CAM 0x2d -#define TEGRA186_SID_APE_CAM_1X 0x2e - -/* - * The BPMP has its SID value hardcoded in the firmware. Changing it requires - * considerable effort. - */ -#define TEGRA186_SID_BPMP 0x32 - -/* for SMMU tests */ -#define TEGRA186_SID_SMMU_TEST 0x33 - -/* host1x virtualization channels */ -#define TEGRA186_SID_HOST1X_CTX0 0x38 -#define TEGRA186_SID_HOST1X_CTX1 0x39 -#define TEGRA186_SID_HOST1X_CTX2 0x3a -#define TEGRA186_SID_HOST1X_CTX3 0x3b -#define TEGRA186_SID_HOST1X_CTX4 0x3c -#define TEGRA186_SID_HOST1X_CTX5 0x3d -#define TEGRA186_SID_HOST1X_CTX6 0x3e -#define TEGRA186_SID_HOST1X_CTX7 0x3f - -/* host1x command buffers */ -#define TEGRA186_SID_HOST1X_VM0 0x40 -#define TEGRA186_SID_HOST1X_VM1 0x41 -#define TEGRA186_SID_HOST1X_VM2 0x42 -#define TEGRA186_SID_HOST1X_VM3 0x43 -#define TEGRA186_SID_HOST1X_VM4 0x44 -#define TEGRA186_SID_HOST1X_VM5 0x45 -#define TEGRA186_SID_HOST1X_VM6 0x46 -#define TEGRA186_SID_HOST1X_VM7 0x47 - -/* SE data buffers */ -#define TEGRA186_SID_SE_VM0 0x48 -#define TEGRA186_SID_SE_VM1 0x49 -#define TEGRA186_SID_SE_VM2 0x4a -#define TEGRA186_SID_SE_VM3 0x4b -#define TEGRA186_SID_SE_VM4 0x4c -#define TEGRA186_SID_SE_VM5 0x4d -#define TEGRA186_SID_SE_VM6 0x4e -#define TEGRA186_SID_SE_VM7 0x4f - -/* - * memory client IDs - */ - -/* Misses from System Memory Management Unit (SMMU) Page Table Cache (PTC) */ -#define TEGRA186_MEMORY_CLIENT_PTCR 0x00 -/* PCIE reads */ -#define TEGRA186_MEMORY_CLIENT_AFIR 0x0e -/* High-definition audio (HDA) reads */ -#define TEGRA186_MEMORY_CLIENT_HDAR 0x15 -/* Host channel data reads */ -#define TEGRA186_MEMORY_CLIENT_HOST1XDMAR 0x16 -#define TEGRA186_MEMORY_CLIENT_NVENCSRD 0x1c -/* SATA reads */ -#define TEGRA186_MEMORY_CLIENT_SATAR 0x1f -/* Reads from Cortex-A9 4 CPU cores via the L2 cache */ -#define TEGRA186_MEMORY_CLIENT_MPCORER 0x27 -#define TEGRA186_MEMORY_CLIENT_NVENCSWR 0x2b -/* PCIE writes */ -#define TEGRA186_MEMORY_CLIENT_AFIW 0x31 -/* High-definition audio (HDA) writes */ -#define TEGRA186_MEMORY_CLIENT_HDAW 0x35 -/* Writes from Cortex-A9 4 CPU cores via the L2 cache */ -#define TEGRA186_MEMORY_CLIENT_MPCOREW 0x39 -/* SATA writes */ -#define TEGRA186_MEMORY_CLIENT_SATAW 0x3d -/* ISP Read client for Crossbar A */ -#define TEGRA186_MEMORY_CLIENT_ISPRA 0x44 -/* ISP Write client for Crossbar A */ -#define TEGRA186_MEMORY_CLIENT_ISPWA 0x46 -/* ISP Write client Crossbar B */ -#define TEGRA186_MEMORY_CLIENT_ISPWB 0x47 -/* XUSB reads */ -#define TEGRA186_MEMORY_CLIENT_XUSB_HOSTR 0x4a -/* XUSB_HOST writes */ -#define TEGRA186_MEMORY_CLIENT_XUSB_HOSTW 0x4b -/* XUSB reads */ -#define TEGRA186_MEMORY_CLIENT_XUSB_DEVR 0x4c -/* XUSB_DEV writes */ -#define TEGRA186_MEMORY_CLIENT_XUSB_DEVW 0x4d -/* TSEC Memory Return Data Client Description */ -#define TEGRA186_MEMORY_CLIENT_TSECSRD 0x54 -/* TSEC Memory Write Client Description */ -#define TEGRA186_MEMORY_CLIENT_TSECSWR 0x55 -/* 3D, ltcx reads instance 0 */ -#define TEGRA186_MEMORY_CLIENT_GPUSRD 0x58 -/* 3D, ltcx writes instance 0 */ -#define TEGRA186_MEMORY_CLIENT_GPUSWR 0x59 -/* sdmmca memory read client */ -#define TEGRA186_MEMORY_CLIENT_SDMMCRA 0x60 -/* sdmmcbmemory read client */ -#define TEGRA186_MEMORY_CLIENT_SDMMCRAA 0x61 -/* sdmmc memory read client */ -#define TEGRA186_MEMORY_CLIENT_SDMMCR 0x62 -/* sdmmcd memory read client */ -#define TEGRA186_MEMORY_CLIENT_SDMMCRAB 0x63 -/* sdmmca memory write client */ -#define TEGRA186_MEMORY_CLIENT_SDMMCWA 0x64 -/* sdmmcb memory write client */ -#define TEGRA186_MEMORY_CLIENT_SDMMCWAA 0x65 -/* sdmmc memory write client */ -#define TEGRA186_MEMORY_CLIENT_SDMMCW 0x66 -/* sdmmcd memory write client */ -#define TEGRA186_MEMORY_CLIENT_SDMMCWAB 0x67 -#define TEGRA186_MEMORY_CLIENT_VICSRD 0x6c -#define TEGRA186_MEMORY_CLIENT_VICSWR 0x6d -/* VI Write client */ -#define TEGRA186_MEMORY_CLIENT_VIW 0x72 -#define TEGRA186_MEMORY_CLIENT_NVDECSRD 0x78 -#define TEGRA186_MEMORY_CLIENT_NVDECSWR 0x79 -/* Audio Processing (APE) engine reads */ -#define TEGRA186_MEMORY_CLIENT_APER 0x7a -/* Audio Processing (APE) engine writes */ -#define TEGRA186_MEMORY_CLIENT_APEW 0x7b -#define TEGRA186_MEMORY_CLIENT_NVJPGSRD 0x7e -#define TEGRA186_MEMORY_CLIENT_NVJPGSWR 0x7f -/* SE Memory Return Data Client Description */ -#define TEGRA186_MEMORY_CLIENT_SESRD 0x80 -/* SE Memory Write Client Description */ -#define TEGRA186_MEMORY_CLIENT_SESWR 0x81 -/* ETR reads */ -#define TEGRA186_MEMORY_CLIENT_ETRR 0x84 -/* ETR writes */ -#define TEGRA186_MEMORY_CLIENT_ETRW 0x85 -/* TSECB Memory Return Data Client Description */ -#define TEGRA186_MEMORY_CLIENT_TSECSRDB 0x86 -/* TSECB Memory Write Client Description */ -#define TEGRA186_MEMORY_CLIENT_TSECSWRB 0x87 -/* 3D, ltcx reads instance 1 */ -#define TEGRA186_MEMORY_CLIENT_GPUSRD2 0x88 -/* 3D, ltcx writes instance 1 */ -#define TEGRA186_MEMORY_CLIENT_GPUSWR2 0x89 -/* AXI Switch read client */ -#define TEGRA186_MEMORY_CLIENT_AXISR 0x8c -/* AXI Switch write client */ -#define TEGRA186_MEMORY_CLIENT_AXISW 0x8d -/* EQOS read client */ -#define TEGRA186_MEMORY_CLIENT_EQOSR 0x8e -/* EQOS write client */ -#define TEGRA186_MEMORY_CLIENT_EQOSW 0x8f -/* UFSHC read client */ -#define TEGRA186_MEMORY_CLIENT_UFSHCR 0x90 -/* UFSHC write client */ -#define TEGRA186_MEMORY_CLIENT_UFSHCW 0x91 -/* NVDISPLAY read client */ -#define TEGRA186_MEMORY_CLIENT_NVDISPLAYR 0x92 -/* BPMP read client */ -#define TEGRA186_MEMORY_CLIENT_BPMPR 0x93 -/* BPMP write client */ -#define TEGRA186_MEMORY_CLIENT_BPMPW 0x94 -/* BPMPDMA read client */ -#define TEGRA186_MEMORY_CLIENT_BPMPDMAR 0x95 -/* BPMPDMA write client */ -#define TEGRA186_MEMORY_CLIENT_BPMPDMAW 0x96 -/* AON read client */ -#define TEGRA186_MEMORY_CLIENT_AONR 0x97 -/* AON write client */ -#define TEGRA186_MEMORY_CLIENT_AONW 0x98 -/* AONDMA read client */ -#define TEGRA186_MEMORY_CLIENT_AONDMAR 0x99 -/* AONDMA write client */ -#define TEGRA186_MEMORY_CLIENT_AONDMAW 0x9a -/* SCE read client */ -#define TEGRA186_MEMORY_CLIENT_SCER 0x9b -/* SCE write client */ -#define TEGRA186_MEMORY_CLIENT_SCEW 0x9c -/* SCEDMA read client */ -#define TEGRA186_MEMORY_CLIENT_SCEDMAR 0x9d -/* SCEDMA write client */ -#define TEGRA186_MEMORY_CLIENT_SCEDMAW 0x9e -/* APEDMA read client */ -#define TEGRA186_MEMORY_CLIENT_APEDMAR 0x9f -/* APEDMA write client */ -#define TEGRA186_MEMORY_CLIENT_APEDMAW 0xa0 -/* NVDISPLAY read client instance 2 */ -#define TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 0xa1 -#define TEGRA186_MEMORY_CLIENT_VICSRD1 0xa2 -#define TEGRA186_MEMORY_CLIENT_NVDECSRD1 0xa3 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/memory/tegra194-mc.h b/sys/gnu/dts/include/dt-bindings/memory/tegra194-mc.h deleted file mode 100644 index eed48b746bc..00000000000 --- a/sys/gnu/dts/include/dt-bindings/memory/tegra194-mc.h +++ /dev/null @@ -1,410 +0,0 @@ -#ifndef DT_BINDINGS_MEMORY_TEGRA194_MC_H -#define DT_BINDINGS_MEMORY_TEGRA194_MC_H - -/* special clients */ -#define TEGRA194_SID_INVALID 0x00 -#define TEGRA194_SID_PASSTHROUGH 0x7f - -/* host1x clients */ -#define TEGRA194_SID_HOST1X 0x01 -#define TEGRA194_SID_CSI 0x02 -#define TEGRA194_SID_VIC 0x03 -#define TEGRA194_SID_VI 0x04 -#define TEGRA194_SID_ISP 0x05 -#define TEGRA194_SID_NVDEC 0x06 -#define TEGRA194_SID_NVENC 0x07 -#define TEGRA194_SID_NVJPG 0x08 -#define TEGRA194_SID_NVDISPLAY 0x09 -#define TEGRA194_SID_TSEC 0x0a -#define TEGRA194_SID_TSECB 0x0b -#define TEGRA194_SID_SE 0x0c -#define TEGRA194_SID_SE1 0x0d -#define TEGRA194_SID_SE2 0x0e -#define TEGRA194_SID_SE3 0x0f - -/* GPU clients */ -#define TEGRA194_SID_GPU 0x10 - -/* other SoC clients */ -#define TEGRA194_SID_AFI 0x11 -#define TEGRA194_SID_HDA 0x12 -#define TEGRA194_SID_ETR 0x13 -#define TEGRA194_SID_EQOS 0x14 -#define TEGRA194_SID_UFSHC 0x15 -#define TEGRA194_SID_AON 0x16 -#define TEGRA194_SID_SDMMC4 0x17 -#define TEGRA194_SID_SDMMC3 0x18 -#define TEGRA194_SID_SDMMC2 0x19 -#define TEGRA194_SID_SDMMC1 0x1a -#define TEGRA194_SID_XUSB_HOST 0x1b -#define TEGRA194_SID_XUSB_DEV 0x1c -#define TEGRA194_SID_SATA 0x1d -#define TEGRA194_SID_APE 0x1e -#define TEGRA194_SID_SCE 0x1f - -/* GPC DMA clients */ -#define TEGRA194_SID_GPCDMA_0 0x20 -#define TEGRA194_SID_GPCDMA_1 0x21 -#define TEGRA194_SID_GPCDMA_2 0x22 -#define TEGRA194_SID_GPCDMA_3 0x23 -#define TEGRA194_SID_GPCDMA_4 0x24 -#define TEGRA194_SID_GPCDMA_5 0x25 -#define TEGRA194_SID_GPCDMA_6 0x26 -#define TEGRA194_SID_GPCDMA_7 0x27 - -/* APE DMA clients */ -#define TEGRA194_SID_APE_1 0x28 -#define TEGRA194_SID_APE_2 0x29 - -/* camera RTCPU */ -#define TEGRA194_SID_RCE 0x2a - -/* camera RTCPU on host1x address space */ -#define TEGRA194_SID_RCE_1X 0x2b - -/* APE DMA clients */ -#define TEGRA194_SID_APE_3 0x2c - -/* camera RTCPU running on APE */ -#define TEGRA194_SID_APE_CAM 0x2d -#define TEGRA194_SID_APE_CAM_1X 0x2e - -#define TEGRA194_SID_RCE_RM 0x2f -#define TEGRA194_SID_VI_FALCON 0x30 -#define TEGRA194_SID_ISP_FALCON 0x31 - -/* - * The BPMP has its SID value hardcoded in the firmware. Changing it requires - * considerable effort. - */ -#define TEGRA194_SID_BPMP 0x32 - -/* for SMMU tests */ -#define TEGRA194_SID_SMMU_TEST 0x33 - -/* host1x virtualization channels */ -#define TEGRA194_SID_HOST1X_CTX0 0x38 -#define TEGRA194_SID_HOST1X_CTX1 0x39 -#define TEGRA194_SID_HOST1X_CTX2 0x3a -#define TEGRA194_SID_HOST1X_CTX3 0x3b -#define TEGRA194_SID_HOST1X_CTX4 0x3c -#define TEGRA194_SID_HOST1X_CTX5 0x3d -#define TEGRA194_SID_HOST1X_CTX6 0x3e -#define TEGRA194_SID_HOST1X_CTX7 0x3f - -/* host1x command buffers */ -#define TEGRA194_SID_HOST1X_VM0 0x40 -#define TEGRA194_SID_HOST1X_VM1 0x41 -#define TEGRA194_SID_HOST1X_VM2 0x42 -#define TEGRA194_SID_HOST1X_VM3 0x43 -#define TEGRA194_SID_HOST1X_VM4 0x44 -#define TEGRA194_SID_HOST1X_VM5 0x45 -#define TEGRA194_SID_HOST1X_VM6 0x46 -#define TEGRA194_SID_HOST1X_VM7 0x47 - -/* SE data buffers */ -#define TEGRA194_SID_SE_VM0 0x48 -#define TEGRA194_SID_SE_VM1 0x49 -#define TEGRA194_SID_SE_VM2 0x4a -#define TEGRA194_SID_SE_VM3 0x4b -#define TEGRA194_SID_SE_VM4 0x4c -#define TEGRA194_SID_SE_VM5 0x4d -#define TEGRA194_SID_SE_VM6 0x4e -#define TEGRA194_SID_SE_VM7 0x4f - -#define TEGRA194_SID_MIU 0x50 - -#define TEGRA194_SID_NVDLA0 0x51 -#define TEGRA194_SID_NVDLA1 0x52 - -#define TEGRA194_SID_PVA0 0x53 -#define TEGRA194_SID_PVA1 0x54 -#define TEGRA194_SID_NVENC1 0x55 -#define TEGRA194_SID_PCIE0 0x56 -#define TEGRA194_SID_PCIE1 0x57 -#define TEGRA194_SID_PCIE2 0x58 -#define TEGRA194_SID_PCIE3 0x59 -#define TEGRA194_SID_PCIE4 0x5a -#define TEGRA194_SID_PCIE5 0x5b -#define TEGRA194_SID_NVDEC1 0x5c - -#define TEGRA194_SID_XUSB_VF0 0x5d -#define TEGRA194_SID_XUSB_VF1 0x5e -#define TEGRA194_SID_XUSB_VF2 0x5f -#define TEGRA194_SID_XUSB_VF3 0x60 - -#define TEGRA194_SID_RCE_VM3 0x61 -#define TEGRA194_SID_VI_VM2 0x62 -#define TEGRA194_SID_VI_VM3 0x63 -#define TEGRA194_SID_RCE_SERVER 0x64 - -/* - * memory client IDs - */ - -/* Misses from System Memory Management Unit (SMMU) Page Table Cache (PTC) */ -#define TEGRA194_MEMORY_CLIENT_PTCR 0x00 -/* MSS internal memqual MIU7 read clients */ -#define TEGRA194_MEMORY_CLIENT_MIU7R 0x01 -/* MSS internal memqual MIU7 write clients */ -#define TEGRA194_MEMORY_CLIENT_MIU7W 0x02 -/* High-definition audio (HDA) read clients */ -#define TEGRA194_MEMORY_CLIENT_HDAR 0x15 -/* Host channel data read clients */ -#define TEGRA194_MEMORY_CLIENT_HOST1XDMAR 0x16 -#define TEGRA194_MEMORY_CLIENT_NVENCSRD 0x1c -/* SATA read clients */ -#define TEGRA194_MEMORY_CLIENT_SATAR 0x1f -/* Reads from Cortex-A9 4 CPU cores via the L2 cache */ -#define TEGRA194_MEMORY_CLIENT_MPCORER 0x27 -#define TEGRA194_MEMORY_CLIENT_NVENCSWR 0x2b -/* High-definition audio (HDA) write clients */ -#define TEGRA194_MEMORY_CLIENT_HDAW 0x35 -/* Writes from Cortex-A9 4 CPU cores via the L2 cache */ -#define TEGRA194_MEMORY_CLIENT_MPCOREW 0x39 -/* SATA write clients */ -#define TEGRA194_MEMORY_CLIENT_SATAW 0x3d -/* ISP read client for Crossbar A */ -#define TEGRA194_MEMORY_CLIENT_ISPRA 0x44 -/* ISP read client 1 for Crossbar A */ -#define TEGRA194_MEMORY_CLIENT_ISPFALR 0x45 -/* ISP Write client for Crossbar A */ -#define TEGRA194_MEMORY_CLIENT_ISPWA 0x46 -/* ISP Write client Crossbar B */ -#define TEGRA194_MEMORY_CLIENT_ISPWB 0x47 -/* XUSB_HOST read clients */ -#define TEGRA194_MEMORY_CLIENT_XUSB_HOSTR 0x4a -/* XUSB_HOST write clients */ -#define TEGRA194_MEMORY_CLIENT_XUSB_HOSTW 0x4b -/* XUSB read clients */ -#define TEGRA194_MEMORY_CLIENT_XUSB_DEVR 0x4c -/* XUSB_DEV write clients */ -#define TEGRA194_MEMORY_CLIENT_XUSB_DEVW 0x4d -/* sdmmca memory read client */ -#define TEGRA194_MEMORY_CLIENT_SDMMCRA 0x60 -/* sdmmc memory read client */ -#define TEGRA194_MEMORY_CLIENT_SDMMCR 0x62 -/* sdmmcd memory read client */ -#define TEGRA194_MEMORY_CLIENT_SDMMCRAB 0x63 -/* sdmmca memory write client */ -#define TEGRA194_MEMORY_CLIENT_SDMMCWA 0x64 -/* sdmmc memory write client */ -#define TEGRA194_MEMORY_CLIENT_SDMMCW 0x66 -/* sdmmcd memory write client */ -#define TEGRA194_MEMORY_CLIENT_SDMMCWAB 0x67 -#define TEGRA194_MEMORY_CLIENT_VICSRD 0x6c -#define TEGRA194_MEMORY_CLIENT_VICSWR 0x6d -/* VI Write client */ -#define TEGRA194_MEMORY_CLIENT_VIW 0x72 -#define TEGRA194_MEMORY_CLIENT_NVDECSRD 0x78 -#define TEGRA194_MEMORY_CLIENT_NVDECSWR 0x79 -/* Audio Processing (APE) engine read clients */ -#define TEGRA194_MEMORY_CLIENT_APER 0x7a -/* Audio Processing (APE) engine write clients */ -#define TEGRA194_MEMORY_CLIENT_APEW 0x7b -#define TEGRA194_MEMORY_CLIENT_NVJPGSRD 0x7e -#define TEGRA194_MEMORY_CLIENT_NVJPGSWR 0x7f -/* AXI AP and DFD-AUX0/1 read clients Both share the same interface on the on MSS */ -#define TEGRA194_MEMORY_CLIENT_AXIAPR 0x82 -/* AXI AP and DFD-AUX0/1 write clients Both sahre the same interface on MSS */ -#define TEGRA194_MEMORY_CLIENT_AXIAPW 0x83 -/* ETR read clients */ -#define TEGRA194_MEMORY_CLIENT_ETRR 0x84 -/* ETR write clients */ -#define TEGRA194_MEMORY_CLIENT_ETRW 0x85 -/* AXI Switch read client */ -#define TEGRA194_MEMORY_CLIENT_AXISR 0x8c -/* AXI Switch write client */ -#define TEGRA194_MEMORY_CLIENT_AXISW 0x8d -/* EQOS read client */ -#define TEGRA194_MEMORY_CLIENT_EQOSR 0x8e -/* EQOS write client */ -#define TEGRA194_MEMORY_CLIENT_EQOSW 0x8f -/* UFSHC read client */ -#define TEGRA194_MEMORY_CLIENT_UFSHCR 0x90 -/* UFSHC write client */ -#define TEGRA194_MEMORY_CLIENT_UFSHCW 0x91 -/* NVDISPLAY read client */ -#define TEGRA194_MEMORY_CLIENT_NVDISPLAYR 0x92 -/* BPMP read client */ -#define TEGRA194_MEMORY_CLIENT_BPMPR 0x93 -/* BPMP write client */ -#define TEGRA194_MEMORY_CLIENT_BPMPW 0x94 -/* BPMPDMA read client */ -#define TEGRA194_MEMORY_CLIENT_BPMPDMAR 0x95 -/* BPMPDMA write client */ -#define TEGRA194_MEMORY_CLIENT_BPMPDMAW 0x96 -/* AON read client */ -#define TEGRA194_MEMORY_CLIENT_AONR 0x97 -/* AON write client */ -#define TEGRA194_MEMORY_CLIENT_AONW 0x98 -/* AONDMA read client */ -#define TEGRA194_MEMORY_CLIENT_AONDMAR 0x99 -/* AONDMA write client */ -#define TEGRA194_MEMORY_CLIENT_AONDMAW 0x9a -/* SCE read client */ -#define TEGRA194_MEMORY_CLIENT_SCER 0x9b -/* SCE write client */ -#define TEGRA194_MEMORY_CLIENT_SCEW 0x9c -/* SCEDMA read client */ -#define TEGRA194_MEMORY_CLIENT_SCEDMAR 0x9d -/* SCEDMA write client */ -#define TEGRA194_MEMORY_CLIENT_SCEDMAW 0x9e -/* APEDMA read client */ -#define TEGRA194_MEMORY_CLIENT_APEDMAR 0x9f -/* APEDMA write client */ -#define TEGRA194_MEMORY_CLIENT_APEDMAW 0xa0 -/* NVDISPLAY read client instance 2 */ -#define TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 0xa1 -#define TEGRA194_MEMORY_CLIENT_VICSRD1 0xa2 -#define TEGRA194_MEMORY_CLIENT_NVDECSRD1 0xa3 -/* MSS internal memqual MIU0 read clients */ -#define TEGRA194_MEMORY_CLIENT_MIU0R 0xa6 -/* MSS internal memqual MIU0 write clients */ -#define TEGRA194_MEMORY_CLIENT_MIU0W 0xa7 -/* MSS internal memqual MIU1 read clients */ -#define TEGRA194_MEMORY_CLIENT_MIU1R 0xa8 -/* MSS internal memqual MIU1 write clients */ -#define TEGRA194_MEMORY_CLIENT_MIU1W 0xa9 -/* MSS internal memqual MIU2 read clients */ -#define TEGRA194_MEMORY_CLIENT_MIU2R 0xae -/* MSS internal memqual MIU2 write clients */ -#define TEGRA194_MEMORY_CLIENT_MIU2W 0xaf -/* MSS internal memqual MIU3 read clients */ -#define TEGRA194_MEMORY_CLIENT_MIU3R 0xb0 -/* MSS internal memqual MIU3 write clients */ -#define TEGRA194_MEMORY_CLIENT_MIU3W 0xb1 -/* MSS internal memqual MIU4 read clients */ -#define TEGRA194_MEMORY_CLIENT_MIU4R 0xb2 -/* MSS internal memqual MIU4 write clients */ -#define TEGRA194_MEMORY_CLIENT_MIU4W 0xb3 -#define TEGRA194_MEMORY_CLIENT_DPMUR 0xb4 -#define TEGRA194_MEMORY_CLIENT_DPMUW 0xb5 -#define TEGRA194_MEMORY_CLIENT_NVL0R 0xb6 -#define TEGRA194_MEMORY_CLIENT_NVL0W 0xb7 -#define TEGRA194_MEMORY_CLIENT_NVL1R 0xb8 -#define TEGRA194_MEMORY_CLIENT_NVL1W 0xb9 -#define TEGRA194_MEMORY_CLIENT_NVL2R 0xba -#define TEGRA194_MEMORY_CLIENT_NVL2W 0xbb -/* VI FLACON read clients */ -#define TEGRA194_MEMORY_CLIENT_VIFALR 0xbc -/* VIFAL write clients */ -#define TEGRA194_MEMORY_CLIENT_VIFALW 0xbd -/* DLA0ARDA read clients */ -#define TEGRA194_MEMORY_CLIENT_DLA0RDA 0xbe -/* DLA0 Falcon read clients */ -#define TEGRA194_MEMORY_CLIENT_DLA0FALRDB 0xbf -/* DLA0 write clients */ -#define TEGRA194_MEMORY_CLIENT_DLA0WRA 0xc0 -/* DLA0 write clients */ -#define TEGRA194_MEMORY_CLIENT_DLA0FALWRB 0xc1 -/* DLA1ARDA read clients */ -#define TEGRA194_MEMORY_CLIENT_DLA1RDA 0xc2 -/* DLA1 Falcon read clients */ -#define TEGRA194_MEMORY_CLIENT_DLA1FALRDB 0xc3 -/* DLA1 write clients */ -#define TEGRA194_MEMORY_CLIENT_DLA1WRA 0xc4 -/* DLA1 write clients */ -#define TEGRA194_MEMORY_CLIENT_DLA1FALWRB 0xc5 -/* PVA0RDA read clients */ -#define TEGRA194_MEMORY_CLIENT_PVA0RDA 0xc6 -/* PVA0RDB read clients */ -#define TEGRA194_MEMORY_CLIENT_PVA0RDB 0xc7 -/* PVA0RDC read clients */ -#define TEGRA194_MEMORY_CLIENT_PVA0RDC 0xc8 -/* PVA0WRA write clients */ -#define TEGRA194_MEMORY_CLIENT_PVA0WRA 0xc9 -/* PVA0WRB write clients */ -#define TEGRA194_MEMORY_CLIENT_PVA0WRB 0xca -/* PVA0WRC write clients */ -#define TEGRA194_MEMORY_CLIENT_PVA0WRC 0xcb -/* PVA1RDA read clients */ -#define TEGRA194_MEMORY_CLIENT_PVA1RDA 0xcc -/* PVA1RDB read clients */ -#define TEGRA194_MEMORY_CLIENT_PVA1RDB 0xcd -/* PVA1RDC read clients */ -#define TEGRA194_MEMORY_CLIENT_PVA1RDC 0xce -/* PVA1WRA write clients */ -#define TEGRA194_MEMORY_CLIENT_PVA1WRA 0xcf -/* PVA1WRB write clients */ -#define TEGRA194_MEMORY_CLIENT_PVA1WRB 0xd0 -/* PVA1WRC write clients */ -#define TEGRA194_MEMORY_CLIENT_PVA1WRC 0xd1 -/* RCE read client */ -#define TEGRA194_MEMORY_CLIENT_RCER 0xd2 -/* RCE write client */ -#define TEGRA194_MEMORY_CLIENT_RCEW 0xd3 -/* RCEDMA read client */ -#define TEGRA194_MEMORY_CLIENT_RCEDMAR 0xd4 -/* RCEDMA write client */ -#define TEGRA194_MEMORY_CLIENT_RCEDMAW 0xd5 -#define TEGRA194_MEMORY_CLIENT_NVENC1SRD 0xd6 -#define TEGRA194_MEMORY_CLIENT_NVENC1SWR 0xd7 -/* PCIE0 read clients */ -#define TEGRA194_MEMORY_CLIENT_PCIE0R 0xd8 -/* PCIE0 write clients */ -#define TEGRA194_MEMORY_CLIENT_PCIE0W 0xd9 -/* PCIE1 read clients */ -#define TEGRA194_MEMORY_CLIENT_PCIE1R 0xda -/* PCIE1 write clients */ -#define TEGRA194_MEMORY_CLIENT_PCIE1W 0xdb -/* PCIE2 read clients */ -#define TEGRA194_MEMORY_CLIENT_PCIE2AR 0xdc -/* PCIE2 write clients */ -#define TEGRA194_MEMORY_CLIENT_PCIE2AW 0xdd -/* PCIE3 read clients */ -#define TEGRA194_MEMORY_CLIENT_PCIE3R 0xde -/* PCIE3 write clients */ -#define TEGRA194_MEMORY_CLIENT_PCIE3W 0xdf -/* PCIE4 read clients */ -#define TEGRA194_MEMORY_CLIENT_PCIE4R 0xe0 -/* PCIE4 write clients */ -#define TEGRA194_MEMORY_CLIENT_PCIE4W 0xe1 -/* PCIE5 read clients */ -#define TEGRA194_MEMORY_CLIENT_PCIE5R 0xe2 -/* PCIE5 write clients */ -#define TEGRA194_MEMORY_CLIENT_PCIE5W 0xe3 -/* ISP read client 1 for Crossbar A */ -#define TEGRA194_MEMORY_CLIENT_ISPFALW 0xe4 -#define TEGRA194_MEMORY_CLIENT_NVL3R 0xe5 -#define TEGRA194_MEMORY_CLIENT_NVL3W 0xe6 -#define TEGRA194_MEMORY_CLIENT_NVL4R 0xe7 -#define TEGRA194_MEMORY_CLIENT_NVL4W 0xe8 -/* DLA0ARDA1 read clients */ -#define TEGRA194_MEMORY_CLIENT_DLA0RDA1 0xe9 -/* DLA1ARDA1 read clients */ -#define TEGRA194_MEMORY_CLIENT_DLA1RDA1 0xea -/* PVA0RDA1 read clients */ -#define TEGRA194_MEMORY_CLIENT_PVA0RDA1 0xeb -/* PVA0RDB1 read clients */ -#define TEGRA194_MEMORY_CLIENT_PVA0RDB1 0xec -/* PVA1RDA1 read clients */ -#define TEGRA194_MEMORY_CLIENT_PVA1RDA1 0xed -/* PVA1RDB1 read clients */ -#define TEGRA194_MEMORY_CLIENT_PVA1RDB1 0xee -/* PCIE5r1 read clients */ -#define TEGRA194_MEMORY_CLIENT_PCIE5R1 0xef -#define TEGRA194_MEMORY_CLIENT_NVENCSRD1 0xf0 -#define TEGRA194_MEMORY_CLIENT_NVENC1SRD1 0xf1 -/* ISP read client for Crossbar A */ -#define TEGRA194_MEMORY_CLIENT_ISPRA1 0xf2 -/* PCIE0 read clients */ -#define TEGRA194_MEMORY_CLIENT_PCIE0R1 0xf3 -#define TEGRA194_MEMORY_CLIENT_NVL0RHP 0xf4 -#define TEGRA194_MEMORY_CLIENT_NVL1RHP 0xf5 -#define TEGRA194_MEMORY_CLIENT_NVL2RHP 0xf6 -#define TEGRA194_MEMORY_CLIENT_NVL3RHP 0xf7 -#define TEGRA194_MEMORY_CLIENT_NVL4RHP 0xf8 -#define TEGRA194_MEMORY_CLIENT_NVDEC1SRD 0xf9 -#define TEGRA194_MEMORY_CLIENT_NVDEC1SRD1 0xfa -#define TEGRA194_MEMORY_CLIENT_NVDEC1SWR 0xfb -/* MSS internal memqual MIU5 read clients */ -#define TEGRA194_MEMORY_CLIENT_MIU5R 0xfc -/* MSS internal memqual MIU5 write clients */ -#define TEGRA194_MEMORY_CLIENT_MIU5W 0xfd -/* MSS internal memqual MIU6 read clients */ -#define TEGRA194_MEMORY_CLIENT_MIU6R 0xfe -/* MSS internal memqual MIU6 write clients */ -#define TEGRA194_MEMORY_CLIENT_MIU6W 0xff - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/memory/tegra20-mc.h b/sys/gnu/dts/include/dt-bindings/memory/tegra20-mc.h deleted file mode 100644 index 35e131eee19..00000000000 --- a/sys/gnu/dts/include/dt-bindings/memory/tegra20-mc.h +++ /dev/null @@ -1,21 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef DT_BINDINGS_MEMORY_TEGRA20_MC_H -#define DT_BINDINGS_MEMORY_TEGRA20_MC_H - -#define TEGRA20_MC_RESET_AVPC 0 -#define TEGRA20_MC_RESET_DC 1 -#define TEGRA20_MC_RESET_DCB 2 -#define TEGRA20_MC_RESET_EPP 3 -#define TEGRA20_MC_RESET_2D 4 -#define TEGRA20_MC_RESET_HC 5 -#define TEGRA20_MC_RESET_ISP 6 -#define TEGRA20_MC_RESET_MPCORE 7 -#define TEGRA20_MC_RESET_MPEA 8 -#define TEGRA20_MC_RESET_MPEB 9 -#define TEGRA20_MC_RESET_MPEC 10 -#define TEGRA20_MC_RESET_3D 11 -#define TEGRA20_MC_RESET_PPCS 12 -#define TEGRA20_MC_RESET_VDE 13 -#define TEGRA20_MC_RESET_VI 14 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/memory/tegra210-mc.h b/sys/gnu/dts/include/dt-bindings/memory/tegra210-mc.h deleted file mode 100644 index cacf05617e0..00000000000 --- a/sys/gnu/dts/include/dt-bindings/memory/tegra210-mc.h +++ /dev/null @@ -1,68 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef DT_BINDINGS_MEMORY_TEGRA210_MC_H -#define DT_BINDINGS_MEMORY_TEGRA210_MC_H - -#define TEGRA_SWGROUP_PTC 0 -#define TEGRA_SWGROUP_DC 1 -#define TEGRA_SWGROUP_DCB 2 -#define TEGRA_SWGROUP_AFI 3 -#define TEGRA_SWGROUP_AVPC 4 -#define TEGRA_SWGROUP_HDA 5 -#define TEGRA_SWGROUP_HC 6 -#define TEGRA_SWGROUP_NVENC 7 -#define TEGRA_SWGROUP_PPCS 8 -#define TEGRA_SWGROUP_SATA 9 -#define TEGRA_SWGROUP_MPCORE 10 -#define TEGRA_SWGROUP_ISP2 11 -#define TEGRA_SWGROUP_XUSB_HOST 12 -#define TEGRA_SWGROUP_XUSB_DEV 13 -#define TEGRA_SWGROUP_ISP2B 14 -#define TEGRA_SWGROUP_TSEC 15 -#define TEGRA_SWGROUP_A9AVP 16 -#define TEGRA_SWGROUP_GPU 17 -#define TEGRA_SWGROUP_SDMMC1A 18 -#define TEGRA_SWGROUP_SDMMC2A 19 -#define TEGRA_SWGROUP_SDMMC3A 20 -#define TEGRA_SWGROUP_SDMMC4A 21 -#define TEGRA_SWGROUP_VIC 22 -#define TEGRA_SWGROUP_VI 23 -#define TEGRA_SWGROUP_NVDEC 24 -#define TEGRA_SWGROUP_APE 25 -#define TEGRA_SWGROUP_NVJPG 26 -#define TEGRA_SWGROUP_SE 27 -#define TEGRA_SWGROUP_AXIAP 28 -#define TEGRA_SWGROUP_ETR 29 -#define TEGRA_SWGROUP_TSECB 30 - -#define TEGRA210_MC_RESET_AFI 0 -#define TEGRA210_MC_RESET_AVPC 1 -#define TEGRA210_MC_RESET_DC 2 -#define TEGRA210_MC_RESET_DCB 3 -#define TEGRA210_MC_RESET_HC 4 -#define TEGRA210_MC_RESET_HDA 5 -#define TEGRA210_MC_RESET_ISP2 6 -#define TEGRA210_MC_RESET_MPCORE 7 -#define TEGRA210_MC_RESET_NVENC 8 -#define TEGRA210_MC_RESET_PPCS 9 -#define TEGRA210_MC_RESET_SATA 10 -#define TEGRA210_MC_RESET_VI 11 -#define TEGRA210_MC_RESET_VIC 12 -#define TEGRA210_MC_RESET_XUSB_HOST 13 -#define TEGRA210_MC_RESET_XUSB_DEV 14 -#define TEGRA210_MC_RESET_A9AVP 15 -#define TEGRA210_MC_RESET_TSEC 16 -#define TEGRA210_MC_RESET_SDMMC1 17 -#define TEGRA210_MC_RESET_SDMMC2 18 -#define TEGRA210_MC_RESET_SDMMC3 19 -#define TEGRA210_MC_RESET_SDMMC4 20 -#define TEGRA210_MC_RESET_ISP2B 21 -#define TEGRA210_MC_RESET_GPU 22 -#define TEGRA210_MC_RESET_NVDEC 23 -#define TEGRA210_MC_RESET_APE 24 -#define TEGRA210_MC_RESET_SE 25 -#define TEGRA210_MC_RESET_NVJPG 26 -#define TEGRA210_MC_RESET_AXIAP 27 -#define TEGRA210_MC_RESET_ETR 28 -#define TEGRA210_MC_RESET_TSECB 29 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/memory/tegra30-mc.h b/sys/gnu/dts/include/dt-bindings/memory/tegra30-mc.h deleted file mode 100644 index 169f005fbc7..00000000000 --- a/sys/gnu/dts/include/dt-bindings/memory/tegra30-mc.h +++ /dev/null @@ -1,44 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef DT_BINDINGS_MEMORY_TEGRA30_MC_H -#define DT_BINDINGS_MEMORY_TEGRA30_MC_H - -#define TEGRA_SWGROUP_PTC 0 -#define TEGRA_SWGROUP_DC 1 -#define TEGRA_SWGROUP_DCB 2 -#define TEGRA_SWGROUP_EPP 3 -#define TEGRA_SWGROUP_G2 4 -#define TEGRA_SWGROUP_MPE 5 -#define TEGRA_SWGROUP_VI 6 -#define TEGRA_SWGROUP_AFI 7 -#define TEGRA_SWGROUP_AVPC 8 -#define TEGRA_SWGROUP_NV 9 -#define TEGRA_SWGROUP_NV2 10 -#define TEGRA_SWGROUP_HDA 11 -#define TEGRA_SWGROUP_HC 12 -#define TEGRA_SWGROUP_PPCS 13 -#define TEGRA_SWGROUP_SATA 14 -#define TEGRA_SWGROUP_VDE 15 -#define TEGRA_SWGROUP_MPCORELP 16 -#define TEGRA_SWGROUP_MPCORE 17 -#define TEGRA_SWGROUP_ISP 18 - -#define TEGRA30_MC_RESET_AFI 0 -#define TEGRA30_MC_RESET_AVPC 1 -#define TEGRA30_MC_RESET_DC 2 -#define TEGRA30_MC_RESET_DCB 3 -#define TEGRA30_MC_RESET_EPP 4 -#define TEGRA30_MC_RESET_2D 5 -#define TEGRA30_MC_RESET_HC 6 -#define TEGRA30_MC_RESET_HDA 7 -#define TEGRA30_MC_RESET_ISP 8 -#define TEGRA30_MC_RESET_MPCORE 9 -#define TEGRA30_MC_RESET_MPCORELP 10 -#define TEGRA30_MC_RESET_MPE 11 -#define TEGRA30_MC_RESET_3D 12 -#define TEGRA30_MC_RESET_3D2 13 -#define TEGRA30_MC_RESET_PPCS 14 -#define TEGRA30_MC_RESET_SATA 15 -#define TEGRA30_MC_RESET_VDE 16 -#define TEGRA30_MC_RESET_VI 17 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/mfd/arizona.h b/sys/gnu/dts/include/dt-bindings/mfd/arizona.h deleted file mode 100644 index 1056108c959..00000000000 --- a/sys/gnu/dts/include/dt-bindings/mfd/arizona.h +++ /dev/null @@ -1,115 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Device Tree defines for Arizona devices - * - * Copyright 2015 Cirrus Logic Inc. - * - * Author: Charles Keepax - */ - -#ifndef _DT_BINDINGS_MFD_ARIZONA_H -#define _DT_BINDINGS_MFD_ARIZONA_H - -/* GPIO Function Definitions */ -#define ARIZONA_GP_FN_TXLRCLK 0x00 -#define ARIZONA_GP_FN_GPIO 0x01 -#define ARIZONA_GP_FN_IRQ1 0x02 -#define ARIZONA_GP_FN_IRQ2 0x03 -#define ARIZONA_GP_FN_OPCLK 0x04 -#define ARIZONA_GP_FN_FLL1_OUT 0x05 -#define ARIZONA_GP_FN_FLL2_OUT 0x06 -#define ARIZONA_GP_FN_PWM1 0x08 -#define ARIZONA_GP_FN_PWM2 0x09 -#define ARIZONA_GP_FN_SYSCLK_UNDERCLOCKED 0x0A -#define ARIZONA_GP_FN_ASYNCCLK_UNDERCLOCKED 0x0B -#define ARIZONA_GP_FN_FLL1_LOCK 0x0C -#define ARIZONA_GP_FN_FLL2_LOCK 0x0D -#define ARIZONA_GP_FN_FLL1_CLOCK_OK 0x0F -#define ARIZONA_GP_FN_FLL2_CLOCK_OK 0x10 -#define ARIZONA_GP_FN_HEADPHONE_DET 0x12 -#define ARIZONA_GP_FN_MIC_DET 0x13 -#define ARIZONA_GP_FN_WSEQ_STATUS 0x15 -#define ARIZONA_GP_FN_CIF_ADDRESS_ERROR 0x16 -#define ARIZONA_GP_FN_ASRC1_LOCK 0x1A -#define ARIZONA_GP_FN_ASRC2_LOCK 0x1B -#define ARIZONA_GP_FN_ASRC_CONFIG_ERROR 0x1C -#define ARIZONA_GP_FN_DRC1_SIGNAL_DETECT 0x1D -#define ARIZONA_GP_FN_DRC1_ANTICLIP 0x1E -#define ARIZONA_GP_FN_DRC1_DECAY 0x1F -#define ARIZONA_GP_FN_DRC1_NOISE 0x20 -#define ARIZONA_GP_FN_DRC1_QUICK_RELEASE 0x21 -#define ARIZONA_GP_FN_DRC2_SIGNAL_DETECT 0x22 -#define ARIZONA_GP_FN_DRC2_ANTICLIP 0x23 -#define ARIZONA_GP_FN_DRC2_DECAY 0x24 -#define ARIZONA_GP_FN_DRC2_NOISE 0x25 -#define ARIZONA_GP_FN_DRC2_QUICK_RELEASE 0x26 -#define ARIZONA_GP_FN_MIXER_DROPPED_SAMPLE 0x27 -#define ARIZONA_GP_FN_AIF1_CONFIG_ERROR 0x28 -#define ARIZONA_GP_FN_AIF2_CONFIG_ERROR 0x29 -#define ARIZONA_GP_FN_AIF3_CONFIG_ERROR 0x2A -#define ARIZONA_GP_FN_SPK_TEMP_SHUTDOWN 0x2B -#define ARIZONA_GP_FN_SPK_TEMP_WARNING 0x2C -#define ARIZONA_GP_FN_UNDERCLOCKED 0x2D -#define ARIZONA_GP_FN_OVERCLOCKED 0x2E -#define ARIZONA_GP_FN_DSP_IRQ1 0x35 -#define ARIZONA_GP_FN_DSP_IRQ2 0x36 -#define ARIZONA_GP_FN_ASYNC_OPCLK 0x3D -#define ARIZONA_GP_FN_BOOT_DONE 0x44 -#define ARIZONA_GP_FN_DSP1_RAM_READY 0x45 -#define ARIZONA_GP_FN_SYSCLK_ENA_STATUS 0x4B -#define ARIZONA_GP_FN_ASYNCCLK_ENA_STATUS 0x4C - -/* GPIO Configuration Bits */ -#define ARIZONA_GPN_DIR 0x8000 -#define ARIZONA_GPN_PU 0x4000 -#define ARIZONA_GPN_PD 0x2000 -#define ARIZONA_GPN_LVL 0x0800 -#define ARIZONA_GPN_POL 0x0400 -#define ARIZONA_GPN_OP_CFG 0x0200 -#define ARIZONA_GPN_DB 0x0100 - -/* Provide some defines for the most common configs */ -#define ARIZONA_GP_DEFAULT 0xffffffff -#define ARIZONA_GP_OUTPUT (ARIZONA_GP_FN_GPIO) -#define ARIZONA_GP_INPUT (ARIZONA_GP_FN_GPIO | \ - ARIZONA_GPN_DIR) - -#define ARIZONA_32KZ_MCLK1 1 -#define ARIZONA_32KZ_MCLK2 2 -#define ARIZONA_32KZ_NONE 3 - -#define ARIZONA_DMIC_MICVDD 0 -#define ARIZONA_DMIC_MICBIAS1 1 -#define ARIZONA_DMIC_MICBIAS2 2 -#define ARIZONA_DMIC_MICBIAS3 3 - -#define ARIZONA_INMODE_DIFF 0 -#define ARIZONA_INMODE_SE 1 -#define ARIZONA_INMODE_DMIC 2 - -#define ARIZONA_MICD_TIME_CONTINUOUS 0 -#define ARIZONA_MICD_TIME_250US 1 -#define ARIZONA_MICD_TIME_500US 2 -#define ARIZONA_MICD_TIME_1MS 3 -#define ARIZONA_MICD_TIME_2MS 4 -#define ARIZONA_MICD_TIME_4MS 5 -#define ARIZONA_MICD_TIME_8MS 6 -#define ARIZONA_MICD_TIME_16MS 7 -#define ARIZONA_MICD_TIME_32MS 8 -#define ARIZONA_MICD_TIME_64MS 9 -#define ARIZONA_MICD_TIME_128MS 10 -#define ARIZONA_MICD_TIME_256MS 11 -#define ARIZONA_MICD_TIME_512MS 12 - -#define ARIZONA_ACCDET_MODE_MIC 0 -#define ARIZONA_ACCDET_MODE_HPL 1 -#define ARIZONA_ACCDET_MODE_HPR 2 -#define ARIZONA_ACCDET_MODE_HPM 4 -#define ARIZONA_ACCDET_MODE_ADC 7 - -#define ARIZONA_GPSW_OPEN 0 -#define ARIZONA_GPSW_CLOSED 1 -#define ARIZONA_GPSW_CLAMP_ENABLED 2 -#define ARIZONA_GPSW_CLAMP_DISABLED 3 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/mfd/as3722.h b/sys/gnu/dts/include/dt-bindings/mfd/as3722.h deleted file mode 100644 index 9ef0cba9040..00000000000 --- a/sys/gnu/dts/include/dt-bindings/mfd/as3722.h +++ /dev/null @@ -1,53 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides macros for ams AS3722 device bindings. - * - * Copyright (c) 2013, NVIDIA Corporation. - * - * Author: Laxman Dewangan - * - */ - -#ifndef __DT_BINDINGS_AS3722_H__ -#define __DT_BINDINGS_AS3722_H__ - -/* External control pins */ -#define AS3722_EXT_CONTROL_PIN_ENABLE1 1 -#define AS3722_EXT_CONTROL_PIN_ENABLE2 2 -#define AS3722_EXT_CONTROL_PIN_ENABLE3 3 - -/* Interrupt numbers for AS3722 */ -#define AS3722_IRQ_LID 0 -#define AS3722_IRQ_ACOK 1 -#define AS3722_IRQ_ENABLE1 2 -#define AS3722_IRQ_OCCUR_ALARM_SD0 3 -#define AS3722_IRQ_ONKEY_LONG_PRESS 4 -#define AS3722_IRQ_ONKEY 5 -#define AS3722_IRQ_OVTMP 6 -#define AS3722_IRQ_LOWBAT 7 -#define AS3722_IRQ_SD0_LV 8 -#define AS3722_IRQ_SD1_LV 9 -#define AS3722_IRQ_SD2_LV 10 -#define AS3722_IRQ_PWM1_OV_PROT 11 -#define AS3722_IRQ_PWM2_OV_PROT 12 -#define AS3722_IRQ_ENABLE2 13 -#define AS3722_IRQ_SD6_LV 14 -#define AS3722_IRQ_RTC_REP 15 -#define AS3722_IRQ_RTC_ALARM 16 -#define AS3722_IRQ_GPIO1 17 -#define AS3722_IRQ_GPIO2 18 -#define AS3722_IRQ_GPIO3 19 -#define AS3722_IRQ_GPIO4 20 -#define AS3722_IRQ_GPIO5 21 -#define AS3722_IRQ_WATCHDOG 22 -#define AS3722_IRQ_ENABLE3 23 -#define AS3722_IRQ_TEMP_SD0_SHUTDOWN 24 -#define AS3722_IRQ_TEMP_SD1_SHUTDOWN 25 -#define AS3722_IRQ_TEMP_SD2_SHUTDOWN 26 -#define AS3722_IRQ_TEMP_SD0_ALARM 27 -#define AS3722_IRQ_TEMP_SD1_ALARM 28 -#define AS3722_IRQ_TEMP_SD6_ALARM 29 -#define AS3722_IRQ_OCCUR_ALARM_SD6 30 -#define AS3722_IRQ_ADC 31 - -#endif /* __DT_BINDINGS_AS3722_H__ */ diff --git a/sys/gnu/dts/include/dt-bindings/mfd/at91-usart.h b/sys/gnu/dts/include/dt-bindings/mfd/at91-usart.h deleted file mode 100644 index 2de5bc312e1..00000000000 --- a/sys/gnu/dts/include/dt-bindings/mfd/at91-usart.h +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides macros for AT91 USART DT bindings. - * - * Copyright (C) 2018 Microchip Technology - * - * Author: Radu Pirea - * - */ - -#ifndef __DT_BINDINGS_AT91_USART_H__ -#define __DT_BINDINGS_AT91_USART_H__ - -#define AT91_USART_MODE_SERIAL 0 -#define AT91_USART_MODE_SPI 1 - -#endif /* __DT_BINDINGS_AT91_USART_H__ */ diff --git a/sys/gnu/dts/include/dt-bindings/mfd/atmel-flexcom.h b/sys/gnu/dts/include/dt-bindings/mfd/atmel-flexcom.h deleted file mode 100644 index 4e2fc323639..00000000000 --- a/sys/gnu/dts/include/dt-bindings/mfd/atmel-flexcom.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * This header provides macros for Atmel Flexcom DT bindings. - * - * Copyright (C) 2015 Cyrille Pitchen - */ - -#ifndef __DT_BINDINGS_ATMEL_FLEXCOM_H__ -#define __DT_BINDINGS_ATMEL_FLEXCOM_H__ - -#define ATMEL_FLEXCOM_MODE_USART 1 -#define ATMEL_FLEXCOM_MODE_SPI 2 -#define ATMEL_FLEXCOM_MODE_TWI 3 - -#endif /* __DT_BINDINGS_ATMEL_FLEXCOM_H__ */ diff --git a/sys/gnu/dts/include/dt-bindings/mfd/dbx500-prcmu.h b/sys/gnu/dts/include/dt-bindings/mfd/dbx500-prcmu.h deleted file mode 100644 index 0404bcc47dd..00000000000 --- a/sys/gnu/dts/include/dt-bindings/mfd/dbx500-prcmu.h +++ /dev/null @@ -1,84 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides constants for the PRCMU bindings. - * - */ - -#ifndef _DT_BINDINGS_MFD_PRCMU_H -#define _DT_BINDINGS_MFD_PRCMU_H - -/* - * Clock identifiers. - */ -#define ARMCLK 0 -#define PRCMU_ACLK 1 -#define PRCMU_SVAMMCSPCLK 2 -#define PRCMU_SDMMCHCLK 2 /* DBx540 only. */ -#define PRCMU_SIACLK 3 -#define PRCMU_SIAMMDSPCLK 3 /* DBx540 only. */ -#define PRCMU_SGACLK 4 -#define PRCMU_UARTCLK 5 -#define PRCMU_MSP02CLK 6 -#define PRCMU_MSP1CLK 7 -#define PRCMU_I2CCLK 8 -#define PRCMU_SDMMCCLK 9 -#define PRCMU_SLIMCLK 10 -#define PRCMU_CAMCLK 10 /* DBx540 only. */ -#define PRCMU_PER1CLK 11 -#define PRCMU_PER2CLK 12 -#define PRCMU_PER3CLK 13 -#define PRCMU_PER5CLK 14 -#define PRCMU_PER6CLK 15 -#define PRCMU_PER7CLK 16 -#define PRCMU_LCDCLK 17 -#define PRCMU_BMLCLK 18 -#define PRCMU_HSITXCLK 19 -#define PRCMU_HSIRXCLK 20 -#define PRCMU_HDMICLK 21 -#define PRCMU_APEATCLK 22 -#define PRCMU_APETRACECLK 23 -#define PRCMU_MCDECLK 24 -#define PRCMU_IPI2CCLK 25 -#define PRCMU_DSIALTCLK 26 -#define PRCMU_DMACLK 27 -#define PRCMU_B2R2CLK 28 -#define PRCMU_TVCLK 29 -#define SPARE_UNIPROCLK 30 -#define PRCMU_SSPCLK 31 -#define PRCMU_RNGCLK 32 -#define PRCMU_UICCCLK 33 -#define PRCMU_G1CLK 34 /* DBx540 only. */ -#define PRCMU_HVACLK 35 /* DBx540 only. */ -#define PRCMU_SPARE1CLK 36 -#define PRCMU_SPARE2CLK 37 - -#define PRCMU_NUM_REG_CLOCKS 38 - -#define PRCMU_RTCCLK PRCMU_NUM_REG_CLOCKS -#define PRCMU_SYSCLK 39 -#define PRCMU_CDCLK 40 -#define PRCMU_TIMCLK 41 -#define PRCMU_PLLSOC0 42 -#define PRCMU_PLLSOC1 43 -#define PRCMU_ARMSS 44 -#define PRCMU_PLLDDR 45 - -/* DSI Clocks */ -#define PRCMU_PLLDSI 46 -#define PRCMU_DSI0CLK 47 -#define PRCMU_DSI1CLK 48 -#define PRCMU_DSI0ESCCLK 49 -#define PRCMU_DSI1ESCCLK 50 -#define PRCMU_DSI2ESCCLK 51 - -/* LCD DSI PLL - Ux540 only */ -#define PRCMU_PLLDSI_LCD 52 -#define PRCMU_DSI0CLK_LCD 53 -#define PRCMU_DSI1CLK_LCD 54 -#define PRCMU_DSI0ESCCLK_LCD 55 -#define PRCMU_DSI1ESCCLK_LCD 56 -#define PRCMU_DSI2ESCCLK_LCD 57 - -#define PRCMU_NUM_CLKS 58 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/mfd/max77620.h b/sys/gnu/dts/include/dt-bindings/mfd/max77620.h deleted file mode 100644 index 1e19c5f908d..00000000000 --- a/sys/gnu/dts/include/dt-bindings/mfd/max77620.h +++ /dev/null @@ -1,40 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides macros for MAXIM MAX77620 device bindings. - * - * Copyright (c) 2016, NVIDIA Corporation. - * Author: Laxman Dewangan - */ - -#ifndef _DT_BINDINGS_MFD_MAX77620_H -#define _DT_BINDINGS_MFD_MAX77620_H - -/* MAX77620 interrupts */ -#define MAX77620_IRQ_TOP_GLBL 0 /* Low-Battery */ -#define MAX77620_IRQ_TOP_SD 1 /* SD power fail */ -#define MAX77620_IRQ_TOP_LDO 2 /* LDO power fail */ -#define MAX77620_IRQ_TOP_GPIO 3 /* GPIO internal int to MAX77620 */ -#define MAX77620_IRQ_TOP_RTC 4 /* RTC */ -#define MAX77620_IRQ_TOP_32K 5 /* 32kHz oscillator */ -#define MAX77620_IRQ_TOP_ONOFF 6 /* ON/OFF oscillator */ -#define MAX77620_IRQ_LBT_MBATLOW 7 /* Thermal alarm status, > 120C */ -#define MAX77620_IRQ_LBT_TJALRM1 8 /* Thermal alarm status, > 120C */ -#define MAX77620_IRQ_LBT_TJALRM2 9 /* Thermal alarm status, > 140C */ - -/* FPS event source */ -#define MAX77620_FPS_EVENT_SRC_EN0 0 -#define MAX77620_FPS_EVENT_SRC_EN1 1 -#define MAX77620_FPS_EVENT_SRC_SW 2 - -/* Device state when FPS event LOW */ -#define MAX77620_FPS_INACTIVE_STATE_SLEEP 0 -#define MAX77620_FPS_INACTIVE_STATE_LOW_POWER 1 - -/* FPS source */ -#define MAX77620_FPS_SRC_0 0 -#define MAX77620_FPS_SRC_1 1 -#define MAX77620_FPS_SRC_2 2 -#define MAX77620_FPS_SRC_NONE 3 -#define MAX77620_FPS_SRC_DEF 4 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/mfd/palmas.h b/sys/gnu/dts/include/dt-bindings/mfd/palmas.h deleted file mode 100644 index c4f1d57ff4f..00000000000 --- a/sys/gnu/dts/include/dt-bindings/mfd/palmas.h +++ /dev/null @@ -1,19 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides macros for Palmas device bindings. - * - * Copyright (c) 2013, NVIDIA Corporation. - * - * Author: Laxman Dewangan - * - */ - -#ifndef __DT_BINDINGS_PALMAS_H -#define __DT_BINDINGS_PALMAS_H - -/* External control pins */ -#define PALMAS_EXT_CONTROL_PIN_ENABLE1 1 -#define PALMAS_EXT_CONTROL_PIN_ENABLE2 2 -#define PALMAS_EXT_CONTROL_PIN_NSLEEP 3 - -#endif /* __DT_BINDINGS_PALMAS_H */ diff --git a/sys/gnu/dts/include/dt-bindings/mfd/qcom-rpm.h b/sys/gnu/dts/include/dt-bindings/mfd/qcom-rpm.h deleted file mode 100644 index c9204c4df52..00000000000 --- a/sys/gnu/dts/include/dt-bindings/mfd/qcom-rpm.h +++ /dev/null @@ -1,183 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides constants for the Qualcomm RPM bindings. - */ - -#ifndef _DT_BINDINGS_MFD_QCOM_RPM_H -#define _DT_BINDINGS_MFD_QCOM_RPM_H - -/* - * Constants use to identify individual resources in the RPM. - */ -#define QCOM_RPM_APPS_FABRIC_ARB 1 -#define QCOM_RPM_APPS_FABRIC_CLK 2 -#define QCOM_RPM_APPS_FABRIC_HALT 3 -#define QCOM_RPM_APPS_FABRIC_IOCTL 4 -#define QCOM_RPM_APPS_FABRIC_MODE 5 -#define QCOM_RPM_APPS_L2_CACHE_CTL 6 -#define QCOM_RPM_CFPB_CLK 7 -#define QCOM_RPM_CXO_BUFFERS 8 -#define QCOM_RPM_CXO_CLK 9 -#define QCOM_RPM_DAYTONA_FABRIC_CLK 10 -#define QCOM_RPM_DDR_DMM 11 -#define QCOM_RPM_EBI1_CLK 12 -#define QCOM_RPM_HDMI_SWITCH 13 -#define QCOM_RPM_MMFPB_CLK 14 -#define QCOM_RPM_MM_FABRIC_ARB 15 -#define QCOM_RPM_MM_FABRIC_CLK 16 -#define QCOM_RPM_MM_FABRIC_HALT 17 -#define QCOM_RPM_MM_FABRIC_IOCTL 18 -#define QCOM_RPM_MM_FABRIC_MODE 19 -#define QCOM_RPM_PLL_4 20 -#define QCOM_RPM_PM8058_LDO0 21 -#define QCOM_RPM_PM8058_LDO1 22 -#define QCOM_RPM_PM8058_LDO2 23 -#define QCOM_RPM_PM8058_LDO3 24 -#define QCOM_RPM_PM8058_LDO4 25 -#define QCOM_RPM_PM8058_LDO5 26 -#define QCOM_RPM_PM8058_LDO6 27 -#define QCOM_RPM_PM8058_LDO7 28 -#define QCOM_RPM_PM8058_LDO8 29 -#define QCOM_RPM_PM8058_LDO9 30 -#define QCOM_RPM_PM8058_LDO10 31 -#define QCOM_RPM_PM8058_LDO11 32 -#define QCOM_RPM_PM8058_LDO12 33 -#define QCOM_RPM_PM8058_LDO13 34 -#define QCOM_RPM_PM8058_LDO14 35 -#define QCOM_RPM_PM8058_LDO15 36 -#define QCOM_RPM_PM8058_LDO16 37 -#define QCOM_RPM_PM8058_LDO17 38 -#define QCOM_RPM_PM8058_LDO18 39 -#define QCOM_RPM_PM8058_LDO19 40 -#define QCOM_RPM_PM8058_LDO20 41 -#define QCOM_RPM_PM8058_LDO21 42 -#define QCOM_RPM_PM8058_LDO22 43 -#define QCOM_RPM_PM8058_LDO23 44 -#define QCOM_RPM_PM8058_LDO24 45 -#define QCOM_RPM_PM8058_LDO25 46 -#define QCOM_RPM_PM8058_LVS0 47 -#define QCOM_RPM_PM8058_LVS1 48 -#define QCOM_RPM_PM8058_NCP 49 -#define QCOM_RPM_PM8058_SMPS0 50 -#define QCOM_RPM_PM8058_SMPS1 51 -#define QCOM_RPM_PM8058_SMPS2 52 -#define QCOM_RPM_PM8058_SMPS3 53 -#define QCOM_RPM_PM8058_SMPS4 54 -#define QCOM_RPM_PM8821_LDO1 55 -#define QCOM_RPM_PM8821_SMPS1 56 -#define QCOM_RPM_PM8821_SMPS2 57 -#define QCOM_RPM_PM8901_LDO0 58 -#define QCOM_RPM_PM8901_LDO1 59 -#define QCOM_RPM_PM8901_LDO2 60 -#define QCOM_RPM_PM8901_LDO3 61 -#define QCOM_RPM_PM8901_LDO4 62 -#define QCOM_RPM_PM8901_LDO5 63 -#define QCOM_RPM_PM8901_LDO6 64 -#define QCOM_RPM_PM8901_LVS0 65 -#define QCOM_RPM_PM8901_LVS1 66 -#define QCOM_RPM_PM8901_LVS2 67 -#define QCOM_RPM_PM8901_LVS3 68 -#define QCOM_RPM_PM8901_MVS 69 -#define QCOM_RPM_PM8901_SMPS0 70 -#define QCOM_RPM_PM8901_SMPS1 71 -#define QCOM_RPM_PM8901_SMPS2 72 -#define QCOM_RPM_PM8901_SMPS3 73 -#define QCOM_RPM_PM8901_SMPS4 74 -#define QCOM_RPM_PM8921_CLK1 75 -#define QCOM_RPM_PM8921_CLK2 76 -#define QCOM_RPM_PM8921_LDO1 77 -#define QCOM_RPM_PM8921_LDO2 78 -#define QCOM_RPM_PM8921_LDO3 79 -#define QCOM_RPM_PM8921_LDO4 80 -#define QCOM_RPM_PM8921_LDO5 81 -#define QCOM_RPM_PM8921_LDO6 82 -#define QCOM_RPM_PM8921_LDO7 83 -#define QCOM_RPM_PM8921_LDO8 84 -#define QCOM_RPM_PM8921_LDO9 85 -#define QCOM_RPM_PM8921_LDO10 86 -#define QCOM_RPM_PM8921_LDO11 87 -#define QCOM_RPM_PM8921_LDO12 88 -#define QCOM_RPM_PM8921_LDO13 89 -#define QCOM_RPM_PM8921_LDO14 90 -#define QCOM_RPM_PM8921_LDO15 91 -#define QCOM_RPM_PM8921_LDO16 92 -#define QCOM_RPM_PM8921_LDO17 93 -#define QCOM_RPM_PM8921_LDO18 94 -#define QCOM_RPM_PM8921_LDO19 95 -#define QCOM_RPM_PM8921_LDO20 96 -#define QCOM_RPM_PM8921_LDO21 97 -#define QCOM_RPM_PM8921_LDO22 98 -#define QCOM_RPM_PM8921_LDO23 99 -#define QCOM_RPM_PM8921_LDO24 100 -#define QCOM_RPM_PM8921_LDO25 101 -#define QCOM_RPM_PM8921_LDO26 102 -#define QCOM_RPM_PM8921_LDO27 103 -#define QCOM_RPM_PM8921_LDO28 104 -#define QCOM_RPM_PM8921_LDO29 105 -#define QCOM_RPM_PM8921_LVS1 106 -#define QCOM_RPM_PM8921_LVS2 107 -#define QCOM_RPM_PM8921_LVS3 108 -#define QCOM_RPM_PM8921_LVS4 109 -#define QCOM_RPM_PM8921_LVS5 110 -#define QCOM_RPM_PM8921_LVS6 111 -#define QCOM_RPM_PM8921_LVS7 112 -#define QCOM_RPM_PM8921_MVS 113 -#define QCOM_RPM_PM8921_NCP 114 -#define QCOM_RPM_PM8921_SMPS1 115 -#define QCOM_RPM_PM8921_SMPS2 116 -#define QCOM_RPM_PM8921_SMPS3 117 -#define QCOM_RPM_PM8921_SMPS4 118 -#define QCOM_RPM_PM8921_SMPS5 119 -#define QCOM_RPM_PM8921_SMPS6 120 -#define QCOM_RPM_PM8921_SMPS7 121 -#define QCOM_RPM_PM8921_SMPS8 122 -#define QCOM_RPM_PXO_CLK 123 -#define QCOM_RPM_QDSS_CLK 124 -#define QCOM_RPM_SFPB_CLK 125 -#define QCOM_RPM_SMI_CLK 126 -#define QCOM_RPM_SYS_FABRIC_ARB 127 -#define QCOM_RPM_SYS_FABRIC_CLK 128 -#define QCOM_RPM_SYS_FABRIC_HALT 129 -#define QCOM_RPM_SYS_FABRIC_IOCTL 130 -#define QCOM_RPM_SYS_FABRIC_MODE 131 -#define QCOM_RPM_USB_OTG_SWITCH 132 -#define QCOM_RPM_VDDMIN_GPIO 133 -#define QCOM_RPM_NSS_FABRIC_0_CLK 134 -#define QCOM_RPM_NSS_FABRIC_1_CLK 135 -#define QCOM_RPM_SMB208_S1a 136 -#define QCOM_RPM_SMB208_S1b 137 -#define QCOM_RPM_SMB208_S2a 138 -#define QCOM_RPM_SMB208_S2b 139 -#define QCOM_RPM_PM8018_SMPS1 140 -#define QCOM_RPM_PM8018_SMPS2 141 -#define QCOM_RPM_PM8018_SMPS3 142 -#define QCOM_RPM_PM8018_SMPS4 143 -#define QCOM_RPM_PM8018_SMPS5 144 -#define QCOM_RPM_PM8018_LDO1 145 -#define QCOM_RPM_PM8018_LDO2 146 -#define QCOM_RPM_PM8018_LDO3 147 -#define QCOM_RPM_PM8018_LDO4 148 -#define QCOM_RPM_PM8018_LDO5 149 -#define QCOM_RPM_PM8018_LDO6 150 -#define QCOM_RPM_PM8018_LDO7 151 -#define QCOM_RPM_PM8018_LDO8 152 -#define QCOM_RPM_PM8018_LDO9 153 -#define QCOM_RPM_PM8018_LDO10 154 -#define QCOM_RPM_PM8018_LDO11 155 -#define QCOM_RPM_PM8018_LDO12 156 -#define QCOM_RPM_PM8018_LDO13 157 -#define QCOM_RPM_PM8018_LDO14 158 -#define QCOM_RPM_PM8018_LVS1 159 -#define QCOM_RPM_PM8018_NCP 160 -#define QCOM_RPM_VOLTAGE_CORNER 161 - -/* - * Constants used to select force mode for regulators. - */ -#define QCOM_RPM_FORCE_MODE_NONE 0 -#define QCOM_RPM_FORCE_MODE_LPM 1 -#define QCOM_RPM_FORCE_MODE_HPM 2 -#define QCOM_RPM_FORCE_MODE_AUTO 3 -#define QCOM_RPM_FORCE_MODE_BYPASS 4 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/mfd/st,stpmic1.h b/sys/gnu/dts/include/dt-bindings/mfd/st,stpmic1.h deleted file mode 100644 index 321cd08797d..00000000000 --- a/sys/gnu/dts/include/dt-bindings/mfd/st,stpmic1.h +++ /dev/null @@ -1,50 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) STMicroelectronics 2018 - All Rights Reserved - * Author: Philippe Peurichard , - * Pascal Paillet for STMicroelectronics. - */ - -#ifndef __DT_BINDINGS_STPMIC1_H__ -#define __DT_BINDINGS_STPMIC1_H__ - -/* IRQ definitions */ -#define IT_PONKEY_F 0 -#define IT_PONKEY_R 1 -#define IT_WAKEUP_F 2 -#define IT_WAKEUP_R 3 -#define IT_VBUS_OTG_F 4 -#define IT_VBUS_OTG_R 5 -#define IT_SWOUT_F 6 -#define IT_SWOUT_R 7 - -#define IT_CURLIM_BUCK1 8 -#define IT_CURLIM_BUCK2 9 -#define IT_CURLIM_BUCK3 10 -#define IT_CURLIM_BUCK4 11 -#define IT_OCP_OTG 12 -#define IT_OCP_SWOUT 13 -#define IT_OCP_BOOST 14 -#define IT_OVP_BOOST 15 - -#define IT_CURLIM_LDO1 16 -#define IT_CURLIM_LDO2 17 -#define IT_CURLIM_LDO3 18 -#define IT_CURLIM_LDO4 19 -#define IT_CURLIM_LDO5 20 -#define IT_CURLIM_LDO6 21 -#define IT_SHORT_SWOTG 22 -#define IT_SHORT_SWOUT 23 - -#define IT_TWARN_F 24 -#define IT_TWARN_R 25 -#define IT_VINLOW_F 26 -#define IT_VINLOW_R 27 -#define IT_SWIN_F 30 -#define IT_SWIN_R 31 - -/* BUCK MODES definitions */ -#define STPMIC1_BUCK_MODE_NORMAL 0 -#define STPMIC1_BUCK_MODE_LP 2 - -#endif /* __DT_BINDINGS_STPMIC1_H__ */ diff --git a/sys/gnu/dts/include/dt-bindings/mfd/st-lpc.h b/sys/gnu/dts/include/dt-bindings/mfd/st-lpc.h deleted file mode 100644 index 88a7f56843b..00000000000 --- a/sys/gnu/dts/include/dt-bindings/mfd/st-lpc.h +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides shared DT/Driver defines for ST's LPC device - * - * Copyright (C) 2014 STMicroelectronics -- All Rights Reserved - * - * Author: Lee Jones for STMicroelectronics - */ - -#ifndef __DT_BINDINGS_ST_LPC_H__ -#define __DT_BINDINGS_ST_LPC_H__ - -#define ST_LPC_MODE_RTC 0 -#define ST_LPC_MODE_WDT 1 -#define ST_LPC_MODE_CLKSRC 2 - -#endif /* __DT_BINDINGS_ST_LPC_H__ */ diff --git a/sys/gnu/dts/include/dt-bindings/mfd/stm32f4-rcc.h b/sys/gnu/dts/include/dt-bindings/mfd/stm32f4-rcc.h deleted file mode 100644 index 309e8c79f27..00000000000 --- a/sys/gnu/dts/include/dt-bindings/mfd/stm32f4-rcc.h +++ /dev/null @@ -1,109 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides constants for the STM32F4 RCC IP - */ - -#ifndef _DT_BINDINGS_MFD_STM32F4_RCC_H -#define _DT_BINDINGS_MFD_STM32F4_RCC_H - -/* AHB1 */ -#define STM32F4_RCC_AHB1_GPIOA 0 -#define STM32F4_RCC_AHB1_GPIOB 1 -#define STM32F4_RCC_AHB1_GPIOC 2 -#define STM32F4_RCC_AHB1_GPIOD 3 -#define STM32F4_RCC_AHB1_GPIOE 4 -#define STM32F4_RCC_AHB1_GPIOF 5 -#define STM32F4_RCC_AHB1_GPIOG 6 -#define STM32F4_RCC_AHB1_GPIOH 7 -#define STM32F4_RCC_AHB1_GPIOI 8 -#define STM32F4_RCC_AHB1_GPIOJ 9 -#define STM32F4_RCC_AHB1_GPIOK 10 -#define STM32F4_RCC_AHB1_CRC 12 -#define STM32F4_RCC_AHB1_BKPSRAM 18 -#define STM32F4_RCC_AHB1_CCMDATARAM 20 -#define STM32F4_RCC_AHB1_DMA1 21 -#define STM32F4_RCC_AHB1_DMA2 22 -#define STM32F4_RCC_AHB1_DMA2D 23 -#define STM32F4_RCC_AHB1_ETHMAC 25 -#define STM32F4_RCC_AHB1_ETHMACTX 26 -#define STM32F4_RCC_AHB1_ETHMACRX 27 -#define STM32F4_RCC_AHB1_ETHMACPTP 28 -#define STM32F4_RCC_AHB1_OTGHS 29 -#define STM32F4_RCC_AHB1_OTGHSULPI 30 - -#define STM32F4_AHB1_RESET(bit) (STM32F4_RCC_AHB1_##bit + (0x10 * 8)) -#define STM32F4_AHB1_CLOCK(bit) (STM32F4_RCC_AHB1_##bit) - - -/* AHB2 */ -#define STM32F4_RCC_AHB2_DCMI 0 -#define STM32F4_RCC_AHB2_CRYP 4 -#define STM32F4_RCC_AHB2_HASH 5 -#define STM32F4_RCC_AHB2_RNG 6 -#define STM32F4_RCC_AHB2_OTGFS 7 - -#define STM32F4_AHB2_RESET(bit) (STM32F4_RCC_AHB2_##bit + (0x14 * 8)) -#define STM32F4_AHB2_CLOCK(bit) (STM32F4_RCC_AHB2_##bit + 0x20) - -/* AHB3 */ -#define STM32F4_RCC_AHB3_FMC 0 -#define STM32F4_RCC_AHB3_QSPI 1 - -#define STM32F4_AHB3_RESET(bit) (STM32F4_RCC_AHB3_##bit + (0x18 * 8)) -#define STM32F4_AHB3_CLOCK(bit) (STM32F4_RCC_AHB3_##bit + 0x40) - -/* APB1 */ -#define STM32F4_RCC_APB1_TIM2 0 -#define STM32F4_RCC_APB1_TIM3 1 -#define STM32F4_RCC_APB1_TIM4 2 -#define STM32F4_RCC_APB1_TIM5 3 -#define STM32F4_RCC_APB1_TIM6 4 -#define STM32F4_RCC_APB1_TIM7 5 -#define STM32F4_RCC_APB1_TIM12 6 -#define STM32F4_RCC_APB1_TIM13 7 -#define STM32F4_RCC_APB1_TIM14 8 -#define STM32F4_RCC_APB1_WWDG 11 -#define STM32F4_RCC_APB1_SPI2 14 -#define STM32F4_RCC_APB1_SPI3 15 -#define STM32F4_RCC_APB1_UART2 17 -#define STM32F4_RCC_APB1_UART3 18 -#define STM32F4_RCC_APB1_UART4 19 -#define STM32F4_RCC_APB1_UART5 20 -#define STM32F4_RCC_APB1_I2C1 21 -#define STM32F4_RCC_APB1_I2C2 22 -#define STM32F4_RCC_APB1_I2C3 23 -#define STM32F4_RCC_APB1_CAN1 25 -#define STM32F4_RCC_APB1_CAN2 26 -#define STM32F4_RCC_APB1_PWR 28 -#define STM32F4_RCC_APB1_DAC 29 -#define STM32F4_RCC_APB1_UART7 30 -#define STM32F4_RCC_APB1_UART8 31 - -#define STM32F4_APB1_RESET(bit) (STM32F4_RCC_APB1_##bit + (0x20 * 8)) -#define STM32F4_APB1_CLOCK(bit) (STM32F4_RCC_APB1_##bit + 0x80) - -/* APB2 */ -#define STM32F4_RCC_APB2_TIM1 0 -#define STM32F4_RCC_APB2_TIM8 1 -#define STM32F4_RCC_APB2_USART1 4 -#define STM32F4_RCC_APB2_USART6 5 -#define STM32F4_RCC_APB2_ADC1 8 -#define STM32F4_RCC_APB2_ADC2 9 -#define STM32F4_RCC_APB2_ADC3 10 -#define STM32F4_RCC_APB2_SDIO 11 -#define STM32F4_RCC_APB2_SPI1 12 -#define STM32F4_RCC_APB2_SPI4 13 -#define STM32F4_RCC_APB2_SYSCFG 14 -#define STM32F4_RCC_APB2_TIM9 16 -#define STM32F4_RCC_APB2_TIM10 17 -#define STM32F4_RCC_APB2_TIM11 18 -#define STM32F4_RCC_APB2_SPI5 20 -#define STM32F4_RCC_APB2_SPI6 21 -#define STM32F4_RCC_APB2_SAI1 22 -#define STM32F4_RCC_APB2_LTDC 26 -#define STM32F4_RCC_APB2_DSI 27 - -#define STM32F4_APB2_RESET(bit) (STM32F4_RCC_APB2_##bit + (0x24 * 8)) -#define STM32F4_APB2_CLOCK(bit) (STM32F4_RCC_APB2_##bit + 0xA0) - -#endif /* _DT_BINDINGS_MFD_STM32F4_RCC_H */ diff --git a/sys/gnu/dts/include/dt-bindings/mfd/stm32f7-rcc.h b/sys/gnu/dts/include/dt-bindings/mfd/stm32f7-rcc.h deleted file mode 100644 index a90f3613c58..00000000000 --- a/sys/gnu/dts/include/dt-bindings/mfd/stm32f7-rcc.h +++ /dev/null @@ -1,114 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides constants for the STM32F7 RCC IP - */ - -#ifndef _DT_BINDINGS_MFD_STM32F7_RCC_H -#define _DT_BINDINGS_MFD_STM32F7_RCC_H - -/* AHB1 */ -#define STM32F7_RCC_AHB1_GPIOA 0 -#define STM32F7_RCC_AHB1_GPIOB 1 -#define STM32F7_RCC_AHB1_GPIOC 2 -#define STM32F7_RCC_AHB1_GPIOD 3 -#define STM32F7_RCC_AHB1_GPIOE 4 -#define STM32F7_RCC_AHB1_GPIOF 5 -#define STM32F7_RCC_AHB1_GPIOG 6 -#define STM32F7_RCC_AHB1_GPIOH 7 -#define STM32F7_RCC_AHB1_GPIOI 8 -#define STM32F7_RCC_AHB1_GPIOJ 9 -#define STM32F7_RCC_AHB1_GPIOK 10 -#define STM32F7_RCC_AHB1_CRC 12 -#define STM32F7_RCC_AHB1_BKPSRAM 18 -#define STM32F7_RCC_AHB1_DTCMRAM 20 -#define STM32F7_RCC_AHB1_DMA1 21 -#define STM32F7_RCC_AHB1_DMA2 22 -#define STM32F7_RCC_AHB1_DMA2D 23 -#define STM32F7_RCC_AHB1_ETHMAC 25 -#define STM32F7_RCC_AHB1_ETHMACTX 26 -#define STM32F7_RCC_AHB1_ETHMACRX 27 -#define STM32FF_RCC_AHB1_ETHMACPTP 28 -#define STM32F7_RCC_AHB1_OTGHS 29 -#define STM32F7_RCC_AHB1_OTGHSULPI 30 - -#define STM32F7_AHB1_RESET(bit) (STM32F7_RCC_AHB1_##bit + (0x10 * 8)) -#define STM32F7_AHB1_CLOCK(bit) (STM32F7_RCC_AHB1_##bit) - - -/* AHB2 */ -#define STM32F7_RCC_AHB2_DCMI 0 -#define STM32F7_RCC_AHB2_CRYP 4 -#define STM32F7_RCC_AHB2_HASH 5 -#define STM32F7_RCC_AHB2_RNG 6 -#define STM32F7_RCC_AHB2_OTGFS 7 - -#define STM32F7_AHB2_RESET(bit) (STM32F7_RCC_AHB2_##bit + (0x14 * 8)) -#define STM32F7_AHB2_CLOCK(bit) (STM32F7_RCC_AHB2_##bit + 0x20) - -/* AHB3 */ -#define STM32F7_RCC_AHB3_FMC 0 -#define STM32F7_RCC_AHB3_QSPI 1 - -#define STM32F7_AHB3_RESET(bit) (STM32F7_RCC_AHB3_##bit + (0x18 * 8)) -#define STM32F7_AHB3_CLOCK(bit) (STM32F7_RCC_AHB3_##bit + 0x40) - -/* APB1 */ -#define STM32F7_RCC_APB1_TIM2 0 -#define STM32F7_RCC_APB1_TIM3 1 -#define STM32F7_RCC_APB1_TIM4 2 -#define STM32F7_RCC_APB1_TIM5 3 -#define STM32F7_RCC_APB1_TIM6 4 -#define STM32F7_RCC_APB1_TIM7 5 -#define STM32F7_RCC_APB1_TIM12 6 -#define STM32F7_RCC_APB1_TIM13 7 -#define STM32F7_RCC_APB1_TIM14 8 -#define STM32F7_RCC_APB1_LPTIM1 9 -#define STM32F7_RCC_APB1_WWDG 11 -#define STM32F7_RCC_APB1_SPI2 14 -#define STM32F7_RCC_APB1_SPI3 15 -#define STM32F7_RCC_APB1_SPDIFRX 16 -#define STM32F7_RCC_APB1_UART2 17 -#define STM32F7_RCC_APB1_UART3 18 -#define STM32F7_RCC_APB1_UART4 19 -#define STM32F7_RCC_APB1_UART5 20 -#define STM32F7_RCC_APB1_I2C1 21 -#define STM32F7_RCC_APB1_I2C2 22 -#define STM32F7_RCC_APB1_I2C3 23 -#define STM32F7_RCC_APB1_I2C4 24 -#define STM32F7_RCC_APB1_CAN1 25 -#define STM32F7_RCC_APB1_CAN2 26 -#define STM32F7_RCC_APB1_CEC 27 -#define STM32F7_RCC_APB1_PWR 28 -#define STM32F7_RCC_APB1_DAC 29 -#define STM32F7_RCC_APB1_UART7 30 -#define STM32F7_RCC_APB1_UART8 31 - -#define STM32F7_APB1_RESET(bit) (STM32F7_RCC_APB1_##bit + (0x20 * 8)) -#define STM32F7_APB1_CLOCK(bit) (STM32F7_RCC_APB1_##bit + 0x80) - -/* APB2 */ -#define STM32F7_RCC_APB2_TIM1 0 -#define STM32F7_RCC_APB2_TIM8 1 -#define STM32F7_RCC_APB2_USART1 4 -#define STM32F7_RCC_APB2_USART6 5 -#define STM32F7_RCC_APB2_SDMMC2 7 -#define STM32F7_RCC_APB2_ADC1 8 -#define STM32F7_RCC_APB2_ADC2 9 -#define STM32F7_RCC_APB2_ADC3 10 -#define STM32F7_RCC_APB2_SDMMC1 11 -#define STM32F7_RCC_APB2_SPI1 12 -#define STM32F7_RCC_APB2_SPI4 13 -#define STM32F7_RCC_APB2_SYSCFG 14 -#define STM32F7_RCC_APB2_TIM9 16 -#define STM32F7_RCC_APB2_TIM10 17 -#define STM32F7_RCC_APB2_TIM11 18 -#define STM32F7_RCC_APB2_SPI5 20 -#define STM32F7_RCC_APB2_SPI6 21 -#define STM32F7_RCC_APB2_SAI1 22 -#define STM32F7_RCC_APB2_SAI2 23 -#define STM32F7_RCC_APB2_LTDC 26 - -#define STM32F7_APB2_RESET(bit) (STM32F7_RCC_APB2_##bit + (0x24 * 8)) -#define STM32F7_APB2_CLOCK(bit) (STM32F7_RCC_APB2_##bit + 0xA0) - -#endif /* _DT_BINDINGS_MFD_STM32F7_RCC_H */ diff --git a/sys/gnu/dts/include/dt-bindings/mfd/stm32h7-rcc.h b/sys/gnu/dts/include/dt-bindings/mfd/stm32h7-rcc.h deleted file mode 100644 index 461a8e04453..00000000000 --- a/sys/gnu/dts/include/dt-bindings/mfd/stm32h7-rcc.h +++ /dev/null @@ -1,136 +0,0 @@ -/* - * This header provides constants for the STM32H7 RCC IP - */ - -#ifndef _DT_BINDINGS_MFD_STM32H7_RCC_H -#define _DT_BINDINGS_MFD_STM32H7_RCC_H - -/* AHB3 */ -#define STM32H7_RCC_AHB3_MDMA 0 -#define STM32H7_RCC_AHB3_DMA2D 4 -#define STM32H7_RCC_AHB3_JPGDEC 5 -#define STM32H7_RCC_AHB3_FMC 12 -#define STM32H7_RCC_AHB3_QUADSPI 14 -#define STM32H7_RCC_AHB3_SDMMC1 16 -#define STM32H7_RCC_AHB3_CPU 31 - -#define STM32H7_AHB3_RESET(bit) (STM32H7_RCC_AHB3_##bit + (0x7C * 8)) - -/* AHB1 */ -#define STM32H7_RCC_AHB1_DMA1 0 -#define STM32H7_RCC_AHB1_DMA2 1 -#define STM32H7_RCC_AHB1_ADC12 5 -#define STM32H7_RCC_AHB1_ART 14 -#define STM32H7_RCC_AHB1_ETH1MAC 15 -#define STM32H7_RCC_AHB1_USB1OTG 25 -#define STM32H7_RCC_AHB1_USB2OTG 27 - -#define STM32H7_AHB1_RESET(bit) (STM32H7_RCC_AHB1_##bit + (0x80 * 8)) - -/* AHB2 */ -#define STM32H7_RCC_AHB2_CAMITF 0 -#define STM32H7_RCC_AHB2_CRYPT 4 -#define STM32H7_RCC_AHB2_HASH 5 -#define STM32H7_RCC_AHB2_RNG 6 -#define STM32H7_RCC_AHB2_SDMMC2 9 - -#define STM32H7_AHB2_RESET(bit) (STM32H7_RCC_AHB2_##bit + (0x84 * 8)) - -/* AHB4 */ -#define STM32H7_RCC_AHB4_GPIOA 0 -#define STM32H7_RCC_AHB4_GPIOB 1 -#define STM32H7_RCC_AHB4_GPIOC 2 -#define STM32H7_RCC_AHB4_GPIOD 3 -#define STM32H7_RCC_AHB4_GPIOE 4 -#define STM32H7_RCC_AHB4_GPIOF 5 -#define STM32H7_RCC_AHB4_GPIOG 6 -#define STM32H7_RCC_AHB4_GPIOH 7 -#define STM32H7_RCC_AHB4_GPIOI 8 -#define STM32H7_RCC_AHB4_GPIOJ 9 -#define STM32H7_RCC_AHB4_GPIOK 10 -#define STM32H7_RCC_AHB4_CRC 19 -#define STM32H7_RCC_AHB4_BDMA 21 -#define STM32H7_RCC_AHB4_ADC3 24 -#define STM32H7_RCC_AHB4_HSEM 25 - -#define STM32H7_AHB4_RESET(bit) (STM32H7_RCC_AHB4_##bit + (0x88 * 8)) - -/* APB3 */ -#define STM32H7_RCC_APB3_LTDC 3 -#define STM32H7_RCC_APB3_DSI 4 - -#define STM32H7_APB3_RESET(bit) (STM32H7_RCC_APB3_##bit + (0x8C * 8)) - -/* APB1L */ -#define STM32H7_RCC_APB1L_TIM2 0 -#define STM32H7_RCC_APB1L_TIM3 1 -#define STM32H7_RCC_APB1L_TIM4 2 -#define STM32H7_RCC_APB1L_TIM5 3 -#define STM32H7_RCC_APB1L_TIM6 4 -#define STM32H7_RCC_APB1L_TIM7 5 -#define STM32H7_RCC_APB1L_TIM12 6 -#define STM32H7_RCC_APB1L_TIM13 7 -#define STM32H7_RCC_APB1L_TIM14 8 -#define STM32H7_RCC_APB1L_LPTIM1 9 -#define STM32H7_RCC_APB1L_SPI2 14 -#define STM32H7_RCC_APB1L_SPI3 15 -#define STM32H7_RCC_APB1L_SPDIF_RX 16 -#define STM32H7_RCC_APB1L_USART2 17 -#define STM32H7_RCC_APB1L_USART3 18 -#define STM32H7_RCC_APB1L_UART4 19 -#define STM32H7_RCC_APB1L_UART5 20 -#define STM32H7_RCC_APB1L_I2C1 21 -#define STM32H7_RCC_APB1L_I2C2 22 -#define STM32H7_RCC_APB1L_I2C3 23 -#define STM32H7_RCC_APB1L_HDMICEC 27 -#define STM32H7_RCC_APB1L_DAC12 29 -#define STM32H7_RCC_APB1L_USART7 30 -#define STM32H7_RCC_APB1L_USART8 31 - -#define STM32H7_APB1L_RESET(bit) (STM32H7_RCC_APB1L_##bit + (0x90 * 8)) - -/* APB1H */ -#define STM32H7_RCC_APB1H_CRS 1 -#define STM32H7_RCC_APB1H_SWP 2 -#define STM32H7_RCC_APB1H_OPAMP 4 -#define STM32H7_RCC_APB1H_MDIOS 5 -#define STM32H7_RCC_APB1H_FDCAN 8 - -#define STM32H7_APB1H_RESET(bit) (STM32H7_RCC_APB1H_##bit + (0x94 * 8)) - -/* APB2 */ -#define STM32H7_RCC_APB2_TIM1 0 -#define STM32H7_RCC_APB2_TIM8 1 -#define STM32H7_RCC_APB2_USART1 4 -#define STM32H7_RCC_APB2_USART6 5 -#define STM32H7_RCC_APB2_SPI1 12 -#define STM32H7_RCC_APB2_SPI4 13 -#define STM32H7_RCC_APB2_TIM15 16 -#define STM32H7_RCC_APB2_TIM16 17 -#define STM32H7_RCC_APB2_TIM17 18 -#define STM32H7_RCC_APB2_SPI5 20 -#define STM32H7_RCC_APB2_SAI1 22 -#define STM32H7_RCC_APB2_SAI2 23 -#define STM32H7_RCC_APB2_SAI3 24 -#define STM32H7_RCC_APB2_DFSDM1 28 -#define STM32H7_RCC_APB2_HRTIM 29 - -#define STM32H7_APB2_RESET(bit) (STM32H7_RCC_APB2_##bit + (0x98 * 8)) - -/* APB4 */ -#define STM32H7_RCC_APB4_SYSCFG 1 -#define STM32H7_RCC_APB4_LPUART1 3 -#define STM32H7_RCC_APB4_SPI6 5 -#define STM32H7_RCC_APB4_I2C4 7 -#define STM32H7_RCC_APB4_LPTIM2 9 -#define STM32H7_RCC_APB4_LPTIM3 10 -#define STM32H7_RCC_APB4_LPTIM4 11 -#define STM32H7_RCC_APB4_LPTIM5 12 -#define STM32H7_RCC_APB4_COMP12 14 -#define STM32H7_RCC_APB4_VREF 15 -#define STM32H7_RCC_APB4_SAI4 21 -#define STM32H7_RCC_APB4_TMPSENS 26 - -#define STM32H7_APB4_RESET(bit) (STM32H7_RCC_APB4_##bit + (0x9C * 8)) - -#endif /* _DT_BINDINGS_MFD_STM32H7_RCC_H */ diff --git a/sys/gnu/dts/include/dt-bindings/mips/lantiq_rcu_gphy.h b/sys/gnu/dts/include/dt-bindings/mips/lantiq_rcu_gphy.h deleted file mode 100644 index 7756d66cc59..00000000000 --- a/sys/gnu/dts/include/dt-bindings/mips/lantiq_rcu_gphy.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * - * Copyright (C) 2016 Martin Blumenstingl - * Copyright (C) 2017 Hauke Mehrtens - */ -#ifndef _DT_BINDINGS_MIPS_LANTIQ_RCU_GPHY_H -#define _DT_BINDINGS_MIPS_LANTIQ_RCU_GPHY_H - -#define GPHY_MODE_GE 1 -#define GPHY_MODE_FE 2 - -#endif /* _DT_BINDINGS_MIPS_LANTIQ_RCU_GPHY_H */ diff --git a/sys/gnu/dts/include/dt-bindings/mux/mux.h b/sys/gnu/dts/include/dt-bindings/mux/mux.h deleted file mode 100644 index 042719218db..00000000000 --- a/sys/gnu/dts/include/dt-bindings/mux/mux.h +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides constants for most Multiplexer bindings. - * - * Most Multiplexer bindings specify an idle state. In most cases, the - * the multiplexer can be left as is when idle, and in some cases it can - * disconnect the input/output and leave the multiplexer in a high - * impedance state. - */ - -#ifndef _DT_BINDINGS_MUX_MUX_H -#define _DT_BINDINGS_MUX_MUX_H - -#define MUX_IDLE_AS_IS (-1) -#define MUX_IDLE_DISCONNECT (-2) - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/net/microchip-lan78xx.h b/sys/gnu/dts/include/dt-bindings/net/microchip-lan78xx.h deleted file mode 100644 index 0742ff07530..00000000000 --- a/sys/gnu/dts/include/dt-bindings/net/microchip-lan78xx.h +++ /dev/null @@ -1,21 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _DT_BINDINGS_MICROCHIP_LAN78XX_H -#define _DT_BINDINGS_MICROCHIP_LAN78XX_H - -/* LED modes for LAN7800/LAN7850 embedded PHY */ - -#define LAN78XX_LINK_ACTIVITY 0 -#define LAN78XX_LINK_1000_ACTIVITY 1 -#define LAN78XX_LINK_100_ACTIVITY 2 -#define LAN78XX_LINK_10_ACTIVITY 3 -#define LAN78XX_LINK_100_1000_ACTIVITY 4 -#define LAN78XX_LINK_10_1000_ACTIVITY 5 -#define LAN78XX_LINK_10_100_ACTIVITY 6 -#define LAN78XX_DUPLEX_COLLISION 8 -#define LAN78XX_COLLISION 9 -#define LAN78XX_ACTIVITY 10 -#define LAN78XX_AUTONEG_FAULT 12 -#define LAN78XX_FORCE_LED_OFF 14 -#define LAN78XX_FORCE_LED_ON 15 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/net/mscc-phy-vsc8531.h b/sys/gnu/dts/include/dt-bindings/net/mscc-phy-vsc8531.h deleted file mode 100644 index 9eb2ec2b2ea..00000000000 --- a/sys/gnu/dts/include/dt-bindings/net/mscc-phy-vsc8531.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * Device Tree constants for Microsemi VSC8531 PHY - * - * Author: Nagaraju Lakkaraju - * - * License: Dual MIT/GPL - * Copyright (c) 2017 Microsemi Corporation - */ - -#ifndef _DT_BINDINGS_MSCC_VSC8531_H -#define _DT_BINDINGS_MSCC_VSC8531_H - -/* PHY LED Modes */ -#define VSC8531_LINK_ACTIVITY 0 -#define VSC8531_LINK_1000_ACTIVITY 1 -#define VSC8531_LINK_100_ACTIVITY 2 -#define VSC8531_LINK_10_ACTIVITY 3 -#define VSC8531_LINK_100_1000_ACTIVITY 4 -#define VSC8531_LINK_10_1000_ACTIVITY 5 -#define VSC8531_LINK_10_100_ACTIVITY 6 -#define VSC8584_LINK_100FX_1000X_ACTIVITY 7 -#define VSC8531_DUPLEX_COLLISION 8 -#define VSC8531_COLLISION 9 -#define VSC8531_ACTIVITY 10 -#define VSC8584_100FX_1000X_ACTIVITY 11 -#define VSC8531_AUTONEG_FAULT 12 -#define VSC8531_SERIAL_MODE 13 -#define VSC8531_FORCE_LED_OFF 14 -#define VSC8531_FORCE_LED_ON 15 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/net/qca-ar803x.h b/sys/gnu/dts/include/dt-bindings/net/qca-ar803x.h deleted file mode 100644 index 9c046c7242e..00000000000 --- a/sys/gnu/dts/include/dt-bindings/net/qca-ar803x.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Device Tree constants for the Qualcomm Atheros AR803x PHYs - */ - -#ifndef _DT_BINDINGS_QCA_AR803X_H -#define _DT_BINDINGS_QCA_AR803X_H - -#define AR803X_STRENGTH_FULL 0 -#define AR803X_STRENGTH_HALF 1 -#define AR803X_STRENGTH_QUARTER 2 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/net/rfkill-regulator.h b/sys/gnu/dts/include/dt-bindings/net/rfkill-regulator.h deleted file mode 100644 index ae32273c7ba..00000000000 --- a/sys/gnu/dts/include/dt-bindings/net/rfkill-regulator.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This header provides macros for rfkill-regulator bindings. - * - * Copyright (C) 2014 Marek Belisko - * - * GPLv2 only - */ - -#ifndef __DT_BINDINGS_RFKILL_REGULATOR_H__ -#define __DT_BINDINGS_RFKILL_REGULATOR_H__ - - -#define RFKILL_TYPE_ALL (0) -#define RFKILL_TYPE_WLAN (1) -#define RFKILL_TYPE_BLUETOOTH (2) -#define RFKILL_TYPE_UWB (3) -#define RFKILL_TYPE_WIMAX (4) -#define RFKILL_TYPE_WWAN (5) -#define RFKILL_TYPE_GPS (6) -#define RFKILL_TYPE_FM (7) -#define RFKILL_TYPE_NFC (8) - -#endif /* __DT_BINDINGS_RFKILL_REGULATOR_H__ */ diff --git a/sys/gnu/dts/include/dt-bindings/net/ti-dp83867.h b/sys/gnu/dts/include/dt-bindings/net/ti-dp83867.h deleted file mode 100644 index 6fc4b445d3a..00000000000 --- a/sys/gnu/dts/include/dt-bindings/net/ti-dp83867.h +++ /dev/null @@ -1,53 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Device Tree constants for the Texas Instruments DP83867 PHY - * - * Author: Dan Murphy - * - * Copyright: (C) 2015 Texas Instruments, Inc. - */ - -#ifndef _DT_BINDINGS_TI_DP83867_H -#define _DT_BINDINGS_TI_DP83867_H - -/* PHY CTRL bits */ -#define DP83867_PHYCR_FIFO_DEPTH_3_B_NIB 0x00 -#define DP83867_PHYCR_FIFO_DEPTH_4_B_NIB 0x01 -#define DP83867_PHYCR_FIFO_DEPTH_6_B_NIB 0x02 -#define DP83867_PHYCR_FIFO_DEPTH_8_B_NIB 0x03 - -/* RGMIIDCTL internal delay for rx and tx */ -#define DP83867_RGMIIDCTL_250_PS 0x0 -#define DP83867_RGMIIDCTL_500_PS 0x1 -#define DP83867_RGMIIDCTL_750_PS 0x2 -#define DP83867_RGMIIDCTL_1_NS 0x3 -#define DP83867_RGMIIDCTL_1_25_NS 0x4 -#define DP83867_RGMIIDCTL_1_50_NS 0x5 -#define DP83867_RGMIIDCTL_1_75_NS 0x6 -#define DP83867_RGMIIDCTL_2_00_NS 0x7 -#define DP83867_RGMIIDCTL_2_25_NS 0x8 -#define DP83867_RGMIIDCTL_2_50_NS 0x9 -#define DP83867_RGMIIDCTL_2_75_NS 0xa -#define DP83867_RGMIIDCTL_3_00_NS 0xb -#define DP83867_RGMIIDCTL_3_25_NS 0xc -#define DP83867_RGMIIDCTL_3_50_NS 0xd -#define DP83867_RGMIIDCTL_3_75_NS 0xe -#define DP83867_RGMIIDCTL_4_00_NS 0xf - -/* IO_MUX_CFG - Clock output selection */ -#define DP83867_CLK_O_SEL_CHN_A_RCLK 0x0 -#define DP83867_CLK_O_SEL_CHN_B_RCLK 0x1 -#define DP83867_CLK_O_SEL_CHN_C_RCLK 0x2 -#define DP83867_CLK_O_SEL_CHN_D_RCLK 0x3 -#define DP83867_CLK_O_SEL_CHN_A_RCLK_DIV5 0x4 -#define DP83867_CLK_O_SEL_CHN_B_RCLK_DIV5 0x5 -#define DP83867_CLK_O_SEL_CHN_C_RCLK_DIV5 0x6 -#define DP83867_CLK_O_SEL_CHN_D_RCLK_DIV5 0x7 -#define DP83867_CLK_O_SEL_CHN_A_TCLK 0x8 -#define DP83867_CLK_O_SEL_CHN_B_TCLK 0x9 -#define DP83867_CLK_O_SEL_CHN_C_TCLK 0xA -#define DP83867_CLK_O_SEL_CHN_D_TCLK 0xB -#define DP83867_CLK_O_SEL_REF_CLK 0xC -/* Special flag to indicate clock should be off */ -#define DP83867_CLK_O_SEL_OFF 0xFFFFFFFF -#endif diff --git a/sys/gnu/dts/include/dt-bindings/net/ti-dp83869.h b/sys/gnu/dts/include/dt-bindings/net/ti-dp83869.h deleted file mode 100644 index 218b1a64e97..00000000000 --- a/sys/gnu/dts/include/dt-bindings/net/ti-dp83869.h +++ /dev/null @@ -1,42 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Device Tree constants for the Texas Instruments DP83869 PHY - * - * Author: Dan Murphy - * - * Copyright: (C) 2019 Texas Instruments, Inc. - */ - -#ifndef _DT_BINDINGS_TI_DP83869_H -#define _DT_BINDINGS_TI_DP83869_H - -/* PHY CTRL bits */ -#define DP83869_PHYCR_FIFO_DEPTH_3_B_NIB 0x00 -#define DP83869_PHYCR_FIFO_DEPTH_4_B_NIB 0x01 -#define DP83869_PHYCR_FIFO_DEPTH_6_B_NIB 0x02 -#define DP83869_PHYCR_FIFO_DEPTH_8_B_NIB 0x03 - -/* IO_MUX_CFG - Clock output selection */ -#define DP83869_CLK_O_SEL_CHN_A_RCLK 0x0 -#define DP83869_CLK_O_SEL_CHN_B_RCLK 0x1 -#define DP83869_CLK_O_SEL_CHN_C_RCLK 0x2 -#define DP83869_CLK_O_SEL_CHN_D_RCLK 0x3 -#define DP83869_CLK_O_SEL_CHN_A_RCLK_DIV5 0x4 -#define DP83869_CLK_O_SEL_CHN_B_RCLK_DIV5 0x5 -#define DP83869_CLK_O_SEL_CHN_C_RCLK_DIV5 0x6 -#define DP83869_CLK_O_SEL_CHN_D_RCLK_DIV5 0x7 -#define DP83869_CLK_O_SEL_CHN_A_TCLK 0x8 -#define DP83869_CLK_O_SEL_CHN_B_TCLK 0x9 -#define DP83869_CLK_O_SEL_CHN_C_TCLK 0xa -#define DP83869_CLK_O_SEL_CHN_D_TCLK 0xb -#define DP83869_CLK_O_SEL_REF_CLK 0xc - -#define DP83869_RGMII_COPPER_ETHERNET 0x00 -#define DP83869_RGMII_1000_BASE 0x01 -#define DP83869_RGMII_100_BASE 0x02 -#define DP83869_RGMII_SGMII_BRIDGE 0x03 -#define DP83869_1000M_MEDIA_CONVERT 0x04 -#define DP83869_100M_MEDIA_CONVERT 0x05 -#define DP83869_SGMII_COPPER_ETHERNET 0x06 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/phy/phy-am654-serdes.h b/sys/gnu/dts/include/dt-bindings/phy/phy-am654-serdes.h deleted file mode 100644 index e8d901729ed..00000000000 --- a/sys/gnu/dts/include/dt-bindings/phy/phy-am654-serdes.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides constants for AM654 SERDES. - */ - -#ifndef _DT_BINDINGS_AM654_SERDES -#define _DT_BINDINGS_AM654_SERDES - -#define AM654_SERDES_CMU_REFCLK 0 -#define AM654_SERDES_LO_REFCLK 1 -#define AM654_SERDES_RO_REFCLK 2 - -#endif /* _DT_BINDINGS_AM654_SERDES */ diff --git a/sys/gnu/dts/include/dt-bindings/phy/phy-lantiq-vrx200-pcie.h b/sys/gnu/dts/include/dt-bindings/phy/phy-lantiq-vrx200-pcie.h deleted file mode 100644 index 95a7896356d..00000000000 --- a/sys/gnu/dts/include/dt-bindings/phy/phy-lantiq-vrx200-pcie.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) 2019 Martin Blumenstingl - */ - -#define LANTIQ_PCIE_PHY_MODE_25MHZ 0 -#define LANTIQ_PCIE_PHY_MODE_25MHZ_SSC 1 -#define LANTIQ_PCIE_PHY_MODE_36MHZ 2 -#define LANTIQ_PCIE_PHY_MODE_36MHZ_SSC 3 -#define LANTIQ_PCIE_PHY_MODE_100MHZ 4 -#define LANTIQ_PCIE_PHY_MODE_100MHZ_SSC 5 diff --git a/sys/gnu/dts/include/dt-bindings/phy/phy-miphy365x.h b/sys/gnu/dts/include/dt-bindings/phy/phy-miphy365x.h deleted file mode 100644 index 8ef8aba6edd..00000000000 --- a/sys/gnu/dts/include/dt-bindings/phy/phy-miphy365x.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * This header provides constants for the phy framework - * based on the STMicroelectronics MiPHY365x. - * - * Author: Lee Jones - */ -#ifndef _DT_BINDINGS_PHY_MIPHY -#define _DT_BINDINGS_PHY_MIPHY - -#define MIPHY_TYPE_SATA 1 -#define MIPHY_TYPE_PCIE 2 -#define MIPHY_TYPE_USB 3 - -#endif /* _DT_BINDINGS_PHY_MIPHY */ diff --git a/sys/gnu/dts/include/dt-bindings/phy/phy-ocelot-serdes.h b/sys/gnu/dts/include/dt-bindings/phy/phy-ocelot-serdes.h deleted file mode 100644 index fe70adaca68..00000000000 --- a/sys/gnu/dts/include/dt-bindings/phy/phy-ocelot-serdes.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ -/* Copyright (c) 2018 Microsemi Corporation */ -#ifndef __PHY_OCELOT_SERDES_H__ -#define __PHY_OCELOT_SERDES_H__ - -#define SERDES1G(x) (x) -#define SERDES1G_MAX SERDES1G(5) -#define SERDES6G(x) (SERDES1G_MAX + 1 + (x)) -#define SERDES6G_MAX SERDES6G(2) -#define SERDES_MAX (SERDES6G_MAX + 1) - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/phy/phy-pistachio-usb.h b/sys/gnu/dts/include/dt-bindings/phy/phy-pistachio-usb.h deleted file mode 100644 index 3542a67dafb..00000000000 --- a/sys/gnu/dts/include/dt-bindings/phy/phy-pistachio-usb.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) 2015 Google, Inc. - */ - -#ifndef _DT_BINDINGS_PHY_PISTACHIO -#define _DT_BINDINGS_PHY_PISTACHIO - -#define REFCLK_XO_CRYSTAL 0x0 -#define REFCLK_X0_EXT_CLK 0x1 -#define REFCLK_CLK_CORE 0x2 - -#endif /* _DT_BINDINGS_PHY_PISTACHIO */ diff --git a/sys/gnu/dts/include/dt-bindings/phy/phy-qcom-qusb2.h b/sys/gnu/dts/include/dt-bindings/phy/phy-qcom-qusb2.h deleted file mode 100644 index 5c5e4d800ca..00000000000 --- a/sys/gnu/dts/include/dt-bindings/phy/phy-qcom-qusb2.h +++ /dev/null @@ -1,37 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_QCOM_PHY_QUSB2_H_ -#define _DT_BINDINGS_QCOM_PHY_QUSB2_H_ - -/* PHY HSTX TRIM bit values (24mA to 15mA) */ -#define QUSB2_V2_HSTX_TRIM_24_0_MA 0x0 -#define QUSB2_V2_HSTX_TRIM_23_4_MA 0x1 -#define QUSB2_V2_HSTX_TRIM_22_8_MA 0x2 -#define QUSB2_V2_HSTX_TRIM_22_2_MA 0x3 -#define QUSB2_V2_HSTX_TRIM_21_6_MA 0x4 -#define QUSB2_V2_HSTX_TRIM_21_0_MA 0x5 -#define QUSB2_V2_HSTX_TRIM_20_4_MA 0x6 -#define QUSB2_V2_HSTX_TRIM_19_8_MA 0x7 -#define QUSB2_V2_HSTX_TRIM_19_2_MA 0x8 -#define QUSB2_V2_HSTX_TRIM_18_6_MA 0x9 -#define QUSB2_V2_HSTX_TRIM_18_0_MA 0xa -#define QUSB2_V2_HSTX_TRIM_17_4_MA 0xb -#define QUSB2_V2_HSTX_TRIM_16_8_MA 0xc -#define QUSB2_V2_HSTX_TRIM_16_2_MA 0xd -#define QUSB2_V2_HSTX_TRIM_15_6_MA 0xe -#define QUSB2_V2_HSTX_TRIM_15_0_MA 0xf - -/* PHY PREEMPHASIS bit values */ -#define QUSB2_V2_PREEMPHASIS_NONE 0 -#define QUSB2_V2_PREEMPHASIS_5_PERCENT 1 -#define QUSB2_V2_PREEMPHASIS_10_PERCENT 2 -#define QUSB2_V2_PREEMPHASIS_15_PERCENT 3 - -/* PHY PREEMPHASIS-WIDTH bit values */ -#define QUSB2_V2_PREEMPHASIS_WIDTH_FULL_BIT 0 -#define QUSB2_V2_PREEMPHASIS_WIDTH_HALF_BIT 1 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/phy/phy.h b/sys/gnu/dts/include/dt-bindings/phy/phy.h deleted file mode 100644 index 1f3f866fae7..00000000000 --- a/sys/gnu/dts/include/dt-bindings/phy/phy.h +++ /dev/null @@ -1,21 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * - * This header provides constants for the phy framework - * - * Copyright (C) 2014 STMicroelectronics - * Author: Gabriel Fernandez - */ - -#ifndef _DT_BINDINGS_PHY -#define _DT_BINDINGS_PHY - -#define PHY_NONE 0 -#define PHY_TYPE_SATA 1 -#define PHY_TYPE_PCIE 2 -#define PHY_TYPE_USB2 3 -#define PHY_TYPE_USB3 4 -#define PHY_TYPE_UFS 5 -#define PHY_TYPE_DP 6 - -#endif /* _DT_BINDINGS_PHY */ diff --git a/sys/gnu/dts/include/dt-bindings/pinctrl/am33xx.h b/sys/gnu/dts/include/dt-bindings/pinctrl/am33xx.h deleted file mode 100644 index 17877e85980..00000000000 --- a/sys/gnu/dts/include/dt-bindings/pinctrl/am33xx.h +++ /dev/null @@ -1,172 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides constants specific to AM33XX pinctrl bindings. - */ - -#ifndef _DT_BINDINGS_PINCTRL_AM33XX_H -#define _DT_BINDINGS_PINCTRL_AM33XX_H - -#include - -/* am33xx specific mux bit defines */ -#undef PULL_ENA -#undef INPUT_EN - -#define PULL_DISABLE (1 << 3) -#define INPUT_EN (1 << 5) -#define SLEWCTRL_SLOW (1 << 6) -#define SLEWCTRL_FAST 0 - -/* update macro depending on INPUT_EN and PULL_ENA */ -#undef PIN_OUTPUT -#undef PIN_OUTPUT_PULLUP -#undef PIN_OUTPUT_PULLDOWN -#undef PIN_INPUT -#undef PIN_INPUT_PULLUP -#undef PIN_INPUT_PULLDOWN - -#define PIN_OUTPUT (PULL_DISABLE) -#define PIN_OUTPUT_PULLUP (PULL_UP) -#define PIN_OUTPUT_PULLDOWN 0 -#define PIN_INPUT (INPUT_EN | PULL_DISABLE) -#define PIN_INPUT_PULLUP (INPUT_EN | PULL_UP) -#define PIN_INPUT_PULLDOWN (INPUT_EN) - -/* undef non-existing modes */ -#undef PIN_OFF_NONE -#undef PIN_OFF_OUTPUT_HIGH -#undef PIN_OFF_OUTPUT_LOW -#undef PIN_OFF_INPUT_PULLUP -#undef PIN_OFF_INPUT_PULLDOWN -#undef PIN_OFF_WAKEUPENABLE - -#define AM335X_PIN_OFFSET_MIN 0x0800U - -#define AM335X_PIN_GPMC_AD0 0x800 -#define AM335X_PIN_GPMC_AD1 0x804 -#define AM335X_PIN_GPMC_AD2 0x808 -#define AM335X_PIN_GPMC_AD3 0x80c -#define AM335X_PIN_GPMC_AD4 0x810 -#define AM335X_PIN_GPMC_AD5 0x814 -#define AM335X_PIN_GPMC_AD6 0x818 -#define AM335X_PIN_GPMC_AD7 0x81c -#define AM335X_PIN_GPMC_AD8 0x820 -#define AM335X_PIN_GPMC_AD9 0x824 -#define AM335X_PIN_GPMC_AD10 0x828 -#define AM335X_PIN_GPMC_AD11 0x82c -#define AM335X_PIN_GPMC_AD12 0x830 -#define AM335X_PIN_GPMC_AD13 0x834 -#define AM335X_PIN_GPMC_AD14 0x838 -#define AM335X_PIN_GPMC_AD15 0x83c -#define AM335X_PIN_GPMC_A0 0x840 -#define AM335X_PIN_GPMC_A1 0x844 -#define AM335X_PIN_GPMC_A2 0x848 -#define AM335X_PIN_GPMC_A3 0x84c -#define AM335X_PIN_GPMC_A4 0x850 -#define AM335X_PIN_GPMC_A5 0x854 -#define AM335X_PIN_GPMC_A6 0x858 -#define AM335X_PIN_GPMC_A7 0x85c -#define AM335X_PIN_GPMC_A8 0x860 -#define AM335X_PIN_GPMC_A9 0x864 -#define AM335X_PIN_GPMC_A10 0x868 -#define AM335X_PIN_GPMC_A11 0x86c -#define AM335X_PIN_GPMC_WAIT0 0x870 -#define AM335X_PIN_GPMC_WPN 0x874 -#define AM335X_PIN_GPMC_BEN1 0x878 -#define AM335X_PIN_GPMC_CSN0 0x87c -#define AM335X_PIN_GPMC_CSN1 0x880 -#define AM335X_PIN_GPMC_CSN2 0x884 -#define AM335X_PIN_GPMC_CSN3 0x888 -#define AM335X_PIN_GPMC_CLK 0x88c -#define AM335X_PIN_GPMC_ADVN_ALE 0x890 -#define AM335X_PIN_GPMC_OEN_REN 0x894 -#define AM335X_PIN_GPMC_WEN 0x898 -#define AM335X_PIN_GPMC_BEN0_CLE 0x89c -#define AM335X_PIN_LCD_DATA0 0x8a0 -#define AM335X_PIN_LCD_DATA1 0x8a4 -#define AM335X_PIN_LCD_DATA2 0x8a8 -#define AM335X_PIN_LCD_DATA3 0x8ac -#define AM335X_PIN_LCD_DATA4 0x8b0 -#define AM335X_PIN_LCD_DATA5 0x8b4 -#define AM335X_PIN_LCD_DATA6 0x8b8 -#define AM335X_PIN_LCD_DATA7 0x8bc -#define AM335X_PIN_LCD_DATA8 0x8c0 -#define AM335X_PIN_LCD_DATA9 0x8c4 -#define AM335X_PIN_LCD_DATA10 0x8c8 -#define AM335X_PIN_LCD_DATA11 0x8cc -#define AM335X_PIN_LCD_DATA12 0x8d0 -#define AM335X_PIN_LCD_DATA13 0x8d4 -#define AM335X_PIN_LCD_DATA14 0x8d8 -#define AM335X_PIN_LCD_DATA15 0x8dc -#define AM335X_PIN_LCD_VSYNC 0x8e0 -#define AM335X_PIN_LCD_HSYNC 0x8e4 -#define AM335X_PIN_LCD_PCLK 0x8e8 -#define AM335X_PIN_LCD_AC_BIAS_EN 0x8ec -#define AM335X_PIN_MMC0_DAT3 0x8f0 -#define AM335X_PIN_MMC0_DAT2 0x8f4 -#define AM335X_PIN_MMC0_DAT1 0x8f8 -#define AM335X_PIN_MMC0_DAT0 0x8fc -#define AM335X_PIN_MMC0_CLK 0x900 -#define AM335X_PIN_MMC0_CMD 0x904 -#define AM335X_PIN_MII1_COL 0x908 -#define AM335X_PIN_MII1_CRS 0x90c -#define AM335X_PIN_MII1_RX_ER 0x910 -#define AM335X_PIN_MII1_TX_EN 0x914 -#define AM335X_PIN_MII1_RX_DV 0x918 -#define AM335X_PIN_MII1_TXD3 0x91c -#define AM335X_PIN_MII1_TXD2 0x920 -#define AM335X_PIN_MII1_TXD1 0x924 -#define AM335X_PIN_MII1_TXD0 0x928 -#define AM335X_PIN_MII1_TX_CLK 0x92c -#define AM335X_PIN_MII1_RX_CLK 0x930 -#define AM335X_PIN_MII1_RXD3 0x934 -#define AM335X_PIN_MII1_RXD2 0x938 -#define AM335X_PIN_MII1_RXD1 0x93c -#define AM335X_PIN_MII1_RXD0 0x940 -#define AM335X_PIN_RMII1_REF_CLK 0x944 -#define AM335X_PIN_MDIO 0x948 -#define AM335X_PIN_MDC 0x94c -#define AM335X_PIN_SPI0_SCLK 0x950 -#define AM335X_PIN_SPI0_D0 0x954 -#define AM335X_PIN_SPI0_D1 0x958 -#define AM335X_PIN_SPI0_CS0 0x95c -#define AM335X_PIN_SPI0_CS1 0x960 -#define AM335X_PIN_ECAP0_IN_PWM0_OUT 0x964 -#define AM335X_PIN_UART0_CTSN 0x968 -#define AM335X_PIN_UART0_RTSN 0x96c -#define AM335X_PIN_UART0_RXD 0x970 -#define AM335X_PIN_UART0_TXD 0x974 -#define AM335X_PIN_UART1_CTSN 0x978 -#define AM335X_PIN_UART1_RTSN 0x97c -#define AM335X_PIN_UART1_RXD 0x980 -#define AM335X_PIN_UART1_TXD 0x984 -#define AM335X_PIN_I2C0_SDA 0x988 -#define AM335X_PIN_I2C0_SCL 0x98c -#define AM335X_PIN_MCASP0_ACLKX 0x990 -#define AM335X_PIN_MCASP0_FSX 0x994 -#define AM335X_PIN_MCASP0_AXR0 0x998 -#define AM335X_PIN_MCASP0_AHCLKR 0x99c -#define AM335X_PIN_MCASP0_ACLKR 0x9a0 -#define AM335X_PIN_MCASP0_FSR 0x9a4 -#define AM335X_PIN_MCASP0_AXR1 0x9a8 -#define AM335X_PIN_MCASP0_AHCLKX 0x9ac -#define AM335X_PIN_XDMA_EVENT_INTR0 0x9b0 -#define AM335X_PIN_XDMA_EVENT_INTR1 0x9b4 -#define AM335X_PIN_WARMRSTN 0x9b8 -#define AM335X_PIN_NNMI 0x9c0 -#define AM335X_PIN_TMS 0x9d0 -#define AM335X_PIN_TDI 0x9d4 -#define AM335X_PIN_TDO 0x9d8 -#define AM335X_PIN_TCK 0x9dc -#define AM335X_PIN_TRSTN 0x9e0 -#define AM335X_PIN_EMU0 0x9e4 -#define AM335X_PIN_EMU1 0x9e8 -#define AM335X_PIN_RTC_PWRONRSTN 0x9f8 -#define AM335X_PIN_PMIC_POWER_EN 0x9fc -#define AM335X_PIN_EXT_WAKEUP 0xa00 -#define AM335X_PIN_USB0_DRVVBUS 0xa1c -#define AM335X_PIN_USB1_DRVVBUS 0xa34 - -#define AM335X_PIN_OFFSET_MAX 0x0a34U - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/pinctrl/am43xx.h b/sys/gnu/dts/include/dt-bindings/pinctrl/am43xx.h deleted file mode 100644 index 6ce4a32f77d..00000000000 --- a/sys/gnu/dts/include/dt-bindings/pinctrl/am43xx.h +++ /dev/null @@ -1,55 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides constants specific to AM43XX pinctrl bindings. - */ - -#ifndef _DT_BINDINGS_PINCTRL_AM43XX_H -#define _DT_BINDINGS_PINCTRL_AM43XX_H - -#define MUX_MODE0 0 -#define MUX_MODE1 1 -#define MUX_MODE2 2 -#define MUX_MODE3 3 -#define MUX_MODE4 4 -#define MUX_MODE5 5 -#define MUX_MODE6 6 -#define MUX_MODE7 7 -#define MUX_MODE8 8 -#define MUX_MODE9 9 - -#define PULL_DISABLE (1 << 16) -#define PULL_UP (1 << 17) -#define INPUT_EN (1 << 18) -#define SLEWCTRL_SLOW (1 << 19) -#define SLEWCTRL_FAST 0 -#define DS0_FORCE_OFF_MODE (1 << 24) -#define DS0_INPUT (1 << 25) -#define DS0_FORCE_OUT_HIGH (1 << 26) -#define DS0_PULL_UP_DOWN_EN (0 << 27) -#define DS0_PULL_UP_DOWN_DIS (1 << 27) -#define DS0_PULL_UP_SEL (1 << 28) -#define WAKEUP_ENABLE (1 << 29) - -#define DS0_PIN_OUTPUT (DS0_FORCE_OFF_MODE) -#define DS0_PIN_OUTPUT_HIGH (DS0_FORCE_OFF_MODE | DS0_FORCE_OUT_HIGH) -#define DS0_PIN_OUTPUT_PULLUP (DS0_FORCE_OFF_MODE | DS0_PULL_UP_DOWN_EN | DS0_PULL_UP_SEL) -#define DS0_PIN_OUTPUT_PULLDOWN (DS0_FORCE_OFF_MODE | DS0_PULL_UP_DOWN_EN) -#define DS0_PIN_INPUT (DS0_FORCE_OFF_MODE | DS0_INPUT) -#define DS0_PIN_INPUT_PULLUP (DS0_FORCE_OFF_MODE | DS0_INPUT | DS0_PULL_UP_DOWN_EN | DS0_PULL_UP_SEL) -#define DS0_PIN_INPUT_PULLDOWN (DS0_FORCE_OFF_MODE | DS0_INPUT | DS0_PULL_UP_DOWN_EN) - -#define PIN_OUTPUT (PULL_DISABLE) -#define PIN_OUTPUT_PULLUP (PULL_UP) -#define PIN_OUTPUT_PULLDOWN 0 -#define PIN_INPUT (INPUT_EN | PULL_DISABLE) -#define PIN_INPUT_PULLUP (INPUT_EN | PULL_UP) -#define PIN_INPUT_PULLDOWN (INPUT_EN) - -/* - * Macro to allow using the absolute physical address instead of the - * padconf registers instead of the offset from padconf base. - */ -#define AM4372_IOPAD(pa, val) (((pa) & 0xffff) - 0x0800) (val) - -#endif - diff --git a/sys/gnu/dts/include/dt-bindings/pinctrl/at91.h b/sys/gnu/dts/include/dt-bindings/pinctrl/at91.h deleted file mode 100644 index e8e117306b1..00000000000 --- a/sys/gnu/dts/include/dt-bindings/pinctrl/at91.h +++ /dev/null @@ -1,49 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * This header provides constants for most at91 pinctrl bindings. - * - * Copyright (C) 2013 Jean-Christophe PLAGNIOL-VILLARD - */ - -#ifndef __DT_BINDINGS_AT91_PINCTRL_H__ -#define __DT_BINDINGS_AT91_PINCTRL_H__ - -#define AT91_PINCTRL_NONE (0 << 0) -#define AT91_PINCTRL_PULL_UP (1 << 0) -#define AT91_PINCTRL_MULTI_DRIVE (1 << 1) -#define AT91_PINCTRL_DEGLITCH (1 << 2) -#define AT91_PINCTRL_PULL_DOWN (1 << 3) -#define AT91_PINCTRL_DIS_SCHMIT (1 << 4) -#define AT91_PINCTRL_OUTPUT (1 << 7) -#define AT91_PINCTRL_OUTPUT_VAL(x) ((x & 0x1) << 8) -#define AT91_PINCTRL_SLEWRATE (1 << 9) -#define AT91_PINCTRL_DEBOUNCE (1 << 16) -#define AT91_PINCTRL_DEBOUNCE_VAL(x) (x << 17) - -#define AT91_PINCTRL_PULL_UP_DEGLITCH (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DEGLITCH) - -#define AT91_PINCTRL_DRIVE_STRENGTH_DEFAULT (0x0 << 5) -#define AT91_PINCTRL_DRIVE_STRENGTH_LOW (0x1 << 5) -#define AT91_PINCTRL_DRIVE_STRENGTH_MED (0x2 << 5) -#define AT91_PINCTRL_DRIVE_STRENGTH_HI (0x3 << 5) - -#define AT91_PINCTRL_SLEWRATE_ENA (0x0 << 9) -#define AT91_PINCTRL_SLEWRATE_DIS (0x1 << 9) - -#define AT91_PIOA 0 -#define AT91_PIOB 1 -#define AT91_PIOC 2 -#define AT91_PIOD 3 -#define AT91_PIOE 4 - -#define AT91_PERIPH_GPIO 0 -#define AT91_PERIPH_A 1 -#define AT91_PERIPH_B 2 -#define AT91_PERIPH_C 3 -#define AT91_PERIPH_D 4 - -#define ATMEL_PIO_DRVSTR_LO 1 -#define ATMEL_PIO_DRVSTR_ME 2 -#define ATMEL_PIO_DRVSTR_HI 3 - -#endif /* __DT_BINDINGS_AT91_PINCTRL_H__ */ diff --git a/sys/gnu/dts/include/dt-bindings/pinctrl/bcm2835.h b/sys/gnu/dts/include/dt-bindings/pinctrl/bcm2835.h deleted file mode 100644 index b5b2654a0e4..00000000000 --- a/sys/gnu/dts/include/dt-bindings/pinctrl/bcm2835.h +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Header providing constants for bcm2835 pinctrl bindings. - * - * Copyright (C) 2015 Stefan Wahren - */ - -#ifndef __DT_BINDINGS_PINCTRL_BCM2835_H__ -#define __DT_BINDINGS_PINCTRL_BCM2835_H__ - -/* brcm,function property */ -#define BCM2835_FSEL_GPIO_IN 0 -#define BCM2835_FSEL_GPIO_OUT 1 -#define BCM2835_FSEL_ALT5 2 -#define BCM2835_FSEL_ALT4 3 -#define BCM2835_FSEL_ALT0 4 -#define BCM2835_FSEL_ALT1 5 -#define BCM2835_FSEL_ALT2 6 -#define BCM2835_FSEL_ALT3 7 - -/* brcm,pull property */ -#define BCM2835_PUD_OFF 0 -#define BCM2835_PUD_DOWN 1 -#define BCM2835_PUD_UP 2 - -#endif /* __DT_BINDINGS_PINCTRL_BCM2835_H__ */ diff --git a/sys/gnu/dts/include/dt-bindings/pinctrl/brcm,pinctrl-stingray.h b/sys/gnu/dts/include/dt-bindings/pinctrl/brcm,pinctrl-stingray.h deleted file mode 100644 index caa6c664b4f..00000000000 --- a/sys/gnu/dts/include/dt-bindings/pinctrl/brcm,pinctrl-stingray.h +++ /dev/null @@ -1,68 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright(c) 2017 Broadcom Corporation. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __DT_BINDINGS_PINCTRL_BRCM_STINGRAY_H__ -#define __DT_BINDINGS_PINCTRL_BRCM_STINGRAY_H__ - -/* Alternate functions available in MUX controller */ -#define MODE_NITRO 0 -#define MODE_NAND 1 -#define MODE_PNOR 2 -#define MODE_GPIO 3 - -/* Pad configuration attribute */ -#define PAD_SLEW_RATE_ENA (1 << 0) -#define PAD_SLEW_RATE_ENA_MASK (1 << 0) - -#define PAD_DRIVE_STRENGTH_2_MA (0 << 1) -#define PAD_DRIVE_STRENGTH_4_MA (1 << 1) -#define PAD_DRIVE_STRENGTH_6_MA (2 << 1) -#define PAD_DRIVE_STRENGTH_8_MA (3 << 1) -#define PAD_DRIVE_STRENGTH_10_MA (4 << 1) -#define PAD_DRIVE_STRENGTH_12_MA (5 << 1) -#define PAD_DRIVE_STRENGTH_14_MA (6 << 1) -#define PAD_DRIVE_STRENGTH_16_MA (7 << 1) -#define PAD_DRIVE_STRENGTH_MASK (7 << 1) - -#define PAD_PULL_UP_ENA (1 << 4) -#define PAD_PULL_UP_ENA_MASK (1 << 4) - -#define PAD_PULL_DOWN_ENA (1 << 5) -#define PAD_PULL_DOWN_ENA_MASK (1 << 5) - -#define PAD_INPUT_PATH_DIS (1 << 6) -#define PAD_INPUT_PATH_DIS_MASK (1 << 6) - -#define PAD_HYSTERESIS_ENA (1 << 7) -#define PAD_HYSTERESIS_ENA_MASK (1 << 7) - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/pinctrl/dm814x.h b/sys/gnu/dts/include/dt-bindings/pinctrl/dm814x.h deleted file mode 100644 index afbabbc4ddb..00000000000 --- a/sys/gnu/dts/include/dt-bindings/pinctrl/dm814x.h +++ /dev/null @@ -1,49 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides constants specific to DM814X pinctrl bindings. - */ - -#ifndef _DT_BINDINGS_PINCTRL_DM814X_H -#define _DT_BINDINGS_PINCTRL_DM814X_H - -#include - -#undef INPUT_EN -#undef PULL_UP -#undef PULL_ENA - -/* - * Note that dm814x silicon revision 2.1 and older require input enabled - * (bit 18 set) for all 3.3V I/Os to avoid cumulative hardware damage. For - * more info, see errata advisory 2.1.87. We leave bit 18 out of - * function-mask in dm814x.h and rely on the bootloader for it. - */ -#define INPUT_EN (1 << 18) -#define PULL_UP (1 << 17) -#define PULL_DISABLE (1 << 16) - -/* update macro depending on INPUT_EN and PULL_ENA */ -#undef PIN_OUTPUT -#undef PIN_OUTPUT_PULLUP -#undef PIN_OUTPUT_PULLDOWN -#undef PIN_INPUT -#undef PIN_INPUT_PULLUP -#undef PIN_INPUT_PULLDOWN - -#define PIN_OUTPUT (PULL_DISABLE) -#define PIN_OUTPUT_PULLUP (PULL_UP) -#define PIN_OUTPUT_PULLDOWN 0 -#define PIN_INPUT (INPUT_EN | PULL_DISABLE) -#define PIN_INPUT_PULLUP (INPUT_EN | PULL_UP) -#define PIN_INPUT_PULLDOWN (INPUT_EN) - -/* undef non-existing modes */ -#undef PIN_OFF_NONE -#undef PIN_OFF_OUTPUT_HIGH -#undef PIN_OFF_OUTPUT_LOW -#undef PIN_OFF_INPUT_PULLUP -#undef PIN_OFF_INPUT_PULLDOWN -#undef PIN_OFF_WAKEUPENABLE - -#endif - diff --git a/sys/gnu/dts/include/dt-bindings/pinctrl/dra.h b/sys/gnu/dts/include/dt-bindings/pinctrl/dra.h deleted file mode 100644 index 252cdfd0d83..00000000000 --- a/sys/gnu/dts/include/dt-bindings/pinctrl/dra.h +++ /dev/null @@ -1,77 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * This header provides constants for DRA pinctrl bindings. - * - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ - * Author: Rajendra Nayak - */ - -#ifndef _DT_BINDINGS_PINCTRL_DRA_H -#define _DT_BINDINGS_PINCTRL_DRA_H - -/* DRA7 mux mode options for each pin. See TRM for options */ -#define MUX_MODE0 0x0 -#define MUX_MODE1 0x1 -#define MUX_MODE2 0x2 -#define MUX_MODE3 0x3 -#define MUX_MODE4 0x4 -#define MUX_MODE5 0x5 -#define MUX_MODE6 0x6 -#define MUX_MODE7 0x7 -#define MUX_MODE8 0x8 -#define MUX_MODE9 0x9 -#define MUX_MODE10 0xa -#define MUX_MODE11 0xb -#define MUX_MODE12 0xc -#define MUX_MODE13 0xd -#define MUX_MODE14 0xe -#define MUX_MODE15 0xf - -/* Certain pins need virtual mode, but note: they may glitch */ -#define MUX_VIRTUAL_MODE0 (MODE_SELECT | (0x0 << 4)) -#define MUX_VIRTUAL_MODE1 (MODE_SELECT | (0x1 << 4)) -#define MUX_VIRTUAL_MODE2 (MODE_SELECT | (0x2 << 4)) -#define MUX_VIRTUAL_MODE3 (MODE_SELECT | (0x3 << 4)) -#define MUX_VIRTUAL_MODE4 (MODE_SELECT | (0x4 << 4)) -#define MUX_VIRTUAL_MODE5 (MODE_SELECT | (0x5 << 4)) -#define MUX_VIRTUAL_MODE6 (MODE_SELECT | (0x6 << 4)) -#define MUX_VIRTUAL_MODE7 (MODE_SELECT | (0x7 << 4)) -#define MUX_VIRTUAL_MODE8 (MODE_SELECT | (0x8 << 4)) -#define MUX_VIRTUAL_MODE9 (MODE_SELECT | (0x9 << 4)) -#define MUX_VIRTUAL_MODE10 (MODE_SELECT | (0xa << 4)) -#define MUX_VIRTUAL_MODE11 (MODE_SELECT | (0xb << 4)) -#define MUX_VIRTUAL_MODE12 (MODE_SELECT | (0xc << 4)) -#define MUX_VIRTUAL_MODE13 (MODE_SELECT | (0xd << 4)) -#define MUX_VIRTUAL_MODE14 (MODE_SELECT | (0xe << 4)) -#define MUX_VIRTUAL_MODE15 (MODE_SELECT | (0xf << 4)) - -#define MODE_SELECT (1 << 8) - -#define PULL_ENA (0 << 16) -#define PULL_DIS (1 << 16) -#define PULL_UP (1 << 17) -#define INPUT_EN (1 << 18) -#define SLEWCONTROL (1 << 19) -#define WAKEUP_EN (1 << 24) -#define WAKEUP_EVENT (1 << 25) - -/* Active pin states */ -#define PIN_OUTPUT (0 | PULL_DIS) -#define PIN_OUTPUT_PULLUP (PULL_UP) -#define PIN_OUTPUT_PULLDOWN (0) -#define PIN_INPUT (INPUT_EN | PULL_DIS) -#define PIN_INPUT_SLEW (INPUT_EN | SLEWCONTROL) -#define PIN_INPUT_PULLUP (PULL_ENA | INPUT_EN | PULL_UP) -#define PIN_INPUT_PULLDOWN (PULL_ENA | INPUT_EN) - -/* - * Macro to allow using the absolute physical address instead of the - * padconf registers instead of the offset from padconf base. - */ -#define DRA7XX_CORE_IOPAD(pa, val) (((pa) & 0xffff) - 0x3400) (val) - -/* DRA7 IODELAY configuration parameters */ -#define A_DELAY_PS(val) ((val) & 0xffff) -#define G_DELAY_PS(val) ((val) & 0xffff) -#endif - diff --git a/sys/gnu/dts/include/dt-bindings/pinctrl/hisi.h b/sys/gnu/dts/include/dt-bindings/pinctrl/hisi.h deleted file mode 100644 index 0359bfdc911..00000000000 --- a/sys/gnu/dts/include/dt-bindings/pinctrl/hisi.h +++ /dev/null @@ -1,74 +0,0 @@ -/* - * This header provides constants for hisilicon pinctrl bindings. - * - * Copyright (c) 2015 Hisilicon Limited. - * Copyright (c) 2015 Linaro Limited. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _DT_BINDINGS_PINCTRL_HISI_H -#define _DT_BINDINGS_PINCTRL_HISI_H - -/* iomg bit definition */ -#define MUX_M0 0 -#define MUX_M1 1 -#define MUX_M2 2 -#define MUX_M3 3 -#define MUX_M4 4 -#define MUX_M5 5 -#define MUX_M6 6 -#define MUX_M7 7 - -/* iocg bit definition */ -#define PULL_MASK (3) -#define PULL_DIS (0) -#define PULL_UP (1 << 0) -#define PULL_DOWN (1 << 1) - -/* drive strength definition */ -#define DRIVE_MASK (7 << 4) -#define DRIVE1_02MA (0 << 4) -#define DRIVE1_04MA (1 << 4) -#define DRIVE1_08MA (2 << 4) -#define DRIVE1_10MA (3 << 4) -#define DRIVE2_02MA (0 << 4) -#define DRIVE2_04MA (1 << 4) -#define DRIVE2_08MA (2 << 4) -#define DRIVE2_10MA (3 << 4) -#define DRIVE3_04MA (0 << 4) -#define DRIVE3_08MA (1 << 4) -#define DRIVE3_12MA (2 << 4) -#define DRIVE3_16MA (3 << 4) -#define DRIVE3_20MA (4 << 4) -#define DRIVE3_24MA (5 << 4) -#define DRIVE3_32MA (6 << 4) -#define DRIVE3_40MA (7 << 4) -#define DRIVE4_02MA (0 << 4) -#define DRIVE4_04MA (2 << 4) -#define DRIVE4_08MA (4 << 4) -#define DRIVE4_10MA (6 << 4) - -/* drive strength definition for hi3660 */ -#define DRIVE6_MASK (15 << 4) -#define DRIVE6_04MA (0 << 4) -#define DRIVE6_12MA (4 << 4) -#define DRIVE6_19MA (8 << 4) -#define DRIVE6_27MA (10 << 4) -#define DRIVE6_32MA (15 << 4) -#define DRIVE7_02MA (0 << 4) -#define DRIVE7_04MA (1 << 4) -#define DRIVE7_06MA (2 << 4) -#define DRIVE7_08MA (3 << 4) -#define DRIVE7_10MA (4 << 4) -#define DRIVE7_12MA (5 << 4) -#define DRIVE7_14MA (6 << 4) -#define DRIVE7_16MA (7 << 4) -#endif diff --git a/sys/gnu/dts/include/dt-bindings/pinctrl/k3.h b/sys/gnu/dts/include/dt-bindings/pinctrl/k3.h deleted file mode 100644 index 499de621658..00000000000 --- a/sys/gnu/dts/include/dt-bindings/pinctrl/k3.h +++ /dev/null @@ -1,38 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides constants for pinctrl bindings for TI's K3 SoC - * family. - * - * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ - */ -#ifndef _DT_BINDINGS_PINCTRL_TI_K3_H -#define _DT_BINDINGS_PINCTRL_TI_K3_H - -#define PULLUDEN_SHIFT (16) -#define PULLTYPESEL_SHIFT (17) -#define RXACTIVE_SHIFT (18) - -#define PULL_DISABLE (1 << PULLUDEN_SHIFT) -#define PULL_ENABLE (0 << PULLUDEN_SHIFT) - -#define PULL_UP (1 << PULLTYPESEL_SHIFT | PULL_ENABLE) -#define PULL_DOWN (0 << PULLTYPESEL_SHIFT | PULL_ENABLE) - -#define INPUT_EN (1 << RXACTIVE_SHIFT) -#define INPUT_DISABLE (0 << RXACTIVE_SHIFT) - -/* Only these macros are expected be used directly in device tree files */ -#define PIN_OUTPUT (INPUT_DISABLE | PULL_DISABLE) -#define PIN_OUTPUT_PULLUP (INPUT_DISABLE | PULL_UP) -#define PIN_OUTPUT_PULLDOWN (INPUT_DISABLE | PULL_DOWN) -#define PIN_INPUT (INPUT_EN | PULL_DISABLE) -#define PIN_INPUT_PULLUP (INPUT_EN | PULL_UP) -#define PIN_INPUT_PULLDOWN (INPUT_EN | PULL_DOWN) - -#define AM65X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) -#define AM65X_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) - -#define J721E_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) -#define J721E_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/pinctrl/keystone.h b/sys/gnu/dts/include/dt-bindings/pinctrl/keystone.h deleted file mode 100644 index 7f97d776a8f..00000000000 --- a/sys/gnu/dts/include/dt-bindings/pinctrl/keystone.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * This header provides constants for Keystone pinctrl bindings. - * - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _DT_BINDINGS_PINCTRL_KEYSTONE_H -#define _DT_BINDINGS_PINCTRL_KEYSTONE_H - -#define MUX_MODE0 0 -#define MUX_MODE1 1 -#define MUX_MODE2 2 -#define MUX_MODE3 3 -#define MUX_MODE4 4 -#define MUX_MODE5 5 - -#define BUFFER_CLASS_B (0 << 19) -#define BUFFER_CLASS_C (1 << 19) -#define BUFFER_CLASS_D (2 << 19) -#define BUFFER_CLASS_E (3 << 19) - -#define PULL_DISABLE (1 << 16) -#define PIN_PULLUP (1 << 17) -#define PIN_PULLDOWN (0 << 17) - -#define KEYSTONE_IOPAD_OFFSET(pa, offset) (((pa) & 0xffff) - (offset)) - -#define K2G_CORE_IOPAD(pa) KEYSTONE_IOPAD_OFFSET((pa), 0x1000) - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/pinctrl/lochnagar.h b/sys/gnu/dts/include/dt-bindings/pinctrl/lochnagar.h deleted file mode 100644 index 644760bf572..00000000000 --- a/sys/gnu/dts/include/dt-bindings/pinctrl/lochnagar.h +++ /dev/null @@ -1,132 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Device Tree defines for Lochnagar pinctrl - * - * Copyright (c) 2018 Cirrus Logic, Inc. and - * Cirrus Logic International Semiconductor Ltd. - * - * Author: Charles Keepax - */ - -#ifndef DT_BINDINGS_PINCTRL_LOCHNAGAR_H -#define DT_BINDINGS_PINCTRL_LOCHNAGAR_H - -#define LOCHNAGAR1_PIN_CDC_RESET 0 -#define LOCHNAGAR1_PIN_DSP_RESET 1 -#define LOCHNAGAR1_PIN_CDC_CIF1MODE 2 -#define LOCHNAGAR1_PIN_NUM_GPIOS 3 - -#define LOCHNAGAR2_PIN_CDC_RESET 0 -#define LOCHNAGAR2_PIN_DSP_RESET 1 -#define LOCHNAGAR2_PIN_CDC_CIF1MODE 2 -#define LOCHNAGAR2_PIN_CDC_LDOENA 3 -#define LOCHNAGAR2_PIN_SPDIF_HWMODE 4 -#define LOCHNAGAR2_PIN_SPDIF_RESET 5 -#define LOCHNAGAR2_PIN_FPGA_GPIO1 6 -#define LOCHNAGAR2_PIN_FPGA_GPIO2 7 -#define LOCHNAGAR2_PIN_FPGA_GPIO3 8 -#define LOCHNAGAR2_PIN_FPGA_GPIO4 9 -#define LOCHNAGAR2_PIN_FPGA_GPIO5 10 -#define LOCHNAGAR2_PIN_FPGA_GPIO6 11 -#define LOCHNAGAR2_PIN_CDC_GPIO1 12 -#define LOCHNAGAR2_PIN_CDC_GPIO2 13 -#define LOCHNAGAR2_PIN_CDC_GPIO3 14 -#define LOCHNAGAR2_PIN_CDC_GPIO4 15 -#define LOCHNAGAR2_PIN_CDC_GPIO5 16 -#define LOCHNAGAR2_PIN_CDC_GPIO6 17 -#define LOCHNAGAR2_PIN_CDC_GPIO7 18 -#define LOCHNAGAR2_PIN_CDC_GPIO8 19 -#define LOCHNAGAR2_PIN_DSP_GPIO1 20 -#define LOCHNAGAR2_PIN_DSP_GPIO2 21 -#define LOCHNAGAR2_PIN_DSP_GPIO3 22 -#define LOCHNAGAR2_PIN_DSP_GPIO4 23 -#define LOCHNAGAR2_PIN_DSP_GPIO5 24 -#define LOCHNAGAR2_PIN_DSP_GPIO6 25 -#define LOCHNAGAR2_PIN_GF_GPIO2 26 -#define LOCHNAGAR2_PIN_GF_GPIO3 27 -#define LOCHNAGAR2_PIN_GF_GPIO7 28 -#define LOCHNAGAR2_PIN_CDC_AIF1_BCLK 29 -#define LOCHNAGAR2_PIN_CDC_AIF1_RXDAT 30 -#define LOCHNAGAR2_PIN_CDC_AIF1_LRCLK 31 -#define LOCHNAGAR2_PIN_CDC_AIF1_TXDAT 32 -#define LOCHNAGAR2_PIN_CDC_AIF2_BCLK 33 -#define LOCHNAGAR2_PIN_CDC_AIF2_RXDAT 34 -#define LOCHNAGAR2_PIN_CDC_AIF2_LRCLK 35 -#define LOCHNAGAR2_PIN_CDC_AIF2_TXDAT 36 -#define LOCHNAGAR2_PIN_CDC_AIF3_BCLK 37 -#define LOCHNAGAR2_PIN_CDC_AIF3_RXDAT 38 -#define LOCHNAGAR2_PIN_CDC_AIF3_LRCLK 39 -#define LOCHNAGAR2_PIN_CDC_AIF3_TXDAT 40 -#define LOCHNAGAR2_PIN_DSP_AIF1_BCLK 41 -#define LOCHNAGAR2_PIN_DSP_AIF1_RXDAT 42 -#define LOCHNAGAR2_PIN_DSP_AIF1_LRCLK 43 -#define LOCHNAGAR2_PIN_DSP_AIF1_TXDAT 44 -#define LOCHNAGAR2_PIN_DSP_AIF2_BCLK 45 -#define LOCHNAGAR2_PIN_DSP_AIF2_RXDAT 46 -#define LOCHNAGAR2_PIN_DSP_AIF2_LRCLK 47 -#define LOCHNAGAR2_PIN_DSP_AIF2_TXDAT 48 -#define LOCHNAGAR2_PIN_PSIA1_BCLK 49 -#define LOCHNAGAR2_PIN_PSIA1_RXDAT 50 -#define LOCHNAGAR2_PIN_PSIA1_LRCLK 51 -#define LOCHNAGAR2_PIN_PSIA1_TXDAT 52 -#define LOCHNAGAR2_PIN_PSIA2_BCLK 53 -#define LOCHNAGAR2_PIN_PSIA2_RXDAT 54 -#define LOCHNAGAR2_PIN_PSIA2_LRCLK 55 -#define LOCHNAGAR2_PIN_PSIA2_TXDAT 56 -#define LOCHNAGAR2_PIN_GF_AIF3_BCLK 57 -#define LOCHNAGAR2_PIN_GF_AIF3_RXDAT 58 -#define LOCHNAGAR2_PIN_GF_AIF3_LRCLK 59 -#define LOCHNAGAR2_PIN_GF_AIF3_TXDAT 60 -#define LOCHNAGAR2_PIN_GF_AIF4_BCLK 61 -#define LOCHNAGAR2_PIN_GF_AIF4_RXDAT 62 -#define LOCHNAGAR2_PIN_GF_AIF4_LRCLK 63 -#define LOCHNAGAR2_PIN_GF_AIF4_TXDAT 64 -#define LOCHNAGAR2_PIN_GF_AIF1_BCLK 65 -#define LOCHNAGAR2_PIN_GF_AIF1_RXDAT 66 -#define LOCHNAGAR2_PIN_GF_AIF1_LRCLK 67 -#define LOCHNAGAR2_PIN_GF_AIF1_TXDAT 68 -#define LOCHNAGAR2_PIN_GF_AIF2_BCLK 69 -#define LOCHNAGAR2_PIN_GF_AIF2_RXDAT 70 -#define LOCHNAGAR2_PIN_GF_AIF2_LRCLK 71 -#define LOCHNAGAR2_PIN_GF_AIF2_TXDAT 72 -#define LOCHNAGAR2_PIN_DSP_UART1_RX 73 -#define LOCHNAGAR2_PIN_DSP_UART1_TX 74 -#define LOCHNAGAR2_PIN_DSP_UART2_RX 75 -#define LOCHNAGAR2_PIN_DSP_UART2_TX 76 -#define LOCHNAGAR2_PIN_GF_UART2_RX 77 -#define LOCHNAGAR2_PIN_GF_UART2_TX 78 -#define LOCHNAGAR2_PIN_USB_UART_RX 79 -#define LOCHNAGAR2_PIN_CDC_PDMCLK1 80 -#define LOCHNAGAR2_PIN_CDC_PDMDAT1 81 -#define LOCHNAGAR2_PIN_CDC_PDMCLK2 82 -#define LOCHNAGAR2_PIN_CDC_PDMDAT2 83 -#define LOCHNAGAR2_PIN_CDC_DMICCLK1 84 -#define LOCHNAGAR2_PIN_CDC_DMICDAT1 85 -#define LOCHNAGAR2_PIN_CDC_DMICCLK2 86 -#define LOCHNAGAR2_PIN_CDC_DMICDAT2 87 -#define LOCHNAGAR2_PIN_CDC_DMICCLK3 88 -#define LOCHNAGAR2_PIN_CDC_DMICDAT3 89 -#define LOCHNAGAR2_PIN_CDC_DMICCLK4 90 -#define LOCHNAGAR2_PIN_CDC_DMICDAT4 91 -#define LOCHNAGAR2_PIN_DSP_DMICCLK1 92 -#define LOCHNAGAR2_PIN_DSP_DMICDAT1 93 -#define LOCHNAGAR2_PIN_DSP_DMICCLK2 94 -#define LOCHNAGAR2_PIN_DSP_DMICDAT2 95 -#define LOCHNAGAR2_PIN_I2C2_SCL 96 -#define LOCHNAGAR2_PIN_I2C2_SDA 97 -#define LOCHNAGAR2_PIN_I2C3_SCL 98 -#define LOCHNAGAR2_PIN_I2C3_SDA 99 -#define LOCHNAGAR2_PIN_I2C4_SCL 100 -#define LOCHNAGAR2_PIN_I2C4_SDA 101 -#define LOCHNAGAR2_PIN_DSP_STANDBY 102 -#define LOCHNAGAR2_PIN_CDC_MCLK1 103 -#define LOCHNAGAR2_PIN_CDC_MCLK2 104 -#define LOCHNAGAR2_PIN_DSP_CLKIN 105 -#define LOCHNAGAR2_PIN_PSIA1_MCLK 106 -#define LOCHNAGAR2_PIN_PSIA2_MCLK 107 -#define LOCHNAGAR2_PIN_GF_GPIO1 108 -#define LOCHNAGAR2_PIN_GF_GPIO5 109 -#define LOCHNAGAR2_PIN_DSP_GPIO20 110 -#define LOCHNAGAR2_PIN_NUM_GPIOS 111 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/pinctrl/mt6397-pinfunc.h b/sys/gnu/dts/include/dt-bindings/pinctrl/mt6397-pinfunc.h deleted file mode 100644 index f393fbd6890..00000000000 --- a/sys/gnu/dts/include/dt-bindings/pinctrl/mt6397-pinfunc.h +++ /dev/null @@ -1,257 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __DTS_MT6397_PINFUNC_H -#define __DTS_MT6397_PINFUNC_H - -#include - -#define MT6397_PIN_0_INT__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) -#define MT6397_PIN_0_INT__FUNC_INT (MTK_PIN_NO(0) | 1) - -#define MT6397_PIN_1_SRCVOLTEN__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) -#define MT6397_PIN_1_SRCVOLTEN__FUNC_SRCVOLTEN (MTK_PIN_NO(1) | 1) -#define MT6397_PIN_1_SRCVOLTEN__FUNC_TEST_CK1 (MTK_PIN_NO(1) | 6) - -#define MT6397_PIN_2_SRCLKEN_PERI__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) -#define MT6397_PIN_2_SRCLKEN_PERI__FUNC_SRCLKEN_PERI (MTK_PIN_NO(2) | 1) -#define MT6397_PIN_2_SRCLKEN_PERI__FUNC_TEST_CK2 (MTK_PIN_NO(2) | 6) - -#define MT6397_PIN_3_RTC_32K1V8__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) -#define MT6397_PIN_3_RTC_32K1V8__FUNC_RTC_32K1V8 (MTK_PIN_NO(3) | 1) -#define MT6397_PIN_3_RTC_32K1V8__FUNC_TEST_CK3 (MTK_PIN_NO(3) | 6) - -#define MT6397_PIN_4_WRAP_EVENT__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) -#define MT6397_PIN_4_WRAP_EVENT__FUNC_WRAP_EVENT (MTK_PIN_NO(4) | 1) - -#define MT6397_PIN_5_SPI_CLK__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) -#define MT6397_PIN_5_SPI_CLK__FUNC_SPI_CLK (MTK_PIN_NO(5) | 1) - -#define MT6397_PIN_6_SPI_CSN__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) -#define MT6397_PIN_6_SPI_CSN__FUNC_SPI_CSN (MTK_PIN_NO(6) | 1) - -#define MT6397_PIN_7_SPI_MOSI__FUNC_GPIO7 (MTK_PIN_NO(7) | 0) -#define MT6397_PIN_7_SPI_MOSI__FUNC_SPI_MOSI (MTK_PIN_NO(7) | 1) - -#define MT6397_PIN_8_SPI_MISO__FUNC_GPIO8 (MTK_PIN_NO(8) | 0) -#define MT6397_PIN_8_SPI_MISO__FUNC_SPI_MISO (MTK_PIN_NO(8) | 1) - -#define MT6397_PIN_9_AUD_CLK_MOSI__FUNC_GPIO9 (MTK_PIN_NO(9) | 0) -#define MT6397_PIN_9_AUD_CLK_MOSI__FUNC_AUD_CLK (MTK_PIN_NO(9) | 1) -#define MT6397_PIN_9_AUD_CLK_MOSI__FUNC_TEST_IN0 (MTK_PIN_NO(9) | 6) -#define MT6397_PIN_9_AUD_CLK_MOSI__FUNC_TEST_OUT0 (MTK_PIN_NO(9) | 7) - -#define MT6397_PIN_10_AUD_DAT_MISO__FUNC_GPIO10 (MTK_PIN_NO(10) | 0) -#define MT6397_PIN_10_AUD_DAT_MISO__FUNC_AUD_MISO (MTK_PIN_NO(10) | 1) -#define MT6397_PIN_10_AUD_DAT_MISO__FUNC_TEST_IN1 (MTK_PIN_NO(10) | 6) -#define MT6397_PIN_10_AUD_DAT_MISO__FUNC_TEST_OUT1 (MTK_PIN_NO(10) | 7) - -#define MT6397_PIN_11_AUD_DAT_MOSI__FUNC_GPIO11 (MTK_PIN_NO(11) | 0) -#define MT6397_PIN_11_AUD_DAT_MOSI__FUNC_AUD_MOSI (MTK_PIN_NO(11) | 1) -#define MT6397_PIN_11_AUD_DAT_MOSI__FUNC_TEST_IN2 (MTK_PIN_NO(11) | 6) -#define MT6397_PIN_11_AUD_DAT_MOSI__FUNC_TEST_OUT2 (MTK_PIN_NO(11) | 7) - -#define MT6397_PIN_12_COL0__FUNC_GPIO12 (MTK_PIN_NO(12) | 0) -#define MT6397_PIN_12_COL0__FUNC_COL0_USBDL (MTK_PIN_NO(12) | 1) -#define MT6397_PIN_12_COL0__FUNC_EINT10_1X (MTK_PIN_NO(12) | 2) -#define MT6397_PIN_12_COL0__FUNC_PWM1_3X (MTK_PIN_NO(12) | 3) -#define MT6397_PIN_12_COL0__FUNC_TEST_IN3 (MTK_PIN_NO(12) | 6) -#define MT6397_PIN_12_COL0__FUNC_TEST_OUT3 (MTK_PIN_NO(12) | 7) - -#define MT6397_PIN_13_COL1__FUNC_GPIO13 (MTK_PIN_NO(13) | 0) -#define MT6397_PIN_13_COL1__FUNC_COL1 (MTK_PIN_NO(13) | 1) -#define MT6397_PIN_13_COL1__FUNC_EINT11_1X (MTK_PIN_NO(13) | 2) -#define MT6397_PIN_13_COL1__FUNC_SCL0_2X (MTK_PIN_NO(13) | 3) -#define MT6397_PIN_13_COL1__FUNC_TEST_IN4 (MTK_PIN_NO(13) | 6) -#define MT6397_PIN_13_COL1__FUNC_TEST_OUT4 (MTK_PIN_NO(13) | 7) - -#define MT6397_PIN_14_COL2__FUNC_GPIO14 (MTK_PIN_NO(14) | 0) -#define MT6397_PIN_14_COL2__FUNC_COL2 (MTK_PIN_NO(14) | 1) -#define MT6397_PIN_14_COL2__FUNC_EINT12_1X (MTK_PIN_NO(14) | 2) -#define MT6397_PIN_14_COL2__FUNC_SDA0_2X (MTK_PIN_NO(14) | 3) -#define MT6397_PIN_14_COL2__FUNC_TEST_IN5 (MTK_PIN_NO(14) | 6) -#define MT6397_PIN_14_COL2__FUNC_TEST_OUT5 (MTK_PIN_NO(14) | 7) - -#define MT6397_PIN_15_COL3__FUNC_GPIO15 (MTK_PIN_NO(15) | 0) -#define MT6397_PIN_15_COL3__FUNC_COL3 (MTK_PIN_NO(15) | 1) -#define MT6397_PIN_15_COL3__FUNC_EINT13_1X (MTK_PIN_NO(15) | 2) -#define MT6397_PIN_15_COL3__FUNC_SCL1_2X (MTK_PIN_NO(15) | 3) -#define MT6397_PIN_15_COL3__FUNC_TEST_IN6 (MTK_PIN_NO(15) | 6) -#define MT6397_PIN_15_COL3__FUNC_TEST_OUT6 (MTK_PIN_NO(15) | 7) - -#define MT6397_PIN_16_COL4__FUNC_GPIO16 (MTK_PIN_NO(16) | 0) -#define MT6397_PIN_16_COL4__FUNC_COL4 (MTK_PIN_NO(16) | 1) -#define MT6397_PIN_16_COL4__FUNC_EINT14_1X (MTK_PIN_NO(16) | 2) -#define MT6397_PIN_16_COL4__FUNC_SDA1_2X (MTK_PIN_NO(16) | 3) -#define MT6397_PIN_16_COL4__FUNC_TEST_IN7 (MTK_PIN_NO(16) | 6) -#define MT6397_PIN_16_COL4__FUNC_TEST_OUT7 (MTK_PIN_NO(16) | 7) - -#define MT6397_PIN_17_COL5__FUNC_GPIO17 (MTK_PIN_NO(17) | 0) -#define MT6397_PIN_17_COL5__FUNC_COL5 (MTK_PIN_NO(17) | 1) -#define MT6397_PIN_17_COL5__FUNC_EINT15_1X (MTK_PIN_NO(17) | 2) -#define MT6397_PIN_17_COL5__FUNC_SCL2_2X (MTK_PIN_NO(17) | 3) -#define MT6397_PIN_17_COL5__FUNC_TEST_IN8 (MTK_PIN_NO(17) | 6) -#define MT6397_PIN_17_COL5__FUNC_TEST_OUT8 (MTK_PIN_NO(17) | 7) - -#define MT6397_PIN_18_COL6__FUNC_GPIO18 (MTK_PIN_NO(18) | 0) -#define MT6397_PIN_18_COL6__FUNC_COL6 (MTK_PIN_NO(18) | 1) -#define MT6397_PIN_18_COL6__FUNC_EINT16_1X (MTK_PIN_NO(18) | 2) -#define MT6397_PIN_18_COL6__FUNC_SDA2_2X (MTK_PIN_NO(18) | 3) -#define MT6397_PIN_18_COL6__FUNC_GPIO32K_0 (MTK_PIN_NO(18) | 4) -#define MT6397_PIN_18_COL6__FUNC_GPIO26M_0 (MTK_PIN_NO(18) | 5) -#define MT6397_PIN_18_COL6__FUNC_TEST_IN9 (MTK_PIN_NO(18) | 6) -#define MT6397_PIN_18_COL6__FUNC_TEST_OUT9 (MTK_PIN_NO(18) | 7) - -#define MT6397_PIN_19_COL7__FUNC_GPIO19 (MTK_PIN_NO(19) | 0) -#define MT6397_PIN_19_COL7__FUNC_COL7 (MTK_PIN_NO(19) | 1) -#define MT6397_PIN_19_COL7__FUNC_EINT17_1X (MTK_PIN_NO(19) | 2) -#define MT6397_PIN_19_COL7__FUNC_PWM2_3X (MTK_PIN_NO(19) | 3) -#define MT6397_PIN_19_COL7__FUNC_GPIO32K_1 (MTK_PIN_NO(19) | 4) -#define MT6397_PIN_19_COL7__FUNC_GPIO26M_1 (MTK_PIN_NO(19) | 5) -#define MT6397_PIN_19_COL7__FUNC_TEST_IN10 (MTK_PIN_NO(19) | 6) -#define MT6397_PIN_19_COL7__FUNC_TEST_OUT10 (MTK_PIN_NO(19) | 7) - -#define MT6397_PIN_20_ROW0__FUNC_GPIO20 (MTK_PIN_NO(20) | 0) -#define MT6397_PIN_20_ROW0__FUNC_ROW0 (MTK_PIN_NO(20) | 1) -#define MT6397_PIN_20_ROW0__FUNC_EINT18_1X (MTK_PIN_NO(20) | 2) -#define MT6397_PIN_20_ROW0__FUNC_SCL0_3X (MTK_PIN_NO(20) | 3) -#define MT6397_PIN_20_ROW0__FUNC_TEST_IN11 (MTK_PIN_NO(20) | 6) -#define MT6397_PIN_20_ROW0__FUNC_TEST_OUT11 (MTK_PIN_NO(20) | 7) - -#define MT6397_PIN_21_ROW1__FUNC_GPIO21 (MTK_PIN_NO(21) | 0) -#define MT6397_PIN_21_ROW1__FUNC_ROW1 (MTK_PIN_NO(21) | 1) -#define MT6397_PIN_21_ROW1__FUNC_EINT19_1X (MTK_PIN_NO(21) | 2) -#define MT6397_PIN_21_ROW1__FUNC_SDA0_3X (MTK_PIN_NO(21) | 3) -#define MT6397_PIN_21_ROW1__FUNC_AUD_TSTCK (MTK_PIN_NO(21) | 4) -#define MT6397_PIN_21_ROW1__FUNC_TEST_IN12 (MTK_PIN_NO(21) | 6) -#define MT6397_PIN_21_ROW1__FUNC_TEST_OUT12 (MTK_PIN_NO(21) | 7) - -#define MT6397_PIN_22_ROW2__FUNC_GPIO22 (MTK_PIN_NO(22) | 0) -#define MT6397_PIN_22_ROW2__FUNC_ROW2 (MTK_PIN_NO(22) | 1) -#define MT6397_PIN_22_ROW2__FUNC_EINT20_1X (MTK_PIN_NO(22) | 2) -#define MT6397_PIN_22_ROW2__FUNC_SCL1_3X (MTK_PIN_NO(22) | 3) -#define MT6397_PIN_22_ROW2__FUNC_TEST_IN13 (MTK_PIN_NO(22) | 6) -#define MT6397_PIN_22_ROW2__FUNC_TEST_OUT13 (MTK_PIN_NO(22) | 7) - -#define MT6397_PIN_23_ROW3__FUNC_GPIO23 (MTK_PIN_NO(23) | 0) -#define MT6397_PIN_23_ROW3__FUNC_ROW3 (MTK_PIN_NO(23) | 1) -#define MT6397_PIN_23_ROW3__FUNC_EINT21_1X (MTK_PIN_NO(23) | 2) -#define MT6397_PIN_23_ROW3__FUNC_SDA1_3X (MTK_PIN_NO(23) | 3) -#define MT6397_PIN_23_ROW3__FUNC_TEST_IN14 (MTK_PIN_NO(23) | 6) -#define MT6397_PIN_23_ROW3__FUNC_TEST_OUT14 (MTK_PIN_NO(23) | 7) - -#define MT6397_PIN_24_ROW4__FUNC_GPIO24 (MTK_PIN_NO(24) | 0) -#define MT6397_PIN_24_ROW4__FUNC_ROW4 (MTK_PIN_NO(24) | 1) -#define MT6397_PIN_24_ROW4__FUNC_EINT22_1X (MTK_PIN_NO(24) | 2) -#define MT6397_PIN_24_ROW4__FUNC_SCL2_3X (MTK_PIN_NO(24) | 3) -#define MT6397_PIN_24_ROW4__FUNC_TEST_IN15 (MTK_PIN_NO(24) | 6) -#define MT6397_PIN_24_ROW4__FUNC_TEST_OUT15 (MTK_PIN_NO(24) | 7) - -#define MT6397_PIN_25_ROW5__FUNC_GPIO25 (MTK_PIN_NO(25) | 0) -#define MT6397_PIN_25_ROW5__FUNC_ROW5 (MTK_PIN_NO(25) | 1) -#define MT6397_PIN_25_ROW5__FUNC_EINT23_1X (MTK_PIN_NO(25) | 2) -#define MT6397_PIN_25_ROW5__FUNC_SDA2_3X (MTK_PIN_NO(25) | 3) -#define MT6397_PIN_25_ROW5__FUNC_TEST_IN16 (MTK_PIN_NO(25) | 6) -#define MT6397_PIN_25_ROW5__FUNC_TEST_OUT16 (MTK_PIN_NO(25) | 7) - -#define MT6397_PIN_26_ROW6__FUNC_GPIO26 (MTK_PIN_NO(26) | 0) -#define MT6397_PIN_26_ROW6__FUNC_ROW6 (MTK_PIN_NO(26) | 1) -#define MT6397_PIN_26_ROW6__FUNC_EINT24_1X (MTK_PIN_NO(26) | 2) -#define MT6397_PIN_26_ROW6__FUNC_PWM3_3X (MTK_PIN_NO(26) | 3) -#define MT6397_PIN_26_ROW6__FUNC_GPIO32K_2 (MTK_PIN_NO(26) | 4) -#define MT6397_PIN_26_ROW6__FUNC_GPIO26M_2 (MTK_PIN_NO(26) | 5) -#define MT6397_PIN_26_ROW6__FUNC_TEST_IN17 (MTK_PIN_NO(26) | 6) -#define MT6397_PIN_26_ROW6__FUNC_TEST_OUT17 (MTK_PIN_NO(26) | 7) - -#define MT6397_PIN_27_ROW7__FUNC_GPIO27 (MTK_PIN_NO(27) | 0) -#define MT6397_PIN_27_ROW7__FUNC_ROW7 (MTK_PIN_NO(27) | 1) -#define MT6397_PIN_27_ROW7__FUNC_EINT3_1X (MTK_PIN_NO(27) | 2) -#define MT6397_PIN_27_ROW7__FUNC_CBUS (MTK_PIN_NO(27) | 3) -#define MT6397_PIN_27_ROW7__FUNC_GPIO32K_3 (MTK_PIN_NO(27) | 4) -#define MT6397_PIN_27_ROW7__FUNC_GPIO26M_3 (MTK_PIN_NO(27) | 5) -#define MT6397_PIN_27_ROW7__FUNC_TEST_IN18 (MTK_PIN_NO(27) | 6) -#define MT6397_PIN_27_ROW7__FUNC_TEST_OUT18 (MTK_PIN_NO(27) | 7) - -#define MT6397_PIN_28_PWM1__FUNC_GPIO28 (MTK_PIN_NO(28) | 0) -#define MT6397_PIN_28_PWM1__FUNC_PWM1 (MTK_PIN_NO(28) | 1) -#define MT6397_PIN_28_PWM1__FUNC_EINT4_1X (MTK_PIN_NO(28) | 2) -#define MT6397_PIN_28_PWM1__FUNC_GPIO32K_4 (MTK_PIN_NO(28) | 4) -#define MT6397_PIN_28_PWM1__FUNC_GPIO26M_4 (MTK_PIN_NO(28) | 5) -#define MT6397_PIN_28_PWM1__FUNC_TEST_IN19 (MTK_PIN_NO(28) | 6) -#define MT6397_PIN_28_PWM1__FUNC_TEST_OUT19 (MTK_PIN_NO(28) | 7) - -#define MT6397_PIN_29_PWM2__FUNC_GPIO29 (MTK_PIN_NO(29) | 0) -#define MT6397_PIN_29_PWM2__FUNC_PWM2 (MTK_PIN_NO(29) | 1) -#define MT6397_PIN_29_PWM2__FUNC_EINT5_1X (MTK_PIN_NO(29) | 2) -#define MT6397_PIN_29_PWM2__FUNC_GPIO32K_5 (MTK_PIN_NO(29) | 4) -#define MT6397_PIN_29_PWM2__FUNC_GPIO26M_5 (MTK_PIN_NO(29) | 5) -#define MT6397_PIN_29_PWM2__FUNC_TEST_IN20 (MTK_PIN_NO(29) | 6) -#define MT6397_PIN_29_PWM2__FUNC_TEST_OUT20 (MTK_PIN_NO(29) | 7) - -#define MT6397_PIN_30_PWM3__FUNC_GPIO30 (MTK_PIN_NO(30) | 0) -#define MT6397_PIN_30_PWM3__FUNC_PWM3 (MTK_PIN_NO(30) | 1) -#define MT6397_PIN_30_PWM3__FUNC_EINT6_1X (MTK_PIN_NO(30) | 2) -#define MT6397_PIN_30_PWM3__FUNC_COL0 (MTK_PIN_NO(30) | 3) -#define MT6397_PIN_30_PWM3__FUNC_GPIO32K_6 (MTK_PIN_NO(30) | 4) -#define MT6397_PIN_30_PWM3__FUNC_GPIO26M_6 (MTK_PIN_NO(30) | 5) -#define MT6397_PIN_30_PWM3__FUNC_TEST_IN21 (MTK_PIN_NO(30) | 6) -#define MT6397_PIN_30_PWM3__FUNC_TEST_OUT21 (MTK_PIN_NO(30) | 7) - -#define MT6397_PIN_31_SCL0__FUNC_GPIO31 (MTK_PIN_NO(31) | 0) -#define MT6397_PIN_31_SCL0__FUNC_SCL0 (MTK_PIN_NO(31) | 1) -#define MT6397_PIN_31_SCL0__FUNC_EINT7_1X (MTK_PIN_NO(31) | 2) -#define MT6397_PIN_31_SCL0__FUNC_PWM1_2X (MTK_PIN_NO(31) | 3) -#define MT6397_PIN_31_SCL0__FUNC_TEST_IN22 (MTK_PIN_NO(31) | 6) -#define MT6397_PIN_31_SCL0__FUNC_TEST_OUT22 (MTK_PIN_NO(31) | 7) - -#define MT6397_PIN_32_SDA0__FUNC_GPIO32 (MTK_PIN_NO(32) | 0) -#define MT6397_PIN_32_SDA0__FUNC_SDA0 (MTK_PIN_NO(32) | 1) -#define MT6397_PIN_32_SDA0__FUNC_EINT8_1X (MTK_PIN_NO(32) | 2) -#define MT6397_PIN_32_SDA0__FUNC_TEST_IN23 (MTK_PIN_NO(32) | 6) -#define MT6397_PIN_32_SDA0__FUNC_TEST_OUT23 (MTK_PIN_NO(32) | 7) - -#define MT6397_PIN_33_SCL1__FUNC_GPIO33 (MTK_PIN_NO(33) | 0) -#define MT6397_PIN_33_SCL1__FUNC_SCL1 (MTK_PIN_NO(33) | 1) -#define MT6397_PIN_33_SCL1__FUNC_EINT9_1X (MTK_PIN_NO(33) | 2) -#define MT6397_PIN_33_SCL1__FUNC_PWM2_2X (MTK_PIN_NO(33) | 3) -#define MT6397_PIN_33_SCL1__FUNC_TEST_IN24 (MTK_PIN_NO(33) | 6) -#define MT6397_PIN_33_SCL1__FUNC_TEST_OUT24 (MTK_PIN_NO(33) | 7) - -#define MT6397_PIN_34_SDA1__FUNC_GPIO34 (MTK_PIN_NO(34) | 0) -#define MT6397_PIN_34_SDA1__FUNC_SDA1 (MTK_PIN_NO(34) | 1) -#define MT6397_PIN_34_SDA1__FUNC_EINT0_1X (MTK_PIN_NO(34) | 2) -#define MT6397_PIN_34_SDA1__FUNC_TEST_IN25 (MTK_PIN_NO(34) | 6) -#define MT6397_PIN_34_SDA1__FUNC_TEST_OUT25 (MTK_PIN_NO(34) | 7) - -#define MT6397_PIN_35_SCL2__FUNC_GPIO35 (MTK_PIN_NO(35) | 0) -#define MT6397_PIN_35_SCL2__FUNC_SCL2 (MTK_PIN_NO(35) | 1) -#define MT6397_PIN_35_SCL2__FUNC_EINT1_1X (MTK_PIN_NO(35) | 2) -#define MT6397_PIN_35_SCL2__FUNC_PWM3_2X (MTK_PIN_NO(35) | 3) -#define MT6397_PIN_35_SCL2__FUNC_TEST_IN26 (MTK_PIN_NO(35) | 6) -#define MT6397_PIN_35_SCL2__FUNC_TEST_OUT26 (MTK_PIN_NO(35) | 7) - -#define MT6397_PIN_36_SDA2__FUNC_GPIO36 (MTK_PIN_NO(36) | 0) -#define MT6397_PIN_36_SDA2__FUNC_SDA2 (MTK_PIN_NO(36) | 1) -#define MT6397_PIN_36_SDA2__FUNC_EINT2_1X (MTK_PIN_NO(36) | 2) -#define MT6397_PIN_36_SDA2__FUNC_TEST_IN27 (MTK_PIN_NO(36) | 6) -#define MT6397_PIN_36_SDA2__FUNC_TEST_OUT27 (MTK_PIN_NO(36) | 7) - -#define MT6397_PIN_37_HDMISD__FUNC_GPIO37 (MTK_PIN_NO(37) | 0) -#define MT6397_PIN_37_HDMISD__FUNC_HDMISD (MTK_PIN_NO(37) | 1) -#define MT6397_PIN_37_HDMISD__FUNC_TEST_IN28 (MTK_PIN_NO(37) | 6) -#define MT6397_PIN_37_HDMISD__FUNC_TEST_OUT28 (MTK_PIN_NO(37) | 7) - -#define MT6397_PIN_38_HDMISCK__FUNC_GPIO38 (MTK_PIN_NO(38) | 0) -#define MT6397_PIN_38_HDMISCK__FUNC_HDMISCK (MTK_PIN_NO(38) | 1) -#define MT6397_PIN_38_HDMISCK__FUNC_TEST_IN29 (MTK_PIN_NO(38) | 6) -#define MT6397_PIN_38_HDMISCK__FUNC_TEST_OUT29 (MTK_PIN_NO(38) | 7) - -#define MT6397_PIN_39_HTPLG__FUNC_GPIO39 (MTK_PIN_NO(39) | 0) -#define MT6397_PIN_39_HTPLG__FUNC_HTPLG (MTK_PIN_NO(39) | 1) -#define MT6397_PIN_39_HTPLG__FUNC_TEST_IN30 (MTK_PIN_NO(39) | 6) -#define MT6397_PIN_39_HTPLG__FUNC_TEST_OUT30 (MTK_PIN_NO(39) | 7) - -#define MT6397_PIN_40_CEC__FUNC_GPIO40 (MTK_PIN_NO(40) | 0) -#define MT6397_PIN_40_CEC__FUNC_CEC (MTK_PIN_NO(40) | 1) -#define MT6397_PIN_40_CEC__FUNC_TEST_IN31 (MTK_PIN_NO(40) | 6) -#define MT6397_PIN_40_CEC__FUNC_TEST_OUT31 (MTK_PIN_NO(40) | 7) - -#endif /* __DTS_MT6397_PINFUNC_H */ diff --git a/sys/gnu/dts/include/dt-bindings/pinctrl/mt65xx.h b/sys/gnu/dts/include/dt-bindings/pinctrl/mt65xx.h deleted file mode 100644 index 7e16e58fe1f..00000000000 --- a/sys/gnu/dts/include/dt-bindings/pinctrl/mt65xx.h +++ /dev/null @@ -1,32 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2014 MediaTek Inc. - * Author: Hongzhou.Yang - */ - -#ifndef _DT_BINDINGS_PINCTRL_MT65XX_H -#define _DT_BINDINGS_PINCTRL_MT65XX_H - -#define MTK_PIN_NO(x) ((x) << 8) -#define MTK_GET_PIN_NO(x) ((x) >> 8) -#define MTK_GET_PIN_FUNC(x) ((x) & 0xf) - -#define MTK_PUPD_SET_R1R0_00 100 -#define MTK_PUPD_SET_R1R0_01 101 -#define MTK_PUPD_SET_R1R0_10 102 -#define MTK_PUPD_SET_R1R0_11 103 - -#define MTK_DRIVE_2mA 2 -#define MTK_DRIVE_4mA 4 -#define MTK_DRIVE_6mA 6 -#define MTK_DRIVE_8mA 8 -#define MTK_DRIVE_10mA 10 -#define MTK_DRIVE_12mA 12 -#define MTK_DRIVE_14mA 14 -#define MTK_DRIVE_16mA 16 -#define MTK_DRIVE_20mA 20 -#define MTK_DRIVE_24mA 24 -#define MTK_DRIVE_28mA 28 -#define MTK_DRIVE_32mA 32 - -#endif /* _DT_BINDINGS_PINCTRL_MT65XX_H */ diff --git a/sys/gnu/dts/include/dt-bindings/pinctrl/mt6797-pinfunc.h b/sys/gnu/dts/include/dt-bindings/pinctrl/mt6797-pinfunc.h deleted file mode 100644 index e9813361b27..00000000000 --- a/sys/gnu/dts/include/dt-bindings/pinctrl/mt6797-pinfunc.h +++ /dev/null @@ -1,1368 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __DTS_MT6797_PINFUNC_H -#define __DTS_MT6797_PINFUNC_H - -#include - -#define MT6797_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) -#define MT6797_GPIO0__FUNC_CSI0A_L0P_T0A (MTK_PIN_NO(0) | 1) - -#define MT6797_GPIO1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) -#define MT6797_GPIO1__FUNC_CSI0A_L0N_T0B (MTK_PIN_NO(1) | 1) - -#define MT6797_GPIO2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) -#define MT6797_GPIO2__FUNC_CSI0A_L1P_T0C (MTK_PIN_NO(2) | 1) - -#define MT6797_GPIO3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) -#define MT6797_GPIO3__FUNC_CSI0A_L1N_T1A (MTK_PIN_NO(3) | 1) - -#define MT6797_GPIO4__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) -#define MT6797_GPIO4__FUNC_CSI0A_L2P_T1B (MTK_PIN_NO(4) | 1) - -#define MT6797_GPIO5__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) -#define MT6797_GPIO5__FUNC_CSI0A_L2N_T1C (MTK_PIN_NO(5) | 1) - -#define MT6797_GPIO6__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) -#define MT6797_GPIO6__FUNC_CSI0B_L0P_T0A (MTK_PIN_NO(6) | 1) - -#define MT6797_GPIO7__FUNC_GPIO7 (MTK_PIN_NO(7) | 0) -#define MT6797_GPIO7__FUNC_CSI0B_L0N_T0B (MTK_PIN_NO(7) | 1) - -#define MT6797_GPIO8__FUNC_GPIO8 (MTK_PIN_NO(8) | 0) -#define MT6797_GPIO8__FUNC_CSI0B_L1P_T0C (MTK_PIN_NO(8) | 1) - -#define MT6797_GPIO9__FUNC_GPIO9 (MTK_PIN_NO(9) | 0) -#define MT6797_GPIO9__FUNC_CSI0B_L1N_T1A (MTK_PIN_NO(9) | 1) - -#define MT6797_GPIO10__FUNC_GPIO10 (MTK_PIN_NO(10) | 0) -#define MT6797_GPIO10__FUNC_CSI1A_L0P_T0A (MTK_PIN_NO(10) | 1) - -#define MT6797_GPIO11__FUNC_GPIO11 (MTK_PIN_NO(11) | 0) -#define MT6797_GPIO11__FUNC_CSI1A_L0N_T0B (MTK_PIN_NO(11) | 1) - -#define MT6797_GPIO12__FUNC_GPIO12 (MTK_PIN_NO(12) | 0) -#define MT6797_GPIO12__FUNC_CSI1A_L1P_T0C (MTK_PIN_NO(12) | 1) - -#define MT6797_GPIO13__FUNC_GPIO13 (MTK_PIN_NO(13) | 0) -#define MT6797_GPIO13__FUNC_CSI1A_L1N_T1A (MTK_PIN_NO(13) | 1) - -#define MT6797_GPIO14__FUNC_GPIO14 (MTK_PIN_NO(14) | 0) -#define MT6797_GPIO14__FUNC_CSI1A_L2P_T1B (MTK_PIN_NO(14) | 1) - -#define MT6797_GPIO15__FUNC_GPIO15 (MTK_PIN_NO(15) | 0) -#define MT6797_GPIO15__FUNC_CSI1A_L2N_T1C (MTK_PIN_NO(15) | 1) - -#define MT6797_GPIO16__FUNC_GPIO16 (MTK_PIN_NO(16) | 0) -#define MT6797_GPIO16__FUNC_CSI1B_L0P_T0A (MTK_PIN_NO(16) | 1) - -#define MT6797_GPIO17__FUNC_GPIO17 (MTK_PIN_NO(17) | 0) -#define MT6797_GPIO17__FUNC_CSI1B_L0N_T0B (MTK_PIN_NO(17) | 1) - -#define MT6797_GPIO18__FUNC_GPIO18 (MTK_PIN_NO(18) | 0) -#define MT6797_GPIO18__FUNC_CSI1B_L1P_T0C (MTK_PIN_NO(18) | 1) - -#define MT6797_GPIO19__FUNC_GPIO19 (MTK_PIN_NO(19) | 0) -#define MT6797_GPIO19__FUNC_CSI1B_L1N_T1A (MTK_PIN_NO(19) | 1) - -#define MT6797_GPIO20__FUNC_GPIO20 (MTK_PIN_NO(20) | 0) -#define MT6797_GPIO20__FUNC_CSI1B_L2P_T1B (MTK_PIN_NO(20) | 1) - -#define MT6797_GPIO21__FUNC_GPIO21 (MTK_PIN_NO(21) | 0) -#define MT6797_GPIO21__FUNC_CSI1B_L2N_T1C (MTK_PIN_NO(21) | 1) - -#define MT6797_GPIO22__FUNC_GPIO22 (MTK_PIN_NO(22) | 0) -#define MT6797_GPIO22__FUNC_CSI2_L0P_T0A (MTK_PIN_NO(22) | 1) - -#define MT6797_GPIO23__FUNC_GPIO23 (MTK_PIN_NO(23) | 0) -#define MT6797_GPIO23__FUNC_CSI2_L0N_T0B (MTK_PIN_NO(23) | 1) - -#define MT6797_GPIO24__FUNC_GPIO24 (MTK_PIN_NO(24) | 0) -#define MT6797_GPIO24__FUNC_CSI2_L1P_T0C (MTK_PIN_NO(24) | 1) - -#define MT6797_GPIO25__FUNC_GPIO25 (MTK_PIN_NO(25) | 0) -#define MT6797_GPIO25__FUNC_CSI2_L1N_T1A (MTK_PIN_NO(25) | 1) - -#define MT6797_GPIO26__FUNC_GPIO26 (MTK_PIN_NO(26) | 0) -#define MT6797_GPIO26__FUNC_CSI2_L2P_T1B (MTK_PIN_NO(26) | 1) - -#define MT6797_GPIO27__FUNC_GPIO27 (MTK_PIN_NO(27) | 0) -#define MT6797_GPIO27__FUNC_CSI2_L2N_T1C (MTK_PIN_NO(27) | 1) - -#define MT6797_GPIO28__FUNC_GPIO28 (MTK_PIN_NO(28) | 0) -#define MT6797_GPIO28__FUNC_SPI5_CLK_A (MTK_PIN_NO(28) | 1) -#define MT6797_GPIO28__FUNC_IRTX_OUT (MTK_PIN_NO(28) | 2) -#define MT6797_GPIO28__FUNC_UDI_TDO (MTK_PIN_NO(28) | 3) -#define MT6797_GPIO28__FUNC_SCP_JTAG_TDO (MTK_PIN_NO(28) | 4) -#define MT6797_GPIO28__FUNC_CONN_MCU_TDO (MTK_PIN_NO(28) | 5) -#define MT6797_GPIO28__FUNC_PWM_A (MTK_PIN_NO(28) | 6) -#define MT6797_GPIO28__FUNC_C2K_DM_OTDO (MTK_PIN_NO(28) | 7) - -#define MT6797_GPIO29__FUNC_GPIO29 (MTK_PIN_NO(29) | 0) -#define MT6797_GPIO29__FUNC_SPI5_MI_A (MTK_PIN_NO(29) | 1) -#define MT6797_GPIO29__FUNC_DAP_SIB1_SWD (MTK_PIN_NO(29) | 2) -#define MT6797_GPIO29__FUNC_UDI_TMS (MTK_PIN_NO(29) | 3) -#define MT6797_GPIO29__FUNC_SCP_JTAG_TMS (MTK_PIN_NO(29) | 4) -#define MT6797_GPIO29__FUNC_CONN_MCU_TMS (MTK_PIN_NO(29) | 5) -#define MT6797_GPIO29__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(29) | 6) -#define MT6797_GPIO29__FUNC_C2K_DM_OTMS (MTK_PIN_NO(29) | 7) - -#define MT6797_GPIO30__FUNC_GPIO30 (MTK_PIN_NO(30) | 0) -#define MT6797_GPIO30__FUNC_CMMCLK0 (MTK_PIN_NO(30) | 1) -#define MT6797_GPIO30__FUNC_MD_CLKM0 (MTK_PIN_NO(30) | 7) - -#define MT6797_GPIO31__FUNC_GPIO31 (MTK_PIN_NO(31) | 0) -#define MT6797_GPIO31__FUNC_CMMCLK1 (MTK_PIN_NO(31) | 1) -#define MT6797_GPIO31__FUNC_MD_CLKM1 (MTK_PIN_NO(31) | 7) - -#define MT6797_GPIO32__FUNC_GPIO32 (MTK_PIN_NO(32) | 0) -#define MT6797_GPIO32__FUNC_SPI5_CS_A (MTK_PIN_NO(32) | 1) -#define MT6797_GPIO32__FUNC_DAP_SIB1_SWCK (MTK_PIN_NO(32) | 2) -#define MT6797_GPIO32__FUNC_UDI_TCK_XI (MTK_PIN_NO(32) | 3) -#define MT6797_GPIO32__FUNC_SCP_JTAG_TCK (MTK_PIN_NO(32) | 4) -#define MT6797_GPIO32__FUNC_CONN_MCU_TCK (MTK_PIN_NO(32) | 5) -#define MT6797_GPIO32__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(32) | 6) -#define MT6797_GPIO32__FUNC_C2K_DM_OTCK (MTK_PIN_NO(32) | 7) - -#define MT6797_GPIO33__FUNC_GPIO33 (MTK_PIN_NO(33) | 0) -#define MT6797_GPIO33__FUNC_SPI5_MO_A (MTK_PIN_NO(33) | 1) -#define MT6797_GPIO33__FUNC_CMFLASH (MTK_PIN_NO(33) | 2) -#define MT6797_GPIO33__FUNC_UDI_TDI (MTK_PIN_NO(33) | 3) -#define MT6797_GPIO33__FUNC_SCP_JTAG_TDI (MTK_PIN_NO(33) | 4) -#define MT6797_GPIO33__FUNC_CONN_MCU_TDI (MTK_PIN_NO(33) | 5) -#define MT6797_GPIO33__FUNC_MD_URXD0 (MTK_PIN_NO(33) | 6) -#define MT6797_GPIO33__FUNC_C2K_DM_OTDI (MTK_PIN_NO(33) | 7) - -#define MT6797_GPIO34__FUNC_GPIO34 (MTK_PIN_NO(34) | 0) -#define MT6797_GPIO34__FUNC_CMFLASH (MTK_PIN_NO(34) | 1) -#define MT6797_GPIO34__FUNC_CLKM0 (MTK_PIN_NO(34) | 2) -#define MT6797_GPIO34__FUNC_UDI_NTRST (MTK_PIN_NO(34) | 3) -#define MT6797_GPIO34__FUNC_SCP_JTAG_TRSTN (MTK_PIN_NO(34) | 4) -#define MT6797_GPIO34__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(34) | 5) -#define MT6797_GPIO34__FUNC_MD_UTXD0 (MTK_PIN_NO(34) | 6) -#define MT6797_GPIO34__FUNC_C2K_DM_JTINTP (MTK_PIN_NO(34) | 7) - -#define MT6797_GPIO35__FUNC_GPIO35 (MTK_PIN_NO(35) | 0) -#define MT6797_GPIO35__FUNC_CMMCLK3 (MTK_PIN_NO(35) | 1) -#define MT6797_GPIO35__FUNC_CLKM1 (MTK_PIN_NO(35) | 2) -#define MT6797_GPIO35__FUNC_MD_URXD1 (MTK_PIN_NO(35) | 3) -#define MT6797_GPIO35__FUNC_PTA_RXD (MTK_PIN_NO(35) | 4) -#define MT6797_GPIO35__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(35) | 5) -#define MT6797_GPIO35__FUNC_PWM_B (MTK_PIN_NO(35) | 6) -#define MT6797_GPIO35__FUNC_PCC_PPC_IO (MTK_PIN_NO(35) | 7) - -#define MT6797_GPIO36__FUNC_GPIO36 (MTK_PIN_NO(36) | 0) -#define MT6797_GPIO36__FUNC_CMMCLK2 (MTK_PIN_NO(36) | 1) -#define MT6797_GPIO36__FUNC_CLKM2 (MTK_PIN_NO(36) | 2) -#define MT6797_GPIO36__FUNC_MD_UTXD1 (MTK_PIN_NO(36) | 3) -#define MT6797_GPIO36__FUNC_PTA_TXD (MTK_PIN_NO(36) | 4) -#define MT6797_GPIO36__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(36) | 5) -#define MT6797_GPIO36__FUNC_PWM_C (MTK_PIN_NO(36) | 6) -#define MT6797_GPIO36__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(36) | 7) - -#define MT6797_GPIO37__FUNC_GPIO37 (MTK_PIN_NO(37) | 0) -#define MT6797_GPIO37__FUNC_SCL0_0 (MTK_PIN_NO(37) | 1) - -#define MT6797_GPIO38__FUNC_GPIO38 (MTK_PIN_NO(38) | 0) -#define MT6797_GPIO38__FUNC_SDA0_0 (MTK_PIN_NO(38) | 1) - -#define MT6797_GPIO39__FUNC_GPIO39 (MTK_PIN_NO(39) | 0) -#define MT6797_GPIO39__FUNC_DPI_D0 (MTK_PIN_NO(39) | 1) -#define MT6797_GPIO39__FUNC_SPI1_CLK_A (MTK_PIN_NO(39) | 2) -#define MT6797_GPIO39__FUNC_PCM0_SYNC (MTK_PIN_NO(39) | 3) -#define MT6797_GPIO39__FUNC_I2S0_LRCK (MTK_PIN_NO(39) | 4) -#define MT6797_GPIO39__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(39) | 5) -#define MT6797_GPIO39__FUNC_URXD3 (MTK_PIN_NO(39) | 6) -#define MT6797_GPIO39__FUNC_C2K_NTRST (MTK_PIN_NO(39) | 7) - -#define MT6797_GPIO40__FUNC_GPIO40 (MTK_PIN_NO(40) | 0) -#define MT6797_GPIO40__FUNC_DPI_D1 (MTK_PIN_NO(40) | 1) -#define MT6797_GPIO40__FUNC_SPI1_MI_A (MTK_PIN_NO(40) | 2) -#define MT6797_GPIO40__FUNC_PCM0_CLK (MTK_PIN_NO(40) | 3) -#define MT6797_GPIO40__FUNC_I2S0_BCK (MTK_PIN_NO(40) | 4) -#define MT6797_GPIO40__FUNC_CONN_MCU_TDO (MTK_PIN_NO(40) | 5) -#define MT6797_GPIO40__FUNC_UTXD3 (MTK_PIN_NO(40) | 6) -#define MT6797_GPIO40__FUNC_C2K_TCK (MTK_PIN_NO(40) | 7) - -#define MT6797_GPIO41__FUNC_GPIO41 (MTK_PIN_NO(41) | 0) -#define MT6797_GPIO41__FUNC_DPI_D2 (MTK_PIN_NO(41) | 1) -#define MT6797_GPIO41__FUNC_SPI1_CS_A (MTK_PIN_NO(41) | 2) -#define MT6797_GPIO41__FUNC_PCM0_DO (MTK_PIN_NO(41) | 3) -#define MT6797_GPIO41__FUNC_I2S3_DO (MTK_PIN_NO(41) | 4) -#define MT6797_GPIO41__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(41) | 5) -#define MT6797_GPIO41__FUNC_URTS3 (MTK_PIN_NO(41) | 6) -#define MT6797_GPIO41__FUNC_C2K_TDI (MTK_PIN_NO(41) | 7) - -#define MT6797_GPIO42__FUNC_GPIO42 (MTK_PIN_NO(42) | 0) -#define MT6797_GPIO42__FUNC_DPI_D3 (MTK_PIN_NO(42) | 1) -#define MT6797_GPIO42__FUNC_SPI1_MO_A (MTK_PIN_NO(42) | 2) -#define MT6797_GPIO42__FUNC_PCM0_DI (MTK_PIN_NO(42) | 3) -#define MT6797_GPIO42__FUNC_I2S0_DI (MTK_PIN_NO(42) | 4) -#define MT6797_GPIO42__FUNC_CONN_MCU_TDI (MTK_PIN_NO(42) | 5) -#define MT6797_GPIO42__FUNC_UCTS3 (MTK_PIN_NO(42) | 6) -#define MT6797_GPIO42__FUNC_C2K_TMS (MTK_PIN_NO(42) | 7) - -#define MT6797_GPIO43__FUNC_GPIO43 (MTK_PIN_NO(43) | 0) -#define MT6797_GPIO43__FUNC_DPI_D4 (MTK_PIN_NO(43) | 1) -#define MT6797_GPIO43__FUNC_SPI2_CLK_A (MTK_PIN_NO(43) | 2) -#define MT6797_GPIO43__FUNC_PCM1_SYNC (MTK_PIN_NO(43) | 3) -#define MT6797_GPIO43__FUNC_I2S2_LRCK (MTK_PIN_NO(43) | 4) -#define MT6797_GPIO43__FUNC_CONN_MCU_TMS (MTK_PIN_NO(43) | 5) -#define MT6797_GPIO43__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(43) | 6) -#define MT6797_GPIO43__FUNC_C2K_TDO (MTK_PIN_NO(43) | 7) - -#define MT6797_GPIO44__FUNC_GPIO44 (MTK_PIN_NO(44) | 0) -#define MT6797_GPIO44__FUNC_DPI_D5 (MTK_PIN_NO(44) | 1) -#define MT6797_GPIO44__FUNC_SPI2_MI_A (MTK_PIN_NO(44) | 2) -#define MT6797_GPIO44__FUNC_PCM1_CLK (MTK_PIN_NO(44) | 3) -#define MT6797_GPIO44__FUNC_I2S2_BCK (MTK_PIN_NO(44) | 4) -#define MT6797_GPIO44__FUNC_CONN_MCU_TCK (MTK_PIN_NO(44) | 5) -#define MT6797_GPIO44__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(44) | 6) -#define MT6797_GPIO44__FUNC_C2K_RTCK (MTK_PIN_NO(44) | 7) - -#define MT6797_GPIO45__FUNC_GPIO45 (MTK_PIN_NO(45) | 0) -#define MT6797_GPIO45__FUNC_DPI_D6 (MTK_PIN_NO(45) | 1) -#define MT6797_GPIO45__FUNC_SPI2_CS_A (MTK_PIN_NO(45) | 2) -#define MT6797_GPIO45__FUNC_PCM1_DI (MTK_PIN_NO(45) | 3) -#define MT6797_GPIO45__FUNC_I2S2_DI (MTK_PIN_NO(45) | 4) -#define MT6797_GPIO45__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(45) | 5) -#define MT6797_GPIO45__FUNC_MD_URXD0 (MTK_PIN_NO(45) | 6) - -#define MT6797_GPIO46__FUNC_GPIO46 (MTK_PIN_NO(46) | 0) -#define MT6797_GPIO46__FUNC_DPI_D7 (MTK_PIN_NO(46) | 1) -#define MT6797_GPIO46__FUNC_SPI2_MO_A (MTK_PIN_NO(46) | 2) -#define MT6797_GPIO46__FUNC_PCM1_DO0 (MTK_PIN_NO(46) | 3) -#define MT6797_GPIO46__FUNC_I2S1_DO (MTK_PIN_NO(46) | 4) -#define MT6797_GPIO46__FUNC_ANT_SEL0 (MTK_PIN_NO(46) | 5) -#define MT6797_GPIO46__FUNC_MD_UTXD0 (MTK_PIN_NO(46) | 6) - -#define MT6797_GPIO47__FUNC_GPIO47 (MTK_PIN_NO(47) | 0) -#define MT6797_GPIO47__FUNC_DPI_D8 (MTK_PIN_NO(47) | 1) -#define MT6797_GPIO47__FUNC_CLKM0 (MTK_PIN_NO(47) | 2) -#define MT6797_GPIO47__FUNC_PCM1_DO1 (MTK_PIN_NO(47) | 3) -#define MT6797_GPIO47__FUNC_I2S0_MCK (MTK_PIN_NO(47) | 4) -#define MT6797_GPIO47__FUNC_ANT_SEL1 (MTK_PIN_NO(47) | 5) -#define MT6797_GPIO47__FUNC_PTA_RXD (MTK_PIN_NO(47) | 6) -#define MT6797_GPIO47__FUNC_C2K_URXD0 (MTK_PIN_NO(47) | 7) - -#define MT6797_GPIO48__FUNC_GPIO48 (MTK_PIN_NO(48) | 0) -#define MT6797_GPIO48__FUNC_DPI_D9 (MTK_PIN_NO(48) | 1) -#define MT6797_GPIO48__FUNC_CLKM1 (MTK_PIN_NO(48) | 2) -#define MT6797_GPIO48__FUNC_CMFLASH (MTK_PIN_NO(48) | 3) -#define MT6797_GPIO48__FUNC_I2S2_MCK (MTK_PIN_NO(48) | 4) -#define MT6797_GPIO48__FUNC_ANT_SEL2 (MTK_PIN_NO(48) | 5) -#define MT6797_GPIO48__FUNC_PTA_TXD (MTK_PIN_NO(48) | 6) -#define MT6797_GPIO48__FUNC_C2K_UTXD0 (MTK_PIN_NO(48) | 7) - -#define MT6797_GPIO49__FUNC_GPIO49 (MTK_PIN_NO(49) | 0) -#define MT6797_GPIO49__FUNC_DPI_D10 (MTK_PIN_NO(49) | 1) -#define MT6797_GPIO49__FUNC_MD_INT1_C2K_UIM1_HOT_PLUG_IN (MTK_PIN_NO(49) | 2) -#define MT6797_GPIO49__FUNC_PWM_C (MTK_PIN_NO(49) | 3) -#define MT6797_GPIO49__FUNC_IRTX_OUT (MTK_PIN_NO(49) | 4) -#define MT6797_GPIO49__FUNC_ANT_SEL3 (MTK_PIN_NO(49) | 5) -#define MT6797_GPIO49__FUNC_MD_URXD1 (MTK_PIN_NO(49) | 6) - -#define MT6797_GPIO50__FUNC_GPIO50 (MTK_PIN_NO(50) | 0) -#define MT6797_GPIO50__FUNC_DPI_D11 (MTK_PIN_NO(50) | 1) -#define MT6797_GPIO50__FUNC_MD_INT2 (MTK_PIN_NO(50) | 2) -#define MT6797_GPIO50__FUNC_PWM_D (MTK_PIN_NO(50) | 3) -#define MT6797_GPIO50__FUNC_CLKM2 (MTK_PIN_NO(50) | 4) -#define MT6797_GPIO50__FUNC_ANT_SEL4 (MTK_PIN_NO(50) | 5) -#define MT6797_GPIO50__FUNC_MD_UTXD1 (MTK_PIN_NO(50) | 6) - -#define MT6797_GPIO51__FUNC_GPIO51 (MTK_PIN_NO(51) | 0) -#define MT6797_GPIO51__FUNC_DPI_DE (MTK_PIN_NO(51) | 1) -#define MT6797_GPIO51__FUNC_SPI4_CLK_A (MTK_PIN_NO(51) | 2) -#define MT6797_GPIO51__FUNC_IRTX_OUT (MTK_PIN_NO(51) | 3) -#define MT6797_GPIO51__FUNC_SCL0_1 (MTK_PIN_NO(51) | 4) -#define MT6797_GPIO51__FUNC_ANT_SEL5 (MTK_PIN_NO(51) | 5) -#define MT6797_GPIO51__FUNC_C2K_UTXD1 (MTK_PIN_NO(51) | 7) - -#define MT6797_GPIO52__FUNC_GPIO52 (MTK_PIN_NO(52) | 0) -#define MT6797_GPIO52__FUNC_DPI_CK (MTK_PIN_NO(52) | 1) -#define MT6797_GPIO52__FUNC_SPI4_MI_A (MTK_PIN_NO(52) | 2) -#define MT6797_GPIO52__FUNC_SPI4_MO_A (MTK_PIN_NO(52) | 3) -#define MT6797_GPIO52__FUNC_SDA0_1 (MTK_PIN_NO(52) | 4) -#define MT6797_GPIO52__FUNC_ANT_SEL6 (MTK_PIN_NO(52) | 5) -#define MT6797_GPIO52__FUNC_C2K_URXD1 (MTK_PIN_NO(52) | 7) - -#define MT6797_GPIO53__FUNC_GPIO53 (MTK_PIN_NO(53) | 0) -#define MT6797_GPIO53__FUNC_DPI_HSYNC (MTK_PIN_NO(53) | 1) -#define MT6797_GPIO53__FUNC_SPI4_CS_A (MTK_PIN_NO(53) | 2) -#define MT6797_GPIO53__FUNC_CMFLASH (MTK_PIN_NO(53) | 3) -#define MT6797_GPIO53__FUNC_SCL1_1 (MTK_PIN_NO(53) | 4) -#define MT6797_GPIO53__FUNC_ANT_SEL7 (MTK_PIN_NO(53) | 5) -#define MT6797_GPIO53__FUNC_MD_URXD2 (MTK_PIN_NO(53) | 6) -#define MT6797_GPIO53__FUNC_PCC_PPC_IO (MTK_PIN_NO(53) | 7) - -#define MT6797_GPIO54__FUNC_GPIO54 (MTK_PIN_NO(54) | 0) -#define MT6797_GPIO54__FUNC_DPI_VSYNC (MTK_PIN_NO(54) | 1) -#define MT6797_GPIO54__FUNC_SPI4_MO_A (MTK_PIN_NO(54) | 2) -#define MT6797_GPIO54__FUNC_SPI4_MI_A (MTK_PIN_NO(54) | 3) -#define MT6797_GPIO54__FUNC_SDA1_1 (MTK_PIN_NO(54) | 4) -#define MT6797_GPIO54__FUNC_PWM_A (MTK_PIN_NO(54) | 5) -#define MT6797_GPIO54__FUNC_MD_UTXD2 (MTK_PIN_NO(54) | 6) -#define MT6797_GPIO54__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(54) | 7) - -#define MT6797_GPIO55__FUNC_GPIO55 (MTK_PIN_NO(55) | 0) -#define MT6797_GPIO55__FUNC_SCL1_0 (MTK_PIN_NO(55) | 1) - -#define MT6797_GPIO56__FUNC_GPIO56 (MTK_PIN_NO(56) | 0) -#define MT6797_GPIO56__FUNC_SDA1_0 (MTK_PIN_NO(56) | 1) - -#define MT6797_GPIO57__FUNC_GPIO57 (MTK_PIN_NO(57) | 0) -#define MT6797_GPIO57__FUNC_SPI0_CLK (MTK_PIN_NO(57) | 1) -#define MT6797_GPIO57__FUNC_SCL0_2 (MTK_PIN_NO(57) | 2) -#define MT6797_GPIO57__FUNC_PWM_B (MTK_PIN_NO(57) | 3) -#define MT6797_GPIO57__FUNC_UTXD3 (MTK_PIN_NO(57) | 4) -#define MT6797_GPIO57__FUNC_PCM0_SYNC (MTK_PIN_NO(57) | 5) - -#define MT6797_GPIO58__FUNC_GPIO58 (MTK_PIN_NO(58) | 0) -#define MT6797_GPIO58__FUNC_SPI0_MI (MTK_PIN_NO(58) | 1) -#define MT6797_GPIO58__FUNC_SPI0_MO (MTK_PIN_NO(58) | 2) -#define MT6797_GPIO58__FUNC_SDA1_2 (MTK_PIN_NO(58) | 3) -#define MT6797_GPIO58__FUNC_URXD3 (MTK_PIN_NO(58) | 4) -#define MT6797_GPIO58__FUNC_PCM0_CLK (MTK_PIN_NO(58) | 5) - -#define MT6797_GPIO59__FUNC_GPIO59 (MTK_PIN_NO(59) | 0) -#define MT6797_GPIO59__FUNC_SPI0_MO (MTK_PIN_NO(59) | 1) -#define MT6797_GPIO59__FUNC_SPI0_MI (MTK_PIN_NO(59) | 2) -#define MT6797_GPIO59__FUNC_PWM_C (MTK_PIN_NO(59) | 3) -#define MT6797_GPIO59__FUNC_URTS3 (MTK_PIN_NO(59) | 4) -#define MT6797_GPIO59__FUNC_PCM0_DO (MTK_PIN_NO(59) | 5) - -#define MT6797_GPIO60__FUNC_GPIO60 (MTK_PIN_NO(60) | 0) -#define MT6797_GPIO60__FUNC_SPI0_CS (MTK_PIN_NO(60) | 1) -#define MT6797_GPIO60__FUNC_SDA0_2 (MTK_PIN_NO(60) | 2) -#define MT6797_GPIO60__FUNC_SCL1_2 (MTK_PIN_NO(60) | 3) -#define MT6797_GPIO60__FUNC_UCTS3 (MTK_PIN_NO(60) | 4) -#define MT6797_GPIO60__FUNC_PCM0_DI (MTK_PIN_NO(60) | 5) - -#define MT6797_GPIO61__FUNC_GPIO61 (MTK_PIN_NO(61) | 0) -#define MT6797_GPIO61__FUNC_EINT0 (MTK_PIN_NO(61) | 1) -#define MT6797_GPIO61__FUNC_IDDIG (MTK_PIN_NO(61) | 2) -#define MT6797_GPIO61__FUNC_SPI4_CLK_B (MTK_PIN_NO(61) | 3) -#define MT6797_GPIO61__FUNC_I2S0_LRCK (MTK_PIN_NO(61) | 4) -#define MT6797_GPIO61__FUNC_PCM0_SYNC (MTK_PIN_NO(61) | 5) -#define MT6797_GPIO61__FUNC_C2K_EINT0 (MTK_PIN_NO(61) | 7) - -#define MT6797_GPIO62__FUNC_GPIO62 (MTK_PIN_NO(62) | 0) -#define MT6797_GPIO62__FUNC_EINT1 (MTK_PIN_NO(62) | 1) -#define MT6797_GPIO62__FUNC_USB_DRVVBUS (MTK_PIN_NO(62) | 2) -#define MT6797_GPIO62__FUNC_SPI4_MI_B (MTK_PIN_NO(62) | 3) -#define MT6797_GPIO62__FUNC_I2S0_BCK (MTK_PIN_NO(62) | 4) -#define MT6797_GPIO62__FUNC_PCM0_CLK (MTK_PIN_NO(62) | 5) -#define MT6797_GPIO62__FUNC_C2K_EINT1 (MTK_PIN_NO(62) | 7) - -#define MT6797_GPIO63__FUNC_GPIO63 (MTK_PIN_NO(63) | 0) -#define MT6797_GPIO63__FUNC_EINT2 (MTK_PIN_NO(63) | 1) -#define MT6797_GPIO63__FUNC_IRTX_OUT (MTK_PIN_NO(63) | 2) -#define MT6797_GPIO63__FUNC_SPI4_MO_B (MTK_PIN_NO(63) | 3) -#define MT6797_GPIO63__FUNC_I2S0_MCK (MTK_PIN_NO(63) | 4) -#define MT6797_GPIO63__FUNC_PCM0_DI (MTK_PIN_NO(63) | 5) -#define MT6797_GPIO63__FUNC_C2K_DM_EINT0 (MTK_PIN_NO(63) | 7) - -#define MT6797_GPIO64__FUNC_GPIO64 (MTK_PIN_NO(64) | 0) -#define MT6797_GPIO64__FUNC_EINT3 (MTK_PIN_NO(64) | 1) -#define MT6797_GPIO64__FUNC_CMFLASH (MTK_PIN_NO(64) | 2) -#define MT6797_GPIO64__FUNC_SPI4_CS_B (MTK_PIN_NO(64) | 3) -#define MT6797_GPIO64__FUNC_I2S0_DI (MTK_PIN_NO(64) | 4) -#define MT6797_GPIO64__FUNC_PCM0_DO (MTK_PIN_NO(64) | 5) -#define MT6797_GPIO64__FUNC_C2K_DM_EINT1 (MTK_PIN_NO(64) | 7) - -#define MT6797_GPIO65__FUNC_GPIO65 (MTK_PIN_NO(65) | 0) -#define MT6797_GPIO65__FUNC_EINT4 (MTK_PIN_NO(65) | 1) -#define MT6797_GPIO65__FUNC_CLKM0 (MTK_PIN_NO(65) | 2) -#define MT6797_GPIO65__FUNC_SPI5_CLK_B (MTK_PIN_NO(65) | 3) -#define MT6797_GPIO65__FUNC_I2S1_LRCK (MTK_PIN_NO(65) | 4) -#define MT6797_GPIO65__FUNC_PWM_A (MTK_PIN_NO(65) | 5) -#define MT6797_GPIO65__FUNC_C2K_DM_EINT2 (MTK_PIN_NO(65) | 7) - -#define MT6797_GPIO66__FUNC_GPIO66 (MTK_PIN_NO(66) | 0) -#define MT6797_GPIO66__FUNC_EINT5 (MTK_PIN_NO(66) | 1) -#define MT6797_GPIO66__FUNC_CLKM1 (MTK_PIN_NO(66) | 2) -#define MT6797_GPIO66__FUNC_SPI5_MI_B (MTK_PIN_NO(66) | 3) -#define MT6797_GPIO66__FUNC_I2S1_BCK (MTK_PIN_NO(66) | 4) -#define MT6797_GPIO66__FUNC_PWM_B (MTK_PIN_NO(66) | 5) -#define MT6797_GPIO66__FUNC_C2K_DM_EINT3 (MTK_PIN_NO(66) | 7) - -#define MT6797_GPIO67__FUNC_GPIO67 (MTK_PIN_NO(67) | 0) -#define MT6797_GPIO67__FUNC_EINT6 (MTK_PIN_NO(67) | 1) -#define MT6797_GPIO67__FUNC_CLKM2 (MTK_PIN_NO(67) | 2) -#define MT6797_GPIO67__FUNC_SPI5_MO_B (MTK_PIN_NO(67) | 3) -#define MT6797_GPIO67__FUNC_I2S1_MCK (MTK_PIN_NO(67) | 4) -#define MT6797_GPIO67__FUNC_PWM_C (MTK_PIN_NO(67) | 5) -#define MT6797_GPIO67__FUNC_DBG_MON_A0 (MTK_PIN_NO(67) | 7) - -#define MT6797_GPIO68__FUNC_GPIO68 (MTK_PIN_NO(68) | 0) -#define MT6797_GPIO68__FUNC_EINT7 (MTK_PIN_NO(68) | 1) -#define MT6797_GPIO68__FUNC_CLKM3 (MTK_PIN_NO(68) | 2) -#define MT6797_GPIO68__FUNC_SPI5_CS_B (MTK_PIN_NO(68) | 3) -#define MT6797_GPIO68__FUNC_I2S1_DO (MTK_PIN_NO(68) | 4) -#define MT6797_GPIO68__FUNC_PWM_D (MTK_PIN_NO(68) | 5) -#define MT6797_GPIO68__FUNC_DBG_MON_A1 (MTK_PIN_NO(68) | 7) - -#define MT6797_GPIO69__FUNC_GPIO69 (MTK_PIN_NO(69) | 0) -#define MT6797_GPIO69__FUNC_I2S0_LRCK (MTK_PIN_NO(69) | 1) -#define MT6797_GPIO69__FUNC_I2S3_LRCK (MTK_PIN_NO(69) | 2) -#define MT6797_GPIO69__FUNC_I2S1_LRCK (MTK_PIN_NO(69) | 3) -#define MT6797_GPIO69__FUNC_I2S2_LRCK (MTK_PIN_NO(69) | 4) -#define MT6797_GPIO69__FUNC_DBG_MON_A2 (MTK_PIN_NO(69) | 7) - -#define MT6797_GPIO70__FUNC_GPIO70 (MTK_PIN_NO(70) | 0) -#define MT6797_GPIO70__FUNC_I2S0_BCK (MTK_PIN_NO(70) | 1) -#define MT6797_GPIO70__FUNC_I2S3_BCK (MTK_PIN_NO(70) | 2) -#define MT6797_GPIO70__FUNC_I2S1_BCK (MTK_PIN_NO(70) | 3) -#define MT6797_GPIO70__FUNC_I2S2_BCK (MTK_PIN_NO(70) | 4) -#define MT6797_GPIO70__FUNC_DBG_MON_A3 (MTK_PIN_NO(70) | 7) - -#define MT6797_GPIO71__FUNC_GPIO71 (MTK_PIN_NO(71) | 0) -#define MT6797_GPIO71__FUNC_I2S0_MCK (MTK_PIN_NO(71) | 1) -#define MT6797_GPIO71__FUNC_I2S3_MCK (MTK_PIN_NO(71) | 2) -#define MT6797_GPIO71__FUNC_I2S1_MCK (MTK_PIN_NO(71) | 3) -#define MT6797_GPIO71__FUNC_I2S2_MCK (MTK_PIN_NO(71) | 4) -#define MT6797_GPIO71__FUNC_DBG_MON_A4 (MTK_PIN_NO(71) | 7) - -#define MT6797_GPIO72__FUNC_GPIO72 (MTK_PIN_NO(72) | 0) -/* #define MT6797_GPIO72__FUNC_I2S0_DI (MTK_PIN_NO(72) | 1) */ -#define MT6797_GPIO72__FUNC_I2S0_DI (MTK_PIN_NO(72) | 2) -/* #define MT6797_GPIO72__FUNC_I2S2_DI (MTK_PIN_NO(72) | 3) */ -#define MT6797_GPIO72__FUNC_I2S2_DI (MTK_PIN_NO(72) | 4) -#define MT6797_GPIO72__FUNC_DBG_MON_A5 (MTK_PIN_NO(72) | 7) - -#define MT6797_GPIO73__FUNC_GPIO73 (MTK_PIN_NO(73) | 0) -/* #define MT6797_GPIO73__FUNC_I2S3_DO (MTK_PIN_NO(73) | 1) */ -#define MT6797_GPIO73__FUNC_I2S3_DO (MTK_PIN_NO(73) | 2) -/* #define MT6797_GPIO73__FUNC_I2S1_DO (MTK_PIN_NO(73) | 3) */ -#define MT6797_GPIO73__FUNC_I2S1_DO (MTK_PIN_NO(73) | 4) -#define MT6797_GPIO73__FUNC_DBG_MON_A6 (MTK_PIN_NO(73) | 7) - -#define MT6797_GPIO74__FUNC_GPIO74 (MTK_PIN_NO(74) | 0) -#define MT6797_GPIO74__FUNC_SCL3_0 (MTK_PIN_NO(74) | 1) -#define MT6797_GPIO74__FUNC_AUXIF_CLK1 (MTK_PIN_NO(74) | 7) - -#define MT6797_GPIO75__FUNC_GPIO75 (MTK_PIN_NO(75) | 0) -#define MT6797_GPIO75__FUNC_SDA3_0 (MTK_PIN_NO(75) | 1) -#define MT6797_GPIO75__FUNC_AUXIF_ST1 (MTK_PIN_NO(75) | 7) - -#define MT6797_GPIO76__FUNC_GPIO76 (MTK_PIN_NO(76) | 0) -#define MT6797_GPIO76__FUNC_CONN_HRST_B (MTK_PIN_NO(76) | 1) -#define MT6797_GPIO76__FUNC_C2K_DM_EINT0 (MTK_PIN_NO(76) | 7) - -#define MT6797_GPIO77__FUNC_GPIO77 (MTK_PIN_NO(77) | 0) -#define MT6797_GPIO77__FUNC_CONN_TOP_CLK (MTK_PIN_NO(77) | 1) -#define MT6797_GPIO77__FUNC_C2K_DM_EINT1 (MTK_PIN_NO(77) | 7) - -#define MT6797_GPIO78__FUNC_GPIO78 (MTK_PIN_NO(78) | 0) -#define MT6797_GPIO78__FUNC_CONN_TOP_DATA (MTK_PIN_NO(78) | 1) -#define MT6797_GPIO78__FUNC_C2K_DM_EINT2 (MTK_PIN_NO(78) | 7) - -#define MT6797_GPIO79__FUNC_GPIO79 (MTK_PIN_NO(79) | 0) -#define MT6797_GPIO79__FUNC_CONN_WB_PTA (MTK_PIN_NO(79) | 1) -#define MT6797_GPIO79__FUNC_C2K_DM_EINT3 (MTK_PIN_NO(79) | 7) - -#define MT6797_GPIO80__FUNC_GPIO80 (MTK_PIN_NO(80) | 0) -#define MT6797_GPIO80__FUNC_CONN_WF_HB0 (MTK_PIN_NO(80) | 1) -#define MT6797_GPIO80__FUNC_C2K_EINT0 (MTK_PIN_NO(80) | 7) - -#define MT6797_GPIO81__FUNC_GPIO81 (MTK_PIN_NO(81) | 0) -#define MT6797_GPIO81__FUNC_CONN_WF_HB1 (MTK_PIN_NO(81) | 1) -#define MT6797_GPIO81__FUNC_C2K_EINT1 (MTK_PIN_NO(81) | 7) - -#define MT6797_GPIO82__FUNC_GPIO82 (MTK_PIN_NO(82) | 0) -#define MT6797_GPIO82__FUNC_CONN_WF_HB2 (MTK_PIN_NO(82) | 1) -#define MT6797_GPIO82__FUNC_MD_CLKM0 (MTK_PIN_NO(82) | 7) - -#define MT6797_GPIO83__FUNC_GPIO83 (MTK_PIN_NO(83) | 0) -#define MT6797_GPIO83__FUNC_CONN_BT_CLK (MTK_PIN_NO(83) | 1) -#define MT6797_GPIO83__FUNC_MD_CLKM1 (MTK_PIN_NO(83) | 7) - -#define MT6797_GPIO84__FUNC_GPIO84 (MTK_PIN_NO(84) | 0) -#define MT6797_GPIO84__FUNC_CONN_BT_DATA (MTK_PIN_NO(84) | 1) - -#define MT6797_GPIO85__FUNC_GPIO85 (MTK_PIN_NO(85) | 0) -#define MT6797_GPIO85__FUNC_EINT8 (MTK_PIN_NO(85) | 1) -#define MT6797_GPIO85__FUNC_I2S1_LRCK (MTK_PIN_NO(85) | 2) -#define MT6797_GPIO85__FUNC_I2S2_LRCK (MTK_PIN_NO(85) | 3) -#define MT6797_GPIO85__FUNC_URXD1 (MTK_PIN_NO(85) | 4) -#define MT6797_GPIO85__FUNC_MD_URXD0 (MTK_PIN_NO(85) | 5) -#define MT6797_GPIO85__FUNC_DBG_MON_A7 (MTK_PIN_NO(85) | 7) - -#define MT6797_GPIO86__FUNC_GPIO86 (MTK_PIN_NO(86) | 0) -#define MT6797_GPIO86__FUNC_EINT9 (MTK_PIN_NO(86) | 1) -#define MT6797_GPIO86__FUNC_I2S1_BCK (MTK_PIN_NO(86) | 2) -#define MT6797_GPIO86__FUNC_I2S2_BCK (MTK_PIN_NO(86) | 3) -#define MT6797_GPIO86__FUNC_UTXD1 (MTK_PIN_NO(86) | 4) -#define MT6797_GPIO86__FUNC_MD_UTXD0 (MTK_PIN_NO(86) | 5) -#define MT6797_GPIO86__FUNC_DBG_MON_A8 (MTK_PIN_NO(86) | 7) - -#define MT6797_GPIO87__FUNC_GPIO87 (MTK_PIN_NO(87) | 0) -#define MT6797_GPIO87__FUNC_EINT10 (MTK_PIN_NO(87) | 1) -#define MT6797_GPIO87__FUNC_I2S1_MCK (MTK_PIN_NO(87) | 2) -#define MT6797_GPIO87__FUNC_I2S2_MCK (MTK_PIN_NO(87) | 3) -#define MT6797_GPIO87__FUNC_URTS1 (MTK_PIN_NO(87) | 4) -#define MT6797_GPIO87__FUNC_MD_URXD1 (MTK_PIN_NO(87) | 5) -#define MT6797_GPIO87__FUNC_DBG_MON_A9 (MTK_PIN_NO(87) | 7) - -#define MT6797_GPIO88__FUNC_GPIO88 (MTK_PIN_NO(88) | 0) -#define MT6797_GPIO88__FUNC_EINT11 (MTK_PIN_NO(88) | 1) -#define MT6797_GPIO88__FUNC_I2S1_DO (MTK_PIN_NO(88) | 2) -#define MT6797_GPIO88__FUNC_I2S2_DI (MTK_PIN_NO(88) | 3) -#define MT6797_GPIO88__FUNC_UCTS1 (MTK_PIN_NO(88) | 4) -#define MT6797_GPIO88__FUNC_MD_UTXD1 (MTK_PIN_NO(88) | 5) -#define MT6797_GPIO88__FUNC_DBG_MON_A10 (MTK_PIN_NO(88) | 7) - -#define MT6797_GPIO89__FUNC_GPIO89 (MTK_PIN_NO(89) | 0) -#define MT6797_GPIO89__FUNC_EINT12 (MTK_PIN_NO(89) | 1) -#define MT6797_GPIO89__FUNC_IRTX_OUT (MTK_PIN_NO(89) | 2) -#define MT6797_GPIO89__FUNC_CLKM0 (MTK_PIN_NO(89) | 3) -#define MT6797_GPIO89__FUNC_PCM1_SYNC (MTK_PIN_NO(89) | 4) -#define MT6797_GPIO89__FUNC_URTS0 (MTK_PIN_NO(89) | 5) -#define MT6797_GPIO89__FUNC_DBG_MON_A11 (MTK_PIN_NO(89) | 7) - -#define MT6797_GPIO90__FUNC_GPIO90 (MTK_PIN_NO(90) | 0) -#define MT6797_GPIO90__FUNC_EINT13 (MTK_PIN_NO(90) | 1) -#define MT6797_GPIO90__FUNC_CMFLASH (MTK_PIN_NO(90) | 2) -#define MT6797_GPIO90__FUNC_CLKM1 (MTK_PIN_NO(90) | 3) -#define MT6797_GPIO90__FUNC_PCM1_CLK (MTK_PIN_NO(90) | 4) -#define MT6797_GPIO90__FUNC_UCTS0 (MTK_PIN_NO(90) | 5) -#define MT6797_GPIO90__FUNC_C2K_DM_EINT0 (MTK_PIN_NO(90) | 7) - -#define MT6797_GPIO91__FUNC_GPIO91 (MTK_PIN_NO(91) | 0) -#define MT6797_GPIO91__FUNC_EINT14 (MTK_PIN_NO(91) | 1) -#define MT6797_GPIO91__FUNC_PWM_A (MTK_PIN_NO(91) | 2) -#define MT6797_GPIO91__FUNC_CLKM2 (MTK_PIN_NO(91) | 3) -#define MT6797_GPIO91__FUNC_PCM1_DI (MTK_PIN_NO(91) | 4) -#define MT6797_GPIO91__FUNC_SDA0_3 (MTK_PIN_NO(91) | 5) -#define MT6797_GPIO91__FUNC_C2K_DM_EINT1 (MTK_PIN_NO(91) | 7) - -#define MT6797_GPIO92__FUNC_GPIO92 (MTK_PIN_NO(92) | 0) -#define MT6797_GPIO92__FUNC_EINT15 (MTK_PIN_NO(92) | 1) -#define MT6797_GPIO92__FUNC_PWM_B (MTK_PIN_NO(92) | 2) -#define MT6797_GPIO92__FUNC_CLKM3 (MTK_PIN_NO(92) | 3) -#define MT6797_GPIO92__FUNC_PCM1_DO0 (MTK_PIN_NO(92) | 4) -#define MT6797_GPIO92__FUNC_SCL0_3 (MTK_PIN_NO(92) | 5) - -#define MT6797_GPIO93__FUNC_GPIO93 (MTK_PIN_NO(93) | 0) -#define MT6797_GPIO93__FUNC_EINT16 (MTK_PIN_NO(93) | 1) -#define MT6797_GPIO93__FUNC_IDDIG (MTK_PIN_NO(93) | 2) -#define MT6797_GPIO93__FUNC_CLKM4 (MTK_PIN_NO(93) | 3) -#define MT6797_GPIO93__FUNC_PCM1_DO1 (MTK_PIN_NO(93) | 4) -#define MT6797_GPIO93__FUNC_MD_INT2 (MTK_PIN_NO(93) | 5) -#define MT6797_GPIO93__FUNC_DROP_ZONE (MTK_PIN_NO(93) | 7) - -#define MT6797_GPIO94__FUNC_GPIO94 (MTK_PIN_NO(94) | 0) -#define MT6797_GPIO94__FUNC_USB_DRVVBUS (MTK_PIN_NO(94) | 1) -#define MT6797_GPIO94__FUNC_PWM_C (MTK_PIN_NO(94) | 2) -#define MT6797_GPIO94__FUNC_CLKM5 (MTK_PIN_NO(94) | 3) - -#define MT6797_GPIO95__FUNC_GPIO95 (MTK_PIN_NO(95) | 0) -#define MT6797_GPIO95__FUNC_SDA2_0 (MTK_PIN_NO(95) | 1) -#define MT6797_GPIO95__FUNC_AUXIF_ST0 (MTK_PIN_NO(95) | 7) - -#define MT6797_GPIO96__FUNC_GPIO96 (MTK_PIN_NO(96) | 0) -#define MT6797_GPIO96__FUNC_SCL2_0 (MTK_PIN_NO(96) | 1) -#define MT6797_GPIO96__FUNC_AUXIF_CLK0 (MTK_PIN_NO(96) | 7) - -#define MT6797_GPIO97__FUNC_GPIO97 (MTK_PIN_NO(97) | 0) -#define MT6797_GPIO97__FUNC_URXD0 (MTK_PIN_NO(97) | 1) -#define MT6797_GPIO97__FUNC_UTXD0 (MTK_PIN_NO(97) | 2) -#define MT6797_GPIO97__FUNC_MD_URXD0 (MTK_PIN_NO(97) | 3) -#define MT6797_GPIO97__FUNC_MD_URXD1 (MTK_PIN_NO(97) | 4) -#define MT6797_GPIO97__FUNC_MD_URXD2 (MTK_PIN_NO(97) | 5) -#define MT6797_GPIO97__FUNC_C2K_URXD0 (MTK_PIN_NO(97) | 6) -#define MT6797_GPIO97__FUNC_C2K_URXD1 (MTK_PIN_NO(97) | 7) - -#define MT6797_GPIO98__FUNC_GPIO98 (MTK_PIN_NO(98) | 0) -#define MT6797_GPIO98__FUNC_UTXD0 (MTK_PIN_NO(98) | 1) -#define MT6797_GPIO98__FUNC_URXD0 (MTK_PIN_NO(98) | 2) -#define MT6797_GPIO98__FUNC_MD_UTXD0 (MTK_PIN_NO(98) | 3) -#define MT6797_GPIO98__FUNC_MD_UTXD1 (MTK_PIN_NO(98) | 4) -#define MT6797_GPIO98__FUNC_MD_UTXD2 (MTK_PIN_NO(98) | 5) -#define MT6797_GPIO98__FUNC_C2K_UTXD0 (MTK_PIN_NO(98) | 6) -#define MT6797_GPIO98__FUNC_C2K_UTXD1 (MTK_PIN_NO(98) | 7) - -#define MT6797_GPIO99__FUNC_GPIO99 (MTK_PIN_NO(99) | 0) -#define MT6797_GPIO99__FUNC_RTC32K_CK (MTK_PIN_NO(99) | 1) - -#define MT6797_GPIO100__FUNC_GPIO100 (MTK_PIN_NO(100) | 0) -#define MT6797_GPIO100__FUNC_SRCLKENAI0 (MTK_PIN_NO(100) | 1) - -#define MT6797_GPIO101__FUNC_GPIO101 (MTK_PIN_NO(101) | 0) -#define MT6797_GPIO101__FUNC_SRCLKENAI1 (MTK_PIN_NO(101) | 1) - -#define MT6797_GPIO102__FUNC_GPIO102 (MTK_PIN_NO(102) | 0) -#define MT6797_GPIO102__FUNC_SRCLKENA0 (MTK_PIN_NO(102) | 1) - -#define MT6797_GPIO103__FUNC_GPIO103 (MTK_PIN_NO(103) | 0) -#define MT6797_GPIO103__FUNC_SRCLKENA1 (MTK_PIN_NO(103) | 1) - -#define MT6797_GPIO104__FUNC_GPIO104 (MTK_PIN_NO(104) | 0) -#define MT6797_GPIO104__FUNC_SYSRSTB (MTK_PIN_NO(104) | 1) - -#define MT6797_GPIO105__FUNC_GPIO105 (MTK_PIN_NO(105) | 0) -#define MT6797_GPIO105__FUNC_WATCHDOG (MTK_PIN_NO(105) | 1) - -#define MT6797_GPIO106__FUNC_GPIO106 (MTK_PIN_NO(106) | 0) -#define MT6797_GPIO106__FUNC_KPROW0 (MTK_PIN_NO(106) | 1) -#define MT6797_GPIO106__FUNC_CMFLASH (MTK_PIN_NO(106) | 2) -#define MT6797_GPIO106__FUNC_CLKM4 (MTK_PIN_NO(106) | 3) -#define MT6797_GPIO106__FUNC_TP_GPIO0_AO (MTK_PIN_NO(106) | 4) -#define MT6797_GPIO106__FUNC_IRTX_OUT (MTK_PIN_NO(106) | 5) - -#define MT6797_GPIO107__FUNC_GPIO107 (MTK_PIN_NO(107) | 0) -#define MT6797_GPIO107__FUNC_KPROW1 (MTK_PIN_NO(107) | 1) -#define MT6797_GPIO107__FUNC_IDDIG (MTK_PIN_NO(107) | 2) -#define MT6797_GPIO107__FUNC_CLKM5 (MTK_PIN_NO(107) | 3) -#define MT6797_GPIO107__FUNC_TP_GPIO1_AO (MTK_PIN_NO(107) | 4) -#define MT6797_GPIO107__FUNC_I2S1_BCK (MTK_PIN_NO(107) | 5) -#define MT6797_GPIO107__FUNC_DAP_SIB1_SWD (MTK_PIN_NO(107) | 7) - -#define MT6797_GPIO108__FUNC_GPIO108 (MTK_PIN_NO(108) | 0) -#define MT6797_GPIO108__FUNC_KPROW2 (MTK_PIN_NO(108) | 1) -#define MT6797_GPIO108__FUNC_USB_DRVVBUS (MTK_PIN_NO(108) | 2) -#define MT6797_GPIO108__FUNC_PWM_A (MTK_PIN_NO(108) | 3) -#define MT6797_GPIO108__FUNC_CMFLASH (MTK_PIN_NO(108) | 4) -#define MT6797_GPIO108__FUNC_I2S1_LRCK (MTK_PIN_NO(108) | 5) -#define MT6797_GPIO108__FUNC_DAP_SIB1_SWCK (MTK_PIN_NO(108) | 7) - -#define MT6797_GPIO109__FUNC_GPIO109 (MTK_PIN_NO(109) | 0) -#define MT6797_GPIO109__FUNC_KPCOL0 (MTK_PIN_NO(109) | 1) - -#define MT6797_GPIO110__FUNC_GPIO110 (MTK_PIN_NO(110) | 0) -#define MT6797_GPIO110__FUNC_KPCOL1 (MTK_PIN_NO(110) | 1) -#define MT6797_GPIO110__FUNC_SDA1_3 (MTK_PIN_NO(110) | 2) -#define MT6797_GPIO110__FUNC_PWM_B (MTK_PIN_NO(110) | 3) -#define MT6797_GPIO110__FUNC_CLKM0 (MTK_PIN_NO(110) | 4) -#define MT6797_GPIO110__FUNC_I2S1_DO (MTK_PIN_NO(110) | 5) -#define MT6797_GPIO110__FUNC_C2K_DM_EINT3 (MTK_PIN_NO(110) | 7) - -#define MT6797_GPIO111__FUNC_GPIO111 (MTK_PIN_NO(111) | 0) -#define MT6797_GPIO111__FUNC_KPCOL2 (MTK_PIN_NO(111) | 1) -#define MT6797_GPIO111__FUNC_SCL1_3 (MTK_PIN_NO(111) | 2) -#define MT6797_GPIO111__FUNC_PWM_C (MTK_PIN_NO(111) | 3) -#define MT6797_GPIO111__FUNC_DISP_PWM (MTK_PIN_NO(111) | 4) -#define MT6797_GPIO111__FUNC_I2S1_MCK (MTK_PIN_NO(111) | 5) -#define MT6797_GPIO111__FUNC_C2K_DM_EINT2 (MTK_PIN_NO(111) | 7) - -#define MT6797_GPIO112__FUNC_GPIO112 (MTK_PIN_NO(112) | 0) -#define MT6797_GPIO112__FUNC_MD_INT1_C2K_UIM1_HOT_PLUG_IN (MTK_PIN_NO(112) | 1) -#define MT6797_GPIO112__FUNC_C2K_DM_EINT1 (MTK_PIN_NO(112) | 7) - -#define MT6797_GPIO113__FUNC_GPIO113 (MTK_PIN_NO(113) | 0) -#define MT6797_GPIO113__FUNC_MD_INT0_C2K_UIM0_HOT_PLUG_IN (MTK_PIN_NO(113) | 1) -#define MT6797_GPIO113__FUNC_C2K_DM_EINT0 (MTK_PIN_NO(113) | 7) - -#define MT6797_GPIO114__FUNC_GPIO114 (MTK_PIN_NO(114) | 0) -#define MT6797_GPIO114__FUNC_MSDC0_DAT0 (MTK_PIN_NO(114) | 1) - -#define MT6797_GPIO115__FUNC_GPIO115 (MTK_PIN_NO(115) | 0) -#define MT6797_GPIO115__FUNC_MSDC0_DAT1 (MTK_PIN_NO(115) | 1) - -#define MT6797_GPIO116__FUNC_GPIO116 (MTK_PIN_NO(116) | 0) -#define MT6797_GPIO116__FUNC_MSDC0_DAT2 (MTK_PIN_NO(116) | 1) - -#define MT6797_GPIO117__FUNC_GPIO117 (MTK_PIN_NO(117) | 0) -#define MT6797_GPIO117__FUNC_MSDC0_DAT3 (MTK_PIN_NO(117) | 1) - -#define MT6797_GPIO118__FUNC_GPIO118 (MTK_PIN_NO(118) | 0) -#define MT6797_GPIO118__FUNC_MSDC0_DAT4 (MTK_PIN_NO(118) | 1) - -#define MT6797_GPIO119__FUNC_GPIO119 (MTK_PIN_NO(119) | 0) -#define MT6797_GPIO119__FUNC_MSDC0_DAT5 (MTK_PIN_NO(119) | 1) - -#define MT6797_GPIO120__FUNC_GPIO120 (MTK_PIN_NO(120) | 0) -#define MT6797_GPIO120__FUNC_MSDC0_DAT6 (MTK_PIN_NO(120) | 1) - -#define MT6797_GPIO121__FUNC_GPIO121 (MTK_PIN_NO(121) | 0) -#define MT6797_GPIO121__FUNC_MSDC0_DAT7 (MTK_PIN_NO(121) | 1) - -#define MT6797_GPIO122__FUNC_GPIO122 (MTK_PIN_NO(122) | 0) -#define MT6797_GPIO122__FUNC_MSDC0_CMD (MTK_PIN_NO(122) | 1) - -#define MT6797_GPIO123__FUNC_GPIO123 (MTK_PIN_NO(123) | 0) -#define MT6797_GPIO123__FUNC_MSDC0_CLK (MTK_PIN_NO(123) | 1) - -#define MT6797_GPIO124__FUNC_GPIO124 (MTK_PIN_NO(124) | 0) -#define MT6797_GPIO124__FUNC_MSDC0_DSL (MTK_PIN_NO(124) | 1) - -#define MT6797_GPIO125__FUNC_GPIO125 (MTK_PIN_NO(125) | 0) -#define MT6797_GPIO125__FUNC_MSDC0_RSTB (MTK_PIN_NO(125) | 1) - -#define MT6797_GPIO126__FUNC_GPIO126 (MTK_PIN_NO(126) | 0) -#define MT6797_GPIO126__FUNC_MD1_SIM1_SCLK (MTK_PIN_NO(126) | 1) -#define MT6797_GPIO126__FUNC_MD1_SIM2_SCLK (MTK_PIN_NO(126) | 2) -#define MT6797_GPIO126__FUNC_C2K_UIM0_CLK (MTK_PIN_NO(126) | 3) -#define MT6797_GPIO126__FUNC_C2K_UIM1_CLK (MTK_PIN_NO(126) | 4) - -#define MT6797_GPIO127__FUNC_GPIO127 (MTK_PIN_NO(127) | 0) -#define MT6797_GPIO127__FUNC_MD1_SIM1_SRST (MTK_PIN_NO(127) | 1) -#define MT6797_GPIO127__FUNC_MD1_SIM2_SRST (MTK_PIN_NO(127) | 2) -#define MT6797_GPIO127__FUNC_C2K_UIM0_RST (MTK_PIN_NO(127) | 3) -#define MT6797_GPIO127__FUNC_C2K_UIM1_RST (MTK_PIN_NO(127) | 4) - -#define MT6797_GPIO128__FUNC_GPIO128 (MTK_PIN_NO(128) | 0) -#define MT6797_GPIO128__FUNC_MD1_SIM1_SIO (MTK_PIN_NO(128) | 1) -#define MT6797_GPIO128__FUNC_MD1_SIM2_SIO (MTK_PIN_NO(128) | 2) -#define MT6797_GPIO128__FUNC_C2K_UIM0_IO (MTK_PIN_NO(128) | 3) -#define MT6797_GPIO128__FUNC_C2K_UIM1_IO (MTK_PIN_NO(128) | 4) - -#define MT6797_GPIO129__FUNC_GPIO129 (MTK_PIN_NO(129) | 0) -#define MT6797_GPIO129__FUNC_MSDC1_CMD (MTK_PIN_NO(129) | 1) -#define MT6797_GPIO129__FUNC_CONN_DSP_JMS (MTK_PIN_NO(129) | 2) -#define MT6797_GPIO129__FUNC_LTE_JTAG_TMS (MTK_PIN_NO(129) | 3) -#define MT6797_GPIO129__FUNC_UDI_TMS (MTK_PIN_NO(129) | 4) -#define MT6797_GPIO129__FUNC_C2K_TMS (MTK_PIN_NO(129) | 5) - -#define MT6797_GPIO130__FUNC_GPIO130 (MTK_PIN_NO(130) | 0) -#define MT6797_GPIO130__FUNC_MSDC1_DAT0 (MTK_PIN_NO(130) | 1) -#define MT6797_GPIO130__FUNC_CONN_DSP_JDI (MTK_PIN_NO(130) | 2) -#define MT6797_GPIO130__FUNC_LTE_JTAG_TDI (MTK_PIN_NO(130) | 3) -#define MT6797_GPIO130__FUNC_UDI_TDI (MTK_PIN_NO(130) | 4) -#define MT6797_GPIO130__FUNC_C2K_TDI (MTK_PIN_NO(130) | 5) - -#define MT6797_GPIO131__FUNC_GPIO131 (MTK_PIN_NO(131) | 0) -#define MT6797_GPIO131__FUNC_MSDC1_DAT1 (MTK_PIN_NO(131) | 1) -#define MT6797_GPIO131__FUNC_CONN_DSP_JDO (MTK_PIN_NO(131) | 2) -#define MT6797_GPIO131__FUNC_LTE_JTAG_TDO (MTK_PIN_NO(131) | 3) -#define MT6797_GPIO131__FUNC_UDI_TDO (MTK_PIN_NO(131) | 4) -#define MT6797_GPIO131__FUNC_C2K_TDO (MTK_PIN_NO(131) | 5) - -#define MT6797_GPIO132__FUNC_GPIO132 (MTK_PIN_NO(132) | 0) -#define MT6797_GPIO132__FUNC_MSDC1_DAT2 (MTK_PIN_NO(132) | 1) -#define MT6797_GPIO132__FUNC_C2K_RTCK (MTK_PIN_NO(132) | 5) - -#define MT6797_GPIO133__FUNC_GPIO133 (MTK_PIN_NO(133) | 0) -#define MT6797_GPIO133__FUNC_MSDC1_DAT3 (MTK_PIN_NO(133) | 1) -#define MT6797_GPIO133__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(133) | 2) -#define MT6797_GPIO133__FUNC_LTE_JTAG_TRSTN (MTK_PIN_NO(133) | 3) -#define MT6797_GPIO133__FUNC_UDI_NTRST (MTK_PIN_NO(133) | 4) -#define MT6797_GPIO133__FUNC_C2K_NTRST (MTK_PIN_NO(133) | 5) - -#define MT6797_GPIO134__FUNC_GPIO134 (MTK_PIN_NO(134) | 0) -#define MT6797_GPIO134__FUNC_MSDC1_CLK (MTK_PIN_NO(134) | 1) -#define MT6797_GPIO134__FUNC_CONN_DSP_JCK (MTK_PIN_NO(134) | 2) -#define MT6797_GPIO134__FUNC_LTE_JTAG_TCK (MTK_PIN_NO(134) | 3) -#define MT6797_GPIO134__FUNC_UDI_TCK_XI (MTK_PIN_NO(134) | 4) -#define MT6797_GPIO134__FUNC_C2K_TCK (MTK_PIN_NO(134) | 5) - -#define MT6797_GPIO135__FUNC_GPIO135 (MTK_PIN_NO(135) | 0) -#define MT6797_GPIO135__FUNC_TDM_LRCK (MTK_PIN_NO(135) | 1) -#define MT6797_GPIO135__FUNC_I2S0_LRCK (MTK_PIN_NO(135) | 2) -#define MT6797_GPIO135__FUNC_CLKM0 (MTK_PIN_NO(135) | 3) -#define MT6797_GPIO135__FUNC_PCM1_SYNC (MTK_PIN_NO(135) | 4) -#define MT6797_GPIO135__FUNC_PWM_A (MTK_PIN_NO(135) | 5) -#define MT6797_GPIO135__FUNC_DBG_MON_A12 (MTK_PIN_NO(135) | 7) - -#define MT6797_GPIO136__FUNC_GPIO136 (MTK_PIN_NO(136) | 0) -#define MT6797_GPIO136__FUNC_TDM_BCK (MTK_PIN_NO(136) | 1) -#define MT6797_GPIO136__FUNC_I2S0_BCK (MTK_PIN_NO(136) | 2) -#define MT6797_GPIO136__FUNC_CLKM1 (MTK_PIN_NO(136) | 3) -#define MT6797_GPIO136__FUNC_PCM1_CLK (MTK_PIN_NO(136) | 4) -#define MT6797_GPIO136__FUNC_PWM_B (MTK_PIN_NO(136) | 5) -#define MT6797_GPIO136__FUNC_DBG_MON_A13 (MTK_PIN_NO(136) | 7) - -#define MT6797_GPIO137__FUNC_GPIO137 (MTK_PIN_NO(137) | 0) -#define MT6797_GPIO137__FUNC_TDM_MCK (MTK_PIN_NO(137) | 1) -#define MT6797_GPIO137__FUNC_I2S0_MCK (MTK_PIN_NO(137) | 2) -#define MT6797_GPIO137__FUNC_CLKM2 (MTK_PIN_NO(137) | 3) -#define MT6797_GPIO137__FUNC_PCM1_DI (MTK_PIN_NO(137) | 4) -#define MT6797_GPIO137__FUNC_IRTX_OUT (MTK_PIN_NO(137) | 5) -#define MT6797_GPIO137__FUNC_DBG_MON_A14 (MTK_PIN_NO(137) | 7) - -#define MT6797_GPIO138__FUNC_GPIO138 (MTK_PIN_NO(138) | 0) -#define MT6797_GPIO138__FUNC_TDM_DATA0 (MTK_PIN_NO(138) | 1) -#define MT6797_GPIO138__FUNC_I2S0_DI (MTK_PIN_NO(138) | 2) -#define MT6797_GPIO138__FUNC_CLKM3 (MTK_PIN_NO(138) | 3) -#define MT6797_GPIO138__FUNC_PCM1_DO0 (MTK_PIN_NO(138) | 4) -#define MT6797_GPIO138__FUNC_PWM_C (MTK_PIN_NO(138) | 5) -#define MT6797_GPIO138__FUNC_SDA3_1 (MTK_PIN_NO(138) | 6) -#define MT6797_GPIO138__FUNC_DBG_MON_A15 (MTK_PIN_NO(138) | 7) - -#define MT6797_GPIO139__FUNC_GPIO139 (MTK_PIN_NO(139) | 0) -#define MT6797_GPIO139__FUNC_TDM_DATA1 (MTK_PIN_NO(139) | 1) -#define MT6797_GPIO139__FUNC_I2S3_DO (MTK_PIN_NO(139) | 2) -#define MT6797_GPIO139__FUNC_CLKM4 (MTK_PIN_NO(139) | 3) -#define MT6797_GPIO139__FUNC_PCM1_DO1 (MTK_PIN_NO(139) | 4) -#define MT6797_GPIO139__FUNC_ANT_SEL2 (MTK_PIN_NO(139) | 5) -#define MT6797_GPIO139__FUNC_SCL3_1 (MTK_PIN_NO(139) | 6) -#define MT6797_GPIO139__FUNC_DBG_MON_A16 (MTK_PIN_NO(139) | 7) - -#define MT6797_GPIO140__FUNC_GPIO140 (MTK_PIN_NO(140) | 0) -#define MT6797_GPIO140__FUNC_TDM_DATA2 (MTK_PIN_NO(140) | 1) -#define MT6797_GPIO140__FUNC_DISP_PWM (MTK_PIN_NO(140) | 2) -#define MT6797_GPIO140__FUNC_CLKM5 (MTK_PIN_NO(140) | 3) -#define MT6797_GPIO140__FUNC_SDA1_4 (MTK_PIN_NO(140) | 4) -#define MT6797_GPIO140__FUNC_ANT_SEL1 (MTK_PIN_NO(140) | 5) -#define MT6797_GPIO140__FUNC_URXD3 (MTK_PIN_NO(140) | 6) -#define MT6797_GPIO140__FUNC_DBG_MON_A17 (MTK_PIN_NO(140) | 7) - -#define MT6797_GPIO141__FUNC_GPIO141 (MTK_PIN_NO(141) | 0) -#define MT6797_GPIO141__FUNC_TDM_DATA3 (MTK_PIN_NO(141) | 1) -#define MT6797_GPIO141__FUNC_CMFLASH (MTK_PIN_NO(141) | 2) -#define MT6797_GPIO141__FUNC_IRTX_OUT (MTK_PIN_NO(141) | 3) -#define MT6797_GPIO141__FUNC_SCL1_4 (MTK_PIN_NO(141) | 4) -#define MT6797_GPIO141__FUNC_ANT_SEL0 (MTK_PIN_NO(141) | 5) -#define MT6797_GPIO141__FUNC_UTXD3 (MTK_PIN_NO(141) | 6) -#define MT6797_GPIO141__FUNC_DBG_MON_A18 (MTK_PIN_NO(141) | 7) - -#define MT6797_GPIO142__FUNC_GPIO142 (MTK_PIN_NO(142) | 0) -#define MT6797_GPIO142__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(142) | 1) -#define MT6797_GPIO142__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(142) | 2) - -#define MT6797_GPIO143__FUNC_GPIO143 (MTK_PIN_NO(143) | 0) -#define MT6797_GPIO143__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(143) | 1) -#define MT6797_GPIO143__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(143) | 2) - -#define MT6797_GPIO144__FUNC_GPIO144 (MTK_PIN_NO(144) | 0) -#define MT6797_GPIO144__FUNC_PWRAP_SPI0_CK (MTK_PIN_NO(144) | 1) - -#define MT6797_GPIO145__FUNC_GPIO145 (MTK_PIN_NO(145) | 0) -#define MT6797_GPIO145__FUNC_PWRAP_SPI0_CSN (MTK_PIN_NO(145) | 1) - -#define MT6797_GPIO146__FUNC_GPIO146 (MTK_PIN_NO(146) | 0) -#define MT6797_GPIO146__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(146) | 1) - -#define MT6797_GPIO147__FUNC_GPIO147 (MTK_PIN_NO(147) | 0) -#define MT6797_GPIO147__FUNC_AUD_DAT_MISO (MTK_PIN_NO(147) | 1) -#define MT6797_GPIO147__FUNC_AUD_DAT_MOSI (MTK_PIN_NO(147) | 2) -#define MT6797_GPIO147__FUNC_VOW_DAT_MISO (MTK_PIN_NO(147) | 3) - -#define MT6797_GPIO148__FUNC_GPIO148 (MTK_PIN_NO(148) | 0) -#define MT6797_GPIO148__FUNC_AUD_DAT_MOSI (MTK_PIN_NO(148) | 1) -#define MT6797_GPIO148__FUNC_AUD_DAT_MISO (MTK_PIN_NO(148) | 2) - -#define MT6797_GPIO149__FUNC_GPIO149 (MTK_PIN_NO(149) | 0) -#define MT6797_GPIO149__FUNC_VOW_CLK_MISO (MTK_PIN_NO(149) | 1) - -#define MT6797_GPIO150__FUNC_GPIO150 (MTK_PIN_NO(150) | 0) -#define MT6797_GPIO150__FUNC_ANC_DAT_MOSI (MTK_PIN_NO(150) | 1) - -#define MT6797_GPIO151__FUNC_GPIO151 (MTK_PIN_NO(151) | 0) -#define MT6797_GPIO151__FUNC_SCL6_0 (MTK_PIN_NO(151) | 1) - -#define MT6797_GPIO152__FUNC_GPIO152 (MTK_PIN_NO(152) | 0) -#define MT6797_GPIO152__FUNC_SDA6_0 (MTK_PIN_NO(152) | 1) - -#define MT6797_GPIO153__FUNC_GPIO153 (MTK_PIN_NO(153) | 0) -#define MT6797_GPIO153__FUNC_SCL7_0 (MTK_PIN_NO(153) | 1) - -#define MT6797_GPIO154__FUNC_GPIO154 (MTK_PIN_NO(154) | 0) -#define MT6797_GPIO154__FUNC_SDA7_0 (MTK_PIN_NO(154) | 1) - -#define MT6797_GPIO155__FUNC_GPIO155 (MTK_PIN_NO(155) | 0) -#define MT6797_GPIO155__FUNC_MD1_SIM2_SCLK (MTK_PIN_NO(155) | 1) -#define MT6797_GPIO155__FUNC_MD1_SIM1_SCLK (MTK_PIN_NO(155) | 2) -#define MT6797_GPIO155__FUNC_C2K_UIM0_CLK (MTK_PIN_NO(155) | 3) -#define MT6797_GPIO155__FUNC_C2K_UIM1_CLK (MTK_PIN_NO(155) | 4) - -#define MT6797_GPIO156__FUNC_GPIO156 (MTK_PIN_NO(156) | 0) -#define MT6797_GPIO156__FUNC_MD1_SIM2_SRST (MTK_PIN_NO(156) | 1) -#define MT6797_GPIO156__FUNC_MD1_SIM1_SRST (MTK_PIN_NO(156) | 2) -#define MT6797_GPIO156__FUNC_C2K_UIM0_RST (MTK_PIN_NO(156) | 3) -#define MT6797_GPIO156__FUNC_C2K_UIM1_RST (MTK_PIN_NO(156) | 4) - -#define MT6797_GPIO157__FUNC_GPIO157 (MTK_PIN_NO(157) | 0) -#define MT6797_GPIO157__FUNC_MD1_SIM2_SIO (MTK_PIN_NO(157) | 1) -#define MT6797_GPIO157__FUNC_MD1_SIM1_SIO (MTK_PIN_NO(157) | 2) -#define MT6797_GPIO157__FUNC_C2K_UIM0_IO (MTK_PIN_NO(157) | 3) -#define MT6797_GPIO157__FUNC_C2K_UIM1_IO (MTK_PIN_NO(157) | 4) - -#define MT6797_GPIO158__FUNC_GPIO158 (MTK_PIN_NO(158) | 0) -#define MT6797_GPIO158__FUNC_MIPI_TDP0 (MTK_PIN_NO(158) | 1) - -#define MT6797_GPIO159__FUNC_GPIO159 (MTK_PIN_NO(159) | 0) -#define MT6797_GPIO159__FUNC_MIPI_TDN0 (MTK_PIN_NO(159) | 1) - -#define MT6797_GPIO160__FUNC_GPIO160 (MTK_PIN_NO(160) | 0) -#define MT6797_GPIO160__FUNC_MIPI_TDP1 (MTK_PIN_NO(160) | 1) - -#define MT6797_GPIO161__FUNC_GPIO161 (MTK_PIN_NO(161) | 0) -#define MT6797_GPIO161__FUNC_MIPI_TDN1 (MTK_PIN_NO(161) | 1) - -#define MT6797_GPIO162__FUNC_GPIO162 (MTK_PIN_NO(162) | 0) -#define MT6797_GPIO162__FUNC_MIPI_TCP (MTK_PIN_NO(162) | 1) - -#define MT6797_GPIO163__FUNC_GPIO163 (MTK_PIN_NO(163) | 0) -#define MT6797_GPIO163__FUNC_MIPI_TCN (MTK_PIN_NO(163) | 1) - -#define MT6797_GPIO164__FUNC_GPIO164 (MTK_PIN_NO(164) | 0) -#define MT6797_GPIO164__FUNC_MIPI_TDP2 (MTK_PIN_NO(164) | 1) - -#define MT6797_GPIO165__FUNC_GPIO165 (MTK_PIN_NO(165) | 0) -#define MT6797_GPIO165__FUNC_MIPI_TDN2 (MTK_PIN_NO(165) | 1) - -#define MT6797_GPIO166__FUNC_GPIO166 (MTK_PIN_NO(166) | 0) -#define MT6797_GPIO166__FUNC_MIPI_TDP3 (MTK_PIN_NO(166) | 1) - -#define MT6797_GPIO167__FUNC_GPIO167 (MTK_PIN_NO(167) | 0) -#define MT6797_GPIO167__FUNC_MIPI_TDN3 (MTK_PIN_NO(167) | 1) - -#define MT6797_GPIO168__FUNC_GPIO168 (MTK_PIN_NO(168) | 0) -#define MT6797_GPIO168__FUNC_MIPI_TDP0_A (MTK_PIN_NO(168) | 1) - -#define MT6797_GPIO169__FUNC_GPIO169 (MTK_PIN_NO(169) | 0) -#define MT6797_GPIO169__FUNC_MIPI_TDN0_A (MTK_PIN_NO(169) | 1) - -#define MT6797_GPIO170__FUNC_GPIO170 (MTK_PIN_NO(170) | 0) -#define MT6797_GPIO170__FUNC_MIPI_TDP1_A (MTK_PIN_NO(170) | 1) - -#define MT6797_GPIO171__FUNC_GPIO171 (MTK_PIN_NO(171) | 0) -#define MT6797_GPIO171__FUNC_MIPI_TDN1_A (MTK_PIN_NO(171) | 1) - -#define MT6797_GPIO172__FUNC_GPIO172 (MTK_PIN_NO(172) | 0) -#define MT6797_GPIO172__FUNC_MIPI_TCP_A (MTK_PIN_NO(172) | 1) - -#define MT6797_GPIO173__FUNC_GPIO173 (MTK_PIN_NO(173) | 0) -#define MT6797_GPIO173__FUNC_MIPI_TCN_A (MTK_PIN_NO(173) | 1) - -#define MT6797_GPIO174__FUNC_GPIO174 (MTK_PIN_NO(174) | 0) -#define MT6797_GPIO174__FUNC_MIPI_TDP2_A (MTK_PIN_NO(174) | 1) - -#define MT6797_GPIO175__FUNC_GPIO175 (MTK_PIN_NO(175) | 0) -#define MT6797_GPIO175__FUNC_MIPI_TDN2_A (MTK_PIN_NO(175) | 1) - -#define MT6797_GPIO176__FUNC_GPIO176 (MTK_PIN_NO(176) | 0) -#define MT6797_GPIO176__FUNC_MIPI_TDP3_A (MTK_PIN_NO(176) | 1) - -#define MT6797_GPIO177__FUNC_GPIO177 (MTK_PIN_NO(177) | 0) -#define MT6797_GPIO177__FUNC_MIPI_TDN3_A (MTK_PIN_NO(177) | 1) - -#define MT6797_GPIO178__FUNC_GPIO178 (MTK_PIN_NO(178) | 0) -#define MT6797_GPIO178__FUNC_DISP_PWM (MTK_PIN_NO(178) | 1) -#define MT6797_GPIO178__FUNC_PWM_D (MTK_PIN_NO(178) | 2) -#define MT6797_GPIO178__FUNC_CLKM5 (MTK_PIN_NO(178) | 3) -#define MT6797_GPIO178__FUNC_DBG_MON_A19 (MTK_PIN_NO(178) | 7) - -#define MT6797_GPIO179__FUNC_GPIO179 (MTK_PIN_NO(179) | 0) -#define MT6797_GPIO179__FUNC_DSI_TE0 (MTK_PIN_NO(179) | 1) -#define MT6797_GPIO179__FUNC_DBG_MON_A20 (MTK_PIN_NO(179) | 7) - -#define MT6797_GPIO180__FUNC_GPIO180 (MTK_PIN_NO(180) | 0) -#define MT6797_GPIO180__FUNC_LCM_RST (MTK_PIN_NO(180) | 1) -#define MT6797_GPIO180__FUNC_DSI_TE1 (MTK_PIN_NO(180) | 2) -#define MT6797_GPIO180__FUNC_DBG_MON_A21 (MTK_PIN_NO(180) | 7) - -#define MT6797_GPIO181__FUNC_GPIO181 (MTK_PIN_NO(181) | 0) -#define MT6797_GPIO181__FUNC_IDDIG (MTK_PIN_NO(181) | 1) -#define MT6797_GPIO181__FUNC_DSI_TE1 (MTK_PIN_NO(181) | 2) -#define MT6797_GPIO181__FUNC_DBG_MON_A22 (MTK_PIN_NO(181) | 7) - -#define MT6797_GPIO182__FUNC_GPIO182 (MTK_PIN_NO(182) | 0) -#define MT6797_GPIO182__FUNC_TESTMODE (MTK_PIN_NO(182) | 1) - -#define MT6797_GPIO183__FUNC_GPIO183 (MTK_PIN_NO(183) | 0) -#define MT6797_GPIO183__FUNC_RFIC0_BSI_CK (MTK_PIN_NO(183) | 1) -#define MT6797_GPIO183__FUNC_SPM_BSI_CK (MTK_PIN_NO(183) | 2) -#define MT6797_GPIO183__FUNC_DBG_MON_B27 (MTK_PIN_NO(183) | 7) - -#define MT6797_GPIO184__FUNC_GPIO184 (MTK_PIN_NO(184) | 0) -#define MT6797_GPIO184__FUNC_RFIC0_BSI_EN (MTK_PIN_NO(184) | 1) -#define MT6797_GPIO184__FUNC_SPM_BSI_EN (MTK_PIN_NO(184) | 2) -#define MT6797_GPIO184__FUNC_DBG_MON_B28 (MTK_PIN_NO(184) | 7) - -#define MT6797_GPIO185__FUNC_GPIO185 (MTK_PIN_NO(185) | 0) -#define MT6797_GPIO185__FUNC_RFIC0_BSI_D0 (MTK_PIN_NO(185) | 1) -#define MT6797_GPIO185__FUNC_SPM_BSI_D0 (MTK_PIN_NO(185) | 2) -#define MT6797_GPIO185__FUNC_DBG_MON_B29 (MTK_PIN_NO(185) | 7) - -#define MT6797_GPIO186__FUNC_GPIO186 (MTK_PIN_NO(186) | 0) -#define MT6797_GPIO186__FUNC_RFIC0_BSI_D1 (MTK_PIN_NO(186) | 1) -#define MT6797_GPIO186__FUNC_SPM_BSI_D1 (MTK_PIN_NO(186) | 2) -#define MT6797_GPIO186__FUNC_DBG_MON_B30 (MTK_PIN_NO(186) | 7) - -#define MT6797_GPIO187__FUNC_GPIO187 (MTK_PIN_NO(187) | 0) -#define MT6797_GPIO187__FUNC_RFIC0_BSI_D2 (MTK_PIN_NO(187) | 1) -#define MT6797_GPIO187__FUNC_SPM_BSI_D2 (MTK_PIN_NO(187) | 2) -#define MT6797_GPIO187__FUNC_DBG_MON_B31 (MTK_PIN_NO(187) | 7) - -#define MT6797_GPIO188__FUNC_GPIO188 (MTK_PIN_NO(188) | 0) -#define MT6797_GPIO188__FUNC_MIPI0_SCLK (MTK_PIN_NO(188) | 1) -#define MT6797_GPIO188__FUNC_DBG_MON_B32 (MTK_PIN_NO(188) | 7) - -#define MT6797_GPIO189__FUNC_GPIO189 (MTK_PIN_NO(189) | 0) -#define MT6797_GPIO189__FUNC_MIPI0_SDATA (MTK_PIN_NO(189) | 1) - -#define MT6797_GPIO190__FUNC_GPIO190 (MTK_PIN_NO(190) | 0) -#define MT6797_GPIO190__FUNC_MIPI1_SCLK (MTK_PIN_NO(190) | 1) - -#define MT6797_GPIO191__FUNC_GPIO191 (MTK_PIN_NO(191) | 0) -#define MT6797_GPIO191__FUNC_MIPI1_SDATA (MTK_PIN_NO(191) | 1) - -#define MT6797_GPIO192__FUNC_GPIO192 (MTK_PIN_NO(192) | 0) -#define MT6797_GPIO192__FUNC_BPI_BUS4 (MTK_PIN_NO(192) | 1) - -#define MT6797_GPIO193__FUNC_GPIO193 (MTK_PIN_NO(193) | 0) -#define MT6797_GPIO193__FUNC_BPI_BUS5 (MTK_PIN_NO(193) | 1) -#define MT6797_GPIO193__FUNC_DBG_MON_B0 (MTK_PIN_NO(193) | 7) - -#define MT6797_GPIO194__FUNC_GPIO194 (MTK_PIN_NO(194) | 0) -#define MT6797_GPIO194__FUNC_BPI_BUS6 (MTK_PIN_NO(194) | 1) -#define MT6797_GPIO194__FUNC_DBG_MON_B1 (MTK_PIN_NO(194) | 7) - -#define MT6797_GPIO195__FUNC_GPIO195 (MTK_PIN_NO(195) | 0) -#define MT6797_GPIO195__FUNC_BPI_BUS7 (MTK_PIN_NO(195) | 1) -#define MT6797_GPIO195__FUNC_DBG_MON_B2 (MTK_PIN_NO(195) | 7) - -#define MT6797_GPIO196__FUNC_GPIO196 (MTK_PIN_NO(196) | 0) -#define MT6797_GPIO196__FUNC_BPI_BUS8 (MTK_PIN_NO(196) | 1) -#define MT6797_GPIO196__FUNC_DBG_MON_B3 (MTK_PIN_NO(196) | 7) - -#define MT6797_GPIO197__FUNC_GPIO197 (MTK_PIN_NO(197) | 0) -#define MT6797_GPIO197__FUNC_BPI_BUS9 (MTK_PIN_NO(197) | 1) -#define MT6797_GPIO197__FUNC_DBG_MON_B4 (MTK_PIN_NO(197) | 7) - -#define MT6797_GPIO198__FUNC_GPIO198 (MTK_PIN_NO(198) | 0) -#define MT6797_GPIO198__FUNC_BPI_BUS10 (MTK_PIN_NO(198) | 1) -#define MT6797_GPIO198__FUNC_DBG_MON_B5 (MTK_PIN_NO(198) | 7) - -#define MT6797_GPIO199__FUNC_GPIO199 (MTK_PIN_NO(199) | 0) -#define MT6797_GPIO199__FUNC_BPI_BUS11 (MTK_PIN_NO(199) | 1) -#define MT6797_GPIO199__FUNC_DBG_MON_B6 (MTK_PIN_NO(199) | 7) - -#define MT6797_GPIO200__FUNC_GPIO200 (MTK_PIN_NO(200) | 0) -#define MT6797_GPIO200__FUNC_BPI_BUS12 (MTK_PIN_NO(200) | 1) -#define MT6797_GPIO200__FUNC_DBG_MON_B7 (MTK_PIN_NO(200) | 7) - -#define MT6797_GPIO201__FUNC_GPIO201 (MTK_PIN_NO(201) | 0) -#define MT6797_GPIO201__FUNC_BPI_BUS13 (MTK_PIN_NO(201) | 1) -#define MT6797_GPIO201__FUNC_DBG_MON_B8 (MTK_PIN_NO(201) | 7) - -#define MT6797_GPIO202__FUNC_GPIO202 (MTK_PIN_NO(202) | 0) -#define MT6797_GPIO202__FUNC_BPI_BUS14 (MTK_PIN_NO(202) | 1) -#define MT6797_GPIO202__FUNC_DBG_MON_B9 (MTK_PIN_NO(202) | 7) - -#define MT6797_GPIO203__FUNC_GPIO203 (MTK_PIN_NO(203) | 0) -#define MT6797_GPIO203__FUNC_BPI_BUS15 (MTK_PIN_NO(203) | 1) -#define MT6797_GPIO203__FUNC_DBG_MON_B10 (MTK_PIN_NO(203) | 7) - -#define MT6797_GPIO204__FUNC_GPIO204 (MTK_PIN_NO(204) | 0) -#define MT6797_GPIO204__FUNC_BPI_BUS16 (MTK_PIN_NO(204) | 1) -#define MT6797_GPIO204__FUNC_PA_VM0 (MTK_PIN_NO(204) | 2) -#define MT6797_GPIO204__FUNC_DBG_MON_B11 (MTK_PIN_NO(204) | 7) - -#define MT6797_GPIO205__FUNC_GPIO205 (MTK_PIN_NO(205) | 0) -#define MT6797_GPIO205__FUNC_BPI_BUS17 (MTK_PIN_NO(205) | 1) -#define MT6797_GPIO205__FUNC_PA_VM1 (MTK_PIN_NO(205) | 2) -#define MT6797_GPIO205__FUNC_DBG_MON_B12 (MTK_PIN_NO(205) | 7) - -#define MT6797_GPIO206__FUNC_GPIO206 (MTK_PIN_NO(206) | 0) -#define MT6797_GPIO206__FUNC_BPI_BUS18 (MTK_PIN_NO(206) | 1) -#define MT6797_GPIO206__FUNC_TX_SWAP0 (MTK_PIN_NO(206) | 2) -#define MT6797_GPIO206__FUNC_DBG_MON_B13 (MTK_PIN_NO(206) | 7) - -#define MT6797_GPIO207__FUNC_GPIO207 (MTK_PIN_NO(207) | 0) -#define MT6797_GPIO207__FUNC_BPI_BUS19 (MTK_PIN_NO(207) | 1) -#define MT6797_GPIO207__FUNC_TX_SWAP1 (MTK_PIN_NO(207) | 2) -#define MT6797_GPIO207__FUNC_DBG_MON_B14 (MTK_PIN_NO(207) | 7) - -#define MT6797_GPIO208__FUNC_GPIO208 (MTK_PIN_NO(208) | 0) -#define MT6797_GPIO208__FUNC_BPI_BUS20 (MTK_PIN_NO(208) | 1) -#define MT6797_GPIO208__FUNC_TX_SWAP2 (MTK_PIN_NO(208) | 2) -#define MT6797_GPIO208__FUNC_DBG_MON_B15 (MTK_PIN_NO(208) | 7) - -#define MT6797_GPIO209__FUNC_GPIO209 (MTK_PIN_NO(209) | 0) -#define MT6797_GPIO209__FUNC_BPI_BUS21 (MTK_PIN_NO(209) | 1) -#define MT6797_GPIO209__FUNC_TX_SWAP3 (MTK_PIN_NO(209) | 2) -#define MT6797_GPIO209__FUNC_DBG_MON_B16 (MTK_PIN_NO(209) | 7) - -#define MT6797_GPIO210__FUNC_GPIO210 (MTK_PIN_NO(210) | 0) -#define MT6797_GPIO210__FUNC_BPI_BUS22 (MTK_PIN_NO(210) | 1) -#define MT6797_GPIO210__FUNC_DET_BPI0 (MTK_PIN_NO(210) | 2) -#define MT6797_GPIO210__FUNC_DBG_MON_B17 (MTK_PIN_NO(210) | 7) - -#define MT6797_GPIO211__FUNC_GPIO211 (MTK_PIN_NO(211) | 0) -#define MT6797_GPIO211__FUNC_BPI_BUS23 (MTK_PIN_NO(211) | 1) -#define MT6797_GPIO211__FUNC_DET_BPI1 (MTK_PIN_NO(211) | 2) -#define MT6797_GPIO211__FUNC_DBG_MON_B18 (MTK_PIN_NO(211) | 7) - -#define MT6797_GPIO212__FUNC_GPIO212 (MTK_PIN_NO(212) | 0) -#define MT6797_GPIO212__FUNC_BPI_BUS0 (MTK_PIN_NO(212) | 1) -#define MT6797_GPIO212__FUNC_DBG_MON_B19 (MTK_PIN_NO(212) | 7) - -#define MT6797_GPIO213__FUNC_GPIO213 (MTK_PIN_NO(213) | 0) -#define MT6797_GPIO213__FUNC_BPI_BUS1 (MTK_PIN_NO(213) | 1) -#define MT6797_GPIO213__FUNC_DBG_MON_B20 (MTK_PIN_NO(213) | 7) - -#define MT6797_GPIO214__FUNC_GPIO214 (MTK_PIN_NO(214) | 0) -#define MT6797_GPIO214__FUNC_BPI_BUS2 (MTK_PIN_NO(214) | 1) -#define MT6797_GPIO214__FUNC_DBG_MON_B21 (MTK_PIN_NO(214) | 7) - -#define MT6797_GPIO215__FUNC_GPIO215 (MTK_PIN_NO(215) | 0) -#define MT6797_GPIO215__FUNC_BPI_BUS3 (MTK_PIN_NO(215) | 1) -#define MT6797_GPIO215__FUNC_DBG_MON_B22 (MTK_PIN_NO(215) | 7) - -#define MT6797_GPIO216__FUNC_GPIO216 (MTK_PIN_NO(216) | 0) -#define MT6797_GPIO216__FUNC_MIPI2_SCLK (MTK_PIN_NO(216) | 1) -#define MT6797_GPIO216__FUNC_DBG_MON_B23 (MTK_PIN_NO(216) | 7) - -#define MT6797_GPIO217__FUNC_GPIO217 (MTK_PIN_NO(217) | 0) -#define MT6797_GPIO217__FUNC_MIPI2_SDATA (MTK_PIN_NO(217) | 1) -#define MT6797_GPIO217__FUNC_DBG_MON_B24 (MTK_PIN_NO(217) | 7) - -#define MT6797_GPIO218__FUNC_GPIO218 (MTK_PIN_NO(218) | 0) -#define MT6797_GPIO218__FUNC_MIPI3_SCLK (MTK_PIN_NO(218) | 1) -#define MT6797_GPIO218__FUNC_DBG_MON_B25 (MTK_PIN_NO(218) | 7) - -#define MT6797_GPIO219__FUNC_GPIO219 (MTK_PIN_NO(219) | 0) -#define MT6797_GPIO219__FUNC_MIPI3_SDATA (MTK_PIN_NO(219) | 1) -#define MT6797_GPIO219__FUNC_DBG_MON_B26 (MTK_PIN_NO(219) | 7) - -#define MT6797_GPIO220__FUNC_GPIO220 (MTK_PIN_NO(220) | 0) -#define MT6797_GPIO220__FUNC_CONN_WF_IP (MTK_PIN_NO(220) | 1) - -#define MT6797_GPIO221__FUNC_GPIO221 (MTK_PIN_NO(221) | 0) -#define MT6797_GPIO221__FUNC_CONN_WF_IN (MTK_PIN_NO(221) | 1) - -#define MT6797_GPIO222__FUNC_GPIO222 (MTK_PIN_NO(222) | 0) -#define MT6797_GPIO222__FUNC_CONN_WF_QP (MTK_PIN_NO(222) | 1) - -#define MT6797_GPIO223__FUNC_GPIO223 (MTK_PIN_NO(223) | 0) -#define MT6797_GPIO223__FUNC_CONN_WF_QN (MTK_PIN_NO(223) | 1) - -#define MT6797_GPIO224__FUNC_GPIO224 (MTK_PIN_NO(224) | 0) -#define MT6797_GPIO224__FUNC_CONN_BT_IP (MTK_PIN_NO(224) | 1) - -#define MT6797_GPIO225__FUNC_GPIO225 (MTK_PIN_NO(225) | 0) -#define MT6797_GPIO225__FUNC_CONN_BT_IN (MTK_PIN_NO(225) | 1) - -#define MT6797_GPIO226__FUNC_GPIO226 (MTK_PIN_NO(226) | 0) -#define MT6797_GPIO226__FUNC_CONN_BT_QP (MTK_PIN_NO(226) | 1) - -#define MT6797_GPIO227__FUNC_GPIO227 (MTK_PIN_NO(227) | 0) -#define MT6797_GPIO227__FUNC_CONN_BT_QN (MTK_PIN_NO(227) | 1) - -#define MT6797_GPIO228__FUNC_GPIO228 (MTK_PIN_NO(228) | 0) -#define MT6797_GPIO228__FUNC_CONN_GPS_IP (MTK_PIN_NO(228) | 1) - -#define MT6797_GPIO229__FUNC_GPIO229 (MTK_PIN_NO(229) | 0) -#define MT6797_GPIO229__FUNC_CONN_GPS_IN (MTK_PIN_NO(229) | 1) - -#define MT6797_GPIO230__FUNC_GPIO230 (MTK_PIN_NO(230) | 0) -#define MT6797_GPIO230__FUNC_CONN_GPS_QP (MTK_PIN_NO(230) | 1) - -#define MT6797_GPIO231__FUNC_GPIO231 (MTK_PIN_NO(231) | 0) -#define MT6797_GPIO231__FUNC_CONN_GPS_QN (MTK_PIN_NO(231) | 1) - -#define MT6797_GPIO232__FUNC_GPIO232 (MTK_PIN_NO(232) | 0) -#define MT6797_GPIO232__FUNC_URXD1 (MTK_PIN_NO(232) | 1) -#define MT6797_GPIO232__FUNC_UTXD1 (MTK_PIN_NO(232) | 2) -#define MT6797_GPIO232__FUNC_MD_URXD0 (MTK_PIN_NO(232) | 3) -#define MT6797_GPIO232__FUNC_MD_URXD1 (MTK_PIN_NO(232) | 4) -#define MT6797_GPIO232__FUNC_MD_URXD2 (MTK_PIN_NO(232) | 5) -#define MT6797_GPIO232__FUNC_C2K_URXD0 (MTK_PIN_NO(232) | 6) -#define MT6797_GPIO232__FUNC_C2K_URXD1 (MTK_PIN_NO(232) | 7) - -#define MT6797_GPIO233__FUNC_GPIO233 (MTK_PIN_NO(233) | 0) -#define MT6797_GPIO233__FUNC_UTXD1 (MTK_PIN_NO(233) | 1) -#define MT6797_GPIO233__FUNC_URXD1 (MTK_PIN_NO(233) | 2) -#define MT6797_GPIO233__FUNC_MD_UTXD0 (MTK_PIN_NO(233) | 3) -#define MT6797_GPIO233__FUNC_MD_UTXD1 (MTK_PIN_NO(233) | 4) -#define MT6797_GPIO233__FUNC_MD_UTXD2 (MTK_PIN_NO(233) | 5) -#define MT6797_GPIO233__FUNC_C2K_UTXD0 (MTK_PIN_NO(233) | 6) -#define MT6797_GPIO233__FUNC_C2K_UTXD1 (MTK_PIN_NO(233) | 7) - -#define MT6797_GPIO234__FUNC_GPIO234 (MTK_PIN_NO(234) | 0) -#define MT6797_GPIO234__FUNC_SPI1_CLK_B (MTK_PIN_NO(234) | 1) -#define MT6797_GPIO234__FUNC_TP_UTXD1_AO (MTK_PIN_NO(234) | 2) -#define MT6797_GPIO234__FUNC_SCL4_1 (MTK_PIN_NO(234) | 3) -#define MT6797_GPIO234__FUNC_UTXD0 (MTK_PIN_NO(234) | 4) -#define MT6797_GPIO234__FUNC_PWM_A (MTK_PIN_NO(234) | 6) -#define MT6797_GPIO234__FUNC_DBG_MON_A23 (MTK_PIN_NO(234) | 7) - -#define MT6797_GPIO235__FUNC_GPIO235 (MTK_PIN_NO(235) | 0) -#define MT6797_GPIO235__FUNC_SPI1_MI_B (MTK_PIN_NO(235) | 1) -#define MT6797_GPIO235__FUNC_SPI1_MO_B (MTK_PIN_NO(235) | 2) -#define MT6797_GPIO235__FUNC_SDA4_1 (MTK_PIN_NO(235) | 3) -#define MT6797_GPIO235__FUNC_URXD0 (MTK_PIN_NO(235) | 4) -#define MT6797_GPIO235__FUNC_CLKM0 (MTK_PIN_NO(235) | 6) -#define MT6797_GPIO235__FUNC_DBG_MON_A24 (MTK_PIN_NO(235) | 7) - -#define MT6797_GPIO236__FUNC_GPIO236 (MTK_PIN_NO(236) | 0) -#define MT6797_GPIO236__FUNC_SPI1_MO_B (MTK_PIN_NO(236) | 1) -#define MT6797_GPIO236__FUNC_SPI1_MI_B (MTK_PIN_NO(236) | 2) -#define MT6797_GPIO236__FUNC_SCL5_1 (MTK_PIN_NO(236) | 3) -#define MT6797_GPIO236__FUNC_URTS0 (MTK_PIN_NO(236) | 4) -#define MT6797_GPIO236__FUNC_PWM_B (MTK_PIN_NO(236) | 6) -#define MT6797_GPIO236__FUNC_DBG_MON_A25 (MTK_PIN_NO(236) | 7) - -#define MT6797_GPIO237__FUNC_GPIO237 (MTK_PIN_NO(237) | 0) -#define MT6797_GPIO237__FUNC_SPI1_CS_B (MTK_PIN_NO(237) | 1) -#define MT6797_GPIO237__FUNC_TP_URXD1_AO (MTK_PIN_NO(237) | 2) -#define MT6797_GPIO237__FUNC_SDA5_1 (MTK_PIN_NO(237) | 3) -#define MT6797_GPIO237__FUNC_UCTS0 (MTK_PIN_NO(237) | 4) -#define MT6797_GPIO237__FUNC_CLKM1 (MTK_PIN_NO(237) | 6) -#define MT6797_GPIO237__FUNC_DBG_MON_A26 (MTK_PIN_NO(237) | 7) - -#define MT6797_GPIO238__FUNC_GPIO238 (MTK_PIN_NO(238) | 0) -#define MT6797_GPIO238__FUNC_SDA4_0 (MTK_PIN_NO(238) | 1) - -#define MT6797_GPIO239__FUNC_GPIO239 (MTK_PIN_NO(239) | 0) -#define MT6797_GPIO239__FUNC_SCL4_0 (MTK_PIN_NO(239) | 1) - -#define MT6797_GPIO240__FUNC_GPIO240 (MTK_PIN_NO(240) | 0) -#define MT6797_GPIO240__FUNC_SDA5_0 (MTK_PIN_NO(240) | 1) - -#define MT6797_GPIO241__FUNC_GPIO241 (MTK_PIN_NO(241) | 0) -#define MT6797_GPIO241__FUNC_SCL5_0 (MTK_PIN_NO(241) | 1) - -#define MT6797_GPIO242__FUNC_GPIO242 (MTK_PIN_NO(242) | 0) -#define MT6797_GPIO242__FUNC_SPI2_CLK_B (MTK_PIN_NO(242) | 1) -#define MT6797_GPIO242__FUNC_TP_UTXD2_AO (MTK_PIN_NO(242) | 2) -#define MT6797_GPIO242__FUNC_SCL4_2 (MTK_PIN_NO(242) | 3) -#define MT6797_GPIO242__FUNC_UTXD1 (MTK_PIN_NO(242) | 4) -#define MT6797_GPIO242__FUNC_URTS3 (MTK_PIN_NO(242) | 5) -#define MT6797_GPIO242__FUNC_PWM_C (MTK_PIN_NO(242) | 6) -#define MT6797_GPIO242__FUNC_DBG_MON_A27 (MTK_PIN_NO(242) | 7) - -#define MT6797_GPIO243__FUNC_GPIO243 (MTK_PIN_NO(243) | 0) -#define MT6797_GPIO243__FUNC_SPI2_MI_B (MTK_PIN_NO(243) | 1) -#define MT6797_GPIO243__FUNC_SPI2_MO_B (MTK_PIN_NO(243) | 2) -#define MT6797_GPIO243__FUNC_SDA4_2 (MTK_PIN_NO(243) | 3) -#define MT6797_GPIO243__FUNC_URXD1 (MTK_PIN_NO(243) | 4) -#define MT6797_GPIO243__FUNC_UCTS3 (MTK_PIN_NO(243) | 5) -#define MT6797_GPIO243__FUNC_CLKM2 (MTK_PIN_NO(243) | 6) -#define MT6797_GPIO243__FUNC_DBG_MON_A28 (MTK_PIN_NO(243) | 7) - -#define MT6797_GPIO244__FUNC_GPIO244 (MTK_PIN_NO(244) | 0) -#define MT6797_GPIO244__FUNC_SPI2_MO_B (MTK_PIN_NO(244) | 1) -#define MT6797_GPIO244__FUNC_SPI2_MI_B (MTK_PIN_NO(244) | 2) -#define MT6797_GPIO244__FUNC_SCL5_2 (MTK_PIN_NO(244) | 3) -#define MT6797_GPIO244__FUNC_URTS1 (MTK_PIN_NO(244) | 4) -#define MT6797_GPIO244__FUNC_UTXD3 (MTK_PIN_NO(244) | 5) -#define MT6797_GPIO244__FUNC_PWM_D (MTK_PIN_NO(244) | 6) -#define MT6797_GPIO244__FUNC_DBG_MON_A29 (MTK_PIN_NO(244) | 7) - -#define MT6797_GPIO245__FUNC_GPIO245 (MTK_PIN_NO(245) | 0) -#define MT6797_GPIO245__FUNC_SPI2_CS_B (MTK_PIN_NO(245) | 1) -#define MT6797_GPIO245__FUNC_TP_URXD2_AO (MTK_PIN_NO(245) | 2) -#define MT6797_GPIO245__FUNC_SDA5_2 (MTK_PIN_NO(245) | 3) -#define MT6797_GPIO245__FUNC_UCTS1 (MTK_PIN_NO(245) | 4) -#define MT6797_GPIO245__FUNC_URXD3 (MTK_PIN_NO(245) | 5) -#define MT6797_GPIO245__FUNC_CLKM3 (MTK_PIN_NO(245) | 6) -#define MT6797_GPIO245__FUNC_DBG_MON_A30 (MTK_PIN_NO(245) | 7) - -#define MT6797_GPIO246__FUNC_GPIO246 (MTK_PIN_NO(246) | 0) -#define MT6797_GPIO246__FUNC_I2S1_LRCK (MTK_PIN_NO(246) | 1) -#define MT6797_GPIO246__FUNC_I2S2_LRCK (MTK_PIN_NO(246) | 2) -#define MT6797_GPIO246__FUNC_I2S0_LRCK (MTK_PIN_NO(246) | 3) -#define MT6797_GPIO246__FUNC_I2S3_LRCK (MTK_PIN_NO(246) | 4) -#define MT6797_GPIO246__FUNC_PCM0_SYNC (MTK_PIN_NO(246) | 5) -#define MT6797_GPIO246__FUNC_SPI5_CLK_C (MTK_PIN_NO(246) | 6) -#define MT6797_GPIO246__FUNC_DBG_MON_A31 (MTK_PIN_NO(246) | 7) - -#define MT6797_GPIO247__FUNC_GPIO247 (MTK_PIN_NO(247) | 0) -#define MT6797_GPIO247__FUNC_I2S1_BCK (MTK_PIN_NO(247) | 1) -#define MT6797_GPIO247__FUNC_I2S2_BCK (MTK_PIN_NO(247) | 2) -#define MT6797_GPIO247__FUNC_I2S0_BCK (MTK_PIN_NO(247) | 3) -#define MT6797_GPIO247__FUNC_I2S3_BCK (MTK_PIN_NO(247) | 4) -#define MT6797_GPIO247__FUNC_PCM0_CLK (MTK_PIN_NO(247) | 5) -#define MT6797_GPIO247__FUNC_SPI5_MI_C (MTK_PIN_NO(247) | 6) -#define MT6797_GPIO247__FUNC_DBG_MON_A32 (MTK_PIN_NO(247) | 7) - -#define MT6797_GPIO248__FUNC_GPIO248 (MTK_PIN_NO(248) | 0) -/* #define MT6797_GPIO248__FUNC_I2S2_DI (MTK_PIN_NO(248) | 1) */ -#define MT6797_GPIO248__FUNC_I2S2_DI (MTK_PIN_NO(248) | 2) -/* #define MT6797_GPIO248__FUNC_I2S0_DI (MTK_PIN_NO(248) | 3) */ -#define MT6797_GPIO248__FUNC_I2S0_DI (MTK_PIN_NO(248) | 4) -#define MT6797_GPIO248__FUNC_PCM0_DI (MTK_PIN_NO(248) | 5) -#define MT6797_GPIO248__FUNC_SPI5_CS_C (MTK_PIN_NO(248) | 6) - -#define MT6797_GPIO249__FUNC_GPIO249 (MTK_PIN_NO(249) | 0) -/* #define MT6797_GPIO249__FUNC_I2S1_DO (MTK_PIN_NO(249) | 1) */ -#define MT6797_GPIO249__FUNC_I2S1_DO (MTK_PIN_NO(249) | 2) -/* #define MT6797_GPIO249__FUNC_I2S3_DO (MTK_PIN_NO(249) | 3) */ -#define MT6797_GPIO249__FUNC_I2S3_DO (MTK_PIN_NO(249) | 4) -#define MT6797_GPIO249__FUNC_PCM0_DO (MTK_PIN_NO(249) | 5) -#define MT6797_GPIO249__FUNC_SPI5_MO_C (MTK_PIN_NO(249) | 6) -#define MT6797_GPIO249__FUNC_TRAP_SRAM_PWR_BYPASS (MTK_PIN_NO(249) | 7) - -#define MT6797_GPIO250__FUNC_GPIO250 (MTK_PIN_NO(250) | 0) -#define MT6797_GPIO250__FUNC_SPI3_MI (MTK_PIN_NO(250) | 1) -#define MT6797_GPIO250__FUNC_SPI3_MO (MTK_PIN_NO(250) | 2) -#define MT6797_GPIO250__FUNC_IRTX_OUT (MTK_PIN_NO(250) | 3) -#define MT6797_GPIO250__FUNC_TP_URXD1_AO (MTK_PIN_NO(250) | 6) -#define MT6797_GPIO250__FUNC_DROP_ZONE (MTK_PIN_NO(250) | 7) - -#define MT6797_GPIO251__FUNC_GPIO251 (MTK_PIN_NO(251) | 0) -#define MT6797_GPIO251__FUNC_SPI3_MO (MTK_PIN_NO(251) | 1) -#define MT6797_GPIO251__FUNC_SPI3_MI (MTK_PIN_NO(251) | 2) -#define MT6797_GPIO251__FUNC_CMFLASH (MTK_PIN_NO(251) | 3) -#define MT6797_GPIO251__FUNC_TP_UTXD1_AO (MTK_PIN_NO(251) | 6) -#define MT6797_GPIO251__FUNC_C2K_RTCK (MTK_PIN_NO(251) | 7) - -#define MT6797_GPIO252__FUNC_GPIO252 (MTK_PIN_NO(252) | 0) -#define MT6797_GPIO252__FUNC_SPI3_CLK (MTK_PIN_NO(252) | 1) -#define MT6797_GPIO252__FUNC_SCL0_4 (MTK_PIN_NO(252) | 2) -#define MT6797_GPIO252__FUNC_PWM_D (MTK_PIN_NO(252) | 3) -#define MT6797_GPIO252__FUNC_C2K_TMS (MTK_PIN_NO(252) | 7) - -#define MT6797_GPIO253__FUNC_GPIO253 (MTK_PIN_NO(253) | 0) -#define MT6797_GPIO253__FUNC_SPI3_CS (MTK_PIN_NO(253) | 1) -#define MT6797_GPIO253__FUNC_SDA0_4 (MTK_PIN_NO(253) | 2) -#define MT6797_GPIO253__FUNC_PWM_A (MTK_PIN_NO(253) | 3) -#define MT6797_GPIO253__FUNC_C2K_TCK (MTK_PIN_NO(253) | 7) - -#define MT6797_GPIO254__FUNC_GPIO254 (MTK_PIN_NO(254) | 0) -#define MT6797_GPIO254__FUNC_I2S1_MCK (MTK_PIN_NO(254) | 1) -#define MT6797_GPIO254__FUNC_I2S2_MCK (MTK_PIN_NO(254) | 2) -#define MT6797_GPIO254__FUNC_I2S0_MCK (MTK_PIN_NO(254) | 3) -#define MT6797_GPIO254__FUNC_I2S3_MCK (MTK_PIN_NO(254) | 4) -#define MT6797_GPIO254__FUNC_CLKM0 (MTK_PIN_NO(254) | 5) -#define MT6797_GPIO254__FUNC_C2K_TDI (MTK_PIN_NO(254) | 7) - -#define MT6797_GPIO255__FUNC_GPIO255 (MTK_PIN_NO(255) | 0) -#define MT6797_GPIO255__FUNC_CLKM1 (MTK_PIN_NO(255) | 1) -#define MT6797_GPIO255__FUNC_DISP_PWM (MTK_PIN_NO(255) | 2) -#define MT6797_GPIO255__FUNC_PWM_B (MTK_PIN_NO(255) | 3) -#define MT6797_GPIO255__FUNC_TP_GPIO1_AO (MTK_PIN_NO(255) | 6) -#define MT6797_GPIO255__FUNC_C2K_TDO (MTK_PIN_NO(255) | 7) - -#define MT6797_GPIO256__FUNC_GPIO256 (MTK_PIN_NO(256) | 0) -#define MT6797_GPIO256__FUNC_CLKM2 (MTK_PIN_NO(256) | 1) -#define MT6797_GPIO256__FUNC_IRTX_OUT (MTK_PIN_NO(256) | 2) -#define MT6797_GPIO256__FUNC_PWM_C (MTK_PIN_NO(256) | 3) -#define MT6797_GPIO256__FUNC_TP_GPIO0_AO (MTK_PIN_NO(256) | 6) -#define MT6797_GPIO256__FUNC_C2K_NTRST (MTK_PIN_NO(256) | 7) - -#define MT6797_GPIO257__FUNC_GPIO257 (MTK_PIN_NO(257) | 0) -#define MT6797_GPIO257__FUNC_IO_JTAG_TMS (MTK_PIN_NO(257) | 1) -#define MT6797_GPIO257__FUNC_LTE_JTAG_TMS (MTK_PIN_NO(257) | 2) -#define MT6797_GPIO257__FUNC_DFD_TMS (MTK_PIN_NO(257) | 3) -#define MT6797_GPIO257__FUNC_DAP_SIB1_SWD (MTK_PIN_NO(257) | 4) -#define MT6797_GPIO257__FUNC_ANC_JTAG_TMS (MTK_PIN_NO(257) | 5) -#define MT6797_GPIO257__FUNC_SCP_JTAG_TMS (MTK_PIN_NO(257) | 6) -#define MT6797_GPIO257__FUNC_C2K_DM_OTMS (MTK_PIN_NO(257) | 7) - -#define MT6797_GPIO258__FUNC_GPIO258 (MTK_PIN_NO(258) | 0) -#define MT6797_GPIO258__FUNC_IO_JTAG_TCK (MTK_PIN_NO(258) | 1) -#define MT6797_GPIO258__FUNC_LTE_JTAG_TCK (MTK_PIN_NO(258) | 2) -#define MT6797_GPIO258__FUNC_DFD_TCK_XI (MTK_PIN_NO(258) | 3) -#define MT6797_GPIO258__FUNC_DAP_SIB1_SWCK (MTK_PIN_NO(258) | 4) -#define MT6797_GPIO258__FUNC_ANC_JTAG_TCK (MTK_PIN_NO(258) | 5) -#define MT6797_GPIO258__FUNC_SCP_JTAG_TCK (MTK_PIN_NO(258) | 6) -#define MT6797_GPIO258__FUNC_C2K_DM_OTCK (MTK_PIN_NO(258) | 7) - -#define MT6797_GPIO259__FUNC_GPIO259 (MTK_PIN_NO(259) | 0) -#define MT6797_GPIO259__FUNC_IO_JTAG_TDI (MTK_PIN_NO(259) | 1) -#define MT6797_GPIO259__FUNC_LTE_JTAG_TDI (MTK_PIN_NO(259) | 2) -#define MT6797_GPIO259__FUNC_DFD_TDI (MTK_PIN_NO(259) | 3) -#define MT6797_GPIO259__FUNC_ANC_JTAG_TDI (MTK_PIN_NO(259) | 5) -#define MT6797_GPIO259__FUNC_SCP_JTAG_TDI (MTK_PIN_NO(259) | 6) -#define MT6797_GPIO259__FUNC_C2K_DM_OTDI (MTK_PIN_NO(259) | 7) - -#define MT6797_GPIO260__FUNC_GPIO260 (MTK_PIN_NO(260) | 0) -#define MT6797_GPIO260__FUNC_IO_JTAG_TDO (MTK_PIN_NO(260) | 1) -#define MT6797_GPIO260__FUNC_LTE_JTAG_TDO (MTK_PIN_NO(260) | 2) -#define MT6797_GPIO260__FUNC_DFD_TDO (MTK_PIN_NO(260) | 3) -#define MT6797_GPIO260__FUNC_ANC_JTAG_TDO (MTK_PIN_NO(260) | 5) -#define MT6797_GPIO260__FUNC_SCP_JTAG_TDO (MTK_PIN_NO(260) | 6) -#define MT6797_GPIO260__FUNC_C2K_DM_OTDO (MTK_PIN_NO(260) | 7) - -#define MT6797_GPIO261__FUNC_GPIO261 (MTK_PIN_NO(261) | 0) -#define MT6797_GPIO261__FUNC_LTE_JTAG_TRSTN (MTK_PIN_NO(261) | 2) -#define MT6797_GPIO261__FUNC_DFD_NTRST (MTK_PIN_NO(261) | 3) -#define MT6797_GPIO261__FUNC_ANC_JTAG_TRSTN (MTK_PIN_NO(261) | 5) -#define MT6797_GPIO261__FUNC_SCP_JTAG_TRSTN (MTK_PIN_NO(261) | 6) -#define MT6797_GPIO261__FUNC_C2K_DM_JTINTP (MTK_PIN_NO(261) | 7) - -#endif /* __DTS_MT6797_PINFUNC_H */ diff --git a/sys/gnu/dts/include/dt-bindings/pinctrl/mt7623-pinfunc.h b/sys/gnu/dts/include/dt-bindings/pinctrl/mt7623-pinfunc.h deleted file mode 100644 index 604fe781c46..00000000000 --- a/sys/gnu/dts/include/dt-bindings/pinctrl/mt7623-pinfunc.h +++ /dev/null @@ -1,651 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __DTS_MT7623_PINFUNC_H -#define __DTS_MT7623_PINFUNC_H - -#include - -#define MT7623_PIN_0_PWRAP_SPI0_MI_FUNC_GPIO0 (MTK_PIN_NO(0) | 0) -#define MT7623_PIN_0_PWRAP_SPI0_MI_FUNC_PWRAP_SPIDO (MTK_PIN_NO(0) | 1) -#define MT7623_PIN_0_PWRAP_SPI0_MI_FUNC_PWRAP_SPIDI (MTK_PIN_NO(0) | 2) - -#define MT7623_PIN_1_PWRAP_SPI0_MO_FUNC_GPIO1 (MTK_PIN_NO(1) | 0) -#define MT7623_PIN_1_PWRAP_SPI0_MO_FUNC_PWRAP_SPIDI (MTK_PIN_NO(1) | 1) -#define MT7623_PIN_1_PWRAP_SPI0_MO_FUNC_PWRAP_SPIDO (MTK_PIN_NO(1) | 2) - -#define MT7623_PIN_2_PWRAP_INT_FUNC_GPIO2 (MTK_PIN_NO(2) | 0) -#define MT7623_PIN_2_PWRAP_INT_FUNC_PWRAP_INT (MTK_PIN_NO(2) | 1) - -#define MT7623_PIN_3_PWRAP_SPI0_CK_FUNC_GPIO3 (MTK_PIN_NO(3) | 0) -#define MT7623_PIN_3_PWRAP_SPI0_CK_FUNC_PWRAP_SPICK_I (MTK_PIN_NO(3) | 1) - -#define MT7623_PIN_4_PWRAP_SPI0_CSN_FUNC_GPIO4 (MTK_PIN_NO(4) | 0) -#define MT7623_PIN_4_PWRAP_SPI0_CSN_FUNC_PWRAP_SPICS_B_I (MTK_PIN_NO(4) | 1) - -#define MT7623_PIN_5_PWRAP_SPI0_CK2_FUNC_GPIO5 (MTK_PIN_NO(5) | 0) -#define MT7623_PIN_5_PWRAP_SPI0_CK2_FUNC_PWRAP_SPICK2_I (MTK_PIN_NO(5) | 1) -#define MT7623_PIN_5_PWRAP_SPI0_CK2_FUNC_ANT_SEL1 (MTK_PIN_NO(5) | 5) - -#define MT7623_PIN_6_PWRAP_SPI0_CSN2_FUNC_GPIO6 (MTK_PIN_NO(6) | 0) -#define MT7623_PIN_6_PWRAP_SPI0_CSN2_FUNC_PWRAP_SPICS2_B_I (MTK_PIN_NO(6) | 1) -#define MT7623_PIN_6_PWRAP_SPI0_CSN2_FUNC_ANT_SEL0 (MTK_PIN_NO(6) | 5) - -#define MT7623_PIN_7_SPI1_CSN_FUNC_GPIO7 (MTK_PIN_NO(7) | 0) -#define MT7623_PIN_7_SPI1_CSN_FUNC_SPI1_CS (MTK_PIN_NO(7) | 1) -#define MT7623_PIN_7_SPI1_CSN_FUNC_KCOL0 (MTK_PIN_NO(7) | 4) - -#define MT7623_PIN_8_SPI1_MI_FUNC_GPIO8 (MTK_PIN_NO(8) | 0) -#define MT7623_PIN_8_SPI1_MI_FUNC_SPI1_MI (MTK_PIN_NO(8) | 1) -#define MT7623_PIN_8_SPI1_MI_FUNC_SPI1_MO (MTK_PIN_NO(8) | 2) -#define MT7623_PIN_8_SPI1_MI_FUNC_KCOL1 (MTK_PIN_NO(8) | 4) - -#define MT7623_PIN_9_SPI1_MO_FUNC_GPIO9 (MTK_PIN_NO(9) | 0) -#define MT7623_PIN_9_SPI1_MO_FUNC_SPI1_MO (MTK_PIN_NO(9) | 1) -#define MT7623_PIN_9_SPI1_MO_FUNC_SPI1_MI (MTK_PIN_NO(9) | 2) -#define MT7623_PIN_9_SPI1_MO_FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(9) | 3) -#define MT7623_PIN_9_SPI1_MO_FUNC_KCOL2 (MTK_PIN_NO(9) | 4) - -#define MT7623_PIN_10_RTC32K_CK_FUNC_GPIO10 (MTK_PIN_NO(10) | 0) -#define MT7623_PIN_10_RTC32K_CK_FUNC_RTC32K_CK (MTK_PIN_NO(10) | 1) - -#define MT7623_PIN_11_WATCHDOG_FUNC_GPIO11 (MTK_PIN_NO(11) | 0) -#define MT7623_PIN_11_WATCHDOG_FUNC_WATCHDOG (MTK_PIN_NO(11) | 1) - -#define MT7623_PIN_12_SRCLKENA_FUNC_GPIO12 (MTK_PIN_NO(12) | 0) -#define MT7623_PIN_12_SRCLKENA_FUNC_SRCLKENA (MTK_PIN_NO(12) | 1) - -#define MT7623_PIN_13_SRCLKENAI_FUNC_GPIO13 (MTK_PIN_NO(13) | 0) -#define MT7623_PIN_13_SRCLKENAI_FUNC_SRCLKENAI (MTK_PIN_NO(13) | 1) - -#define MT7623_PIN_14_GPIO14_FUNC_GPIO14 (MTK_PIN_NO(14) | 0) -#define MT7623_PIN_14_GPIO14_FUNC_URXD2 (MTK_PIN_NO(14) | 1) -#define MT7623_PIN_14_GPIO14_FUNC_UTXD2 (MTK_PIN_NO(14) | 2) -#define MT7623_PIN_14_GPIO14_FUNC_SRCCLKENAI2 (MTK_PIN_NO(14) | 5) - -#define MT7623_PIN_15_GPIO15_FUNC_GPIO15 (MTK_PIN_NO(15) | 0) -#define MT7623_PIN_15_GPIO15_FUNC_UTXD2 (MTK_PIN_NO(15) | 1) -#define MT7623_PIN_15_GPIO15_FUNC_URXD2 (MTK_PIN_NO(15) | 2) - -#define MT7623_PIN_18_PCM_CLK_FUNC_GPIO18 (MTK_PIN_NO(18) | 0) -#define MT7623_PIN_18_PCM_CLK_FUNC_PCM_CLK0 (MTK_PIN_NO(18) | 1) -#define MT7623_PIN_18_PCM_CLK_FUNC_MRG_CLK (MTK_PIN_NO(18) | 2) -#define MT7623_PIN_18_PCM_CLK_FUNC_MM_TEST_CK (MTK_PIN_NO(18) | 4) -#define MT7623_PIN_18_PCM_CLK_FUNC_CONN_DSP_JCK (MTK_PIN_NO(18) | 5) -#define MT7623_PIN_18_PCM_CLK_FUNC_AP_PCM_CLKO (MTK_PIN_NO(18) | 6) - -#define MT7623_PIN_19_PCM_SYNC_FUNC_GPIO19 (MTK_PIN_NO(19) | 0) -#define MT7623_PIN_19_PCM_SYNC_FUNC_PCM_SYNC (MTK_PIN_NO(19) | 1) -#define MT7623_PIN_19_PCM_SYNC_FUNC_MRG_SYNC (MTK_PIN_NO(19) | 2) -#define MT7623_PIN_19_PCM_SYNC_FUNC_CONN_DSP_JINTP (MTK_PIN_NO(19) | 5) -#define MT7623_PIN_19_PCM_SYNC_FUNC_AP_PCM_SYNC (MTK_PIN_NO(19) | 6) - -#define MT7623_PIN_20_PCM_RX_FUNC_GPIO20 (MTK_PIN_NO(20) | 0) -#define MT7623_PIN_20_PCM_RX_FUNC_PCM_RX (MTK_PIN_NO(20) | 1) -#define MT7623_PIN_20_PCM_RX_FUNC_MRG_RX (MTK_PIN_NO(20) | 2) -#define MT7623_PIN_20_PCM_RX_FUNC_MRG_TX (MTK_PIN_NO(20) | 3) -#define MT7623_PIN_20_PCM_RX_FUNC_PCM_TX (MTK_PIN_NO(20) | 4) -#define MT7623_PIN_20_PCM_RX_FUNC_CONN_DSP_JDI (MTK_PIN_NO(20) | 5) -#define MT7623_PIN_20_PCM_RX_FUNC_AP_PCM_RX (MTK_PIN_NO(20) | 6) - -#define MT7623_PIN_21_PCM_TX_FUNC_GPIO21 (MTK_PIN_NO(21) | 0) -#define MT7623_PIN_21_PCM_TX_FUNC_PCM_TX (MTK_PIN_NO(21) | 1) -#define MT7623_PIN_21_PCM_TX_FUNC_MRG_TX (MTK_PIN_NO(21) | 2) -#define MT7623_PIN_21_PCM_TX_FUNC_MRG_RX (MTK_PIN_NO(21) | 3) -#define MT7623_PIN_21_PCM_TX_FUNC_PCM_RX (MTK_PIN_NO(21) | 4) -#define MT7623_PIN_21_PCM_TX_FUNC_CONN_DSP_JMS (MTK_PIN_NO(21) | 5) -#define MT7623_PIN_21_PCM_TX_FUNC_AP_PCM_TX (MTK_PIN_NO(21) | 6) - -#define MT7623_PIN_22_EINT0_FUNC_GPIO22 (MTK_PIN_NO(22) | 0) -#define MT7623_PIN_22_EINT0_FUNC_UCTS0 (MTK_PIN_NO(22) | 1) -#define MT7623_PIN_22_EINT0_FUNC_PCIE0_PERST_N (MTK_PIN_NO(22) | 2) -#define MT7623_PIN_22_EINT0_FUNC_KCOL3 (MTK_PIN_NO(22) | 3) -#define MT7623_PIN_22_EINT0_FUNC_CONN_DSP_JDO (MTK_PIN_NO(22) | 4) -#define MT7623_PIN_22_EINT0_FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(22) | 5) - -#define MT7623_PIN_23_EINT1_FUNC_GPIO23 (MTK_PIN_NO(23) | 0) -#define MT7623_PIN_23_EINT1_FUNC_URTS0 (MTK_PIN_NO(23) | 1) -#define MT7623_PIN_23_EINT1_FUNC_PCIE1_PERST_N (MTK_PIN_NO(23) | 2) -#define MT7623_PIN_23_EINT1_FUNC_KCOL2 (MTK_PIN_NO(23) | 3) -#define MT7623_PIN_23_EINT1_FUNC_CONN_MCU_TDO (MTK_PIN_NO(23) | 4) -#define MT7623_PIN_23_EINT1_FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(23) | 5) - -#define MT7623_PIN_24_EINT2_FUNC_GPIO24 (MTK_PIN_NO(24) | 0) -#define MT7623_PIN_24_EINT2_FUNC_UCTS1 (MTK_PIN_NO(24) | 1) -#define MT7623_PIN_24_EINT2_FUNC_PCIE2_PERST_N (MTK_PIN_NO(24) | 2) -#define MT7623_PIN_24_EINT2_FUNC_KCOL1 (MTK_PIN_NO(24) | 3) -#define MT7623_PIN_24_EINT2_FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(24) | 4) - -#define MT7623_PIN_25_EINT3_FUNC_GPIO25 (MTK_PIN_NO(25) | 0) -#define MT7623_PIN_25_EINT3_FUNC_URTS1 (MTK_PIN_NO(25) | 1) -#define MT7623_PIN_25_EINT3_FUNC_KCOL0 (MTK_PIN_NO(25) | 3) -#define MT7623_PIN_25_EINT3_FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(25) | 4) - -#define MT7623_PIN_26_EINT4_FUNC_GPIO26 (MTK_PIN_NO(26) | 0) -#define MT7623_PIN_26_EINT4_FUNC_UCTS3 (MTK_PIN_NO(26) | 1) -#define MT7623_PIN_26_EINT4_FUNC_DRV_VBUS_P1 (MTK_PIN_NO(26) | 2) -#define MT7623_PIN_26_EINT4_FUNC_KROW3 (MTK_PIN_NO(26) | 3) -#define MT7623_PIN_26_EINT4_FUNC_CONN_MCU_TCK0 (MTK_PIN_NO(26) | 4) -#define MT7623_PIN_26_EINT4_FUNC_CONN_MCU_AICE_JCKC (MTK_PIN_NO(26) | 5) -#define MT7623_PIN_26_EINT4_FUNC_PCIE2_WAKE_N (MTK_PIN_NO(26) | 6) - -#define MT7623_PIN_27_EINT5_FUNC_GPIO27 (MTK_PIN_NO(27) | 0) -#define MT7623_PIN_27_EINT5_FUNC_URTS3 (MTK_PIN_NO(27) | 1) -#define MT7623_PIN_27_EINT5_FUNC_IDDIG_P1 (MTK_PIN_NO(27) | 2) -#define MT7623_PIN_27_EINT5_FUNC_KROW2 (MTK_PIN_NO(27) | 3) -#define MT7623_PIN_27_EINT5_FUNC_CONN_MCU_TDI (MTK_PIN_NO(27) | 4) -#define MT7623_PIN_27_EINT5_FUNC_PCIE1_WAKE_N (MTK_PIN_NO(27) | 6) - -#define MT7623_PIN_28_EINT6_FUNC_GPIO28 (MTK_PIN_NO(28) | 0) -#define MT7623_PIN_28_EINT6_FUNC_DRV_VBUS (MTK_PIN_NO(28) | 1) -#define MT7623_PIN_28_EINT6_FUNC_KROW1 (MTK_PIN_NO(28) | 3) -#define MT7623_PIN_28_EINT6_FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(28) | 4) -#define MT7623_PIN_28_EINT6_FUNC_PCIE0_WAKE_N (MTK_PIN_NO(28) | 6) - -#define MT7623_PIN_29_EINT7_FUNC_GPIO29 (MTK_PIN_NO(29) | 0) -#define MT7623_PIN_29_EINT7_FUNC_IDDIG (MTK_PIN_NO(29) | 1) -#define MT7623_PIN_29_EINT7_FUNC_MSDC1_WP (MTK_PIN_NO(29) | 2) -#define MT7623_PIN_29_EINT7_FUNC_KROW0 (MTK_PIN_NO(29) | 3) -#define MT7623_PIN_29_EINT7_FUNC_CONN_MCU_TMS (MTK_PIN_NO(29) | 4) -#define MT7623_PIN_29_EINT7_FUNC_CONN_MCU_AICE_JMSC (MTK_PIN_NO(29) | 5) -#define MT7623_PIN_29_EINT7_FUNC_PCIE2_PERST_N (MTK_PIN_NO(29) | 6) - -#define MT7623_PIN_33_I2S1_DATA_FUNC_GPIO33 (MTK_PIN_NO(33) | 0) -#define MT7623_PIN_33_I2S1_DATA_FUNC_I2S1_DATA (MTK_PIN_NO(33) | 1) -#define MT7623_PIN_33_I2S1_DATA_FUNC_I2S1_DATA_BYPS (MTK_PIN_NO(33) | 2) -#define MT7623_PIN_33_I2S1_DATA_FUNC_PCM_TX (MTK_PIN_NO(33) | 3) -#define MT7623_PIN_33_I2S1_DATA_FUNC_IMG_TEST_CK (MTK_PIN_NO(33) | 4) -#define MT7623_PIN_33_I2S1_DATA_FUNC_G1_RXD0 (MTK_PIN_NO(33) | 5) -#define MT7623_PIN_33_I2S1_DATA_FUNC_AP_PCM_TX (MTK_PIN_NO(33) | 6) - -#define MT7623_PIN_34_I2S1_DATA_IN_FUNC_GPIO34 (MTK_PIN_NO(34) | 0) -#define MT7623_PIN_34_I2S1_DATA_IN_FUNC_I2S1_DATA_IN (MTK_PIN_NO(34) | 1) -#define MT7623_PIN_34_I2S1_DATA_IN_FUNC_PCM_RX (MTK_PIN_NO(34) | 3) -#define MT7623_PIN_34_I2S1_DATA_IN_FUNC_VDEC_TEST_CK (MTK_PIN_NO(34) | 4) -#define MT7623_PIN_34_I2S1_DATA_IN_FUNC_G1_RXD1 (MTK_PIN_NO(34) | 5) -#define MT7623_PIN_34_I2S1_DATA_IN_FUNC_AP_PCM_RX (MTK_PIN_NO(34) | 6) - -#define MT7623_PIN_35_I2S1_BCK_FUNC_GPIO35 (MTK_PIN_NO(35) | 0) -#define MT7623_PIN_35_I2S1_BCK_FUNC_I2S1_BCK (MTK_PIN_NO(35) | 1) -#define MT7623_PIN_35_I2S1_BCK_FUNC_PCM_CLK0 (MTK_PIN_NO(35) | 3) -#define MT7623_PIN_35_I2S1_BCK_FUNC_G1_RXD2 (MTK_PIN_NO(35) | 5) -#define MT7623_PIN_35_I2S1_BCK_FUNC_AP_PCM_CLKO (MTK_PIN_NO(35) | 6) - -#define MT7623_PIN_36_I2S1_LRCK_FUNC_GPIO36 (MTK_PIN_NO(36) | 0) -#define MT7623_PIN_36_I2S1_LRCK_FUNC_I2S1_LRCK (MTK_PIN_NO(36) | 1) -#define MT7623_PIN_36_I2S1_LRCK_FUNC_PCM_SYNC (MTK_PIN_NO(36) | 3) -#define MT7623_PIN_36_I2S1_LRCK_FUNC_G1_RXD3 (MTK_PIN_NO(36) | 5) -#define MT7623_PIN_36_I2S1_LRCK_FUNC_AP_PCM_SYNC (MTK_PIN_NO(36) | 6) - -#define MT7623_PIN_37_I2S1_MCLK_FUNC_GPIO37 (MTK_PIN_NO(37) | 0) -#define MT7623_PIN_37_I2S1_MCLK_FUNC_I2S1_MCLK (MTK_PIN_NO(37) | 1) -#define MT7623_PIN_37_I2S1_MCLK_FUNC_G1_RXDV (MTK_PIN_NO(37) | 5) - -#define MT7623_PIN_39_JTMS_FUNC_GPIO39 (MTK_PIN_NO(39) | 0) -#define MT7623_PIN_39_JTMS_FUNC_JTMS (MTK_PIN_NO(39) | 1) -#define MT7623_PIN_39_JTMS_FUNC_CONN_MCU_TMS (MTK_PIN_NO(39) | 2) -#define MT7623_PIN_39_JTMS_FUNC_CONN_MCU_AICE_JMSC (MTK_PIN_NO(39) | 3) -#define MT7623_PIN_39_JTMS_FUNC_DFD_TMS_XI (MTK_PIN_NO(39) | 4) - -#define MT7623_PIN_40_JTCK_FUNC_GPIO40 (MTK_PIN_NO(40) | 0) -#define MT7623_PIN_40_JTCK_FUNC_JTCK (MTK_PIN_NO(40) | 1) -#define MT7623_PIN_40_JTCK_FUNC_CONN_MCU_TCK1 (MTK_PIN_NO(40) | 2) -#define MT7623_PIN_40_JTCK_FUNC_CONN_MCU_AICE_JCKC (MTK_PIN_NO(40) | 3) -#define MT7623_PIN_40_JTCK_FUNC_DFD_TCK_XI (MTK_PIN_NO(40) | 4) - -#define MT7623_PIN_41_JTDI_FUNC_GPIO41 (MTK_PIN_NO(41) | 0) -#define MT7623_PIN_41_JTDI_FUNC_JTDI (MTK_PIN_NO(41) | 1) -#define MT7623_PIN_41_JTDI_FUNC_CONN_MCU_TDI (MTK_PIN_NO(41) | 2) -#define MT7623_PIN_41_JTDI_FUNC_DFD_TDI_XI (MTK_PIN_NO(41) | 4) - -#define MT7623_PIN_42_JTDO_FUNC_GPIO42 (MTK_PIN_NO(42) | 0) -#define MT7623_PIN_42_JTDO_FUNC_JTDO (MTK_PIN_NO(42) | 1) -#define MT7623_PIN_42_JTDO_FUNC_CONN_MCU_TDO (MTK_PIN_NO(42) | 2) -#define MT7623_PIN_42_JTDO_FUNC_DFD_TDO (MTK_PIN_NO(42) | 4) - -#define MT7623_PIN_43_NCLE_FUNC_GPIO43 (MTK_PIN_NO(43) | 0) -#define MT7623_PIN_43_NCLE_FUNC_NCLE (MTK_PIN_NO(43) | 1) -#define MT7623_PIN_43_NCLE_FUNC_EXT_XCS2 (MTK_PIN_NO(43) | 2) - -#define MT7623_PIN_44_NCEB1_FUNC_GPIO44 (MTK_PIN_NO(44) | 0) -#define MT7623_PIN_44_NCEB1_FUNC_NCEB1 (MTK_PIN_NO(44) | 1) -#define MT7623_PIN_44_NCEB1_FUNC_IDDIG (MTK_PIN_NO(44) | 2) - -#define MT7623_PIN_45_NCEB0_FUNC_GPIO45 (MTK_PIN_NO(45) | 0) -#define MT7623_PIN_45_NCEB0_FUNC_NCEB0 (MTK_PIN_NO(45) | 1) -#define MT7623_PIN_45_NCEB0_FUNC_DRV_VBUS (MTK_PIN_NO(45) | 2) - -#define MT7623_PIN_46_IR_FUNC_GPIO46 (MTK_PIN_NO(46) | 0) -#define MT7623_PIN_46_IR_FUNC_IR (MTK_PIN_NO(46) | 1) - -#define MT7623_PIN_47_NREB_FUNC_GPIO47 (MTK_PIN_NO(47) | 0) -#define MT7623_PIN_47_NREB_FUNC_NREB (MTK_PIN_NO(47) | 1) -#define MT7623_PIN_47_NREB_FUNC_IDDIG_P1 (MTK_PIN_NO(47) | 2) - -#define MT7623_PIN_48_NRNB_FUNC_GPIO48 (MTK_PIN_NO(48) | 0) -#define MT7623_PIN_48_NRNB_FUNC_NRNB (MTK_PIN_NO(48) | 1) -#define MT7623_PIN_48_NRNB_FUNC_DRV_VBUS_P1 (MTK_PIN_NO(48) | 2) - -#define MT7623_PIN_49_I2S0_DATA_FUNC_GPIO49 (MTK_PIN_NO(49) | 0) -#define MT7623_PIN_49_I2S0_DATA_FUNC_I2S0_DATA (MTK_PIN_NO(49) | 1) -#define MT7623_PIN_49_I2S0_DATA_FUNC_I2S0_DATA_BYPS (MTK_PIN_NO(49) | 2) -#define MT7623_PIN_49_I2S0_DATA_FUNC_PCM_TX (MTK_PIN_NO(49) | 3) -#define MT7623_PIN_49_I2S0_DATA_FUNC_AP_I2S_DO (MTK_PIN_NO(49) | 6) - -#define MT7623_PIN_53_SPI0_CSN_FUNC_GPIO53 (MTK_PIN_NO(53) | 0) -#define MT7623_PIN_53_SPI0_CSN_FUNC_SPI0_CS (MTK_PIN_NO(53) | 1) -#define MT7623_PIN_53_SPI0_CSN_FUNC_SPDIF (MTK_PIN_NO(53) | 3) -#define MT7623_PIN_53_SPI0_CSN_FUNC_ADC_CK (MTK_PIN_NO(53) | 4) -#define MT7623_PIN_53_SPI0_CSN_FUNC_PWM1 (MTK_PIN_NO(53) | 5) - -#define MT7623_PIN_54_SPI0_CK_FUNC_GPIO54 (MTK_PIN_NO(54) | 0) -#define MT7623_PIN_54_SPI0_CK_FUNC_SPI0_CK (MTK_PIN_NO(54) | 1) -#define MT7623_PIN_54_SPI0_CK_FUNC_SPDIF_IN1 (MTK_PIN_NO(54) | 3) -#define MT7623_PIN_54_SPI0_CK_FUNC_ADC_DAT_IN (MTK_PIN_NO(54) | 4) - -#define MT7623_PIN_55_SPI0_MI_FUNC_GPIO55 (MTK_PIN_NO(55) | 0) -#define MT7623_PIN_55_SPI0_MI_FUNC_SPI0_MI (MTK_PIN_NO(55) | 1) -#define MT7623_PIN_55_SPI0_MI_FUNC_SPI0_MO (MTK_PIN_NO(55) | 2) -#define MT7623_PIN_55_SPI0_MI_FUNC_MSDC1_WP (MTK_PIN_NO(55) | 3) -#define MT7623_PIN_55_SPI0_MI_FUNC_ADC_WS (MTK_PIN_NO(55) | 4) -#define MT7623_PIN_55_SPI0_MI_FUNC_PWM2 (MTK_PIN_NO(55) | 5) - -#define MT7623_PIN_56_SPI0_MO_FUNC_GPIO56 (MTK_PIN_NO(56) | 0) -#define MT7623_PIN_56_SPI0_MO_FUNC_SPI0_MO (MTK_PIN_NO(56) | 1) -#define MT7623_PIN_56_SPI0_MO_FUNC_SPI0_MI (MTK_PIN_NO(56) | 2) -#define MT7623_PIN_56_SPI0_MO_FUNC_SPDIF_IN0 (MTK_PIN_NO(56) | 3) - -#define MT7623_PIN_57_SDA1_FUNC_GPIO57 (MTK_PIN_NO(57) | 0) -#define MT7623_PIN_57_SDA1_FUNC_SDA1 (MTK_PIN_NO(57) | 1) - -#define MT7623_PIN_58_SCL1_FUNC_GPIO58 (MTK_PIN_NO(58) | 0) -#define MT7623_PIN_58_SCL1_FUNC_SCL1 (MTK_PIN_NO(58) | 1) - -#define MT7623_PIN_60_WB_RSTB_FUNC_GPIO60 (MTK_PIN_NO(60) | 0) -#define MT7623_PIN_60_WB_RSTB_FUNC_WB_RSTB (MTK_PIN_NO(60) | 1) - -#define MT7623_PIN_61_GPIO61_FUNC_GPIO61 (MTK_PIN_NO(61) | 0) -#define MT7623_PIN_61_GPIO61_FUNC_TEST_FD (MTK_PIN_NO(61) | 1) - -#define MT7623_PIN_62_GPIO62_FUNC_GPIO62 (MTK_PIN_NO(62) | 0) -#define MT7623_PIN_62_GPIO62_FUNC_TEST_FC (MTK_PIN_NO(62) | 1) - -#define MT7623_PIN_63_WB_SCLK_FUNC_GPIO63 (MTK_PIN_NO(63) | 0) -#define MT7623_PIN_63_WB_SCLK_FUNC_WB_SCLK (MTK_PIN_NO(63) | 1) - -#define MT7623_PIN_64_WB_SDATA_FUNC_GPIO64 (MTK_PIN_NO(64) | 0) -#define MT7623_PIN_64_WB_SDATA_FUNC_WB_SDATA (MTK_PIN_NO(64) | 1) - -#define MT7623_PIN_65_WB_SEN_FUNC_GPIO65 (MTK_PIN_NO(65) | 0) -#define MT7623_PIN_65_WB_SEN_FUNC_WB_SEN (MTK_PIN_NO(65) | 1) - -#define MT7623_PIN_66_WB_CRTL0_FUNC_GPIO66 (MTK_PIN_NO(66) | 0) -#define MT7623_PIN_66_WB_CRTL0_FUNC_WB_CRTL0 (MTK_PIN_NO(66) | 1) - -#define MT7623_PIN_67_WB_CRTL1_FUNC_GPIO67 (MTK_PIN_NO(67) | 0) -#define MT7623_PIN_67_WB_CRTL1_FUNC_WB_CRTL1 (MTK_PIN_NO(67) | 1) - -#define MT7623_PIN_68_WB_CRTL2_FUNC_GPIO68 (MTK_PIN_NO(68) | 0) -#define MT7623_PIN_68_WB_CRTL2_FUNC_WB_CRTL2 (MTK_PIN_NO(68) | 1) - -#define MT7623_PIN_69_WB_CRTL3_FUNC_GPIO69 (MTK_PIN_NO(69) | 0) -#define MT7623_PIN_69_WB_CRTL3_FUNC_WB_CRTL3 (MTK_PIN_NO(69) | 1) - -#define MT7623_PIN_70_WB_CRTL4_FUNC_GPIO70 (MTK_PIN_NO(70) | 0) -#define MT7623_PIN_70_WB_CRTL4_FUNC_WB_CRTL4 (MTK_PIN_NO(70) | 1) - -#define MT7623_PIN_71_WB_CRTL5_FUNC_GPIO71 (MTK_PIN_NO(71) | 0) -#define MT7623_PIN_71_WB_CRTL5_FUNC_WB_CRTL5 (MTK_PIN_NO(71) | 1) - -#define MT7623_PIN_72_I2S0_DATA_IN_FUNC_GPIO72 (MTK_PIN_NO(72) | 0) -#define MT7623_PIN_72_I2S0_DATA_IN_FUNC_I2S0_DATA_IN (MTK_PIN_NO(72) | 1) -#define MT7623_PIN_72_I2S0_DATA_IN_FUNC_PCM_RX (MTK_PIN_NO(72) | 3) -#define MT7623_PIN_72_I2S0_DATA_IN_FUNC_PWM0 (MTK_PIN_NO(72) | 4) -#define MT7623_PIN_72_I2S0_DATA_IN_FUNC_DISP_PWM (MTK_PIN_NO(72) | 5) -#define MT7623_PIN_72_I2S0_DATA_IN_FUNC_AP_I2S_DI (MTK_PIN_NO(72) | 6) - -#define MT7623_PIN_73_I2S0_LRCK_FUNC_GPIO73 (MTK_PIN_NO(73) | 0) -#define MT7623_PIN_73_I2S0_LRCK_FUNC_I2S0_LRCK (MTK_PIN_NO(73) | 1) -#define MT7623_PIN_73_I2S0_LRCK_FUNC_PCM_SYNC (MTK_PIN_NO(73) | 3) -#define MT7623_PIN_73_I2S0_LRCK_FUNC_AP_I2S_LRCK (MTK_PIN_NO(73) | 6) - -#define MT7623_PIN_74_I2S0_BCK_FUNC_GPIO74 (MTK_PIN_NO(74) | 0) -#define MT7623_PIN_74_I2S0_BCK_FUNC_I2S0_BCK (MTK_PIN_NO(74) | 1) -#define MT7623_PIN_74_I2S0_BCK_FUNC_PCM_CLK0 (MTK_PIN_NO(74) | 3) -#define MT7623_PIN_74_I2S0_BCK_FUNC_AP_I2S_BCK (MTK_PIN_NO(74) | 6) - -#define MT7623_PIN_75_SDA0_FUNC_GPIO75 (MTK_PIN_NO(75) | 0) -#define MT7623_PIN_75_SDA0_FUNC_SDA0 (MTK_PIN_NO(75) | 1) - -#define MT7623_PIN_76_SCL0_FUNC_GPIO76 (MTK_PIN_NO(76) | 0) -#define MT7623_PIN_76_SCL0_FUNC_SCL0 (MTK_PIN_NO(76) | 1) - -#define MT7623_PIN_77_SDA2_FUNC_GPIO77 (MTK_PIN_NO(77) | 0) -#define MT7623_PIN_77_SDA2_FUNC_SDA2 (MTK_PIN_NO(77) | 1) - -#define MT7623_PIN_78_SCL2_FUNC_GPIO78 (MTK_PIN_NO(78) | 0) -#define MT7623_PIN_78_SCL2_FUNC_SCL2 (MTK_PIN_NO(78) | 1) - -#define MT7623_PIN_79_URXD0_FUNC_GPIO79 (MTK_PIN_NO(79) | 0) -#define MT7623_PIN_79_URXD0_FUNC_URXD0 (MTK_PIN_NO(79) | 1) -#define MT7623_PIN_79_URXD0_FUNC_UTXD0 (MTK_PIN_NO(79) | 2) - -#define MT7623_PIN_80_UTXD0_FUNC_GPIO80 (MTK_PIN_NO(80) | 0) -#define MT7623_PIN_80_UTXD0_FUNC_UTXD0 (MTK_PIN_NO(80) | 1) -#define MT7623_PIN_80_UTXD0_FUNC_URXD0 (MTK_PIN_NO(80) | 2) - -#define MT7623_PIN_81_URXD1_FUNC_GPIO81 (MTK_PIN_NO(81) | 0) -#define MT7623_PIN_81_URXD1_FUNC_URXD1 (MTK_PIN_NO(81) | 1) -#define MT7623_PIN_81_URXD1_FUNC_UTXD1 (MTK_PIN_NO(81) | 2) - -#define MT7623_PIN_82_UTXD1_FUNC_GPIO82 (MTK_PIN_NO(82) | 0) -#define MT7623_PIN_82_UTXD1_FUNC_UTXD1 (MTK_PIN_NO(82) | 1) -#define MT7623_PIN_82_UTXD1_FUNC_URXD1 (MTK_PIN_NO(82) | 2) - -#define MT7623_PIN_83_LCM_RST_FUNC_GPIO83 (MTK_PIN_NO(83) | 0) -#define MT7623_PIN_83_LCM_RST_FUNC_LCM_RST (MTK_PIN_NO(83) | 1) -#define MT7623_PIN_83_LCM_RST_FUNC_VDAC_CK_XI (MTK_PIN_NO(83) | 2) - -#define MT7623_PIN_84_DSI_TE_FUNC_GPIO84 (MTK_PIN_NO(84) | 0) -#define MT7623_PIN_84_DSI_TE_FUNC_DSI_TE (MTK_PIN_NO(84) | 1) - -#define MT7623_PIN_91_MIPI_TDN3_FUNC_GPIO91 (MTK_PIN_NO(91) | 0) -#define MT7623_PIN_91_MIPI_TDN3_FUNC_TDN3 (MTK_PIN_NO(91) | 1) - -#define MT7623_PIN_92_MIPI_TDP3_FUNC_GPIO92 (MTK_PIN_NO(92) | 0) -#define MT7623_PIN_92_MIPI_TDP3_FUNC_TDP3 (MTK_PIN_NO(92) | 1) - -#define MT7623_PIN_93_MIPI_TDN2_FUNC_GPIO93 (MTK_PIN_NO(93) | 0) -#define MT7623_PIN_93_MIPI_TDN2_FUNC_TDN2 (MTK_PIN_NO(93) | 1) - -#define MT7623_PIN_94_MIPI_TDP2_FUNC_GPIO94 (MTK_PIN_NO(94) | 0) -#define MT7623_PIN_94_MIPI_TDP2_FUNC_TDP2 (MTK_PIN_NO(94) | 1) - -#define MT7623_PIN_95_MIPI_TCN_FUNC_GPIO95 (MTK_PIN_NO(95) | 0) -#define MT7623_PIN_95_MIPI_TCN_FUNC_TCN (MTK_PIN_NO(95) | 1) - -#define MT7623_PIN_96_MIPI_TCP_FUNC_GPIO96 (MTK_PIN_NO(96) | 0) -#define MT7623_PIN_96_MIPI_TCP_FUNC_TCP (MTK_PIN_NO(96) | 1) - -#define MT7623_PIN_97_MIPI_TDN1_FUNC_GPIO97 (MTK_PIN_NO(97) | 0) -#define MT7623_PIN_97_MIPI_TDN1_FUNC_TDN1 (MTK_PIN_NO(97) | 1) - -#define MT7623_PIN_98_MIPI_TDP1_FUNC_GPIO98 (MTK_PIN_NO(98) | 0) -#define MT7623_PIN_98_MIPI_TDP1_FUNC_TDP1 (MTK_PIN_NO(98) | 1) - -#define MT7623_PIN_99_MIPI_TDN0_FUNC_GPIO99 (MTK_PIN_NO(99) | 0) -#define MT7623_PIN_99_MIPI_TDN0_FUNC_TDN0 (MTK_PIN_NO(99) | 1) - -#define MT7623_PIN_100_MIPI_TDP0_FUNC_GPIO100 (MTK_PIN_NO(100) | 0) -#define MT7623_PIN_100_MIPI_TDP0_FUNC_TDP0 (MTK_PIN_NO(100) | 1) - -#define MT7623_PIN_101_SPI2_CSN_FUNC_GPIO101 (MTK_PIN_NO(101) | 0) -#define MT7623_PIN_101_SPI2_CSN_FUNC_SPI2_CS (MTK_PIN_NO(101) | 1) -#define MT7623_PIN_101_SPI2_CSN_FUNC_SCL3 (MTK_PIN_NO(101) | 3) -#define MT7623_PIN_101_SPI2_CSN_FUNC_KROW0 (MTK_PIN_NO(101) | 4) - -#define MT7623_PIN_102_SPI2_MI_FUNC_GPIO102 (MTK_PIN_NO(102) | 0) -#define MT7623_PIN_102_SPI2_MI_FUNC_SPI2_MI (MTK_PIN_NO(102) | 1) -#define MT7623_PIN_102_SPI2_MI_FUNC_SPI2_MO (MTK_PIN_NO(102) | 2) -#define MT7623_PIN_102_SPI2_MI_FUNC_SDA3 (MTK_PIN_NO(102) | 3) -#define MT7623_PIN_102_SPI2_MI_FUNC_KROW1 (MTK_PIN_NO(102) | 4) - -#define MT7623_PIN_103_SPI2_MO_FUNC_GPIO103 (MTK_PIN_NO(103) | 0) -#define MT7623_PIN_103_SPI2_MO_FUNC_SPI2_MO (MTK_PIN_NO(103) | 1) -#define MT7623_PIN_103_SPI2_MO_FUNC_SPI2_MI (MTK_PIN_NO(103) | 2) -#define MT7623_PIN_103_SPI2_MO_FUNC_SCL3 (MTK_PIN_NO(103) | 3) -#define MT7623_PIN_103_SPI2_MO_FUNC_KROW2 (MTK_PIN_NO(103) | 4) - -#define MT7623_PIN_104_SPI2_CK_FUNC_GPIO104 (MTK_PIN_NO(104) | 0) -#define MT7623_PIN_104_SPI2_CK_FUNC_SPI2_CK (MTK_PIN_NO(104) | 1) -#define MT7623_PIN_104_SPI2_CK_FUNC_SDA3 (MTK_PIN_NO(104) | 3) -#define MT7623_PIN_104_SPI2_CK_FUNC_KROW3 (MTK_PIN_NO(104) | 4) - -#define MT7623_PIN_105_MSDC1_CMD_FUNC_GPIO105 (MTK_PIN_NO(105) | 0) -#define MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD (MTK_PIN_NO(105) | 1) -#define MT7623_PIN_105_MSDC1_CMD_FUNC_SDA1 (MTK_PIN_NO(105) | 3) -#define MT7623_PIN_105_MSDC1_CMD_FUNC_I2SOUT_BCK (MTK_PIN_NO(105) | 6) - -#define MT7623_PIN_106_MSDC1_CLK_FUNC_GPIO106 (MTK_PIN_NO(106) | 0) -#define MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK (MTK_PIN_NO(106) | 1) -#define MT7623_PIN_106_MSDC1_CLK_FUNC_SCL1 (MTK_PIN_NO(106) | 3) -#define MT7623_PIN_106_MSDC1_CLK_FUNC_I2SOUT_LRCK (MTK_PIN_NO(106) | 6) - -#define MT7623_PIN_107_MSDC1_DAT0_FUNC_GPIO107 (MTK_PIN_NO(107) | 0) -#define MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0 (MTK_PIN_NO(107) | 1) -#define MT7623_PIN_107_MSDC1_DAT0_FUNC_UTXD0 (MTK_PIN_NO(107) | 5) -#define MT7623_PIN_107_MSDC1_DAT0_FUNC_I2SOUT_DATA_OUT (MTK_PIN_NO(107) | 6) - -#define MT7623_PIN_108_MSDC1_DAT1_FUNC_GPIO108 (MTK_PIN_NO(108) | 0) -#define MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1 (MTK_PIN_NO(108) | 1) -#define MT7623_PIN_108_MSDC1_DAT1_FUNC_PWM0 (MTK_PIN_NO(108) | 3) -#define MT7623_PIN_108_MSDC1_DAT1_FUNC_URXD0 (MTK_PIN_NO(108) | 5) -#define MT7623_PIN_108_MSDC1_DAT1_FUNC_PWM1 (MTK_PIN_NO(108) | 6) - -#define MT7623_PIN_109_MSDC1_DAT2_FUNC_GPIO109 (MTK_PIN_NO(109) | 0) -#define MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2 (MTK_PIN_NO(109) | 1) -#define MT7623_PIN_109_MSDC1_DAT2_FUNC_SDA2 (MTK_PIN_NO(109) | 3) -#define MT7623_PIN_109_MSDC1_DAT2_FUNC_UTXD1 (MTK_PIN_NO(109) | 5) -#define MT7623_PIN_109_MSDC1_DAT2_FUNC_PWM2 (MTK_PIN_NO(109) | 6) - -#define MT7623_PIN_110_MSDC1_DAT3_FUNC_GPIO110 (MTK_PIN_NO(110) | 0) -#define MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3 (MTK_PIN_NO(110) | 1) -#define MT7623_PIN_110_MSDC1_DAT3_FUNC_SCL2 (MTK_PIN_NO(110) | 3) -#define MT7623_PIN_110_MSDC1_DAT3_FUNC_URXD1 (MTK_PIN_NO(110) | 5) -#define MT7623_PIN_110_MSDC1_DAT3_FUNC_PWM3 (MTK_PIN_NO(110) | 6) - -#define MT7623_PIN_111_MSDC0_DAT7_FUNC_GPIO111 (MTK_PIN_NO(111) | 0) -#define MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7 (MTK_PIN_NO(111) | 1) -#define MT7623_PIN_111_MSDC0_DAT7_FUNC_NLD7 (MTK_PIN_NO(111) | 4) - -#define MT7623_PIN_112_MSDC0_DAT6_FUNC_GPIO112 (MTK_PIN_NO(112) | 0) -#define MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6 (MTK_PIN_NO(112) | 1) -#define MT7623_PIN_112_MSDC0_DAT6_FUNC_NLD6 (MTK_PIN_NO(112) | 4) - -#define MT7623_PIN_113_MSDC0_DAT5_FUNC_GPIO113 (MTK_PIN_NO(113) | 0) -#define MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5 (MTK_PIN_NO(113) | 1) -#define MT7623_PIN_113_MSDC0_DAT5_FUNC_NLD5 (MTK_PIN_NO(113) | 4) - -#define MT7623_PIN_114_MSDC0_DAT4_FUNC_GPIO114 (MTK_PIN_NO(114) | 0) -#define MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4 (MTK_PIN_NO(114) | 1) -#define MT7623_PIN_114_MSDC0_DAT4_FUNC_NLD4 (MTK_PIN_NO(114) | 4) - -#define MT7623_PIN_115_MSDC0_RSTB_FUNC_GPIO115 (MTK_PIN_NO(115) | 0) -#define MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB (MTK_PIN_NO(115) | 1) -#define MT7623_PIN_115_MSDC0_RSTB_FUNC_NLD8 (MTK_PIN_NO(115) | 4) - -#define MT7623_PIN_116_MSDC0_CMD_FUNC_GPIO116 (MTK_PIN_NO(116) | 0) -#define MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD (MTK_PIN_NO(116) | 1) -#define MT7623_PIN_116_MSDC0_CMD_FUNC_NALE (MTK_PIN_NO(116) | 4) - -#define MT7623_PIN_117_MSDC0_CLK_FUNC_GPIO117 (MTK_PIN_NO(117) | 0) -#define MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK (MTK_PIN_NO(117) | 1) -#define MT7623_PIN_117_MSDC0_CLK_FUNC_NWEB (MTK_PIN_NO(117) | 4) - -#define MT7623_PIN_118_MSDC0_DAT3_FUNC_GPIO118 (MTK_PIN_NO(118) | 0) -#define MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3 (MTK_PIN_NO(118) | 1) -#define MT7623_PIN_118_MSDC0_DAT3_FUNC_NLD3 (MTK_PIN_NO(118) | 4) - -#define MT7623_PIN_119_MSDC0_DAT2_FUNC_GPIO119 (MTK_PIN_NO(119) | 0) -#define MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2 (MTK_PIN_NO(119) | 1) -#define MT7623_PIN_119_MSDC0_DAT2_FUNC_NLD2 (MTK_PIN_NO(119) | 4) - -#define MT7623_PIN_120_MSDC0_DAT1_FUNC_GPIO120 (MTK_PIN_NO(120) | 0) -#define MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1 (MTK_PIN_NO(120) | 1) -#define MT7623_PIN_120_MSDC0_DAT1_FUNC_NLD1 (MTK_PIN_NO(120) | 4) - -#define MT7623_PIN_121_MSDC0_DAT0_FUNC_GPIO121 (MTK_PIN_NO(121) | 0) -#define MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0 (MTK_PIN_NO(121) | 1) -#define MT7623_PIN_121_MSDC0_DAT0_FUNC_NLD0 (MTK_PIN_NO(121) | 4) -#define MT7623_PIN_121_MSDC0_DAT0_FUNC_WATCHDOG (MTK_PIN_NO(121) | 5) - -#define MT7623_PIN_122_GPIO122_FUNC_GPIO122 (MTK_PIN_NO(122) | 0) -#define MT7623_PIN_122_GPIO122_FUNC_CEC (MTK_PIN_NO(122) | 1) -#define MT7623_PIN_122_GPIO122_FUNC_SDA2 (MTK_PIN_NO(122) | 4) -#define MT7623_PIN_122_GPIO122_FUNC_URXD0 (MTK_PIN_NO(122) | 5) - -#define MT7623_PIN_123_HTPLG_FUNC_GPIO123 (MTK_PIN_NO(123) | 0) -#define MT7623_PIN_123_HTPLG_FUNC_HTPLG (MTK_PIN_NO(123) | 1) -#define MT7623_PIN_123_HTPLG_FUNC_SCL2 (MTK_PIN_NO(123) | 4) -#define MT7623_PIN_123_HTPLG_FUNC_UTXD0 (MTK_PIN_NO(123) | 5) - -#define MT7623_PIN_124_GPIO124_FUNC_GPIO124 (MTK_PIN_NO(124) | 0) -#define MT7623_PIN_124_GPIO124_FUNC_HDMISCK (MTK_PIN_NO(124) | 1) -#define MT7623_PIN_124_GPIO124_FUNC_SDA1 (MTK_PIN_NO(124) | 4) -#define MT7623_PIN_124_GPIO124_FUNC_PWM3 (MTK_PIN_NO(124) | 5) - -#define MT7623_PIN_125_GPIO125_FUNC_GPIO125 (MTK_PIN_NO(125) | 0) -#define MT7623_PIN_125_GPIO125_FUNC_HDMISD (MTK_PIN_NO(125) | 1) -#define MT7623_PIN_125_GPIO125_FUNC_SCL1 (MTK_PIN_NO(125) | 4) -#define MT7623_PIN_125_GPIO125_FUNC_PWM4 (MTK_PIN_NO(125) | 5) - -#define MT7623_PIN_126_I2S0_MCLK_FUNC_GPIO126 (MTK_PIN_NO(126) | 0) -#define MT7623_PIN_126_I2S0_MCLK_FUNC_I2S0_MCLK (MTK_PIN_NO(126) | 1) -#define MT7623_PIN_126_I2S0_MCLK_FUNC_AP_I2S_MCLK (MTK_PIN_NO(126) | 6) - -#define MT7623_PIN_199_SPI1_CK_FUNC_GPIO199 (MTK_PIN_NO(199) | 0) -#define MT7623_PIN_199_SPI1_CK_FUNC_SPI1_CK (MTK_PIN_NO(199) | 1) - -#define MT7623_PIN_200_URXD2_FUNC_GPIO200 (MTK_PIN_NO(200) | 0) -#define MT7623_PIN_200_URXD2_FUNC_URXD2 (MTK_PIN_NO(200) | 6) - -#define MT7623_PIN_201_UTXD2_FUNC_GPIO201 (MTK_PIN_NO(201) | 0) -#define MT7623_PIN_201_UTXD2_FUNC_UTXD2 (MTK_PIN_NO(201) | 6) - -#define MT7623_PIN_203_PWM0_FUNC_GPIO203 (MTK_PIN_NO(203) | 0) -#define MT7623_PIN_203_PWM0_FUNC_PWM0 (MTK_PIN_NO(203) | 1) -#define MT7623_PIN_203_PWM0_FUNC_DISP_PWM (MTK_PIN_NO(203) | 2) - -#define MT7623_PIN_204_PWM1_FUNC_GPIO204 (MTK_PIN_NO(204) | 0) -#define MT7623_PIN_204_PWM1_FUNC_PWM1 (MTK_PIN_NO(204) | 1) - -#define MT7623_PIN_205_PWM2_FUNC_GPIO205 (MTK_PIN_NO(205) | 0) -#define MT7623_PIN_205_PWM2_FUNC_PWM2 (MTK_PIN_NO(205) | 1) - -#define MT7623_PIN_206_PWM3_FUNC_GPIO206 (MTK_PIN_NO(206) | 0) -#define MT7623_PIN_206_PWM3_FUNC_PWM3 (MTK_PIN_NO(206) | 1) - -#define MT7623_PIN_207_PWM4_FUNC_GPIO207 (MTK_PIN_NO(207) | 0) -#define MT7623_PIN_207_PWM4_FUNC_PWM4 (MTK_PIN_NO(207) | 1) - -#define MT7623_PIN_208_AUD_EXT_CK1_FUNC_GPIO208 (MTK_PIN_NO(208) | 0) -#define MT7623_PIN_208_AUD_EXT_CK1_FUNC_AUD_EXT_CK1 (MTK_PIN_NO(208) | 1) -#define MT7623_PIN_208_AUD_EXT_CK1_FUNC_PWM0 (MTK_PIN_NO(208) | 2) -#define MT7623_PIN_208_AUD_EXT_CK1_FUNC_PCIE0_PERST_N (MTK_PIN_NO(208) | 3) -#define MT7623_PIN_208_AUD_EXT_CK1_FUNC_DISP_PWM (MTK_PIN_NO(208) | 5) - -#define MT7623_PIN_209_AUD_EXT_CK2_FUNC_GPIO209 (MTK_PIN_NO(209) | 0) -#define MT7623_PIN_209_AUD_EXT_CK2_FUNC_AUD_EXT_CK2 (MTK_PIN_NO(209) | 1) -#define MT7623_PIN_209_AUD_EXT_CK2_FUNC_MSDC1_WP (MTK_PIN_NO(209) | 2) -#define MT7623_PIN_209_AUD_EXT_CK2_FUNC_PCIE1_PERST_N (MTK_PIN_NO(209) | 3) -#define MT7623_PIN_209_AUD_EXT_CK2_FUNC_PWM1 (MTK_PIN_NO(209) | 5) - -#define MT7623_PIN_236_EXT_SDIO3_FUNC_GPIO236 (MTK_PIN_NO(236) | 0) -#define MT7623_PIN_236_EXT_SDIO3_FUNC_EXT_SDIO3 (MTK_PIN_NO(236) | 1) -#define MT7623_PIN_236_EXT_SDIO3_FUNC_IDDIG (MTK_PIN_NO(236) | 2) - -#define MT7623_PIN_237_EXT_SDIO2_FUNC_GPIO237 (MTK_PIN_NO(237) | 0) -#define MT7623_PIN_237_EXT_SDIO2_FUNC_EXT_SDIO2 (MTK_PIN_NO(237) | 1) -#define MT7623_PIN_237_EXT_SDIO2_FUNC_DRV_VBUS (MTK_PIN_NO(237) | 2) - -#define MT7623_PIN_238_EXT_SDIO1_FUNC_GPIO238 (MTK_PIN_NO(238) | 0) -#define MT7623_PIN_238_EXT_SDIO1_FUNC_EXT_SDIO1 (MTK_PIN_NO(238) | 1) - -#define MT7623_PIN_239_EXT_SDIO0_FUNC_GPIO239 (MTK_PIN_NO(239) | 0) -#define MT7623_PIN_239_EXT_SDIO0_FUNC_EXT_SDIO0 (MTK_PIN_NO(239) | 1) - -#define MT7623_PIN_240_EXT_XCS_FUNC_GPIO240 (MTK_PIN_NO(240) | 0) -#define MT7623_PIN_240_EXT_XCS_FUNC_EXT_XCS (MTK_PIN_NO(240) | 1) - -#define MT7623_PIN_241_EXT_SCK_FUNC_GPIO241 (MTK_PIN_NO(241) | 0) -#define MT7623_PIN_241_EXT_SCK_FUNC_EXT_SCK (MTK_PIN_NO(241) | 1) - -#define MT7623_PIN_242_URTS2_FUNC_GPIO242 (MTK_PIN_NO(242) | 0) -#define MT7623_PIN_242_URTS2_FUNC_URTS2 (MTK_PIN_NO(242) | 1) -#define MT7623_PIN_242_URTS2_FUNC_UTXD3 (MTK_PIN_NO(242) | 2) -#define MT7623_PIN_242_URTS2_FUNC_URXD3 (MTK_PIN_NO(242) | 3) -#define MT7623_PIN_242_URTS2_FUNC_SCL1 (MTK_PIN_NO(242) | 4) - -#define MT7623_PIN_243_UCTS2_FUNC_GPIO243 (MTK_PIN_NO(243) | 0) -#define MT7623_PIN_243_UCTS2_FUNC_UCTS2 (MTK_PIN_NO(243) | 1) -#define MT7623_PIN_243_UCTS2_FUNC_URXD3 (MTK_PIN_NO(243) | 2) -#define MT7623_PIN_243_UCTS2_FUNC_UTXD3 (MTK_PIN_NO(243) | 3) -#define MT7623_PIN_243_UCTS2_FUNC_SDA1 (MTK_PIN_NO(243) | 4) - -#define MT7623_PIN_250_GPIO250_FUNC_GPIO250 (MTK_PIN_NO(250) | 0) -#define MT7623_PIN_250_GPIO250_FUNC_TEST_MD7 (MTK_PIN_NO(250) | 1) -#define MT7623_PIN_250_GPIO250_FUNC_PCIE0_CLKREQ_N (MTK_PIN_NO(250) | 6) - -#define MT7623_PIN_251_GPIO251_FUNC_GPIO251 (MTK_PIN_NO(251) | 0) -#define MT7623_PIN_251_GPIO251_FUNC_TEST_MD6 (MTK_PIN_NO(251) | 1) -#define MT7623_PIN_251_GPIO251_FUNC_PCIE0_WAKE_N (MTK_PIN_NO(251) | 6) - -#define MT7623_PIN_252_GPIO252_FUNC_GPIO252 (MTK_PIN_NO(252) | 0) -#define MT7623_PIN_252_GPIO252_FUNC_TEST_MD5 (MTK_PIN_NO(252) | 1) -#define MT7623_PIN_252_GPIO252_FUNC_PCIE1_CLKREQ_N (MTK_PIN_NO(252) | 6) - -#define MT7623_PIN_253_GPIO253_FUNC_GPIO253 (MTK_PIN_NO(253) | 0) -#define MT7623_PIN_253_GPIO253_FUNC_TEST_MD4 (MTK_PIN_NO(253) | 1) -#define MT7623_PIN_253_GPIO253_FUNC_PCIE1_WAKE_N (MTK_PIN_NO(253) | 6) - -#define MT7623_PIN_254_GPIO254_FUNC_GPIO254 (MTK_PIN_NO(254) | 0) -#define MT7623_PIN_254_GPIO254_FUNC_TEST_MD3 (MTK_PIN_NO(254) | 1) -#define MT7623_PIN_254_GPIO254_FUNC_PCIE2_CLKREQ_N (MTK_PIN_NO(254) | 6) - -#define MT7623_PIN_255_GPIO255_FUNC_GPIO255 (MTK_PIN_NO(255) | 0) -#define MT7623_PIN_255_GPIO255_FUNC_TEST_MD2 (MTK_PIN_NO(255) | 1) -#define MT7623_PIN_255_GPIO255_FUNC_PCIE2_WAKE_N (MTK_PIN_NO(255) | 6) - -#define MT7623_PIN_256_GPIO256_FUNC_GPIO256 (MTK_PIN_NO(256) | 0) -#define MT7623_PIN_256_GPIO256_FUNC_TEST_MD1 (MTK_PIN_NO(256) | 1) - -#define MT7623_PIN_257_GPIO257_FUNC_GPIO257 (MTK_PIN_NO(257) | 0) -#define MT7623_PIN_257_GPIO257_FUNC_TEST_MD0 (MTK_PIN_NO(257) | 1) - -#define MT7623_PIN_261_MSDC1_INS_FUNC_GPIO261 (MTK_PIN_NO(261) | 0) -#define MT7623_PIN_261_MSDC1_INS_FUNC_MSDC1_INS (MTK_PIN_NO(261) | 1) - -#define MT7623_PIN_262_G2_TXEN_FUNC_GPIO262 (MTK_PIN_NO(262) | 0) -#define MT7623_PIN_262_G2_TXEN_FUNC_G2_TXEN (MTK_PIN_NO(262) | 1) - -#define MT7623_PIN_263_G2_TXD3_FUNC_GPIO263 (MTK_PIN_NO(263) | 0) -#define MT7623_PIN_263_G2_TXD3_FUNC_G2_TXD3 (MTK_PIN_NO(263) | 1) - -#define MT7623_PIN_264_G2_TXD2_FUNC_GPIO264 (MTK_PIN_NO(264) | 0) -#define MT7623_PIN_264_G2_TXD2_FUNC_G2_TXD2 (MTK_PIN_NO(264) | 1) - -#define MT7623_PIN_265_G2_TXD1_FUNC_GPIO265 (MTK_PIN_NO(265) | 0) -#define MT7623_PIN_265_G2_TXD1_FUNC_G2_TXD1 (MTK_PIN_NO(265) | 1) - -#define MT7623_PIN_266_G2_TXD0_FUNC_GPIO266 (MTK_PIN_NO(266) | 0) -#define MT7623_PIN_266_G2_TXD0_FUNC_G2_TXD0 (MTK_PIN_NO(266) | 1) - -#define MT7623_PIN_267_G2_TXCLK_FUNC_GPIO267 (MTK_PIN_NO(267) | 0) -#define MT7623_PIN_267_G2_TXCLK_FUNC_G2_TXC (MTK_PIN_NO(267) | 1) - -#define MT7623_PIN_268_G2_RXCLK_FUNC_GPIO268 (MTK_PIN_NO(268) | 0) -#define MT7623_PIN_268_G2_RXCLK_FUNC_G2_RXC (MTK_PIN_NO(268) | 1) - -#define MT7623_PIN_269_G2_RXD0_FUNC_GPIO269 (MTK_PIN_NO(269) | 0) -#define MT7623_PIN_269_G2_RXD0_FUNC_G2_RXD0 (MTK_PIN_NO(269) | 1) - -#define MT7623_PIN_270_G2_RXD1_FUNC_GPIO270 (MTK_PIN_NO(270) | 0) -#define MT7623_PIN_270_G2_RXD1_FUNC_G2_RXD1 (MTK_PIN_NO(270) | 1) - -#define MT7623_PIN_271_G2_RXD2_FUNC_GPIO271 (MTK_PIN_NO(271) | 0) -#define MT7623_PIN_271_G2_RXD2_FUNC_G2_RXD2 (MTK_PIN_NO(271) | 1) - -#define MT7623_PIN_272_G2_RXD3_FUNC_GPIO272 (MTK_PIN_NO(272) | 0) -#define MT7623_PIN_272_G2_RXD3_FUNC_G2_RXD3 (MTK_PIN_NO(272) | 1) - -#define MT7623_PIN_274_G2_RXDV_FUNC_GPIO274 (MTK_PIN_NO(274) | 0) -#define MT7623_PIN_274_G2_RXDV_FUNC_G2_RXDV (MTK_PIN_NO(274) | 1) - -#define MT7623_PIN_275_G2_MDC_FUNC_GPIO275 (MTK_PIN_NO(275) | 0) -#define MT7623_PIN_275_G2_MDC_FUNC_MDC (MTK_PIN_NO(275) | 1) - -#define MT7623_PIN_276_G2_MDIO_FUNC_GPIO276 (MTK_PIN_NO(276) | 0) -#define MT7623_PIN_276_G2_MDIO_FUNC_MDIO (MTK_PIN_NO(276) | 1) - -#define MT7623_PIN_278_JTAG_RESET_FUNC_GPIO278 (MTK_PIN_NO(278) | 0) -#define MT7623_PIN_278_JTAG_RESET_FUNC_JTAG_RESET (MTK_PIN_NO(278) | 1) - -#endif /* __DTS_MT7623_PINFUNC_H */ diff --git a/sys/gnu/dts/include/dt-bindings/pinctrl/nomadik.h b/sys/gnu/dts/include/dt-bindings/pinctrl/nomadik.h deleted file mode 100644 index fa24565e000..00000000000 --- a/sys/gnu/dts/include/dt-bindings/pinctrl/nomadik.h +++ /dev/null @@ -1,36 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * nomadik.h - * - * Copyright (C) ST-Ericsson SA 2013 - * Author: Gabriel Fernandez for ST-Ericsson. - */ - -#define INPUT_NOPULL 0 -#define INPUT_PULLUP 1 -#define INPUT_PULLDOWN 2 - -#define OUTPUT_LOW 0 -#define OUTPUT_HIGH 1 -#define DIR_OUTPUT 2 - -#define SLPM_DISABLED 0 -#define SLPM_ENABLED 1 - -#define SLPM_INPUT_NOPULL 0 -#define SLPM_INPUT_PULLUP 1 -#define SLPM_INPUT_PULLDOWN 2 -#define SLPM_DIR_INPUT 3 - -#define SLPM_OUTPUT_LOW 0 -#define SLPM_OUTPUT_HIGH 1 -#define SLPM_DIR_OUTPUT 2 - -#define SLPM_WAKEUP_DISABLE 0 -#define SLPM_WAKEUP_ENABLE 1 - -#define GPIOMODE_DISABLED 0 -#define GPIOMODE_ENABLED 1 - -#define SLPM_PDIS_DISABLED 0 -#define SLPM_PDIS_ENABLED 1 diff --git a/sys/gnu/dts/include/dt-bindings/pinctrl/omap.h b/sys/gnu/dts/include/dt-bindings/pinctrl/omap.h deleted file mode 100644 index 62571804241..00000000000 --- a/sys/gnu/dts/include/dt-bindings/pinctrl/omap.h +++ /dev/null @@ -1,92 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides constants for OMAP pinctrl bindings. - * - * Copyright (C) 2009 Nokia - * Copyright (C) 2009-2010 Texas Instruments - */ - -#ifndef _DT_BINDINGS_PINCTRL_OMAP_H -#define _DT_BINDINGS_PINCTRL_OMAP_H - -/* 34xx mux mode options for each pin. See TRM for options */ -#define MUX_MODE0 0 -#define MUX_MODE1 1 -#define MUX_MODE2 2 -#define MUX_MODE3 3 -#define MUX_MODE4 4 -#define MUX_MODE5 5 -#define MUX_MODE6 6 -#define MUX_MODE7 7 - -/* 24xx/34xx mux bit defines */ -#define PULL_ENA (1 << 3) -#define PULL_UP (1 << 4) -#define ALTELECTRICALSEL (1 << 5) - -/* omap3/4/5 specific mux bit defines */ -#define INPUT_EN (1 << 8) -#define OFF_EN (1 << 9) -#define OFFOUT_EN (1 << 10) -#define OFFOUT_VAL (1 << 11) -#define OFF_PULL_EN (1 << 12) -#define OFF_PULL_UP (1 << 13) -#define WAKEUP_EN (1 << 14) -#define WAKEUP_EVENT (1 << 15) - -/* Active pin states */ -#define PIN_OUTPUT 0 -#define PIN_OUTPUT_PULLUP (PIN_OUTPUT | PULL_ENA | PULL_UP) -#define PIN_OUTPUT_PULLDOWN (PIN_OUTPUT | PULL_ENA) -#define PIN_INPUT INPUT_EN -#define PIN_INPUT_PULLUP (PULL_ENA | INPUT_EN | PULL_UP) -#define PIN_INPUT_PULLDOWN (PULL_ENA | INPUT_EN) - -/* Off mode states */ -#define PIN_OFF_NONE 0 -#define PIN_OFF_OUTPUT_HIGH (OFF_EN | OFFOUT_EN | OFFOUT_VAL) -#define PIN_OFF_OUTPUT_LOW (OFF_EN | OFFOUT_EN) -#define PIN_OFF_INPUT_PULLUP (OFF_EN | OFFOUT_EN | OFF_PULL_EN | OFF_PULL_UP) -#define PIN_OFF_INPUT_PULLDOWN (OFF_EN | OFFOUT_EN | OFF_PULL_EN) -#define PIN_OFF_WAKEUPENABLE WAKEUP_EN - -/* - * Macros to allow using the absolute physical address instead of the - * padconf registers instead of the offset from padconf base. - */ -#define OMAP_IOPAD_OFFSET(pa, offset) (((pa) & 0xffff) - (offset)) - -#define OMAP2420_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0030) (val) -#define OMAP2430_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2030) (val) -#define OMAP3_CORE1_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2030) (val) -#define OMAP3430_CORE2_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x25d8) (val) -#define OMAP3630_CORE2_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x25a0) (val) -#define OMAP3_WKUP_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2a00) (val) -#define DM814X_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val) -#define DM816X_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val) -#define AM33XX_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val) -#define AM33XX_PADCONF(pa, dir, mux) OMAP_IOPAD_OFFSET((pa), 0x0800) ((dir) | (mux)) - -/* - * Macros to allow using the offset from the padconf physical address - * instead of the offset from padconf base. - */ -#define OMAP_PADCONF_OFFSET(offset, base_offset) ((offset) - (base_offset)) - -#define OMAP4_IOPAD(offset, val) OMAP_PADCONF_OFFSET((offset), 0x0040) (val) -#define OMAP5_IOPAD(offset, val) OMAP_PADCONF_OFFSET((offset), 0x0040) (val) - -/* - * Define some commonly used pins configured by the boards. - * Note that some boards use alternative pins, so check - * the schematics before using these. - */ -#define OMAP3_UART1_RX 0x152 -#define OMAP3_UART2_RX 0x14a -#define OMAP3_UART3_RX 0x16e -#define OMAP4_UART2_RX 0xdc -#define OMAP4_UART3_RX 0x104 -#define OMAP4_UART4_RX 0x11c - -#endif - diff --git a/sys/gnu/dts/include/dt-bindings/pinctrl/pads-imx8qm.h b/sys/gnu/dts/include/dt-bindings/pinctrl/pads-imx8qm.h deleted file mode 100644 index ae7b2942da6..00000000000 --- a/sys/gnu/dts/include/dt-bindings/pinctrl/pads-imx8qm.h +++ /dev/null @@ -1,960 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2016 Freescale Semiconductor, Inc. - * Copyright 2017~2018 NXP - */ - -#ifndef _IMX8QM_PADS_H -#define _IMX8QM_PADS_H - -/* pin id */ -#define IMX8QM_SIM0_CLK 0 -#define IMX8QM_SIM0_RST 1 -#define IMX8QM_SIM0_IO 2 -#define IMX8QM_SIM0_PD 3 -#define IMX8QM_SIM0_POWER_EN 4 -#define IMX8QM_SIM0_GPIO0_00 5 -#define IMX8QM_COMP_CTL_GPIO_1V8_3V3_SIM 6 -#define IMX8QM_M40_I2C0_SCL 7 -#define IMX8QM_M40_I2C0_SDA 8 -#define IMX8QM_M40_GPIO0_00 9 -#define IMX8QM_M40_GPIO0_01 10 -#define IMX8QM_M41_I2C0_SCL 11 -#define IMX8QM_M41_I2C0_SDA 12 -#define IMX8QM_M41_GPIO0_00 13 -#define IMX8QM_M41_GPIO0_01 14 -#define IMX8QM_GPT0_CLK 15 -#define IMX8QM_GPT0_CAPTURE 16 -#define IMX8QM_GPT0_COMPARE 17 -#define IMX8QM_GPT1_CLK 18 -#define IMX8QM_GPT1_CAPTURE 19 -#define IMX8QM_GPT1_COMPARE 20 -#define IMX8QM_UART0_RX 21 -#define IMX8QM_UART0_TX 22 -#define IMX8QM_UART0_RTS_B 23 -#define IMX8QM_UART0_CTS_B 24 -#define IMX8QM_UART1_TX 25 -#define IMX8QM_UART1_RX 26 -#define IMX8QM_UART1_RTS_B 27 -#define IMX8QM_UART1_CTS_B 28 -#define IMX8QM_COMP_CTL_GPIO_1V8_3V3_GPIOLH 29 -#define IMX8QM_SCU_PMIC_MEMC_ON 30 -#define IMX8QM_SCU_WDOG_OUT 31 -#define IMX8QM_PMIC_I2C_SDA 32 -#define IMX8QM_PMIC_I2C_SCL 33 -#define IMX8QM_PMIC_EARLY_WARNING 34 -#define IMX8QM_PMIC_INT_B 35 -#define IMX8QM_SCU_GPIO0_00 36 -#define IMX8QM_SCU_GPIO0_01 37 -#define IMX8QM_SCU_GPIO0_02 38 -#define IMX8QM_SCU_GPIO0_03 39 -#define IMX8QM_SCU_GPIO0_04 40 -#define IMX8QM_SCU_GPIO0_05 41 -#define IMX8QM_SCU_GPIO0_06 42 -#define IMX8QM_SCU_GPIO0_07 43 -#define IMX8QM_SCU_BOOT_MODE0 44 -#define IMX8QM_SCU_BOOT_MODE1 45 -#define IMX8QM_SCU_BOOT_MODE2 46 -#define IMX8QM_SCU_BOOT_MODE3 47 -#define IMX8QM_SCU_BOOT_MODE4 48 -#define IMX8QM_SCU_BOOT_MODE5 49 -#define IMX8QM_LVDS0_GPIO00 50 -#define IMX8QM_LVDS0_GPIO01 51 -#define IMX8QM_LVDS0_I2C0_SCL 52 -#define IMX8QM_LVDS0_I2C0_SDA 53 -#define IMX8QM_LVDS0_I2C1_SCL 54 -#define IMX8QM_LVDS0_I2C1_SDA 55 -#define IMX8QM_LVDS1_GPIO00 56 -#define IMX8QM_LVDS1_GPIO01 57 -#define IMX8QM_LVDS1_I2C0_SCL 58 -#define IMX8QM_LVDS1_I2C0_SDA 59 -#define IMX8QM_LVDS1_I2C1_SCL 60 -#define IMX8QM_LVDS1_I2C1_SDA 61 -#define IMX8QM_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO 62 -#define IMX8QM_MIPI_DSI0_I2C0_SCL 63 -#define IMX8QM_MIPI_DSI0_I2C0_SDA 64 -#define IMX8QM_MIPI_DSI0_GPIO0_00 65 -#define IMX8QM_MIPI_DSI0_GPIO0_01 66 -#define IMX8QM_MIPI_DSI1_I2C0_SCL 67 -#define IMX8QM_MIPI_DSI1_I2C0_SDA 68 -#define IMX8QM_MIPI_DSI1_GPIO0_00 69 -#define IMX8QM_MIPI_DSI1_GPIO0_01 70 -#define IMX8QM_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO 71 -#define IMX8QM_MIPI_CSI0_MCLK_OUT 72 -#define IMX8QM_MIPI_CSI0_I2C0_SCL 73 -#define IMX8QM_MIPI_CSI0_I2C0_SDA 74 -#define IMX8QM_MIPI_CSI0_GPIO0_00 75 -#define IMX8QM_MIPI_CSI0_GPIO0_01 76 -#define IMX8QM_MIPI_CSI1_MCLK_OUT 77 -#define IMX8QM_MIPI_CSI1_GPIO0_00 78 -#define IMX8QM_MIPI_CSI1_GPIO0_01 79 -#define IMX8QM_MIPI_CSI1_I2C0_SCL 80 -#define IMX8QM_MIPI_CSI1_I2C0_SDA 81 -#define IMX8QM_HDMI_TX0_TS_SCL 82 -#define IMX8QM_HDMI_TX0_TS_SDA 83 -#define IMX8QM_COMP_CTL_GPIO_3V3_HDMIGPIO 84 -#define IMX8QM_ESAI1_FSR 85 -#define IMX8QM_ESAI1_FST 86 -#define IMX8QM_ESAI1_SCKR 87 -#define IMX8QM_ESAI1_SCKT 88 -#define IMX8QM_ESAI1_TX0 89 -#define IMX8QM_ESAI1_TX1 90 -#define IMX8QM_ESAI1_TX2_RX3 91 -#define IMX8QM_ESAI1_TX3_RX2 92 -#define IMX8QM_ESAI1_TX4_RX1 93 -#define IMX8QM_ESAI1_TX5_RX0 94 -#define IMX8QM_SPDIF0_RX 95 -#define IMX8QM_SPDIF0_TX 96 -#define IMX8QM_SPDIF0_EXT_CLK 97 -#define IMX8QM_SPI3_SCK 98 -#define IMX8QM_SPI3_SDO 99 -#define IMX8QM_SPI3_SDI 100 -#define IMX8QM_SPI3_CS0 101 -#define IMX8QM_SPI3_CS1 102 -#define IMX8QM_COMP_CTL_GPIO_1V8_3V3_GPIORHB 103 -#define IMX8QM_ESAI0_FSR 104 -#define IMX8QM_ESAI0_FST 105 -#define IMX8QM_ESAI0_SCKR 106 -#define IMX8QM_ESAI0_SCKT 107 -#define IMX8QM_ESAI0_TX0 108 -#define IMX8QM_ESAI0_TX1 109 -#define IMX8QM_ESAI0_TX2_RX3 110 -#define IMX8QM_ESAI0_TX3_RX2 111 -#define IMX8QM_ESAI0_TX4_RX1 112 -#define IMX8QM_ESAI0_TX5_RX0 113 -#define IMX8QM_MCLK_IN0 114 -#define IMX8QM_MCLK_OUT0 115 -#define IMX8QM_COMP_CTL_GPIO_1V8_3V3_GPIORHC 116 -#define IMX8QM_SPI0_SCK 117 -#define IMX8QM_SPI0_SDO 118 -#define IMX8QM_SPI0_SDI 119 -#define IMX8QM_SPI0_CS0 120 -#define IMX8QM_SPI0_CS1 121 -#define IMX8QM_SPI2_SCK 122 -#define IMX8QM_SPI2_SDO 123 -#define IMX8QM_SPI2_SDI 124 -#define IMX8QM_SPI2_CS0 125 -#define IMX8QM_SPI2_CS1 126 -#define IMX8QM_SAI1_RXC 127 -#define IMX8QM_SAI1_RXD 128 -#define IMX8QM_SAI1_RXFS 129 -#define IMX8QM_SAI1_TXC 130 -#define IMX8QM_SAI1_TXD 131 -#define IMX8QM_SAI1_TXFS 132 -#define IMX8QM_COMP_CTL_GPIO_1V8_3V3_GPIORHT 133 -#define IMX8QM_ADC_IN7 134 -#define IMX8QM_ADC_IN6 135 -#define IMX8QM_ADC_IN5 136 -#define IMX8QM_ADC_IN4 137 -#define IMX8QM_ADC_IN3 138 -#define IMX8QM_ADC_IN2 139 -#define IMX8QM_ADC_IN1 140 -#define IMX8QM_ADC_IN0 141 -#define IMX8QM_MLB_SIG 142 -#define IMX8QM_MLB_CLK 143 -#define IMX8QM_MLB_DATA 144 -#define IMX8QM_COMP_CTL_GPIO_1V8_3V3_GPIOLHT 145 -#define IMX8QM_FLEXCAN0_RX 146 -#define IMX8QM_FLEXCAN0_TX 147 -#define IMX8QM_FLEXCAN1_RX 148 -#define IMX8QM_FLEXCAN1_TX 149 -#define IMX8QM_FLEXCAN2_RX 150 -#define IMX8QM_FLEXCAN2_TX 151 -#define IMX8QM_COMP_CTL_GPIO_1V8_3V3_GPIOTHR 152 -#define IMX8QM_USB_SS3_TC0 153 -#define IMX8QM_USB_SS3_TC1 154 -#define IMX8QM_USB_SS3_TC2 155 -#define IMX8QM_USB_SS3_TC3 156 -#define IMX8QM_COMP_CTL_GPIO_3V3_USB3IO 157 -#define IMX8QM_USDHC1_RESET_B 158 -#define IMX8QM_USDHC1_VSELECT 159 -#define IMX8QM_USDHC2_RESET_B 160 -#define IMX8QM_USDHC2_VSELECT 161 -#define IMX8QM_USDHC2_WP 162 -#define IMX8QM_USDHC2_CD_B 163 -#define IMX8QM_COMP_CTL_GPIO_1V8_3V3_VSELSEP 164 -#define IMX8QM_ENET0_MDIO 165 -#define IMX8QM_ENET0_MDC 166 -#define IMX8QM_ENET0_REFCLK_125M_25M 167 -#define IMX8QM_ENET1_REFCLK_125M_25M 168 -#define IMX8QM_ENET1_MDIO 169 -#define IMX8QM_ENET1_MDC 170 -#define IMX8QM_COMP_CTL_GPIO_1V8_3V3_GPIOCT 171 -#define IMX8QM_QSPI1A_SS0_B 172 -#define IMX8QM_QSPI1A_SS1_B 173 -#define IMX8QM_QSPI1A_SCLK 174 -#define IMX8QM_QSPI1A_DQS 175 -#define IMX8QM_QSPI1A_DATA3 176 -#define IMX8QM_QSPI1A_DATA2 177 -#define IMX8QM_QSPI1A_DATA1 178 -#define IMX8QM_QSPI1A_DATA0 179 -#define IMX8QM_COMP_CTL_GPIO_1V8_3V3_QSPI1 180 -#define IMX8QM_QSPI0A_DATA0 181 -#define IMX8QM_QSPI0A_DATA1 182 -#define IMX8QM_QSPI0A_DATA2 183 -#define IMX8QM_QSPI0A_DATA3 184 -#define IMX8QM_QSPI0A_DQS 185 -#define IMX8QM_QSPI0A_SS0_B 186 -#define IMX8QM_QSPI0A_SS1_B 187 -#define IMX8QM_QSPI0A_SCLK 188 -#define IMX8QM_QSPI0B_SCLK 189 -#define IMX8QM_QSPI0B_DATA0 190 -#define IMX8QM_QSPI0B_DATA1 191 -#define IMX8QM_QSPI0B_DATA2 192 -#define IMX8QM_QSPI0B_DATA3 193 -#define IMX8QM_QSPI0B_DQS 194 -#define IMX8QM_QSPI0B_SS0_B 195 -#define IMX8QM_QSPI0B_SS1_B 196 -#define IMX8QM_COMP_CTL_GPIO_1V8_3V3_QSPI0 197 -#define IMX8QM_PCIE_CTRL0_CLKREQ_B 198 -#define IMX8QM_PCIE_CTRL0_WAKE_B 199 -#define IMX8QM_PCIE_CTRL0_PERST_B 200 -#define IMX8QM_PCIE_CTRL1_CLKREQ_B 201 -#define IMX8QM_PCIE_CTRL1_WAKE_B 202 -#define IMX8QM_PCIE_CTRL1_PERST_B 203 -#define IMX8QM_COMP_CTL_GPIO_1V8_3V3_PCIESEP 204 -#define IMX8QM_USB_HSIC0_DATA 205 -#define IMX8QM_USB_HSIC0_STROBE 206 -#define IMX8QM_CALIBRATION_0_HSIC 207 -#define IMX8QM_CALIBRATION_1_HSIC 208 -#define IMX8QM_EMMC0_CLK 209 -#define IMX8QM_EMMC0_CMD 210 -#define IMX8QM_EMMC0_DATA0 211 -#define IMX8QM_EMMC0_DATA1 212 -#define IMX8QM_EMMC0_DATA2 213 -#define IMX8QM_EMMC0_DATA3 214 -#define IMX8QM_EMMC0_DATA4 215 -#define IMX8QM_EMMC0_DATA5 216 -#define IMX8QM_EMMC0_DATA6 217 -#define IMX8QM_EMMC0_DATA7 218 -#define IMX8QM_EMMC0_STROBE 219 -#define IMX8QM_EMMC0_RESET_B 220 -#define IMX8QM_COMP_CTL_GPIO_1V8_3V3_SD1FIX 221 -#define IMX8QM_USDHC1_CLK 222 -#define IMX8QM_USDHC1_CMD 223 -#define IMX8QM_USDHC1_DATA0 224 -#define IMX8QM_USDHC1_DATA1 225 -#define IMX8QM_CTL_NAND_RE_P_N 226 -#define IMX8QM_USDHC1_DATA2 227 -#define IMX8QM_USDHC1_DATA3 228 -#define IMX8QM_CTL_NAND_DQS_P_N 229 -#define IMX8QM_USDHC1_DATA4 230 -#define IMX8QM_USDHC1_DATA5 231 -#define IMX8QM_USDHC1_DATA6 232 -#define IMX8QM_USDHC1_DATA7 233 -#define IMX8QM_USDHC1_STROBE 234 -#define IMX8QM_COMP_CTL_GPIO_1V8_3V3_VSEL2 235 -#define IMX8QM_USDHC2_CLK 236 -#define IMX8QM_USDHC2_CMD 237 -#define IMX8QM_USDHC2_DATA0 238 -#define IMX8QM_USDHC2_DATA1 239 -#define IMX8QM_USDHC2_DATA2 240 -#define IMX8QM_USDHC2_DATA3 241 -#define IMX8QM_COMP_CTL_GPIO_1V8_3V3_VSEL3 242 -#define IMX8QM_ENET0_RGMII_TXC 243 -#define IMX8QM_ENET0_RGMII_TX_CTL 244 -#define IMX8QM_ENET0_RGMII_TXD0 245 -#define IMX8QM_ENET0_RGMII_TXD1 246 -#define IMX8QM_ENET0_RGMII_TXD2 247 -#define IMX8QM_ENET0_RGMII_TXD3 248 -#define IMX8QM_ENET0_RGMII_RXC 249 -#define IMX8QM_ENET0_RGMII_RX_CTL 250 -#define IMX8QM_ENET0_RGMII_RXD0 251 -#define IMX8QM_ENET0_RGMII_RXD1 252 -#define IMX8QM_ENET0_RGMII_RXD2 253 -#define IMX8QM_ENET0_RGMII_RXD3 254 -#define IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB 255 -#define IMX8QM_ENET1_RGMII_TXC 256 -#define IMX8QM_ENET1_RGMII_TX_CTL 257 -#define IMX8QM_ENET1_RGMII_TXD0 258 -#define IMX8QM_ENET1_RGMII_TXD1 259 -#define IMX8QM_ENET1_RGMII_TXD2 260 -#define IMX8QM_ENET1_RGMII_TXD3 261 -#define IMX8QM_ENET1_RGMII_RXC 262 -#define IMX8QM_ENET1_RGMII_RX_CTL 263 -#define IMX8QM_ENET1_RGMII_RXD0 264 -#define IMX8QM_ENET1_RGMII_RXD1 265 -#define IMX8QM_ENET1_RGMII_RXD2 266 -#define IMX8QM_ENET1_RGMII_RXD3 267 -#define IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA 268 - -/* - * format: - */ -#define IMX8QM_SIM0_CLK_DMA_SIM0_CLK IMX8QM_SIM0_CLK 0 -#define IMX8QM_SIM0_CLK_LSIO_GPIO0_IO00 IMX8QM_SIM0_CLK 3 -#define IMX8QM_SIM0_RST_DMA_SIM0_RST IMX8QM_SIM0_RST 0 -#define IMX8QM_SIM0_RST_LSIO_GPIO0_IO01 IMX8QM_SIM0_RST 3 -#define IMX8QM_SIM0_IO_DMA_SIM0_IO IMX8QM_SIM0_IO 0 -#define IMX8QM_SIM0_IO_LSIO_GPIO0_IO02 IMX8QM_SIM0_IO 3 -#define IMX8QM_SIM0_PD_DMA_SIM0_PD IMX8QM_SIM0_PD 0 -#define IMX8QM_SIM0_PD_DMA_I2C3_SCL IMX8QM_SIM0_PD 1 -#define IMX8QM_SIM0_PD_LSIO_GPIO0_IO03 IMX8QM_SIM0_PD 3 -#define IMX8QM_SIM0_POWER_EN_DMA_SIM0_POWER_EN IMX8QM_SIM0_POWER_EN 0 -#define IMX8QM_SIM0_POWER_EN_DMA_I2C3_SDA IMX8QM_SIM0_POWER_EN 1 -#define IMX8QM_SIM0_POWER_EN_LSIO_GPIO0_IO04 IMX8QM_SIM0_POWER_EN 3 -#define IMX8QM_SIM0_GPIO0_00_DMA_SIM0_POWER_EN IMX8QM_SIM0_GPIO0_00 0 -#define IMX8QM_SIM0_GPIO0_00_LSIO_GPIO0_IO05 IMX8QM_SIM0_GPIO0_00 3 -#define IMX8QM_M40_I2C0_SCL_M40_I2C0_SCL IMX8QM_M40_I2C0_SCL 0 -#define IMX8QM_M40_I2C0_SCL_M40_UART0_RX IMX8QM_M40_I2C0_SCL 1 -#define IMX8QM_M40_I2C0_SCL_M40_GPIO0_IO02 IMX8QM_M40_I2C0_SCL 2 -#define IMX8QM_M40_I2C0_SCL_LSIO_GPIO0_IO06 IMX8QM_M40_I2C0_SCL 3 -#define IMX8QM_M40_I2C0_SDA_M40_I2C0_SDA IMX8QM_M40_I2C0_SDA 0 -#define IMX8QM_M40_I2C0_SDA_M40_UART0_TX IMX8QM_M40_I2C0_SDA 1 -#define IMX8QM_M40_I2C0_SDA_M40_GPIO0_IO03 IMX8QM_M40_I2C0_SDA 2 -#define IMX8QM_M40_I2C0_SDA_LSIO_GPIO0_IO07 IMX8QM_M40_I2C0_SDA 3 -#define IMX8QM_M40_GPIO0_00_M40_GPIO0_IO00 IMX8QM_M40_GPIO0_00 0 -#define IMX8QM_M40_GPIO0_00_M40_TPM0_CH0 IMX8QM_M40_GPIO0_00 1 -#define IMX8QM_M40_GPIO0_00_DMA_UART4_RX IMX8QM_M40_GPIO0_00 2 -#define IMX8QM_M40_GPIO0_00_LSIO_GPIO0_IO08 IMX8QM_M40_GPIO0_00 3 -#define IMX8QM_M40_GPIO0_01_M40_GPIO0_IO01 IMX8QM_M40_GPIO0_01 0 -#define IMX8QM_M40_GPIO0_01_M40_TPM0_CH1 IMX8QM_M40_GPIO0_01 1 -#define IMX8QM_M40_GPIO0_01_DMA_UART4_TX IMX8QM_M40_GPIO0_01 2 -#define IMX8QM_M40_GPIO0_01_LSIO_GPIO0_IO09 IMX8QM_M40_GPIO0_01 3 -#define IMX8QM_M41_I2C0_SCL_M41_I2C0_SCL IMX8QM_M41_I2C0_SCL 0 -#define IMX8QM_M41_I2C0_SCL_M41_UART0_RX IMX8QM_M41_I2C0_SCL 1 -#define IMX8QM_M41_I2C0_SCL_M41_GPIO0_IO02 IMX8QM_M41_I2C0_SCL 2 -#define IMX8QM_M41_I2C0_SCL_LSIO_GPIO0_IO10 IMX8QM_M41_I2C0_SCL 3 -#define IMX8QM_M41_I2C0_SDA_M41_I2C0_SDA IMX8QM_M41_I2C0_SDA 0 -#define IMX8QM_M41_I2C0_SDA_M41_UART0_TX IMX8QM_M41_I2C0_SDA 1 -#define IMX8QM_M41_I2C0_SDA_M41_GPIO0_IO03 IMX8QM_M41_I2C0_SDA 2 -#define IMX8QM_M41_I2C0_SDA_LSIO_GPIO0_IO11 IMX8QM_M41_I2C0_SDA 3 -#define IMX8QM_M41_GPIO0_00_M41_GPIO0_IO00 IMX8QM_M41_GPIO0_00 0 -#define IMX8QM_M41_GPIO0_00_M41_TPM0_CH0 IMX8QM_M41_GPIO0_00 1 -#define IMX8QM_M41_GPIO0_00_DMA_UART3_RX IMX8QM_M41_GPIO0_00 2 -#define IMX8QM_M41_GPIO0_00_LSIO_GPIO0_IO12 IMX8QM_M41_GPIO0_00 3 -#define IMX8QM_M41_GPIO0_01_M41_GPIO0_IO01 IMX8QM_M41_GPIO0_01 0 -#define IMX8QM_M41_GPIO0_01_M41_TPM0_CH1 IMX8QM_M41_GPIO0_01 1 -#define IMX8QM_M41_GPIO0_01_DMA_UART3_TX IMX8QM_M41_GPIO0_01 2 -#define IMX8QM_M41_GPIO0_01_LSIO_GPIO0_IO13 IMX8QM_M41_GPIO0_01 3 -#define IMX8QM_GPT0_CLK_LSIO_GPT0_CLK IMX8QM_GPT0_CLK 0 -#define IMX8QM_GPT0_CLK_DMA_I2C1_SCL IMX8QM_GPT0_CLK 1 -#define IMX8QM_GPT0_CLK_LSIO_KPP0_COL4 IMX8QM_GPT0_CLK 2 -#define IMX8QM_GPT0_CLK_LSIO_GPIO0_IO14 IMX8QM_GPT0_CLK 3 -#define IMX8QM_GPT0_CAPTURE_LSIO_GPT0_CAPTURE IMX8QM_GPT0_CAPTURE 0 -#define IMX8QM_GPT0_CAPTURE_DMA_I2C1_SDA IMX8QM_GPT0_CAPTURE 1 -#define IMX8QM_GPT0_CAPTURE_LSIO_KPP0_COL5 IMX8QM_GPT0_CAPTURE 2 -#define IMX8QM_GPT0_CAPTURE_LSIO_GPIO0_IO15 IMX8QM_GPT0_CAPTURE 3 -#define IMX8QM_GPT0_COMPARE_LSIO_GPT0_COMPARE IMX8QM_GPT0_COMPARE 0 -#define IMX8QM_GPT0_COMPARE_LSIO_PWM3_OUT IMX8QM_GPT0_COMPARE 1 -#define IMX8QM_GPT0_COMPARE_LSIO_KPP0_COL6 IMX8QM_GPT0_COMPARE 2 -#define IMX8QM_GPT0_COMPARE_LSIO_GPIO0_IO16 IMX8QM_GPT0_COMPARE 3 -#define IMX8QM_GPT1_CLK_LSIO_GPT1_CLK IMX8QM_GPT1_CLK 0 -#define IMX8QM_GPT1_CLK_DMA_I2C2_SCL IMX8QM_GPT1_CLK 1 -#define IMX8QM_GPT1_CLK_LSIO_KPP0_COL7 IMX8QM_GPT1_CLK 2 -#define IMX8QM_GPT1_CLK_LSIO_GPIO0_IO17 IMX8QM_GPT1_CLK 3 -#define IMX8QM_GPT1_CAPTURE_LSIO_GPT1_CAPTURE IMX8QM_GPT1_CAPTURE 0 -#define IMX8QM_GPT1_CAPTURE_DMA_I2C2_SDA IMX8QM_GPT1_CAPTURE 1 -#define IMX8QM_GPT1_CAPTURE_LSIO_KPP0_ROW4 IMX8QM_GPT1_CAPTURE 2 -#define IMX8QM_GPT1_CAPTURE_LSIO_GPIO0_IO18 IMX8QM_GPT1_CAPTURE 3 -#define IMX8QM_GPT1_COMPARE_LSIO_GPT1_COMPARE IMX8QM_GPT1_COMPARE 0 -#define IMX8QM_GPT1_COMPARE_LSIO_PWM2_OUT IMX8QM_GPT1_COMPARE 1 -#define IMX8QM_GPT1_COMPARE_LSIO_KPP0_ROW5 IMX8QM_GPT1_COMPARE 2 -#define IMX8QM_GPT1_COMPARE_LSIO_GPIO0_IO19 IMX8QM_GPT1_COMPARE 3 -#define IMX8QM_UART0_RX_DMA_UART0_RX IMX8QM_UART0_RX 0 -#define IMX8QM_UART0_RX_SCU_UART0_RX IMX8QM_UART0_RX 1 -#define IMX8QM_UART0_RX_LSIO_GPIO0_IO20 IMX8QM_UART0_RX 3 -#define IMX8QM_UART0_TX_DMA_UART0_TX IMX8QM_UART0_TX 0 -#define IMX8QM_UART0_TX_SCU_UART0_TX IMX8QM_UART0_TX 1 -#define IMX8QM_UART0_TX_LSIO_GPIO0_IO21 IMX8QM_UART0_TX 3 -#define IMX8QM_UART0_RTS_B_DMA_UART0_RTS_B IMX8QM_UART0_RTS_B 0 -#define IMX8QM_UART0_RTS_B_LSIO_PWM0_OUT IMX8QM_UART0_RTS_B 1 -#define IMX8QM_UART0_RTS_B_DMA_UART2_RX IMX8QM_UART0_RTS_B 2 -#define IMX8QM_UART0_RTS_B_LSIO_GPIO0_IO22 IMX8QM_UART0_RTS_B 3 -#define IMX8QM_UART0_CTS_B_DMA_UART0_CTS_B IMX8QM_UART0_CTS_B 0 -#define IMX8QM_UART0_CTS_B_LSIO_PWM1_OUT IMX8QM_UART0_CTS_B 1 -#define IMX8QM_UART0_CTS_B_DMA_UART2_TX IMX8QM_UART0_CTS_B 2 -#define IMX8QM_UART0_CTS_B_LSIO_GPIO0_IO23 IMX8QM_UART0_CTS_B 3 -#define IMX8QM_UART1_TX_DMA_UART1_TX IMX8QM_UART1_TX 0 -#define IMX8QM_UART1_TX_DMA_SPI3_SCK IMX8QM_UART1_TX 1 -#define IMX8QM_UART1_TX_LSIO_GPIO0_IO24 IMX8QM_UART1_TX 3 -#define IMX8QM_UART1_RX_DMA_UART1_RX IMX8QM_UART1_RX 0 -#define IMX8QM_UART1_RX_DMA_SPI3_SDO IMX8QM_UART1_RX 1 -#define IMX8QM_UART1_RX_LSIO_GPIO0_IO25 IMX8QM_UART1_RX 3 -#define IMX8QM_UART1_RTS_B_DMA_UART1_RTS_B IMX8QM_UART1_RTS_B 0 -#define IMX8QM_UART1_RTS_B_DMA_SPI3_SDI IMX8QM_UART1_RTS_B 1 -#define IMX8QM_UART1_RTS_B_DMA_UART1_CTS_B IMX8QM_UART1_RTS_B 2 -#define IMX8QM_UART1_RTS_B_LSIO_GPIO0_IO26 IMX8QM_UART1_RTS_B 3 -#define IMX8QM_UART1_CTS_B_DMA_UART1_CTS_B IMX8QM_UART1_CTS_B 0 -#define IMX8QM_UART1_CTS_B_DMA_SPI3_CS0 IMX8QM_UART1_CTS_B 1 -#define IMX8QM_UART1_CTS_B_DMA_UART1_RTS_B IMX8QM_UART1_CTS_B 2 -#define IMX8QM_UART1_CTS_B_LSIO_GPIO0_IO27 IMX8QM_UART1_CTS_B 3 -#define IMX8QM_SCU_PMIC_MEMC_ON_SCU_GPIO0_IOXX_PMIC_MEMC_ON IMX8QM_SCU_PMIC_MEMC_ON 0 -#define IMX8QM_SCU_WDOG_OUT_SCU_WDOG0_WDOG_OUT IMX8QM_SCU_WDOG_OUT 0 -#define IMX8QM_PMIC_I2C_SDA_SCU_PMIC_I2C_SDA IMX8QM_PMIC_I2C_SDA 0 -#define IMX8QM_PMIC_I2C_SCL_SCU_PMIC_I2C_SCL IMX8QM_PMIC_I2C_SCL 0 -#define IMX8QM_PMIC_EARLY_WARNING_SCU_PMIC_EARLY_WARNING IMX8QM_PMIC_EARLY_WARNING 0 -#define IMX8QM_PMIC_INT_B_SCU_DIMX8QMMIC_INT_B IMX8QM_PMIC_INT_B 0 -#define IMX8QM_SCU_GPIO0_00_SCU_GPIO0_IO00 IMX8QM_SCU_GPIO0_00 0 -#define IMX8QM_SCU_GPIO0_00_SCU_UART0_RX IMX8QM_SCU_GPIO0_00 1 -#define IMX8QM_SCU_GPIO0_00_LSIO_GPIO0_IO28 IMX8QM_SCU_GPIO0_00 3 -#define IMX8QM_SCU_GPIO0_01_SCU_GPIO0_IO01 IMX8QM_SCU_GPIO0_01 0 -#define IMX8QM_SCU_GPIO0_01_SCU_UART0_TX IMX8QM_SCU_GPIO0_01 1 -#define IMX8QM_SCU_GPIO0_01_LSIO_GPIO0_IO29 IMX8QM_SCU_GPIO0_01 3 -#define IMX8QM_SCU_GPIO0_02_SCU_GPIO0_IO02 IMX8QM_SCU_GPIO0_02 0 -#define IMX8QM_SCU_GPIO0_02_SCU_GPIO0_IOXX_PMIC_GPU0_ON IMX8QM_SCU_GPIO0_02 1 -#define IMX8QM_SCU_GPIO0_02_LSIO_GPIO0_IO30 IMX8QM_SCU_GPIO0_02 3 -#define IMX8QM_SCU_GPIO0_03_SCU_GPIO0_IO03 IMX8QM_SCU_GPIO0_03 0 -#define IMX8QM_SCU_GPIO0_03_SCU_GPIO0_IOXX_PMIC_GPU1_ON IMX8QM_SCU_GPIO0_03 1 -#define IMX8QM_SCU_GPIO0_03_LSIO_GPIO0_IO31 IMX8QM_SCU_GPIO0_03 3 -#define IMX8QM_SCU_GPIO0_04_SCU_GPIO0_IO04 IMX8QM_SCU_GPIO0_04 0 -#define IMX8QM_SCU_GPIO0_04_SCU_GPIO0_IOXX_PMIC_A72_ON IMX8QM_SCU_GPIO0_04 1 -#define IMX8QM_SCU_GPIO0_04_LSIO_GPIO1_IO00 IMX8QM_SCU_GPIO0_04 3 -#define IMX8QM_SCU_GPIO0_05_SCU_GPIO0_IO05 IMX8QM_SCU_GPIO0_05 0 -#define IMX8QM_SCU_GPIO0_05_SCU_GPIO0_IOXX_PMIC_A53_ON IMX8QM_SCU_GPIO0_05 1 -#define IMX8QM_SCU_GPIO0_05_LSIO_GPIO1_IO01 IMX8QM_SCU_GPIO0_05 3 -#define IMX8QM_SCU_GPIO0_06_SCU_GPIO0_IO06 IMX8QM_SCU_GPIO0_06 0 -#define IMX8QM_SCU_GPIO0_06_SCU_TPM0_CH0 IMX8QM_SCU_GPIO0_06 1 -#define IMX8QM_SCU_GPIO0_06_LSIO_GPIO1_IO02 IMX8QM_SCU_GPIO0_06 3 -#define IMX8QM_SCU_GPIO0_07_SCU_GPIO0_IO07 IMX8QM_SCU_GPIO0_07 0 -#define IMX8QM_SCU_GPIO0_07_SCU_TPM0_CH1 IMX8QM_SCU_GPIO0_07 1 -#define IMX8QM_SCU_GPIO0_07_SCU_DSC_RTC_CLOCK_OUTPUT_32K IMX8QM_SCU_GPIO0_07 2 -#define IMX8QM_SCU_GPIO0_07_LSIO_GPIO1_IO03 IMX8QM_SCU_GPIO0_07 3 -#define IMX8QM_SCU_BOOT_MODE0_SCU_DSC_BOOT_MODE0 IMX8QM_SCU_BOOT_MODE0 0 -#define IMX8QM_SCU_BOOT_MODE1_SCU_DSC_BOOT_MODE1 IMX8QM_SCU_BOOT_MODE1 0 -#define IMX8QM_SCU_BOOT_MODE2_SCU_DSC_BOOT_MODE2 IMX8QM_SCU_BOOT_MODE2 0 -#define IMX8QM_SCU_BOOT_MODE3_SCU_DSC_BOOT_MODE3 IMX8QM_SCU_BOOT_MODE3 0 -#define IMX8QM_SCU_BOOT_MODE4_SCU_DSC_BOOT_MODE4 IMX8QM_SCU_BOOT_MODE4 0 -#define IMX8QM_SCU_BOOT_MODE4_SCU_PMIC_I2C_SCL IMX8QM_SCU_BOOT_MODE4 1 -#define IMX8QM_SCU_BOOT_MODE5_SCU_DSC_BOOT_MODE5 IMX8QM_SCU_BOOT_MODE5 0 -#define IMX8QM_SCU_BOOT_MODE5_SCU_PMIC_I2C_SDA IMX8QM_SCU_BOOT_MODE5 1 -#define IMX8QM_LVDS0_GPIO00_LVDS0_GPIO0_IO00 IMX8QM_LVDS0_GPIO00 0 -#define IMX8QM_LVDS0_GPIO00_LVDS0_PWM0_OUT IMX8QM_LVDS0_GPIO00 1 -#define IMX8QM_LVDS0_GPIO00_LSIO_GPIO1_IO04 IMX8QM_LVDS0_GPIO00 3 -#define IMX8QM_LVDS0_GPIO01_LVDS0_GPIO0_IO01 IMX8QM_LVDS0_GPIO01 0 -#define IMX8QM_LVDS0_GPIO01_LSIO_GPIO1_IO05 IMX8QM_LVDS0_GPIO01 3 -#define IMX8QM_LVDS0_I2C0_SCL_LVDS0_I2C0_SCL IMX8QM_LVDS0_I2C0_SCL 0 -#define IMX8QM_LVDS0_I2C0_SCL_LVDS0_GPIO0_IO02 IMX8QM_LVDS0_I2C0_SCL 1 -#define IMX8QM_LVDS0_I2C0_SCL_LSIO_GPIO1_IO06 IMX8QM_LVDS0_I2C0_SCL 3 -#define IMX8QM_LVDS0_I2C0_SDA_LVDS0_I2C0_SDA IMX8QM_LVDS0_I2C0_SDA 0 -#define IMX8QM_LVDS0_I2C0_SDA_LVDS0_GPIO0_IO03 IMX8QM_LVDS0_I2C0_SDA 1 -#define IMX8QM_LVDS0_I2C0_SDA_LSIO_GPIO1_IO07 IMX8QM_LVDS0_I2C0_SDA 3 -#define IMX8QM_LVDS0_I2C1_SCL_LVDS0_I2C1_SCL IMX8QM_LVDS0_I2C1_SCL 0 -#define IMX8QM_LVDS0_I2C1_SCL_DMA_UART2_TX IMX8QM_LVDS0_I2C1_SCL 1 -#define IMX8QM_LVDS0_I2C1_SCL_LSIO_GPIO1_IO08 IMX8QM_LVDS0_I2C1_SCL 3 -#define IMX8QM_LVDS0_I2C1_SDA_LVDS0_I2C1_SDA IMX8QM_LVDS0_I2C1_SDA 0 -#define IMX8QM_LVDS0_I2C1_SDA_DMA_UART2_RX IMX8QM_LVDS0_I2C1_SDA 1 -#define IMX8QM_LVDS0_I2C1_SDA_LSIO_GPIO1_IO09 IMX8QM_LVDS0_I2C1_SDA 3 -#define IMX8QM_LVDS1_GPIO00_LVDS1_GPIO0_IO00 IMX8QM_LVDS1_GPIO00 0 -#define IMX8QM_LVDS1_GPIO00_LVDS1_PWM0_OUT IMX8QM_LVDS1_GPIO00 1 -#define IMX8QM_LVDS1_GPIO00_LSIO_GPIO1_IO10 IMX8QM_LVDS1_GPIO00 3 -#define IMX8QM_LVDS1_GPIO01_LVDS1_GPIO0_IO01 IMX8QM_LVDS1_GPIO01 0 -#define IMX8QM_LVDS1_GPIO01_LSIO_GPIO1_IO11 IMX8QM_LVDS1_GPIO01 3 -#define IMX8QM_LVDS1_I2C0_SCL_LVDS1_I2C0_SCL IMX8QM_LVDS1_I2C0_SCL 0 -#define IMX8QM_LVDS1_I2C0_SCL_LVDS1_GPIO0_IO02 IMX8QM_LVDS1_I2C0_SCL 1 -#define IMX8QM_LVDS1_I2C0_SCL_LSIO_GPIO1_IO12 IMX8QM_LVDS1_I2C0_SCL 3 -#define IMX8QM_LVDS1_I2C0_SDA_LVDS1_I2C0_SDA IMX8QM_LVDS1_I2C0_SDA 0 -#define IMX8QM_LVDS1_I2C0_SDA_LVDS1_GPIO0_IO03 IMX8QM_LVDS1_I2C0_SDA 1 -#define IMX8QM_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13 IMX8QM_LVDS1_I2C0_SDA 3 -#define IMX8QM_LVDS1_I2C1_SCL_LVDS1_I2C1_SCL IMX8QM_LVDS1_I2C1_SCL 0 -#define IMX8QM_LVDS1_I2C1_SCL_DMA_UART3_TX IMX8QM_LVDS1_I2C1_SCL 1 -#define IMX8QM_LVDS1_I2C1_SCL_LSIO_GPIO1_IO14 IMX8QM_LVDS1_I2C1_SCL 3 -#define IMX8QM_LVDS1_I2C1_SDA_LVDS1_I2C1_SDA IMX8QM_LVDS1_I2C1_SDA 0 -#define IMX8QM_LVDS1_I2C1_SDA_DMA_UART3_RX IMX8QM_LVDS1_I2C1_SDA 1 -#define IMX8QM_LVDS1_I2C1_SDA_LSIO_GPIO1_IO15 IMX8QM_LVDS1_I2C1_SDA 3 -#define IMX8QM_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL IMX8QM_MIPI_DSI0_I2C0_SCL 0 -#define IMX8QM_MIPI_DSI0_I2C0_SCL_LSIO_GPIO1_IO16 IMX8QM_MIPI_DSI0_I2C0_SCL 3 -#define IMX8QM_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA IMX8QM_MIPI_DSI0_I2C0_SDA 0 -#define IMX8QM_MIPI_DSI0_I2C0_SDA_LSIO_GPIO1_IO17 IMX8QM_MIPI_DSI0_I2C0_SDA 3 -#define IMX8QM_MIPI_DSI0_GPIO0_00_MIPI_DSI0_GPIO0_IO00 IMX8QM_MIPI_DSI0_GPIO0_00 0 -#define IMX8QM_MIPI_DSI0_GPIO0_00_MIPI_DSI0_PWM0_OUT IMX8QM_MIPI_DSI0_GPIO0_00 1 -#define IMX8QM_MIPI_DSI0_GPIO0_00_LSIO_GPIO1_IO18 IMX8QM_MIPI_DSI0_GPIO0_00 3 -#define IMX8QM_MIPI_DSI0_GPIO0_01_MIPI_DSI0_GPIO0_IO01 IMX8QM_MIPI_DSI0_GPIO0_01 0 -#define IMX8QM_MIPI_DSI0_GPIO0_01_LSIO_GPIO1_IO19 IMX8QM_MIPI_DSI0_GPIO0_01 3 -#define IMX8QM_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL IMX8QM_MIPI_DSI1_I2C0_SCL 0 -#define IMX8QM_MIPI_DSI1_I2C0_SCL_LSIO_GPIO1_IO20 IMX8QM_MIPI_DSI1_I2C0_SCL 3 -#define IMX8QM_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA IMX8QM_MIPI_DSI1_I2C0_SDA 0 -#define IMX8QM_MIPI_DSI1_I2C0_SDA_LSIO_GPIO1_IO21 IMX8QM_MIPI_DSI1_I2C0_SDA 3 -#define IMX8QM_MIPI_DSI1_GPIO0_00_MIPI_DSI1_GPIO0_IO00 IMX8QM_MIPI_DSI1_GPIO0_00 0 -#define IMX8QM_MIPI_DSI1_GPIO0_00_MIPI_DSI1_PWM0_OUT IMX8QM_MIPI_DSI1_GPIO0_00 1 -#define IMX8QM_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO22 IMX8QM_MIPI_DSI1_GPIO0_00 3 -#define IMX8QM_MIPI_DSI1_GPIO0_01_MIPI_DSI1_GPIO0_IO01 IMX8QM_MIPI_DSI1_GPIO0_01 0 -#define IMX8QM_MIPI_DSI1_GPIO0_01_LSIO_GPIO1_IO23 IMX8QM_MIPI_DSI1_GPIO0_01 3 -#define IMX8QM_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT IMX8QM_MIPI_CSI0_MCLK_OUT 0 -#define IMX8QM_MIPI_CSI0_MCLK_OUT_LSIO_GPIO1_IO24 IMX8QM_MIPI_CSI0_MCLK_OUT 3 -#define IMX8QM_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL IMX8QM_MIPI_CSI0_I2C0_SCL 0 -#define IMX8QM_MIPI_CSI0_I2C0_SCL_LSIO_GPIO1_IO25 IMX8QM_MIPI_CSI0_I2C0_SCL 3 -#define IMX8QM_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA IMX8QM_MIPI_CSI0_I2C0_SDA 0 -#define IMX8QM_MIPI_CSI0_I2C0_SDA_LSIO_GPIO1_IO26 IMX8QM_MIPI_CSI0_I2C0_SDA 3 -#define IMX8QM_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_IO00 IMX8QM_MIPI_CSI0_GPIO0_00 0 -#define IMX8QM_MIPI_CSI0_GPIO0_00_DMA_I2C0_SCL IMX8QM_MIPI_CSI0_GPIO0_00 1 -#define IMX8QM_MIPI_CSI0_GPIO0_00_MIPI_CSI1_I2C0_SCL IMX8QM_MIPI_CSI0_GPIO0_00 2 -#define IMX8QM_MIPI_CSI0_GPIO0_00_LSIO_GPIO1_IO27 IMX8QM_MIPI_CSI0_GPIO0_00 3 -#define IMX8QM_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_IO01 IMX8QM_MIPI_CSI0_GPIO0_01 0 -#define IMX8QM_MIPI_CSI0_GPIO0_01_DMA_I2C0_SDA IMX8QM_MIPI_CSI0_GPIO0_01 1 -#define IMX8QM_MIPI_CSI0_GPIO0_01_MIPI_CSI1_I2C0_SDA IMX8QM_MIPI_CSI0_GPIO0_01 2 -#define IMX8QM_MIPI_CSI0_GPIO0_01_LSIO_GPIO1_IO28 IMX8QM_MIPI_CSI0_GPIO0_01 3 -#define IMX8QM_MIPI_CSI1_MCLK_OUT_MIPI_CSI1_ACM_MCLK_OUT IMX8QM_MIPI_CSI1_MCLK_OUT 0 -#define IMX8QM_MIPI_CSI1_MCLK_OUT_LSIO_GPIO1_IO29 IMX8QM_MIPI_CSI1_MCLK_OUT 3 -#define IMX8QM_MIPI_CSI1_GPIO0_00_MIPI_CSI1_GPIO0_IO00 IMX8QM_MIPI_CSI1_GPIO0_00 0 -#define IMX8QM_MIPI_CSI1_GPIO0_00_DMA_UART4_RX IMX8QM_MIPI_CSI1_GPIO0_00 1 -#define IMX8QM_MIPI_CSI1_GPIO0_00_LSIO_GPIO1_IO30 IMX8QM_MIPI_CSI1_GPIO0_00 3 -#define IMX8QM_MIPI_CSI1_GPIO0_01_MIPI_CSI1_GPIO0_IO01 IMX8QM_MIPI_CSI1_GPIO0_01 0 -#define IMX8QM_MIPI_CSI1_GPIO0_01_DMA_UART4_TX IMX8QM_MIPI_CSI1_GPIO0_01 1 -#define IMX8QM_MIPI_CSI1_GPIO0_01_LSIO_GPIO1_IO31 IMX8QM_MIPI_CSI1_GPIO0_01 3 -#define IMX8QM_MIPI_CSI1_I2C0_SCL_MIPI_CSI1_I2C0_SCL IMX8QM_MIPI_CSI1_I2C0_SCL 0 -#define IMX8QM_MIPI_CSI1_I2C0_SCL_LSIO_GPIO2_IO00 IMX8QM_MIPI_CSI1_I2C0_SCL 3 -#define IMX8QM_MIPI_CSI1_I2C0_SDA_MIPI_CSI1_I2C0_SDA IMX8QM_MIPI_CSI1_I2C0_SDA 0 -#define IMX8QM_MIPI_CSI1_I2C0_SDA_LSIO_GPIO2_IO01 IMX8QM_MIPI_CSI1_I2C0_SDA 3 -#define IMX8QM_HDMI_TX0_TS_SCL_HDMI_TX0_I2C0_SCL IMX8QM_HDMI_TX0_TS_SCL 0 -#define IMX8QM_HDMI_TX0_TS_SCL_DMA_I2C0_SCL IMX8QM_HDMI_TX0_TS_SCL 1 -#define IMX8QM_HDMI_TX0_TS_SCL_LSIO_GPIO2_IO02 IMX8QM_HDMI_TX0_TS_SCL 3 -#define IMX8QM_HDMI_TX0_TS_SDA_HDMI_TX0_I2C0_SDA IMX8QM_HDMI_TX0_TS_SDA 0 -#define IMX8QM_HDMI_TX0_TS_SDA_DMA_I2C0_SDA IMX8QM_HDMI_TX0_TS_SDA 1 -#define IMX8QM_HDMI_TX0_TS_SDA_LSIO_GPIO2_IO03 IMX8QM_HDMI_TX0_TS_SDA 3 -#define IMX8QM_ESAI1_FSR_AUD_ESAI1_FSR IMX8QM_ESAI1_FSR 0 -#define IMX8QM_ESAI1_FSR_LSIO_GPIO2_IO04 IMX8QM_ESAI1_FSR 3 -#define IMX8QM_ESAI1_FST_AUD_ESAI1_FST IMX8QM_ESAI1_FST 0 -#define IMX8QM_ESAI1_FST_AUD_SPDIF0_EXT_CLK IMX8QM_ESAI1_FST 1 -#define IMX8QM_ESAI1_FST_LSIO_GPIO2_IO05 IMX8QM_ESAI1_FST 3 -#define IMX8QM_ESAI1_SCKR_AUD_ESAI1_SCKR IMX8QM_ESAI1_SCKR 0 -#define IMX8QM_ESAI1_SCKR_LSIO_GPIO2_IO06 IMX8QM_ESAI1_SCKR 3 -#define IMX8QM_ESAI1_SCKT_AUD_ESAI1_SCKT IMX8QM_ESAI1_SCKT 0 -#define IMX8QM_ESAI1_SCKT_AUD_SAI2_RXC IMX8QM_ESAI1_SCKT 1 -#define IMX8QM_ESAI1_SCKT_AUD_SPDIF0_EXT_CLK IMX8QM_ESAI1_SCKT 2 -#define IMX8QM_ESAI1_SCKT_LSIO_GPIO2_IO07 IMX8QM_ESAI1_SCKT 3 -#define IMX8QM_ESAI1_TX0_AUD_ESAI1_TX0 IMX8QM_ESAI1_TX0 0 -#define IMX8QM_ESAI1_TX0_AUD_SAI2_RXD IMX8QM_ESAI1_TX0 1 -#define IMX8QM_ESAI1_TX0_AUD_SPDIF0_RX IMX8QM_ESAI1_TX0 2 -#define IMX8QM_ESAI1_TX0_LSIO_GPIO2_IO08 IMX8QM_ESAI1_TX0 3 -#define IMX8QM_ESAI1_TX1_AUD_ESAI1_TX1 IMX8QM_ESAI1_TX1 0 -#define IMX8QM_ESAI1_TX1_AUD_SAI2_RXFS IMX8QM_ESAI1_TX1 1 -#define IMX8QM_ESAI1_TX1_AUD_SPDIF0_TX IMX8QM_ESAI1_TX1 2 -#define IMX8QM_ESAI1_TX1_LSIO_GPIO2_IO09 IMX8QM_ESAI1_TX1 3 -#define IMX8QM_ESAI1_TX2_RX3_AUD_ESAI1_TX2_RX3 IMX8QM_ESAI1_TX2_RX3 0 -#define IMX8QM_ESAI1_TX2_RX3_AUD_SPDIF0_RX IMX8QM_ESAI1_TX2_RX3 1 -#define IMX8QM_ESAI1_TX2_RX3_LSIO_GPIO2_IO10 IMX8QM_ESAI1_TX2_RX3 3 -#define IMX8QM_ESAI1_TX3_RX2_AUD_ESAI1_TX3_RX2 IMX8QM_ESAI1_TX3_RX2 0 -#define IMX8QM_ESAI1_TX3_RX2_AUD_SPDIF0_TX IMX8QM_ESAI1_TX3_RX2 1 -#define IMX8QM_ESAI1_TX3_RX2_LSIO_GPIO2_IO11 IMX8QM_ESAI1_TX3_RX2 3 -#define IMX8QM_ESAI1_TX4_RX1_AUD_ESAI1_TX4_RX1 IMX8QM_ESAI1_TX4_RX1 0 -#define IMX8QM_ESAI1_TX4_RX1_LSIO_GPIO2_IO12 IMX8QM_ESAI1_TX4_RX1 3 -#define IMX8QM_ESAI1_TX5_RX0_AUD_ESAI1_TX5_RX0 IMX8QM_ESAI1_TX5_RX0 0 -#define IMX8QM_ESAI1_TX5_RX0_LSIO_GPIO2_IO13 IMX8QM_ESAI1_TX5_RX0 3 -#define IMX8QM_SPDIF0_RX_AUD_SPDIF0_RX IMX8QM_SPDIF0_RX 0 -#define IMX8QM_SPDIF0_RX_AUD_MQS_R IMX8QM_SPDIF0_RX 1 -#define IMX8QM_SPDIF0_RX_AUD_ACM_MCLK_IN1 IMX8QM_SPDIF0_RX 2 -#define IMX8QM_SPDIF0_RX_LSIO_GPIO2_IO14 IMX8QM_SPDIF0_RX 3 -#define IMX8QM_SPDIF0_TX_AUD_SPDIF0_TX IMX8QM_SPDIF0_TX 0 -#define IMX8QM_SPDIF0_TX_AUD_MQS_L IMX8QM_SPDIF0_TX 1 -#define IMX8QM_SPDIF0_TX_AUD_ACM_MCLK_OUT1 IMX8QM_SPDIF0_TX 2 -#define IMX8QM_SPDIF0_TX_LSIO_GPIO2_IO15 IMX8QM_SPDIF0_TX 3 -#define IMX8QM_SPDIF0_EXT_CLK_AUD_SPDIF0_EXT_CLK IMX8QM_SPDIF0_EXT_CLK 0 -#define IMX8QM_SPDIF0_EXT_CLK_DMA_DMA0_REQ_IN0 IMX8QM_SPDIF0_EXT_CLK 1 -#define IMX8QM_SPDIF0_EXT_CLK_LSIO_GPIO2_IO16 IMX8QM_SPDIF0_EXT_CLK 3 -#define IMX8QM_SPI3_SCK_DMA_SPI3_SCK IMX8QM_SPI3_SCK 0 -#define IMX8QM_SPI3_SCK_LSIO_GPIO2_IO17 IMX8QM_SPI3_SCK 3 -#define IMX8QM_SPI3_SDO_DMA_SPI3_SDO IMX8QM_SPI3_SDO 0 -#define IMX8QM_SPI3_SDO_DMA_FTM_CH0 IMX8QM_SPI3_SDO 1 -#define IMX8QM_SPI3_SDO_LSIO_GPIO2_IO18 IMX8QM_SPI3_SDO 3 -#define IMX8QM_SPI3_SDI_DMA_SPI3_SDI IMX8QM_SPI3_SDI 0 -#define IMX8QM_SPI3_SDI_DMA_FTM_CH1 IMX8QM_SPI3_SDI 1 -#define IMX8QM_SPI3_SDI_LSIO_GPIO2_IO19 IMX8QM_SPI3_SDI 3 -#define IMX8QM_SPI3_CS0_DMA_SPI3_CS0 IMX8QM_SPI3_CS0 0 -#define IMX8QM_SPI3_CS0_DMA_FTM_CH2 IMX8QM_SPI3_CS0 1 -#define IMX8QM_SPI3_CS0_LSIO_GPIO2_IO20 IMX8QM_SPI3_CS0 3 -#define IMX8QM_SPI3_CS1_DMA_SPI3_CS1 IMX8QM_SPI3_CS1 0 -#define IMX8QM_SPI3_CS1_LSIO_GPIO2_IO21 IMX8QM_SPI3_CS1 3 -#define IMX8QM_ESAI0_FSR_AUD_ESAI0_FSR IMX8QM_ESAI0_FSR 0 -#define IMX8QM_ESAI0_FSR_LSIO_GPIO2_IO22 IMX8QM_ESAI0_FSR 3 -#define IMX8QM_ESAI0_FST_AUD_ESAI0_FST IMX8QM_ESAI0_FST 0 -#define IMX8QM_ESAI0_FST_LSIO_GPIO2_IO23 IMX8QM_ESAI0_FST 3 -#define IMX8QM_ESAI0_SCKR_AUD_ESAI0_SCKR IMX8QM_ESAI0_SCKR 0 -#define IMX8QM_ESAI0_SCKR_LSIO_GPIO2_IO24 IMX8QM_ESAI0_SCKR 3 -#define IMX8QM_ESAI0_SCKT_AUD_ESAI0_SCKT IMX8QM_ESAI0_SCKT 0 -#define IMX8QM_ESAI0_SCKT_LSIO_GPIO2_IO25 IMX8QM_ESAI0_SCKT 3 -#define IMX8QM_ESAI0_TX0_AUD_ESAI0_TX0 IMX8QM_ESAI0_TX0 0 -#define IMX8QM_ESAI0_TX0_LSIO_GPIO2_IO26 IMX8QM_ESAI0_TX0 3 -#define IMX8QM_ESAI0_TX1_AUD_ESAI0_TX1 IMX8QM_ESAI0_TX1 0 -#define IMX8QM_ESAI0_TX1_LSIO_GPIO2_IO27 IMX8QM_ESAI0_TX1 3 -#define IMX8QM_ESAI0_TX2_RX3_AUD_ESAI0_TX2_RX3 IMX8QM_ESAI0_TX2_RX3 0 -#define IMX8QM_ESAI0_TX2_RX3_LSIO_GPIO2_IO28 IMX8QM_ESAI0_TX2_RX3 3 -#define IMX8QM_ESAI0_TX3_RX2_AUD_ESAI0_TX3_RX2 IMX8QM_ESAI0_TX3_RX2 0 -#define IMX8QM_ESAI0_TX3_RX2_LSIO_GPIO2_IO29 IMX8QM_ESAI0_TX3_RX2 3 -#define IMX8QM_ESAI0_TX4_RX1_AUD_ESAI0_TX4_RX1 IMX8QM_ESAI0_TX4_RX1 0 -#define IMX8QM_ESAI0_TX4_RX1_LSIO_GPIO2_IO30 IMX8QM_ESAI0_TX4_RX1 3 -#define IMX8QM_ESAI0_TX5_RX0_AUD_ESAI0_TX5_RX0 IMX8QM_ESAI0_TX5_RX0 0 -#define IMX8QM_ESAI0_TX5_RX0_LSIO_GPIO2_IO31 IMX8QM_ESAI0_TX5_RX0 3 -#define IMX8QM_MCLK_IN0_AUD_ACM_MCLK_IN0 IMX8QM_MCLK_IN0 0 -#define IMX8QM_MCLK_IN0_AUD_ESAI0_RX_HF_CLK IMX8QM_MCLK_IN0 1 -#define IMX8QM_MCLK_IN0_AUD_ESAI1_RX_HF_CLK IMX8QM_MCLK_IN0 2 -#define IMX8QM_MCLK_IN0_LSIO_GPIO3_IO00 IMX8QM_MCLK_IN0 3 -#define IMX8QM_MCLK_OUT0_AUD_ACM_MCLK_OUT0 IMX8QM_MCLK_OUT0 0 -#define IMX8QM_MCLK_OUT0_AUD_ESAI0_TX_HF_CLK IMX8QM_MCLK_OUT0 1 -#define IMX8QM_MCLK_OUT0_AUD_ESAI1_TX_HF_CLK IMX8QM_MCLK_OUT0 2 -#define IMX8QM_MCLK_OUT0_LSIO_GPIO3_IO01 IMX8QM_MCLK_OUT0 3 -#define IMX8QM_SPI0_SCK_DMA_SPI0_SCK IMX8QM_SPI0_SCK 0 -#define IMX8QM_SPI0_SCK_AUD_SAI0_RXC IMX8QM_SPI0_SCK 1 -#define IMX8QM_SPI0_SCK_LSIO_GPIO3_IO02 IMX8QM_SPI0_SCK 3 -#define IMX8QM_SPI0_SDO_DMA_SPI0_SDO IMX8QM_SPI0_SDO 0 -#define IMX8QM_SPI0_SDO_AUD_SAI0_TXD IMX8QM_SPI0_SDO 1 -#define IMX8QM_SPI0_SDO_LSIO_GPIO3_IO03 IMX8QM_SPI0_SDO 3 -#define IMX8QM_SPI0_SDI_DMA_SPI0_SDI IMX8QM_SPI0_SDI 0 -#define IMX8QM_SPI0_SDI_AUD_SAI0_RXD IMX8QM_SPI0_SDI 1 -#define IMX8QM_SPI0_SDI_LSIO_GPIO3_IO04 IMX8QM_SPI0_SDI 3 -#define IMX8QM_SPI0_CS0_DMA_SPI0_CS0 IMX8QM_SPI0_CS0 0 -#define IMX8QM_SPI0_CS0_AUD_SAI0_RXFS IMX8QM_SPI0_CS0 1 -#define IMX8QM_SPI0_CS0_LSIO_GPIO3_IO05 IMX8QM_SPI0_CS0 3 -#define IMX8QM_SPI0_CS1_DMA_SPI0_CS1 IMX8QM_SPI0_CS1 0 -#define IMX8QM_SPI0_CS1_AUD_SAI0_TXC IMX8QM_SPI0_CS1 1 -#define IMX8QM_SPI0_CS1_LSIO_GPIO3_IO06 IMX8QM_SPI0_CS1 3 -#define IMX8QM_SPI2_SCK_DMA_SPI2_SCK IMX8QM_SPI2_SCK 0 -#define IMX8QM_SPI2_SCK_LSIO_GPIO3_IO07 IMX8QM_SPI2_SCK 3 -#define IMX8QM_SPI2_SDO_DMA_SPI2_SDO IMX8QM_SPI2_SDO 0 -#define IMX8QM_SPI2_SDO_LSIO_GPIO3_IO08 IMX8QM_SPI2_SDO 3 -#define IMX8QM_SPI2_SDI_DMA_SPI2_SDI IMX8QM_SPI2_SDI 0 -#define IMX8QM_SPI2_SDI_LSIO_GPIO3_IO09 IMX8QM_SPI2_SDI 3 -#define IMX8QM_SPI2_CS0_DMA_SPI2_CS0 IMX8QM_SPI2_CS0 0 -#define IMX8QM_SPI2_CS0_LSIO_GPIO3_IO10 IMX8QM_SPI2_CS0 3 -#define IMX8QM_SPI2_CS1_DMA_SPI2_CS1 IMX8QM_SPI2_CS1 0 -#define IMX8QM_SPI2_CS1_AUD_SAI0_TXFS IMX8QM_SPI2_CS1 1 -#define IMX8QM_SPI2_CS1_LSIO_GPIO3_IO11 IMX8QM_SPI2_CS1 3 -#define IMX8QM_SAI1_RXC_AUD_SAI1_RXC IMX8QM_SAI1_RXC 0 -#define IMX8QM_SAI1_RXC_AUD_SAI0_TXD IMX8QM_SAI1_RXC 1 -#define IMX8QM_SAI1_RXC_LSIO_GPIO3_IO12 IMX8QM_SAI1_RXC 3 -#define IMX8QM_SAI1_RXD_AUD_SAI1_RXD IMX8QM_SAI1_RXD 0 -#define IMX8QM_SAI1_RXD_AUD_SAI0_TXFS IMX8QM_SAI1_RXD 1 -#define IMX8QM_SAI1_RXD_LSIO_GPIO3_IO13 IMX8QM_SAI1_RXD 3 -#define IMX8QM_SAI1_RXFS_AUD_SAI1_RXFS IMX8QM_SAI1_RXFS 0 -#define IMX8QM_SAI1_RXFS_AUD_SAI0_RXD IMX8QM_SAI1_RXFS 1 -#define IMX8QM_SAI1_RXFS_LSIO_GPIO3_IO14 IMX8QM_SAI1_RXFS 3 -#define IMX8QM_SAI1_TXC_AUD_SAI1_TXC IMX8QM_SAI1_TXC 0 -#define IMX8QM_SAI1_TXC_AUD_SAI0_TXC IMX8QM_SAI1_TXC 1 -#define IMX8QM_SAI1_TXC_LSIO_GPIO3_IO15 IMX8QM_SAI1_TXC 3 -#define IMX8QM_SAI1_TXD_AUD_SAI1_TXD IMX8QM_SAI1_TXD 0 -#define IMX8QM_SAI1_TXD_AUD_SAI1_RXC IMX8QM_SAI1_TXD 1 -#define IMX8QM_SAI1_TXD_LSIO_GPIO3_IO16 IMX8QM_SAI1_TXD 3 -#define IMX8QM_SAI1_TXFS_AUD_SAI1_TXFS IMX8QM_SAI1_TXFS 0 -#define IMX8QM_SAI1_TXFS_AUD_SAI1_RXFS IMX8QM_SAI1_TXFS 1 -#define IMX8QM_SAI1_TXFS_LSIO_GPIO3_IO17 IMX8QM_SAI1_TXFS 3 -#define IMX8QM_ADC_IN7_DMA_ADC1_IN3 IMX8QM_ADC_IN7 0 -#define IMX8QM_ADC_IN7_DMA_SPI1_CS1 IMX8QM_ADC_IN7 1 -#define IMX8QM_ADC_IN7_LSIO_KPP0_ROW3 IMX8QM_ADC_IN7 2 -#define IMX8QM_ADC_IN7_LSIO_GPIO3_IO25 IMX8QM_ADC_IN7 3 -#define IMX8QM_ADC_IN6_DMA_ADC1_IN2 IMX8QM_ADC_IN6 0 -#define IMX8QM_ADC_IN6_DMA_SPI1_CS0 IMX8QM_ADC_IN6 1 -#define IMX8QM_ADC_IN6_LSIO_KPP0_ROW2 IMX8QM_ADC_IN6 2 -#define IMX8QM_ADC_IN6_LSIO_GPIO3_IO24 IMX8QM_ADC_IN6 3 -#define IMX8QM_ADC_IN5_DMA_ADC1_IN1 IMX8QM_ADC_IN5 0 -#define IMX8QM_ADC_IN5_DMA_SPI1_SDI IMX8QM_ADC_IN5 1 -#define IMX8QM_ADC_IN5_LSIO_KPP0_ROW1 IMX8QM_ADC_IN5 2 -#define IMX8QM_ADC_IN5_LSIO_GPIO3_IO23 IMX8QM_ADC_IN5 3 -#define IMX8QM_ADC_IN4_DMA_ADC1_IN0 IMX8QM_ADC_IN4 0 -#define IMX8QM_ADC_IN4_DMA_SPI1_SDO IMX8QM_ADC_IN4 1 -#define IMX8QM_ADC_IN4_LSIO_KPP0_ROW0 IMX8QM_ADC_IN4 2 -#define IMX8QM_ADC_IN4_LSIO_GPIO3_IO22 IMX8QM_ADC_IN4 3 -#define IMX8QM_ADC_IN3_DMA_ADC0_IN3 IMX8QM_ADC_IN3 0 -#define IMX8QM_ADC_IN3_DMA_SPI1_SCK IMX8QM_ADC_IN3 1 -#define IMX8QM_ADC_IN3_LSIO_KPP0_COL3 IMX8QM_ADC_IN3 2 -#define IMX8QM_ADC_IN3_LSIO_GPIO3_IO21 IMX8QM_ADC_IN3 3 -#define IMX8QM_ADC_IN2_DMA_ADC0_IN2 IMX8QM_ADC_IN2 0 -#define IMX8QM_ADC_IN2_LSIO_KPP0_COL2 IMX8QM_ADC_IN2 2 -#define IMX8QM_ADC_IN2_LSIO_GPIO3_IO20 IMX8QM_ADC_IN2 3 -#define IMX8QM_ADC_IN1_DMA_ADC0_IN1 IMX8QM_ADC_IN1 0 -#define IMX8QM_ADC_IN1_LSIO_KPP0_COL1 IMX8QM_ADC_IN1 2 -#define IMX8QM_ADC_IN1_LSIO_GPIO3_IO19 IMX8QM_ADC_IN1 3 -#define IMX8QM_ADC_IN0_DMA_ADC0_IN0 IMX8QM_ADC_IN0 0 -#define IMX8QM_ADC_IN0_LSIO_KPP0_COL0 IMX8QM_ADC_IN0 2 -#define IMX8QM_ADC_IN0_LSIO_GPIO3_IO18 IMX8QM_ADC_IN0 3 -#define IMX8QM_MLB_SIG_CONN_MLB_SIG IMX8QM_MLB_SIG 0 -#define IMX8QM_MLB_SIG_AUD_SAI3_RXC IMX8QM_MLB_SIG 1 -#define IMX8QM_MLB_SIG_LSIO_GPIO3_IO26 IMX8QM_MLB_SIG 3 -#define IMX8QM_MLB_CLK_CONN_MLB_CLK IMX8QM_MLB_CLK 0 -#define IMX8QM_MLB_CLK_AUD_SAI3_RXFS IMX8QM_MLB_CLK 1 -#define IMX8QM_MLB_CLK_LSIO_GPIO3_IO27 IMX8QM_MLB_CLK 3 -#define IMX8QM_MLB_DATA_CONN_MLB_DATA IMX8QM_MLB_DATA 0 -#define IMX8QM_MLB_DATA_AUD_SAI3_RXD IMX8QM_MLB_DATA 1 -#define IMX8QM_MLB_DATA_LSIO_GPIO3_IO28 IMX8QM_MLB_DATA 3 -#define IMX8QM_FLEXCAN0_RX_DMA_FLEXCAN0_RX IMX8QM_FLEXCAN0_RX 0 -#define IMX8QM_FLEXCAN0_RX_LSIO_GPIO3_IO29 IMX8QM_FLEXCAN0_RX 3 -#define IMX8QM_FLEXCAN0_TX_DMA_FLEXCAN0_TX IMX8QM_FLEXCAN0_TX 0 -#define IMX8QM_FLEXCAN0_TX_LSIO_GPIO3_IO30 IMX8QM_FLEXCAN0_TX 3 -#define IMX8QM_FLEXCAN1_RX_DMA_FLEXCAN1_RX IMX8QM_FLEXCAN1_RX 0 -#define IMX8QM_FLEXCAN1_RX_LSIO_GPIO3_IO31 IMX8QM_FLEXCAN1_RX 3 -#define IMX8QM_FLEXCAN1_TX_DMA_FLEXCAN1_TX IMX8QM_FLEXCAN1_TX 0 -#define IMX8QM_FLEXCAN1_TX_LSIO_GPIO4_IO00 IMX8QM_FLEXCAN1_TX 3 -#define IMX8QM_FLEXCAN2_RX_DMA_FLEXCAN2_RX IMX8QM_FLEXCAN2_RX 0 -#define IMX8QM_FLEXCAN2_RX_LSIO_GPIO4_IO01 IMX8QM_FLEXCAN2_RX 3 -#define IMX8QM_FLEXCAN2_TX_DMA_FLEXCAN2_TX IMX8QM_FLEXCAN2_TX 0 -#define IMX8QM_FLEXCAN2_TX_LSIO_GPIO4_IO02 IMX8QM_FLEXCAN2_TX 3 -#define IMX8QM_USB_SS3_TC0_DMA_I2C1_SCL IMX8QM_USB_SS3_TC0 0 -#define IMX8QM_USB_SS3_TC0_CONN_USB_OTG1_PWR IMX8QM_USB_SS3_TC0 1 -#define IMX8QM_USB_SS3_TC0_LSIO_GPIO4_IO03 IMX8QM_USB_SS3_TC0 3 -#define IMX8QM_USB_SS3_TC1_DMA_I2C1_SCL IMX8QM_USB_SS3_TC1 0 -#define IMX8QM_USB_SS3_TC1_CONN_USB_OTG2_PWR IMX8QM_USB_SS3_TC1 1 -#define IMX8QM_USB_SS3_TC1_LSIO_GPIO4_IO04 IMX8QM_USB_SS3_TC1 3 -#define IMX8QM_USB_SS3_TC2_DMA_I2C1_SDA IMX8QM_USB_SS3_TC2 0 -#define IMX8QM_USB_SS3_TC2_CONN_USB_OTG1_OC IMX8QM_USB_SS3_TC2 1 -#define IMX8QM_USB_SS3_TC2_LSIO_GPIO4_IO05 IMX8QM_USB_SS3_TC2 3 -#define IMX8QM_USB_SS3_TC3_DMA_I2C1_SDA IMX8QM_USB_SS3_TC3 0 -#define IMX8QM_USB_SS3_TC3_CONN_USB_OTG2_OC IMX8QM_USB_SS3_TC3 1 -#define IMX8QM_USB_SS3_TC3_LSIO_GPIO4_IO06 IMX8QM_USB_SS3_TC3 3 -#define IMX8QM_USDHC1_RESET_B_CONN_USDHC1_RESET_B IMX8QM_USDHC1_RESET_B 0 -#define IMX8QM_USDHC1_RESET_B_LSIO_GPIO4_IO07 IMX8QM_USDHC1_RESET_B 3 -#define IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT IMX8QM_USDHC1_VSELECT 0 -#define IMX8QM_USDHC1_VSELECT_LSIO_GPIO4_IO08 IMX8QM_USDHC1_VSELECT 3 -#define IMX8QM_USDHC2_RESET_B_CONN_USDHC2_RESET_B IMX8QM_USDHC2_RESET_B 0 -#define IMX8QM_USDHC2_RESET_B_LSIO_GPIO4_IO09 IMX8QM_USDHC2_RESET_B 3 -#define IMX8QM_USDHC2_VSELECT_CONN_USDHC2_VSELECT IMX8QM_USDHC2_VSELECT 0 -#define IMX8QM_USDHC2_VSELECT_LSIO_GPIO4_IO10 IMX8QM_USDHC2_VSELECT 3 -#define IMX8QM_USDHC2_WP_CONN_USDHC2_WP IMX8QM_USDHC2_WP 0 -#define IMX8QM_USDHC2_WP_LSIO_GPIO4_IO11 IMX8QM_USDHC2_WP 3 -#define IMX8QM_USDHC2_CD_B_CONN_USDHC2_CD_B IMX8QM_USDHC2_CD_B 0 -#define IMX8QM_USDHC2_CD_B_LSIO_GPIO4_IO12 IMX8QM_USDHC2_CD_B 3 -#define IMX8QM_ENET0_MDIO_CONN_ENET0_MDIO IMX8QM_ENET0_MDIO 0 -#define IMX8QM_ENET0_MDIO_DMA_I2C4_SDA IMX8QM_ENET0_MDIO 1 -#define IMX8QM_ENET0_MDIO_LSIO_GPIO4_IO13 IMX8QM_ENET0_MDIO 3 -#define IMX8QM_ENET0_MDC_CONN_ENET0_MDC IMX8QM_ENET0_MDC 0 -#define IMX8QM_ENET0_MDC_DMA_I2C4_SCL IMX8QM_ENET0_MDC 1 -#define IMX8QM_ENET0_MDC_LSIO_GPIO4_IO14 IMX8QM_ENET0_MDC 3 -#define IMX8QM_ENET0_REFCLK_125M_25M_CONN_ENET0_REFCLK_125M_25M IMX8QM_ENET0_REFCLK_125M_25M 0 -#define IMX8QM_ENET0_REFCLK_125M_25M_CONN_ENET0_PPS IMX8QM_ENET0_REFCLK_125M_25M 1 -#define IMX8QM_ENET0_REFCLK_125M_25M_LSIO_GPIO4_IO15 IMX8QM_ENET0_REFCLK_125M_25M 3 -#define IMX8QM_ENET1_REFCLK_125M_25M_CONN_ENET1_REFCLK_125M_25M IMX8QM_ENET1_REFCLK_125M_25M 0 -#define IMX8QM_ENET1_REFCLK_125M_25M_CONN_ENET1_PPS IMX8QM_ENET1_REFCLK_125M_25M 1 -#define IMX8QM_ENET1_REFCLK_125M_25M_LSIO_GPIO4_IO16 IMX8QM_ENET1_REFCLK_125M_25M 3 -#define IMX8QM_ENET1_MDIO_CONN_ENET1_MDIO IMX8QM_ENET1_MDIO 0 -#define IMX8QM_ENET1_MDIO_DMA_I2C4_SDA IMX8QM_ENET1_MDIO 1 -#define IMX8QM_ENET1_MDIO_LSIO_GPIO4_IO17 IMX8QM_ENET1_MDIO 3 -#define IMX8QM_ENET1_MDC_CONN_ENET1_MDC IMX8QM_ENET1_MDC 0 -#define IMX8QM_ENET1_MDC_DMA_I2C4_SCL IMX8QM_ENET1_MDC 1 -#define IMX8QM_ENET1_MDC_LSIO_GPIO4_IO18 IMX8QM_ENET1_MDC 3 -#define IMX8QM_QSPI1A_SS0_B_LSIO_QSPI1A_SS0_B IMX8QM_QSPI1A_SS0_B 0 -#define IMX8QM_QSPI1A_SS0_B_LSIO_GPIO4_IO19 IMX8QM_QSPI1A_SS0_B 3 -#define IMX8QM_QSPI1A_SS1_B_LSIO_QSPI1A_SS1_B IMX8QM_QSPI1A_SS1_B 0 -#define IMX8QM_QSPI1A_SS1_B_LSIO_QSPI1A_SCLK2 IMX8QM_QSPI1A_SS1_B 1 -#define IMX8QM_QSPI1A_SS1_B_LSIO_GPIO4_IO20 IMX8QM_QSPI1A_SS1_B 3 -#define IMX8QM_QSPI1A_SCLK_LSIO_QSPI1A_SCLK IMX8QM_QSPI1A_SCLK 0 -#define IMX8QM_QSPI1A_SCLK_LSIO_GPIO4_IO21 IMX8QM_QSPI1A_SCLK 3 -#define IMX8QM_QSPI1A_DQS_LSIO_QSPI1A_DQS IMX8QM_QSPI1A_DQS 0 -#define IMX8QM_QSPI1A_DQS_LSIO_GPIO4_IO22 IMX8QM_QSPI1A_DQS 3 -#define IMX8QM_QSPI1A_DATA3_LSIO_QSPI1A_DATA3 IMX8QM_QSPI1A_DATA3 0 -#define IMX8QM_QSPI1A_DATA3_DMA_I2C1_SDA IMX8QM_QSPI1A_DATA3 1 -#define IMX8QM_QSPI1A_DATA3_CONN_USB_OTG1_OC IMX8QM_QSPI1A_DATA3 2 -#define IMX8QM_QSPI1A_DATA3_LSIO_GPIO4_IO23 IMX8QM_QSPI1A_DATA3 3 -#define IMX8QM_QSPI1A_DATA2_LSIO_QSPI1A_DATA2 IMX8QM_QSPI1A_DATA2 0 -#define IMX8QM_QSPI1A_DATA2_DMA_I2C1_SCL IMX8QM_QSPI1A_DATA2 1 -#define IMX8QM_QSPI1A_DATA2_CONN_USB_OTG2_PWR IMX8QM_QSPI1A_DATA2 2 -#define IMX8QM_QSPI1A_DATA2_LSIO_GPIO4_IO24 IMX8QM_QSPI1A_DATA2 3 -#define IMX8QM_QSPI1A_DATA1_LSIO_QSPI1A_DATA1 IMX8QM_QSPI1A_DATA1 0 -#define IMX8QM_QSPI1A_DATA1_DMA_I2C1_SDA IMX8QM_QSPI1A_DATA1 1 -#define IMX8QM_QSPI1A_DATA1_CONN_USB_OTG2_OC IMX8QM_QSPI1A_DATA1 2 -#define IMX8QM_QSPI1A_DATA1_LSIO_GPIO4_IO25 IMX8QM_QSPI1A_DATA1 3 -#define IMX8QM_QSPI1A_DATA0_LSIO_QSPI1A_DATA0 IMX8QM_QSPI1A_DATA0 0 -#define IMX8QM_QSPI1A_DATA0_LSIO_GPIO4_IO26 IMX8QM_QSPI1A_DATA0 3 -#define IMX8QM_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 IMX8QM_QSPI0A_DATA0 0 -#define IMX8QM_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 IMX8QM_QSPI0A_DATA1 0 -#define IMX8QM_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 IMX8QM_QSPI0A_DATA2 0 -#define IMX8QM_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 IMX8QM_QSPI0A_DATA3 0 -#define IMX8QM_QSPI0A_DQS_LSIO_QSPI0A_DQS IMX8QM_QSPI0A_DQS 0 -#define IMX8QM_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B IMX8QM_QSPI0A_SS0_B 0 -#define IMX8QM_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B IMX8QM_QSPI0A_SS1_B 0 -#define IMX8QM_QSPI0A_SS1_B_LSIO_QSPI0A_SCLK2 IMX8QM_QSPI0A_SS1_B 1 -#define IMX8QM_QSPI0A_SCLK_LSIO_QSPI0A_SCLK IMX8QM_QSPI0A_SCLK 0 -#define IMX8QM_QSPI0B_SCLK_LSIO_QSPI0B_SCLK IMX8QM_QSPI0B_SCLK 0 -#define IMX8QM_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 IMX8QM_QSPI0B_DATA0 0 -#define IMX8QM_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 IMX8QM_QSPI0B_DATA1 0 -#define IMX8QM_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 IMX8QM_QSPI0B_DATA2 0 -#define IMX8QM_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 IMX8QM_QSPI0B_DATA3 0 -#define IMX8QM_QSPI0B_DQS_LSIO_QSPI0B_DQS IMX8QM_QSPI0B_DQS 0 -#define IMX8QM_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B IMX8QM_QSPI0B_SS0_B 0 -#define IMX8QM_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B IMX8QM_QSPI0B_SS1_B 0 -#define IMX8QM_QSPI0B_SS1_B_LSIO_QSPI0B_SCLK2 IMX8QM_QSPI0B_SS1_B 1 -#define IMX8QM_PCIE_CTRL0_CLKREQ_B_HSIO_PCIE0_CLKREQ_B IMX8QM_PCIE_CTRL0_CLKREQ_B 0 -#define IMX8QM_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO27 IMX8QM_PCIE_CTRL0_CLKREQ_B 3 -#define IMX8QM_PCIE_CTRL0_WAKE_B_HSIO_PCIE0_WAKE_B IMX8QM_PCIE_CTRL0_WAKE_B 0 -#define IMX8QM_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO28 IMX8QM_PCIE_CTRL0_WAKE_B 3 -#define IMX8QM_PCIE_CTRL0_PERST_B_HSIO_PCIE0_PERST_B IMX8QM_PCIE_CTRL0_PERST_B 0 -#define IMX8QM_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29 IMX8QM_PCIE_CTRL0_PERST_B 3 -#define IMX8QM_PCIE_CTRL1_CLKREQ_B_HSIO_PCIE1_CLKREQ_B IMX8QM_PCIE_CTRL1_CLKREQ_B 0 -#define IMX8QM_PCIE_CTRL1_CLKREQ_B_DMA_I2C1_SDA IMX8QM_PCIE_CTRL1_CLKREQ_B 1 -#define IMX8QM_PCIE_CTRL1_CLKREQ_B_CONN_USB_OTG2_OC IMX8QM_PCIE_CTRL1_CLKREQ_B 2 -#define IMX8QM_PCIE_CTRL1_CLKREQ_B_LSIO_GPIO4_IO30 IMX8QM_PCIE_CTRL1_CLKREQ_B 3 -#define IMX8QM_PCIE_CTRL1_WAKE_B_HSIO_PCIE1_WAKE_B IMX8QM_PCIE_CTRL1_WAKE_B 0 -#define IMX8QM_PCIE_CTRL1_WAKE_B_DMA_I2C1_SCL IMX8QM_PCIE_CTRL1_WAKE_B 1 -#define IMX8QM_PCIE_CTRL1_WAKE_B_CONN_USB_OTG2_PWR IMX8QM_PCIE_CTRL1_WAKE_B 2 -#define IMX8QM_PCIE_CTRL1_WAKE_B_LSIO_GPIO4_IO31 IMX8QM_PCIE_CTRL1_WAKE_B 3 -#define IMX8QM_PCIE_CTRL1_PERST_B_HSIO_PCIE1_PERST_B IMX8QM_PCIE_CTRL1_PERST_B 0 -#define IMX8QM_PCIE_CTRL1_PERST_B_DMA_I2C1_SCL IMX8QM_PCIE_CTRL1_PERST_B 1 -#define IMX8QM_PCIE_CTRL1_PERST_B_CONN_USB_OTG1_PWR IMX8QM_PCIE_CTRL1_PERST_B 2 -#define IMX8QM_PCIE_CTRL1_PERST_B_LSIO_GPIO5_IO00 IMX8QM_PCIE_CTRL1_PERST_B 3 -#define IMX8QM_USB_HSIC0_DATA_CONN_USB_HSIC0_DATA IMX8QM_USB_HSIC0_DATA 0 -#define IMX8QM_USB_HSIC0_DATA_DMA_I2C1_SDA IMX8QM_USB_HSIC0_DATA 1 -#define IMX8QM_USB_HSIC0_DATA_LSIO_GPIO5_IO01 IMX8QM_USB_HSIC0_DATA 3 -#define IMX8QM_USB_HSIC0_STROBE_CONN_USB_HSIC0_STROBE IMX8QM_USB_HSIC0_STROBE 0 -#define IMX8QM_USB_HSIC0_STROBE_DMA_I2C1_SCL IMX8QM_USB_HSIC0_STROBE 1 -#define IMX8QM_USB_HSIC0_STROBE_LSIO_GPIO5_IO02 IMX8QM_USB_HSIC0_STROBE 3 -#define IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK IMX8QM_EMMC0_CLK 0 -#define IMX8QM_EMMC0_CLK_CONN_NAND_READY_B IMX8QM_EMMC0_CLK 1 -#define IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD IMX8QM_EMMC0_CMD 0 -#define IMX8QM_EMMC0_CMD_CONN_NAND_DQS IMX8QM_EMMC0_CMD 1 -#define IMX8QM_EMMC0_CMD_AUD_MQS_R IMX8QM_EMMC0_CMD 2 -#define IMX8QM_EMMC0_CMD_LSIO_GPIO5_IO03 IMX8QM_EMMC0_CMD 3 -#define IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 IMX8QM_EMMC0_DATA0 0 -#define IMX8QM_EMMC0_DATA0_CONN_NAND_DATA00 IMX8QM_EMMC0_DATA0 1 -#define IMX8QM_EMMC0_DATA0_LSIO_GPIO5_IO04 IMX8QM_EMMC0_DATA0 3 -#define IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 IMX8QM_EMMC0_DATA1 0 -#define IMX8QM_EMMC0_DATA1_CONN_NAND_DATA01 IMX8QM_EMMC0_DATA1 1 -#define IMX8QM_EMMC0_DATA1_LSIO_GPIO5_IO05 IMX8QM_EMMC0_DATA1 3 -#define IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 IMX8QM_EMMC0_DATA2 0 -#define IMX8QM_EMMC0_DATA2_CONN_NAND_DATA02 IMX8QM_EMMC0_DATA2 1 -#define IMX8QM_EMMC0_DATA2_LSIO_GPIO5_IO06 IMX8QM_EMMC0_DATA2 3 -#define IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 IMX8QM_EMMC0_DATA3 0 -#define IMX8QM_EMMC0_DATA3_CONN_NAND_DATA03 IMX8QM_EMMC0_DATA3 1 -#define IMX8QM_EMMC0_DATA3_LSIO_GPIO5_IO07 IMX8QM_EMMC0_DATA3 3 -#define IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 IMX8QM_EMMC0_DATA4 0 -#define IMX8QM_EMMC0_DATA4_CONN_NAND_DATA04 IMX8QM_EMMC0_DATA4 1 -#define IMX8QM_EMMC0_DATA4_LSIO_GPIO5_IO08 IMX8QM_EMMC0_DATA4 3 -#define IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 IMX8QM_EMMC0_DATA5 0 -#define IMX8QM_EMMC0_DATA5_CONN_NAND_DATA05 IMX8QM_EMMC0_DATA5 1 -#define IMX8QM_EMMC0_DATA5_LSIO_GPIO5_IO09 IMX8QM_EMMC0_DATA5 3 -#define IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 IMX8QM_EMMC0_DATA6 0 -#define IMX8QM_EMMC0_DATA6_CONN_NAND_DATA06 IMX8QM_EMMC0_DATA6 1 -#define IMX8QM_EMMC0_DATA6_LSIO_GPIO5_IO10 IMX8QM_EMMC0_DATA6 3 -#define IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 IMX8QM_EMMC0_DATA7 0 -#define IMX8QM_EMMC0_DATA7_CONN_NAND_DATA07 IMX8QM_EMMC0_DATA7 1 -#define IMX8QM_EMMC0_DATA7_LSIO_GPIO5_IO11 IMX8QM_EMMC0_DATA7 3 -#define IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE IMX8QM_EMMC0_STROBE 0 -#define IMX8QM_EMMC0_STROBE_CONN_NAND_CLE IMX8QM_EMMC0_STROBE 1 -#define IMX8QM_EMMC0_STROBE_LSIO_GPIO5_IO12 IMX8QM_EMMC0_STROBE 3 -#define IMX8QM_EMMC0_RESET_B_CONN_EMMC0_RESET_B IMX8QM_EMMC0_RESET_B 0 -#define IMX8QM_EMMC0_RESET_B_CONN_NAND_WP_B IMX8QM_EMMC0_RESET_B 1 -#define IMX8QM_EMMC0_RESET_B_CONN_USDHC1_VSELECT IMX8QM_EMMC0_RESET_B 2 -#define IMX8QM_EMMC0_RESET_B_LSIO_GPIO5_IO13 IMX8QM_EMMC0_RESET_B 3 -#define IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK IMX8QM_USDHC1_CLK 0 -#define IMX8QM_USDHC1_CLK_AUD_MQS_R IMX8QM_USDHC1_CLK 1 -#define IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD IMX8QM_USDHC1_CMD 0 -#define IMX8QM_USDHC1_CMD_AUD_MQS_L IMX8QM_USDHC1_CMD 1 -#define IMX8QM_USDHC1_CMD_LSIO_GPIO5_IO14 IMX8QM_USDHC1_CMD 3 -#define IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 IMX8QM_USDHC1_DATA0 0 -#define IMX8QM_USDHC1_DATA0_CONN_NAND_RE_N IMX8QM_USDHC1_DATA0 1 -#define IMX8QM_USDHC1_DATA0_LSIO_GPIO5_IO15 IMX8QM_USDHC1_DATA0 3 -#define IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 IMX8QM_USDHC1_DATA1 0 -#define IMX8QM_USDHC1_DATA1_CONN_NAND_RE_P IMX8QM_USDHC1_DATA1 1 -#define IMX8QM_USDHC1_DATA1_LSIO_GPIO5_IO16 IMX8QM_USDHC1_DATA1 3 -#define IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 IMX8QM_USDHC1_DATA2 0 -#define IMX8QM_USDHC1_DATA2_CONN_NAND_DQS_N IMX8QM_USDHC1_DATA2 1 -#define IMX8QM_USDHC1_DATA2_LSIO_GPIO5_IO17 IMX8QM_USDHC1_DATA2 3 -#define IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 IMX8QM_USDHC1_DATA3 0 -#define IMX8QM_USDHC1_DATA3_CONN_NAND_DQS_P IMX8QM_USDHC1_DATA3 1 -#define IMX8QM_USDHC1_DATA3_LSIO_GPIO5_IO18 IMX8QM_USDHC1_DATA3 3 -#define IMX8QM_USDHC1_DATA4_CONN_USDHC1_DATA4 IMX8QM_USDHC1_DATA4 0 -#define IMX8QM_USDHC1_DATA4_CONN_NAND_CE0_B IMX8QM_USDHC1_DATA4 1 -#define IMX8QM_USDHC1_DATA4_AUD_MQS_R IMX8QM_USDHC1_DATA4 2 -#define IMX8QM_USDHC1_DATA4_LSIO_GPIO5_IO19 IMX8QM_USDHC1_DATA4 3 -#define IMX8QM_USDHC1_DATA5_CONN_USDHC1_DATA5 IMX8QM_USDHC1_DATA5 0 -#define IMX8QM_USDHC1_DATA5_CONN_NAND_RE_B IMX8QM_USDHC1_DATA5 1 -#define IMX8QM_USDHC1_DATA5_AUD_MQS_L IMX8QM_USDHC1_DATA5 2 -#define IMX8QM_USDHC1_DATA5_LSIO_GPIO5_IO20 IMX8QM_USDHC1_DATA5 3 -#define IMX8QM_USDHC1_DATA6_CONN_USDHC1_DATA6 IMX8QM_USDHC1_DATA6 0 -#define IMX8QM_USDHC1_DATA6_CONN_NAND_WE_B IMX8QM_USDHC1_DATA6 1 -#define IMX8QM_USDHC1_DATA6_CONN_USDHC1_WP IMX8QM_USDHC1_DATA6 2 -#define IMX8QM_USDHC1_DATA6_LSIO_GPIO5_IO21 IMX8QM_USDHC1_DATA6 3 -#define IMX8QM_USDHC1_DATA7_CONN_USDHC1_DATA7 IMX8QM_USDHC1_DATA7 0 -#define IMX8QM_USDHC1_DATA7_CONN_NAND_ALE IMX8QM_USDHC1_DATA7 1 -#define IMX8QM_USDHC1_DATA7_CONN_USDHC1_CD_B IMX8QM_USDHC1_DATA7 2 -#define IMX8QM_USDHC1_DATA7_LSIO_GPIO5_IO22 IMX8QM_USDHC1_DATA7 3 -#define IMX8QM_USDHC1_STROBE_CONN_USDHC1_STROBE IMX8QM_USDHC1_STROBE 0 -#define IMX8QM_USDHC1_STROBE_CONN_NAND_CE1_B IMX8QM_USDHC1_STROBE 1 -#define IMX8QM_USDHC1_STROBE_CONN_USDHC1_RESET_B IMX8QM_USDHC1_STROBE 2 -#define IMX8QM_USDHC1_STROBE_LSIO_GPIO5_IO23 IMX8QM_USDHC1_STROBE 3 -#define IMX8QM_USDHC2_CLK_CONN_USDHC2_CLK IMX8QM_USDHC2_CLK 0 -#define IMX8QM_USDHC2_CLK_AUD_MQS_R IMX8QM_USDHC2_CLK 1 -#define IMX8QM_USDHC2_CLK_LSIO_GPIO5_IO24 IMX8QM_USDHC2_CLK 3 -#define IMX8QM_USDHC2_CMD_CONN_USDHC2_CMD IMX8QM_USDHC2_CMD 0 -#define IMX8QM_USDHC2_CMD_AUD_MQS_L IMX8QM_USDHC2_CMD 1 -#define IMX8QM_USDHC2_CMD_LSIO_GPIO5_IO25 IMX8QM_USDHC2_CMD 3 -#define IMX8QM_USDHC2_DATA0_CONN_USDHC2_DATA0 IMX8QM_USDHC2_DATA0 0 -#define IMX8QM_USDHC2_DATA0_DMA_UART4_RX IMX8QM_USDHC2_DATA0 1 -#define IMX8QM_USDHC2_DATA0_LSIO_GPIO5_IO26 IMX8QM_USDHC2_DATA0 3 -#define IMX8QM_USDHC2_DATA1_CONN_USDHC2_DATA1 IMX8QM_USDHC2_DATA1 0 -#define IMX8QM_USDHC2_DATA1_DMA_UART4_TX IMX8QM_USDHC2_DATA1 1 -#define IMX8QM_USDHC2_DATA1_LSIO_GPIO5_IO27 IMX8QM_USDHC2_DATA1 3 -#define IMX8QM_USDHC2_DATA2_CONN_USDHC2_DATA2 IMX8QM_USDHC2_DATA2 0 -#define IMX8QM_USDHC2_DATA2_DMA_UART4_CTS_B IMX8QM_USDHC2_DATA2 1 -#define IMX8QM_USDHC2_DATA2_LSIO_GPIO5_IO28 IMX8QM_USDHC2_DATA2 3 -#define IMX8QM_USDHC2_DATA3_CONN_USDHC2_DATA3 IMX8QM_USDHC2_DATA3 0 -#define IMX8QM_USDHC2_DATA3_DMA_UART4_RTS_B IMX8QM_USDHC2_DATA3 1 -#define IMX8QM_USDHC2_DATA3_LSIO_GPIO5_IO29 IMX8QM_USDHC2_DATA3 3 -#define IMX8QM_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC IMX8QM_ENET0_RGMII_TXC 0 -#define IMX8QM_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT IMX8QM_ENET0_RGMII_TXC 1 -#define IMX8QM_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_IN IMX8QM_ENET0_RGMII_TXC 2 -#define IMX8QM_ENET0_RGMII_TXC_LSIO_GPIO5_IO30 IMX8QM_ENET0_RGMII_TXC 3 -#define IMX8QM_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL IMX8QM_ENET0_RGMII_TX_CTL 0 -#define IMX8QM_ENET0_RGMII_TX_CTL_LSIO_GPIO5_IO31 IMX8QM_ENET0_RGMII_TX_CTL 3 -#define IMX8QM_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 IMX8QM_ENET0_RGMII_TXD0 0 -#define IMX8QM_ENET0_RGMII_TXD0_LSIO_GPIO6_IO00 IMX8QM_ENET0_RGMII_TXD0 3 -#define IMX8QM_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 IMX8QM_ENET0_RGMII_TXD1 0 -#define IMX8QM_ENET0_RGMII_TXD1_LSIO_GPIO6_IO01 IMX8QM_ENET0_RGMII_TXD1 3 -#define IMX8QM_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 IMX8QM_ENET0_RGMII_TXD2 0 -#define IMX8QM_ENET0_RGMII_TXD2_DMA_UART3_TX IMX8QM_ENET0_RGMII_TXD2 1 -#define IMX8QM_ENET0_RGMII_TXD2_VPU_TSI_S1_VID IMX8QM_ENET0_RGMII_TXD2 2 -#define IMX8QM_ENET0_RGMII_TXD2_LSIO_GPIO6_IO02 IMX8QM_ENET0_RGMII_TXD2 3 -#define IMX8QM_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 IMX8QM_ENET0_RGMII_TXD3 0 -#define IMX8QM_ENET0_RGMII_TXD3_DMA_UART3_RTS_B IMX8QM_ENET0_RGMII_TXD3 1 -#define IMX8QM_ENET0_RGMII_TXD3_VPU_TSI_S1_SYNC IMX8QM_ENET0_RGMII_TXD3 2 -#define IMX8QM_ENET0_RGMII_TXD3_LSIO_GPIO6_IO03 IMX8QM_ENET0_RGMII_TXD3 3 -#define IMX8QM_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC IMX8QM_ENET0_RGMII_RXC 0 -#define IMX8QM_ENET0_RGMII_RXC_DMA_UART3_CTS_B IMX8QM_ENET0_RGMII_RXC 1 -#define IMX8QM_ENET0_RGMII_RXC_VPU_TSI_S1_DATA IMX8QM_ENET0_RGMII_RXC 2 -#define IMX8QM_ENET0_RGMII_RXC_LSIO_GPIO6_IO04 IMX8QM_ENET0_RGMII_RXC 3 -#define IMX8QM_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL IMX8QM_ENET0_RGMII_RX_CTL 0 -#define IMX8QM_ENET0_RGMII_RX_CTL_VPU_TSI_S0_VID IMX8QM_ENET0_RGMII_RX_CTL 2 -#define IMX8QM_ENET0_RGMII_RX_CTL_LSIO_GPIO6_IO05 IMX8QM_ENET0_RGMII_RX_CTL 3 -#define IMX8QM_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 IMX8QM_ENET0_RGMII_RXD0 0 -#define IMX8QM_ENET0_RGMII_RXD0_VPU_TSI_S0_SYNC IMX8QM_ENET0_RGMII_RXD0 2 -#define IMX8QM_ENET0_RGMII_RXD0_LSIO_GPIO6_IO06 IMX8QM_ENET0_RGMII_RXD0 3 -#define IMX8QM_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 IMX8QM_ENET0_RGMII_RXD1 0 -#define IMX8QM_ENET0_RGMII_RXD1_VPU_TSI_S0_DATA IMX8QM_ENET0_RGMII_RXD1 2 -#define IMX8QM_ENET0_RGMII_RXD1_LSIO_GPIO6_IO07 IMX8QM_ENET0_RGMII_RXD1 3 -#define IMX8QM_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 IMX8QM_ENET0_RGMII_RXD2 0 -#define IMX8QM_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER IMX8QM_ENET0_RGMII_RXD2 1 -#define IMX8QM_ENET0_RGMII_RXD2_VPU_TSI_S0_CLK IMX8QM_ENET0_RGMII_RXD2 2 -#define IMX8QM_ENET0_RGMII_RXD2_LSIO_GPIO6_IO08 IMX8QM_ENET0_RGMII_RXD2 3 -#define IMX8QM_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 IMX8QM_ENET0_RGMII_RXD3 0 -#define IMX8QM_ENET0_RGMII_RXD3_DMA_UART3_RX IMX8QM_ENET0_RGMII_RXD3 1 -#define IMX8QM_ENET0_RGMII_RXD3_VPU_TSI_S1_CLK IMX8QM_ENET0_RGMII_RXD3 2 -#define IMX8QM_ENET0_RGMII_RXD3_LSIO_GPIO6_IO09 IMX8QM_ENET0_RGMII_RXD3 3 -#define IMX8QM_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC IMX8QM_ENET1_RGMII_TXC 0 -#define IMX8QM_ENET1_RGMII_TXC_CONN_ENET1_RCLK50M_OUT IMX8QM_ENET1_RGMII_TXC 1 -#define IMX8QM_ENET1_RGMII_TXC_CONN_ENET1_RCLK50M_IN IMX8QM_ENET1_RGMII_TXC 2 -#define IMX8QM_ENET1_RGMII_TXC_LSIO_GPIO6_IO10 IMX8QM_ENET1_RGMII_TXC 3 -#define IMX8QM_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL IMX8QM_ENET1_RGMII_TX_CTL 0 -#define IMX8QM_ENET1_RGMII_TX_CTL_LSIO_GPIO6_IO11 IMX8QM_ENET1_RGMII_TX_CTL 3 -#define IMX8QM_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 IMX8QM_ENET1_RGMII_TXD0 0 -#define IMX8QM_ENET1_RGMII_TXD0_LSIO_GPIO6_IO12 IMX8QM_ENET1_RGMII_TXD0 3 -#define IMX8QM_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 IMX8QM_ENET1_RGMII_TXD1 0 -#define IMX8QM_ENET1_RGMII_TXD1_LSIO_GPIO6_IO13 IMX8QM_ENET1_RGMII_TXD1 3 -#define IMX8QM_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2 IMX8QM_ENET1_RGMII_TXD2 0 -#define IMX8QM_ENET1_RGMII_TXD2_DMA_UART3_TX IMX8QM_ENET1_RGMII_TXD2 1 -#define IMX8QM_ENET1_RGMII_TXD2_VPU_TSI_S1_VID IMX8QM_ENET1_RGMII_TXD2 2 -#define IMX8QM_ENET1_RGMII_TXD2_LSIO_GPIO6_IO14 IMX8QM_ENET1_RGMII_TXD2 3 -#define IMX8QM_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3 IMX8QM_ENET1_RGMII_TXD3 0 -#define IMX8QM_ENET1_RGMII_TXD3_DMA_UART3_RTS_B IMX8QM_ENET1_RGMII_TXD3 1 -#define IMX8QM_ENET1_RGMII_TXD3_VPU_TSI_S1_SYNC IMX8QM_ENET1_RGMII_TXD3 2 -#define IMX8QM_ENET1_RGMII_TXD3_LSIO_GPIO6_IO15 IMX8QM_ENET1_RGMII_TXD3 3 -#define IMX8QM_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC IMX8QM_ENET1_RGMII_RXC 0 -#define IMX8QM_ENET1_RGMII_RXC_DMA_UART3_CTS_B IMX8QM_ENET1_RGMII_RXC 1 -#define IMX8QM_ENET1_RGMII_RXC_VPU_TSI_S1_DATA IMX8QM_ENET1_RGMII_RXC 2 -#define IMX8QM_ENET1_RGMII_RXC_LSIO_GPIO6_IO16 IMX8QM_ENET1_RGMII_RXC 3 -#define IMX8QM_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL IMX8QM_ENET1_RGMII_RX_CTL 0 -#define IMX8QM_ENET1_RGMII_RX_CTL_VPU_TSI_S0_VID IMX8QM_ENET1_RGMII_RX_CTL 2 -#define IMX8QM_ENET1_RGMII_RX_CTL_LSIO_GPIO6_IO17 IMX8QM_ENET1_RGMII_RX_CTL 3 -#define IMX8QM_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 IMX8QM_ENET1_RGMII_RXD0 0 -#define IMX8QM_ENET1_RGMII_RXD0_VPU_TSI_S0_SYNC IMX8QM_ENET1_RGMII_RXD0 2 -#define IMX8QM_ENET1_RGMII_RXD0_LSIO_GPIO6_IO18 IMX8QM_ENET1_RGMII_RXD0 3 -#define IMX8QM_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 IMX8QM_ENET1_RGMII_RXD1 0 -#define IMX8QM_ENET1_RGMII_RXD1_VPU_TSI_S0_DATA IMX8QM_ENET1_RGMII_RXD1 2 -#define IMX8QM_ENET1_RGMII_RXD1_LSIO_GPIO6_IO19 IMX8QM_ENET1_RGMII_RXD1 3 -#define IMX8QM_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2 IMX8QM_ENET1_RGMII_RXD2 0 -#define IMX8QM_ENET1_RGMII_RXD2_CONN_ENET1_RMII_RX_ER IMX8QM_ENET1_RGMII_RXD2 1 -#define IMX8QM_ENET1_RGMII_RXD2_VPU_TSI_S0_CLK IMX8QM_ENET1_RGMII_RXD2 2 -#define IMX8QM_ENET1_RGMII_RXD2_LSIO_GPIO6_IO20 IMX8QM_ENET1_RGMII_RXD2 3 -#define IMX8QM_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3 IMX8QM_ENET1_RGMII_RXD3 0 -#define IMX8QM_ENET1_RGMII_RXD3_DMA_UART3_RX IMX8QM_ENET1_RGMII_RXD3 1 -#define IMX8QM_ENET1_RGMII_RXD3_VPU_TSI_S1_CLK IMX8QM_ENET1_RGMII_RXD3 2 -#define IMX8QM_ENET1_RGMII_RXD3_LSIO_GPIO6_IO21 IMX8QM_ENET1_RGMII_RXD3 3 -#define IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB 0 -#define IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA 0 - -#endif /* _IMX8QM_PADS_H */ diff --git a/sys/gnu/dts/include/dt-bindings/pinctrl/pads-imx8qxp.h b/sys/gnu/dts/include/dt-bindings/pinctrl/pads-imx8qxp.h deleted file mode 100644 index fbfee7ecf84..00000000000 --- a/sys/gnu/dts/include/dt-bindings/pinctrl/pads-imx8qxp.h +++ /dev/null @@ -1,751 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2016 Freescale Semiconductor, Inc. - * Copyright 2017~2018 NXP - */ - -#ifndef _IMX8QXP_PADS_H -#define _IMX8QXP_PADS_H - -/* pin id */ -#define IMX8QXP_PCIE_CTRL0_PERST_B 0 -#define IMX8QXP_PCIE_CTRL0_CLKREQ_B 1 -#define IMX8QXP_PCIE_CTRL0_WAKE_B 2 -#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_PCIESEP 3 -#define IMX8QXP_USB_SS3_TC0 4 -#define IMX8QXP_USB_SS3_TC1 5 -#define IMX8QXP_USB_SS3_TC2 6 -#define IMX8QXP_USB_SS3_TC3 7 -#define IMX8QXP_COMP_CTL_GPIO_3V3_USB3IO 8 -#define IMX8QXP_EMMC0_CLK 9 -#define IMX8QXP_EMMC0_CMD 10 -#define IMX8QXP_EMMC0_DATA0 11 -#define IMX8QXP_EMMC0_DATA1 12 -#define IMX8QXP_EMMC0_DATA2 13 -#define IMX8QXP_EMMC0_DATA3 14 -#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_SD1FIX0 15 -#define IMX8QXP_EMMC0_DATA4 16 -#define IMX8QXP_EMMC0_DATA5 17 -#define IMX8QXP_EMMC0_DATA6 18 -#define IMX8QXP_EMMC0_DATA7 19 -#define IMX8QXP_EMMC0_STROBE 20 -#define IMX8QXP_EMMC0_RESET_B 21 -#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_SD1FIX1 22 -#define IMX8QXP_USDHC1_RESET_B 23 -#define IMX8QXP_USDHC1_VSELECT 24 -#define IMX8QXP_CTL_NAND_RE_P_N 25 -#define IMX8QXP_USDHC1_WP 26 -#define IMX8QXP_USDHC1_CD_B 27 -#define IMX8QXP_CTL_NAND_DQS_P_N 28 -#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_VSELSEP 29 -#define IMX8QXP_USDHC1_CLK 30 -#define IMX8QXP_USDHC1_CMD 31 -#define IMX8QXP_USDHC1_DATA0 32 -#define IMX8QXP_USDHC1_DATA1 33 -#define IMX8QXP_USDHC1_DATA2 34 -#define IMX8QXP_USDHC1_DATA3 35 -#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_VSEL3 36 -#define IMX8QXP_ENET0_RGMII_TXC 37 -#define IMX8QXP_ENET0_RGMII_TX_CTL 38 -#define IMX8QXP_ENET0_RGMII_TXD0 39 -#define IMX8QXP_ENET0_RGMII_TXD1 40 -#define IMX8QXP_ENET0_RGMII_TXD2 41 -#define IMX8QXP_ENET0_RGMII_TXD3 42 -#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0 43 -#define IMX8QXP_ENET0_RGMII_RXC 44 -#define IMX8QXP_ENET0_RGMII_RX_CTL 45 -#define IMX8QXP_ENET0_RGMII_RXD0 46 -#define IMX8QXP_ENET0_RGMII_RXD1 47 -#define IMX8QXP_ENET0_RGMII_RXD2 48 -#define IMX8QXP_ENET0_RGMII_RXD3 49 -#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1 50 -#define IMX8QXP_ENET0_REFCLK_125M_25M 51 -#define IMX8QXP_ENET0_MDIO 52 -#define IMX8QXP_ENET0_MDC 53 -#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIOCT 54 -#define IMX8QXP_ESAI0_FSR 55 -#define IMX8QXP_ESAI0_FST 56 -#define IMX8QXP_ESAI0_SCKR 57 -#define IMX8QXP_ESAI0_SCKT 58 -#define IMX8QXP_ESAI0_TX0 59 -#define IMX8QXP_ESAI0_TX1 60 -#define IMX8QXP_ESAI0_TX2_RX3 61 -#define IMX8QXP_ESAI0_TX3_RX2 62 -#define IMX8QXP_ESAI0_TX4_RX1 63 -#define IMX8QXP_ESAI0_TX5_RX0 64 -#define IMX8QXP_SPDIF0_RX 65 -#define IMX8QXP_SPDIF0_TX 66 -#define IMX8QXP_SPDIF0_EXT_CLK 67 -#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHB 68 -#define IMX8QXP_SPI3_SCK 69 -#define IMX8QXP_SPI3_SDO 70 -#define IMX8QXP_SPI3_SDI 71 -#define IMX8QXP_SPI3_CS0 72 -#define IMX8QXP_SPI3_CS1 73 -#define IMX8QXP_MCLK_IN1 74 -#define IMX8QXP_MCLK_IN0 75 -#define IMX8QXP_MCLK_OUT0 76 -#define IMX8QXP_UART1_TX 77 -#define IMX8QXP_UART1_RX 78 -#define IMX8QXP_UART1_RTS_B 79 -#define IMX8QXP_UART1_CTS_B 80 -#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHK 81 -#define IMX8QXP_SAI0_TXD 82 -#define IMX8QXP_SAI0_TXC 83 -#define IMX8QXP_SAI0_RXD 84 -#define IMX8QXP_SAI0_TXFS 85 -#define IMX8QXP_SAI1_RXD 86 -#define IMX8QXP_SAI1_RXC 87 -#define IMX8QXP_SAI1_RXFS 88 -#define IMX8QXP_SPI2_CS0 89 -#define IMX8QXP_SPI2_SDO 90 -#define IMX8QXP_SPI2_SDI 91 -#define IMX8QXP_SPI2_SCK 92 -#define IMX8QXP_SPI0_SCK 93 -#define IMX8QXP_SPI0_SDI 94 -#define IMX8QXP_SPI0_SDO 95 -#define IMX8QXP_SPI0_CS1 96 -#define IMX8QXP_SPI0_CS0 97 -#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHT 98 -#define IMX8QXP_ADC_IN1 99 -#define IMX8QXP_ADC_IN0 100 -#define IMX8QXP_ADC_IN3 101 -#define IMX8QXP_ADC_IN2 102 -#define IMX8QXP_ADC_IN5 103 -#define IMX8QXP_ADC_IN4 104 -#define IMX8QXP_FLEXCAN0_RX 105 -#define IMX8QXP_FLEXCAN0_TX 106 -#define IMX8QXP_FLEXCAN1_RX 107 -#define IMX8QXP_FLEXCAN1_TX 108 -#define IMX8QXP_FLEXCAN2_RX 109 -#define IMX8QXP_FLEXCAN2_TX 110 -#define IMX8QXP_UART0_RX 111 -#define IMX8QXP_UART0_TX 112 -#define IMX8QXP_UART2_TX 113 -#define IMX8QXP_UART2_RX 114 -#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIOLH 115 -#define IMX8QXP_MIPI_DSI0_I2C0_SCL 116 -#define IMX8QXP_MIPI_DSI0_I2C0_SDA 117 -#define IMX8QXP_MIPI_DSI0_GPIO0_00 118 -#define IMX8QXP_MIPI_DSI0_GPIO0_01 119 -#define IMX8QXP_MIPI_DSI1_I2C0_SCL 120 -#define IMX8QXP_MIPI_DSI1_I2C0_SDA 121 -#define IMX8QXP_MIPI_DSI1_GPIO0_00 122 -#define IMX8QXP_MIPI_DSI1_GPIO0_01 123 -#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO 124 -#define IMX8QXP_JTAG_TRST_B 125 -#define IMX8QXP_PMIC_I2C_SCL 126 -#define IMX8QXP_PMIC_I2C_SDA 127 -#define IMX8QXP_PMIC_INT_B 128 -#define IMX8QXP_SCU_GPIO0_00 129 -#define IMX8QXP_SCU_GPIO0_01 130 -#define IMX8QXP_SCU_PMIC_STANDBY 131 -#define IMX8QXP_SCU_BOOT_MODE0 132 -#define IMX8QXP_SCU_BOOT_MODE1 133 -#define IMX8QXP_SCU_BOOT_MODE2 134 -#define IMX8QXP_SCU_BOOT_MODE3 135 -#define IMX8QXP_CSI_D00 136 -#define IMX8QXP_CSI_D01 137 -#define IMX8QXP_CSI_D02 138 -#define IMX8QXP_CSI_D03 139 -#define IMX8QXP_CSI_D04 140 -#define IMX8QXP_CSI_D05 141 -#define IMX8QXP_CSI_D06 142 -#define IMX8QXP_CSI_D07 143 -#define IMX8QXP_CSI_HSYNC 144 -#define IMX8QXP_CSI_VSYNC 145 -#define IMX8QXP_CSI_PCLK 146 -#define IMX8QXP_CSI_MCLK 147 -#define IMX8QXP_CSI_EN 148 -#define IMX8QXP_CSI_RESET 149 -#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHD 150 -#define IMX8QXP_MIPI_CSI0_MCLK_OUT 151 -#define IMX8QXP_MIPI_CSI0_I2C0_SCL 152 -#define IMX8QXP_MIPI_CSI0_I2C0_SDA 153 -#define IMX8QXP_MIPI_CSI0_GPIO0_01 154 -#define IMX8QXP_MIPI_CSI0_GPIO0_00 155 -#define IMX8QXP_QSPI0A_DATA0 156 -#define IMX8QXP_QSPI0A_DATA1 157 -#define IMX8QXP_QSPI0A_DATA2 158 -#define IMX8QXP_QSPI0A_DATA3 159 -#define IMX8QXP_QSPI0A_DQS 160 -#define IMX8QXP_QSPI0A_SS0_B 161 -#define IMX8QXP_QSPI0A_SS1_B 162 -#define IMX8QXP_QSPI0A_SCLK 163 -#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_QSPI0A 164 -#define IMX8QXP_QSPI0B_SCLK 165 -#define IMX8QXP_QSPI0B_DATA0 166 -#define IMX8QXP_QSPI0B_DATA1 167 -#define IMX8QXP_QSPI0B_DATA2 168 -#define IMX8QXP_QSPI0B_DATA3 169 -#define IMX8QXP_QSPI0B_DQS 170 -#define IMX8QXP_QSPI0B_SS0_B 171 -#define IMX8QXP_QSPI0B_SS1_B 172 -#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_QSPI0B 173 - -/* - * format: - */ -#define IMX8QXP_PCIE_CTRL0_PERST_B_HSIO_PCIE0_PERST_B IMX8QXP_PCIE_CTRL0_PERST_B 0 -#define IMX8QXP_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 IMX8QXP_PCIE_CTRL0_PERST_B 4 -#define IMX8QXP_PCIE_CTRL0_CLKREQ_B_HSIO_PCIE0_CLKREQ_B IMX8QXP_PCIE_CTRL0_CLKREQ_B 0 -#define IMX8QXP_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 IMX8QXP_PCIE_CTRL0_CLKREQ_B 4 -#define IMX8QXP_PCIE_CTRL0_WAKE_B_HSIO_PCIE0_WAKE_B IMX8QXP_PCIE_CTRL0_WAKE_B 0 -#define IMX8QXP_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 IMX8QXP_PCIE_CTRL0_WAKE_B 4 -#define IMX8QXP_USB_SS3_TC0_ADMA_I2C1_SCL IMX8QXP_USB_SS3_TC0 0 -#define IMX8QXP_USB_SS3_TC0_CONN_USB_OTG1_PWR IMX8QXP_USB_SS3_TC0 1 -#define IMX8QXP_USB_SS3_TC0_CONN_USB_OTG2_PWR IMX8QXP_USB_SS3_TC0 2 -#define IMX8QXP_USB_SS3_TC0_LSIO_GPIO4_IO03 IMX8QXP_USB_SS3_TC0 4 -#define IMX8QXP_USB_SS3_TC1_ADMA_I2C1_SCL IMX8QXP_USB_SS3_TC1 0 -#define IMX8QXP_USB_SS3_TC1_CONN_USB_OTG2_PWR IMX8QXP_USB_SS3_TC1 1 -#define IMX8QXP_USB_SS3_TC1_LSIO_GPIO4_IO04 IMX8QXP_USB_SS3_TC1 4 -#define IMX8QXP_USB_SS3_TC2_ADMA_I2C1_SDA IMX8QXP_USB_SS3_TC2 0 -#define IMX8QXP_USB_SS3_TC2_CONN_USB_OTG1_OC IMX8QXP_USB_SS3_TC2 1 -#define IMX8QXP_USB_SS3_TC2_CONN_USB_OTG2_OC IMX8QXP_USB_SS3_TC2 2 -#define IMX8QXP_USB_SS3_TC2_LSIO_GPIO4_IO05 IMX8QXP_USB_SS3_TC2 4 -#define IMX8QXP_USB_SS3_TC3_ADMA_I2C1_SDA IMX8QXP_USB_SS3_TC3 0 -#define IMX8QXP_USB_SS3_TC3_CONN_USB_OTG2_OC IMX8QXP_USB_SS3_TC3 1 -#define IMX8QXP_USB_SS3_TC3_LSIO_GPIO4_IO06 IMX8QXP_USB_SS3_TC3 4 -#define IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK IMX8QXP_EMMC0_CLK 0 -#define IMX8QXP_EMMC0_CLK_CONN_NAND_READY_B IMX8QXP_EMMC0_CLK 1 -#define IMX8QXP_EMMC0_CLK_LSIO_GPIO4_IO07 IMX8QXP_EMMC0_CLK 4 -#define IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD IMX8QXP_EMMC0_CMD 0 -#define IMX8QXP_EMMC0_CMD_CONN_NAND_DQS IMX8QXP_EMMC0_CMD 1 -#define IMX8QXP_EMMC0_CMD_LSIO_GPIO4_IO08 IMX8QXP_EMMC0_CMD 4 -#define IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 IMX8QXP_EMMC0_DATA0 0 -#define IMX8QXP_EMMC0_DATA0_CONN_NAND_DATA00 IMX8QXP_EMMC0_DATA0 1 -#define IMX8QXP_EMMC0_DATA0_LSIO_GPIO4_IO09 IMX8QXP_EMMC0_DATA0 4 -#define IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 IMX8QXP_EMMC0_DATA1 0 -#define IMX8QXP_EMMC0_DATA1_CONN_NAND_DATA01 IMX8QXP_EMMC0_DATA1 1 -#define IMX8QXP_EMMC0_DATA1_LSIO_GPIO4_IO10 IMX8QXP_EMMC0_DATA1 4 -#define IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 IMX8QXP_EMMC0_DATA2 0 -#define IMX8QXP_EMMC0_DATA2_CONN_NAND_DATA02 IMX8QXP_EMMC0_DATA2 1 -#define IMX8QXP_EMMC0_DATA2_LSIO_GPIO4_IO11 IMX8QXP_EMMC0_DATA2 4 -#define IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 IMX8QXP_EMMC0_DATA3 0 -#define IMX8QXP_EMMC0_DATA3_CONN_NAND_DATA03 IMX8QXP_EMMC0_DATA3 1 -#define IMX8QXP_EMMC0_DATA3_LSIO_GPIO4_IO12 IMX8QXP_EMMC0_DATA3 4 -#define IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 IMX8QXP_EMMC0_DATA4 0 -#define IMX8QXP_EMMC0_DATA4_CONN_NAND_DATA04 IMX8QXP_EMMC0_DATA4 1 -#define IMX8QXP_EMMC0_DATA4_CONN_EMMC0_WP IMX8QXP_EMMC0_DATA4 3 -#define IMX8QXP_EMMC0_DATA4_LSIO_GPIO4_IO13 IMX8QXP_EMMC0_DATA4 4 -#define IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 IMX8QXP_EMMC0_DATA5 0 -#define IMX8QXP_EMMC0_DATA5_CONN_NAND_DATA05 IMX8QXP_EMMC0_DATA5 1 -#define IMX8QXP_EMMC0_DATA5_CONN_EMMC0_VSELECT IMX8QXP_EMMC0_DATA5 3 -#define IMX8QXP_EMMC0_DATA5_LSIO_GPIO4_IO14 IMX8QXP_EMMC0_DATA5 4 -#define IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 IMX8QXP_EMMC0_DATA6 0 -#define IMX8QXP_EMMC0_DATA6_CONN_NAND_DATA06 IMX8QXP_EMMC0_DATA6 1 -#define IMX8QXP_EMMC0_DATA6_CONN_MLB_CLK IMX8QXP_EMMC0_DATA6 3 -#define IMX8QXP_EMMC0_DATA6_LSIO_GPIO4_IO15 IMX8QXP_EMMC0_DATA6 4 -#define IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 IMX8QXP_EMMC0_DATA7 0 -#define IMX8QXP_EMMC0_DATA7_CONN_NAND_DATA07 IMX8QXP_EMMC0_DATA7 1 -#define IMX8QXP_EMMC0_DATA7_CONN_MLB_SIG IMX8QXP_EMMC0_DATA7 3 -#define IMX8QXP_EMMC0_DATA7_LSIO_GPIO4_IO16 IMX8QXP_EMMC0_DATA7 4 -#define IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE IMX8QXP_EMMC0_STROBE 0 -#define IMX8QXP_EMMC0_STROBE_CONN_NAND_CLE IMX8QXP_EMMC0_STROBE 1 -#define IMX8QXP_EMMC0_STROBE_CONN_MLB_DATA IMX8QXP_EMMC0_STROBE 3 -#define IMX8QXP_EMMC0_STROBE_LSIO_GPIO4_IO17 IMX8QXP_EMMC0_STROBE 4 -#define IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B IMX8QXP_EMMC0_RESET_B 0 -#define IMX8QXP_EMMC0_RESET_B_CONN_NAND_WP_B IMX8QXP_EMMC0_RESET_B 1 -#define IMX8QXP_EMMC0_RESET_B_LSIO_GPIO4_IO18 IMX8QXP_EMMC0_RESET_B 4 -#define IMX8QXP_USDHC1_RESET_B_CONN_USDHC1_RESET_B IMX8QXP_USDHC1_RESET_B 0 -#define IMX8QXP_USDHC1_RESET_B_CONN_NAND_RE_N IMX8QXP_USDHC1_RESET_B 1 -#define IMX8QXP_USDHC1_RESET_B_ADMA_SPI2_SCK IMX8QXP_USDHC1_RESET_B 2 -#define IMX8QXP_USDHC1_RESET_B_LSIO_GPIO4_IO19 IMX8QXP_USDHC1_RESET_B 4 -#define IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT IMX8QXP_USDHC1_VSELECT 0 -#define IMX8QXP_USDHC1_VSELECT_CONN_NAND_RE_P IMX8QXP_USDHC1_VSELECT 1 -#define IMX8QXP_USDHC1_VSELECT_ADMA_SPI2_SDO IMX8QXP_USDHC1_VSELECT 2 -#define IMX8QXP_USDHC1_VSELECT_CONN_NAND_RE_B IMX8QXP_USDHC1_VSELECT 3 -#define IMX8QXP_USDHC1_VSELECT_LSIO_GPIO4_IO20 IMX8QXP_USDHC1_VSELECT 4 -#define IMX8QXP_USDHC1_WP_CONN_USDHC1_WP IMX8QXP_USDHC1_WP 0 -#define IMX8QXP_USDHC1_WP_CONN_NAND_DQS_N IMX8QXP_USDHC1_WP 1 -#define IMX8QXP_USDHC1_WP_ADMA_SPI2_SDI IMX8QXP_USDHC1_WP 2 -#define IMX8QXP_USDHC1_WP_LSIO_GPIO4_IO21 IMX8QXP_USDHC1_WP 4 -#define IMX8QXP_USDHC1_CD_B_CONN_USDHC1_CD_B IMX8QXP_USDHC1_CD_B 0 -#define IMX8QXP_USDHC1_CD_B_CONN_NAND_DQS_P IMX8QXP_USDHC1_CD_B 1 -#define IMX8QXP_USDHC1_CD_B_ADMA_SPI2_CS0 IMX8QXP_USDHC1_CD_B 2 -#define IMX8QXP_USDHC1_CD_B_CONN_NAND_DQS IMX8QXP_USDHC1_CD_B 3 -#define IMX8QXP_USDHC1_CD_B_LSIO_GPIO4_IO22 IMX8QXP_USDHC1_CD_B 4 -#define IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK IMX8QXP_USDHC1_CLK 0 -#define IMX8QXP_USDHC1_CLK_ADMA_UART3_RX IMX8QXP_USDHC1_CLK 2 -#define IMX8QXP_USDHC1_CLK_LSIO_GPIO4_IO23 IMX8QXP_USDHC1_CLK 4 -#define IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD IMX8QXP_USDHC1_CMD 0 -#define IMX8QXP_USDHC1_CMD_CONN_NAND_CE0_B IMX8QXP_USDHC1_CMD 1 -#define IMX8QXP_USDHC1_CMD_ADMA_MQS_R IMX8QXP_USDHC1_CMD 2 -#define IMX8QXP_USDHC1_CMD_LSIO_GPIO4_IO24 IMX8QXP_USDHC1_CMD 4 -#define IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 IMX8QXP_USDHC1_DATA0 0 -#define IMX8QXP_USDHC1_DATA0_CONN_NAND_CE1_B IMX8QXP_USDHC1_DATA0 1 -#define IMX8QXP_USDHC1_DATA0_ADMA_MQS_L IMX8QXP_USDHC1_DATA0 2 -#define IMX8QXP_USDHC1_DATA0_LSIO_GPIO4_IO25 IMX8QXP_USDHC1_DATA0 4 -#define IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 IMX8QXP_USDHC1_DATA1 0 -#define IMX8QXP_USDHC1_DATA1_CONN_NAND_RE_B IMX8QXP_USDHC1_DATA1 1 -#define IMX8QXP_USDHC1_DATA1_ADMA_UART3_TX IMX8QXP_USDHC1_DATA1 2 -#define IMX8QXP_USDHC1_DATA1_LSIO_GPIO4_IO26 IMX8QXP_USDHC1_DATA1 4 -#define IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 IMX8QXP_USDHC1_DATA2 0 -#define IMX8QXP_USDHC1_DATA2_CONN_NAND_WE_B IMX8QXP_USDHC1_DATA2 1 -#define IMX8QXP_USDHC1_DATA2_ADMA_UART3_CTS_B IMX8QXP_USDHC1_DATA2 2 -#define IMX8QXP_USDHC1_DATA2_LSIO_GPIO4_IO27 IMX8QXP_USDHC1_DATA2 4 -#define IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 IMX8QXP_USDHC1_DATA3 0 -#define IMX8QXP_USDHC1_DATA3_CONN_NAND_ALE IMX8QXP_USDHC1_DATA3 1 -#define IMX8QXP_USDHC1_DATA3_ADMA_UART3_RTS_B IMX8QXP_USDHC1_DATA3 2 -#define IMX8QXP_USDHC1_DATA3_LSIO_GPIO4_IO28 IMX8QXP_USDHC1_DATA3 4 -#define IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC IMX8QXP_ENET0_RGMII_TXC 0 -#define IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT IMX8QXP_ENET0_RGMII_TXC 1 -#define IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_IN IMX8QXP_ENET0_RGMII_TXC 2 -#define IMX8QXP_ENET0_RGMII_TXC_CONN_NAND_CE1_B IMX8QXP_ENET0_RGMII_TXC 3 -#define IMX8QXP_ENET0_RGMII_TXC_LSIO_GPIO4_IO29 IMX8QXP_ENET0_RGMII_TXC 4 -#define IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL IMX8QXP_ENET0_RGMII_TX_CTL 0 -#define IMX8QXP_ENET0_RGMII_TX_CTL_CONN_USDHC1_RESET_B IMX8QXP_ENET0_RGMII_TX_CTL 3 -#define IMX8QXP_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30 IMX8QXP_ENET0_RGMII_TX_CTL 4 -#define IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 IMX8QXP_ENET0_RGMII_TXD0 0 -#define IMX8QXP_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT IMX8QXP_ENET0_RGMII_TXD0 3 -#define IMX8QXP_ENET0_RGMII_TXD0_LSIO_GPIO4_IO31 IMX8QXP_ENET0_RGMII_TXD0 4 -#define IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 IMX8QXP_ENET0_RGMII_TXD1 0 -#define IMX8QXP_ENET0_RGMII_TXD1_CONN_USDHC1_WP IMX8QXP_ENET0_RGMII_TXD1 3 -#define IMX8QXP_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00 IMX8QXP_ENET0_RGMII_TXD1 4 -#define IMX8QXP_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 IMX8QXP_ENET0_RGMII_TXD2 0 -#define IMX8QXP_ENET0_RGMII_TXD2_CONN_MLB_CLK IMX8QXP_ENET0_RGMII_TXD2 1 -#define IMX8QXP_ENET0_RGMII_TXD2_CONN_NAND_CE0_B IMX8QXP_ENET0_RGMII_TXD2 2 -#define IMX8QXP_ENET0_RGMII_TXD2_CONN_USDHC1_CD_B IMX8QXP_ENET0_RGMII_TXD2 3 -#define IMX8QXP_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 IMX8QXP_ENET0_RGMII_TXD2 4 -#define IMX8QXP_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 IMX8QXP_ENET0_RGMII_TXD3 0 -#define IMX8QXP_ENET0_RGMII_TXD3_CONN_MLB_SIG IMX8QXP_ENET0_RGMII_TXD3 1 -#define IMX8QXP_ENET0_RGMII_TXD3_CONN_NAND_RE_B IMX8QXP_ENET0_RGMII_TXD3 2 -#define IMX8QXP_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02 IMX8QXP_ENET0_RGMII_TXD3 4 -#define IMX8QXP_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC IMX8QXP_ENET0_RGMII_RXC 0 -#define IMX8QXP_ENET0_RGMII_RXC_CONN_MLB_DATA IMX8QXP_ENET0_RGMII_RXC 1 -#define IMX8QXP_ENET0_RGMII_RXC_CONN_NAND_WE_B IMX8QXP_ENET0_RGMII_RXC 2 -#define IMX8QXP_ENET0_RGMII_RXC_CONN_USDHC1_CLK IMX8QXP_ENET0_RGMII_RXC 3 -#define IMX8QXP_ENET0_RGMII_RXC_LSIO_GPIO5_IO03 IMX8QXP_ENET0_RGMII_RXC 4 -#define IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL IMX8QXP_ENET0_RGMII_RX_CTL 0 -#define IMX8QXP_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD IMX8QXP_ENET0_RGMII_RX_CTL 3 -#define IMX8QXP_ENET0_RGMII_RX_CTL_LSIO_GPIO5_IO04 IMX8QXP_ENET0_RGMII_RX_CTL 4 -#define IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 IMX8QXP_ENET0_RGMII_RXD0 0 -#define IMX8QXP_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 IMX8QXP_ENET0_RGMII_RXD0 3 -#define IMX8QXP_ENET0_RGMII_RXD0_LSIO_GPIO5_IO05 IMX8QXP_ENET0_RGMII_RXD0 4 -#define IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 IMX8QXP_ENET0_RGMII_RXD1 0 -#define IMX8QXP_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 IMX8QXP_ENET0_RGMII_RXD1 3 -#define IMX8QXP_ENET0_RGMII_RXD1_LSIO_GPIO5_IO06 IMX8QXP_ENET0_RGMII_RXD1 4 -#define IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 IMX8QXP_ENET0_RGMII_RXD2 0 -#define IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER IMX8QXP_ENET0_RGMII_RXD2 1 -#define IMX8QXP_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 IMX8QXP_ENET0_RGMII_RXD2 3 -#define IMX8QXP_ENET0_RGMII_RXD2_LSIO_GPIO5_IO07 IMX8QXP_ENET0_RGMII_RXD2 4 -#define IMX8QXP_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 IMX8QXP_ENET0_RGMII_RXD3 0 -#define IMX8QXP_ENET0_RGMII_RXD3_CONN_NAND_ALE IMX8QXP_ENET0_RGMII_RXD3 2 -#define IMX8QXP_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 IMX8QXP_ENET0_RGMII_RXD3 3 -#define IMX8QXP_ENET0_RGMII_RXD3_LSIO_GPIO5_IO08 IMX8QXP_ENET0_RGMII_RXD3 4 -#define IMX8QXP_ENET0_REFCLK_125M_25M_CONN_ENET0_REFCLK_125M_25M IMX8QXP_ENET0_REFCLK_125M_25M 0 -#define IMX8QXP_ENET0_REFCLK_125M_25M_CONN_ENET0_PPS IMX8QXP_ENET0_REFCLK_125M_25M 1 -#define IMX8QXP_ENET0_REFCLK_125M_25M_CONN_ENET1_PPS IMX8QXP_ENET0_REFCLK_125M_25M 2 -#define IMX8QXP_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 IMX8QXP_ENET0_REFCLK_125M_25M 4 -#define IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO IMX8QXP_ENET0_MDIO 0 -#define IMX8QXP_ENET0_MDIO_ADMA_I2C3_SDA IMX8QXP_ENET0_MDIO 1 -#define IMX8QXP_ENET0_MDIO_CONN_ENET1_MDIO IMX8QXP_ENET0_MDIO 2 -#define IMX8QXP_ENET0_MDIO_LSIO_GPIO5_IO10 IMX8QXP_ENET0_MDIO 4 -#define IMX8QXP_ENET0_MDC_CONN_ENET0_MDC IMX8QXP_ENET0_MDC 0 -#define IMX8QXP_ENET0_MDC_ADMA_I2C3_SCL IMX8QXP_ENET0_MDC 1 -#define IMX8QXP_ENET0_MDC_CONN_ENET1_MDC IMX8QXP_ENET0_MDC 2 -#define IMX8QXP_ENET0_MDC_LSIO_GPIO5_IO11 IMX8QXP_ENET0_MDC 4 -#define IMX8QXP_ESAI0_FSR_ADMA_ESAI0_FSR IMX8QXP_ESAI0_FSR 0 -#define IMX8QXP_ESAI0_FSR_CONN_ENET1_RCLK50M_OUT IMX8QXP_ESAI0_FSR 1 -#define IMX8QXP_ESAI0_FSR_ADMA_LCDIF_D00 IMX8QXP_ESAI0_FSR 2 -#define IMX8QXP_ESAI0_FSR_CONN_ENET1_RGMII_TXC IMX8QXP_ESAI0_FSR 3 -#define IMX8QXP_ESAI0_FSR_CONN_ENET1_RCLK50M_IN IMX8QXP_ESAI0_FSR 4 -#define IMX8QXP_ESAI0_FST_ADMA_ESAI0_FST IMX8QXP_ESAI0_FST 0 -#define IMX8QXP_ESAI0_FST_CONN_MLB_CLK IMX8QXP_ESAI0_FST 1 -#define IMX8QXP_ESAI0_FST_ADMA_LCDIF_D01 IMX8QXP_ESAI0_FST 2 -#define IMX8QXP_ESAI0_FST_CONN_ENET1_RGMII_TXD2 IMX8QXP_ESAI0_FST 3 -#define IMX8QXP_ESAI0_FST_LSIO_GPIO0_IO01 IMX8QXP_ESAI0_FST 4 -#define IMX8QXP_ESAI0_SCKR_ADMA_ESAI0_SCKR IMX8QXP_ESAI0_SCKR 0 -#define IMX8QXP_ESAI0_SCKR_ADMA_LCDIF_D02 IMX8QXP_ESAI0_SCKR 2 -#define IMX8QXP_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL IMX8QXP_ESAI0_SCKR 3 -#define IMX8QXP_ESAI0_SCKR_LSIO_GPIO0_IO02 IMX8QXP_ESAI0_SCKR 4 -#define IMX8QXP_ESAI0_SCKT_ADMA_ESAI0_SCKT IMX8QXP_ESAI0_SCKT 0 -#define IMX8QXP_ESAI0_SCKT_CONN_MLB_SIG IMX8QXP_ESAI0_SCKT 1 -#define IMX8QXP_ESAI0_SCKT_ADMA_LCDIF_D03 IMX8QXP_ESAI0_SCKT 2 -#define IMX8QXP_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3 IMX8QXP_ESAI0_SCKT 3 -#define IMX8QXP_ESAI0_SCKT_LSIO_GPIO0_IO03 IMX8QXP_ESAI0_SCKT 4 -#define IMX8QXP_ESAI0_TX0_ADMA_ESAI0_TX0 IMX8QXP_ESAI0_TX0 0 -#define IMX8QXP_ESAI0_TX0_CONN_MLB_DATA IMX8QXP_ESAI0_TX0 1 -#define IMX8QXP_ESAI0_TX0_ADMA_LCDIF_D04 IMX8QXP_ESAI0_TX0 2 -#define IMX8QXP_ESAI0_TX0_CONN_ENET1_RGMII_RXC IMX8QXP_ESAI0_TX0 3 -#define IMX8QXP_ESAI0_TX0_LSIO_GPIO0_IO04 IMX8QXP_ESAI0_TX0 4 -#define IMX8QXP_ESAI0_TX1_ADMA_ESAI0_TX1 IMX8QXP_ESAI0_TX1 0 -#define IMX8QXP_ESAI0_TX1_ADMA_LCDIF_D05 IMX8QXP_ESAI0_TX1 2 -#define IMX8QXP_ESAI0_TX1_CONN_ENET1_RGMII_RXD3 IMX8QXP_ESAI0_TX1 3 -#define IMX8QXP_ESAI0_TX1_LSIO_GPIO0_IO05 IMX8QXP_ESAI0_TX1 4 -#define IMX8QXP_ESAI0_TX2_RX3_ADMA_ESAI0_TX2_RX3 IMX8QXP_ESAI0_TX2_RX3 0 -#define IMX8QXP_ESAI0_TX2_RX3_CONN_ENET1_RMII_RX_ER IMX8QXP_ESAI0_TX2_RX3 1 -#define IMX8QXP_ESAI0_TX2_RX3_ADMA_LCDIF_D06 IMX8QXP_ESAI0_TX2_RX3 2 -#define IMX8QXP_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2 IMX8QXP_ESAI0_TX2_RX3 3 -#define IMX8QXP_ESAI0_TX2_RX3_LSIO_GPIO0_IO06 IMX8QXP_ESAI0_TX2_RX3 4 -#define IMX8QXP_ESAI0_TX3_RX2_ADMA_ESAI0_TX3_RX2 IMX8QXP_ESAI0_TX3_RX2 0 -#define IMX8QXP_ESAI0_TX3_RX2_ADMA_LCDIF_D07 IMX8QXP_ESAI0_TX3_RX2 2 -#define IMX8QXP_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 IMX8QXP_ESAI0_TX3_RX2 3 -#define IMX8QXP_ESAI0_TX3_RX2_LSIO_GPIO0_IO07 IMX8QXP_ESAI0_TX3_RX2 4 -#define IMX8QXP_ESAI0_TX4_RX1_ADMA_ESAI0_TX4_RX1 IMX8QXP_ESAI0_TX4_RX1 0 -#define IMX8QXP_ESAI0_TX4_RX1_ADMA_LCDIF_D08 IMX8QXP_ESAI0_TX4_RX1 2 -#define IMX8QXP_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 IMX8QXP_ESAI0_TX4_RX1 3 -#define IMX8QXP_ESAI0_TX4_RX1_LSIO_GPIO0_IO08 IMX8QXP_ESAI0_TX4_RX1 4 -#define IMX8QXP_ESAI0_TX5_RX0_ADMA_ESAI0_TX5_RX0 IMX8QXP_ESAI0_TX5_RX0 0 -#define IMX8QXP_ESAI0_TX5_RX0_ADMA_LCDIF_D09 IMX8QXP_ESAI0_TX5_RX0 2 -#define IMX8QXP_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 IMX8QXP_ESAI0_TX5_RX0 3 -#define IMX8QXP_ESAI0_TX5_RX0_LSIO_GPIO0_IO09 IMX8QXP_ESAI0_TX5_RX0 4 -#define IMX8QXP_SPDIF0_RX_ADMA_SPDIF0_RX IMX8QXP_SPDIF0_RX 0 -#define IMX8QXP_SPDIF0_RX_ADMA_MQS_R IMX8QXP_SPDIF0_RX 1 -#define IMX8QXP_SPDIF0_RX_ADMA_LCDIF_D10 IMX8QXP_SPDIF0_RX 2 -#define IMX8QXP_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 IMX8QXP_SPDIF0_RX 3 -#define IMX8QXP_SPDIF0_RX_LSIO_GPIO0_IO10 IMX8QXP_SPDIF0_RX 4 -#define IMX8QXP_SPDIF0_TX_ADMA_SPDIF0_TX IMX8QXP_SPDIF0_TX 0 -#define IMX8QXP_SPDIF0_TX_ADMA_MQS_L IMX8QXP_SPDIF0_TX 1 -#define IMX8QXP_SPDIF0_TX_ADMA_LCDIF_D11 IMX8QXP_SPDIF0_TX 2 -#define IMX8QXP_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL IMX8QXP_SPDIF0_TX 3 -#define IMX8QXP_SPDIF0_TX_LSIO_GPIO0_IO11 IMX8QXP_SPDIF0_TX 4 -#define IMX8QXP_SPDIF0_EXT_CLK_ADMA_SPDIF0_EXT_CLK IMX8QXP_SPDIF0_EXT_CLK 0 -#define IMX8QXP_SPDIF0_EXT_CLK_ADMA_LCDIF_D12 IMX8QXP_SPDIF0_EXT_CLK 2 -#define IMX8QXP_SPDIF0_EXT_CLK_CONN_ENET1_REFCLK_125M_25M IMX8QXP_SPDIF0_EXT_CLK 3 -#define IMX8QXP_SPDIF0_EXT_CLK_LSIO_GPIO0_IO12 IMX8QXP_SPDIF0_EXT_CLK 4 -#define IMX8QXP_SPI3_SCK_ADMA_SPI3_SCK IMX8QXP_SPI3_SCK 0 -#define IMX8QXP_SPI3_SCK_ADMA_LCDIF_D13 IMX8QXP_SPI3_SCK 2 -#define IMX8QXP_SPI3_SCK_LSIO_GPIO0_IO13 IMX8QXP_SPI3_SCK 4 -#define IMX8QXP_SPI3_SDO_ADMA_SPI3_SDO IMX8QXP_SPI3_SDO 0 -#define IMX8QXP_SPI3_SDO_ADMA_LCDIF_D14 IMX8QXP_SPI3_SDO 2 -#define IMX8QXP_SPI3_SDO_LSIO_GPIO0_IO14 IMX8QXP_SPI3_SDO 4 -#define IMX8QXP_SPI3_SDI_ADMA_SPI3_SDI IMX8QXP_SPI3_SDI 0 -#define IMX8QXP_SPI3_SDI_ADMA_LCDIF_D15 IMX8QXP_SPI3_SDI 2 -#define IMX8QXP_SPI3_SDI_LSIO_GPIO0_IO15 IMX8QXP_SPI3_SDI 4 -#define IMX8QXP_SPI3_CS0_ADMA_SPI3_CS0 IMX8QXP_SPI3_CS0 0 -#define IMX8QXP_SPI3_CS0_ADMA_ACM_MCLK_OUT1 IMX8QXP_SPI3_CS0 1 -#define IMX8QXP_SPI3_CS0_ADMA_LCDIF_HSYNC IMX8QXP_SPI3_CS0 2 -#define IMX8QXP_SPI3_CS0_LSIO_GPIO0_IO16 IMX8QXP_SPI3_CS0 4 -#define IMX8QXP_SPI3_CS1_ADMA_SPI3_CS1 IMX8QXP_SPI3_CS1 0 -#define IMX8QXP_SPI3_CS1_ADMA_I2C3_SCL IMX8QXP_SPI3_CS1 1 -#define IMX8QXP_SPI3_CS1_ADMA_LCDIF_RESET IMX8QXP_SPI3_CS1 2 -#define IMX8QXP_SPI3_CS1_ADMA_SPI2_CS0 IMX8QXP_SPI3_CS1 3 -#define IMX8QXP_SPI3_CS1_ADMA_LCDIF_D16 IMX8QXP_SPI3_CS1 4 -#define IMX8QXP_MCLK_IN1_ADMA_ACM_MCLK_IN1 IMX8QXP_MCLK_IN1 0 -#define IMX8QXP_MCLK_IN1_ADMA_I2C3_SDA IMX8QXP_MCLK_IN1 1 -#define IMX8QXP_MCLK_IN1_ADMA_LCDIF_EN IMX8QXP_MCLK_IN1 2 -#define IMX8QXP_MCLK_IN1_ADMA_SPI2_SCK IMX8QXP_MCLK_IN1 3 -#define IMX8QXP_MCLK_IN1_ADMA_LCDIF_D17 IMX8QXP_MCLK_IN1 4 -#define IMX8QXP_MCLK_IN0_ADMA_ACM_MCLK_IN0 IMX8QXP_MCLK_IN0 0 -#define IMX8QXP_MCLK_IN0_ADMA_ESAI0_RX_HF_CLK IMX8QXP_MCLK_IN0 1 -#define IMX8QXP_MCLK_IN0_ADMA_LCDIF_VSYNC IMX8QXP_MCLK_IN0 2 -#define IMX8QXP_MCLK_IN0_ADMA_SPI2_SDI IMX8QXP_MCLK_IN0 3 -#define IMX8QXP_MCLK_IN0_LSIO_GPIO0_IO19 IMX8QXP_MCLK_IN0 4 -#define IMX8QXP_MCLK_OUT0_ADMA_ACM_MCLK_OUT0 IMX8QXP_MCLK_OUT0 0 -#define IMX8QXP_MCLK_OUT0_ADMA_ESAI0_TX_HF_CLK IMX8QXP_MCLK_OUT0 1 -#define IMX8QXP_MCLK_OUT0_ADMA_LCDIF_CLK IMX8QXP_MCLK_OUT0 2 -#define IMX8QXP_MCLK_OUT0_ADMA_SPI2_SDO IMX8QXP_MCLK_OUT0 3 -#define IMX8QXP_MCLK_OUT0_LSIO_GPIO0_IO20 IMX8QXP_MCLK_OUT0 4 -#define IMX8QXP_UART1_TX_ADMA_UART1_TX IMX8QXP_UART1_TX 0 -#define IMX8QXP_UART1_TX_LSIO_PWM0_OUT IMX8QXP_UART1_TX 1 -#define IMX8QXP_UART1_TX_LSIO_GPT0_CAPTURE IMX8QXP_UART1_TX 2 -#define IMX8QXP_UART1_TX_LSIO_GPIO0_IO21 IMX8QXP_UART1_TX 4 -#define IMX8QXP_UART1_RX_ADMA_UART1_RX IMX8QXP_UART1_RX 0 -#define IMX8QXP_UART1_RX_LSIO_PWM1_OUT IMX8QXP_UART1_RX 1 -#define IMX8QXP_UART1_RX_LSIO_GPT0_COMPARE IMX8QXP_UART1_RX 2 -#define IMX8QXP_UART1_RX_LSIO_GPT1_CLK IMX8QXP_UART1_RX 3 -#define IMX8QXP_UART1_RX_LSIO_GPIO0_IO22 IMX8QXP_UART1_RX 4 -#define IMX8QXP_UART1_RTS_B_ADMA_UART1_RTS_B IMX8QXP_UART1_RTS_B 0 -#define IMX8QXP_UART1_RTS_B_LSIO_PWM2_OUT IMX8QXP_UART1_RTS_B 1 -#define IMX8QXP_UART1_RTS_B_ADMA_LCDIF_D16 IMX8QXP_UART1_RTS_B 2 -#define IMX8QXP_UART1_RTS_B_LSIO_GPT1_CAPTURE IMX8QXP_UART1_RTS_B 3 -#define IMX8QXP_UART1_RTS_B_LSIO_GPT0_CLK IMX8QXP_UART1_RTS_B 4 -#define IMX8QXP_UART1_CTS_B_ADMA_UART1_CTS_B IMX8QXP_UART1_CTS_B 0 -#define IMX8QXP_UART1_CTS_B_LSIO_PWM3_OUT IMX8QXP_UART1_CTS_B 1 -#define IMX8QXP_UART1_CTS_B_ADMA_LCDIF_D17 IMX8QXP_UART1_CTS_B 2 -#define IMX8QXP_UART1_CTS_B_LSIO_GPT1_COMPARE IMX8QXP_UART1_CTS_B 3 -#define IMX8QXP_UART1_CTS_B_LSIO_GPIO0_IO24 IMX8QXP_UART1_CTS_B 4 -#define IMX8QXP_SAI0_TXD_ADMA_SAI0_TXD IMX8QXP_SAI0_TXD 0 -#define IMX8QXP_SAI0_TXD_ADMA_SAI1_RXC IMX8QXP_SAI0_TXD 1 -#define IMX8QXP_SAI0_TXD_ADMA_SPI1_SDO IMX8QXP_SAI0_TXD 2 -#define IMX8QXP_SAI0_TXD_ADMA_LCDIF_D18 IMX8QXP_SAI0_TXD 3 -#define IMX8QXP_SAI0_TXD_LSIO_GPIO0_IO25 IMX8QXP_SAI0_TXD 4 -#define IMX8QXP_SAI0_TXC_ADMA_SAI0_TXC IMX8QXP_SAI0_TXC 0 -#define IMX8QXP_SAI0_TXC_ADMA_SAI1_TXD IMX8QXP_SAI0_TXC 1 -#define IMX8QXP_SAI0_TXC_ADMA_SPI1_SDI IMX8QXP_SAI0_TXC 2 -#define IMX8QXP_SAI0_TXC_ADMA_LCDIF_D19 IMX8QXP_SAI0_TXC 3 -#define IMX8QXP_SAI0_TXC_LSIO_GPIO0_IO26 IMX8QXP_SAI0_TXC 4 -#define IMX8QXP_SAI0_RXD_ADMA_SAI0_RXD IMX8QXP_SAI0_RXD 0 -#define IMX8QXP_SAI0_RXD_ADMA_SAI1_RXFS IMX8QXP_SAI0_RXD 1 -#define IMX8QXP_SAI0_RXD_ADMA_SPI1_CS0 IMX8QXP_SAI0_RXD 2 -#define IMX8QXP_SAI0_RXD_ADMA_LCDIF_D20 IMX8QXP_SAI0_RXD 3 -#define IMX8QXP_SAI0_RXD_LSIO_GPIO0_IO27 IMX8QXP_SAI0_RXD 4 -#define IMX8QXP_SAI0_TXFS_ADMA_SAI0_TXFS IMX8QXP_SAI0_TXFS 0 -#define IMX8QXP_SAI0_TXFS_ADMA_SPI2_CS1 IMX8QXP_SAI0_TXFS 1 -#define IMX8QXP_SAI0_TXFS_ADMA_SPI1_SCK IMX8QXP_SAI0_TXFS 2 -#define IMX8QXP_SAI0_TXFS_LSIO_GPIO0_IO28 IMX8QXP_SAI0_TXFS 4 -#define IMX8QXP_SAI1_RXD_ADMA_SAI1_RXD IMX8QXP_SAI1_RXD 0 -#define IMX8QXP_SAI1_RXD_ADMA_SAI0_RXFS IMX8QXP_SAI1_RXD 1 -#define IMX8QXP_SAI1_RXD_ADMA_SPI1_CS1 IMX8QXP_SAI1_RXD 2 -#define IMX8QXP_SAI1_RXD_ADMA_LCDIF_D21 IMX8QXP_SAI1_RXD 3 -#define IMX8QXP_SAI1_RXD_LSIO_GPIO0_IO29 IMX8QXP_SAI1_RXD 4 -#define IMX8QXP_SAI1_RXC_ADMA_SAI1_RXC IMX8QXP_SAI1_RXC 0 -#define IMX8QXP_SAI1_RXC_ADMA_SAI1_TXC IMX8QXP_SAI1_RXC 1 -#define IMX8QXP_SAI1_RXC_ADMA_LCDIF_D22 IMX8QXP_SAI1_RXC 3 -#define IMX8QXP_SAI1_RXC_LSIO_GPIO0_IO30 IMX8QXP_SAI1_RXC 4 -#define IMX8QXP_SAI1_RXFS_ADMA_SAI1_RXFS IMX8QXP_SAI1_RXFS 0 -#define IMX8QXP_SAI1_RXFS_ADMA_SAI1_TXFS IMX8QXP_SAI1_RXFS 1 -#define IMX8QXP_SAI1_RXFS_ADMA_LCDIF_D23 IMX8QXP_SAI1_RXFS 3 -#define IMX8QXP_SAI1_RXFS_LSIO_GPIO0_IO31 IMX8QXP_SAI1_RXFS 4 -#define IMX8QXP_SPI2_CS0_ADMA_SPI2_CS0 IMX8QXP_SPI2_CS0 0 -#define IMX8QXP_SPI2_CS0_LSIO_GPIO1_IO00 IMX8QXP_SPI2_CS0 4 -#define IMX8QXP_SPI2_SDO_ADMA_SPI2_SDO IMX8QXP_SPI2_SDO 0 -#define IMX8QXP_SPI2_SDO_LSIO_GPIO1_IO01 IMX8QXP_SPI2_SDO 4 -#define IMX8QXP_SPI2_SDI_ADMA_SPI2_SDI IMX8QXP_SPI2_SDI 0 -#define IMX8QXP_SPI2_SDI_LSIO_GPIO1_IO02 IMX8QXP_SPI2_SDI 4 -#define IMX8QXP_SPI2_SCK_ADMA_SPI2_SCK IMX8QXP_SPI2_SCK 0 -#define IMX8QXP_SPI2_SCK_LSIO_GPIO1_IO03 IMX8QXP_SPI2_SCK 4 -#define IMX8QXP_SPI0_SCK_ADMA_SPI0_SCK IMX8QXP_SPI0_SCK 0 -#define IMX8QXP_SPI0_SCK_ADMA_SAI0_TXC IMX8QXP_SPI0_SCK 1 -#define IMX8QXP_SPI0_SCK_M40_I2C0_SCL IMX8QXP_SPI0_SCK 2 -#define IMX8QXP_SPI0_SCK_M40_GPIO0_IO00 IMX8QXP_SPI0_SCK 3 -#define IMX8QXP_SPI0_SCK_LSIO_GPIO1_IO04 IMX8QXP_SPI0_SCK 4 -#define IMX8QXP_SPI0_SDI_ADMA_SPI0_SDI IMX8QXP_SPI0_SDI 0 -#define IMX8QXP_SPI0_SDI_ADMA_SAI0_TXD IMX8QXP_SPI0_SDI 1 -#define IMX8QXP_SPI0_SDI_M40_TPM0_CH0 IMX8QXP_SPI0_SDI 2 -#define IMX8QXP_SPI0_SDI_M40_GPIO0_IO02 IMX8QXP_SPI0_SDI 3 -#define IMX8QXP_SPI0_SDI_LSIO_GPIO1_IO05 IMX8QXP_SPI0_SDI 4 -#define IMX8QXP_SPI0_SDO_ADMA_SPI0_SDO IMX8QXP_SPI0_SDO 0 -#define IMX8QXP_SPI0_SDO_ADMA_SAI0_TXFS IMX8QXP_SPI0_SDO 1 -#define IMX8QXP_SPI0_SDO_M40_I2C0_SDA IMX8QXP_SPI0_SDO 2 -#define IMX8QXP_SPI0_SDO_M40_GPIO0_IO01 IMX8QXP_SPI0_SDO 3 -#define IMX8QXP_SPI0_SDO_LSIO_GPIO1_IO06 IMX8QXP_SPI0_SDO 4 -#define IMX8QXP_SPI0_CS1_ADMA_SPI0_CS1 IMX8QXP_SPI0_CS1 0 -#define IMX8QXP_SPI0_CS1_ADMA_SAI0_RXC IMX8QXP_SPI0_CS1 1 -#define IMX8QXP_SPI0_CS1_ADMA_SAI1_TXD IMX8QXP_SPI0_CS1 2 -#define IMX8QXP_SPI0_CS1_ADMA_LCD_PWM0_OUT IMX8QXP_SPI0_CS1 3 -#define IMX8QXP_SPI0_CS1_LSIO_GPIO1_IO07 IMX8QXP_SPI0_CS1 4 -#define IMX8QXP_SPI0_CS0_ADMA_SPI0_CS0 IMX8QXP_SPI0_CS0 0 -#define IMX8QXP_SPI0_CS0_ADMA_SAI0_RXD IMX8QXP_SPI0_CS0 1 -#define IMX8QXP_SPI0_CS0_M40_TPM0_CH1 IMX8QXP_SPI0_CS0 2 -#define IMX8QXP_SPI0_CS0_M40_GPIO0_IO03 IMX8QXP_SPI0_CS0 3 -#define IMX8QXP_SPI0_CS0_LSIO_GPIO1_IO08 IMX8QXP_SPI0_CS0 4 -#define IMX8QXP_ADC_IN1_ADMA_ADC_IN1 IMX8QXP_ADC_IN1 0 -#define IMX8QXP_ADC_IN1_M40_I2C0_SDA IMX8QXP_ADC_IN1 1 -#define IMX8QXP_ADC_IN1_M40_GPIO0_IO01 IMX8QXP_ADC_IN1 2 -#define IMX8QXP_ADC_IN1_LSIO_GPIO1_IO09 IMX8QXP_ADC_IN1 4 -#define IMX8QXP_ADC_IN0_ADMA_ADC_IN0 IMX8QXP_ADC_IN0 0 -#define IMX8QXP_ADC_IN0_M40_I2C0_SCL IMX8QXP_ADC_IN0 1 -#define IMX8QXP_ADC_IN0_M40_GPIO0_IO00 IMX8QXP_ADC_IN0 2 -#define IMX8QXP_ADC_IN0_LSIO_GPIO1_IO10 IMX8QXP_ADC_IN0 4 -#define IMX8QXP_ADC_IN3_ADMA_ADC_IN3 IMX8QXP_ADC_IN3 0 -#define IMX8QXP_ADC_IN3_M40_UART0_TX IMX8QXP_ADC_IN3 1 -#define IMX8QXP_ADC_IN3_M40_GPIO0_IO03 IMX8QXP_ADC_IN3 2 -#define IMX8QXP_ADC_IN3_ADMA_ACM_MCLK_OUT0 IMX8QXP_ADC_IN3 3 -#define IMX8QXP_ADC_IN3_LSIO_GPIO1_IO11 IMX8QXP_ADC_IN3 4 -#define IMX8QXP_ADC_IN2_ADMA_ADC_IN2 IMX8QXP_ADC_IN2 0 -#define IMX8QXP_ADC_IN2_M40_UART0_RX IMX8QXP_ADC_IN2 1 -#define IMX8QXP_ADC_IN2_M40_GPIO0_IO02 IMX8QXP_ADC_IN2 2 -#define IMX8QXP_ADC_IN2_ADMA_ACM_MCLK_IN0 IMX8QXP_ADC_IN2 3 -#define IMX8QXP_ADC_IN2_LSIO_GPIO1_IO12 IMX8QXP_ADC_IN2 4 -#define IMX8QXP_ADC_IN5_ADMA_ADC_IN5 IMX8QXP_ADC_IN5 0 -#define IMX8QXP_ADC_IN5_M40_TPM0_CH1 IMX8QXP_ADC_IN5 1 -#define IMX8QXP_ADC_IN5_M40_GPIO0_IO05 IMX8QXP_ADC_IN5 2 -#define IMX8QXP_ADC_IN5_LSIO_GPIO1_IO13 IMX8QXP_ADC_IN5 4 -#define IMX8QXP_ADC_IN4_ADMA_ADC_IN4 IMX8QXP_ADC_IN4 0 -#define IMX8QXP_ADC_IN4_M40_TPM0_CH0 IMX8QXP_ADC_IN4 1 -#define IMX8QXP_ADC_IN4_M40_GPIO0_IO04 IMX8QXP_ADC_IN4 2 -#define IMX8QXP_ADC_IN4_LSIO_GPIO1_IO14 IMX8QXP_ADC_IN4 4 -#define IMX8QXP_FLEXCAN0_RX_ADMA_FLEXCAN0_RX IMX8QXP_FLEXCAN0_RX 0 -#define IMX8QXP_FLEXCAN0_RX_ADMA_SAI2_RXC IMX8QXP_FLEXCAN0_RX 1 -#define IMX8QXP_FLEXCAN0_RX_ADMA_UART0_RTS_B IMX8QXP_FLEXCAN0_RX 2 -#define IMX8QXP_FLEXCAN0_RX_ADMA_SAI1_TXC IMX8QXP_FLEXCAN0_RX 3 -#define IMX8QXP_FLEXCAN0_RX_LSIO_GPIO1_IO15 IMX8QXP_FLEXCAN0_RX 4 -#define IMX8QXP_FLEXCAN0_TX_ADMA_FLEXCAN0_TX IMX8QXP_FLEXCAN0_TX 0 -#define IMX8QXP_FLEXCAN0_TX_ADMA_SAI2_RXD IMX8QXP_FLEXCAN0_TX 1 -#define IMX8QXP_FLEXCAN0_TX_ADMA_UART0_CTS_B IMX8QXP_FLEXCAN0_TX 2 -#define IMX8QXP_FLEXCAN0_TX_ADMA_SAI1_TXFS IMX8QXP_FLEXCAN0_TX 3 -#define IMX8QXP_FLEXCAN0_TX_LSIO_GPIO1_IO16 IMX8QXP_FLEXCAN0_TX 4 -#define IMX8QXP_FLEXCAN1_RX_ADMA_FLEXCAN1_RX IMX8QXP_FLEXCAN1_RX 0 -#define IMX8QXP_FLEXCAN1_RX_ADMA_SAI2_RXFS IMX8QXP_FLEXCAN1_RX 1 -#define IMX8QXP_FLEXCAN1_RX_ADMA_FTM_CH2 IMX8QXP_FLEXCAN1_RX 2 -#define IMX8QXP_FLEXCAN1_RX_ADMA_SAI1_TXD IMX8QXP_FLEXCAN1_RX 3 -#define IMX8QXP_FLEXCAN1_RX_LSIO_GPIO1_IO17 IMX8QXP_FLEXCAN1_RX 4 -#define IMX8QXP_FLEXCAN1_TX_ADMA_FLEXCAN1_TX IMX8QXP_FLEXCAN1_TX 0 -#define IMX8QXP_FLEXCAN1_TX_ADMA_SAI3_RXC IMX8QXP_FLEXCAN1_TX 1 -#define IMX8QXP_FLEXCAN1_TX_ADMA_DMA0_REQ_IN0 IMX8QXP_FLEXCAN1_TX 2 -#define IMX8QXP_FLEXCAN1_TX_ADMA_SAI1_RXD IMX8QXP_FLEXCAN1_TX 3 -#define IMX8QXP_FLEXCAN1_TX_LSIO_GPIO1_IO18 IMX8QXP_FLEXCAN1_TX 4 -#define IMX8QXP_FLEXCAN2_RX_ADMA_FLEXCAN2_RX IMX8QXP_FLEXCAN2_RX 0 -#define IMX8QXP_FLEXCAN2_RX_ADMA_SAI3_RXD IMX8QXP_FLEXCAN2_RX 1 -#define IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX IMX8QXP_FLEXCAN2_RX 2 -#define IMX8QXP_FLEXCAN2_RX_ADMA_SAI1_RXFS IMX8QXP_FLEXCAN2_RX 3 -#define IMX8QXP_FLEXCAN2_RX_LSIO_GPIO1_IO19 IMX8QXP_FLEXCAN2_RX 4 -#define IMX8QXP_FLEXCAN2_TX_ADMA_FLEXCAN2_TX IMX8QXP_FLEXCAN2_TX 0 -#define IMX8QXP_FLEXCAN2_TX_ADMA_SAI3_RXFS IMX8QXP_FLEXCAN2_TX 1 -#define IMX8QXP_FLEXCAN2_TX_ADMA_UART3_TX IMX8QXP_FLEXCAN2_TX 2 -#define IMX8QXP_FLEXCAN2_TX_ADMA_SAI1_RXC IMX8QXP_FLEXCAN2_TX 3 -#define IMX8QXP_FLEXCAN2_TX_LSIO_GPIO1_IO20 IMX8QXP_FLEXCAN2_TX 4 -#define IMX8QXP_UART0_RX_ADMA_UART0_RX IMX8QXP_UART0_RX 0 -#define IMX8QXP_UART0_RX_ADMA_MQS_R IMX8QXP_UART0_RX 1 -#define IMX8QXP_UART0_RX_ADMA_FLEXCAN0_RX IMX8QXP_UART0_RX 2 -#define IMX8QXP_UART0_RX_LSIO_GPIO1_IO21 IMX8QXP_UART0_RX 4 -#define IMX8QXP_UART0_TX_ADMA_UART0_TX IMX8QXP_UART0_TX 0 -#define IMX8QXP_UART0_TX_ADMA_MQS_L IMX8QXP_UART0_TX 1 -#define IMX8QXP_UART0_TX_ADMA_FLEXCAN0_TX IMX8QXP_UART0_TX 2 -#define IMX8QXP_UART0_TX_LSIO_GPIO1_IO22 IMX8QXP_UART0_TX 4 -#define IMX8QXP_UART2_TX_ADMA_UART2_TX IMX8QXP_UART2_TX 0 -#define IMX8QXP_UART2_TX_ADMA_FTM_CH1 IMX8QXP_UART2_TX 1 -#define IMX8QXP_UART2_TX_ADMA_FLEXCAN1_TX IMX8QXP_UART2_TX 2 -#define IMX8QXP_UART2_TX_LSIO_GPIO1_IO23 IMX8QXP_UART2_TX 4 -#define IMX8QXP_UART2_RX_ADMA_UART2_RX IMX8QXP_UART2_RX 0 -#define IMX8QXP_UART2_RX_ADMA_FTM_CH0 IMX8QXP_UART2_RX 1 -#define IMX8QXP_UART2_RX_ADMA_FLEXCAN1_RX IMX8QXP_UART2_RX 2 -#define IMX8QXP_UART2_RX_LSIO_GPIO1_IO24 IMX8QXP_UART2_RX 4 -#define IMX8QXP_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL IMX8QXP_MIPI_DSI0_I2C0_SCL 0 -#define IMX8QXP_MIPI_DSI0_I2C0_SCL_MIPI_DSI1_GPIO0_IO02 IMX8QXP_MIPI_DSI0_I2C0_SCL 1 -#define IMX8QXP_MIPI_DSI0_I2C0_SCL_LSIO_GPIO1_IO25 IMX8QXP_MIPI_DSI0_I2C0_SCL 4 -#define IMX8QXP_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA IMX8QXP_MIPI_DSI0_I2C0_SDA 0 -#define IMX8QXP_MIPI_DSI0_I2C0_SDA_MIPI_DSI1_GPIO0_IO03 IMX8QXP_MIPI_DSI0_I2C0_SDA 1 -#define IMX8QXP_MIPI_DSI0_I2C0_SDA_LSIO_GPIO1_IO26 IMX8QXP_MIPI_DSI0_I2C0_SDA 4 -#define IMX8QXP_MIPI_DSI0_GPIO0_00_MIPI_DSI0_GPIO0_IO00 IMX8QXP_MIPI_DSI0_GPIO0_00 0 -#define IMX8QXP_MIPI_DSI0_GPIO0_00_ADMA_I2C1_SCL IMX8QXP_MIPI_DSI0_GPIO0_00 1 -#define IMX8QXP_MIPI_DSI0_GPIO0_00_MIPI_DSI0_PWM0_OUT IMX8QXP_MIPI_DSI0_GPIO0_00 2 -#define IMX8QXP_MIPI_DSI0_GPIO0_00_LSIO_GPIO1_IO27 IMX8QXP_MIPI_DSI0_GPIO0_00 4 -#define IMX8QXP_MIPI_DSI0_GPIO0_01_MIPI_DSI0_GPIO0_IO01 IMX8QXP_MIPI_DSI0_GPIO0_01 0 -#define IMX8QXP_MIPI_DSI0_GPIO0_01_ADMA_I2C1_SDA IMX8QXP_MIPI_DSI0_GPIO0_01 1 -#define IMX8QXP_MIPI_DSI0_GPIO0_01_LSIO_GPIO1_IO28 IMX8QXP_MIPI_DSI0_GPIO0_01 4 -#define IMX8QXP_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL IMX8QXP_MIPI_DSI1_I2C0_SCL 0 -#define IMX8QXP_MIPI_DSI1_I2C0_SCL_MIPI_DSI0_GPIO0_IO02 IMX8QXP_MIPI_DSI1_I2C0_SCL 1 -#define IMX8QXP_MIPI_DSI1_I2C0_SCL_LSIO_GPIO1_IO29 IMX8QXP_MIPI_DSI1_I2C0_SCL 4 -#define IMX8QXP_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA IMX8QXP_MIPI_DSI1_I2C0_SDA 0 -#define IMX8QXP_MIPI_DSI1_I2C0_SDA_MIPI_DSI0_GPIO0_IO03 IMX8QXP_MIPI_DSI1_I2C0_SDA 1 -#define IMX8QXP_MIPI_DSI1_I2C0_SDA_LSIO_GPIO1_IO30 IMX8QXP_MIPI_DSI1_I2C0_SDA 4 -#define IMX8QXP_MIPI_DSI1_GPIO0_00_MIPI_DSI1_GPIO0_IO00 IMX8QXP_MIPI_DSI1_GPIO0_00 0 -#define IMX8QXP_MIPI_DSI1_GPIO0_00_ADMA_I2C2_SCL IMX8QXP_MIPI_DSI1_GPIO0_00 1 -#define IMX8QXP_MIPI_DSI1_GPIO0_00_MIPI_DSI1_PWM0_OUT IMX8QXP_MIPI_DSI1_GPIO0_00 2 -#define IMX8QXP_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO31 IMX8QXP_MIPI_DSI1_GPIO0_00 4 -#define IMX8QXP_MIPI_DSI1_GPIO0_01_MIPI_DSI1_GPIO0_IO01 IMX8QXP_MIPI_DSI1_GPIO0_01 0 -#define IMX8QXP_MIPI_DSI1_GPIO0_01_ADMA_I2C2_SDA IMX8QXP_MIPI_DSI1_GPIO0_01 1 -#define IMX8QXP_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00 IMX8QXP_MIPI_DSI1_GPIO0_01 4 -#define IMX8QXP_JTAG_TRST_B_SCU_JTAG_TRST_B IMX8QXP_JTAG_TRST_B 0 -#define IMX8QXP_JTAG_TRST_B_SCU_WDOG0_WDOG_OUT IMX8QXP_JTAG_TRST_B 1 -#define IMX8QXP_PMIC_I2C_SCL_SCU_PMIC_I2C_SCL IMX8QXP_PMIC_I2C_SCL 0 -#define IMX8QXP_PMIC_I2C_SCL_SCU_GPIO0_IOXX_PMIC_A35_ON IMX8QXP_PMIC_I2C_SCL 1 -#define IMX8QXP_PMIC_I2C_SCL_LSIO_GPIO2_IO01 IMX8QXP_PMIC_I2C_SCL 4 -#define IMX8QXP_PMIC_I2C_SDA_SCU_PMIC_I2C_SDA IMX8QXP_PMIC_I2C_SDA 0 -#define IMX8QXP_PMIC_I2C_SDA_SCU_GPIO0_IOXX_PMIC_GPU_ON IMX8QXP_PMIC_I2C_SDA 1 -#define IMX8QXP_PMIC_I2C_SDA_LSIO_GPIO2_IO02 IMX8QXP_PMIC_I2C_SDA 4 -#define IMX8QXP_PMIC_INT_B_SCU_DIMX8QXPMIC_INT_B IMX8QXP_PMIC_INT_B 0 -#define IMX8QXP_SCU_GPIO0_00_SCU_GPIO0_IO00 IMX8QXP_SCU_GPIO0_00 0 -#define IMX8QXP_SCU_GPIO0_00_SCU_UART0_RX IMX8QXP_SCU_GPIO0_00 1 -#define IMX8QXP_SCU_GPIO0_00_M40_UART0_RX IMX8QXP_SCU_GPIO0_00 2 -#define IMX8QXP_SCU_GPIO0_00_ADMA_UART3_RX IMX8QXP_SCU_GPIO0_00 3 -#define IMX8QXP_SCU_GPIO0_00_LSIO_GPIO2_IO03 IMX8QXP_SCU_GPIO0_00 4 -#define IMX8QXP_SCU_GPIO0_01_SCU_GPIO0_IO01 IMX8QXP_SCU_GPIO0_01 0 -#define IMX8QXP_SCU_GPIO0_01_SCU_UART0_TX IMX8QXP_SCU_GPIO0_01 1 -#define IMX8QXP_SCU_GPIO0_01_M40_UART0_TX IMX8QXP_SCU_GPIO0_01 2 -#define IMX8QXP_SCU_GPIO0_01_ADMA_UART3_TX IMX8QXP_SCU_GPIO0_01 3 -#define IMX8QXP_SCU_GPIO0_01_SCU_WDOG0_WDOG_OUT IMX8QXP_SCU_GPIO0_01 4 -#define IMX8QXP_SCU_PMIC_STANDBY_SCU_DIMX8QXPMIC_STANDBY IMX8QXP_SCU_PMIC_STANDBY 0 -#define IMX8QXP_SCU_BOOT_MODE0_SCU_DSC_BOOT_MODE0 IMX8QXP_SCU_BOOT_MODE0 0 -#define IMX8QXP_SCU_BOOT_MODE1_SCU_DSC_BOOT_MODE1 IMX8QXP_SCU_BOOT_MODE1 0 -#define IMX8QXP_SCU_BOOT_MODE2_SCU_DSC_BOOT_MODE2 IMX8QXP_SCU_BOOT_MODE2 0 -#define IMX8QXP_SCU_BOOT_MODE2_SCU_PMIC_I2C_SDA IMX8QXP_SCU_BOOT_MODE2 1 -#define IMX8QXP_SCU_BOOT_MODE3_SCU_DSC_BOOT_MODE3 IMX8QXP_SCU_BOOT_MODE3 0 -#define IMX8QXP_SCU_BOOT_MODE3_SCU_PMIC_I2C_SCL IMX8QXP_SCU_BOOT_MODE3 1 -#define IMX8QXP_SCU_BOOT_MODE3_SCU_DSC_RTC_CLOCK_OUTPUT_32K IMX8QXP_SCU_BOOT_MODE3 3 -#define IMX8QXP_CSI_D00_CI_PI_D02 IMX8QXP_CSI_D00 0 -#define IMX8QXP_CSI_D00_ADMA_SAI0_RXC IMX8QXP_CSI_D00 2 -#define IMX8QXP_CSI_D01_CI_PI_D03 IMX8QXP_CSI_D01 0 -#define IMX8QXP_CSI_D01_ADMA_SAI0_RXD IMX8QXP_CSI_D01 2 -#define IMX8QXP_CSI_D02_CI_PI_D04 IMX8QXP_CSI_D02 0 -#define IMX8QXP_CSI_D02_ADMA_SAI0_RXFS IMX8QXP_CSI_D02 2 -#define IMX8QXP_CSI_D03_CI_PI_D05 IMX8QXP_CSI_D03 0 -#define IMX8QXP_CSI_D03_ADMA_SAI2_RXC IMX8QXP_CSI_D03 2 -#define IMX8QXP_CSI_D04_CI_PI_D06 IMX8QXP_CSI_D04 0 -#define IMX8QXP_CSI_D04_ADMA_SAI2_RXD IMX8QXP_CSI_D04 2 -#define IMX8QXP_CSI_D05_CI_PI_D07 IMX8QXP_CSI_D05 0 -#define IMX8QXP_CSI_D05_ADMA_SAI2_RXFS IMX8QXP_CSI_D05 2 -#define IMX8QXP_CSI_D06_CI_PI_D08 IMX8QXP_CSI_D06 0 -#define IMX8QXP_CSI_D06_ADMA_SAI3_RXC IMX8QXP_CSI_D06 2 -#define IMX8QXP_CSI_D07_CI_PI_D09 IMX8QXP_CSI_D07 0 -#define IMX8QXP_CSI_D07_ADMA_SAI3_RXD IMX8QXP_CSI_D07 2 -#define IMX8QXP_CSI_HSYNC_CI_PI_HSYNC IMX8QXP_CSI_HSYNC 0 -#define IMX8QXP_CSI_HSYNC_CI_PI_D00 IMX8QXP_CSI_HSYNC 1 -#define IMX8QXP_CSI_HSYNC_ADMA_SAI3_RXFS IMX8QXP_CSI_HSYNC 2 -#define IMX8QXP_CSI_VSYNC_CI_PI_VSYNC IMX8QXP_CSI_VSYNC 0 -#define IMX8QXP_CSI_VSYNC_CI_PI_D01 IMX8QXP_CSI_VSYNC 1 -#define IMX8QXP_CSI_PCLK_CI_PI_PCLK IMX8QXP_CSI_PCLK 0 -#define IMX8QXP_CSI_PCLK_MIPI_CSI0_I2C0_SCL IMX8QXP_CSI_PCLK 1 -#define IMX8QXP_CSI_PCLK_ADMA_SPI1_SCK IMX8QXP_CSI_PCLK 3 -#define IMX8QXP_CSI_PCLK_LSIO_GPIO3_IO00 IMX8QXP_CSI_PCLK 4 -#define IMX8QXP_CSI_MCLK_CI_PI_MCLK IMX8QXP_CSI_MCLK 0 -#define IMX8QXP_CSI_MCLK_MIPI_CSI0_I2C0_SDA IMX8QXP_CSI_MCLK 1 -#define IMX8QXP_CSI_MCLK_ADMA_SPI1_SDO IMX8QXP_CSI_MCLK 3 -#define IMX8QXP_CSI_MCLK_LSIO_GPIO3_IO01 IMX8QXP_CSI_MCLK 4 -#define IMX8QXP_CSI_EN_CI_PI_EN IMX8QXP_CSI_EN 0 -#define IMX8QXP_CSI_EN_CI_PI_I2C_SCL IMX8QXP_CSI_EN 1 -#define IMX8QXP_CSI_EN_ADMA_I2C3_SCL IMX8QXP_CSI_EN 2 -#define IMX8QXP_CSI_EN_ADMA_SPI1_SDI IMX8QXP_CSI_EN 3 -#define IMX8QXP_CSI_EN_LSIO_GPIO3_IO02 IMX8QXP_CSI_EN 4 -#define IMX8QXP_CSI_RESET_CI_PI_RESET IMX8QXP_CSI_RESET 0 -#define IMX8QXP_CSI_RESET_CI_PI_I2C_SDA IMX8QXP_CSI_RESET 1 -#define IMX8QXP_CSI_RESET_ADMA_I2C3_SDA IMX8QXP_CSI_RESET 2 -#define IMX8QXP_CSI_RESET_ADMA_SPI1_CS0 IMX8QXP_CSI_RESET 3 -#define IMX8QXP_CSI_RESET_LSIO_GPIO3_IO03 IMX8QXP_CSI_RESET 4 -#define IMX8QXP_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT IMX8QXP_MIPI_CSI0_MCLK_OUT 0 -#define IMX8QXP_MIPI_CSI0_MCLK_OUT_LSIO_GPIO3_IO04 IMX8QXP_MIPI_CSI0_MCLK_OUT 4 -#define IMX8QXP_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL IMX8QXP_MIPI_CSI0_I2C0_SCL 0 -#define IMX8QXP_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_GPIO0_IO02 IMX8QXP_MIPI_CSI0_I2C0_SCL 1 -#define IMX8QXP_MIPI_CSI0_I2C0_SCL_LSIO_GPIO3_IO05 IMX8QXP_MIPI_CSI0_I2C0_SCL 4 -#define IMX8QXP_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA IMX8QXP_MIPI_CSI0_I2C0_SDA 0 -#define IMX8QXP_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_GPIO0_IO03 IMX8QXP_MIPI_CSI0_I2C0_SDA 1 -#define IMX8QXP_MIPI_CSI0_I2C0_SDA_LSIO_GPIO3_IO06 IMX8QXP_MIPI_CSI0_I2C0_SDA 4 -#define IMX8QXP_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_IO01 IMX8QXP_MIPI_CSI0_GPIO0_01 0 -#define IMX8QXP_MIPI_CSI0_GPIO0_01_ADMA_I2C0_SDA IMX8QXP_MIPI_CSI0_GPIO0_01 1 -#define IMX8QXP_MIPI_CSI0_GPIO0_01_LSIO_GPIO3_IO07 IMX8QXP_MIPI_CSI0_GPIO0_01 4 -#define IMX8QXP_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_IO00 IMX8QXP_MIPI_CSI0_GPIO0_00 0 -#define IMX8QXP_MIPI_CSI0_GPIO0_00_ADMA_I2C0_SCL IMX8QXP_MIPI_CSI0_GPIO0_00 1 -#define IMX8QXP_MIPI_CSI0_GPIO0_00_LSIO_GPIO3_IO08 IMX8QXP_MIPI_CSI0_GPIO0_00 4 -#define IMX8QXP_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 IMX8QXP_QSPI0A_DATA0 0 -#define IMX8QXP_QSPI0A_DATA0_LSIO_GPIO3_IO09 IMX8QXP_QSPI0A_DATA0 4 -#define IMX8QXP_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 IMX8QXP_QSPI0A_DATA1 0 -#define IMX8QXP_QSPI0A_DATA1_LSIO_GPIO3_IO10 IMX8QXP_QSPI0A_DATA1 4 -#define IMX8QXP_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 IMX8QXP_QSPI0A_DATA2 0 -#define IMX8QXP_QSPI0A_DATA2_LSIO_GPIO3_IO11 IMX8QXP_QSPI0A_DATA2 4 -#define IMX8QXP_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 IMX8QXP_QSPI0A_DATA3 0 -#define IMX8QXP_QSPI0A_DATA3_LSIO_GPIO3_IO12 IMX8QXP_QSPI0A_DATA3 4 -#define IMX8QXP_QSPI0A_DQS_LSIO_QSPI0A_DQS IMX8QXP_QSPI0A_DQS 0 -#define IMX8QXP_QSPI0A_DQS_LSIO_GPIO3_IO13 IMX8QXP_QSPI0A_DQS 4 -#define IMX8QXP_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B IMX8QXP_QSPI0A_SS0_B 0 -#define IMX8QXP_QSPI0A_SS0_B_LSIO_GPIO3_IO14 IMX8QXP_QSPI0A_SS0_B 4 -#define IMX8QXP_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B IMX8QXP_QSPI0A_SS1_B 0 -#define IMX8QXP_QSPI0A_SS1_B_LSIO_GPIO3_IO15 IMX8QXP_QSPI0A_SS1_B 4 -#define IMX8QXP_QSPI0A_SCLK_LSIO_QSPI0A_SCLK IMX8QXP_QSPI0A_SCLK 0 -#define IMX8QXP_QSPI0A_SCLK_LSIO_GPIO3_IO16 IMX8QXP_QSPI0A_SCLK 4 -#define IMX8QXP_QSPI0B_SCLK_LSIO_QSPI0B_SCLK IMX8QXP_QSPI0B_SCLK 0 -#define IMX8QXP_QSPI0B_SCLK_LSIO_QSPI1A_SCLK IMX8QXP_QSPI0B_SCLK 1 -#define IMX8QXP_QSPI0B_SCLK_LSIO_KPP0_COL0 IMX8QXP_QSPI0B_SCLK 2 -#define IMX8QXP_QSPI0B_SCLK_LSIO_GPIO3_IO17 IMX8QXP_QSPI0B_SCLK 4 -#define IMX8QXP_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 IMX8QXP_QSPI0B_DATA0 0 -#define IMX8QXP_QSPI0B_DATA0_LSIO_QSPI1A_DATA0 IMX8QXP_QSPI0B_DATA0 1 -#define IMX8QXP_QSPI0B_DATA0_LSIO_KPP0_COL1 IMX8QXP_QSPI0B_DATA0 2 -#define IMX8QXP_QSPI0B_DATA0_LSIO_GPIO3_IO18 IMX8QXP_QSPI0B_DATA0 4 -#define IMX8QXP_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 IMX8QXP_QSPI0B_DATA1 0 -#define IMX8QXP_QSPI0B_DATA1_LSIO_QSPI1A_DATA1 IMX8QXP_QSPI0B_DATA1 1 -#define IMX8QXP_QSPI0B_DATA1_LSIO_KPP0_COL2 IMX8QXP_QSPI0B_DATA1 2 -#define IMX8QXP_QSPI0B_DATA1_LSIO_GPIO3_IO19 IMX8QXP_QSPI0B_DATA1 4 -#define IMX8QXP_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 IMX8QXP_QSPI0B_DATA2 0 -#define IMX8QXP_QSPI0B_DATA2_LSIO_QSPI1A_DATA2 IMX8QXP_QSPI0B_DATA2 1 -#define IMX8QXP_QSPI0B_DATA2_LSIO_KPP0_COL3 IMX8QXP_QSPI0B_DATA2 2 -#define IMX8QXP_QSPI0B_DATA2_LSIO_GPIO3_IO20 IMX8QXP_QSPI0B_DATA2 4 -#define IMX8QXP_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 IMX8QXP_QSPI0B_DATA3 0 -#define IMX8QXP_QSPI0B_DATA3_LSIO_QSPI1A_DATA3 IMX8QXP_QSPI0B_DATA3 1 -#define IMX8QXP_QSPI0B_DATA3_LSIO_KPP0_ROW0 IMX8QXP_QSPI0B_DATA3 2 -#define IMX8QXP_QSPI0B_DATA3_LSIO_GPIO3_IO21 IMX8QXP_QSPI0B_DATA3 4 -#define IMX8QXP_QSPI0B_DQS_LSIO_QSPI0B_DQS IMX8QXP_QSPI0B_DQS 0 -#define IMX8QXP_QSPI0B_DQS_LSIO_QSPI1A_DQS IMX8QXP_QSPI0B_DQS 1 -#define IMX8QXP_QSPI0B_DQS_LSIO_KPP0_ROW1 IMX8QXP_QSPI0B_DQS 2 -#define IMX8QXP_QSPI0B_DQS_LSIO_GPIO3_IO22 IMX8QXP_QSPI0B_DQS 4 -#define IMX8QXP_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B IMX8QXP_QSPI0B_SS0_B 0 -#define IMX8QXP_QSPI0B_SS0_B_LSIO_QSPI1A_SS0_B IMX8QXP_QSPI0B_SS0_B 1 -#define IMX8QXP_QSPI0B_SS0_B_LSIO_KPP0_ROW2 IMX8QXP_QSPI0B_SS0_B 2 -#define IMX8QXP_QSPI0B_SS0_B_LSIO_GPIO3_IO23 IMX8QXP_QSPI0B_SS0_B 4 -#define IMX8QXP_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B IMX8QXP_QSPI0B_SS1_B 0 -#define IMX8QXP_QSPI0B_SS1_B_LSIO_QSPI1A_SS1_B IMX8QXP_QSPI0B_SS1_B 1 -#define IMX8QXP_QSPI0B_SS1_B_LSIO_KPP0_ROW3 IMX8QXP_QSPI0B_SS1_B 2 -#define IMX8QXP_QSPI0B_SS1_B_LSIO_GPIO3_IO24 IMX8QXP_QSPI0B_SS1_B 4 - -#endif /* _IMX8QXP_PADS_H */ diff --git a/sys/gnu/dts/include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h b/sys/gnu/dts/include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h deleted file mode 100644 index 20f43404cac..00000000000 --- a/sys/gnu/dts/include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * pinctrl-tegra-io-pad.h: Tegra I/O pad source voltage configuration constants - * pinctrl bindings. - * - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * Author: Aapo Vienamo - */ - -#ifndef _DT_BINDINGS_PINCTRL_TEGRA_IO_PAD_H -#define _DT_BINDINGS_PINCTRL_TEGRA_IO_PAD_H - -/* Voltage levels of the I/O pad's source rail */ -#define TEGRA_IO_PAD_VOLTAGE_1V8 0 -#define TEGRA_IO_PAD_VOLTAGE_3V3 1 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/pinctrl/pinctrl-tegra-xusb.h b/sys/gnu/dts/include/dt-bindings/pinctrl/pinctrl-tegra-xusb.h deleted file mode 100644 index ac63c399b4b..00000000000 --- a/sys/gnu/dts/include/dt-bindings/pinctrl/pinctrl-tegra-xusb.h +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _DT_BINDINGS_PINCTRL_TEGRA_XUSB_H -#define _DT_BINDINGS_PINCTRL_TEGRA_XUSB_H 1 - -#define TEGRA_XUSB_PADCTL_PCIE 0 -#define TEGRA_XUSB_PADCTL_SATA 1 - -#endif /* _DT_BINDINGS_PINCTRL_TEGRA_XUSB_H */ diff --git a/sys/gnu/dts/include/dt-bindings/pinctrl/pinctrl-tegra.h b/sys/gnu/dts/include/dt-bindings/pinctrl/pinctrl-tegra.h deleted file mode 100644 index d9b18bf2649..00000000000 --- a/sys/gnu/dts/include/dt-bindings/pinctrl/pinctrl-tegra.h +++ /dev/null @@ -1,37 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * This header provides constants for Tegra pinctrl bindings. - * - * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. - * - * Author: Laxman Dewangan - */ - -#ifndef _DT_BINDINGS_PINCTRL_TEGRA_H -#define _DT_BINDINGS_PINCTRL_TEGRA_H - -/* - * Enable/disable for diffeent dt properties. This is applicable for - * properties nvidia,enable-input, nvidia,tristate, nvidia,open-drain, - * nvidia,lock, nvidia,rcv-sel, nvidia,high-speed-mode, nvidia,schmitt. - */ -#define TEGRA_PIN_DISABLE 0 -#define TEGRA_PIN_ENABLE 1 - -#define TEGRA_PIN_PULL_NONE 0 -#define TEGRA_PIN_PULL_DOWN 1 -#define TEGRA_PIN_PULL_UP 2 - -/* Low power mode driver */ -#define TEGRA_PIN_LP_DRIVE_DIV_8 0 -#define TEGRA_PIN_LP_DRIVE_DIV_4 1 -#define TEGRA_PIN_LP_DRIVE_DIV_2 2 -#define TEGRA_PIN_LP_DRIVE_DIV_1 3 - -/* Rising/Falling slew rate */ -#define TEGRA_PIN_SLEW_RATE_FASTEST 0 -#define TEGRA_PIN_SLEW_RATE_FAST 1 -#define TEGRA_PIN_SLEW_RATE_SLOW 2 -#define TEGRA_PIN_SLEW_RATE_SLOWEST 3 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/pinctrl/qcom,pmic-gpio.h b/sys/gnu/dts/include/dt-bindings/pinctrl/qcom,pmic-gpio.h deleted file mode 100644 index e5df5ce45a0..00000000000 --- a/sys/gnu/dts/include/dt-bindings/pinctrl/qcom,pmic-gpio.h +++ /dev/null @@ -1,164 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides constants for the Qualcomm PMIC GPIO binding. - */ - -#ifndef _DT_BINDINGS_PINCTRL_QCOM_PMIC_GPIO_H -#define _DT_BINDINGS_PINCTRL_QCOM_PMIC_GPIO_H - -#define PMIC_GPIO_PULL_UP_30 0 -#define PMIC_GPIO_PULL_UP_1P5 1 -#define PMIC_GPIO_PULL_UP_31P5 2 -#define PMIC_GPIO_PULL_UP_1P5_30 3 - -#define PMIC_GPIO_STRENGTH_NO 0 -#define PMIC_GPIO_STRENGTH_HIGH 1 -#define PMIC_GPIO_STRENGTH_MED 2 -#define PMIC_GPIO_STRENGTH_LOW 3 - -/* - * Note: PM8018 GPIO3 and GPIO4 are supporting - * only S3 and L2 options (1.8V) - */ -#define PM8018_GPIO_L6 0 -#define PM8018_GPIO_L5 1 -#define PM8018_GPIO_S3 2 -#define PM8018_GPIO_L14 3 -#define PM8018_GPIO_L2 4 -#define PM8018_GPIO_L4 5 -#define PM8018_GPIO_VDD 6 - -/* - * Note: PM8038 GPIO7 and GPIO8 are supporting - * only L11 and L4 options (1.8V) - */ -#define PM8038_GPIO_VPH 0 -#define PM8038_GPIO_BB 1 -#define PM8038_GPIO_L11 2 -#define PM8038_GPIO_L15 3 -#define PM8038_GPIO_L4 4 -#define PM8038_GPIO_L3 5 -#define PM8038_GPIO_L17 6 - -#define PM8058_GPIO_VPH 0 -#define PM8058_GPIO_BB 1 -#define PM8058_GPIO_S3 2 -#define PM8058_GPIO_L3 3 -#define PM8058_GPIO_L7 4 -#define PM8058_GPIO_L6 5 -#define PM8058_GPIO_L5 6 -#define PM8058_GPIO_L2 7 - -/* - * Note: PM8916 GPIO1 and GPIO2 are supporting - * only L2(1.15V) and L5(1.8V) options - */ -#define PM8916_GPIO_VPH 0 -#define PM8916_GPIO_L2 2 -#define PM8916_GPIO_L5 3 - -#define PM8917_GPIO_VPH 0 -#define PM8917_GPIO_S4 2 -#define PM8917_GPIO_L15 3 -#define PM8917_GPIO_L4 4 -#define PM8917_GPIO_L3 5 -#define PM8917_GPIO_L17 6 - -#define PM8921_GPIO_VPH 0 -#define PM8921_GPIO_BB 1 -#define PM8921_GPIO_S4 2 -#define PM8921_GPIO_L15 3 -#define PM8921_GPIO_L4 4 -#define PM8921_GPIO_L3 5 -#define PM8921_GPIO_L17 6 - -/* - * Note: PM8941 gpios from 15 to 18 are supporting - * only S3 and L6 options (1.8V) - */ -#define PM8941_GPIO_VPH 0 -#define PM8941_GPIO_L1 1 -#define PM8941_GPIO_S3 2 -#define PM8941_GPIO_L6 3 - -/* - * Note: PMA8084 gpios from 15 to 18 are supporting - * only S4 and L6 options (1.8V) - */ -#define PMA8084_GPIO_VPH 0 -#define PMA8084_GPIO_L1 1 -#define PMA8084_GPIO_S4 2 -#define PMA8084_GPIO_L6 3 - -#define PM8994_GPIO_VPH 0 -#define PM8994_GPIO_S4 2 -#define PM8994_GPIO_L12 3 - -/* To be used with "function" */ -#define PMIC_GPIO_FUNC_NORMAL "normal" -#define PMIC_GPIO_FUNC_PAIRED "paired" -#define PMIC_GPIO_FUNC_FUNC1 "func1" -#define PMIC_GPIO_FUNC_FUNC2 "func2" -#define PMIC_GPIO_FUNC_FUNC3 "func3" -#define PMIC_GPIO_FUNC_FUNC4 "func4" -#define PMIC_GPIO_FUNC_DTEST1 "dtest1" -#define PMIC_GPIO_FUNC_DTEST2 "dtest2" -#define PMIC_GPIO_FUNC_DTEST3 "dtest3" -#define PMIC_GPIO_FUNC_DTEST4 "dtest4" - -#define PM8038_GPIO1_2_LPG_DRV PMIC_GPIO_FUNC_FUNC1 -#define PM8038_GPIO3_5V_BOOST_EN PMIC_GPIO_FUNC_FUNC1 -#define PM8038_GPIO4_SSBI_ALT_CLK PMIC_GPIO_FUNC_FUNC1 -#define PM8038_GPIO5_6_EXT_REG_EN PMIC_GPIO_FUNC_FUNC1 -#define PM8038_GPIO10_11_EXT_REG_EN PMIC_GPIO_FUNC_FUNC1 -#define PM8038_GPIO6_7_CLK PMIC_GPIO_FUNC_FUNC1 -#define PM8038_GPIO9_BAT_ALRM_OUT PMIC_GPIO_FUNC_FUNC1 -#define PM8038_GPIO6_12_KYPD_DRV PMIC_GPIO_FUNC_FUNC2 - -#define PM8058_GPIO7_8_MP3_CLK PMIC_GPIO_FUNC_FUNC1 -#define PM8058_GPIO7_8_BCLK_19P2MHZ PMIC_GPIO_FUNC_FUNC2 -#define PM8058_GPIO9_26_KYPD_DRV PMIC_GPIO_FUNC_FUNC1 -#define PM8058_GPIO21_23_UART_TX PMIC_GPIO_FUNC_FUNC2 -#define PM8058_GPIO24_26_LPG_DRV PMIC_GPIO_FUNC_FUNC2 -#define PM8058_GPIO33_BCLK_19P2MHZ PMIC_GPIO_FUNC_FUNC1 -#define PM8058_GPIO34_35_MP3_CLK PMIC_GPIO_FUNC_FUNC1 -#define PM8058_GPIO36_BCLK_19P2MHZ PMIC_GPIO_FUNC_FUNC1 -#define PM8058_GPIO37_UPL_OUT PMIC_GPIO_FUNC_FUNC1 -#define PM8058_GPIO37_UART_M_RX PMIC_GPIO_FUNC_FUNC2 -#define PM8058_GPIO38_XO_SLEEP_CLK PMIC_GPIO_FUNC_FUNC1 -#define PM8058_GPIO38_39_CLK_32KHZ PMIC_GPIO_FUNC_FUNC2 -#define PM8058_GPIO39_MP3_CLK PMIC_GPIO_FUNC_FUNC1 -#define PM8058_GPIO40_EXT_BB_EN PMIC_GPIO_FUNC_FUNC1 - -#define PM8916_GPIO1_BAT_ALRM_OUT PMIC_GPIO_FUNC_FUNC1 -#define PM8916_GPIO1_KEYP_DRV PMIC_GPIO_FUNC_FUNC2 -#define PM8916_GPIO2_DIV_CLK PMIC_GPIO_FUNC_FUNC1 -#define PM8916_GPIO2_SLEEP_CLK PMIC_GPIO_FUNC_FUNC2 -#define PM8916_GPIO3_KEYP_DRV PMIC_GPIO_FUNC_FUNC1 -#define PM8916_GPIO4_KEYP_DRV PMIC_GPIO_FUNC_FUNC2 - -#define PM8917_GPIO9_18_KEYP_DRV PMIC_GPIO_FUNC_FUNC1 -#define PM8917_GPIO20_BAT_ALRM_OUT PMIC_GPIO_FUNC_FUNC1 -#define PM8917_GPIO21_23_UART_TX PMIC_GPIO_FUNC_FUNC2 -#define PM8917_GPIO25_26_EXT_REG_EN PMIC_GPIO_FUNC_FUNC1 -#define PM8917_GPIO37_38_XO_SLEEP_CLK PMIC_GPIO_FUNC_FUNC1 -#define PM8917_GPIO37_38_MP3_CLK PMIC_GPIO_FUNC_FUNC2 - -#define PM8941_GPIO9_14_KYPD_DRV PMIC_GPIO_FUNC_FUNC1 -#define PM8941_GPIO15_18_DIV_CLK PMIC_GPIO_FUNC_FUNC1 -#define PM8941_GPIO15_18_SLEEP_CLK PMIC_GPIO_FUNC_FUNC2 -#define PM8941_GPIO23_26_KYPD_DRV PMIC_GPIO_FUNC_FUNC1 -#define PM8941_GPIO23_26_LPG_DRV_HI PMIC_GPIO_FUNC_FUNC2 -#define PM8941_GPIO31_BAT_ALRM_OUT PMIC_GPIO_FUNC_FUNC1 -#define PM8941_GPIO33_36_LPG_DRV_3D PMIC_GPIO_FUNC_FUNC1 -#define PM8941_GPIO33_36_LPG_DRV_HI PMIC_GPIO_FUNC_FUNC2 - -#define PMA8084_GPIO4_5_LPG_DRV PMIC_GPIO_FUNC_FUNC1 -#define PMA8084_GPIO7_10_LPG_DRV PMIC_GPIO_FUNC_FUNC1 -#define PMA8084_GPIO5_14_KEYP_DRV PMIC_GPIO_FUNC_FUNC2 -#define PMA8084_GPIO19_21_KEYP_DRV PMIC_GPIO_FUNC_FUNC2 -#define PMA8084_GPIO15_18_DIV_CLK PMIC_GPIO_FUNC_FUNC1 -#define PMA8084_GPIO15_18_SLEEP_CLK PMIC_GPIO_FUNC_FUNC2 -#define PMA8084_GPIO22_BAT_ALRM_OUT PMIC_GPIO_FUNC_FUNC1 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/pinctrl/qcom,pmic-mpp.h b/sys/gnu/dts/include/dt-bindings/pinctrl/qcom,pmic-mpp.h deleted file mode 100644 index 32e66ee7e83..00000000000 --- a/sys/gnu/dts/include/dt-bindings/pinctrl/qcom,pmic-mpp.h +++ /dev/null @@ -1,106 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides constants for the Qualcomm PMIC's - * Multi-Purpose Pin binding. - */ - -#ifndef _DT_BINDINGS_PINCTRL_QCOM_PMIC_MPP_H -#define _DT_BINDINGS_PINCTRL_QCOM_PMIC_MPP_H - -/* power-source */ - -/* Digital Input/Output: level [PM8058] */ -#define PM8058_MPP_VPH 0 -#define PM8058_MPP_S3 1 -#define PM8058_MPP_L2 2 -#define PM8058_MPP_L3 3 - -/* Digital Input/Output: level [PM8901] */ -#define PM8901_MPP_MSMIO 0 -#define PM8901_MPP_DIG 1 -#define PM8901_MPP_L5 2 -#define PM8901_MPP_S4 3 -#define PM8901_MPP_VPH 4 - -/* Digital Input/Output: level [PM8921] */ -#define PM8921_MPP_S4 1 -#define PM8921_MPP_L15 3 -#define PM8921_MPP_L17 4 -#define PM8921_MPP_VPH 7 - -/* Digital Input/Output: level [PM8821] */ -#define PM8821_MPP_1P8 0 -#define PM8821_MPP_VPH 7 - -/* Digital Input/Output: level [PM8018] */ -#define PM8018_MPP_L4 0 -#define PM8018_MPP_L14 1 -#define PM8018_MPP_S3 2 -#define PM8018_MPP_L6 3 -#define PM8018_MPP_L2 4 -#define PM8018_MPP_L5 5 -#define PM8018_MPP_VPH 7 - -/* Digital Input/Output: level [PM8038] */ -#define PM8038_MPP_L20 0 -#define PM8038_MPP_L11 1 -#define PM8038_MPP_L5 2 -#define PM8038_MPP_L15 3 -#define PM8038_MPP_L17 4 -#define PM8038_MPP_VPH 7 - -#define PM8841_MPP_VPH 0 -#define PM8841_MPP_S3 2 - -#define PM8916_MPP_VPH 0 -#define PM8916_MPP_L2 2 -#define PM8916_MPP_L5 3 - -#define PM8941_MPP_VPH 0 -#define PM8941_MPP_L1 1 -#define PM8941_MPP_S3 2 -#define PM8941_MPP_L6 3 - -#define PMA8084_MPP_VPH 0 -#define PMA8084_MPP_L1 1 -#define PMA8084_MPP_S4 2 -#define PMA8084_MPP_L6 3 - -#define PM8994_MPP_VPH 0 -/* Only supported for MPP_05-MPP_08 */ -#define PM8994_MPP_L19 1 -#define PM8994_MPP_S4 2 -#define PM8994_MPP_L12 3 - -/* - * Analog Input - Set the source for analog input. - * To be used with "qcom,amux-route" property - */ -#define PMIC_MPP_AMUX_ROUTE_CH5 0 -#define PMIC_MPP_AMUX_ROUTE_CH6 1 -#define PMIC_MPP_AMUX_ROUTE_CH7 2 -#define PMIC_MPP_AMUX_ROUTE_CH8 3 -#define PMIC_MPP_AMUX_ROUTE_ABUS1 4 -#define PMIC_MPP_AMUX_ROUTE_ABUS2 5 -#define PMIC_MPP_AMUX_ROUTE_ABUS3 6 -#define PMIC_MPP_AMUX_ROUTE_ABUS4 7 - -/* Analog Output: level */ -#define PMIC_MPP_AOUT_LVL_1V25 0 -#define PMIC_MPP_AOUT_LVL_1V25_2 1 -#define PMIC_MPP_AOUT_LVL_0V625 2 -#define PMIC_MPP_AOUT_LVL_0V3125 3 -#define PMIC_MPP_AOUT_LVL_MPP 4 -#define PMIC_MPP_AOUT_LVL_ABUS1 5 -#define PMIC_MPP_AOUT_LVL_ABUS2 6 -#define PMIC_MPP_AOUT_LVL_ABUS3 7 - -/* To be used with "function" */ -#define PMIC_MPP_FUNC_NORMAL "normal" -#define PMIC_MPP_FUNC_PAIRED "paired" -#define PMIC_MPP_FUNC_DTEST1 "dtest1" -#define PMIC_MPP_FUNC_DTEST2 "dtest2" -#define PMIC_MPP_FUNC_DTEST3 "dtest3" -#define PMIC_MPP_FUNC_DTEST4 "dtest4" - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/pinctrl/r7s72100-pinctrl.h b/sys/gnu/dts/include/dt-bindings/pinctrl/r7s72100-pinctrl.h deleted file mode 100644 index cdb95024688..00000000000 --- a/sys/gnu/dts/include/dt-bindings/pinctrl/r7s72100-pinctrl.h +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Defines macros and constants for Renesas RZ/A1 pin controller pin - * muxing functions. - */ -#ifndef __DT_BINDINGS_PINCTRL_RENESAS_RZA1_H -#define __DT_BINDINGS_PINCTRL_RENESAS_RZA1_H - -#define RZA1_PINS_PER_PORT 16 - -/* - * Create the pin index from its bank and position numbers and store in - * the upper 16 bits the alternate function identifier - */ -#define RZA1_PINMUX(b, p, f) ((b) * RZA1_PINS_PER_PORT + (p) | (f << 16)) - -#endif /* __DT_BINDINGS_PINCTRL_RENESAS_RZA1_H */ diff --git a/sys/gnu/dts/include/dt-bindings/pinctrl/r7s9210-pinctrl.h b/sys/gnu/dts/include/dt-bindings/pinctrl/r7s9210-pinctrl.h deleted file mode 100644 index 2d0c23e5d3a..00000000000 --- a/sys/gnu/dts/include/dt-bindings/pinctrl/r7s9210-pinctrl.h +++ /dev/null @@ -1,47 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Defines macros and constants for Renesas RZ/A2 pin controller pin - * muxing functions. - */ -#ifndef __DT_BINDINGS_PINCTRL_RENESAS_RZA2_H -#define __DT_BINDINGS_PINCTRL_RENESAS_RZA2_H - -#define RZA2_PINS_PER_PORT 8 - -/* Port names as labeled in the Hardware Manual */ -#define PORT0 0 -#define PORT1 1 -#define PORT2 2 -#define PORT3 3 -#define PORT4 4 -#define PORT5 5 -#define PORT6 6 -#define PORT7 7 -#define PORT8 8 -#define PORT9 9 -#define PORTA 10 -#define PORTB 11 -#define PORTC 12 -#define PORTD 13 -#define PORTE 14 -#define PORTF 15 -#define PORTG 16 -#define PORTH 17 -/* No I */ -#define PORTJ 18 -#define PORTK 19 -#define PORTL 20 -#define PORTM 21 /* Pins PM_0/1 are labeled JP_0/1 in HW manual */ - -/* - * Create the pin index from its bank and position numbers and store in - * the upper 16 bits the alternate function identifier - */ -#define RZA2_PINMUX(b, p, f) ((b) * RZA2_PINS_PER_PORT + (p) | (f << 16)) - -/* - * Convert a port and pin label to its global pin index - */ - #define RZA2_PIN(port, pin) ((port) * RZA2_PINS_PER_PORT + (pin)) - -#endif /* __DT_BINDINGS_PINCTRL_RENESAS_RZA2_H */ diff --git a/sys/gnu/dts/include/dt-bindings/pinctrl/rockchip.h b/sys/gnu/dts/include/dt-bindings/pinctrl/rockchip.h deleted file mode 100644 index 6d6bac1c26d..00000000000 --- a/sys/gnu/dts/include/dt-bindings/pinctrl/rockchip.h +++ /dev/null @@ -1,58 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Header providing constants for Rockchip pinctrl bindings. - * - * Copyright (c) 2013 MundoReader S.L. - * Author: Heiko Stuebner - */ - -#ifndef __DT_BINDINGS_ROCKCHIP_PINCTRL_H__ -#define __DT_BINDINGS_ROCKCHIP_PINCTRL_H__ - -#define RK_GPIO0 0 -#define RK_GPIO1 1 -#define RK_GPIO2 2 -#define RK_GPIO3 3 -#define RK_GPIO4 4 -#define RK_GPIO6 6 - -#define RK_PA0 0 -#define RK_PA1 1 -#define RK_PA2 2 -#define RK_PA3 3 -#define RK_PA4 4 -#define RK_PA5 5 -#define RK_PA6 6 -#define RK_PA7 7 -#define RK_PB0 8 -#define RK_PB1 9 -#define RK_PB2 10 -#define RK_PB3 11 -#define RK_PB4 12 -#define RK_PB5 13 -#define RK_PB6 14 -#define RK_PB7 15 -#define RK_PC0 16 -#define RK_PC1 17 -#define RK_PC2 18 -#define RK_PC3 19 -#define RK_PC4 20 -#define RK_PC5 21 -#define RK_PC6 22 -#define RK_PC7 23 -#define RK_PD0 24 -#define RK_PD1 25 -#define RK_PD2 26 -#define RK_PD3 27 -#define RK_PD4 28 -#define RK_PD5 29 -#define RK_PD6 30 -#define RK_PD7 31 - -#define RK_FUNC_GPIO 0 -#define RK_FUNC_1 1 /* deprecated */ -#define RK_FUNC_2 2 /* deprecated */ -#define RK_FUNC_3 3 /* deprecated */ -#define RK_FUNC_4 4 /* deprecated */ - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/pinctrl/rzn1-pinctrl.h b/sys/gnu/dts/include/dt-bindings/pinctrl/rzn1-pinctrl.h deleted file mode 100644 index 21d6cc4d59f..00000000000 --- a/sys/gnu/dts/include/dt-bindings/pinctrl/rzn1-pinctrl.h +++ /dev/null @@ -1,141 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Defines macros and constants for Renesas RZ/N1 pin controller pin - * muxing functions. - */ -#ifndef __DT_BINDINGS_RZN1_PINCTRL_H -#define __DT_BINDINGS_RZN1_PINCTRL_H - -#define RZN1_PINMUX(_gpio, _func) \ - (((_func) << 8) | (_gpio)) - -/* - * Given the different levels of muxing on the SoC, it was decided to - * 'linearize' them into one numerical space. So mux level 1, 2 and the MDIO - * muxes are all represented by one single value. - * - * You can derive the hardware value pretty easily too, as - * 0...9 are Level 1 - * 10...71 are Level 2. The Level 2 mux will be set to this - * value - RZN1_FUNC_L2_OFFSET, and the Level 1 mux will be - * set accordingly. - * 72...103 are for the 2 MDIO muxes. - */ -#define RZN1_FUNC_HIGHZ 0 -#define RZN1_FUNC_0L 1 -#define RZN1_FUNC_CLK_ETH_MII_RGMII_RMII 2 -#define RZN1_FUNC_CLK_ETH_NAND 3 -#define RZN1_FUNC_QSPI 4 -#define RZN1_FUNC_SDIO 5 -#define RZN1_FUNC_LCD 6 -#define RZN1_FUNC_LCD_E 7 -#define RZN1_FUNC_MSEBIM 8 -#define RZN1_FUNC_MSEBIS 9 -#define RZN1_FUNC_L2_OFFSET 10 /* I'm Special */ - -#define RZN1_FUNC_HIGHZ1 (RZN1_FUNC_L2_OFFSET + 0) -#define RZN1_FUNC_ETHERCAT (RZN1_FUNC_L2_OFFSET + 1) -#define RZN1_FUNC_SERCOS3 (RZN1_FUNC_L2_OFFSET + 2) -#define RZN1_FUNC_SDIO_E (RZN1_FUNC_L2_OFFSET + 3) -#define RZN1_FUNC_ETH_MDIO (RZN1_FUNC_L2_OFFSET + 4) -#define RZN1_FUNC_ETH_MDIO_E1 (RZN1_FUNC_L2_OFFSET + 5) -#define RZN1_FUNC_USB (RZN1_FUNC_L2_OFFSET + 6) -#define RZN1_FUNC_MSEBIM_E (RZN1_FUNC_L2_OFFSET + 7) -#define RZN1_FUNC_MSEBIS_E (RZN1_FUNC_L2_OFFSET + 8) -#define RZN1_FUNC_RSV (RZN1_FUNC_L2_OFFSET + 9) -#define RZN1_FUNC_RSV_E (RZN1_FUNC_L2_OFFSET + 10) -#define RZN1_FUNC_RSV_E1 (RZN1_FUNC_L2_OFFSET + 11) -#define RZN1_FUNC_UART0_I (RZN1_FUNC_L2_OFFSET + 12) -#define RZN1_FUNC_UART0_I_E (RZN1_FUNC_L2_OFFSET + 13) -#define RZN1_FUNC_UART1_I (RZN1_FUNC_L2_OFFSET + 14) -#define RZN1_FUNC_UART1_I_E (RZN1_FUNC_L2_OFFSET + 15) -#define RZN1_FUNC_UART2_I (RZN1_FUNC_L2_OFFSET + 16) -#define RZN1_FUNC_UART2_I_E (RZN1_FUNC_L2_OFFSET + 17) -#define RZN1_FUNC_UART0 (RZN1_FUNC_L2_OFFSET + 18) -#define RZN1_FUNC_UART0_E (RZN1_FUNC_L2_OFFSET + 19) -#define RZN1_FUNC_UART1 (RZN1_FUNC_L2_OFFSET + 20) -#define RZN1_FUNC_UART1_E (RZN1_FUNC_L2_OFFSET + 21) -#define RZN1_FUNC_UART2 (RZN1_FUNC_L2_OFFSET + 22) -#define RZN1_FUNC_UART2_E (RZN1_FUNC_L2_OFFSET + 23) -#define RZN1_FUNC_UART3 (RZN1_FUNC_L2_OFFSET + 24) -#define RZN1_FUNC_UART3_E (RZN1_FUNC_L2_OFFSET + 25) -#define RZN1_FUNC_UART4 (RZN1_FUNC_L2_OFFSET + 26) -#define RZN1_FUNC_UART4_E (RZN1_FUNC_L2_OFFSET + 27) -#define RZN1_FUNC_UART5 (RZN1_FUNC_L2_OFFSET + 28) -#define RZN1_FUNC_UART5_E (RZN1_FUNC_L2_OFFSET + 29) -#define RZN1_FUNC_UART6 (RZN1_FUNC_L2_OFFSET + 30) -#define RZN1_FUNC_UART6_E (RZN1_FUNC_L2_OFFSET + 31) -#define RZN1_FUNC_UART7 (RZN1_FUNC_L2_OFFSET + 32) -#define RZN1_FUNC_UART7_E (RZN1_FUNC_L2_OFFSET + 33) -#define RZN1_FUNC_SPI0_M (RZN1_FUNC_L2_OFFSET + 34) -#define RZN1_FUNC_SPI0_M_E (RZN1_FUNC_L2_OFFSET + 35) -#define RZN1_FUNC_SPI1_M (RZN1_FUNC_L2_OFFSET + 36) -#define RZN1_FUNC_SPI1_M_E (RZN1_FUNC_L2_OFFSET + 37) -#define RZN1_FUNC_SPI2_M (RZN1_FUNC_L2_OFFSET + 38) -#define RZN1_FUNC_SPI2_M_E (RZN1_FUNC_L2_OFFSET + 39) -#define RZN1_FUNC_SPI3_M (RZN1_FUNC_L2_OFFSET + 40) -#define RZN1_FUNC_SPI3_M_E (RZN1_FUNC_L2_OFFSET + 41) -#define RZN1_FUNC_SPI4_S (RZN1_FUNC_L2_OFFSET + 42) -#define RZN1_FUNC_SPI4_S_E (RZN1_FUNC_L2_OFFSET + 43) -#define RZN1_FUNC_SPI5_S (RZN1_FUNC_L2_OFFSET + 44) -#define RZN1_FUNC_SPI5_S_E (RZN1_FUNC_L2_OFFSET + 45) -#define RZN1_FUNC_SGPIO0_M (RZN1_FUNC_L2_OFFSET + 46) -#define RZN1_FUNC_SGPIO1_M (RZN1_FUNC_L2_OFFSET + 47) -#define RZN1_FUNC_GPIO (RZN1_FUNC_L2_OFFSET + 48) -#define RZN1_FUNC_CAN (RZN1_FUNC_L2_OFFSET + 49) -#define RZN1_FUNC_I2C (RZN1_FUNC_L2_OFFSET + 50) -#define RZN1_FUNC_SAFE (RZN1_FUNC_L2_OFFSET + 51) -#define RZN1_FUNC_PTO_PWM (RZN1_FUNC_L2_OFFSET + 52) -#define RZN1_FUNC_PTO_PWM1 (RZN1_FUNC_L2_OFFSET + 53) -#define RZN1_FUNC_PTO_PWM2 (RZN1_FUNC_L2_OFFSET + 54) -#define RZN1_FUNC_PTO_PWM3 (RZN1_FUNC_L2_OFFSET + 55) -#define RZN1_FUNC_PTO_PWM4 (RZN1_FUNC_L2_OFFSET + 56) -#define RZN1_FUNC_DELTA_SIGMA (RZN1_FUNC_L2_OFFSET + 57) -#define RZN1_FUNC_SGPIO2_M (RZN1_FUNC_L2_OFFSET + 58) -#define RZN1_FUNC_SGPIO3_M (RZN1_FUNC_L2_OFFSET + 59) -#define RZN1_FUNC_SGPIO4_S (RZN1_FUNC_L2_OFFSET + 60) -#define RZN1_FUNC_MAC_MTIP_SWITCH (RZN1_FUNC_L2_OFFSET + 61) - -#define RZN1_FUNC_MDIO_OFFSET (RZN1_FUNC_L2_OFFSET + 62) - -/* These are MDIO0 peripherals for the RZN1_FUNC_ETH_MDIO function */ -#define RZN1_FUNC_MDIO0_HIGHZ (RZN1_FUNC_MDIO_OFFSET + 0) -#define RZN1_FUNC_MDIO0_GMAC0 (RZN1_FUNC_MDIO_OFFSET + 1) -#define RZN1_FUNC_MDIO0_GMAC1 (RZN1_FUNC_MDIO_OFFSET + 2) -#define RZN1_FUNC_MDIO0_ECAT (RZN1_FUNC_MDIO_OFFSET + 3) -#define RZN1_FUNC_MDIO0_S3_MDIO0 (RZN1_FUNC_MDIO_OFFSET + 4) -#define RZN1_FUNC_MDIO0_S3_MDIO1 (RZN1_FUNC_MDIO_OFFSET + 5) -#define RZN1_FUNC_MDIO0_HWRTOS (RZN1_FUNC_MDIO_OFFSET + 6) -#define RZN1_FUNC_MDIO0_SWITCH (RZN1_FUNC_MDIO_OFFSET + 7) -/* These are MDIO0 peripherals for the RZN1_FUNC_ETH_MDIO_E1 function */ -#define RZN1_FUNC_MDIO0_E1_HIGHZ (RZN1_FUNC_MDIO_OFFSET + 8) -#define RZN1_FUNC_MDIO0_E1_GMAC0 (RZN1_FUNC_MDIO_OFFSET + 9) -#define RZN1_FUNC_MDIO0_E1_GMAC1 (RZN1_FUNC_MDIO_OFFSET + 10) -#define RZN1_FUNC_MDIO0_E1_ECAT (RZN1_FUNC_MDIO_OFFSET + 11) -#define RZN1_FUNC_MDIO0_E1_S3_MDIO0 (RZN1_FUNC_MDIO_OFFSET + 12) -#define RZN1_FUNC_MDIO0_E1_S3_MDIO1 (RZN1_FUNC_MDIO_OFFSET + 13) -#define RZN1_FUNC_MDIO0_E1_HWRTOS (RZN1_FUNC_MDIO_OFFSET + 14) -#define RZN1_FUNC_MDIO0_E1_SWITCH (RZN1_FUNC_MDIO_OFFSET + 15) - -/* These are MDIO1 peripherals for the RZN1_FUNC_ETH_MDIO function */ -#define RZN1_FUNC_MDIO1_HIGHZ (RZN1_FUNC_MDIO_OFFSET + 16) -#define RZN1_FUNC_MDIO1_GMAC0 (RZN1_FUNC_MDIO_OFFSET + 17) -#define RZN1_FUNC_MDIO1_GMAC1 (RZN1_FUNC_MDIO_OFFSET + 18) -#define RZN1_FUNC_MDIO1_ECAT (RZN1_FUNC_MDIO_OFFSET + 19) -#define RZN1_FUNC_MDIO1_S3_MDIO0 (RZN1_FUNC_MDIO_OFFSET + 20) -#define RZN1_FUNC_MDIO1_S3_MDIO1 (RZN1_FUNC_MDIO_OFFSET + 21) -#define RZN1_FUNC_MDIO1_HWRTOS (RZN1_FUNC_MDIO_OFFSET + 22) -#define RZN1_FUNC_MDIO1_SWITCH (RZN1_FUNC_MDIO_OFFSET + 23) -/* These are MDIO1 peripherals for the RZN1_FUNC_ETH_MDIO_E1 function */ -#define RZN1_FUNC_MDIO1_E1_HIGHZ (RZN1_FUNC_MDIO_OFFSET + 24) -#define RZN1_FUNC_MDIO1_E1_GMAC0 (RZN1_FUNC_MDIO_OFFSET + 25) -#define RZN1_FUNC_MDIO1_E1_GMAC1 (RZN1_FUNC_MDIO_OFFSET + 26) -#define RZN1_FUNC_MDIO1_E1_ECAT (RZN1_FUNC_MDIO_OFFSET + 27) -#define RZN1_FUNC_MDIO1_E1_S3_MDIO0 (RZN1_FUNC_MDIO_OFFSET + 28) -#define RZN1_FUNC_MDIO1_E1_S3_MDIO1 (RZN1_FUNC_MDIO_OFFSET + 29) -#define RZN1_FUNC_MDIO1_E1_HWRTOS (RZN1_FUNC_MDIO_OFFSET + 30) -#define RZN1_FUNC_MDIO1_E1_SWITCH (RZN1_FUNC_MDIO_OFFSET + 31) - -#define RZN1_FUNC_MAX (RZN1_FUNC_MDIO_OFFSET + 32) - -#endif /* __DT_BINDINGS_RZN1_PINCTRL_H */ diff --git a/sys/gnu/dts/include/dt-bindings/pinctrl/samsung.h b/sys/gnu/dts/include/dt-bindings/pinctrl/samsung.h deleted file mode 100644 index b1832506b92..00000000000 --- a/sys/gnu/dts/include/dt-bindings/pinctrl/samsung.h +++ /dev/null @@ -1,77 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Samsung's Exynos pinctrl bindings - * - * Copyright (c) 2016 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * Author: Krzysztof Kozlowski - */ - -#ifndef __DT_BINDINGS_PINCTRL_SAMSUNG_H__ -#define __DT_BINDINGS_PINCTRL_SAMSUNG_H__ - -#define EXYNOS_PIN_PULL_NONE 0 -#define EXYNOS_PIN_PULL_DOWN 1 -#define EXYNOS_PIN_PULL_UP 3 - -#define S3C64XX_PIN_PULL_NONE 0 -#define S3C64XX_PIN_PULL_DOWN 1 -#define S3C64XX_PIN_PULL_UP 2 - -/* Pin function in power down mode */ -#define EXYNOS_PIN_PDN_OUT0 0 -#define EXYNOS_PIN_PDN_OUT1 1 -#define EXYNOS_PIN_PDN_INPUT 2 -#define EXYNOS_PIN_PDN_PREV 3 - -/* Drive strengths for Exynos3250, Exynos4 (all) and Exynos5250 */ -#define EXYNOS4_PIN_DRV_LV1 0 -#define EXYNOS4_PIN_DRV_LV2 2 -#define EXYNOS4_PIN_DRV_LV3 1 -#define EXYNOS4_PIN_DRV_LV4 3 - -/* Drive strengths for Exynos5260 */ -#define EXYNOS5260_PIN_DRV_LV1 0 -#define EXYNOS5260_PIN_DRV_LV2 1 -#define EXYNOS5260_PIN_DRV_LV4 2 -#define EXYNOS5260_PIN_DRV_LV6 3 - -/* Drive strengths for Exynos5410, Exynos542x and Exynos5800 */ -#define EXYNOS5420_PIN_DRV_LV1 0 -#define EXYNOS5420_PIN_DRV_LV2 1 -#define EXYNOS5420_PIN_DRV_LV3 2 -#define EXYNOS5420_PIN_DRV_LV4 3 - -/* Drive strengths for Exynos5433 */ -#define EXYNOS5433_PIN_DRV_FAST_SR1 0 -#define EXYNOS5433_PIN_DRV_FAST_SR2 1 -#define EXYNOS5433_PIN_DRV_FAST_SR3 2 -#define EXYNOS5433_PIN_DRV_FAST_SR4 3 -#define EXYNOS5433_PIN_DRV_FAST_SR5 4 -#define EXYNOS5433_PIN_DRV_FAST_SR6 5 -#define EXYNOS5433_PIN_DRV_SLOW_SR1 8 -#define EXYNOS5433_PIN_DRV_SLOW_SR2 9 -#define EXYNOS5433_PIN_DRV_SLOW_SR3 0xa -#define EXYNOS5433_PIN_DRV_SLOW_SR4 0xb -#define EXYNOS5433_PIN_DRV_SLOW_SR5 0xc -#define EXYNOS5433_PIN_DRV_SLOW_SR6 0xf - -#define EXYNOS_PIN_FUNC_INPUT 0 -#define EXYNOS_PIN_FUNC_OUTPUT 1 -#define EXYNOS_PIN_FUNC_2 2 -#define EXYNOS_PIN_FUNC_3 3 -#define EXYNOS_PIN_FUNC_4 4 -#define EXYNOS_PIN_FUNC_5 5 -#define EXYNOS_PIN_FUNC_6 6 -#define EXYNOS_PIN_FUNC_EINT 0xf -#define EXYNOS_PIN_FUNC_F EXYNOS_PIN_FUNC_EINT - -/* Drive strengths for Exynos7 FSYS1 block */ -#define EXYNOS7_FSYS1_PIN_DRV_LV1 0 -#define EXYNOS7_FSYS1_PIN_DRV_LV2 4 -#define EXYNOS7_FSYS1_PIN_DRV_LV3 2 -#define EXYNOS7_FSYS1_PIN_DRV_LV4 6 -#define EXYNOS7_FSYS1_PIN_DRV_LV5 1 -#define EXYNOS7_FSYS1_PIN_DRV_LV6 5 - -#endif /* __DT_BINDINGS_PINCTRL_SAMSUNG_H__ */ diff --git a/sys/gnu/dts/include/dt-bindings/pinctrl/stm32-pinfunc.h b/sys/gnu/dts/include/dt-bindings/pinctrl/stm32-pinfunc.h deleted file mode 100644 index e6fb8ada3f4..00000000000 --- a/sys/gnu/dts/include/dt-bindings/pinctrl/stm32-pinfunc.h +++ /dev/null @@ -1,42 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ -/* - * Copyright (C) STMicroelectronics 2017 - All Rights Reserved - * Author: Torgue Alexandre for STMicroelectronics. - */ - -#ifndef _DT_BINDINGS_STM32_PINFUNC_H -#define _DT_BINDINGS_STM32_PINFUNC_H - -/* define PIN modes */ -#define GPIO 0x0 -#define AF0 0x1 -#define AF1 0x2 -#define AF2 0x3 -#define AF3 0x4 -#define AF4 0x5 -#define AF5 0x6 -#define AF6 0x7 -#define AF7 0x8 -#define AF8 0x9 -#define AF9 0xa -#define AF10 0xb -#define AF11 0xc -#define AF12 0xd -#define AF13 0xe -#define AF14 0xf -#define AF15 0x10 -#define ANALOG 0x11 - -/* define Pins number*/ -#define PIN_NO(port, line) (((port) - 'A') * 0x10 + (line)) - -#define STM32_PINMUX(port, line, mode) (((PIN_NO(port, line)) << 8) | (mode)) - -/* package information */ -#define STM32MP_PKG_AA 0x1 -#define STM32MP_PKG_AB 0x2 -#define STM32MP_PKG_AC 0x4 -#define STM32MP_PKG_AD 0x8 - -#endif /* _DT_BINDINGS_STM32_PINFUNC_H */ - diff --git a/sys/gnu/dts/include/dt-bindings/pinctrl/stm32f429-pinfunc.h b/sys/gnu/dts/include/dt-bindings/pinctrl/stm32f429-pinfunc.h deleted file mode 100644 index 9a5a028f0d0..00000000000 --- a/sys/gnu/dts/include/dt-bindings/pinctrl/stm32f429-pinfunc.h +++ /dev/null @@ -1,1240 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _DT_BINDINGS_STM32F429_PINFUNC_H -#define _DT_BINDINGS_STM32F429_PINFUNC_H - -#define STM32F429_PA0_FUNC_GPIO 0x0 -#define STM32F429_PA0_FUNC_TIM2_CH1_TIM2_ETR 0x2 -#define STM32F429_PA0_FUNC_TIM5_CH1 0x3 -#define STM32F429_PA0_FUNC_TIM8_ETR 0x4 -#define STM32F429_PA0_FUNC_USART2_CTS 0x8 -#define STM32F429_PA0_FUNC_UART4_TX 0x9 -#define STM32F429_PA0_FUNC_ETH_MII_CRS 0xc -#define STM32F429_PA0_FUNC_EVENTOUT 0x10 -#define STM32F429_PA0_FUNC_ANALOG 0x11 - -#define STM32F429_PA1_FUNC_GPIO 0x100 -#define STM32F429_PA1_FUNC_TIM2_CH2 0x102 -#define STM32F429_PA1_FUNC_TIM5_CH2 0x103 -#define STM32F429_PA1_FUNC_USART2_RTS 0x108 -#define STM32F429_PA1_FUNC_UART4_RX 0x109 -#define STM32F429_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK 0x10c -#define STM32F429_PA1_FUNC_EVENTOUT 0x110 -#define STM32F429_PA1_FUNC_ANALOG 0x111 - -#define STM32F429_PA2_FUNC_GPIO 0x200 -#define STM32F429_PA2_FUNC_TIM2_CH3 0x202 -#define STM32F429_PA2_FUNC_TIM5_CH3 0x203 -#define STM32F429_PA2_FUNC_TIM9_CH1 0x204 -#define STM32F429_PA2_FUNC_USART2_TX 0x208 -#define STM32F429_PA2_FUNC_ETH_MDIO 0x20c -#define STM32F429_PA2_FUNC_EVENTOUT 0x210 -#define STM32F429_PA2_FUNC_ANALOG 0x211 - -#define STM32F429_PA3_FUNC_GPIO 0x300 -#define STM32F429_PA3_FUNC_TIM2_CH4 0x302 -#define STM32F429_PA3_FUNC_TIM5_CH4 0x303 -#define STM32F429_PA3_FUNC_TIM9_CH2 0x304 -#define STM32F429_PA3_FUNC_USART2_RX 0x308 -#define STM32F429_PA3_FUNC_OTG_HS_ULPI_D0 0x30b -#define STM32F429_PA3_FUNC_ETH_MII_COL 0x30c -#define STM32F429_PA3_FUNC_LCD_B5 0x30f -#define STM32F429_PA3_FUNC_EVENTOUT 0x310 -#define STM32F429_PA3_FUNC_ANALOG 0x311 - -#define STM32F429_PA4_FUNC_GPIO 0x400 -#define STM32F429_PA4_FUNC_SPI1_NSS 0x406 -#define STM32F429_PA4_FUNC_SPI3_NSS_I2S3_WS 0x407 -#define STM32F429_PA4_FUNC_USART2_CK 0x408 -#define STM32F429_PA4_FUNC_OTG_HS_SOF 0x40d -#define STM32F429_PA4_FUNC_DCMI_HSYNC 0x40e -#define STM32F429_PA4_FUNC_LCD_VSYNC 0x40f -#define STM32F429_PA4_FUNC_EVENTOUT 0x410 -#define STM32F429_PA4_FUNC_ANALOG 0x411 - -#define STM32F429_PA5_FUNC_GPIO 0x500 -#define STM32F429_PA5_FUNC_TIM2_CH1_TIM2_ETR 0x502 -#define STM32F429_PA5_FUNC_TIM8_CH1N 0x504 -#define STM32F429_PA5_FUNC_SPI1_SCK 0x506 -#define STM32F429_PA5_FUNC_OTG_HS_ULPI_CK 0x50b -#define STM32F429_PA5_FUNC_EVENTOUT 0x510 -#define STM32F429_PA5_FUNC_ANALOG 0x511 - -#define STM32F429_PA6_FUNC_GPIO 0x600 -#define STM32F429_PA6_FUNC_TIM1_BKIN 0x602 -#define STM32F429_PA6_FUNC_TIM3_CH1 0x603 -#define STM32F429_PA6_FUNC_TIM8_BKIN 0x604 -#define STM32F429_PA6_FUNC_SPI1_MISO 0x606 -#define STM32F429_PA6_FUNC_TIM13_CH1 0x60a -#define STM32F429_PA6_FUNC_DCMI_PIXCLK 0x60e -#define STM32F429_PA6_FUNC_LCD_G2 0x60f -#define STM32F429_PA6_FUNC_EVENTOUT 0x610 -#define STM32F429_PA6_FUNC_ANALOG 0x611 - -#define STM32F429_PA7_FUNC_GPIO 0x700 -#define STM32F429_PA7_FUNC_TIM1_CH1N 0x702 -#define STM32F429_PA7_FUNC_TIM3_CH2 0x703 -#define STM32F429_PA7_FUNC_TIM8_CH1N 0x704 -#define STM32F429_PA7_FUNC_SPI1_MOSI 0x706 -#define STM32F429_PA7_FUNC_TIM14_CH1 0x70a -#define STM32F429_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV 0x70c -#define STM32F429_PA7_FUNC_EVENTOUT 0x710 -#define STM32F429_PA7_FUNC_ANALOG 0x711 - -#define STM32F429_PA8_FUNC_GPIO 0x800 -#define STM32F429_PA8_FUNC_MCO1 0x801 -#define STM32F429_PA8_FUNC_TIM1_CH1 0x802 -#define STM32F429_PA8_FUNC_I2C3_SCL 0x805 -#define STM32F429_PA8_FUNC_USART1_CK 0x808 -#define STM32F429_PA8_FUNC_OTG_FS_SOF 0x80b -#define STM32F429_PA8_FUNC_LCD_R6 0x80f -#define STM32F429_PA8_FUNC_EVENTOUT 0x810 -#define STM32F429_PA8_FUNC_ANALOG 0x811 - -#define STM32F429_PA9_FUNC_GPIO 0x900 -#define STM32F429_PA9_FUNC_TIM1_CH2 0x902 -#define STM32F429_PA9_FUNC_I2C3_SMBA 0x905 -#define STM32F429_PA9_FUNC_USART1_TX 0x908 -#define STM32F429_PA9_FUNC_DCMI_D0 0x90e -#define STM32F429_PA9_FUNC_EVENTOUT 0x910 -#define STM32F429_PA9_FUNC_ANALOG 0x911 - -#define STM32F429_PA10_FUNC_GPIO 0xa00 -#define STM32F429_PA10_FUNC_TIM1_CH3 0xa02 -#define STM32F429_PA10_FUNC_USART1_RX 0xa08 -#define STM32F429_PA10_FUNC_OTG_FS_ID 0xa0b -#define STM32F429_PA10_FUNC_DCMI_D1 0xa0e -#define STM32F429_PA10_FUNC_EVENTOUT 0xa10 -#define STM32F429_PA10_FUNC_ANALOG 0xa11 - -#define STM32F429_PA11_FUNC_GPIO 0xb00 -#define STM32F429_PA11_FUNC_TIM1_CH4 0xb02 -#define STM32F429_PA11_FUNC_USART1_CTS 0xb08 -#define STM32F429_PA11_FUNC_CAN1_RX 0xb0a -#define STM32F429_PA11_FUNC_OTG_FS_DM 0xb0b -#define STM32F429_PA11_FUNC_LCD_R4 0xb0f -#define STM32F429_PA11_FUNC_EVENTOUT 0xb10 -#define STM32F429_PA11_FUNC_ANALOG 0xb11 - -#define STM32F429_PA12_FUNC_GPIO 0xc00 -#define STM32F429_PA12_FUNC_TIM1_ETR 0xc02 -#define STM32F429_PA12_FUNC_USART1_RTS 0xc08 -#define STM32F429_PA12_FUNC_CAN1_TX 0xc0a -#define STM32F429_PA12_FUNC_OTG_FS_DP 0xc0b -#define STM32F429_PA12_FUNC_LCD_R5 0xc0f -#define STM32F429_PA12_FUNC_EVENTOUT 0xc10 -#define STM32F429_PA12_FUNC_ANALOG 0xc11 - -#define STM32F429_PA13_FUNC_GPIO 0xd00 -#define STM32F429_PA13_FUNC_JTMS_SWDIO 0xd01 -#define STM32F429_PA13_FUNC_EVENTOUT 0xd10 -#define STM32F429_PA13_FUNC_ANALOG 0xd11 - -#define STM32F429_PA14_FUNC_GPIO 0xe00 -#define STM32F429_PA14_FUNC_JTCK_SWCLK 0xe01 -#define STM32F429_PA14_FUNC_EVENTOUT 0xe10 -#define STM32F429_PA14_FUNC_ANALOG 0xe11 - -#define STM32F429_PA15_FUNC_GPIO 0xf00 -#define STM32F429_PA15_FUNC_JTDI 0xf01 -#define STM32F429_PA15_FUNC_TIM2_CH1_TIM2_ETR 0xf02 -#define STM32F429_PA15_FUNC_SPI1_NSS 0xf06 -#define STM32F429_PA15_FUNC_SPI3_NSS_I2S3_WS 0xf07 -#define STM32F429_PA15_FUNC_EVENTOUT 0xf10 -#define STM32F429_PA15_FUNC_ANALOG 0xf11 - - - -#define STM32F429_PB0_FUNC_GPIO 0x1000 -#define STM32F429_PB0_FUNC_TIM1_CH2N 0x1002 -#define STM32F429_PB0_FUNC_TIM3_CH3 0x1003 -#define STM32F429_PB0_FUNC_TIM8_CH2N 0x1004 -#define STM32F429_PB0_FUNC_LCD_R3 0x100a -#define STM32F429_PB0_FUNC_OTG_HS_ULPI_D1 0x100b -#define STM32F429_PB0_FUNC_ETH_MII_RXD2 0x100c -#define STM32F429_PB0_FUNC_EVENTOUT 0x1010 -#define STM32F429_PB0_FUNC_ANALOG 0x1011 - -#define STM32F429_PB1_FUNC_GPIO 0x1100 -#define STM32F429_PB1_FUNC_TIM1_CH3N 0x1102 -#define STM32F429_PB1_FUNC_TIM3_CH4 0x1103 -#define STM32F429_PB1_FUNC_TIM8_CH3N 0x1104 -#define STM32F429_PB1_FUNC_LCD_R6 0x110a -#define STM32F429_PB1_FUNC_OTG_HS_ULPI_D2 0x110b -#define STM32F429_PB1_FUNC_ETH_MII_RXD3 0x110c -#define STM32F429_PB1_FUNC_EVENTOUT 0x1110 -#define STM32F429_PB1_FUNC_ANALOG 0x1111 - -#define STM32F429_PB2_FUNC_GPIO 0x1200 -#define STM32F429_PB2_FUNC_EVENTOUT 0x1210 -#define STM32F429_PB2_FUNC_ANALOG 0x1211 - -#define STM32F429_PB3_FUNC_GPIO 0x1300 -#define STM32F429_PB3_FUNC_JTDO_TRACESWO 0x1301 -#define STM32F429_PB3_FUNC_TIM2_CH2 0x1302 -#define STM32F429_PB3_FUNC_SPI1_SCK 0x1306 -#define STM32F429_PB3_FUNC_SPI3_SCK_I2S3_CK 0x1307 -#define STM32F429_PB3_FUNC_EVENTOUT 0x1310 -#define STM32F429_PB3_FUNC_ANALOG 0x1311 - -#define STM32F429_PB4_FUNC_GPIO 0x1400 -#define STM32F429_PB4_FUNC_NJTRST 0x1401 -#define STM32F429_PB4_FUNC_TIM3_CH1 0x1403 -#define STM32F429_PB4_FUNC_SPI1_MISO 0x1406 -#define STM32F429_PB4_FUNC_SPI3_MISO 0x1407 -#define STM32F429_PB4_FUNC_I2S3EXT_SD 0x1408 -#define STM32F429_PB4_FUNC_EVENTOUT 0x1410 -#define STM32F429_PB4_FUNC_ANALOG 0x1411 - -#define STM32F429_PB5_FUNC_GPIO 0x1500 -#define STM32F429_PB5_FUNC_TIM3_CH2 0x1503 -#define STM32F429_PB5_FUNC_I2C1_SMBA 0x1505 -#define STM32F429_PB5_FUNC_SPI1_MOSI 0x1506 -#define STM32F429_PB5_FUNC_SPI3_MOSI_I2S3_SD 0x1507 -#define STM32F429_PB5_FUNC_CAN2_RX 0x150a -#define STM32F429_PB5_FUNC_OTG_HS_ULPI_D7 0x150b -#define STM32F429_PB5_FUNC_ETH_PPS_OUT 0x150c -#define STM32F429_PB5_FUNC_FMC_SDCKE1 0x150d -#define STM32F429_PB5_FUNC_DCMI_D10 0x150e -#define STM32F429_PB5_FUNC_EVENTOUT 0x1510 -#define STM32F429_PB5_FUNC_ANALOG 0x1511 - -#define STM32F429_PB6_FUNC_GPIO 0x1600 -#define STM32F429_PB6_FUNC_TIM4_CH1 0x1603 -#define STM32F429_PB6_FUNC_I2C1_SCL 0x1605 -#define STM32F429_PB6_FUNC_USART1_TX 0x1608 -#define STM32F429_PB6_FUNC_CAN2_TX 0x160a -#define STM32F429_PB6_FUNC_FMC_SDNE1 0x160d -#define STM32F429_PB6_FUNC_DCMI_D5 0x160e -#define STM32F429_PB6_FUNC_EVENTOUT 0x1610 -#define STM32F429_PB6_FUNC_ANALOG 0x1611 - -#define STM32F429_PB7_FUNC_GPIO 0x1700 -#define STM32F429_PB7_FUNC_TIM4_CH2 0x1703 -#define STM32F429_PB7_FUNC_I2C1_SDA 0x1705 -#define STM32F429_PB7_FUNC_USART1_RX 0x1708 -#define STM32F429_PB7_FUNC_FMC_NL 0x170d -#define STM32F429_PB7_FUNC_DCMI_VSYNC 0x170e -#define STM32F429_PB7_FUNC_EVENTOUT 0x1710 -#define STM32F429_PB7_FUNC_ANALOG 0x1711 - -#define STM32F429_PB8_FUNC_GPIO 0x1800 -#define STM32F429_PB8_FUNC_TIM4_CH3 0x1803 -#define STM32F429_PB8_FUNC_TIM10_CH1 0x1804 -#define STM32F429_PB8_FUNC_I2C1_SCL 0x1805 -#define STM32F429_PB8_FUNC_CAN1_RX 0x180a -#define STM32F429_PB8_FUNC_ETH_MII_TXD3 0x180c -#define STM32F429_PB8_FUNC_SDIO_D4 0x180d -#define STM32F429_PB8_FUNC_DCMI_D6 0x180e -#define STM32F429_PB8_FUNC_LCD_B6 0x180f -#define STM32F429_PB8_FUNC_EVENTOUT 0x1810 -#define STM32F429_PB8_FUNC_ANALOG 0x1811 - -#define STM32F429_PB9_FUNC_GPIO 0x1900 -#define STM32F429_PB9_FUNC_TIM4_CH4 0x1903 -#define STM32F429_PB9_FUNC_TIM11_CH1 0x1904 -#define STM32F429_PB9_FUNC_I2C1_SDA 0x1905 -#define STM32F429_PB9_FUNC_SPI2_NSS_I2S2_WS 0x1906 -#define STM32F429_PB9_FUNC_CAN1_TX 0x190a -#define STM32F429_PB9_FUNC_SDIO_D5 0x190d -#define STM32F429_PB9_FUNC_DCMI_D7 0x190e -#define STM32F429_PB9_FUNC_LCD_B7 0x190f -#define STM32F429_PB9_FUNC_EVENTOUT 0x1910 -#define STM32F429_PB9_FUNC_ANALOG 0x1911 - -#define STM32F429_PB10_FUNC_GPIO 0x1a00 -#define STM32F429_PB10_FUNC_TIM2_CH3 0x1a02 -#define STM32F429_PB10_FUNC_I2C2_SCL 0x1a05 -#define STM32F429_PB10_FUNC_SPI2_SCK_I2S2_CK 0x1a06 -#define STM32F429_PB10_FUNC_USART3_TX 0x1a08 -#define STM32F429_PB10_FUNC_OTG_HS_ULPI_D3 0x1a0b -#define STM32F429_PB10_FUNC_ETH_MII_RX_ER 0x1a0c -#define STM32F429_PB10_FUNC_LCD_G4 0x1a0f -#define STM32F429_PB10_FUNC_EVENTOUT 0x1a10 -#define STM32F429_PB10_FUNC_ANALOG 0x1a11 - -#define STM32F429_PB11_FUNC_GPIO 0x1b00 -#define STM32F429_PB11_FUNC_TIM2_CH4 0x1b02 -#define STM32F429_PB11_FUNC_I2C2_SDA 0x1b05 -#define STM32F429_PB11_FUNC_USART3_RX 0x1b08 -#define STM32F429_PB11_FUNC_OTG_HS_ULPI_D4 0x1b0b -#define STM32F429_PB11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN 0x1b0c -#define STM32F429_PB11_FUNC_LCD_G5 0x1b0f -#define STM32F429_PB11_FUNC_EVENTOUT 0x1b10 -#define STM32F429_PB11_FUNC_ANALOG 0x1b11 - -#define STM32F429_PB12_FUNC_GPIO 0x1c00 -#define STM32F429_PB12_FUNC_TIM1_BKIN 0x1c02 -#define STM32F429_PB12_FUNC_I2C2_SMBA 0x1c05 -#define STM32F429_PB12_FUNC_SPI2_NSS_I2S2_WS 0x1c06 -#define STM32F429_PB12_FUNC_USART3_CK 0x1c08 -#define STM32F429_PB12_FUNC_CAN2_RX 0x1c0a -#define STM32F429_PB12_FUNC_OTG_HS_ULPI_D5 0x1c0b -#define STM32F429_PB12_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0 0x1c0c -#define STM32F429_PB12_FUNC_OTG_HS_ID 0x1c0d -#define STM32F429_PB12_FUNC_EVENTOUT 0x1c10 -#define STM32F429_PB12_FUNC_ANALOG 0x1c11 - -#define STM32F429_PB13_FUNC_GPIO 0x1d00 -#define STM32F429_PB13_FUNC_TIM1_CH1N 0x1d02 -#define STM32F429_PB13_FUNC_SPI2_SCK_I2S2_CK 0x1d06 -#define STM32F429_PB13_FUNC_USART3_CTS 0x1d08 -#define STM32F429_PB13_FUNC_CAN2_TX 0x1d0a -#define STM32F429_PB13_FUNC_OTG_HS_ULPI_D6 0x1d0b -#define STM32F429_PB13_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1 0x1d0c -#define STM32F429_PB13_FUNC_EVENTOUT 0x1d10 -#define STM32F429_PB13_FUNC_ANALOG 0x1d11 - -#define STM32F429_PB14_FUNC_GPIO 0x1e00 -#define STM32F429_PB14_FUNC_TIM1_CH2N 0x1e02 -#define STM32F429_PB14_FUNC_TIM8_CH2N 0x1e04 -#define STM32F429_PB14_FUNC_SPI2_MISO 0x1e06 -#define STM32F429_PB14_FUNC_I2S2EXT_SD 0x1e07 -#define STM32F429_PB14_FUNC_USART3_RTS 0x1e08 -#define STM32F429_PB14_FUNC_TIM12_CH1 0x1e0a -#define STM32F429_PB14_FUNC_OTG_HS_DM 0x1e0d -#define STM32F429_PB14_FUNC_EVENTOUT 0x1e10 -#define STM32F429_PB14_FUNC_ANALOG 0x1e11 - -#define STM32F429_PB15_FUNC_GPIO 0x1f00 -#define STM32F429_PB15_FUNC_RTC_REFIN 0x1f01 -#define STM32F429_PB15_FUNC_TIM1_CH3N 0x1f02 -#define STM32F429_PB15_FUNC_TIM8_CH3N 0x1f04 -#define STM32F429_PB15_FUNC_SPI2_MOSI_I2S2_SD 0x1f06 -#define STM32F429_PB15_FUNC_TIM12_CH2 0x1f0a -#define STM32F429_PB15_FUNC_OTG_HS_DP 0x1f0d -#define STM32F429_PB15_FUNC_EVENTOUT 0x1f10 -#define STM32F429_PB15_FUNC_ANALOG 0x1f11 - - - -#define STM32F429_PC0_FUNC_GPIO 0x2000 -#define STM32F429_PC0_FUNC_OTG_HS_ULPI_STP 0x200b -#define STM32F429_PC0_FUNC_FMC_SDNWE 0x200d -#define STM32F429_PC0_FUNC_EVENTOUT 0x2010 -#define STM32F429_PC0_FUNC_ANALOG 0x2011 - -#define STM32F429_PC1_FUNC_GPIO 0x2100 -#define STM32F429_PC1_FUNC_ETH_MDC 0x210c -#define STM32F429_PC1_FUNC_EVENTOUT 0x2110 -#define STM32F429_PC1_FUNC_ANALOG 0x2111 - -#define STM32F429_PC2_FUNC_GPIO 0x2200 -#define STM32F429_PC2_FUNC_SPI2_MISO 0x2206 -#define STM32F429_PC2_FUNC_I2S2EXT_SD 0x2207 -#define STM32F429_PC2_FUNC_OTG_HS_ULPI_DIR 0x220b -#define STM32F429_PC2_FUNC_ETH_MII_TXD2 0x220c -#define STM32F429_PC2_FUNC_FMC_SDNE0 0x220d -#define STM32F429_PC2_FUNC_EVENTOUT 0x2210 -#define STM32F429_PC2_FUNC_ANALOG 0x2211 - -#define STM32F429_PC3_FUNC_GPIO 0x2300 -#define STM32F429_PC3_FUNC_SPI2_MOSI_I2S2_SD 0x2306 -#define STM32F429_PC3_FUNC_OTG_HS_ULPI_NXT 0x230b -#define STM32F429_PC3_FUNC_ETH_MII_TX_CLK 0x230c -#define STM32F429_PC3_FUNC_FMC_SDCKE0 0x230d -#define STM32F429_PC3_FUNC_EVENTOUT 0x2310 -#define STM32F429_PC3_FUNC_ANALOG 0x2311 - -#define STM32F429_PC4_FUNC_GPIO 0x2400 -#define STM32F429_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0 0x240c -#define STM32F429_PC4_FUNC_EVENTOUT 0x2410 -#define STM32F429_PC4_FUNC_ANALOG 0x2411 - -#define STM32F429_PC5_FUNC_GPIO 0x2500 -#define STM32F429_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1 0x250c -#define STM32F429_PC5_FUNC_EVENTOUT 0x2510 -#define STM32F429_PC5_FUNC_ANALOG 0x2511 - -#define STM32F429_PC6_FUNC_GPIO 0x2600 -#define STM32F429_PC6_FUNC_TIM3_CH1 0x2603 -#define STM32F429_PC6_FUNC_TIM8_CH1 0x2604 -#define STM32F429_PC6_FUNC_I2S2_MCK 0x2606 -#define STM32F429_PC6_FUNC_USART6_TX 0x2609 -#define STM32F429_PC6_FUNC_SDIO_D6 0x260d -#define STM32F429_PC6_FUNC_DCMI_D0 0x260e -#define STM32F429_PC6_FUNC_LCD_HSYNC 0x260f -#define STM32F429_PC6_FUNC_EVENTOUT 0x2610 -#define STM32F429_PC6_FUNC_ANALOG 0x2611 - -#define STM32F429_PC7_FUNC_GPIO 0x2700 -#define STM32F429_PC7_FUNC_TIM3_CH2 0x2703 -#define STM32F429_PC7_FUNC_TIM8_CH2 0x2704 -#define STM32F429_PC7_FUNC_I2S3_MCK 0x2707 -#define STM32F429_PC7_FUNC_USART6_RX 0x2709 -#define STM32F429_PC7_FUNC_SDIO_D7 0x270d -#define STM32F429_PC7_FUNC_DCMI_D1 0x270e -#define STM32F429_PC7_FUNC_LCD_G6 0x270f -#define STM32F429_PC7_FUNC_EVENTOUT 0x2710 -#define STM32F429_PC7_FUNC_ANALOG 0x2711 - -#define STM32F429_PC8_FUNC_GPIO 0x2800 -#define STM32F429_PC8_FUNC_TIM3_CH3 0x2803 -#define STM32F429_PC8_FUNC_TIM8_CH3 0x2804 -#define STM32F429_PC8_FUNC_USART6_CK 0x2809 -#define STM32F429_PC8_FUNC_SDIO_D0 0x280d -#define STM32F429_PC8_FUNC_DCMI_D2 0x280e -#define STM32F429_PC8_FUNC_EVENTOUT 0x2810 -#define STM32F429_PC8_FUNC_ANALOG 0x2811 - -#define STM32F429_PC9_FUNC_GPIO 0x2900 -#define STM32F429_PC9_FUNC_MCO2 0x2901 -#define STM32F429_PC9_FUNC_TIM3_CH4 0x2903 -#define STM32F429_PC9_FUNC_TIM8_CH4 0x2904 -#define STM32F429_PC9_FUNC_I2C3_SDA 0x2905 -#define STM32F429_PC9_FUNC_I2S_CKIN 0x2906 -#define STM32F429_PC9_FUNC_SDIO_D1 0x290d -#define STM32F429_PC9_FUNC_DCMI_D3 0x290e -#define STM32F429_PC9_FUNC_EVENTOUT 0x2910 -#define STM32F429_PC9_FUNC_ANALOG 0x2911 - -#define STM32F429_PC10_FUNC_GPIO 0x2a00 -#define STM32F429_PC10_FUNC_SPI3_SCK_I2S3_CK 0x2a07 -#define STM32F429_PC10_FUNC_USART3_TX 0x2a08 -#define STM32F429_PC10_FUNC_UART4_TX 0x2a09 -#define STM32F429_PC10_FUNC_SDIO_D2 0x2a0d -#define STM32F429_PC10_FUNC_DCMI_D8 0x2a0e -#define STM32F429_PC10_FUNC_LCD_R2 0x2a0f -#define STM32F429_PC10_FUNC_EVENTOUT 0x2a10 -#define STM32F429_PC10_FUNC_ANALOG 0x2a11 - -#define STM32F429_PC11_FUNC_GPIO 0x2b00 -#define STM32F429_PC11_FUNC_I2S3EXT_SD 0x2b06 -#define STM32F429_PC11_FUNC_SPI3_MISO 0x2b07 -#define STM32F429_PC11_FUNC_USART3_RX 0x2b08 -#define STM32F429_PC11_FUNC_UART4_RX 0x2b09 -#define STM32F429_PC11_FUNC_SDIO_D3 0x2b0d -#define STM32F429_PC11_FUNC_DCMI_D4 0x2b0e -#define STM32F429_PC11_FUNC_EVENTOUT 0x2b10 -#define STM32F429_PC11_FUNC_ANALOG 0x2b11 - -#define STM32F429_PC12_FUNC_GPIO 0x2c00 -#define STM32F429_PC12_FUNC_SPI3_MOSI_I2S3_SD 0x2c07 -#define STM32F429_PC12_FUNC_USART3_CK 0x2c08 -#define STM32F429_PC12_FUNC_UART5_TX 0x2c09 -#define STM32F429_PC12_FUNC_SDIO_CK 0x2c0d -#define STM32F429_PC12_FUNC_DCMI_D9 0x2c0e -#define STM32F429_PC12_FUNC_EVENTOUT 0x2c10 -#define STM32F429_PC12_FUNC_ANALOG 0x2c11 - -#define STM32F429_PC13_FUNC_GPIO 0x2d00 -#define STM32F429_PC13_FUNC_EVENTOUT 0x2d10 -#define STM32F429_PC13_FUNC_ANALOG 0x2d11 - -#define STM32F429_PC14_FUNC_GPIO 0x2e00 -#define STM32F429_PC14_FUNC_EVENTOUT 0x2e10 -#define STM32F429_PC14_FUNC_ANALOG 0x2e11 - -#define STM32F429_PC15_FUNC_GPIO 0x2f00 -#define STM32F429_PC15_FUNC_EVENTOUT 0x2f10 -#define STM32F429_PC15_FUNC_ANALOG 0x2f11 - - - -#define STM32F429_PD0_FUNC_GPIO 0x3000 -#define STM32F429_PD0_FUNC_CAN1_RX 0x300a -#define STM32F429_PD0_FUNC_FMC_D2 0x300d -#define STM32F429_PD0_FUNC_EVENTOUT 0x3010 -#define STM32F429_PD0_FUNC_ANALOG 0x3011 - -#define STM32F429_PD1_FUNC_GPIO 0x3100 -#define STM32F429_PD1_FUNC_CAN1_TX 0x310a -#define STM32F429_PD1_FUNC_FMC_D3 0x310d -#define STM32F429_PD1_FUNC_EVENTOUT 0x3110 -#define STM32F429_PD1_FUNC_ANALOG 0x3111 - -#define STM32F429_PD2_FUNC_GPIO 0x3200 -#define STM32F429_PD2_FUNC_TIM3_ETR 0x3203 -#define STM32F429_PD2_FUNC_UART5_RX 0x3209 -#define STM32F429_PD2_FUNC_SDIO_CMD 0x320d -#define STM32F429_PD2_FUNC_DCMI_D11 0x320e -#define STM32F429_PD2_FUNC_EVENTOUT 0x3210 -#define STM32F429_PD2_FUNC_ANALOG 0x3211 - -#define STM32F429_PD3_FUNC_GPIO 0x3300 -#define STM32F429_PD3_FUNC_SPI2_SCK_I2S2_CK 0x3306 -#define STM32F429_PD3_FUNC_USART2_CTS 0x3308 -#define STM32F429_PD3_FUNC_FMC_CLK 0x330d -#define STM32F429_PD3_FUNC_DCMI_D5 0x330e -#define STM32F429_PD3_FUNC_LCD_G7 0x330f -#define STM32F429_PD3_FUNC_EVENTOUT 0x3310 -#define STM32F429_PD3_FUNC_ANALOG 0x3311 - -#define STM32F429_PD4_FUNC_GPIO 0x3400 -#define STM32F429_PD4_FUNC_USART2_RTS 0x3408 -#define STM32F429_PD4_FUNC_FMC_NOE 0x340d -#define STM32F429_PD4_FUNC_EVENTOUT 0x3410 -#define STM32F429_PD4_FUNC_ANALOG 0x3411 - -#define STM32F429_PD5_FUNC_GPIO 0x3500 -#define STM32F429_PD5_FUNC_USART2_TX 0x3508 -#define STM32F429_PD5_FUNC_FMC_NWE 0x350d -#define STM32F429_PD5_FUNC_EVENTOUT 0x3510 -#define STM32F429_PD5_FUNC_ANALOG 0x3511 - -#define STM32F429_PD6_FUNC_GPIO 0x3600 -#define STM32F429_PD6_FUNC_SPI3_MOSI_I2S3_SD 0x3606 -#define STM32F429_PD6_FUNC_SAI1_SD_A 0x3607 -#define STM32F429_PD6_FUNC_USART2_RX 0x3608 -#define STM32F429_PD6_FUNC_FMC_NWAIT 0x360d -#define STM32F429_PD6_FUNC_DCMI_D10 0x360e -#define STM32F429_PD6_FUNC_LCD_B2 0x360f -#define STM32F429_PD6_FUNC_EVENTOUT 0x3610 -#define STM32F429_PD6_FUNC_ANALOG 0x3611 - -#define STM32F429_PD7_FUNC_GPIO 0x3700 -#define STM32F429_PD7_FUNC_USART2_CK 0x3708 -#define STM32F429_PD7_FUNC_FMC_NE1_FMC_NCE2 0x370d -#define STM32F429_PD7_FUNC_EVENTOUT 0x3710 -#define STM32F429_PD7_FUNC_ANALOG 0x3711 - -#define STM32F429_PD8_FUNC_GPIO 0x3800 -#define STM32F429_PD8_FUNC_USART3_TX 0x3808 -#define STM32F429_PD8_FUNC_FMC_D13 0x380d -#define STM32F429_PD8_FUNC_EVENTOUT 0x3810 -#define STM32F429_PD8_FUNC_ANALOG 0x3811 - -#define STM32F429_PD9_FUNC_GPIO 0x3900 -#define STM32F429_PD9_FUNC_USART3_RX 0x3908 -#define STM32F429_PD9_FUNC_FMC_D14 0x390d -#define STM32F429_PD9_FUNC_EVENTOUT 0x3910 -#define STM32F429_PD9_FUNC_ANALOG 0x3911 - -#define STM32F429_PD10_FUNC_GPIO 0x3a00 -#define STM32F429_PD10_FUNC_USART3_CK 0x3a08 -#define STM32F429_PD10_FUNC_FMC_D15 0x3a0d -#define STM32F429_PD10_FUNC_LCD_B3 0x3a0f -#define STM32F429_PD10_FUNC_EVENTOUT 0x3a10 -#define STM32F429_PD10_FUNC_ANALOG 0x3a11 - -#define STM32F429_PD11_FUNC_GPIO 0x3b00 -#define STM32F429_PD11_FUNC_USART3_CTS 0x3b08 -#define STM32F429_PD11_FUNC_FMC_A16 0x3b0d -#define STM32F429_PD11_FUNC_EVENTOUT 0x3b10 -#define STM32F429_PD11_FUNC_ANALOG 0x3b11 - -#define STM32F429_PD12_FUNC_GPIO 0x3c00 -#define STM32F429_PD12_FUNC_TIM4_CH1 0x3c03 -#define STM32F429_PD12_FUNC_USART3_RTS 0x3c08 -#define STM32F429_PD12_FUNC_FMC_A17 0x3c0d -#define STM32F429_PD12_FUNC_EVENTOUT 0x3c10 -#define STM32F429_PD12_FUNC_ANALOG 0x3c11 - -#define STM32F429_PD13_FUNC_GPIO 0x3d00 -#define STM32F429_PD13_FUNC_TIM4_CH2 0x3d03 -#define STM32F429_PD13_FUNC_FMC_A18 0x3d0d -#define STM32F429_PD13_FUNC_EVENTOUT 0x3d10 -#define STM32F429_PD13_FUNC_ANALOG 0x3d11 - -#define STM32F429_PD14_FUNC_GPIO 0x3e00 -#define STM32F429_PD14_FUNC_TIM4_CH3 0x3e03 -#define STM32F429_PD14_FUNC_FMC_D0 0x3e0d -#define STM32F429_PD14_FUNC_EVENTOUT 0x3e10 -#define STM32F429_PD14_FUNC_ANALOG 0x3e11 - -#define STM32F429_PD15_FUNC_GPIO 0x3f00 -#define STM32F429_PD15_FUNC_TIM4_CH4 0x3f03 -#define STM32F429_PD15_FUNC_FMC_D1 0x3f0d -#define STM32F429_PD15_FUNC_EVENTOUT 0x3f10 -#define STM32F429_PD15_FUNC_ANALOG 0x3f11 - - - -#define STM32F429_PE0_FUNC_GPIO 0x4000 -#define STM32F429_PE0_FUNC_TIM4_ETR 0x4003 -#define STM32F429_PE0_FUNC_UART8_RX 0x4009 -#define STM32F429_PE0_FUNC_FMC_NBL0 0x400d -#define STM32F429_PE0_FUNC_DCMI_D2 0x400e -#define STM32F429_PE0_FUNC_EVENTOUT 0x4010 -#define STM32F429_PE0_FUNC_ANALOG 0x4011 - -#define STM32F429_PE1_FUNC_GPIO 0x4100 -#define STM32F429_PE1_FUNC_UART8_TX 0x4109 -#define STM32F429_PE1_FUNC_FMC_NBL1 0x410d -#define STM32F429_PE1_FUNC_DCMI_D3 0x410e -#define STM32F429_PE1_FUNC_EVENTOUT 0x4110 -#define STM32F429_PE1_FUNC_ANALOG 0x4111 - -#define STM32F429_PE2_FUNC_GPIO 0x4200 -#define STM32F429_PE2_FUNC_TRACECLK 0x4201 -#define STM32F429_PE2_FUNC_SPI4_SCK 0x4206 -#define STM32F429_PE2_FUNC_SAI1_MCLK_A 0x4207 -#define STM32F429_PE2_FUNC_ETH_MII_TXD3 0x420c -#define STM32F429_PE2_FUNC_FMC_A23 0x420d -#define STM32F429_PE2_FUNC_EVENTOUT 0x4210 -#define STM32F429_PE2_FUNC_ANALOG 0x4211 - -#define STM32F429_PE3_FUNC_GPIO 0x4300 -#define STM32F429_PE3_FUNC_TRACED0 0x4301 -#define STM32F429_PE3_FUNC_SAI1_SD_B 0x4307 -#define STM32F429_PE3_FUNC_FMC_A19 0x430d -#define STM32F429_PE3_FUNC_EVENTOUT 0x4310 -#define STM32F429_PE3_FUNC_ANALOG 0x4311 - -#define STM32F429_PE4_FUNC_GPIO 0x4400 -#define STM32F429_PE4_FUNC_TRACED1 0x4401 -#define STM32F429_PE4_FUNC_SPI4_NSS 0x4406 -#define STM32F429_PE4_FUNC_SAI1_FS_A 0x4407 -#define STM32F429_PE4_FUNC_FMC_A20 0x440d -#define STM32F429_PE4_FUNC_DCMI_D4 0x440e -#define STM32F429_PE4_FUNC_LCD_B0 0x440f -#define STM32F429_PE4_FUNC_EVENTOUT 0x4410 -#define STM32F429_PE4_FUNC_ANALOG 0x4411 - -#define STM32F429_PE5_FUNC_GPIO 0x4500 -#define STM32F429_PE5_FUNC_TRACED2 0x4501 -#define STM32F429_PE5_FUNC_TIM9_CH1 0x4504 -#define STM32F429_PE5_FUNC_SPI4_MISO 0x4506 -#define STM32F429_PE5_FUNC_SAI1_SCK_A 0x4507 -#define STM32F429_PE5_FUNC_FMC_A21 0x450d -#define STM32F429_PE5_FUNC_DCMI_D6 0x450e -#define STM32F429_PE5_FUNC_LCD_G0 0x450f -#define STM32F429_PE5_FUNC_EVENTOUT 0x4510 -#define STM32F429_PE5_FUNC_ANALOG 0x4511 - -#define STM32F429_PE6_FUNC_GPIO 0x4600 -#define STM32F429_PE6_FUNC_TRACED3 0x4601 -#define STM32F429_PE6_FUNC_TIM9_CH2 0x4604 -#define STM32F429_PE6_FUNC_SPI4_MOSI 0x4606 -#define STM32F429_PE6_FUNC_SAI1_SD_A 0x4607 -#define STM32F429_PE6_FUNC_FMC_A22 0x460d -#define STM32F429_PE6_FUNC_DCMI_D7 0x460e -#define STM32F429_PE6_FUNC_LCD_G1 0x460f -#define STM32F429_PE6_FUNC_EVENTOUT 0x4610 -#define STM32F429_PE6_FUNC_ANALOG 0x4611 - -#define STM32F429_PE7_FUNC_GPIO 0x4700 -#define STM32F429_PE7_FUNC_TIM1_ETR 0x4702 -#define STM32F429_PE7_FUNC_UART7_RX 0x4709 -#define STM32F429_PE7_FUNC_FMC_D4 0x470d -#define STM32F429_PE7_FUNC_EVENTOUT 0x4710 -#define STM32F429_PE7_FUNC_ANALOG 0x4711 - -#define STM32F429_PE8_FUNC_GPIO 0x4800 -#define STM32F429_PE8_FUNC_TIM1_CH1N 0x4802 -#define STM32F429_PE8_FUNC_UART7_TX 0x4809 -#define STM32F429_PE8_FUNC_FMC_D5 0x480d -#define STM32F429_PE8_FUNC_EVENTOUT 0x4810 -#define STM32F429_PE8_FUNC_ANALOG 0x4811 - -#define STM32F429_PE9_FUNC_GPIO 0x4900 -#define STM32F429_PE9_FUNC_TIM1_CH1 0x4902 -#define STM32F429_PE9_FUNC_FMC_D6 0x490d -#define STM32F429_PE9_FUNC_EVENTOUT 0x4910 -#define STM32F429_PE9_FUNC_ANALOG 0x4911 - -#define STM32F429_PE10_FUNC_GPIO 0x4a00 -#define STM32F429_PE10_FUNC_TIM1_CH2N 0x4a02 -#define STM32F429_PE10_FUNC_FMC_D7 0x4a0d -#define STM32F429_PE10_FUNC_EVENTOUT 0x4a10 -#define STM32F429_PE10_FUNC_ANALOG 0x4a11 - -#define STM32F429_PE11_FUNC_GPIO 0x4b00 -#define STM32F429_PE11_FUNC_TIM1_CH2 0x4b02 -#define STM32F429_PE11_FUNC_SPI4_NSS 0x4b06 -#define STM32F429_PE11_FUNC_FMC_D8 0x4b0d -#define STM32F429_PE11_FUNC_LCD_G3 0x4b0f -#define STM32F429_PE11_FUNC_EVENTOUT 0x4b10 -#define STM32F429_PE11_FUNC_ANALOG 0x4b11 - -#define STM32F429_PE12_FUNC_GPIO 0x4c00 -#define STM32F429_PE12_FUNC_TIM1_CH3N 0x4c02 -#define STM32F429_PE12_FUNC_SPI4_SCK 0x4c06 -#define STM32F429_PE12_FUNC_FMC_D9 0x4c0d -#define STM32F429_PE12_FUNC_LCD_B4 0x4c0f -#define STM32F429_PE12_FUNC_EVENTOUT 0x4c10 -#define STM32F429_PE12_FUNC_ANALOG 0x4c11 - -#define STM32F429_PE13_FUNC_GPIO 0x4d00 -#define STM32F429_PE13_FUNC_TIM1_CH3 0x4d02 -#define STM32F429_PE13_FUNC_SPI4_MISO 0x4d06 -#define STM32F429_PE13_FUNC_FMC_D10 0x4d0d -#define STM32F429_PE13_FUNC_LCD_DE 0x4d0f -#define STM32F429_PE13_FUNC_EVENTOUT 0x4d10 -#define STM32F429_PE13_FUNC_ANALOG 0x4d11 - -#define STM32F429_PE14_FUNC_GPIO 0x4e00 -#define STM32F429_PE14_FUNC_TIM1_CH4 0x4e02 -#define STM32F429_PE14_FUNC_SPI4_MOSI 0x4e06 -#define STM32F429_PE14_FUNC_FMC_D11 0x4e0d -#define STM32F429_PE14_FUNC_LCD_CLK 0x4e0f -#define STM32F429_PE14_FUNC_EVENTOUT 0x4e10 -#define STM32F429_PE14_FUNC_ANALOG 0x4e11 - -#define STM32F429_PE15_FUNC_GPIO 0x4f00 -#define STM32F429_PE15_FUNC_TIM1_BKIN 0x4f02 -#define STM32F429_PE15_FUNC_FMC_D12 0x4f0d -#define STM32F429_PE15_FUNC_LCD_R7 0x4f0f -#define STM32F429_PE15_FUNC_EVENTOUT 0x4f10 -#define STM32F429_PE15_FUNC_ANALOG 0x4f11 - - - -#define STM32F429_PF0_FUNC_GPIO 0x5000 -#define STM32F429_PF0_FUNC_I2C2_SDA 0x5005 -#define STM32F429_PF0_FUNC_FMC_A0 0x500d -#define STM32F429_PF0_FUNC_EVENTOUT 0x5010 -#define STM32F429_PF0_FUNC_ANALOG 0x5011 - -#define STM32F429_PF1_FUNC_GPIO 0x5100 -#define STM32F429_PF1_FUNC_I2C2_SCL 0x5105 -#define STM32F429_PF1_FUNC_FMC_A1 0x510d -#define STM32F429_PF1_FUNC_EVENTOUT 0x5110 -#define STM32F429_PF1_FUNC_ANALOG 0x5111 - -#define STM32F429_PF2_FUNC_GPIO 0x5200 -#define STM32F429_PF2_FUNC_I2C2_SMBA 0x5205 -#define STM32F429_PF2_FUNC_FMC_A2 0x520d -#define STM32F429_PF2_FUNC_EVENTOUT 0x5210 -#define STM32F429_PF2_FUNC_ANALOG 0x5211 - -#define STM32F429_PF3_FUNC_GPIO 0x5300 -#define STM32F429_PF3_FUNC_FMC_A3 0x530d -#define STM32F429_PF3_FUNC_EVENTOUT 0x5310 -#define STM32F429_PF3_FUNC_ANALOG 0x5311 - -#define STM32F429_PF4_FUNC_GPIO 0x5400 -#define STM32F429_PF4_FUNC_FMC_A4 0x540d -#define STM32F429_PF4_FUNC_EVENTOUT 0x5410 -#define STM32F429_PF4_FUNC_ANALOG 0x5411 - -#define STM32F429_PF5_FUNC_GPIO 0x5500 -#define STM32F429_PF5_FUNC_FMC_A5 0x550d -#define STM32F429_PF5_FUNC_EVENTOUT 0x5510 -#define STM32F429_PF5_FUNC_ANALOG 0x5511 - -#define STM32F429_PF6_FUNC_GPIO 0x5600 -#define STM32F429_PF6_FUNC_TIM10_CH1 0x5604 -#define STM32F429_PF6_FUNC_SPI5_NSS 0x5606 -#define STM32F429_PF6_FUNC_SAI1_SD_B 0x5607 -#define STM32F429_PF6_FUNC_UART7_RX 0x5609 -#define STM32F429_PF6_FUNC_FMC_NIORD 0x560d -#define STM32F429_PF6_FUNC_EVENTOUT 0x5610 -#define STM32F429_PF6_FUNC_ANALOG 0x5611 - -#define STM32F429_PF7_FUNC_GPIO 0x5700 -#define STM32F429_PF7_FUNC_TIM11_CH1 0x5704 -#define STM32F429_PF7_FUNC_SPI5_SCK 0x5706 -#define STM32F429_PF7_FUNC_SAI1_MCLK_B 0x5707 -#define STM32F429_PF7_FUNC_UART7_TX 0x5709 -#define STM32F429_PF7_FUNC_FMC_NREG 0x570d -#define STM32F429_PF7_FUNC_EVENTOUT 0x5710 -#define STM32F429_PF7_FUNC_ANALOG 0x5711 - -#define STM32F429_PF8_FUNC_GPIO 0x5800 -#define STM32F429_PF8_FUNC_SPI5_MISO 0x5806 -#define STM32F429_PF8_FUNC_SAI1_SCK_B 0x5807 -#define STM32F429_PF8_FUNC_TIM13_CH1 0x580a -#define STM32F429_PF8_FUNC_FMC_NIOWR 0x580d -#define STM32F429_PF8_FUNC_EVENTOUT 0x5810 -#define STM32F429_PF8_FUNC_ANALOG 0x5811 - -#define STM32F429_PF9_FUNC_GPIO 0x5900 -#define STM32F429_PF9_FUNC_SPI5_MOSI 0x5906 -#define STM32F429_PF9_FUNC_SAI1_FS_B 0x5907 -#define STM32F429_PF9_FUNC_TIM14_CH1 0x590a -#define STM32F429_PF9_FUNC_FMC_CD 0x590d -#define STM32F429_PF9_FUNC_EVENTOUT 0x5910 -#define STM32F429_PF9_FUNC_ANALOG 0x5911 - -#define STM32F429_PF10_FUNC_GPIO 0x5a00 -#define STM32F429_PF10_FUNC_FMC_INTR 0x5a0d -#define STM32F429_PF10_FUNC_DCMI_D11 0x5a0e -#define STM32F429_PF10_FUNC_LCD_DE 0x5a0f -#define STM32F429_PF10_FUNC_EVENTOUT 0x5a10 -#define STM32F429_PF10_FUNC_ANALOG 0x5a11 - -#define STM32F429_PF11_FUNC_GPIO 0x5b00 -#define STM32F429_PF11_FUNC_SPI5_MOSI 0x5b06 -#define STM32F429_PF11_FUNC_FMC_SDNRAS 0x5b0d -#define STM32F429_PF11_FUNC_DCMI_D12 0x5b0e -#define STM32F429_PF11_FUNC_EVENTOUT 0x5b10 -#define STM32F429_PF11_FUNC_ANALOG 0x5b11 - -#define STM32F429_PF12_FUNC_GPIO 0x5c00 -#define STM32F429_PF12_FUNC_FMC_A6 0x5c0d -#define STM32F429_PF12_FUNC_EVENTOUT 0x5c10 -#define STM32F429_PF12_FUNC_ANALOG 0x5c11 - -#define STM32F429_PF13_FUNC_GPIO 0x5d00 -#define STM32F429_PF13_FUNC_FMC_A7 0x5d0d -#define STM32F429_PF13_FUNC_EVENTOUT 0x5d10 -#define STM32F429_PF13_FUNC_ANALOG 0x5d11 - -#define STM32F429_PF14_FUNC_GPIO 0x5e00 -#define STM32F429_PF14_FUNC_FMC_A8 0x5e0d -#define STM32F429_PF14_FUNC_EVENTOUT 0x5e10 -#define STM32F429_PF14_FUNC_ANALOG 0x5e11 - -#define STM32F429_PF15_FUNC_GPIO 0x5f00 -#define STM32F429_PF15_FUNC_FMC_A9 0x5f0d -#define STM32F429_PF15_FUNC_EVENTOUT 0x5f10 -#define STM32F429_PF15_FUNC_ANALOG 0x5f11 - - - -#define STM32F429_PG0_FUNC_GPIO 0x6000 -#define STM32F429_PG0_FUNC_FMC_A10 0x600d -#define STM32F429_PG0_FUNC_EVENTOUT 0x6010 -#define STM32F429_PG0_FUNC_ANALOG 0x6011 - -#define STM32F429_PG1_FUNC_GPIO 0x6100 -#define STM32F429_PG1_FUNC_FMC_A11 0x610d -#define STM32F429_PG1_FUNC_EVENTOUT 0x6110 -#define STM32F429_PG1_FUNC_ANALOG 0x6111 - -#define STM32F429_PG2_FUNC_GPIO 0x6200 -#define STM32F429_PG2_FUNC_FMC_A12 0x620d -#define STM32F429_PG2_FUNC_EVENTOUT 0x6210 -#define STM32F429_PG2_FUNC_ANALOG 0x6211 - -#define STM32F429_PG3_FUNC_GPIO 0x6300 -#define STM32F429_PG3_FUNC_FMC_A13 0x630d -#define STM32F429_PG3_FUNC_EVENTOUT 0x6310 -#define STM32F429_PG3_FUNC_ANALOG 0x6311 - -#define STM32F429_PG4_FUNC_GPIO 0x6400 -#define STM32F429_PG4_FUNC_FMC_A14_FMC_BA0 0x640d -#define STM32F429_PG4_FUNC_EVENTOUT 0x6410 -#define STM32F429_PG4_FUNC_ANALOG 0x6411 - -#define STM32F429_PG5_FUNC_GPIO 0x6500 -#define STM32F429_PG5_FUNC_FMC_A15_FMC_BA1 0x650d -#define STM32F429_PG5_FUNC_EVENTOUT 0x6510 -#define STM32F429_PG5_FUNC_ANALOG 0x6511 - -#define STM32F429_PG6_FUNC_GPIO 0x6600 -#define STM32F429_PG6_FUNC_FMC_INT2 0x660d -#define STM32F429_PG6_FUNC_DCMI_D12 0x660e -#define STM32F429_PG6_FUNC_LCD_R7 0x660f -#define STM32F429_PG6_FUNC_EVENTOUT 0x6610 -#define STM32F429_PG6_FUNC_ANALOG 0x6611 - -#define STM32F429_PG7_FUNC_GPIO 0x6700 -#define STM32F429_PG7_FUNC_USART6_CK 0x6709 -#define STM32F429_PG7_FUNC_FMC_INT3 0x670d -#define STM32F429_PG7_FUNC_DCMI_D13 0x670e -#define STM32F429_PG7_FUNC_LCD_CLK 0x670f -#define STM32F429_PG7_FUNC_EVENTOUT 0x6710 -#define STM32F429_PG7_FUNC_ANALOG 0x6711 - -#define STM32F429_PG8_FUNC_GPIO 0x6800 -#define STM32F429_PG8_FUNC_SPI6_NSS 0x6806 -#define STM32F429_PG8_FUNC_USART6_RTS 0x6809 -#define STM32F429_PG8_FUNC_ETH_PPS_OUT 0x680c -#define STM32F429_PG8_FUNC_FMC_SDCLK 0x680d -#define STM32F429_PG8_FUNC_EVENTOUT 0x6810 -#define STM32F429_PG8_FUNC_ANALOG 0x6811 - -#define STM32F429_PG9_FUNC_GPIO 0x6900 -#define STM32F429_PG9_FUNC_USART6_RX 0x6909 -#define STM32F429_PG9_FUNC_FMC_NE2_FMC_NCE3 0x690d -#define STM32F429_PG9_FUNC_DCMI_VSYNC 0x690e -#define STM32F429_PG9_FUNC_EVENTOUT 0x6910 -#define STM32F429_PG9_FUNC_ANALOG 0x6911 - -#define STM32F429_PG10_FUNC_GPIO 0x6a00 -#define STM32F429_PG10_FUNC_LCD_G3 0x6a0a -#define STM32F429_PG10_FUNC_FMC_NCE4_1_FMC_NE3 0x6a0d -#define STM32F429_PG10_FUNC_DCMI_D2 0x6a0e -#define STM32F429_PG10_FUNC_LCD_B2 0x6a0f -#define STM32F429_PG10_FUNC_EVENTOUT 0x6a10 -#define STM32F429_PG10_FUNC_ANALOG 0x6a11 - -#define STM32F429_PG11_FUNC_GPIO 0x6b00 -#define STM32F429_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN 0x6b0c -#define STM32F429_PG11_FUNC_FMC_NCE4_2 0x6b0d -#define STM32F429_PG11_FUNC_DCMI_D3 0x6b0e -#define STM32F429_PG11_FUNC_LCD_B3 0x6b0f -#define STM32F429_PG11_FUNC_EVENTOUT 0x6b10 -#define STM32F429_PG11_FUNC_ANALOG 0x6b11 - -#define STM32F429_PG12_FUNC_GPIO 0x6c00 -#define STM32F429_PG12_FUNC_SPI6_MISO 0x6c06 -#define STM32F429_PG12_FUNC_USART6_RTS 0x6c09 -#define STM32F429_PG12_FUNC_LCD_B4 0x6c0a -#define STM32F429_PG12_FUNC_FMC_NE4 0x6c0d -#define STM32F429_PG12_FUNC_LCD_B1 0x6c0f -#define STM32F429_PG12_FUNC_EVENTOUT 0x6c10 -#define STM32F429_PG12_FUNC_ANALOG 0x6c11 - -#define STM32F429_PG13_FUNC_GPIO 0x6d00 -#define STM32F429_PG13_FUNC_SPI6_SCK 0x6d06 -#define STM32F429_PG13_FUNC_USART6_CTS 0x6d09 -#define STM32F429_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0 0x6d0c -#define STM32F429_PG13_FUNC_FMC_A24 0x6d0d -#define STM32F429_PG13_FUNC_EVENTOUT 0x6d10 -#define STM32F429_PG13_FUNC_ANALOG 0x6d11 - -#define STM32F429_PG14_FUNC_GPIO 0x6e00 -#define STM32F429_PG14_FUNC_SPI6_MOSI 0x6e06 -#define STM32F429_PG14_FUNC_USART6_TX 0x6e09 -#define STM32F429_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1 0x6e0c -#define STM32F429_PG14_FUNC_FMC_A25 0x6e0d -#define STM32F429_PG14_FUNC_EVENTOUT 0x6e10 -#define STM32F429_PG14_FUNC_ANALOG 0x6e11 - -#define STM32F429_PG15_FUNC_GPIO 0x6f00 -#define STM32F429_PG15_FUNC_USART6_CTS 0x6f09 -#define STM32F429_PG15_FUNC_FMC_SDNCAS 0x6f0d -#define STM32F429_PG15_FUNC_DCMI_D13 0x6f0e -#define STM32F429_PG15_FUNC_EVENTOUT 0x6f10 -#define STM32F429_PG15_FUNC_ANALOG 0x6f11 - - - -#define STM32F429_PH0_FUNC_GPIO 0x7000 -#define STM32F429_PH0_FUNC_EVENTOUT 0x7010 -#define STM32F429_PH0_FUNC_ANALOG 0x7011 - -#define STM32F429_PH1_FUNC_GPIO 0x7100 -#define STM32F429_PH1_FUNC_EVENTOUT 0x7110 -#define STM32F429_PH1_FUNC_ANALOG 0x7111 - -#define STM32F429_PH2_FUNC_GPIO 0x7200 -#define STM32F429_PH2_FUNC_ETH_MII_CRS 0x720c -#define STM32F429_PH2_FUNC_FMC_SDCKE0 0x720d -#define STM32F429_PH2_FUNC_LCD_R0 0x720f -#define STM32F429_PH2_FUNC_EVENTOUT 0x7210 -#define STM32F429_PH2_FUNC_ANALOG 0x7211 - -#define STM32F429_PH3_FUNC_GPIO 0x7300 -#define STM32F429_PH3_FUNC_ETH_MII_COL 0x730c -#define STM32F429_PH3_FUNC_FMC_SDNE0 0x730d -#define STM32F429_PH3_FUNC_LCD_R1 0x730f -#define STM32F429_PH3_FUNC_EVENTOUT 0x7310 -#define STM32F429_PH3_FUNC_ANALOG 0x7311 - -#define STM32F429_PH4_FUNC_GPIO 0x7400 -#define STM32F429_PH4_FUNC_I2C2_SCL 0x7405 -#define STM32F429_PH4_FUNC_OTG_HS_ULPI_NXT 0x740b -#define STM32F429_PH4_FUNC_EVENTOUT 0x7410 -#define STM32F429_PH4_FUNC_ANALOG 0x7411 - -#define STM32F429_PH5_FUNC_GPIO 0x7500 -#define STM32F429_PH5_FUNC_I2C2_SDA 0x7505 -#define STM32F429_PH5_FUNC_SPI5_NSS 0x7506 -#define STM32F429_PH5_FUNC_FMC_SDNWE 0x750d -#define STM32F429_PH5_FUNC_EVENTOUT 0x7510 -#define STM32F429_PH5_FUNC_ANALOG 0x7511 - -#define STM32F429_PH6_FUNC_GPIO 0x7600 -#define STM32F429_PH6_FUNC_I2C2_SMBA 0x7605 -#define STM32F429_PH6_FUNC_SPI5_SCK 0x7606 -#define STM32F429_PH6_FUNC_TIM12_CH1 0x760a -#define STM32F429_PH6_FUNC_ETH_MII_RXD2 0x760c -#define STM32F429_PH6_FUNC_FMC_SDNE1 0x760d -#define STM32F429_PH6_FUNC_DCMI_D8 0x760e -#define STM32F429_PH6_FUNC_EVENTOUT 0x7610 -#define STM32F429_PH6_FUNC_ANALOG 0x7611 - -#define STM32F429_PH7_FUNC_GPIO 0x7700 -#define STM32F429_PH7_FUNC_I2C3_SCL 0x7705 -#define STM32F429_PH7_FUNC_SPI5_MISO 0x7706 -#define STM32F429_PH7_FUNC_ETH_MII_RXD3 0x770c -#define STM32F429_PH7_FUNC_FMC_SDCKE1 0x770d -#define STM32F429_PH7_FUNC_DCMI_D9 0x770e -#define STM32F429_PH7_FUNC_EVENTOUT 0x7710 -#define STM32F429_PH7_FUNC_ANALOG 0x7711 - -#define STM32F429_PH8_FUNC_GPIO 0x7800 -#define STM32F429_PH8_FUNC_I2C3_SDA 0x7805 -#define STM32F429_PH8_FUNC_FMC_D16 0x780d -#define STM32F429_PH8_FUNC_DCMI_HSYNC 0x780e -#define STM32F429_PH8_FUNC_LCD_R2 0x780f -#define STM32F429_PH8_FUNC_EVENTOUT 0x7810 -#define STM32F429_PH8_FUNC_ANALOG 0x7811 - -#define STM32F429_PH9_FUNC_GPIO 0x7900 -#define STM32F429_PH9_FUNC_I2C3_SMBA 0x7905 -#define STM32F429_PH9_FUNC_TIM12_CH2 0x790a -#define STM32F429_PH9_FUNC_FMC_D17 0x790d -#define STM32F429_PH9_FUNC_DCMI_D0 0x790e -#define STM32F429_PH9_FUNC_LCD_R3 0x790f -#define STM32F429_PH9_FUNC_EVENTOUT 0x7910 -#define STM32F429_PH9_FUNC_ANALOG 0x7911 - -#define STM32F429_PH10_FUNC_GPIO 0x7a00 -#define STM32F429_PH10_FUNC_TIM5_CH1 0x7a03 -#define STM32F429_PH10_FUNC_FMC_D18 0x7a0d -#define STM32F429_PH10_FUNC_DCMI_D1 0x7a0e -#define STM32F429_PH10_FUNC_LCD_R4 0x7a0f -#define STM32F429_PH10_FUNC_EVENTOUT 0x7a10 -#define STM32F429_PH10_FUNC_ANALOG 0x7a11 - -#define STM32F429_PH11_FUNC_GPIO 0x7b00 -#define STM32F429_PH11_FUNC_TIM5_CH2 0x7b03 -#define STM32F429_PH11_FUNC_FMC_D19 0x7b0d -#define STM32F429_PH11_FUNC_DCMI_D2 0x7b0e -#define STM32F429_PH11_FUNC_LCD_R5 0x7b0f -#define STM32F429_PH11_FUNC_EVENTOUT 0x7b10 -#define STM32F429_PH11_FUNC_ANALOG 0x7b11 - -#define STM32F429_PH12_FUNC_GPIO 0x7c00 -#define STM32F429_PH12_FUNC_TIM5_CH3 0x7c03 -#define STM32F429_PH12_FUNC_FMC_D20 0x7c0d -#define STM32F429_PH12_FUNC_DCMI_D3 0x7c0e -#define STM32F429_PH12_FUNC_LCD_R6 0x7c0f -#define STM32F429_PH12_FUNC_EVENTOUT 0x7c10 -#define STM32F429_PH12_FUNC_ANALOG 0x7c11 - -#define STM32F429_PH13_FUNC_GPIO 0x7d00 -#define STM32F429_PH13_FUNC_TIM8_CH1N 0x7d04 -#define STM32F429_PH13_FUNC_CAN1_TX 0x7d0a -#define STM32F429_PH13_FUNC_FMC_D21 0x7d0d -#define STM32F429_PH13_FUNC_LCD_G2 0x7d0f -#define STM32F429_PH13_FUNC_EVENTOUT 0x7d10 -#define STM32F429_PH13_FUNC_ANALOG 0x7d11 - -#define STM32F429_PH14_FUNC_GPIO 0x7e00 -#define STM32F429_PH14_FUNC_TIM8_CH2N 0x7e04 -#define STM32F429_PH14_FUNC_FMC_D22 0x7e0d -#define STM32F429_PH14_FUNC_DCMI_D4 0x7e0e -#define STM32F429_PH14_FUNC_LCD_G3 0x7e0f -#define STM32F429_PH14_FUNC_EVENTOUT 0x7e10 -#define STM32F429_PH14_FUNC_ANALOG 0x7e11 - -#define STM32F429_PH15_FUNC_GPIO 0x7f00 -#define STM32F429_PH15_FUNC_TIM8_CH3N 0x7f04 -#define STM32F429_PH15_FUNC_FMC_D23 0x7f0d -#define STM32F429_PH15_FUNC_DCMI_D11 0x7f0e -#define STM32F429_PH15_FUNC_LCD_G4 0x7f0f -#define STM32F429_PH15_FUNC_EVENTOUT 0x7f10 -#define STM32F429_PH15_FUNC_ANALOG 0x7f11 - - - -#define STM32F429_PI0_FUNC_GPIO 0x8000 -#define STM32F429_PI0_FUNC_TIM5_CH4 0x8003 -#define STM32F429_PI0_FUNC_SPI2_NSS_I2S2_WS 0x8006 -#define STM32F429_PI0_FUNC_FMC_D24 0x800d -#define STM32F429_PI0_FUNC_DCMI_D13 0x800e -#define STM32F429_PI0_FUNC_LCD_G5 0x800f -#define STM32F429_PI0_FUNC_EVENTOUT 0x8010 -#define STM32F429_PI0_FUNC_ANALOG 0x8011 - -#define STM32F429_PI1_FUNC_GPIO 0x8100 -#define STM32F429_PI1_FUNC_SPI2_SCK_I2S2_CK 0x8106 -#define STM32F429_PI1_FUNC_FMC_D25 0x810d -#define STM32F429_PI1_FUNC_DCMI_D8 0x810e -#define STM32F429_PI1_FUNC_LCD_G6 0x810f -#define STM32F429_PI1_FUNC_EVENTOUT 0x8110 -#define STM32F429_PI1_FUNC_ANALOG 0x8111 - -#define STM32F429_PI2_FUNC_GPIO 0x8200 -#define STM32F429_PI2_FUNC_TIM8_CH4 0x8204 -#define STM32F429_PI2_FUNC_SPI2_MISO 0x8206 -#define STM32F429_PI2_FUNC_I2S2EXT_SD 0x8207 -#define STM32F429_PI2_FUNC_FMC_D26 0x820d -#define STM32F429_PI2_FUNC_DCMI_D9 0x820e -#define STM32F429_PI2_FUNC_LCD_G7 0x820f -#define STM32F429_PI2_FUNC_EVENTOUT 0x8210 -#define STM32F429_PI2_FUNC_ANALOG 0x8211 - -#define STM32F429_PI3_FUNC_GPIO 0x8300 -#define STM32F429_PI3_FUNC_TIM8_ETR 0x8304 -#define STM32F429_PI3_FUNC_SPI2_MOSI_I2S2_SD 0x8306 -#define STM32F429_PI3_FUNC_FMC_D27 0x830d -#define STM32F429_PI3_FUNC_DCMI_D10 0x830e -#define STM32F429_PI3_FUNC_EVENTOUT 0x8310 -#define STM32F429_PI3_FUNC_ANALOG 0x8311 - -#define STM32F429_PI4_FUNC_GPIO 0x8400 -#define STM32F429_PI4_FUNC_TIM8_BKIN 0x8404 -#define STM32F429_PI4_FUNC_FMC_NBL2 0x840d -#define STM32F429_PI4_FUNC_DCMI_D5 0x840e -#define STM32F429_PI4_FUNC_LCD_B4 0x840f -#define STM32F429_PI4_FUNC_EVENTOUT 0x8410 -#define STM32F429_PI4_FUNC_ANALOG 0x8411 - -#define STM32F429_PI5_FUNC_GPIO 0x8500 -#define STM32F429_PI5_FUNC_TIM8_CH1 0x8504 -#define STM32F429_PI5_FUNC_FMC_NBL3 0x850d -#define STM32F429_PI5_FUNC_DCMI_VSYNC 0x850e -#define STM32F429_PI5_FUNC_LCD_B5 0x850f -#define STM32F429_PI5_FUNC_EVENTOUT 0x8510 -#define STM32F429_PI5_FUNC_ANALOG 0x8511 - -#define STM32F429_PI6_FUNC_GPIO 0x8600 -#define STM32F429_PI6_FUNC_TIM8_CH2 0x8604 -#define STM32F429_PI6_FUNC_FMC_D28 0x860d -#define STM32F429_PI6_FUNC_DCMI_D6 0x860e -#define STM32F429_PI6_FUNC_LCD_B6 0x860f -#define STM32F429_PI6_FUNC_EVENTOUT 0x8610 -#define STM32F429_PI6_FUNC_ANALOG 0x8611 - -#define STM32F429_PI7_FUNC_GPIO 0x8700 -#define STM32F429_PI7_FUNC_TIM8_CH3 0x8704 -#define STM32F429_PI7_FUNC_FMC_D29 0x870d -#define STM32F429_PI7_FUNC_DCMI_D7 0x870e -#define STM32F429_PI7_FUNC_LCD_B7 0x870f -#define STM32F429_PI7_FUNC_EVENTOUT 0x8710 -#define STM32F429_PI7_FUNC_ANALOG 0x8711 - -#define STM32F429_PI8_FUNC_GPIO 0x8800 -#define STM32F429_PI8_FUNC_EVENTOUT 0x8810 -#define STM32F429_PI8_FUNC_ANALOG 0x8811 - -#define STM32F429_PI9_FUNC_GPIO 0x8900 -#define STM32F429_PI9_FUNC_CAN1_RX 0x890a -#define STM32F429_PI9_FUNC_FMC_D30 0x890d -#define STM32F429_PI9_FUNC_LCD_VSYNC 0x890f -#define STM32F429_PI9_FUNC_EVENTOUT 0x8910 -#define STM32F429_PI9_FUNC_ANALOG 0x8911 - -#define STM32F429_PI10_FUNC_GPIO 0x8a00 -#define STM32F429_PI10_FUNC_ETH_MII_RX_ER 0x8a0c -#define STM32F429_PI10_FUNC_FMC_D31 0x8a0d -#define STM32F429_PI10_FUNC_LCD_HSYNC 0x8a0f -#define STM32F429_PI10_FUNC_EVENTOUT 0x8a10 -#define STM32F429_PI10_FUNC_ANALOG 0x8a11 - -#define STM32F429_PI11_FUNC_GPIO 0x8b00 -#define STM32F429_PI11_FUNC_OTG_HS_ULPI_DIR 0x8b0b -#define STM32F429_PI11_FUNC_EVENTOUT 0x8b10 -#define STM32F429_PI11_FUNC_ANALOG 0x8b11 - -#define STM32F429_PI12_FUNC_GPIO 0x8c00 -#define STM32F429_PI12_FUNC_LCD_HSYNC 0x8c0f -#define STM32F429_PI12_FUNC_EVENTOUT 0x8c10 -#define STM32F429_PI12_FUNC_ANALOG 0x8c11 - -#define STM32F429_PI13_FUNC_GPIO 0x8d00 -#define STM32F429_PI13_FUNC_LCD_VSYNC 0x8d0f -#define STM32F429_PI13_FUNC_EVENTOUT 0x8d10 -#define STM32F429_PI13_FUNC_ANALOG 0x8d11 - -#define STM32F429_PI14_FUNC_GPIO 0x8e00 -#define STM32F429_PI14_FUNC_LCD_CLK 0x8e0f -#define STM32F429_PI14_FUNC_EVENTOUT 0x8e10 -#define STM32F429_PI14_FUNC_ANALOG 0x8e11 - -#define STM32F429_PI15_FUNC_GPIO 0x8f00 -#define STM32F429_PI15_FUNC_LCD_R0 0x8f0f -#define STM32F429_PI15_FUNC_EVENTOUT 0x8f10 -#define STM32F429_PI15_FUNC_ANALOG 0x8f11 - - - -#define STM32F429_PJ0_FUNC_GPIO 0x9000 -#define STM32F429_PJ0_FUNC_LCD_R1 0x900f -#define STM32F429_PJ0_FUNC_EVENTOUT 0x9010 -#define STM32F429_PJ0_FUNC_ANALOG 0x9011 - -#define STM32F429_PJ1_FUNC_GPIO 0x9100 -#define STM32F429_PJ1_FUNC_LCD_R2 0x910f -#define STM32F429_PJ1_FUNC_EVENTOUT 0x9110 -#define STM32F429_PJ1_FUNC_ANALOG 0x9111 - -#define STM32F429_PJ2_FUNC_GPIO 0x9200 -#define STM32F429_PJ2_FUNC_LCD_R3 0x920f -#define STM32F429_PJ2_FUNC_EVENTOUT 0x9210 -#define STM32F429_PJ2_FUNC_ANALOG 0x9211 - -#define STM32F429_PJ3_FUNC_GPIO 0x9300 -#define STM32F429_PJ3_FUNC_LCD_R4 0x930f -#define STM32F429_PJ3_FUNC_EVENTOUT 0x9310 -#define STM32F429_PJ3_FUNC_ANALOG 0x9311 - -#define STM32F429_PJ4_FUNC_GPIO 0x9400 -#define STM32F429_PJ4_FUNC_LCD_R5 0x940f -#define STM32F429_PJ4_FUNC_EVENTOUT 0x9410 -#define STM32F429_PJ4_FUNC_ANALOG 0x9411 - -#define STM32F429_PJ5_FUNC_GPIO 0x9500 -#define STM32F429_PJ5_FUNC_LCD_R6 0x950f -#define STM32F429_PJ5_FUNC_EVENTOUT 0x9510 -#define STM32F429_PJ5_FUNC_ANALOG 0x9511 - -#define STM32F429_PJ6_FUNC_GPIO 0x9600 -#define STM32F429_PJ6_FUNC_LCD_R7 0x960f -#define STM32F429_PJ6_FUNC_EVENTOUT 0x9610 -#define STM32F429_PJ6_FUNC_ANALOG 0x9611 - -#define STM32F429_PJ7_FUNC_GPIO 0x9700 -#define STM32F429_PJ7_FUNC_LCD_G0 0x970f -#define STM32F429_PJ7_FUNC_EVENTOUT 0x9710 -#define STM32F429_PJ7_FUNC_ANALOG 0x9711 - -#define STM32F429_PJ8_FUNC_GPIO 0x9800 -#define STM32F429_PJ8_FUNC_LCD_G1 0x980f -#define STM32F429_PJ8_FUNC_EVENTOUT 0x9810 -#define STM32F429_PJ8_FUNC_ANALOG 0x9811 - -#define STM32F429_PJ9_FUNC_GPIO 0x9900 -#define STM32F429_PJ9_FUNC_LCD_G2 0x990f -#define STM32F429_PJ9_FUNC_EVENTOUT 0x9910 -#define STM32F429_PJ9_FUNC_ANALOG 0x9911 - -#define STM32F429_PJ10_FUNC_GPIO 0x9a00 -#define STM32F429_PJ10_FUNC_LCD_G3 0x9a0f -#define STM32F429_PJ10_FUNC_EVENTOUT 0x9a10 -#define STM32F429_PJ10_FUNC_ANALOG 0x9a11 - -#define STM32F429_PJ11_FUNC_GPIO 0x9b00 -#define STM32F429_PJ11_FUNC_LCD_G4 0x9b0f -#define STM32F429_PJ11_FUNC_EVENTOUT 0x9b10 -#define STM32F429_PJ11_FUNC_ANALOG 0x9b11 - -#define STM32F429_PJ12_FUNC_GPIO 0x9c00 -#define STM32F429_PJ12_FUNC_LCD_B0 0x9c0f -#define STM32F429_PJ12_FUNC_EVENTOUT 0x9c10 -#define STM32F429_PJ12_FUNC_ANALOG 0x9c11 - -#define STM32F429_PJ13_FUNC_GPIO 0x9d00 -#define STM32F429_PJ13_FUNC_LCD_B1 0x9d0f -#define STM32F429_PJ13_FUNC_EVENTOUT 0x9d10 -#define STM32F429_PJ13_FUNC_ANALOG 0x9d11 - -#define STM32F429_PJ14_FUNC_GPIO 0x9e00 -#define STM32F429_PJ14_FUNC_LCD_B2 0x9e0f -#define STM32F429_PJ14_FUNC_EVENTOUT 0x9e10 -#define STM32F429_PJ14_FUNC_ANALOG 0x9e11 - -#define STM32F429_PJ15_FUNC_GPIO 0x9f00 -#define STM32F429_PJ15_FUNC_LCD_B3 0x9f0f -#define STM32F429_PJ15_FUNC_EVENTOUT 0x9f10 -#define STM32F429_PJ15_FUNC_ANALOG 0x9f11 - - - -#define STM32F429_PK0_FUNC_GPIO 0xa000 -#define STM32F429_PK0_FUNC_LCD_G5 0xa00f -#define STM32F429_PK0_FUNC_EVENTOUT 0xa010 -#define STM32F429_PK0_FUNC_ANALOG 0xa011 - -#define STM32F429_PK1_FUNC_GPIO 0xa100 -#define STM32F429_PK1_FUNC_LCD_G6 0xa10f -#define STM32F429_PK1_FUNC_EVENTOUT 0xa110 -#define STM32F429_PK1_FUNC_ANALOG 0xa111 - -#define STM32F429_PK2_FUNC_GPIO 0xa200 -#define STM32F429_PK2_FUNC_LCD_G7 0xa20f -#define STM32F429_PK2_FUNC_EVENTOUT 0xa210 -#define STM32F429_PK2_FUNC_ANALOG 0xa211 - -#define STM32F429_PK3_FUNC_GPIO 0xa300 -#define STM32F429_PK3_FUNC_LCD_B4 0xa30f -#define STM32F429_PK3_FUNC_EVENTOUT 0xa310 -#define STM32F429_PK3_FUNC_ANALOG 0xa311 - -#define STM32F429_PK4_FUNC_GPIO 0xa400 -#define STM32F429_PK4_FUNC_LCD_B5 0xa40f -#define STM32F429_PK4_FUNC_EVENTOUT 0xa410 -#define STM32F429_PK4_FUNC_ANALOG 0xa411 - -#define STM32F429_PK5_FUNC_GPIO 0xa500 -#define STM32F429_PK5_FUNC_LCD_B6 0xa50f -#define STM32F429_PK5_FUNC_EVENTOUT 0xa510 -#define STM32F429_PK5_FUNC_ANALOG 0xa511 - -#define STM32F429_PK6_FUNC_GPIO 0xa600 -#define STM32F429_PK6_FUNC_LCD_B7 0xa60f -#define STM32F429_PK6_FUNC_EVENTOUT 0xa610 -#define STM32F429_PK6_FUNC_ANALOG 0xa611 - -#define STM32F429_PK7_FUNC_GPIO 0xa700 -#define STM32F429_PK7_FUNC_LCD_DE 0xa70f -#define STM32F429_PK7_FUNC_EVENTOUT 0xa710 -#define STM32F429_PK7_FUNC_ANALOG 0xa711 - -#endif /* _DT_BINDINGS_STM32F429_PINFUNC_H */ diff --git a/sys/gnu/dts/include/dt-bindings/pinctrl/stm32f746-pinfunc.h b/sys/gnu/dts/include/dt-bindings/pinctrl/stm32f746-pinfunc.h deleted file mode 100644 index 4c28f8f4162..00000000000 --- a/sys/gnu/dts/include/dt-bindings/pinctrl/stm32f746-pinfunc.h +++ /dev/null @@ -1,1325 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _DT_BINDINGS_STM32F746_PINFUNC_H -#define _DT_BINDINGS_STM32F746_PINFUNC_H - -#define STM32F746_PA0_FUNC_GPIO 0x0 -#define STM32F746_PA0_FUNC_TIM2_CH1_TIM2_ETR 0x2 -#define STM32F746_PA0_FUNC_TIM5_CH1 0x3 -#define STM32F746_PA0_FUNC_TIM8_ETR 0x4 -#define STM32F746_PA0_FUNC_USART2_CTS 0x8 -#define STM32F746_PA0_FUNC_UART4_TX 0x9 -#define STM32F746_PA0_FUNC_SAI2_SD_B 0xb -#define STM32F746_PA0_FUNC_ETH_MII_CRS 0xc -#define STM32F746_PA0_FUNC_EVENTOUT 0x10 -#define STM32F746_PA0_FUNC_ANALOG 0x11 - -#define STM32F746_PA1_FUNC_GPIO 0x100 -#define STM32F746_PA1_FUNC_TIM2_CH2 0x102 -#define STM32F746_PA1_FUNC_TIM5_CH2 0x103 -#define STM32F746_PA1_FUNC_USART2_RTS 0x108 -#define STM32F746_PA1_FUNC_UART4_RX 0x109 -#define STM32F746_PA1_FUNC_QUADSPI_BK1_IO3 0x10a -#define STM32F746_PA1_FUNC_SAI2_MCLK_B 0x10b -#define STM32F746_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK 0x10c -#define STM32F746_PA1_FUNC_LCD_R2 0x10f -#define STM32F746_PA1_FUNC_EVENTOUT 0x110 -#define STM32F746_PA1_FUNC_ANALOG 0x111 - -#define STM32F746_PA2_FUNC_GPIO 0x200 -#define STM32F746_PA2_FUNC_TIM2_CH3 0x202 -#define STM32F746_PA2_FUNC_TIM5_CH3 0x203 -#define STM32F746_PA2_FUNC_TIM9_CH1 0x204 -#define STM32F746_PA2_FUNC_USART2_TX 0x208 -#define STM32F746_PA2_FUNC_SAI2_SCK_B 0x209 -#define STM32F746_PA2_FUNC_ETH_MDIO 0x20c -#define STM32F746_PA2_FUNC_LCD_R1 0x20f -#define STM32F746_PA2_FUNC_EVENTOUT 0x210 -#define STM32F746_PA2_FUNC_ANALOG 0x211 - -#define STM32F746_PA3_FUNC_GPIO 0x300 -#define STM32F746_PA3_FUNC_TIM2_CH4 0x302 -#define STM32F746_PA3_FUNC_TIM5_CH4 0x303 -#define STM32F746_PA3_FUNC_TIM9_CH2 0x304 -#define STM32F746_PA3_FUNC_USART2_RX 0x308 -#define STM32F746_PA3_FUNC_OTG_HS_ULPI_D0 0x30b -#define STM32F746_PA3_FUNC_ETH_MII_COL 0x30c -#define STM32F746_PA3_FUNC_LCD_B5 0x30f -#define STM32F746_PA3_FUNC_EVENTOUT 0x310 -#define STM32F746_PA3_FUNC_ANALOG 0x311 - -#define STM32F746_PA4_FUNC_GPIO 0x400 -#define STM32F746_PA4_FUNC_SPI1_NSS_I2S1_WS 0x406 -#define STM32F746_PA4_FUNC_SPI3_NSS_I2S3_WS 0x407 -#define STM32F746_PA4_FUNC_USART2_CK 0x408 -#define STM32F746_PA4_FUNC_OTG_HS_SOF 0x40d -#define STM32F746_PA4_FUNC_DCMI_HSYNC 0x40e -#define STM32F746_PA4_FUNC_LCD_VSYNC 0x40f -#define STM32F746_PA4_FUNC_EVENTOUT 0x410 -#define STM32F746_PA4_FUNC_ANALOG 0x411 - -#define STM32F746_PA5_FUNC_GPIO 0x500 -#define STM32F746_PA5_FUNC_TIM2_CH1_TIM2_ETR 0x502 -#define STM32F746_PA5_FUNC_TIM8_CH1N 0x504 -#define STM32F746_PA5_FUNC_SPI1_SCK_I2S1_CK 0x506 -#define STM32F746_PA5_FUNC_OTG_HS_ULPI_CK 0x50b -#define STM32F746_PA5_FUNC_LCD_R4 0x50f -#define STM32F746_PA5_FUNC_EVENTOUT 0x510 -#define STM32F746_PA5_FUNC_ANALOG 0x511 - -#define STM32F746_PA6_FUNC_GPIO 0x600 -#define STM32F746_PA6_FUNC_TIM1_BKIN 0x602 -#define STM32F746_PA6_FUNC_TIM3_CH1 0x603 -#define STM32F746_PA6_FUNC_TIM8_BKIN 0x604 -#define STM32F746_PA6_FUNC_SPI1_MISO 0x606 -#define STM32F746_PA6_FUNC_TIM13_CH1 0x60a -#define STM32F746_PA6_FUNC_DCMI_PIXCLK 0x60e -#define STM32F746_PA6_FUNC_LCD_G2 0x60f -#define STM32F746_PA6_FUNC_EVENTOUT 0x610 -#define STM32F746_PA6_FUNC_ANALOG 0x611 - -#define STM32F746_PA7_FUNC_GPIO 0x700 -#define STM32F746_PA7_FUNC_TIM1_CH1N 0x702 -#define STM32F746_PA7_FUNC_TIM3_CH2 0x703 -#define STM32F746_PA7_FUNC_TIM8_CH1N 0x704 -#define STM32F746_PA7_FUNC_SPI1_MOSI_I2S1_SD 0x706 -#define STM32F746_PA7_FUNC_TIM14_CH1 0x70a -#define STM32F746_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV 0x70c -#define STM32F746_PA7_FUNC_FMC_SDNWE 0x70d -#define STM32F746_PA7_FUNC_EVENTOUT 0x710 -#define STM32F746_PA7_FUNC_ANALOG 0x711 - -#define STM32F746_PA8_FUNC_GPIO 0x800 -#define STM32F746_PA8_FUNC_MCO1 0x801 -#define STM32F746_PA8_FUNC_TIM1_CH1 0x802 -#define STM32F746_PA8_FUNC_TIM8_BKIN2 0x804 -#define STM32F746_PA8_FUNC_I2C3_SCL 0x805 -#define STM32F746_PA8_FUNC_USART1_CK 0x808 -#define STM32F746_PA8_FUNC_OTG_FS_SOF 0x80b -#define STM32F746_PA8_FUNC_LCD_R6 0x80f -#define STM32F746_PA8_FUNC_EVENTOUT 0x810 -#define STM32F746_PA8_FUNC_ANALOG 0x811 - -#define STM32F746_PA9_FUNC_GPIO 0x900 -#define STM32F746_PA9_FUNC_TIM1_CH2 0x902 -#define STM32F746_PA9_FUNC_I2C3_SMBA 0x905 -#define STM32F746_PA9_FUNC_SPI2_SCK_I2S2_CK 0x906 -#define STM32F746_PA9_FUNC_USART1_TX 0x908 -#define STM32F746_PA9_FUNC_DCMI_D0 0x90e -#define STM32F746_PA9_FUNC_EVENTOUT 0x910 -#define STM32F746_PA9_FUNC_ANALOG 0x911 - -#define STM32F746_PA10_FUNC_GPIO 0xa00 -#define STM32F746_PA10_FUNC_TIM1_CH3 0xa02 -#define STM32F746_PA10_FUNC_USART1_RX 0xa08 -#define STM32F746_PA10_FUNC_OTG_FS_ID 0xa0b -#define STM32F746_PA10_FUNC_DCMI_D1 0xa0e -#define STM32F746_PA10_FUNC_EVENTOUT 0xa10 -#define STM32F746_PA10_FUNC_ANALOG 0xa11 - -#define STM32F746_PA11_FUNC_GPIO 0xb00 -#define STM32F746_PA11_FUNC_TIM1_CH4 0xb02 -#define STM32F746_PA11_FUNC_USART1_CTS 0xb08 -#define STM32F746_PA11_FUNC_CAN1_RX 0xb0a -#define STM32F746_PA11_FUNC_OTG_FS_DM 0xb0b -#define STM32F746_PA11_FUNC_LCD_R4 0xb0f -#define STM32F746_PA11_FUNC_EVENTOUT 0xb10 -#define STM32F746_PA11_FUNC_ANALOG 0xb11 - -#define STM32F746_PA12_FUNC_GPIO 0xc00 -#define STM32F746_PA12_FUNC_TIM1_ETR 0xc02 -#define STM32F746_PA12_FUNC_USART1_RTS 0xc08 -#define STM32F746_PA12_FUNC_SAI2_FS_B 0xc09 -#define STM32F746_PA12_FUNC_CAN1_TX 0xc0a -#define STM32F746_PA12_FUNC_OTG_FS_DP 0xc0b -#define STM32F746_PA12_FUNC_LCD_R5 0xc0f -#define STM32F746_PA12_FUNC_EVENTOUT 0xc10 -#define STM32F746_PA12_FUNC_ANALOG 0xc11 - -#define STM32F746_PA13_FUNC_GPIO 0xd00 -#define STM32F746_PA13_FUNC_JTMS_SWDIO 0xd01 -#define STM32F746_PA13_FUNC_EVENTOUT 0xd10 -#define STM32F746_PA13_FUNC_ANALOG 0xd11 - -#define STM32F746_PA14_FUNC_GPIO 0xe00 -#define STM32F746_PA14_FUNC_JTCK_SWCLK 0xe01 -#define STM32F746_PA14_FUNC_EVENTOUT 0xe10 -#define STM32F746_PA14_FUNC_ANALOG 0xe11 - -#define STM32F746_PA15_FUNC_GPIO 0xf00 -#define STM32F746_PA15_FUNC_JTDI 0xf01 -#define STM32F746_PA15_FUNC_TIM2_CH1_TIM2_ETR 0xf02 -#define STM32F746_PA15_FUNC_HDMI_CEC 0xf05 -#define STM32F746_PA15_FUNC_SPI1_NSS_I2S1_WS 0xf06 -#define STM32F746_PA15_FUNC_SPI3_NSS_I2S3_WS 0xf07 -#define STM32F746_PA15_FUNC_UART4_RTS 0xf09 -#define STM32F746_PA15_FUNC_EVENTOUT 0xf10 -#define STM32F746_PA15_FUNC_ANALOG 0xf11 - - -#define STM32F746_PB0_FUNC_GPIO 0x1000 -#define STM32F746_PB0_FUNC_TIM1_CH2N 0x1002 -#define STM32F746_PB0_FUNC_TIM3_CH3 0x1003 -#define STM32F746_PB0_FUNC_TIM8_CH2N 0x1004 -#define STM32F746_PB0_FUNC_UART4_CTS 0x1009 -#define STM32F746_PB0_FUNC_LCD_R3 0x100a -#define STM32F746_PB0_FUNC_OTG_HS_ULPI_D1 0x100b -#define STM32F746_PB0_FUNC_ETH_MII_RXD2 0x100c -#define STM32F746_PB0_FUNC_EVENTOUT 0x1010 -#define STM32F746_PB0_FUNC_ANALOG 0x1011 - -#define STM32F746_PB1_FUNC_GPIO 0x1100 -#define STM32F746_PB1_FUNC_TIM1_CH3N 0x1102 -#define STM32F746_PB1_FUNC_TIM3_CH4 0x1103 -#define STM32F746_PB1_FUNC_TIM8_CH3N 0x1104 -#define STM32F746_PB1_FUNC_LCD_R6 0x110a -#define STM32F746_PB1_FUNC_OTG_HS_ULPI_D2 0x110b -#define STM32F746_PB1_FUNC_ETH_MII_RXD3 0x110c -#define STM32F746_PB1_FUNC_EVENTOUT 0x1110 -#define STM32F746_PB1_FUNC_ANALOG 0x1111 - -#define STM32F746_PB2_FUNC_GPIO 0x1200 -#define STM32F746_PB2_FUNC_SAI1_SD_A 0x1207 -#define STM32F746_PB2_FUNC_SPI3_MOSI_I2S3_SD 0x1208 -#define STM32F746_PB2_FUNC_QUADSPI_CLK 0x120a -#define STM32F746_PB2_FUNC_EVENTOUT 0x1210 -#define STM32F746_PB2_FUNC_ANALOG 0x1211 - -#define STM32F746_PB3_FUNC_GPIO 0x1300 -#define STM32F746_PB3_FUNC_JTDO_TRACESWO 0x1301 -#define STM32F746_PB3_FUNC_TIM2_CH2 0x1302 -#define STM32F746_PB3_FUNC_SPI1_SCK_I2S1_CK 0x1306 -#define STM32F746_PB3_FUNC_SPI3_SCK_I2S3_CK 0x1307 -#define STM32F746_PB3_FUNC_EVENTOUT 0x1310 -#define STM32F746_PB3_FUNC_ANALOG 0x1311 - -#define STM32F746_PB4_FUNC_GPIO 0x1400 -#define STM32F746_PB4_FUNC_NJTRST 0x1401 -#define STM32F746_PB4_FUNC_TIM3_CH1 0x1403 -#define STM32F746_PB4_FUNC_SPI1_MISO 0x1406 -#define STM32F746_PB4_FUNC_SPI3_MISO 0x1407 -#define STM32F746_PB4_FUNC_SPI2_NSS_I2S2_WS 0x1408 -#define STM32F746_PB4_FUNC_EVENTOUT 0x1410 -#define STM32F746_PB4_FUNC_ANALOG 0x1411 - -#define STM32F746_PB5_FUNC_GPIO 0x1500 -#define STM32F746_PB5_FUNC_TIM3_CH2 0x1503 -#define STM32F746_PB5_FUNC_I2C1_SMBA 0x1505 -#define STM32F746_PB5_FUNC_SPI1_MOSI_I2S1_SD 0x1506 -#define STM32F746_PB5_FUNC_SPI3_MOSI_I2S3_SD 0x1507 -#define STM32F746_PB5_FUNC_CAN2_RX 0x150a -#define STM32F746_PB5_FUNC_OTG_HS_ULPI_D7 0x150b -#define STM32F746_PB5_FUNC_ETH_PPS_OUT 0x150c -#define STM32F746_PB5_FUNC_FMC_SDCKE1 0x150d -#define STM32F746_PB5_FUNC_DCMI_D10 0x150e -#define STM32F746_PB5_FUNC_EVENTOUT 0x1510 -#define STM32F746_PB5_FUNC_ANALOG 0x1511 - -#define STM32F746_PB6_FUNC_GPIO 0x1600 -#define STM32F746_PB6_FUNC_TIM4_CH1 0x1603 -#define STM32F746_PB6_FUNC_HDMI_CEC 0x1604 -#define STM32F746_PB6_FUNC_I2C1_SCL 0x1605 -#define STM32F746_PB6_FUNC_USART1_TX 0x1608 -#define STM32F746_PB6_FUNC_CAN2_TX 0x160a -#define STM32F746_PB6_FUNC_QUADSPI_BK1_NCS 0x160b -#define STM32F746_PB6_FUNC_FMC_SDNE1 0x160d -#define STM32F746_PB6_FUNC_DCMI_D5 0x160e -#define STM32F746_PB6_FUNC_EVENTOUT 0x1610 -#define STM32F746_PB6_FUNC_ANALOG 0x1611 - -#define STM32F746_PB7_FUNC_GPIO 0x1700 -#define STM32F746_PB7_FUNC_TIM4_CH2 0x1703 -#define STM32F746_PB7_FUNC_I2C1_SDA 0x1705 -#define STM32F746_PB7_FUNC_USART1_RX 0x1708 -#define STM32F746_PB7_FUNC_FMC_NL 0x170d -#define STM32F746_PB7_FUNC_DCMI_VSYNC 0x170e -#define STM32F746_PB7_FUNC_EVENTOUT 0x1710 -#define STM32F746_PB7_FUNC_ANALOG 0x1711 - -#define STM32F746_PB8_FUNC_GPIO 0x1800 -#define STM32F746_PB8_FUNC_TIM4_CH3 0x1803 -#define STM32F746_PB8_FUNC_TIM10_CH1 0x1804 -#define STM32F746_PB8_FUNC_I2C1_SCL 0x1805 -#define STM32F746_PB8_FUNC_CAN1_RX 0x180a -#define STM32F746_PB8_FUNC_ETH_MII_TXD3 0x180c -#define STM32F746_PB8_FUNC_SDMMC1_D4 0x180d -#define STM32F746_PB8_FUNC_DCMI_D6 0x180e -#define STM32F746_PB8_FUNC_LCD_B6 0x180f -#define STM32F746_PB8_FUNC_EVENTOUT 0x1810 -#define STM32F746_PB8_FUNC_ANALOG 0x1811 - -#define STM32F746_PB9_FUNC_GPIO 0x1900 -#define STM32F746_PB9_FUNC_TIM4_CH4 0x1903 -#define STM32F746_PB9_FUNC_TIM11_CH1 0x1904 -#define STM32F746_PB9_FUNC_I2C1_SDA 0x1905 -#define STM32F746_PB9_FUNC_SPI2_NSS_I2S2_WS 0x1906 -#define STM32F746_PB9_FUNC_CAN1_TX 0x190a -#define STM32F746_PB9_FUNC_SDMMC1_D5 0x190d -#define STM32F746_PB9_FUNC_DCMI_D7 0x190e -#define STM32F746_PB9_FUNC_LCD_B7 0x190f -#define STM32F746_PB9_FUNC_EVENTOUT 0x1910 -#define STM32F746_PB9_FUNC_ANALOG 0x1911 - -#define STM32F746_PB10_FUNC_GPIO 0x1a00 -#define STM32F746_PB10_FUNC_TIM2_CH3 0x1a02 -#define STM32F746_PB10_FUNC_I2C2_SCL 0x1a05 -#define STM32F746_PB10_FUNC_SPI2_SCK_I2S2_CK 0x1a06 -#define STM32F746_PB10_FUNC_USART3_TX 0x1a08 -#define STM32F746_PB10_FUNC_OTG_HS_ULPI_D3 0x1a0b -#define STM32F746_PB10_FUNC_ETH_MII_RX_ER 0x1a0c -#define STM32F746_PB10_FUNC_LCD_G4 0x1a0f -#define STM32F746_PB10_FUNC_EVENTOUT 0x1a10 -#define STM32F746_PB10_FUNC_ANALOG 0x1a11 - -#define STM32F746_PB11_FUNC_GPIO 0x1b00 -#define STM32F746_PB11_FUNC_TIM2_CH4 0x1b02 -#define STM32F746_PB11_FUNC_I2C2_SDA 0x1b05 -#define STM32F746_PB11_FUNC_USART3_RX 0x1b08 -#define STM32F746_PB11_FUNC_OTG_HS_ULPI_D4 0x1b0b -#define STM32F746_PB11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN 0x1b0c -#define STM32F746_PB11_FUNC_LCD_G5 0x1b0f -#define STM32F746_PB11_FUNC_EVENTOUT 0x1b10 -#define STM32F746_PB11_FUNC_ANALOG 0x1b11 - -#define STM32F746_PB12_FUNC_GPIO 0x1c00 -#define STM32F746_PB12_FUNC_TIM1_BKIN 0x1c02 -#define STM32F746_PB12_FUNC_I2C2_SMBA 0x1c05 -#define STM32F746_PB12_FUNC_SPI2_NSS_I2S2_WS 0x1c06 -#define STM32F746_PB12_FUNC_USART3_CK 0x1c08 -#define STM32F746_PB12_FUNC_CAN2_RX 0x1c0a -#define STM32F746_PB12_FUNC_OTG_HS_ULPI_D5 0x1c0b -#define STM32F746_PB12_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0 0x1c0c -#define STM32F746_PB12_FUNC_OTG_HS_ID 0x1c0d -#define STM32F746_PB12_FUNC_EVENTOUT 0x1c10 -#define STM32F746_PB12_FUNC_ANALOG 0x1c11 - -#define STM32F746_PB13_FUNC_GPIO 0x1d00 -#define STM32F746_PB13_FUNC_TIM1_CH1N 0x1d02 -#define STM32F746_PB13_FUNC_SPI2_SCK_I2S2_CK 0x1d06 -#define STM32F746_PB13_FUNC_USART3_CTS 0x1d08 -#define STM32F746_PB13_FUNC_CAN2_TX 0x1d0a -#define STM32F746_PB13_FUNC_OTG_HS_ULPI_D6 0x1d0b -#define STM32F746_PB13_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1 0x1d0c -#define STM32F746_PB13_FUNC_EVENTOUT 0x1d10 -#define STM32F746_PB13_FUNC_ANALOG 0x1d11 - -#define STM32F746_PB14_FUNC_GPIO 0x1e00 -#define STM32F746_PB14_FUNC_TIM1_CH2N 0x1e02 -#define STM32F746_PB14_FUNC_TIM8_CH2N 0x1e04 -#define STM32F746_PB14_FUNC_SPI2_MISO 0x1e06 -#define STM32F746_PB14_FUNC_USART3_RTS 0x1e08 -#define STM32F746_PB14_FUNC_TIM12_CH1 0x1e0a -#define STM32F746_PB14_FUNC_OTG_HS_DM 0x1e0d -#define STM32F746_PB14_FUNC_EVENTOUT 0x1e10 -#define STM32F746_PB14_FUNC_ANALOG 0x1e11 - -#define STM32F746_PB15_FUNC_GPIO 0x1f00 -#define STM32F746_PB15_FUNC_RTC_REFIN 0x1f01 -#define STM32F746_PB15_FUNC_TIM1_CH3N 0x1f02 -#define STM32F746_PB15_FUNC_TIM8_CH3N 0x1f04 -#define STM32F746_PB15_FUNC_SPI2_MOSI_I2S2_SD 0x1f06 -#define STM32F746_PB15_FUNC_TIM12_CH2 0x1f0a -#define STM32F746_PB15_FUNC_OTG_HS_DP 0x1f0d -#define STM32F746_PB15_FUNC_EVENTOUT 0x1f10 -#define STM32F746_PB15_FUNC_ANALOG 0x1f11 - - -#define STM32F746_PC0_FUNC_GPIO 0x2000 -#define STM32F746_PC0_FUNC_SAI2_FS_B 0x2009 -#define STM32F746_PC0_FUNC_OTG_HS_ULPI_STP 0x200b -#define STM32F746_PC0_FUNC_FMC_SDNWE 0x200d -#define STM32F746_PC0_FUNC_LCD_R5 0x200f -#define STM32F746_PC0_FUNC_EVENTOUT 0x2010 -#define STM32F746_PC0_FUNC_ANALOG 0x2011 - -#define STM32F746_PC1_FUNC_GPIO 0x2100 -#define STM32F746_PC1_FUNC_TRACED0 0x2101 -#define STM32F746_PC1_FUNC_SPI2_MOSI_I2S2_SD 0x2106 -#define STM32F746_PC1_FUNC_SAI1_SD_A 0x2107 -#define STM32F746_PC1_FUNC_ETH_MDC 0x210c -#define STM32F746_PC1_FUNC_EVENTOUT 0x2110 -#define STM32F746_PC1_FUNC_ANALOG 0x2111 - -#define STM32F746_PC2_FUNC_GPIO 0x2200 -#define STM32F746_PC2_FUNC_SPI2_MISO 0x2206 -#define STM32F746_PC2_FUNC_OTG_HS_ULPI_DIR 0x220b -#define STM32F746_PC2_FUNC_ETH_MII_TXD2 0x220c -#define STM32F746_PC2_FUNC_FMC_SDNE0 0x220d -#define STM32F746_PC2_FUNC_EVENTOUT 0x2210 -#define STM32F746_PC2_FUNC_ANALOG 0x2211 - -#define STM32F746_PC3_FUNC_GPIO 0x2300 -#define STM32F746_PC3_FUNC_SPI2_MOSI_I2S2_SD 0x2306 -#define STM32F746_PC3_FUNC_OTG_HS_ULPI_NXT 0x230b -#define STM32F746_PC3_FUNC_ETH_MII_TX_CLK 0x230c -#define STM32F746_PC3_FUNC_FMC_SDCKE0 0x230d -#define STM32F746_PC3_FUNC_EVENTOUT 0x2310 -#define STM32F746_PC3_FUNC_ANALOG 0x2311 - -#define STM32F746_PC4_FUNC_GPIO 0x2400 -#define STM32F746_PC4_FUNC_I2S1_MCK 0x2406 -#define STM32F746_PC4_FUNC_SPDIFRX_IN2 0x2409 -#define STM32F746_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0 0x240c -#define STM32F746_PC4_FUNC_FMC_SDNE0 0x240d -#define STM32F746_PC4_FUNC_EVENTOUT 0x2410 -#define STM32F746_PC4_FUNC_ANALOG 0x2411 - -#define STM32F746_PC5_FUNC_GPIO 0x2500 -#define STM32F746_PC5_FUNC_SPDIFRX_IN3 0x2509 -#define STM32F746_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1 0x250c -#define STM32F746_PC5_FUNC_FMC_SDCKE0 0x250d -#define STM32F746_PC5_FUNC_EVENTOUT 0x2510 -#define STM32F746_PC5_FUNC_ANALOG 0x2511 - -#define STM32F746_PC6_FUNC_GPIO 0x2600 -#define STM32F746_PC6_FUNC_TIM3_CH1 0x2603 -#define STM32F746_PC6_FUNC_TIM8_CH1 0x2604 -#define STM32F746_PC6_FUNC_I2S2_MCK 0x2606 -#define STM32F746_PC6_FUNC_USART6_TX 0x2609 -#define STM32F746_PC6_FUNC_SDMMC1_D6 0x260d -#define STM32F746_PC6_FUNC_DCMI_D0 0x260e -#define STM32F746_PC6_FUNC_LCD_HSYNC 0x260f -#define STM32F746_PC6_FUNC_EVENTOUT 0x2610 -#define STM32F746_PC6_FUNC_ANALOG 0x2611 - -#define STM32F746_PC7_FUNC_GPIO 0x2700 -#define STM32F746_PC7_FUNC_TIM3_CH2 0x2703 -#define STM32F746_PC7_FUNC_TIM8_CH2 0x2704 -#define STM32F746_PC7_FUNC_I2S3_MCK 0x2707 -#define STM32F746_PC7_FUNC_USART6_RX 0x2709 -#define STM32F746_PC7_FUNC_SDMMC1_D7 0x270d -#define STM32F746_PC7_FUNC_DCMI_D1 0x270e -#define STM32F746_PC7_FUNC_LCD_G6 0x270f -#define STM32F746_PC7_FUNC_EVENTOUT 0x2710 -#define STM32F746_PC7_FUNC_ANALOG 0x2711 - -#define STM32F746_PC8_FUNC_GPIO 0x2800 -#define STM32F746_PC8_FUNC_TRACED1 0x2801 -#define STM32F746_PC8_FUNC_TIM3_CH3 0x2803 -#define STM32F746_PC8_FUNC_TIM8_CH3 0x2804 -#define STM32F746_PC8_FUNC_UART5_RTS 0x2808 -#define STM32F746_PC8_FUNC_USART6_CK 0x2809 -#define STM32F746_PC8_FUNC_SDMMC1_D0 0x280d -#define STM32F746_PC8_FUNC_DCMI_D2 0x280e -#define STM32F746_PC8_FUNC_EVENTOUT 0x2810 -#define STM32F746_PC8_FUNC_ANALOG 0x2811 - -#define STM32F746_PC9_FUNC_GPIO 0x2900 -#define STM32F746_PC9_FUNC_MCO2 0x2901 -#define STM32F746_PC9_FUNC_TIM3_CH4 0x2903 -#define STM32F746_PC9_FUNC_TIM8_CH4 0x2904 -#define STM32F746_PC9_FUNC_I2C3_SDA 0x2905 -#define STM32F746_PC9_FUNC_I2S_CKIN 0x2906 -#define STM32F746_PC9_FUNC_UART5_CTS 0x2908 -#define STM32F746_PC9_FUNC_QUADSPI_BK1_IO0 0x290a -#define STM32F746_PC9_FUNC_SDMMC1_D1 0x290d -#define STM32F746_PC9_FUNC_DCMI_D3 0x290e -#define STM32F746_PC9_FUNC_EVENTOUT 0x2910 -#define STM32F746_PC9_FUNC_ANALOG 0x2911 - -#define STM32F746_PC10_FUNC_GPIO 0x2a00 -#define STM32F746_PC10_FUNC_SPI3_SCK_I2S3_CK 0x2a07 -#define STM32F746_PC10_FUNC_USART3_TX 0x2a08 -#define STM32F746_PC10_FUNC_UART4_TX 0x2a09 -#define STM32F746_PC10_FUNC_QUADSPI_BK1_IO1 0x2a0a -#define STM32F746_PC10_FUNC_SDMMC1_D2 0x2a0d -#define STM32F746_PC10_FUNC_DCMI_D8 0x2a0e -#define STM32F746_PC10_FUNC_LCD_R2 0x2a0f -#define STM32F746_PC10_FUNC_EVENTOUT 0x2a10 -#define STM32F746_PC10_FUNC_ANALOG 0x2a11 - -#define STM32F746_PC11_FUNC_GPIO 0x2b00 -#define STM32F746_PC11_FUNC_SPI3_MISO 0x2b07 -#define STM32F746_PC11_FUNC_USART3_RX 0x2b08 -#define STM32F746_PC11_FUNC_UART4_RX 0x2b09 -#define STM32F746_PC11_FUNC_QUADSPI_BK2_NCS 0x2b0a -#define STM32F746_PC11_FUNC_SDMMC1_D3 0x2b0d -#define STM32F746_PC11_FUNC_DCMI_D4 0x2b0e -#define STM32F746_PC11_FUNC_EVENTOUT 0x2b10 -#define STM32F746_PC11_FUNC_ANALOG 0x2b11 - -#define STM32F746_PC12_FUNC_GPIO 0x2c00 -#define STM32F746_PC12_FUNC_TRACED3 0x2c01 -#define STM32F746_PC12_FUNC_SPI3_MOSI_I2S3_SD 0x2c07 -#define STM32F746_PC12_FUNC_USART3_CK 0x2c08 -#define STM32F746_PC12_FUNC_UART5_TX 0x2c09 -#define STM32F746_PC12_FUNC_SDMMC1_CK 0x2c0d -#define STM32F746_PC12_FUNC_DCMI_D9 0x2c0e -#define STM32F746_PC12_FUNC_EVENTOUT 0x2c10 -#define STM32F746_PC12_FUNC_ANALOG 0x2c11 - -#define STM32F746_PC13_FUNC_GPIO 0x2d00 -#define STM32F746_PC13_FUNC_EVENTOUT 0x2d10 -#define STM32F746_PC13_FUNC_ANALOG 0x2d11 - -#define STM32F746_PC14_FUNC_GPIO 0x2e00 -#define STM32F746_PC14_FUNC_EVENTOUT 0x2e10 -#define STM32F746_PC14_FUNC_ANALOG 0x2e11 - -#define STM32F746_PC15_FUNC_GPIO 0x2f00 -#define STM32F746_PC15_FUNC_EVENTOUT 0x2f10 -#define STM32F746_PC15_FUNC_ANALOG 0x2f11 - - -#define STM32F746_PD0_FUNC_GPIO 0x3000 -#define STM32F746_PD0_FUNC_CAN1_RX 0x300a -#define STM32F746_PD0_FUNC_FMC_D2 0x300d -#define STM32F746_PD0_FUNC_EVENTOUT 0x3010 -#define STM32F746_PD0_FUNC_ANALOG 0x3011 - -#define STM32F746_PD1_FUNC_GPIO 0x3100 -#define STM32F746_PD1_FUNC_CAN1_TX 0x310a -#define STM32F746_PD1_FUNC_FMC_D3 0x310d -#define STM32F746_PD1_FUNC_EVENTOUT 0x3110 -#define STM32F746_PD1_FUNC_ANALOG 0x3111 - -#define STM32F746_PD2_FUNC_GPIO 0x3200 -#define STM32F746_PD2_FUNC_TRACED2 0x3201 -#define STM32F746_PD2_FUNC_TIM3_ETR 0x3203 -#define STM32F746_PD2_FUNC_UART5_RX 0x3209 -#define STM32F746_PD2_FUNC_SDMMC1_CMD 0x320d -#define STM32F746_PD2_FUNC_DCMI_D11 0x320e -#define STM32F746_PD2_FUNC_EVENTOUT 0x3210 -#define STM32F746_PD2_FUNC_ANALOG 0x3211 - -#define STM32F746_PD3_FUNC_GPIO 0x3300 -#define STM32F746_PD3_FUNC_SPI2_SCK_I2S2_CK 0x3306 -#define STM32F746_PD3_FUNC_USART2_CTS 0x3308 -#define STM32F746_PD3_FUNC_FMC_CLK 0x330d -#define STM32F746_PD3_FUNC_DCMI_D5 0x330e -#define STM32F746_PD3_FUNC_LCD_G7 0x330f -#define STM32F746_PD3_FUNC_EVENTOUT 0x3310 -#define STM32F746_PD3_FUNC_ANALOG 0x3311 - -#define STM32F746_PD4_FUNC_GPIO 0x3400 -#define STM32F746_PD4_FUNC_USART2_RTS 0x3408 -#define STM32F746_PD4_FUNC_FMC_NOE 0x340d -#define STM32F746_PD4_FUNC_EVENTOUT 0x3410 -#define STM32F746_PD4_FUNC_ANALOG 0x3411 - -#define STM32F746_PD5_FUNC_GPIO 0x3500 -#define STM32F746_PD5_FUNC_USART2_TX 0x3508 -#define STM32F746_PD5_FUNC_FMC_NWE 0x350d -#define STM32F746_PD5_FUNC_EVENTOUT 0x3510 -#define STM32F746_PD5_FUNC_ANALOG 0x3511 - -#define STM32F746_PD6_FUNC_GPIO 0x3600 -#define STM32F746_PD6_FUNC_SPI3_MOSI_I2S3_SD 0x3606 -#define STM32F746_PD6_FUNC_SAI1_SD_A 0x3607 -#define STM32F746_PD6_FUNC_USART2_RX 0x3608 -#define STM32F746_PD6_FUNC_FMC_NWAIT 0x360d -#define STM32F746_PD6_FUNC_DCMI_D10 0x360e -#define STM32F746_PD6_FUNC_LCD_B2 0x360f -#define STM32F746_PD6_FUNC_EVENTOUT 0x3610 -#define STM32F746_PD6_FUNC_ANALOG 0x3611 - -#define STM32F746_PD7_FUNC_GPIO 0x3700 -#define STM32F746_PD7_FUNC_USART2_CK 0x3708 -#define STM32F746_PD7_FUNC_SPDIFRX_IN0 0x3709 -#define STM32F746_PD7_FUNC_FMC_NE1 0x370d -#define STM32F746_PD7_FUNC_EVENTOUT 0x3710 -#define STM32F746_PD7_FUNC_ANALOG 0x3711 - -#define STM32F746_PD8_FUNC_GPIO 0x3800 -#define STM32F746_PD8_FUNC_USART3_TX 0x3808 -#define STM32F746_PD8_FUNC_SPDIFRX_IN1 0x3809 -#define STM32F746_PD8_FUNC_FMC_D13 0x380d -#define STM32F746_PD8_FUNC_EVENTOUT 0x3810 -#define STM32F746_PD8_FUNC_ANALOG 0x3811 - -#define STM32F746_PD9_FUNC_GPIO 0x3900 -#define STM32F746_PD9_FUNC_USART3_RX 0x3908 -#define STM32F746_PD9_FUNC_FMC_D14 0x390d -#define STM32F746_PD9_FUNC_EVENTOUT 0x3910 -#define STM32F746_PD9_FUNC_ANALOG 0x3911 - -#define STM32F746_PD10_FUNC_GPIO 0x3a00 -#define STM32F746_PD10_FUNC_USART3_CK 0x3a08 -#define STM32F746_PD10_FUNC_FMC_D15 0x3a0d -#define STM32F746_PD10_FUNC_LCD_B3 0x3a0f -#define STM32F746_PD10_FUNC_EVENTOUT 0x3a10 -#define STM32F746_PD10_FUNC_ANALOG 0x3a11 - -#define STM32F746_PD11_FUNC_GPIO 0x3b00 -#define STM32F746_PD11_FUNC_I2C4_SMBA 0x3b05 -#define STM32F746_PD11_FUNC_USART3_CTS 0x3b08 -#define STM32F746_PD11_FUNC_QUADSPI_BK1_IO0 0x3b0a -#define STM32F746_PD11_FUNC_SAI2_SD_A 0x3b0b -#define STM32F746_PD11_FUNC_FMC_A16_FMC_CLE 0x3b0d -#define STM32F746_PD11_FUNC_EVENTOUT 0x3b10 -#define STM32F746_PD11_FUNC_ANALOG 0x3b11 - -#define STM32F746_PD12_FUNC_GPIO 0x3c00 -#define STM32F746_PD12_FUNC_TIM4_CH1 0x3c03 -#define STM32F746_PD12_FUNC_LPTIM1_IN1 0x3c04 -#define STM32F746_PD12_FUNC_I2C4_SCL 0x3c05 -#define STM32F746_PD12_FUNC_USART3_RTS 0x3c08 -#define STM32F746_PD12_FUNC_QUADSPI_BK1_IO1 0x3c0a -#define STM32F746_PD12_FUNC_SAI2_FS_A 0x3c0b -#define STM32F746_PD12_FUNC_FMC_A17_FMC_ALE 0x3c0d -#define STM32F746_PD12_FUNC_EVENTOUT 0x3c10 -#define STM32F746_PD12_FUNC_ANALOG 0x3c11 - -#define STM32F746_PD13_FUNC_GPIO 0x3d00 -#define STM32F746_PD13_FUNC_TIM4_CH2 0x3d03 -#define STM32F746_PD13_FUNC_LPTIM1_OUT 0x3d04 -#define STM32F746_PD13_FUNC_I2C4_SDA 0x3d05 -#define STM32F746_PD13_FUNC_QUADSPI_BK1_IO3 0x3d0a -#define STM32F746_PD13_FUNC_SAI2_SCK_A 0x3d0b -#define STM32F746_PD13_FUNC_FMC_A18 0x3d0d -#define STM32F746_PD13_FUNC_EVENTOUT 0x3d10 -#define STM32F746_PD13_FUNC_ANALOG 0x3d11 - -#define STM32F746_PD14_FUNC_GPIO 0x3e00 -#define STM32F746_PD14_FUNC_TIM4_CH3 0x3e03 -#define STM32F746_PD14_FUNC_UART8_CTS 0x3e09 -#define STM32F746_PD14_FUNC_FMC_D0 0x3e0d -#define STM32F746_PD14_FUNC_EVENTOUT 0x3e10 -#define STM32F746_PD14_FUNC_ANALOG 0x3e11 - -#define STM32F746_PD15_FUNC_GPIO 0x3f00 -#define STM32F746_PD15_FUNC_TIM4_CH4 0x3f03 -#define STM32F746_PD15_FUNC_UART8_RTS 0x3f09 -#define STM32F746_PD15_FUNC_FMC_D1 0x3f0d -#define STM32F746_PD15_FUNC_EVENTOUT 0x3f10 -#define STM32F746_PD15_FUNC_ANALOG 0x3f11 - - -#define STM32F746_PE0_FUNC_GPIO 0x4000 -#define STM32F746_PE0_FUNC_TIM4_ETR 0x4003 -#define STM32F746_PE0_FUNC_LPTIM1_ETR 0x4004 -#define STM32F746_PE0_FUNC_UART8_RX 0x4009 -#define STM32F746_PE0_FUNC_SAI2_MCLK_A 0x400b -#define STM32F746_PE0_FUNC_FMC_NBL0 0x400d -#define STM32F746_PE0_FUNC_DCMI_D2 0x400e -#define STM32F746_PE0_FUNC_EVENTOUT 0x4010 -#define STM32F746_PE0_FUNC_ANALOG 0x4011 - -#define STM32F746_PE1_FUNC_GPIO 0x4100 -#define STM32F746_PE1_FUNC_LPTIM1_IN2 0x4104 -#define STM32F746_PE1_FUNC_UART8_TX 0x4109 -#define STM32F746_PE1_FUNC_FMC_NBL1 0x410d -#define STM32F746_PE1_FUNC_DCMI_D3 0x410e -#define STM32F746_PE1_FUNC_EVENTOUT 0x4110 -#define STM32F746_PE1_FUNC_ANALOG 0x4111 - -#define STM32F746_PE2_FUNC_GPIO 0x4200 -#define STM32F746_PE2_FUNC_TRACECLK 0x4201 -#define STM32F746_PE2_FUNC_SPI4_SCK 0x4206 -#define STM32F746_PE2_FUNC_SAI1_MCLK_A 0x4207 -#define STM32F746_PE2_FUNC_QUADSPI_BK1_IO2 0x420a -#define STM32F746_PE2_FUNC_ETH_MII_TXD3 0x420c -#define STM32F746_PE2_FUNC_FMC_A23 0x420d -#define STM32F746_PE2_FUNC_EVENTOUT 0x4210 -#define STM32F746_PE2_FUNC_ANALOG 0x4211 - -#define STM32F746_PE3_FUNC_GPIO 0x4300 -#define STM32F746_PE3_FUNC_TRACED0 0x4301 -#define STM32F746_PE3_FUNC_SAI1_SD_B 0x4307 -#define STM32F746_PE3_FUNC_FMC_A19 0x430d -#define STM32F746_PE3_FUNC_EVENTOUT 0x4310 -#define STM32F746_PE3_FUNC_ANALOG 0x4311 - -#define STM32F746_PE4_FUNC_GPIO 0x4400 -#define STM32F746_PE4_FUNC_TRACED1 0x4401 -#define STM32F746_PE4_FUNC_SPI4_NSS 0x4406 -#define STM32F746_PE4_FUNC_SAI1_FS_A 0x4407 -#define STM32F746_PE4_FUNC_FMC_A20 0x440d -#define STM32F746_PE4_FUNC_DCMI_D4 0x440e -#define STM32F746_PE4_FUNC_LCD_B0 0x440f -#define STM32F746_PE4_FUNC_EVENTOUT 0x4410 -#define STM32F746_PE4_FUNC_ANALOG 0x4411 - -#define STM32F746_PE5_FUNC_GPIO 0x4500 -#define STM32F746_PE5_FUNC_TRACED2 0x4501 -#define STM32F746_PE5_FUNC_TIM9_CH1 0x4504 -#define STM32F746_PE5_FUNC_SPI4_MISO 0x4506 -#define STM32F746_PE5_FUNC_SAI1_SCK_A 0x4507 -#define STM32F746_PE5_FUNC_FMC_A21 0x450d -#define STM32F746_PE5_FUNC_DCMI_D6 0x450e -#define STM32F746_PE5_FUNC_LCD_G0 0x450f -#define STM32F746_PE5_FUNC_EVENTOUT 0x4510 -#define STM32F746_PE5_FUNC_ANALOG 0x4511 - -#define STM32F746_PE6_FUNC_GPIO 0x4600 -#define STM32F746_PE6_FUNC_TRACED3 0x4601 -#define STM32F746_PE6_FUNC_TIM1_BKIN2 0x4602 -#define STM32F746_PE6_FUNC_TIM9_CH2 0x4604 -#define STM32F746_PE6_FUNC_SPI4_MOSI 0x4606 -#define STM32F746_PE6_FUNC_SAI1_SD_A 0x4607 -#define STM32F746_PE6_FUNC_SAI2_MCLK_B 0x460b -#define STM32F746_PE6_FUNC_FMC_A22 0x460d -#define STM32F746_PE6_FUNC_DCMI_D7 0x460e -#define STM32F746_PE6_FUNC_LCD_G1 0x460f -#define STM32F746_PE6_FUNC_EVENTOUT 0x4610 -#define STM32F746_PE6_FUNC_ANALOG 0x4611 - -#define STM32F746_PE7_FUNC_GPIO 0x4700 -#define STM32F746_PE7_FUNC_TIM1_ETR 0x4702 -#define STM32F746_PE7_FUNC_UART7_RX 0x4709 -#define STM32F746_PE7_FUNC_QUADSPI_BK2_IO0 0x470b -#define STM32F746_PE7_FUNC_FMC_D4 0x470d -#define STM32F746_PE7_FUNC_EVENTOUT 0x4710 -#define STM32F746_PE7_FUNC_ANALOG 0x4711 - -#define STM32F746_PE8_FUNC_GPIO 0x4800 -#define STM32F746_PE8_FUNC_TIM1_CH1N 0x4802 -#define STM32F746_PE8_FUNC_UART7_TX 0x4809 -#define STM32F746_PE8_FUNC_QUADSPI_BK2_IO1 0x480b -#define STM32F746_PE8_FUNC_FMC_D5 0x480d -#define STM32F746_PE8_FUNC_EVENTOUT 0x4810 -#define STM32F746_PE8_FUNC_ANALOG 0x4811 - -#define STM32F746_PE9_FUNC_GPIO 0x4900 -#define STM32F746_PE9_FUNC_TIM1_CH1 0x4902 -#define STM32F746_PE9_FUNC_UART7_RTS 0x4909 -#define STM32F746_PE9_FUNC_QUADSPI_BK2_IO2 0x490b -#define STM32F746_PE9_FUNC_FMC_D6 0x490d -#define STM32F746_PE9_FUNC_EVENTOUT 0x4910 -#define STM32F746_PE9_FUNC_ANALOG 0x4911 - -#define STM32F746_PE10_FUNC_GPIO 0x4a00 -#define STM32F746_PE10_FUNC_TIM1_CH2N 0x4a02 -#define STM32F746_PE10_FUNC_UART7_CTS 0x4a09 -#define STM32F746_PE10_FUNC_QUADSPI_BK2_IO3 0x4a0b -#define STM32F746_PE10_FUNC_FMC_D7 0x4a0d -#define STM32F746_PE10_FUNC_EVENTOUT 0x4a10 -#define STM32F746_PE10_FUNC_ANALOG 0x4a11 - -#define STM32F746_PE11_FUNC_GPIO 0x4b00 -#define STM32F746_PE11_FUNC_TIM1_CH2 0x4b02 -#define STM32F746_PE11_FUNC_SPI4_NSS 0x4b06 -#define STM32F746_PE11_FUNC_SAI2_SD_B 0x4b0b -#define STM32F746_PE11_FUNC_FMC_D8 0x4b0d -#define STM32F746_PE11_FUNC_LCD_G3 0x4b0f -#define STM32F746_PE11_FUNC_EVENTOUT 0x4b10 -#define STM32F746_PE11_FUNC_ANALOG 0x4b11 - -#define STM32F746_PE12_FUNC_GPIO 0x4c00 -#define STM32F746_PE12_FUNC_TIM1_CH3N 0x4c02 -#define STM32F746_PE12_FUNC_SPI4_SCK 0x4c06 -#define STM32F746_PE12_FUNC_SAI2_SCK_B 0x4c0b -#define STM32F746_PE12_FUNC_FMC_D9 0x4c0d -#define STM32F746_PE12_FUNC_LCD_B4 0x4c0f -#define STM32F746_PE12_FUNC_EVENTOUT 0x4c10 -#define STM32F746_PE12_FUNC_ANALOG 0x4c11 - -#define STM32F746_PE13_FUNC_GPIO 0x4d00 -#define STM32F746_PE13_FUNC_TIM1_CH3 0x4d02 -#define STM32F746_PE13_FUNC_SPI4_MISO 0x4d06 -#define STM32F746_PE13_FUNC_SAI2_FS_B 0x4d0b -#define STM32F746_PE13_FUNC_FMC_D10 0x4d0d -#define STM32F746_PE13_FUNC_LCD_DE 0x4d0f -#define STM32F746_PE13_FUNC_EVENTOUT 0x4d10 -#define STM32F746_PE13_FUNC_ANALOG 0x4d11 - -#define STM32F746_PE14_FUNC_GPIO 0x4e00 -#define STM32F746_PE14_FUNC_TIM1_CH4 0x4e02 -#define STM32F746_PE14_FUNC_SPI4_MOSI 0x4e06 -#define STM32F746_PE14_FUNC_SAI2_MCLK_B 0x4e0b -#define STM32F746_PE14_FUNC_FMC_D11 0x4e0d -#define STM32F746_PE14_FUNC_LCD_CLK 0x4e0f -#define STM32F746_PE14_FUNC_EVENTOUT 0x4e10 -#define STM32F746_PE14_FUNC_ANALOG 0x4e11 - -#define STM32F746_PE15_FUNC_GPIO 0x4f00 -#define STM32F746_PE15_FUNC_TIM1_BKIN 0x4f02 -#define STM32F746_PE15_FUNC_FMC_D12 0x4f0d -#define STM32F746_PE15_FUNC_LCD_R7 0x4f0f -#define STM32F746_PE15_FUNC_EVENTOUT 0x4f10 -#define STM32F746_PE15_FUNC_ANALOG 0x4f11 - - -#define STM32F746_PF0_FUNC_GPIO 0x5000 -#define STM32F746_PF0_FUNC_I2C2_SDA 0x5005 -#define STM32F746_PF0_FUNC_FMC_A0 0x500d -#define STM32F746_PF0_FUNC_EVENTOUT 0x5010 -#define STM32F746_PF0_FUNC_ANALOG 0x5011 - -#define STM32F746_PF1_FUNC_GPIO 0x5100 -#define STM32F746_PF1_FUNC_I2C2_SCL 0x5105 -#define STM32F746_PF1_FUNC_FMC_A1 0x510d -#define STM32F746_PF1_FUNC_EVENTOUT 0x5110 -#define STM32F746_PF1_FUNC_ANALOG 0x5111 - -#define STM32F746_PF2_FUNC_GPIO 0x5200 -#define STM32F746_PF2_FUNC_I2C2_SMBA 0x5205 -#define STM32F746_PF2_FUNC_FMC_A2 0x520d -#define STM32F746_PF2_FUNC_EVENTOUT 0x5210 -#define STM32F746_PF2_FUNC_ANALOG 0x5211 - -#define STM32F746_PF3_FUNC_GPIO 0x5300 -#define STM32F746_PF3_FUNC_FMC_A3 0x530d -#define STM32F746_PF3_FUNC_EVENTOUT 0x5310 -#define STM32F746_PF3_FUNC_ANALOG 0x5311 - -#define STM32F746_PF4_FUNC_GPIO 0x5400 -#define STM32F746_PF4_FUNC_FMC_A4 0x540d -#define STM32F746_PF4_FUNC_EVENTOUT 0x5410 -#define STM32F746_PF4_FUNC_ANALOG 0x5411 - -#define STM32F746_PF5_FUNC_GPIO 0x5500 -#define STM32F746_PF5_FUNC_FMC_A5 0x550d -#define STM32F746_PF5_FUNC_EVENTOUT 0x5510 -#define STM32F746_PF5_FUNC_ANALOG 0x5511 - -#define STM32F746_PF6_FUNC_GPIO 0x5600 -#define STM32F746_PF6_FUNC_TIM10_CH1 0x5604 -#define STM32F746_PF6_FUNC_SPI5_NSS 0x5606 -#define STM32F746_PF6_FUNC_SAI1_SD_B 0x5607 -#define STM32F746_PF6_FUNC_UART7_RX 0x5609 -#define STM32F746_PF6_FUNC_QUADSPI_BK1_IO3 0x560a -#define STM32F746_PF6_FUNC_EVENTOUT 0x5610 -#define STM32F746_PF6_FUNC_ANALOG 0x5611 - -#define STM32F746_PF7_FUNC_GPIO 0x5700 -#define STM32F746_PF7_FUNC_TIM11_CH1 0x5704 -#define STM32F746_PF7_FUNC_SPI5_SCK 0x5706 -#define STM32F746_PF7_FUNC_SAI1_MCLK_B 0x5707 -#define STM32F746_PF7_FUNC_UART7_TX 0x5709 -#define STM32F746_PF7_FUNC_QUADSPI_BK1_IO2 0x570a -#define STM32F746_PF7_FUNC_EVENTOUT 0x5710 -#define STM32F746_PF7_FUNC_ANALOG 0x5711 - -#define STM32F746_PF8_FUNC_GPIO 0x5800 -#define STM32F746_PF8_FUNC_SPI5_MISO 0x5806 -#define STM32F746_PF8_FUNC_SAI1_SCK_B 0x5807 -#define STM32F746_PF8_FUNC_UART7_RTS 0x5809 -#define STM32F746_PF8_FUNC_TIM13_CH1 0x580a -#define STM32F746_PF8_FUNC_QUADSPI_BK1_IO0 0x580b -#define STM32F746_PF8_FUNC_EVENTOUT 0x5810 -#define STM32F746_PF8_FUNC_ANALOG 0x5811 - -#define STM32F746_PF9_FUNC_GPIO 0x5900 -#define STM32F746_PF9_FUNC_SPI5_MOSI 0x5906 -#define STM32F746_PF9_FUNC_SAI1_FS_B 0x5907 -#define STM32F746_PF9_FUNC_UART7_CTS 0x5909 -#define STM32F746_PF9_FUNC_TIM14_CH1 0x590a -#define STM32F746_PF9_FUNC_QUADSPI_BK1_IO1 0x590b -#define STM32F746_PF9_FUNC_EVENTOUT 0x5910 -#define STM32F746_PF9_FUNC_ANALOG 0x5911 - -#define STM32F746_PF10_FUNC_GPIO 0x5a00 -#define STM32F746_PF10_FUNC_DCMI_D11 0x5a0e -#define STM32F746_PF10_FUNC_LCD_DE 0x5a0f -#define STM32F746_PF10_FUNC_EVENTOUT 0x5a10 -#define STM32F746_PF10_FUNC_ANALOG 0x5a11 - -#define STM32F746_PF11_FUNC_GPIO 0x5b00 -#define STM32F746_PF11_FUNC_SPI5_MOSI 0x5b06 -#define STM32F746_PF11_FUNC_SAI2_SD_B 0x5b0b -#define STM32F746_PF11_FUNC_FMC_SDNRAS 0x5b0d -#define STM32F746_PF11_FUNC_DCMI_D12 0x5b0e -#define STM32F746_PF11_FUNC_EVENTOUT 0x5b10 -#define STM32F746_PF11_FUNC_ANALOG 0x5b11 - -#define STM32F746_PF12_FUNC_GPIO 0x5c00 -#define STM32F746_PF12_FUNC_FMC_A6 0x5c0d -#define STM32F746_PF12_FUNC_EVENTOUT 0x5c10 -#define STM32F746_PF12_FUNC_ANALOG 0x5c11 - -#define STM32F746_PF13_FUNC_GPIO 0x5d00 -#define STM32F746_PF13_FUNC_I2C4_SMBA 0x5d05 -#define STM32F746_PF13_FUNC_FMC_A7 0x5d0d -#define STM32F746_PF13_FUNC_EVENTOUT 0x5d10 -#define STM32F746_PF13_FUNC_ANALOG 0x5d11 - -#define STM32F746_PF14_FUNC_GPIO 0x5e00 -#define STM32F746_PF14_FUNC_I2C4_SCL 0x5e05 -#define STM32F746_PF14_FUNC_FMC_A8 0x5e0d -#define STM32F746_PF14_FUNC_EVENTOUT 0x5e10 -#define STM32F746_PF14_FUNC_ANALOG 0x5e11 - -#define STM32F746_PF15_FUNC_GPIO 0x5f00 -#define STM32F746_PF15_FUNC_I2C4_SDA 0x5f05 -#define STM32F746_PF15_FUNC_FMC_A9 0x5f0d -#define STM32F746_PF15_FUNC_EVENTOUT 0x5f10 -#define STM32F746_PF15_FUNC_ANALOG 0x5f11 - - -#define STM32F746_PG0_FUNC_GPIO 0x6000 -#define STM32F746_PG0_FUNC_FMC_A10 0x600d -#define STM32F746_PG0_FUNC_EVENTOUT 0x6010 -#define STM32F746_PG0_FUNC_ANALOG 0x6011 - -#define STM32F746_PG1_FUNC_GPIO 0x6100 -#define STM32F746_PG1_FUNC_FMC_A11 0x610d -#define STM32F746_PG1_FUNC_EVENTOUT 0x6110 -#define STM32F746_PG1_FUNC_ANALOG 0x6111 - -#define STM32F746_PG2_FUNC_GPIO 0x6200 -#define STM32F746_PG2_FUNC_FMC_A12 0x620d -#define STM32F746_PG2_FUNC_EVENTOUT 0x6210 -#define STM32F746_PG2_FUNC_ANALOG 0x6211 - -#define STM32F746_PG3_FUNC_GPIO 0x6300 -#define STM32F746_PG3_FUNC_FMC_A13 0x630d -#define STM32F746_PG3_FUNC_EVENTOUT 0x6310 -#define STM32F746_PG3_FUNC_ANALOG 0x6311 - -#define STM32F746_PG4_FUNC_GPIO 0x6400 -#define STM32F746_PG4_FUNC_FMC_A14_FMC_BA0 0x640d -#define STM32F746_PG4_FUNC_EVENTOUT 0x6410 -#define STM32F746_PG4_FUNC_ANALOG 0x6411 - -#define STM32F746_PG5_FUNC_GPIO 0x6500 -#define STM32F746_PG5_FUNC_FMC_A15_FMC_BA1 0x650d -#define STM32F746_PG5_FUNC_EVENTOUT 0x6510 -#define STM32F746_PG5_FUNC_ANALOG 0x6511 - -#define STM32F746_PG6_FUNC_GPIO 0x6600 -#define STM32F746_PG6_FUNC_DCMI_D12 0x660e -#define STM32F746_PG6_FUNC_LCD_R7 0x660f -#define STM32F746_PG6_FUNC_EVENTOUT 0x6610 -#define STM32F746_PG6_FUNC_ANALOG 0x6611 - -#define STM32F746_PG7_FUNC_GPIO 0x6700 -#define STM32F746_PG7_FUNC_USART6_CK 0x6709 -#define STM32F746_PG7_FUNC_FMC_INT 0x670d -#define STM32F746_PG7_FUNC_DCMI_D13 0x670e -#define STM32F746_PG7_FUNC_LCD_CLK 0x670f -#define STM32F746_PG7_FUNC_EVENTOUT 0x6710 -#define STM32F746_PG7_FUNC_ANALOG 0x6711 - -#define STM32F746_PG8_FUNC_GPIO 0x6800 -#define STM32F746_PG8_FUNC_SPI6_NSS 0x6806 -#define STM32F746_PG8_FUNC_SPDIFRX_IN2 0x6808 -#define STM32F746_PG8_FUNC_USART6_RTS 0x6809 -#define STM32F746_PG8_FUNC_ETH_PPS_OUT 0x680c -#define STM32F746_PG8_FUNC_FMC_SDCLK 0x680d -#define STM32F746_PG8_FUNC_EVENTOUT 0x6810 -#define STM32F746_PG8_FUNC_ANALOG 0x6811 - -#define STM32F746_PG9_FUNC_GPIO 0x6900 -#define STM32F746_PG9_FUNC_SPDIFRX_IN3 0x6908 -#define STM32F746_PG9_FUNC_USART6_RX 0x6909 -#define STM32F746_PG9_FUNC_QUADSPI_BK2_IO2 0x690a -#define STM32F746_PG9_FUNC_SAI2_FS_B 0x690b -#define STM32F746_PG9_FUNC_FMC_NE2_FMC_NCE 0x690d -#define STM32F746_PG9_FUNC_DCMI_VSYNC 0x690e -#define STM32F746_PG9_FUNC_EVENTOUT 0x6910 -#define STM32F746_PG9_FUNC_ANALOG 0x6911 - -#define STM32F746_PG10_FUNC_GPIO 0x6a00 -#define STM32F746_PG10_FUNC_LCD_G3 0x6a0a -#define STM32F746_PG10_FUNC_SAI2_SD_B 0x6a0b -#define STM32F746_PG10_FUNC_FMC_NE3 0x6a0d -#define STM32F746_PG10_FUNC_DCMI_D2 0x6a0e -#define STM32F746_PG10_FUNC_LCD_B2 0x6a0f -#define STM32F746_PG10_FUNC_EVENTOUT 0x6a10 -#define STM32F746_PG10_FUNC_ANALOG 0x6a11 - -#define STM32F746_PG11_FUNC_GPIO 0x6b00 -#define STM32F746_PG11_FUNC_SPDIFRX_IN0 0x6b08 -#define STM32F746_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN 0x6b0c -#define STM32F746_PG11_FUNC_DCMI_D3 0x6b0e -#define STM32F746_PG11_FUNC_LCD_B3 0x6b0f -#define STM32F746_PG11_FUNC_EVENTOUT 0x6b10 -#define STM32F746_PG11_FUNC_ANALOG 0x6b11 - -#define STM32F746_PG12_FUNC_GPIO 0x6c00 -#define STM32F746_PG12_FUNC_LPTIM1_IN1 0x6c04 -#define STM32F746_PG12_FUNC_SPI6_MISO 0x6c06 -#define STM32F746_PG12_FUNC_SPDIFRX_IN1 0x6c08 -#define STM32F746_PG12_FUNC_USART6_RTS 0x6c09 -#define STM32F746_PG12_FUNC_LCD_B4 0x6c0a -#define STM32F746_PG12_FUNC_FMC_NE4 0x6c0d -#define STM32F746_PG12_FUNC_LCD_B1 0x6c0f -#define STM32F746_PG12_FUNC_EVENTOUT 0x6c10 -#define STM32F746_PG12_FUNC_ANALOG 0x6c11 - -#define STM32F746_PG13_FUNC_GPIO 0x6d00 -#define STM32F746_PG13_FUNC_TRACED0 0x6d01 -#define STM32F746_PG13_FUNC_LPTIM1_OUT 0x6d04 -#define STM32F746_PG13_FUNC_SPI6_SCK 0x6d06 -#define STM32F746_PG13_FUNC_USART6_CTS 0x6d09 -#define STM32F746_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0 0x6d0c -#define STM32F746_PG13_FUNC_FMC_A24 0x6d0d -#define STM32F746_PG13_FUNC_LCD_R0 0x6d0f -#define STM32F746_PG13_FUNC_EVENTOUT 0x6d10 -#define STM32F746_PG13_FUNC_ANALOG 0x6d11 - -#define STM32F746_PG14_FUNC_GPIO 0x6e00 -#define STM32F746_PG14_FUNC_TRACED1 0x6e01 -#define STM32F746_PG14_FUNC_LPTIM1_ETR 0x6e04 -#define STM32F746_PG14_FUNC_SPI6_MOSI 0x6e06 -#define STM32F746_PG14_FUNC_USART6_TX 0x6e09 -#define STM32F746_PG14_FUNC_QUADSPI_BK2_IO3 0x6e0a -#define STM32F746_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1 0x6e0c -#define STM32F746_PG14_FUNC_FMC_A25 0x6e0d -#define STM32F746_PG14_FUNC_LCD_B0 0x6e0f -#define STM32F746_PG14_FUNC_EVENTOUT 0x6e10 -#define STM32F746_PG14_FUNC_ANALOG 0x6e11 - -#define STM32F746_PG15_FUNC_GPIO 0x6f00 -#define STM32F746_PG15_FUNC_USART6_CTS 0x6f09 -#define STM32F746_PG15_FUNC_FMC_SDNCAS 0x6f0d -#define STM32F746_PG15_FUNC_DCMI_D13 0x6f0e -#define STM32F746_PG15_FUNC_EVENTOUT 0x6f10 -#define STM32F746_PG15_FUNC_ANALOG 0x6f11 - - -#define STM32F746_PH0_FUNC_GPIO 0x7000 -#define STM32F746_PH0_FUNC_EVENTOUT 0x7010 -#define STM32F746_PH0_FUNC_ANALOG 0x7011 - -#define STM32F746_PH1_FUNC_GPIO 0x7100 -#define STM32F746_PH1_FUNC_EVENTOUT 0x7110 -#define STM32F746_PH1_FUNC_ANALOG 0x7111 - -#define STM32F746_PH2_FUNC_GPIO 0x7200 -#define STM32F746_PH2_FUNC_LPTIM1_IN2 0x7204 -#define STM32F746_PH2_FUNC_QUADSPI_BK2_IO0 0x720a -#define STM32F746_PH2_FUNC_SAI2_SCK_B 0x720b -#define STM32F746_PH2_FUNC_ETH_MII_CRS 0x720c -#define STM32F746_PH2_FUNC_FMC_SDCKE0 0x720d -#define STM32F746_PH2_FUNC_LCD_R0 0x720f -#define STM32F746_PH2_FUNC_EVENTOUT 0x7210 -#define STM32F746_PH2_FUNC_ANALOG 0x7211 - -#define STM32F746_PH3_FUNC_GPIO 0x7300 -#define STM32F746_PH3_FUNC_QUADSPI_BK2_IO1 0x730a -#define STM32F746_PH3_FUNC_SAI2_MCLK_B 0x730b -#define STM32F746_PH3_FUNC_ETH_MII_COL 0x730c -#define STM32F746_PH3_FUNC_FMC_SDNE0 0x730d -#define STM32F746_PH3_FUNC_LCD_R1 0x730f -#define STM32F746_PH3_FUNC_EVENTOUT 0x7310 -#define STM32F746_PH3_FUNC_ANALOG 0x7311 - -#define STM32F746_PH4_FUNC_GPIO 0x7400 -#define STM32F746_PH4_FUNC_I2C2_SCL 0x7405 -#define STM32F746_PH4_FUNC_OTG_HS_ULPI_NXT 0x740b -#define STM32F746_PH4_FUNC_EVENTOUT 0x7410 -#define STM32F746_PH4_FUNC_ANALOG 0x7411 - -#define STM32F746_PH5_FUNC_GPIO 0x7500 -#define STM32F746_PH5_FUNC_I2C2_SDA 0x7505 -#define STM32F746_PH5_FUNC_SPI5_NSS 0x7506 -#define STM32F746_PH5_FUNC_FMC_SDNWE 0x750d -#define STM32F746_PH5_FUNC_EVENTOUT 0x7510 -#define STM32F746_PH5_FUNC_ANALOG 0x7511 - -#define STM32F746_PH6_FUNC_GPIO 0x7600 -#define STM32F746_PH6_FUNC_I2C2_SMBA 0x7605 -#define STM32F746_PH6_FUNC_SPI5_SCK 0x7606 -#define STM32F746_PH6_FUNC_TIM12_CH1 0x760a -#define STM32F746_PH6_FUNC_ETH_MII_RXD2 0x760c -#define STM32F746_PH6_FUNC_FMC_SDNE1 0x760d -#define STM32F746_PH6_FUNC_DCMI_D8 0x760e -#define STM32F746_PH6_FUNC_EVENTOUT 0x7610 -#define STM32F746_PH6_FUNC_ANALOG 0x7611 - -#define STM32F746_PH7_FUNC_GPIO 0x7700 -#define STM32F746_PH7_FUNC_I2C3_SCL 0x7705 -#define STM32F746_PH7_FUNC_SPI5_MISO 0x7706 -#define STM32F746_PH7_FUNC_ETH_MII_RXD3 0x770c -#define STM32F746_PH7_FUNC_FMC_SDCKE1 0x770d -#define STM32F746_PH7_FUNC_DCMI_D9 0x770e -#define STM32F746_PH7_FUNC_EVENTOUT 0x7710 -#define STM32F746_PH7_FUNC_ANALOG 0x7711 - -#define STM32F746_PH8_FUNC_GPIO 0x7800 -#define STM32F746_PH8_FUNC_I2C3_SDA 0x7805 -#define STM32F746_PH8_FUNC_FMC_D16 0x780d -#define STM32F746_PH8_FUNC_DCMI_HSYNC 0x780e -#define STM32F746_PH8_FUNC_LCD_R2 0x780f -#define STM32F746_PH8_FUNC_EVENTOUT 0x7810 -#define STM32F746_PH8_FUNC_ANALOG 0x7811 - -#define STM32F746_PH9_FUNC_GPIO 0x7900 -#define STM32F746_PH9_FUNC_I2C3_SMBA 0x7905 -#define STM32F746_PH9_FUNC_TIM12_CH2 0x790a -#define STM32F746_PH9_FUNC_FMC_D17 0x790d -#define STM32F746_PH9_FUNC_DCMI_D0 0x790e -#define STM32F746_PH9_FUNC_LCD_R3 0x790f -#define STM32F746_PH9_FUNC_EVENTOUT 0x7910 -#define STM32F746_PH9_FUNC_ANALOG 0x7911 - -#define STM32F746_PH10_FUNC_GPIO 0x7a00 -#define STM32F746_PH10_FUNC_TIM5_CH1 0x7a03 -#define STM32F746_PH10_FUNC_I2C4_SMBA 0x7a05 -#define STM32F746_PH10_FUNC_FMC_D18 0x7a0d -#define STM32F746_PH10_FUNC_DCMI_D1 0x7a0e -#define STM32F746_PH10_FUNC_LCD_R4 0x7a0f -#define STM32F746_PH10_FUNC_EVENTOUT 0x7a10 -#define STM32F746_PH10_FUNC_ANALOG 0x7a11 - -#define STM32F746_PH11_FUNC_GPIO 0x7b00 -#define STM32F746_PH11_FUNC_TIM5_CH2 0x7b03 -#define STM32F746_PH11_FUNC_I2C4_SCL 0x7b05 -#define STM32F746_PH11_FUNC_FMC_D19 0x7b0d -#define STM32F746_PH11_FUNC_DCMI_D2 0x7b0e -#define STM32F746_PH11_FUNC_LCD_R5 0x7b0f -#define STM32F746_PH11_FUNC_EVENTOUT 0x7b10 -#define STM32F746_PH11_FUNC_ANALOG 0x7b11 - -#define STM32F746_PH12_FUNC_GPIO 0x7c00 -#define STM32F746_PH12_FUNC_TIM5_CH3 0x7c03 -#define STM32F746_PH12_FUNC_I2C4_SDA 0x7c05 -#define STM32F746_PH12_FUNC_FMC_D20 0x7c0d -#define STM32F746_PH12_FUNC_DCMI_D3 0x7c0e -#define STM32F746_PH12_FUNC_LCD_R6 0x7c0f -#define STM32F746_PH12_FUNC_EVENTOUT 0x7c10 -#define STM32F746_PH12_FUNC_ANALOG 0x7c11 - -#define STM32F746_PH13_FUNC_GPIO 0x7d00 -#define STM32F746_PH13_FUNC_TIM8_CH1N 0x7d04 -#define STM32F746_PH13_FUNC_CAN1_TX 0x7d0a -#define STM32F746_PH13_FUNC_FMC_D21 0x7d0d -#define STM32F746_PH13_FUNC_LCD_G2 0x7d0f -#define STM32F746_PH13_FUNC_EVENTOUT 0x7d10 -#define STM32F746_PH13_FUNC_ANALOG 0x7d11 - -#define STM32F746_PH14_FUNC_GPIO 0x7e00 -#define STM32F746_PH14_FUNC_TIM8_CH2N 0x7e04 -#define STM32F746_PH14_FUNC_FMC_D22 0x7e0d -#define STM32F746_PH14_FUNC_DCMI_D4 0x7e0e -#define STM32F746_PH14_FUNC_LCD_G3 0x7e0f -#define STM32F746_PH14_FUNC_EVENTOUT 0x7e10 -#define STM32F746_PH14_FUNC_ANALOG 0x7e11 - -#define STM32F746_PH15_FUNC_GPIO 0x7f00 -#define STM32F746_PH15_FUNC_TIM8_CH3N 0x7f04 -#define STM32F746_PH15_FUNC_FMC_D23 0x7f0d -#define STM32F746_PH15_FUNC_DCMI_D11 0x7f0e -#define STM32F746_PH15_FUNC_LCD_G4 0x7f0f -#define STM32F746_PH15_FUNC_EVENTOUT 0x7f10 -#define STM32F746_PH15_FUNC_ANALOG 0x7f11 - - -#define STM32F746_PI0_FUNC_GPIO 0x8000 -#define STM32F746_PI0_FUNC_TIM5_CH4 0x8003 -#define STM32F746_PI0_FUNC_SPI2_NSS_I2S2_WS 0x8006 -#define STM32F746_PI0_FUNC_FMC_D24 0x800d -#define STM32F746_PI0_FUNC_DCMI_D13 0x800e -#define STM32F746_PI0_FUNC_LCD_G5 0x800f -#define STM32F746_PI0_FUNC_EVENTOUT 0x8010 -#define STM32F746_PI0_FUNC_ANALOG 0x8011 - -#define STM32F746_PI1_FUNC_GPIO 0x8100 -#define STM32F746_PI1_FUNC_TIM8_BKIN2 0x8104 -#define STM32F746_PI1_FUNC_SPI2_SCK_I2S2_CK 0x8106 -#define STM32F746_PI1_FUNC_FMC_D25 0x810d -#define STM32F746_PI1_FUNC_DCMI_D8 0x810e -#define STM32F746_PI1_FUNC_LCD_G6 0x810f -#define STM32F746_PI1_FUNC_EVENTOUT 0x8110 -#define STM32F746_PI1_FUNC_ANALOG 0x8111 - -#define STM32F746_PI2_FUNC_GPIO 0x8200 -#define STM32F746_PI2_FUNC_TIM8_CH4 0x8204 -#define STM32F746_PI2_FUNC_SPI2_MISO 0x8206 -#define STM32F746_PI2_FUNC_FMC_D26 0x820d -#define STM32F746_PI2_FUNC_DCMI_D9 0x820e -#define STM32F746_PI2_FUNC_LCD_G7 0x820f -#define STM32F746_PI2_FUNC_EVENTOUT 0x8210 -#define STM32F746_PI2_FUNC_ANALOG 0x8211 - -#define STM32F746_PI3_FUNC_GPIO 0x8300 -#define STM32F746_PI3_FUNC_TIM8_ETR 0x8304 -#define STM32F746_PI3_FUNC_SPI2_MOSI_I2S2_SD 0x8306 -#define STM32F746_PI3_FUNC_FMC_D27 0x830d -#define STM32F746_PI3_FUNC_DCMI_D10 0x830e -#define STM32F746_PI3_FUNC_EVENTOUT 0x8310 -#define STM32F746_PI3_FUNC_ANALOG 0x8311 - -#define STM32F746_PI4_FUNC_GPIO 0x8400 -#define STM32F746_PI4_FUNC_TIM8_BKIN 0x8404 -#define STM32F746_PI4_FUNC_SAI2_MCLK_A 0x840b -#define STM32F746_PI4_FUNC_FMC_NBL2 0x840d -#define STM32F746_PI4_FUNC_DCMI_D5 0x840e -#define STM32F746_PI4_FUNC_LCD_B4 0x840f -#define STM32F746_PI4_FUNC_EVENTOUT 0x8410 -#define STM32F746_PI4_FUNC_ANALOG 0x8411 - -#define STM32F746_PI5_FUNC_GPIO 0x8500 -#define STM32F746_PI5_FUNC_TIM8_CH1 0x8504 -#define STM32F746_PI5_FUNC_SAI2_SCK_A 0x850b -#define STM32F746_PI5_FUNC_FMC_NBL3 0x850d -#define STM32F746_PI5_FUNC_DCMI_VSYNC 0x850e -#define STM32F746_PI5_FUNC_LCD_B5 0x850f -#define STM32F746_PI5_FUNC_EVENTOUT 0x8510 -#define STM32F746_PI5_FUNC_ANALOG 0x8511 - -#define STM32F746_PI6_FUNC_GPIO 0x8600 -#define STM32F746_PI6_FUNC_TIM8_CH2 0x8604 -#define STM32F746_PI6_FUNC_SAI2_SD_A 0x860b -#define STM32F746_PI6_FUNC_FMC_D28 0x860d -#define STM32F746_PI6_FUNC_DCMI_D6 0x860e -#define STM32F746_PI6_FUNC_LCD_B6 0x860f -#define STM32F746_PI6_FUNC_EVENTOUT 0x8610 -#define STM32F746_PI6_FUNC_ANALOG 0x8611 - -#define STM32F746_PI7_FUNC_GPIO 0x8700 -#define STM32F746_PI7_FUNC_TIM8_CH3 0x8704 -#define STM32F746_PI7_FUNC_SAI2_FS_A 0x870b -#define STM32F746_PI7_FUNC_FMC_D29 0x870d -#define STM32F746_PI7_FUNC_DCMI_D7 0x870e -#define STM32F746_PI7_FUNC_LCD_B7 0x870f -#define STM32F746_PI7_FUNC_EVENTOUT 0x8710 -#define STM32F746_PI7_FUNC_ANALOG 0x8711 - -#define STM32F746_PI8_FUNC_GPIO 0x8800 -#define STM32F746_PI8_FUNC_EVENTOUT 0x8810 -#define STM32F746_PI8_FUNC_ANALOG 0x8811 - -#define STM32F746_PI9_FUNC_GPIO 0x8900 -#define STM32F746_PI9_FUNC_CAN1_RX 0x890a -#define STM32F746_PI9_FUNC_FMC_D30 0x890d -#define STM32F746_PI9_FUNC_LCD_VSYNC 0x890f -#define STM32F746_PI9_FUNC_EVENTOUT 0x8910 -#define STM32F746_PI9_FUNC_ANALOG 0x8911 - -#define STM32F746_PI10_FUNC_GPIO 0x8a00 -#define STM32F746_PI10_FUNC_ETH_MII_RX_ER 0x8a0c -#define STM32F746_PI10_FUNC_FMC_D31 0x8a0d -#define STM32F746_PI10_FUNC_LCD_HSYNC 0x8a0f -#define STM32F746_PI10_FUNC_EVENTOUT 0x8a10 -#define STM32F746_PI10_FUNC_ANALOG 0x8a11 - -#define STM32F746_PI11_FUNC_GPIO 0x8b00 -#define STM32F746_PI11_FUNC_OTG_HS_ULPI_DIR 0x8b0b -#define STM32F746_PI11_FUNC_EVENTOUT 0x8b10 -#define STM32F746_PI11_FUNC_ANALOG 0x8b11 - -#define STM32F746_PI12_FUNC_GPIO 0x8c00 -#define STM32F746_PI12_FUNC_LCD_HSYNC 0x8c0f -#define STM32F746_PI12_FUNC_EVENTOUT 0x8c10 -#define STM32F746_PI12_FUNC_ANALOG 0x8c11 - -#define STM32F746_PI13_FUNC_GPIO 0x8d00 -#define STM32F746_PI13_FUNC_LCD_VSYNC 0x8d0f -#define STM32F746_PI13_FUNC_EVENTOUT 0x8d10 -#define STM32F746_PI13_FUNC_ANALOG 0x8d11 - -#define STM32F746_PI14_FUNC_GPIO 0x8e00 -#define STM32F746_PI14_FUNC_LCD_CLK 0x8e0f -#define STM32F746_PI14_FUNC_EVENTOUT 0x8e10 -#define STM32F746_PI14_FUNC_ANALOG 0x8e11 - -#define STM32F746_PI15_FUNC_GPIO 0x8f00 -#define STM32F746_PI15_FUNC_LCD_R0 0x8f0f -#define STM32F746_PI15_FUNC_EVENTOUT 0x8f10 -#define STM32F746_PI15_FUNC_ANALOG 0x8f11 - - -#define STM32F746_PJ0_FUNC_GPIO 0x9000 -#define STM32F746_PJ0_FUNC_LCD_R1 0x900f -#define STM32F746_PJ0_FUNC_EVENTOUT 0x9010 -#define STM32F746_PJ0_FUNC_ANALOG 0x9011 - -#define STM32F746_PJ1_FUNC_GPIO 0x9100 -#define STM32F746_PJ1_FUNC_LCD_R2 0x910f -#define STM32F746_PJ1_FUNC_EVENTOUT 0x9110 -#define STM32F746_PJ1_FUNC_ANALOG 0x9111 - -#define STM32F746_PJ2_FUNC_GPIO 0x9200 -#define STM32F746_PJ2_FUNC_LCD_R3 0x920f -#define STM32F746_PJ2_FUNC_EVENTOUT 0x9210 -#define STM32F746_PJ2_FUNC_ANALOG 0x9211 - -#define STM32F746_PJ3_FUNC_GPIO 0x9300 -#define STM32F746_PJ3_FUNC_LCD_R4 0x930f -#define STM32F746_PJ3_FUNC_EVENTOUT 0x9310 -#define STM32F746_PJ3_FUNC_ANALOG 0x9311 - -#define STM32F746_PJ4_FUNC_GPIO 0x9400 -#define STM32F746_PJ4_FUNC_LCD_R5 0x940f -#define STM32F746_PJ4_FUNC_EVENTOUT 0x9410 -#define STM32F746_PJ4_FUNC_ANALOG 0x9411 - -#define STM32F746_PJ5_FUNC_GPIO 0x9500 -#define STM32F746_PJ5_FUNC_LCD_R6 0x950f -#define STM32F746_PJ5_FUNC_EVENTOUT 0x9510 -#define STM32F746_PJ5_FUNC_ANALOG 0x9511 - -#define STM32F746_PJ6_FUNC_GPIO 0x9600 -#define STM32F746_PJ6_FUNC_LCD_R7 0x960f -#define STM32F746_PJ6_FUNC_EVENTOUT 0x9610 -#define STM32F746_PJ6_FUNC_ANALOG 0x9611 - -#define STM32F746_PJ7_FUNC_GPIO 0x9700 -#define STM32F746_PJ7_FUNC_LCD_G0 0x970f -#define STM32F746_PJ7_FUNC_EVENTOUT 0x9710 -#define STM32F746_PJ7_FUNC_ANALOG 0x9711 - -#define STM32F746_PJ8_FUNC_GPIO 0x9800 -#define STM32F746_PJ8_FUNC_LCD_G1 0x980f -#define STM32F746_PJ8_FUNC_EVENTOUT 0x9810 -#define STM32F746_PJ8_FUNC_ANALOG 0x9811 - -#define STM32F746_PJ9_FUNC_GPIO 0x9900 -#define STM32F746_PJ9_FUNC_LCD_G2 0x990f -#define STM32F746_PJ9_FUNC_EVENTOUT 0x9910 -#define STM32F746_PJ9_FUNC_ANALOG 0x9911 - -#define STM32F746_PJ10_FUNC_GPIO 0x9a00 -#define STM32F746_PJ10_FUNC_LCD_G3 0x9a0f -#define STM32F746_PJ10_FUNC_EVENTOUT 0x9a10 -#define STM32F746_PJ10_FUNC_ANALOG 0x9a11 - -#define STM32F746_PJ11_FUNC_GPIO 0x9b00 -#define STM32F746_PJ11_FUNC_LCD_G4 0x9b0f -#define STM32F746_PJ11_FUNC_EVENTOUT 0x9b10 -#define STM32F746_PJ11_FUNC_ANALOG 0x9b11 - -#define STM32F746_PJ12_FUNC_GPIO 0x9c00 -#define STM32F746_PJ12_FUNC_LCD_B0 0x9c0f -#define STM32F746_PJ12_FUNC_EVENTOUT 0x9c10 -#define STM32F746_PJ12_FUNC_ANALOG 0x9c11 - -#define STM32F746_PJ13_FUNC_GPIO 0x9d00 -#define STM32F746_PJ13_FUNC_LCD_B1 0x9d0f -#define STM32F746_PJ13_FUNC_EVENTOUT 0x9d10 -#define STM32F746_PJ13_FUNC_ANALOG 0x9d11 - -#define STM32F746_PJ14_FUNC_GPIO 0x9e00 -#define STM32F746_PJ14_FUNC_LCD_B2 0x9e0f -#define STM32F746_PJ14_FUNC_EVENTOUT 0x9e10 -#define STM32F746_PJ14_FUNC_ANALOG 0x9e11 - -#define STM32F746_PJ15_FUNC_GPIO 0x9f00 -#define STM32F746_PJ15_FUNC_LCD_B3 0x9f0f -#define STM32F746_PJ15_FUNC_EVENTOUT 0x9f10 -#define STM32F746_PJ15_FUNC_ANALOG 0x9f11 - - -#define STM32F746_PK0_FUNC_GPIO 0xa000 -#define STM32F746_PK0_FUNC_LCD_G5 0xa00f -#define STM32F746_PK0_FUNC_EVENTOUT 0xa010 -#define STM32F746_PK0_FUNC_ANALOG 0xa011 - -#define STM32F746_PK1_FUNC_GPIO 0xa100 -#define STM32F746_PK1_FUNC_LCD_G6 0xa10f -#define STM32F746_PK1_FUNC_EVENTOUT 0xa110 -#define STM32F746_PK1_FUNC_ANALOG 0xa111 - -#define STM32F746_PK2_FUNC_GPIO 0xa200 -#define STM32F746_PK2_FUNC_LCD_G7 0xa20f -#define STM32F746_PK2_FUNC_EVENTOUT 0xa210 -#define STM32F746_PK2_FUNC_ANALOG 0xa211 - -#define STM32F746_PK3_FUNC_GPIO 0xa300 -#define STM32F746_PK3_FUNC_LCD_B4 0xa30f -#define STM32F746_PK3_FUNC_EVENTOUT 0xa310 -#define STM32F746_PK3_FUNC_ANALOG 0xa311 - -#define STM32F746_PK4_FUNC_GPIO 0xa400 -#define STM32F746_PK4_FUNC_LCD_B5 0xa40f -#define STM32F746_PK4_FUNC_EVENTOUT 0xa410 -#define STM32F746_PK4_FUNC_ANALOG 0xa411 - -#define STM32F746_PK5_FUNC_GPIO 0xa500 -#define STM32F746_PK5_FUNC_LCD_B6 0xa50f -#define STM32F746_PK5_FUNC_EVENTOUT 0xa510 -#define STM32F746_PK5_FUNC_ANALOG 0xa511 - -#define STM32F746_PK6_FUNC_GPIO 0xa600 -#define STM32F746_PK6_FUNC_LCD_B7 0xa60f -#define STM32F746_PK6_FUNC_EVENTOUT 0xa610 -#define STM32F746_PK6_FUNC_ANALOG 0xa611 - -#define STM32F746_PK7_FUNC_GPIO 0xa700 -#define STM32F746_PK7_FUNC_LCD_DE 0xa70f -#define STM32F746_PK7_FUNC_EVENTOUT 0xa710 -#define STM32F746_PK7_FUNC_ANALOG 0xa711 - -#endif /* _DT_BINDINGS_STM32F746_PINFUNC_H */ diff --git a/sys/gnu/dts/include/dt-bindings/pinctrl/stm32h7-pinfunc.h b/sys/gnu/dts/include/dt-bindings/pinctrl/stm32h7-pinfunc.h deleted file mode 100644 index 06d99a8ddbc..00000000000 --- a/sys/gnu/dts/include/dt-bindings/pinctrl/stm32h7-pinfunc.h +++ /dev/null @@ -1,1613 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _DT_BINDINGS_STM32H7_PINFUNC_H -#define _DT_BINDINGS_STM32H7_PINFUNC_H - -#define STM32H7_PA0_FUNC_GPIO 0x0 -#define STM32H7_PA0_FUNC_TIM2_CH1_TIM2_ETR 0x2 -#define STM32H7_PA0_FUNC_TIM5_CH1 0x3 -#define STM32H7_PA0_FUNC_TIM8_ETR 0x4 -#define STM32H7_PA0_FUNC_TIM15_BKIN 0x5 -#define STM32H7_PA0_FUNC_USART2_CTS_NSS 0x8 -#define STM32H7_PA0_FUNC_UART4_TX 0x9 -#define STM32H7_PA0_FUNC_SDMMC2_CMD 0xa -#define STM32H7_PA0_FUNC_SAI2_SD_B 0xb -#define STM32H7_PA0_FUNC_ETH_MII_CRS 0xc -#define STM32H7_PA0_FUNC_EVENTOUT 0x10 -#define STM32H7_PA0_FUNC_ANALOG 0x11 - -#define STM32H7_PA1_FUNC_GPIO 0x100 -#define STM32H7_PA1_FUNC_TIM2_CH2 0x102 -#define STM32H7_PA1_FUNC_TIM5_CH2 0x103 -#define STM32H7_PA1_FUNC_LPTIM3_OUT 0x104 -#define STM32H7_PA1_FUNC_TIM15_CH1N 0x105 -#define STM32H7_PA1_FUNC_USART2_RTS 0x108 -#define STM32H7_PA1_FUNC_UART4_RX 0x109 -#define STM32H7_PA1_FUNC_QUADSPI_BK1_IO3 0x10a -#define STM32H7_PA1_FUNC_SAI2_MCK_B 0x10b -#define STM32H7_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK 0x10c -#define STM32H7_PA1_FUNC_LCD_R2 0x10f -#define STM32H7_PA1_FUNC_EVENTOUT 0x110 -#define STM32H7_PA1_FUNC_ANALOG 0x111 - -#define STM32H7_PA2_FUNC_GPIO 0x200 -#define STM32H7_PA2_FUNC_TIM2_CH3 0x202 -#define STM32H7_PA2_FUNC_TIM5_CH3 0x203 -#define STM32H7_PA2_FUNC_LPTIM4_OUT 0x204 -#define STM32H7_PA2_FUNC_TIM15_CH1 0x205 -#define STM32H7_PA2_FUNC_USART2_TX 0x208 -#define STM32H7_PA2_FUNC_SAI2_SCK_B 0x209 -#define STM32H7_PA2_FUNC_ETH_MDIO 0x20c -#define STM32H7_PA2_FUNC_MDIOS_MDIO 0x20d -#define STM32H7_PA2_FUNC_LCD_R1 0x20f -#define STM32H7_PA2_FUNC_EVENTOUT 0x210 -#define STM32H7_PA2_FUNC_ANALOG 0x211 - -#define STM32H7_PA3_FUNC_GPIO 0x300 -#define STM32H7_PA3_FUNC_TIM2_CH4 0x302 -#define STM32H7_PA3_FUNC_TIM5_CH4 0x303 -#define STM32H7_PA3_FUNC_LPTIM5_OUT 0x304 -#define STM32H7_PA3_FUNC_TIM15_CH2 0x305 -#define STM32H7_PA3_FUNC_USART2_RX 0x308 -#define STM32H7_PA3_FUNC_LCD_B2 0x30a -#define STM32H7_PA3_FUNC_OTG_HS_ULPI_D0 0x30b -#define STM32H7_PA3_FUNC_ETH_MII_COL 0x30c -#define STM32H7_PA3_FUNC_LCD_B5 0x30f -#define STM32H7_PA3_FUNC_EVENTOUT 0x310 -#define STM32H7_PA3_FUNC_ANALOG 0x311 - -#define STM32H7_PA4_FUNC_GPIO 0x400 -#define STM32H7_PA4_FUNC_TIM5_ETR 0x403 -#define STM32H7_PA4_FUNC_SPI1_NSS_I2S1_WS 0x406 -#define STM32H7_PA4_FUNC_SPI3_NSS_I2S3_WS 0x407 -#define STM32H7_PA4_FUNC_USART2_CK 0x408 -#define STM32H7_PA4_FUNC_SPI6_NSS 0x409 -#define STM32H7_PA4_FUNC_OTG_HS_SOF 0x40d -#define STM32H7_PA4_FUNC_DCMI_HSYNC 0x40e -#define STM32H7_PA4_FUNC_LCD_VSYNC 0x40f -#define STM32H7_PA4_FUNC_EVENTOUT 0x410 -#define STM32H7_PA4_FUNC_ANALOG 0x411 - -#define STM32H7_PA5_FUNC_GPIO 0x500 -#define STM32H7_PA5_FUNC_TIM2_CH1_TIM2_ETR 0x502 -#define STM32H7_PA5_FUNC_TIM8_CH1N 0x504 -#define STM32H7_PA5_FUNC_SPI1_SCK_I2S1_CK 0x506 -#define STM32H7_PA5_FUNC_SPI6_SCK 0x509 -#define STM32H7_PA5_FUNC_OTG_HS_ULPI_CK 0x50b -#define STM32H7_PA5_FUNC_LCD_R4 0x50f -#define STM32H7_PA5_FUNC_EVENTOUT 0x510 -#define STM32H7_PA5_FUNC_ANALOG 0x511 - -#define STM32H7_PA6_FUNC_GPIO 0x600 -#define STM32H7_PA6_FUNC_TIM1_BKIN 0x602 -#define STM32H7_PA6_FUNC_TIM3_CH1 0x603 -#define STM32H7_PA6_FUNC_TIM8_BKIN 0x604 -#define STM32H7_PA6_FUNC_SPI1_MISO_I2S1_SDI 0x606 -#define STM32H7_PA6_FUNC_SPI6_MISO 0x609 -#define STM32H7_PA6_FUNC_TIM13_CH1 0x60a -#define STM32H7_PA6_FUNC_TIM8_BKIN_COMP12 0x60b -#define STM32H7_PA6_FUNC_MDIOS_MDC 0x60c -#define STM32H7_PA6_FUNC_TIM1_BKIN_COMP12 0x60d -#define STM32H7_PA6_FUNC_DCMI_PIXCLK 0x60e -#define STM32H7_PA6_FUNC_LCD_G2 0x60f -#define STM32H7_PA6_FUNC_EVENTOUT 0x610 -#define STM32H7_PA6_FUNC_ANALOG 0x611 - -#define STM32H7_PA7_FUNC_GPIO 0x700 -#define STM32H7_PA7_FUNC_TIM1_CH1N 0x702 -#define STM32H7_PA7_FUNC_TIM3_CH2 0x703 -#define STM32H7_PA7_FUNC_TIM8_CH1N 0x704 -#define STM32H7_PA7_FUNC_SPI1_MOSI_I2S1_SDO 0x706 -#define STM32H7_PA7_FUNC_SPI6_MOSI 0x709 -#define STM32H7_PA7_FUNC_TIM14_CH1 0x70a -#define STM32H7_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV 0x70c -#define STM32H7_PA7_FUNC_FMC_SDNWE 0x70d -#define STM32H7_PA7_FUNC_EVENTOUT 0x710 -#define STM32H7_PA7_FUNC_ANALOG 0x711 - -#define STM32H7_PA8_FUNC_GPIO 0x800 -#define STM32H7_PA8_FUNC_MCO1 0x801 -#define STM32H7_PA8_FUNC_TIM1_CH1 0x802 -#define STM32H7_PA8_FUNC_HRTIM_CHB2 0x803 -#define STM32H7_PA8_FUNC_TIM8_BKIN2 0x804 -#define STM32H7_PA8_FUNC_I2C3_SCL 0x805 -#define STM32H7_PA8_FUNC_USART1_CK 0x808 -#define STM32H7_PA8_FUNC_OTG_FS_SOF 0x80b -#define STM32H7_PA8_FUNC_UART7_RX 0x80c -#define STM32H7_PA8_FUNC_TIM8_BKIN2_COMP12 0x80d -#define STM32H7_PA8_FUNC_LCD_B3 0x80e -#define STM32H7_PA8_FUNC_LCD_R6 0x80f -#define STM32H7_PA8_FUNC_EVENTOUT 0x810 -#define STM32H7_PA8_FUNC_ANALOG 0x811 - -#define STM32H7_PA9_FUNC_GPIO 0x900 -#define STM32H7_PA9_FUNC_TIM1_CH2 0x902 -#define STM32H7_PA9_FUNC_HRTIM_CHC1 0x903 -#define STM32H7_PA9_FUNC_LPUART1_TX 0x904 -#define STM32H7_PA9_FUNC_I2C3_SMBA 0x905 -#define STM32H7_PA9_FUNC_SPI2_SCK_I2S2_CK 0x906 -#define STM32H7_PA9_FUNC_USART1_TX 0x908 -#define STM32H7_PA9_FUNC_CAN1_RXFD 0x90a -#define STM32H7_PA9_FUNC_ETH_TX_ER 0x90c -#define STM32H7_PA9_FUNC_DCMI_D0 0x90e -#define STM32H7_PA9_FUNC_LCD_R5 0x90f -#define STM32H7_PA9_FUNC_EVENTOUT 0x910 -#define STM32H7_PA9_FUNC_ANALOG 0x911 - -#define STM32H7_PA10_FUNC_GPIO 0xa00 -#define STM32H7_PA10_FUNC_TIM1_CH3 0xa02 -#define STM32H7_PA10_FUNC_HRTIM_CHC2 0xa03 -#define STM32H7_PA10_FUNC_LPUART1_RX 0xa04 -#define STM32H7_PA10_FUNC_USART1_RX 0xa08 -#define STM32H7_PA10_FUNC_CAN1_TXFD 0xa0a -#define STM32H7_PA10_FUNC_OTG_FS_ID 0xa0b -#define STM32H7_PA10_FUNC_MDIOS_MDIO 0xa0c -#define STM32H7_PA10_FUNC_LCD_B4 0xa0d -#define STM32H7_PA10_FUNC_DCMI_D1 0xa0e -#define STM32H7_PA10_FUNC_LCD_B1 0xa0f -#define STM32H7_PA10_FUNC_EVENTOUT 0xa10 -#define STM32H7_PA10_FUNC_ANALOG 0xa11 - -#define STM32H7_PA11_FUNC_GPIO 0xb00 -#define STM32H7_PA11_FUNC_TIM1_CH4 0xb02 -#define STM32H7_PA11_FUNC_HRTIM_CHD1 0xb03 -#define STM32H7_PA11_FUNC_LPUART1_CTS 0xb04 -#define STM32H7_PA11_FUNC_SPI2_NSS_I2S2_WS 0xb06 -#define STM32H7_PA11_FUNC_UART4_RX 0xb07 -#define STM32H7_PA11_FUNC_USART1_CTS_NSS 0xb08 -#define STM32H7_PA11_FUNC_CAN1_RX 0xb0a -#define STM32H7_PA11_FUNC_OTG_FS_DM 0xb0b -#define STM32H7_PA11_FUNC_LCD_R4 0xb0f -#define STM32H7_PA11_FUNC_EVENTOUT 0xb10 -#define STM32H7_PA11_FUNC_ANALOG 0xb11 - -#define STM32H7_PA12_FUNC_GPIO 0xc00 -#define STM32H7_PA12_FUNC_TIM1_ETR 0xc02 -#define STM32H7_PA12_FUNC_HRTIM_CHD2 0xc03 -#define STM32H7_PA12_FUNC_LPUART1_RTS 0xc04 -#define STM32H7_PA12_FUNC_SPI2_SCK_I2S2_CK 0xc06 -#define STM32H7_PA12_FUNC_UART4_TX 0xc07 -#define STM32H7_PA12_FUNC_USART1_RTS 0xc08 -#define STM32H7_PA12_FUNC_SAI2_FS_B 0xc09 -#define STM32H7_PA12_FUNC_CAN1_TX 0xc0a -#define STM32H7_PA12_FUNC_OTG_FS_DP 0xc0b -#define STM32H7_PA12_FUNC_LCD_R5 0xc0f -#define STM32H7_PA12_FUNC_EVENTOUT 0xc10 -#define STM32H7_PA12_FUNC_ANALOG 0xc11 - -#define STM32H7_PA13_FUNC_GPIO 0xd00 -#define STM32H7_PA13_FUNC_JTMS_SWDIO 0xd01 -#define STM32H7_PA13_FUNC_EVENTOUT 0xd10 -#define STM32H7_PA13_FUNC_ANALOG 0xd11 - -#define STM32H7_PA14_FUNC_GPIO 0xe00 -#define STM32H7_PA14_FUNC_JTCK_SWCLK 0xe01 -#define STM32H7_PA14_FUNC_EVENTOUT 0xe10 -#define STM32H7_PA14_FUNC_ANALOG 0xe11 - -#define STM32H7_PA15_FUNC_GPIO 0xf00 -#define STM32H7_PA15_FUNC_JTDI 0xf01 -#define STM32H7_PA15_FUNC_TIM2_CH1_TIM2_ETR 0xf02 -#define STM32H7_PA15_FUNC_HRTIM_FLT1 0xf03 -#define STM32H7_PA15_FUNC_HDMI_CEC 0xf05 -#define STM32H7_PA15_FUNC_SPI1_NSS_I2S1_WS 0xf06 -#define STM32H7_PA15_FUNC_SPI3_NSS_I2S3_WS 0xf07 -#define STM32H7_PA15_FUNC_SPI6_NSS 0xf08 -#define STM32H7_PA15_FUNC_UART4_RTS 0xf09 -#define STM32H7_PA15_FUNC_UART7_TX 0xf0c -#define STM32H7_PA15_FUNC_DSI_TE 0xf0e -#define STM32H7_PA15_FUNC_EVENTOUT 0xf10 -#define STM32H7_PA15_FUNC_ANALOG 0xf11 - -#define STM32H7_PB0_FUNC_GPIO 0x1000 -#define STM32H7_PB0_FUNC_TIM1_CH2N 0x1002 -#define STM32H7_PB0_FUNC_TIM3_CH3 0x1003 -#define STM32H7_PB0_FUNC_TIM8_CH2N 0x1004 -#define STM32H7_PB0_FUNC_DFSDM_CKOUT 0x1007 -#define STM32H7_PB0_FUNC_UART4_CTS 0x1009 -#define STM32H7_PB0_FUNC_LCD_R3 0x100a -#define STM32H7_PB0_FUNC_OTG_HS_ULPI_D1 0x100b -#define STM32H7_PB0_FUNC_ETH_MII_RXD2 0x100c -#define STM32H7_PB0_FUNC_LCD_G1 0x100f -#define STM32H7_PB0_FUNC_EVENTOUT 0x1010 -#define STM32H7_PB0_FUNC_ANALOG 0x1011 - -#define STM32H7_PB1_FUNC_GPIO 0x1100 -#define STM32H7_PB1_FUNC_TIM1_CH3N 0x1102 -#define STM32H7_PB1_FUNC_TIM3_CH4 0x1103 -#define STM32H7_PB1_FUNC_TIM8_CH3N 0x1104 -#define STM32H7_PB1_FUNC_DFSDM_DATIN1 0x1107 -#define STM32H7_PB1_FUNC_LCD_R6 0x110a -#define STM32H7_PB1_FUNC_OTG_HS_ULPI_D2 0x110b -#define STM32H7_PB1_FUNC_ETH_MII_RXD3 0x110c -#define STM32H7_PB1_FUNC_LCD_G0 0x110f -#define STM32H7_PB1_FUNC_EVENTOUT 0x1110 -#define STM32H7_PB1_FUNC_ANALOG 0x1111 - -#define STM32H7_PB2_FUNC_GPIO 0x1200 -#define STM32H7_PB2_FUNC_SAI1_D1 0x1203 -#define STM32H7_PB2_FUNC_DFSDM_CKIN1 0x1205 -#define STM32H7_PB2_FUNC_SAI1_SD_A 0x1207 -#define STM32H7_PB2_FUNC_SPI3_MOSI_I2S3_SDO 0x1208 -#define STM32H7_PB2_FUNC_SAI4_SD_A 0x1209 -#define STM32H7_PB2_FUNC_QUADSPI_CLK 0x120a -#define STM32H7_PB2_FUNC_SAI4_D1 0x120b -#define STM32H7_PB2_FUNC_ETH_TX_ER 0x120c -#define STM32H7_PB2_FUNC_EVENTOUT 0x1210 -#define STM32H7_PB2_FUNC_ANALOG 0x1211 - -#define STM32H7_PB3_FUNC_GPIO 0x1300 -#define STM32H7_PB3_FUNC_JTDO_TRACESWO 0x1301 -#define STM32H7_PB3_FUNC_TIM2_CH2 0x1302 -#define STM32H7_PB3_FUNC_HRTIM_FLT4 0x1303 -#define STM32H7_PB3_FUNC_SPI1_SCK_I2S1_CK 0x1306 -#define STM32H7_PB3_FUNC_SPI3_SCK_I2S3_CK 0x1307 -#define STM32H7_PB3_FUNC_SPI6_SCK 0x1309 -#define STM32H7_PB3_FUNC_SDMMC2_D2 0x130a -#define STM32H7_PB3_FUNC_UART7_RX 0x130c -#define STM32H7_PB3_FUNC_EVENTOUT 0x1310 -#define STM32H7_PB3_FUNC_ANALOG 0x1311 - -#define STM32H7_PB4_FUNC_GPIO 0x1400 -#define STM32H7_PB4_FUNC_NJTRST 0x1401 -#define STM32H7_PB4_FUNC_TIM16_BKIN 0x1402 -#define STM32H7_PB4_FUNC_TIM3_CH1 0x1403 -#define STM32H7_PB4_FUNC_HRTIM_EEV6 0x1404 -#define STM32H7_PB4_FUNC_SPI1_MISO_I2S1_SDI 0x1406 -#define STM32H7_PB4_FUNC_SPI3_MISO_I2S3_SDI 0x1407 -#define STM32H7_PB4_FUNC_SPI2_NSS_I2S2_WS 0x1408 -#define STM32H7_PB4_FUNC_SPI6_MISO 0x1409 -#define STM32H7_PB4_FUNC_SDMMC2_D3 0x140a -#define STM32H7_PB4_FUNC_UART7_TX 0x140c -#define STM32H7_PB4_FUNC_EVENTOUT 0x1410 -#define STM32H7_PB4_FUNC_ANALOG 0x1411 - -#define STM32H7_PB5_FUNC_GPIO 0x1500 -#define STM32H7_PB5_FUNC_TIM17_BKIN 0x1502 -#define STM32H7_PB5_FUNC_TIM3_CH2 0x1503 -#define STM32H7_PB5_FUNC_HRTIM_EEV7 0x1504 -#define STM32H7_PB5_FUNC_I2C1_SMBA 0x1505 -#define STM32H7_PB5_FUNC_SPI1_MOSI_I2S1_SDO 0x1506 -#define STM32H7_PB5_FUNC_I2C4_SMBA 0x1507 -#define STM32H7_PB5_FUNC_SPI3_MOSI_I2S3_SDO 0x1508 -#define STM32H7_PB5_FUNC_SPI6_MOSI 0x1509 -#define STM32H7_PB5_FUNC_CAN2_RX 0x150a -#define STM32H7_PB5_FUNC_OTG_HS_ULPI_D7 0x150b -#define STM32H7_PB5_FUNC_ETH_PPS_OUT 0x150c -#define STM32H7_PB5_FUNC_FMC_SDCKE1 0x150d -#define STM32H7_PB5_FUNC_DCMI_D10 0x150e -#define STM32H7_PB5_FUNC_UART5_RX 0x150f -#define STM32H7_PB5_FUNC_EVENTOUT 0x1510 -#define STM32H7_PB5_FUNC_ANALOG 0x1511 - -#define STM32H7_PB6_FUNC_GPIO 0x1600 -#define STM32H7_PB6_FUNC_TIM16_CH1N 0x1602 -#define STM32H7_PB6_FUNC_TIM4_CH1 0x1603 -#define STM32H7_PB6_FUNC_HRTIM_EEV8 0x1604 -#define STM32H7_PB6_FUNC_I2C1_SCL 0x1605 -#define STM32H7_PB6_FUNC_HDMI_CEC 0x1606 -#define STM32H7_PB6_FUNC_I2C4_SCL 0x1607 -#define STM32H7_PB6_FUNC_USART1_TX 0x1608 -#define STM32H7_PB6_FUNC_LPUART1_TX 0x1609 -#define STM32H7_PB6_FUNC_CAN2_TX 0x160a -#define STM32H7_PB6_FUNC_QUADSPI_BK1_NCS 0x160b -#define STM32H7_PB6_FUNC_DFSDM_DATIN5 0x160c -#define STM32H7_PB6_FUNC_FMC_SDNE1 0x160d -#define STM32H7_PB6_FUNC_DCMI_D5 0x160e -#define STM32H7_PB6_FUNC_UART5_TX 0x160f -#define STM32H7_PB6_FUNC_EVENTOUT 0x1610 -#define STM32H7_PB6_FUNC_ANALOG 0x1611 - -#define STM32H7_PB7_FUNC_GPIO 0x1700 -#define STM32H7_PB7_FUNC_TIM17_CH1N 0x1702 -#define STM32H7_PB7_FUNC_TIM4_CH2 0x1703 -#define STM32H7_PB7_FUNC_HRTIM_EEV9 0x1704 -#define STM32H7_PB7_FUNC_I2C1_SDA 0x1705 -#define STM32H7_PB7_FUNC_I2C4_SDA 0x1707 -#define STM32H7_PB7_FUNC_USART1_RX 0x1708 -#define STM32H7_PB7_FUNC_LPUART1_RX 0x1709 -#define STM32H7_PB7_FUNC_CAN2_TXFD 0x170a -#define STM32H7_PB7_FUNC_DFSDM_CKIN5 0x170c -#define STM32H7_PB7_FUNC_FMC_NL 0x170d -#define STM32H7_PB7_FUNC_DCMI_VSYNC 0x170e -#define STM32H7_PB7_FUNC_EVENTOUT 0x1710 -#define STM32H7_PB7_FUNC_ANALOG 0x1711 - -#define STM32H7_PB8_FUNC_GPIO 0x1800 -#define STM32H7_PB8_FUNC_TIM16_CH1 0x1802 -#define STM32H7_PB8_FUNC_TIM4_CH3 0x1803 -#define STM32H7_PB8_FUNC_DFSDM_CKIN7 0x1804 -#define STM32H7_PB8_FUNC_I2C1_SCL 0x1805 -#define STM32H7_PB8_FUNC_I2C4_SCL 0x1807 -#define STM32H7_PB8_FUNC_SDMMC1_CKIN 0x1808 -#define STM32H7_PB8_FUNC_UART4_RX 0x1809 -#define STM32H7_PB8_FUNC_CAN1_RX 0x180a -#define STM32H7_PB8_FUNC_SDMMC2_D4 0x180b -#define STM32H7_PB8_FUNC_ETH_MII_TXD3 0x180c -#define STM32H7_PB8_FUNC_SDMMC1_D4 0x180d -#define STM32H7_PB8_FUNC_DCMI_D6 0x180e -#define STM32H7_PB8_FUNC_LCD_B6 0x180f -#define STM32H7_PB8_FUNC_EVENTOUT 0x1810 -#define STM32H7_PB8_FUNC_ANALOG 0x1811 - -#define STM32H7_PB9_FUNC_GPIO 0x1900 -#define STM32H7_PB9_FUNC_TIM17_CH1 0x1902 -#define STM32H7_PB9_FUNC_TIM4_CH4 0x1903 -#define STM32H7_PB9_FUNC_DFSDM_DATIN7 0x1904 -#define STM32H7_PB9_FUNC_I2C1_SDA 0x1905 -#define STM32H7_PB9_FUNC_SPI2_NSS_I2S2_WS 0x1906 -#define STM32H7_PB9_FUNC_I2C4_SDA 0x1907 -#define STM32H7_PB9_FUNC_SDMMC1_CDIR 0x1908 -#define STM32H7_PB9_FUNC_UART4_TX 0x1909 -#define STM32H7_PB9_FUNC_CAN1_TX 0x190a -#define STM32H7_PB9_FUNC_SDMMC2_D5 0x190b -#define STM32H7_PB9_FUNC_I2C4_SMBA 0x190c -#define STM32H7_PB9_FUNC_SDMMC1_D5 0x190d -#define STM32H7_PB9_FUNC_DCMI_D7 0x190e -#define STM32H7_PB9_FUNC_LCD_B7 0x190f -#define STM32H7_PB9_FUNC_EVENTOUT 0x1910 -#define STM32H7_PB9_FUNC_ANALOG 0x1911 - -#define STM32H7_PB10_FUNC_GPIO 0x1a00 -#define STM32H7_PB10_FUNC_TIM2_CH3 0x1a02 -#define STM32H7_PB10_FUNC_HRTIM_SCOUT 0x1a03 -#define STM32H7_PB10_FUNC_LPTIM2_IN1 0x1a04 -#define STM32H7_PB10_FUNC_I2C2_SCL 0x1a05 -#define STM32H7_PB10_FUNC_SPI2_SCK_I2S2_CK 0x1a06 -#define STM32H7_PB10_FUNC_DFSDM_DATIN7 0x1a07 -#define STM32H7_PB10_FUNC_USART3_TX 0x1a08 -#define STM32H7_PB10_FUNC_QUADSPI_BK1_NCS 0x1a0a -#define STM32H7_PB10_FUNC_OTG_HS_ULPI_D3 0x1a0b -#define STM32H7_PB10_FUNC_ETH_MII_RX_ER 0x1a0c -#define STM32H7_PB10_FUNC_LCD_G4 0x1a0f -#define STM32H7_PB10_FUNC_EVENTOUT 0x1a10 -#define STM32H7_PB10_FUNC_ANALOG 0x1a11 - -#define STM32H7_PB11_FUNC_GPIO 0x1b00 -#define STM32H7_PB11_FUNC_TIM2_CH4 0x1b02 -#define STM32H7_PB11_FUNC_HRTIM_SCIN 0x1b03 -#define STM32H7_PB11_FUNC_LPTIM2_ETR 0x1b04 -#define STM32H7_PB11_FUNC_I2C2_SDA 0x1b05 -#define STM32H7_PB11_FUNC_DFSDM_CKIN7 0x1b07 -#define STM32H7_PB11_FUNC_USART3_RX 0x1b08 -#define STM32H7_PB11_FUNC_OTG_HS_ULPI_D4 0x1b0b -#define STM32H7_PB11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN 0x1b0c -#define STM32H7_PB11_FUNC_DSI_TE 0x1b0e -#define STM32H7_PB11_FUNC_LCD_G5 0x1b0f -#define STM32H7_PB11_FUNC_EVENTOUT 0x1b10 -#define STM32H7_PB11_FUNC_ANALOG 0x1b11 - -#define STM32H7_PB12_FUNC_GPIO 0x1c00 -#define STM32H7_PB12_FUNC_TIM1_BKIN 0x1c02 -#define STM32H7_PB12_FUNC_I2C2_SMBA 0x1c05 -#define STM32H7_PB12_FUNC_SPI2_NSS_I2S2_WS 0x1c06 -#define STM32H7_PB12_FUNC_DFSDM_DATIN1 0x1c07 -#define STM32H7_PB12_FUNC_USART3_CK 0x1c08 -#define STM32H7_PB12_FUNC_CAN2_RX 0x1c0a -#define STM32H7_PB12_FUNC_OTG_HS_ULPI_D5 0x1c0b -#define STM32H7_PB12_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0 0x1c0c -#define STM32H7_PB12_FUNC_OTG_HS_ID 0x1c0d -#define STM32H7_PB12_FUNC_TIM1_BKIN_COMP12 0x1c0e -#define STM32H7_PB12_FUNC_UART5_RX 0x1c0f -#define STM32H7_PB12_FUNC_EVENTOUT 0x1c10 -#define STM32H7_PB12_FUNC_ANALOG 0x1c11 - -#define STM32H7_PB13_FUNC_GPIO 0x1d00 -#define STM32H7_PB13_FUNC_TIM1_CH1N 0x1d02 -#define STM32H7_PB13_FUNC_LPTIM2_OUT 0x1d04 -#define STM32H7_PB13_FUNC_SPI2_SCK_I2S2_CK 0x1d06 -#define STM32H7_PB13_FUNC_DFSDM_CKIN1 0x1d07 -#define STM32H7_PB13_FUNC_USART3_CTS_NSS 0x1d08 -#define STM32H7_PB13_FUNC_CAN2_TX 0x1d0a -#define STM32H7_PB13_FUNC_OTG_HS_ULPI_D6 0x1d0b -#define STM32H7_PB13_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1 0x1d0c -#define STM32H7_PB13_FUNC_UART5_TX 0x1d0f -#define STM32H7_PB13_FUNC_EVENTOUT 0x1d10 -#define STM32H7_PB13_FUNC_ANALOG 0x1d11 - -#define STM32H7_PB14_FUNC_GPIO 0x1e00 -#define STM32H7_PB14_FUNC_TIM1_CH2N 0x1e02 -#define STM32H7_PB14_FUNC_TIM8_CH2N 0x1e04 -#define STM32H7_PB14_FUNC_USART1_TX 0x1e05 -#define STM32H7_PB14_FUNC_SPI2_MISO_I2S2_SDI 0x1e06 -#define STM32H7_PB14_FUNC_DFSDM_DATIN2 0x1e07 -#define STM32H7_PB14_FUNC_USART3_RTS 0x1e08 -#define STM32H7_PB14_FUNC_UART4_RTS 0x1e09 -#define STM32H7_PB14_FUNC_SDMMC2_D0 0x1e0a -#define STM32H7_PB14_FUNC_OTG_HS_DM 0x1e0d -#define STM32H7_PB14_FUNC_EVENTOUT 0x1e10 -#define STM32H7_PB14_FUNC_ANALOG 0x1e11 - -#define STM32H7_PB15_FUNC_GPIO 0x1f00 -#define STM32H7_PB15_FUNC_RTC_REFIN 0x1f01 -#define STM32H7_PB15_FUNC_TIM1_CH3N 0x1f02 -#define STM32H7_PB15_FUNC_TIM8_CH3N 0x1f04 -#define STM32H7_PB15_FUNC_USART1_RX 0x1f05 -#define STM32H7_PB15_FUNC_SPI2_MOSI_I2S2_SDO 0x1f06 -#define STM32H7_PB15_FUNC_DFSDM_CKIN2 0x1f07 -#define STM32H7_PB15_FUNC_UART4_CTS 0x1f09 -#define STM32H7_PB15_FUNC_SDMMC2_D1 0x1f0a -#define STM32H7_PB15_FUNC_OTG_HS_DP 0x1f0d -#define STM32H7_PB15_FUNC_EVENTOUT 0x1f10 -#define STM32H7_PB15_FUNC_ANALOG 0x1f11 - -#define STM32H7_PC0_FUNC_GPIO 0x2000 -#define STM32H7_PC0_FUNC_DFSDM_CKIN0 0x2004 -#define STM32H7_PC0_FUNC_DFSDM_DATIN4 0x2007 -#define STM32H7_PC0_FUNC_SAI2_FS_B 0x2009 -#define STM32H7_PC0_FUNC_OTG_HS_ULPI_STP 0x200b -#define STM32H7_PC0_FUNC_FMC_SDNWE 0x200d -#define STM32H7_PC0_FUNC_LCD_R5 0x200f -#define STM32H7_PC0_FUNC_EVENTOUT 0x2010 -#define STM32H7_PC0_FUNC_ANALOG 0x2011 - -#define STM32H7_PC1_FUNC_GPIO 0x2100 -#define STM32H7_PC1_FUNC_TRACED0 0x2101 -#define STM32H7_PC1_FUNC_SAI1_D1 0x2103 -#define STM32H7_PC1_FUNC_DFSDM_DATIN0 0x2104 -#define STM32H7_PC1_FUNC_DFSDM_CKIN4 0x2105 -#define STM32H7_PC1_FUNC_SPI2_MOSI_I2S2_SDO 0x2106 -#define STM32H7_PC1_FUNC_SAI1_SD_A 0x2107 -#define STM32H7_PC1_FUNC_SAI4_SD_A 0x2109 -#define STM32H7_PC1_FUNC_SDMMC2_CK 0x210a -#define STM32H7_PC1_FUNC_SAI4_D1 0x210b -#define STM32H7_PC1_FUNC_ETH_MDC 0x210c -#define STM32H7_PC1_FUNC_MDIOS_MDC 0x210d -#define STM32H7_PC1_FUNC_EVENTOUT 0x2110 -#define STM32H7_PC1_FUNC_ANALOG 0x2111 - -#define STM32H7_PC2_FUNC_GPIO 0x2200 -#define STM32H7_PC2_FUNC_DFSDM_CKIN1 0x2204 -#define STM32H7_PC2_FUNC_SPI2_MISO_I2S2_SDI 0x2206 -#define STM32H7_PC2_FUNC_DFSDM_CKOUT 0x2207 -#define STM32H7_PC2_FUNC_OTG_HS_ULPI_DIR 0x220b -#define STM32H7_PC2_FUNC_ETH_MII_TXD2 0x220c -#define STM32H7_PC2_FUNC_FMC_SDNE0 0x220d -#define STM32H7_PC2_FUNC_EVENTOUT 0x2210 -#define STM32H7_PC2_FUNC_ANALOG 0x2211 - -#define STM32H7_PC3_FUNC_GPIO 0x2300 -#define STM32H7_PC3_FUNC_DFSDM_DATIN1 0x2304 -#define STM32H7_PC3_FUNC_SPI2_MOSI_I2S2_SDO 0x2306 -#define STM32H7_PC3_FUNC_OTG_HS_ULPI_NXT 0x230b -#define STM32H7_PC3_FUNC_ETH_MII_TX_CLK 0x230c -#define STM32H7_PC3_FUNC_FMC_SDCKE0 0x230d -#define STM32H7_PC3_FUNC_EVENTOUT 0x2310 -#define STM32H7_PC3_FUNC_ANALOG 0x2311 - -#define STM32H7_PC4_FUNC_GPIO 0x2400 -#define STM32H7_PC4_FUNC_DFSDM_CKIN2 0x2404 -#define STM32H7_PC4_FUNC_I2S1_MCK 0x2406 -#define STM32H7_PC4_FUNC_SPDIFRX_IN2 0x240a -#define STM32H7_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0 0x240c -#define STM32H7_PC4_FUNC_FMC_SDNE0 0x240d -#define STM32H7_PC4_FUNC_EVENTOUT 0x2410 -#define STM32H7_PC4_FUNC_ANALOG 0x2411 - -#define STM32H7_PC5_FUNC_GPIO 0x2500 -#define STM32H7_PC5_FUNC_SAI1_D3 0x2503 -#define STM32H7_PC5_FUNC_DFSDM_DATIN2 0x2504 -#define STM32H7_PC5_FUNC_SPDIFRX_IN3 0x250a -#define STM32H7_PC5_FUNC_SAI4_D3 0x250b -#define STM32H7_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1 0x250c -#define STM32H7_PC5_FUNC_FMC_SDCKE0 0x250d -#define STM32H7_PC5_FUNC_COMP_1_OUT 0x250e -#define STM32H7_PC5_FUNC_EVENTOUT 0x2510 -#define STM32H7_PC5_FUNC_ANALOG 0x2511 - -#define STM32H7_PC6_FUNC_GPIO 0x2600 -#define STM32H7_PC6_FUNC_HRTIM_CHA1 0x2602 -#define STM32H7_PC6_FUNC_TIM3_CH1 0x2603 -#define STM32H7_PC6_FUNC_TIM8_CH1 0x2604 -#define STM32H7_PC6_FUNC_DFSDM_CKIN3 0x2605 -#define STM32H7_PC6_FUNC_I2S2_MCK 0x2606 -#define STM32H7_PC6_FUNC_USART6_TX 0x2608 -#define STM32H7_PC6_FUNC_SDMMC1_D0DIR 0x2609 -#define STM32H7_PC6_FUNC_FMC_NWAIT 0x260a -#define STM32H7_PC6_FUNC_SDMMC2_D6 0x260b -#define STM32H7_PC6_FUNC_SDMMC1_D6 0x260d -#define STM32H7_PC6_FUNC_DCMI_D0 0x260e -#define STM32H7_PC6_FUNC_LCD_HSYNC 0x260f -#define STM32H7_PC6_FUNC_EVENTOUT 0x2610 -#define STM32H7_PC6_FUNC_ANALOG 0x2611 - -#define STM32H7_PC7_FUNC_GPIO 0x2700 -#define STM32H7_PC7_FUNC_TRGIO 0x2701 -#define STM32H7_PC7_FUNC_HRTIM_CHA2 0x2702 -#define STM32H7_PC7_FUNC_TIM3_CH2 0x2703 -#define STM32H7_PC7_FUNC_TIM8_CH2 0x2704 -#define STM32H7_PC7_FUNC_DFSDM_DATIN3 0x2705 -#define STM32H7_PC7_FUNC_I2S3_MCK 0x2707 -#define STM32H7_PC7_FUNC_USART6_RX 0x2708 -#define STM32H7_PC7_FUNC_SDMMC1_D123DIR 0x2709 -#define STM32H7_PC7_FUNC_FMC_NE1 0x270a -#define STM32H7_PC7_FUNC_SDMMC2_D7 0x270b -#define STM32H7_PC7_FUNC_SWPMI_TX 0x270c -#define STM32H7_PC7_FUNC_SDMMC1_D7 0x270d -#define STM32H7_PC7_FUNC_DCMI_D1 0x270e -#define STM32H7_PC7_FUNC_LCD_G6 0x270f -#define STM32H7_PC7_FUNC_EVENTOUT 0x2710 -#define STM32H7_PC7_FUNC_ANALOG 0x2711 - -#define STM32H7_PC8_FUNC_GPIO 0x2800 -#define STM32H7_PC8_FUNC_TRACED1 0x2801 -#define STM32H7_PC8_FUNC_HRTIM_CHB1 0x2802 -#define STM32H7_PC8_FUNC_TIM3_CH3 0x2803 -#define STM32H7_PC8_FUNC_TIM8_CH3 0x2804 -#define STM32H7_PC8_FUNC_USART6_CK 0x2808 -#define STM32H7_PC8_FUNC_UART5_RTS 0x2809 -#define STM32H7_PC8_FUNC_FMC_NE2_FMC_NCE 0x280a -#define STM32H7_PC8_FUNC_SWPMI_RX 0x280c -#define STM32H7_PC8_FUNC_SDMMC1_D0 0x280d -#define STM32H7_PC8_FUNC_DCMI_D2 0x280e -#define STM32H7_PC8_FUNC_EVENTOUT 0x2810 -#define STM32H7_PC8_FUNC_ANALOG 0x2811 - -#define STM32H7_PC9_FUNC_GPIO 0x2900 -#define STM32H7_PC9_FUNC_MCO2 0x2901 -#define STM32H7_PC9_FUNC_TIM3_CH4 0x2903 -#define STM32H7_PC9_FUNC_TIM8_CH4 0x2904 -#define STM32H7_PC9_FUNC_I2C3_SDA 0x2905 -#define STM32H7_PC9_FUNC_I2S_CKIN 0x2906 -#define STM32H7_PC9_FUNC_UART5_CTS 0x2909 -#define STM32H7_PC9_FUNC_QUADSPI_BK1_IO0 0x290a -#define STM32H7_PC9_FUNC_LCD_G3 0x290b -#define STM32H7_PC9_FUNC_SWPMI_SUSPEND 0x290c -#define STM32H7_PC9_FUNC_SDMMC1_D1 0x290d -#define STM32H7_PC9_FUNC_DCMI_D3 0x290e -#define STM32H7_PC9_FUNC_LCD_B2 0x290f -#define STM32H7_PC9_FUNC_EVENTOUT 0x2910 -#define STM32H7_PC9_FUNC_ANALOG 0x2911 - -#define STM32H7_PC10_FUNC_GPIO 0x2a00 -#define STM32H7_PC10_FUNC_HRTIM_EEV1 0x2a03 -#define STM32H7_PC10_FUNC_DFSDM_CKIN5 0x2a04 -#define STM32H7_PC10_FUNC_SPI3_SCK_I2S3_CK 0x2a07 -#define STM32H7_PC10_FUNC_USART3_TX 0x2a08 -#define STM32H7_PC10_FUNC_UART4_TX 0x2a09 -#define STM32H7_PC10_FUNC_QUADSPI_BK1_IO1 0x2a0a -#define STM32H7_PC10_FUNC_SDMMC1_D2 0x2a0d -#define STM32H7_PC10_FUNC_DCMI_D8 0x2a0e -#define STM32H7_PC10_FUNC_LCD_R2 0x2a0f -#define STM32H7_PC10_FUNC_EVENTOUT 0x2a10 -#define STM32H7_PC10_FUNC_ANALOG 0x2a11 - -#define STM32H7_PC11_FUNC_GPIO 0x2b00 -#define STM32H7_PC11_FUNC_HRTIM_FLT2 0x2b03 -#define STM32H7_PC11_FUNC_DFSDM_DATIN5 0x2b04 -#define STM32H7_PC11_FUNC_SPI3_MISO_I2S3_SDI 0x2b07 -#define STM32H7_PC11_FUNC_USART3_RX 0x2b08 -#define STM32H7_PC11_FUNC_UART4_RX 0x2b09 -#define STM32H7_PC11_FUNC_QUADSPI_BK2_NCS 0x2b0a -#define STM32H7_PC11_FUNC_SDMMC1_D3 0x2b0d -#define STM32H7_PC11_FUNC_DCMI_D4 0x2b0e -#define STM32H7_PC11_FUNC_EVENTOUT 0x2b10 -#define STM32H7_PC11_FUNC_ANALOG 0x2b11 - -#define STM32H7_PC12_FUNC_GPIO 0x2c00 -#define STM32H7_PC12_FUNC_TRACED3 0x2c01 -#define STM32H7_PC12_FUNC_HRTIM_EEV2 0x2c03 -#define STM32H7_PC12_FUNC_SPI3_MOSI_I2S3_SDO 0x2c07 -#define STM32H7_PC12_FUNC_USART3_CK 0x2c08 -#define STM32H7_PC12_FUNC_UART5_TX 0x2c09 -#define STM32H7_PC12_FUNC_SDMMC1_CK 0x2c0d -#define STM32H7_PC12_FUNC_DCMI_D9 0x2c0e -#define STM32H7_PC12_FUNC_EVENTOUT 0x2c10 -#define STM32H7_PC12_FUNC_ANALOG 0x2c11 - -#define STM32H7_PC13_FUNC_GPIO 0x2d00 -#define STM32H7_PC13_FUNC_EVENTOUT 0x2d10 -#define STM32H7_PC13_FUNC_ANALOG 0x2d11 - -#define STM32H7_PC14_FUNC_GPIO 0x2e00 -#define STM32H7_PC14_FUNC_EVENTOUT 0x2e10 -#define STM32H7_PC14_FUNC_ANALOG 0x2e11 - -#define STM32H7_PC15_FUNC_GPIO 0x2f00 -#define STM32H7_PC15_FUNC_EVENTOUT 0x2f10 -#define STM32H7_PC15_FUNC_ANALOG 0x2f11 - -#define STM32H7_PD0_FUNC_GPIO 0x3000 -#define STM32H7_PD0_FUNC_DFSDM_CKIN6 0x3004 -#define STM32H7_PD0_FUNC_SAI3_SCK_A 0x3007 -#define STM32H7_PD0_FUNC_UART4_RX 0x3009 -#define STM32H7_PD0_FUNC_CAN1_RX 0x300a -#define STM32H7_PD0_FUNC_FMC_D2_FMC_DA2 0x300d -#define STM32H7_PD0_FUNC_EVENTOUT 0x3010 -#define STM32H7_PD0_FUNC_ANALOG 0x3011 - -#define STM32H7_PD1_FUNC_GPIO 0x3100 -#define STM32H7_PD1_FUNC_DFSDM_DATIN6 0x3104 -#define STM32H7_PD1_FUNC_SAI3_SD_A 0x3107 -#define STM32H7_PD1_FUNC_UART4_TX 0x3109 -#define STM32H7_PD1_FUNC_CAN1_TX 0x310a -#define STM32H7_PD1_FUNC_FMC_D3_FMC_DA3 0x310d -#define STM32H7_PD1_FUNC_EVENTOUT 0x3110 -#define STM32H7_PD1_FUNC_ANALOG 0x3111 - -#define STM32H7_PD2_FUNC_GPIO 0x3200 -#define STM32H7_PD2_FUNC_TRACED2 0x3201 -#define STM32H7_PD2_FUNC_TIM3_ETR 0x3203 -#define STM32H7_PD2_FUNC_UART5_RX 0x3209 -#define STM32H7_PD2_FUNC_SDMMC1_CMD 0x320d -#define STM32H7_PD2_FUNC_DCMI_D11 0x320e -#define STM32H7_PD2_FUNC_EVENTOUT 0x3210 -#define STM32H7_PD2_FUNC_ANALOG 0x3211 - -#define STM32H7_PD3_FUNC_GPIO 0x3300 -#define STM32H7_PD3_FUNC_DFSDM_CKOUT 0x3304 -#define STM32H7_PD3_FUNC_SPI2_SCK_I2S2_CK 0x3306 -#define STM32H7_PD3_FUNC_USART2_CTS_NSS 0x3308 -#define STM32H7_PD3_FUNC_FMC_CLK 0x330d -#define STM32H7_PD3_FUNC_DCMI_D5 0x330e -#define STM32H7_PD3_FUNC_LCD_G7 0x330f -#define STM32H7_PD3_FUNC_EVENTOUT 0x3310 -#define STM32H7_PD3_FUNC_ANALOG 0x3311 - -#define STM32H7_PD4_FUNC_GPIO 0x3400 -#define STM32H7_PD4_FUNC_HRTIM_FLT3 0x3403 -#define STM32H7_PD4_FUNC_SAI3_FS_A 0x3407 -#define STM32H7_PD4_FUNC_USART2_RTS 0x3408 -#define STM32H7_PD4_FUNC_CAN1_RXFD 0x340a -#define STM32H7_PD4_FUNC_FMC_NOE 0x340d -#define STM32H7_PD4_FUNC_EVENTOUT 0x3410 -#define STM32H7_PD4_FUNC_ANALOG 0x3411 - -#define STM32H7_PD5_FUNC_GPIO 0x3500 -#define STM32H7_PD5_FUNC_HRTIM_EEV3 0x3503 -#define STM32H7_PD5_FUNC_USART2_TX 0x3508 -#define STM32H7_PD5_FUNC_CAN1_TXFD 0x350a -#define STM32H7_PD5_FUNC_FMC_NWE 0x350d -#define STM32H7_PD5_FUNC_EVENTOUT 0x3510 -#define STM32H7_PD5_FUNC_ANALOG 0x3511 - -#define STM32H7_PD6_FUNC_GPIO 0x3600 -#define STM32H7_PD6_FUNC_SAI1_D1 0x3603 -#define STM32H7_PD6_FUNC_DFSDM_CKIN4 0x3604 -#define STM32H7_PD6_FUNC_DFSDM_DATIN1 0x3605 -#define STM32H7_PD6_FUNC_SPI3_MOSI_I2S3_SDO 0x3606 -#define STM32H7_PD6_FUNC_SAI1_SD_A 0x3607 -#define STM32H7_PD6_FUNC_USART2_RX 0x3608 -#define STM32H7_PD6_FUNC_SAI4_SD_A 0x3609 -#define STM32H7_PD6_FUNC_CAN2_RXFD 0x360a -#define STM32H7_PD6_FUNC_SAI4_D1 0x360b -#define STM32H7_PD6_FUNC_SDMMC2_CK 0x360c -#define STM32H7_PD6_FUNC_FMC_NWAIT 0x360d -#define STM32H7_PD6_FUNC_DCMI_D10 0x360e -#define STM32H7_PD6_FUNC_LCD_B2 0x360f -#define STM32H7_PD6_FUNC_EVENTOUT 0x3610 -#define STM32H7_PD6_FUNC_ANALOG 0x3611 - -#define STM32H7_PD7_FUNC_GPIO 0x3700 -#define STM32H7_PD7_FUNC_DFSDM_DATIN4 0x3704 -#define STM32H7_PD7_FUNC_SPI1_MOSI_I2S1_SDO 0x3706 -#define STM32H7_PD7_FUNC_DFSDM_CKIN1 0x3707 -#define STM32H7_PD7_FUNC_USART2_CK 0x3708 -#define STM32H7_PD7_FUNC_SPDIFRX_IN0 0x370a -#define STM32H7_PD7_FUNC_SDMMC2_CMD 0x370c -#define STM32H7_PD7_FUNC_FMC_NE1 0x370d -#define STM32H7_PD7_FUNC_EVENTOUT 0x3710 -#define STM32H7_PD7_FUNC_ANALOG 0x3711 - -#define STM32H7_PD8_FUNC_GPIO 0x3800 -#define STM32H7_PD8_FUNC_DFSDM_CKIN3 0x3804 -#define STM32H7_PD8_FUNC_SAI3_SCK_B 0x3807 -#define STM32H7_PD8_FUNC_USART3_TX 0x3808 -#define STM32H7_PD8_FUNC_SPDIFRX_IN1 0x380a -#define STM32H7_PD8_FUNC_FMC_D13_FMC_DA13 0x380d -#define STM32H7_PD8_FUNC_EVENTOUT 0x3810 -#define STM32H7_PD8_FUNC_ANALOG 0x3811 - -#define STM32H7_PD9_FUNC_GPIO 0x3900 -#define STM32H7_PD9_FUNC_DFSDM_DATIN3 0x3904 -#define STM32H7_PD9_FUNC_SAI3_SD_B 0x3907 -#define STM32H7_PD9_FUNC_USART3_RX 0x3908 -#define STM32H7_PD9_FUNC_CAN2_RXFD 0x390a -#define STM32H7_PD9_FUNC_FMC_D14_FMC_DA14 0x390d -#define STM32H7_PD9_FUNC_EVENTOUT 0x3910 -#define STM32H7_PD9_FUNC_ANALOG 0x3911 - -#define STM32H7_PD10_FUNC_GPIO 0x3a00 -#define STM32H7_PD10_FUNC_DFSDM_CKOUT 0x3a04 -#define STM32H7_PD10_FUNC_SAI3_FS_B 0x3a07 -#define STM32H7_PD10_FUNC_USART3_CK 0x3a08 -#define STM32H7_PD10_FUNC_CAN2_TXFD 0x3a0a -#define STM32H7_PD10_FUNC_FMC_D15_FMC_DA15 0x3a0d -#define STM32H7_PD10_FUNC_LCD_B3 0x3a0f -#define STM32H7_PD10_FUNC_EVENTOUT 0x3a10 -#define STM32H7_PD10_FUNC_ANALOG 0x3a11 - -#define STM32H7_PD11_FUNC_GPIO 0x3b00 -#define STM32H7_PD11_FUNC_LPTIM2_IN2 0x3b04 -#define STM32H7_PD11_FUNC_I2C4_SMBA 0x3b05 -#define STM32H7_PD11_FUNC_USART3_CTS_NSS 0x3b08 -#define STM32H7_PD11_FUNC_QUADSPI_BK1_IO0 0x3b0a -#define STM32H7_PD11_FUNC_SAI2_SD_A 0x3b0b -#define STM32H7_PD11_FUNC_FMC_A16 0x3b0d -#define STM32H7_PD11_FUNC_EVENTOUT 0x3b10 -#define STM32H7_PD11_FUNC_ANALOG 0x3b11 - -#define STM32H7_PD12_FUNC_GPIO 0x3c00 -#define STM32H7_PD12_FUNC_LPTIM1_IN1 0x3c02 -#define STM32H7_PD12_FUNC_TIM4_CH1 0x3c03 -#define STM32H7_PD12_FUNC_LPTIM2_IN1 0x3c04 -#define STM32H7_PD12_FUNC_I2C4_SCL 0x3c05 -#define STM32H7_PD12_FUNC_USART3_RTS 0x3c08 -#define STM32H7_PD12_FUNC_QUADSPI_BK1_IO1 0x3c0a -#define STM32H7_PD12_FUNC_SAI2_FS_A 0x3c0b -#define STM32H7_PD12_FUNC_FMC_A17 0x3c0d -#define STM32H7_PD12_FUNC_EVENTOUT 0x3c10 -#define STM32H7_PD12_FUNC_ANALOG 0x3c11 - -#define STM32H7_PD13_FUNC_GPIO 0x3d00 -#define STM32H7_PD13_FUNC_LPTIM1_OUT 0x3d02 -#define STM32H7_PD13_FUNC_TIM4_CH2 0x3d03 -#define STM32H7_PD13_FUNC_I2C4_SDA 0x3d05 -#define STM32H7_PD13_FUNC_QUADSPI_BK1_IO3 0x3d0a -#define STM32H7_PD13_FUNC_SAI2_SCK_A 0x3d0b -#define STM32H7_PD13_FUNC_FMC_A18 0x3d0d -#define STM32H7_PD13_FUNC_EVENTOUT 0x3d10 -#define STM32H7_PD13_FUNC_ANALOG 0x3d11 - -#define STM32H7_PD14_FUNC_GPIO 0x3e00 -#define STM32H7_PD14_FUNC_TIM4_CH3 0x3e03 -#define STM32H7_PD14_FUNC_SAI3_MCLK_B 0x3e07 -#define STM32H7_PD14_FUNC_UART8_CTS 0x3e09 -#define STM32H7_PD14_FUNC_FMC_D0_FMC_DA0 0x3e0d -#define STM32H7_PD14_FUNC_EVENTOUT 0x3e10 -#define STM32H7_PD14_FUNC_ANALOG 0x3e11 - -#define STM32H7_PD15_FUNC_GPIO 0x3f00 -#define STM32H7_PD15_FUNC_TIM4_CH4 0x3f03 -#define STM32H7_PD15_FUNC_SAI3_MCLK_A 0x3f07 -#define STM32H7_PD15_FUNC_UART8_RTS 0x3f09 -#define STM32H7_PD15_FUNC_FMC_D1_FMC_DA1 0x3f0d -#define STM32H7_PD15_FUNC_EVENTOUT 0x3f10 -#define STM32H7_PD15_FUNC_ANALOG 0x3f11 - -#define STM32H7_PE0_FUNC_GPIO 0x4000 -#define STM32H7_PE0_FUNC_LPTIM1_ETR 0x4002 -#define STM32H7_PE0_FUNC_TIM4_ETR 0x4003 -#define STM32H7_PE0_FUNC_HRTIM_SCIN 0x4004 -#define STM32H7_PE0_FUNC_LPTIM2_ETR 0x4005 -#define STM32H7_PE0_FUNC_UART8_RX 0x4009 -#define STM32H7_PE0_FUNC_CAN1_RXFD 0x400a -#define STM32H7_PE0_FUNC_SAI2_MCK_A 0x400b -#define STM32H7_PE0_FUNC_FMC_NBL0 0x400d -#define STM32H7_PE0_FUNC_DCMI_D2 0x400e -#define STM32H7_PE0_FUNC_EVENTOUT 0x4010 -#define STM32H7_PE0_FUNC_ANALOG 0x4011 - -#define STM32H7_PE1_FUNC_GPIO 0x4100 -#define STM32H7_PE1_FUNC_LPTIM1_IN2 0x4102 -#define STM32H7_PE1_FUNC_HRTIM_SCOUT 0x4104 -#define STM32H7_PE1_FUNC_UART8_TX 0x4109 -#define STM32H7_PE1_FUNC_CAN1_TXFD 0x410a -#define STM32H7_PE1_FUNC_FMC_NBL1 0x410d -#define STM32H7_PE1_FUNC_DCMI_D3 0x410e -#define STM32H7_PE1_FUNC_EVENTOUT 0x4110 -#define STM32H7_PE1_FUNC_ANALOG 0x4111 - -#define STM32H7_PE2_FUNC_GPIO 0x4200 -#define STM32H7_PE2_FUNC_TRACECLK 0x4201 -#define STM32H7_PE2_FUNC_SAI1_CK1 0x4203 -#define STM32H7_PE2_FUNC_SPI4_SCK 0x4206 -#define STM32H7_PE2_FUNC_SAI1_MCLK_A 0x4207 -#define STM32H7_PE2_FUNC_SAI4_MCLK_A 0x4209 -#define STM32H7_PE2_FUNC_QUADSPI_BK1_IO2 0x420a -#define STM32H7_PE2_FUNC_SAI4_CK1 0x420b -#define STM32H7_PE2_FUNC_ETH_MII_TXD3 0x420c -#define STM32H7_PE2_FUNC_FMC_A23 0x420d -#define STM32H7_PE2_FUNC_EVENTOUT 0x4210 -#define STM32H7_PE2_FUNC_ANALOG 0x4211 - -#define STM32H7_PE3_FUNC_GPIO 0x4300 -#define STM32H7_PE3_FUNC_TRACED0 0x4301 -#define STM32H7_PE3_FUNC_TIM15_BKIN 0x4305 -#define STM32H7_PE3_FUNC_SAI1_SD_B 0x4307 -#define STM32H7_PE3_FUNC_SAI4_SD_B 0x4309 -#define STM32H7_PE3_FUNC_FMC_A19 0x430d -#define STM32H7_PE3_FUNC_EVENTOUT 0x4310 -#define STM32H7_PE3_FUNC_ANALOG 0x4311 - -#define STM32H7_PE4_FUNC_GPIO 0x4400 -#define STM32H7_PE4_FUNC_TRACED1 0x4401 -#define STM32H7_PE4_FUNC_SAI1_D2 0x4403 -#define STM32H7_PE4_FUNC_DFSDM_DATIN3 0x4404 -#define STM32H7_PE4_FUNC_TIM15_CH1N 0x4405 -#define STM32H7_PE4_FUNC_SPI4_NSS 0x4406 -#define STM32H7_PE4_FUNC_SAI1_FS_A 0x4407 -#define STM32H7_PE4_FUNC_SAI4_FS_A 0x4409 -#define STM32H7_PE4_FUNC_SAI4_D2 0x440b -#define STM32H7_PE4_FUNC_FMC_A20 0x440d -#define STM32H7_PE4_FUNC_DCMI_D4 0x440e -#define STM32H7_PE4_FUNC_LCD_B0 0x440f -#define STM32H7_PE4_FUNC_EVENTOUT 0x4410 -#define STM32H7_PE4_FUNC_ANALOG 0x4411 - -#define STM32H7_PE5_FUNC_GPIO 0x4500 -#define STM32H7_PE5_FUNC_TRACED2 0x4501 -#define STM32H7_PE5_FUNC_SAI1_CK2 0x4503 -#define STM32H7_PE5_FUNC_DFSDM_CKIN3 0x4504 -#define STM32H7_PE5_FUNC_TIM15_CH1 0x4505 -#define STM32H7_PE5_FUNC_SPI4_MISO 0x4506 -#define STM32H7_PE5_FUNC_SAI1_SCK_A 0x4507 -#define STM32H7_PE5_FUNC_SAI4_SCK_A 0x4509 -#define STM32H7_PE5_FUNC_SAI4_CK2 0x450b -#define STM32H7_PE5_FUNC_FMC_A21 0x450d -#define STM32H7_PE5_FUNC_DCMI_D6 0x450e -#define STM32H7_PE5_FUNC_LCD_G0 0x450f -#define STM32H7_PE5_FUNC_EVENTOUT 0x4510 -#define STM32H7_PE5_FUNC_ANALOG 0x4511 - -#define STM32H7_PE6_FUNC_GPIO 0x4600 -#define STM32H7_PE6_FUNC_TRACED3 0x4601 -#define STM32H7_PE6_FUNC_TIM1_BKIN2 0x4602 -#define STM32H7_PE6_FUNC_SAI1_D1 0x4603 -#define STM32H7_PE6_FUNC_TIM15_CH2 0x4605 -#define STM32H7_PE6_FUNC_SPI4_MOSI 0x4606 -#define STM32H7_PE6_FUNC_SAI1_SD_A 0x4607 -#define STM32H7_PE6_FUNC_SAI4_SD_A 0x4609 -#define STM32H7_PE6_FUNC_SAI4_D1 0x460a -#define STM32H7_PE6_FUNC_SAI2_MCK_B 0x460b -#define STM32H7_PE6_FUNC_TIM1_BKIN2_COMP12 0x460c -#define STM32H7_PE6_FUNC_FMC_A22 0x460d -#define STM32H7_PE6_FUNC_DCMI_D7 0x460e -#define STM32H7_PE6_FUNC_LCD_G1 0x460f -#define STM32H7_PE6_FUNC_EVENTOUT 0x4610 -#define STM32H7_PE6_FUNC_ANALOG 0x4611 - -#define STM32H7_PE7_FUNC_GPIO 0x4700 -#define STM32H7_PE7_FUNC_TIM1_ETR 0x4702 -#define STM32H7_PE7_FUNC_DFSDM_DATIN2 0x4704 -#define STM32H7_PE7_FUNC_UART7_RX 0x4708 -#define STM32H7_PE7_FUNC_QUADSPI_BK2_IO0 0x470b -#define STM32H7_PE7_FUNC_FMC_D4_FMC_DA4 0x470d -#define STM32H7_PE7_FUNC_EVENTOUT 0x4710 -#define STM32H7_PE7_FUNC_ANALOG 0x4711 - -#define STM32H7_PE8_FUNC_GPIO 0x4800 -#define STM32H7_PE8_FUNC_TIM1_CH1N 0x4802 -#define STM32H7_PE8_FUNC_DFSDM_CKIN2 0x4804 -#define STM32H7_PE8_FUNC_UART7_TX 0x4808 -#define STM32H7_PE8_FUNC_QUADSPI_BK2_IO1 0x480b -#define STM32H7_PE8_FUNC_FMC_D5_FMC_DA5 0x480d -#define STM32H7_PE8_FUNC_COMP_2_OUT 0x480e -#define STM32H7_PE8_FUNC_EVENTOUT 0x4810 -#define STM32H7_PE8_FUNC_ANALOG 0x4811 - -#define STM32H7_PE9_FUNC_GPIO 0x4900 -#define STM32H7_PE9_FUNC_TIM1_CH1 0x4902 -#define STM32H7_PE9_FUNC_DFSDM_CKOUT 0x4904 -#define STM32H7_PE9_FUNC_UART7_RTS 0x4908 -#define STM32H7_PE9_FUNC_QUADSPI_BK2_IO2 0x490b -#define STM32H7_PE9_FUNC_FMC_D6_FMC_DA6 0x490d -#define STM32H7_PE9_FUNC_EVENTOUT 0x4910 -#define STM32H7_PE9_FUNC_ANALOG 0x4911 - -#define STM32H7_PE10_FUNC_GPIO 0x4a00 -#define STM32H7_PE10_FUNC_TIM1_CH2N 0x4a02 -#define STM32H7_PE10_FUNC_DFSDM_DATIN4 0x4a04 -#define STM32H7_PE10_FUNC_UART7_CTS 0x4a08 -#define STM32H7_PE10_FUNC_QUADSPI_BK2_IO3 0x4a0b -#define STM32H7_PE10_FUNC_FMC_D7_FMC_DA7 0x4a0d -#define STM32H7_PE10_FUNC_EVENTOUT 0x4a10 -#define STM32H7_PE10_FUNC_ANALOG 0x4a11 - -#define STM32H7_PE11_FUNC_GPIO 0x4b00 -#define STM32H7_PE11_FUNC_TIM1_CH2 0x4b02 -#define STM32H7_PE11_FUNC_DFSDM_CKIN4 0x4b04 -#define STM32H7_PE11_FUNC_SPI4_NSS 0x4b06 -#define STM32H7_PE11_FUNC_SAI2_SD_B 0x4b0b -#define STM32H7_PE11_FUNC_FMC_D8_FMC_DA8 0x4b0d -#define STM32H7_PE11_FUNC_LCD_G3 0x4b0f -#define STM32H7_PE11_FUNC_EVENTOUT 0x4b10 -#define STM32H7_PE11_FUNC_ANALOG 0x4b11 - -#define STM32H7_PE12_FUNC_GPIO 0x4c00 -#define STM32H7_PE12_FUNC_TIM1_CH3N 0x4c02 -#define STM32H7_PE12_FUNC_DFSDM_DATIN5 0x4c04 -#define STM32H7_PE12_FUNC_SPI4_SCK 0x4c06 -#define STM32H7_PE12_FUNC_SAI2_SCK_B 0x4c0b -#define STM32H7_PE12_FUNC_FMC_D9_FMC_DA9 0x4c0d -#define STM32H7_PE12_FUNC_COMP_1_OUT 0x4c0e -#define STM32H7_PE12_FUNC_LCD_B4 0x4c0f -#define STM32H7_PE12_FUNC_EVENTOUT 0x4c10 -#define STM32H7_PE12_FUNC_ANALOG 0x4c11 - -#define STM32H7_PE13_FUNC_GPIO 0x4d00 -#define STM32H7_PE13_FUNC_TIM1_CH3 0x4d02 -#define STM32H7_PE13_FUNC_DFSDM_CKIN5 0x4d04 -#define STM32H7_PE13_FUNC_SPI4_MISO 0x4d06 -#define STM32H7_PE13_FUNC_SAI2_FS_B 0x4d0b -#define STM32H7_PE13_FUNC_FMC_D10_FMC_DA10 0x4d0d -#define STM32H7_PE13_FUNC_COMP_2_OUT 0x4d0e -#define STM32H7_PE13_FUNC_LCD_DE 0x4d0f -#define STM32H7_PE13_FUNC_EVENTOUT 0x4d10 -#define STM32H7_PE13_FUNC_ANALOG 0x4d11 - -#define STM32H7_PE14_FUNC_GPIO 0x4e00 -#define STM32H7_PE14_FUNC_TIM1_CH4 0x4e02 -#define STM32H7_PE14_FUNC_SPI4_MOSI 0x4e06 -#define STM32H7_PE14_FUNC_SAI2_MCK_B 0x4e0b -#define STM32H7_PE14_FUNC_FMC_D11_FMC_DA11 0x4e0d -#define STM32H7_PE14_FUNC_LCD_CLK 0x4e0f -#define STM32H7_PE14_FUNC_EVENTOUT 0x4e10 -#define STM32H7_PE14_FUNC_ANALOG 0x4e11 - -#define STM32H7_PE15_FUNC_GPIO 0x4f00 -#define STM32H7_PE15_FUNC_TIM1_BKIN 0x4f02 -#define STM32H7_PE15_FUNC_HDMI__TIM1_BKIN 0x4f06 -#define STM32H7_PE15_FUNC_FMC_D12_FMC_DA12 0x4f0d -#define STM32H7_PE15_FUNC_TIM1_BKIN_COMP12 0x4f0e -#define STM32H7_PE15_FUNC_LCD_R7 0x4f0f -#define STM32H7_PE15_FUNC_EVENTOUT 0x4f10 -#define STM32H7_PE15_FUNC_ANALOG 0x4f11 - -#define STM32H7_PF0_FUNC_GPIO 0x5000 -#define STM32H7_PF0_FUNC_I2C2_SDA 0x5005 -#define STM32H7_PF0_FUNC_FMC_A0 0x500d -#define STM32H7_PF0_FUNC_EVENTOUT 0x5010 -#define STM32H7_PF0_FUNC_ANALOG 0x5011 - -#define STM32H7_PF1_FUNC_GPIO 0x5100 -#define STM32H7_PF1_FUNC_I2C2_SCL 0x5105 -#define STM32H7_PF1_FUNC_FMC_A1 0x510d -#define STM32H7_PF1_FUNC_EVENTOUT 0x5110 -#define STM32H7_PF1_FUNC_ANALOG 0x5111 - -#define STM32H7_PF2_FUNC_GPIO 0x5200 -#define STM32H7_PF2_FUNC_I2C2_SMBA 0x5205 -#define STM32H7_PF2_FUNC_FMC_A2 0x520d -#define STM32H7_PF2_FUNC_EVENTOUT 0x5210 -#define STM32H7_PF2_FUNC_ANALOG 0x5211 - -#define STM32H7_PF3_FUNC_GPIO 0x5300 -#define STM32H7_PF3_FUNC_FMC_A3 0x530d -#define STM32H7_PF3_FUNC_EVENTOUT 0x5310 -#define STM32H7_PF3_FUNC_ANALOG 0x5311 - -#define STM32H7_PF4_FUNC_GPIO 0x5400 -#define STM32H7_PF4_FUNC_FMC_A4 0x540d -#define STM32H7_PF4_FUNC_EVENTOUT 0x5410 -#define STM32H7_PF4_FUNC_ANALOG 0x5411 - -#define STM32H7_PF5_FUNC_GPIO 0x5500 -#define STM32H7_PF5_FUNC_FMC_A5 0x550d -#define STM32H7_PF5_FUNC_EVENTOUT 0x5510 -#define STM32H7_PF5_FUNC_ANALOG 0x5511 - -#define STM32H7_PF6_FUNC_GPIO 0x5600 -#define STM32H7_PF6_FUNC_TIM16_CH1 0x5602 -#define STM32H7_PF6_FUNC_SPI5_NSS 0x5606 -#define STM32H7_PF6_FUNC_SAI1_SD_B 0x5607 -#define STM32H7_PF6_FUNC_UART7_RX 0x5608 -#define STM32H7_PF6_FUNC_SAI4_SD_B 0x5609 -#define STM32H7_PF6_FUNC_QUADSPI_BK1_IO3 0x560a -#define STM32H7_PF6_FUNC_EVENTOUT 0x5610 -#define STM32H7_PF6_FUNC_ANALOG 0x5611 - -#define STM32H7_PF7_FUNC_GPIO 0x5700 -#define STM32H7_PF7_FUNC_TIM17_CH1 0x5702 -#define STM32H7_PF7_FUNC_SPI5_SCK 0x5706 -#define STM32H7_PF7_FUNC_SAI1_MCLK_B 0x5707 -#define STM32H7_PF7_FUNC_UART7_TX 0x5708 -#define STM32H7_PF7_FUNC_SAI4_MCLK_B 0x5709 -#define STM32H7_PF7_FUNC_QUADSPI_BK1_IO2 0x570a -#define STM32H7_PF7_FUNC_EVENTOUT 0x5710 -#define STM32H7_PF7_FUNC_ANALOG 0x5711 - -#define STM32H7_PF8_FUNC_GPIO 0x5800 -#define STM32H7_PF8_FUNC_TIM16_CH1N 0x5802 -#define STM32H7_PF8_FUNC_SPI5_MISO 0x5806 -#define STM32H7_PF8_FUNC_SAI1_SCK_B 0x5807 -#define STM32H7_PF8_FUNC_UART7_RTS 0x5808 -#define STM32H7_PF8_FUNC_SAI4_SCK_B 0x5809 -#define STM32H7_PF8_FUNC_TIM13_CH1 0x580a -#define STM32H7_PF8_FUNC_QUADSPI_BK1_IO0 0x580b -#define STM32H7_PF8_FUNC_EVENTOUT 0x5810 -#define STM32H7_PF8_FUNC_ANALOG 0x5811 - -#define STM32H7_PF9_FUNC_GPIO 0x5900 -#define STM32H7_PF9_FUNC_TIM17_CH1N 0x5902 -#define STM32H7_PF9_FUNC_SPI5_MOSI 0x5906 -#define STM32H7_PF9_FUNC_SAI1_FS_B 0x5907 -#define STM32H7_PF9_FUNC_UART7_CTS 0x5908 -#define STM32H7_PF9_FUNC_SAI4_FS_B 0x5909 -#define STM32H7_PF9_FUNC_TIM14_CH1 0x590a -#define STM32H7_PF9_FUNC_QUADSPI_BK1_IO1 0x590b -#define STM32H7_PF9_FUNC_EVENTOUT 0x5910 -#define STM32H7_PF9_FUNC_ANALOG 0x5911 - -#define STM32H7_PF10_FUNC_GPIO 0x5a00 -#define STM32H7_PF10_FUNC_TIM16_BKIN 0x5a02 -#define STM32H7_PF10_FUNC_SAI1_D3 0x5a03 -#define STM32H7_PF10_FUNC_QUADSPI_CLK 0x5a0a -#define STM32H7_PF10_FUNC_SAI4_D3 0x5a0b -#define STM32H7_PF10_FUNC_DCMI_D11 0x5a0e -#define STM32H7_PF10_FUNC_LCD_DE 0x5a0f -#define STM32H7_PF10_FUNC_EVENTOUT 0x5a10 -#define STM32H7_PF10_FUNC_ANALOG 0x5a11 - -#define STM32H7_PF11_FUNC_GPIO 0x5b00 -#define STM32H7_PF11_FUNC_SPI5_MOSI 0x5b06 -#define STM32H7_PF11_FUNC_SAI2_SD_B 0x5b0b -#define STM32H7_PF11_FUNC_FMC_SDNRAS 0x5b0d -#define STM32H7_PF11_FUNC_DCMI_D12 0x5b0e -#define STM32H7_PF11_FUNC_EVENTOUT 0x5b10 -#define STM32H7_PF11_FUNC_ANALOG 0x5b11 - -#define STM32H7_PF12_FUNC_GPIO 0x5c00 -#define STM32H7_PF12_FUNC_FMC_A6 0x5c0d -#define STM32H7_PF12_FUNC_EVENTOUT 0x5c10 -#define STM32H7_PF12_FUNC_ANALOG 0x5c11 - -#define STM32H7_PF13_FUNC_GPIO 0x5d00 -#define STM32H7_PF13_FUNC_DFSDM_DATIN6 0x5d04 -#define STM32H7_PF13_FUNC_I2C4_SMBA 0x5d05 -#define STM32H7_PF13_FUNC_FMC_A7 0x5d0d -#define STM32H7_PF13_FUNC_EVENTOUT 0x5d10 -#define STM32H7_PF13_FUNC_ANALOG 0x5d11 - -#define STM32H7_PF14_FUNC_GPIO 0x5e00 -#define STM32H7_PF14_FUNC_DFSDM_CKIN6 0x5e04 -#define STM32H7_PF14_FUNC_I2C4_SCL 0x5e05 -#define STM32H7_PF14_FUNC_FMC_A8 0x5e0d -#define STM32H7_PF14_FUNC_EVENTOUT 0x5e10 -#define STM32H7_PF14_FUNC_ANALOG 0x5e11 - -#define STM32H7_PF15_FUNC_GPIO 0x5f00 -#define STM32H7_PF15_FUNC_I2C4_SDA 0x5f05 -#define STM32H7_PF15_FUNC_FMC_A9 0x5f0d -#define STM32H7_PF15_FUNC_EVENTOUT 0x5f10 -#define STM32H7_PF15_FUNC_ANALOG 0x5f11 - -#define STM32H7_PG0_FUNC_GPIO 0x6000 -#define STM32H7_PG0_FUNC_FMC_A10 0x600d -#define STM32H7_PG0_FUNC_EVENTOUT 0x6010 -#define STM32H7_PG0_FUNC_ANALOG 0x6011 - -#define STM32H7_PG1_FUNC_GPIO 0x6100 -#define STM32H7_PG1_FUNC_FMC_A11 0x610d -#define STM32H7_PG1_FUNC_EVENTOUT 0x6110 -#define STM32H7_PG1_FUNC_ANALOG 0x6111 - -#define STM32H7_PG2_FUNC_GPIO 0x6200 -#define STM32H7_PG2_FUNC_TIM8_BKIN 0x6204 -#define STM32H7_PG2_FUNC_TIM8_BKIN_COMP12 0x620c -#define STM32H7_PG2_FUNC_FMC_A12 0x620d -#define STM32H7_PG2_FUNC_EVENTOUT 0x6210 -#define STM32H7_PG2_FUNC_ANALOG 0x6211 - -#define STM32H7_PG3_FUNC_GPIO 0x6300 -#define STM32H7_PG3_FUNC_TIM8_BKIN2 0x6304 -#define STM32H7_PG3_FUNC_TIM8_BKIN2_COMP12 0x630c -#define STM32H7_PG3_FUNC_FMC_A13 0x630d -#define STM32H7_PG3_FUNC_EVENTOUT 0x6310 -#define STM32H7_PG3_FUNC_ANALOG 0x6311 - -#define STM32H7_PG4_FUNC_GPIO 0x6400 -#define STM32H7_PG4_FUNC_TIM1_BKIN2 0x6402 -#define STM32H7_PG4_FUNC_TIM1_BKIN2_COMP12 0x640c -#define STM32H7_PG4_FUNC_FMC_A14_FMC_BA0 0x640d -#define STM32H7_PG4_FUNC_EVENTOUT 0x6410 -#define STM32H7_PG4_FUNC_ANALOG 0x6411 - -#define STM32H7_PG5_FUNC_GPIO 0x6500 -#define STM32H7_PG5_FUNC_TIM1_ETR 0x6502 -#define STM32H7_PG5_FUNC_FMC_A15_FMC_BA1 0x650d -#define STM32H7_PG5_FUNC_EVENTOUT 0x6510 -#define STM32H7_PG5_FUNC_ANALOG 0x6511 - -#define STM32H7_PG6_FUNC_GPIO 0x6600 -#define STM32H7_PG6_FUNC_TIM17_BKIN 0x6602 -#define STM32H7_PG6_FUNC_HRTIM_CHE1 0x6603 -#define STM32H7_PG6_FUNC_QUADSPI_BK1_NCS 0x660b -#define STM32H7_PG6_FUNC_FMC_NE3 0x660d -#define STM32H7_PG6_FUNC_DCMI_D12 0x660e -#define STM32H7_PG6_FUNC_LCD_R7 0x660f -#define STM32H7_PG6_FUNC_EVENTOUT 0x6610 -#define STM32H7_PG6_FUNC_ANALOG 0x6611 - -#define STM32H7_PG7_FUNC_GPIO 0x6700 -#define STM32H7_PG7_FUNC_HRTIM_CHE2 0x6703 -#define STM32H7_PG7_FUNC_SAI1_MCLK_A 0x6707 -#define STM32H7_PG7_FUNC_USART6_CK 0x6708 -#define STM32H7_PG7_FUNC_FMC_INT 0x670d -#define STM32H7_PG7_FUNC_DCMI_D13 0x670e -#define STM32H7_PG7_FUNC_LCD_CLK 0x670f -#define STM32H7_PG7_FUNC_EVENTOUT 0x6710 -#define STM32H7_PG7_FUNC_ANALOG 0x6711 - -#define STM32H7_PG8_FUNC_GPIO 0x6800 -#define STM32H7_PG8_FUNC_TIM8_ETR 0x6804 -#define STM32H7_PG8_FUNC_SPI6_NSS 0x6806 -#define STM32H7_PG8_FUNC_USART6_RTS 0x6808 -#define STM32H7_PG8_FUNC_SPDIFRX_IN2 0x6809 -#define STM32H7_PG8_FUNC_ETH_PPS_OUT 0x680c -#define STM32H7_PG8_FUNC_FMC_SDCLK 0x680d -#define STM32H7_PG8_FUNC_LCD_G7 0x680f -#define STM32H7_PG8_FUNC_EVENTOUT 0x6810 -#define STM32H7_PG8_FUNC_ANALOG 0x6811 - -#define STM32H7_PG9_FUNC_GPIO 0x6900 -#define STM32H7_PG9_FUNC_SPI1_MISO_I2S1_SDI 0x6906 -#define STM32H7_PG9_FUNC_USART6_RX 0x6908 -#define STM32H7_PG9_FUNC_SPDIFRX_IN3 0x6909 -#define STM32H7_PG9_FUNC_QUADSPI_BK2_IO2 0x690a -#define STM32H7_PG9_FUNC_SAI2_FS_B 0x690b -#define STM32H7_PG9_FUNC_FMC_NE2_FMC_NCE 0x690d -#define STM32H7_PG9_FUNC_DCMI_VSYNC 0x690e -#define STM32H7_PG9_FUNC_EVENTOUT 0x6910 -#define STM32H7_PG9_FUNC_ANALOG 0x6911 - -#define STM32H7_PG10_FUNC_GPIO 0x6a00 -#define STM32H7_PG10_FUNC_HRTIM_FLT5 0x6a03 -#define STM32H7_PG10_FUNC_SPI1_NSS_I2S1_WS 0x6a06 -#define STM32H7_PG10_FUNC_LCD_G3 0x6a0a -#define STM32H7_PG10_FUNC_SAI2_SD_B 0x6a0b -#define STM32H7_PG10_FUNC_FMC_NE3 0x6a0d -#define STM32H7_PG10_FUNC_DCMI_D2 0x6a0e -#define STM32H7_PG10_FUNC_LCD_B2 0x6a0f -#define STM32H7_PG10_FUNC_EVENTOUT 0x6a10 -#define STM32H7_PG10_FUNC_ANALOG 0x6a11 - -#define STM32H7_PG11_FUNC_GPIO 0x6b00 -#define STM32H7_PG11_FUNC_HRTIM_EEV4 0x6b03 -#define STM32H7_PG11_FUNC_SPI1_SCK_I2S1_CK 0x6b06 -#define STM32H7_PG11_FUNC_SPDIFRX_IN0 0x6b09 -#define STM32H7_PG11_FUNC_SDMMC2_D2 0x6b0b -#define STM32H7_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN 0x6b0c -#define STM32H7_PG11_FUNC_DCMI_D3 0x6b0e -#define STM32H7_PG11_FUNC_LCD_B3 0x6b0f -#define STM32H7_PG11_FUNC_EVENTOUT 0x6b10 -#define STM32H7_PG11_FUNC_ANALOG 0x6b11 - -#define STM32H7_PG12_FUNC_GPIO 0x6c00 -#define STM32H7_PG12_FUNC_LPTIM1_IN1 0x6c02 -#define STM32H7_PG12_FUNC_HRTIM_EEV5 0x6c03 -#define STM32H7_PG12_FUNC_SPI6_MISO 0x6c06 -#define STM32H7_PG12_FUNC_USART6_RTS 0x6c08 -#define STM32H7_PG12_FUNC_SPDIFRX_IN1 0x6c09 -#define STM32H7_PG12_FUNC_LCD_B4 0x6c0a -#define STM32H7_PG12_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1 0x6c0c -#define STM32H7_PG12_FUNC_FMC_NE4 0x6c0d -#define STM32H7_PG12_FUNC_LCD_B1 0x6c0f -#define STM32H7_PG12_FUNC_EVENTOUT 0x6c10 -#define STM32H7_PG12_FUNC_ANALOG 0x6c11 - -#define STM32H7_PG13_FUNC_GPIO 0x6d00 -#define STM32H7_PG13_FUNC_TRACED0 0x6d01 -#define STM32H7_PG13_FUNC_LPTIM1_OUT 0x6d02 -#define STM32H7_PG13_FUNC_HRTIM_EEV10 0x6d03 -#define STM32H7_PG13_FUNC_SPI6_SCK 0x6d06 -#define STM32H7_PG13_FUNC_USART6_CTS_NSS 0x6d08 -#define STM32H7_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0 0x6d0c -#define STM32H7_PG13_FUNC_FMC_A24 0x6d0d -#define STM32H7_PG13_FUNC_LCD_R0 0x6d0f -#define STM32H7_PG13_FUNC_EVENTOUT 0x6d10 -#define STM32H7_PG13_FUNC_ANALOG 0x6d11 - -#define STM32H7_PG14_FUNC_GPIO 0x6e00 -#define STM32H7_PG14_FUNC_TRACED1 0x6e01 -#define STM32H7_PG14_FUNC_LPTIM1_ETR 0x6e02 -#define STM32H7_PG14_FUNC_SPI6_MOSI 0x6e06 -#define STM32H7_PG14_FUNC_USART6_TX 0x6e08 -#define STM32H7_PG14_FUNC_QUADSPI_BK2_IO3 0x6e0a -#define STM32H7_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1 0x6e0c -#define STM32H7_PG14_FUNC_FMC_A25 0x6e0d -#define STM32H7_PG14_FUNC_LCD_B0 0x6e0f -#define STM32H7_PG14_FUNC_EVENTOUT 0x6e10 -#define STM32H7_PG14_FUNC_ANALOG 0x6e11 - -#define STM32H7_PG15_FUNC_GPIO 0x6f00 -#define STM32H7_PG15_FUNC_USART6_CTS_NSS 0x6f08 -#define STM32H7_PG15_FUNC_FMC_SDNCAS 0x6f0d -#define STM32H7_PG15_FUNC_DCMI_D13 0x6f0e -#define STM32H7_PG15_FUNC_EVENTOUT 0x6f10 -#define STM32H7_PG15_FUNC_ANALOG 0x6f11 - -#define STM32H7_PH0_FUNC_GPIO 0x7000 -#define STM32H7_PH0_FUNC_EVENTOUT 0x7010 -#define STM32H7_PH0_FUNC_ANALOG 0x7011 - -#define STM32H7_PH1_FUNC_GPIO 0x7100 -#define STM32H7_PH1_FUNC_EVENTOUT 0x7110 -#define STM32H7_PH1_FUNC_ANALOG 0x7111 - -#define STM32H7_PH2_FUNC_GPIO 0x7200 -#define STM32H7_PH2_FUNC_LPTIM1_IN2 0x7202 -#define STM32H7_PH2_FUNC_QUADSPI_BK2_IO0 0x720a -#define STM32H7_PH2_FUNC_SAI2_SCK_B 0x720b -#define STM32H7_PH2_FUNC_ETH_MII_CRS 0x720c -#define STM32H7_PH2_FUNC_FMC_SDCKE0 0x720d -#define STM32H7_PH2_FUNC_LCD_R0 0x720f -#define STM32H7_PH2_FUNC_EVENTOUT 0x7210 -#define STM32H7_PH2_FUNC_ANALOG 0x7211 - -#define STM32H7_PH3_FUNC_GPIO 0x7300 -#define STM32H7_PH3_FUNC_QUADSPI_BK2_IO1 0x730a -#define STM32H7_PH3_FUNC_SAI2_MCK_B 0x730b -#define STM32H7_PH3_FUNC_ETH_MII_COL 0x730c -#define STM32H7_PH3_FUNC_FMC_SDNE0 0x730d -#define STM32H7_PH3_FUNC_LCD_R1 0x730f -#define STM32H7_PH3_FUNC_EVENTOUT 0x7310 -#define STM32H7_PH3_FUNC_ANALOG 0x7311 - -#define STM32H7_PH4_FUNC_GPIO 0x7400 -#define STM32H7_PH4_FUNC_I2C2_SCL 0x7405 -#define STM32H7_PH4_FUNC_LCD_G5 0x740a -#define STM32H7_PH4_FUNC_OTG_HS_ULPI_NXT 0x740b -#define STM32H7_PH4_FUNC_LCD_G4 0x740f -#define STM32H7_PH4_FUNC_EVENTOUT 0x7410 -#define STM32H7_PH4_FUNC_ANALOG 0x7411 - -#define STM32H7_PH5_FUNC_GPIO 0x7500 -#define STM32H7_PH5_FUNC_I2C2_SDA 0x7505 -#define STM32H7_PH5_FUNC_SPI5_NSS 0x7506 -#define STM32H7_PH5_FUNC_FMC_SDNWE 0x750d -#define STM32H7_PH5_FUNC_EVENTOUT 0x7510 -#define STM32H7_PH5_FUNC_ANALOG 0x7511 - -#define STM32H7_PH6_FUNC_GPIO 0x7600 -#define STM32H7_PH6_FUNC_I2C2_SMBA 0x7605 -#define STM32H7_PH6_FUNC_SPI5_SCK 0x7606 -#define STM32H7_PH6_FUNC_ETH_MII_RXD2 0x760c -#define STM32H7_PH6_FUNC_FMC_SDNE1 0x760d -#define STM32H7_PH6_FUNC_DCMI_D8 0x760e -#define STM32H7_PH6_FUNC_EVENTOUT 0x7610 -#define STM32H7_PH6_FUNC_ANALOG 0x7611 - -#define STM32H7_PH7_FUNC_GPIO 0x7700 -#define STM32H7_PH7_FUNC_I2C3_SCL 0x7705 -#define STM32H7_PH7_FUNC_SPI5_MISO 0x7706 -#define STM32H7_PH7_FUNC_ETH_MII_RXD3 0x770c -#define STM32H7_PH7_FUNC_FMC_SDCKE1 0x770d -#define STM32H7_PH7_FUNC_DCMI_D9 0x770e -#define STM32H7_PH7_FUNC_EVENTOUT 0x7710 -#define STM32H7_PH7_FUNC_ANALOG 0x7711 - -#define STM32H7_PH8_FUNC_GPIO 0x7800 -#define STM32H7_PH8_FUNC_TIM5_ETR 0x7803 -#define STM32H7_PH8_FUNC_I2C3_SDA 0x7805 -#define STM32H7_PH8_FUNC_FMC_D16 0x780d -#define STM32H7_PH8_FUNC_DCMI_HSYNC 0x780e -#define STM32H7_PH8_FUNC_LCD_R2 0x780f -#define STM32H7_PH8_FUNC_EVENTOUT 0x7810 -#define STM32H7_PH8_FUNC_ANALOG 0x7811 - -#define STM32H7_PH9_FUNC_GPIO 0x7900 -#define STM32H7_PH9_FUNC_I2C3_SMBA 0x7905 -#define STM32H7_PH9_FUNC_FMC_D17 0x790d -#define STM32H7_PH9_FUNC_DCMI_D0 0x790e -#define STM32H7_PH9_FUNC_LCD_R3 0x790f -#define STM32H7_PH9_FUNC_EVENTOUT 0x7910 -#define STM32H7_PH9_FUNC_ANALOG 0x7911 - -#define STM32H7_PH10_FUNC_GPIO 0x7a00 -#define STM32H7_PH10_FUNC_TIM5_CH1 0x7a03 -#define STM32H7_PH10_FUNC_I2C4_SMBA 0x7a05 -#define STM32H7_PH10_FUNC_FMC_D18 0x7a0d -#define STM32H7_PH10_FUNC_DCMI_D1 0x7a0e -#define STM32H7_PH10_FUNC_LCD_R4 0x7a0f -#define STM32H7_PH10_FUNC_EVENTOUT 0x7a10 -#define STM32H7_PH10_FUNC_ANALOG 0x7a11 - -#define STM32H7_PH11_FUNC_GPIO 0x7b00 -#define STM32H7_PH11_FUNC_TIM5_CH2 0x7b03 -#define STM32H7_PH11_FUNC_I2C4_SCL 0x7b05 -#define STM32H7_PH11_FUNC_FMC_D19 0x7b0d -#define STM32H7_PH11_FUNC_DCMI_D2 0x7b0e -#define STM32H7_PH11_FUNC_LCD_R5 0x7b0f -#define STM32H7_PH11_FUNC_EVENTOUT 0x7b10 -#define STM32H7_PH11_FUNC_ANALOG 0x7b11 - -#define STM32H7_PH12_FUNC_GPIO 0x7c00 -#define STM32H7_PH12_FUNC_TIM5_CH3 0x7c03 -#define STM32H7_PH12_FUNC_I2C4_SDA 0x7c05 -#define STM32H7_PH12_FUNC_FMC_D20 0x7c0d -#define STM32H7_PH12_FUNC_DCMI_D3 0x7c0e -#define STM32H7_PH12_FUNC_LCD_R6 0x7c0f -#define STM32H7_PH12_FUNC_EVENTOUT 0x7c10 -#define STM32H7_PH12_FUNC_ANALOG 0x7c11 - -#define STM32H7_PH13_FUNC_GPIO 0x7d00 -#define STM32H7_PH13_FUNC_TIM8_CH1N 0x7d04 -#define STM32H7_PH13_FUNC_UART4_TX 0x7d09 -#define STM32H7_PH13_FUNC_CAN1_TX 0x7d0a -#define STM32H7_PH13_FUNC_FMC_D21 0x7d0d -#define STM32H7_PH13_FUNC_LCD_G2 0x7d0f -#define STM32H7_PH13_FUNC_EVENTOUT 0x7d10 -#define STM32H7_PH13_FUNC_ANALOG 0x7d11 - -#define STM32H7_PH14_FUNC_GPIO 0x7e00 -#define STM32H7_PH14_FUNC_TIM8_CH2N 0x7e04 -#define STM32H7_PH14_FUNC_UART4_RX 0x7e09 -#define STM32H7_PH14_FUNC_CAN1_RX 0x7e0a -#define STM32H7_PH14_FUNC_FMC_D22 0x7e0d -#define STM32H7_PH14_FUNC_DCMI_D4 0x7e0e -#define STM32H7_PH14_FUNC_LCD_G3 0x7e0f -#define STM32H7_PH14_FUNC_EVENTOUT 0x7e10 -#define STM32H7_PH14_FUNC_ANALOG 0x7e11 - -#define STM32H7_PH15_FUNC_GPIO 0x7f00 -#define STM32H7_PH15_FUNC_TIM8_CH3N 0x7f04 -#define STM32H7_PH15_FUNC_CAN1_TXFD 0x7f0a -#define STM32H7_PH15_FUNC_FMC_D23 0x7f0d -#define STM32H7_PH15_FUNC_DCMI_D11 0x7f0e -#define STM32H7_PH15_FUNC_LCD_G4 0x7f0f -#define STM32H7_PH15_FUNC_EVENTOUT 0x7f10 -#define STM32H7_PH15_FUNC_ANALOG 0x7f11 - -#define STM32H7_PI0_FUNC_GPIO 0x8000 -#define STM32H7_PI0_FUNC_TIM5_CH4 0x8003 -#define STM32H7_PI0_FUNC_SPI2_NSS_I2S2_WS 0x8006 -#define STM32H7_PI0_FUNC_CAN1_RXFD 0x800a -#define STM32H7_PI0_FUNC_FMC_D24 0x800d -#define STM32H7_PI0_FUNC_DCMI_D13 0x800e -#define STM32H7_PI0_FUNC_LCD_G5 0x800f -#define STM32H7_PI0_FUNC_EVENTOUT 0x8010 -#define STM32H7_PI0_FUNC_ANALOG 0x8011 - -#define STM32H7_PI1_FUNC_GPIO 0x8100 -#define STM32H7_PI1_FUNC_TIM8_BKIN2 0x8104 -#define STM32H7_PI1_FUNC_SPI2_SCK_I2S2_CK 0x8106 -#define STM32H7_PI1_FUNC_TIM8_BKIN2_COMP12 0x810c -#define STM32H7_PI1_FUNC_FMC_D25 0x810d -#define STM32H7_PI1_FUNC_DCMI_D8 0x810e -#define STM32H7_PI1_FUNC_LCD_G6 0x810f -#define STM32H7_PI1_FUNC_EVENTOUT 0x8110 -#define STM32H7_PI1_FUNC_ANALOG 0x8111 - -#define STM32H7_PI2_FUNC_GPIO 0x8200 -#define STM32H7_PI2_FUNC_TIM8_CH4 0x8204 -#define STM32H7_PI2_FUNC_SPI2_MISO_I2S2_SDI 0x8206 -#define STM32H7_PI2_FUNC_FMC_D26 0x820d -#define STM32H7_PI2_FUNC_DCMI_D9 0x820e -#define STM32H7_PI2_FUNC_LCD_G7 0x820f -#define STM32H7_PI2_FUNC_EVENTOUT 0x8210 -#define STM32H7_PI2_FUNC_ANALOG 0x8211 - -#define STM32H7_PI3_FUNC_GPIO 0x8300 -#define STM32H7_PI3_FUNC_TIM8_ETR 0x8304 -#define STM32H7_PI3_FUNC_SPI2_MOSI_I2S2_SDO 0x8306 -#define STM32H7_PI3_FUNC_FMC_D27 0x830d -#define STM32H7_PI3_FUNC_DCMI_D10 0x830e -#define STM32H7_PI3_FUNC_EVENTOUT 0x8310 -#define STM32H7_PI3_FUNC_ANALOG 0x8311 - -#define STM32H7_PI4_FUNC_GPIO 0x8400 -#define STM32H7_PI4_FUNC_TIM8_BKIN 0x8404 -#define STM32H7_PI4_FUNC_SAI2_MCK_A 0x840b -#define STM32H7_PI4_FUNC_TIM8_BKIN_COMP12 0x840c -#define STM32H7_PI4_FUNC_FMC_NBL2 0x840d -#define STM32H7_PI4_FUNC_DCMI_D5 0x840e -#define STM32H7_PI4_FUNC_LCD_B4 0x840f -#define STM32H7_PI4_FUNC_EVENTOUT 0x8410 -#define STM32H7_PI4_FUNC_ANALOG 0x8411 - -#define STM32H7_PI5_FUNC_GPIO 0x8500 -#define STM32H7_PI5_FUNC_TIM8_CH1 0x8504 -#define STM32H7_PI5_FUNC_SAI2_SCK_A 0x850b -#define STM32H7_PI5_FUNC_FMC_NBL3 0x850d -#define STM32H7_PI5_FUNC_DCMI_VSYNC 0x850e -#define STM32H7_PI5_FUNC_LCD_B5 0x850f -#define STM32H7_PI5_FUNC_EVENTOUT 0x8510 -#define STM32H7_PI5_FUNC_ANALOG 0x8511 - -#define STM32H7_PI6_FUNC_GPIO 0x8600 -#define STM32H7_PI6_FUNC_TIM8_CH2 0x8604 -#define STM32H7_PI6_FUNC_SAI2_SD_A 0x860b -#define STM32H7_PI6_FUNC_FMC_D28 0x860d -#define STM32H7_PI6_FUNC_DCMI_D6 0x860e -#define STM32H7_PI6_FUNC_LCD_B6 0x860f -#define STM32H7_PI6_FUNC_EVENTOUT 0x8610 -#define STM32H7_PI6_FUNC_ANALOG 0x8611 - -#define STM32H7_PI7_FUNC_GPIO 0x8700 -#define STM32H7_PI7_FUNC_TIM8_CH3 0x8704 -#define STM32H7_PI7_FUNC_SAI2_FS_A 0x870b -#define STM32H7_PI7_FUNC_FMC_D29 0x870d -#define STM32H7_PI7_FUNC_DCMI_D7 0x870e -#define STM32H7_PI7_FUNC_LCD_B7 0x870f -#define STM32H7_PI7_FUNC_EVENTOUT 0x8710 -#define STM32H7_PI7_FUNC_ANALOG 0x8711 - -#define STM32H7_PI8_FUNC_GPIO 0x8800 -#define STM32H7_PI8_FUNC_EVENTOUT 0x8810 -#define STM32H7_PI8_FUNC_ANALOG 0x8811 - -#define STM32H7_PI9_FUNC_GPIO 0x8900 -#define STM32H7_PI9_FUNC_UART4_RX 0x8909 -#define STM32H7_PI9_FUNC_CAN1_RX 0x890a -#define STM32H7_PI9_FUNC_FMC_D30 0x890d -#define STM32H7_PI9_FUNC_LCD_VSYNC 0x890f -#define STM32H7_PI9_FUNC_EVENTOUT 0x8910 -#define STM32H7_PI9_FUNC_ANALOG 0x8911 - -#define STM32H7_PI10_FUNC_GPIO 0x8a00 -#define STM32H7_PI10_FUNC_CAN1_RXFD 0x8a0a -#define STM32H7_PI10_FUNC_ETH_MII_RX_ER 0x8a0c -#define STM32H7_PI10_FUNC_FMC_D31 0x8a0d -#define STM32H7_PI10_FUNC_LCD_HSYNC 0x8a0f -#define STM32H7_PI10_FUNC_EVENTOUT 0x8a10 -#define STM32H7_PI10_FUNC_ANALOG 0x8a11 - -#define STM32H7_PI11_FUNC_GPIO 0x8b00 -#define STM32H7_PI11_FUNC_LCD_G6 0x8b0a -#define STM32H7_PI11_FUNC_OTG_HS_ULPI_DIR 0x8b0b -#define STM32H7_PI11_FUNC_EVENTOUT 0x8b10 -#define STM32H7_PI11_FUNC_ANALOG 0x8b11 - -#define STM32H7_PI12_FUNC_GPIO 0x8c00 -#define STM32H7_PI12_FUNC_ETH_TX_ER 0x8c0c -#define STM32H7_PI12_FUNC_LCD_HSYNC 0x8c0f -#define STM32H7_PI12_FUNC_EVENTOUT 0x8c10 -#define STM32H7_PI12_FUNC_ANALOG 0x8c11 - -#define STM32H7_PI13_FUNC_GPIO 0x8d00 -#define STM32H7_PI13_FUNC_LCD_VSYNC 0x8d0f -#define STM32H7_PI13_FUNC_EVENTOUT 0x8d10 -#define STM32H7_PI13_FUNC_ANALOG 0x8d11 - -#define STM32H7_PI14_FUNC_GPIO 0x8e00 -#define STM32H7_PI14_FUNC_LCD_CLK 0x8e0f -#define STM32H7_PI14_FUNC_EVENTOUT 0x8e10 -#define STM32H7_PI14_FUNC_ANALOG 0x8e11 - -#define STM32H7_PI15_FUNC_GPIO 0x8f00 -#define STM32H7_PI15_FUNC_LCD_G2 0x8f0a -#define STM32H7_PI15_FUNC_LCD_R0 0x8f0f -#define STM32H7_PI15_FUNC_EVENTOUT 0x8f10 -#define STM32H7_PI15_FUNC_ANALOG 0x8f11 - -#define STM32H7_PJ0_FUNC_GPIO 0x9000 -#define STM32H7_PJ0_FUNC_LCD_R7 0x900a -#define STM32H7_PJ0_FUNC_LCD_R1 0x900f -#define STM32H7_PJ0_FUNC_EVENTOUT 0x9010 -#define STM32H7_PJ0_FUNC_ANALOG 0x9011 - -#define STM32H7_PJ1_FUNC_GPIO 0x9100 -#define STM32H7_PJ1_FUNC_LCD_R2 0x910f -#define STM32H7_PJ1_FUNC_EVENTOUT 0x9110 -#define STM32H7_PJ1_FUNC_ANALOG 0x9111 - -#define STM32H7_PJ2_FUNC_GPIO 0x9200 -#define STM32H7_PJ2_FUNC_DSI_TE 0x920e -#define STM32H7_PJ2_FUNC_LCD_R3 0x920f -#define STM32H7_PJ2_FUNC_EVENTOUT 0x9210 -#define STM32H7_PJ2_FUNC_ANALOG 0x9211 - -#define STM32H7_PJ3_FUNC_GPIO 0x9300 -#define STM32H7_PJ3_FUNC_LCD_R4 0x930f -#define STM32H7_PJ3_FUNC_EVENTOUT 0x9310 -#define STM32H7_PJ3_FUNC_ANALOG 0x9311 - -#define STM32H7_PJ4_FUNC_GPIO 0x9400 -#define STM32H7_PJ4_FUNC_LCD_R5 0x940f -#define STM32H7_PJ4_FUNC_EVENTOUT 0x9410 -#define STM32H7_PJ4_FUNC_ANALOG 0x9411 - -#define STM32H7_PJ5_FUNC_GPIO 0x9500 -#define STM32H7_PJ5_FUNC_LCD_R6 0x950f -#define STM32H7_PJ5_FUNC_EVENTOUT 0x9510 -#define STM32H7_PJ5_FUNC_ANALOG 0x9511 - -#define STM32H7_PJ6_FUNC_GPIO 0x9600 -#define STM32H7_PJ6_FUNC_TIM8_CH2 0x9604 -#define STM32H7_PJ6_FUNC_LCD_R7 0x960f -#define STM32H7_PJ6_FUNC_EVENTOUT 0x9610 -#define STM32H7_PJ6_FUNC_ANALOG 0x9611 - -#define STM32H7_PJ7_FUNC_GPIO 0x9700 -#define STM32H7_PJ7_FUNC_TRGIN 0x9701 -#define STM32H7_PJ7_FUNC_TIM8_CH2N 0x9704 -#define STM32H7_PJ7_FUNC_LCD_G0 0x970f -#define STM32H7_PJ7_FUNC_EVENTOUT 0x9710 -#define STM32H7_PJ7_FUNC_ANALOG 0x9711 - -#define STM32H7_PJ8_FUNC_GPIO 0x9800 -#define STM32H7_PJ8_FUNC_TIM1_CH3N 0x9802 -#define STM32H7_PJ8_FUNC_TIM8_CH1 0x9804 -#define STM32H7_PJ8_FUNC_UART8_TX 0x9809 -#define STM32H7_PJ8_FUNC_LCD_G1 0x980f -#define STM32H7_PJ8_FUNC_EVENTOUT 0x9810 -#define STM32H7_PJ8_FUNC_ANALOG 0x9811 - -#define STM32H7_PJ9_FUNC_GPIO 0x9900 -#define STM32H7_PJ9_FUNC_TIM1_CH3 0x9902 -#define STM32H7_PJ9_FUNC_TIM8_CH1N 0x9904 -#define STM32H7_PJ9_FUNC_UART8_RX 0x9909 -#define STM32H7_PJ9_FUNC_LCD_G2 0x990f -#define STM32H7_PJ9_FUNC_EVENTOUT 0x9910 -#define STM32H7_PJ9_FUNC_ANALOG 0x9911 - -#define STM32H7_PJ10_FUNC_GPIO 0x9a00 -#define STM32H7_PJ10_FUNC_TIM1_CH2N 0x9a02 -#define STM32H7_PJ10_FUNC_TIM8_CH2 0x9a04 -#define STM32H7_PJ10_FUNC_SPI5_MOSI 0x9a06 -#define STM32H7_PJ10_FUNC_LCD_G3 0x9a0f -#define STM32H7_PJ10_FUNC_EVENTOUT 0x9a10 -#define STM32H7_PJ10_FUNC_ANALOG 0x9a11 - -#define STM32H7_PJ11_FUNC_GPIO 0x9b00 -#define STM32H7_PJ11_FUNC_TIM1_CH2 0x9b02 -#define STM32H7_PJ11_FUNC_TIM8_CH2N 0x9b04 -#define STM32H7_PJ11_FUNC_SPI5_MISO 0x9b06 -#define STM32H7_PJ11_FUNC_LCD_G4 0x9b0f -#define STM32H7_PJ11_FUNC_EVENTOUT 0x9b10 -#define STM32H7_PJ11_FUNC_ANALOG 0x9b11 - -#define STM32H7_PJ12_FUNC_GPIO 0x9c00 -#define STM32H7_PJ12_FUNC_TRGOUT 0x9c01 -#define STM32H7_PJ12_FUNC_LCD_G3 0x9c0a -#define STM32H7_PJ12_FUNC_LCD_B0 0x9c0f -#define STM32H7_PJ12_FUNC_EVENTOUT 0x9c10 -#define STM32H7_PJ12_FUNC_ANALOG 0x9c11 - -#define STM32H7_PJ13_FUNC_GPIO 0x9d00 -#define STM32H7_PJ13_FUNC_LCD_B4 0x9d0a -#define STM32H7_PJ13_FUNC_LCD_B1 0x9d0f -#define STM32H7_PJ13_FUNC_EVENTOUT 0x9d10 -#define STM32H7_PJ13_FUNC_ANALOG 0x9d11 - -#define STM32H7_PJ14_FUNC_GPIO 0x9e00 -#define STM32H7_PJ14_FUNC_LCD_B2 0x9e0f -#define STM32H7_PJ14_FUNC_EVENTOUT 0x9e10 -#define STM32H7_PJ14_FUNC_ANALOG 0x9e11 - -#define STM32H7_PJ15_FUNC_GPIO 0x9f00 -#define STM32H7_PJ15_FUNC_LCD_B3 0x9f0f -#define STM32H7_PJ15_FUNC_EVENTOUT 0x9f10 -#define STM32H7_PJ15_FUNC_ANALOG 0x9f11 - -#define STM32H7_PK0_FUNC_GPIO 0xa000 -#define STM32H7_PK0_FUNC_TIM1_CH1N 0xa002 -#define STM32H7_PK0_FUNC_TIM8_CH3 0xa004 -#define STM32H7_PK0_FUNC_SPI5_SCK 0xa006 -#define STM32H7_PK0_FUNC_LCD_G5 0xa00f -#define STM32H7_PK0_FUNC_EVENTOUT 0xa010 -#define STM32H7_PK0_FUNC_ANALOG 0xa011 - -#define STM32H7_PK1_FUNC_GPIO 0xa100 -#define STM32H7_PK1_FUNC_TIM1_CH1 0xa102 -#define STM32H7_PK1_FUNC_TIM8_CH3N 0xa104 -#define STM32H7_PK1_FUNC_SPI5_NSS 0xa106 -#define STM32H7_PK1_FUNC_LCD_G6 0xa10f -#define STM32H7_PK1_FUNC_EVENTOUT 0xa110 -#define STM32H7_PK1_FUNC_ANALOG 0xa111 - -#define STM32H7_PK2_FUNC_GPIO 0xa200 -#define STM32H7_PK2_FUNC_TIM1_BKIN 0xa202 -#define STM32H7_PK2_FUNC_TIM8_BKIN 0xa204 -#define STM32H7_PK2_FUNC_TIM8_BKIN_COMP12 0xa20b -#define STM32H7_PK2_FUNC_TIM1_BKIN_COMP12 0xa20c -#define STM32H7_PK2_FUNC_LCD_G7 0xa20f -#define STM32H7_PK2_FUNC_EVENTOUT 0xa210 -#define STM32H7_PK2_FUNC_ANALOG 0xa211 - -#define STM32H7_PK3_FUNC_GPIO 0xa300 -#define STM32H7_PK3_FUNC_LCD_B4 0xa30f -#define STM32H7_PK3_FUNC_EVENTOUT 0xa310 -#define STM32H7_PK3_FUNC_ANALOG 0xa311 - -#define STM32H7_PK4_FUNC_GPIO 0xa400 -#define STM32H7_PK4_FUNC_LCD_B5 0xa40f -#define STM32H7_PK4_FUNC_EVENTOUT 0xa410 -#define STM32H7_PK4_FUNC_ANALOG 0xa411 - -#define STM32H7_PK5_FUNC_GPIO 0xa500 -#define STM32H7_PK5_FUNC_LCD_B6 0xa50f -#define STM32H7_PK5_FUNC_EVENTOUT 0xa510 -#define STM32H7_PK5_FUNC_ANALOG 0xa511 - -#define STM32H7_PK6_FUNC_GPIO 0xa600 -#define STM32H7_PK6_FUNC_LCD_B7 0xa60f -#define STM32H7_PK6_FUNC_EVENTOUT 0xa610 -#define STM32H7_PK6_FUNC_ANALOG 0xa611 - -#define STM32H7_PK7_FUNC_GPIO 0xa700 -#define STM32H7_PK7_FUNC_LCD_DE 0xa70f -#define STM32H7_PK7_FUNC_EVENTOUT 0xa710 -#define STM32H7_PK7_FUNC_ANALOG 0xa711 - -#endif /* _DT_BINDINGS_STM32H7_PINFUNC_H */ diff --git a/sys/gnu/dts/include/dt-bindings/pinctrl/sun4i-a10.h b/sys/gnu/dts/include/dt-bindings/pinctrl/sun4i-a10.h deleted file mode 100644 index f7553c143b4..00000000000 --- a/sys/gnu/dts/include/dt-bindings/pinctrl/sun4i-a10.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - * Copyright 2014 Maxime Ripard - * - * Maxime Ripard - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef __DT_BINDINGS_PINCTRL_SUN4I_A10_H_ -#define __DT_BINDINGS_PINCTRL_SUN4I_A10_H_ - -#define SUN4I_PINCTRL_10_MA 0 -#define SUN4I_PINCTRL_20_MA 1 -#define SUN4I_PINCTRL_30_MA 2 -#define SUN4I_PINCTRL_40_MA 3 - -#define SUN4I_PINCTRL_NO_PULL 0 -#define SUN4I_PINCTRL_PULL_UP 1 -#define SUN4I_PINCTRL_PULL_DOWN 2 - -#endif /* __DT_BINDINGS_PINCTRL_SUN4I_A10_H_ */ diff --git a/sys/gnu/dts/include/dt-bindings/pmu/exynos_ppmu.h b/sys/gnu/dts/include/dt-bindings/pmu/exynos_ppmu.h deleted file mode 100644 index 8724abe130f..00000000000 --- a/sys/gnu/dts/include/dt-bindings/pmu/exynos_ppmu.h +++ /dev/null @@ -1,25 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Samsung Exynos PPMU event types for counting in regs - * - * Copyright (c) 2019, Samsung Electronics - * Author: Lukasz Luba - */ - -#ifndef __DT_BINDINGS_PMU_EXYNOS_PPMU_H -#define __DT_BINDINGS_PMU_EXYNOS_PPMU_H - -#define PPMU_RO_BUSY_CYCLE_CNT 0x0 -#define PPMU_WO_BUSY_CYCLE_CNT 0x1 -#define PPMU_RW_BUSY_CYCLE_CNT 0x2 -#define PPMU_RO_REQUEST_CNT 0x3 -#define PPMU_WO_REQUEST_CNT 0x4 -#define PPMU_RO_DATA_CNT 0x5 -#define PPMU_WO_DATA_CNT 0x6 -#define PPMU_RO_LATENCY 0x12 -#define PPMU_WO_LATENCY 0x16 -#define PPMU_V2_RO_DATA_CNT 0x4 -#define PPMU_V2_WO_DATA_CNT 0x5 -#define PPMU_V2_EVT3_RW_DATA_CNT 0x22 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/power/imx7-power.h b/sys/gnu/dts/include/dt-bindings/power/imx7-power.h deleted file mode 100644 index 597c1aa06ae..00000000000 --- a/sys/gnu/dts/include/dt-bindings/power/imx7-power.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) 2017 Impinj - */ - -#ifndef __DT_BINDINGS_IMX7_POWER_H__ -#define __DT_BINDINGS_IMX7_POWER_H__ - -#define IMX7_POWER_DOMAIN_MIPI_PHY 0 -#define IMX7_POWER_DOMAIN_PCIE_PHY 1 -#define IMX7_POWER_DOMAIN_USB_HSIC_PHY 2 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/power/imx8mq-power.h b/sys/gnu/dts/include/dt-bindings/power/imx8mq-power.h deleted file mode 100644 index 8a513bd9166..00000000000 --- a/sys/gnu/dts/include/dt-bindings/power/imx8mq-power.h +++ /dev/null @@ -1,21 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ -/* - * Copyright (C) 2018 Pengutronix, Lucas Stach - */ - -#ifndef __DT_BINDINGS_IMX8MQ_POWER_H__ -#define __DT_BINDINGS_IMX8MQ_POWER_H__ - -#define IMX8M_POWER_DOMAIN_MIPI 0 -#define IMX8M_POWER_DOMAIN_PCIE1 1 -#define IMX8M_POWER_DOMAIN_USB_OTG1 2 -#define IMX8M_POWER_DOMAIN_USB_OTG2 3 -#define IMX8M_POWER_DOMAIN_DDR1 4 -#define IMX8M_POWER_DOMAIN_GPU 5 -#define IMX8M_POWER_DOMAIN_VPU 6 -#define IMX8M_POWER_DOMAIN_DISP 7 -#define IMX8M_POWER_DOMAIN_MIPI_CSI1 8 -#define IMX8M_POWER_DOMAIN_MIPI_CSI2 9 -#define IMX8M_POWER_DOMAIN_PCIE2 10 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/power/meson-g12a-power.h b/sys/gnu/dts/include/dt-bindings/power/meson-g12a-power.h deleted file mode 100644 index bb5e67a842d..00000000000 --- a/sys/gnu/dts/include/dt-bindings/power/meson-g12a-power.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ -/* - * Copyright (c) 2019 BayLibre, SAS - * Author: Neil Armstrong - */ - -#ifndef _DT_BINDINGS_MESON_G12A_POWER_H -#define _DT_BINDINGS_MESON_G12A_POWER_H - -#define PWRC_G12A_VPU_ID 0 -#define PWRC_G12A_ETH_ID 1 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/power/meson-sm1-power.h b/sys/gnu/dts/include/dt-bindings/power/meson-sm1-power.h deleted file mode 100644 index a020ab00c13..00000000000 --- a/sys/gnu/dts/include/dt-bindings/power/meson-sm1-power.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ -/* - * Copyright (c) 2019 BayLibre, SAS - * Author: Neil Armstrong - */ - -#ifndef _DT_BINDINGS_MESON_SM1_POWER_H -#define _DT_BINDINGS_MESON_SM1_POWER_H - -#define PWRC_SM1_VPU_ID 0 -#define PWRC_SM1_NNA_ID 1 -#define PWRC_SM1_USB_ID 2 -#define PWRC_SM1_PCIE_ID 3 -#define PWRC_SM1_GE2D_ID 4 -#define PWRC_SM1_AUDIO_ID 5 -#define PWRC_SM1_ETH_ID 6 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/power/mt2701-power.h b/sys/gnu/dts/include/dt-bindings/power/mt2701-power.h deleted file mode 100644 index 09e16f89576..00000000000 --- a/sys/gnu/dts/include/dt-bindings/power/mt2701-power.h +++ /dev/null @@ -1,19 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) 2015 MediaTek Inc. - */ - -#ifndef _DT_BINDINGS_POWER_MT2701_POWER_H -#define _DT_BINDINGS_POWER_MT2701_POWER_H - -#define MT2701_POWER_DOMAIN_CONN 0 -#define MT2701_POWER_DOMAIN_DISP 1 -#define MT2701_POWER_DOMAIN_MFG 2 -#define MT2701_POWER_DOMAIN_VDEC 3 -#define MT2701_POWER_DOMAIN_ISP 4 -#define MT2701_POWER_DOMAIN_BDP 5 -#define MT2701_POWER_DOMAIN_ETH 6 -#define MT2701_POWER_DOMAIN_HIF 7 -#define MT2701_POWER_DOMAIN_IFR_MSC 8 - -#endif /* _DT_BINDINGS_POWER_MT2701_POWER_H */ diff --git a/sys/gnu/dts/include/dt-bindings/power/mt2712-power.h b/sys/gnu/dts/include/dt-bindings/power/mt2712-power.h deleted file mode 100644 index 95bdb1c20f7..00000000000 --- a/sys/gnu/dts/include/dt-bindings/power/mt2712-power.h +++ /dev/null @@ -1,21 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) 2017 MediaTek Inc. - */ - -#ifndef _DT_BINDINGS_POWER_MT2712_POWER_H -#define _DT_BINDINGS_POWER_MT2712_POWER_H - -#define MT2712_POWER_DOMAIN_MM 0 -#define MT2712_POWER_DOMAIN_VDEC 1 -#define MT2712_POWER_DOMAIN_VENC 2 -#define MT2712_POWER_DOMAIN_ISP 3 -#define MT2712_POWER_DOMAIN_AUDIO 4 -#define MT2712_POWER_DOMAIN_USB 5 -#define MT2712_POWER_DOMAIN_USB2 6 -#define MT2712_POWER_DOMAIN_MFG 7 -#define MT2712_POWER_DOMAIN_MFG_SC1 8 -#define MT2712_POWER_DOMAIN_MFG_SC2 9 -#define MT2712_POWER_DOMAIN_MFG_SC3 10 - -#endif /* _DT_BINDINGS_POWER_MT2712_POWER_H */ diff --git a/sys/gnu/dts/include/dt-bindings/power/mt6765-power.h b/sys/gnu/dts/include/dt-bindings/power/mt6765-power.h deleted file mode 100644 index d347b4ee9ee..00000000000 --- a/sys/gnu/dts/include/dt-bindings/power/mt6765-power.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _DT_BINDINGS_POWER_MT6765_POWER_H -#define _DT_BINDINGS_POWER_MT6765_POWER_H - -#define MT6765_POWER_DOMAIN_CONN 0 -#define MT6765_POWER_DOMAIN_MM 1 -#define MT6765_POWER_DOMAIN_MFG_ASYNC 2 -#define MT6765_POWER_DOMAIN_ISP 3 -#define MT6765_POWER_DOMAIN_MFG 4 -#define MT6765_POWER_DOMAIN_MFG_CORE0 5 -#define MT6765_POWER_DOMAIN_CAM 6 -#define MT6765_POWER_DOMAIN_VCODEC 7 - -#endif /* _DT_BINDINGS_POWER_MT6765_POWER_H */ diff --git a/sys/gnu/dts/include/dt-bindings/power/mt6797-power.h b/sys/gnu/dts/include/dt-bindings/power/mt6797-power.h deleted file mode 100644 index a60c1d81cf7..00000000000 --- a/sys/gnu/dts/include/dt-bindings/power/mt6797-power.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (c) 2017 MediaTek Inc. - * Author: Mars.C - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _DT_BINDINGS_POWER_MT6797_POWER_H -#define _DT_BINDINGS_POWER_MT6797_POWER_H - -#define MT6797_POWER_DOMAIN_VDEC 0 -#define MT6797_POWER_DOMAIN_VENC 1 -#define MT6797_POWER_DOMAIN_ISP 2 -#define MT6797_POWER_DOMAIN_MM 3 -#define MT6797_POWER_DOMAIN_AUDIO 4 -#define MT6797_POWER_DOMAIN_MFG_ASYNC 5 -#define MT6797_POWER_DOMAIN_MFG 6 -#define MT6797_POWER_DOMAIN_MFG_CORE0 7 -#define MT6797_POWER_DOMAIN_MFG_CORE1 8 -#define MT6797_POWER_DOMAIN_MFG_CORE2 9 -#define MT6797_POWER_DOMAIN_MFG_CORE3 10 -#define MT6797_POWER_DOMAIN_MJC 11 - -#endif /* _DT_BINDINGS_POWER_MT6797_POWER_H */ diff --git a/sys/gnu/dts/include/dt-bindings/power/mt7622-power.h b/sys/gnu/dts/include/dt-bindings/power/mt7622-power.h deleted file mode 100644 index ffad81ad3d4..00000000000 --- a/sys/gnu/dts/include/dt-bindings/power/mt7622-power.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) 2017 MediaTek Inc. - */ - -#ifndef _DT_BINDINGS_POWER_MT7622_POWER_H -#define _DT_BINDINGS_POWER_MT7622_POWER_H - -#define MT7622_POWER_DOMAIN_ETHSYS 0 -#define MT7622_POWER_DOMAIN_HIF0 1 -#define MT7622_POWER_DOMAIN_HIF1 2 -#define MT7622_POWER_DOMAIN_WB 3 - -#endif /* _DT_BINDINGS_POWER_MT7622_POWER_H */ diff --git a/sys/gnu/dts/include/dt-bindings/power/mt7623a-power.h b/sys/gnu/dts/include/dt-bindings/power/mt7623a-power.h deleted file mode 100644 index 2544822aa76..00000000000 --- a/sys/gnu/dts/include/dt-bindings/power/mt7623a-power.h +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _DT_BINDINGS_POWER_MT7623A_POWER_H -#define _DT_BINDINGS_POWER_MT7623A_POWER_H - -#define MT7623A_POWER_DOMAIN_CONN 0 -#define MT7623A_POWER_DOMAIN_ETH 1 -#define MT7623A_POWER_DOMAIN_HIF 2 -#define MT7623A_POWER_DOMAIN_IFR_MSC 3 - -#endif /* _DT_BINDINGS_POWER_MT7623A_POWER_H */ diff --git a/sys/gnu/dts/include/dt-bindings/power/mt8173-power.h b/sys/gnu/dts/include/dt-bindings/power/mt8173-power.h deleted file mode 100644 index ef4a7f94484..00000000000 --- a/sys/gnu/dts/include/dt-bindings/power/mt8173-power.h +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _DT_BINDINGS_POWER_MT8173_POWER_H -#define _DT_BINDINGS_POWER_MT8173_POWER_H - -#define MT8173_POWER_DOMAIN_VDEC 0 -#define MT8173_POWER_DOMAIN_VENC 1 -#define MT8173_POWER_DOMAIN_ISP 2 -#define MT8173_POWER_DOMAIN_MM 3 -#define MT8173_POWER_DOMAIN_VENC_LT 4 -#define MT8173_POWER_DOMAIN_AUDIO 5 -#define MT8173_POWER_DOMAIN_USB 6 -#define MT8173_POWER_DOMAIN_MFG_ASYNC 7 -#define MT8173_POWER_DOMAIN_MFG_2D 8 -#define MT8173_POWER_DOMAIN_MFG 9 - -#endif /* _DT_BINDINGS_POWER_MT8173_POWER_H */ diff --git a/sys/gnu/dts/include/dt-bindings/power/owl-s500-powergate.h b/sys/gnu/dts/include/dt-bindings/power/owl-s500-powergate.h deleted file mode 100644 index 0a1c451865e..00000000000 --- a/sys/gnu/dts/include/dt-bindings/power/owl-s500-powergate.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * Copyright (c) 2017 Andreas Färber - * - * SPDX-License-Identifier: (GPL-2.0+ OR MIT) - */ -#ifndef DT_BINDINGS_POWER_OWL_S500_POWERGATE_H -#define DT_BINDINGS_POWER_OWL_S500_POWERGATE_H - -#define S500_PD_VDE 0 -#define S500_PD_VCE_SI 1 -#define S500_PD_USB2_1 2 -#define S500_PD_CPU2 3 -#define S500_PD_CPU3 4 -#define S500_PD_DMA 5 -#define S500_PD_DS 6 -#define S500_PD_USB3 7 -#define S500_PD_USB2_0 8 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/power/owl-s700-powergate.h b/sys/gnu/dts/include/dt-bindings/power/owl-s700-powergate.h deleted file mode 100644 index 4cf1aefbf09..00000000000 --- a/sys/gnu/dts/include/dt-bindings/power/owl-s700-powergate.h +++ /dev/null @@ -1,19 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Actions Semi S700 SPS - * - * Copyright (c) 2017 Andreas Färber - */ -#ifndef DT_BINDINGS_POWER_OWL_S700_POWERGATE_H -#define DT_BINDINGS_POWER_OWL_S700_POWERGATE_H - -#define S700_PD_VDE 0 -#define S700_PD_VCE_SI 1 -#define S700_PD_USB2_1 2 -#define S700_PD_HDE 3 -#define S700_PD_DMA 4 -#define S700_PD_DS 5 -#define S700_PD_USB3 6 -#define S700_PD_USB2_0 7 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/power/owl-s900-powergate.h b/sys/gnu/dts/include/dt-bindings/power/owl-s900-powergate.h deleted file mode 100644 index d939bd96465..00000000000 --- a/sys/gnu/dts/include/dt-bindings/power/owl-s900-powergate.h +++ /dev/null @@ -1,23 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) */ -/* - * Actions Semi S900 SPS - * - * Copyright (c) 2018 Linaro Ltd. - */ -#ifndef DT_BINDINGS_POWER_OWL_S900_POWERGATE_H -#define DT_BINDINGS_POWER_OWL_S900_POWERGATE_H - -#define S900_PD_GPU_B 0 -#define S900_PD_VCE 1 -#define S900_PD_SENSOR 2 -#define S900_PD_VDE 3 -#define S900_PD_HDE 4 -#define S900_PD_USB3 5 -#define S900_PD_DDR0 6 -#define S900_PD_DDR1 7 -#define S900_PD_DE 8 -#define S900_PD_NAND 9 -#define S900_PD_USB2_H0 10 -#define S900_PD_USB2_H1 11 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/power/px30-power.h b/sys/gnu/dts/include/dt-bindings/power/px30-power.h deleted file mode 100644 index 30917a99ad2..00000000000 --- a/sys/gnu/dts/include/dt-bindings/power/px30-power.h +++ /dev/null @@ -1,27 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __DT_BINDINGS_POWER_PX30_POWER_H__ -#define __DT_BINDINGS_POWER_PX30_POWER_H__ - -/* VD_CORE */ -#define PX30_PD_A35_0 0 -#define PX30_PD_A35_1 1 -#define PX30_PD_A35_2 2 -#define PX30_PD_A35_3 3 -#define PX30_PD_SCU 4 - -/* VD_LOGIC */ -#define PX30_PD_USB 5 -#define PX30_PD_DDR 6 -#define PX30_PD_SDCARD 7 -#define PX30_PD_CRYPTO 8 -#define PX30_PD_GMAC 9 -#define PX30_PD_MMC_NAND 10 -#define PX30_PD_VPU 11 -#define PX30_PD_VO 12 -#define PX30_PD_VI 13 -#define PX30_PD_GPU 14 - -/* VD_PMU */ -#define PX30_PD_PMU 15 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/power/qcom-aoss-qmp.h b/sys/gnu/dts/include/dt-bindings/power/qcom-aoss-qmp.h deleted file mode 100644 index ec336d31dee..00000000000 --- a/sys/gnu/dts/include/dt-bindings/power/qcom-aoss-qmp.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* Copyright (c) 2018, Linaro Ltd. */ - -#ifndef __DT_BINDINGS_POWER_QCOM_AOSS_QMP_H -#define __DT_BINDINGS_POWER_QCOM_AOSS_QMP_H - -#define AOSS_QMP_LS_CDSP 0 -#define AOSS_QMP_LS_LPASS 1 -#define AOSS_QMP_LS_MODEM 2 -#define AOSS_QMP_LS_SLPI 3 -#define AOSS_QMP_LS_SPSS 4 -#define AOSS_QMP_LS_VENUS 5 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/power/qcom-rpmpd.h b/sys/gnu/dts/include/dt-bindings/power/qcom-rpmpd.h deleted file mode 100644 index 3f74096d5a7..00000000000 --- a/sys/gnu/dts/include/dt-bindings/power/qcom-rpmpd.h +++ /dev/null @@ -1,106 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* Copyright (c) 2018, The Linux Foundation. All rights reserved. */ - -#ifndef _DT_BINDINGS_POWER_QCOM_RPMPD_H -#define _DT_BINDINGS_POWER_QCOM_RPMPD_H - -/* SDM845 Power Domain Indexes */ -#define SDM845_EBI 0 -#define SDM845_MX 1 -#define SDM845_MX_AO 2 -#define SDM845_CX 3 -#define SDM845_CX_AO 4 -#define SDM845_LMX 5 -#define SDM845_LCX 6 -#define SDM845_GFX 7 -#define SDM845_MSS 8 - -/* SM8150 Power Domain Indexes */ -#define SM8150_MSS 0 -#define SM8150_EBI 1 -#define SM8150_LMX 2 -#define SM8150_LCX 3 -#define SM8150_GFX 4 -#define SM8150_MX 5 -#define SM8150_MX_AO 6 -#define SM8150_CX 7 -#define SM8150_CX_AO 8 -#define SM8150_MMCX 9 -#define SM8150_MMCX_AO 10 - -/* SC7180 Power Domain Indexes */ -#define SC7180_CX 0 -#define SC7180_CX_AO 1 -#define SC7180_GFX 2 -#define SC7180_MX 3 -#define SC7180_MX_AO 4 -#define SC7180_LMX 5 -#define SC7180_LCX 6 -#define SC7180_MSS 7 - -/* SDM845 Power Domain performance levels */ -#define RPMH_REGULATOR_LEVEL_RETENTION 16 -#define RPMH_REGULATOR_LEVEL_MIN_SVS 48 -#define RPMH_REGULATOR_LEVEL_LOW_SVS 64 -#define RPMH_REGULATOR_LEVEL_SVS 128 -#define RPMH_REGULATOR_LEVEL_SVS_L1 192 -#define RPMH_REGULATOR_LEVEL_SVS_L2 224 -#define RPMH_REGULATOR_LEVEL_NOM 256 -#define RPMH_REGULATOR_LEVEL_NOM_L1 320 -#define RPMH_REGULATOR_LEVEL_NOM_L2 336 -#define RPMH_REGULATOR_LEVEL_TURBO 384 -#define RPMH_REGULATOR_LEVEL_TURBO_L1 416 - -/* MSM8976 Power Domain Indexes */ -#define MSM8976_VDDCX 0 -#define MSM8976_VDDCX_AO 1 -#define MSM8976_VDDCX_VFL 2 -#define MSM8976_VDDMX 3 -#define MSM8976_VDDMX_AO 4 -#define MSM8976_VDDMX_VFL 5 - -/* MSM8996 Power Domain Indexes */ -#define MSM8996_VDDCX 0 -#define MSM8996_VDDCX_AO 1 -#define MSM8996_VDDCX_VFC 2 -#define MSM8996_VDDMX 3 -#define MSM8996_VDDMX_AO 4 -#define MSM8996_VDDSSCX 5 -#define MSM8996_VDDSSCX_VFC 6 - -/* MSM8998 Power Domain Indexes */ -#define MSM8998_VDDCX 0 -#define MSM8998_VDDCX_AO 1 -#define MSM8998_VDDCX_VFL 2 -#define MSM8998_VDDMX 3 -#define MSM8998_VDDMX_AO 4 -#define MSM8998_VDDMX_VFL 5 -#define MSM8998_SSCCX 6 -#define MSM8998_SSCCX_VFL 7 -#define MSM8998_SSCMX 8 -#define MSM8998_SSCMX_VFL 9 - -/* QCS404 Power Domains */ -#define QCS404_VDDMX 0 -#define QCS404_VDDMX_AO 1 -#define QCS404_VDDMX_VFL 2 -#define QCS404_LPICX 3 -#define QCS404_LPICX_VFL 4 -#define QCS404_LPIMX 5 -#define QCS404_LPIMX_VFL 6 - -/* RPM SMD Power Domain performance levels */ -#define RPM_SMD_LEVEL_RETENTION 16 -#define RPM_SMD_LEVEL_RETENTION_PLUS 32 -#define RPM_SMD_LEVEL_MIN_SVS 48 -#define RPM_SMD_LEVEL_LOW_SVS 64 -#define RPM_SMD_LEVEL_SVS 128 -#define RPM_SMD_LEVEL_SVS_PLUS 192 -#define RPM_SMD_LEVEL_NOM 256 -#define RPM_SMD_LEVEL_NOM_PLUS 320 -#define RPM_SMD_LEVEL_TURBO 384 -#define RPM_SMD_LEVEL_TURBO_NO_CPR 416 -#define RPM_SMD_LEVEL_TURBO_HIGH 448 -#define RPM_SMD_LEVEL_BINNING 512 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/power/r8a7743-sysc.h b/sys/gnu/dts/include/dt-bindings/power/r8a7743-sysc.h deleted file mode 100644 index 1b863932da1..00000000000 --- a/sys/gnu/dts/include/dt-bindings/power/r8a7743-sysc.h +++ /dev/null @@ -1,22 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) 2016 Cogent Embedded Inc. - */ -#ifndef __DT_BINDINGS_POWER_R8A7743_SYSC_H__ -#define __DT_BINDINGS_POWER_R8A7743_SYSC_H__ - -/* - * These power domain indices match the numbers of the interrupt bits - * representing the power areas in the various Interrupt Registers - * (e.g. SYSCISR, Interrupt Status Register) - */ - -#define R8A7743_PD_CA15_CPU0 0 -#define R8A7743_PD_CA15_CPU1 1 -#define R8A7743_PD_CA15_SCU 12 -#define R8A7743_PD_SGX 20 - -/* Always-on power area */ -#define R8A7743_PD_ALWAYS_ON 32 - -#endif /* __DT_BINDINGS_POWER_R8A7743_SYSC_H__ */ diff --git a/sys/gnu/dts/include/dt-bindings/power/r8a7744-sysc.h b/sys/gnu/dts/include/dt-bindings/power/r8a7744-sysc.h deleted file mode 100644 index 8b6529778f9..00000000000 --- a/sys/gnu/dts/include/dt-bindings/power/r8a7744-sysc.h +++ /dev/null @@ -1,24 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 - * - * Copyright (C) 2018 Renesas Electronics Corp. - */ -#ifndef __DT_BINDINGS_POWER_R8A7744_SYSC_H__ -#define __DT_BINDINGS_POWER_R8A7744_SYSC_H__ - -/* - * These power domain indices match the numbers of the interrupt bits - * representing the power areas in the various Interrupt Registers - * (e.g. SYSCISR, Interrupt Status Register) - * - * Note that RZ/G1N is identical to RZ/G2M w.r.t. power domains. - */ - -#define R8A7744_PD_CA15_CPU0 0 -#define R8A7744_PD_CA15_CPU1 1 -#define R8A7744_PD_CA15_SCU 12 -#define R8A7744_PD_SGX 20 - -/* Always-on power area */ -#define R8A7744_PD_ALWAYS_ON 32 - -#endif /* __DT_BINDINGS_POWER_R8A7744_SYSC_H__ */ diff --git a/sys/gnu/dts/include/dt-bindings/power/r8a7745-sysc.h b/sys/gnu/dts/include/dt-bindings/power/r8a7745-sysc.h deleted file mode 100644 index 725ad3504d6..00000000000 --- a/sys/gnu/dts/include/dt-bindings/power/r8a7745-sysc.h +++ /dev/null @@ -1,22 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) 2016 Cogent Embedded Inc. - */ -#ifndef __DT_BINDINGS_POWER_R8A7745_SYSC_H__ -#define __DT_BINDINGS_POWER_R8A7745_SYSC_H__ - -/* - * These power domain indices match the numbers of the interrupt bits - * representing the power areas in the various Interrupt Registers - * (e.g. SYSCISR, Interrupt Status Register) - */ - -#define R8A7745_PD_CA7_CPU0 5 -#define R8A7745_PD_CA7_CPU1 6 -#define R8A7745_PD_SGX 20 -#define R8A7745_PD_CA7_SCU 21 - -/* Always-on power area */ -#define R8A7745_PD_ALWAYS_ON 32 - -#endif /* __DT_BINDINGS_POWER_R8A7745_SYSC_H__ */ diff --git a/sys/gnu/dts/include/dt-bindings/power/r8a77470-sysc.h b/sys/gnu/dts/include/dt-bindings/power/r8a77470-sysc.h deleted file mode 100644 index 8bf4db187c3..00000000000 --- a/sys/gnu/dts/include/dt-bindings/power/r8a77470-sysc.h +++ /dev/null @@ -1,22 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 - * - * Copyright (C) 2018 Renesas Electronics Corp. - */ -#ifndef __DT_BINDINGS_POWER_R8A77470_SYSC_H__ -#define __DT_BINDINGS_POWER_R8A77470_SYSC_H__ - -/* - * These power domain indices match the numbers of the interrupt bits - * representing the power areas in the various Interrupt Registers - * (e.g. SYSCISR, Interrupt Status Register) - */ - -#define R8A77470_PD_CA7_CPU0 5 -#define R8A77470_PD_CA7_CPU1 6 -#define R8A77470_PD_SGX 20 -#define R8A77470_PD_CA7_SCU 21 - -/* Always-on power area */ -#define R8A77470_PD_ALWAYS_ON 32 - -#endif /* __DT_BINDINGS_POWER_R8A77470_SYSC_H__ */ diff --git a/sys/gnu/dts/include/dt-bindings/power/r8a774a1-sysc.h b/sys/gnu/dts/include/dt-bindings/power/r8a774a1-sysc.h deleted file mode 100644 index 580f431cd32..00000000000 --- a/sys/gnu/dts/include/dt-bindings/power/r8a774a1-sysc.h +++ /dev/null @@ -1,31 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 - * - * Copyright (C) 2018 Renesas Electronics Corp. - */ -#ifndef __DT_BINDINGS_POWER_R8A774A1_SYSC_H__ -#define __DT_BINDINGS_POWER_R8A774A1_SYSC_H__ - -/* - * These power domain indices match the numbers of the interrupt bits - * representing the power areas in the various Interrupt Registers - * (e.g. SYSCISR, Interrupt Status Register) - */ - -#define R8A774A1_PD_CA57_CPU0 0 -#define R8A774A1_PD_CA57_CPU1 1 -#define R8A774A1_PD_CA53_CPU0 5 -#define R8A774A1_PD_CA53_CPU1 6 -#define R8A774A1_PD_CA53_CPU2 7 -#define R8A774A1_PD_CA53_CPU3 8 -#define R8A774A1_PD_CA57_SCU 12 -#define R8A774A1_PD_A3VC 14 -#define R8A774A1_PD_3DG_A 17 -#define R8A774A1_PD_3DG_B 18 -#define R8A774A1_PD_CA53_SCU 21 -#define R8A774A1_PD_A2VC0 25 -#define R8A774A1_PD_A2VC1 26 - -/* Always-on power area */ -#define R8A774A1_PD_ALWAYS_ON 32 - -#endif /* __DT_BINDINGS_POWER_R8A774A1_SYSC_H__ */ diff --git a/sys/gnu/dts/include/dt-bindings/power/r8a774b1-sysc.h b/sys/gnu/dts/include/dt-bindings/power/r8a774b1-sysc.h deleted file mode 100644 index 373736402f0..00000000000 --- a/sys/gnu/dts/include/dt-bindings/power/r8a774b1-sysc.h +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 - * - * Copyright (C) 2019 Renesas Electronics Corp. - */ -#ifndef __DT_BINDINGS_POWER_R8A774B1_SYSC_H__ -#define __DT_BINDINGS_POWER_R8A774B1_SYSC_H__ - -/* - * These power domain indices match the numbers of the interrupt bits - * representing the power areas in the various Interrupt Registers - * (e.g. SYSCISR, Interrupt Status Register) - */ - -#define R8A774B1_PD_CA57_CPU0 0 -#define R8A774B1_PD_CA57_CPU1 1 -#define R8A774B1_PD_A3VP 9 -#define R8A774B1_PD_CA57_SCU 12 -#define R8A774B1_PD_A3VC 14 -#define R8A774B1_PD_3DG_A 17 -#define R8A774B1_PD_3DG_B 18 -#define R8A774B1_PD_A2VC1 26 - -/* Always-on power area */ -#define R8A774B1_PD_ALWAYS_ON 32 - -#endif /* __DT_BINDINGS_POWER_R8A774B1_SYSC_H__ */ diff --git a/sys/gnu/dts/include/dt-bindings/power/r8a774c0-sysc.h b/sys/gnu/dts/include/dt-bindings/power/r8a774c0-sysc.h deleted file mode 100644 index 9922d4c6f87..00000000000 --- a/sys/gnu/dts/include/dt-bindings/power/r8a774c0-sysc.h +++ /dev/null @@ -1,25 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 - * - * Copyright (C) 2018 Renesas Electronics Corp. - */ -#ifndef __DT_BINDINGS_POWER_R8A774C0_SYSC_H__ -#define __DT_BINDINGS_POWER_R8A774C0_SYSC_H__ - -/* - * These power domain indices match the numbers of the interrupt bits - * representing the power areas in the various Interrupt Registers - * (e.g. SYSCISR, Interrupt Status Register) - */ - -#define R8A774C0_PD_CA53_CPU0 5 -#define R8A774C0_PD_CA53_CPU1 6 -#define R8A774C0_PD_A3VC 14 -#define R8A774C0_PD_3DG_A 17 -#define R8A774C0_PD_3DG_B 18 -#define R8A774C0_PD_CA53_SCU 21 -#define R8A774C0_PD_A2VC1 26 - -/* Always-on power area */ -#define R8A774C0_PD_ALWAYS_ON 32 - -#endif /* __DT_BINDINGS_POWER_R8A774C0_SYSC_H__ */ diff --git a/sys/gnu/dts/include/dt-bindings/power/r8a7779-sysc.h b/sys/gnu/dts/include/dt-bindings/power/r8a7779-sysc.h deleted file mode 100644 index c4f528b6cc1..00000000000 --- a/sys/gnu/dts/include/dt-bindings/power/r8a7779-sysc.h +++ /dev/null @@ -1,24 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) 2016 Glider bvba - */ -#ifndef __DT_BINDINGS_POWER_R8A7779_SYSC_H__ -#define __DT_BINDINGS_POWER_R8A7779_SYSC_H__ - -/* - * These power domain indices match the numbers of the interrupt bits - * representing the power areas in the various Interrupt Registers - * (e.g. SYSCISR, Interrupt Status Register) - */ - -#define R8A7779_PD_ARM1 1 -#define R8A7779_PD_ARM2 2 -#define R8A7779_PD_ARM3 3 -#define R8A7779_PD_SGX 20 -#define R8A7779_PD_VDP 21 -#define R8A7779_PD_IMP 24 - -/* Always-on power area */ -#define R8A7779_PD_ALWAYS_ON 32 - -#endif /* __DT_BINDINGS_POWER_R8A7779_SYSC_H__ */ diff --git a/sys/gnu/dts/include/dt-bindings/power/r8a7790-sysc.h b/sys/gnu/dts/include/dt-bindings/power/r8a7790-sysc.h deleted file mode 100644 index bcb49057060..00000000000 --- a/sys/gnu/dts/include/dt-bindings/power/r8a7790-sysc.h +++ /dev/null @@ -1,31 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) 2016 Glider bvba - */ -#ifndef __DT_BINDINGS_POWER_R8A7790_SYSC_H__ -#define __DT_BINDINGS_POWER_R8A7790_SYSC_H__ - -/* - * These power domain indices match the numbers of the interrupt bits - * representing the power areas in the various Interrupt Registers - * (e.g. SYSCISR, Interrupt Status Register) - */ - -#define R8A7790_PD_CA15_CPU0 0 -#define R8A7790_PD_CA15_CPU1 1 -#define R8A7790_PD_CA15_CPU2 2 -#define R8A7790_PD_CA15_CPU3 3 -#define R8A7790_PD_CA7_CPU0 5 -#define R8A7790_PD_CA7_CPU1 6 -#define R8A7790_PD_CA7_CPU2 7 -#define R8A7790_PD_CA7_CPU3 8 -#define R8A7790_PD_CA15_SCU 12 -#define R8A7790_PD_SH_4A 16 -#define R8A7790_PD_RGX 20 -#define R8A7790_PD_CA7_SCU 21 -#define R8A7790_PD_IMP 24 - -/* Always-on power area */ -#define R8A7790_PD_ALWAYS_ON 32 - -#endif /* __DT_BINDINGS_POWER_R8A7790_SYSC_H__ */ diff --git a/sys/gnu/dts/include/dt-bindings/power/r8a7791-sysc.h b/sys/gnu/dts/include/dt-bindings/power/r8a7791-sysc.h deleted file mode 100644 index 1d20fae4242..00000000000 --- a/sys/gnu/dts/include/dt-bindings/power/r8a7791-sysc.h +++ /dev/null @@ -1,23 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) 2016 Glider bvba - */ -#ifndef __DT_BINDINGS_POWER_R8A7791_SYSC_H__ -#define __DT_BINDINGS_POWER_R8A7791_SYSC_H__ - -/* - * These power domain indices match the numbers of the interrupt bits - * representing the power areas in the various Interrupt Registers - * (e.g. SYSCISR, Interrupt Status Register) - */ - -#define R8A7791_PD_CA15_CPU0 0 -#define R8A7791_PD_CA15_CPU1 1 -#define R8A7791_PD_CA15_SCU 12 -#define R8A7791_PD_SH_4A 16 -#define R8A7791_PD_SGX 20 - -/* Always-on power area */ -#define R8A7791_PD_ALWAYS_ON 32 - -#endif /* __DT_BINDINGS_POWER_R8A7791_SYSC_H__ */ diff --git a/sys/gnu/dts/include/dt-bindings/power/r8a7792-sysc.h b/sys/gnu/dts/include/dt-bindings/power/r8a7792-sysc.h deleted file mode 100644 index dd3a4667ca1..00000000000 --- a/sys/gnu/dts/include/dt-bindings/power/r8a7792-sysc.h +++ /dev/null @@ -1,23 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) 2016 Cogent Embedded Inc. - */ -#ifndef __DT_BINDINGS_POWER_R8A7792_SYSC_H__ -#define __DT_BINDINGS_POWER_R8A7792_SYSC_H__ - -/* - * These power domain indices match the numbers of the interrupt bits - * representing the power areas in the various Interrupt Registers - * (e.g. SYSCISR, Interrupt Status Register) - */ - -#define R8A7792_PD_CA15_CPU0 0 -#define R8A7792_PD_CA15_CPU1 1 -#define R8A7792_PD_CA15_SCU 12 -#define R8A7792_PD_SGX 20 -#define R8A7792_PD_IMP 24 - -/* Always-on power area */ -#define R8A7792_PD_ALWAYS_ON 32 - -#endif /* __DT_BINDINGS_POWER_R8A7792_SYSC_H__ */ diff --git a/sys/gnu/dts/include/dt-bindings/power/r8a7793-sysc.h b/sys/gnu/dts/include/dt-bindings/power/r8a7793-sysc.h deleted file mode 100644 index 056998c635a..00000000000 --- a/sys/gnu/dts/include/dt-bindings/power/r8a7793-sysc.h +++ /dev/null @@ -1,25 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) 2016 Glider bvba - */ -#ifndef __DT_BINDINGS_POWER_R8A7793_SYSC_H__ -#define __DT_BINDINGS_POWER_R8A7793_SYSC_H__ - -/* - * These power domain indices match the numbers of the interrupt bits - * representing the power areas in the various Interrupt Registers - * (e.g. SYSCISR, Interrupt Status Register) - * - * Note that R-Car M2-N is identical to R-Car M2-W w.r.t. power domains. - */ - -#define R8A7793_PD_CA15_CPU0 0 -#define R8A7793_PD_CA15_CPU1 1 -#define R8A7793_PD_CA15_SCU 12 -#define R8A7793_PD_SH_4A 16 -#define R8A7793_PD_SGX 20 - -/* Always-on power area */ -#define R8A7793_PD_ALWAYS_ON 32 - -#endif /* __DT_BINDINGS_POWER_R8A7793_SYSC_H__ */ diff --git a/sys/gnu/dts/include/dt-bindings/power/r8a7794-sysc.h b/sys/gnu/dts/include/dt-bindings/power/r8a7794-sysc.h deleted file mode 100644 index 4d6c708e6f3..00000000000 --- a/sys/gnu/dts/include/dt-bindings/power/r8a7794-sysc.h +++ /dev/null @@ -1,23 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) 2016 Glider bvba - */ -#ifndef __DT_BINDINGS_POWER_R8A7794_SYSC_H__ -#define __DT_BINDINGS_POWER_R8A7794_SYSC_H__ - -/* - * These power domain indices match the numbers of the interrupt bits - * representing the power areas in the various Interrupt Registers - * (e.g. SYSCISR, Interrupt Status Register) - */ - -#define R8A7794_PD_CA7_CPU0 5 -#define R8A7794_PD_CA7_CPU1 6 -#define R8A7794_PD_SH_4A 16 -#define R8A7794_PD_SGX 20 -#define R8A7794_PD_CA7_SCU 21 - -/* Always-on power area */ -#define R8A7794_PD_ALWAYS_ON 32 - -#endif /* __DT_BINDINGS_POWER_R8A7794_SYSC_H__ */ diff --git a/sys/gnu/dts/include/dt-bindings/power/r8a7795-sysc.h b/sys/gnu/dts/include/dt-bindings/power/r8a7795-sysc.h deleted file mode 100644 index eea6ad69f0b..00000000000 --- a/sys/gnu/dts/include/dt-bindings/power/r8a7795-sysc.h +++ /dev/null @@ -1,39 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) 2016 Glider bvba - */ -#ifndef __DT_BINDINGS_POWER_R8A7795_SYSC_H__ -#define __DT_BINDINGS_POWER_R8A7795_SYSC_H__ - -/* - * These power domain indices match the numbers of the interrupt bits - * representing the power areas in the various Interrupt Registers - * (e.g. SYSCISR, Interrupt Status Register) - */ - -#define R8A7795_PD_CA57_CPU0 0 -#define R8A7795_PD_CA57_CPU1 1 -#define R8A7795_PD_CA57_CPU2 2 -#define R8A7795_PD_CA57_CPU3 3 -#define R8A7795_PD_CA53_CPU0 5 -#define R8A7795_PD_CA53_CPU1 6 -#define R8A7795_PD_CA53_CPU2 7 -#define R8A7795_PD_CA53_CPU3 8 -#define R8A7795_PD_A3VP 9 -#define R8A7795_PD_CA57_SCU 12 -#define R8A7795_PD_CR7 13 -#define R8A7795_PD_A3VC 14 -#define R8A7795_PD_3DG_A 17 -#define R8A7795_PD_3DG_B 18 -#define R8A7795_PD_3DG_C 19 -#define R8A7795_PD_3DG_D 20 -#define R8A7795_PD_CA53_SCU 21 -#define R8A7795_PD_3DG_E 22 -#define R8A7795_PD_A3IR 24 -#define R8A7795_PD_A2VC0 25 /* ES1.x only */ -#define R8A7795_PD_A2VC1 26 - -/* Always-on power area */ -#define R8A7795_PD_ALWAYS_ON 32 - -#endif /* __DT_BINDINGS_POWER_R8A7795_SYSC_H__ */ diff --git a/sys/gnu/dts/include/dt-bindings/power/r8a7796-sysc.h b/sys/gnu/dts/include/dt-bindings/power/r8a7796-sysc.h deleted file mode 100644 index 7e6fc06ebff..00000000000 --- a/sys/gnu/dts/include/dt-bindings/power/r8a7796-sysc.h +++ /dev/null @@ -1,33 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) 2016 Glider bvba - */ -#ifndef __DT_BINDINGS_POWER_R8A7796_SYSC_H__ -#define __DT_BINDINGS_POWER_R8A7796_SYSC_H__ - -/* - * These power domain indices match the numbers of the interrupt bits - * representing the power areas in the various Interrupt Registers - * (e.g. SYSCISR, Interrupt Status Register) - */ - -#define R8A7796_PD_CA57_CPU0 0 -#define R8A7796_PD_CA57_CPU1 1 -#define R8A7796_PD_CA53_CPU0 5 -#define R8A7796_PD_CA53_CPU1 6 -#define R8A7796_PD_CA53_CPU2 7 -#define R8A7796_PD_CA53_CPU3 8 -#define R8A7796_PD_CA57_SCU 12 -#define R8A7796_PD_CR7 13 -#define R8A7796_PD_A3VC 14 -#define R8A7796_PD_3DG_A 17 -#define R8A7796_PD_3DG_B 18 -#define R8A7796_PD_CA53_SCU 21 -#define R8A7796_PD_A3IR 24 -#define R8A7796_PD_A2VC0 25 -#define R8A7796_PD_A2VC1 26 - -/* Always-on power area */ -#define R8A7796_PD_ALWAYS_ON 32 - -#endif /* __DT_BINDINGS_POWER_R8A7796_SYSC_H__ */ diff --git a/sys/gnu/dts/include/dt-bindings/power/r8a77961-sysc.h b/sys/gnu/dts/include/dt-bindings/power/r8a77961-sysc.h deleted file mode 100644 index 7a3800996f7..00000000000 --- a/sys/gnu/dts/include/dt-bindings/power/r8a77961-sysc.h +++ /dev/null @@ -1,32 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) 2019 Glider bvba - */ -#ifndef __DT_BINDINGS_POWER_R8A77961_SYSC_H__ -#define __DT_BINDINGS_POWER_R8A77961_SYSC_H__ - -/* - * These power domain indices match the numbers of the interrupt bits - * representing the power areas in the various Interrupt Registers - * (e.g. SYSCISR, Interrupt Status Register) - */ - -#define R8A77961_PD_CA57_CPU0 0 -#define R8A77961_PD_CA57_CPU1 1 -#define R8A77961_PD_CA53_CPU0 5 -#define R8A77961_PD_CA53_CPU1 6 -#define R8A77961_PD_CA53_CPU2 7 -#define R8A77961_PD_CA53_CPU3 8 -#define R8A77961_PD_CA57_SCU 12 -#define R8A77961_PD_CR7 13 -#define R8A77961_PD_A3VC 14 -#define R8A77961_PD_3DG_A 17 -#define R8A77961_PD_3DG_B 18 -#define R8A77961_PD_CA53_SCU 21 -#define R8A77961_PD_A3IR 24 -#define R8A77961_PD_A2VC1 26 - -/* Always-on power area */ -#define R8A77961_PD_ALWAYS_ON 32 - -#endif /* __DT_BINDINGS_POWER_R8A77961_SYSC_H__ */ diff --git a/sys/gnu/dts/include/dt-bindings/power/r8a77965-sysc.h b/sys/gnu/dts/include/dt-bindings/power/r8a77965-sysc.h deleted file mode 100644 index de82d8a15ea..00000000000 --- a/sys/gnu/dts/include/dt-bindings/power/r8a77965-sysc.h +++ /dev/null @@ -1,29 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2018 Jacopo Mondi - * Copyright (C) 2016 Glider bvba - */ - -#ifndef __DT_BINDINGS_POWER_R8A77965_SYSC_H__ -#define __DT_BINDINGS_POWER_R8A77965_SYSC_H__ - -/* - * These power domain indices match the numbers of the interrupt bits - * representing the power areas in the various Interrupt Registers - * (e.g. SYSCISR, Interrupt Status Register) - */ - -#define R8A77965_PD_CA57_CPU0 0 -#define R8A77965_PD_CA57_CPU1 1 -#define R8A77965_PD_A3VP 9 -#define R8A77965_PD_CA57_SCU 12 -#define R8A77965_PD_CR7 13 -#define R8A77965_PD_A3VC 14 -#define R8A77965_PD_3DG_A 17 -#define R8A77965_PD_3DG_B 18 -#define R8A77965_PD_A2VC1 26 - -/* Always-on power area */ -#define R8A77965_PD_ALWAYS_ON 32 - -#endif /* __DT_BINDINGS_POWER_R8A77965_SYSC_H__ */ diff --git a/sys/gnu/dts/include/dt-bindings/power/r8a77970-sysc.h b/sys/gnu/dts/include/dt-bindings/power/r8a77970-sysc.h deleted file mode 100644 index 9dcdbd5a930..00000000000 --- a/sys/gnu/dts/include/dt-bindings/power/r8a77970-sysc.h +++ /dev/null @@ -1,28 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) 2017 Cogent Embedded Inc. - */ -#ifndef __DT_BINDINGS_POWER_R8A77970_SYSC_H__ -#define __DT_BINDINGS_POWER_R8A77970_SYSC_H__ - -/* - * These power domain indices match the numbers of the interrupt bits - * representing the power areas in the various Interrupt Registers - * (e.g. SYSCISR, Interrupt Status Register) - */ - -#define R8A77970_PD_CA53_CPU0 5 -#define R8A77970_PD_CA53_CPU1 6 -#define R8A77970_PD_CA53_SCU 21 -#define R8A77970_PD_A2IR0 23 -#define R8A77970_PD_A3IR 24 -#define R8A77970_PD_A2IR1 27 -#define R8A77970_PD_A2DP 28 -#define R8A77970_PD_A2CN 29 -#define R8A77970_PD_A2SC0 30 -#define R8A77970_PD_A2SC1 31 - -/* Always-on power area */ -#define R8A77970_PD_ALWAYS_ON 32 - -#endif /* __DT_BINDINGS_POWER_R8A77970_SYSC_H__ */ diff --git a/sys/gnu/dts/include/dt-bindings/power/r8a77980-sysc.h b/sys/gnu/dts/include/dt-bindings/power/r8a77980-sysc.h deleted file mode 100644 index e12c8587b87..00000000000 --- a/sys/gnu/dts/include/dt-bindings/power/r8a77980-sysc.h +++ /dev/null @@ -1,43 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 - * - * Copyright (C) 2018 Renesas Electronics Corp. - * Copyright (C) 2018 Cogent Embedded, Inc. - */ -#ifndef __DT_BINDINGS_POWER_R8A77980_SYSC_H__ -#define __DT_BINDINGS_POWER_R8A77980_SYSC_H__ - -/* - * These power domain indices match the numbers of the interrupt bits - * representing the power areas in the various Interrupt Registers - * (e.g. SYSCISR, Interrupt Status Register) - */ - -#define R8A77980_PD_A2SC2 0 -#define R8A77980_PD_A2SC3 1 -#define R8A77980_PD_A2SC4 2 -#define R8A77980_PD_A2DP0 3 -#define R8A77980_PD_A2DP1 4 -#define R8A77980_PD_CA53_CPU0 5 -#define R8A77980_PD_CA53_CPU1 6 -#define R8A77980_PD_CA53_CPU2 7 -#define R8A77980_PD_CA53_CPU3 8 -#define R8A77980_PD_A2CN 10 -#define R8A77980_PD_A3VIP0 11 -#define R8A77980_PD_A2IR5 12 -#define R8A77980_PD_CR7 13 -#define R8A77980_PD_A2IR4 15 -#define R8A77980_PD_CA53_SCU 21 -#define R8A77980_PD_A2IR0 23 -#define R8A77980_PD_A3IR 24 -#define R8A77980_PD_A3VIP1 25 -#define R8A77980_PD_A3VIP2 26 -#define R8A77980_PD_A2IR1 27 -#define R8A77980_PD_A2IR2 28 -#define R8A77980_PD_A2IR3 29 -#define R8A77980_PD_A2SC0 30 -#define R8A77980_PD_A2SC1 31 - -/* Always-on power area */ -#define R8A77980_PD_ALWAYS_ON 32 - -#endif /* __DT_BINDINGS_POWER_R8A77980_SYSC_H__ */ diff --git a/sys/gnu/dts/include/dt-bindings/power/r8a77990-sysc.h b/sys/gnu/dts/include/dt-bindings/power/r8a77990-sysc.h deleted file mode 100644 index 944d85beec1..00000000000 --- a/sys/gnu/dts/include/dt-bindings/power/r8a77990-sysc.h +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2018 Renesas Electronics Corp. - */ -#ifndef __DT_BINDINGS_POWER_R8A77990_SYSC_H__ -#define __DT_BINDINGS_POWER_R8A77990_SYSC_H__ - -/* - * These power domain indices match the numbers of the interrupt bits - * representing the power areas in the various Interrupt Registers - * (e.g. SYSCISR, Interrupt Status Register) - */ - -#define R8A77990_PD_CA53_CPU0 5 -#define R8A77990_PD_CA53_CPU1 6 -#define R8A77990_PD_CR7 13 -#define R8A77990_PD_A3VC 14 -#define R8A77990_PD_3DG_A 17 -#define R8A77990_PD_3DG_B 18 -#define R8A77990_PD_CA53_SCU 21 -#define R8A77990_PD_A2VC1 26 - -/* Always-on power area */ -#define R8A77990_PD_ALWAYS_ON 32 - -#endif /* __DT_BINDINGS_POWER_R8A77990_SYSC_H__ */ diff --git a/sys/gnu/dts/include/dt-bindings/power/r8a77995-sysc.h b/sys/gnu/dts/include/dt-bindings/power/r8a77995-sysc.h deleted file mode 100644 index f2b35502f2b..00000000000 --- a/sys/gnu/dts/include/dt-bindings/power/r8a77995-sysc.h +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) 2017 Glider bvba - */ -#ifndef __DT_BINDINGS_POWER_R8A77995_SYSC_H__ -#define __DT_BINDINGS_POWER_R8A77995_SYSC_H__ - -/* - * These power domain indices match the numbers of the interrupt bits - * representing the power areas in the various Interrupt Registers - * (e.g. SYSCISR, Interrupt Status Register) - */ - -#define R8A77995_PD_CA53_CPU0 5 -#define R8A77995_PD_CA53_SCU 21 - -/* Always-on power area */ -#define R8A77995_PD_ALWAYS_ON 32 - -#endif /* __DT_BINDINGS_POWER_R8A77995_SYSC_H__ */ diff --git a/sys/gnu/dts/include/dt-bindings/power/raspberrypi-power.h b/sys/gnu/dts/include/dt-bindings/power/raspberrypi-power.h deleted file mode 100644 index 3575f9f4b0b..00000000000 --- a/sys/gnu/dts/include/dt-bindings/power/raspberrypi-power.h +++ /dev/null @@ -1,38 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright © 2015 Broadcom - */ - -#ifndef _DT_BINDINGS_ARM_BCM2835_RPI_POWER_H -#define _DT_BINDINGS_ARM_BCM2835_RPI_POWER_H - -/* These power domain indices are the firmware interface's indices - * minus one. - */ -#define RPI_POWER_DOMAIN_I2C0 0 -#define RPI_POWER_DOMAIN_I2C1 1 -#define RPI_POWER_DOMAIN_I2C2 2 -#define RPI_POWER_DOMAIN_VIDEO_SCALER 3 -#define RPI_POWER_DOMAIN_VPU1 4 -#define RPI_POWER_DOMAIN_HDMI 5 -#define RPI_POWER_DOMAIN_USB 6 -#define RPI_POWER_DOMAIN_VEC 7 -#define RPI_POWER_DOMAIN_JPEG 8 -#define RPI_POWER_DOMAIN_H264 9 -#define RPI_POWER_DOMAIN_V3D 10 -#define RPI_POWER_DOMAIN_ISP 11 -#define RPI_POWER_DOMAIN_UNICAM0 12 -#define RPI_POWER_DOMAIN_UNICAM1 13 -#define RPI_POWER_DOMAIN_CCP2RX 14 -#define RPI_POWER_DOMAIN_CSI2 15 -#define RPI_POWER_DOMAIN_CPI 16 -#define RPI_POWER_DOMAIN_DSI0 17 -#define RPI_POWER_DOMAIN_DSI1 18 -#define RPI_POWER_DOMAIN_TRANSPOSER 19 -#define RPI_POWER_DOMAIN_CCP2TX 20 -#define RPI_POWER_DOMAIN_CDP 21 -#define RPI_POWER_DOMAIN_ARM 22 - -#define RPI_POWER_DOMAIN_COUNT 23 - -#endif /* _DT_BINDINGS_ARM_BCM2835_RPI_POWER_H */ diff --git a/sys/gnu/dts/include/dt-bindings/power/rk3036-power.h b/sys/gnu/dts/include/dt-bindings/power/rk3036-power.h deleted file mode 100644 index 0bc6b5d5075..00000000000 --- a/sys/gnu/dts/include/dt-bindings/power/rk3036-power.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __DT_BINDINGS_POWER_RK3036_POWER_H__ -#define __DT_BINDINGS_POWER_RK3036_POWER_H__ - -#define RK3036_PD_MSCH 0 -#define RK3036_PD_CORE 1 -#define RK3036_PD_PERI 2 -#define RK3036_PD_VIO 3 -#define RK3036_PD_VPU 4 -#define RK3036_PD_GPU 5 -#define RK3036_PD_SYS 6 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/power/rk3066-power.h b/sys/gnu/dts/include/dt-bindings/power/rk3066-power.h deleted file mode 100644 index acf9f310ac5..00000000000 --- a/sys/gnu/dts/include/dt-bindings/power/rk3066-power.h +++ /dev/null @@ -1,22 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __DT_BINDINGS_POWER_RK3066_POWER_H__ -#define __DT_BINDINGS_POWER_RK3066_POWER_H__ - -/* VD_CORE */ -#define RK3066_PD_A9_0 0 -#define RK3066_PD_A9_1 1 -#define RK3066_PD_DBG 4 -#define RK3066_PD_SCU 5 - -/* VD_LOGIC */ -#define RK3066_PD_VIDEO 6 -#define RK3066_PD_VIO 7 -#define RK3066_PD_GPU 8 -#define RK3066_PD_PERI 9 -#define RK3066_PD_CPU 10 -#define RK3066_PD_ALIVE 11 - -/* VD_PMU */ -#define RK3066_PD_RTC 12 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/power/rk3128-power.h b/sys/gnu/dts/include/dt-bindings/power/rk3128-power.h deleted file mode 100644 index c051dc3108d..00000000000 --- a/sys/gnu/dts/include/dt-bindings/power/rk3128-power.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __DT_BINDINGS_POWER_RK3128_POWER_H__ -#define __DT_BINDINGS_POWER_RK3128_POWER_H__ - -/* VD_CORE */ -#define RK3128_PD_CORE 0 - -/* VD_LOGIC */ -#define RK3128_PD_VIO 1 -#define RK3128_PD_VIDEO 2 -#define RK3128_PD_GPU 3 -#define RK3128_PD_MSCH 4 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/power/rk3188-power.h b/sys/gnu/dts/include/dt-bindings/power/rk3188-power.h deleted file mode 100644 index 93d23dfba33..00000000000 --- a/sys/gnu/dts/include/dt-bindings/power/rk3188-power.h +++ /dev/null @@ -1,24 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __DT_BINDINGS_POWER_RK3188_POWER_H__ -#define __DT_BINDINGS_POWER_RK3188_POWER_H__ - -/* VD_CORE */ -#define RK3188_PD_A9_0 0 -#define RK3188_PD_A9_1 1 -#define RK3188_PD_A9_2 2 -#define RK3188_PD_A9_3 3 -#define RK3188_PD_DBG 4 -#define RK3188_PD_SCU 5 - -/* VD_LOGIC */ -#define RK3188_PD_VIDEO 6 -#define RK3188_PD_VIO 7 -#define RK3188_PD_GPU 8 -#define RK3188_PD_PERI 9 -#define RK3188_PD_CPU 10 -#define RK3188_PD_ALIVE 11 - -/* VD_PMU */ -#define RK3188_PD_RTC 12 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/power/rk3228-power.h b/sys/gnu/dts/include/dt-bindings/power/rk3228-power.h deleted file mode 100644 index 6a8dc1bf76c..00000000000 --- a/sys/gnu/dts/include/dt-bindings/power/rk3228-power.h +++ /dev/null @@ -1,21 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __DT_BINDINGS_POWER_RK3228_POWER_H__ -#define __DT_BINDINGS_POWER_RK3228_POWER_H__ - -/** - * RK3228 idle id Summary. - */ - -#define RK3228_PD_CORE 0 -#define RK3228_PD_MSCH 1 -#define RK3228_PD_BUS 2 -#define RK3228_PD_SYS 3 -#define RK3228_PD_VIO 4 -#define RK3228_PD_VOP 5 -#define RK3228_PD_VPU 6 -#define RK3228_PD_RKVDEC 7 -#define RK3228_PD_GPU 8 -#define RK3228_PD_PERI 9 -#define RK3228_PD_GMAC 10 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/power/rk3288-power.h b/sys/gnu/dts/include/dt-bindings/power/rk3288-power.h deleted file mode 100644 index f710b56ccd8..00000000000 --- a/sys/gnu/dts/include/dt-bindings/power/rk3288-power.h +++ /dev/null @@ -1,32 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __DT_BINDINGS_POWER_RK3288_POWER_H__ -#define __DT_BINDINGS_POWER_RK3288_POWER_H__ - -/** - * RK3288 Power Domain and Voltage Domain Summary. - */ - -/* VD_CORE */ -#define RK3288_PD_A17_0 0 -#define RK3288_PD_A17_1 1 -#define RK3288_PD_A17_2 2 -#define RK3288_PD_A17_3 3 -#define RK3288_PD_SCU 4 -#define RK3288_PD_DEBUG 5 -#define RK3288_PD_MEM 6 - -/* VD_LOGIC */ -#define RK3288_PD_BUS 7 -#define RK3288_PD_PERI 8 -#define RK3288_PD_VIO 9 -#define RK3288_PD_ALIVE 10 -#define RK3288_PD_HEVC 11 -#define RK3288_PD_VIDEO 12 - -/* VD_GPU */ -#define RK3288_PD_GPU 13 - -/* VD_PMU */ -#define RK3288_PD_PMU 14 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/power/rk3328-power.h b/sys/gnu/dts/include/dt-bindings/power/rk3328-power.h deleted file mode 100644 index 02e3d7fc1cc..00000000000 --- a/sys/gnu/dts/include/dt-bindings/power/rk3328-power.h +++ /dev/null @@ -1,19 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __DT_BINDINGS_POWER_RK3328_POWER_H__ -#define __DT_BINDINGS_POWER_RK3328_POWER_H__ - -/** - * RK3328 idle id Summary. - */ -#define RK3328_PD_CORE 0 -#define RK3328_PD_GPU 1 -#define RK3328_PD_BUS 2 -#define RK3328_PD_MSCH 3 -#define RK3328_PD_PERI 4 -#define RK3328_PD_VIDEO 5 -#define RK3328_PD_HEVC 6 -#define RK3328_PD_SYS 7 -#define RK3328_PD_VPU 8 -#define RK3328_PD_VIO 9 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/power/rk3366-power.h b/sys/gnu/dts/include/dt-bindings/power/rk3366-power.h deleted file mode 100644 index 223a3dce049..00000000000 --- a/sys/gnu/dts/include/dt-bindings/power/rk3366-power.h +++ /dev/null @@ -1,24 +0,0 @@ -#ifndef __DT_BINDINGS_POWER_RK3366_POWER_H__ -#define __DT_BINDINGS_POWER_RK3366_POWER_H__ - -/* VD_CORE */ -#define RK3366_PD_A53_0 0 -#define RK3366_PD_A53_1 1 -#define RK3366_PD_A53_2 2 -#define RK3366_PD_A53_3 3 - -/* VD_LOGIC */ -#define RK3366_PD_BUS 4 -#define RK3366_PD_PERI 5 -#define RK3366_PD_VIO 6 -#define RK3366_PD_VIDEO 7 -#define RK3366_PD_RKVDEC 8 -#define RK3366_PD_WIFIBT 9 -#define RK3366_PD_VPU 10 -#define RK3366_PD_GPU 11 -#define RK3366_PD_ALIVE 12 - -/* VD_PMU */ -#define RK3366_PD_PMU 13 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/power/rk3368-power.h b/sys/gnu/dts/include/dt-bindings/power/rk3368-power.h deleted file mode 100644 index 5e602dbd64e..00000000000 --- a/sys/gnu/dts/include/dt-bindings/power/rk3368-power.h +++ /dev/null @@ -1,29 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __DT_BINDINGS_POWER_RK3368_POWER_H__ -#define __DT_BINDINGS_POWER_RK3368_POWER_H__ - -/* VD_CORE */ -#define RK3368_PD_A53_L0 0 -#define RK3368_PD_A53_L1 1 -#define RK3368_PD_A53_L2 2 -#define RK3368_PD_A53_L3 3 -#define RK3368_PD_SCU_L 4 -#define RK3368_PD_A53_B0 5 -#define RK3368_PD_A53_B1 6 -#define RK3368_PD_A53_B2 7 -#define RK3368_PD_A53_B3 8 -#define RK3368_PD_SCU_B 9 - -/* VD_LOGIC */ -#define RK3368_PD_BUS 10 -#define RK3368_PD_PERI 11 -#define RK3368_PD_VIO 12 -#define RK3368_PD_ALIVE 13 -#define RK3368_PD_VIDEO 14 -#define RK3368_PD_GPU_0 15 -#define RK3368_PD_GPU_1 16 - -/* VD_PMU */ -#define RK3368_PD_PMU 17 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/power/rk3399-power.h b/sys/gnu/dts/include/dt-bindings/power/rk3399-power.h deleted file mode 100644 index aedd8b180fe..00000000000 --- a/sys/gnu/dts/include/dt-bindings/power/rk3399-power.h +++ /dev/null @@ -1,54 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __DT_BINDINGS_POWER_RK3399_POWER_H__ -#define __DT_BINDINGS_POWER_RK3399_POWER_H__ - -/* VD_CORE_L */ -#define RK3399_PD_A53_L0 0 -#define RK3399_PD_A53_L1 1 -#define RK3399_PD_A53_L2 2 -#define RK3399_PD_A53_L3 3 -#define RK3399_PD_SCU_L 4 - -/* VD_CORE_B */ -#define RK3399_PD_A72_B0 5 -#define RK3399_PD_A72_B1 6 -#define RK3399_PD_SCU_B 7 - -/* VD_LOGIC */ -#define RK3399_PD_TCPD0 8 -#define RK3399_PD_TCPD1 9 -#define RK3399_PD_CCI 10 -#define RK3399_PD_CCI0 11 -#define RK3399_PD_CCI1 12 -#define RK3399_PD_PERILP 13 -#define RK3399_PD_PERIHP 14 -#define RK3399_PD_VIO 15 -#define RK3399_PD_VO 16 -#define RK3399_PD_VOPB 17 -#define RK3399_PD_VOPL 18 -#define RK3399_PD_ISP0 19 -#define RK3399_PD_ISP1 20 -#define RK3399_PD_HDCP 21 -#define RK3399_PD_GMAC 22 -#define RK3399_PD_EMMC 23 -#define RK3399_PD_USB3 24 -#define RK3399_PD_EDP 25 -#define RK3399_PD_GIC 26 -#define RK3399_PD_SD 27 -#define RK3399_PD_SDIOAUDIO 28 -#define RK3399_PD_ALIVE 29 - -/* VD_CENTER */ -#define RK3399_PD_CENTER 30 -#define RK3399_PD_VCODEC 31 -#define RK3399_PD_VDU 32 -#define RK3399_PD_RGA 33 -#define RK3399_PD_IEP 34 - -/* VD_GPU */ -#define RK3399_PD_GPU 35 - -/* VD_PMU */ -#define RK3399_PD_PMU 36 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/power/tegra186-powergate.h b/sys/gnu/dts/include/dt-bindings/power/tegra186-powergate.h deleted file mode 100644 index 31fd3f90018..00000000000 --- a/sys/gnu/dts/include/dt-bindings/power/tegra186-powergate.h +++ /dev/null @@ -1,28 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved. - */ - -#ifndef _DT_BINDINGS_POWER_TEGRA186_POWERGATE_H -#define _DT_BINDINGS_POWER_TEGRA186_POWERGATE_H - -#define TEGRA186_POWER_DOMAIN_AUD 0 -#define TEGRA186_POWER_DOMAIN_DFD 1 -#define TEGRA186_POWER_DOMAIN_DISP 2 -#define TEGRA186_POWER_DOMAIN_DISPB 3 -#define TEGRA186_POWER_DOMAIN_DISPC 4 -#define TEGRA186_POWER_DOMAIN_ISPA 5 -#define TEGRA186_POWER_DOMAIN_NVDEC 6 -#define TEGRA186_POWER_DOMAIN_NVJPG 7 -#define TEGRA186_POWER_DOMAIN_MPE 8 -#define TEGRA186_POWER_DOMAIN_PCX 9 -#define TEGRA186_POWER_DOMAIN_SAX 10 -#define TEGRA186_POWER_DOMAIN_VE 11 -#define TEGRA186_POWER_DOMAIN_VIC 12 -#define TEGRA186_POWER_DOMAIN_XUSBA 13 -#define TEGRA186_POWER_DOMAIN_XUSBB 14 -#define TEGRA186_POWER_DOMAIN_XUSBC 15 -#define TEGRA186_POWER_DOMAIN_GPU 43 -#define TEGRA186_POWER_DOMAIN_MAX 44 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/power/tegra194-powergate.h b/sys/gnu/dts/include/dt-bindings/power/tegra194-powergate.h deleted file mode 100644 index 82253742a49..00000000000 --- a/sys/gnu/dts/include/dt-bindings/power/tegra194-powergate.h +++ /dev/null @@ -1,35 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. */ - -#ifndef __ABI_MACH_T194_POWERGATE_T194_H_ -#define __ABI_MACH_T194_POWERGATE_T194_H_ - -#define TEGRA194_POWER_DOMAIN_AUD 1 -#define TEGRA194_POWER_DOMAIN_DISP 2 -#define TEGRA194_POWER_DOMAIN_DISPB 3 -#define TEGRA194_POWER_DOMAIN_DISPC 4 -#define TEGRA194_POWER_DOMAIN_ISPA 5 -#define TEGRA194_POWER_DOMAIN_NVDECA 6 -#define TEGRA194_POWER_DOMAIN_NVJPG 7 -#define TEGRA194_POWER_DOMAIN_NVENCA 8 -#define TEGRA194_POWER_DOMAIN_NVENCB 9 -#define TEGRA194_POWER_DOMAIN_NVDECB 10 -#define TEGRA194_POWER_DOMAIN_SAX 11 -#define TEGRA194_POWER_DOMAIN_VE 12 -#define TEGRA194_POWER_DOMAIN_VIC 13 -#define TEGRA194_POWER_DOMAIN_XUSBA 14 -#define TEGRA194_POWER_DOMAIN_XUSBB 15 -#define TEGRA194_POWER_DOMAIN_XUSBC 16 -#define TEGRA194_POWER_DOMAIN_PCIEX8A 17 -#define TEGRA194_POWER_DOMAIN_PCIEX4A 18 -#define TEGRA194_POWER_DOMAIN_PCIEX1A 19 -#define TEGRA194_POWER_DOMAIN_PCIEX8B 21 -#define TEGRA194_POWER_DOMAIN_PVAA 22 -#define TEGRA194_POWER_DOMAIN_PVAB 23 -#define TEGRA194_POWER_DOMAIN_DLAA 24 -#define TEGRA194_POWER_DOMAIN_DLAB 25 -#define TEGRA194_POWER_DOMAIN_CV 26 -#define TEGRA194_POWER_DOMAIN_GPU 27 -#define TEGRA194_POWER_DOMAIN_MAX 27 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/power/xlnx-zynqmp-power.h b/sys/gnu/dts/include/dt-bindings/power/xlnx-zynqmp-power.h deleted file mode 100644 index 0d9a412fd5e..00000000000 --- a/sys/gnu/dts/include/dt-bindings/power/xlnx-zynqmp-power.h +++ /dev/null @@ -1,39 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2018 Xilinx, Inc. - */ - -#ifndef _DT_BINDINGS_ZYNQMP_POWER_H -#define _DT_BINDINGS_ZYNQMP_POWER_H - -#define PD_USB_0 22 -#define PD_USB_1 23 -#define PD_TTC_0 24 -#define PD_TTC_1 25 -#define PD_TTC_2 26 -#define PD_TTC_3 27 -#define PD_SATA 28 -#define PD_ETH_0 29 -#define PD_ETH_1 30 -#define PD_ETH_2 31 -#define PD_ETH_3 32 -#define PD_UART_0 33 -#define PD_UART_1 34 -#define PD_SPI_0 35 -#define PD_SPI_1 36 -#define PD_I2C_0 37 -#define PD_I2C_1 38 -#define PD_SD_0 39 -#define PD_SD_1 40 -#define PD_DP 41 -#define PD_GDMA 42 -#define PD_ADMA 43 -#define PD_NAND 44 -#define PD_QSPI 45 -#define PD_GPIO 46 -#define PD_CAN_0 47 -#define PD_CAN_1 48 -#define PD_GPU 58 -#define PD_PCIE 59 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/pwm/pwm.h b/sys/gnu/dts/include/dt-bindings/pwm/pwm.h deleted file mode 100644 index ab9a077e3c7..00000000000 --- a/sys/gnu/dts/include/dt-bindings/pwm/pwm.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides constants for most PWM bindings. - * - * Most PWM bindings can include a flags cell as part of the PWM specifier. - * In most cases, the format of the flags cell uses the standard values - * defined in this header. - */ - -#ifndef _DT_BINDINGS_PWM_PWM_H -#define _DT_BINDINGS_PWM_PWM_H - -#define PWM_POLARITY_INVERTED (1 << 0) - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/regulator/active-semi,8865-regulator.h b/sys/gnu/dts/include/dt-bindings/regulator/active-semi,8865-regulator.h deleted file mode 100644 index 15473dbeaf3..00000000000 --- a/sys/gnu/dts/include/dt-bindings/regulator/active-semi,8865-regulator.h +++ /dev/null @@ -1,28 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Device Tree binding constants for the ACT8865 PMIC regulators - */ - -#ifndef _DT_BINDINGS_REGULATOR_ACT8865_H -#define _DT_BINDINGS_REGULATOR_ACT8865_H - -/* - * These constants should be used to specify regulator modes in device tree for - * ACT8865 regulators as follows: - * ACT8865_REGULATOR_MODE_FIXED: It is specific to DCDC regulators and it - * specifies the usage of fixed-frequency - * PWM. - * - * ACT8865_REGULATOR_MODE_NORMAL: It is specific to LDO regulators and it - * specifies the usage of normal mode. - * - * ACT8865_REGULATOR_MODE_LOWPOWER: For DCDC and LDO regulators; it specify - * the usage of proprietary power-saving - * mode. - */ - -#define ACT8865_REGULATOR_MODE_FIXED 1 -#define ACT8865_REGULATOR_MODE_NORMAL 2 -#define ACT8865_REGULATOR_MODE_LOWPOWER 3 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/regulator/active-semi,8945a-regulator.h b/sys/gnu/dts/include/dt-bindings/regulator/active-semi,8945a-regulator.h deleted file mode 100644 index 9bdba5e3141..00000000000 --- a/sys/gnu/dts/include/dt-bindings/regulator/active-semi,8945a-regulator.h +++ /dev/null @@ -1,30 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2018 Microchip Technology, Inc. All rights reserved. - * - * Device Tree binding constants for the ACT8945A PMIC regulators - */ - -#ifndef _DT_BINDINGS_REGULATOR_ACT8945A_H -#define _DT_BINDINGS_REGULATOR_ACT8945A_H - -/* - * These constants should be used to specify regulator modes in device tree for - * ACT8945A regulators as follows: - * ACT8945A_REGULATOR_MODE_FIXED: It is specific to DCDC regulators and it - * specifies the usage of fixed-frequency - * PWM. - * - * ACT8945A_REGULATOR_MODE_NORMAL: It is specific to LDO regulators and it - * specifies the usage of normal mode. - * - * ACT8945A_REGULATOR_MODE_LOWPOWER: For DCDC and LDO regulators; it specify - * the usage of proprietary power-saving - * mode. - */ - -#define ACT8945A_REGULATOR_MODE_FIXED 1 -#define ACT8945A_REGULATOR_MODE_NORMAL 2 -#define ACT8945A_REGULATOR_MODE_LOWPOWER 3 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/regulator/dlg,da9063-regulator.h b/sys/gnu/dts/include/dt-bindings/regulator/dlg,da9063-regulator.h deleted file mode 100644 index 1de710dd089..00000000000 --- a/sys/gnu/dts/include/dt-bindings/regulator/dlg,da9063-regulator.h +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ - -#ifndef _DT_BINDINGS_REGULATOR_DLG_DA9063_H -#define _DT_BINDINGS_REGULATOR_DLG_DA9063_H - -/* - * These buck mode constants may be used to specify values in device tree - * properties (e.g. regulator-initial-mode). - * A description of the following modes is in the manufacturers datasheet. - */ - -#define DA9063_BUCK_MODE_SLEEP 1 -#define DA9063_BUCK_MODE_SYNC 2 -#define DA9063_BUCK_MODE_AUTO 3 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/regulator/maxim,max77802.h b/sys/gnu/dts/include/dt-bindings/regulator/maxim,max77802.h deleted file mode 100644 index d0baba1973d..00000000000 --- a/sys/gnu/dts/include/dt-bindings/regulator/maxim,max77802.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2014 Google, Inc - * - * Device Tree binding constants for the Maxim 77802 PMIC regulators - */ - -#ifndef _DT_BINDINGS_REGULATOR_MAXIM_MAX77802_H -#define _DT_BINDINGS_REGULATOR_MAXIM_MAX77802_H - -/* Regulator operating modes */ -#define MAX77802_OPMODE_LP 1 -#define MAX77802_OPMODE_NORMAL 3 - -#endif /* _DT_BINDINGS_REGULATOR_MAXIM_MAX77802_H */ diff --git a/sys/gnu/dts/include/dt-bindings/regulator/qcom,rpmh-regulator.h b/sys/gnu/dts/include/dt-bindings/regulator/qcom,rpmh-regulator.h deleted file mode 100644 index 86713dcf9e0..00000000000 --- a/sys/gnu/dts/include/dt-bindings/regulator/qcom,rpmh-regulator.h +++ /dev/null @@ -1,36 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* Copyright (c) 2018, The Linux Foundation. All rights reserved. */ - -#ifndef __QCOM_RPMH_REGULATOR_H -#define __QCOM_RPMH_REGULATOR_H - -/* - * These mode constants may be used to specify modes for various RPMh regulator - * device tree properties (e.g. regulator-initial-mode). Each type of regulator - * supports a subset of the possible modes. - * - * %RPMH_REGULATOR_MODE_RET: Retention mode in which only an extremely small - * load current is allowed. This mode is supported - * by LDO and SMPS type regulators. - * %RPMH_REGULATOR_MODE_LPM: Low power mode in which a small load current is - * allowed. This mode corresponds to PFM for SMPS - * and BOB type regulators. This mode is supported - * by LDO, HFSMPS, BOB, and PMIC4 FTSMPS type - * regulators. - * %RPMH_REGULATOR_MODE_AUTO: Auto mode in which the regulator hardware - * automatically switches between LPM and HPM based - * upon the real-time load current. This mode is - * supported by HFSMPS, BOB, and PMIC4 FTSMPS type - * regulators. - * %RPMH_REGULATOR_MODE_HPM: High power mode in which the full rated current - * of the regulator is allowed. This mode - * corresponds to PWM for SMPS and BOB type - * regulators. This mode is supported by all types - * of regulators. - */ -#define RPMH_REGULATOR_MODE_RET 0 -#define RPMH_REGULATOR_MODE_LPM 1 -#define RPMH_REGULATOR_MODE_AUTO 2 -#define RPMH_REGULATOR_MODE_HPM 3 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/reset-controller/mt2712-resets.h b/sys/gnu/dts/include/dt-bindings/reset-controller/mt2712-resets.h deleted file mode 100644 index 9e7ee762f07..00000000000 --- a/sys/gnu/dts/include/dt-bindings/reset-controller/mt2712-resets.h +++ /dev/null @@ -1,22 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2019 MediaTek Inc. - * Author: Yong Liang - */ - -#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT2712 -#define _DT_BINDINGS_RESET_CONTROLLER_MT2712 - -#define MT2712_TOPRGU_INFRA_SW_RST 0 -#define MT2712_TOPRGU_MM_SW_RST 1 -#define MT2712_TOPRGU_MFG_SW_RST 2 -#define MT2712_TOPRGU_VENC_SW_RST 3 -#define MT2712_TOPRGU_VDEC_SW_RST 4 -#define MT2712_TOPRGU_IMG_SW_RST 5 -#define MT2712_TOPRGU_INFRA_AO_SW_RST 8 -#define MT2712_TOPRGU_USB_SW_RST 9 -#define MT2712_TOPRGU_APMIXED_SW_RST 10 - -#define MT2712_TOPRGU_SW_RST_NUM 11 - -#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT2712 */ diff --git a/sys/gnu/dts/include/dt-bindings/reset-controller/mt8183-resets.h b/sys/gnu/dts/include/dt-bindings/reset-controller/mt8183-resets.h deleted file mode 100644 index a1bbd41e0d1..00000000000 --- a/sys/gnu/dts/include/dt-bindings/reset-controller/mt8183-resets.h +++ /dev/null @@ -1,98 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2019 MediaTek Inc. - * Author: Yong Liang - */ - -#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8183 -#define _DT_BINDINGS_RESET_CONTROLLER_MT8183 - -/* INFRACFG AO resets */ -#define MT8183_INFRACFG_AO_THERM_SW_RST 0 -#define MT8183_INFRACFG_AO_USB_TOP_SW_RST 1 -#define MT8183_INFRACFG_AO_MM_IOMMU_SW_RST 3 -#define MT8183_INFRACFG_AO_MSDC3_SW_RST 4 -#define MT8183_INFRACFG_AO_MSDC2_SW_RST 5 -#define MT8183_INFRACFG_AO_MSDC1_SW_RST 6 -#define MT8183_INFRACFG_AO_MSDC0_SW_RST 7 -#define MT8183_INFRACFG_AO_APDMA_SW_RST 9 -#define MT8183_INFRACFG_AO_MIMP_D_SW_RST 10 -#define MT8183_INFRACFG_AO_BTIF_SW_RST 12 -#define MT8183_INFRACFG_AO_DISP_PWM_SW_RST 14 -#define MT8183_INFRACFG_AO_AUXADC_SW_RST 15 - -#define MT8183_INFRACFG_AO_IRTX_SW_RST 32 -#define MT8183_INFRACFG_AO_SPI0_SW_RST 33 -#define MT8183_INFRACFG_AO_I2C0_SW_RST 34 -#define MT8183_INFRACFG_AO_I2C1_SW_RST 35 -#define MT8183_INFRACFG_AO_I2C2_SW_RST 36 -#define MT8183_INFRACFG_AO_I2C3_SW_RST 37 -#define MT8183_INFRACFG_AO_UART0_SW_RST 38 -#define MT8183_INFRACFG_AO_UART1_SW_RST 39 -#define MT8183_INFRACFG_AO_UART2_SW_RST 40 -#define MT8183_INFRACFG_AO_PWM_SW_RST 41 -#define MT8183_INFRACFG_AO_SPI1_SW_RST 42 -#define MT8183_INFRACFG_AO_I2C4_SW_RST 43 -#define MT8183_INFRACFG_AO_DVFSP_SW_RST 44 -#define MT8183_INFRACFG_AO_SPI2_SW_RST 45 -#define MT8183_INFRACFG_AO_SPI3_SW_RST 46 -#define MT8183_INFRACFG_AO_UFSHCI_SW_RST 47 - -#define MT8183_INFRACFG_AO_PMIC_WRAP_SW_RST 64 -#define MT8183_INFRACFG_AO_SPM_SW_RST 65 -#define MT8183_INFRACFG_AO_USBSIF_SW_RST 66 -#define MT8183_INFRACFG_AO_KP_SW_RST 68 -#define MT8183_INFRACFG_AO_APXGPT_SW_RST 69 -#define MT8183_INFRACFG_AO_CLDMA_AO_SW_RST 70 -#define MT8183_INFRACFG_AO_UNIPRO_UFS_SW_RST 71 -#define MT8183_INFRACFG_AO_DX_CC_SW_RST 72 -#define MT8183_INFRACFG_AO_UFSPHY_SW_RST 73 - -#define MT8183_INFRACFG_AO_DX_CC_SEC_SW_RST 96 -#define MT8183_INFRACFG_AO_GCE_SW_RST 97 -#define MT8183_INFRACFG_AO_CLDMA_SW_RST 98 -#define MT8183_INFRACFG_AO_TRNG_SW_RST 99 -#define MT8183_INFRACFG_AO_AP_MD_CCIF_1_SW_RST 103 -#define MT8183_INFRACFG_AO_AP_MD_CCIF_SW_RST 104 -#define MT8183_INFRACFG_AO_I2C1_IMM_SW_RST 105 -#define MT8183_INFRACFG_AO_I2C1_ARB_SW_RST 106 -#define MT8183_INFRACFG_AO_I2C2_IMM_SW_RST 107 -#define MT8183_INFRACFG_AO_I2C2_ARB_SW_RST 108 -#define MT8183_INFRACFG_AO_I2C5_SW_RST 109 -#define MT8183_INFRACFG_AO_I2C5_IMM_SW_RST 110 -#define MT8183_INFRACFG_AO_I2C5_ARB_SW_RST 111 -#define MT8183_INFRACFG_AO_SPI4_SW_RST 112 -#define MT8183_INFRACFG_AO_SPI5_SW_RST 113 -#define MT8183_INFRACFG_AO_INFRA2MFGAXI_CBIP_CLAS_SW_RST 114 -#define MT8183_INFRACFG_AO_MFGAXI2INFRA_M0_CBIP_GLAS_OUT_SW_RST 115 -#define MT8183_INFRACFG_AO_MFGAXI2INFRA_M1_CBIP_GLAS_OUT_SW_RST 116 -#define MT8183_INFRACFG_AO_UFS_AES_SW_RST 117 -#define MT8183_INFRACFG_AO_CCU_I2C_IRQ_SW_RST 118 -#define MT8183_INFRACFG_AO_CCU_I2C_DMA_SW_RST 119 -#define MT8183_INFRACFG_AO_I2C6_SW_RST 120 -#define MT8183_INFRACFG_AO_CCU_GALS_SW_RST 121 -#define MT8183_INFRACFG_AO_IPU_GALS_SW_RST 122 -#define MT8183_INFRACFG_AO_CONN2AP_GALS_SW_RST 123 -#define MT8183_INFRACFG_AO_AP_MD_CCIF2_SW_RST 124 -#define MT8183_INFRACFG_AO_AP_MD_CCIF3_SW_RST 125 -#define MT8183_INFRACFG_AO_I2C7_SW_RST 126 -#define MT8183_INFRACFG_AO_I2C8_SW_RST 127 - -#define MT8183_INFRACFG_SW_RST_NUM 128 - -#define MT8183_TOPRGU_MM_SW_RST 1 -#define MT8183_TOPRGU_MFG_SW_RST 2 -#define MT8183_TOPRGU_VENC_SW_RST 3 -#define MT8183_TOPRGU_VDEC_SW_RST 4 -#define MT8183_TOPRGU_IMG_SW_RST 5 -#define MT8183_TOPRGU_MD_SW_RST 7 -#define MT8183_TOPRGU_CONN_SW_RST 9 -#define MT8183_TOPRGU_CONN_MCU_SW_RST 12 -#define MT8183_TOPRGU_IPU0_SW_RST 14 -#define MT8183_TOPRGU_IPU1_SW_RST 15 -#define MT8183_TOPRGU_AUDIO_SW_RST 17 -#define MT8183_TOPRGU_CAMSYS_SW_RST 18 - -#define MT8183_TOPRGU_SW_RST_NUM 19 - -#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8183 */ diff --git a/sys/gnu/dts/include/dt-bindings/reset-controller/stih407-resets.h b/sys/gnu/dts/include/dt-bindings/reset-controller/stih407-resets.h deleted file mode 100644 index 02d4328fe47..00000000000 --- a/sys/gnu/dts/include/dt-bindings/reset-controller/stih407-resets.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * This header provides constants for the reset controller - * based peripheral powerdown requests on the STMicroelectronics - * STiH407 SoC. - */ -#ifndef _DT_BINDINGS_RESET_CONTROLLER_STIH407 -#define _DT_BINDINGS_RESET_CONTROLLER_STIH407 - -/* Powerdown requests control 0 */ -#define STIH407_EMISS_POWERDOWN 0 -#define STIH407_NAND_POWERDOWN 1 - -/* Synp GMAC PowerDown */ -#define STIH407_ETH1_POWERDOWN 2 - -/* Powerdown requests control 1 */ -#define STIH407_USB3_POWERDOWN 3 -#define STIH407_USB2_PORT1_POWERDOWN 4 -#define STIH407_USB2_PORT0_POWERDOWN 5 -#define STIH407_PCIE1_POWERDOWN 6 -#define STIH407_PCIE0_POWERDOWN 7 -#define STIH407_SATA1_POWERDOWN 8 -#define STIH407_SATA0_POWERDOWN 9 - -/* Reset defines */ -#define STIH407_ETH1_SOFTRESET 0 -#define STIH407_MMC1_SOFTRESET 1 -#define STIH407_PICOPHY_SOFTRESET 2 -#define STIH407_IRB_SOFTRESET 3 -#define STIH407_PCIE0_SOFTRESET 4 -#define STIH407_PCIE1_SOFTRESET 5 -#define STIH407_SATA0_SOFTRESET 6 -#define STIH407_SATA1_SOFTRESET 7 -#define STIH407_MIPHY0_SOFTRESET 8 -#define STIH407_MIPHY1_SOFTRESET 9 -#define STIH407_MIPHY2_SOFTRESET 10 -#define STIH407_SATA0_PWR_SOFTRESET 11 -#define STIH407_SATA1_PWR_SOFTRESET 12 -#define STIH407_DELTA_SOFTRESET 13 -#define STIH407_BLITTER_SOFTRESET 14 -#define STIH407_HDTVOUT_SOFTRESET 15 -#define STIH407_HDQVDP_SOFTRESET 16 -#define STIH407_VDP_AUX_SOFTRESET 17 -#define STIH407_COMPO_SOFTRESET 18 -#define STIH407_HDMI_TX_PHY_SOFTRESET 19 -#define STIH407_JPEG_DEC_SOFTRESET 20 -#define STIH407_VP8_DEC_SOFTRESET 21 -#define STIH407_GPU_SOFTRESET 22 -#define STIH407_HVA_SOFTRESET 23 -#define STIH407_ERAM_HVA_SOFTRESET 24 -#define STIH407_LPM_SOFTRESET 25 -#define STIH407_KEYSCAN_SOFTRESET 26 -#define STIH407_USB2_PORT0_SOFTRESET 27 -#define STIH407_USB2_PORT1_SOFTRESET 28 - -/* Picophy reset defines */ -#define STIH407_PICOPHY0_RESET 0 -#define STIH407_PICOPHY1_RESET 1 -#define STIH407_PICOPHY2_RESET 2 - -#endif /* _DT_BINDINGS_RESET_CONTROLLER_STIH407 */ diff --git a/sys/gnu/dts/include/dt-bindings/reset-controller/stih415-resets.h b/sys/gnu/dts/include/dt-bindings/reset-controller/stih415-resets.h deleted file mode 100644 index c2329fe29cf..00000000000 --- a/sys/gnu/dts/include/dt-bindings/reset-controller/stih415-resets.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * This header provides constants for the reset controller - * based peripheral powerdown requests on the STMicroelectronics - * STiH415 SoC. - */ -#ifndef _DT_BINDINGS_RESET_CONTROLLER_STIH415 -#define _DT_BINDINGS_RESET_CONTROLLER_STIH415 - -#define STIH415_EMISS_POWERDOWN 0 -#define STIH415_NAND_POWERDOWN 1 -#define STIH415_KEYSCAN_POWERDOWN 2 -#define STIH415_USB0_POWERDOWN 3 -#define STIH415_USB1_POWERDOWN 4 -#define STIH415_USB2_POWERDOWN 5 -#define STIH415_SATA0_POWERDOWN 6 -#define STIH415_SATA1_POWERDOWN 7 -#define STIH415_PCIE_POWERDOWN 8 - -#define STIH415_ETH0_SOFTRESET 0 -#define STIH415_ETH1_SOFTRESET 1 -#define STIH415_IRB_SOFTRESET 2 -#define STIH415_USB0_SOFTRESET 3 -#define STIH415_USB1_SOFTRESET 4 -#define STIH415_USB2_SOFTRESET 5 -#define STIH415_KEYSCAN_SOFTRESET 6 - -#endif /* _DT_BINDINGS_RESET_CONTROLLER_STIH415 */ diff --git a/sys/gnu/dts/include/dt-bindings/reset-controller/stih416-resets.h b/sys/gnu/dts/include/dt-bindings/reset-controller/stih416-resets.h deleted file mode 100644 index fcf9af1ac0b..00000000000 --- a/sys/gnu/dts/include/dt-bindings/reset-controller/stih416-resets.h +++ /dev/null @@ -1,51 +0,0 @@ -/* - * This header provides constants for the reset controller - * based peripheral powerdown requests on the STMicroelectronics - * STiH416 SoC. - */ -#ifndef _DT_BINDINGS_RESET_CONTROLLER_STIH416 -#define _DT_BINDINGS_RESET_CONTROLLER_STIH416 - -#define STIH416_EMISS_POWERDOWN 0 -#define STIH416_NAND_POWERDOWN 1 -#define STIH416_KEYSCAN_POWERDOWN 2 -#define STIH416_USB0_POWERDOWN 3 -#define STIH416_USB1_POWERDOWN 4 -#define STIH416_USB2_POWERDOWN 5 -#define STIH416_USB3_POWERDOWN 6 -#define STIH416_SATA0_POWERDOWN 7 -#define STIH416_SATA1_POWERDOWN 8 -#define STIH416_PCIE0_POWERDOWN 9 -#define STIH416_PCIE1_POWERDOWN 10 - -#define STIH416_ETH0_SOFTRESET 0 -#define STIH416_ETH1_SOFTRESET 1 -#define STIH416_IRB_SOFTRESET 2 -#define STIH416_USB0_SOFTRESET 3 -#define STIH416_USB1_SOFTRESET 4 -#define STIH416_USB2_SOFTRESET 5 -#define STIH416_USB3_SOFTRESET 6 -#define STIH416_SATA0_SOFTRESET 7 -#define STIH416_SATA1_SOFTRESET 8 -#define STIH416_PCIE0_SOFTRESET 9 -#define STIH416_PCIE1_SOFTRESET 10 -#define STIH416_AUD_DAC_SOFTRESET 11 -#define STIH416_HDTVOUT_SOFTRESET 12 -#define STIH416_VTAC_M_RX_SOFTRESET 13 -#define STIH416_VTAC_A_RX_SOFTRESET 14 -#define STIH416_SYNC_HD_SOFTRESET 15 -#define STIH416_SYNC_SD_SOFTRESET 16 -#define STIH416_BLITTER_SOFTRESET 17 -#define STIH416_GPU_SOFTRESET 18 -#define STIH416_VTAC_M_TX_SOFTRESET 19 -#define STIH416_VTAC_A_TX_SOFTRESET 20 -#define STIH416_VTG_AUX_SOFTRESET 21 -#define STIH416_JPEG_DEC_SOFTRESET 22 -#define STIH416_HVA_SOFTRESET 23 -#define STIH416_COMPO_M_SOFTRESET 24 -#define STIH416_COMPO_A_SOFTRESET 25 -#define STIH416_VP8_DEC_SOFTRESET 26 -#define STIH416_VTG_MAIN_SOFTRESET 27 -#define STIH416_KEYSCAN_SOFTRESET 28 - -#endif /* _DT_BINDINGS_RESET_CONTROLLER_STIH416 */ diff --git a/sys/gnu/dts/include/dt-bindings/reset/actions,s700-reset.h b/sys/gnu/dts/include/dt-bindings/reset/actions,s700-reset.h deleted file mode 100644 index 5e3b16b8ef5..00000000000 --- a/sys/gnu/dts/include/dt-bindings/reset/actions,s700-reset.h +++ /dev/null @@ -1,34 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) -// -// Device Tree binding constants for Actions Semi S700 Reset Management Unit -// -// Copyright (c) 2018 Linaro Ltd. - -#ifndef __DT_BINDINGS_ACTIONS_S700_RESET_H -#define __DT_BINDINGS_ACTIONS_S700_RESET_H - -#define RESET_AUDIO 0 -#define RESET_CSI 1 -#define RESET_DE 2 -#define RESET_DSI 3 -#define RESET_GPIO 4 -#define RESET_I2C0 5 -#define RESET_I2C1 6 -#define RESET_I2C2 7 -#define RESET_I2C3 8 -#define RESET_KEY 9 -#define RESET_LCD0 10 -#define RESET_SI 11 -#define RESET_SPI0 12 -#define RESET_SPI1 13 -#define RESET_SPI2 14 -#define RESET_SPI3 15 -#define RESET_UART0 16 -#define RESET_UART1 17 -#define RESET_UART2 18 -#define RESET_UART3 19 -#define RESET_UART4 20 -#define RESET_UART5 21 -#define RESET_UART6 22 - -#endif /* __DT_BINDINGS_ACTIONS_S700_RESET_H */ diff --git a/sys/gnu/dts/include/dt-bindings/reset/actions,s900-reset.h b/sys/gnu/dts/include/dt-bindings/reset/actions,s900-reset.h deleted file mode 100644 index 42c19d02e43..00000000000 --- a/sys/gnu/dts/include/dt-bindings/reset/actions,s900-reset.h +++ /dev/null @@ -1,65 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) -// -// Device Tree binding constants for Actions Semi S900 Reset Management Unit -// -// Copyright (c) 2018 Linaro Ltd. - -#ifndef __DT_BINDINGS_ACTIONS_S900_RESET_H -#define __DT_BINDINGS_ACTIONS_S900_RESET_H - -#define RESET_CHIPID 0 -#define RESET_CPU_SCNT 1 -#define RESET_SRAMI 2 -#define RESET_DDR_CTL_PHY 3 -#define RESET_DMAC 4 -#define RESET_GPIO 5 -#define RESET_BISP_AXI 6 -#define RESET_CSI0 7 -#define RESET_CSI1 8 -#define RESET_DE 9 -#define RESET_DSI 10 -#define RESET_GPU3D_PA 11 -#define RESET_GPU3D_PB 12 -#define RESET_HDE 13 -#define RESET_I2C0 14 -#define RESET_I2C1 15 -#define RESET_I2C2 16 -#define RESET_I2C3 17 -#define RESET_I2C4 18 -#define RESET_I2C5 19 -#define RESET_IMX 20 -#define RESET_NANDC0 21 -#define RESET_NANDC1 22 -#define RESET_SD0 23 -#define RESET_SD1 24 -#define RESET_SD2 25 -#define RESET_SD3 26 -#define RESET_SPI0 27 -#define RESET_SPI1 28 -#define RESET_SPI2 29 -#define RESET_SPI3 30 -#define RESET_UART0 31 -#define RESET_UART1 32 -#define RESET_UART2 33 -#define RESET_UART3 34 -#define RESET_UART4 35 -#define RESET_UART5 36 -#define RESET_UART6 37 -#define RESET_HDMI 38 -#define RESET_LVDS 39 -#define RESET_EDP 40 -#define RESET_USB2HUB 41 -#define RESET_USB2HSIC 42 -#define RESET_USB3 43 -#define RESET_PCM1 44 -#define RESET_AUDIO 45 -#define RESET_PCM0 46 -#define RESET_SE 47 -#define RESET_GIC 48 -#define RESET_DDR_CTL_PHY_AXI 49 -#define RESET_CMU_DDR 50 -#define RESET_DMM 51 -#define RESET_HDCP2TX 52 -#define RESET_ETHERNET 53 - -#endif /* __DT_BINDINGS_ACTIONS_S900_RESET_H */ diff --git a/sys/gnu/dts/include/dt-bindings/reset/altr,rst-mgr-a10.h b/sys/gnu/dts/include/dt-bindings/reset/altr,rst-mgr-a10.h deleted file mode 100644 index 5d8a494c98d..00000000000 --- a/sys/gnu/dts/include/dt-bindings/reset/altr,rst-mgr-a10.h +++ /dev/null @@ -1,102 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2014, Steffen Trumtrar - */ - -#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_A10_H -#define _DT_BINDINGS_RESET_ALTR_RST_MGR_A10_H - -/* MPUMODRST */ -#define CPU0_RESET 0 -#define CPU1_RESET 1 -#define WDS_RESET 2 -#define SCUPER_RESET 3 - -/* PER0MODRST */ -#define EMAC0_RESET 32 -#define EMAC1_RESET 33 -#define EMAC2_RESET 34 -#define USB0_RESET 35 -#define USB1_RESET 36 -#define NAND_RESET 37 -#define QSPI_RESET 38 -#define SDMMC_RESET 39 -#define EMAC0_OCP_RESET 40 -#define EMAC1_OCP_RESET 41 -#define EMAC2_OCP_RESET 42 -#define USB0_OCP_RESET 43 -#define USB1_OCP_RESET 44 -#define NAND_OCP_RESET 45 -#define QSPI_OCP_RESET 46 -#define SDMMC_OCP_RESET 47 -#define DMA_RESET 48 -#define SPIM0_RESET 49 -#define SPIM1_RESET 50 -#define SPIS0_RESET 51 -#define SPIS1_RESET 52 -#define DMA_OCP_RESET 53 -#define EMAC_PTP_RESET 54 -/* 55 is empty*/ -#define DMAIF0_RESET 56 -#define DMAIF1_RESET 57 -#define DMAIF2_RESET 58 -#define DMAIF3_RESET 59 -#define DMAIF4_RESET 60 -#define DMAIF5_RESET 61 -#define DMAIF6_RESET 62 -#define DMAIF7_RESET 63 - -/* PER1MODRST */ -#define L4WD0_RESET 64 -#define L4WD1_RESET 65 -#define L4SYSTIMER0_RESET 66 -#define L4SYSTIMER1_RESET 67 -#define SPTIMER0_RESET 68 -#define SPTIMER1_RESET 69 -/* 70-71 is reserved */ -#define I2C0_RESET 72 -#define I2C1_RESET 73 -#define I2C2_RESET 74 -#define I2C3_RESET 75 -#define I2C4_RESET 76 -/* 77-79 is reserved */ -#define UART0_RESET 80 -#define UART1_RESET 81 -/* 82-87 is reserved */ -#define GPIO0_RESET 88 -#define GPIO1_RESET 89 -#define GPIO2_RESET 90 - -/* BRGMODRST */ -#define HPS2FPGA_RESET 96 -#define LWHPS2FPGA_RESET 97 -#define FPGA2HPS_RESET 98 -#define F2SSDRAM0_RESET 99 -#define F2SSDRAM1_RESET 100 -#define F2SSDRAM2_RESET 101 -#define DDRSCH_RESET 102 - -/* SYSMODRST*/ -#define ROM_RESET 128 -#define OCRAM_RESET 129 -/* 130 is reserved */ -#define FPGAMGR_RESET 131 -#define S2F_RESET 132 -#define SYSDBG_RESET 133 -#define OCRAM_OCP_RESET 134 - -/* COLDMODRST */ -#define CLKMGRCOLD_RESET 160 -/* 161-162 is reserved */ -#define S2FCOLD_RESET 163 -#define TIMESTAMPCOLD_RESET 164 -#define TAPCOLD_RESET 165 -#define HMCCOLD_RESET 166 -#define IOMGRCOLD_RESET 167 - -/* NRSTMODRST */ -#define NRSTPINOE_RESET 192 - -/* DBGMODRST */ -#define DBG_RESET 224 -#endif diff --git a/sys/gnu/dts/include/dt-bindings/reset/altr,rst-mgr-a10sr.h b/sys/gnu/dts/include/dt-bindings/reset/altr,rst-mgr-a10sr.h deleted file mode 100644 index 09a15ea5818..00000000000 --- a/sys/gnu/dts/include/dt-bindings/reset/altr,rst-mgr-a10sr.h +++ /dev/null @@ -1,22 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright Intel Corporation (C) 2017. All Rights Reserved - * - * Reset binding definitions for Altera Arria10 MAX5 System Resource Chip - * - * Adapted from altr,rst-mgr-a10.h - */ - -#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_A10SR_H -#define _DT_BINDINGS_RESET_ALTR_RST_MGR_A10SR_H - -/* Peripheral PHY resets */ -#define A10SR_RESET_ENET_HPS 0 -#define A10SR_RESET_PCIE 1 -#define A10SR_RESET_FILE 2 -#define A10SR_RESET_BQSPI 3 -#define A10SR_RESET_USB 4 - -#define A10SR_RESET_NUM 5 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/reset/altr,rst-mgr-s10.h b/sys/gnu/dts/include/dt-bindings/reset/altr,rst-mgr-s10.h deleted file mode 100644 index 70ea3a09dbe..00000000000 --- a/sys/gnu/dts/include/dt-bindings/reset/altr,rst-mgr-s10.h +++ /dev/null @@ -1,97 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) 2016 Intel Corporation. All rights reserved - * Copyright (C) 2016 Altera Corporation. All rights reserved - * - * derived from Steffen Trumtrar's "altr,rst-mgr-a10.h" - */ - -#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_S10_H -#define _DT_BINDINGS_RESET_ALTR_RST_MGR_S10_H - -/* MPUMODRST */ -#define CPU0_RESET 0 -#define CPU1_RESET 1 -#define CPU2_RESET 2 -#define CPU3_RESET 3 - -/* PER0MODRST */ -#define EMAC0_RESET 32 -#define EMAC1_RESET 33 -#define EMAC2_RESET 34 -#define USB0_RESET 35 -#define USB1_RESET 36 -#define NAND_RESET 37 -/* 38 is empty */ -#define SDMMC_RESET 39 -#define EMAC0_OCP_RESET 40 -#define EMAC1_OCP_RESET 41 -#define EMAC2_OCP_RESET 42 -#define USB0_OCP_RESET 43 -#define USB1_OCP_RESET 44 -#define NAND_OCP_RESET 45 -/* 46 is empty */ -#define SDMMC_OCP_RESET 47 -#define DMA_RESET 48 -#define SPIM0_RESET 49 -#define SPIM1_RESET 50 -#define SPIS0_RESET 51 -#define SPIS1_RESET 52 -#define DMA_OCP_RESET 53 -#define EMAC_PTP_RESET 54 -/* 55 is empty*/ -#define DMAIF0_RESET 56 -#define DMAIF1_RESET 57 -#define DMAIF2_RESET 58 -#define DMAIF3_RESET 59 -#define DMAIF4_RESET 60 -#define DMAIF5_RESET 61 -#define DMAIF6_RESET 62 -#define DMAIF7_RESET 63 - -/* PER1MODRST */ -#define WATCHDOG0_RESET 64 -#define WATCHDOG1_RESET 65 -#define WATCHDOG2_RESET 66 -#define WATCHDOG3_RESET 67 -#define L4SYSTIMER0_RESET 68 -#define L4SYSTIMER1_RESET 69 -#define SPTIMER0_RESET 70 -#define SPTIMER1_RESET 71 -#define I2C0_RESET 72 -#define I2C1_RESET 73 -#define I2C2_RESET 74 -#define I2C3_RESET 75 -#define I2C4_RESET 76 -/* 77-79 is empty */ -#define UART0_RESET 80 -#define UART1_RESET 81 -/* 82-87 is empty */ -#define GPIO0_RESET 88 -#define GPIO1_RESET 89 - -/* BRGMODRST */ -#define SOC2FPGA_RESET 96 -#define LWHPS2FPGA_RESET 97 -#define FPGA2SOC_RESET 98 -#define F2SSDRAM0_RESET 99 -#define F2SSDRAM1_RESET 100 -#define F2SSDRAM2_RESET 101 -#define DDRSCH_RESET 102 - -/* COLDMODRST */ -#define CPUPO0_RESET 160 -#define CPUPO1_RESET 161 -#define CPUPO2_RESET 162 -#define CPUPO3_RESET 163 -/* 164-167 is empty */ -#define L2_RESET 168 - -/* DBGMODRST */ -#define DBG_RESET 224 -#define CSDAP_RESET 225 - -/* TAPMODRST */ -#define TAP_RESET 256 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/reset/altr,rst-mgr.h b/sys/gnu/dts/include/dt-bindings/reset/altr,rst-mgr.h deleted file mode 100644 index 9b6ce14f62c..00000000000 --- a/sys/gnu/dts/include/dt-bindings/reset/altr,rst-mgr.h +++ /dev/null @@ -1,82 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2014, Steffen Trumtrar - */ - -#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_H -#define _DT_BINDINGS_RESET_ALTR_RST_MGR_H - -/* MPUMODRST */ -#define CPU0_RESET 0 -#define CPU1_RESET 1 -#define WDS_RESET 2 -#define SCUPER_RESET 3 -#define L2_RESET 4 - -/* PERMODRST */ -#define EMAC0_RESET 32 -#define EMAC1_RESET 33 -#define USB0_RESET 34 -#define USB1_RESET 35 -#define NAND_RESET 36 -#define QSPI_RESET 37 -#define L4WD0_RESET 38 -#define L4WD1_RESET 39 -#define OSC1TIMER0_RESET 40 -#define OSC1TIMER1_RESET 41 -#define SPTIMER0_RESET 42 -#define SPTIMER1_RESET 43 -#define I2C0_RESET 44 -#define I2C1_RESET 45 -#define I2C2_RESET 46 -#define I2C3_RESET 47 -#define UART0_RESET 48 -#define UART1_RESET 49 -#define SPIM0_RESET 50 -#define SPIM1_RESET 51 -#define SPIS0_RESET 52 -#define SPIS1_RESET 53 -#define SDMMC_RESET 54 -#define CAN0_RESET 55 -#define CAN1_RESET 56 -#define GPIO0_RESET 57 -#define GPIO1_RESET 58 -#define GPIO2_RESET 59 -#define DMA_RESET 60 -#define SDR_RESET 61 - -/* PER2MODRST */ -#define DMAIF0_RESET 64 -#define DMAIF1_RESET 65 -#define DMAIF2_RESET 66 -#define DMAIF3_RESET 67 -#define DMAIF4_RESET 68 -#define DMAIF5_RESET 69 -#define DMAIF6_RESET 70 -#define DMAIF7_RESET 71 - -/* BRGMODRST */ -#define HPS2FPGA_RESET 96 -#define LWHPS2FPGA_RESET 97 -#define FPGA2HPS_RESET 98 - -/* MISCMODRST*/ -#define ROM_RESET 128 -#define OCRAM_RESET 129 -#define SYSMGR_RESET 130 -#define SYSMGRCOLD_RESET 131 -#define FPGAMGR_RESET 132 -#define ACPIDMAP_RESET 133 -#define S2F_RESET 134 -#define S2FCOLD_RESET 135 -#define NRSTPIN_RESET 136 -#define TIMESTAMPCOLD_RESET 137 -#define CLKMGRCOLD_RESET 138 -#define SCANMGR_RESET 139 -#define FRZCTRLCOLD_RESET 140 -#define SYSDBG_RESET 141 -#define DBG_RESET 142 -#define TAPCOLD_RESET 143 -#define SDRCOLD_RESET 144 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/reset/amlogic,meson-a1-reset.h b/sys/gnu/dts/include/dt-bindings/reset/amlogic,meson-a1-reset.h deleted file mode 100644 index f1a3a797540..00000000000 --- a/sys/gnu/dts/include/dt-bindings/reset/amlogic,meson-a1-reset.h +++ /dev/null @@ -1,74 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) - * - * Copyright (c) 2019 Amlogic, Inc. All rights reserved. - * Author: Xingyu Chen - * - */ - -#ifndef _DT_BINDINGS_AMLOGIC_MESON_A1_RESET_H -#define _DT_BINDINGS_AMLOGIC_MESON_A1_RESET_H - -/* RESET0 */ -/* 0 */ -#define RESET_AM2AXI_VAD 1 -/* 2-3 */ -#define RESET_PSRAM 4 -#define RESET_PAD_CTRL 5 -/* 6 */ -#define RESET_TEMP_SENSOR 7 -#define RESET_AM2AXI_DEV 8 -/* 9 */ -#define RESET_SPICC_A 10 -#define RESET_MSR_CLK 11 -#define RESET_AUDIO 12 -#define RESET_ANALOG_CTRL 13 -#define RESET_SAR_ADC 14 -#define RESET_AUDIO_VAD 15 -#define RESET_CEC 16 -#define RESET_PWM_EF 17 -#define RESET_PWM_CD 18 -#define RESET_PWM_AB 19 -/* 20 */ -#define RESET_IR_CTRL 21 -#define RESET_I2C_S_A 22 -/* 23 */ -#define RESET_I2C_M_D 24 -#define RESET_I2C_M_C 25 -#define RESET_I2C_M_B 26 -#define RESET_I2C_M_A 27 -#define RESET_I2C_PROD_AHB 28 -#define RESET_I2C_PROD 29 -/* 30-31 */ - -/* RESET1 */ -#define RESET_ACODEC 32 -#define RESET_DMA 33 -#define RESET_SD_EMMC_A 34 -/* 35 */ -#define RESET_USBCTRL 36 -/* 37 */ -#define RESET_USBPHY 38 -/* 39-41 */ -#define RESET_RSA 42 -#define RESET_DMC 43 -/* 44 */ -#define RESET_IRQ_CTRL 45 -/* 46 */ -#define RESET_NIC_VAD 47 -#define RESET_NIC_AXI 48 -#define RESET_RAMA 49 -#define RESET_RAMB 50 -/* 51-52 */ -#define RESET_ROM 53 -#define RESET_SPIFC 54 -#define RESET_GIC 55 -#define RESET_UART_C 56 -#define RESET_UART_B 57 -#define RESET_UART_A 58 -#define RESET_OSC_RING 59 -/* 60-63 */ - -/* RESET2 */ -/* 64-95 */ - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/reset/amlogic,meson-axg-audio-arb.h b/sys/gnu/dts/include/dt-bindings/reset/amlogic,meson-axg-audio-arb.h deleted file mode 100644 index 1ef807856cb..00000000000 --- a/sys/gnu/dts/include/dt-bindings/reset/amlogic,meson-axg-audio-arb.h +++ /dev/null @@ -1,19 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0 OR MIT) - * - * Copyright (c) 2018 Baylibre SAS. - * Author: Jerome Brunet - */ - -#ifndef _DT_BINDINGS_AMLOGIC_MESON_AXG_AUDIO_ARB_H -#define _DT_BINDINGS_AMLOGIC_MESON_AXG_AUDIO_ARB_H - -#define AXG_ARB_TODDR_A 0 -#define AXG_ARB_TODDR_B 1 -#define AXG_ARB_TODDR_C 2 -#define AXG_ARB_FRDDR_A 3 -#define AXG_ARB_FRDDR_B 4 -#define AXG_ARB_FRDDR_C 5 -#define AXG_ARB_TODDR_D 6 -#define AXG_ARB_FRDDR_D 7 - -#endif /* _DT_BINDINGS_AMLOGIC_MESON_AXG_AUDIO_ARB_H */ diff --git a/sys/gnu/dts/include/dt-bindings/reset/amlogic,meson-axg-reset.h b/sys/gnu/dts/include/dt-bindings/reset/amlogic,meson-axg-reset.h deleted file mode 100644 index 0f2e0fe45ca..00000000000 --- a/sys/gnu/dts/include/dt-bindings/reset/amlogic,meson-axg-reset.h +++ /dev/null @@ -1,123 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ -/* - * Copyright (c) 2016 BayLibre, SAS. - * Author: Neil Armstrong - * - * Copyright (c) 2017 Amlogic, inc. - * Author: Yixun Lan - * - */ - -#ifndef _DT_BINDINGS_AMLOGIC_MESON_AXG_RESET_H -#define _DT_BINDINGS_AMLOGIC_MESON_AXG_RESET_H - -/* RESET0 */ -#define RESET_HIU 0 -#define RESET_PCIE_A 1 -#define RESET_PCIE_B 2 -#define RESET_DDR_TOP 3 -/* 4 */ -#define RESET_VIU 5 -#define RESET_PCIE_PHY 6 -#define RESET_PCIE_APB 7 -/* 8 */ -/* 9 */ -#define RESET_VENC 10 -#define RESET_ASSIST 11 -/* 12 */ -#define RESET_VCBUS 13 -/* 14 */ -/* 15 */ -#define RESET_GIC 16 -#define RESET_CAPB3_DECODE 17 -/* 18-21 */ -#define RESET_SYS_CPU_CAPB3 22 -#define RESET_CBUS_CAPB3 23 -#define RESET_AHB_CNTL 24 -#define RESET_AHB_DATA 25 -#define RESET_VCBUS_CLK81 26 -#define RESET_MMC 27 -/* 28-31 */ -/* RESET1 */ -/* 32 */ -/* 33 */ -#define RESET_USB_OTG 34 -#define RESET_DDR 35 -#define RESET_AO_RESET 36 -/* 37 */ -#define RESET_AHB_SRAM 38 -/* 39 */ -/* 40 */ -#define RESET_DMA 41 -#define RESET_ISA 42 -#define RESET_ETHERNET 43 -/* 44 */ -#define RESET_SD_EMMC_B 45 -#define RESET_SD_EMMC_C 46 -#define RESET_ROM_BOOT 47 -#define RESET_SYS_CPU_0 48 -#define RESET_SYS_CPU_1 49 -#define RESET_SYS_CPU_2 50 -#define RESET_SYS_CPU_3 51 -#define RESET_SYS_CPU_CORE_0 52 -#define RESET_SYS_CPU_CORE_1 53 -#define RESET_SYS_CPU_CORE_2 54 -#define RESET_SYS_CPU_CORE_3 55 -#define RESET_SYS_PLL_DIV 56 -#define RESET_SYS_CPU_AXI 57 -#define RESET_SYS_CPU_L2 58 -#define RESET_SYS_CPU_P 59 -#define RESET_SYS_CPU_MBIST 60 -/* 61-63 */ -/* RESET2 */ -/* 64 */ -/* 65 */ -#define RESET_AUDIO 66 -/* 67 */ -#define RESET_MIPI_HOST 68 -#define RESET_AUDIO_LOCKER 69 -#define RESET_GE2D 70 -/* 71-76 */ -#define RESET_AO_CPU_RESET 77 -/* 78-95 */ -/* RESET3 */ -#define RESET_RING_OSCILLATOR 96 -/* 97-127 */ -/* RESET4 */ -/* 128 */ -/* 129 */ -#define RESET_MIPI_PHY 130 -/* 131-140 */ -#define RESET_VENCL 141 -#define RESET_I2C_MASTER_2 142 -#define RESET_I2C_MASTER_1 143 -/* 144-159 */ -/* RESET5 */ -/* 160-191 */ -/* RESET6 */ -#define RESET_PERIPHS_GENERAL 192 -#define RESET_PERIPHS_SPICC 193 -/* 194 */ -/* 195 */ -#define RESET_PERIPHS_I2C_MASTER_0 196 -/* 197-200 */ -#define RESET_PERIPHS_UART_0 201 -#define RESET_PERIPHS_UART_1 202 -/* 203-204 */ -#define RESET_PERIPHS_SPI_0 205 -#define RESET_PERIPHS_I2C_MASTER_3 206 -/* 207-223 */ -/* RESET7 */ -#define RESET_USB_DDR_0 224 -#define RESET_USB_DDR_1 225 -#define RESET_USB_DDR_2 226 -#define RESET_USB_DDR_3 227 -/* 228 */ -#define RESET_DEVICE_MMC_ARB 229 -/* 230 */ -#define RESET_VID_LOCK 231 -#define RESET_A9_DMC_PIPEL 232 -#define RESET_DMC_VPU_PIPEL 233 -/* 234-255 */ - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/reset/amlogic,meson-g12a-audio-reset.h b/sys/gnu/dts/include/dt-bindings/reset/amlogic,meson-g12a-audio-reset.h deleted file mode 100644 index f805129ca7a..00000000000 --- a/sys/gnu/dts/include/dt-bindings/reset/amlogic,meson-g12a-audio-reset.h +++ /dev/null @@ -1,53 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2019 BayLibre, SAS. - * Author: Jerome Brunet - * - */ - -#ifndef _DT_BINDINGS_AMLOGIC_MESON_G12A_AUDIO_RESET_H -#define _DT_BINDINGS_AMLOGIC_MESON_G12A_AUDIO_RESET_H - -#define AUD_RESET_PDM 0 -#define AUD_RESET_TDMIN_A 1 -#define AUD_RESET_TDMIN_B 2 -#define AUD_RESET_TDMIN_C 3 -#define AUD_RESET_TDMIN_LB 4 -#define AUD_RESET_LOOPBACK 5 -#define AUD_RESET_TODDR_A 6 -#define AUD_RESET_TODDR_B 7 -#define AUD_RESET_TODDR_C 8 -#define AUD_RESET_FRDDR_A 9 -#define AUD_RESET_FRDDR_B 10 -#define AUD_RESET_FRDDR_C 11 -#define AUD_RESET_TDMOUT_A 12 -#define AUD_RESET_TDMOUT_B 13 -#define AUD_RESET_TDMOUT_C 14 -#define AUD_RESET_SPDIFOUT 15 -#define AUD_RESET_SPDIFOUT_B 16 -#define AUD_RESET_SPDIFIN 17 -#define AUD_RESET_EQDRC 18 -#define AUD_RESET_RESAMPLE 19 -#define AUD_RESET_DDRARB 20 -#define AUD_RESET_POWDET 21 -#define AUD_RESET_TORAM 22 -#define AUD_RESET_TOACODEC 23 -#define AUD_RESET_TOHDMITX 24 -#define AUD_RESET_CLKTREE 25 - -/* SM1 added resets */ -#define AUD_RESET_RESAMPLE_B 26 -#define AUD_RESET_TOVAD 27 -#define AUD_RESET_LOCKER 28 -#define AUD_RESET_SPDIFIN_LB 29 -#define AUD_RESET_FRATV 30 -#define AUD_RESET_FRHDMIRX 31 -#define AUD_RESET_FRDDR_D 32 -#define AUD_RESET_TODDR_D 33 -#define AUD_RESET_LOOPBACK_B 34 -#define AUD_RESET_EARCTX 35 -#define AUD_RESET_EARCRX 36 -#define AUD_RESET_FRDDR_E 37 -#define AUD_RESET_TODDR_E 38 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/reset/amlogic,meson-g12a-reset.h b/sys/gnu/dts/include/dt-bindings/reset/amlogic,meson-g12a-reset.h deleted file mode 100644 index 6d487c5eba2..00000000000 --- a/sys/gnu/dts/include/dt-bindings/reset/amlogic,meson-g12a-reset.h +++ /dev/null @@ -1,137 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ -/* - * Copyright (c) 2019 BayLibre, SAS. - * Author: Jerome Brunet - * - */ - -#ifndef _DT_BINDINGS_AMLOGIC_MESON_G12A_RESET_H -#define _DT_BINDINGS_AMLOGIC_MESON_G12A_RESET_H - -/* RESET0 */ -#define RESET_HIU 0 -/* 1 */ -#define RESET_DOS 2 -/* 3-4 */ -#define RESET_VIU 5 -#define RESET_AFIFO 6 -#define RESET_VID_PLL_DIV 7 -/* 8-9 */ -#define RESET_VENC 10 -#define RESET_ASSIST 11 -#define RESET_PCIE_CTRL_A 12 -#define RESET_VCBUS 13 -#define RESET_PCIE_PHY 14 -#define RESET_PCIE_APB 15 -#define RESET_GIC 16 -#define RESET_CAPB3_DECODE 17 -/* 18 */ -#define RESET_HDMITX_CAPB3 19 -#define RESET_DVALIN_CAPB3 20 -#define RESET_DOS_CAPB3 21 -/* 22 */ -#define RESET_CBUS_CAPB3 23 -#define RESET_AHB_CNTL 24 -#define RESET_AHB_DATA 25 -#define RESET_VCBUS_CLK81 26 -/* 27-31 */ -/* RESET1 */ -/* 32 */ -#define RESET_DEMUX 33 -#define RESET_USB 34 -#define RESET_DDR 35 -/* 36 */ -#define RESET_BT656 37 -#define RESET_AHB_SRAM 38 -/* 39 */ -#define RESET_PARSER 40 -/* 41 */ -#define RESET_ISA 42 -#define RESET_ETHERNET 43 -#define RESET_SD_EMMC_A 44 -#define RESET_SD_EMMC_B 45 -#define RESET_SD_EMMC_C 46 -/* 47 */ -#define RESET_USB_PHY20 48 -#define RESET_USB_PHY21 49 -/* 50-60 */ -#define RESET_AUDIO_CODEC 61 -/* 62-63 */ -/* RESET2 */ -/* 64 */ -#define RESET_AUDIO 65 -#define RESET_HDMITX_PHY 66 -/* 67 */ -#define RESET_MIPI_DSI_HOST 68 -#define RESET_ALOCKER 69 -#define RESET_GE2D 70 -#define RESET_PARSER_REG 71 -#define RESET_PARSER_FETCH 72 -#define RESET_CTL 73 -#define RESET_PARSER_TOP 74 -/* 75-77 */ -#define RESET_DVALIN 78 -#define RESET_HDMITX 79 -/* 80-95 */ -/* RESET3 */ -/* 96-95 */ -#define RESET_DEMUX_TOP 105 -#define RESET_DEMUX_DES_PL 106 -#define RESET_DEMUX_S2P_0 107 -#define RESET_DEMUX_S2P_1 108 -#define RESET_DEMUX_0 109 -#define RESET_DEMUX_1 110 -#define RESET_DEMUX_2 111 -/* 112-127 */ -/* RESET4 */ -/* 128-129 */ -#define RESET_MIPI_DSI_PHY 130 -/* 131-132 */ -#define RESET_RDMA 133 -#define RESET_VENCI 134 -#define RESET_VENCP 135 -/* 136 */ -#define RESET_VDAC 137 -/* 138-139 */ -#define RESET_VDI6 140 -#define RESET_VENCL 141 -#define RESET_I2C_M1 142 -#define RESET_I2C_M2 143 -/* 144-159 */ -/* RESET5 */ -/* 160-191 */ -/* RESET6 */ -#define RESET_GEN 192 -#define RESET_SPICC0 193 -#define RESET_SC 194 -#define RESET_SANA_3 195 -#define RESET_I2C_M0 196 -#define RESET_TS_PLL 197 -#define RESET_SPICC1 198 -#define RESET_STREAM 199 -#define RESET_TS_CPU 200 -#define RESET_UART0 201 -#define RESET_UART1_2 202 -#define RESET_ASYNC0 203 -#define RESET_ASYNC1 204 -#define RESET_SPIFC0 205 -#define RESET_I2C_M3 206 -/* 207-223 */ -/* RESET7 */ -#define RESET_USB_DDR_0 224 -#define RESET_USB_DDR_1 225 -#define RESET_USB_DDR_2 226 -#define RESET_USB_DDR_3 227 -#define RESET_TS_GPU 228 -#define RESET_DEVICE_MMC_ARB 229 -#define RESET_DVALIN_DMC_PIPL 230 -#define RESET_VID_LOCK 231 -#define RESET_NIC_DMC_PIPL 232 -#define RESET_DMC_VPU_PIPL 233 -#define RESET_GE2D_DMC_PIPL 234 -#define RESET_HCODEC_DMC_PIPL 235 -#define RESET_WAVE420_DMC_PIPL 236 -#define RESET_HEVCF_DMC_PIPL 237 -/* 238-255 */ - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/reset/amlogic,meson-gxbb-reset.h b/sys/gnu/dts/include/dt-bindings/reset/amlogic,meson-gxbb-reset.h deleted file mode 100644 index ea505861886..00000000000 --- a/sys/gnu/dts/include/dt-bindings/reset/amlogic,meson-gxbb-reset.h +++ /dev/null @@ -1,161 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ -/* - * Copyright (c) 2016 BayLibre, SAS. - * Author: Neil Armstrong - */ -#ifndef _DT_BINDINGS_AMLOGIC_MESON_GXBB_RESET_H -#define _DT_BINDINGS_AMLOGIC_MESON_GXBB_RESET_H - -/* RESET0 */ -#define RESET_HIU 0 -/* 1 */ -#define RESET_DOS_RESET 2 -#define RESET_DDR_TOP 3 -#define RESET_DCU_RESET 4 -#define RESET_VIU 5 -#define RESET_AIU 6 -#define RESET_VID_PLL_DIV 7 -/* 8 */ -#define RESET_PMUX 9 -#define RESET_VENC 10 -#define RESET_ASSIST 11 -#define RESET_AFIFO2 12 -#define RESET_VCBUS 13 -/* 14 */ -/* 15 */ -#define RESET_GIC 16 -#define RESET_CAPB3_DECODE 17 -#define RESET_NAND_CAPB3 18 -#define RESET_HDMITX_CAPB3 19 -#define RESET_MALI_CAPB3 20 -#define RESET_DOS_CAPB3 21 -#define RESET_SYS_CPU_CAPB3 22 -#define RESET_CBUS_CAPB3 23 -#define RESET_AHB_CNTL 24 -#define RESET_AHB_DATA 25 -#define RESET_VCBUS_CLK81 26 -#define RESET_MMC 27 -#define RESET_MIPI_0 28 -#define RESET_MIPI_1 29 -#define RESET_MIPI_2 30 -#define RESET_MIPI_3 31 -/* RESET1 */ -#define RESET_CPPM 32 -#define RESET_DEMUX 33 -#define RESET_USB_OTG 34 -#define RESET_DDR 35 -#define RESET_AO_RESET 36 -#define RESET_BT656 37 -#define RESET_AHB_SRAM 38 -/* 39 */ -#define RESET_PARSER 40 -#define RESET_BLKMV 41 -#define RESET_ISA 42 -#define RESET_ETHERNET 43 -#define RESET_SD_EMMC_A 44 -#define RESET_SD_EMMC_B 45 -#define RESET_SD_EMMC_C 46 -#define RESET_ROM_BOOT 47 -#define RESET_SYS_CPU_0 48 -#define RESET_SYS_CPU_1 49 -#define RESET_SYS_CPU_2 50 -#define RESET_SYS_CPU_3 51 -#define RESET_SYS_CPU_CORE_0 52 -#define RESET_SYS_CPU_CORE_1 53 -#define RESET_SYS_CPU_CORE_2 54 -#define RESET_SYS_CPU_CORE_3 55 -#define RESET_SYS_PLL_DIV 56 -#define RESET_SYS_CPU_AXI 57 -#define RESET_SYS_CPU_L2 58 -#define RESET_SYS_CPU_P 59 -#define RESET_SYS_CPU_MBIST 60 -/* 61 */ -/* 62 */ -/* 63 */ -/* RESET2 */ -#define RESET_VD_RMEM 64 -#define RESET_AUDIN 65 -#define RESET_HDMI_TX 66 -/* 67 */ -/* 68 */ -/* 69 */ -#define RESET_GE2D 70 -#define RESET_PARSER_REG 71 -#define RESET_PARSER_FETCH 72 -#define RESET_PARSER_CTL 73 -#define RESET_PARSER_TOP 74 -/* 75 */ -/* 76 */ -#define RESET_AO_CPU_RESET 77 -#define RESET_MALI 78 -#define RESET_HDMI_SYSTEM_RESET 79 -/* 80-95 */ -/* RESET3 */ -#define RESET_RING_OSCILLATOR 96 -#define RESET_SYS_CPU 97 -#define RESET_EFUSE 98 -#define RESET_SYS_CPU_BVCI 99 -#define RESET_AIFIFO 100 -#define RESET_TVFE 101 -#define RESET_AHB_BRIDGE_CNTL 102 -/* 103 */ -#define RESET_AUDIO_DAC 104 -#define RESET_DEMUX_TOP 105 -#define RESET_DEMUX_DES 106 -#define RESET_DEMUX_S2P_0 107 -#define RESET_DEMUX_S2P_1 108 -#define RESET_DEMUX_RESET_0 109 -#define RESET_DEMUX_RESET_1 110 -#define RESET_DEMUX_RESET_2 111 -/* 112-127 */ -/* RESET4 */ -/* 128 */ -/* 129 */ -/* 130 */ -/* 131 */ -#define RESET_DVIN_RESET 132 -#define RESET_RDMA 133 -#define RESET_VENCI 134 -#define RESET_VENCP 135 -/* 136 */ -#define RESET_VDAC 137 -#define RESET_RTC 138 -/* 139 */ -#define RESET_VDI6 140 -#define RESET_VENCL 141 -#define RESET_I2C_MASTER_2 142 -#define RESET_I2C_MASTER_1 143 -/* 144-159 */ -/* RESET5 */ -/* 160-191 */ -/* RESET6 */ -#define RESET_PERIPHS_GENERAL 192 -#define RESET_PERIPHS_SPICC 193 -#define RESET_PERIPHS_SMART_CARD 194 -#define RESET_PERIPHS_SAR_ADC 195 -#define RESET_PERIPHS_I2C_MASTER_0 196 -#define RESET_SANA 197 -/* 198 */ -#define RESET_PERIPHS_STREAM_INTERFACE 199 -#define RESET_PERIPHS_SDIO 200 -#define RESET_PERIPHS_UART_0 201 -#define RESET_PERIPHS_UART_1_2 202 -#define RESET_PERIPHS_ASYNC_0 203 -#define RESET_PERIPHS_ASYNC_1 204 -#define RESET_PERIPHS_SPI_0 205 -#define RESET_PERIPHS_SDHC 206 -#define RESET_UART_SLIP 207 -/* 208-223 */ -/* RESET7 */ -#define RESET_USB_DDR_0 224 -#define RESET_USB_DDR_1 225 -#define RESET_USB_DDR_2 226 -#define RESET_USB_DDR_3 227 -/* 228 */ -#define RESET_DEVICE_MMC_ARB 229 -/* 230 */ -#define RESET_VID_LOCK 231 -#define RESET_A9_DMC_PIPEL 232 -/* 233-255 */ - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/reset/amlogic,meson8b-clkc-reset.h b/sys/gnu/dts/include/dt-bindings/reset/amlogic,meson8b-clkc-reset.h deleted file mode 100644 index 1f1b56e5734..00000000000 --- a/sys/gnu/dts/include/dt-bindings/reset/amlogic,meson8b-clkc-reset.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Copyright (c) 2017 Martin Blumenstingl . - * - * SPDX-License-Identifier: (GPL-2.0+ OR MIT) - */ - -#ifndef _DT_BINDINGS_AMLOGIC_MESON8B_CLKC_RESET_H -#define _DT_BINDINGS_AMLOGIC_MESON8B_CLKC_RESET_H - -#define CLKC_RESET_L2_CACHE_SOFT_RESET 0 -#define CLKC_RESET_AXI_64_TO_128_BRIDGE_A5_SOFT_RESET 1 -#define CLKC_RESET_SCU_SOFT_RESET 2 -#define CLKC_RESET_CPU0_SOFT_RESET 3 -#define CLKC_RESET_CPU1_SOFT_RESET 4 -#define CLKC_RESET_CPU2_SOFT_RESET 5 -#define CLKC_RESET_CPU3_SOFT_RESET 6 -#define CLKC_RESET_A5_GLOBAL_RESET 7 -#define CLKC_RESET_A5_AXI_SOFT_RESET 8 -#define CLKC_RESET_A5_ABP_SOFT_RESET 9 -#define CLKC_RESET_AXI_64_TO_128_BRIDGE_MMC_SOFT_RESET 10 -#define CLKC_RESET_VID_CLK_CNTL_SOFT_RESET 11 -#define CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_POST 12 -#define CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_PRE 13 -#define CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_POST 14 -#define CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_PRE 15 - -#endif /* _DT_BINDINGS_AMLOGIC_MESON8B_CLKC_RESET_H */ diff --git a/sys/gnu/dts/include/dt-bindings/reset/amlogic,meson8b-reset.h b/sys/gnu/dts/include/dt-bindings/reset/amlogic,meson8b-reset.h deleted file mode 100644 index fbc524a900d..00000000000 --- a/sys/gnu/dts/include/dt-bindings/reset/amlogic,meson8b-reset.h +++ /dev/null @@ -1,126 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ -/* - * Copyright (c) 2016 BayLibre, SAS. - * Author: Neil Armstrong - */ -#ifndef _DT_BINDINGS_AMLOGIC_MESON8B_RESET_H -#define _DT_BINDINGS_AMLOGIC_MESON8B_RESET_H - -/* RESET0 */ -#define RESET_HIU 0 -#define RESET_VLD 1 -#define RESET_IQIDCT 2 -#define RESET_MC 3 -/* 8 */ -#define RESET_VIU 5 -#define RESET_AIU 6 -#define RESET_MCPU 7 -#define RESET_CCPU 8 -#define RESET_PMUX 9 -#define RESET_VENC 10 -#define RESET_ASSIST 11 -#define RESET_AFIFO2 12 -#define RESET_MDEC 13 -#define RESET_VLD_PART 14 -#define RESET_VIFIFO 15 -/* 16-31 */ -/* RESET1 */ -/* 32 */ -#define RESET_DEMUX 33 -#define RESET_USB_OTG 34 -#define RESET_DDR 35 -#define RESET_VDAC_1 36 -#define RESET_BT656 37 -#define RESET_AHB_SRAM 38 -#define RESET_AHB_BRIDGE 39 -#define RESET_PARSER 40 -#define RESET_BLKMV 41 -#define RESET_ISA 42 -#define RESET_ETHERNET 43 -#define RESET_ABUF 44 -#define RESET_AHB_DATA 45 -#define RESET_AHB_CNTL 46 -#define RESET_ROM_BOOT 47 -/* 48-63 */ -/* RESET2 */ -#define RESET_VD_RMEM 64 -#define RESET_AUDIN 65 -#define RESET_DBLK 66 -#define RESET_PIC_DC 67 -#define RESET_PSC 68 -#define RESET_NAND 69 -#define RESET_GE2D 70 -#define RESET_PARSER_REG 71 -#define RESET_PARSER_FETCH 72 -#define RESET_PARSER_CTL 73 -#define RESET_PARSER_TOP 74 -#define RESET_HDMI_APB 75 -#define RESET_AUDIO_APB 76 -#define RESET_MEDIA_CPU 77 -#define RESET_MALI 78 -#define RESET_HDMI_SYSTEM_RESET 79 -/* 80-95 */ -/* RESET3 */ -#define RESET_RING_OSCILLATOR 96 -#define RESET_SYS_CPU_0 97 -#define RESET_EFUSE 98 -#define RESET_SYS_CPU_BVCI 99 -#define RESET_AIFIFO 100 -#define RESET_AUDIO_PLL_MODULATOR 101 -#define RESET_AHB_BRIDGE_CNTL 102 -#define RESET_SYS_CPU_1 103 -#define RESET_AUDIO_DAC 104 -#define RESET_DEMUX_TOP 105 -#define RESET_DEMUX_DES 106 -#define RESET_DEMUX_S2P_0 107 -#define RESET_DEMUX_S2P_1 108 -#define RESET_DEMUX_RESET_0 109 -#define RESET_DEMUX_RESET_1 110 -#define RESET_DEMUX_RESET_2 111 -/* 112-127 */ -/* RESET4 */ -#define RESET_PL310 128 -#define RESET_A5_APB 129 -#define RESET_A5_AXI 130 -#define RESET_A5 131 -#define RESET_DVIN 132 -#define RESET_RDMA 133 -#define RESET_VENCI 134 -#define RESET_VENCP 135 -#define RESET_VENCT 136 -#define RESET_VDAC_4 137 -#define RESET_RTC 138 -#define RESET_A5_DEBUG 139 -#define RESET_VDI6 140 -#define RESET_VENCL 141 -/* 142-159 */ -/* RESET5 */ -#define RESET_DDR_PLL 160 -#define RESET_MISC_PLL 161 -#define RESET_SYS_PLL 162 -#define RESET_HPLL_PLL 163 -#define RESET_AUDIO_PLL 164 -#define RESET_VID2_PLL 165 -/* 166-191 */ -/* RESET6 */ -#define RESET_PERIPHS_GENERAL 192 -#define RESET_PERIPHS_IR_REMOTE 193 -#define RESET_PERIPHS_SMART_CARD 194 -#define RESET_PERIPHS_SAR_ADC 195 -#define RESET_PERIPHS_I2C_MASTER_0 196 -#define RESET_PERIPHS_I2C_MASTER_1 197 -#define RESET_PERIPHS_I2C_SLAVE 198 -#define RESET_PERIPHS_STREAM_INTERFACE 199 -#define RESET_PERIPHS_SDIO 200 -#define RESET_PERIPHS_UART_0 201 -#define RESET_PERIPHS_UART_1 202 -#define RESET_PERIPHS_ASYNC_0 203 -#define RESET_PERIPHS_ASYNC_1 204 -#define RESET_PERIPHS_SPI_0 205 -#define RESET_PERIPHS_SPI_1 206 -#define RESET_PERIPHS_LED_PWM 207 -/* 208-223 */ -/* RESET7 */ -/* 224-255 */ - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/reset/axg-aoclkc.h b/sys/gnu/dts/include/dt-bindings/reset/axg-aoclkc.h deleted file mode 100644 index d342c0b6b2a..00000000000 --- a/sys/gnu/dts/include/dt-bindings/reset/axg-aoclkc.h +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ -/* - * Copyright (c) 2016 BayLibre, SAS - * Author: Neil Armstrong - * - * Copyright (c) 2018 Amlogic, inc. - * Author: Qiufang Dai - */ - -#ifndef DT_BINDINGS_RESET_AMLOGIC_MESON_AXG_AOCLK -#define DT_BINDINGS_RESET_AMLOGIC_MESON_AXG_AOCLK - -#define RESET_AO_REMOTE 0 -#define RESET_AO_I2C_MASTER 1 -#define RESET_AO_I2C_SLAVE 2 -#define RESET_AO_UART1 3 -#define RESET_AO_UART2 4 -#define RESET_AO_IR_BLASTER 5 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/reset/bitmain,bm1880-reset.h b/sys/gnu/dts/include/dt-bindings/reset/bitmain,bm1880-reset.h deleted file mode 100644 index 4c0de522377..00000000000 --- a/sys/gnu/dts/include/dt-bindings/reset/bitmain,bm1880-reset.h +++ /dev/null @@ -1,51 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2018 Bitmain Ltd. - * Copyright (c) 2019 Linaro Ltd. - */ - -#ifndef _DT_BINDINGS_BM1880_RESET_H -#define _DT_BINDINGS_BM1880_RESET_H - -#define BM1880_RST_MAIN_AP 0 -#define BM1880_RST_SECOND_AP 1 -#define BM1880_RST_DDR 2 -#define BM1880_RST_VIDEO 3 -#define BM1880_RST_JPEG 4 -#define BM1880_RST_VPP 5 -#define BM1880_RST_GDMA 6 -#define BM1880_RST_AXI_SRAM 7 -#define BM1880_RST_TPU 8 -#define BM1880_RST_USB 9 -#define BM1880_RST_ETH0 10 -#define BM1880_RST_ETH1 11 -#define BM1880_RST_NAND 12 -#define BM1880_RST_EMMC 13 -#define BM1880_RST_SD 14 -#define BM1880_RST_SDMA 15 -#define BM1880_RST_I2S0 16 -#define BM1880_RST_I2S1 17 -#define BM1880_RST_UART0_1_CLK 18 -#define BM1880_RST_UART0_1_ACLK 19 -#define BM1880_RST_UART2_3_CLK 20 -#define BM1880_RST_UART2_3_ACLK 21 -#define BM1880_RST_MINER 22 -#define BM1880_RST_I2C0 23 -#define BM1880_RST_I2C1 24 -#define BM1880_RST_I2C2 25 -#define BM1880_RST_I2C3 26 -#define BM1880_RST_I2C4 27 -#define BM1880_RST_PWM0 28 -#define BM1880_RST_PWM1 29 -#define BM1880_RST_PWM2 30 -#define BM1880_RST_PWM3 31 -#define BM1880_RST_SPI 32 -#define BM1880_RST_GPIO0 33 -#define BM1880_RST_GPIO1 34 -#define BM1880_RST_GPIO2 35 -#define BM1880_RST_EFUSE 36 -#define BM1880_RST_WDT 37 -#define BM1880_RST_AHB_ROM 38 -#define BM1880_RST_SPIC 39 - -#endif /* _DT_BINDINGS_BM1880_RESET_H */ diff --git a/sys/gnu/dts/include/dt-bindings/reset/cortina,gemini-reset.h b/sys/gnu/dts/include/dt-bindings/reset/cortina,gemini-reset.h deleted file mode 100644 index f48aff23847..00000000000 --- a/sys/gnu/dts/include/dt-bindings/reset/cortina,gemini-reset.h +++ /dev/null @@ -1,37 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _DT_BINDINGS_RESET_CORTINA_GEMINI_H -#define _DT_BINDINGS_RESET_CORTINA_GEMINI_H - -#define GEMINI_RESET_DRAM 0 -#define GEMINI_RESET_FLASH 1 -#define GEMINI_RESET_IDE 2 -#define GEMINI_RESET_RAID 3 -#define GEMINI_RESET_SECURITY 4 -#define GEMINI_RESET_GMAC0 5 -#define GEMINI_RESET_GMAC1 6 -#define GEMINI_RESET_PCI 7 -#define GEMINI_RESET_USB0 8 -#define GEMINI_RESET_USB1 9 -#define GEMINI_RESET_DMAC 10 -#define GEMINI_RESET_APB 11 -#define GEMINI_RESET_LPC 12 -#define GEMINI_RESET_LCD 13 -#define GEMINI_RESET_INTCON0 14 -#define GEMINI_RESET_INTCON1 15 -#define GEMINI_RESET_RTC 16 -#define GEMINI_RESET_TIMER 17 -#define GEMINI_RESET_UART 18 -#define GEMINI_RESET_SSP 19 -#define GEMINI_RESET_GPIO0 20 -#define GEMINI_RESET_GPIO1 21 -#define GEMINI_RESET_GPIO2 22 -#define GEMINI_RESET_WDOG 23 -#define GEMINI_RESET_EXTERN 24 -#define GEMINI_RESET_CIR 25 -#define GEMINI_RESET_SATA0 26 -#define GEMINI_RESET_SATA1 27 -#define GEMINI_RESET_TVC 28 -#define GEMINI_RESET_CPU1 30 -#define GEMINI_RESET_GLOBAL 31 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/reset/g12a-aoclkc.h b/sys/gnu/dts/include/dt-bindings/reset/g12a-aoclkc.h deleted file mode 100644 index bd2e2337135..00000000000 --- a/sys/gnu/dts/include/dt-bindings/reset/g12a-aoclkc.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ -/* - * Copyright (c) 2016 BayLibre, SAS - * Author: Neil Armstrong - */ - -#ifndef DT_BINDINGS_RESET_AMLOGIC_MESON_G12A_AOCLK -#define DT_BINDINGS_RESET_AMLOGIC_MESON_G12A_AOCLK - -#define RESET_AO_IR_IN 0 -#define RESET_AO_UART 1 -#define RESET_AO_I2C_M 2 -#define RESET_AO_I2C_S 3 -#define RESET_AO_SAR_ADC 4 -#define RESET_AO_UART2 5 -#define RESET_AO_IR_OUT 6 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/reset/gxbb-aoclkc.h b/sys/gnu/dts/include/dt-bindings/reset/gxbb-aoclkc.h deleted file mode 100644 index 9e3fd60c309..00000000000 --- a/sys/gnu/dts/include/dt-bindings/reset/gxbb-aoclkc.h +++ /dev/null @@ -1,66 +0,0 @@ -/* - * This file is provided under a dual BSD/GPLv2 license. When using or - * redistributing this file, you may do so under either license. - * - * GPL LICENSE SUMMARY - * - * Copyright (c) 2016 BayLibre, SAS. - * Author: Neil Armstrong - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, see . - * The full GNU General Public License is included in this distribution - * in the file called COPYING. - * - * BSD LICENSE - * - * Copyright (c) 2016 BayLibre, SAS. - * Author: Neil Armstrong - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Intel Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef DT_BINDINGS_RESET_AMLOGIC_MESON_GXBB_AOCLK -#define DT_BINDINGS_RESET_AMLOGIC_MESON_GXBB_AOCLK - -#define RESET_AO_REMOTE 0 -#define RESET_AO_I2C_MASTER 1 -#define RESET_AO_I2C_SLAVE 2 -#define RESET_AO_UART1 3 -#define RESET_AO_UART2 4 -#define RESET_AO_IR_BLASTER 5 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/reset/hisi,hi6220-resets.h b/sys/gnu/dts/include/dt-bindings/reset/hisi,hi6220-resets.h deleted file mode 100644 index 63aff7d8aa4..00000000000 --- a/sys/gnu/dts/include/dt-bindings/reset/hisi,hi6220-resets.h +++ /dev/null @@ -1,83 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/** - * This header provides index for the reset controller - * based on hi6220 SoC. - */ -#ifndef _DT_BINDINGS_RESET_CONTROLLER_HI6220 -#define _DT_BINDINGS_RESET_CONTROLLER_HI6220 - -#define PERIPH_RSTDIS0_MMC0 0x000 -#define PERIPH_RSTDIS0_MMC1 0x001 -#define PERIPH_RSTDIS0_MMC2 0x002 -#define PERIPH_RSTDIS0_NANDC 0x003 -#define PERIPH_RSTDIS0_USBOTG_BUS 0x004 -#define PERIPH_RSTDIS0_POR_PICOPHY 0x005 -#define PERIPH_RSTDIS0_USBOTG 0x006 -#define PERIPH_RSTDIS0_USBOTG_32K 0x007 -#define PERIPH_RSTDIS1_HIFI 0x100 -#define PERIPH_RSTDIS1_DIGACODEC 0x105 -#define PERIPH_RSTEN2_IPF 0x200 -#define PERIPH_RSTEN2_SOCP 0x201 -#define PERIPH_RSTEN2_DMAC 0x202 -#define PERIPH_RSTEN2_SECENG 0x203 -#define PERIPH_RSTEN2_ABB 0x204 -#define PERIPH_RSTEN2_HPM0 0x205 -#define PERIPH_RSTEN2_HPM1 0x206 -#define PERIPH_RSTEN2_HPM2 0x207 -#define PERIPH_RSTEN2_HPM3 0x208 -#define PERIPH_RSTEN3_CSSYS 0x300 -#define PERIPH_RSTEN3_I2C0 0x301 -#define PERIPH_RSTEN3_I2C1 0x302 -#define PERIPH_RSTEN3_I2C2 0x303 -#define PERIPH_RSTEN3_I2C3 0x304 -#define PERIPH_RSTEN3_UART1 0x305 -#define PERIPH_RSTEN3_UART2 0x306 -#define PERIPH_RSTEN3_UART3 0x307 -#define PERIPH_RSTEN3_UART4 0x308 -#define PERIPH_RSTEN3_SSP 0x309 -#define PERIPH_RSTEN3_PWM 0x30a -#define PERIPH_RSTEN3_BLPWM 0x30b -#define PERIPH_RSTEN3_TSENSOR 0x30c -#define PERIPH_RSTEN3_DAPB 0x312 -#define PERIPH_RSTEN3_HKADC 0x313 -#define PERIPH_RSTEN3_CODEC_SSI 0x314 -#define PERIPH_RSTEN3_PMUSSI1 0x316 -#define PERIPH_RSTEN8_RS0 0x400 -#define PERIPH_RSTEN8_RS2 0x401 -#define PERIPH_RSTEN8_RS3 0x402 -#define PERIPH_RSTEN8_MS0 0x403 -#define PERIPH_RSTEN8_MS2 0x405 -#define PERIPH_RSTEN8_XG2RAM0 0x406 -#define PERIPH_RSTEN8_X2SRAM_TZMA 0x407 -#define PERIPH_RSTEN8_SRAM 0x408 -#define PERIPH_RSTEN8_HARQ 0x40a -#define PERIPH_RSTEN8_DDRC 0x40c -#define PERIPH_RSTEN8_DDRC_APB 0x40d -#define PERIPH_RSTEN8_DDRPACK_APB 0x40e -#define PERIPH_RSTEN8_DDRT 0x411 -#define PERIPH_RSDIST9_CARM_DAP 0x500 -#define PERIPH_RSDIST9_CARM_ATB 0x501 -#define PERIPH_RSDIST9_CARM_LBUS 0x502 -#define PERIPH_RSDIST9_CARM_POR 0x503 -#define PERIPH_RSDIST9_CARM_CORE 0x504 -#define PERIPH_RSDIST9_CARM_DBG 0x505 -#define PERIPH_RSDIST9_CARM_L2 0x506 -#define PERIPH_RSDIST9_CARM_SOCDBG 0x507 -#define PERIPH_RSDIST9_CARM_ETM 0x508 - -#define MEDIA_G3D 0 -#define MEDIA_CODEC_VPU 2 -#define MEDIA_CODEC_JPEG 3 -#define MEDIA_ISP 4 -#define MEDIA_ADE 5 -#define MEDIA_MMU 6 -#define MEDIA_XG2RAM1 7 - -#define AO_G3D 1 -#define AO_CODECISP 2 -#define AO_MCPU 4 -#define AO_BBPHARQMEM 5 -#define AO_HIFI 8 -#define AO_ACPUSCUL2C 12 - -#endif /*_DT_BINDINGS_RESET_CONTROLLER_HI6220*/ diff --git a/sys/gnu/dts/include/dt-bindings/reset/imx7-reset.h b/sys/gnu/dts/include/dt-bindings/reset/imx7-reset.h deleted file mode 100644 index a5b35b4754d..00000000000 --- a/sys/gnu/dts/include/dt-bindings/reset/imx7-reset.h +++ /dev/null @@ -1,53 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) 2017 Impinj, Inc. - * - * Author: Andrey Smirnov - */ - -#ifndef DT_BINDING_RESET_IMX7_H -#define DT_BINDING_RESET_IMX7_H - -#define IMX7_RESET_A7_CORE_POR_RESET0 0 -#define IMX7_RESET_A7_CORE_POR_RESET1 1 -#define IMX7_RESET_A7_CORE_RESET0 2 -#define IMX7_RESET_A7_CORE_RESET1 3 -#define IMX7_RESET_A7_DBG_RESET0 4 -#define IMX7_RESET_A7_DBG_RESET1 5 -#define IMX7_RESET_A7_ETM_RESET0 6 -#define IMX7_RESET_A7_ETM_RESET1 7 -#define IMX7_RESET_A7_SOC_DBG_RESET 8 -#define IMX7_RESET_A7_L2RESET 9 -#define IMX7_RESET_SW_M4C_RST 10 -#define IMX7_RESET_SW_M4P_RST 11 -#define IMX7_RESET_EIM_RST 12 -#define IMX7_RESET_HSICPHY_PORT_RST 13 -#define IMX7_RESET_USBPHY1_POR 14 -#define IMX7_RESET_USBPHY1_PORT_RST 15 -#define IMX7_RESET_USBPHY2_POR 16 -#define IMX7_RESET_USBPHY2_PORT_RST 17 -#define IMX7_RESET_MIPI_PHY_MRST 18 -#define IMX7_RESET_MIPI_PHY_SRST 19 - -/* - * IMX7_RESET_PCIEPHY is a logical reset line combining PCIEPHY_BTN - * and PCIEPHY_G_RST - */ -#define IMX7_RESET_PCIEPHY 20 -#define IMX7_RESET_PCIEPHY_PERST 21 - -/* - * IMX7_RESET_PCIE_CTRL_APPS_EN is not strictly a reset line, but it - * can be used to inhibit PCIe LTTSM, so, in a way, it can be thoguht - * of as one - */ -#define IMX7_RESET_PCIE_CTRL_APPS_EN 22 -#define IMX7_RESET_DDRC_PRST 23 -#define IMX7_RESET_DDRC_CORE_RST 24 - -#define IMX7_RESET_PCIE_CTRL_APPS_TURNOFF 25 - -#define IMX7_RESET_NUM 26 - -#endif - diff --git a/sys/gnu/dts/include/dt-bindings/reset/imx8mq-reset.h b/sys/gnu/dts/include/dt-bindings/reset/imx8mq-reset.h deleted file mode 100644 index 9a301082d36..00000000000 --- a/sys/gnu/dts/include/dt-bindings/reset/imx8mq-reset.h +++ /dev/null @@ -1,64 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2018 Zodiac Inflight Innovations - * - * Author: Andrey Smirnov - */ - -#ifndef DT_BINDING_RESET_IMX8MQ_H -#define DT_BINDING_RESET_IMX8MQ_H - -#define IMX8MQ_RESET_A53_CORE_POR_RESET0 0 -#define IMX8MQ_RESET_A53_CORE_POR_RESET1 1 -#define IMX8MQ_RESET_A53_CORE_POR_RESET2 2 -#define IMX8MQ_RESET_A53_CORE_POR_RESET3 3 -#define IMX8MQ_RESET_A53_CORE_RESET0 4 -#define IMX8MQ_RESET_A53_CORE_RESET1 5 -#define IMX8MQ_RESET_A53_CORE_RESET2 6 -#define IMX8MQ_RESET_A53_CORE_RESET3 7 -#define IMX8MQ_RESET_A53_DBG_RESET0 8 -#define IMX8MQ_RESET_A53_DBG_RESET1 9 -#define IMX8MQ_RESET_A53_DBG_RESET2 10 -#define IMX8MQ_RESET_A53_DBG_RESET3 11 -#define IMX8MQ_RESET_A53_ETM_RESET0 12 -#define IMX8MQ_RESET_A53_ETM_RESET1 13 -#define IMX8MQ_RESET_A53_ETM_RESET2 14 -#define IMX8MQ_RESET_A53_ETM_RESET3 15 -#define IMX8MQ_RESET_A53_SOC_DBG_RESET 16 -#define IMX8MQ_RESET_A53_L2RESET 17 -#define IMX8MQ_RESET_SW_NON_SCLR_M4C_RST 18 -#define IMX8MQ_RESET_OTG1_PHY_RESET 19 -#define IMX8MQ_RESET_OTG2_PHY_RESET 20 -#define IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N 21 -#define IMX8MQ_RESET_MIPI_DSI_RESET_N 22 -#define IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N 23 -#define IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N 24 -#define IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N 25 -#define IMX8MQ_RESET_PCIEPHY 26 -#define IMX8MQ_RESET_PCIEPHY_PERST 27 -#define IMX8MQ_RESET_PCIE_CTRL_APPS_EN 28 -#define IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF 29 -#define IMX8MQ_RESET_HDMI_PHY_APB_RESET 30 /* i.MX8MM does NOT support */ -#define IMX8MQ_RESET_DISP_RESET 31 -#define IMX8MQ_RESET_GPU_RESET 32 -#define IMX8MQ_RESET_VPU_RESET 33 -#define IMX8MQ_RESET_PCIEPHY2 34 /* i.MX8MM does NOT support */ -#define IMX8MQ_RESET_PCIEPHY2_PERST 35 /* i.MX8MM does NOT support */ -#define IMX8MQ_RESET_PCIE2_CTRL_APPS_EN 36 /* i.MX8MM does NOT support */ -#define IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF 37 /* i.MX8MM does NOT support */ -#define IMX8MQ_RESET_MIPI_CSI1_CORE_RESET 38 /* i.MX8MM does NOT support */ -#define IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET 39 /* i.MX8MM does NOT support */ -#define IMX8MQ_RESET_MIPI_CSI1_ESC_RESET 40 /* i.MX8MM does NOT support */ -#define IMX8MQ_RESET_MIPI_CSI2_CORE_RESET 41 /* i.MX8MM does NOT support */ -#define IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET 42 /* i.MX8MM does NOT support */ -#define IMX8MQ_RESET_MIPI_CSI2_ESC_RESET 43 /* i.MX8MM does NOT support */ -#define IMX8MQ_RESET_DDRC1_PRST 44 -#define IMX8MQ_RESET_DDRC1_CORE_RESET 45 -#define IMX8MQ_RESET_DDRC1_PHY_RESET 46 -#define IMX8MQ_RESET_DDRC2_PRST 47 /* i.MX8MM does NOT support */ -#define IMX8MQ_RESET_DDRC2_CORE_RESET 48 /* i.MX8MM does NOT support */ -#define IMX8MQ_RESET_DDRC2_PHY_RESET 49 /* i.MX8MM does NOT support */ - -#define IMX8MQ_RESET_NUM 50 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/reset/mt2701-resets.h b/sys/gnu/dts/include/dt-bindings/reset/mt2701-resets.h deleted file mode 100644 index 91e4200fd74..00000000000 --- a/sys/gnu/dts/include/dt-bindings/reset/mt2701-resets.h +++ /dev/null @@ -1,85 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2015 MediaTek, Shunli Wang - */ - -#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT2701 -#define _DT_BINDINGS_RESET_CONTROLLER_MT2701 - -/* INFRACFG resets */ -#define MT2701_INFRA_EMI_REG_RST 0 -#define MT2701_INFRA_DRAMC0_A0_RST 1 -#define MT2701_INFRA_FHCTL_RST 2 -#define MT2701_INFRA_APCIRQ_EINT_RST 3 -#define MT2701_INFRA_APXGPT_RST 4 -#define MT2701_INFRA_SCPSYS_RST 5 -#define MT2701_INFRA_KP_RST 6 -#define MT2701_INFRA_PMIC_WRAP_RST 7 -#define MT2701_INFRA_MIPI_RST 8 -#define MT2701_INFRA_IRRX_RST 9 -#define MT2701_INFRA_CEC_RST 10 -#define MT2701_INFRA_EMI_RST 32 -#define MT2701_INFRA_DRAMC0_RST 34 -#define MT2701_INFRA_TRNG_RST 37 -#define MT2701_INFRA_SYSIRQ_RST 38 - -/* PERICFG resets */ -#define MT2701_PERI_UART0_SW_RST 0 -#define MT2701_PERI_UART1_SW_RST 1 -#define MT2701_PERI_UART2_SW_RST 2 -#define MT2701_PERI_UART3_SW_RST 3 -#define MT2701_PERI_GCPU_SW_RST 5 -#define MT2701_PERI_BTIF_SW_RST 6 -#define MT2701_PERI_PWM_SW_RST 8 -#define MT2701_PERI_AUXADC_SW_RST 10 -#define MT2701_PERI_DMA_SW_RST 11 -#define MT2701_PERI_NFI_SW_RST 14 -#define MT2701_PERI_NLI_SW_RST 15 -#define MT2701_PERI_THERM_SW_RST 16 -#define MT2701_PERI_MSDC2_SW_RST 17 -#define MT2701_PERI_MSDC0_SW_RST 19 -#define MT2701_PERI_MSDC1_SW_RST 20 -#define MT2701_PERI_I2C0_SW_RST 22 -#define MT2701_PERI_I2C1_SW_RST 23 -#define MT2701_PERI_I2C2_SW_RST 24 -#define MT2701_PERI_I2C3_SW_RST 25 -#define MT2701_PERI_USB_SW_RST 28 -#define MT2701_PERI_ETH_SW_RST 29 -#define MT2701_PERI_SPI0_SW_RST 33 - -/* TOPRGU resets */ -#define MT2701_TOPRGU_INFRA_RST 0 -#define MT2701_TOPRGU_MM_RST 1 -#define MT2701_TOPRGU_MFG_RST 2 -#define MT2701_TOPRGU_ETHDMA_RST 3 -#define MT2701_TOPRGU_VDEC_RST 4 -#define MT2701_TOPRGU_VENC_IMG_RST 5 -#define MT2701_TOPRGU_DDRPHY_RST 6 -#define MT2701_TOPRGU_MD_RST 7 -#define MT2701_TOPRGU_INFRA_AO_RST 8 -#define MT2701_TOPRGU_CONN_RST 9 -#define MT2701_TOPRGU_APMIXED_RST 10 -#define MT2701_TOPRGU_HIFSYS_RST 11 -#define MT2701_TOPRGU_CONN_MCU_RST 12 -#define MT2701_TOPRGU_BDP_DISP_RST 13 - -/* HIFSYS resets */ -#define MT2701_HIFSYS_UHOST0_RST 3 -#define MT2701_HIFSYS_UHOST1_RST 4 -#define MT2701_HIFSYS_UPHY0_RST 21 -#define MT2701_HIFSYS_UPHY1_RST 22 -#define MT2701_HIFSYS_PCIE0_RST 24 -#define MT2701_HIFSYS_PCIE1_RST 25 -#define MT2701_HIFSYS_PCIE2_RST 26 - -/* ETHSYS resets */ -#define MT2701_ETHSYS_SYS_RST 0 -#define MT2701_ETHSYS_MCM_RST 2 -#define MT2701_ETHSYS_FE_RST 6 -#define MT2701_ETHSYS_GMAC_RST 23 -#define MT2701_ETHSYS_PPE_RST 31 - -/* G3DSYS resets */ -#define MT2701_G3DSYS_CORE_RST 0 - -#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT2701 */ diff --git a/sys/gnu/dts/include/dt-bindings/reset/mt7622-reset.h b/sys/gnu/dts/include/dt-bindings/reset/mt7622-reset.h deleted file mode 100644 index da0d1ae81cb..00000000000 --- a/sys/gnu/dts/include/dt-bindings/reset/mt7622-reset.h +++ /dev/null @@ -1,86 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2017 MediaTek Inc. - * Author: Sean Wang - */ - -#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT7622 -#define _DT_BINDINGS_RESET_CONTROLLER_MT7622 - -/* INFRACFG resets */ -#define MT7622_INFRA_EMI_REG_RST 0 -#define MT7622_INFRA_DRAMC0_A0_RST 1 -#define MT7622_INFRA_APCIRQ_EINT_RST 3 -#define MT7622_INFRA_APXGPT_RST 4 -#define MT7622_INFRA_SCPSYS_RST 5 -#define MT7622_INFRA_PMIC_WRAP_RST 7 -#define MT7622_INFRA_IRRX_RST 9 -#define MT7622_INFRA_EMI_RST 16 -#define MT7622_INFRA_WED0_RST 17 -#define MT7622_INFRA_DRAMC_RST 18 -#define MT7622_INFRA_CCI_INTF_RST 19 -#define MT7622_INFRA_TRNG_RST 21 -#define MT7622_INFRA_SYSIRQ_RST 22 -#define MT7622_INFRA_WED1_RST 25 - -/* PERICFG Subsystem resets */ -#define MT7622_PERI_UART0_SW_RST 0 -#define MT7622_PERI_UART1_SW_RST 1 -#define MT7622_PERI_UART2_SW_RST 2 -#define MT7622_PERI_UART3_SW_RST 3 -#define MT7622_PERI_UART4_SW_RST 4 -#define MT7622_PERI_BTIF_SW_RST 6 -#define MT7622_PERI_PWM_SW_RST 8 -#define MT7622_PERI_AUXADC_SW_RST 10 -#define MT7622_PERI_DMA_SW_RST 11 -#define MT7622_PERI_IRTX_SW_RST 13 -#define MT7622_PERI_NFI_SW_RST 14 -#define MT7622_PERI_THERM_SW_RST 16 -#define MT7622_PERI_MSDC0_SW_RST 19 -#define MT7622_PERI_MSDC1_SW_RST 20 -#define MT7622_PERI_I2C0_SW_RST 22 -#define MT7622_PERI_I2C1_SW_RST 23 -#define MT7622_PERI_I2C2_SW_RST 24 -#define MT7622_PERI_SPI0_SW_RST 33 -#define MT7622_PERI_SPI1_SW_RST 34 -#define MT7622_PERI_FLASHIF_SW_RST 36 - -/* TOPRGU resets */ -#define MT7622_TOPRGU_INFRA_RST 0 -#define MT7622_TOPRGU_ETHDMA_RST 1 -#define MT7622_TOPRGU_DDRPHY_RST 6 -#define MT7622_TOPRGU_INFRA_AO_RST 8 -#define MT7622_TOPRGU_CONN_RST 9 -#define MT7622_TOPRGU_APMIXED_RST 10 -#define MT7622_TOPRGU_CONN_MCU_RST 12 - -/* PCIe/SATA Subsystem resets */ -#define MT7622_SATA_PHY_REG_RST 12 -#define MT7622_SATA_PHY_SW_RST 13 -#define MT7622_SATA_AXI_BUS_RST 15 -#define MT7622_PCIE1_CORE_RST 19 -#define MT7622_PCIE1_MMIO_RST 20 -#define MT7622_PCIE1_HRST 21 -#define MT7622_PCIE1_USER_RST 22 -#define MT7622_PCIE1_PIPE_RST 23 -#define MT7622_PCIE0_CORE_RST 27 -#define MT7622_PCIE0_MMIO_RST 28 -#define MT7622_PCIE0_HRST 29 -#define MT7622_PCIE0_USER_RST 30 -#define MT7622_PCIE0_PIPE_RST 31 - -/* SSUSB Subsystem resets */ -#define MT7622_SSUSB_PHY_PWR_RST 3 -#define MT7622_SSUSB_MAC_PWR_RST 4 - -/* ETHSYS Subsystem resets */ -#define MT7622_ETHSYS_SYS_RST 0 -#define MT7622_ETHSYS_MCM_RST 2 -#define MT7622_ETHSYS_HSDMA_RST 5 -#define MT7622_ETHSYS_FE_RST 6 -#define MT7622_ETHSYS_GMAC_RST 23 -#define MT7622_ETHSYS_EPHY_RST 24 -#define MT7622_ETHSYS_CRYPTO_RST 29 -#define MT7622_ETHSYS_PPE_RST 31 - -#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT7622 */ diff --git a/sys/gnu/dts/include/dt-bindings/reset/mt7629-resets.h b/sys/gnu/dts/include/dt-bindings/reset/mt7629-resets.h deleted file mode 100644 index 6bb85734f68..00000000000 --- a/sys/gnu/dts/include/dt-bindings/reset/mt7629-resets.h +++ /dev/null @@ -1,71 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2019 MediaTek Inc. - */ - -#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT7629 -#define _DT_BINDINGS_RESET_CONTROLLER_MT7629 - -/* INFRACFG resets */ -#define MT7629_INFRA_EMI_MPU_RST 0 -#define MT7629_INFRA_UART5_RST 2 -#define MT7629_INFRA_CIRQ_EINT_RST 3 -#define MT7629_INFRA_APXGPT_RST 4 -#define MT7629_INFRA_SCPSYS_RST 5 -#define MT7629_INFRA_KP_RST 6 -#define MT7629_INFRA_SPI1_RST 7 -#define MT7629_INFRA_SPI4_RST 8 -#define MT7629_INFRA_SYSTIMER_RST 9 -#define MT7629_INFRA_IRRX_RST 10 -#define MT7629_INFRA_AO_BUS_RST 16 -#define MT7629_INFRA_EMI_RST 32 -#define MT7629_INFRA_APMIXED_RST 35 -#define MT7629_INFRA_MIPI_RST 36 -#define MT7629_INFRA_TRNG_RST 37 -#define MT7629_INFRA_SYSCIRQ_RST 38 -#define MT7629_INFRA_MIPI_CSI_RST 39 -#define MT7629_INFRA_GCE_FAXI_RST 40 -#define MT7629_INFRA_I2C_SRAM_RST 41 -#define MT7629_INFRA_IOMMU_RST 47 - -/* PERICFG resets */ -#define MT7629_PERI_UART0_SW_RST 0 -#define MT7629_PERI_UART1_SW_RST 1 -#define MT7629_PERI_UART2_SW_RST 2 -#define MT7629_PERI_BTIF_SW_RST 6 -#define MT7629_PERI_PWN_SW_RST 8 -#define MT7629_PERI_DMA_SW_RST 11 -#define MT7629_PERI_NFI_SW_RST 14 -#define MT7629_PERI_I2C0_SW_RST 22 -#define MT7629_PERI_SPI0_SW_RST 33 -#define MT7629_PERI_SPI1_SW_RST 34 -#define MT7629_PERI_FLASHIF_SW_RST 36 - -/* PCIe Subsystem resets */ -#define MT7629_PCIE1_CORE_RST 19 -#define MT7629_PCIE1_MMIO_RST 20 -#define MT7629_PCIE1_HRST 21 -#define MT7629_PCIE1_USER_RST 22 -#define MT7629_PCIE1_PIPE_RST 23 -#define MT7629_PCIE0_CORE_RST 27 -#define MT7629_PCIE0_MMIO_RST 28 -#define MT7629_PCIE0_HRST 29 -#define MT7629_PCIE0_USER_RST 30 -#define MT7629_PCIE0_PIPE_RST 31 - -/* SSUSB Subsystem resets */ -#define MT7629_SSUSB_PHY_PWR_RST 3 -#define MT7629_SSUSB_MAC_PWR_RST 4 - -/* ETH Subsystem resets */ -#define MT7629_ETHSYS_SYS_RST 0 -#define MT7629_ETHSYS_MCM_RST 2 -#define MT7629_ETHSYS_HSDMA_RST 5 -#define MT7629_ETHSYS_FE_RST 6 -#define MT7629_ETHSYS_ESW_RST 16 -#define MT7629_ETHSYS_GMAC_RST 23 -#define MT7629_ETHSYS_EPHY_RST 24 -#define MT7629_ETHSYS_CRYPTO_RST 29 -#define MT7629_ETHSYS_PPE_RST 31 - -#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT7629 */ diff --git a/sys/gnu/dts/include/dt-bindings/reset/mt8135-resets.h b/sys/gnu/dts/include/dt-bindings/reset/mt8135-resets.h deleted file mode 100644 index 8c060d08716..00000000000 --- a/sys/gnu/dts/include/dt-bindings/reset/mt8135-resets.h +++ /dev/null @@ -1,56 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2014 MediaTek Inc. - * Author: Flora Fu, MediaTek - */ - -#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8135 -#define _DT_BINDINGS_RESET_CONTROLLER_MT8135 - -/* INFRACFG resets */ -#define MT8135_INFRA_EMI_REG_RST 0 -#define MT8135_INFRA_DRAMC0_A0_RST 1 -#define MT8135_INFRA_CCIF0_RST 2 -#define MT8135_INFRA_APCIRQ_EINT_RST 3 -#define MT8135_INFRA_APXGPT_RST 4 -#define MT8135_INFRA_SCPSYS_RST 5 -#define MT8135_INFRA_CCIF1_RST 6 -#define MT8135_INFRA_PMIC_WRAP_RST 7 -#define MT8135_INFRA_KP_RST 8 -#define MT8135_INFRA_EMI_RST 32 -#define MT8135_INFRA_DRAMC0_RST 34 -#define MT8135_INFRA_SMI_RST 35 -#define MT8135_INFRA_M4U_RST 36 - -/* PERICFG resets */ -#define MT8135_PERI_UART0_SW_RST 0 -#define MT8135_PERI_UART1_SW_RST 1 -#define MT8135_PERI_UART2_SW_RST 2 -#define MT8135_PERI_UART3_SW_RST 3 -#define MT8135_PERI_IRDA_SW_RST 4 -#define MT8135_PERI_PTP_SW_RST 5 -#define MT8135_PERI_AP_HIF_SW_RST 6 -#define MT8135_PERI_GPCU_SW_RST 7 -#define MT8135_PERI_MD_HIF_SW_RST 8 -#define MT8135_PERI_NLI_SW_RST 9 -#define MT8135_PERI_AUXADC_SW_RST 10 -#define MT8135_PERI_DMA_SW_RST 11 -#define MT8135_PERI_NFI_SW_RST 14 -#define MT8135_PERI_PWM_SW_RST 15 -#define MT8135_PERI_THERM_SW_RST 16 -#define MT8135_PERI_MSDC0_SW_RST 17 -#define MT8135_PERI_MSDC1_SW_RST 18 -#define MT8135_PERI_MSDC2_SW_RST 19 -#define MT8135_PERI_MSDC3_SW_RST 20 -#define MT8135_PERI_I2C0_SW_RST 22 -#define MT8135_PERI_I2C1_SW_RST 23 -#define MT8135_PERI_I2C2_SW_RST 24 -#define MT8135_PERI_I2C3_SW_RST 25 -#define MT8135_PERI_I2C4_SW_RST 26 -#define MT8135_PERI_I2C5_SW_RST 27 -#define MT8135_PERI_I2C6_SW_RST 28 -#define MT8135_PERI_USB_SW_RST 29 -#define MT8135_PERI_SPI1_SW_RST 33 -#define MT8135_PERI_PWRAP_BRIDGE_SW_RST 34 - -#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8135 */ diff --git a/sys/gnu/dts/include/dt-bindings/reset/mt8173-resets.h b/sys/gnu/dts/include/dt-bindings/reset/mt8173-resets.h deleted file mode 100644 index ba8636eda5a..00000000000 --- a/sys/gnu/dts/include/dt-bindings/reset/mt8173-resets.h +++ /dev/null @@ -1,55 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2014 MediaTek Inc. - * Author: Flora Fu, MediaTek - */ - -#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8173 -#define _DT_BINDINGS_RESET_CONTROLLER_MT8173 - -/* INFRACFG resets */ -#define MT8173_INFRA_EMI_REG_RST 0 -#define MT8173_INFRA_DRAMC0_A0_RST 1 -#define MT8173_INFRA_APCIRQ_EINT_RST 3 -#define MT8173_INFRA_APXGPT_RST 4 -#define MT8173_INFRA_SCPSYS_RST 5 -#define MT8173_INFRA_KP_RST 6 -#define MT8173_INFRA_PMIC_WRAP_RST 7 -#define MT8173_INFRA_MPIP_RST 8 -#define MT8173_INFRA_CEC_RST 9 -#define MT8173_INFRA_EMI_RST 32 -#define MT8173_INFRA_DRAMC0_RST 34 -#define MT8173_INFRA_APMIXEDSYS_RST 35 -#define MT8173_INFRA_MIPI_DSI_RST 36 -#define MT8173_INFRA_TRNG_RST 37 -#define MT8173_INFRA_SYSIRQ_RST 38 -#define MT8173_INFRA_MIPI_CSI_RST 39 -#define MT8173_INFRA_GCE_FAXI_RST 40 -#define MT8173_INFRA_MMIOMMURST 47 - - -/* PERICFG resets */ -#define MT8173_PERI_UART0_SW_RST 0 -#define MT8173_PERI_UART1_SW_RST 1 -#define MT8173_PERI_UART2_SW_RST 2 -#define MT8173_PERI_UART3_SW_RST 3 -#define MT8173_PERI_IRRX_SW_RST 4 -#define MT8173_PERI_PWM_SW_RST 8 -#define MT8173_PERI_AUXADC_SW_RST 10 -#define MT8173_PERI_DMA_SW_RST 11 -#define MT8173_PERI_I2C6_SW_RST 13 -#define MT8173_PERI_NFI_SW_RST 14 -#define MT8173_PERI_THERM_SW_RST 16 -#define MT8173_PERI_MSDC2_SW_RST 17 -#define MT8173_PERI_MSDC3_SW_RST 18 -#define MT8173_PERI_MSDC0_SW_RST 19 -#define MT8173_PERI_MSDC1_SW_RST 20 -#define MT8173_PERI_I2C0_SW_RST 22 -#define MT8173_PERI_I2C1_SW_RST 23 -#define MT8173_PERI_I2C2_SW_RST 24 -#define MT8173_PERI_I2C3_SW_RST 25 -#define MT8173_PERI_I2C4_SW_RST 26 -#define MT8173_PERI_HDMI_SW_RST 29 -#define MT8173_PERI_SPI0_SW_RST 33 - -#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8173 */ diff --git a/sys/gnu/dts/include/dt-bindings/reset/nuvoton,npcm7xx-reset.h b/sys/gnu/dts/include/dt-bindings/reset/nuvoton,npcm7xx-reset.h deleted file mode 100644 index df088e68a9b..00000000000 --- a/sys/gnu/dts/include/dt-bindings/reset/nuvoton,npcm7xx-reset.h +++ /dev/null @@ -1,91 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -// Copyright (c) 2019 Nuvoton Technology corporation. - -#ifndef _DT_BINDINGS_NPCM7XX_RESET_H -#define _DT_BINDINGS_NPCM7XX_RESET_H - -#define NPCM7XX_RESET_IPSRST1 0x20 -#define NPCM7XX_RESET_IPSRST2 0x24 -#define NPCM7XX_RESET_IPSRST3 0x34 - -/* Reset lines on IP1 reset module (NPCM7XX_RESET_IPSRST1) */ -#define NPCM7XX_RESET_FIU3 1 -#define NPCM7XX_RESET_UDC1 5 -#define NPCM7XX_RESET_EMC1 6 -#define NPCM7XX_RESET_UART_2_3 7 -#define NPCM7XX_RESET_UDC2 8 -#define NPCM7XX_RESET_PECI 9 -#define NPCM7XX_RESET_AES 10 -#define NPCM7XX_RESET_UART_0_1 11 -#define NPCM7XX_RESET_MC 12 -#define NPCM7XX_RESET_SMB2 13 -#define NPCM7XX_RESET_SMB3 14 -#define NPCM7XX_RESET_SMB4 15 -#define NPCM7XX_RESET_SMB5 16 -#define NPCM7XX_RESET_PWM_M0 18 -#define NPCM7XX_RESET_TIMER_0_4 19 -#define NPCM7XX_RESET_TIMER_5_9 20 -#define NPCM7XX_RESET_EMC2 21 -#define NPCM7XX_RESET_UDC4 22 -#define NPCM7XX_RESET_UDC5 23 -#define NPCM7XX_RESET_UDC6 24 -#define NPCM7XX_RESET_UDC3 25 -#define NPCM7XX_RESET_ADC 27 -#define NPCM7XX_RESET_SMB6 28 -#define NPCM7XX_RESET_SMB7 29 -#define NPCM7XX_RESET_SMB0 30 -#define NPCM7XX_RESET_SMB1 31 - -/* Reset lines on IP2 reset module (NPCM7XX_RESET_IPSRST2) */ -#define NPCM7XX_RESET_MFT0 0 -#define NPCM7XX_RESET_MFT1 1 -#define NPCM7XX_RESET_MFT2 2 -#define NPCM7XX_RESET_MFT3 3 -#define NPCM7XX_RESET_MFT4 4 -#define NPCM7XX_RESET_MFT5 5 -#define NPCM7XX_RESET_MFT6 6 -#define NPCM7XX_RESET_MFT7 7 -#define NPCM7XX_RESET_MMC 8 -#define NPCM7XX_RESET_SDHC 9 -#define NPCM7XX_RESET_GFX_SYS 10 -#define NPCM7XX_RESET_AHB_PCIBRG 11 -#define NPCM7XX_RESET_VDMA 12 -#define NPCM7XX_RESET_ECE 13 -#define NPCM7XX_RESET_VCD 14 -#define NPCM7XX_RESET_OTP 16 -#define NPCM7XX_RESET_SIOX1 18 -#define NPCM7XX_RESET_SIOX2 19 -#define NPCM7XX_RESET_3DES 21 -#define NPCM7XX_RESET_PSPI1 22 -#define NPCM7XX_RESET_PSPI2 23 -#define NPCM7XX_RESET_GMAC2 25 -#define NPCM7XX_RESET_USB_HOST 26 -#define NPCM7XX_RESET_GMAC1 28 -#define NPCM7XX_RESET_CP 31 - -/* Reset lines on IP3 reset module (NPCM7XX_RESET_IPSRST3) */ -#define NPCM7XX_RESET_PWM_M1 0 -#define NPCM7XX_RESET_SMB12 1 -#define NPCM7XX_RESET_SPIX 2 -#define NPCM7XX_RESET_SMB13 3 -#define NPCM7XX_RESET_UDC0 4 -#define NPCM7XX_RESET_UDC7 5 -#define NPCM7XX_RESET_UDC8 6 -#define NPCM7XX_RESET_UDC9 7 -#define NPCM7XX_RESET_PCI_MAILBOX 9 -#define NPCM7XX_RESET_SMB14 12 -#define NPCM7XX_RESET_SHA 13 -#define NPCM7XX_RESET_SEC_ECC 14 -#define NPCM7XX_RESET_PCIE_RC 15 -#define NPCM7XX_RESET_TIMER_10_14 16 -#define NPCM7XX_RESET_RNG 17 -#define NPCM7XX_RESET_SMB15 18 -#define NPCM7XX_RESET_SMB8 19 -#define NPCM7XX_RESET_SMB9 20 -#define NPCM7XX_RESET_SMB10 21 -#define NPCM7XX_RESET_SMB11 22 -#define NPCM7XX_RESET_ESPI 23 -#define NPCM7XX_RESET_USB_PHY_1 24 -#define NPCM7XX_RESET_USB_PHY_2 25 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/reset/oxsemi,ox810se.h b/sys/gnu/dts/include/dt-bindings/reset/oxsemi,ox810se.h deleted file mode 100644 index e943187e652..00000000000 --- a/sys/gnu/dts/include/dt-bindings/reset/oxsemi,ox810se.h +++ /dev/null @@ -1,42 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) 2016 Neil Armstrong - */ - -#ifndef DT_RESET_OXSEMI_OX810SE_H -#define DT_RESET_OXSEMI_OX810SE_H - -#define RESET_ARM 0 -#define RESET_COPRO 1 -/* Reserved 2 */ -/* Reserved 3 */ -#define RESET_USBHS 4 -#define RESET_USBHSPHY 5 -#define RESET_MAC 6 -#define RESET_PCI 7 -#define RESET_DMA 8 -#define RESET_DPE 9 -#define RESET_DDR 10 -#define RESET_SATA 11 -#define RESET_SATA_LINK 12 -#define RESET_SATA_PHY 13 - /* Reserved 14 */ -#define RESET_NAND 15 -#define RESET_GPIO 16 -#define RESET_UART1 17 -#define RESET_UART2 18 -#define RESET_MISC 19 -#define RESET_I2S 20 -#define RESET_AHB_MON 21 -#define RESET_UART3 22 -#define RESET_UART4 23 -#define RESET_SGDMA 24 -/* Reserved 25 */ -/* Reserved 26 */ -/* Reserved 27 */ -/* Reserved 28 */ -/* Reserved 29 */ -/* Reserved 30 */ -#define RESET_BUS 31 - -#endif /* DT_RESET_OXSEMI_OX810SE_H */ diff --git a/sys/gnu/dts/include/dt-bindings/reset/oxsemi,ox820.h b/sys/gnu/dts/include/dt-bindings/reset/oxsemi,ox820.h deleted file mode 100644 index 54b58e09c1c..00000000000 --- a/sys/gnu/dts/include/dt-bindings/reset/oxsemi,ox820.h +++ /dev/null @@ -1,42 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) 2016 Neil Armstrong - */ - -#ifndef DT_RESET_OXSEMI_OX820_H -#define DT_RESET_OXSEMI_OX820_H - -#define RESET_SCU 0 -#define RESET_LEON 1 -#define RESET_ARM0 2 -#define RESET_ARM1 3 -#define RESET_USBHS 4 -#define RESET_USBPHYA 5 -#define RESET_MAC 6 -#define RESET_PCIEA 7 -#define RESET_SGDMA 8 -#define RESET_CIPHER 9 -#define RESET_DDR 10 -#define RESET_SATA 11 -#define RESET_SATA_LINK 12 -#define RESET_SATA_PHY 13 -#define RESET_PCIEPHY 14 -#define RESET_NAND 15 -#define RESET_GPIO 16 -#define RESET_UART1 17 -#define RESET_UART2 18 -#define RESET_MISC 19 -#define RESET_I2S 20 -#define RESET_SD 21 -#define RESET_MAC_2 22 -#define RESET_PCIEB 23 -#define RESET_VIDEO 24 -#define RESET_DDR_PHY 25 -#define RESET_USBPHYB 26 -#define RESET_USBDEV 27 -/* Reserved 29 */ -#define RESET_ARMDBG 29 -#define RESET_PLLA 30 -#define RESET_PLLB 31 - -#endif /* DT_RESET_OXSEMI_OX820_H */ diff --git a/sys/gnu/dts/include/dt-bindings/reset/pistachio-resets.h b/sys/gnu/dts/include/dt-bindings/reset/pistachio-resets.h deleted file mode 100644 index 5bb4dd0d637..00000000000 --- a/sys/gnu/dts/include/dt-bindings/reset/pistachio-resets.h +++ /dev/null @@ -1,37 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides constants for the reset controller - * present in the Pistachio SoC - */ - -#ifndef _PISTACHIO_RESETS_H -#define _PISTACHIO_RESETS_H - -#define PISTACHIO_RESET_I2C0 0 -#define PISTACHIO_RESET_I2C1 1 -#define PISTACHIO_RESET_I2C2 2 -#define PISTACHIO_RESET_I2C3 3 -#define PISTACHIO_RESET_I2S_IN 4 -#define PISTACHIO_RESET_PRL_OUT 5 -#define PISTACHIO_RESET_SPDIF_OUT 6 -#define PISTACHIO_RESET_SPI 7 -#define PISTACHIO_RESET_PWM_PDM 8 -#define PISTACHIO_RESET_UART0 9 -#define PISTACHIO_RESET_UART1 10 -#define PISTACHIO_RESET_QSPI 11 -#define PISTACHIO_RESET_MDC 12 -#define PISTACHIO_RESET_SDHOST 13 -#define PISTACHIO_RESET_ETHERNET 14 -#define PISTACHIO_RESET_IR 15 -#define PISTACHIO_RESET_HASH 16 -#define PISTACHIO_RESET_TIMER 17 -#define PISTACHIO_RESET_I2S_OUT 18 -#define PISTACHIO_RESET_SPDIF_IN 19 -#define PISTACHIO_RESET_EVT 20 -#define PISTACHIO_RESET_USB_H 21 -#define PISTACHIO_RESET_USB_PR 22 -#define PISTACHIO_RESET_USB_PHY_PR 23 -#define PISTACHIO_RESET_USB_PHY_PON 24 -#define PISTACHIO_RESET_MAX 24 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/reset/qcom,gcc-apq8084.h b/sys/gnu/dts/include/dt-bindings/reset/qcom,gcc-apq8084.h deleted file mode 100644 index e76be38342c..00000000000 --- a/sys/gnu/dts/include/dt-bindings/reset/qcom,gcc-apq8084.h +++ /dev/null @@ -1,101 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2014, The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_RESET_APQ_GCC_8084_H -#define _DT_BINDINGS_RESET_APQ_GCC_8084_H - -#define GCC_SYSTEM_NOC_BCR 0 -#define GCC_CONFIG_NOC_BCR 1 -#define GCC_PERIPH_NOC_BCR 2 -#define GCC_IMEM_BCR 3 -#define GCC_MMSS_BCR 4 -#define GCC_QDSS_BCR 5 -#define GCC_USB_30_BCR 6 -#define GCC_USB3_PHY_BCR 7 -#define GCC_USB_HS_HSIC_BCR 8 -#define GCC_USB_HS_BCR 9 -#define GCC_USB2A_PHY_BCR 10 -#define GCC_USB2B_PHY_BCR 11 -#define GCC_SDCC1_BCR 12 -#define GCC_SDCC2_BCR 13 -#define GCC_SDCC3_BCR 14 -#define GCC_SDCC4_BCR 15 -#define GCC_BLSP1_BCR 16 -#define GCC_BLSP1_QUP1_BCR 17 -#define GCC_BLSP1_UART1_BCR 18 -#define GCC_BLSP1_QUP2_BCR 19 -#define GCC_BLSP1_UART2_BCR 20 -#define GCC_BLSP1_QUP3_BCR 21 -#define GCC_BLSP1_UART3_BCR 22 -#define GCC_BLSP1_QUP4_BCR 23 -#define GCC_BLSP1_UART4_BCR 24 -#define GCC_BLSP1_QUP5_BCR 25 -#define GCC_BLSP1_UART5_BCR 26 -#define GCC_BLSP1_QUP6_BCR 27 -#define GCC_BLSP1_UART6_BCR 28 -#define GCC_BLSP2_BCR 29 -#define GCC_BLSP2_QUP1_BCR 30 -#define GCC_BLSP2_UART1_BCR 31 -#define GCC_BLSP2_QUP2_BCR 32 -#define GCC_BLSP2_UART2_BCR 33 -#define GCC_BLSP2_QUP3_BCR 34 -#define GCC_BLSP2_UART3_BCR 35 -#define GCC_BLSP2_QUP4_BCR 36 -#define GCC_BLSP2_UART4_BCR 37 -#define GCC_BLSP2_QUP5_BCR 38 -#define GCC_BLSP2_UART5_BCR 39 -#define GCC_BLSP2_QUP6_BCR 40 -#define GCC_BLSP2_UART6_BCR 41 -#define GCC_PDM_BCR 42 -#define GCC_PRNG_BCR 43 -#define GCC_BAM_DMA_BCR 44 -#define GCC_TSIF_BCR 45 -#define GCC_TCSR_BCR 46 -#define GCC_BOOT_ROM_BCR 47 -#define GCC_MSG_RAM_BCR 48 -#define GCC_TLMM_BCR 49 -#define GCC_MPM_BCR 50 -#define GCC_MPM_AHB_RESET 51 -#define GCC_MPM_NON_AHB_RESET 52 -#define GCC_SEC_CTRL_BCR 53 -#define GCC_SPMI_BCR 54 -#define GCC_SPDM_BCR 55 -#define GCC_CE1_BCR 56 -#define GCC_CE2_BCR 57 -#define GCC_BIMC_BCR 58 -#define GCC_SNOC_BUS_TIMEOUT0_BCR 59 -#define GCC_SNOC_BUS_TIMEOUT2_BCR 60 -#define GCC_PNOC_BUS_TIMEOUT0_BCR 61 -#define GCC_PNOC_BUS_TIMEOUT1_BCR 62 -#define GCC_PNOC_BUS_TIMEOUT2_BCR 63 -#define GCC_PNOC_BUS_TIMEOUT3_BCR 64 -#define GCC_PNOC_BUS_TIMEOUT4_BCR 65 -#define GCC_CNOC_BUS_TIMEOUT0_BCR 66 -#define GCC_CNOC_BUS_TIMEOUT1_BCR 67 -#define GCC_CNOC_BUS_TIMEOUT2_BCR 68 -#define GCC_CNOC_BUS_TIMEOUT3_BCR 69 -#define GCC_CNOC_BUS_TIMEOUT4_BCR 70 -#define GCC_CNOC_BUS_TIMEOUT5_BCR 71 -#define GCC_CNOC_BUS_TIMEOUT6_BCR 72 -#define GCC_DEHR_BCR 73 -#define GCC_RBCPR_BCR 74 -#define GCC_MSS_RESTART 75 -#define GCC_LPASS_RESTART 76 -#define GCC_WCSS_RESTART 77 -#define GCC_VENUS_RESTART 78 -#define GCC_COPSS_SMMU_BCR 79 -#define GCC_SPSS_BCR 80 -#define GCC_PCIE_0_BCR 81 -#define GCC_PCIE_0_PHY_BCR 82 -#define GCC_PCIE_1_BCR 83 -#define GCC_PCIE_1_PHY_BCR 84 -#define GCC_USB_30_SEC_BCR 85 -#define GCC_USB3_SEC_PHY_BCR 86 -#define GCC_SATA_BCR 87 -#define GCC_CE3_BCR 88 -#define GCC_UFS_BCR 89 -#define GCC_USB30_PHY_COM_BCR 90 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/reset/qcom,gcc-ipq6018.h b/sys/gnu/dts/include/dt-bindings/reset/qcom,gcc-ipq6018.h deleted file mode 100644 index 02a220ad010..00000000000 --- a/sys/gnu/dts/include/dt-bindings/reset/qcom,gcc-ipq6018.h +++ /dev/null @@ -1,157 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_RESET_IPQ_GCC_6018_H -#define _DT_BINDINGS_RESET_IPQ_GCC_6018_H - -#define GCC_BLSP1_BCR 0 -#define GCC_BLSP1_QUP1_BCR 1 -#define GCC_BLSP1_UART1_BCR 2 -#define GCC_BLSP1_QUP2_BCR 3 -#define GCC_BLSP1_UART2_BCR 4 -#define GCC_BLSP1_QUP3_BCR 5 -#define GCC_BLSP1_UART3_BCR 6 -#define GCC_BLSP1_QUP4_BCR 7 -#define GCC_BLSP1_UART4_BCR 8 -#define GCC_BLSP1_QUP5_BCR 9 -#define GCC_BLSP1_UART5_BCR 10 -#define GCC_BLSP1_QUP6_BCR 11 -#define GCC_BLSP1_UART6_BCR 12 -#define GCC_IMEM_BCR 13 -#define GCC_SMMU_BCR 14 -#define GCC_APSS_TCU_BCR 15 -#define GCC_SMMU_XPU_BCR 16 -#define GCC_PCNOC_TBU_BCR 17 -#define GCC_SMMU_CFG_BCR 18 -#define GCC_PRNG_BCR 19 -#define GCC_BOOT_ROM_BCR 20 -#define GCC_CRYPTO_BCR 21 -#define GCC_WCSS_BCR 22 -#define GCC_WCSS_Q6_BCR 23 -#define GCC_NSS_BCR 24 -#define GCC_SEC_CTRL_BCR 25 -#define GCC_DDRSS_BCR 26 -#define GCC_SYSTEM_NOC_BCR 27 -#define GCC_PCNOC_BCR 28 -#define GCC_TCSR_BCR 29 -#define GCC_QDSS_BCR 30 -#define GCC_DCD_BCR 31 -#define GCC_MSG_RAM_BCR 32 -#define GCC_MPM_BCR 33 -#define GCC_SPDM_BCR 34 -#define GCC_RBCPR_BCR 35 -#define GCC_RBCPR_MX_BCR 36 -#define GCC_TLMM_BCR 37 -#define GCC_RBCPR_WCSS_BCR 38 -#define GCC_USB0_PHY_BCR 39 -#define GCC_USB3PHY_0_PHY_BCR 40 -#define GCC_USB0_BCR 41 -#define GCC_USB1_BCR 42 -#define GCC_QUSB2_0_PHY_BCR 43 -#define GCC_QUSB2_1_PHY_BCR 44 -#define GCC_SDCC1_BCR 45 -#define GCC_SNOC_BUS_TIMEOUT0_BCR 46 -#define GCC_SNOC_BUS_TIMEOUT1_BCR 47 -#define GCC_SNOC_BUS_TIMEOUT2_BCR 48 -#define GCC_PCNOC_BUS_TIMEOUT0_BCR 49 -#define GCC_PCNOC_BUS_TIMEOUT1_BCR 50 -#define GCC_PCNOC_BUS_TIMEOUT2_BCR 51 -#define GCC_PCNOC_BUS_TIMEOUT3_BCR 52 -#define GCC_PCNOC_BUS_TIMEOUT4_BCR 53 -#define GCC_PCNOC_BUS_TIMEOUT5_BCR 54 -#define GCC_PCNOC_BUS_TIMEOUT6_BCR 55 -#define GCC_PCNOC_BUS_TIMEOUT7_BCR 56 -#define GCC_PCNOC_BUS_TIMEOUT8_BCR 57 -#define GCC_PCNOC_BUS_TIMEOUT9_BCR 58 -#define GCC_UNIPHY0_BCR 59 -#define GCC_UNIPHY1_BCR 60 -#define GCC_CMN_12GPLL_BCR 61 -#define GCC_QPIC_BCR 62 -#define GCC_MDIO_BCR 63 -#define GCC_WCSS_CORE_TBU_BCR 64 -#define GCC_WCSS_Q6_TBU_BCR 65 -#define GCC_USB0_TBU_BCR 66 -#define GCC_PCIE0_TBU_BCR 67 -#define GCC_PCIE0_BCR 68 -#define GCC_PCIE0_PHY_BCR 69 -#define GCC_PCIE0PHY_PHY_BCR 70 -#define GCC_PCIE0_LINK_DOWN_BCR 71 -#define GCC_DCC_BCR 72 -#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR 73 -#define GCC_SMMU_CATS_BCR 74 -#define GCC_UBI0_AXI_ARES 75 -#define GCC_UBI0_AHB_ARES 76 -#define GCC_UBI0_NC_AXI_ARES 77 -#define GCC_UBI0_DBG_ARES 78 -#define GCC_UBI0_CORE_CLAMP_ENABLE 79 -#define GCC_UBI0_CLKRST_CLAMP_ENABLE 80 -#define GCC_UBI0_UTCM_ARES 81 -#define GCC_NSS_CFG_ARES 82 -#define GCC_NSS_NOC_ARES 83 -#define GCC_NSS_CRYPTO_ARES 84 -#define GCC_NSS_CSR_ARES 85 -#define GCC_NSS_CE_APB_ARES 86 -#define GCC_NSS_CE_AXI_ARES 87 -#define GCC_NSSNOC_CE_APB_ARES 88 -#define GCC_NSSNOC_CE_AXI_ARES 89 -#define GCC_NSSNOC_UBI0_AHB_ARES 90 -#define GCC_NSSNOC_SNOC_ARES 91 -#define GCC_NSSNOC_CRYPTO_ARES 92 -#define GCC_NSSNOC_ATB_ARES 93 -#define GCC_NSSNOC_QOSGEN_REF_ARES 94 -#define GCC_NSSNOC_TIMEOUT_REF_ARES 95 -#define GCC_PCIE0_PIPE_ARES 96 -#define GCC_PCIE0_SLEEP_ARES 97 -#define GCC_PCIE0_CORE_STICKY_ARES 98 -#define GCC_PCIE0_AXI_MASTER_ARES 99 -#define GCC_PCIE0_AXI_SLAVE_ARES 100 -#define GCC_PCIE0_AHB_ARES 101 -#define GCC_PCIE0_AXI_MASTER_STICKY_ARES 102 -#define GCC_PCIE0_AXI_SLAVE_STICKY_ARES 103 -#define GCC_PPE_FULL_RESET 104 -#define GCC_UNIPHY0_SOFT_RESET 105 -#define GCC_UNIPHY0_XPCS_RESET 106 -#define GCC_UNIPHY1_SOFT_RESET 107 -#define GCC_UNIPHY1_XPCS_RESET 108 -#define GCC_EDMA_HW_RESET 109 -#define GCC_ADSS_BCR 110 -#define GCC_NSS_NOC_TBU_BCR 111 -#define GCC_NSSPORT1_RESET 112 -#define GCC_NSSPORT2_RESET 113 -#define GCC_NSSPORT3_RESET 114 -#define GCC_NSSPORT4_RESET 115 -#define GCC_NSSPORT5_RESET 116 -#define GCC_UNIPHY0_PORT1_ARES 117 -#define GCC_UNIPHY0_PORT2_ARES 118 -#define GCC_UNIPHY0_PORT3_ARES 119 -#define GCC_UNIPHY0_PORT4_ARES 120 -#define GCC_UNIPHY0_PORT5_ARES 121 -#define GCC_UNIPHY0_PORT_4_5_RESET 122 -#define GCC_UNIPHY0_PORT_4_RESET 123 -#define GCC_LPASS_BCR 124 -#define GCC_UBI32_TBU_BCR 125 -#define GCC_LPASS_TBU_BCR 126 -#define GCC_WCSSAON_RESET 127 -#define GCC_LPASS_Q6_AXIM_ARES 128 -#define GCC_LPASS_Q6SS_TSCTR_1TO2_ARES 129 -#define GCC_LPASS_Q6SS_TRIG_ARES 130 -#define GCC_LPASS_Q6_ATBM_AT_ARES 131 -#define GCC_LPASS_Q6_PCLKDBG_ARES 132 -#define GCC_LPASS_CORE_AXIM_ARES 133 -#define GCC_LPASS_SNOC_CFG_ARES 134 -#define GCC_WCSS_DBG_ARES 135 -#define GCC_WCSS_ECAHB_ARES 136 -#define GCC_WCSS_ACMT_ARES 137 -#define GCC_WCSS_DBG_BDG_ARES 138 -#define GCC_WCSS_AHB_S_ARES 139 -#define GCC_WCSS_AXI_M_ARES 140 -#define GCC_Q6SS_DBG_ARES 141 -#define GCC_Q6_AHB_S_ARES 142 -#define GCC_Q6_AHB_ARES 143 -#define GCC_Q6_AXIM2_ARES 144 -#define GCC_Q6_AXIM_ARES 145 -#define GCC_UBI0_CORE_ARES 146 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/reset/qcom,gcc-ipq806x.h b/sys/gnu/dts/include/dt-bindings/reset/qcom,gcc-ipq806x.h deleted file mode 100644 index 26b6f920062..00000000000 --- a/sys/gnu/dts/include/dt-bindings/reset/qcom,gcc-ipq806x.h +++ /dev/null @@ -1,167 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2014, The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_RESET_IPQ_806X_H -#define _DT_BINDINGS_RESET_IPQ_806X_H - -#define QDSS_STM_RESET 0 -#define AFAB_SMPSS_S_RESET 1 -#define AFAB_SMPSS_M1_RESET 2 -#define AFAB_SMPSS_M0_RESET 3 -#define AFAB_EBI1_CH0_RESET 4 -#define AFAB_EBI1_CH1_RESET 5 -#define SFAB_ADM0_M0_RESET 6 -#define SFAB_ADM0_M1_RESET 7 -#define SFAB_ADM0_M2_RESET 8 -#define ADM0_C2_RESET 9 -#define ADM0_C1_RESET 10 -#define ADM0_C0_RESET 11 -#define ADM0_PBUS_RESET 12 -#define ADM0_RESET 13 -#define QDSS_CLKS_SW_RESET 14 -#define QDSS_POR_RESET 15 -#define QDSS_TSCTR_RESET 16 -#define QDSS_HRESET_RESET 17 -#define QDSS_AXI_RESET 18 -#define QDSS_DBG_RESET 19 -#define SFAB_PCIE_M_RESET 20 -#define SFAB_PCIE_S_RESET 21 -#define PCIE_EXT_RESET 22 -#define PCIE_PHY_RESET 23 -#define PCIE_PCI_RESET 24 -#define PCIE_POR_RESET 25 -#define PCIE_HCLK_RESET 26 -#define PCIE_ACLK_RESET 27 -#define SFAB_LPASS_RESET 28 -#define SFAB_AFAB_M_RESET 29 -#define AFAB_SFAB_M0_RESET 30 -#define AFAB_SFAB_M1_RESET 31 -#define SFAB_SATA_S_RESET 32 -#define SFAB_DFAB_M_RESET 33 -#define DFAB_SFAB_M_RESET 34 -#define DFAB_SWAY0_RESET 35 -#define DFAB_SWAY1_RESET 36 -#define DFAB_ARB0_RESET 37 -#define DFAB_ARB1_RESET 38 -#define PPSS_PROC_RESET 39 -#define PPSS_RESET 40 -#define DMA_BAM_RESET 41 -#define SPS_TIC_H_RESET 42 -#define SFAB_CFPB_M_RESET 43 -#define SFAB_CFPB_S_RESET 44 -#define TSIF_H_RESET 45 -#define CE1_H_RESET 46 -#define CE1_CORE_RESET 47 -#define CE1_SLEEP_RESET 48 -#define CE2_H_RESET 49 -#define CE2_CORE_RESET 50 -#define SFAB_SFPB_M_RESET 51 -#define SFAB_SFPB_S_RESET 52 -#define RPM_PROC_RESET 53 -#define PMIC_SSBI2_RESET 54 -#define SDC1_RESET 55 -#define SDC2_RESET 56 -#define SDC3_RESET 57 -#define SDC4_RESET 58 -#define USB_HS1_RESET 59 -#define USB_HSIC_RESET 60 -#define USB_FS1_XCVR_RESET 61 -#define USB_FS1_RESET 62 -#define GSBI1_RESET 63 -#define GSBI2_RESET 64 -#define GSBI3_RESET 65 -#define GSBI4_RESET 66 -#define GSBI5_RESET 67 -#define GSBI6_RESET 68 -#define GSBI7_RESET 69 -#define SPDM_RESET 70 -#define SEC_CTRL_RESET 71 -#define TLMM_H_RESET 72 -#define SFAB_SATA_M_RESET 73 -#define SATA_RESET 74 -#define TSSC_RESET 75 -#define PDM_RESET 76 -#define MPM_H_RESET 77 -#define MPM_RESET 78 -#define SFAB_SMPSS_S_RESET 79 -#define PRNG_RESET 80 -#define SFAB_CE3_M_RESET 81 -#define SFAB_CE3_S_RESET 82 -#define CE3_SLEEP_RESET 83 -#define PCIE_1_M_RESET 84 -#define PCIE_1_S_RESET 85 -#define PCIE_1_EXT_RESET 86 -#define PCIE_1_PHY_RESET 87 -#define PCIE_1_PCI_RESET 88 -#define PCIE_1_POR_RESET 89 -#define PCIE_1_HCLK_RESET 90 -#define PCIE_1_ACLK_RESET 91 -#define PCIE_2_M_RESET 92 -#define PCIE_2_S_RESET 93 -#define PCIE_2_EXT_RESET 94 -#define PCIE_2_PHY_RESET 95 -#define PCIE_2_PCI_RESET 96 -#define PCIE_2_POR_RESET 97 -#define PCIE_2_HCLK_RESET 98 -#define PCIE_2_ACLK_RESET 99 -#define SFAB_USB30_S_RESET 100 -#define SFAB_USB30_M_RESET 101 -#define USB30_0_PORT2_HS_PHY_RESET 102 -#define USB30_0_MASTER_RESET 103 -#define USB30_0_SLEEP_RESET 104 -#define USB30_0_UTMI_PHY_RESET 105 -#define USB30_0_POWERON_RESET 106 -#define USB30_0_PHY_RESET 107 -#define USB30_1_MASTER_RESET 108 -#define USB30_1_SLEEP_RESET 109 -#define USB30_1_UTMI_PHY_RESET 110 -#define USB30_1_POWERON_RESET 111 -#define USB30_1_PHY_RESET 112 -#define NSSFB0_RESET 113 -#define NSSFB1_RESET 114 -#define UBI32_CORE1_CLKRST_CLAMP_RESET 115 -#define UBI32_CORE1_CLAMP_RESET 116 -#define UBI32_CORE1_AHB_RESET 117 -#define UBI32_CORE1_AXI_RESET 118 -#define UBI32_CORE2_CLKRST_CLAMP_RESET 119 -#define UBI32_CORE2_CLAMP_RESET 120 -#define UBI32_CORE2_AHB_RESET 121 -#define UBI32_CORE2_AXI_RESET 122 -#define GMAC_CORE1_RESET 123 -#define GMAC_CORE2_RESET 124 -#define GMAC_CORE3_RESET 125 -#define GMAC_CORE4_RESET 126 -#define GMAC_AHB_RESET 127 -#define NSS_CH0_RST_RX_CLK_N_RESET 128 -#define NSS_CH0_RST_TX_CLK_N_RESET 129 -#define NSS_CH0_RST_RX_125M_N_RESET 130 -#define NSS_CH0_HW_RST_RX_125M_N_RESET 131 -#define NSS_CH0_RST_TX_125M_N_RESET 132 -#define NSS_CH1_RST_RX_CLK_N_RESET 133 -#define NSS_CH1_RST_TX_CLK_N_RESET 134 -#define NSS_CH1_RST_RX_125M_N_RESET 135 -#define NSS_CH1_HW_RST_RX_125M_N_RESET 136 -#define NSS_CH1_RST_TX_125M_N_RESET 137 -#define NSS_CH2_RST_RX_CLK_N_RESET 138 -#define NSS_CH2_RST_TX_CLK_N_RESET 139 -#define NSS_CH2_RST_RX_125M_N_RESET 140 -#define NSS_CH2_HW_RST_RX_125M_N_RESET 141 -#define NSS_CH2_RST_TX_125M_N_RESET 142 -#define NSS_CH3_RST_RX_CLK_N_RESET 143 -#define NSS_CH3_RST_TX_CLK_N_RESET 144 -#define NSS_CH3_RST_RX_125M_N_RESET 145 -#define NSS_CH3_HW_RST_RX_125M_N_RESET 146 -#define NSS_CH3_RST_TX_125M_N_RESET 147 -#define NSS_RST_RX_250M_125M_N_RESET 148 -#define NSS_RST_TX_250M_125M_N_RESET 149 -#define NSS_QSGMII_TXPI_RST_N_RESET 150 -#define NSS_QSGMII_CDR_RST_N_RESET 151 -#define NSS_SGMII2_CDR_RST_N_RESET 152 -#define NSS_SGMII3_CDR_RST_N_RESET 153 -#define NSS_CAL_PRBS_RST_N_RESET 154 -#define NSS_LCKDT_RST_N_RESET 155 -#define NSS_SRDS_N_RESET 156 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/reset/qcom,gcc-mdm9615.h b/sys/gnu/dts/include/dt-bindings/reset/qcom,gcc-mdm9615.h deleted file mode 100644 index 5faf02d7e28..00000000000 --- a/sys/gnu/dts/include/dt-bindings/reset/qcom,gcc-mdm9615.h +++ /dev/null @@ -1,128 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2013, The Linux Foundation. All rights reserved. - * Copyright (c) BayLibre, SAS. - * Author : Neil Armstrong - */ - -#ifndef _DT_BINDINGS_RESET_GCC_MDM9615_H -#define _DT_BINDINGS_RESET_GCC_MDM9615_H - -#define SFAB_MSS_Q6_SW_RESET 0 -#define SFAB_MSS_Q6_FW_RESET 1 -#define QDSS_STM_RESET 2 -#define AFAB_SMPSS_S_RESET 3 -#define AFAB_SMPSS_M1_RESET 4 -#define AFAB_SMPSS_M0_RESET 5 -#define AFAB_EBI1_CH0_RESET 6 -#define AFAB_EBI1_CH1_RESET 7 -#define SFAB_ADM0_M0_RESET 8 -#define SFAB_ADM0_M1_RESET 9 -#define SFAB_ADM0_M2_RESET 10 -#define ADM0_C2_RESET 11 -#define ADM0_C1_RESET 12 -#define ADM0_C0_RESET 13 -#define ADM0_PBUS_RESET 14 -#define ADM0_RESET 15 -#define QDSS_CLKS_SW_RESET 16 -#define QDSS_POR_RESET 17 -#define QDSS_TSCTR_RESET 18 -#define QDSS_HRESET_RESET 19 -#define QDSS_AXI_RESET 20 -#define QDSS_DBG_RESET 21 -#define PCIE_A_RESET 22 -#define PCIE_AUX_RESET 23 -#define PCIE_H_RESET 24 -#define SFAB_PCIE_M_RESET 25 -#define SFAB_PCIE_S_RESET 26 -#define SFAB_MSS_M_RESET 27 -#define SFAB_USB3_M_RESET 28 -#define SFAB_RIVA_M_RESET 29 -#define SFAB_LPASS_RESET 30 -#define SFAB_AFAB_M_RESET 31 -#define AFAB_SFAB_M0_RESET 32 -#define AFAB_SFAB_M1_RESET 33 -#define SFAB_SATA_S_RESET 34 -#define SFAB_DFAB_M_RESET 35 -#define DFAB_SFAB_M_RESET 36 -#define DFAB_SWAY0_RESET 37 -#define DFAB_SWAY1_RESET 38 -#define DFAB_ARB0_RESET 39 -#define DFAB_ARB1_RESET 40 -#define PPSS_PROC_RESET 41 -#define PPSS_RESET 42 -#define DMA_BAM_RESET 43 -#define SPS_TIC_H_RESET 44 -#define SLIMBUS_H_RESET 45 -#define SFAB_CFPB_M_RESET 46 -#define SFAB_CFPB_S_RESET 47 -#define TSIF_H_RESET 48 -#define CE1_H_RESET 49 -#define CE1_CORE_RESET 50 -#define CE1_SLEEP_RESET 51 -#define CE2_H_RESET 52 -#define CE2_CORE_RESET 53 -#define SFAB_SFPB_M_RESET 54 -#define SFAB_SFPB_S_RESET 55 -#define RPM_PROC_RESET 56 -#define PMIC_SSBI2_RESET 57 -#define SDC1_RESET 58 -#define SDC2_RESET 59 -#define SDC3_RESET 60 -#define SDC4_RESET 61 -#define SDC5_RESET 62 -#define DFAB_A2_RESET 63 -#define USB_HS1_RESET 64 -#define USB_HSIC_RESET 65 -#define USB_FS1_XCVR_RESET 66 -#define USB_FS1_RESET 67 -#define USB_FS2_XCVR_RESET 68 -#define USB_FS2_RESET 69 -#define GSBI1_RESET 70 -#define GSBI2_RESET 71 -#define GSBI3_RESET 72 -#define GSBI4_RESET 73 -#define GSBI5_RESET 74 -#define GSBI6_RESET 75 -#define GSBI7_RESET 76 -#define GSBI8_RESET 77 -#define GSBI9_RESET 78 -#define GSBI10_RESET 79 -#define GSBI11_RESET 80 -#define GSBI12_RESET 81 -#define SPDM_RESET 82 -#define TLMM_H_RESET 83 -#define SFAB_MSS_S_RESET 84 -#define MSS_SLP_RESET 85 -#define MSS_Q6SW_JTAG_RESET 86 -#define MSS_Q6FW_JTAG_RESET 87 -#define MSS_RESET 88 -#define SATA_H_RESET 89 -#define SATA_RXOOB_RESE 90 -#define SATA_PMALIVE_RESET 91 -#define SATA_SFAB_M_RESET 92 -#define TSSC_RESET 93 -#define PDM_RESET 94 -#define MPM_H_RESET 95 -#define MPM_RESET 96 -#define SFAB_SMPSS_S_RESET 97 -#define PRNG_RESET 98 -#define RIVA_RESET 99 -#define USB_HS3_RESET 100 -#define USB_HS4_RESET 101 -#define CE3_RESET 102 -#define PCIE_EXT_PCI_RESET 103 -#define PCIE_PHY_RESET 104 -#define PCIE_PCI_RESET 105 -#define PCIE_POR_RESET 106 -#define PCIE_HCLK_RESET 107 -#define PCIE_ACLK_RESET 108 -#define CE3_H_RESET 109 -#define SFAB_CE3_M_RESET 110 -#define SFAB_CE3_S_RESET 111 -#define SATA_RESET 112 -#define CE3_SLEEP_RESET 113 -#define GSS_SLP_RESET 114 -#define GSS_RESET 115 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/reset/qcom,gcc-msm8660.h b/sys/gnu/dts/include/dt-bindings/reset/qcom,gcc-msm8660.h deleted file mode 100644 index f6d2b3cbe7b..00000000000 --- a/sys/gnu/dts/include/dt-bindings/reset/qcom,gcc-msm8660.h +++ /dev/null @@ -1,126 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2013, The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_RESET_MSM_GCC_8660_H -#define _DT_BINDINGS_RESET_MSM_GCC_8660_H - -#define AFAB_CORE_RESET 0 -#define SCSS_SYS_RESET 1 -#define SCSS_SYS_POR_RESET 2 -#define AFAB_SMPSS_S_RESET 3 -#define AFAB_SMPSS_M1_RESET 4 -#define AFAB_SMPSS_M0_RESET 5 -#define AFAB_EBI1_S_RESET 6 -#define SFAB_CORE_RESET 7 -#define SFAB_ADM0_M0_RESET 8 -#define SFAB_ADM0_M1_RESET 9 -#define SFAB_ADM0_M2_RESET 10 -#define ADM0_C2_RESET 11 -#define ADM0_C1_RESET 12 -#define ADM0_C0_RESET 13 -#define ADM0_PBUS_RESET 14 -#define ADM0_RESET 15 -#define SFAB_ADM1_M0_RESET 16 -#define SFAB_ADM1_M1_RESET 17 -#define SFAB_ADM1_M2_RESET 18 -#define MMFAB_ADM1_M3_RESET 19 -#define ADM1_C3_RESET 20 -#define ADM1_C2_RESET 21 -#define ADM1_C1_RESET 22 -#define ADM1_C0_RESET 23 -#define ADM1_PBUS_RESET 24 -#define ADM1_RESET 25 -#define IMEM0_RESET 26 -#define SFAB_LPASS_Q6_RESET 27 -#define SFAB_AFAB_M_RESET 28 -#define AFAB_SFAB_M0_RESET 29 -#define AFAB_SFAB_M1_RESET 30 -#define DFAB_CORE_RESET 31 -#define SFAB_DFAB_M_RESET 32 -#define DFAB_SFAB_M_RESET 33 -#define DFAB_SWAY0_RESET 34 -#define DFAB_SWAY1_RESET 35 -#define DFAB_ARB0_RESET 36 -#define DFAB_ARB1_RESET 37 -#define PPSS_PROC_RESET 38 -#define PPSS_RESET 39 -#define PMEM_RESET 40 -#define DMA_BAM_RESET 41 -#define SIC_RESET 42 -#define SPS_TIC_RESET 43 -#define CFBP0_RESET 44 -#define CFBP1_RESET 45 -#define CFBP2_RESET 46 -#define EBI2_RESET 47 -#define SFAB_CFPB_M_RESET 48 -#define CFPB_MASTER_RESET 49 -#define SFAB_CFPB_S_RESET 50 -#define CFPB_SPLITTER_RESET 51 -#define TSIF_RESET 52 -#define CE1_RESET 53 -#define CE2_RESET 54 -#define SFAB_SFPB_M_RESET 55 -#define SFAB_SFPB_S_RESET 56 -#define RPM_PROC_RESET 57 -#define RPM_BUS_RESET 58 -#define RPM_MSG_RAM_RESET 59 -#define PMIC_ARB0_RESET 60 -#define PMIC_ARB1_RESET 61 -#define PMIC_SSBI2_RESET 62 -#define SDC1_RESET 63 -#define SDC2_RESET 64 -#define SDC3_RESET 65 -#define SDC4_RESET 66 -#define SDC5_RESET 67 -#define USB_HS1_RESET 68 -#define USB_HS2_XCVR_RESET 69 -#define USB_HS2_RESET 70 -#define USB_FS1_XCVR_RESET 71 -#define USB_FS1_RESET 72 -#define USB_FS2_XCVR_RESET 73 -#define USB_FS2_RESET 74 -#define GSBI1_RESET 75 -#define GSBI2_RESET 76 -#define GSBI3_RESET 77 -#define GSBI4_RESET 78 -#define GSBI5_RESET 79 -#define GSBI6_RESET 80 -#define GSBI7_RESET 81 -#define GSBI8_RESET 82 -#define GSBI9_RESET 83 -#define GSBI10_RESET 84 -#define GSBI11_RESET 85 -#define GSBI12_RESET 86 -#define SPDM_RESET 87 -#define SEC_CTRL_RESET 88 -#define TLMM_H_RESET 89 -#define TLMM_RESET 90 -#define MARRM_PWRON_RESET 91 -#define MARM_RESET 92 -#define MAHB1_RESET 93 -#define SFAB_MSS_S_RESET 94 -#define MAHB2_RESET 95 -#define MODEM_SW_AHB_RESET 96 -#define MODEM_RESET 97 -#define SFAB_MSS_MDM1_RESET 98 -#define SFAB_MSS_MDM0_RESET 99 -#define MSS_SLP_RESET 100 -#define MSS_MARM_SAW_RESET 101 -#define MSS_WDOG_RESET 102 -#define TSSC_RESET 103 -#define PDM_RESET 104 -#define SCSS_CORE0_RESET 105 -#define SCSS_CORE0_POR_RESET 106 -#define SCSS_CORE1_RESET 107 -#define SCSS_CORE1_POR_RESET 108 -#define MPM_RESET 109 -#define EBI1_1X_DIV_RESET 110 -#define EBI1_RESET 111 -#define SFAB_SMPSS_S_RESET 112 -#define USB_PHY0_RESET 113 -#define USB_PHY1_RESET 114 -#define PRNG_RESET 115 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/reset/qcom,gcc-msm8916.h b/sys/gnu/dts/include/dt-bindings/reset/qcom,gcc-msm8916.h deleted file mode 100644 index 1f9be10872d..00000000000 --- a/sys/gnu/dts/include/dt-bindings/reset/qcom,gcc-msm8916.h +++ /dev/null @@ -1,100 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2015 Linaro Limited - */ - -#ifndef _DT_BINDINGS_RESET_MSM_GCC_8916_H -#define _DT_BINDINGS_RESET_MSM_GCC_8916_H - -#define GCC_BLSP1_BCR 0 -#define GCC_BLSP1_QUP1_BCR 1 -#define GCC_BLSP1_UART1_BCR 2 -#define GCC_BLSP1_QUP2_BCR 3 -#define GCC_BLSP1_UART2_BCR 4 -#define GCC_BLSP1_QUP3_BCR 5 -#define GCC_BLSP1_QUP4_BCR 6 -#define GCC_BLSP1_QUP5_BCR 7 -#define GCC_BLSP1_QUP6_BCR 8 -#define GCC_IMEM_BCR 9 -#define GCC_SMMU_BCR 10 -#define GCC_APSS_TCU_BCR 11 -#define GCC_SMMU_XPU_BCR 12 -#define GCC_PCNOC_TBU_BCR 13 -#define GCC_PRNG_BCR 14 -#define GCC_BOOT_ROM_BCR 15 -#define GCC_CRYPTO_BCR 16 -#define GCC_SEC_CTRL_BCR 17 -#define GCC_AUDIO_CORE_BCR 18 -#define GCC_ULT_AUDIO_BCR 19 -#define GCC_DEHR_BCR 20 -#define GCC_SYSTEM_NOC_BCR 21 -#define GCC_PCNOC_BCR 22 -#define GCC_TCSR_BCR 23 -#define GCC_QDSS_BCR 24 -#define GCC_DCD_BCR 25 -#define GCC_MSG_RAM_BCR 26 -#define GCC_MPM_BCR 27 -#define GCC_SPMI_BCR 28 -#define GCC_SPDM_BCR 29 -#define GCC_MM_SPDM_BCR 30 -#define GCC_BIMC_BCR 31 -#define GCC_RBCPR_BCR 32 -#define GCC_TLMM_BCR 33 -#define GCC_USB_HS_BCR 34 -#define GCC_USB2A_PHY_BCR 35 -#define GCC_SDCC1_BCR 36 -#define GCC_SDCC2_BCR 37 -#define GCC_PDM_BCR 38 -#define GCC_SNOC_BUS_TIMEOUT0_BCR 39 -#define GCC_PCNOC_BUS_TIMEOUT0_BCR 40 -#define GCC_PCNOC_BUS_TIMEOUT1_BCR 41 -#define GCC_PCNOC_BUS_TIMEOUT2_BCR 42 -#define GCC_PCNOC_BUS_TIMEOUT3_BCR 43 -#define GCC_PCNOC_BUS_TIMEOUT4_BCR 44 -#define GCC_PCNOC_BUS_TIMEOUT5_BCR 45 -#define GCC_PCNOC_BUS_TIMEOUT6_BCR 46 -#define GCC_PCNOC_BUS_TIMEOUT7_BCR 47 -#define GCC_PCNOC_BUS_TIMEOUT8_BCR 48 -#define GCC_PCNOC_BUS_TIMEOUT9_BCR 49 -#define GCC_MMSS_BCR 50 -#define GCC_VENUS0_BCR 51 -#define GCC_MDSS_BCR 52 -#define GCC_CAMSS_PHY0_BCR 53 -#define GCC_CAMSS_CSI0_BCR 54 -#define GCC_CAMSS_CSI0PHY_BCR 55 -#define GCC_CAMSS_CSI0RDI_BCR 56 -#define GCC_CAMSS_CSI0PIX_BCR 57 -#define GCC_CAMSS_PHY1_BCR 58 -#define GCC_CAMSS_CSI1_BCR 59 -#define GCC_CAMSS_CSI1PHY_BCR 60 -#define GCC_CAMSS_CSI1RDI_BCR 61 -#define GCC_CAMSS_CSI1PIX_BCR 62 -#define GCC_CAMSS_ISPIF_BCR 63 -#define GCC_CAMSS_CCI_BCR 64 -#define GCC_CAMSS_MCLK0_BCR 65 -#define GCC_CAMSS_MCLK1_BCR 66 -#define GCC_CAMSS_GP0_BCR 67 -#define GCC_CAMSS_GP1_BCR 68 -#define GCC_CAMSS_TOP_BCR 69 -#define GCC_CAMSS_MICRO_BCR 70 -#define GCC_CAMSS_JPEG_BCR 71 -#define GCC_CAMSS_VFE_BCR 72 -#define GCC_CAMSS_CSI_VFE0_BCR 73 -#define GCC_OXILI_BCR 74 -#define GCC_GMEM_BCR 75 -#define GCC_CAMSS_AHB_BCR 76 -#define GCC_MDP_TBU_BCR 77 -#define GCC_GFX_TBU_BCR 78 -#define GCC_GFX_TCU_BCR 79 -#define GCC_MSS_TBU_AXI_BCR 80 -#define GCC_MSS_TBU_GSS_AXI_BCR 81 -#define GCC_MSS_TBU_Q6_AXI_BCR 82 -#define GCC_GTCU_AHB_BCR 83 -#define GCC_SMMU_CFG_BCR 84 -#define GCC_VFE_TBU_BCR 85 -#define GCC_VENUS_TBU_BCR 86 -#define GCC_JPEG_TBU_BCR 87 -#define GCC_PRONTO_TBU_BCR 88 -#define GCC_SMMU_CATS_BCR 89 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/reset/qcom,gcc-msm8960.h b/sys/gnu/dts/include/dt-bindings/reset/qcom,gcc-msm8960.h deleted file mode 100644 index c7ebae7bb25..00000000000 --- a/sys/gnu/dts/include/dt-bindings/reset/qcom,gcc-msm8960.h +++ /dev/null @@ -1,126 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2013, The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_RESET_MSM_GCC_8960_H -#define _DT_BINDINGS_RESET_MSM_GCC_8960_H - -#define SFAB_MSS_Q6_SW_RESET 0 -#define SFAB_MSS_Q6_FW_RESET 1 -#define QDSS_STM_RESET 2 -#define AFAB_SMPSS_S_RESET 3 -#define AFAB_SMPSS_M1_RESET 4 -#define AFAB_SMPSS_M0_RESET 5 -#define AFAB_EBI1_CH0_RESET 6 -#define AFAB_EBI1_CH1_RESET 7 -#define SFAB_ADM0_M0_RESET 8 -#define SFAB_ADM0_M1_RESET 9 -#define SFAB_ADM0_M2_RESET 10 -#define ADM0_C2_RESET 11 -#define ADM0_C1_RESET 12 -#define ADM0_C0_RESET 13 -#define ADM0_PBUS_RESET 14 -#define ADM0_RESET 15 -#define QDSS_CLKS_SW_RESET 16 -#define QDSS_POR_RESET 17 -#define QDSS_TSCTR_RESET 18 -#define QDSS_HRESET_RESET 19 -#define QDSS_AXI_RESET 20 -#define QDSS_DBG_RESET 21 -#define PCIE_A_RESET 22 -#define PCIE_AUX_RESET 23 -#define PCIE_H_RESET 24 -#define SFAB_PCIE_M_RESET 25 -#define SFAB_PCIE_S_RESET 26 -#define SFAB_MSS_M_RESET 27 -#define SFAB_USB3_M_RESET 28 -#define SFAB_RIVA_M_RESET 29 -#define SFAB_LPASS_RESET 30 -#define SFAB_AFAB_M_RESET 31 -#define AFAB_SFAB_M0_RESET 32 -#define AFAB_SFAB_M1_RESET 33 -#define SFAB_SATA_S_RESET 34 -#define SFAB_DFAB_M_RESET 35 -#define DFAB_SFAB_M_RESET 36 -#define DFAB_SWAY0_RESET 37 -#define DFAB_SWAY1_RESET 38 -#define DFAB_ARB0_RESET 39 -#define DFAB_ARB1_RESET 40 -#define PPSS_PROC_RESET 41 -#define PPSS_RESET 42 -#define DMA_BAM_RESET 43 -#define SPS_TIC_H_RESET 44 -#define SLIMBUS_H_RESET 45 -#define SFAB_CFPB_M_RESET 46 -#define SFAB_CFPB_S_RESET 47 -#define TSIF_H_RESET 48 -#define CE1_H_RESET 49 -#define CE1_CORE_RESET 50 -#define CE1_SLEEP_RESET 51 -#define CE2_H_RESET 52 -#define CE2_CORE_RESET 53 -#define SFAB_SFPB_M_RESET 54 -#define SFAB_SFPB_S_RESET 55 -#define RPM_PROC_RESET 56 -#define PMIC_SSBI2_RESET 57 -#define SDC1_RESET 58 -#define SDC2_RESET 59 -#define SDC3_RESET 60 -#define SDC4_RESET 61 -#define SDC5_RESET 62 -#define DFAB_A2_RESET 63 -#define USB_HS1_RESET 64 -#define USB_HSIC_RESET 65 -#define USB_FS1_XCVR_RESET 66 -#define USB_FS1_RESET 67 -#define USB_FS2_XCVR_RESET 68 -#define USB_FS2_RESET 69 -#define GSBI1_RESET 70 -#define GSBI2_RESET 71 -#define GSBI3_RESET 72 -#define GSBI4_RESET 73 -#define GSBI5_RESET 74 -#define GSBI6_RESET 75 -#define GSBI7_RESET 76 -#define GSBI8_RESET 77 -#define GSBI9_RESET 78 -#define GSBI10_RESET 79 -#define GSBI11_RESET 80 -#define GSBI12_RESET 81 -#define SPDM_RESET 82 -#define TLMM_H_RESET 83 -#define SFAB_MSS_S_RESET 84 -#define MSS_SLP_RESET 85 -#define MSS_Q6SW_JTAG_RESET 86 -#define MSS_Q6FW_JTAG_RESET 87 -#define MSS_RESET 88 -#define SATA_H_RESET 89 -#define SATA_RXOOB_RESE 90 -#define SATA_PMALIVE_RESET 91 -#define SATA_SFAB_M_RESET 92 -#define TSSC_RESET 93 -#define PDM_RESET 94 -#define MPM_H_RESET 95 -#define MPM_RESET 96 -#define SFAB_SMPSS_S_RESET 97 -#define PRNG_RESET 98 -#define RIVA_RESET 99 -#define USB_HS3_RESET 100 -#define USB_HS4_RESET 101 -#define CE3_RESET 102 -#define PCIE_EXT_PCI_RESET 103 -#define PCIE_PHY_RESET 104 -#define PCIE_PCI_RESET 105 -#define PCIE_POR_RESET 106 -#define PCIE_HCLK_RESET 107 -#define PCIE_ACLK_RESET 108 -#define CE3_H_RESET 109 -#define SFAB_CE3_M_RESET 110 -#define SFAB_CE3_S_RESET 111 -#define SATA_RESET 112 -#define CE3_SLEEP_RESET 113 -#define GSS_SLP_RESET 114 -#define GSS_RESET 115 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/reset/qcom,gcc-msm8974.h b/sys/gnu/dts/include/dt-bindings/reset/qcom,gcc-msm8974.h deleted file mode 100644 index 23777e5ca4e..00000000000 --- a/sys/gnu/dts/include/dt-bindings/reset/qcom,gcc-msm8974.h +++ /dev/null @@ -1,88 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2013, The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_RESET_MSM_GCC_8974_H -#define _DT_BINDINGS_RESET_MSM_GCC_8974_H - -#define GCC_SYSTEM_NOC_BCR 0 -#define GCC_CONFIG_NOC_BCR 1 -#define GCC_PERIPH_NOC_BCR 2 -#define GCC_IMEM_BCR 3 -#define GCC_MMSS_BCR 4 -#define GCC_QDSS_BCR 5 -#define GCC_USB_30_BCR 6 -#define GCC_USB3_PHY_BCR 7 -#define GCC_USB_HS_HSIC_BCR 8 -#define GCC_USB_HS_BCR 9 -#define GCC_USB2A_PHY_BCR 10 -#define GCC_USB2B_PHY_BCR 11 -#define GCC_SDCC1_BCR 12 -#define GCC_SDCC2_BCR 13 -#define GCC_SDCC3_BCR 14 -#define GCC_SDCC4_BCR 15 -#define GCC_BLSP1_BCR 16 -#define GCC_BLSP1_QUP1_BCR 17 -#define GCC_BLSP1_UART1_BCR 18 -#define GCC_BLSP1_QUP2_BCR 19 -#define GCC_BLSP1_UART2_BCR 20 -#define GCC_BLSP1_QUP3_BCR 21 -#define GCC_BLSP1_UART3_BCR 22 -#define GCC_BLSP1_QUP4_BCR 23 -#define GCC_BLSP1_UART4_BCR 24 -#define GCC_BLSP1_QUP5_BCR 25 -#define GCC_BLSP1_UART5_BCR 26 -#define GCC_BLSP1_QUP6_BCR 27 -#define GCC_BLSP1_UART6_BCR 28 -#define GCC_BLSP2_BCR 29 -#define GCC_BLSP2_QUP1_BCR 30 -#define GCC_BLSP2_UART1_BCR 31 -#define GCC_BLSP2_QUP2_BCR 32 -#define GCC_BLSP2_UART2_BCR 33 -#define GCC_BLSP2_QUP3_BCR 34 -#define GCC_BLSP2_UART3_BCR 35 -#define GCC_BLSP2_QUP4_BCR 36 -#define GCC_BLSP2_UART4_BCR 37 -#define GCC_BLSP2_QUP5_BCR 38 -#define GCC_BLSP2_UART5_BCR 39 -#define GCC_BLSP2_QUP6_BCR 40 -#define GCC_BLSP2_UART6_BCR 41 -#define GCC_PDM_BCR 42 -#define GCC_BAM_DMA_BCR 43 -#define GCC_TSIF_BCR 44 -#define GCC_TCSR_BCR 45 -#define GCC_BOOT_ROM_BCR 46 -#define GCC_MSG_RAM_BCR 47 -#define GCC_TLMM_BCR 48 -#define GCC_MPM_BCR 49 -#define GCC_SEC_CTRL_BCR 50 -#define GCC_SPMI_BCR 51 -#define GCC_SPDM_BCR 52 -#define GCC_CE1_BCR 53 -#define GCC_CE2_BCR 54 -#define GCC_BIMC_BCR 55 -#define GCC_MPM_NON_AHB_RESET 56 -#define GCC_MPM_AHB_RESET 57 -#define GCC_SNOC_BUS_TIMEOUT0_BCR 58 -#define GCC_SNOC_BUS_TIMEOUT2_BCR 59 -#define GCC_PNOC_BUS_TIMEOUT0_BCR 60 -#define GCC_PNOC_BUS_TIMEOUT1_BCR 61 -#define GCC_PNOC_BUS_TIMEOUT2_BCR 62 -#define GCC_PNOC_BUS_TIMEOUT3_BCR 63 -#define GCC_PNOC_BUS_TIMEOUT4_BCR 64 -#define GCC_CNOC_BUS_TIMEOUT0_BCR 65 -#define GCC_CNOC_BUS_TIMEOUT1_BCR 66 -#define GCC_CNOC_BUS_TIMEOUT2_BCR 67 -#define GCC_CNOC_BUS_TIMEOUT3_BCR 68 -#define GCC_CNOC_BUS_TIMEOUT4_BCR 69 -#define GCC_CNOC_BUS_TIMEOUT5_BCR 70 -#define GCC_CNOC_BUS_TIMEOUT6_BCR 71 -#define GCC_DEHR_BCR 72 -#define GCC_RBCPR_BCR 73 -#define GCC_MSS_RESTART 74 -#define GCC_LPASS_RESTART 75 -#define GCC_WCSS_RESTART 76 -#define GCC_VENUS_RESTART 77 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/reset/qcom,mmcc-apq8084.h b/sys/gnu/dts/include/dt-bindings/reset/qcom,mmcc-apq8084.h deleted file mode 100644 index faaeb40959f..00000000000 --- a/sys/gnu/dts/include/dt-bindings/reset/qcom,mmcc-apq8084.h +++ /dev/null @@ -1,56 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2014, The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_RESET_APQ_MMCC_8084_H -#define _DT_BINDINGS_RESET_APQ_MMCC_8084_H - -#define MMSS_SPDM_RESET 0 -#define MMSS_SPDM_RM_RESET 1 -#define VENUS0_RESET 2 -#define VPU_RESET 3 -#define MDSS_RESET 4 -#define AVSYNC_RESET 5 -#define CAMSS_PHY0_RESET 6 -#define CAMSS_PHY1_RESET 7 -#define CAMSS_PHY2_RESET 8 -#define CAMSS_CSI0_RESET 9 -#define CAMSS_CSI0PHY_RESET 10 -#define CAMSS_CSI0RDI_RESET 11 -#define CAMSS_CSI0PIX_RESET 12 -#define CAMSS_CSI1_RESET 13 -#define CAMSS_CSI1PHY_RESET 14 -#define CAMSS_CSI1RDI_RESET 15 -#define CAMSS_CSI1PIX_RESET 16 -#define CAMSS_CSI2_RESET 17 -#define CAMSS_CSI2PHY_RESET 18 -#define CAMSS_CSI2RDI_RESET 19 -#define CAMSS_CSI2PIX_RESET 20 -#define CAMSS_CSI3_RESET 21 -#define CAMSS_CSI3PHY_RESET 22 -#define CAMSS_CSI3RDI_RESET 23 -#define CAMSS_CSI3PIX_RESET 24 -#define CAMSS_ISPIF_RESET 25 -#define CAMSS_CCI_RESET 26 -#define CAMSS_MCLK0_RESET 27 -#define CAMSS_MCLK1_RESET 28 -#define CAMSS_MCLK2_RESET 29 -#define CAMSS_MCLK3_RESET 30 -#define CAMSS_GP0_RESET 31 -#define CAMSS_GP1_RESET 32 -#define CAMSS_TOP_RESET 33 -#define CAMSS_AHB_RESET 34 -#define CAMSS_MICRO_RESET 35 -#define CAMSS_JPEG_RESET 36 -#define CAMSS_VFE_RESET 37 -#define CAMSS_CSI_VFE0_RESET 38 -#define CAMSS_CSI_VFE1_RESET 39 -#define OXILI_RESET 40 -#define OXILICX_RESET 41 -#define OCMEMCX_RESET 42 -#define MMSS_RBCRP_RESET 43 -#define MMSSNOCAHB_RESET 44 -#define MMSSNOCAXI_RESET 45 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/reset/qcom,mmcc-msm8960.h b/sys/gnu/dts/include/dt-bindings/reset/qcom,mmcc-msm8960.h deleted file mode 100644 index eb4186aa2c0..00000000000 --- a/sys/gnu/dts/include/dt-bindings/reset/qcom,mmcc-msm8960.h +++ /dev/null @@ -1,93 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2013, The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_RESET_MSM_MMCC_8960_H -#define _DT_BINDINGS_RESET_MSM_MMCC_8960_H - -#define VPE_AXI_RESET 0 -#define IJPEG_AXI_RESET 1 -#define MPD_AXI_RESET 2 -#define VFE_AXI_RESET 3 -#define SP_AXI_RESET 4 -#define VCODEC_AXI_RESET 5 -#define ROT_AXI_RESET 6 -#define VCODEC_AXI_A_RESET 7 -#define VCODEC_AXI_B_RESET 8 -#define FAB_S3_AXI_RESET 9 -#define FAB_S2_AXI_RESET 10 -#define FAB_S1_AXI_RESET 11 -#define FAB_S0_AXI_RESET 12 -#define SMMU_GFX3D_ABH_RESET 13 -#define SMMU_VPE_AHB_RESET 14 -#define SMMU_VFE_AHB_RESET 15 -#define SMMU_ROT_AHB_RESET 16 -#define SMMU_VCODEC_B_AHB_RESET 17 -#define SMMU_VCODEC_A_AHB_RESET 18 -#define SMMU_MDP1_AHB_RESET 19 -#define SMMU_MDP0_AHB_RESET 20 -#define SMMU_JPEGD_AHB_RESET 21 -#define SMMU_IJPEG_AHB_RESET 22 -#define SMMU_GFX2D0_AHB_RESET 23 -#define SMMU_GFX2D1_AHB_RESET 24 -#define APU_AHB_RESET 25 -#define CSI_AHB_RESET 26 -#define TV_ENC_AHB_RESET 27 -#define VPE_AHB_RESET 28 -#define FABRIC_AHB_RESET 29 -#define GFX2D0_AHB_RESET 30 -#define GFX2D1_AHB_RESET 31 -#define GFX3D_AHB_RESET 32 -#define HDMI_AHB_RESET 33 -#define MSSS_IMEM_AHB_RESET 34 -#define IJPEG_AHB_RESET 35 -#define DSI_M_AHB_RESET 36 -#define DSI_S_AHB_RESET 37 -#define JPEGD_AHB_RESET 38 -#define MDP_AHB_RESET 39 -#define ROT_AHB_RESET 40 -#define VCODEC_AHB_RESET 41 -#define VFE_AHB_RESET 42 -#define DSI2_M_AHB_RESET 43 -#define DSI2_S_AHB_RESET 44 -#define CSIPHY2_RESET 45 -#define CSI_PIX1_RESET 46 -#define CSIPHY0_RESET 47 -#define CSIPHY1_RESET 48 -#define DSI2_RESET 49 -#define VFE_CSI_RESET 50 -#define MDP_RESET 51 -#define AMP_RESET 52 -#define JPEGD_RESET 53 -#define CSI1_RESET 54 -#define VPE_RESET 55 -#define MMSS_FABRIC_RESET 56 -#define VFE_RESET 57 -#define GFX2D0_RESET 58 -#define GFX2D1_RESET 59 -#define GFX3D_RESET 60 -#define HDMI_RESET 61 -#define MMSS_IMEM_RESET 62 -#define IJPEG_RESET 63 -#define CSI0_RESET 64 -#define DSI_RESET 65 -#define VCODEC_RESET 66 -#define MDP_TV_RESET 67 -#define MDP_VSYNC_RESET 68 -#define ROT_RESET 69 -#define TV_HDMI_RESET 70 -#define TV_ENC_RESET 71 -#define CSI2_RESET 72 -#define CSI_RDI1_RESET 73 -#define CSI_RDI2_RESET 74 -#define GFX3D_AXI_RESET 75 -#define VCAP_AXI_RESET 76 -#define SMMU_VCAP_AHB_RESET 77 -#define VCAP_AHB_RESET 78 -#define CSI_RDI_RESET 79 -#define CSI_PIX_RESET 80 -#define VCAP_NPL_RESET 81 -#define VCAP_RESET 82 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/reset/qcom,mmcc-msm8974.h b/sys/gnu/dts/include/dt-bindings/reset/qcom,mmcc-msm8974.h deleted file mode 100644 index d61b077e911..00000000000 --- a/sys/gnu/dts/include/dt-bindings/reset/qcom,mmcc-msm8974.h +++ /dev/null @@ -1,54 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2013, The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_RESET_MSM_MMCC_8974_H -#define _DT_BINDINGS_RESET_MSM_MMCC_8974_H - -#define SPDM_RESET 0 -#define SPDM_RM_RESET 1 -#define VENUS0_RESET 2 -#define MDSS_RESET 3 -#define CAMSS_PHY0_RESET 4 -#define CAMSS_PHY1_RESET 5 -#define CAMSS_PHY2_RESET 6 -#define CAMSS_CSI0_RESET 7 -#define CAMSS_CSI0PHY_RESET 8 -#define CAMSS_CSI0RDI_RESET 9 -#define CAMSS_CSI0PIX_RESET 10 -#define CAMSS_CSI1_RESET 11 -#define CAMSS_CSI1PHY_RESET 12 -#define CAMSS_CSI1RDI_RESET 13 -#define CAMSS_CSI1PIX_RESET 14 -#define CAMSS_CSI2_RESET 15 -#define CAMSS_CSI2PHY_RESET 16 -#define CAMSS_CSI2RDI_RESET 17 -#define CAMSS_CSI2PIX_RESET 18 -#define CAMSS_CSI3_RESET 19 -#define CAMSS_CSI3PHY_RESET 20 -#define CAMSS_CSI3RDI_RESET 21 -#define CAMSS_CSI3PIX_RESET 22 -#define CAMSS_ISPIF_RESET 23 -#define CAMSS_CCI_RESET 24 -#define CAMSS_MCLK0_RESET 25 -#define CAMSS_MCLK1_RESET 26 -#define CAMSS_MCLK2_RESET 27 -#define CAMSS_MCLK3_RESET 28 -#define CAMSS_GP0_RESET 29 -#define CAMSS_GP1_RESET 30 -#define CAMSS_TOP_RESET 31 -#define CAMSS_MICRO_RESET 32 -#define CAMSS_JPEG_RESET 33 -#define CAMSS_VFE_RESET 34 -#define CAMSS_CSI_VFE0_RESET 35 -#define CAMSS_CSI_VFE1_RESET 36 -#define OXILI_RESET 37 -#define OXILICX_RESET 38 -#define OCMEMCX_RESET 39 -#define MMSS_RBCRP_RESET 40 -#define MMSSNOCAHB_RESET 41 -#define MMSSNOCAXI_RESET 42 -#define OCMEMNOC_RESET 43 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/reset/qcom,sdm845-aoss.h b/sys/gnu/dts/include/dt-bindings/reset/qcom,sdm845-aoss.h deleted file mode 100644 index 476c5fc873b..00000000000 --- a/sys/gnu/dts/include/dt-bindings/reset/qcom,sdm845-aoss.h +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2018 The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_RESET_AOSS_SDM_845_H -#define _DT_BINDINGS_RESET_AOSS_SDM_845_H - -#define AOSS_CC_MSS_RESTART 0 -#define AOSS_CC_CAMSS_RESTART 1 -#define AOSS_CC_VENUS_RESTART 2 -#define AOSS_CC_GPU_RESTART 3 -#define AOSS_CC_DISPSS_RESTART 4 -#define AOSS_CC_WCSS_RESTART 5 -#define AOSS_CC_LPASS_RESTART 6 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/reset/qcom,sdm845-pdc.h b/sys/gnu/dts/include/dt-bindings/reset/qcom,sdm845-pdc.h deleted file mode 100644 index 53c37f9c319..00000000000 --- a/sys/gnu/dts/include/dt-bindings/reset/qcom,sdm845-pdc.h +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2018 The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_RESET_PDC_SDM_845_H -#define _DT_BINDINGS_RESET_PDC_SDM_845_H - -#define PDC_APPS_SYNC_RESET 0 -#define PDC_SP_SYNC_RESET 1 -#define PDC_AUDIO_SYNC_RESET 2 -#define PDC_SENSORS_SYNC_RESET 3 -#define PDC_AOP_SYNC_RESET 4 -#define PDC_DEBUG_SYNC_RESET 5 -#define PDC_GPU_SYNC_RESET 6 -#define PDC_DISPLAY_SYNC_RESET 7 -#define PDC_COMPUTE_SYNC_RESET 8 -#define PDC_MODEM_SYNC_RESET 9 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/reset/realtek,rtd1295.h b/sys/gnu/dts/include/dt-bindings/reset/realtek,rtd1295.h deleted file mode 100644 index 2c0cb6afe81..00000000000 --- a/sys/gnu/dts/include/dt-bindings/reset/realtek,rtd1295.h +++ /dev/null @@ -1,111 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) */ -/* - * Realtek RTD1295 reset controllers - * - * Copyright (c) 2017 Andreas Färber - */ -#ifndef DT_BINDINGS_RESET_RTD1295_H -#define DT_BINDINGS_RESET_RTD1295_H - -/* soft reset 1 */ -#define RTD1295_RSTN_MISC 0 -#define RTD1295_RSTN_NAT 1 -#define RTD1295_RSTN_USB3_PHY0_POW 2 -#define RTD1295_RSTN_GSPI 3 -#define RTD1295_RSTN_USB3_P0_MDIO 4 -#define RTD1295_RSTN_SATA_0 5 -#define RTD1295_RSTN_USB 6 -#define RTD1295_RSTN_SATA_PHY_0 7 -#define RTD1295_RSTN_USB_PHY0 8 -#define RTD1295_RSTN_USB_PHY1 9 -#define RTD1295_RSTN_SATA_PHY_POW_0 10 -#define RTD1295_RSTN_SATA_FUNC_EXIST_0 11 -#define RTD1295_RSTN_HDMI 12 -#define RTD1295_RSTN_VE1 13 -#define RTD1295_RSTN_VE2 14 -#define RTD1295_RSTN_VE3 15 -#define RTD1295_RSTN_ETN 16 -#define RTD1295_RSTN_AIO 17 -#define RTD1295_RSTN_GPU 18 -#define RTD1295_RSTN_TVE 19 -#define RTD1295_RSTN_VO 20 -#define RTD1295_RSTN_LVDS 21 -#define RTD1295_RSTN_SE 22 -#define RTD1295_RSTN_DCU 23 -#define RTD1295_RSTN_DC_PHY 24 -#define RTD1295_RSTN_CP 25 -#define RTD1295_RSTN_MD 26 -#define RTD1295_RSTN_TP 27 -#define RTD1295_RSTN_AE 28 -#define RTD1295_RSTN_NF 29 -#define RTD1295_RSTN_MIPI 30 -#define RTD1295_RSTN_RSA 31 - -/* soft reset 2 */ -#define RTD1295_RSTN_ACPU 0 -#define RTD1295_RSTN_JPEG 1 -#define RTD1295_RSTN_USB_PHY3 2 -#define RTD1295_RSTN_USB_PHY2 3 -#define RTD1295_RSTN_USB3_PHY1_POW 4 -#define RTD1295_RSTN_USB3_P1_MDIO 5 -#define RTD1295_RSTN_PCIE0_STITCH 6 -#define RTD1295_RSTN_PCIE0_PHY 7 -#define RTD1295_RSTN_PCIE0 8 -#define RTD1295_RSTN_PCR_CNT 9 -#define RTD1295_RSTN_CR 10 -#define RTD1295_RSTN_EMMC 11 -#define RTD1295_RSTN_SDIO 12 -#define RTD1295_RSTN_PCIE0_CORE 13 -#define RTD1295_RSTN_PCIE0_POWER 14 -#define RTD1295_RSTN_PCIE0_NONSTICH 15 -#define RTD1295_RSTN_PCIE1_PHY 16 -#define RTD1295_RSTN_PCIE1 17 -#define RTD1295_RSTN_I2C_5 18 -#define RTD1295_RSTN_PCIE1_STITCH 19 -#define RTD1295_RSTN_PCIE1_CORE 20 -#define RTD1295_RSTN_PCIE1_POWER 21 -#define RTD1295_RSTN_PCIE1_NONSTICH 22 -#define RTD1295_RSTN_I2C_4 23 -#define RTD1295_RSTN_I2C_3 24 -#define RTD1295_RSTN_I2C_2 25 -#define RTD1295_RSTN_I2C_1 26 -#define RTD1295_RSTN_UR2 27 -#define RTD1295_RSTN_UR1 28 -#define RTD1295_RSTN_MISC_SC 29 -#define RTD1295_RSTN_CBUS_TX 30 -#define RTD1295_RSTN_SDS_PHY 31 - -/* soft reset 4 */ -#define RTD1295_RSTN_DCPHY_CRT 0 -#define RTD1295_RSTN_DCPHY_ALERT_RX 1 -#define RTD1295_RSTN_DCPHY_PTR 2 -#define RTD1295_RSTN_DCPHY_LDO 3 -#define RTD1295_RSTN_DCPHY_SSC_DIG 4 -#define RTD1295_RSTN_HDMIRX 5 -#define RTD1295_RSTN_CBUSRX 6 -#define RTD1295_RSTN_SATA_PHY_POW_1 7 -#define RTD1295_RSTN_SATA_FUNC_EXIST_1 8 -#define RTD1295_RSTN_SATA_PHY_1 9 -#define RTD1295_RSTN_SATA_1 10 -#define RTD1295_RSTN_FAN 11 -#define RTD1295_RSTN_HDMIRX_WRAP 12 -#define RTD1295_RSTN_PCIE0_PHY_MDIO 13 -#define RTD1295_RSTN_PCIE1_PHY_MDIO 14 -#define RTD1295_RSTN_DISP 15 - -/* iso reset */ -#define RTD1295_ISO_RSTN_IR 1 -#define RTD1295_ISO_RSTN_CEC0 2 -#define RTD1295_ISO_RSTN_CEC1 3 -#define RTD1295_ISO_RSTN_DP 4 -#define RTD1295_ISO_RSTN_CBUSTX 5 -#define RTD1295_ISO_RSTN_CBUSRX 6 -#define RTD1295_ISO_RSTN_EFUSE 7 -#define RTD1295_ISO_RSTN_UR0 8 -#define RTD1295_ISO_RSTN_GMAC 9 -#define RTD1295_ISO_RSTN_GPHY 10 -#define RTD1295_ISO_RSTN_I2C_0 11 -#define RTD1295_ISO_RSTN_I2C_1 12 -#define RTD1295_ISO_RSTN_CBUS 13 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/reset/snps,hsdk-reset.h b/sys/gnu/dts/include/dt-bindings/reset/snps,hsdk-reset.h deleted file mode 100644 index e1a643e4bc9..00000000000 --- a/sys/gnu/dts/include/dt-bindings/reset/snps,hsdk-reset.h +++ /dev/null @@ -1,17 +0,0 @@ -/** - * This header provides index for the HSDK reset controller. - */ -#ifndef _DT_BINDINGS_RESET_CONTROLLER_SNPS_HSDK -#define _DT_BINDINGS_RESET_CONTROLLER_SNPS_HSDK - -#define HSDK_APB_RESET 0 -#define HSDK_AXI_RESET 1 -#define HSDK_ETH_RESET 2 -#define HSDK_USB_RESET 3 -#define HSDK_SDIO_RESET 4 -#define HSDK_HDMI_RESET 5 -#define HSDK_GFX_RESET 6 -#define HSDK_DMAC_RESET 7 -#define HSDK_EBI_RESET 8 - -#endif /*_DT_BINDINGS_RESET_CONTROLLER_SNPS_HSDK*/ diff --git a/sys/gnu/dts/include/dt-bindings/reset/stih407-resets.h b/sys/gnu/dts/include/dt-bindings/reset/stih407-resets.h deleted file mode 100644 index f2a2c4f7f06..00000000000 --- a/sys/gnu/dts/include/dt-bindings/reset/stih407-resets.h +++ /dev/null @@ -1,66 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides constants for the reset controller - * based peripheral powerdown requests on the STMicroelectronics - * STiH407 SoC. - */ -#ifndef _DT_BINDINGS_RESET_CONTROLLER_STIH407 -#define _DT_BINDINGS_RESET_CONTROLLER_STIH407 - -/* Powerdown requests control 0 */ -#define STIH407_EMISS_POWERDOWN 0 -#define STIH407_NAND_POWERDOWN 1 - -/* Synp GMAC PowerDown */ -#define STIH407_ETH1_POWERDOWN 2 - -/* Powerdown requests control 1 */ -#define STIH407_USB3_POWERDOWN 3 -#define STIH407_USB2_PORT1_POWERDOWN 4 -#define STIH407_USB2_PORT0_POWERDOWN 5 -#define STIH407_PCIE1_POWERDOWN 6 -#define STIH407_PCIE0_POWERDOWN 7 -#define STIH407_SATA1_POWERDOWN 8 -#define STIH407_SATA0_POWERDOWN 9 - -/* Reset defines */ -#define STIH407_ETH1_SOFTRESET 0 -#define STIH407_MMC1_SOFTRESET 1 -#define STIH407_PICOPHY_SOFTRESET 2 -#define STIH407_IRB_SOFTRESET 3 -#define STIH407_PCIE0_SOFTRESET 4 -#define STIH407_PCIE1_SOFTRESET 5 -#define STIH407_SATA0_SOFTRESET 6 -#define STIH407_SATA1_SOFTRESET 7 -#define STIH407_MIPHY0_SOFTRESET 8 -#define STIH407_MIPHY1_SOFTRESET 9 -#define STIH407_MIPHY2_SOFTRESET 10 -#define STIH407_SATA0_PWR_SOFTRESET 11 -#define STIH407_SATA1_PWR_SOFTRESET 12 -#define STIH407_DELTA_SOFTRESET 13 -#define STIH407_BLITTER_SOFTRESET 14 -#define STIH407_HDTVOUT_SOFTRESET 15 -#define STIH407_HDQVDP_SOFTRESET 16 -#define STIH407_VDP_AUX_SOFTRESET 17 -#define STIH407_COMPO_SOFTRESET 18 -#define STIH407_HDMI_TX_PHY_SOFTRESET 19 -#define STIH407_JPEG_DEC_SOFTRESET 20 -#define STIH407_VP8_DEC_SOFTRESET 21 -#define STIH407_GPU_SOFTRESET 22 -#define STIH407_HVA_SOFTRESET 23 -#define STIH407_ERAM_HVA_SOFTRESET 24 -#define STIH407_LPM_SOFTRESET 25 -#define STIH407_KEYSCAN_SOFTRESET 26 -#define STIH407_USB2_PORT0_SOFTRESET 27 -#define STIH407_USB2_PORT1_SOFTRESET 28 -#define STIH407_ST231_AUD_SOFTRESET 29 -#define STIH407_ST231_DMU_SOFTRESET 30 -#define STIH407_ST231_GP0_SOFTRESET 31 -#define STIH407_ST231_GP1_SOFTRESET 32 - -/* Picophy reset defines */ -#define STIH407_PICOPHY0_RESET 0 -#define STIH407_PICOPHY1_RESET 1 -#define STIH407_PICOPHY2_RESET 2 - -#endif /* _DT_BINDINGS_RESET_CONTROLLER_STIH407 */ diff --git a/sys/gnu/dts/include/dt-bindings/reset/stih415-resets.h b/sys/gnu/dts/include/dt-bindings/reset/stih415-resets.h deleted file mode 100644 index 96f7831a1db..00000000000 --- a/sys/gnu/dts/include/dt-bindings/reset/stih415-resets.h +++ /dev/null @@ -1,28 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides constants for the reset controller - * based peripheral powerdown requests on the STMicroelectronics - * STiH415 SoC. - */ -#ifndef _DT_BINDINGS_RESET_CONTROLLER_STIH415 -#define _DT_BINDINGS_RESET_CONTROLLER_STIH415 - -#define STIH415_EMISS_POWERDOWN 0 -#define STIH415_NAND_POWERDOWN 1 -#define STIH415_KEYSCAN_POWERDOWN 2 -#define STIH415_USB0_POWERDOWN 3 -#define STIH415_USB1_POWERDOWN 4 -#define STIH415_USB2_POWERDOWN 5 -#define STIH415_SATA0_POWERDOWN 6 -#define STIH415_SATA1_POWERDOWN 7 -#define STIH415_PCIE_POWERDOWN 8 - -#define STIH415_ETH0_SOFTRESET 0 -#define STIH415_ETH1_SOFTRESET 1 -#define STIH415_IRB_SOFTRESET 2 -#define STIH415_USB0_SOFTRESET 3 -#define STIH415_USB1_SOFTRESET 4 -#define STIH415_USB2_SOFTRESET 5 -#define STIH415_KEYSCAN_SOFTRESET 6 - -#endif /* _DT_BINDINGS_RESET_CONTROLLER_STIH415 */ diff --git a/sys/gnu/dts/include/dt-bindings/reset/stih416-resets.h b/sys/gnu/dts/include/dt-bindings/reset/stih416-resets.h deleted file mode 100644 index f682c906ed5..00000000000 --- a/sys/gnu/dts/include/dt-bindings/reset/stih416-resets.h +++ /dev/null @@ -1,52 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides constants for the reset controller - * based peripheral powerdown requests on the STMicroelectronics - * STiH416 SoC. - */ -#ifndef _DT_BINDINGS_RESET_CONTROLLER_STIH416 -#define _DT_BINDINGS_RESET_CONTROLLER_STIH416 - -#define STIH416_EMISS_POWERDOWN 0 -#define STIH416_NAND_POWERDOWN 1 -#define STIH416_KEYSCAN_POWERDOWN 2 -#define STIH416_USB0_POWERDOWN 3 -#define STIH416_USB1_POWERDOWN 4 -#define STIH416_USB2_POWERDOWN 5 -#define STIH416_USB3_POWERDOWN 6 -#define STIH416_SATA0_POWERDOWN 7 -#define STIH416_SATA1_POWERDOWN 8 -#define STIH416_PCIE0_POWERDOWN 9 -#define STIH416_PCIE1_POWERDOWN 10 - -#define STIH416_ETH0_SOFTRESET 0 -#define STIH416_ETH1_SOFTRESET 1 -#define STIH416_IRB_SOFTRESET 2 -#define STIH416_USB0_SOFTRESET 3 -#define STIH416_USB1_SOFTRESET 4 -#define STIH416_USB2_SOFTRESET 5 -#define STIH416_USB3_SOFTRESET 6 -#define STIH416_SATA0_SOFTRESET 7 -#define STIH416_SATA1_SOFTRESET 8 -#define STIH416_PCIE0_SOFTRESET 9 -#define STIH416_PCIE1_SOFTRESET 10 -#define STIH416_AUD_DAC_SOFTRESET 11 -#define STIH416_HDTVOUT_SOFTRESET 12 -#define STIH416_VTAC_M_RX_SOFTRESET 13 -#define STIH416_VTAC_A_RX_SOFTRESET 14 -#define STIH416_SYNC_HD_SOFTRESET 15 -#define STIH416_SYNC_SD_SOFTRESET 16 -#define STIH416_BLITTER_SOFTRESET 17 -#define STIH416_GPU_SOFTRESET 18 -#define STIH416_VTAC_M_TX_SOFTRESET 19 -#define STIH416_VTAC_A_TX_SOFTRESET 20 -#define STIH416_VTG_AUX_SOFTRESET 21 -#define STIH416_JPEG_DEC_SOFTRESET 22 -#define STIH416_HVA_SOFTRESET 23 -#define STIH416_COMPO_M_SOFTRESET 24 -#define STIH416_COMPO_A_SOFTRESET 25 -#define STIH416_VP8_DEC_SOFTRESET 26 -#define STIH416_VTG_MAIN_SOFTRESET 27 -#define STIH416_KEYSCAN_SOFTRESET 28 - -#endif /* _DT_BINDINGS_RESET_CONTROLLER_STIH416 */ diff --git a/sys/gnu/dts/include/dt-bindings/reset/stm32mp1-resets.h b/sys/gnu/dts/include/dt-bindings/reset/stm32mp1-resets.h deleted file mode 100644 index f0c3aaef67a..00000000000 --- a/sys/gnu/dts/include/dt-bindings/reset/stm32mp1-resets.h +++ /dev/null @@ -1,108 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ -/* - * Copyright (C) STMicroelectronics 2018 - All Rights Reserved - * Author: Gabriel Fernandez for STMicroelectronics. - */ - -#ifndef _DT_BINDINGS_STM32MP1_RESET_H_ -#define _DT_BINDINGS_STM32MP1_RESET_H_ - -#define LTDC_R 3072 -#define DSI_R 3076 -#define DDRPERFM_R 3080 -#define USBPHY_R 3088 -#define SPI6_R 3136 -#define I2C4_R 3138 -#define I2C6_R 3139 -#define USART1_R 3140 -#define STGEN_R 3156 -#define GPIOZ_R 3200 -#define CRYP1_R 3204 -#define HASH1_R 3205 -#define RNG1_R 3206 -#define AXIM_R 3216 -#define GPU_R 3269 -#define ETHMAC_R 3274 -#define FMC_R 3276 -#define QSPI_R 3278 -#define SDMMC1_R 3280 -#define SDMMC2_R 3281 -#define CRC1_R 3284 -#define USBH_R 3288 -#define MDMA_R 3328 -#define MCU_R 8225 -#define TIM2_R 19456 -#define TIM3_R 19457 -#define TIM4_R 19458 -#define TIM5_R 19459 -#define TIM6_R 19460 -#define TIM7_R 19461 -#define TIM12_R 16462 -#define TIM13_R 16463 -#define TIM14_R 16464 -#define LPTIM1_R 19465 -#define SPI2_R 19467 -#define SPI3_R 19468 -#define USART2_R 19470 -#define USART3_R 19471 -#define UART4_R 19472 -#define UART5_R 19473 -#define UART7_R 19474 -#define UART8_R 19475 -#define I2C1_R 19477 -#define I2C2_R 19478 -#define I2C3_R 19479 -#define I2C5_R 19480 -#define SPDIF_R 19482 -#define CEC_R 19483 -#define DAC12_R 19485 -#define MDIO_R 19847 -#define TIM1_R 19520 -#define TIM8_R 19521 -#define TIM15_R 19522 -#define TIM16_R 19523 -#define TIM17_R 19524 -#define SPI1_R 19528 -#define SPI4_R 19529 -#define SPI5_R 19530 -#define USART6_R 19533 -#define SAI1_R 19536 -#define SAI2_R 19537 -#define SAI3_R 19538 -#define DFSDM_R 19540 -#define FDCAN_R 19544 -#define LPTIM2_R 19584 -#define LPTIM3_R 19585 -#define LPTIM4_R 19586 -#define LPTIM5_R 19587 -#define SAI4_R 19592 -#define SYSCFG_R 19595 -#define VREF_R 19597 -#define TMPSENS_R 19600 -#define PMBCTRL_R 19601 -#define DMA1_R 19648 -#define DMA2_R 19649 -#define DMAMUX_R 19650 -#define ADC12_R 19653 -#define USBO_R 19656 -#define SDMMC3_R 19664 -#define CAMITF_R 19712 -#define CRYP2_R 19716 -#define HASH2_R 19717 -#define RNG2_R 19718 -#define CRC2_R 19719 -#define HSEM_R 19723 -#define MBOX_R 19724 -#define GPIOA_R 19776 -#define GPIOB_R 19777 -#define GPIOC_R 19778 -#define GPIOD_R 19779 -#define GPIOE_R 19780 -#define GPIOF_R 19781 -#define GPIOG_R 19782 -#define GPIOH_R 19783 -#define GPIOI_R 19784 -#define GPIOJ_R 19785 -#define GPIOK_R 19786 - -#endif /* _DT_BINDINGS_STM32MP1_RESET_H_ */ diff --git a/sys/gnu/dts/include/dt-bindings/reset/sun4i-a10-ccu.h b/sys/gnu/dts/include/dt-bindings/reset/sun4i-a10-ccu.h deleted file mode 100644 index 5f4480bedc8..00000000000 --- a/sys/gnu/dts/include/dt-bindings/reset/sun4i-a10-ccu.h +++ /dev/null @@ -1,69 +0,0 @@ -/* - * Copyright (C) 2017 Priit Laes - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_RST_SUN4I_A10_H -#define _DT_BINDINGS_RST_SUN4I_A10_H - -#define RST_USB_PHY0 1 -#define RST_USB_PHY1 2 -#define RST_USB_PHY2 3 -#define RST_GPS 4 -#define RST_DE_BE0 5 -#define RST_DE_BE1 6 -#define RST_DE_FE0 7 -#define RST_DE_FE1 8 -#define RST_DE_MP 9 -#define RST_TVE0 10 -#define RST_TCON0 11 -#define RST_TVE1 12 -#define RST_TCON1 13 -#define RST_CSI0 14 -#define RST_CSI1 15 -#define RST_VE 16 -#define RST_ACE 17 -#define RST_LVDS 18 -#define RST_GPU 19 -#define RST_HDMI_H 20 -#define RST_HDMI_SYS 21 -#define RST_HDMI_AUDIO_DMA 22 - -#endif /* DT_BINDINGS_RST_SUN4I_A10_H */ diff --git a/sys/gnu/dts/include/dt-bindings/reset/sun50i-a64-ccu.h b/sys/gnu/dts/include/dt-bindings/reset/sun50i-a64-ccu.h deleted file mode 100644 index db60b29ddb1..00000000000 --- a/sys/gnu/dts/include/dt-bindings/reset/sun50i-a64-ccu.h +++ /dev/null @@ -1,98 +0,0 @@ -/* - * Copyright (C) 2016 Maxime Ripard - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_RST_SUN50I_A64_H_ -#define _DT_BINDINGS_RST_SUN50I_A64_H_ - -#define RST_USB_PHY0 0 -#define RST_USB_PHY1 1 -#define RST_USB_HSIC 2 -#define RST_DRAM 3 -#define RST_MBUS 4 -#define RST_BUS_MIPI_DSI 5 -#define RST_BUS_CE 6 -#define RST_BUS_DMA 7 -#define RST_BUS_MMC0 8 -#define RST_BUS_MMC1 9 -#define RST_BUS_MMC2 10 -#define RST_BUS_NAND 11 -#define RST_BUS_DRAM 12 -#define RST_BUS_EMAC 13 -#define RST_BUS_TS 14 -#define RST_BUS_HSTIMER 15 -#define RST_BUS_SPI0 16 -#define RST_BUS_SPI1 17 -#define RST_BUS_OTG 18 -#define RST_BUS_EHCI0 19 -#define RST_BUS_EHCI1 20 -#define RST_BUS_OHCI0 21 -#define RST_BUS_OHCI1 22 -#define RST_BUS_VE 23 -#define RST_BUS_TCON0 24 -#define RST_BUS_TCON1 25 -#define RST_BUS_DEINTERLACE 26 -#define RST_BUS_CSI 27 -#define RST_BUS_HDMI0 28 -#define RST_BUS_HDMI1 29 -#define RST_BUS_DE 30 -#define RST_BUS_GPU 31 -#define RST_BUS_MSGBOX 32 -#define RST_BUS_SPINLOCK 33 -#define RST_BUS_DBG 34 -#define RST_BUS_LVDS 35 -#define RST_BUS_CODEC 36 -#define RST_BUS_SPDIF 37 -#define RST_BUS_THS 38 -#define RST_BUS_I2S0 39 -#define RST_BUS_I2S1 40 -#define RST_BUS_I2S2 41 -#define RST_BUS_I2C0 42 -#define RST_BUS_I2C1 43 -#define RST_BUS_I2C2 44 -#define RST_BUS_SCR 45 -#define RST_BUS_UART0 46 -#define RST_BUS_UART1 47 -#define RST_BUS_UART2 48 -#define RST_BUS_UART3 49 -#define RST_BUS_UART4 50 - -#endif /* _DT_BINDINGS_RST_SUN50I_A64_H_ */ diff --git a/sys/gnu/dts/include/dt-bindings/reset/sun50i-h6-ccu.h b/sys/gnu/dts/include/dt-bindings/reset/sun50i-h6-ccu.h deleted file mode 100644 index 81106f45509..00000000000 --- a/sys/gnu/dts/include/dt-bindings/reset/sun50i-h6-ccu.h +++ /dev/null @@ -1,73 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ or MIT) -/* - * Copyright (C) 2017 Icenowy Zheng - */ - -#ifndef _DT_BINDINGS_RESET_SUN50I_H6_H_ -#define _DT_BINDINGS_RESET_SUN50I_H6_H_ - -#define RST_MBUS 0 -#define RST_BUS_DE 1 -#define RST_BUS_DEINTERLACE 2 -#define RST_BUS_GPU 3 -#define RST_BUS_CE 4 -#define RST_BUS_VE 5 -#define RST_BUS_EMCE 6 -#define RST_BUS_VP9 7 -#define RST_BUS_DMA 8 -#define RST_BUS_MSGBOX 9 -#define RST_BUS_SPINLOCK 10 -#define RST_BUS_HSTIMER 11 -#define RST_BUS_DBG 12 -#define RST_BUS_PSI 13 -#define RST_BUS_PWM 14 -#define RST_BUS_IOMMU 15 -#define RST_BUS_DRAM 16 -#define RST_BUS_NAND 17 -#define RST_BUS_MMC0 18 -#define RST_BUS_MMC1 19 -#define RST_BUS_MMC2 20 -#define RST_BUS_UART0 21 -#define RST_BUS_UART1 22 -#define RST_BUS_UART2 23 -#define RST_BUS_UART3 24 -#define RST_BUS_I2C0 25 -#define RST_BUS_I2C1 26 -#define RST_BUS_I2C2 27 -#define RST_BUS_I2C3 28 -#define RST_BUS_SCR0 29 -#define RST_BUS_SCR1 30 -#define RST_BUS_SPI0 31 -#define RST_BUS_SPI1 32 -#define RST_BUS_EMAC 33 -#define RST_BUS_TS 34 -#define RST_BUS_IR_TX 35 -#define RST_BUS_THS 36 -#define RST_BUS_I2S0 37 -#define RST_BUS_I2S1 38 -#define RST_BUS_I2S2 39 -#define RST_BUS_I2S3 40 -#define RST_BUS_SPDIF 41 -#define RST_BUS_DMIC 42 -#define RST_BUS_AUDIO_HUB 43 -#define RST_USB_PHY0 44 -#define RST_USB_PHY1 45 -#define RST_USB_PHY3 46 -#define RST_USB_HSIC 47 -#define RST_BUS_OHCI0 48 -#define RST_BUS_OHCI3 49 -#define RST_BUS_EHCI0 50 -#define RST_BUS_XHCI 51 -#define RST_BUS_EHCI3 52 -#define RST_BUS_OTG 53 -#define RST_BUS_PCIE 54 -#define RST_PCIE_POWERUP 55 -#define RST_BUS_HDMI 56 -#define RST_BUS_HDMI_SUB 57 -#define RST_BUS_TCON_TOP 58 -#define RST_BUS_TCON_LCD0 59 -#define RST_BUS_TCON_TV0 60 -#define RST_BUS_CSI 61 -#define RST_BUS_HDCP 62 - -#endif /* _DT_BINDINGS_RESET_SUN50I_H6_H_ */ diff --git a/sys/gnu/dts/include/dt-bindings/reset/sun50i-h6-r-ccu.h b/sys/gnu/dts/include/dt-bindings/reset/sun50i-h6-r-ccu.h deleted file mode 100644 index 01c84dba49a..00000000000 --- a/sys/gnu/dts/include/dt-bindings/reset/sun50i-h6-r-ccu.h +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ -/* - * Copyright (C) 2016 Icenowy Zheng - */ - -#ifndef _DT_BINDINGS_RST_SUN50I_H6_R_CCU_H_ -#define _DT_BINDINGS_RST_SUN50I_H6_R_CCU_H_ - -#define RST_R_APB1_TIMER 0 -#define RST_R_APB1_TWD 1 -#define RST_R_APB1_PWM 2 -#define RST_R_APB2_UART 3 -#define RST_R_APB2_I2C 4 -#define RST_R_APB1_IR 5 -#define RST_R_APB1_W1 6 - -#endif /* _DT_BINDINGS_RST_SUN50I_H6_R_CCU_H_ */ diff --git a/sys/gnu/dts/include/dt-bindings/reset/sun5i-ccu.h b/sys/gnu/dts/include/dt-bindings/reset/sun5i-ccu.h deleted file mode 100644 index 40cc22ae763..00000000000 --- a/sys/gnu/dts/include/dt-bindings/reset/sun5i-ccu.h +++ /dev/null @@ -1,23 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright 2016 Maxime Ripard - * - * Maxime Ripard - */ - -#ifndef _RST_SUN5I_H_ -#define _RST_SUN5I_H_ - -#define RST_USB_PHY0 0 -#define RST_USB_PHY1 1 -#define RST_GPS 2 -#define RST_DE_BE 3 -#define RST_DE_FE 4 -#define RST_TVE 5 -#define RST_LCD 6 -#define RST_CSI 7 -#define RST_VE 8 -#define RST_GPU 9 -#define RST_IEP 10 - -#endif /* _RST_SUN5I_H_ */ diff --git a/sys/gnu/dts/include/dt-bindings/reset/sun6i-a31-ccu.h b/sys/gnu/dts/include/dt-bindings/reset/sun6i-a31-ccu.h deleted file mode 100644 index fbff365ed6e..00000000000 --- a/sys/gnu/dts/include/dt-bindings/reset/sun6i-a31-ccu.h +++ /dev/null @@ -1,106 +0,0 @@ -/* - * Copyright (C) 2016 Chen-Yu Tsai - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_RST_SUN6I_A31_H_ -#define _DT_BINDINGS_RST_SUN6I_A31_H_ - -#define RST_USB_PHY0 0 -#define RST_USB_PHY1 1 -#define RST_USB_PHY2 2 - -#define RST_AHB1_MIPI_DSI 3 -#define RST_AHB1_SS 4 -#define RST_AHB1_DMA 5 -#define RST_AHB1_MMC0 6 -#define RST_AHB1_MMC1 7 -#define RST_AHB1_MMC2 8 -#define RST_AHB1_MMC3 9 -#define RST_AHB1_NAND1 10 -#define RST_AHB1_NAND0 11 -#define RST_AHB1_SDRAM 12 -#define RST_AHB1_EMAC 13 -#define RST_AHB1_TS 14 -#define RST_AHB1_HSTIMER 15 -#define RST_AHB1_SPI0 16 -#define RST_AHB1_SPI1 17 -#define RST_AHB1_SPI2 18 -#define RST_AHB1_SPI3 19 -#define RST_AHB1_OTG 20 -#define RST_AHB1_EHCI0 21 -#define RST_AHB1_EHCI1 22 -#define RST_AHB1_OHCI0 23 -#define RST_AHB1_OHCI1 24 -#define RST_AHB1_OHCI2 25 -#define RST_AHB1_VE 26 -#define RST_AHB1_LCD0 27 -#define RST_AHB1_LCD1 28 -#define RST_AHB1_CSI 29 -#define RST_AHB1_HDMI 30 -#define RST_AHB1_BE0 31 -#define RST_AHB1_BE1 32 -#define RST_AHB1_FE0 33 -#define RST_AHB1_FE1 34 -#define RST_AHB1_MP 35 -#define RST_AHB1_GPU 36 -#define RST_AHB1_DEU0 37 -#define RST_AHB1_DEU1 38 -#define RST_AHB1_DRC0 39 -#define RST_AHB1_DRC1 40 -#define RST_AHB1_LVDS 41 - -#define RST_APB1_CODEC 42 -#define RST_APB1_SPDIF 43 -#define RST_APB1_DIGITAL_MIC 44 -#define RST_APB1_DAUDIO0 45 -#define RST_APB1_DAUDIO1 46 -#define RST_APB2_I2C0 47 -#define RST_APB2_I2C1 48 -#define RST_APB2_I2C2 49 -#define RST_APB2_I2C3 50 -#define RST_APB2_UART0 51 -#define RST_APB2_UART1 52 -#define RST_APB2_UART2 53 -#define RST_APB2_UART3 54 -#define RST_APB2_UART4 55 -#define RST_APB2_UART5 56 - -#endif /* _DT_BINDINGS_RST_SUN6I_A31_H_ */ diff --git a/sys/gnu/dts/include/dt-bindings/reset/sun8i-a23-a33-ccu.h b/sys/gnu/dts/include/dt-bindings/reset/sun8i-a23-a33-ccu.h deleted file mode 100644 index 6121f2b0cd0..00000000000 --- a/sys/gnu/dts/include/dt-bindings/reset/sun8i-a23-a33-ccu.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright (C) 2016 Maxime Ripard - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_RST_SUN8I_A23_A33_H_ -#define _DT_BINDINGS_RST_SUN8I_A23_A33_H_ - -#define RST_USB_PHY0 0 -#define RST_USB_PHY1 1 -#define RST_USB_HSIC 2 -#define RST_MBUS 3 -#define RST_BUS_MIPI_DSI 4 -#define RST_BUS_SS 5 -#define RST_BUS_DMA 6 -#define RST_BUS_MMC0 7 -#define RST_BUS_MMC1 8 -#define RST_BUS_MMC2 9 -#define RST_BUS_NAND 10 -#define RST_BUS_DRAM 11 -#define RST_BUS_HSTIMER 12 -#define RST_BUS_SPI0 13 -#define RST_BUS_SPI1 14 -#define RST_BUS_OTG 15 -#define RST_BUS_EHCI 16 -#define RST_BUS_OHCI 17 -#define RST_BUS_VE 18 -#define RST_BUS_LCD 19 -#define RST_BUS_CSI 20 -#define RST_BUS_DE_BE 21 -#define RST_BUS_DE_FE 22 -#define RST_BUS_GPU 23 -#define RST_BUS_MSGBOX 24 -#define RST_BUS_SPINLOCK 25 -#define RST_BUS_DRC 26 -#define RST_BUS_SAT 27 -#define RST_BUS_LVDS 28 -#define RST_BUS_CODEC 29 -#define RST_BUS_I2S0 30 -#define RST_BUS_I2S1 31 -#define RST_BUS_I2C0 32 -#define RST_BUS_I2C1 33 -#define RST_BUS_I2C2 34 -#define RST_BUS_UART0 35 -#define RST_BUS_UART1 36 -#define RST_BUS_UART2 37 -#define RST_BUS_UART3 38 -#define RST_BUS_UART4 39 - -#endif /* _DT_BINDINGS_RST_SUN8I_A23_A33_H_ */ diff --git a/sys/gnu/dts/include/dt-bindings/reset/sun8i-a83t-ccu.h b/sys/gnu/dts/include/dt-bindings/reset/sun8i-a83t-ccu.h deleted file mode 100644 index 784f6e11664..00000000000 --- a/sys/gnu/dts/include/dt-bindings/reset/sun8i-a83t-ccu.h +++ /dev/null @@ -1,98 +0,0 @@ -/* - * Copyright (C) 2017 Chen-Yu Tsai - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_RESET_SUN8I_A83T_CCU_H_ -#define _DT_BINDINGS_RESET_SUN8I_A83T_CCU_H_ - -#define RST_USB_PHY0 0 -#define RST_USB_PHY1 1 -#define RST_USB_HSIC 2 - -#define RST_DRAM 3 -#define RST_MBUS 4 - -#define RST_BUS_MIPI_DSI 5 -#define RST_BUS_SS 6 -#define RST_BUS_DMA 7 -#define RST_BUS_MMC0 8 -#define RST_BUS_MMC1 9 -#define RST_BUS_MMC2 10 -#define RST_BUS_NAND 11 -#define RST_BUS_DRAM 12 -#define RST_BUS_EMAC 13 -#define RST_BUS_HSTIMER 14 -#define RST_BUS_SPI0 15 -#define RST_BUS_SPI1 16 -#define RST_BUS_OTG 17 -#define RST_BUS_EHCI0 18 -#define RST_BUS_EHCI1 19 -#define RST_BUS_OHCI0 20 - -#define RST_BUS_VE 21 -#define RST_BUS_TCON0 22 -#define RST_BUS_TCON1 23 -#define RST_BUS_CSI 24 -#define RST_BUS_HDMI0 25 -#define RST_BUS_HDMI1 26 -#define RST_BUS_DE 27 -#define RST_BUS_GPU 28 -#define RST_BUS_MSGBOX 29 -#define RST_BUS_SPINLOCK 30 - -#define RST_BUS_LVDS 31 - -#define RST_BUS_SPDIF 32 -#define RST_BUS_I2S0 33 -#define RST_BUS_I2S1 34 -#define RST_BUS_I2S2 35 -#define RST_BUS_TDM 36 - -#define RST_BUS_I2C0 37 -#define RST_BUS_I2C1 38 -#define RST_BUS_I2C2 39 -#define RST_BUS_UART0 40 -#define RST_BUS_UART1 41 -#define RST_BUS_UART2 42 -#define RST_BUS_UART3 43 -#define RST_BUS_UART4 44 - -#endif /* _DT_BINDINGS_RESET_SUN8I_A83T_CCU_H_ */ diff --git a/sys/gnu/dts/include/dt-bindings/reset/sun8i-de2.h b/sys/gnu/dts/include/dt-bindings/reset/sun8i-de2.h deleted file mode 100644 index 1c36a6ac86d..00000000000 --- a/sys/gnu/dts/include/dt-bindings/reset/sun8i-de2.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright (C) 2016 Icenowy Zheng - * - * SPDX-License-Identifier: (GPL-2.0+ OR MIT) - */ - -#ifndef _DT_BINDINGS_RESET_SUN8I_DE2_H_ -#define _DT_BINDINGS_RESET_SUN8I_DE2_H_ - -#define RST_MIXER0 0 -#define RST_MIXER1 1 -#define RST_WB 2 -#define RST_ROT 3 - -#endif /* _DT_BINDINGS_RESET_SUN8I_DE2_H_ */ diff --git a/sys/gnu/dts/include/dt-bindings/reset/sun8i-h3-ccu.h b/sys/gnu/dts/include/dt-bindings/reset/sun8i-h3-ccu.h deleted file mode 100644 index 484c2a22919..00000000000 --- a/sys/gnu/dts/include/dt-bindings/reset/sun8i-h3-ccu.h +++ /dev/null @@ -1,106 +0,0 @@ -/* - * Copyright (C) 2016 Maxime Ripard - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_RST_SUN8I_H3_H_ -#define _DT_BINDINGS_RST_SUN8I_H3_H_ - -#define RST_USB_PHY0 0 -#define RST_USB_PHY1 1 -#define RST_USB_PHY2 2 -#define RST_USB_PHY3 3 - -#define RST_MBUS 4 - -#define RST_BUS_CE 5 -#define RST_BUS_DMA 6 -#define RST_BUS_MMC0 7 -#define RST_BUS_MMC1 8 -#define RST_BUS_MMC2 9 -#define RST_BUS_NAND 10 -#define RST_BUS_DRAM 11 -#define RST_BUS_EMAC 12 -#define RST_BUS_TS 13 -#define RST_BUS_HSTIMER 14 -#define RST_BUS_SPI0 15 -#define RST_BUS_SPI1 16 -#define RST_BUS_OTG 17 -#define RST_BUS_EHCI0 18 -#define RST_BUS_EHCI1 19 -#define RST_BUS_EHCI2 20 -#define RST_BUS_EHCI3 21 -#define RST_BUS_OHCI0 22 -#define RST_BUS_OHCI1 23 -#define RST_BUS_OHCI2 24 -#define RST_BUS_OHCI3 25 -#define RST_BUS_VE 26 -#define RST_BUS_TCON0 27 -#define RST_BUS_TCON1 28 -#define RST_BUS_DEINTERLACE 29 -#define RST_BUS_CSI 30 -#define RST_BUS_TVE 31 -#define RST_BUS_HDMI0 32 -#define RST_BUS_HDMI1 33 -#define RST_BUS_DE 34 -#define RST_BUS_GPU 35 -#define RST_BUS_MSGBOX 36 -#define RST_BUS_SPINLOCK 37 -#define RST_BUS_DBG 38 -#define RST_BUS_EPHY 39 -#define RST_BUS_CODEC 40 -#define RST_BUS_SPDIF 41 -#define RST_BUS_THS 42 -#define RST_BUS_I2S0 43 -#define RST_BUS_I2S1 44 -#define RST_BUS_I2S2 45 -#define RST_BUS_I2C0 46 -#define RST_BUS_I2C1 47 -#define RST_BUS_I2C2 48 -#define RST_BUS_UART0 49 -#define RST_BUS_UART1 50 -#define RST_BUS_UART2 51 -#define RST_BUS_UART3 52 -#define RST_BUS_SCR0 53 - -/* New resets imported in H5 */ -#define RST_BUS_SCR1 54 - -#endif /* _DT_BINDINGS_RST_SUN8I_H3_H_ */ diff --git a/sys/gnu/dts/include/dt-bindings/reset/sun8i-r-ccu.h b/sys/gnu/dts/include/dt-bindings/reset/sun8i-r-ccu.h deleted file mode 100644 index 4ba64f3d6fc..00000000000 --- a/sys/gnu/dts/include/dt-bindings/reset/sun8i-r-ccu.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright (C) 2016 Icenowy Zheng - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_RST_SUN8I_R_CCU_H_ -#define _DT_BINDINGS_RST_SUN8I_R_CCU_H_ - -#define RST_APB0_IR 0 -#define RST_APB0_TIMER 1 -#define RST_APB0_RSB 2 -#define RST_APB0_UART 3 -/* 4 is reserved for RST_APB0_W1 on A31 */ -#define RST_APB0_I2C 5 - -#endif /* _DT_BINDINGS_RST_SUN8I_R_CCU_H_ */ diff --git a/sys/gnu/dts/include/dt-bindings/reset/sun8i-r40-ccu.h b/sys/gnu/dts/include/dt-bindings/reset/sun8i-r40-ccu.h deleted file mode 100644 index c5ebcf6672e..00000000000 --- a/sys/gnu/dts/include/dt-bindings/reset/sun8i-r40-ccu.h +++ /dev/null @@ -1,130 +0,0 @@ -/* - * Copyright (C) 2017 Icenowy Zheng - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_RST_SUN8I_R40_H_ -#define _DT_BINDINGS_RST_SUN8I_R40_H_ - -#define RST_USB_PHY0 0 -#define RST_USB_PHY1 1 -#define RST_USB_PHY2 2 - -#define RST_DRAM 3 -#define RST_MBUS 4 - -#define RST_BUS_MIPI_DSI 5 -#define RST_BUS_CE 6 -#define RST_BUS_DMA 7 -#define RST_BUS_MMC0 8 -#define RST_BUS_MMC1 9 -#define RST_BUS_MMC2 10 -#define RST_BUS_MMC3 11 -#define RST_BUS_NAND 12 -#define RST_BUS_DRAM 13 -#define RST_BUS_EMAC 14 -#define RST_BUS_TS 15 -#define RST_BUS_HSTIMER 16 -#define RST_BUS_SPI0 17 -#define RST_BUS_SPI1 18 -#define RST_BUS_SPI2 19 -#define RST_BUS_SPI3 20 -#define RST_BUS_SATA 21 -#define RST_BUS_OTG 22 -#define RST_BUS_EHCI0 23 -#define RST_BUS_EHCI1 24 -#define RST_BUS_EHCI2 25 -#define RST_BUS_OHCI0 26 -#define RST_BUS_OHCI1 27 -#define RST_BUS_OHCI2 28 -#define RST_BUS_VE 29 -#define RST_BUS_MP 30 -#define RST_BUS_DEINTERLACE 31 -#define RST_BUS_CSI0 32 -#define RST_BUS_CSI1 33 -#define RST_BUS_HDMI0 34 -#define RST_BUS_HDMI1 35 -#define RST_BUS_DE 36 -#define RST_BUS_TVE0 37 -#define RST_BUS_TVE1 38 -#define RST_BUS_TVE_TOP 39 -#define RST_BUS_GMAC 40 -#define RST_BUS_GPU 41 -#define RST_BUS_TVD0 42 -#define RST_BUS_TVD1 43 -#define RST_BUS_TVD2 44 -#define RST_BUS_TVD3 45 -#define RST_BUS_TVD_TOP 46 -#define RST_BUS_TCON_LCD0 47 -#define RST_BUS_TCON_LCD1 48 -#define RST_BUS_TCON_TV0 49 -#define RST_BUS_TCON_TV1 50 -#define RST_BUS_TCON_TOP 51 -#define RST_BUS_DBG 52 -#define RST_BUS_LVDS 53 -#define RST_BUS_CODEC 54 -#define RST_BUS_SPDIF 55 -#define RST_BUS_AC97 56 -#define RST_BUS_IR0 57 -#define RST_BUS_IR1 58 -#define RST_BUS_THS 59 -#define RST_BUS_KEYPAD 60 -#define RST_BUS_I2S0 61 -#define RST_BUS_I2S1 62 -#define RST_BUS_I2S2 63 -#define RST_BUS_I2C0 64 -#define RST_BUS_I2C1 65 -#define RST_BUS_I2C2 66 -#define RST_BUS_I2C3 67 -#define RST_BUS_CAN 68 -#define RST_BUS_SCR 69 -#define RST_BUS_PS20 70 -#define RST_BUS_PS21 71 -#define RST_BUS_I2C4 72 -#define RST_BUS_UART0 73 -#define RST_BUS_UART1 74 -#define RST_BUS_UART2 75 -#define RST_BUS_UART3 76 -#define RST_BUS_UART4 77 -#define RST_BUS_UART5 78 -#define RST_BUS_UART6 79 -#define RST_BUS_UART7 80 - -#endif /* _DT_BINDINGS_RST_SUN8I_R40_H_ */ diff --git a/sys/gnu/dts/include/dt-bindings/reset/sun8i-v3s-ccu.h b/sys/gnu/dts/include/dt-bindings/reset/sun8i-v3s-ccu.h deleted file mode 100644 index b6790173afd..00000000000 --- a/sys/gnu/dts/include/dt-bindings/reset/sun8i-v3s-ccu.h +++ /dev/null @@ -1,81 +0,0 @@ -/* - * Copyright (C) 2016 Icenowy Zheng - * - * Based on sun8i-v3s-ccu.h, which is - * Copyright (C) 2016 Maxime Ripard - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_RST_SUN8I_V3S_H_ -#define _DT_BINDINGS_RST_SUN8I_V3S_H_ - -#define RST_USB_PHY0 0 - -#define RST_MBUS 1 - -#define RST_BUS_CE 5 -#define RST_BUS_DMA 6 -#define RST_BUS_MMC0 7 -#define RST_BUS_MMC1 8 -#define RST_BUS_MMC2 9 -#define RST_BUS_DRAM 11 -#define RST_BUS_EMAC 12 -#define RST_BUS_HSTIMER 14 -#define RST_BUS_SPI0 15 -#define RST_BUS_OTG 17 -#define RST_BUS_EHCI0 18 -#define RST_BUS_OHCI0 22 -#define RST_BUS_VE 26 -#define RST_BUS_TCON0 27 -#define RST_BUS_CSI 30 -#define RST_BUS_DE 34 -#define RST_BUS_DBG 38 -#define RST_BUS_EPHY 39 -#define RST_BUS_CODEC 40 -#define RST_BUS_I2C0 46 -#define RST_BUS_I2C1 47 -#define RST_BUS_UART0 49 -#define RST_BUS_UART1 50 -#define RST_BUS_UART2 51 - -/* Reset lines not available on V3s */ -#define RST_BUS_I2S0 52 - -#endif /* _DT_BINDINGS_RST_SUN8I_H3_H_ */ diff --git a/sys/gnu/dts/include/dt-bindings/reset/sun9i-a80-ccu.h b/sys/gnu/dts/include/dt-bindings/reset/sun9i-a80-ccu.h deleted file mode 100644 index 4b8df4b3678..00000000000 --- a/sys/gnu/dts/include/dt-bindings/reset/sun9i-a80-ccu.h +++ /dev/null @@ -1,102 +0,0 @@ -/* - * Copyright (C) 2016 Chen-Yu Tsai - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_RESET_SUN9I_A80_CCU_H_ -#define _DT_BINDINGS_RESET_SUN9I_A80_CCU_H_ - -#define RST_BUS_FD 0 -#define RST_BUS_VE 1 -#define RST_BUS_GPU_CTRL 2 -#define RST_BUS_SS 3 -#define RST_BUS_MMC 4 -#define RST_BUS_NAND0 5 -#define RST_BUS_NAND1 6 -#define RST_BUS_SDRAM 7 -#define RST_BUS_SATA 8 -#define RST_BUS_TS 9 -#define RST_BUS_SPI0 10 -#define RST_BUS_SPI1 11 -#define RST_BUS_SPI2 12 -#define RST_BUS_SPI3 13 - -#define RST_BUS_OTG 14 -#define RST_BUS_OTG_PHY 15 -#define RST_BUS_MIPI_HSI 16 -#define RST_BUS_GMAC 17 -#define RST_BUS_MSGBOX 18 -#define RST_BUS_SPINLOCK 19 -#define RST_BUS_HSTIMER 20 -#define RST_BUS_DMA 21 - -#define RST_BUS_LCD0 22 -#define RST_BUS_LCD1 23 -#define RST_BUS_EDP 24 -#define RST_BUS_LVDS 25 -#define RST_BUS_CSI 26 -#define RST_BUS_HDMI0 27 -#define RST_BUS_HDMI1 28 -#define RST_BUS_DE 29 -#define RST_BUS_MP 30 -#define RST_BUS_GPU 31 -#define RST_BUS_MIPI_DSI 32 - -#define RST_BUS_SPDIF 33 -#define RST_BUS_AC97 34 -#define RST_BUS_I2S0 35 -#define RST_BUS_I2S1 36 -#define RST_BUS_LRADC 37 -#define RST_BUS_GPADC 38 -#define RST_BUS_CIR_TX 39 - -#define RST_BUS_I2C0 40 -#define RST_BUS_I2C1 41 -#define RST_BUS_I2C2 42 -#define RST_BUS_I2C3 43 -#define RST_BUS_I2C4 44 -#define RST_BUS_UART0 45 -#define RST_BUS_UART1 46 -#define RST_BUS_UART2 47 -#define RST_BUS_UART3 48 -#define RST_BUS_UART4 49 -#define RST_BUS_UART5 50 - -#endif /* _DT_BINDINGS_RESET_SUN9I_A80_CCU_H_ */ diff --git a/sys/gnu/dts/include/dt-bindings/reset/sun9i-a80-de.h b/sys/gnu/dts/include/dt-bindings/reset/sun9i-a80-de.h deleted file mode 100644 index 20507277017..00000000000 --- a/sys/gnu/dts/include/dt-bindings/reset/sun9i-a80-de.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * Copyright (C) 2016 Chen-Yu Tsai - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_RESET_SUN9I_A80_DE_H_ -#define _DT_BINDINGS_RESET_SUN9I_A80_DE_H_ - -#define RST_FE0 0 -#define RST_FE1 1 -#define RST_FE2 2 -#define RST_DEU0 3 -#define RST_DEU1 4 -#define RST_BE0 5 -#define RST_BE1 6 -#define RST_BE2 7 -#define RST_DRC0 8 -#define RST_DRC1 9 -#define RST_MERGE 10 - -#endif /* _DT_BINDINGS_RESET_SUN9I_A80_DE_H_ */ diff --git a/sys/gnu/dts/include/dt-bindings/reset/sun9i-a80-usb.h b/sys/gnu/dts/include/dt-bindings/reset/sun9i-a80-usb.h deleted file mode 100644 index ee492864c2a..00000000000 --- a/sys/gnu/dts/include/dt-bindings/reset/sun9i-a80-usb.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - * Copyright (C) 2016 Chen-Yu Tsai - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_RESET_SUN9I_A80_USB_H_ -#define _DT_BINDINGS_RESET_SUN9I_A80_USB_H_ - -#define RST_USB0_HCI 0 -#define RST_USB1_HCI 1 -#define RST_USB2_HCI 2 - -#define RST_USB0_PHY 3 -#define RST_USB1_HSIC 4 -#define RST_USB1_PHY 5 -#define RST_USB2_HSIC 6 -#define RST_USB2_PHY 7 - -#endif /* _DT_BINDINGS_RESET_SUN9I_A80_USB_H_ */ diff --git a/sys/gnu/dts/include/dt-bindings/reset/suniv-ccu-f1c100s.h b/sys/gnu/dts/include/dt-bindings/reset/suniv-ccu-f1c100s.h deleted file mode 100644 index 6a4b4385fe5..00000000000 --- a/sys/gnu/dts/include/dt-bindings/reset/suniv-ccu-f1c100s.h +++ /dev/null @@ -1,38 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) - * - * Copyright (C) 2018 Icenowy Zheng - * - */ - -#ifndef _DT_BINDINGS_RST_SUNIV_F1C100S_H_ -#define _DT_BINDINGS_RST_SUNIV_F1C100S_H_ - -#define RST_USB_PHY0 0 -#define RST_BUS_DMA 1 -#define RST_BUS_MMC0 2 -#define RST_BUS_MMC1 3 -#define RST_BUS_DRAM 4 -#define RST_BUS_SPI0 5 -#define RST_BUS_SPI1 6 -#define RST_BUS_OTG 7 -#define RST_BUS_VE 8 -#define RST_BUS_LCD 9 -#define RST_BUS_DEINTERLACE 10 -#define RST_BUS_CSI 11 -#define RST_BUS_TVD 12 -#define RST_BUS_TVE 13 -#define RST_BUS_DE_BE 14 -#define RST_BUS_DE_FE 15 -#define RST_BUS_CODEC 16 -#define RST_BUS_SPDIF 17 -#define RST_BUS_IR 18 -#define RST_BUS_RSB 19 -#define RST_BUS_I2S0 20 -#define RST_BUS_I2C0 21 -#define RST_BUS_I2C1 22 -#define RST_BUS_I2C2 23 -#define RST_BUS_UART0 24 -#define RST_BUS_UART1 25 -#define RST_BUS_UART2 26 - -#endif /* _DT_BINDINGS_RST_SUNIV_F1C100S_H_ */ diff --git a/sys/gnu/dts/include/dt-bindings/reset/tegra124-car.h b/sys/gnu/dts/include/dt-bindings/reset/tegra124-car.h deleted file mode 100644 index 97d2f3db82b..00000000000 --- a/sys/gnu/dts/include/dt-bindings/reset/tegra124-car.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides Tegra124-specific constants for binding - * nvidia,tegra124-car. - */ - -#ifndef _DT_BINDINGS_RESET_TEGRA124_CAR_H -#define _DT_BINDINGS_RESET_TEGRA124_CAR_H - -#define TEGRA124_RESET(x) (6 * 32 + (x)) -#define TEGRA124_RST_DFLL_DVCO TEGRA124_RESET(0) - -#endif /* _DT_BINDINGS_RESET_TEGRA124_CAR_H */ diff --git a/sys/gnu/dts/include/dt-bindings/reset/tegra186-reset.h b/sys/gnu/dts/include/dt-bindings/reset/tegra186-reset.h deleted file mode 100644 index 3c60e3e03eb..00000000000 --- a/sys/gnu/dts/include/dt-bindings/reset/tegra186-reset.h +++ /dev/null @@ -1,206 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. - */ - -#ifndef _ABI_MACH_T186_RESET_T186_H_ -#define _ABI_MACH_T186_RESET_T186_H_ - - -#define TEGRA186_RESET_ACTMON 0 -#define TEGRA186_RESET_AFI 1 -#define TEGRA186_RESET_CEC 2 -#define TEGRA186_RESET_CSITE 3 -#define TEGRA186_RESET_DP2 4 -#define TEGRA186_RESET_DPAUX 5 -#define TEGRA186_RESET_DSI 6 -#define TEGRA186_RESET_DSIB 7 -#define TEGRA186_RESET_DTV 8 -#define TEGRA186_RESET_DVFS 9 -#define TEGRA186_RESET_ENTROPY 10 -#define TEGRA186_RESET_EXTPERIPH1 11 -#define TEGRA186_RESET_EXTPERIPH2 12 -#define TEGRA186_RESET_EXTPERIPH3 13 -#define TEGRA186_RESET_GPU 14 -#define TEGRA186_RESET_HDA 15 -#define TEGRA186_RESET_HDA2CODEC_2X 16 -#define TEGRA186_RESET_HDA2HDMICODEC 17 -#define TEGRA186_RESET_HOST1X 18 -#define TEGRA186_RESET_I2C1 19 -#define TEGRA186_RESET_I2C2 20 -#define TEGRA186_RESET_I2C3 21 -#define TEGRA186_RESET_I2C4 22 -#define TEGRA186_RESET_I2C5 23 -#define TEGRA186_RESET_I2C6 24 -#define TEGRA186_RESET_ISP 25 -#define TEGRA186_RESET_KFUSE 26 -#define TEGRA186_RESET_LA 27 -#define TEGRA186_RESET_MIPI_CAL 28 -#define TEGRA186_RESET_PCIE 29 -#define TEGRA186_RESET_PCIEXCLK 30 -#define TEGRA186_RESET_SATA 31 -#define TEGRA186_RESET_SATACOLD 32 -#define TEGRA186_RESET_SDMMC1 33 -#define TEGRA186_RESET_SDMMC2 34 -#define TEGRA186_RESET_SDMMC3 35 -#define TEGRA186_RESET_SDMMC4 36 -#define TEGRA186_RESET_SE 37 -#define TEGRA186_RESET_SOC_THERM 38 -#define TEGRA186_RESET_SOR0 39 -#define TEGRA186_RESET_SPI1 40 -#define TEGRA186_RESET_SPI2 41 -#define TEGRA186_RESET_SPI3 42 -#define TEGRA186_RESET_SPI4 43 -#define TEGRA186_RESET_TMR 44 -#define TEGRA186_RESET_TRIG_SYS 45 -#define TEGRA186_RESET_TSEC 46 -#define TEGRA186_RESET_UARTA 47 -#define TEGRA186_RESET_UARTB 48 -#define TEGRA186_RESET_UARTC 49 -#define TEGRA186_RESET_UARTD 50 -#define TEGRA186_RESET_VI 51 -#define TEGRA186_RESET_VIC 52 -#define TEGRA186_RESET_XUSB_DEV 53 -#define TEGRA186_RESET_XUSB_HOST 54 -#define TEGRA186_RESET_XUSB_PADCTL 55 -#define TEGRA186_RESET_XUSB_SS 56 -#define TEGRA186_RESET_AON_APB 57 -#define TEGRA186_RESET_AXI_CBB 58 -#define TEGRA186_RESET_BPMP_APB 59 -#define TEGRA186_RESET_CAN1 60 -#define TEGRA186_RESET_CAN2 61 -#define TEGRA186_RESET_DMIC5 62 -#define TEGRA186_RESET_DSIC 63 -#define TEGRA186_RESET_DSID 64 -#define TEGRA186_RESET_EMC_EMC 65 -#define TEGRA186_RESET_EMC_MEM 66 -#define TEGRA186_RESET_EMCSB_EMC 67 -#define TEGRA186_RESET_EMCSB_MEM 68 -#define TEGRA186_RESET_EQOS 69 -#define TEGRA186_RESET_GPCDMA 70 -#define TEGRA186_RESET_GPIO_CTL0 71 -#define TEGRA186_RESET_GPIO_CTL1 72 -#define TEGRA186_RESET_GPIO_CTL2 73 -#define TEGRA186_RESET_GPIO_CTL3 74 -#define TEGRA186_RESET_GPIO_CTL4 75 -#define TEGRA186_RESET_GPIO_CTL5 76 -#define TEGRA186_RESET_I2C10 77 -#define TEGRA186_RESET_I2C12 78 -#define TEGRA186_RESET_I2C13 79 -#define TEGRA186_RESET_I2C14 80 -#define TEGRA186_RESET_I2C7 81 -#define TEGRA186_RESET_I2C8 82 -#define TEGRA186_RESET_I2C9 83 -#define TEGRA186_RESET_JTAG2AXI 84 -#define TEGRA186_RESET_MPHY_IOBIST 85 -#define TEGRA186_RESET_MPHY_L0_RX 86 -#define TEGRA186_RESET_MPHY_L0_TX 87 -#define TEGRA186_RESET_NVCSI 88 -#define TEGRA186_RESET_NVDISPLAY0_HEAD0 89 -#define TEGRA186_RESET_NVDISPLAY0_HEAD1 90 -#define TEGRA186_RESET_NVDISPLAY0_HEAD2 91 -#define TEGRA186_RESET_NVDISPLAY0_MISC 92 -#define TEGRA186_RESET_NVDISPLAY0_WGRP0 93 -#define TEGRA186_RESET_NVDISPLAY0_WGRP1 94 -#define TEGRA186_RESET_NVDISPLAY0_WGRP2 95 -#define TEGRA186_RESET_NVDISPLAY0_WGRP3 96 -#define TEGRA186_RESET_NVDISPLAY0_WGRP4 97 -#define TEGRA186_RESET_NVDISPLAY0_WGRP5 98 -#define TEGRA186_RESET_PWM1 99 -#define TEGRA186_RESET_PWM2 100 -#define TEGRA186_RESET_PWM3 101 -#define TEGRA186_RESET_PWM4 102 -#define TEGRA186_RESET_PWM5 103 -#define TEGRA186_RESET_PWM6 104 -#define TEGRA186_RESET_PWM7 105 -#define TEGRA186_RESET_PWM8 106 -#define TEGRA186_RESET_SCE_APB 107 -#define TEGRA186_RESET_SOR1 108 -#define TEGRA186_RESET_TACH 109 -#define TEGRA186_RESET_TSC 110 -#define TEGRA186_RESET_UARTF 111 -#define TEGRA186_RESET_UARTG 112 -#define TEGRA186_RESET_UFSHC 113 -#define TEGRA186_RESET_UFSHC_AXI_M 114 -#define TEGRA186_RESET_UPHY 115 -#define TEGRA186_RESET_ADSP 116 -#define TEGRA186_RESET_ADSPDBG 117 -#define TEGRA186_RESET_ADSPINTF 118 -#define TEGRA186_RESET_ADSPNEON 119 -#define TEGRA186_RESET_ADSPPERIPH 120 -#define TEGRA186_RESET_ADSPSCU 121 -#define TEGRA186_RESET_ADSPWDT 122 -#define TEGRA186_RESET_APE 123 -#define TEGRA186_RESET_DPAUX1 124 -#define TEGRA186_RESET_NVDEC 125 -#define TEGRA186_RESET_NVENC 126 -#define TEGRA186_RESET_NVJPG 127 -#define TEGRA186_RESET_PEX_USB_UPHY 128 -#define TEGRA186_RESET_QSPI 129 -#define TEGRA186_RESET_TSECB 130 -#define TEGRA186_RESET_VI_I2C 131 -#define TEGRA186_RESET_UARTE 132 -#define TEGRA186_RESET_TOP_GTE 133 -#define TEGRA186_RESET_SHSP 134 -#define TEGRA186_RESET_PEX_USB_UPHY_L5 135 -#define TEGRA186_RESET_PEX_USB_UPHY_L4 136 -#define TEGRA186_RESET_PEX_USB_UPHY_L3 137 -#define TEGRA186_RESET_PEX_USB_UPHY_L2 138 -#define TEGRA186_RESET_PEX_USB_UPHY_L1 139 -#define TEGRA186_RESET_PEX_USB_UPHY_L0 140 -#define TEGRA186_RESET_PEX_USB_UPHY_PLL1 141 -#define TEGRA186_RESET_PEX_USB_UPHY_PLL0 142 -#define TEGRA186_RESET_TSCTNVI 143 -#define TEGRA186_RESET_EXTPERIPH4 144 -#define TEGRA186_RESET_DSIPADCTL 145 -#define TEGRA186_RESET_AUD_MCLK 146 -#define TEGRA186_RESET_MPHY_CLK_CTL 147 -#define TEGRA186_RESET_MPHY_L1_RX 148 -#define TEGRA186_RESET_MPHY_L1_TX 149 -#define TEGRA186_RESET_UFSHC_LP 150 -#define TEGRA186_RESET_BPMP_NIC 151 -#define TEGRA186_RESET_BPMP_NSYSPORESET 152 -#define TEGRA186_RESET_BPMP_NRESET 153 -#define TEGRA186_RESET_BPMP_DBGRESETN 154 -#define TEGRA186_RESET_BPMP_PRESETDBGN 155 -#define TEGRA186_RESET_BPMP_PM 156 -#define TEGRA186_RESET_BPMP_CVC 157 -#define TEGRA186_RESET_BPMP_DMA 158 -#define TEGRA186_RESET_BPMP_HSP 159 -#define TEGRA186_RESET_TSCTNBPMP 160 -#define TEGRA186_RESET_BPMP_TKE 161 -#define TEGRA186_RESET_BPMP_GTE 162 -#define TEGRA186_RESET_BPMP_PM_ACTMON 163 -#define TEGRA186_RESET_AON_NIC 164 -#define TEGRA186_RESET_AON_NSYSPORESET 165 -#define TEGRA186_RESET_AON_NRESET 166 -#define TEGRA186_RESET_AON_DBGRESETN 167 -#define TEGRA186_RESET_AON_PRESETDBGN 168 -#define TEGRA186_RESET_AON_ACTMON 169 -#define TEGRA186_RESET_AOPM 170 -#define TEGRA186_RESET_AOVC 171 -#define TEGRA186_RESET_AON_DMA 172 -#define TEGRA186_RESET_AON_GPIO 173 -#define TEGRA186_RESET_AON_HSP 174 -#define TEGRA186_RESET_TSCTNAON 175 -#define TEGRA186_RESET_AON_TKE 176 -#define TEGRA186_RESET_AON_GTE 177 -#define TEGRA186_RESET_SCE_NIC 178 -#define TEGRA186_RESET_SCE_NSYSPORESET 179 -#define TEGRA186_RESET_SCE_NRESET 180 -#define TEGRA186_RESET_SCE_DBGRESETN 181 -#define TEGRA186_RESET_SCE_PRESETDBGN 182 -#define TEGRA186_RESET_SCE_ACTMON 183 -#define TEGRA186_RESET_SCE_PM 184 -#define TEGRA186_RESET_SCE_DMA 185 -#define TEGRA186_RESET_SCE_HSP 186 -#define TEGRA186_RESET_TSCTNSCE 187 -#define TEGRA186_RESET_SCE_TKE 188 -#define TEGRA186_RESET_SCE_GTE 189 -#define TEGRA186_RESET_SCE_CFG 190 -#define TEGRA186_RESET_ADSP_ALL 191 -/** @brief controls the power up/down sequence of UFSHC PSW partition. Controls LP_PWR_READY, LP_ISOL_EN, and LP_RESET_N signals */ -#define TEGRA186_RESET_UFSHC_LP_SEQ 192 -#define TEGRA186_RESET_SIZE 193 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/reset/tegra194-reset.h b/sys/gnu/dts/include/dt-bindings/reset/tegra194-reset.h deleted file mode 100644 index 473afaa25bf..00000000000 --- a/sys/gnu/dts/include/dt-bindings/reset/tegra194-reset.h +++ /dev/null @@ -1,152 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. */ - -#ifndef __ABI_MACH_T194_RESET_H -#define __ABI_MACH_T194_RESET_H - -#define TEGRA194_RESET_ACTMON 1 -#define TEGRA194_RESET_ADSP_ALL 2 -#define TEGRA194_RESET_AFI 3 -#define TEGRA194_RESET_CAN1 4 -#define TEGRA194_RESET_CAN2 5 -#define TEGRA194_RESET_DLA0 6 -#define TEGRA194_RESET_DLA1 7 -#define TEGRA194_RESET_DPAUX 8 -#define TEGRA194_RESET_DPAUX1 9 -#define TEGRA194_RESET_DPAUX2 10 -#define TEGRA194_RESET_DPAUX3 11 -#define TEGRA194_RESET_EQOS 17 -#define TEGRA194_RESET_GPCDMA 18 -#define TEGRA194_RESET_GPU 19 -#define TEGRA194_RESET_HDA 20 -#define TEGRA194_RESET_HDA2CODEC_2X 21 -#define TEGRA194_RESET_HDA2HDMICODEC 22 -#define TEGRA194_RESET_HOST1X 23 -#define TEGRA194_RESET_I2C1 24 -#define TEGRA194_RESET_I2C10 25 -#define TEGRA194_RESET_RSVD_26 26 -#define TEGRA194_RESET_RSVD_27 27 -#define TEGRA194_RESET_RSVD_28 28 -#define TEGRA194_RESET_I2C2 29 -#define TEGRA194_RESET_I2C3 30 -#define TEGRA194_RESET_I2C4 31 -#define TEGRA194_RESET_I2C6 32 -#define TEGRA194_RESET_I2C7 33 -#define TEGRA194_RESET_I2C8 34 -#define TEGRA194_RESET_I2C9 35 -#define TEGRA194_RESET_ISP 36 -#define TEGRA194_RESET_MIPI_CAL 37 -#define TEGRA194_RESET_MPHY_CLK_CTL 38 -#define TEGRA194_RESET_MPHY_L0_RX 39 -#define TEGRA194_RESET_MPHY_L0_TX 40 -#define TEGRA194_RESET_MPHY_L1_RX 41 -#define TEGRA194_RESET_MPHY_L1_TX 42 -#define TEGRA194_RESET_NVCSI 43 -#define TEGRA194_RESET_NVDEC 44 -#define TEGRA194_RESET_NVDISPLAY0_HEAD0 45 -#define TEGRA194_RESET_NVDISPLAY0_HEAD1 46 -#define TEGRA194_RESET_NVDISPLAY0_HEAD2 47 -#define TEGRA194_RESET_NVDISPLAY0_HEAD3 48 -#define TEGRA194_RESET_NVDISPLAY0_MISC 49 -#define TEGRA194_RESET_NVDISPLAY0_WGRP0 50 -#define TEGRA194_RESET_NVDISPLAY0_WGRP1 51 -#define TEGRA194_RESET_NVDISPLAY0_WGRP2 52 -#define TEGRA194_RESET_NVDISPLAY0_WGRP3 53 -#define TEGRA194_RESET_NVDISPLAY0_WGRP4 54 -#define TEGRA194_RESET_NVDISPLAY0_WGRP5 55 -#define TEGRA194_RESET_RSVD_56 56 -#define TEGRA194_RESET_RSVD_57 57 -#define TEGRA194_RESET_RSVD_58 58 -#define TEGRA194_RESET_NVENC 59 -#define TEGRA194_RESET_NVENC1 60 -#define TEGRA194_RESET_NVJPG 61 -#define TEGRA194_RESET_PCIE 62 -#define TEGRA194_RESET_PCIEXCLK 63 -#define TEGRA194_RESET_RSVD_64 64 -#define TEGRA194_RESET_RSVD_65 65 -#define TEGRA194_RESET_PVA0_ALL 66 -#define TEGRA194_RESET_PVA1_ALL 67 -#define TEGRA194_RESET_PWM1 68 -#define TEGRA194_RESET_PWM2 69 -#define TEGRA194_RESET_PWM3 70 -#define TEGRA194_RESET_PWM4 71 -#define TEGRA194_RESET_PWM5 72 -#define TEGRA194_RESET_PWM6 73 -#define TEGRA194_RESET_PWM7 74 -#define TEGRA194_RESET_PWM8 75 -#define TEGRA194_RESET_QSPI0 76 -#define TEGRA194_RESET_QSPI1 77 -#define TEGRA194_RESET_SATA 78 -#define TEGRA194_RESET_SATACOLD 79 -#define TEGRA194_RESET_SCE_ALL 80 -#define TEGRA194_RESET_RCE_ALL 81 -#define TEGRA194_RESET_SDMMC1 82 -#define TEGRA194_RESET_RSVD_83 83 -#define TEGRA194_RESET_SDMMC3 84 -#define TEGRA194_RESET_SDMMC4 85 -#define TEGRA194_RESET_SE 86 -#define TEGRA194_RESET_SOR0 87 -#define TEGRA194_RESET_SOR1 88 -#define TEGRA194_RESET_SOR2 89 -#define TEGRA194_RESET_SOR3 90 -#define TEGRA194_RESET_SPI1 91 -#define TEGRA194_RESET_SPI2 92 -#define TEGRA194_RESET_SPI3 93 -#define TEGRA194_RESET_SPI4 94 -#define TEGRA194_RESET_TACH 95 -#define TEGRA194_RESET_RSVD_96 96 -#define TEGRA194_RESET_TSCTNVI 97 -#define TEGRA194_RESET_TSEC 98 -#define TEGRA194_RESET_TSECB 99 -#define TEGRA194_RESET_UARTA 100 -#define TEGRA194_RESET_UARTB 101 -#define TEGRA194_RESET_UARTC 102 -#define TEGRA194_RESET_UARTD 103 -#define TEGRA194_RESET_UARTE 104 -#define TEGRA194_RESET_UARTF 105 -#define TEGRA194_RESET_UARTG 106 -#define TEGRA194_RESET_UARTH 107 -#define TEGRA194_RESET_UFSHC 108 -#define TEGRA194_RESET_UFSHC_AXI_M 109 -#define TEGRA194_RESET_UFSHC_LP_SEQ 110 -#define TEGRA194_RESET_RSVD_111 111 -#define TEGRA194_RESET_VI 112 -#define TEGRA194_RESET_VIC 113 -#define TEGRA194_RESET_XUSB_PADCTL 114 -#define TEGRA194_RESET_NVDEC1 115 -#define TEGRA194_RESET_PEX0_CORE_0 116 -#define TEGRA194_RESET_PEX0_CORE_1 117 -#define TEGRA194_RESET_PEX0_CORE_2 118 -#define TEGRA194_RESET_PEX0_CORE_3 119 -#define TEGRA194_RESET_PEX0_CORE_4 120 -#define TEGRA194_RESET_PEX0_CORE_0_APB 121 -#define TEGRA194_RESET_PEX0_CORE_1_APB 122 -#define TEGRA194_RESET_PEX0_CORE_2_APB 123 -#define TEGRA194_RESET_PEX0_CORE_3_APB 124 -#define TEGRA194_RESET_PEX0_CORE_4_APB 125 -#define TEGRA194_RESET_PEX0_COMMON_APB 126 -#define TEGRA194_RESET_PEX1_CORE_5 129 -#define TEGRA194_RESET_PEX1_CORE_5_APB 130 -#define TEGRA194_RESET_CVNAS 131 -#define TEGRA194_RESET_CVNAS_FCM 132 -#define TEGRA194_RESET_DMIC5 144 -#define TEGRA194_RESET_APE 145 -#define TEGRA194_RESET_PEX_USB_UPHY 146 -#define TEGRA194_RESET_PEX_USB_UPHY_L0 147 -#define TEGRA194_RESET_PEX_USB_UPHY_L1 148 -#define TEGRA194_RESET_PEX_USB_UPHY_L2 149 -#define TEGRA194_RESET_PEX_USB_UPHY_L3 150 -#define TEGRA194_RESET_PEX_USB_UPHY_L4 151 -#define TEGRA194_RESET_PEX_USB_UPHY_L5 152 -#define TEGRA194_RESET_PEX_USB_UPHY_L6 153 -#define TEGRA194_RESET_PEX_USB_UPHY_L7 154 -#define TEGRA194_RESET_PEX_USB_UPHY_L8 155 -#define TEGRA194_RESET_PEX_USB_UPHY_L9 156 -#define TEGRA194_RESET_PEX_USB_UPHY_L10 157 -#define TEGRA194_RESET_PEX_USB_UPHY_L11 158 -#define TEGRA194_RESET_PEX_USB_UPHY_PLL0 159 -#define TEGRA194_RESET_PEX_USB_UPHY_PLL1 160 -#define TEGRA194_RESET_PEX_USB_UPHY_PLL2 161 -#define TEGRA194_RESET_PEX_USB_UPHY_PLL3 162 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/reset/tegra210-car.h b/sys/gnu/dts/include/dt-bindings/reset/tegra210-car.h deleted file mode 100644 index 9dc84ec7630..00000000000 --- a/sys/gnu/dts/include/dt-bindings/reset/tegra210-car.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides Tegra210-specific constants for binding - * nvidia,tegra210-car. - */ - -#ifndef _DT_BINDINGS_RESET_TEGRA210_CAR_H -#define _DT_BINDINGS_RESET_TEGRA210_CAR_H - -#define TEGRA210_RESET(x) (7 * 32 + (x)) -#define TEGRA210_RST_DFLL_DVCO TEGRA210_RESET(0) -#define TEGRA210_RST_ADSP TEGRA210_RESET(1) - -#endif /* _DT_BINDINGS_RESET_TEGRA210_CAR_H */ diff --git a/sys/gnu/dts/include/dt-bindings/reset/ti-syscon.h b/sys/gnu/dts/include/dt-bindings/reset/ti-syscon.h deleted file mode 100644 index 6d696d2d150..00000000000 --- a/sys/gnu/dts/include/dt-bindings/reset/ti-syscon.h +++ /dev/null @@ -1,29 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * TI Syscon Reset definitions - * - * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/ - */ - -#ifndef __DT_BINDINGS_RESET_TI_SYSCON_H__ -#define __DT_BINDINGS_RESET_TI_SYSCON_H__ - -/* - * The reset does not support the feature and corresponding - * values are not valid - */ -#define ASSERT_NONE (1 << 0) -#define DEASSERT_NONE (1 << 1) -#define STATUS_NONE (1 << 2) - -/* When set this function is activated by setting(vs clearing) this bit */ -#define ASSERT_SET (1 << 3) -#define DEASSERT_SET (1 << 4) -#define STATUS_SET (1 << 5) - -/* The following are the inverse of the above and are added for consistency */ -#define ASSERT_CLEAR (0 << 3) -#define DEASSERT_CLEAR (0 << 4) -#define STATUS_CLEAR (0 << 5) - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/reset/xlnx-zynqmp-resets.h b/sys/gnu/dts/include/dt-bindings/reset/xlnx-zynqmp-resets.h deleted file mode 100644 index d44525b9f8d..00000000000 --- a/sys/gnu/dts/include/dt-bindings/reset/xlnx-zynqmp-resets.h +++ /dev/null @@ -1,130 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2018 Xilinx, Inc. - */ - -#ifndef _DT_BINDINGS_ZYNQMP_RESETS_H -#define _DT_BINDINGS_ZYNQMP_RESETS_H - -#define ZYNQMP_RESET_PCIE_CFG 0 -#define ZYNQMP_RESET_PCIE_BRIDGE 1 -#define ZYNQMP_RESET_PCIE_CTRL 2 -#define ZYNQMP_RESET_DP 3 -#define ZYNQMP_RESET_SWDT_CRF 4 -#define ZYNQMP_RESET_AFI_FM5 5 -#define ZYNQMP_RESET_AFI_FM4 6 -#define ZYNQMP_RESET_AFI_FM3 7 -#define ZYNQMP_RESET_AFI_FM2 8 -#define ZYNQMP_RESET_AFI_FM1 9 -#define ZYNQMP_RESET_AFI_FM0 10 -#define ZYNQMP_RESET_GDMA 11 -#define ZYNQMP_RESET_GPU_PP1 12 -#define ZYNQMP_RESET_GPU_PP0 13 -#define ZYNQMP_RESET_GPU 14 -#define ZYNQMP_RESET_GT 15 -#define ZYNQMP_RESET_SATA 16 -#define ZYNQMP_RESET_ACPU3_PWRON 17 -#define ZYNQMP_RESET_ACPU2_PWRON 18 -#define ZYNQMP_RESET_ACPU1_PWRON 19 -#define ZYNQMP_RESET_ACPU0_PWRON 20 -#define ZYNQMP_RESET_APU_L2 21 -#define ZYNQMP_RESET_ACPU3 22 -#define ZYNQMP_RESET_ACPU2 23 -#define ZYNQMP_RESET_ACPU1 24 -#define ZYNQMP_RESET_ACPU0 25 -#define ZYNQMP_RESET_DDR 26 -#define ZYNQMP_RESET_APM_FPD 27 -#define ZYNQMP_RESET_SOFT 28 -#define ZYNQMP_RESET_GEM0 29 -#define ZYNQMP_RESET_GEM1 30 -#define ZYNQMP_RESET_GEM2 31 -#define ZYNQMP_RESET_GEM3 32 -#define ZYNQMP_RESET_QSPI 33 -#define ZYNQMP_RESET_UART0 34 -#define ZYNQMP_RESET_UART1 35 -#define ZYNQMP_RESET_SPI0 36 -#define ZYNQMP_RESET_SPI1 37 -#define ZYNQMP_RESET_SDIO0 38 -#define ZYNQMP_RESET_SDIO1 39 -#define ZYNQMP_RESET_CAN0 40 -#define ZYNQMP_RESET_CAN1 41 -#define ZYNQMP_RESET_I2C0 42 -#define ZYNQMP_RESET_I2C1 43 -#define ZYNQMP_RESET_TTC0 44 -#define ZYNQMP_RESET_TTC1 45 -#define ZYNQMP_RESET_TTC2 46 -#define ZYNQMP_RESET_TTC3 47 -#define ZYNQMP_RESET_SWDT_CRL 48 -#define ZYNQMP_RESET_NAND 49 -#define ZYNQMP_RESET_ADMA 50 -#define ZYNQMP_RESET_GPIO 51 -#define ZYNQMP_RESET_IOU_CC 52 -#define ZYNQMP_RESET_TIMESTAMP 53 -#define ZYNQMP_RESET_RPU_R50 54 -#define ZYNQMP_RESET_RPU_R51 55 -#define ZYNQMP_RESET_RPU_AMBA 56 -#define ZYNQMP_RESET_OCM 57 -#define ZYNQMP_RESET_RPU_PGE 58 -#define ZYNQMP_RESET_USB0_CORERESET 59 -#define ZYNQMP_RESET_USB1_CORERESET 60 -#define ZYNQMP_RESET_USB0_HIBERRESET 61 -#define ZYNQMP_RESET_USB1_HIBERRESET 62 -#define ZYNQMP_RESET_USB0_APB 63 -#define ZYNQMP_RESET_USB1_APB 64 -#define ZYNQMP_RESET_IPI 65 -#define ZYNQMP_RESET_APM_LPD 66 -#define ZYNQMP_RESET_RTC 67 -#define ZYNQMP_RESET_SYSMON 68 -#define ZYNQMP_RESET_AFI_FM6 69 -#define ZYNQMP_RESET_LPD_SWDT 70 -#define ZYNQMP_RESET_FPD 71 -#define ZYNQMP_RESET_RPU_DBG1 72 -#define ZYNQMP_RESET_RPU_DBG0 73 -#define ZYNQMP_RESET_DBG_LPD 74 -#define ZYNQMP_RESET_DBG_FPD 75 -#define ZYNQMP_RESET_APLL 76 -#define ZYNQMP_RESET_DPLL 77 -#define ZYNQMP_RESET_VPLL 78 -#define ZYNQMP_RESET_IOPLL 79 -#define ZYNQMP_RESET_RPLL 80 -#define ZYNQMP_RESET_GPO3_PL_0 81 -#define ZYNQMP_RESET_GPO3_PL_1 82 -#define ZYNQMP_RESET_GPO3_PL_2 83 -#define ZYNQMP_RESET_GPO3_PL_3 84 -#define ZYNQMP_RESET_GPO3_PL_4 85 -#define ZYNQMP_RESET_GPO3_PL_5 86 -#define ZYNQMP_RESET_GPO3_PL_6 87 -#define ZYNQMP_RESET_GPO3_PL_7 88 -#define ZYNQMP_RESET_GPO3_PL_8 89 -#define ZYNQMP_RESET_GPO3_PL_9 90 -#define ZYNQMP_RESET_GPO3_PL_10 91 -#define ZYNQMP_RESET_GPO3_PL_11 92 -#define ZYNQMP_RESET_GPO3_PL_12 93 -#define ZYNQMP_RESET_GPO3_PL_13 94 -#define ZYNQMP_RESET_GPO3_PL_14 95 -#define ZYNQMP_RESET_GPO3_PL_15 96 -#define ZYNQMP_RESET_GPO3_PL_16 97 -#define ZYNQMP_RESET_GPO3_PL_17 98 -#define ZYNQMP_RESET_GPO3_PL_18 99 -#define ZYNQMP_RESET_GPO3_PL_19 100 -#define ZYNQMP_RESET_GPO3_PL_20 101 -#define ZYNQMP_RESET_GPO3_PL_21 102 -#define ZYNQMP_RESET_GPO3_PL_22 103 -#define ZYNQMP_RESET_GPO3_PL_23 104 -#define ZYNQMP_RESET_GPO3_PL_24 105 -#define ZYNQMP_RESET_GPO3_PL_25 106 -#define ZYNQMP_RESET_GPO3_PL_26 107 -#define ZYNQMP_RESET_GPO3_PL_27 108 -#define ZYNQMP_RESET_GPO3_PL_28 109 -#define ZYNQMP_RESET_GPO3_PL_29 110 -#define ZYNQMP_RESET_GPO3_PL_30 111 -#define ZYNQMP_RESET_GPO3_PL_31 112 -#define ZYNQMP_RESET_RPU_LS 113 -#define ZYNQMP_RESET_PS_ONLY 114 -#define ZYNQMP_RESET_PL 115 -#define ZYNQMP_RESET_PS_PL0 116 -#define ZYNQMP_RESET_PS_PL1 117 -#define ZYNQMP_RESET_PS_PL2 118 -#define ZYNQMP_RESET_PS_PL3 119 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/soc/bcm2835-pm.h b/sys/gnu/dts/include/dt-bindings/soc/bcm2835-pm.h deleted file mode 100644 index 153d75b8d99..00000000000 --- a/sys/gnu/dts/include/dt-bindings/soc/bcm2835-pm.h +++ /dev/null @@ -1,28 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ - -#ifndef _DT_BINDINGS_ARM_BCM2835_PM_H -#define _DT_BINDINGS_ARM_BCM2835_PM_H - -#define BCM2835_POWER_DOMAIN_GRAFX 0 -#define BCM2835_POWER_DOMAIN_GRAFX_V3D 1 -#define BCM2835_POWER_DOMAIN_IMAGE 2 -#define BCM2835_POWER_DOMAIN_IMAGE_PERI 3 -#define BCM2835_POWER_DOMAIN_IMAGE_ISP 4 -#define BCM2835_POWER_DOMAIN_IMAGE_H264 5 -#define BCM2835_POWER_DOMAIN_USB 6 -#define BCM2835_POWER_DOMAIN_DSI0 7 -#define BCM2835_POWER_DOMAIN_DSI1 8 -#define BCM2835_POWER_DOMAIN_CAM0 9 -#define BCM2835_POWER_DOMAIN_CAM1 10 -#define BCM2835_POWER_DOMAIN_CCP2TX 11 -#define BCM2835_POWER_DOMAIN_HDMI 12 - -#define BCM2835_POWER_DOMAIN_COUNT 13 - -#define BCM2835_RESET_V3D 0 -#define BCM2835_RESET_ISP 1 -#define BCM2835_RESET_H264 2 - -#define BCM2835_RESET_COUNT 3 - -#endif /* _DT_BINDINGS_ARM_BCM2835_PM_H */ diff --git a/sys/gnu/dts/include/dt-bindings/soc/qcom,apr.h b/sys/gnu/dts/include/dt-bindings/soc/qcom,apr.h deleted file mode 100644 index 006362400c0..00000000000 --- a/sys/gnu/dts/include/dt-bindings/soc/qcom,apr.h +++ /dev/null @@ -1,28 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __DT_BINDINGS_QCOM_APR_H -#define __DT_BINDINGS_QCOM_APR_H - -/* Domain IDs */ -#define APR_DOMAIN_SIM 0x1 -#define APR_DOMAIN_PC 0x2 -#define APR_DOMAIN_MODEM 0x3 -#define APR_DOMAIN_ADSP 0x4 -#define APR_DOMAIN_APPS 0x5 -#define APR_DOMAIN_MAX 0x6 - -/* ADSP service IDs */ -#define APR_SVC_ADSP_CORE 0x3 -#define APR_SVC_AFE 0x4 -#define APR_SVC_VSM 0x5 -#define APR_SVC_VPM 0x6 -#define APR_SVC_ASM 0x7 -#define APR_SVC_ADM 0x8 -#define APR_SVC_ADSP_MVM 0x09 -#define APR_SVC_ADSP_CVS 0x0A -#define APR_SVC_ADSP_CVP 0x0B -#define APR_SVC_USM 0x0C -#define APR_SVC_LSM 0x0D -#define APR_SVC_VIDC 0x16 -#define APR_SVC_MAX 0x17 - -#endif /* __DT_BINDINGS_QCOM_APR_H */ diff --git a/sys/gnu/dts/include/dt-bindings/soc/qcom,gsbi.h b/sys/gnu/dts/include/dt-bindings/soc/qcom,gsbi.h deleted file mode 100644 index c00ab8c5f3b..00000000000 --- a/sys/gnu/dts/include/dt-bindings/soc/qcom,gsbi.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* Copyright (c) 2013, The Linux Foundation. All rights reserved. - */ -#ifndef __DT_BINDINGS_QCOM_GSBI_H -#define __DT_BINDINGS_QCOM_GSBI_H - -#define GSBI_PROT_IDLE 0 -#define GSBI_PROT_I2C_UIM 1 -#define GSBI_PROT_I2C 2 -#define GSBI_PROT_SPI 3 -#define GSBI_PROT_UART_W_FC 4 -#define GSBI_PROT_UIM 5 -#define GSBI_PROT_I2C_UART 6 - -#define GSBI_CRCI_QUP 0 -#define GSBI_CRCI_UART 1 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/soc/qcom,rpmh-rsc.h b/sys/gnu/dts/include/dt-bindings/soc/qcom,rpmh-rsc.h deleted file mode 100644 index 868f998ea99..00000000000 --- a/sys/gnu/dts/include/dt-bindings/soc/qcom,rpmh-rsc.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. - */ - -#ifndef __DT_QCOM_RPMH_RSC_H__ -#define __DT_QCOM_RPMH_RSC_H__ - -#define SLEEP_TCS 0 -#define WAKE_TCS 1 -#define ACTIVE_TCS 2 -#define CONTROL_TCS 3 - -#endif /* __DT_QCOM_RPMH_RSC_H__ */ diff --git a/sys/gnu/dts/include/dt-bindings/soc/rockchip,boot-mode.h b/sys/gnu/dts/include/dt-bindings/soc/rockchip,boot-mode.h deleted file mode 100644 index 4b0914c0989..00000000000 --- a/sys/gnu/dts/include/dt-bindings/soc/rockchip,boot-mode.h +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __ROCKCHIP_BOOT_MODE_H -#define __ROCKCHIP_BOOT_MODE_H - -/*high 24 bits is tag, low 8 bits is type*/ -#define REBOOT_FLAG 0x5242C300 -/* normal boot */ -#define BOOT_NORMAL (REBOOT_FLAG + 0) -/* enter bootloader rockusb mode */ -#define BOOT_BL_DOWNLOAD (REBOOT_FLAG + 1) -/* enter recovery */ -#define BOOT_RECOVERY (REBOOT_FLAG + 3) - /* enter fastboot mode */ -#define BOOT_FASTBOOT (REBOOT_FLAG + 9) - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/soc/ti,sci_pm_domain.h b/sys/gnu/dts/include/dt-bindings/soc/ti,sci_pm_domain.h deleted file mode 100644 index 8f2a7360b65..00000000000 --- a/sys/gnu/dts/include/dt-bindings/soc/ti,sci_pm_domain.h +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ - -#ifndef __DT_BINDINGS_TI_SCI_PM_DOMAIN_H -#define __DT_BINDINGS_TI_SCI_PM_DOMAIN_H - -#define TI_SCI_PD_EXCLUSIVE 1 -#define TI_SCI_PD_SHARED 0 - -#endif /* __DT_BINDINGS_TI_SCI_PM_DOMAIN_H */ diff --git a/sys/gnu/dts/include/dt-bindings/soc/zte,pm_domains.h b/sys/gnu/dts/include/dt-bindings/soc/zte,pm_domains.h deleted file mode 100644 index df044705a5e..00000000000 --- a/sys/gnu/dts/include/dt-bindings/soc/zte,pm_domains.h +++ /dev/null @@ -1,24 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) 2017 Linaro Ltd. - * - * Author: Baoyou Xie - */ - -#ifndef _DT_BINDINGS_SOC_ZTE_PM_DOMAINS_H -#define _DT_BINDINGS_SOC_ZTE_PM_DOMAINS_H - -#define DM_ZX296718_SAPPU 0 -#define DM_ZX296718_VDE 1 /* g1v6 */ -#define DM_ZX296718_VCE 2 /* h1v6 */ -#define DM_ZX296718_HDE 3 /* g2v2 */ -#define DM_ZX296718_VIU 4 -#define DM_ZX296718_USB20 5 -#define DM_ZX296718_USB21 6 -#define DM_ZX296718_USB30 7 -#define DM_ZX296718_HSIC 8 -#define DM_ZX296718_GMAC 9 -#define DM_ZX296718_TS 10 -#define DM_ZX296718_VOU 11 - -#endif /* _DT_BINDINGS_SOC_ZTE_PM_DOMAINS_H */ diff --git a/sys/gnu/dts/include/dt-bindings/sound/apq8016-lpass.h b/sys/gnu/dts/include/dt-bindings/sound/apq8016-lpass.h deleted file mode 100644 index 3c3e16c0aad..00000000000 --- a/sys/gnu/dts/include/dt-bindings/sound/apq8016-lpass.h +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __DT_APQ8016_LPASS_H -#define __DT_APQ8016_LPASS_H - -#define MI2S_PRIMARY 0 -#define MI2S_SECONDARY 1 -#define MI2S_TERTIARY 2 -#define MI2S_QUATERNARY 3 - -#endif /* __DT_APQ8016_LPASS_H */ diff --git a/sys/gnu/dts/include/dt-bindings/sound/audio-jack-events.h b/sys/gnu/dts/include/dt-bindings/sound/audio-jack-events.h deleted file mode 100644 index 1b29b295126..00000000000 --- a/sys/gnu/dts/include/dt-bindings/sound/audio-jack-events.h +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __AUDIO_JACK_EVENTS_H -#define __AUDIO_JACK_EVENTS_H - -#define JACK_HEADPHONE 1 -#define JACK_MICROPHONE 2 -#define JACK_LINEOUT 3 -#define JACK_LINEIN 4 - -#endif /* __AUDIO_JACK_EVENTS_H */ diff --git a/sys/gnu/dts/include/dt-bindings/sound/cs35l32.h b/sys/gnu/dts/include/dt-bindings/sound/cs35l32.h deleted file mode 100644 index 7549d5019e8..00000000000 --- a/sys/gnu/dts/include/dt-bindings/sound/cs35l32.h +++ /dev/null @@ -1,27 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __DT_CS35L32_H -#define __DT_CS35L32_H - -#define CS35L32_BOOST_MGR_AUTO 0 -#define CS35L32_BOOST_MGR_AUTO_AUDIO 1 -#define CS35L32_BOOST_MGR_BYPASS 2 -#define CS35L32_BOOST_MGR_FIXED 3 - -#define CS35L32_DATA_CFG_LR_VP 0 -#define CS35L32_DATA_CFG_LR_STAT 1 -#define CS35L32_DATA_CFG_LR 2 -#define CS35L32_DATA_CFG_LR_VPSTAT 3 - -#define CS35L32_BATT_THRESH_3_1V 0 -#define CS35L32_BATT_THRESH_3_2V 1 -#define CS35L32_BATT_THRESH_3_3V 2 -#define CS35L32_BATT_THRESH_3_4V 3 - -#define CS35L32_BATT_RECOV_3_1V 0 -#define CS35L32_BATT_RECOV_3_2V 1 -#define CS35L32_BATT_RECOV_3_3V 2 -#define CS35L32_BATT_RECOV_3_4V 3 -#define CS35L32_BATT_RECOV_3_5V 4 -#define CS35L32_BATT_RECOV_3_6V 5 - -#endif /* __DT_CS35L32_H */ diff --git a/sys/gnu/dts/include/dt-bindings/sound/cs42l42.h b/sys/gnu/dts/include/dt-bindings/sound/cs42l42.h deleted file mode 100644 index f25d83c6188..00000000000 --- a/sys/gnu/dts/include/dt-bindings/sound/cs42l42.h +++ /dev/null @@ -1,69 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * cs42l42.h -- CS42L42 ALSA SoC audio driver DT bindings header - * - * Copyright 2016 Cirrus Logic, Inc. - * - * Author: James Schulman - * Author: Brian Austin - * Author: Michael White - */ - -#ifndef __DT_CS42L42_H -#define __DT_CS42L42_H - -/* HPOUT Load Capacity */ -#define CS42L42_HPOUT_LOAD_1NF 0 -#define CS42L42_HPOUT_LOAD_10NF 1 - -/* HPOUT Clamp to GND Override */ -#define CS42L42_HPOUT_CLAMP_EN 0 -#define CS42L42_HPOUT_CLAMP_DIS 1 - -/* Tip Sense Inversion */ -#define CS42L42_TS_INV_DIS 0 -#define CS42L42_TS_INV_EN 1 - -/* Tip Sense Debounce */ -#define CS42L42_TS_DBNCE_0 0 -#define CS42L42_TS_DBNCE_125 1 -#define CS42L42_TS_DBNCE_250 2 -#define CS42L42_TS_DBNCE_500 3 -#define CS42L42_TS_DBNCE_750 4 -#define CS42L42_TS_DBNCE_1000 5 -#define CS42L42_TS_DBNCE_1250 6 -#define CS42L42_TS_DBNCE_1500 7 - -/* Button Press Software Debounce Times */ -#define CS42L42_BTN_DET_INIT_DBNCE_MIN 0 -#define CS42L42_BTN_DET_INIT_DBNCE_DEFAULT 100 -#define CS42L42_BTN_DET_INIT_DBNCE_MAX 200 - -#define CS42L42_BTN_DET_EVENT_DBNCE_MIN 0 -#define CS42L42_BTN_DET_EVENT_DBNCE_DEFAULT 10 -#define CS42L42_BTN_DET_EVENT_DBNCE_MAX 20 - -/* Button Detect Level Sensitivities */ -#define CS42L42_NUM_BIASES 4 - -#define CS42L42_HS_DET_LEVEL_15 0x0F -#define CS42L42_HS_DET_LEVEL_8 0x08 -#define CS42L42_HS_DET_LEVEL_4 0x04 -#define CS42L42_HS_DET_LEVEL_1 0x01 - -#define CS42L42_HS_DET_LEVEL_MIN 0 -#define CS42L42_HS_DET_LEVEL_MAX 0x3F - -/* HS Bias Ramp Rate */ - -#define CS42L42_HSBIAS_RAMP_FAST_RISE_SLOW_FALL 0 -#define CS42L42_HSBIAS_RAMP_FAST 1 -#define CS42L42_HSBIAS_RAMP_SLOW 2 -#define CS42L42_HSBIAS_RAMP_SLOWEST 3 - -#define CS42L42_HSBIAS_RAMP_TIME0 10 -#define CS42L42_HSBIAS_RAMP_TIME1 40 -#define CS42L42_HSBIAS_RAMP_TIME2 90 -#define CS42L42_HSBIAS_RAMP_TIME3 170 - -#endif /* __DT_CS42L42_H */ diff --git a/sys/gnu/dts/include/dt-bindings/sound/fsl-imx-audmux.h b/sys/gnu/dts/include/dt-bindings/sound/fsl-imx-audmux.h deleted file mode 100644 index 15f138bebe1..00000000000 --- a/sys/gnu/dts/include/dt-bindings/sound/fsl-imx-audmux.h +++ /dev/null @@ -1,64 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __DT_FSL_IMX_AUDMUX_H -#define __DT_FSL_IMX_AUDMUX_H - -#define MX27_AUDMUX_HPCR1_SSI0 0 -#define MX27_AUDMUX_HPCR2_SSI1 1 -#define MX27_AUDMUX_HPCR3_SSI_PINS_4 2 -#define MX27_AUDMUX_PPCR1_SSI_PINS_1 3 -#define MX27_AUDMUX_PPCR2_SSI_PINS_2 4 -#define MX27_AUDMUX_PPCR3_SSI_PINS_3 5 - -#define MX31_AUDMUX_PORT1_SSI0 0 -#define MX31_AUDMUX_PORT2_SSI1 1 -#define MX31_AUDMUX_PORT3_SSI_PINS_3 2 -#define MX31_AUDMUX_PORT4_SSI_PINS_4 3 -#define MX31_AUDMUX_PORT5_SSI_PINS_5 4 -#define MX31_AUDMUX_PORT6_SSI_PINS_6 5 -#define MX31_AUDMUX_PORT7_SSI_PINS_7 6 - -#define MX51_AUDMUX_PORT1_SSI0 0 -#define MX51_AUDMUX_PORT2_SSI1 1 -#define MX51_AUDMUX_PORT3 2 -#define MX51_AUDMUX_PORT4 3 -#define MX51_AUDMUX_PORT5 4 -#define MX51_AUDMUX_PORT6 5 -#define MX51_AUDMUX_PORT7 6 - -/* - * TFCSEL/RFCSEL (i.MX27) or TFSEL/TCSEL/RFSEL/RCSEL (i.MX31/51/53/6Q) - * can be sourced from Rx/Tx. - */ -#define IMX_AUDMUX_RXFS 0x8 -#define IMX_AUDMUX_RXCLK 0x8 - -/* Register definitions for the i.MX21/27 Digital Audio Multiplexer */ -#define IMX_AUDMUX_V1_PCR_INMMASK(x) ((x) & 0xff) -#define IMX_AUDMUX_V1_PCR_INMEN (1 << 8) -#define IMX_AUDMUX_V1_PCR_TXRXEN (1 << 10) -#define IMX_AUDMUX_V1_PCR_SYN (1 << 12) -#define IMX_AUDMUX_V1_PCR_RXDSEL(x) (((x) & 0x7) << 13) -#define IMX_AUDMUX_V1_PCR_RFCSEL(x) (((x) & 0xf) << 20) -#define IMX_AUDMUX_V1_PCR_RCLKDIR (1 << 24) -#define IMX_AUDMUX_V1_PCR_RFSDIR (1 << 25) -#define IMX_AUDMUX_V1_PCR_TFCSEL(x) (((x) & 0xf) << 26) -#define IMX_AUDMUX_V1_PCR_TCLKDIR (1 << 30) -#define IMX_AUDMUX_V1_PCR_TFSDIR (1 << 31) - -/* Register definitions for the i.MX25/31/35/51 Digital Audio Multiplexer */ -#define IMX_AUDMUX_V2_PTCR_TFSDIR (1 << 31) -#define IMX_AUDMUX_V2_PTCR_TFSEL(x) (((x) & 0xf) << 27) -#define IMX_AUDMUX_V2_PTCR_TCLKDIR (1 << 26) -#define IMX_AUDMUX_V2_PTCR_TCSEL(x) (((x) & 0xf) << 22) -#define IMX_AUDMUX_V2_PTCR_RFSDIR (1 << 21) -#define IMX_AUDMUX_V2_PTCR_RFSEL(x) (((x) & 0xf) << 17) -#define IMX_AUDMUX_V2_PTCR_RCLKDIR (1 << 16) -#define IMX_AUDMUX_V2_PTCR_RCSEL(x) (((x) & 0xf) << 12) -#define IMX_AUDMUX_V2_PTCR_SYN (1 << 11) - -#define IMX_AUDMUX_V2_PDCR_RXDSEL(x) (((x) & 0x7) << 13) -#define IMX_AUDMUX_V2_PDCR_TXRXEN (1 << 12) -#define IMX_AUDMUX_V2_PDCR_MODE(x) (((x) & 0x3) << 8) -#define IMX_AUDMUX_V2_PDCR_INMMASK(x) ((x) & 0xff) - -#endif /* __DT_FSL_IMX_AUDMUX_H */ diff --git a/sys/gnu/dts/include/dt-bindings/sound/madera.h b/sys/gnu/dts/include/dt-bindings/sound/madera.h deleted file mode 100644 index d0096d5eb0d..00000000000 --- a/sys/gnu/dts/include/dt-bindings/sound/madera.h +++ /dev/null @@ -1,25 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Device Tree defines for Madera codecs - * - * Copyright (C) 2016-2017 Cirrus Logic, Inc. and - * Cirrus Logic International Semiconductor Ltd. - */ - -#ifndef DT_BINDINGS_SOUND_MADERA_H -#define DT_BINDINGS_SOUND_MADERA_H - -#define MADERA_INMODE_DIFF 0 -#define MADERA_INMODE_SE 1 -#define MADERA_INMODE_DMIC 2 - -#define MADERA_DMIC_REF_MICVDD 0 -#define MADERA_DMIC_REF_MICBIAS1 1 -#define MADERA_DMIC_REF_MICBIAS2 2 -#define MADERA_DMIC_REF_MICBIAS3 3 - -#define CS47L35_DMIC_REF_MICBIAS1B 1 -#define CS47L35_DMIC_REF_MICBIAS2A 2 -#define CS47L35_DMIC_REF_MICBIAS2B 3 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/sound/meson-g12a-tohdmitx.h b/sys/gnu/dts/include/dt-bindings/sound/meson-g12a-tohdmitx.h deleted file mode 100644 index c5e1f48d30d..00000000000 --- a/sys/gnu/dts/include/dt-bindings/sound/meson-g12a-tohdmitx.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __DT_MESON_G12A_TOHDMITX_H -#define __DT_MESON_G12A_TOHDMITX_H - -#define TOHDMITX_I2S_IN_A 0 -#define TOHDMITX_I2S_IN_B 1 -#define TOHDMITX_I2S_IN_C 2 -#define TOHDMITX_I2S_OUT 3 -#define TOHDMITX_SPDIF_IN_A 4 -#define TOHDMITX_SPDIF_IN_B 5 -#define TOHDMITX_SPDIF_OUT 6 - -#endif /* __DT_MESON_G12A_TOHDMITX_H */ diff --git a/sys/gnu/dts/include/dt-bindings/sound/qcom,q6afe.h b/sys/gnu/dts/include/dt-bindings/sound/qcom,q6afe.h deleted file mode 100644 index 1df06f8ad5c..00000000000 --- a/sys/gnu/dts/include/dt-bindings/sound/qcom,q6afe.h +++ /dev/null @@ -1,112 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __DT_BINDINGS_Q6_AFE_H__ -#define __DT_BINDINGS_Q6_AFE_H__ - -/* Audio Front End (AFE) virtual ports IDs */ -#define HDMI_RX 1 -#define SLIMBUS_0_RX 2 -#define SLIMBUS_0_TX 3 -#define SLIMBUS_1_RX 4 -#define SLIMBUS_1_TX 5 -#define SLIMBUS_2_RX 6 -#define SLIMBUS_2_TX 7 -#define SLIMBUS_3_RX 8 -#define SLIMBUS_3_TX 9 -#define SLIMBUS_4_RX 10 -#define SLIMBUS_4_TX 11 -#define SLIMBUS_5_RX 12 -#define SLIMBUS_5_TX 13 -#define SLIMBUS_6_RX 14 -#define SLIMBUS_6_TX 15 -#define PRIMARY_MI2S_RX 16 -#define PRIMARY_MI2S_TX 17 -#define SECONDARY_MI2S_RX 18 -#define SECONDARY_MI2S_TX 19 -#define TERTIARY_MI2S_RX 20 -#define TERTIARY_MI2S_TX 21 -#define QUATERNARY_MI2S_RX 22 -#define QUATERNARY_MI2S_TX 23 -#define PRIMARY_TDM_RX_0 24 -#define PRIMARY_TDM_TX_0 25 -#define PRIMARY_TDM_RX_1 26 -#define PRIMARY_TDM_TX_1 27 -#define PRIMARY_TDM_RX_2 28 -#define PRIMARY_TDM_TX_2 29 -#define PRIMARY_TDM_RX_3 30 -#define PRIMARY_TDM_TX_3 31 -#define PRIMARY_TDM_RX_4 32 -#define PRIMARY_TDM_TX_4 33 -#define PRIMARY_TDM_RX_5 34 -#define PRIMARY_TDM_TX_5 35 -#define PRIMARY_TDM_RX_6 36 -#define PRIMARY_TDM_TX_6 37 -#define PRIMARY_TDM_RX_7 38 -#define PRIMARY_TDM_TX_7 39 -#define SECONDARY_TDM_RX_0 40 -#define SECONDARY_TDM_TX_0 41 -#define SECONDARY_TDM_RX_1 42 -#define SECONDARY_TDM_TX_1 43 -#define SECONDARY_TDM_RX_2 44 -#define SECONDARY_TDM_TX_2 45 -#define SECONDARY_TDM_RX_3 46 -#define SECONDARY_TDM_TX_3 47 -#define SECONDARY_TDM_RX_4 48 -#define SECONDARY_TDM_TX_4 49 -#define SECONDARY_TDM_RX_5 50 -#define SECONDARY_TDM_TX_5 51 -#define SECONDARY_TDM_RX_6 52 -#define SECONDARY_TDM_TX_6 53 -#define SECONDARY_TDM_RX_7 54 -#define SECONDARY_TDM_TX_7 55 -#define TERTIARY_TDM_RX_0 56 -#define TERTIARY_TDM_TX_0 57 -#define TERTIARY_TDM_RX_1 58 -#define TERTIARY_TDM_TX_1 59 -#define TERTIARY_TDM_RX_2 60 -#define TERTIARY_TDM_TX_2 61 -#define TERTIARY_TDM_RX_3 62 -#define TERTIARY_TDM_TX_3 63 -#define TERTIARY_TDM_RX_4 64 -#define TERTIARY_TDM_TX_4 65 -#define TERTIARY_TDM_RX_5 66 -#define TERTIARY_TDM_TX_5 67 -#define TERTIARY_TDM_RX_6 68 -#define TERTIARY_TDM_TX_6 69 -#define TERTIARY_TDM_RX_7 70 -#define TERTIARY_TDM_TX_7 71 -#define QUATERNARY_TDM_RX_0 72 -#define QUATERNARY_TDM_TX_0 73 -#define QUATERNARY_TDM_RX_1 74 -#define QUATERNARY_TDM_TX_1 75 -#define QUATERNARY_TDM_RX_2 76 -#define QUATERNARY_TDM_TX_2 77 -#define QUATERNARY_TDM_RX_3 78 -#define QUATERNARY_TDM_TX_3 79 -#define QUATERNARY_TDM_RX_4 80 -#define QUATERNARY_TDM_TX_4 81 -#define QUATERNARY_TDM_RX_5 82 -#define QUATERNARY_TDM_TX_5 83 -#define QUATERNARY_TDM_RX_6 84 -#define QUATERNARY_TDM_TX_6 85 -#define QUATERNARY_TDM_RX_7 86 -#define QUATERNARY_TDM_TX_7 87 -#define QUINARY_TDM_RX_0 88 -#define QUINARY_TDM_TX_0 89 -#define QUINARY_TDM_RX_1 90 -#define QUINARY_TDM_TX_1 91 -#define QUINARY_TDM_RX_2 92 -#define QUINARY_TDM_TX_2 93 -#define QUINARY_TDM_RX_3 94 -#define QUINARY_TDM_TX_3 95 -#define QUINARY_TDM_RX_4 96 -#define QUINARY_TDM_TX_4 97 -#define QUINARY_TDM_RX_5 98 -#define QUINARY_TDM_TX_5 99 -#define QUINARY_TDM_RX_6 100 -#define QUINARY_TDM_TX_6 101 -#define QUINARY_TDM_RX_7 102 -#define QUINARY_TDM_TX_7 103 -#define DISPLAY_PORT_RX 104 - -#endif /* __DT_BINDINGS_Q6_AFE_H__ */ - diff --git a/sys/gnu/dts/include/dt-bindings/sound/qcom,q6asm.h b/sys/gnu/dts/include/dt-bindings/sound/qcom,q6asm.h deleted file mode 100644 index 1eb77d87c2e..00000000000 --- a/sys/gnu/dts/include/dt-bindings/sound/qcom,q6asm.h +++ /dev/null @@ -1,22 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __DT_BINDINGS_Q6_ASM_H__ -#define __DT_BINDINGS_Q6_ASM_H__ - -#define MSM_FRONTEND_DAI_MULTIMEDIA1 0 -#define MSM_FRONTEND_DAI_MULTIMEDIA2 1 -#define MSM_FRONTEND_DAI_MULTIMEDIA3 2 -#define MSM_FRONTEND_DAI_MULTIMEDIA4 3 -#define MSM_FRONTEND_DAI_MULTIMEDIA5 4 -#define MSM_FRONTEND_DAI_MULTIMEDIA6 5 -#define MSM_FRONTEND_DAI_MULTIMEDIA7 6 -#define MSM_FRONTEND_DAI_MULTIMEDIA8 7 -#define MSM_FRONTEND_DAI_MULTIMEDIA9 8 -#define MSM_FRONTEND_DAI_MULTIMEDIA10 9 -#define MSM_FRONTEND_DAI_MULTIMEDIA11 10 -#define MSM_FRONTEND_DAI_MULTIMEDIA12 11 -#define MSM_FRONTEND_DAI_MULTIMEDIA13 12 -#define MSM_FRONTEND_DAI_MULTIMEDIA14 13 -#define MSM_FRONTEND_DAI_MULTIMEDIA15 14 -#define MSM_FRONTEND_DAI_MULTIMEDIA16 15 - -#endif /* __DT_BINDINGS_Q6_ASM_H__ */ diff --git a/sys/gnu/dts/include/dt-bindings/sound/rt5640.h b/sys/gnu/dts/include/dt-bindings/sound/rt5640.h deleted file mode 100644 index 154c9b4414f..00000000000 --- a/sys/gnu/dts/include/dt-bindings/sound/rt5640.h +++ /dev/null @@ -1,25 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __DT_RT5640_H -#define __DT_RT5640_H - -#define RT5640_DMIC1_DATA_PIN_NONE 0 -#define RT5640_DMIC1_DATA_PIN_IN1P 1 -#define RT5640_DMIC1_DATA_PIN_GPIO3 2 - -#define RT5640_DMIC2_DATA_PIN_NONE 0 -#define RT5640_DMIC2_DATA_PIN_IN1N 1 -#define RT5640_DMIC2_DATA_PIN_GPIO4 2 - -#define RT5640_JD_SRC_GPIO1 1 -#define RT5640_JD_SRC_JD1_IN4P 2 -#define RT5640_JD_SRC_JD2_IN4N 3 -#define RT5640_JD_SRC_GPIO2 4 -#define RT5640_JD_SRC_GPIO3 5 -#define RT5640_JD_SRC_GPIO4 6 - -#define RT5640_OVCD_SF_0P5 0 -#define RT5640_OVCD_SF_0P75 1 -#define RT5640_OVCD_SF_1P0 2 -#define RT5640_OVCD_SF_1P5 3 - -#endif /* __DT_RT5640_H */ diff --git a/sys/gnu/dts/include/dt-bindings/sound/rt5651.h b/sys/gnu/dts/include/dt-bindings/sound/rt5651.h deleted file mode 100644 index 2f2dac91516..00000000000 --- a/sys/gnu/dts/include/dt-bindings/sound/rt5651.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __DT_RT5651_H -#define __DT_RT5651_H - -#define RT5651_JD_NULL 0 -#define RT5651_JD1_1 1 -#define RT5651_JD1_2 2 -#define RT5651_JD2 3 - -#define RT5651_OVCD_SF_0P5 0 -#define RT5651_OVCD_SF_0P75 1 -#define RT5651_OVCD_SF_1P0 2 -#define RT5651_OVCD_SF_1P5 3 - -#endif /* __DT_RT5651_H */ diff --git a/sys/gnu/dts/include/dt-bindings/sound/samsung-i2s.h b/sys/gnu/dts/include/dt-bindings/sound/samsung-i2s.h deleted file mode 100644 index 250de0d6c73..00000000000 --- a/sys/gnu/dts/include/dt-bindings/sound/samsung-i2s.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _DT_BINDINGS_SAMSUNG_I2S_H -#define _DT_BINDINGS_SAMSUNG_I2S_H - -#define CLK_I2S_CDCLK 0 /* the CDCLK (CODECLKO) gate clock */ - -#define CLK_I2S_RCLK_SRC 1 /* the RCLKSRC mux clock (corresponding to - * RCLKSRC bit in IISMOD register) - */ - -#define CLK_I2S_RCLK_PSR 2 /* the RCLK prescaler divider clock - * (corresponding to the IISPSR register) - */ - -#endif /* _DT_BINDINGS_SAMSUNG_I2S_H */ diff --git a/sys/gnu/dts/include/dt-bindings/sound/tas2552.h b/sys/gnu/dts/include/dt-bindings/sound/tas2552.h deleted file mode 100644 index 0daeb838583..00000000000 --- a/sys/gnu/dts/include/dt-bindings/sound/tas2552.h +++ /dev/null @@ -1,19 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __DT_TAS2552_H -#define __DT_TAS2552_H - -#define TAS2552_PLL_CLKIN (0) -#define TAS2552_PDM_CLK (1) -#define TAS2552_CLK_TARGET_MASK (1) - -#define TAS2552_PLL_CLKIN_MCLK ((0 << 1) | TAS2552_PLL_CLKIN) -#define TAS2552_PLL_CLKIN_BCLK ((1 << 1) | TAS2552_PLL_CLKIN) -#define TAS2552_PLL_CLKIN_IVCLKIN ((2 << 1) | TAS2552_PLL_CLKIN) -#define TAS2552_PLL_CLKIN_1_8_FIXED ((3 << 1) | TAS2552_PLL_CLKIN) - -#define TAS2552_PDM_CLK_PLL ((0 << 1) | TAS2552_PDM_CLK) -#define TAS2552_PDM_CLK_IVCLKIN ((1 << 1) | TAS2552_PDM_CLK) -#define TAS2552_PDM_CLK_BCLK ((2 << 1) | TAS2552_PDM_CLK) -#define TAS2552_PDM_CLK_MCLK ((3 << 1) | TAS2552_PDM_CLK) - -#endif /* __DT_TAS2552_H */ diff --git a/sys/gnu/dts/include/dt-bindings/sound/tlv320aic31xx-micbias.h b/sys/gnu/dts/include/dt-bindings/sound/tlv320aic31xx-micbias.h deleted file mode 100644 index c6895a18a45..00000000000 --- a/sys/gnu/dts/include/dt-bindings/sound/tlv320aic31xx-micbias.h +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __DT_TLV320AIC31XX_MICBIAS_H -#define __DT_TLV320AIC31XX_MICBIAS_H - -#define MICBIAS_2_0V 1 -#define MICBIAS_2_5V 2 -#define MICBIAS_AVDDV 3 - -#endif /* __DT_TLV320AIC31XX_MICBIAS_H */ diff --git a/sys/gnu/dts/include/dt-bindings/spmi/spmi.h b/sys/gnu/dts/include/dt-bindings/spmi/spmi.h deleted file mode 100644 index ad4a43481de..00000000000 --- a/sys/gnu/dts/include/dt-bindings/spmi/spmi.h +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* Copyright (c) 2013, The Linux Foundation. All rights reserved. - */ -#ifndef __DT_BINDINGS_SPMI_H -#define __DT_BINDINGS_SPMI_H - -#define SPMI_USID 0 -#define SPMI_GSID 1 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/thermal/lm90.h b/sys/gnu/dts/include/dt-bindings/thermal/lm90.h deleted file mode 100644 index eed91a16c32..00000000000 --- a/sys/gnu/dts/include/dt-bindings/thermal/lm90.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides constants for the LM90 thermal bindings. - */ - -#ifndef _DT_BINDINGS_THERMAL_LM90_H_ -#define _DT_BINDINGS_THERMAL_LM90_H_ - -#define LM90_LOCAL_TEMPERATURE 0 -#define LM90_REMOTE_TEMPERATURE 1 -#define LM90_REMOTE2_TEMPERATURE 2 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/thermal/tegra124-soctherm.h b/sys/gnu/dts/include/dt-bindings/thermal/tegra124-soctherm.h deleted file mode 100644 index 444c7bdde14..00000000000 --- a/sys/gnu/dts/include/dt-bindings/thermal/tegra124-soctherm.h +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides constants for binding nvidia,tegra124-soctherm. - */ - -#ifndef _DT_BINDINGS_THERMAL_TEGRA124_SOCTHERM_H -#define _DT_BINDINGS_THERMAL_TEGRA124_SOCTHERM_H - -#define TEGRA124_SOCTHERM_SENSOR_CPU 0 -#define TEGRA124_SOCTHERM_SENSOR_MEM 1 -#define TEGRA124_SOCTHERM_SENSOR_GPU 2 -#define TEGRA124_SOCTHERM_SENSOR_PLLX 3 -#define TEGRA124_SOCTHERM_SENSOR_NUM 4 - -#define TEGRA_SOCTHERM_THROT_LEVEL_NONE 0 -#define TEGRA_SOCTHERM_THROT_LEVEL_LOW 1 -#define TEGRA_SOCTHERM_THROT_LEVEL_MED 2 -#define TEGRA_SOCTHERM_THROT_LEVEL_HIGH 3 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/thermal/tegra186-bpmp-thermal.h b/sys/gnu/dts/include/dt-bindings/thermal/tegra186-bpmp-thermal.h deleted file mode 100644 index a96b8fa31aa..00000000000 --- a/sys/gnu/dts/include/dt-bindings/thermal/tegra186-bpmp-thermal.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * This header provides constants for binding nvidia,tegra186-bpmp-thermal. - */ - -#ifndef _DT_BINDINGS_THERMAL_TEGRA186_BPMP_THERMAL_H -#define _DT_BINDINGS_THERMAL_TEGRA186_BPMP_THERMAL_H - -#define TEGRA186_BPMP_THERMAL_ZONE_CPU 2 -#define TEGRA186_BPMP_THERMAL_ZONE_GPU 3 -#define TEGRA186_BPMP_THERMAL_ZONE_AUX 4 -#define TEGRA186_BPMP_THERMAL_ZONE_PLLX 5 -#define TEGRA186_BPMP_THERMAL_ZONE_AO 6 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/thermal/tegra194-bpmp-thermal.h b/sys/gnu/dts/include/dt-bindings/thermal/tegra194-bpmp-thermal.h deleted file mode 100644 index aa7fb08135c..00000000000 --- a/sys/gnu/dts/include/dt-bindings/thermal/tegra194-bpmp-thermal.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * This header provides constants for binding nvidia,tegra194-bpmp-thermal. - */ - -#ifndef _DT_BINDINGS_THERMAL_TEGRA194_BPMP_THERMAL_H -#define _DT_BINDINGS_THERMAL_TEGRA194_BPMP_THERMAL_H - -#define TEGRA194_BPMP_THERMAL_ZONE_CPU 2 -#define TEGRA194_BPMP_THERMAL_ZONE_GPU 3 -#define TEGRA194_BPMP_THERMAL_ZONE_AUX 4 -#define TEGRA194_BPMP_THERMAL_ZONE_PLLX 5 -#define TEGRA194_BPMP_THERMAL_ZONE_AO 6 -#define TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX 7 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/thermal/thermal.h b/sys/gnu/dts/include/dt-bindings/thermal/thermal.h deleted file mode 100644 index bc7babb1a67..00000000000 --- a/sys/gnu/dts/include/dt-bindings/thermal/thermal.h +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * This header provides constants for most thermal bindings. - * - * Copyright (C) 2013 Texas Instruments - * Eduardo Valentin - */ - -#ifndef _DT_BINDINGS_THERMAL_THERMAL_H -#define _DT_BINDINGS_THERMAL_THERMAL_H - -/* On cooling devices upper and lower limits */ -#define THERMAL_NO_LIMIT (~0) - -#endif - diff --git a/sys/gnu/dts/include/dt-bindings/thermal/thermal_exynos.h b/sys/gnu/dts/include/dt-bindings/thermal/thermal_exynos.h deleted file mode 100644 index 52fcb51dda3..00000000000 --- a/sys/gnu/dts/include/dt-bindings/thermal/thermal_exynos.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * thermal_exynos.h - Samsung Exynos TMU device tree definitions - * - * Copyright (C) 2014 Samsung Electronics - * Lukasz Majewski - */ - -#ifndef _EXYNOS_THERMAL_TMU_DT_H -#define _EXYNOS_THERMAL_TMU_DT_H - -#define TYPE_ONE_POINT_TRIMMING 0 -#define TYPE_ONE_POINT_TRIMMING_25 1 -#define TYPE_ONE_POINT_TRIMMING_85 2 -#define TYPE_TWO_POINT_TRIMMING 3 -#define TYPE_NONE 4 - -#endif /* _EXYNOS_THERMAL_TMU_DT_H */ diff --git a/sys/gnu/dts/include/dt-bindings/usb/pd.h b/sys/gnu/dts/include/dt-bindings/usb/pd.h deleted file mode 100644 index 985f2bbd4d2..00000000000 --- a/sys/gnu/dts/include/dt-bindings/usb/pd.h +++ /dev/null @@ -1,88 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __DT_POWER_DELIVERY_H -#define __DT_POWER_DELIVERY_H - -/* Power delivery Power Data Object definitions */ -#define PDO_TYPE_FIXED 0 -#define PDO_TYPE_BATT 1 -#define PDO_TYPE_VAR 2 -#define PDO_TYPE_APDO 3 - -#define PDO_TYPE_SHIFT 30 -#define PDO_TYPE_MASK 0x3 - -#define PDO_TYPE(t) ((t) << PDO_TYPE_SHIFT) - -#define PDO_VOLT_MASK 0x3ff -#define PDO_CURR_MASK 0x3ff -#define PDO_PWR_MASK 0x3ff - -#define PDO_FIXED_DUAL_ROLE (1 << 29) /* Power role swap supported */ -#define PDO_FIXED_SUSPEND (1 << 28) /* USB Suspend supported (Source) */ -#define PDO_FIXED_HIGHER_CAP (1 << 28) /* Requires more than vSafe5V (Sink) */ -#define PDO_FIXED_EXTPOWER (1 << 27) /* Externally powered */ -#define PDO_FIXED_USB_COMM (1 << 26) /* USB communications capable */ -#define PDO_FIXED_DATA_SWAP (1 << 25) /* Data role swap supported */ -#define PDO_FIXED_VOLT_SHIFT 10 /* 50mV units */ -#define PDO_FIXED_CURR_SHIFT 0 /* 10mA units */ - -#define PDO_FIXED_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_FIXED_VOLT_SHIFT) -#define PDO_FIXED_CURR(ma) ((((ma) / 10) & PDO_CURR_MASK) << PDO_FIXED_CURR_SHIFT) - -#define PDO_FIXED(mv, ma, flags) \ - (PDO_TYPE(PDO_TYPE_FIXED) | (flags) | \ - PDO_FIXED_VOLT(mv) | PDO_FIXED_CURR(ma)) - -#define VSAFE5V 5000 /* mv units */ - -#define PDO_BATT_MAX_VOLT_SHIFT 20 /* 50mV units */ -#define PDO_BATT_MIN_VOLT_SHIFT 10 /* 50mV units */ -#define PDO_BATT_MAX_PWR_SHIFT 0 /* 250mW units */ - -#define PDO_BATT_MIN_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_BATT_MIN_VOLT_SHIFT) -#define PDO_BATT_MAX_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_BATT_MAX_VOLT_SHIFT) -#define PDO_BATT_MAX_POWER(mw) ((((mw) / 250) & PDO_PWR_MASK) << PDO_BATT_MAX_PWR_SHIFT) - -#define PDO_BATT(min_mv, max_mv, max_mw) \ - (PDO_TYPE(PDO_TYPE_BATT) | PDO_BATT_MIN_VOLT(min_mv) | \ - PDO_BATT_MAX_VOLT(max_mv) | PDO_BATT_MAX_POWER(max_mw)) - -#define PDO_VAR_MAX_VOLT_SHIFT 20 /* 50mV units */ -#define PDO_VAR_MIN_VOLT_SHIFT 10 /* 50mV units */ -#define PDO_VAR_MAX_CURR_SHIFT 0 /* 10mA units */ - -#define PDO_VAR_MIN_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_VAR_MIN_VOLT_SHIFT) -#define PDO_VAR_MAX_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_VAR_MAX_VOLT_SHIFT) -#define PDO_VAR_MAX_CURR(ma) ((((ma) / 10) & PDO_CURR_MASK) << PDO_VAR_MAX_CURR_SHIFT) - -#define PDO_VAR(min_mv, max_mv, max_ma) \ - (PDO_TYPE(PDO_TYPE_VAR) | PDO_VAR_MIN_VOLT(min_mv) | \ - PDO_VAR_MAX_VOLT(max_mv) | PDO_VAR_MAX_CURR(max_ma)) - -#define APDO_TYPE_PPS 0 - -#define PDO_APDO_TYPE_SHIFT 28 /* Only valid value currently is 0x0 - PPS */ -#define PDO_APDO_TYPE_MASK 0x3 - -#define PDO_APDO_TYPE(t) ((t) << PDO_APDO_TYPE_SHIFT) - -#define PDO_PPS_APDO_MAX_VOLT_SHIFT 17 /* 100mV units */ -#define PDO_PPS_APDO_MIN_VOLT_SHIFT 8 /* 100mV units */ -#define PDO_PPS_APDO_MAX_CURR_SHIFT 0 /* 50mA units */ - -#define PDO_PPS_APDO_VOLT_MASK 0xff -#define PDO_PPS_APDO_CURR_MASK 0x7f - -#define PDO_PPS_APDO_MIN_VOLT(mv) \ - ((((mv) / 100) & PDO_PPS_APDO_VOLT_MASK) << PDO_PPS_APDO_MIN_VOLT_SHIFT) -#define PDO_PPS_APDO_MAX_VOLT(mv) \ - ((((mv) / 100) & PDO_PPS_APDO_VOLT_MASK) << PDO_PPS_APDO_MAX_VOLT_SHIFT) -#define PDO_PPS_APDO_MAX_CURR(ma) \ - ((((ma) / 50) & PDO_PPS_APDO_CURR_MASK) << PDO_PPS_APDO_MAX_CURR_SHIFT) - -#define PDO_PPS_APDO(min_mv, max_mv, max_ma) \ - (PDO_TYPE(PDO_TYPE_APDO) | PDO_APDO_TYPE(APDO_TYPE_PPS) | \ - PDO_PPS_APDO_MIN_VOLT(min_mv) | PDO_PPS_APDO_MAX_VOLT(max_mv) | \ - PDO_PPS_APDO_MAX_CURR(max_ma)) - - #endif /* __DT_POWER_DELIVERY_H */ diff --git a/sys/gnu/dts/mips/3G-6200N.dts b/sys/gnu/dts/mips/3G-6200N.dts deleted file mode 100644 index cd2ba51d1ac..00000000000 --- a/sys/gnu/dts/mips/3G-6200N.dts +++ /dev/null @@ -1,109 +0,0 @@ -/dts-v1/; - -#include "rt3050.dtsi" - -/ { - compatible = "3G-6200N", "ralink,rt3050-soc"; - model = "Edimax 3g-6200n"; - - cfi@1f000000 { - compatible = "cfi-flash"; - reg = <0x1f000000 0x800000>; - bank-width = <2>; - device-width = <2>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@3e0000 { - label = "cimage"; - reg = <0x3e0000 0x20000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x390000>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - power { - label = "3g-6200n:green:power"; - gpios = <&gpio0 9 1>; - }; - - wlan { - label = "3g-6200n:amber:wlan"; - gpios = <&gpio0 14 1>; - }; - - 3g { - label = "3g-6200n:blue:3g"; - gpios = <&gpio0 7 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - wps { - label = "wps"; - gpios = <&gpio0 12 1>; - linux,code = <0x211>; - }; - - wlanswitch { - label = "wlanswitch"; - gpios = <&gpio0 13 1>; - linux,code = <0x100>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - mtd-mac-address = <&factory 0x4>; -}; - -&esw { - mediatek,portmap = <0x2f>; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; - -&otg { - status = "okay"; -}; diff --git a/sys/gnu/dts/mips/3G-6200NL.dts b/sys/gnu/dts/mips/3G-6200NL.dts deleted file mode 100644 index 5ae43b81cbc..00000000000 --- a/sys/gnu/dts/mips/3G-6200NL.dts +++ /dev/null @@ -1,93 +0,0 @@ -/dts-v1/; - -#include "rt3050.dtsi" - -/ { - compatible = "3G-6200NL", "ralink,rt3050-soc"; - model = "Edimax 3g-6200nl"; - - cfi@1f000000 { - compatible = "cfi-flash"; - reg = <0x1f000000 0x800000>; - bank-width = <2>; - device-width = <2>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@3e0000 { - label = "cimage"; - reg = <0x3e0000 0x20000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x390000>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - wlan { - label = "3g-6200nl:amber:wlan"; - gpios = <&gpio0 14 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - wps { - label = "wps"; - gpios = <&gpio0 12 1>; - linux,code = <0x211>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - mtd-mac-address = <&factory 0x4>; -}; - -&esw { - mediatek,portmap = <0x2f>; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; - -&otg { - status = "okay"; -}; diff --git a/sys/gnu/dts/mips/3G150B.dts b/sys/gnu/dts/mips/3G150B.dts deleted file mode 100644 index 3d348ff0f35..00000000000 --- a/sys/gnu/dts/mips/3G150B.dts +++ /dev/null @@ -1,116 +0,0 @@ -/dts-v1/; - -#include "rt5350.dtsi" - -/ { - compatible = "3G150B", "ralink,rt5350-soc"; - model = "Tenda 3G150B"; - - gpio-leds { - compatible = "gpio-leds"; - - ap { - label = "3g150b:blue:ap"; - gpios = <&gpio0 7 1>; - }; - - 3g { - label = "3g150b:blue:3g"; - gpios = <&gpio0 14 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio0 0 1>; - linux,code = <0x198>; - }; - }; - - gpio_export { - compatible = "gpio-export"; - #size-cells = <0>; - - usb { - gpio-export,name = "usb"; - gpio-export,output = <1>; - gpios = <&gpio0 13 0>; - }; - }; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80", "s25fl064k"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x3b0000>; - }; - }; -}; - -&gpio1 { - status = "okay"; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "jtag", "rgmii", "mdio", "uartf", "led"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - mtd-mac-address = <&factory 0x4>; -}; - -&esw { - mediatek,portmap = <0x2f>; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; - ralink,led-polarity = <1>; -}; - -&ehci { - status = "okay"; -}; - -&ohci { - status = "okay"; -}; diff --git a/sys/gnu/dts/mips/3G300M.dts b/sys/gnu/dts/mips/3G300M.dts deleted file mode 100644 index df770d83d51..00000000000 --- a/sys/gnu/dts/mips/3G300M.dts +++ /dev/null @@ -1,122 +0,0 @@ -/dts-v1/; - -#include "rt3050.dtsi" - -/ { - compatible = "3G300M", "ralink,rt3052-soc"; - model = "Tenda 3G300M"; - - gpio-leds { - compatible = "gpio-leds"; - - 3grouter { - label = "3g300m:blue:3grouter"; - gpios = <&gpio0 11 1>; - }; - - ap { - label = "3g300m:blue:ap"; - gpios = <&gpio0 12 1>; - }; - - wisprouter { - label = "3g300m:blue:wisprouter"; - gpios = <&gpio0 9 1>; - }; - - wirelessrouter { - label = "3g300m:blue:wirelessrouter"; - gpios = <&gpio0 13 1>; - }; - - 3g { - label = "3g300m:blue:3g"; - gpios = <&gpio0 7 1>; - }; - - wpsreset { - label = "3g300m:blue:wpsreset"; - gpios = <&gpio0 14 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio0 0 1>; - linux,code = <0x198>; - }; - - mode { - label = "mode"; - gpios = <&gpio0 10 1>; - linux,code = <0x100>; - }; - }; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80", "mx25l3205d"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x3b0000>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - mtd-mac-address = <&factory 0x4>; -}; - -&esw { - mediatek,portmap = <0x2f>; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; - -&otg { - status = "okay"; -}; diff --git a/sys/gnu/dts/mips/A5-V11.dts b/sys/gnu/dts/mips/A5-V11.dts deleted file mode 100644 index 51eb0058746..00000000000 --- a/sys/gnu/dts/mips/A5-V11.dts +++ /dev/null @@ -1,122 +0,0 @@ -/dts-v1/; - -#include "rt5350.dtsi" - -/ { - compatible = "A5-V11", "ralink,rt5350-soc"; - model = "A5-V11"; - - gpio-leds { - compatible = "gpio-leds"; - - system { - label = "a5-v11:blue:system"; - gpios = <&gpio0 20 1>; - }; - - power { - label = "a5-v11:red:power"; - gpios = <&gpio0 17 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio0 0 1>; - linux,code = <0x198>; - }; - }; - - gpio_export { - compatible = "gpio-export"; - #size-cells = <0>; - - usb { - gpio-export,name = "usb"; - gpio-export,output = <1>; - gpios = <&gpio0 7 0>; - }; - - root_hub { - gpio-export,name = "root_hub"; - gpio-export,output = <1>; - gpios = <&gpio0 12 0>; - }; - }; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80", "pm25lq032"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x3b0000>; - }; - }; -}; - -&gpio1 { - status = "okay"; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "jtag", "uartf", "led"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - mtd-mac-address = <&factory 0x4>; -}; - -&esw { - mediatek,portmap = <0x1>; - mediatek,portdisable = <0x3e>; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; - -&ehci { - status = "okay"; -}; - -&ohci { - status = "okay"; -}; diff --git a/sys/gnu/dts/mips/AI-BR100.dts b/sys/gnu/dts/mips/AI-BR100.dts deleted file mode 100644 index 2c3293331a9..00000000000 --- a/sys/gnu/dts/mips/AI-BR100.dts +++ /dev/null @@ -1,107 +0,0 @@ -/dts-v1/; - -#include "mt7620a.dtsi" - -/ { - compatible = "AI-BR100", "ralink,mt7620a-soc"; - model = "Aigale Ai-BR100"; - - gpio-leds { - compatible = "gpio-leds"; - - wan { - label = "ai-br100:blue:wan"; - gpios = <&gpio2 4 1>; - }; - - wlan { - label = "ai-br100:blue:wlan"; - gpios = <&gpio3 0 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio0 12 1>; - linux,code = <0x198>; - }; - }; -}; - -&gpio2 { - status = "okay"; -}; - -&gpio3 { - status = "okay"; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0 0>; - linux,modalias = "m25p80", "en25q64"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x20000>; - read-only; - }; - - partition@20000 { - label = "u-boot-env"; - reg = <0x20000 0x10000>; - read-only; - }; - - factory: partition@30000 { - label = "factory"; - reg = <0x30000 0x10000>; - read-only; - }; - - partition@40000 { - label = "firmware"; - reg = <0x40000 0x7c0000>; - }; - }; -}; - -&ehci { - status = "okay"; -}; - -&ohci { - status = "okay"; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "uartf", "rgmii1", "rgmii2", "ephy", "wled", "nd_sd"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - pinctrl-names = "default"; - pinctrl-0 = <&ephy_pins>; - mtd-mac-address = <&factory 0x4>; - mediatek,portmap = "llllw"; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; diff --git a/sys/gnu/dts/mips/AIR3GII.dts b/sys/gnu/dts/mips/AIR3GII.dts deleted file mode 100644 index 2b08895b496..00000000000 --- a/sys/gnu/dts/mips/AIR3GII.dts +++ /dev/null @@ -1,96 +0,0 @@ -/dts-v1/; - -#include "rt5350.dtsi" - -/ { - compatible = "AIR3GII", "ralink,rt5350-soc"; - model = "AirLive Air3GII"; - - gpio-leds { - compatible = "gpio-leds"; - - wlan { - label = "air3gii:green:wlan"; - gpios = <&gpio0 8 0>; - }; - - mobile { - label = "air3gii:green:mobile"; - gpios = <&gpio0 9 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - wps { - label = "wps"; - gpios = <&gpio0 7 1>; - linux,code = <0x211>; - }; - }; -}; - -&gpio0 { - status = "okay"; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80", "en25q32b"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x3b0000>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "jtag", "uartf"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - mtd-mac-address = <&factory 0x4>; -}; - -&esw { - mediatek,portmap = <0x2f>; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; diff --git a/sys/gnu/dts/mips/ALL0239-3G.dts b/sys/gnu/dts/mips/ALL0239-3G.dts deleted file mode 100644 index d1d92e168c9..00000000000 --- a/sys/gnu/dts/mips/ALL0239-3G.dts +++ /dev/null @@ -1,116 +0,0 @@ -/dts-v1/; - -#include "rt3050.dtsi" - -/ { - compatible = "ALL0239-3G", "ralink,rt3052-soc"; - model = "Allnet ALL0239-3G"; - - - cfi@1f000000 { - compatible = "cfi-flash"; - reg = <0x1f000000 0x800000>; - bank-width = <2>; - device-width = <2>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x7b0000>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - usb { - label = "all0239-3g:green:usb"; - gpios = <&gpio0 8 1>; - }; - - 3g { - label = "all0239-3g:green:3g"; - gpios = <&gpio0 11 1>; - }; - - status { - label = "all0239-3g:green:status"; - gpios = <&gpio0 12 1>; - }; - - wps { - label = "all0239-3g:green:wps"; - gpios = <&gpio0 14 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio0 10 1>; - linux,code = <0x198>; - }; - - connect { - label = "connect"; - gpios = <&gpio0 7 1>; - linux,code = <0xda>; - }; - - wps { - label = "wps"; - gpios = <&gpio0 0 1>; - linux,code = <0x211>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - mtd-mac-address = <&factory 0x28>; -}; - -&esw { - status = "okay"; - mediatek,portmap = <0x3e>; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; - -&otg { - status = "okay"; -}; diff --git a/sys/gnu/dts/mips/ALL0256N-4M.dts b/sys/gnu/dts/mips/ALL0256N-4M.dts deleted file mode 100644 index 1cfaed67bb7..00000000000 --- a/sys/gnu/dts/mips/ALL0256N-4M.dts +++ /dev/null @@ -1,101 +0,0 @@ -/dts-v1/; - -#include "rt3050.dtsi" - -/ { - compatible = "ALL0256N", "ralink,rt3050-soc"; - model = "Allnet ALL0256N"; - - gpio-leds { - compatible = "gpio-leds"; - - rssilow { - label = "all0256n:green:rssilow"; - gpios = <&gpio0 14 1>; - }; - - rssimed { - label = "all0256n:green:rssimed"; - gpios = <&gpio0 12 1>; - }; - - rssihigh { - label = "all0256n:green:rssihigh"; - gpios = <&gpio0 13 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio0 0 1>; - linux,code = <0x198>; - }; - }; -}; - -&gpio0 { - status = "okay"; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80", "mx25l3205d"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x3c8000>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - mtd-mac-address = <&factory 0x28>; -}; - -&esw { - mediatek,portmap = <0x3f>; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; diff --git a/sys/gnu/dts/mips/ALL0256N-8M.dts b/sys/gnu/dts/mips/ALL0256N-8M.dts deleted file mode 100644 index 074273d6088..00000000000 --- a/sys/gnu/dts/mips/ALL0256N-8M.dts +++ /dev/null @@ -1,101 +0,0 @@ -/dts-v1/; - -#include "rt3050.dtsi" - -/ { - compatible = "ALL0256N", "ralink,rt3050-soc"; - model = "Allnet ALL0256N"; - - gpio-leds { - compatible = "gpio-leds"; - - rssilow { - label = "all0256n:green:rssilow"; - gpios = <&gpio0 14 1>; - }; - - rssimed { - label = "all0256n:green:rssimed"; - gpios = <&gpio0 12 1>; - }; - - rssihigh { - label = "all0256n:green:rssihigh"; - gpios = <&gpio0 13 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio0 0 1>; - linux,code = <0x198>; - }; - }; -}; - -&gpio0 { - status = "okay"; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80", "mx25l3205d"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x7b0000>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - mtd-mac-address = <&factory 0x28>; -}; - -&esw { - mediatek,portmap = <0x3f>; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; diff --git a/sys/gnu/dts/mips/ALL5002.dts b/sys/gnu/dts/mips/ALL5002.dts deleted file mode 100644 index 14bbdcdf122..00000000000 --- a/sys/gnu/dts/mips/ALL5002.dts +++ /dev/null @@ -1,109 +0,0 @@ -/dts-v1/; - -#include "rt3352.dtsi" - -/ { - compatible = "ALL5002", "ralink,rt3352-soc"; - model = "Allnet ALL5002"; - - i2c-gpio { - compatible = "i2c-gpio"; - gpios = <&gpio0 1 0 &gpio0 2 0>; - i2c-gpio,delay-us = <10>; - - pcf0: iexp@38 { - #gpio-cells = <2>; - compatible = "inxp,pcf8574a"; - reg = <0x38>; - gpio-controller; - }; - - hwmon@4b { - compatible = "national,lm92"; - reg = <0x4b>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - ld1 { - label = "all5002:green:ld1"; - gpios = <&pcf0 0 1>; - }; - - ld2 { - label = "all5002:green:ld2"; - gpios = <&pcf0 1 1>; - }; - }; -}; - -&gpio0 { - status = "okay"; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80", "mx25l25635e"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x1fb0000>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - mtd-mac-address = <&factory 0x28>; -}; - -&esw { - mediatek,portmap = <0x3f>; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; - -&ehci { - status = "okay"; -}; - -&ohci { - status = "okay"; -}; diff --git a/sys/gnu/dts/mips/ALL5003.dts b/sys/gnu/dts/mips/ALL5003.dts deleted file mode 100644 index 432dd516ff2..00000000000 --- a/sys/gnu/dts/mips/ALL5003.dts +++ /dev/null @@ -1,109 +0,0 @@ -/dts-v1/; - -#include "rt5350.dtsi" - -/ { - compatible = "ALL5003", "ralink,rt5350-soc"; - model = "Allnet ALL5003"; - - i2c-gpio { - compatible = "i2c-gpio"; - gpios = <&gpio0 1 0 &gpio0 2 0>; - i2c-gpio,delay-us = <10>; - - pcf0: iexp@38 { - #gpio-cells = <2>; - compatible = "inxp,pcf8574a"; - reg = <0x38>; - gpio-controller; - }; - - hwmon@4b { - compatible = "national,lm92"; - reg = <0x4b>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - ld1 { - label = "all5003:green:ld1"; - gpios = <&pcf0 0 1>; - }; - - ld2 { - label = "all5003:green:ld2"; - gpios = <&pcf0 1 1>; - }; - }; -}; - -&gpio0 { - status = "okay"; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80", "mx25l25635e"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x1fb0000>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - mtd-mac-address = <&factory 0x28>; -}; - -&esw { - mediatek,portmap = <0x3f>; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; - -&ehci { - status = "okay"; -}; - -&ohci { - status = "okay"; -}; diff --git a/sys/gnu/dts/mips/AR670W.dts b/sys/gnu/dts/mips/AR670W.dts deleted file mode 100644 index c1eac438816..00000000000 --- a/sys/gnu/dts/mips/AR670W.dts +++ /dev/null @@ -1,103 +0,0 @@ -/dts-v1/; - -#include "rt2880.dtsi" - -/ { - compatible = "AR670W", "ralink,rt2880-soc"; - model = "Airlink101 AR670W"; - - cfi@bdc00000 { - compatible = "cfi-flash"; - reg = <0xbc400000 0x800000>; - bank-width = <2>; - #address-cells = <1>; - #size-cells = <1>; - - u-boot@0 { - reg = <0x0 0x30000>; - label = "u-boot"; - read-only; - }; - - factory: factory@30000 { - reg = <0x30000 0x10000>; - label = "factory"; - read-only; - }; - - firmware@40000 { - reg = <0x40000 0x3c0000>; - label = "firmware"; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - status { - label = "ar670w:green:power"; - gpios = <&gpio0 7 1>; - }; - - wpsblue { - label = "ar670w:blue:wps"; - gpios = <&gpio0 13 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <100>; - - wps { - label = "wps"; - gpios = <&gpio0 0 1>; - linux,code = <0x211>; - }; - - reset { - label = "reset"; - gpios = <&gpio0 9 1>; - linux,code = <0x198>; - }; - }; -}; - -&gpio0 { - status = "okay"; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "spi", "uartlite"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - status = "okay"; - mtd-mac-address = <&factory 0x2004>; - - port@0 { - phy-handle = <&phy0>; - phy-mode = "mii"; - }; - - mdio-bus { - status = "okay"; - - phy0: ethernet-phy@0 { - phy-mode = "mii"; - reg = <0>; - }; - }; -}; - -&wmac { - status = "okay"; - ralink,mtd-eeprom = <&factory 0x2000>; -}; diff --git a/sys/gnu/dts/mips/AR725W.dts b/sys/gnu/dts/mips/AR725W.dts deleted file mode 100644 index 3b8cfb3be71..00000000000 --- a/sys/gnu/dts/mips/AR725W.dts +++ /dev/null @@ -1,113 +0,0 @@ -/dts-v1/; - -#include "rt2880.dtsi" - -/ { - compatible = "AR725W", "ralink,rt2880-soc"; - model = "Airlink101 AR725W"; - - cfi@bdc00000 { - compatible = "cfi-flash"; - reg = <0xbc400000 0x800000>; - bank-width = <2>; - #address-cells = <1>; - #size-cells = <1>; - - u-boot@0 { - reg = <0x0 0x30000>; - label = "u-boot"; - read-only; - }; - - u-boot-env@30000 { - reg = <0x30000 0x10000>; - label = "u-boot-env"; - }; - - factory: factory@40000 { - reg = <0x40000 0x10000>; - label = "factory"; - read-only; - }; - - firmware@50000 { - reg = <0x50000 0x3B0000>; - label = "firmware"; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - status { - label = "ar725w:green:power"; - gpios = <&gpio0 7 0>; - }; - - wpsred { - label = "ar725w:red:wps"; - gpios = <&gpio0 8 1>; - }; - - wpsblue { - label = "ar725w:blue:wps"; - gpios = <&gpio0 13 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <100>; - - wps { - label = "wps"; - gpios = <&gpio0 0 1>; - linux,code = <0x211>; - }; - - reset { - label = "reset"; - gpios = <&gpio0 9 1>; - linux,code = <0x198>; - }; - }; -}; - -&gpio0 { - status = "okay"; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "spi", "uartlite"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - status = "okay"; - mtd-mac-address = <&factory 0x4>; - - port@0 { - phy-handle = <&phy0>; - phy-mode = "mii"; - }; - - mdio-bus { - status = "okay"; - - phy0: ethernet-phy@0 { - phy-mode = "mii"; - reg = <0>; - }; - }; -}; - -&wmac { - status = "okay"; - ralink,mtd-eeprom = <&factory 0>; -}; diff --git a/sys/gnu/dts/mips/ASL26555-16M.dts b/sys/gnu/dts/mips/ASL26555-16M.dts deleted file mode 100644 index 56f3c9d99c9..00000000000 --- a/sys/gnu/dts/mips/ASL26555-16M.dts +++ /dev/null @@ -1,154 +0,0 @@ -/dts-v1/; - -#include "rt3050.dtsi" - -/ { - compatible = "ASL26555", "ralink,rt3050-soc"; - model = "Alpha ASL26555"; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio0 10 0>; - linux,code = <0x198>; - }; - - wps { - label = "wps"; - gpios = <&gpio0 12 0>; - linux,code = <0x211>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - eth { - label = "asl26555:green:eth"; - gpios = <&gpio0 0 1>; - }; - - wan-red { - label = "asl26555:red:wan"; - gpios = <&gpio0 1 0>; - }; - - wan-green { - label = "asl26555:green:wan"; - gpios = <&gpio0 2 0>; - }; - - wlan { - label = "asl26555:green:wlan"; - gpios = <&gpio0 7 0>; - }; - - power-green { - label = "asl26555:green:power"; - gpios = <&gpio0 8 0>; - }; - - power-red { - label = "asl26555:red:power"; - gpios = <&gpio0 9 0>; - }; - - 3g-green { - label = "asl26555:green:3g"; - gpios = <&gpio0 14 1>; - }; - - 3g-red { - label = "asl26555:red:3g"; - gpios = <&gpio0 17 1>; - }; - }; -}; - -&gpio0 { - status = "okay"; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80", "s25sl12801"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "uboot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "uboot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0xf80000>; - }; - - partition@fd0000 { - label = "cert"; - reg = <0xfd0000 0x10000>; - read-only; - }; - - partition@fe0000 { - label = "langpack"; - reg = <0xfe0000 0x10000>; - read-only; - }; - - devdata: partition@ff0000 { - label = "devdata"; - reg = <0xff0000 0x10000>; - read-only; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - mtd-mac-address = <&devdata 0x4004>; -}; - -&esw { - mediatek,portmap = <0x1e>; -}; - -&wmac { - ralink,mtd-eeprom = <&devdata 0x4000>; -}; - -&otg { - status = "okay"; -}; diff --git a/sys/gnu/dts/mips/ASL26555-8M.dts b/sys/gnu/dts/mips/ASL26555-8M.dts deleted file mode 100644 index 0dbc1dd3373..00000000000 --- a/sys/gnu/dts/mips/ASL26555-8M.dts +++ /dev/null @@ -1,148 +0,0 @@ -/dts-v1/; - -#include "rt3050.dtsi" - -/ { - compatible = "ASL26555", "ralink,rt3050-soc"; - model = "Alpha ASL26555"; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio0 10 0>; - linux,code = <0x198>; - }; - - wps { - label = "wps"; - gpios = <&gpio0 12 0>; - linux,code = <0x211>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - eth { - label = "asl26555:green:eth"; - gpios = <&gpio0 0 1>; - }; - - wan-red { - label = "asl26555:red:wan"; - gpios = <&gpio0 1 0>; - }; - - wan-green { - label = "asl26555:green:wan"; - gpios = <&gpio0 2 0>; - }; - - wlan { - label = "asl26555:green:wlan"; - gpios = <&gpio0 7 0>; - }; - - power-green { - label = "asl26555:green:power"; - gpios = <&gpio0 8 0>; - }; - - power-red { - label = "asl26555:red:power"; - gpios = <&gpio0 9 0>; - }; - - 3g-green { - label = "asl26555:green:3g"; - gpios = <&gpio0 14 1>; - }; - - 3g-red { - label = "asl26555:red:3g"; - gpios = <&gpio0 17 1>; - }; - }; -}; - -&gpio0 { - status = "okay"; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80", "s25sl064p"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "uboot"; - reg = <0x0 0x30000>; - read-only; - }; - - ubootenv: partition@30000 { - label = "uboot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - partition@40000 { - label = "rgdb"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x790000>; - }; - - partition@7e0000 { - label = "cert"; - reg = <0x7e0000 0x10000>; - read-only; - }; - - partition@7f0000 { - label = "langpack"; - reg = <0x7f0000 0x10000>; - read-only; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - mtd-mac-address = <&ubootenv 0x4004>; -}; - -&esw { - mediatek,portmap = <0x1e>; -}; - -&wmac { - ralink,mtd-eeprom = <&ubootenv 0x4000>; -}; - -&otg { - status = "okay"; -}; diff --git a/sys/gnu/dts/mips/ATP-52B.dts b/sys/gnu/dts/mips/ATP-52B.dts deleted file mode 100644 index c15d3a46458..00000000000 --- a/sys/gnu/dts/mips/ATP-52B.dts +++ /dev/null @@ -1,97 +0,0 @@ -/dts-v1/; - -#include "rt3050.dtsi" - -/ { - compatible = "ATP-52B", "ralink,rt3052-soc"; - model = "Argus ATP-52B"; - - cfi@1f000000 { - compatible = "cfi-flash"; - reg = <0x1f000000 0x800000>; - bank-width = <2>; - device-width = <2>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "bootloader"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "config"; - reg = <0x30000 0x10000>; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x7a0000>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - run { - label = "atp-52b:green:run"; - gpios = <&gpio0 9 1>; - }; - - net { - label = "atp-52b:amber:net"; - gpios = <&gpio0 13 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - wps { - label = "wps"; - gpios = <&gpio0 0 1>; - linux,code = <0x211>; - }; - - reset { - label = "reset"; - gpios = <&gpio0 10 1>; - linux,code = <0x198>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; -}; - - -ðernet { - mtd-mac-address = <&factory 0x4>; -}; - -&esw { - mediatek,portmap = <0x3e>; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; - -&otg { - status = "okay"; -}; diff --git a/sys/gnu/dts/mips/AWAPN2403.dts b/sys/gnu/dts/mips/AWAPN2403.dts deleted file mode 100644 index 7babe42d56f..00000000000 --- a/sys/gnu/dts/mips/AWAPN2403.dts +++ /dev/null @@ -1,83 +0,0 @@ -/dts-v1/; - -#include "rt3050.dtsi" - -/ { - compatible = "AWAPN2403", "ralink,rt3052-soc"; - model = "AsiaRF AWAPN2403"; - - gpio-leds { - compatible = "gpio-leds"; - - link { - label = "awapn2403:green:wps"; - gpios = <&gpio0 14 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio0 0 1>; - linux,code = <0x198>; - }; - }; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80", "mx25l3205d"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x3b0000>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; -}; - -&esw { - mediatek,portmap = <0x3e>; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; diff --git a/sys/gnu/dts/mips/AWM002-4M.dtsi b/sys/gnu/dts/mips/AWM002-4M.dtsi deleted file mode 100644 index 69d25bb5d45..00000000000 --- a/sys/gnu/dts/mips/AWM002-4M.dtsi +++ /dev/null @@ -1,11 +0,0 @@ -#include "AWM002.dtsi" - -/ { - compatible = "AWM002", "ralink,rt5350-soc"; - model = "AsiaRF AWM002"; -}; - -&m25p80 { - compatible = "jedec,spi-nor"; - linux,modalias = "m25p80", "mx25l3205d"; -}; diff --git a/sys/gnu/dts/mips/AWM002-8M.dtsi b/sys/gnu/dts/mips/AWM002-8M.dtsi deleted file mode 100644 index 1e6970ddec4..00000000000 --- a/sys/gnu/dts/mips/AWM002-8M.dtsi +++ /dev/null @@ -1,11 +0,0 @@ -#include "AWM002.dtsi" - -/ { - compatible = "AWM002", "ralink,rt5350-soc"; - model = "AsiaRF AWM002"; -}; - -&m25p80 { - compatible = "jedec,spi-nor"; - linux,modalias = "m25p80", "mx25l6405d"; -}; diff --git a/sys/gnu/dts/mips/AWM002-EVB-4M.dts b/sys/gnu/dts/mips/AWM002-EVB-4M.dts deleted file mode 100644 index e1252325578..00000000000 --- a/sys/gnu/dts/mips/AWM002-EVB-4M.dts +++ /dev/null @@ -1,53 +0,0 @@ -/dts-v1/; - -#include "AWM002-4M.dtsi" - -/ { - model = "AsiaRF AWM002 EVB"; - - gpio-leds { - compatible = "gpio-leds"; - - tx { - label = "awm002-evb:green:tx"; - gpios = <&gpio0 15 1>; - }; - - rx { - label = "awm002-evb:green:rx"; - gpios = <&gpio0 16 1>; - }; - - wps { - label = "awm002-evb:green:wps"; - gpios = <&gpio0 21 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset_wps { - label = "reset_wps"; - gpios = <&gpio0 0 1>; - linux,code = <0x198>; - }; - - mode { - label = "mode"; - gpios = <&gpio0 20 1>; - linux,code = <0x32>; - }; - }; -}; - -ðernet { - mtd-mac-address = <&factory 0x28>; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; diff --git a/sys/gnu/dts/mips/AWM002-EVB-8M.dts b/sys/gnu/dts/mips/AWM002-EVB-8M.dts deleted file mode 100644 index f2f91bb3d93..00000000000 --- a/sys/gnu/dts/mips/AWM002-EVB-8M.dts +++ /dev/null @@ -1,53 +0,0 @@ -/dts-v1/; - -#include "AWM002-8M.dtsi" - -/ { - model = "AsiaRF AWM002 EVB"; - - gpio-leds { - compatible = "gpio-leds"; - - tx { - label = "awm002-evb:green:tx"; - gpios = <&gpio0 15 1>; - }; - - rx { - label = "awm002-evb:green:rx"; - gpios = <&gpio0 16 1>; - }; - - wps { - label = "awm002-evb:green:wps"; - gpios = <&gpio0 21 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset_wps { - label = "reset_wps"; - gpios = <&gpio0 0 1>; - linux,code = <0x198>; - }; - - mode { - label = "mode"; - gpios = <&gpio0 20 1>; - linux,code = <0x32>; - }; - }; -}; - -ðernet { - mtd-mac-address = <&factory 0x28>; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; diff --git a/sys/gnu/dts/mips/AWM002.dtsi b/sys/gnu/dts/mips/AWM002.dtsi deleted file mode 100644 index 9ff64917eac..00000000000 --- a/sys/gnu/dts/mips/AWM002.dtsi +++ /dev/null @@ -1,76 +0,0 @@ -#include "rt5350.dtsi" - -/ { - compatible = "AWM002", "ralink,rt5350-soc"; - model = "AsiaRF AWM002"; - - gpio-leds { - compatible = "gpio-leds"; - - ld1 { - label = "awm002:green:ld1"; - gpios = <&gpio0 0 1>; - }; - - ld2 { - label = "awm002:green:ld2"; - gpios = <&gpio0 1 1>; - }; - }; -}; - -&spi0 { - status = "okay"; - - m25p80: m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - reg = <0>; - compatible = "jedec,spi-nor"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x1fb0000>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "jtag"; - ralink,function = "gpio"; - }; - }; -}; - -&esw { - mediatek,portmap = <0x3f>; -}; - -&ehci { - status = "okay"; -}; - -&ohci { - status = "okay"; -}; diff --git a/sys/gnu/dts/mips/AWM003-EVB.dts b/sys/gnu/dts/mips/AWM003-EVB.dts deleted file mode 100644 index 13e6964ccc2..00000000000 --- a/sys/gnu/dts/mips/AWM003-EVB.dts +++ /dev/null @@ -1,64 +0,0 @@ -/dts-v1/; - -#include "AWM002-8M.dtsi" - -/ { - compatible = "AWM003", "ralink,rt5350-soc"; - model = "AsiaRF AWM003 EVB"; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x4000000>; - }; - - gpio-leds { - compatible = "gpio-leds"; - - tx { - label = "awm003-evb:green:tx"; - gpios = <&gpio0 15 1>; - }; - - rx { - label = "awm003-evb:green:rx"; - gpios = <&gpio0 16 1>; - }; - - wps { - label = "awm003-evb:green:wps"; - gpios = <&gpio0 21 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset_wps { - label = "reset_wps"; - gpios = <&gpio0 0 1>; - linux,code = <0x198>; - }; - - mode { - label = "mode"; - gpios = <&gpio0 20 1>; - linux,code = <0x32>; - }; - }; -}; - -&m25p80 { - compatible = "jedec,spi-nor"; - linux,modalias = "m25p80", "mx25l6405d"; -}; - -ðernet { - mtd-mac-address = <&factory 0x28>; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; diff --git a/sys/gnu/dts/mips/ArcherC20i.dts b/sys/gnu/dts/mips/ArcherC20i.dts deleted file mode 100644 index e7a7b073462..00000000000 --- a/sys/gnu/dts/mips/ArcherC20i.dts +++ /dev/null @@ -1,116 +0,0 @@ -/dts-v1/; - -#include "mt7620a.dtsi" - -/ { - compatible = "ralink,mt7620a-soc"; - model = "TP-Link Archer C20i"; - - chosen { - bootargs = "console=ttyS0,115200"; - }; - - gpio-leds { - compatible = "gpio-leds"; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - }; -}; - -&gpio2 { - status = "okay"; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80", "mx25l6405d"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x20000>; - read-only; - }; - - partition@20000 { - label = "firmware"; - reg = <0x20000 0x7a0000>; - }; - - partition@7c0000 { - label = "config"; - reg = <0x7c0000 0x10000>; - }; - - rom: partition@7d0000 { - label = "rom"; - reg = <0x7d0000 0x10000>; - }; - - partition@7e0000 { - label = "romfile"; - reg = <0x7e0000 0x10000>; - }; - - radio: partition@7f0000 { - label = "radio"; - reg = <0x7f0000 0x10000>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "uartf", "rgmii1", "rgmii2", "wled", "nd_sd"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - pinctrl-names = "default"; - pinctrl-0 = <&ephy_pins>; - mtd-mac-address = <&rom 0xf100>; - mediatek,portmap = "wllll"; - }; - -&ehci { - status = "okay"; -}; - -&ohci { - status = "okay"; -}; - -&gsw { - mediatek,port4 = "ephy"; -}; - -&wmac { - ralink,mtd-eeprom = <&radio 0>; -}; - -&pcie { - status = "okay"; - - pcie-bridge { - mt76@0,0 { - reg = <0x0000 0 0 0 0>; - device_type = "pci"; - mediatek,mtd-eeprom = <&radio 32768>; - mediatek,2ghz = <0>; - }; - }; -}; diff --git a/sys/gnu/dts/mips/BC2.dts b/sys/gnu/dts/mips/BC2.dts deleted file mode 100644 index 5ae10a31a0f..00000000000 --- a/sys/gnu/dts/mips/BC2.dts +++ /dev/null @@ -1,87 +0,0 @@ -/dts-v1/; - -#include "rt3050.dtsi" - -/ { - compatible = "BC2", "ralink,rt3052-soc"; - model = "NexAira BC2"; - - cfi@1f000000 { - compatible = "cfi-flash"; - reg = <0x1f000000 0x800000>; - bank-width = <2>; - device-width = <2>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x7b0000>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - usb { - label = "bc2:blue:usb"; - gpios = <&gpio0 20 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio0 17 1>; - linux,code = <0x198>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - mtd-mac-address = <&factory 0x4>; -}; - -&esw { - mediatek,portmap = <0x2f>; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; - -&otg { - status = "okay"; -}; diff --git a/sys/gnu/dts/mips/BR-6425.dts b/sys/gnu/dts/mips/BR-6425.dts deleted file mode 100644 index b871ead992a..00000000000 --- a/sys/gnu/dts/mips/BR-6425.dts +++ /dev/null @@ -1,71 +0,0 @@ -/dts-v1/; - -#include "rt3050.dtsi" - -/ { - compatible = "BR-6425", "ralink,rt3052-soc"; - model = "Edimax BR-6425"; - - cfi@1f000000 { - compatible = "cfi-flash"; - reg = <0x1f000000 0x800000>; - bank-width = <2>; - device-width = <2>; - #address-cells = <1>; - #size-cells = <1>; - }; - - gpio-leds { - compatible = "gpio-leds"; - - power { - label = "br-6425:green:power"; - gpios = <&gpio0 9 1>; - }; - - wlan { - label = "br-6425:orange:wlan"; - gpios = <&gpio0 14 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset_wps { - label = "reset_wps"; - gpios = <&gpio0 12 1>; - linux,code = <0x198>; - }; - - rfkill { - label = "RFKILL switch"; - gpios = <&gpio0 13 1>; - linux,code = <0xf7>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { -/* mtd-mac-address = <&factory 0x4>; */ -}; - -&esw { - mediatek,portmap = <0x2f>; -}; - -&wmac { -/* ralink,mtd-eeprom = <&factory 0>; */ -}; diff --git a/sys/gnu/dts/mips/BR-6475ND.dts b/sys/gnu/dts/mips/BR-6475ND.dts deleted file mode 100644 index f437ac165ca..00000000000 --- a/sys/gnu/dts/mips/BR-6475ND.dts +++ /dev/null @@ -1,181 +0,0 @@ -/dts-v1/; - -#include "rt3883.dtsi" - -/ { - compatible = "BR-6475ND", "ralink,rt3883-soc"; - model = "Edimax BR-6475nD"; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <100>; - - reset { - label = "reset"; - gpios = <&gpio0 7 1>; - linux,code = <0x198>; - }; - - rfkill { - label = "rfkill"; - gpios = <&gpio0 9 1>; - linux,input-type = <5>; - linux,code = <0xf7>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - power { - label = "br-6475nd:green:power"; - gpios = <&gpio0 10 1>; - }; - - wlan { - label = "br-6475nd:amber:wlan"; - gpios = <&gpio0 11 1>; - }; - - wlan_5ghz { - label = "br-6475nd:amber:wlan_5ghz"; - gpios = <&gpio0 14 1>; - }; - }; - - nor-flash@1c000000 { - compatible = "cfi-flash"; - reg = <0x1c000000 0x800000>; - bank-width = <2>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - reg = <0x00000000 0x00030000>; - label = "u-boot"; - read-only; - }; - - partition@30000 { - reg = <0x00030000 0x00010000>; - label = "nvram"; - read-only; - }; - - factory: partition@40000 { - reg = <0x00040000 0x00010000>; - label = "factory"; - read-only; - }; - - devdata: partition@50000 { - reg = <0x00050000 0x00020000>; - label = "devdata"; - read-only; - }; - - partition@70000 { - reg = <0x00070000 0x00790000>; - label = "firmware"; - }; - - partition@170000 { - reg = <0x00270000 0x00590000>; - label = "rootfs"; - }; - }; - - rtl8367 { - compatible = "realtek,rtl8367"; - gpio-sda = <&gpio0 5 0>; - gpio-sck = <&gpio0 4 0>; - realtek,extif0 = <1 0 1 1 1 1 1 1 2>; - }; - - /* Unclear if this is the correct gpio setup; the USB ports are - unpopulated on a stock BR-6475nD, even though the hardware exists - and the headers are there. */ - /* - gpio_export { - compatible = "gpio-export"; - #size-cells = <0>; - - usb { - gpio-export,name="usb"; - gpio-export,output=<0>; - gpios = <&gpio0 19 0>; - }; - }; - */ -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "spi", "jtag", "uartf"; - ralink,function = "gpio"; - }; - }; -}; - -&timer { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&uartlite { - status = "okay"; -}; - -ðernet { - status = "okay"; - mtd-mac-address = <&devdata 0x0d>; - - port@0 { - mediatek,fixed-link = <1000 1 1 1>; - }; -}; - -&wmac { - status = "okay"; - ralink,mtd-eeprom = <&factory 0>; -}; - -&pci { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pci_pins>; - - pci_pins: pci { - pci { - ralink,group = "pci"; - ralink,function = "pci-fnc"; - }; - }; - - host-bridge { - pci-bridge@1 { - status = "okay"; - - wmac@0,0 { - ralink,5ghz = <0>; - compatible = "ralink,rt2880-pci", "pciclass060400", "pciclass0604"; - reg = < 0x10000 0 0 0 0 >; - ralink,eeprom = "rt2x00pci_1_0.eeprom"; - }; - }; - }; -}; - -&ehci { - status = "okay"; -}; - -&ohci { - status = "okay"; -}; diff --git a/sys/gnu/dts/mips/BROADWAY.dts b/sys/gnu/dts/mips/BROADWAY.dts deleted file mode 100644 index 790dcc0467f..00000000000 --- a/sys/gnu/dts/mips/BROADWAY.dts +++ /dev/null @@ -1,92 +0,0 @@ -/dts-v1/; - -#include "rt3050.dtsi" - -/ { - compatible = "BROADWAY", "ralink,rt3052-soc"; - model = "Hauppauge Broadway"; - - cfi@1f000000 { - compatible = "cfi-flash"; - reg = <0x1f000000 0x800000>; - bank-width = <2>; - device-width = <2>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "bootloader"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "config"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x790000>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - diskmounted { - label = "broadway:red:diskmounted"; - gpios = <&gpio0 9 1>; - }; - - wps_active { - label = "broadway:red:wps_active"; - gpios = <&gpio0 14 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - factory { - label = "Factory Reset button"; - gpios = <&gpio0 13 1>; - linux,code = <0x198>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - mtd-mac-address = <&factory 0x4>; -}; - -&esw { - mediatek,portmap = <0x3e>; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; - -&otg { - status = "okay"; -}; diff --git a/sys/gnu/dts/mips/CARAMBOLA.dts b/sys/gnu/dts/mips/CARAMBOLA.dts deleted file mode 100644 index e38c49f9574..00000000000 --- a/sys/gnu/dts/mips/CARAMBOLA.dts +++ /dev/null @@ -1,75 +0,0 @@ -/dts-v1/; - -#include "rt3050.dtsi" - -/ { - compatible = "CARAMBOLA", "ralink,rt3050-soc"; - model = "8devices Carambola"; - - chosen { - bootargs = "console=ttyS0,115200"; - }; - - cfi@1f000000 { - compatible = "cfi-flash"; - reg = <0x1f000000 0x800000>; - bank-width = <2>; - device-width = <2>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x7b0000>; - }; - }; - - i2c-gpio { - compatible = "i2c-gpio"; - gpios = <&gpio0 1 0 &gpio0 2 0>; - i2c-gpio,delay-us = <10>; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - mtd-mac-address = <&factory 0x28>; -}; - -&esw { - mediatek,portmap = <0x3f>; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; - -&otg { - status = "okay"; -}; diff --git a/sys/gnu/dts/mips/CF-WR800N.dts b/sys/gnu/dts/mips/CF-WR800N.dts deleted file mode 100644 index 913f142f352..00000000000 --- a/sys/gnu/dts/mips/CF-WR800N.dts +++ /dev/null @@ -1,113 +0,0 @@ -/dts-v1/; - -#include "mt7620n.dtsi" - -/ { - compatible = "cf-wr800n", "ralink,mt7620n-soc"; - model = "Comfast CF-WR800N"; - - chosen { - bootargs = "console=ttyS0,115200"; - }; - - gpio-leds { - compatible = "gpio-leds"; - - ethernet { - label = "cf-wr800n:white:ethernet"; - gpios = <&gpio2 4 1>; - }; - - wifi { - label = "cf-wr800n:white:wifi"; - gpios = <&gpio3 0 1>; - }; - - wps { - label = "cf-wr800n:white:wps"; - gpios = <&gpio1 15 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio0 2 1>; - linux,code = <0x198>; - }; - }; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&gpio2 { - status = "okay"; -}; - -&gpio3 { - status = "okay"; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80", "w25q64"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x7b0000>; - }; - }; -}; - -ðernet { - mtd-mac-address = <&factory 0x4>; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; - -&pinctrl { - state_default: pinctrl0 { - default { - ralink,group = "ephy", "wled", "spi refclk", "i2c"; - ralink,function = "gpio"; - }; - }; -}; diff --git a/sys/gnu/dts/mips/CS-QR10.dts b/sys/gnu/dts/mips/CS-QR10.dts deleted file mode 100644 index c3cb711a05f..00000000000 --- a/sys/gnu/dts/mips/CS-QR10.dts +++ /dev/null @@ -1,161 +0,0 @@ -/dts-v1/; - -#include "mt7620a.dtsi" - -/ { - compatible = "ralink,mt7620a-soc"; - model = "Planex CS-QR10"; - - sound { - compatible = "mediatek,mt7620-audio-wm8960"; - model = "mt7620-wm8960"; - i2s-controller = <&i2s>; - audio-routing = - "Ext Spk", "SPK_LP", - "Ext Spk", "SPK_LN", - "Ext Spk", "SPK_RP", - "Ext Spk", "SPK_RN"; - }; - - gpio-leds { - compatible = "gpio-leds"; - - power { - label = "cs-qr10:red:power"; - gpios = <&gpio1 4 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - s1 { - label = "reset"; - gpios = <&gpio1 1 1>; - linux,code = <0x198>; - }; - - s2 { - label = "wps"; - gpios = <&gpio1 3 1>; - linux,code = <0x211>; - }; - }; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&gpio2 { - status = "okay"; -}; - -&gpio3 { - status = "okay"; -}; - -&i2c { - status = "okay"; -}; - -&i2s { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pcm_i2s_pins>; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80", "mx25l6405d"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x7b0000>; - }; - }; -}; - -&pcm { - status = "okay"; -}; - -&gdma { - status = "okay"; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "spi refclk", "rgmii1"; - ralink,function = "gpio"; - }; - wdt { - ralink,group = "wdt"; - ralink,function = "wdt refclk"; - }; - }; -}; - -ðernet { - pinctrl-names = "default"; - pinctrl-0 = <&ephy_pins>; - mtd-mac-address = <&factory 0x4>; - mediatek,portmap = "llllw"; -}; - -&gsw { - ralink,port4 = "ephy"; -}; - -&sdhci { - status = "okay"; -}; - -&ehci { - status = "okay"; -}; - -&ohci { - status = "okay"; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; - -&pcie { - status = "okay"; -}; diff --git a/sys/gnu/dts/mips/CY-SWR1100.dts b/sys/gnu/dts/mips/CY-SWR1100.dts deleted file mode 100644 index 031d8f00523..00000000000 --- a/sys/gnu/dts/mips/CY-SWR1100.dts +++ /dev/null @@ -1,150 +0,0 @@ -/dts-v1/; - -#include "rt3883.dtsi" - -/ { - compatible = "CY-SWR1100", "ralink,rt3883-soc"; - model = "Samsung CY-SWR1100"; - - nor-flash@1c000000 { - compatible = "cfi-flash"; - reg = <0x1c000000 0x800000>; - bank-width = <2>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "uboot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "uboot-env"; - reg = <0x30000 0x4000>; - read-only; - }; - - factory: partition@34000 { - label = "factory"; - reg = <0x34000 0x4000>; - read-only; - }; - - partition@38000 { - label = "nvram"; - reg = <0x38000 0x8000>; - read-only; - }; - - partition@40000 { - label = "devdata"; - reg = <0x40000 0x10000>; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x7b0000>; - }; - }; - - rtl8367 { - compatible = "realtek,rtl8367"; - gpio-sda = <&gpio0 1 0>; - gpio-sck = <&gpio0 2 0>; - realtek,extif0 = <1 0 1 1 1 1 1 1 2>; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <100>; - - reset { - label = "reset"; - gpios = <&gpio0 6 1>; - linux,code = <0x198>; - }; - - wps { - label = "wps"; - gpios = <&gpio0 3 1>; - linux,code = <0x211>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - wps { - label = "cy-swr1100:blue:wps"; - gpios = <&gpio0 0 1>; - }; - - usb { - label = "cy-swr1100:blue:usb"; - gpios = <&gpio1 1 1>; - }; - }; -}; - -&gpio1 { - status = "okay"; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "spi"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - port@0 { - mediatek,fixed-link = <1000 1 1 1>; - phy-mode = "rgmii"; - }; -}; - -&pci { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pci_pins>; - - pci_pins: pci { - pci { - ralink,group = "pci"; - ralink,function = "pci-fnc"; - }; - }; - - host-bridge { - pci-bridge@1 { - status = "okay"; - - wmac@0,0 { - ralink,5ghz = <0>; - compatible = "ralink,rt2880-pci", "pciclass060400", "pciclass0604"; - reg = < 0x10000 0 0 0 0 >; - ralink,eeprom = "rt2x00pci_1_0.eeprom"; - }; - }; - }; -}; - -&wmac { - status = "okay"; - ralink,2ghz = <0>; - ralink,mtd-eeprom = <&factory 0>; -}; - -&ehci { - status = "okay"; -}; - -&ohci { - status = "okay"; -}; diff --git a/sys/gnu/dts/mips/D105.dts b/sys/gnu/dts/mips/D105.dts deleted file mode 100644 index 2e86d1edac2..00000000000 --- a/sys/gnu/dts/mips/D105.dts +++ /dev/null @@ -1,92 +0,0 @@ -/dts-v1/; - -#include "rt3050.dtsi" - -/ { - compatible = "D105", "ralink,rt3050-soc"; - model = "Huawei D105"; - - cfi@1f000000 { - compatible = "cfi-flash"; - reg = <0x1f000000 0x800000>; - bank-width = <2>; - device-width = <2>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x3b0000>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - power { - label = "d105:red:power"; - gpios = <&gpio0 0 1>; - }; - - wps { - label = "d105:green:usb"; - gpios = <&gpio0 13 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio0 10 1>; - linux,code = <0x198>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - mtd-mac-address = <&factory 0x4>; -}; - -&esw { - mediatek,portmap = <0x2f>; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; - -&otg { - status = "okay"; -}; diff --git a/sys/gnu/dts/mips/DAP-1350.dts b/sys/gnu/dts/mips/DAP-1350.dts deleted file mode 100644 index 4628544fb6a..00000000000 --- a/sys/gnu/dts/mips/DAP-1350.dts +++ /dev/null @@ -1,125 +0,0 @@ -/dts-v1/; - -#include "rt3050.dtsi" - -/ { - compatible = "DAP-1350", "ralink,rt3052-soc"; - model = "D-Link DAP-1350"; - - chosen { - bootargs = "console=ttyS0,115200"; - }; - - cfi@1f000000 { - compatible = "cfi-flash"; - reg = <0x1f000000 0x800000>; - bank-width = <2>; - device-width = <2>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - devdata: partition@30000 { - label = "devdata"; - reg = <0x30000 0x10000>; - read-only; - }; - - partition@40000 { - label = "devconf"; - reg = <0x40000 0x30000>; - read-only; - }; - - partition@70000 { - label = "devlang"; - reg = <0x70000 0x40000>; - read-only; - }; - - partition@b0000 { - label = "firmware"; - reg = <0xb0000 0x750000>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - power { - label = "dap-1350:blue:power"; - gpios = <&gpio0 8 1>; - }; - - power2 { - label = "dap-1350:red:power"; - gpios = <&gpio0 9 1>; - }; - - wps { - label = "dap-1350:blue:wps"; - gpios = <&gpio0 14 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio0 10 1>; - linux,code = <0x198>; - }; - - wps { - label = "wps"; - gpios = <&gpio0 0 1>; - linux,code = <0x211>; - }; - - rt { - label = "rt"; - gpios = <&gpio0 11 1>; - linux,code = <0x100>; - }; - - ap { - label = "ap"; - gpios = <&gpio0 7 1>; - linux,code = <0x101>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - mtd-mac-address = <&devdata 0x2e>; -}; - -&esw { - mediatek,portmap = <0x2f>; -}; - -&wmac { - ralink,mtd-eeprom = <&devdata 0>; -}; - -&otg { - status = "okay"; -}; diff --git a/sys/gnu/dts/mips/DB-WRT01.dts b/sys/gnu/dts/mips/DB-WRT01.dts deleted file mode 100644 index 4560dc5ca84..00000000000 --- a/sys/gnu/dts/mips/DB-WRT01.dts +++ /dev/null @@ -1,98 +0,0 @@ -/dts-v1/; - -#include "mt7620a.dtsi" - -/ { - compatible = "ralink,mt7620a-soc"; - model = "Planex DB-WRT01"; - - gpio-leds { - compatible = "gpio-leds"; - - power { - label = "db-wrt01:orange:power"; - gpios = <&gpio1 1 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - s1 { - label = "wps"; - gpios = <&gpio0 2 1>; - linux,code = <0x211>; - }; - }; -}; - -&gpio1 { - status = "okay"; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80", "mx25l6405d"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x7b0000>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "spi refclk", "rgmii1"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - pinctrl-names = "default"; - pinctrl-0 = <&ephy_pins>; - mtd-mac-address = <&factory 0x4>; - mediatek,portmap = "llllw"; -}; - -&gsw { - mediatek,port4 = "ephy"; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; - -&pcie { - status = "okay"; -}; diff --git a/sys/gnu/dts/mips/DCS-930.dts b/sys/gnu/dts/mips/DCS-930.dts deleted file mode 100644 index 373973c3df8..00000000000 --- a/sys/gnu/dts/mips/DCS-930.dts +++ /dev/null @@ -1,113 +0,0 @@ -/dts-v1/; - -#include "rt3050.dtsi" - -/ { - compatible = "DCS-930", "ralink,rt3050-soc"; - model = "D-Link DCS-930"; - - cfi@1f000000 { - compatible = "cfi-flash"; - reg = <0x1f000000 0x400000>; - bank-width = <2>; - device-width = <2>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "kernel"; - reg = <0x50000 0x150000>; - }; - - partition@150000 { - label = "rootfs"; - reg = <0x150000 0x2b0000>; - }; - - partition { - label = "firmware"; - reg = <0x50000 0x3b0000>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - wifi { - label = "dcs-930:red:alert"; - gpios = <&gpio0 8 1>; - }; - - power { - label = "dcs-930:green:status"; - gpios = <&gpio0 9 1>; - }; - - wps { - label = "dcs-930:blue:wps"; - gpios = <&gpio0 13 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - wps { - label = "wps"; - gpios = <&gpio0 0 1>; - linux,code = <0x101>; - }; - - reset { - label = "reset"; - gpios = <&gpio0 10 1>; - linux,code = <0x198>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "spi", "jtag", "mdio", "rgmii", "uartf"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - mtd-mac-address = <&factory 0x4>; -}; - -&esw { - mediatek,portmap = <0x2f>; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; - -&otg { - status = "okay"; -}; diff --git a/sys/gnu/dts/mips/DCS-930L-B1.dts b/sys/gnu/dts/mips/DCS-930L-B1.dts deleted file mode 100644 index 133245cb74b..00000000000 --- a/sys/gnu/dts/mips/DCS-930L-B1.dts +++ /dev/null @@ -1,106 +0,0 @@ -/dts-v1/; - -#include "rt5350.dtsi" - -/ { - compatible = "DCS-930L-B1", "ralink,rt5350-soc"; - model = "D-Link DCS-930L B1"; - - gpio-leds { - compatible = "gpio-leds"; - - power { - label = "dcs-930l-b1:red:power"; - gpios = <&gpio0 17 1>; - }; - - wps { - label = "dcs-930l-b1:blue:wps"; - gpios = <&gpio0 19 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio0 0 1>; - linux,code = <0x198>; - }; - - wps { - label = "wps"; - gpios = <&gpio0 20 1>; - linux,code = <0x211>; - }; - }; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80", "s25fl064k"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x3b0000>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "jtag", "uartf", "led"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - mtd-mac-address = <&factory 0x4>; -}; - -&esw { - mediatek,portmap = <0x2f>; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; - -&ehci { - status = "okay"; -}; - -&ohci { - status = "okay"; -}; diff --git a/sys/gnu/dts/mips/DIR-300-B1.dts b/sys/gnu/dts/mips/DIR-300-B1.dts deleted file mode 100644 index 4f0a7ffde75..00000000000 --- a/sys/gnu/dts/mips/DIR-300-B1.dts +++ /dev/null @@ -1,109 +0,0 @@ -/dts-v1/; - -#include "rt3050.dtsi" - -/ { - compatible = "DIR-300-B1", "ralink,rt3050-soc"; - model = "D-Link DIR-300 B1"; - - cfi@1f000000 { - compatible = "cfi-flash"; - reg = <0x1f000000 0x800000>; - bank-width = <2>; - device-width = <2>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - devdata: partition@30000 { - label = "devdata"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "devconf"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x3b0000>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio0 10 1>; - linux,code = <0x198>; - }; - - wps { - label = "wps"; - gpios = <&gpio0 0 1>; - linux,code = <0x211>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - status { - label = "dir-300-b1:amber:status"; - gpios = <&gpio0 8 1>; - }; - - status2 { - label = "dir-300-b1:green:status"; - gpios = <&gpio0 9 1>; - }; - - wan { - label = "dir-300-b1:amber:wan"; - gpios = <&gpio0 14 1>; - }; - - wan2 { - label = "dir-300-b1:green:wan"; - gpios = <&gpio0 12 1>; - }; - - wps { - label = "dir-300-b1:blue:wps"; - gpios = <&gpio0 13 1>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "spi", "jtag", "mdio", "rgmii", "uartf"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - mtd-mac-address = <&devdata 0x4004>; -}; - -&esw { - mediatek,portmap = <0x2f>; -}; - -&wmac { - ralink,mtd-eeprom = <&devdata 0x4000>; -}; diff --git a/sys/gnu/dts/mips/DIR-300-B7.dts b/sys/gnu/dts/mips/DIR-300-B7.dts deleted file mode 100644 index 9b9a6a45926..00000000000 --- a/sys/gnu/dts/mips/DIR-300-B7.dts +++ /dev/null @@ -1,101 +0,0 @@ -/dts-v1/; - -#include "rt5350.dtsi" - -/ { - compatible = "DIR-300-B7", "ralink,rt5350-soc"; - model = "D-Link DIR-300 B7"; - - gpio-leds { - compatible = "gpio-leds"; - - status { - label = "dir-300-b7:green:status"; - gpios = <&gpio0 9 1>; - }; - - wps { - label = "dir-300-b7:blue:wps"; - gpios = <&gpio0 13 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio0 10 1>; - linux,code = <0x198>; - }; - - wps { - label = "wps"; - gpios = <&gpio0 0 1>; - linux,code = <0x211>; - }; - }; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80", "s25fl064k"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x7b0000>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - mtd-mac-address = <&factory 0x4>; -}; - -&esw { - mediatek,portmap = <0x2f>; - mediatek,led_polarity = <0x17>; -}; - -&wmac { - status = "okay"; - ralink,led-polarity = <1>; - ralink,mtd-eeprom = <&factory 0>; -}; diff --git a/sys/gnu/dts/mips/DIR-320-B1.dts b/sys/gnu/dts/mips/DIR-320-B1.dts deleted file mode 100644 index 102e06abf9a..00000000000 --- a/sys/gnu/dts/mips/DIR-320-B1.dts +++ /dev/null @@ -1,129 +0,0 @@ -/dts-v1/; - -#include "rt5350.dtsi" - -/ { - compatible = "DIR-320-B1", "ralink,rt5350-soc"; - model = "D-Link DIR-320 B1"; - - gpio-leds { - compatible = "gpio-leds"; - - status { - label = "dir-320-b1:green:status"; - gpios = <&gpio0 9 1>; - }; - - usb { - label = "dir-320-b1:green:usb"; - gpios = <&gpio0 14 1>; - }; - - wps { - label = "dir-320-b1:green:wps"; - gpios = <&gpio0 13 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio0 10 1>; - linux,code = <0x198>; - }; - - wps { - label = "wps"; - gpios = <&gpio0 0 1>; - linux,code = <0x211>; - }; - }; - - gpio_export { - compatible = "gpio-export"; - #size-cells = <0>; - - usb { - gpio-export,name = "usb"; - gpio-export,output = <1>; - gpios = <&gpio0 7 0>; - }; - - root_hub { - gpio-export,name = "root_hub"; - gpio-export,output = <1>; - gpios = <&gpio0 12 0>; - }; - }; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80", "s25fl064k"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x7b0000>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - mtd-mac-address = <&factory 0x4>; -}; - -&esw { - mediatek,portmap = <0x2f>; - mediatek,led_polarity = <0x17>; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; - -&ehci { - status = "okay"; -}; - -&ohci { - status = "okay"; -}; diff --git a/sys/gnu/dts/mips/DIR-600-B1.dts b/sys/gnu/dts/mips/DIR-600-B1.dts deleted file mode 100644 index d45d3c5ccdf..00000000000 --- a/sys/gnu/dts/mips/DIR-600-B1.dts +++ /dev/null @@ -1,109 +0,0 @@ -/dts-v1/; - -#include "rt3050.dtsi" - -/ { - compatible = "DIR-600-B1", "ralink,rt3050-soc"; - model = "D-Link DIR-600 B1"; - - cfi@1f000000 { - compatible = "cfi-flash"; - reg = <0x1f000000 0x800000>; - bank-width = <2>; - device-width = <2>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - devdata: partition@30000 { - label = "devdata"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "devconf"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x3b0000>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio0 10 1>; - linux,code = <0x198>; - }; - - wps { - label = "wps"; - gpios = <&gpio0 0 1>; - linux,code = <0x211>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - status { - label = "dir-600-b1:amber:status"; - gpios = <&gpio0 8 1>; - }; - - status2 { - label = "dir-600-b1:green:status"; - gpios = <&gpio0 9 1>; - }; - - wan { - label = "dir-600-b1:amber:wan"; - gpios = <&gpio0 14 1>; - }; - - wan2 { - label = "dir-600-b1:green:wan"; - gpios = <&gpio0 12 1>; - }; - - wps { - label = "dir-600-b1:blue:wps"; - gpios = <&gpio0 13 1>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "spi", "jtag", "mdio", "rgmii", "uartf"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - mtd-mac-address = <&devdata 0x4004>; -}; - -&esw { - mediatek,portmap = <0x2f>; -}; - -&wmac { - ralink,mtd-eeprom = <&devdata 0x4000>; -}; diff --git a/sys/gnu/dts/mips/DIR-600-B2.dts b/sys/gnu/dts/mips/DIR-600-B2.dts deleted file mode 100644 index f0269cfa2e5..00000000000 --- a/sys/gnu/dts/mips/DIR-600-B2.dts +++ /dev/null @@ -1,105 +0,0 @@ -/dts-v1/; - -#include "rt3050.dtsi" - -/ { - compatible = "DIR-600-B2", "ralink,rt3050-soc"; - model = "D-Link DIR-600 B2"; - - cfi@1f000000 { - compatible = "cfi-flash"; - reg = <0x1f000000 0x800000>; - bank-width = <2>; - device-width = <2>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - devdata: partition@30000 { - label = "devdata"; - reg = <0x30000 0x10000>; - read-only; - }; - - partition@40000 { - label = "devconf"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x3b0000>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio0 10 1>; - linux,code = <0x198>; - }; - - wps { - label = "wps"; - gpios = <&gpio0 0 1>; - linux,code = <0x211>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - status { - label = "dir-600-b2:amber:status"; - gpios = <&gpio0 8 1>; - }; - - status2 { - label = "dir-600-b2:green:status"; - gpios = <&gpio0 9 1>; - }; - - wan { - label = "dir-600-b2:amber:wan"; - gpios = <&gpio0 14 1>; - }; - - wan2 { - label = "dir-600-b2:green:wan"; - gpios = <&gpio0 12 1>; - }; - - wps { - label = "dir-600-b2:blue:wps"; - gpios = <&gpio0 13 1>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "spi", "jtag", "mdio", "rgmii", "uartf"; - ralink,function = "gpio"; - }; - }; -}; - -&esw { - mediatek,portmap = <0x2f>; -}; - -&wmac { - ralink,mtd-eeprom = <&devdata 0x4000>; -}; diff --git a/sys/gnu/dts/mips/DIR-610-A1.dts b/sys/gnu/dts/mips/DIR-610-A1.dts deleted file mode 100644 index 9ec66b4b003..00000000000 --- a/sys/gnu/dts/mips/DIR-610-A1.dts +++ /dev/null @@ -1,102 +0,0 @@ -/dts-v1/; - -#include "rt5350.dtsi" - -/ { - compatible = "DIR-610-A1", "ralink,rt5350-soc"; - model = "D-Link DIR-610 A1"; - - gpio-leds { - compatible = "gpio-leds"; - - status { - label = "dir-610-a1:green:status"; - gpios = <&gpio0 9 1>; - }; - - wps { - label = "dir-610-a1:green:wps"; - gpios = <&gpio0 13 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio0 10 1>; - linux,code = <0x198>; - }; - - wps { - label = "wps"; - gpios = <&gpio0 0 1>; - linux,code = <0x211>; - }; - }; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - devdata: partition@30000 { - label = "devdata"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x3b0000>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "jtag", "uartf"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - mtd-mac-address = <&devdata 0x4004>; -}; - -&esw { - status = "okay"; - mediatek,portmap = <0x2f>; - mediatek,led_polarity = <0x17>; -}; - -&wmac { - status = "okay"; - ralink,led-polarity = <1>; - ralink,mtd-eeprom = <&devdata 0x4000>; -}; diff --git a/sys/gnu/dts/mips/DIR-615-D.dts b/sys/gnu/dts/mips/DIR-615-D.dts deleted file mode 100644 index cac9d2602cb..00000000000 --- a/sys/gnu/dts/mips/DIR-615-D.dts +++ /dev/null @@ -1,107 +0,0 @@ -/dts-v1/; - -#include "rt3050.dtsi" - -/ { - compatible = "DIR-615-D", "ralink,rt3050-soc"; - model = "D-Link DIR-615 D"; - - cfi@1f000000 { - compatible = "cfi-flash"; - reg = <0x1f000000 0x800000>; - bank-width = <2>; - device-width = <2>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - devdata: partition@30000 { - label = "devdata"; - reg = <0x30000 0x10000>; - read-only; - }; - - partition@40000 { - label = "devconf"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x3b0000>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio0 10 1>; - linux,code = <0x198>; - }; - - wps { - label = "wps"; - gpios = <&gpio0 0 1>; - linux,code = <0x211>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - status { - label = "dir-615-d:amber:status"; - gpios = <&gpio0 8 1>; - }; - - status2 { - label = "dir-615-d:green:status"; - gpios = <&gpio0 9 1>; - }; - - wan { - label = "dir-615-d:amber:wan"; - gpios = <&gpio0 14 1>; - }; - - wan2 { - label = "dir-615-d:green:wan"; - gpios = <&gpio0 12 1>; - }; - - wps { - label = "dir-615-d:blue:wps"; - gpios = <&gpio0 13 1>; - }; - }; -}; - -&esw { - mediatek,portmap = <0x2f>; -}; - -&wmac { - ralink,mtd-eeprom = <&devdata 0x4000>; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "spi", "jtag", "mdio", "rgmii", "uartf"; - ralink,function = "gpio"; - }; - }; -}; - - diff --git a/sys/gnu/dts/mips/DIR-615-H1.dts b/sys/gnu/dts/mips/DIR-615-H1.dts deleted file mode 100644 index d53c82609f0..00000000000 --- a/sys/gnu/dts/mips/DIR-615-H1.dts +++ /dev/null @@ -1,123 +0,0 @@ -/dts-v1/; - -#include "rt3352.dtsi" - -/ { - compatible = "DIR-615-H1", "ralink,rt3352-soc"; - model = "D-Link DIR-615 H1"; - - gpio-leds { - compatible = "gpio-leds"; - - status { - label = "dir-615-h1:amber:status"; - gpios = <&gpio0 7 0>; - }; - - status2 { - label = "dir-615-h1:green:status"; - gpios = <&gpio0 9 0>; - }; - - wan { - label = "dir-615-h1:amber:wan"; - gpios = <&gpio0 12 1>; - }; - - wan2 { - label = "dir-615-h1:green:wan"; - gpios = <&gpio0 13 1>; - }; - - wps { - label = "dir-615-h1:blue:wps"; - gpios = <&gpio0 14 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio0 10 1>; - linux,code = <0x198>; - }; - - wps { - label = "wps"; - gpios = <&gpio0 0 1>; - linux,code = <0x211>; - }; - }; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80", "mx25l3205d"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x3b0000>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "jtag", "uartf"; - ralink,function = "gpio"; - }; - - rgmii { - ralink,group = "rgmii"; - ralink,function = "rgmii"; - }; - - mdio { - ralink,group = "mdio"; - ralink,function = "mdio"; - }; - }; -}; - -ðernet { - mtd-mac-address = <&factory 0x28>; -}; - -&esw { - mediatek,portmap = <0x2f>; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; diff --git a/sys/gnu/dts/mips/DIR-620-A1.dts b/sys/gnu/dts/mips/DIR-620-A1.dts deleted file mode 100644 index 68a23465a64..00000000000 --- a/sys/gnu/dts/mips/DIR-620-A1.dts +++ /dev/null @@ -1,118 +0,0 @@ -/dts-v1/; - -#include "rt3050.dtsi" - -/ { - compatible = "DIR-620-A1", "ralink,rt3050-soc"; - model = "D-Link DIR-620 A1"; - - cfi@1f000000 { - compatible = "cfi-flash"; - reg = <0x1f000000 0x800000>; - bank-width = <2>; - device-width = <2>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x7b0000>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio0 10 1>; - linux,code = <0x198>; - }; - - wps { - label = "wps"; - gpios = <&gpio0 0 1>; - linux,code = <0x211>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - status { - label = "dir-620-a1:amber:status"; - gpios = <&gpio0 8 1>; - }; - - status2 { - label = "dir-620-a1:green:status"; - gpios = <&gpio0 9 1>; - }; - - wan { - label = "dir-620-a1:amber:wan"; - gpios = <&gpio0 14 1>; - }; - - wan2 { - label = "dir-620-a1:green:wan"; - gpios = <&gpio0 12 1>; - }; - - wps { - label = "dir-620-a1:blue:wps"; - gpios = <&gpio0 13 0>; - }; - - wps2 { - label = "dir-620-a1:amber:wps"; - gpios = <&gpio0 11 0>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - mtd-mac-address = <&factory 0x4>; -}; - -&esw { - mediatek,portmap = <0x2f>; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; - -&otg { - status = "okay"; -}; diff --git a/sys/gnu/dts/mips/DIR-620-D1.dts b/sys/gnu/dts/mips/DIR-620-D1.dts deleted file mode 100644 index 5cf330e66bb..00000000000 --- a/sys/gnu/dts/mips/DIR-620-D1.dts +++ /dev/null @@ -1,110 +0,0 @@ -/dts-v1/; - -#include "rt3352.dtsi" - -/ { - compatible = "DIR-620-D1", "ralink,rt3352-soc"; - model = "D-Link DIR-620 D1"; - - gpio-leds { - compatible = "gpio-leds"; - - status { - label = "dir-620-d1:green:status"; - gpios = <&gpio0 9 1>; - }; - - wifi { - label = "dir-620-d1:green:wifi"; - gpios = <&gpio0 17 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset_wps { - label = "reset_wps"; - gpios = <&gpio0 7 1>; - linux,code = <0x198>; - }; - }; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80", "mx25l6405d"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x7b0000>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "jtag", "uartf"; - ralink,function = "gpio"; - }; - - rgmii { - ralink,group = "rgmii"; - ralink,function = "rgmii"; - }; - - mdio { - ralink,group = "mdio"; - ralink,function = "mdio"; - }; - }; -}; - -ðernet { - mtd-mac-address = <&factory 0x4>; -}; - -&esw { - mediatek,portmap = <0x2f>; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; - -&ehci { - status = "okay"; -}; - -&ohci { - status = "okay"; -}; diff --git a/sys/gnu/dts/mips/DIR-645.dts b/sys/gnu/dts/mips/DIR-645.dts deleted file mode 100644 index d508297ac18..00000000000 --- a/sys/gnu/dts/mips/DIR-645.dts +++ /dev/null @@ -1,140 +0,0 @@ -/dts-v1/; - -#include "rt3883.dtsi" - -/ { - compatible = "DIR-645", "ralink,rt3883-soc"; - model = "D-Link DIR-645"; - - rtl8367b { - compatible = "realtek,rtl8367b"; - gpio-sda = <&gpio0 1 0>; - gpio-sck = <&gpio0 2 0>; - realtek,extif1 = <1 0 1 1 1 1 1 1 2>; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <100>; - - reset { - label = "reset"; - gpios = <&gpio0 9 0>; - linux,code = <0x198>; - }; - - wps { - label = "wps"; - gpios = <&gpio0 14 0>; - linux,code = <0x211>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - inet { - label = "dir-645:green:inet"; - gpios = <&gpio0 0 1>; - }; - - wps { - label = "dir-645:green:wps"; - gpios = <&gpio1 2 0>; - }; - }; - - gpio_export { - compatible = "gpio-export"; - #size-cells = <0>; - - usb { - gpio-export,name = "usb"; - gpio-export,output = <1>; - gpios = <&gpio1 6 0>; - }; - }; -}; - -&gpio1 { - status = "okay"; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80"; - spi-max-frequency = <25000000>; - - partition@0 { - label = "uboot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "uboot-env"; - reg = <0x30000 0x4000>; - read-only; - }; - - factory: partition@34000 { - label = "factory"; - reg = <0x34000 0x4000>; - read-only; - }; - - partition@38000 { - label = "nvram"; - reg = <0x38000 0x8000>; - read-only; - }; - - partition@40000 { - label = "devdata"; - reg = <0x40000 0x10000>; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x7b0000>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "jtag", "uartf"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - mtd-mac-address = <&factory 0x4>; - - port@0 { - mediatek,fixed-link = <1000 1 1 0>; - }; -}; - -&wmac { - ralink,5ghz = <0>; - ralink,mtd-eeprom = <&factory 0>; -}; - -&ehci { - status = "okay"; -}; - -&ohci { - status = "okay"; -}; diff --git a/sys/gnu/dts/mips/DIR-810L.dts b/sys/gnu/dts/mips/DIR-810L.dts deleted file mode 100644 index 1f9ad8a5d2d..00000000000 --- a/sys/gnu/dts/mips/DIR-810L.dts +++ /dev/null @@ -1,134 +0,0 @@ -/dts-v1/; - -#include "mt7620a.dtsi" - -/ { - compatible = "dlink,dir-810l", "ralink,mt7620a-soc"; - model = "D-Link DIR-810L"; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio0 1 1>; - linux,code = <0x100>; - }; - - wps { - label = "wps"; - gpios = <&gpio0 2 1>; - linux,code = <0x100>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - power { - label = "dir-810l:green:power"; - gpios = <&gpio0 9 0>; - }; - - wan { - label = "dir-810l:orange:wan"; - gpios = <&gpio0 12 0>; - }; - - status { - label = "dir-810l:orange:power"; - gpios = <&gpio0 13 0>; - }; - }; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - factory5g: partition@50000 { - label = "factory5g"; - reg = <0x50000 0x10000>; - read-only; - }; - - partition@60000 { - label = "Wolf_Config"; - reg = <0x60000 0x10000>; - read-only; - }; - - partition@70000 { - label = "MyDlink"; - reg = <0x70000 0x80000>; - read-only; - }; - - partition@e0000 { - label = "Jffs2"; - reg = <0xe0000 0x80000>; - read-only; - }; - - partition@170000 { - label = "firmware"; - reg = <0x170000 0x690000>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "mdio", "rgmii1", "i2c", "wled", "uartf"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - mtd-mac-address = <&factory 0x28>; - mediatek,portmap = "llllw"; -}; - -&gsw { - mediatek,port4 = "ephy"; - pinctrl-names = "default"; - pinctrl-0 = <&ephy_pins>; -}; - -&pcie { - status = "okay"; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; diff --git a/sys/gnu/dts/mips/DIR-860L-B1.dts b/sys/gnu/dts/mips/DIR-860L-B1.dts deleted file mode 100644 index b6336d87d35..00000000000 --- a/sys/gnu/dts/mips/DIR-860L-B1.dts +++ /dev/null @@ -1,127 +0,0 @@ -/dts-v1/; - -#include "mt7621.dtsi" - -/ { - compatible = "ralink,mt7621-eval-board", "ralink,mt7621-soc"; - model = "D-Link DIR-860L B1"; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x8000000>; - }; - - chosen { - bootargs = "console=ttyS0,57600"; - }; - - gpio-leds { - compatible = "gpio-leds"; - - power { - label = "dir-860l-b1:orange:power"; - gpios = <&gpio0 13 1>; - }; - - power2 { - label = "dir-860l-b1:green:power"; - gpios = <&gpio0 15 1>; - }; - - net { - label = "dir-860l-b1:orange:net"; - gpios = <&gpio0 14 1>; - }; - - net2 { - label = "dir-860l-b1:green:net"; - gpios = <&gpio0 16 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - }; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x4000>; - read-only; - }; - - radio: partition@34000 { - label = "radio"; - reg = <0x34000 0x4000>; - read-only; - }; - - factory: partition@38000 { - label = "factory"; - reg = <0x38000 0x8000>; - read-only; - }; - - partition@40000 { - label = "defaults"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0xfb0000>; - }; - }; -}; - -&pcie { - status = "okay"; - - pcie0 { - mt76@0,0 { - reg = <0x0000 0 0 0 0>; - device_type = "pci"; - mediatek,mtd-eeprom = <&radio 0x2000>; - mediatek,2ghz = <0>; - }; - }; - - pcie1 { - mt76@1,0 { - reg = <0x0000 0 0 0 0>; - device_type = "pci"; - mediatek,mtd-eeprom = <&radio 0>; - mediatek,5ghz = <0>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "uart2", "uart3", "rgmii2", "sdhci"; - ralink,function = "gpio"; - }; - }; -}; diff --git a/sys/gnu/dts/mips/E1700.dts b/sys/gnu/dts/mips/E1700.dts deleted file mode 100644 index 36126ab42b0..00000000000 --- a/sys/gnu/dts/mips/E1700.dts +++ /dev/null @@ -1,152 +0,0 @@ -/* - * Device Tree file for the Linksys E1700 - * - * Copyright (C) 2014 Imre Kaloz - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -/dts-v1/; - -#include "mt7620a.dtsi" - -/ { - compatible = "linksys,e1700", "ralink,mt7620a-soc"; - model = "Linksys E1700"; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio0 1 0>; - linux,code = <0x198>; - }; - - wps { - label = "wps"; - gpios = <&gpio0 2 0>; - linux,code = <0x211>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - power { - label = "e1700:green:power"; - gpios = <&gpio0 10 1>; - }; - - wan { - label = "e1700:green:wps"; - gpios = <&gpio0 12 1>; - }; - }; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80", "mx25l6405d"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "config"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x7b0000>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "uartf"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - status = "okay"; - mtd-mac-address = <&factory 0x28>; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>; - - port@5 { - status = "okay"; - mediatek,fixed-link = <1000 1 1 1>; - phy-mode = "rgmii"; - }; - - mdio-bus { - status = "okay"; - - phy0: ethernet-phy@0 { - reg = <0>; - phy-mode = "rgmii"; - }; - - phy1: ethernet-phy@1 { - reg = <1>; - phy-mode = "rgmii"; - }; - - phy2: ethernet-phy@2 { - reg = <2>; - phy-mode = "rgmii"; - }; - - phy3: ethernet-phy@3 { - reg = <3>; - phy-mode = "rgmii"; - }; - - phy4: ethernet-phy@4 { - reg = <4>; - phy-mode = "rgmii"; - }; - - phy1f: ethernet-phy@1f { - reg = <0x1f>; - phy-mode = "rgmii"; - }; - }; -}; - -&gsw { - mediatek,port4 = "gmac"; - mediatek,mt7530 = <1>; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; diff --git a/sys/gnu/dts/mips/ESR-9753.dts b/sys/gnu/dts/mips/ESR-9753.dts deleted file mode 100644 index 68691667874..00000000000 --- a/sys/gnu/dts/mips/ESR-9753.dts +++ /dev/null @@ -1,94 +0,0 @@ -/dts-v1/; - -#include "rt3050.dtsi" - -/ { - compatible = "ESR-9753", "ralink,rt3052-soc"; - model = "Senao / EnGenius ESR-9753"; - - cfi@1f000000 { - compatible = "cfi-flash"; - reg = <0x1f000000 0x800000>; - bank-width = <2>; - device-width = <2>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x3b0000>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - power { - label = "esr-9753:orange:power"; - gpios = <&gpio0 8 1>; - }; - - wps { - label = "esr-9753:orange:wps"; - gpios = <&gpio0 14 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio0 10 1>; - linux,code = <0x198>; - }; - - wps { - label = "wps"; - gpios = <&gpio0 0 1>; - linux,code = <0x211>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - mtd-mac-address = <&factory 0x4>; -}; - -&esw { - mediatek,portmap = <0x3e>; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; diff --git a/sys/gnu/dts/mips/EX2700.dts b/sys/gnu/dts/mips/EX2700.dts deleted file mode 100644 index c711adc6b4e..00000000000 --- a/sys/gnu/dts/mips/EX2700.dts +++ /dev/null @@ -1,145 +0,0 @@ -/* - * Device Tree file for the Netgear EX2700 - * - * Copyright (C) 2016 Joseph C. Lehner - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -/dts-v1/; - -#include "mt7620a.dtsi" - -/ { - compatible = "ralink,mt7620a-soc"; - model = "Netgear EX2700"; - - chosen { - bootargs = "console=ttyS0,57600"; - }; - - gpio-leds { - compatible = "gpio-leds"; - - power_g { - label = "ex2700:green:power"; - gpios = <&gpio0 9 1>; - default-state = "on"; - }; - - power_r { - label = "ex2700:red:power"; - gpios = <&gpio0 11 1>; - }; - - device_g { - label = "ex2700:green:device"; - gpios = <&gpio0 13 1>; - }; - - device_r { - label = "ex2700:red:device"; - gpios = <&gpio0 10 1>; - }; - - router_g { - label = "ex2700:green:router"; - gpios = <&gpio0 12 1>; - }; - - router_r { - label = "ex2700:red:router"; - gpios = <&gpio0 14 1>; - }; - - wps { - label = "ex2700:green:wps"; - gpios = <&gpio1 15 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio0 1 1>; - linux,code = <0x198>; - }; - - wps { - label = "wps"; - gpios = <&gpio0 2 1>; - linux,code = <0x211>; - }; - }; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80", "mx25l3205d"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - partition@40000 { - label = "firmware"; - reg = <0x40000 0x3b0000>; - }; - - art: partition@3f0000 { - label = "art"; - reg = <0x3f0000 0x10000>; - read-only; - }; - }; -}; - -ðernet { - mtd-mac-address = <&art 0x0>; -}; - -&wmac { - ralink,mtd-eeprom = <&art 0x1000>; -}; - -&pinctrl { - state_default: pinctrl0 { - default { - // spi refclk: pins 37, 38, 39 - // uartf: pins 8, 9, 10, 11, 12, 13, 14 - // i2c: pins 1, 2 - ralink,group = "i2c", "uartf", "spi refclk"; - ralink,function = "gpio"; - }; - }; -}; diff --git a/sys/gnu/dts/mips/F5D8235_V1.dts b/sys/gnu/dts/mips/F5D8235_V1.dts deleted file mode 100644 index dacdea6ca40..00000000000 --- a/sys/gnu/dts/mips/F5D8235_V1.dts +++ /dev/null @@ -1,111 +0,0 @@ -/dts-v1/; - -#include "rt2880.dtsi" - -/ { - #address-cells = <1>; - #size-cells = <1>; - compatible = "F5D8235_V1", "ralink,rt2880-soc"; - model = "Belkin F5D8235 v1"; - - cfi@1f000000 { - compatible = "cfi-flash"; - reg = <0x1f000000 0x800000>; - bank-width = <2>; - device-width = <2>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "uboot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "uboot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "linux"; - reg = <0x50000 0x3b0000>; - }; - }; - - rtl8366s { - compatible = "realtek,rtl8366s"; - gpio-sda = <&gpio0 1 0>; - gpio-sck = <&gpio0 2 0>; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <100>; - - wps { - label = "wps"; - gpios = <&gpio0 0 1>; - linux,code = <0x211>; - }; - - reset { - label = "reset"; - gpios = <&gpio0 9 1>; - linux,code = <0x198>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - storage { - label = "f5d8235-v1:blue:storage"; - gpios = <&gpio0 7 1>; - }; - - storage2 { - label = "f5d8235-v1:orange:storage"; - gpios = <&gpio0 8 1>; - }; - }; -}; - -&gpio0 { - status = "okay"; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - status = "okay"; - mtd-mac-address = <&factory 0x4>; - - port@0 { - mediatek,fixed-link = <1000 1 1 1>; - }; -}; - -/* FIXME: no u-boot partition and 0x40000@uboot is out of boundaries */ -/*&wmac { - status = "okay"; - ralink,mtd-eeprom = <&u-boot 0x40000>; -}; -*/ - diff --git a/sys/gnu/dts/mips/F5D8235_V2.dts b/sys/gnu/dts/mips/F5D8235_V2.dts deleted file mode 100644 index 084ca0f25a7..00000000000 --- a/sys/gnu/dts/mips/F5D8235_V2.dts +++ /dev/null @@ -1,118 +0,0 @@ -/dts-v1/; - -#include "rt3050.dtsi" - -/ { - compatible = "F5D8235_V2", "ralink,rt3052-soc"; - model = "Belkin F5D8235 v2"; - - cfi@1f000000 { - compatible = "cfi-flash"; - reg = <0x1f000000 0x800000>; - bank-width = <2>; - device-width = <2>; - #address-cells = <1>; - #size-cells = <1>; - - uboot: partition@0 { - label = "uboot"; - reg = <0x0 0x50000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x790000>; - }; - - partition@7e0000 { - label = "nvram"; - reg = <0x7e0000 0x10000>; - }; - - factory: partition@7f0000 { - label = "factory"; - reg = <0x7f0000 0x10000>; - }; - }; - - rtl8366rb { - compatible = "rtl8366rb"; - gpio-sda = <&gpio0 1 0>; - gpio-sck = <&gpio0 2 0>; - }; - - gpio-leds { - compatible = "gpio-leds"; - - internet { - label = "f5d8235-v2:blue:internet"; - gpios = <&gpio0 5 1>; - }; - - internet2 { - label = "f5d8235-v2:amber:internet"; - gpios = <&gpio0 6 1>; - }; - - modem { - label = "f5d8235-v2:blue:modem"; - gpios = <&gpio0 11 1>; - }; - - modem2 { - label = "f5d8235-v2:amber:modem"; - gpios = <&gpio0 8 1>; - }; - - router { - label = "f5d8235-v2:blue:router"; - gpios = <&gpio0 9 1>; - }; - - storage { - label = "f5d8235-v2:blue:storage"; - gpios = <&gpio0 23 1>; - }; - - storage2 { - label = "f5d8235-v2:amber:storage"; - gpios = <&gpio0 22 1>; - }; - - security { - label = "f5d8235-v2:blue:security"; - gpios = <&gpio0 13 1>; - }; - - security2 { - label = "f5d8235-v2:amber:security"; - gpios = <&gpio0 12 1>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - mtd-mac-address = <&uboot 0x40004>; -}; - -&esw { - mediatek,portmap = <0x3f>; -}; - -&wmac { - ralink,mtd-eeprom = <&uboot 0x40000>; -}; - -&otg { - status = "okay"; -}; diff --git a/sys/gnu/dts/mips/F7C027.dts b/sys/gnu/dts/mips/F7C027.dts deleted file mode 100644 index 6214c85d037..00000000000 --- a/sys/gnu/dts/mips/F7C027.dts +++ /dev/null @@ -1,131 +0,0 @@ -/dts-v1/; - -#include "rt5350.dtsi" - -/ { - compatible = "F7C027", "ralink,rt5350-soc"; - model = "Belkin F7C027"; - - gpio-leds { - compatible = "gpio-leds"; - - status { - label = "f7c027:blue:status"; - gpios = <&gpio0 7 1>; - }; - - power { - label = "f7c027:blue:power"; - gpios = <&gpio0 9 1>; - }; - - orange { - label = "f7c027:orange:status"; - gpios = <&gpio0 11 1>; - }; - - relay { - label = "f7c027:device:relay"; - gpios = <&gpio0 13 0>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - top { - label = "top"; - gpios = <&gpio0 10 1>; - linux,code = <0x198>; - }; - - power { - label = "power"; - gpios = <&gpio0 12 1>; - linux,code = <0x100>; - }; - - sensor { - label = "sensor"; - gpios = <&gpio0 14 1>; - linux,code = <0x101>; - }; - }; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80", "mx25l12805d"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x770000>; - }; - - partition@7c0000 { - label = "firmware2"; - reg = <0x7c0000 0x770000>; - }; - - partition@f30000 { - label = "belkin_settings"; - reg = <0xf30000 0xa0000>; - }; - - partition@fd0000 { - label = "unknown"; - reg = <0xfd0000 0x10000>; - }; - - partition@fe0000 { - label = "nvram"; - reg = <0xfe0000 0x10000>; - }; - - partition@ff0000 { - label = "user_factory"; - reg = <0xff0000 0x10000>; - }; - }; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "jtag", "uartf"; - ralink,function = "gpio"; - }; - }; -}; diff --git a/sys/gnu/dts/mips/FIREWRT.dts b/sys/gnu/dts/mips/FIREWRT.dts deleted file mode 100644 index 4299b68a340..00000000000 --- a/sys/gnu/dts/mips/FIREWRT.dts +++ /dev/null @@ -1,120 +0,0 @@ -/dts-v1/; - -#include "mt7621.dtsi" - -/ { - compatible = "mediatek,mt7621-eval-board", "mediatek,mt7621-soc"; - model = "Firefly FireWRT"; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x1c000000>, <0x20000000 0x4000000>; - }; - - chosen { - bootargs = "console=ttyS0,57600"; - }; - - gpio-leds { - compatible = "gpio-leds"; - - power { - label = "firewrt:green:power"; - gpios = <&gpio0 22 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - wps { - label = "wps"; - gpios = <&gpio0 18 1>; - linux,code = <0x211>; - }; - - power { - label = "power"; - gpios = <&gpio0 23 1>; - linux,code = <116>; - }; - }; -}; - -&sdhci { - status = "okay"; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0xfb0000>; - }; - }; -}; - -&pcie { - status = "okay"; - - pcie0 { - mt76@0,0 { - reg = <0x0000 0 0 0 0>; - device_type = "pci"; - mediatek,mtd-eeprom = <&factory 0x8000>; - mediatek,2ghz = <0>; - }; - }; - - pcie1 { - mt76@1,0 { - reg = <0x0000 0 0 0 0>; - device_type = "pci"; - mediatek,mtd-eeprom = <&factory 0x0000>; - mediatek,5ghz = <0>; - }; - }; -}; - -ðernet { - mtd-mac-address = <&factory 0xe000>; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "wdt", "rgmii2"; - ralink,function = "gpio"; - }; - }; -}; diff --git a/sys/gnu/dts/mips/FONERA20N.dts b/sys/gnu/dts/mips/FONERA20N.dts deleted file mode 100644 index b7eb91ea7bc..00000000000 --- a/sys/gnu/dts/mips/FONERA20N.dts +++ /dev/null @@ -1,134 +0,0 @@ -/dts-v1/; - -#include "rt3050.dtsi" - -/ { - compatible = "FONERA20N", "ralink,rt3052-soc"; - model = "La Fonera 2.0N"; - - cfi@1f000000 { - compatible = "cfi-flash"; - reg = <0x1f000000 0x800000>; - bank-width = <2>; - device-width = <2>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x7b0000>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - wifi { - label = "fonera20n:orange:wifi"; - gpios = <&gpio0 7 1>; - }; - - power { - label = "fonera20n:green:power"; - gpios = <&gpio0 9 1>; - }; - - usb { - label = "fonera20n:orange:usb"; - gpios = <&gpio0 14 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio0 12 1>; - linux,code = <0x198>; - }; - - switch { - label = "switch"; - gpios = <&gpio0 13 1>; - linux,code = <0xf7>; - linux,input-type = <5>; /* EV_SW */ - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "spi", "jtag", "mdio", "rgmii", "uartf"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - mtd-mac-address = <&factory 0x28>; -}; - -&esw { - mediatek,portmap = <0x2f>; - - port@0 { - compatible = "swconfig,port"; - swconfig,segment = "lan"; - swconfig,portmap = <0 4>; - }; - - port@1 { - compatible = "swconfig,port"; - swconfig,segment = "lan"; - swconfig,portmap = <1 3>; - }; - - port@2 { - compatible = "swconfig,port"; - swconfig,segment = "lan"; - swconfig,portmap = <2 2>; - }; - - port@3 { - compatible = "swconfig,port"; - swconfig,segment = "lan"; - swconfig,portmap = <3 1>; - }; - - port@4 { - compatible = "swconfig,port"; - swconfig,segment = "wan"; - swconfig,portmap = <4 0>; - }; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; - -&otg { - status = "okay"; -}; diff --git a/sys/gnu/dts/mips/FREESTATION5.dts b/sys/gnu/dts/mips/FREESTATION5.dts deleted file mode 100644 index 425eb2adbe0..00000000000 --- a/sys/gnu/dts/mips/FREESTATION5.dts +++ /dev/null @@ -1,102 +0,0 @@ -/dts-v1/; - -#include "rt3050.dtsi" - -/ { - compatible = "FREESTATION5", "ralink,rt3050-soc"; - model = "ARC FreeStation5"; - - chosen { - bootargs = "console=ttyS0,115200"; - }; - - cfi@1f000000 { - compatible = "cfi-flash"; - reg = <0x1f000000 0x800000>; - bank-width = <2>; - device-width = <2>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x7b0000>; - }; - }; - - gpio-export { - compatible = "gpio-export"; - - // Used to enable power-over-ethernet passthrough from port0 to port1. - // Disable passthrough by default to prevent accidental equipment damage. - poe { - gpio-export,name = "poe-passthrough"; - gpio-export,output = <1>; // OUT_INIT_HIGH - gpios = <&gpio0 11 1>; // GPIO 11, ACTIVE_LOW - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - // The following leds are defined in the ArcOS firmware, but reportedly - // not present in the Freestation5 device. - wifi { - label = "freestation5:unknown:wifi"; - gpios = <&gpio0 7 1>; - }; - - powerg { - label = "freestation5:unknown:powerg"; - gpios = <&gpio0 9 1>; - }; - - usb { - label = "freestation5:unknown:usb"; - gpios = <&gpio0 14 1>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - mtd-mac-address = <&factory 0x4>; -}; - -&esw { - mediatek,portmap = <0x01>; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; - -&otg { - status = "okay"; -}; diff --git a/sys/gnu/dts/mips/GL-MT300A.dts b/sys/gnu/dts/mips/GL-MT300A.dts deleted file mode 100644 index 5edb7ca4878..00000000000 --- a/sys/gnu/dts/mips/GL-MT300A.dts +++ /dev/null @@ -1,162 +0,0 @@ -/dts-v1/; - -#include "mt7620a.dtsi" - -/ { - compatible = "GL-MT300A", "ralink,mt7620a-soc"; - model = "GL-MT300A"; - - chosen { - bootargs = "console=ttyS0,115200"; - }; - - gpio-leds { - compatible = "gpio-leds"; - - wan { - label = "gl-mt300a:wan"; - gpios = <&gpio2 0 1>; - }; - - lan { - label = "gl-mt300a:lan"; - gpios = <&gpio2 1 1>; - }; - - wlan { - label = "gl-mt300a:wlan"; - gpios = <&gpio3 0 1>; - }; - - usb { - label = "gl-mt300a:usb"; - gpios = <&gpio0 7 1>; - }; - - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - reset { - label = "reset"; - gpios = <&gpio0 13 1>; - linux,code = <0x198>; - }; - - BTN_0 { - label = "BTN_0"; - gpios = <&gpio0 1 1>; - linux,code = <0x100>; - }; - - BTN_1 { - label = "BTN_1"; - gpios = <&gpio0 2 1>; - linux,code = <0x101>; - }; - }; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&gpio2 { - status = "okay"; -}; - -&gpio3 { - status = "okay"; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "w25q128"; - reg = <0>; - linux,modalias = "m25p80", "w25q128"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0xf80000>; - }; - - partition@ff0000 { - label = "art"; - reg = <0xff0000 0x10000>; - }; - }; -}; - -&sdhci { - status = "okay"; -}; - -&ehci { - status = "okay"; -}; - -&ohci { - status = "okay"; -}; - -ðernet { - pinctrl-names = "default"; - pinctrl-0 = <&ephy_pins>; - mtd-mac-address = <&factory 0x4000>; - ralink,port-map = "wllll"; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; - -&pcie { - status = "okay"; - - pcie-bridge { - mt76@0,0 { - reg = <0x0000 0 0 0 0>; - device_type = "pci"; - mediatek,mtd-eeprom = <&factory 0x8000>; - mediatek,2ghz = <0>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "wled","ephy","uartf","i2c"; - ralink,function = "gpio"; - }; - }; -}; diff --git a/sys/gnu/dts/mips/GL-MT300N.dts b/sys/gnu/dts/mips/GL-MT300N.dts deleted file mode 100644 index 341a8f64628..00000000000 --- a/sys/gnu/dts/mips/GL-MT300N.dts +++ /dev/null @@ -1,151 +0,0 @@ -/dts-v1/; - -#include "mt7620a.dtsi" - -/ { - compatible = "GL-MT300N", "ralink,mt7620a-soc"; - model = "GL-MT300N"; - - chosen { - bootargs = "console=ttyS0,115200"; - }; - - gpio-leds { - compatible = "gpio-leds"; - - wan { - label = "gl-mt300n:wan"; - gpios = <&gpio2 0 1>; - }; - - lan { - label = "gl-mt300n:lan"; - gpios = <&gpio2 1 1>; - }; - - wlan { - label = "gl-mt300n:wlan"; - gpios = <&gpio3 0 1>; - }; - - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - reset { - label = "reset"; - gpios = <&gpio0 1 1>; - linux,code = <0x198>; - }; - - BTN_0 { - label = "BTN_0"; - gpios = <&gpio2 2 1>; - linux,code = <0x100>; - }; - - BTN_1 { - label = "BTN_1"; - gpios = <&gpio2 3 1>; - linux,code = <0x101>; - }; - }; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&gpio2 { - status = "okay"; -}; - -&gpio3 { - status = "okay"; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "w25q128"; - reg = <0>; - linux,modalias = "m25p80", "w25q128"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0xf80000>; - }; - - partition@ff0000 { - label = "art"; - reg = <0xff0000 0x10000>; - }; - }; -}; - -&ehci { - status = "okay"; -}; - -&ohci { - status = "okay"; -}; - -ðernet { - mtd-mac-address = <&factory 0x4000>; - ralink,port-map = "wllll"; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; - -&pcie { - status = "okay"; - - pcie-bridge { - mt76@0,0 { - reg = <0x0000 0 0 0 0>; - device_type = "pci"; - mediatek,mtd-eeprom = <&factory 0x8000>; - mediatek,2ghz = <0>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "wled","ephy","i2c"; - ralink,function = "gpio"; - }; - }; -}; diff --git a/sys/gnu/dts/mips/GL-MT750.dts b/sys/gnu/dts/mips/GL-MT750.dts deleted file mode 100644 index c59ffb37565..00000000000 --- a/sys/gnu/dts/mips/GL-MT750.dts +++ /dev/null @@ -1,157 +0,0 @@ -/dts-v1/; - -#include "mt7620a.dtsi" - -/ { - compatible = "GL-MT750", "ralink,mt7620a-soc"; - model = "GL-MT750"; - - chosen { - bootargs = "console=ttyS0,115200"; - }; - - gpio-leds { - compatible = "gpio-leds"; - - wan { - label = "gl-mt750:wan"; - gpios = <&gpio2 0 1>; - }; - - lan { - label = "gl-mt750:lan"; - gpios = <&gpio2 1 1>; - }; - - wlan { - label = "gl-mt750:wlan"; - gpios = <&gpio3 0 1>; - }; - - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - reset { - label = "reset"; - gpios = <&gpio0 13 1>; - linux,code = <0x198>; - }; - - BTN_0 { - label = "BTN_0"; - gpios = <&gpio2 2 1>; - linux,code = <0x100>; - }; - - BTN_1 { - label = "BTN_1"; - gpios = <&gpio2 3 1>; - linux,code = <0x101>; - }; - }; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&gpio2 { - status = "okay"; -}; - -&gpio3 { - status = "okay"; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "w25q128"; - reg = <0>; - linux,modalias = "m25p80", "w25q128"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0xf80000>; - }; - - partition@ff0000 { - label = "art"; - reg = <0xff0000 0x10000>; - }; - }; -}; - -&sdhci { - status = "okay"; -}; - -&ehci { - status = "okay"; -}; - -&ohci { - status = "okay"; -}; - -ðernet { - pinctrl-names = "default"; - pinctrl-0 = <&ephy_pins>; - mtd-mac-address = <&factory 0x4000>; - ralink,port-map = "llllw"; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; - -&pcie { - status = "okay"; - - pcie-bridge { - mt76@0,0 { - reg = <0x0000 0 0 0 0>; - device_type = "pci"; - mediatek,mtd-eeprom = <&factory 0x8000>; - mediatek,2ghz = <0>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "wled","ephy","uartf"; - ralink,function = "gpio"; - }; - }; -}; diff --git a/sys/gnu/dts/mips/HC5661.dts b/sys/gnu/dts/mips/HC5661.dts deleted file mode 100644 index eb1df345edd..00000000000 --- a/sys/gnu/dts/mips/HC5661.dts +++ /dev/null @@ -1,32 +0,0 @@ -/dts-v1/; - -#include "HC5XXX.dtsi" - -/ { - compatible = "HC5661", "ralink,mt7620a-soc"; - model = "HiWiFi HC5661"; - - gpio-leds { - compatible = "gpio-leds"; - - system { - label = "hc5661:blue:system"; - gpios = <&gpio0 9 1>; - }; - - internet { - label = "hc5661:blue:internet"; - gpios = <&gpio0 11 1>; - }; - - wlan2g { - label = "hc5661:blue:wlan2g"; - gpios = <&gpio3 0 1>; - }; - - wlan5g { - label = "hc5661:blue:wlan5g"; - gpios = <&gpio0 7 1>; - }; - }; -}; diff --git a/sys/gnu/dts/mips/HC5761.dts b/sys/gnu/dts/mips/HC5761.dts deleted file mode 100644 index 6b0554a054a..00000000000 --- a/sys/gnu/dts/mips/HC5761.dts +++ /dev/null @@ -1,32 +0,0 @@ -/dts-v1/; - -#include "HC5XXX.dtsi" - -/ { - compatible = "HC5761", "ralink,mt7620a-soc"; - model = "HiWiFi HC5761"; - - gpio-leds { - compatible = "gpio-leds"; - - system { - label = "hc5761:blue:system"; - gpios = <&gpio0 9 1>; - }; - - internet { - label = "hc5761:blue:internet"; - gpios = <&gpio0 11 1>; - }; - - wlan2g { - label = "hc5761:blue:wlan2g"; - gpios = <&gpio3 0 1>; - }; - - wlan5g { - label = "hc5761:blue:wlan5g"; - gpios = <&gpio0 7 1>; - }; - }; -}; diff --git a/sys/gnu/dts/mips/HC5861.dts b/sys/gnu/dts/mips/HC5861.dts deleted file mode 100644 index 3e812f691d7..00000000000 --- a/sys/gnu/dts/mips/HC5861.dts +++ /dev/null @@ -1,92 +0,0 @@ -/dts-v1/; - -#include "HC5XXX.dtsi" - -/ { - compatible = "HC5861", "ralink,mt7620a-soc"; - model = "HiWiFi HC5861"; - - gpio-leds { - compatible = "gpio-leds"; - - system { - label = "hc5861:blue:system"; - gpios = <&gpio0 9 1>; - }; - - wlan2g { - label = "hc5861:blue:wlan2g"; - gpios = <&gpio0 11 1>; - }; - - internet { - label = "hc5861:blue:internet"; - gpios = <&gpio3 0 1>; - }; - - wlan5g { - label = "hc5861:blue:wlan5g"; - gpios = <&gpio0 7 1>; - }; - - turbo { - label = "hc5861:blue:turbo"; - gpios = <&gpio0 10 1>; - }; - }; - - gpio_export { - compatible = "gpio-export"; - #size-cells = <0>; - - usbpower { - gpio-export,name = "usbpower"; - gpio-export,output = <0>; - gpios = <&gpio0 13 0>; - }; - - sdpower { - gpio-export,name = "sdpower"; - gpio-export,output = <0>; - gpios = <&gpio0 8 0>; - }; - }; -}; - -ðernet { - status = "okay"; - mtd-mac-address = <&factory 0x4>; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>; - mediatek,portmap = "wllll"; - - port@4 { - status = "okay"; - phy-handle = <&phy4>; - phy-mode = "rgmii"; - }; - - port@5 { - status = "okay"; - phy-handle = <&phy5>; - phy-mode = "rgmii"; - }; - - mdio-bus { - status = "okay"; - - phy4: ethernet-phy@4 { - reg = <4>; - phy-mode = "rgmii"; - }; - - phy5: ethernet-phy@5 { - reg = <5>; - phy-mode = "rgmii"; - }; - }; -}; - -&gsw { - mediatek,port4 = "gmac"; -}; diff --git a/sys/gnu/dts/mips/HC5XXX.dtsi b/sys/gnu/dts/mips/HC5XXX.dtsi deleted file mode 100644 index d55d5b65cd6..00000000000 --- a/sys/gnu/dts/mips/HC5XXX.dtsi +++ /dev/null @@ -1,139 +0,0 @@ -#include "mt7620a.dtsi" - -/ { - chosen { - bootargs = "console=ttyS0,115200"; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio0 12 1>; - linux,code = <0x198>; - }; - }; - - gpio_export { - compatible = "gpio-export"; - #size-cells = <0>; - - usbpower { - gpio-export,name = "usbpower"; - gpio-export,output = <1>; - gpios = <&gpio0 13 0>; - }; - }; -}; - -&sysc { - ralink,gpiomux = "i2c", "jtag"; - ralink,uartmux = "gpio"; - ralink,wdtmux = <1>; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio2 { - status = "okay"; -}; - -&gpio3 { - status = "okay"; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80", "w25q128"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0xf80000>; - }; - - partition@fd0000 { - label = "hwf_config"; - reg = <0xfd0000 0x10000>; - }; - - bdinfo: partition@fe0000 { - label = "bdinfo"; - reg = <0xfe0000 0x10000>; - }; - - partition@ff0000 { - label = "backup"; - reg = <0xff0000 0x10000>; - }; - }; -}; - -&ehci { - status = "okay"; -}; - -&ohci { - status = "okay"; -}; - -ðernet { - pinctrl-names = "default"; - pinctrl-0 = <&ephy_pins>; - mtd-mac-address = <&factory 0x4>; - mediatek,portmap = "wllll"; -}; - -&sdhci { - status = "okay"; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; - -&pcie { - status = "okay"; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "uartf", "wled", "nd_sd"; - ralink,function = "gpio"; - }; - - pa { - ralink,group = "pa"; - ralink,function = "pa"; - }; - }; -}; diff --git a/sys/gnu/dts/mips/HG255D.dts b/sys/gnu/dts/mips/HG255D.dts deleted file mode 100644 index ee385097b2c..00000000000 --- a/sys/gnu/dts/mips/HG255D.dts +++ /dev/null @@ -1,130 +0,0 @@ -/dts-v1/; - -#include "rt3050.dtsi" - -/ { - compatible = "HG255D", "ralink,rt3052-soc"; - model = "HuaWei HG255D"; - - cfi@1f000000 { - compatible = "cfi-flash"; - reg = <0x1f000000 0x1000000>; - bank-width = <2>; - device-width = <2>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x40000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x40000 0x20000>; - read-only; - }; - - factory: partition@60000 { - label = "factory"; - reg = <0x60000 0x20000>; - read-only; - }; - - partition@80000 { - label = "firmware"; - reg = <0x80000 0xf60000>; - }; - - partition@fa0000 { - label = "factory-orig"; - reg = <0xfa0000 0x20000>; - read-only; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - power { - label = "hg255d:green:power"; - gpios = <&gpio0 8 1>; - }; - - internet { - label = "hg255d:green:internet"; - gpios = <&gpio0 13 1>; - }; - - wifi { - label = "hg255d:green:wlan"; - gpios = <&gpio0 14 1>; - }; - - usb { - label = "hg255d:green:usb"; - gpios = <&gpio0 9 1>; - }; - - wps { - label = "hg255d:green:wps"; - gpios = <&gpio0 12 1>; - }; - - voice { - label = "hg255d:green:voice"; - gpios = <&gpio0 5 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <10>; - - reset { - label = "reset"; - gpios = <&gpio0 4 1>; - linux,code = <0x198>; - }; - - wps { - label = "wps"; - gpios = <&gpio0 10 1>; - linux,code = <0x211>; - }; - - rfkill { - label = "rfkill"; - gpios = <&gpio0 0 1>; - linux,code = <0xf7>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - mtd-mac-address = <&factory 0x28>; -}; - -&esw { - mediatek,portmap = <0x2f>; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; - -&otg { - status = "okay"; -}; diff --git a/sys/gnu/dts/mips/HLKRM04.dts b/sys/gnu/dts/mips/HLKRM04.dts deleted file mode 100644 index 2f4e43548f5..00000000000 --- a/sys/gnu/dts/mips/HLKRM04.dts +++ /dev/null @@ -1,123 +0,0 @@ -/dts-v1/; - -#include "rt5350.dtsi" - -/ { - compatible = "HLKRM04", "ralink,rt5350-soc"; - model = "HILINK HLK-RM04"; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x1000000>; - }; - - chosen { - bootargs = "console=ttyS1,57600"; - }; - - gpio-export { - compatible = "gpio-export"; - #size-cells = <0>; - - /* I2C */ - gpio1 { - /* I2C_I2C_SD */ - gpio-export,name = "hlk-rm04:gpio0"; - gpio-export,direction_may_change = <1>; - gpios = <&gpio0 1 0>; - }; - gpio2 { - /* I2C_I2C_SCLK */ - gpio-export,name = "hlk-rm04:gpio1"; - gpio-export,direction_may_change = <1>; - gpios = <&gpio0 2 0>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - reset { - label = "reset"; - gpios = <&gpio0 0 1>; - linux,code = <0x198>; - }; - wps { - label = "wps"; - gpios = <&gpio0 14 1>; - linux,code = <0x211>; - }; - }; -}; - -&uart { - status = "okay"; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80", "s25fl064k"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x3b0000>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "jtag"; - ralink,function = "gpio"; - }; - - uartf_gpio { - ralink,group = "uartf"; - ralink,function = "gpio uartf"; - }; - }; -}; - -ðernet { - mtd-mac-address = <&factory 0x4>; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; - -&ehci { - status = "okay"; -}; - -&ohci { - status = "okay"; -}; diff --git a/sys/gnu/dts/mips/HPM.dts b/sys/gnu/dts/mips/HPM.dts deleted file mode 100644 index 000750fa127..00000000000 --- a/sys/gnu/dts/mips/HPM.dts +++ /dev/null @@ -1,147 +0,0 @@ -/dts-v1/; - -#include "rt3883.dtsi" - -/ { - compatible = "HPM", "ralink,rt3883-soc"; - model = "Omnima HPM"; - - chosen { - bootargs = "console=ttyS0,115200"; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <100>; - - reset { - label = "reset"; - gpios = <&gpio0 14 0>; - linux,code = <0x198>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - power { - label = "hpm:orange:power"; - gpios = <&gpio0 7 1>; - }; - - status { - label = "hpm:green:status"; - gpios = <&gpio0 21 1>; - }; - - eth { - label = "hpm:green:eth"; - gpios = <&gpio0 20 1>; - }; - - eth2 { - label = "hpm:red:eth"; - gpios = <&gpio0 18 1>; - }; - - wifi { - label = "hpm:green:wifi"; - gpios = <&gpio0 17 1>; - }; - - wifi2 { - label = "hpm:red:wifi"; - gpios = <&gpio0 19 1>; - }; - }; - - gpio_export { - compatible = "gpio-export"; - #size-cells = <0>; - /* gpio 12 and 13 handle the OC input */ - - usb0 { - gpio-export,name = "usb0"; - gpio-export,output = <1>; - gpios = <&gpio0 2 0>; - }; - - usb1 { - gpio-export,name = "usb1"; - gpio-export,output = <1>; - gpios = <&gpio0 1 0>; - }; - }; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - compatible = "jedec,spi-nor"; - spi-max-frequency = <25000000>; - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - reg = <0x0 0x0030000>; - label = "u-boot"; - read-only; - }; - - partition@30000 { - reg = <0x00030000 0x00010000>; - label = "config"; - read-only; - }; - - factory: partition@40000 { - reg = <0x00040000 0x00010000>; - label = "factory"; - read-only; - }; - - partition@50000 { - reg = <0x00050000 0x00fb0000>; - label = "firmware"; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "jtag", "uartf"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - phy-handle = <&phy0>; - phy-mode = "rgmii"; - mtd-mac-address = <&factory 0x28>; - - mdio-bus { - status = "okay"; - - phy0: ethernet-phy@4 { - reg = <4>; - }; - }; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; - -&ehci { - status = "okay"; -}; - -&ohci { - status = "okay"; -}; diff --git a/sys/gnu/dts/mips/HT-TM02.dts b/sys/gnu/dts/mips/HT-TM02.dts deleted file mode 100644 index bfa3536a29d..00000000000 --- a/sys/gnu/dts/mips/HT-TM02.dts +++ /dev/null @@ -1,112 +0,0 @@ -/dts-v1/; - -#include "rt5350.dtsi" - -/ { - compatible = "HT-TM02", "ralink,rt5350-soc"; - model = "HooToo HT-TM02"; - - gpio-leds { - compatible = "gpio-leds"; - - wlan { - label = "ht-tm02:blue:wlan"; - gpios = <&gpio0 7 1>; - }; - - lan { - label = "ht-tm02:green:lan"; - gpios = <&gpio0 12 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio0 10 1>; - linux,code = <0x198>; - }; - - modeswitch { - label = "modeswitch"; - gpios = <&gpio0 14 1>; - linux,code = <0x100>; - linux,input-type = <5>; - }; - }; -}; - -&gpio0 { - status = "okay"; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80", "mx25l6405d"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x7b0000>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "jtag", "uartf"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - mtd-mac-address = <&factory 0x28>; -}; - -&esw { - mediatek,portmap = <0x10>; - mediatek,portdisable = <0x2f>; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; - -&ehci { - status = "okay"; -}; - -&ohci { - status = "okay"; -}; diff --git a/sys/gnu/dts/mips/HW550-3G.dts b/sys/gnu/dts/mips/HW550-3G.dts deleted file mode 100644 index 0efa8d0f54b..00000000000 --- a/sys/gnu/dts/mips/HW550-3G.dts +++ /dev/null @@ -1,114 +0,0 @@ -/dts-v1/; - -#include "rt3050.dtsi" - -/ { - compatible = "HW550-3G", "ralink,rt3052-soc"; - model = "Aztech HW550-3G"; - - cfi@1f000000 { - compatible = "cfi-flash"; - reg = <0x1f000000 0x800000>; - bank-width = <2>; - device-width = <2>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x7b0000>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - usb { - label = "hw550-3g:green:usb"; - gpios = <&gpio0 8 1>; - }; - - 3g { - label = "hw550-3g:green:3g"; - gpios = <&gpio0 11 1>; - }; - - status { - label = "hw550-3g:green:status"; - gpios = <&gpio0 12 1>; - }; - - wps { - label = "hw550-3g:green:wps"; - gpios = <&gpio0 14 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio0 10 1>; - linux,code = <0x198>; - }; - - connect { - label = "connect"; - gpios = <&gpio0 7 1>; - linux,code = <0xda>; - }; - - wps { - label = "wps"; - gpios = <&gpio0 0 1>; - linux,code = <0x211>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - mtd-mac-address = <&factory 0x28>; -}; - -&esw { - mediatek,portmap = <0x3e>; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; - -&otg { - status = "okay"; -}; diff --git a/sys/gnu/dts/mips/IP2202.dts b/sys/gnu/dts/mips/IP2202.dts deleted file mode 100644 index 50d5532a2d6..00000000000 --- a/sys/gnu/dts/mips/IP2202.dts +++ /dev/null @@ -1,88 +0,0 @@ -/dts-v1/; - -#include "rt3050.dtsi" - -/ { - compatible = "IP2202", "ralink,rt3052-soc"; - model = "Poray IP2202"; - - cfi@1f000000 { - compatible = "cfi-flash"; - reg = <0x1f000000 0x800000>; - bank-width = <2>; - device-width = <2>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x7b0000>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - run { - label = "ip2202:green:run"; - gpios = <&gpio0 9 1>; - }; - - net { - label = "ip2202:amber:net"; - gpios = <&gpio0 13 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio0 10 1>; - linux,code = <0x198>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - mtd-mac-address = <&factory 0x28>; -}; - -&esw { - mediatek,portmap = <0x2f>; -}; - -&otg { - status = "okay"; -}; diff --git a/sys/gnu/dts/mips/JHR-N805R.dts b/sys/gnu/dts/mips/JHR-N805R.dts deleted file mode 100644 index 0688c3ab023..00000000000 --- a/sys/gnu/dts/mips/JHR-N805R.dts +++ /dev/null @@ -1,87 +0,0 @@ -/dts-v1/; - -#include "rt3050.dtsi" - -/ { - compatible = "JHR-N805R", "ralink,rt3050-soc"; - model = "JCG JHR-N805R"; - - gpio-leds { - compatible = "gpio-leds"; - - system { - label = "jhr-n805r:blue:system"; - gpios = <&gpio0 9 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio0 10 1>; - linux,code = <0x198>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80", "mx25l3205d"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x3b0000>; - }; - }; -}; - -ðernet { - mtd-mac-address = <&factory 0x2e>; -}; - -&esw { - mediatek,portmap = <0x3e>; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; diff --git a/sys/gnu/dts/mips/JHR-N825R.dts b/sys/gnu/dts/mips/JHR-N825R.dts deleted file mode 100644 index 1e9acdf1139..00000000000 --- a/sys/gnu/dts/mips/JHR-N825R.dts +++ /dev/null @@ -1,81 +0,0 @@ -/dts-v1/; - -#include "rt3050.dtsi" - -/ { - compatible = "JHR-N825R", "ralink,rt3052-soc"; - model = "JCG JHR-N825R"; - - cfi@1f000000 { - compatible = "cfi-flash"; - reg = <0x1f000000 0x800000>; - bank-width = <2>; - device-width = <2>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x3b0000>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - system { - label = "jhr-n825r:red:power"; - gpios = <&gpio0 9 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - reset_wps { - label = "reset_wps"; - gpios = <&gpio0 10 1>; - linux,code = <0x198>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - mtd-mac-address = <&factory 0x2e>; -}; - -&esw { - mediatek,portmap = <0x3e>; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; diff --git a/sys/gnu/dts/mips/JHR-N926R.dts b/sys/gnu/dts/mips/JHR-N926R.dts deleted file mode 100644 index 1a63656ed93..00000000000 --- a/sys/gnu/dts/mips/JHR-N926R.dts +++ /dev/null @@ -1,127 +0,0 @@ -/dts-v1/; - -#include "rt3050.dtsi" - -/ { - compatible = "JHR-N926R", "ralink,rt3052-soc"; - model = "JCG JHR-N926R"; - - cfi@1f000000 { - compatible = "cfi-flash"; - reg = <0x1f000000 0x800000>; - bank-width = <2>; - device-width = <2>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x3b0000>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - wlan1 { - label = "jhr-n926r:red:wlan"; - gpios = <&gpio0 20 1>; - }; - - wlan2 { - label = "jhr-n926r:yellow:wlan"; - gpios = <&gpio0 19 1>; - }; - - wlan3 { - label = "jhr-n926r:green:wlan"; - gpios = <&gpio0 17 1>; - }; - - system { - label = "jhr-n926r:blue:system"; - gpios = <&gpio0 13 1>; - }; - }; - - gpio_export { - compatible = "gpio-export"; - #size-cells = <0>; - - display_data { - gpio-export,name = "display_data"; - gpio-export,output = <1>; - gpios = <&gpio0 7 1>; - }; - - display_clock { - gpio-export,name = "display_clock"; - gpio-export,output = <1>; - gpios = <&gpio0 8 0>; - }; - - display_blank { - gpio-export,name = "display_blank"; - gpio-export,output = <1>; - gpios = <&gpio0 11 0>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset_wps { - label = "reset_wps"; - gpios = <&gpio0 10 1>; - linux,code = <0x198>; - }; - - wlan { - label = "wlan"; - gpios = <&gpio0 1 1>; - linux,code = <0x100>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - mtd-mac-address = <&factory 0x2e>; -}; - -&esw { - mediatek,portmap = <0x3e>; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; diff --git a/sys/gnu/dts/mips/LINKIT7688.dts b/sys/gnu/dts/mips/LINKIT7688.dts deleted file mode 100644 index 09a8c987f7c..00000000000 --- a/sys/gnu/dts/mips/LINKIT7688.dts +++ /dev/null @@ -1,182 +0,0 @@ -/dts-v1/; - -#include "mt7628an.dtsi" - -/ { - compatible = "mediatek,linkit", "mediatek,mt7628an-soc"; - model = "MediaTek LinkIt Smart 7688"; - - chosen { - bootargs = "console=ttyS2,57600"; - }; - - aliases { - serial0 = &uart2; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x8000000>; - }; - - bootstrap { - compatible = "mediatek,linkit"; - - status = "okay"; - }; - - gpio-leds { - compatible = "gpio-leds"; - - wifi { - label = "mediatek:orange:wifi"; - gpios = <&wgpio 0 0>; - default-state = "on"; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - wps { - label = "reset"; - gpios = <&gpio1 6 1>; - linux,code = <0x211>; - }; - }; - - wgpio: gpio-wifi { - compatible = "mediatek,gpio-wifi"; - #address-cells = <1>; - #size-cells = <0>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "gpio"; - ralink,function = "gpio"; - }; - - perst { - ralink,group = "perst"; - ralink,function = "gpio"; - }; - - refclk { - ralink,group = "refclk"; - ralink,function = "gpio"; - }; - - i2s { - ralink,group = "i2s"; - ralink,function = "gpio"; - }; - - spis { - ralink,group = "spis"; - ralink,function = "gpio"; - }; - - wled_kn { - ralink,group = "wled_kn"; - ralink,function = "gpio"; - }; - - wled_an { - ralink,group = "wled_an"; - ralink,function = "wled_an"; - }; - - wdt { - ralink,group = "wdt"; - ralink,function = "gpio"; - }; - }; -}; - -&wmac { - status = "okay"; -}; - -&spi0 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&spi_pins>, <&spi_cs1_pins>; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80", "mx25l25635e"; - spi-max-frequency = <40000000>; - m25p,chunked-io = <31>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x1fb0000>; - }; - }; - - spidev@1 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "linux,spidev"; - reg = <1>; - spi-max-frequency = <40000000>; - }; -}; - -&i2c { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&pwm { - status = "okay"; -}; - -ðernet { - mtd-mac-address = <&factory 0x28>; -}; - -&sdhci { - status = "okay"; - mediatek,cd-high; -}; - -&wmac { - status = "okay"; -}; diff --git a/sys/gnu/dts/mips/M2M.dts b/sys/gnu/dts/mips/M2M.dts deleted file mode 100644 index 22ec534a2a6..00000000000 --- a/sys/gnu/dts/mips/M2M.dts +++ /dev/null @@ -1,110 +0,0 @@ -/dts-v1/; - -#include "rt5350.dtsi" - -/ { - compatible = "M2M", "ralink,rt5350-soc"; - model = "Intenso Memory 2 Move"; - - chosen { - bootargs = "console=ttyS0,57600n8 root=/dev/mtdblock5"; - }; - - gpio-leds { - compatible = "gpio-leds"; - - wifi { - label = "m2m:blue:wifi"; - gpios = <&gpio0 7 1>; - }; - - wan { - label = "m2m:green:wan"; - gpios = <&gpio0 12 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - power { - label = "power"; - gpios = <&gpio0 1 1>; - linux,code = <0x116>; - }; - - reset { - label = "reset"; - gpios = <&gpio0 10 1>; - linux,code = <0x198>; - }; - }; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80", "mx25l6405d"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "Bootloader"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "Config"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "Factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x7b0000>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "uartf"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - mtd-mac-address = <&factory 0x28>; -}; - -&esw { - mediatek,portmap = <0x2f>; -}; - -&ehci { - status = "okay"; -}; - -&ohci { - status = "okay"; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0x0>; -}; diff --git a/sys/gnu/dts/mips/M3.dts b/sys/gnu/dts/mips/M3.dts deleted file mode 100644 index 9b6ed89142a..00000000000 --- a/sys/gnu/dts/mips/M3.dts +++ /dev/null @@ -1,104 +0,0 @@ -/dts-v1/; - -#include "rt5350.dtsi" - -/ { - compatible = "M3", "ralink,rt5350-soc"; - model = "Poray M3"; - - gpio-leds { - compatible = "gpio-leds"; - - status { - label = "m3:blue:status"; - gpios = <&gpio0 9 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio0 10 1>; - linux,code = <0x198>; - }; - - mode { - label = "mode"; - gpios = <&gpio0 17 1>; - linux,code = <0x100>; - linux,input-type = <5>; - }; - }; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80", "w25q32"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x3b0000>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "jtag", "uartf"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - mtd-mac-address = <&factory 0x4>; -}; - -&esw { - mediatek,portmap = <0x2f>; - mediatek,led_polarity = <1>; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; - ralink,led-polarity = <1>; -}; - -&ehci { - status = "okay"; -}; - -&ohci { - status = "okay"; -}; diff --git a/sys/gnu/dts/mips/M4-4M.dts b/sys/gnu/dts/mips/M4-4M.dts deleted file mode 100644 index 0502714c3b0..00000000000 --- a/sys/gnu/dts/mips/M4-4M.dts +++ /dev/null @@ -1,92 +0,0 @@ -/dts-v1/; - -#include "rt5350.dtsi" - -/ { - compatible = "M4", "ralink,rt5350-soc"; - model = "Poray M4"; - - gpio-leds { - compatible = "gpio-leds"; - - status { - label = "m4:blue:status"; - gpios = <&gpio0 9 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio0 10 1>; - linux,code = <0x198>; - }; - }; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80", "pm25lq032"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x3b0000>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "jtag", "uartf"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - mtd-mac-address = <&factory 0x4>; -}; - -&esw { - mediatek,portmap = <0x2f>; - mediatek,led_polarity = <1>; -}; - -&ehci { - status = "okay"; -}; - -&ohci { - status = "okay"; -}; diff --git a/sys/gnu/dts/mips/M4-8M.dts b/sys/gnu/dts/mips/M4-8M.dts deleted file mode 100644 index 16ee184ed26..00000000000 --- a/sys/gnu/dts/mips/M4-8M.dts +++ /dev/null @@ -1,97 +0,0 @@ -/dts-v1/; - -#include "rt5350.dtsi" - -/ { - compatible = "M4", "ralink,rt5350-soc"; - model = "Poray M4"; - - gpio-leds { - compatible = "gpio-leds"; - - status { - label = "m4:blue:status"; - gpios = <&gpio0 9 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio0 10 1>; - linux,code = <0x198>; - }; - }; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80", "gd25q64"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x7b0000>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "jtag", "uartf"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - mtd-mac-address = <&factory 0x4>; -}; - -&esw { - mediatek,portmap = <0x2f>; - mediatek,led_polarity = <1>; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; - ralink,led-polarity = <1>; -}; - -&ehci { - status = "okay"; -}; - -&ohci { - status = "okay"; -}; diff --git a/sys/gnu/dts/mips/MINIEMBPLUG.dts b/sys/gnu/dts/mips/MINIEMBPLUG.dts deleted file mode 100644 index eefac574c13..00000000000 --- a/sys/gnu/dts/mips/MINIEMBPLUG.dts +++ /dev/null @@ -1,122 +0,0 @@ -/dts-v1/; - -#include "rt5350.dtsi" - -/ { - compatible = "MINIEMBPLUG", "ralink,rt5350-soc"; - model = "Omnima MiniEMBPlug"; - - gpio-leds { - compatible = "gpio-leds"; - - wlan { - label = "miniembplug:red:wlan"; - gpios = <&gpio0 9 0>; - }; - - mobile { - label = "miniembplug:green:mobile"; - gpios = <&gpio0 13 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - wps { - label = "wps"; - gpios = <&gpio0 0 1>; - linux,code = <0x211>; - }; - - reset { - label = "reset"; - gpios = <&gpio0 10 1>; - linux,code = <0x211>; - }; - - mode-one { - label = "mode1"; - gpios = <&gpio0 11 1>; - linux,code = <0x211>; - }; - - mode-two { - label = "mode2"; - gpios = <&gpio0 12 1>; - linux,code = <0x211>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "jtag", "uartf"; - ralink,function = "gpio"; - }; - }; -}; - -&gpio0 { - status = "okay"; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80", "mx25l6405d"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x7b0000>; - }; - }; -}; - -ðernet { - mtd-mac-address = <&factory 0x4>; -}; - -&esw { - mediatek,portmap = <0x2f>; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; - -&ehci { - status = "okay"; -}; - -&ohci { - status = "okay"; -}; diff --git a/sys/gnu/dts/mips/MINIEMBWIFI.dts b/sys/gnu/dts/mips/MINIEMBWIFI.dts deleted file mode 100644 index 1240adede0a..00000000000 --- a/sys/gnu/dts/mips/MINIEMBWIFI.dts +++ /dev/null @@ -1,92 +0,0 @@ -/dts-v1/; - -#include "rt3050.dtsi" - -/ { - compatible = "MINIEMBWIFI", "ralink,rt3052-soc"; - model = "Omnima MiniEMBWiFi"; - - gpio-leds { - compatible = "gpio-leds"; - - status { - label = "miniembwifi:green:status"; - gpios = <&gpio0 9 1>; - }; - - wlan { - label = "miniembwifi:green:wlan"; - gpios = <&gpio0 14 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio0 12 1>; - linux,code = <0x198>; - }; - }; - - cfi@1f000000 { - compatible = "cfi-flash"; - reg = <0x1f000000 0x800000>; - bank-width = <2>; - device-width = <2>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x7b0000>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - mtd-mac-address = <&factory 0x28>; -}; - -&esw { - mediatek,portmap = <0x2f>; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; - -&otg { - status = "okay"; -}; diff --git a/sys/gnu/dts/mips/MIWIFI-MINI.dts b/sys/gnu/dts/mips/MIWIFI-MINI.dts deleted file mode 100644 index e9ad3750b70..00000000000 --- a/sys/gnu/dts/mips/MIWIFI-MINI.dts +++ /dev/null @@ -1,153 +0,0 @@ -/dts-v1/; - -#include "mt7620a.dtsi" - -/ { - compatible = "xiaomi,miwifi-mini", "ralink,mt7620a-soc"; - model = "Xiaomi MiWiFi Mini"; - - chosen { - bootargs = "console=ttyS0,115200"; - }; - - gpio-leds { - compatible = "gpio-leds"; - - blue { - label = "miwifi-mini:blue:status"; - gpios = <&gpio1 0 1>; - }; - - yellow { - label = "miwifi-mini:yellow:status"; - gpios = <&gpio1 2 1>; - }; - - red { - label = "miwifi-mini:red:status"; - gpios = <&gpio1 5 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio1 6 0>; - linux,code = <0x198>; - }; - }; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&gpio2 { - status = "okay"; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80", "w25q128"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0xf80000>; - }; - - partition@fd0000 { - label = "crash"; - reg = <0xfd0000 0x10000>; - }; - - partition@fe0000 { - label = "reserved"; - reg = <0xfe0000 0x10000>; - read-only; - }; - - partition@ff0000 { - label = "Bdata"; - reg = <0xff0000 0x10000>; - }; - }; -}; - -&ehci { - status = "okay"; -}; - -&ohci { - status = "okay"; -}; - -ðernet { - pinctrl-names = "default"; - pinctrl-0 = <&ephy_pins>; - mtd-mac-address = <&factory 0x4>; - mediatek,portmap = "llllw"; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; - -&pcie { - status = "okay"; - - pcie-bridge { - mt76@0,0 { - reg = <0x0000 0 0 0 0>; - device_type = "pci"; - mediatek,mtd-eeprom = <&factory 0x8000>; - mediatek,2ghz = <0>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "rgmii1"; - ralink,function = "gpio"; - }; - - pa { - ralink,group = "pa"; - ralink,function = "pa"; - }; - }; -}; diff --git a/sys/gnu/dts/mips/MIWIFI-NANO.dts b/sys/gnu/dts/mips/MIWIFI-NANO.dts deleted file mode 100644 index 57a976ddf00..00000000000 --- a/sys/gnu/dts/mips/MIWIFI-NANO.dts +++ /dev/null @@ -1,88 +0,0 @@ -/dts-v1/; - -#include "mt7628an.dtsi" - -/ { - compatible = "xiaomi,MiWifi Nano", "mediatek,mt7628an-soc"; - model = "MiWiFi Nano"; - - chosen { - bootargs = "console=ttyS0,115200"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x4000000>; - }; - - gpio-leds { - compatible = "gpio-leds"; - - wifi { - label = "miwifi-nano:blue:wifi"; - gpios = <&gpio0 11 1>; - default-state = "1"; - }; - status { - label = "miwifi-nano:red:status"; - gpios = <&gpio1 5 1>; - default-state = "on"; - }; - radio { - label = "miwifi-nano:amber:radio"; - gpios = <&gpio1 12 1>; - default-state = "1"; - - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "refclk", "wled", "gpio"; - ralink,function = "gpio"; - }; - }; -}; - -&wmac { - status = "okay"; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80"; - spi-max-frequency = <10000000>; - m25p,chunked-io = <32>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x7b0000>; - }; - }; -}; diff --git a/sys/gnu/dts/mips/MLW221.dts b/sys/gnu/dts/mips/MLW221.dts deleted file mode 100644 index 670a36aadb3..00000000000 --- a/sys/gnu/dts/mips/MLW221.dts +++ /dev/null @@ -1,120 +0,0 @@ -/dts-v1/; - -#include "mt7620n.dtsi" - -/ { - compatible = "mlw221", "ralink,mt7620n-soc"; - model = "Kingston MLW221"; - - gpio-leds { - compatible = "gpio-leds"; - - system { - label = "mlw221:blue:system"; - gpios = <&gpio2 3 1>; - }; - - wifi { - label = "mlw221:blue:wifi"; - gpios = <&gpio3 0 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio0 1 1>; - linux,code = <0x198>; - }; - - system { - label = "system"; - gpios = <&gpio0 2 1>; - linux,code = <0x211>; - }; - }; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio2 { - status = "okay"; -}; - -&gpio3 { - status = "okay"; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80", "s25fl129p1"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0xf60000>; - }; - - partition@fb0000 { - label = "user-config"; - reg = <0xfb0000 0x50000>; - }; - }; -}; - -&ehci { - status = "okay"; -}; - -&ohci { - status = "okay"; -}; - -ðernet { - mtd-mac-address = <&factory 0x4>; - mediatek,portmap = "wllll"; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; - -&pinctrl { - state_default: pinctrl0 { - default { - ralink,group = "i2c", "ephy", "wled"; - ralink,function = "gpio"; - }; - }; -}; diff --git a/sys/gnu/dts/mips/MLWG2.dts b/sys/gnu/dts/mips/MLWG2.dts deleted file mode 100644 index c9f61c735f3..00000000000 --- a/sys/gnu/dts/mips/MLWG2.dts +++ /dev/null @@ -1,120 +0,0 @@ -/dts-v1/; - -#include "mt7620n.dtsi" - -/ { - compatible = "mlwg2", "ralink,mt7620n-soc"; - model = "Kingston MLWG2"; - - gpio-leds { - compatible = "gpio-leds"; - - system { - label = "mlwg2:blue:system"; - gpios = <&gpio2 3 1>; - }; - - wifi { - label = "mlwg2:blue:wifi"; - gpios = <&gpio3 0 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio0 1 1>; - linux,code = <0x198>; - }; - - system { - label = "system"; - gpios = <&gpio0 2 1>; - linux,code = <0x211>; - }; - }; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio2 { - status = "okay"; -}; - -&gpio3 { - status = "okay"; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0xf60000>; - }; - - partition@fb0000 { - label = "user-config"; - reg = <0xfb0000 0x50000>; - }; - }; -}; - -&ehci { - status = "okay"; -}; - -&ohci { - status = "okay"; -}; - -ðernet { - mtd-mac-address = <&factory 0x4>; - mediatek,portmap = "wllll"; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; - -&pinctrl { - state_default: pinctrl0 { - default { - ralink,group = "i2c", "ephy", "wled"; - ralink,function = "gpio"; - }; - }; -}; diff --git a/sys/gnu/dts/mips/MOFI3500-3GN.dts b/sys/gnu/dts/mips/MOFI3500-3GN.dts deleted file mode 100644 index 633f20a7504..00000000000 --- a/sys/gnu/dts/mips/MOFI3500-3GN.dts +++ /dev/null @@ -1,111 +0,0 @@ -/dts-v1/; - -#include "rt3050.dtsi" - -/ { - compatible = "MOFI3500-3GN", "ralink,rt3052-soc"; - model = "MoFi Network MOFI3500-3GN"; - - cfi@1f000000 { - compatible = "cfi-flash"; - reg = <0x1f000000 0x800000>; - bank-width = <2>; - device-width = <2>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x7b0000>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - usb { - label = "mofi3500-3gn:green:usb"; - gpios = <&gpio0 8 1>; - }; - - 3g { - label = "mofi3500-3gn:green:3g"; - gpios = <&gpio0 11 1>; - }; - - status { - label = "mofi3500-3gn:green:status"; - gpios = <&gpio0 12 1>; - }; - - wps { - label = "mofi3500-3gn:green:wps"; - gpios = <&gpio0 14 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio0 10 1>; - linux,code = <0x198>; - }; - - connect { - label = "connect"; - gpios = <&gpio0 7 1>; - linux,code = <0xda>; - }; - - wps { - label = "wps"; - gpios = <&gpio0 0 1>; - linux,code = <0x211>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; -}; - -&esw { - mediatek,portmap = <0x2f>; -}; - -&wmac { - status = "okay"; - ralink,mtd-eeprom = <&factory 0>; -}; - -&otg { - status = "okay"; -}; diff --git a/sys/gnu/dts/mips/MPRA1.dts b/sys/gnu/dts/mips/MPRA1.dts deleted file mode 100644 index d9baed732a2..00000000000 --- a/sys/gnu/dts/mips/MPRA1.dts +++ /dev/null @@ -1,121 +0,0 @@ -/dts-v1/; - -#include "rt5350.dtsi" - -/ { - compatible = "MPRA1", "ralink,rt5350-soc"; - model = "HAME MPR-A1"; - - gpio-leds { - compatible = "gpio-leds"; - - system { - label = "mpr-a1:blue:system"; - gpios = <&gpio0 20 1>; - }; - - power { - label = "mpr-a1:red:power"; - gpios = <&gpio0 17 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - wps { - label = "reset"; - gpios = <&gpio0 0 1>; - linux,code = <0x198>; - }; - }; - - gpio_export { - compatible = "gpio-export"; - #size-cells = <0>; - - usb { - gpio-export,name = "usb"; - gpio-export,output = <1>; - gpios = <&gpio0 7 0>; - }; - - root_hub { - gpio-export,name = "root_hub"; - gpio-export,output = <1>; - gpios = <&gpio0 12 0>; - }; - }; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80", "s25fl064k"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x3b0000>; - }; - }; -}; - -&gpio1 { - status = "okay"; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "jtag", "rgmii", "mdio", "uartf", "led"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - mtd-mac-address = <&factory 0x4>; -}; - -&esw { - mediatek,portmap = <0x2f>; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; - -&ehci { - status = "okay"; -}; - -&ohci { - status = "okay"; -}; diff --git a/sys/gnu/dts/mips/MPRA2.dts b/sys/gnu/dts/mips/MPRA2.dts deleted file mode 100644 index 84f5dda3a63..00000000000 --- a/sys/gnu/dts/mips/MPRA2.dts +++ /dev/null @@ -1,118 +0,0 @@ -/dts-v1/; - -#include "rt5350.dtsi" - -/ { - compatible = "MPRA2", "ralink,rt5350-soc"; - model = "HAME MPR-A2"; - - gpio-leds { - compatible = "gpio-leds"; - - system { - label = "mpr-a2:blue:system"; - gpios = <&gpio0 20 1>; - }; - - power { - label = "mpr-a2:red:power"; - gpios = <&gpio0 17 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - wps { - label = "reset"; - gpios = <&gpio0 0 1>; - linux,code = <0x198>; - }; - }; - - gpio_export { - compatible = "gpio-export"; - #size-cells = <0>; - - usb { - gpio-export,name = "usb"; - gpio-export,output = <1>; - gpios = <&gpio0 7 0>; - }; - - root_hub { - gpio-export,name = "root_hub"; - gpio-export,output = <1>; - gpios = <&gpio0 12 0>; - }; - }; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80", "s25fl064k"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x7b0000>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - mtd-mac-address = <&factory 0x4>; -}; - -&esw { - mediatek,portmap = <0x1>; - mediatek,portdisable = <0x3e>; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; - -&ehci { - status = "okay"; -}; - -&ohci { - status = "okay"; -}; diff --git a/sys/gnu/dts/mips/MR-102N.dts b/sys/gnu/dts/mips/MR-102N.dts deleted file mode 100644 index 6546601f158..00000000000 --- a/sys/gnu/dts/mips/MR-102N.dts +++ /dev/null @@ -1,116 +0,0 @@ -/dts-v1/; - -#include "rt3050.dtsi" - -/ { - compatible = "MR-102N", "ralink,rt3052-soc"; - model = "AXIMCom MR-102N"; - - cfi@1f000000 { - compatible = "cfi-flash"; - reg = <0x1f000000 0x800000>; - bank-width = <2>; - device-width = <2>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x790000>; - }; - - partition@7e0000 { - label = "nvram"; - reg = <0x7e0000 0x10000>; - }; - - partition@7f0000 { - label = "nvram_backup"; - reg = <0x7f0000 0x10000>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - usb { - label = "mr-102n:green:usb"; - gpios = <&gpio0 8 1>; - }; - - status { - label = "mr-102n:amber:status"; - gpios = <&gpio0 9 1>; - }; - - wlan { - label = "mr-102n:green:wlan"; - gpios = <&gpio0 11 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio0 13 1>; - linux,code = <0x198>; - }; - - wps { - label = "wps"; - gpios = <&gpio0 18 1>; - linux,code = <0x211>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - mtd-mac-address = <&factory 0x4>; -}; - -&esw { - status = "okay"; - #mediatek,portmap = <0x3e>; - mediatek,portmap = <0x2f>; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; - - -&otg { - status = "okay"; -}; diff --git a/sys/gnu/dts/mips/MT7620a.dts b/sys/gnu/dts/mips/MT7620a.dts deleted file mode 100644 index 7bf38976f61..00000000000 --- a/sys/gnu/dts/mips/MT7620a.dts +++ /dev/null @@ -1,125 +0,0 @@ -/dts-v1/; - -#include "mt7620a.dtsi" - -/ { - compatible = "ralink,mt7620a-eval-board", "ralink,mt7620a-soc"; - model = "Ralink MT7620a + MT7610e evaluation board"; - - gpio-keys-polled { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - s2 { - label = "S2"; - gpios = <&gpio0 1 1>; - linux,code = <0x100>; - }; - - s3 { - label = "S3"; - gpios = <&gpio0 2 1>; - linux,code = <0x101>; - }; - }; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80", "en25q64"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x7b0000>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "uartf"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>; - mediatek,portmap = "llllw"; - - port@4 { - status = "okay"; - phy-mode = "rgmii"; - phy-handle = <&phy4>; - }; - - port@5 { - status = "okay"; - phy-mode = "rgmii"; - phy-handle = <&phy5>; - }; - - mdio-bus { - status = "okay"; - - phy4: ethernet-phy@4 { - reg = <4>; - phy-mode = "rgmii"; - }; - - phy5: ethernet-phy@5 { - reg = <5>; - phy-mode = "rgmii"; - }; - }; -}; - -&gsw { - mediatek,port4 = "gmac"; -}; - -&sdhci { - status = "okay"; -}; - -&pcie { - status = "okay"; -}; - -&ehci { - status = "okay"; -}; - -&ohci { - status = "okay"; -}; diff --git a/sys/gnu/dts/mips/MT7620a_MT7530.dts b/sys/gnu/dts/mips/MT7620a_MT7530.dts deleted file mode 100644 index 5885ed045d0..00000000000 --- a/sys/gnu/dts/mips/MT7620a_MT7530.dts +++ /dev/null @@ -1,117 +0,0 @@ -/dts-v1/; - -#include "mt7620a.dtsi" - -/ { - compatible = "ralink,mt7620a-eval-board", "ralink,mt7620a-soc"; - model = "Ralink MT7620a + MT7530 evaluation board"; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80", "s25fl064k"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x7b0000>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "uartf"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>; - mediatek,portmap = "llllw"; - - port@5 { - status = "okay"; - mediatek,fixed-link = <1000 1 1 1>; - phy-mode = "rgmii"; - }; - - mdio-bus { - status = "okay"; - - phy0: ethernet-phy@0 { - reg = <0>; - phy-mode = "rgmii"; - }; - - phy1: ethernet-phy@1 { - reg = <1>; - phy-mode = "rgmii"; - }; - - phy2: ethernet-phy@2 { - reg = <2>; - phy-mode = "rgmii"; - }; - - phy3: ethernet-phy@3 { - reg = <3>; - phy-mode = "rgmii"; - }; - - phy4: ethernet-phy@4 { - reg = <4>; - phy-mode = "rgmii"; - }; - - phy1f: ethernet-phy@1f { - reg = <0x1f>; - phy-mode = "rgmii"; - }; - }; -}; - -&gsw { - mediatek,port4 = "gmac"; - mediatek,mt7530 = <1>; -}; - -&pcie { - status = "okay"; -}; - -&ehci { - status = "okay"; -}; - -&ohci { - status = "okay"; -}; diff --git a/sys/gnu/dts/mips/MT7620a_MT7610e.dts b/sys/gnu/dts/mips/MT7620a_MT7610e.dts deleted file mode 100644 index 52ceddcbc82..00000000000 --- a/sys/gnu/dts/mips/MT7620a_MT7610e.dts +++ /dev/null @@ -1,86 +0,0 @@ -/dts-v1/; - -#include "mt7620a.dtsi" - -/ { - compatible = "ralink,mt7620a-eval-board", "ralink,mt7620a-soc"; - model = "Ralink MT7620A evaluation board"; - - gpio-keys-polled { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - wps { - label = "wps"; - gpios = <&gpio0 12 1>; - linux,code = <0x100>; - }; - - reset { - label = "reset"; - gpios = <&gpio0 13 1>; - linux,code = <0x101>; - }; - }; -}; - -&gpio0 { - status = "okay"; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80", "en25q64"; - spi-max-frequency = <1000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x7b0000>; - }; - }; -}; - -ðernet { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&ephy_pins>; - mediatek,portmap = "llllw"; -}; - -&gsw { - mediatek,port4 = "ephy"; -}; - -&sdhci { - status = "okay"; -}; - -&pcie { - status = "okay"; -}; diff --git a/sys/gnu/dts/mips/MT7620a_V22SG.dts b/sys/gnu/dts/mips/MT7620a_V22SG.dts deleted file mode 100644 index a3e206e5ddd..00000000000 --- a/sys/gnu/dts/mips/MT7620a_V22SG.dts +++ /dev/null @@ -1,114 +0,0 @@ -/dts-v1/; - -#include "mt7620a.dtsi" - -/ { - compatible = "ralink,mt7620a-eval-board", "ralink,mt7620a-soc"; - model = "Ralink MT7620a V22SG High Power evaluation board"; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio0 1 1>; - linux,code = <0x198>; - }; - - aoss { - label = "aoss"; - gpios = <&gpio0 2 1>; - linux,code = <0x211>; - }; - }; - - nand { - #address-cells = <1>; - #size-cells = <1>; - compatible = "mtk,mt7620-nand"; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x40000>; - read-only; - }; - - partition@40000 { - label = "u-boot-env"; - reg = <0x40000 0x20000>; - read-only; - }; - - factory: partition@60000 { - label = "factory"; - reg = <0x60000 0x20000>; - read-only; - }; - - partition@80000 { - label = "firmware"; - reg = <0x80000 0x7f80000>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "uartf", "spi"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>; - mediatek,portmap = "llllw"; - - port@4 { - status = "okay"; - phy-handle = <&phy4>; - phy-mode = "rgmii"; - }; - - port@5 { - status = "okay"; - phy-handle = <&phy5>; - phy-mode = "rgmii"; - }; - - mdio-bus { - status = "okay"; - - phy4: ethernet-phy@4 { - reg = <4>; - phy-mode = "rgmii"; - }; - - phy5: ethernet-phy@5 { - reg = <5>; - phy-mode = "rgmii"; - }; - }; -}; - -&gsw { - mediatek,port4 = "gmac"; -}; - -&pcie { - status = "okay"; -}; - -&ehci { - status = "okay"; -}; - -&ohci { - status = "okay"; -}; diff --git a/sys/gnu/dts/mips/MT7621.dts b/sys/gnu/dts/mips/MT7621.dts deleted file mode 100644 index 4013f3c7b53..00000000000 --- a/sys/gnu/dts/mips/MT7621.dts +++ /dev/null @@ -1,56 +0,0 @@ -/dts-v1/; - -#include "mt7621.dtsi" - -/ { - compatible = "mediatek,mt7621-eval-board", "mediatek,mt7621-soc"; - model = "Mediatek MT7621 evaluation board"; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x2000000>; - }; - - chosen { - bootargs = "console=ttyS0,57600"; - }; - - nand@1e003000 { - partition@0 { - label = "uboot"; - reg = <0x00000 0x80000>; /* 64 KB */ - }; - - partition@80000 { - label = "uboot_env"; - reg = <0x80000 0x80000>; /* 64 KB */ - }; - - partition@100000 { - label = "factory"; - reg = <0x100000 0x40000>; - }; - - partition@140000 { - label = "rootfs"; - reg = <0x140000 0xec0000>; - }; - }; -}; - -&sdhci { - status = "okay"; -}; - -&xhci { - status = "okay"; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "uart2", "uart3", "rgmii2", "sdhci"; - ralink,function = "gpio"; - }; - }; -}; diff --git a/sys/gnu/dts/mips/MT7628.dts b/sys/gnu/dts/mips/MT7628.dts deleted file mode 100644 index a4b066cfd5a..00000000000 --- a/sys/gnu/dts/mips/MT7628.dts +++ /dev/null @@ -1,67 +0,0 @@ -/dts-v1/; - -#include "mt7628an.dtsi" - -/ { - compatible = "mediatek,mt7628an-eval-board", "mediatek,mt7628an-soc"; - model = "Mediatek MT7628AN evaluation board"; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x2000000>; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "jtag"; - ralink,function = "gpio"; - }; - }; -}; - -&wmac { - status = "okay"; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80", "en25q64"; - spi-max-frequency = <10000000>; - m25p,chunked-io = <32>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x7b0000>; - }; - }; -}; - -&wmac { - status = "okay"; -}; diff --git a/sys/gnu/dts/mips/MZK-750DHP.dts b/sys/gnu/dts/mips/MZK-750DHP.dts deleted file mode 100644 index 01fe2a1e24f..00000000000 --- a/sys/gnu/dts/mips/MZK-750DHP.dts +++ /dev/null @@ -1,127 +0,0 @@ -/dts-v1/; - -#include "mt7620a.dtsi" - -/ { - compatible = "ralink,mt7620a-soc"; - model = "Planex MZK-750DHP"; - - gpio-leds { - compatible = "gpio-leds"; - - wps { - label = "mzk-750dhp:green:wps"; - gpios = <&gpio2 15 1>; - }; - - power { - label = "mzk-750dhp:green:power"; - gpios = <&gpio1 15 1>; - }; - - wlan5g { - label = "mzk-750dhp:green:wlan5g"; - gpios = <&gpio1 14 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - s1 { - label = "reset"; - gpios = <&gpio0 1 1>; - linux,code = <0x198>; - }; - - s2 { - label = "wps"; - gpios = <&gpio2 19 1>; - linux,code = <0x211>; - }; - }; -}; - -&gpio1 { - status = "okay"; -}; - -&gpio2 { - status = "okay"; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80", "mx25l6405d"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x7b0000>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "spi refclk", "rgmii1", "nd_sd"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - pinctrl-names = "default"; - pinctrl-0 = <&ephy_pins>; - mtd-mac-address = <&factory 0x4>; - mediatek,portmap = "llllw"; -}; - -&gsw { - mediatek,port4 = "ephy"; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; - -&pcie { - status = "okay"; - - pcie-bridge { - mt76@0,0 { - reg = <0x0000 0 0 0 0>; - device_type = "pci"; - mediatek,mtd-eeprom = <&factory 0x8000>; - mediatek,2ghz = <0>; - }; - }; -}; diff --git a/sys/gnu/dts/mips/MZK-DP150N.dts b/sys/gnu/dts/mips/MZK-DP150N.dts deleted file mode 100644 index 86f82ba59ae..00000000000 --- a/sys/gnu/dts/mips/MZK-DP150N.dts +++ /dev/null @@ -1,100 +0,0 @@ -/dts-v1/; - -#include "rt5350.dtsi" - -/ { - compatible = "MZK-DP150N", "ralink,rt5350-soc"; - model = "Planex MZK-DP150N"; - - gpio-leds { - compatible = "gpio-leds"; - - power { - label = "mzk-dp150n:green:power"; - gpios = <&gpio0 9 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio0 10 1>; - linux,code = <0x198>; - }; - }; -}; - -&gpio1 { - status = "okay"; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80", "s25fl064k"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "uboot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "uboot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x3b0000>; - }; - }; -}; - -&spi1 { - spidev@0 { - compatible = "linux,spidev"; - spi-max-frequency = <10000000>; - reg = <0>; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "jtag", "uartf", "led"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - mtd-mac-address = <&factory 0x4>; -}; - -&esw { - mediatek,portmap = <0x17>; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; - ralink,led-polarity = <1>; -}; diff --git a/sys/gnu/dts/mips/MZK-EX300NP.dts b/sys/gnu/dts/mips/MZK-EX300NP.dts deleted file mode 100644 index 05c79d3faf8..00000000000 --- a/sys/gnu/dts/mips/MZK-EX300NP.dts +++ /dev/null @@ -1,130 +0,0 @@ -/dts-v1/; - -#include "mt7620a.dtsi" - -/ { - compatible = "ralink,mt7620a-soc"; - model = "Planex MZK-EX300NP"; - - gpio-leds { - compatible = "gpio-leds"; - - wifi { - label = "mzk-ex300np:green:wifi"; - gpios = <&gpio3 0 1>; - }; - - wps { - label = "mzk-ex300np:green:wps"; - gpios = <&gpio1 5 1>; - }; - - rep { - label = "mzk-ex300np:blue:rep"; - gpios = <&gpio1 4 1>; - }; - - wifi1 { - label = "mzk-ex300np:blue:wifi1"; - gpios = <&gpio1 1 1>; - }; - - wifi2 { - label = "mzk-ex300np:blue:wifi2"; - gpios = <&gpio1 2 1>; - }; - - wifi3 { - label = "mzk-ex300np:blue:wifi3"; - gpios = <&gpio1 0 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio0 1 1>; - linux,code = <0x198>; - }; - - wps { - label = "wps"; - gpios = <&gpio1 3 0>; - linux,code = <0x211>; - }; - }; -}; - -&gpio1 { - status = "okay"; -}; - -&gpio3 { - status = "okay"; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80", "w25q64"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x730000>; - }; - - partition@780000 { - label = "Udata"; - reg = <0x780000 0x80000>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "spi refclk", "rgmii1", "wled"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - pinctrl-names = "default"; - pinctrl-0 = <&ephy_pins>; - mtd-mac-address = <&factory 0x4>; - mediatek,portmap = "llllw"; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; diff --git a/sys/gnu/dts/mips/MZK-EX750NP.dts b/sys/gnu/dts/mips/MZK-EX750NP.dts deleted file mode 100644 index 565b4356f0f..00000000000 --- a/sys/gnu/dts/mips/MZK-EX750NP.dts +++ /dev/null @@ -1,148 +0,0 @@ -/dts-v1/; - -#include "mt7620a.dtsi" - -/ { - compatible = "ralink,mt7620a-soc"; - model = "Planex MZK-EX750NP"; - - gpio-leds { - compatible = "gpio-leds"; - - power { - label = "mzk-ex750np:red:power"; - gpios = <&gpio0 14 1>; - }; - - wifi { - label = "mzk-ex750np:red:wifi"; - gpios = <&gpio3 0 1>; - }; - - wps { - label = "mzk-ex750np:green:wps"; - gpios = <&gpio0 10 1>; - }; - - rep { - label = "mzk-ex750np:blue:rep"; - gpios = <&gpio2 16 1>; - }; - - wifi1 { - label = "mzk-ex750np:blue:wifi1"; - gpios = <&gpio2 19 1>; - }; - - wifi2 { - label = "mzk-ex750np:blue:wifi2"; - gpios = <&gpio2 18 1>; - }; - - wifi3 { - label = "mzk-ex750np:blue:wifi3"; - gpios = <&gpio2 17 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio0 9 1>; - linux,code = <0x198>; - }; - - wps { - label = "wps"; - gpios = <&gpio0 13 0>; - linux,code = <0x211>; - }; - }; -}; - -&gpio2 { - status = "okay"; -}; - -&gpio3 { - status = "okay"; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80", "w25q64"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x730000>; - }; - - partition@780000 { - label = "Udata"; - reg = <0x780000 0x80000>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "uartf", "nd_sd", "rgmii2", "wled"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - pinctrl-names = "default"; - pinctrl-0 = <&ephy_pins>; - mtd-mac-address = <&factory 0x4>; - mediatek,portmap = "llllw"; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; - -&pcie { - status = "okay"; - - pcie-bridge { - mt76@0,0 { - reg = <0x0000 0 0 0 0>; - device_type = "pci"; - mediatek,mtd-eeprom = <&factory 0x8000>; - mediatek,2ghz = <0>; - }; - }; -}; diff --git a/sys/gnu/dts/mips/MZK-W04N-XX.dts b/sys/gnu/dts/mips/MZK-W04N-XX.dts deleted file mode 100644 index 5c198c9c779..00000000000 --- a/sys/gnu/dts/mips/MZK-W04N-XX.dts +++ /dev/null @@ -1,94 +0,0 @@ -/dts-v1/; - -#include "rt2880.dtsi" - -/ { - compatible = "MZK-WNH", "ralink,rt2880-soc"; - model = "Planex MZK-WNH"; - -/* - memory@0 { - device_type = "memory"; - reg = <0x0 0x2000000>; - }; -*/ - - cfi@1f000000 { - compatible = "cfi-flash"; - reg = <0x1f000000 0x800000>; - bank-width = <2>; - device-width = <2>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "Bootloader"; - reg = <0x0 0x30000>; - read-only; - }; - - devdata: partition@30000 { - label = "Config"; - reg = <0x00030000 0x00010000>; - read-only; - }; - - factory: partition@40000 { - label = "Factory"; - reg = <0x00040000 0x00010000>; - read-only; - }; - kernel: partition@50000 { - label = "kernel"; - reg = <0x00050000 0x000f0000>; - read-only; - }; - rootfs: partition@160000 { - label = "rootfs"; - reg = <0x00140000 0x002c0000>; - read-only; - }; - upgrade: partition@400000 { - label = "upgrade"; - reg = <0x00050000 0x003b0000>; - read-only; - }; - - }; - - gpio-leds { - compatible = "gpio-leds"; - - status { - label = "status"; - gpios = <&gpio0 12 0>; - }; - - }; - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio0 10 1>; - linux,code = <0x198>; - }; - - }; - - ip17x@0 { - compatible = "icplus,ip17x"; - }; - -}; - -ðernet { - mtd-mac-address = <&factory 0x28>; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; diff --git a/sys/gnu/dts/mips/MZK-W300NH2.dts b/sys/gnu/dts/mips/MZK-W300NH2.dts deleted file mode 100644 index 987d6a7c0d2..00000000000 --- a/sys/gnu/dts/mips/MZK-W300NH2.dts +++ /dev/null @@ -1,111 +0,0 @@ -/dts-v1/; - -#include "rt3050.dtsi" - -/ { - compatible = "MZK-W300NH2", "ralink,rt3052-soc"; - model = "Planex MZK-W300NH2"; - - cfi@1f000000 { - compatible = "cfi-flash"; - reg = <0x1f000000 0x800000>; - bank-width = <2>; - device-width = <2>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@3e0000 { - label = "cimage"; - reg = <0x3e0000 0x20000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x390000>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - power { - label = "mzk-w300nh2:green:power"; - gpios = <&gpio0 9 1>; - }; - - wlan { - label = "mzk-w300nh2:amber:wlan"; - gpios = <&gpio0 14 1>; - }; - - wps { - label = "mzk-w300nh2:amber:wps"; - gpios = <&gpio0 11 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - wps { - label = "wps"; - gpios = <&gpio0 12 1>; - linux,code = <0x211>; - }; - - reset { - label = "reset"; - gpios = <&gpio0 0 1>; - linux,code = <0x198>; - }; - - rt { - label = "rt"; - gpios = <&gpio0 13 1>; - linux,code = <0x100>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - mtd-mac-address = <&factory 0x4>; -}; - -&esw { - mediatek,portmap = <0x2f>; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; diff --git a/sys/gnu/dts/mips/MZK-WDPR.dts b/sys/gnu/dts/mips/MZK-WDPR.dts deleted file mode 100644 index ff26b153b6c..00000000000 --- a/sys/gnu/dts/mips/MZK-WDPR.dts +++ /dev/null @@ -1,86 +0,0 @@ -/dts-v1/; - -#include "rt3050.dtsi" - -/ { - compatible = "MZK-WDPR", "ralink,rt3052-soc"; - model = "Planex MZK-WDPR"; - - chosen { - bootargs = "console=ttyS0,115200"; - }; - - cfi@1f000000 { - compatible = "cfi-flash"; - reg = <0x1f000000 0x800000>; - - bank-width = <2>; - device-width = <2>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@7f0000 { - label = "Data3G"; - reg = <0x7f0000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x680000>; - }; - }; - - gpio-export { - compatible = "gpio-export"; - - lcd_ctrl1 { - gpio-export,name = "lcd_ctrl1"; - gpio-export,output = <0>; - gpios = <&gpio0 1 0>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - mtd-mac-address = <&factory 0x28>; -}; - -&esw { - mediatek,portmap = <0x2f>; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; - -&otg { - status = "okay"; -}; diff --git a/sys/gnu/dts/mips/MicroWRT.dts b/sys/gnu/dts/mips/MicroWRT.dts deleted file mode 100644 index 07e01550a7f..00000000000 --- a/sys/gnu/dts/mips/MicroWRT.dts +++ /dev/null @@ -1,107 +0,0 @@ -/dts-v1/; - -#include "mt7620a.dtsi" - -/ { - compatible = "microwrt", "ralink,mt7620a-soc"; - model = "Microduino MicroWRT"; - - chosen { - bootargs = "console=ttyS0,115200"; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio0 1 1>; - linux,code = <0x198>; - }; - - wps { - label = "wps"; - gpios = <&gpio0 2 1>; - linux,code = <0x211>; - }; - }; -}; - -&gpio2 { - status = "okay"; -}; - -&gpio3 { - status = "okay"; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80", "w25q128"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x20000>; - read-only; - }; - - partition@20000 { - label = "u-boot-env"; - reg = <0x20000 0x10000>; - read-only; - }; - - factory: partition@30000 { - label = "factory"; - reg = <0x30000 0x10000>; - read-only; - }; - - partition@40000 { - label = "firmware"; - reg = <0x40000 0xfc0000>; - }; - }; -}; - -&ehci { - status = "okay"; -}; - -&ohci { - status = "okay"; -}; - -&pcie { - status = "okay"; -}; - -ðernet { - pinctrl-names = "default"; - pinctrl-0 = <&ephy_pins>; - mtd-mac-address = <&factory 0x4>; - mediatek,portmap = "llllw"; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; - -&pinctrl { - state_default: pinctrl0 { - default { - ralink,group = "wled", "i2c", "wdt", "uartf"; - ralink,function = "gpio"; - }; - }; -}; diff --git a/sys/gnu/dts/mips/NA930.dts b/sys/gnu/dts/mips/NA930.dts deleted file mode 100644 index 4093932a50e..00000000000 --- a/sys/gnu/dts/mips/NA930.dts +++ /dev/null @@ -1,172 +0,0 @@ -/dts-v1/; - -#include "mt7620a.dtsi" - -/ { - compatible = "ralink,mt7620a-eval-board", "ralink,mt7620a-soc"; - model = "Sercomm NA930"; - - chosen { - bootargs = "console=ttyS1,57600"; - }; - - nand { - #address-cells = <1>; - #size-cells = <1>; - compatible = "mtk,mt7620-nand"; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x20000>; - read-only; - }; - - partition@200000 { - label = "factory"; - reg = <0x200000 0x40000>; - read-only; - }; - - partition@240000 { - label = "Config"; - reg = <0x240000 0x400000>; - read-only; - }; - - partition@640000 { - label = "firmware"; - reg = <0x640000 0x1400000>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio0 11 1>; - linux,code = <0x198>; - }; - - zwave { - label = "zwave"; - gpios = <&gpio0 12 1>; - linux,code = <0x100>; - }; - - wps { - label = "wps"; - gpios = <&gpio0 14 1>; - linux,code = <0x211>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - zwave { - label = "na930:blue:zwave"; - gpios = <&gpio2 0 1>; - }; - - status { - label = "na930:blue:status"; - gpios = <&gpio2 26 1>; - }; - - service { - label = "na930:blue:service"; - gpios = <&gpio2 28 1>; - }; - - power { - label = "na930:blue:power"; - gpios = <&gpio2 29 1>; - }; - }; - - gpio_export { - compatible = "gpio-export"; - #size-cells = <0>; - - telit { - gpio-export,name = "telit"; - gpio-export,output = <1>; - gpios = <&gpio0 13 0>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "rgmii2", "spi", "ephy"; - ralink,function = "gpio"; - }; - - uartf_gpio { - ralink,group = "uartf"; - ralink,function = "gpio uartf"; - }; - }; -}; - -&uart { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&gpio2 { - status = "okay"; -}; - -ðernet { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii1_pins &mdio_pins>; - mediatek,portmap = "llllw"; - - port@4 { - status = "okay"; - phy-handle = <&phy4>; - phy-mode = "rgmii"; - }; - - port@5 { - status = "okay"; - phy-handle = <&phy5>; - phy-mode = "rgmii"; - }; - - mdio-bus { - status = "okay"; - - phy4: ethernet-phy@4 { - reg = <4>; - phy-mode = "rgmii"; - }; - - phy5: ethernet-phy@5 { - reg = <5>; - phy-mode = "rgmii"; - }; - }; -}; - -&gsw { - mediatek,port4 = "gmac"; -}; - -&ehci { - status = "okay"; -}; - -&ohci { - status = "okay"; -}; diff --git a/sys/gnu/dts/mips/NBG-419N.dts b/sys/gnu/dts/mips/NBG-419N.dts deleted file mode 100644 index 59ab665da71..00000000000 --- a/sys/gnu/dts/mips/NBG-419N.dts +++ /dev/null @@ -1,94 +0,0 @@ -/dts-v1/; - -#include "rt3050.dtsi" - -/ { - compatible = "NBG-419N", "ralink,rt3052-soc"; - model = "ZyXEL NBG-419N"; - - cfi@1f000000 { - compatible = "cfi-flash"; - reg = <0x1f000000 0x800000>; - bank-width = <2>; - device-width = <2>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x3b0000>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - power { - label = "nbg-419n:green:power"; - gpios = <&gpio0 9 1>; - }; - - wps { - label = "nbg-419n:green:wps"; - gpios = <&gpio0 14 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio0 10 1>; - linux,code = <0x198>; - }; - - wps { - label = "wps"; - gpios = <&gpio0 0 1>; - linux,code = <0x211>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - mtd-mac-address = <&factory 0x28>; -}; - -&esw { - mediatek,portmap = <0x2f>; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; diff --git a/sys/gnu/dts/mips/NCS601W.dts b/sys/gnu/dts/mips/NCS601W.dts deleted file mode 100644 index 1942b0f9086..00000000000 --- a/sys/gnu/dts/mips/NCS601W.dts +++ /dev/null @@ -1,73 +0,0 @@ -/dts-v1/; - -#include "rt5350.dtsi" - -/ { - compatible = "NCS601W", "ralink,rt5350-soc"; - model = "Wansview NCS601W"; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80", "s25fl064k"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x7b0000>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - mtd-mac-address = <&factory 0x4>; -}; - -&esw { - mediatek,portmap = <0x2f>; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; - -&ehci { - status = "okay"; -}; - -&ohci { - status = "okay"; -}; diff --git a/sys/gnu/dts/mips/NW718.dts b/sys/gnu/dts/mips/NW718.dts deleted file mode 100644 index 06c6b0d62dc..00000000000 --- a/sys/gnu/dts/mips/NW718.dts +++ /dev/null @@ -1,107 +0,0 @@ -/dts-v1/; - -#include "rt3050.dtsi" - -/ { - compatible = "NW718", "ralink,rt3050-soc"; - model = "Netcore NW718"; - - gpio-leds { - compatible = "gpio-leds"; - - cpu { - label = "nw718:amber:cpu"; - gpios = <&gpio0 13 1>; - }; - - usb { - label = "nw718:amber:usb"; - gpios = <&gpio0 8 1>; - }; - - wps { - label = "nw718:amber:wps"; - gpios = <&gpio0 14 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio0 10 1>; - linux,code = <0x198>; - }; - - wps { - label = "wps"; - gpios = <&gpio0 0 1>; - linux,code = <0x211>; - }; - }; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80", "mx25l3205d"; - spi-max-frequency = <25000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "config"; - reg = <0x30000 0x20000>; - read-only; - }; - - factory: partition@50000 { - label = "factory"; - reg = <0x50000 0x10000>; - read-only; - }; - - partition@60000 { - label = "firmware"; - reg = <0x60000 0x3a0000>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - mtd-mac-address = <&factory 0x4>; -}; - -&esw { - mediatek,portmap = <0x2f>; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; - -&otg { - status = "okay"; -}; diff --git a/sys/gnu/dts/mips/OY-0001.dts b/sys/gnu/dts/mips/OY-0001.dts deleted file mode 100644 index 6bf1ad6be70..00000000000 --- a/sys/gnu/dts/mips/OY-0001.dts +++ /dev/null @@ -1,122 +0,0 @@ -/dts-v1/; - -#include "mt7620a.dtsi" - -/ { - compatible = "ralink,mt7620a-soc"; - model = "OY-0001"; - - chosen { - bootargs = "console=ttyS0,115200"; - }; - - gpio-leds { - compatible = "gpio-leds"; - - powerled { - label = "oy-0001:green:power"; - gpios = <&gpio0 9 1>; - }; - - wifiled { - label = "oy-0001:green:wifi"; - gpios = <&gpio3 0 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - s1 { - label = "reset"; - gpios = <&gpio0 1 1>; - linux,code = <0x198>; - }; - }; -}; - -&gpio2 { - status = "okay"; -}; - -&gpio3 { - status = "okay"; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80", "w25q128"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0xfb0000>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "uartf", "rgmii1", "rgmii2", "wled", "nd_sd"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - pinctrl-names = "default"; - pinctrl-0 = <&ephy_pins>; - mediatek,portmap = "llllw"; -}; - -&gsw { - mediatek,port4 = "ephy"; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; - -&sdhci { - status = "okay"; -}; - -&ehci { - status = "okay"; -}; - -&ohci { - status = "okay"; -}; - -&pcie { - status = "okay"; -}; diff --git a/sys/gnu/dts/mips/PBR-M1.dts b/sys/gnu/dts/mips/PBR-M1.dts deleted file mode 100644 index 708c7c52ddf..00000000000 --- a/sys/gnu/dts/mips/PBR-M1.dts +++ /dev/null @@ -1,188 +0,0 @@ -/dts-v1/; - -#include "mt7621.dtsi" - -/ { - compatible = "mediatek,mt7621-eval-board", "mediatek,mt7621-soc"; - model = "PBR-M1"; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x10000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200"; - }; - - palmbus: palmbus@1E000000 { - i2c: i2c@900 { - compatible = "ralink,i2c-mt7621"; - reg = <0x900 0x100>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c_pins>; - status = "okay"; - - pcf8563: rtc@51 { - status = "okay"; - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - power { - label = "pbr-m1:blue:power"; - gpios = <&gpio0 31 1>; - }; - - sys { - label = "pbr-m1:blue:sys"; - gpios = <&gpio1 0 1>; - }; - - internet { - label = "pbr-m1:blue:internet"; - gpios = <&gpio0 29 1>; - }; - - wlan2g { - label = "pbr-m1:blue:wlan2g"; - gpios = <&gpio1 1 1>; - }; - - wlan5g { - label = "pbr-m1:blue:wlan5g"; - gpios = <&gpio0 28 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio0 18 1>; - linux,code = <0x198>; - }; - }; - - gpio_export { - compatible = "gpio-export"; - #size-cells = <0>; - - power_usb2 { - gpio-export,name = "power_usb2"; - gpio-export,output = <1>; - gpios = <&gpio0 22 0>; - }; - - power_usb3 { - gpio-export,name = "power_usb3"; - gpio-export,output = <1>; - gpios = <&gpio0 25 0>; - }; - - power_sata { - gpio-export,name = "power_sata"; - gpio-export,output = <1>; - gpios = <&gpio0 27 0>; - }; - }; - - beeper: beeper { - compatible = "gpio-beeper"; - gpios = <&gpio0 26 1>; - }; -}; - -&sdhci { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&sdhci_pins>; -}; - -&xhci { - status = "okay"; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0xfb0000>; - }; - }; -}; - -&pcie { - status = "okay"; - - pcie0 { - mt76@0,0 { - reg = <0x0000 0 0 0 0>; - device_type = "pci"; - mediatek,mtd-eeprom = <&factory 0x8000>; - mediatek,2ghz = <0>; - }; - }; - - pcie1 { - mt76@1,0 { - reg = <0x0000 0 0 0 0>; - device_type = "pci"; - mediatek,mtd-eeprom = <&factory 0x0000>; - mediatek,5ghz = <0>; - }; - }; -}; - -ðernet { - mtd-mac-address = <&factory 0xe000>; -}; - - - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "wdt", "rgmii2", "jtag", "mdio"; - ralink,function = "gpio"; - }; - }; -}; diff --git a/sys/gnu/dts/mips/PSG1208.dts b/sys/gnu/dts/mips/PSG1208.dts deleted file mode 100644 index dc1adc4c731..00000000000 --- a/sys/gnu/dts/mips/PSG1208.dts +++ /dev/null @@ -1,112 +0,0 @@ -/dts-v1/; - -#include "mt7620a.dtsi" - -/ { - compatible = "PSG1208", "ralink,mt7620a-soc"; - model = "Phicomm PSG1208"; - - gpio-leds { - compatible = "gpio-leds"; - - wan { - label = "psg1208:white:wps"; - gpios = <&gpio1 15 1>; - }; - - wlan { - label = "psg1208:white:wlan2g"; - gpios = <&gpio3 0 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio0 1 1>; - linux,code = <0x198>; - }; - }; -}; - -&gpio1 { - status = "okay"; -}; - -&gpio3 { - status = "okay"; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80", "en25q64"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@20000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@30000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@40000 { - label = "firmware"; - reg = <0x50000 0x7b0000>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "uartf", "rgmii1", "rgmii2", "ephy", "wled", "nd_sd"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - pinctrl-names = "default"; - pinctrl-0 = <&ephy_pins>; - mtd-mac-address = <&factory 0x4>; - mediatek,portmap = "llllw"; -}; - -&pcie { - status = "okay"; - - pcie-bridge { - mt76@0,0 { - reg = <0x0000 0 0 0 0>; - device_type = "pci"; - mediatek,mtd-eeprom = <&factory 0x8000>; - mediatek,2ghz = <0>; - }; - }; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; diff --git a/sys/gnu/dts/mips/PSR-680W.dts b/sys/gnu/dts/mips/PSR-680W.dts deleted file mode 100644 index c4c4522afc5..00000000000 --- a/sys/gnu/dts/mips/PSR-680W.dts +++ /dev/null @@ -1,91 +0,0 @@ -/dts-v1/; - -#include "rt3050.dtsi" - -/ { - compatible = "PSR-680W", "ralink,rt3052-soc"; - model = "Petatel PSR-680W Wireless 3G Router"; - - chosen { - bootargs = "console=ttyS0,115200"; - }; - - cfi@1f000000 { - compatible = "cfi-flash"; - reg = <0x1f000000 0x800000>; - bank-width = <2>; - device-width = <2>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x3b0000>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - wan { - label = "psr-680w:red:wan"; - gpios = <&gpio0 19 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio0 0 1>; - linux,code = <0x198>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - mtd-mac-address = <&factory 0x4>; -}; - -&esw { - mediatek,portmap = <0x3e>; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; - -&otg { - status = "okay"; -}; diff --git a/sys/gnu/dts/mips/PWH2004.dts b/sys/gnu/dts/mips/PWH2004.dts deleted file mode 100644 index 51f43928f46..00000000000 --- a/sys/gnu/dts/mips/PWH2004.dts +++ /dev/null @@ -1,84 +0,0 @@ -/dts-v1/; - -#include "rt3050.dtsi" - -/ { - compatible = "PWH2004", "ralink,rt3052-soc"; - model = "Prolink PWH2004"; - - cfi@1f000000 { - compatible = "cfi-flash"; - reg = <0x1f000000 0x800000>; - bank-width = <2>; - device-width = <2>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x7b0000>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - wifi { - label = "pwh2004:red:wifi"; - gpios = <&gpio0 14 1>; - }; - - power { - label = "pwh2004:green:power"; - gpios = <&gpio0 9 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - wps { - label = "wps"; - gpios = <&gpio0 12 1>; - linux,code = <0x198>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; -}; - -&esw { - mediatek,portmap = <0x2f>; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; diff --git a/sys/gnu/dts/mips/PX-4885-4M.dts b/sys/gnu/dts/mips/PX-4885-4M.dts deleted file mode 100644 index fb2b14cdc15..00000000000 --- a/sys/gnu/dts/mips/PX-4885-4M.dts +++ /dev/null @@ -1,39 +0,0 @@ -/dts-v1/; - -#include "PX-4885.dtsi" - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80", "mx25l3205d"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x20000>; - read-only; - }; - - partition@20000 { - label = "devdata"; - reg = <0x20000 0x20000>; - read-only; - }; - - factory: partition@40000 { - label = "devconf"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x3b0000>; - }; - }; -}; diff --git a/sys/gnu/dts/mips/PX-4885-8M.dts b/sys/gnu/dts/mips/PX-4885-8M.dts deleted file mode 100644 index 6367a5eb2d1..00000000000 --- a/sys/gnu/dts/mips/PX-4885-8M.dts +++ /dev/null @@ -1,39 +0,0 @@ -/dts-v1/; - -#include "PX-4885.dtsi" - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80", "mx25l3205d"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x20000>; - read-only; - }; - - partition@20000 { - label = "devdata"; - reg = <0x20000 0x20000>; - read-only; - }; - - factory: partition@40000 { - label = "devconf"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x7b0000>; - }; - }; -}; diff --git a/sys/gnu/dts/mips/PX-4885.dtsi b/sys/gnu/dts/mips/PX-4885.dtsi deleted file mode 100644 index b135b5747b5..00000000000 --- a/sys/gnu/dts/mips/PX-4885.dtsi +++ /dev/null @@ -1,54 +0,0 @@ -#include "rt5350.dtsi" - -/ { - compatible = "PX-4885", "ralink,rt5350-soc"; - model = "7Links PX-4885"; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio0 10 1>; - linux,code = <0x198>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - orange { - label = "px-4885:orange:wifi"; - gpios = <&gpio0 18 1>; - }; - - blue { - label = "px-4885:blue:storage"; - gpios = <&gpio0 19 1>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "jtag", "uartf"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - mtd-mac-address = <&factory 0x28>; -}; - -&esw { - mediatek,portmap = <0x3f>; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; diff --git a/sys/gnu/dts/mips/RE6500.dts b/sys/gnu/dts/mips/RE6500.dts deleted file mode 100644 index 39205c41acf..00000000000 --- a/sys/gnu/dts/mips/RE6500.dts +++ /dev/null @@ -1,121 +0,0 @@ -/dts-v1/; - -#include "mt7621.dtsi" - -/ { - compatible = "mediatek,mt7621-eval-board", "mediatek,mt7621-soc"; - model = "Linksys RE6500"; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x4000000>; - }; - - chosen { - bootargs = "console=ttyS0,57600"; - }; - - gpio-leds { - compatible = "gpio-leds"; - - wifi { - label = "re6500:orange:wifi"; - gpios = <&gpio0 0 0>; - }; - - power { - label = "re6500:white:power"; - gpios = <&gpio0 9 0>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - wps { - label = "wps"; - gpios = <&gpio0 10 1>; - linux,code = <0x211>; - }; - - reset { - label = "reset"; - gpios = <&gpio0 11 0>; - linux,code = <0x198>; - }; - }; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80", "en25q64"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x7b0000>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "uart2", "uart3", "rgmii2"; - ralink,function = "gpio"; - }; - }; -}; - -&pcie { - status = "okay"; - - pcie0 { - mt76@0,0 { - reg = <0x0000 0 0 0 0>; - device_type = "pci"; - mediatek,mtd-eeprom = <&factory 0x0000>; - mediatek,2ghz = <0>; - }; - }; - - pcie1 { - mt76@1,0 { - reg = <0x0000 0 0 0 0>; - device_type = "pci"; - mediatek,mtd-eeprom = <&factory 0x8000>; - mediatek,5ghz = <0>; - }; - }; -}; - -ðernet { - mtd-mac-address = <&factory 0x2e>; -}; diff --git a/sys/gnu/dts/mips/RP-N53.dts b/sys/gnu/dts/mips/RP-N53.dts deleted file mode 100644 index c661be3a28c..00000000000 --- a/sys/gnu/dts/mips/RP-N53.dts +++ /dev/null @@ -1,164 +0,0 @@ -/dts-v1/; - -#include "mt7620a.dtsi" - -/ { - compatible = "asus,rp-n53", "ralink,mt7620a-soc"; - model = "Asus RP-N53"; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - touch { - label = "touch"; - gpios = <&gpio1 0 1>; - linux,code = <0x100>; - }; - - wps { - label = "wps"; - gpios = <&gpio1 1 1>; - linux,code = <0x100>; - }; - - reset { - label = "reset"; - gpios = <&gpio1 2 1>; - linux,code = <0x100>; - }; - - audio { - label = "audio"; - gpios = <&gpio1 3 0>; - linux,code = <0x101>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - backlight { - label = "rp-n53:white:back"; - gpios = <&gpio1 4 1>; - }; - - wifi0 { - label = "rp-n53:blue:5g3"; - gpios = <&gpio1 5 1>; - }; - - wifi1 { - label = "rp-n53:blue:5g2"; - gpios = <&gpio1 6 1>; - }; - - wifi2 { - label = "rp-n53:blue:5g1"; - gpios = <&gpio1 7 1>; - }; - - wifi3 { - label = "rp-n53:blue:wifi"; - gpios = <&gpio1 8 1>; - }; - - wifi4 { - label = "rp-n53:blue:2g1"; - gpios = <&gpio1 9 1>; - }; - - wifi5 { - label = "rp-n53:blue:2g2"; - gpios = <&gpio1 10 1>; - }; - - wifi6 { - label = "rp-n53:blue:2g3"; - gpios = <&gpio1 11 1>; - }; - }; -}; - -&gpio1 { - status = "okay"; -}; - -&i2c { - status = "okay"; -}; - -&i2s { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pcm_i2s_pins>; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x7b0000>; - }; - }; -}; - -&pcm { - status = "okay"; -}; - -&gdma { - status = "okay"; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "mdio", "rgmii1"; - ralink,function = "gpio"; - }; - }; -}; - -&gsw { - mediatek,port4 = "ephy"; - pinctrl-names = "default"; - pinctrl-0 = <&ephy_pins>; -}; - -&pcie { - status = "okay"; -}; diff --git a/sys/gnu/dts/mips/RT-G32-B1.dts b/sys/gnu/dts/mips/RT-G32-B1.dts deleted file mode 100644 index ab8e3fdad3c..00000000000 --- a/sys/gnu/dts/mips/RT-G32-B1.dts +++ /dev/null @@ -1,84 +0,0 @@ -/dts-v1/; - -#include "rt3050.dtsi" - -/ { - compatible = "RT-G32-B1", "ralink,rt3050-soc"; - model = "Asus RT-G32 B1"; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio0 10 1>; - linux,code = <0x198>; - }; - - wps { - label = "wps"; - gpios = <&gpio0 0 1>; - linux,code = <0x211>; - }; - }; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80", "mx25l3205d"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "devdata"; - reg = <0x30000 0x10000>; - read-only; - }; - - devconf: partition@40000 { - label = "devconf"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x3b0000>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - mtd-mac-address = <&devconf 0x4>; -}; - -&esw { - mediatek,portmap = <0x2f>; -}; - -&wmac { - ralink,mtd-eeprom = <&devconf 0>; -}; diff --git a/sys/gnu/dts/mips/RT-N10-PLUS.dts b/sys/gnu/dts/mips/RT-N10-PLUS.dts deleted file mode 100644 index 43535d417bf..00000000000 --- a/sys/gnu/dts/mips/RT-N10-PLUS.dts +++ /dev/null @@ -1,80 +0,0 @@ -/dts-v1/; - -#include "rt3050.dtsi" - -/ { - compatible = "RT-N10-PLUS", "ralink,rt3050-soc"; - model = "Asus RT-N10+"; - - cfi@1f000000 { - compatible = "cfi-flash"; - reg = <0x1f000000 0x800000>; - bank-width = <2>; - device-width = <2>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "devdata"; - reg = <0x30000 0x10000>; - read-only; - }; - - devconf: partition@40000 { - label = "devconf"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x3b0000>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - wps { - label = "rt-n10-plus:green:wps"; - gpios = <&gpio0 14 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio0 10 1>; - linux,code = <0x198>; - }; - - wps { - label = "wps"; - gpios = <&gpio0 0 1>; - linux,code = <0x211>; - }; - }; -}; - -ðernet { - mtd-mac-address = <&devconf 0x4>; -}; - -&esw { - mediatek,portmap = <0x3e>; -}; - -&wmac { - ralink,mtd-eeprom = <&devconf 0>; -}; diff --git a/sys/gnu/dts/mips/RT-N13U.dts b/sys/gnu/dts/mips/RT-N13U.dts deleted file mode 100644 index 14cff67855a..00000000000 --- a/sys/gnu/dts/mips/RT-N13U.dts +++ /dev/null @@ -1,98 +0,0 @@ -/dts-v1/; - -#include "rt3050.dtsi" - -/ { - compatible = "RT-N13U", "ralink,rt3052-soc"; - model = "Asus RT-N13U"; - - cfi@1f000000 { - compatible = "cfi-flash"; - reg = <0x1f000000 0x800000>; - bank-width = <2>; - device-width = <2>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x7b0000>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - power { - label = "rt-n13u:blue:power"; - gpios = <&gpio0 7 1>; - }; - - wifi { - label = "rt-n13u:blue:wifi"; - gpios = <&gpio0 8 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <10>; - - reset { - label = "reset"; - gpios = <&gpio0 10 1>; - linux,code = <0x198>; - }; - - wps { - label = "wps"; - gpios = <&gpio0 0 1>; - linux,code = <0x211>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - mtd-mac-address = <&factory 0x28>; -}; - -&esw { - mediatek,portmap = <0x2f>; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; - -&otg { - status = "okay"; -}; diff --git a/sys/gnu/dts/mips/RT-N14U.dts b/sys/gnu/dts/mips/RT-N14U.dts deleted file mode 100644 index 05263e165d6..00000000000 --- a/sys/gnu/dts/mips/RT-N14U.dts +++ /dev/null @@ -1,126 +0,0 @@ -/dts-v1/; - -#include "mt7620n.dtsi" - -/ { - compatible = "asus,rt-n14u", "ralink,mt7620n-soc"; - model = "Asus RT-N14U"; - - gpio-leds { - compatible = "gpio-leds"; - - wan { - label = "rt-n14u:blue:wan"; - gpios = <&gpio2 0 1>; - }; - - lan { - label = "rt-n14u:blue:lan"; - gpios = <&gpio2 1 1>; - }; - - usb { - label = "rt-n14u:blue:usb"; - gpios = <&gpio2 2 1>; - }; - - power { - label = "rt-n14u:blue:power"; - gpios = <&gpio2 3 1>; - }; - - air { - label = "rt-n14u:blue:air"; - gpios = <&gpio3 0 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio0 1 1>; - linux,code = <0x198>; - }; - - wps { - label = "wps"; - gpios = <&gpio0 2 1>; - linux,code = <0x211>; - }; - }; -}; - -&gpio2 { - status = "okay"; -}; - -&gpio3 { - status = "okay"; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80", "w25q128"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0xfb0000>; - }; - }; -}; - -&ehci { - status = "okay"; -}; - -&ohci { - status = "okay"; -}; - -ðernet { - mtd-mac-address = <&factory 0x4>; - mediatek,portmap = "wllll"; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; - -&pinctrl { - state_default: pinctrl0 { - default { - ralink,group = "ephy", "wled", "i2c"; - ralink,function = "gpio"; - }; - }; -}; diff --git a/sys/gnu/dts/mips/RT-N15.dts b/sys/gnu/dts/mips/RT-N15.dts deleted file mode 100644 index d5bcbe3409e..00000000000 --- a/sys/gnu/dts/mips/RT-N15.dts +++ /dev/null @@ -1,111 +0,0 @@ -/dts-v1/; - -#include "rt2880.dtsi" - -/ { - #address-cells = <1>; - #size-cells = <1>; - compatible = "RT-N15", "ralink,rt2880-soc"; - model = "Asus RT-N15"; - - cfi@1f000000 { - compatible = "cfi-flash"; - reg = <0x1f000000 0x800000>; - bank-width = <2>; - device-width = <2>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "uboot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "uboot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x3b0000>; - }; - }; - - rtl8366s { - compatible = "realtek,rtl8366s"; - gpio-sda = <&gpio0 1 0>; - gpio-sck = <&gpio0 2 0>; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <100>; - - wps { - label = "wps"; - gpios = <&gpio0 0 0>; - linux,code = <0x211>; - }; - - reset { - label = "reset"; - gpios = <&gpio0 12 0>; - linux,code = <0x198>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - power { - label = "rt-n15:blue:power"; - gpios = <&gpio0 11 1>; - }; - }; -}; - -&gpio0 { - status = "okay"; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "uartlite", "mdio"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - status = "okay"; - mtd-mac-address = <&factory 0x4>; - - port@0 { - mediatek,fixed-link = <1000 1 1 1>; - }; - - mdio-bus { - status = "okay"; - - phy0: ethernet-phy@0 { - phy-mode = "mii"; - reg = <0>; - }; - }; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; diff --git a/sys/gnu/dts/mips/RT-N56U.dts b/sys/gnu/dts/mips/RT-N56U.dts deleted file mode 100644 index d3a1f1bbfb9..00000000000 --- a/sys/gnu/dts/mips/RT-N56U.dts +++ /dev/null @@ -1,149 +0,0 @@ -/dts-v1/; - -#include "rt3883.dtsi" - -/ { - compatible = "RT-N56U", "ralink,rt3883-soc"; - model = "Asus RT-N56U"; - - nor-flash@1c000000 { - compatible = "cfi-flash"; - reg = <0x1c000000 0x800000>; - bank-width = <2>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - reg = <0x0 0x0030000>; - label = "u-boot"; - read-only; - }; - - partition@30000 { - reg = <0x00030000 0x00010000>; - label = "u-boot-env"; - read-only; - }; - - factory: partition@40000 { - reg = <0x00040000 0x00010000>; - label = "factory"; - read-only; - }; - - partition@50000 { - reg = <0x00050000 0x007b0000>; - label = "firmware"; - }; - }; - - rtl8367 { - compatible = "realtek,rtl8367"; - gpio-sda = <&gpio0 1 0>; - gpio-sck = <&gpio0 2 0>; - realtek,extif1 = <1 0 1 1 1 1 1 1 2>; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <100>; - - reset { - label = "reset"; - gpios = <&gpio0 13 1>; - linux,code = <0x198>; - }; - - wps { - label = "wps"; - gpios = <&gpio1 2 1>; - linux,code = <0x211>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - power { - label = "rt-n56u:blue:power"; - gpios = <&gpio0 0 1>; - }; - - lan { - label = "rt-n56u:blue:lan"; - gpios = <&gpio0 19 1>; - }; - - wan { - label = "rt-n56u:blue:wan"; - gpios = <&gpio1 3 1>; - }; - - usb { - label = "rt-n56u:blue:usb"; - gpios = <&gpio1 0 1>; - }; - }; -}; - -&gpio1 { - status = "okay"; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "spi", "i2c", "jtag", "uartf"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - mtd-mac-address = <&factory 0x4>; - - port@0 { - mediatek,fixed-link = <1000 1 1 1>; - }; -}; - -&pci { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pci_pins>; - - pci_pins: pci { - pci { - ralink,group = "pci"; - ralink,function = "pci-fnc"; - }; - }; - - host-bridge { - pci-bridge@1 { - status = "okay"; - - wmac@0,0 { - compatible = "ralink,rt2880-pci", "pciclass060400", "pciclass0604"; - reg = < 0x10000 0 0 0 0 >; - ralink,eeprom = "rt2x00pci_1_0.eeprom"; - }; - }; - }; -}; - -&wmac { - status = "okay"; - ralink,2ghz = <0>; - ralink,mtd-eeprom = <&factory 0>; -}; - -&ehci { - status = "okay"; -}; - -&ohci { - status = "okay"; -}; diff --git a/sys/gnu/dts/mips/RT5350F-OLINUXINO-EVB.dts b/sys/gnu/dts/mips/RT5350F-OLINUXINO-EVB.dts deleted file mode 100644 index 6c45d7a56e3..00000000000 --- a/sys/gnu/dts/mips/RT5350F-OLINUXINO-EVB.dts +++ /dev/null @@ -1,100 +0,0 @@ -/dts-v1/; - -#include "rt5350.dtsi" - -/ { - compatible = "RT5350F-OLINUXINO-EVB", "ralink,rt5350-soc"; - model = "Olimex RT5350F-OLinuXino-EVB"; - - gpio_export { - compatible = "gpio-export"; - #size-cells = <0>; - - relay1 { - gpio-export,name = "relay1"; - gpio-export,output = <0>; - gpios = <&gpio0 14 0>; - }; - - relay2 { - gpio-export,name = "relay2"; - gpio-export,output = <0>; - gpios = <&gpio0 12 0>; - }; - - button { - gpio-export,name = "button"; - gpios = <&gpio0 0 1>; - }; - }; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80", "s25fl064k"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x3b0000>; - }; - }; -}; - -&gpio1 { - status = "okay"; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - mtd-mac-address = <&factory 0x4>; -}; - -&esw { - mediatek,portmap = <0x2f>; - mediatek,led_polarity = <0x17>; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; - -&ehci { - status = "okay"; -}; - -&ohci { - status = "okay"; -}; diff --git a/sys/gnu/dts/mips/RT5350F-OLINUXINO.dts b/sys/gnu/dts/mips/RT5350F-OLINUXINO.dts deleted file mode 100644 index e59b4181217..00000000000 --- a/sys/gnu/dts/mips/RT5350F-OLINUXINO.dts +++ /dev/null @@ -1,78 +0,0 @@ -/dts-v1/; - -#include "rt5350.dtsi" - -/ { - compatible = "RT5350F-OLINUXINO", "ralink,rt5350-soc"; - model = "Olimex RT5350F-OLinuXino"; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80", "s25fl064k"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x3b0000>; - }; - }; -}; - -&gpio1 { - status = "okay"; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - mtd-mac-address = <&factory 0x4>; -}; - -&esw { - mediatek,portmap = <0x2f>; - mediatek,led_polarity = <0x17>; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; - -&ehci { - status = "okay"; -}; - -&ohci { - status = "okay"; -}; diff --git a/sys/gnu/dts/mips/RUT5XX.dts b/sys/gnu/dts/mips/RUT5XX.dts deleted file mode 100644 index 85c26d96bee..00000000000 --- a/sys/gnu/dts/mips/RUT5XX.dts +++ /dev/null @@ -1,91 +0,0 @@ -/dts-v1/; - -#include "rt3050.dtsi" - -/ { - compatible = "RUT5XX", "ralink,rt3050-soc"; - model = "Teltonika RUT5XX"; - - gpio-leds { - compatible = "gpio-leds"; - - status { - label = "rut5xx:green:status"; - gpios = <&gpio0 14 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio0 10 1>; - linux,code = <0x198>; - }; - }; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80", "n25q128a13"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0xfb0000>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - mtd-mac-address = <&factory 0x28>; -}; - -&esw { - mediatek,portmap = <0x3e>; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; - -&otg { - status = "okay"; -}; diff --git a/sys/gnu/dts/mips/SAP-G3200U3.dts b/sys/gnu/dts/mips/SAP-G3200U3.dts deleted file mode 100644 index d6f2f305766..00000000000 --- a/sys/gnu/dts/mips/SAP-G3200U3.dts +++ /dev/null @@ -1,122 +0,0 @@ -/dts-v1/; - -#include "mt7621.dtsi" - -/ { - compatible = "mediatek,mt7621-eval-board", "mediatek,mt7621-soc"; - model = "STORYLiNK SAP-G3200U3"; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x8000000>; - }; - - chosen { - bootargs = "console=ttyS0,57600"; - }; - - gpio-leds { - compatible = "gpio-leds"; - - usb { - label = "sap-g3200u3:green:usb"; - gpios = <&gpio0 13 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio0 16 1>; - linux,code = <0x198>; - }; - - rfkill { - label = "rfkill"; - gpios = <&gpio0 14 1>; - linux,code = <0xf7>; - }; - }; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80", "en25q64"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x1000>; - read-only; - }; - - partition@31000 { - label = "config"; - reg = <0x31000 0xf000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x7b0000>; - }; - }; -}; - -&pcie { - status = "okay"; - - pcie0 { - mt76@0,0 { - reg = <0x0000 0 0 0 0>; - device_type = "pci"; - mediatek,mtd-eeprom = <&factory 0x8000>; - mediatek,2ghz = <0>; - }; - }; - - pcie1 { - mt76@1,0 { - reg = <0x0000 0 0 0 0>; - device_type = "pci"; - mediatek,mtd-eeprom = <&factory 0x0000>; - mediatek,5ghz = <0>; - }; - }; -}; - -ðernet { - mtd-mac-address = <&factory 0xe006>; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "uart3", "jtag"; - ralink,function = "gpio"; - }; - }; -}; diff --git a/sys/gnu/dts/mips/SK-WB8.dts b/sys/gnu/dts/mips/SK-WB8.dts deleted file mode 100644 index 1fed89e11e4..00000000000 --- a/sys/gnu/dts/mips/SK-WB8.dts +++ /dev/null @@ -1,124 +0,0 @@ -/dts-v1/; - -#include "mt7621.dtsi" - -/ { - compatible = "mediatek,mt7621-eval-board", "mediatek,mt7621-soc"; - model = "SamKnows Whitebox 8"; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x8000000>; - }; - - chosen { - bootargs = "console=ttyS0,57600"; - }; - - gpio-leds { - compatible = "gpio-leds"; - - wps { - label = "sk-wb8:green:wps"; - gpios = <&gpio1 14 1>; - }; - - usb { - label = "sk-wb8:green:usb"; - gpios = <&gpio1 15 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - wps { - label = "wps"; - gpios = <&gpio1 11 1>; - linux,code = <0x211>; - }; - reset { - label = "reset"; - gpios = <&gpio1 9 1>; - linux,code = <0x198>; - }; - }; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x7b0000>; - }; - - partition@e30000 { - label = "recovery"; - reg = <0xe30000 0x1d0000>; - }; - - }; -}; - -&pcie { - status = "okay"; - - pcie0 { - mt76@0,0 { - reg = <0x0000 0 0 0 0>; - device_type = "pci"; - mediatek,mtd-eeprom = <&factory 0x8000>; - mediatek,2ghz = <0>; - }; - }; - - pcie1 { - mt76@1,0 { - reg = <0x0000 0 0 0 0>; - device_type = "pci"; - mediatek,mtd-eeprom = <&factory 0x0000>; - mediatek,5ghz = <0>; - }; - }; -}; - -ðernet { - mtd-mac-address = <&factory 0xe000>; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "uart2", "uart3", "rgmii2", "sdhci"; - ralink,function = "gpio"; - }; - }; -}; diff --git a/sys/gnu/dts/mips/SL-R7205.dts b/sys/gnu/dts/mips/SL-R7205.dts deleted file mode 100644 index f5884fbecd8..00000000000 --- a/sys/gnu/dts/mips/SL-R7205.dts +++ /dev/null @@ -1,93 +0,0 @@ -/dts-v1/; - -#include "rt3050.dtsi" - -/ { - compatible = "SL-R7205", "ralink,rt3052-soc"; - model = "Skyline SL-R7205 Wireless 3G Router"; - - cfi@1f000000 { - compatible = "cfi-flash"; - reg = <0x1f000000 0x800000>; - bank-width = <2>; - device-width = <2>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x3b0000>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - wifi { - label = "sl-r7205:green:wifi"; - gpios = <&gpio0 7 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio0 10 1>; - linux,code = <0x198>; - }; - - wps { - label = "wps"; - gpios = <&gpio0 0 1>; - linux,code = <0x211>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - mtd-mac-address = <&factory 0x4>; -}; - -&esw { - mediatek,portmap = <0x3e>; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; - -&otg { - status = "okay"; -}; diff --git a/sys/gnu/dts/mips/TEW-691GR.dts b/sys/gnu/dts/mips/TEW-691GR.dts deleted file mode 100644 index 750c24fbe93..00000000000 --- a/sys/gnu/dts/mips/TEW-691GR.dts +++ /dev/null @@ -1,107 +0,0 @@ -/dts-v1/; - -#include "rt3883.dtsi" - -/ { - compatible = "TEW-691GR", "ralink,rt3883-soc"; - model = "TRENDnet TEW-691GR"; - - nor-flash@1c000000 { - compatible = "cfi-flash"; - reg = <0x1c000000 0x800000>; - bank-width = <2>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - reg = <0x0 0x0030000>; - label = "u-boot"; - read-only; - }; - - partition@30000 { - reg = <0x00030000 0x00010000>; - label = "u-boot-env"; - read-only; - }; - - factory: partition@40000 { - reg = <0x00040000 0x00010000>; - label = "factory"; - read-only; - }; - - partition@50000 { - reg = <0x00050000 0x007b0000>; - label = "firmware"; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <100>; - - reset { - label = "reset"; - gpios = <&gpio0 10 1>; - linux,code = <0x198>; - }; - - wps { - label = "wps"; - gpios = <&gpio1 2 1>; - linux,code = <0x211>; - }; - - rfkill { - label = "rfkill"; - gpios = <&gpio0 0 1>; - linux,code = <0xf7>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - wps { - label = "tew-691gr:green:wps"; - gpios = <&gpio0 9 1>; - }; - }; -}; - -&gpio1 { - status = "okay"; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "spi", "i2c", "jtag", "uartf"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - mtd-mac-address = <&factory 0x28>; - - port@0 { - phy-handle = <&phy0>; - phy-mode = "rgmii"; - }; - - mdio-bus { - status = "okay"; - - phy0: ethernet-phy@0 { - reg = <0>; - }; - }; -}; - -&wmac { - ralink,5ghz = <0>; -}; diff --git a/sys/gnu/dts/mips/TEW-692GR.dts b/sys/gnu/dts/mips/TEW-692GR.dts deleted file mode 100644 index 5bba8a50b8d..00000000000 --- a/sys/gnu/dts/mips/TEW-692GR.dts +++ /dev/null @@ -1,126 +0,0 @@ -/dts-v1/; - -#include "rt3883.dtsi" - -/ { - compatible = "TEW-692GR", "ralink,rt3883-soc"; - model = "TRENDnet TEW-692GR"; - - nor-flash@1c000000 { - compatible = "cfi-flash"; - reg = <0x1c000000 0x800000>; - bank-width = <2>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - reg = <0x0 0x0030000>; - label = "u-boot"; - read-only; - }; - - partition@30000 { - reg = <0x00030000 0x00010000>; - label = "u-boot-env"; - read-only; - }; - - factory: partition@40000 { - reg = <0x00040000 0x00010000>; - label = "factory"; - read-only; - }; - - partition@50000 { - reg = <0x00050000 0x007b0000>; - label = "firmware"; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <100>; - - reset { - label = "reset"; - gpios = <&gpio0 10 1>; - linux,code = <0x198>; - }; - - wps { - label = "wps"; - gpios = <&gpio1 2 1>; - linux,code = <0x211>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - wps { - label = "tew-692gr:orange:wps"; - gpios = <&gpio0 9 1>; - }; - - wps2 { - label = "tew-692gr:green:wps"; - gpios = <&gpio1 4 1>; - }; - }; -}; - -&gpio1 { - status = "okay"; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "spi", "i2c", "jtag", "uartf"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - status = "okay"; - mtd-mac-address = <&factory 0x28>; - - port@0 { - phy-handle = <&phy0>; - phy-mode = "rgmii"; - }; - - mdio-bus { - status = "okay"; - - phy0: ethernet-phy@0 { - reg = <0>; - }; - }; -}; - -&pci { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pci_pins>; - - pci_pins: pci { - pci { - ralink,group = "pci"; - ralink,function = "pci-fnc"; - }; - }; - - host-bridge { - pci-bridge@1 { - status = "okay"; - }; - }; -}; - -&wmac { - ralink,5ghz = <0>; -}; diff --git a/sys/gnu/dts/mips/TINY-AC.dts b/sys/gnu/dts/mips/TINY-AC.dts deleted file mode 100644 index 6a212477678..00000000000 --- a/sys/gnu/dts/mips/TINY-AC.dts +++ /dev/null @@ -1,163 +0,0 @@ -/dts-v1/; - -#include "mt7620a.dtsi" - -/ { - compatible = "TINY-AC", "ralink,mt7620a-soc"; - model = "Dovado Tiny AC"; - - chosen { - bootargs = "console=ttyS0,57600"; - }; - - gpio-leds { - compatible = "gpio-leds"; - - usb { - label = "tiny-ac:green:usb"; - gpios = <&gpio0 11 1>; - }; - - wifi { - label = "tiny-ac:orange:wifi"; - gpios = <&gpio3 0 1>; - }; - - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio0 13 1>; - linux,code = <0x198>; - }; - - }; - - gpio_export { - compatible = "gpio-export"; - #size-cells = <0>; - - usbpower { - gpio-export,name = "usbpower"; - gpio-export,output = <1>; - gpios = <&gpio2 5 0>; - }; - }; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio2 { - status = "okay"; -}; - -&gpio3 { - status = "okay"; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80", "mx25l6405d"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x7b0000>; - }; - }; -}; - -&ehci { - status = "okay"; -}; - -&ohci { - status = "okay"; -}; - -ðernet { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>; - mediatek,portmap = "llllw"; - - port@4 { - status = "okay"; - phy-mode = "rgmii"; - phy-handle = <&phy4>; - }; - - port@5 { - status = "okay"; - phy-mode = "rgmii"; - phy-handle = <&phy5>; - }; - - mdio-bus { - status = "okay"; - - phy4: ethernet-phy@4 { - reg = <4>; - phy-mode = "rgmii"; - }; - - phy5: ethernet-phy@5 { - reg = <5>; - phy-mode = "rgmii"; - }; - }; -}; - -&gsw { - mediatek,port4 = "gmac"; - mediatek,mt7530 = <1>; -}; - -&wmac { - ralink,eeprom = "rt2x00pci_1_0.eeprom"; -}; - -&pcie { - status = "okay"; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "uartf", "nd_sd", "wled"; - ralink,function = "gpio"; - }; - }; -}; diff --git a/sys/gnu/dts/mips/UBNT-ERX.dts b/sys/gnu/dts/mips/UBNT-ERX.dts deleted file mode 100644 index 713519d5d9e..00000000000 --- a/sys/gnu/dts/mips/UBNT-ERX.dts +++ /dev/null @@ -1,112 +0,0 @@ -#include - -/dts-v1/; - -#include "mt7621.dtsi" - -/ { - compatible = "mediatek,mt7621-eval-board", "mediatek,mt7621-soc"; - model = "UBNT-ERX"; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x10000000>; - }; - - chosen { - bootargs = "console=ttyS0,57600"; - }; - - nand@1e003000 { - status = "okay"; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x80000>; - read-only; - }; - - partition@80000 { - label = "u-boot-env"; - reg = <0x80000 0x60000>; - read-only; - }; - - factory: partition@e0000 { - label = "factory"; - reg = <0xe0000 0x60000>; - }; - - partition@140000 { - label = "kernel1"; - reg = <0x140000 0x300000>; - }; - - partition@440000 { - label = "kernel2"; - reg = <0x440000 0x300000>; - }; - - partition@740000 { - label = "ubi"; - reg = <0x740000 0xf7c0000>; - }; - - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio0 12 1>; - linux,code = ; - }; - }; -}; - -ðernet { - mtd-mac-address = <&factory 0x22>; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "uart2", "uart3", "i2c", "pcie", "rgmii2", "jtag"; - ralink,function = "gpio"; - }; - }; -}; - -&sdhci { - status = "disabled"; -}; - -&pcie { - status = "disabled"; -}; - -&spi0 { - /* This board has 2Mb spi flash soldered in and visible - from manufacturer's firmware. - But this SoC shares spi and nand pins, - and current driver does't handle this sharing well */ - status = "disabled"; - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <1>; - linux,modalias = "m25p80"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "spi"; - reg = <0x0 0x200000>; - read-only; - }; - }; -}; diff --git a/sys/gnu/dts/mips/UR-326N4G.dts b/sys/gnu/dts/mips/UR-326N4G.dts deleted file mode 100644 index d90d77c0611..00000000000 --- a/sys/gnu/dts/mips/UR-326N4G.dts +++ /dev/null @@ -1,113 +0,0 @@ -/dts-v1/; - -#include "rt3050.dtsi" - -/ { - compatible = "UR-326N4G", "ralink,rt3052-soc"; - model = "UPVEL UR-326N4G"; - - cfi@1f000000 { - compatible = "cfi-flash"; - reg = <0x1f000000 0x800000>; - bank-width = <2>; - device-width = <2>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x3b0000>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - 3g { - label = "ur-326n4g:green:3g"; - gpios = <&gpio0 9 1>; - }; - - gateway { - label = "ur-326n4g:green:gateway"; - gpios = <&gpio0 11 1>; - }; - - ap { - label = "ur-326n4g:green:ap"; - gpios = <&gpio0 12 1>; - }; - - wps { - label = "ur-326n4g:green:wps"; - gpios = <&gpio0 14 1>; - }; - - station { - label = "ur-326n4g:green:station"; - gpios = <&gpio0 13 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset_wps { - label = "reset_wps"; - gpios = <&gpio0 10 1>; - linux,code = <0x198>; - }; - - mode { - label = "mode"; - gpios = <&gpio0 7 1>; - linux,code = <0x32>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - mtd-mac-address = <&factory 0x4004>; -}; - -&esw { - mediatek,portmap = <0x2f>; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; - -&otg { - status = "okay"; -}; diff --git a/sys/gnu/dts/mips/UR-336UN.dts b/sys/gnu/dts/mips/UR-336UN.dts deleted file mode 100644 index e0325a7c567..00000000000 --- a/sys/gnu/dts/mips/UR-336UN.dts +++ /dev/null @@ -1,92 +0,0 @@ -/dts-v1/; - -#include "rt3050.dtsi" - -/ { - compatible = "UR-336UN", "ralink,rt3052-soc"; - model = "UPVEL UR-336UN"; - - cfi@1f000000 { - compatible = "cfi-flash"; - reg = <0x1f000000 0x800000>; - bank-width = <2>; - device-width = <2>; - #address-cells = <1>; - #size-cells = <1>; - }; - - gpio-leds { - compatible = "gpio-leds"; - - 3g { - label = "ur-336un:green:3g"; - gpios = <&gpio0 9 1>; - }; - - gateway { - label = "ur-336un:green:gateway"; - gpios = <&gpio0 11 1>; - }; - - ap { - label = "ur-336un:green:ap"; - gpios = <&gpio0 12 1>; - }; - - wps { - label = "ur-336un:green:wps"; - gpios = <&gpio0 14 1>; - }; - - station { - label = "ur-336un:green:station"; - gpios = <&gpio0 13 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset_wps { - label = "reset_wps"; - gpios = <&gpio0 10 1>; - linux,code = <0x198>; - }; - - mode { - label = "mode"; - gpios = <&gpio0 7 1>; - linux,code = <0x32>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; -}; - -/* FIXME: no partitions defined */ -/*ðernet { - mtd-mac-address = <&factory 0x4004>; -}; -*/ -&esw { - mediatek,portmap = <0x2f>; -}; - -/* FIXME: no partitions defined */ -/*&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; -*/ -&otg { - status = "okay"; -}; diff --git a/sys/gnu/dts/mips/V11STFE.dts b/sys/gnu/dts/mips/V11STFE.dts deleted file mode 100644 index 6f7a5cbdfd6..00000000000 --- a/sys/gnu/dts/mips/V11STFE.dts +++ /dev/null @@ -1,83 +0,0 @@ -/dts-v1/; - -#include "rt2880.dtsi" - -/ { - compatible = "V11ST-FE", "ralink,rt2880-soc"; - model = "Ralink V11ST-FE"; - - pci@440000 { - status = "okay"; - - host-bridge { - pci-bridge@1 { - status = "okay"; - }; - }; - }; - - nor-flash@1c000000 { - compatible = "cfi-flash"; - reg = <0x1c000000 0x800000>; - bank-width = <2>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - reg = <0x0 0x0030000>; - label = "u-boot"; - read-only; - }; - - partition@30000 { - reg = <0x00030000 0x00010000>; - label = "u-boot-env"; - read-only; - }; - - factory: partition@40000 { - reg = <0x00040000 0x00010000>; - label = "factory"; - read-only; - }; - - partition@50000 { - reg = <0x00050000 0x003b0000>; - label = "firmware"; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <100>; - - wps { - label = "wps"; - gpios = <&gpio0 0 0>; - linux,code = <0x211>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - status { - label = "v11st-fe:green:status"; - gpios = <&gpio0 12 1>; - }; - }; -}; - -&gpio0 { - status = "okay"; -}; - -ðernet { - status = "okay"; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; diff --git a/sys/gnu/dts/mips/V22RW-2X2.dts b/sys/gnu/dts/mips/V22RW-2X2.dts deleted file mode 100644 index 602e170e607..00000000000 --- a/sys/gnu/dts/mips/V22RW-2X2.dts +++ /dev/null @@ -1,94 +0,0 @@ -/dts-v1/; - -#include "rt3050.dtsi" - -/ { - compatible = "V22RW-2X2", "ralink,rt3052-soc"; - model = "Ralink AP-RT3052-V22RW-2X2"; - - cfi@1f000000 { - compatible = "cfi-flash"; - reg = <0x1f000000 0x800000>; - bank-width = <2>; - device-width = <2>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x3b0000>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - security { - label = "v22rw-2x2:green:security"; - gpios = <&gpio0 13 1>; - }; - - wps { - label = "v22rw-2x2:red:wps"; - gpios = <&gpio0 14 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio0 10 1>; - linux,code = <0x198>; - }; - - wps { - label = "wps"; - gpios = <&gpio0 0 1>; - linux,code = <0x211>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; -}; - -&esw { - mediatek,portmap = <0x2f>; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; - -&otg { - status = "okay"; -}; diff --git a/sys/gnu/dts/mips/VOCORE-16M.dts b/sys/gnu/dts/mips/VOCORE-16M.dts deleted file mode 100644 index f51c4f5407e..00000000000 --- a/sys/gnu/dts/mips/VOCORE-16M.dts +++ /dev/null @@ -1,39 +0,0 @@ -/dts-v1/; - -#include "VOCORE.dtsi" - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80", "w25q128"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "uboot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "uboot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0xfb0000>; - }; - }; -}; diff --git a/sys/gnu/dts/mips/VOCORE-8M.dts b/sys/gnu/dts/mips/VOCORE-8M.dts deleted file mode 100644 index 1026c865c55..00000000000 --- a/sys/gnu/dts/mips/VOCORE-8M.dts +++ /dev/null @@ -1,39 +0,0 @@ -/dts-v1/; - -#include "VOCORE.dtsi" - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80", "s25fl064k"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "uboot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "uboot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x7b0000>; - }; - }; -}; diff --git a/sys/gnu/dts/mips/VOCORE.dtsi b/sys/gnu/dts/mips/VOCORE.dtsi deleted file mode 100644 index bb8a458831f..00000000000 --- a/sys/gnu/dts/mips/VOCORE.dtsi +++ /dev/null @@ -1,196 +0,0 @@ -#include "rt5350.dtsi" - -/ { - compatible = "VoCore", "ralink,rt5350-soc"; - model = "VoCore"; - - gpio-export { - compatible = "gpio-export"; - #size-cells = <0>; - - gpio0 { - gpio-export,name = "gpio0"; - gpio-export,direction_may_change = <1>; - gpios = <&gpio0 0 0>; - }; - - /* UARTF */ - gpio7 { - /* UARTF_RTS_N */ - gpio-export,name = "gpio7"; - gpio-export,direction_may_change = <1>; - gpios = <&gpio0 7 0>; - }; - - gpio8 { - /* UARTF_TXD */ - gpio-export,name = "gpio8"; - gpio-export,direction_may_change = <1>; - gpios = <&gpio0 8 0>; - }; - - gpio9 { - /* UARTF_CTS_N */ - gpio-export,name = "gpio9"; - gpio-export,direction_may_change = <1>; - gpios = <&gpio0 9 0>; - }; - - gpio12 { - /* UARTF_DCD_N */ - gpio-export,name = "gpio12"; - gpio-export,direction_may_change = <1>; - gpios = <&gpio0 12 0>; - }; - - gpio13 { - /* UARTF_DSR_N */ - gpio-export,name = "gpio13"; - gpio-export,direction_may_change = <1>; - gpios = <&gpio0 13 0>; - }; - - gpio14 { - /* UARTF_RIN */ - gpio-export,name = "gpio14"; - gpio-export,direction_may_change = <1>; - gpios = <&gpio0 14 0>; - }; - - /* JTAG */ - gpio17 { - /* JTAG_TDO */ - gpio-export,name = "gpio17"; - gpio-export,direction_may_change = <1>; - gpios = <&gpio0 17 0>; - }; - - gpio18 { - /* JTAG_TDI */ - gpio-export,name = "gpio18"; - gpio-export,direction_may_change = <1>; - gpios = <&gpio0 18 0>; - }; - - gpio19 { - /* JTAG_TMS */ - gpio-export,name = "gpio19"; - gpio-export,direction_may_change = <1>; - gpios = <&gpio0 19 0>; - }; - - gpio20 { - /* JTAG_TCLK */ - gpio-export,name = "gpio20"; - gpio-export,direction_may_change = <1>; - gpios = <&gpio0 20 0>; - }; - - gpio21 { - /* JTAG_TRST_N */ - gpio-export,name = "gpio21"; - gpio-export,direction_may_change = <1>; - gpios = <&gpio0 21 0>; - }; - - /* ETH LEDs */ - gpio22 { - /* ETH0_LED */ - gpio-export,name = "gpio22"; - gpio-export,direction_may_change = <1>; - gpios = <&gpio1 0 0>; - }; - - gpio23 { - /* ETH1_LED */ - gpio-export,name = "gpio23"; - gpio-export,direction_may_change = <1>; - gpios = <&gpio1 1 0>; - }; - - gpio24 { - /* ETH2_LED */ - gpio-export,name = "gpio24"; - gpio-export,direction_may_change = <1>; - gpios = <&gpio1 2 0>; - }; - - gpio25 { - /* ETH3_LED */ - gpio-export,name = "gpio25"; - gpio-export,direction_may_change = <1>; - gpios = <&gpio1 3 0>; - }; - - gpio26 { - /* ETH4_LED */ - gpio-export,name = "gpio26"; - gpio-export,direction_may_change = <1>; - gpios = <&gpio1 4 0>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - status { - /* UARTF_RXD */ - label = "vocore:green:status"; - gpios = <&gpio0 10 0>; - }; - - eth { - /* UARTF_DTR_N */ - label = "vocore:orange:eth"; - gpios = <&gpio0 11 0>; - }; - }; -}; - -&gpio1 { - status = "okay"; -}; - -&i2c { - status = "okay"; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "jtag", "uartf", "led"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - mtd-mac-address = <&factory 0x4>; -}; - -&esw { - mediatek,portmap = <0x11>; - mediatek,portdisable = <0x2e>; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; - -&ehci { - status = "okay"; -}; - -&ohci { - status = "okay"; -}; - -&spi1 { - status = "okay"; - - spidev@0 { - compatible = "linux,spidev"; - spi-max-frequency = <10000000>; - reg = <0>; - }; -}; diff --git a/sys/gnu/dts/mips/W150M.dts b/sys/gnu/dts/mips/W150M.dts deleted file mode 100644 index 679db60af4a..00000000000 --- a/sys/gnu/dts/mips/W150M.dts +++ /dev/null @@ -1,114 +0,0 @@ -/dts-v1/; - -#include "rt3050.dtsi" - -/ { - compatible = "W150M", "ralink,rt3050-soc"; - model = "Tenda W150M"; - - cfi@1f000000 { - compatible = "cfi-flash"; - reg = <0x1f000000 0x800000>; - bank-width = <2>; - device-width = <2>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x3c8000>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - 3grouter { - label = "w150m:blue:3grouter"; - gpios = <&gpio0 11 1>; - }; - - ap { - label = "w150m:blue:ap"; - gpios = <&gpio0 12 1>; - }; - - wisprouter { - label = "w150m:blue:wisprouter"; - gpios = <&gpio0 9 1>; - }; - - wirelessrouter { - label = "w150m:blue:wirelessrouter"; - gpios = <&gpio0 13 1>; - }; - - 3g { - label = "w150m:blue:3g"; - gpios = <&gpio0 7 1>; - }; - - wpsreset { - label = "w150m:blue:wpsreset"; - gpios = <&gpio0 14 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio0 0 1>; - linux,code = <0x198>; - }; - - mode { - label = "mode"; - gpios = <&gpio0 10 1>; - linux,code = <0x100>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - mtd-mac-address = <&factory 0x4>; -}; - -&esw { - mediatek,portmap = <0x2f>; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; diff --git a/sys/gnu/dts/mips/W306R_V20.dts b/sys/gnu/dts/mips/W306R_V20.dts deleted file mode 100644 index 79ae23dd632..00000000000 --- a/sys/gnu/dts/mips/W306R_V20.dts +++ /dev/null @@ -1,88 +0,0 @@ -/dts-v1/; - -#include "rt3050.dtsi" - -/ { - compatible = "W306R_V20", "ralink,rt3052-soc"; - model = "Tenda W306R V2.0"; - - cfi@1f000000 { - compatible = "cfi-flash"; - reg = <0x1f000000 0x800000>; - bank-width = <2>; - device-width = <2>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x3b0000>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - sys { - label = "w306r-v20:green:sys"; - gpios = <&gpio0 9 1>; - }; - - wps { - label = "w306r-v20:green:wps"; - gpios = <&gpio0 13 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset { - label = "RESET/WPS"; - gpios = <&gpio0 10 1>; - linux,code = <0x198>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - mtd-mac-address = <&factory 0x28>; -}; - -&esw { - mediatek,portmap = <0x3e>; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; diff --git a/sys/gnu/dts/mips/W502U.dts b/sys/gnu/dts/mips/W502U.dts deleted file mode 100644 index 739817022b4..00000000000 --- a/sys/gnu/dts/mips/W502U.dts +++ /dev/null @@ -1,102 +0,0 @@ -/dts-v1/; - -#include "rt3050.dtsi" - -/ { - compatible = "W502U", "ralink,rt3052-soc"; - model = "ALFA Networks W502U"; - - chosen { - bootargs = "console=ttyS0,115200"; - }; - - cfi@1f000000 { - compatible = "cfi-flash"; - reg = <0x1f000000 0x800000>; - bank-width = <2>; - device-width = <2>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x7b0000>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - usb { - label = "w502u:blue:usb"; - gpios = <&gpio0 13 1>; - }; - - wps { - label = "w502u:blue:wps"; - gpios = <&gpio0 14 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio0 10 1>; - linux,code = <0x198>; - }; - - wps { - label = "wps"; - gpios = <&gpio0 0 1>; - linux,code = <0x211>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - mtd-mac-address = <&factory 0x28>; -}; - -&esw { - mediatek,portmap = <0x3e>; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; - -&otg { - status = "okay"; -}; diff --git a/sys/gnu/dts/mips/WCR150GN.dts b/sys/gnu/dts/mips/WCR150GN.dts deleted file mode 100644 index 541836b2185..00000000000 --- a/sys/gnu/dts/mips/WCR150GN.dts +++ /dev/null @@ -1,98 +0,0 @@ -/dts-v1/; - -#include "rt3050.dtsi" - -/ { - compatible = "WCR150GN", "ralink,rt3050-soc"; - model = "Sparklan WCR-150GN"; - - cfi@1f000000 { - compatible = "cfi-flash"; - reg = <0x1f000000 0x800000>; - bank-width = <2>; - device-width = <2>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x3b0000>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - user { - label = "wcr-150gn:amber:user"; - gpios = <&gpio0 12 1>; - }; - - power { - label = "wcr-150gn:amber:power"; - gpios = <&gpio0 8 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - wps { - label = "wps"; - gpios = <&gpio0 10 1>; - linux,code = <0x211>; - }; - - reset { - label = "reset"; - gpios = <&gpio0 0 1>; - linux,code = <0x198>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - mtd-mac-address = <&factory 0x4>; -}; - -&esw { - mediatek,portmap = <0x2f>; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; - -&otg { - status = "okay"; -}; diff --git a/sys/gnu/dts/mips/WF-2881.dts b/sys/gnu/dts/mips/WF-2881.dts deleted file mode 100644 index 050bc2e7ccb..00000000000 --- a/sys/gnu/dts/mips/WF-2881.dts +++ /dev/null @@ -1,116 +0,0 @@ -/dts-v1/; - -#include "mt7621.dtsi" - -/ { - compatible = "mediatek,mt7621-eval-board", "mediatek,mt7621-soc"; - model = "NETIS WF-2881"; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x8000000>; - }; - - chosen { - bootargs = "console=ttyS0,57600"; - }; - - nand@1e003000 { - status = "okay"; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x1000>; - read-only; - }; - - partition@80000 { - label = "config"; - reg = <0x80000 0x80000>; - read-only; - }; - - factory: partition@100000 { - label = "factory"; - reg = <0x100000 0x40000>; - read-only; - }; - - partition@140000 { - label = "firmware"; - reg = <0x140000 0x7E40000>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - usb { - label = "wf-2881:green:usb"; - gpios = <&gpio0 6 1>; - }; - - wps { - label = "wf-2881:green:wps"; - gpios = <&gpio0 0 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio0 12 1>; - linux,code = <0x198>; - }; - }; -}; - -&spi0 { - status="disabled"; -}; - -&pcie { - status = "okay"; - - pcie0 { - mt76@0,0 { - reg = <0x0000 0 0 0 0>; - device_type = "pci"; - mediatek,mtd-eeprom = <&factory 0x8000>; - mediatek,2ghz = <0>; - }; - }; - - pcie1 { - mt76@1,0 { - reg = <0x0000 0 0 0 0>; - device_type = "pci"; - mediatek,mtd-eeprom = <&factory 0x0000>; - mediatek,5ghz = <0>; - }; - }; -}; - -ðernet { - mtd-mac-address = <&factory 0xe006>; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "uart3", "jtag"; - ralink,function = "gpio"; - }; - }; -}; diff --git a/sys/gnu/dts/mips/WHR-1166D.dts b/sys/gnu/dts/mips/WHR-1166D.dts deleted file mode 100644 index 0c0f62728c7..00000000000 --- a/sys/gnu/dts/mips/WHR-1166D.dts +++ /dev/null @@ -1,170 +0,0 @@ -/dts-v1/; - -#include "mt7620a.dtsi" - -/ { - compatible = "ralink,mt7620a-soc"; - model = "Buffalo WHR-1166D"; - - gpio-leds { - compatible = "gpio-leds"; - - power { - label = "whr-1166d:red:power"; - gpios = <&gpio0 7 1>; - }; - - wifi { - label = "whr-1166d:green:wifi"; - gpios = <&gpio0 8 1>; - }; - - power2 { - label = "whr-1166d:green:power"; - gpios = <&gpio0 9 1>; - }; - - wifi2 { - label = "whr-1166d:orange:wifi"; - gpios = <&gpio0 10 1>; - }; - - internet { - label = "whr-1166d:green:internet"; - gpios = <&gpio2 17 1>; - }; - - router { - label = "whr-1166d:orange:router"; - gpios = <&gpio2 18 1>; - }; - - router2 { - label = "whr-1166d:green:router"; - gpios = <&gpio2 19 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio2 12 1>; - linux,code = <0x198>; - }; - - aoss { - label = "aoss"; - gpios = <&gpio2 13 1>; - linux,code = <0x211>; - }; - - ap { - label = "ap"; - gpios = <&gpio2 14 1>; - linux,code = <0x100>; - linux,input-type = <5>; /* EV_SW */ - }; - - bridge { - label = "bridge"; - gpios = <&gpio2 15 1>; - linux,code = <0x100>; - linux,input-type = <5>; /* EV_SW */ - }; - }; -}; - -&gpio2 { - status = "okay"; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80", "mx25l6405d"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0xfb0000>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "uartf", "wled", "nd_sd"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - pinctrl-names = "default"; - pinctrl-0 = <&rgmii1_pins &mdio_pins>; - - port@5 { - status = "okay"; - phy-handle = <&phy5>; - phy-mode = "rgmii"; - }; - - mdio-bus { - status = "okay"; - - phy5: ethernet-phy@5 { - reg = <5>; - phy-mode = "rgmii"; - }; - }; -}; - -&gsw { - mediatek,port4 = "ephy"; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; - -&pcie { - status = "okay"; - - pcie-bridge { - mt76@0,0 { - reg = <0x0000 0 0 0 0>; - device_type = "pci"; - mediatek,mtd-eeprom = <&factory 32768>; - mediatek,2ghz = <0>; - }; - }; -}; diff --git a/sys/gnu/dts/mips/WHR-300HP2.dts b/sys/gnu/dts/mips/WHR-300HP2.dts deleted file mode 100644 index acd4ce47e54..00000000000 --- a/sys/gnu/dts/mips/WHR-300HP2.dts +++ /dev/null @@ -1,148 +0,0 @@ -/dts-v1/; - -#include "mt7620a.dtsi" - -/ { - compatible = "ralink,mt7620a-soc"; - model = "Buffalo WHR-300HP2"; - - gpio-leds { - compatible = "gpio-leds"; - - power { - label = "whr-300hp2:red:power"; - gpios = <&gpio0 7 1>; - }; - - wifi { - label = "whr-300hp2:green:wifi"; - gpios = <&gpio0 8 1>; - }; - - power2 { - label = "whr-300hp2:green:power"; - gpios = <&gpio0 9 1>; - }; - - wifi2 { - label = "whr-300hp2:orange:wifi"; - gpios = <&gpio0 10 1>; - }; - - internet { - label = "whr-300hp2:green:internet"; - gpios = <&gpio2 17 1>; - }; - - router { - label = "whr-300hp2:green:router"; - gpios = <&gpio2 18 1>; - }; - - router2 { - label = "whr-300hp2:orange:router"; - gpios = <&gpio2 19 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio2 12 1>; - linux,code = <0x198>; - }; - - aoss { - label = "aoss"; - gpios = <&gpio2 13 1>; - linux,code = <0x211>; - }; - - ap { - label = "ap"; - gpios = <&gpio2 14 1>; - linux,code = <0x100>; - linux,input-type = <5>; /* EV_SW */ - }; - - bridge { - label = "bridge"; - gpios = <&gpio2 15 1>; - linux,code = <0x100>; - linux,input-type = <5>; /* EV_SW */ - }; - }; -}; - -&gpio2 { - status = "okay"; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80", "s25fl064k"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x7b0000>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "uartf", "rgmii1", "rgmii2", "wled", "nd_sd"; - ralink,function = "gpio"; - }; - - pa { - ralink,group = "pa"; - ralink,function = "pa"; - }; - }; -}; - -ðernet { - pinctrl-names = "default"; - pinctrl-0 = <&ephy_pins>; - mediatek,portmap = "llllw"; -}; - -&gsw { - mediatek,port4 = "ephy"; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; diff --git a/sys/gnu/dts/mips/WHR-600D.dts b/sys/gnu/dts/mips/WHR-600D.dts deleted file mode 100644 index 7d26f32b973..00000000000 --- a/sys/gnu/dts/mips/WHR-600D.dts +++ /dev/null @@ -1,148 +0,0 @@ -/dts-v1/; - -#include "mt7620a.dtsi" - -/ { - compatible = "ralink,mt7620a-soc"; - model = "Buffalo WHR-600D"; - - gpio-leds { - compatible = "gpio-leds"; - - power { - label = "whr-600d:red:power"; - gpios = <&gpio0 7 1>; - }; - - wifi { - label = "whr-600d:green:wifi"; - gpios = <&gpio0 8 1>; - }; - - power2 { - label = "whr-600d:green:power"; - gpios = <&gpio0 9 1>; - }; - - wifi2 { - label = "whr-600d:orange:wifi"; - gpios = <&gpio0 10 1>; - }; - - internet { - label = "whr-600d:green:internet"; - gpios = <&gpio2 17 1>; - }; - - router { - label = "whr-600d:green:router"; - gpios = <&gpio2 18 1>; - }; - - router2 { - label = "whr-600d:orange:router"; - gpios = <&gpio2 19 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio2 12 1>; - linux,code = <0x198>; - }; - - aoss { - label = "aoss"; - gpios = <&gpio2 13 1>; - linux,code = <0x211>; - }; - - ap { - label = "ap"; - gpios = <&gpio2 14 1>; - linux,code = <0x100>; - linux,input-type = <5>; /* EV_SW */ - }; - - bridge { - label = "bridge"; - gpios = <&gpio2 15 1>; - linux,code = <0x100>; - linux,input-type = <5>; /* EV_SW */ - }; - }; -}; - -&gpio2 { - status = "okay"; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80", "mx25l6405d"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x7b0000>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "uartf", "rgmii1", "rgmii2", "wled", "nd_sd"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - pinctrl-names = "default"; - pinctrl-0 = <&ephy_pins>; - mtd-mac-address = <&factory 0x4>; - mediatek,portmap = "llllw"; -}; - -&gsw { - mediatek,port4 = "ephy"; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; - -&pcie { - status = "okay"; -}; diff --git a/sys/gnu/dts/mips/WHR-G300N.dts b/sys/gnu/dts/mips/WHR-G300N.dts deleted file mode 100644 index 4f80f2db1a3..00000000000 --- a/sys/gnu/dts/mips/WHR-G300N.dts +++ /dev/null @@ -1,86 +0,0 @@ -/dts-v1/; - -#include "rt3050.dtsi" - -/ { - compatible = "WHR-G300N", "ralink,rt3052-soc"; - model = "Buffalo WHR-G300N"; - - cfi@1f000000 { - compatible = "cfi-flash"; - reg = <0x1f000000 0x800000>; - bank-width = <2>; - device-width = <2>; - #address-cells = <1>; - #size-cells = <1>; - }; - - gpio-leds { - compatible = "gpio-leds"; - - diag { - label = "whr-g300n:red:diag"; - gpios = <&gpio0 7 1>; - }; - - router { - label = "whr-g300n:green:router"; - gpios = <&gpio0 9 1>; - }; - - security { - label = "whr-g300n:amber:security"; - gpios = <&gpio0 14 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio0 10 1>; - linux,code = <0x198>; - }; - - aoss { - label = "aoss"; - gpios = <&gpio0 0 1>; - linux,code = <0x211>; - }; - - router-off { - label = "router-off"; - gpios = <&gpio0 11 1>; - linux,code = <0x102>; - }; - - router-on { - label = "router-on"; - gpios = <&gpio0 8 1>; - linux,code = <0x103>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; -}; - -&esw { - mediatek,portmap = <0x2f>; -}; - -/* FIXME: no partitions defined */ -/*&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; -*/ diff --git a/sys/gnu/dts/mips/WITI.dts b/sys/gnu/dts/mips/WITI.dts deleted file mode 100644 index 8cb5916c59d..00000000000 --- a/sys/gnu/dts/mips/WITI.dts +++ /dev/null @@ -1,129 +0,0 @@ -/dts-v1/; - -#include "mt7621.dtsi" - -/ { - compatible = "mediatek,mt7621-eval-board", "mediatek,mt7621-soc"; - model = "MQmaker WiTi"; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x10000000>; - }; - - chosen { - bootargs = "console=ttyS0,57600"; - }; - - palmbus: palmbus@1E000000 { - i2c@900 { - compatible = "ralink,i2c-mt7621"; - reg = <0x900 0x100>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c_pins>; - status = "okay"; - - pcf8563: rtc@51 { - status = "okay"; - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio0 18 1>; - linux,code = <0x198>; - }; - }; -}; - - -&sdhci { - status = "okay"; -}; - -&xhci { - status = "okay"; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0xfb0000>; - }; - }; -}; - -&pcie { - status = "okay"; - - pcie0 { - mt76@0,0 { - reg = <0x0000 0 0 0 0>; - device_type = "pci"; - mediatek,mtd-eeprom = <&factory 0x8000>; - mediatek,2ghz = <0>; - mtd-mac-address = <&factory 0xe000>; - }; - }; - - pcie1 { - mt76@1,0 { - reg = <0x0000 0 0 0 0>; - device_type = "pci"; - mediatek,mtd-eeprom = <&factory 0x0000>; - mediatek,5ghz = <0>; - mtd-mac-address = <&factory 0xe000>; - }; - }; -}; - -ðernet { - mtd-mac-address = <&factory 0xe000>; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "wdt", "rgmii2", "jtag", "mdio"; - ralink,function = "gpio"; - }; - }; -}; diff --git a/sys/gnu/dts/mips/WIZARD8800.dts b/sys/gnu/dts/mips/WIZARD8800.dts deleted file mode 100644 index bbfa61085d2..00000000000 --- a/sys/gnu/dts/mips/WIZARD8800.dts +++ /dev/null @@ -1,81 +0,0 @@ -/dts-v1/; - -#include "rt5350.dtsi" - -/ { - compatible = "WIZARD8800", "ralink,rt5350-soc"; - model = "EASYACC WI-STOR WIZARD 8800"; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80", "w25q32"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x7b0000>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - mtd-mac-address = <&factory 0x4>; -}; - -&esw { - mediatek,portmap = <0x2f>; -}; - -&ehci { - status = "okay"; -}; - -&ohci { - status = "okay"; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; diff --git a/sys/gnu/dts/mips/WIZFI630A.dts b/sys/gnu/dts/mips/WIZFI630A.dts deleted file mode 100644 index 0f7ede54dfd..00000000000 --- a/sys/gnu/dts/mips/WIZFI630A.dts +++ /dev/null @@ -1,184 +0,0 @@ -/dts-v1/; - -#include "rt5350.dtsi" - -/ { - compatible = "wizfi630a", "ralink,rt5350-soc"; - model = "WIZnet WizFi630A"; - - chosen { - bootargs = "console=ttyS1,115200"; - }; - - gpio-export { - compatible = "gpio-export"; - #size-cells = <0>; - }; - - gpio-leds { - compatible = "gpio-leds"; - - run { - label = "wizfi630a::run"; - gpios = <&gpio0 1 1>; - }; - - wps { - label = "wizfi630a::wps"; - gpios = <&gpio0 20 1>; - }; - - uart1 { - label = "wizfi630a::uart1"; - gpios = <&gpio0 18 1>; - }; - - uart2 { - label = "wizfi630a::uart2"; - gpios = <&gpio0 21 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio0 17 1>; - linux,code = <0x198>; - }; - - wps { - label = "wps"; - gpios = <&gpio0 0 1>; - linux,code = <0x211>; - }; - - scm1 { - label = "SCM1"; - gpios = <&gpio0 19 1>; - linux,code = <0x100>; - }; - - scm2 { - label = "SCM2"; - gpios = <&gpio0 2 1>; - linux,code = <0x101>; - }; - }; -}; - -&gpio1 { - status = "okay"; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80", "w25q128"; - spi-max-frequency = <10000000>; - - partition@0 { - #size-cells = <1>; - label = "uboot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - #size-cells = <1>; - label = "uboot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - #size-cells = <1>; - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - #size-cells = <1>; - label = "firmware"; - reg = <0x50000 0xfb0000>; - }; - }; -}; - -&uart { - compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a"; - reg = <0x500 0x100>; - resets = <&rstctrl 12>; - reset-names = "uart"; - interrupt-parent = <&intc>; - interrupts = <5>; - reg-shift = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&uartf_pins>; - status = "okay"; -}; - -&uartlite { - compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a"; - reg = <0xc00 0x100>; - resets = <&rstctrl 19>; - reset-names = "uartl"; - interrupt-parent = <&intc>; - interrupts = <12>; - reg-shift = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&uartlite_pins>; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "jtag" ; - ralink,function = "gpio"; - }; - }; - - uartf_gpio_pins: uartf_gpio { - uartf_gpio { - ralink,group = "uartf"; - ralink,function = "uartf"; - }; - }; - - uartlite_pins: uartlite { - uart { - ralink,group = "uartlite"; - ralink,function = "uartlite"; - }; - }; -}; - -ðernet { - mtd-mac-address = <&factory 0x4>; -}; - -&esw { - mediatek,portmap = <0x17>; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; - -&ehci { - status = "okay"; -}; - -&ohci { - status = "okay"; -}; diff --git a/sys/gnu/dts/mips/WL-330N.dts b/sys/gnu/dts/mips/WL-330N.dts deleted file mode 100644 index d3cd74b2ab3..00000000000 --- a/sys/gnu/dts/mips/WL-330N.dts +++ /dev/null @@ -1,98 +0,0 @@ -/dts-v1/; - -#include "rt3050.dtsi" - -/ { - compatible = "WL-330N", "ralink,rt3050-soc"; - model = "Asus WL-330N"; - - gpio-leds { - compatible = "gpio-leds"; - - link { - label = "wl-330n:blue:link"; - gpios = <&gpio0 9 1>; - }; - - power { - label = "wl-330n:blue:power"; - gpios = <&gpio0 11 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio0 10 1>; - linux,code = <0x198>; - }; - - wps { - label = "wps"; - gpios = <&gpio0 0 1>; - linux,code = <0x198>; - }; - }; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80", "mx25l3205d"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x3b0000>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - mtd-mac-address = <&factory 0x4>; -}; - -&esw { - mediatek,portmap = <0x3e>; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; diff --git a/sys/gnu/dts/mips/WL-330N3G.dts b/sys/gnu/dts/mips/WL-330N3G.dts deleted file mode 100644 index 9290673419d..00000000000 --- a/sys/gnu/dts/mips/WL-330N3G.dts +++ /dev/null @@ -1,107 +0,0 @@ -/dts-v1/; - -#include "rt3050.dtsi" - -/ { - compatible = "WL-330N3G", "ralink,rt3050-soc"; - model = "Asus WL-330N3G"; - - gpio-leds { - compatible = "gpio-leds"; - - 3g { - label = "wl-330n3g:blue:3g"; - gpios = <&gpio0 9 1>; - }; - - 3g2 { - label = "wl-330n3g:red:3g"; - gpios = <&gpio0 13 1>; - }; - - power { - label = "wl-330n3g:blue:power"; - gpios = <&gpio0 11 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio0 10 1>; - linux,code = <0x198>; - }; - - wps { - label = "wps"; - gpios = <&gpio0 0 1>; - linux,code = <0x198>; - }; - }; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80", "mx25l3205d"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x3b0000>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - mtd-mac-address = <&factory 0x4>; -}; - -&esw { - mediatek,portmap = <0x3e>; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; - -&otg { - status = "okay"; -}; diff --git a/sys/gnu/dts/mips/WL-341V3.dts b/sys/gnu/dts/mips/WL-341V3.dts deleted file mode 100644 index 5f9e1dd9246..00000000000 --- a/sys/gnu/dts/mips/WL-341V3.dts +++ /dev/null @@ -1,123 +0,0 @@ -/dts-v1/; - -#include "rt3050.dtsi" - -/ { - compatible = "WL-341V3", "ralink,rt3052-soc"; - model = "Sitecom WL-341 v3"; - - cfi@1f000000 { - compatible = "cfi-flash"; - reg = <0x1f000000 0x800000>; - bank-width = <2>; - device-width = <2>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x20000>; - read-only; - }; - - boardnvram: partition@20000 { - label = "board-nvram"; - reg = <0x20000 0x10000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - partition@40000 { - label = "firmware"; - reg = <0x40000 0x3b0000>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - first { - label = "wl-341v3:amber:first"; - gpios = <&gpio0 9 1>; - }; - - first2 { - label = "wl-341v3:blue:first"; - gpios = <&gpio0 13 1>; - }; - - third { - label = "wl-341v3:amber:third"; - gpios = <&gpio0 11 1>; - }; - - third2 { - label = "wl-341v3:blue:third"; - gpios = <&gpio0 14 1>; - }; - - fourth { - label = "wl-341v3:blue:fourth"; - gpios = <&gpio0 10 1>; - }; - - fifth { - label = "wl-341v3:amber:fifth"; - gpios = <&gpio0 12 1>; - }; - - fifth2 { - label = "wl-341v3:blue:fifth"; - gpios = <&gpio0 8 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio0 7 1>; - linux,code = <0x198>; - }; - - wps { - label = "wps"; - gpios = <&gpio0 5 1>; - linux,code = <0x211>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - mtd-mac-address = <&boardnvram 0xffa0>; -}; - -&esw { - mediatek,portmap = <0x3e>; -}; - -&wmac { - ralink,mtd-eeprom = <&boardnvram 0xfd70>; -}; - -&otg { - status = "okay"; -}; diff --git a/sys/gnu/dts/mips/WL-351.dts b/sys/gnu/dts/mips/WL-351.dts deleted file mode 100644 index ecda696732c..00000000000 --- a/sys/gnu/dts/mips/WL-351.dts +++ /dev/null @@ -1,117 +0,0 @@ -/dts-v1/; - -#include "rt3050.dtsi" - -/ { - compatible = "WL-351", "ralink,rt3052-soc"; - model = "Sitecom WL-351 v1 002"; - - cfi@1f000000 { - compatible = "cfi-flash"; - reg = <0x1f000000 0x800000>; - bank-width = <2>; - device-width = <2>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x3b0000>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - power { - label = "wl-351:amber:power"; - gpios = <&gpio0 8 1>; - }; - - unpopulated { - label = "wl-351:amber:unpopulated"; - gpios = <&gpio0 12 1>; - }; - - unpopulated2 { - label = "wl-351:blue:unpopulated"; - gpios = <&gpio0 13 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio0 10 1>; - linux,code = <0x198>; - }; - - wps { - label = "wps"; - gpios = <&gpio0 0 1>; - linux,code = <0x211>; - }; - }; - - rtl8366rb { - compatible = "rtl8366rb"; - gpio-sda = <&gpio0 1 0>; - gpio-sck = <&gpio0 2 0>; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - mtd-mac-address = <&factory 0x4>; -}; - -&esw { - mediatek,portmap = <0x3f>; - ralink,fct2 = <0x0002500c>; - /* - * ext phy base addr 31, rx/tx clock skew 0, - * turbo mii off, rgmi 3.3v off, port 5 polling off - * port5: enabled, gige, full-duplex, rx/tx-flow-control - * port6: enabled, gige, full-duplex, rx/tx-flow-control - */ - ralink,fpa2 = <0x1f003fff>; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; - -&otg { - status = "okay"; -}; diff --git a/sys/gnu/dts/mips/WLI-TX4-AG300N.dts b/sys/gnu/dts/mips/WLI-TX4-AG300N.dts deleted file mode 100644 index 70521a71edb..00000000000 --- a/sys/gnu/dts/mips/WLI-TX4-AG300N.dts +++ /dev/null @@ -1,103 +0,0 @@ -/dts-v1/; - -#include "rt2880.dtsi" - -/ { - #address-cells = <1>; - #size-cells = <1>; - compatible = "WLI-TX4-AG300N", "ralink,rt2880-soc"; - model = "Buffalo WLI-TX4-AG300N"; - - cfi@1f000000 { - compatible = "cfi-flash"; - reg = <0x1f000000 0x800000>; - bank-width = <2>; - device-width = <2>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "uboot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "uboot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "linux"; - reg = <0x50000 0x3b0000>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <100>; - - wps { - label = "wps"; - gpios = <&gpio0 0 1>; - linux,code = <0x211>; - }; - - bandwidth { - label = "bandwidth"; - gpios = <&gpio0 8 0>; - linux,code = <0x198>; - }; - - reset { - label = "reset"; - gpios = <&gpio0 9 1>; - linux,code = <0x198>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - diag { - label = "wli-tx4-ag300n:red:diag"; - gpios = <&gpio0 10 1>; - }; - - power { - label = "wli-tx4-ag300n:blue:power"; - gpios = <&gpio0 12 1>; - }; - - security { - label = "wli-tx4-ag300n:blue:security"; - gpios = <&gpio0 13 1>; - }; - }; -}; - -&gpio0 { - status = "okay"; -}; - -ðernet { - status = "okay"; - mtd-mac-address = <&factory 0x4>; - - port@0 { - mediatek,fixed-link = <1000 1 1 1>; - }; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; diff --git a/sys/gnu/dts/mips/WMR-300.dts b/sys/gnu/dts/mips/WMR-300.dts deleted file mode 100644 index 02fbdc598a5..00000000000 --- a/sys/gnu/dts/mips/WMR-300.dts +++ /dev/null @@ -1,104 +0,0 @@ -/dts-v1/; - -#include "mt7620n.dtsi" - -/ { - compatible = "buffalo,wmr-300", "ralink,mt7620n-soc"; - model = "Buffalo WMR-300"; - - gpio-leds { - compatible = "gpio-leds"; - - aoss1 { - label = "wmr-300:red:aoss"; - gpios = <&gpio2 1 1>; - }; - - aoss2 { - label = "wmr-300:green:aoss"; - gpios = <&gpio2 2 1>; - }; - - power { - label = "wmr-300:green:status"; - gpios = <&gpio2 4 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio0 1 1>; - linux,code = <0x198>; - }; - - aoss { - label = "aoss"; - gpios = <&gpio0 2 1>; - linux,code = <0x211>; - }; - }; -}; - -&gpio2 { - status = "okay"; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80", "en25q64"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x7b0000>; - }; - }; -}; - -ðernet { - mtd-mac-address = <&factory 0x4>; - mediatek,portmap = "wllll"; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; - -&pinctrl { - state_default: pinctrl0 { - default { - ralink,group = "i2c", "ephy"; - ralink,function = "gpio"; - }; - }; -}; diff --git a/sys/gnu/dts/mips/WNCE2001.dts b/sys/gnu/dts/mips/WNCE2001.dts deleted file mode 100644 index 2dc39ce142a..00000000000 --- a/sys/gnu/dts/mips/WNCE2001.dts +++ /dev/null @@ -1,137 +0,0 @@ -/dts-v1/; - -#include "rt3050.dtsi" - -/ { - compatible = "WNCE2001", "ralink,rt3052-soc"; - model = "Netgear WNCE2001"; - - chosen { - bootargs = "console=ttyS0,115200"; - }; - - gpio-leds { - compatible = "gpio-leds"; - - power-green { - label = "wnce2001:green:power"; - gpios = <&gpio0 8 1>; - }; - - power-red { - label = "wnce2001:red:power"; - gpios = <&gpio0 9 1>; - }; - - wlan-green { - label = "wnce2001:green:wlan"; - gpios = <&gpio0 12 0>; - }; - - wlan-red { - label = "wnce2001:red:wlan"; - gpios = <&gpio0 13 0>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio0 10 1>; - linux,code = <0x198>; - }; - - wps { - label = "wps"; - gpios = <&gpio0 0 1>; - linux,code = <0x211>; - }; - - rt { - label = "rt"; - gpios = <&gpio0 11 1>; - linux,code = <0x100>; - }; - - ap { - label = "ap"; - gpios = <&gpio0 7 1>; - linux,code = <0x101>; - }; - }; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80", "mx25l3205d"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - factory: partition@30000 { - label = "factory"; - reg = <0x30000 0x10000>; - read-only; - }; - - partition@40000 { - label = "config"; - reg = <0x40000 0x20000>; - read-only; - }; - - partition@60000 { - label = "language"; - reg = <0x60000 0x30000>; - read-only; - }; - - partition@90000 { - label = "pot"; - reg = <0x90000 0x10000>; - read-only; - }; - - partition@a0000 { - label = "checksum"; - reg = <0xa0000 0x10000>; - }; - - partition@b0000 { - label = "firmware"; - reg = <0xb0000 0x350000>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - mtd-mac-address = <&factory 0x28>; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; diff --git a/sys/gnu/dts/mips/WNDR3700V5.dts b/sys/gnu/dts/mips/WNDR3700V5.dts deleted file mode 100644 index 9d3d0d53968..00000000000 --- a/sys/gnu/dts/mips/WNDR3700V5.dts +++ /dev/null @@ -1,137 +0,0 @@ -/dts-v1/; - -#include "mt7621.dtsi" - -/ { - compatible = "mediatek,mt7621-eval-board","ralink,mt7621-soc"; - model = "Netgear WNDR3700v5"; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x8000000>; - }; - - chosen { - bootargs = "console=ttyS0,57600 maxcpus=2"; - }; - - gpio-leds { - compatible = "gpio-leds"; - - wps { - label = "wndr3700v5:green:wps"; - gpios = <&gpio0 12 1>; - }; - - power { - label = "wndr3700v5:green:power"; - gpios = <&gpio0 18 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - wps { - label = "wndr3700v5:wps"; - gpios = <&gpio0 7 0>; - linux,code = <0x211>; - }; - - wifi { - label = "wndr3700v5:wifi"; - gpios = <&gpio0 8 0>; - linux,code = <0xf7>; - }; - - reset { - label = "wndr3700v5:reset"; - gpios = <&gpio0 14 0>; - linux,code = <0x198>; - }; - }; - - gpio_export { - compatible = "gpio-export"; - #size-cells = <0>; - - usbpower { - gpio-export,name = "usbpower"; - gpio-export,output = <1>; - gpios = <&gpio0 10 1>; - }; - }; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "mx25l12805d"; - reg = <0>; - linux,modalias = "m25p80", "w25q128"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@f30000 { - label = "factory"; - reg = <0xf30000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0xfb0000>; - }; - }; -}; - -&pcie { - status = "okay"; - - pcie0 { - mt76@0,0 { - reg = <0x0000 0 0 0 0>; - device_type = "pci"; - mediatek,mtd-eeprom = <&factory 0x0004>; - mediatek,2ghz = <0>; - }; - }; - - pcie2 { - mt76@2,0 { - reg = <0x1000 0 0 0 0>; - device_type = "pci"; - mediatek,mtd-eeprom = <&factory 0x8004>; - mediatek,5ghz = <0>; - }; - }; -}; - -ðernet { - mtd-mac-address = <&factory 0x0000000c>; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "rgmii2", "mdio", "wdt"; - ralink,function = "gpio"; - }; - }; -}; diff --git a/sys/gnu/dts/mips/WR512-3GN-4M.dts b/sys/gnu/dts/mips/WR512-3GN-4M.dts deleted file mode 100644 index 45e1463bf0f..00000000000 --- a/sys/gnu/dts/mips/WR512-3GN-4M.dts +++ /dev/null @@ -1,109 +0,0 @@ -/dts-v1/; - -#include "rt3050.dtsi" - -/ { - compatible = "WR512-3GN", "ralink,rt3052-soc"; - model = "WR512-3GN-like router"; - - cfi@1f000000 { - compatible = "cfi-flash"; - reg = <0x1f000000 0x800000>; - bank-width = <2>; - device-width = <2>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x3c8000>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - 3g { - label = "wr512-3gn:green:3g"; - gpios = <&gpio0 9 1>; - }; - - gateway { - label = "wr512-3gn:green:gateway"; - gpios = <&gpio0 11 1>; - }; - - ap { - label = "wr512-3gn:green:ap"; - gpios = <&gpio0 12 1>; - }; - - wps { - label = "wr512-3gn:green:wps"; - gpios = <&gpio0 14 1>; - }; - - station { - label = "wr512-3gn:green:station"; - gpios = <&gpio0 13 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset_wps { - label = "reset_wps"; - gpios = <&gpio0 10 1>; - linux,code = <0x198>; - }; - - mode { - label = "mode"; - gpios = <&gpio0 7 1>; - linux,code = <0x32>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; -}; - -&esw { - mediatek,portmap = <0x2f>; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; - -&otg { - status = "okay"; -}; diff --git a/sys/gnu/dts/mips/WR512-3GN-8M.dts b/sys/gnu/dts/mips/WR512-3GN-8M.dts deleted file mode 100644 index 7e9a0c25ed2..00000000000 --- a/sys/gnu/dts/mips/WR512-3GN-8M.dts +++ /dev/null @@ -1,109 +0,0 @@ -/dts-v1/; - -#include "rt3050.dtsi" - -/ { - compatible = "WR512-3GN", "ralink,rt3052-soc"; - model = "WR512-3GN-like router"; - - cfi@1f000000 { - compatible = "cfi-flash"; - reg = <0x1f000000 0x800000>; - bank-width = <2>; - device-width = <2>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x7b0000>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - 3g { - label = "wr512-3gn:green:3g"; - gpios = <&gpio0 9 1>; - }; - - gateway { - label = "wr512-3gn:green:gateway"; - gpios = <&gpio0 11 1>; - }; - - ap { - label = "wr512-3gn:green:ap"; - gpios = <&gpio0 12 1>; - }; - - wps { - label = "wr512-3gn:green:wps"; - gpios = <&gpio0 14 1>; - }; - - station { - label = "wr512-3gn:green:station"; - gpios = <&gpio0 13 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset_wps { - label = "reset_wps"; - gpios = <&gpio0 10 1>; - linux,code = <0x198>; - }; - - mode { - label = "mode"; - gpios = <&gpio0 7 1>; - linux,code = <0x32>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; -}; - -&esw { - mediatek,portmap = <0x2f>; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; - -&otg { - status = "okay"; -}; diff --git a/sys/gnu/dts/mips/WR6202.dts b/sys/gnu/dts/mips/WR6202.dts deleted file mode 100644 index 534d78d3fa0..00000000000 --- a/sys/gnu/dts/mips/WR6202.dts +++ /dev/null @@ -1,113 +0,0 @@ -/dts-v1/; - -#include "rt3050.dtsi" - -/ { - compatible = "WR6202", "ralink,rt3052-soc"; - model = "AWB WR6202"; - - chosen { - bootargs = "console=ttyS0,115200"; - }; - - gpio-leds { - compatible = "gpio-leds"; - - wps { - label = "wr6202:blue:wps"; - gpios = <&gpio0 14 1>; - }; - - 3g { - label = "wr6202:blue:3g"; - gpios = <&gpio0 13 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio0 10 1>; - linux,code = <0x198>; - }; - - wps { - label = "wps"; - gpios = <&gpio0 0 1>; - linux,code = <0x211>; - }; - }; - - cfi@1f000000 { - compatible = "cfi-flash"; - reg = <0x1f000000 0x800000>; - bank-width = <2>; - device-width = <2>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x7b0000>; - }; - }; - - gpio_export { - compatible = "gpio-export"; - #size-cells = <0>; - - usb { - gpio-export,name = "usb"; - gpio-export,output = <0>; - gpios = <&gpio0 11 0>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - mtd-mac-address = <&factory 0x28>; -}; - -&esw { - mediatek,portmap = <0x3e>; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; - -&otg { - status = "okay"; -}; diff --git a/sys/gnu/dts/mips/WRH-300CR.dts b/sys/gnu/dts/mips/WRH-300CR.dts deleted file mode 100644 index aece2e68847..00000000000 --- a/sys/gnu/dts/mips/WRH-300CR.dts +++ /dev/null @@ -1,125 +0,0 @@ -/dts-v1/; - -#include "mt7620n.dtsi" - -/ { - compatible = "elecom,wrh-300cr", "ralink,mt7620n-soc"; - model = "ELECOM WRH-300CR"; - - gpio-leds { - compatible = "gpio-leds"; - - wps { - label = "wrh-300cr:green:wps"; - gpios = <&gpio2 0 1>; - }; - - ethernet { - label = "wrh-300cr:green:ethernet"; - gpios = <&gpio2 3 1>; - }; - - wlan { - label = "wrh-300cr:green:wlan"; - gpios = <&gpio3 0 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio0 1 1>; - linux,code = <0x198>; - }; - - wps { - label = "wps"; - gpios = <&gpio0 2 1>; - linux,code = <0x211>; - }; - }; -}; - -&gpio1 { - status = "okay"; -}; - -&gpio2 { - status = "okay"; -}; - -&gpio3 { - status = "okay"; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80", "mx25l12805d"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "recover"; - reg = <0x50000 0x1c0000>; - read-only; - }; - - partition@210000 { - label = "firmware"; - reg = <0x210000 0xdf0000>; - }; - }; -}; - -&ehci { - status = "okay"; -}; - -&ohci { - status = "okay"; -}; - -ðernet { - mtd-mac-address = <&factory 0x2e>; - mediatek,portmap = "llllw"; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; - -&pinctrl { - state_default: pinctrl0 { - default { - ralink,group = "i2c", "ephy", "wled"; - ralink,function = "gpio"; - }; - }; -}; diff --git a/sys/gnu/dts/mips/WRTNODE.dts b/sys/gnu/dts/mips/WRTNODE.dts deleted file mode 100644 index 04f5836d0a9..00000000000 --- a/sys/gnu/dts/mips/WRTNODE.dts +++ /dev/null @@ -1,91 +0,0 @@ -/dts-v1/; - -#include "mt7620n.dtsi" - -/ { - compatible = "wrtnode", "ralink,mt7620n-soc"; - model = "WRTNODE"; - - gpio-leds { - compatible = "gpio-leds"; - - indicator { - label = "wrtnode:blue:indicator"; - gpios = <&gpio1 14 1>; - }; - }; -}; - -&gpio1 { - status = "okay"; -}; - -&gpio2 { - status = "okay"; -}; - -&gpio3 { - status = "okay"; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80", "w25q128"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0xfb0000>; - }; - }; -}; - -&ehci { - status = "okay"; -}; - -&ohci { - status = "okay"; -}; - -ðernet { - mtd-mac-address = <&factory 0x4>; - mediatek,portmap = "wllll"; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; - -&pinctrl { - state_default: pinctrl0 { - default { - ralink,group = "ephy", "wled", "pa", "i2c", "wdt", "uartf", "spi refclk"; - ralink,function = "gpio"; - }; - }; -}; diff --git a/sys/gnu/dts/mips/WRTNODE2.dtsi b/sys/gnu/dts/mips/WRTNODE2.dtsi deleted file mode 100644 index 0242314dfb2..00000000000 --- a/sys/gnu/dts/mips/WRTNODE2.dtsi +++ /dev/null @@ -1,89 +0,0 @@ -#include "mt7628an.dtsi" - -/ { - chosen { - bootargs = "console=ttyS0,115200"; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio0 5 1>; - linux,code = <0x198>; - }; - }; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <10000000>; - m25p,chunked-io = <32>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x1fb0000>; - }; - }; - - spidev@1 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "linux,spidev"; - reg = <1>; - spi-max-frequency = <10000000>; - }; -}; - -&uart1 { - status = "okay"; -}; - -&i2c { - status = "okay"; -}; - -ðernet { - mtd-mac-address = <&factory 0x4>; - ralink,port-map = "llllw"; -}; - -&sdhci { - status = "okay"; -}; - -&pcie { - status = "okay"; -}; - -&wmac { - status = "okay"; -}; diff --git a/sys/gnu/dts/mips/WRTNODE2P.dts b/sys/gnu/dts/mips/WRTNODE2P.dts deleted file mode 100644 index 94c21a4249e..00000000000 --- a/sys/gnu/dts/mips/WRTNODE2P.dts +++ /dev/null @@ -1,26 +0,0 @@ -/dts-v1/; - -#include "WRTNODE2.dtsi" - -/ { - compatible = "mediatek,wrtnode2p", "mediatek,mt7628an-soc"; - model = "WRTnode2P"; - - gpio-leds { - compatible = "gpio-leds"; - - indicator { - label = "wrtnode:blue:indicator"; - gpios = <&gpio1 9 1>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "gpio", "jtag"; - ralink,function = "gpio"; - }; - }; -}; diff --git a/sys/gnu/dts/mips/WRTNODE2R.dts b/sys/gnu/dts/mips/WRTNODE2R.dts deleted file mode 100644 index 1c25770e76f..00000000000 --- a/sys/gnu/dts/mips/WRTNODE2R.dts +++ /dev/null @@ -1,26 +0,0 @@ -/dts-v1/; - -#include "WRTNODE2.dtsi" - -/ { - compatible = "mediatek,wrtnode2r", "mediatek,mt7628an-soc"; - model = "WRTnode2R"; - - gpio-leds { - compatible = "gpio-leds"; - - indicator { - label = "wrtnode:blue:indicator"; - gpios = <&gpio1 12 1>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "gpio", "wled_an"; - ralink,function = "gpio"; - }; - }; -}; diff --git a/sys/gnu/dts/mips/WSR-1166.dts b/sys/gnu/dts/mips/WSR-1166.dts deleted file mode 100644 index 8f9991f4a7f..00000000000 --- a/sys/gnu/dts/mips/WSR-1166.dts +++ /dev/null @@ -1,184 +0,0 @@ -/dts-v1/; - -#include "mt7621.dtsi" - -/ { - compatible = "ralink,mt7621-eval-board", "ralink,mt7621-soc"; - model = "Buffalo WSR-1166DHP"; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x8000000>; - }; - - chosen { - bootargs = "console=ttyS0,57600"; - }; - - gpio-leds { - compatible = "gpio-leds"; - - internet_g { - label = "wsr-1166:green:internet"; - gpios = <&gpio1 9 1>; - }; - - router_g { - label = "wsr-1166:green:router"; - gpios = <&gpio1 10 1>; - }; - - router_o { - label = "wsr-1166:orange:router"; - gpios = <&gpio1 11 1>; - }; - - internet_o { - label = "wsr-1166:orange:internet"; - gpios = <&gpio1 12 1>; - }; - - wifi_o { - label = "wsr-1166:orange:wifi"; - gpios = <&gpio1 13 1>; - }; - - power { - label = "wsr-1166:green:power"; - gpios = <&gpio1 14 1>; - }; - - diag { - label = "wsr-1166:orange:diag"; - gpios = <&gpio1 15 1>; - }; - - wifi_g { - label = "wsr-1166:green:wifi"; - gpios = <&gpio1 16 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - power { - label = "power"; - gpios = <&gpio0 18 1>; - linux,code = <0x74>; - }; - - reset { - label = "reset"; - gpios = <&gpio0 3 1>; - linux,code = <0x198>; - }; - - aoss { - label = "aoss"; - gpios = <&gpio0 6 1>; - linux,code = <0x211>; - }; - - auto { - label = "mode"; - gpios = <&gpio0 7 0>; - linux,code = <0x100>; - linux,input-type = <5>; /* EV_SW */ - }; - - ap { - label = "ap"; - gpios = <&gpio0 10 0>; - linux,code = <0x100>; - linux,input-type = <5>; /* EV_SW */ - }; - - router { - label = "router"; - gpios = <&gpio0 12 0>; - linux,code = <0x100>; - linux,input-type = <5>; /* EV_SW */ - }; - }; - - gpio_poweroff { - compatible = "gpio-poweroff"; - gpios = <&gpio0 0 1>; - }; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0xf90000>; - }; - - partition@fe0000 { - label = "board_data"; - reg = <0xfe0000 0x20000>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "uart2", "uart3", "rgmii2", "sdhci"; - ralink,function = "gpio"; - }; - }; -}; - -&pcie { - status = "okay"; - - pcie0 { - mt76@0,0 { - reg = <0x0000 0 0 0 0>; - device_type = "pci"; - mediatek,mtd-eeprom = <&factory 0x8000>; - mediatek,2ghz = <0>; - }; - }; - - pcie1 { - mt76@1,0 { - reg = <0x0000 0 0 0 0>; - device_type = "pci"; - mediatek,mtd-eeprom = <&factory 0x0000>; - mediatek,5ghz = <0>; - }; - }; -}; diff --git a/sys/gnu/dts/mips/WSR-600.dts b/sys/gnu/dts/mips/WSR-600.dts deleted file mode 100644 index 2d08b9369be..00000000000 --- a/sys/gnu/dts/mips/WSR-600.dts +++ /dev/null @@ -1,157 +0,0 @@ -/dts-v1/; - -#include "mt7621.dtsi" - -/ { - compatible = "ralink,mt7621-eval-board", "ralink,mt7621-soc"; - model = "Buffalo WSR-600DHP"; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x4000000>; - }; - - chosen { - bootargs = "console=ttyS0,57600"; - }; - - gpio-leds { - compatible = "gpio-leds"; - - power { - label = "wsr-600:green:power"; - gpios = <&gpio0 12 1>; - }; - - wifi_o { - label = "wsr-600:orange:wifi"; - gpios = <&gpio1 9 1>; - }; - - diag { - label = "wsr-600:orange:diag"; - gpios = <&gpio1 10 1>; - }; - - wifi_g { - label = "wsr-600:green:wifi"; - gpios = <&gpio1 12 1>; - }; - - router_o { - label = "wsr-600:orange:router"; - gpios = <&gpio1 13 1>; - }; - - router_g { - label = "wsr-600:green:router"; - gpios = <&gpio1 14 1>; - }; - - internet_o { - label = "wsr-600:orange:internet"; - gpios = <&gpio1 15 1>; - }; - - internet_g { - label = "wsr-600:green:internet"; - gpios = <&gpio1 16 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - power { - label = "power"; - gpios = <&gpio0 8 1>; - linux,code = <0x74>; - }; - - reset { - label = "reset"; - gpios = <&gpio0 11 1>; - linux,code = <0x198>; - }; - - aoss { - label = "aoss"; - gpios = <&gpio0 18 1>; - linux,code = <0x211>; - }; - - auto { - label = "mode"; - gpios = <&gpio0 7 0>; - linux,code = <0x100>; - linux,input-type = <5>; /* EV_SW */ - }; - - ap { - label = "ap"; - gpios = <&gpio0 6 0>; - linux,code = <0x100>; - linux,input-type = <5>; /* EV_SW */ - }; - - router { - label = "router"; - gpios = <&gpio0 10 0>; - linux,code = <0x100>; - linux,input-type = <5>; /* EV_SW */ - }; - }; - - gpio_poweroff { - compatible = "gpio-poweroff"; - gpios = <&gpio1 11 1>; - }; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0xfb0000>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "uart2", "uart3", "rgmii2", "sdhci"; - ralink,function = "gpio"; - }; - }; -}; diff --git a/sys/gnu/dts/mips/WT1520-4M.dts b/sys/gnu/dts/mips/WT1520-4M.dts deleted file mode 100644 index 9f3d6a74484..00000000000 --- a/sys/gnu/dts/mips/WT1520-4M.dts +++ /dev/null @@ -1,39 +0,0 @@ -/dts-v1/; - -#include "WT1520.dtsi" - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80", "s25fl064k"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x3b0000>; - }; - }; -}; diff --git a/sys/gnu/dts/mips/WT1520-8M.dts b/sys/gnu/dts/mips/WT1520-8M.dts deleted file mode 100644 index 48b62bef4f5..00000000000 --- a/sys/gnu/dts/mips/WT1520-8M.dts +++ /dev/null @@ -1,39 +0,0 @@ -/dts-v1/; - -#include "WT1520.dtsi" - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80", "s25fl064k"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x7b0000>; - }; - }; -}; diff --git a/sys/gnu/dts/mips/WT1520.dtsi b/sys/gnu/dts/mips/WT1520.dtsi deleted file mode 100644 index 8cbf99fde24..00000000000 --- a/sys/gnu/dts/mips/WT1520.dtsi +++ /dev/null @@ -1,46 +0,0 @@ -#include "rt5350.dtsi" - -/ { - compatible = "NEXXWT1520", "ralink,rt5350-soc"; - model = "Nexx WT1520"; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x2000000>; - }; - - chosen { - bootargs = "console=ttyS1,57600"; - }; -}; - -&uart { - pinctrl-names = "default"; - pinctrl-0 = <&uartf_pins>; - status = "okay"; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "jtag"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - mtd-mac-address = <&factory 0x4>; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; - -&ehci { - status = "okay"; -}; - -&ohci { - status = "okay"; -}; diff --git a/sys/gnu/dts/mips/WT3020-4M.dts b/sys/gnu/dts/mips/WT3020-4M.dts deleted file mode 100644 index f611cdfce9a..00000000000 --- a/sys/gnu/dts/mips/WT3020-4M.dts +++ /dev/null @@ -1,100 +0,0 @@ -/dts-v1/; - -#include "mt7620n.dtsi" - -/ { - compatible = "wt3020", "ralink,mt7620n-soc"; - model = "Nexx WT3020"; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio0 1 1>; - linux,code = <0x198>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - power { - label = "wt3020:blue:power"; - gpios = <&gpio3 0 0>; - }; - }; -}; - -&gpio2 { - status = "okay"; -}; - -&gpio3 { - status = "okay"; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80", "w25q32"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x3b0000>; - }; - }; -}; - -&ehci { - status = "okay"; -}; - -&ohci { - status = "okay"; -}; - -ðernet { - mtd-mac-address = <&factory 0x4>; - mediatek,portmap = "wllll"; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; - -&pinctrl { - state_default: pinctrl0 { - default { - ralink,group = "ephy", "wled", "pa", "i2c", "wdt", "uartf"; - ralink,function = "gpio"; - }; - }; -}; diff --git a/sys/gnu/dts/mips/WT3020-8M.dts b/sys/gnu/dts/mips/WT3020-8M.dts deleted file mode 100644 index 3c6230726c5..00000000000 --- a/sys/gnu/dts/mips/WT3020-8M.dts +++ /dev/null @@ -1,100 +0,0 @@ -/dts-v1/; - -#include "mt7620n.dtsi" - -/ { - compatible = "wt3020", "ralink,mt7620n-soc"; - model = "Nexx WT3020"; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio0 1 1>; - linux,code = <0x198>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - power { - label = "wt3020:blue:power"; - gpios = <&gpio3 0 0>; - }; - }; -}; - -&gpio2 { - status = "okay"; -}; - -&gpio3 { - status = "okay"; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80", "w25q64"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x7b0000>; - }; - }; -}; - -&ehci { - status = "okay"; -}; - -&ohci { - status = "okay"; -}; - -ðernet { - mtd-mac-address = <&factory 0x4>; - mediatek,portmap = "wllll"; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; - -&pinctrl { - state_default: pinctrl0 { - default { - ralink,group = "ephy", "wled", "pa", "i2c", "wdt", "uartf"; - ralink,function = "gpio"; - }; - }; -}; diff --git a/sys/gnu/dts/mips/WZR-AGL300NH.dts b/sys/gnu/dts/mips/WZR-AGL300NH.dts deleted file mode 100644 index 23fba7cb8fd..00000000000 --- a/sys/gnu/dts/mips/WZR-AGL300NH.dts +++ /dev/null @@ -1,140 +0,0 @@ -/dts-v1/; - -#include "rt2880.dtsi" - -/ { - #address-cells = <1>; - #size-cells = <1>; - compatible = "WZR-AGL300NH", "ralink,rt2880-soc"; - model = "Buffalo WZR-AGL300NH"; - - pci@440000 { - compatible = "ralink,rt288x-pci"; - reg = <0x00440000 0x20000>; - #address-cells = <1>; - #size-cells = <1>; - status = "ok"; - }; - - cfi@1f000000 { - compatible = "cfi-flash"; - reg = <0x1f000000 0x800000>; - bank-width = <2>; - device-width = <2>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "uboot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "uboot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x3b0000>; - }; - }; - - rtl8366s { - compatible = "realtek,rtl8366s"; - gpio-sda = <&gpio0 1 0>; - gpio-sck = <&gpio0 2 0>; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <100>; - - wps { - label = "wps"; - gpios = <&gpio0 0 1>; - linux,code = <0x211>; - }; - - router { - label = "router_switch"; - gpios = <&gpio0 7 0>; - linux,code = <0x100>; - }; - - reset { - label = "reset"; - gpios = <&gpio0 9 1>; - linux,code = <0x198>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - router { - label = "wzr-agl300nh:green:router"; - gpios = <&gpio0 8 1>; - }; - - diag { - label = "wzr-agl300nh:red:diag"; - gpios = <&gpio0 12 1>; - }; - - security_g { - label = "wzr-agl300nh:orange:security_g"; - gpios = <&gpio0 11 1>; - }; - - security_n { - label = "wzr-agl300nh:orange:security_n"; - gpios = <&gpio0 13 1>; - }; - }; -}; - -&gpio0 { - status = "okay"; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "uartlite", "mdio"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - status = "okay"; - mtd-mac-address = <&factory 0x4>; - - port@0 { - mediatek,fixed-link = <1000 1 1 1>; - }; - - mdio-bus { - status = "okay"; - - phy0: ethernet-phy@0 { - phy-mode = "mii"; - reg = <0>; - }; - }; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; diff --git a/sys/gnu/dts/mips/X5.dts b/sys/gnu/dts/mips/X5.dts deleted file mode 100644 index 86f5c635f1a..00000000000 --- a/sys/gnu/dts/mips/X5.dts +++ /dev/null @@ -1,136 +0,0 @@ -/dts-v1/; - -#include "rt5350.dtsi" - -/ { - compatible = "X5", "ralink,rt5350-soc"; - model = "Poray X5"; - - gpio-leds { - compatible = "gpio-leds"; - - power { - label = "x5:green:power"; - gpios = <&gpio0 13 1>; - }; - - 20 { - label = "x5:green:20"; - gpios = <&gpio0 12 1>; - }; - - 50 { - label = "x5:green:50"; - gpios = <&gpio0 11 1>; - }; - - 80 { - label = "x5:green:80"; - gpios = <&gpio0 7 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - bat { - label = "bat"; - gpios = <&gpio0 9 1>; - linux,code = <0x211>; - }; - - reset { - label = "reset"; - gpios = <&gpio0 10 1>; - linux,code = <0x198>; - }; - - mode { - label = "mode"; - gpios = <&gpio0 14 1>; - linux,code = <0x100>; - linux,input-type = <5>; - }; - }; - - gpio_export { - compatible = "gpio-export"; - #size-cells = <0>; - - usb-mode { - gpio-export,name = "usb-mode"; - gpio-export,output = <0>; - gpios = <&gpio0 18 0>; - }; - }; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80", "gd25q64"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x7b0000>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "jtag", "uartf"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - mtd-mac-address = <&factory 0x4>; -}; - -&esw { - mediatek,portmap = <0x2f>; - mediatek,led_polarity = <1>; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; - ralink,led-polarity = <1>; -}; - -&ehci { - status = "okay"; -}; - -&ohci { - status = "okay"; -}; diff --git a/sys/gnu/dts/mips/X8.dts b/sys/gnu/dts/mips/X8.dts deleted file mode 100644 index 733bbb55d49..00000000000 --- a/sys/gnu/dts/mips/X8.dts +++ /dev/null @@ -1,97 +0,0 @@ -/dts-v1/; - -#include "rt5350.dtsi" - -/ { - compatible = "X8", "ralink,rt5350-soc"; - model = "Poray X8"; - - gpio-leds { - compatible = "gpio-leds"; - - power { - label = "x8:green:power"; - gpios = <&gpio0 13 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio0 10 1>; - linux,code = <0x198>; - }; - }; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80", "gd25q64"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x7b0000>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "jtag", "uartf"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - mtd-mac-address = <&factory 0x4>; -}; - -&esw { - mediatek,portmap = <0x2f>; - mediatek,led_polarity = <1>; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; - ralink,led-polarity = <1>; -}; - -&ehci { - status = "okay"; -}; - -&ohci { - status = "okay"; -}; diff --git a/sys/gnu/dts/mips/XDXRN502J.dts b/sys/gnu/dts/mips/XDXRN502J.dts deleted file mode 100644 index 34a29cc74b9..00000000000 --- a/sys/gnu/dts/mips/XDXRN502J.dts +++ /dev/null @@ -1,92 +0,0 @@ -/dts-v1/; - -#include "rt3050.dtsi" - -/ { - compatible = "XDXRN502J", "ralink,rt3052-soc"; - model = "XDX RN502J"; - - cfi@1f000000 { - compatible = "cfi-flash"; - reg = <0x1f000000 0x800000>; - bank-width = <2>; - device-width = <2>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x3b0000>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - wifi { - label = "xdxrn502j:green:wifi"; - gpios = <&gpio0 7 1>; - }; - - power { - label = "xdxrn502j:green:power"; - gpios = <&gpio0 9 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio0 10 1>; - linux,code = <0x198>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - mtd-mac-address = <&factory 0x28>; -}; - -&esw { - mediatek,portmap = <0x3e>; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; - -&otg { - status = "okay"; -}; diff --git a/sys/gnu/dts/mips/Y1.dts b/sys/gnu/dts/mips/Y1.dts deleted file mode 100644 index ac9b7d56c04..00000000000 --- a/sys/gnu/dts/mips/Y1.dts +++ /dev/null @@ -1,49 +0,0 @@ -/dts-v1/; - -#include "Y1.dtsi" - -/ { - compatible = "lenovo,Y1", "ralink,mt7620a-soc"; - model = "Lenovo Y1"; - - gpio-leds { - compatible = "gpio-leds"; - - power1 { - label = "y1:blue:power"; - gpios = <&gpio0 9 1>; - }; - - wlan1 { - label = "y1:blue:wifi"; - gpios = <&gpio3 0 1>; - }; - - wlan2 { - label = "y1:blue:wifi5g"; - gpios = <&gpio2 10 1>; - }; - - usb { - label = "y1:blue:usb"; - gpios = <&gpio2 12 1>; - }; - - lan { - label = "y1:blue:lan"; - gpios = <&gpio2 15 1>; - }; - - internet { - label = "y1:blue:internet"; - gpios = <&gpio2 11 1>; - }; - }; -}; - -ðernet { - pinctrl-names = "default"; - pinctrl-0 = <&ephy_pins>; - mtd-mac-address = <&factory 0x4>; - mediatek,portmap = "llllw"; -}; diff --git a/sys/gnu/dts/mips/Y1.dtsi b/sys/gnu/dts/mips/Y1.dtsi deleted file mode 100644 index 201f48b6261..00000000000 --- a/sys/gnu/dts/mips/Y1.dtsi +++ /dev/null @@ -1,107 +0,0 @@ -#include "mt7620a.dtsi" - -/ { - chosen { - bootargs = "console=ttyS0,115200"; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio0 11 1>; - linux,code = <0x198>; - }; - }; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio2 { - status = "okay"; -}; - -&gpio3 { - status = "okay"; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80", "w25q128"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0xfb0000>; - }; - }; -}; - -&ehci { - status = "okay"; -}; - -&ohci { - status = "okay"; -}; - -&pcie { - status = "okay"; - - pcie-bridge { - mt76@0,0 { - reg = <0x0000 0 0 0 0>; - device_type = "pci"; - mediatek,mtd-eeprom = <&factory 0x8000>; - mediatek,2ghz = <0>; - }; - }; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "uartf", "wled", "nd_sd"; - ralink,function = "gpio"; - }; - - pa { - ralink,group = "pa"; - ralink,function = "pa"; - }; - }; -}; diff --git a/sys/gnu/dts/mips/Y1S.dts b/sys/gnu/dts/mips/Y1S.dts deleted file mode 100644 index cfa5e2123aa..00000000000 --- a/sys/gnu/dts/mips/Y1S.dts +++ /dev/null @@ -1,106 +0,0 @@ -/dts-v1/; - -#include "Y1.dtsi" - -/ { - compatible = "lenovo,Y1S", "ralink,mt7620a-soc"; - model = "Lenovo Y1S"; - - gpio_export { - compatible = "gpio-export"; - #size-cells = <0>; - /* GPIO 54、55、56 USB1、2、3 */ - usb0 { - gpio-export,name = "usb0"; - gpio-export,output = <1>; // GPIOF_OUT_INIT_HIGH - gpios = <&gpio2 14 0>; // GPIO2:40+14=GPIO 54 - }; - usb1 { - gpio-export,name = "usb1"; - gpio-export,output = <1>; - gpios = <&gpio2 15 0>; - }; - usb2 { - gpio-export,name = "usb2"; - gpio-export,output = <1>; - gpios = <&gpio2 16 0>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - power1 { - label = "y1s:yellow:power"; - gpios = <&gpio0 14 1>; - }; - - power2 { - label = "y1s:blue:power"; - gpios = <&gpio0 9 1>; - }; - - wlan1 { - label = "y1s:yellow:wifi"; - gpios = <&gpio3 0 1>; - }; - - wlan2 { - label = "y1s:blue:wifi"; - gpios = <&gpio2 10 1>; - }; - - usb1 { - label = "y1s:yellow:usb"; - gpios = <&gpio2 13 1>; - }; - - usb2 { - label = "y1s:blue:usb"; - gpios = <&gpio2 12 1>; - }; - - internet { - label = "y1s:blue:internet"; - gpios = <&gpio2 11 1>; - }; - }; -}; - -ðernet { - status = "okay"; - mtd-mac-address = <&factory 0x4>; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>; - mediatek,portmap = "wllll"; - - port@4 { - status = "okay"; - phy-handle = <&phy4>; - phy-mode = "rgmii"; - }; - - port@5 { - status = "okay"; - phy-handle = <&phy5>; - phy-mode = "rgmii"; - }; - - mdio-bus { - status = "okay"; - - phy4: ethernet-phy@4 { - reg = <4>; - phy-mode = "rgmii"; - }; - - phy5: ethernet-phy@5 { - reg = <5>; - phy-mode = "rgmii"; - }; - }; -}; - -&gsw { - mediatek,port4 = "gmac"; -}; diff --git a/sys/gnu/dts/mips/YOUKU-YK1.dts b/sys/gnu/dts/mips/YOUKU-YK1.dts deleted file mode 100644 index a9c13e50b66..00000000000 --- a/sys/gnu/dts/mips/YOUKU-YK1.dts +++ /dev/null @@ -1,124 +0,0 @@ -/dts-v1/; - -#include "mt7620a.dtsi" - -/ { - compatible = "YOUKU-YK1", "ralink,mt7620a-soc"; - model = "YOUKU YK1"; - - gpio-leds { - compatible = "gpio-leds"; - wan { - label = "youku-yk1:blue:wan"; - gpios = <&gpio2 4 1>; - }; - air { - label = "youku-yk1:blue:air"; - gpios = <&gpio3 0 1>; - }; - usb { - label = "youku-yk1:blue:usb"; - gpios = <&gpio1 11 1>; - }; - power { - label = "youku-yk1:blue:power"; - gpios = <&gpio1 5 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - reset { - label = "reset"; - gpios = <&gpio0 1 1>; - linux,code = <0x198>; - }; - }; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&gpio2 { - status = "okay"; -}; - -&gpio3 { - status = "okay"; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80", "w25q256"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x1fb0000>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - default { - ralink,group = "i2c", "uartf", "rgmii1", "rgmii2", "ephy", "wled", "nd_sd"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - pinctrl-names = "default"; - pinctrl-0 = <&ephy_pins>; - mtd-mac-address = <&factory 0x4>; - mediatek,portmap = "llllw"; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; - -&sdhci { - status = "okay"; -}; - -&ehci { - status = "okay"; -}; - -&ohci { - status = "okay"; -}; diff --git a/sys/gnu/dts/mips/ZBT-WA05.dts b/sys/gnu/dts/mips/ZBT-WA05.dts deleted file mode 100644 index c2d51c300ac..00000000000 --- a/sys/gnu/dts/mips/ZBT-WA05.dts +++ /dev/null @@ -1,118 +0,0 @@ -/dts-v1/; - -#include "mt7620n.dtsi" - -/ { - compatible = "zbtlink,zbt-wa05", "ralink,mt7620n-soc"; - model = "Zbtlink ZBT-WA05"; - - chosen { - bootargs = "console=ttyS0,115200"; - }; - - gpio-leds { - compatible = "gpio-leds"; - - power { - label = "zbt-wa05:blue:power"; - gpios = <&gpio1 14 1>; - }; - - usb { - label = "zbt-wa05:blue:usb"; - gpios = <&gpio1 15 0>; - }; - - air { - label = "zbt-wa05:blue:air"; - gpios = <&gpio3 0 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio0 1 1>; - linux,code = <0x198>; - }; - }; -}; - -&gpio1 { - status = "okay"; -}; - -&gpio2 { - status = "okay"; -}; - -&gpio3 { - status = "okay"; -}; - -&spi0 { - status = "okay"; - - en25q64@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x760000>; - }; - }; -}; - -&ehci { - status = "okay"; -}; - -&ohci { - status = "okay"; -}; - -ðernet { - mtd-mac-address = <&factory 0x4>; - mediatek,portmap = "wllll"; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; - -&pinctrl { - state_default: pinctrl0 { - default { - ralink,group = "i2c", "spi refclk", "wled"; - ralink,function = "gpio"; - }; - }; -}; diff --git a/sys/gnu/dts/mips/ZBT-WE826.dts b/sys/gnu/dts/mips/ZBT-WE826.dts deleted file mode 100644 index 75c99a7fdc5..00000000000 --- a/sys/gnu/dts/mips/ZBT-WE826.dts +++ /dev/null @@ -1,122 +0,0 @@ -/dts-v1/; - -#include "mt7620a.dtsi" - -/ { - compatible = "zbtlink,zbt-we826", "ralink,mt7620a-soc"; - model = "ZBT-WE826"; - - chosen { - bootargs = "console=ttyS0,115200"; - }; - - gpio-leds { - compatible = "gpio-leds"; - power { - label = "zbt-we826:green:power"; - gpios = <&gpio1 14 0>; - }; - usb { - label = "zbt-we826:green:usb"; - gpios = <&gpio1 15 0>; - }; - air { - label = "zbt-we826:green:wifi"; - gpios = <&gpio3 0 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - reset { - label = "reset"; - gpios = <&gpio0 1 1>; - linux,code = <0x198>; - }; - }; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&gpio3 { - status = "okay"; -}; - -&spi0 { - status = "okay"; - - en25q128@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "w25q128"; - reg = <0>; - linux,modalias = "m25p80"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0xfb0000>; - }; - }; -}; - -&sdhci { - status = "okay"; -}; - -&ehci { - status = "okay"; -}; - -&ohci { - status = "okay"; -}; - -ðernet { - mtd-mac-address = <&factory 0x4>; - ralink,port-map = "wllll"; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; - -&pinctrl { - state_default: pinctrl0 { - default { - ralink,group = "i2c", "uartf", "wled", "spi refclk", "pa"; - ralink,function = "gpio"; - }; - }; -}; - -&pcie { - status = "okay"; -}; diff --git a/sys/gnu/dts/mips/ZBT-WG2626.dts b/sys/gnu/dts/mips/ZBT-WG2626.dts deleted file mode 100644 index 31f0ffb3736..00000000000 --- a/sys/gnu/dts/mips/ZBT-WG2626.dts +++ /dev/null @@ -1,126 +0,0 @@ -/dts-v1/; - -#include "mt7621.dtsi" - -/ { - compatible = "mediatek,mt7621-eval-board", "mediatek,mt7621-soc"; - model = "ZBT-WG2626"; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x1c000000>, <0x20000000 0x4000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200"; - }; - - palmbus: palmbus@1E000000 { - i2c@900 { - compatible = "ralink,i2c-mt7621"; - reg = <0x900 0x100>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c_pins>; - status = "okay"; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio0 18 1>; - linux,code = <0x198>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - status { - label = "zbt-wg2626:green:status"; - gpios = <&gpio0 24 1>; - }; - }; -}; - -&sdhci { - status = "okay"; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0xfb0000>; - }; - }; -}; - -&pcie { - status = "okay"; - - pcie0 { - mt76@0,0 { - reg = <0x0000 0 0 0 0>; - device_type = "pci"; - mediatek,mtd-eeprom = <&factory 0x8000>; - mediatek,2ghz = <0>; - }; - }; - - pcie1 { - mt76@1,0 { - reg = <0x0000 0 0 0 0>; - device_type = "pci"; - mediatek,mtd-eeprom = <&factory 0x0000>; - mediatek,5ghz = <0>; - }; - }; -}; - -ðernet { - mtd-mac-address = <&factory 0xe000>; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "wdt", "rgmii2", "wdt rst", "jtag", "mdio"; - ralink,function = "gpio"; - }; - }; -}; diff --git a/sys/gnu/dts/mips/ZBT-WG3526.dts b/sys/gnu/dts/mips/ZBT-WG3526.dts deleted file mode 100644 index 2fc8d90e302..00000000000 --- a/sys/gnu/dts/mips/ZBT-WG3526.dts +++ /dev/null @@ -1,126 +0,0 @@ -/dts-v1/; - -#include "mt7621.dtsi" - -/ { - compatible = "mediatek,mt7621-eval-board", "mediatek,mt7621-soc"; - model = "ZBT-WG3526"; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x1c000000>, <0x20000000 0x4000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200"; - }; - - palmbus: palmbus@1E000000 { - i2c@900 { - compatible = "ralink,i2c-mt7621"; - reg = <0x900 0x100>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c_pins>; - status = "okay"; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio0 18 1>; - linux,code = <0x198>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - status { - label = "zbt-wg3526:green:status"; - gpios = <&gpio0 24 1>; - }; - }; -}; - -&sdhci { - status = "okay"; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0xfb0000>; - }; - }; -}; - -&pcie { - status = "okay"; - - pcie0 { - mt76@0,0 { - reg = <0x0000 0 0 0 0>; - device_type = "pci"; - mediatek,mtd-eeprom = <&factory 0x0000>; - mediatek,5ghz = <0>; - }; - }; - - pcie1 { - mt76@1,0 { - reg = <0x0000 0 0 0 0>; - device_type = "pci"; - mediatek,mtd-eeprom = <&factory 0x8000>; - mediatek,2ghz = <0>; - }; - }; -}; - -ðernet { - mtd-mac-address = <&factory 0xe000>; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "wdt", "rgmii2", "wdt rst", "jtag", "mdio"; - ralink,function = "gpio"; - }; - }; -}; diff --git a/sys/gnu/dts/mips/ZBT-WR8305RT.dts b/sys/gnu/dts/mips/ZBT-WR8305RT.dts deleted file mode 100644 index 694b7cfa962..00000000000 --- a/sys/gnu/dts/mips/ZBT-WR8305RT.dts +++ /dev/null @@ -1,115 +0,0 @@ -/dts-v1/; - -#include "mt7620n.dtsi" - -/ { - compatible = "zbtlink,zbt-wr8305rt", "ralink,mt7620n-soc"; - model = "Zbtlink ZBT-WR8305RT"; - - gpio-leds { - compatible = "gpio-leds"; - - sys { - label = "zbt-wr8305rt:green:sys"; - gpios = <&gpio1 14 1>; - }; - - lan { - label = "zbt-wr8305rt:green:usb"; - gpios = <&gpio1 15 1>; - }; - - wifi { - label = "zbt-wr8305rt:green:wifi"; - gpios = <&gpio3 0 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio0 1 1>; - linux,code = <0x198>; - }; - }; -}; - -&gpio1 { - status = "okay"; -}; - -&gpio3 { - status = "okay"; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80", "en25q64"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x7b0000>; - }; - }; -}; - -&ehci { - status = "okay"; -}; - -&ohci { - status = "okay"; -}; - -ðernet { - mtd-mac-address = <&factory 0x4>; - mediatek,portmap = "llllw"; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; - -&pinctrl { - state_default: pinctrl0 { - ephy { - ralink,group = "ephy"; - ralink,function = "ephy"; - }; - - default { - ralink,group = "i2c", "uartf", "spi refclk", "wled"; - ralink,function = "gpio"; - }; - }; -}; diff --git a/sys/gnu/dts/mips/ZTE-Q7.dts b/sys/gnu/dts/mips/ZTE-Q7.dts deleted file mode 100644 index 2c4c2e57121..00000000000 --- a/sys/gnu/dts/mips/ZTE-Q7.dts +++ /dev/null @@ -1,111 +0,0 @@ -/dts-v1/; - -#include "mt7620a.dtsi" - -/ { - compatible = "ZTE-Q7", "ralink,mt7620a-soc"; - model = "ZTE Q7"; - - gpio-leds { - compatible = "gpio-leds"; - - statred { - label = "zte-q7:red:status"; - gpios = <&gpio0 13 1>; - }; - - statblue { - label = "zte-q7:blue:status"; - gpios = <&gpio0 9 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio1 2 1>; - linux,code = <0x198>; - }; - }; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&spi0 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80", "en25q64"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x7b0000>; - }; - }; -}; - -&pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "uartf", "rgmii1", "rgmii2", "ephy", "wled", "nd_sd"; - ralink,function = "gpio"; - }; - }; -}; - -ðernet { - pinctrl-names = "default"; - pinctrl-0 = <&ephy_pins>; - mtd-mac-address = <&factory 0x4>; - mediatek,portmap = "wllll"; -}; - -&wmac { - ralink,mtd-eeprom = <&factory 0>; -}; - -&sdhci { - status = "okay"; -}; - -&ehci { - status = "okay"; -}; - -&ohci { - status = "okay"; -}; diff --git a/sys/gnu/dts/mips/ingenic/canna.dts b/sys/gnu/dts/mips/ingenic/canna.dts deleted file mode 100644 index 98ddb98f7ee..00000000000 --- a/sys/gnu/dts/mips/ingenic/canna.dts +++ /dev/null @@ -1,42 +0,0 @@ -/dts-v1/; -#include -#include -#include "x1000.dtsi" - -/ { - compatible = "ingenic,x1000"; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - }; - - chosen { - stdout-path = &uart2; - }; - - memory { - device_type = "memory"; - reg = <0x0 0x2000000>; /* 32 MiB at 0x0 */ - }; -}; - -&ext { - clock-frequency = <48000000>; -}; - -&msc0 { - bus-width = <4>; - max-frequency = <6000000>; - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pins_msc0_pa>; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pins_uart2_dataplusflow>; -}; diff --git a/sys/gnu/dts/mips/ingenic/ci20.dts b/sys/gnu/dts/mips/ingenic/ci20.dts deleted file mode 100644 index 456c8b83f0d..00000000000 --- a/sys/gnu/dts/mips/ingenic/ci20.dts +++ /dev/null @@ -1,395 +0,0 @@ -/dts-v1/; -#include -#include -#include "jz4780.dtsi" - -/ { - compatible = "imgtec,ci20", "ingenic,jz4780"; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - serial3 = &uart3; - serial4 = &uart4; - }; - - chosen { - stdout-path = &uart4; - }; - - memory { - device_type = "memory"; - reg = <0x0 0x10000000 - 0x30000000 0x30000000>; - }; - - audio: audio-ci20 { - compatible = "ingenic,ci20-audio"; - ingenic,i2s-controller = <&i2s>; - ingenic,codec = <&codec>; - }; - - eth0_power: fixedregulator@0 { - compatible = "regulator-fixed"; - regulator-name = "eth0_power"; - gpio = <&gpb 25 GPIO_ACTIVE_LOW>; - enable-active-high; - }; - - hdmi_power: fixedregulator@1 { - compatible = "regulator-fixed"; - regulator-name = "hdmi_power"; - gpio = <&gpa 25 GPIO_ACTIVE_LOW>; - enable-active-high; - regulator-always-on; - }; - - wifi_power: fixedregulator@2 { - compatible = "regulator-fixed"; - regulator-name = "wifi_power_gpio"; - gpio = <&gpb 19 0>; - enable-active-high; - - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - }; - - /* HACK: Keeping wifi reset high. No simple driver fix */ - wifi_reset: fixedregulator@3 { - compatible = "regulator-fixed"; - regulator-name = "wifi_reset_gpio"; - gpio = <&gpf 7 0>; - enable-active-high; - regulator-always-on; - }; - - /* HACK: Keeping BT reset high. No simple driver fix */ - bt_reset: fixedregulator@4 { - compatible = "regulator-fixed"; - regulator-name = "bt_reset_gpio"; - gpio = <&gpf 8 0>; - enable-active-high; - }; - - /* HACK: Keeping BT_reg_on high. No simple driver fix */ - bt_reg_on: fixedregulator@5 { - compatible = "regulator-fixed"; - regulator-name = "bt_reg_on_gpio"; - gpio = <&gpf 4 0>; - enable-active-high; - regulator-always-on; - }; - - /* HACK: Keeping BT wake high. No simple driver fix */ - bt_wake: fixedregulator@6 { - compatible = "regulator-fixed"; - regulator-name = "bt_wake_gpio"; - gpio = <&gpf 5 0>; - enable-active-high; - regulator-always-on; - }; - - ir: ir-receiver { - compatible = "gpio-ir-receiver"; - gpios = <&gpe 3 GPIO_ACTIVE_LOW>; - }; - - bt-rfkill { - compatible = "rfkill-regulator"; - label = "bt-reset"; - type = ; - vrfkill-supply = <&bt_reset>; - }; - - leds { - compatible = "gpio-leds"; - led3 { - gpios = <&gpc 0 0>; - linux,default-trigger = "cpu0"; - }; - led2 { - gpios = <&gpc 1 0>; - linux,default-trigger = "cpu1"; - }; - led1 { - gpios = <&gpc 2 0>; - linux,default-trigger = "nand-disk"; - }; - led0 { - gpios = <&gpc 3 0>; - linux,default-trigger = "none"; - }; - }; -}; - -&ext { - clock-frequency = <48000000>; -}; - -&msc0 { - bus-width = <4>; - max-frequency = <50000000>; - cd-gpios = <&gpf 20 GPIO_ACTIVE_LOW>; - - pinctrl-names = "default"; - pinctrl-0 = <&pins_msc0_pe>; -}; - -&msc1 { - bus-width = <4>; - max-frequency = <24000000>; - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pins_msc1_pd>; - vmmc-supply = <&wifi_power>; -}; - -&ehci { - ingenic,vbus-gpio = <&gpf 15 0>; -}; - -&ohci { - ingenic,vbus-gpio = <&gpf 15 0>; -}; - -&nemc { - /* - * Only CLE/ALE are needed for the devices that are connected, rather - * than the full address line set. - */ - pinctrl-names = "default"; - pinctrl-0 = <&pins_nemc_data - &pins_nemc_cle_ale - &pins_nemc_rd_we - &pins_nemc_frd_fwe>; - - nand: nand@1 { - compatible = "ingenic,jz4780-nand"; - reg = <1 0 0x1000000>; - - ingenic,nemc-tAS = <10>; - ingenic,nemc-tAH = <5>; - ingenic,nemc-tBP = <10>; - ingenic,nemc-tAW = <15>; - ingenic,nemc-tSTRV = <100>; - - ingenic,bch-device = <&bch>; - ingenic,ecc-size = <1024>; - ingenic,ecc-strength = <24>; - - ingenic,busy-gpio = <&gpa 20 GPIO_ACTIVE_LOW>; - ingenic,wp-gpio = <&gpf 22 GPIO_ACTIVE_LOW>; - - pinctrl-names = "default"; - pinctrl-0 = <&pins_nemc_cs1>; - - #address-cells = <2>; - #size-cells = <2>; - - partition@0 { - label = "u-boot-spl"; - reg = <0x0 0x0 0x0 0x800000>; - }; - - partition@0x800000 { - label = "u-boot"; - reg = <0x0 0x800000 0x0 0x200000>; - }; - - partition@0xa00000 { - label = "u-boot-env"; - reg = <0x0 0xa00000 0x0 0x200000>; - }; - - partition@0xc00000 { - label = "boot"; - reg = <0x0 0xc00000 0x0 0x4000000>; - }; - - partition@0x8c00000 { - label = "system"; - reg = <0x0 0x4c00000 0x1 0xfb400000>; - }; - }; - - dm9000@6 { - compatible = "davicom,dm9000"; - davicom,no-eeprom; - - pinctrl-names = "default"; - pinctrl-0 = <&pins_nemc_cs6>; - - reg = <6 0x0 1 /* addr */ - 6 0x2 1>; /* data */ - - ingenic,nemc-tAS = <15>; - ingenic,nemc-tAH = <10>; - ingenic,nemc-tBP = <20>; - ingenic,nemc-tAW = <50>; - ingenic,nemc-tSTRV = <100>; - - reset-gpios = <&gpf 12 GPIO_ACTIVE_HIGH>; - vcc-supply = <ð0_power>; - - interrupt-parent = <&gpe>; - interrupts = <19 0x4>; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&pins_uart0_data>; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pins_uart1_data>; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pins_uart2_dataplusflow>; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pins_uart3_data>; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pins_uart4_data>; -}; - -&i2c0 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pins_i2c0_data>; - - pmic: act8600@5a { - compatible = "active-semi,act8600"; - reg = <0x5a>; - - regulators { - vcore1v_reg: DCDC_REG1 { - regulator-name = "vcore1v2"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - }; - - vddmem1v5_reg: DCDC_REG2 { - regulator-name = "vddmem1v5"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - }; - - vccio3v3_reg: DCDC_REG3 { - regulator-name = "vccio3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vcc2v5_reg: LDO_REG5 { - regulator-name = "vcc2.5"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - vwifi_reg: LDO_REG6 { - regulator-name = "vwifi3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vcim2v8_reg: LDO_REG7 { - regulator-name = "vcim2v8"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - vcim1v5_reg: LDO_REG8 { - regulator-name = "vcim1v5"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - }; - - /* Do not disable RTC as they connect to reset line */ - vrtc1v8_reg: LDO_REG9 { - regulator-name = "vrtc1v8"; - regulator-always-on; - }; - - vrtc1v1_reg: LDO_REG10 { - regulator-name = "vrtc1v2"; - regulator-always-on; - }; - }; - }; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pins_i2c1_data>; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pins_i2c2_data>; - - ov5640@0x3C { - compatible = "omnivision,ov5640"; - reg = <0x3C>; - - core-supply = <&vcim1v5_reg>; - analog-supply = <&vcim2v8_reg>; - - gpio-enable = <&gpb 18 0>; - gpio-reset = <&gpb 26 0>; - - remote = <&cim>; - port { - ov5640_1: endpoint { - bus-width = <8>; - remote-endpoint = <&cim>; - }; - }; - }; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pins_i2c3_data>; -}; - -&i2c4 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pins_i2c4_data_pf>; -}; - -&cim { - clock-frequency = <24000000>; - - port { - #address-cells = <1>; - #size-cells = <0>; - - /* Parallel bus endpoint */ - camera: endpoint@0 { - reg = <0>; /* Local endpoint # */ - remote-endpoint = <&ov5640_1>; - hsync-active = <1>; /* Active high */ - vsync-active = <1>; /* Active high */ - pclk-sample = <0>; /* Falling */ - }; - }; -}; diff --git a/sys/gnu/dts/mips/ingenic/jz4780.dtsi b/sys/gnu/dts/mips/ingenic/jz4780.dtsi deleted file mode 100644 index c53ee03f463..00000000000 --- a/sys/gnu/dts/mips/ingenic/jz4780.dtsi +++ /dev/null @@ -1,768 +0,0 @@ -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - compatible = "ingenic,jz4780"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "ingenic,xburst"; - reg = <0>; - }; - cpu1: cpu@1 { - compatible = "ingenic,xburst"; - reg = <1>; - clocks = <&cgu JZ4780_CLK_CORE1>; - }; - }; - - cpuintc: cpuintc@0 { - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - compatible = "mti,cpu-interrupt-controller"; - }; - - intc: intc@10001000 { - compatible = "ingenic,jz4780-intc"; - reg = <0x10001000 0x50>; - - interrupt-controller; - #interrupt-cells = <1>; - - interrupt-parent = <&cpuintc>; - interrupts = <2>; - }; - - ext: ext { - compatible = "fixed-clock"; - #clock-cells = <0>; - }; - - rtc: rtc { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - - cgu: jz4780-cgu@10000000 { - compatible = "ingenic,jz4780-cgu"; - reg = <0x10000000 0x100>; - - clocks = <&ext>, <&rtc>; - clock-names = "ext", "rtc"; - - #clock-cells = <1>; - }; - - gpu: jz4780-sgx@13040000 { - compatible = "ingenic,jz4780-sgx"; - reg = <0x13040000 0x4000>; - - clocks = <&cgu JZ4780_CLK_GPU>; - clock-names = "gpu"; - - interrupt-parent = <&intc>; - interrupts = <63>; - }; - - apb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <>; - - tcu@0x10002000 { - compatible = "ingenic,jz4780-tcu"; - reg = <0x10002000 0x140>; - - interrupt-parent = <&intc>; - interrupts = <27 26 25>; - }; - - watchdog: jz47xx-watchdog@0x10002000 { - compatible = "ingenic,jz4780-watchdog"; - reg = <0x10002000 0x100>; - - clocks = <&rtc>; - clock-names = "rtc"; - }; - - rtcdev: rtcdev@10003000 { - compatible = "ingenic,jz4780-rtc"; - reg = <0x10003000 0x4c>; - interrupt-parent = <&intc>; - interrupts = <32>; - }; - - i2s: i2s@10020000 { - compatible = "ingenic,jz4780-i2s"; - reg = <0x10020000 0x94>; - - clocks = <&cgu JZ4780_CLK_AIC>, <&cgu JZ4780_CLK_I2SPLL>; - clock-names = "aic", "i2s"; - - dmas = <&dma 0 JZ4780_DMA_I2S0_RX 0xffffffff>, <&dma JZ4780_DMA_I2S0_TX 0 0xffffffff>; - dma-names = "rx" , "tx"; - - }; - - codec: codec@100200a4 { - compatible = "ingenic,jz4780-codec"; - reg = <0x100200a4 0x8>; - - clocks = <&cgu JZ4780_CLK_I2SPLL>; - clock-names = "i2s"; - - }; - - pinctrl@0x10010000 { - compatible = "ingenic,jz4780-pinctrl"; - reg = <0x10010000 0x600>; - - gpa: gpa { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - - interrupt-parent = <&intc>; - interrupts = <17>; - - ingenic,pull-ups = <0x3fffffff>; - }; - - gpb: gpb { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - - interrupt-parent = <&intc>; - interrupts = <16>; - - ingenic,pull-downs = <0x000f0c03>; - ingenic,pull-ups = <0xfff0030c>; - }; - - gpc: gpc { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - - interrupt-parent = <&intc>; - interrupts = <15>; - - ingenic,pull-ups = <0xffffffff>; - }; - - gpd: gpd { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - - interrupt-parent = <&intc>; - interrupts = <14>; - - ingenic,pull-downs = <0x0000b000>; - ingenic,pull-ups = <0xffff4fff>; - }; - - gpe: gpe { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - - interrupt-parent = <&intc>; - interrupts = <13>; - - ingenic,pull-downs = <0x00000483>; - ingenic,pull-ups = <0xfffffb7c>; - }; - - gpf: gpf { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - - interrupt-parent = <&intc>; - interrupts = <12>; - - ingenic,pull-downs = <0x00580ff0>; - ingenic,pull-ups = <0xffa7f00f>; - }; - - pincfg_nobias: nobias { - bias-disable; - }; - - pincfg_pull_up: pull_up { - bias-pull-up; - }; - - pincfg_pull_down: pull_down { - bias-pull-down; - }; - - pinfunc_uart0: uart0 { - pins_uart0_data: uart0-data { - ingenic,pins = <&gpf 0 0 &pincfg_pull_up /* rxd */ - &gpf 3 0 &pincfg_nobias>; /* txd */ - }; - - pins_uart0_dataplusflow: uart0-dataplusflow { - ingenic,pins = <&gpf 0 0 &pincfg_pull_up /* rxd */ - &gpf 1 0 &pincfg_nobias /* cts */ - &gpf 2 0 &pincfg_nobias /* rts */ - &gpf 3 0 &pincfg_nobias>; /* txd */ - }; - }; - - pinfunc_uart1: uart1 { - pins_uart1_data: uart1-data { - ingenic,pins = <&gpd 26 0 &pincfg_pull_up /* rxd */ - &gpd 28 0 &pincfg_nobias>; /* txd */ - }; - - pins_uart1_dataplusflow: uart1-dataplusflow { - ingenic,pins = <&gpd 26 0 &pincfg_pull_up /* rxd */ - &gpd 27 0 &pincfg_nobias /* cts */ - &gpd 29 0 &pincfg_nobias /* rts */ - &gpd 28 0 &pincfg_nobias>; /* txd */ - }; - }; - - pinfunc_uart2: uart2 { - pins_uart2_data: uart2-data { - ingenic,pins = <&gpd 6 1 &pincfg_nobias /* rxd */ - &gpd 7 1 &pincfg_nobias>; /* txd */ - }; - - pins_uart2_dataplusflow: uart2-dataplusflow { - ingenic,pins = <&gpd 6 1 &pincfg_nobias /* rxd */ - &gpd 5 1 &pincfg_nobias /* cts */ - &gpd 4 1 &pincfg_nobias /* rts */ - &gpd 7 1 &pincfg_nobias>; /* txd */ - }; - }; - - pinfunc_uart3: uart3 { - pins_uart3_data: uart3-data { - ingenic,pins = <&gpd 12 0 &pincfg_pull_down /* rxd */ - &gpe 5 1 &pincfg_nobias>; /* txd */ - }; - - pins_uart3_dataplusflow: uart3-dataplusflow { - ingenic,pins = <&gpd 12 0 &pincfg_pull_down /* rxd */ - &gpe 5 1 &pincfg_nobias /* txd */ - &gpe 8 0 &pincfg_nobias /* cts */ - &gpe 9 0 &pincfg_nobias>; /* rts */ - }; - }; - - pinfunc_uart4: uart4 { - pins_uart4_data: uart4-data { - ingenic,pins = <&gpc 20 2 &pincfg_pull_up /* rxd */ - &gpc 10 2 &pincfg_nobias>; /* txd */ - }; - }; - - pinfunc_msc0: msc0 { - pins_msc0_pa: msc0-pa { - ingenic,pins = <&gpa 4 1 &pincfg_nobias /* d4 */ - &gpa 5 1 &pincfg_nobias /* d5 */ - &gpa 6 1 &pincfg_nobias /* d6 */ - &gpa 7 1 &pincfg_nobias /* d7 */ - &gpa 18 1 &pincfg_nobias /* clk */ - &gpa 19 1 &pincfg_nobias /* cmd */ - &gpa 20 1 &pincfg_nobias /* d0 */ - &gpa 21 1 &pincfg_nobias /* d1 */ - &gpa 22 1 &pincfg_nobias /* d2 */ - &gpa 23 1 &pincfg_nobias /* d3 */ - &gpa 24 1 &pincfg_nobias>; /* rst */ - }; - - pins_msc0_pe: msc0-pe { - ingenic,pins = <&gpe 20 0 &pincfg_nobias /* d0 */ - &gpe 21 0 &pincfg_nobias /* d1 */ - &gpe 22 0 &pincfg_nobias /* d2 */ - &gpe 23 0 &pincfg_nobias /* d3 */ - &gpe 28 0 &pincfg_nobias /* clk */ - &gpe 29 0 &pincfg_nobias>; /* cmd */ - }; - }; - - pinfunc_msc1: msc1 { - pins_msc1_pd: msc1-pd { - ingenic,pins = <&gpd 20 0 &pincfg_nobias /* d0 */ - &gpd 21 0 &pincfg_nobias /* d1 */ - &gpd 22 0 &pincfg_nobias /* d2 */ - &gpd 23 0 &pincfg_nobias /* d3 */ - &gpd 24 0 &pincfg_nobias /* clk */ - &gpd 25 0 &pincfg_nobias>; /* cmd */ - }; - - pins_msc1_pe: msc1-pe { - ingenic,pins = <&gpe 20 1 &pincfg_nobias /* d0 */ - &gpe 21 1 &pincfg_nobias /* d1 */ - &gpe 22 1 &pincfg_nobias /* d2 */ - &gpe 23 1 &pincfg_nobias /* d3 */ - &gpe 28 1 &pincfg_nobias /* clk */ - &gpe 29 1 &pincfg_nobias>; /* cmd */ - }; - }; - - pinfunc_nemc: nemc { - pins_nemc_data: nemc-data { - ingenic,pins = <&gpa 0 0 &pincfg_nobias /* sd0 */ - &gpa 1 0 &pincfg_nobias /* sd1 */ - &gpa 2 0 &pincfg_nobias /* sd2 */ - &gpa 3 0 &pincfg_nobias /* sd3 */ - &gpa 4 0 &pincfg_nobias /* sd4 */ - &gpa 5 0 &pincfg_nobias /* sd5 */ - &gpa 6 0 &pincfg_nobias /* sd6 */ - &gpa 7 0 &pincfg_nobias>; /* sd7 */ - }; - - pins_nemc_cle_ale: nemc-cle-ale { - ingenic,pins = <&gpb 0 0 &pincfg_nobias /* sa0_cl */ - &gpb 1 0 &pincfg_nobias>; /* sa1_al */ - }; - - pins_nemc_addr: nemc-addr { - ingenic,pins = <&gpb 0 0 &pincfg_nobias /* sa0_cl */ - &gpb 1 0 &pincfg_nobias /* sa1_al */ - &gpb 2 0 &pincfg_nobias /* sa2 */ - &gpb 3 0 &pincfg_nobias /* sa3 */ - &gpb 4 0 &pincfg_nobias /* sa4 */ - &gpb 5 0 &pincfg_nobias>; /* sa5 */ - }; - - pins_nemc_rd_we: nemc-rd-we { - ingenic,pins = <&gpa 16 0 &pincfg_nobias /* rd */ - &gpa 17 0 &pincfg_nobias>; /* we */ - }; - - pins_nemc_frd_fwe: nemc-frd-fwe { - ingenic,pins = <&gpa 18 0 &pincfg_nobias /* rd */ - &gpa 19 0 &pincfg_nobias>; /* we */ - }; - - pins_nemc_cs1: nemc-cs1 { - ingenic,pins = <&gpa 21 0 &pincfg_nobias>; /* cs1 */ - }; - - pins_nemc_cs6: nemc-cs6 { - ingenic,pins = <&gpa 26 0 &pincfg_nobias>; /* cs6 */ - }; - }; - - pinfunc_i2c0: i2c0 { - pins_i2c0_data: i2c0-data{ - ingenic,pins = <&gpd 30 0 &pincfg_nobias /* sda */ - &gpd 31 0 &pincfg_nobias>; /* sck */ - }; - }; - - pinfunc_i2c1: i2c1 { - pins_i2c1_data: i2c1-data{ - ingenic,pins = <&gpe 30 0 &pincfg_nobias /* sda */ - &gpe 31 0 &pincfg_nobias>; /* sck */ - }; - }; - - pinfunc_i2c2: i2c2 { - pins_i2c2_data: i2c2-data{ - ingenic,pins = <&gpf 16 2 &pincfg_nobias /* sda */ - &gpf 17 2 &pincfg_nobias>; /* sck */ - }; - }; - - pinfunc_i2c3: i2c3 { - pins_i2c3_data: i2c3-data{ - ingenic,pins = <&gpd 10 1 &pincfg_nobias /* sda */ - &gpd 11 1 &pincfg_nobias>; /* sck */ - }; - }; - - pinfunc_i2c4: i2c4 { - pins_i2c4_data: i2c4-data-pe{ - ingenic,pins = <&gpe 12 1 &pincfg_nobias /* sda */ - &gpe 13 1 &pincfg_nobias>; /* sck */ - }; - - pins_i2c4_data_pf: i2c4-data-pf{ - ingenic,pins = <&gpf 25 1 &pincfg_nobias /* hdmi_sda */ - &gpf 24 1 &pincfg_nobias>; /* hdmi_sck */ - }; - }; - - pinfunc_cim: cim { - pins_cim: cim-pb { - ingenic,pins = <&gpb 6 0 &pincfg_nobias - &gpb 7 0 &pincfg_nobias - &gpb 8 0 &pincfg_nobias - &gpb 9 0 &pincfg_nobias - &gpb 10 0 &pincfg_nobias - &gpb 11 0 &pincfg_nobias - &gpb 12 0 &pincfg_nobias - &gpb 13 0 &pincfg_nobias - &gpb 14 0 &pincfg_nobias - &gpb 15 0 &pincfg_nobias - &gpb 16 0 &pincfg_nobias - &gpb 17 0 &pincfg_nobias>; - }; - }; - }; - - spi_gpio { - compatible = "spi-gpio"; - #address-cells = <1>; - #size-cells = <0>; - num-chipselects = <2>; - - gpio-miso = <&gpe 14 0>; - gpio-sck = <&gpe 15 0>; - gpio-mosi = <&gpe 17 0>; - cs-gpios = <&gpe 16 0 - &gpe 18 0>; - - spidev@0 { - compatible = "spidev"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - }; - - uart0: serial@10030000 { - compatible = "ingenic,jz4780-uart"; - reg = <0x10030000 0x100>; - reg-shift = <2>; - - interrupt-parent = <&intc>; - interrupts = <51>; - - clocks = <&ext>, <&cgu JZ4780_CLK_UART0>; - clock-names = "baud", "module"; - }; - - uart1: serial@10031000 { - compatible = "ingenic,jz4780-uart"; - reg = <0x10031000 0x100>; - reg-shift = <2>; - - interrupt-parent = <&intc>; - interrupts = <50>; - - clocks = <&ext>, <&cgu JZ4780_CLK_UART1>; - clock-names = "baud", "module"; - }; - - uart2: serial@10032000 { - compatible = "ingenic,jz4780-uart"; - reg = <0x10032000 0x100>; - reg-shift = <2>; - - interrupt-parent = <&intc>; - interrupts = <49>; - - clocks = <&ext>, <&cgu JZ4780_CLK_UART2>; - clock-names = "baud", "module"; - }; - - uart3: serial@10033000 { - compatible = "ingenic,jz4780-uart"; - reg = <0x10033000 0x100>; - reg-shift = <2>; - - interrupt-parent = <&intc>; - interrupts = <48>; - - clocks = <&ext>, <&cgu JZ4780_CLK_UART3>; - clock-names = "baud", "module"; - }; - - uart4: serial@10034000 { - compatible = "ingenic,jz4780-uart"; - reg = <0x10034000 0x100>; - reg-shift = <2>; - - interrupt-parent = <&intc>; - interrupts = <34>; - - clocks = <&ext>, <&cgu JZ4780_CLK_UART4>; - clock-names = "baud", "module"; - }; - - i2c0: i2c0@0x10050000 { - compatible = "ingenic,jz4780-i2c"; - reg = <0x10050000 0x1000>; - - interrupt-parent = <&intc>; - interrupts = <60>; - - clocks = <&cgu JZ4780_CLK_SMB0>; - - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c1: i2c1@0x10051000 { - compatible = "ingenic,jz4780-i2c"; - reg = <0x10051000 0x1000>; - - interrupt-parent = <&intc>; - interrupts = <59>; - - clocks = <&cgu JZ4780_CLK_SMB1>; - - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c2: i2c2@0x10052000 { - compatible = "ingenic,jz4780-i2c"; - reg = <0x10052000 0x1000>; - - interrupt-parent = <&intc>; - interrupts = <58>; - - clocks = <&cgu JZ4780_CLK_SMB2>; - - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c3: i2c3@0x10053000 { - compatible = "ingenic,jz4780-i2c"; - reg = <0x10053000 0x1000>; - - interrupt-parent = <&intc>; - interrupts = <57>; - - clocks = <&cgu JZ4780_CLK_SMB3>; - - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c4: i2c4@0x10054000 { - compatible = "ingenic,jz4780-i2c"; - reg = <0x10054000 0x1000>; - - interrupt-parent = <&intc>; - interrupts = <56>; - - clocks = <&cgu JZ4780_CLK_SMB4>; - - #address-cells = <1>; - #size-cells = <0>; - }; - - lpcr: lcr@0x10000004 { - compatible = "ingenic,jz4780-lcr"; - reg = <0x10000004 0x4>; - - regulators { - vpu_power: VPU { - }; - gpu_power: GPU { - }; - gps_power: GPS { - }; - }; - }; - - adc@0x10070000 { - compatible = "ingenic,jz4780-adc"; - reg = <0x10070000 0x30>; - - interrupt-parent = <&intc>; - interrupts = <18>; - - clocks = <&cgu JZ4780_CLK_SADC>; - clock-names = "adc"; - }; - }; - - ahb2 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <>; - - - lcd: jz4780-lcdk@0x13050000 { - compatible = "ingenic,jz4780-lcd"; - reg = <0x13050000 0x1800>; - - clocks = <&cgu JZ4780_CLK_TVE>, <&cgu JZ4780_CLK_LCD0PIXCLK>; - clock-names = "lcd_clk", "lcd_pixclk"; - - interrupt-parent = <&intc>; - interrupts = <31>; - - hdmi = <&hdmi>; - ddc = <&i2c4>; - }; - - cim: jz4780-cim@0x13060000 { - compatible = "ingenic,jz4780-cim"; - reg = <0x13060000 0x68>; - reg-shift = <2>; - - interrupt-parent = <&intc>; - interrupts = <30>; - - pinctrl-names = "default"; - pinctrl-0 = <&pins_cim>; - - clocks = <&cgu JZ4780_CLK_CIM>, <&cgu JZ4780_CLK_CIMMCLK>; - clock-names = "cim", "module"; - }; - - hdmi: jz4780-hdmi3@0x10180000 { - compatible = "synopsys,dwc-hdmi"; - reg = <0x10180000 0x8000>; - reg-shift = <2>; - - clocks = <&cgu JZ4780_CLK_HDMI>, <&cgu JZ4780_CLK_AHB0>; - clock-names = "hdmi" , "ahb"; - - clock-frequency = <27000000>; - - interrupt-parent = <&intc>; - interrupts = <3>; - - ddc = <&i2c4>; - }; - - - nemc: nemc@13410000 { - compatible = "ingenic,jz4780-nemc"; - reg = <0x13410000 0x10000>; - #address-cells = <2>; - #size-cells = <1>; - ranges = <1 0 0x1b000000 0x1000000 - 2 0 0x1a000000 0x1000000 - 3 0 0x19000000 0x1000000 - 4 0 0x18000000 0x1000000 - 5 0 0x17000000 0x1000000 - 6 0 0x16000000 0x1000000>; - - clocks = <&cgu JZ4780_CLK_NEMC>; - }; - - efuse: efuse@134100D0 { - compatible = "ingenic,jz4780-efuse"; - reg = <0x134100D0 0xFF>; - - clocks = <&cgu JZ4780_CLK_AHB2>; - clock-names = "bus_clk"; - }; - - dma: dma@13420000 { - compatible = "ingenic,jz4780-dma"; - reg = <0x13420000 0x10000>; - - interrupt-parent = <&intc>; - interrupts = <10>; - - clocks = <&cgu JZ4780_CLK_PDMA>; - - #dma-cells = <3>; - }; - - msc0: msc@13450000 { - compatible = "ingenic,jz4780-mmc"; - reg = <0x13450000 0x1000>; - - interrupt-parent = <&intc>; - interrupts = <37>; - - clocks = <&cgu JZ4780_CLK_MSC0>; - clock-names = "mmc"; - - cap-sd-highspeed; - cap-mmc-highspeed; - cap-sdio-irq; - - dmas = <&dma JZ4780_DMA_MSC0_TX JZ4780_DMA_MSC0_RX 0xffffffff>; - dma-names = "rx-tx"; - }; - - msc1: msc@13460000 { - compatible = "ingenic,jz4780-mmc"; - reg = <0x13460000 0x1000>; - - status = "disabled"; - - interrupt-parent = <&intc>; - interrupts = <36>; - - clocks = <&cgu JZ4780_CLK_MSC1>; - clock-names = "mmc"; - - cap-sd-highspeed; - cap-mmc-highspeed; - cap-sdio-irq; - - dmas = <&dma JZ4780_DMA_MSC1_TX JZ4780_DMA_MSC1_RX 0xffffffff>; - dma-names = "rx-tx"; - }; - - ehci: jz4780-ehci@0x13490000 { - compatible = "ingenic,jz4780-ehci"; - reg = <0x13490000 0x10000>; - - interrupt-parent = <&intc>; - interrupts = <20>; - - clocks = <&cgu JZ4780_CLK_UHC>; - }; - - ohci: jz4780-ohci@0x134a0000 { - compatible = "ingenic,jz4780-ohci"; - reg = <0x134a0000 0x10000>; - - interrupt-parent = <&intc>; - interrupts = <5>; - - clocks = <&cgu JZ4780_CLK_UHC>; - clock-names = "uhc"; - }; - - bch: bch@134d0000 { - compatible = "ingenic,jz4780-bch"; - reg = <0x134d0000 0x10000>; - - clocks = <&cgu JZ4780_CLK_BCH>; - }; - - otg: jz4780-otg@0x13500000 { - compatible = "ingenic,jz4780-otg"; - reg = <0x13500000 0x40000>; - - interrupt-parent = <&intc>; - interrupts = <21>; - - clocks = <&cgu JZ4780_CLK_OTGPHY>, <&cgu JZ4780_CLK_OTG1>; - clock-names = "otg_phy", "otg1"; - }; - }; -}; diff --git a/sys/gnu/dts/mips/ingenic/x1000.dtsi b/sys/gnu/dts/mips/ingenic/x1000.dtsi deleted file mode 100644 index dd0105e04e5..00000000000 --- a/sys/gnu/dts/mips/ingenic/x1000.dtsi +++ /dev/null @@ -1,420 +0,0 @@ -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - compatible = "ingenic,x1000"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "ingenic,xburst"; - reg = <0>; - }; - }; - - cpuintc: cpuintc@0 { - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - compatible = "mti,cpu-interrupt-controller"; - }; - - intc: intc@10001000 { - compatible = "ingenic,jz4780-intc"; - reg = <0x10001000 0x50>; - - interrupt-controller; - #interrupt-cells = <1>; - - interrupt-parent = <&cpuintc>; - interrupts = <2>; - }; - - ext: ext { - compatible = "fixed-clock"; - #clock-cells = <0>; - }; - - rtc: rtc { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - - cgu: jz4780-cgu@10000000 { - compatible = "ingenic,jz4780-cgu"; - reg = <0x10000000 0x100>; - - clocks = <&ext>, <&rtc>; - clock-names = "ext", "rtc"; - - #clock-cells = <1>; - }; - - apb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <>; - - tcu@0x10002000 { - compatible = "ingenic,jz4780-tcu"; - reg = <0x10002000 0x140>; - - interrupt-parent = <&intc>; - interrupts = <27 26 25>; - }; - - watchdog: jz47xx-watchdog@0x10002000 { - compatible = "ingenic,jz4780-watchdog"; - reg = <0x10002000 0x100>; - - clocks = <&rtc>; - clock-names = "rtc"; - }; - - rtcdev: rtcdev@10003000 { - compatible = "ingenic,jz4780-rtc"; - reg = <0x10003000 0x4c>; - interrupt-parent = <&intc>; - interrupts = <32>; - }; - - i2s: i2s@10020000 { - compatible = "ingenic,jz4780-i2s"; - reg = <0x10020000 0x94>; - - clocks = <&cgu JZ4780_CLK_AIC>, <&cgu JZ4780_CLK_I2SPLL>; - clock-names = "aic", "i2s"; - - dmas = <&dma 0 JZ4780_DMA_I2S0_RX 0xffffffff>, <&dma JZ4780_DMA_I2S0_TX 0 0xffffffff>; - dma-names = "rx" , "tx"; - - }; - - codec: codec@100200a4 { - compatible = "ingenic,jz4780-codec"; - reg = <0x100200a4 0x8>; - - clocks = <&cgu JZ4780_CLK_I2SPLL>; - clock-names = "i2s"; - - }; - - pinctrl@0x10010000 { - compatible = "ingenic,jz4780-pinctrl"; - reg = <0x10010000 0x600>; - - gpa: gpa { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - - interrupt-parent = <&intc>; - interrupts = <17>; - - ingenic,pull-ups = <0x3fffffff>; - }; - - gpb: gpb { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - - interrupt-parent = <&intc>; - interrupts = <16>; - - ingenic,pull-downs = <0x000f0c03>; - ingenic,pull-ups = <0xfff0030c>; - }; - - gpc: gpc { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - - interrupt-parent = <&intc>; - interrupts = <15>; - - ingenic,pull-ups = <0xffffffff>; - }; - - gpd: gpd { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - - interrupt-parent = <&intc>; - interrupts = <14>; - - ingenic,pull-downs = <0x0000b000>; - ingenic,pull-ups = <0xffff4fff>; - }; - - pincfg_nobias: nobias { - bias-disable; - }; - - pincfg_pull_up: pull_up { - bias-pull-up; - }; - - pincfg_pull_down: pull_down { - bias-pull-down; - }; - - pinfunc_uart2: uart2 { - pins_uart2_data: uart2-data { - ingenic,pins = <&gpd 6 1 &pincfg_nobias /* rxd */ - &gpd 7 1 &pincfg_nobias>; /* txd */ - }; - - pins_uart2_dataplusflow: uart2-dataplusflow { - ingenic,pins = <&gpd 6 1 &pincfg_nobias /* rxd */ - &gpd 5 1 &pincfg_nobias /* cts */ - &gpd 4 1 &pincfg_nobias /* rts */ - &gpd 7 1 &pincfg_nobias>; /* txd */ - }; - }; - - pinfunc_msc0: msc0 { - pins_msc0_pa: msc0-pa { - ingenic,pins = <&gpa 16 1 &pincfg_nobias /* d7 */ - &gpa 17 1 &pincfg_nobias /* d6 */ - &gpa 18 1 &pincfg_nobias /* d5 */ - &gpa 19 1 &pincfg_nobias /* d4 */ - &gpa 20 1 &pincfg_nobias /* d3 */ - &gpa 21 1 &pincfg_nobias /* d2 */ - &gpa 22 1 &pincfg_nobias /* d1 */ - &gpa 23 1 &pincfg_nobias /* d0 */ - &gpa 24 1 &pincfg_nobias /* clk */ - &gpa 25 1 &pincfg_nobias>; /* cmd */ - }; - }; - - pinfunc_cim: cim { - pins_cim: cim-pb { - ingenic,pins = < /* Fill me. */ >; - }; - }; - }; - - uart0: serial@10030000 { - compatible = "ingenic,jz4780-uart"; - reg = <0x10030000 0x100>; - reg-shift = <2>; - - interrupt-parent = <&intc>; - interrupts = <51>; - status = "disabled"; - - clocks = <&ext>, <&cgu JZ4780_CLK_UART0>; - clock-names = "baud", "module"; - }; - - uart1: serial@10031000 { - compatible = "ingenic,jz4780-uart"; - reg = <0x10031000 0x100>; - reg-shift = <2>; - - interrupt-parent = <&intc>; - interrupts = <50>; - status = "disabled"; - - clocks = <&ext>, <&cgu JZ4780_CLK_UART1>; - clock-names = "baud", "module"; - }; - - uart2: serial@10032000 { - compatible = "ingenic,jz4780-uart"; - reg = <0x10032000 0x100>; - reg-shift = <2>; - - interrupt-parent = <&intc>; - interrupts = <49>; - - clocks = <&ext>, <&cgu JZ4780_CLK_UART2>; - clock-names = "baud", "module"; - }; - - uart3: serial@10033000 { - compatible = "ingenic,jz4780-uart"; - reg = <0x10033000 0x100>; - reg-shift = <2>; - - interrupt-parent = <&intc>; - interrupts = <48>; - status = "disabled"; - - clocks = <&ext>, <&cgu JZ4780_CLK_UART3>; - clock-names = "baud", "module"; - }; - - i2c0: i2c0@0x10050000 { - compatible = "ingenic,jz4780-i2c"; - reg = <0x10050000 0x1000>; - - interrupt-parent = <&intc>; - interrupts = <60>; - - clocks = <&cgu JZ4780_CLK_SMB0>; - - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c1: i2c1@0x10051000 { - compatible = "ingenic,jz4780-i2c"; - reg = <0x10051000 0x1000>; - - interrupt-parent = <&intc>; - interrupts = <59>; - - clocks = <&cgu JZ4780_CLK_SMB1>; - - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c2: i2c2@0x10052000 { - compatible = "ingenic,jz4780-i2c"; - reg = <0x10052000 0x1000>; - - interrupt-parent = <&intc>; - interrupts = <58>; - - clocks = <&cgu JZ4780_CLK_SMB2>; - - #address-cells = <1>; - #size-cells = <0>; - }; - - lpcr: lcr@0x10000004 { - compatible = "ingenic,jz4780-lcr"; - reg = <0x10000004 0x4>; - - regulators { - vpu_power: VPU { - }; - gpu_power: GPU { - }; - gps_power: GPS { - }; - }; - }; - }; - - ahb2 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <>; - - lcd: jz4780-lcdk@0x13050000 { - compatible = "ingenic,jz4780-lcd"; - reg = <0x13050000 0x1800>; - - clocks = <&cgu JZ4780_CLK_TVE>, <&cgu JZ4780_CLK_LCD0PIXCLK>; - clock-names = "lcd_clk", "lcd_pixclk"; - - interrupt-parent = <&intc>; - interrupts = <31>; - }; - - cim: jz4780-cim@0x13060000 { - compatible = "ingenic,jz4780-cim"; - reg = <0x13060000 0x68>; - reg-shift = <2>; - - interrupt-parent = <&intc>; - interrupts = <30>; - - pinctrl-names = "default"; - pinctrl-0 = <&pins_cim>; - - clocks = <&cgu JZ4780_CLK_CIM>, <&cgu JZ4780_CLK_CIMMCLK>; - clock-names = "cim", "module"; - }; - - efuse: efuse@13540000 { - compatible = "ingenic,jz4780-efuse"; - reg = <0x13540000 0xFF>; - - clocks = <&cgu JZ4780_CLK_AHB2>; - clock-names = "bus_clk"; - }; - - dma: dma@13420000 { - compatible = "ingenic,jz4780-dma"; - reg = <0x13420000 0x10000>; - - interrupt-parent = <&intc>; - interrupts = <10>; - - clocks = <&cgu JZ4780_CLK_PDMA>; - - #dma-cells = <3>; - }; - - msc0: msc@13450000 { - compatible = "ingenic,jz4780-mmc"; - reg = <0x13450000 0x1000>; - - interrupt-parent = <&intc>; - interrupts = <37>; - - clocks = <&cgu JZ4780_CLK_MSC0>; - clock-names = "mmc"; - - cap-sd-highspeed; - cap-mmc-highspeed; - cap-sdio-irq; - - dmas = <&dma JZ4780_DMA_MSC0_TX JZ4780_DMA_MSC0_RX 0xffffffff>; - dma-names = "rx-tx"; - }; - - msc1: msc@13460000 { - compatible = "ingenic,jz4780-mmc"; - reg = <0x13460000 0x1000>; - - status = "disabled"; - - interrupt-parent = <&intc>; - interrupts = <36>; - - clocks = <&cgu JZ4780_CLK_MSC1>; - clock-names = "mmc"; - - cap-sd-highspeed; - cap-mmc-highspeed; - cap-sdio-irq; - - dmas = <&dma JZ4780_DMA_MSC1_TX JZ4780_DMA_MSC1_RX 0xffffffff>; - dma-names = "rx-tx"; - }; - - otg: jz4780-otg@0x13500000 { - compatible = "ingenic,jz4780-otg"; - reg = <0x13500000 0x40000>; - - interrupt-parent = <&intc>; - interrupts = <21>; - - clocks = <&cgu JZ4780_CLK_OTGPHY>, <&cgu JZ4780_CLK_OTG1>; - clock-names = "otg_phy", "otg1"; - }; - }; -}; diff --git a/sys/gnu/dts/mips/mt7620a.dtsi b/sys/gnu/dts/mips/mt7620a.dtsi deleted file mode 100644 index 570eb5aefff..00000000000 --- a/sys/gnu/dts/mips/mt7620a.dtsi +++ /dev/null @@ -1,550 +0,0 @@ -/ { - #address-cells = <1>; - #size-cells = <1>; - compatible = "ralink,mtk7620a-soc"; - - cpus { - cpu@0 { - compatible = "mips,mips24KEc"; - }; - }; - - chosen { - bootargs = "console=ttyS0,57600"; - }; - - cpuintc: cpuintc@0 { - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - compatible = "mti,cpu-interrupt-controller"; - }; - - aliases { - spi0 = &spi0; - spi1 = &spi1; - serial0 = &uartlite; - }; - - palmbus: palmbus@10000000 { - compatible = "palmbus"; - reg = <0x10000000 0x200000>; - ranges = <0x0 0x10000000 0x1FFFFF>; - - #address-cells = <1>; - #size-cells = <1>; - - sysc: sysc@0 { - compatible = "ralink,mt7620a-sysc", "ralink,rt3050-sysc"; - reg = <0x0 0x100>; - }; - - timer: timer@100 { - compatible = "ralink,mt7620a-timer", "ralink,rt2880-timer"; - reg = <0x100 0x20>; - - interrupt-parent = <&intc>; - interrupts = <1>; - }; - - watchdog: watchdog@120 { - compatible = "ralink,mt7620a-wdt", "ralink,rt2880-wdt"; - reg = <0x120 0x10>; - - resets = <&rstctrl 8>; - reset-names = "wdt"; - - interrupt-parent = <&intc>; - interrupts = <1>; - }; - - intc: intc@200 { - compatible = "ralink,mt7620a-intc", "ralink,rt2880-intc"; - reg = <0x200 0x100>; - - resets = <&rstctrl 19>; - reset-names = "intc"; - - interrupt-controller; - #interrupt-cells = <1>; - - interrupt-parent = <&cpuintc>; - interrupts = <2>; - }; - - memc: memc@300 { - compatible = "ralink,mt7620a-memc", "ralink,rt3050-memc"; - reg = <0x300 0x100>; - - resets = <&rstctrl 20>; - reset-names = "mc"; - - interrupt-parent = <&intc>; - interrupts = <3>; - }; - - uart: uart@500 { - compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a"; - reg = <0x500 0x100>; - - resets = <&rstctrl 12>; - reset-names = "uart"; - - interrupt-parent = <&intc>; - interrupts = <5>; - - reg-shift = <2>; - - status = "disabled"; - }; - - gpio0: gpio@600 { - compatible = "ralink,mt7620a-gpio", "ralink,rt2880-gpio"; - reg = <0x600 0x34>; - - resets = <&rstctrl 13>; - reset-names = "pio"; - - interrupt-parent = <&intc>; - interrupts = <6>; - - gpio-controller; - #gpio-cells = <2>; - - ralink,gpio-base = <0>; - ralink,num-gpios = <24>; - ralink,register-map = [ 00 04 08 0c - 20 24 28 2c - 30 34 ]; - }; - - gpio1: gpio@638 { - compatible = "ralink,mt7620a-gpio", "ralink,rt2880-gpio"; - reg = <0x638 0x24>; - - interrupt-parent = <&intc>; - interrupts = <6>; - - gpio-controller; - #gpio-cells = <2>; - - ralink,gpio-base = <24>; - ralink,num-gpios = <16>; - ralink,register-map = [ 00 04 08 0c - 10 14 18 1c - 20 24 ]; - - status = "disabled"; - }; - - gpio2: gpio@660 { - compatible = "ralink,mt7620a-gpio", "ralink,rt2880-gpio"; - reg = <0x660 0x24>; - - interrupt-parent = <&intc>; - interrupts = <6>; - - gpio-controller; - #gpio-cells = <2>; - - ralink,gpio-base = <40>; - ralink,num-gpios = <32>; - ralink,register-map = [ 00 04 08 0c - 10 14 18 1c - 20 24 ]; - - status = "disabled"; - }; - - gpio3: gpio@688 { - compatible = "ralink,mt7620a-gpio", "ralink,rt2880-gpio"; - reg = <0x688 0x24>; - - interrupt-parent = <&intc>; - interrupts = <6>; - - gpio-controller; - #gpio-cells = <2>; - - ralink,gpio-base = <72>; - ralink,num-gpios = <1>; - ralink,register-map = [ 00 04 08 0c - 10 14 18 1c - 20 24 ]; - - status = "disabled"; - }; - - i2c: i2c@900 { - compatible = "link,mt7620a-i2c", "ralink,rt2880-i2c"; - reg = <0x900 0x100>; - - resets = <&rstctrl 16>; - reset-names = "i2c"; - - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - - pinctrl-names = "default"; - pinctrl-0 = <&i2c_pins>; - }; - - i2s: i2s@a00 { - compatible = "ralink,mt7620a-i2s"; - reg = <0xa00 0x100>; - - resets = <&rstctrl 17>; - reset-names = "i2s"; - - interrupt-parent = <&intc>; - interrupts = <10>; - - dmas = <&gdma 4>, - <&gdma 5>; - dma-names = "tx", "rx"; - - status = "disabled"; - }; - - spi0: spi@b00 { - compatible = "ralink,mt7620a-spi", "ralink,rt2880-spi"; - reg = <0xb00 0x40>; - - resets = <&rstctrl 18>; - reset-names = "spi"; - - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - - pinctrl-names = "default"; - pinctrl-0 = <&spi_pins>; - }; - - spi1: spi@b40 { - compatible = "ralink,rt2880-spi"; - reg = <0xb40 0x60>; - - resets = <&rstctrl 18>; - reset-names = "spi"; - - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - - pinctrl-names = "default"; - pinctrl-0 = <&spi_cs1>; - }; - - uartlite: uartlite@c00 { - compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a"; - reg = <0xc00 0x100>; - - resets = <&rstctrl 19>; - reset-names = "uartl"; - - interrupt-parent = <&intc>; - interrupts = <12>; - - reg-shift = <2>; - - pinctrl-names = "default"; - pinctrl-0 = <&uartlite_pins>; - }; - - systick: systick@d00 { - compatible = "ralink,mt7620a-systick", "ralink,cevt-systick"; - reg = <0xd00 0x10>; - - resets = <&rstctrl 28>; - reset-names = "intc"; - - interrupt-parent = <&cpuintc>; - interrupts = <7>; - }; - - pcm: pcm@2000 { - compatible = "ralink,mt7620a-pcm"; - reg = <0x2000 0x800>; - - resets = <&rstctrl 11>; - reset-names = "pcm"; - - interrupt-parent = <&intc>; - interrupts = <4>; - - status = "disabled"; - }; - - gdma: gdma@2800 { - compatible = "ralink,mt7620a-gdma", "ralink,rt2880-gdma"; - reg = <0x2800 0x800>; - - resets = <&rstctrl 14>; - reset-names = "dma"; - - interrupt-parent = <&intc>; - interrupts = <7>; - - #dma-cells = <1>; - #dma-channels = <16>; - #dma-requests = <16>; - - status = "disabled"; - }; - }; - - pinctrl: pinctrl { - compatible = "ralink,rt2880-pinmux"; - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinctrl0 { - }; - - pcm_i2s_pins: pcm_i2s { - pcm_i2s { - ralink,group = "uartf"; - ralink,function = "pcm i2s"; - }; - }; - - uartf_gpio_pins: uartf_gpio { - uartf_gpio { - ralink,group = "uartf"; - ralink,function = "gpio uartf"; - }; - }; - - spi_pins: spi { - spi { - ralink,group = "spi"; - ralink,function = "spi"; - }; - }; - - spi_cs1: spi1 { - spi1 { - ralink,group = "spi_cs1"; - ralink,function = "spi_cs1"; - }; - }; - - i2c_pins: i2c { - i2c { - ralink,group = "i2c"; - ralink,function = "i2c"; - }; - }; - - uartlite_pins: uartlite { - uart { - ralink,group = "uartlite"; - ralink,function = "uartlite"; - }; - }; - - mdio_pins: mdio { - mdio { - ralink,group = "mdio"; - ralink,function = "mdio"; - }; - }; - - ephy_pins: ephy { - ephy { - ralink,group = "ephy"; - ralink,function = "ephy"; - }; - }; - - wled_pins: wled { - wled { - ralink,group = "wled"; - ralink,function = "wled"; - }; - }; - - rgmii1_pins: rgmii1 { - rgmii1 { - ralink,group = "rgmii1"; - ralink,function = "rgmii1"; - }; - }; - - rgmii2_pins: rgmii2 { - rgmii2 { - ralink,group = "rgmii2"; - ralink,function = "rgmii2"; - }; - }; - - pcie_pins: pcie { - pcie { - ralink,group = "pcie"; - ralink,function = "pcie rst"; - }; - }; - }; - - rstctrl: rstctrl { - compatible = "ralink,mt7620a-reset", "ralink,rt2880-reset"; - #reset-cells = <1>; - }; - - clkctrl: clkctrl { - compatible = "ralink,rt2880-clock"; - #clock-cells = <1>; - }; - - usbphy: usbphy { - compatible = "mediatek,mt7620-usbphy"; - #phy-cells = <1>; - - resets = <&rstctrl 22 &rstctrl 25>; - reset-names = "host", "device"; - - clocks = <&clkctrl 22 &clkctrl 25>; - clock-names = "host", "device"; - }; - - ethernet: ethernet@10100000 { - compatible = "mediatek,mt7620-eth"; - reg = <0x10100000 0x10000>; - - #address-cells = <1>; - #size-cells = <0>; - - interrupt-parent = <&cpuintc>; - interrupts = <5>; - - resets = <&rstctrl 21 &rstctrl 23>; - reset-names = "fe", "esw"; - - mediatek,switch = <&gsw>; - - port@4 { - compatible = "mediatek,mt7620a-gsw-port", "mediatek,eth-port"; - reg = <4>; - - status = "disabled"; - }; - - port@5 { - compatible = "mediatek,mt7620a-gsw-port", "mediatek,eth-port"; - reg = <5>; - - status = "disabled"; - }; - - mdio-bus { - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - }; - - gsw: gsw@10110000 { - compatible = "mediatek,mt7620-gsw"; - reg = <0x10110000 0x8000>; - - resets = <&rstctrl 23>; - reset-names = "esw"; - - interrupt-parent = <&intc>; - interrupts = <17>; - }; - - sdhci: sdhci@10130000 { - compatible = "ralink,mt7620-sdhci"; - reg = <0x10130000 0x4000>; - - interrupt-parent = <&intc>; - interrupts = <14>; - - status = "disabled"; - }; - - ehci: ehci@101c0000 { - compatible = "generic-ehci"; - reg = <0x101c0000 0x1000>; - - interrupt-parent = <&intc>; - interrupts = <18>; - - phys = <&usbphy 1>; - phy-names = "usb"; - - status = "disabled"; - }; - - ohci: ohci@101c1000 { - compatible = "generic-ohci"; - reg = <0x101c1000 0x1000>; - - interrupt-parent = <&intc>; - interrupts = <18>; - - phys = <&usbphy 1>; - phy-names = "usb"; - - status = "disabled"; - }; - - pcie: pcie@10140000 { - compatible = "mediatek,mt7620-pci"; - reg = <0x10140000 0x100 - 0x10142000 0x100>; - - #address-cells = <3>; - #size-cells = <2>; - - resets = <&rstctrl 26>; - reset-names = "pcie0"; - - clocks = <&clkctrl 26>; - clock-names = "pcie0"; - - interrupt-parent = <&cpuintc>; - interrupts = <4>; - - pinctrl-names = "default"; - pinctrl-0 = <&pcie_pins>; - - device_type = "pci"; - - bus-range = <0 255>; - ranges = < - 0x02000000 0 0x00000000 0x20000000 0 0x10000000 /* pci memory */ - 0x01000000 0 0x00000000 0x10160000 0 0x00010000 /* io space */ - >; - - status = "disabled"; - - pcie-bridge { - reg = <0x0000 0 0 0 0>; - - #address-cells = <3>; - #size-cells = <2>; - - device_type = "pci"; - }; - }; - - wmac: wmac@10180000 { - compatible = "ralink,rt7620-wmac", "ralink,rt2880-wmac"; - reg = <0x10180000 0x40000>; - - interrupt-parent = <&cpuintc>; - interrupts = <6>; - - ralink,eeprom = "soc_wmac.eeprom"; - }; -}; - -#include "fbsd-mt7620a.dtsi" diff --git a/sys/gnu/dts/mips/mt7620n.dtsi b/sys/gnu/dts/mips/mt7620n.dtsi deleted file mode 100644 index f1593acd93b..00000000000 --- a/sys/gnu/dts/mips/mt7620n.dtsi +++ /dev/null @@ -1,344 +0,0 @@ -/ { - #address-cells = <1>; - #size-cells = <1>; - compatible = "ralink,mtk7620n-soc"; - - cpus { - cpu@0 { - compatible = "mips,mips24KEc"; - }; - }; - - chosen { - bootargs = "console=ttyS0,57600"; - }; - - cpuintc: cpuintc@0 { - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - compatible = "mti,cpu-interrupt-controller"; - }; - - aliases { - spi0 = &spi0; - spi1 = &spi1; - serial0 = &uartlite; - }; - - palmbus: palmbus@10000000 { - compatible = "palmbus"; - reg = <0x10000000 0x200000>; - ranges = <0x0 0x10000000 0x1FFFFF>; - - #address-cells = <1>; - #size-cells = <1>; - - sysc: sysc@0 { - compatible = "ralink,mt7620a-sysc", "ralink,rt3050-sysc"; - reg = <0x0 0x100>; - }; - - timer: timer@100 { - compatible = "ralink,mt7620a-timer", "ralink,rt2880-timer"; - reg = <0x100 0x20>; - - interrupt-parent = <&intc>; - interrupts = <1>; - }; - - watchdog: watchdog@120 { - compatible = "ralink,mt7620a-wdt", "ralink,rt2880-wdt"; - reg = <0x120 0x10>; - - resets = <&rstctrl 8>; - reset-names = "wdt"; - - interrupt-parent = <&intc>; - interrupts = <1>; - }; - - intc: intc@200 { - compatible = "ralink,mt7620a-intc", "ralink,rt2880-intc"; - reg = <0x200 0x100>; - - resets = <&rstctrl 19>; - reset-names = "intc"; - - interrupt-controller; - #interrupt-cells = <1>; - - interrupt-parent = <&cpuintc>; - interrupts = <2>; - }; - - memc: memc@300 { - compatible = "ralink,mt7620a-memc", "ralink,rt3050-memc"; - reg = <0x300 0x100>; - - resets = <&rstctrl 20>; - reset-names = "mc"; - - interrupt-parent = <&intc>; - interrupts = <3>; - }; - - gpio0: gpio@600 { - compatible = "ralink,mt7620a-gpio", "ralink,rt2880-gpio"; - reg = <0x600 0x34>; - - resets = <&rstctrl 13>; - reset-names = "pio"; - - interrupt-parent = <&intc>; - interrupts = <6>; - - gpio-controller; - #gpio-cells = <2>; - - ralink,gpio-base = <0>; - ralink,num-gpios = <24>; - ralink,register-map = [ 00 04 08 0c - 20 24 28 2c - 30 34 ]; - }; - - gpio1: gpio@638 { - compatible = "ralink,mt7620a-gpio", "ralink,rt2880-gpio"; - reg = <0x638 0x24>; - - interrupt-parent = <&intc>; - interrupts = <6>; - - gpio-controller; - #gpio-cells = <2>; - - ralink,gpio-base = <24>; - ralink,num-gpios = <16>; - ralink,register-map = [ 00 04 08 0c - 10 14 18 1c - 20 24 ]; - - status = "disabled"; - }; - - gpio2: gpio@660 { - compatible = "ralink,mt7620a-gpio", "ralink,rt2880-gpio"; - reg = <0x660 0x24>; - - interrupt-parent = <&intc>; - interrupts = <6>; - - gpio-controller; - #gpio-cells = <2>; - - ralink,gpio-base = <40>; - ralink,num-gpios = <32>; - ralink,register-map = [ 00 04 08 0c - 10 14 18 1c - 20 24 ]; - - status = "disabled"; - }; - - gpio3: gpio@688 { - compatible = "ralink,mt7620a-gpio", "ralink,rt2880-gpio"; - reg = <0x688 0x24>; - - interrupt-parent = <&intc>; - interrupts = <6>; - - gpio-controller; - #gpio-cells = <2>; - - ralink,gpio-base = <72>; - ralink,num-gpios = <1>; - ralink,register-map = [ 00 04 08 0c - 10 14 18 1c - 20 24 ]; - - status = "disabled"; - }; - - spi0: spi@b00 { - compatible = "ralink,mt7620a-spi", "ralink,rt2880-spi"; - reg = <0xb00 0x40>; - - resets = <&rstctrl 18>; - reset-names = "spi"; - - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - - pinctrl-names = "default"; - pinctrl-0 = <&spi_pins>; - }; - - spi1: spi@b40 { - compatible = "ralink,rt2880-spi"; - reg = <0xb40 0x60>; - - resets = <&rstctrl 18>; - reset-names = "spi"; - - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - - pinctrl-names = "default"; - pinctrl-0 = <&spi_cs1>; - }; - - uartlite: uartlite@c00 { - compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a"; - reg = <0xc00 0x100>; - - resets = <&rstctrl 19>; - reset-names = "uartl"; - - interrupt-parent = <&intc>; - interrupts = <12>; - - reg-shift = <2>; - - pinctrl-names = "default"; - pinctrl-0 = <&uartlite_pins>; - }; - - systick: systick@d00 { - compatible = "ralink,mt7620a-systick", "ralink,cevt-systick"; - reg = <0xd00 0x10>; - - resets = <&rstctrl 28>; - reset-names = "intc"; - - interrupt-parent = <&cpuintc>; - interrupts = <7>; - }; - }; - - pinctrl: pinctrl { - compatible = "ralink,rt2880-pinmux"; - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinctrl0 { - }; - - spi_pins: spi { - spi { - ralink,group = "spi"; - ralink,function = "spi"; - }; - }; - - spi_cs1: spi1 { - spi1 { - ralink,group = "spi_cs1"; - ralink,function = "spi_cs1"; - }; - }; - - uartlite_pins: uartlite { - uart { - ralink,group = "uartlite"; - ralink,function = "uartlite"; - }; - }; - }; - - rstctrl: rstctrl { - compatible = "ralink,mt7620a-reset", "ralink,rt2880-reset"; - #reset-cells = <1>; - }; - - clkctrl: clkctrl { - compatible = "ralink,rt2880-clock"; - #clock-cells = <1>; - }; - - usbphy: usbphy { - compatible = "mediatek,mt7620-usbphy"; - #phy-cells = <1>; - - resets = <&rstctrl 22 &rstctrl 25>; - reset-names = "host", "device"; - - clocks = <&clkctrl 22 &clkctrl 25>; - clock-names = "host", "device"; - }; - - ethernet: ethernet@10100000 { - compatible = "mediatek,mt7620-eth"; - reg = <0x10100000 0x10000>; - - #address-cells = <1>; - #size-cells = <0>; - - interrupt-parent = <&cpuintc>; - interrupts = <5>; - - resets = <&rstctrl 21 &rstctrl 23>; - reset-names = "fe", "esw"; - - mediatek,switch = <&gsw>; - - mdio-bus { - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - }; - - gsw: gsw@10110000 { - compatible = "mediatek,mt7620-gsw"; - reg = <0x10110000 0x8000>; - - resets = <&rstctrl 23>; - reset-names = "esw"; - - interrupt-parent = <&intc>; - interrupts = <17>; - mediatek,port4 = "gmac"; - }; - - ehci: ehci@101c0000 { - compatible = "generic-ehci"; - reg = <0x101c0000 0x1000>; - - interrupt-parent = <&intc>; - interrupts = <18>; - - phys = <&usbphy 1>; - phy-names = "usb"; - - status = "disabled"; - }; - - ohci: ohci@101c1000 { - compatible = "generic-ohci"; - reg = <0x101c1000 0x1000>; - - phys = <&usbphy 1>; - phy-names = "usb"; - - interrupt-parent = <&intc>; - interrupts = <18>; - - status = "disabled"; - }; - - wmac: wmac@10180000 { - compatible = "ralink,rt7620-wmac", "ralink,rt2880-wmac"; - reg = <0x10180000 0x40000>; - - interrupt-parent = <&cpuintc>; - interrupts = <6>; - - ralink,eeprom = "soc_wmac.eeprom"; - }; -}; diff --git a/sys/gnu/dts/mips/mt7621.dtsi b/sys/gnu/dts/mips/mt7621.dtsi deleted file mode 100644 index de8bfc943d7..00000000000 --- a/sys/gnu/dts/mips/mt7621.dtsi +++ /dev/null @@ -1,392 +0,0 @@ -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - compatible = "mediatek,mtk7621-soc"; - - cpus { - cpu@0 { - compatible = "mips,mips1004Kc"; - }; - - cpu@1 { - compatible = "mips,mips1004Kc"; - }; - }; - - cpuintc: cpuintc@0 { - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - compatible = "mti,cpu-interrupt-controller"; - }; - - aliases { - serial0 = &uartlite; - }; - - cpuclock: cpuclock@0 { - #clock-cells = <0>; - compatible = "fixed-clock"; - - /* FIXME: there should be way to detect this */ - clock-frequency = <880000000>; - }; - - sysclock: sysclock@0 { - #clock-cells = <0>; - compatible = "fixed-clock"; - - /* FIXME: there should be way to detect this */ - clock-frequency = <50000000>; - }; - - palmbus: palmbus@1E000000 { - compatible = "palmbus"; - reg = <0x1E000000 0x100000>; - ranges = <0x0 0x1E000000 0x0FFFFF>; - - #address-cells = <1>; - #size-cells = <1>; - - sysc: sysc@0 { - compatible = "mtk,mt7621-sysc"; - reg = <0x0 0x100>; - }; - - wdt: wdt@100 { - compatible = "mtk,mt7621-wdt"; - reg = <0x100 0x100>; - }; - - gpio@600 { - #address-cells = <1>; - #size-cells = <0>; - - compatible = "mtk,mt7621-gpio"; - reg = <0x600 0x100>; - - gpio0: bank@0 { - reg = <0>; - compatible = "mtk,mt7621-gpio-bank"; - gpio-controller; - #gpio-cells = <2>; - }; - - gpio1: bank@1 { - reg = <1>; - compatible = "mtk,mt7621-gpio-bank"; - gpio-controller; - #gpio-cells = <2>; - }; - - gpio2: bank@2 { - reg = <2>; - compatible = "mtk,mt7621-gpio-bank"; - gpio-controller; - #gpio-cells = <2>; - }; - }; - - memc: memc@5000 { - compatible = "mtk,mt7621-memc"; - reg = <0x300 0x100>; - }; - - cpc: cpc@1fbf0000 { - compatible = "mtk,mt7621-cpc"; - reg = <0x1fbf0000 0x8000>; - }; - - mc: mc@1fbf8000 { - compatible = "mtk,mt7621-mc"; - reg = <0x1fbf8000 0x8000>; - }; - - uartlite: uartlite@c00 { - compatible = "ns16550a"; - reg = <0xc00 0x100>; - - clocks = <&sysclock>; - clock-frequency = <50000000>; - - interrupt-parent = <&gic>; - interrupts = ; - - reg-shift = <2>; - reg-io-width = <4>; - no-loopback-test; - }; - - spi0: spi@b00 { - status = "okay"; - - compatible = "ralink,mt7621-spi"; - reg = <0xb00 0x100>; - - clocks = <&sysclock>; - - resets = <&rstctrl 18>; - reset-names = "spi"; - - #address-cells = <1>; - #size-cells = <0>; - - pinctrl-names = "default"; - pinctrl-0 = <&spi_pins>; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - reg = <0>; - spi-max-frequency = <10000000>; - m25p,chunked-io = <32>; - }; - }; - }; - - pinctrl: pinctrl { - compatible = "ralink,rt2880-pinmux"; - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinctrl0 { - }; - - spi_pins: spi { - spi { - ralink,group = "spi"; - ralink,function = "spi"; - }; - }; - - i2c_pins: i2c { - i2c { - ralink,group = "i2c"; - ralink,function = "i2c"; - }; - }; - - uart1_pins: uart1 { - uart1 { - ralink,group = "uart1"; - ralink,function = "uart1"; - }; - }; - - uart2_pins: uart2 { - uart2 { - ralink,group = "uart2"; - ralink,function = "uart2"; - }; - }; - - uart3_pins: uart3 { - uart3 { - ralink,group = "uart3"; - ralink,function = "uart3"; - }; - }; - - rgmii1_pins: rgmii1 { - rgmii1 { - ralink,group = "rgmii1"; - ralink,function = "rgmii1"; - }; - }; - - rgmii2_pins: rgmii2 { - rgmii2 { - ralink,group = "rgmii2"; - ralink,function = "rgmii2"; - }; - }; - - mdio_pins: mdio { - mdio { - ralink,group = "mdio"; - ralink,function = "mdio"; - }; - }; - - pcie_pins: pcie { - pcie { - ralink,group = "pcie"; - ralink,function = "pcie rst"; - }; - }; - - nand_pins: nand { - spi-nand { - ralink,group = "spi"; - ralink,function = "nand1"; - }; - - sdhci-nand { - ralink,group = "sdhci"; - ralink,function = "nand2"; - }; - }; - - sdhci_pins: sdhci { - sdhci { - ralink,group = "sdhci"; - ralink,function = "sdhci"; - }; - }; - }; - - rstctrl: rstctrl { - compatible = "ralink,rt2880-reset"; - #reset-cells = <1>; - }; - - clkctrl: clkctrl { - compatible = "ralink,rt2880-clock"; - #clock-cells = <1>; - }; - - sdhci: sdhci@1E130000 { - compatible = "ralink,mt7620-sdhci"; - reg = <0x1E130000 0x4000>; - - interrupt-parent = <&gic>; - interrupts = ; - }; - - xhci: xhci@1E1C0000 { - status = "okay"; - - compatible = "mediatek,mt8173-xhci"; - reg = <0x1e1c0000 0x1000 - 0x1e1d0700 0x0100>; - - clocks = <&sysclock>; - clock-names = "sys_ck"; - - interrupt-parent = <&gic>; - interrupts = ; - }; - - gic: interrupt-controller@1fbc0000 { - compatible = "mti,gic"; - reg = <0x1fbc0000 0x2000>; - - interrupt-controller; - #interrupt-cells = <3>; - - mti,reserved-cpu-vectors = <7>; - - timer { - compatible = "mti,gic-timer"; - interrupts = ; - clocks = <&cpuclock>; - }; - }; - - nand: nand@1e003000 { - status = "disabled"; - - compatible = "mtk,mt7621-nand"; - bank-width = <2>; - reg = <0x1e003000 0x800 - 0x1e003800 0x800>; - #address-cells = <1>; - #size-cells = <1>; - }; - - ethernet: ethernet@1e100000 { - compatible = "mediatek,mt7621-eth"; - reg = <0x1e100000 0x10000>; - - #address-cells = <1>; - #size-cells = <0>; - - resets = <&rstctrl 6 &rstctrl 23>; - reset-names = "fe", "eth"; - - interrupt-parent = <&gic>; - interrupts = ; - - mediatek,switch = <&gsw>; - - mdio-bus { - #address-cells = <1>; - #size-cells = <0>; - - phy1f: ethernet-phy@1f { - reg = <0x1f>; - phy-mode = "rgmii"; - }; - }; - }; - - gsw: gsw@1e110000 { - compatible = "mediatek,mt7621-gsw"; - reg = <0x1e110000 0x8000>; - interrupt-parent = <&gic>; - interrupts = ; - }; - - pcie: pcie@1e140000 { - compatible = "mediatek,mt7621-pci"; - reg = <0x1e140000 0x100 - 0x1e142000 0x100>; - - #address-cells = <3>; - #size-cells = <2>; - - pinctrl-names = "default"; - pinctrl-0 = <&pcie_pins>; - - device_type = "pci"; - - bus-range = <0 255>; - ranges = < - 0x02000000 0 0x00000000 0x60000000 0 0x10000000 /* pci memory */ - 0x01000000 0 0x00000000 0x1e160000 0 0x00010000 /* io space */ - >; - - interrupt-parent = <&gic>; - interrupts = ; - - status = "okay"; - - resets = <&rstctrl 24 &rstctrl 25 &rstctrl 26>; - reset-names = "pcie0", "pcie1", "pcie2"; - clocks = <&clkctrl 24 &clkctrl 25 &clkctrl 26>; - clock-names = "pcie0", "pcie1", "pcie2"; - - pcie0 { - reg = <0x0000 0 0 0 0>; - - #address-cells = <3>; - #size-cells = <2>; - - device_type = "pci"; - }; - - pcie1 { - reg = <0x0800 0 0 0 0>; - - #address-cells = <3>; - #size-cells = <2>; - - device_type = "pci"; - }; - - pcie2 { - reg = <0x1000 0 0 0 0>; - - #address-cells = <3>; - #size-cells = <2>; - - device_type = "pci"; - }; - }; -}; - -#include "fbsd-mt7621.dtsi" diff --git a/sys/gnu/dts/mips/mt7628an.dtsi b/sys/gnu/dts/mips/mt7628an.dtsi deleted file mode 100644 index 683b65272cf..00000000000 --- a/sys/gnu/dts/mips/mt7628an.dtsi +++ /dev/null @@ -1,478 +0,0 @@ -/ { - #address-cells = <1>; - #size-cells = <1>; - compatible = "ralink,mtk7628an-soc"; - - cpus { - cpu@0 { - compatible = "mips,mips24KEc"; - }; - }; - - chosen { - bootargs = "console=ttyS0,57600"; - }; - - aliases { - serial0 = &uartlite; - }; - - cpuintc: cpuintc@0 { - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - compatible = "mti,cpu-interrupt-controller"; - }; - - palmbus: palmbus@10000000 { - compatible = "palmbus"; - reg = <0x10000000 0x200000>; - ranges = <0x0 0x10000000 0x1FFFFF>; - - #address-cells = <1>; - #size-cells = <1>; - - sysc: sysc@0 { - compatible = "ralink,mt7620a-sysc"; - reg = <0x0 0x100>; - }; - - watchdog: watchdog@120 { - compatible = "ralink,mt7628an-wdt", "mtk,mt7621-wdt"; - reg = <0x120 0x10>; - - resets = <&rstctrl 8>; - reset-names = "wdt"; - - interrupt-parent = <&intc>; - interrupts = <24>; - }; - - intc: intc@200 { - compatible = "ralink,mt7628an-intc", "ralink,rt2880-intc"; - reg = <0x200 0x100>; - - resets = <&rstctrl 9>; - reset-names = "intc"; - - interrupt-controller; - #interrupt-cells = <1>; - - interrupt-parent = <&cpuintc>; - interrupts = <2>; - - ralink,intc-registers = <0x9c 0xa0 - 0x6c 0xa4 - 0x80 0x78>; - }; - - memc: memc@300 { - compatible = "ralink,mt7620a-memc", "ralink,rt3050-memc"; - reg = <0x300 0x100>; - - resets = <&rstctrl 20>; - reset-names = "mc"; - - interrupt-parent = <&intc>; - interrupts = <3>; - }; - - gpio@600 { - #address-cells = <1>; - #size-cells = <0>; - - compatible = "mtk,mt7628-gpio", "mtk,mt7621-gpio"; - reg = <0x600 0x100>; - - interrupt-parent = <&intc>; - interrupts = <6>; - - gpio0: bank@0 { - reg = <0>; - compatible = "mtk,mt7621-gpio-bank"; - gpio-controller; - #gpio-cells = <2>; - }; - - gpio1: bank@1 { - reg = <1>; - compatible = "mtk,mt7621-gpio-bank"; - gpio-controller; - #gpio-cells = <2>; - }; - - gpio2: bank@2 { - reg = <2>; - compatible = "mtk,mt7621-gpio-bank"; - gpio-controller; - #gpio-cells = <2>; - }; - }; - - i2c: i2c@900 { - compatible = "mediatek,mt7628-i2c"; - reg = <0x900 0x100>; - - resets = <&rstctrl 16>; - reset-names = "i2c"; - - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - - pinctrl-names = "default"; - pinctrl-0 = <&i2c_pins>; - }; - - i2s: i2s@a00 { - compatible = "ralink,mt7620a-i2s"; - reg = <0xa00 0x100>; - - resets = <&rstctrl 17>; - reset-names = "i2s"; - - interrupt-parent = <&intc>; - interrupts = <10>; - - dmas = <&gdma 2>, - <&gdma 3>; - dma-names = "tx", "rx"; - - status = "disabled"; - }; - - spi0: spi@b00 { - compatible = "ralink,mt7621-spi"; - reg = <0xb00 0x100>; - - resets = <&rstctrl 18>; - reset-names = "spi"; - - #address-cells = <1>; - #size-cells = <0>; - - pinctrl-names = "default"; - pinctrl-0 = <&spi_pins>; - - status = "disabled"; - }; - - uartlite: uartlite@c00 { - compatible = "ns16550a"; - reg = <0xc00 0x100>; - - reg-shift = <2>; - reg-io-width = <4>; - no-loopback-test; - - clock-frequency = <40000000>; - - resets = <&rstctrl 12>; - reset-names = "uartl"; - - interrupt-parent = <&intc>; - interrupts = <20>; - - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - }; - - uart1: uart1@d00 { - compatible = "ns16550a"; - reg = <0xd00 0x100>; - - reg-shift = <2>; - reg-io-width = <4>; - no-loopback-test; - - clock-frequency = <40000000>; - - resets = <&rstctrl 19>; - reset-names = "uart1"; - - interrupt-parent = <&intc>; - interrupts = <21>; - - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; - - status = "disabled"; - }; - - uart2: uart2@e00 { - compatible = "ns16550a"; - reg = <0xe00 0x100>; - - reg-shift = <2>; - reg-io-width = <4>; - no-loopback-test; - - clock-frequency = <40000000>; - - resets = <&rstctrl 20>; - reset-names = "uart2"; - - interrupt-parent = <&intc>; - interrupts = <22>; - - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; - - status = "disabled"; - }; - - pwm: pwm@5000 { - compatible = "mediatek,mt7628-pwm"; - reg = <0x5000 0x1000>; - - resets = <&rstctrl 31>; - reset-names = "pwm"; - - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pins>, <&pwm1_pins>; - - status = "disabled"; - }; - - pcm: pcm@2000 { - compatible = "ralink,mt7620a-pcm"; - reg = <0x2000 0x800>; - - resets = <&rstctrl 11>; - reset-names = "pcm"; - - interrupt-parent = <&intc>; - interrupts = <4>; - - status = "disabled"; - }; - - gdma: gdma@2800 { - compatible = "ralink,mt7620a-gdma", "ralink,rt2880-gdma"; - reg = <0x2800 0x800>; - - resets = <&rstctrl 14>; - reset-names = "dma"; - - interrupt-parent = <&intc>; - interrupts = <7>; - - #dma-cells = <1>; - #dma-channels = <16>; - #dma-requests = <16>; - - status = "disabled"; - }; - }; - - pinctrl: pinctrl { - compatible = "ralink,rt2880-pinmux"; - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinctrl0 { - }; - - spi_pins: spi { - spi { - ralink,group = "spi"; - ralink,function = "spi"; - }; - }; - - spi_cs1_pins: spi_cs1 { - spi_cs1 { - ralink,group = "spi cs1"; - ralink,function = "spi cs1"; - }; - }; - - i2c_pins: i2c { - i2c { - ralink,group = "i2c"; - ralink,function = "i2c"; - }; - }; - - uart0_pins: uartlite { - uartlite { - ralink,group = "uart0"; - ralink,function = "uart0"; - }; - }; - - uart1_pins: uart1 { - uart1 { - ralink,group = "uart1"; - ralink,function = "uart1"; - }; - }; - - uart2_pins: uart2 { - uart2 { - ralink,group = "uart2"; - ralink,function = "uart2"; - }; - }; - - sdxc_pins: sdxc { - sdxc { - ralink,group = "sdmode"; - ralink,function = "sdxc"; - }; - }; - - pwm0_pins: pwm0 { - pwm0 { - ralink,group = "pwm0"; - ralink,function = "pwm0"; - }; - }; - - pwm1_pins: pwm1 { - pwm1 { - ralink,group = "pwm1"; - ralink,function = "pwm1"; - }; - }; - - pcm_i2s_pins: i2s { - i2s { - ralink,group = "i2s"; - ralink,function = "pcm"; - }; - }; - }; - - rstctrl: rstctrl { - compatible = "ralink,mt7620a-reset", "ralink,rt2880-reset"; - #reset-cells = <1>; - }; - - clkctrl: clkctrl { - compatible = "ralink,rt2880-clock"; - #clock-cells = <1>; - }; - - usbphy: usbphy@10120000 { - compatible = "ralink,mt7628an-usbphy", "mediatek,mt7620-usbphy"; - reg = <0x10120000 0x4000>; - #phy-cells = <1>; - - resets = <&rstctrl 22 &rstctrl 25>; - reset-names = "host", "device"; - clocks = <&clkctrl 22 &clkctrl 25>; - clock-names = "host", "device"; - }; - - sdhci: sdhci@10130000 { - compatible = "ralink,mt7620-sdhci"; - reg = <0x10130000 0x4000>; - - interrupt-parent = <&intc>; - interrupts = <14>; - - pinctrl-names = "default"; - pinctrl-0 = <&sdxc_pins>; - - status = "disabled"; - }; - - ehci: ehci@101c0000 { - compatible = "generic-ehci"; - reg = <0x101c0000 0x1000>; - - phys = <&usbphy 1>; - phy-names = "usb"; - - interrupt-parent = <&intc>; - interrupts = <18>; - }; - - ohci: ohci@101c1000 { - compatible = "generic-ohci"; - reg = <0x101c1000 0x1000>; - - phys = <&usbphy 1>; - phy-names = "usb"; - - interrupt-parent = <&intc>; - interrupts = <18>; - }; - - ethernet: ethernet@10100000 { - compatible = "ralink,rt5350-eth"; - reg = <0x10100000 0x10000>; - - interrupt-parent = <&cpuintc>; - interrupts = <5>; - - resets = <&rstctrl 21 &rstctrl 23>; - reset-names = "fe", "esw"; - - mediatek,switch = <&esw>; - }; - - esw: esw@10110000 { - compatible = "mediatek,mt7628-esw", "ralink,rt3050-esw"; - reg = <0x10110000 0x8000>; - - resets = <&rstctrl 23>; - reset-names = "esw"; - - interrupt-parent = <&intc>; - interrupts = <17>; - }; - - pcie: pcie@10140000 { - compatible = "mediatek,mt7620-pci"; - reg = <0x10140000 0x100 - 0x10142000 0x100>; - - #address-cells = <3>; - #size-cells = <2>; - - interrupt-parent = <&cpuintc>; - interrupts = <4>; - - resets = <&rstctrl 26 &rstctrl 27>; - reset-names = "pcie0", "pcie1"; - clocks = <&clkctrl 26 &clkctrl 27>; - clock-names = "pcie0", "pcie1"; - - status = "disabled"; - - device_type = "pci"; - - bus-range = <0 255>; - ranges = < - 0x02000000 0 0x00000000 0x20000000 0 0x10000000 /* pci memory */ - 0x01000000 0 0x00000000 0x10160000 0 0x00010000 /* io space */ - >; - - pcie-bridge { - reg = <0x0000 0 0 0 0>; - - #address-cells = <3>; - #size-cells = <2>; - - device_type = "pci"; - }; - }; - - wmac: wmac@10300000 { - compatible = "mediatek,mt7628-wmac"; - reg = <0x10300000 0x100000>; - - interrupt-parent = <&cpuintc>; - interrupts = <6>; - - status = "disabled"; - - mediatek,mtd-eeprom = <&factory 0x0000>; - mediatek,5ghz = <0>; - }; -}; - -#include "fbsd-mt7628an.dtsi" diff --git a/sys/gnu/dts/mips/rt2880.dtsi b/sys/gnu/dts/mips/rt2880.dtsi deleted file mode 100644 index 284a7e9b2c7..00000000000 --- a/sys/gnu/dts/mips/rt2880.dtsi +++ /dev/null @@ -1,206 +0,0 @@ -/ { - #address-cells = <1>; - #size-cells = <1>; - compatible = "ralink,rt2880-soc"; - - cpus { - cpu@0 { - compatible = "mips,mips4KEc"; - }; - }; - - chosen { - bootargs = "console=ttyS0,57600"; - }; - - aliases { - serial0 = &uartlite; - }; - - cpuintc: cpuintc@0 { - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - compatible = "mti,cpu-interrupt-controller"; - }; - - palmbus: palmbus@300000 { - compatible = "palmbus"; - reg = <0x300000 0x200000>; - ranges = <0x0 0x300000 0x1FFFFF>; - - #address-cells = <1>; - #size-cells = <1>; - - sysc: sysc@0 { - compatible = "ralink,rt2880-sysc"; - reg = <0x000 0x100>; - }; - - timer: timer@100 { - compatible = "ralink,rt2880-timer"; - reg = <0x100 0x20>; - - interrupt-parent = <&intc>; - interrupts = <1>; - - status = "disabled"; - }; - - watchdog: watchdog@120 { - compatible = "ralink,rt2880-wdt"; - reg = <0x120 0x10>; - }; - - intc: intc@200 { - compatible = "ralink,rt2880-intc"; - reg = <0x200 0x100>; - - interrupt-controller; - #interrupt-cells = <1>; - - interrupt-parent = <&cpuintc>; - interrupts = <2>; - }; - - memc: memc@300 { - compatible = "ralink,rt2880-memc"; - reg = <0x300 0x100>; - }; - - gpio0: gpio@600 { - compatible = "ralink,rt2880-gpio"; - reg = <0x600 0x34>; - - gpio-controller; - #gpio-cells = <2>; - - ralink,gpio-base = <0>; - ralink,num-gpios = <24>; - ralink,register-map = [ 00 04 08 0c - 20 24 28 2c - 30 34 ]; - - interrupt-parent = <&intc>; - interrupts = <7>; - }; - - gpio1: gpio@638 { - compatible = "ralink,rt2880-gpio"; - reg = <0x638 0x24>; - - gpio-controller; - #gpio-cells = <2>; - - ralink,gpio-base = <24>; - ralink,num-gpios = <16>; - ralink,register-map = [ 00 04 08 0c - 10 14 18 1c - 20 24 ]; - - status = "disabled"; - }; - - gpio2: gpio@660 { - compatible = "ralink,rt2880-gpio"; - reg = <0x660 0x24>; - - gpio-controller; - #gpio-cells = <2>; - - ralink,gpio-base = <40>; - ralink,num-gpios = <32>; - ralink,register-map = [ 00 04 08 0c - 10 14 18 1c - 20 24 ]; - - status = "disabled"; - }; - - uartlite: uartlite@c00 { - compatible = "ralink,rt2880-uart", "ns16550a"; - reg = <0xc00 0x100>; - - interrupt-parent = <&intc>; - interrupts = <8>; - - reg-shift = <2>; - }; - }; - - pinctrl: pinctrl { - compatible = "ralink,rt2880-pinmux"; - - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinctrl0 { - sdram { - ralink,group = "sdram"; - ralink,function = "sdram"; - }; - }; - - spi_pins: spi { - spi { - ralink,group = "spi"; - ralink,function = "spi"; - }; - }; - - uartlite_pins: uartlite { - uart { - ralink,group = "uartlite"; - ralink,function = "uartlite"; - }; - }; - }; - - rstctrl: rstctrl { - compatible = "ralink,rt2880-reset"; - #reset-cells = <1>; - }; - - clkctrl: clkctrl { - compatible = "ralink,rt2880-clock"; - #clock-cells = <1>; - }; - - ethernet: ethernet@400000 { - compatible = "ralink,rt2880-eth"; - reg = <0x00400000 0x10000>; - - #address-cells = <1>; - #size-cells = <0>; - - resets = <&rstctrl 18>; - reset-names = "fe"; - - interrupt-parent = <&cpuintc>; - interrupts = <5>; - - status = "disabled"; - - port@0 { - compatible = "ralink,rt2880-port", "mediatek,eth-port"; - reg = <0>; - }; - }; - - mdio-bus { - compatible = "ralink,rt2880-mdio"; - reg = <0x00400000 0x10000>; - #address-cells = <1>; - #size-cells = <0>; - }; - - wmac: wmac@480000 { - compatible = "ralink,rt2880-wmac"; - reg = <0x480000 0x40000>; - - interrupt-parent = <&cpuintc>; - interrupts = <6>; - - ralink,eeprom = "soc_wmac.eeprom"; - }; -}; diff --git a/sys/gnu/dts/mips/rt3050.dtsi b/sys/gnu/dts/mips/rt3050.dtsi deleted file mode 100644 index caf448bd160..00000000000 --- a/sys/gnu/dts/mips/rt3050.dtsi +++ /dev/null @@ -1,277 +0,0 @@ -/ { - #address-cells = <1>; - #size-cells = <1>; - compatible = "ralink,rt3050-soc", "ralink,rt3052-soc", "ralink,rt3350-soc"; - - cpus { - cpu@0 { - compatible = "mips,mips24KEc"; - }; - }; - - chosen { - bootargs = "console=ttyS0,57600"; - }; - - aliases { - spi0 = &spi0; - serial0 = &uartlite; - }; - - cpuintc: cpuintc@0 { - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - compatible = "mti,cpu-interrupt-controller"; - }; - - palmbus: palmbus@10000000 { - compatible = "palmbus"; - reg = <0x10000000 0x200000>; - ranges = <0x0 0x10000000 0x1FFFFF>; - - #address-cells = <1>; - #size-cells = <1>; - - sysc: sysc@0 { - compatible = "ralink,rt3050-sysc"; - reg = <0x0 0x100>; - }; - - timer: timer@100 { - compatible = "ralink,rt3050-timer", "ralink,rt2880-timer"; - reg = <0x100 0x20>; - - interrupt-parent = <&intc>; - interrupts = <1>; - }; - - watchdog: watchdog@120 { - compatible = "ralink,rt3050-wdt", "ralink,rt2880-wdt"; - reg = <0x120 0x10>; - - resets = <&rstctrl 8>; - reset-names = "wdt"; - - interrupt-parent = <&intc>; - interrupts = <1>; - }; - - intc: intc@200 { - compatible = "ralink,rt3050-intc", "ralink,rt2880-intc"; - reg = <0x200 0x100>; - - resets = <&rstctrl 19>; - reset-names = "intc"; - - interrupt-controller; - #interrupt-cells = <1>; - - interrupt-parent = <&cpuintc>; - interrupts = <2>; - }; - - memc: memc@300 { - compatible = "ralink,rt3050-memc"; - reg = <0x300 0x100>; - - resets = <&rstctrl 20>; - reset-names = "mc"; - - interrupt-parent = <&intc>; - interrupts = <3>; - }; - - uart: uart@500 { - compatible = "ralink,rt3050-uart", "ralink,rt2880-uart", "ns16550a"; - reg = <0x500 0x100>; - - resets = <&rstctrl 12>; - reset-names = "uart"; - - interrupt-parent = <&intc>; - interrupts = <5>; - - reg-shift = <2>; - - status = "disabled"; - }; - - gpio0: gpio@600 { - compatible = "ralink,rt3050-gpio", "ralink,rt2880-gpio"; - reg = <0x600 0x34>; - - gpio-controller; - #gpio-cells = <2>; - - ralink,gpio-base = <0>; - ralink,num-gpios = <24>; - ralink,register-map = [ 00 04 08 0c - 20 24 28 2c - 30 34 ]; - - resets = <&rstctrl 13>; - reset-names = "pio"; - - interrupt-parent = <&intc>; - interrupts = <6>; - }; - - gpio1: gpio@638 { - compatible = "ralink,rt3050-gpio", "ralink,rt2880-gpio"; - reg = <0x638 0x24>; - - gpio-controller; - #gpio-cells = <2>; - - ralink,gpio-base = <24>; - ralink,num-gpios = <16>; - ralink,register-map = [ 00 04 08 0c - 10 14 18 1c - 20 24 ]; - - status = "disabled"; - }; - - gpio2: gpio@660 { - compatible = "ralink,rt3050-gpio", "ralink,rt2880-gpio"; - reg = <0x660 0x24>; - - gpio-controller; - #gpio-cells = <2>; - - ralink,gpio-base = <40>; - ralink,num-gpios = <12>; - ralink,register-map = [ 00 04 08 0c - 10 14 18 1c - 20 24 ]; - - status = "disabled"; - }; - - spi0: spi@b00 { - compatible = "ralink,rt3050-spi", "ralink,rt2880-spi"; - reg = <0xb00 0x100>; - - resets = <&rstctrl 18>; - reset-names = "spi"; - - #address-cells = <1>; - #size-cells = <0>; - - pinctrl-names = "default"; - pinctrl-0 = <&spi_pins>; - - status = "disabled"; - }; - - uartlite: uartlite@c00 { - compatible = "ralink,rt3050-uart", "ralink,rt2880-uart", "ns16550a"; - reg = <0xc00 0x100>; - - resets = <&rstctrl 19>; - reset-names = "uartl"; - - interrupt-parent = <&intc>; - interrupts = <12>; - - reg-shift = <2>; - - pinctrl-names = "default"; - pinctrl-0 = <&uartlite_pins>; - }; - }; - - pinctrl: pinctrl { - compatible = "ralink,rt2880-pinmux"; - - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinctrl0 { - sdram { - ralink,group = "sdram"; - ralink,function = "sdram"; - }; - }; - - spi_pins: spi { - spi { - ralink,group = "spi"; - ralink,function = "spi"; - }; - }; - - uartlite_pins: uartlite { - uart { - ralink,group = "uartlite"; - ralink,function = "uartlite"; - }; - }; - }; - - rstctrl: rstctrl { - compatible = "ralink,rt3050-reset", "ralink,rt2880-reset"; - #reset-cells = <1>; - }; - - clkctrl: clkctrl { - compatible = "ralink,rt2880-clock"; - #clock-cells = <1>; - }; - - usbphy: usbphy { - compatible = "ralink,rt3050-usbphy"; - resets = <&rstctrl 22>; - reset-names = "host"; - clocks = <&clkctrl 18>; - clock-names = "host"; - }; - - ethernet: ethernet@10100000 { - compatible = "ralink,rt3050-eth"; - reg = <0x10100000 0x10000>; - - resets = <&rstctrl 21>; - reset-names = "fe"; - - interrupt-parent = <&cpuintc>; - interrupts = <5>; - - mediatek,switch = <&esw>; - }; - - esw: esw@10110000 { - compatible = "ralink,rt3050-esw"; - reg = <0x10110000 0x8000>; - - resets = <&rstctrl 23>; - reset-names = "esw"; - - interrupt-parent = <&intc>; - interrupts = <17>; - }; - - wmac: wmac@10180000 { - compatible = "ralink,rt3050-wmac", "ralink,rt2880-wmac"; - reg = <0x10180000 0x40000>; - - interrupt-parent = <&cpuintc>; - interrupts = <6>; - - ralink,eeprom = "soc_wmac.eeprom"; - }; - - otg: otg@101c0000 { - compatible = "ralink,rt3050-otg", "snps,dwc2"; - reg = <0x101c0000 0x40000>; - - interrupt-parent = <&intc>; - interrupts = <18>; - - resets = <&rstctrl 22>; - reset-names = "otg"; - - status = "disabled"; - }; -}; diff --git a/sys/gnu/dts/mips/rt3352.dtsi b/sys/gnu/dts/mips/rt3352.dtsi deleted file mode 100644 index 0f64576b1ea..00000000000 --- a/sys/gnu/dts/mips/rt3352.dtsi +++ /dev/null @@ -1,306 +0,0 @@ -/ { - #address-cells = <1>; - #size-cells = <1>; - compatible = "ralink,rt3352-soc"; - - cpus { - cpu@0 { - compatible = "mips,mips24KEc"; - }; - }; - - chosen { - bootargs = "console=ttyS0,57600"; - }; - - cpuintc: cpuintc@0 { - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - compatible = "mti,cpu-interrupt-controller"; - }; - - aliases { - spi0 = &spi0; - spi1 = &spi1; - serial0 = &uartlite; - }; - - palmbus: palmbus@10000000 { - compatible = "palmbus"; - reg = <0x10000000 0x200000>; - ranges = <0x0 0x10000000 0x1FFFFF>; - - #address-cells = <1>; - #size-cells = <1>; - - sysc: sysc@0 { - compatible = "ralink,rt3352-sysc", "ralink,rt3050-sysc"; - reg = <0x0 0x100>; - }; - - timer: timer@100 { - compatible = "ralink,rt3352-timer", "ralink,rt2880-timer"; - reg = <0x100 0x20>; - - interrupt-parent = <&intc>; - interrupts = <1>; - }; - - watchdog: watchdog@120 { - compatible = "ralink,rt3352-wdt", "ralink,rt2880-wdt"; - reg = <0x120 0x10>; - - resets = <&rstctrl 8>; - reset-names = "wdt"; - - interrupt-parent = <&intc>; - interrupts = <1>; - }; - - intc: intc@200 { - compatible = "ralink,rt3352-intc", "ralink,rt2880-intc"; - reg = <0x200 0x100>; - - interrupt-controller; - #interrupt-cells = <1>; - - interrupt-parent = <&cpuintc>; - interrupts = <2>; - }; - - memc: memc@300 { - compatible = "ralink,rt3352-memc", "ralink,rt3050-memc"; - reg = <0x300 0x100>; - - resets = <&rstctrl 20>; - reset-names = "mc"; - - interrupt-parent = <&intc>; - interrupts = <3>; - }; - - uart: uart@500 { - compatible = "ralink,rt3352-uart", "ralink,rt2880-uart", "ns16550a"; - reg = <0x500 0x100>; - - resets = <&rstctrl 12>; - reset-names = "uart"; - - interrupt-parent = <&intc>; - interrupts = <5>; - - reg-shift = <2>; - - status = "disabled"; - }; - - gpio0: gpio@600 { - compatible = "ralink,rt3352-gpio", "ralink,rt2880-gpio"; - reg = <0x600 0x34>; - - gpio-controller; - #gpio-cells = <2>; - - ralink,gpio-base = <0>; - ralink,num-gpios = <24>; - ralink,register-map = [ 00 04 08 0c - 20 24 28 2c - 30 34 ]; - resets = <&rstctrl 13>; - reset-names = "pio"; - - interrupt-parent = <&intc>; - interrupts = <6>; - }; - - gpio1: gpio@638 { - compatible = "ralink,rt3352-gpio", "ralink,rt2880-gpio"; - reg = <0x638 0x24>; - - gpio-controller; - #gpio-cells = <2>; - - ralink,gpio-base = <24>; - ralink,num-gpios = <16>; - ralink,register-map = [ 00 04 08 0c - 10 14 18 1c - 20 24 ]; - - status = "disabled"; - }; - - gpio2: gpio@660 { - compatible = "ralink,rt3352-gpio", "ralink,rt2880-gpio"; - reg = <0x660 0x24>; - - gpio-controller; - #gpio-cells = <2>; - - ralink,gpio-base = <40>; - ralink,num-gpios = <6>; - ralink,register-map = [ 00 04 08 0c - 10 14 18 1c - 20 24 ]; - - status = "disabled"; - }; - - spi0: spi@b00 { - compatible = "ralink,rt3352-spi", "ralink,rt2880-spi"; - reg = <0xb00 0x40>; - #address-cells = <1>; - #size-cells = <0>; - - resets = <&rstctrl 18>; - reset-names = "spi"; - - pinctrl-names = "default"; - pinctrl-0 = <&spi_pins>; - - status = "disabled"; - }; - - spi1: spi@b40 { - compatible = "ralink,rt3352-spi", "ralink,rt2880-spi"; - reg = <0xb40 0x60>; - #address-cells = <1>; - #size-cells = <0>; - - resets = <&rstctrl 18>; - reset-names = "spi"; - - pinctrl-names = "default"; - pinctrl-0 = <&spi_cs1>; - - status = "disabled"; - }; - - uartlite: uartlite@c00 { - compatible = "ralink,rt3352-uart", "ralink,rt2880-uart", "ns16550a"; - reg = <0xc00 0x100>; - - resets = <&rstctrl 19>; - reset-names = "uartl"; - - interrupt-parent = <&intc>; - interrupts = <12>; - - reg-shift = <2>; - - pinctrl-names = "default"; - pinctrl-0 = <&uartlite_pins>; - }; - }; - - pinctrl: pinctrl { - compatible = "ralink,rt2880-pinmux"; - - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinctrl0 { - }; - - spi_pins: spi { - spi { - ralink,group = "spi"; - ralink,function = "spi"; - }; - }; - - spi_cs1: spi1 { - spi1 { - ralink,group = "spi_cs1"; - ralink,function = "spi_cs1"; - }; - }; - - uartlite_pins: uartlite { - uart { - ralink,group = "uartlite"; - ralink,function = "uartlite"; - }; - }; - }; - - rstctrl: rstctrl { - compatible = "ralink,rt3352-reset", "ralink,rt2880-reset"; - #reset-cells = <1>; - }; - - clkctrl: clkctrl { - compatible = "ralink,rt2880-clock"; - #clock-cells = <1>; - }; - - ethernet: ethernet@10100000 { - compatible = "ralink,rt3352-eth", "ralink,rt3050-eth"; - reg = <0x10100000 0x10000>; - - resets = <&rstctrl 21>; - reset-names = "fe"; - - interrupt-parent = <&cpuintc>; - interrupts = <5>; - - mediatek,switch = <&esw>; - }; - - esw: esw@10110000 { - compatible = "ralink,rt3352-esw", "ralink,rt3050-esw"; - reg = <0x10110000 0x8000>; - - resets = <&rstctrl 23>; - reset-names = "esw"; - - interrupt-parent = <&intc>; - interrupts = <17>; - }; - - usbphy: usbphy { - compatible = "ralink,rt3352-usbphy"; - #phy-cells = <1>; - - resets = <&rstctrl 22 &rstctrl 25>; - reset-names = "host", "device"; - clocks = <&clkctrl 18 &clkctrl 20>; - clock-names = "host", "device"; - }; - - wmac: wmac@10180000 { - compatible = "ralink,rt3352-wmac", "ralink,rt2880-wmac"; - reg = <0x10180000 0x40000>; - - interrupt-parent = <&cpuintc>; - interrupts = <6>; - - ralink,eeprom = "soc_wmac.eeprom"; - }; - - ehci: ehci@101c0000 { - compatible = "generic-ehci"; - reg = <0x101c0000 0x1000>; - - phys = <&usbphy 1>; - phy-names = "usb"; - - interrupt-parent = <&intc>; - interrupts = <18>; - - status = "disabled"; - }; - - ohci: ohci@101c1000 { - compatible = "generic-ohci"; - reg = <0x101c1000 0x1000>; - - phys = <&usbphy 1>; - phy-names = "usb"; - - interrupt-parent = <&intc>; - interrupts = <18>; - - status = "disabled"; - }; -}; diff --git a/sys/gnu/dts/mips/rt3883.dtsi b/sys/gnu/dts/mips/rt3883.dtsi deleted file mode 100644 index e4fa2aeca05..00000000000 --- a/sys/gnu/dts/mips/rt3883.dtsi +++ /dev/null @@ -1,413 +0,0 @@ -/ { - #address-cells = <1>; - #size-cells = <1>; - compatible = "ralink,rt3883-soc"; - - cpus { - cpu@0 { - compatible = "mips,mips74Kc"; - }; - }; - - chosen { - bootargs = "console=ttyS0,57600"; - }; - - aliases { - spi0 = &spi0; - spi1 = &spi1; - serial0 = &uartlite; - }; - - cpuintc: cpuintc@0 { - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - compatible = "mti,cpu-interrupt-controller"; - }; - - palmbus: palmbus@10000000 { - compatible = "palmbus"; - reg = <0x10000000 0x200000>; - ranges = <0x0 0x10000000 0x1FFFFF>; - - #address-cells = <1>; - #size-cells = <1>; - - sysc: sysc@0 { - compatible = "ralink,rt3883-sysc", "ralink,rt3050-sysc"; - reg = <0x0 0x100>; - }; - - timer: timer@100 { - compatible = "ralink,rt3883-timer", "ralink,rt2880-timer"; - reg = <0x100 0x20>; - - interrupt-parent = <&intc>; - interrupts = <1>; - }; - - watchdog: watchdog@120 { - compatible = "ralink,rt3883-wdt", "ralink,rt2880-wdt"; - reg = <0x120 0x10>; - - resets = <&rstctrl 8>; - reset-names = "wdt"; - - interrupt-parent = <&intc>; - interrupts = <1>; - }; - - intc: intc@200 { - compatible = "ralink,rt3883-intc", "ralink,rt2880-intc"; - reg = <0x200 0x100>; - - resets = <&rstctrl 19>; - reset-names = "intc"; - - interrupt-controller; - #interrupt-cells = <1>; - - interrupt-parent = <&cpuintc>; - interrupts = <2>; - }; - - memc: memc@300 { - compatible = "ralink,rt3883-memc", "ralink,rt3050-memc"; - reg = <0x300 0x100>; - - resets = <&rstctrl 20>; - reset-names = "mc"; - - interrupt-parent = <&intc>; - interrupts = <3>; - }; - - uart: uart@500 { - compatible = "ralink,rt3883-uart", "ralink,rt2880-uart", "ns16550a"; - reg = <0x500 0x100>; - - resets = <&rstctrl 12>; - reset-names = "uart"; - - interrupt-parent = <&intc>; - interrupts = <5>; - - reg-shift = <2>; - - status = "disabled"; - }; - - gpio0: gpio@600 { - compatible = "ralink,rt3883-gpio", "ralink,rt2880-gpio"; - reg = <0x600 0x34>; - - resets = <&rstctrl 13>; - reset-names = "pio"; - - interrupt-parent = <&intc>; - interrupts = <6>; - - gpio-controller; - #gpio-cells = <2>; - - ralink,gpio-base = <0>; - ralink,num-gpios = <24>; - ralink,register-map = [ 00 04 08 0c - 20 24 28 2c - 30 34 ]; - }; - - gpio1: gpio@638 { - compatible = "ralink,rt3883-gpio", "ralink,rt2880-gpio"; - reg = <0x638 0x24>; - - gpio-controller; - #gpio-cells = <2>; - - ralink,gpio-base = <24>; - ralink,num-gpios = <16>; - ralink,register-map = [ 00 04 08 0c - 10 14 18 1c - 20 24 ]; - - status = "disabled"; - }; - - gpio2: gpio@660 { - compatible = "ralink,rt3883-gpio", "ralink,rt2880-gpio"; - reg = <0x660 0x24>; - - gpio-controller; - #gpio-cells = <2>; - - ralink,gpio-base = <40>; - ralink,num-gpios = <32>; - ralink,register-map = [ 00 04 08 0c - 10 14 18 1c - 20 24 ]; - - status = "disabled"; - }; - - gpio3: gpio@688 { - compatible = "ralink,rt3883-gpio", "ralink,rt2880-gpio"; - reg = <0x688 0x24>; - - gpio-controller; - #gpio-cells = <2>; - - ralink,gpio-base = <72>; - ralink,num-gpios = <24>; - ralink,register-map = [ 00 04 08 0c - 10 14 18 1c - 20 24 ]; - - status = "disabled"; - }; - - spi0: spi@b00 { - compatible = "ralink,rt3883-spi", "ralink,rt2880-spi"; - reg = <0xb00 0x40>; - #address-cells = <1>; - #size-cells = <0>; - - resets = <&rstctrl 18>; - reset-names = "spi"; - - pinctrl-names = "default"; - pinctrl-0 = <&spi_pins>; - - status = "disabled"; - }; - - spi1: spi@b40 { - compatible = "ralink,rt3883-spi", "ralink,rt2880-spi"; - reg = <0xb40 0x60>; - #address-cells = <1>; - #size-cells = <0>; - - resets = <&rstctrl 18>; - reset-names = "spi"; - - pinctrl-names = "default"; - pinctrl-0 = <&spi_cs1>; - - status = "disabled"; - }; - - uartlite: uartlite@c00 { - compatible = "ralink,rt3883-uart", "ralink,rt2880-uart", "ns16550a"; - reg = <0xc00 0x100>; - - resets = <&rstctrl 19>; - reset-names = "uartl"; - - interrupt-parent = <&intc>; - interrupts = <12>; - - reg-shift = <2>; - - pinctrl-names = "default"; - pinctrl-0 = <&uartlite_pins>; - }; - }; - - pinctrl: pinctrl { - compatible = "ralink,rt2880-pinmux"; - - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinctrl0 { - }; - - spi_pins: spi { - spi { - ralink,group = "spi"; - ralink,function = "spi"; - }; - }; - - spi_cs1: spi1 { - spi1 { - ralink,group = "spi_cs1"; - ralink,function = "spi_cs1"; - }; - }; - - uartlite_pins: uartlite { - uart { - ralink,group = "uartlite"; - ralink,function = "uartlite"; - }; - }; - }; - - ethernet: ethernet@10100000 { - compatible = "ralink,rt3883-eth"; - reg = <0x10100000 0x10000>; - - resets = <&rstctrl 21>; - reset-names = "fe"; - - interrupt-parent = <&cpuintc>; - interrupts = <5>; - - port@0 { - compatible = "ralink,rt3883-port", "mediatek,eth-port"; - reg = <0>; - }; - - mdio-bus { - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - }; - - rstctrl: rstctrl { - compatible = "ralink,rt3883-reset", "ralink,rt2880-reset"; - #reset-cells = <1>; - }; - - clkctrl: clkctrl { - compatible = "ralink,rt2880-clock"; - #clock-cells = <1>; - }; - - pci: pci@10140000 { - compatible = "ralink,rt3883-pci"; - reg = <0x10140000 0x20000>; - #address-cells = <1>; - #size-cells = <1>; - ranges; /* direct mapping */ - - status = "disabled"; - - pciintc: interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - - interrupt-parent = <&cpuintc>; - interrupts = <4>; - }; - - host-bridge { - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - - device_type = "pci"; - - bus-range = <0 255>; - ranges = < - 0x02000000 0 0x00000000 0x20000000 0 0x10000000 /* pci memory */ - 0x01000000 0 0x00000000 0x10160000 0 0x00010000 /* io space */ - >; - - interrupt-map-mask = <0xf800 0 0 7>; - interrupt-map = < - /* IDSEL 17 */ - 0x8800 0 0 1 &pciintc 18 - 0x8800 0 0 2 &pciintc 18 - 0x8800 0 0 3 &pciintc 18 - 0x8800 0 0 4 &pciintc 18 - /* IDSEL 18 */ - 0x9000 0 0 1 &pciintc 19 - 0x9000 0 0 2 &pciintc 19 - 0x9000 0 0 3 &pciintc 19 - 0x9000 0 0 4 &pciintc 19 - >; - - pci-bridge@1 { - reg = <0x0800 0 0 0 0>; - device_type = "pci"; - #interrupt-cells = <1>; - #address-cells = <3>; - #size-cells = <2>; - - status = "disabled"; - - ralink,pci-slot = <1>; - - interrupt-map-mask = <0x0 0 0 0>; - interrupt-map = <0x0 0 0 0 &pciintc 20>; - }; - - pci-slot@17 { - reg = <0x8800 0 0 0 0>; - device_type = "pci"; - #interrupt-cells = <1>; - #address-cells = <3>; - #size-cells = <2>; - - ralink,pci-slot = <17>; - - status = "disabled"; - }; - - pci-slot@18 { - reg = <0x9000 0 0 0 0>; - device_type = "pci"; - #interrupt-cells = <1>; - #address-cells = <3>; - #size-cells = <2>; - - ralink,pci-slot = <18>; - - status = "disabled"; - }; - }; - }; - - usbphy: usbphy { - compatible = "ralink,rt3352-usbphy"; - #phy-cells = <1>; - - resets = <&rstctrl 22 &rstctrl 25>; - reset-names = "host", "device"; - clocks = <&clkctrl 22 &clkctrl 25>; - clock-names = "host", "device"; - }; - - wmac: wmac@10180000 { - compatible = "ralink,rt3883-wmac", "ralink,rt2880-wmac"; - reg = <0x10180000 0x40000>; - - interrupt-parent = <&cpuintc>; - interrupts = <6>; - - ralink,eeprom = "soc_wmac.eeprom"; - }; - - ehci: ehci@101c0000 { - compatible = "generic-ehci"; - reg = <0x101c0000 0x1000>; - - phys = <&usbphy 1>; - phy-names = "usb"; - - interrupt-parent = <&intc>; - interrupts = <18>; - - status = "disabled"; - }; - - ohci: ohci@101c1000 { - compatible = "generic-ohci"; - reg = <0x101c1000 0x1000>; - - phys = <&usbphy 1>; - phy-names = "usb"; - - interrupt-parent = <&intc>; - interrupts = <18>; - - status = "disabled"; - }; -}; - -#include "fbsd-rt3883.dtsi" diff --git a/sys/gnu/dts/mips/rt5350.dtsi b/sys/gnu/dts/mips/rt5350.dtsi deleted file mode 100644 index 05dce6d3e01..00000000000 --- a/sys/gnu/dts/mips/rt5350.dtsi +++ /dev/null @@ -1,340 +0,0 @@ -/ { - #address-cells = <1>; - #size-cells = <1>; - compatible = "ralink,rt5350-soc"; - - cpus { - cpu@0 { - compatible = "mips,mips24KEc"; - }; - }; - - chosen { - bootargs = "console=ttyS0,57600"; - }; - - cpuintc: cpuintc@0 { - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - compatible = "mti,cpu-interrupt-controller"; - }; - - aliases { - spi0 = &spi0; - spi1 = &spi1; - serial0 = &uartlite; - }; - - palmbus: palmbus@10000000 { - compatible = "palmbus"; - reg = <0x10000000 0x200000>; - ranges = <0x0 0x10000000 0x1FFFFF>; - - #address-cells = <1>; - #size-cells = <1>; - - sysc: sysc@0 { - compatible = "ralink,rt5350-sysc", "ralink,rt3050-sysc"; - reg = <0x0 0x100>; - }; - - timer: timer@100 { - compatible = "ralink,rt5350-timer", "ralink,rt2880-timer"; - reg = <0x100 0x20>; - - interrupt-parent = <&intc>; - interrupts = <1>; - }; - - watchdog: watchdog@120 { - compatible = "ralink,rt5350-wdt", "ralink,rt2880-wdt"; - reg = <0x120 0x10>; - - resets = <&rstctrl 8>; - reset-names = "wdt"; - - interrupt-parent = <&intc>; - interrupts = <1>; - }; - - intc: intc@200 { - compatible = "ralink,rt5350-intc", "ralink,rt2880-intc"; - reg = <0x200 0x100>; - - resets = <&rstctrl 19>; - reset-names = "intc"; - - interrupt-controller; - #interrupt-cells = <1>; - - interrupt-parent = <&cpuintc>; - interrupts = <2>; - }; - - memc: memc@300 { - compatible = "ralink,rt5350-memc", "ralink,rt3050-memc"; - reg = <0x300 0x100>; - - resets = <&rstctrl 20>; - reset-names = "mc"; - - interrupt-parent = <&intc>; - interrupts = <3>; - }; - - uart: uart@500 { - compatible = "ralink,rt5350-uart", "ralink,rt2880-uart", "ns16550a"; - reg = <0x500 0x100>; - - resets = <&rstctrl 12>; - reset-names = "uart"; - - interrupt-parent = <&intc>; - interrupts = <5>; - - reg-shift = <2>; - - status = "disabled"; - }; - - gpio0: gpio@600 { - compatible = "ralink,rt5350-gpio", "ralink,rt2880-gpio"; - reg = <0x600 0x34>; - - resets = <&rstctrl 13>; - reset-names = "pio"; - - interrupt-parent = <&intc>; - interrupts = <6>; - - gpio-controller; - #gpio-cells = <2>; - - ralink,gpio-base = <0>; - ralink,num-gpios = <22>; - ralink,register-map = [ 00 04 08 0c - 20 24 28 2c - 30 34 ]; - }; - - gpio1: gpio@660 { - compatible = "ralink,rt5350-gpio", "ralink,rt2880-gpio"; - reg = <0x660 0x24>; - - interrupt-parent = <&intc>; - interrupts = <6>; - - gpio-controller; - #gpio-cells = <2>; - - ralink,gpio-base = <22>; - ralink,num-gpios = <6>; - ralink,register-map = [ 00 04 08 0c - 10 14 18 1c - 20 24 ]; - - status = "disabled"; - }; - - i2c: i2c@900 { - compatible = "link,rt5350-i2c", "ralink,rt2880-i2c"; - reg = <0x900 0x100>; - - resets = <&rstctrl 16>; - reset-names = "i2c"; - - #address-cells = <1>; - #size-cells = <0>; - - pinctrl-names = "default"; - pinctrl-0 = <&i2c_pins>; - - status = "disabled"; - }; - - spi0: spi@b00 { - compatible = "ralink,rt5350-spi", "ralink,rt2880-spi"; - reg = <0xb00 0x40>; - - resets = <&rstctrl 18>; - reset-names = "spi"; - - #address-cells = <1>; - #size-cells = <0>; - - pinctrl-names = "default"; - pinctrl-0 = <&spi_pins>; - - status = "disabled"; - }; - - spi1: spi@b40 { - compatible = "ralink,rt5350-spi", "ralink,rt2880-spi"; - reg = <0xb40 0x60>; - - resets = <&rstctrl 18>; - reset-names = "spi"; - - #address-cells = <1>; - #size-cells = <0>; - - pinctrl-names = "default"; - pinctrl-0 = <&spi_cs1>; - - status = "disabled"; - }; - - uartlite: uartlite@c00 { - compatible = "ralink,rt5350-uart", "ralink,rt2880-uart", "ns16550a"; - reg = <0xc00 0x100>; - - resets = <&rstctrl 19>; - reset-names = "uartl"; - - interrupt-parent = <&intc>; - interrupts = <12>; - - pinctrl-names = "default"; - pinctrl-0 = <&uartlite_pins>; - - reg-shift = <2>; - }; - - systick: systick@d00 { - compatible = "ralink,rt5350-systick", "ralink,cevt-systick"; - reg = <0xd00 0x10>; - - interrupt-parent = <&cpuintc>; - interrupts = <7>; - }; - }; - - pinctrl: pinctrl { - compatible = "ralink,rt2880-pinmux"; - - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinctrl0 { - }; - - spi_pins: spi { - spi { - ralink,group = "spi"; - ralink,function = "spi"; - }; - }; - - i2c_pins: i2c { - i2c { - ralink,group = "i2c"; - ralink,function = "i2c"; - }; - }; - - phy_led_pins: phy_led { - phy_led { - ralink,group = "led"; - ralink,function = "led"; - }; - }; - - uartlite_pins: uartlite { - uart { - ralink,group = "uartlite"; - ralink,function = "uartlite"; - }; - }; - - uartf_pins: uartf { - uartf { - ralink,group = "uartf"; - ralink,function = "uartf"; - }; - }; - - spi_cs1: spi1 { - spi1 { - ralink,group = "spi_cs1"; - ralink,function = "spi_cs1"; - }; - }; - }; - - rstctrl: rstctrl { - compatible = "ralink,rt5350-reset", "ralink,rt2880-reset"; - #reset-cells = <1>; - }; - - clkctrl: clkctrl { - compatible = "ralink,rt2880-clock"; - #clock-cells = <1>; - }; - - usbphy: usbphy { - compatible = "ralink,rt3352-usbphy"; - #phy-cells = <1>; - - resets = <&rstctrl 22 &rstctrl 25>; - reset-names = "host", "device"; - clocks = <&clkctrl 18>; - clock-names = "host"; - }; - - ethernet: ethernet@10100000 { - compatible = "ralink,rt5350-eth"; - reg = <0x10100000 0x10000>; - - resets = <&rstctrl 21 &rstctrl 23>; - reset-names = "fe", "esw"; - - interrupt-parent = <&cpuintc>; - interrupts = <5>; - - mediatek,switch = <&esw>; - }; - - esw: esw@10110000 { - compatible = "ralink,rt5350-esw", "ralink,rt3050-esw"; - reg = <0x10110000 0x8000>; - - resets = <&rstctrl 23>; - reset-names = "esw"; - - interrupt-parent = <&intc>; - interrupts = <17>; - }; - - wmac: wmac@10180000 { - compatible = "ralink,rt5350-wmac", "ralink,rt2880-wmac"; - reg = <0x10180000 0x40000>; - - interrupt-parent = <&cpuintc>; - interrupts = <6>; - - ralink,eeprom = "soc_wmac.eeprom"; - }; - - ehci: ehci@101c0000 { - compatible = "generic-ehci"; - reg = <0x101c0000 0x1000>; - - phys = <&usbphy 1>; - phy-names = "usb"; - - interrupt-parent = <&intc>; - interrupts = <18>; - }; - - ohci: ohci@101c1000 { - compatible = "generic-ohci"; - reg = <0x101c1000 0x1000>; - - phys = <&usbphy 1>; - phy-names = "usb"; - - interrupt-parent = <&intc>; - interrupts = <18>; - }; -}; diff --git a/sys/gnu/dts/riscv/sifive/fu540-c000.dtsi b/sys/gnu/dts/riscv/sifive/fu540-c000.dtsi deleted file mode 100644 index 7db86105348..00000000000 --- a/sys/gnu/dts/riscv/sifive/fu540-c000.dtsi +++ /dev/null @@ -1,286 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* Copyright (c) 2018-2019 SiFive, Inc */ - -/dts-v1/; - -#include - -/ { - #address-cells = <2>; - #size-cells = <2>; - compatible = "sifive,fu540-c000", "sifive,fu540"; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - ethernet0 = ð0; - }; - - chosen { - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu0: cpu@0 { - compatible = "sifive,e51", "sifive,rocket0", "riscv"; - device_type = "cpu"; - i-cache-block-size = <64>; - i-cache-sets = <128>; - i-cache-size = <16384>; - reg = <0>; - riscv,isa = "rv64imac"; - status = "disabled"; - cpu0_intc: interrupt-controller { - #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; - interrupt-controller; - }; - }; - cpu1: cpu@1 { - compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; - d-cache-block-size = <64>; - d-cache-sets = <64>; - d-cache-size = <32768>; - d-tlb-sets = <1>; - d-tlb-size = <32>; - device_type = "cpu"; - i-cache-block-size = <64>; - i-cache-sets = <64>; - i-cache-size = <32768>; - i-tlb-sets = <1>; - i-tlb-size = <32>; - mmu-type = "riscv,sv39"; - reg = <1>; - riscv,isa = "rv64imafdc"; - tlb-split; - next-level-cache = <&l2cache>; - cpu1_intc: interrupt-controller { - #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; - interrupt-controller; - }; - }; - cpu2: cpu@2 { - compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; - d-cache-block-size = <64>; - d-cache-sets = <64>; - d-cache-size = <32768>; - d-tlb-sets = <1>; - d-tlb-size = <32>; - device_type = "cpu"; - i-cache-block-size = <64>; - i-cache-sets = <64>; - i-cache-size = <32768>; - i-tlb-sets = <1>; - i-tlb-size = <32>; - mmu-type = "riscv,sv39"; - reg = <2>; - riscv,isa = "rv64imafdc"; - tlb-split; - next-level-cache = <&l2cache>; - cpu2_intc: interrupt-controller { - #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; - interrupt-controller; - }; - }; - cpu3: cpu@3 { - compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; - d-cache-block-size = <64>; - d-cache-sets = <64>; - d-cache-size = <32768>; - d-tlb-sets = <1>; - d-tlb-size = <32>; - device_type = "cpu"; - i-cache-block-size = <64>; - i-cache-sets = <64>; - i-cache-size = <32768>; - i-tlb-sets = <1>; - i-tlb-size = <32>; - mmu-type = "riscv,sv39"; - reg = <3>; - riscv,isa = "rv64imafdc"; - tlb-split; - next-level-cache = <&l2cache>; - cpu3_intc: interrupt-controller { - #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; - interrupt-controller; - }; - }; - cpu4: cpu@4 { - compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; - d-cache-block-size = <64>; - d-cache-sets = <64>; - d-cache-size = <32768>; - d-tlb-sets = <1>; - d-tlb-size = <32>; - device_type = "cpu"; - i-cache-block-size = <64>; - i-cache-sets = <64>; - i-cache-size = <32768>; - i-tlb-sets = <1>; - i-tlb-size = <32>; - mmu-type = "riscv,sv39"; - reg = <4>; - riscv,isa = "rv64imafdc"; - tlb-split; - next-level-cache = <&l2cache>; - cpu4_intc: interrupt-controller { - #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; - interrupt-controller; - }; - }; - }; - soc { - #address-cells = <2>; - #size-cells = <2>; - compatible = "sifive,fu540-c000", "sifive,fu540", "simple-bus"; - ranges; - plic0: interrupt-controller@c000000 { - #interrupt-cells = <1>; - compatible = "sifive,plic-1.0.0"; - reg = <0x0 0xc000000 0x0 0x4000000>; - riscv,ndev = <53>; - interrupt-controller; - interrupts-extended = < - &cpu0_intc 0xffffffff - &cpu1_intc 0xffffffff &cpu1_intc 9 - &cpu2_intc 0xffffffff &cpu2_intc 9 - &cpu3_intc 0xffffffff &cpu3_intc 9 - &cpu4_intc 0xffffffff &cpu4_intc 9>; - }; - prci: clock-controller@10000000 { - compatible = "sifive,fu540-c000-prci"; - reg = <0x0 0x10000000 0x0 0x1000>; - clocks = <&hfclk>, <&rtcclk>; - #clock-cells = <1>; - }; - uart0: serial@10010000 { - compatible = "sifive,fu540-c000-uart", "sifive,uart0"; - reg = <0x0 0x10010000 0x0 0x1000>; - interrupt-parent = <&plic0>; - interrupts = <4>; - clocks = <&prci PRCI_CLK_TLCLK>; - status = "disabled"; - }; - dma: dma@3000000 { - compatible = "sifive,fu540-c000-pdma"; - reg = <0x0 0x3000000 0x0 0x8000>; - interrupt-parent = <&plic0>; - interrupts = <23 24 25 26 27 28 29 30>; - #dma-cells = <1>; - }; - uart1: serial@10011000 { - compatible = "sifive,fu540-c000-uart", "sifive,uart0"; - reg = <0x0 0x10011000 0x0 0x1000>; - interrupt-parent = <&plic0>; - interrupts = <5>; - clocks = <&prci PRCI_CLK_TLCLK>; - status = "disabled"; - }; - i2c0: i2c@10030000 { - compatible = "sifive,fu540-c000-i2c", "sifive,i2c0"; - reg = <0x0 0x10030000 0x0 0x1000>; - interrupt-parent = <&plic0>; - interrupts = <50>; - clocks = <&prci PRCI_CLK_TLCLK>; - reg-shift = <2>; - reg-io-width = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - qspi0: spi@10040000 { - compatible = "sifive,fu540-c000-spi", "sifive,spi0"; - reg = <0x0 0x10040000 0x0 0x1000 - 0x0 0x20000000 0x0 0x10000000>; - interrupt-parent = <&plic0>; - interrupts = <51>; - clocks = <&prci PRCI_CLK_TLCLK>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - qspi1: spi@10041000 { - compatible = "sifive,fu540-c000-spi", "sifive,spi0"; - reg = <0x0 0x10041000 0x0 0x1000 - 0x0 0x30000000 0x0 0x10000000>; - interrupt-parent = <&plic0>; - interrupts = <52>; - clocks = <&prci PRCI_CLK_TLCLK>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - qspi2: spi@10050000 { - compatible = "sifive,fu540-c000-spi", "sifive,spi0"; - reg = <0x0 0x10050000 0x0 0x1000>; - interrupt-parent = <&plic0>; - interrupts = <6>; - clocks = <&prci PRCI_CLK_TLCLK>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - eth0: ethernet@10090000 { - compatible = "sifive,fu540-c000-gem"; - interrupt-parent = <&plic0>; - interrupts = <53>; - reg = <0x0 0x10090000 0x0 0x2000 - 0x0 0x100a0000 0x0 0x1000>; - local-mac-address = [00 00 00 00 00 00]; - clock-names = "pclk", "hclk"; - clocks = <&prci PRCI_CLK_GEMGXLPLL>, - <&prci PRCI_CLK_GEMGXLPLL>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - pwm0: pwm@10020000 { - compatible = "sifive,fu540-c000-pwm", "sifive,pwm0"; - reg = <0x0 0x10020000 0x0 0x1000>; - interrupt-parent = <&plic0>; - interrupts = <42 43 44 45>; - clocks = <&prci PRCI_CLK_TLCLK>; - #pwm-cells = <3>; - status = "disabled"; - }; - pwm1: pwm@10021000 { - compatible = "sifive,fu540-c000-pwm", "sifive,pwm0"; - reg = <0x0 0x10021000 0x0 0x1000>; - interrupt-parent = <&plic0>; - interrupts = <46 47 48 49>; - clocks = <&prci PRCI_CLK_TLCLK>; - #pwm-cells = <3>; - status = "disabled"; - }; - l2cache: cache-controller@2010000 { - compatible = "sifive,fu540-c000-ccache", "cache"; - cache-block-size = <64>; - cache-level = <2>; - cache-sets = <1024>; - cache-size = <2097152>; - cache-unified; - interrupt-parent = <&plic0>; - interrupts = <1 2 3>; - reg = <0x0 0x2010000 0x0 0x1000>; - }; - gpio: gpio@10060000 { - compatible = "sifive,fu540-c000-gpio", "sifive,gpio0"; - interrupt-parent = <&plic0>; - interrupts = <7>, <8>, <9>, <10>, <11>, <12>, <13>, - <14>, <15>, <16>, <17>, <18>, <19>, <20>, - <21>, <22>; - reg = <0x0 0x10060000 0x0 0x1000>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&prci PRCI_CLK_TLCLK>; - status = "disabled"; - }; - }; -}; diff --git a/sys/gnu/dts/riscv/sifive/hifive-unleashed-a00.dts b/sys/gnu/dts/riscv/sifive/hifive-unleashed-a00.dts deleted file mode 100644 index 4a2729f5ca3..00000000000 --- a/sys/gnu/dts/riscv/sifive/hifive-unleashed-a00.dts +++ /dev/null @@ -1,105 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* Copyright (c) 2018-2019 SiFive, Inc */ - -#include "fu540-c000.dtsi" -#include - -/* Clock frequency (in Hz) of the PCB crystal for rtcclk */ -#define RTCCLK_FREQ 1000000 - -/ { - #address-cells = <2>; - #size-cells = <2>; - model = "SiFive HiFive Unleashed A00"; - compatible = "sifive,hifive-unleashed-a00", "sifive,fu540-c000"; - - chosen { - stdout-path = "serial0"; - }; - - cpus { - timebase-frequency = ; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x0 0x80000000 0x2 0x00000000>; - }; - - soc { - }; - - hfclk: hfclk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <33333333>; - clock-output-names = "hfclk"; - }; - - rtcclk: rtcclk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = ; - clock-output-names = "rtcclk"; - }; - gpio-restart { - compatible = "gpio-restart"; - gpios = <&gpio 10 GPIO_ACTIVE_LOW>; - }; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; -}; - -&qspi0 { - status = "okay"; - flash@0 { - compatible = "issi,is25wp256", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <50000000>; - m25p,fast-read; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - }; -}; - -&qspi2 { - status = "okay"; - mmc@0 { - compatible = "mmc-spi-slot"; - reg = <0>; - spi-max-frequency = <20000000>; - voltage-ranges = <3300 3300>; - disable-wp; - }; -}; - -ð0 { - status = "okay"; - phy-mode = "gmii"; - phy-handle = <&phy0>; - phy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -&pwm0 { - status = "okay"; -}; - -&pwm1 { - status = "okay"; -}; - -&gpio { - status = "okay"; -}; diff --git a/sys/i386/bios/apm.c b/sys/i386/bios/apm.c deleted file mode 100644 index 6cbe675dbed..00000000000 --- a/sys/i386/bios/apm.c +++ /dev/null @@ -1,1536 +0,0 @@ -/*- - * APM (Advanced Power Management) BIOS Device Driver - * - * Copyright (c) 1994 UKAI, Fumitoshi. - * Copyright (c) 1994-1995 by HOSOKAWA, Tatsumi - * Copyright (c) 1996 Nate Williams - * Copyright (c) 1997 Poul-Henning Kamp - * - * This software may be used, modified, copied, and distributed, in - * both source and binary form provided that the above copyright and - * these terms are retained. Under no circumstances is the author - * responsible for the proper functioning of this software, nor does - * the author assume any responsibility for damages incurred with its - * use. - * - * Sep, 1994 Implemented on FreeBSD 1.1.5.1R (Toshiba AVS001WD) - */ - -/*- - * Copyright (c) 2000 Mitsuru IWASAKI - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include -#include -#include - -#include -#include - -/* Used by the apm_saver screen saver module */ -int apm_display(int newstate); -struct apm_softc apm_softc; - -static void apm_resume(void); -static int apm_bioscall(void); -static int apm_check_function_supported(u_int version, u_int func); - -static int apm_pm_func(u_long, void*, ...); - -static u_long apm_version; - -int apm_evindex; - -#define SCFLAG_ONORMAL 0x0000001 -#define SCFLAG_OCTL 0x0000002 -#define SCFLAG_OPEN (SCFLAG_ONORMAL|SCFLAG_OCTL) - -#define APMDEV_NORMAL 0 -#define APMDEV_CTL 1 - -static struct apmhook *hook[NAPM_HOOK]; /* XXX */ - -#define is_enabled(foo) ((foo) ? "enabled" : "disabled") - -/* Map version number to integer (keeps ordering of version numbers) */ -#define INTVERSION(major, minor) ((major)*100 + (minor)) - -static d_open_t apmopen; -static d_close_t apmclose; -static d_write_t apmwrite; -static d_ioctl_t apmioctl; -static d_poll_t apmpoll; - -static struct cdevsw apm_cdevsw = { - .d_version = D_VERSION, - .d_flags = D_NEEDGIANT, - .d_open = apmopen, - .d_close = apmclose, - .d_write = apmwrite, - .d_ioctl = apmioctl, - .d_poll = apmpoll, - .d_name = "apm", -}; - -static int apm_suspend_delay = 1; -static int apm_standby_delay = 1; -static int apm_swab_batt_minutes = 0; -static int apm_debug = 0; - -#define APM_DPRINT(args...) do { \ - if (apm_debug) { \ - printf(args); \ - } \ -} while (0) - -SYSCTL_INT(_machdep, OID_AUTO, apm_suspend_delay, CTLFLAG_RW, &apm_suspend_delay, 1, ""); -SYSCTL_INT(_machdep, OID_AUTO, apm_standby_delay, CTLFLAG_RW, &apm_standby_delay, 1, ""); -SYSCTL_INT(_debug, OID_AUTO, apm_debug, CTLFLAG_RW, &apm_debug, 0, ""); - -SYSCTL_INT(_machdep, OID_AUTO, apm_swab_batt_minutes, CTLFLAG_RWTUN, - &apm_swab_batt_minutes, 0, "Byte swap battery time value."); - -/* - * return 0 if the function successfull, - * return 1 if the function unsuccessfull, - * return -1 if the function unsupported. - */ -static int -apm_bioscall(void) -{ - struct apm_softc *sc = &apm_softc; - int errno = 0; - u_int apm_func = sc->bios.r.eax & 0xff; - - if (!apm_check_function_supported(sc->intversion, apm_func)) { - APM_DPRINT("apm_bioscall: function 0x%x is not supported in v%d.%d\n", - apm_func, sc->majorversion, sc->minorversion); - return (-1); - } - - sc->bios_busy = 1; - if (sc->connectmode == APM_PROT32CONNECT) { - set_bios_selectors(&sc->bios.seg, - BIOSCODE_FLAG | BIOSDATA_FLAG); - errno = bios32(&sc->bios.r, - sc->bios.entry, GSEL(GBIOSCODE32_SEL, SEL_KPL)); - } else { - errno = bios16(&sc->bios, NULL); - } - sc->bios_busy = 0; - return (errno); -} - -/* check whether APM function is supported (1) or not (0). */ -static int -apm_check_function_supported(u_int version, u_int func) -{ - /* except driver version */ - if (func == APM_DRVVERSION) { - return (1); - } - - switch (version) { - case INTVERSION(1, 0): - if (func > APM_GETPMEVENT) { - return (0); /* not supported */ - } - break; - case INTVERSION(1, 1): - if (func > APM_ENGAGEDISENGAGEPM && - func < APM_OEMFUNC) { - return (0); /* not supported */ - } - break; - case INTVERSION(1, 2): - break; - } - - return (1); /* supported */ -} - -/* enable/disable power management */ -static int -apm_enable_disable_pm(int enable) -{ - struct apm_softc *sc = &apm_softc; - - sc->bios.r.eax = (APM_BIOS << 8) | APM_ENABLEDISABLEPM; - - if (sc->intversion >= INTVERSION(1, 1)) - sc->bios.r.ebx = PMDV_ALLDEV; - else - sc->bios.r.ebx = 0xffff; /* APM version 1.0 only */ - sc->bios.r.ecx = enable; - sc->bios.r.edx = 0; - return (apm_bioscall()); -} - -/* register driver version (APM 1.1 or later) */ -static int -apm_driver_version(int version) -{ - struct apm_softc *sc = &apm_softc; - - sc->bios.r.eax = (APM_BIOS << 8) | APM_DRVVERSION; - sc->bios.r.ebx = 0x0; - sc->bios.r.ecx = version; - sc->bios.r.edx = 0; - - if (apm_bioscall() == 0 && sc->bios.r.eax == version) - return (0); - - /* Some old BIOSes don't return the connection version in %ax. */ - if (sc->bios.r.eax == ((APM_BIOS << 8) | APM_DRVVERSION)) - return (0); - - return (1); -} - -/* engage/disengage power management (APM 1.1 or later) */ -static int -apm_engage_disengage_pm(int engage) -{ - struct apm_softc *sc = &apm_softc; - - sc->bios.r.eax = (APM_BIOS << 8) | APM_ENGAGEDISENGAGEPM; - sc->bios.r.ebx = PMDV_ALLDEV; - sc->bios.r.ecx = engage; - sc->bios.r.edx = 0; - return (apm_bioscall()); -} - -/* get PM event */ -static u_int -apm_getevent(void) -{ - struct apm_softc *sc = &apm_softc; - - sc->bios.r.eax = (APM_BIOS << 8) | APM_GETPMEVENT; - - sc->bios.r.ebx = 0; - sc->bios.r.ecx = 0; - sc->bios.r.edx = 0; - if (apm_bioscall()) - return (PMEV_NOEVENT); - return (sc->bios.r.ebx & 0xffff); -} - -/* suspend entire system */ -static int -apm_suspend_system(int state) -{ - struct apm_softc *sc = &apm_softc; - - sc->bios.r.eax = (APM_BIOS << 8) | APM_SETPWSTATE; - sc->bios.r.ebx = PMDV_ALLDEV; - sc->bios.r.ecx = state; - sc->bios.r.edx = 0; - - if (apm_bioscall()) { - printf("Entire system suspend failure: errcode = %d\n", - 0xff & (sc->bios.r.eax >> 8)); - return 1; - } - - return 0; -} - -/* Display control */ -/* - * Experimental implementation: My laptop machine can't handle this function - * If your laptop can control the display via APM, please inform me. - * HOSOKAWA, Tatsumi - */ -int -apm_display(int newstate) -{ - struct apm_softc *sc = &apm_softc; - - sc->bios.r.eax = (APM_BIOS << 8) | APM_SETPWSTATE; - sc->bios.r.ebx = PMDV_DISP0; - sc->bios.r.ecx = newstate ? PMST_APMENABLED:PMST_SUSPEND; - sc->bios.r.edx = 0; - if (apm_bioscall() == 0) { - return 0; - } - - /* If failed, then try to blank all display devices instead. */ - sc->bios.r.eax = (APM_BIOS << 8) | APM_SETPWSTATE; - sc->bios.r.ebx = PMDV_DISPALL; /* all display devices */ - sc->bios.r.ecx = newstate ? PMST_APMENABLED:PMST_SUSPEND; - sc->bios.r.edx = 0; - if (apm_bioscall() == 0) { - return 0; - } - printf("Display off failure: errcode = %d\n", - 0xff & (sc->bios.r.eax >> 8)); - return 1; -} - -/* - * Turn off the entire system. - */ -static void -apm_power_off(void *junk, int howto) -{ - struct apm_softc *sc = &apm_softc; - - /* Not halting powering off, or not active */ - if (!(howto & RB_POWEROFF) || !apm_softc.active) - return; - sc->bios.r.eax = (APM_BIOS << 8) | APM_SETPWSTATE; - sc->bios.r.ebx = PMDV_ALLDEV; - sc->bios.r.ecx = PMST_OFF; - sc->bios.r.edx = 0; - (void) apm_bioscall(); -} - -/* APM Battery low handler */ -static void -apm_battery_low(void) -{ - printf("\007\007 * * * BATTERY IS LOW * * * \007\007"); -} - -/* APM hook manager */ -static struct apmhook * -apm_add_hook(struct apmhook **list, struct apmhook *ah) -{ - struct apmhook *p, *prev; - - APM_DPRINT("Add hook \"%s\"\n", ah->ah_name); - - if (ah == NULL) - panic("illegal apm_hook!"); - prev = NULL; - for (p = *list; p != NULL; prev = p, p = p->ah_next) - if (p->ah_order > ah->ah_order) - break; - - if (prev == NULL) { - ah->ah_next = *list; - *list = ah; - } else { - ah->ah_next = prev->ah_next; - prev->ah_next = ah; - } - return ah; -} - -static void -apm_del_hook(struct apmhook **list, struct apmhook *ah) -{ - struct apmhook *p, *prev; - - prev = NULL; - for (p = *list; p != NULL; prev = p, p = p->ah_next) - if (p == ah) - goto deleteit; - panic("Tried to delete unregistered apm_hook."); - return; -deleteit: - if (prev != NULL) - prev->ah_next = p->ah_next; - else - *list = p->ah_next; -} - - -/* APM driver calls some functions automatically */ -static void -apm_execute_hook(struct apmhook *list) -{ - struct apmhook *p; - - for (p = list; p != NULL; p = p->ah_next) { - APM_DPRINT("Execute APM hook \"%s.\"\n", p->ah_name); - if ((*(p->ah_fun))(p->ah_arg)) - printf("Warning: APM hook \"%s\" failed", p->ah_name); - } -} - - -/* establish an apm hook */ -struct apmhook * -apm_hook_establish(int apmh, struct apmhook *ah) -{ - if (apmh < 0 || apmh >= NAPM_HOOK) - return NULL; - - return apm_add_hook(&hook[apmh], ah); -} - -/* disestablish an apm hook */ -void -apm_hook_disestablish(int apmh, struct apmhook *ah) -{ - if (apmh < 0 || apmh >= NAPM_HOOK) - return; - - apm_del_hook(&hook[apmh], ah); -} - -static int apm_record_event(struct apm_softc *, u_int); -static void apm_processevent(void); - -static u_int apm_op_inprog = 0; - -static void -apm_do_suspend(void) -{ - struct apm_softc *sc = &apm_softc; - int error; - - if (sc == NULL || sc->initialized == 0) - return; - - apm_op_inprog = 0; - sc->suspends = sc->suspend_countdown = 0; - - EVENTHANDLER_INVOKE(power_suspend); - - /* - * Be sure to hold Giant across DEVICE_SUSPEND/RESUME since - * non-MPSAFE drivers need this. - */ - mtx_lock(&Giant); - error = DEVICE_SUSPEND(root_bus); - if (error) - goto backout; - - apm_execute_hook(hook[APM_HOOK_SUSPEND]); - if (apm_suspend_system(PMST_SUSPEND) == 0) { - sc->suspending = 1; - apm_processevent(); - mtx_unlock(&Giant); - return; - } - - /* Failure, 'resume' the system again */ - apm_execute_hook(hook[APM_HOOK_RESUME]); - DEVICE_RESUME(root_bus); -backout: - mtx_unlock(&Giant); - EVENTHANDLER_INVOKE(power_resume); -} - -static void -apm_do_standby(void) -{ - struct apm_softc *sc = &apm_softc; - - if (sc == NULL || sc->initialized == 0) - return; - - apm_op_inprog = 0; - sc->standbys = sc->standby_countdown = 0; - - /* - * As far as standby, we don't need to execute - * all of suspend hooks. - */ - if (apm_suspend_system(PMST_STANDBY) == 0) - apm_processevent(); - return; -} - -static void -apm_lastreq_notify(void) -{ - struct apm_softc *sc = &apm_softc; - - sc->bios.r.eax = (APM_BIOS << 8) | APM_SETPWSTATE; - sc->bios.r.ebx = PMDV_ALLDEV; - sc->bios.r.ecx = PMST_LASTREQNOTIFY; - sc->bios.r.edx = 0; - apm_bioscall(); -} - -static int -apm_lastreq_rejected(void) -{ - struct apm_softc *sc = &apm_softc; - - if (apm_op_inprog == 0) { - return 1; /* no operation in progress */ - } - - sc->bios.r.eax = (APM_BIOS << 8) | APM_SETPWSTATE; - sc->bios.r.ebx = PMDV_ALLDEV; - sc->bios.r.ecx = PMST_LASTREQREJECT; - sc->bios.r.edx = 0; - - if (apm_bioscall()) { - APM_DPRINT("apm_lastreq_rejected: failed\n"); - return 1; - } - apm_op_inprog = 0; - return 0; -} - -/* - * Public interface to the suspend/resume: - * - * Execute suspend and resume hook before and after sleep, respectively. - * - */ - -void -apm_suspend(int state) -{ - struct apm_softc *sc = &apm_softc; - - if (sc == NULL || sc->initialized == 0) - return; - - switch (state) { - case PMST_SUSPEND: - if (sc->suspends) - return; - sc->suspends++; - sc->suspend_countdown = apm_suspend_delay; - break; - case PMST_STANDBY: - if (sc->standbys) - return; - sc->standbys++; - sc->standby_countdown = apm_standby_delay; - break; - default: - printf("apm_suspend: Unknown Suspend state 0x%x\n", state); - return; - } - - apm_op_inprog++; - apm_lastreq_notify(); -} - -static void -apm_resume(void) -{ - struct apm_softc *sc = &apm_softc; - - if (sc == NULL || sc->initialized == 0 || sc->suspending == 0) - return; - - sc->suspending = 0; - apm_execute_hook(hook[APM_HOOK_RESUME]); - mtx_lock(&Giant); - DEVICE_RESUME(root_bus); - mtx_unlock(&Giant); - EVENTHANDLER_INVOKE(power_resume); -} - - -/* get power status per battery */ -static int -apm_get_pwstatus(apm_pwstatus_t app) -{ - struct apm_softc *sc = &apm_softc; - - if (app->ap_device != PMDV_ALLDEV && - (app->ap_device < PMDV_BATT0 || app->ap_device > PMDV_BATT_ALL)) - return 1; - - sc->bios.r.eax = (APM_BIOS << 8) | APM_GETPWSTATUS; - sc->bios.r.ebx = app->ap_device; - sc->bios.r.ecx = 0; - sc->bios.r.edx = 0xffff; /* default to unknown battery time */ - - if (apm_bioscall()) - return 1; - - app->ap_acline = (sc->bios.r.ebx >> 8) & 0xff; - app->ap_batt_stat = sc->bios.r.ebx & 0xff; - app->ap_batt_flag = (sc->bios.r.ecx >> 8) & 0xff; - app->ap_batt_life = sc->bios.r.ecx & 0xff; - sc->bios.r.edx &= 0xffff; - if (apm_swab_batt_minutes) - sc->bios.r.edx = __bswap16(sc->bios.r.edx) | 0x8000; - if (sc->bios.r.edx == 0xffff) /* Time is unknown */ - app->ap_batt_time = -1; - else if (sc->bios.r.edx & 0x8000) /* Time is in minutes */ - app->ap_batt_time = (sc->bios.r.edx & 0x7fff) * 60; - else /* Time is in seconds */ - app->ap_batt_time = sc->bios.r.edx; - - return 0; -} - - -/* get APM information */ -static int -apm_get_info(apm_info_t aip) -{ - struct apm_softc *sc = &apm_softc; - struct apm_pwstatus aps; - - bzero(&aps, sizeof(aps)); - aps.ap_device = PMDV_ALLDEV; - if (apm_get_pwstatus(&aps)) - return 1; - - aip->ai_infoversion = 1; - aip->ai_acline = aps.ap_acline; - aip->ai_batt_stat = aps.ap_batt_stat; - aip->ai_batt_life = aps.ap_batt_life; - aip->ai_batt_time = aps.ap_batt_time; - aip->ai_major = (u_int)sc->majorversion; - aip->ai_minor = (u_int)sc->minorversion; - aip->ai_status = (u_int)sc->active; - - sc->bios.r.eax = (APM_BIOS << 8) | APM_GETCAPABILITIES; - sc->bios.r.ebx = 0; - sc->bios.r.ecx = 0; - sc->bios.r.edx = 0; - if (apm_bioscall()) { - aip->ai_batteries = 0xffffffff; /* Unknown */ - aip->ai_capabilities = 0xff00; /* Unknown, with no bits set */ - } else { - aip->ai_batteries = sc->bios.r.ebx & 0xff; - aip->ai_capabilities = sc->bios.r.ecx & 0xff; - } - - bzero(aip->ai_spare, sizeof aip->ai_spare); - - return 0; -} - - -/* inform APM BIOS that CPU is idle */ -void -apm_cpu_idle(void) -{ - struct apm_softc *sc = &apm_softc; - - if (sc->active) { - - sc->bios.r.eax = (APM_BIOS <<8) | APM_CPUIDLE; - sc->bios.r.edx = sc->bios.r.ecx = sc->bios.r.ebx = 0; - (void) apm_bioscall(); - } - /* - * Some APM implementation halts CPU in BIOS, whenever - * "CPU-idle" function are invoked, but swtch() of - * FreeBSD halts CPU, therefore, CPU is halted twice - * in the sched loop. It makes the interrupt latency - * terribly long and be able to cause a serious problem - * in interrupt processing. We prevent it by removing - * "hlt" operation from swtch() and managed it under - * APM driver. - */ - if (!sc->active || sc->always_halt_cpu) - halt(); /* wait for interrupt */ -} - -/* inform APM BIOS that CPU is busy */ -void -apm_cpu_busy(void) -{ - struct apm_softc *sc = &apm_softc; - - /* - * The APM specification says this is only necessary if your BIOS - * slows down the processor in the idle task, otherwise it's not - * necessary. - */ - if (sc->slow_idle_cpu && sc->active) { - - sc->bios.r.eax = (APM_BIOS <<8) | APM_CPUBUSY; - sc->bios.r.edx = sc->bios.r.ecx = sc->bios.r.ebx = 0; - apm_bioscall(); - } -} - - -/* - * APM thread loop. - * - * This routine wakes up from time to time to deal with delaying the - * suspend of the system, or other events. - */ -static void -apm_event_thread(void *arg) -{ - struct apm_softc *sc = &apm_softc; - - sc->running = 1; - while (sc->active) { - if (apm_op_inprog) - apm_lastreq_notify(); - if (sc->standbys && sc->standby_countdown-- <= 0) - apm_do_standby(); - if (sc->suspends && sc->suspend_countdown-- <= 0) - apm_do_suspend(); - if (!sc->bios_busy) - apm_processevent(); - mtx_lock(&sc->mtx); - cv_timedwait(&sc->cv, &sc->mtx, 10 * hz / 9); - mtx_unlock(&sc->mtx); - } - sc->running = 0; - kproc_exit(0); -} - -/* enable APM BIOS */ -static void -apm_event_enable(void) -{ - struct apm_softc *sc = &apm_softc; - - APM_DPRINT("called apm_event_enable()\n"); - - if (sc == NULL || sc->initialized == 0) - return; - - /* Start the thread */ - sc->active = 1; - if (kproc_create(apm_event_thread, sc, &sc->event_thread, 0, 0, - "apm worker")) - panic("Cannot create apm worker thread"); - - return; -} - -/* disable APM BIOS */ -static void -apm_event_disable(void) -{ - struct apm_softc *sc = &apm_softc; - - APM_DPRINT("called apm_event_disable()\n"); - - if (sc == NULL || sc->initialized == 0) - return; - - mtx_lock(&sc->mtx); - sc->active = 0; - while (sc->running) { - cv_broadcast(&sc->cv); - msleep(sc->event_thread, &sc->mtx, PWAIT, "apmdie", 0); - } - mtx_unlock(&sc->mtx); - sc->event_thread = NULL; - return; -} - -/* halt CPU in scheduling loop */ -static void -apm_halt_cpu(void) -{ - struct apm_softc *sc = &apm_softc; - - if (sc == NULL || sc->initialized == 0) - return; - - sc->always_halt_cpu = 1; - - return; -} - -/* don't halt CPU in scheduling loop */ -static void -apm_not_halt_cpu(void) -{ - struct apm_softc *sc = &apm_softc; - - if (sc == NULL || sc->initialized == 0) - return; - - sc->always_halt_cpu = 0; - - return; -} - -/* device driver definitions */ - -/* - * Module event - */ - -static int -apm_modevent(struct module *mod, int event, void *junk) -{ - - switch (event) { - case MOD_LOAD: - if (!cold) - return (EPERM); - break; - case MOD_UNLOAD: - if (!cold && power_pm_get_type() == POWER_PM_TYPE_APM) - return (EBUSY); - break; - default: - break; - } - - return (0); -} - -/* - * Create "connection point" - */ -static void -apm_identify(driver_t *driver, device_t parent) -{ - device_t child; - - if (!cold) { - printf("Don't load this driver from userland!!\n"); - return; - } - - if (resource_disabled("apm", 0)) - return; - - child = BUS_ADD_CHILD(parent, 0, "apm", 0); - if (child == NULL) - panic("apm_identify"); -} - -/* - * probe for APM BIOS - */ -static int -apm_probe(device_t dev) -{ -#define APM_KERNBASE KERNBASE - struct vm86frame vmf; - struct apm_softc *sc = &apm_softc; - - device_set_desc(dev, "APM BIOS"); - if (device_get_unit(dev) > 0) { - printf("apm: Only one APM driver supported.\n"); - return ENXIO; - } - - if (power_pm_get_type() != POWER_PM_TYPE_NONE && - power_pm_get_type() != POWER_PM_TYPE_APM) { - printf("apm: Other PM system enabled.\n"); - return ENXIO; - } - - bzero(&vmf, sizeof(struct vm86frame)); /* safety */ - bzero(&apm_softc, sizeof(apm_softc)); - vmf.vmf_ah = APM_BIOS; - vmf.vmf_al = APM_INSTCHECK; - vmf.vmf_bx = 0; - if (vm86_intcall(APM_INT, &vmf)) - return ENXIO; /* APM not found */ - if (vmf.vmf_bx != 0x504d) { - printf("apm: incorrect signature (0x%x)\n", vmf.vmf_bx); - return ENXIO; - } - if ((vmf.vmf_cx & (APM_32BIT_SUPPORT | APM_16BIT_SUPPORT)) == 0) { - printf("apm: protected mode connections are not supported\n"); - return ENXIO; - } - - apm_version = vmf.vmf_ax; - sc->slow_idle_cpu = ((vmf.vmf_cx & APM_CPUIDLE_SLOW) != 0); - sc->disabled = ((vmf.vmf_cx & APM_DISABLED) != 0); - sc->disengaged = ((vmf.vmf_cx & APM_DISENGAGED) != 0); - - vmf.vmf_ah = APM_BIOS; - vmf.vmf_al = APM_DISCONNECT; - vmf.vmf_bx = 0; - vm86_intcall(APM_INT, &vmf); /* disconnect, just in case */ - - if ((vmf.vmf_cx & APM_32BIT_SUPPORT) != 0) { - vmf.vmf_ah = APM_BIOS; - vmf.vmf_al = APM_PROT32CONNECT; - vmf.vmf_bx = 0; - if (vm86_intcall(APM_INT, &vmf)) { - printf("apm: 32-bit connection error.\n"); - return (ENXIO); - } - sc->bios.seg.code32.base = (vmf.vmf_ax << 4) + APM_KERNBASE; - sc->bios.seg.code32.limit = 0xffff; - sc->bios.seg.code16.base = (vmf.vmf_cx << 4) + APM_KERNBASE; - sc->bios.seg.code16.limit = 0xffff; - sc->bios.seg.data.base = (vmf.vmf_dx << 4) + APM_KERNBASE; - sc->bios.seg.data.limit = 0xffff; - sc->bios.entry = vmf.vmf_ebx; - sc->connectmode = APM_PROT32CONNECT; - } else { - /* use 16-bit connection */ - vmf.vmf_ah = APM_BIOS; - vmf.vmf_al = APM_PROT16CONNECT; - vmf.vmf_bx = 0; - if (vm86_intcall(APM_INT, &vmf)) { - printf("apm: 16-bit connection error.\n"); - return (ENXIO); - } - sc->bios.seg.code16.base = (vmf.vmf_ax << 4) + APM_KERNBASE; - sc->bios.seg.code16.limit = 0xffff; - sc->bios.seg.data.base = (vmf.vmf_cx << 4) + APM_KERNBASE; - sc->bios.seg.data.limit = 0xffff; - sc->bios.entry = vmf.vmf_bx; - sc->connectmode = APM_PROT16CONNECT; - } - - return(0); -} - - -/* - * return 0 if the user will notice and handle the event, - * return 1 if the kernel driver should do so. - */ -static int -apm_record_event(struct apm_softc *sc, u_int event_type) -{ - struct apm_event_info *evp; - - if ((sc->sc_flags & SCFLAG_OPEN) == 0) - return 1; /* no user waiting */ - if (sc->event_count == APM_NEVENTS) - return 1; /* overflow */ - if (sc->event_filter[event_type] == 0) - return 1; /* not registered */ - evp = &sc->event_list[sc->event_ptr]; - sc->event_count++; - sc->event_ptr++; - sc->event_ptr %= APM_NEVENTS; - evp->type = event_type; - evp->index = ++apm_evindex; - selwakeuppri(&sc->sc_rsel, PZERO); - return (sc->sc_flags & SCFLAG_OCTL) ? 0 : 1; /* user may handle */ -} - -/* Power profile */ -static void -apm_power_profile(struct apm_softc *sc) -{ - int state; - struct apm_info info; - static int apm_acline = 0; - - if (apm_get_info(&info)) - return; - - if (apm_acline != info.ai_acline) { - apm_acline = info.ai_acline; - state = apm_acline ? POWER_PROFILE_PERFORMANCE : POWER_PROFILE_ECONOMY; - power_profile_set_state(state); - } -} - -/* Process APM event */ -static void -apm_processevent(void) -{ - int apm_event; - struct apm_softc *sc = &apm_softc; - -#define OPMEV_DEBUGMESSAGE(symbol) case symbol: \ - APM_DPRINT("Received APM Event: " #symbol "\n"); - - do { - apm_event = apm_getevent(); - switch (apm_event) { - OPMEV_DEBUGMESSAGE(PMEV_STANDBYREQ); - if (apm_op_inprog == 0) { - apm_op_inprog++; - if (apm_record_event(sc, apm_event)) { - apm_suspend(PMST_STANDBY); - } - } - break; - OPMEV_DEBUGMESSAGE(PMEV_USERSTANDBYREQ); - if (apm_op_inprog == 0) { - apm_op_inprog++; - if (apm_record_event(sc, apm_event)) { - apm_suspend(PMST_STANDBY); - } - } - break; - OPMEV_DEBUGMESSAGE(PMEV_SUSPENDREQ); - apm_lastreq_notify(); - if (apm_op_inprog == 0) { - apm_op_inprog++; - if (apm_record_event(sc, apm_event)) { - apm_do_suspend(); - } - } - return; /* XXX skip the rest */ - OPMEV_DEBUGMESSAGE(PMEV_USERSUSPENDREQ); - apm_lastreq_notify(); - if (apm_op_inprog == 0) { - apm_op_inprog++; - if (apm_record_event(sc, apm_event)) { - apm_do_suspend(); - } - } - return; /* XXX skip the rest */ - OPMEV_DEBUGMESSAGE(PMEV_CRITSUSPEND); - apm_do_suspend(); - break; - OPMEV_DEBUGMESSAGE(PMEV_NORMRESUME); - apm_record_event(sc, apm_event); - apm_resume(); - break; - OPMEV_DEBUGMESSAGE(PMEV_CRITRESUME); - apm_record_event(sc, apm_event); - apm_resume(); - break; - OPMEV_DEBUGMESSAGE(PMEV_STANDBYRESUME); - apm_record_event(sc, apm_event); - break; - OPMEV_DEBUGMESSAGE(PMEV_BATTERYLOW); - if (apm_record_event(sc, apm_event)) { - apm_battery_low(); - apm_suspend(PMST_SUSPEND); - } - break; - OPMEV_DEBUGMESSAGE(PMEV_POWERSTATECHANGE); - apm_record_event(sc, apm_event); - apm_power_profile(sc); - break; - OPMEV_DEBUGMESSAGE(PMEV_UPDATETIME); - apm_record_event(sc, apm_event); - inittodr(0); /* adjust time to RTC */ - break; - OPMEV_DEBUGMESSAGE(PMEV_CAPABILITIESCHANGE); - apm_record_event(sc, apm_event); - apm_power_profile(sc); - break; - case PMEV_NOEVENT: - break; - default: - printf("Unknown Original APM Event 0x%x\n", apm_event); - break; - } - } while (apm_event != PMEV_NOEVENT); -} - -static struct timeval suspend_time; -static struct timeval diff_time; - -static int -apm_rtc_suspend(void *arg __unused) -{ - - microtime(&diff_time); - inittodr(0); - microtime(&suspend_time); - timevalsub(&diff_time, &suspend_time); - return (0); -} - -static int -apm_rtc_resume(void *arg __unused) -{ - u_int second, minute, hour; - struct timeval resume_time, tmp_time; - - /* modified for adjkerntz */ - timer_restore(); /* restore the all timers */ - inittodr(0); /* adjust time to RTC */ - microtime(&resume_time); - getmicrotime(&tmp_time); - timevaladd(&tmp_time, &diff_time); - /* Calculate the delta time suspended */ - timevalsub(&resume_time, &suspend_time); - -#ifdef PMTIMER_FIXUP_CALLTODO - /* Fixup the calltodo list with the delta time. */ - adjust_timeout_calltodo(&resume_time); -#endif /* PMTIMER_FIXUP_CALLTODO */ - second = resume_time.tv_sec; - hour = second / 3600; - second %= 3600; - minute = second / 60; - second %= 60; - log(LOG_NOTICE, "wakeup from sleeping state (slept %02d:%02d:%02d)\n", - hour, minute, second); - return (0); -} - -/* - * Attach APM: - * - * Initialize APM driver - */ - -static int -apm_attach(device_t dev) -{ - struct apm_softc *sc = &apm_softc; - int drv_version; - - mtx_init(&sc->mtx, device_get_nameunit(dev), "apm", MTX_DEF); - cv_init(&sc->cv, "cbb cv"); - - if (device_get_flags(dev) & 0x20) - atrtcclock_disable = 1; - - sc->initialized = 0; - - /* Must be externally enabled */ - sc->active = 0; - - /* Always call HLT in idle loop */ - sc->always_halt_cpu = 1; - - getenv_int("debug.apm_debug", &apm_debug); - - /* print bootstrap messages */ - APM_DPRINT("apm: APM BIOS version %04lx\n", apm_version); - APM_DPRINT("apm: Code16 0x%08x, Data 0x%08x\n", - sc->bios.seg.code16.base, sc->bios.seg.data.base); - APM_DPRINT("apm: Code entry 0x%08x, Idling CPU %s, Management %s\n", - sc->bios.entry, is_enabled(sc->slow_idle_cpu), - is_enabled(!sc->disabled)); - APM_DPRINT("apm: CS_limit=0x%x, DS_limit=0x%x\n", - sc->bios.seg.code16.limit, sc->bios.seg.data.limit); - - /* - * In one test, apm bios version was 1.02; an attempt to register - * a 1.04 driver resulted in a 1.00 connection! Registering a - * 1.02 driver resulted in a 1.02 connection. - */ - drv_version = apm_version > 0x102 ? 0x102 : apm_version; - for (; drv_version > 0x100; drv_version--) - if (apm_driver_version(drv_version) == 0) - break; - sc->minorversion = ((drv_version & 0x00f0) >> 4) * 10 + - ((drv_version & 0x000f) >> 0); - sc->majorversion = ((drv_version & 0xf000) >> 12) * 10 + - ((apm_version & 0x0f00) >> 8); - - sc->intversion = INTVERSION(sc->majorversion, sc->minorversion); - - if (sc->intversion >= INTVERSION(1, 1)) - APM_DPRINT("apm: Engaged control %s\n", is_enabled(!sc->disengaged)); - device_printf(dev, "found APM BIOS v%ld.%ld, connected at v%d.%d\n", - ((apm_version & 0xf000) >> 12) * 10 + ((apm_version & 0x0f00) >> 8), - ((apm_version & 0x00f0) >> 4) * 10 + ((apm_version & 0x000f) >> 0), - sc->majorversion, sc->minorversion); - - - APM_DPRINT("apm: Slow Idling CPU %s\n", is_enabled(sc->slow_idle_cpu)); - /* enable power management */ - if (sc->disabled) { - if (apm_enable_disable_pm(1)) { - APM_DPRINT("apm: *Warning* enable function failed! [%x]\n", - (sc->bios.r.eax >> 8) & 0xff); - } - } - - /* engage power managment (APM 1.1 or later) */ - if (sc->intversion >= INTVERSION(1, 1) && sc->disengaged) { - if (apm_engage_disengage_pm(1)) { - APM_DPRINT("apm: *Warning* engage function failed err=[%x]", - (sc->bios.r.eax >> 8) & 0xff); - APM_DPRINT(" (Docked or using external power?).\n"); - } - } - - /* Power the system off using APM */ - EVENTHANDLER_REGISTER(shutdown_final, apm_power_off, NULL, - SHUTDOWN_PRI_LAST); - - /* Register APM again to pass the correct argument of pm_func. */ - power_pm_register(POWER_PM_TYPE_APM, apm_pm_func, sc); - - sc->initialized = 1; - sc->suspending = 0; - sc->running = 0; - - make_dev(&apm_cdevsw, APMDEV_NORMAL, - UID_ROOT, GID_OPERATOR, 0664, "apm"); - make_dev(&apm_cdevsw, APMDEV_CTL, - UID_ROOT, GID_OPERATOR, 0660, "apmctl"); - - sc->sc_suspend.ah_fun = apm_rtc_suspend; - sc->sc_suspend.ah_arg = sc; - apm_hook_establish(APM_HOOK_SUSPEND, &sc->sc_suspend); - - sc->sc_resume.ah_fun = apm_rtc_resume; - sc->sc_resume.ah_arg = sc; - apm_hook_establish(APM_HOOK_RESUME, &sc->sc_resume); - - gone_in_dev(dev, 13, "APM support has been removed."); - - return 0; -} - -static int -apmopen(struct cdev *dev, int flag, int fmt, struct thread *td) -{ - struct apm_softc *sc = &apm_softc; - - if (sc == NULL || sc->initialized == 0) - return (ENXIO); - - switch (dev2unit(dev)) { - case APMDEV_CTL: - if (!(flag & FWRITE)) - return EINVAL; - if (sc->sc_flags & SCFLAG_OCTL) - return EBUSY; - sc->sc_flags |= SCFLAG_OCTL; - bzero(sc->event_filter, sizeof sc->event_filter); - break; - case APMDEV_NORMAL: - sc->sc_flags |= SCFLAG_ONORMAL; - break; - } - return 0; -} - -static int -apmclose(struct cdev *dev, int flag, int fmt, struct thread *td) -{ - struct apm_softc *sc = &apm_softc; - - switch (dev2unit(dev)) { - case APMDEV_CTL: - apm_lastreq_rejected(); - sc->sc_flags &= ~SCFLAG_OCTL; - bzero(sc->event_filter, sizeof sc->event_filter); - break; - case APMDEV_NORMAL: - sc->sc_flags &= ~SCFLAG_ONORMAL; - break; - } - if ((sc->sc_flags & SCFLAG_OPEN) == 0) { - sc->event_count = 0; - sc->event_ptr = 0; - } - return 0; -} - -static int -apmioctl(struct cdev *dev, u_long cmd, caddr_t addr, int flag, struct thread *td) -{ - struct apm_softc *sc = &apm_softc; - struct apm_bios_arg *args; - int error = 0; - int ret; - int newstate; - - if (sc == NULL || sc->initialized == 0) - return (ENXIO); - - APM_DPRINT("APM ioctl: cmd = 0x%lx\n", cmd); - switch (cmd) { - case APMIO_SUSPEND: - if (!(flag & FWRITE)) - return (EPERM); - if (sc->active) - apm_suspend(PMST_SUSPEND); - else - error = EINVAL; - break; - - case APMIO_STANDBY: - if (!(flag & FWRITE)) - return (EPERM); - if (sc->active) - apm_suspend(PMST_STANDBY); - else - error = EINVAL; - break; - - case APMIO_GETINFO_OLD: - { - struct apm_info info; - apm_info_old_t aiop; - - if (apm_get_info(&info)) - error = ENXIO; - aiop = (apm_info_old_t)addr; - aiop->ai_major = info.ai_major; - aiop->ai_minor = info.ai_minor; - aiop->ai_acline = info.ai_acline; - aiop->ai_batt_stat = info.ai_batt_stat; - aiop->ai_batt_life = info.ai_batt_life; - aiop->ai_status = info.ai_status; - } - break; - case APMIO_GETINFO: - if (apm_get_info((apm_info_t)addr)) - error = ENXIO; - break; - case APMIO_GETPWSTATUS: - if (apm_get_pwstatus((apm_pwstatus_t)addr)) - error = ENXIO; - break; - case APMIO_ENABLE: - if (!(flag & FWRITE)) - return (EPERM); - apm_event_enable(); - break; - case APMIO_DISABLE: - if (!(flag & FWRITE)) - return (EPERM); - apm_event_disable(); - break; - case APMIO_HALTCPU: - if (!(flag & FWRITE)) - return (EPERM); - apm_halt_cpu(); - break; - case APMIO_NOTHALTCPU: - if (!(flag & FWRITE)) - return (EPERM); - apm_not_halt_cpu(); - break; - case APMIO_DISPLAY: - if (!(flag & FWRITE)) - return (EPERM); - newstate = *(int *)addr; - if (apm_display(newstate)) - error = ENXIO; - break; - case APMIO_BIOS: - if (!(flag & FWRITE)) - return (EPERM); - /* XXX compatibility with the old interface */ - args = (struct apm_bios_arg *)addr; - sc->bios.r.eax = args->eax; - sc->bios.r.ebx = args->ebx; - sc->bios.r.ecx = args->ecx; - sc->bios.r.edx = args->edx; - sc->bios.r.esi = args->esi; - sc->bios.r.edi = args->edi; - if ((ret = apm_bioscall())) { - /* - * Return code 1 means bios call was unsuccessful. - * Error code is stored in %ah. - * Return code -1 means bios call was unsupported - * in the APM BIOS version. - */ - if (ret == -1) { - error = EINVAL; - } - } else { - /* - * Return code 0 means bios call was successful. - * We need only %al and can discard %ah. - */ - sc->bios.r.eax &= 0xff; - } - args->eax = sc->bios.r.eax; - args->ebx = sc->bios.r.ebx; - args->ecx = sc->bios.r.ecx; - args->edx = sc->bios.r.edx; - args->esi = sc->bios.r.esi; - args->edi = sc->bios.r.edi; - break; - default: - error = EINVAL; - break; - } - - /* for /dev/apmctl */ - if (dev2unit(dev) == APMDEV_CTL) { - struct apm_event_info *evp; - int i; - - error = 0; - switch (cmd) { - case APMIO_NEXTEVENT: - if (!sc->event_count) { - error = EAGAIN; - } else { - evp = (struct apm_event_info *)addr; - i = sc->event_ptr + APM_NEVENTS - sc->event_count; - i %= APM_NEVENTS; - *evp = sc->event_list[i]; - sc->event_count--; - } - break; - case APMIO_REJECTLASTREQ: - if (apm_lastreq_rejected()) { - error = EINVAL; - } - break; - default: - error = EINVAL; - break; - } - } - - return error; -} - -static int -apmwrite(struct cdev *dev, struct uio *uio, int ioflag) -{ - struct apm_softc *sc = &apm_softc; - u_int event_type; - int error; - u_char enabled; - - if (dev2unit(dev) != APMDEV_CTL) - return(ENODEV); - if (uio->uio_resid != sizeof(u_int)) - return(E2BIG); - - if ((error = uiomove((caddr_t)&event_type, sizeof(u_int), uio))) - return(error); - - if (event_type >= APM_NPMEV) - return(EINVAL); - - if (sc->event_filter[event_type] == 0) { - enabled = 1; - } else { - enabled = 0; - } - sc->event_filter[event_type] = enabled; - APM_DPRINT("apmwrite: event 0x%x %s\n", event_type, is_enabled(enabled)); - - return uio->uio_resid; -} - -static int -apmpoll(struct cdev *dev, int events, struct thread *td) -{ - struct apm_softc *sc = &apm_softc; - int revents = 0; - - if (events & (POLLIN | POLLRDNORM)) { - if (sc->event_count) { - revents |= events & (POLLIN | POLLRDNORM); - } else { - selrecord(td, &sc->sc_rsel); - } - } - - return (revents); -} - -static device_method_t apm_methods[] = { - /* Device interface */ - DEVMETHOD(device_identify, apm_identify), - DEVMETHOD(device_probe, apm_probe), - DEVMETHOD(device_attach, apm_attach), - - { 0, 0 } -}; - -static driver_t apm_driver = { - "apm", - apm_methods, - 1, /* no softc (XXX) */ -}; - -static devclass_t apm_devclass; - -DRIVER_MODULE(apm, legacy, apm_driver, apm_devclass, apm_modevent, 0); -MODULE_VERSION(apm, 1); - -static int -apm_pm_func(u_long cmd, void *arg, ...) -{ - int state, apm_state; - int error; - va_list ap; - - error = 0; - switch (cmd) { - case POWER_CMD_SUSPEND: - va_start(ap, arg); - state = va_arg(ap, int); - va_end(ap); - - switch (state) { - case POWER_SLEEP_STATE_STANDBY: - apm_state = PMST_STANDBY; - break; - case POWER_SLEEP_STATE_SUSPEND: - case POWER_SLEEP_STATE_HIBERNATE: - apm_state = PMST_SUSPEND; - break; - default: - error = EINVAL; - goto out; - } - - apm_suspend(apm_state); - break; - - default: - error = EINVAL; - goto out; - } - -out: - return (error); -} - -static void -apm_pm_register(void *arg) -{ - - if (!resource_disabled("apm", 0)) - power_pm_register(POWER_PM_TYPE_APM, apm_pm_func, NULL); -} - -SYSINIT(power, SI_SUB_KLD, SI_ORDER_ANY, apm_pm_register, NULL); diff --git a/sys/i386/bios/apm.h b/sys/i386/bios/apm.h deleted file mode 100644 index fd1df2ea803..00000000000 --- a/sys/i386/bios/apm.h +++ /dev/null @@ -1,51 +0,0 @@ -/*- - * APM (Advanced Power Management) BIOS Device Driver - * - * Copyright (c) 1994 UKAI, Fumitoshi. - * Copyright (c) 1994-1995 by HOSOKAWA, Tatsumi - * Copyright (c) 1996 Nate Williams - * Copyright (c) 1997 Poul-Henning Kamp - * - * This software may be used, modified, copied, and distributed, in - * both source and binary form provided that the above copyright and - * these terms are retained. Under no circumstances is the author - * responsible for the proper functioning of this software, nor does - * the author assume any responsibility for damages incurred with its - * use. - * - * Sep, 1994 Implemented on FreeBSD 1.1.5.1R (Toshiba AVS001WD) - * - */ - -#ifndef __APM_H__ -#define __APM_H__ - -#define APM_NEVENTS 16 -#define APM_NPMEV 13 -#define APM_UNKNOWN 0xff - -/* static data */ -struct apm_softc { - struct mtx mtx; - struct cv cv; - struct proc *event_thread; - int initialized, active, running, bios_busy; - int always_halt_cpu, slow_idle_cpu; - int disabled, disengaged; - int suspending; - int standby_countdown, suspend_countdown; - u_int minorversion, majorversion; - u_int intversion, connectmode; - u_int standbys, suspends; - struct bios_args bios; - struct apmhook sc_suspend; - struct apmhook sc_resume; - struct selinfo sc_rsel; - int sc_flags; - int event_count; - int event_ptr; - struct apm_event_info event_list[APM_NEVENTS]; - u_char event_filter[APM_NPMEV]; -}; - -#endif /* !__APM_H__ */ diff --git a/sys/i386/conf/Makefile b/sys/i386/conf/Makefile deleted file mode 100644 index 967a1d90b37..00000000000 --- a/sys/i386/conf/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -# $FreeBSD: stable/10/sys/i386/conf/Makefile 201813 2010-01-08 18:57:31Z bz $ - -TARGET=i386 - -.include "${.CURDIR}/../../conf/makeLINT.mk" diff --git a/sys/i386/i386/in_cksum.c b/sys/i386/i386/in_cksum.c deleted file mode 100644 index 7bd2cb2a8d7..00000000000 --- a/sys/i386/i386/in_cksum.c +++ /dev/null @@ -1,492 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-3-Clause - * - * Copyright (c) 1990 The Regents of the University of California. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the University nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * from tahoe: in_cksum.c 1.2 86/01/05 - * from: @(#)in_cksum.c 1.3 (Berkeley) 1/19/91 - */ - -#include - -#include -#include -#include - -#include -#include -#include - -#include - -/* - * Checksum routine for Internet Protocol family headers. - * - * This routine is very heavily used in the network - * code and should be modified for each CPU to be as fast as possible. - * - * This implementation is 386 version. - */ - -#undef ADDCARRY -#define ADDCARRY(x) if ((x) > 0xffff) (x) -= 0xffff -/* - * icc needs to be special cased here, as the asm code below results - * in broken code if compiled with icc. - */ -#if !defined(__GNUCLIKE_ASM) || defined(__INTEL_COMPILER) -/* non gcc parts stolen from sys/alpha/alpha/in_cksum.c */ -#define REDUCE32 \ - { \ - q_util.q = sum; \ - sum = q_util.s[0] + q_util.s[1] + q_util.s[2] + q_util.s[3]; \ - } -#define REDUCE16 \ - { \ - q_util.q = sum; \ - l_util.l = q_util.s[0] + q_util.s[1] + q_util.s[2] + q_util.s[3]; \ - sum = l_util.s[0] + l_util.s[1]; \ - ADDCARRY(sum); \ - } -#endif -#define REDUCE {sum = (sum & 0xffff) + (sum >> 16); ADDCARRY(sum);} - -#if !defined(__GNUCLIKE_ASM) || defined(__INTEL_COMPILER) -static const u_int32_t in_masks[] = { - /*0 bytes*/ /*1 byte*/ /*2 bytes*/ /*3 bytes*/ - 0x00000000, 0x000000FF, 0x0000FFFF, 0x00FFFFFF, /* offset 0 */ - 0x00000000, 0x0000FF00, 0x00FFFF00, 0xFFFFFF00, /* offset 1 */ - 0x00000000, 0x00FF0000, 0xFFFF0000, 0xFFFF0000, /* offset 2 */ - 0x00000000, 0xFF000000, 0xFF000000, 0xFF000000, /* offset 3 */ -}; - -union l_util { - u_int16_t s[2]; - u_int32_t l; -}; -union q_util { - u_int16_t s[4]; - u_int32_t l[2]; - u_int64_t q; -}; - -static u_int64_t -in_cksumdata(const u_int32_t *lw, int len) -{ - u_int64_t sum = 0; - u_int64_t prefilled; - int offset; - union q_util q_util; - - if ((3 & (long) lw) == 0 && len == 20) { - sum = (u_int64_t) lw[0] + lw[1] + lw[2] + lw[3] + lw[4]; - REDUCE32; - return sum; - } - - if ((offset = 3 & (long) lw) != 0) { - const u_int32_t *masks = in_masks + (offset << 2); - lw = (u_int32_t *) (((long) lw) - offset); - sum = *lw++ & masks[len >= 3 ? 3 : len]; - len -= 4 - offset; - if (len <= 0) { - REDUCE32; - return sum; - } - } -#if 0 - /* - * Force to cache line boundary. - */ - offset = 32 - (0x1f & (long) lw); - if (offset < 32 && len > offset) { - len -= offset; - if (4 & offset) { - sum += (u_int64_t) lw[0]; - lw += 1; - } - if (8 & offset) { - sum += (u_int64_t) lw[0] + lw[1]; - lw += 2; - } - if (16 & offset) { - sum += (u_int64_t) lw[0] + lw[1] + lw[2] + lw[3]; - lw += 4; - } - } -#endif - /* - * access prefilling to start load of next cache line. - * then add current cache line - * save result of prefilling for loop iteration. - */ - prefilled = lw[0]; - while ((len -= 32) >= 4) { - u_int64_t prefilling = lw[8]; - sum += prefilled + lw[1] + lw[2] + lw[3] - + lw[4] + lw[5] + lw[6] + lw[7]; - lw += 8; - prefilled = prefilling; - } - if (len >= 0) { - sum += prefilled + lw[1] + lw[2] + lw[3] - + lw[4] + lw[5] + lw[6] + lw[7]; - lw += 8; - } else { - len += 32; - } - while ((len -= 16) >= 0) { - sum += (u_int64_t) lw[0] + lw[1] + lw[2] + lw[3]; - lw += 4; - } - len += 16; - while ((len -= 4) >= 0) { - sum += (u_int64_t) *lw++; - } - len += 4; - if (len > 0) - sum += (u_int64_t) (in_masks[len] & *lw); - REDUCE32; - return sum; -} - -u_short -in_addword(u_short a, u_short b) -{ - u_int64_t sum = a + b; - - ADDCARRY(sum); - return (sum); -} - -u_short -in_pseudo(u_int32_t a, u_int32_t b, u_int32_t c) -{ - u_int64_t sum; - union q_util q_util; - union l_util l_util; - - sum = (u_int64_t) a + b + c; - REDUCE16; - return (sum); -} - -u_short -in_cksum_skip(struct mbuf *m, int len, int skip) -{ - u_int64_t sum = 0; - int mlen = 0; - int clen = 0; - caddr_t addr; - union q_util q_util; - union l_util l_util; - - len -= skip; - for (; skip && m; m = m->m_next) { - if (m->m_len > skip) { - mlen = m->m_len - skip; - addr = mtod(m, caddr_t) + skip; - goto skip_start; - } else { - skip -= m->m_len; - } - } - - for (; m && len; m = m->m_next) { - if (m->m_len == 0) - continue; - mlen = m->m_len; - addr = mtod(m, caddr_t); -skip_start: - if (len < mlen) - mlen = len; - if ((clen ^ (long) addr) & 1) - sum += in_cksumdata((const u_int32_t *)addr, mlen) << 8; - else - sum += in_cksumdata((const u_int32_t *)addr, mlen); - - clen += mlen; - len -= mlen; - } - REDUCE16; - return (~sum & 0xffff); -} - -u_int in_cksum_hdr(const struct ip *ip) -{ - u_int64_t sum = in_cksumdata((const u_int32_t *)ip, sizeof(struct ip)); - union q_util q_util; - union l_util l_util; - - REDUCE16; - return (~sum & 0xffff); -} -#else - -/* - * These asm statements require __volatile because they pass information - * via the condition codes. GCC does not currently provide a way to specify - * the condition codes as an input or output operand. - * - * The LOAD macro below is effectively a prefetch into cache. GCC will - * load the value into a register but will not use it. Since modern CPUs - * reorder operations, this will generally take place in parallel with - * other calculations. - */ -u_short -in_cksum_skip(m, len, skip) - struct mbuf *m; - int len; - int skip; -{ - u_short *w; - unsigned sum = 0; - int mlen = 0; - int byte_swapped = 0; - union { char c[2]; u_short s; } su; - - len -= skip; - for (; skip && m; m = m->m_next) { - if (m->m_len > skip) { - mlen = m->m_len - skip; - w = (u_short *)(mtod(m, u_char *) + skip); - goto skip_start; - } else { - skip -= m->m_len; - } - } - - for (;m && len; m = m->m_next) { - if (m->m_len == 0) - continue; - w = mtod(m, u_short *); - if (mlen == -1) { - /* - * The first byte of this mbuf is the continuation - * of a word spanning between this mbuf and the - * last mbuf. - */ - - /* su.c[0] is already saved when scanning previous - * mbuf. sum was REDUCEd when we found mlen == -1 - */ - su.c[1] = *(u_char *)w; - sum += su.s; - w = (u_short *)((char *)w + 1); - mlen = m->m_len - 1; - len--; - } else - mlen = m->m_len; -skip_start: - if (len < mlen) - mlen = len; - len -= mlen; - /* - * Force to long boundary so we do longword aligned - * memory operations - */ - if (3 & (int) w) { - REDUCE; - if ((1 & (int) w) && (mlen > 0)) { - sum <<= 8; - su.c[0] = *(char *)w; - w = (u_short *)((char *)w + 1); - mlen--; - byte_swapped = 1; - } - if ((2 & (int) w) && (mlen >= 2)) { - sum += *w++; - mlen -= 2; - } - } - /* - * Advance to a 486 cache line boundary. - */ - if (4 & (int) w && mlen >= 4) { - __asm __volatile ( - "addl %1, %0\n" - "adcl $0, %0" - : "+r" (sum) - : "g" (((const u_int32_t *)w)[0]) - ); - w += 2; - mlen -= 4; - } - if (8 & (int) w && mlen >= 8) { - __asm __volatile ( - "addl %1, %0\n" - "adcl %2, %0\n" - "adcl $0, %0" - : "+r" (sum) - : "g" (((const u_int32_t *)w)[0]), - "g" (((const u_int32_t *)w)[1]) - ); - w += 4; - mlen -= 8; - } - /* - * Do as much of the checksum as possible 32 bits at at time. - * In fact, this loop is unrolled to make overhead from - * branches &c small. - */ - mlen -= 1; - while ((mlen -= 32) >= 0) { - /* - * Add with carry 16 words and fold in the last - * carry by adding a 0 with carry. - * - * The early ADD(16) and the LOAD(32) are to load - * the next 2 cache lines in advance on 486's. The - * 486 has a penalty of 2 clock cycles for loading - * a cache line, plus whatever time the external - * memory takes to load the first word(s) addressed. - * These penalties are unavoidable. Subsequent - * accesses to a cache line being loaded (and to - * other external memory?) are delayed until the - * whole load finishes. These penalties are mostly - * avoided by not accessing external memory for - * 8 cycles after the ADD(16) and 12 cycles after - * the LOAD(32). The loop terminates when mlen - * is initially 33 (not 32) to guaranteed that - * the LOAD(32) is within bounds. - */ - __asm __volatile ( - "addl %1, %0\n" - "adcl %2, %0\n" - "adcl %3, %0\n" - "adcl %4, %0\n" - "adcl %5, %0\n" - "mov %6, %%eax\n" - "adcl %7, %0\n" - "adcl %8, %0\n" - "adcl %9, %0\n" - "adcl $0, %0" - : "+r" (sum) - : "g" (((const u_int32_t *)w)[4]), - "g" (((const u_int32_t *)w)[0]), - "g" (((const u_int32_t *)w)[1]), - "g" (((const u_int32_t *)w)[2]), - "g" (((const u_int32_t *)w)[3]), - "g" (((const u_int32_t *)w)[8]), - "g" (((const u_int32_t *)w)[5]), - "g" (((const u_int32_t *)w)[6]), - "g" (((const u_int32_t *)w)[7]) - : "eax" - ); - w += 16; - } - mlen += 32 + 1; - if (mlen >= 32) { - __asm __volatile ( - "addl %1, %0\n" - "adcl %2, %0\n" - "adcl %3, %0\n" - "adcl %4, %0\n" - "adcl %5, %0\n" - "adcl %6, %0\n" - "adcl %7, %0\n" - "adcl %8, %0\n" - "adcl $0, %0" - : "+r" (sum) - : "g" (((const u_int32_t *)w)[4]), - "g" (((const u_int32_t *)w)[0]), - "g" (((const u_int32_t *)w)[1]), - "g" (((const u_int32_t *)w)[2]), - "g" (((const u_int32_t *)w)[3]), - "g" (((const u_int32_t *)w)[5]), - "g" (((const u_int32_t *)w)[6]), - "g" (((const u_int32_t *)w)[7]) - ); - w += 16; - mlen -= 32; - } - if (mlen >= 16) { - __asm __volatile ( - "addl %1, %0\n" - "adcl %2, %0\n" - "adcl %3, %0\n" - "adcl %4, %0\n" - "adcl $0, %0" - : "+r" (sum) - : "g" (((const u_int32_t *)w)[0]), - "g" (((const u_int32_t *)w)[1]), - "g" (((const u_int32_t *)w)[2]), - "g" (((const u_int32_t *)w)[3]) - ); - w += 8; - mlen -= 16; - } - if (mlen >= 8) { - __asm __volatile ( - "addl %1, %0\n" - "adcl %2, %0\n" - "adcl $0, %0" - : "+r" (sum) - : "g" (((const u_int32_t *)w)[0]), - "g" (((const u_int32_t *)w)[1]) - ); - w += 4; - mlen -= 8; - } - if (mlen == 0 && byte_swapped == 0) - continue; /* worth 1% maybe ?? */ - REDUCE; - while ((mlen -= 2) >= 0) { - sum += *w++; - } - if (byte_swapped) { - sum <<= 8; - byte_swapped = 0; - if (mlen == -1) { - su.c[1] = *(char *)w; - sum += su.s; - mlen = 0; - } else - mlen = -1; - } else if (mlen == -1) - /* - * This mbuf has odd number of bytes. - * There could be a word split between - * this mbuf and the next mbuf. - * Save the last byte (to prepend to next mbuf). - */ - su.c[0] = *(char *)w; - } - - if (len) - printf("%s: out of data by %d\n", __func__, len); - if (mlen == -1) { - /* The last mbuf has odd # of bytes. Follow the - standard (the odd byte is shifted left by 8 bits) */ - su.c[1] = 0; - sum += su.s; - } - REDUCE; - return (~sum & 0xffff); -} -#endif diff --git a/sys/i386/ibcs2/Makefile b/sys/i386/ibcs2/Makefile deleted file mode 100644 index 7583e5b2e6e..00000000000 --- a/sys/i386/ibcs2/Makefile +++ /dev/null @@ -1,35 +0,0 @@ -# Makefile for syscall tables -# - -# Don't use an OBJDIR -.OBJDIR: ${.CURDIR} - -MAKESYSCALLS= ../../kern/makesyscalls.sh -BASE_GENERATED= ibcs2_syscall.h \ - ibcs2_sysent.c \ - ibcs2_proto.h -ISC_GENERATED= ibcs2_isc_syscall.h \ - ibcs2_isc_sysent.c -XENIX_GENERATED= ibcs2_xenix_syscall.h \ - ibcs2_xenix_sysent.c \ - ibcs2_xenix_proto.h - -all: - @echo "make sysent, isc_sysent or xenix_sysent only" - -.ORDER: ${BASE_GENERATED} -.ORDER: ${ISC_GENERATED} -.ORDER: ${XENIX_GENERATED} - -sysent: ${BASE_GENERATED} -isc_sysent: ${ISC_GENERATED} -xenix_sysent: ${XENIX_GENERATED} - -${BASE_GENERATED}: ${MAKESYSCALLS} syscalls.master syscalls.conf - sh ${MAKESYSCALLS} syscalls.master syscalls.conf - -${ISC_GENERATED}: ${MAKESYSCALLS} syscalls.isc syscalls.isc.conf - sh ${MAKESYSCALLS} syscalls.isc syscalls.isc.conf - -${XENIX_GENERATED}: ${MAKESYSCALLS} syscalls.xenix syscalls.xenix.conf - sh ${MAKESYSCALLS} syscalls.xenix syscalls.xenix.conf diff --git a/sys/i386/ibcs2/coff.h b/sys/i386/ibcs2/coff.h deleted file mode 100644 index 9497144e9e9..00000000000 --- a/sys/i386/ibcs2/coff.h +++ /dev/null @@ -1,107 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-3-Clause - * - * Copyright (c) 1994 Sean Eric Fagan - * Copyright (c) 1994 Søren Schmidt - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer - * in this position and unchanged. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef _COFF_H -#define _COFF_H - -struct filehdr { - unsigned short f_magic; /* magic number */ - unsigned short f_nscns; /* # of sections */ - long f_timdat; /* time stamp */ - long f_symptr; /* symbol table offset */ - long f_nsyms; /* # of symbols */ - unsigned short f_opthdr; /* size of system header */ - unsigned short f_flags; /* flags, see below */ -}; - -enum filehdr_flags { - F_RELFLG = 0x01, /* relocs have been stripped */ - F_EXEC = 0x02, /* executable file (or shlib) */ - F_LNNO = 0x04, /* line numbers have been stripped */ - F_LSYMS = 0x08, /* symbols have been stripped */ - F_SWABD = 0x40, /* swabbed byte names */ - F_AR16WR = 0x80, /* 16-bit, byte reversed words */ - F_AR32WR = 0x100 /* 32-bit, byte reversed words */ -}; - -struct aouthdr { - short magic; /* magic number -- see below */ - short vstamp; /* artifacts from a by-gone day */ - long tsize; /* */ - long dsize; /* */ - long bsize; /* */ - long entry; /* Entry point -- offset into file */ - long tstart; /* artifacts from a by-gone day */ - long dstart; /* */ -}; - -#define I386_COFF 0x14c - -#define COFF_OMAGIC 0407 /* impure format */ -#define COFF_NMAGIC 0410 /* read-only text */ -#define COFF_ZMAGIC 0413 /* pagable from disk */ -#define COFF_SHLIB 0443 /* a shared library */ - -struct scnhdr { - char s_name[8]; /* name of section (e.g., ".text") */ - long s_paddr; /* physical addr, used for standalone */ - long s_vaddr; /* virtual address */ - long s_size; /* size of section */ - long s_scnptr; /* file offset of section */ - long s_relptr; /* points to relocs for section */ - long s_lnnoptr; /* points to line numbers for section */ - unsigned short s_nreloc; /* # of relocs */ - unsigned short s_nlnno; /* # of line no's */ - long s_flags; /* section flags -- see below */ -}; - -enum scnhdr_flags { - STYP_REG = 0x00, /* regular (alloc'ed, reloc'ed, loaded) */ - STYP_DSECT = 0x01, /* dummy (reloc'd) */ - STYP_NOLOAD = 0x02, /* no-load (reloc'd) */ - STYP_GROUP = 0x04, /* grouped */ - STYP_PAD = 0x08, /* padding (loaded) */ - STYP_COPY = 0x10, /* ??? */ - STYP_TEXT = 0x20, /* text */ - STYP_DATA = 0x40, /* data */ - STYP_BSS = 0x80, /* bss */ - STYP_INFO = 0x200, /* comment (!loaded, !alloc'ed, !reloc'd) */ - STYP_OVER = 0x400, /* overlay (!allocated, reloc'd, !loaded) */ - STYP_LIB = 0x800 /* lists shared library files */ -}; - -struct slhdr { - long entry_length; - long path_index; - char *shlib_name; -}; -#endif /* _COFF_H */ diff --git a/sys/i386/ibcs2/ibcs2_dirent.h b/sys/i386/ibcs2/ibcs2_dirent.h deleted file mode 100644 index 92a7e890a23..00000000000 --- a/sys/i386/ibcs2/ibcs2_dirent.h +++ /dev/null @@ -1,59 +0,0 @@ -/* $NetBSD: ibcs2_dirent.h,v 1.2 1994/10/26 02:52:51 cgd Exp $ */ - -/*- - * SPDX-License-Identifier: BSD-4-Clause - * - * Copyright (c) 1994 Scott Bartram - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by Scott Bartram. - * 4. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - - -#ifndef _IBCS2_DIRENT_H -#define _IBCS2_DIRENT_H 1 - -#include - -#define IBCS2_MAXNAMLEN 512 -#define IBCS2_DIRBUF 1048 - -typedef struct { - int dd_fd; - int dd_loc; - int dd_size; - char *dd_buf; -} IBCS2_DIR; - -struct ibcs2_dirent { - ibcs2_ino_t d_ino; - short d_pad; - ibcs2_off_t d_off; - u_short d_reclen; - char d_name[1]; -}; - -#endif /* _IBCS2_DIRENT_H */ diff --git a/sys/i386/ibcs2/ibcs2_errno.c b/sys/i386/ibcs2/ibcs2_errno.c deleted file mode 100644 index f45a41be67e..00000000000 --- a/sys/i386/ibcs2/ibcs2_errno.c +++ /dev/null @@ -1,128 +0,0 @@ -/*- - * ibcs2_errno.c - * SPDX-License-Identifier: BSD-4-Clause - * - * Copyright (c) 1995 Scott Bartram - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by Scott Bartram. - * 4. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include - -#include -#include - -int bsd_to_ibcs2_errno[ELAST + 1] = { - 0, /* 0 */ - IBCS2_EPERM, /* 1 */ - IBCS2_ENOENT, /* 2 */ - IBCS2_ESRCH, /* 3 */ - IBCS2_EINTR, /* 4 */ - IBCS2_EIO, /* 5 */ - IBCS2_ENXIO, /* 6 */ - IBCS2_E2BIG, /* 7 */ - IBCS2_ENOEXEC, /* 8 */ - IBCS2_EBADF, /* 9 */ - IBCS2_ECHILD, /* 10 */ - IBCS2_EDEADLK, /* 11 */ - IBCS2_ENOMEM, /* 12 */ - IBCS2_EACCES, /* 13 */ - IBCS2_EFAULT, /* 14 */ - IBCS2_ENOTBLK, /* 15 */ - IBCS2_EBUSY, /* 16 */ - IBCS2_EEXIST, /* 17 */ - IBCS2_EXDEV, /* 18 */ - IBCS2_ENODEV, /* 19 */ - IBCS2_ENOTDIR, /* 20 */ - IBCS2_EISDIR, /* 21 */ - IBCS2_EINVAL, /* 22 */ - IBCS2_ENFILE, /* 23 */ - IBCS2_EMFILE, /* 24 */ - IBCS2_ENOTTY, /* 25 */ - IBCS2_ETXTBSY, /* 26 */ - IBCS2_EFBIG, /* 27 */ - IBCS2_ENOSPC, /* 28 */ - IBCS2_ESPIPE, /* 29 */ - IBCS2_EROFS, /* 30 */ - IBCS2_EMLINK, /* 31 */ - IBCS2_EPIPE, /* 32 */ - IBCS2_EDOM, /* 33 */ - IBCS2_ERANGE, /* 34 */ - IBCS2_EAGAIN, /* 35 */ - IBCS2_EINPROGRESS, /* 36 */ - IBCS2_EALREADY, /* 37 */ - IBCS2_ENOTSOCK, /* 38 */ - IBCS2_EDESTADDRREQ, /* 39 */ - IBCS2_EMSGSIZE, /* 40 */ - IBCS2_EPROTOTYPE, /* 41 */ - IBCS2_ENOPROTOOPT, /* 42 */ - IBCS2_EPROTONOSUPPORT, /* 43 */ - IBCS2_ESOCKTNOSUPPORT, /* 44 */ - IBCS2_EOPNOTSUPP, /* 45 */ - IBCS2_EPFNOSUPPORT, /* 46 */ - IBCS2_EAFNOSUPPORT, /* 47 */ - IBCS2_EADDRINUSE, /* 48 */ - IBCS2_EADDRNOTAVAIL, /* 49 */ - IBCS2_ENETDOWN, /* 50 */ - IBCS2_ENETUNREACH, /* 51 */ - IBCS2_ENETRESET, /* 52 */ - IBCS2_ECONNABORTED, /* 53 */ - IBCS2_ECONNRESET, /* 54 */ - IBCS2_ENOBUFS, /* 55 */ - IBCS2_EISCONN, /* 56 */ - IBCS2_ENOTCONN, /* 57 */ - IBCS2_ESHUTDOWN, /* 58 */ - IBCS2_ETOOMANYREFS, /* 59 */ - IBCS2_ETIMEDOUT, /* 60 */ - IBCS2_ECONNREFUSED, /* 61 */ - IBCS2_ELOOP, /* 62 */ - IBCS2_ENAMETOOLONG, /* 63 */ - IBCS2_EHOSTDOWN, /* 64 */ - IBCS2_EHOSTUNREACH, /* 65 */ - IBCS2_ENOTEMPTY, /* 66 */ - 0, /* 67 */ - 0, /* 68 */ - 0, /* 69 */ - IBCS2_ESTALE, /* 70 */ - IBCS2_EREMOTE, /* 71 */ - 0, /* 72 */ - 0, /* 73 */ - 0, /* 74 */ - 0, /* 75 */ - 0, /* 76 */ - IBCS2_ENOLCK, /* 77 */ - IBCS2_ENOSYS, /* 78 */ - 0, /* 79 */ - 0, /* 80 */ - 0, /* 81 */ - IBCS2_EIDRM, /* 82 */ - IBCS2_ENOMSG, /* 83 */ - IBCS2_EOVERFLOW, /* 84 */ - 0, /* 85 */ - IBCS2_EILSEQ, /* 86 */ -}; - diff --git a/sys/i386/ibcs2/ibcs2_errno.h b/sys/i386/ibcs2/ibcs2_errno.h deleted file mode 100644 index 6900e512e23..00000000000 --- a/sys/i386/ibcs2/ibcs2_errno.h +++ /dev/null @@ -1,156 +0,0 @@ -/*- - * ibcs2_errno.h - * SPDX-License-Identifier: BSD-4-Clause - * - * Copyright (c) 1995 Scott Bartram - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by Scott Bartram. - * 4. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef _IBCS2_ERRNO_H -#define _IBCS2_ERRNO_H - -#define _SCO_NET 1 - -#define IBCS2_EPERM 1 -#define IBCS2_ENOENT 2 -#define IBCS2_ESRCH 3 -#define IBCS2_EINTR 4 -#define IBCS2_EIO 5 -#define IBCS2_ENXIO 6 -#define IBCS2_E2BIG 7 -#define IBCS2_ENOEXEC 8 -#define IBCS2_EBADF 9 -#define IBCS2_ECHILD 10 -#define IBCS2_EAGAIN 11 -#define IBCS2_ENOMEM 12 -#define IBCS2_EACCES 13 -#define IBCS2_EFAULT 14 -#define IBCS2_ENOTBLK 15 -#define IBCS2_EBUSY 16 -#define IBCS2_EEXIST 17 -#define IBCS2_EXDEV 18 -#define IBCS2_ENODEV 19 -#define IBCS2_ENOTDIR 20 -#define IBCS2_EISDIR 21 -#define IBCS2_EINVAL 22 -#define IBCS2_ENFILE 23 -#define IBCS2_EMFILE 24 -#define IBCS2_ENOTTY 25 -#define IBCS2_ETXTBSY 26 -#define IBCS2_EFBIG 27 -#define IBCS2_ENOSPC 28 -#define IBCS2_ESPIPE 29 -#define IBCS2_EROFS 30 -#define IBCS2_EMLINK 31 -#define IBCS2_EPIPE 32 -#define IBCS2_EDOM 33 -#define IBCS2_ERANGE 34 -#define IBCS2_ENOMSG 35 -#define IBCS2_EIDRM 36 -#define IBCS2_ECHRNG 37 -#define IBCS2_EL2NSYNC 38 -#define IBCS2_EL3HLT 39 -#define IBCS2_EL3RST 40 -#define IBCS2_ELNRNG 41 -#define IBCS2_EUNATCH 42 -#define IBCS2_ENOCSI 43 -#define IBCS2_EL2HLT 44 -#define IBCS2_EDEADLK 45 -#define IBCS2_ENOLCK 46 -#define IBCS2_ENOSTR 60 -#define IBCS2_ENODATA 61 -#define IBCS2_ETIME 62 -#define IBCS2_ENOSR 63 -#define IBCS2_ENONET 64 -#define IBCS2_ENOPKG 65 -#define IBCS2_EREMOTE 66 -#define IBCS2_ENOLINK 67 -#define IBCS2_EADV 68 -#define IBCS2_ESRMNT 69 -#define IBCS2_ECOMM 70 -#define IBCS2_EPROTO 71 -#define IBCS2_EMULTIHOP 74 -#define IBCS2_ELBIN 75 -#define IBCS2_EDOTDOT 76 -#define IBCS2_EBADMSG 77 -#define IBCS2_ENAMETOOLONG 78 -#define IBCS2_EOVERFLOW 79 -#define IBCS2_ENOTUNIQ 80 -#define IBCS2_EBADFD 81 -#define IBCS2_EREMCHG 82 -#define IBCS2_EILSEQ 88 -#define IBCS2_ENOSYS 89 - -#if defined(_SCO_NET) /* not strict iBCS2 */ -#define IBCS2_EWOULDBLOCK 90 -#define IBCS2_EINPROGRESS 91 -#define IBCS2_EALREADY 92 -#define IBCS2_ENOTSOCK 93 -#define IBCS2_EDESTADDRREQ 94 -#define IBCS2_EMSGSIZE 95 -#define IBCS2_EPROTOTYPE 96 -#define IBCS2_EPROTONOSUPPORT 97 -#define IBCS2_ESOCKTNOSUPPORT 98 -#define IBCS2_EOPNOTSUPP 99 -#define IBCS2_EPFNOSUPPORT 100 -#define IBCS2_EAFNOSUPPORT 101 -#define IBCS2_EADDRINUSE 102 -#define IBCS2_EADDRNOTAVAIL 103 -#define IBCS2_ENETDOWN 104 -#define IBCS2_ENETUNREACH 105 -#define IBCS2_ENETRESET 106 -#define IBCS2_ECONNABORTED 107 -#define IBCS2_ECONNRESET 108 -#define IBCS2_ENOBUFS IBCS2_ENOSR -#define IBCS2_EISCONN 110 -#define IBCS2_ENOTCONN 111 -#define IBCS2_ESHUTDOWN 112 -#define IBCS2_ETOOMANYREFS 113 -#define IBCS2_ETIMEDOUT 114 -#define IBCS2_ECONNREFUSED 115 -#define IBCS2_EHOSTDOWN 116 -#define IBCS2_EHOSTUNREACH 117 -#define IBCS2_ENOPROTOOPT 118 -#define IBCS2_ENOTEMPTY 145 -#define IBCS2_ELOOP 150 -#else -#define IBCS2_ELOOP 90 -#define IBCS2_EWOULDBLOCK 90 -#define IBCS2_ERESTART 91 -#define IBCS2_ESTRPIPE 92 -#define IBCS2_ENOTEMPTY 93 -#define IBCS2_EUSERS 94 -#endif - -#define IBCS2_ESTALE 151 -#define IBCS2_EIORESID 500 - -extern int bsd2ibcs_errno[]; - -#endif /* _IBCS2_ERRNO_H */ diff --git a/sys/i386/ibcs2/ibcs2_fcntl.c b/sys/i386/ibcs2/ibcs2_fcntl.c deleted file mode 100644 index 77183f32b34..00000000000 --- a/sys/i386/ibcs2/ibcs2_fcntl.c +++ /dev/null @@ -1,318 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-3-Clause - * - * Copyright (c) 1995 Scott Bartram - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include - -#include "opt_spx_hack.h" - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -static void cvt_iflock2flock(struct ibcs2_flock *, struct flock *); -static void cvt_flock2iflock(struct flock *, struct ibcs2_flock *); -static int cvt_o_flags(int); -static int oflags2ioflags(int); -static int ioflags2oflags(int); - -static int -cvt_o_flags(flags) - int flags; -{ - int r = 0; - - /* convert mode into NetBSD mode */ - if (flags & IBCS2_O_WRONLY) r |= O_WRONLY; - if (flags & IBCS2_O_RDWR) r |= O_RDWR; - if (flags & (IBCS2_O_NDELAY | IBCS2_O_NONBLOCK)) r |= O_NONBLOCK; - if (flags & IBCS2_O_APPEND) r |= O_APPEND; - if (flags & IBCS2_O_SYNC) r |= O_FSYNC; - if (flags & IBCS2_O_CREAT) r |= O_CREAT; - if (flags & IBCS2_O_TRUNC) r |= O_TRUNC /* | O_CREAT ??? */; - if (flags & IBCS2_O_EXCL) r |= O_EXCL; - if (flags & IBCS2_O_RDONLY) r |= O_RDONLY; - if (flags & IBCS2_O_PRIV) r |= O_EXLOCK; - if (flags & IBCS2_O_NOCTTY) r |= O_NOCTTY; - return r; -} - -static void -cvt_flock2iflock(flp, iflp) - struct flock *flp; - struct ibcs2_flock *iflp; -{ - switch (flp->l_type) { - case F_RDLCK: - iflp->l_type = IBCS2_F_RDLCK; - break; - case F_WRLCK: - iflp->l_type = IBCS2_F_WRLCK; - break; - case F_UNLCK: - iflp->l_type = IBCS2_F_UNLCK; - break; - } - iflp->l_whence = (short)flp->l_whence; - iflp->l_start = (ibcs2_off_t)flp->l_start; - iflp->l_len = (ibcs2_off_t)flp->l_len; - iflp->l_sysid = flp->l_sysid; - iflp->l_pid = (ibcs2_pid_t)flp->l_pid; -} - -#ifdef DEBUG_IBCS2 -static void -print_flock(struct flock *flp) -{ - printf("flock: start=%x len=%x pid=%d type=%d whence=%d\n", - (int)flp->l_start, (int)flp->l_len, (int)flp->l_pid, - flp->l_type, flp->l_whence); -} -#endif - -static void -cvt_iflock2flock(iflp, flp) - struct ibcs2_flock *iflp; - struct flock *flp; -{ - flp->l_start = (off_t)iflp->l_start; - flp->l_len = (off_t)iflp->l_len; - flp->l_pid = (pid_t)iflp->l_pid; - switch (iflp->l_type) { - case IBCS2_F_RDLCK: - flp->l_type = F_RDLCK; - break; - case IBCS2_F_WRLCK: - flp->l_type = F_WRLCK; - break; - case IBCS2_F_UNLCK: - flp->l_type = F_UNLCK; - break; - } - flp->l_whence = iflp->l_whence; - flp->l_sysid = iflp->l_sysid; -} - -/* convert iBCS2 mode into NetBSD mode */ -static int -ioflags2oflags(flags) - int flags; -{ - int r = 0; - - if (flags & IBCS2_O_RDONLY) r |= O_RDONLY; - if (flags & IBCS2_O_WRONLY) r |= O_WRONLY; - if (flags & IBCS2_O_RDWR) r |= O_RDWR; - if (flags & IBCS2_O_NDELAY) r |= O_NONBLOCK; - if (flags & IBCS2_O_APPEND) r |= O_APPEND; - if (flags & IBCS2_O_SYNC) r |= O_FSYNC; - if (flags & IBCS2_O_NONBLOCK) r |= O_NONBLOCK; - if (flags & IBCS2_O_CREAT) r |= O_CREAT; - if (flags & IBCS2_O_TRUNC) r |= O_TRUNC; - if (flags & IBCS2_O_EXCL) r |= O_EXCL; - if (flags & IBCS2_O_NOCTTY) r |= O_NOCTTY; - return r; -} - -/* convert NetBSD mode into iBCS2 mode */ -static int -oflags2ioflags(flags) - int flags; -{ - int r = 0; - - if (flags & O_RDONLY) r |= IBCS2_O_RDONLY; - if (flags & O_WRONLY) r |= IBCS2_O_WRONLY; - if (flags & O_RDWR) r |= IBCS2_O_RDWR; - if (flags & O_NDELAY) r |= IBCS2_O_NONBLOCK; - if (flags & O_APPEND) r |= IBCS2_O_APPEND; - if (flags & O_FSYNC) r |= IBCS2_O_SYNC; - if (flags & O_NONBLOCK) r |= IBCS2_O_NONBLOCK; - if (flags & O_CREAT) r |= IBCS2_O_CREAT; - if (flags & O_TRUNC) r |= IBCS2_O_TRUNC; - if (flags & O_EXCL) r |= IBCS2_O_EXCL; - if (flags & O_NOCTTY) r |= IBCS2_O_NOCTTY; - return r; -} - -int -ibcs2_open(td, uap) - struct thread *td; - struct ibcs2_open_args *uap; -{ - struct proc *p; - char *path; - int flags, noctty, ret; - - p = td->td_proc; - noctty = uap->flags & IBCS2_O_NOCTTY; - flags = cvt_o_flags(uap->flags); - if (uap->flags & O_CREAT) - CHECKALTCREAT(td, uap->path, &path); - else - CHECKALTEXIST(td, uap->path, &path); - ret = kern_openat(td, AT_FDCWD, path, UIO_SYSSPACE, flags, uap->mode); - -#ifdef SPX_HACK - if (ret == ENXIO) { - if (!strcmp(path, "/compat/ibcs2/dev/spx")) - ret = spx_open(td); - free(path, M_TEMP); - } else -#endif /* SPX_HACK */ - free(path, M_TEMP); - PROC_LOCK(p); - if (!ret && !noctty && SESS_LEADER(p) && !(p->p_flag & P_CONTROLT)) { - cap_rights_t rights; - struct file *fp; - int error; - - error = fget(td, td->td_retval[0], - cap_rights_init(&rights, CAP_IOCTL), &fp); - PROC_UNLOCK(p); - if (error) - return (EBADF); - - /* ignore any error, just give it a try */ - if (fp->f_type == DTYPE_VNODE) - fo_ioctl(fp, TIOCSCTTY, (caddr_t) 0, td->td_ucred, - td); - fdrop(fp, td); - } else - PROC_UNLOCK(p); - return ret; -} - -int -ibcs2_creat(td, uap) - struct thread *td; - struct ibcs2_creat_args *uap; -{ - char *path; - int error; - - CHECKALTCREAT(td, uap->path, &path); - error = kern_openat(td, AT_FDCWD, path, UIO_SYSSPACE, - O_WRONLY | O_CREAT | O_TRUNC, uap->mode); - free(path, M_TEMP); - return (error); -} - -int -ibcs2_access(td, uap) - struct thread *td; - struct ibcs2_access_args *uap; -{ - char *path; - int error; - - CHECKALTEXIST(td, uap->path, &path); - error = kern_accessat(td, AT_FDCWD, path, UIO_SYSSPACE, 0, uap->amode); - free(path, M_TEMP); - return (error); -} - -int -ibcs2_fcntl(td, uap) - struct thread *td; - struct ibcs2_fcntl_args *uap; -{ - intptr_t arg; - int error; - struct flock fl; - struct ibcs2_flock ifl; - - arg = (intptr_t)uap->arg; - switch(uap->cmd) { - case IBCS2_F_DUPFD: - return (kern_fcntl(td, uap->fd, F_DUPFD, arg)); - case IBCS2_F_GETFD: - return (kern_fcntl(td, uap->fd, F_GETFD, arg)); - case IBCS2_F_SETFD: - return (kern_fcntl(td, uap->fd, F_SETFD, arg)); - case IBCS2_F_GETFL: - error = kern_fcntl(td, uap->fd, F_GETFL, arg); - if (error) - return error; - td->td_retval[0] = oflags2ioflags(td->td_retval[0]); - return error; - case IBCS2_F_SETFL: - return (kern_fcntl(td, uap->fd, F_SETFL, - ioflags2oflags(arg))); - - case IBCS2_F_GETLK: - { - error = copyin((caddr_t)uap->arg, (caddr_t)&ifl, - ibcs2_flock_len); - if (error) - return error; - cvt_iflock2flock(&ifl, &fl); - error = kern_fcntl(td, uap->fd, F_GETLK, (intptr_t)&fl); - if (error) - return error; - cvt_flock2iflock(&fl, &ifl); - return copyout((caddr_t)&ifl, (caddr_t)uap->arg, - ibcs2_flock_len); - } - - case IBCS2_F_SETLK: - { - error = copyin((caddr_t)uap->arg, (caddr_t)&ifl, - ibcs2_flock_len); - if (error) - return error; - cvt_iflock2flock(&ifl, &fl); - return (kern_fcntl(td, uap->fd, F_SETLK, (intptr_t)&fl)); - } - - case IBCS2_F_SETLKW: - { - error = copyin((caddr_t)uap->arg, (caddr_t)&ifl, - ibcs2_flock_len); - if (error) - return error; - cvt_iflock2flock(&ifl, &fl); - return (kern_fcntl(td, uap->fd, F_SETLKW, (intptr_t)&fl)); - } - } - return ENOSYS; -} diff --git a/sys/i386/ibcs2/ibcs2_fcntl.h b/sys/i386/ibcs2/ibcs2_fcntl.h deleted file mode 100644 index 71f080fc722..00000000000 --- a/sys/i386/ibcs2/ibcs2_fcntl.h +++ /dev/null @@ -1,79 +0,0 @@ -/* $NetBSD: ibcs2_fcntl.h,v 1.2 1994/10/26 02:52:54 cgd Exp $ */ - -/*- - * SPDX-License-Identifier: BSD-4-Clause - * - * Copyright (c) 1994 Scott Bartram - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by Scott Bartram. - * 4. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _IBCS2_FCNTL_H -#define _IBCS2_FCNTL_H 1 - -#include - -#define IBCS2_O_RDONLY 0x0000 -#define IBCS2_O_WRONLY 0x0001 -#define IBCS2_O_RDWR 0x0002 -#define IBCS2_O_NDELAY 0x0004 -#define IBCS2_O_APPEND 0x0008 -#define IBCS2_O_SYNC 0x0010 -#define IBCS2_O_NONBLOCK 0x0080 -#define IBCS2_O_CREAT 0x0100 -#define IBCS2_O_TRUNC 0x0200 -#define IBCS2_O_EXCL 0x0400 -#define IBCS2_O_NOCTTY 0x0800 -#define IBCS2_O_PRIV 0x1000 - -#define IBCS2_F_DUPFD 0 -#define IBCS2_F_GETFD 1 -#define IBCS2_F_SETFD 2 -#define IBCS2_F_GETFL 3 -#define IBCS2_F_SETFL 4 -#define IBCS2_F_GETLK 5 -#define IBCS2_F_SETLK 6 -#define IBCS2_F_SETLKW 7 - -struct ibcs2_flock { - short l_type; - short l_whence; - ibcs2_off_t l_start; - ibcs2_off_t l_len; - short l_sysid; - ibcs2_pid_t l_pid; -}; -#define ibcs2_flock_len (sizeof(struct ibcs2_flock)) - -#define IBCS2_F_RDLCK 1 -#define IBCS2_F_WRLCK 2 -#define IBCS2_F_UNLCK 3 - -#define IBCS2_O_ACCMODE 3 -#define IBCS2_FD_CLOEXEC 1 - -#endif /* _IBCS2_FCNTL_H */ diff --git a/sys/i386/ibcs2/ibcs2_ioctl.c b/sys/i386/ibcs2/ibcs2_ioctl.c deleted file mode 100644 index 55217546e59..00000000000 --- a/sys/i386/ibcs2/ibcs2_ioctl.c +++ /dev/null @@ -1,690 +0,0 @@ -/* $NetBSD: ibcs2_ioctl.c,v 1.6 1995/03/14 15:12:28 scottb Exp $ */ - -/*- - * SPDX-License-Identifier: BSD-2-Clause - * - * Copyright (c) 1994, 1995 Scott Bartram - * All rights reserved. - * - * based on compat/sunos/sun_ioctl.c - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include - -static void stios2btios(struct ibcs2_termios *, struct termios *); -static void btios2stios(struct termios *, struct ibcs2_termios *); -static void stios2stio(struct ibcs2_termios *, struct ibcs2_termio *); -static void stio2stios(struct ibcs2_termio *, struct ibcs2_termios *); - -/* - * iBCS2 ioctl calls. - */ - -struct speedtab { - int sp_speed; /* Speed. */ - int sp_code; /* Code. */ -}; - -static struct speedtab sptab[] = { - { 0, 0 }, - { 50, 1 }, - { 75, 2 }, - { 110, 3 }, - { 134, 4 }, - { 135, 4 }, - { 150, 5 }, - { 200, 6 }, - { 300, 7 }, - { 600, 8 }, - { 1200, 9 }, - { 1800, 10 }, - { 2400, 11 }, - { 4800, 12 }, - { 9600, 13 }, - { 19200, 14 }, - { 38400, 15 }, - { -1, -1 } -}; - -static u_long s2btab[] = { - 0, - 50, - 75, - 110, - 134, - 150, - 200, - 300, - 600, - 1200, - 1800, - 2400, - 4800, - 9600, - 19200, - 38400, -}; - -static int -ttspeedtab(int speed, struct speedtab *table) -{ - - for ( ; table->sp_speed != -1; table++) - if (table->sp_speed == speed) - return (table->sp_code); - return (-1); -} - -static void -stios2btios(st, bt) - struct ibcs2_termios *st; - struct termios *bt; -{ - register u_long l, r; - - l = st->c_iflag; r = 0; - if (l & IBCS2_IGNBRK) r |= IGNBRK; - if (l & IBCS2_BRKINT) r |= BRKINT; - if (l & IBCS2_IGNPAR) r |= IGNPAR; - if (l & IBCS2_PARMRK) r |= PARMRK; - if (l & IBCS2_INPCK) r |= INPCK; - if (l & IBCS2_ISTRIP) r |= ISTRIP; - if (l & IBCS2_INLCR) r |= INLCR; - if (l & IBCS2_IGNCR) r |= IGNCR; - if (l & IBCS2_ICRNL) r |= ICRNL; - if (l & IBCS2_IXON) r |= IXON; - if (l & IBCS2_IXANY) r |= IXANY; - if (l & IBCS2_IXOFF) r |= IXOFF; - if (l & IBCS2_IMAXBEL) r |= IMAXBEL; - bt->c_iflag = r; - - l = st->c_oflag; r = 0; - if (l & IBCS2_OPOST) r |= OPOST; - if (l & IBCS2_ONLCR) r |= ONLCR; - if (l & IBCS2_TAB3) r |= TAB3; - bt->c_oflag = r; - - l = st->c_cflag; r = 0; - switch (l & IBCS2_CSIZE) { - case IBCS2_CS5: r |= CS5; break; - case IBCS2_CS6: r |= CS6; break; - case IBCS2_CS7: r |= CS7; break; - case IBCS2_CS8: r |= CS8; break; - } - if (l & IBCS2_CSTOPB) r |= CSTOPB; - if (l & IBCS2_CREAD) r |= CREAD; - if (l & IBCS2_PARENB) r |= PARENB; - if (l & IBCS2_PARODD) r |= PARODD; - if (l & IBCS2_HUPCL) r |= HUPCL; - if (l & IBCS2_CLOCAL) r |= CLOCAL; - bt->c_cflag = r; - - bt->c_ispeed = bt->c_ospeed = s2btab[l & 0x0000000f]; - - l = st->c_lflag; r = 0; - if (l & IBCS2_ISIG) r |= ISIG; - if (l & IBCS2_ICANON) r |= ICANON; - if (l & IBCS2_ECHO) r |= ECHO; - if (l & IBCS2_ECHOE) r |= ECHOE; - if (l & IBCS2_ECHOK) r |= ECHOK; - if (l & IBCS2_ECHONL) r |= ECHONL; - if (l & IBCS2_NOFLSH) r |= NOFLSH; - if (l & IBCS2_TOSTOP) r |= TOSTOP; - bt->c_lflag = r; - - bt->c_cc[VINTR] = - st->c_cc[IBCS2_VINTR] ? st->c_cc[IBCS2_VINTR] : _POSIX_VDISABLE; - bt->c_cc[VQUIT] = - st->c_cc[IBCS2_VQUIT] ? st->c_cc[IBCS2_VQUIT] : _POSIX_VDISABLE; - bt->c_cc[VERASE] = - st->c_cc[IBCS2_VERASE] ? st->c_cc[IBCS2_VERASE] : _POSIX_VDISABLE; - bt->c_cc[VKILL] = - st->c_cc[IBCS2_VKILL] ? st->c_cc[IBCS2_VKILL] : _POSIX_VDISABLE; - if (bt->c_lflag & ICANON) { - bt->c_cc[VEOF] = - st->c_cc[IBCS2_VEOF] ? st->c_cc[IBCS2_VEOF] : _POSIX_VDISABLE; - bt->c_cc[VEOL] = - st->c_cc[IBCS2_VEOL] ? st->c_cc[IBCS2_VEOL] : _POSIX_VDISABLE; - } else { - bt->c_cc[VMIN] = st->c_cc[IBCS2_VMIN]; - bt->c_cc[VTIME] = st->c_cc[IBCS2_VTIME]; - } - bt->c_cc[VEOL2] = - st->c_cc[IBCS2_VEOL2] ? st->c_cc[IBCS2_VEOL2] : _POSIX_VDISABLE; -#if 0 - bt->c_cc[VSWTCH] = - st->c_cc[IBCS2_VSWTCH] ? st->c_cc[IBCS2_VSWTCH] : _POSIX_VDISABLE; -#endif - bt->c_cc[VSTART] = - st->c_cc[IBCS2_VSTART] ? st->c_cc[IBCS2_VSTART] : _POSIX_VDISABLE; - bt->c_cc[VSTOP] = - st->c_cc[IBCS2_VSTOP] ? st->c_cc[IBCS2_VSTOP] : _POSIX_VDISABLE; - bt->c_cc[VSUSP] = - st->c_cc[IBCS2_VSUSP] ? st->c_cc[IBCS2_VSUSP] : _POSIX_VDISABLE; - bt->c_cc[VDSUSP] = _POSIX_VDISABLE; - bt->c_cc[VREPRINT] = _POSIX_VDISABLE; - bt->c_cc[VDISCARD] = _POSIX_VDISABLE; - bt->c_cc[VWERASE] = _POSIX_VDISABLE; - bt->c_cc[VLNEXT] = _POSIX_VDISABLE; - bt->c_cc[VSTATUS] = _POSIX_VDISABLE; -} - -static void -btios2stios(bt, st) - struct termios *bt; - struct ibcs2_termios *st; -{ - register u_long l, r; - - l = bt->c_iflag; r = 0; - if (l & IGNBRK) r |= IBCS2_IGNBRK; - if (l & BRKINT) r |= IBCS2_BRKINT; - if (l & IGNPAR) r |= IBCS2_IGNPAR; - if (l & PARMRK) r |= IBCS2_PARMRK; - if (l & INPCK) r |= IBCS2_INPCK; - if (l & ISTRIP) r |= IBCS2_ISTRIP; - if (l & INLCR) r |= IBCS2_INLCR; - if (l & IGNCR) r |= IBCS2_IGNCR; - if (l & ICRNL) r |= IBCS2_ICRNL; - if (l & IXON) r |= IBCS2_IXON; - if (l & IXANY) r |= IBCS2_IXANY; - if (l & IXOFF) r |= IBCS2_IXOFF; - if (l & IMAXBEL) r |= IBCS2_IMAXBEL; - st->c_iflag = r; - - l = bt->c_oflag; r = 0; - if (l & OPOST) r |= IBCS2_OPOST; - if (l & ONLCR) r |= IBCS2_ONLCR; - if (l & TAB3) r |= IBCS2_TAB3; - st->c_oflag = r; - - l = bt->c_cflag; r = 0; - switch (l & CSIZE) { - case CS5: r |= IBCS2_CS5; break; - case CS6: r |= IBCS2_CS6; break; - case CS7: r |= IBCS2_CS7; break; - case CS8: r |= IBCS2_CS8; break; - } - if (l & CSTOPB) r |= IBCS2_CSTOPB; - if (l & CREAD) r |= IBCS2_CREAD; - if (l & PARENB) r |= IBCS2_PARENB; - if (l & PARODD) r |= IBCS2_PARODD; - if (l & HUPCL) r |= IBCS2_HUPCL; - if (l & CLOCAL) r |= IBCS2_CLOCAL; - st->c_cflag = r; - - l = bt->c_lflag; r = 0; - if (l & ISIG) r |= IBCS2_ISIG; - if (l & ICANON) r |= IBCS2_ICANON; - if (l & ECHO) r |= IBCS2_ECHO; - if (l & ECHOE) r |= IBCS2_ECHOE; - if (l & ECHOK) r |= IBCS2_ECHOK; - if (l & ECHONL) r |= IBCS2_ECHONL; - if (l & NOFLSH) r |= IBCS2_NOFLSH; - if (l & TOSTOP) r |= IBCS2_TOSTOP; - st->c_lflag = r; - - l = ttspeedtab(bt->c_ospeed, sptab); - if ((int)l >= 0) - st->c_cflag |= l; - - st->c_cc[IBCS2_VINTR] = - bt->c_cc[VINTR] != _POSIX_VDISABLE ? bt->c_cc[VINTR] : 0; - st->c_cc[IBCS2_VQUIT] = - bt->c_cc[VQUIT] != _POSIX_VDISABLE ? bt->c_cc[VQUIT] : 0; - st->c_cc[IBCS2_VERASE] = - bt->c_cc[VERASE] != _POSIX_VDISABLE ? bt->c_cc[VERASE] : 0; - st->c_cc[IBCS2_VKILL] = - bt->c_cc[VKILL] != _POSIX_VDISABLE ? bt->c_cc[VKILL] : 0; - if (bt->c_lflag & ICANON) { - st->c_cc[IBCS2_VEOF] = - bt->c_cc[VEOF] != _POSIX_VDISABLE ? bt->c_cc[VEOF] : 0; - st->c_cc[IBCS2_VEOL] = - bt->c_cc[VEOL] != _POSIX_VDISABLE ? bt->c_cc[VEOL] : 0; - } else { - st->c_cc[IBCS2_VMIN] = bt->c_cc[VMIN]; - st->c_cc[IBCS2_VTIME] = bt->c_cc[VTIME]; - } - st->c_cc[IBCS2_VEOL2] = - bt->c_cc[VEOL2] != _POSIX_VDISABLE ? bt->c_cc[VEOL2] : 0; - st->c_cc[IBCS2_VSWTCH] = - 0; - st->c_cc[IBCS2_VSUSP] = - bt->c_cc[VSUSP] != _POSIX_VDISABLE ? bt->c_cc[VSUSP] : 0; - st->c_cc[IBCS2_VSTART] = - bt->c_cc[VSTART] != _POSIX_VDISABLE ? bt->c_cc[VSTART] : 0; - st->c_cc[IBCS2_VSTOP] = - bt->c_cc[VSTOP] != _POSIX_VDISABLE ? bt->c_cc[VSTOP] : 0; - - st->c_line = 0; -} - -static void -stios2stio(ts, t) - struct ibcs2_termios *ts; - struct ibcs2_termio *t; -{ - t->c_iflag = ts->c_iflag; - t->c_oflag = ts->c_oflag; - t->c_cflag = ts->c_cflag; - t->c_lflag = ts->c_lflag; - t->c_line = ts->c_line; - bcopy(ts->c_cc, t->c_cc, IBCS2_NCC); -} - -static void -stio2stios(t, ts) - struct ibcs2_termio *t; - struct ibcs2_termios *ts; -{ - ts->c_iflag = t->c_iflag; - ts->c_oflag = t->c_oflag; - ts->c_cflag = t->c_cflag; - ts->c_lflag = t->c_lflag; - ts->c_line = t->c_line; - bcopy(t->c_cc, ts->c_cc, IBCS2_NCC); -} - -int -ibcs2_ioctl(td, uap) - struct thread *td; - struct ibcs2_ioctl_args *uap; -{ - struct proc *p = td->td_proc; - cap_rights_t rights; - struct file *fp; - int error; - - error = fget(td, uap->fd, cap_rights_init(&rights, CAP_IOCTL), &fp); - if (error != 0) { - DPRINTF(("ibcs2_ioctl(%d): bad fd %d ", p->p_pid, - uap->fd)); - return EBADF; - } - - if ((fp->f_flag & (FREAD|FWRITE)) == 0) { - fdrop(fp, td); - DPRINTF(("ibcs2_ioctl(%d): bad fp flag ", p->p_pid)); - return EBADF; - } - - switch (uap->cmd) { - case IBCS2_TCGETA: - case IBCS2_XCGETA: - case IBCS2_OXCGETA: - { - struct termios bts; - struct ibcs2_termios sts; - struct ibcs2_termio st; - - if ((error = fo_ioctl(fp, TIOCGETA, (caddr_t)&bts, - td->td_ucred, td)) != 0) - break; - - btios2stios (&bts, &sts); - if (uap->cmd == IBCS2_TCGETA) { - stios2stio (&sts, &st); - error = copyout((caddr_t)&st, uap->data, - sizeof (st)); -#ifdef DEBUG_IBCS2 - if (error) - DPRINTF(("ibcs2_ioctl(%d): copyout failed ", - p->p_pid)); -#endif - break; - } else { - error = copyout((caddr_t)&sts, uap->data, - sizeof (sts)); - break; - } - /*NOTREACHED*/ - } - - case IBCS2_TCSETA: - case IBCS2_TCSETAW: - case IBCS2_TCSETAF: - { - struct termios bts; - struct ibcs2_termios sts; - struct ibcs2_termio st; - - if ((error = copyin(uap->data, (caddr_t)&st, - sizeof(st))) != 0) { - DPRINTF(("ibcs2_ioctl(%d): TCSET copyin failed ", - p->p_pid)); - break; - } - - /* get full BSD termios so we don't lose information */ - if ((error = fo_ioctl(fp, TIOCGETA, (caddr_t)&bts, - td->td_ucred, td)) != 0) { - DPRINTF(("ibcs2_ioctl(%d): TCSET ctl failed fd %d ", - p->p_pid, uap->fd)); - break; - } - - /* - * convert to iBCS2 termios, copy in information from - * termio, and convert back, then set new values. - */ - btios2stios(&bts, &sts); - stio2stios(&st, &sts); - stios2btios(&sts, &bts); - - error = fo_ioctl(fp, uap->cmd - IBCS2_TCSETA + TIOCSETA, - (caddr_t)&bts, td->td_ucred, td); - break; - } - - case IBCS2_XCSETA: - case IBCS2_XCSETAW: - case IBCS2_XCSETAF: - { - struct termios bts; - struct ibcs2_termios sts; - - if ((error = copyin(uap->data, (caddr_t)&sts, - sizeof (sts))) != 0) - break; - stios2btios (&sts, &bts); - error = fo_ioctl(fp, uap->cmd - IBCS2_XCSETA + TIOCSETA, - (caddr_t)&bts, td->td_ucred, td); - break; - } - - case IBCS2_OXCSETA: - case IBCS2_OXCSETAW: - case IBCS2_OXCSETAF: - { - struct termios bts; - struct ibcs2_termios sts; - - if ((error = copyin(uap->data, (caddr_t)&sts, - sizeof (sts))) != 0) - break; - stios2btios (&sts, &bts); - error = fo_ioctl(fp, uap->cmd - IBCS2_OXCSETA + TIOCSETA, - (caddr_t)&bts, td->td_ucred, td); - break; - } - - case IBCS2_TCSBRK: - DPRINTF(("ibcs2_ioctl(%d): TCSBRK ", p->p_pid)); - error = ENOSYS; - break; - - case IBCS2_TCXONC: - { - switch ((int)uap->data) { - case 0: - case 1: - DPRINTF(("ibcs2_ioctl(%d): TCXONC ", p->p_pid)); - error = ENOSYS; - break; - case 2: - error = fo_ioctl(fp, TIOCSTOP, (caddr_t)0, - td->td_ucred, td); - break; - case 3: - error = fo_ioctl(fp, TIOCSTART, (caddr_t)1, - td->td_ucred, td); - break; - default: - error = EINVAL; - break; - } - break; - } - - case IBCS2_TCFLSH: - { - int arg; - - switch ((int)uap->data) { - case 0: - arg = FREAD; - break; - case 1: - arg = FWRITE; - break; - case 2: - arg = FREAD | FWRITE; - break; - default: - fdrop(fp, td); - return EINVAL; - } - error = fo_ioctl(fp, TIOCFLUSH, (caddr_t)&arg, td->td_ucred, - td); - break; - } - - case IBCS2_TIOCGWINSZ: - uap->cmd = TIOCGWINSZ; - error = sys_ioctl(td, (struct ioctl_args *)uap); - break; - - case IBCS2_TIOCSWINSZ: - uap->cmd = TIOCSWINSZ; - error = sys_ioctl(td, (struct ioctl_args *)uap); - break; - - case IBCS2_TIOCGPGRP: - { - pid_t pg_id; - - PROC_LOCK(p); - pg_id = p->p_pgrp->pg_id; - PROC_UNLOCK(p); - error = copyout((caddr_t)&pg_id, uap->data, - sizeof(pg_id)); - break; - } - - case IBCS2_TIOCSPGRP: /* XXX - is uap->data a pointer to pgid? */ - { - struct setpgid_args sa; - - sa.pid = 0; - sa.pgid = (int)uap->data; - error = sys_setpgid(td, &sa); - break; - } - - case IBCS2_TCGETSC: /* SCO console - get scancode flags */ - error = EINTR; /* ENOSYS; */ - break; - - case IBCS2_TCSETSC: /* SCO console - set scancode flags */ - error = 0; /* ENOSYS; */ - break; - - case IBCS2_JWINSIZE: /* Unix to Jerq I/O control */ - { - struct ibcs2_jwinsize { - char bytex, bytey; - short bitx, bity; - } ibcs2_jwinsize; - - PROC_LOCK(p); - SESS_LOCK(p->p_session); - ibcs2_jwinsize.bytex = 80; - /* p->p_session->s_ttyp->t_winsize.ws_col; XXX */ - ibcs2_jwinsize.bytey = 25; - /* p->p_session->s_ttyp->t_winsize.ws_row; XXX */ - ibcs2_jwinsize.bitx = - p->p_session->s_ttyp->t_winsize.ws_xpixel; - ibcs2_jwinsize.bity = - p->p_session->s_ttyp->t_winsize.ws_ypixel; - SESS_UNLOCK(p->p_session); - PROC_UNLOCK(p); - error = copyout((caddr_t)&ibcs2_jwinsize, uap->data, - sizeof(ibcs2_jwinsize)); - break; - } - - /* keyboard and display ioctl's -- type 'K' */ - case IBCS2_KDGKBMODE: /* get keyboard translation mode */ - uap->cmd = KDGKBMODE; -/* printf("ioctl KDGKBMODE = %x\n", uap->cmd);*/ - error = sys_ioctl(td, (struct ioctl_args *)uap); - break; - - case IBCS2_KDSKBMODE: /* set keyboard translation mode */ - uap->cmd = KDSKBMODE; - error = sys_ioctl(td, (struct ioctl_args *)uap); - break; - - case IBCS2_KDMKTONE: /* sound tone */ - uap->cmd = KDMKTONE; - error = sys_ioctl(td, (struct ioctl_args *)uap); - break; - - case IBCS2_KDGETMODE: /* get text/graphics mode */ - uap->cmd = KDGETMODE; - error = sys_ioctl(td, (struct ioctl_args *)uap); - break; - - case IBCS2_KDSETMODE: /* set text/graphics mode */ - uap->cmd = KDSETMODE; - error = sys_ioctl(td, (struct ioctl_args *)uap); - break; - - case IBCS2_KDSBORDER: /* set ega color border */ - uap->cmd = KDSBORDER; - error = sys_ioctl(td, (struct ioctl_args *)uap); - break; - - case IBCS2_KDGKBSTATE: - uap->cmd = KDGKBSTATE; - error = sys_ioctl(td, (struct ioctl_args *)uap); - break; - - case IBCS2_KDSETRAD: - uap->cmd = KDSETRAD; - error = sys_ioctl(td, (struct ioctl_args *)uap); - break; - - case IBCS2_KDENABIO: /* enable direct I/O to ports */ - uap->cmd = KDENABIO; - error = sys_ioctl(td, (struct ioctl_args *)uap); - break; - - case IBCS2_KDDISABIO: /* disable direct I/O to ports */ - uap->cmd = KDDISABIO; - error = sys_ioctl(td, (struct ioctl_args *)uap); - break; - - case IBCS2_KIOCSOUND: /* start sound generation */ - uap->cmd = KIOCSOUND; - error = sys_ioctl(td, (struct ioctl_args *)uap); - break; - - case IBCS2_KDGKBTYPE: /* get keyboard type */ - uap->cmd = KDGKBTYPE; - error = sys_ioctl(td, (struct ioctl_args *)uap); - break; - - case IBCS2_KDGETLED: /* get keyboard LED status */ - uap->cmd = KDGETLED; - error = sys_ioctl(td, (struct ioctl_args *)uap); - break; - - case IBCS2_KDSETLED: /* set keyboard LED status */ - uap->cmd = KDSETLED; - error = sys_ioctl(td, (struct ioctl_args *)uap); - break; - - /* Xenix keyboard and display ioctl's from sys/kd.h -- type 'k' */ - case IBCS2_GETFKEY: /* Get function key */ - uap->cmd = GETFKEY; - error = sys_ioctl(td, (struct ioctl_args *)uap); - break; - - case IBCS2_SETFKEY: /* Set function key */ - uap->cmd = SETFKEY; - error = sys_ioctl(td, (struct ioctl_args *)uap); - break; - - case IBCS2_GIO_SCRNMAP: /* Get screen output map table */ - uap->cmd = GIO_SCRNMAP; - error = sys_ioctl(td, (struct ioctl_args *)uap); - break; - - case IBCS2_PIO_SCRNMAP: /* Set screen output map table */ - uap->cmd = PIO_SCRNMAP; - error = sys_ioctl(td, (struct ioctl_args *)uap); - break; - - case IBCS2_GIO_KEYMAP: /* Get keyboard map table */ - uap->cmd = OGIO_KEYMAP; - error = sys_ioctl(td, (struct ioctl_args *)uap); - break; - - case IBCS2_PIO_KEYMAP: /* Set keyboard map table */ - uap->cmd = OPIO_KEYMAP; - error = sys_ioctl(td, (struct ioctl_args *)uap); - break; - - /* socksys */ - case IBCS2_SIOCSOCKSYS: - error = ibcs2_socksys(td, (struct ibcs2_socksys_args *)uap); - break; - - case IBCS2_FIONREAD: - case IBCS2_I_NREAD: /* STREAMS */ - uap->cmd = FIONREAD; - error = sys_ioctl(td, (struct ioctl_args *)uap); - break; - - default: - DPRINTF(("ibcs2_ioctl(%d): unknown cmd 0x%lx ", - td->proc->p_pid, uap->cmd)); - error = ENOSYS; - break; - } - - fdrop(fp, td); - return error; -} diff --git a/sys/i386/ibcs2/ibcs2_ioctl.h b/sys/i386/ibcs2/ibcs2_ioctl.h deleted file mode 100644 index eb66cb00f65..00000000000 --- a/sys/i386/ibcs2/ibcs2_ioctl.h +++ /dev/null @@ -1,55 +0,0 @@ -/* misc IOCTL's */ - -/* Unix to Jerq I/O control */ -#define IBCS2_JTYPE ('j'<<8) -#define IBCS2_JBOOT (IBCS2_JTYPE|1) -#define IBCS2_JTERM (IBCS2_JTYPE|2) -#define IBCS2_JMPX (IBCS2_JTYPE|3) -#define IBCS2_JTIMO (IBCS2_JTYPE|4) -#define IBCS2_JWINSIZE (IBCS2_JTYPE|5) -#define IBCS2_JTIMOM (IBCS2_JTYPE|6) -#define IBCS2_JZOMBOOT (IBCS2_JTYPE|7) -#define IBCS2_JAGENT (IBCS2_JTYPE|9) -#define IBCS2_JTRUN (IBCS2_JTYPE|10) - - -/* Defines for keyboard and display ioctl's */ -#define IBCS2_KIOC ('K'<<8) -#define IBCS2_KDDISPTYPE (IBCS2_KIOC|1) -#define IBCS2_KDMAPDISP (IBCS2_KIOC|2) -#define IBCS2_KDUNMAPDISP (IBCS2_KIOC|3) -#define IBCS2_KDGKBENT (IBCS2_KIOC|4) -#define IBCS2_KDSKBENT (IBCS2_KIOC|5) -#define IBCS2_KDGKBMODE (IBCS2_KIOC|6) -#define IBCS2_KDSKBMODE (IBCS2_KIOC|7) -#define IBCS2_KDMKTONE (IBCS2_KIOC|8) -#define IBCS2_KDGETMODE (IBCS2_KIOC|9) -#define IBCS2_KDSETMODE (IBCS2_KIOC|10) -#define IBCS2_KDADDIO (IBCS2_KIOC|11) -#define IBCS2_KDDELIO (IBCS2_KIOC|12) -#define IBCS2_KDSBORDER (IBCS2_KIOC|13) -#define IBCS2_KDQUEMODE (IBCS2_KIOC|15) -#define IBCS2_KDVDCTYPE (IBCS2_KIOC|16) -#define IBCS2_KDGKBSTATE (IBCS2_KIOC|19) -#define IBCS2_KDSETRAD (IBCS2_KIOC|20) -#define IBCS2_KDENABIO (IBCS2_KIOC|60) -#define IBCS2_KDDISABIO (IBCS2_KIOC|61) -#define IBCS2_KIOCINFO (IBCS2_KIOC|62) -#define IBCS2_KIOCSOUND (IBCS2_KIOC|63) -#define IBCS2_KDGKBTYPE (IBCS2_KIOC|64) -#define IBCS2_KDGETLED (IBCS2_KIOC|65) -#define IBCS2_KDSETLED (IBCS2_KIOC|66) - - -/* Defines for Xenix keyboard and display ioctl's */ -#define IBCS2_MIOC ('k' << 8) -#define IBCS2_GETFKEY (IBCS2_MIOC | 0) -#define IBCS2_SETFKEY (IBCS2_MIOC | 1) -#define IBCS2_GIO_SCRNMAP (IBCS2_MIOC | 2) -#define IBCS2_PIO_SCRNMAP (IBCS2_MIOC | 3) -#define IBCS2_GIO_STRMAP_21 (IBCS2_MIOC | 4) -#define IBCS2_PIO_STRMAP_21 (IBCS2_MIOC | 5) -#define IBCS2_GIO_KEYMAP (IBCS2_MIOC | 6) -#define IBCS2_PIO_KEYMAP (IBCS2_MIOC | 7) -#define IBCS2_GIO_STRMAP (IBCS2_MIOC | 11) -#define IBCS2_PIO_STRMAP (IBCS2_MIOC | 12) diff --git a/sys/i386/ibcs2/ibcs2_ipc.c b/sys/i386/ibcs2/ibcs2_ipc.c deleted file mode 100644 index 19fe166ea85..00000000000 --- a/sys/i386/ibcs2/ibcs2_ipc.c +++ /dev/null @@ -1,561 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 1995 Scott Bartram - * Copyright (c) 1995 Steven Wallace - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#define IBCS2_IPC_RMID 0 -#define IBCS2_IPC_SET 1 -#define IBCS2_IPC_STAT 2 -#define IBCS2_SETVAL 8 - - - -static void cvt_msqid2imsqid(struct msqid_ds *, struct ibcs2_msqid_ds *); -static void cvt_imsqid2msqid(struct ibcs2_msqid_ds *, struct msqid_ds *); -#ifdef unused -static void cvt_sem2isem(struct sem *, struct ibcs2_sem *); -static void cvt_isem2sem(struct ibcs2_sem *, struct sem *); -#endif -static void cvt_semid2isemid(struct semid_ds *, struct ibcs2_semid_ds *); -static void cvt_isemid2semid(struct ibcs2_semid_ds *, struct semid_ds *); -static void cvt_shmid2ishmid(struct shmid_ds *, struct ibcs2_shmid_ds *); -static void cvt_ishmid2shmid(struct ibcs2_shmid_ds *, struct shmid_ds *); -static void cvt_perm2iperm(struct ipc_perm *, struct ibcs2_ipc_perm *); -static void cvt_iperm2perm(struct ibcs2_ipc_perm *, struct ipc_perm *); - - -/* - * iBCS2 msgsys call - */ - -static void -cvt_msqid2imsqid(bp, ibp) -struct msqid_ds *bp; -struct ibcs2_msqid_ds *ibp; -{ - memset(ibp, 0, sizeof(*ibp)); - cvt_perm2iperm(&bp->msg_perm, &ibp->msg_perm); - ibp->msg_cbytes = (u_short)bp->msg_cbytes; - ibp->msg_qnum = (u_short)bp->msg_qnum; - ibp->msg_qbytes = (u_short)bp->msg_qbytes; - ibp->msg_lspid = (u_short)bp->msg_lspid; - ibp->msg_lrpid = (u_short)bp->msg_lrpid; - ibp->msg_stime = bp->msg_stime; - ibp->msg_rtime = bp->msg_rtime; - ibp->msg_ctime = bp->msg_ctime; - return; -} - -static void -cvt_imsqid2msqid(ibp, bp) -struct ibcs2_msqid_ds *ibp; -struct msqid_ds *bp; -{ - cvt_iperm2perm(&ibp->msg_perm, &bp->msg_perm); - bp->msg_cbytes = ibp->msg_cbytes; - bp->msg_qnum = ibp->msg_qnum; - bp->msg_qbytes = ibp->msg_qbytes; - bp->msg_lspid = ibp->msg_lspid; - bp->msg_lrpid = ibp->msg_lrpid; - bp->msg_stime = ibp->msg_stime; - bp->msg_rtime = ibp->msg_rtime; - bp->msg_ctime = ibp->msg_ctime; - return; -} - -struct ibcs2_msgget_args { - int what; - ibcs2_key_t key; - int msgflg; -}; - -static int -ibcs2_msgget(struct thread *td, void *v) -{ - struct ibcs2_msgget_args *uap = v; - struct msgget_args ap; - - ap.key = uap->key; - ap.msgflg = uap->msgflg; - return sys_msgget(td, &ap); -} - -struct ibcs2_msgctl_args { - int what; - int msqid; - int cmd; - struct ibcs2_msqid_ds *buf; -}; - -static int -ibcs2_msgctl(struct thread *td, void *v) -{ - struct ibcs2_msgctl_args *uap = v; - struct ibcs2_msqid_ds is; - struct msqid_ds bs; - int error; - - memset(&is, 0, sizeof(is)); - - switch (uap->cmd) { - case IBCS2_IPC_STAT: - error = kern_msgctl(td, uap->msqid, IPC_STAT, &bs); - if (!error) { - cvt_msqid2imsqid(&bs, &is); - error = copyout(&is, uap->buf, sizeof(is)); - } - return (error); - case IBCS2_IPC_SET: - error = copyin(uap->buf, &is, sizeof(is)); - if (error) - return (error); - cvt_imsqid2msqid(&is, &bs); - return (kern_msgctl(td, uap->msqid, IPC_SET, &bs)); - case IBCS2_IPC_RMID: - return (kern_msgctl(td, uap->msqid, IPC_RMID, NULL)); - } - return (EINVAL); -} - -struct ibcs2_msgrcv_args { - int what; - int msqid; - void *msgp; - size_t msgsz; - long msgtyp; - int msgflg; -}; - -static int -ibcs2_msgrcv(struct thread *td, void *v) -{ - struct ibcs2_msgrcv_args *uap = v; - struct msgrcv_args ap; - - ap.msqid = uap->msqid; - ap.msgp = uap->msgp; - ap.msgsz = uap->msgsz; - ap.msgtyp = uap->msgtyp; - ap.msgflg = uap->msgflg; - return (sys_msgrcv(td, &ap)); -} - -struct ibcs2_msgsnd_args { - int what; - int msqid; - void *msgp; - size_t msgsz; - int msgflg; -}; - -static int -ibcs2_msgsnd(struct thread *td, void *v) -{ - struct ibcs2_msgsnd_args *uap = v; - struct msgsnd_args ap; - - ap.msqid = uap->msqid; - ap.msgp = uap->msgp; - ap.msgsz = uap->msgsz; - ap.msgflg = uap->msgflg; - return (sys_msgsnd(td, &ap)); -} - -int -ibcs2_msgsys(td, uap) - struct thread *td; - struct ibcs2_msgsys_args *uap; -{ - switch (uap->which) { - case 0: - return (ibcs2_msgget(td, uap)); - case 1: - return (ibcs2_msgctl(td, uap)); - case 2: - return (ibcs2_msgrcv(td, uap)); - case 3: - return (ibcs2_msgsnd(td, uap)); - default: - return (EINVAL); - } -} - -/* - * iBCS2 semsys call - */ -#ifdef unused -static void -cvt_sem2isem(bp, ibp) -struct sem *bp; -struct ibcs2_sem *ibp; -{ - ibp->semval = bp->semval; - ibp->sempid = bp->sempid; - ibp->semncnt = bp->semncnt; - ibp->semzcnt = bp->semzcnt; - return; -} - -static void -cvt_isem2sem(ibp, bp) -struct ibcs2_sem *ibp; -struct sem *bp; -{ - bp->semval = ibp->semval; - bp->sempid = ibp->sempid; - bp->semncnt = ibp->semncnt; - bp->semzcnt = ibp->semzcnt; - return; -} -#endif - -static void -cvt_iperm2perm(ipp, pp) -struct ibcs2_ipc_perm *ipp; -struct ipc_perm *pp; -{ - pp->uid = ipp->uid; - pp->gid = ipp->gid; - pp->cuid = ipp->cuid; - pp->cgid = ipp->cgid; - pp->mode = ipp->mode; - pp->seq = ipp->seq; - pp->key = ipp->key; -} - -static void -cvt_perm2iperm(pp, ipp) -struct ipc_perm *pp; -struct ibcs2_ipc_perm *ipp; -{ - ipp->uid = pp->uid; - ipp->gid = pp->gid; - ipp->cuid = pp->cuid; - ipp->cgid = pp->cgid; - ipp->mode = pp->mode; - ipp->seq = pp->seq; - ipp->key = pp->key; -} - -static void -cvt_semid2isemid(bp, ibp) -struct semid_ds *bp; -struct ibcs2_semid_ds *ibp; -{ - memset(ibp, 0, sizeof(*ibp)); - cvt_perm2iperm(&bp->sem_perm, &ibp->sem_perm); - ibp->sem_nsems = bp->sem_nsems; - ibp->sem_otime = bp->sem_otime; - ibp->sem_ctime = bp->sem_ctime; - return; -} - -static void -cvt_isemid2semid(ibp, bp) -struct ibcs2_semid_ds *ibp; -struct semid_ds *bp; -{ - cvt_iperm2perm(&ibp->sem_perm, &bp->sem_perm); - bp->sem_nsems = ibp->sem_nsems; - bp->sem_otime = ibp->sem_otime; - bp->sem_ctime = ibp->sem_ctime; - return; -} - -struct ibcs2_semctl_args { - int what; - int semid; - int semnum; - int cmd; - union semun arg; -}; - -static int -ibcs2_semctl(struct thread *td, void *v) -{ - struct ibcs2_semctl_args *uap = v; - struct ibcs2_semid_ds is; - struct semid_ds bs; - union semun semun; - register_t rval; - int error; - - memset(&is, 0, sizeof(is)); - - switch(uap->cmd) { - case IBCS2_IPC_STAT: - semun.buf = &bs; - error = kern_semctl(td, uap->semid, uap->semnum, IPC_STAT, - &semun, &rval); - if (error) - return (error); - cvt_semid2isemid(&bs, &is); - error = copyout(&is, uap->arg.buf, sizeof(is)); - if (error == 0) - td->td_retval[0] = rval; - return (error); - - case IBCS2_IPC_SET: - error = copyin(uap->arg.buf, &is, sizeof(is)); - if (error) - return (error); - cvt_isemid2semid(&is, &bs); - semun.buf = &bs; - return (kern_semctl(td, uap->semid, uap->semnum, IPC_SET, - &semun, td->td_retval)); - } - - return (kern_semctl(td, uap->semid, uap->semnum, uap->cmd, &uap->arg, - td->td_retval)); -} - -struct ibcs2_semget_args { - int what; - ibcs2_key_t key; - int nsems; - int semflg; -}; - -static int -ibcs2_semget(struct thread *td, void *v) -{ - struct ibcs2_semget_args *uap = v; - struct semget_args ap; - - ap.key = uap->key; - ap.nsems = uap->nsems; - ap.semflg = uap->semflg; - return (sys_semget(td, &ap)); -} - -struct ibcs2_semop_args { - int what; - int semid; - struct sembuf *sops; - size_t nsops; -}; - -static int -ibcs2_semop(struct thread *td, void *v) -{ - struct ibcs2_semop_args *uap = v; - struct semop_args ap; - - ap.semid = uap->semid; - ap.sops = uap->sops; - ap.nsops = uap->nsops; - return (sys_semop(td, &ap)); -} - -int -ibcs2_semsys(td, uap) - struct thread *td; - struct ibcs2_semsys_args *uap; -{ - - switch (uap->which) { - case 0: - return (ibcs2_semctl(td, uap)); - case 1: - return (ibcs2_semget(td, uap)); - case 2: - return (ibcs2_semop(td, uap)); - } - return (EINVAL); -} - - -/* - * iBCS2 shmsys call - */ - -static void -cvt_shmid2ishmid(bp, ibp) -struct shmid_ds *bp; -struct ibcs2_shmid_ds *ibp; -{ - cvt_perm2iperm(&bp->shm_perm, &ibp->shm_perm); - ibp->shm_segsz = bp->shm_segsz; - ibp->shm_lpid = bp->shm_lpid; - ibp->shm_cpid = bp->shm_cpid; - if (bp->shm_nattch > SHRT_MAX) - ibp->shm_nattch = SHRT_MAX; - else - ibp->shm_nattch = bp->shm_nattch; - ibp->shm_cnattch = 0; /* ignored anyway */ - ibp->shm_atime = bp->shm_atime; - ibp->shm_dtime = bp->shm_dtime; - ibp->shm_ctime = bp->shm_ctime; - return; -} - -static void -cvt_ishmid2shmid(ibp, bp) -struct ibcs2_shmid_ds *ibp; -struct shmid_ds *bp; -{ - cvt_iperm2perm(&ibp->shm_perm, &bp->shm_perm); - bp->shm_segsz = ibp->shm_segsz; - bp->shm_lpid = ibp->shm_lpid; - bp->shm_cpid = ibp->shm_cpid; - bp->shm_nattch = ibp->shm_nattch; - bp->shm_atime = ibp->shm_atime; - bp->shm_dtime = ibp->shm_dtime; - bp->shm_ctime = ibp->shm_ctime; - return; -} - -struct ibcs2_shmat_args { - int what; - int shmid; - const void *shmaddr; - int shmflg; -}; - -static int -ibcs2_shmat(struct thread *td, void *v) -{ - struct ibcs2_shmat_args *uap = v; - struct shmat_args ap; - - ap.shmid = uap->shmid; - ap.shmaddr = uap->shmaddr; - ap.shmflg = uap->shmflg; - return (sys_shmat(td, &ap)); -} - -struct ibcs2_shmctl_args { - int what; - int shmid; - int cmd; - struct ibcs2_shmid_ds *buf; -}; - -static int -ibcs2_shmctl(struct thread *td, void *v) -{ - struct ibcs2_shmctl_args *uap = v; - struct ibcs2_shmid_ds is; - struct shmid_ds bs; - int error; - - switch(uap->cmd) { - case IBCS2_IPC_STAT: - error = kern_shmctl(td, uap->shmid, IPC_STAT, &bs, NULL); - if (error) - return (error); - cvt_shmid2ishmid(&bs, &is); - return (copyout(&is, uap->buf, sizeof(is))); - - case IBCS2_IPC_SET: - error = copyin(uap->buf, &is, sizeof(is)); - if (error) - return (error); - cvt_ishmid2shmid(&is, &bs); - return (kern_shmctl(td, uap->shmid, IPC_SET, &bs, NULL)); - - case IPC_INFO: - case SHM_INFO: - case SHM_STAT: - /* XXX: */ - return (EINVAL); - } - - return (kern_shmctl(td, uap->shmid, uap->cmd, NULL, NULL)); -} - -struct ibcs2_shmdt_args { - int what; - const void *shmaddr; -}; - -static int -ibcs2_shmdt(struct thread *td, void *v) -{ - struct ibcs2_shmdt_args *uap = v; - struct shmdt_args ap; - - ap.shmaddr = uap->shmaddr; - return (sys_shmdt(td, &ap)); -} - -struct ibcs2_shmget_args { - int what; - ibcs2_key_t key; - size_t size; - int shmflg; -}; - -static int -ibcs2_shmget(struct thread *td, void *v) -{ - struct ibcs2_shmget_args *uap = v; - struct shmget_args ap; - - ap.key = uap->key; - ap.size = uap->size; - ap.shmflg = uap->shmflg; - return (sys_shmget(td, &ap)); -} - -int -ibcs2_shmsys(td, uap) - struct thread *td; - struct ibcs2_shmsys_args *uap; -{ - - switch (uap->which) { - case 0: - return (ibcs2_shmat(td, uap)); - case 1: - return (ibcs2_shmctl(td, uap)); - case 2: - return (ibcs2_shmdt(td, uap)); - case 3: - return (ibcs2_shmget(td, uap)); - } - return (EINVAL); -} - -MODULE_DEPEND(ibcs2, sysvmsg, 1, 1, 1); -MODULE_DEPEND(ibcs2, sysvsem, 1, 1, 1); -MODULE_DEPEND(ibcs2, sysvshm, 1, 1, 1); diff --git a/sys/i386/ibcs2/ibcs2_ipc.h b/sys/i386/ibcs2/ibcs2_ipc.h deleted file mode 100644 index b6f8d856756..00000000000 --- a/sys/i386/ibcs2/ibcs2_ipc.h +++ /dev/null @@ -1,86 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-4-Clause - * - * Copyright (c) 1995 Steven Wallace - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by Steven Wallace. - * 4. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - - -struct ibcs2_ipc_perm { - u_short uid; /* user id */ - u_short gid; /* group id */ - u_short cuid; /* creator user id */ - u_short cgid; /* creator group id */ - u_short mode; /* r/w permission */ - u_short seq; /* sequence # (to generate unique msg/sem/shm id) */ - ibcs2_key_t key; /* user specified msg/sem/shm key */ -}; - -struct ibcs2_msqid_ds { - struct ibcs2_ipc_perm msg_perm; - struct msg *msg_first; - struct msg *msg_last; - u_short msg_cbytes; - u_short msg_qnum; - u_short msg_qbytes; - u_short msg_lspid; - u_short msg_lrpid; - ibcs2_time_t msg_stime; - ibcs2_time_t msg_rtime; - ibcs2_time_t msg_ctime; -}; - -struct ibcs2_semid_ds { - struct ibcs2_ipc_perm sem_perm; - struct ibcs2_sem *sem_base; - u_short sem_nsems; - ibcs2_time_t sem_otime; - ibcs2_time_t sem_ctime; -}; - -struct ibcs2_sem { - u_short semval; - ibcs2_pid_t sempid; - u_short semncnt; - u_short semzcnt; -}; - -struct ibcs2_shmid_ds { - struct ibcs2_ipc_perm shm_perm; - int shm_segsz; - int pad1; - char pad2[4]; - u_short shm_lpid; - u_short shm_cpid; - u_short shm_nattch; - u_short shm_cnattch; - ibcs2_time_t shm_atime; - ibcs2_time_t shm_dtime; - ibcs2_time_t shm_ctime; -}; diff --git a/sys/i386/ibcs2/ibcs2_isc.c b/sys/i386/ibcs2/ibcs2_isc.c deleted file mode 100644 index c45c6fc75ef..00000000000 --- a/sys/i386/ibcs2/ibcs2_isc.c +++ /dev/null @@ -1,67 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-3-Clause - * - * Copyright (c) 1994 Søren Schmidt - * Copyright (c) 1994 Sean Eric Fagan - * Copyright (c) 1995 Steven Wallace - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer - * in this position and unchanged. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include - -#include -#include -#include -#include -#include -#include - -#include - -#include -#include -#include -#include - -extern struct sysent isc_sysent[]; - -int -ibcs2_isc(struct thread *td, struct ibcs2_isc_args *uap) -{ - struct trapframe *tf = td->td_frame; - struct sysent *callp; - u_int code; - int error; - - code = (tf->tf_eax & 0xffffff00) >> 8; - callp = &isc_sysent[code]; - - if (code < IBCS2_ISC_MAXSYSCALL) - error = (*callp->sy_call)(td, (void *)uap); - else - error = ENOSYS; - return (error); -} diff --git a/sys/i386/ibcs2/ibcs2_isc_syscall.h b/sys/i386/ibcs2/ibcs2_isc_syscall.h deleted file mode 100644 index 54f6ac7e6e9..00000000000 --- a/sys/i386/ibcs2/ibcs2_isc_syscall.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * System call numbers. - * - * DO NOT EDIT-- this file is automatically @generated. - */ - -#define IBCS2_ISC_ibcs2_rename 2 -#define IBCS2_ISC_ibcs2_sigaction 3 -#define IBCS2_ISC_ibcs2_sigprocmask 4 -#define IBCS2_ISC_ibcs2_sigpending 5 -#define IBCS2_ISC_getgroups 6 -#define IBCS2_ISC_setgroups 7 -#define IBCS2_ISC_ibcs2_pathconf 8 -#define IBCS2_ISC_ibcs2_fpathconf 9 -#define IBCS2_ISC_ibcs2_wait 11 -#define IBCS2_ISC_setsid 12 -#define IBCS2_ISC_getpid 13 -#define IBCS2_ISC_ibcs2_sysconf 16 -#define IBCS2_ISC_ibcs2_sigsuspend 17 -#define IBCS2_ISC_ibcs2_symlink 18 -#define IBCS2_ISC_ibcs2_readlink 19 -#define IBCS2_ISC_MAXSYSCALL 21 diff --git a/sys/i386/ibcs2/ibcs2_isc_sysent.c b/sys/i386/ibcs2/ibcs2_isc_sysent.c deleted file mode 100644 index f274edafbda..00000000000 --- a/sys/i386/ibcs2/ibcs2_isc_sysent.c +++ /dev/null @@ -1,40 +0,0 @@ -/* - * System call switch table. - * - * DO NOT EDIT-- this file is automatically @generated. - */ - -#include -#include -#include -#include -#include -#include -#include - -#define AS(name) (sizeof(struct name) / sizeof(register_t)) - -/* The casts are bogus but will do for now. */ -struct sysent isc_sysent[] = { - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 0 = nosys */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 1 = isc_setostype */ - { AS(ibcs2_rename_args), (sy_call_t *)ibcs2_rename, AUE_RENAME, NULL, 0, 0, 0, SY_THR_STATIC }, /* 2 = ibcs2_rename */ - { AS(ibcs2_sigaction_args), (sy_call_t *)ibcs2_sigaction, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 3 = ibcs2_sigaction */ - { AS(ibcs2_sigprocmask_args), (sy_call_t *)ibcs2_sigprocmask, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 4 = ibcs2_sigprocmask */ - { AS(ibcs2_sigpending_args), (sy_call_t *)ibcs2_sigpending, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 5 = ibcs2_sigpending */ - { AS(getgroups_args), (sy_call_t *)sys_getgroups, AUE_GETGROUPS, NULL, 0, 0, 0, SY_THR_STATIC }, /* 6 = getgroups */ - { AS(setgroups_args), (sy_call_t *)sys_setgroups, AUE_SETGROUPS, NULL, 0, 0, 0, SY_THR_STATIC }, /* 7 = setgroups */ - { AS(ibcs2_pathconf_args), (sy_call_t *)ibcs2_pathconf, AUE_PATHCONF, NULL, 0, 0, 0, SY_THR_STATIC }, /* 8 = ibcs2_pathconf */ - { AS(ibcs2_fpathconf_args), (sy_call_t *)ibcs2_fpathconf, AUE_FPATHCONF, NULL, 0, 0, 0, SY_THR_STATIC }, /* 9 = ibcs2_fpathconf */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 10 = nosys */ - { AS(ibcs2_wait_args), (sy_call_t *)ibcs2_wait, AUE_WAIT4, NULL, 0, 0, 0, SY_THR_STATIC }, /* 11 = ibcs2_wait */ - { 0, (sy_call_t *)sys_setsid, AUE_SETSID, NULL, 0, 0, 0, SY_THR_STATIC }, /* 12 = setsid */ - { 0, (sy_call_t *)sys_getpid, AUE_GETPID, NULL, 0, 0, 0, SY_THR_STATIC }, /* 13 = getpid */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 14 = isc_adduser */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 15 = isc_setuser */ - { AS(ibcs2_sysconf_args), (sy_call_t *)ibcs2_sysconf, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 16 = ibcs2_sysconf */ - { AS(ibcs2_sigsuspend_args), (sy_call_t *)ibcs2_sigsuspend, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 17 = ibcs2_sigsuspend */ - { AS(ibcs2_symlink_args), (sy_call_t *)ibcs2_symlink, AUE_SYMLINK, NULL, 0, 0, 0, SY_THR_STATIC }, /* 18 = ibcs2_symlink */ - { AS(ibcs2_readlink_args), (sy_call_t *)ibcs2_readlink, AUE_READLINK, NULL, 0, 0, 0, SY_THR_STATIC }, /* 19 = ibcs2_readlink */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 20 = isc_getmajor */ -}; diff --git a/sys/i386/ibcs2/ibcs2_misc.c b/sys/i386/ibcs2/ibcs2_misc.c deleted file mode 100644 index a6809910b43..00000000000 --- a/sys/i386/ibcs2/ibcs2_misc.c +++ /dev/null @@ -1,1197 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-4-Clause - * - * Copyright (c) 1995 Steven Wallace - * Copyright (c) 1994, 1995 Scott Bartram - * Copyright (c) 1992, 1993 - * The Regents of the University of California. All rights reserved. - * - * This software was developed by the Computer Systems Engineering group - * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and - * contributed to Berkeley. - * - * All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by the University of - * California, Lawrence Berkeley Laboratory. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by the University of - * California, Berkeley and its contributors. - * 4. Neither the name of the University nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * from: Header: sun_misc.c,v 1.16 93/04/07 02:46:27 torek Exp - * - * @(#)sun_misc.c 8.1 (Berkeley) 6/18/93 - */ - -#include - -/* - * IBCS2 compatibility module. - * - * IBCS2 system calls that are implemented differently in BSD are - * handled here. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include /* Must come after sys/malloc.h */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include -#include -#include -#include -#include -#include -#include - -#include - -int -ibcs2_ulimit(struct thread *td, struct ibcs2_ulimit_args *uap) -{ - struct rlimit rl; - int error; -#define IBCS2_GETFSIZE 1 -#define IBCS2_SETFSIZE 2 -#define IBCS2_GETPSIZE 3 -#define IBCS2_GETDTABLESIZE 4 - - switch (uap->cmd) { - case IBCS2_GETFSIZE: - td->td_retval[0] = lim_cur(td, RLIMIT_FSIZE); - if (td->td_retval[0] == -1) - td->td_retval[0] = 0x7fffffff; - return 0; - case IBCS2_SETFSIZE: - rl.rlim_max = lim_max(td, RLIMIT_FSIZE); - rl.rlim_cur = uap->newlimit; - error = kern_setrlimit(td, RLIMIT_FSIZE, &rl); - if (!error) { - td->td_retval[0] = lim_cur(td, RLIMIT_FSIZE); - } else { - DPRINTF(("failed ")); - } - return error; - case IBCS2_GETPSIZE: - td->td_retval[0] = lim_cur(td, RLIMIT_RSS); /* XXX */ - return 0; - case IBCS2_GETDTABLESIZE: - uap->cmd = IBCS2_SC_OPEN_MAX; - return ibcs2_sysconf(td, (struct ibcs2_sysconf_args *)uap); - default: - return ENOSYS; - } -} - -#define IBCS2_WSTOPPED 0177 -#define IBCS2_STOPCODE(sig) ((sig) << 8 | IBCS2_WSTOPPED) -int -ibcs2_wait(struct thread *td, struct ibcs2_wait_args *uap) -{ - int error, options, status; - int *statusp; - pid_t pid; - struct trapframe *tf = td->td_frame; - - if ((tf->tf_eflags & (PSL_Z|PSL_PF|PSL_N|PSL_V)) - == (PSL_Z|PSL_PF|PSL_N|PSL_V)) { - /* waitpid */ - pid = uap->a1; - statusp = (int *)uap->a2; - options = uap->a3; - } else { - /* wait */ - pid = WAIT_ANY; - statusp = (int *)uap->a1; - options = 0; - } - error = kern_wait(td, pid, &status, options, NULL); - if (error) - return error; - if (statusp) { - /* - * Convert status/signal result. - */ - if (WIFSTOPPED(status)) { - if (WSTOPSIG(status) <= 0 || - WSTOPSIG(status) > IBCS2_SIGTBLSZ) - return (EINVAL); - status = - IBCS2_STOPCODE(bsd_to_ibcs2_sig[_SIG_IDX(WSTOPSIG(status))]); - } else if (WIFSIGNALED(status)) { - if (WTERMSIG(status) <= 0 || - WTERMSIG(status) > IBCS2_SIGTBLSZ) - return (EINVAL); - status = bsd_to_ibcs2_sig[_SIG_IDX(WTERMSIG(status))]; - } - /* else exit status -- identical */ - - /* record result/status */ - td->td_retval[1] = status; - return copyout(&status, statusp, sizeof(status)); - } - - return 0; -} - -int -ibcs2_execv(struct thread *td, struct ibcs2_execv_args *uap) -{ - struct image_args eargs; - struct vmspace *oldvmspace; - char *path; - int error; - - CHECKALTEXIST(td, uap->path, &path); - - error = pre_execve(td, &oldvmspace); - if (error != 0) { - free(path, M_TEMP); - return (error); - } - error = exec_copyin_args(&eargs, path, UIO_SYSSPACE, uap->argp, NULL); - free(path, M_TEMP); - if (error == 0) - error = kern_execve(td, &eargs, NULL); - post_execve(td, error, oldvmspace); - return (error); -} - -int -ibcs2_execve(struct thread *td, struct ibcs2_execve_args *uap) -{ - struct image_args eargs; - struct vmspace *oldvmspace; - char *path; - int error; - - CHECKALTEXIST(td, uap->path, &path); - - error = pre_execve(td, &oldvmspace); - if (error != 0) { - free(path, M_TEMP); - return (error); - } - error = exec_copyin_args(&eargs, path, UIO_SYSSPACE, uap->argp, - uap->envp); - free(path, M_TEMP); - if (error == 0) - error = kern_execve(td, &eargs, NULL); - post_execve(td, error, oldvmspace); - return (error); -} - -int -ibcs2_umount(struct thread *td, struct ibcs2_umount_args *uap) -{ - struct unmount_args um; - - um.path = uap->name; - um.flags = 0; - return sys_unmount(td, &um); -} - -int -ibcs2_mount(struct thread *td, struct ibcs2_mount_args *uap) -{ -#ifdef notyet - int oflags = uap->flags, nflags, error; - char fsname[MFSNAMELEN]; - - if (oflags & (IBCS2_MS_NOSUB | IBCS2_MS_SYS5)) - return (EINVAL); - if ((oflags & IBCS2_MS_NEWTYPE) == 0) - return (EINVAL); - nflags = 0; - if (oflags & IBCS2_MS_RDONLY) - nflags |= MNT_RDONLY; - if (oflags & IBCS2_MS_NOSUID) - nflags |= MNT_NOSUID; - if (oflags & IBCS2_MS_REMOUNT) - nflags |= MNT_UPDATE; - uap->flags = nflags; - - if (error = copyinstr((caddr_t)uap->type, fsname, sizeof fsname, - (u_int *)0)) - return (error); - - if (strcmp(fsname, "4.2") == 0) { - uap->type = (caddr_t)STACK_ALLOC(); - if (error = copyout("ufs", uap->type, sizeof("ufs"))) - return (error); - } else if (strcmp(fsname, "nfs") == 0) { - struct ibcs2_nfs_args sna; - struct sockaddr_in sain; - struct nfs_args na; - struct sockaddr sa; - - if (error = copyin(uap->data, &sna, sizeof sna)) - return (error); - if (error = copyin(sna.addr, &sain, sizeof sain)) - return (error); - bcopy(&sain, &sa, sizeof sa); - sa.sa_len = sizeof(sain); - uap->data = (caddr_t)STACK_ALLOC(); - na.addr = (struct sockaddr *)((int)uap->data + sizeof na); - na.sotype = SOCK_DGRAM; - na.proto = IPPROTO_UDP; - na.fh = (nfsv2fh_t *)sna.fh; - na.flags = sna.flags; - na.wsize = sna.wsize; - na.rsize = sna.rsize; - na.timeo = sna.timeo; - na.retrans = sna.retrans; - na.hostname = sna.hostname; - - if (error = copyout(&sa, na.addr, sizeof sa)) - return (error); - if (error = copyout(&na, uap->data, sizeof na)) - return (error); - } - return (mount(td, uap)); -#else - return EINVAL; -#endif -} - -/* - * Read iBCS2-style directory entries. We suck them into kernel space so - * that they can be massaged before being copied out to user code. Like - * SunOS, we squish out `empty' entries. - * - * This is quite ugly, but what do you expect from compatibility code? - */ - -int -ibcs2_getdents(struct thread *td, struct ibcs2_getdents_args *uap) -{ - struct vnode *vp; - caddr_t inp, buf; /* BSD-format */ - int len, reclen; /* BSD-format */ - caddr_t outp; /* iBCS2-format */ - int resid; /* iBCS2-format */ - cap_rights_t rights; - struct file *fp; - struct uio auio; - struct iovec aiov; - struct ibcs2_dirent idb; - off_t off; /* true file offset */ - int buflen, error, eofflag; - u_long *cookies = NULL, *cookiep; - int ncookies; -#define BSD_DIRENT(cp) ((struct dirent *)(cp)) -#define IBCS2_RECLEN(reclen) (reclen + sizeof(u_short)) - - memset(&idb, 0, sizeof(idb)); - error = getvnode(td, uap->fd, cap_rights_init(&rights, CAP_READ), &fp); - if (error != 0) - return (error); - if ((fp->f_flag & FREAD) == 0) { - fdrop(fp, td); - return (EBADF); - } - vp = fp->f_vnode; - if (vp->v_type != VDIR) { /* XXX vnode readdir op should do this */ - fdrop(fp, td); - return (EINVAL); - } - - off = fp->f_offset; -#define DIRBLKSIZ 512 /* XXX we used to use ufs's DIRBLKSIZ */ - buflen = max(DIRBLKSIZ, uap->nbytes); - buflen = min(buflen, MAXBSIZE); - buf = malloc(buflen, M_TEMP, M_WAITOK); - vn_lock(vp, LK_SHARED | LK_RETRY); -again: - aiov.iov_base = buf; - aiov.iov_len = buflen; - auio.uio_iov = &aiov; - auio.uio_iovcnt = 1; - auio.uio_rw = UIO_READ; - auio.uio_segflg = UIO_SYSSPACE; - auio.uio_td = td; - auio.uio_resid = buflen; - auio.uio_offset = off; - - if (cookies) { - free(cookies, M_TEMP); - cookies = NULL; - } - -#ifdef MAC - error = mac_vnode_check_readdir(td->td_ucred, vp); - if (error) - goto out; -#endif - - /* - * First we read into the malloc'ed buffer, then - * we massage it into user space, one record at a time. - */ - if ((error = VOP_READDIR(vp, &auio, fp->f_cred, &eofflag, &ncookies, &cookies)) != 0) - goto out; - inp = buf; - outp = uap->buf; - resid = uap->nbytes; - if ((len = buflen - auio.uio_resid) <= 0) - goto eof; - - cookiep = cookies; - - if (cookies) { - /* - * When using cookies, the vfs has the option of reading from - * a different offset than that supplied (UFS truncates the - * offset to a block boundary to make sure that it never reads - * partway through a directory entry, even if the directory - * has been compacted). - */ - while (len > 0 && ncookies > 0 && *cookiep <= off) { - len -= BSD_DIRENT(inp)->d_reclen; - inp += BSD_DIRENT(inp)->d_reclen; - cookiep++; - ncookies--; - } - } - - for (; len > 0; len -= reclen) { - if (cookiep && ncookies == 0) - break; - reclen = BSD_DIRENT(inp)->d_reclen; - if (reclen & 3) { - printf("ibcs2_getdents: reclen=%d\n", reclen); - error = EFAULT; - goto out; - } - if (BSD_DIRENT(inp)->d_fileno == 0) { - inp += reclen; /* it is a hole; squish it out */ - if (cookiep) { - off = *cookiep++; - ncookies--; - } else - off += reclen; - continue; - } - if (reclen > len || resid < IBCS2_RECLEN(reclen)) { - /* entry too big for buffer, so just stop */ - outp++; - break; - } - /* - * Massage in place to make an iBCS2-shaped dirent (otherwise - * we have to worry about touching user memory outside of - * the copyout() call). - */ - idb.d_ino = (ibcs2_ino_t)BSD_DIRENT(inp)->d_fileno; - idb.d_off = (ibcs2_off_t)off; - idb.d_reclen = (u_short)IBCS2_RECLEN(reclen); - if ((error = copyout((caddr_t)&idb, outp, 10)) != 0 || - (error = copyout(BSD_DIRENT(inp)->d_name, outp + 10, - BSD_DIRENT(inp)->d_namlen + 1)) != 0) - goto out; - /* advance past this real entry */ - if (cookiep) { - off = *cookiep++; - ncookies--; - } else - off += reclen; - inp += reclen; - /* advance output past iBCS2-shaped entry */ - outp += IBCS2_RECLEN(reclen); - resid -= IBCS2_RECLEN(reclen); - } - /* if we squished out the whole block, try again */ - if (outp == uap->buf) - goto again; - fp->f_offset = off; /* update the vnode offset */ -eof: - td->td_retval[0] = uap->nbytes - resid; -out: - VOP_UNLOCK(vp, 0); - fdrop(fp, td); - if (cookies) - free(cookies, M_TEMP); - free(buf, M_TEMP); - return (error); -} - -int -ibcs2_read(struct thread *td, struct ibcs2_read_args *uap) -{ - struct vnode *vp; - caddr_t inp, buf; /* BSD-format */ - int len, reclen; /* BSD-format */ - caddr_t outp; /* iBCS2-format */ - int resid; /* iBCS2-format */ - cap_rights_t rights; - struct file *fp; - struct uio auio; - struct iovec aiov; - struct ibcs2_direct { - ibcs2_ino_t ino; - char name[14]; - } idb; - off_t off; /* true file offset */ - int buflen, error, eofflag, size; - u_long *cookies = NULL, *cookiep; - int ncookies; - - error = getvnode(td, uap->fd, cap_rights_init(&rights, CAP_READ), &fp); - if (error != 0) { - if (error == EINVAL) - return sys_read(td, (struct read_args *)uap); - else - return error; - } - if ((fp->f_flag & FREAD) == 0) { - fdrop(fp, td); - return (EBADF); - } - vp = fp->f_vnode; - if (vp->v_type != VDIR) { - fdrop(fp, td); - return sys_read(td, (struct read_args *)uap); - } - - off = fp->f_offset; - - DPRINTF(("ibcs2_read: read directory\n")); - - buflen = max(DIRBLKSIZ, uap->nbytes); - buflen = min(buflen, MAXBSIZE); - buf = malloc(buflen, M_TEMP, M_WAITOK); - vn_lock(vp, LK_SHARED | LK_RETRY); -again: - aiov.iov_base = buf; - aiov.iov_len = buflen; - auio.uio_iov = &aiov; - auio.uio_iovcnt = 1; - auio.uio_rw = UIO_READ; - auio.uio_segflg = UIO_SYSSPACE; - auio.uio_td = td; - auio.uio_resid = buflen; - auio.uio_offset = off; - - if (cookies) { - free(cookies, M_TEMP); - cookies = NULL; - } - -#ifdef MAC - error = mac_vnode_check_readdir(td->td_ucred, vp); - if (error) - goto out; -#endif - - /* - * First we read into the malloc'ed buffer, then - * we massage it into user space, one record at a time. - */ - if ((error = VOP_READDIR(vp, &auio, fp->f_cred, &eofflag, &ncookies, &cookies)) != 0) { - DPRINTF(("VOP_READDIR failed: %d\n", error)); - goto out; - } - inp = buf; - outp = uap->buf; - resid = uap->nbytes; - if ((len = buflen - auio.uio_resid) <= 0) - goto eof; - - cookiep = cookies; - - if (cookies) { - /* - * When using cookies, the vfs has the option of reading from - * a different offset than that supplied (UFS truncates the - * offset to a block boundary to make sure that it never reads - * partway through a directory entry, even if the directory - * has been compacted). - */ - while (len > 0 && ncookies > 0 && *cookiep <= off) { - len -= BSD_DIRENT(inp)->d_reclen; - inp += BSD_DIRENT(inp)->d_reclen; - cookiep++; - ncookies--; - } - } - - for (; len > 0 && resid > 0; len -= reclen) { - if (cookiep && ncookies == 0) - break; - reclen = BSD_DIRENT(inp)->d_reclen; - if (reclen & 3) { - printf("ibcs2_read: reclen=%d\n", reclen); - error = EFAULT; - goto out; - } - if (BSD_DIRENT(inp)->d_fileno == 0) { - inp += reclen; /* it is a hole; squish it out */ - if (cookiep) { - off = *cookiep++; - ncookies--; - } else - off += reclen; - continue; - } - if (reclen > len || resid < sizeof(struct ibcs2_direct)) { - /* entry too big for buffer, so just stop */ - outp++; - break; - } - /* - * Massage in place to make an iBCS2-shaped dirent (otherwise - * we have to worry about touching user memory outside of - * the copyout() call). - * - * TODO: if length(filename) > 14, then break filename into - * multiple entries and set inode = 0xffff except last - */ - idb.ino = (BSD_DIRENT(inp)->d_fileno > 0xfffe) ? 0xfffe : - BSD_DIRENT(inp)->d_fileno; - (void)copystr(BSD_DIRENT(inp)->d_name, idb.name, 14, &size); - bzero(idb.name + size, 14 - size); - if ((error = copyout(&idb, outp, sizeof(struct ibcs2_direct))) != 0) - goto out; - /* advance past this real entry */ - if (cookiep) { - off = *cookiep++; - ncookies--; - } else - off += reclen; - inp += reclen; - /* advance output past iBCS2-shaped entry */ - outp += sizeof(struct ibcs2_direct); - resid -= sizeof(struct ibcs2_direct); - } - /* if we squished out the whole block, try again */ - if (outp == uap->buf) - goto again; - fp->f_offset = off; /* update the vnode offset */ -eof: - td->td_retval[0] = uap->nbytes - resid; -out: - VOP_UNLOCK(vp, 0); - fdrop(fp, td); - if (cookies) - free(cookies, M_TEMP); - free(buf, M_TEMP); - return (error); -} - -int -ibcs2_mknod(struct thread *td, struct ibcs2_mknod_args *uap) -{ - char *path; - int error; - - CHECKALTCREAT(td, uap->path, &path); - if (S_ISFIFO(uap->mode)) { - error = kern_mkfifoat(td, AT_FDCWD, path, - UIO_SYSSPACE, uap->mode); - } else { - error = kern_mknodat(td, AT_FDCWD, path, UIO_SYSSPACE, - uap->mode, uap->dev); - } - free(path, M_TEMP); - return (error); -} - -int -ibcs2_getgroups(struct thread *td, struct ibcs2_getgroups_args *uap) -{ - struct ucred *cred; - ibcs2_gid_t *iset; - u_int i, ngrp; - int error; - - cred = td->td_ucred; - ngrp = cred->cr_ngroups; - - if (uap->gidsetsize == 0) { - error = 0; - goto out; - } - if (uap->gidsetsize < ngrp) - return (EINVAL); - - iset = malloc(ngrp * sizeof(*iset), M_TEMP, M_WAITOK); - for (i = 0; i < ngrp; i++) - iset[i] = (ibcs2_gid_t)cred->cr_groups[i]; - error = copyout(iset, uap->gidset, ngrp * sizeof(ibcs2_gid_t)); - free(iset, M_TEMP); -out: - td->td_retval[0] = ngrp; - return (error); -} - -int -ibcs2_setgroups(struct thread *td, struct ibcs2_setgroups_args *uap) -{ - ibcs2_gid_t *iset; - gid_t *gp; - int error, i; - - if (uap->gidsetsize < 0 || uap->gidsetsize > ngroups_max + 1) - return (EINVAL); - if (uap->gidsetsize && uap->gidset == NULL) - return (EINVAL); - gp = malloc(uap->gidsetsize * sizeof(*gp), M_TEMP, M_WAITOK); - if (uap->gidsetsize) { - iset = malloc(uap->gidsetsize * sizeof(*iset), M_TEMP, M_WAITOK); - error = copyin(uap->gidset, iset, sizeof(ibcs2_gid_t) * - uap->gidsetsize); - if (error) { - free(iset, M_TEMP); - goto out; - } - for (i = 0; i < uap->gidsetsize; i++) - gp[i] = (gid_t)iset[i]; - } - - error = kern_setgroups(td, uap->gidsetsize, gp); -out: - free(gp, M_TEMP); - return (error); -} - -int -ibcs2_setuid(struct thread *td, struct ibcs2_setuid_args *uap) -{ - struct setuid_args sa; - - sa.uid = (uid_t)uap->uid; - return sys_setuid(td, &sa); -} - -int -ibcs2_setgid(struct thread *td, struct ibcs2_setgid_args *uap) -{ - struct setgid_args sa; - - sa.gid = (gid_t)uap->gid; - return sys_setgid(td, &sa); -} - -int -ibcs2_time(struct thread *td, struct ibcs2_time_args *uap) -{ - struct timeval tv; - - microtime(&tv); - td->td_retval[0] = tv.tv_sec; - if (uap->tp) - return copyout((caddr_t)&tv.tv_sec, (caddr_t)uap->tp, - sizeof(ibcs2_time_t)); - else - return 0; -} - -int -ibcs2_pathconf(struct thread *td, struct ibcs2_pathconf_args *uap) -{ - char *path; - long value; - int error; - - CHECKALTEXIST(td, uap->path, &path); - uap->name++; /* iBCS2 _PC_* defines are offset by one */ - error = kern_pathconf(td, path, UIO_SYSSPACE, uap->name, FOLLOW, - &value); - free(path, M_TEMP); - if (error == 0) - td->td_retval[0] = value; - return (error); -} - -int -ibcs2_fpathconf(struct thread *td, struct ibcs2_fpathconf_args *uap) -{ - uap->name++; /* iBCS2 _PC_* defines are offset by one */ - return sys_fpathconf(td, (struct fpathconf_args *)uap); -} - -int -ibcs2_sysconf(struct thread *td, struct ibcs2_sysconf_args *uap) -{ - int mib[2], value, len, error; - - switch(uap->name) { - case IBCS2_SC_ARG_MAX: - mib[1] = KERN_ARGMAX; - break; - - case IBCS2_SC_CHILD_MAX: - td->td_retval[0] = lim_cur(td, RLIMIT_NPROC); - return 0; - - case IBCS2_SC_CLK_TCK: - td->td_retval[0] = hz; - return 0; - - case IBCS2_SC_NGROUPS_MAX: - mib[1] = KERN_NGROUPS; - break; - - case IBCS2_SC_OPEN_MAX: - td->td_retval[0] = lim_cur(td, RLIMIT_NOFILE); - return 0; - - case IBCS2_SC_JOB_CONTROL: - mib[1] = KERN_JOB_CONTROL; - break; - - case IBCS2_SC_SAVED_IDS: - mib[1] = KERN_SAVED_IDS; - break; - - case IBCS2_SC_VERSION: - mib[1] = KERN_POSIX1; - break; - - case IBCS2_SC_PASS_MAX: - td->td_retval[0] = 128; /* XXX - should we create PASS_MAX ? */ - return 0; - - case IBCS2_SC_XOPEN_VERSION: - td->td_retval[0] = 2; /* XXX: What should that be? */ - return 0; - - default: - return EINVAL; - } - - mib[0] = CTL_KERN; - len = sizeof(value); - error = kernel_sysctl(td, mib, 2, &value, &len, NULL, 0, NULL, 0); - if (error) - return error; - td->td_retval[0] = value; - return 0; -} - -int -ibcs2_alarm(struct thread *td, struct ibcs2_alarm_args *uap) -{ - struct itimerval itv, oitv; - int error; - - timevalclear(&itv.it_interval); - itv.it_value.tv_sec = uap->sec; - itv.it_value.tv_usec = 0; - error = kern_setitimer(td, ITIMER_REAL, &itv, &oitv); - if (error) - return (error); - if (oitv.it_value.tv_usec != 0) - oitv.it_value.tv_sec++; - td->td_retval[0] = oitv.it_value.tv_sec; - return (0); -} - -int -ibcs2_times(struct thread *td, struct ibcs2_times_args *uap) -{ - struct rusage ru; - struct timeval t; - struct tms tms; - int error; - -#define CONVTCK(r) (r.tv_sec * hz + r.tv_usec / (1000000 / hz)) - - error = kern_getrusage(td, RUSAGE_SELF, &ru); - if (error) - return (error); - tms.tms_utime = CONVTCK(ru.ru_utime); - tms.tms_stime = CONVTCK(ru.ru_stime); - - error = kern_getrusage(td, RUSAGE_CHILDREN, &ru); - if (error) - return (error); - tms.tms_cutime = CONVTCK(ru.ru_utime); - tms.tms_cstime = CONVTCK(ru.ru_stime); - - microtime(&t); - td->td_retval[0] = CONVTCK(t); - - return (copyout(&tms, uap->tp, sizeof(struct tms))); -} - -int -ibcs2_stime(struct thread *td, struct ibcs2_stime_args *uap) -{ - struct timeval tv; - long secs; - int error; - - error = copyin(uap->timep, &secs, sizeof(long)); - if (error) - return (error); - tv.tv_sec = secs; - tv.tv_usec = 0; - error = kern_settimeofday(td, &tv, NULL); - if (error) - error = EPERM; - return (error); -} - -int -ibcs2_utime(struct thread *td, struct ibcs2_utime_args *uap) -{ - struct ibcs2_utimbuf ubuf; - struct timeval tbuf[2], *tp; - char *path; - int error; - - if (uap->buf) { - error = copyin(uap->buf, &ubuf, sizeof(ubuf)); - if (error) - return (error); - tbuf[0].tv_sec = ubuf.actime; - tbuf[0].tv_usec = 0; - tbuf[1].tv_sec = ubuf.modtime; - tbuf[1].tv_usec = 0; - tp = tbuf; - } else - tp = NULL; - - CHECKALTEXIST(td, uap->path, &path); - error = kern_utimesat(td, AT_FDCWD, path, UIO_SYSSPACE, - tp, UIO_SYSSPACE); - free(path, M_TEMP); - return (error); -} - -int -ibcs2_nice(struct thread *td, struct ibcs2_nice_args *uap) -{ - int error; - struct setpriority_args sa; - - sa.which = PRIO_PROCESS; - sa.who = 0; - sa.prio = td->td_proc->p_nice + uap->incr; - if ((error = sys_setpriority(td, &sa)) != 0) - return EPERM; - td->td_retval[0] = td->td_proc->p_nice; - return 0; -} - -/* - * iBCS2 getpgrp, setpgrp, setsid, and setpgid - */ - -int -ibcs2_pgrpsys(struct thread *td, struct ibcs2_pgrpsys_args *uap) -{ - struct proc *p = td->td_proc; - switch (uap->type) { - case 0: /* getpgrp */ - PROC_LOCK(p); - td->td_retval[0] = p->p_pgrp->pg_id; - PROC_UNLOCK(p); - return 0; - - case 1: /* setpgrp */ - { - struct setpgid_args sa; - - sa.pid = 0; - sa.pgid = 0; - sys_setpgid(td, &sa); - PROC_LOCK(p); - td->td_retval[0] = p->p_pgrp->pg_id; - PROC_UNLOCK(p); - return 0; - } - - case 2: /* setpgid */ - { - struct setpgid_args sa; - - sa.pid = uap->pid; - sa.pgid = uap->pgid; - return sys_setpgid(td, &sa); - } - - case 3: /* setsid */ - return sys_setsid(td, NULL); - - default: - return EINVAL; - } -} - -/* - * XXX - need to check for nested calls - */ - -int -ibcs2_plock(struct thread *td, struct ibcs2_plock_args *uap) -{ - int error; -#define IBCS2_UNLOCK 0 -#define IBCS2_PROCLOCK 1 -#define IBCS2_TEXTLOCK 2 -#define IBCS2_DATALOCK 4 - - - switch(uap->cmd) { - case IBCS2_UNLOCK: - error = priv_check(td, PRIV_VM_MUNLOCK); - if (error) - return (error); - /* XXX - TODO */ - return (0); - - case IBCS2_PROCLOCK: - case IBCS2_TEXTLOCK: - case IBCS2_DATALOCK: - error = priv_check(td, PRIV_VM_MLOCK); - if (error) - return (error); - /* XXX - TODO */ - return 0; - } - return EINVAL; -} - -int -ibcs2_uadmin(struct thread *td, struct ibcs2_uadmin_args *uap) -{ -#define SCO_A_REBOOT 1 -#define SCO_A_SHUTDOWN 2 -#define SCO_A_REMOUNT 4 -#define SCO_A_CLOCK 8 -#define SCO_A_SETCONFIG 128 -#define SCO_A_GETDEV 130 - -#define SCO_AD_HALT 0 -#define SCO_AD_BOOT 1 -#define SCO_AD_IBOOT 2 -#define SCO_AD_PWRDOWN 3 -#define SCO_AD_PWRNAP 4 - -#define SCO_AD_PANICBOOT 1 - -#define SCO_AD_GETBMAJ 0 -#define SCO_AD_GETCMAJ 1 - - switch(uap->cmd) { - case SCO_A_REBOOT: - case SCO_A_SHUTDOWN: - switch(uap->func) { - struct reboot_args r; - case SCO_AD_HALT: - case SCO_AD_PWRDOWN: - case SCO_AD_PWRNAP: - r.opt = RB_HALT; - return (sys_reboot(td, &r)); - case SCO_AD_BOOT: - case SCO_AD_IBOOT: - r.opt = RB_AUTOBOOT; - return (sys_reboot(td, &r)); - } - return EINVAL; - case SCO_A_REMOUNT: - case SCO_A_CLOCK: - case SCO_A_SETCONFIG: - return 0; - case SCO_A_GETDEV: - return EINVAL; /* XXX - TODO */ - } - return EINVAL; -} - -int -ibcs2_sysfs(struct thread *td, struct ibcs2_sysfs_args *uap) -{ -#define IBCS2_GETFSIND 1 -#define IBCS2_GETFSTYP 2 -#define IBCS2_GETNFSTYP 3 - - switch(uap->cmd) { - case IBCS2_GETFSIND: - case IBCS2_GETFSTYP: - case IBCS2_GETNFSTYP: - break; - } - return EINVAL; /* XXX - TODO */ -} - -int -ibcs2_unlink(struct thread *td, struct ibcs2_unlink_args *uap) -{ - char *path; - int error; - - CHECKALTEXIST(td, uap->path, &path); - error = kern_unlinkat(td, AT_FDCWD, path, UIO_SYSSPACE, 0); - free(path, M_TEMP); - return (error); -} - -int -ibcs2_chdir(struct thread *td, struct ibcs2_chdir_args *uap) -{ - char *path; - int error; - - CHECKALTEXIST(td, uap->path, &path); - error = kern_chdir(td, path, UIO_SYSSPACE); - free(path, M_TEMP); - return (error); -} - -int -ibcs2_chmod(struct thread *td, struct ibcs2_chmod_args *uap) -{ - char *path; - int error; - - CHECKALTEXIST(td, uap->path, &path); - error = kern_fchmodat(td, AT_FDCWD, path, UIO_SYSSPACE, uap->mode, 0); - free(path, M_TEMP); - return (error); -} - -int -ibcs2_chown(struct thread *td, struct ibcs2_chown_args *uap) -{ - char *path; - int error; - - CHECKALTEXIST(td, uap->path, &path); - error = kern_fchownat(td, AT_FDCWD, path, UIO_SYSSPACE, uap->uid, - uap->gid, 0); - free(path, M_TEMP); - return (error); -} - -int -ibcs2_rmdir(struct thread *td, struct ibcs2_rmdir_args *uap) -{ - char *path; - int error; - - CHECKALTEXIST(td, uap->path, &path); - error = kern_rmdirat(td, AT_FDCWD, path, UIO_SYSSPACE); - free(path, M_TEMP); - return (error); -} - -int -ibcs2_mkdir(struct thread *td, struct ibcs2_mkdir_args *uap) -{ - char *path; - int error; - - CHECKALTEXIST(td, uap->path, &path); - error = kern_mkdirat(td, AT_FDCWD, path, UIO_SYSSPACE, uap->mode); - free(path, M_TEMP); - return (error); -} - -int -ibcs2_symlink(struct thread *td, struct ibcs2_symlink_args *uap) -{ - char *path, *link; - int error; - - CHECKALTEXIST(td, uap->path, &path); - - /* - * Have to expand CHECKALTCREAT() so that 'path' can be freed on - * errors. - */ - error = ibcs2_emul_find(td, uap->link, UIO_USERSPACE, &link, 1); - if (link == NULL) { - free(path, M_TEMP); - return (error); - } - error = kern_symlinkat(td, path, AT_FDCWD, link, UIO_SYSSPACE); - free(path, M_TEMP); - free(link, M_TEMP); - return (error); -} - -int -ibcs2_rename(struct thread *td, struct ibcs2_rename_args *uap) -{ - char *from, *to; - int error; - - CHECKALTEXIST(td, uap->from, &from); - - /* - * Have to expand CHECKALTCREAT() so that 'from' can be freed on - * errors. - */ - error = ibcs2_emul_find(td, uap->to, UIO_USERSPACE, &to, 1); - if (to == NULL) { - free(from, M_TEMP); - return (error); - } - error = kern_renameat(td, AT_FDCWD, from, AT_FDCWD, to, UIO_SYSSPACE); - free(from, M_TEMP); - free(to, M_TEMP); - return (error); -} - -int -ibcs2_readlink(struct thread *td, struct ibcs2_readlink_args *uap) -{ - char *path; - int error; - - CHECKALTEXIST(td, uap->path, &path); - error = kern_readlinkat(td, AT_FDCWD, path, UIO_SYSSPACE, - uap->buf, UIO_USERSPACE, uap->count); - free(path, M_TEMP); - return (error); -} diff --git a/sys/i386/ibcs2/ibcs2_mount.h b/sys/i386/ibcs2/ibcs2_mount.h deleted file mode 100644 index 3e1ebf6d30b..00000000000 --- a/sys/i386/ibcs2/ibcs2_mount.h +++ /dev/null @@ -1,43 +0,0 @@ -/* $NetBSD: ibcs2_mount.h,v 1.2 1994/10/26 02:53:00 cgd Exp $ */ - -/*- - * SPDX-License-Identifier: BSD-4-Clause - * - * Copyright (c) 1994 Scott Bartram - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by Scott Bartram. - * 4. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _IBCS2_MOUNT_H -#define _IBCS2_MOUNT_H - -#define IBCS2_MS_RDONLY 0x01 -#define IBCS2_MS_FSS 0x02 -#define IBCS2_MS_DATA 0x04 -#define IBCS2_MS_CACHE 0x08 - -#endif /* _IBCS2_MOUNT_H */ diff --git a/sys/i386/ibcs2/ibcs2_msg.c b/sys/i386/ibcs2/ibcs2_msg.c deleted file mode 100644 index 3e0f65213e7..00000000000 --- a/sys/i386/ibcs2/ibcs2_msg.c +++ /dev/null @@ -1,59 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 1995 Steven Wallace - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include - -/* - * IBCS2 message compatibility module. - * - */ - -#include -#include -#include -#include - -#include -#include -#include -#include - - -int -ibcs2_getmsg(td, uap) - struct thread *td; - struct ibcs2_getmsg_args *uap; -{ - return 0; /* fake */ -} - -int -ibcs2_putmsg(td, uap) - struct thread *td; - struct ibcs2_putmsg_args *uap; -{ - return 0; /* fake */ -} diff --git a/sys/i386/ibcs2/ibcs2_other.c b/sys/i386/ibcs2/ibcs2_other.c deleted file mode 100644 index bdbd0b24d13..00000000000 --- a/sys/i386/ibcs2/ibcs2_other.c +++ /dev/null @@ -1,120 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 1995 Steven Wallace - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include - -/* - * IBCS2 compatibility module. - */ - -#include "opt_spx_hack.h" - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#define IBCS2_SECURE_GETLUID 1 -#define IBCS2_SECURE_SETLUID 2 - -int -ibcs2_secure(struct thread *td, struct ibcs2_secure_args *uap) -{ - switch (uap->cmd) { - - case IBCS2_SECURE_GETLUID: /* get login uid */ - td->td_retval[0] = td->td_ucred->cr_uid; - return 0; - - case IBCS2_SECURE_SETLUID: /* set login uid */ - return EPERM; - - default: - printf("IBCS2: 'secure' cmd=%d not implemented\n", uap->cmd); - } - - return EINVAL; -} - -int -ibcs2_lseek(struct thread *td, struct ibcs2_lseek_args *uap) -{ - struct lseek_args largs; - int error; - - largs.fd = uap->fd; - largs.offset = uap->offset; - largs.whence = uap->whence; - error = sys_lseek(td, &largs); - return (error); -} - -#ifdef SPX_HACK -#include -#include - -int -spx_open(struct thread *td) -{ - struct socket_args sock; - struct sockaddr_un sun; - int fd, error; - - /* obtain a socket. */ - DPRINTF(("SPX: open socket\n")); - sock.domain = AF_UNIX; - sock.type = SOCK_STREAM; - sock.protocol = 0; - error = sys_socket(td, &sock); - if (error) - return error; - fd = td->td_retval[0]; - - /* connect the socket to standard X socket */ - DPRINTF(("SPX: connect to /tmp/X11-unix/X0\n")); - sun.sun_family = AF_UNIX; - strcpy(sun.sun_path, "/tmp/.X11-unix/X0"); - sun.sun_len = sizeof(struct sockaddr_un) - sizeof(sun.sun_path) + - strlen(sun.sun_path) + 1; - - error = kern_connectat(td, AT_FDCWD, fd, (struct sockaddr *)&sun); - if (error) { - kern_close(td, fd); - return error; - } - td->td_retval[0] = fd; - return 0; -} -#endif /* SPX_HACK */ diff --git a/sys/i386/ibcs2/ibcs2_proto.h b/sys/i386/ibcs2/ibcs2_proto.h deleted file mode 100644 index 11be3805b61..00000000000 --- a/sys/i386/ibcs2/ibcs2_proto.h +++ /dev/null @@ -1,425 +0,0 @@ -/* - * System call prototypes. - * - * DO NOT EDIT-- this file is automatically @generated. - */ - -#ifndef _IBCS2_SYSPROTO_H_ -#define _IBCS2_SYSPROTO_H_ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -struct proc; - -struct thread; - -#define PAD_(t) (sizeof(register_t) <= sizeof(t) ? \ - 0 : sizeof(register_t) - sizeof(t)) - -#if BYTE_ORDER == LITTLE_ENDIAN -#define PADL_(t) 0 -#define PADR_(t) PAD_(t) -#else -#define PADL_(t) PAD_(t) -#define PADR_(t) 0 -#endif - -struct ibcs2_read_args { - char fd_l_[PADL_(int)]; int fd; char fd_r_[PADR_(int)]; - char buf_l_[PADL_(char *)]; char * buf; char buf_r_[PADR_(char *)]; - char nbytes_l_[PADL_(u_int)]; u_int nbytes; char nbytes_r_[PADR_(u_int)]; -}; -struct ibcs2_open_args { - char path_l_[PADL_(char *)]; char * path; char path_r_[PADR_(char *)]; - char flags_l_[PADL_(int)]; int flags; char flags_r_[PADR_(int)]; - char mode_l_[PADL_(int)]; int mode; char mode_r_[PADR_(int)]; -}; -struct ibcs2_wait_args { - char a1_l_[PADL_(int)]; int a1; char a1_r_[PADR_(int)]; - char a2_l_[PADL_(int)]; int a2; char a2_r_[PADR_(int)]; - char a3_l_[PADL_(int)]; int a3; char a3_r_[PADR_(int)]; -}; -struct ibcs2_creat_args { - char path_l_[PADL_(char *)]; char * path; char path_r_[PADR_(char *)]; - char mode_l_[PADL_(int)]; int mode; char mode_r_[PADR_(int)]; -}; -struct ibcs2_unlink_args { - char path_l_[PADL_(char *)]; char * path; char path_r_[PADR_(char *)]; -}; -struct ibcs2_execv_args { - char path_l_[PADL_(char *)]; char * path; char path_r_[PADR_(char *)]; - char argp_l_[PADL_(char **)]; char ** argp; char argp_r_[PADR_(char **)]; -}; -struct ibcs2_chdir_args { - char path_l_[PADL_(char *)]; char * path; char path_r_[PADR_(char *)]; -}; -struct ibcs2_time_args { - char tp_l_[PADL_(ibcs2_time_t *)]; ibcs2_time_t * tp; char tp_r_[PADR_(ibcs2_time_t *)]; -}; -struct ibcs2_mknod_args { - char path_l_[PADL_(char *)]; char * path; char path_r_[PADR_(char *)]; - char mode_l_[PADL_(int)]; int mode; char mode_r_[PADR_(int)]; - char dev_l_[PADL_(int)]; int dev; char dev_r_[PADR_(int)]; -}; -struct ibcs2_chmod_args { - char path_l_[PADL_(char *)]; char * path; char path_r_[PADR_(char *)]; - char mode_l_[PADL_(int)]; int mode; char mode_r_[PADR_(int)]; -}; -struct ibcs2_chown_args { - char path_l_[PADL_(char *)]; char * path; char path_r_[PADR_(char *)]; - char uid_l_[PADL_(int)]; int uid; char uid_r_[PADR_(int)]; - char gid_l_[PADL_(int)]; int gid; char gid_r_[PADR_(int)]; -}; -struct ibcs2_stat_args { - char path_l_[PADL_(char *)]; char * path; char path_r_[PADR_(char *)]; - char st_l_[PADL_(struct ibcs2_stat *)]; struct ibcs2_stat * st; char st_r_[PADR_(struct ibcs2_stat *)]; -}; -struct ibcs2_lseek_args { - char fd_l_[PADL_(int)]; int fd; char fd_r_[PADR_(int)]; - char offset_l_[PADL_(long)]; long offset; char offset_r_[PADR_(long)]; - char whence_l_[PADL_(int)]; int whence; char whence_r_[PADR_(int)]; -}; -struct ibcs2_mount_args { - char special_l_[PADL_(char *)]; char * special; char special_r_[PADR_(char *)]; - char dir_l_[PADL_(char *)]; char * dir; char dir_r_[PADR_(char *)]; - char flags_l_[PADL_(int)]; int flags; char flags_r_[PADR_(int)]; - char fstype_l_[PADL_(int)]; int fstype; char fstype_r_[PADR_(int)]; - char data_l_[PADL_(char *)]; char * data; char data_r_[PADR_(char *)]; - char len_l_[PADL_(int)]; int len; char len_r_[PADR_(int)]; -}; -struct ibcs2_umount_args { - char name_l_[PADL_(char *)]; char * name; char name_r_[PADR_(char *)]; -}; -struct ibcs2_setuid_args { - char uid_l_[PADL_(int)]; int uid; char uid_r_[PADR_(int)]; -}; -struct ibcs2_stime_args { - char timep_l_[PADL_(long *)]; long * timep; char timep_r_[PADR_(long *)]; -}; -struct ibcs2_alarm_args { - char sec_l_[PADL_(unsigned)]; unsigned sec; char sec_r_[PADR_(unsigned)]; -}; -struct ibcs2_fstat_args { - char fd_l_[PADL_(int)]; int fd; char fd_r_[PADR_(int)]; - char st_l_[PADL_(struct ibcs2_stat *)]; struct ibcs2_stat * st; char st_r_[PADR_(struct ibcs2_stat *)]; -}; -struct ibcs2_pause_args { - register_t dummy; -}; -struct ibcs2_utime_args { - char path_l_[PADL_(char *)]; char * path; char path_r_[PADR_(char *)]; - char buf_l_[PADL_(struct ibcs2_utimbuf *)]; struct ibcs2_utimbuf * buf; char buf_r_[PADR_(struct ibcs2_utimbuf *)]; -}; -struct ibcs2_access_args { - char path_l_[PADL_(char *)]; char * path; char path_r_[PADR_(char *)]; - char amode_l_[PADL_(int)]; int amode; char amode_r_[PADR_(int)]; -}; -struct ibcs2_nice_args { - char incr_l_[PADL_(int)]; int incr; char incr_r_[PADR_(int)]; -}; -struct ibcs2_statfs_args { - char path_l_[PADL_(char *)]; char * path; char path_r_[PADR_(char *)]; - char buf_l_[PADL_(struct ibcs2_statfs *)]; struct ibcs2_statfs * buf; char buf_r_[PADR_(struct ibcs2_statfs *)]; - char len_l_[PADL_(int)]; int len; char len_r_[PADR_(int)]; - char fstype_l_[PADL_(int)]; int fstype; char fstype_r_[PADR_(int)]; -}; -struct ibcs2_kill_args { - char pid_l_[PADL_(int)]; int pid; char pid_r_[PADR_(int)]; - char signo_l_[PADL_(int)]; int signo; char signo_r_[PADR_(int)]; -}; -struct ibcs2_fstatfs_args { - char fd_l_[PADL_(int)]; int fd; char fd_r_[PADR_(int)]; - char buf_l_[PADL_(struct ibcs2_statfs *)]; struct ibcs2_statfs * buf; char buf_r_[PADR_(struct ibcs2_statfs *)]; - char len_l_[PADL_(int)]; int len; char len_r_[PADR_(int)]; - char fstype_l_[PADL_(int)]; int fstype; char fstype_r_[PADR_(int)]; -}; -struct ibcs2_pgrpsys_args { - char type_l_[PADL_(int)]; int type; char type_r_[PADR_(int)]; - char dummy_l_[PADL_(caddr_t)]; caddr_t dummy; char dummy_r_[PADR_(caddr_t)]; - char pid_l_[PADL_(int)]; int pid; char pid_r_[PADR_(int)]; - char pgid_l_[PADL_(int)]; int pgid; char pgid_r_[PADR_(int)]; -}; -struct ibcs2_xenix_args { - char a1_l_[PADL_(int)]; int a1; char a1_r_[PADR_(int)]; - char a2_l_[PADL_(int)]; int a2; char a2_r_[PADR_(int)]; - char a3_l_[PADL_(int)]; int a3; char a3_r_[PADR_(int)]; - char a4_l_[PADL_(int)]; int a4; char a4_r_[PADR_(int)]; - char a5_l_[PADL_(int)]; int a5; char a5_r_[PADR_(int)]; -}; -struct ibcs2_times_args { - char tp_l_[PADL_(struct tms *)]; struct tms * tp; char tp_r_[PADR_(struct tms *)]; -}; -struct ibcs2_plock_args { - char cmd_l_[PADL_(int)]; int cmd; char cmd_r_[PADR_(int)]; -}; -struct ibcs2_setgid_args { - char gid_l_[PADL_(int)]; int gid; char gid_r_[PADR_(int)]; -}; -struct ibcs2_sigsys_args { - char sig_l_[PADL_(int)]; int sig; char sig_r_[PADR_(int)]; - char fp_l_[PADL_(ibcs2_sig_t)]; ibcs2_sig_t fp; char fp_r_[PADR_(ibcs2_sig_t)]; -}; -struct ibcs2_msgsys_args { - char which_l_[PADL_(int)]; int which; char which_r_[PADR_(int)]; - char a2_l_[PADL_(int)]; int a2; char a2_r_[PADR_(int)]; - char a3_l_[PADL_(int)]; int a3; char a3_r_[PADR_(int)]; - char a4_l_[PADL_(int)]; int a4; char a4_r_[PADR_(int)]; - char a5_l_[PADL_(int)]; int a5; char a5_r_[PADR_(int)]; - char a6_l_[PADL_(int)]; int a6; char a6_r_[PADR_(int)]; -}; -struct ibcs2_sysi86_args { - char cmd_l_[PADL_(int)]; int cmd; char cmd_r_[PADR_(int)]; - char arg_l_[PADL_(int *)]; int * arg; char arg_r_[PADR_(int *)]; -}; -struct ibcs2_shmsys_args { - char which_l_[PADL_(int)]; int which; char which_r_[PADR_(int)]; - char a2_l_[PADL_(int)]; int a2; char a2_r_[PADR_(int)]; - char a3_l_[PADL_(int)]; int a3; char a3_r_[PADR_(int)]; - char a4_l_[PADL_(int)]; int a4; char a4_r_[PADR_(int)]; -}; -struct ibcs2_semsys_args { - char which_l_[PADL_(int)]; int which; char which_r_[PADR_(int)]; - char a2_l_[PADL_(int)]; int a2; char a2_r_[PADR_(int)]; - char a3_l_[PADL_(int)]; int a3; char a3_r_[PADR_(int)]; - char a4_l_[PADL_(int)]; int a4; char a4_r_[PADR_(int)]; - char a5_l_[PADL_(int)]; int a5; char a5_r_[PADR_(int)]; -}; -struct ibcs2_ioctl_args { - char fd_l_[PADL_(int)]; int fd; char fd_r_[PADR_(int)]; - char cmd_l_[PADL_(int)]; int cmd; char cmd_r_[PADR_(int)]; - char data_l_[PADL_(caddr_t)]; caddr_t data; char data_r_[PADR_(caddr_t)]; -}; -struct ibcs2_uadmin_args { - char cmd_l_[PADL_(int)]; int cmd; char cmd_r_[PADR_(int)]; - char func_l_[PADL_(int)]; int func; char func_r_[PADR_(int)]; - char data_l_[PADL_(caddr_t)]; caddr_t data; char data_r_[PADR_(caddr_t)]; -}; -struct ibcs2_utssys_args { - char a1_l_[PADL_(int)]; int a1; char a1_r_[PADR_(int)]; - char a2_l_[PADL_(int)]; int a2; char a2_r_[PADR_(int)]; - char flag_l_[PADL_(int)]; int flag; char flag_r_[PADR_(int)]; -}; -struct ibcs2_execve_args { - char path_l_[PADL_(char *)]; char * path; char path_r_[PADR_(char *)]; - char argp_l_[PADL_(char **)]; char ** argp; char argp_r_[PADR_(char **)]; - char envp_l_[PADL_(char **)]; char ** envp; char envp_r_[PADR_(char **)]; -}; -struct ibcs2_fcntl_args { - char fd_l_[PADL_(int)]; int fd; char fd_r_[PADR_(int)]; - char cmd_l_[PADL_(int)]; int cmd; char cmd_r_[PADR_(int)]; - char arg_l_[PADL_(char *)]; char * arg; char arg_r_[PADR_(char *)]; -}; -struct ibcs2_ulimit_args { - char cmd_l_[PADL_(int)]; int cmd; char cmd_r_[PADR_(int)]; - char newlimit_l_[PADL_(int)]; int newlimit; char newlimit_r_[PADR_(int)]; -}; -struct ibcs2_rmdir_args { - char path_l_[PADL_(char *)]; char * path; char path_r_[PADR_(char *)]; -}; -struct ibcs2_mkdir_args { - char path_l_[PADL_(char *)]; char * path; char path_r_[PADR_(char *)]; - char mode_l_[PADL_(int)]; int mode; char mode_r_[PADR_(int)]; -}; -struct ibcs2_getdents_args { - char fd_l_[PADL_(int)]; int fd; char fd_r_[PADR_(int)]; - char buf_l_[PADL_(char *)]; char * buf; char buf_r_[PADR_(char *)]; - char nbytes_l_[PADL_(int)]; int nbytes; char nbytes_r_[PADR_(int)]; -}; -struct ibcs2_sysfs_args { - char cmd_l_[PADL_(int)]; int cmd; char cmd_r_[PADR_(int)]; - char d1_l_[PADL_(caddr_t)]; caddr_t d1; char d1_r_[PADR_(caddr_t)]; - char buf_l_[PADL_(char *)]; char * buf; char buf_r_[PADR_(char *)]; -}; -struct ibcs2_getmsg_args { - char fd_l_[PADL_(int)]; int fd; char fd_r_[PADR_(int)]; - char ctl_l_[PADL_(struct ibcs2_stropts *)]; struct ibcs2_stropts * ctl; char ctl_r_[PADR_(struct ibcs2_stropts *)]; - char dat_l_[PADL_(struct ibcs2_stropts *)]; struct ibcs2_stropts * dat; char dat_r_[PADR_(struct ibcs2_stropts *)]; - char flags_l_[PADL_(int *)]; int * flags; char flags_r_[PADR_(int *)]; -}; -struct ibcs2_putmsg_args { - char fd_l_[PADL_(int)]; int fd; char fd_r_[PADR_(int)]; - char ctl_l_[PADL_(struct ibcs2_stropts *)]; struct ibcs2_stropts * ctl; char ctl_r_[PADR_(struct ibcs2_stropts *)]; - char dat_l_[PADL_(struct ibcs2_stropts *)]; struct ibcs2_stropts * dat; char dat_r_[PADR_(struct ibcs2_stropts *)]; - char flags_l_[PADL_(int)]; int flags; char flags_r_[PADR_(int)]; -}; -struct ibcs2_secure_args { - char cmd_l_[PADL_(int)]; int cmd; char cmd_r_[PADR_(int)]; - char a1_l_[PADL_(int)]; int a1; char a1_r_[PADR_(int)]; - char a2_l_[PADL_(int)]; int a2; char a2_r_[PADR_(int)]; - char a3_l_[PADL_(int)]; int a3; char a3_r_[PADR_(int)]; - char a4_l_[PADL_(int)]; int a4; char a4_r_[PADR_(int)]; - char a5_l_[PADL_(int)]; int a5; char a5_r_[PADR_(int)]; -}; -struct ibcs2_symlink_args { - char path_l_[PADL_(char *)]; char * path; char path_r_[PADR_(char *)]; - char link_l_[PADL_(char *)]; char * link; char link_r_[PADR_(char *)]; -}; -struct ibcs2_lstat_args { - char path_l_[PADL_(char *)]; char * path; char path_r_[PADR_(char *)]; - char st_l_[PADL_(struct ibcs2_stat *)]; struct ibcs2_stat * st; char st_r_[PADR_(struct ibcs2_stat *)]; -}; -struct ibcs2_readlink_args { - char path_l_[PADL_(char *)]; char * path; char path_r_[PADR_(char *)]; - char buf_l_[PADL_(char *)]; char * buf; char buf_r_[PADR_(char *)]; - char count_l_[PADL_(int)]; int count; char count_r_[PADR_(int)]; -}; -struct ibcs2_isc_args { - register_t dummy; -}; -int ibcs2_read(struct thread *, struct ibcs2_read_args *); -int ibcs2_open(struct thread *, struct ibcs2_open_args *); -int ibcs2_wait(struct thread *, struct ibcs2_wait_args *); -int ibcs2_creat(struct thread *, struct ibcs2_creat_args *); -int ibcs2_unlink(struct thread *, struct ibcs2_unlink_args *); -int ibcs2_execv(struct thread *, struct ibcs2_execv_args *); -int ibcs2_chdir(struct thread *, struct ibcs2_chdir_args *); -int ibcs2_time(struct thread *, struct ibcs2_time_args *); -int ibcs2_mknod(struct thread *, struct ibcs2_mknod_args *); -int ibcs2_chmod(struct thread *, struct ibcs2_chmod_args *); -int ibcs2_chown(struct thread *, struct ibcs2_chown_args *); -int ibcs2_stat(struct thread *, struct ibcs2_stat_args *); -int ibcs2_lseek(struct thread *, struct ibcs2_lseek_args *); -int ibcs2_mount(struct thread *, struct ibcs2_mount_args *); -int ibcs2_umount(struct thread *, struct ibcs2_umount_args *); -int ibcs2_setuid(struct thread *, struct ibcs2_setuid_args *); -int ibcs2_stime(struct thread *, struct ibcs2_stime_args *); -int ibcs2_alarm(struct thread *, struct ibcs2_alarm_args *); -int ibcs2_fstat(struct thread *, struct ibcs2_fstat_args *); -int ibcs2_pause(struct thread *, struct ibcs2_pause_args *); -int ibcs2_utime(struct thread *, struct ibcs2_utime_args *); -int ibcs2_access(struct thread *, struct ibcs2_access_args *); -int ibcs2_nice(struct thread *, struct ibcs2_nice_args *); -int ibcs2_statfs(struct thread *, struct ibcs2_statfs_args *); -int ibcs2_kill(struct thread *, struct ibcs2_kill_args *); -int ibcs2_fstatfs(struct thread *, struct ibcs2_fstatfs_args *); -int ibcs2_pgrpsys(struct thread *, struct ibcs2_pgrpsys_args *); -int ibcs2_xenix(struct thread *, struct ibcs2_xenix_args *); -int ibcs2_times(struct thread *, struct ibcs2_times_args *); -int ibcs2_plock(struct thread *, struct ibcs2_plock_args *); -int ibcs2_setgid(struct thread *, struct ibcs2_setgid_args *); -int ibcs2_sigsys(struct thread *, struct ibcs2_sigsys_args *); -int ibcs2_msgsys(struct thread *, struct ibcs2_msgsys_args *); -int ibcs2_sysi86(struct thread *, struct ibcs2_sysi86_args *); -int ibcs2_shmsys(struct thread *, struct ibcs2_shmsys_args *); -int ibcs2_semsys(struct thread *, struct ibcs2_semsys_args *); -int ibcs2_ioctl(struct thread *, struct ibcs2_ioctl_args *); -int ibcs2_uadmin(struct thread *, struct ibcs2_uadmin_args *); -int ibcs2_utssys(struct thread *, struct ibcs2_utssys_args *); -int ibcs2_execve(struct thread *, struct ibcs2_execve_args *); -int ibcs2_fcntl(struct thread *, struct ibcs2_fcntl_args *); -int ibcs2_ulimit(struct thread *, struct ibcs2_ulimit_args *); -int ibcs2_rmdir(struct thread *, struct ibcs2_rmdir_args *); -int ibcs2_mkdir(struct thread *, struct ibcs2_mkdir_args *); -int ibcs2_getdents(struct thread *, struct ibcs2_getdents_args *); -int ibcs2_sysfs(struct thread *, struct ibcs2_sysfs_args *); -int ibcs2_getmsg(struct thread *, struct ibcs2_getmsg_args *); -int ibcs2_putmsg(struct thread *, struct ibcs2_putmsg_args *); -int ibcs2_secure(struct thread *, struct ibcs2_secure_args *); -int ibcs2_symlink(struct thread *, struct ibcs2_symlink_args *); -int ibcs2_lstat(struct thread *, struct ibcs2_lstat_args *); -int ibcs2_readlink(struct thread *, struct ibcs2_readlink_args *); -int ibcs2_isc(struct thread *, struct ibcs2_isc_args *); - -#ifdef COMPAT_43 - - -#endif /* COMPAT_43 */ - - -#ifdef COMPAT_FREEBSD4 - - -#endif /* COMPAT_FREEBSD4 */ - - -#ifdef COMPAT_FREEBSD6 - - -#endif /* COMPAT_FREEBSD6 */ - - -#ifdef COMPAT_FREEBSD7 - - -#endif /* COMPAT_FREEBSD7 */ - - -#ifdef COMPAT_FREEBSD10 - - -#endif /* COMPAT_FREEBSD10 */ - - -#ifdef COMPAT_FREEBSD11 - - -#endif /* COMPAT_FREEBSD11 */ - -#define IBCS2_SYS_AUE_ibcs2_read AUE_NULL -#define IBCS2_SYS_AUE_ibcs2_open AUE_OPEN_RWTC -#define IBCS2_SYS_AUE_ibcs2_wait AUE_WAIT4 -#define IBCS2_SYS_AUE_ibcs2_creat AUE_CREAT -#define IBCS2_SYS_AUE_ibcs2_unlink AUE_UNLINK -#define IBCS2_SYS_AUE_ibcs2_execv AUE_EXECVE -#define IBCS2_SYS_AUE_ibcs2_chdir AUE_CHDIR -#define IBCS2_SYS_AUE_ibcs2_time AUE_NULL -#define IBCS2_SYS_AUE_ibcs2_mknod AUE_MKNOD -#define IBCS2_SYS_AUE_ibcs2_chmod AUE_CHMOD -#define IBCS2_SYS_AUE_ibcs2_chown AUE_CHOWN -#define IBCS2_SYS_AUE_ibcs2_stat AUE_STAT -#define IBCS2_SYS_AUE_ibcs2_lseek AUE_LSEEK -#define IBCS2_SYS_AUE_ibcs2_mount AUE_MOUNT -#define IBCS2_SYS_AUE_ibcs2_umount AUE_UMOUNT -#define IBCS2_SYS_AUE_ibcs2_setuid AUE_SETUID -#define IBCS2_SYS_AUE_ibcs2_stime AUE_SETTIMEOFDAY -#define IBCS2_SYS_AUE_ibcs2_alarm AUE_NULL -#define IBCS2_SYS_AUE_ibcs2_fstat AUE_FSTAT -#define IBCS2_SYS_AUE_ibcs2_pause AUE_NULL -#define IBCS2_SYS_AUE_ibcs2_utime AUE_NULL -#define IBCS2_SYS_AUE_ibcs2_access AUE_ACCESS -#define IBCS2_SYS_AUE_ibcs2_nice AUE_NICE -#define IBCS2_SYS_AUE_ibcs2_statfs AUE_STATFS -#define IBCS2_SYS_AUE_ibcs2_kill AUE_KILL -#define IBCS2_SYS_AUE_ibcs2_fstatfs AUE_FSTATFS -#define IBCS2_SYS_AUE_ibcs2_pgrpsys AUE_NULL -#define IBCS2_SYS_AUE_ibcs2_xenix AUE_NULL -#define IBCS2_SYS_AUE_ibcs2_times AUE_NULL -#define IBCS2_SYS_AUE_ibcs2_plock AUE_NULL -#define IBCS2_SYS_AUE_ibcs2_setgid AUE_SETGID -#define IBCS2_SYS_AUE_ibcs2_sigsys AUE_NULL -#define IBCS2_SYS_AUE_ibcs2_msgsys AUE_MSGSYS -#define IBCS2_SYS_AUE_ibcs2_sysi86 AUE_NULL -#define IBCS2_SYS_AUE_ibcs2_shmsys AUE_SHMSYS -#define IBCS2_SYS_AUE_ibcs2_semsys AUE_SEMSYS -#define IBCS2_SYS_AUE_ibcs2_ioctl AUE_IOCTL -#define IBCS2_SYS_AUE_ibcs2_uadmin AUE_NULL -#define IBCS2_SYS_AUE_ibcs2_utssys AUE_NULL -#define IBCS2_SYS_AUE_ibcs2_execve AUE_EXECVE -#define IBCS2_SYS_AUE_ibcs2_fcntl AUE_FCNTL -#define IBCS2_SYS_AUE_ibcs2_ulimit AUE_NULL -#define IBCS2_SYS_AUE_ibcs2_rmdir AUE_RMDIR -#define IBCS2_SYS_AUE_ibcs2_mkdir AUE_MKDIR -#define IBCS2_SYS_AUE_ibcs2_getdents AUE_GETDIRENTRIES -#define IBCS2_SYS_AUE_ibcs2_sysfs AUE_NULL -#define IBCS2_SYS_AUE_ibcs2_getmsg AUE_GETMSG -#define IBCS2_SYS_AUE_ibcs2_putmsg AUE_PUTMSG -#define IBCS2_SYS_AUE_ibcs2_secure AUE_NULL -#define IBCS2_SYS_AUE_ibcs2_symlink AUE_SYMLINK -#define IBCS2_SYS_AUE_ibcs2_lstat AUE_LSTAT -#define IBCS2_SYS_AUE_ibcs2_readlink AUE_READLINK -#define IBCS2_SYS_AUE_ibcs2_isc AUE_NULL - -#undef PAD_ -#undef PADL_ -#undef PADR_ - -#endif /* !_IBCS2_SYSPROTO_H_ */ diff --git a/sys/i386/ibcs2/ibcs2_signal.c b/sys/i386/ibcs2/ibcs2_signal.c deleted file mode 100644 index 411f51b00de..00000000000 --- a/sys/i386/ibcs2/ibcs2_signal.c +++ /dev/null @@ -1,428 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-3-Clause - * - * Copyright (c) 1995 Scott Bartram - * Copyright (c) 1995 Steven Wallace - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#define sigemptyset(s) SIGEMPTYSET(*(s)) -#define sigismember(s, n) SIGISMEMBER(*(s), n) -#define sigaddset(s, n) SIGADDSET(*(s), n) - -#define ibcs2_sigmask(n) (1 << ((n) - 1)) -#define ibcs2_sigemptyset(s) bzero((s), sizeof(*(s))) -#define ibcs2_sigismember(s, n) (*(s) & ibcs2_sigmask(n)) -#define ibcs2_sigaddset(s, n) (*(s) |= ibcs2_sigmask(n)) - -static void ibcs2_to_bsd_sigset(const ibcs2_sigset_t *, sigset_t *); -static void bsd_to_ibcs2_sigset(const sigset_t *, ibcs2_sigset_t *); -static void ibcs2_to_bsd_sigaction(struct ibcs2_sigaction *, - struct sigaction *); -static void bsd_to_ibcs2_sigaction(struct sigaction *, - struct ibcs2_sigaction *); - -int bsd_to_ibcs2_sig[IBCS2_SIGTBLSZ] = { - IBCS2_SIGHUP, /* 1 */ - IBCS2_SIGINT, /* 2 */ - IBCS2_SIGQUIT, /* 3 */ - IBCS2_SIGILL, /* 4 */ - IBCS2_SIGTRAP, /* 5 */ - IBCS2_SIGABRT, /* 6 */ - IBCS2_SIGEMT, /* 7 */ - IBCS2_SIGFPE, /* 8 */ - IBCS2_SIGKILL, /* 9 */ - IBCS2_SIGBUS, /* 10 */ - IBCS2_SIGSEGV, /* 11 */ - IBCS2_SIGSYS, /* 12 */ - IBCS2_SIGPIPE, /* 13 */ - IBCS2_SIGALRM, /* 14 */ - IBCS2_SIGTERM, /* 15 */ - 0, /* 16 - SIGURG */ - IBCS2_SIGSTOP, /* 17 */ - IBCS2_SIGTSTP, /* 18 */ - IBCS2_SIGCONT, /* 19 */ - IBCS2_SIGCLD, /* 20 */ - IBCS2_SIGTTIN, /* 21 */ - IBCS2_SIGTTOU, /* 22 */ - IBCS2_SIGPOLL, /* 23 */ - 0, /* 24 - SIGXCPU */ - 0, /* 25 - SIGXFSZ */ - IBCS2_SIGVTALRM, /* 26 */ - IBCS2_SIGPROF, /* 27 */ - IBCS2_SIGWINCH, /* 28 */ - 0, /* 29 */ - IBCS2_SIGUSR1, /* 30 */ - IBCS2_SIGUSR2, /* 31 */ - 0 /* 32 */ -}; - -static int ibcs2_to_bsd_sig[IBCS2_SIGTBLSZ] = { - SIGHUP, /* 1 */ - SIGINT, /* 2 */ - SIGQUIT, /* 3 */ - SIGILL, /* 4 */ - SIGTRAP, /* 5 */ - SIGABRT, /* 6 */ - SIGEMT, /* 7 */ - SIGFPE, /* 8 */ - SIGKILL, /* 9 */ - SIGBUS, /* 10 */ - SIGSEGV, /* 11 */ - SIGSYS, /* 12 */ - SIGPIPE, /* 13 */ - SIGALRM, /* 14 */ - SIGTERM, /* 15 */ - SIGUSR1, /* 16 */ - SIGUSR2, /* 17 */ - SIGCHLD, /* 18 */ - 0, /* 19 - SIGPWR */ - SIGWINCH, /* 20 */ - 0, /* 21 */ - SIGIO, /* 22 */ - SIGSTOP, /* 23 */ - SIGTSTP, /* 24 */ - SIGCONT, /* 25 */ - SIGTTIN, /* 26 */ - SIGTTOU, /* 27 */ - SIGVTALRM, /* 28 */ - SIGPROF, /* 29 */ - 0, /* 30 */ - 0, /* 31 */ - 0 /* 32 */ -}; - -void -ibcs2_to_bsd_sigset(iss, bss) - const ibcs2_sigset_t *iss; - sigset_t *bss; -{ - int i, newsig; - - sigemptyset(bss); - for (i = 1; i <= IBCS2_SIGTBLSZ; i++) { - if (ibcs2_sigismember(iss, i)) { - newsig = ibcs2_to_bsd_sig[_SIG_IDX(i)]; - if (newsig) - sigaddset(bss, newsig); - } - } -} - -static void -bsd_to_ibcs2_sigset(bss, iss) - const sigset_t *bss; - ibcs2_sigset_t *iss; -{ - int i, newsig; - - ibcs2_sigemptyset(iss); - for (i = 1; i <= IBCS2_SIGTBLSZ; i++) { - if (sigismember(bss, i)) { - newsig = bsd_to_ibcs2_sig[_SIG_IDX(i)]; - if (newsig) - ibcs2_sigaddset(iss, newsig); - } - } -} - -static void -ibcs2_to_bsd_sigaction(isa, bsa) - struct ibcs2_sigaction *isa; - struct sigaction *bsa; -{ - - bsa->sa_handler = isa->isa_handler; - ibcs2_to_bsd_sigset(&isa->isa_mask, &bsa->sa_mask); - bsa->sa_flags = 0; /* ??? SA_NODEFER */ - if ((isa->isa_flags & IBCS2_SA_NOCLDSTOP) != 0) - bsa->sa_flags |= SA_NOCLDSTOP; -} - -static void -bsd_to_ibcs2_sigaction(bsa, isa) - struct sigaction *bsa; - struct ibcs2_sigaction *isa; -{ - - isa->isa_handler = bsa->sa_handler; - bsd_to_ibcs2_sigset(&bsa->sa_mask, &isa->isa_mask); - isa->isa_flags = 0; - if ((bsa->sa_flags & SA_NOCLDSTOP) != 0) - isa->isa_flags |= IBCS2_SA_NOCLDSTOP; -} - -int -ibcs2_sigaction(struct thread *td, struct ibcs2_sigaction_args *uap) -{ - struct ibcs2_sigaction isa; - struct sigaction nbsa, obsa; - struct sigaction *nbsap; - int error; - - if (uap->act != NULL) { - if ((error = copyin(uap->act, &isa, sizeof(isa))) != 0) - return (error); - ibcs2_to_bsd_sigaction(&isa, &nbsa); - nbsap = &nbsa; - } else - nbsap = NULL; - if (uap->sig <= 0 || uap->sig > IBCS2_NSIG) - return (EINVAL); - error = kern_sigaction(td, ibcs2_to_bsd_sig[_SIG_IDX(uap->sig)], &nbsa, - &obsa, 0); - if (error == 0 && uap->oact != NULL) { - bsd_to_ibcs2_sigaction(&obsa, &isa); - error = copyout(&isa, uap->oact, sizeof(isa)); - } - return (error); -} - -int -ibcs2_sigsys(struct thread *td, struct ibcs2_sigsys_args *uap) -{ - struct proc *p = td->td_proc; - struct sigaction sa; - int signum = IBCS2_SIGNO(uap->sig); - int error; - - if (signum <= 0 || signum > IBCS2_NSIG) { - if (IBCS2_SIGCALL(uap->sig) == IBCS2_SIGNAL_MASK || - IBCS2_SIGCALL(uap->sig) == IBCS2_SIGSET_MASK) - td->td_retval[0] = (int)IBCS2_SIG_ERR; - return EINVAL; - } - signum = ibcs2_to_bsd_sig[_SIG_IDX(signum)]; - - switch (IBCS2_SIGCALL(uap->sig)) { - case IBCS2_SIGSET_MASK: - /* - * Check for SIG_HOLD action. - * Otherwise, perform signal() except with different sa_flags. - */ - if (uap->fp != IBCS2_SIG_HOLD) { - /* add sig to mask before exececuting signal handler */ - sa.sa_flags = 0; - goto ibcs2_sigset; - } - /* else FALLTHROUGH to sighold */ - - case IBCS2_SIGHOLD_MASK: - { - sigset_t mask; - - SIGEMPTYSET(mask); - SIGADDSET(mask, signum); - return (kern_sigprocmask(td, SIG_BLOCK, &mask, NULL, - 0)); - } - - case IBCS2_SIGNAL_MASK: - { - struct sigaction osa; - - /* do not automatically block signal */ - sa.sa_flags = SA_NODEFER; -#ifdef SA_RESETHAND - if((signum != IBCS2_SIGILL) && - (signum != IBCS2_SIGTRAP) && - (signum != IBCS2_SIGPWR)) - /* set to SIG_DFL before executing handler */ - sa.sa_flags |= SA_RESETHAND; -#endif - ibcs2_sigset: - sa.sa_handler = uap->fp; - sigemptyset(&sa.sa_mask); -#if 0 - if (signum != SIGALRM) - sa.sa_flags |= SA_RESTART; -#endif - error = kern_sigaction(td, signum, &sa, &osa, 0); - if (error != 0) { - DPRINTF(("signal: sigaction failed: %d\n", - error)); - td->td_retval[0] = (int)IBCS2_SIG_ERR; - return (error); - } - td->td_retval[0] = (int)osa.sa_handler; - - /* special sigset() check */ - if(IBCS2_SIGCALL(uap->sig) == IBCS2_SIGSET_MASK) { - PROC_LOCK(p); - /* check to make sure signal is not blocked */ - if(sigismember(&td->td_sigmask, signum)) { - /* return SIG_HOLD and unblock signal*/ - td->td_retval[0] = (int)IBCS2_SIG_HOLD; - SIGDELSET(td->td_sigmask, signum); - signotify(td); - } - PROC_UNLOCK(p); - } - - return 0; - } - - case IBCS2_SIGRELSE_MASK: - { - sigset_t mask; - - SIGEMPTYSET(mask); - SIGADDSET(mask, signum); - return (kern_sigprocmask(td, SIG_UNBLOCK, &mask, NULL, - 0)); - } - - case IBCS2_SIGIGNORE_MASK: - { - sa.sa_handler = SIG_IGN; - sigemptyset(&sa.sa_mask); - sa.sa_flags = 0; - error = kern_sigaction(td, signum, &sa, NULL, 0); - if (error != 0) - DPRINTF(("sigignore: sigaction failed\n")); - return (error); - } - - case IBCS2_SIGPAUSE_MASK: - { - sigset_t mask; - - PROC_LOCK(p); - mask = td->td_sigmask; - PROC_UNLOCK(p); - SIGDELSET(mask, signum); - return kern_sigsuspend(td, mask); - } - - default: - return ENOSYS; - } -} - -int -ibcs2_sigprocmask(struct thread *td, struct ibcs2_sigprocmask_args *uap) -{ - ibcs2_sigset_t iss; - sigset_t oss, nss; - sigset_t *nssp; - int error, how; - - switch (uap->how) { - case IBCS2_SIG_BLOCK: - how = SIG_BLOCK; - break; - case IBCS2_SIG_UNBLOCK: - how = SIG_UNBLOCK; - break; - case IBCS2_SIG_SETMASK: - how = SIG_SETMASK; - break; - default: - return (EINVAL); - } - if (uap->set != NULL) { - if ((error = copyin(uap->set, &iss, sizeof(iss))) != 0) - return error; - ibcs2_to_bsd_sigset(&iss, &nss); - nssp = &nss; - } else - nssp = NULL; - error = kern_sigprocmask(td, how, nssp, &oss, 0); - if (error == 0 && uap->oset != NULL) { - bsd_to_ibcs2_sigset(&oss, &iss); - error = copyout(&iss, uap->oset, sizeof(iss)); - } - return (error); -} - -int -ibcs2_sigpending(struct thread *td, struct ibcs2_sigpending_args *uap) -{ - struct proc *p = td->td_proc; - sigset_t bss; - ibcs2_sigset_t iss; - - PROC_LOCK(p); - bss = td->td_siglist; - SIGSETOR(bss, p->p_siglist); - SIGSETAND(bss, td->td_sigmask); - PROC_UNLOCK(p); - bsd_to_ibcs2_sigset(&bss, &iss); - - return copyout(&iss, uap->mask, sizeof(iss)); -} - -int -ibcs2_sigsuspend(struct thread *td, struct ibcs2_sigsuspend_args *uap) -{ - ibcs2_sigset_t sss; - sigset_t bss; - int error; - - if ((error = copyin(uap->mask, &sss, sizeof(sss))) != 0) - return error; - - ibcs2_to_bsd_sigset(&sss, &bss); - return kern_sigsuspend(td, bss); -} - -int -ibcs2_pause(struct thread *td, struct ibcs2_pause_args *uap) -{ - sigset_t mask; - - PROC_LOCK(td->td_proc); - mask = td->td_sigmask; - PROC_UNLOCK(td->td_proc); - return kern_sigsuspend(td, mask); -} - -int -ibcs2_kill(struct thread *td, struct ibcs2_kill_args *uap) -{ - struct kill_args ka; - - if (uap->signo <= 0 || uap->signo > IBCS2_NSIG) - return (EINVAL); - ka.pid = uap->pid; - ka.signum = ibcs2_to_bsd_sig[_SIG_IDX(uap->signo)]; - return sys_kill(td, &ka); -} diff --git a/sys/i386/ibcs2/ibcs2_signal.h b/sys/i386/ibcs2/ibcs2_signal.h deleted file mode 100644 index cef997d5475..00000000000 --- a/sys/i386/ibcs2/ibcs2_signal.h +++ /dev/null @@ -1,111 +0,0 @@ -/* $NetBSD: ibcs2_signal.h,v 1.7 1995/08/14 02:26:01 mycroft Exp $ */ - -/*- - * SPDX-License-Identifier: BSD-4-Clause - * - * Copyright (c) 1994, 1995 Scott Bartram - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by Scott Bartram. - * 4. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef _IBCS2_SIGNAL_H -#define _IBCS2_SIGNAL_H - -#define IBCS2_SIGHUP 1 -#define IBCS2_SIGINT 2 -#define IBCS2_SIGQUIT 3 -#define IBCS2_SIGILL 4 -#define IBCS2_SIGTRAP 5 -#define IBCS2_SIGIOT 6 -#define IBCS2_SIGABRT 6 -#define IBCS2_SIGEMT 7 -#define IBCS2_SIGFPE 8 -#define IBCS2_SIGKILL 9 -#define IBCS2_SIGBUS 10 -#define IBCS2_SIGSEGV 11 -#define IBCS2_SIGSYS 12 -#define IBCS2_SIGPIPE 13 -#define IBCS2_SIGALRM 14 -#define IBCS2_SIGTERM 15 -#define IBCS2_SIGUSR1 16 -#define IBCS2_SIGUSR2 17 -#define IBCS2_SIGCLD 18 -#define IBCS2_SIGPWR 19 -#define IBCS2_SIGWINCH 20 -#define IBCS2_SIGPOLL 22 -#define IBCS2_NSIG 32 -#define IBCS2_SIGTBLSZ 32 - -/* - * SCO-specific - */ -#define IBCS2_SIGSTOP 23 -#define IBCS2_SIGTSTP 24 -#define IBCS2_SIGCONT 25 -#define IBCS2_SIGTTIN 26 -#define IBCS2_SIGTTOU 27 -#define IBCS2_SIGVTALRM 28 -#define IBCS2_SIGPROF 29 - -#define IBCS2_SIGNO_MASK 0x00FF -#define IBCS2_SIGNAL_MASK 0x0000 -#define IBCS2_SIGSET_MASK 0x0100 -#define IBCS2_SIGHOLD_MASK 0x0200 -#define IBCS2_SIGRELSE_MASK 0x0400 -#define IBCS2_SIGIGNORE_MASK 0x0800 -#define IBCS2_SIGPAUSE_MASK 0x1000 - -#define IBCS2_SIGNO(x) ((x) & IBCS2_SIGNO_MASK) -#define IBCS2_SIGCALL(x) ((x) & ~IBCS2_SIGNO_MASK) - -typedef long ibcs2_sigset_t; -typedef void (*ibcs2_sig_t)(int); - -struct ibcs2_sigaction { - ibcs2_sig_t isa_handler; - ibcs2_sigset_t isa_mask; - int isa_flags; -}; - -#define IBCS2_SIG_DFL ((ibcs2_sig_t)0) -#define IBCS2_SIG_ERR ((ibcs2_sig_t)-1) -#define IBCS2_SIG_IGN ((ibcs2_sig_t)1) -#define IBCS2_SIG_HOLD ((ibcs2_sig_t)2) - -#define IBCS2_SIG_SETMASK 0 -#define IBCS2_SIG_BLOCK 1 -#define IBCS2_SIG_UNBLOCK 2 - -/* sa_flags */ -#define IBCS2_SA_NOCLDSTOP 1 - -#define IBCS2_MINSIGSTKSZ 8192 - -extern int bsd_to_ibcs2_sig[]; - -#endif /* _IBCS2_SIGNAL_H */ diff --git a/sys/i386/ibcs2/ibcs2_socksys.c b/sys/i386/ibcs2/ibcs2_socksys.c deleted file mode 100644 index 5d4e88eb991..00000000000 --- a/sys/i386/ibcs2/ibcs2_socksys.c +++ /dev/null @@ -1,205 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 1994, 1995 Scott Bartram - * Copyright (c) 1994 Arne H Juul - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include - -#include -#include -#include -#include -#include -#include - -#include -#include - -/* Local structures */ -struct getipdomainname_args { - char *ipdomainname; - int len; -}; - -struct setipdomainname_args { - char *ipdomainname; - int len; -}; - -/* Local prototypes */ -static int ibcs2_getipdomainname(struct thread *, - struct getipdomainname_args *); -static int ibcs2_setipdomainname(struct thread *, - struct setipdomainname_args *); - -/* - * iBCS2 socksys calls. - */ - -int -ibcs2_socksys(struct thread *td, struct ibcs2_socksys_args *uap) -{ - int error; - int realargs[7]; /* 1 for command, 6 for recvfrom */ - void *passargs; - - /* - * SOCKET should only be legal on /dev/socksys. - * GETIPDOMAINNAME should only be legal on /dev/socksys ? - * The others are (and should be) only legal on sockets. - */ - - if ((error = copyin(uap->argsp, (caddr_t)realargs, sizeof(realargs))) != 0) - return error; - DPRINTF(("ibcs2_socksys: %08x %08x %08x %08x %08x %08x %08x\n", - realargs[0], realargs[1], realargs[2], realargs[3], - realargs[4], realargs[5], realargs[6])); - - passargs = (void *)(realargs + 1); - switch (realargs[0]) { - case SOCKSYS_ACCEPT: - return sys_accept(td, passargs); - case SOCKSYS_BIND: - return sys_bind(td, passargs); - case SOCKSYS_CONNECT: - return sys_connect(td, passargs); - case SOCKSYS_GETPEERNAME: - return sys_getpeername(td, passargs); - case SOCKSYS_GETSOCKNAME: - return sys_getsockname(td, passargs); - case SOCKSYS_GETSOCKOPT: - return sys_getsockopt(td, passargs); - case SOCKSYS_LISTEN: - return sys_listen(td, passargs); - case SOCKSYS_RECV: - realargs[5] = realargs[6] = 0; - /* FALLTHROUGH */ - case SOCKSYS_RECVFROM: - return sys_recvfrom(td, passargs); - case SOCKSYS_SEND: - realargs[5] = realargs[6] = 0; - /* FALLTHROUGH */ - case SOCKSYS_SENDTO: - return sys_sendto(td, passargs); - case SOCKSYS_SETSOCKOPT: - return sys_setsockopt(td, passargs); - case SOCKSYS_SHUTDOWN: - return sys_shutdown(td, passargs); - case SOCKSYS_SOCKET: - return sys_socket(td, passargs); - case SOCKSYS_SELECT: - return sys_select(td, passargs); - case SOCKSYS_GETIPDOMAIN: - return ibcs2_getipdomainname(td, passargs); - case SOCKSYS_SETIPDOMAIN: - return ibcs2_setipdomainname(td, passargs); - case SOCKSYS_ADJTIME: - return sys_adjtime(td, passargs); - case SOCKSYS_SETREUID: - return sys_setreuid(td, passargs); - case SOCKSYS_SETREGID: - return sys_setregid(td, passargs); - case SOCKSYS_GETTIME: - return sys_gettimeofday(td, passargs); - case SOCKSYS_SETTIME: - return sys_settimeofday(td, passargs); - case SOCKSYS_GETITIMER: - return sys_getitimer(td, passargs); - case SOCKSYS_SETITIMER: - return sys_setitimer(td, passargs); - - default: - printf("socksys unknown %08x %08x %08x %08x %08x %08x %08x\n", - realargs[0], realargs[1], realargs[2], realargs[3], - realargs[4], realargs[5], realargs[6]); - return EINVAL; - } - /* NOTREACHED */ -} - -/* ARGSUSED */ -static int -ibcs2_getipdomainname(struct thread *td, struct getipdomainname_args *uap) -{ - char hname[MAXHOSTNAMELEN], *dptr; - int len; - - /* Get the domain name. */ - getcredhostname(td->td_ucred, hname, sizeof(hname)); - - dptr = strchr(hname, '.'); - if ( dptr ) - dptr++; - else - /* Make it effectively an empty string */ - dptr = hname + strlen(hname); - - len = strlen(dptr) + 1; - if ((u_int)uap->len > len + 1) - uap->len = len + 1; - return (copyout((caddr_t)dptr, (caddr_t)uap->ipdomainname, uap->len)); -} - -/* ARGSUSED */ -static int -ibcs2_setipdomainname(struct thread *td, struct setipdomainname_args *uap) -{ - char hname[MAXHOSTNAMELEN], *ptr; - int error, sctl[2], hlen; - - /* Get the domain name */ - getcredhostname(td->td_ucred, hname, sizeof(hname)); - - /* W/out a hostname a domain-name is nonsense */ - if ( strlen(hname) == 0 ) - return EINVAL; - - /* Get the host's unqualified name (strip off the domain) */ - ptr = strchr(hname, '.'); - if ( ptr != NULL ) { - ptr++; - *ptr = '\0'; - } else { - if (strlcat(hname, ".", sizeof(hname)) >= sizeof(hname)) - return (EINVAL); - } - - /* Set ptr to the end of the string so we can append to it */ - hlen = strlen(hname); - ptr = hname + hlen; - if ((u_int)uap->len > (sizeof (hname) - hlen - 1)) - return EINVAL; - - /* Append the ipdomain to the end */ - error = copyinstr((caddr_t)uap->ipdomainname, ptr, uap->len, NULL); - if (error) - return (error); - - /* 'sethostname' with the new information */ - sctl[0] = CTL_KERN; - sctl[1] = KERN_HOSTNAME; - hlen = strlen(hname) + 1; - return (kernel_sysctl(td, sctl, 2, 0, 0, hname, hlen, 0, 0)); -} diff --git a/sys/i386/ibcs2/ibcs2_socksys.h b/sys/i386/ibcs2/ibcs2_socksys.h deleted file mode 100644 index 1d1a2d226e5..00000000000 --- a/sys/i386/ibcs2/ibcs2_socksys.h +++ /dev/null @@ -1,129 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 1994, 1995 Scott Bartram - * Copyright (c) 1994 Arne H Juul - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef _I386_IBCS2_IBCS2_SOCKSYS_H_ -#define _I386_IBCS2_IBCS2_SOCKSYS_H_ - -#include - -#include - -#define SOCKSYS_ACCEPT 1 -#define SOCKSYS_BIND 2 -#define SOCKSYS_CONNECT 3 -#define SOCKSYS_GETPEERNAME 4 -#define SOCKSYS_GETSOCKNAME 5 -#define SOCKSYS_GETSOCKOPT 6 -#define SOCKSYS_LISTEN 7 -#define SOCKSYS_RECV 8 -#define SOCKSYS_RECVFROM 9 -#define SOCKSYS_SEND 10 -#define SOCKSYS_SENDTO 11 -#define SOCKSYS_SETSOCKOPT 12 -#define SOCKSYS_SHUTDOWN 13 -#define SOCKSYS_SOCKET 14 -#define SOCKSYS_SELECT 15 -#define SOCKSYS_GETIPDOMAIN 16 -#define SOCKSYS_SETIPDOMAIN 17 -#define SOCKSYS_ADJTIME 18 -#define SOCKSYS_SETREUID 19 -#define SOCKSYS_SETREGID 20 -#define SOCKSYS_GETTIME 21 -#define SOCKSYS_SETTIME 22 -#define SOCKSYS_GETITIMER 23 -#define SOCKSYS_SETITIMER 24 - -#define IBCS2_SIOCSHIWAT _IOW('S', 1, int) -#define IBCS2_SIOCGHIWAT _IOR('S', 2, int) -#define IBCS2_SIOCSLOWAT _IOW('S', 3, int) -#define IBCS2_SIOCGLOWAT _IOR('S', 4, int) -#define IBCS2_SIOCATMARK _IOR('S', 5, int) -#define IBCS2_SIOCSPGRP _IOW('S', 6, int) -#define IBCS2_SIOCGPGRP _IOR('S', 7, int) -#define IBCS2_FIONREAD _IOR('S', 8, int) -#define IBCS2_FIONBIO _IOW('S', 9, int) -#define IBCS2_FIOASYNC _IOW('S', 10, int) -#define IBCS2_SIOCPROTO _IOW('S', 11, struct socknewproto) -#define IBCS2_SIOCGETNAME _IOR('S', 12, struct sockaddr) -#define IBCS2_SIOCGETPEER _IOR('S', 13, struct sockaddr) -#define IBCS2_IF_UNITSEL _IOW('S', 14, int) -#define IBCS2_SIOCXPROTO _IO('S', 15) - -#define IBCS2_SIOCADDRT _IOW('R', 9, struct rtentry) -#define IBCS2_SIOCDELRT _IOW('R', 10, struct rtentry) - -#define IBCS2_SIOCSIFADDR _IOW('I', 11, struct ifreq) -#define IBCS2_SIOCGIFADDR _IOWR('I', 12, struct ifreq) -#define IBCS2_SIOCSIFDSTADDR _IOW('I', 13, struct ifreq) -#define IBCS2_SIOCGIFDSTADDR _IOWR('I', 14, struct ifreq) -#define IBCS2_SIOCSIFFLAGS _IOW('I', 15, struct ifreq) -#define IBCS2_SIOCGIFFLAGS _IOWR('I', 16, struct ifreq) -#define IBCS2_SIOCGIFCONF _IOWR('I', 17, struct ifconf) -#define IBCS2_SIOCSIFMTU _IOW('I', 21, struct ifreq) -#define IBCS2_SIOCGIFMTU _IOWR('I', 22, struct ifreq) -#define IBCS2_SIOCIFDETACH _IOW('I', 26, struct ifreq) -#define IBCS2_SIOCGENPSTATS _IOWR('I', 27, struct ifreq) -#define IBCS2_SIOCX25XMT _IOWR('I', 29, struct ifreq) -#define IBCS2_SIOCX25RCV _IOWR('I', 30, struct ifreq) -#define IBCS2_SIOCX25TBL _IOWR('I', 31, struct ifreq) -#define IBCS2_SIOCGIFBRDADDR _IOWR('I', 32, struct ifreq) -#define IBCS2_SIOCSIFBRDADDR _IOW('I', 33, struct ifreq) -#define IBCS2_SIOCGIFNETMASK _IOWR('I', 34, struct ifreq) -#define IBCS2_SIOCSIFNETMASK _IOW('I', 35, struct ifreq) -#define IBCS2_SIOCGIFMETRIC _IOWR('I', 36, struct ifreq) -#define IBCS2_SIOCSIFMETRIC _IOW('I', 37, struct ifreq) -#define IBCS2_SIOCSARP _IOW('I', 38, struct arpreq) -#define IBCS2_SIOCGARP _IOWR('I', 39, struct arpreq) -#define IBCS2_SIOCDARP _IOW('I', 40, struct arpreq) -#define IBCS2_SIOCSIFNAME _IOW('I', 41, struct ifreq) -#define IBCS2_SIOCGIFONEP _IOWR('I', 42, struct ifreq) -#define IBCS2_SIOCSIFONEP _IOW('I', 43, struct ifreq) -#define IBCS2_SIOCGENADDR _IOWR('I', 65, struct ifreq) -#define IBCS2_SIOCSOCKSYS _IOW('I', 66, struct socksysreq) - -struct socksysreq { - int realargs[7]; -}; - -struct socknewproto { - int family; - int type; - int proto; - ibcs2_dev_t dev; - int flags; -}; - -struct ibcs2_socksys_args { - int fd; - int magic; - caddr_t argsp; -}; - -int ibcs2_socksys(struct thread *, struct ibcs2_socksys_args *); - -#endif /* !_I386_IBCS2_IBCS2_SOCKSYS_H_ */ diff --git a/sys/i386/ibcs2/ibcs2_stat.c b/sys/i386/ibcs2/ibcs2_stat.c deleted file mode 100644 index 6617d8cacc1..00000000000 --- a/sys/i386/ibcs2/ibcs2_stat.c +++ /dev/null @@ -1,244 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-3-Clause - * - * Copyright (c) 1995 Scott Bartram - * Copyright (c) 1995 Steven Wallace - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - - -static void bsd_stat2ibcs_stat(struct stat *, struct ibcs2_stat *); -static int cvt_statfs(struct statfs *, caddr_t, int); - -static void -bsd_stat2ibcs_stat(st, st4) - struct stat *st; - struct ibcs2_stat *st4; -{ - bzero(st4, sizeof(*st4)); - st4->st_dev = (ibcs2_dev_t)st->st_dev; - st4->st_ino = (ibcs2_ino_t)st->st_ino; - st4->st_mode = (ibcs2_mode_t)st->st_mode; - st4->st_nlink= (ibcs2_nlink_t)st->st_nlink; - st4->st_uid = (ibcs2_uid_t)st->st_uid; - st4->st_gid = (ibcs2_gid_t)st->st_gid; - st4->st_rdev = (ibcs2_dev_t)st->st_rdev; - if (st->st_size < (quad_t)1 << 32) - st4->st_size = (ibcs2_off_t)st->st_size; - else - st4->st_size = -2; - st4->st_atim = (ibcs2_time_t)st->st_atim.tv_sec; - st4->st_mtim = (ibcs2_time_t)st->st_mtim.tv_sec; - st4->st_ctim = (ibcs2_time_t)st->st_ctim.tv_sec; -} - -static int -cvt_statfs(sp, buf, len) - struct statfs *sp; - caddr_t buf; - int len; -{ - struct ibcs2_statfs ssfs; - - if (len < 0) - return (EINVAL); - else if (len > sizeof(ssfs)) - len = sizeof(ssfs); - bzero(&ssfs, sizeof ssfs); - ssfs.f_fstyp = 0; - ssfs.f_bsize = sp->f_bsize; - ssfs.f_frsize = 0; - ssfs.f_blocks = sp->f_blocks; - ssfs.f_bfree = sp->f_bfree; - ssfs.f_files = sp->f_files; - ssfs.f_ffree = sp->f_ffree; - ssfs.f_fname[0] = 0; - ssfs.f_fpack[0] = 0; - return copyout((caddr_t)&ssfs, buf, len); -} - -int -ibcs2_statfs(td, uap) - struct thread *td; - struct ibcs2_statfs_args *uap; -{ - struct statfs *sf; - char *path; - int error; - - CHECKALTEXIST(td, uap->path, &path); - sf = malloc(sizeof(struct statfs), M_STATFS, M_WAITOK); - error = kern_statfs(td, path, UIO_SYSSPACE, sf); - free(path, M_TEMP); - if (error == 0) - error = cvt_statfs(sf, (caddr_t)uap->buf, uap->len); - free(sf, M_STATFS); - return (error); -} - -int -ibcs2_fstatfs(td, uap) - struct thread *td; - struct ibcs2_fstatfs_args *uap; -{ - struct statfs *sf; - int error; - - sf = malloc(sizeof(struct statfs), M_STATFS, M_WAITOK); - error = kern_fstatfs(td, uap->fd, sf); - if (error == 0) - error = cvt_statfs(sf, (caddr_t)uap->buf, uap->len); - free(sf, M_STATFS); - return (error); -} - -int -ibcs2_stat(td, uap) - struct thread *td; - struct ibcs2_stat_args *uap; -{ - struct ibcs2_stat ibcs2_st; - struct stat st; - char *path; - int error; - - CHECKALTEXIST(td, uap->path, &path); - - error = kern_statat(td, 0, AT_FDCWD, path, UIO_SYSSPACE, &st, NULL); - free(path, M_TEMP); - if (error) - return (error); - bsd_stat2ibcs_stat(&st, &ibcs2_st); - return copyout((caddr_t)&ibcs2_st, (caddr_t)uap->st, - ibcs2_stat_len); -} - -int -ibcs2_lstat(td, uap) - struct thread *td; - struct ibcs2_lstat_args *uap; -{ - struct ibcs2_stat ibcs2_st; - struct stat st; - char *path; - int error; - - CHECKALTEXIST(td, uap->path, &path); - - error = kern_statat(td, AT_SYMLINK_NOFOLLOW, AT_FDCWD, path, - UIO_SYSSPACE, &st, NULL); - free(path, M_TEMP); - if (error) - return (error); - bsd_stat2ibcs_stat(&st, &ibcs2_st); - return copyout((caddr_t)&ibcs2_st, (caddr_t)uap->st, - ibcs2_stat_len); -} - -int -ibcs2_fstat(td, uap) - struct thread *td; - struct ibcs2_fstat_args *uap; -{ - struct ibcs2_stat ibcs2_st; - struct stat st; - int error; - - error = kern_fstat(td, uap->fd, &st); - if (error) - return (error); - bsd_stat2ibcs_stat(&st, &ibcs2_st); - return copyout((caddr_t)&ibcs2_st, (caddr_t)uap->st, - ibcs2_stat_len); -} - -int -ibcs2_utssys(td, uap) - struct thread *td; - struct ibcs2_utssys_args *uap; -{ - switch (uap->flag) { - case 0: /* uname(2) */ - { - char machine_name[9], *p; - struct ibcs2_utsname sut; - bzero(&sut, ibcs2_utsname_len); - - strncpy(sut.sysname, - IBCS2_UNAME_SYSNAME, sizeof(sut.sysname) - 1); - strncpy(sut.release, - IBCS2_UNAME_RELEASE, sizeof(sut.release) - 1); - strncpy(sut.version, - IBCS2_UNAME_VERSION, sizeof(sut.version) - 1); - getcredhostname(td->td_ucred, machine_name, - sizeof(machine_name) - 1); - p = strchr(machine_name, '.'); - if ( p ) - *p = '\0'; - strncpy(sut.nodename, machine_name, sizeof(sut.nodename) - 1); - strncpy(sut.machine, machine, sizeof(sut.machine) - 1); - - DPRINTF(("IBCS2 uname: sys=%s rel=%s ver=%s node=%s mach=%s\n", - sut.sysname, sut.release, sut.version, sut.nodename, - sut.machine)); - return copyout((caddr_t)&sut, (caddr_t)uap->a1, - ibcs2_utsname_len); - } - - case 2: /* ustat(2) */ - { - return ENOSYS; /* XXX - TODO */ - } - - default: - return ENOSYS; - } -} diff --git a/sys/i386/ibcs2/ibcs2_stat.h b/sys/i386/ibcs2/ibcs2_stat.h deleted file mode 100644 index 1b3a1e8e98a..00000000000 --- a/sys/i386/ibcs2/ibcs2_stat.h +++ /dev/null @@ -1,91 +0,0 @@ -/* $NetBSD: ibcs2_stat.h,v 1.2 1994/10/26 02:53:03 cgd Exp $ */ - -/*- - * SPDX-License-Identifier: BSD-4-Clause - * - * Copyright (c) 1994 Scott Bartram - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by Scott Bartram. - * 4. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _IBCS2_STAT_H -#define _IBCS2_STAT_H - -#include - -struct ibcs2_stat { - ibcs2_dev_t st_dev; - ibcs2_ino_t st_ino; - ibcs2_mode_t st_mode; - ibcs2_nlink_t st_nlink; - ibcs2_uid_t st_uid; - ibcs2_gid_t st_gid; - ibcs2_dev_t st_rdev; - ibcs2_off_t st_size; - ibcs2_time_t st_atim; - ibcs2_time_t st_mtim; - ibcs2_time_t st_ctim; -}; - -#define ibcs2_stat_len (sizeof(struct ibcs2_stat)) - -#define IBCS2_S_IFMT 0xf000 -#define IBCS2_S_IFIFO 0x1000 -#define IBCS2_S_IFCHR 0x2000 -#define IBCS2_S_IFDIR 0x4000 -#define IBCS2_S_IFBLK 0x6000 -#define IBCS2_S_IFREG 0x8000 -#define IBCS2_S_IFSOCK 0xc000 - -#define IBCS2_S_IFNAM 0x5000 -#define IBCS2_S_IFLNK 0xa000 - -#define IBCS2_S_ISUID 0x0800 -#define IBCS2_S_ISGID 0x0400 -#define IBCS2_S_ISVTX 0x0200 - -#define IBCS2_S_IRWXU 0x01c0 -#define IBCS2_S_IRUSR 0x0100 -#define IBCS2_S_IWUSR 0x0080 -#define IBCS2_S_IXUSR 0x0040 -#define IBCS2_S_IRWXG 0x0038 -#define IBCS2_S_IRGRP 0x0020 -#define IBCS2_S_IWGRP 0x000f -#define IBCS2_S_IXGRP 0x0008 -#define IBCS2_S_IRWXO 0x0007 -#define IBCS2_S_IROTH 0x0004 -#define IBCS2_S_IWOTH 0x0002 -#define IBCS2_S_IXOTH 0x0001 - -#define IBCS2_S_ISFIFO(mode) (((mode) & IBCS2_S_IFMT) == IBCS2_S_IFIFO) -#define IBCS2_S_ISCHR(mode) (((mode) & IBCS2_S_IFMT) == IBCS2_S_IFCHR) -#define IBCS2_S_ISDIR(mode) (((mode) & IBCS2_S_IFMT) == IBCS2_S_IFDIR) -#define IBCS2_S_ISBLK(mode) (((mode) & IBCS2_S_IFMT) == IBCS2_S_IFBLK) -#define IBCS2_S_ISREG(mode) (((mode) & IBCS2_S_IFMT) == IBCS2_S_IFREG) -#define IBCS2_S_ISSOCK(mode) (((mode) & IBCS2_S_IFMT) == IBCS2_S_IFSOCK) - -#endif /* _IBCS2_STAT_H */ diff --git a/sys/i386/ibcs2/ibcs2_statfs.h b/sys/i386/ibcs2/ibcs2_statfs.h deleted file mode 100644 index 759e54aa2fb..00000000000 --- a/sys/i386/ibcs2/ibcs2_statfs.h +++ /dev/null @@ -1,50 +0,0 @@ -/* $NetBSD: ibcs2_statfs.h,v 1.2 1994/10/26 02:53:06 cgd Exp $ */ - -/*- - * SPDX-License-Identifier: BSD-4-Clause - * - * Copyright (c) 1994 Scott Bartram - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by Scott Bartram. - * 4. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _IBCS2_STATFS_H -#define _IBCS2_STATFS_H - -struct ibcs2_statfs { - short f_fstyp; - long f_bsize; - long f_frsize; - long f_blocks; - long f_bfree; - long f_files; - long f_ffree; - char f_fname[6]; - char f_fpack[6]; -}; - -#endif /* _IBCS2_STATFS_H */ diff --git a/sys/i386/ibcs2/ibcs2_stropts.h b/sys/i386/ibcs2/ibcs2_stropts.h deleted file mode 100644 index 68b241a5034..00000000000 --- a/sys/i386/ibcs2/ibcs2_stropts.h +++ /dev/null @@ -1,51 +0,0 @@ -/*- - * ibcs2_stropts.h - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 1995 Scott Bartram - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef _IBCS2_STROPTS_H -#define _IBCS2_STROPTS_H - -#define IBCS2_STR ('S'<<8) -#define IBCS2_I_NREAD (IBCS2_STR|01) -#define IBCS2_I_PUSH (IBCS2_STR|02) -#define IBCS2_I_POP (IBCS2_STR|03) -#define IBCS2_I_LOOK (IBCS2_STR|04) -#define IBCS2_I_FLUSH (IBCS2_STR|05) -#define IBCS2_I_SRDOPT (IBCS2_STR|06) -#define IBCS2_I_GRDOPT (IBCS2_STR|07) -#define IBCS2_I_STR (IBCS2_STR|010) -#define IBCS2_I_SETSIG (IBCS2_STR|011) -#define IBCS2_I_GETSIG (IBCS2_STR|012) -#define IBCS2_I_FIND (IBCS2_STR|013) -#define IBCS2_I_LINK (IBCS2_STR|014) -#define IBCS2_I_UNLINK (IBCS2_STR|015) -#define IBCS2_I_PEEK (IBCS2_STR|017) -#define IBCS2_I_FDINSERT (IBCS2_STR|020) -#define IBCS2_I_SENDFD (IBCS2_STR|021) -#define IBCS2_I_RECVFD (IBCS2_STR|022) - -#endif /* _IBCS2_STROPTS_H */ diff --git a/sys/i386/ibcs2/ibcs2_syscall.h b/sys/i386/ibcs2/ibcs2_syscall.h deleted file mode 100644 index fe72939404e..00000000000 --- a/sys/i386/ibcs2/ibcs2_syscall.h +++ /dev/null @@ -1,88 +0,0 @@ -/* - * System call numbers. - * - * DO NOT EDIT-- this file is automatically @generated. - */ - -#define IBCS2_SYS_syscall 0 -#define IBCS2_SYS_exit 1 -#define IBCS2_SYS_fork 2 -#define IBCS2_SYS_ibcs2_read 3 -#define IBCS2_SYS_write 4 -#define IBCS2_SYS_ibcs2_open 5 -#define IBCS2_SYS_close 6 -#define IBCS2_SYS_ibcs2_wait 7 -#define IBCS2_SYS_ibcs2_creat 8 -#define IBCS2_SYS_link 9 -#define IBCS2_SYS_ibcs2_unlink 10 -#define IBCS2_SYS_ibcs2_execv 11 -#define IBCS2_SYS_ibcs2_chdir 12 -#define IBCS2_SYS_ibcs2_time 13 -#define IBCS2_SYS_ibcs2_mknod 14 -#define IBCS2_SYS_ibcs2_chmod 15 -#define IBCS2_SYS_ibcs2_chown 16 -#define IBCS2_SYS_break 17 -#define IBCS2_SYS_ibcs2_stat 18 -#define IBCS2_SYS_ibcs2_lseek 19 -#define IBCS2_SYS_getpid 20 -#define IBCS2_SYS_ibcs2_mount 21 -#define IBCS2_SYS_ibcs2_umount 22 -#define IBCS2_SYS_ibcs2_setuid 23 -#define IBCS2_SYS_getuid 24 -#define IBCS2_SYS_ibcs2_stime 25 -#define IBCS2_SYS_ptrace 26 -#define IBCS2_SYS_ibcs2_alarm 27 -#define IBCS2_SYS_ibcs2_fstat 28 -#define IBCS2_SYS_ibcs2_pause 29 -#define IBCS2_SYS_ibcs2_utime 30 -#define IBCS2_SYS_ibcs2_access 33 -#define IBCS2_SYS_ibcs2_nice 34 -#define IBCS2_SYS_ibcs2_statfs 35 -#define IBCS2_SYS_sync 36 -#define IBCS2_SYS_ibcs2_kill 37 -#define IBCS2_SYS_ibcs2_fstatfs 38 -#define IBCS2_SYS_ibcs2_pgrpsys 39 -#define IBCS2_SYS_ibcs2_xenix 40 -#define IBCS2_SYS_dup 41 -#define IBCS2_SYS_pipe 42 -#define IBCS2_SYS_ibcs2_times 43 -#define IBCS2_SYS_profil 44 -#define IBCS2_SYS_ibcs2_plock 45 -#define IBCS2_SYS_ibcs2_setgid 46 -#define IBCS2_SYS_getgid 47 -#define IBCS2_SYS_ibcs2_sigsys 48 -#define IBCS2_SYS_ibcs2_msgsys 49 -#define IBCS2_SYS_ibcs2_sysi86 50 -#define IBCS2_SYS_ibcs2_shmsys 52 -#define IBCS2_SYS_ibcs2_semsys 53 -#define IBCS2_SYS_ibcs2_ioctl 54 -#define IBCS2_SYS_ibcs2_uadmin 55 -#define IBCS2_SYS_ibcs2_utssys 57 -#define IBCS2_SYS_fsync 58 -#define IBCS2_SYS_ibcs2_execve 59 -#define IBCS2_SYS_umask 60 -#define IBCS2_SYS_chroot 61 -#define IBCS2_SYS_ibcs2_fcntl 62 -#define IBCS2_SYS_ibcs2_ulimit 63 - /* 70 is obsolete rfs_advfs */ - /* 71 is obsolete rfs_unadvfs */ - /* 72 is obsolete rfs_rmount */ - /* 73 is obsolete rfs_rumount */ - /* 74 is obsolete rfs_rfstart */ - /* 75 is obsolete rfs_sigret */ - /* 76 is obsolete rfs_rdebug */ - /* 77 is obsolete rfs_rfstop */ -#define IBCS2_SYS_ibcs2_rmdir 79 -#define IBCS2_SYS_ibcs2_mkdir 80 -#define IBCS2_SYS_ibcs2_getdents 81 -#define IBCS2_SYS_ibcs2_sysfs 84 -#define IBCS2_SYS_ibcs2_getmsg 85 -#define IBCS2_SYS_ibcs2_putmsg 86 -#define IBCS2_SYS_poll 87 -#define IBCS2_SYS_ibcs2_secure 89 -#define IBCS2_SYS_ibcs2_symlink 90 -#define IBCS2_SYS_ibcs2_lstat 91 -#define IBCS2_SYS_ibcs2_readlink 92 -#define IBCS2_SYS_sigreturn 103 -#define IBCS2_SYS_ibcs2_isc 105 -#define IBCS2_SYS_MAXSYSCALL 128 diff --git a/sys/i386/ibcs2/ibcs2_sysent.c b/sys/i386/ibcs2/ibcs2_sysent.c deleted file mode 100644 index b8312a7b99f..00000000000 --- a/sys/i386/ibcs2/ibcs2_sysent.c +++ /dev/null @@ -1,146 +0,0 @@ -/* - * System call switch table. - * - * DO NOT EDIT-- this file is automatically @generated. - */ - -#include -#include -#include -#include -#include -#include - -#define AS(name) (sizeof(struct name) / sizeof(register_t)) - -/* The casts are bogus but will do for now. */ -struct sysent ibcs2_sysent[] = { - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 0 = syscall */ - { AS(sys_exit_args), (sy_call_t *)sys_sys_exit, AUE_EXIT, NULL, 0, 0, 0, SY_THR_STATIC }, /* 1 = exit */ - { 0, (sy_call_t *)sys_fork, AUE_FORK, NULL, 0, 0, 0, SY_THR_STATIC }, /* 2 = fork */ - { AS(ibcs2_read_args), (sy_call_t *)ibcs2_read, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 3 = ibcs2_read */ - { AS(write_args), (sy_call_t *)sys_write, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 4 = write */ - { AS(ibcs2_open_args), (sy_call_t *)ibcs2_open, AUE_OPEN_RWTC, NULL, 0, 0, 0, SY_THR_STATIC }, /* 5 = ibcs2_open */ - { AS(close_args), (sy_call_t *)sys_close, AUE_CLOSE, NULL, 0, 0, 0, SY_THR_STATIC }, /* 6 = close */ - { AS(ibcs2_wait_args), (sy_call_t *)ibcs2_wait, AUE_WAIT4, NULL, 0, 0, 0, SY_THR_STATIC }, /* 7 = ibcs2_wait */ - { AS(ibcs2_creat_args), (sy_call_t *)ibcs2_creat, AUE_CREAT, NULL, 0, 0, 0, SY_THR_STATIC }, /* 8 = ibcs2_creat */ - { AS(link_args), (sy_call_t *)sys_link, AUE_LINK, NULL, 0, 0, 0, SY_THR_STATIC }, /* 9 = link */ - { AS(ibcs2_unlink_args), (sy_call_t *)ibcs2_unlink, AUE_UNLINK, NULL, 0, 0, 0, SY_THR_STATIC }, /* 10 = ibcs2_unlink */ - { AS(ibcs2_execv_args), (sy_call_t *)ibcs2_execv, AUE_EXECVE, NULL, 0, 0, 0, SY_THR_STATIC }, /* 11 = ibcs2_execv */ - { AS(ibcs2_chdir_args), (sy_call_t *)ibcs2_chdir, AUE_CHDIR, NULL, 0, 0, 0, SY_THR_STATIC }, /* 12 = ibcs2_chdir */ - { AS(ibcs2_time_args), (sy_call_t *)ibcs2_time, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 13 = ibcs2_time */ - { AS(ibcs2_mknod_args), (sy_call_t *)ibcs2_mknod, AUE_MKNOD, NULL, 0, 0, 0, SY_THR_STATIC }, /* 14 = ibcs2_mknod */ - { AS(ibcs2_chmod_args), (sy_call_t *)ibcs2_chmod, AUE_CHMOD, NULL, 0, 0, 0, SY_THR_STATIC }, /* 15 = ibcs2_chmod */ - { AS(ibcs2_chown_args), (sy_call_t *)ibcs2_chown, AUE_CHOWN, NULL, 0, 0, 0, SY_THR_STATIC }, /* 16 = ibcs2_chown */ - { AS(break_args), (sy_call_t *)sys_break, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 17 = break */ - { AS(ibcs2_stat_args), (sy_call_t *)ibcs2_stat, AUE_STAT, NULL, 0, 0, 0, SY_THR_STATIC }, /* 18 = ibcs2_stat */ - { AS(ibcs2_lseek_args), (sy_call_t *)ibcs2_lseek, AUE_LSEEK, NULL, 0, 0, 0, SY_THR_STATIC }, /* 19 = ibcs2_lseek */ - { 0, (sy_call_t *)sys_getpid, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 20 = getpid */ - { AS(ibcs2_mount_args), (sy_call_t *)ibcs2_mount, AUE_MOUNT, NULL, 0, 0, 0, SY_THR_STATIC }, /* 21 = ibcs2_mount */ - { AS(ibcs2_umount_args), (sy_call_t *)ibcs2_umount, AUE_UMOUNT, NULL, 0, 0, 0, SY_THR_STATIC }, /* 22 = ibcs2_umount */ - { AS(ibcs2_setuid_args), (sy_call_t *)ibcs2_setuid, AUE_SETUID, NULL, 0, 0, 0, SY_THR_STATIC }, /* 23 = ibcs2_setuid */ - { 0, (sy_call_t *)sys_getuid, AUE_GETUID, NULL, 0, 0, 0, SY_THR_STATIC }, /* 24 = getuid */ - { AS(ibcs2_stime_args), (sy_call_t *)ibcs2_stime, AUE_SETTIMEOFDAY, NULL, 0, 0, 0, SY_THR_STATIC }, /* 25 = ibcs2_stime */ - { AS(ptrace_args), (sy_call_t *)sys_ptrace, AUE_PTRACE, NULL, 0, 0, 0, SY_THR_STATIC }, /* 26 = ptrace */ - { AS(ibcs2_alarm_args), (sy_call_t *)ibcs2_alarm, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 27 = ibcs2_alarm */ - { AS(ibcs2_fstat_args), (sy_call_t *)ibcs2_fstat, AUE_FSTAT, NULL, 0, 0, 0, SY_THR_STATIC }, /* 28 = ibcs2_fstat */ - { 0, (sy_call_t *)ibcs2_pause, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 29 = ibcs2_pause */ - { AS(ibcs2_utime_args), (sy_call_t *)ibcs2_utime, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 30 = ibcs2_utime */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 31 = ibcs2_stty */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 32 = ibcs2_gtty */ - { AS(ibcs2_access_args), (sy_call_t *)ibcs2_access, AUE_ACCESS, NULL, 0, 0, 0, SY_THR_STATIC }, /* 33 = ibcs2_access */ - { AS(ibcs2_nice_args), (sy_call_t *)ibcs2_nice, AUE_NICE, NULL, 0, 0, 0, SY_THR_STATIC }, /* 34 = ibcs2_nice */ - { AS(ibcs2_statfs_args), (sy_call_t *)ibcs2_statfs, AUE_STATFS, NULL, 0, 0, 0, SY_THR_STATIC }, /* 35 = ibcs2_statfs */ - { 0, (sy_call_t *)sys_sync, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 36 = sync */ - { AS(ibcs2_kill_args), (sy_call_t *)ibcs2_kill, AUE_KILL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 37 = ibcs2_kill */ - { AS(ibcs2_fstatfs_args), (sy_call_t *)ibcs2_fstatfs, AUE_FSTATFS, NULL, 0, 0, 0, SY_THR_STATIC }, /* 38 = ibcs2_fstatfs */ - { AS(ibcs2_pgrpsys_args), (sy_call_t *)ibcs2_pgrpsys, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 39 = ibcs2_pgrpsys */ - { AS(ibcs2_xenix_args), (sy_call_t *)ibcs2_xenix, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 40 = ibcs2_xenix */ - { AS(dup_args), (sy_call_t *)sys_dup, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 41 = dup */ - { 0, (sy_call_t *)sys_pipe, AUE_PIPE, NULL, 0, 0, 0, SY_THR_STATIC }, /* 42 = pipe */ - { AS(ibcs2_times_args), (sy_call_t *)ibcs2_times, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 43 = ibcs2_times */ - { AS(profil_args), (sy_call_t *)sys_profil, AUE_PROFILE, NULL, 0, 0, 0, SY_THR_STATIC }, /* 44 = profil */ - { AS(ibcs2_plock_args), (sy_call_t *)ibcs2_plock, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 45 = ibcs2_plock */ - { AS(ibcs2_setgid_args), (sy_call_t *)ibcs2_setgid, AUE_SETGID, NULL, 0, 0, 0, SY_THR_STATIC }, /* 46 = ibcs2_setgid */ - { 0, (sy_call_t *)sys_getgid, AUE_GETGID, NULL, 0, 0, 0, SY_THR_STATIC }, /* 47 = getgid */ - { AS(ibcs2_sigsys_args), (sy_call_t *)ibcs2_sigsys, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 48 = ibcs2_sigsys */ - { AS(ibcs2_msgsys_args), (sy_call_t *)ibcs2_msgsys, AUE_MSGSYS, NULL, 0, 0, 0, SY_THR_STATIC }, /* 49 = ibcs2_msgsys */ - { AS(ibcs2_sysi86_args), (sy_call_t *)ibcs2_sysi86, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 50 = ibcs2_sysi86 */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 51 = ibcs2_acct */ - { AS(ibcs2_shmsys_args), (sy_call_t *)ibcs2_shmsys, AUE_SHMSYS, NULL, 0, 0, 0, SY_THR_STATIC }, /* 52 = ibcs2_shmsys */ - { AS(ibcs2_semsys_args), (sy_call_t *)ibcs2_semsys, AUE_SEMSYS, NULL, 0, 0, 0, SY_THR_STATIC }, /* 53 = ibcs2_semsys */ - { AS(ibcs2_ioctl_args), (sy_call_t *)ibcs2_ioctl, AUE_IOCTL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 54 = ibcs2_ioctl */ - { AS(ibcs2_uadmin_args), (sy_call_t *)ibcs2_uadmin, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 55 = ibcs2_uadmin */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 56 = nosys */ - { AS(ibcs2_utssys_args), (sy_call_t *)ibcs2_utssys, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 57 = ibcs2_utssys */ - { AS(fsync_args), (sy_call_t *)sys_fsync, AUE_FSYNC, NULL, 0, 0, 0, SY_THR_STATIC }, /* 58 = fsync */ - { AS(ibcs2_execve_args), (sy_call_t *)ibcs2_execve, AUE_EXECVE, NULL, 0, 0, 0, SY_THR_STATIC }, /* 59 = ibcs2_execve */ - { AS(umask_args), (sy_call_t *)sys_umask, AUE_UMASK, NULL, 0, 0, 0, SY_THR_STATIC }, /* 60 = umask */ - { AS(chroot_args), (sy_call_t *)sys_chroot, AUE_CHROOT, NULL, 0, 0, 0, SY_THR_STATIC }, /* 61 = chroot */ - { AS(ibcs2_fcntl_args), (sy_call_t *)ibcs2_fcntl, AUE_FCNTL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 62 = ibcs2_fcntl */ - { AS(ibcs2_ulimit_args), (sy_call_t *)ibcs2_ulimit, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 63 = ibcs2_ulimit */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 64 = reserved for unix/pc */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 65 = reserved for unix/pc */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 66 = reserved for unix/pc */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 67 = reserved for unix/pc */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 68 = reserved for unix/pc */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 69 = reserved for unix/pc */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 70 = obsolete rfs_advfs */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 71 = obsolete rfs_unadvfs */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 72 = obsolete rfs_rmount */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 73 = obsolete rfs_rumount */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 74 = obsolete rfs_rfstart */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 75 = obsolete rfs_sigret */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 76 = obsolete rfs_rdebug */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 77 = obsolete rfs_rfstop */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 78 = rfs_rfsys */ - { AS(ibcs2_rmdir_args), (sy_call_t *)ibcs2_rmdir, AUE_RMDIR, NULL, 0, 0, 0, SY_THR_STATIC }, /* 79 = ibcs2_rmdir */ - { AS(ibcs2_mkdir_args), (sy_call_t *)ibcs2_mkdir, AUE_MKDIR, NULL, 0, 0, 0, SY_THR_STATIC }, /* 80 = ibcs2_mkdir */ - { AS(ibcs2_getdents_args), (sy_call_t *)ibcs2_getdents, AUE_GETDIRENTRIES, NULL, 0, 0, 0, SY_THR_STATIC }, /* 81 = ibcs2_getdents */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 82 = nosys */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 83 = nosys */ - { AS(ibcs2_sysfs_args), (sy_call_t *)ibcs2_sysfs, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 84 = ibcs2_sysfs */ - { AS(ibcs2_getmsg_args), (sy_call_t *)ibcs2_getmsg, AUE_GETMSG, NULL, 0, 0, 0, SY_THR_STATIC }, /* 85 = ibcs2_getmsg */ - { AS(ibcs2_putmsg_args), (sy_call_t *)ibcs2_putmsg, AUE_PUTMSG, NULL, 0, 0, 0, SY_THR_STATIC }, /* 86 = ibcs2_putmsg */ - { AS(poll_args), (sy_call_t *)sys_poll, AUE_POLL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 87 = poll */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 88 = nosys */ - { AS(ibcs2_secure_args), (sy_call_t *)ibcs2_secure, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 89 = ibcs2_secure */ - { AS(ibcs2_symlink_args), (sy_call_t *)ibcs2_symlink, AUE_SYMLINK, NULL, 0, 0, 0, SY_THR_STATIC }, /* 90 = ibcs2_symlink */ - { AS(ibcs2_lstat_args), (sy_call_t *)ibcs2_lstat, AUE_LSTAT, NULL, 0, 0, 0, SY_THR_STATIC }, /* 91 = ibcs2_lstat */ - { AS(ibcs2_readlink_args), (sy_call_t *)ibcs2_readlink, AUE_READLINK, NULL, 0, 0, 0, SY_THR_STATIC }, /* 92 = ibcs2_readlink */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 93 = nosys */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 94 = nosys */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 95 = nosys */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 96 = nosys */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 97 = nosys */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 98 = nosys */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 99 = nosys */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 100 = nosys */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 101 = nosys */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 102 = nosys */ - { AS(sigreturn_args), (sy_call_t *)sys_sigreturn, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 103 = sigreturn */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 104 = nosys */ - { 0, (sy_call_t *)ibcs2_isc, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 105 = ibcs2_isc */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 106 = nosys */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 107 = nosys */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 108 = nosys */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 109 = nosys */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 110 = nosys */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 111 = nosys */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 112 = nosys */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 113 = nosys */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 114 = nosys */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 115 = nosys */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 116 = nosys */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 117 = nosys */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 118 = nosys */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 119 = nosys */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 120 = nosys */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 121 = nosys */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 122 = nosys */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 123 = nosys */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 124 = nosys */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 125 = nosys */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 126 = nosys */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 127 = nosys */ -}; diff --git a/sys/i386/ibcs2/ibcs2_sysi86.c b/sys/i386/ibcs2/ibcs2_sysi86.c deleted file mode 100644 index 70a6aad11e7..00000000000 --- a/sys/i386/ibcs2/ibcs2_sysi86.c +++ /dev/null @@ -1,97 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-3-Clause - * - * Copyright (c) 1994 Søren Schmidt - * Copyright (c) 1995 Steven Wallace - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer - * in this position and unchanged. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include - -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#define IBCS2_FP_NO 0 /* no fp support */ -#define IBCS2_FP_SW 1 /* software emulator */ -#define IBCS2_FP_287 2 /* 80287 FPU */ -#define IBCS2_FP_387 3 /* 80387 FPU */ - -#define SI86_FPHW 40 -#define STIME 54 -#define SETNAME 56 -#define SI86_MEM 65 - -extern int hw_float; - -int -ibcs2_sysi86(struct thread *td, struct ibcs2_sysi86_args *args) -{ - switch (args->cmd) { - case SI86_FPHW: { /* Floating Point information */ - int val, error; - - if (hw_float) - val = IBCS2_FP_387; - else - val = IBCS2_FP_NO; - if ((error = copyout(&val, args->arg, sizeof(val))) != 0) - return error; - return 0; - } - - case STIME: /* set the system time given pointer to long */ - /* gettimeofday; time.tv_sec = *args->arg; settimeofday */ - return EINVAL; - - case SETNAME: { /* set hostname given string w/ len <= 7 chars */ - int name[2]; - - name[0] = CTL_KERN; - name[1] = KERN_HOSTNAME; - return (userland_sysctl(td, name, 2, 0, 0, 0, - args->arg, 7, 0, 0)); - } - - case SI86_MEM: /* size of physical memory */ - td->td_retval[0] = ctob(physmem); - return 0; - - default: -#ifdef DIAGNOSTIC - printf("IBCS2: 'sysi86' function %d(0x%x) " - "not implemented yet\n", args->cmd, args->cmd); -#endif - return EINVAL; - } -} diff --git a/sys/i386/ibcs2/ibcs2_sysvec.c b/sys/i386/ibcs2/ibcs2_sysvec.c deleted file mode 100644 index 31b8e0adbbb..00000000000 --- a/sys/i386/ibcs2/ibcs2_sysvec.c +++ /dev/null @@ -1,139 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-4-Clause - * - * Copyright (c) 1995 Steven Wallace - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by Steven Wallace. - * 4. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include -#include - -MODULE_VERSION(ibcs2, 1); - -extern int bsd_to_ibcs2_errno[]; -extern struct sysent ibcs2_sysent[IBCS2_SYS_MAXSYSCALL]; -static int ibcs2_fixup(register_t **, struct image_params *); - -struct sysentvec ibcs2_svr3_sysvec = { - .sv_size = nitems(ibcs2_sysent), - .sv_table = ibcs2_sysent, - .sv_mask = 0xff, - .sv_sigsize = IBCS2_SIGTBLSZ, - .sv_sigtbl = bsd_to_ibcs2_sig, - .sv_errsize = ELAST + 1, - .sv_errtbl = bsd_to_ibcs2_errno, - .sv_transtrap = NULL, - .sv_fixup = ibcs2_fixup, - .sv_sendsig = sendsig, - .sv_sigcode = sigcode, /* use generic trampoline */ - .sv_szsigcode = &szsigcode, - .sv_prepsyscall = NULL, - .sv_name = "IBCS2 COFF", - .sv_coredump = NULL, /* we don't have a COFF coredump function */ - .sv_imgact_try = NULL, - .sv_minsigstksz = IBCS2_MINSIGSTKSZ, - .sv_pagesize = PAGE_SIZE, - .sv_minuser = VM_MIN_ADDRESS, - .sv_maxuser = VM_MAXUSER_ADDRESS, - .sv_usrstack = USRSTACK, - .sv_psstrings = PS_STRINGS, - .sv_stackprot = VM_PROT_ALL, - .sv_copyout_strings = exec_copyout_strings, - .sv_setregs = exec_setregs, - .sv_fixlimit = NULL, - .sv_maxssiz = NULL, - .sv_flags = SV_ABI_UNDEF | SV_IA32 | SV_ILP32, - .sv_set_syscall_retval = cpu_set_syscall_retval, - .sv_fetch_syscall_args = cpu_fetch_syscall_args, - .sv_syscallnames = NULL, - .sv_schedtail = NULL, - .sv_thread_detach = NULL, - .sv_trap = NULL, -}; - -static int -ibcs2_fixup(register_t **stack_base, struct image_params *imgp) -{ - - return (suword(--(*stack_base), imgp->args->argc)); -} - -/* - * Create an "ibcs2" module that does nothing but allow checking for - * the presence of the subsystem. - */ -static int -ibcs2_modevent(module_t mod, int type, void *unused) -{ - struct proc *p = NULL; - int rval = 0; - - switch(type) { - case MOD_LOAD: - break; - case MOD_UNLOAD: - /* if this was an ELF module we'd use elf_brand_inuse()... */ - sx_slock(&allproc_lock); - FOREACH_PROC_IN_SYSTEM(p) { - if (p->p_sysent == &ibcs2_svr3_sysvec) { - rval = EBUSY; - break; - } - } - sx_sunlock(&allproc_lock); - break; - default: - rval = EOPNOTSUPP; - break; - } - return (rval); -} -static moduledata_t ibcs2_mod = { - "ibcs2", - ibcs2_modevent, - 0 -}; -DECLARE_MODULE_TIED(ibcs2, ibcs2_mod, SI_SUB_PSEUDO, SI_ORDER_ANY); diff --git a/sys/i386/ibcs2/ibcs2_termios.h b/sys/i386/ibcs2/ibcs2_termios.h deleted file mode 100644 index f0dd3b900c2..00000000000 --- a/sys/i386/ibcs2/ibcs2_termios.h +++ /dev/null @@ -1,237 +0,0 @@ -/* $NetBSD: ibcs2_termios.h,v 1.3 1994/10/26 02:53:07 cgd Exp $ */ - -/*- - * SPDX-License-Identifier: BSD-4-Clause - * - * Copyright (c) 1994 Scott Bartram - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by Scott Bartram. - * 4. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _IBCS2_TERMIOS_H -#define _IBCS2_TERMIOS_H 1 - -#include - -#define IBCS2_NCC 8 -#define IBCS2_NCCS 13 - -typedef u_short ibcs2_tcflag_t; -typedef u_char ibcs2_cc_t; -typedef u_long ibcs2_speed_t; - -struct ibcs2_termio { - u_short c_iflag; - u_short c_oflag; - u_short c_cflag; - u_short c_lflag; - char c_line; - u_char c_cc[IBCS2_NCC]; -}; - -struct ibcs2_termios { - ibcs2_tcflag_t c_iflag; - ibcs2_tcflag_t c_oflag; - ibcs2_tcflag_t c_cflag; - ibcs2_tcflag_t c_lflag; - char c_line; - ibcs2_cc_t c_cc[IBCS2_NCCS]; - char c_ispeed; - char c_ospeed; -}; - -#define IBCS2_VINTR 0 -#define IBCS2_VQUIT 1 -#define IBCS2_VERASE 2 -#define IBCS2_VKILL 3 -#define IBCS2_VEOF 4 -#define IBCS2_VEOL 5 -#define IBCS2_VEOL2 6 -#define IBCS2_VMIN 4 -#define IBCS2_VTIME 5 -#define IBCS2_VSWTCH 7 -#define IBCS2_VSUSP 10 -#define IBCS2_VSTART 11 -#define IBCS2_VSTOP 12 - -#define IBCS2_CNUL 0 -#define IBCS2_CDEL 0377 -#define IBCS2_CESC '\\' -#define IBCS2_CINTR 0177 -#define IBCS2_CQUIT 034 -#define IBCS2_CERASE '#' -#define IBCS2_CKILL '@' -#define IBCS2_CSTART 021 -#define IBCS2_CSTOP 023 -#define IBCS2_CSWTCH 032 -#define IBCS2_CNSWTCH 0 -#define IBCS2_CSUSP 032 - -#define IBCS2_IGNBRK 0000001 -#define IBCS2_BRKINT 0000002 -#define IBCS2_IGNPAR 0000004 -#define IBCS2_PARMRK 0000010 -#define IBCS2_INPCK 0000020 -#define IBCS2_ISTRIP 0000040 -#define IBCS2_INLCR 0000100 -#define IBCS2_IGNCR 0000200 -#define IBCS2_ICRNL 0000400 -#define IBCS2_IUCLC 0001000 -#define IBCS2_IXON 0002000 -#define IBCS2_IXANY 0004000 -#define IBCS2_IXOFF 0010000 -#define IBCS2_IMAXBEL 0020000 -#define IBCS2_DOSMODE 0100000 - -#define IBCS2_OPOST 0000001 -#define IBCS2_OLCUC 0000002 -#define IBCS2_ONLCR 0000004 -#define IBCS2_OCRNL 0000010 -#define IBCS2_ONOCR 0000020 -#define IBCS2_ONLRET 0000040 -#define IBCS2_OFILL 0000100 -#define IBCS2_OFDEL 0000200 -#define IBCS2_NLDLY 0000400 -#define IBCS2_NL0 0000000 -#define IBCS2_NL1 0000400 -#define IBCS2_CRDLY 0003000 -#define IBCS2_CR0 0000000 -#define IBCS2_CR1 0001000 -#define IBCS2_CR2 0002000 -#define IBCS2_CR3 0003000 -#define IBCS2_TABDLY 0014000 -#define IBCS2_TAB0 0000000 -#define IBCS2_TAB1 0004000 -#define IBCS2_TAB2 0010000 -#define IBCS2_TAB3 0014000 -#define IBCS2_BSDLY 0020000 -#define IBCS2_BS0 0000000 -#define IBCS2_BS1 0020000 -#define IBCS2_VTDLY 0040000 -#define IBCS2_VT0 0000000 -#define IBCS2_VT1 0040000 -#define IBCS2_FFDLY 0100000 -#define IBCS2_FF0 0000000 -#define IBCS2_FF1 0100000 - -#define IBCS2_CBAUD 0000017 -#define IBCS2_CSIZE 0000060 -#define IBCS2_CS5 0000000 -#define IBCS2_CS6 0000020 -#define IBCS2_CS7 0000040 -#define IBCS2_CS8 0000060 -#define IBCS2_CSTOPB 0000100 -#define IBCS2_CREAD 0000200 -#define IBCS2_PARENB 0000400 -#define IBCS2_PARODD 0001000 -#define IBCS2_HUPCL 0002000 -#define IBCS2_CLOCAL 0004000 -#define IBCS2_RCV1EN 0010000 -#define IBCS2_XMT1EN 0020000 -#define IBCS2_LOBLK 0040000 -#define IBCS2_XCLUDE 0100000 - -#define IBCS2_ISIG 0000001 -#define IBCS2_ICANON 0000002 -#define IBCS2_XCASE 0000004 -#define IBCS2_ECHO 0000010 -#define IBCS2_ECHOE 0000020 -#define IBCS2_ECHOK 0000040 -#define IBCS2_ECHONL 0000100 -#define IBCS2_NOFLSH 0000200 -#define IBCS2_IEXTEN 0000400 -#define IBCS2_TOSTOP 0001000 - -#define IBCS2_XIOC (('i'<<24)|('X'<<16)) -#define IBCS2_XCGETA (IBCS2_XIOC|1) -#define IBCS2_XCSETA (IBCS2_XIOC|2) -#define IBCS2_XCSETAW (IBCS2_XIOC|3) -#define IBCS2_XCSETAF (IBCS2_XIOC|4) - -#define IBCS2_OXIOC ('x'<<8) -#define IBCS2_OXCGETA (IBCS2_OXIOC|1) -#define IBCS2_OXCSETA (IBCS2_OXIOC|2) -#define IBCS2_OXCSETAW (IBCS2_OXIOC|3) -#define IBCS2_OXCSETAF (IBCS2_OXIOC|4) - -#define IBCS2_TIOC ('T'<<8) -#define IBCS2_TCGETA (IBCS2_TIOC|1) -#define IBCS2_TCSETA (IBCS2_TIOC|2) -#define IBCS2_TCSETAW (IBCS2_TIOC|3) -#define IBCS2_TCSETAF (IBCS2_TIOC|4) -#define IBCS2_TCSBRK (IBCS2_TIOC|5) -#define IBCS2_TCXONC (IBCS2_TIOC|6) -#define IBCS2_TCFLSH (IBCS2_TIOC|7) - -#define IBCS2_TCGETSC (IBCS2_TIOC|34) -#define IBCS2_TCSETSC (IBCS2_TIOC|35) - -#define IBCS2_TIOCSWINSZ (IBCS2_TIOC|103) -#define IBCS2_TIOCGWINSZ (IBCS2_TIOC|104) -#define IBCS2_TIOCSPGRP (IBCS2_TIOC|118) -#define IBCS2_TIOCGPGRP (IBCS2_TIOC|119) - -#define IBCS2_TCSANOW IBCS2_XCSETA -#define IBCS2_TCSADRAIN IBCS2_XCSETAW -#define IBCS2_TCSAFLUSH IBCS2_XCSETAF -#define IBCS2_TCSADFLUSH IBCS2_XCSETAF - -#define IBCS2_TCIFLUSH 0 -#define IBCS2_TCOFLUSH 1 -#define IBCS2_TCIOFLUSH 2 - -#define IBCS2_TCOOFF 0 -#define IBCS2_TCOON 1 -#define IBCS2_TCIOFF 2 -#define IBCS2_TCION 3 - -#define IBCS2_B0 0 -#define IBCS2_B50 1 -#define IBCS2_B75 2 -#define IBCS2_B110 3 -#define IBCS2_B134 4 -#define IBCS2_B150 5 -#define IBCS2_B200 6 -#define IBCS2_B300 7 -#define IBCS2_B600 8 -#define IBCS2_B1200 9 -#define IBCS2_B1800 10 -#define IBCS2_B2400 11 -#define IBCS2_B4800 12 -#define IBCS2_B9600 13 -#define IBCS2_B19200 14 -#define IBCS2_B38400 15 - -struct ibcs2_winsize { - u_short ws_row; - u_short ws_col; - u_short ws_xpixel; - u_short ws_ypixel; -}; - -#endif /* _IBCS2_H_ */ - diff --git a/sys/i386/ibcs2/ibcs2_time.h b/sys/i386/ibcs2/ibcs2_time.h deleted file mode 100644 index 4bed80129f2..00000000000 --- a/sys/i386/ibcs2/ibcs2_time.h +++ /dev/null @@ -1,52 +0,0 @@ -/* $NetBSD: ibcs2_time.h,v 1.2 1994/10/26 02:53:08 cgd Exp $ */ - -/*- - * SPDX-License-Identifier: BSD-4-Clause - * - * Copyright (c) 1994 Scott Bartram - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by Scott Bartram. - * 4. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _IBCS2_TIME_H -#define _IBCS2_TIME_H - -#include - -struct ibcs2_tm { - int tm_sec; - int tm_min; - int tm_hour; - int tm_mday; - int tm_mon; - int tm_year; - int tm_wday; - int tm_yday; - int tm_isdst; -}; - -#endif /* _IBCS2_TIME_H */ diff --git a/sys/i386/ibcs2/ibcs2_types.h b/sys/i386/ibcs2/ibcs2_types.h deleted file mode 100644 index 192ed7ebc91..00000000000 --- a/sys/i386/ibcs2/ibcs2_types.h +++ /dev/null @@ -1,56 +0,0 @@ -/* $NetBSD: ibcs2_types.h,v 1.5 1995/08/14 01:11:54 mycroft Exp $ */ - -/*- - * SPDX-License-Identifier: BSD-4-Clause - * - * Copyright (c) 1994 Scott Bartram - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by Scott Bartram. - * 4. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _IBCS2_TYPES_H -#define _IBCS2_TYPES_H - -typedef unsigned char ibcs2_uchar_t; -typedef unsigned long ibcs2_ulong_t; - -typedef char * ibcs2_caddr_t; -typedef long ibcs2_daddr_t; -typedef long ibcs2_off_t; -typedef long ibcs2_key_t; -typedef unsigned short ibcs2_uid_t; -typedef unsigned short ibcs2_gid_t; -typedef short ibcs2_nlink_t; -typedef short ibcs2_dev_t; -typedef unsigned short ibcs2_ino_t; -typedef unsigned int ibcs2_size_t; -typedef long ibcs2_time_t; -typedef long ibcs2_clock_t; -typedef unsigned short ibcs2_mode_t; -typedef short ibcs2_pid_t; - -#endif /* _IBCS2_TYPES_H */ diff --git a/sys/i386/ibcs2/ibcs2_unistd.h b/sys/i386/ibcs2/ibcs2_unistd.h deleted file mode 100644 index f2b1656c8a5..00000000000 --- a/sys/i386/ibcs2/ibcs2_unistd.h +++ /dev/null @@ -1,77 +0,0 @@ -/* $NetBSD: ibcs2_unistd.h,v 1.2 1994/10/26 02:53:11 cgd Exp $ */ - -/*- - * SPDX-License-Identifier: BSD-4-Clause - * - * Copyright (c) 1994 Scott Bartram - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by Scott Bartram. - * 4. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _IBCS2_UNISTD_H -#define _IBCS2_UNISTD_H - -#define IBCS2_R_OK 4 -#define IBCS2_W_OK 2 -#define IBCS2_X_OK 1 -#define IBCS2_F_OK 0 - -#define IBCS2_F_ULOCK 0 -#define IBCS2_F_LOCK 1 -#define IBCS2_F_TLOCK 2 -#define IBCS2_F_TEST 3 - -#define IBCS2_SEEK_SET 0 -#define IBCS2_SEEK_CUR 1 -#define IBCS2_SEEK_END 2 - -#define IBCS2_SC_ARG_MAX 0 -#define IBCS2_SC_CHILD_MAX 1 -#define IBCS2_SC_CLK_TCK 2 -#define IBCS2_SC_NGROUPS_MAX 3 -#define IBCS2_SC_OPEN_MAX 4 -#define IBCS2_SC_JOB_CONTROL 5 -#define IBCS2_SC_SAVED_IDS 6 -#define IBCS2_SC_VERSION 7 -#define IBCS2_SC_PASS_MAX 8 -#define IBCS2_SC_XOPEN_VERSION 9 - -#define IBCS2_PC_LINK_MAX 0 -#define IBCS2_PC_MAX_CANON 1 -#define IBCS2_PC_MAX_INPUT 2 -#define IBCS2_PC_NAME_MAX 3 -#define IBCS2_PC_PATH_MAX 4 -#define IBCS2_PC_PIPE_BUF 5 -#define IBCS2_PC_CHOWN_RESTRICTED 6 -#define IBCS2_PC_NO_TRUNC 7 -#define IBCS2_PC_VDISABLE 8 - -#define IBCS2_STDIN_FILENO 0 -#define IBCS2_STDOUT_FILENO 1 -#define IBCS2_STDERR_FILENO 2 - -#endif /* _IBCS2_UNISTD_H */ diff --git a/sys/i386/ibcs2/ibcs2_ustat.h b/sys/i386/ibcs2/ibcs2_ustat.h deleted file mode 100644 index 62f9cb04bd5..00000000000 --- a/sys/i386/ibcs2/ibcs2_ustat.h +++ /dev/null @@ -1,48 +0,0 @@ -/* $NetBSD: ibcs2_ustat.h,v 1.2 1994/10/26 02:53:13 cgd Exp $ */ - -/*- - * SPDX-License-Identifier: BSD-4-Clause - * - * Copyright (c) 1994 Scott Bartram - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by Scott Bartram. - * 4. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _IBCS2_USTAT_H -#define _IBCS2_USTAT_H 1 - -#include - -struct ibcs2_ustat { - long f_tfree; - ibcs2_ino_t f_tinode; - char f_fname[6]; - char f_fpack[6]; -}; -#define ibcs2_ustat_len (sizeof(struct ibcs2_ustat)) - -#endif /* _IBCS2_USTAT_H */ diff --git a/sys/i386/ibcs2/ibcs2_util.c b/sys/i386/ibcs2/ibcs2_util.c deleted file mode 100644 index 420d2d7967b..00000000000 --- a/sys/i386/ibcs2/ibcs2_util.c +++ /dev/null @@ -1,61 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-3-Clause - * - * Copyright (c) 1994 Christos Zoulas - * Copyright (c) 1995 Frank van der Linden - * Copyright (c) 1995 Scott Bartram - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * from: svr4_util.c,v 1.5 1995/01/22 23:44:50 christos Exp - */ - -#include - -#include -#include -#include -#include - -#include - - -const char ibcs2_emul_path[] = "/compat/ibcs2"; - -/* - * Search an alternate path before passing pathname arguments on - * to system calls. Useful for keeping a separate 'emulation tree'. - * - * If cflag is set, we check if an attempt can be made to create - * the named file, i.e. we check if the directory it should - * be in exists. - */ -int -ibcs2_emul_find(struct thread *td, char *path, enum uio_seg pathseg, - char **pbuf, int cflag) -{ - - return (kern_alternate_path(td, ibcs2_emul_path, path, pathseg, pbuf, - cflag, AT_FDCWD)); -} diff --git a/sys/i386/ibcs2/ibcs2_util.h b/sys/i386/ibcs2/ibcs2_util.h deleted file mode 100644 index 514c0563d29..00000000000 --- a/sys/i386/ibcs2/ibcs2_util.h +++ /dev/null @@ -1,73 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-3-Clause - * - * Copyright (c) 1994 Christos Zoulas - * Copyright (c) 1995 Frank van der Linden - * Copyright (c) 1995 Scott Bartram - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * from: svr4_util.h,v 1.5 1994/11/18 02:54:31 christos Exp - * from: linux_util.h,v 1.2 1995/03/05 23:23:50 fvdl Exp - * - */ - -/* - * This file is pretty much the same as Christos' svr4_util.h - * (for now). - */ - -#ifndef _IBCS2_UTIL_H_ -#define _IBCS2_UTIL_H_ - -#include -#include - -#ifdef DEBUG_IBCS2 -#define DPRINTF(a) printf a; -#else -#define DPRINTF(a) -#endif - -extern const char ibcs2_emul_path[]; - -int ibcs2_emul_find(struct thread *, char *, enum uio_seg, char **, int); - -#define CHECKALT(td, upath, pathp, i) \ - do { \ - int _error; \ - \ - _error = ibcs2_emul_find(td, upath, UIO_USERSPACE, pathp, i); \ - if (*(pathp) == NULL) \ - return (_error); \ - } while (0) - -#define CHECKALTEXIST(td, upath, pathp) CHECKALT(td, upath, pathp, 0) -#define CHECKALTCREAT(td, upath, pathp) CHECKALT(td, upath, pathp, 1) - -#ifdef SPX_HACK -int spx_open(struct thread *td); -#endif - -#endif /* !_IBCS2_UTIL_H_ */ diff --git a/sys/i386/ibcs2/ibcs2_utime.h b/sys/i386/ibcs2/ibcs2_utime.h deleted file mode 100644 index 53db767c36d..00000000000 --- a/sys/i386/ibcs2/ibcs2_utime.h +++ /dev/null @@ -1,44 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-4-Clause - * - * Copyright (c) 1995 Scott Bartram - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by Scott Bartram. - * 4. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef _IBCS2_UTIME_H -#define _IBCS2_UTIME_H - -#include - -struct ibcs2_utimbuf { - ibcs2_time_t actime; - ibcs2_time_t modtime; -}; - -#endif /* _IBCS2_UTIME_H */ diff --git a/sys/i386/ibcs2/ibcs2_utsname.h b/sys/i386/ibcs2/ibcs2_utsname.h deleted file mode 100644 index a042213d25e..00000000000 --- a/sys/i386/ibcs2/ibcs2_utsname.h +++ /dev/null @@ -1,59 +0,0 @@ -/* $NetBSD: ibcs2_utsname.h,v 1.2 1994/10/26 02:53:14 cgd Exp $ */ - -/*- - * SPDX-License-Identifier: BSD-4-Clause - * - * Copyright (c) 1994 Scott Bartram - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by Scott Bartram. - * 4. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _IBCS2_UTSNAME_H -#define _IBCS2_UTSNAME_H - -#ifndef IBCS2_UNAME_SYSNAME -#define IBCS2_UNAME_SYSNAME ostype -#endif - -#ifndef IBCS2_UNAME_RELEASE -#define IBCS2_UNAME_RELEASE "3.2" -#endif - -#ifndef IBCS2_UNAME_VERSION -#define IBCS2_UNAME_VERSION "2.0" -#endif - -struct ibcs2_utsname { - char sysname[9]; - char nodename[9]; - char release[9]; - char version[9]; - char machine[9]; -}; -#define ibcs2_utsname_len (sizeof(struct ibcs2_utsname)) - -#endif /* _IBCS2_UTSNAME_H */ diff --git a/sys/i386/ibcs2/ibcs2_xenix.c b/sys/i386/ibcs2/ibcs2_xenix.c deleted file mode 100644 index b54480073f3..00000000000 --- a/sys/i386/ibcs2/ibcs2_xenix.c +++ /dev/null @@ -1,218 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-3-Clause - * - * Copyright (c) 1994 Sean Eric Fagan - * Copyright (c) 1994 Søren Schmidt - * Copyright (c) 1995 Steven Wallace - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer - * in this position and unchanged. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include -#include -#include -#include -#include -#include -#include - - -extern struct sysent xenix_sysent[]; - -int -ibcs2_xenix(struct thread *td, struct ibcs2_xenix_args *uap) -{ - struct trapframe *tf = td->td_frame; - struct sysent *callp; - u_int code; - int error; - - code = (tf->tf_eax & 0xff00) >> 8; - callp = &xenix_sysent[code]; - - if (code < IBCS2_XENIX_MAXSYSCALL) - error = ((*callp->sy_call)(td, (void *)uap)); - else - error = ENOSYS; - return (error); -} - -int -xenix_rdchk(td, uap) - struct thread *td; - struct xenix_rdchk_args *uap; -{ - int data, error; - - DPRINTF(("IBCS2: 'xenix rdchk'\n")); - - error = kern_ioctl(td, uap->fd, FIONREAD, (caddr_t)&data); - if (error) - return (error); - td->td_retval[0] = data ? 1 : 0; - return (0); -} - -int -xenix_chsize(td, uap) - struct thread *td; - struct xenix_chsize_args *uap; -{ - struct ftruncate_args sa; - - DPRINTF(("IBCS2: 'xenix chsize'\n")); - sa.fd = uap->fd; - sa.length = uap->size; - return sys_ftruncate(td, &sa); -} - - -int -xenix_ftime(td, uap) - struct thread *td; - struct xenix_ftime_args *uap; -{ - struct timeval tv; - struct ibcs2_timeb { - unsigned long time __packed; - unsigned short millitm; - short timezone; - short dstflag; - } itb; - - DPRINTF(("IBCS2: 'xenix ftime'\n")); - microtime(&tv); - itb.time = tv.tv_sec; - itb.millitm = (tv.tv_usec / 1000); - itb.timezone = tz_minuteswest; - itb.dstflag = tz_dsttime != DST_NONE; - - return copyout((caddr_t)&itb, (caddr_t)uap->tp, - sizeof(struct ibcs2_timeb)); -} - -int -xenix_nap(struct thread *td, struct xenix_nap_args *uap) -{ - long period; - - DPRINTF(("IBCS2: 'xenix nap %d ms'\n", uap->millisec)); - period = (long)uap->millisec / (1000/hz); - if (period) - pause("nap", period); - return 0; -} - -int -xenix_utsname(struct thread *td, struct xenix_utsname_args *uap) -{ - struct ibcs2_sco_utsname { - char sysname[9]; - char nodename[9]; - char release[16]; - char kernelid[20]; - char machine[9]; - char bustype[9]; - char sysserial[10]; - unsigned short sysorigin; - unsigned short sysoem; - char numusers[9]; - unsigned short numcpu; - } ibcs2_sco_uname; - - DPRINTF(("IBCS2: 'xenix sco_utsname'\n")); - bzero(&ibcs2_sco_uname, sizeof(struct ibcs2_sco_utsname)); - strncpy(ibcs2_sco_uname.sysname, ostype, - sizeof(ibcs2_sco_uname.sysname) - 1); - getcredhostname(td->td_ucred, ibcs2_sco_uname.nodename, - sizeof(ibcs2_sco_uname.nodename) - 1); - strncpy(ibcs2_sco_uname.release, osrelease, - sizeof(ibcs2_sco_uname.release) - 1); - strncpy(ibcs2_sco_uname.kernelid, version, - sizeof(ibcs2_sco_uname.kernelid) - 1); - strncpy(ibcs2_sco_uname.machine, machine, - sizeof(ibcs2_sco_uname.machine) - 1); - strncpy(ibcs2_sco_uname.bustype, "ISA/EISA", - sizeof(ibcs2_sco_uname.bustype) - 1); - strncpy(ibcs2_sco_uname.sysserial, "no charge", - sizeof(ibcs2_sco_uname.sysserial) - 1); - strncpy(ibcs2_sco_uname.numusers, "unlim", - sizeof(ibcs2_sco_uname.numusers) - 1); - ibcs2_sco_uname.sysorigin = 0xFFFF; - ibcs2_sco_uname.sysoem = 0xFFFF; - ibcs2_sco_uname.numcpu = 1; - return copyout((caddr_t)&ibcs2_sco_uname, - (caddr_t)(void *)(intptr_t)uap->addr, - sizeof(struct ibcs2_sco_utsname)); -} - -int -xenix_scoinfo(struct thread *td, struct xenix_scoinfo_args *uap) -{ - /* scoinfo (not documented) */ - td->td_retval[0] = 0; - return 0; -} - -int -xenix_eaccess(struct thread *td, struct xenix_eaccess_args *uap) -{ - char *path; - int error, bsd_flags; - - bsd_flags = 0; - if (uap->flags & IBCS2_R_OK) - bsd_flags |= R_OK; - if (uap->flags & IBCS2_W_OK) - bsd_flags |= W_OK; - if (uap->flags & IBCS2_X_OK) - bsd_flags |= X_OK; - - CHECKALTEXIST(td, uap->path, &path); - error = kern_accessat(td, AT_FDCWD, path, UIO_SYSSPACE, - AT_EACCESS, bsd_flags); - free(path, M_TEMP); - return (error); -} diff --git a/sys/i386/ibcs2/ibcs2_xenix.h b/sys/i386/ibcs2/ibcs2_xenix.h deleted file mode 100644 index 895494d2436..00000000000 --- a/sys/i386/ibcs2/ibcs2_xenix.h +++ /dev/null @@ -1,173 +0,0 @@ -/* - * System call prototypes. - * - * DO NOT EDIT-- this file is automatically @generated. - */ - -#ifndef _IBCS2_XENIX_H_ -#define _IBCS2_XENIX_H_ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -struct proc; - -struct thread; - -#define PAD_(t) (sizeof(register_t) <= sizeof(t) ? \ - 0 : sizeof(register_t) - sizeof(t)) - -#if BYTE_ORDER == LITTLE_ENDIAN -#define PADL_(t) 0 -#define PADR_(t) PAD_(t) -#else -#define PADL_(t) PAD_(t) -#define PADR_(t) 0 -#endif - -struct xenix_rdchk_args { - char fd_l_[PADL_(int)]; int fd; char fd_r_[PADR_(int)]; -}; -struct xenix_chsize_args { - char fd_l_[PADL_(int)]; int fd; char fd_r_[PADR_(int)]; - char size_l_[PADL_(long)]; long size; char size_r_[PADR_(long)]; -}; -struct xenix_ftime_args { - char tp_l_[PADL_(struct timeb *)]; struct timeb * tp; char tp_r_[PADR_(struct timeb *)]; -}; -struct xenix_nap_args { - char millisec_l_[PADL_(int)]; int millisec; char millisec_r_[PADR_(int)]; -}; -struct xenix_scoinfo_args { - register_t dummy; -}; -struct xenix_eaccess_args { - char path_l_[PADL_(char *)]; char * path; char path_r_[PADR_(char *)]; - char flags_l_[PADL_(int)]; int flags; char flags_r_[PADR_(int)]; -}; -struct ibcs2_sigaction_args { - char sig_l_[PADL_(int)]; int sig; char sig_r_[PADR_(int)]; - char act_l_[PADL_(struct ibcs2_sigaction *)]; struct ibcs2_sigaction * act; char act_r_[PADR_(struct ibcs2_sigaction *)]; - char oact_l_[PADL_(struct ibcs2_sigaction *)]; struct ibcs2_sigaction * oact; char oact_r_[PADR_(struct ibcs2_sigaction *)]; -}; -struct ibcs2_sigprocmask_args { - char how_l_[PADL_(int)]; int how; char how_r_[PADR_(int)]; - char set_l_[PADL_(ibcs2_sigset_t *)]; ibcs2_sigset_t * set; char set_r_[PADR_(ibcs2_sigset_t *)]; - char oset_l_[PADL_(ibcs2_sigset_t *)]; ibcs2_sigset_t * oset; char oset_r_[PADR_(ibcs2_sigset_t *)]; -}; -struct ibcs2_sigpending_args { - char mask_l_[PADL_(ibcs2_sigset_t *)]; ibcs2_sigset_t * mask; char mask_r_[PADR_(ibcs2_sigset_t *)]; -}; -struct ibcs2_sigsuspend_args { - char mask_l_[PADL_(ibcs2_sigset_t *)]; ibcs2_sigset_t * mask; char mask_r_[PADR_(ibcs2_sigset_t *)]; -}; -struct ibcs2_getgroups_args { - char gidsetsize_l_[PADL_(int)]; int gidsetsize; char gidsetsize_r_[PADR_(int)]; - char gidset_l_[PADL_(ibcs2_gid_t *)]; ibcs2_gid_t * gidset; char gidset_r_[PADR_(ibcs2_gid_t *)]; -}; -struct ibcs2_setgroups_args { - char gidsetsize_l_[PADL_(int)]; int gidsetsize; char gidsetsize_r_[PADR_(int)]; - char gidset_l_[PADL_(ibcs2_gid_t *)]; ibcs2_gid_t * gidset; char gidset_r_[PADR_(ibcs2_gid_t *)]; -}; -struct ibcs2_sysconf_args { - char name_l_[PADL_(int)]; int name; char name_r_[PADR_(int)]; -}; -struct ibcs2_pathconf_args { - char path_l_[PADL_(char *)]; char * path; char path_r_[PADR_(char *)]; - char name_l_[PADL_(int)]; int name; char name_r_[PADR_(int)]; -}; -struct ibcs2_fpathconf_args { - char fd_l_[PADL_(int)]; int fd; char fd_r_[PADR_(int)]; - char name_l_[PADL_(int)]; int name; char name_r_[PADR_(int)]; -}; -struct ibcs2_rename_args { - char from_l_[PADL_(char *)]; char * from; char from_r_[PADR_(char *)]; - char to_l_[PADL_(char *)]; char * to; char to_r_[PADR_(char *)]; -}; -struct xenix_utsname_args { - char addr_l_[PADL_(long)]; long addr; char addr_r_[PADR_(long)]; -}; -int xenix_rdchk(struct thread *, struct xenix_rdchk_args *); -int xenix_chsize(struct thread *, struct xenix_chsize_args *); -int xenix_ftime(struct thread *, struct xenix_ftime_args *); -int xenix_nap(struct thread *, struct xenix_nap_args *); -int xenix_scoinfo(struct thread *, struct xenix_scoinfo_args *); -int xenix_eaccess(struct thread *, struct xenix_eaccess_args *); -int ibcs2_sigaction(struct thread *, struct ibcs2_sigaction_args *); -int ibcs2_sigprocmask(struct thread *, struct ibcs2_sigprocmask_args *); -int ibcs2_sigpending(struct thread *, struct ibcs2_sigpending_args *); -int ibcs2_sigsuspend(struct thread *, struct ibcs2_sigsuspend_args *); -int ibcs2_getgroups(struct thread *, struct ibcs2_getgroups_args *); -int ibcs2_setgroups(struct thread *, struct ibcs2_setgroups_args *); -int ibcs2_sysconf(struct thread *, struct ibcs2_sysconf_args *); -int ibcs2_pathconf(struct thread *, struct ibcs2_pathconf_args *); -int ibcs2_fpathconf(struct thread *, struct ibcs2_fpathconf_args *); -int ibcs2_rename(struct thread *, struct ibcs2_rename_args *); -int xenix_utsname(struct thread *, struct xenix_utsname_args *); - -#ifdef COMPAT_43 - - -#endif /* COMPAT_43 */ - - -#ifdef COMPAT_FREEBSD4 - - -#endif /* COMPAT_FREEBSD4 */ - - -#ifdef COMPAT_FREEBSD6 - - -#endif /* COMPAT_FREEBSD6 */ - - -#ifdef COMPAT_FREEBSD7 - - -#endif /* COMPAT_FREEBSD7 */ - - -#ifdef COMPAT_FREEBSD10 - - -#endif /* COMPAT_FREEBSD10 */ - - -#ifdef COMPAT_FREEBSD11 - - -#endif /* COMPAT_FREEBSD11 */ - -#define IBCS2_XENIX_AUE_xenix_rdchk AUE_NULL -#define IBCS2_XENIX_AUE_xenix_chsize AUE_FTRUNCATE -#define IBCS2_XENIX_AUE_xenix_ftime AUE_NULL -#define IBCS2_XENIX_AUE_xenix_nap AUE_NULL -#define IBCS2_XENIX_AUE_xenix_scoinfo AUE_NULL -#define IBCS2_XENIX_AUE_xenix_eaccess AUE_EACCESS -#define IBCS2_XENIX_AUE_ibcs2_sigaction AUE_NULL -#define IBCS2_XENIX_AUE_ibcs2_sigprocmask AUE_NULL -#define IBCS2_XENIX_AUE_ibcs2_sigpending AUE_NULL -#define IBCS2_XENIX_AUE_ibcs2_sigsuspend AUE_NULL -#define IBCS2_XENIX_AUE_ibcs2_getgroups AUE_GETGROUPS -#define IBCS2_XENIX_AUE_ibcs2_setgroups AUE_SETGROUPS -#define IBCS2_XENIX_AUE_ibcs2_sysconf AUE_NULL -#define IBCS2_XENIX_AUE_ibcs2_pathconf AUE_PATHCONF -#define IBCS2_XENIX_AUE_ibcs2_fpathconf AUE_FPATHCONF -#define IBCS2_XENIX_AUE_ibcs2_rename AUE_RENAME -#define IBCS2_XENIX_AUE_xenix_utsname AUE_NULL - -#undef PAD_ -#undef PADL_ -#undef PADR_ - -#endif /* !_IBCS2_XENIX_H_ */ diff --git a/sys/i386/ibcs2/ibcs2_xenix_syscall.h b/sys/i386/ibcs2/ibcs2_xenix_syscall.h deleted file mode 100644 index 3c5b5b3e7fe..00000000000 --- a/sys/i386/ibcs2/ibcs2_xenix_syscall.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * System call numbers. - * - * DO NOT EDIT-- this file is automatically @generated. - */ - -#define IBCS2_XENIX_xenix_rdchk 7 -#define IBCS2_XENIX_xenix_chsize 10 -#define IBCS2_XENIX_xenix_ftime 11 -#define IBCS2_XENIX_xenix_nap 12 -#define IBCS2_XENIX_xenix_scoinfo 21 -#define IBCS2_XENIX_select 36 -#define IBCS2_XENIX_xenix_eaccess 37 -#define IBCS2_XENIX_ibcs2_sigaction 39 -#define IBCS2_XENIX_ibcs2_sigprocmask 40 -#define IBCS2_XENIX_ibcs2_sigpending 41 -#define IBCS2_XENIX_ibcs2_sigsuspend 42 -#define IBCS2_XENIX_ibcs2_getgroups 43 -#define IBCS2_XENIX_ibcs2_setgroups 44 -#define IBCS2_XENIX_ibcs2_sysconf 45 -#define IBCS2_XENIX_ibcs2_pathconf 46 -#define IBCS2_XENIX_ibcs2_fpathconf 47 -#define IBCS2_XENIX_ibcs2_rename 48 -#define IBCS2_XENIX_xenix_utsname 50 -#define IBCS2_XENIX_getitimer 55 -#define IBCS2_XENIX_setitimer 56 -#define IBCS2_XENIX_MAXSYSCALL 57 diff --git a/sys/i386/ibcs2/ibcs2_xenix_sysent.c b/sys/i386/ibcs2/ibcs2_xenix_sysent.c deleted file mode 100644 index dda44e93337..00000000000 --- a/sys/i386/ibcs2/ibcs2_xenix_sysent.c +++ /dev/null @@ -1,75 +0,0 @@ -/* - * System call switch table. - * - * DO NOT EDIT-- this file is automatically @generated. - */ - -#include -#include -#include -#include -#include -#include - -#define AS(name) (sizeof(struct name) / sizeof(register_t)) - -/* The casts are bogus but will do for now. */ -struct sysent xenix_sysent[] = { - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 0 = nosys */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 1 = xenix_xlocking */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 2 = xenix_creatsem */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 3 = xenix_opensem */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 4 = xenix_sigsem */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 5 = xenix_waitsem */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 6 = xenix_nbwaitsem */ - { AS(xenix_rdchk_args), (sy_call_t *)xenix_rdchk, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 7 = xenix_rdchk */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 8 = nosys */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 9 = nosys */ - { AS(xenix_chsize_args), (sy_call_t *)xenix_chsize, AUE_FTRUNCATE, NULL, 0, 0, 0, SY_THR_STATIC }, /* 10 = xenix_chsize */ - { AS(xenix_ftime_args), (sy_call_t *)xenix_ftime, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 11 = xenix_ftime */ - { AS(xenix_nap_args), (sy_call_t *)xenix_nap, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 12 = xenix_nap */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 13 = xenix_sdget */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 14 = xenix_sdfree */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 15 = xenix_sdenter */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 16 = xenix_sdleave */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 17 = xenix_sdgetv */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 18 = xenix_sdwaitv */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 19 = nosys */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 20 = nosys */ - { 0, (sy_call_t *)xenix_scoinfo, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 21 = xenix_scoinfo */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 22 = nosys */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 23 = nosys */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 24 = nosys */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 25 = nosys */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 26 = nosys */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 27 = nosys */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 28 = nosys */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 29 = nosys */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 30 = nosys */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 31 = nosys */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 32 = xenix_proctl */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 33 = xenix_execseg */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 34 = xenix_unexecseg */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 35 = nosys */ - { AS(select_args), (sy_call_t *)sys_select, AUE_SELECT, NULL, 0, 0, 0, SY_THR_STATIC }, /* 36 = select */ - { AS(xenix_eaccess_args), (sy_call_t *)xenix_eaccess, AUE_EACCESS, NULL, 0, 0, 0, SY_THR_STATIC }, /* 37 = xenix_eaccess */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 38 = xenix_paccess */ - { AS(ibcs2_sigaction_args), (sy_call_t *)ibcs2_sigaction, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 39 = ibcs2_sigaction */ - { AS(ibcs2_sigprocmask_args), (sy_call_t *)ibcs2_sigprocmask, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 40 = ibcs2_sigprocmask */ - { AS(ibcs2_sigpending_args), (sy_call_t *)ibcs2_sigpending, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 41 = ibcs2_sigpending */ - { AS(ibcs2_sigsuspend_args), (sy_call_t *)ibcs2_sigsuspend, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 42 = ibcs2_sigsuspend */ - { AS(ibcs2_getgroups_args), (sy_call_t *)ibcs2_getgroups, AUE_GETGROUPS, NULL, 0, 0, 0, SY_THR_STATIC }, /* 43 = ibcs2_getgroups */ - { AS(ibcs2_setgroups_args), (sy_call_t *)ibcs2_setgroups, AUE_SETGROUPS, NULL, 0, 0, 0, SY_THR_STATIC }, /* 44 = ibcs2_setgroups */ - { AS(ibcs2_sysconf_args), (sy_call_t *)ibcs2_sysconf, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 45 = ibcs2_sysconf */ - { AS(ibcs2_pathconf_args), (sy_call_t *)ibcs2_pathconf, AUE_PATHCONF, NULL, 0, 0, 0, SY_THR_STATIC }, /* 46 = ibcs2_pathconf */ - { AS(ibcs2_fpathconf_args), (sy_call_t *)ibcs2_fpathconf, AUE_FPATHCONF, NULL, 0, 0, 0, SY_THR_STATIC }, /* 47 = ibcs2_fpathconf */ - { AS(ibcs2_rename_args), (sy_call_t *)ibcs2_rename, AUE_RENAME, NULL, 0, 0, 0, SY_THR_STATIC }, /* 48 = ibcs2_rename */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 49 = nosys */ - { AS(xenix_utsname_args), (sy_call_t *)xenix_utsname, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC }, /* 50 = xenix_utsname */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 51 = nosys */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 52 = nosys */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 53 = nosys */ - { 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT }, /* 54 = nosys */ - { AS(getitimer_args), (sy_call_t *)sys_getitimer, AUE_GETITIMER, NULL, 0, 0, 0, SY_THR_STATIC }, /* 55 = getitimer */ - { AS(setitimer_args), (sy_call_t *)sys_setitimer, AUE_SETITIMER, NULL, 0, 0, 0, SY_THR_STATIC }, /* 56 = setitimer */ -}; diff --git a/sys/i386/ibcs2/imgact_coff.c b/sys/i386/ibcs2/imgact_coff.c deleted file mode 100644 index 58fd79804ed..00000000000 --- a/sys/i386/ibcs2/imgact_coff.c +++ /dev/null @@ -1,494 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-3-Clause - * - * Copyright (c) 1994 Sean Eric Fagan - * Copyright (c) 1994 Søren Schmidt - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer - * in this position and unchanged. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include -#include - -MODULE_DEPEND(coff, ibcs2, 1, 1, 1); - -extern struct sysentvec ibcs2_svr3_sysvec; - -static int coff_load_file(struct thread *td, char *name); -static int exec_coff_imgact(struct image_params *imgp); - -static int load_coff_section(struct vmspace *vmspace, struct vnode *vp, vm_offset_t offset, caddr_t vmaddr, size_t memsz, size_t filsz, vm_prot_t prot); - -static int -load_coff_section(struct vmspace *vmspace, struct vnode *vp, vm_offset_t offset, - caddr_t vmaddr, size_t memsz, size_t filsz, vm_prot_t prot) -{ - size_t map_len; - vm_offset_t map_offset; - vm_offset_t map_addr; - int error; - unsigned char *data_buf = NULL; - size_t copy_len; - - map_offset = trunc_page(offset); - map_addr = trunc_page((vm_offset_t)vmaddr); - - if (memsz > filsz) { - /* - * We have the stupid situation that - * the section is longer than it is on file, - * which means it has zero-filled areas, and - * we have to work for it. Stupid iBCS! - */ - map_len = trunc_page(offset + filsz) - trunc_page(map_offset); - } else { - /* - * The only stuff we care about is on disk, and we - * don't care if we map in more than is really there. - */ - map_len = round_page(offset + filsz) - trunc_page(map_offset); - } - - DPRINTF(("%s(%d): vm_mmap(&vmspace->vm_map, &0x%08jx, 0x%x, 0x%x, " - "VM_PROT_ALL, MAP_PRIVATE | MAP_FIXED, OBJT_VNODE, vp, 0x%x)\n", - __FILE__, __LINE__, (uintmax_t)map_addr, map_len, prot, - map_offset)); - - if ((error = vm_mmap(&vmspace->vm_map, - &map_addr, - map_len, - prot, - VM_PROT_ALL, - MAP_PRIVATE | MAP_FIXED, - OBJT_VNODE, - vp, - map_offset)) != 0) - return error; - - if (memsz == filsz) { - /* We're done! */ - return 0; - } - - /* - * Now we have screwball stuff, to accomodate stupid COFF. - * We have to map the remaining bit of the file into the kernel's - * memory map, allocate some anonymous memory, copy that last - * bit into it, and then we're done. *sigh* - * For clean-up reasons, we actally map in the file last. - */ - - copy_len = (offset + filsz) - trunc_page(offset + filsz); - map_addr = trunc_page((vm_offset_t)vmaddr + filsz); - map_len = round_page((vm_offset_t)vmaddr + memsz) - map_addr; - - DPRINTF(("%s(%d): vm_map_find(&vmspace->vm_map, NULL, 0, &0x%08jx,0x%x, VMFS_NO_SPACE, VM_PROT_ALL, VM_PROT_ALL, 0)\n", __FILE__, __LINE__, (uintmax_t)map_addr, map_len)); - - if (map_len != 0) { - error = vm_map_find(&vmspace->vm_map, NULL, 0, &map_addr, - map_len, 0, VMFS_NO_SPACE, VM_PROT_ALL, VM_PROT_ALL, 0); - if (error) - return (vm_mmap_to_errno(error)); - } - - if ((error = vm_mmap(exec_map, - (vm_offset_t *) &data_buf, - PAGE_SIZE, - VM_PROT_READ, - VM_PROT_READ, - 0, - OBJT_VNODE, - vp, - trunc_page(offset + filsz))) != 0) - return error; - - error = copyout(data_buf, (caddr_t) map_addr, copy_len); - - kmap_free_wakeup(exec_map, (vm_offset_t)data_buf, PAGE_SIZE); - - return error; -} - -static int -coff_load_file(struct thread *td, char *name) -{ - struct proc *p = td->td_proc; - struct vmspace *vmspace = p->p_vmspace; - int error; - struct nameidata nd; - struct vnode *vp; - struct vattr attr; - struct filehdr *fhdr; - struct aouthdr *ahdr; - struct scnhdr *scns; - char *ptr = NULL; - int nscns; - unsigned long text_offset = 0, text_address = 0, text_size = 0; - unsigned long data_offset = 0, data_address = 0, data_size = 0; - unsigned long bss_size = 0; - int i, writecount; - - NDINIT(&nd, LOOKUP, ISOPEN | LOCKLEAF | FOLLOW | SAVENAME, - UIO_SYSSPACE, name, td); - - error = namei(&nd); - if (error) - return error; - - vp = nd.ni_vp; - if (vp == NULL) - return ENOEXEC; - - error = VOP_GET_WRITECOUNT(vp, &writecount); - if (error != 0) - goto fail; - if (writecount != 0) { - error = ETXTBSY; - goto fail; - } - - if ((error = VOP_GETATTR(vp, &attr, td->td_ucred)) != 0) - goto fail; - - if ((vp->v_mount->mnt_flag & MNT_NOEXEC) - || ((attr.va_mode & 0111) == 0) - || (attr.va_type != VREG)) - goto fail; - - if (attr.va_size == 0) { - error = ENOEXEC; - goto fail; - } - - if ((error = VOP_ACCESS(vp, VEXEC, td->td_ucred, td)) != 0) - goto fail; - - if ((error = VOP_OPEN(vp, FREAD, td->td_ucred, td, NULL)) != 0) - goto fail; - - /* - * Lose the lock on the vnode. It's no longer needed, and must not - * exist for the pagefault paging to work below. - */ - VOP_UNLOCK(vp, 0); - - if ((error = vm_mmap(exec_map, - (vm_offset_t *) &ptr, - PAGE_SIZE, - VM_PROT_READ, - VM_PROT_READ, - 0, - OBJT_VNODE, - vp, - 0)) != 0) - goto unlocked_fail; - - fhdr = (struct filehdr *)ptr; - - if (fhdr->f_magic != I386_COFF) { - error = ENOEXEC; - goto dealloc_and_fail; - } - - nscns = fhdr->f_nscns; - - if ((nscns * sizeof(struct scnhdr)) > PAGE_SIZE) { - /* - * XXX -- just fail. I'm so lazy. - */ - error = ENOEXEC; - goto dealloc_and_fail; - } - - ahdr = (struct aouthdr*)(ptr + sizeof(struct filehdr)); - - scns = (struct scnhdr*)(ptr + sizeof(struct filehdr) - + sizeof(struct aouthdr)); - - for (i = 0; i < nscns; i++) { - if (scns[i].s_flags & STYP_NOLOAD) - continue; - else if (scns[i].s_flags & STYP_TEXT) { - text_address = scns[i].s_vaddr; - text_size = scns[i].s_size; - text_offset = scns[i].s_scnptr; - } - else if (scns[i].s_flags & STYP_DATA) { - data_address = scns[i].s_vaddr; - data_size = scns[i].s_size; - data_offset = scns[i].s_scnptr; - } else if (scns[i].s_flags & STYP_BSS) { - bss_size = scns[i].s_size; - } - } - - if ((error = load_coff_section(vmspace, vp, text_offset, - (caddr_t)(void *)(uintptr_t)text_address, - text_size, text_size, - VM_PROT_READ | VM_PROT_EXECUTE)) != 0) { - goto dealloc_and_fail; - } - if ((error = load_coff_section(vmspace, vp, data_offset, - (caddr_t)(void *)(uintptr_t)data_address, - data_size + bss_size, data_size, - VM_PROT_ALL)) != 0) { - goto dealloc_and_fail; - } - - error = 0; - - dealloc_and_fail: - kmap_free_wakeup(exec_map, (vm_offset_t)ptr, PAGE_SIZE); - fail: - VOP_UNLOCK(vp, 0); - unlocked_fail: - NDFREE(&nd, NDF_ONLY_PNBUF); - vrele(nd.ni_vp); - return error; -} - -static int -exec_coff_imgact(imgp) - struct image_params *imgp; -{ - const struct filehdr *fhdr = (const struct filehdr*)imgp->image_header; - const struct aouthdr *ahdr; - const struct scnhdr *scns; - int i; - struct vmspace *vmspace; - int nscns; - int error; - unsigned long text_offset = 0, text_address = 0, text_size = 0; - unsigned long data_offset = 0, data_address = 0, data_size = 0; - unsigned long bss_size = 0; - vm_offset_t hole; - - if (fhdr->f_magic != I386_COFF || - !(fhdr->f_flags & F_EXEC)) { - - DPRINTF(("%s(%d): return -1\n", __FILE__, __LINE__)); - return -1; - } - - nscns = fhdr->f_nscns; - if ((nscns * sizeof(struct scnhdr)) > PAGE_SIZE) { - /* - * For now, return an error -- need to be able to - * read in all of the section structures. - */ - - DPRINTF(("%s(%d): return -1\n", __FILE__, __LINE__)); - return -1; - } - - ahdr = (const struct aouthdr*) - ((const char*)(imgp->image_header) + sizeof(struct filehdr)); - imgp->entry_addr = ahdr->entry; - - scns = (const struct scnhdr*) - ((const char*)(imgp->image_header) + sizeof(struct filehdr) + - sizeof(struct aouthdr)); - - VOP_UNLOCK(imgp->vp, 0); - - error = exec_new_vmspace(imgp, &ibcs2_svr3_sysvec); - if (error) - goto fail; - vmspace = imgp->proc->p_vmspace; - - for (i = 0; i < nscns; i++) { - - DPRINTF(("i = %d, s_name = %s, s_vaddr = %08lx, " - "s_scnptr = %ld s_size = %lx\n", i, scns[i].s_name, - scns[i].s_vaddr, scns[i].s_scnptr, scns[i].s_size)); - if (scns[i].s_flags & STYP_NOLOAD) { - /* - * A section that is not loaded, for whatever - * reason. It takes precedance over other flag - * bits... - */ - continue; - } else if (scns[i].s_flags & STYP_TEXT) { - text_address = scns[i].s_vaddr; - text_size = scns[i].s_size; - text_offset = scns[i].s_scnptr; - } else if (scns[i].s_flags & STYP_DATA) { - /* .data section */ - data_address = scns[i].s_vaddr; - data_size = scns[i].s_size; - data_offset = scns[i].s_scnptr; - } else if (scns[i].s_flags & STYP_BSS) { - /* .bss section */ - bss_size = scns[i].s_size; - } else if (scns[i].s_flags & STYP_LIB) { - char *buf = NULL; - int foff = trunc_page(scns[i].s_scnptr); - int off = scns[i].s_scnptr - foff; - int len = round_page(scns[i].s_size + PAGE_SIZE); - int j; - - if ((error = vm_mmap(exec_map, - (vm_offset_t *) &buf, - len, - VM_PROT_READ, - VM_PROT_READ, - MAP_SHARED, - OBJT_VNODE, - imgp->vp, - foff)) != 0) { - error = ENOEXEC; - goto fail; - } - if(scns[i].s_size) { - char *libbuf; - int emul_path_len = strlen(ibcs2_emul_path); - - libbuf = malloc(MAXPATHLEN + emul_path_len, - M_TEMP, M_WAITOK); - strcpy(libbuf, ibcs2_emul_path); - - for (j = off; j < scns[i].s_size + off;) { - long stroff, nextoff; - char *libname; - - nextoff = 4 * *(long *)(buf + j); - stroff = 4 * *(long *)(buf + j + sizeof(long)); - - libname = buf + j + stroff; - j += nextoff; - - DPRINTF(("%s(%d): shared library %s\n", - __FILE__, __LINE__, libname)); - strlcpy(&libbuf[emul_path_len], libname, MAXPATHLEN); - error = coff_load_file( - FIRST_THREAD_IN_PROC(imgp->proc), libbuf); - if (error) - error = coff_load_file( - FIRST_THREAD_IN_PROC(imgp->proc), - libname); - if (error) { - printf( - "error %d loading coff shared library %s\n", - error, libname); - break; - } - } - free(libbuf, M_TEMP); - } - kmap_free_wakeup(exec_map, (vm_offset_t)buf, len); - if (error) - goto fail; - } - } - /* - * Map in .text now - */ - - DPRINTF(("%s(%d): load_coff_section(vmspace, " - "imgp->vp, %08lx, %08lx, 0x%lx, 0x%lx, 0x%x)\n", - __FILE__, __LINE__, text_offset, text_address, - text_size, text_size, VM_PROT_READ | VM_PROT_EXECUTE)); - if ((error = load_coff_section(vmspace, imgp->vp, - text_offset, - (caddr_t)(void *)(uintptr_t)text_address, - text_size, text_size, - VM_PROT_READ | VM_PROT_EXECUTE)) != 0) { - DPRINTF(("%s(%d): error = %d\n", __FILE__, __LINE__, error)); - goto fail; - } - /* - * Map in .data and .bss now - */ - - - DPRINTF(("%s(%d): load_coff_section(vmspace, " - "imgp->vp, 0x%08lx, 0x%08lx, 0x%lx, 0x%lx, 0x%x)\n", - __FILE__, __LINE__, data_offset, data_address, - data_size + bss_size, data_size, VM_PROT_ALL)); - if ((error = load_coff_section(vmspace, imgp->vp, - data_offset, - (caddr_t)(void *)(uintptr_t)data_address, - data_size + bss_size, data_size, - VM_PROT_ALL)) != 0) { - - DPRINTF(("%s(%d): error = %d\n", __FILE__, __LINE__, error)); - goto fail; - } - - imgp->interpreted = 0; - imgp->proc->p_sysent = &ibcs2_svr3_sysvec; - - vmspace->vm_tsize = round_page(text_size) >> PAGE_SHIFT; - vmspace->vm_dsize = round_page(data_size + bss_size) >> PAGE_SHIFT; - vmspace->vm_taddr = (caddr_t)(void *)(uintptr_t)text_address; - vmspace->vm_daddr = (caddr_t)(void *)(uintptr_t)data_address; - - hole = trunc_page((vm_offset_t)vmspace->vm_daddr + - ctob(vmspace->vm_dsize)); - - DPRINTF(("%s(%d): vm_map_find(&vmspace->vm_map, NULL, 0, &0x%jx, PAGE_SIZE, FALSE, VM_PROT_ALL, VM_PROT_ALL, 0)\n", - __FILE__, __LINE__, (uintmax_t)hole)); - DPRINTF(("imgact: error = %d\n", error)); - - vm_map_find(&vmspace->vm_map, NULL, 0, - (vm_offset_t *)&hole, PAGE_SIZE, 0, VMFS_NO_SPACE, - VM_PROT_ALL, VM_PROT_ALL, 0); - DPRINTF(("IBCS2: start vm_dsize = 0x%x, vm_daddr = 0x%p end = 0x%p\n", - ctob(vmspace->vm_dsize), vmspace->vm_daddr, - ctob(vmspace->vm_dsize) + vmspace->vm_daddr )); - DPRINTF(("%s(%d): returning %d!\n", __FILE__, __LINE__, error)); - -fail: - vn_lock(imgp->vp, LK_EXCLUSIVE | LK_RETRY); - - return (error); -} - -/* - * Tell kern_execve.c about it, with a little help from the linker. - */ -static struct execsw coff_execsw = { exec_coff_imgact, "coff" }; -EXEC_SET(coff, coff_execsw); diff --git a/sys/i386/ibcs2/syscalls.conf b/sys/i386/ibcs2/syscalls.conf deleted file mode 100644 index cbfbec42fce..00000000000 --- a/sys/i386/ibcs2/syscalls.conf +++ /dev/null @@ -1,10 +0,0 @@ -sysnames="/dev/null" -sysproto="ibcs2_proto.h" -sysproto_h=_IBCS2_SYSPROTO_H_ -syshdr="ibcs2_syscall.h" -sysmk="/dev/null" -syssw="ibcs2_sysent.c" -syscallprefix="IBCS2_SYS_" -switchname="ibcs2_sysent" -namesname="ibcs2_syscallnames" -systrace="/dev/null" diff --git a/sys/i386/ibcs2/syscalls.isc b/sys/i386/ibcs2/syscalls.isc deleted file mode 100644 index 5d48250c2ef..00000000000 --- a/sys/i386/ibcs2/syscalls.isc +++ /dev/null @@ -1,37 +0,0 @@ - -#include -#include -#include -#include -#include -#include -#include - -0 AUE_NULL UNIMPL nosys -1 AUE_NULL UNIMPL isc_setostype -2 AUE_RENAME NOPROTO { int ibcs2_rename(char *from, char *to); } -3 AUE_NULL NOPROTO { int ibcs2_sigaction(int sig, \ - struct ibcs2_sigaction *act, \ - struct ibcs2_sigaction *oact); } -4 AUE_NULL NOPROTO { int ibcs2_sigprocmask(int how, \ - ibcs2_sigset_t *set, \ - ibcs2_sigset_t *oset); } -5 AUE_NULL NOPROTO { int ibcs2_sigpending(ibcs2_sigset_t *mask); } -6 AUE_GETGROUPS NOPROTO { int getgroups(u_int gidsetsize, \ - gid_t *gidset); } -7 AUE_SETGROUPS NOPROTO { int setgroups(u_int gidsetsize, \ - gid_t *gidset); } -8 AUE_PATHCONF NOPROTO { int ibcs2_pathconf(char *path, int name); } -9 AUE_FPATHCONF NOPROTO { int ibcs2_fpathconf(int fd, int name); } -10 AUE_NULL UNIMPL nosys -11 AUE_WAIT4 NOPROTO { int ibcs2_wait(int a1, int a2, int a3); } -12 AUE_SETSID NOPROTO { int setsid(void); } -13 AUE_GETPID NOPROTO { pid_t getpid(void); } -14 AUE_NULL UNIMPL isc_adduser -15 AUE_NULL UNIMPL isc_setuser -16 AUE_NULL NOPROTO { int ibcs2_sysconf(int name); } -17 AUE_NULL NOPROTO { int ibcs2_sigsuspend(ibcs2_sigset_t *mask); } -18 AUE_SYMLINK NOPROTO { int ibcs2_symlink(char *path, char *link); } -19 AUE_READLINK NOPROTO { int ibcs2_readlink(char *path, char *buf, \ - int count); } -20 AUE_NULL UNIMPL isc_getmajor diff --git a/sys/i386/ibcs2/syscalls.isc.conf b/sys/i386/ibcs2/syscalls.isc.conf deleted file mode 100644 index 3958e2199f1..00000000000 --- a/sys/i386/ibcs2/syscalls.isc.conf +++ /dev/null @@ -1,11 +0,0 @@ -sysnames="/dev/null" -#sysproto="ibcs2_isc.h" -sysproto="/dev/null" -sysproto_h=_IBCS2_ISC_H_ -syshdr="ibcs2_isc_syscall.h" -sysmk="/dev/null" -syssw="ibcs2_isc_sysent.c" -syscallprefix="IBCS2_ISC_" -switchname="isc_sysent" -namesname="isc_syscallnames" -systrace="/dev/null" diff --git a/sys/i386/ibcs2/syscalls.master b/sys/i386/ibcs2/syscalls.master deleted file mode 100644 index 4325eaeebe0..00000000000 --- a/sys/i386/ibcs2/syscalls.master +++ /dev/null @@ -1,204 +0,0 @@ - -; @(#)syscalls.master 8.1 (Berkeley) 7/19/93 -; System call name/number master file (or rather, slave, from IBCS2). -; Processed to created ibcs2_sysent.c, ibcs2_syscalls.c and ibcs2_syscall.h. - -; Columns: number audit type nargs name alt{name,tag,rtyp}/comments -; number system call number, must be in order -; audit the audit event associated with the system call -; A value of AUE_NULL means no auditing, but it also means that -; there is no audit event for the call at this time. For the -; case where the event exists, but we don't want auditing, the -; event should be #defined to AUE_NULL in audit_kevents.h. -; type one of STD, OBSOL, UNIMPL, COMPAT -; name pseudo-prototype of syscall routine -; If one of the following alts is different, then all appear: -; altname name of system call if different -; alttag name of args struct tag if different from [o]`name'"_args" -; altrtyp return type if not int (bogus - syscalls always return int) -; for UNIMPL/OBSOL, name continues with comments - -; types: -; STD always included -; COMPAT included on COMPAT #ifdef -; OBSOL obsolete, not included in system, only specifies name -; UNIMPL not implemented, placeholder only - -#include -#include -#include -#include -#include -#include - -; #ifdef's, etc. may be included, and are copied to the output files. - -0 AUE_NULL NOPROTO { int nosys(void); } syscall nosys_args int -1 AUE_EXIT NOPROTO { void sys_exit(int rval); } exit \ - sys_exit_args void -2 AUE_FORK NOPROTO { int fork(void); } -3 AUE_NULL STD { int ibcs2_read(int fd, char *buf, \ - u_int nbytes); } -4 AUE_NULL NOPROTO { int write(int fd, char *buf, \ - u_int nbytes); } -5 AUE_OPEN_RWTC STD { int ibcs2_open(char *path, int flags, \ - int mode); } -6 AUE_CLOSE NOPROTO { int close(int fd); } -7 AUE_WAIT4 STD { int ibcs2_wait(int a1, int a2, int a3); } -8 AUE_CREAT STD { int ibcs2_creat(char *path, int mode); } -9 AUE_LINK NOPROTO { int link(char *path, char *link); } -10 AUE_UNLINK STD { int ibcs2_unlink(char *path); } -11 AUE_EXECVE STD { int ibcs2_execv(char *path, char **argp); } -12 AUE_CHDIR STD { int ibcs2_chdir(char *path); } -13 AUE_NULL STD { int ibcs2_time(ibcs2_time_t *tp); } -14 AUE_MKNOD STD { int ibcs2_mknod(char* path, int mode, \ - int dev); } -15 AUE_CHMOD STD { int ibcs2_chmod(char *path, int mode); } -16 AUE_CHOWN STD { int ibcs2_chown(char *path, int uid, \ - int gid); } -17 AUE_NULL NOPROTO { caddr_t break(caddr_t nsize); } -18 AUE_STAT STD { int ibcs2_stat(char* path, \ - struct ibcs2_stat *st); } -19 AUE_LSEEK STD { long ibcs2_lseek(int fd, long offset, \ - int whence); } -20 AUE_NULL NOPROTO { pid_t getpid(void); } -21 AUE_MOUNT STD { int ibcs2_mount(char *special, char *dir, \ - int flags, int fstype, char *data, \ - int len); } -22 AUE_UMOUNT STD { int ibcs2_umount(char *name); } -23 AUE_SETUID STD { int ibcs2_setuid(int uid); } -24 AUE_GETUID NOPROTO { uid_t getuid(void); } -25 AUE_SETTIMEOFDAY STD { int ibcs2_stime(long *timep); } -26 AUE_PTRACE NOPROTO { int ptrace(int req, pid_t pid, \ - caddr_t addr, int data); } -27 AUE_NULL STD { int ibcs2_alarm(unsigned sec); } -28 AUE_FSTAT STD { int ibcs2_fstat(int fd, \ - struct ibcs2_stat *st); } -29 AUE_NULL STD { int ibcs2_pause(void); } -30 AUE_NULL STD { int ibcs2_utime(char *path, \ - struct ibcs2_utimbuf *buf); } -31 AUE_NULL UNIMPL ibcs2_stty -32 AUE_NULL UNIMPL ibcs2_gtty -33 AUE_ACCESS STD { int ibcs2_access(char *path, int amode); } -34 AUE_NICE STD { int ibcs2_nice(int incr); } -35 AUE_STATFS STD { int ibcs2_statfs(char *path, \ - struct ibcs2_statfs *buf, int len, \ - int fstype); } -36 AUE_NULL NOPROTO { int sync(void); } -37 AUE_KILL STD { int ibcs2_kill(int pid, int signo); } -38 AUE_FSTATFS STD { int ibcs2_fstatfs(int fd, \ - struct ibcs2_statfs *buf, int len, \ - int fstype); } -39 AUE_NULL STD { int ibcs2_pgrpsys(int type, caddr_t dummy, \ - int pid, int pgid); } -40 AUE_NULL STD { int ibcs2_xenix(int a1, int a2, int a3, \ - int a4, int a5); } -41 AUE_NULL NOPROTO { int dup(u_int fd); } -42 AUE_PIPE NOPROTO { int pipe(void); } -43 AUE_NULL STD { int ibcs2_times(struct tms *tp); } -44 AUE_PROFILE NOPROTO { int profil(caddr_t samples, u_int size, \ - u_int offset, u_int scale); } -45 AUE_NULL STD { int ibcs2_plock(int cmd); } -46 AUE_SETGID STD { int ibcs2_setgid(int gid); } -47 AUE_GETGID NOPROTO { gid_t getgid(void); } -48 AUE_NULL STD { int ibcs2_sigsys(int sig, ibcs2_sig_t fp); } -49 AUE_MSGSYS STD { int ibcs2_msgsys(int which, int a2, \ - int a3, int a4, int a5, int a6); } -50 AUE_NULL STD { int ibcs2_sysi86(int cmd, int *arg); } -51 AUE_NULL UNIMPL ibcs2_acct -52 AUE_SHMSYS STD { int ibcs2_shmsys(int which, int a2, \ - int a3, int a4); } -53 AUE_SEMSYS STD { int ibcs2_semsys(int which, int a2, \ - int a3, int a4, int a5); } -54 AUE_IOCTL STD { int ibcs2_ioctl(int fd, int cmd, \ - caddr_t data); } -55 AUE_NULL STD { int ibcs2_uadmin(int cmd, int func, \ - caddr_t data); } -56 AUE_NULL UNIMPL nosys -57 AUE_NULL STD { int ibcs2_utssys(int a1, int a2, \ - int flag); } -58 AUE_FSYNC NOPROTO { int fsync(int fd); } -59 AUE_EXECVE STD { int ibcs2_execve(char *path, char **argp, \ - char **envp); } -60 AUE_UMASK NOPROTO { int umask(int newmask); } -61 AUE_CHROOT NOPROTO { int chroot(char *path); } -62 AUE_FCNTL STD { int ibcs2_fcntl(int fd, int cmd, \ - char *arg); } -63 AUE_NULL STD { long ibcs2_ulimit(int cmd, int newlimit); } -64 AUE_NULL UNIMPL reserved for unix/pc -65 AUE_NULL UNIMPL reserved for unix/pc -66 AUE_NULL UNIMPL reserved for unix/pc -67 AUE_NULL UNIMPL reserved for unix/pc -68 AUE_NULL UNIMPL reserved for unix/pc -69 AUE_NULL UNIMPL reserved for unix/pc -70 AUE_NULL OBSOL rfs_advfs -71 AUE_NULL OBSOL rfs_unadvfs -72 AUE_NULL OBSOL rfs_rmount -73 AUE_NULL OBSOL rfs_rumount -74 AUE_NULL OBSOL rfs_rfstart -75 AUE_NULL OBSOL rfs_sigret -76 AUE_NULL OBSOL rfs_rdebug -77 AUE_NULL OBSOL rfs_rfstop -78 AUE_NULL UNIMPL rfs_rfsys -79 AUE_RMDIR STD { int ibcs2_rmdir(char *path); } -80 AUE_MKDIR STD { int ibcs2_mkdir(char *path, int mode); } -81 AUE_GETDIRENTRIES STD { int ibcs2_getdents(int fd, char *buf, \ - int nbytes); } -82 AUE_NULL UNIMPL nosys -83 AUE_NULL UNIMPL nosys -84 AUE_NULL STD { int ibcs2_sysfs(int cmd, caddr_t d1, \ - char *buf); } -85 AUE_GETMSG STD { int ibcs2_getmsg(int fd, \ - struct ibcs2_stropts *ctl, \ - struct ibcs2_stropts *dat, int *flags); } -86 AUE_PUTMSG STD { int ibcs2_putmsg(int fd, \ - struct ibcs2_stropts *ctl, \ - struct ibcs2_stropts *dat, int flags); } -87 AUE_POLL NOPROTO { int poll(struct pollfd *fds, u_int nfds, \ - int timeout); } -88 AUE_NULL UNIMPL nosys -89 AUE_NULL STD { int ibcs2_secure(int cmd, int a1, int a2, \ - int a3, int a4, int a5); } -90 AUE_SYMLINK STD { int ibcs2_symlink(char *path, \ - char *link); } -91 AUE_LSTAT STD { int ibcs2_lstat(char *path, \ - struct ibcs2_stat *st); } -92 AUE_READLINK STD { int ibcs2_readlink(char *path, char *buf, \ - int count); } -93 AUE_NULL UNIMPL nosys -94 AUE_NULL UNIMPL nosys -95 AUE_NULL UNIMPL nosys -96 AUE_NULL UNIMPL nosys -97 AUE_NULL UNIMPL nosys -98 AUE_NULL UNIMPL nosys -99 AUE_NULL UNIMPL nosys -100 AUE_NULL UNIMPL nosys -101 AUE_NULL UNIMPL nosys -102 AUE_NULL UNIMPL nosys -103 AUE_NULL NOPROTO { int sigreturn( \ - struct sigcontext *sigcntxp); } -104 AUE_NULL UNIMPL nosys -105 AUE_NULL STD { int ibcs2_isc(void); } -106 AUE_NULL UNIMPL nosys -107 AUE_NULL UNIMPL nosys -108 AUE_NULL UNIMPL nosys -109 AUE_NULL UNIMPL nosys -110 AUE_NULL UNIMPL nosys -111 AUE_NULL UNIMPL nosys -112 AUE_NULL UNIMPL nosys -113 AUE_NULL UNIMPL nosys -114 AUE_NULL UNIMPL nosys -115 AUE_NULL UNIMPL nosys -116 AUE_NULL UNIMPL nosys -117 AUE_NULL UNIMPL nosys -118 AUE_NULL UNIMPL nosys -119 AUE_NULL UNIMPL nosys -120 AUE_NULL UNIMPL nosys -121 AUE_NULL UNIMPL nosys -122 AUE_NULL UNIMPL nosys -123 AUE_NULL UNIMPL nosys -124 AUE_NULL UNIMPL nosys -125 AUE_NULL UNIMPL nosys -126 AUE_NULL UNIMPL nosys -127 AUE_NULL UNIMPL nosys -; vim: syntax=off diff --git a/sys/i386/ibcs2/syscalls.xenix b/sys/i386/ibcs2/syscalls.xenix deleted file mode 100644 index 65539d1d75a..00000000000 --- a/sys/i386/ibcs2/syscalls.xenix +++ /dev/null @@ -1,76 +0,0 @@ - -#include -#include -#include -#include -#include -#include - -0 AUE_NULL UNIMPL nosys -1 AUE_NULL UNIMPL xenix_xlocking -2 AUE_NULL UNIMPL xenix_creatsem -3 AUE_NULL UNIMPL xenix_opensem -4 AUE_NULL UNIMPL xenix_sigsem -5 AUE_NULL UNIMPL xenix_waitsem -6 AUE_NULL UNIMPL xenix_nbwaitsem -7 AUE_NULL STD { int xenix_rdchk(int fd); } -8 AUE_NULL UNIMPL nosys -9 AUE_NULL UNIMPL nosys -10 AUE_FTRUNCATE STD { int xenix_chsize(int fd, long size); } -11 AUE_NULL STD { int xenix_ftime(struct timeb *tp); } -12 AUE_NULL STD { int xenix_nap(int millisec); } -13 AUE_NULL UNIMPL xenix_sdget -14 AUE_NULL UNIMPL xenix_sdfree -15 AUE_NULL UNIMPL xenix_sdenter -16 AUE_NULL UNIMPL xenix_sdleave -17 AUE_NULL UNIMPL xenix_sdgetv -18 AUE_NULL UNIMPL xenix_sdwaitv -19 AUE_NULL UNIMPL nosys -20 AUE_NULL UNIMPL nosys -21 AUE_NULL STD { int xenix_scoinfo(void); } -22 AUE_NULL UNIMPL nosys -23 AUE_NULL UNIMPL nosys -24 AUE_NULL UNIMPL nosys -25 AUE_NULL UNIMPL nosys -26 AUE_NULL UNIMPL nosys -27 AUE_NULL UNIMPL nosys -28 AUE_NULL UNIMPL nosys -29 AUE_NULL UNIMPL nosys -30 AUE_NULL UNIMPL nosys -31 AUE_NULL UNIMPL nosys -32 AUE_NULL UNIMPL xenix_proctl -33 AUE_NULL UNIMPL xenix_execseg -34 AUE_NULL UNIMPL xenix_unexecseg -35 AUE_NULL UNIMPL nosys -36 AUE_SELECT NOPROTO { int select(u_int nd, fd_set *in, \ - fd_set *ou, fd_set *ex, \ - struct timeval *tv); } -37 AUE_EACCESS STD { int xenix_eaccess(char *path, int flags); } -38 AUE_NULL UNIMPL xenix_paccess -39 AUE_NULL STD { int ibcs2_sigaction(int sig, \ - struct ibcs2_sigaction *act, \ - struct ibcs2_sigaction *oact); } -40 AUE_NULL STD { int ibcs2_sigprocmask(int how, \ - ibcs2_sigset_t *set, \ - ibcs2_sigset_t *oset); } -41 AUE_NULL STD { int ibcs2_sigpending(ibcs2_sigset_t *mask); } -42 AUE_NULL STD { int ibcs2_sigsuspend(ibcs2_sigset_t *mask); } -43 AUE_GETGROUPS STD { int ibcs2_getgroups(int gidsetsize, \ - ibcs2_gid_t *gidset); } -44 AUE_SETGROUPS STD { int ibcs2_setgroups(int gidsetsize, \ - ibcs2_gid_t *gidset); } -45 AUE_NULL STD { int ibcs2_sysconf(int name); } -46 AUE_PATHCONF STD { int ibcs2_pathconf(char *path, int name); } -47 AUE_FPATHCONF STD { int ibcs2_fpathconf(int fd, int name); } -48 AUE_RENAME STD { int ibcs2_rename(char *from, char *to); } -49 AUE_NULL UNIMPL nosys -50 AUE_NULL STD { int xenix_utsname(long addr); } -51 AUE_NULL UNIMPL nosys -52 AUE_NULL UNIMPL nosys -53 AUE_NULL UNIMPL nosys -54 AUE_NULL UNIMPL nosys -55 AUE_GETITIMER NOPROTO { int getitimer(u_int which, \ - struct itimerval *itv); } -56 AUE_SETITIMER NOPROTO { int setitimer(u_int which, \ - struct itimerval *itv, \ - struct itimerval *otv); } diff --git a/sys/i386/ibcs2/syscalls.xenix.conf b/sys/i386/ibcs2/syscalls.xenix.conf deleted file mode 100644 index 9d7f1146937..00000000000 --- a/sys/i386/ibcs2/syscalls.xenix.conf +++ /dev/null @@ -1,10 +0,0 @@ -sysnames="/dev/null" -sysproto="ibcs2_xenix.h" -sysproto_h=_IBCS2_XENIX_H_ -syshdr="ibcs2_xenix_syscall.h" -sysmk="/dev/null" -syssw="ibcs2_xenix_sysent.c" -syscallprefix="IBCS2_XENIX_" -switchname="xenix_sysent" -namesname="xenix_syscallnames" -systrace="/dev/null" diff --git a/sys/i386/include/if_wl_wavelan.h b/sys/i386/include/if_wl_wavelan.h deleted file mode 100644 index a69ab8c4dcf..00000000000 --- a/sys/i386/include/if_wl_wavelan.h +++ /dev/null @@ -1,168 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain all copyright - * notices, this list of conditions and the following disclaimer. - * 2. The names of the authors may not be used to endorse or promote products - * derived from this software without specific prior written permission - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -#ifndef _CHIPS_WAVELAN_H -#define _CHIPS_WAVELAN_H - -/* This file contains definitions that are common for all versions of - * the NCR WaveLAN - */ - -#define WAVELAN_ADDR_SIZE 6 /* Size of a MAC address */ -#define WAVELAN_MTU 1500 /* Maximum size of Wavelan packet */ - -/* Modem Management Controler write commands */ -#define MMC_ENCR_KEY 0x00 /* to 0x07 */ -#define MMC_ENCR_ENABLE 0x08 -#define MMC_DES_IO_INVERT 0x0a -#define MMC_LOOPT_SEL 0x10 -#define MMC_JABBER_ENABLE 0x11 -#define MMC_FREEZE 0x12 -#define MMC_ANTEN_SEL 0x13 -#define MMC_IFS 0x14 -#define MMC_MOD_DELAY 0x15 -#define MMC_JAM_TIME 0x16 -#define MMC_THR_PRE_SET 0x18 -#define MMC_DECAY_PRM 0x19 -#define MMC_DECAY_UPDAT_PRM 0x1a -#define MMC_QUALITY_THR 0x1b -#define MMC_NETW_ID_L 0x1c -#define MMC_NETW_ID_H 0x1d -#define MMC_MODE_SEL 0x1e -#define MMC_EECTRL 0x20 /* 2.4 Gz */ -#define MMC_EEADDR 0x21 /* 2.4 Gz */ -#define MMC_EEDATAL 0x22 /* 2.4 Gz */ -#define MMC_EEDATAH 0x23 /* 2.4 Gz */ -#define MMC_ANALCTRL 0x24 /* 2.4 Gz */ - -/* fields in MMC registers that relate to EEPROM in WaveMODEM daughtercard */ -#define MMC_EECTRL_EEPRE 0x10 /* 2.4 Gz EEPROM Protect Reg Enable */ -#define MMC_EECTRL_DWLD 0x08 /* 2.4 Gz EEPROM Download Synths */ -#define MMC_EECTRL_EEOP 0x07 /* 2.4 Gz EEPROM Opcode mask */ -#define MMC_EECTRL_EEOP_READ 0x06 /* 2.4 Gz EEPROM Read Opcode */ -#define MMC_EEADDR_CHAN 0xf0 /* 2.4 Gz EEPROM Channel # mask */ -#define MMC_EEADDR_WDCNT 0x0f /* 2.4 Gz EEPROM DNLD WordCount-1 */ -#define MMC_ANALCTRL_ANTPOL 0x02 /* 2.4 Gz Antenna Polarity mask */ -#define MMC_ANALCTRL_EXTANT 0x01 /* 2.4 Gz External Antenna mask */ - -/* MMC read register names */ -#define MMC_DCE_STATUS 0x10 -#define MMC_CORRECT_NWID_L 0x14 -#define MMC_CORRECT_NWID_H 0x15 -#define MMC_WRONG_NWID_L 0x16 -#define MMC_WRONG_NWID_H 0x17 -#define MMC_THR_PRE_SET 0x18 -#define MMC_SIGNAL_LVL 0x19 -#define MMC_SILENCE_LVL 0x1a -#define MMC_SIGN_QUAL 0x1b -#define MMC_DES_AVAIL 0x09 -#define MMC_EECTRLstat 0x20 /* 2.4 Gz EEPROM r/w/dwld status */ -#define MMC_EEDATALrv 0x22 /* 2.4 Gz EEPROM read value */ -#define MMC_EEDATAHrv 0x23 /* 2.4 Gz EEPROM read value */ - -/* fields in MMC registers that relate to EEPROM in WaveMODEM daughtercard */ -#define MMC_EECTRLstat_ID24 0xf0 /* 2.4 Gz =A0 rev-A, =B0 rev-B */ -#define MMC_EECTRLstat_DWLD 0x08 /* 2.4 Gz Synth/Tx-Pwr DWLD busy */ -#define MMC_EECTRLstat_EEBUSY 0x04 /* 2.4 Gz EEPROM busy */ - -/* additional socket ioctl params for wl card - * see sys/sockio.h for numbers. The 2nd params here - * must be greater than any values in sockio.h - */ - -#define SIOCGWLCNWID _IOWR('i', 60, struct ifreq) /* get wlan current nwid */ -#define SIOCSWLCNWID _IOWR('i', 61, struct ifreq) /* set wlan current nwid */ -#define SIOCGWLPSA _IOWR('i', 62, struct ifreq) /* get wlan PSA (all) */ -#define SIOCSWLPSA _IOWR('i', 63, struct ifreq) /* set wlan PSA (all) */ -#define SIOCDWLCACHE _IOW('i', 64, struct ifreq) /* clear SNR cache */ -#define SIOCSWLTHR _IOW('i', 65, struct ifreq) /* set new quality threshold */ -#define SIOCGWLEEPROM _IOWR('i', 66, struct ifreq) /* get modem EEPROM */ -#define SIOCGWLCACHE _IOWR('i', 67, struct ifreq) /* get SNR cache */ -#define SIOCGWLCITEM _IOWR('i', 68, struct ifreq) /* get cache element count */ - -/* PSA address definitions */ -#define WLPSA_ID 0x0 /* ID byte (0 for ISA, 0x14 for MCA) */ -#define WLPSA_IO1 0x1 /* I/O address 1 */ -#define WLPSA_IO2 0x2 /* I/O address 2 */ -#define WLPSA_IO3 0x3 /* I/O address 3 */ -#define WLPSA_BR1 0x4 /* Bootrom address 1 */ -#define WLPSA_BR2 0x5 /* Bootrom address 2 */ -#define WLPSA_BR3 0x6 /* Bootrom address 3 */ -#define WLPSA_HWCONF 0x7 /* HW config bits */ -#define WLPSA_IRQNO 0x8 /* IRQ value */ -#define WLPSA_UNIMAC 0x10 /* Universal MAC address */ -#define WLPSA_LOCALMAC 0x16 /* Locally configured MAC address */ -#define WLPSA_MACSEL 0x1c /* MAC selector */ -#define WLPSA_COMPATNO 0x1d /* compatibility number */ -#define WLPSA_THRESH 0x1e /* RF modem threshold preset */ -#define WLPSA_FEATSEL 0x1f /* feature select */ -#define WLPSA_SUBBAND 0x20 /* subband selector */ -#define WLPSA_QUALTHRESH 0x21 /* RF modem quality threshold preset */ -#define WLPSA_HWVERSION 0x22 /* hardware version indicator */ -#define WLPSA_NWID 0x23 /* network ID */ -#define WLPSA_NWIDENABLE 0x24 /* network ID enable */ -#define WLPSA_SECURITY 0x25 /* datalink security enable */ -#define WLPSA_DESKEY 0x26 /* datalink security DES key */ -#define WLPSA_DBWIDTH 0x2f /* databus width select */ -#define WLPSA_CALLCODE 0x30 /* call code (japan only) */ -#define WLPSA_CONFIGURED 0x3c /* configuration status */ -#define WLPSA_CRCLOW 0x3d /* CRC-16 (lowbyte) */ -#define WLPSA_CRCHIGH 0x3e /* (highbyte) */ -#define WLPSA_CRCOK 0x3f /* CRC OK flag */ - -#define WLPSA_COMPATNO_WL24B 0x04 /* 2.4 Gz WaveMODEM ISA rev-B */ - -/* - * signal strength cache - * - * driver (wlp only at the moment) keeps cache of last - * IP (only) packets to arrive including signal strength info. - * daemons may read this with kvm. See if_wlp.c for globals - * that may be accessed through kvm. - * - * Each entry in the w_sigcache has a unique macsrc and age. - * Each entry is identified by its macsrc field. - * Age of the packet is identified by its age field. - */ - -#define MAXCACHEITEMS 10 -#ifndef INT_MAX -#define INT_MAX 2147483647 -#endif -#define MAX_AGE (INT_MAX - MAXCACHEITEMS) - -/* signal is 7 bits, 0..63, although it doesn't seem to get to 63. - * silence is 7 bits, 0..63 - * quality is 4 bits, 0..15 - */ -struct w_sigcache { - char macsrc[6]; /* unique MAC address for entry */ - int ipsrc; /* ip address associated with packet */ - int signal; /* signal strength of the packet */ - int silence; /* silence of the packet */ - int quality; /* quality of the packet */ - int snr; /* packet has unique age between 1 to MAX_AGE - 1 */ -}; - -#endif /* _CHIPS_WAVELAN_H */ - diff --git a/sys/i386/include/ioctl_bt848.h b/sys/i386/include/ioctl_bt848.h deleted file mode 100644 index 0d401cef78c..00000000000 --- a/sys/i386/include/ioctl_bt848.h +++ /dev/null @@ -1,41 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2003 David O'Brien - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef _MACHINE_IOCTL_BT848_H_ -#define _MACHINE_IOCTL_BT848_H_ - -#include - -#ifdef __CC_SUPPORTS_WARNING -#warning Include dev/bktr/ioctl_bt848.h instead of this header. -#endif - -#include - -#endif /* _MACHINE_IOCTL_BT848_H_ */ diff --git a/sys/i386/include/ioctl_meteor.h b/sys/i386/include/ioctl_meteor.h deleted file mode 100644 index 72f75e348ba..00000000000 --- a/sys/i386/include/ioctl_meteor.h +++ /dev/null @@ -1,41 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2003 David O'Brien - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef _MACHINE_IOCTL_METEOR_H_ -#define _MACHINE_IOCTL_METEOR_H_ - -#include - -#ifdef __CC_SUPPORTS_WARNING -#warning Include dev/bktr/ioctl_meteor.h instead of this header. -#endif - -#include - -#endif /* _MACHINE_IOCTL_METEOR_H_ */ diff --git a/sys/i386/linux/linux_ptrace.c b/sys/i386/linux/linux_ptrace.c deleted file mode 100644 index 2c86061566e..00000000000 --- a/sys/i386/linux/linux_ptrace.c +++ /dev/null @@ -1,473 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2001 Alexander Kabaev - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include - -#include "opt_cpu.h" - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include -#include -#include - -/* - * Linux ptrace requests numbers. Mostly identical to FreeBSD, - * except for MD ones and PT_ATTACH/PT_DETACH. - */ -#define PTRACE_TRACEME 0 -#define PTRACE_PEEKTEXT 1 -#define PTRACE_PEEKDATA 2 -#define PTRACE_PEEKUSR 3 -#define PTRACE_POKETEXT 4 -#define PTRACE_POKEDATA 5 -#define PTRACE_POKEUSR 6 -#define PTRACE_CONT 7 -#define PTRACE_KILL 8 -#define PTRACE_SINGLESTEP 9 - -#define PTRACE_ATTACH 16 -#define PTRACE_DETACH 17 - -#define LINUX_PTRACE_SYSCALL 24 - -#define PTRACE_GETREGS 12 -#define PTRACE_SETREGS 13 -#define PTRACE_GETFPREGS 14 -#define PTRACE_SETFPREGS 15 -#define PTRACE_GETFPXREGS 18 -#define PTRACE_SETFPXREGS 19 - -#define PTRACE_SETOPTIONS 21 - -/* - * Linux keeps debug registers at the following - * offset in the user struct - */ -#define LINUX_DBREG_OFFSET 252 -#define LINUX_DBREG_SIZE (8*sizeof(l_int)) - -static __inline int -map_signum(int signum) -{ - - signum = linux_to_bsd_signal(signum); - return ((signum == SIGSTOP)? 0 : signum); -} - -struct linux_pt_reg { - l_long ebx; - l_long ecx; - l_long edx; - l_long esi; - l_long edi; - l_long ebp; - l_long eax; - l_int xds; - l_int xes; - l_int xfs; - l_int xgs; - l_long orig_eax; - l_long eip; - l_int xcs; - l_long eflags; - l_long esp; - l_int xss; -}; - -/* - * Translate i386 ptrace registers between Linux and FreeBSD formats. - * The translation is pretty straighforward, for all registers, but - * orig_eax on Linux side and r_trapno and r_err in FreeBSD - */ -static void -map_regs_to_linux(struct reg *bsd_r, struct linux_pt_reg *linux_r) -{ - linux_r->ebx = bsd_r->r_ebx; - linux_r->ecx = bsd_r->r_ecx; - linux_r->edx = bsd_r->r_edx; - linux_r->esi = bsd_r->r_esi; - linux_r->edi = bsd_r->r_edi; - linux_r->ebp = bsd_r->r_ebp; - linux_r->eax = bsd_r->r_eax; - linux_r->xds = bsd_r->r_ds; - linux_r->xes = bsd_r->r_es; - linux_r->xfs = bsd_r->r_fs; - linux_r->xgs = bsd_r->r_gs; - linux_r->orig_eax = bsd_r->r_eax; - linux_r->eip = bsd_r->r_eip; - linux_r->xcs = bsd_r->r_cs; - linux_r->eflags = bsd_r->r_eflags; - linux_r->esp = bsd_r->r_esp; - linux_r->xss = bsd_r->r_ss; -} - -static void -map_regs_from_linux(struct reg *bsd_r, struct linux_pt_reg *linux_r) -{ - bsd_r->r_ebx = linux_r->ebx; - bsd_r->r_ecx = linux_r->ecx; - bsd_r->r_edx = linux_r->edx; - bsd_r->r_esi = linux_r->esi; - bsd_r->r_edi = linux_r->edi; - bsd_r->r_ebp = linux_r->ebp; - bsd_r->r_eax = linux_r->eax; - bsd_r->r_ds = linux_r->xds; - bsd_r->r_es = linux_r->xes; - bsd_r->r_fs = linux_r->xfs; - bsd_r->r_gs = linux_r->xgs; - bsd_r->r_eip = linux_r->eip; - bsd_r->r_cs = linux_r->xcs; - bsd_r->r_eflags = linux_r->eflags; - bsd_r->r_esp = linux_r->esp; - bsd_r->r_ss = linux_r->xss; -} - -struct linux_pt_fpreg { - l_long cwd; - l_long swd; - l_long twd; - l_long fip; - l_long fcs; - l_long foo; - l_long fos; - l_long st_space[2*10]; -}; - -static void -map_fpregs_to_linux(struct fpreg *bsd_r, struct linux_pt_fpreg *linux_r) -{ - linux_r->cwd = bsd_r->fpr_env[0]; - linux_r->swd = bsd_r->fpr_env[1]; - linux_r->twd = bsd_r->fpr_env[2]; - linux_r->fip = bsd_r->fpr_env[3]; - linux_r->fcs = bsd_r->fpr_env[4]; - linux_r->foo = bsd_r->fpr_env[5]; - linux_r->fos = bsd_r->fpr_env[6]; - bcopy(bsd_r->fpr_acc, linux_r->st_space, sizeof(linux_r->st_space)); -} - -static void -map_fpregs_from_linux(struct fpreg *bsd_r, struct linux_pt_fpreg *linux_r) -{ - bsd_r->fpr_env[0] = linux_r->cwd; - bsd_r->fpr_env[1] = linux_r->swd; - bsd_r->fpr_env[2] = linux_r->twd; - bsd_r->fpr_env[3] = linux_r->fip; - bsd_r->fpr_env[4] = linux_r->fcs; - bsd_r->fpr_env[5] = linux_r->foo; - bsd_r->fpr_env[6] = linux_r->fos; - bcopy(bsd_r->fpr_acc, linux_r->st_space, sizeof(bsd_r->fpr_acc)); -} - -struct linux_pt_fpxreg { - l_ushort cwd; - l_ushort swd; - l_ushort twd; - l_ushort fop; - l_long fip; - l_long fcs; - l_long foo; - l_long fos; - l_long mxcsr; - l_long reserved; - l_long st_space[32]; - l_long xmm_space[32]; - l_long padding[56]; -}; - -static int -linux_proc_read_fpxregs(struct thread *td, struct linux_pt_fpxreg *fpxregs) -{ - - PROC_LOCK_ASSERT(td->td_proc, MA_OWNED); - if (cpu_fxsr == 0 || (td->td_proc->p_flag & P_INMEM) == 0) - return (EIO); - bcopy(&get_pcb_user_save_td(td)->sv_xmm, fpxregs, sizeof(*fpxregs)); - return (0); -} - -static int -linux_proc_write_fpxregs(struct thread *td, struct linux_pt_fpxreg *fpxregs) -{ - - PROC_LOCK_ASSERT(td->td_proc, MA_OWNED); - if (cpu_fxsr == 0 || (td->td_proc->p_flag & P_INMEM) == 0) - return (EIO); - bcopy(fpxregs, &get_pcb_user_save_td(td)->sv_xmm, sizeof(*fpxregs)); - return (0); -} - -int -linux_ptrace(struct thread *td, struct linux_ptrace_args *uap) -{ - union { - struct linux_pt_reg reg; - struct linux_pt_fpreg fpreg; - struct linux_pt_fpxreg fpxreg; - } r; - union { - struct reg bsd_reg; - struct fpreg bsd_fpreg; - struct dbreg bsd_dbreg; - } u; - void *addr; - pid_t pid; - int error, req; - - error = 0; - - /* by default, just copy data intact */ - req = uap->req; - pid = (pid_t)uap->pid; - addr = (void *)uap->addr; - - switch (req) { - case PTRACE_TRACEME: - case PTRACE_POKETEXT: - case PTRACE_POKEDATA: - case PTRACE_KILL: - error = kern_ptrace(td, req, pid, addr, uap->data); - break; - case PTRACE_PEEKTEXT: - case PTRACE_PEEKDATA: { - /* need to preserve return value */ - int rval = td->td_retval[0]; - error = kern_ptrace(td, req, pid, addr, 0); - if (error == 0) - error = copyout(td->td_retval, (void *)uap->data, - sizeof(l_int)); - td->td_retval[0] = rval; - break; - } - case PTRACE_DETACH: - error = kern_ptrace(td, PT_DETACH, pid, (void *)1, - map_signum(uap->data)); - break; - case PTRACE_SINGLESTEP: - case PTRACE_CONT: - error = kern_ptrace(td, req, pid, (void *)1, - map_signum(uap->data)); - break; - case PTRACE_ATTACH: - error = kern_ptrace(td, PT_ATTACH, pid, addr, uap->data); - break; - case PTRACE_GETREGS: - /* Linux is using data where FreeBSD is using addr */ - error = kern_ptrace(td, PT_GETREGS, pid, &u.bsd_reg, 0); - if (error == 0) { - map_regs_to_linux(&u.bsd_reg, &r.reg); - error = copyout(&r.reg, (void *)uap->data, - sizeof(r.reg)); - } - break; - case PTRACE_SETREGS: - /* Linux is using data where FreeBSD is using addr */ - error = copyin((void *)uap->data, &r.reg, sizeof(r.reg)); - if (error == 0) { - map_regs_from_linux(&u.bsd_reg, &r.reg); - error = kern_ptrace(td, PT_SETREGS, pid, &u.bsd_reg, 0); - } - break; - case PTRACE_GETFPREGS: - /* Linux is using data where FreeBSD is using addr */ - error = kern_ptrace(td, PT_GETFPREGS, pid, &u.bsd_fpreg, 0); - if (error == 0) { - map_fpregs_to_linux(&u.bsd_fpreg, &r.fpreg); - error = copyout(&r.fpreg, (void *)uap->data, - sizeof(r.fpreg)); - } - break; - case PTRACE_SETFPREGS: - /* Linux is using data where FreeBSD is using addr */ - error = copyin((void *)uap->data, &r.fpreg, sizeof(r.fpreg)); - if (error == 0) { - map_fpregs_from_linux(&u.bsd_fpreg, &r.fpreg); - error = kern_ptrace(td, PT_SETFPREGS, pid, - &u.bsd_fpreg, 0); - } - break; - case PTRACE_SETFPXREGS: - error = copyin((void *)uap->data, &r.fpxreg, sizeof(r.fpxreg)); - if (error) - break; - /* FALL THROUGH */ - case PTRACE_GETFPXREGS: { - struct proc *p; - struct thread *td2; - - if (sizeof(struct linux_pt_fpxreg) != sizeof(struct savexmm)) { - static int once = 0; - if (!once) { - printf("linux: savexmm != linux_pt_fpxreg\n"); - once = 1; - } - error = EIO; - break; - } - - if ((p = pfind(uap->pid)) == NULL) { - error = ESRCH; - break; - } - - /* Exiting processes can't be debugged. */ - if ((p->p_flag & P_WEXIT) != 0) { - error = ESRCH; - goto fail; - } - - if ((error = p_candebug(td, p)) != 0) - goto fail; - - /* System processes can't be debugged. */ - if ((p->p_flag & P_SYSTEM) != 0) { - error = EINVAL; - goto fail; - } - - /* not being traced... */ - if ((p->p_flag & P_TRACED) == 0) { - error = EPERM; - goto fail; - } - - /* not being traced by YOU */ - if (p->p_pptr != td->td_proc) { - error = EBUSY; - goto fail; - } - - /* not currently stopped */ - if (!P_SHOULDSTOP(p) || (p->p_flag & P_WAITED) == 0) { - error = EBUSY; - goto fail; - } - - if (req == PTRACE_GETFPXREGS) { - _PHOLD(p); /* may block */ - td2 = FIRST_THREAD_IN_PROC(p); - error = linux_proc_read_fpxregs(td2, &r.fpxreg); - _PRELE(p); - PROC_UNLOCK(p); - if (error == 0) - error = copyout(&r.fpxreg, (void *)uap->data, - sizeof(r.fpxreg)); - } else { - /* clear dangerous bits exactly as Linux does*/ - r.fpxreg.mxcsr &= 0xffbf; - _PHOLD(p); /* may block */ - td2 = FIRST_THREAD_IN_PROC(p); - error = linux_proc_write_fpxregs(td2, &r.fpxreg); - _PRELE(p); - PROC_UNLOCK(p); - } - break; - - fail: - PROC_UNLOCK(p); - break; - } - case PTRACE_PEEKUSR: - case PTRACE_POKEUSR: { - error = EIO; - - /* check addr for alignment */ - if (uap->addr < 0 || uap->addr & (sizeof(l_int) - 1)) - break; - /* - * Allow Linux programs to access register values in - * user struct. We simulate this through PT_GET/SETREGS - * as necessary. - */ - if (uap->addr < sizeof(struct linux_pt_reg)) { - error = kern_ptrace(td, PT_GETREGS, pid, &u.bsd_reg, 0); - if (error != 0) - break; - - map_regs_to_linux(&u.bsd_reg, &r.reg); - if (req == PTRACE_PEEKUSR) { - error = copyout((char *)&r.reg + uap->addr, - (void *)uap->data, sizeof(l_int)); - break; - } - - *(l_int *)((char *)&r.reg + uap->addr) = - (l_int)uap->data; - - map_regs_from_linux(&u.bsd_reg, &r.reg); - error = kern_ptrace(td, PT_SETREGS, pid, &u.bsd_reg, 0); - } - - /* - * Simulate debug registers access - */ - if (uap->addr >= LINUX_DBREG_OFFSET && - uap->addr <= LINUX_DBREG_OFFSET + LINUX_DBREG_SIZE) { - error = kern_ptrace(td, PT_GETDBREGS, pid, &u.bsd_dbreg, - 0); - if (error != 0) - break; - - uap->addr -= LINUX_DBREG_OFFSET; - if (req == PTRACE_PEEKUSR) { - error = copyout((char *)&u.bsd_dbreg + - uap->addr, (void *)uap->data, - sizeof(l_int)); - break; - } - - *(l_int *)((char *)&u.bsd_dbreg + uap->addr) = - uap->data; - error = kern_ptrace(td, PT_SETDBREGS, pid, - &u.bsd_dbreg, 0); - } - - break; - } - case LINUX_PTRACE_SYSCALL: - /* fall through */ - default: - printf("linux: ptrace(%u, ...) not implemented\n", - (unsigned int)uap->req); - error = EINVAL; - break; - } - - return (error); -} diff --git a/sys/kgssapi/krb5/kcrypto_arcfour.c b/sys/kgssapi/krb5/kcrypto_arcfour.c deleted file mode 100644 index b7330733c87..00000000000 --- a/sys/kgssapi/krb5/kcrypto_arcfour.c +++ /dev/null @@ -1,224 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2008 Isilon Inc http://www.isilon.com/ - * Authors: Doug Rabson - * Developed with Red Inc: Alfred Perlstein - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include - -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include "kcrypto.h" - -static void -arcfour_init(struct krb5_key_state *ks) -{ - static struct timeval lastwarn; - - ks->ks_priv = NULL; - if (ratecheck(&lastwarn, &krb5_warn_interval)) - gone_in(13, "RC4 cipher for Kerberos GSS"); -} - -static void -arcfour_destroy(struct krb5_key_state *ks) -{ - -} - -static void -arcfour_set_key(struct krb5_key_state *ks, const void *in) -{ - void *kp = ks->ks_key; - - if (kp != in) - bcopy(in, kp, 16); -} - -static void -arcfour_random_to_key(struct krb5_key_state *ks, const void *in) -{ - - arcfour_set_key(ks, in); -} - -static void -arcfour_hmac(uint8_t *key, uint8_t *data, size_t datalen, - uint8_t *result) -{ - uint8_t buf[64]; - MD5_CTX md5; - int i; - - for (i = 0; i < 16; i++) - buf[i] = key[i] ^ 0x36; - for (; i < 64; i++) - buf[i] = 0x36; - - MD5Init(&md5); - MD5Update(&md5, buf, 64); - MD5Update(&md5, data, datalen); - MD5Final(result, &md5); - - for (i = 0; i < 16; i++) - buf[i] = key[i] ^ 0x5c; - for (; i < 64; i++) - buf[i] = 0x5c; - - MD5Init(&md5); - MD5Update(&md5, buf, 64); - MD5Update(&md5, result, 16); - MD5Final(result, &md5); -} - -static void -arcfour_derive_key(const struct krb5_key_state *ks, uint32_t usage, - uint8_t *newkey) -{ - uint8_t t[4]; - - t[0] = (usage >> 24); - t[1] = (usage >> 16); - t[2] = (usage >> 8); - t[3] = (usage >> 0); - if (ks->ks_class->ec_type == ETYPE_ARCFOUR_HMAC_MD5_56) { - uint8_t L40[14] = "fortybits"; - bcopy(t, L40 + 10, 4); - arcfour_hmac(ks->ks_key, L40, 14, newkey); - memset(newkey + 7, 0xab, 9); - } else { - arcfour_hmac(ks->ks_key, t, 4, newkey); - } -} - -static int -rc4_crypt_int(void *rs, void *buf, u_int len) -{ - - rc4_crypt(rs, buf, buf, len); - return (0); -} - -static void -arcfour_encrypt(const struct krb5_key_state *ks, struct mbuf *inout, - size_t skip, size_t len, void *ivec, size_t ivlen) -{ - struct rc4_state rs; - uint8_t newkey[16]; - - arcfour_derive_key(ks, 0, newkey); - - /* - * If we have an IV, then generate a new key from it using HMAC. - */ - if (ivec) { - uint8_t kk[16]; - arcfour_hmac(newkey, ivec, ivlen, kk); - rc4_init(&rs, kk, 16); - } else { - rc4_init(&rs, newkey, 16); - } - - m_apply(inout, skip, len, rc4_crypt_int, &rs); -} - -static int -MD5Update_int(void *ctx, void *buf, u_int len) -{ - - MD5Update(ctx, buf, len); - return (0); -} - -static void -arcfour_checksum(const struct krb5_key_state *ks, int usage, - struct mbuf *inout, size_t skip, size_t inlen, size_t outlen) -{ - MD5_CTX md5; - uint8_t Ksign[16]; - uint8_t t[4]; - uint8_t sgn_cksum[16]; - - arcfour_hmac(ks->ks_key, "signaturekey", 13, Ksign); - - t[0] = usage >> 0; - t[1] = usage >> 8; - t[2] = usage >> 16; - t[3] = usage >> 24; - - MD5Init(&md5); - MD5Update(&md5, t, 4); - m_apply(inout, skip, inlen, MD5Update_int, &md5); - MD5Final(sgn_cksum, &md5); - - arcfour_hmac(Ksign, sgn_cksum, 16, sgn_cksum); - m_copyback(inout, skip + inlen, outlen, sgn_cksum); -} - -struct krb5_encryption_class krb5_arcfour_encryption_class = { - "arcfour-hmac-md5", /* name */ - ETYPE_ARCFOUR_HMAC_MD5, /* etype */ - 0, /* flags */ - 1, /* blocklen */ - 1, /* msgblocklen */ - 8, /* checksumlen */ - 128, /* keybits */ - 16, /* keylen */ - arcfour_init, - arcfour_destroy, - arcfour_set_key, - arcfour_random_to_key, - arcfour_encrypt, - arcfour_encrypt, - arcfour_checksum -}; - -struct krb5_encryption_class krb5_arcfour_56_encryption_class = { - "arcfour-hmac-md5-56", /* name */ - ETYPE_ARCFOUR_HMAC_MD5_56, /* etype */ - 0, /* flags */ - 1, /* blocklen */ - 1, /* msgblocklen */ - 8, /* checksumlen */ - 128, /* keybits */ - 16, /* keylen */ - arcfour_init, - arcfour_destroy, - arcfour_set_key, - arcfour_random_to_key, - arcfour_encrypt, - arcfour_encrypt, - arcfour_checksum -}; diff --git a/sys/kgssapi/krb5/kcrypto_des.c b/sys/kgssapi/krb5/kcrypto_des.c deleted file mode 100644 index 80d98089867..00000000000 --- a/sys/kgssapi/krb5/kcrypto_des.c +++ /dev/null @@ -1,266 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2008 Isilon Inc http://www.isilon.com/ - * Authors: Doug Rabson - * Developed with Red Inc: Alfred Perlstein - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include "kcrypto.h" - -struct des1_state { - struct mtx ds_lock; - crypto_session_t ds_session; -}; - -static void -des1_init(struct krb5_key_state *ks) -{ - static struct timeval lastwarn; - struct des1_state *ds; - - ds = malloc(sizeof(struct des1_state), M_GSSAPI, M_WAITOK|M_ZERO); - mtx_init(&ds->ds_lock, "gss des lock", NULL, MTX_DEF); - ks->ks_priv = ds; - if (ratecheck(&lastwarn, &krb5_warn_interval)) - gone_in(13, "DES cipher for Kerberos GSS"); -} - -static void -des1_destroy(struct krb5_key_state *ks) -{ - struct des1_state *ds = ks->ks_priv; - - if (ds->ds_session) - crypto_freesession(ds->ds_session); - mtx_destroy(&ds->ds_lock); - free(ks->ks_priv, M_GSSAPI); - -} - -static void -des1_set_key(struct krb5_key_state *ks, const void *in) -{ - void *kp = ks->ks_key; - struct des1_state *ds = ks->ks_priv; - struct cryptoini cri[1]; - - if (kp != in) - bcopy(in, kp, ks->ks_class->ec_keylen); - - if (ds->ds_session) - crypto_freesession(ds->ds_session); - - bzero(cri, sizeof(cri)); - - cri[0].cri_alg = CRYPTO_DES_CBC; - cri[0].cri_klen = 64; - cri[0].cri_mlen = 0; - cri[0].cri_key = ks->ks_key; - cri[0].cri_next = NULL; - - crypto_newsession(&ds->ds_session, cri, - CRYPTOCAP_F_HARDWARE | CRYPTOCAP_F_SOFTWARE); -} - -static void -des1_random_to_key(struct krb5_key_state *ks, const void *in) -{ - uint8_t *outkey = ks->ks_key; - const uint8_t *inkey = in; - - /* - * Expand 56 bits of random data to 64 bits as follows - * (in the example, bit number 1 is the MSB of the 56 - * bits of random data): - * - * expanded = - * 1 2 3 4 5 6 7 p - * 9 10 11 12 13 14 15 p - * 17 18 19 20 21 22 23 p - * 25 26 27 28 29 30 31 p - * 33 34 35 36 37 38 39 p - * 41 42 43 44 45 46 47 p - * 49 50 51 52 53 54 55 p - * 56 48 40 32 24 16 8 p - */ - outkey[0] = inkey[0]; - outkey[1] = inkey[1]; - outkey[2] = inkey[2]; - outkey[3] = inkey[3]; - outkey[4] = inkey[4]; - outkey[5] = inkey[5]; - outkey[6] = inkey[6]; - outkey[7] = (((inkey[0] & 1) << 1) - | ((inkey[1] & 1) << 2) - | ((inkey[2] & 1) << 3) - | ((inkey[3] & 1) << 4) - | ((inkey[4] & 1) << 5) - | ((inkey[5] & 1) << 6) - | ((inkey[6] & 1) << 7)); - des_set_odd_parity((des_cblock *) outkey); - if (des_is_weak_key((des_cblock *) outkey)) - outkey[7] ^= 0xf0; - - des1_set_key(ks, ks->ks_key); -} - -static int -des1_crypto_cb(struct cryptop *crp) -{ - int error; - struct des1_state *ds = (struct des1_state *) crp->crp_opaque; - - if (crypto_ses2caps(ds->ds_session) & CRYPTOCAP_F_SYNC) - return (0); - - error = crp->crp_etype; - if (error == EAGAIN) - error = crypto_dispatch(crp); - mtx_lock(&ds->ds_lock); - if (error || (crp->crp_flags & CRYPTO_F_DONE)) - wakeup(crp); - mtx_unlock(&ds->ds_lock); - - return (0); -} - -static void -des1_encrypt_1(const struct krb5_key_state *ks, int buftype, void *buf, - size_t skip, size_t len, void *ivec, int encdec) -{ - struct des1_state *ds = ks->ks_priv; - struct cryptop *crp; - struct cryptodesc *crd; - int error; - - crp = crypto_getreq(1); - crd = crp->crp_desc; - - crd->crd_skip = skip; - crd->crd_len = len; - crd->crd_flags = CRD_F_IV_EXPLICIT | CRD_F_IV_PRESENT | encdec; - if (ivec) { - bcopy(ivec, crd->crd_iv, 8); - } else { - bzero(crd->crd_iv, 8); - } - crd->crd_next = NULL; - crd->crd_alg = CRYPTO_DES_CBC; - - crp->crp_session = ds->ds_session; - crp->crp_flags = buftype | CRYPTO_F_CBIFSYNC; - crp->crp_buf = buf; - crp->crp_opaque = (void *) ds; - crp->crp_callback = des1_crypto_cb; - - error = crypto_dispatch(crp); - - if ((crypto_ses2caps(ds->ds_session) & CRYPTOCAP_F_SYNC) == 0) { - mtx_lock(&ds->ds_lock); - if (!error && !(crp->crp_flags & CRYPTO_F_DONE)) - error = msleep(crp, &ds->ds_lock, 0, "gssdes", 0); - mtx_unlock(&ds->ds_lock); - } - - crypto_freereq(crp); -} - -static void -des1_encrypt(const struct krb5_key_state *ks, struct mbuf *inout, - size_t skip, size_t len, void *ivec, size_t ivlen) -{ - - des1_encrypt_1(ks, CRYPTO_F_IMBUF, inout, skip, len, ivec, - CRD_F_ENCRYPT); -} - -static void -des1_decrypt(const struct krb5_key_state *ks, struct mbuf *inout, - size_t skip, size_t len, void *ivec, size_t ivlen) -{ - - des1_encrypt_1(ks, CRYPTO_F_IMBUF, inout, skip, len, ivec, 0); -} - -static int -MD5Update_int(void *ctx, void *buf, u_int len) -{ - - MD5Update(ctx, buf, len); - return (0); -} - -static void -des1_checksum(const struct krb5_key_state *ks, int usage, - struct mbuf *inout, size_t skip, size_t inlen, size_t outlen) -{ - char hash[16]; - MD5_CTX md5; - - /* - * This checksum is specifically for GSS-API. First take the - * MD5 checksum of the message, then calculate the CBC mode - * checksum of that MD5 checksum using a zero IV. - */ - MD5Init(&md5); - m_apply(inout, skip, inlen, MD5Update_int, &md5); - MD5Final(hash, &md5); - - des1_encrypt_1(ks, 0, hash, 0, 16, NULL, CRD_F_ENCRYPT); - m_copyback(inout, skip + inlen, outlen, hash + 8); -} - -struct krb5_encryption_class krb5_des_encryption_class = { - "des-cbc-md5", /* name */ - ETYPE_DES_CBC_CRC, /* etype */ - 0, /* flags */ - 8, /* blocklen */ - 8, /* msgblocklen */ - 8, /* checksumlen */ - 56, /* keybits */ - 8, /* keylen */ - des1_init, - des1_destroy, - des1_set_key, - des1_random_to_key, - des1_encrypt, - des1_decrypt, - des1_checksum -}; diff --git a/sys/kgssapi/krb5/kcrypto_des3.c b/sys/kgssapi/krb5/kcrypto_des3.c deleted file mode 100644 index bbd1c9f5325..00000000000 --- a/sys/kgssapi/krb5/kcrypto_des3.c +++ /dev/null @@ -1,406 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2008 Isilon Inc http://www.isilon.com/ - * Authors: Doug Rabson - * Developed with Red Inc: Alfred Perlstein - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include "kcrypto.h" - -#define DES3_FLAGS (CRYPTOCAP_F_HARDWARE | CRYPTOCAP_F_SOFTWARE) - -struct des3_state { - struct mtx ds_lock; - crypto_session_t ds_session; -}; - -static void -des3_init(struct krb5_key_state *ks) -{ - static struct timeval lastwarn; - struct des3_state *ds; - - ds = malloc(sizeof(struct des3_state), M_GSSAPI, M_WAITOK|M_ZERO); - mtx_init(&ds->ds_lock, "gss des3 lock", NULL, MTX_DEF); - ks->ks_priv = ds; - if (ratecheck(&lastwarn, &krb5_warn_interval)) - gone_in(13, "DES3 cipher for Kerberos GSS"); -} - -static void -des3_destroy(struct krb5_key_state *ks) -{ - struct des3_state *ds = ks->ks_priv; - - if (ds->ds_session) - crypto_freesession(ds->ds_session); - mtx_destroy(&ds->ds_lock); - free(ks->ks_priv, M_GSSAPI); -} - -static void -des3_set_key(struct krb5_key_state *ks, const void *in) -{ - void *kp = ks->ks_key; - struct des3_state *ds = ks->ks_priv; - struct cryptoini cri[2]; - - if (kp != in) - bcopy(in, kp, ks->ks_class->ec_keylen); - - if (ds->ds_session) - crypto_freesession(ds->ds_session); - - bzero(cri, sizeof(cri)); - - cri[0].cri_alg = CRYPTO_SHA1_HMAC; - cri[0].cri_klen = 192; - cri[0].cri_mlen = 0; - cri[0].cri_key = ks->ks_key; - cri[0].cri_next = &cri[1]; - - cri[1].cri_alg = CRYPTO_3DES_CBC; - cri[1].cri_klen = 192; - cri[1].cri_mlen = 0; - cri[1].cri_key = ks->ks_key; - cri[1].cri_next = NULL; - - crypto_newsession(&ds->ds_session, cri, - CRYPTOCAP_F_HARDWARE | CRYPTOCAP_F_SOFTWARE); -} - -static void -des3_random_to_key(struct krb5_key_state *ks, const void *in) -{ - uint8_t *outkey; - const uint8_t *inkey; - int subkey; - - for (subkey = 0, outkey = ks->ks_key, inkey = in; subkey < 3; - subkey++, outkey += 8, inkey += 7) { - /* - * Expand 56 bits of random data to 64 bits as follows - * (in the example, bit number 1 is the MSB of the 56 - * bits of random data): - * - * expanded = - * 1 2 3 4 5 6 7 p - * 9 10 11 12 13 14 15 p - * 17 18 19 20 21 22 23 p - * 25 26 27 28 29 30 31 p - * 33 34 35 36 37 38 39 p - * 41 42 43 44 45 46 47 p - * 49 50 51 52 53 54 55 p - * 56 48 40 32 24 16 8 p - */ - outkey[0] = inkey[0]; - outkey[1] = inkey[1]; - outkey[2] = inkey[2]; - outkey[3] = inkey[3]; - outkey[4] = inkey[4]; - outkey[5] = inkey[5]; - outkey[6] = inkey[6]; - outkey[7] = (((inkey[0] & 1) << 1) - | ((inkey[1] & 1) << 2) - | ((inkey[2] & 1) << 3) - | ((inkey[3] & 1) << 4) - | ((inkey[4] & 1) << 5) - | ((inkey[5] & 1) << 6) - | ((inkey[6] & 1) << 7)); - des_set_odd_parity((des_cblock *) outkey); - if (des_is_weak_key((des_cblock *) outkey)) - outkey[7] ^= 0xf0; - } - - des3_set_key(ks, ks->ks_key); -} - -static int -des3_crypto_cb(struct cryptop *crp) -{ - int error; - struct des3_state *ds = (struct des3_state *) crp->crp_opaque; - - if (crypto_ses2caps(ds->ds_session) & CRYPTOCAP_F_SYNC) - return (0); - - error = crp->crp_etype; - if (error == EAGAIN) - error = crypto_dispatch(crp); - mtx_lock(&ds->ds_lock); - if (error || (crp->crp_flags & CRYPTO_F_DONE)) - wakeup(crp); - mtx_unlock(&ds->ds_lock); - - return (0); -} - -static void -des3_encrypt_1(const struct krb5_key_state *ks, struct mbuf *inout, - size_t skip, size_t len, void *ivec, int encdec) -{ - struct des3_state *ds = ks->ks_priv; - struct cryptop *crp; - struct cryptodesc *crd; - int error; - - crp = crypto_getreq(1); - crd = crp->crp_desc; - - crd->crd_skip = skip; - crd->crd_len = len; - crd->crd_flags = CRD_F_IV_EXPLICIT | CRD_F_IV_PRESENT | encdec; - if (ivec) { - bcopy(ivec, crd->crd_iv, 8); - } else { - bzero(crd->crd_iv, 8); - } - crd->crd_next = NULL; - crd->crd_alg = CRYPTO_3DES_CBC; - - crp->crp_session = ds->ds_session; - crp->crp_flags = CRYPTO_F_IMBUF | CRYPTO_F_CBIFSYNC; - crp->crp_buf = (void *) inout; - crp->crp_opaque = (void *) ds; - crp->crp_callback = des3_crypto_cb; - - error = crypto_dispatch(crp); - - if ((crypto_ses2caps(ds->ds_session) & CRYPTOCAP_F_SYNC) == 0) { - mtx_lock(&ds->ds_lock); - if (!error && !(crp->crp_flags & CRYPTO_F_DONE)) - error = msleep(crp, &ds->ds_lock, 0, "gssdes3", 0); - mtx_unlock(&ds->ds_lock); - } - - crypto_freereq(crp); -} - -static void -des3_encrypt(const struct krb5_key_state *ks, struct mbuf *inout, - size_t skip, size_t len, void *ivec, size_t ivlen) -{ - - des3_encrypt_1(ks, inout, skip, len, ivec, CRD_F_ENCRYPT); -} - -static void -des3_decrypt(const struct krb5_key_state *ks, struct mbuf *inout, - size_t skip, size_t len, void *ivec, size_t ivlen) -{ - - des3_encrypt_1(ks, inout, skip, len, ivec, 0); -} - -static void -des3_checksum(const struct krb5_key_state *ks, int usage, - struct mbuf *inout, size_t skip, size_t inlen, size_t outlen) -{ - struct des3_state *ds = ks->ks_priv; - struct cryptop *crp; - struct cryptodesc *crd; - int error; - - crp = crypto_getreq(1); - crd = crp->crp_desc; - - crd->crd_skip = skip; - crd->crd_len = inlen; - crd->crd_inject = skip + inlen; - crd->crd_flags = 0; - crd->crd_next = NULL; - crd->crd_alg = CRYPTO_SHA1_HMAC; - - crp->crp_session = ds->ds_session; - crp->crp_ilen = inlen; - crp->crp_olen = 20; - crp->crp_etype = 0; - crp->crp_flags = CRYPTO_F_IMBUF | CRYPTO_F_CBIFSYNC; - crp->crp_buf = (void *) inout; - crp->crp_opaque = (void *) ds; - crp->crp_callback = des3_crypto_cb; - - error = crypto_dispatch(crp); - - if ((crypto_ses2caps(ds->ds_session) & CRYPTOCAP_F_SYNC) == 0) { - mtx_lock(&ds->ds_lock); - if (!error && !(crp->crp_flags & CRYPTO_F_DONE)) - error = msleep(crp, &ds->ds_lock, 0, "gssdes3", 0); - mtx_unlock(&ds->ds_lock); - } - - crypto_freereq(crp); -} - -struct krb5_encryption_class krb5_des3_encryption_class = { - "des3-cbc-sha1", /* name */ - ETYPE_DES3_CBC_SHA1, /* etype */ - EC_DERIVED_KEYS, /* flags */ - 8, /* blocklen */ - 8, /* msgblocklen */ - 20, /* checksumlen */ - 168, /* keybits */ - 24, /* keylen */ - des3_init, - des3_destroy, - des3_set_key, - des3_random_to_key, - des3_encrypt, - des3_decrypt, - des3_checksum -}; - -#if 0 -struct des3_dk_test { - uint8_t key[24]; - uint8_t usage[8]; - size_t usagelen; - uint8_t dk[24]; -}; -struct des3_dk_test tests[] = { - {{0xdc, 0xe0, 0x6b, 0x1f, 0x64, 0xc8, 0x57, 0xa1, 0x1c, 0x3d, 0xb5, - 0x7c, 0x51, 0x89, 0x9b, 0x2c, 0xc1, 0x79, 0x10, 0x08, 0xce, 0x97, - 0x3b, 0x92}, - {0x00, 0x00, 0x00, 0x01, 0x55}, 5, - {0x92, 0x51, 0x79, 0xd0, 0x45, 0x91, 0xa7, 0x9b, 0x5d, 0x31, 0x92, - 0xc4, 0xa7, 0xe9, 0xc2, 0x89, 0xb0, 0x49, 0xc7, 0x1f, 0x6e, 0xe6, - 0x04, 0xcd}}, - - {{0x5e, 0x13, 0xd3, 0x1c, 0x70, 0xef, 0x76, 0x57, 0x46, 0x57, 0x85, - 0x31, 0xcb, 0x51, 0xc1, 0x5b, 0xf1, 0x1c, 0xa8, 0x2c, 0x97, 0xce, - 0xe9, 0xf2}, - {0x00, 0x00, 0x00, 0x01, 0xaa}, 5, - {0x9e, 0x58, 0xe5, 0xa1, 0x46, 0xd9, 0x94, 0x2a, 0x10, 0x1c, 0x46, - 0x98, 0x45, 0xd6, 0x7a, 0x20, 0xe3, 0xc4, 0x25, 0x9e, 0xd9, 0x13, - 0xf2, 0x07}}, - - {{0x98, 0xe6, 0xfd, 0x8a, 0x04, 0xa4, 0xb6, 0x85, 0x9b, 0x75, 0xa1, - 0x76, 0x54, 0x0b, 0x97, 0x52, 0xba, 0xd3, 0xec, 0xd6, 0x10, 0xa2, - 0x52, 0xbc}, - {0x00, 0x00, 0x00, 0x01, 0x55}, 5, - {0x13, 0xfe, 0xf8, 0x0d, 0x76, 0x3e, 0x94, 0xec, 0x6d, 0x13, 0xfd, - 0x2c, 0xa1, 0xd0, 0x85, 0x07, 0x02, 0x49, 0xda, 0xd3, 0x98, 0x08, - 0xea, 0xbf}}, - - {{0x62, 0x2a, 0xec, 0x25, 0xa2, 0xfe, 0x2c, 0xad, 0x70, 0x94, 0x68, - 0x0b, 0x7c, 0x64, 0x94, 0x02, 0x80, 0x08, 0x4c, 0x1a, 0x7c, 0xec, - 0x92, 0xb5}, - {0x00, 0x00, 0x00, 0x01, 0xaa}, 5, - {0xf8, 0xdf, 0xbf, 0x04, 0xb0, 0x97, 0xe6, 0xd9, 0xdc, 0x07, 0x02, - 0x68, 0x6b, 0xcb, 0x34, 0x89, 0xd9, 0x1f, 0xd9, 0xa4, 0x51, 0x6b, - 0x70, 0x3e}}, - - {{0xd3, 0xf8, 0x29, 0x8c, 0xcb, 0x16, 0x64, 0x38, 0xdc, 0xb9, 0xb9, - 0x3e, 0xe5, 0xa7, 0x62, 0x92, 0x86, 0xa4, 0x91, 0xf8, 0x38, 0xf8, - 0x02, 0xfb}, - {0x6b, 0x65, 0x72, 0x62, 0x65, 0x72, 0x6f, 0x73}, 8, - {0x23, 0x70, 0xda, 0x57, 0x5d, 0x2a, 0x3d, 0xa8, 0x64, 0xce, 0xbf, - 0xdc, 0x52, 0x04, 0xd5, 0x6d, 0xf7, 0x79, 0xa7, 0xdf, 0x43, 0xd9, - 0xda, 0x43}}, - - {{0xc1, 0x08, 0x16, 0x49, 0xad, 0xa7, 0x43, 0x62, 0xe6, 0xa1, 0x45, - 0x9d, 0x01, 0xdf, 0xd3, 0x0d, 0x67, 0xc2, 0x23, 0x4c, 0x94, 0x07, - 0x04, 0xda}, - {0x00, 0x00, 0x00, 0x01, 0x55}, 5, - {0x34, 0x80, 0x57, 0xec, 0x98, 0xfd, 0xc4, 0x80, 0x16, 0x16, 0x1c, - 0x2a, 0x4c, 0x7a, 0x94, 0x3e, 0x92, 0xae, 0x49, 0x2c, 0x98, 0x91, - 0x75, 0xf7}}, - - {{0x5d, 0x15, 0x4a, 0xf2, 0x38, 0xf4, 0x67, 0x13, 0x15, 0x57, 0x19, - 0xd5, 0x5e, 0x2f, 0x1f, 0x79, 0x0d, 0xd6, 0x61, 0xf2, 0x79, 0xa7, - 0x91, 0x7c}, - {0x00, 0x00, 0x00, 0x01, 0xaa}, 5, - {0xa8, 0x80, 0x8a, 0xc2, 0x67, 0xda, 0xda, 0x3d, 0xcb, 0xe9, 0xa7, - 0xc8, 0x46, 0x26, 0xfb, 0xc7, 0x61, 0xc2, 0x94, 0xb0, 0x13, 0x15, - 0xe5, 0xc1}}, - - {{0x79, 0x85, 0x62, 0xe0, 0x49, 0x85, 0x2f, 0x57, 0xdc, 0x8c, 0x34, - 0x3b, 0xa1, 0x7f, 0x2c, 0xa1, 0xd9, 0x73, 0x94, 0xef, 0xc8, 0xad, - 0xc4, 0x43}, - {0x00, 0x00, 0x00, 0x01, 0x55}, 5, - {0xc8, 0x13, 0xf8, 0x8a, 0x3b, 0xe3, 0xb3, 0x34, 0xf7, 0x54, 0x25, - 0xce, 0x91, 0x75, 0xfb, 0xe3, 0xc8, 0x49, 0x3b, 0x89, 0xc8, 0x70, - 0x3b, 0x49}}, - - {{0x26, 0xdc, 0xe3, 0x34, 0xb5, 0x45, 0x29, 0x2f, 0x2f, 0xea, 0xb9, - 0xa8, 0x70, 0x1a, 0x89, 0xa4, 0xb9, 0x9e, 0xb9, 0x94, 0x2c, 0xec, - 0xd0, 0x16}, - {0x00, 0x00, 0x00, 0x01, 0xaa}, 5, - {0xf4, 0x8f, 0xfd, 0x6e, 0x83, 0xf8, 0x3e, 0x73, 0x54, 0xe6, 0x94, - 0xfd, 0x25, 0x2c, 0xf8, 0x3b, 0xfe, 0x58, 0xf7, 0xd5, 0xba, 0x37, - 0xec, 0x5d}}, -}; -#define N_TESTS (sizeof(tests) / sizeof(tests[0])) - -int -main(int argc, char **argv) -{ - struct krb5_key_state *key, *dk; - uint8_t *dkp; - int j, i; - - for (j = 0; j < N_TESTS; j++) { - struct des3_dk_test *t = &tests[j]; - key = krb5_create_key(&des3_encryption_class); - krb5_set_key(key, t->key); - dk = krb5_derive_key(key, t->usage, t->usagelen); - krb5_free_key(key); - if (memcmp(dk->ks_key, t->dk, 24)) { - printf("DES3 dk("); - for (i = 0; i < 24; i++) - printf("%02x", t->key[i]); - printf(", "); - for (i = 0; i < t->usagelen; i++) - printf("%02x", t->usage[i]); - printf(") failed\n"); - printf("should be: "); - for (i = 0; i < 24; i++) - printf("%02x", t->dk[i]); - printf("\n result was: "); - dkp = dk->ks_key; - for (i = 0; i < 24; i++) - printf("%02x", dkp[i]); - printf("\n"); - } - krb5_free_key(dk); - } - - return (0); -} -#endif diff --git a/sys/modules/ata/atacard/Makefile b/sys/modules/ata/atacard/Makefile deleted file mode 100644 index f59f054fccc..00000000000 --- a/sys/modules/ata/atacard/Makefile +++ /dev/null @@ -1,8 +0,0 @@ - -.PATH: ${SRCTOP}/sys/dev/ata - -KMOD= atacard -SRCS= ata-card.c -SRCS+= ata_if.h bus_if.h card_if.h device_if.h pccarddevs.h - -.include diff --git a/sys/modules/geom/geom_bsd/Makefile b/sys/modules/geom/geom_bsd/Makefile deleted file mode 100644 index ce4d7de7ac3..00000000000 --- a/sys/modules/geom/geom_bsd/Makefile +++ /dev/null @@ -1,7 +0,0 @@ - -.PATH: ${SRCTOP}/sys/geom - -KMOD= geom_bsd -SRCS= geom_bsd.c geom_bsd_enc.c - -.include diff --git a/sys/modules/geom/geom_fox/Makefile b/sys/modules/geom/geom_fox/Makefile deleted file mode 100644 index 392c04b920d..00000000000 --- a/sys/modules/geom/geom_fox/Makefile +++ /dev/null @@ -1,7 +0,0 @@ - -.PATH: ${SRCTOP}/sys/geom - -KMOD= geom_fox -SRCS= geom_fox.c - -.include diff --git a/sys/modules/geom/geom_mbr/Makefile b/sys/modules/geom/geom_mbr/Makefile deleted file mode 100644 index 2944300be6a..00000000000 --- a/sys/modules/geom/geom_mbr/Makefile +++ /dev/null @@ -1,7 +0,0 @@ - -.PATH: ${SRCTOP}/sys/geom - -KMOD= geom_mbr -SRCS= geom_mbr.c geom_mbr_enc.c - -.include diff --git a/sys/modules/geom/geom_part/geom_part_vtoc8/Makefile b/sys/modules/geom/geom_part/geom_part_vtoc8/Makefile deleted file mode 100644 index 00f257673bd..00000000000 --- a/sys/modules/geom/geom_part/geom_part_vtoc8/Makefile +++ /dev/null @@ -1,9 +0,0 @@ - -.PATH: ${SRCTOP}/sys/geom/part - -KMOD= geom_part_vtoc8 -SRCS= g_part_vtoc8.c - -SRCS+= bus_if.h device_if.h g_part_if.h - -.include diff --git a/sys/modules/geom/geom_sched/Makefile b/sys/modules/geom/geom_sched/Makefile deleted file mode 100644 index c372dda86a9..00000000000 --- a/sys/modules/geom/geom_sched/Makefile +++ /dev/null @@ -1,4 +0,0 @@ - -SUBDIR= gs_sched gsched_rr gsched_delay - -.include diff --git a/sys/modules/geom/geom_sched/Makefile.inc b/sys/modules/geom/geom_sched/Makefile.inc deleted file mode 100644 index 968378c2356..00000000000 --- a/sys/modules/geom/geom_sched/Makefile.inc +++ /dev/null @@ -1,8 +0,0 @@ -# included by geom_sched children - -.PATH: ${SRCTOP}/sys/geom/sched - -# 6.x needs this path -#CFLAGS += -I${SRCTOP}/sys/geom/sched - -# .include diff --git a/sys/modules/geom/geom_sched/gs_sched/Makefile b/sys/modules/geom/geom_sched/gs_sched/Makefile deleted file mode 100644 index 0caa59b4300..00000000000 --- a/sys/modules/geom/geom_sched/gs_sched/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -KMOD= geom_sched -SRCS= g_sched.c - -# ../Makefile.inc automatically included -.include diff --git a/sys/modules/geom/geom_sched/gsched_delay/Makefile b/sys/modules/geom/geom_sched/gsched_delay/Makefile deleted file mode 100644 index deb1c1c9aae..00000000000 --- a/sys/modules/geom/geom_sched/gsched_delay/Makefile +++ /dev/null @@ -1,6 +0,0 @@ - -KMOD= gsched_delay -SRCS= gs_delay.c - -# ../Makefile.inc automatically included -.include diff --git a/sys/modules/geom/geom_sched/gsched_rr/Makefile b/sys/modules/geom/geom_sched/gsched_rr/Makefile deleted file mode 100644 index 3dc38a37429..00000000000 --- a/sys/modules/geom/geom_sched/gsched_rr/Makefile +++ /dev/null @@ -1,6 +0,0 @@ - -KMOD= gsched_rr -SRCS= gs_rr.c - -# ../Makefile.inc automatically included -.include diff --git a/sys/modules/geom/geom_sunlabel/Makefile b/sys/modules/geom/geom_sunlabel/Makefile deleted file mode 100644 index 32da27be771..00000000000 --- a/sys/modules/geom/geom_sunlabel/Makefile +++ /dev/null @@ -1,7 +0,0 @@ - -.PATH: ${SRCTOP}/sys/geom - -KMOD= geom_sunlabel -SRCS= geom_sunlabel.c geom_sunlabel_enc.c - -.include diff --git a/sys/modules/geom/geom_vol_ffs/Makefile b/sys/modules/geom/geom_vol_ffs/Makefile deleted file mode 100644 index 371542d90d4..00000000000 --- a/sys/modules/geom/geom_vol_ffs/Makefile +++ /dev/null @@ -1,7 +0,0 @@ - -.PATH: ${SRCTOP}/sys/geom - -KMOD= geom_vol_ffs -SRCS= geom_vol_ffs.c - -.include diff --git a/sys/netgraph/bluetooth/drivers/bt3c/ng_bt3c_pccard.c b/sys/netgraph/bluetooth/drivers/bt3c/ng_bt3c_pccard.c deleted file mode 100644 index a5f9fe9aa10..00000000000 --- a/sys/netgraph/bluetooth/drivers/bt3c/ng_bt3c_pccard.c +++ /dev/null @@ -1,1228 +0,0 @@ -/* - * ng_bt3c_pccard.c - */ - -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2001-2002 Maksim Yevmenkin - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * $Id: ng_bt3c_pccard.c,v 1.5 2003/04/01 18:15:21 max Exp $ - * - * XXX XXX XX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX - * - * Based on information obrained from: Jose Orlando Pereira - * and disassembled w2k driver. - * - * XXX XXX XX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX - * - */ - -#include -#include - -#include -#include - -#include -#include -#include -#include -#include -#include - -#include -#include - -#include -#include -#include - -#include -#include -#include "pccarddevs.h" - -#include -#include -#include -#include -#include -#include -#include - -/* Netgraph methods */ -static ng_constructor_t ng_bt3c_constructor; -static ng_shutdown_t ng_bt3c_shutdown; -static ng_newhook_t ng_bt3c_newhook; -static ng_connect_t ng_bt3c_connect; -static ng_disconnect_t ng_bt3c_disconnect; -static ng_rcvmsg_t ng_bt3c_rcvmsg; -static ng_rcvdata_t ng_bt3c_rcvdata; - -/* PCMCIA driver methods */ -static int bt3c_pccard_probe (device_t); -static int bt3c_pccard_attach (device_t); -static int bt3c_pccard_detach (device_t); - -static void bt3c_intr (void *); -static void bt3c_receive (bt3c_softc_p); - -static void bt3c_swi_intr (void *); -static void bt3c_forward (node_p, hook_p, void *, int); -static void bt3c_send (node_p, hook_p, void *, int); - -static void bt3c_download_firmware (bt3c_softc_p, char const *, int); - -#define bt3c_set_address(sc, address) \ -do { \ - bus_space_write_1((sc)->iot, (sc)->ioh, BT3C_ADDR_L, ((address) & 0xff)); \ - bus_space_write_1((sc)->iot, (sc)->ioh, BT3C_ADDR_H, (((address) >> 8) & 0xff)); \ -} while (0) - -#define bt3c_read_data(sc, data) \ -do { \ - (data) = bus_space_read_1((sc)->iot, (sc)->ioh, BT3C_DATA_L); \ - (data) |= ((bus_space_read_1((sc)->iot, (sc)->ioh, BT3C_DATA_H) & 0xff) << 8); \ -} while (0) - -#define bt3c_write_data(sc, data) \ -do { \ - bus_space_write_1((sc)->iot, (sc)->ioh, BT3C_DATA_L, ((data) & 0xff)); \ - bus_space_write_1((sc)->iot, (sc)->ioh, BT3C_DATA_H, (((data) >> 8) & 0xff)); \ -} while (0) - -#define bt3c_read_control(sc, data) \ -do { \ - (data) = bus_space_read_1((sc)->iot, (sc)->ioh, BT3C_CONTROL); \ -} while (0) - -#define bt3c_write_control(sc, data) \ -do { \ - bus_space_write_1((sc)->iot, (sc)->ioh, BT3C_CONTROL, (data)); \ -} while (0) - -#define bt3c_read(sc, address, data) \ -do { \ - bt3c_set_address((sc), (address)); \ - bt3c_read_data((sc), (data)); \ -} while(0) - -#define bt3c_write(sc, address, data) \ -do { \ - bt3c_set_address((sc), (address)); \ - bt3c_write_data((sc), (data)); \ -} while(0) - -static MALLOC_DEFINE(M_BT3C, "bt3c", "bt3c data structures"); - -/**************************************************************************** - **************************************************************************** - ** Netgraph specific - **************************************************************************** - ****************************************************************************/ - -/* - * Netgraph node type - */ - -/* Queue length */ -static const struct ng_parse_struct_field ng_bt3c_node_qlen_type_fields[] = -{ - { "queue", &ng_parse_int32_type, }, - { "qlen", &ng_parse_int32_type, }, - { NULL, } -}; -static const struct ng_parse_type ng_bt3c_node_qlen_type = { - &ng_parse_struct_type, - &ng_bt3c_node_qlen_type_fields -}; - -/* Stat info */ -static const struct ng_parse_struct_field ng_bt3c_node_stat_type_fields[] = -{ - { "pckts_recv", &ng_parse_uint32_type, }, - { "bytes_recv", &ng_parse_uint32_type, }, - { "pckts_sent", &ng_parse_uint32_type, }, - { "bytes_sent", &ng_parse_uint32_type, }, - { "oerrors", &ng_parse_uint32_type, }, - { "ierrors", &ng_parse_uint32_type, }, - { NULL, } -}; -static const struct ng_parse_type ng_bt3c_node_stat_type = { - &ng_parse_struct_type, - &ng_bt3c_node_stat_type_fields -}; - -static const struct ng_cmdlist ng_bt3c_cmdlist[] = { -{ - NGM_BT3C_COOKIE, - NGM_BT3C_NODE_GET_STATE, - "get_state", - NULL, - &ng_parse_uint16_type -}, -{ - NGM_BT3C_COOKIE, - NGM_BT3C_NODE_SET_DEBUG, - "set_debug", - &ng_parse_uint16_type, - NULL -}, -{ - NGM_BT3C_COOKIE, - NGM_BT3C_NODE_GET_DEBUG, - "get_debug", - NULL, - &ng_parse_uint16_type -}, -{ - NGM_BT3C_COOKIE, - NGM_BT3C_NODE_GET_QLEN, - "get_qlen", - NULL, - &ng_bt3c_node_qlen_type -}, -{ - NGM_BT3C_COOKIE, - NGM_BT3C_NODE_SET_QLEN, - "set_qlen", - &ng_bt3c_node_qlen_type, - NULL -}, -{ - NGM_BT3C_COOKIE, - NGM_BT3C_NODE_GET_STAT, - "get_stat", - NULL, - &ng_bt3c_node_stat_type -}, -{ - NGM_BT3C_COOKIE, - NGM_BT3C_NODE_RESET_STAT, - "reset_stat", - NULL, - NULL -}, -{ 0, } -}; - -static struct ng_type typestruct = { - .version = NG_ABI_VERSION, - .name = NG_BT3C_NODE_TYPE, - .constructor = ng_bt3c_constructor, - .rcvmsg = ng_bt3c_rcvmsg, - .shutdown = ng_bt3c_shutdown, - .newhook = ng_bt3c_newhook, - .connect = ng_bt3c_connect, - .rcvdata = ng_bt3c_rcvdata, - .disconnect = ng_bt3c_disconnect, - .cmdlist = ng_bt3c_cmdlist -}; - -/* - * Netgraph node constructor. Do not allow to create node of this type. - */ - -static int -ng_bt3c_constructor(node_p node) -{ - return (EINVAL); -} /* ng_bt3c_constructor */ - -/* - * Netgraph node destructor. Destroy node only when device has been detached - */ - -static int -ng_bt3c_shutdown(node_p node) -{ - bt3c_softc_p sc = (bt3c_softc_p) NG_NODE_PRIVATE(node); - - /* Let old node go */ - NG_NODE_SET_PRIVATE(node, NULL); - NG_NODE_UNREF(node); - - /* Create new fresh one if we are not going down */ - if (sc == NULL) - goto out; - - /* Create new Netgraph node */ - if (ng_make_node_common(&typestruct, &sc->node) != 0) { - device_printf(sc->dev, "Could not create Netgraph node\n"); - sc->node = NULL; - goto out; - } - - /* Name new Netgraph node */ - if (ng_name_node(sc->node, device_get_nameunit(sc->dev)) != 0) { - device_printf(sc->dev, "Could not name Netgraph node\n"); - NG_NODE_UNREF(sc->node); - sc->node = NULL; - goto out; - } - - NG_NODE_SET_PRIVATE(sc->node, sc); -out: - return (0); -} /* ng_bt3c_shutdown */ - -/* - * Create new hook. There can only be one. - */ - -static int -ng_bt3c_newhook(node_p node, hook_p hook, char const *name) -{ - bt3c_softc_p sc = (bt3c_softc_p) NG_NODE_PRIVATE(node); - - if (strcmp(name, NG_BT3C_HOOK) != 0) - return (EINVAL); - - if (sc->hook != NULL) - return (EISCONN); - - sc->hook = hook; - - return (0); -} /* ng_bt3c_newhook */ - -/* - * Connect hook. Say YEP, that's OK with me. - */ - -static int -ng_bt3c_connect(hook_p hook) -{ - bt3c_softc_p sc = (bt3c_softc_p) NG_NODE_PRIVATE(NG_HOOK_NODE(hook)); - - if (hook != sc->hook) { - sc->hook = NULL; - return (EINVAL); - } - - /* set the hook into queueing mode (for incoming (from wire) packets) */ - NG_HOOK_FORCE_QUEUE(NG_HOOK_PEER(hook)); - - return (0); -} /* ng_bt3c_connect */ - -/* - * Disconnect hook - */ - -static int -ng_bt3c_disconnect(hook_p hook) -{ - bt3c_softc_p sc = (bt3c_softc_p) NG_NODE_PRIVATE(NG_HOOK_NODE(hook)); - - /* - * We need to check for sc != NULL because we can be called from - * bt3c_pccard_detach() via ng_rmnode_self() - */ - - if (sc != NULL) { - if (hook != sc->hook) - return (EINVAL); - - IF_DRAIN(&sc->inq); - IF_DRAIN(&sc->outq); - - sc->hook = NULL; - } - - return (0); -} /* ng_bt3c_disconnect */ - -/* - * Process control message - */ - -static int -ng_bt3c_rcvmsg(node_p node, item_p item, hook_p lasthook) -{ - bt3c_softc_p sc = (bt3c_softc_p) NG_NODE_PRIVATE(node); - struct ng_mesg *msg = NULL, *rsp = NULL; - int error = 0; - - if (sc == NULL) { - NG_FREE_ITEM(item); - return (EHOSTDOWN); - } - - NGI_GET_MSG(item, msg); - - switch (msg->header.typecookie) { - case NGM_GENERIC_COOKIE: - switch (msg->header.cmd) { - case NGM_TEXT_STATUS: - NG_MKRESPONSE(rsp, msg, NG_TEXTRESPONSE, M_NOWAIT); - if (rsp == NULL) - error = ENOMEM; - else - snprintf(rsp->data, NG_TEXTRESPONSE, - "Hook: %s\n" \ - "Flags: %#x\n" \ - "Debug: %d\n" \ - "State: %d\n" \ - "IncmQ: [len:%d,max:%d]\n" \ - "OutgQ: [len:%d,max:%d]\n", - (sc->hook != NULL)? NG_BT3C_HOOK : "", - sc->flags, - sc->debug, - sc->state, - _IF_QLEN(&sc->inq), /* XXX */ - sc->inq.ifq_maxlen, /* XXX */ - _IF_QLEN(&sc->outq), /* XXX */ - sc->outq.ifq_maxlen /* XXX */ - ); - break; - - default: - error = EINVAL; - break; - } - break; - - case NGM_BT3C_COOKIE: - switch (msg->header.cmd) { - case NGM_BT3C_NODE_GET_STATE: - NG_MKRESPONSE(rsp, msg, sizeof(ng_bt3c_node_state_ep), - M_NOWAIT); - if (rsp == NULL) - error = ENOMEM; - else - *((ng_bt3c_node_state_ep *)(rsp->data)) = - sc->state; - break; - - case NGM_BT3C_NODE_SET_DEBUG: - if (msg->header.arglen != sizeof(ng_bt3c_node_debug_ep)) - error = EMSGSIZE; - else - sc->debug = - *((ng_bt3c_node_debug_ep *)(msg->data)); - break; - - case NGM_BT3C_NODE_GET_DEBUG: - NG_MKRESPONSE(rsp, msg, sizeof(ng_bt3c_node_debug_ep), - M_NOWAIT); - if (rsp == NULL) - error = ENOMEM; - else - *((ng_bt3c_node_debug_ep *)(rsp->data)) = - sc->debug; - break; - - case NGM_BT3C_NODE_GET_QLEN: - NG_MKRESPONSE(rsp, msg, sizeof(ng_bt3c_node_qlen_ep), - M_NOWAIT); - if (rsp == NULL) { - error = ENOMEM; - break; - } - - switch (((ng_bt3c_node_qlen_ep *)(msg->data))->queue) { - case NGM_BT3C_NODE_IN_QUEUE: - ((ng_bt3c_node_qlen_ep *)(rsp->data))->queue = - NGM_BT3C_NODE_IN_QUEUE; - ((ng_bt3c_node_qlen_ep *)(rsp->data))->qlen = - sc->inq.ifq_maxlen; - break; - - case NGM_BT3C_NODE_OUT_QUEUE: - ((ng_bt3c_node_qlen_ep *)(rsp->data))->queue = - NGM_BT3C_NODE_OUT_QUEUE; - ((ng_bt3c_node_qlen_ep *)(rsp->data))->qlen = - sc->outq.ifq_maxlen; - break; - - default: - NG_FREE_MSG(rsp); - error = EINVAL; - break; - } - break; - - case NGM_BT3C_NODE_SET_QLEN: - if (msg->header.arglen != sizeof(ng_bt3c_node_qlen_ep)){ - error = EMSGSIZE; - break; - } - - if (((ng_bt3c_node_qlen_ep *)(msg->data))->qlen <= 0) { - error = EINVAL; - break; - } - - switch (((ng_bt3c_node_qlen_ep *)(msg->data))->queue) { - case NGM_BT3C_NODE_IN_QUEUE: - sc->inq.ifq_maxlen = ((ng_bt3c_node_qlen_ep *) - (msg->data))->qlen; /* XXX */ - break; - - case NGM_BT3C_NODE_OUT_QUEUE: - sc->outq.ifq_maxlen = ((ng_bt3c_node_qlen_ep *) - (msg->data))->qlen; /* XXX */ - break; - - default: - error = EINVAL; - break; - } - break; - - case NGM_BT3C_NODE_GET_STAT: - NG_MKRESPONSE(rsp, msg, sizeof(ng_bt3c_node_stat_ep), - M_NOWAIT); - if (rsp == NULL) - error = ENOMEM; - else - bcopy(&sc->stat, rsp->data, - sizeof(ng_bt3c_node_stat_ep)); - break; - - case NGM_BT3C_NODE_RESET_STAT: - NG_BT3C_STAT_RESET(sc->stat); - break; - - case NGM_BT3C_NODE_DOWNLOAD_FIRMWARE: - if (msg->header.arglen < - sizeof(ng_bt3c_firmware_block_ep)) - error = EMSGSIZE; - else - bt3c_download_firmware(sc, msg->data, - msg->header.arglen); - break; - - default: - error = EINVAL; - break; - } - break; - - default: - error = EINVAL; - break; - } - - NG_RESPOND_MSG(error, node, item, rsp); - NG_FREE_MSG(msg); - - return (error); -} /* ng_bt3c_rcvmsg */ - -/* - * Process data - */ - -static int -ng_bt3c_rcvdata(hook_p hook, item_p item) -{ - bt3c_softc_p sc = (bt3c_softc_p)NG_NODE_PRIVATE(NG_HOOK_NODE(hook)); - struct mbuf *m = NULL; - int error = 0; - - if (sc == NULL) { - error = EHOSTDOWN; - goto out; - } - - if (hook != sc->hook) { - error = EINVAL; - goto out; - } - - NGI_GET_M(item, m); - - IF_LOCK(&sc->outq); - if (_IF_QFULL(&sc->outq)) { - NG_BT3C_ERR(sc->dev, -"Outgoing queue is full. Dropping mbuf, len=%d\n", m->m_pkthdr.len); - - NG_BT3C_STAT_OERROR(sc->stat); - - NG_FREE_M(m); - } else - _IF_ENQUEUE(&sc->outq, m); - IF_UNLOCK(&sc->outq); - - error = ng_send_fn(sc->node, NULL, bt3c_send, NULL, 0 /* new send */); -out: - NG_FREE_ITEM(item); - - return (error); -} /* ng_bt3c_rcvdata */ - -/**************************************************************************** - **************************************************************************** - ** PCMCIA driver specific - **************************************************************************** - ****************************************************************************/ - -/* - * PC Card (PCMCIA) probe routine - */ - -static struct pccard_product const bt3c_pccard_products[] = { - PCMCIA_CARD(3COM, 3CRWB609), - { NULL, } -}; - -static int -bt3c_pccard_probe(device_t dev) -{ - struct pccard_product const *pp = NULL; - - pp = pccard_product_lookup(dev, bt3c_pccard_products, - sizeof(bt3c_pccard_products[0]), NULL); - if (pp == NULL) - return (ENXIO); - - device_set_desc(dev, pp->pp_name); - - return (0); -} /* bt3c_pccard_probe */ - -/* - * PC Card (PCMCIA) attach routine - */ - -static int -bt3c_pccard_attach(device_t dev) -{ - bt3c_softc_p sc = (bt3c_softc_p) device_get_softc(dev); - - /* Allocate I/O ports */ - sc->iobase_rid = 0; - sc->iobase = bus_alloc_resource_anywhere(dev, SYS_RES_IOPORT, - &sc->iobase_rid, 8, RF_ACTIVE); - if (sc->iobase == NULL) { - device_printf(dev, "Could not allocate I/O ports\n"); - goto bad; - } - sc->iot = rman_get_bustag(sc->iobase); - sc->ioh = rman_get_bushandle(sc->iobase); - - /* Allocate IRQ */ - sc->irq_rid = 0; - sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irq_rid, - RF_ACTIVE); - if (sc->irq == NULL) { - device_printf(dev, "Could not allocate IRQ\n"); - goto bad; - } - - sc->irq_cookie = NULL; - if (bus_setup_intr(dev, sc->irq, INTR_TYPE_TTY, NULL, bt3c_intr, sc, - &sc->irq_cookie) != 0) { - device_printf(dev, "Could not setup ISR\n"); - goto bad; - } - - /* Attach handler to TTY SWI thread */ - sc->ith = NULL; - if (swi_add(&tty_intr_event, device_get_nameunit(dev), - bt3c_swi_intr, sc, SWI_TTY, 0, &sc->ith) < 0) { - device_printf(dev, "Could not setup SWI ISR\n"); - goto bad; - } - - /* Create Netgraph node */ - if (ng_make_node_common(&typestruct, &sc->node) != 0) { - device_printf(dev, "Could not create Netgraph node\n"); - sc->node = NULL; - goto bad; - } - - /* Name Netgraph node */ - if (ng_name_node(sc->node, device_get_nameunit(dev)) != 0) { - device_printf(dev, "Could not name Netgraph node\n"); - NG_NODE_UNREF(sc->node); - sc->node = NULL; - goto bad; - } - - sc->dev = dev; - sc->debug = NG_BT3C_WARN_LEVEL; - - sc->inq.ifq_maxlen = sc->outq.ifq_maxlen = BT3C_DEFAULTQLEN; - mtx_init(&sc->inq.ifq_mtx, "BT3C inq", NULL, MTX_DEF); - mtx_init(&sc->outq.ifq_mtx, "BT3C outq", NULL, MTX_DEF); - - sc->state = NG_BT3C_W4_PKT_IND; - sc->want = 1; - - NG_NODE_SET_PRIVATE(sc->node, sc); - - gone_in_dev(dev, 13, "pccard removed"); - - return (0); -bad: - if (sc->ith != NULL) { - swi_remove(sc->ith); - sc->ith = NULL; - } - - if (sc->irq != NULL) { - if (sc->irq_cookie != NULL) - bus_teardown_intr(dev, sc->irq, sc->irq_cookie); - - bus_release_resource(dev, SYS_RES_IRQ, - sc->irq_rid, sc->irq); - - sc->irq = NULL; - sc->irq_rid = 0; - } - - if (sc->iobase != NULL) { - bus_release_resource(dev, SYS_RES_IOPORT, - sc->iobase_rid, sc->iobase); - - sc->iobase = NULL; - sc->iobase_rid = 0; - } - - return (ENXIO); -} /* bt3c_pccacd_attach */ - -/* - * PC Card (PCMCIA) detach routine - */ - -static int -bt3c_pccard_detach(device_t dev) -{ - bt3c_softc_p sc = (bt3c_softc_p) device_get_softc(dev); - - if (sc == NULL) - return (0); - - swi_remove(sc->ith); - sc->ith = NULL; - - bus_teardown_intr(dev, sc->irq, sc->irq_cookie); - bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid, sc->irq); - sc->irq_cookie = NULL; - sc->irq = NULL; - sc->irq_rid = 0; - - bus_release_resource(dev, SYS_RES_IOPORT, sc->iobase_rid, sc->iobase); - sc->iobase = NULL; - sc->iobase_rid = 0; - - if (sc->node != NULL) { - NG_NODE_SET_PRIVATE(sc->node, NULL); - ng_rmnode_self(sc->node); - sc->node = NULL; - } - - NG_FREE_M(sc->m); - IF_DRAIN(&sc->inq); - IF_DRAIN(&sc->outq); - - mtx_destroy(&sc->inq.ifq_mtx); - mtx_destroy(&sc->outq.ifq_mtx); - - return (0); -} /* bt3c_pccacd_detach */ - -/* - * Interrupt service routine's - */ - -static void -bt3c_intr(void *context) -{ - bt3c_softc_p sc = (bt3c_softc_p) context; - u_int16_t control, status; - - if (sc == NULL || sc->ith == NULL) { - printf("%s: bogus interrupt\n", NG_BT3C_NODE_TYPE); - return; - } - - bt3c_read_control(sc, control); - if ((control & 0x80) == 0) - return; - - bt3c_read(sc, 0x7001, status); - NG_BT3C_INFO(sc->dev, "control=%#x, status=%#x\n", control, status); - - if ((status & 0xff) == 0x7f || (status & 0xff) == 0xff) { - NG_BT3C_WARN(sc->dev, "Strange status=%#x\n", status); - return; - } - - /* Receive complete */ - if (status & 0x0001) - bt3c_receive(sc); - - /* Record status and schedule SWI */ - sc->status |= status; - swi_sched(sc->ith, 0); - - /* Complete interrupt */ - bt3c_write(sc, 0x7001, 0x0000); - bt3c_write_control(sc, control); -} /* bt3c_intr */ - -/* - * Receive data - */ - -static void -bt3c_receive(bt3c_softc_p sc) -{ - u_int16_t i, count, c; - - /* Receive data from the card */ - bt3c_read(sc, 0x7006, count); - NG_BT3C_INFO(sc->dev, "The card has %d characters\n", count); - - bt3c_set_address(sc, 0x7480); - - for (i = 0; i < count; i++) { - /* Allocate new mbuf if needed */ - if (sc->m == NULL) { - sc->state = NG_BT3C_W4_PKT_IND; - sc->want = 1; - - MGETHDR(sc->m, M_NOWAIT, MT_DATA); - if (sc->m == NULL) { - NG_BT3C_ERR(sc->dev, "Could not get mbuf\n"); - NG_BT3C_STAT_IERROR(sc->stat); - - break; /* XXX lost of sync */ - } - - if (!(MCLGET(sc->m, M_NOWAIT))) { - NG_FREE_M(sc->m); - - NG_BT3C_ERR(sc->dev, "Could not get cluster\n"); - NG_BT3C_STAT_IERROR(sc->stat); - - break; /* XXX lost of sync */ - } - - sc->m->m_len = sc->m->m_pkthdr.len = 0; - } - - /* Read and append character to mbuf */ - bt3c_read_data(sc, c); - if (sc->m->m_pkthdr.len >= MCLBYTES) { - NG_BT3C_ERR(sc->dev, "Oversized frame\n"); - - NG_FREE_M(sc->m); - sc->state = NG_BT3C_W4_PKT_IND; - sc->want = 1; - - break; /* XXX lost of sync */ - } - - mtod(sc->m, u_int8_t *)[sc->m->m_len ++] = (u_int8_t) c; - sc->m->m_pkthdr.len ++; - - NG_BT3C_INFO(sc->dev, -"Got char %#x, want=%d, got=%d\n", c, sc->want, sc->m->m_pkthdr.len); - - if (sc->m->m_pkthdr.len < sc->want) - continue; /* wait for more */ - - switch (sc->state) { - /* Got packet indicator */ - case NG_BT3C_W4_PKT_IND: - NG_BT3C_INFO(sc->dev, -"Got packet indicator %#x\n", *mtod(sc->m, u_int8_t *)); - - sc->state = NG_BT3C_W4_PKT_HDR; - - /* - * Since packet indicator included in the packet - * header just set sc->want to sizeof(packet header). - */ - - switch (*mtod(sc->m, u_int8_t *)) { - case NG_HCI_ACL_DATA_PKT: - sc->want = sizeof(ng_hci_acldata_pkt_t); - break; - - case NG_HCI_SCO_DATA_PKT: - sc->want = sizeof(ng_hci_scodata_pkt_t); - break; - - case NG_HCI_EVENT_PKT: - sc->want = sizeof(ng_hci_event_pkt_t); - break; - - default: - NG_BT3C_ERR(sc->dev, -"Ignoring unknown packet type=%#x\n", *mtod(sc->m, u_int8_t *)); - - NG_BT3C_STAT_IERROR(sc->stat); - - NG_FREE_M(sc->m); - sc->state = NG_BT3C_W4_PKT_IND; - sc->want = 1; - break; - } - break; - - /* Got packet header */ - case NG_BT3C_W4_PKT_HDR: - sc->state = NG_BT3C_W4_PKT_DATA; - - switch (*mtod(sc->m, u_int8_t *)) { - case NG_HCI_ACL_DATA_PKT: - c = le16toh(mtod(sc->m, - ng_hci_acldata_pkt_t *)->length); - break; - - case NG_HCI_SCO_DATA_PKT: - c = mtod(sc->m, ng_hci_scodata_pkt_t*)->length; - break; - - case NG_HCI_EVENT_PKT: - c = mtod(sc->m, ng_hci_event_pkt_t *)->length; - break; - - default: - KASSERT(0, -("Invalid packet type=%#x\n", *mtod(sc->m, u_int8_t *))); - break; - } - - NG_BT3C_INFO(sc->dev, -"Got packet header, packet type=%#x, got so far %d, payload size=%d\n", - *mtod(sc->m, u_int8_t *), sc->m->m_pkthdr.len, - c); - - if (c > 0) { - sc->want += c; - break; - } - - /* else FALLTHROUGH and deliver frame */ - /* XXX is this true? should we deliver empty frame? */ - - /* Got packet data */ - case NG_BT3C_W4_PKT_DATA: - NG_BT3C_INFO(sc->dev, -"Got full packet, packet type=%#x, packet size=%d\n", - *mtod(sc->m, u_int8_t *), sc->m->m_pkthdr.len); - - NG_BT3C_STAT_BYTES_RECV(sc->stat, sc->m->m_pkthdr.len); - NG_BT3C_STAT_PCKTS_RECV(sc->stat); - - IF_LOCK(&sc->inq); - if (_IF_QFULL(&sc->inq)) { - NG_BT3C_ERR(sc->dev, -"Incoming queue is full. Dropping mbuf, len=%d\n", sc->m->m_pkthdr.len); - - NG_BT3C_STAT_IERROR(sc->stat); - - NG_FREE_M(sc->m); - } else { - _IF_ENQUEUE(&sc->inq, sc->m); - sc->m = NULL; - } - IF_UNLOCK(&sc->inq); - - sc->state = NG_BT3C_W4_PKT_IND; - sc->want = 1; - break; - - default: - KASSERT(0, -("Invalid node state=%d", sc->state)); - break; - } - } - - bt3c_write(sc, 0x7006, 0x0000); -} /* bt3c_receive */ - -/* - * SWI interrupt handler - * Netgraph part is handled via ng_send_fn() to avoid race with hook - * connection/disconnection - */ - -static void -bt3c_swi_intr(void *context) -{ - bt3c_softc_p sc = (bt3c_softc_p) context; - u_int16_t data; - - /* Receive complete */ - if (sc->status & 0x0001) { - sc->status &= ~0x0001; /* XXX is it safe? */ - - if (ng_send_fn(sc->node, NULL, &bt3c_forward, NULL, 0) != 0) - NG_BT3C_ALERT(sc->dev, "Could not forward frames!\n"); - } - - /* Send complete */ - if (sc->status & 0x0002) { - sc->status &= ~0x0002; /* XXX is it safe */ - - if (ng_send_fn(sc->node, NULL, &bt3c_send, NULL, 1) != 0) - NG_BT3C_ALERT(sc->dev, "Could not send frames!\n"); - } - - /* Antenna position */ - if (sc->status & 0x0020) { - sc->status &= ~0x0020; /* XXX is it safe */ - - bt3c_read(sc, 0x7002, data); - data &= 0x10; - - if (data) - sc->flags |= BT3C_ANTENNA_OUT; - else - sc->flags &= ~BT3C_ANTENNA_OUT; - - NG_BT3C_INFO(sc->dev, "Antenna %s\n", data? "OUT" : "IN"); - } -} /* bt3c_swi_intr */ - -/* - * Send all incoming frames to the upper layer - */ - -static void -bt3c_forward(node_p node, hook_p hook, void *arg1, int arg2) -{ - bt3c_softc_p sc = (bt3c_softc_p) NG_NODE_PRIVATE(node); - struct mbuf *m = NULL; - int error; - - if (sc == NULL) - return; - - if (sc->hook != NULL && NG_HOOK_IS_VALID(sc->hook)) { - for (;;) { - IF_DEQUEUE(&sc->inq, m); - if (m == NULL) - break; - - NG_SEND_DATA_ONLY(error, sc->hook, m); - if (error != 0) - NG_BT3C_STAT_IERROR(sc->stat); - } - } else { - IF_LOCK(&sc->inq); - for (;;) { - _IF_DEQUEUE(&sc->inq, m); - if (m == NULL) - break; - - NG_BT3C_STAT_IERROR(sc->stat); - NG_FREE_M(m); - } - IF_UNLOCK(&sc->inq); - } -} /* bt3c_forward */ - -/* - * Send more data to the device. Must be called when node is locked - */ - -static void -bt3c_send(node_p node, hook_p hook, void *arg, int completed) -{ - bt3c_softc_p sc = (bt3c_softc_p) NG_NODE_PRIVATE(node); - struct mbuf *m = NULL; - int i, wrote, len; - - if (sc == NULL) - return; - - if (completed) - sc->flags &= ~BT3C_XMIT; - - if (sc->flags & BT3C_XMIT) - return; - - bt3c_set_address(sc, 0x7080); - - for (wrote = 0; wrote < BT3C_FIFO_SIZE; ) { - IF_DEQUEUE(&sc->outq, m); - if (m == NULL) - break; - - while (m != NULL) { - len = min((BT3C_FIFO_SIZE - wrote), m->m_len); - - for (i = 0; i < len; i++) - bt3c_write_data(sc, m->m_data[i]); - - wrote += len; - m->m_data += len; - m->m_len -= len; - - if (m->m_len > 0) - break; - - m = m_free(m); - } - - if (m != NULL) { - IF_PREPEND(&sc->outq, m); - break; - } - - NG_BT3C_STAT_PCKTS_SENT(sc->stat); - } - - if (wrote > 0) { - NG_BT3C_INFO(sc->dev, "Wrote %d bytes\n", wrote); - NG_BT3C_STAT_BYTES_SENT(sc->stat, wrote); - - bt3c_write(sc, 0x7005, wrote); - sc->flags |= BT3C_XMIT; - } -} /* bt3c_send */ - -/* - * Download chip firmware - */ - -static void -bt3c_download_firmware(bt3c_softc_p sc, char const *firmware, int firmware_size) -{ - ng_bt3c_firmware_block_ep const *block = NULL; - u_int16_t const *data = NULL; - int i, size; - u_int8_t c; - - /* Reset */ - device_printf(sc->dev, "Reseting the card...\n"); - bt3c_write(sc, 0x8040, 0x0404); - bt3c_write(sc, 0x8040, 0x0400); - DELAY(1); - - bt3c_write(sc, 0x8040, 0x0404); - DELAY(17); - - /* Download firmware */ - device_printf(sc->dev, "Starting firmware download process...\n"); - - for (size = 0; size < firmware_size; ) { - block = (ng_bt3c_firmware_block_ep const *)(firmware + size); - data = (u_int16_t const *)(block + 1); - - if (bootverbose) - device_printf(sc->dev, "Download firmware block, " \ - "address=%#08x, size=%d words, aligment=%d\n", - block->block_address, block->block_size, - block->block_alignment); - - bt3c_set_address(sc, block->block_address); - for (i = 0; i < block->block_size; i++) - bt3c_write_data(sc, data[i]); - - size += (sizeof(*block) + (block->block_size * 2) + - block->block_alignment); - } - - DELAY(17); - device_printf(sc->dev, "Firmware download process complete\n"); - - /* Boot */ - device_printf(sc->dev, "Starting the card...\n"); - bt3c_set_address(sc, 0x3000); - bt3c_read_control(sc, c); - bt3c_write_control(sc, (c | 0x40)); - DELAY(17); - - /* Clear registers */ - device_printf(sc->dev, "Clearing card registers...\n"); - bt3c_write(sc, 0x7006, 0x0000); - bt3c_write(sc, 0x7005, 0x0000); - bt3c_write(sc, 0x7001, 0x0000); - DELAY(1000); -} /* bt3c_download_firmware */ - -/**************************************************************************** - **************************************************************************** - ** Driver module - **************************************************************************** - ****************************************************************************/ - -/* - * PC Card (PCMCIA) driver - */ - -static device_method_t bt3c_pccard_methods[] = { - /* Device interface */ - DEVMETHOD(device_probe, bt3c_pccard_probe), - DEVMETHOD(device_attach, bt3c_pccard_attach), - DEVMETHOD(device_detach, bt3c_pccard_detach), - - { 0, 0 } -}; - -static driver_t bt3c_pccard_driver = { - NG_BT3C_NODE_TYPE, - bt3c_pccard_methods, - sizeof(bt3c_softc_t) -}; - -static devclass_t bt3c_devclass; - - -/* - * Load/Unload the driver module - */ - -static int -bt3c_modevent(module_t mod, int event, void *data) -{ - int error; - - switch (event) { - case MOD_LOAD: - error = ng_newtype(&typestruct); - if (error != 0) - printf("%s: Could not register Netgraph node type, " \ - "error=%d\n", NG_BT3C_NODE_TYPE, error); - break; - - case MOD_UNLOAD: - error = ng_rmtype(&typestruct); - break; - - default: - error = EOPNOTSUPP; - break; - } - - return (error); -} /* bt3c_modevent */ - -DRIVER_MODULE(bt3c, pccard, bt3c_pccard_driver, bt3c_devclass, bt3c_modevent,0); -MODULE_VERSION(ng_bt3c, NG_BLUETOOTH_VERSION); -MODULE_DEPEND(ng_bt3c, netgraph, NG_ABI_VERSION, NG_ABI_VERSION,NG_ABI_VERSION); -PCCARD_PNP_INFO(bt3c_pccard_products); diff --git a/sys/netgraph/bluetooth/drivers/bt3c/ng_bt3c_var.h b/sys/netgraph/bluetooth/drivers/bt3c/ng_bt3c_var.h deleted file mode 100644 index 0aac476d3b8..00000000000 --- a/sys/netgraph/bluetooth/drivers/bt3c/ng_bt3c_var.h +++ /dev/null @@ -1,108 +0,0 @@ -/* - * ng_bt3c_var.h - */ - -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2001-2002 Maksim Yevmenkin - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * $Id: ng_bt3c_var.h,v 1.1 2002/11/24 19:46:54 max Exp $ - * - * XXX XXX XX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX - * - * Based on information obrained from: Jose Orlando Pereira - * and disassembled w2k driver. - * - * XXX XXX XX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX - * - */ - -#ifndef _NG_BT3C_VAR_H_ -#define _NG_BT3C_VAR_H_ - -/* Debug printf's */ -#define NG_BT3C_ALERT if (sc->debug >= NG_BT3C_ALERT_LEVEL) device_printf -#define NG_BT3C_ERR if (sc->debug >= NG_BT3C_ERR_LEVEL) device_printf -#define NG_BT3C_WARN if (sc->debug >= NG_BT3C_WARN_LEVEL) device_printf -#define NG_BT3C_INFO if (sc->debug >= NG_BT3C_INFO_LEVEL) device_printf - -/* Device registers */ -#define BT3C_DATA_L 0x00 /* data low byte */ -#define BT3C_DATA_H 0x01 /* high byte */ -#define BT3C_ADDR_L 0x02 /* address low byte */ -#define BT3C_ADDR_H 0x03 /* high byte */ -#define BT3C_CONTROL 0x04 /* control */ - -#define BT3C_FIFO_SIZE 256 - -/* Device softc structure */ -struct bt3c_softc { - /* Device specific */ - device_t dev; /* pointer back to device */ - int iobase_rid; /* iobase RID */ - struct resource *iobase; /* iobase */ - bus_space_tag_t iot; /* I/O tag */ - bus_space_handle_t ioh; /* I/O handle */ - int irq_rid; /* irq RID */ - struct resource *irq; /* irq */ - void *irq_cookie; /* irq cookie */ - - /* Netgraph specific */ - node_p node; /* pointer back to node */ - hook_p hook; /* hook */ - - ng_bt3c_node_debug_ep debug; /* debug level */ - u_int16_t flags; /* device flags */ -#define BT3C_ANTENNA_OUT (1 << 0) /* antena is out */ -#define BT3C_XMIT (1 << 1) /* xmit in progress */ - - ng_bt3c_node_state_ep state; /* receiving state */ - - ng_bt3c_node_stat_ep stat; /* statistic */ -#define NG_BT3C_STAT_PCKTS_SENT(s) (s).pckts_sent ++ -#define NG_BT3C_STAT_BYTES_SENT(s, n) (s).bytes_sent += (n) -#define NG_BT3C_STAT_PCKTS_RECV(s) (s).pckts_recv ++ -#define NG_BT3C_STAT_BYTES_RECV(s, n) (s).bytes_recv += (n) -#define NG_BT3C_STAT_OERROR(s) (s).oerrors ++ -#define NG_BT3C_STAT_IERROR(s) (s).ierrors ++ -#define NG_BT3C_STAT_RESET(s) bzero(&(s), sizeof((s))) - - u_int32_t status; /* from ISR */ - void *ith; /* ithread handler */ - - struct mbuf *m; /* current frame */ - u_int32_t want; /* # of chars we want */ - - struct ifqueue inq; /* queue of incoming mbuf's */ - struct ifqueue outq; /* queue of outgoing mbuf's */ -#define BT3C_DEFAULTQLEN 12 /* XXX max. size of out queue */ -}; - -typedef struct bt3c_softc bt3c_softc_t; -typedef struct bt3c_softc * bt3c_softc_p; - -#endif /* ndef _NG_BT3C_VAR_H_ */ - diff --git a/sys/netgraph/bluetooth/include/ng_bt3c.h b/sys/netgraph/bluetooth/include/ng_bt3c.h deleted file mode 100644 index c29de4835b4..00000000000 --- a/sys/netgraph/bluetooth/include/ng_bt3c.h +++ /dev/null @@ -1,112 +0,0 @@ -/* - * ng_bt3c.h - */ - -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2001-2002 Maksim Yevmenkin - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * $Id: ng_bt3c.h,v 1.1 2002/11/24 19:47:05 max Exp $ - * - * XXX XXX XX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX - * - * Based on information obrained from: Jose Orlando Pereira - * and disassembled w2k driver. - * - * XXX XXX XX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX - * - */ - -#ifndef _NG_BT3C_H_ -#define _NG_BT3C_H_ - -/************************************************************************** - ************************************************************************** - ** Netgraph node hook name, type name and type cookie and commands - ************************************************************************** - **************************************************************************/ - -#define NG_BT3C_NODE_TYPE "btccc" /* XXX can't use bt3c in pccard.conf */ -#define NG_BT3C_HOOK "hook" - -#define NGM_BT3C_COOKIE 1014752016 - -/* Debug levels */ -#define NG_BT3C_ALERT_LEVEL 1 -#define NG_BT3C_ERR_LEVEL 2 -#define NG_BT3C_WARN_LEVEL 3 -#define NG_BT3C_INFO_LEVEL 4 - -/* Node states */ -#define NG_BT3C_W4_PKT_IND 1 /* wait for packet indicator */ -#define NG_BT3C_W4_PKT_HDR 2 /* wait for packet header */ -#define NG_BT3C_W4_PKT_DATA 3 /* wait for packet data */ - -/************************************************************************** - ************************************************************************** - ** BT3C node command/event parameters - ************************************************************************** - **************************************************************************/ - -#define NGM_BT3C_NODE_GET_STATE 1 /* get node state */ -typedef u_int16_t ng_bt3c_node_state_ep; - -#define NGM_BT3C_NODE_SET_DEBUG 2 /* set debug level */ -#define NGM_BT3C_NODE_GET_DEBUG 3 /* get debug level */ -typedef u_int16_t ng_bt3c_node_debug_ep; - -#define NGM_BT3C_NODE_GET_QLEN 4 /* get queue length */ -#define NGM_BT3C_NODE_SET_QLEN 5 /* set queue length */ -typedef struct { - int32_t queue; /* queue index */ -#define NGM_BT3C_NODE_IN_QUEUE 1 /* incoming queue */ -#define NGM_BT3C_NODE_OUT_QUEUE 2 /* outgoing queue */ - - int32_t qlen; /* queue length */ -} ng_bt3c_node_qlen_ep; - -#define NGM_BT3C_NODE_GET_STAT 6 /* get statistic */ -typedef struct { - u_int32_t pckts_recv; /* # of packets received */ - u_int32_t bytes_recv; /* # of bytes received */ - u_int32_t pckts_sent; /* # of packets sent */ - u_int32_t bytes_sent; /* # of bytes sent */ - u_int32_t oerrors; /* # of output errors */ - u_int32_t ierrors; /* # of input errors */ -} ng_bt3c_node_stat_ep; - -#define NGM_BT3C_NODE_RESET_STAT 7 /* reset statistic */ - -#define NGM_BT3C_NODE_DOWNLOAD_FIRMWARE 8 /* download firmware */ - -typedef struct { - u_int32_t block_address; - u_int16_t block_size; /* in words */ - u_int16_t block_alignment; /* in bytes */ -} ng_bt3c_firmware_block_ep; - -#endif /* ndef _NG_BT3C_H_ */ - diff --git a/sys/ofed/include/rdma/ib_verbs_compat.h b/sys/ofed/include/rdma/ib_verbs_compat.h deleted file mode 100644 index 85550fd81e7..00000000000 --- a/sys/ofed/include/rdma/ib_verbs_compat.h +++ /dev/null @@ -1,582 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2018, Mellanox Technologies, Ltd. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * $FreeBSD: stable/11/sys/ofed/include/rdma/ib_verbs_compat.h 331769 2018-03-30 18:06:29Z hselasky $ - */ - -#if !defined(IB_VERBS_COMPAT_H) -#define IB_VERBS_COMPAT_H - -#include - -enum ib_device_attr_comp_mask { - IB_DEVICE_ATTR_WITH_TIMESTAMP_MASK = 1ULL << 1, - IB_DEVICE_ATTR_WITH_HCA_CORE_CLOCK = 1ULL << 2 -}; - -struct ib_protocol_stats { - /* TBD... */ -}; - -struct iw_protocol_stats { - u64 ipInReceives; - u64 ipInHdrErrors; - u64 ipInTooBigErrors; - u64 ipInNoRoutes; - u64 ipInAddrErrors; - u64 ipInUnknownProtos; - u64 ipInTruncatedPkts; - u64 ipInDiscards; - u64 ipInDelivers; - u64 ipOutForwDatagrams; - u64 ipOutRequests; - u64 ipOutDiscards; - u64 ipOutNoRoutes; - u64 ipReasmTimeout; - u64 ipReasmReqds; - u64 ipReasmOKs; - u64 ipReasmFails; - u64 ipFragOKs; - u64 ipFragFails; - u64 ipFragCreates; - u64 ipInMcastPkts; - u64 ipOutMcastPkts; - u64 ipInBcastPkts; - u64 ipOutBcastPkts; - - u64 tcpRtoAlgorithm; - u64 tcpRtoMin; - u64 tcpRtoMax; - u64 tcpMaxConn; - u64 tcpActiveOpens; - u64 tcpPassiveOpens; - u64 tcpAttemptFails; - u64 tcpEstabResets; - u64 tcpCurrEstab; - u64 tcpInSegs; - u64 tcpOutSegs; - u64 tcpRetransSegs; - u64 tcpInErrs; - u64 tcpOutRsts; -}; - -union rdma_protocol_stats { - struct ib_protocol_stats ib; - struct iw_protocol_stats iw; -}; - -enum ib_mr_create_flags { - IB_MR_SIGNATURE_EN = 1, -}; - -struct ib_mr_init_attr { - int max_reg_descriptors; - u32 flags; -}; - -enum ib_qpg_type { - IB_QPG_NONE = 0, - IB_QPG_PARENT = (1 << 0), - IB_QPG_CHILD_RX = (1 << 1), - IB_QPG_CHILD_TX = (1 << 2) -}; - -struct ib_qpg_init_attrib { - u32 tss_child_count; - u32 rss_child_count; -}; - -enum { - IB_DCT_CREATE_FLAG_RCV_INLINE = 1 << 0, - IB_DCT_CREATE_FLAGS_MASK = IB_DCT_CREATE_FLAG_RCV_INLINE, -}; - -struct ib_dct_init_attr { - struct ib_pd *pd; - struct ib_cq *cq; - struct ib_srq *srq; - u64 dc_key; - u8 port; - u32 access_flags; - u8 min_rnr_timer; - u8 tclass; - u32 flow_label; - enum ib_mtu mtu; - u8 pkey_index; - u8 gid_index; - u8 hop_limit; - u32 create_flags; -}; - -struct ib_dct_attr { - u64 dc_key; - u8 port; - u32 access_flags; - u8 min_rnr_timer; - u8 tclass; - u32 flow_label; - enum ib_mtu mtu; - u8 pkey_index; - u8 gid_index; - u8 hop_limit; - u32 key_violations; - u8 state; -}; - -struct ib_fast_reg_page_list { - struct ib_device *device; - u64 *page_list; - unsigned int max_page_list_len; -}; - -struct ib_mw_bind_info { - struct ib_mr *mr; - u64 addr; - u64 length; - int mw_access_flags; -}; - -struct ib_mr_attr { - struct ib_pd *pd; - u64 device_virt_addr; - u64 size; - int mr_access_flags; - u32 lkey; - u32 rkey; -}; - -struct ib_mw_bind { - u64 wr_id; - int send_flags; - struct ib_mw_bind_info bind_info; -}; - -enum ib_cq_attr_mask { - IB_CQ_MODERATION = (1 << 0), - IB_CQ_CAP_FLAGS = (1 << 1) -}; - -enum ib_cq_cap_flags { - IB_CQ_IGNORE_OVERRUN = (1 << 0) -}; - -struct ib_cq_attr { - struct { - u16 cq_count; - u16 cq_period; - } moderation; - u32 cq_cap_flags; -}; - -struct ib_dct { - struct ib_device *device; - struct ib_uobject *uobject; - struct ib_pd *pd; - struct ib_cq *cq; - struct ib_srq *srq; - u32 dct_num; -}; - -enum verbs_values_mask { - IBV_VALUES_HW_CLOCK = 1 << 0 -}; - -struct ib_device_values { - int values_mask; - uint64_t hwclock; -}; - -#define IB_WR_FAST_REG_MR -2 /* not implemented */ - -struct ib_send_wr_compat { - union { - /* - * NOTE: The following structure must be kept in sync - * with "struct ib_send_wr": - */ - struct { - struct ib_send_wr_compat *next; - union { - u64 wr_id; - struct ib_cqe *wr_cqe; - }; - struct ib_sge *sg_list; - int num_sge; - enum ib_wr_opcode opcode; - int send_flags; - union { - __be32 imm_data; - u32 invalidate_rkey; - } ex; - }; - union { - struct ib_rdma_wr rdma; - struct ib_atomic_wr atomic; - struct ib_ud_wr ud; - struct ib_sig_handover_wr sig_handover; - struct { - struct ib_send_wr wr; - u64 iova_start; - struct ib_fast_reg_page_list *page_list; - unsigned int page_shift; - unsigned int page_list_len; - u32 length; - int access_flags; - u32 rkey; - } fast_reg; - struct { - struct ib_send_wr wr; - int npages; - int access_flags; - u32 mkey; - struct ib_pd *pd; - u64 virt_addr; - u64 length; - int page_shift; - } umr; - struct { - struct ib_send_wr wr; - struct ib_mw *mw; - /* The new rkey for the memory window. */ - u32 rkey; - struct ib_mw_bind_info bind_info; - } bind_mw; - } wr; - }; - u32 xrc_remote_srq_num; /* XRC TGT QPs only */ -}; - -static inline int -ib_post_send_compat(struct ib_qp *qp, - struct ib_send_wr_compat *send_wr, - struct ib_send_wr_compat **bad_send_wr) -{ - return (ib_post_send(qp, (struct ib_send_wr *)send_wr, - (struct ib_send_wr **)bad_send_wr)); -} - -#undef ib_post_send -#define ib_post_send(...) \ - ib_post_send_compat(__VA_ARGS__) - -#define ib_send_wr \ - ib_send_wr_compat - -static inline int -ib_query_device_compat(struct ib_device *device, - struct ib_device_attr *device_attr) -{ - *device_attr = device->attrs; - return (0); -} - -#undef ib_query_device -#define ib_query_device(...) \ - ib_query_device_compat(__VA_ARGS__) - -static inline int -ib_query_gid_compat(struct ib_device *device, - u8 port_num, int index, union ib_gid *gid) -{ - return (ib_query_gid(device, port_num, index, gid, NULL)); -} - -#undef ib_query_gid -#define ib_query_gid(...) \ - ib_query_gid_compat(__VA_ARGS__) - -static inline int -ib_find_gid_compat(struct ib_device *device, union ib_gid *gid, - u8 * port_num, u16 * index) -{ - return (ib_find_gid(device, gid, IB_GID_TYPE_IB, NULL, port_num, index)); -} - -#undef ib_find_gid -#define ib_find_gid(...) \ - ib_find_gid_compat(__VA_ARGS__) - -static inline struct ib_pd * -ib_alloc_pd_compat(struct ib_device *device) -{ - return (ib_alloc_pd(device, 0)); -} - -#undef ib_alloc_pd -#define ib_alloc_pd(...) \ - ib_alloc_pd_compat(__VA_ARGS__) - -static inline struct ib_cq * -ib_create_cq_compat(struct ib_device *device, - ib_comp_handler comp_handler, - void (*event_handler) (struct ib_event *, void *), - void *cq_context, int cqe, int comp_vector) -{ - const struct ib_cq_init_attr cq_attr = {.cqe = cqe,.comp_vector = comp_vector}; - - return (ib_create_cq(device, comp_handler, event_handler, cq_context, &cq_attr)); -} - -#undef ib_create_cq -#define ib_create_cq(...) \ - ib_create_cq_compat(__VA_ARGS__) - -static inline int -ib_modify_cq_compat(struct ib_cq *cq, - struct ib_cq_attr *cq_attr, - int cq_attr_mask) -{ - if (cq_attr_mask & IB_CQ_MODERATION) { - return (ib_modify_cq(cq, cq_attr->moderation.cq_count, - cq_attr->moderation.cq_period)); - } else { - return (0); - } -} - -#undef ib_modify_cq -#define ib_modify_cq(...) \ - ib_modify_cq_compat(__VA_ARGS__) - -static inline struct ib_mr * -ib_get_dma_mr(struct ib_pd *pd, int mr_access_flags) -{ - struct ib_mr *mr; - int err; - - err = ib_check_mr_access(mr_access_flags); - if (err) - return ERR_PTR(err); - - if (!pd->device->get_dma_mr) - return ERR_PTR(-ENOSYS); - - mr = pd->device->get_dma_mr(pd, mr_access_flags); - if (IS_ERR(mr)) - return ERR_CAST(mr); - - mr->device = pd->device; - mr->pd = pd; - mr->uobject = NULL; - mr->need_inval = false; - atomic_inc(&pd->usecnt); - - return (mr); -} - -static inline struct ib_mr * -ib_reg_phys_mr(struct ib_pd *pd, - struct ib_phys_buf *phys_buf_array, - int num_phys_buf, - int mr_access_flags, - u64 * iova_start) -{ - struct ib_mr *mr; - int err; - - err = ib_check_mr_access(mr_access_flags); - if (err) - return ERR_PTR(err); - - if (!pd->device->reg_phys_mr) - return ERR_PTR(-ENOSYS); - - mr = pd->device->reg_phys_mr(pd, phys_buf_array, num_phys_buf, - mr_access_flags, iova_start); - if (IS_ERR(mr)) - return ERR_CAST(mr); - - mr->device = pd->device; - mr->pd = pd; - mr->uobject = NULL; - atomic_inc(&pd->usecnt); - - return (mr); -} - -static inline int -ib_rereg_phys_mr(struct ib_mr *mr, - int mr_rereg_mask, - struct ib_pd *pd, - struct ib_phys_buf *phys_buf_array, - int num_phys_buf, - int mr_access_flags, - u64 * iova_start) -{ - return (-EOPNOTSUPP); -} - -static inline int -ib_query_mr(struct ib_mr *mr, struct ib_mr_attr *mr_attr) -{ - return (-EOPNOTSUPP); -} - -static inline struct ib_mr * -ib_create_mr(struct ib_pd *pd, - struct ib_mr_init_attr *mr_init_attr) -{ - return (ERR_PTR(-ENOSYS)); -} - -static inline int -ib_destroy_mr(struct ib_mr *mr) -{ - return (-EOPNOTSUPP); -} - -static inline struct ib_mr * -ib_alloc_fast_reg_mr(struct ib_pd *pd, int max_page_list_len) -{ - return (ERR_PTR(-ENOSYS)); -} - -static inline struct ib_fast_reg_page_list * -ib_alloc_fast_reg_page_list(struct ib_device *device, int page_list_len) -{ - return (ERR_PTR(-ENOSYS)); -} - -static inline void -ib_free_fast_reg_page_list(struct ib_fast_reg_page_list *page_list) -{ - -} - -static inline struct ib_mw * -ib_alloc_mw(struct ib_pd *pd, enum ib_mw_type type) -{ - struct ib_mw *mw; - - if (!pd->device->alloc_mw) - return ERR_PTR(-ENOSYS); - - mw = pd->device->alloc_mw(pd, type, NULL); - if (!IS_ERR(mw)) { - mw->device = pd->device; - mw->pd = pd; - mw->uobject = NULL; - mw->type = type; - atomic_inc(&pd->usecnt); - } - return (mw); -} - -static inline int -ib_bind_mw(struct ib_qp *qp, - struct ib_mw *mw, - struct ib_mw_bind *mw_bind) -{ - return (-EOPNOTSUPP); -} - -static inline int -ib_dealloc_mw(struct ib_mw *mw) -{ - struct ib_pd *pd; - int ret; - - pd = mw->pd; - ret = mw->device->dealloc_mw(mw); - if (!ret) - atomic_dec(&pd->usecnt); - return (ret); -} - -static inline struct ib_dct * -ib_create_dct(struct ib_pd *pd, struct ib_dct_init_attr *attr, - struct ib_udata *udata) -{ - return (ERR_PTR(-ENOSYS)); -} - -static inline int -ib_destroy_dct(struct ib_dct *dct) -{ - return (-EOPNOTSUPP); -} - -static inline int -ib_query_dct(struct ib_dct *dct, struct ib_dct_attr *attr) -{ - return (-EOPNOTSUPP); -} - -static inline int -ib_query_values(struct ib_device *device, - int q_values, struct ib_device_values *values) -{ - return (-EOPNOTSUPP); -} - -static inline void -ib_active_speed_enum_to_rate(u8 active_speed, - int *rate, - char **speed) -{ - switch (active_speed) { - case IB_SPEED_DDR: - *speed = " DDR"; - *rate = 50; - break; - case IB_SPEED_QDR: - *speed = " QDR"; - *rate = 100; - break; - case IB_SPEED_FDR10: - *speed = " FDR10"; - *rate = 100; - break; - case IB_SPEED_FDR: - *speed = " FDR"; - *rate = 140; - break; - case IB_SPEED_EDR: - *speed = " EDR"; - *rate = 250; - break; - case IB_SPEED_SDR: - default: /* default to SDR for invalid rates */ - *rate = 25; - break; - } -} - -#include - -static inline struct rdma_cm_id * -rdma_create_id_compat(rdma_cm_event_handler event_handler, - void *context, enum rdma_port_space ps, - enum ib_qp_type qp_type) -{ - return (rdma_create_id(&init_net, event_handler, context, ps, qp_type)); -} - -#undef rdma_create_id -#define rdma_create_id(...) \ - rdma_create_id_compat(__VA_ARGS__) - -#endif /* IB_VERBS_COMPAT_H */ diff --git a/sys/powerpc/aim/isa3_hashtb.c b/sys/powerpc/aim/isa3_hashtb.c deleted file mode 100644 index 0b153f243c4..00000000000 --- a/sys/powerpc/aim/isa3_hashtb.c +++ /dev/null @@ -1,630 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD AND 4-Clause-BSD - * - * Copyright (c) 2001 The NetBSD Foundation, Inc. - * All rights reserved. - * - * This code is derived from software contributed to The NetBSD Foundation - * by Matt Thomas of Allegro Networks, Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS - * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ -/*- - * Copyright (C) 1995, 1996 Wolfgang Solfrank. - * Copyright (C) 1995, 1996 TooLs GmbH. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by TooLs GmbH. - * 4. The name of TooLs GmbH may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF - * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $ - */ -/*- - * Copyright (C) 2001 Benno Rice. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF - * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include - -/* - * Native 64-bit page table operations for running without a hypervisor. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include "mmu_oea64.h" -#include "mmu_if.h" -#include "moea64_if.h" - -#define PTESYNC() __asm __volatile("ptesync"); -#define TLBSYNC() __asm __volatile("tlbsync; ptesync"); -#define SYNC() __asm __volatile("sync"); -#define EIEIO() __asm __volatile("eieio"); - -#define VSID_HASH_MASK 0x0000007fffffffffULL - -/* POWER9 only permits a 64k partition table size. */ -#define PART_SIZE 0x10000 - -static __inline void -TLBIE(uint64_t vpn) -{ - vpn <<= ADDR_PIDX_SHFT; - - __asm __volatile("tlbie %0" :: "r"(vpn) : "memory"); - __asm __volatile("eieio; tlbsync; ptesync" ::: "memory"); -} - -#define DISABLE_TRANS(msr) msr = mfmsr(); mtmsr(msr & ~PSL_DR) -#define ENABLE_TRANS(msr) mtmsr(msr) - -/* - * PTEG data. - */ -static volatile struct pate *isa3_part_table; -static volatile struct lpte *isa3_hashtb_pteg_table; -static struct rwlock isa3_hashtb_eviction_lock; - -/* - * PTE calls. - */ -static int isa3_hashtb_pte_insert(mmu_t, struct pvo_entry *); -static int64_t isa3_hashtb_pte_synch(mmu_t, struct pvo_entry *); -static int64_t isa3_hashtb_pte_clear(mmu_t, struct pvo_entry *, uint64_t); -static int64_t isa3_hashtb_pte_replace(mmu_t, struct pvo_entry *, int); -static int64_t isa3_hashtb_pte_unset(mmu_t mmu, struct pvo_entry *); - -/* - * Utility routines. - */ -static void isa3_hashtb_bootstrap(mmu_t mmup, - vm_offset_t kernelstart, vm_offset_t kernelend); -static void isa3_hashtb_cpu_bootstrap(mmu_t, int ap); -static void tlbia(void); - -static mmu_method_t isa3_hashtb_methods[] = { - /* Internal interfaces */ - MMUMETHOD(mmu_bootstrap, isa3_hashtb_bootstrap), - MMUMETHOD(mmu_cpu_bootstrap, isa3_hashtb_cpu_bootstrap), - - MMUMETHOD(moea64_pte_synch, isa3_hashtb_pte_synch), - MMUMETHOD(moea64_pte_clear, isa3_hashtb_pte_clear), - MMUMETHOD(moea64_pte_unset, isa3_hashtb_pte_unset), - MMUMETHOD(moea64_pte_replace, isa3_hashtb_pte_replace), - MMUMETHOD(moea64_pte_insert, isa3_hashtb_pte_insert), - - { 0, 0 } -}; - -MMU_DEF_INHERIT(isa3_mmu_native, MMU_TYPE_P9H, isa3_hashtb_methods, - 0, oea64_mmu); - -static int64_t -isa3_hashtb_pte_synch(mmu_t mmu, struct pvo_entry *pvo) -{ - volatile struct lpte *pt = isa3_hashtb_pteg_table + pvo->pvo_pte.slot; - struct lpte properpt; - uint64_t ptelo; - - PMAP_LOCK_ASSERT(pvo->pvo_pmap, MA_OWNED); - - moea64_pte_from_pvo(pvo, &properpt); - - rw_rlock(&isa3_hashtb_eviction_lock); - if ((be64toh(pt->pte_hi) & LPTE_AVPN_MASK) != - (properpt.pte_hi & LPTE_AVPN_MASK)) { - /* Evicted */ - rw_runlock(&isa3_hashtb_eviction_lock); - return (-1); - } - - PTESYNC(); - ptelo = be64toh(pt->pte_lo); - - rw_runlock(&isa3_hashtb_eviction_lock); - - return (ptelo & (LPTE_REF | LPTE_CHG)); -} - -static int64_t -isa3_hashtb_pte_clear(mmu_t mmu, struct pvo_entry *pvo, uint64_t ptebit) -{ - volatile struct lpte *pt = isa3_hashtb_pteg_table + pvo->pvo_pte.slot; - struct lpte properpt; - uint64_t ptelo; - - PMAP_LOCK_ASSERT(pvo->pvo_pmap, MA_OWNED); - - moea64_pte_from_pvo(pvo, &properpt); - - rw_rlock(&isa3_hashtb_eviction_lock); - if ((be64toh(pt->pte_hi) & LPTE_AVPN_MASK) != - (properpt.pte_hi & LPTE_AVPN_MASK)) { - /* Evicted */ - rw_runlock(&isa3_hashtb_eviction_lock); - return (-1); - } - - if (ptebit == LPTE_REF) { - /* See "Resetting the Reference Bit" in arch manual */ - PTESYNC(); - /* 2-step here safe: precision is not guaranteed */ - ptelo = be64toh(pt->pte_lo); - - /* One-byte store to avoid touching the C bit */ - ((volatile uint8_t *)(&pt->pte_lo))[6] = -#if BYTE_ORDER == BIG_ENDIAN - ((uint8_t *)(&properpt.pte_lo))[6]; -#else - ((uint8_t *)(&properpt.pte_lo))[1]; -#endif - rw_runlock(&isa3_hashtb_eviction_lock); - - critical_enter(); - TLBIE(pvo->pvo_vpn); - critical_exit(); - } else { - rw_runlock(&isa3_hashtb_eviction_lock); - ptelo = isa3_hashtb_pte_unset(mmu, pvo); - isa3_hashtb_pte_insert(mmu, pvo); - } - - return (ptelo & (LPTE_REF | LPTE_CHG)); -} - -static int64_t -isa3_hashtb_pte_unset(mmu_t mmu, struct pvo_entry *pvo) -{ - volatile struct lpte *pt = isa3_hashtb_pteg_table + pvo->pvo_pte.slot; - struct lpte properpt; - uint64_t ptelo; - - moea64_pte_from_pvo(pvo, &properpt); - - rw_rlock(&isa3_hashtb_eviction_lock); - if ((be64toh(pt->pte_hi & LPTE_AVPN_MASK)) != - (properpt.pte_hi & LPTE_AVPN_MASK)) { - /* Evicted */ - moea64_pte_overflow--; - rw_runlock(&isa3_hashtb_eviction_lock); - return (-1); - } - - /* - * Invalidate the pte, briefly locking it to collect RC bits. No - * atomics needed since this is protected against eviction by the lock. - */ - isync(); - critical_enter(); - pt->pte_hi = be64toh((pt->pte_hi & ~LPTE_VALID) | LPTE_LOCKED); - PTESYNC(); - TLBIE(pvo->pvo_vpn); - ptelo = be64toh(pt->pte_lo); - *((volatile int32_t *)(&pt->pte_hi) + 1) = 0; /* Release lock */ - critical_exit(); - rw_runlock(&isa3_hashtb_eviction_lock); - - /* Keep statistics */ - moea64_pte_valid--; - - return (ptelo & (LPTE_CHG | LPTE_REF)); -} - -static int64_t -isa3_hashtb_pte_replace(mmu_t mmu, struct pvo_entry *pvo, int flags) -{ - volatile struct lpte *pt = isa3_hashtb_pteg_table + pvo->pvo_pte.slot; - struct lpte properpt; - int64_t ptelo; - - if (flags == 0) { - /* Just some software bits changing. */ - moea64_pte_from_pvo(pvo, &properpt); - - rw_rlock(&isa3_hashtb_eviction_lock); - if ((be64toh(pt->pte_hi) & LPTE_AVPN_MASK) != - (properpt.pte_hi & LPTE_AVPN_MASK)) { - rw_runlock(&isa3_hashtb_eviction_lock); - return (-1); - } - pt->pte_hi = htobe64(properpt.pte_hi); - ptelo = be64toh(pt->pte_lo); - rw_runlock(&isa3_hashtb_eviction_lock); - } else { - /* Otherwise, need reinsertion and deletion */ - ptelo = isa3_hashtb_pte_unset(mmu, pvo); - isa3_hashtb_pte_insert(mmu, pvo); - } - - return (ptelo); -} - -static void -isa3_hashtb_cpu_bootstrap(mmu_t mmup, int ap) -{ - int i = 0; - struct slb *slb = PCPU_GET(aim.slb); - register_t seg0; - - /* - * Initialize segment registers and MMU - */ - - mtmsr(mfmsr() & ~PSL_DR & ~PSL_IR); - - switch (mfpvr() >> 16) { - case IBMPOWER9: - mtspr(SPR_HID0, mfspr(SPR_HID0) & ~HID0_RADIX); - break; - } - - /* - * Install kernel SLB entries - */ - - __asm __volatile ("slbia"); - __asm __volatile ("slbmfee %0,%1; slbie %0;" : "=r"(seg0) : - "r"(0)); - - for (i = 0; i < n_slbs; i++) { - if (!(slb[i].slbe & SLBE_VALID)) - continue; - - __asm __volatile ("slbmte %0, %1" :: - "r"(slb[i].slbv), "r"(slb[i].slbe)); - } - - /* - * Install page table - */ - - mtspr(SPR_PTCR, - ((uintptr_t)isa3_part_table & ~DMAP_BASE_ADDRESS) | - flsl((PART_SIZE >> 12) - 1)); - tlbia(); -} - -static void -isa3_hashtb_bootstrap(mmu_t mmup, vm_offset_t kernelstart, - vm_offset_t kernelend) -{ - vm_size_t size; - vm_offset_t off; - vm_paddr_t pa; - register_t msr; - - moea64_early_bootstrap(mmup, kernelstart, kernelend); - - /* - * Allocate PTEG table. - */ - - size = moea64_pteg_count * sizeof(struct lpteg); - CTR2(KTR_PMAP, "moea64_bootstrap: %d PTEGs, %lu bytes", - moea64_pteg_count, size); - rw_init(&isa3_hashtb_eviction_lock, "pte eviction"); - - /* - * We now need to allocate memory. This memory, to be allocated, - * has to reside in a page table. The page table we are about to - * allocate. We don't have BAT. So drop to data real mode for a minute - * as a measure of last resort. We do this a couple times. - */ - - isa3_part_table = - (struct pate *)moea64_bootstrap_alloc(PART_SIZE, PART_SIZE); - if (hw_direct_map) - isa3_part_table = (struct pate *)PHYS_TO_DMAP( - (vm_offset_t)isa3_part_table); - /* - * PTEG table must be aligned on a 256k boundary, but can be placed - * anywhere with that alignment on POWER ISA 3+ systems. - */ - isa3_hashtb_pteg_table = (struct lpte *)moea64_bootstrap_alloc(size, - MAX(256*1024, size)); - if (hw_direct_map) - isa3_hashtb_pteg_table = - (struct lpte *)PHYS_TO_DMAP((vm_offset_t)isa3_hashtb_pteg_table); - DISABLE_TRANS(msr); - bzero(__DEVOLATILE(void *, isa3_part_table), PART_SIZE); - isa3_part_table[0].pagetab = - ((uintptr_t)isa3_hashtb_pteg_table & ~DMAP_BASE_ADDRESS) | - (uintptr_t)(flsl((moea64_pteg_count - 1) >> 11)); - bzero(__DEVOLATILE(void *, isa3_hashtb_pteg_table), moea64_pteg_count * - sizeof(struct lpteg)); - ENABLE_TRANS(msr); - - CTR1(KTR_PMAP, "moea64_bootstrap: PTEG table at %p", isa3_hashtb_pteg_table); - - moea64_mid_bootstrap(mmup, kernelstart, kernelend); - - /* - * Add a mapping for the page table itself if there is no direct map. - */ - if (!hw_direct_map) { - size = moea64_pteg_count * sizeof(struct lpteg); - off = (vm_offset_t)(isa3_hashtb_pteg_table); - DISABLE_TRANS(msr); - for (pa = off; pa < off + size; pa += PAGE_SIZE) - pmap_kenter(pa, pa); - ENABLE_TRANS(msr); - } - - /* Bring up virtual memory */ - moea64_late_bootstrap(mmup, kernelstart, kernelend); -} - -static void -tlbia(void) -{ - vm_offset_t i; - - i = 0xc00; /* IS = 11 */ - - TLBSYNC(); - - for (; i < 0x200000; i += 0x00001000) { - __asm __volatile("tlbiel %0" :: "r"(i)); - } - - EIEIO(); - TLBSYNC(); -} - -static int -atomic_pte_lock(volatile struct lpte *pte, uint64_t bitmask, uint64_t *oldhi) -{ - int ret; - uint32_t oldhihalf; - - /* - * Note: in principle, if just the locked bit were set here, we - * could avoid needing the eviction lock. However, eviction occurs - * so rarely that it isn't worth bothering about in practice. - */ - - __asm __volatile ( - "1:\tlwarx %1, 0, %3\n\t" /* load old value */ - "and. %0,%1,%4\n\t" /* check if any bits set */ - "bne 2f\n\t" /* exit if any set */ - "stwcx. %5, 0, %3\n\t" /* attempt to store */ - "bne- 1b\n\t" /* spin if failed */ - "li %0, 1\n\t" /* success - retval = 1 */ - "b 3f\n\t" /* we've succeeded */ - "2:\n\t" - "stwcx. %1, 0, %3\n\t" /* clear reservation (74xx) */ - "li %0, 0\n\t" /* failure - retval = 0 */ - "3:\n\t" - : "=&r" (ret), "=&r"(oldhihalf), "=m" (pte->pte_hi) - : "r" ((volatile char *)&pte->pte_hi + 4), - "r" ((uint32_t)bitmask), "r" ((uint32_t)LPTE_LOCKED), - "m" (pte->pte_hi) - : "cr0", "cr1", "cr2", "memory"); - - *oldhi = (pte->pte_hi & 0xffffffff00000000ULL) | oldhihalf; - - return (ret); -} - -static uintptr_t -isa3_hashtb_insert_to_pteg(struct lpte *pvo_pt, uintptr_t slotbase, - uint64_t mask) -{ - volatile struct lpte *pt; - uint64_t oldptehi, va; - uintptr_t k; - int i, j; - - /* Start at a random slot */ - i = mftb() % 8; - for (j = 0; j < 8; j++) { - k = slotbase + (i + j) % 8; - pt = &isa3_hashtb_pteg_table[k]; - /* Invalidate and seize lock only if no bits in mask set */ - if (atomic_pte_lock(pt, mask, &oldptehi)) /* Lock obtained */ - break; - } - - if (j == 8) - return (-1); - - if (oldptehi & LPTE_VALID) { - KASSERT(!(oldptehi & LPTE_WIRED), ("Unmapped wired entry")); - /* - * Need to invalidate old entry completely: see - * "Modifying a Page Table Entry". Need to reconstruct - * the virtual address for the outgoing entry to do that. - */ - if (oldptehi & LPTE_BIG) - va = oldptehi >> moea64_large_page_shift; - else - va = oldptehi >> ADDR_PIDX_SHFT; - if (oldptehi & LPTE_HID) - va = (((k >> 3) ^ moea64_pteg_mask) ^ va) & - VSID_HASH_MASK; - else - va = ((k >> 3) ^ va) & VSID_HASH_MASK; - va |= (oldptehi & LPTE_AVPN_MASK) << - (ADDR_API_SHFT64 - ADDR_PIDX_SHFT); - PTESYNC(); - TLBIE(va); - moea64_pte_valid--; - moea64_pte_overflow++; - } - - /* - * Update the PTE as per "Adding a Page Table Entry". Lock is released - * by setting the high doubleworld. - */ - pt->pte_lo = htobe64(pvo_pt->pte_lo); - EIEIO(); - pt->pte_hi = htobe64(pvo_pt->pte_hi); - PTESYNC(); - - /* Keep statistics */ - moea64_pte_valid++; - - return (k); -} - -static int -isa3_hashtb_pte_insert(mmu_t mmu, struct pvo_entry *pvo) -{ - struct lpte insertpt; - uintptr_t slot; - - /* Initialize PTE */ - moea64_pte_from_pvo(pvo, &insertpt); - - /* Make sure further insertion is locked out during evictions */ - rw_rlock(&isa3_hashtb_eviction_lock); - - /* - * First try primary hash. - */ - pvo->pvo_pte.slot &= ~7ULL; /* Base slot address */ - slot = isa3_hashtb_insert_to_pteg(&insertpt, pvo->pvo_pte.slot, - LPTE_VALID | LPTE_WIRED | LPTE_LOCKED); - if (slot != -1) { - rw_runlock(&isa3_hashtb_eviction_lock); - pvo->pvo_pte.slot = slot; - return (0); - } - - /* - * Now try secondary hash. - */ - pvo->pvo_vaddr ^= PVO_HID; - insertpt.pte_hi ^= LPTE_HID; - pvo->pvo_pte.slot ^= (moea64_pteg_mask << 3); - slot = isa3_hashtb_insert_to_pteg(&insertpt, pvo->pvo_pte.slot, - LPTE_VALID | LPTE_WIRED | LPTE_LOCKED); - if (slot != -1) { - rw_runlock(&isa3_hashtb_eviction_lock); - pvo->pvo_pte.slot = slot; - return (0); - } - - /* - * Out of luck. Find a PTE to sacrifice. - */ - - /* Lock out all insertions for a bit */ - if (!rw_try_upgrade(&isa3_hashtb_eviction_lock)) { - rw_runlock(&isa3_hashtb_eviction_lock); - rw_wlock(&isa3_hashtb_eviction_lock); - } - - slot = isa3_hashtb_insert_to_pteg(&insertpt, pvo->pvo_pte.slot, - LPTE_WIRED | LPTE_LOCKED); - if (slot != -1) { - rw_wunlock(&isa3_hashtb_eviction_lock); - pvo->pvo_pte.slot = slot; - return (0); - } - - /* Try other hash table. Now we're getting desperate... */ - pvo->pvo_vaddr ^= PVO_HID; - insertpt.pte_hi ^= LPTE_HID; - pvo->pvo_pte.slot ^= (moea64_pteg_mask << 3); - slot = isa3_hashtb_insert_to_pteg(&insertpt, pvo->pvo_pte.slot, - LPTE_WIRED | LPTE_LOCKED); - if (slot != -1) { - rw_wunlock(&isa3_hashtb_eviction_lock); - pvo->pvo_pte.slot = slot; - return (0); - } - - /* No freeable slots in either PTEG? We're hosed. */ - rw_wunlock(&isa3_hashtb_eviction_lock); - panic("moea64_pte_insert: overflow"); - return (-1); -} - diff --git a/sys/powerpc/aim/moea64_if.m b/sys/powerpc/aim/moea64_if.m deleted file mode 100644 index 72c4cee8a1c..00000000000 --- a/sys/powerpc/aim/moea64_if.m +++ /dev/null @@ -1,120 +0,0 @@ -#- -# Copyright (c) 2010,2015 Nathan Whitehorn -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# -# THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND -# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -# ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE -# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -# OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -# HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -# OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -# SUCH DAMAGE. -# -# - - -#include -#include -#include -#include - -#include -#include - -#include - -/** - * MOEA64 kobj methods for 64-bit Book-S page table - * manipulation routines used, for example, by hypervisors. - */ - -INTERFACE moea64; - -CODE { - static moea64_pte_replace_t moea64_pte_replace_default; - - static int64_t moea64_pte_replace_default(mmu_t mmu, - struct pvo_entry *pvo, int flags) - { - int64_t refchg; - - refchg = MOEA64_PTE_UNSET(mmu, pvo); - MOEA64_PTE_INSERT(mmu, pvo); - - return (refchg); - } -} - -/** - * Return ref/changed bits from PTE referenced by _pvo if _pvo is currently in - * the page table. Returns -1 if _pvo not currently present in the page table. - */ -METHOD int64_t pte_synch { - mmu_t _mmu; - struct pvo_entry *_pvo; -}; - -/** - * Clear bits ptebit (a mask) from the low word of the PTE referenced by - * _pvo. Return previous values of ref/changed bits or -1 if _pvo is not - * currently in the page table. - */ -METHOD int64_t pte_clear { - mmu_t _mmu; - struct pvo_entry *_pvo; - uint64_t _ptebit; -}; - -/** - * Invalidate the PTE referenced by _pvo, returning its ref/changed bits. - * Returns -1 if PTE not currently present in page table. - */ -METHOD int64_t pte_unset { - mmu_t _mmu; - struct pvo_entry *_pvo; -}; - -/** - * Update the reference PTE to correspond to the contents of _pvo. Has the - * same ref/changed semantics as pte_unset() (and should clear R/C bits). May - * change the PVO's location in the page table or return with it unmapped if - * PVO_WIRED is not set. By default, does unset() followed by insert(). - * - * _flags is a bitmask describing what level of page invalidation should occur: - * 0 means no invalidation is required - * MOEA64_PTE_PROT_UPDATE signifies that the page protection bits are changing - * MOEA64_PTE_INVALIDATE requires an invalidation of the same strength as - * pte_unset() followed by pte_insert() - */ -METHOD int64_t pte_replace { - mmu_t _mmu; - struct pvo_entry *_pvo; - int _flags; -} DEFAULT moea64_pte_replace_default; - -/** - * Insert a PTE corresponding to _pvo into the page table, returning any errors - * encountered and (optionally) setting the PVO slot value to some - * representation of where the entry was placed. - * - * Must not replace PTEs marked LPTE_WIRED. If an existing valid PTE is spilled, - * must synchronize ref/changed bits as in pte_unset(). - */ -METHOD int pte_insert { - mmu_t _mmu; - struct pvo_entry *_pvo; -}; - diff --git a/sys/powerpc/booke/machdep_ppc4xx.c b/sys/powerpc/booke/machdep_ppc4xx.c deleted file mode 100644 index f1da7986cb6..00000000000 --- a/sys/powerpc/booke/machdep_ppc4xx.c +++ /dev/null @@ -1,215 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2011-2012 Semihalf. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include - -#include -#include - -#include - -#include -#include - -#include - -#define OCP_ADDR_WORDLO(addr) ((uint32_t)((uint64_t)(addr) & 0xFFFFFFFF)) -#define OCP_ADDR_WORDHI(addr) ((uint32_t)((uint64_t)(addr) >> 32)) - -extern void tlb_write(u_int, uint32_t, uint32_t, uint32_t, tlbtid_t, uint32_t, - uint32_t); -extern void tlb_read(u_int, uint32_t *, uint32_t *, uint32_t *, uint32_t *, - uint32_t *, uint32_t *); - -unsigned int tlb_static_entries; -unsigned int tlb_current_entry = TLB_SIZE; -unsigned int tlb_misses = 0; -unsigned int tlb_invals = 0; - -void tlb_map(uint32_t, uint32_t, uint32_t, uint32_t, uint32_t); -void tlb_map_mem(uint32_t, uint32_t, uint32_t); -void tlb_dump(void); - -void -booke_init_tlb(vm_paddr_t fdt_immr_pa) -{ - - /* Map register space */ - tlb_map(APM86XXX_DEEP_SLEEP_VA, - OCP_ADDR_WORDLO(APM86XXX_DEEP_SLEEP_PA), - OCP_ADDR_WORDHI(APM86XXX_DEEP_SLEEP_PA), TLB_VALID | TLB_SIZE_16M, - TLB_SW | TLB_SR | TLB_I | TLB_G); - - tlb_map(APM86XXX_CSR_VA, OCP_ADDR_WORDLO(APM86XXX_CSR_PA), - OCP_ADDR_WORDHI(APM86XXX_CSR_PA), TLB_VALID | TLB_SIZE_16M, - TLB_SW | TLB_SR | TLB_I | TLB_G); - - tlb_map(APM86XXX_PRIMARY_FABRIC_VA, - OCP_ADDR_WORDLO(APM86XXX_PRIMARY_FABRIC_PA), - OCP_ADDR_WORDHI(APM86XXX_PRIMARY_FABRIC_PA), - TLB_VALID | TLB_SIZE_16M, - TLB_SW | TLB_SR | TLB_I | TLB_G); - - tlb_map(APM86XXX_AHB_VA, OCP_ADDR_WORDLO(APM86XXX_AHB_PA), - OCP_ADDR_WORDHI(APM86XXX_AHB_PA), - TLB_VALID | TLB_SIZE_16M, - TLB_SW | TLB_SR | TLB_I | TLB_G); - - /* Map MailBox space */ - tlb_map(APM86XXX_MBOX_VA, OCP_ADDR_WORDLO(APM86XXX_MBOX_PA), - OCP_ADDR_WORDHI(APM86XXX_MBOX_PA), - TLB_VALID | TLB_SIZE_4K, - TLB_UX | TLB_UW | TLB_UR | - TLB_SX | TLB_SW | TLB_SR | - TLB_I | TLB_G); - - tlb_map(APM86XXX_MBOX_VA + 0x1000, - OCP_ADDR_WORDLO(APM86XXX_MBOX_PA) + 0x1000, - OCP_ADDR_WORDHI(APM86XXX_MBOX_PA), - TLB_VALID | TLB_SIZE_4K, - TLB_UX | TLB_UW | TLB_UR | - TLB_SX | TLB_SW | TLB_SR | - TLB_I | TLB_G); - - tlb_map(APM86XXX_MBOX_VA + 0x2000, - OCP_ADDR_WORDLO(APM86XXX_MBOX_PA)+ 0x2000, - OCP_ADDR_WORDHI(APM86XXX_MBOX_PA), - TLB_VALID | TLB_SIZE_4K, - TLB_UX | TLB_UW | TLB_UR | - TLB_SX | TLB_SW | TLB_SR | - TLB_I | TLB_G); -} - -void -booke_enable_l1_cache(void) -{ -} - -void -booke_enable_l2_cache(void) -{ -} - -void -booke_disable_l2_cache(void) -{ - uint32_t ccr1,l2cr0; - - /* Disable L2 cache op broadcast */ - ccr1 = mfspr(SPR_CCR1); - ccr1 &= ~CCR1_L2COBE; - mtspr(SPR_CCR1, ccr1); - - /* Set L2 array size to 0 i.e. disable L2 cache */ - mtdcr(DCR_L2DCDCRAI, DCR_L2CR0); - l2cr0 = mfdcr(DCR_L2DCDCRDI); - l2cr0 &= ~L2CR0_AS; - mtdcr(DCR_L2DCDCRDI, l2cr0); -} - -void tlb_map(uint32_t epn, uint32_t rpn, uint32_t erpn, uint32_t flags, - uint32_t perms) -{ - - tlb_write(++tlb_static_entries, epn, rpn, erpn, 0, flags, perms); -} - -static void tlb_dump_entry(u_int entry) -{ - uint32_t epn, rpn, erpn, tid, flags, perms; - const char *size; - - tlb_read(entry, &epn, &rpn, &erpn, &tid, &flags, &perms); - - switch (flags & TLB_SIZE_MASK) { - case TLB_SIZE_1K: - size = " 1k"; - break; - case TLB_SIZE_4K: - size = " 4k"; - break; - case TLB_SIZE_16K: - size = " 16k"; - break; - case TLB_SIZE_256K: - size = "256k"; - break; - case TLB_SIZE_1M: - size = " 1M"; - break; - case TLB_SIZE_16M: - size = " 16M"; - break; - case TLB_SIZE_256M: - size = "256M"; - break; - case TLB_SIZE_1G: - size = " 1G"; - break; - default: - size = "????"; - break; - } - - - printf("TLB[%02u]: 0x%08X => " - "0x%01X_%08X %s %c %c %s %s %s %s %s " - "%c%c%c%c%c%c%c%c%c%c%c%c%c%c%c (%u)\n", - entry, epn, erpn, rpn, size, - (flags & TLB_TS) ? '1' : '0', - (flags & TLB_VALID) ? 'V' : '.', - (perms & TLB_WL1) ? "WL1" : "___", - (perms & TLB_IL1I) ? "IL1I" : "____", - (perms & TLB_IL1D) ? "IL1D" : "____", - (perms & TLB_IL2I) ? "IL2I" : "____", - (perms & TLB_IL2D) ? "IL2D" : "____", - (perms & TLB_U0) ? '1' : '.', - (perms & TLB_U1) ? '2' : '.', - (perms & TLB_U2) ? '3' : '.', - (perms & TLB_U3) ? '4' : '.', - (perms & TLB_W) ? 'W' : '.', - (perms & TLB_I) ? 'I' : '.', - (perms & TLB_M) ? 'M' : '.', - (perms & TLB_G) ? 'G' : '.', - (perms & TLB_E) ? 'E' : '.', - (perms & TLB_UX) ? 'x' : '.', - (perms & TLB_UW) ? 'w' : '.', - (perms & TLB_UR) ? 'r' : '.', - (perms & TLB_SX) ? 'X' : '.', - (perms & TLB_SW) ? 'W' : '.', - (perms & TLB_SR) ? 'R' : '.', - tid); -} - -void tlb_dump(void) -{ - int i; - - for (i = 0; i < TLB_SIZE; i++) - tlb_dump_entry(i); -} diff --git a/sys/sys/disk/vtoc.h b/sys/sys/disk/vtoc.h deleted file mode 100644 index 1227ab2b653..00000000000 --- a/sys/sys/disk/vtoc.h +++ /dev/null @@ -1,109 +0,0 @@ -/*- - * Copyright (c) 2008 Marcel Moolenaar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef _SYS_DISK_VTOC_H_ -#define _SYS_DISK_VTOC_H_ - -#include - -#define VTOC_TAG_UNASSIGNED 0x00 -#define VTOC_TAG_BOOT 0x01 -#define VTOC_TAG_ROOT 0x02 -#define VTOC_TAG_SWAP 0x03 -#define VTOC_TAG_USR 0x04 -#define VTOC_TAG_BACKUP 0x05 /* "c" partition */ -#define VTOC_TAG_STAND 0x06 -#define VTOC_TAG_VAR 0x07 -#define VTOC_TAG_HOME 0x08 -#define VTOC_TAG_ALTSCTR 0x09 /* alternate sector partition */ -#define VTOC_TAG_CACHE 0x0a /* Solaris cachefs partition */ -#define VTOC_TAG_VXVM_PUB 0x0e /* VxVM public region */ -#define VTOC_TAG_VXVM_PRIV 0x0f /* VxVM private region */ - -/* NetBSD/mips defines this */ -#define VTOC_TAG_NETBSD_FFS 0xff - -/* MidnightBSD tags: the high byte equals ELFOSABI_FREEBSD */ -#define VTOC_TAG_MIDNIGHTBSD_SWAP 0x0901 -#define VTOC_TAG_MIDNIGHTBSD_UFS 0x0902 -#define VTOC_TAG_MIDNIGHTBSD_VINUM 0x0903 -#define VTOC_TAG_MIDNIGHTBSD_ZFS 0x0904 -#define VTOC_TAG_MIDNIGHTBSD_NANDFS 0x0905 - -#define VTOC_FLAG_UNMNT 0x01 /* unmountable partition */ -#define VTOC_FLAG_RDONLY 0x10 /* partition is read/only */ - -#define VTOC_ASCII_LEN 128 -#define VTOC_BOOTSIZE 8192 /* 16 sectors */ -#define VTOC_MAGIC 0xdabe -#define VTOC_RAW_PART 2 -#define VTOC_SANITY 0x600ddeee -#define VTOC_VERSION 1 -#define VTOC_VOLUME_LEN 8 - -#define VTOC8_NPARTS 8 - -struct vtoc8 { - char ascii[VTOC_ASCII_LEN]; - uint32_t version; - char volume[VTOC_VOLUME_LEN]; - uint16_t nparts; - struct { - uint16_t tag; - uint16_t flag; - } part[VTOC8_NPARTS]; - uint16_t __alignment; - uint32_t bootinfo[3]; - uint32_t sanity; - uint32_t reserved[10]; - uint32_t timestamp[VTOC8_NPARTS]; - uint16_t wskip; - uint16_t rskip; - char padding[152]; - uint16_t rpm; - uint16_t physcyls; - uint16_t sparesecs; - uint16_t spare1[2]; - uint16_t interleave; - uint16_t ncyls; - uint16_t altcyls; - uint16_t nheads; - uint16_t nsecs; - uint16_t spare2[2]; - struct { - uint32_t cyl; - uint32_t nblks; - } map[VTOC8_NPARTS]; - uint16_t magic; - uint16_t cksum; -}; - -#ifdef CTASSERT -CTASSERT(sizeof(struct vtoc8) == 512); -#endif - -#endif /* _SYS_DISK_VTOC_H_ */ diff --git a/sys/x86/acpica/acpi_wakeup.c b/sys/x86/acpica/acpi_wakeup.c deleted file mode 100644 index a17d7fa37a6..00000000000 --- a/sys/x86/acpica/acpi_wakeup.c +++ /dev/null @@ -1,483 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2001 Takanori Watanabe - * Copyright (c) 2001-2012 Mitsuru IWASAKI - * Copyright (c) 2003 Peter Wemm - * Copyright (c) 2008-2012 Jung-uk Kim - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include - -#if defined(__amd64__) -#define DEV_APIC -#else -#include "opt_apic.h" -#endif - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include - -#ifdef DEV_APIC -#include -#include -#endif -#ifdef SMP -#include -#include -#endif - -#include - -#include - -#include "acpi_wakecode.h" -#include "acpi_wakedata.h" - -/* Make sure the code is less than a page and leave room for the stack. */ -CTASSERT(sizeof(wakecode) < PAGE_SIZE - 1024); - -extern int acpi_resume_beep; -extern int acpi_reset_video; -extern int acpi_susp_bounce; - -#ifdef SMP -extern struct susppcb **susppcbs; -static cpuset_t suspcpus; -#else -static struct susppcb **susppcbs; -#endif - -static void *acpi_alloc_wakeup_handler(void **); -static void acpi_stop_beep(void *); - -#ifdef SMP -static int acpi_wakeup_ap(struct acpi_softc *, int); -static void acpi_wakeup_cpus(struct acpi_softc *); -#endif - -#ifdef __amd64__ -#define ACPI_WAKEPAGES 4 -#else -#define ACPI_WAKEPAGES 1 -#endif - -#define WAKECODE_FIXUP(offset, type, val) do { \ - type *addr; \ - addr = (type *)(sc->acpi_wakeaddr + (offset)); \ - *addr = val; \ -} while (0) - -static void -acpi_stop_beep(void *arg) -{ - - if (acpi_resume_beep != 0) - timer_spkr_release(); -} - -#ifdef SMP -static int -acpi_wakeup_ap(struct acpi_softc *sc, int cpu) -{ - struct pcb *pcb; - int vector = (sc->acpi_wakephys >> 12) & 0xff; - int apic_id = cpu_apic_ids[cpu]; - int ms; - - pcb = &susppcbs[cpu]->sp_pcb; - WAKECODE_FIXUP(wakeup_pcb, struct pcb *, pcb); - WAKECODE_FIXUP(wakeup_gdt, uint16_t, pcb->pcb_gdt.rd_limit); - WAKECODE_FIXUP(wakeup_gdt + 2, uint64_t, pcb->pcb_gdt.rd_base); - - ipi_startup(apic_id, vector); - - /* Wait up to 5 seconds for it to resume. */ - for (ms = 0; ms < 5000; ms++) { - if (!CPU_ISSET(cpu, &suspended_cpus)) - return (1); /* return SUCCESS */ - DELAY(1000); - } - return (0); /* return FAILURE */ -} - -#define WARMBOOT_TARGET 0 -#ifdef __amd64__ -#define WARMBOOT_OFF (KERNBASE + 0x0467) -#define WARMBOOT_SEG (KERNBASE + 0x0469) -#else /* __i386__ */ -#define WARMBOOT_OFF (PMAP_MAP_LOW + 0x0467) -#define WARMBOOT_SEG (PMAP_MAP_LOW + 0x0469) -#endif - -#define CMOS_REG (0x70) -#define CMOS_DATA (0x71) -#define BIOS_RESET (0x0f) -#define BIOS_WARM (0x0a) - -static void -acpi_wakeup_cpus(struct acpi_softc *sc) -{ - uint32_t mpbioswarmvec; - int cpu; - u_char mpbiosreason; - - /* save the current value of the warm-start vector */ - mpbioswarmvec = *((uint32_t *)WARMBOOT_OFF); - outb(CMOS_REG, BIOS_RESET); - mpbiosreason = inb(CMOS_DATA); - - /* setup a vector to our boot code */ - *((volatile u_short *)WARMBOOT_OFF) = WARMBOOT_TARGET; - *((volatile u_short *)WARMBOOT_SEG) = sc->acpi_wakephys >> 4; - outb(CMOS_REG, BIOS_RESET); - outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */ - - /* Wake up each AP. */ - for (cpu = 1; cpu < mp_ncpus; cpu++) { - if (!CPU_ISSET(cpu, &suspcpus)) - continue; - if (acpi_wakeup_ap(sc, cpu) == 0) { - /* restore the warmstart vector */ - *(uint32_t *)WARMBOOT_OFF = mpbioswarmvec; - panic("acpi_wakeup: failed to resume AP #%d (PHY #%d)", - cpu, cpu_apic_ids[cpu]); - } - } - -#ifdef __i386__ - /* - * Remove the identity mapping of low memory for all CPUs and sync - * the TLB for the BSP. The APs are now spinning in - * cpususpend_handler() and we will release them soon. Then each - * will invalidate its TLB. - */ - PTD[KPTDI] = 0; - invltlb_glob(); -#endif - - /* restore the warmstart vector */ - *(uint32_t *)WARMBOOT_OFF = mpbioswarmvec; - - outb(CMOS_REG, BIOS_RESET); - outb(CMOS_DATA, mpbiosreason); -} -#endif - -int -acpi_sleep_machdep(struct acpi_softc *sc, int state) -{ - ACPI_STATUS status; - struct pcb *pcb; -#ifdef __amd64__ - struct pcpu *pc; - int i; -#endif - - if (sc->acpi_wakeaddr == 0ul) - return (-1); /* couldn't alloc wake memory */ - -#ifdef SMP - suspcpus = all_cpus; - CPU_CLR(PCPU_GET(cpuid), &suspcpus); -#endif - - if (acpi_resume_beep != 0) - timer_spkr_acquire(); - - AcpiSetFirmwareWakingVector(sc->acpi_wakephys, 0); - - intr_suspend(); - - pcb = &susppcbs[0]->sp_pcb; - if (savectx(pcb)) { -#ifdef __amd64__ - fpususpend(susppcbs[0]->sp_fpususpend); -#else - npxsuspend(susppcbs[0]->sp_fpususpend); -#endif -#ifdef SMP - if (!CPU_EMPTY(&suspcpus) && suspend_cpus(suspcpus) == 0) { - device_printf(sc->acpi_dev, "Failed to suspend APs\n"); - return (0); /* couldn't sleep */ - } -#endif -#ifdef __amd64__ - hw_ibrs_ibpb_active = 0; - hw_ssb_active = 0; - cpu_stdext_feature3 = 0; - CPU_FOREACH(i) { - pc = pcpu_find(i); - pc->pc_ibpb_set = 0; - } -#endif - - WAKECODE_FIXUP(resume_beep, uint8_t, (acpi_resume_beep != 0)); - WAKECODE_FIXUP(reset_video, uint8_t, (acpi_reset_video != 0)); - -#ifdef __amd64__ - WAKECODE_FIXUP(wakeup_efer, uint64_t, rdmsr(MSR_EFER) & - ~(EFER_LMA)); -#else - WAKECODE_FIXUP(wakeup_cr4, register_t, pcb->pcb_cr4); -#endif - WAKECODE_FIXUP(wakeup_pcb, struct pcb *, pcb); - WAKECODE_FIXUP(wakeup_gdt, uint16_t, pcb->pcb_gdt.rd_limit); - WAKECODE_FIXUP(wakeup_gdt + 2, uint64_t, pcb->pcb_gdt.rd_base); - -#ifdef __i386__ - /* - * Map some low memory with virt == phys for ACPI wakecode - * to use to jump to high memory after enabling paging. This - * is the same as for similar jump in locore, except the - * jump is a single instruction, and we know its address - * more precisely so only need a single PTD, and we have to - * be careful to use the kernel map (PTD[0] is for curthread - * which may be a user thread in deprecated APIs). - */ - PTD[KPTDI] = PTD[LOWPTDI]; -#endif - - /* Call ACPICA to enter the desired sleep state */ - if (state == ACPI_STATE_S4 && sc->acpi_s4bios) - status = AcpiEnterSleepStateS4bios(); - else - status = AcpiEnterSleepState(state); - if (ACPI_FAILURE(status)) { - device_printf(sc->acpi_dev, - "AcpiEnterSleepState failed - %s\n", - AcpiFormatException(status)); - return (0); /* couldn't sleep */ - } - - if (acpi_susp_bounce) - resumectx(pcb); - - for (;;) - ia32_pause(); - } else { - /* - * Re-initialize console hardware as soon as possibe. - * No console output (e.g. printf) is allowed before - * this point. - */ - cnresume(); -#ifdef __amd64__ - fpuresume(susppcbs[0]->sp_fpususpend); -#else - npxresume(susppcbs[0]->sp_fpususpend); -#endif - } - - return (1); /* wakeup successfully */ -} - -int -acpi_wakeup_machdep(struct acpi_softc *sc, int state, int sleep_result, - int intr_enabled) -{ - - if (sleep_result == -1) - return (sleep_result); - - if (!intr_enabled) { - /* Wakeup MD procedures in interrupt disabled context */ - if (sleep_result == 1) { - ucode_reload(); - pmap_init_pat(); - initializecpu(); - PCPU_SET(switchtime, 0); - PCPU_SET(switchticks, ticks); -#ifdef DEV_APIC - lapic_xapic_mode(); -#endif -#ifdef SMP - if (!CPU_EMPTY(&suspcpus)) - acpi_wakeup_cpus(sc); -#endif - } - -#ifdef SMP - if (!CPU_EMPTY(&suspcpus)) - resume_cpus(suspcpus); -#endif - mca_resume(); -#ifdef __amd64__ - if (vmm_resume_p != NULL) - vmm_resume_p(); -#endif - intr_resume(/*suspend_cancelled*/false); - - AcpiSetFirmwareWakingVector(0, 0); - } else { - /* Wakeup MD procedures in interrupt enabled context */ - if (sleep_result == 1 && mem_range_softc.mr_op != NULL && - mem_range_softc.mr_op->reinit != NULL) - mem_range_softc.mr_op->reinit(&mem_range_softc); - } - - return (sleep_result); -} - -static void * -acpi_alloc_wakeup_handler(void *wakepages[ACPI_WAKEPAGES]) -{ - int i; - - memset(wakepages, 0, ACPI_WAKEPAGES * sizeof(*wakepages)); - - /* - * Specify the region for our wakeup code. We want it in the low 1 MB - * region, excluding real mode IVT (0-0x3ff), BDA (0x400-0x4ff), EBDA - * (less than 128KB, below 0xa0000, must be excluded by SMAP and DSDT), - * and ROM area (0xa0000 and above). The temporary page tables must be - * page-aligned. - */ - for (i = 0; i < ACPI_WAKEPAGES; i++) { - wakepages[i] = contigmalloc(PAGE_SIZE, M_DEVBUF, M_NOWAIT, - 0x500, 0xa0000, PAGE_SIZE, 0ul); - if (wakepages[i] == NULL) { - printf("%s: can't alloc wake memory\n", __func__); - goto freepages; - } - } - if (EVENTHANDLER_REGISTER(power_resume, acpi_stop_beep, NULL, - EVENTHANDLER_PRI_LAST) == NULL) { - printf("%s: can't register event handler\n", __func__); - goto freepages; - } - susppcbs = malloc(mp_ncpus * sizeof(*susppcbs), M_DEVBUF, M_WAITOK); - for (i = 0; i < mp_ncpus; i++) { - susppcbs[i] = malloc(sizeof(**susppcbs), M_DEVBUF, M_WAITOK); - susppcbs[i]->sp_fpususpend = alloc_fpusave(M_WAITOK); - } - - return (wakepages); - -freepages: - for (i = 0; i < ACPI_WAKEPAGES; i++) - if (wakepages[i] != NULL) - contigfree(wakepages[i], PAGE_SIZE, M_DEVBUF); - return (NULL); -} - -void -acpi_install_wakeup_handler(struct acpi_softc *sc) -{ - static void *wakeaddr; - void *wakepages[ACPI_WAKEPAGES]; -#ifdef __amd64__ - uint64_t *pt4, *pt3, *pt2; - vm_paddr_t pt4pa, pt3pa, pt2pa; - int i; -#endif - - if (wakeaddr != NULL) - return; - - if (acpi_alloc_wakeup_handler(wakepages) == NULL) - return; - - wakeaddr = wakepages[0]; - sc->acpi_wakeaddr = (vm_offset_t)wakeaddr; - sc->acpi_wakephys = vtophys(wakeaddr); - -#ifdef __amd64__ - pt4 = wakepages[1]; - pt3 = wakepages[2]; - pt2 = wakepages[3]; - pt4pa = vtophys(pt4); - pt3pa = vtophys(pt3); - pt2pa = vtophys(pt2); -#endif - - bcopy(wakecode, (void *)sc->acpi_wakeaddr, sizeof(wakecode)); - - /* Patch GDT base address, ljmp targets. */ - WAKECODE_FIXUP((bootgdtdesc + 2), uint32_t, - sc->acpi_wakephys + bootgdt); - WAKECODE_FIXUP((wakeup_sw32 + 2), uint32_t, - sc->acpi_wakephys + wakeup_32); -#ifdef __amd64__ - WAKECODE_FIXUP((wakeup_sw64 + 1), uint32_t, - sc->acpi_wakephys + wakeup_64); - WAKECODE_FIXUP(wakeup_pagetables, uint32_t, pt4pa); -#endif - - /* Save pointers to some global data. */ - WAKECODE_FIXUP(wakeup_ret, void *, resumectx); -#ifndef __amd64__ -#if defined(PAE) || defined(PAE_TABLES) - WAKECODE_FIXUP(wakeup_cr3, register_t, vtophys(kernel_pmap->pm_pdpt)); -#else - WAKECODE_FIXUP(wakeup_cr3, register_t, vtophys(kernel_pmap->pm_pdir)); -#endif - -#else /* __amd64__ */ - /* Create the initial 1GB replicated page tables */ - for (i = 0; i < 512; i++) { - /* - * Each slot of the level 4 pages points - * to the same level 3 page - */ - pt4[i] = (uint64_t)pt3pa; - pt4[i] |= PG_V | PG_RW | PG_U; - - /* - * Each slot of the level 3 pages points - * to the same level 2 page - */ - pt3[i] = (uint64_t)pt2pa; - pt3[i] |= PG_V | PG_RW | PG_U; - - /* The level 2 page slots are mapped with 2MB pages for 1GB. */ - pt2[i] = i * (2 * 1024 * 1024); - pt2[i] |= PG_V | PG_RW | PG_PS | PG_U; - } -#endif /* !__amd64__ */ - - if (bootverbose) - device_printf(sc->acpi_dev, "wakeup code va %#jx pa %#jx\n", - (uintmax_t)sc->acpi_wakeaddr, (uintmax_t)sc->acpi_wakephys); -} diff --git a/sys/x86/bios/smbios.c b/sys/x86/bios/smbios.c deleted file mode 100644 index 85f9825f4d0..00000000000 --- a/sys/x86/bios/smbios.c +++ /dev/null @@ -1,250 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2003 Matthew N. Dodd - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include - -#include -#include -#include -#include -#include - -#include -#include - -#include -#include -#include - -#include -#include -#include -#include -#include - -/* - * System Management BIOS Reference Specification, v2.4 Final - * http://www.dmtf.org/standards/published_documents/DSP0134.pdf - */ - -struct smbios_softc { - device_t dev; - struct resource * res; - int rid; - - struct smbios_eps * eps; -}; - -#define RES2EPS(res) ((struct smbios_eps *)rman_get_virtual(res)) -#define ADDR2EPS(addr) ((struct smbios_eps *)BIOS_PADDRTOVADDR(addr)) - -static devclass_t smbios_devclass; - -static void smbios_identify (driver_t *, device_t); -static int smbios_probe (device_t); -static int smbios_attach (device_t); -static int smbios_detach (device_t); -static int smbios_modevent (module_t, int, void *); - -static int smbios_cksum (struct smbios_eps *); - -static void -smbios_identify (driver_t *driver, device_t parent) -{ - device_t child; - u_int32_t addr; - int length; - int rid; - - if (!device_is_alive(parent)) - return; - - addr = bios_sigsearch(SMBIOS_START, SMBIOS_SIG, SMBIOS_LEN, - SMBIOS_STEP, SMBIOS_OFF); - if (addr != 0) { - rid = 0; - length = ADDR2EPS(addr)->length; - - if (length != 0x1f) { - u_int8_t major, minor; - - major = ADDR2EPS(addr)->major_version; - minor = ADDR2EPS(addr)->minor_version; - - /* SMBIOS v2.1 implementation might use 0x1e. */ - if (length == 0x1e && major == 2 && minor == 1) - length = 0x1f; - else - return; - } - - child = BUS_ADD_CHILD(parent, 5, "smbios", -1); - device_set_driver(child, driver); - bus_set_resource(child, SYS_RES_MEMORY, rid, addr, length); - device_set_desc(child, "System Management BIOS"); - } - - return; -} - -static int -smbios_probe (device_t dev) -{ - struct resource *res; - int rid; - int error; - - error = 0; - rid = 0; - res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); - if (res == NULL) { - device_printf(dev, "Unable to allocate memory resource.\n"); - error = ENOMEM; - goto bad; - } - - if (smbios_cksum(RES2EPS(res))) { - device_printf(dev, "SMBIOS checksum failed.\n"); - error = ENXIO; - goto bad; - } - -bad: - if (res) - bus_release_resource(dev, SYS_RES_MEMORY, rid, res); - return (error); -} - -static int -smbios_attach (device_t dev) -{ - struct smbios_softc *sc; - int error; - - sc = device_get_softc(dev); - error = 0; - - sc->dev = dev; - sc->rid = 0; - sc->res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->rid, - RF_ACTIVE); - if (sc->res == NULL) { - device_printf(dev, "Unable to allocate memory resource.\n"); - error = ENOMEM; - goto bad; - } - sc->eps = RES2EPS(sc->res); - - device_printf(dev, "Version: %u.%u", - sc->eps->major_version, sc->eps->minor_version); - if (bcd2bin(sc->eps->BCD_revision)) - printf(", BCD Revision: %u.%u", - bcd2bin(sc->eps->BCD_revision >> 4), - bcd2bin(sc->eps->BCD_revision & 0x0f)); - printf("\n"); - - return (0); -bad: - if (sc->res) - bus_release_resource(dev, SYS_RES_MEMORY, sc->rid, sc->res); - return (error); -} - -static int -smbios_detach (device_t dev) -{ - struct smbios_softc *sc; - - sc = device_get_softc(dev); - - if (sc->res) - bus_release_resource(dev, SYS_RES_MEMORY, sc->rid, sc->res); - - return (0); -} - -static int -smbios_modevent (mod, what, arg) - module_t mod; - int what; - void * arg; -{ - device_t * devs; - int count; - int i; - - switch (what) { - case MOD_LOAD: - break; - case MOD_UNLOAD: - devclass_get_devices(smbios_devclass, &devs, &count); - for (i = 0; i < count; i++) { - device_delete_child(device_get_parent(devs[i]), devs[i]); - } - free(devs, M_TEMP); - break; - default: - break; - } - - return (0); -} - -static device_method_t smbios_methods[] = { - /* Device interface */ - DEVMETHOD(device_identify, smbios_identify), - DEVMETHOD(device_probe, smbios_probe), - DEVMETHOD(device_attach, smbios_attach), - DEVMETHOD(device_detach, smbios_detach), - { 0, 0 } -}; - -static driver_t smbios_driver = { - "smbios", - smbios_methods, - sizeof(struct smbios_softc), -}; - -DRIVER_MODULE(smbios, nexus, smbios_driver, smbios_devclass, smbios_modevent, 0); -MODULE_VERSION(smbios, 1); - -static int -smbios_cksum (struct smbios_eps *e) -{ - u_int8_t *ptr; - u_int8_t cksum; - int i; - - ptr = (u_int8_t *)e; - cksum = 0; - for (i = 0; i < e->length; i++) { - cksum += ptr[i]; - } - - return (cksum); -} diff --git a/sys/x86/cpufreq/hwpstate.c b/sys/x86/cpufreq/hwpstate.c deleted file mode 100644 index ba3982f86f3..00000000000 --- a/sys/x86/cpufreq/hwpstate.c +++ /dev/null @@ -1,542 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2005 Nate Lawson - * Copyright (c) 2004 Colin Percival - * Copyright (c) 2004-2005 Bruno Durcot - * Copyright (c) 2004 FUKUDA Nobuhiko - * Copyright (c) 2009 Michael Reifenberger - * Copyright (c) 2009 Norikatsu Shigemura - * Copyright (c) 2008-2009 Gen Otsuji - * - * This code is depending on kern_cpu.c, est.c, powernow.c, p4tcc.c, smist.c - * in various parts. The authors of these files are Nate Lawson, - * Colin Percival, Bruno Durcot, and FUKUDA Nobuhiko. - * This code contains patches by Michael Reifenberger and Norikatsu Shigemura. - * Thank you. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted providing that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -/* - * For more info: - * BIOS and Kernel Developer's Guide(BKDG) for AMD Family 10h Processors - * 31116 Rev 3.20 February 04, 2009 - * BIOS and Kernel Developer's Guide(BKDG) for AMD Family 11h Processors - * 41256 Rev 3.00 - July 07, 2008 - */ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include - -#include - -#include "acpi_if.h" -#include "cpufreq_if.h" - -#define MSR_AMD_10H_11H_LIMIT 0xc0010061 -#define MSR_AMD_10H_11H_CONTROL 0xc0010062 -#define MSR_AMD_10H_11H_STATUS 0xc0010063 -#define MSR_AMD_10H_11H_CONFIG 0xc0010064 - -#define AMD_10H_11H_MAX_STATES 16 - -/* for MSR_AMD_10H_11H_LIMIT C001_0061 */ -#define AMD_10H_11H_GET_PSTATE_MAX_VAL(msr) (((msr) >> 4) & 0x7) -#define AMD_10H_11H_GET_PSTATE_LIMIT(msr) (((msr)) & 0x7) -/* for MSR_AMD_10H_11H_CONFIG 10h:C001_0064:68 / 11h:C001_0064:6B */ -#define AMD_10H_11H_CUR_VID(msr) (((msr) >> 9) & 0x7F) -#define AMD_10H_11H_CUR_DID(msr) (((msr) >> 6) & 0x07) -#define AMD_10H_11H_CUR_FID(msr) ((msr) & 0x3F) - -#define AMD_17H_CUR_VID(msr) (((msr) >> 14) & 0xFF) -#define AMD_17H_CUR_DID(msr) (((msr) >> 8) & 0x3F) -#define AMD_17H_CUR_FID(msr) ((msr) & 0xFF) - -#define HWPSTATE_DEBUG(dev, msg...) \ - do { \ - if (hwpstate_verbose) \ - device_printf(dev, msg); \ - } while (0) - -struct hwpstate_setting { - int freq; /* CPU clock in Mhz or 100ths of a percent. */ - int volts; /* Voltage in mV. */ - int power; /* Power consumed in mW. */ - int lat; /* Transition latency in us. */ - int pstate_id; /* P-State id */ -}; - -struct hwpstate_softc { - device_t dev; - struct hwpstate_setting hwpstate_settings[AMD_10H_11H_MAX_STATES]; - int cfnum; -}; - -static void hwpstate_identify(driver_t *driver, device_t parent); -static int hwpstate_probe(device_t dev); -static int hwpstate_attach(device_t dev); -static int hwpstate_detach(device_t dev); -static int hwpstate_set(device_t dev, const struct cf_setting *cf); -static int hwpstate_get(device_t dev, struct cf_setting *cf); -static int hwpstate_settings(device_t dev, struct cf_setting *sets, int *count); -static int hwpstate_type(device_t dev, int *type); -static int hwpstate_shutdown(device_t dev); -static int hwpstate_features(driver_t *driver, u_int *features); -static int hwpstate_get_info_from_acpi_perf(device_t dev, device_t perf_dev); -static int hwpstate_get_info_from_msr(device_t dev); -static int hwpstate_goto_pstate(device_t dev, int pstate_id); - -static int hwpstate_verbose; -SYSCTL_INT(_debug, OID_AUTO, hwpstate_verbose, CTLFLAG_RWTUN, - &hwpstate_verbose, 0, "Debug hwpstate"); - -static int hwpstate_verify; -SYSCTL_INT(_debug, OID_AUTO, hwpstate_verify, CTLFLAG_RWTUN, - &hwpstate_verify, 0, "Verify P-state after setting"); - -static device_method_t hwpstate_methods[] = { - /* Device interface */ - DEVMETHOD(device_identify, hwpstate_identify), - DEVMETHOD(device_probe, hwpstate_probe), - DEVMETHOD(device_attach, hwpstate_attach), - DEVMETHOD(device_detach, hwpstate_detach), - DEVMETHOD(device_shutdown, hwpstate_shutdown), - - /* cpufreq interface */ - DEVMETHOD(cpufreq_drv_set, hwpstate_set), - DEVMETHOD(cpufreq_drv_get, hwpstate_get), - DEVMETHOD(cpufreq_drv_settings, hwpstate_settings), - DEVMETHOD(cpufreq_drv_type, hwpstate_type), - - /* ACPI interface */ - DEVMETHOD(acpi_get_features, hwpstate_features), - - {0, 0} -}; - -static devclass_t hwpstate_devclass; -static driver_t hwpstate_driver = { - "hwpstate", - hwpstate_methods, - sizeof(struct hwpstate_softc), -}; - -DRIVER_MODULE(hwpstate, cpu, hwpstate_driver, hwpstate_devclass, 0, 0); - -/* - * Go to Px-state on all cpus considering the limit. - */ -static int -hwpstate_goto_pstate(device_t dev, int id) -{ - sbintime_t sbt; - uint64_t msr; - int cpu, i, j, limit; - - /* get the current pstate limit */ - msr = rdmsr(MSR_AMD_10H_11H_LIMIT); - limit = AMD_10H_11H_GET_PSTATE_LIMIT(msr); - if (limit > id) - id = limit; - - cpu = curcpu; - HWPSTATE_DEBUG(dev, "setting P%d-state on cpu%d\n", id, cpu); - /* Go To Px-state */ - wrmsr(MSR_AMD_10H_11H_CONTROL, id); - - /* - * We are going to the same Px-state on all cpus. - * Probably should take _PSD into account. - */ - CPU_FOREACH(i) { - if (i == cpu) - continue; - - /* Bind to each cpu. */ - thread_lock(curthread); - sched_bind(curthread, i); - thread_unlock(curthread); - HWPSTATE_DEBUG(dev, "setting P%d-state on cpu%d\n", id, i); - /* Go To Px-state */ - wrmsr(MSR_AMD_10H_11H_CONTROL, id); - } - - /* - * Verify whether each core is in the requested P-state. - */ - if (hwpstate_verify) { - CPU_FOREACH(i) { - thread_lock(curthread); - sched_bind(curthread, i); - thread_unlock(curthread); - /* wait loop (100*100 usec is enough ?) */ - for (j = 0; j < 100; j++) { - /* get the result. not assure msr=id */ - msr = rdmsr(MSR_AMD_10H_11H_STATUS); - if (msr == id) - break; - sbt = SBT_1MS / 10; - tsleep_sbt(dev, PZERO, "pstate_goto", sbt, - sbt >> tc_precexp, 0); - } - HWPSTATE_DEBUG(dev, "result: P%d-state on cpu%d\n", - (int)msr, i); - if (msr != id) { - HWPSTATE_DEBUG(dev, - "error: loop is not enough.\n"); - return (ENXIO); - } - } - } - - return (0); -} - -static int -hwpstate_set(device_t dev, const struct cf_setting *cf) -{ - struct hwpstate_softc *sc; - struct hwpstate_setting *set; - int i; - - if (cf == NULL) - return (EINVAL); - sc = device_get_softc(dev); - set = sc->hwpstate_settings; - for (i = 0; i < sc->cfnum; i++) - if (CPUFREQ_CMP(cf->freq, set[i].freq)) - break; - if (i == sc->cfnum) - return (EINVAL); - - return (hwpstate_goto_pstate(dev, set[i].pstate_id)); -} - -static int -hwpstate_get(device_t dev, struct cf_setting *cf) -{ - struct hwpstate_softc *sc; - struct hwpstate_setting set; - uint64_t msr; - - sc = device_get_softc(dev); - if (cf == NULL) - return (EINVAL); - msr = rdmsr(MSR_AMD_10H_11H_STATUS); - if (msr >= sc->cfnum) - return (EINVAL); - set = sc->hwpstate_settings[msr]; - - cf->freq = set.freq; - cf->volts = set.volts; - cf->power = set.power; - cf->lat = set.lat; - cf->dev = dev; - return (0); -} - -static int -hwpstate_settings(device_t dev, struct cf_setting *sets, int *count) -{ - struct hwpstate_softc *sc; - struct hwpstate_setting set; - int i; - - if (sets == NULL || count == NULL) - return (EINVAL); - sc = device_get_softc(dev); - if (*count < sc->cfnum) - return (E2BIG); - for (i = 0; i < sc->cfnum; i++, sets++) { - set = sc->hwpstate_settings[i]; - sets->freq = set.freq; - sets->volts = set.volts; - sets->power = set.power; - sets->lat = set.lat; - sets->dev = dev; - } - *count = sc->cfnum; - - return (0); -} - -static int -hwpstate_type(device_t dev, int *type) -{ - - if (type == NULL) - return (EINVAL); - - *type = CPUFREQ_TYPE_ABSOLUTE; - return (0); -} - -static void -hwpstate_identify(driver_t *driver, device_t parent) -{ - - if (device_find_child(parent, "hwpstate", -1) != NULL) - return; - - if ((cpu_vendor_id != CPU_VENDOR_AMD || CPUID_TO_FAMILY(cpu_id) < 0x10) && - cpu_vendor_id != CPU_VENDOR_HYGON) - return; - - /* - * Check if hardware pstate enable bit is set. - */ - if ((amd_pminfo & AMDPM_HW_PSTATE) == 0) { - HWPSTATE_DEBUG(parent, "hwpstate enable bit is not set.\n"); - return; - } - - if (resource_disabled("hwpstate", 0)) - return; - - if (BUS_ADD_CHILD(parent, 10, "hwpstate", -1) == NULL) - device_printf(parent, "hwpstate: add child failed\n"); -} - -static int -hwpstate_probe(device_t dev) -{ - struct hwpstate_softc *sc; - device_t perf_dev; - uint64_t msr; - int error, type; - - /* - * Only hwpstate0. - * It goes well with acpi_throttle. - */ - if (device_get_unit(dev) != 0) - return (ENXIO); - - sc = device_get_softc(dev); - sc->dev = dev; - - /* - * Check if acpi_perf has INFO only flag. - */ - perf_dev = device_find_child(device_get_parent(dev), "acpi_perf", -1); - error = TRUE; - if (perf_dev && device_is_attached(perf_dev)) { - error = CPUFREQ_DRV_TYPE(perf_dev, &type); - if (error == 0) { - if ((type & CPUFREQ_FLAG_INFO_ONLY) == 0) { - /* - * If acpi_perf doesn't have INFO_ONLY flag, - * it will take care of pstate transitions. - */ - HWPSTATE_DEBUG(dev, "acpi_perf will take care of pstate transitions.\n"); - return (ENXIO); - } else { - /* - * If acpi_perf has INFO_ONLY flag, (_PCT has FFixedHW) - * we can get _PSS info from acpi_perf - * without going into ACPI. - */ - HWPSTATE_DEBUG(dev, "going to fetch info from acpi_perf\n"); - error = hwpstate_get_info_from_acpi_perf(dev, perf_dev); - } - } - } - - if (error == 0) { - /* - * Now we get _PSS info from acpi_perf without error. - * Let's check it. - */ - msr = rdmsr(MSR_AMD_10H_11H_LIMIT); - if (sc->cfnum != 1 + AMD_10H_11H_GET_PSTATE_MAX_VAL(msr)) { - HWPSTATE_DEBUG(dev, "MSR (%jd) and ACPI _PSS (%d)" - " count mismatch\n", (intmax_t)msr, sc->cfnum); - error = TRUE; - } - } - - /* - * If we cannot get info from acpi_perf, - * Let's get info from MSRs. - */ - if (error) - error = hwpstate_get_info_from_msr(dev); - if (error) - return (error); - - device_set_desc(dev, "Cool`n'Quiet 2.0"); - return (0); -} - -static int -hwpstate_attach(device_t dev) -{ - - return (cpufreq_register(dev)); -} - -static int -hwpstate_get_info_from_msr(device_t dev) -{ - struct hwpstate_softc *sc; - struct hwpstate_setting *hwpstate_set; - uint64_t msr; - int family, i, fid, did; - - family = CPUID_TO_FAMILY(cpu_id); - sc = device_get_softc(dev); - /* Get pstate count */ - msr = rdmsr(MSR_AMD_10H_11H_LIMIT); - sc->cfnum = 1 + AMD_10H_11H_GET_PSTATE_MAX_VAL(msr); - hwpstate_set = sc->hwpstate_settings; - for (i = 0; i < sc->cfnum; i++) { - msr = rdmsr(MSR_AMD_10H_11H_CONFIG + i); - if ((msr & ((uint64_t)1 << 63)) == 0) { - HWPSTATE_DEBUG(dev, "msr is not valid.\n"); - return (ENXIO); - } - did = AMD_10H_11H_CUR_DID(msr); - fid = AMD_10H_11H_CUR_FID(msr); - - /* Convert fid/did to frequency. */ - switch (family) { - case 0x11: - hwpstate_set[i].freq = (100 * (fid + 0x08)) >> did; - break; - case 0x10: - case 0x12: - case 0x15: - case 0x16: - hwpstate_set[i].freq = (100 * (fid + 0x10)) >> did; - break; - case 0x17: - case 0x18: - did = AMD_17H_CUR_DID(msr); - if (did == 0) { - HWPSTATE_DEBUG(dev, "unexpected did: 0\n"); - did = 1; - } - fid = AMD_17H_CUR_FID(msr); - hwpstate_set[i].freq = (200 * fid) / did; - break; - default: - HWPSTATE_DEBUG(dev, "get_info_from_msr: %s family" - " 0x%02x CPUs are not supported yet\n", - cpu_vendor_id == CPU_VENDOR_HYGON ? "Hygon" : "AMD", - family); - return (ENXIO); - } - hwpstate_set[i].pstate_id = i; - /* There was volts calculation, but deleted it. */ - hwpstate_set[i].volts = CPUFREQ_VAL_UNKNOWN; - hwpstate_set[i].power = CPUFREQ_VAL_UNKNOWN; - hwpstate_set[i].lat = CPUFREQ_VAL_UNKNOWN; - } - return (0); -} - -static int -hwpstate_get_info_from_acpi_perf(device_t dev, device_t perf_dev) -{ - struct hwpstate_softc *sc; - struct cf_setting *perf_set; - struct hwpstate_setting *hwpstate_set; - int count, error, i; - - perf_set = malloc(MAX_SETTINGS * sizeof(*perf_set), M_TEMP, M_NOWAIT); - if (perf_set == NULL) { - HWPSTATE_DEBUG(dev, "nomem\n"); - return (ENOMEM); - } - /* - * Fetch settings from acpi_perf. - * Now it is attached, and has info only flag. - */ - count = MAX_SETTINGS; - error = CPUFREQ_DRV_SETTINGS(perf_dev, perf_set, &count); - if (error) { - HWPSTATE_DEBUG(dev, "error: CPUFREQ_DRV_SETTINGS.\n"); - goto out; - } - sc = device_get_softc(dev); - sc->cfnum = count; - hwpstate_set = sc->hwpstate_settings; - for (i = 0; i < count; i++) { - if (i == perf_set[i].spec[0]) { - hwpstate_set[i].pstate_id = i; - hwpstate_set[i].freq = perf_set[i].freq; - hwpstate_set[i].volts = perf_set[i].volts; - hwpstate_set[i].power = perf_set[i].power; - hwpstate_set[i].lat = perf_set[i].lat; - } else { - HWPSTATE_DEBUG(dev, "ACPI _PSS object mismatch.\n"); - error = ENXIO; - goto out; - } - } -out: - if (perf_set) - free(perf_set, M_TEMP); - return (error); -} - -static int -hwpstate_detach(device_t dev) -{ - - hwpstate_goto_pstate(dev, 0); - return (cpufreq_unregister(dev)); -} - -static int -hwpstate_shutdown(device_t dev) -{ - - /* hwpstate_goto_pstate(dev, 0); */ - return (0); -} - -static int -hwpstate_features(driver_t *driver, u_int *features) -{ - - /* Notify the ACPI CPU that we support direct access to MSRs */ - *features = ACPI_CAP_PERF_MSRS; - return (0); -} diff --git a/sys/x86/iommu/busdma_dmar.c b/sys/x86/iommu/busdma_dmar.c deleted file mode 100644 index d2255aae095..00000000000 --- a/sys/x86/iommu/busdma_dmar.c +++ /dev/null @@ -1,1022 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2013 The FreeBSD Foundation - * All rights reserved. - * - * This software was developed by Konstantin Belousov - * under sponsorship from the FreeBSD Foundation. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* - * busdma_dmar.c, the implementation of the busdma(9) interface using - * DMAR units from Intel VT-d. - */ - -static bool -dmar_bus_dma_is_dev_disabled(int domain, int bus, int slot, int func) -{ - char str[128], *env; - int default_bounce; - bool ret; - static const char bounce_str[] = "bounce"; - static const char dmar_str[] = "dmar"; - - default_bounce = 0; - env = kern_getenv("hw.busdma.default"); - if (env != NULL) { - if (strcmp(env, bounce_str) == 0) - default_bounce = 1; - else if (strcmp(env, dmar_str) == 0) - default_bounce = 0; - freeenv(env); - } - - snprintf(str, sizeof(str), "hw.busdma.pci%d.%d.%d.%d", - domain, bus, slot, func); - env = kern_getenv(str); - if (env == NULL) - return (default_bounce != 0); - if (strcmp(env, bounce_str) == 0) - ret = true; - else if (strcmp(env, dmar_str) == 0) - ret = false; - else - ret = default_bounce != 0; - freeenv(env); - return (ret); -} - -/* - * Given original device, find the requester ID that will be seen by - * the DMAR unit and used for page table lookup. PCI bridges may take - * ownership of transactions from downstream devices, so it may not be - * the same as the BSF of the target device. In those cases, all - * devices downstream of the bridge must share a single mapping - * domain, and must collectively be assigned to use either DMAR or - * bounce mapping. - */ -device_t -dmar_get_requester(device_t dev, uint16_t *rid) -{ - devclass_t pci_class; - device_t l, pci, pcib, pcip, pcibp, requester; - int cap_offset; - uint16_t pcie_flags; - bool bridge_is_pcie; - - pci_class = devclass_find("pci"); - l = requester = dev; - - *rid = pci_get_rid(dev); - - /* - * Walk the bridge hierarchy from the target device to the - * host port to find the translating bridge nearest the DMAR - * unit. - */ - for (;;) { - pci = device_get_parent(l); - KASSERT(pci != NULL, ("dmar_get_requester(%s): NULL parent " - "for %s", device_get_name(dev), device_get_name(l))); - KASSERT(device_get_devclass(pci) == pci_class, - ("dmar_get_requester(%s): non-pci parent %s for %s", - device_get_name(dev), device_get_name(pci), - device_get_name(l))); - - pcib = device_get_parent(pci); - KASSERT(pcib != NULL, ("dmar_get_requester(%s): NULL bridge " - "for %s", device_get_name(dev), device_get_name(pci))); - - /* - * The parent of our "bridge" isn't another PCI bus, - * so pcib isn't a PCI->PCI bridge but rather a host - * port, and the requester ID won't be translated - * further. - */ - pcip = device_get_parent(pcib); - if (device_get_devclass(pcip) != pci_class) - break; - pcibp = device_get_parent(pcip); - - if (pci_find_cap(l, PCIY_EXPRESS, &cap_offset) == 0) { - /* - * Do not stop the loop even if the target - * device is PCIe, because it is possible (but - * unlikely) to have a PCI->PCIe bridge - * somewhere in the hierarchy. - */ - l = pcib; - } else { - /* - * Device is not PCIe, it cannot be seen as a - * requester by DMAR unit. Check whether the - * bridge is PCIe. - */ - bridge_is_pcie = pci_find_cap(pcib, PCIY_EXPRESS, - &cap_offset) == 0; - requester = pcib; - - /* - * Check for a buggy PCIe/PCI bridge that - * doesn't report the express capability. If - * the bridge above it is express but isn't a - * PCI bridge, then we know pcib is actually a - * PCIe/PCI bridge. - */ - if (!bridge_is_pcie && pci_find_cap(pcibp, - PCIY_EXPRESS, &cap_offset) == 0) { - pcie_flags = pci_read_config(pcibp, - cap_offset + PCIER_FLAGS, 2); - if ((pcie_flags & PCIEM_FLAGS_TYPE) != - PCIEM_TYPE_PCI_BRIDGE) - bridge_is_pcie = true; - } - - if (bridge_is_pcie) { - /* - * The current device is not PCIe, but - * the bridge above it is. This is a - * PCIe->PCI bridge. Assume that the - * requester ID will be the secondary - * bus number with slot and function - * set to zero. - * - * XXX: Doesn't handle the case where - * the bridge is PCIe->PCI-X, and the - * bridge will only take ownership of - * requests in some cases. We should - * provide context entries with the - * same page tables for taken and - * non-taken transactions. - */ - *rid = PCI_RID(pci_get_bus(l), 0, 0); - l = pcibp; - } else { - /* - * Neither the device nor the bridge - * above it are PCIe. This is a - * conventional PCI->PCI bridge, which - * will use the bridge's BSF as the - * requester ID. - */ - *rid = pci_get_rid(pcib); - l = pcib; - } - } - } - return (requester); -} - -struct dmar_ctx * -dmar_instantiate_ctx(struct dmar_unit *dmar, device_t dev, bool rmrr) -{ - device_t requester; - struct dmar_ctx *ctx; - bool disabled; - uint16_t rid; - - requester = dmar_get_requester(dev, &rid); - - /* - * If the user requested the IOMMU disabled for the device, we - * cannot disable the DMAR, due to possibility of other - * devices on the same DMAR still requiring translation. - * Instead provide the identity mapping for the device - * context. - */ - disabled = dmar_bus_dma_is_dev_disabled(pci_get_domain(requester), - pci_get_bus(requester), pci_get_slot(requester), - pci_get_function(requester)); - ctx = dmar_get_ctx_for_dev(dmar, requester, rid, disabled, rmrr); - if (ctx == NULL) - return (NULL); - if (disabled) { - /* - * Keep the first reference on context, release the - * later refs. - */ - DMAR_LOCK(dmar); - if ((ctx->flags & DMAR_CTX_DISABLED) == 0) { - ctx->flags |= DMAR_CTX_DISABLED; - DMAR_UNLOCK(dmar); - } else { - dmar_free_ctx_locked(dmar, ctx); - } - ctx = NULL; - } - return (ctx); -} - -bus_dma_tag_t -dmar_get_dma_tag(device_t dev, device_t child) -{ - struct dmar_unit *dmar; - struct dmar_ctx *ctx; - bus_dma_tag_t res; - - dmar = dmar_find(child, bootverbose); - /* Not in scope of any DMAR ? */ - if (dmar == NULL) - return (NULL); - if (!dmar->dma_enabled) - return (NULL); - dmar_quirks_pre_use(dmar); - dmar_instantiate_rmrr_ctxs(dmar); - - ctx = dmar_instantiate_ctx(dmar, child, false); - res = ctx == NULL ? NULL : (bus_dma_tag_t)&ctx->ctx_tag; - return (res); -} - -bool -bus_dma_dmar_set_buswide(device_t dev) -{ - struct dmar_unit *dmar; - device_t parent; - u_int busno, slot, func; - - parent = device_get_parent(dev); - if (device_get_devclass(parent) != devclass_find("pci")) - return (false); - dmar = dmar_find(dev, bootverbose); - if (dmar == NULL) - return (false); - busno = pci_get_bus(dev); - slot = pci_get_slot(dev); - func = pci_get_function(dev); - if (slot != 0 || func != 0) { - if (bootverbose) { - device_printf(dev, - "dmar%d pci%d:%d:%d requested buswide busdma\n", - dmar->unit, busno, slot, func); - } - return (false); - } - dmar_set_buswide_ctx(dmar, busno); - return (true); -} - -static MALLOC_DEFINE(M_DMAR_DMAMAP, "dmar_dmamap", "Intel DMAR DMA Map"); - -static void dmar_bus_schedule_dmamap(struct dmar_unit *unit, - struct bus_dmamap_dmar *map); - -static int -dmar_bus_dma_tag_create(bus_dma_tag_t parent, bus_size_t alignment, - bus_addr_t boundary, bus_addr_t lowaddr, bus_addr_t highaddr, - bus_dma_filter_t *filter, void *filterarg, bus_size_t maxsize, - int nsegments, bus_size_t maxsegsz, int flags, bus_dma_lock_t *lockfunc, - void *lockfuncarg, bus_dma_tag_t *dmat) -{ - struct bus_dma_tag_dmar *newtag, *oldtag; - int error; - - *dmat = NULL; - error = common_bus_dma_tag_create(parent != NULL ? - &((struct bus_dma_tag_dmar *)parent)->common : NULL, alignment, - boundary, lowaddr, highaddr, filter, filterarg, maxsize, - nsegments, maxsegsz, flags, lockfunc, lockfuncarg, - sizeof(struct bus_dma_tag_dmar), (void **)&newtag); - if (error != 0) - goto out; - - oldtag = (struct bus_dma_tag_dmar *)parent; - newtag->common.impl = &bus_dma_dmar_impl; - newtag->ctx = oldtag->ctx; - newtag->owner = oldtag->owner; - - *dmat = (bus_dma_tag_t)newtag; -out: - CTR4(KTR_BUSDMA, "%s returned tag %p tag flags 0x%x error %d", - __func__, newtag, (newtag != NULL ? newtag->common.flags : 0), - error); - return (error); -} - -static int -dmar_bus_dma_tag_set_domain(bus_dma_tag_t dmat) -{ - - return (0); -} - -static int -dmar_bus_dma_tag_destroy(bus_dma_tag_t dmat1) -{ - struct bus_dma_tag_dmar *dmat, *dmat_copy, *parent; - int error; - - error = 0; - dmat_copy = dmat = (struct bus_dma_tag_dmar *)dmat1; - - if (dmat != NULL) { - if (dmat->map_count != 0) { - error = EBUSY; - goto out; - } - while (dmat != NULL) { - parent = (struct bus_dma_tag_dmar *)dmat->common.parent; - if (atomic_fetchadd_int(&dmat->common.ref_count, -1) == - 1) { - if (dmat == &dmat->ctx->ctx_tag) - dmar_free_ctx(dmat->ctx); - free_domain(dmat->segments, M_DMAR_DMAMAP); - free(dmat, M_DEVBUF); - dmat = parent; - } else - dmat = NULL; - } - } -out: - CTR3(KTR_BUSDMA, "%s tag %p error %d", __func__, dmat_copy, error); - return (error); -} - -static bool -dmar_bus_dma_id_mapped(bus_dma_tag_t dmat, vm_paddr_t buf, bus_size_t buflen) -{ - - return (false); -} - -static int -dmar_bus_dmamap_create(bus_dma_tag_t dmat, int flags, bus_dmamap_t *mapp) -{ - struct bus_dma_tag_dmar *tag; - struct bus_dmamap_dmar *map; - - tag = (struct bus_dma_tag_dmar *)dmat; - map = malloc_domainset(sizeof(*map), M_DMAR_DMAMAP, - DOMAINSET_PREF(tag->common.domain), M_NOWAIT | M_ZERO); - if (map == NULL) { - *mapp = NULL; - return (ENOMEM); - } - if (tag->segments == NULL) { - tag->segments = malloc_domainset(sizeof(bus_dma_segment_t) * - tag->common.nsegments, M_DMAR_DMAMAP, - DOMAINSET_PREF(tag->common.domain), M_NOWAIT); - if (tag->segments == NULL) { - free_domain(map, M_DMAR_DMAMAP); - *mapp = NULL; - return (ENOMEM); - } - } - TAILQ_INIT(&map->map_entries); - map->tag = tag; - map->locked = true; - map->cansleep = false; - tag->map_count++; - *mapp = (bus_dmamap_t)map; - - return (0); -} - -static int -dmar_bus_dmamap_destroy(bus_dma_tag_t dmat, bus_dmamap_t map1) -{ - struct bus_dma_tag_dmar *tag; - struct bus_dmamap_dmar *map; - struct dmar_domain *domain; - - tag = (struct bus_dma_tag_dmar *)dmat; - map = (struct bus_dmamap_dmar *)map1; - if (map != NULL) { - domain = tag->ctx->domain; - DMAR_DOMAIN_LOCK(domain); - if (!TAILQ_EMPTY(&map->map_entries)) { - DMAR_DOMAIN_UNLOCK(domain); - return (EBUSY); - } - DMAR_DOMAIN_UNLOCK(domain); - free_domain(map, M_DMAR_DMAMAP); - } - tag->map_count--; - return (0); -} - - -static int -dmar_bus_dmamem_alloc(bus_dma_tag_t dmat, void** vaddr, int flags, - bus_dmamap_t *mapp) -{ - struct bus_dma_tag_dmar *tag; - struct bus_dmamap_dmar *map; - int error, mflags; - vm_memattr_t attr; - - error = dmar_bus_dmamap_create(dmat, flags, mapp); - if (error != 0) - return (error); - - mflags = (flags & BUS_DMA_NOWAIT) != 0 ? M_NOWAIT : M_WAITOK; - mflags |= (flags & BUS_DMA_ZERO) != 0 ? M_ZERO : 0; - attr = (flags & BUS_DMA_NOCACHE) != 0 ? VM_MEMATTR_UNCACHEABLE : - VM_MEMATTR_DEFAULT; - - tag = (struct bus_dma_tag_dmar *)dmat; - map = (struct bus_dmamap_dmar *)*mapp; - - if (tag->common.maxsize < PAGE_SIZE && - tag->common.alignment <= tag->common.maxsize && - attr == VM_MEMATTR_DEFAULT) { - *vaddr = malloc_domainset(tag->common.maxsize, M_DEVBUF, - DOMAINSET_PREF(tag->common.domain), mflags); - map->flags |= BUS_DMAMAP_DMAR_MALLOC; - } else { - *vaddr = (void *)kmem_alloc_attr_domainset( - DOMAINSET_PREF(tag->common.domain), tag->common.maxsize, - mflags, 0ul, BUS_SPACE_MAXADDR, attr); - map->flags |= BUS_DMAMAP_DMAR_KMEM_ALLOC; - } - if (*vaddr == NULL) { - dmar_bus_dmamap_destroy(dmat, *mapp); - *mapp = NULL; - return (ENOMEM); - } - return (0); -} - -static void -dmar_bus_dmamem_free(bus_dma_tag_t dmat, void *vaddr, bus_dmamap_t map1) -{ - struct bus_dma_tag_dmar *tag; - struct bus_dmamap_dmar *map; - - tag = (struct bus_dma_tag_dmar *)dmat; - map = (struct bus_dmamap_dmar *)map1; - - if ((map->flags & BUS_DMAMAP_DMAR_MALLOC) != 0) { - free_domain(vaddr, M_DEVBUF); - map->flags &= ~BUS_DMAMAP_DMAR_MALLOC; - } else { - KASSERT((map->flags & BUS_DMAMAP_DMAR_KMEM_ALLOC) != 0, - ("dmar_bus_dmamem_free for non alloced map %p", map)); - kmem_free((vm_offset_t)vaddr, tag->common.maxsize); - map->flags &= ~BUS_DMAMAP_DMAR_KMEM_ALLOC; - } - - dmar_bus_dmamap_destroy(dmat, map1); -} - -static int -dmar_bus_dmamap_load_something1(struct bus_dma_tag_dmar *tag, - struct bus_dmamap_dmar *map, vm_page_t *ma, int offset, bus_size_t buflen, - int flags, bus_dma_segment_t *segs, int *segp, - struct dmar_map_entries_tailq *unroll_list) -{ - struct dmar_ctx *ctx; - struct dmar_domain *domain; - struct dmar_map_entry *entry; - dmar_gaddr_t size; - bus_size_t buflen1; - int error, idx, gas_flags, seg; - - KASSERT(offset < DMAR_PAGE_SIZE, ("offset %d", offset)); - if (segs == NULL) - segs = tag->segments; - ctx = tag->ctx; - domain = ctx->domain; - seg = *segp; - error = 0; - idx = 0; - while (buflen > 0) { - seg++; - if (seg >= tag->common.nsegments) { - error = EFBIG; - break; - } - buflen1 = buflen > tag->common.maxsegsz ? - tag->common.maxsegsz : buflen; - size = round_page(offset + buflen1); - - /* - * (Too) optimistically allow split if there are more - * then one segments left. - */ - gas_flags = map->cansleep ? DMAR_GM_CANWAIT : 0; - if (seg + 1 < tag->common.nsegments) - gas_flags |= DMAR_GM_CANSPLIT; - - error = dmar_gas_map(domain, &tag->common, size, offset, - DMAR_MAP_ENTRY_READ | DMAR_MAP_ENTRY_WRITE, - gas_flags, ma + idx, &entry); - if (error != 0) - break; - if ((gas_flags & DMAR_GM_CANSPLIT) != 0) { - KASSERT(size >= entry->end - entry->start, - ("split increased entry size %jx %jx %jx", - (uintmax_t)size, (uintmax_t)entry->start, - (uintmax_t)entry->end)); - size = entry->end - entry->start; - if (buflen1 > size) - buflen1 = size; - } else { - KASSERT(entry->end - entry->start == size, - ("no split allowed %jx %jx %jx", - (uintmax_t)size, (uintmax_t)entry->start, - (uintmax_t)entry->end)); - } - if (offset + buflen1 > size) - buflen1 = size - offset; - if (buflen1 > tag->common.maxsegsz) - buflen1 = tag->common.maxsegsz; - - KASSERT(((entry->start + offset) & (tag->common.alignment - 1)) - == 0, - ("alignment failed: ctx %p start 0x%jx offset %x " - "align 0x%jx", ctx, (uintmax_t)entry->start, offset, - (uintmax_t)tag->common.alignment)); - KASSERT(entry->end <= tag->common.lowaddr || - entry->start >= tag->common.highaddr, - ("entry placement failed: ctx %p start 0x%jx end 0x%jx " - "lowaddr 0x%jx highaddr 0x%jx", ctx, - (uintmax_t)entry->start, (uintmax_t)entry->end, - (uintmax_t)tag->common.lowaddr, - (uintmax_t)tag->common.highaddr)); - KASSERT(dmar_test_boundary(entry->start + offset, buflen1, - tag->common.boundary), - ("boundary failed: ctx %p start 0x%jx end 0x%jx " - "boundary 0x%jx", ctx, (uintmax_t)entry->start, - (uintmax_t)entry->end, (uintmax_t)tag->common.boundary)); - KASSERT(buflen1 <= tag->common.maxsegsz, - ("segment too large: ctx %p start 0x%jx end 0x%jx " - "buflen1 0x%jx maxsegsz 0x%jx", ctx, - (uintmax_t)entry->start, (uintmax_t)entry->end, - (uintmax_t)buflen1, (uintmax_t)tag->common.maxsegsz)); - - DMAR_DOMAIN_LOCK(domain); - TAILQ_INSERT_TAIL(&map->map_entries, entry, dmamap_link); - entry->flags |= DMAR_MAP_ENTRY_MAP; - DMAR_DOMAIN_UNLOCK(domain); - TAILQ_INSERT_TAIL(unroll_list, entry, unroll_link); - - segs[seg].ds_addr = entry->start + offset; - segs[seg].ds_len = buflen1; - - idx += OFF_TO_IDX(trunc_page(offset + buflen1)); - offset += buflen1; - offset &= DMAR_PAGE_MASK; - buflen -= buflen1; - } - if (error == 0) - *segp = seg; - return (error); -} - -static int -dmar_bus_dmamap_load_something(struct bus_dma_tag_dmar *tag, - struct bus_dmamap_dmar *map, vm_page_t *ma, int offset, bus_size_t buflen, - int flags, bus_dma_segment_t *segs, int *segp) -{ - struct dmar_ctx *ctx; - struct dmar_domain *domain; - struct dmar_map_entry *entry, *entry1; - struct dmar_map_entries_tailq unroll_list; - int error; - - ctx = tag->ctx; - domain = ctx->domain; - atomic_add_long(&ctx->loads, 1); - - TAILQ_INIT(&unroll_list); - error = dmar_bus_dmamap_load_something1(tag, map, ma, offset, - buflen, flags, segs, segp, &unroll_list); - if (error != 0) { - /* - * The busdma interface does not allow us to report - * partial buffer load, so unfortunately we have to - * revert all work done. - */ - DMAR_DOMAIN_LOCK(domain); - TAILQ_FOREACH_SAFE(entry, &unroll_list, unroll_link, - entry1) { - /* - * No entries other than what we have created - * during the failed run might have been - * inserted there in between, since we own ctx - * pglock. - */ - TAILQ_REMOVE(&map->map_entries, entry, dmamap_link); - TAILQ_REMOVE(&unroll_list, entry, unroll_link); - TAILQ_INSERT_TAIL(&domain->unload_entries, entry, - dmamap_link); - } - DMAR_DOMAIN_UNLOCK(domain); - taskqueue_enqueue(domain->dmar->delayed_taskqueue, - &domain->unload_task); - } - - if (error == ENOMEM && (flags & BUS_DMA_NOWAIT) == 0 && - !map->cansleep) - error = EINPROGRESS; - if (error == EINPROGRESS) - dmar_bus_schedule_dmamap(domain->dmar, map); - return (error); -} - -static int -dmar_bus_dmamap_load_ma(bus_dma_tag_t dmat, bus_dmamap_t map1, - struct vm_page **ma, bus_size_t tlen, int ma_offs, int flags, - bus_dma_segment_t *segs, int *segp) -{ - struct bus_dma_tag_dmar *tag; - struct bus_dmamap_dmar *map; - - tag = (struct bus_dma_tag_dmar *)dmat; - map = (struct bus_dmamap_dmar *)map1; - return (dmar_bus_dmamap_load_something(tag, map, ma, ma_offs, tlen, - flags, segs, segp)); -} - -static int -dmar_bus_dmamap_load_phys(bus_dma_tag_t dmat, bus_dmamap_t map1, - vm_paddr_t buf, bus_size_t buflen, int flags, bus_dma_segment_t *segs, - int *segp) -{ - struct bus_dma_tag_dmar *tag; - struct bus_dmamap_dmar *map; - vm_page_t *ma; - vm_paddr_t pstart, pend; - int error, i, ma_cnt, offset; - - tag = (struct bus_dma_tag_dmar *)dmat; - map = (struct bus_dmamap_dmar *)map1; - pstart = trunc_page(buf); - pend = round_page(buf + buflen); - offset = buf & PAGE_MASK; - ma_cnt = OFF_TO_IDX(pend - pstart); - ma = malloc(sizeof(vm_page_t) * ma_cnt, M_DEVBUF, map->cansleep ? - M_WAITOK : M_NOWAIT); - if (ma == NULL) - return (ENOMEM); - for (i = 0; i < ma_cnt; i++) - ma[i] = PHYS_TO_VM_PAGE(pstart + i * PAGE_SIZE); - error = dmar_bus_dmamap_load_something(tag, map, ma, offset, buflen, - flags, segs, segp); - free(ma, M_DEVBUF); - return (error); -} - -static int -dmar_bus_dmamap_load_buffer(bus_dma_tag_t dmat, bus_dmamap_t map1, void *buf, - bus_size_t buflen, pmap_t pmap, int flags, bus_dma_segment_t *segs, - int *segp) -{ - struct bus_dma_tag_dmar *tag; - struct bus_dmamap_dmar *map; - vm_page_t *ma, fma; - vm_paddr_t pstart, pend, paddr; - int error, i, ma_cnt, offset; - - tag = (struct bus_dma_tag_dmar *)dmat; - map = (struct bus_dmamap_dmar *)map1; - pstart = trunc_page((vm_offset_t)buf); - pend = round_page((vm_offset_t)buf + buflen); - offset = (vm_offset_t)buf & PAGE_MASK; - ma_cnt = OFF_TO_IDX(pend - pstart); - ma = malloc(sizeof(vm_page_t) * ma_cnt, M_DEVBUF, map->cansleep ? - M_WAITOK : M_NOWAIT); - if (ma == NULL) - return (ENOMEM); - if (dumping) { - /* - * If dumping, do not attempt to call - * PHYS_TO_VM_PAGE() at all. It may return non-NULL - * but the vm_page returned might be not initialized, - * e.g. for the kernel itself. - */ - KASSERT(pmap == kernel_pmap, ("non-kernel address write")); - fma = malloc(sizeof(struct vm_page) * ma_cnt, M_DEVBUF, - M_ZERO | (map->cansleep ? M_WAITOK : M_NOWAIT)); - if (fma == NULL) { - free(ma, M_DEVBUF); - return (ENOMEM); - } - for (i = 0; i < ma_cnt; i++, pstart += PAGE_SIZE) { - paddr = pmap_kextract(pstart); - vm_page_initfake(&fma[i], paddr, VM_MEMATTR_DEFAULT); - ma[i] = &fma[i]; - } - } else { - fma = NULL; - for (i = 0; i < ma_cnt; i++, pstart += PAGE_SIZE) { - if (pmap == kernel_pmap) - paddr = pmap_kextract(pstart); - else - paddr = pmap_extract(pmap, pstart); - ma[i] = PHYS_TO_VM_PAGE(paddr); - KASSERT(VM_PAGE_TO_PHYS(ma[i]) == paddr, - ("PHYS_TO_VM_PAGE failed %jx %jx m %p", - (uintmax_t)paddr, (uintmax_t)VM_PAGE_TO_PHYS(ma[i]), - ma[i])); - } - } - error = dmar_bus_dmamap_load_something(tag, map, ma, offset, buflen, - flags, segs, segp); - free(ma, M_DEVBUF); - free(fma, M_DEVBUF); - return (error); -} - -static void -dmar_bus_dmamap_waitok(bus_dma_tag_t dmat, bus_dmamap_t map1, - struct memdesc *mem, bus_dmamap_callback_t *callback, void *callback_arg) -{ - struct bus_dmamap_dmar *map; - - if (map1 == NULL) - return; - map = (struct bus_dmamap_dmar *)map1; - map->mem = *mem; - map->tag = (struct bus_dma_tag_dmar *)dmat; - map->callback = callback; - map->callback_arg = callback_arg; -} - -static bus_dma_segment_t * -dmar_bus_dmamap_complete(bus_dma_tag_t dmat, bus_dmamap_t map1, - bus_dma_segment_t *segs, int nsegs, int error) -{ - struct bus_dma_tag_dmar *tag; - struct bus_dmamap_dmar *map; - - tag = (struct bus_dma_tag_dmar *)dmat; - map = (struct bus_dmamap_dmar *)map1; - - if (!map->locked) { - KASSERT(map->cansleep, - ("map not locked and not sleepable context %p", map)); - - /* - * We are called from the delayed context. Relock the - * driver. - */ - (tag->common.lockfunc)(tag->common.lockfuncarg, BUS_DMA_LOCK); - map->locked = true; - } - - if (segs == NULL) - segs = tag->segments; - return (segs); -} - -/* - * The limitations of busdma KPI forces the dmar to perform the actual - * unload, consisting of the unmapping of the map entries page tables, - * from the delayed context on i386, since page table page mapping - * might require a sleep to be successfull. The unfortunate - * consequence is that the DMA requests can be served some time after - * the bus_dmamap_unload() call returned. - * - * On amd64, we assume that sf allocation cannot fail. - */ -static void -dmar_bus_dmamap_unload(bus_dma_tag_t dmat, bus_dmamap_t map1) -{ - struct bus_dma_tag_dmar *tag; - struct bus_dmamap_dmar *map; - struct dmar_ctx *ctx; - struct dmar_domain *domain; -#if defined(__amd64__) - struct dmar_map_entries_tailq entries; -#endif - - tag = (struct bus_dma_tag_dmar *)dmat; - map = (struct bus_dmamap_dmar *)map1; - ctx = tag->ctx; - domain = ctx->domain; - atomic_add_long(&ctx->unloads, 1); - -#if defined(__i386__) - DMAR_DOMAIN_LOCK(domain); - TAILQ_CONCAT(&domain->unload_entries, &map->map_entries, dmamap_link); - DMAR_DOMAIN_UNLOCK(domain); - taskqueue_enqueue(domain->dmar->delayed_taskqueue, - &domain->unload_task); -#else /* defined(__amd64__) */ - TAILQ_INIT(&entries); - DMAR_DOMAIN_LOCK(domain); - TAILQ_CONCAT(&entries, &map->map_entries, dmamap_link); - DMAR_DOMAIN_UNLOCK(domain); - THREAD_NO_SLEEPING(); - dmar_domain_unload(domain, &entries, false); - THREAD_SLEEPING_OK(); - KASSERT(TAILQ_EMPTY(&entries), ("lazy dmar_ctx_unload %p", ctx)); -#endif -} - -static void -dmar_bus_dmamap_sync(bus_dma_tag_t dmat, bus_dmamap_t map, - bus_dmasync_op_t op) -{ -} - -struct bus_dma_impl bus_dma_dmar_impl = { - .tag_create = dmar_bus_dma_tag_create, - .tag_destroy = dmar_bus_dma_tag_destroy, - .tag_set_domain = dmar_bus_dma_tag_set_domain, - .id_mapped = dmar_bus_dma_id_mapped, - .map_create = dmar_bus_dmamap_create, - .map_destroy = dmar_bus_dmamap_destroy, - .mem_alloc = dmar_bus_dmamem_alloc, - .mem_free = dmar_bus_dmamem_free, - .load_phys = dmar_bus_dmamap_load_phys, - .load_buffer = dmar_bus_dmamap_load_buffer, - .load_ma = dmar_bus_dmamap_load_ma, - .map_waitok = dmar_bus_dmamap_waitok, - .map_complete = dmar_bus_dmamap_complete, - .map_unload = dmar_bus_dmamap_unload, - .map_sync = dmar_bus_dmamap_sync, -}; - -static void -dmar_bus_task_dmamap(void *arg, int pending) -{ - struct bus_dma_tag_dmar *tag; - struct bus_dmamap_dmar *map; - struct dmar_unit *unit; - - unit = arg; - DMAR_LOCK(unit); - while ((map = TAILQ_FIRST(&unit->delayed_maps)) != NULL) { - TAILQ_REMOVE(&unit->delayed_maps, map, delay_link); - DMAR_UNLOCK(unit); - tag = map->tag; - map->cansleep = true; - map->locked = false; - bus_dmamap_load_mem((bus_dma_tag_t)tag, (bus_dmamap_t)map, - &map->mem, map->callback, map->callback_arg, - BUS_DMA_WAITOK); - map->cansleep = false; - if (map->locked) { - (tag->common.lockfunc)(tag->common.lockfuncarg, - BUS_DMA_UNLOCK); - } else - map->locked = true; - map->cansleep = false; - DMAR_LOCK(unit); - } - DMAR_UNLOCK(unit); -} - -static void -dmar_bus_schedule_dmamap(struct dmar_unit *unit, struct bus_dmamap_dmar *map) -{ - - map->locked = false; - DMAR_LOCK(unit); - TAILQ_INSERT_TAIL(&unit->delayed_maps, map, delay_link); - DMAR_UNLOCK(unit); - taskqueue_enqueue(unit->delayed_taskqueue, &unit->dmamap_load_task); -} - -int -dmar_init_busdma(struct dmar_unit *unit) -{ - - unit->dma_enabled = 1; - TUNABLE_INT_FETCH("hw.dmar.dma", &unit->dma_enabled); - TAILQ_INIT(&unit->delayed_maps); - TASK_INIT(&unit->dmamap_load_task, 0, dmar_bus_task_dmamap, unit); - unit->delayed_taskqueue = taskqueue_create("dmar", M_WAITOK, - taskqueue_thread_enqueue, &unit->delayed_taskqueue); - taskqueue_start_threads(&unit->delayed_taskqueue, 1, PI_DISK, - "dmar%d busdma taskq", unit->unit); - return (0); -} - -void -dmar_fini_busdma(struct dmar_unit *unit) -{ - - if (unit->delayed_taskqueue == NULL) - return; - - taskqueue_drain(unit->delayed_taskqueue, &unit->dmamap_load_task); - taskqueue_free(unit->delayed_taskqueue); - unit->delayed_taskqueue = NULL; -} - -int -bus_dma_dmar_load_ident(bus_dma_tag_t dmat, bus_dmamap_t map1, - vm_paddr_t start, vm_size_t length, int flags) -{ - struct bus_dma_tag_common *tc; - struct bus_dma_tag_dmar *tag; - struct bus_dmamap_dmar *map; - struct dmar_ctx *ctx; - struct dmar_domain *domain; - struct dmar_map_entry *entry; - vm_page_t *ma; - vm_size_t i; - int error; - bool waitok; - - MPASS((start & PAGE_MASK) == 0); - MPASS((length & PAGE_MASK) == 0); - MPASS(length > 0); - MPASS(start + length >= start); - MPASS((flags & ~(BUS_DMA_NOWAIT | BUS_DMA_NOWRITE)) == 0); - - tc = (struct bus_dma_tag_common *)dmat; - if (tc->impl != &bus_dma_dmar_impl) - return (0); - - tag = (struct bus_dma_tag_dmar *)dmat; - ctx = tag->ctx; - domain = ctx->domain; - map = (struct bus_dmamap_dmar *)map1; - waitok = (flags & BUS_DMA_NOWAIT) != 0; - - entry = dmar_gas_alloc_entry(domain, waitok ? 0 : DMAR_PGF_WAITOK); - if (entry == NULL) - return (ENOMEM); - entry->start = start; - entry->end = start + length; - ma = malloc(sizeof(vm_page_t) * atop(length), M_TEMP, waitok ? - M_WAITOK : M_NOWAIT); - if (ma == NULL) { - dmar_gas_free_entry(domain, entry); - return (ENOMEM); - } - for (i = 0; i < atop(length); i++) { - ma[i] = vm_page_getfake(entry->start + PAGE_SIZE * i, - VM_MEMATTR_DEFAULT); - } - error = dmar_gas_map_region(domain, entry, DMAR_MAP_ENTRY_READ | - ((flags & BUS_DMA_NOWRITE) ? 0 : DMAR_MAP_ENTRY_WRITE), - waitok ? DMAR_GM_CANWAIT : 0, ma); - if (error == 0) { - DMAR_DOMAIN_LOCK(domain); - TAILQ_INSERT_TAIL(&map->map_entries, entry, dmamap_link); - entry->flags |= DMAR_MAP_ENTRY_MAP; - DMAR_DOMAIN_UNLOCK(domain); - } else { - dmar_domain_unload_entry(entry, true); - } - for (i = 0; i < atop(length); i++) - vm_page_putfake(ma[i]); - free(ma, M_TEMP); - return (error); -} diff --git a/sys/x86/iommu/busdma_dmar.h b/sys/x86/iommu/busdma_dmar.h deleted file mode 100644 index fadd923baa8..00000000000 --- a/sys/x86/iommu/busdma_dmar.h +++ /dev/null @@ -1,66 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2013 The FreeBSD Foundation - * All rights reserved. - * - * This software was developed by Konstantin Belousov - * under sponsorship from the FreeBSD Foundation. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - */ - -#ifndef __X86_IOMMU_BUSDMA_DMAR_H -#define __X86_IOMMU_BUSDMA_DMAR_H - -struct dmar_map_entry; -TAILQ_HEAD(dmar_map_entries_tailq, dmar_map_entry); - -struct bus_dma_tag_dmar { - struct bus_dma_tag_common common; - struct dmar_ctx *ctx; - device_t owner; - int map_count; - bus_dma_segment_t *segments; -}; - -struct bus_dmamap_dmar { - struct bus_dma_tag_dmar *tag; - struct memdesc mem; - bus_dmamap_callback_t *callback; - void *callback_arg; - struct dmar_map_entries_tailq map_entries; - TAILQ_ENTRY(bus_dmamap_dmar) delay_link; - bool locked; - bool cansleep; - int flags; -}; - -#define BUS_DMAMAP_DMAR_MALLOC 0x0001 -#define BUS_DMAMAP_DMAR_KMEM_ALLOC 0x0002 - -extern struct bus_dma_impl bus_dma_dmar_impl; - -bus_dma_tag_t dmar_get_dma_tag(device_t dev, device_t child); - -#endif diff --git a/sys/x86/iommu/intel_gas.c b/sys/x86/iommu/intel_gas.c deleted file mode 100644 index ba707bcd26a..00000000000 --- a/sys/x86/iommu/intel_gas.c +++ /dev/null @@ -1,744 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2013 The FreeBSD Foundation - * All rights reserved. - * - * This software was developed by Konstantin Belousov - * under sponsorship from the FreeBSD Foundation. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include - -#define RB_AUGMENT(entry) dmar_gas_augment_entry(entry) - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* - * Guest Address Space management. - */ - -static uma_zone_t dmar_map_entry_zone; - -static void -intel_gas_init(void) -{ - - dmar_map_entry_zone = uma_zcreate("DMAR_MAP_ENTRY", - sizeof(struct dmar_map_entry), NULL, NULL, - NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_NODUMP); -} -SYSINIT(intel_gas, SI_SUB_DRIVERS, SI_ORDER_FIRST, intel_gas_init, NULL); - -struct dmar_map_entry * -dmar_gas_alloc_entry(struct dmar_domain *domain, u_int flags) -{ - struct dmar_map_entry *res; - - KASSERT((flags & ~(DMAR_PGF_WAITOK)) == 0, - ("unsupported flags %x", flags)); - - res = uma_zalloc(dmar_map_entry_zone, ((flags & DMAR_PGF_WAITOK) != - 0 ? M_WAITOK : M_NOWAIT) | M_ZERO); - if (res != NULL) { - res->domain = domain; - atomic_add_int(&domain->entries_cnt, 1); - } - return (res); -} - -void -dmar_gas_free_entry(struct dmar_domain *domain, struct dmar_map_entry *entry) -{ - - KASSERT(domain == entry->domain, - ("mismatched free domain %p entry %p entry->domain %p", domain, - entry, entry->domain)); - atomic_subtract_int(&domain->entries_cnt, 1); - uma_zfree(dmar_map_entry_zone, entry); -} - -static int -dmar_gas_cmp_entries(struct dmar_map_entry *a, struct dmar_map_entry *b) -{ - - /* Last entry have zero size, so <= */ - KASSERT(a->start <= a->end, ("inverted entry %p (%jx, %jx)", - a, (uintmax_t)a->start, (uintmax_t)a->end)); - KASSERT(b->start <= b->end, ("inverted entry %p (%jx, %jx)", - b, (uintmax_t)b->start, (uintmax_t)b->end)); - KASSERT(a->end <= b->start || b->end <= a->start || - a->end == a->start || b->end == b->start, - ("overlapping entries %p (%jx, %jx) %p (%jx, %jx)", - a, (uintmax_t)a->start, (uintmax_t)a->end, - b, (uintmax_t)b->start, (uintmax_t)b->end)); - - if (a->end < b->end) - return (-1); - else if (b->end < a->end) - return (1); - return (0); -} - -static void -dmar_gas_augment_entry(struct dmar_map_entry *entry) -{ - struct dmar_map_entry *l, *r; - - for (; entry != NULL; entry = RB_PARENT(entry, rb_entry)) { - l = RB_LEFT(entry, rb_entry); - r = RB_RIGHT(entry, rb_entry); - if (l == NULL && r == NULL) { - entry->free_down = entry->free_after; - } else if (l == NULL && r != NULL) { - entry->free_down = MAX(entry->free_after, r->free_down); - } else if (/*l != NULL && */ r == NULL) { - entry->free_down = MAX(entry->free_after, l->free_down); - } else /* if (l != NULL && r != NULL) */ { - entry->free_down = MAX(entry->free_after, l->free_down); - entry->free_down = MAX(entry->free_down, r->free_down); - } - } -} - -RB_GENERATE(dmar_gas_entries_tree, dmar_map_entry, rb_entry, - dmar_gas_cmp_entries); - -static void -dmar_gas_fix_free(struct dmar_domain *domain, struct dmar_map_entry *entry) -{ - struct dmar_map_entry *next; - - next = RB_NEXT(dmar_gas_entries_tree, &domain->rb_root, entry); - entry->free_after = (next != NULL ? next->start : domain->end) - - entry->end; - dmar_gas_augment_entry(entry); -} - -#ifdef INVARIANTS -static void -dmar_gas_check_free(struct dmar_domain *domain) -{ - struct dmar_map_entry *entry, *next, *l, *r; - dmar_gaddr_t v; - - RB_FOREACH(entry, dmar_gas_entries_tree, &domain->rb_root) { - KASSERT(domain == entry->domain, - ("mismatched free domain %p entry %p entry->domain %p", - domain, entry, entry->domain)); - next = RB_NEXT(dmar_gas_entries_tree, &domain->rb_root, entry); - if (next == NULL) { - MPASS(entry->free_after == domain->end - entry->end); - } else { - MPASS(entry->free_after = next->start - entry->end); - MPASS(entry->end <= next->start); - } - l = RB_LEFT(entry, rb_entry); - r = RB_RIGHT(entry, rb_entry); - if (l == NULL && r == NULL) { - MPASS(entry->free_down == entry->free_after); - } else if (l == NULL && r != NULL) { - MPASS(entry->free_down = MAX(entry->free_after, - r->free_down)); - } else if (r == NULL) { - MPASS(entry->free_down = MAX(entry->free_after, - l->free_down)); - } else { - v = MAX(entry->free_after, l->free_down); - v = MAX(v, r->free_down); - MPASS(entry->free_down == v); - } - } -} -#endif - -static bool -dmar_gas_rb_insert(struct dmar_domain *domain, struct dmar_map_entry *entry) -{ - struct dmar_map_entry *prev, *found; - - found = RB_INSERT(dmar_gas_entries_tree, &domain->rb_root, entry); - dmar_gas_fix_free(domain, entry); - prev = RB_PREV(dmar_gas_entries_tree, &domain->rb_root, entry); - if (prev != NULL) - dmar_gas_fix_free(domain, prev); - return (found == NULL); -} - -static void -dmar_gas_rb_remove(struct dmar_domain *domain, struct dmar_map_entry *entry) -{ - struct dmar_map_entry *prev; - - prev = RB_PREV(dmar_gas_entries_tree, &domain->rb_root, entry); - RB_REMOVE(dmar_gas_entries_tree, &domain->rb_root, entry); - if (prev != NULL) - dmar_gas_fix_free(domain, prev); -} - -void -dmar_gas_init_domain(struct dmar_domain *domain) -{ - struct dmar_map_entry *begin, *end; - - begin = dmar_gas_alloc_entry(domain, DMAR_PGF_WAITOK); - end = dmar_gas_alloc_entry(domain, DMAR_PGF_WAITOK); - - DMAR_DOMAIN_LOCK(domain); - KASSERT(domain->entries_cnt == 2, ("dirty domain %p", domain)); - KASSERT(RB_EMPTY(&domain->rb_root), ("non-empty entries %p", domain)); - - begin->start = 0; - begin->end = DMAR_PAGE_SIZE; - begin->free_after = domain->end - begin->end; - begin->flags = DMAR_MAP_ENTRY_PLACE | DMAR_MAP_ENTRY_UNMAPPED; - dmar_gas_rb_insert(domain, begin); - - end->start = domain->end; - end->end = domain->end; - end->free_after = 0; - end->flags = DMAR_MAP_ENTRY_PLACE | DMAR_MAP_ENTRY_UNMAPPED; - dmar_gas_rb_insert(domain, end); - - domain->first_place = begin; - domain->last_place = end; - domain->flags |= DMAR_DOMAIN_GAS_INITED; - DMAR_DOMAIN_UNLOCK(domain); -} - -void -dmar_gas_fini_domain(struct dmar_domain *domain) -{ - struct dmar_map_entry *entry, *entry1; - - DMAR_DOMAIN_ASSERT_LOCKED(domain); - KASSERT(domain->entries_cnt == 2, ("domain still in use %p", domain)); - - entry = RB_MIN(dmar_gas_entries_tree, &domain->rb_root); - KASSERT(entry->start == 0, ("start entry start %p", domain)); - KASSERT(entry->end == DMAR_PAGE_SIZE, ("start entry end %p", domain)); - KASSERT(entry->flags == DMAR_MAP_ENTRY_PLACE, - ("start entry flags %p", domain)); - RB_REMOVE(dmar_gas_entries_tree, &domain->rb_root, entry); - dmar_gas_free_entry(domain, entry); - - entry = RB_MAX(dmar_gas_entries_tree, &domain->rb_root); - KASSERT(entry->start == domain->end, ("end entry start %p", domain)); - KASSERT(entry->end == domain->end, ("end entry end %p", domain)); - KASSERT(entry->free_after == 0, ("end entry free_after %p", domain)); - KASSERT(entry->flags == DMAR_MAP_ENTRY_PLACE, - ("end entry flags %p", domain)); - RB_REMOVE(dmar_gas_entries_tree, &domain->rb_root, entry); - dmar_gas_free_entry(domain, entry); - - RB_FOREACH_SAFE(entry, dmar_gas_entries_tree, &domain->rb_root, - entry1) { - KASSERT((entry->flags & DMAR_MAP_ENTRY_RMRR) != 0, - ("non-RMRR entry left %p", domain)); - RB_REMOVE(dmar_gas_entries_tree, &domain->rb_root, entry); - dmar_gas_free_entry(domain, entry); - } -} - -struct dmar_gas_match_args { - struct dmar_domain *domain; - dmar_gaddr_t size; - int offset; - const struct bus_dma_tag_common *common; - u_int gas_flags; - struct dmar_map_entry *entry; -}; - -static bool -dmar_gas_match_one(struct dmar_gas_match_args *a, struct dmar_map_entry *prev, - dmar_gaddr_t end) -{ - dmar_gaddr_t bs, start; - - if (a->entry->start + a->size > end) - return (false); - - /* DMAR_PAGE_SIZE to create gap after new entry. */ - if (a->entry->start < prev->end + DMAR_PAGE_SIZE || - a->entry->start + a->size + a->offset + DMAR_PAGE_SIZE > - prev->end + prev->free_after) - return (false); - - /* No boundary crossing. */ - if (dmar_test_boundary(a->entry->start + a->offset, a->size, - a->common->boundary)) - return (true); - - /* - * The start + offset to start + offset + size region crosses - * the boundary. Check if there is enough space after the - * next boundary after the prev->end. - */ - bs = rounddown2(a->entry->start + a->offset + a->common->boundary, - a->common->boundary); - start = roundup2(bs, a->common->alignment); - /* DMAR_PAGE_SIZE to create gap after new entry. */ - if (start + a->offset + a->size + DMAR_PAGE_SIZE <= - prev->end + prev->free_after && - start + a->offset + a->size <= end && - dmar_test_boundary(start + a->offset, a->size, - a->common->boundary)) { - a->entry->start = start; - return (true); - } - - /* - * Not enough space to align at the requested boundary, or - * boundary is smaller than the size, but allowed to split. - * We already checked that start + size does not overlap end. - * - * XXXKIB. It is possible that bs is exactly at the start of - * the next entry, then we do not have gap. Ignore for now. - */ - if ((a->gas_flags & DMAR_GM_CANSPLIT) != 0) { - a->size = bs - a->entry->start; - return (true); - } - - return (false); -} - -static void -dmar_gas_match_insert(struct dmar_gas_match_args *a, - struct dmar_map_entry *prev) -{ - struct dmar_map_entry *next; - bool found; - - /* - * The prev->end is always aligned on the page size, which - * causes page alignment for the entry->start too. The size - * is checked to be multiple of the page size. - * - * The page sized gap is created between consequent - * allocations to ensure that out-of-bounds accesses fault. - */ - a->entry->end = a->entry->start + a->size; - - next = RB_NEXT(dmar_gas_entries_tree, &a->domain->rb_root, prev); - KASSERT(next->start >= a->entry->end && - next->start - a->entry->start >= a->size && - prev->end <= a->entry->end, - ("dmar_gas_match_insert hole failed %p prev (%jx, %jx) " - "free_after %jx next (%jx, %jx) entry (%jx, %jx)", a->domain, - (uintmax_t)prev->start, (uintmax_t)prev->end, - (uintmax_t)prev->free_after, - (uintmax_t)next->start, (uintmax_t)next->end, - (uintmax_t)a->entry->start, (uintmax_t)a->entry->end)); - - prev->free_after = a->entry->start - prev->end; - a->entry->free_after = next->start - a->entry->end; - - found = dmar_gas_rb_insert(a->domain, a->entry); - KASSERT(found, ("found dup %p start %jx size %jx", - a->domain, (uintmax_t)a->entry->start, (uintmax_t)a->size)); - a->entry->flags = DMAR_MAP_ENTRY_MAP; - - KASSERT(RB_PREV(dmar_gas_entries_tree, &a->domain->rb_root, - a->entry) == prev, - ("entry %p prev %p inserted prev %p", a->entry, prev, - RB_PREV(dmar_gas_entries_tree, &a->domain->rb_root, a->entry))); - KASSERT(RB_NEXT(dmar_gas_entries_tree, &a->domain->rb_root, - a->entry) == next, - ("entry %p next %p inserted next %p", a->entry, next, - RB_NEXT(dmar_gas_entries_tree, &a->domain->rb_root, a->entry))); -} - -static int -dmar_gas_lowermatch(struct dmar_gas_match_args *a, struct dmar_map_entry *prev) -{ - struct dmar_map_entry *l; - int ret; - - if (prev->end < a->common->lowaddr) { - a->entry->start = roundup2(prev->end + DMAR_PAGE_SIZE, - a->common->alignment); - if (dmar_gas_match_one(a, prev, a->common->lowaddr)) { - dmar_gas_match_insert(a, prev); - return (0); - } - } - if (prev->free_down < a->size + a->offset + DMAR_PAGE_SIZE) - return (ENOMEM); - l = RB_LEFT(prev, rb_entry); - if (l != NULL) { - ret = dmar_gas_lowermatch(a, l); - if (ret == 0) - return (0); - } - l = RB_RIGHT(prev, rb_entry); - if (l != NULL) - return (dmar_gas_lowermatch(a, l)); - return (ENOMEM); -} - -static int -dmar_gas_uppermatch(struct dmar_gas_match_args *a) -{ - struct dmar_map_entry *next, *prev, find_entry; - - find_entry.start = a->common->highaddr; - next = RB_NFIND(dmar_gas_entries_tree, &a->domain->rb_root, - &find_entry); - if (next == NULL) - return (ENOMEM); - prev = RB_PREV(dmar_gas_entries_tree, &a->domain->rb_root, next); - KASSERT(prev != NULL, ("no prev %p %jx", a->domain, - (uintmax_t)find_entry.start)); - for (;;) { - a->entry->start = prev->start + DMAR_PAGE_SIZE; - if (a->entry->start < a->common->highaddr) - a->entry->start = a->common->highaddr; - a->entry->start = roundup2(a->entry->start, - a->common->alignment); - if (dmar_gas_match_one(a, prev, a->domain->end)) { - dmar_gas_match_insert(a, prev); - return (0); - } - - /* - * XXXKIB. This falls back to linear iteration over - * the free space in the high region. But high - * regions are almost unused, the code should be - * enough to cover the case, although in the - * non-optimal way. - */ - prev = next; - next = RB_NEXT(dmar_gas_entries_tree, &a->domain->rb_root, - prev); - KASSERT(next != NULL, ("no next %p %jx", a->domain, - (uintmax_t)find_entry.start)); - if (next->end >= a->domain->end) - return (ENOMEM); - } -} - -static int -dmar_gas_find_space(struct dmar_domain *domain, - const struct bus_dma_tag_common *common, dmar_gaddr_t size, - int offset, u_int flags, struct dmar_map_entry *entry) -{ - struct dmar_gas_match_args a; - int error; - - DMAR_DOMAIN_ASSERT_LOCKED(domain); - KASSERT(entry->flags == 0, ("dirty entry %p %p", domain, entry)); - KASSERT((size & DMAR_PAGE_MASK) == 0, ("size %jx", (uintmax_t)size)); - - a.domain = domain; - a.size = size; - a.offset = offset; - a.common = common; - a.gas_flags = flags; - a.entry = entry; - - /* Handle lower region. */ - if (common->lowaddr > 0) { - error = dmar_gas_lowermatch(&a, RB_ROOT(&domain->rb_root)); - if (error == 0) - return (0); - KASSERT(error == ENOMEM, - ("error %d from dmar_gas_lowermatch", error)); - } - /* Handle upper region. */ - if (common->highaddr >= domain->end) - return (ENOMEM); - error = dmar_gas_uppermatch(&a); - KASSERT(error == ENOMEM, - ("error %d from dmar_gas_uppermatch", error)); - return (error); -} - -static int -dmar_gas_alloc_region(struct dmar_domain *domain, struct dmar_map_entry *entry, - u_int flags) -{ - struct dmar_map_entry *next, *prev; - bool found; - - DMAR_DOMAIN_ASSERT_LOCKED(domain); - - if ((entry->start & DMAR_PAGE_MASK) != 0 || - (entry->end & DMAR_PAGE_MASK) != 0) - return (EINVAL); - if (entry->start >= entry->end) - return (EINVAL); - if (entry->end >= domain->end) - return (EINVAL); - - next = RB_NFIND(dmar_gas_entries_tree, &domain->rb_root, entry); - KASSERT(next != NULL, ("next must be non-null %p %jx", domain, - (uintmax_t)entry->start)); - prev = RB_PREV(dmar_gas_entries_tree, &domain->rb_root, next); - /* prev could be NULL */ - - /* - * Adapt to broken BIOSes which specify overlapping RMRR - * entries. - * - * XXXKIB: this does not handle a case when prev or next - * entries are completely covered by the current one, which - * extends both ways. - */ - if (prev != NULL && prev->end > entry->start && - (prev->flags & DMAR_MAP_ENTRY_PLACE) == 0) { - if ((flags & DMAR_GM_RMRR) == 0 || - (prev->flags & DMAR_MAP_ENTRY_RMRR) == 0) - return (EBUSY); - entry->start = prev->end; - } - if (next != NULL && next->start < entry->end && - (next->flags & DMAR_MAP_ENTRY_PLACE) == 0) { - if ((flags & DMAR_GM_RMRR) == 0 || - (next->flags & DMAR_MAP_ENTRY_RMRR) == 0) - return (EBUSY); - entry->end = next->start; - } - if (entry->end == entry->start) - return (0); - - if (prev != NULL && prev->end > entry->start) { - /* This assumes that prev is the placeholder entry. */ - dmar_gas_rb_remove(domain, prev); - prev = NULL; - } - if (next != NULL && next->start < entry->end) { - dmar_gas_rb_remove(domain, next); - next = NULL; - } - - found = dmar_gas_rb_insert(domain, entry); - KASSERT(found, ("found RMRR dup %p start %jx end %jx", - domain, (uintmax_t)entry->start, (uintmax_t)entry->end)); - if ((flags & DMAR_GM_RMRR) != 0) - entry->flags = DMAR_MAP_ENTRY_RMRR; - -#ifdef INVARIANTS - struct dmar_map_entry *ip, *in; - ip = RB_PREV(dmar_gas_entries_tree, &domain->rb_root, entry); - in = RB_NEXT(dmar_gas_entries_tree, &domain->rb_root, entry); - KASSERT(prev == NULL || ip == prev, - ("RMRR %p (%jx %jx) prev %p (%jx %jx) ins prev %p (%jx %jx)", - entry, entry->start, entry->end, prev, - prev == NULL ? 0 : prev->start, prev == NULL ? 0 : prev->end, - ip, ip == NULL ? 0 : ip->start, ip == NULL ? 0 : ip->end)); - KASSERT(next == NULL || in == next, - ("RMRR %p (%jx %jx) next %p (%jx %jx) ins next %p (%jx %jx)", - entry, entry->start, entry->end, next, - next == NULL ? 0 : next->start, next == NULL ? 0 : next->end, - in, in == NULL ? 0 : in->start, in == NULL ? 0 : in->end)); -#endif - - return (0); -} - -void -dmar_gas_free_space(struct dmar_domain *domain, struct dmar_map_entry *entry) -{ - - DMAR_DOMAIN_ASSERT_LOCKED(domain); - KASSERT((entry->flags & (DMAR_MAP_ENTRY_PLACE | DMAR_MAP_ENTRY_RMRR | - DMAR_MAP_ENTRY_MAP)) == DMAR_MAP_ENTRY_MAP, - ("permanent entry %p %p", domain, entry)); - - dmar_gas_rb_remove(domain, entry); - entry->flags &= ~DMAR_MAP_ENTRY_MAP; -#ifdef INVARIANTS - if (dmar_check_free) - dmar_gas_check_free(domain); -#endif -} - -void -dmar_gas_free_region(struct dmar_domain *domain, struct dmar_map_entry *entry) -{ - struct dmar_map_entry *next, *prev; - - DMAR_DOMAIN_ASSERT_LOCKED(domain); - KASSERT((entry->flags & (DMAR_MAP_ENTRY_PLACE | DMAR_MAP_ENTRY_RMRR | - DMAR_MAP_ENTRY_MAP)) == DMAR_MAP_ENTRY_RMRR, - ("non-RMRR entry %p %p", domain, entry)); - - prev = RB_PREV(dmar_gas_entries_tree, &domain->rb_root, entry); - next = RB_NEXT(dmar_gas_entries_tree, &domain->rb_root, entry); - dmar_gas_rb_remove(domain, entry); - entry->flags &= ~DMAR_MAP_ENTRY_RMRR; - - if (prev == NULL) - dmar_gas_rb_insert(domain, domain->first_place); - if (next == NULL) - dmar_gas_rb_insert(domain, domain->last_place); -} - -int -dmar_gas_map(struct dmar_domain *domain, - const struct bus_dma_tag_common *common, dmar_gaddr_t size, int offset, - u_int eflags, u_int flags, vm_page_t *ma, struct dmar_map_entry **res) -{ - struct dmar_map_entry *entry; - int error; - - KASSERT((flags & ~(DMAR_GM_CANWAIT | DMAR_GM_CANSPLIT)) == 0, - ("invalid flags 0x%x", flags)); - - entry = dmar_gas_alloc_entry(domain, (flags & DMAR_GM_CANWAIT) != 0 ? - DMAR_PGF_WAITOK : 0); - if (entry == NULL) - return (ENOMEM); - DMAR_DOMAIN_LOCK(domain); - error = dmar_gas_find_space(domain, common, size, offset, flags, - entry); - if (error == ENOMEM) { - DMAR_DOMAIN_UNLOCK(domain); - dmar_gas_free_entry(domain, entry); - return (error); - } -#ifdef INVARIANTS - if (dmar_check_free) - dmar_gas_check_free(domain); -#endif - KASSERT(error == 0, - ("unexpected error %d from dmar_gas_find_entry", error)); - KASSERT(entry->end < domain->end, ("allocated GPA %jx, max GPA %jx", - (uintmax_t)entry->end, (uintmax_t)domain->end)); - entry->flags |= eflags; - DMAR_DOMAIN_UNLOCK(domain); - - error = domain_map_buf(domain, entry->start, entry->end - entry->start, - ma, - ((eflags & DMAR_MAP_ENTRY_READ) != 0 ? DMAR_PTE_R : 0) | - ((eflags & DMAR_MAP_ENTRY_WRITE) != 0 ? DMAR_PTE_W : 0) | - ((eflags & DMAR_MAP_ENTRY_SNOOP) != 0 ? DMAR_PTE_SNP : 0) | - ((eflags & DMAR_MAP_ENTRY_TM) != 0 ? DMAR_PTE_TM : 0), - (flags & DMAR_GM_CANWAIT) != 0 ? DMAR_PGF_WAITOK : 0); - if (error == ENOMEM) { - dmar_domain_unload_entry(entry, true); - return (error); - } - KASSERT(error == 0, - ("unexpected error %d from domain_map_buf", error)); - - *res = entry; - return (0); -} - -int -dmar_gas_map_region(struct dmar_domain *domain, struct dmar_map_entry *entry, - u_int eflags, u_int flags, vm_page_t *ma) -{ - dmar_gaddr_t start; - int error; - - KASSERT(entry->flags == 0, ("used RMRR entry %p %p %x", domain, - entry, entry->flags)); - KASSERT((flags & ~(DMAR_GM_CANWAIT | DMAR_GM_RMRR)) == 0, - ("invalid flags 0x%x", flags)); - - start = entry->start; - DMAR_DOMAIN_LOCK(domain); - error = dmar_gas_alloc_region(domain, entry, flags); - if (error != 0) { - DMAR_DOMAIN_UNLOCK(domain); - return (error); - } - entry->flags |= eflags; - DMAR_DOMAIN_UNLOCK(domain); - if (entry->end == entry->start) - return (0); - - error = domain_map_buf(domain, entry->start, entry->end - entry->start, - ma + OFF_TO_IDX(start - entry->start), - ((eflags & DMAR_MAP_ENTRY_READ) != 0 ? DMAR_PTE_R : 0) | - ((eflags & DMAR_MAP_ENTRY_WRITE) != 0 ? DMAR_PTE_W : 0) | - ((eflags & DMAR_MAP_ENTRY_SNOOP) != 0 ? DMAR_PTE_SNP : 0) | - ((eflags & DMAR_MAP_ENTRY_TM) != 0 ? DMAR_PTE_TM : 0), - (flags & DMAR_GM_CANWAIT) != 0 ? DMAR_PGF_WAITOK : 0); - if (error == ENOMEM) { - dmar_domain_unload_entry(entry, false); - return (error); - } - KASSERT(error == 0, - ("unexpected error %d from domain_map_buf", error)); - - return (0); -} - -int -dmar_gas_reserve_region(struct dmar_domain *domain, dmar_gaddr_t start, - dmar_gaddr_t end) -{ - struct dmar_map_entry *entry; - int error; - - entry = dmar_gas_alloc_entry(domain, DMAR_PGF_WAITOK); - entry->start = start; - entry->end = end; - DMAR_DOMAIN_LOCK(domain); - error = dmar_gas_alloc_region(domain, entry, DMAR_GM_CANWAIT); - if (error == 0) - entry->flags |= DMAR_MAP_ENTRY_UNMAPPED; - DMAR_DOMAIN_UNLOCK(domain); - if (error != 0) - dmar_gas_free_entry(domain, entry); - return (error); -} diff --git a/sys/xen/interface/acm.h b/sys/xen/interface/acm.h deleted file mode 100644 index ef62da02013..00000000000 --- a/sys/xen/interface/acm.h +++ /dev/null @@ -1,228 +0,0 @@ -/* - * acm.h: Xen access control module interface defintions - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to - * deal in the Software without restriction, including without limitation the - * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - * Reiner Sailer - * Copyright (c) 2005, International Business Machines Corporation. - */ - -#ifndef _XEN_PUBLIC_ACM_H -#define _XEN_PUBLIC_ACM_H - -#include "xen.h" - -/* if ACM_DEBUG defined, all hooks should - * print a short trace message (comment it out - * when not in testing mode ) - */ -/* #define ACM_DEBUG */ - -#ifdef ACM_DEBUG -# define printkd(fmt, args...) printk(fmt,## args) -#else -# define printkd(fmt, args...) -#endif - -/* default ssid reference value if not supplied */ -#define ACM_DEFAULT_SSID 0x0 -#define ACM_DEFAULT_LOCAL_SSID 0x0 - -/* Internal ACM ERROR types */ -#define ACM_OK 0 -#define ACM_UNDEF -1 -#define ACM_INIT_SSID_ERROR -2 -#define ACM_INIT_SOID_ERROR -3 -#define ACM_ERROR -4 - -/* External ACCESS DECISIONS */ -#define ACM_ACCESS_PERMITTED 0 -#define ACM_ACCESS_DENIED -111 -#define ACM_NULL_POINTER_ERROR -200 - -/* - Error codes reported in when trying to test for a new policy - These error codes are reported in an array of tuples where - each error code is followed by a parameter describing the error - more closely, such as a domain id. -*/ -#define ACM_EVTCHN_SHARING_VIOLATION 0x100 -#define ACM_GNTTAB_SHARING_VIOLATION 0x101 -#define ACM_DOMAIN_LOOKUP 0x102 -#define ACM_CHWALL_CONFLICT 0x103 -#define ACM_SSIDREF_IN_USE 0x104 - - -/* primary policy in lower 4 bits */ -#define ACM_NULL_POLICY 0 -#define ACM_CHINESE_WALL_POLICY 1 -#define ACM_SIMPLE_TYPE_ENFORCEMENT_POLICY 2 -#define ACM_POLICY_UNDEFINED 15 - -/* combinations have secondary policy component in higher 4bit */ -#define ACM_CHINESE_WALL_AND_SIMPLE_TYPE_ENFORCEMENT_POLICY \ - ((ACM_SIMPLE_TYPE_ENFORCEMENT_POLICY << 4) | ACM_CHINESE_WALL_POLICY) - -/* policy: */ -#define ACM_POLICY_NAME(X) \ - ((X) == (ACM_NULL_POLICY)) ? "NULL" : \ - ((X) == (ACM_CHINESE_WALL_POLICY)) ? "CHINESE WALL" : \ - ((X) == (ACM_SIMPLE_TYPE_ENFORCEMENT_POLICY)) ? "SIMPLE TYPE ENFORCEMENT" : \ - ((X) == (ACM_CHINESE_WALL_AND_SIMPLE_TYPE_ENFORCEMENT_POLICY)) ? "CHINESE WALL AND SIMPLE TYPE ENFORCEMENT" : \ - "UNDEFINED" - -/* the following policy versions must be increased - * whenever the interpretation of the related - * policy's data structure changes - */ -#define ACM_POLICY_VERSION 3 -#define ACM_CHWALL_VERSION 1 -#define ACM_STE_VERSION 1 - -/* defines a ssid reference used by xen */ -typedef uint32_t ssidref_t; - -/* hooks that are known to domains */ -#define ACMHOOK_none 0 -#define ACMHOOK_sharing 1 - -/* -------security policy relevant type definitions-------- */ - -/* type identifier; compares to "equal" or "not equal" */ -typedef uint16_t domaintype_t; - -/* CHINESE WALL POLICY DATA STRUCTURES - * - * current accumulated conflict type set: - * When a domain is started and has a type that is in - * a conflict set, the conflicting types are incremented in - * the aggregate set. When a domain is destroyed, the - * conflicting types to its type are decremented. - * If a domain has multiple types, this procedure works over - * all those types. - * - * conflict_aggregate_set[i] holds the number of - * running domains that have a conflict with type i. - * - * running_types[i] holds the number of running domains - * that include type i in their ssidref-referenced type set - * - * conflict_sets[i][j] is "0" if type j has no conflict - * with type i and is "1" otherwise. - */ -/* high-16 = version, low-16 = check magic */ -#define ACM_MAGIC 0x0001debc - -/* each offset in bytes from start of the struct they - * are part of */ - -/* V3 of the policy buffer aded a version structure */ -struct acm_policy_version -{ - uint32_t major; - uint32_t minor; -}; - - -/* each buffer consists of all policy information for - * the respective policy given in the policy code - * - * acm_policy_buffer, acm_chwall_policy_buffer, - * and acm_ste_policy_buffer need to stay 32-bit aligned - * because we create binary policies also with external - * tools that assume packed representations (e.g. the java tool) - */ -struct acm_policy_buffer { - uint32_t policy_version; /* ACM_POLICY_VERSION */ - uint32_t magic; - uint32_t len; - uint32_t policy_reference_offset; - uint32_t primary_policy_code; - uint32_t primary_buffer_offset; - uint32_t secondary_policy_code; - uint32_t secondary_buffer_offset; - struct acm_policy_version xml_pol_version; /* add in V3 */ -}; - - -struct acm_policy_reference_buffer { - uint32_t len; -}; - -struct acm_chwall_policy_buffer { - uint32_t policy_version; /* ACM_CHWALL_VERSION */ - uint32_t policy_code; - uint32_t chwall_max_types; - uint32_t chwall_max_ssidrefs; - uint32_t chwall_max_conflictsets; - uint32_t chwall_ssid_offset; - uint32_t chwall_conflict_sets_offset; - uint32_t chwall_running_types_offset; - uint32_t chwall_conflict_aggregate_offset; -}; - -struct acm_ste_policy_buffer { - uint32_t policy_version; /* ACM_STE_VERSION */ - uint32_t policy_code; - uint32_t ste_max_types; - uint32_t ste_max_ssidrefs; - uint32_t ste_ssid_offset; -}; - -struct acm_stats_buffer { - uint32_t magic; - uint32_t len; - uint32_t primary_policy_code; - uint32_t primary_stats_offset; - uint32_t secondary_policy_code; - uint32_t secondary_stats_offset; -}; - -struct acm_ste_stats_buffer { - uint32_t ec_eval_count; - uint32_t gt_eval_count; - uint32_t ec_denied_count; - uint32_t gt_denied_count; - uint32_t ec_cachehit_count; - uint32_t gt_cachehit_count; -}; - -struct acm_ssid_buffer { - uint32_t len; - ssidref_t ssidref; - uint32_t policy_reference_offset; - uint32_t primary_policy_code; - uint32_t primary_max_types; - uint32_t primary_types_offset; - uint32_t secondary_policy_code; - uint32_t secondary_max_types; - uint32_t secondary_types_offset; -}; - -#endif - -/* - * Local variables: - * mode: C - * c-set-style: "BSD" - * c-basic-offset: 4 - * tab-width: 4 - * indent-tabs-mode: nil - * End: - */ diff --git a/sys/xen/interface/acm_ops.h b/sys/xen/interface/acm_ops.h deleted file mode 100644 index 27a88720a79..00000000000 --- a/sys/xen/interface/acm_ops.h +++ /dev/null @@ -1,159 +0,0 @@ -/* - * acm_ops.h: Xen access control module hypervisor commands - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to - * deal in the Software without restriction, including without limitation the - * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - * Reiner Sailer - * Copyright (c) 2005,2006 International Business Machines Corporation. - */ - -#ifndef __XEN_PUBLIC_ACM_OPS_H__ -#define __XEN_PUBLIC_ACM_OPS_H__ - -#include "xen.h" -#include "acm.h" - -/* - * Make sure you increment the interface version whenever you modify this file! - * This makes sure that old versions of acm tools will stop working in a - * well-defined way (rather than crashing the machine, for instance). - */ -#define ACM_INTERFACE_VERSION 0xAAAA000A - -/************************************************************************/ - -/* - * Prototype for this hypercall is: - * int acm_op(int cmd, void *args) - * @cmd == ACMOP_??? (access control module operation). - * @args == Operation-specific extra arguments (NULL if none). - */ - - -#define ACMOP_setpolicy 1 -struct acm_setpolicy { - /* IN */ - XEN_GUEST_HANDLE_64(void) pushcache; - uint32_t pushcache_size; -}; - - -#define ACMOP_getpolicy 2 -struct acm_getpolicy { - /* IN */ - XEN_GUEST_HANDLE_64(void) pullcache; - uint32_t pullcache_size; -}; - - -#define ACMOP_dumpstats 3 -struct acm_dumpstats { - /* IN */ - XEN_GUEST_HANDLE_64(void) pullcache; - uint32_t pullcache_size; -}; - - -#define ACMOP_getssid 4 -#define ACM_GETBY_ssidref 1 -#define ACM_GETBY_domainid 2 -struct acm_getssid { - /* IN */ - uint32_t get_ssid_by; /* ACM_GETBY_* */ - union { - domaintype_t domainid; - ssidref_t ssidref; - } id; - XEN_GUEST_HANDLE_64(void) ssidbuf; - uint32_t ssidbuf_size; -}; - -#define ACMOP_getdecision 5 -struct acm_getdecision { - /* IN */ - uint32_t get_decision_by1; /* ACM_GETBY_* */ - uint32_t get_decision_by2; /* ACM_GETBY_* */ - union { - domaintype_t domainid; - ssidref_t ssidref; - } id1; - union { - domaintype_t domainid; - ssidref_t ssidref; - } id2; - uint32_t hook; - /* OUT */ - uint32_t acm_decision; -}; - - -#define ACMOP_chgpolicy 6 -struct acm_change_policy { - /* IN */ - XEN_GUEST_HANDLE_64(void) policy_pushcache; - uint32_t policy_pushcache_size; - XEN_GUEST_HANDLE_64(void) del_array; - uint32_t delarray_size; - XEN_GUEST_HANDLE_64(void) chg_array; - uint32_t chgarray_size; - /* OUT */ - /* array with error code */ - XEN_GUEST_HANDLE_64(void) err_array; - uint32_t errarray_size; -}; - -#define ACMOP_relabeldoms 7 -struct acm_relabel_doms { - /* IN */ - XEN_GUEST_HANDLE_64(void) relabel_map; - uint32_t relabel_map_size; - /* OUT */ - XEN_GUEST_HANDLE_64(void) err_array; - uint32_t errarray_size; -}; - -/* future interface to Xen */ -struct xen_acmctl { - uint32_t cmd; - uint32_t interface_version; - union { - struct acm_setpolicy setpolicy; - struct acm_getpolicy getpolicy; - struct acm_dumpstats dumpstats; - struct acm_getssid getssid; - struct acm_getdecision getdecision; - struct acm_change_policy change_policy; - struct acm_relabel_doms relabel_doms; - } u; -}; - -typedef struct xen_acmctl xen_acmctl_t; -DEFINE_XEN_GUEST_HANDLE(xen_acmctl_t); - -#endif /* __XEN_PUBLIC_ACM_OPS_H__ */ - -/* - * Local variables: - * mode: C - * c-set-style: "BSD" - * c-basic-offset: 4 - * tab-width: 4 - * indent-tabs-mode: nil - * End: - */ diff --git a/sys/xen/interface/arch-ia64.h b/sys/xen/interface/arch-ia64.h deleted file mode 100644 index c9da5d4f828..00000000000 --- a/sys/xen/interface/arch-ia64.h +++ /dev/null @@ -1,637 +0,0 @@ -/****************************************************************************** - * arch-ia64/hypervisor-if.h - * - * Guest OS interface to IA64 Xen. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to - * deal in the Software without restriction, including without limitation the - * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - */ - -#include "xen.h" - -#ifndef __HYPERVISOR_IF_IA64_H__ -#define __HYPERVISOR_IF_IA64_H__ - -#if !defined(__GNUC__) || defined(__STRICT_ANSI__) -#error "Anonymous structs/unions are a GNU extension." -#endif - -/* Structural guest handles introduced in 0x00030201. */ -#if __XEN_INTERFACE_VERSION__ >= 0x00030201 -#define ___DEFINE_XEN_GUEST_HANDLE(name, type) \ - typedef struct { type *p; } __guest_handle_ ## name -#else -#define ___DEFINE_XEN_GUEST_HANDLE(name, type) \ - typedef type * __guest_handle_ ## name -#endif - -#define __DEFINE_XEN_GUEST_HANDLE(name, type) \ - ___DEFINE_XEN_GUEST_HANDLE(name, type); \ - ___DEFINE_XEN_GUEST_HANDLE(const_##name, const type) - -#define DEFINE_XEN_GUEST_HANDLE(name) __DEFINE_XEN_GUEST_HANDLE(name, name) -#define XEN_GUEST_HANDLE(name) __guest_handle_ ## name -#define XEN_GUEST_HANDLE_64(name) XEN_GUEST_HANDLE(name) -#define uint64_aligned_t uint64_t -#define set_xen_guest_handle_raw(hnd, val) do { (hnd).p = val; } while (0) -#ifdef __XEN_TOOLS__ -#define get_xen_guest_handle(val, hnd) do { val = (hnd).p; } while (0) -#endif -#define set_xen_guest_handle(hnd, val) set_xen_guest_handle_raw(hnd, val) - -#ifndef __ASSEMBLY__ -typedef unsigned long xen_pfn_t; -#define PRI_xen_pfn "lx" -#endif - -/* Arch specific VIRQs definition */ -#define VIRQ_ITC VIRQ_ARCH_0 /* V. Virtual itc timer */ -#define VIRQ_MCA_CMC VIRQ_ARCH_1 /* MCA cmc interrupt */ -#define VIRQ_MCA_CPE VIRQ_ARCH_2 /* MCA cpe interrupt */ - -/* Maximum number of virtual CPUs in multi-processor guests. */ -/* WARNING: before changing this, check that shared_info fits on a page */ -#define XEN_LEGACY_MAX_VCPUS 64 - -/* IO ports location for PV. */ -#define IO_PORTS_PADDR 0x00000ffffc000000UL -#define IO_PORTS_SIZE 0x0000000004000000UL - -#ifndef __ASSEMBLY__ - -typedef unsigned long xen_ulong_t; - -#ifdef __XEN_TOOLS__ -#define XEN_PAGE_SIZE XC_PAGE_SIZE -#else -#define XEN_PAGE_SIZE PAGE_SIZE -#endif - -#define INVALID_MFN (~0UL) - -struct pt_fpreg { - union { - unsigned long bits[2]; - long double __dummy; /* force 16-byte alignment */ - } u; -}; - -union vac { - unsigned long value; - struct { - int a_int:1; - int a_from_int_cr:1; - int a_to_int_cr:1; - int a_from_psr:1; - int a_from_cpuid:1; - int a_cover:1; - int a_bsw:1; - long reserved:57; - }; -}; -typedef union vac vac_t; - -union vdc { - unsigned long value; - struct { - int d_vmsw:1; - int d_extint:1; - int d_ibr_dbr:1; - int d_pmc:1; - int d_to_pmd:1; - int d_itm:1; - long reserved:58; - }; -}; -typedef union vdc vdc_t; - -struct mapped_regs { - union vac vac; - union vdc vdc; - unsigned long virt_env_vaddr; - unsigned long reserved1[29]; - unsigned long vhpi; - unsigned long reserved2[95]; - union { - unsigned long vgr[16]; - unsigned long bank1_regs[16]; // bank1 regs (r16-r31) when bank0 active - }; - union { - unsigned long vbgr[16]; - unsigned long bank0_regs[16]; // bank0 regs (r16-r31) when bank1 active - }; - unsigned long vnat; - unsigned long vbnat; - unsigned long vcpuid[5]; - unsigned long reserved3[11]; - unsigned long vpsr; - unsigned long vpr; - unsigned long reserved4[76]; - union { - unsigned long vcr[128]; - struct { - unsigned long dcr; // CR0 - unsigned long itm; - unsigned long iva; - unsigned long rsv1[5]; - unsigned long pta; // CR8 - unsigned long rsv2[7]; - unsigned long ipsr; // CR16 - unsigned long isr; - unsigned long rsv3; - unsigned long iip; - unsigned long ifa; - unsigned long itir; - unsigned long iipa; - unsigned long ifs; - unsigned long iim; // CR24 - unsigned long iha; - unsigned long rsv4[38]; - unsigned long lid; // CR64 - unsigned long ivr; - unsigned long tpr; - unsigned long eoi; - unsigned long irr[4]; - unsigned long itv; // CR72 - unsigned long pmv; - unsigned long cmcv; - unsigned long rsv5[5]; - unsigned long lrr0; // CR80 - unsigned long lrr1; - unsigned long rsv6[46]; - }; - }; - union { - unsigned long reserved5[128]; - struct { - unsigned long precover_ifs; - unsigned long unat; // not sure if this is needed until NaT arch is done - int interrupt_collection_enabled; // virtual psr.ic - /* virtual interrupt deliverable flag is evtchn_upcall_mask in - * shared info area now. interrupt_mask_addr is the address - * of evtchn_upcall_mask for current vcpu - */ - unsigned char *interrupt_mask_addr; - int pending_interruption; - unsigned char vpsr_pp; - unsigned char vpsr_dfh; - unsigned char hpsr_dfh; - unsigned char hpsr_mfh; - unsigned long reserved5_1[4]; - int metaphysical_mode; // 1 = use metaphys mapping, 0 = use virtual - int banknum; // 0 or 1, which virtual register bank is active - unsigned long rrs[8]; // region registers - unsigned long krs[8]; // kernel registers - unsigned long tmp[16]; // temp registers (e.g. for hyperprivops) - - /* itc paravirtualization - * vAR.ITC = mAR.ITC + itc_offset - * itc_last is one which was lastly passed to - * the guest OS in order to prevent it from - * going backwords. - */ - unsigned long itc_offset; - unsigned long itc_last; - }; - }; -}; -typedef struct mapped_regs mapped_regs_t; - -struct vpd { - struct mapped_regs vpd_low; - unsigned long reserved6[3456]; - unsigned long vmm_avail[128]; - unsigned long reserved7[4096]; -}; -typedef struct vpd vpd_t; - -struct arch_vcpu_info { -}; -typedef struct arch_vcpu_info arch_vcpu_info_t; - -/* - * This structure is used for magic page in domain pseudo physical address - * space and the result of XENMEM_machine_memory_map. - * As the XENMEM_machine_memory_map result, - * xen_memory_map::nr_entries indicates the size in bytes - * including struct xen_ia64_memmap_info. Not the number of entries. - */ -struct xen_ia64_memmap_info { - uint64_t efi_memmap_size; /* size of EFI memory map */ - uint64_t efi_memdesc_size; /* size of an EFI memory map descriptor */ - uint32_t efi_memdesc_version; /* memory descriptor version */ - void *memdesc[0]; /* array of efi_memory_desc_t */ -}; -typedef struct xen_ia64_memmap_info xen_ia64_memmap_info_t; - -struct arch_shared_info { - /* PFN of the start_info page. */ - unsigned long start_info_pfn; - - /* Interrupt vector for event channel. */ - int evtchn_vector; - - /* PFN of memmap_info page */ - unsigned int memmap_info_num_pages;/* currently only = 1 case is - supported. */ - unsigned long memmap_info_pfn; - - uint64_t pad[31]; -}; -typedef struct arch_shared_info arch_shared_info_t; - -typedef unsigned long xen_callback_t; - -struct ia64_tr_entry { - unsigned long pte; - unsigned long itir; - unsigned long vadr; - unsigned long rid; -}; -typedef struct ia64_tr_entry ia64_tr_entry_t; -DEFINE_XEN_GUEST_HANDLE(ia64_tr_entry_t); - -struct vcpu_tr_regs { - struct ia64_tr_entry itrs[12]; - struct ia64_tr_entry dtrs[12]; -}; - -union vcpu_ar_regs { - unsigned long ar[128]; - struct { - unsigned long kr[8]; - unsigned long rsv1[8]; - unsigned long rsc; - unsigned long bsp; - unsigned long bspstore; - unsigned long rnat; - unsigned long rsv2; - unsigned long fcr; - unsigned long rsv3[2]; - unsigned long eflag; - unsigned long csd; - unsigned long ssd; - unsigned long cflg; - unsigned long fsr; - unsigned long fir; - unsigned long fdr; - unsigned long rsv4; - unsigned long ccv; /* 32 */ - unsigned long rsv5[3]; - unsigned long unat; - unsigned long rsv6[3]; - unsigned long fpsr; - unsigned long rsv7[3]; - unsigned long itc; - unsigned long rsv8[3]; - unsigned long ign1[16]; - unsigned long pfs; /* 64 */ - unsigned long lc; - unsigned long ec; - unsigned long rsv9[45]; - unsigned long ign2[16]; - }; -}; - -union vcpu_cr_regs { - unsigned long cr[128]; - struct { - unsigned long dcr; // CR0 - unsigned long itm; - unsigned long iva; - unsigned long rsv1[5]; - unsigned long pta; // CR8 - unsigned long rsv2[7]; - unsigned long ipsr; // CR16 - unsigned long isr; - unsigned long rsv3; - unsigned long iip; - unsigned long ifa; - unsigned long itir; - unsigned long iipa; - unsigned long ifs; - unsigned long iim; // CR24 - unsigned long iha; - unsigned long rsv4[38]; - unsigned long lid; // CR64 - unsigned long ivr; - unsigned long tpr; - unsigned long eoi; - unsigned long irr[4]; - unsigned long itv; // CR72 - unsigned long pmv; - unsigned long cmcv; - unsigned long rsv5[5]; - unsigned long lrr0; // CR80 - unsigned long lrr1; - unsigned long rsv6[46]; - }; -}; - -struct vcpu_guest_context_regs { - unsigned long r[32]; - unsigned long b[8]; - unsigned long bank[16]; - unsigned long ip; - unsigned long psr; - unsigned long cfm; - unsigned long pr; - unsigned int nats; /* NaT bits for r1-r31. */ - unsigned int bnats; /* Nat bits for banked registers. */ - union vcpu_ar_regs ar; - union vcpu_cr_regs cr; - struct pt_fpreg f[128]; - unsigned long dbr[8]; - unsigned long ibr[8]; - unsigned long rr[8]; - unsigned long pkr[16]; - - /* FIXME: cpuid,pmd,pmc */ - - unsigned long xip; - unsigned long xpsr; - unsigned long xfs; - unsigned long xr[4]; - - struct vcpu_tr_regs tr; - - /* Physical registers in case of debug event. */ - unsigned long excp_iipa; - unsigned long excp_ifa; - unsigned long excp_isr; - unsigned int excp_vector; - - /* - * The rbs is intended to be the image of the stacked registers still - * in the cpu (not yet stored in memory). It is laid out as if it - * were written in memory at a 512 (64*8) aligned address + offset. - * rbs_voff is (offset / 8). rbs_nat contains NaT bits for the - * remaining rbs registers. rbs_rnat contains NaT bits for in memory - * rbs registers. - * Note: loadrs is 2**14 bytes == 2**11 slots. - */ - unsigned int rbs_voff; - unsigned long rbs[2048]; - unsigned long rbs_rnat; - - /* - * RSE.N_STACKED_PHYS via PAL_RSE_INFO - * Strictly this isn't cpu context, but this value is necessary - * for domain save/restore. So is here. - */ - unsigned long num_phys_stacked; -}; - -struct vcpu_guest_context { -#define VGCF_EXTRA_REGS (1UL << 1) /* Set extra regs. */ -#define VGCF_SET_CR_IRR (1UL << 2) /* Set cr_irr[0:3]. */ -#define VGCF_online (1UL << 3) /* make this vcpu online */ -#define VGCF_SET_AR_ITC (1UL << 4) /* set pv ar.itc. itc_offset, itc_last */ - unsigned long flags; /* VGCF_* flags */ - - struct vcpu_guest_context_regs regs; - - unsigned long event_callback_ip; - - /* xen doesn't share privregs pages with hvm domain so that this member - * doesn't make sense for hvm domain. - * ~0UL is already used for INVALID_P2M_ENTRY. */ -#define VGC_PRIVREGS_HVM (~(-2UL)) - unsigned long privregs_pfn; -}; -typedef struct vcpu_guest_context vcpu_guest_context_t; -DEFINE_XEN_GUEST_HANDLE(vcpu_guest_context_t); - -/* dom0 vp op */ -#define __HYPERVISOR_ia64_dom0vp_op __HYPERVISOR_arch_0 -/* Map io space in machine address to dom0 physical address space. - Currently physical assigned address equals to machine address. */ -#define IA64_DOM0VP_ioremap 0 - -/* Convert a pseudo physical page frame number to the corresponding - machine page frame number. If no page is assigned, INVALID_MFN or - GPFN_INV_MASK is returned depending on domain's non-vti/vti mode. */ -#define IA64_DOM0VP_phystomach 1 - -/* Convert a machine page frame number to the corresponding pseudo physical - page frame number of the caller domain. */ -#define IA64_DOM0VP_machtophys 3 - -/* Reserved for future use. */ -#define IA64_DOM0VP_iounmap 4 - -/* Unmap and free pages contained in the specified pseudo physical region. */ -#define IA64_DOM0VP_zap_physmap 5 - -/* Assign machine page frame to dom0's pseudo physical address space. */ -#define IA64_DOM0VP_add_physmap 6 - -/* expose the p2m table into domain */ -#define IA64_DOM0VP_expose_p2m 7 - -/* xen perfmon */ -#define IA64_DOM0VP_perfmon 8 - -/* gmfn version of IA64_DOM0VP_add_physmap */ -#define IA64_DOM0VP_add_physmap_with_gmfn 9 - -/* get fpswa revision */ -#define IA64_DOM0VP_fpswa_revision 10 - -/* Add an I/O port space range */ -#define IA64_DOM0VP_add_io_space 11 - -/* expose the foreign domain's p2m table into privileged domain */ -#define IA64_DOM0VP_expose_foreign_p2m 12 -#define IA64_DOM0VP_EFP_ALLOC_PTE 0x1 /* allocate p2m table */ - -/* unexpose the foreign domain's p2m table into privileged domain */ -#define IA64_DOM0VP_unexpose_foreign_p2m 13 - -/* get memmap_info and memmap. It is possible to map the page directly - by foreign page mapping, but there is a race between writer. - This hypercall avoids such race. */ -#define IA64_DOM0VP_get_memmap 14 - -// flags for page assignement to pseudo physical address space -#define _ASSIGN_readonly 0 -#define ASSIGN_readonly (1UL << _ASSIGN_readonly) -#define ASSIGN_writable (0UL << _ASSIGN_readonly) // dummy flag -/* Internal only: memory attribute must be WC/UC/UCE. */ -#define _ASSIGN_nocache 1 -#define ASSIGN_nocache (1UL << _ASSIGN_nocache) -// tlb tracking -#define _ASSIGN_tlb_track 2 -#define ASSIGN_tlb_track (1UL << _ASSIGN_tlb_track) -/* Internal only: associated with PGC_allocated bit */ -#define _ASSIGN_pgc_allocated 3 -#define ASSIGN_pgc_allocated (1UL << _ASSIGN_pgc_allocated) -/* Page is an IO page. */ -#define _ASSIGN_io 4 -#define ASSIGN_io (1UL << _ASSIGN_io) - -/* This structure has the same layout of struct ia64_boot_param, defined in - . It is redefined here to ease use. */ -struct xen_ia64_boot_param { - unsigned long command_line; /* physical address of cmd line args */ - unsigned long efi_systab; /* physical address of EFI system table */ - unsigned long efi_memmap; /* physical address of EFI memory map */ - unsigned long efi_memmap_size; /* size of EFI memory map */ - unsigned long efi_memdesc_size; /* size of an EFI memory map descriptor */ - unsigned int efi_memdesc_version; /* memory descriptor version */ - struct { - unsigned short num_cols; /* number of columns on console. */ - unsigned short num_rows; /* number of rows on console. */ - unsigned short orig_x; /* cursor's x position */ - unsigned short orig_y; /* cursor's y position */ - } console_info; - unsigned long fpswa; /* physical address of the fpswa interface */ - unsigned long initrd_start; - unsigned long initrd_size; - unsigned long domain_start; /* va where the boot time domain begins */ - unsigned long domain_size; /* how big is the boot domain */ -}; - -#endif /* !__ASSEMBLY__ */ - -/* Size of the shared_info area (this is not related to page size). */ -#define XSI_SHIFT 14 -#define XSI_SIZE (1 << XSI_SHIFT) -/* Log size of mapped_regs area (64 KB - only 4KB is used). */ -#define XMAPPEDREGS_SHIFT 12 -#define XMAPPEDREGS_SIZE (1 << XMAPPEDREGS_SHIFT) -/* Offset of XASI (Xen arch shared info) wrt XSI_BASE. */ -#define XMAPPEDREGS_OFS XSI_SIZE - -/* Hyperprivops. */ -#define HYPERPRIVOP_START 0x1 -#define HYPERPRIVOP_RFI (HYPERPRIVOP_START + 0x0) -#define HYPERPRIVOP_RSM_DT (HYPERPRIVOP_START + 0x1) -#define HYPERPRIVOP_SSM_DT (HYPERPRIVOP_START + 0x2) -#define HYPERPRIVOP_COVER (HYPERPRIVOP_START + 0x3) -#define HYPERPRIVOP_ITC_D (HYPERPRIVOP_START + 0x4) -#define HYPERPRIVOP_ITC_I (HYPERPRIVOP_START + 0x5) -#define HYPERPRIVOP_SSM_I (HYPERPRIVOP_START + 0x6) -#define HYPERPRIVOP_GET_IVR (HYPERPRIVOP_START + 0x7) -#define HYPERPRIVOP_GET_TPR (HYPERPRIVOP_START + 0x8) -#define HYPERPRIVOP_SET_TPR (HYPERPRIVOP_START + 0x9) -#define HYPERPRIVOP_EOI (HYPERPRIVOP_START + 0xa) -#define HYPERPRIVOP_SET_ITM (HYPERPRIVOP_START + 0xb) -#define HYPERPRIVOP_THASH (HYPERPRIVOP_START + 0xc) -#define HYPERPRIVOP_PTC_GA (HYPERPRIVOP_START + 0xd) -#define HYPERPRIVOP_ITR_D (HYPERPRIVOP_START + 0xe) -#define HYPERPRIVOP_GET_RR (HYPERPRIVOP_START + 0xf) -#define HYPERPRIVOP_SET_RR (HYPERPRIVOP_START + 0x10) -#define HYPERPRIVOP_SET_KR (HYPERPRIVOP_START + 0x11) -#define HYPERPRIVOP_FC (HYPERPRIVOP_START + 0x12) -#define HYPERPRIVOP_GET_CPUID (HYPERPRIVOP_START + 0x13) -#define HYPERPRIVOP_GET_PMD (HYPERPRIVOP_START + 0x14) -#define HYPERPRIVOP_GET_EFLAG (HYPERPRIVOP_START + 0x15) -#define HYPERPRIVOP_SET_EFLAG (HYPERPRIVOP_START + 0x16) -#define HYPERPRIVOP_RSM_BE (HYPERPRIVOP_START + 0x17) -#define HYPERPRIVOP_GET_PSR (HYPERPRIVOP_START + 0x18) -#define HYPERPRIVOP_SET_RR0_TO_RR4 (HYPERPRIVOP_START + 0x19) -#define HYPERPRIVOP_MAX (0x1a) - -/* Fast and light hypercalls. */ -#define __HYPERVISOR_ia64_fast_eoi __HYPERVISOR_arch_1 - -/* Extra debug features. */ -#define __HYPERVISOR_ia64_debug_op __HYPERVISOR_arch_2 - -/* Xencomm macros. */ -#define XENCOMM_INLINE_MASK 0xf800000000000000UL -#define XENCOMM_INLINE_FLAG 0x8000000000000000UL - -#ifndef __ASSEMBLY__ - -/* - * Optimization features. - * The hypervisor may do some special optimizations for guests. This hypercall - * can be used to switch on/of these special optimizations. - */ -#define __HYPERVISOR_opt_feature 0x700UL - -#define XEN_IA64_OPTF_OFF 0x0 -#define XEN_IA64_OPTF_ON 0x1 - -/* - * If this feature is switched on, the hypervisor inserts the - * tlb entries without calling the guests traphandler. - * This is useful in guests using region 7 for identity mapping - * like the linux kernel does. - */ -#define XEN_IA64_OPTF_IDENT_MAP_REG7 1 - -/* Identity mapping of region 4 addresses in HVM. */ -#define XEN_IA64_OPTF_IDENT_MAP_REG4 2 - -/* Identity mapping of region 5 addresses in HVM. */ -#define XEN_IA64_OPTF_IDENT_MAP_REG5 3 - -#define XEN_IA64_OPTF_IDENT_MAP_NOT_SET (0) - -struct xen_ia64_opt_feature { - unsigned long cmd; /* Which feature */ - unsigned char on; /* Switch feature on/off */ - union { - struct { - /* The page protection bit mask of the pte. - * This will be or'ed with the pte. */ - unsigned long pgprot; - unsigned long key; /* A protection key for itir. */ - }; - }; -}; - -#endif /* __ASSEMBLY__ */ - -/* xen perfmon */ -#ifdef XEN -#ifndef __ASSEMBLY__ -#ifndef _ASM_IA64_PERFMON_H - -#include // asm/perfmon.h requires struct list_head -#include -// for PFM_xxx and pfarg_features_t, pfarg_context_t, pfarg_reg_t, pfarg_load_t - -#endif /* _ASM_IA64_PERFMON_H */ - -DEFINE_XEN_GUEST_HANDLE(pfarg_features_t); -DEFINE_XEN_GUEST_HANDLE(pfarg_context_t); -DEFINE_XEN_GUEST_HANDLE(pfarg_reg_t); -DEFINE_XEN_GUEST_HANDLE(pfarg_load_t); -#endif /* __ASSEMBLY__ */ -#endif /* XEN */ - -#ifndef __ASSEMBLY__ -#include "arch-ia64/hvm/memmap.h" -#endif - -#endif /* __HYPERVISOR_IF_IA64_H__ */ - -/* - * Local variables: - * mode: C - * c-set-style: "BSD" - * c-basic-offset: 4 - * tab-width: 4 - * indent-tabs-mode: nil - * End: - */ diff --git a/sys/xen/interface/arch-ia64/debug_op.h b/sys/xen/interface/arch-ia64/debug_op.h deleted file mode 100644 index 8f473582130..00000000000 --- a/sys/xen/interface/arch-ia64/debug_op.h +++ /dev/null @@ -1,99 +0,0 @@ -/****************************************************************************** - * debug_op.h - * - * Copyright (c) 2007 Tristan Gingold - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to - * deal in the Software without restriction, including without limitation the - * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef __XEN_PUBLIC_IA64_DEBUG_OP_H__ -#define __XEN_PUBLIC_IA64_DEBUG_OP_H__ - -/* Set/Get extra conditions to break. */ -#define XEN_IA64_DEBUG_OP_SET_FLAGS 1 -#define XEN_IA64_DEBUG_OP_GET_FLAGS 2 - -/* Break on kernel single step. */ -#define XEN_IA64_DEBUG_ON_KERN_SSTEP (1 << 0) - -/* Break on kernel debug (breakpoint or watch point). */ -#define XEN_IA64_DEBUG_ON_KERN_DEBUG (1 << 1) - -/* Break on kernel taken branch. */ -#define XEN_IA64_DEBUG_ON_KERN_TBRANCH (1 << 2) - -/* Break on interrupt injection. */ -#define XEN_IA64_DEBUG_ON_EXTINT (1 << 3) - -/* Break on interrupt injection. */ -#define XEN_IA64_DEBUG_ON_EXCEPT (1 << 4) - -/* Break on event injection. */ -#define XEN_IA64_DEBUG_ON_EVENT (1 << 5) - -/* Break on privop/virtualized instruction (slow path only). */ -#define XEN_IA64_DEBUG_ON_PRIVOP (1 << 6) - -/* Break on emulated PAL call (at entry). */ -#define XEN_IA64_DEBUG_ON_PAL (1 << 7) - -/* Break on emulated SAL call (at entry). */ -#define XEN_IA64_DEBUG_ON_SAL (1 << 8) - -/* Break on emulated EFI call (at entry). */ -#define XEN_IA64_DEBUG_ON_EFI (1 << 9) - -/* Break on rfi emulation (slow path only, before exec). */ -#define XEN_IA64_DEBUG_ON_RFI (1 << 10) - -/* Break on address translation switch. */ -#define XEN_IA64_DEBUG_ON_MMU (1 << 11) - -/* Break on bad guest physical address. */ -#define XEN_IA64_DEBUG_ON_BAD_MPA (1 << 12) - -/* Force psr.ss bit. */ -#define XEN_IA64_DEBUG_FORCE_SS (1 << 13) - -/* Force psr.db bit. */ -#define XEN_IA64_DEBUG_FORCE_DB (1 << 14) - -/* Break on ITR/PTR. */ -#define XEN_IA64_DEBUG_ON_TR (1 << 15) - -/* Break on ITC/PTC.L/PTC.G/PTC.GA. */ -#define XEN_IA64_DEBUG_ON_TC (1 << 16) - -/* Get translation cache. */ -#define XEN_IA64_DEBUG_OP_GET_TC 3 - -/* Translate virtual address to guest physical address. */ -#define XEN_IA64_DEBUG_OP_TRANSLATE 4 - -union xen_ia64_debug_op { - uint64_t flags; - struct xen_ia64_debug_vtlb { - uint64_t nbr; /* IN/OUT */ - XEN_GUEST_HANDLE_64(ia64_tr_entry_t) tr; /* IN/OUT */ - } vtlb; -}; -typedef union xen_ia64_debug_op xen_ia64_debug_op_t; -DEFINE_XEN_GUEST_HANDLE(xen_ia64_debug_op_t); - -#endif /* __XEN_PUBLIC_IA64_DEBUG_OP_H__ */ diff --git a/sys/xen/interface/arch-ia64/hvm/memmap.h b/sys/xen/interface/arch-ia64/hvm/memmap.h deleted file mode 100644 index 68d14f335cc..00000000000 --- a/sys/xen/interface/arch-ia64/hvm/memmap.h +++ /dev/null @@ -1,91 +0,0 @@ -/****************************************************************************** - * memmap.h - * - * Copyright (c) 2008 Tristan Gingold - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to - * deal in the Software without restriction, including without limitation the - * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef __XEN_PUBLIC_HVM_MEMMAP_IA64_H__ -#define __XEN_PUBLIC_HVM_MEMMAP_IA64_H__ - -#define MEM_G (1UL << 30) -#define MEM_M (1UL << 20) -#define MEM_K (1UL << 10) - -/* Guest physical address of IO ports space. */ -#define MMIO_START (3 * MEM_G) -#define MMIO_SIZE (512 * MEM_M) - -#define VGA_IO_START 0xA0000UL -#define VGA_IO_SIZE 0x20000 - -#define LEGACY_IO_START (MMIO_START + MMIO_SIZE) -#define LEGACY_IO_SIZE (64 * MEM_M) - -#define IO_PAGE_START (LEGACY_IO_START + LEGACY_IO_SIZE) -#define IO_PAGE_SIZE XEN_PAGE_SIZE - -#define STORE_PAGE_START (IO_PAGE_START + IO_PAGE_SIZE) -#define STORE_PAGE_SIZE XEN_PAGE_SIZE - -#define BUFFER_IO_PAGE_START (STORE_PAGE_START + STORE_PAGE_SIZE) -#define BUFFER_IO_PAGE_SIZE XEN_PAGE_SIZE - -#define BUFFER_PIO_PAGE_START (BUFFER_IO_PAGE_START + BUFFER_IO_PAGE_SIZE) -#define BUFFER_PIO_PAGE_SIZE XEN_PAGE_SIZE - -#define IO_SAPIC_START 0xfec00000UL -#define IO_SAPIC_SIZE 0x100000 - -#define PIB_START 0xfee00000UL -#define PIB_SIZE 0x200000 - -#define GFW_START (4 * MEM_G - 16 * MEM_M) -#define GFW_SIZE (16 * MEM_M) - -/* domVTI */ -#define GPFN_FRAME_BUFFER 0x1 /* VGA framebuffer */ -#define GPFN_LOW_MMIO 0x2 /* Low MMIO range */ -#define GPFN_PIB 0x3 /* PIB base */ -#define GPFN_IOSAPIC 0x4 /* IOSAPIC base */ -#define GPFN_LEGACY_IO 0x5 /* Legacy I/O base */ -#define GPFN_HIGH_MMIO 0x6 /* High MMIO range */ - -/* Nvram belongs to GFW memory space */ -#define NVRAM_SIZE (MEM_K * 64) -#define NVRAM_START (GFW_START + 10 * MEM_M) - -#define NVRAM_VALID_SIG 0x4650494e45584948 /* "HIXENIPF" */ -struct nvram_save_addr { - unsigned long addr; - unsigned long signature; -}; - -#endif /* __XEN_PUBLIC_HVM_MEMMAP_IA64_H__ */ - -/* - * Local variables: - * mode: C - * c-set-style: "BSD" - * c-basic-offset: 4 - * tab-width: 4 - * indent-tabs-mode: nil - * End: - */ diff --git a/sys/xen/interface/arch-ia64/hvm/save.h b/sys/xen/interface/arch-ia64/hvm/save.h deleted file mode 100644 index c44e913b235..00000000000 --- a/sys/xen/interface/arch-ia64/hvm/save.h +++ /dev/null @@ -1,208 +0,0 @@ -/****************************************************************************** - * save_types.h - * - * Copyright (c) 2007 Isaku Yamahata - * VA Linux Systems Japan K.K. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to - * deal in the Software without restriction, including without limitation the - * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef __XEN_PUBLIC_HVM_SAVE_IA64_H__ -#define __XEN_PUBLIC_HVM_SAVE_IA64_H__ - -#include "../../hvm/save.h" -#include "../../arch-ia64.h" - -/* - * Save/restore header: general info about the save file. - */ - -/* x86 uses 0x54381286 */ -#define HVM_FILE_MAGIC 0x343641492f6e6558UL /* "Xen/IA64" */ -#define HVM_FILE_VERSION 0x0000000000000001UL - -struct hvm_save_header { - uint64_t magic; /* Must be HVM_FILE_MAGIC */ - uint64_t version; /* File format version */ - uint64_t changeset; /* Version of Xen that saved this file */ - uint64_t cpuid[5]; /* CPUID[0x01][%eax] on the saving machine */ -}; - -DECLARE_HVM_SAVE_TYPE(HEADER, 1, struct hvm_save_header); - -/* - * CPU - */ -struct hvm_hw_ia64_cpu { - uint64_t ipsr; -}; -DECLARE_HVM_SAVE_TYPE(CPU, 2, struct hvm_hw_ia64_cpu); - -/* - * CPU - */ -struct hvm_hw_ia64_vpd { - struct vpd vpd; -}; -DECLARE_HVM_SAVE_TYPE(VPD, 3, struct hvm_hw_ia64_vpd); - -/* - * device dependency - * vacpi => viosapic => vlsapic - */ -/* - * vlsapic - */ -struct hvm_hw_ia64_vlsapic { - uint64_t insvc[4]; - uint64_t vhpi; // ??? should this be saved in vpd - uint8_t xtp; - uint8_t pal_init_pending; - uint8_t pad[2]; -}; -DECLARE_HVM_SAVE_TYPE(VLSAPIC, 4, struct hvm_hw_ia64_vlsapic); -/* set - * unconditionaly set v->arch.irq_new_peding = 1 - * unconditionaly set v->arch.irq_new_condition = 0 - */ - -/* - * vtime - */ -/* itc, itm, itv are saved by arch vcpu context */ -struct hvm_hw_ia64_vtime { - uint64_t itc; - uint64_t itm; - - uint64_t last_itc; - uint64_t pending; -}; -DECLARE_HVM_SAVE_TYPE(VTIME, 5, struct hvm_hw_ia64_vtime); -/* - * calculate v->vtm.vtm_offset - * ??? Or should vtm_offset be set by leave_hypervisor_tail()? - * start vtm_timer if necessary by vtm_set_itm(). - * ??? Or should vtm_timer be set by leave_hypervisor_tail()? - * - * ??? or should be done by schedule_tail() - * => schedule_tail() should do. - */ - -/* - * viosapic - */ -#define VIOSAPIC_NUM_PINS 48 - -/* To share VT-d code which uses vioapic_redir_entry. - * Although on ia64 this is for vsapic, but we have to vioapic_redir_entry - * instead of viosapic_redir_entry. - */ -union vioapic_redir_entry -{ - uint64_t bits; - struct { - uint8_t vector; - - uint8_t delivery_mode : 3; - uint8_t reserve1 : 1; - uint8_t delivery_status: 1; - uint8_t polarity : 1; - uint8_t reserve2 : 1; - uint8_t trig_mode : 1; - - uint8_t mask : 1; - uint8_t reserve3 : 7; - - uint8_t reserved[3]; - uint16_t dest_id; - } fields; -}; - -struct hvm_hw_ia64_viosapic { - uint64_t irr; - uint64_t isr; - uint32_t ioregsel; - uint32_t pad; - uint64_t lowest_vcpu_id; - uint64_t base_address; - union vioapic_redir_entry redirtbl[VIOSAPIC_NUM_PINS]; -}; -DECLARE_HVM_SAVE_TYPE(VIOSAPIC, 6, struct hvm_hw_ia64_viosapic); - -/* - * vacpi - * PM timer - */ -struct vacpi_regs { - union { - struct { - uint32_t pm1a_sts:16;/* PM1a_EVT_BLK.PM1a_STS: status register */ - uint32_t pm1a_en:16; /* PM1a_EVT_BLK.PM1a_EN: enable register */ - }; - uint32_t evt_blk; - }; - uint32_t tmr_val; /* PM_TMR_BLK.TMR_VAL: 32bit free-running counter */ -}; - -struct hvm_hw_ia64_vacpi { - struct vacpi_regs regs; -}; -DECLARE_HVM_SAVE_TYPE(VACPI, 7, struct hvm_hw_ia64_vacpi); -/* update last_gtime and setup timer of struct vacpi */ - -/* - * opt_feature: identity mapping of region 4, 5 and 7. - * With the c/s 16396:d2935f9c217f of xen-ia64-devel.hg, - * opt_feature hypercall supports only region 4,5,7 identity mappings. - * structure hvm_hw_ia64_identity_mappings only supports them. - * The new structure, struct hvm_hw_ia64_identity_mappings, is created to - * avoid to keep up with change of the xen/ia64 internal structure, struct - * opt_feature. - * - * If it is enhanced in the future, new structure will be created. - */ -struct hvm_hw_ia64_identity_mapping { - uint64_t on; /* on/off */ - uint64_t pgprot; /* The page protection bit mask of the pte. */ - uint64_t key; /* A protection key. */ -}; - -struct hvm_hw_ia64_identity_mappings { - struct hvm_hw_ia64_identity_mapping im_reg4;/* Region 4 identity mapping */ - struct hvm_hw_ia64_identity_mapping im_reg5;/* Region 5 identity mapping */ - struct hvm_hw_ia64_identity_mapping im_reg7;/* Region 7 identity mapping */ -}; -DECLARE_HVM_SAVE_TYPE(OPT_FEATURE_IDENTITY_MAPPINGS, 8, struct hvm_hw_ia64_identity_mappings); - -/* - * Largest type-code in use - */ -#define HVM_SAVE_CODE_MAX 8 - -#endif /* __XEN_PUBLIC_HVM_SAVE_IA64_H__ */ - -/* - * Local variables: - * mode: C - * c-set-style: "BSD" - * c-basic-offset: 4 - * tab-width: 4 - * indent-tabs-mode: nil - * End: - */ diff --git a/sys/xen/interface/arch-ia64/sioemu.h b/sys/xen/interface/arch-ia64/sioemu.h deleted file mode 100644 index d48da1a20fe..00000000000 --- a/sys/xen/interface/arch-ia64/sioemu.h +++ /dev/null @@ -1,92 +0,0 @@ -/****************************************************************************** - * sioemu.h - * - * Copyright (c) 2008 Tristan Gingold - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to - * deal in the Software without restriction, including without limitation the - * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef __XEN_PUBLIC_IA64_SIOEMU_H__ -#define __XEN_PUBLIC_IA64_SIOEMU_H__ - -/* SIOEMU specific hypercalls. - The numbers are the minor part of FW_HYPERCALL_SIOEMU. */ - -/* Defines the callback entry point. r8=ip, r9=data. - Must be called per-vcpu. */ -#define SIOEMU_HYPERCALL_SET_CALLBACK 0x01 - -/* Finish sioemu fw initialization and start firmware. r8=ip. */ -#define SIOEMU_HYPERCALL_START_FW 0x02 - -/* Add IO pages in physmap. */ -#define SIOEMU_HYPERCALL_ADD_IO_PHYSMAP 0x03 - -/* Get wallclock time. */ -#define SIOEMU_HYPERCALL_GET_TIME 0x04 - -/* Flush cache. */ -#define SIOEMU_HYPERCALL_FLUSH_CACHE 0x07 - -/* Get freq base. */ -#define SIOEMU_HYPERCALL_FREQ_BASE 0x08 - -/* Return from callback. */ -#define SIOEMU_HYPERCALL_CALLBACK_RETURN 0x09 - -/* Deliver an interrupt. */ -#define SIOEMU_HYPERCALL_DELIVER_INT 0x0a - -/* SIOEMU callback reason. */ - -/* An event (from event channel) has to be delivered. */ -#define SIOEMU_CB_EVENT 0x00 - -/* Emulate an IO access. */ -#define SIOEMU_CB_IO_EMULATE 0x01 - -/* An IPI is sent to a dead vcpu. */ -#define SIOEMU_CB_WAKEUP_VCPU 0x02 - -/* A SAL hypercall is executed. */ -#define SIOEMU_CB_SAL_ASSIST 0x03 - -#ifndef __ASSEMBLY__ -struct sioemu_callback_info { - /* Saved registers. */ - unsigned long ip; - unsigned long psr; - unsigned long ifs; - unsigned long nats; - unsigned long r8; - unsigned long r9; - unsigned long r10; - unsigned long r11; - - /* Callback parameters. */ - unsigned long cause; - unsigned long arg0; - unsigned long arg1; - unsigned long arg2; - unsigned long arg3; - unsigned long _pad2[2]; - unsigned long r2; -}; -#endif /* __ASSEMBLY__ */ -#endif /* __XEN_PUBLIC_IA64_SIOEMU_H__ */ diff --git a/sys/xen/interface/arch-powerpc.h b/sys/xen/interface/arch-powerpc.h deleted file mode 100644 index d92532f3ce1..00000000000 --- a/sys/xen/interface/arch-powerpc.h +++ /dev/null @@ -1,120 +0,0 @@ -/* - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to - * deal in the Software without restriction, including without limitation the - * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - * Copyright (C) IBM Corp. 2005, 2006 - * - * Authors: Hollis Blanchard - */ - -#include "xen.h" - -#ifndef __XEN_PUBLIC_ARCH_PPC_64_H__ -#define __XEN_PUBLIC_ARCH_PPC_64_H__ - -#define ___DEFINE_XEN_GUEST_HANDLE(name, type) \ - typedef struct { \ - int __pad[(sizeof (long long) - sizeof (void *)) / sizeof (int)]; \ - type *p; \ - } __attribute__((__aligned__(8))) __guest_handle_ ## name - -#define __DEFINE_XEN_GUEST_HANDLE(name, type) \ - ___DEFINE_XEN_GUEST_HANDLE(name, type); \ - ___DEFINE_XEN_GUEST_HANDLE(const_##name, const type) -#define DEFINE_XEN_GUEST_HANDLE(name) __DEFINE_XEN_GUEST_HANDLE(name, name) -#define XEN_GUEST_HANDLE(name) __guest_handle_ ## name -#define set_xen_guest_handle(hnd, val) \ - do { \ - if (sizeof ((hnd).__pad)) \ - (hnd).__pad[0] = 0; \ - (hnd).p = val; \ - } while (0) - -#ifdef __XEN_TOOLS__ -#define get_xen_guest_handle(val, hnd) do { val = (hnd).p; } while (0) -#endif - -#ifndef __ASSEMBLY__ -typedef unsigned long long xen_pfn_t; -#define PRI_xen_pfn "llx" -#endif - -/* - * Pointers and other address fields inside interface structures are padded to - * 64 bits. This means that field alignments aren't different between 32- and - * 64-bit architectures. - */ -/* NB. Multi-level macro ensures __LINE__ is expanded before concatenation. */ -#define __MEMORY_PADDING(_X) -#define _MEMORY_PADDING(_X) __MEMORY_PADDING(_X) -#define MEMORY_PADDING _MEMORY_PADDING(__LINE__) - -/* And the trap vector is... */ -#define TRAP_INSTR "li 0,-1; sc" /* XXX just "sc"? */ - -#ifndef __ASSEMBLY__ - -#define XENCOMM_INLINE_FLAG (1UL << 63) - -typedef uint64_t xen_ulong_t; - -/* User-accessible registers: nost of these need to be saved/restored - * for every nested Xen invocation. */ -struct cpu_user_regs -{ - uint64_t gprs[32]; - uint64_t lr; - uint64_t ctr; - uint64_t srr0; - uint64_t srr1; - uint64_t pc; - uint64_t msr; - uint64_t fpscr; /* XXX Is this necessary */ - uint64_t xer; - uint64_t hid4; /* debug only */ - uint64_t dar; /* debug only */ - uint32_t dsisr; /* debug only */ - uint32_t cr; - uint32_t __pad; /* good spot for another 32bit reg */ - uint32_t entry_vector; -}; -typedef struct cpu_user_regs cpu_user_regs_t; - -typedef uint64_t tsc_timestamp_t; /* RDTSC timestamp */ /* XXX timebase */ - -/* ONLY used to communicate with dom0! See also struct exec_domain. */ -struct vcpu_guest_context { - cpu_user_regs_t user_regs; /* User-level CPU registers */ - uint64_t sdr1; /* Pagetable base */ - /* XXX etc */ -}; -typedef struct vcpu_guest_context vcpu_guest_context_t; -DEFINE_XEN_GUEST_HANDLE(vcpu_guest_context_t); - -struct arch_shared_info { - uint64_t boot_timebase; -}; - -struct arch_vcpu_info { -}; - -/* Support for multi-processor guests. */ -#define MAX_VIRT_CPUS 32 -#endif - -#endif diff --git a/sys/xen/interface/elfstructs.h b/sys/xen/interface/elfstructs.h deleted file mode 100644 index 77362f3b9e8..00000000000 --- a/sys/xen/interface/elfstructs.h +++ /dev/null @@ -1,527 +0,0 @@ -#ifndef __XEN_PUBLIC_ELFSTRUCTS_H__ -#define __XEN_PUBLIC_ELFSTRUCTS_H__ 1 -/* - * Copyright (c) 1995, 1996 Erik Theisen. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -typedef uint8_t Elf_Byte; - -typedef uint32_t Elf32_Addr; /* Unsigned program address */ -typedef uint32_t Elf32_Off; /* Unsigned file offset */ -typedef int32_t Elf32_Sword; /* Signed large integer */ -typedef uint32_t Elf32_Word; /* Unsigned large integer */ -typedef uint16_t Elf32_Half; /* Unsigned medium integer */ - -typedef uint64_t Elf64_Addr; -typedef uint64_t Elf64_Off; -typedef int32_t Elf64_Shalf; - -typedef int32_t Elf64_Sword; -typedef uint32_t Elf64_Word; - -typedef int64_t Elf64_Sxword; -typedef uint64_t Elf64_Xword; - -typedef uint32_t Elf64_Half; -typedef uint16_t Elf64_Quarter; - -/* - * e_ident[] identification indexes - * See http://www.caldera.com/developers/gabi/2000-07-17/ch4.eheader.html - */ -#define EI_MAG0 0 /* file ID */ -#define EI_MAG1 1 /* file ID */ -#define EI_MAG2 2 /* file ID */ -#define EI_MAG3 3 /* file ID */ -#define EI_CLASS 4 /* file class */ -#define EI_DATA 5 /* data encoding */ -#define EI_VERSION 6 /* ELF header version */ -#define EI_OSABI 7 /* OS/ABI ID */ -#define EI_ABIVERSION 8 /* ABI version */ -#define EI_PAD 9 /* start of pad bytes */ -#define EI_NIDENT 16 /* Size of e_ident[] */ - -/* e_ident[] magic number */ -#define ELFMAG0 0x7f /* e_ident[EI_MAG0] */ -#define ELFMAG1 'E' /* e_ident[EI_MAG1] */ -#define ELFMAG2 'L' /* e_ident[EI_MAG2] */ -#define ELFMAG3 'F' /* e_ident[EI_MAG3] */ -#define ELFMAG "\177ELF" /* magic */ -#define SELFMAG 4 /* size of magic */ - -/* e_ident[] file class */ -#define ELFCLASSNONE 0 /* invalid */ -#define ELFCLASS32 1 /* 32-bit objs */ -#define ELFCLASS64 2 /* 64-bit objs */ -#define ELFCLASSNUM 3 /* number of classes */ - -/* e_ident[] data encoding */ -#define ELFDATANONE 0 /* invalid */ -#define ELFDATA2LSB 1 /* Little-Endian */ -#define ELFDATA2MSB 2 /* Big-Endian */ -#define ELFDATANUM 3 /* number of data encode defines */ - -/* e_ident[] Operating System/ABI */ -#define ELFOSABI_SYSV 0 /* UNIX System V ABI */ -#define ELFOSABI_HPUX 1 /* HP-UX operating system */ -#define ELFOSABI_NETBSD 2 /* NetBSD */ -#define ELFOSABI_LINUX 3 /* GNU/Linux */ -#define ELFOSABI_HURD 4 /* GNU/Hurd */ -#define ELFOSABI_86OPEN 5 /* 86Open common IA32 ABI */ -#define ELFOSABI_SOLARIS 6 /* Solaris */ -#define ELFOSABI_MONTEREY 7 /* Monterey */ -#define ELFOSABI_IRIX 8 /* IRIX */ -#define ELFOSABI_FREEBSD 9 /* FreeBSD */ -#define ELFOSABI_TRU64 10 /* TRU64 UNIX */ -#define ELFOSABI_MODESTO 11 /* Novell Modesto */ -#define ELFOSABI_OPENBSD 12 /* OpenBSD */ -#define ELFOSABI_ARM 97 /* ARM */ -#define ELFOSABI_STANDALONE 255 /* Standalone (embedded) application */ - -/* e_ident */ -#define IS_ELF(ehdr) ((ehdr).e_ident[EI_MAG0] == ELFMAG0 && \ - (ehdr).e_ident[EI_MAG1] == ELFMAG1 && \ - (ehdr).e_ident[EI_MAG2] == ELFMAG2 && \ - (ehdr).e_ident[EI_MAG3] == ELFMAG3) - -/* ELF Header */ -typedef struct elfhdr { - unsigned char e_ident[EI_NIDENT]; /* ELF Identification */ - Elf32_Half e_type; /* object file type */ - Elf32_Half e_machine; /* machine */ - Elf32_Word e_version; /* object file version */ - Elf32_Addr e_entry; /* virtual entry point */ - Elf32_Off e_phoff; /* program header table offset */ - Elf32_Off e_shoff; /* section header table offset */ - Elf32_Word e_flags; /* processor-specific flags */ - Elf32_Half e_ehsize; /* ELF header size */ - Elf32_Half e_phentsize; /* program header entry size */ - Elf32_Half e_phnum; /* number of program header entries */ - Elf32_Half e_shentsize; /* section header entry size */ - Elf32_Half e_shnum; /* number of section header entries */ - Elf32_Half e_shstrndx; /* section header table's "section - header string table" entry offset */ -} Elf32_Ehdr; - -typedef struct { - unsigned char e_ident[EI_NIDENT]; /* Id bytes */ - Elf64_Quarter e_type; /* file type */ - Elf64_Quarter e_machine; /* machine type */ - Elf64_Half e_version; /* version number */ - Elf64_Addr e_entry; /* entry point */ - Elf64_Off e_phoff; /* Program hdr offset */ - Elf64_Off e_shoff; /* Section hdr offset */ - Elf64_Half e_flags; /* Processor flags */ - Elf64_Quarter e_ehsize; /* sizeof ehdr */ - Elf64_Quarter e_phentsize; /* Program header entry size */ - Elf64_Quarter e_phnum; /* Number of program headers */ - Elf64_Quarter e_shentsize; /* Section header entry size */ - Elf64_Quarter e_shnum; /* Number of section headers */ - Elf64_Quarter e_shstrndx; /* String table index */ -} Elf64_Ehdr; - -/* e_type */ -#define ET_NONE 0 /* No file type */ -#define ET_REL 1 /* relocatable file */ -#define ET_EXEC 2 /* executable file */ -#define ET_DYN 3 /* shared object file */ -#define ET_CORE 4 /* core file */ -#define ET_NUM 5 /* number of types */ -#define ET_LOPROC 0xff00 /* reserved range for processor */ -#define ET_HIPROC 0xffff /* specific e_type */ - -/* e_machine */ -#define EM_NONE 0 /* No Machine */ -#define EM_M32 1 /* AT&T WE 32100 */ -#define EM_SPARC 2 /* SPARC */ -#define EM_386 3 /* Intel 80386 */ -#define EM_68K 4 /* Motorola 68000 */ -#define EM_88K 5 /* Motorola 88000 */ -#define EM_486 6 /* Intel 80486 - unused? */ -#define EM_860 7 /* Intel 80860 */ -#define EM_MIPS 8 /* MIPS R3000 Big-Endian only */ -/* - * Don't know if EM_MIPS_RS4_BE, - * EM_SPARC64, EM_PARISC, - * or EM_PPC are ABI compliant - */ -#define EM_MIPS_RS4_BE 10 /* MIPS R4000 Big-Endian */ -#define EM_SPARC64 11 /* SPARC v9 64-bit unoffical */ -#define EM_PARISC 15 /* HPPA */ -#define EM_SPARC32PLUS 18 /* Enhanced instruction set SPARC */ -#define EM_PPC 20 /* PowerPC */ -#define EM_PPC64 21 /* PowerPC 64-bit */ -#define EM_ARM 40 /* Advanced RISC Machines ARM */ -#define EM_ALPHA 41 /* DEC ALPHA */ -#define EM_SPARCV9 43 /* SPARC version 9 */ -#define EM_ALPHA_EXP 0x9026 /* DEC ALPHA */ -#define EM_IA_64 50 /* Intel Merced */ -#define EM_X86_64 62 /* AMD x86-64 architecture */ -#define EM_VAX 75 /* DEC VAX */ - -/* Version */ -#define EV_NONE 0 /* Invalid */ -#define EV_CURRENT 1 /* Current */ -#define EV_NUM 2 /* number of versions */ - -/* Section Header */ -typedef struct { - Elf32_Word sh_name; /* name - index into section header - string table section */ - Elf32_Word sh_type; /* type */ - Elf32_Word sh_flags; /* flags */ - Elf32_Addr sh_addr; /* address */ - Elf32_Off sh_offset; /* file offset */ - Elf32_Word sh_size; /* section size */ - Elf32_Word sh_link; /* section header table index link */ - Elf32_Word sh_info; /* extra information */ - Elf32_Word sh_addralign; /* address alignment */ - Elf32_Word sh_entsize; /* section entry size */ -} Elf32_Shdr; - -typedef struct { - Elf64_Half sh_name; /* section name */ - Elf64_Half sh_type; /* section type */ - Elf64_Xword sh_flags; /* section flags */ - Elf64_Addr sh_addr; /* virtual address */ - Elf64_Off sh_offset; /* file offset */ - Elf64_Xword sh_size; /* section size */ - Elf64_Half sh_link; /* link to another */ - Elf64_Half sh_info; /* misc info */ - Elf64_Xword sh_addralign; /* memory alignment */ - Elf64_Xword sh_entsize; /* table entry size */ -} Elf64_Shdr; - -/* Special Section Indexes */ -#define SHN_UNDEF 0 /* undefined */ -#define SHN_LORESERVE 0xff00 /* lower bounds of reserved indexes */ -#define SHN_LOPROC 0xff00 /* reserved range for processor */ -#define SHN_HIPROC 0xff1f /* specific section indexes */ -#define SHN_ABS 0xfff1 /* absolute value */ -#define SHN_COMMON 0xfff2 /* common symbol */ -#define SHN_HIRESERVE 0xffff /* upper bounds of reserved indexes */ - -/* sh_type */ -#define SHT_NULL 0 /* inactive */ -#define SHT_PROGBITS 1 /* program defined information */ -#define SHT_SYMTAB 2 /* symbol table section */ -#define SHT_STRTAB 3 /* string table section */ -#define SHT_RELA 4 /* relocation section with addends*/ -#define SHT_HASH 5 /* symbol hash table section */ -#define SHT_DYNAMIC 6 /* dynamic section */ -#define SHT_NOTE 7 /* note section */ -#define SHT_NOBITS 8 /* no space section */ -#define SHT_REL 9 /* relation section without addends */ -#define SHT_SHLIB 10 /* reserved - purpose unknown */ -#define SHT_DYNSYM 11 /* dynamic symbol table section */ -#define SHT_NUM 12 /* number of section types */ -#define SHT_LOPROC 0x70000000 /* reserved range for processor */ -#define SHT_HIPROC 0x7fffffff /* specific section header types */ -#define SHT_LOUSER 0x80000000 /* reserved range for application */ -#define SHT_HIUSER 0xffffffff /* specific indexes */ - -/* Section names */ -#define ELF_BSS ".bss" /* uninitialized data */ -#define ELF_DATA ".data" /* initialized data */ -#define ELF_DEBUG ".debug" /* debug */ -#define ELF_DYNAMIC ".dynamic" /* dynamic linking information */ -#define ELF_DYNSTR ".dynstr" /* dynamic string table */ -#define ELF_DYNSYM ".dynsym" /* dynamic symbol table */ -#define ELF_FINI ".fini" /* termination code */ -#define ELF_GOT ".got" /* global offset table */ -#define ELF_HASH ".hash" /* symbol hash table */ -#define ELF_INIT ".init" /* initialization code */ -#define ELF_REL_DATA ".rel.data" /* relocation data */ -#define ELF_REL_FINI ".rel.fini" /* relocation termination code */ -#define ELF_REL_INIT ".rel.init" /* relocation initialization code */ -#define ELF_REL_DYN ".rel.dyn" /* relocaltion dynamic link info */ -#define ELF_REL_RODATA ".rel.rodata" /* relocation read-only data */ -#define ELF_REL_TEXT ".rel.text" /* relocation code */ -#define ELF_RODATA ".rodata" /* read-only data */ -#define ELF_SHSTRTAB ".shstrtab" /* section header string table */ -#define ELF_STRTAB ".strtab" /* string table */ -#define ELF_SYMTAB ".symtab" /* symbol table */ -#define ELF_TEXT ".text" /* code */ - - -/* Section Attribute Flags - sh_flags */ -#define SHF_WRITE 0x1 /* Writable */ -#define SHF_ALLOC 0x2 /* occupies memory */ -#define SHF_EXECINSTR 0x4 /* executable */ -#define SHF_MASKPROC 0xf0000000 /* reserved bits for processor */ - /* specific section attributes */ - -/* Symbol Table Entry */ -typedef struct elf32_sym { - Elf32_Word st_name; /* name - index into string table */ - Elf32_Addr st_value; /* symbol value */ - Elf32_Word st_size; /* symbol size */ - unsigned char st_info; /* type and binding */ - unsigned char st_other; /* 0 - no defined meaning */ - Elf32_Half st_shndx; /* section header index */ -} Elf32_Sym; - -typedef struct { - Elf64_Half st_name; /* Symbol name index in str table */ - Elf_Byte st_info; /* type / binding attrs */ - Elf_Byte st_other; /* unused */ - Elf64_Quarter st_shndx; /* section index of symbol */ - Elf64_Xword st_value; /* value of symbol */ - Elf64_Xword st_size; /* size of symbol */ -} Elf64_Sym; - -/* Symbol table index */ -#define STN_UNDEF 0 /* undefined */ - -/* Extract symbol info - st_info */ -#define ELF32_ST_BIND(x) ((x) >> 4) -#define ELF32_ST_TYPE(x) (((unsigned int) x) & 0xf) -#define ELF32_ST_INFO(b,t) (((b) << 4) + ((t) & 0xf)) - -#define ELF64_ST_BIND(x) ((x) >> 4) -#define ELF64_ST_TYPE(x) (((unsigned int) x) & 0xf) -#define ELF64_ST_INFO(b,t) (((b) << 4) + ((t) & 0xf)) - -/* Symbol Binding - ELF32_ST_BIND - st_info */ -#define STB_LOCAL 0 /* Local symbol */ -#define STB_GLOBAL 1 /* Global symbol */ -#define STB_WEAK 2 /* like global - lower precedence */ -#define STB_NUM 3 /* number of symbol bindings */ -#define STB_LOPROC 13 /* reserved range for processor */ -#define STB_HIPROC 15 /* specific symbol bindings */ - -/* Symbol type - ELF32_ST_TYPE - st_info */ -#define STT_NOTYPE 0 /* not specified */ -#define STT_OBJECT 1 /* data object */ -#define STT_FUNC 2 /* function */ -#define STT_SECTION 3 /* section */ -#define STT_FILE 4 /* file */ -#define STT_NUM 5 /* number of symbol types */ -#define STT_LOPROC 13 /* reserved range for processor */ -#define STT_HIPROC 15 /* specific symbol types */ - -/* Relocation entry with implicit addend */ -typedef struct { - Elf32_Addr r_offset; /* offset of relocation */ - Elf32_Word r_info; /* symbol table index and type */ -} Elf32_Rel; - -/* Relocation entry with explicit addend */ -typedef struct { - Elf32_Addr r_offset; /* offset of relocation */ - Elf32_Word r_info; /* symbol table index and type */ - Elf32_Sword r_addend; -} Elf32_Rela; - -/* Extract relocation info - r_info */ -#define ELF32_R_SYM(i) ((i) >> 8) -#define ELF32_R_TYPE(i) ((unsigned char) (i)) -#define ELF32_R_INFO(s,t) (((s) << 8) + (unsigned char)(t)) - -typedef struct { - Elf64_Xword r_offset; /* where to do it */ - Elf64_Xword r_info; /* index & type of relocation */ -} Elf64_Rel; - -typedef struct { - Elf64_Xword r_offset; /* where to do it */ - Elf64_Xword r_info; /* index & type of relocation */ - Elf64_Sxword r_addend; /* adjustment value */ -} Elf64_Rela; - -#define ELF64_R_SYM(info) ((info) >> 32) -#define ELF64_R_TYPE(info) ((info) & 0xFFFFFFFF) -#define ELF64_R_INFO(s,t) (((s) << 32) + (u_int32_t)(t)) - -/* Program Header */ -typedef struct { - Elf32_Word p_type; /* segment type */ - Elf32_Off p_offset; /* segment offset */ - Elf32_Addr p_vaddr; /* virtual address of segment */ - Elf32_Addr p_paddr; /* physical address - ignored? */ - Elf32_Word p_filesz; /* number of bytes in file for seg. */ - Elf32_Word p_memsz; /* number of bytes in mem. for seg. */ - Elf32_Word p_flags; /* flags */ - Elf32_Word p_align; /* memory alignment */ -} Elf32_Phdr; - -typedef struct { - Elf64_Half p_type; /* entry type */ - Elf64_Half p_flags; /* flags */ - Elf64_Off p_offset; /* offset */ - Elf64_Addr p_vaddr; /* virtual address */ - Elf64_Addr p_paddr; /* physical address */ - Elf64_Xword p_filesz; /* file size */ - Elf64_Xword p_memsz; /* memory size */ - Elf64_Xword p_align; /* memory & file alignment */ -} Elf64_Phdr; - -/* Segment types - p_type */ -#define PT_NULL 0 /* unused */ -#define PT_LOAD 1 /* loadable segment */ -#define PT_DYNAMIC 2 /* dynamic linking section */ -#define PT_INTERP 3 /* the RTLD */ -#define PT_NOTE 4 /* auxiliary information */ -#define PT_SHLIB 5 /* reserved - purpose undefined */ -#define PT_PHDR 6 /* program header */ -#define PT_NUM 7 /* Number of segment types */ -#define PT_LOPROC 0x70000000 /* reserved range for processor */ -#define PT_HIPROC 0x7fffffff /* specific segment types */ - -/* Segment flags - p_flags */ -#define PF_X 0x1 /* Executable */ -#define PF_W 0x2 /* Writable */ -#define PF_R 0x4 /* Readable */ -#define PF_MASKPROC 0xf0000000 /* reserved bits for processor */ - /* specific segment flags */ - -/* Dynamic structure */ -typedef struct { - Elf32_Sword d_tag; /* controls meaning of d_val */ - union { - Elf32_Word d_val; /* Multiple meanings - see d_tag */ - Elf32_Addr d_ptr; /* program virtual address */ - } d_un; -} Elf32_Dyn; - -typedef struct { - Elf64_Xword d_tag; /* controls meaning of d_val */ - union { - Elf64_Addr d_ptr; - Elf64_Xword d_val; - } d_un; -} Elf64_Dyn; - -/* Dynamic Array Tags - d_tag */ -#define DT_NULL 0 /* marks end of _DYNAMIC array */ -#define DT_NEEDED 1 /* string table offset of needed lib */ -#define DT_PLTRELSZ 2 /* size of relocation entries in PLT */ -#define DT_PLTGOT 3 /* address PLT/GOT */ -#define DT_HASH 4 /* address of symbol hash table */ -#define DT_STRTAB 5 /* address of string table */ -#define DT_SYMTAB 6 /* address of symbol table */ -#define DT_RELA 7 /* address of relocation table */ -#define DT_RELASZ 8 /* size of relocation table */ -#define DT_RELAENT 9 /* size of relocation entry */ -#define DT_STRSZ 10 /* size of string table */ -#define DT_SYMENT 11 /* size of symbol table entry */ -#define DT_INIT 12 /* address of initialization func. */ -#define DT_FINI 13 /* address of termination function */ -#define DT_SONAME 14 /* string table offset of shared obj */ -#define DT_RPATH 15 /* string table offset of library - search path */ -#define DT_SYMBOLIC 16 /* start sym search in shared obj. */ -#define DT_REL 17 /* address of rel. tbl. w addends */ -#define DT_RELSZ 18 /* size of DT_REL relocation table */ -#define DT_RELENT 19 /* size of DT_REL relocation entry */ -#define DT_PLTREL 20 /* PLT referenced relocation entry */ -#define DT_DEBUG 21 /* bugger */ -#define DT_TEXTREL 22 /* Allow rel. mod. to unwritable seg */ -#define DT_JMPREL 23 /* add. of PLT's relocation entries */ -#define DT_BIND_NOW 24 /* Bind now regardless of env setting */ -#define DT_NUM 25 /* Number used. */ -#define DT_LOPROC 0x70000000 /* reserved range for processor */ -#define DT_HIPROC 0x7fffffff /* specific dynamic array tags */ - -/* Standard ELF hashing function */ -unsigned int elf_hash(const unsigned char *name); - -/* - * Note Definitions - */ -typedef struct { - Elf32_Word namesz; - Elf32_Word descsz; - Elf32_Word type; -} Elf32_Note; - -typedef struct { - Elf64_Half namesz; - Elf64_Half descsz; - Elf64_Half type; -} Elf64_Note; - - -#if defined(ELFSIZE) -#define CONCAT(x,y) __CONCAT(x,y) -#define ELFNAME(x) CONCAT(elf,CONCAT(ELFSIZE,CONCAT(_,x))) -#define ELFNAME2(x,y) CONCAT(x,CONCAT(_elf,CONCAT(ELFSIZE,CONCAT(_,y)))) -#define ELFNAMEEND(x) CONCAT(x,CONCAT(_elf,ELFSIZE)) -#define ELFDEFNNAME(x) CONCAT(ELF,CONCAT(ELFSIZE,CONCAT(_,x))) -#endif - -#if defined(ELFSIZE) && (ELFSIZE == 32) -#define Elf_Ehdr Elf32_Ehdr -#define Elf_Phdr Elf32_Phdr -#define Elf_Shdr Elf32_Shdr -#define Elf_Sym Elf32_Sym -#define Elf_Rel Elf32_Rel -#define Elf_RelA Elf32_Rela -#define Elf_Dyn Elf32_Dyn -#define Elf_Word Elf32_Word -#define Elf_Sword Elf32_Sword -#define Elf_Addr Elf32_Addr -#define Elf_Off Elf32_Off -#define Elf_Nhdr Elf32_Nhdr -#define Elf_Note Elf32_Note - -#define ELF_R_SYM ELF32_R_SYM -#define ELF_R_TYPE ELF32_R_TYPE -#define ELF_R_INFO ELF32_R_INFO -#define ELFCLASS ELFCLASS32 - -#define ELF_ST_BIND ELF32_ST_BIND -#define ELF_ST_TYPE ELF32_ST_TYPE -#define ELF_ST_INFO ELF32_ST_INFO - -#define AuxInfo Aux32Info -#elif defined(ELFSIZE) && (ELFSIZE == 64) -#define Elf_Ehdr Elf64_Ehdr -#define Elf_Phdr Elf64_Phdr -#define Elf_Shdr Elf64_Shdr -#define Elf_Sym Elf64_Sym -#define Elf_Rel Elf64_Rel -#define Elf_RelA Elf64_Rela -#define Elf_Dyn Elf64_Dyn -#define Elf_Word Elf64_Word -#define Elf_Sword Elf64_Sword -#define Elf_Addr Elf64_Addr -#define Elf_Off Elf64_Off -#define Elf_Nhdr Elf64_Nhdr -#define Elf_Note Elf64_Note - -#define ELF_R_SYM ELF64_R_SYM -#define ELF_R_TYPE ELF64_R_TYPE -#define ELF_R_INFO ELF64_R_INFO -#define ELFCLASS ELFCLASS64 - -#define ELF_ST_BIND ELF64_ST_BIND -#define ELF_ST_TYPE ELF64_ST_TYPE -#define ELF_ST_INFO ELF64_ST_INFO - -#define AuxInfo Aux64Info -#endif - -#endif /* __XEN_PUBLIC_ELFSTRUCTS_H__ */ diff --git a/sys/xen/interface/foreign/Makefile b/sys/xen/interface/foreign/Makefile deleted file mode 100644 index 7bde873d757..00000000000 --- a/sys/xen/interface/foreign/Makefile +++ /dev/null @@ -1,37 +0,0 @@ -XEN_ROOT=../../../.. -include $(XEN_ROOT)/Config.mk - -architectures := x86_32 x86_64 ia64 -headers := $(patsubst %, %.h, $(architectures)) -scripts := $(wildcard *.py) - -.PHONY: all clean check-headers -all: $(headers) check-headers - -clean: - rm -f $(headers) - rm -f checker checker.c $(XEN_TARGET_ARCH).size - rm -f *.pyc *.o *~ - -ifeq ($(CROSS_COMPILE)$(XEN_TARGET_ARCH),$(XEN_COMPILE_ARCH)) -check-headers: checker - ./checker > $(XEN_TARGET_ARCH).size - diff -u reference.size $(XEN_TARGET_ARCH).size -checker: checker.c $(headers) - $(HOSTCC) $(HOSTCFLAGS) -o $@ $< -else -check-headers: - @echo "cross build: skipping check" -endif - -x86_32.h: ../arch-x86/xen-x86_32.h ../arch-x86/xen.h ../xen.h $(scripts) - python mkheader.py $* $@ $(filter %.h,$^) - -x86_64.h: ../arch-x86/xen-x86_64.h ../arch-x86/xen.h ../xen.h $(scripts) - python mkheader.py $* $@ $(filter %.h,$^) - -ia64.h: ../arch-ia64.h ../xen.h $(scripts) - python mkheader.py $* $@ $(filter %.h,$^) - -checker.c: $(scripts) - python mkchecker.py $(XEN_TARGET_ARCH) $@ $(architectures) diff --git a/sys/xen/interface/foreign/mkchecker.py b/sys/xen/interface/foreign/mkchecker.py deleted file mode 100644 index 9da1e2b1d1c..00000000000 --- a/sys/xen/interface/foreign/mkchecker.py +++ /dev/null @@ -1,58 +0,0 @@ -#!/usr/bin/python - -import sys; -from structs import structs; - -# command line arguments -arch = sys.argv[1]; -outfile = sys.argv[2]; -archs = sys.argv[3:]; - -f = open(outfile, "w"); -f.write(''' -/* - * sanity checks for generated foreign headers: - * - verify struct sizes - * - * generated by %s -- DO NOT EDIT - */ -#include -#include -#include -#include -#include "../xen.h" -'''); - -for a in archs: - f.write('#include "%s.h"\n' % a); - -f.write('int main(int argc, char *argv[])\n{\n'); - -f.write('\tprintf("\\n");'); -f.write('printf("%-25s |", "structs");\n'); -for a in archs: - f.write('\tprintf("%%8s", "%s");\n' % a); -f.write('\tprintf("\\n");'); - -f.write('\tprintf("\\n");'); -for struct in structs: - f.write('\tprintf("%%-25s |", "%s");\n' % struct); - for a in archs: - if a == arch: - s = struct; # native - else: - s = struct + "_" + a; - f.write('#ifdef %s_has_no_%s\n' % (a, struct)); - f.write('\tprintf("%8s", "-");\n'); - f.write("#else\n"); - f.write('\tprintf("%%8zd", sizeof(struct %s));\n' % s); - f.write("#endif\n"); - - f.write('\tprintf("\\n");\n\n'); - -f.write('\tprintf("\\n");\n'); -f.write('\texit(0);\n'); -f.write('}\n'); - -f.close(); - diff --git a/sys/xen/interface/foreign/mkheader.py b/sys/xen/interface/foreign/mkheader.py deleted file mode 100644 index d833c7e4365..00000000000 --- a/sys/xen/interface/foreign/mkheader.py +++ /dev/null @@ -1,167 +0,0 @@ -#!/usr/bin/python - -import sys, re; -from structs import unions, structs, defines; - -# command line arguments -arch = sys.argv[1]; -outfile = sys.argv[2]; -infiles = sys.argv[3:]; - - -########################################################################### -# configuration #2: architecture information - -inttypes = {}; -header = {}; -footer = {}; - -# x86_32 -inttypes["x86_32"] = { - "unsigned long" : "uint32_t", - "long" : "uint32_t", - "xen_pfn_t" : "uint32_t", -}; -header["x86_32"] = """ -#define __i386___X86_32 1 -#pragma pack(4) -"""; -footer["x86_32"] = """ -#pragma pack() -"""; - -# x86_64 -inttypes["x86_64"] = { - "unsigned long" : "__align8__ uint64_t", - "long" : "__align8__ uint64_t", - "xen_pfn_t" : "__align8__ uint64_t", -}; -header["x86_64"] = """ -#ifdef __GNUC__ -# define __DECL_REG(name) union { uint64_t r ## name, e ## name; } -# define __align8__ __attribute__((aligned (8))) -#else -# define __DECL_REG(name) uint64_t r ## name -# define __align8__ FIXME -#endif -#define __x86_64___X86_64 1 -"""; - -# ia64 -inttypes["ia64"] = { - "unsigned long" : "__align8__ uint64_t", - "long" : "__align8__ uint64_t", - "xen_pfn_t" : "__align8__ uint64_t", - "long double" : "__align16__ ldouble_t", -}; -header["ia64"] = """ -#define __align8__ __attribute__((aligned (8))) -#define __align16__ __attribute__((aligned (16))) -typedef unsigned char ldouble_t[16]; -"""; - - -########################################################################### -# main - -input = ""; -output = ""; -fileid = re.sub("[-.]", "_", "__FOREIGN_%s__" % outfile.upper()); - -# read input header files -for name in infiles: - f = open(name, "r"); - input += f.read(); - f.close(); - -# add header -output += """ -/* - * public xen defines and struct for %s - * generated by %s -- DO NOT EDIT - */ - -#ifndef %s -#define %s 1 - -""" % (arch, sys.argv[0], fileid, fileid) - -if arch in header: - output += header[arch]; - output += "\n"; - -# add defines to output -for line in re.findall("#define[^\n]+", input): - for define in defines: - regex = "#define\s+%s\\b" % define; - match = re.search(regex, line); - if None == match: - continue; - if define.upper()[0] == define[0]: - replace = define + "_" + arch.upper(); - else: - replace = define + "_" + arch; - regex = "\\b%s\\b" % define; - output += re.sub(regex, replace, line) + "\n"; -output += "\n"; - -# delete defines, comments, empty lines -input = re.sub("#define[^\n]+\n", "", input); -input = re.compile("/\*(.*?)\*/", re.S).sub("", input) -input = re.compile("\n\s*\n", re.S).sub("\n", input); - -# add unions to output -for union in unions: - regex = "union\s+%s\s*\{(.*?)\n\};" % union; - match = re.search(regex, input, re.S) - if None == match: - output += "#define %s_has_no_%s 1\n" % (arch, union); - else: - output += "union %s_%s {%s\n};\n" % (union, arch, match.group(1)); - output += "\n"; - -# add structs to output -for struct in structs: - regex = "struct\s+%s\s*\{(.*?)\n\};" % struct; - match = re.search(regex, input, re.S) - if None == match: - output += "#define %s_has_no_%s 1\n" % (arch, struct); - else: - output += "struct %s_%s {%s\n};\n" % (struct, arch, match.group(1)); - output += "typedef struct %s_%s %s_%s_t;\n" % (struct, arch, struct, arch); - output += "\n"; - -# add footer -if arch in footer: - output += footer[arch]; - output += "\n"; -output += "#endif /* %s */\n" % fileid; - -# replace: defines -for define in defines: - if define.upper()[0] == define[0]: - replace = define + "_" + arch.upper(); - else: - replace = define + "_" + arch; - output = re.sub("\\b%s\\b" % define, replace, output); - -# replace: unions -for union in unions: - output = re.sub("\\b(union\s+%s)\\b" % union, "\\1_%s" % arch, output); - -# replace: structs + struct typedefs -for struct in structs: - output = re.sub("\\b(struct\s+%s)\\b" % struct, "\\1_%s" % arch, output); - output = re.sub("\\b(%s)_t\\b" % struct, "\\1_%s_t" % arch, output); - -# replace: integer types -integers = list(inttypes[arch].keys()); -integers.sort(lambda a, b: cmp(len(b),len(a))); -for type in integers: - output = re.sub("\\b%s\\b" % type, inttypes[arch][type], output); - -# print results -f = open(outfile, "w"); -f.write(output); -f.close; - diff --git a/sys/xen/interface/foreign/reference.size b/sys/xen/interface/foreign/reference.size deleted file mode 100644 index f35d281d485..00000000000 --- a/sys/xen/interface/foreign/reference.size +++ /dev/null @@ -1,17 +0,0 @@ - -structs | x86_32 x86_64 ia64 - -start_info | 1104 1152 1152 -trap_info | 8 16 - -pt_fpreg | - - 16 -cpu_user_regs | 68 200 496 -xen_ia64_boot_param | - - 96 -ia64_tr_entry | - - 32 -vcpu_extra_regs | - - 536 -vcpu_guest_context | 2800 5168 1056 -arch_vcpu_info | 24 16 0 -vcpu_time_info | 32 32 32 -vcpu_info | 64 64 48 -arch_shared_info | 268 280 272 -shared_info | 2584 3368 4384 - diff --git a/sys/xen/interface/foreign/structs.py b/sys/xen/interface/foreign/structs.py deleted file mode 100644 index a1bc055a197..00000000000 --- a/sys/xen/interface/foreign/structs.py +++ /dev/null @@ -1,58 +0,0 @@ -# configuration: what needs translation - -unions = [ "vcpu_cr_regs", - "vcpu_ar_regs" ]; - -structs = [ "start_info", - "trap_info", - "pt_fpreg", - "cpu_user_regs", - "xen_ia64_boot_param", - "ia64_tr_entry", - "vcpu_tr_regs", - "vcpu_guest_context_regs", - "vcpu_guest_context", - "arch_vcpu_info", - "vcpu_time_info", - "vcpu_info", - "arch_shared_info", - "shared_info" ]; - -defines = [ "__i386__", - "__x86_64__", - - "FLAT_RING1_CS", - "FLAT_RING1_DS", - "FLAT_RING1_SS", - - "FLAT_RING3_CS64", - "FLAT_RING3_DS64", - "FLAT_RING3_SS64", - "FLAT_KERNEL_CS64", - "FLAT_KERNEL_DS64", - "FLAT_KERNEL_SS64", - - "FLAT_KERNEL_CS", - "FLAT_KERNEL_DS", - "FLAT_KERNEL_SS", - - # x86_{32,64} - "_VGCF_i387_valid", - "VGCF_i387_valid", - "_VGCF_in_kernel", - "VGCF_in_kernel", - "_VGCF_failsafe_disables_events", - "VGCF_failsafe_disables_events", - "_VGCF_syscall_disables_events", - "VGCF_syscall_disables_events", - "_VGCF_online", - "VGCF_online", - - # ia64 - "VGCF_EXTRA_REGS", - - # all archs - "xen_pfn_to_cr3", - "XEN_LEGACY_MAX_VCPUS", - "MAX_GUEST_CMDLINE" ]; - diff --git a/sys/xen/interface/libelf.h b/sys/xen/interface/libelf.h deleted file mode 100644 index d2383301fa1..00000000000 --- a/sys/xen/interface/libelf.h +++ /dev/null @@ -1,265 +0,0 @@ -/****************************************************************************** - * libelf.h - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to - * deal in the Software without restriction, including without limitation the - * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef __XC_LIBELF__ -#define __XC_LIBELF__ 1 - -#if defined(__i386__) || defined(__x86_64__) || defined(__ia64__) -#define XEN_ELF_LITTLE_ENDIAN -#else -#error define architectural endianness -#endif - -#undef ELFSIZE -#include "elfnote.h" -#include "elfstructs.h" -#include "features.h" - -/* ------------------------------------------------------------------------ */ - -typedef union { - Elf32_Ehdr e32; - Elf64_Ehdr e64; -} elf_ehdr; - -typedef union { - Elf32_Phdr e32; - Elf64_Phdr e64; -} elf_phdr; - -typedef union { - Elf32_Shdr e32; - Elf64_Shdr e64; -} elf_shdr; - -typedef union { - Elf32_Sym e32; - Elf64_Sym e64; -} elf_sym; - -typedef union { - Elf32_Rel e32; - Elf64_Rel e64; -} elf_rel; - -typedef union { - Elf32_Rela e32; - Elf64_Rela e64; -} elf_rela; - -typedef union { - Elf32_Note e32; - Elf64_Note e64; -} elf_note; - -struct elf_binary { - /* elf binary */ - const char *image; - size_t size; - char class; - char data; - - const elf_ehdr *ehdr; - const char *sec_strtab; - const elf_shdr *sym_tab; - const char *sym_strtab; - - /* loaded to */ - char *dest; - uint64_t pstart; - uint64_t pend; - uint64_t reloc_offset; - - uint64_t bsd_symtab_pstart; - uint64_t bsd_symtab_pend; - -#ifndef __XEN__ - /* misc */ - FILE *log; -#endif - int verbose; -}; - -/* ------------------------------------------------------------------------ */ -/* accessing elf header fields */ - -#ifdef XEN_ELF_BIG_ENDIAN -# define NATIVE_ELFDATA ELFDATA2MSB -#else -# define NATIVE_ELFDATA ELFDATA2LSB -#endif - -#define elf_32bit(elf) (ELFCLASS32 == (elf)->class) -#define elf_64bit(elf) (ELFCLASS64 == (elf)->class) -#define elf_msb(elf) (ELFDATA2MSB == (elf)->data) -#define elf_lsb(elf) (ELFDATA2LSB == (elf)->data) -#define elf_swap(elf) (NATIVE_ELFDATA != (elf)->data) - -#define elf_uval(elf, str, elem) \ - ((ELFCLASS64 == (elf)->class) \ - ? elf_access_unsigned((elf), (str), \ - offsetof(typeof(*(str)),e64.elem), \ - sizeof((str)->e64.elem)) \ - : elf_access_unsigned((elf), (str), \ - offsetof(typeof(*(str)),e32.elem), \ - sizeof((str)->e32.elem))) - -#define elf_sval(elf, str, elem) \ - ((ELFCLASS64 == (elf)->class) \ - ? elf_access_signed((elf), (str), \ - offsetof(typeof(*(str)),e64.elem), \ - sizeof((str)->e64.elem)) \ - : elf_access_signed((elf), (str), \ - offsetof(typeof(*(str)),e32.elem), \ - sizeof((str)->e32.elem))) - -#define elf_size(elf, str) \ - ((ELFCLASS64 == (elf)->class) \ - ? sizeof((str)->e64) : sizeof((str)->e32)) - -uint64_t elf_access_unsigned(struct elf_binary *elf, const void *ptr, - uint64_t offset, size_t size); -int64_t elf_access_signed(struct elf_binary *elf, const void *ptr, - uint64_t offset, size_t size); - -uint64_t elf_round_up(struct elf_binary *elf, uint64_t addr); - -/* ------------------------------------------------------------------------ */ -/* xc_libelf_tools.c */ - -int elf_shdr_count(struct elf_binary *elf); -int elf_phdr_count(struct elf_binary *elf); - -const elf_shdr *elf_shdr_by_name(struct elf_binary *elf, const char *name); -const elf_shdr *elf_shdr_by_index(struct elf_binary *elf, int index); -const elf_phdr *elf_phdr_by_index(struct elf_binary *elf, int index); - -const char *elf_section_name(struct elf_binary *elf, const elf_shdr * shdr); -const void *elf_section_start(struct elf_binary *elf, const elf_shdr * shdr); -const void *elf_section_end(struct elf_binary *elf, const elf_shdr * shdr); - -const void *elf_segment_start(struct elf_binary *elf, const elf_phdr * phdr); -const void *elf_segment_end(struct elf_binary *elf, const elf_phdr * phdr); - -const elf_sym *elf_sym_by_name(struct elf_binary *elf, const char *symbol); -const elf_sym *elf_sym_by_index(struct elf_binary *elf, int index); - -const char *elf_note_name(struct elf_binary *elf, const elf_note * note); -const void *elf_note_desc(struct elf_binary *elf, const elf_note * note); -uint64_t elf_note_numeric(struct elf_binary *elf, const elf_note * note); -const elf_note *elf_note_next(struct elf_binary *elf, const elf_note * note); - -int elf_is_elfbinary(const void *image); -int elf_phdr_is_loadable(struct elf_binary *elf, const elf_phdr * phdr); - -/* ------------------------------------------------------------------------ */ -/* xc_libelf_loader.c */ - -int elf_init(struct elf_binary *elf, const char *image, size_t size); -#ifdef __XEN__ -void elf_set_verbose(struct elf_binary *elf); -#else -void elf_set_logfile(struct elf_binary *elf, FILE * log, int verbose); -#endif - -void elf_parse_binary(struct elf_binary *elf); -void elf_load_binary(struct elf_binary *elf); - -void *elf_get_ptr(struct elf_binary *elf, unsigned long addr); -uint64_t elf_lookup_addr(struct elf_binary *elf, const char *symbol); - -void elf_parse_bsdsyms(struct elf_binary *elf, uint64_t pstart); /* private */ - -/* ------------------------------------------------------------------------ */ -/* xc_libelf_relocate.c */ - -int elf_reloc(struct elf_binary *elf); - -/* ------------------------------------------------------------------------ */ -/* xc_libelf_dominfo.c */ - -#define UNSET_ADDR ((uint64_t)-1) - -enum xen_elfnote_type { - XEN_ENT_NONE = 0, - XEN_ENT_LONG = 1, - XEN_ENT_STR = 2 -}; - -struct xen_elfnote { - enum xen_elfnote_type type; - const char *name; - union { - const char *str; - uint64_t num; - } data; -}; - -struct elf_dom_parms { - /* raw */ - const char *guest_info; - const void *elf_note_start; - const void *elf_note_end; - struct xen_elfnote elf_notes[XEN_ELFNOTE_MAX + 1]; - - /* parsed */ - char guest_os[16]; - char guest_ver[16]; - char xen_ver[16]; - char loader[16]; - int pae; - int bsd_symtab; - uint64_t virt_base; - uint64_t virt_entry; - uint64_t virt_hypercall; - uint64_t virt_hv_start_low; - uint64_t elf_paddr_offset; - uint32_t f_supported[XENFEAT_NR_SUBMAPS]; - uint32_t f_required[XENFEAT_NR_SUBMAPS]; - - /* calculated */ - uint64_t virt_offset; - uint64_t virt_kstart; - uint64_t virt_kend; -}; - -static inline void elf_xen_feature_set(int nr, uint32_t * addr) -{ - addr[nr >> 5] |= 1 << (nr & 31); -} -static inline int elf_xen_feature_get(int nr, uint32_t * addr) -{ - return !!(addr[nr >> 5] & (1 << (nr & 31))); -} - -int elf_xen_parse_features(const char *features, - uint32_t *supported, - uint32_t *required); -int elf_xen_parse_note(struct elf_binary *elf, - struct elf_dom_parms *parms, - const elf_note *note); -int elf_xen_parse_guest_info(struct elf_binary *elf, - struct elf_dom_parms *parms); -int elf_xen_parse(struct elf_binary *elf, - struct elf_dom_parms *parms); - -#endif /* __XC_LIBELF__ */ diff --git a/sys/xen/interface/mem_event.h b/sys/xen/interface/mem_event.h deleted file mode 100644 index 5d0bd4c838d..00000000000 --- a/sys/xen/interface/mem_event.h +++ /dev/null @@ -1,80 +0,0 @@ -/****************************************************************************** - * mem_event.h - * - * Memory event common structures. - * - * Copyright (c) 2009 by Citrix Systems, Inc. (Patrick Colp) - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to - * deal in the Software without restriction, including without limitation the - * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef _XEN_PUBLIC_MEM_EVENT_H -#define _XEN_PUBLIC_MEM_EVENT_H - -#include "xen.h" -#include "io/ring.h" - -/* Memory event flags */ -#define MEM_EVENT_FLAG_VCPU_PAUSED (1 << 0) -#define MEM_EVENT_FLAG_DROP_PAGE (1 << 1) -#define MEM_EVENT_FLAG_EVICT_FAIL (1 << 2) -#define MEM_EVENT_FLAG_FOREIGN (1 << 3) -#define MEM_EVENT_FLAG_DUMMY (1 << 4) - -/* Reasons for the memory event request */ -#define MEM_EVENT_REASON_UNKNOWN 0 /* typical reason */ -#define MEM_EVENT_REASON_VIOLATION 1 /* access violation, GFN is address */ -#define MEM_EVENT_REASON_CR0 2 /* CR0 was hit: gfn is CR0 value */ -#define MEM_EVENT_REASON_CR3 3 /* CR3 was hit: gfn is CR3 value */ -#define MEM_EVENT_REASON_CR4 4 /* CR4 was hit: gfn is CR4 value */ -#define MEM_EVENT_REASON_INT3 5 /* int3 was hit: gla/gfn are RIP */ -#define MEM_EVENT_REASON_SINGLESTEP 6 /* single step was invoked: gla/gfn are RIP */ - -typedef struct mem_event_st { - uint32_t flags; - uint32_t vcpu_id; - - uint64_t gfn; - uint64_t offset; - uint64_t gla; /* if gla_valid */ - - uint32_t p2mt; - - uint16_t access_r:1; - uint16_t access_w:1; - uint16_t access_x:1; - uint16_t gla_valid:1; - uint16_t available:12; - - uint16_t reason; -} mem_event_request_t, mem_event_response_t; - -DEFINE_RING_TYPES(mem_event, mem_event_request_t, mem_event_response_t); - -#endif - -/* - * Local variables: - * mode: C - * c-set-style: "BSD" - * c-basic-offset: 4 - * tab-width: 4 - * indent-tabs-mode: nil - * End: - */ diff --git a/tests/etc/rc.d/rc.d.new b/tests/etc/rc.d/rc.d.new deleted file mode 100644 index 2e81dde5d33..00000000000 Binary files a/tests/etc/rc.d/rc.d.new and /dev/null differ diff --git a/tests/sys/geom/class/eli/attach_d_test.sh b/tests/sys/geom/class/eli/attach_d_test.sh deleted file mode 100644 index 9d9e14bba88..00000000000 --- a/tests/sys/geom/class/eli/attach_d_test.sh +++ /dev/null @@ -1,38 +0,0 @@ -#!/bin/sh -# $MidnightBSD$ - -. $(dirname $0)/conf.sh - -base=`basename $0` -sectors=100 -keyfile=`mktemp $base.XXXXXX` || exit 1 -mdconfig -a -t malloc -s `expr $sectors + 1` -u $no || exit 1 - -echo "1..3" - -dd if=/dev/random of=${keyfile} bs=512 count=16 >/dev/null 2>&1 - -geli init -B none -P -K $keyfile md${no} -geli attach -d -p -k $keyfile md${no} -if [ -c /dev/md${no}.eli ]; then - echo "ok 1" -else - echo "not ok 1" -fi -# Be sure it doesn't detach on read. -dd if=/dev/md${no}.eli of=/dev/null 2>/dev/null -sleep 1 -if [ -c /dev/md${no}.eli ]; then - echo "ok 2" -else - echo "not ok 2" -fi -true > /dev/md${no}.eli -sleep 1 -if [ ! -c /dev/md${no}.eli ]; then - echo "ok 3" -else - echo "not ok 3" -fi - -rm -f $keyfile diff --git a/tests/sys/geom/class/eli/configure_b_B_test.sh b/tests/sys/geom/class/eli/configure_b_B_test.sh deleted file mode 100644 index 580a9327a6b..00000000000 --- a/tests/sys/geom/class/eli/configure_b_B_test.sh +++ /dev/null @@ -1,129 +0,0 @@ -#!/bin/sh -# $MidnightBSD$ - -. $(dirname $0)/conf.sh - -base=`basename $0` -sectors=100 -mdconfig -a -t malloc -s `expr $sectors + 1` -u $no || exit 1 - -echo "1..17" - -geli init -B none -P -K /dev/null md${no} -if [ $? -eq 0 ]; then - echo "ok 1" -else - echo "not ok 1" -fi - -geli dump md${no} | egrep 'flags: 0x0$' >/dev/null -if [ $? -eq 0 ]; then - echo "ok 2" -else - echo "not ok 2" -fi - -geli init -B none -b -P -K /dev/null md${no} -if [ $? -eq 0 ]; then - echo "ok 3" -else - echo "not ok 3" -fi - -geli dump md${no} | egrep 'flags: 0x2$' >/dev/null -if [ $? -eq 0 ]; then - echo "ok 4" -else - echo "not ok 4" -fi - -geli configure -B md${no} -if [ $? -eq 0 ]; then - echo "ok 5" -else - echo "not ok 5" -fi - -geli dump md${no} | egrep 'flags: 0x0$' >/dev/null -if [ $? -eq 0 ]; then - echo "ok 6" -else - echo "not ok 6" -fi - -geli configure -b md${no} -if [ $? -eq 0 ]; then - echo "ok 7" -else - echo "not ok 7" -fi - -geli dump md${no} | egrep 'flags: 0x2$' >/dev/null -if [ $? -eq 0 ]; then - echo "ok 8" -else - echo "not ok 8" -fi - -geli attach -p -k /dev/null md${no} -if [ $? -eq 0 ]; then - echo "ok 9" -else - echo "not ok 9" -fi - -geli list md${no}.eli | egrep '^Flags: .*BOOT' >/dev/null -if [ $? -eq 0 ]; then - echo "ok 10" -else - echo "not ok 10" -fi - -geli configure -B md${no} -if [ $? -eq 0 ]; then - echo "ok 11" -else - echo "not ok 11" -fi - -geli list md${no}.eli | egrep '^Flags: .*BOOT' >/dev/null -if [ $? -ne 0 ]; then - echo "ok 12" -else - echo "not ok 12" -fi - -geli dump md${no} | egrep 'flags: 0x0$' >/dev/null -if [ $? -eq 0 ]; then - echo "ok 13" -else - echo "not ok 13" -fi - -geli configure -b md${no} -if [ $? -eq 0 ]; then - echo "ok 14" -else - echo "not ok 14" -fi - -geli list md${no}.eli | egrep '^Flags: .*BOOT' >/dev/null -if [ $? -eq 0 ]; then - echo "ok 15" -else - echo "not ok 15" -fi - -geli dump md${no} | egrep 'flags: 0x2$' >/dev/null -if [ $? -eq 0 ]; then - echo "ok 16" -else - echo "not ok 16" -fi - -geli detach md${no} -if [ $? -eq 0 ]; then - echo "ok 17" -else - echo "not ok 17" -fi diff --git a/tests/sys/geom/class/eli/detach_l_test.sh b/tests/sys/geom/class/eli/detach_l_test.sh deleted file mode 100644 index 35f12a61440..00000000000 --- a/tests/sys/geom/class/eli/detach_l_test.sh +++ /dev/null @@ -1,44 +0,0 @@ -#!/bin/sh -# $MidnightBSD$ - -. $(dirname $0)/conf.sh - -base=`basename $0` -sectors=100 -keyfile=`mktemp $base.XXXXXX` || exit 1 -mdconfig -a -t malloc -s `expr $sectors + 1` -u $no || exit 1 - -echo "1..4" - -dd if=/dev/random of=${keyfile} bs=512 count=16 >/dev/null 2>&1 - -geli init -B none -P -K $keyfile md${no} -geli attach -p -k $keyfile md${no} -if [ -c /dev/md${no}.eli ]; then - echo "ok 1" -else - echo "not ok 1" -fi -# Be sure it doesn't detach before 'detach -l'. -dd if=/dev/md${no}.eli of=/dev/null 2>/dev/null -sleep 1 -if [ -c /dev/md${no}.eli ]; then - echo "ok 2" -else - echo "not ok 2" -fi -geli detach -l md${no} -if [ -c /dev/md${no}.eli ]; then - echo "ok 3" -else - echo "not ok 3" -fi -dd if=/dev/md${no}.eli of=/dev/null 2>/dev/null -sleep 1 -if [ ! -c /dev/md${no}.eli ]; then - echo "ok 4" -else - echo "not ok 4" -fi - -rm -f $keyfile diff --git a/tests/sys/geom/class/eli/init_B_test.sh b/tests/sys/geom/class/eli/init_B_test.sh deleted file mode 100644 index 0a601401fac..00000000000 --- a/tests/sys/geom/class/eli/init_B_test.sh +++ /dev/null @@ -1,104 +0,0 @@ -#!/bin/sh -# $MidnightBSD$ - -. $(dirname $0)/conf.sh - -base=`basename $0` -sectors=100 -keyfile=`mktemp $base.XXXXXX` || exit 1 -backupfile=`mktemp $base.XXXXXX` || exit 1 - -echo "1..13" - -dd if=/dev/random of=${keyfile} bs=512 count=16 >/dev/null 2>&1 - -mdconfig -a -t malloc -s $sectors -u $no || exit 1 - -# -B none -rm -f /var/backups/md${no}.eli -geli init -B none -P -K $keyfile md${no} 2>/dev/null -if [ ! -f /var/backups/md${no}.eli ]; then - echo "ok 1 - -B none" -else - echo "not ok 1 - -B none" -fi - -# no -B -rm -f /var/backups/md${no}.eli -geli init -P -K $keyfile md${no} >/dev/null 2>&1 -if [ -f /var/backups/md${no}.eli ]; then - echo "ok 2 - no -B" -else - echo "not ok 2 - no -B" -fi -geli clear md${no} -geli attach -p -k $keyfile md${no} 2>/dev/null -if [ $? -ne 0 ]; then - echo "ok 3 - no -B" -else - echo "not ok 3 - no -B" -fi -if [ ! -c /dev/md${no}.eli ]; then - echo "ok 4 - no -B" -else - echo "not ok 4 - no -B" -fi -geli restore /var/backups/md${no}.eli md${no} -if [ $? -eq 0 ]; then - echo "ok 5 - no -B" -else - echo "not ok 5 - no -B" -fi -geli attach -p -k $keyfile md${no} 2>/dev/null -if [ $? -eq 0 ]; then - echo "ok 6 - no -B" -else - echo "not ok 6 - no -B" -fi -if [ -c /dev/md${no}.eli ]; then - echo "ok 7 - no -B" -else - echo "not ok 7 - no -B" -fi -geli detach md${no} -rm -f /var/backups/md${no}.eli - -# -B file -rm -f $backupfile -geli init -B $backupfile -P -K $keyfile md${no} >/dev/null 2>&1 -if [ -f $backupfile ]; then - echo "ok 8 - -B file" -else - echo "not ok 8 - -B file" -fi -geli clear md${no} -geli attach -p -k $keyfile md${no} 2>/dev/null -if [ $? -ne 0 ]; then - echo "ok 9 - -B file" -else - echo "not ok 9 - -B file" -fi -if [ ! -c /dev/md${no}.eli ]; then - echo "ok 10 - -B file" -else - echo "not ok 10 - -B file" -fi -geli restore $backupfile md${no} -if [ $? -eq 0 ]; then - echo "ok 11 - -B file" -else - echo "not ok 11 - -B file" -fi -geli attach -p -k $keyfile md${no} 2>/dev/null -if [ $? -eq 0 ]; then - echo "ok 12 - -B file" -else - echo "not ok 12 - -B file" -fi -if [ -c /dev/md${no}.eli ]; then - echo "ok 13 - -B file" -else - echo "not ok 13 - -B file" -fi - -rm -f $backupfile $keyfile diff --git a/tests/sys/geom/class/eli/init_J_test.sh b/tests/sys/geom/class/eli/init_J_test.sh deleted file mode 100644 index 24c5b61a110..00000000000 --- a/tests/sys/geom/class/eli/init_J_test.sh +++ /dev/null @@ -1,126 +0,0 @@ -#!/bin/sh -# $MidnightBSD$ - -. $(dirname $0)/conf.sh - -base=`basename $0` -sectors=100 -keyfile0=`mktemp $base.XXXXXX` || exit 1 -keyfile1=`mktemp $base.XXXXXX` || exit 1 -passfile0=`mktemp $base.XXXXXX` || exit 1 -passfile1=`mktemp $base.XXXXXX` || exit 1 -mdconfig -a -t malloc -s `expr $sectors + 1` -u $no || exit 1 - -echo "1..150" - -dd if=/dev/random of=${keyfile0} bs=512 count=16 >/dev/null 2>&1 -dd if=/dev/random of=${keyfile1} bs=512 count=16 >/dev/null 2>&1 -dd if=/dev/random bs=512 count=16 2>/dev/null | sha1 > ${passfile0} -dd if=/dev/random bs=512 count=16 2>/dev/null | sha1 > ${passfile1} - -i=1 -for iter in -1 0 64; do - geli init -i ${iter} -B none -J ${passfile0} -P md${no} 2>/dev/null && echo -n "not " - echo "ok ${i}"; i=$((i+1)) - geli init -i ${iter} -B none -J ${passfile0} -P -K ${keyfile0} md${no} 2>/dev/null && echo -n "not " - echo "ok ${i}"; i=$((i+1)) - geli init -i ${iter} -B none -J ${passfile0} -K ${keyfile0} md${no} 2>/dev/null || echo -n "not " - echo "ok ${i}"; i=$((i+1)) - geli attach -k ${keyfile0} -p md${no} 2>/dev/null && echo -n "not " - echo "ok ${i}"; i=$((i+1)) - geli attach -j ${passfile0} md${no} 2>/dev/null && echo -n "not " - echo "ok ${i}"; i=$((i+1)) - geli attach -j ${keyfile0} md${no} 2>/dev/null && echo -n "not " - echo "ok ${i}"; i=$((i+1)) - geli attach -k ${passfile0} -p md${no} 2>/dev/null && echo -n "not " - echo "ok ${i}"; i=$((i+1)) - geli attach -j ${keyfile0} -k ${passfile0} md${no} 2>/dev/null && echo -n "not " - echo "ok ${i}"; i=$((i+1)) - geli attach -j ${keyfile0} -k ${keyfile0} md${no} 2>/dev/null && echo -n "not " - echo "ok ${i}"; i=$((i+1)) - geli attach -j ${passfile0} -k ${passfile0} md${no} 2>/dev/null && echo -n "not " - echo "ok ${i}"; i=$((i+1)) - geli attach -j ${passfile0} -k ${keyfile0} md${no} 2>/dev/null || echo -n "not " - echo "ok ${i}"; i=$((i+1)) - geli detach md${no} || echo -n "not " - echo "ok ${i}"; i=$((i+1)) - cat ${keyfile0} | geli attach -j ${passfile0} -k - md${no} 2>/dev/null || echo -n "not " - echo "ok ${i}"; i=$((i+1)) - geli detach md${no} || echo -n "not " - echo "ok ${i}"; i=$((i+1)) - cat ${passfile0} | geli attach -j - -k ${keyfile0} md${no} 2>/dev/null || echo -n "not " - echo "ok ${i}"; i=$((i+1)) - geli detach md${no} || echo -n "not " - echo "ok ${i}"; i=$((i+1)) - - geli init -i ${iter} -B none -J ${passfile0} -J ${passfile1} -P md${no} 2>/dev/null && echo -n "not " - echo "ok ${i}"; i=$((i+1)) - geli init -i ${iter} -B none -J ${passfile0} -J ${passfile1} -P -K ${keyfile0} -K ${keyfile1} md${no} 2>/dev/null && echo -n "not " - echo "ok ${i}"; i=$((i+1)) - geli init -i ${iter} -B none -J ${passfile0} -J ${passfile1} -K ${keyfile0} -K ${keyfile1} md${no} 2>/dev/null || echo -n "not " - echo "ok ${i}"; i=$((i+1)) - geli attach -k ${keyfile0} -p md${no} 2>/dev/null && echo -n "not " - echo "ok ${i}"; i=$((i+1)) - geli attach -k ${keyfile1} -p md${no} 2>/dev/null && echo -n "not " - echo "ok ${i}"; i=$((i+1)) - geli attach -j ${passfile0} md${no} 2>/dev/null && echo -n "not " - echo "ok ${i}"; i=$((i+1)) - geli attach -j ${passfile1} md${no} 2>/dev/null && echo -n "not " - echo "ok ${i}"; i=$((i+1)) - geli attach -k ${keyfile0} -k ${keyfile1} -p md${no} 2>/dev/null && echo -n "not " - echo "ok ${i}"; i=$((i+1)) - geli attach -j ${passfile0} -j ${passfile1} md${no} 2>/dev/null && echo -n "not " - echo "ok ${i}"; i=$((i+1)) - geli attach -k ${keyfile0} -j ${passfile0} md${no} 2>/dev/null && echo -n "not " - echo "ok ${i}"; i=$((i+1)) - geli attach -k ${keyfile0} -j ${passfile1} md${no} 2>/dev/null && echo -n "not " - echo "ok ${i}"; i=$((i+1)) - geli attach -k ${keyfile1} -j ${passfile0} md${no} 2>/dev/null && echo -n "not " - echo "ok ${i}"; i=$((i+1)) - geli attach -k ${keyfile1} -j ${passfile1} md${no} 2>/dev/null && echo -n "not " - echo "ok ${i}"; i=$((i+1)) - geli attach -k ${keyfile0} -j ${passfile0} -j ${passfile1} md${no} 2>/dev/null && echo -n "not " - echo "ok ${i}"; i=$((i+1)) - geli attach -k ${keyfile1} -j ${passfile0} -j ${passfile1} md${no} 2>/dev/null && echo -n "not " - echo "ok ${i}"; i=$((i+1)) - geli attach -k ${keyfile0} -k ${keyfile1} -j ${passfile0} md${no} 2>/dev/null && echo -n "not " - echo "ok ${i}"; i=$((i+1)) - geli attach -k ${keyfile0} -k ${keyfile1} -j ${passfile1} md${no} 2>/dev/null && echo -n "not " - echo "ok ${i}"; i=$((i+1)) - geli attach -k ${keyfile1} -k ${keyfile0} -j ${passfile0} -j ${passfile1} md${no} 2>/dev/null && echo -n "not " - echo "ok ${i}"; i=$((i+1)) - geli attach -k ${keyfile0} -k ${keyfile1} -j ${passfile1} -j ${passfile0} md${no} 2>/dev/null && echo -n "not " - echo "ok ${i}"; i=$((i+1)) - geli attach -k ${keyfile1} -k ${keyfile0} -j ${passfile1} -j ${passfile0} md${no} 2>/dev/null && echo -n "not " - echo "ok ${i}"; i=$((i+1)) - geli attach -j ${passfile0} -j ${passfile1} -k ${keyfile0} -k ${keyfile1} md${no} 2>/dev/null || echo -n "not " - echo "ok ${i}"; i=$((i+1)) - geli detach md${no} || echo -n "not " - echo "ok ${i}"; i=$((i+1)) - cat ${passfile0} | geli attach -j - -j ${passfile1} -k ${keyfile0} -k ${keyfile1} md${no} 2>/dev/null || echo -n "not " - echo "ok ${i}"; i=$((i+1)) - geli detach md${no} || echo -n "not " - echo "ok ${i}"; i=$((i+1)) - cat ${passfile1} | geli attach -j ${passfile0} -j - -k ${keyfile0} -k ${keyfile1} md${no} 2>/dev/null || echo -n "not " - echo "ok ${i}"; i=$((i+1)) - geli detach md${no} || echo -n "not " - echo "ok ${i}"; i=$((i+1)) - cat ${keyfile0} | geli attach -j ${passfile0} -j ${passfile1} -k - -k ${keyfile1} md${no} 2>/dev/null || echo -n "not " - echo "ok ${i}"; i=$((i+1)) - geli detach md${no} || echo -n "not " - echo "ok ${i}"; i=$((i+1)) - cat ${keyfile1} | geli attach -j ${passfile0} -j ${passfile1} -k ${keyfile0} -k - md${no} 2>/dev/null || echo -n "not " - echo "ok ${i}"; i=$((i+1)) - geli detach md${no} || echo -n "not " - echo "ok ${i}"; i=$((i+1)) - cat ${keyfile0} ${keyfile1} | geli attach -j ${passfile0} -j ${passfile1} -k - md${no} 2>/dev/null || echo -n "not " - echo "ok ${i}"; i=$((i+1)) - geli detach md${no} || echo -n "not " - echo "ok ${i}"; i=$((i+1)) - cat ${passfile0} ${passfile1} | awk '{printf "%s", $0}' | geli attach -j - -k ${keyfile0} -k ${keyfile1} md${no} 2>/dev/null || echo -n "not " - echo "ok ${i}"; i=$((i+1)) - geli detach md${no} || echo -n "not " - echo "ok ${i}"; i=$((i+1)) -done - -rm -f ${keyfile0} ${keyfile1} ${passfile0} ${passfile1} diff --git a/tests/sys/geom/class/eli/init_a_test.sh b/tests/sys/geom/class/eli/init_a_test.sh deleted file mode 100644 index 5d771acc9e4..00000000000 --- a/tests/sys/geom/class/eli/init_a_test.sh +++ /dev/null @@ -1,50 +0,0 @@ -#!/bin/sh -# $MidnightBSD$ - -. $(dirname $0)/conf.sh - -base=`basename $0` -sectors=100 -keyfile=`mktemp $base.XXXXXX` || exit 1 -rnd=`mktemp $base.XXXXXX` || exit 1 - -do_test() { - cipher=$1 - aalgo=$2 - secsize=$3 - ealgo=${cipher%%:*} - keylen=${cipher##*:} - - mdconfig -a -t malloc -s `expr $secsize \* $sectors + 512`b -u $no || exit 1 - geli init -B none -a $aalgo -e $ealgo -l $keylen -P -K $keyfile -s $secsize md${no} 2>/dev/null - geli attach -p -k $keyfile md${no} - - secs=`diskinfo /dev/md${no}.eli | awk '{print $4}'` - - dd if=${rnd} of=/dev/md${no}.eli bs=${secsize} count=${secs} 2>/dev/null - - md_rnd=`dd if=${rnd} bs=${secsize} count=${secs} 2>/dev/null | md5` - md_ddev=`dd if=/dev/md${no}.eli bs=${secsize} count=${secs} 2>/dev/null | md5` - - if [ ${md_rnd} = ${md_ddev} ]; then - echo "ok $i - aalgo=${aalgo} ealgo=${ealgo} keylen=${keylen} sec=${secsize}" - else - echo "not ok $i - aalgo=${aalgo} ealgo=${ealgo} keylen=${keylen} sec=${secsize}" - fi - i=$((i+1)) - - geli detach md${no} - mdconfig -d -u $no -} - -echo "1..600" - -i=1 - -dd if=/dev/random of=${keyfile} bs=512 count=16 >/dev/null 2>&1 -dd if=/dev/random of=${rnd} bs=8192 count=${sectors} >/dev/null 2>&1 - -for_each_geli_config do_test - -rm -f $rnd -rm -f $keyfile diff --git a/tests/sys/geom/class/eli/init_alias_test.sh b/tests/sys/geom/class/eli/init_alias_test.sh deleted file mode 100644 index 64af6a7f3a2..00000000000 --- a/tests/sys/geom/class/eli/init_alias_test.sh +++ /dev/null @@ -1,64 +0,0 @@ -#!/bin/sh -# $MidnightBSD$ - -# Test "geli init"'s various cipher aliases -. $(dirname $0)/conf.sh - -base=`basename $0` -sectors=100 -keyfile=`mktemp $base.XXXXXX` || exit 1 -rnd=`mktemp $base.XXXXXX` || exit 1 - -do_test() { - ealgo=$1 - keylen=$2 - expected_ealgo=$3 - expected_keylen=$4 - - geli init -B none -e $ealgo -l $keylen -P -K $keyfile md${no} 2>/dev/null - geli attach -p -k $keyfile md${no} - real_ealgo=`geli list md${no}.eli | awk '/EncryptionAlgorithm/ {print $2}'` - real_keylen=`geli list md${no}.eli | awk '/KeyLength/ {print $2}'` - - if [ ${real_ealgo} = ${expected_ealgo} ]; then - echo "ok $i - ${ealgo} aliased to ${real_ealgo}" - else - echo "not ok $i - expected ${expected_ealgo} but got ${real_ealgo}" - fi - i=$((i+1)) - - if [ ${real_keylen} = ${expected_keylen} ]; then - echo "ok $i - keylen=${keylen} for ealgo=${ealgo} aliases to ${real_keylen}" - else - echo "not ok $i - expected ${expected_keylen} but got ${real_keylen}" - fi - i=$((i+1)) - - geli detach md${no} -} - -echo "1..38" -i=1 -mdconfig -a -t malloc -s 1024k -u $no || exit 1 -dd if=/dev/random of=${keyfile} bs=512 count=16 >/dev/null 2>&1 - -for spec in aes:0:AES-XTS:128 aes:128:AES-XTS:128 aes:256:AES-XTS:256 \ - 3des:0:3DES-CBC:192 3des:192:3DES-CBC:192 \ - blowfish:0:Blowfish-CBC:128 blowfish:128:Blowfish-CBC:128 \ - blowfish:160:Blowfish-CBC:160 blowfish:192:Blowfish-CBC:192 \ - blowfish:224:Blowfish-CBC:224 blowfish:256:Blowfish-CBC:256 \ - blowfish:288:Blowfish-CBC:288 blowfish:352:Blowfish-CBC:352 \ - blowfish:384:Blowfish-CBC:384 blowfish:416:Blowfish-CBC:416 \ - blowfish:448:Blowfish-CBC:448 \ - camellia:0:CAMELLIA-CBC:128 camellia:128:CAMELLIA-CBC:128 \ - camellia:256:CAMELLIA-CBC:256 ; do - - ealgo=`echo $spec | cut -d : -f 1` - keylen=`echo $spec | cut -d : -f 2` - expected_ealgo=`echo $spec | cut -d : -f 3` - expected_keylen=`echo $spec | cut -d : -f 4` - - do_test $ealgo $keylen $expected_ealgo $expected_keylen -done - -rm -f $keyfile diff --git a/tests/sys/geom/class/eli/init_i_P_test.sh b/tests/sys/geom/class/eli/init_i_P_test.sh deleted file mode 100644 index a2da42a413c..00000000000 --- a/tests/sys/geom/class/eli/init_i_P_test.sh +++ /dev/null @@ -1,22 +0,0 @@ -#!/bin/sh -# $MidnightBSD$ - -. $(dirname $0)/conf.sh - -base=`basename $0` -sectors=100 -keyfile=`mktemp $base.XXXXXX` || exit 1 -mdconfig -a -t malloc -s `expr $sectors + 1` -u $no || exit 1 - -echo "1..1" - -dd if=/dev/random of=${keyfile} bs=512 count=16 >/dev/null 2>&1 - -geli init -B none -i 64 -P -K ${keyfile} md${no} 2>/dev/null -if [ $? -ne 0 ]; then - echo "ok 1" -else - echo "not ok 1" -fi - -rm -f $keyfile diff --git a/tests/sys/geom/class/eli/integrity_copy_test.sh b/tests/sys/geom/class/eli/integrity_copy_test.sh deleted file mode 100644 index a526ac81b54..00000000000 --- a/tests/sys/geom/class/eli/integrity_copy_test.sh +++ /dev/null @@ -1,88 +0,0 @@ -#!/bin/sh -# $MidnightBSD$ - -. $(dirname $0)/conf.sh - -base=`basename $0` -keyfile=`mktemp $base.XXXXXX` || exit 1 -sector=`mktemp $base.XXXXXX` || exit 1 - -echo "1..2400" - -do_test() { - cipher=$1 - aalgo=$2 - secsize=$3 - ealgo=${cipher%%:*} - keylen=${cipher##*:} - - mdconfig -a -t malloc -s `expr $secsize \* 2 + 512`b -u $no || exit 1 - geli init -B none -a $aalgo -e $ealgo -l $keylen -P -K $keyfile -s $secsize md${no} 2>/dev/null - geli attach -p -k $keyfile md${no} - - dd if=/dev/random of=/dev/md${no}.eli bs=${secsize} count=1 >/dev/null 2>&1 - - dd if=/dev/md${no}.eli bs=${secsize} count=1 >/dev/null 2>&1 - if [ $? -eq 0 ]; then - echo "ok $i - small 1 aalgo=${aalgo} ealgo=${ealgo} keylen=${keylen} sec=${secsize}" - else - echo "not ok $i - small 1 aalgo=${aalgo} ealgo=${ealgo} keylen=${keylen} sec=${secsize}" - fi - i=$((i+1)) - - geli detach md${no} - # Copy first small sector to the second small sector. - # This should be detected as corruption. - dd if=/dev/md${no} of=${sector} bs=512 count=1 >/dev/null 2>&1 - dd if=${sector} of=/dev/md${no} bs=512 count=1 seek=1 >/dev/null 2>&1 - geli attach -p -k $keyfile md${no} - - dd if=/dev/md${no}.eli of=/dev/null bs=${secsize} count=1 >/dev/null 2>&1 - if [ $? -ne 0 ]; then - echo "ok $i - small 2 aalgo=${aalgo} ealgo=${ealgo} keylen=${keylen} sec=${secsize}" - else - echo "not ok $i - small 2 aalgo=${aalgo} ealgo=${ealgo} keylen=${keylen} sec=${secsize}" - fi - i=$((i+1)) - - ms=`diskinfo /dev/md${no} | awk '{print $3 - 512}'` - ns=`diskinfo /dev/md${no}.eli | awk '{print $4}'` - usecsize=`echo "($ms / $ns) - (($ms / $ns) % 512)" | bc` - - # Fix the corruption - dd if=/dev/random of=/dev/md${no}.eli bs=${secsize} count=2 >/dev/null 2>&1 - - dd if=/dev/md${no}.eli bs=${secsize} count=2 >/dev/null 2>&1 - if [ $? -eq 0 ]; then - echo "ok $i - big 1 aalgo=${aalgo} ealgo=${ealgo} keylen=${keylen} sec=${secsize}" - else - echo "not ok $i - big 1 aalgo=${aalgo} ealgo=${ealgo} keylen=${keylen} sec=${secsize}" - fi - i=$((i+1)) - - geli detach md${no} - # Copy first big sector to the second big sector. - # This should be detected as corruption. - dd if=/dev/md${no} of=${sector} bs=${usecsize} count=1 >/dev/null 2>&1 - dd if=${sector} of=/dev/md${no} bs=${usecsize} count=1 seek=1 >/dev/null 2>&1 - geli attach -p -k $keyfile md${no} - - dd if=/dev/md${no}.eli of=/dev/null bs=${secsize} count=2 >/dev/null 2>&1 - if [ $? -ne 0 ]; then - echo "ok $i - big 2 aalgo=${aalgo} ealgo=${ealgo} keylen=${keylen} sec=${secsize}" - else - echo "not ok $i - big 2 aalgo=${aalgo} ealgo=${ealgo} keylen=${keylen} sec=${secsize}" - fi - i=$((i+1)) - - geli detach md${no} - mdconfig -d -u $no -} - - -i=1 -dd if=/dev/random of=${keyfile} bs=512 count=16 >/dev/null 2>&1 - -for_each_geli_config do_test - -rm -f $keyfile $sector diff --git a/tests/sys/geom/class/eli/integrity_data_test.sh b/tests/sys/geom/class/eli/integrity_data_test.sh deleted file mode 100644 index c324befa051..00000000000 --- a/tests/sys/geom/class/eli/integrity_data_test.sh +++ /dev/null @@ -1,45 +0,0 @@ -#!/bin/sh -# $MidnightBSD$ - -. $(dirname $0)/conf.sh - -base=`basename $0` -keyfile=`mktemp $base.XXXXXX` || exit 1 -sector=`mktemp $base.XXXXXX` || exit 1 - -echo "1..600" - -do_test() { - cipher=$1 - aalgo=$2 - secsize=$3 - ealgo=${cipher%%:*} - keylen=${cipher##*:} - - mdconfig -a -t malloc -s `expr $secsize \* 2 + 512`b -u $no || exit 1 - geli init -B none -a $aalgo -e $ealgo -l $keylen -P -K $keyfile -s $secsize md${no} 2>/dev/null - - # Corrupt 8 bytes of data. - dd if=/dev/md${no} of=${sector} bs=512 count=1 >/dev/null 2>&1 - dd if=/dev/random of=${sector} bs=1 count=8 seek=64 conv=notrunc >/dev/null 2>&1 - dd if=${sector} of=/dev/md${no} bs=512 count=1 >/dev/null 2>&1 - geli attach -p -k $keyfile md${no} - - dd if=/dev/md${no}.eli of=/dev/null bs=${secsize} count=1 >/dev/null 2>&1 - if [ $? -ne 0 ]; then - echo "ok $i - aalgo=${aalgo} ealgo=${ealgo} keylen=${keylen} sec=${secsize}" - else - echo "not ok $i - aalgo=${aalgo} ealgo=${ealgo} keylen=${keylen} sec=${secsize}" - fi - i=$((i+1)) - - geli detach md${no} - mdconfig -d -u $no -} - -i=1 -dd if=/dev/random of=${keyfile} bs=512 count=16 >/dev/null 2>&1 - -for_each_geli_config do_test - -rm -f $keyfile $sector diff --git a/tests/sys/geom/class/eli/integrity_hmac_test.sh b/tests/sys/geom/class/eli/integrity_hmac_test.sh deleted file mode 100644 index 73cbee0977a..00000000000 --- a/tests/sys/geom/class/eli/integrity_hmac_test.sh +++ /dev/null @@ -1,46 +0,0 @@ -#!/bin/sh -# $MidnightBSD$ - -. $(dirname $0)/conf.sh - -base=`basename $0` -keyfile=`mktemp $base.XXXXXX` || exit 1 -sector=`mktemp $base.XXXXXX` || exit 1 - -echo "1..600" - -do_test() { - cipher=$1 - aalgo=$2 - secsize=$3 - ealgo=${cipher%%:*} - keylen=${cipher##*:} - - mdconfig -a -t malloc -s `expr $secsize \* 2 + 512`b -u $no || exit 2 - geli init -B none -a $aalgo -e $ealgo -l $keylen -P -K $keyfile -s $secsize md${no} 2>/dev/null - - # Corrupt 8 bytes of HMAC. - dd if=/dev/md${no} of=${sector} bs=512 count=1 >/dev/null 2>&1 - dd if=/dev/random of=${sector} bs=1 count=16 conv=notrunc >/dev/null 2>&1 - dd if=${sector} of=/dev/md${no} bs=512 count=1 >/dev/null 2>&1 - geli attach -p -k $keyfile md${no} - - dd if=/dev/md${no}.eli bs=${secsize} count=1 >/dev/null 2>&1 - if [ $? -ne 0 ]; then - echo "ok $i - aalgo=${aalgo} ealgo=${ealgo} keylen=${keylen} sec=${secsize}" - else - echo "not ok $i - aalgo=${aalgo} ealgo=${ealgo} keylen=${keylen} sec=${secsize}" - fi - i=$((i+1)) - - geli detach md${no} - mdconfig -d -u $no -} - - -i=1 -dd if=/dev/random of=${keyfile} bs=512 count=16 >/dev/null 2>&1 - -for_each_geli_config do_test - -rm -f $keyfile $sector diff --git a/tests/sys/geom/class/eli/nokey_test.sh b/tests/sys/geom/class/eli/nokey_test.sh deleted file mode 100644 index 5f797cda817..00000000000 --- a/tests/sys/geom/class/eli/nokey_test.sh +++ /dev/null @@ -1,65 +0,0 @@ -#!/bin/sh -# $MidnightBSD$ - -. $(dirname $0)/conf.sh - -base=`basename $0` -sectors=100 -keyfile=`mktemp $base.XXXXXX` || exit 1 -mdconfig -a -t malloc -s `expr $sectors + 1` -u $no || exit 1 - -echo "1..8" - -geli init -B none -P md${no} 2>/dev/null -if [ $? -ne 0 ]; then - echo "ok 1" -else - echo "not ok 1" -fi - -dd if=/dev/random of=${keyfile} bs=512 count=16 >/dev/null 2>&1 - -geli init -B none -P -K ${keyfile} md${no} 2>/dev/null -if [ $? -eq 0 ]; then - echo "ok 2" -else - echo "not ok 2" -fi -geli attach -p md${no} 2>/dev/null -if [ $? -ne 0 ]; then - echo "ok 3" -else - echo "not ok 3" -fi -geli attach -p -k ${keyfile} md${no} 2>/dev/null -if [ $? -eq 0 ]; then - echo "ok 4" -else - echo "not ok 4" -fi -geli setkey -n 0 -P md${no} 2>/dev/null -if [ $? -ne 0 ]; then - echo "ok 5" -else - echo "not ok 5" -fi -geli detach md${no} 2>/dev/null -if [ $? -eq 0 ]; then - echo "ok 6" -else - echo "not ok 6" -fi -geli setkey -n 0 -p -P -K ${keyfile} md${no} 2>/dev/null -if [ $? -ne 0 ]; then - echo "ok 7" -else - echo "not ok 7" -fi -geli setkey -n 0 -p -k ${keyfile} -P md${no} 2>/dev/null -if [ $? -ne 0 ]; then - echo "ok 8" -else - echo "not ok 8" -fi - -rm -f $keyfile diff --git a/tests/sys/geom/class/eli/onetime_a_test.sh b/tests/sys/geom/class/eli/onetime_a_test.sh deleted file mode 100644 index 19ebc678997..00000000000 --- a/tests/sys/geom/class/eli/onetime_a_test.sh +++ /dev/null @@ -1,45 +0,0 @@ -#!/bin/sh -# $MidnightBSD$ - -. $(dirname $0)/conf.sh - -base=`basename $0` -sectors=8 -rnd=`mktemp $base.XXXXXX` || exit 1 - -echo "1..600" - -do_test() { - cipher=$1 - aalgo=$2 - secsize=$3 - ealgo=${cipher%%:*} - keylen=${cipher##*:} - - mdconfig -a -t malloc -s `expr $secsize \* $sectors + 512`b -u $no || exit 1 - geli onetime -a $aalgo -e $ealgo -l $keylen -s $secsize md${no} 2>/dev/null - - secs=`diskinfo /dev/md${no}.eli | awk '{print $4}'` - - dd if=${rnd} of=/dev/md${no}.eli bs=${secsize} count=${secs} 2>/dev/null - - md_rnd=`dd if=${rnd} bs=${secsize} count=${secs} 2>/dev/null | md5` - md_ddev=`dd if=/dev/md${no}.eli bs=${secsize} count=${secs} 2>/dev/null | md5` - - if [ ${md_rnd} = ${md_ddev} ]; then - echo "ok $i - aalgo=${aalgo} ealgo=${ealgo} keylen=${keylen} sec=${secsize}" - else - echo "not ok $i - aalgo=${aalgo} ealgo=${ealgo} keylen=${keylen} sec=${secsize}" - fi - i=$((i+1)) - - geli detach md${no} - mdconfig -d -u $no -} - -i=1 -dd if=/dev/random of=${rnd} bs=1024 count=1024 >/dev/null 2>&1 - -for_each_geli_config do_test - -rm -f $rnd diff --git a/tests/sys/geom/class/eli/onetime_d_test.sh b/tests/sys/geom/class/eli/onetime_d_test.sh deleted file mode 100644 index 0151167fc89..00000000000 --- a/tests/sys/geom/class/eli/onetime_d_test.sh +++ /dev/null @@ -1,34 +0,0 @@ -#!/bin/sh -# $MidnightBSD$ - -. $(dirname $0)/conf.sh - -base=`basename $0` -sectors=100 -mdconfig -a -t malloc -s $sectors -u $no || exit 1 - -echo "1..3" - -geli onetime -d md${no} -if [ -c /dev/md${no}.eli ]; then - echo "ok 1" -else - echo "not ok 1" -fi -# Be sure it doesn't detach on read. -dd if=/dev/md${no}.eli of=/dev/null 2>/dev/null -sleep 1 -if [ -c /dev/md${no}.eli ]; then - echo "ok 2" -else - echo "not ok 2" -fi -true > /dev/md${no}.eli -sleep 1 -if [ ! -c /dev/md${no}.eli ]; then - echo "ok 3" -else - echo "not ok 3" -fi - -mdconfig -d -u $no diff --git a/tests/sys/geom/class/eli/readonly_test.sh b/tests/sys/geom/class/eli/readonly_test.sh deleted file mode 100644 index e9c4ed5ca7a..00000000000 --- a/tests/sys/geom/class/eli/readonly_test.sh +++ /dev/null @@ -1,94 +0,0 @@ -#!/bin/sh -# $MidnightBSD$ - -. $(dirname $0)/conf.sh - -base=`basename $0` -sectors=100 -keyfile=`mktemp $base.XXXXXX` || exit 1 -mdconfig -a -t malloc -s `expr $sectors + 1` -u $no || exit 1 - -echo "1..11" - -dd if=/dev/random of=${keyfile} bs=512 count=16 >/dev/null 2>&1 - -geli init -B none -P -K $keyfile md${no} -if [ $? -eq 0 ]; then - echo "ok 1" -else - echo "not ok 1" -fi - -geli attach -r -p -k $keyfile md${no} -if [ $? -eq 0 ]; then - echo "ok 2" -else - echo "not ok 2" -fi - -sh -c "true >/dev/md${no}.eli" 2>/dev/null -if [ $? -ne 0 ]; then - echo "ok 3" -else - echo "not ok 3" -fi - -geli kill md${no} -if [ $? -eq 0 ]; then - echo "ok 4" -else - echo "not ok 4" -fi - -# kill should detach provider... -if [ ! -c /dev/md{$no}.eli ]; then - echo "ok 5" -else - echo "not ok 5" -fi - -# ...but not destroy the metadata. -geli attach -r -p -k $keyfile md${no} -if [ $? -eq 0 ]; then - echo "ok 6" -else - echo "not ok 6" -fi - -geli setkey -n 1 -P -K /dev/null md${no} 2>/dev/null -if [ $? -ne 0 ]; then - echo "ok 7" -else - echo "not ok 7" -fi - -geli delkey -n 0 md${no} 2>/dev/null -if [ $? -ne 0 ]; then - echo "ok 8" -else - echo "not ok 8" -fi - -geli delkey -f -n 0 md${no} 2>/dev/null -if [ $? -ne 0 ]; then - echo "ok 9" -else - echo "not ok 9" -fi - -geli list md${no}.eli | egrep '^Flags: .*READ-ONLY' >/dev/null -if [ $? -eq 0 ]; then - echo "ok 10" -else - echo "not ok 10" -fi - -geli detach md${no} -if [ $? -eq 0 ]; then - echo "ok 11" -else - echo "not ok 11" -fi - -mdconfig -d -u $no -rm -f $keyfile diff --git a/tests/sys/kqueue/libkqueue/kqueue_test.sh b/tests/sys/kqueue/libkqueue/kqueue_test.sh deleted file mode 100644 index 3185d826c7d..00000000000 --- a/tests/sys/kqueue/libkqueue/kqueue_test.sh +++ /dev/null @@ -1,17 +0,0 @@ -#!/bin/sh -# $FreeBSD$ - -i=1 -"$(dirname $0)/kqtest" | while read line; do - echo $line | grep -q passed - if [ $? -eq 0 ]; then - echo "ok - $i $line" - : $(( i += 1 )) - fi - - echo $line | grep -q 'tests completed' - if [ $? -eq 0 ]; then - echo -n "1.." - echo $line | cut -d' ' -f3 - fi -done diff --git a/tests/sys/kqueue/main.c b/tests/sys/kqueue/main.c deleted file mode 100644 index 31a95e6b11b..00000000000 --- a/tests/sys/kqueue/main.c +++ /dev/null @@ -1,324 +0,0 @@ -/* $MidnightBSD$ */ -/* - * Copyright (c) 2009 Mark Heily - * - * Permission to use, copy, modify, and distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - * $FreeBSD: stable/10/tests/sys/kqueue/main.c 297977 2016-04-14 17:14:11Z vangyzen $ - */ - -#include - -#include "config.h" -#include "common.h" - -int testnum = 1; -char *cur_test_id = NULL; -int kqfd; - -extern void test_evfilt_read(); -extern void test_evfilt_signal(); -extern void test_evfilt_vnode(); -extern void test_evfilt_timer(); -extern void test_evfilt_proc(); -#if HAVE_EVFILT_USER -extern void test_evfilt_user(); -#endif - -/* Checks if any events are pending, which is an error. */ -void -test_no_kevents(void) -{ - int nfds; - struct timespec timeo; - struct kevent kev; - - puts("confirming that there are no events pending"); - memset(&timeo, 0, sizeof(timeo)); - nfds = kevent(kqfd, NULL, 0, &kev, 1, &timeo); - if (nfds != 0) { - puts("\nUnexpected event:"); - puts(kevent_to_str(&kev)); - errx(1, "%d event(s) pending, but none expected:", nfds); - } -} - -/* Retrieve a single kevent */ -struct kevent * -kevent_get(int kqfd) -{ - int nfds; - struct kevent *kev; - - if ((kev = calloc(1, sizeof(*kev))) == NULL) - err(1, "out of memory"); - - nfds = kevent(kqfd, NULL, 0, kev, 1, NULL); - if (nfds < 1) - err(1, "kevent(2)"); - - return (kev); -} - -/* Retrieve a single kevent, specifying a maximum time to wait for it. */ -struct kevent * -kevent_get_timeout(int kqfd, int seconds) -{ - int nfds; - struct kevent *kev; - struct timespec timeout = {seconds, 0}; - - if ((kev = calloc(1, sizeof(*kev))) == NULL) - err(1, "out of memory"); - - nfds = kevent(kqfd, NULL, 0, kev, 1, &timeout); - if (nfds < 0) { - err(1, "kevent(2)"); - } else if (nfds == 0) { - free(kev); - kev = NULL; - } - - return (kev); -} - -char * -kevent_fflags_dump(struct kevent *kev) -{ - char *buf; - -#define KEVFFL_DUMP(attrib) \ - if (kev->fflags & attrib) \ - strncat(buf, #attrib" ", 64); - - if ((buf = calloc(1, 1024)) == NULL) - abort(); - - /* Not every filter has meaningful fflags */ - if (kev->filter == EVFILT_PROC) { - snprintf(buf, 1024, "fflags = %x (", kev->fflags); - KEVFFL_DUMP(NOTE_EXIT); - KEVFFL_DUMP(NOTE_FORK); - KEVFFL_DUMP(NOTE_EXEC); - KEVFFL_DUMP(NOTE_CHILD); - KEVFFL_DUMP(NOTE_TRACKERR); - KEVFFL_DUMP(NOTE_TRACK); - buf[strlen(buf) - 1] = ')'; - } else if (kev->filter == EVFILT_VNODE) { - snprintf(buf, 1024, "fflags = %x (", kev->fflags); - KEVFFL_DUMP(NOTE_DELETE); - KEVFFL_DUMP(NOTE_WRITE); - KEVFFL_DUMP(NOTE_EXTEND); -#if HAVE_NOTE_TRUNCATE - KEVFFL_DUMP(NOTE_TRUNCATE); -#endif - KEVFFL_DUMP(NOTE_ATTRIB); - KEVFFL_DUMP(NOTE_LINK); - KEVFFL_DUMP(NOTE_RENAME); -#if HAVE_NOTE_REVOKE - KEVFFL_DUMP(NOTE_REVOKE); -#endif - buf[strlen(buf) - 1] = ')'; - } else { - snprintf(buf, 1024, "fflags = %x", kev->fflags); - } - - return (buf); -} - -char * -kevent_flags_dump(struct kevent *kev) -{ - char *buf; - -#define KEVFL_DUMP(attrib) \ - if (kev->flags & attrib) \ - strncat(buf, #attrib" ", 64); - - if ((buf = calloc(1, 1024)) == NULL) - abort(); - - snprintf(buf, 1024, "flags = %d (", kev->flags); - KEVFL_DUMP(EV_ADD); - KEVFL_DUMP(EV_ENABLE); - KEVFL_DUMP(EV_DISABLE); - KEVFL_DUMP(EV_DELETE); - KEVFL_DUMP(EV_ONESHOT); - KEVFL_DUMP(EV_CLEAR); - KEVFL_DUMP(EV_EOF); - KEVFL_DUMP(EV_ERROR); -#if HAVE_EV_DISPATCH - KEVFL_DUMP(EV_DISPATCH); -#endif -#if HAVE_EV_RECEIPT - KEVFL_DUMP(EV_RECEIPT); -#endif - buf[strlen(buf) - 1] = ')'; - - return (buf); -} - -/* Copied from ../kevent.c kevent_dump() and improved */ -const char * -kevent_to_str(struct kevent *kev) -{ - char buf[512]; - - snprintf(&buf[0], sizeof(buf), - "[ident=%d, filter=%d, %s, %s, data=%d, udata=%p]", - (u_int) kev->ident, - kev->filter, - kevent_flags_dump(kev), - kevent_fflags_dump(kev), - (int) kev->data, - kev->udata); - - return (strdup(buf)); -} - -void -kevent_add(int kqfd, struct kevent *kev, - uintptr_t ident, - short filter, - u_short flags, - u_int fflags, - intptr_t data, - void *udata) -{ - EV_SET(kev, ident, filter, flags, fflags, data, NULL); - if (kevent(kqfd, kev, 1, NULL, 0, NULL) < 0) { - printf("Unable to add the following kevent:\n%s\n", - kevent_to_str(kev)); - err(1, "kevent(): %s", strerror(errno)); - } -} - -void -kevent_cmp(struct kevent *k1, struct kevent *k2) -{ -/* XXX- - Workaround for inconsistent implementation of kevent(2) - */ -#ifdef __FreeBSD__ - if (k1->flags & EV_ADD) - k2->flags |= EV_ADD; -#endif - if (memcmp(k1, k2, sizeof(*k1)) != 0) { - printf("kevent_cmp: mismatch:\n %s !=\n %s\n", - kevent_to_str(k1), kevent_to_str(k2)); - abort(); - } -} - -void -test_begin(const char *func) -{ - if (cur_test_id) - free(cur_test_id); - cur_test_id = strdup(func); - if (!cur_test_id) - err(1, "strdup failed"); - - printf("\n\nTest %d: %s\n", testnum++, func); -} - -void -success(void) -{ - printf("%-70s %s\n", cur_test_id, "passed"); - free(cur_test_id); - cur_test_id = NULL; -} - -void -test_kqueue(void) -{ - test_begin("kqueue()"); - if ((kqfd = kqueue()) < 0) - err(1, "kqueue()"); - test_no_kevents(); - success(); -} - -void -test_kqueue_close(void) -{ - test_begin("close(kq)"); - if (close(kqfd) < 0) - err(1, "close()"); - success(); -} - -int -main(int argc, char **argv) -{ - int test_proc = 1; - int test_socket = 1; - int test_signal = 1; - int test_vnode = 1; - int test_timer = 1; -#ifdef __FreeBSD__ - int test_user = 1; -#else - /* XXX-FIXME temporary */ - int test_user = 0; -#endif - - while (argc) { - if (strcmp(argv[0], "--no-proc") == 0) - test_proc = 0; - if (strcmp(argv[0], "--no-socket") == 0) - test_socket = 0; - if (strcmp(argv[0], "--no-timer") == 0) - test_timer = 0; - if (strcmp(argv[0], "--no-signal") == 0) - test_signal = 0; - if (strcmp(argv[0], "--no-vnode") == 0) - test_vnode = 0; - if (strcmp(argv[0], "--no-user") == 0) - test_user = 0; - argv++; - argc--; - } - - /* - * Some tests fork. If output is fully buffered, - * the children inherit some buffered data and flush - * it when they exit, causing some data to be printed twice. - * Use line buffering to avoid this problem. - */ - setlinebuf(stdout); - setlinebuf(stderr); - - test_kqueue(); - test_kqueue_close(); - - if (test_socket) - test_evfilt_read(); - if (test_signal) - test_evfilt_signal(); - if (test_vnode) - test_evfilt_vnode(); -#if HAVE_EVFILT_USER - if (test_user) - test_evfilt_user(); -#endif - if (test_timer) - test_evfilt_timer(); - if (test_proc) - test_evfilt_proc(); - - printf("\n---\n" - "+OK All %d tests completed.\n", testnum - 1); - return (0); -} diff --git a/tests/sys/kqueue/read.c b/tests/sys/kqueue/read.c deleted file mode 100644 index 1ab7d7e65da..00000000000 --- a/tests/sys/kqueue/read.c +++ /dev/null @@ -1,325 +0,0 @@ -/* $MidnightBSD$ */ -/* - * Copyright (c) 2009 Mark Heily - * - * Permission to use, copy, modify, and distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - * $FreeBSD: stable/10/tests/sys/kqueue/read.c 200483 2009-12-13 20:27:46Z rwatson $ - */ - -#include "common.h" - -int kqfd; -int sockfd[2]; - -static void -kevent_socket_drain(void) -{ - char buf[1]; - - /* Drain the read buffer, then make sure there are no more events. */ - puts("draining the read buffer"); - if (read(sockfd[0], &buf[0], 1) < 1) - err(1, "read(2)"); -} - -static void -kevent_socket_fill(void) -{ - puts("filling the read buffer"); - if (write(sockfd[1], ".", 1) < 1) - err(1, "write(2)"); -} - - -void -test_kevent_socket_add(void) -{ - const char *test_id = "kevent(EVFILT_READ, EV_ADD)"; - struct kevent kev; - - test_begin(test_id); - EV_SET(&kev, sockfd[0], EVFILT_READ, EV_ADD, 0, 0, &sockfd[0]); - if (kevent(kqfd, &kev, 1, NULL, 0, NULL) < 0) - err(1, "%s", test_id); - - success(); -} - -void -test_kevent_socket_get(void) -{ - const char *test_id = "kevent(EVFILT_READ) wait"; - struct kevent kev; - - test_begin(test_id); - - EV_SET(&kev, sockfd[0], EVFILT_READ, EV_ADD, 0, 0, &sockfd[0]); - if (kevent(kqfd, &kev, 1, NULL, 0, NULL) < 0) - err(1, "%s", test_id); - - kevent_socket_fill(); - - kev.data = 1; - kevent_cmp(&kev, kevent_get(kqfd)); - - kevent_socket_drain(); - test_no_kevents(); - - kev.flags = EV_DELETE; - if (kevent(kqfd, &kev, 1, NULL, 0, NULL) < 0) - err(1, "%s", test_id); - - success(); -} - -void -test_kevent_socket_clear(void) -{ - const char *test_id = "kevent(EVFILT_READ, EV_CLEAR)"; - struct kevent kev; - - test_begin(test_id); - - test_no_kevents(); - - EV_SET(&kev, sockfd[0], EVFILT_READ, EV_ADD | EV_CLEAR, 0, 0, &sockfd[0]); - if (kevent(kqfd, &kev, 1, NULL, 0, NULL) < 0) - err(1, "%s", test_id); - - kevent_socket_fill(); - kevent_socket_fill(); - - kev.data = 2; - kevent_cmp(&kev, kevent_get(kqfd)); - - /* We filled twice, but drain once. Edge-triggered would not generate - additional events. - */ - kevent_socket_drain(); - test_no_kevents(); - - kevent_socket_drain(); - EV_SET(&kev, sockfd[0], EVFILT_READ, EV_DELETE, 0, 0, &sockfd[0]); - if (kevent(kqfd, &kev, 1, NULL, 0, NULL) < 0) - err(1, "%s", test_id); - - success(); -} - -void -test_kevent_socket_disable_and_enable(void) -{ - const char *test_id = "kevent(EVFILT_READ, EV_DISABLE)"; - struct kevent kev; - - test_begin(test_id); - - /* Add an event, then disable it. */ - EV_SET(&kev, sockfd[0], EVFILT_READ, EV_ADD, 0, 0, &sockfd[0]); - if (kevent(kqfd, &kev, 1, NULL, 0, NULL) < 0) - err(1, "%s", test_id); - EV_SET(&kev, sockfd[0], EVFILT_READ, EV_DISABLE, 0, 0, &sockfd[0]); - if (kevent(kqfd, &kev, 1, NULL, 0, NULL) < 0) - err(1, "%s", test_id); - - kevent_socket_fill(); - test_no_kevents(); - - /* Re-enable the knote, then see if an event is generated */ - kev.flags = EV_ENABLE; - if (kevent(kqfd, &kev, 1, NULL, 0, NULL) < 0) - err(1, "%s", test_id); - kev.flags = EV_ADD; - kev.data = 1; - kevent_cmp(&kev, kevent_get(kqfd)); - - kevent_socket_drain(); - - kev.flags = EV_DELETE; - if (kevent(kqfd, &kev, 1, NULL, 0, NULL) < 0) - err(1, "%s", test_id); - - success(); -} - -void -test_kevent_socket_del(void) -{ - const char *test_id = "kevent(EVFILT_READ, EV_DELETE)"; - struct kevent kev; - - test_begin(test_id); - - EV_SET(&kev, sockfd[0], EVFILT_READ, EV_DELETE, 0, 0, &sockfd[0]); - if (kevent(kqfd, &kev, 1, NULL, 0, NULL) < 0) - err(1, "%s", test_id); - - kevent_socket_fill(); - test_no_kevents(); - kevent_socket_drain(); - - success(); -} - -void -test_kevent_socket_oneshot(void) -{ - const char *test_id = "kevent(EVFILT_READ, EV_ONESHOT)"; - struct kevent kev; - - test_begin(test_id); - - /* Re-add the watch and make sure no events are pending */ - puts("-- re-adding knote"); - EV_SET(&kev, sockfd[0], EVFILT_READ, EV_ADD | EV_ONESHOT, 0, 0, &sockfd[0]); - if (kevent(kqfd, &kev, 1, NULL, 0, NULL) < 0) - err(1, "%s", test_id); - test_no_kevents(); - - puts("-- getting one event"); - kevent_socket_fill(); - kev.data = 1; - kevent_cmp(&kev, kevent_get(kqfd)); - - puts("-- checking knote disabled"); - test_no_kevents(); - - /* Try to delete the knote, it should already be deleted */ - EV_SET(&kev, sockfd[0], EVFILT_READ, EV_DELETE, 0, 0, &sockfd[0]); - if (kevent(kqfd, &kev, 1, NULL, 0, NULL) == 0) - err(1, "%s", test_id); - - kevent_socket_drain(); - - success(); -} - - -#if HAVE_EV_DISPATCH -void -test_kevent_socket_dispatch(void) -{ - const char *test_id = "kevent(EVFILT_READ, EV_DISPATCH)"; - - test_begin(test_id); - - struct kevent kev; - - /* Re-add the watch and make sure no events are pending */ - puts("-- re-adding knote"); - EV_SET(&kev, sockfd[0], EVFILT_READ, EV_ADD | EV_DISPATCH, 0, 0, &sockfd[0]); - if (kevent(kqfd, &kev, 1, NULL, 0, NULL) < 0) - err(1, "%s", test_id); - test_no_kevents(); - - /* The event will occur only once, even though EV_CLEAR is not - specified. */ - kevent_socket_fill(); - kev.data = 1; - kevent_cmp(&kev, kevent_get(kqfd)); - test_no_kevents(); - - /* Since the knote is disabled, the EV_DELETE operation succeeds. */ - EV_SET(&kev, sockfd[0], EVFILT_READ, EV_DELETE, 0, 0, &sockfd[0]); - if (kevent(kqfd, &kev, 1, NULL, 0, NULL) < 0) - err(1, "%s", test_id); - - kevent_socket_drain(); - - success(); -} -#endif /* HAVE_EV_DISPATCH */ - -#if BROKEN -void -test_kevent_socket_lowat(void) -{ - const char *test_id = "kevent(EVFILT_READ, NOTE_LOWAT)"; - struct kevent kev; - - test_begin(test_id); - - /* Re-add the watch and make sure no events are pending */ - puts("-- re-adding knote, setting low watermark to 2 bytes"); - EV_SET(&kev, sockfd[0], EVFILT_READ, EV_ADD | EV_ONESHOT, NOTE_LOWAT, 2, &sockfd[0]); - if (kevent(kqfd, &kev, 1, NULL, 0, NULL) < 0) - err(1, "%s", test_id); - test_no_kevents(); - - puts("-- checking that one byte does not trigger an event.."); - kevent_socket_fill(); - test_no_kevents(); - - puts("-- checking that two bytes triggers an event.."); - kevent_socket_fill(); - if (kevent(kqfd, NULL, 0, &kev, 1, NULL) != 1) - err(1, "%s", test_id); - KEV_CMP(kev, sockfd[0], EVFILT_READ, 0); - test_no_kevents(); - - kevent_socket_drain(); - kevent_socket_drain(); - - success(); -} -#endif - -void -test_kevent_socket_eof(void) -{ - const char *test_id = "kevent(EVFILT_READ, EV_EOF)"; - struct kevent kev; - - test_begin(test_id); - - /* Re-add the watch and make sure no events are pending */ - EV_SET(&kev, sockfd[0], EVFILT_READ, EV_ADD, 0, 0, &sockfd[0]); - if (kevent(kqfd, &kev, 1, NULL, 0, NULL) < 0) - err(1, "%s", test_id); - test_no_kevents(); - - if (close(sockfd[1]) < 0) - err(1, "close(2)"); - - kev.flags |= EV_EOF; - kevent_cmp(&kev, kevent_get(kqfd)); - - /* Delete the watch */ - EV_SET(&kev, sockfd[0], EVFILT_READ, EV_DELETE, 0, 0, &sockfd[0]); - if (kevent(kqfd, &kev, 1, NULL, 0, NULL) < 0) - err(1, "%s", test_id); - - success(); -} - -void -test_evfilt_read() -{ - /* Create a connected pair of full-duplex sockets for testing socket events */ - if (socketpair(AF_UNIX, SOCK_STREAM, 0, sockfd) < 0) - abort(); - - kqfd = kqueue(); - test_kevent_socket_add(); - test_kevent_socket_del(); - test_kevent_socket_get(); - test_kevent_socket_disable_and_enable(); - test_kevent_socket_oneshot(); - test_kevent_socket_clear(); -#if HAVE_EV_DISPATCH - test_kevent_socket_dispatch(); -#endif - test_kevent_socket_eof(); - close(kqfd); -} diff --git a/tests/sys/netpfil/pf/rdr.sh b/tests/sys/netpfil/pf/rdr.sh deleted file mode 100755 index 983abe054a3..00000000000 --- a/tests/sys/netpfil/pf/rdr.sh +++ /dev/null @@ -1,73 +0,0 @@ -# $FreeBSD$ -# -# SPDX-License-Identifier: BSD-2-Clause-FreeBSD -# -# Copyright (c) 2018 Kristof Provost -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# -# THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND -# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -# ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE -# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -# OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -# HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -# OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -# SUCH DAMAGE. - -. $(atf_get_srcdir)/utils.subr - -atf_test_case "basic" "cleanup" -basic_head() -{ - atf_set descr 'Basic rdr test' - atf_set require.user root -} - -basic_body() -{ - pft_init - - epair=$(vnet_mkepair) - - vnet_mkjail alcatraz ${epair}b - - ifconfig ${epair}a 192.0.2.2/24 up - route add -net 198.51.100.0/24 192.0.2.1 - - jexec alcatraz ifconfig ${epair}b 192.0.2.1/24 up - jexec alcatraz sysctl net.inet.ip.forwarding=1 - - # Enable pf! - jexec alcatraz pfctl -e - pft_set_rules alcatraz \ - "rdr pass on ${epair}b proto tcp from any to 198.51.100.0/24 port 1234 -> 192.0.2.1 port 4321" - - echo "foo" | jexec alcatraz nc -N -l 4321 & - sleep 1 - - result=$(nc -N -w 3 198.51.100.2 1234) - if [ "$result" != "foo" ]; then - atf_fail "Redirect failed" - fi -} - -basic_cleanup() -{ - pft_cleanup -} - -atf_init_test_cases() -{ - atf_add_test_case "basic" -} diff --git a/tests/sys/opencrypto/dpkt.py b/tests/sys/opencrypto/dpkt.py deleted file mode 100644 index 09c03be5c29..00000000000 --- a/tests/sys/opencrypto/dpkt.py +++ /dev/null @@ -1,160 +0,0 @@ -# $FreeBSD: stable/11/tests/sys/opencrypto/dpkt.py 275732 2014-12-12 19:56:36Z jmg $ -# $Id: dpkt.py 114 2005-09-11 15:15:12Z dugsong $ - -"""fast, simple packet creation / parsing, with definitions for the -basic TCP/IP protocols. -""" - -__author__ = 'Dug Song ' -__copyright__ = 'Copyright (c) 2004 Dug Song' -__license__ = 'BSD' -__url__ = 'http://monkey.org/~dugsong/dpkt/' -__version__ = '1.2' - -try: - from itertools import izip as _it_izip -except ImportError: - _it_izip = zip - -from struct import calcsize as _st_calcsize, \ - pack as _st_pack, unpack as _st_unpack, error as _st_error -from re import compile as _re_compile - -intchr = _re_compile(r"(?P[0-9]+)(?P.)") - -class MetaPacket(type): - def __new__(cls, clsname, clsbases, clsdict): - if '__hdr__' in clsdict: - st = clsdict['__hdr__'] - clsdict['__hdr_fields__'] = [ x[0] for x in st ] - clsdict['__hdr_fmt__'] = clsdict.get('__byte_order__', '>') + \ - ''.join([ x[1] for x in st ]) - clsdict['__hdr_len__'] = _st_calcsize(clsdict['__hdr_fmt__']) - clsdict['__hdr_defaults__'] = \ - dict(zip(clsdict['__hdr_fields__'], [ x[2] for x in st ])) - clsdict['__slots__'] = clsdict['__hdr_fields__'] - return type.__new__(cls, clsname, clsbases, clsdict) - -class Packet(object): - """Packet class - - __hdr__ should be defined as a list of (name, structfmt, default) tuples - __byte_order__ can be set to override the default ('>') - """ - __metaclass__ = MetaPacket - data = '' - - def __init__(self, *args, **kwargs): - """Packet constructor with ([buf], [field=val,...]) prototype. - - Arguments: - - buf -- packet buffer to unpack - - Optional keyword arguments correspond to packet field names. - """ - if args: - self.unpack(args[0]) - else: - for k in self.__hdr_fields__: - setattr(self, k, self.__hdr_defaults__[k]) - for k, v in kwargs.iteritems(): - setattr(self, k, v) - - def __len__(self): - return self.__hdr_len__ + len(self.data) - - def __repr__(self): - l = [ '%s=%r' % (k, getattr(self, k)) - for k in self.__hdr_defaults__ - if getattr(self, k) != self.__hdr_defaults__[k] ] - if self.data: - l.append('data=%r' % self.data) - return '%s(%s)' % (self.__class__.__name__, ', '.join(l)) - - def __str__(self): - return self.pack_hdr() + str(self.data) - - def pack_hdr(self): - """Return packed header string.""" - try: - return _st_pack(self.__hdr_fmt__, - *[ getattr(self, k) for k in self.__hdr_fields__ ]) - except _st_error: - vals = [] - for k in self.__hdr_fields__: - v = getattr(self, k) - if isinstance(v, tuple): - vals.extend(v) - else: - vals.append(v) - return _st_pack(self.__hdr_fmt__, *vals) - - def unpack(self, buf): - """Unpack packet header fields from buf, and set self.data.""" - - res = list(_st_unpack(self.__hdr_fmt__, buf[:self.__hdr_len__])) - for e, k in enumerate(self.__slots__): - sfmt = self.__hdr__[e][1] - mat = intchr.match(sfmt) - if mat and mat.group('chr') != 's': - cnt = int(mat.group('int')) - setattr(self, k, list(res[:cnt])) - del res[:cnt] - else: - if sfmt[-1] == 's': - i = res[0].find('\x00') - if i != -1: - res[0] = res[0][:i] - setattr(self, k, res[0]) - del res[0] - assert len(res) == 0 - self.data = buf[self.__hdr_len__:] - -# XXX - ''.join([(len(`chr(x)`)==3) and chr(x) or '.' for x in range(256)]) -__vis_filter = """................................ !"#$%&\'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[.]^_`abcdefghijklmnopqrstuvwxyz{|}~.................................................................................................................................""" - -def hexdump(buf, length=16): - """Return a hexdump output string of the given buffer.""" - n = 0 - res = [] - while buf: - line, buf = buf[:length], buf[length:] - hexa = ' '.join(['%02x' % ord(x) for x in line]) - line = line.translate(__vis_filter) - res.append(' %04d: %-*s %s' % (n, length * 3, hexa, line)) - n += length - return '\n'.join(res) - -def in_cksum_add(s, buf): - """in_cksum_add(cksum, buf) -> cksum - - Return accumulated Internet checksum. - """ - nleft = len(buf) - i = 0 - while nleft > 1: - s += ord(buf[i]) * 256 + ord(buf[i+1]) - i += 2 - nleft -= 2 - if nleft: - s += ord(buf[i]) * 256 - return s - -def in_cksum_done(s): - """Fold and return Internet checksum.""" - while (s >> 16): - s = (s >> 16) + (s & 0xffff) - return (~s & 0xffff) - -def in_cksum(buf): - """Return computed Internet checksum.""" - return in_cksum_done(in_cksum_add(0, buf)) - -try: - import psyco - psyco.bind(in_cksum) - psyco.bind(Packet) -except ImportError: - pass - diff --git a/tools/debugscripts/kgdb b/tools/debugscripts/kgdb deleted file mode 100644 index 6ac16adb985..00000000000 --- a/tools/debugscripts/kgdb +++ /dev/null @@ -1,66 +0,0 @@ -#!/bin/sh - -# -# Copyright 2004 John-Mark Gurney -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# -# THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND -# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -# ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE -# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -# OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -# HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -# OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -# SUCH DAMAGE. -# - -crashpath="/var/crash" -kld_debpy="kld_deb.py" - -if [ x"$1" = x"-?" -o x"$1" = x"-h" ]; then - echo "Usage: $0 [ [ ] ]" - echo "" - echo "Path for crash dumps: $crashpath" - exit 1 -fi - -if [ x"$1" = x"" ]; then - echo "Need core number." - exit 1 -fi -corenum="$1" -shift - -cmd_file="" -if [ x"$2" != x"" ]; then - cmd_file="-x $2" - shift -fi - -core="$crashpath/vmcore.$corenum" -info="$crashpath/info.$corenum" - -#Get the kernel source compile dir from the info file -kernsrc="`awk 'i == 1 { split($0, a, ":"); print a[2]; i = 0 } $1 == "Versionstring:" { i = 1 }' < "$info"`" - -tmpfile="/tmp/kgdb.asf.$$" -# -mapped (broken?) -# -x command_file -echo "Kernel Source: $kernsrc" -echo "Getting KLD information and locations..." -python $kld_debpy "$kernsrc" "$core" $@ > "$tmpfile" && -echo "Please run the following command to load module symbols:" -echo "source $tmpfile" -(cd "$kernsrc"; kgdb "$kernsrc/kernel.debug" "$core") -rm "$tmpfile" diff --git a/tools/debugscripts/kld_deb.py b/tools/debugscripts/kld_deb.py deleted file mode 100644 index ac5629757b0..00000000000 --- a/tools/debugscripts/kld_deb.py +++ /dev/null @@ -1,142 +0,0 @@ -#!/usr/local/bin/python -# -# Copyright 2004 John-Mark Gurney -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# -# THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND -# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -# ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE -# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -# OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -# HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -# OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -# SUCH DAMAGE. -# - -from __future__ import print_function -import sys -import os -import popen2 -import re - -gdb_cmd = 'kgdb %(p)s/kernel.debug %(core)s | tee /tmp/gdb.log' -#GDB regex -filenamere = re.compile(r'filename\s+=\s+0x[0-9a-f]+\s("(?P[^"]+)"|(?P<[^>]*>))', re.M) -addressre = re.compile(r'address\s+=\s+(?P0x[0-9a-f]+)', re.M) -nextre = re.compile(r'tqe_next\s+=\s+(?P0x[0-9a-f]+)', re.M) -printre = re.compile(r'\$\d+\s+=\s+') - -#Paths to search for ko's/debugs -kld_debug_paths = [] - -if len(sys.argv[1:]) < 2: - print('Usage: prog []') - sys.exit(1) - -#Get the base modules path -pfs = sys.argv[1].split('/') -try: - i = 0 - while 1: - i = i + pfs[i:].index('sys') + 1 -except: - pass - -if i == -1: - sys.stderr.write("No sys dir in kernel source path: %s\n" % sys.argv[1]) - sys.exit(0) - -kld_debug_paths.append('/'.join(pfs[:i] + ['modules'])) -kld_debug_paths.append(sys.argv[1]) -#kld_debug_paths.append(sys.argv[3:]) -gdb_cmd = gdb_cmd % {'p': sys.argv[1], 'core': sys.argv[2] } - -#Start gdb -gdb = popen2.popen4(gdb_cmd) - -def searchfor(inp, re, j = 0, l = None): - """searchfor(inp, re, j, l): Searches for regex re in inp. It will -automatically add more lines. If j is set, the lines will be joined together. -l can provide a starting line to help search against. Return value is a -tuple of the last line, and the match if any.""" - ret = None - if not l: - l = inp.readline() - ret = re.search(l) - while l and not ret: - if j: - l += inp.readline() - else: - l = inp.readline() - ret = re.search(l) - - return (l, ret) - -def get_addresses(inp, out): - """get_addresses(inp, out): It will search for addresses from gdb. -inp and out, are the gdb input and output respectively. Return value is -a list of tuples. The tuples contain the filename and the address the -filename was loaded.""" - addr = [] - nxad = 1 - while nxad: - if nxad == 1: - out.write("print linker_files.tqh_first[0]\n") - else: - out.write("print *(struct linker_file *)%d\n" % nxad) - out.flush() - l = searchfor(inp, printre)[0] - l, fn = searchfor(inp, filenamere, 1, l) - if not fn.group('fn'): - sys.stderr.write("got error: %s\n" % fn.group('error')) - nxad = 0 - else: - l, ad = searchfor(inp, addressre, 1, l) - l, nx = searchfor(inp, nextre, 1, l) - addr.append((fn.group('fn'), long(ad.group('ad'), 16))) - nxad = long(nx.group('ad'), 16) - - return addr - -#Get the addresses -addr = get_addresses(gdb[0], gdb[1]) - -#Pass through the resulting addresses, skipping the kernel. -for i in addr[1:]: - for j in kld_debug_paths: - #Try .debug first. - p = popen2.popen4('find %s -type f -name "%s.debug"' % (j, i[0]))[0].read().strip() - if p: - break - #Try just .ko if .debug wasn't found. - p = popen2.popen4('find %s -type f -name "%s"' % (j, i[0]))[0].read().strip() - if p: - break - - if not p: - #Tell our user that we couldn't find it. - a = i[1] - sys.stderr.write("Can't find module: %s (addr: %d + header)\n" % (i[0], a)) - print('#add-symbol-file ', a, '#add header') - continue - - #j = popen2.popen4('objdump --section-headers /boot/kernel/%s | grep "\.text"' % i[0])[0].read().strip().split() - #Output the necessary information - j = popen2.popen4('objdump --section-headers "%s" | grep "\.text"' % p)[0].read().strip().split() - try: - a = int(j[5], 16) - print('add-symbol-file', p, i[1] + a) - except IndexError: - sys.stderr.write('Bad file: %s, address: %d\n' % (i[0], i[1]))